STM32WB55xx HAL User Manual: STM32WBxx HAL Drivers

STM32WB55xx HAL User Manual
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STM32WBxx HAL Drivers

HAL Drivers User Manual

This document contains the User Manual (UM) of the STM32WB55xx HAL (Hardware Abstraction Layer) drivers.

Document tabsheets description:

  • "Modules" : List the different modules.
  • "Files" : List all the files and globals.
  • "Directories" : Firmware Directory hierarchy.
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC

  • Data Structures
  • Files
  • Directories
Modules
ADC
STM32WBxx_LL_Driver

Modules

ADC Private Constants
ADC Private Macros
ADC Exported Init structure
ADC Exported Constants
ADC Exported Macros
ADC Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for ADC registers.

Register | Bit | Function
AWD2CR | AWD2CH | LL_ADC_GetAnalogWDMonitChannels
 |  | LL_ADC_SetAnalogWDMonitChannels
AWD3CR | AWD3CH | LL_ADC_GetAnalogWDMonitChannels
 |  | LL_ADC_SetAnalogWDMonitChannels
CALFACT | CALFACT_D | LL_ADC_GetCalibrationFactor
 |  | LL_ADC_SetCalibrationFactor
 | CALFACT_S | LL_ADC_GetCalibrationFactor
 |  | LL_ADC_SetCalibrationFactor
CCR | CKMODE | LL_ADC_GetCommonClock
 |  | LL_ADC_SetCommonClock
 | PRESC | LL_ADC_GetCommonClock
 |  | LL_ADC_SetCommonClock
 | TSEN | LL_ADC_GetCommonPathInternalCh
 |  | LL_ADC_SetCommonPathInternalCh
 | VBATEN | LL_ADC_GetCommonPathInternalCh
 |  | LL_ADC_SetCommonPathInternalCh
 | VREFEN | LL_ADC_GetCommonPathInternalCh
 |  | LL_ADC_SetCommonPathInternalCh
CFGR | ALIGN | LL_ADC_GetDataAlignment
 |  | LL_ADC_SetDataAlignment
 | AUTDLY | LL_ADC_GetLowPowerMode
 |  | LL_ADC_SetLowPowerMode
 | AWD1CH | LL_ADC_GetAnalogWDMonitChannels
 |  | LL_ADC_SetAnalogWDMonitChannels
 | AWD1EN | LL_ADC_GetAnalogWDMonitChannels
 |  | LL_ADC_SetAnalogWDMonitChannels
 | AWD1SGL | LL_ADC_GetAnalogWDMonitChannels
 |  | LL_ADC_SetAnalogWDMonitChannels
 | CONT | LL_ADC_REG_GetContinuousMode
 |  | LL_ADC_REG_SetContinuousMode
 | DISCEN | LL_ADC_REG_GetSequencerDiscont
 |  | LL_ADC_REG_SetSequencerDiscont
 | DISCNUM | LL_ADC_REG_GetSequencerDiscont
 |  | LL_ADC_REG_SetSequencerDiscont
 | DMACFG | LL_ADC_REG_GetDMATransfer
 |  | LL_ADC_REG_SetDMATransfer
 | DMAEN | LL_ADC_REG_GetDMATransfer
 |  | LL_ADC_REG_SetDMATransfer
 | EXTEN | LL_ADC_REG_GetTriggerEdge
 |  | LL_ADC_REG_GetTriggerSource
 |  | LL_ADC_REG_IsTriggerSourceSWStart
 |  | LL_ADC_REG_SetTriggerEdge
 |  | LL_ADC_REG_SetTriggerSource
 | EXTSEL | LL_ADC_REG_GetTriggerSource
 |  | LL_ADC_REG_SetTriggerSource
 | JAUTO | LL_ADC_INJ_GetTrigAuto
 |  | LL_ADC_INJ_SetTrigAuto
 | JAWD1EN | LL_ADC_GetAnalogWDMonitChannels
 |  | LL_ADC_SetAnalogWDMonitChannels
 | JDISCEN | LL_ADC_INJ_GetSequencerDiscont
 |  | LL_ADC_INJ_SetSequencerDiscont
 | JQDIS | LL_ADC_INJ_GetQueueMode
 |  | LL_ADC_INJ_SetQueueMode
 | JQM | LL_ADC_INJ_GetQueueMode
 |  | LL_ADC_INJ_SetQueueMode
 | OVRMOD | LL_ADC_REG_GetOverrun
 |  | LL_ADC_REG_SetOverrun
 | RES | LL_ADC_GetResolution
 |  | LL_ADC_SetResolution
CFGR2 | JOVSE | LL_ADC_GetOverSamplingScope
 |  | LL_ADC_SetOverSamplingScope
 | OVSR | LL_ADC_ConfigOverSamplingRatioShift
 |  | LL_ADC_GetOverSamplingRatio
 | OVSS | LL_ADC_ConfigOverSamplingRatioShift
 |  | LL_ADC_GetOverSamplingShift
 | ROVSE | LL_ADC_GetOverSamplingScope
 |  | LL_ADC_SetOverSamplingScope
 | ROVSM | LL_ADC_GetOverSamplingScope
 |  | LL_ADC_SetOverSamplingScope
 | TROVS | LL_ADC_GetOverSamplingDiscont
 |  | LL_ADC_SetOverSamplingDiscont
CR | ADCAL | LL_ADC_IsCalibrationOnGoing
 |  | LL_ADC_StartCalibration
 | ADCALDIF | LL_ADC_StartCalibration
 | ADDIS | LL_ADC_Disable
 |  | LL_ADC_IsDisableOngoing
 | ADEN | LL_ADC_Enable
 |  | LL_ADC_IsEnabled
 | ADSTART | LL_ADC_REG_IsConversionOngoing
 |  | LL_ADC_REG_StartConversion
 | ADSTP | LL_ADC_REG_IsStopConversionOngoing
 |  | LL_ADC_REG_StopConversion
 | ADVREGEN | LL_ADC_DisableInternalRegulator
 |  | LL_ADC_EnableInternalRegulator
 |  | LL_ADC_IsInternalRegulatorEnabled
 | DEEPPWD | LL_ADC_DisableDeepPowerDown
 |  | LL_ADC_EnableDeepPowerDown
 |  | LL_ADC_IsDeepPowerDownEnabled
 | JADSTART | LL_ADC_INJ_IsConversionOngoing
 |  | LL_ADC_INJ_StartConversion
 | JADSTP | LL_ADC_INJ_IsStopConversionOngoing
 |  | LL_ADC_INJ_StopConversion
DIFSEL | DIFSEL | LL_ADC_GetChannelSingleDiff
 |  | LL_ADC_SetChannelSingleDiff
DR | DATA | LL_ADC_DMA_GetRegAddr
 | RDATA | LL_ADC_REG_ReadConversionData10
 |  | LL_ADC_REG_ReadConversionData12
 |  | LL_ADC_REG_ReadConversionData32
 |  | LL_ADC_REG_ReadConversionData6
 |  | LL_ADC_REG_ReadConversionData8
IER | ADRDYIE | LL_ADC_DisableIT_ADRDY
 |  | LL_ADC_EnableIT_ADRDY
 |  | LL_ADC_IsEnabledIT_ADRDY
 | AWD1IE | LL_ADC_DisableIT_AWD1
 |  | LL_ADC_EnableIT_AWD1
 |  | LL_ADC_IsEnabledIT_AWD1
 | AWD2IE | LL_ADC_DisableIT_AWD2
 |  | LL_ADC_EnableIT_AWD2
 |  | LL_ADC_IsEnabledIT_AWD2
 | AWD3IE | LL_ADC_DisableIT_AWD3
 |  | LL_ADC_EnableIT_AWD3
 |  | LL_ADC_IsEnabledIT_AWD3
 | EOCIE | LL_ADC_DisableIT_EOC
 |  | LL_ADC_EnableIT_EOC
 |  | LL_ADC_IsEnabledIT_EOC
 | EOSIE | LL_ADC_DisableIT_EOS
 |  | LL_ADC_EnableIT_EOS
 |  | LL_ADC_IsEnabledIT_EOS
 | EOSMPIE | LL_ADC_DisableIT_EOSMP
 |  | LL_ADC_EnableIT_EOSMP
 |  | LL_ADC_IsEnabledIT_EOSMP
 | JEOCIE | LL_ADC_DisableIT_JEOC
 |  | LL_ADC_EnableIT_JEOC
 |  | LL_ADC_IsEnabledIT_JEOC
 | JEOSIE | LL_ADC_DisableIT_JEOS
 |  | LL_ADC_EnableIT_JEOS
 |  | LL_ADC_IsEnabledIT_JEOS
 | JQOVFIE | LL_ADC_DisableIT_JQOVF
 |  | LL_ADC_EnableIT_JQOVF
 |  | LL_ADC_IsEnabledIT_JQOVF
 | OVRIE | LL_ADC_DisableIT_OVR
 |  | LL_ADC_EnableIT_OVR
 |  | LL_ADC_IsEnabledIT_OVR
ISR | ADRDY | LL_ADC_ClearFlag_ADRDY
 |  | LL_ADC_IsActiveFlag_ADRDY
 | AWD1 | LL_ADC_ClearFlag_AWD1
 |  | LL_ADC_IsActiveFlag_AWD1
 | AWD2 | LL_ADC_ClearFlag_AWD2
 |  | LL_ADC_IsActiveFlag_AWD2
 | AWD3 | LL_ADC_ClearFlag_AWD3
 |  | LL_ADC_IsActiveFlag_AWD3
 | EOC | LL_ADC_ClearFlag_EOC
 |  | LL_ADC_IsActiveFlag_EOC
 | EOS | LL_ADC_ClearFlag_EOS
 |  | LL_ADC_IsActiveFlag_EOS
 | EOSMP | LL_ADC_ClearFlag_EOSMP
 |  | LL_ADC_IsActiveFlag_EOSMP
 | JEOC | LL_ADC_ClearFlag_JEOC
 |  | LL_ADC_IsActiveFlag_JEOC
 | JEOS | LL_ADC_ClearFlag_JEOS
 |  | LL_ADC_IsActiveFlag_JEOS
 | JQOVF | LL_ADC_ClearFlag_JQOVF
 |  | LL_ADC_IsActiveFlag_JQOVF
 | OVR | LL_ADC_ClearFlag_OVR
 |  | LL_ADC_IsActiveFlag_OVR
JDR1 | JDATA | LL_ADC_INJ_ReadConversionData10
 |  | LL_ADC_INJ_ReadConversionData12
 |  | LL_ADC_INJ_ReadConversionData32
 |  | LL_ADC_INJ_ReadConversionData6
 |  | LL_ADC_INJ_ReadConversionData8
JDR2 | JDATA | LL_ADC_INJ_ReadConversionData10
 |  | LL_ADC_INJ_ReadConversionData12
 |  | LL_ADC_INJ_ReadConversionData32
 |  | LL_ADC_INJ_ReadConversionData6
 |  | LL_ADC_INJ_ReadConversionData8
JDR3 | JDATA | LL_ADC_INJ_ReadConversionData10
 |  | LL_ADC_INJ_ReadConversionData12
 |  | LL_ADC_INJ_ReadConversionData32
 |  | LL_ADC_INJ_ReadConversionData6
 |  | LL_ADC_INJ_ReadConversionData8
JDR4 | JDATA | LL_ADC_INJ_ReadConversionData10
 |  | LL_ADC_INJ_ReadConversionData12
 |  | LL_ADC_INJ_ReadConversionData32
 |  | LL_ADC_INJ_ReadConversionData6
 |  | LL_ADC_INJ_ReadConversionData8
JSQR | JEXTEN | LL_ADC_INJ_ConfigQueueContext
 |  | LL_ADC_INJ_GetTriggerEdge
 |  | LL_ADC_INJ_GetTriggerSource
 |  | LL_ADC_INJ_IsTriggerSourceSWStart
 |  | LL_ADC_INJ_SetTriggerEdge
 |  | LL_ADC_INJ_SetTriggerSource
 | JEXTSEL | LL_ADC_INJ_ConfigQueueContext
 |  | LL_ADC_INJ_GetTriggerSource
 |  | LL_ADC_INJ_SetTriggerSource
 | JL | LL_ADC_INJ_ConfigQueueContext
 |  | LL_ADC_INJ_GetSequencerLength
 |  | LL_ADC_INJ_SetSequencerLength
 | JSQ1 | LL_ADC_INJ_ConfigQueueContext
 |  | LL_ADC_INJ_GetSequencerRanks
 |  | LL_ADC_INJ_SetSequencerRanks
 | JSQ2 | LL_ADC_INJ_ConfigQueueContext
 |  | LL_ADC_INJ_GetSequencerRanks
 |  | LL_ADC_INJ_SetSequencerRanks
 | JSQ3 | LL_ADC_INJ_ConfigQueueContext
 |  | LL_ADC_INJ_GetSequencerRanks
 |  | LL_ADC_INJ_SetSequencerRanks
 | JSQ4 | LL_ADC_INJ_ConfigQueueContext
 |  | LL_ADC_INJ_GetSequencerRanks
 |  | LL_ADC_INJ_SetSequencerRanks
OFR1 | OFFSET1 | LL_ADC_GetOffsetLevel
 |  | LL_ADC_SetOffset
 | OFFSET1_CH | LL_ADC_GetOffsetChannel
 |  | LL_ADC_SetOffset
 | OFFSET1_EN | LL_ADC_GetOffsetState
 |  | LL_ADC_SetOffset
 |  | LL_ADC_SetOffsetState
OFR2 | OFFSET2 | LL_ADC_GetOffsetLevel
 |  | LL_ADC_SetOffset
 | OFFSET2_CH | LL_ADC_GetOffsetChannel
 |  | LL_ADC_SetOffset
 | OFFSET2_EN | LL_ADC_GetOffsetState
 |  | LL_ADC_SetOffset
 |  | LL_ADC_SetOffsetState
OFR3 | OFFSET3 | LL_ADC_GetOffsetLevel
 |  | LL_ADC_SetOffset
 | OFFSET3_CH | LL_ADC_GetOffsetChannel
 |  | LL_ADC_SetOffset
 | OFFSET3_EN | LL_ADC_GetOffsetState
 |  | LL_ADC_SetOffset
 |  | LL_ADC_SetOffsetState
OFR4 | OFFSET4 | LL_ADC_GetOffsetLevel
 |  | LL_ADC_SetOffset
 | OFFSET4_CH | LL_ADC_GetOffsetChannel
 |  | LL_ADC_SetOffset
 | OFFSET4_EN | LL_ADC_GetOffsetState
 |  | LL_ADC_SetOffset
 |  | LL_ADC_SetOffsetState
SMPR1 | SMP0 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP1 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP2 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP3 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP4 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP5 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP6 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP7 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP8 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP9 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
SMPR2 | SMP10 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP11 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP12 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP13 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP14 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP15 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP16 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP17 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP18 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
SQR1 | L | LL_ADC_REG_GetSequencerLength
 |  | LL_ADC_REG_SetSequencerLength
 | SQ1 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ2 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ3 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ4 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
SQR2 | SQ5 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ6 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ7 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ8 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ9 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
SQR3 | SQ10 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ11 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ12 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ13 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ14 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
SQR4 | SQ15 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ16 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
TR1 | HT1 | LL_ADC_ConfigAnalogWDThresholds
 |  | LL_ADC_GetAnalogWDThresholds
 |  | LL_ADC_SetAnalogWDThresholds
 | LT1 | LL_ADC_ConfigAnalogWDThresholds
 |  | LL_ADC_GetAnalogWDThresholds
 |  | LL_ADC_SetAnalogWDThresholds
TR2 | HT2 | LL_ADC_ConfigAnalogWDThresholds
 |  | LL_ADC_GetAnalogWDThresholds
 |  | LL_ADC_SetAnalogWDThresholds
 | LT2 | LL_ADC_ConfigAnalogWDThresholds
 |  | LL_ADC_GetAnalogWDThresholds
 |  | LL_ADC_SetAnalogWDThresholds
TR3 | HT3 | LL_ADC_ConfigAnalogWDThresholds
 |  | LL_ADC_GetAnalogWDThresholds
 |  | LL_ADC_SetAnalogWDThresholds
 | LT3 | LL_ADC_ConfigAnalogWDThresholds
 |  | LL_ADC_GetAnalogWDThresholds
 |  | LL_ADC_SetAnalogWDThresholds
Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC Private Constants

Defines
ADC Private Constants
ADC

Defines

#define | ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 16UL * 4UL)
#define | ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
#define | ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
#define | ADC_SQR1_REGOFFSET (0x00000000UL)
#define | ADC_SQR2_REGOFFSET (0x00000100UL)
#define | ADC_SQR3_REGOFFSET (0x00000200UL)
#define | ADC_SQR4_REGOFFSET (0x00000300UL)
#define | ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
#define | ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */
#define | ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
#define | ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR1_SQ1" position in register */
#define | ADC_REG_RANK_2_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR1_SQ2" position in register */
#define | ADC_REG_RANK_3_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR1_SQ3" position in register */
#define | ADC_REG_RANK_4_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR1_SQ4" position in register */
#define | ADC_REG_RANK_5_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR2_SQ5" position in register */
#define | ADC_REG_RANK_6_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR2_SQ6" position in register */
#define | ADC_REG_RANK_7_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR2_SQ7" position in register */
#define | ADC_REG_RANK_8_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR2_SQ8" position in register */
#define | ADC_REG_RANK_9_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR2_SQ9" position in register */
#define | ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR3_SQ10" position in register */
#define | ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR3_SQ11" position in register */
#define | ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR3_SQ12" position in register */
#define | ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR3_SQ13" position in register */
#define | ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR3_SQ14" position in register */
#define | ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR4_SQ15" position in register */
#define | ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR4_SQ16" position in register */
#define | ADC_JDR1_REGOFFSET (0x00000000UL)
#define | ADC_JDR2_REGOFFSET (0x00000100UL)
#define | ADC_JDR3_REGOFFSET (0x00000200UL)
#define | ADC_JDR4_REGOFFSET (0x00000300UL)
#define | ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
#define | ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
#define | ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */
#define | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ( 8UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ1" position in register */
#define | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (14UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ2" position in register */
#define | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ3" position in register */
#define | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (26UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ4" position in register */
#define | ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
#define | ADC_REG_TRIG_SOURCE_MASK
#define | ADC_REG_TRIG_EDGE_MASK
#define | ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_CFGR_EXTSEL" position in register */
#define | ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Value equivalent to bitfield "ADC_CFGR_EXTEN" position in register */
#define | ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
#define | ADC_INJ_TRIG_SOURCE_MASK
#define | ADC_INJ_TRIG_EDGE_MASK
#define | ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ( 2UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTSEL" position in register */
#define | ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTEN" position in register */
#define | ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
#define | ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
#define | ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */
#define | ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
#define | ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
#define | ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
#define | ADC_CHANNEL_ID_INTERNAL_CH_2 (0x00080000UL) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
#define | ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
#define | ADC_SMPR1_REGOFFSET (0x00000000UL)
#define | ADC_SMPR2_REGOFFSET (0x02000000UL)
#define | ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
#define | ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
#define | ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL)
#define | ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */
#define | ADC_CHANNEL_0_NUMBER (0x00000000UL)
#define | ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 )
#define | ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_4_NUMBER ( ADC_CFGR_AWD1CH_2 )
#define | ADC_CHANNEL_5_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_6_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
#define | ADC_CHANNEL_7_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_8_NUMBER ( ADC_CFGR_AWD1CH_3 )
#define | ADC_CHANNEL_9_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_10_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 )
#define | ADC_CHANNEL_11_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_12_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 )
#define | ADC_CHANNEL_13_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_14_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
#define | ADC_CHANNEL_15_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4 )
#define | ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 )
#define | ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
#define | ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
#define | ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
#define | ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
#define | ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
#define | ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
#define | ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
#define | ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
#define | ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
#define | ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
#define | ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
#define | ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
#define | ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
#define | ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
#define | ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
#define | ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
#define | ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
#define | ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
#define | ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
#define | ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP0" position in register */
#define | ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP1" position in register */
#define | ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP2" position in register */
#define | ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP3" position in register */
#define | ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP4" position in register */
#define | ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP5" position in register */
#define | ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP6" position in register */
#define | ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP7" position in register */
#define | ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP8" position in register */
#define | ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP9" position in register */
#define | ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP10" position in register */
#define | ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP11" position in register */
#define | ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP12" position in register */
#define | ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP13" position in register */
#define | ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP14" position in register */
#define | ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP15" position in register */
#define | ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP16" position in register */
#define | ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP17" position in register */
#define | ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP18" position in register */
#define | ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)
#define | ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
#define | ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
#define | ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen to perform of shift when single mode is selected, shift value out of channels bits range. */
#define | ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode: mask of bit */
#define | ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode: position of bit */
#define | ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a shift of 4 ranks */
#define | ADC_AWD_CR1_REGOFFSET (0x00000000UL)
#define | ADC_AWD_CR2_REGOFFSET (0x00100000UL)
#define | ADC_AWD_CR3_REGOFFSET (0x00200000UL)
#define | ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
#define | ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
#define | ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
#define | ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
#define | ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
#define | ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */
#define | ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
#define | ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
#define | ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
#define | ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
#define | ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */
#define | ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate threshold high: mask of bit */
#define | ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate threshold high: position of bit */
#define | ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */
#define | ADC_OFR1_REGOFFSET (0x00000000UL)
#define | ADC_OFR2_REGOFFSET (0x00000001UL)
#define | ADC_OFR3_REGOFFSET (0x00000002UL)
#define | ADC_OFR4_REGOFFSET (0x00000003UL)
#define | ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
#define | ADC_CFGR_RES_BITOFFSET_POS ( 3UL) /* Value equivalent to bitfield "ADC_CFGR_RES" position in register */
#define | ADC_CFGR_AWD1SGL_BITOFFSET_POS (22UL) /* Value equivalent to bitfield "ADC_CFGR_AWD1SGL" position in register */
#define | ADC_CFGR_AWD1EN_BITOFFSET_POS (23UL) /* Value equivalent to bitfield "ADC_CFGR_AWD1EN" position in register */
#define | ADC_CFGR_JAWD1EN_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_CFGR_JAWD1EN" position in register */
#define | ADC_TR1_HT1_BITOFFSET_POS (16UL) /* Value equivalent to bitfield "ADC_TR1_HT1" position in register */
#define | ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
#define | VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, address of parameter VREFINT: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.6 V (tolerance: +-10 mV). */
#define | VREFINT_CAL_VREF (3600UL) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
#define | TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32WB, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
#define | TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75CAUL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32WB, temperature sensor ADC raw data acquired at temperature 130 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
#define | TEMPSENSOR_CAL1_TEMP (30L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define | TEMPSENSOR_CAL2_TEMP (130L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define | TEMPSENSOR_CAL_VREFANALOG (3000UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */

Define Documentation

#define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)

Definition at line 297 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels(), and LL_ADC_SetAnalogWDMonitChannels().

#define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)

Definition at line 298 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels(), and LL_ADC_SetAnalogWDMonitChannels().

#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

Definition at line 302 of file stm32wbxx_ll_adc.h.

#define ADC_AWD_CR1_REGOFFSET (0x00000000UL)

Definition at line 291 of file stm32wbxx_ll_adc.h.

#define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)

Definition at line 303 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels().

#define ADC_AWD_CR2_REGOFFSET (0x00100000UL)

Definition at line 292 of file stm32wbxx_ll_adc.h.

#define ADC_AWD_CR3_REGOFFSET (0x00200000UL)

Definition at line 293 of file stm32wbxx_ll_adc.h.

#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)

Definition at line 304 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels(), and LL_ADC_SetAnalogWDMonitChannels().

#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)

Definition at line 300 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels(), and LL_ADC_SetAnalogWDMonitChannels().

#define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */

Definition at line 306 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels(), and LL_ADC_SetAnalogWDMonitChannels().

#define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)

Definition at line 309 of file stm32wbxx_ll_adc.h.

#define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)

Definition at line 310 of file stm32wbxx_ll_adc.h.

#define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)

Definition at line 311 of file stm32wbxx_ll_adc.h.

#define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate threshold high: mask of bit */

Definition at line 314 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDThresholds(), and LL_ADC_SetAnalogWDThresholds().

#define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate threshold high: position of bit */

Definition at line 315 of file stm32wbxx_ll_adc.h.

#define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */

Definition at line 316 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDThresholds(), and LL_ADC_SetAnalogWDThresholds().

#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)

Definition at line 312 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_ConfigAnalogWDThresholds(), LL_ADC_GetAnalogWDThresholds(), and LL_ADC_SetAnalogWDThresholds().

#define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */

Definition at line 313 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_ConfigAnalogWDThresholds(), LL_ADC_GetAnalogWDThresholds(), and LL_ADC_SetAnalogWDThresholds().

#define ADC_CFGR_AWD1EN_BITOFFSET_POS (23UL) /* Value equivalent to bitfield "ADC_CFGR_AWD1EN" position in register */

Definition at line 330 of file stm32wbxx_ll_adc.h.

#define ADC_CFGR_AWD1SGL_BITOFFSET_POS (22UL) /* Value equivalent to bitfield "ADC_CFGR_AWD1SGL" position in register */

Definition at line 329 of file stm32wbxx_ll_adc.h.

#define ADC_CFGR_JAWD1EN_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_CFGR_JAWD1EN" position in register */

Definition at line 331 of file stm32wbxx_ll_adc.h.

#define ADC_CFGR_RES_BITOFFSET_POS ( 3UL) /* Value equivalent to bitfield "ADC_CFGR_RES" position in register */

Definition at line 328 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)

Definition at line 224 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_0_NUMBER (0x00000000UL)

Definition at line 202 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP0" position in register */

Definition at line 246 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)

Definition at line 234 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_10_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 )

Definition at line 212 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP10" position in register */

Definition at line 256 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)

Definition at line 235 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_11_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

Definition at line 213 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP11" position in register */

Definition at line 257 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)

Definition at line 236 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_12_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 )

Definition at line 214 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP12" position in register */

Definition at line 258 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)

Definition at line 237 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_13_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)

Definition at line 215 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP13" position in register */

Definition at line 259 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)

Definition at line 238 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_14_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )

Definition at line 216 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP14" position in register */

Definition at line 260 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)

Definition at line 239 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_15_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

Definition at line 217 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP15" position in register */

Definition at line 261 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)

Definition at line 240 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4 )

Definition at line 218 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP16" position in register */

Definition at line 262 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)

Definition at line 241 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)

Definition at line 219 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP17" position in register */

Definition at line 263 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)

Definition at line 242 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 )

Definition at line 220 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP18" position in register */

Definition at line 264 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)

Definition at line 225 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0)

Definition at line 203 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP1" position in register */

Definition at line 247 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)

Definition at line 226 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 )

Definition at line 204 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP2" position in register */

Definition at line 248 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)

Definition at line 227 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

Definition at line 205 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP3" position in register */

Definition at line 249 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)

Definition at line 228 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_4_NUMBER ( ADC_CFGR_AWD1CH_2 )

Definition at line 206 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP4" position in register */

Definition at line 250 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)

Definition at line 229 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_5_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)

Definition at line 207 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP5" position in register */

Definition at line 251 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)

Definition at line 230 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_6_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )

Definition at line 208 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP6" position in register */

Definition at line 252 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)

Definition at line 231 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_7_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

Definition at line 209 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP7" position in register */

Definition at line 253 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)

Definition at line 232 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_8_NUMBER ( ADC_CFGR_AWD1CH_3 )

Definition at line 210 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP8" position in register */

Definition at line 254 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)

Definition at line 233 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_9_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)

Definition at line 211 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP9" position in register */

Definition at line 255 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)

Definition at line 179 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */

Definition at line 186 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_ID_INTERNAL_CH_2 (0x00080000UL) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */

Definition at line 187 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)

Definition at line 188 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)

Definition at line 181 of file stm32wbxx_ll_adc.h.

#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */

Definition at line 180 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_INJ_ConfigQueueContext(), LL_ADC_INJ_GetSequencerRanks(), LL_ADC_INJ_SetSequencerRanks(), LL_ADC_REG_GetSequencerRanks(), and LL_ADC_REG_SetSequencerRanks().

#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)

Definition at line 178 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_INJ_ConfigQueueContext(), LL_ADC_INJ_GetSequencerRanks(), LL_ADC_INJ_SetSequencerRanks(), LL_ADC_REG_SetSequencerRanks(), and LL_ADC_SetOffset().

#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */

Definition at line 183 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerRanks(), and LL_ADC_REG_SetSequencerRanks().

#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)

Definition at line 194 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_GetChannelSamplingTime(), and LL_ADC_SetChannelSamplingTime().

#define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL)

Definition at line 197 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_GetChannelSamplingTime(), and LL_ADC_SetChannelSamplingTime().

#define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */

Definition at line 198 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_GetChannelSamplingTime(), and LL_ADC_SetChannelSamplingTime().

#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 16UL * 4UL)

Definition at line 67 of file stm32wbxx_ll_adc.c.

#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */

Definition at line 336 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_Disable(), LL_ADC_DisableDeepPowerDown(), LL_ADC_DisableInternalRegulator(), LL_ADC_Enable(), LL_ADC_EnableDeepPowerDown(), LL_ADC_EnableInternalRegulator(), LL_ADC_INJ_StartConversion(), LL_ADC_INJ_StopConversion(), LL_ADC_REG_StartConversion(), LL_ADC_REG_StopConversion(), and LL_ADC_StartCalibration().

#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)

Definition at line 98 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_INJ_ReadConversionData10(), LL_ADC_INJ_ReadConversionData12(), LL_ADC_INJ_ReadConversionData32(), LL_ADC_INJ_ReadConversionData6(), and LL_ADC_INJ_ReadConversionData8().

#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ( 8UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ1" position in register */

Definition at line 104 of file stm32wbxx_ll_adc.h.

#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (14UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ2" position in register */

Definition at line 105 of file stm32wbxx_ll_adc.h.

#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ3" position in register */

Definition at line 106 of file stm32wbxx_ll_adc.h.

#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (26UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ4" position in register */

Definition at line 107 of file stm32wbxx_ll_adc.h.

#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)

Definition at line 99 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_INJ_ConfigQueueContext(), LL_ADC_INJ_GetSequencerRanks(), and LL_ADC_INJ_SetSequencerRanks().

#define ADC_INJ_TRIG_EDGE_MASK
Value:
(((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \
                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 1UL)) | \
                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 2UL)) | \
                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 3UL))  )

Definition at line 156 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_INJ_GetTriggerSource().

#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */

Definition at line 143 of file stm32wbxx_ll_adc.h.

#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTEN" position in register */

Definition at line 163 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_INJ_GetTriggerSource().

#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ( 2UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTSEL" position in register */

Definition at line 162 of file stm32wbxx_ll_adc.h.

#define ADC_INJ_TRIG_SOURCE_MASK
Value:
(((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL)  << (4U * 0UL)) | \
                                             ((ADC_JSQR_JEXTSEL)                             << (4U * 1UL)) | \
                                             ((ADC_JSQR_JEXTSEL)                             << (4U * 2UL)) | \
                                             ((ADC_JSQR_JEXTSEL)                             << (4U * 3UL))  )

Definition at line 148 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_INJ_GetTriggerSource().

#define ADC_JDR1_REGOFFSET (0x00000000UL)

Definition at line 93 of file stm32wbxx_ll_adc.h.

#define ADC_JDR2_REGOFFSET (0x00000100UL)

Definition at line 94 of file stm32wbxx_ll_adc.h.

#define ADC_JDR3_REGOFFSET (0x00000200UL)

Definition at line 95 of file stm32wbxx_ll_adc.h.

#define ADC_JDR4_REGOFFSET (0x00000300UL)

Definition at line 96 of file stm32wbxx_ll_adc.h.

#define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */

Definition at line 100 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_INJ_ReadConversionData10(), LL_ADC_INJ_ReadConversionData12(), LL_ADC_INJ_ReadConversionData32(), LL_ADC_INJ_ReadConversionData6(), and LL_ADC_INJ_ReadConversionData8().

#define ADC_OFR1_REGOFFSET (0x00000000UL)

Definition at line 320 of file stm32wbxx_ll_adc.h.

#define ADC_OFR2_REGOFFSET (0x00000001UL)

Definition at line 321 of file stm32wbxx_ll_adc.h.

#define ADC_OFR3_REGOFFSET (0x00000002UL)

Definition at line 322 of file stm32wbxx_ll_adc.h.

#define ADC_OFR4_REGOFFSET (0x00000003UL)

Definition at line 323 of file stm32wbxx_ll_adc.h.

#define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)

Definition at line 324 of file stm32wbxx_ll_adc.h.

#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR3_SQ10" position in register */

Definition at line 76 of file stm32wbxx_ll_adc.h.

#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR3_SQ11" position in register */

Definition at line 77 of file stm32wbxx_ll_adc.h.

#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR3_SQ12" position in register */

Definition at line 78 of file stm32wbxx_ll_adc.h.

#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR3_SQ13" position in register */

Definition at line 79 of file stm32wbxx_ll_adc.h.

#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR3_SQ14" position in register */

Definition at line 80 of file stm32wbxx_ll_adc.h.

#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR4_SQ15" position in register */

Definition at line 81 of file stm32wbxx_ll_adc.h.

#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR4_SQ16" position in register */

Definition at line 82 of file stm32wbxx_ll_adc.h.

#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR1_SQ1" position in register */

Definition at line 67 of file stm32wbxx_ll_adc.h.

#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR1_SQ2" position in register */

Definition at line 68 of file stm32wbxx_ll_adc.h.

#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR1_SQ3" position in register */

Definition at line 69 of file stm32wbxx_ll_adc.h.

#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR1_SQ4" position in register */

Definition at line 70 of file stm32wbxx_ll_adc.h.

#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR2_SQ5" position in register */

Definition at line 71 of file stm32wbxx_ll_adc.h.

#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR2_SQ6" position in register */

Definition at line 72 of file stm32wbxx_ll_adc.h.

#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR2_SQ7" position in register */

Definition at line 73 of file stm32wbxx_ll_adc.h.

#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR2_SQ8" position in register */

Definition at line 74 of file stm32wbxx_ll_adc.h.

#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR2_SQ9" position in register */

Definition at line 75 of file stm32wbxx_ll_adc.h.

#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)

Definition at line 63 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerRanks(), and LL_ADC_REG_SetSequencerRanks().

#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)

Definition at line 61 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerRanks(), and LL_ADC_REG_SetSequencerRanks().

#define ADC_REG_TRIG_EDGE_MASK
Value:
(((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \
                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 1UL)) | \
                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 2UL)) | \
                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 3UL))  )

Definition at line 128 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_REG_GetTriggerSource().

#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */

Definition at line 115 of file stm32wbxx_ll_adc.h.

#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Value equivalent to bitfield "ADC_CFGR_EXTEN" position in register */

Definition at line 135 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_REG_GetTriggerSource().

#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_CFGR_EXTSEL" position in register */

Definition at line 134 of file stm32wbxx_ll_adc.h.

#define ADC_REG_TRIG_SOURCE_MASK
Value:
(((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \
                                             ((ADC_CFGR_EXTSEL)                            << (4U * 1UL)) | \
                                             ((ADC_CFGR_EXTSEL)                            << (4U * 2UL)) | \
                                             ((ADC_CFGR_EXTSEL)                            << (4U * 3UL))  )

Definition at line 120 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_REG_GetTriggerSource().

#define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode: mask of bit */

Definition at line 277 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_GetCalibrationFactor(), and LL_ADC_SetCalibrationFactor().

#define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode: position of bit */

Definition at line 278 of file stm32wbxx_ll_adc.h.

#define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a shift of 4 ranks */

Definition at line 279 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_GetCalibrationFactor(), and LL_ADC_SetCalibrationFactor().

#define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)

Definition at line 274 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_GetCalibrationFactor(), and LL_ADC_SetCalibrationFactor().

#define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)

Definition at line 273 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_StartCalibration().

#define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */

Definition at line 275 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_GetChannelSingleDiff(), and LL_ADC_SetChannelSingleDiff().

#define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen to perform of shift when single mode is selected, shift value out of channels bits range. */

Definition at line 276 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_SetChannelSingleDiff().

#define ADC_SMPR1_REGOFFSET (0x00000000UL)

Definition at line 192 of file stm32wbxx_ll_adc.h.

#define ADC_SMPR2_REGOFFSET (0x02000000UL)

Definition at line 193 of file stm32wbxx_ll_adc.h.

#define ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */

Definition at line 195 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_GetChannelSamplingTime(), and LL_ADC_SetChannelSamplingTime().

#define ADC_SQR1_REGOFFSET (0x00000000UL)

Definition at line 56 of file stm32wbxx_ll_adc.h.

#define ADC_SQR2_REGOFFSET (0x00000100UL)

Definition at line 57 of file stm32wbxx_ll_adc.h.

#define ADC_SQR3_REGOFFSET (0x00000200UL)

Definition at line 58 of file stm32wbxx_ll_adc.h.

#define ADC_SQR4_REGOFFSET (0x00000300UL)

Definition at line 59 of file stm32wbxx_ll_adc.h.

#define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */

Definition at line 62 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerRanks(), and LL_ADC_REG_SetSequencerRanks().

#define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)

Definition at line 68 of file stm32wbxx_ll_adc.c.

Referenced by LL_ADC_DeInit().

#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)

Definition at line 69 of file stm32wbxx_ll_adc.c.

Referenced by LL_ADC_DeInit().

#define ADC_TR1_HT1_BITOFFSET_POS (16UL) /* Value equivalent to bitfield "ADC_TR1_HT1" position in register */

Definition at line 332 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_ConfigAnalogWDThresholds().

#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32WB, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */

Definition at line 344 of file stm32wbxx_ll_adc.h.

#define TEMPSENSOR_CAL1_TEMP (30L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */

Definition at line 346 of file stm32wbxx_ll_adc.h.

#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75CAUL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32WB, temperature sensor ADC raw data acquired at temperature 130 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */

Definition at line 345 of file stm32wbxx_ll_adc.h.

#define TEMPSENSOR_CAL2_TEMP (130L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */

Definition at line 347 of file stm32wbxx_ll_adc.h.

#define TEMPSENSOR_CAL_VREFANALOG (3000UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */

Definition at line 348 of file stm32wbxx_ll_adc.h.

#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, address of parameter VREFINT: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.6 V (tolerance: +-10 mV). */

Definition at line 341 of file stm32wbxx_ll_adc.h.

#define VREFINT_CAL_VREF (3600UL) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */

Definition at line 342 of file stm32wbxx_ll_adc.h.

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC Private Macros

Defines
ADC Private Macros
ADC

Defines

#define | IS_LL_ADC_COMMON_CLOCK(__CLOCK__)
#define | IS_LL_ADC_RESOLUTION(__RESOLUTION__)
#define | IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__)
#define | IS_LL_ADC_LOW_POWER(__LOW_POWER__)
#define | IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__)
#define | IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__)
#define | IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__)
#define | IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__)
#define | IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__)
#define | IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__)
#define | IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__)
#define | IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__)
#define | IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__)
#define | IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__)
#define | IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__)
#define | __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.

Define Documentation

#define __ADC_PTR_REG_OFFSET | ( | __REG__,
 |  | __REG_OFFFSET__
 | ) | ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))

Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.

Parameters:
__REG__ | Register basis from which the offset is applied.
__REG_OFFFSET__ | Offset to be applied (unit: number of registers).
Return values:
Pointer to register address

Definition at line 369 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_ConfigAnalogWDThresholds(), LL_ADC_GetAnalogWDMonitChannels(), LL_ADC_GetAnalogWDThresholds(), LL_ADC_GetChannelSamplingTime(), LL_ADC_GetOffsetChannel(), LL_ADC_GetOffsetLevel(), LL_ADC_GetOffsetState(), LL_ADC_INJ_ReadConversionData10(), LL_ADC_INJ_ReadConversionData12(), LL_ADC_INJ_ReadConversionData32(), LL_ADC_INJ_ReadConversionData6(), LL_ADC_INJ_ReadConversionData8(), LL_ADC_REG_GetSequencerRanks(), LL_ADC_REG_SetSequencerRanks(), LL_ADC_SetAnalogWDMonitChannels(), LL_ADC_SetAnalogWDThresholds(), LL_ADC_SetChannelSamplingTime(), LL_ADC_SetOffset(), and LL_ADC_SetOffsetState().

#define IS_LL_ADC_COMMON_CLOCK ( __CLOCK__ )
Value:
(   ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1)                             \
   || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2)                             \
   || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4)                             \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1)                                 \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2)                                 \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4)                                 \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6)                                 \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8)                                 \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10)                                \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12)                                \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16)                                \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32)                                \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64)                                \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128)                               \
   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256)                               \
  )

Definition at line 83 of file stm32wbxx_ll_adc.c.

Referenced by LL_ADC_CommonInit().

#define IS_LL_ADC_DATA_ALIGN ( __DATA_ALIGN__ )
Value:
(   ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT)                            \
   || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT)                             \
  )

Definition at line 110 of file stm32wbxx_ll_adc.c.

Referenced by LL_ADC_Init().

#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE ( __INJ_SEQ_DISCONT_MODE__ )
Value:
(   ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE)           \
   || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK)             \
  )

Definition at line 211 of file stm32wbxx_ll_adc.c.

Referenced by LL_ADC_INJ_Init().

#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH ( __INJ_SEQ_SCAN_LENGTH__ )
Value:
(   ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE)               \
   || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS)         \
   || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS)         \
   || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS)         \
  )

Definition at line 204 of file stm32wbxx_ll_adc.c.

Referenced by LL_ADC_INJ_Init().

#define IS_LL_ADC_INJ_TRIG_AUTO ( __INJ_TRIG_AUTO__ )
Value:
(   ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT)                     \
   || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR)                \
  )

Definition at line 199 of file stm32wbxx_ll_adc.c.

Referenced by LL_ADC_INJ_Init().

#define IS_LL_ADC_INJ_TRIG_EXT_EDGE ( __INJ_TRIG_EXT_EDGE__ )
Value:
(   ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING)                  \
   || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING)                 \
   || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING)           \
  )

Definition at line 193 of file stm32wbxx_ll_adc.c.

#define IS_LL_ADC_INJ_TRIG_SOURCE ( __INJ_TRIG_SOURCE__ )
Value:
(   ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                      \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)                 \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)                \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)                  \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)                 \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1)                  \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)               \
  )

Definition at line 183 of file stm32wbxx_ll_adc.c.

Referenced by LL_ADC_INJ_Init().

#define IS_LL_ADC_LOW_POWER ( __LOW_POWER__ )
Value:
(   ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE)                                 \
   || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT)                                  \
  )

Definition at line 115 of file stm32wbxx_ll_adc.c.

Referenced by LL_ADC_Init().

#define IS_LL_ADC_REG_CONTINUOUS_MODE ( __REG_CONTINUOUS_MODE__ )
Value:
(   ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE)                    \
   || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS)                \
  )

Definition at line 134 of file stm32wbxx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_REG_DMA_TRANSFER ( __REG_DMA_TRANSFER__ )
Value:
(   ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE)                 \
   || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED)              \
   || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED)            \
  )

Definition at line 139 of file stm32wbxx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR ( __REG_OVR_DATA_BEHAVIOR__ )
Value:
(   ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED)           \
   || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN)         \
  )

Definition at line 145 of file stm32wbxx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE ( __REG_SEQ_DISCONT_MODE__ )
Value:
(   ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE)           \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK)             \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS)            \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS)            \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS)            \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS)            \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS)            \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS)            \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS)            \
  )

Definition at line 169 of file stm32wbxx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH ( __REG_SEQ_SCAN_LENGTH__ )
Value:
(   ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE)               \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS)        \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS)        \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS)        \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS)        \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS)        \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS)        \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS)        \
  )

Definition at line 150 of file stm32wbxx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_REG_TRIG_SOURCE ( __REG_TRIG_SOURCE__ )
Value:
(   ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                      \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO)                 \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)                \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1)                  \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2)                  \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3)                  \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO)                 \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)                  \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)               \
  )

Definition at line 122 of file stm32wbxx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_RESOLUTION ( __RESOLUTION__ )
Value:
(   ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B)                              \
   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B)                              \
   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B)                               \
   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B)                               \
  )

Definition at line 103 of file stm32wbxx_ll_adc.c.

Referenced by LL_ADC_Init().

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LL_ADC_CommonInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_ADC_CommonInitTypeDef Struct Reference
ADC Exported Init structure

Structure definition of some features of ADC common parameters and multimode (all ADC instances belonging to the same ADC common instance). More...

#include <stm32wbxx_ll_adc.h>

Data Fields

uint32_t CommonClock

Detailed Description

Structure definition of some features of ADC common parameters and multimode (all ADC instances belonging to the same ADC common instance).

Note:
The setting of these parameters by function LL_ADC_CommonInit() is conditioned to ADC instances state (all ADC instances sharing the same ADC common instance): All ADC instances sharing the same ADC common instance must be disabled.

Definition at line 393 of file stm32wbxx_ll_adc.h.

Field Documentation

uint32_t LL_ADC_CommonInitTypeDef::CommonClock

Set parameter common to several ADC: Clock source and prescaler. This parameter can be a value of ADC common - Clock source

Note:
On this STM32 serie, if ADC group injected is used, some clock ratio constraints between ADC clock and AHB clock must be respected. Refer to reference manual.

This feature can be modified afterwards using unitary function LL_ADC_SetCommonClock().

Definition at line 395 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_CommonInit(), and LL_ADC_CommonStructInit().

The documentation for this struct was generated from the following file:
  • stm32wbxx_ll_adc.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LL_ADC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_ADC_InitTypeDef Struct Reference
ADC Exported Init structure

Structure definition of some features of ADC instance. More...

#include <stm32wbxx_ll_adc.h>

Data Fields

uint32_t | Resolution
uint32_t | DataAlignment
uint32_t | LowPowerMode

Detailed Description

Structure definition of some features of ADC instance.

Note:
These parameters have an impact on ADC scope: ADC instance. Affects both group regular and group injected (availability of ADC group injected depends on STM32 families). Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: ADC instance .
The setting of these parameters by function LL_ADC_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 families. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.

Definition at line 425 of file stm32wbxx_ll_adc.h.

Field Documentation

uint32_t LL_ADC_InitTypeDef::DataAlignment

Set ADC conversion data alignment. This parameter can be a value of ADC instance - Data alignment

This feature can be modified afterwards using unitary function LL_ADC_SetDataAlignment().

Definition at line 432 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_Init(), and LL_ADC_StructInit().

uint32_t LL_ADC_InitTypeDef::LowPowerMode

Set ADC low power mode. This parameter can be a value of ADC instance - Low power mode

This feature can be modified afterwards using unitary function LL_ADC_SetLowPowerMode().

Definition at line 437 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_Init(), and LL_ADC_StructInit().

uint32_t LL_ADC_InitTypeDef::Resolution

Set ADC resolution. This parameter can be a value of ADC instance - Resolution

This feature can be modified afterwards using unitary function LL_ADC_SetResolution().

Definition at line 427 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_Init(), and LL_ADC_StructInit().

The documentation for this struct was generated from the following file:
  • stm32wbxx_ll_adc.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LL_ADC_REG_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_ADC_REG_InitTypeDef Struct Reference
ADC Exported Init structure

Structure definition of some features of ADC group regular. More...

#include <stm32wbxx_ll_adc.h>

Data Fields

uint32_t | TriggerSource
uint32_t | SequencerLength
uint32_t | SequencerDiscont
uint32_t | ContinuousMode
uint32_t | DMATransfer
uint32_t | Overrun

Detailed Description

Structure definition of some features of ADC group regular.

Note:
These parameters have an impact on ADC scope: ADC group regular. Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: group regular (functions with prefix "REG").
The setting of these parameters by function LL_ADC_REG_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 families. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.

Definition at line 463 of file stm32wbxx_ll_adc.h.

Field Documentation

uint32_t LL_ADC_REG_InitTypeDef::ContinuousMode

Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically). This parameter can be a value of ADC group regular - Continuous mode Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.

This feature can be modified afterwards using unitary function LL_ADC_REG_SetContinuousMode().

Definition at line 485 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

uint32_t LL_ADC_REG_InitTypeDef::DMATransfer

Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode. This parameter can be a value of ADC group regular - DMA transfer of ADC conversion data

This feature can be modified afterwards using unitary function LL_ADC_REG_SetDMATransfer().

Definition at line 491 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

uint32_t LL_ADC_REG_InitTypeDef::Overrun

Set ADC group regular behavior in case of overrun: data preserved or overwritten. This parameter can be a value of ADC group regular - Overrun behavior on conversion data

This feature can be modified afterwards using unitary function LL_ADC_REG_SetOverrun().

Definition at line 496 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

uint32_t LL_ADC_REG_InitTypeDef::SequencerDiscont

Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. This parameter can be a value of ADC group regular - Sequencer discontinuous mode

Note:
This parameter has an effect only if group regular sequencer is enabled (scan length of 2 ranks or more).

This feature can be modified afterwards using unitary function LL_ADC_REG_SetSequencerDiscont().

Definition at line 478 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

uint32_t LL_ADC_REG_InitTypeDef::SequencerLength

Set ADC group regular sequencer length. This parameter can be a value of ADC group regular - Sequencer scan length

This feature can be modified afterwards using unitary function LL_ADC_REG_SetSequencerLength().

Definition at line 473 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

uint32_t LL_ADC_REG_InitTypeDef::TriggerSource

Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line). This parameter can be a value of ADC group regular - Trigger source

Note:
On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). In case of need to modify trigger edge, use function LL_ADC_REG_SetTriggerEdge().

This feature can be modified afterwards using unitary function LL_ADC_REG_SetTriggerSource().

Definition at line 465 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

The documentation for this struct was generated from the following file:
  • stm32wbxx_ll_adc.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LL_ADC_INJ_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_ADC_INJ_InitTypeDef Struct Reference
ADC Exported Init structure

Structure definition of some features of ADC group injected. More...

#include <stm32wbxx_ll_adc.h>

Data Fields

uint32_t | TriggerSource
uint32_t | SequencerLength
uint32_t | SequencerDiscont
uint32_t | TrigAuto

Detailed Description

Structure definition of some features of ADC group injected.

Note:
These parameters have an impact on ADC scope: ADC group injected. Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: group regular (functions with prefix "INJ").
The setting of these parameters by function LL_ADC_INJ_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 families. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.

Definition at line 523 of file stm32wbxx_ll_adc.h.

Field Documentation

uint32_t LL_ADC_INJ_InitTypeDef::SequencerDiscont

Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. This parameter can be a value of ADC group injected - Sequencer discontinuous mode

Note:
This parameter has an effect only if group injected sequencer is enabled (scan length of 2 ranks or more).

This feature can be modified afterwards using unitary function LL_ADC_INJ_SetSequencerDiscont().

Definition at line 538 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), and LL_ADC_INJ_StructInit().

uint32_t LL_ADC_INJ_InitTypeDef::SequencerLength

Set ADC group injected sequencer length. This parameter can be a value of ADC group injected - Sequencer scan length

This feature can be modified afterwards using unitary function LL_ADC_INJ_SetSequencerLength().

Definition at line 533 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), and LL_ADC_INJ_StructInit().

uint32_t LL_ADC_INJ_InitTypeDef::TrigAuto

Set ADC group injected conversion trigger: independent or from ADC group regular. This parameter can be a value of ADC group injected - Automatic trigger mode Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.

This feature can be modified afterwards using unitary function LL_ADC_INJ_SetTrigAuto().

Definition at line 545 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), and LL_ADC_INJ_StructInit().

uint32_t LL_ADC_INJ_InitTypeDef::TriggerSource

Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line). This parameter can be a value of ADC group injected - Trigger source

Note:
On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). In case of need to modify trigger edge, use function LL_ADC_INJ_SetTriggerEdge().

This feature can be modified afterwards using unitary function LL_ADC_INJ_SetTriggerSource().

Definition at line 525 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), and LL_ADC_INJ_StructInit().

The documentation for this struct was generated from the following file:
  • stm32wbxx_ll_adc.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC flags

Defines
ADC flags
ADC Exported Constants

Flags defines which can be used with LL_ADC_ReadReg function. More...

Defines

#define | LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY
#define | LL_ADC_FLAG_EOC ADC_ISR_EOC
#define | LL_ADC_FLAG_EOS ADC_ISR_EOS
#define | LL_ADC_FLAG_OVR ADC_ISR_OVR
#define | LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP
#define | LL_ADC_FLAG_JEOC ADC_ISR_JEOC
#define | LL_ADC_FLAG_JEOS ADC_ISR_JEOS
#define | LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF
#define | LL_ADC_FLAG_AWD1 ADC_ISR_AWD1
#define | LL_ADC_FLAG_AWD2 ADC_ISR_AWD2
#define | LL_ADC_FLAG_AWD3 ADC_ISR_AWD3

Detailed Description

Flags defines which can be used with LL_ADC_ReadReg function.

Define Documentation

#define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY

ADC flag ADC instance ready

Definition at line 567 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_ADRDY(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_ADRDY().

#define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1

ADC flag ADC analog watchdog 1

Definition at line 575 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_AWD1(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_AWD1().

#define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2

ADC flag ADC analog watchdog 2

Definition at line 576 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_AWD2(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_AWD2().

#define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3

ADC flag ADC analog watchdog 3

Definition at line 577 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_AWD3(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_AWD3().

#define LL_ADC_FLAG_EOC ADC_ISR_EOC

ADC flag ADC group regular end of unitary conversion

Definition at line 568 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_EOC(), and LL_ADC_DeInit().

#define LL_ADC_FLAG_EOS ADC_ISR_EOS

ADC flag ADC group regular end of sequence conversions

Definition at line 569 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_EOS(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_EOS().

#define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP

ADC flag ADC group regular end of sampling phase

Definition at line 571 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_EOSMP(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_EOSMP().

#define LL_ADC_FLAG_JEOC ADC_ISR_JEOC

ADC flag ADC group injected end of unitary conversion

Definition at line 572 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_JEOC(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_JEOC().

#define LL_ADC_FLAG_JEOS ADC_ISR_JEOS

ADC flag ADC group injected end of sequence conversions

Definition at line 573 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_JEOS(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_JEOS().

#define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF

ADC flag ADC group injected contexts queue overflow

Definition at line 574 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_JQOVF(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_JQOVF().

#define LL_ADC_FLAG_OVR ADC_ISR_OVR

ADC flag ADC group regular overrun

Definition at line 570 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_OVR(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_OVR().

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STM32WB55xx HAL User Manual: ADC interruptions for configuration (interruption enable or disable)

Defines
ADC interruptions for configuration (interruption enable or disable)
ADC Exported Constants

IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions. More...

Defines

#define | LL_ADC_IT_ADRDY ADC_IER_ADRDYIE
#define | LL_ADC_IT_EOC ADC_IER_EOCIE
#define | LL_ADC_IT_EOS ADC_IER_EOSIE
#define | LL_ADC_IT_OVR ADC_IER_OVRIE
#define | LL_ADC_IT_EOSMP ADC_IER_EOSMPIE
#define | LL_ADC_IT_JEOC ADC_IER_JEOCIE
#define | LL_ADC_IT_JEOS ADC_IER_JEOSIE
#define | LL_ADC_IT_JQOVF ADC_IER_JQOVFIE
#define | LL_ADC_IT_AWD1 ADC_IER_AWD1IE
#define | LL_ADC_IT_AWD2 ADC_IER_AWD2IE
#define | LL_ADC_IT_AWD3 ADC_IER_AWD3IE

Detailed Description

IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions.

Define Documentation

#define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE

ADC interruption ADC instance ready

Definition at line 586 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_ADRDY(), LL_ADC_EnableIT_ADRDY(), and LL_ADC_IsEnabledIT_ADRDY().

#define LL_ADC_IT_AWD1 ADC_IER_AWD1IE

ADC interruption ADC analog watchdog 1

Definition at line 594 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_AWD1(), LL_ADC_EnableIT_AWD1(), and LL_ADC_IsEnabledIT_AWD1().

#define LL_ADC_IT_AWD2 ADC_IER_AWD2IE

ADC interruption ADC analog watchdog 2

Definition at line 595 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_AWD2(), LL_ADC_EnableIT_AWD2(), and LL_ADC_IsEnabledIT_AWD2().

#define LL_ADC_IT_AWD3 ADC_IER_AWD3IE

ADC interruption ADC analog watchdog 3

Definition at line 596 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_AWD3(), LL_ADC_EnableIT_AWD3(), and LL_ADC_IsEnabledIT_AWD3().

#define LL_ADC_IT_EOC ADC_IER_EOCIE

ADC interruption ADC group regular end of unitary conversion

Definition at line 587 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_EOC(), LL_ADC_EnableIT_EOC(), and LL_ADC_IsEnabledIT_EOC().

#define LL_ADC_IT_EOS ADC_IER_EOSIE

ADC interruption ADC group regular end of sequence conversions

Definition at line 588 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_EOS(), LL_ADC_EnableIT_EOS(), and LL_ADC_IsEnabledIT_EOS().

#define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE

ADC interruption ADC group regular end of sampling phase

Definition at line 590 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_EOSMP(), LL_ADC_EnableIT_EOSMP(), and LL_ADC_IsEnabledIT_EOSMP().

#define LL_ADC_IT_JEOC ADC_IER_JEOCIE

ADC interruption ADC group injected end of unitary conversion

Definition at line 591 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_JEOC(), LL_ADC_EnableIT_JEOC(), and LL_ADC_IsEnabledIT_JEOC().

#define LL_ADC_IT_JEOS ADC_IER_JEOSIE

ADC interruption ADC group injected end of sequence conversions

Definition at line 592 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_JEOS(), LL_ADC_EnableIT_JEOS(), and LL_ADC_IsEnabledIT_JEOS().

#define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE

ADC interruption ADC group injected contexts queue overflow

Definition at line 593 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_JQOVF(), LL_ADC_EnableIT_JQOVF(), and LL_ADC_IsEnabledIT_JQOVF().

#define LL_ADC_IT_OVR ADC_IER_OVRIE

ADC interruption ADC group regular overrun

Definition at line 589 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_DisableIT_OVR(), LL_ADC_EnableIT_OVR(), and LL_ADC_IsEnabledIT_OVR().

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STM32WB55xx HAL User Manual: ADC registers compliant with specific purpose

Defines
ADC registers compliant with specific purpose
ADC Exported Constants

Defines

#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */

Define Documentation

#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */

Definition at line 607 of file stm32wbxx_ll_adc.h.

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STM32WB55xx HAL User Manual: ADC common - Clock source

Defines
ADC common - Clock source
ADC Exported Constants

Defines

#define | LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0)
#define | LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 )
#define | LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0)
#define | LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL)
#define | LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 )
#define | LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 )
#define | LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 )
#define | LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3)
#define | LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1)
#define | LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)

Define Documentation

#define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL)

ADC asynchronous clock without prescaler

Definition at line 618 of file stm32wbxx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0)

ADC asynchronous clock with prescaler division by 10

Definition at line 623 of file stm32wbxx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 )

ADC asynchronous clock with prescaler division by 12

Definition at line 624 of file stm32wbxx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1)

ADC asynchronous clock with prescaler division by 128

Definition at line 628 of file stm32wbxx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)

ADC asynchronous clock with prescaler division by 16

Definition at line 625 of file stm32wbxx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0)

ADC asynchronous clock with prescaler division by 2

Definition at line 619 of file stm32wbxx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)

ADC asynchronous clock with prescaler division by 256

Definition at line 629 of file stm32wbxx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3)

ADC asynchronous clock with prescaler division by 32

Definition at line 626 of file stm32wbxx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 )

ADC asynchronous clock with prescaler division by 4

Definition at line 620 of file stm32wbxx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)

ADC asynchronous clock with prescaler division by 6

Definition at line 621 of file stm32wbxx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0)

ADC asynchronous clock with prescaler division by 64

Definition at line 627 of file stm32wbxx_ll_adc.h.

#define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 )

ADC asynchronous clock with prescaler division by 8

Definition at line 622 of file stm32wbxx_ll_adc.h.

#define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0)

ADC synchronous clock derived from AHB clock without prescaler

Definition at line 615 of file stm32wbxx_ll_adc.h.

#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 )

ADC synchronous clock derived from AHB clock with prescaler division by 2

Definition at line 616 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_CommonStructInit().

#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0)

ADC synchronous clock derived from AHB clock with prescaler division by 4

Definition at line 617 of file stm32wbxx_ll_adc.h.

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STM32WB55xx HAL User Manual: ADC common - Measurement path to internal channels

Defines
ADC common - Measurement path to internal channels
ADC Exported Constants

Defines

#define | LL_ADC_PATH_INTERNAL_NONE (0x00000000UL)
#define | LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN)
#define | LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN)
#define | LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN)

Define Documentation

#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL)

ADC measurement pathes all disabled

Definition at line 642 of file stm32wbxx_ll_adc.h.

#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN)

ADC measurement path to internal channel temperature sensor

Definition at line 644 of file stm32wbxx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN)

ADC measurement path to internal channel Vbat

Definition at line 645 of file stm32wbxx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN)

ADC measurement path to internal channel VrefInt

Definition at line 643 of file stm32wbxx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

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STM32WB55xx HAL User Manual: ADC instance - Resolution

Defines
ADC instance - Resolution
ADC Exported Constants

Defines

#define | LL_ADC_RESOLUTION_12B (0x00000000UL)
#define | LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_0)
#define | LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_1 )
#define | LL_ADC_RESOLUTION_6B (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)

Define Documentation

#define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_0)

ADC resolution 10 bits

Definition at line 654 of file stm32wbxx_ll_adc.h.

#define LL_ADC_RESOLUTION_12B (0x00000000UL)

ADC resolution 12 bits

Definition at line 653 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_StructInit().

#define LL_ADC_RESOLUTION_6B (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)

ADC resolution 6 bits

Definition at line 656 of file stm32wbxx_ll_adc.h.

#define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_1 )

ADC resolution 8 bits

Definition at line 655 of file stm32wbxx_ll_adc.h.

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STM32WB55xx HAL User Manual: ADC instance - Data alignment

Defines
ADC instance - Data alignment
ADC Exported Constants

Defines

#define | LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL)
#define | LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN)

Define Documentation

#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN)

ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)

Definition at line 665 of file stm32wbxx_ll_adc.h.

#define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL)

ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)

Definition at line 664 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_StructInit().

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STM32WB55xx HAL User Manual: ADC instance - Low power mode

Defines
ADC instance - Low power mode
ADC Exported Constants

Defines

#define | LL_ADC_LP_MODE_NONE (0x00000000UL)
#define | LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY)

Define Documentation

#define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY)

ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function LL_ADC_SetLowPowerMode().

Definition at line 674 of file stm32wbxx_ll_adc.h.

#define LL_ADC_LP_MODE_NONE (0x00000000UL)

No ADC low power mode activated

Definition at line 673 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_StructInit().

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STM32WB55xx HAL User Manual: ADC instance - Offset number

Defines
ADC instance - Offset number
ADC Exported Constants

Defines

#define | LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET
#define | LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET
#define | LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET
#define | LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET

Define Documentation

#define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET

ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)

Definition at line 682 of file stm32wbxx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET

ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)

Definition at line 683 of file stm32wbxx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET

ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)

Definition at line 684 of file stm32wbxx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET

ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)

Definition at line 685 of file stm32wbxx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

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STM32WB55xx HAL User Manual: ADC instance - Offset state

Defines
ADC instance - Offset state
ADC Exported Constants

Defines

#define | LL_ADC_OFFSET_DISABLE (0x00000000UL)
#define | LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN)

Define Documentation

#define LL_ADC_OFFSET_DISABLE (0x00000000UL)

ADC offset disabled (among ADC selected offset number 1, 2, 3 or 4)

Definition at line 693 of file stm32wbxx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN)

ADC offset enabled (among ADC selected offset number 1, 2, 3 or 4)

Definition at line 694 of file stm32wbxx_ll_adc.h.

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STM32WB55xx HAL User Manual: ADC instance - Groups

Defines
ADC instance - Groups
ADC Exported Constants

Defines

#define | LL_ADC_GROUP_REGULAR (0x00000001UL)
#define | LL_ADC_GROUP_INJECTED (0x00000002UL)
#define | LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL)

Define Documentation

#define LL_ADC_GROUP_INJECTED (0x00000002UL)

ADC group injected (not available on all STM32 devices)

Definition at line 703 of file stm32wbxx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define LL_ADC_GROUP_REGULAR (0x00000001UL)

ADC group regular (available on all STM32 devices)

Definition at line 702 of file stm32wbxx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL)

ADC both groups regular and injected

Definition at line 704 of file stm32wbxx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

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STM32WB55xx HAL User Manual: ADC instance - Channel number

Defines
ADC instance - Channel number
ADC Exported Constants

Defines

#define | LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD )
#define | LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD )
#define | LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD )
#define | LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD )
#define | LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD )
#define | LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD )
#define | LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | ADC_CHANNEL_6_BITFIELD )
#define | LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | ADC_CHANNEL_7_BITFIELD )
#define | LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | ADC_CHANNEL_8_BITFIELD )
#define | LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | ADC_CHANNEL_9_BITFIELD )
#define | LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD)
#define | LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD)
#define | LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD)
#define | LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD)
#define | LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD)
#define | LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD)
#define | LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD)
#define | LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD)
#define | LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD)
#define | LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_0 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH)

Define Documentation

#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN0

Definition at line 712 of file stm32wbxx_ll_adc.h.

#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN1

Definition at line 713 of file stm32wbxx_ll_adc.h.

#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD)

ADC external channel (channel connected to GPIO pin) ADCx_IN10

Definition at line 722 of file stm32wbxx_ll_adc.h.

#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD)

ADC external channel (channel connected to GPIO pin) ADCx_IN11

Definition at line 723 of file stm32wbxx_ll_adc.h.

#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD)

ADC external channel (channel connected to GPIO pin) ADCx_IN12

Definition at line 724 of file stm32wbxx_ll_adc.h.

#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD)

ADC external channel (channel connected to GPIO pin) ADCx_IN13

Definition at line 725 of file stm32wbxx_ll_adc.h.

#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD)

ADC external channel (channel connected to GPIO pin) ADCx_IN14

Definition at line 726 of file stm32wbxx_ll_adc.h.

#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD)

ADC external channel (channel connected to GPIO pin) ADCx_IN15

Definition at line 727 of file stm32wbxx_ll_adc.h.

#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD)

ADC external channel (channel connected to GPIO pin) ADCx_IN16

Definition at line 728 of file stm32wbxx_ll_adc.h.

#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD)

ADC external channel (channel connected to GPIO pin) ADCx_IN17

Definition at line 729 of file stm32wbxx_ll_adc.h.

#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD)

ADC external channel (channel connected to GPIO pin) ADCx_IN18

Definition at line 730 of file stm32wbxx_ll_adc.h.

#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN2

Definition at line 714 of file stm32wbxx_ll_adc.h.

#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN3

Definition at line 715 of file stm32wbxx_ll_adc.h.

#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN4

Definition at line 716 of file stm32wbxx_ll_adc.h.

#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN5

Definition at line 717 of file stm32wbxx_ll_adc.h.

#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | ADC_CHANNEL_6_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN6

Definition at line 718 of file stm32wbxx_ll_adc.h.

#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | ADC_CHANNEL_7_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN7

Definition at line 719 of file stm32wbxx_ll_adc.h.

#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | ADC_CHANNEL_8_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN8

Definition at line 720 of file stm32wbxx_ll_adc.h.

#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | ADC_CHANNEL_9_BITFIELD )

ADC external channel (channel connected to GPIO pin) ADCx_IN9

Definition at line 721 of file stm32wbxx_ll_adc.h.

#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH)

ADC internal channel connected to Temperature sensor.

Definition at line 732 of file stm32wbxx_ll_adc.h.

#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH)

ADC internal channel connected to Vbat/2: Vbat voltage through a divider ladder of factor 1/2 to have Vbat always below Vdda.

Definition at line 733 of file stm32wbxx_ll_adc.h.

#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_0 | ADC_CHANNEL_ID_INTERNAL_CH)

ADC internal channel connected to VrefInt: Internal voltage reference.

Definition at line 731 of file stm32wbxx_ll_adc.h.

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STM32WB55xx HAL User Manual: ADC group regular - Trigger source

Defines
ADC group regular - Trigger source
ADC Exported Constants

Defines

#define | LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL)
#define | LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

Define Documentation

#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting).

Definition at line 749 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 744 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 745 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 746 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 742 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting).

Definition at line 743 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 748 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)

ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 747 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL)

ADC group regular conversion trigger internal: SW start.

Definition at line 741 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_REG_IsTriggerSourceSWStart(), and LL_ADC_REG_StructInit().

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STM32WB55xx HAL User Manual: ADC group regular - Trigger edge

Defines
ADC group regular - Trigger edge
ADC Exported Constants

Defines

#define | LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR_EXTEN_0)
#define | LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1 )
#define | LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0)

Define Documentation

#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1 )

ADC group regular conversion trigger polarity set to falling edge

Definition at line 758 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR_EXTEN_0)

ADC group regular conversion trigger polarity set to rising edge

Definition at line 757 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0)

ADC group regular conversion trigger polarity set to both rising and falling edges

Definition at line 759 of file stm32wbxx_ll_adc.h.

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STM32WB55xx HAL User Manual: ADC group regular - Continuous mode

Defines
ADC group regular - Continuous mode
ADC Exported Constants

Defines

#define | LL_ADC_REG_CONV_SINGLE (0x00000000UL)
#define | LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT)

Define Documentation

#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT)

ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically

Definition at line 768 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_CONV_SINGLE (0x00000000UL)

ADC conversions are performed in single mode: one conversion per trigger

Definition at line 767 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_REG_StructInit().

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STM32WB55xx HAL User Manual: ADC group regular - DMA transfer of ADC conversion data

Defines
ADC group regular - DMA transfer of ADC conversion data
ADC Exported Constants

Defines

#define | LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL)
#define | LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMAEN)
#define | LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN)

Define Documentation

#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMAEN)

ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular.

Definition at line 777 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL)

ADC conversions are not transferred by DMA

Definition at line 776 of file stm32wbxx_ll_adc.h.

Referenced by HAL_ADC_IRQHandler(), and LL_ADC_REG_StructInit().

#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN)

ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular.

Definition at line 778 of file stm32wbxx_ll_adc.h.

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STM32WB55xx HAL User Manual: ADC group regular - Overrun behavior on conversion data

Defines
ADC group regular - Overrun behavior on conversion data
ADC Exported Constants

Defines

#define | LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL)
#define | LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD)

Define Documentation

#define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD)

ADC group regular behavior in case of overrun: data overwritten

Definition at line 789 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_REG_StructInit().

#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL)

ADC group regular behavior in case of overrun: data preserved

Definition at line 788 of file stm32wbxx_ll_adc.h.

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STM32WB55xx HAL User Manual: ADC group regular - Sequencer scan length

Defines
ADC group regular - Sequencer scan length
ADC Exported Constants

Defines

#define | LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0)

Define Documentation

#define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL)

ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel)

Definition at line 797 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 10 ranks in the sequence

Definition at line 806 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 )

ADC group regular sequencer enable with 11 ranks in the sequence

Definition at line 807 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 12 ranks in the sequence

Definition at line 808 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 )

ADC group regular sequencer enable with 13 ranks in the sequence

Definition at line 809 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 14 ranks in the sequence

Definition at line 810 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 )

ADC group regular sequencer enable with 15 ranks in the sequence

Definition at line 811 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 16 ranks in the sequence

Definition at line 812 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0)

ADC group regular sequencer enable with 2 ranks in the sequence

Definition at line 798 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 )

ADC group regular sequencer enable with 3 ranks in the sequence

Definition at line 799 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 4 ranks in the sequence

Definition at line 800 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 )

ADC group regular sequencer enable with 5 ranks in the sequence

Definition at line 801 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 6 ranks in the sequence

Definition at line 802 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 )

ADC group regular sequencer enable with 7 ranks in the sequence

Definition at line 803 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 8 ranks in the sequence

Definition at line 804 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 )

ADC group regular sequencer enable with 9 ranks in the sequence

Definition at line 805 of file stm32wbxx_ll_adc.h.

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STM32WB55xx HAL User Manual: ADC group regular - Sequencer discontinuous mode

Defines
ADC group regular - Sequencer discontinuous mode
ADC Exported Constants

Defines

#define | LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL)
#define | LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)

Define Documentation

#define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every rank

Definition at line 821 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)

ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks

Definition at line 822 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks

Definition at line 823 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks

Definition at line 824 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks

Definition at line 825 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks

Definition at line 826 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks

Definition at line 827 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks

Definition at line 828 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL)

ADC group regular sequencer discontinuous mode disable

Definition at line 820 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

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STM32WB55xx HAL User Manual: ADC group regular - Sequencer ranks

Defines
ADC group regular - Sequencer ranks
ADC Exported Constants

Defines

#define | LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS)

Define Documentation

#define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 1

Definition at line 836 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 10

Definition at line 845 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 11

Definition at line 846 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 12

Definition at line 847 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 13

Definition at line 848 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 14

Definition at line 849 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 15

Definition at line 850 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 16

Definition at line 851 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 2

Definition at line 837 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 3

Definition at line 838 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 4

Definition at line 839 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 5

Definition at line 840 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 6

Definition at line 841 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 7

Definition at line 842 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 8

Definition at line 843 of file stm32wbxx_ll_adc.h.

#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 9

Definition at line 844 of file stm32wbxx_ll_adc.h.

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STM32WB55xx HAL User Manual: ADC group injected - Trigger source

Defines
ADC group injected - Trigger source
ADC Exported Constants

Defines

#define | LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL)
#define | LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

Define Documentation

#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting).

Definition at line 865 of file stm32wbxx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 862 of file stm32wbxx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 860 of file stm32wbxx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting).

Definition at line 861 of file stm32wbxx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 864 of file stm32wbxx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)

ADC group injected conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 863 of file stm32wbxx_ll_adc.h.

#define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL)

ADC group injected conversion trigger internal: SW start.. Trigger edge set to rising edge (default setting).

Definition at line 859 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_INJ_ConfigQueueContext(), LL_ADC_INJ_IsTriggerSourceSWStart(), and LL_ADC_INJ_StructInit().

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STM32WB55xx HAL User Manual: ADC group injected - Trigger edge

Defines
ADC group injected - Trigger edge
ADC Exported Constants

Defines

#define | LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0)
#define | LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 )
#define | LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0)

Define Documentation

#define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 )

ADC group injected conversion trigger polarity set to falling edge

Definition at line 874 of file stm32wbxx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0)

ADC group injected conversion trigger polarity set to rising edge

Definition at line 873 of file stm32wbxx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0)

ADC group injected conversion trigger polarity set to both rising and falling edges

Definition at line 875 of file stm32wbxx_ll_adc.h.

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STM32WB55xx HAL User Manual: ADC group injected - Automatic trigger mode

Defines
ADC group injected - Automatic trigger mode
ADC Exported Constants

Defines

#define | LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL)
#define | LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO)

Define Documentation

#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO)

ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular.

Definition at line 884 of file stm32wbxx_ll_adc.h.

#define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL)

ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger.

Definition at line 883 of file stm32wbxx_ll_adc.h.

Referenced by HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), and LL_ADC_INJ_StructInit().

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STM32WB55xx HAL User Manual: ADC group injected - Context queue mode

Defines
ADC group injected - Context queue mode
ADC Exported Constants

Defines

#define | LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */
#define | LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */
#define | LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */

Define Documentation

#define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */

Definition at line 893 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_DeInit().

#define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */

Definition at line 892 of file stm32wbxx_ll_adc.h.

#define LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */

Definition at line 894 of file stm32wbxx_ll_adc.h.

Referenced by HAL_ADCEx_DisableInjectedQueue().

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STM32WB55xx HAL User Manual: ADC group injected - Sequencer scan length

Defines
ADC group injected - Sequencer scan length
ADC Exported Constants

Defines

#define | LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL)
#define | LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0)
#define | LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 )
#define | LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0)

Define Documentation

#define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL)

ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel)

Definition at line 902 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), and LL_ADC_INJ_StructInit().

#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0)

ADC group injected sequencer enable with 2 ranks in the sequence

Definition at line 903 of file stm32wbxx_ll_adc.h.

#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 )

ADC group injected sequencer enable with 3 ranks in the sequence

Definition at line 904 of file stm32wbxx_ll_adc.h.

#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0)

ADC group injected sequencer enable with 4 ranks in the sequence

Definition at line 905 of file stm32wbxx_ll_adc.h.

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STM32WB55xx HAL User Manual: ADC group injected - Sequencer discontinuous mode

Defines
ADC group injected - Sequencer discontinuous mode
ADC Exported Constants

Defines

#define | LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL)
#define | LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN)

Define Documentation

#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN)

ADC group injected sequencer discontinuous mode enable with sequence interruption every rank

Definition at line 914 of file stm32wbxx_ll_adc.h.

#define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL)

ADC group injected sequencer discontinuous mode disable

Definition at line 913 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_INJ_StructInit().

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STM32WB55xx HAL User Manual: ADC group injected - Sequencer ranks

Defines
ADC group injected - Sequencer ranks
ADC Exported Constants

Defines

#define | LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS)
#define | LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS)
#define | LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS)
#define | LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS)

Define Documentation

#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS)

ADC group injected sequencer rank 1

Definition at line 922 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_INJ_ConfigQueueContext().

#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS)

ADC group injected sequencer rank 2

Definition at line 923 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_INJ_ConfigQueueContext().

#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS)

ADC group injected sequencer rank 3

Definition at line 924 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_INJ_ConfigQueueContext().

#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS)

ADC group injected sequencer rank 4

Definition at line 925 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_INJ_ConfigQueueContext().

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STM32WB55xx HAL User Manual: Channel - Sampling time

Defines
Channel - Sampling time
ADC Exported Constants

Defines

#define | LL_ADC_SAMPLINGTIME_2CYCLES_5 (0x00000000UL)
#define | LL_ADC_SAMPLINGTIME_6CYCLES_5 ( ADC_SMPR2_SMP10_0)
#define | LL_ADC_SAMPLINGTIME_12CYCLES_5 ( ADC_SMPR2_SMP10_1 )
#define | LL_ADC_SAMPLINGTIME_24CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)
#define | LL_ADC_SAMPLINGTIME_47CYCLES_5 (ADC_SMPR2_SMP10_2 )
#define | LL_ADC_SAMPLINGTIME_92CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0)
#define | LL_ADC_SAMPLINGTIME_247CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 )
#define | LL_ADC_SAMPLINGTIME_640CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)

Define Documentation

#define LL_ADC_SAMPLINGTIME_12CYCLES_5 ( ADC_SMPR2_SMP10_1 )

Sampling time 12.5 ADC clock cycles

Definition at line 935 of file stm32wbxx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_247CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 )

Sampling time 247.5 ADC clock cycles

Definition at line 939 of file stm32wbxx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_24CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)

Sampling time 24.5 ADC clock cycles

Definition at line 936 of file stm32wbxx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_2CYCLES_5 (0x00000000UL)

Sampling time 2.5 ADC clock cycles

Definition at line 933 of file stm32wbxx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_47CYCLES_5 (ADC_SMPR2_SMP10_2 )

Sampling time 47.5 ADC clock cycles

Definition at line 937 of file stm32wbxx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_640CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)

Sampling time 640.5 ADC clock cycles

Definition at line 940 of file stm32wbxx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_6CYCLES_5 ( ADC_SMPR2_SMP10_0)

Sampling time 6.5 ADC clock cycles

Definition at line 934 of file stm32wbxx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_92CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0)

Sampling time 92.5 ADC clock cycles

Definition at line 938 of file stm32wbxx_ll_adc.h.

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STM32WB55xx HAL User Manual: Channel - Single or differential ending

Defines
Channel - Single or differential ending
ADC Exported Constants

Defines

#define | LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S)
#define | LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D)
#define | LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED)

Define Documentation

#define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED)

ADC channel ending set to both single ended and differential (literal used only to set calibration factors)

Definition at line 950 of file stm32wbxx_ll_adc.h.

#define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D)

ADC channel ending set to differential (literal also used to set calibration mode)

Definition at line 949 of file stm32wbxx_ll_adc.h.

#define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S)

ADC channel ending set to single ended (literal also used to set calibration mode)

Definition at line 948 of file stm32wbxx_ll_adc.h.

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STM32WB55xx HAL User Manual: Analog watchdog - Analog watchdog number

Defines
Analog watchdog - Analog watchdog number
ADC Exported Constants

Defines

#define | LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET)
#define | LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET)
#define | LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET)

Define Documentation

#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET)

ADC analog watchdog number 1

Definition at line 958 of file stm32wbxx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), and LL_ADC_GetAnalogWDMonitChannels().

#define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET)

ADC analog watchdog number 2

Definition at line 959 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET)

ADC analog watchdog number 3

Definition at line 960 of file stm32wbxx_ll_adc.h.

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STM32WB55xx HAL User Manual: Analog watchdog - Monitored channels

Defines
Analog watchdog - Monitored channels
ADC Exported Constants

Defines

#define | LL_ADC_AWD_DISABLE (0x00000000UL)
#define | LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN )
#define | LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN )
#define | LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN )
#define | LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

Define Documentation

#define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN )

ADC analog watchdog monitoring of all channels, converted by group injected only

Definition at line 970 of file stm32wbxx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN )

ADC analog watchdog monitoring of all channels, converted by group regular only

Definition at line 969 of file stm32wbxx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN )

ADC analog watchdog monitoring of all channels, converted by either group regular or injected

Definition at line 971 of file stm32wbxx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only

Definition at line 1033 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only

Definition at line 1032 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected

Definition at line 1034 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only

Definition at line 1036 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only

Definition at line 1035 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda

Definition at line 1037 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only

Definition at line 1030 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only

Definition at line 1029 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected

Definition at line 1031 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only

Definition at line 973 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only

Definition at line 972 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected

Definition at line 974 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only

Definition at line 1003 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only

Definition at line 1002 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected

Definition at line 1004 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only

Definition at line 1006 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only

Definition at line 1005 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected

Definition at line 1007 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only

Definition at line 1009 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only

Definition at line 1008 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected

Definition at line 1010 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only

Definition at line 1012 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only

Definition at line 1011 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected

Definition at line 1013 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only

Definition at line 1015 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only

Definition at line 1014 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected

Definition at line 1016 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only

Definition at line 1018 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only

Definition at line 1017 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected

Definition at line 1019 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only

Definition at line 1021 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only

Definition at line 1020 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected

Definition at line 1022 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only

Definition at line 1024 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only

Definition at line 1023 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected

Definition at line 1025 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only

Definition at line 1027 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only

Definition at line 1026 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected

Definition at line 1028 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only

Definition at line 976 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only

Definition at line 975 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected

Definition at line 977 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only

Definition at line 979 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only

Definition at line 978 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected

Definition at line 980 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only

Definition at line 982 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only

Definition at line 981 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected

Definition at line 983 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only

Definition at line 985 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only

Definition at line 984 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected

Definition at line 986 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only

Definition at line 988 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only

Definition at line 987 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected

Definition at line 989 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only

Definition at line 991 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only

Definition at line 990 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected

Definition at line 992 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only

Definition at line 994 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only

Definition at line 993 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected

Definition at line 995 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only

Definition at line 997 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only

Definition at line 996 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected

Definition at line 998 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only

Definition at line 1000 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only

Definition at line 999 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected

Definition at line 1001 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_DISABLE (0x00000000UL)

ADC analog watchdog monitoring disabled

Definition at line 968 of file stm32wbxx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

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STM32WB55xx HAL User Manual: Analog watchdog - Thresholds

Defines
Analog watchdog - Thresholds
ADC Exported Constants

Defines

#define | LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1 )
#define | LL_ADC_AWD_THRESHOLD_LOW ( ADC_TR1_LT1)
#define | LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR1_HT1 | ADC_TR1_LT1)

Define Documentation

#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1 )

ADC analog watchdog threshold high

Definition at line 1045 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_THRESHOLD_LOW ( ADC_TR1_LT1)

ADC analog watchdog threshold low

Definition at line 1046 of file stm32wbxx_ll_adc.h.

#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR1_HT1 | ADC_TR1_LT1)

ADC analog watchdog both thresholds high and low concatenated into the same data

Definition at line 1047 of file stm32wbxx_ll_adc.h.

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STM32WB55xx HAL User Manual: Oversampling - Oversampling scope

Defines
Oversampling - Oversampling scope
ADC Exported Constants

Defines

#define | LL_ADC_OVS_DISABLE (0x00000000UL)
#define | LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE)
#define | LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE)
#define | LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE )
#define | LL_ADC_OVS_GRP_INJ_REG_RESUMED ( ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)

Define Documentation

#define LL_ADC_OVS_DISABLE (0x00000000UL)

ADC oversampling disabled.

Definition at line 1055 of file stm32wbxx_ll_adc.h.

#define LL_ADC_OVS_GRP_INJ_REG_RESUMED ( ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)

ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset).

Definition at line 1059 of file stm32wbxx_ll_adc.h.

#define LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE )

ADC oversampling on conversions of ADC group injected.

Definition at line 1058 of file stm32wbxx_ll_adc.h.

#define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE)

ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards.

Definition at line 1056 of file stm32wbxx_ll_adc.h.

#define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE)

ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset).

Definition at line 1057 of file stm32wbxx_ll_adc.h.

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STM32WB55xx HAL User Manual: Oversampling - Discontinuous mode

Defines
Oversampling - Discontinuous mode
ADC Exported Constants

Defines

#define | LL_ADC_OVS_REG_CONT (0x00000000UL)
#define | LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS)

Define Documentation

#define LL_ADC_OVS_REG_CONT (0x00000000UL)

ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger)

Definition at line 1067 of file stm32wbxx_ll_adc.h.

#define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS)

ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger)

Definition at line 1068 of file stm32wbxx_ll_adc.h.

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STM32WB55xx HAL User Manual: Oversampling - Ratio

Defines
Oversampling - Ratio
ADC Exported Constants

Defines

#define | LL_ADC_OVS_RATIO_2 (0x00000000UL)
#define | LL_ADC_OVS_RATIO_4 ( ADC_CFGR2_OVSR_0)
#define | LL_ADC_OVS_RATIO_8 ( ADC_CFGR2_OVSR_1 )
#define | LL_ADC_OVS_RATIO_16 ( ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0)
#define | LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2 )
#define | LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0)
#define | LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 )
#define | LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0)

Define Documentation

#define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 )

ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 1082 of file stm32wbxx_ll_adc.h.

#define LL_ADC_OVS_RATIO_16 ( ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0)

ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 1079 of file stm32wbxx_ll_adc.h.

#define LL_ADC_OVS_RATIO_2 (0x00000000UL)

ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 1076 of file stm32wbxx_ll_adc.h.

#define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0)

ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 1083 of file stm32wbxx_ll_adc.h.

#define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2 )

ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 1080 of file stm32wbxx_ll_adc.h.

#define LL_ADC_OVS_RATIO_4 ( ADC_CFGR2_OVSR_0)

ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 1077 of file stm32wbxx_ll_adc.h.

#define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0)

ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 1081 of file stm32wbxx_ll_adc.h.

#define LL_ADC_OVS_RATIO_8 ( ADC_CFGR2_OVSR_1 )

ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 1078 of file stm32wbxx_ll_adc.h.

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STM32WB55xx HAL User Manual: Oversampling - Data shift

Defines
Oversampling - Data shift
ADC Exported Constants

Defines

#define | LL_ADC_OVS_SHIFT_NONE (0x00000000UL)
#define | LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 )
#define | LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 )
#define | LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 )
#define | LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 )

Define Documentation

#define LL_ADC_OVS_SHIFT_NONE (0x00000000UL)

ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data)

Definition at line 1091 of file stm32wbxx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0)

ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data)

Definition at line 1092 of file stm32wbxx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 )

ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data)

Definition at line 1093 of file stm32wbxx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)

ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data)

Definition at line 1094 of file stm32wbxx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 )

ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data)

Definition at line 1095 of file stm32wbxx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0)

ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data)

Definition at line 1096 of file stm32wbxx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 )

ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data)

Definition at line 1097 of file stm32wbxx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)

ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data)

Definition at line 1098 of file stm32wbxx_ll_adc.h.

#define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 )

ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data)

Definition at line 1099 of file stm32wbxx_ll_adc.h.

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STM32WB55xx HAL User Manual: Definitions of ADC hardware constraints delays

Defines
Definitions of ADC hardware constraints delays
ADC Exported Constants

Defines

#define | LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 10UL)
#define | LL_ADC_DELAY_VREFINT_STAB_US ( 12UL)
#define | LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL)
#define | LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL)

Detailed Description

Note:
Only ADC peripheral HW delays are defined in ADC LL driver driver, not timeout values. For details on delays values, refer to descriptions in source code above each literal definition.

Define Documentation

#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL)

Delay required between ADC end of calibration and ADC enable

Definition at line 1156 of file stm32wbxx_ll_adc.h.

#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 10UL)

Delay for ADC stabilization time (ADC voltage regulator start-up time)

Definition at line 1135 of file stm32wbxx_ll_adc.h.

Referenced by HAL_ADC_Init().

#define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL)

Delay for temperature sensor stabilization time

Definition at line 1147 of file stm32wbxx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL)

Delay for internal voltage reference stabilization time

Definition at line 1141 of file stm32wbxx_ll_adc.h.

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STM32WB55xx HAL User Manual: Common write and read registers Macros

Defines
Common write and read registers Macros
ADC Exported Macros

Defines

#define | LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in ADC register.
#define | LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in ADC register.

Define Documentation

#define LL_ADC_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in ADC register.

Parameters:
__INSTANCE__ | ADC Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 1191 of file stm32wbxx_ll_adc.h.

#define LL_ADC_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in ADC register.

Parameters:
__INSTANCE__ | ADC Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 1183 of file stm32wbxx_ll_adc.h.

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STM32WB55xx HAL User Manual: ADC helper macro

Defines
ADC helper macro
ADC Exported Macros

Defines

#define | __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)
Helper macro to get ADC channel number in decimal format from literals LL_ADC_CHANNEL_x.
#define | __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)
Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x from number in decimal format.
#define | __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
Helper macro to determine whether the selected channel corresponds to literal definitions of driver.
#define | __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
Helper macro to convert a channel defined from parameter definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), to its equivalent parameter definition of a ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
#define | __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)
Helper macro to determine whether the internal channel selected is available on the ADC instance selected.
#define | __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)
Helper macro to define ADC analog watchdog parameter: define a single channel to monitor with analog watchdog from sequencer channel and groups definition.
#define | __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
Helper macro to set the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.
#define | __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
Helper macro to get the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.
#define | __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) & LL_ADC_AWD_THRESHOLD_LOW)
Helper macro to get the ADC analog watchdog threshold high or low from raw value containing both thresholds concatenated.
#define | __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))
Helper macro to set the ADC calibration value with both single ended and differential modes calibration factors concatenated.
#define | __LL_ADC_COMMON_INSTANCE(__ADCx__) (ADC1_COMMON)
Helper macro to select the ADC common instance to which is belonging the selected ADC instance.
#define | __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) (LL_ADC_IsEnabled(ADC1))
Helper macro to check if all ADC instances sharing the same ADC common instance are disabled.
#define | __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))
Helper macro to define the ADC conversion data full-scale digital value corresponding to the selected ADC resolution.
#define | __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__)
Helper macro to convert the ADC conversion data from a resolution to another resolution.
#define | __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__, __ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value).
#define | __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate analog reference voltage (Vref+) (unit: mVolt) from ADC conversion data of internal voltage reference VrefInt.
#define | __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.
#define | __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__, __TEMPSENSOR_TYP_CALX_V__, __TEMPSENSOR_CALX_TEMP__, __VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Define Documentation

#define __LL_ADC_ANALOGWD_CHANNEL_GROUP | ( | __CHANNEL__,
 |  | __GROUP__
 | ) |
Value:
(((__GROUP__) == LL_ADC_GROUP_REGULAR)                                                                  \
   ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)                         \
   :                                                                                                      \
   ((__GROUP__) == LL_ADC_GROUP_INJECTED)                                                                 \
   ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)                        \
   :                                                                                                      \
   (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)        \
  )

Helper macro to define ADC analog watchdog parameter: define a single channel to monitor with analog watchdog from sequencer channel and groups definition.

Note:
To be used with function LL_ADC_SetAnalogWDMonitChannels(). Example: LL_ADC_SetAnalogWDMonitChannels( ADC1, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (7)
  • LL_ADC_CHANNEL_2 (7)
  • LL_ADC_CHANNEL_3 (7)
  • LL_ADC_CHANNEL_4 (7)
  • LL_ADC_CHANNEL_5 (7)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (4)
  • LL_ADC_CHANNEL_VBAT (4)
(7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
(4) For ADC channel read back from ADC register, comparison with internal channel parameter to be done using helper macro __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
__GROUP__ This parameter can be one of the following values:
  • LL_ADC_GROUP_REGULAR
  • LL_ADC_GROUP_INJECTED
  • LL_ADC_GROUP_REGULAR_INJECTED
Return values:
Returned value can be one of the following values:
  • LL_ADC_AWD_DISABLE
  • LL_ADC_AWD_ALL_CHANNELS_REG (0)
  • LL_ADC_AWD_ALL_CHANNELS_INJ (0)
  • LL_ADC_AWD_ALL_CHANNELS_REG_INJ
  • LL_ADC_AWD_CHANNEL_0_REG (0)
  • LL_ADC_AWD_CHANNEL_0_INJ (0)
  • LL_ADC_AWD_CHANNEL_0_REG_INJ
  • LL_ADC_AWD_CHANNEL_1_REG (0)
  • LL_ADC_AWD_CHANNEL_1_INJ (0)
  • LL_ADC_AWD_CHANNEL_1_REG_INJ
  • LL_ADC_AWD_CHANNEL_2_REG (0)
  • LL_ADC_AWD_CHANNEL_2_INJ (0)
  • LL_ADC_AWD_CHANNEL_2_REG_INJ
  • LL_ADC_AWD_CHANNEL_3_REG (0)
  • LL_ADC_AWD_CHANNEL_3_INJ (0)
  • LL_ADC_AWD_CHANNEL_3_REG_INJ
  • LL_ADC_AWD_CHANNEL_4_REG (0)
  • LL_ADC_AWD_CHANNEL_4_INJ (0)
  • LL_ADC_AWD_CHANNEL_4_REG_INJ
  • LL_ADC_AWD_CHANNEL_5_REG (0)
  • LL_ADC_AWD_CHANNEL_5_INJ (0)
  • LL_ADC_AWD_CHANNEL_5_REG_INJ
  • LL_ADC_AWD_CHANNEL_6_REG (0)
  • LL_ADC_AWD_CHANNEL_6_INJ (0)
  • LL_ADC_AWD_CHANNEL_6_REG_INJ
  • LL_ADC_AWD_CHANNEL_7_REG (0)
  • LL_ADC_AWD_CHANNEL_7_INJ (0)
  • LL_ADC_AWD_CHANNEL_7_REG_INJ
  • LL_ADC_AWD_CHANNEL_8_REG (0)
  • LL_ADC_AWD_CHANNEL_8_INJ (0)
  • LL_ADC_AWD_CHANNEL_8_REG_INJ
  • LL_ADC_AWD_CHANNEL_9_REG (0)
  • LL_ADC_AWD_CHANNEL_9_INJ (0)
  • LL_ADC_AWD_CHANNEL_9_REG_INJ
  • LL_ADC_AWD_CHANNEL_10_REG (0)
  • LL_ADC_AWD_CHANNEL_10_INJ (0)
  • LL_ADC_AWD_CHANNEL_10_REG_INJ
  • LL_ADC_AWD_CHANNEL_11_REG (0)
  • LL_ADC_AWD_CHANNEL_11_INJ (0)
  • LL_ADC_AWD_CHANNEL_11_REG_INJ
  • LL_ADC_AWD_CHANNEL_12_REG (0)
  • LL_ADC_AWD_CHANNEL_12_INJ (0)
  • LL_ADC_AWD_CHANNEL_12_REG_INJ
  • LL_ADC_AWD_CHANNEL_13_REG (0)
  • LL_ADC_AWD_CHANNEL_13_INJ (0)
  • LL_ADC_AWD_CHANNEL_13_REG_INJ
  • LL_ADC_AWD_CHANNEL_14_REG (0)
  • LL_ADC_AWD_CHANNEL_14_INJ (0)
  • LL_ADC_AWD_CHANNEL_14_REG_INJ
  • LL_ADC_AWD_CHANNEL_15_REG (0)
  • LL_ADC_AWD_CHANNEL_15_INJ (0)
  • LL_ADC_AWD_CHANNEL_15_REG_INJ
  • LL_ADC_AWD_CHANNEL_16_REG (0)
  • LL_ADC_AWD_CHANNEL_16_INJ (0)
  • LL_ADC_AWD_CHANNEL_16_REG_INJ
  • LL_ADC_AWD_CHANNEL_17_REG (0)
  • LL_ADC_AWD_CHANNEL_17_INJ (0)
  • LL_ADC_AWD_CHANNEL_17_REG_INJ
  • LL_ADC_AWD_CHANNEL_18_REG (0)
  • LL_ADC_AWD_CHANNEL_18_INJ (0)
  • LL_ADC_AWD_CHANNEL_18_REG_INJ
  • LL_ADC_AWD_CH_VREFINT_REG (0)
  • LL_ADC_AWD_CH_VREFINT_INJ (0)
  • LL_ADC_AWD_CH_VREFINT_REG_INJ
  • LL_ADC_AWD_CH_TEMPSENSOR_REG (0)
  • LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)
  • LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ
  • LL_ADC_AWD_CH_VBAT_REG (0)
  • LL_ADC_AWD_CH_VBAT_INJ (0)
  • LL_ADC_AWD_CH_VBAT_REG_INJ
(0) On STM32WB, parameter available only on analog watchdog number: AWD1.

Definition at line 1556 of file stm32wbxx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION | ( | __ADC_RESOLUTION__,
 |  | __AWD_THRESHOLD_12_BITS__
 | ) | ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))

Helper macro to get the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.

Note:
To be used with function LL_ADC_GetAnalogWDThresholds(). Example, with a ADC resolution of 8 bits, to get the value of analog watchdog threshold high (on 8 bits): < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION (LL_ADC_RESOLUTION_8B, LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH) );
Parameters:
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
__AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 1608 of file stm32wbxx_ll_adc.h.

#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION | ( | __ADC_RESOLUTION__,
 |  | __AWD_THRESHOLD__
 | ) | ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))

Helper macro to set the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.

Note:
To be used with function LL_ADC_ConfigAnalogWDThresholds() or LL_ADC_SetAnalogWDThresholds(). Example, with a ADC resolution of 8 bits, to set the value of analog watchdog threshold high (on 8 bits): LL_ADC_SetAnalogWDThresholds (< ADCx param >, __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>) );
Parameters:
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
__AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 1586 of file stm32wbxx_ll_adc.h.

#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW | ( | __AWD_THRESHOLD_TYPE__,
 |  | __AWD_THRESHOLDS__
 | ) | (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) & LL_ADC_AWD_THRESHOLD_LOW)

Helper macro to get the ADC analog watchdog threshold high or low from raw value containing both thresholds concatenated.

Note:
To be used with function LL_ADC_GetAnalogWDThresholds(). Example, to get analog watchdog threshold high from the register raw value: __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
Parameters:
__AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
  • LL_ADC_AWD_THRESHOLD_HIGH
  • LL_ADC_AWD_THRESHOLD_LOW
__AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 1623 of file stm32wbxx_ll_adc.h.

#define __LL_ADC_CALC_DATA_TO_VOLTAGE | ( | __VREFANALOG_VOLTAGE__,
 |  | __ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__)                                   \
   / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                                \
  )

Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value).

Note:
Analog reference voltage (Vref+) must be either known from user board environment or can be calculated using ADC measurement and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
Parameters:
__VREFANALOG_VOLTAGE__ | Analog reference voltage (unit: mV)
__ADC_DATA__ | ADC conversion data (resolution 12 bits) (unit: digital value).
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
Return values:
ADC conversion data equivalent voltage value (unit: mVolt)

Definition at line 1752 of file stm32wbxx_ll_adc.h.

#define __LL_ADC_CALC_TEMPERATURE | ( | __VREFANALOG_VOLTAGE__,
 |  | __TEMPSENSOR_ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
(((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__),     \
                                                    (__ADC_RESOLUTION__),          \
                                                    LL_ADC_RESOLUTION_12B)         \
                   * (__VREFANALOG_VOLTAGE__))                                     \
                  / TEMPSENSOR_CAL_VREFANALOG)                                     \
        - (int32_t) *TEMPSENSOR_CAL1_ADDR)                                         \
     ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP)                    \
    ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
   ) + TEMPSENSOR_CAL1_TEMP                                                        \
  )

Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Note:
Computation is using temperature sensor calibration values stored in system memory for each device during production.
Calculation formula: Temperature = ((TS_ADC_DATA - TS_CAL1) * (TS_CAL2_TEMP - TS_CAL1_TEMP)) / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP with TS_ADC_DATA = temperature sensor raw data measured by ADC Avg_Slope = (TS_CAL2 - TS_CAL1) / (TS_CAL2_TEMP - TS_CAL1_TEMP) TS_CAL1 = equivalent TS_ADC_DATA at temperature TEMP_DEGC_CAL1 (calibrated in factory) TS_CAL2 = equivalent TS_ADC_DATA at temperature TEMP_DEGC_CAL2 (calibrated in factory) Caution: Calculation relevancy under reserve that calibration parameters are correct (address and data). To calculate temperature using temperature sensor datasheet typical values (generic values less, therefore less accurate than calibrated values), use helper macro __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
As calculation input, the analog reference voltage (Vref+) must be defined as it impacts the ADC LSB equivalent voltage.
Analog reference voltage (Vref+) must be either known from user board environment or can be calculated using ADC measurement and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
On this STM32 serie, calibration data of temperature sensor corresponds to a resolution of 12 bits, this is the recommended ADC resolution to convert voltage of temperature sensor. Otherwise, this macro performs the processing to scale ADC conversion data to 12 bits.
Parameters:
__VREFANALOG_VOLTAGE__ | Analog reference voltage (unit: mV)
__TEMPSENSOR_ADC_DATA__ | ADC conversion data of internal temperature sensor (unit: digital value).
__ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
Return values:
Temperature (unit: degree Celsius)

Definition at line 1836 of file stm32wbxx_ll_adc.h.

#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS | ( | __TEMPSENSOR_TYP_AVGSLOPE__,
 |  | __TEMPSENSOR_TYP_CALX_V__,
 |  | __TEMPSENSOR_CALX_TEMP__,
 |  | __VREFANALOG_VOLTAGE__,
 |  | __TEMPSENSOR_ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
((( (                                                                        \
       (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__))       \
                  / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))                \
                 * 1000UL)                                                     \
       -                                                                       \
       (int32_t)(((__TEMPSENSOR_TYP_CALX_V__))                                 \
                 * 1000UL)                                                     \
      )                                                                        \
    ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__)                                 \
   ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__)                                     \
  )

Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Note:
Computation is using temperature sensor typical values (refer to device datasheet).
Calculation formula: Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) / Avg_Slope + CALx_TEMP with TS_ADC_DATA = temperature sensor raw data measured by ADC (unit: digital value) Avg_Slope = temperature sensor slope (unit: uV/Degree Celsius) TS_TYP_CALx_VOLT = temperature sensor digital value at temperature CALx_TEMP (unit: mV) Caution: Calculation relevancy under reserve the temperature sensor of the current device has characteristics in line with datasheet typical values. If temperature sensor calibration values are available on on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), temperature calculation will be more accurate using helper macro __LL_ADC_CALC_TEMPERATURE().
As calculation input, the analog reference voltage (Vref+) must be defined as it impacts the ADC LSB equivalent voltage.
Analog reference voltage (Vref+) must be either known from user board environment or can be calculated using ADC measurement and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
ADC measurement data must correspond to a resolution of 12 bits (full scale digital value 4095). If not the case, the data must be preliminarily rescaled to an equivalent resolution of 12 bits.
Parameters:
__TEMPSENSOR_TYP_AVGSLOPE__ | Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). On STM32WB, refer to device datasheet parameter "Avg_Slope".
__TEMPSENSOR_TYP_CALX_V__ | Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). On STM32WB, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
__TEMPSENSOR_CALX_TEMP__ | Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
__VREFANALOG_VOLTAGE__ | Analog voltage reference (Vref+) voltage (unit: mV)
__TEMPSENSOR_ADC_DATA__ | ADC conversion data of internal temperature sensor (unit: digital value).
__ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
Return values:
Temperature (unit: degree Celsius)

Definition at line 1894 of file stm32wbxx_ll_adc.h.

#define __LL_ADC_CALC_VREFANALOG_VOLTAGE | ( | __VREFINT_ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
(((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF)                          \
   / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__),                  \
                                      (__ADC_RESOLUTION__),                    \
                                      LL_ADC_RESOLUTION_12B))

Helper macro to calculate analog reference voltage (Vref+) (unit: mVolt) from ADC conversion data of internal voltage reference VrefInt.

Note:
Computation is using VrefInt calibration value stored in system memory for each device during production.
This voltage depends on user board environment: voltage level connected to pin Vref+. On devices with small package, the pin Vref+ is not present and internally bonded to pin Vdda.
On this STM32 serie, calibration data of internal voltage reference VrefInt corresponds to a resolution of 12 bits, this is the recommended ADC resolution to convert voltage of internal voltage reference VrefInt. Otherwise, this macro performs the processing to scale ADC conversion data to 12 bits.
Parameters:
__VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) of internal voltage reference VrefInt (unit: digital value).
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
Return values:
Analog reference voltage (unit: mV)

Definition at line 1784 of file stm32wbxx_ll_adc.h.

#define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF | ( | __CALIB_FACTOR_SINGLE_ENDED__,
 |  | __CALIB_FACTOR_DIFFERENTIAL__
 | ) | (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))

Helper macro to set the ADC calibration value with both single ended and differential modes calibration factors concatenated.

Note:
To be used with function LL_ADC_SetCalibrationFactor(). Example, to set calibration factors single ended to 0x55 and differential ended to 0x2A: LL_ADC_SetCalibrationFactor( ADC1, __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
Parameters:
__CALIB_FACTOR_SINGLE_ENDED__ | Value between Min_Data=0x00 and Max_Data=0x7F
__CALIB_FACTOR_DIFFERENTIAL__ | Value between Min_Data=0x00 and Max_Data=0x7F
Return values:
Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

Definition at line 1639 of file stm32wbxx_ll_adc.h.

#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL ( __CHANNEL__ ) ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)

Helper macro to convert a channel defined from parameter definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), to its equivalent parameter definition of a ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).

Note:
The channel parameter can be, additionally to a value defined from parameter definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), a value defined from parameter definition of ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) or a value from functions where a channel number is returned from ADC registers.
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (7)
  • LL_ADC_CHANNEL_2 (7)
  • LL_ADC_CHANNEL_3 (7)
  • LL_ADC_CHANNEL_4 (7)
  • LL_ADC_CHANNEL_5 (7)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT
  • LL_ADC_CHANNEL_TEMPSENSOR
  • LL_ADC_CHANNEL_VBAT
(7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
Return values:
Returned value can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18

Definition at line 1409 of file stm32wbxx_ll_adc.h.

#define __LL_ADC_CHANNEL_TO_DECIMAL_NB ( __CHANNEL__ )
Value:
((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL)                                 \
   ? (                                                                                     \
       ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
     )                                                                                     \
   :                                                                                       \
   (                                                                                       \
       (uint32_t)POSITION_VAL((__CHANNEL__))                                               \
   )                                                                                       \
  )

Helper macro to get ADC channel number in decimal format from literals LL_ADC_CHANNEL_x.

Note:
Example: __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4) will return decimal number "4".
The input can be a value from functions where a channel number is returned, either defined with number or with bitfield (only one bit must be set).
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (7)
  • LL_ADC_CHANNEL_2 (7)
  • LL_ADC_CHANNEL_3 (7)
  • LL_ADC_CHANNEL_4 (7)
  • LL_ADC_CHANNEL_5 (7)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT
  • LL_ADC_CHANNEL_TEMPSENSOR
  • LL_ADC_CHANNEL_VBAT
(7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
Return values:
Value between Min_Data=0 and Max_Data=18

Definition at line 1237 of file stm32wbxx_ll_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADCEx_InjectedConfigChannel(), and LL_ADC_GetAnalogWDMonitChannels().

#define __LL_ADC_COMMON_INSTANCE ( __ADCx__ ) (ADC1_COMMON)

Helper macro to select the ADC common instance to which is belonging the selected ADC instance.

Note:
ADC common register instance can be used for:
  • Set parameters common to several ADC instances
  • Multimode (for devices with several ADC instances) Refer to functions having argument "ADCxy_COMMON" as parameter.
Parameters:
__ADCx__ ADC instance
Return values:
ADC common register instance

Definition at line 1659 of file stm32wbxx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), HAL_ADC_DeInit(), HAL_ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

#define __LL_ADC_CONVERT_DATA_RESOLUTION | ( | __DATA__,
 |  | __ADC_RESOLUTION_CURRENT__,
 |  | __ADC_RESOLUTION_TARGET__
 | ) |
Value:
(((__DATA__)                                                                 \
    << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))   \
   >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))      \
  )

Helper macro to convert the ADC conversion data from a resolution to another resolution.

Parameters:
__DATA__ ADC conversion data to be converted
__ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
__ADC_RESOLUTION_TARGET__ Resolution of the data after conversion This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
Return values:
ADC conversion data to the requested resolution

Definition at line 1728 of file stm32wbxx_ll_adc.h.

#define __LL_ADC_DECIMAL_NB_TO_CHANNEL ( __DECIMAL_NB__ )
Value:
(((__DECIMAL_NB__) <= 9UL)                                                                            \
   ? (                                                                                                  \
       ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                             |          \
       (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                             |          \
       (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))           \
     )                                                                                                  \
   :                                                                                                    \
   (                                                                                                    \
       ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                      | \
       (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                                      | \
       (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))  \
   )                                                                                                    \
  )

Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x from number in decimal format.

Note:
Example: __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) will return a data equivalent to "LL_ADC_CHANNEL_4".
Parameters:
__DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
Return values:
Returned value can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (7)
  • LL_ADC_CHANNEL_2 (7)
  • LL_ADC_CHANNEL_3 (7)
  • LL_ADC_CHANNEL_4 (7)
  • LL_ADC_CHANNEL_5 (7)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (4)
  • LL_ADC_CHANNEL_VBAT (4)
(7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
(4) For ADC channel read back from ADC register, comparison with internal channel parameter to be done using helper macro __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

Definition at line 1285 of file stm32wbxx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define __LL_ADC_DIGITAL_SCALE ( __ADC_RESOLUTION__ ) (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))

Helper macro to define the ADC conversion data full-scale digital value corresponding to the selected ADC resolution.

Note:
ADC conversion data full-scale corresponds to voltage range determined by analog voltage references Vref+ and Vref- (refer to reference manual).
Parameters:
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
Return values:
ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)

Definition at line 1707 of file stm32wbxx_ll_adc.h.

#define __LL_ADC_IS_CHANNEL_INTERNAL ( __CHANNEL__ ) (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)

Helper macro to determine whether the selected channel corresponds to literal definitions of driver.

Note:
The different literal definitions of ADC channels are:
  • ADC internal channel: LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
  • ADC external channel (channel connected to a GPIO pin): LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
The channel parameter must be a value defined from literal definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...), must not be a value from functions where a channel number is returned from ADC registers, because internal and external channels share the same channel number in ADC registers. The differentiation is made only with parameters definitions of driver.
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (7)
  • LL_ADC_CHANNEL_2 (7)
  • LL_ADC_CHANNEL_3 (7)
  • LL_ADC_CHANNEL_4 (7)
  • LL_ADC_CHANNEL_5 (7)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT
  • LL_ADC_CHANNEL_TEMPSENSOR
  • LL_ADC_CHANNEL_VBAT
(7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
Return values:
Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.

Definition at line 1346 of file stm32wbxx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE | ( | __ADC_INSTANCE__,
 |  | __CHANNEL__
 | ) |
Value:
(                                                                            \
    ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                            \
    ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) ||                            \
    ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)                                     \
  )

Helper macro to determine whether the internal channel selected is available on the ADC instance selected.

Note:
The channel parameter must be a value defined from parameter definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), must not be a value defined from parameter definition of ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) or a value from functions where a channel number is returned from ADC registers, because internal and external channels share the same channel number in ADC registers. The differentiation is made only with parameters definitions of driver.
Parameters:
__ADC_INSTANCE__ ADC instance
__CHANNEL__ This parameter can be one of the following values:
  • LL_ADC_CHANNEL_VREFINT
  • LL_ADC_CHANNEL_TEMPSENSOR
  • LL_ADC_CHANNEL_VBAT
Return values:
Value "0" if the internal channel selected is not available on the ADC instance selected. Value "1" if the internal channel selected is available on the ADC instance selected.

Definition at line 1433 of file stm32wbxx_ll_adc.h.

#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE ( __ADCXY_COMMON__ ) (LL_ADC_IsEnabled(ADC1))

Helper macro to check if all ADC instances sharing the same ADC common instance are disabled.

Note:
This check is required by functions with setting conditioned to ADC state: All ADC instances of the ADC common group must be disabled. Refer to functions having argument "ADCxy_COMMON" as parameter.
On devices with only 1 ADC common instance, parameter of this macro is useless and can be ignored (parameter kept for compatibility with devices featuring several ADC common instances).
Parameters:
__ADCXY_COMMON__ ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
Value "0" if all ADC instances sharing the same ADC common instance are disabled. Value "1" if at least one ADC instance sharing the same ADC common instance is enabled.

Definition at line 1690 of file stm32wbxx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), HAL_ADC_DeInit(), HAL_ADC_Init(), HAL_ADCEx_InjectedConfigChannel(), and LL_ADC_CommonInit().

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC DMA management

Functions
ADC DMA management
ADC Exported Functions

Functions

__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr (ADC_TypeDef *ADCx, uint32_t Register)
Function to help to configure DMA transfer from ADC: retrieve the ADC register address from ADC instance and a list of ADC registers intended to be used (most commonly) with DMA transfer.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Register
 | ) |  |

Function to help to configure DMA transfer from ADC: retrieve the ADC register address from ADC instance and a list of ADC registers intended to be used (most commonly) with DMA transfer.

Note:
These ADC registers are data registers: when ADC conversion data is available in ADC data registers, ADC generates a DMA transfer request.
This macro is intended to be used with LL DMA driver, refer to function "LL_DMA_ConfigAddresses()". Example: LL_DMA_ConfigAddresses(DMA1, LL_DMA_CHANNEL_1, LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA), (uint32_t)&< array or variable >, LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
For devices with several ADC: in multimode, some devices use a different data register outside of ADC instance scope (common data register). This macro manages this register difference, only ADC instance has to be set as parameter.
Reference Manual to LL API cross reference:
DR DATA LL_ADC_DMA_GetRegAddr
Parameters:
ADCx ADC instance
Register This parameter can be one of the following values:
  • LL_ADC_DMA_REG_REGULAR_DATA
Return values:
ADC register address

Definition at line 1958 of file stm32wbxx_ll_adc.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Configuration of ADC hierarchical scope: common to several ADC instances

Functions
Configuration of ADC hierarchical scope: common to several ADC instances
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_SetCommonClock (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
Set parameter common to several ADC: Clock source and prescaler.
__STATIC_INLINE uint32_t | LL_ADC_GetCommonClock (ADC_Common_TypeDef *ADCxy_COMMON)
Get parameter common to several ADC: Clock source and prescaler.
__STATIC_INLINE void | LL_ADC_SetCommonPathInternalCh (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
Set parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).
__STATIC_INLINE uint32_t | LL_ADC_GetCommonPathInternalCh (ADC_Common_TypeDef *ADCxy_COMMON)
Get parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_GetCommonClock ( ADC_Common_TypeDef * ADCxy_COMMON )

Get parameter common to several ADC: Clock source and prescaler.

Reference Manual to LL API cross reference:
CCR CKMODE LL_ADC_GetCommonClock
CCR PRESC LL_ADC_GetCommonClock
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
Returned value can be one of the following values:
  • LL_ADC_CLOCK_SYNC_PCLK_DIV1
  • LL_ADC_CLOCK_SYNC_PCLK_DIV2
  • LL_ADC_CLOCK_SYNC_PCLK_DIV4
  • LL_ADC_CLOCK_ASYNC_DIV1
  • LL_ADC_CLOCK_ASYNC_DIV2
  • LL_ADC_CLOCK_ASYNC_DIV4
  • LL_ADC_CLOCK_ASYNC_DIV6
  • LL_ADC_CLOCK_ASYNC_DIV8
  • LL_ADC_CLOCK_ASYNC_DIV10
  • LL_ADC_CLOCK_ASYNC_DIV12
  • LL_ADC_CLOCK_ASYNC_DIV16
  • LL_ADC_CLOCK_ASYNC_DIV32
  • LL_ADC_CLOCK_ASYNC_DIV64
  • LL_ADC_CLOCK_ASYNC_DIV128
  • LL_ADC_CLOCK_ASYNC_DIV256

Definition at line 2041 of file stm32wbxx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh ( ADC_Common_TypeDef * ADCxy_COMMON )

Get parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).

Note:
One or several values can be selected. Example: (LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_PATH_INTERNAL_TEMPSENSOR)
Reference Manual to LL API cross reference:
CCR VREFEN LL_ADC_GetCommonPathInternalCh
CCR TSEN LL_ADC_GetCommonPathInternalCh
CCR VBATEN LL_ADC_GetCommonPathInternalCh
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
Returned value can be a combination of the following values:
  • LL_ADC_PATH_INTERNAL_NONE
  • LL_ADC_PATH_INTERNAL_VREFINT
  • LL_ADC_PATH_INTERNAL_TEMPSENSOR
  • LL_ADC_PATH_INTERNAL_VBAT

Definition at line 2103 of file stm32wbxx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

__STATIC_INLINE void LL_ADC_SetCommonClock | ( | ADC_Common_TypeDef * | ADCxy_COMMON,
 |  | uint32_t | CommonClock
 | ) |  |

Set parameter common to several ADC: Clock source and prescaler.

Note:
ADC clock source and prescaler must be selected in function of system clock to not exceed ADC maximum frequency, depending on devices. Example: STM32WB55xx ADC maximum frequency is 64MHz (corresponding to 4.27Msmp/s maximum) Example: STM32WB50xx ADC maximum frequency is 32MHz (corresponding to 2.13Msmp/s maximum) For ADC maximum frequency, refer to datasheet of the selected device.
On this STM32 serie, if ADC group injected is used, some clock ratio constraints between ADC clock and AHB clock must be respected. Refer to reference manual.
On this STM32 serie, setting of this feature is conditioned to ADC state: All ADC instances of the ADC common group must be disabled. This check can be done with function LL_ADC_IsEnabled() for each ADC instance or by using helper macro helper macro __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
Reference Manual to LL API cross reference:
CCR CKMODE LL_ADC_SetCommonClock
CCR PRESC LL_ADC_SetCommonClock
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
CommonClock This parameter can be one of the following values:
  • LL_ADC_CLOCK_SYNC_PCLK_DIV1
  • LL_ADC_CLOCK_SYNC_PCLK_DIV2
  • LL_ADC_CLOCK_SYNC_PCLK_DIV4
  • LL_ADC_CLOCK_ASYNC_DIV1
  • LL_ADC_CLOCK_ASYNC_DIV2
  • LL_ADC_CLOCK_ASYNC_DIV4
  • LL_ADC_CLOCK_ASYNC_DIV6
  • LL_ADC_CLOCK_ASYNC_DIV8
  • LL_ADC_CLOCK_ASYNC_DIV10
  • LL_ADC_CLOCK_ASYNC_DIV12
  • LL_ADC_CLOCK_ASYNC_DIV16
  • LL_ADC_CLOCK_ASYNC_DIV32
  • LL_ADC_CLOCK_ASYNC_DIV64
  • LL_ADC_CLOCK_ASYNC_DIV128
  • LL_ADC_CLOCK_ASYNC_DIV256
Return values:
None

Definition at line 2013 of file stm32wbxx_ll_adc.h.

Referenced by HAL_ADC_Init(), and LL_ADC_CommonInit().

__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh | ( | ADC_Common_TypeDef * | ADCxy_COMMON,
 |  | uint32_t | PathInternal
 | ) |  |

Set parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).

Note:
One or several values can be selected. Example: (LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_PATH_INTERNAL_TEMPSENSOR)
Stabilization time of measurement path to internal channel: After enabling internal paths, before starting ADC conversion, a delay is required for internal voltage reference and temperature sensor stabilization time. Refer to device datasheet. Refer to literal LL_ADC_DELAY_VREFINT_STAB_US. Refer to literal LL_ADC_DELAY_TEMPSENSOR_STAB_US.
ADC internal channel sampling time constraint: For ADC conversion of internal channels, a sampling time minimum value is required. Refer to device datasheet.
On this STM32 serie, setting of this feature is conditioned to ADC state: All ADC instances of the ADC common group must be disabled. This check can be done with function LL_ADC_IsEnabled() for each ADC instance or by using helper macro helper macro __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
Reference Manual to LL API cross reference:
CCR VREFEN LL_ADC_SetCommonPathInternalCh
CCR TSEN LL_ADC_SetCommonPathInternalCh
CCR VBATEN LL_ADC_SetCommonPathInternalCh
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
PathInternal This parameter can be a combination of the following values:
  • LL_ADC_PATH_INTERNAL_NONE
  • LL_ADC_PATH_INTERNAL_VREFINT
  • LL_ADC_PATH_INTERNAL_TEMPSENSOR
  • LL_ADC_PATH_INTERNAL_VBAT
Return values:
None

Definition at line 2081 of file stm32wbxx_ll_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Configuration of ADC hierarchical scope: ADC instance

Functions
Configuration of ADC hierarchical scope: ADC instance
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_SetCalibrationFactor (ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
Set ADC calibration factor in the mode single-ended or differential (for devices with differential mode available).
__STATIC_INLINE uint32_t | LL_ADC_GetCalibrationFactor (ADC_TypeDef *ADCx, uint32_t SingleDiff)
Get ADC calibration factor in the mode single-ended or differential (for devices with differential mode available).
__STATIC_INLINE void | LL_ADC_SetResolution (ADC_TypeDef *ADCx, uint32_t Resolution)
Set ADC resolution.
__STATIC_INLINE uint32_t | LL_ADC_GetResolution (ADC_TypeDef *ADCx)
Get ADC resolution.
__STATIC_INLINE void | LL_ADC_SetDataAlignment (ADC_TypeDef *ADCx, uint32_t DataAlignment)
Set ADC conversion data alignment.
__STATIC_INLINE uint32_t | LL_ADC_GetDataAlignment (ADC_TypeDef *ADCx)
Get ADC conversion data alignment.
__STATIC_INLINE void | LL_ADC_SetLowPowerMode (ADC_TypeDef *ADCx, uint32_t LowPowerMode)
Set ADC low power mode.
__STATIC_INLINE uint32_t | LL_ADC_GetLowPowerMode (ADC_TypeDef *ADCx)
Get ADC low power mode:
__STATIC_INLINE void | LL_ADC_SetOffset (ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
Set ADC selected offset number 1, 2, 3 or 4.
__STATIC_INLINE uint32_t | LL_ADC_GetOffsetChannel (ADC_TypeDef *ADCx, uint32_t Offsety)
Get for the ADC selected offset number 1, 2, 3 or 4: Channel to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)
__STATIC_INLINE uint32_t | LL_ADC_GetOffsetLevel (ADC_TypeDef *ADCx, uint32_t Offsety)
Get for the ADC selected offset number 1, 2, 3 or 4: Offset level (offset to be subtracted from the raw converted data).
__STATIC_INLINE void | LL_ADC_SetOffsetState (ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
Set for the ADC selected offset number 1, 2, 3 or 4: force offset state disable or enable without modifying offset channel or offset value.
__STATIC_INLINE uint32_t | LL_ADC_GetOffsetState (ADC_TypeDef *ADCx, uint32_t Offsety)
Get for the ADC selected offset number 1, 2, 3 or 4: offset state disabled or enabled.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SingleDiff
 | ) |  |

Get ADC calibration factor in the mode single-ended or differential (for devices with differential mode available).

Note:
Calibration factors are set by hardware after performing a calibration run using function LL_ADC_StartCalibration().
For devices with differential mode available: Calibration of offset is specific to each of single-ended and differential modes
Reference Manual to LL API cross reference:
CALFACT CALFACT_S LL_ADC_GetCalibrationFactor
CALFACT CALFACT_D LL_ADC_GetCalibrationFactor
Parameters:
ADCx ADC instance
SingleDiff This parameter can be one of the following values:
  • LL_ADC_SINGLE_ENDED
  • LL_ADC_DIFFERENTIAL_ENDED
Return values:
Value between Min_Data=0x00 and Max_Data=0x7F

Definition at line 2170 of file stm32wbxx_ll_adc.h.

References ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK, ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4, and ADC_SINGLEDIFF_CALIB_FACTOR_MASK.

Referenced by HAL_ADCEx_Calibration_GetValue().

__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment ( ADC_TypeDef * ADCx )

Get ADC conversion data alignment.

Note:
Refer to reference manual for alignments formats dependencies to ADC resolutions.
Reference Manual to LL API cross reference:
CFGR ALIGN LL_ADC_GetDataAlignment
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_DATA_ALIGN_RIGHT
  • LL_ADC_DATA_ALIGN_LEFT

Definition at line 2248 of file stm32wbxx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode ( ADC_TypeDef * ADCx )

Get ADC low power mode:

Note:
Description of ADC low power modes:
  • ADC low power mode "auto wait": Dynamic low power mode, ADC conversions occurrences are limited to the minimum necessary in order to reduce power consumption. New ADC conversion starts only when the previous unitary conversion data (for ADC group regular) or previous sequence conversions data (for ADC group injected) has been retrieved by user software. In the meantime, ADC remains idle: does not performs any other conversion. This mode allows to automatically adapt the ADC conversions triggers to the speed of the software that reads the data. Moreover, this avoids risk of overrun for low frequency applications. How to use this low power mode:
    • Do not use with interruption or DMA since these modes have to clear immediately the EOC flag to free the IRQ vector sequencer.
    • Do use with polling: 1. Start conversion, 2. Later on, when conversion data is needed: poll for end of conversion to ensure that conversion is completed and retrieve ADC conversion data. This will trig another ADC conversion start.
  • ADC low power mode "auto power-off" (feature available on this device if parameter LL_ADC_LP_AUTOPOWEROFF is available): the ADC automatically powers-off after a conversion and automatically wakes up when a new conversion is triggered (with startup time between trigger and start of sampling). This feature can be combined with low power mode "auto wait".
With ADC low power mode "auto wait", the ADC conversion data read is corresponding to previous ADC conversion start, independently of delay during which ADC was idle. Therefore, the ADC conversion data may be outdated: does not correspond to the current voltage level on the selected ADC channel.
Reference Manual to LL API cross reference:
CFGR AUTDLY LL_ADC_GetLowPowerMode
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_LP_MODE_NONE
  • LL_ADC_LP_AUTOWAIT

Definition at line 2349 of file stm32wbxx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Offsety
 | ) |  |

Get for the ADC selected offset number 1, 2, 3 or 4: Channel to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)

Note:
Usage of the returned channel number:
  • To reinject this channel into another function LL_ADC_xxx: the returned channel number is only partly formatted on definition of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared with parts of literals LL_ADC_CHANNEL_x or using helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB(). Then the selected literal LL_ADC_CHANNEL_x can be used as parameter for another function.
  • To get the channel number in decimal format: process the returned value with the helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB().
On STM32WB, some fast channels are available: fast analog inputs coming from GPIO pads (ADC_IN1..5).
Reference Manual to LL API cross reference:
OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel
OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel
OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel
OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel
Parameters:
ADCx ADC instance
Offsety This parameter can be one of the following values:
  • LL_ADC_OFFSET_1
  • LL_ADC_OFFSET_2
  • LL_ADC_OFFSET_3
  • LL_ADC_OFFSET_4
Return values:
Returned value can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (7)
  • LL_ADC_CHANNEL_2 (7)
  • LL_ADC_CHANNEL_3 (7)
  • LL_ADC_CHANNEL_4 (7)
  • LL_ADC_CHANNEL_5 (7)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (4)
  • LL_ADC_CHANNEL_VBAT (4)
(7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
(4) For ADC channel read back from ADC register, comparison with internal channel parameter to be done using helper macro __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

Definition at line 2489 of file stm32wbxx_ll_adc.h.

References __ADC_PTR_REG_OFFSET.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Offsety
 | ) |  |

Get for the ADC selected offset number 1, 2, 3 or 4: Offset level (offset to be subtracted from the raw converted data).

Note:
Caution: Offset format is dependent to ADC resolution: offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0.
Reference Manual to LL API cross reference:
OFR1 OFFSET1 LL_ADC_GetOffsetLevel
OFR2 OFFSET2 LL_ADC_GetOffsetLevel
OFR3 OFFSET3 LL_ADC_GetOffsetLevel
OFR4 OFFSET4 LL_ADC_GetOffsetLevel
Parameters:
ADCx ADC instance
Offsety This parameter can be one of the following values:
  • LL_ADC_OFFSET_1
  • LL_ADC_OFFSET_2
  • LL_ADC_OFFSET_3
  • LL_ADC_OFFSET_4
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 2515 of file stm32wbxx_ll_adc.h.

References __ADC_PTR_REG_OFFSET.

__STATIC_INLINE uint32_t LL_ADC_GetOffsetState | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Offsety
 | ) |  |

Get for the ADC selected offset number 1, 2, 3 or 4: offset state disabled or enabled.

Reference Manual to LL API cross reference:
OFR1 OFFSET1_EN LL_ADC_GetOffsetState
OFR2 OFFSET2_EN LL_ADC_GetOffsetState
OFR3 OFFSET3_EN LL_ADC_GetOffsetState
OFR4 OFFSET4_EN LL_ADC_GetOffsetState
Parameters:
ADCx ADC instance
Offsety This parameter can be one of the following values:
  • LL_ADC_OFFSET_1
  • LL_ADC_OFFSET_2
  • LL_ADC_OFFSET_3
  • LL_ADC_OFFSET_4
Return values:
Returned value can be one of the following values:
  • LL_ADC_OFFSET_DISABLE
  • LL_ADC_OFFSET_ENABLE

Definition at line 2574 of file stm32wbxx_ll_adc.h.

References __ADC_PTR_REG_OFFSET.

__STATIC_INLINE uint32_t LL_ADC_GetResolution ( ADC_TypeDef * ADCx )

Get ADC resolution.

Refer to reference manual for alignments formats dependencies to ADC resolutions.

Reference Manual to LL API cross reference:
CFGR RES LL_ADC_GetResolution
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B

Definition at line 2213 of file stm32wbxx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetCalibrationFactor | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SingleDiff,
 |  | uint32_t | CalibrationFactor
 | ) |  |

Set ADC calibration factor in the mode single-ended or differential (for devices with differential mode available).

Note:
This function is intended to set calibration parameters without having to perform a new calibration using LL_ADC_StartCalibration().
For devices with differential mode available: Calibration of offset is specific to each of single-ended and differential modes (calibration factor must be specified for each of these differential modes, if used afterwards and if the application requires their calibration).
In case of setting calibration factors of both modes single ended and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED): both calibration factors must be concatenated. To perform this processing, use helper macro __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be enabled, without calibration on going, without conversion on going on group regular.
Reference Manual to LL API cross reference:
CALFACT CALFACT_S LL_ADC_SetCalibrationFactor
CALFACT CALFACT_D LL_ADC_SetCalibrationFactor
Parameters:
ADCx | ADC instance
SingleDiff This parameter can be one of the following values:
  • LL_ADC_SINGLE_ENDED
  • LL_ADC_DIFFERENTIAL_ENDED
  • LL_ADC_BOTH_SINGLE_DIFF_ENDED
CalibrationFactor | Value between Min_Data=0x00 and Max_Data=0x7F
Return values:
None

Definition at line 2147 of file stm32wbxx_ll_adc.h.

References ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK, ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4, and ADC_SINGLEDIFF_CALIB_FACTOR_MASK.

Referenced by HAL_ADCEx_Calibration_SetValue().

__STATIC_INLINE void LL_ADC_SetDataAlignment | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | DataAlignment
 | ) |  |

Set ADC conversion data alignment.

Note:
Refer to reference manual for alignments formats dependencies to ADC resolutions.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CFGR ALIGN LL_ADC_SetDataAlignment
Parameters:
ADCx ADC instance
DataAlignment This parameter can be one of the following values:
  • LL_ADC_DATA_ALIGN_RIGHT
  • LL_ADC_DATA_ALIGN_LEFT
Return values:
None

Definition at line 2233 of file stm32wbxx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetLowPowerMode | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | LowPowerMode
 | ) |  |

Set ADC low power mode.

Note:
Description of ADC low power modes:
  • ADC low power mode "auto wait": Dynamic low power mode, ADC conversions occurrences are limited to the minimum necessary in order to reduce power consumption. New ADC conversion starts only when the previous unitary conversion data (for ADC group regular) or previous sequence conversions data (for ADC group injected) has been retrieved by user software. In the meantime, ADC remains idle: does not performs any other conversion. This mode allows to automatically adapt the ADC conversions triggers to the speed of the software that reads the data. Moreover, this avoids risk of overrun for low frequency applications. How to use this low power mode:
    • Do not use with interruption or DMA since these modes have to clear immediately the EOC flag to free the IRQ vector sequencer.
    • Do use with polling: 1. Start conversion, 2. Later on, when conversion data is needed: poll for end of conversion to ensure that conversion is completed and retrieve ADC conversion data. This will trig another ADC conversion start.
  • ADC low power mode "auto power-off" (feature available on this device if parameter LL_ADC_LP_AUTOPOWEROFF is available): the ADC automatically powers-off after a conversion and automatically wakes up when a new conversion is triggered (with startup time between trigger and start of sampling). This feature can be combined with low power mode "auto wait".
With ADC low power mode "auto wait", the ADC conversion data read is corresponding to previous ADC conversion start, independently of delay during which ADC was idle. Therefore, the ADC conversion data may be outdated: does not correspond to the current voltage level on the selected ADC channel.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CFGR AUTDLY LL_ADC_SetLowPowerMode
Parameters:
ADCx ADC instance
LowPowerMode This parameter can be one of the following values:
  • LL_ADC_LP_MODE_NONE
  • LL_ADC_LP_AUTOWAIT
Return values:
None

Definition at line 2301 of file stm32wbxx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetOffset | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Offsety,
 |  | uint32_t | Channel,
 |  | uint32_t | OffsetLevel
 | ) |  |

Set ADC selected offset number 1, 2, 3 or 4.

Note:
This function set the 2 items of offset configuration:
  • ADC channel to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)
  • Offset level (offset to be subtracted from the raw converted data).
Caution: Offset format is dependent to ADC resolution: offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0.
This function enables the offset, by default. It can be forced to disable state using function LL_ADC_SetOffsetState().
If a channel is mapped on several offsets numbers, only the offset with the lowest value is considered for the subtraction.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
On STM32WB, some fast channels are available: fast analog inputs coming from GPIO pads (ADC_IN1..5).
Reference Manual to LL API cross reference:
OFR1 OFFSET1_CH LL_ADC_SetOffset
OFR1 OFFSET1 LL_ADC_SetOffset
OFR1 OFFSET1_EN LL_ADC_SetOffset
OFR2 OFFSET2_CH LL_ADC_SetOffset
OFR2 OFFSET2 LL_ADC_SetOffset
OFR2 OFFSET2_EN LL_ADC_SetOffset
OFR3 OFFSET3_CH LL_ADC_SetOffset
OFR3 OFFSET3 LL_ADC_SetOffset
OFR3 OFFSET3_EN LL_ADC_SetOffset
OFR4 OFFSET4_CH LL_ADC_SetOffset
OFR4 OFFSET4 LL_ADC_SetOffset
OFR4 OFFSET4_EN LL_ADC_SetOffset
Parameters:
ADCx | ADC instance
Offsety This parameter can be one of the following values:
  • LL_ADC_OFFSET_1
  • LL_ADC_OFFSET_2
  • LL_ADC_OFFSET_3
  • LL_ADC_OFFSET_4
Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (7)
  • LL_ADC_CHANNEL_2 (7)
  • LL_ADC_CHANNEL_3 (7)
  • LL_ADC_CHANNEL_4 (7)
  • LL_ADC_CHANNEL_5 (7)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT
  • LL_ADC_CHANNEL_TEMPSENSOR
  • LL_ADC_CHANNEL_VBAT
(7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
OffsetLevel | Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
None

Definition at line 2422 of file stm32wbxx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, and ADC_CHANNEL_ID_NUMBER_MASK.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

__STATIC_INLINE void LL_ADC_SetOffsetState | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Offsety,
 |  | uint32_t | OffsetState
 | ) |  |

Set for the ADC selected offset number 1, 2, 3 or 4: force offset state disable or enable without modifying offset channel or offset value.

Note:
This function should be needed only in case of offset to be enabled-disabled dynamically, and should not be needed in other cases: function LL_ADC_SetOffset() automatically enables the offset.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
OFR1 OFFSET1_EN LL_ADC_SetOffsetState
OFR2 OFFSET2_EN LL_ADC_SetOffsetState
OFR3 OFFSET3_EN LL_ADC_SetOffsetState
OFR4 OFFSET4_EN LL_ADC_SetOffsetState
Parameters:
ADCx ADC instance
Offsety This parameter can be one of the following values:
  • LL_ADC_OFFSET_1
  • LL_ADC_OFFSET_2
  • LL_ADC_OFFSET_3
  • LL_ADC_OFFSET_4
OffsetState This parameter can be one of the following values:
  • LL_ADC_OFFSET_DISABLE
  • LL_ADC_OFFSET_ENABLE
Return values:
None

Definition at line 2548 of file stm32wbxx_ll_adc.h.

References __ADC_PTR_REG_OFFSET.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

__STATIC_INLINE void LL_ADC_SetResolution | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Resolution
 | ) |  |

Set ADC resolution.

Refer to reference manual for alignments formats dependencies to ADC resolutions.

Note:
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CFGR RES LL_ADC_SetResolution
Parameters:
ADCx ADC instance
Resolution This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
  • LL_ADC_RESOLUTION_10B
  • LL_ADC_RESOLUTION_8B
  • LL_ADC_RESOLUTION_6B
Return values:
None

Definition at line 2196 of file stm32wbxx_ll_adc.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Configuration of ADC hierarchical scope: group regular

Functions
Configuration of ADC hierarchical scope: group regular
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_REG_SetTriggerSource (ADC_TypeDef *ADCx, uint32_t TriggerSource)
Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_REG_GetTriggerSource (ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_REG_IsTriggerSourceSWStart (ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger source internal (SW start) or external.
__STATIC_INLINE void | LL_ADC_REG_SetTriggerEdge (ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
Set ADC group regular conversion trigger polarity.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetTriggerEdge (ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger polarity.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerLength (ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
Set ADC group regular sequencer length and scan direction.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerLength (ADC_TypeDef *ADCx)
Get ADC group regular sequencer length and scan direction.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerDiscont (ADC_TypeDef *ADCx, uint32_t SeqDiscont)
Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerDiscont (ADC_TypeDef *ADCx)
Get ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
Set ADC group regular sequence: channel on the selected scan sequence rank.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group regular sequence: channel on the selected scan sequence rank.
__STATIC_INLINE void | LL_ADC_REG_SetContinuousMode (ADC_TypeDef *ADCx, uint32_t Continuous)
Set ADC continuous conversion mode on ADC group regular.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetContinuousMode (ADC_TypeDef *ADCx)
Get ADC continuous conversion mode on ADC group regular.
__STATIC_INLINE void | LL_ADC_REG_SetDMATransfer (ADC_TypeDef *ADCx, uint32_t DMATransfer)
Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetDMATransfer (ADC_TypeDef *ADCx)
Get ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
__STATIC_INLINE void | LL_ADC_REG_SetOverrun (ADC_TypeDef *ADCx, uint32_t Overrun)
Set ADC group regular behavior in case of overrun: data preserved or overwritten.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetOverrun (ADC_TypeDef *ADCx)
Get ADC group regular behavior in case of overrun: data preserved or overwritten.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode ( ADC_TypeDef * ADCx )

Get ADC continuous conversion mode on ADC group regular.

Note:
Description of ADC continuous conversion mode:
  • single mode: one conversion per trigger
  • continuous mode: after the first trigger, following conversions launched successively automatically.
Reference Manual to LL API cross reference:
CFGR CONT LL_ADC_REG_GetContinuousMode
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_CONV_SINGLE
  • LL_ADC_REG_CONV_CONTINUOUS

Definition at line 3112 of file stm32wbxx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer ( ADC_TypeDef * ADCx )

Get ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.

Note:
If transfer by DMA selected, specifies the DMA requests mode:
  • Limited mode (One shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular.
  • Unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transfers (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular.
If ADC DMA requests mode is set to unlimited and DMA is set to mode non-circular: when DMA transfers size will be reached, DMA will stop transfers of ADC conversions data ADC will raise an overrun error (overrun flag and interruption if enabled).
To configure DMA source address (peripheral address), use function LL_ADC_DMA_GetRegAddr().
Reference Manual to LL API cross reference:
CFGR DMAEN LL_ADC_REG_GetDMATransfer
CFGR DMACFG LL_ADC_REG_GetDMATransfer
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_DMA_TRANSFER_NONE
  • LL_ADC_REG_DMA_TRANSFER_LIMITED
  • LL_ADC_REG_DMA_TRANSFER_UNLIMITED

Definition at line 3183 of file stm32wbxx_ll_adc.h.

Referenced by HAL_ADC_IRQHandler().

__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun ( ADC_TypeDef * ADCx )

Get ADC group regular behavior in case of overrun: data preserved or overwritten.

Reference Manual to LL API cross reference:
CFGR OVRMOD LL_ADC_REG_GetOverrun
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_OVR_DATA_PRESERVED
  • LL_ADC_REG_OVR_DATA_OVERWRITTEN

Definition at line 3223 of file stm32wbxx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont ( ADC_TypeDef * ADCx )

Get ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

Reference Manual to LL API cross reference:
CFGR DISCEN LL_ADC_REG_GetSequencerDiscont
CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_SEQ_DISCONT_DISABLE
  • LL_ADC_REG_SEQ_DISCONT_1RANK
  • LL_ADC_REG_SEQ_DISCONT_2RANKS
  • LL_ADC_REG_SEQ_DISCONT_3RANKS
  • LL_ADC_REG_SEQ_DISCONT_4RANKS
  • LL_ADC_REG_SEQ_DISCONT_5RANKS
  • LL_ADC_REG_SEQ_DISCONT_6RANKS
  • LL_ADC_REG_SEQ_DISCONT_7RANKS
  • LL_ADC_REG_SEQ_DISCONT_8RANKS

Definition at line 2882 of file stm32wbxx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength ( ADC_TypeDef * ADCx )

Get ADC group regular sequencer length and scan direction.

Note:
Description of ADC group regular sequencer features:
  • For devices with sequencer fully configurable (function "LL_ADC_REG_SetSequencerRanks()" available): sequencer length and each rank affectation to a channel are configurable. This function retrieves:
    • Sequence length: Number of ranks in the scan sequence.
    • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from rank 1 to rank n). Sequencer ranks are selected using function "LL_ADC_REG_SetSequencerRanks()".
  • For devices with sequencer not fully configurable (function "LL_ADC_REG_SetSequencerChannels()" available): sequencer length and each rank affectation to a channel are defined by channel number. This function retrieves:
    • Sequence length: Number of ranks in the scan sequence is defined by number of channels set in the sequence, rank of each channel is fixed by channel HW number. (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
    • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from lowest channel number to highest channel number). Sequencer ranks are selected using function "LL_ADC_REG_SetSequencerChannels()".
Sequencer disabled is equivalent to sequencer of 1 rank: ADC conversion on only 1 channel.
Reference Manual to LL API cross reference:
SQR1 L LL_ADC_REG_GetSequencerLength
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_SEQ_SCAN_DISABLE
  • LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS

Definition at line 2827 of file stm32wbxx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group regular sequence: channel on the selected scan sequence rank.

Note:
On this STM32 serie, ADC group regular sequencer is fully configurable: sequencer length and each rank affectation to a channel are configurable. Refer to description of function LL_ADC_REG_SetSequencerLength().
Depending on devices and packages, some channels may not be available. Refer to device datasheet for channels availability.
Usage of the returned channel number:
  • To reinject this channel into another function LL_ADC_xxx: the returned channel number is only partly formatted on definition of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared with parts of literals LL_ADC_CHANNEL_x or using helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB(). Then the selected literal LL_ADC_CHANNEL_x can be used as parameter for another function.
  • To get the channel number in decimal format: process the returned value with the helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB().
Reference Manual to LL API cross reference:
SQR1 SQ1 LL_ADC_REG_GetSequencerRanks
SQR1 SQ2 LL_ADC_REG_GetSequencerRanks
SQR1 SQ3 LL_ADC_REG_GetSequencerRanks
SQR1 SQ4 LL_ADC_REG_GetSequencerRanks
SQR2 SQ5 LL_ADC_REG_GetSequencerRanks
SQR2 SQ6 LL_ADC_REG_GetSequencerRanks
SQR2 SQ7 LL_ADC_REG_GetSequencerRanks
SQR2 SQ8 LL_ADC_REG_GetSequencerRanks
SQR2 SQ9 LL_ADC_REG_GetSequencerRanks
SQR3 SQ10 LL_ADC_REG_GetSequencerRanks
SQR3 SQ11 LL_ADC_REG_GetSequencerRanks
SQR3 SQ12 LL_ADC_REG_GetSequencerRanks
SQR3 SQ13 LL_ADC_REG_GetSequencerRanks
SQR3 SQ14 LL_ADC_REG_GetSequencerRanks
SQR4 SQ15 LL_ADC_REG_GetSequencerRanks
SQR4 SQ16 LL_ADC_REG_GetSequencerRanks
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_REG_RANK_1
  • LL_ADC_REG_RANK_2
  • LL_ADC_REG_RANK_3
  • LL_ADC_REG_RANK_4
  • LL_ADC_REG_RANK_5
  • LL_ADC_REG_RANK_6
  • LL_ADC_REG_RANK_7
  • LL_ADC_REG_RANK_8
  • LL_ADC_REG_RANK_9
  • LL_ADC_REG_RANK_10
  • LL_ADC_REG_RANK_11
  • LL_ADC_REG_RANK_12
  • LL_ADC_REG_RANK_13
  • LL_ADC_REG_RANK_14
  • LL_ADC_REG_RANK_15
  • LL_ADC_REG_RANK_16
Return values:
Returned value can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (7)
  • LL_ADC_CHANNEL_2 (7)
  • LL_ADC_CHANNEL_3 (7)
  • LL_ADC_CHANNEL_4 (7)
  • LL_ADC_CHANNEL_5 (7)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (4)
  • LL_ADC_CHANNEL_VBAT (4)
(7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
(4) For ADC channel read back from ADC register, comparison with internal channel parameter to be done using helper macro __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

Definition at line 3066 of file stm32wbxx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0, ADC_REG_RANK_ID_SQRX_MASK, ADC_REG_SQRX_REGOFFSET_MASK, and ADC_SQRX_REGOFFSET_POS.

__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge ( ADC_TypeDef * ADCx )

Get ADC group regular conversion trigger polarity.

Note:
Applicable only for trigger source set to external trigger.
Reference Manual to LL API cross reference:
CFGR EXTEN LL_ADC_REG_GetTriggerEdge
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_TRIG_EXT_RISING
  • LL_ADC_REG_TRIG_EXT_FALLING
  • LL_ADC_REG_TRIG_EXT_RISINGFALLING

Definition at line 2714 of file stm32wbxx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource ( ADC_TypeDef * ADCx )

Get ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).

Note:
To determine whether group regular trigger source is internal (SW start) or external, without detail of which peripheral is selected as external trigger, (equivalent to "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)") use function LL_ADC_REG_IsTriggerSourceSWStart.
Availability of parameters of trigger sources from timer depends on timers availability on the selected device.
Reference Manual to LL API cross reference:
CFGR EXTSEL LL_ADC_REG_GetTriggerSource
CFGR EXTEN LL_ADC_REG_GetTriggerSource
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_TRIG_SOFTWARE
  • LL_ADC_REG_TRIG_EXT_TIM1_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
  • LL_ADC_REG_TRIG_EXT_TIM1_CH1
  • LL_ADC_REG_TRIG_EXT_TIM1_CH2
  • LL_ADC_REG_TRIG_EXT_TIM1_CH3
  • LL_ADC_REG_TRIG_EXT_TIM2_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM2_CH2
  • LL_ADC_REG_TRIG_EXT_EXTI_LINE11

Definition at line 2652 of file stm32wbxx_ll_adc.h.

References ADC_REG_TRIG_EDGE_MASK, ADC_REG_TRIG_EXTEN_BITOFFSET_POS, and ADC_REG_TRIG_SOURCE_MASK.

__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart ( ADC_TypeDef * ADCx )

Get ADC group regular conversion trigger source internal (SW start) or external.

Note:
In case of group regular trigger source set to external trigger, to determine which peripheral is selected as external trigger, use function LL_ADC_REG_GetTriggerSource().
Reference Manual to LL API cross reference:
CFGR EXTEN LL_ADC_REG_IsTriggerSourceSWStart
Parameters:
ADCx ADC instance
Return values:
Value "0" if trigger source external trigger Value "1" if trigger source SW start.

Definition at line 2679 of file stm32wbxx_ll_adc.h.

References LL_ADC_REG_TRIG_SOFTWARE.

Referenced by ADC_DMAConvCplt(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), and HAL_ADCEx_InjectedPollForConversion().

__STATIC_INLINE void LL_ADC_REG_SetContinuousMode | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Continuous
 | ) |  |

Set ADC continuous conversion mode on ADC group regular.

Note:
Description of ADC continuous conversion mode:
  • single mode: one conversion per trigger
  • continuous mode: after the first trigger, following conversions launched successively automatically.
It is not possible to enable both ADC group regular continuous mode and sequencer discontinuous mode.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
CFGR CONT LL_ADC_REG_SetContinuousMode
Parameters:
ADCx ADC instance
Continuous This parameter can be one of the following values:
  • LL_ADC_REG_CONV_SINGLE
  • LL_ADC_REG_CONV_CONTINUOUS
Return values:
None

Definition at line 3095 of file stm32wbxx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_SetDMATransfer | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | DMATransfer
 | ) |  |

Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.

Note:
If transfer by DMA selected, specifies the DMA requests mode:
  • Limited mode (One shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular.
  • Unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transfers (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular.
If ADC DMA requests mode is set to unlimited and DMA is set to mode non-circular: when DMA transfers size will be reached, DMA will stop transfers of ADC conversions data ADC will raise an overrun error (overrun flag and interruption if enabled).
To configure DMA source address (peripheral address), use function LL_ADC_DMA_GetRegAddr().
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CFGR DMAEN LL_ADC_REG_SetDMATransfer
CFGR DMACFG LL_ADC_REG_SetDMATransfer
Parameters:
ADCx ADC instance
DMATransfer This parameter can be one of the following values:
  • LL_ADC_REG_DMA_TRANSFER_NONE
  • LL_ADC_REG_DMA_TRANSFER_LIMITED
  • LL_ADC_REG_DMA_TRANSFER_UNLIMITED
Return values:
None

Definition at line 3150 of file stm32wbxx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_SetOverrun | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Overrun
 | ) |  |

Set ADC group regular behavior in case of overrun: data preserved or overwritten.

Note:
Compatibility with devices without feature overrun: other devices without this feature have a behavior equivalent to data overwritten. The default setting of overrun is data preserved. Therefore, for compatibility with all devices, parameter overrun should be set to data overwritten.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
CFGR OVRMOD LL_ADC_REG_SetOverrun
Parameters:
ADCx ADC instance
Overrun This parameter can be one of the following values:
  • LL_ADC_REG_OVR_DATA_PRESERVED
  • LL_ADC_REG_OVR_DATA_OVERWRITTEN
Return values:
None

Definition at line 3209 of file stm32wbxx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SeqDiscont
 | ) |  |

Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

Note:
It is not possible to enable both ADC group regular continuous mode and sequencer discontinuous mode.
It is not possible to enable both ADC auto-injected mode and ADC group regular sequencer discontinuous mode.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
CFGR DISCEN LL_ADC_REG_SetSequencerDiscont
CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont
Parameters:
ADCx ADC instance
SeqDiscont This parameter can be one of the following values:
  • LL_ADC_REG_SEQ_DISCONT_DISABLE
  • LL_ADC_REG_SEQ_DISCONT_1RANK
  • LL_ADC_REG_SEQ_DISCONT_2RANKS
  • LL_ADC_REG_SEQ_DISCONT_3RANKS
  • LL_ADC_REG_SEQ_DISCONT_4RANKS
  • LL_ADC_REG_SEQ_DISCONT_5RANKS
  • LL_ADC_REG_SEQ_DISCONT_6RANKS
  • LL_ADC_REG_SEQ_DISCONT_7RANKS
  • LL_ADC_REG_SEQ_DISCONT_8RANKS
Return values:
None

Definition at line 2859 of file stm32wbxx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_SetSequencerLength | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SequencerNbRanks
 | ) |  |

Set ADC group regular sequencer length and scan direction.

Note:
Description of ADC group regular sequencer features:
  • For devices with sequencer fully configurable (function "LL_ADC_REG_SetSequencerRanks()" available): sequencer length and each rank affectation to a channel are configurable. This function performs configuration of:
    • Sequence length: Number of ranks in the scan sequence.
    • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from rank 1 to rank n). Sequencer ranks are selected using function "LL_ADC_REG_SetSequencerRanks()".
  • For devices with sequencer not fully configurable (function "LL_ADC_REG_SetSequencerChannels()" available): sequencer length and each rank affectation to a channel are defined by channel number. This function performs configuration of:
    • Sequence length: Number of ranks in the scan sequence is defined by number of channels set in the sequence, rank of each channel is fixed by channel HW number. (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
    • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from lowest channel number to highest channel number). Sequencer ranks are selected using function "LL_ADC_REG_SetSequencerChannels()".
Sequencer disabled is equivalent to sequencer of 1 rank: ADC conversion on only 1 channel.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
SQR1 L LL_ADC_REG_SetSequencerLength
Parameters:
ADCx ADC instance
SequencerNbRanks This parameter can be one of the following values:
  • LL_ADC_REG_SEQ_SCAN_DISABLE
  • LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
Return values:
None

Definition at line 2773 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_REG_Init().

__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank,
 |  | uint32_t | Channel
 | ) |  |

Set ADC group regular sequence: channel on the selected scan sequence rank.

Note:
This function performs configuration of:
  • Channels ordering into each rank of scan sequence: whatever channel can be placed into whatever rank.
On this STM32 serie, ADC group regular sequencer is fully configurable: sequencer length and each rank affectation to a channel are configurable. Refer to description of function LL_ADC_REG_SetSequencerLength().
Depending on devices and packages, some channels may not be available. Refer to device datasheet for channels availability.
On this STM32 serie, to measure internal channels (VrefInt, TempSensor, ...), measurement paths to internal channels must be enabled separately. This can be done using function LL_ADC_SetCommonPathInternalCh().
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
SQR1 SQ1 LL_ADC_REG_SetSequencerRanks
SQR1 SQ2 LL_ADC_REG_SetSequencerRanks
SQR1 SQ3 LL_ADC_REG_SetSequencerRanks
SQR1 SQ4 LL_ADC_REG_SetSequencerRanks
SQR2 SQ5 LL_ADC_REG_SetSequencerRanks
SQR2 SQ6 LL_ADC_REG_SetSequencerRanks
SQR2 SQ7 LL_ADC_REG_SetSequencerRanks
SQR2 SQ8 LL_ADC_REG_SetSequencerRanks
SQR2 SQ9 LL_ADC_REG_SetSequencerRanks
SQR3 SQ10 LL_ADC_REG_SetSequencerRanks
SQR3 SQ11 LL_ADC_REG_SetSequencerRanks
SQR3 SQ12 LL_ADC_REG_SetSequencerRanks
SQR3 SQ13 LL_ADC_REG_SetSequencerRanks
SQR3 SQ14 LL_ADC_REG_SetSequencerRanks
SQR4 SQ15 LL_ADC_REG_SetSequencerRanks
SQR4 SQ16 LL_ADC_REG_SetSequencerRanks
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_REG_RANK_1
  • LL_ADC_REG_RANK_2
  • LL_ADC_REG_RANK_3
  • LL_ADC_REG_RANK_4
  • LL_ADC_REG_RANK_5
  • LL_ADC_REG_RANK_6
  • LL_ADC_REG_RANK_7
  • LL_ADC_REG_RANK_8
  • LL_ADC_REG_RANK_9
  • LL_ADC_REG_RANK_10
  • LL_ADC_REG_RANK_11
  • LL_ADC_REG_RANK_12
  • LL_ADC_REG_RANK_13
  • LL_ADC_REG_RANK_14
  • LL_ADC_REG_RANK_15
  • LL_ADC_REG_RANK_16
Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (7)
  • LL_ADC_CHANNEL_2 (7)
  • LL_ADC_CHANNEL_3 (7)
  • LL_ADC_CHANNEL_4 (7)
  • LL_ADC_CHANNEL_5 (7)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT
  • LL_ADC_CHANNEL_TEMPSENSOR
  • LL_ADC_CHANNEL_VBAT
(7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
Return values:
None

Definition at line 2969 of file stm32wbxx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS, ADC_CHANNEL_ID_NUMBER_MASK, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0, ADC_REG_RANK_ID_SQRX_MASK, ADC_REG_SQRX_REGOFFSET_MASK, and ADC_SQRX_REGOFFSET_POS.

Referenced by HAL_ADC_ConfigChannel().

__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | ExternalTriggerEdge
 | ) |  |

Set ADC group regular conversion trigger polarity.

Note:
Applicable only for trigger source set to external trigger.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
CFGR EXTEN LL_ADC_REG_SetTriggerEdge
Parameters:
ADCx ADC instance
ExternalTriggerEdge This parameter can be one of the following values:
  • LL_ADC_REG_TRIG_EXT_RISING
  • LL_ADC_REG_TRIG_EXT_FALLING
  • LL_ADC_REG_TRIG_EXT_RISINGFALLING
Return values:
None

Definition at line 2699 of file stm32wbxx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_SetTriggerSource | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | TriggerSource
 | ) |  |

Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).

Note:
On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). In case of need to modify trigger edge, use function LL_ADC_REG_SetTriggerEdge().
Availability of parameters of trigger sources from timer depends on timers availability on the selected device.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
Reference Manual to LL API cross reference:
CFGR EXTSEL LL_ADC_REG_SetTriggerSource
CFGR EXTEN LL_ADC_REG_SetTriggerSource
Parameters:
ADCx ADC instance
TriggerSource This parameter can be one of the following values:
  • LL_ADC_REG_TRIG_SOFTWARE
  • LL_ADC_REG_TRIG_EXT_TIM1_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
  • LL_ADC_REG_TRIG_EXT_TIM1_CH1
  • LL_ADC_REG_TRIG_EXT_TIM1_CH2
  • LL_ADC_REG_TRIG_EXT_TIM1_CH3
  • LL_ADC_REG_TRIG_EXT_TIM2_TRGO
  • LL_ADC_REG_TRIG_EXT_TIM2_CH2
  • LL_ADC_REG_TRIG_EXT_EXTI_LINE11
Return values:
None

Definition at line 2621 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_DeInit().

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Configuration of ADC hierarchical scope: group injected

Functions
Configuration of ADC hierarchical scope: group injected
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_INJ_SetTriggerSource (ADC_TypeDef *ADCx, uint32_t TriggerSource)
Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetTriggerSource (ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_INJ_IsTriggerSourceSWStart (ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger source internal (SW start) or external.
__STATIC_INLINE void | LL_ADC_INJ_SetTriggerEdge (ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
Set ADC group injected conversion trigger polarity.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetTriggerEdge (ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger polarity.
__STATIC_INLINE void | LL_ADC_INJ_SetSequencerLength (ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
Set ADC group injected sequencer length and scan direction.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetSequencerLength (ADC_TypeDef *ADCx)
Get ADC group injected sequencer length and scan direction.
__STATIC_INLINE void | LL_ADC_INJ_SetSequencerDiscont (ADC_TypeDef *ADCx, uint32_t SeqDiscont)
Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetSequencerDiscont (ADC_TypeDef *ADCx)
Get ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE void | LL_ADC_INJ_SetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
Set ADC group injected sequence: channel on the selected sequence rank.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected sequence: channel on the selected sequence rank.
__STATIC_INLINE void | LL_ADC_INJ_SetTrigAuto (ADC_TypeDef *ADCx, uint32_t TrigAuto)
Set ADC group injected conversion trigger: independent or from ADC group regular.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetTrigAuto (ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger: independent or from ADC group regular.
__STATIC_INLINE void | LL_ADC_INJ_SetQueueMode (ADC_TypeDef *ADCx, uint32_t QueueMode)
Set ADC group injected contexts queue mode.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetQueueMode (ADC_TypeDef *ADCx)
Get ADC group injected context queue mode.
__STATIC_INLINE void | LL_ADC_INJ_ConfigQueueContext (ADC_TypeDef *ADCx, uint32_t TriggerSource, uint32_t ExternalTriggerEdge, uint32_t SequencerNbRanks, uint32_t Rank1_Channel, uint32_t Rank2_Channel, uint32_t Rank3_Channel, uint32_t Rank4_Channel)
Set one context on ADC group injected that will be checked in contexts queue.

Function Documentation

__STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | TriggerSource,
 |  | uint32_t | ExternalTriggerEdge,
 |  | uint32_t | SequencerNbRanks,
 |  | uint32_t | Rank1_Channel,
 |  | uint32_t | Rank2_Channel,
 |  | uint32_t | Rank3_Channel,
 |  | uint32_t | Rank4_Channel
 | ) |  |

Set one context on ADC group injected that will be checked in contexts queue.

Note:
A context is a setting of group injected sequencer:
  • group injected trigger
  • sequencer length
  • sequencer ranks This function is intended to be used when contexts queue is enabled, because the sequence must be fully configured in one time (functions to set separately injected trigger and sequencer channels cannot be used): Refer to function LL_ADC_INJ_SetQueueMode().
In the contexts queue, only the active context can be read. The parameters of this function can be read using functions:
  • LL_ADC_INJ_GetTriggerSource()
  • LL_ADC_INJ_GetTriggerEdge()
  • LL_ADC_INJ_GetSequencerRanks()
On this STM32 serie, to measure internal channels (VrefInt, TempSensor, ...), measurement paths to internal channels must be enabled separately. This can be done using function LL_ADC_SetCommonPathInternalCh().
On STM32WB, some fast channels are available: fast analog inputs coming from GPIO pads (ADC_IN1..5).
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must not be disabled. Can be enabled with or without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext
JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext
JSQR JL LL_ADC_INJ_ConfigQueueContext
JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext
JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext
JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext
JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext
Parameters:
ADCx ADC instance
TriggerSource This parameter can be one of the following values:
  • LL_ADC_INJ_TRIG_SOFTWARE
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
  • LL_ADC_INJ_TRIG_EXT_TIM1_CH4
  • LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM2_CH1
  • LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
ExternalTriggerEdge This parameter can be one of the following values:
  • LL_ADC_INJ_TRIG_EXT_RISING
  • LL_ADC_INJ_TRIG_EXT_FALLING
  • LL_ADC_INJ_TRIG_EXT_RISINGFALLING
Note: This parameter is discarded in case of SW start: parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
SequencerNbRanks This parameter can be one of the following values:
  • LL_ADC_INJ_SEQ_SCAN_DISABLE
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
Rank1_Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (7)
  • LL_ADC_CHANNEL_2 (7)
  • LL_ADC_CHANNEL_3 (7)
  • LL_ADC_CHANNEL_4 (7)
  • LL_ADC_CHANNEL_5 (7)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT
  • LL_ADC_CHANNEL_TEMPSENSOR
  • LL_ADC_CHANNEL_VBAT
(7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
Rank2_Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (7)
  • LL_ADC_CHANNEL_2 (7)
  • LL_ADC_CHANNEL_3 (7)
  • LL_ADC_CHANNEL_4 (7)
  • LL_ADC_CHANNEL_5 (7)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT
  • LL_ADC_CHANNEL_TEMPSENSOR
  • LL_ADC_CHANNEL_VBAT
(7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
Rank3_Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (7)
  • LL_ADC_CHANNEL_2 (7)
  • LL_ADC_CHANNEL_3 (7)
  • LL_ADC_CHANNEL_4 (7)
  • LL_ADC_CHANNEL_5 (7)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT
  • LL_ADC_CHANNEL_TEMPSENSOR
  • LL_ADC_CHANNEL_VBAT
(7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
Rank4_Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (7)
  • LL_ADC_CHANNEL_2 (7)
  • LL_ADC_CHANNEL_3 (7)
  • LL_ADC_CHANNEL_4 (7)
  • LL_ADC_CHANNEL_5 (7)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT
  • LL_ADC_CHANNEL_TEMPSENSOR
  • LL_ADC_CHANNEL_VBAT
(7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
Return values:
None

Definition at line 3840 of file stm32wbxx_ll_adc.h.

References ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS, ADC_CHANNEL_ID_NUMBER_MASK, ADC_INJ_RANK_ID_JSQR_MASK, LL_ADC_INJ_RANK_1, LL_ADC_INJ_RANK_2, LL_ADC_INJ_RANK_3, LL_ADC_INJ_RANK_4, and LL_ADC_INJ_TRIG_SOFTWARE.

__STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode ( ADC_TypeDef * ADCx )

Get ADC group injected context queue mode.

Reference Manual to LL API cross reference:
CFGR JQM LL_ADC_INJ_GetQueueMode
CFGR JQDIS LL_ADC_INJ_GetQueueMode
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_INJ_QUEUE_DISABLE
  • LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
  • LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY

Definition at line 3674 of file stm32wbxx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont ( ADC_TypeDef * ADCx )

Get ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

Reference Manual to LL API cross reference:
CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_INJ_SEQ_DISCONT_DISABLE
  • LL_ADC_INJ_SEQ_DISCONT_1RANK

Definition at line 3436 of file stm32wbxx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength ( ADC_TypeDef * ADCx )

Get ADC group injected sequencer length and scan direction.

Note:
This function retrieves:
  • Sequence length: Number of ranks in the scan sequence.
  • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from rank 1 to rank n).
Sequencer disabled is equivalent to sequencer of 1 rank: ADC conversion on only 1 channel.
Reference Manual to LL API cross reference:
JSQR JL LL_ADC_INJ_GetSequencerLength
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_INJ_SEQ_SCAN_DISABLE
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS

Definition at line 3403 of file stm32wbxx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group injected sequence: channel on the selected sequence rank.

Note:
Depending on devices and packages, some channels may not be available. Refer to device datasheet for channels availability.
Usage of the returned channel number:
  • To reinject this channel into another function LL_ADC_xxx: the returned channel number is only partly formatted on definition of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared with parts of literals LL_ADC_CHANNEL_x or using helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB(). Then the selected literal LL_ADC_CHANNEL_x can be used as parameter for another function.
  • To get the channel number in decimal format: process the returned value with the helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB().
Reference Manual to LL API cross reference:
JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks
JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks
JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks
JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
Return values:
Returned value can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (7)
  • LL_ADC_CHANNEL_2 (7)
  • LL_ADC_CHANNEL_3 (7)
  • LL_ADC_CHANNEL_4 (7)
  • LL_ADC_CHANNEL_5 (7)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (4)
  • LL_ADC_CHANNEL_VBAT (4)
(7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
(4) For ADC channel read back from ADC register, comparison with internal channel parameter to be done using helper macro __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

Definition at line 3561 of file stm32wbxx_ll_adc.h.

References ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS, ADC_CHANNEL_ID_NUMBER_MASK, and ADC_INJ_RANK_ID_JSQR_MASK.

__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto ( ADC_TypeDef * ADCx )

Get ADC group injected conversion trigger: independent or from ADC group regular.

Reference Manual to LL API cross reference:
CFGR JAUTO LL_ADC_INJ_GetTrigAuto
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_INJ_TRIG_INDEPENDENT
  • LL_ADC_INJ_TRIG_FROM_GRP_REGULAR

Definition at line 3613 of file stm32wbxx_ll_adc.h.

Referenced by HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge ( ADC_TypeDef * ADCx )

Get ADC group injected conversion trigger polarity.

Applicable only for trigger source set to external trigger.

Reference Manual to LL API cross reference:
JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_INJ_TRIG_EXT_RISING
  • LL_ADC_INJ_TRIG_EXT_FALLING
  • LL_ADC_INJ_TRIG_EXT_RISINGFALLING

Definition at line 3356 of file stm32wbxx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource ( ADC_TypeDef * ADCx )

Get ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).

Note:
To determine whether group injected trigger source is internal (SW start) or external, without detail of which peripheral is selected as external trigger, (equivalent to "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)") use function LL_ADC_INJ_IsTriggerSourceSWStart.
Availability of parameters of trigger sources from timer depends on timers availability on the selected device.
Reference Manual to LL API cross reference:
JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource
JSQR JEXTEN LL_ADC_INJ_GetTriggerSource
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_INJ_TRIG_SOFTWARE
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
  • LL_ADC_INJ_TRIG_EXT_TIM1_CH4
  • LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM2_CH1
  • LL_ADC_INJ_TRIG_EXT_EXTI_LINE15

Definition at line 3294 of file stm32wbxx_ll_adc.h.

References ADC_INJ_TRIG_EDGE_MASK, ADC_INJ_TRIG_EXTEN_BITOFFSET_POS, and ADC_INJ_TRIG_SOURCE_MASK.

__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart ( ADC_TypeDef * ADCx )

Get ADC group injected conversion trigger source internal (SW start) or external.

Note:
In case of group injected trigger source set to external trigger, to determine which peripheral is selected as external trigger, use function LL_ADC_INJ_GetTriggerSource.
Reference Manual to LL API cross reference:
JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
Parameters:
ADCx ADC instance
Return values:
Value "0" if trigger source external trigger Value "1" if trigger source SW start.

Definition at line 3321 of file stm32wbxx_ll_adc.h.

References LL_ADC_INJ_TRIG_SOFTWARE.

Referenced by HAL_ADC_IRQHandler(), and HAL_ADCEx_InjectedPollForConversion().

__STATIC_INLINE void LL_ADC_INJ_SetQueueMode | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | QueueMode
 | ) |  |

Set ADC group injected contexts queue mode.

Note:
A context is a setting of group injected sequencer:
  • group injected trigger
  • sequencer length
  • sequencer ranks If contexts queue is disabled:
  • only 1 sequence can be configured and is active perpetually. If contexts queue is enabled:
  • up to 2 contexts can be queued and are checked in and out as a FIFO stack (first-in, first-out).
  • If a new context is set when queues is full, error is triggered by interruption "Injected Queue Overflow".
  • Two behaviors are possible when all contexts have been processed: the contexts queue can maintain the last context active perpetually or can be empty and injected group triggers are disabled.
  • Triggers can be only external (not internal SW start)
  • Caution: The sequence must be fully configured in one time (one write of register JSQR makes a check-in of a new context into the queue). Therefore functions to set separately injected trigger and sequencer channels cannot be used, register JSQR must be set using function LL_ADC_INJ_ConfigQueueContext().
This parameter can be modified only when no conversion is on going on either groups regular or injected.
A modification of the context mode (bit JQDIS) causes the contexts queue to be flushed and the register JSQR is cleared.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CFGR JQM LL_ADC_INJ_SetQueueMode
CFGR JQDIS LL_ADC_INJ_SetQueueMode
Parameters:
ADCx ADC instance
QueueMode This parameter can be one of the following values:
  • LL_ADC_INJ_QUEUE_DISABLE
  • LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
  • LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
Return values:
None

Definition at line 3659 of file stm32wbxx_ll_adc.h.

Referenced by HAL_ADCEx_DisableInjectedQueue(), and LL_ADC_DeInit().

__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SeqDiscont
 | ) |  |

Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

Note:
It is not possible to enable both ADC group injected auto-injected mode and sequencer discontinuous mode.
Reference Manual to LL API cross reference:
CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont
Parameters:
ADCx ADC instance
SeqDiscont This parameter can be one of the following values:
  • LL_ADC_INJ_SEQ_DISCONT_DISABLE
  • LL_ADC_INJ_SEQ_DISCONT_1RANK
Return values:
None

Definition at line 3421 of file stm32wbxx_ll_adc.h.

__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SequencerNbRanks
 | ) |  |

Set ADC group injected sequencer length and scan direction.

Note:
This function performs configuration of:
  • Sequence length: Number of ranks in the scan sequence.
  • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from rank 1 to rank n).
Sequencer disabled is equivalent to sequencer of 1 rank: ADC conversion on only 1 channel.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must not be disabled. Can be enabled with or without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
JSQR JL LL_ADC_INJ_SetSequencerLength
Parameters:
ADCx ADC instance
SequencerNbRanks This parameter can be one of the following values:
  • LL_ADC_INJ_SEQ_SCAN_DISABLE
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
Return values:
None

Definition at line 3382 of file stm32wbxx_ll_adc.h.

__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank,
 |  | uint32_t | Channel
 | ) |  |

Set ADC group injected sequence: channel on the selected sequence rank.

Note:
Depending on devices and packages, some channels may not be available. Refer to device datasheet for channels availability.
On this STM32 serie, to measure internal channels (VrefInt, TempSensor, ...), measurement paths to internal channels must be enabled separately. This can be done using function LL_ADC_SetCommonPathInternalCh().
On STM32WB, some fast channels are available: fast analog inputs coming from GPIO pads (ADC_IN1..5).
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must not be disabled. Can be enabled with or without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks
JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks
JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks
JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (7)
  • LL_ADC_CHANNEL_2 (7)
  • LL_ADC_CHANNEL_3 (7)
  • LL_ADC_CHANNEL_4 (7)
  • LL_ADC_CHANNEL_5 (7)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT
  • LL_ADC_CHANNEL_TEMPSENSOR
  • LL_ADC_CHANNEL_VBAT
(7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
Return values:
None

Definition at line 3494 of file stm32wbxx_ll_adc.h.

References ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS, ADC_CHANNEL_ID_NUMBER_MASK, and ADC_INJ_RANK_ID_JSQR_MASK.

__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | TrigAuto
 | ) |  |

Set ADC group injected conversion trigger: independent or from ADC group regular.

Note:
This mode can be used to extend number of data registers updated after one ADC conversion trigger and with data permanently kept (not erased by successive conversions of scan of ADC sequencer ranks), up to 5 data registers: 1 data register on ADC group regular, 4 data registers on ADC group injected.
If ADC group injected injected trigger source is set to an external trigger, this feature must be must be set to independent trigger. ADC group injected automatic trigger is compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular.
It is not possible to enable both ADC group injected auto-injected mode and sequencer discontinuous mode.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CFGR JAUTO LL_ADC_INJ_SetTrigAuto
Parameters:
ADCx ADC instance
TrigAuto This parameter can be one of the following values:
  • LL_ADC_INJ_TRIG_INDEPENDENT
  • LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
Return values:
None

Definition at line 3599 of file stm32wbxx_ll_adc.h.

__STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | ExternalTriggerEdge
 | ) |  |

Set ADC group injected conversion trigger polarity.

Applicable only for trigger source set to external trigger.

Note:
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must not be disabled. Can be enabled with or without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge
Parameters:
ADCx ADC instance
ExternalTriggerEdge This parameter can be one of the following values:
  • LL_ADC_INJ_TRIG_EXT_RISING
  • LL_ADC_INJ_TRIG_EXT_FALLING
  • LL_ADC_INJ_TRIG_EXT_RISINGFALLING
Return values:
None

Definition at line 3341 of file stm32wbxx_ll_adc.h.

__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | TriggerSource
 | ) |  |

Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).

Note:
On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). In case of need to modify trigger edge, use function LL_ADC_INJ_SetTriggerEdge().
Availability of parameters of trigger sources from timer depends on timers availability on the selected device.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must not be disabled. Can be enabled with or without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource
JSQR JEXTEN LL_ADC_INJ_SetTriggerSource
Parameters:
ADCx ADC instance
TriggerSource This parameter can be one of the following values:
  • LL_ADC_INJ_TRIG_SOFTWARE
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
  • LL_ADC_INJ_TRIG_EXT_TIM1_CH4
  • LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
  • LL_ADC_INJ_TRIG_EXT_TIM2_CH1
  • LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
Return values:
None

Definition at line 3265 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_DeInit().

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Configuration of ADC hierarchical scope: channels

Functions
Configuration of ADC hierarchical scope: channels
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_SetChannelSamplingTime (ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
Set sampling time of the selected ADC channel Unit: ADC clock cycles.
__STATIC_INLINE uint32_t | LL_ADC_GetChannelSamplingTime (ADC_TypeDef *ADCx, uint32_t Channel)
Get sampling time of the selected ADC channel Unit: ADC clock cycles.
__STATIC_INLINE void | LL_ADC_SetChannelSingleDiff (ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
Set mode single-ended or differential input of the selected ADC channel.
__STATIC_INLINE uint32_t | LL_ADC_GetChannelSingleDiff (ADC_TypeDef *ADCx, uint32_t Channel)
Get mode single-ended or differential input of the selected ADC channel.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Channel
 | ) |  |

Get sampling time of the selected ADC channel Unit: ADC clock cycles.

Note:
On this device, sampling time is on channel scope: independently of channel mapped on ADC group regular or injected.
Conversion time is the addition of sampling time and processing time. On this STM32 serie, ADC processing time is:
  • 12.5 ADC clock cycles at ADC resolution 12 bits
  • 10.5 ADC clock cycles at ADC resolution 10 bits
  • 8.5 ADC clock cycles at ADC resolution 8 bits
  • 6.5 ADC clock cycles at ADC resolution 6 bits
Reference Manual to LL API cross reference:
SMPR1 SMP0 LL_ADC_GetChannelSamplingTime
SMPR1 SMP1 LL_ADC_GetChannelSamplingTime
SMPR1 SMP2 LL_ADC_GetChannelSamplingTime
SMPR1 SMP3 LL_ADC_GetChannelSamplingTime
SMPR1 SMP4 LL_ADC_GetChannelSamplingTime
SMPR1 SMP5 LL_ADC_GetChannelSamplingTime
SMPR1 SMP6 LL_ADC_GetChannelSamplingTime
SMPR1 SMP7 LL_ADC_GetChannelSamplingTime
SMPR1 SMP8 LL_ADC_GetChannelSamplingTime
SMPR1 SMP9 LL_ADC_GetChannelSamplingTime
SMPR2 SMP10 LL_ADC_GetChannelSamplingTime
SMPR2 SMP11 LL_ADC_GetChannelSamplingTime
SMPR2 SMP12 LL_ADC_GetChannelSamplingTime
SMPR2 SMP13 LL_ADC_GetChannelSamplingTime
SMPR2 SMP14 LL_ADC_GetChannelSamplingTime
SMPR2 SMP15 LL_ADC_GetChannelSamplingTime
SMPR2 SMP16 LL_ADC_GetChannelSamplingTime
SMPR2 SMP17 LL_ADC_GetChannelSamplingTime
SMPR2 SMP18 LL_ADC_GetChannelSamplingTime
Parameters:
ADCx ADC instance
Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (7)
  • LL_ADC_CHANNEL_2 (7)
  • LL_ADC_CHANNEL_3 (7)
  • LL_ADC_CHANNEL_4 (7)
  • LL_ADC_CHANNEL_5 (7)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT
  • LL_ADC_CHANNEL_TEMPSENSOR
  • LL_ADC_CHANNEL_VBAT
(7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
Return values:
Returned value can be one of the following values:
  • LL_ADC_SAMPLINGTIME_2CYCLES_5
  • LL_ADC_SAMPLINGTIME_6CYCLES_5
  • LL_ADC_SAMPLINGTIME_12CYCLES_5
  • LL_ADC_SAMPLINGTIME_24CYCLES_5
  • LL_ADC_SAMPLINGTIME_47CYCLES_5
  • LL_ADC_SAMPLINGTIME_92CYCLES_5
  • LL_ADC_SAMPLINGTIME_247CYCLES_5
  • LL_ADC_SAMPLINGTIME_640CYCLES_5

Definition at line 4045 of file stm32wbxx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, ADC_CHANNEL_SMPRX_REGOFFSET_MASK, ADC_CHANNEL_SMPx_BITOFFSET_MASK, ADC_CHANNEL_SMPx_BITOFFSET_POS, and ADC_SMPRX_REGOFFSET_POS.

__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Channel
 | ) |  |

Get mode single-ended or differential input of the selected ADC channel.

Note:
When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. Therefore, to ensure a channel is configured in single-ended mode, the configuration of channel itself and the channel 'i-1' must be read back (to ensure that the selected channel channel has not been configured in differential mode by the previous channel).
Refer to Reference Manual to ensure the selected channel is available in differential mode. For example, internal channels (VrefInt, TempSensor, ...) are not available in differential mode.
When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
On STM32WB, channels 16, 17, 18 of ADC1 are internally fixed to single-ended inputs configuration.
One or several values can be selected. In this case, the value returned is null if all channels are in single ended-mode. Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
Reference Manual to LL API cross reference:
DIFSEL DIFSEL LL_ADC_GetChannelSingleDiff
Parameters:
ADCx ADC instance
Channel This parameter can be a combination of the following values:
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
Return values:
0,: channel in single-ended mode, else: channel in differential mode

Definition at line 4153 of file stm32wbxx_ll_adc.h.

References ADC_SINGLEDIFF_CHANNEL_MASK.

__STATIC_INLINE void LL_ADC_SetChannelSamplingTime | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Channel,
 |  | uint32_t | SamplingTime
 | ) |  |

Set sampling time of the selected ADC channel Unit: ADC clock cycles.

Note:
On this device, sampling time is on channel scope: independently of channel mapped on ADC group regular or injected.
In case of internal channel (VrefInt, TempSensor, ...) to be converted: sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting). Refer to device datasheet for timings values (parameters TS_vrefint, TS_temp, ...).
Conversion time is the addition of sampling time and processing time. On this STM32 serie, ADC processing time is:
  • 12.5 ADC clock cycles at ADC resolution 12 bits
  • 10.5 ADC clock cycles at ADC resolution 10 bits
  • 8.5 ADC clock cycles at ADC resolution 8 bits
  • 6.5 ADC clock cycles at ADC resolution 6 bits
In case of ADC conversion of internal channel (VrefInt, temperature sensor, ...), a sampling time minimum value is required. Refer to device datasheet.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
SMPR1 SMP0 LL_ADC_SetChannelSamplingTime
SMPR1 SMP1 LL_ADC_SetChannelSamplingTime
SMPR1 SMP2 LL_ADC_SetChannelSamplingTime
SMPR1 SMP3 LL_ADC_SetChannelSamplingTime
SMPR1 SMP4 LL_ADC_SetChannelSamplingTime
SMPR1 SMP5 LL_ADC_SetChannelSamplingTime
SMPR1 SMP6 LL_ADC_SetChannelSamplingTime
SMPR1 SMP7 LL_ADC_SetChannelSamplingTime
SMPR1 SMP8 LL_ADC_SetChannelSamplingTime
SMPR1 SMP9 LL_ADC_SetChannelSamplingTime
SMPR2 SMP10 LL_ADC_SetChannelSamplingTime
SMPR2 SMP11 LL_ADC_SetChannelSamplingTime
SMPR2 SMP12 LL_ADC_SetChannelSamplingTime
SMPR2 SMP13 LL_ADC_SetChannelSamplingTime
SMPR2 SMP14 LL_ADC_SetChannelSamplingTime
SMPR2 SMP15 LL_ADC_SetChannelSamplingTime
SMPR2 SMP16 LL_ADC_SetChannelSamplingTime
SMPR2 SMP17 LL_ADC_SetChannelSamplingTime
SMPR2 SMP18 LL_ADC_SetChannelSamplingTime
Parameters:
ADCx ADC instance
Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1 (7)
  • LL_ADC_CHANNEL_2 (7)
  • LL_ADC_CHANNEL_3 (7)
  • LL_ADC_CHANNEL_4 (7)
  • LL_ADC_CHANNEL_5 (7)
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_18
  • LL_ADC_CHANNEL_VREFINT
  • LL_ADC_CHANNEL_TEMPSENSOR
  • LL_ADC_CHANNEL_VBAT
(7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
SamplingTime This parameter can be one of the following values:
  • LL_ADC_SAMPLINGTIME_2CYCLES_5
  • LL_ADC_SAMPLINGTIME_6CYCLES_5
  • LL_ADC_SAMPLINGTIME_12CYCLES_5
  • LL_ADC_SAMPLINGTIME_24CYCLES_5
  • LL_ADC_SAMPLINGTIME_47CYCLES_5
  • LL_ADC_SAMPLINGTIME_92CYCLES_5
  • LL_ADC_SAMPLINGTIME_247CYCLES_5
  • LL_ADC_SAMPLINGTIME_640CYCLES_5
Return values:
None

Definition at line 3965 of file stm32wbxx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, ADC_CHANNEL_SMPRX_REGOFFSET_MASK, ADC_CHANNEL_SMPx_BITOFFSET_MASK, ADC_CHANNEL_SMPx_BITOFFSET_POS, and ADC_SMPRX_REGOFFSET_POS.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

__STATIC_INLINE void LL_ADC_SetChannelSingleDiff | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Channel,
 |  | uint32_t | SingleDiff
 | ) |  |

Set mode single-ended or differential input of the selected ADC channel.

Note:
Channel ending is on channel scope: independently of channel mapped on ADC group regular or injected. In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input). Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
Refer to Reference Manual to ensure the selected channel is available in differential mode. For example, internal channels (VrefInt, TempSensor, ...) are not available in differential mode.
When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
On STM32WB, channels 16, 17, 18 of ADC1 are internally fixed to single-ended inputs configuration.
For ADC channels configured in differential mode, both inputs should be biased at (Vref+)/2 +/-200mV. (Vref+ is the analog voltage reference)
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be ADC disabled.
One or several values can be selected. Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
Reference Manual to LL API cross reference:
DIFSEL DIFSEL LL_ADC_SetChannelSingleDiff
Parameters:
ADCx ADC instance
Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
SingleDiff This parameter can be a combination of the following values:
  • LL_ADC_SINGLE_ENDED
  • LL_ADC_DIFFERENTIAL_ENDED
Return values:
None

Definition at line 4103 of file stm32wbxx_ll_adc.h.

References ADC_SINGLEDIFF_CHANNEL_MASK, and ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Configuration of ADC transversal scope: analog watchdog

Functions
Configuration of ADC transversal scope: analog watchdog
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_SetAnalogWDMonitChannels (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
Set ADC analog watchdog monitored channels: a single channel, multiple channels or all channels, on ADC groups regular and-or injected.
__STATIC_INLINE uint32_t | LL_ADC_GetAnalogWDMonitChannels (ADC_TypeDef *ADCx, uint32_t AWDy)
Get ADC analog watchdog monitored channel.
__STATIC_INLINE void | LL_ADC_ConfigAnalogWDThresholds (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue)
Set ADC analog watchdog thresholds value of both thresholds high and low.
__STATIC_INLINE void | LL_ADC_SetAnalogWDThresholds (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
Set ADC analog watchdog threshold value of threshold high or low.
__STATIC_INLINE uint32_t | LL_ADC_GetAnalogWDThresholds (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
Get ADC analog watchdog threshold value of threshold high, threshold low or raw data with ADC thresholds high and low concatenated.

Function Documentation

__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | AWDy,
 |  | uint32_t | AWDThresholdHighValue,
 |  | uint32_t | AWDThresholdLowValue
 | ) |  |

Set ADC analog watchdog thresholds value of both thresholds high and low.

Note:
If value of only one threshold high or low must be set, use function LL_ADC_SetAnalogWDThresholds().
In case of ADC resolution different of 12 bits, analog watchdog thresholds data require a specific shift. Use helper macro __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
On this STM32 serie, there are 2 kinds of analog watchdog instance:
  • AWD standard (instance AWD1):
    • channels monitored: can monitor 1 channel or all channels.
    • groups monitored: ADC groups regular and-or injected.
    • resolution: resolution is not limited (corresponds to ADC resolution configured).
  • AWD flexible (instances AWD2, AWD3):
    • channels monitored: flexible on channels monitored, selection is channel wise, from from 1 to all channels. Specificity of this analog watchdog: Multiple channels can be selected. For example: (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
    • groups monitored: not selection possible (monitoring on both groups regular and injected). Channels selected are monitored on groups regular and injected: LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
    • resolution: resolution is limited to 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
If ADC oversampling is enabled, ADC analog watchdog thresholds are impacted: the comparison of analog watchdog thresholds is done on oversampling final computation (after ratio and shift application): ADC data register bitfield [15:4] (12 most significant bits).
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
TR1 HT1 LL_ADC_ConfigAnalogWDThresholds
TR2 HT2 LL_ADC_ConfigAnalogWDThresholds
TR3 HT3 LL_ADC_ConfigAnalogWDThresholds
TR1 LT1 LL_ADC_ConfigAnalogWDThresholds
TR2 LT2 LL_ADC_ConfigAnalogWDThresholds
TR3 LT3 LL_ADC_ConfigAnalogWDThresholds
Parameters:
ADCx | ADC instance
AWDy This parameter can be one of the following values:
  • LL_ADC_AWD1
  • LL_ADC_AWD2
  • LL_ADC_AWD3
AWDThresholdHighValue | Value between Min_Data=0x000 and Max_Data=0xFFF
AWDThresholdLowValue | Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
None

Definition at line 4530 of file stm32wbxx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, ADC_AWD_TRX_REGOFFSET_MASK, ADC_AWD_TRX_REGOFFSET_POS, and ADC_TR1_HT1_BITOFFSET_POS.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | AWDy
 | ) |  |

Get ADC analog watchdog monitored channel.

Note:
Usage of the returned channel number:
  • To reinject this channel into another function LL_ADC_xxx: the returned channel number is only partly formatted on definition of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared with parts of literals LL_ADC_CHANNEL_x or using helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB(). Then the selected literal LL_ADC_CHANNEL_x can be used as parameter for another function.
  • To get the channel number in decimal format: process the returned value with the helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB(). Applicable only when the analog watchdog is set to monitor one channel.
On this STM32 serie, there are 2 kinds of analog watchdog instance:
  • AWD standard (instance AWD1):
    • channels monitored: can monitor 1 channel or all channels.
    • groups monitored: ADC groups regular and-or injected.
    • resolution: resolution is not limited (corresponds to ADC resolution configured).
  • AWD flexible (instances AWD2, AWD3):
    • channels monitored: flexible on channels monitored, selection is channel wise, from from 1 to all channels. Specificity of this analog watchdog: Multiple channels can be selected. For example: (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
    • groups monitored: not selection possible (monitoring on both groups regular and injected). Channels selected are monitored on groups regular and injected: LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
    • resolution: resolution is limited to 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels
CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels
CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels
CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels
AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels
AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
Parameters:
ADCx ADC instance
AWDy This parameter can be one of the following values:
  • LL_ADC_AWD1
  • LL_ADC_AWD2 (1)
  • LL_ADC_AWD3 (1)
(1) On this AWD number, monitored channel can be retrieved if only 1 channel is programmed (or none or all channels). This function cannot retrieve monitored channel if multiple channels are programmed simultaneously by bitfield.
Return values:
Returned value can be one of the following values:
  • LL_ADC_AWD_DISABLE
  • LL_ADC_AWD_ALL_CHANNELS_REG (0)
  • LL_ADC_AWD_ALL_CHANNELS_INJ (0)
  • LL_ADC_AWD_ALL_CHANNELS_REG_INJ
  • LL_ADC_AWD_CHANNEL_0_REG (0)
  • LL_ADC_AWD_CHANNEL_0_INJ (0)
  • LL_ADC_AWD_CHANNEL_0_REG_INJ
  • LL_ADC_AWD_CHANNEL_1_REG (0)
  • LL_ADC_AWD_CHANNEL_1_INJ (0)
  • LL_ADC_AWD_CHANNEL_1_REG_INJ
  • LL_ADC_AWD_CHANNEL_2_REG (0)
  • LL_ADC_AWD_CHANNEL_2_INJ (0)
  • LL_ADC_AWD_CHANNEL_2_REG_INJ
  • LL_ADC_AWD_CHANNEL_3_REG (0)
  • LL_ADC_AWD_CHANNEL_3_INJ (0)
  • LL_ADC_AWD_CHANNEL_3_REG_INJ
  • LL_ADC_AWD_CHANNEL_4_REG (0)
  • LL_ADC_AWD_CHANNEL_4_INJ (0)
  • LL_ADC_AWD_CHANNEL_4_REG_INJ
  • LL_ADC_AWD_CHANNEL_5_REG (0)
  • LL_ADC_AWD_CHANNEL_5_INJ (0)
  • LL_ADC_AWD_CHANNEL_5_REG_INJ
  • LL_ADC_AWD_CHANNEL_6_REG (0)
  • LL_ADC_AWD_CHANNEL_6_INJ (0)
  • LL_ADC_AWD_CHANNEL_6_REG_INJ
  • LL_ADC_AWD_CHANNEL_7_REG (0)
  • LL_ADC_AWD_CHANNEL_7_INJ (0)
  • LL_ADC_AWD_CHANNEL_7_REG_INJ
  • LL_ADC_AWD_CHANNEL_8_REG (0)
  • LL_ADC_AWD_CHANNEL_8_INJ (0)
  • LL_ADC_AWD_CHANNEL_8_REG_INJ
  • LL_ADC_AWD_CHANNEL_9_REG (0)
  • LL_ADC_AWD_CHANNEL_9_INJ (0)
  • LL_ADC_AWD_CHANNEL_9_REG_INJ
  • LL_ADC_AWD_CHANNEL_10_REG (0)
  • LL_ADC_AWD_CHANNEL_10_INJ (0)
  • LL_ADC_AWD_CHANNEL_10_REG_INJ
  • LL_ADC_AWD_CHANNEL_11_REG (0)
  • LL_ADC_AWD_CHANNEL_11_INJ (0)
  • LL_ADC_AWD_CHANNEL_11_REG_INJ
  • LL_ADC_AWD_CHANNEL_12_REG (0)
  • LL_ADC_AWD_CHANNEL_12_INJ (0)
  • LL_ADC_AWD_CHANNEL_12_REG_INJ
  • LL_ADC_AWD_CHANNEL_13_REG (0)
  • LL_ADC_AWD_CHANNEL_13_INJ (0)
  • LL_ADC_AWD_CHANNEL_13_REG_INJ
  • LL_ADC_AWD_CHANNEL_14_REG (0)
  • LL_ADC_AWD_CHANNEL_14_INJ (0)
  • LL_ADC_AWD_CHANNEL_14_REG_INJ
  • LL_ADC_AWD_CHANNEL_15_REG (0)
  • LL_ADC_AWD_CHANNEL_15_INJ (0)
  • LL_ADC_AWD_CHANNEL_15_REG_INJ
  • LL_ADC_AWD_CHANNEL_16_REG (0)
  • LL_ADC_AWD_CHANNEL_16_INJ (0)
  • LL_ADC_AWD_CHANNEL_16_REG_INJ
  • LL_ADC_AWD_CHANNEL_17_REG (0)
  • LL_ADC_AWD_CHANNEL_17_INJ (0)
  • LL_ADC_AWD_CHANNEL_17_REG_INJ
  • LL_ADC_AWD_CHANNEL_18_REG (0)
  • LL_ADC_AWD_CHANNEL_18_INJ (0)
  • LL_ADC_AWD_CHANNEL_18_REG_INJ
(0) On STM32WB, parameter available only on analog watchdog number: AWD1.

Definition at line 4422 of file stm32wbxx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, __LL_ADC_CHANNEL_TO_DECIMAL_NB, ADC_AWD_CR12_REGOFFSETGAP_MASK, ADC_AWD_CR12_REGOFFSETGAP_VAL, ADC_AWD_CR23_CHANNEL_MASK, ADC_AWD_CR_ALL_CHANNEL_MASK, ADC_AWD_CRX_REGOFFSET_MASK, ADC_AWD_CRX_REGOFFSET_POS, and LL_ADC_AWD1.

__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | AWDy,
 |  | uint32_t | AWDThresholdsHighLow
 | ) |  |

Get ADC analog watchdog threshold value of threshold high, threshold low or raw data with ADC thresholds high and low concatenated.

Note:
If raw data with ADC thresholds high and low is retrieved, the data of each threshold high or low can be isolated using helper macro: __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
In case of ADC resolution different of 12 bits, analog watchdog thresholds data require a specific shift. Use helper macro __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
Reference Manual to LL API cross reference:
TR1 HT1 LL_ADC_GetAnalogWDThresholds
TR2 HT2 LL_ADC_GetAnalogWDThresholds
TR3 HT3 LL_ADC_GetAnalogWDThresholds
TR1 LT1 LL_ADC_GetAnalogWDThresholds
TR2 LT2 LL_ADC_GetAnalogWDThresholds
TR3 LT3 LL_ADC_GetAnalogWDThresholds
Parameters:
ADCx ADC instance
AWDy This parameter can be one of the following values:
  • LL_ADC_AWD1
  • LL_ADC_AWD2
  • LL_ADC_AWD3
AWDThresholdsHighLow This parameter can be one of the following values:
  • LL_ADC_AWD_THRESHOLD_HIGH
  • LL_ADC_AWD_THRESHOLD_LOW
  • LL_ADC_AWD_THRESHOLDS_HIGH_LOW
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 4642 of file stm32wbxx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, ADC_AWD_TRX_BIT_HIGH_MASK, ADC_AWD_TRX_BIT_HIGH_SHIFT4, ADC_AWD_TRX_REGOFFSET_MASK, and ADC_AWD_TRX_REGOFFSET_POS.

__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | AWDy,
 |  | uint32_t | AWDChannelGroup
 | ) |  |

Set ADC analog watchdog monitored channels: a single channel, multiple channels or all channels, on ADC groups regular and-or injected.

Note:
Once monitored channels are selected, analog watchdog is enabled.
In case of need to define a single channel to monitor with analog watchdog from sequencer channel definition, use helper macro __LL_ADC_ANALOGWD_CHANNEL_GROUP().
On this STM32 serie, there are 2 kinds of analog watchdog instance:
  • AWD standard (instance AWD1):
    • channels monitored: can monitor 1 channel or all channels.
    • groups monitored: ADC groups regular and-or injected.
    • resolution: resolution is not limited (corresponds to ADC resolution configured).
  • AWD flexible (instances AWD2, AWD3):
    • channels monitored: flexible on channels monitored, selection is channel wise, from from 1 to all channels. Specificity of this analog watchdog: Multiple channels can be selected. For example: (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
    • groups monitored: not selection possible (monitoring on both groups regular and injected). Channels selected are monitored on groups regular and injected: LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
    • resolution: resolution is limited to 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels
CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels
CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels
CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels
AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels
AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
Parameters:
ADCx ADC instance
AWDy This parameter can be one of the following values:
  • LL_ADC_AWD1
  • LL_ADC_AWD2
  • LL_ADC_AWD3
AWDChannelGroup This parameter can be one of the following values:
  • LL_ADC_AWD_DISABLE
  • LL_ADC_AWD_ALL_CHANNELS_REG (0)
  • LL_ADC_AWD_ALL_CHANNELS_INJ (0)
  • LL_ADC_AWD_ALL_CHANNELS_REG_INJ
  • LL_ADC_AWD_CHANNEL_0_REG (0)
  • LL_ADC_AWD_CHANNEL_0_INJ (0)
  • LL_ADC_AWD_CHANNEL_0_REG_INJ
  • LL_ADC_AWD_CHANNEL_1_REG (0)
  • LL_ADC_AWD_CHANNEL_1_INJ (0)
  • LL_ADC_AWD_CHANNEL_1_REG_INJ
  • LL_ADC_AWD_CHANNEL_2_REG (0)
  • LL_ADC_AWD_CHANNEL_2_INJ (0)
  • LL_ADC_AWD_CHANNEL_2_REG_INJ
  • LL_ADC_AWD_CHANNEL_3_REG (0)
  • LL_ADC_AWD_CHANNEL_3_INJ (0)
  • LL_ADC_AWD_CHANNEL_3_REG_INJ
  • LL_ADC_AWD_CHANNEL_4_REG (0)
  • LL_ADC_AWD_CHANNEL_4_INJ (0)
  • LL_ADC_AWD_CHANNEL_4_REG_INJ
  • LL_ADC_AWD_CHANNEL_5_REG (0)
  • LL_ADC_AWD_CHANNEL_5_INJ (0)
  • LL_ADC_AWD_CHANNEL_5_REG_INJ
  • LL_ADC_AWD_CHANNEL_6_REG (0)
  • LL_ADC_AWD_CHANNEL_6_INJ (0)
  • LL_ADC_AWD_CHANNEL_6_REG_INJ
  • LL_ADC_AWD_CHANNEL_7_REG (0)
  • LL_ADC_AWD_CHANNEL_7_INJ (0)
  • LL_ADC_AWD_CHANNEL_7_REG_INJ
  • LL_ADC_AWD_CHANNEL_8_REG (0)
  • LL_ADC_AWD_CHANNEL_8_INJ (0)
  • LL_ADC_AWD_CHANNEL_8_REG_INJ
  • LL_ADC_AWD_CHANNEL_9_REG (0)
  • LL_ADC_AWD_CHANNEL_9_INJ (0)
  • LL_ADC_AWD_CHANNEL_9_REG_INJ
  • LL_ADC_AWD_CHANNEL_10_REG (0)
  • LL_ADC_AWD_CHANNEL_10_INJ (0)
  • LL_ADC_AWD_CHANNEL_10_REG_INJ
  • LL_ADC_AWD_CHANNEL_11_REG (0)
  • LL_ADC_AWD_CHANNEL_11_INJ (0)
  • LL_ADC_AWD_CHANNEL_11_REG_INJ
  • LL_ADC_AWD_CHANNEL_12_REG (0)
  • LL_ADC_AWD_CHANNEL_12_INJ (0)
  • LL_ADC_AWD_CHANNEL_12_REG_INJ
  • LL_ADC_AWD_CHANNEL_13_REG (0)
  • LL_ADC_AWD_CHANNEL_13_INJ (0)
  • LL_ADC_AWD_CHANNEL_13_REG_INJ
  • LL_ADC_AWD_CHANNEL_14_REG (0)
  • LL_ADC_AWD_CHANNEL_14_INJ (0)
  • LL_ADC_AWD_CHANNEL_14_REG_INJ
  • LL_ADC_AWD_CHANNEL_15_REG (0)
  • LL_ADC_AWD_CHANNEL_15_INJ (0)
  • LL_ADC_AWD_CHANNEL_15_REG_INJ
  • LL_ADC_AWD_CHANNEL_16_REG (0)
  • LL_ADC_AWD_CHANNEL_16_INJ (0)
  • LL_ADC_AWD_CHANNEL_16_REG_INJ
  • LL_ADC_AWD_CHANNEL_17_REG (0)
  • LL_ADC_AWD_CHANNEL_17_INJ (0)
  • LL_ADC_AWD_CHANNEL_17_REG_INJ
  • LL_ADC_AWD_CHANNEL_18_REG (0)
  • LL_ADC_AWD_CHANNEL_18_INJ (0)
  • LL_ADC_AWD_CHANNEL_18_REG_INJ
  • LL_ADC_AWD_CH_VREFINT_REG (0)
  • LL_ADC_AWD_CH_VREFINT_INJ (0)
  • LL_ADC_AWD_CH_VREFINT_REG_INJ
  • LL_ADC_AWD_CH_TEMPSENSOR_REG (0)
  • LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)
  • LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ
  • LL_ADC_AWD_CH_VBAT_REG (0)
  • LL_ADC_AWD_CH_VBAT_INJ (0)
  • LL_ADC_AWD_CH_VBAT_REG_INJ
(0) On STM32WB, parameter available only on analog watchdog number: AWD1.
Return values:
None

Definition at line 4286 of file stm32wbxx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, ADC_AWD_CR12_REGOFFSETGAP_MASK, ADC_AWD_CR12_REGOFFSETGAP_VAL, ADC_AWD_CR_ALL_CHANNEL_MASK, ADC_AWD_CRX_REGOFFSET_MASK, and ADC_AWD_CRX_REGOFFSET_POS.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | AWDy,
 |  | uint32_t | AWDThresholdsHighLow,
 |  | uint32_t | AWDThresholdValue
 | ) |  |

Set ADC analog watchdog threshold value of threshold high or low.

Note:
If values of both thresholds high or low must be set, use function LL_ADC_ConfigAnalogWDThresholds().
In case of ADC resolution different of 12 bits, analog watchdog thresholds data require a specific shift. Use helper macro __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
On this STM32 serie, there are 2 kinds of analog watchdog instance:
  • AWD standard (instance AWD1):
    • channels monitored: can monitor 1 channel or all channels.
    • groups monitored: ADC groups regular and-or injected.
    • resolution: resolution is not limited (corresponds to ADC resolution configured).
  • AWD flexible (instances AWD2, AWD3):
    • channels monitored: flexible on channels monitored, selection is channel wise, from from 1 to all channels. Specificity of this analog watchdog: Multiple channels can be selected. For example: (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
    • groups monitored: not selection possible (monitoring on both groups regular and injected). Channels selected are monitored on groups regular and injected: LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
    • resolution: resolution is limited to 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
If ADC oversampling is enabled, ADC analog watchdog thresholds are impacted: the comparison of analog watchdog thresholds is done on oversampling final computation (after ratio and shift application): ADC data register bitfield [15:4] (12 most significant bits).
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either ADC groups regular or injected.
Reference Manual to LL API cross reference:
TR1 HT1 LL_ADC_SetAnalogWDThresholds
TR2 HT2 LL_ADC_SetAnalogWDThresholds
TR3 HT3 LL_ADC_SetAnalogWDThresholds
TR1 LT1 LL_ADC_SetAnalogWDThresholds
TR2 LT2 LL_ADC_SetAnalogWDThresholds
TR3 LT3 LL_ADC_SetAnalogWDThresholds
Parameters:
ADCx | ADC instance
AWDy This parameter can be one of the following values:
  • LL_ADC_AWD1
  • LL_ADC_AWD2
  • LL_ADC_AWD3
AWDThresholdsHighLow This parameter can be one of the following values:
  • LL_ADC_AWD_THRESHOLD_HIGH
  • LL_ADC_AWD_THRESHOLD_LOW
AWDThresholdValue | Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
None

Definition at line 4599 of file stm32wbxx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, ADC_AWD_TRX_BIT_HIGH_MASK, ADC_AWD_TRX_BIT_HIGH_SHIFT4, ADC_AWD_TRX_REGOFFSET_MASK, and ADC_AWD_TRX_REGOFFSET_POS.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Configuration of ADC transversal scope: oversampling

Functions
Configuration of ADC transversal scope: oversampling
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_SetOverSamplingScope (ADC_TypeDef *ADCx, uint32_t OvsScope)
Set ADC oversampling scope: ADC groups regular and-or injected (availability of ADC group injected depends on STM32 families).
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingScope (ADC_TypeDef *ADCx)
Get ADC oversampling scope: ADC groups regular and-or injected (availability of ADC group injected depends on STM32 families).
__STATIC_INLINE void | LL_ADC_SetOverSamplingDiscont (ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
Set ADC oversampling discontinuous mode (triggered mode) on the selected ADC group.
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingDiscont (ADC_TypeDef *ADCx)
Get ADC oversampling discontinuous mode (triggered mode) on the selected ADC group.
__STATIC_INLINE void | LL_ADC_ConfigOverSamplingRatioShift (ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
Set ADC oversampling (impacting both ADC groups regular and injected)
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingRatio (ADC_TypeDef *ADCx)
Get ADC oversampling ratio (impacting both ADC groups regular and injected)
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingShift (ADC_TypeDef *ADCx)
Get ADC oversampling shift (impacting both ADC groups regular and injected)

Function Documentation

__STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Ratio,
 |  | uint32_t | Shift
 | ) |  |

Set ADC oversampling (impacting both ADC groups regular and injected)

Note:
This function set the 2 items of oversampling configuration:
  • ratio
  • shift
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift
CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift
Parameters:
ADCx ADC instance
Ratio This parameter can be one of the following values:
  • LL_ADC_OVS_RATIO_2
  • LL_ADC_OVS_RATIO_4
  • LL_ADC_OVS_RATIO_8
  • LL_ADC_OVS_RATIO_16
  • LL_ADC_OVS_RATIO_32
  • LL_ADC_OVS_RATIO_64
  • LL_ADC_OVS_RATIO_128
  • LL_ADC_OVS_RATIO_256
Shift This parameter can be one of the following values:
  • LL_ADC_OVS_SHIFT_NONE
  • LL_ADC_OVS_SHIFT_RIGHT_1
  • LL_ADC_OVS_SHIFT_RIGHT_2
  • LL_ADC_OVS_SHIFT_RIGHT_3
  • LL_ADC_OVS_SHIFT_RIGHT_4
  • LL_ADC_OVS_SHIFT_RIGHT_5
  • LL_ADC_OVS_SHIFT_RIGHT_6
  • LL_ADC_OVS_SHIFT_RIGHT_7
  • LL_ADC_OVS_SHIFT_RIGHT_8
Return values:
None

Definition at line 4795 of file stm32wbxx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont ( ADC_TypeDef * ADCx )

Get ADC oversampling discontinuous mode (triggered mode) on the selected ADC group.

Note:
Number of oversampled conversions are done either in:
  • continuous mode (all conversions of oversampling ratio are done from 1 trigger)
  • discontinuous mode (each conversion of oversampling ratio needs a trigger)
Reference Manual to LL API cross reference:
CFGR2 TROVS LL_ADC_GetOverSamplingDiscont
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_OVS_REG_CONT
  • LL_ADC_OVS_REG_DISCONT

Definition at line 4756 of file stm32wbxx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio ( ADC_TypeDef * ADCx )

Get ADC oversampling ratio (impacting both ADC groups regular and injected)

Reference Manual to LL API cross reference:
CFGR2 OVSR LL_ADC_GetOverSamplingRatio
Parameters:
ADCx ADC instance
Return values:
Ratio This parameter can be one of the following values:
  • LL_ADC_OVS_RATIO_2
  • LL_ADC_OVS_RATIO_4
  • LL_ADC_OVS_RATIO_8
  • LL_ADC_OVS_RATIO_16
  • LL_ADC_OVS_RATIO_32
  • LL_ADC_OVS_RATIO_64
  • LL_ADC_OVS_RATIO_128
  • LL_ADC_OVS_RATIO_256

Definition at line 4815 of file stm32wbxx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope ( ADC_TypeDef * ADCx )

Get ADC oversampling scope: ADC groups regular and-or injected (availability of ADC group injected depends on STM32 families).

Note:
If both groups regular and injected are selected, specify behavior of ADC group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is either temporary stopped and continued, or resumed from start (oversampler buffer reset).
Reference Manual to LL API cross reference:
CFGR2 ROVSE LL_ADC_GetOverSamplingScope
CFGR2 JOVSE LL_ADC_GetOverSamplingScope
CFGR2 ROVSM LL_ADC_GetOverSamplingScope
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_OVS_DISABLE
  • LL_ADC_OVS_GRP_REGULAR_CONTINUED
  • LL_ADC_OVS_GRP_REGULAR_RESUMED
  • LL_ADC_OVS_GRP_INJECTED
  • LL_ADC_OVS_GRP_INJ_REG_RESUMED

Definition at line 4710 of file stm32wbxx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift ( ADC_TypeDef * ADCx )

Get ADC oversampling shift (impacting both ADC groups regular and injected)

Reference Manual to LL API cross reference:
CFGR2 OVSS LL_ADC_GetOverSamplingShift
Parameters:
ADCx ADC instance
Return values:
Shift This parameter can be one of the following values:
  • LL_ADC_OVS_SHIFT_NONE
  • LL_ADC_OVS_SHIFT_RIGHT_1
  • LL_ADC_OVS_SHIFT_RIGHT_2
  • LL_ADC_OVS_SHIFT_RIGHT_3
  • LL_ADC_OVS_SHIFT_RIGHT_4
  • LL_ADC_OVS_SHIFT_RIGHT_5
  • LL_ADC_OVS_SHIFT_RIGHT_6
  • LL_ADC_OVS_SHIFT_RIGHT_7
  • LL_ADC_OVS_SHIFT_RIGHT_8

Definition at line 4836 of file stm32wbxx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetOverSamplingDiscont | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | OverSamplingDiscont
 | ) |  |

Set ADC oversampling discontinuous mode (triggered mode) on the selected ADC group.

Note:
Number of oversampled conversions are done either in:
  • continuous mode (all conversions of oversampling ratio are done from 1 trigger)
  • discontinuous mode (each conversion of oversampling ratio needs a trigger)
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular.
On this STM32 serie, oversampling discontinuous mode (triggered mode) can be used only when oversampling is set on group regular only and in resumed mode.
Reference Manual to LL API cross reference:
CFGR2 TROVS LL_ADC_SetOverSamplingDiscont
Parameters:
ADCx ADC instance
OverSamplingDiscont This parameter can be one of the following values:
  • LL_ADC_OVS_REG_CONT
  • LL_ADC_OVS_REG_DISCONT
Return values:
None

Definition at line 4737 of file stm32wbxx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetOverSamplingScope | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | OvsScope
 | ) |  |

Set ADC oversampling scope: ADC groups regular and-or injected (availability of ADC group injected depends on STM32 families).

Note:
If both groups regular and injected are selected, specify behavior of ADC group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is either temporary stopped and continued, or resumed from start (oversampler buffer reset).
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CFGR2 ROVSE LL_ADC_SetOverSamplingScope
CFGR2 JOVSE LL_ADC_SetOverSamplingScope
CFGR2 ROVSM LL_ADC_SetOverSamplingScope
Parameters:
ADCx ADC instance
OvsScope This parameter can be one of the following values:
  • LL_ADC_OVS_DISABLE
  • LL_ADC_OVS_GRP_REGULAR_CONTINUED
  • LL_ADC_OVS_GRP_REGULAR_RESUMED
  • LL_ADC_OVS_GRP_INJECTED
  • LL_ADC_OVS_GRP_INJ_REG_RESUMED
Return values:
None

Definition at line 4685 of file stm32wbxx_ll_adc.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Operation on ADC hierarchical scope: ADC instance

Functions
Operation on ADC hierarchical scope: ADC instance
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_EnableDeepPowerDown (ADC_TypeDef *ADCx)
Put ADC instance in deep power down state.
__STATIC_INLINE void | LL_ADC_DisableDeepPowerDown (ADC_TypeDef *ADCx)
Disable ADC deep power down mode.
__STATIC_INLINE uint32_t | LL_ADC_IsDeepPowerDownEnabled (ADC_TypeDef *ADCx)
Get the selected ADC instance deep power down state.
__STATIC_INLINE void | LL_ADC_EnableInternalRegulator (ADC_TypeDef *ADCx)
Enable ADC instance internal voltage regulator.
__STATIC_INLINE void | LL_ADC_DisableInternalRegulator (ADC_TypeDef *ADCx)
Disable ADC internal voltage regulator.
__STATIC_INLINE uint32_t | LL_ADC_IsInternalRegulatorEnabled (ADC_TypeDef *ADCx)
Get the selected ADC instance internal voltage regulator state.
__STATIC_INLINE void | LL_ADC_Enable (ADC_TypeDef *ADCx)
Enable the selected ADC instance.
__STATIC_INLINE void | LL_ADC_Disable (ADC_TypeDef *ADCx)
Disable the selected ADC instance.
__STATIC_INLINE uint32_t | LL_ADC_IsEnabled (ADC_TypeDef *ADCx)
Get the selected ADC instance enable state.
__STATIC_INLINE uint32_t | LL_ADC_IsDisableOngoing (ADC_TypeDef *ADCx)
Get the selected ADC instance disable state.
__STATIC_INLINE void | LL_ADC_StartCalibration (ADC_TypeDef *ADCx, uint32_t SingleDiff)
Start ADC calibration in the mode single-ended or differential (for devices with differential mode available).
__STATIC_INLINE uint32_t | LL_ADC_IsCalibrationOnGoing (ADC_TypeDef *ADCx)
Get ADC calibration state.

Function Documentation

__STATIC_INLINE void LL_ADC_Disable ( ADC_TypeDef * ADCx )

Disable the selected ADC instance.

Note:
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be not disabled. Must be enabled without conversion on going on either groups regular or injected.
Reference Manual to LL API cross reference:
CR ADDIS LL_ADC_Disable
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4989 of file stm32wbxx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

Referenced by ADC_Disable(), and LL_ADC_DeInit().

__STATIC_INLINE void LL_ADC_DisableDeepPowerDown ( ADC_TypeDef * ADCx )

Disable ADC deep power down mode.

Note:
In case of ADC calibration necessary: When ADC is in deep-power-down state, the internal analog calibration is lost. After exiting from deep power down, calibration must be relaunched or calibration factor (preliminarily saved) must be set back into calibration register.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be ADC disabled.
Reference Manual to LL API cross reference:
CR DEEPPWD LL_ADC_DisableDeepPowerDown
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4885 of file stm32wbxx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

Referenced by HAL_ADC_Init().

__STATIC_INLINE void LL_ADC_DisableInternalRegulator ( ADC_TypeDef * ADCx )

Disable ADC internal voltage regulator.

Note:
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be ADC disabled.
Reference Manual to LL API cross reference:
CR ADVREGEN LL_ADC_DisableInternalRegulator
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4937 of file stm32wbxx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

Referenced by HAL_ADCEx_DisableVoltageRegulator().

__STATIC_INLINE void LL_ADC_Enable ( ADC_TypeDef * ADCx )

Enable the selected ADC instance.

Note:
On this STM32 serie, after ADC enable, a delay for ADC internal analog stabilization is required before performing a ADC conversion start. Refer to device datasheet, parameter tSTAB.
On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC is enabled and when conversion clock is active. (not only core clock: this ADC has a dual clock domain)
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be ADC disabled and ADC internal voltage regulator enabled.
Reference Manual to LL API cross reference:
CR ADEN LL_ADC_Enable
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4969 of file stm32wbxx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

Referenced by ADC_Enable().

__STATIC_INLINE void LL_ADC_EnableDeepPowerDown ( ADC_TypeDef * ADCx )

Put ADC instance in deep power down state.

Note:
In case of ADC calibration necessary: When ADC is in deep-power-down state, the internal analog calibration is lost. After exiting from deep power down, calibration must be relaunched or calibration factor (preliminarily saved) must be set back into calibration register.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be ADC disabled.
Reference Manual to LL API cross reference:
CR DEEPPWD LL_ADC_EnableDeepPowerDown
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4862 of file stm32wbxx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

Referenced by HAL_ADCEx_EnterADCDeepPowerDownMode().

__STATIC_INLINE void LL_ADC_EnableInternalRegulator ( ADC_TypeDef * ADCx )

Enable ADC instance internal voltage regulator.

Note:
On this STM32 serie, after ADC internal voltage regulator enable, a delay for ADC internal voltage regulator stabilization is required before performing a ADC calibration or ADC enable. Refer to device datasheet, parameter tADCVREG_STUP. Refer to literal LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be ADC disabled.
Reference Manual to LL API cross reference:
CR ADVREGEN LL_ADC_EnableInternalRegulator
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 4918 of file stm32wbxx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

Referenced by HAL_ADC_Init().

__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing ( ADC_TypeDef * ADCx )

Get ADC calibration state.

Reference Manual to LL API cross reference:
CR ADCAL LL_ADC_IsCalibrationOnGoing
Parameters:
ADCx ADC instance
Return values:
0,: calibration complete, 1: calibration in progress.

Definition at line 5063 of file stm32wbxx_ll_adc.h.

Referenced by HAL_ADCEx_Calibration_Start().

__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled ( ADC_TypeDef * ADCx )

Get the selected ADC instance deep power down state.

Reference Manual to LL API cross reference:
CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled
Parameters:
ADCx ADC instance
Return values:
0,: deep power down is disabled, 1: deep power down is enabled.

Definition at line 4899 of file stm32wbxx_ll_adc.h.

Referenced by HAL_ADC_Init().

__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing ( ADC_TypeDef * ADCx )

Get the selected ADC instance disable state.

Reference Manual to LL API cross reference:
CR ADDIS LL_ADC_IsDisableOngoing
Parameters:
ADCx ADC instance
Return values:
0,: no ADC disable command on going.

Definition at line 5019 of file stm32wbxx_ll_adc.h.

Referenced by ADC_ConversionStop(), ADC_Disable(), and LL_ADC_DeInit().

__STATIC_INLINE uint32_t LL_ADC_IsEnabled ( ADC_TypeDef * ADCx )

Get the selected ADC instance enable state.

Note:
On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC is enabled and when conversion clock is active. (not only core clock: this ADC has a dual clock domain)
Reference Manual to LL API cross reference:
CR ADEN LL_ADC_IsEnabled
Parameters:
ADCx ADC instance
Return values:
0,: ADC is disabled, 1: ADC is enabled.

Definition at line 5008 of file stm32wbxx_ll_adc.h.

Referenced by ADC_Disable(), ADC_Enable(), HAL_ADC_ConfigChannel(), HAL_ADC_Init(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_DisableVoltageRegulator(), HAL_ADCEx_EnterADCDeepPowerDownMode(), HAL_ADCEx_InjectedConfigChannel(), LL_ADC_DeInit(), LL_ADC_Init(), LL_ADC_INJ_Init(), and LL_ADC_REG_Init().

__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled ( ADC_TypeDef * ADCx )

Get the selected ADC instance internal voltage regulator state.

Reference Manual to LL API cross reference:
CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
Parameters:
ADCx ADC instance
Return values:
0,: internal regulator is disabled, 1: internal regulator is enabled.

Definition at line 4948 of file stm32wbxx_ll_adc.h.

Referenced by HAL_ADC_Init().

__STATIC_INLINE void LL_ADC_StartCalibration | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SingleDiff
 | ) |  |

Start ADC calibration in the mode single-ended or differential (for devices with differential mode available).

Note:
On this STM32 serie, a minimum number of ADC clock cycles are required between ADC end of calibration and ADC enable. Refer to literal LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
For devices with differential mode available: Calibration of offset is specific to each of single-ended and differential modes (calibration run must be performed for each of these differential modes, if used afterwards and if the application requires their calibration).
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be ADC disabled.
Reference Manual to LL API cross reference:
CR ADCAL LL_ADC_StartCalibration
CR ADCALDIF LL_ADC_StartCalibration
Parameters:
ADCx ADC instance
SingleDiff This parameter can be one of the following values:
  • LL_ADC_SINGLE_ENDED
  • LL_ADC_DIFFERENTIAL_ENDED
Return values:
None

Definition at line 5047 of file stm32wbxx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS, and ADC_SINGLEDIFF_CALIB_START_MASK.

Referenced by HAL_ADCEx_Calibration_Start().

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Operation on ADC hierarchical scope: group regular

Functions
Operation on ADC hierarchical scope: group regular
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_REG_StartConversion (ADC_TypeDef *ADCx)
Start ADC group regular conversion.
__STATIC_INLINE void | LL_ADC_REG_StopConversion (ADC_TypeDef *ADCx)
Stop ADC group regular conversion.
__STATIC_INLINE uint32_t | LL_ADC_REG_IsConversionOngoing (ADC_TypeDef *ADCx)
Get ADC group regular conversion state.
__STATIC_INLINE uint32_t | LL_ADC_REG_IsStopConversionOngoing (ADC_TypeDef *ADCx)
Get ADC group regular command of conversion stop state.
__STATIC_INLINE uint32_t | LL_ADC_REG_ReadConversionData32 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).
__STATIC_INLINE uint16_t | LL_ADC_REG_ReadConversionData12 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 12 bits.
__STATIC_INLINE uint16_t | LL_ADC_REG_ReadConversionData10 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 10 bits.
__STATIC_INLINE uint8_t | LL_ADC_REG_ReadConversionData8 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 8 bits.
__STATIC_INLINE uint8_t | LL_ADC_REG_ReadConversionData6 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 6 bits.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing ( ADC_TypeDef * ADCx )

Get ADC group regular conversion state.

Reference Manual to LL API cross reference:
CR ADSTART LL_ADC_REG_IsConversionOngoing
Parameters:
ADCx ADC instance
Return values:
0,: no conversion is on going on ADC group regular.

Definition at line 5130 of file stm32wbxx_ll_adc.h.

Referenced by ADC_ConversionStop(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_DisableInjectedQueue(), HAL_ADCEx_EnableInjectedQueue(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), and LL_ADC_DeInit().

__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing ( ADC_TypeDef * ADCx )

Get ADC group regular command of conversion stop state.

Reference Manual to LL API cross reference:
CR ADSTP LL_ADC_REG_IsStopConversionOngoing
Parameters:
ADCx ADC instance
Return values:
0,: no command of conversion stop is on going on ADC group regular.

Definition at line 5141 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_DeInit().

__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10 ( ADC_TypeDef * ADCx )

Get ADC group regular conversion data, range fit for ADC resolution 10 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_REG_ReadConversionData32.
Reference Manual to LL API cross reference:
DR RDATA LL_ADC_REG_ReadConversionData10
Parameters:
ADCx ADC instance
Return values:
Value between Min_Data=0x000 and Max_Data=0x3FF

Definition at line 5185 of file stm32wbxx_ll_adc.h.

__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12 ( ADC_TypeDef * ADCx )

Get ADC group regular conversion data, range fit for ADC resolution 12 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_REG_ReadConversionData32.
Reference Manual to LL API cross reference:
DR RDATA LL_ADC_REG_ReadConversionData12
Parameters:
ADCx ADC instance
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 5170 of file stm32wbxx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32 ( ADC_TypeDef * ADCx )

Get ADC group regular conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).

Reference Manual to LL API cross reference:
DR RDATA LL_ADC_REG_ReadConversionData32
Parameters:
ADCx ADC instance
Return values:
Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

Definition at line 5155 of file stm32wbxx_ll_adc.h.

__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6 ( ADC_TypeDef * ADCx )

Get ADC group regular conversion data, range fit for ADC resolution 6 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_REG_ReadConversionData32.
Reference Manual to LL API cross reference:
DR RDATA LL_ADC_REG_ReadConversionData6
Parameters:
ADCx ADC instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x3F

Definition at line 5215 of file stm32wbxx_ll_adc.h.

__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8 ( ADC_TypeDef * ADCx )

Get ADC group regular conversion data, range fit for ADC resolution 8 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_REG_ReadConversionData32.
Reference Manual to LL API cross reference:
DR RDATA LL_ADC_REG_ReadConversionData8
Parameters:
ADCx ADC instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 5200 of file stm32wbxx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_StartConversion ( ADC_TypeDef * ADCx )

Start ADC group regular conversion.

Note:
On this STM32 serie, this function is relevant for both internal trigger (SW start) and external trigger:
  • If ADC trigger has been set to software start, ADC conversion starts immediately.
  • If ADC trigger has been set to external trigger, ADC conversion will start at next trigger event (on the selected trigger edge) following the ADC start conversion command.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be enabled without conversion on going on group regular, without conversion stop command on going on group regular, without ADC disable command on going.
Reference Manual to LL API cross reference:
CR ADSTART LL_ADC_REG_StartConversion
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5094 of file stm32wbxx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

Referenced by HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

__STATIC_INLINE void LL_ADC_REG_StopConversion ( ADC_TypeDef * ADCx )

Stop ADC group regular conversion.

Note:
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be enabled with conversion on going on group regular, without ADC disable command on going.
Reference Manual to LL API cross reference:
CR ADSTP LL_ADC_REG_StopConversion
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5114 of file stm32wbxx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

Referenced by ADC_ConversionStop(), and LL_ADC_DeInit().

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Operation on ADC hierarchical scope: group injected

Functions
Operation on ADC hierarchical scope: group injected
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_INJ_StartConversion (ADC_TypeDef *ADCx)
Start ADC group injected conversion.
__STATIC_INLINE void | LL_ADC_INJ_StopConversion (ADC_TypeDef *ADCx)
Stop ADC group injected conversion.
__STATIC_INLINE uint32_t | LL_ADC_INJ_IsConversionOngoing (ADC_TypeDef *ADCx)
Get ADC group injected conversion state.
__STATIC_INLINE uint32_t | LL_ADC_INJ_IsStopConversionOngoing (ADC_TypeDef *ADCx)
Get ADC group injected command of conversion stop state.
__STATIC_INLINE uint32_t | LL_ADC_INJ_ReadConversionData32 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).
__STATIC_INLINE uint16_t | LL_ADC_INJ_ReadConversionData12 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 12 bits.
__STATIC_INLINE uint16_t | LL_ADC_INJ_ReadConversionData10 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 10 bits.
__STATIC_INLINE uint8_t | LL_ADC_INJ_ReadConversionData8 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 8 bits.
__STATIC_INLINE uint8_t | LL_ADC_INJ_ReadConversionData6 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 6 bits.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing ( ADC_TypeDef * ADCx )

Get ADC group injected conversion state.

Reference Manual to LL API cross reference:
CR JADSTART LL_ADC_INJ_IsConversionOngoing
Parameters:
ADCx ADC instance
Return values:
0,: no conversion is on going on ADC group injected.

Definition at line 5282 of file stm32wbxx_ll_adc.h.

Referenced by ADC_ConversionStop(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_DisableInjectedQueue(), HAL_ADCEx_EnableInjectedQueue(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), HAL_ADCEx_RegularStop_IT(), and LL_ADC_DeInit().

__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing ( ADC_TypeDef * ADCx )

Get ADC group injected command of conversion stop state.

Reference Manual to LL API cross reference:
CR JADSTP LL_ADC_INJ_IsStopConversionOngoing
Parameters:
ADCx ADC instance
Return values:
0,: no command of conversion stop is on going on ADC group injected.

Definition at line 5293 of file stm32wbxx_ll_adc.h.

Referenced by LL_ADC_DeInit().

__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10 | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group injected conversion data, range fit for ADC resolution 10 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_INJ_ReadConversionData32.
Reference Manual to LL API cross reference:
JDR1 JDATA LL_ADC_INJ_ReadConversionData10
JDR2 JDATA LL_ADC_INJ_ReadConversionData10
JDR3 JDATA LL_ADC_INJ_ReadConversionData10
JDR4 JDATA LL_ADC_INJ_ReadConversionData10
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
Return values:
Value between Min_Data=0x000 and Max_Data=0x3FF

Definition at line 5369 of file stm32wbxx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, ADC_INJ_JDRX_REGOFFSET_MASK, and ADC_JDRX_REGOFFSET_POS.

__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12 | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group injected conversion data, range fit for ADC resolution 12 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_INJ_ReadConversionData32.
Reference Manual to LL API cross reference:
JDR1 JDATA LL_ADC_INJ_ReadConversionData12
JDR2 JDATA LL_ADC_INJ_ReadConversionData12
JDR3 JDATA LL_ADC_INJ_ReadConversionData12
JDR4 JDATA LL_ADC_INJ_ReadConversionData12
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 5342 of file stm32wbxx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, ADC_INJ_JDRX_REGOFFSET_MASK, and ADC_JDRX_REGOFFSET_POS.

__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32 | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group injected conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).

Reference Manual to LL API cross reference:
JDR1 JDATA LL_ADC_INJ_ReadConversionData32
JDR2 JDATA LL_ADC_INJ_ReadConversionData32
JDR3 JDATA LL_ADC_INJ_ReadConversionData32
JDR4 JDATA LL_ADC_INJ_ReadConversionData32
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
Return values:
Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

Definition at line 5315 of file stm32wbxx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, ADC_INJ_JDRX_REGOFFSET_MASK, and ADC_JDRX_REGOFFSET_POS.

__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6 | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group injected conversion data, range fit for ADC resolution 6 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_INJ_ReadConversionData32.
Reference Manual to LL API cross reference:
JDR1 JDATA LL_ADC_INJ_ReadConversionData6
JDR2 JDATA LL_ADC_INJ_ReadConversionData6
JDR3 JDATA LL_ADC_INJ_ReadConversionData6
JDR4 JDATA LL_ADC_INJ_ReadConversionData6
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
Return values:
Value between Min_Data=0x00 and Max_Data=0x3F

Definition at line 5423 of file stm32wbxx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, ADC_INJ_JDRX_REGOFFSET_MASK, and ADC_JDRX_REGOFFSET_POS.

__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8 | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group injected conversion data, range fit for ADC resolution 8 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_INJ_ReadConversionData32.
Reference Manual to LL API cross reference:
JDR1 JDATA LL_ADC_INJ_ReadConversionData8
JDR2 JDATA LL_ADC_INJ_ReadConversionData8
JDR3 JDATA LL_ADC_INJ_ReadConversionData8
JDR4 JDATA LL_ADC_INJ_ReadConversionData8
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 5396 of file stm32wbxx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, ADC_INJ_JDRX_REGOFFSET_MASK, and ADC_JDRX_REGOFFSET_POS.

__STATIC_INLINE void LL_ADC_INJ_StartConversion ( ADC_TypeDef * ADCx )

Start ADC group injected conversion.

Note:
On this STM32 serie, this function is relevant for both internal trigger (SW start) and external trigger:
  • If ADC trigger has been set to software start, ADC conversion starts immediately.
  • If ADC trigger has been set to external trigger, ADC conversion will start at next trigger event (on the selected trigger edge) following the ADC start conversion command.
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be enabled without conversion on going on group injected, without conversion stop command on going on group injected, without ADC disable command on going.
Reference Manual to LL API cross reference:
CR JADSTART LL_ADC_INJ_StartConversion
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5246 of file stm32wbxx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

Referenced by HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

__STATIC_INLINE void LL_ADC_INJ_StopConversion ( ADC_TypeDef * ADCx )

Stop ADC group injected conversion.

Note:
On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be enabled with conversion on going on group injected, without ADC disable command on going.
Reference Manual to LL API cross reference:
CR JADSTP LL_ADC_INJ_StopConversion
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5266 of file stm32wbxx_ll_adc.h.

References ADC_CR_BITS_PROPERTY_RS.

Referenced by ADC_ConversionStop(), and LL_ADC_DeInit().

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC flag management

Functions
ADC flag management
ADC Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_ADRDY (ADC_TypeDef *ADCx)
Get flag ADC ready.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_EOC (ADC_TypeDef *ADCx)
Get flag ADC group regular end of unitary conversion.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_EOS (ADC_TypeDef *ADCx)
Get flag ADC group regular end of sequence conversions.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_OVR (ADC_TypeDef *ADCx)
Get flag ADC group regular overrun.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_EOSMP (ADC_TypeDef *ADCx)
Get flag ADC group regular end of sampling phase.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_JEOC (ADC_TypeDef *ADCx)
Get flag ADC group injected end of unitary conversion.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_JEOS (ADC_TypeDef *ADCx)
Get flag ADC group injected end of sequence conversions.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_JQOVF (ADC_TypeDef *ADCx)
Get flag ADC group injected contexts queue overflow.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_AWD1 (ADC_TypeDef *ADCx)
Get flag ADC analog watchdog 1 flag.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_AWD2 (ADC_TypeDef *ADCx)
Get flag ADC analog watchdog 2.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_AWD3 (ADC_TypeDef *ADCx)
Get flag ADC analog watchdog 3.
__STATIC_INLINE void | LL_ADC_ClearFlag_ADRDY (ADC_TypeDef *ADCx)
Clear flag ADC ready.
__STATIC_INLINE void | LL_ADC_ClearFlag_EOC (ADC_TypeDef *ADCx)
Clear flag ADC group regular end of unitary conversion.
__STATIC_INLINE void | LL_ADC_ClearFlag_EOS (ADC_TypeDef *ADCx)
Clear flag ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_ClearFlag_OVR (ADC_TypeDef *ADCx)
Clear flag ADC group regular overrun.
__STATIC_INLINE void | LL_ADC_ClearFlag_EOSMP (ADC_TypeDef *ADCx)
Clear flag ADC group regular end of sampling phase.
__STATIC_INLINE void | LL_ADC_ClearFlag_JEOC (ADC_TypeDef *ADCx)
Clear flag ADC group injected end of unitary conversion.
__STATIC_INLINE void | LL_ADC_ClearFlag_JEOS (ADC_TypeDef *ADCx)
Clear flag ADC group injected end of sequence conversions.
__STATIC_INLINE void | LL_ADC_ClearFlag_JQOVF (ADC_TypeDef *ADCx)
Clear flag ADC group injected contexts queue overflow.
__STATIC_INLINE void | LL_ADC_ClearFlag_AWD1 (ADC_TypeDef *ADCx)
Clear flag ADC analog watchdog 1.
__STATIC_INLINE void | LL_ADC_ClearFlag_AWD2 (ADC_TypeDef *ADCx)
Clear flag ADC analog watchdog 2.
__STATIC_INLINE void | LL_ADC_ClearFlag_AWD3 (ADC_TypeDef *ADCx)
Clear flag ADC analog watchdog 3.

Function Documentation

__STATIC_INLINE void LL_ADC_ClearFlag_ADRDY ( ADC_TypeDef * ADCx )

Clear flag ADC ready.

Note:
On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC is enabled and when conversion clock is active. (not only core clock: this ADC has a dual clock domain)
Reference Manual to LL API cross reference:
ISR ADRDY LL_ADC_ClearFlag_ADRDY
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5573 of file stm32wbxx_ll_adc.h.

References LL_ADC_FLAG_ADRDY.

__STATIC_INLINE void LL_ADC_ClearFlag_AWD1 ( ADC_TypeDef * ADCx )

Clear flag ADC analog watchdog 1.

Reference Manual to LL API cross reference:
ISR AWD1 LL_ADC_ClearFlag_AWD1
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5661 of file stm32wbxx_ll_adc.h.

References LL_ADC_FLAG_AWD1.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_ClearFlag_AWD2 ( ADC_TypeDef * ADCx )

Clear flag ADC analog watchdog 2.

Reference Manual to LL API cross reference:
ISR AWD2 LL_ADC_ClearFlag_AWD2
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5672 of file stm32wbxx_ll_adc.h.

References LL_ADC_FLAG_AWD2.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_ClearFlag_AWD3 ( ADC_TypeDef * ADCx )

Clear flag ADC analog watchdog 3.

Reference Manual to LL API cross reference:
ISR AWD3 LL_ADC_ClearFlag_AWD3
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5683 of file stm32wbxx_ll_adc.h.

References LL_ADC_FLAG_AWD3.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_ClearFlag_EOC ( ADC_TypeDef * ADCx )

Clear flag ADC group regular end of unitary conversion.

Reference Manual to LL API cross reference:
ISR EOC LL_ADC_ClearFlag_EOC
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5584 of file stm32wbxx_ll_adc.h.

References LL_ADC_FLAG_EOC.

__STATIC_INLINE void LL_ADC_ClearFlag_EOS ( ADC_TypeDef * ADCx )

Clear flag ADC group regular end of sequence conversions.

Reference Manual to LL API cross reference:
ISR EOS LL_ADC_ClearFlag_EOS
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5595 of file stm32wbxx_ll_adc.h.

References LL_ADC_FLAG_EOS.

__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP ( ADC_TypeDef * ADCx )

Clear flag ADC group regular end of sampling phase.

Reference Manual to LL API cross reference:
ISR EOSMP LL_ADC_ClearFlag_EOSMP
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5617 of file stm32wbxx_ll_adc.h.

References LL_ADC_FLAG_EOSMP.

__STATIC_INLINE void LL_ADC_ClearFlag_JEOC ( ADC_TypeDef * ADCx )

Clear flag ADC group injected end of unitary conversion.

Reference Manual to LL API cross reference:
ISR JEOC LL_ADC_ClearFlag_JEOC
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5628 of file stm32wbxx_ll_adc.h.

References LL_ADC_FLAG_JEOC.

__STATIC_INLINE void LL_ADC_ClearFlag_JEOS ( ADC_TypeDef * ADCx )

Clear flag ADC group injected end of sequence conversions.

Reference Manual to LL API cross reference:
ISR JEOS LL_ADC_ClearFlag_JEOS
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5639 of file stm32wbxx_ll_adc.h.

References LL_ADC_FLAG_JEOS.

__STATIC_INLINE void LL_ADC_ClearFlag_JQOVF ( ADC_TypeDef * ADCx )

Clear flag ADC group injected contexts queue overflow.

Reference Manual to LL API cross reference:
ISR JQOVF LL_ADC_ClearFlag_JQOVF
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5650 of file stm32wbxx_ll_adc.h.

References LL_ADC_FLAG_JQOVF.

__STATIC_INLINE void LL_ADC_ClearFlag_OVR ( ADC_TypeDef * ADCx )

Clear flag ADC group regular overrun.

Reference Manual to LL API cross reference:
ISR OVR LL_ADC_ClearFlag_OVR
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5606 of file stm32wbxx_ll_adc.h.

References LL_ADC_FLAG_OVR.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY ( ADC_TypeDef * ADCx )

Get flag ADC ready.

Note:
On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC is enabled and when conversion clock is active. (not only core clock: this ADC has a dual clock domain)
Reference Manual to LL API cross reference:
ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 5449 of file stm32wbxx_ll_adc.h.

References LL_ADC_FLAG_ADRDY.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1 ( ADC_TypeDef * ADCx )

Get flag ADC analog watchdog 1 flag.

Reference Manual to LL API cross reference:
ISR AWD1 LL_ADC_IsActiveFlag_AWD1
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 5537 of file stm32wbxx_ll_adc.h.

References LL_ADC_FLAG_AWD1.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2 ( ADC_TypeDef * ADCx )

Get flag ADC analog watchdog 2.

Reference Manual to LL API cross reference:
ISR AWD2 LL_ADC_IsActiveFlag_AWD2
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 5548 of file stm32wbxx_ll_adc.h.

References LL_ADC_FLAG_AWD2.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3 ( ADC_TypeDef * ADCx )

Get flag ADC analog watchdog 3.

Reference Manual to LL API cross reference:
ISR AWD3 LL_ADC_IsActiveFlag_AWD3
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 5559 of file stm32wbxx_ll_adc.h.

References LL_ADC_FLAG_AWD3.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC ( ADC_TypeDef * ADCx )

Get flag ADC group regular end of unitary conversion.

Reference Manual to LL API cross reference:
ISR EOC LL_ADC_IsActiveFlag_EOC
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 5460 of file stm32wbxx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS ( ADC_TypeDef * ADCx )

Get flag ADC group regular end of sequence conversions.

Reference Manual to LL API cross reference:
ISR EOS LL_ADC_IsActiveFlag_EOS
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 5471 of file stm32wbxx_ll_adc.h.

References LL_ADC_FLAG_EOS.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP ( ADC_TypeDef * ADCx )

Get flag ADC group regular end of sampling phase.

Reference Manual to LL API cross reference:
ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 5493 of file stm32wbxx_ll_adc.h.

References LL_ADC_FLAG_EOSMP.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC ( ADC_TypeDef * ADCx )

Get flag ADC group injected end of unitary conversion.

Reference Manual to LL API cross reference:
ISR JEOC LL_ADC_IsActiveFlag_JEOC
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 5504 of file stm32wbxx_ll_adc.h.

References LL_ADC_FLAG_JEOC.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS ( ADC_TypeDef * ADCx )

Get flag ADC group injected end of sequence conversions.

Reference Manual to LL API cross reference:
ISR JEOS LL_ADC_IsActiveFlag_JEOS
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 5515 of file stm32wbxx_ll_adc.h.

References LL_ADC_FLAG_JEOS.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF ( ADC_TypeDef * ADCx )

Get flag ADC group injected contexts queue overflow.

Reference Manual to LL API cross reference:
ISR JQOVF LL_ADC_IsActiveFlag_JQOVF
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 5526 of file stm32wbxx_ll_adc.h.

References LL_ADC_FLAG_JQOVF.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR ( ADC_TypeDef * ADCx )

Get flag ADC group regular overrun.

Reference Manual to LL API cross reference:
ISR OVR LL_ADC_IsActiveFlag_OVR
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 5482 of file stm32wbxx_ll_adc.h.

References LL_ADC_FLAG_OVR.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC IT management

Functions
ADC IT management
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_EnableIT_ADRDY (ADC_TypeDef *ADCx)
Enable ADC ready.
__STATIC_INLINE void | LL_ADC_EnableIT_EOC (ADC_TypeDef *ADCx)
Enable interruption ADC group regular end of unitary conversion.
__STATIC_INLINE void | LL_ADC_EnableIT_EOS (ADC_TypeDef *ADCx)
Enable interruption ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_EnableIT_OVR (ADC_TypeDef *ADCx)
Enable ADC group regular interruption overrun.
__STATIC_INLINE void | LL_ADC_EnableIT_EOSMP (ADC_TypeDef *ADCx)
Enable interruption ADC group regular end of sampling.
__STATIC_INLINE void | LL_ADC_EnableIT_JEOC (ADC_TypeDef *ADCx)
Enable interruption ADC group injected end of unitary conversion.
__STATIC_INLINE void | LL_ADC_EnableIT_JEOS (ADC_TypeDef *ADCx)
Enable interruption ADC group injected end of sequence conversions.
__STATIC_INLINE void | LL_ADC_EnableIT_JQOVF (ADC_TypeDef *ADCx)
Enable interruption ADC group injected context queue overflow.
__STATIC_INLINE void | LL_ADC_EnableIT_AWD1 (ADC_TypeDef *ADCx)
Enable interruption ADC analog watchdog 1.
__STATIC_INLINE void | LL_ADC_EnableIT_AWD2 (ADC_TypeDef *ADCx)
Enable interruption ADC analog watchdog 2.
__STATIC_INLINE void | LL_ADC_EnableIT_AWD3 (ADC_TypeDef *ADCx)
Enable interruption ADC analog watchdog 3.
__STATIC_INLINE void | LL_ADC_DisableIT_ADRDY (ADC_TypeDef *ADCx)
Disable interruption ADC ready.
__STATIC_INLINE void | LL_ADC_DisableIT_EOC (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of unitary conversion.
__STATIC_INLINE void | LL_ADC_DisableIT_EOS (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_DisableIT_OVR (ADC_TypeDef *ADCx)
Disable interruption ADC group regular overrun.
__STATIC_INLINE void | LL_ADC_DisableIT_EOSMP (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of sampling.
__STATIC_INLINE void | LL_ADC_DisableIT_JEOC (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of unitary conversion.
__STATIC_INLINE void | LL_ADC_DisableIT_JEOS (ADC_TypeDef *ADCx)
Disable interruption ADC group injected end of sequence conversions.
__STATIC_INLINE void | LL_ADC_DisableIT_JQOVF (ADC_TypeDef *ADCx)
Disable interruption ADC group injected context queue overflow.
__STATIC_INLINE void | LL_ADC_DisableIT_AWD1 (ADC_TypeDef *ADCx)
Disable interruption ADC analog watchdog 1.
__STATIC_INLINE void | LL_ADC_DisableIT_AWD2 (ADC_TypeDef *ADCx)
Disable interruption ADC analog watchdog 2.
__STATIC_INLINE void | LL_ADC_DisableIT_AWD3 (ADC_TypeDef *ADCx)
Disable interruption ADC analog watchdog 3.
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_ADRDY (ADC_TypeDef *ADCx)
Get state of interruption ADC ready (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_EOC (ADC_TypeDef *ADCx)
Get state of interruption ADC group regular end of unitary conversion (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_EOS (ADC_TypeDef *ADCx)
Get state of interruption ADC group regular end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_OVR (ADC_TypeDef *ADCx)
Get state of interruption ADC group regular overrun (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_EOSMP (ADC_TypeDef *ADCx)
Get state of interruption ADC group regular end of sampling (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_JEOC (ADC_TypeDef *ADCx)
Get state of interruption ADC group injected end of unitary conversion (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_JEOS (ADC_TypeDef *ADCx)
Get state of interruption ADC group injected end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_JQOVF (ADC_TypeDef *ADCx)
Get state of interruption ADC group injected context queue overflow interrupt state (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_AWD1 (ADC_TypeDef *ADCx)
Get state of interruption ADC analog watchdog 1 (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_AWD2 (ADC_TypeDef *ADCx)
Get state of interruption Get ADC analog watchdog 2 (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_AWD3 (ADC_TypeDef *ADCx)
Get state of interruption Get ADC analog watchdog 3 (0: interrupt disabled, 1: interrupt enabled).

Function Documentation

__STATIC_INLINE void LL_ADC_DisableIT_ADRDY ( ADC_TypeDef * ADCx )

Disable interruption ADC ready.

Reference Manual to LL API cross reference:
IER ADRDYIE LL_ADC_DisableIT_ADRDY
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5823 of file stm32wbxx_ll_adc.h.

References LL_ADC_IT_ADRDY.

__STATIC_INLINE void LL_ADC_DisableIT_AWD1 ( ADC_TypeDef * ADCx )

Disable interruption ADC analog watchdog 1.

Reference Manual to LL API cross reference:
IER AWD1IE LL_ADC_DisableIT_AWD1
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5911 of file stm32wbxx_ll_adc.h.

References LL_ADC_IT_AWD1.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_DisableIT_AWD2 ( ADC_TypeDef * ADCx )

Disable interruption ADC analog watchdog 2.

Reference Manual to LL API cross reference:
IER AWD2IE LL_ADC_DisableIT_AWD2
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5922 of file stm32wbxx_ll_adc.h.

References LL_ADC_IT_AWD2.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_DisableIT_AWD3 ( ADC_TypeDef * ADCx )

Disable interruption ADC analog watchdog 3.

Reference Manual to LL API cross reference:
IER AWD3IE LL_ADC_DisableIT_AWD3
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5933 of file stm32wbxx_ll_adc.h.

References LL_ADC_IT_AWD3.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_DisableIT_EOC ( ADC_TypeDef * ADCx )

Disable interruption ADC group regular end of unitary conversion.

Reference Manual to LL API cross reference:
IER EOCIE LL_ADC_DisableIT_EOC
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5834 of file stm32wbxx_ll_adc.h.

References LL_ADC_IT_EOC.

__STATIC_INLINE void LL_ADC_DisableIT_EOS ( ADC_TypeDef * ADCx )

Disable interruption ADC group regular end of sequence conversions.

Reference Manual to LL API cross reference:
IER EOSIE LL_ADC_DisableIT_EOS
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5845 of file stm32wbxx_ll_adc.h.

References LL_ADC_IT_EOS.

__STATIC_INLINE void LL_ADC_DisableIT_EOSMP ( ADC_TypeDef * ADCx )

Disable interruption ADC group regular end of sampling.

Reference Manual to LL API cross reference:
IER EOSMPIE LL_ADC_DisableIT_EOSMP
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5867 of file stm32wbxx_ll_adc.h.

References LL_ADC_IT_EOSMP.

__STATIC_INLINE void LL_ADC_DisableIT_JEOC ( ADC_TypeDef * ADCx )

Disable interruption ADC group regular end of unitary conversion.

Reference Manual to LL API cross reference:
IER JEOCIE LL_ADC_DisableIT_JEOC
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5878 of file stm32wbxx_ll_adc.h.

References LL_ADC_IT_JEOC.

__STATIC_INLINE void LL_ADC_DisableIT_JEOS ( ADC_TypeDef * ADCx )

Disable interruption ADC group injected end of sequence conversions.

Reference Manual to LL API cross reference:
IER JEOSIE LL_ADC_DisableIT_JEOS
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5889 of file stm32wbxx_ll_adc.h.

References LL_ADC_IT_JEOS.

__STATIC_INLINE void LL_ADC_DisableIT_JQOVF ( ADC_TypeDef * ADCx )

Disable interruption ADC group injected context queue overflow.

Reference Manual to LL API cross reference:
IER JQOVFIE LL_ADC_DisableIT_JQOVF
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5900 of file stm32wbxx_ll_adc.h.

References LL_ADC_IT_JQOVF.

__STATIC_INLINE void LL_ADC_DisableIT_OVR ( ADC_TypeDef * ADCx )

Disable interruption ADC group regular overrun.

Reference Manual to LL API cross reference:
IER OVRIE LL_ADC_DisableIT_OVR
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5856 of file stm32wbxx_ll_adc.h.

References LL_ADC_IT_OVR.

__STATIC_INLINE void LL_ADC_EnableIT_ADRDY ( ADC_TypeDef * ADCx )

Enable ADC ready.

Reference Manual to LL API cross reference:
IER ADRDYIE LL_ADC_EnableIT_ADRDY
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5702 of file stm32wbxx_ll_adc.h.

References LL_ADC_IT_ADRDY.

__STATIC_INLINE void LL_ADC_EnableIT_AWD1 ( ADC_TypeDef * ADCx )

Enable interruption ADC analog watchdog 1.

Reference Manual to LL API cross reference:
IER AWD1IE LL_ADC_EnableIT_AWD1
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5790 of file stm32wbxx_ll_adc.h.

References LL_ADC_IT_AWD1.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_EnableIT_AWD2 ( ADC_TypeDef * ADCx )

Enable interruption ADC analog watchdog 2.

Reference Manual to LL API cross reference:
IER AWD2IE LL_ADC_EnableIT_AWD2
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5801 of file stm32wbxx_ll_adc.h.

References LL_ADC_IT_AWD2.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_EnableIT_AWD3 ( ADC_TypeDef * ADCx )

Enable interruption ADC analog watchdog 3.

Reference Manual to LL API cross reference:
IER AWD3IE LL_ADC_EnableIT_AWD3
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5812 of file stm32wbxx_ll_adc.h.

References LL_ADC_IT_AWD3.

Referenced by HAL_ADC_AnalogWDGConfig().

__STATIC_INLINE void LL_ADC_EnableIT_EOC ( ADC_TypeDef * ADCx )

Enable interruption ADC group regular end of unitary conversion.

Reference Manual to LL API cross reference:
IER EOCIE LL_ADC_EnableIT_EOC
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5713 of file stm32wbxx_ll_adc.h.

References LL_ADC_IT_EOC.

__STATIC_INLINE void LL_ADC_EnableIT_EOS ( ADC_TypeDef * ADCx )

Enable interruption ADC group regular end of sequence conversions.

Reference Manual to LL API cross reference:
IER EOSIE LL_ADC_EnableIT_EOS
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5724 of file stm32wbxx_ll_adc.h.

References LL_ADC_IT_EOS.

__STATIC_INLINE void LL_ADC_EnableIT_EOSMP ( ADC_TypeDef * ADCx )

Enable interruption ADC group regular end of sampling.

Reference Manual to LL API cross reference:
IER EOSMPIE LL_ADC_EnableIT_EOSMP
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5746 of file stm32wbxx_ll_adc.h.

References LL_ADC_IT_EOSMP.

__STATIC_INLINE void LL_ADC_EnableIT_JEOC ( ADC_TypeDef * ADCx )

Enable interruption ADC group injected end of unitary conversion.

Reference Manual to LL API cross reference:
IER JEOCIE LL_ADC_EnableIT_JEOC
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5757 of file stm32wbxx_ll_adc.h.

References LL_ADC_IT_JEOC.

__STATIC_INLINE void LL_ADC_EnableIT_JEOS ( ADC_TypeDef * ADCx )

Enable interruption ADC group injected end of sequence conversions.

Reference Manual to LL API cross reference:
IER JEOSIE LL_ADC_EnableIT_JEOS
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5768 of file stm32wbxx_ll_adc.h.

References LL_ADC_IT_JEOS.

__STATIC_INLINE void LL_ADC_EnableIT_JQOVF ( ADC_TypeDef * ADCx )

Enable interruption ADC group injected context queue overflow.

Reference Manual to LL API cross reference:
IER JQOVFIE LL_ADC_EnableIT_JQOVF
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5779 of file stm32wbxx_ll_adc.h.

References LL_ADC_IT_JQOVF.

__STATIC_INLINE void LL_ADC_EnableIT_OVR ( ADC_TypeDef * ADCx )

Enable ADC group regular interruption overrun.

Reference Manual to LL API cross reference:
IER OVRIE LL_ADC_EnableIT_OVR
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 5735 of file stm32wbxx_ll_adc.h.

References LL_ADC_IT_OVR.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY ( ADC_TypeDef * ADCx )

Get state of interruption ADC ready (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 5945 of file stm32wbxx_ll_adc.h.

References LL_ADC_IT_ADRDY.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1 ( ADC_TypeDef * ADCx )

Get state of interruption ADC analog watchdog 1 (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER AWD1IE LL_ADC_IsEnabledIT_AWD1
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 6041 of file stm32wbxx_ll_adc.h.

References LL_ADC_IT_AWD1.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2 ( ADC_TypeDef * ADCx )

Get state of interruption Get ADC analog watchdog 2 (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER AWD2IE LL_ADC_IsEnabledIT_AWD2
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 6053 of file stm32wbxx_ll_adc.h.

References LL_ADC_IT_AWD2.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3 ( ADC_TypeDef * ADCx )

Get state of interruption Get ADC analog watchdog 3 (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER AWD3IE LL_ADC_IsEnabledIT_AWD3
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 6065 of file stm32wbxx_ll_adc.h.

References LL_ADC_IT_AWD3.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC ( ADC_TypeDef * ADCx )

Get state of interruption ADC group regular end of unitary conversion (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER EOCIE LL_ADC_IsEnabledIT_EOC
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 5957 of file stm32wbxx_ll_adc.h.

References LL_ADC_IT_EOC.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS ( ADC_TypeDef * ADCx )

Get state of interruption ADC group regular end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER EOSIE LL_ADC_IsEnabledIT_EOS
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 5969 of file stm32wbxx_ll_adc.h.

References LL_ADC_IT_EOS.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP ( ADC_TypeDef * ADCx )

Get state of interruption ADC group regular end of sampling (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 5993 of file stm32wbxx_ll_adc.h.

References LL_ADC_IT_EOSMP.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC ( ADC_TypeDef * ADCx )

Get state of interruption ADC group injected end of unitary conversion (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER JEOCIE LL_ADC_IsEnabledIT_JEOC
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 6005 of file stm32wbxx_ll_adc.h.

References LL_ADC_IT_JEOC.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS ( ADC_TypeDef * ADCx )

Get state of interruption ADC group injected end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER JEOSIE LL_ADC_IsEnabledIT_JEOS
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 6017 of file stm32wbxx_ll_adc.h.

References LL_ADC_IT_JEOS.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF ( ADC_TypeDef * ADCx )

Get state of interruption ADC group injected context queue overflow interrupt state (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER JQOVFIE LL_ADC_IsEnabledIT_JQOVF
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 6029 of file stm32wbxx_ll_adc.h.

References LL_ADC_IT_JQOVF.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR ( ADC_TypeDef * ADCx )

Get state of interruption ADC group regular overrun (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
IER OVRIE LL_ADC_IsEnabledIT_OVR
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 5981 of file stm32wbxx_ll_adc.h.

References LL_ADC_IT_OVR.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
ADC Exported Functions

Functions

ErrorStatus | LL_ADC_CommonDeInit (ADC_Common_TypeDef *ADCxy_COMMON)
De-initialize registers of all ADC instances belonging to the same ADC common instance to their default reset values.
ErrorStatus | LL_ADC_CommonInit (ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Initialize some features of ADC common parameters (all ADC instances belonging to the same ADC common instance) and multimode (for devices with several ADC instances available).
void | LL_ADC_CommonStructInit (LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Set each LL_ADC_CommonInitTypeDef field to default value.
ErrorStatus | LL_ADC_DeInit (ADC_TypeDef *ADCx)
De-initialize registers of the selected ADC instance to their default reset values.
ErrorStatus | LL_ADC_Init (ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
Initialize some features of ADC instance.
void | LL_ADC_StructInit (LL_ADC_InitTypeDef *ADC_InitStruct)
Set each LL_ADC_InitTypeDef field to default value.
ErrorStatus | LL_ADC_REG_Init (ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
Initialize some features of ADC group regular.
void | LL_ADC_REG_StructInit (LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
Set each LL_ADC_REG_InitTypeDef field to default value.
ErrorStatus | LL_ADC_INJ_Init (ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
Initialize some features of ADC group injected.
void | LL_ADC_INJ_StructInit (LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
Set each LL_ADC_INJ_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_ADC_CommonDeInit ( ADC_Common_TypeDef * ADCxy_COMMON )

De-initialize registers of all ADC instances belonging to the same ADC common instance to their default reset values.

Note:
This function is performing a hard reset, using high level clock source RCC ADC reset.
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC common registers are de-initialized
  • ERROR: not applicable

Definition at line 243 of file stm32wbxx_ll_adc.c.

References assert_param, LL_AHB2_GRP1_ForceReset(), LL_AHB2_GRP1_PERIPH_ADC, and LL_AHB2_GRP1_ReleaseReset().

ErrorStatus LL_ADC_CommonInit | ( | ADC_Common_TypeDef * | ADCxy_COMMON,
 |  | LL_ADC_CommonInitTypeDef * | ADC_CommonInitStruct
 | ) |  |

Initialize some features of ADC common parameters (all ADC instances belonging to the same ADC common instance) and multimode (for devices with several ADC instances available).

Note:
The setting of ADC common parameters is conditioned to ADC instances state: All ADC instances belonging to the same ADC common instance must be disabled.
Parameters:
ADCxy_COMMON | ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
ADC_CommonInitStruct | Pointer to a LL_ADC_CommonInitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC common registers are initialized
  • ERROR: ADC common registers are not initialized

Definition at line 272 of file stm32wbxx_ll_adc.c.

References __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE, assert_param, LL_ADC_CommonInitTypeDef::CommonClock, IS_LL_ADC_COMMON_CLOCK, and LL_ADC_SetCommonClock().

void LL_ADC_CommonStructInit ( LL_ADC_CommonInitTypeDef * ADC_CommonInitStruct )

Set each LL_ADC_CommonInitTypeDef field to default value.

Parameters:
ADC_CommonInitStruct Pointer to a LL_ADC_CommonInitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 340 of file stm32wbxx_ll_adc.c.

References LL_ADC_CommonInitTypeDef::CommonClock, and LL_ADC_CLOCK_SYNC_PCLK_DIV2.

ErrorStatus LL_ADC_DeInit ( ADC_TypeDef * ADCx )

De-initialize registers of the selected ADC instance to their default reset values.

Note:
To reset all ADC instances quickly (perform a hard reset), use function LL_ADC_CommonDeInit().
If this functions returns error status, it means that ADC instance is in an unknown state. In this case, perform a hard reset using high level clock source RCC ADC reset. Refer to function LL_ADC_CommonDeInit().
Parameters:
ADCx ADC instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC registers are de-initialized
  • ERROR: ADC registers are not de-initialized

Definition at line 364 of file stm32wbxx_ll_adc.c.

References ADC_TIMEOUT_DISABLE_CPU_CYCLES, ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES, assert_param, LL_ADC_Disable(), LL_ADC_FLAG_ADRDY, LL_ADC_FLAG_AWD1, LL_ADC_FLAG_AWD2, LL_ADC_FLAG_AWD3, LL_ADC_FLAG_EOC, LL_ADC_FLAG_EOS, LL_ADC_FLAG_EOSMP, LL_ADC_FLAG_JEOC, LL_ADC_FLAG_JEOS, LL_ADC_FLAG_JQOVF, LL_ADC_FLAG_OVR, LL_ADC_INJ_IsConversionOngoing(), LL_ADC_INJ_IsStopConversionOngoing(), LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY, LL_ADC_INJ_SetQueueMode(), LL_ADC_INJ_SetTriggerSource(), LL_ADC_INJ_StopConversion(), LL_ADC_INJ_TRIG_SOFTWARE, LL_ADC_IsDisableOngoing(), LL_ADC_IsEnabled(), LL_ADC_IT_ADRDY, LL_ADC_IT_AWD1, LL_ADC_IT_AWD2, LL_ADC_IT_AWD3, LL_ADC_IT_EOC, LL_ADC_IT_EOS, LL_ADC_IT_EOSMP, LL_ADC_IT_JEOC, LL_ADC_IT_JEOS, LL_ADC_IT_JQOVF, LL_ADC_IT_OVR, LL_ADC_REG_IsConversionOngoing(), LL_ADC_REG_IsStopConversionOngoing(), LL_ADC_REG_SetTriggerSource(), LL_ADC_REG_StopConversion(), and LL_ADC_REG_TRIG_SOFTWARE.

ErrorStatus LL_ADC_Init | ( | ADC_TypeDef * | ADCx,
 |  | LL_ADC_InitTypeDef * | ADC_InitStruct
 | ) |  |

Initialize some features of ADC instance.

Note:
These parameters have an impact on ADC scope: ADC instance. Affects both group regular and group injected (availability of ADC group injected depends on STM32 families). Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: ADC instance .
The setting of these parameters by function LL_ADC_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 families. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.
After using this function, some other features must be configured using LL unitary functions. The minimum configuration remaining to be done is:
  • Set ADC group regular or group injected sequencer: map channel on the selected sequencer rank. Refer to function LL_ADC_REG_SetSequencerRanks().
  • Set ADC channel sampling time Refer to function LL_ADC_SetChannelSamplingTime();
Parameters:
ADCx | ADC instance
ADC_InitStruct | Pointer to a LL_ADC_REG_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC registers are initialized
  • ERROR: ADC registers are not initialized

Definition at line 636 of file stm32wbxx_ll_adc.c.

References assert_param, LL_ADC_InitTypeDef::DataAlignment, IS_LL_ADC_DATA_ALIGN, IS_LL_ADC_LOW_POWER, IS_LL_ADC_RESOLUTION, LL_ADC_IsEnabled(), LL_ADC_InitTypeDef::LowPowerMode, and LL_ADC_InitTypeDef::Resolution.

ErrorStatus LL_ADC_INJ_Init | ( | ADC_TypeDef * | ADCx,
 |  | LL_ADC_INJ_InitTypeDef * | ADC_INJ_InitStruct
 | ) |  |

Initialize some features of ADC group injected.

Note:
These parameters have an impact on ADC scope: ADC group injected. Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: group regular (functions with prefix "INJ").
The setting of these parameters by function LL_ADC_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 families. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.
After using this function, other features must be configured using LL unitary functions. The minimum configuration remaining to be done is:
  • Set ADC group injected sequencer: map channel on the selected sequencer rank. Refer to function LL_ADC_INJ_SetSequencerRanks().
  • Set ADC channel sampling time Refer to function LL_ADC_SetChannelSamplingTime();
Parameters:
ADCx | ADC instance
ADC_INJ_InitStruct | Pointer to a LL_ADC_INJ_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC registers are initialized
  • ERROR: ADC registers are not initialized

Definition at line 856 of file stm32wbxx_ll_adc.c.

References assert_param, IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE, IS_LL_ADC_INJ_SEQ_SCAN_LENGTH, IS_LL_ADC_INJ_TRIG_AUTO, IS_LL_ADC_INJ_TRIG_SOURCE, LL_ADC_INJ_SEQ_SCAN_DISABLE, LL_ADC_IsEnabled(), LL_ADC_REG_SEQ_DISCONT_DISABLE, LL_ADC_REG_SEQ_SCAN_DISABLE, LL_ADC_INJ_InitTypeDef::SequencerDiscont, LL_ADC_INJ_InitTypeDef::SequencerLength, LL_ADC_INJ_InitTypeDef::TrigAuto, and LL_ADC_INJ_InitTypeDef::TriggerSource.

void LL_ADC_INJ_StructInit ( LL_ADC_INJ_InitTypeDef * ADC_INJ_InitStruct )

Set each LL_ADC_INJ_InitTypeDef field to default value.

Parameters:
ADC_INJ_InitStruct Pointer to a LL_ADC_INJ_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 927 of file stm32wbxx_ll_adc.c.

References LL_ADC_INJ_SEQ_DISCONT_DISABLE, LL_ADC_INJ_SEQ_SCAN_DISABLE, LL_ADC_INJ_TRIG_INDEPENDENT, LL_ADC_INJ_TRIG_SOFTWARE, LL_ADC_INJ_InitTypeDef::SequencerDiscont, LL_ADC_INJ_InitTypeDef::SequencerLength, LL_ADC_INJ_InitTypeDef::TrigAuto, and LL_ADC_INJ_InitTypeDef::TriggerSource.

ErrorStatus LL_ADC_REG_Init | ( | ADC_TypeDef * | ADCx,
 |  | LL_ADC_REG_InitTypeDef * | ADC_REG_InitStruct
 | ) |  |

Initialize some features of ADC group regular.

Note:
These parameters have an impact on ADC scope: ADC group regular. Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: group regular (functions with prefix "REG").
The setting of these parameters by function LL_ADC_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 families. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.
After using this function, other features must be configured using LL unitary functions. The minimum configuration remaining to be done is:
  • Set ADC group regular or group injected sequencer: map channel on the selected sequencer rank. Refer to function LL_ADC_REG_SetSequencerRanks().
  • Set ADC channel sampling time Refer to function LL_ADC_SetChannelSamplingTime();
Parameters:
ADCx | ADC instance
ADC_REG_InitStruct | Pointer to a LL_ADC_REG_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC registers are initialized
  • ERROR: ADC registers are not initialized

Definition at line 723 of file stm32wbxx_ll_adc.c.

References assert_param, LL_ADC_REG_InitTypeDef::ContinuousMode, LL_ADC_REG_InitTypeDef::DMATransfer, IS_LL_ADC_REG_CONTINUOUS_MODE, IS_LL_ADC_REG_DMA_TRANSFER, IS_LL_ADC_REG_OVR_DATA_BEHAVIOR, IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE, IS_LL_ADC_REG_SEQ_SCAN_LENGTH, IS_LL_ADC_REG_TRIG_SOURCE, LL_ADC_IsEnabled(), LL_ADC_REG_SEQ_DISCONT_DISABLE, LL_ADC_REG_SEQ_SCAN_DISABLE, LL_ADC_REG_SetSequencerLength(), LL_ADC_REG_InitTypeDef::Overrun, LL_ADC_REG_InitTypeDef::SequencerDiscont, LL_ADC_REG_InitTypeDef::SequencerLength, and LL_ADC_REG_InitTypeDef::TriggerSource.

void LL_ADC_REG_StructInit ( LL_ADC_REG_InitTypeDef * ADC_REG_InitStruct )

Set each LL_ADC_REG_InitTypeDef field to default value.

Parameters:
ADC_REG_InitStruct Pointer to a LL_ADC_REG_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 810 of file stm32wbxx_ll_adc.c.

References LL_ADC_REG_InitTypeDef::ContinuousMode, LL_ADC_REG_InitTypeDef::DMATransfer, LL_ADC_REG_CONV_SINGLE, LL_ADC_REG_DMA_TRANSFER_NONE, LL_ADC_REG_OVR_DATA_OVERWRITTEN, LL_ADC_REG_SEQ_DISCONT_DISABLE, LL_ADC_REG_SEQ_SCAN_DISABLE, LL_ADC_REG_TRIG_SOFTWARE, LL_ADC_REG_InitTypeDef::Overrun, LL_ADC_REG_InitTypeDef::SequencerDiscont, LL_ADC_REG_InitTypeDef::SequencerLength, and LL_ADC_REG_InitTypeDef::TriggerSource.

void LL_ADC_StructInit ( LL_ADC_InitTypeDef * ADC_InitStruct )

Set each LL_ADC_InitTypeDef field to default value.

Parameters:
ADC_InitStruct Pointer to a LL_ADC_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 681 of file stm32wbxx_ll_adc.c.

References LL_ADC_InitTypeDef::DataAlignment, LL_ADC_DATA_ALIGN_RIGHT, LL_ADC_LP_MODE_NONE, LL_ADC_RESOLUTION_12B, LL_ADC_InitTypeDef::LowPowerMode, and LL_ADC_InitTypeDef::Resolution.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: BUS

Modules
BUS
STM32WBxx_LL_Driver

Modules

BUS Exported Constants
BUS Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for BUS registers.

Register | Bit | Function
AHB1ENR | CRCEN | LL_AHB1_GRP1_DisableClock
 |  | LL_AHB1_GRP1_EnableClock
 |  | LL_AHB1_GRP1_IsEnabledClock
 | DMA1EN | LL_AHB1_GRP1_DisableClock
 |  | LL_AHB1_GRP1_EnableClock
 |  | LL_AHB1_GRP1_IsEnabledClock
 | DMA2EN | LL_AHB1_GRP1_DisableClock
 |  | LL_AHB1_GRP1_EnableClock
 |  | LL_AHB1_GRP1_IsEnabledClock
 | DMAMUX1EN | LL_AHB1_GRP1_DisableClock
 |  | LL_AHB1_GRP1_EnableClock
 |  | LL_AHB1_GRP1_IsEnabledClock
 | TSCEN | LL_AHB1_GRP1_DisableClock
 |  | LL_AHB1_GRP1_EnableClock
 |  | LL_AHB1_GRP1_IsEnabledClock
AHB1RSTR | CRCRST | LL_AHB1_GRP1_ForceReset
 |  | LL_AHB1_GRP1_ReleaseReset
 | DMA1RST | LL_AHB1_GRP1_ForceReset
 |  | LL_AHB1_GRP1_ReleaseReset
 | DMA2RST | LL_AHB1_GRP1_ForceReset
 |  | LL_AHB1_GRP1_ReleaseReset
 | DMAMUX1RST | LL_AHB1_GRP1_ForceReset
 |  | LL_AHB1_GRP1_ReleaseReset
 | TSCRST | LL_AHB1_GRP1_ForceReset
 |  | LL_AHB1_GRP1_ReleaseReset
AHB1SMENR | CRCSMEN | LL_AHB1_GRP1_DisableClockSleep
 |  | LL_AHB1_GRP1_EnableClockSleep
 | DMA1SMEN | LL_AHB1_GRP1_DisableClockSleep
 |  | LL_AHB1_GRP1_EnableClockSleep
 | DMA2SMEN | LL_AHB1_GRP1_DisableClockSleep
 |  | LL_AHB1_GRP1_EnableClockSleep
 | DMAMUX1SMEN | LL_AHB1_GRP1_DisableClockSleep
 |  | LL_AHB1_GRP1_EnableClockSleep
 | SRAM1SMEN | LL_AHB1_GRP1_DisableClockSleep
 |  | LL_AHB1_GRP1_EnableClockSleep
 | TSCSMEN | LL_AHB1_GRP1_DisableClockSleep
 |  | LL_AHB1_GRP1_EnableClockSleep
AHB2ENR | ADCEN | LL_AHB2_GRP1_DisableClock
 |  | LL_AHB2_GRP1_EnableClock
 |  | LL_AHB2_GRP1_IsEnabledClock
 | AES1EN | LL_AHB2_GRP1_DisableClock
 |  | LL_AHB2_GRP1_EnableClock
 |  | LL_AHB2_GRP1_IsEnabledClock
 | GPIOAEN | LL_AHB2_GRP1_DisableClock
 |  | LL_AHB2_GRP1_EnableClock
 |  | LL_AHB2_GRP1_IsEnabledClock
 | GPIOBEN | LL_AHB2_GRP1_DisableClock
 |  | LL_AHB2_GRP1_EnableClock
 |  | LL_AHB2_GRP1_IsEnabledClock
 | GPIOCEN | LL_AHB2_GRP1_DisableClock
 |  | LL_AHB2_GRP1_EnableClock
 |  | LL_AHB2_GRP1_IsEnabledClock
 | GPIODEN | LL_AHB2_GRP1_DisableClock
 |  | LL_AHB2_GRP1_EnableClock
 |  | LL_AHB2_GRP1_IsEnabledClock
 | GPIOEEN | LL_AHB2_GRP1_DisableClock
 |  | LL_AHB2_GRP1_EnableClock
 |  | LL_AHB2_GRP1_IsEnabledClock
 | GPIOHEN | LL_AHB2_GRP1_DisableClock
 |  | LL_AHB2_GRP1_EnableClock
 |  | LL_AHB2_GRP1_IsEnabledClock
AHB2RSTR | ADCRST | LL_AHB2_GRP1_ForceReset
 |  | LL_AHB2_GRP1_ReleaseReset
 | AES1RST | LL_AHB2_GRP1_ForceReset
 |  | LL_AHB2_GRP1_ReleaseReset
 | GPIOARST | LL_AHB2_GRP1_ForceReset
 |  | LL_AHB2_GRP1_ReleaseReset
 | GPIOBRST | LL_AHB2_GRP1_ForceReset
 |  | LL_AHB2_GRP1_ReleaseReset
 | GPIOCRST | LL_AHB2_GRP1_ForceReset
 |  | LL_AHB2_GRP1_ReleaseReset
 | GPIODRST | LL_AHB2_GRP1_ForceReset
 |  | LL_AHB2_GRP1_ReleaseReset
 | GPIOERST | LL_AHB2_GRP1_ForceReset
 |  | LL_AHB2_GRP1_ReleaseReset
 | GPIOHRST | LL_AHB2_GRP1_ForceReset
 |  | LL_AHB2_GRP1_ReleaseReset
AHB2SMENR | ADCSMEN | LL_AHB2_GRP1_DisableClockSleep
 |  | LL_AHB2_GRP1_EnableClockSleep
 | AES1SMEN | LL_AHB2_GRP1_DisableClockSleep
 |  | LL_AHB2_GRP1_EnableClockSleep
 | GPIOASMEN | LL_AHB2_GRP1_DisableClockSleep
 |  | LL_AHB2_GRP1_EnableClockSleep
 | GPIOBSMEN | LL_AHB2_GRP1_DisableClockSleep
 |  | LL_AHB2_GRP1_EnableClockSleep
 | GPIOCSMEN | LL_AHB2_GRP1_DisableClockSleep
 |  | LL_AHB2_GRP1_EnableClockSleep
 | GPIODSMEN | LL_AHB2_GRP1_DisableClockSleep
 |  | LL_AHB2_GRP1_EnableClockSleep
 | GPIOESMEN | LL_AHB2_GRP1_DisableClockSleep
 |  | LL_AHB2_GRP1_EnableClockSleep
 | GPIOHSMEN | LL_AHB2_GRP1_DisableClockSleep
 |  | LL_AHB2_GRP1_EnableClockSleep
AHB3ENR | AES2EN | LL_AHB3_GRP1_DisableClock
 |  | LL_AHB3_GRP1_EnableClock
 |  | LL_AHB3_GRP1_IsEnabledClock
 | FLASHEN | LL_AHB3_GRP1_DisableClock
 |  | LL_AHB3_GRP1_EnableClock
 |  | LL_AHB3_GRP1_IsEnabledClock
 | HSEMEN | LL_AHB3_GRP1_DisableClock
 |  | LL_AHB3_GRP1_EnableClock
 |  | LL_AHB3_GRP1_IsEnabledClock
 | IPCCEN | LL_AHB3_GRP1_DisableClock
 |  | LL_AHB3_GRP1_EnableClock
 |  | LL_AHB3_GRP1_IsEnabledClock
 | PKAEN | LL_AHB3_GRP1_DisableClock
 |  | LL_AHB3_GRP1_EnableClock
 |  | LL_AHB3_GRP1_IsEnabledClock
 | QUADSPIEN | LL_AHB3_GRP1_DisableClock
 |  | LL_AHB3_GRP1_EnableClock
 |  | LL_AHB3_GRP1_IsEnabledClock
 | RNGEN | LL_AHB3_GRP1_DisableClock
 |  | LL_AHB3_GRP1_EnableClock
 |  | LL_AHB3_GRP1_IsEnabledClock
AHB3RSTR | AES2RST | LL_AHB3_GRP1_ForceReset
 |  | LL_AHB3_GRP1_ReleaseReset
 | FLASHRST | LL_AHB3_GRP1_ForceReset
 |  | LL_AHB3_GRP1_ReleaseReset
 | HSEMRST | LL_AHB3_GRP1_ForceReset
 |  | LL_AHB3_GRP1_ReleaseReset
 | IPCCRST | LL_AHB3_GRP1_ForceReset
 |  | LL_AHB3_GRP1_ReleaseReset
 | PKARST | LL_AHB3_GRP1_ForceReset
 |  | LL_AHB3_GRP1_ReleaseReset
 | QUADSPIRST | LL_AHB3_GRP1_ForceReset
 |  | LL_AHB3_GRP1_ReleaseReset
 | RNGRST | LL_AHB3_GRP1_ForceReset
 |  | LL_AHB3_GRP1_ReleaseReset
AHB3SMENR | AES2SMEN | LL_AHB3_GRP1_DisableClockSleep
 |  | LL_AHB3_GRP1_EnableClockSleep
 | FLASHSMEN | LL_AHB3_GRP1_DisableClockSleep
 |  | LL_AHB3_GRP1_EnableClockSleep
 | PKASMEN | LL_AHB3_GRP1_DisableClockSleep
 |  | LL_AHB3_GRP1_EnableClockSleep
 | QUADSPISMEN | LL_AHB3_GRP1_DisableClockSleep
 |  | LL_AHB3_GRP1_EnableClockSleep
 | RNGSMEN | LL_AHB3_GRP1_DisableClockSleep
 |  | LL_AHB3_GRP1_EnableClockSleep
 | SRAM2SMEN | LL_AHB3_GRP1_DisableClockSleep
 |  | LL_AHB3_GRP1_EnableClockSleep
APB1ENR1 | CRSEN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | I2C1EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | I2C3EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | LCDEN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | LPTIM1EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | RTCAPBEN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | SPI2EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | TIM2EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | USBEN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | WWDGEN | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
APB1ENR2 | LPTIM2EN | LL_APB1_GRP2_DisableClock
 |  | LL_APB1_GRP2_EnableClock
 |  | LL_APB1_GRP2_IsEnabledClock
 | LPUART1EN | LL_APB1_GRP2_DisableClock
 |  | LL_APB1_GRP2_EnableClock
 |  | LL_APB1_GRP2_IsEnabledClock
APB1RSTR1 | CRSRST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | I2C1RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | I2C3RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | LCDRST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | LPTIM1RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | SPI2RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | TIM2RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | USBRST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
APB1RSTR2 | LPTIM2RST | LL_APB1_GRP2_ForceReset
 |  | LL_APB1_GRP2_ReleaseReset
 | LPUART1RST | LL_APB1_GRP2_ForceReset
 |  | LL_APB1_GRP2_ReleaseReset
APB1SMENR1 | CRSSMEN | LL_APB1_GRP1_DisableClockSleep
 |  | LL_APB1_GRP1_EnableClockSleep
 | I2C1SMEN | LL_APB1_GRP1_DisableClockSleep
 |  | LL_APB1_GRP1_EnableClockSleep
 | I2C3SMEN | LL_APB1_GRP1_DisableClockSleep
 |  | LL_APB1_GRP1_EnableClockSleep
 | LCDSMEN | LL_APB1_GRP1_DisableClockSleep
 |  | LL_APB1_GRP1_EnableClockSleep
 | LPTIM1SMEN | LL_APB1_GRP1_DisableClockSleep
 |  | LL_APB1_GRP1_EnableClockSleep
 | RTCAPBSMEN | LL_APB1_GRP1_DisableClockSleep
 |  | LL_APB1_GRP1_EnableClockSleep
 | SPI2SMEN | LL_APB1_GRP1_DisableClockSleep
 |  | LL_APB1_GRP1_EnableClockSleep
 | TIM2SMEN | LL_APB1_GRP1_DisableClockSleep
 |  | LL_APB1_GRP1_EnableClockSleep
 | USBSMEN | LL_APB1_GRP1_DisableClockSleep
 |  | LL_APB1_GRP1_EnableClockSleep
 | WWDGSMEN | LL_APB1_GRP1_DisableClockSleep
 |  | LL_APB1_GRP1_EnableClockSleep
APB1SMENR2 | LPTIM2SMEN | LL_APB1_GRP2_DisableClockSleep
 |  | LL_APB1_GRP2_EnableClockSleep
 | LPUART1SMEN | LL_APB1_GRP2_DisableClockSleep
 |  | LL_APB1_GRP2_EnableClockSleep
APB2ENR | SAI1EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | SPI1EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | TIM16EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | TIM17EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | TIM1EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | USART1EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
APB2RSTR | SAI1RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | SPI1RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | TIM16RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | TIM17RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | TIM1RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | USART1RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
APB2SMENR | SAI1SMEN | LL_APB2_GRP1_DisableClockSleep
 |  | LL_APB2_GRP1_EnableClockSleep
 | SPI1SMEN | LL_APB2_GRP1_DisableClockSleep
 |  | LL_APB2_GRP1_EnableClockSleep
 | TIM16SMEN | LL_APB2_GRP1_DisableClockSleep
 |  | LL_APB2_GRP1_EnableClockSleep
 | TIM17SMEN | LL_APB2_GRP1_DisableClockSleep
 |  | LL_APB2_GRP1_EnableClockSleep
 | TIM1SMEN | LL_APB2_GRP1_DisableClockSleep
 |  | LL_APB2_GRP1_EnableClockSleep
 | USART1SMEN | LL_APB2_GRP1_DisableClockSleep
 |  | LL_APB2_GRP1_EnableClockSleep
APB3RSTR | RFRST | LL_APB3_GRP1_ForceReset
 |  | LL_APB3_GRP1_ReleaseReset
C2AHB1ENR | CRCEN | LL_C2_AHB1_GRP1_DisableClock
 |  | LL_C2_AHB1_GRP1_EnableClock
 |  | LL_C2_AHB1_GRP1_IsEnabledClock
 | DMA1EN | LL_C2_AHB1_GRP1_DisableClock
 |  | LL_C2_AHB1_GRP1_EnableClock
 |  | LL_C2_AHB1_GRP1_IsEnabledClock
 | DMA2EN | LL_C2_AHB1_GRP1_DisableClock
 |  | LL_C2_AHB1_GRP1_EnableClock
 |  | LL_C2_AHB1_GRP1_IsEnabledClock
 | DMAMUX1EN | LL_C2_AHB1_GRP1_DisableClock
 |  | LL_C2_AHB1_GRP1_EnableClock
 |  | LL_C2_AHB1_GRP1_IsEnabledClock
 | SRAM1EN | LL_C2_AHB1_GRP1_DisableClock
 |  | LL_C2_AHB1_GRP1_EnableClock
 |  | LL_C2_AHB1_GRP1_IsEnabledClock
 | SRAM1SMEN | LL_C2_AHB1_GRP1_DisableClockSleep
 |  | LL_C2_AHB1_GRP1_EnableClockSleep
 | TSCEN | LL_C2_AHB1_GRP1_DisableClock
 |  | LL_C2_AHB1_GRP1_EnableClock
 |  | LL_C2_AHB1_GRP1_IsEnabledClock
C2AHB1SMENR | CRCSMEN | LL_C2_AHB1_GRP1_DisableClockSleep
 |  | LL_C2_AHB1_GRP1_EnableClockSleep
 | DMA1SMEN | LL_C2_AHB1_GRP1_DisableClockSleep
 |  | LL_C2_AHB1_GRP1_EnableClockSleep
 | DMA2SMEN | LL_C2_AHB1_GRP1_DisableClockSleep
 |  | LL_C2_AHB1_GRP1_EnableClockSleep
 | DMAMUX1SMEN | LL_C2_AHB1_GRP1_DisableClockSleep
 |  | LL_C2_AHB1_GRP1_EnableClockSleep
 | TSCSMEN | LL_C2_AHB1_GRP1_DisableClockSleep
 |  | LL_C2_AHB1_GRP1_EnableClockSleep
C2AHB2ENR | ADCEN | LL_C2_AHB2_GRP1_DisableClock
 |  | LL_C2_AHB2_GRP1_EnableClock
 |  | LL_C2_AHB2_GRP1_IsEnabledClock
 | AES1EN | LL_C2_AHB2_GRP1_DisableClock
 |  | LL_C2_AHB2_GRP1_EnableClock
 |  | LL_C2_AHB2_GRP1_IsEnabledClock
 | GPIOAEN | LL_C2_AHB2_GRP1_DisableClock
 |  | LL_C2_AHB2_GRP1_EnableClock
 |  | LL_C2_AHB2_GRP1_IsEnabledClock
 | GPIOBEN | LL_C2_AHB2_GRP1_DisableClock
 |  | LL_C2_AHB2_GRP1_EnableClock
 |  | LL_C2_AHB2_GRP1_IsEnabledClock
 | GPIOCEN | LL_C2_AHB2_GRP1_DisableClock
 |  | LL_C2_AHB2_GRP1_EnableClock
 |  | LL_C2_AHB2_GRP1_IsEnabledClock
 | GPIODEN | LL_C2_AHB2_GRP1_DisableClock
 |  | LL_C2_AHB2_GRP1_EnableClock
 |  | LL_C2_AHB2_GRP1_IsEnabledClock
 | GPIOEEN | LL_C2_AHB2_GRP1_DisableClock
 |  | LL_C2_AHB2_GRP1_EnableClock
 |  | LL_C2_AHB2_GRP1_IsEnabledClock
 | GPIOHEN | LL_C2_AHB2_GRP1_DisableClock
 |  | LL_C2_AHB2_GRP1_EnableClock
 |  | LL_C2_AHB2_GRP1_IsEnabledClock
C2AHB2SMENR | ADCSMEN | LL_C2_AHB2_GRP1_DisableClockSleep
 |  | LL_C2_AHB2_GRP1_EnableClockSleep
 | AES1SMEN | LL_C2_AHB2_GRP1_DisableClockSleep
 |  | LL_C2_AHB2_GRP1_EnableClockSleep
 | GPIOASMEN | LL_C2_AHB2_GRP1_DisableClockSleep
 |  | LL_C2_AHB2_GRP1_EnableClockSleep
 | GPIOBSMEN | LL_C2_AHB2_GRP1_DisableClockSleep
 |  | LL_C2_AHB2_GRP1_EnableClockSleep
 | GPIOCSMEN | LL_C2_AHB2_GRP1_DisableClockSleep
 |  | LL_C2_AHB2_GRP1_EnableClockSleep
 | GPIODSMEN | LL_C2_AHB2_GRP1_DisableClockSleep
 |  | LL_C2_AHB2_GRP1_EnableClockSleep
 | GPIOESMEN | LL_C2_AHB2_GRP1_DisableClockSleep
 |  | LL_C2_AHB2_GRP1_EnableClockSleep
 | GPIOHSMEN | LL_C2_AHB2_GRP1_DisableClockSleep
 |  | LL_C2_AHB2_GRP1_EnableClockSleep
C2AHB3ENR | AES2EN | LL_C2_AHB3_GRP1_DisableClock
 |  | LL_C2_AHB3_GRP1_EnableClock
 |  | LL_C2_AHB3_GRP1_IsEnabledClock
 | FLASHEN | LL_C2_AHB3_GRP1_DisableClock
 |  | LL_C2_AHB3_GRP1_EnableClock
 |  | LL_C2_AHB3_GRP1_IsEnabledClock
 | HSEMEN | LL_C2_AHB3_GRP1_DisableClock
 |  | LL_C2_AHB3_GRP1_EnableClock
 |  | LL_C2_AHB3_GRP1_IsEnabledClock
 | IPCCEN | LL_C2_AHB3_GRP1_DisableClock
 |  | LL_C2_AHB3_GRP1_EnableClock
 |  | LL_C2_AHB3_GRP1_IsEnabledClock
 | PKAEN | LL_C2_AHB3_GRP1_DisableClock
 |  | LL_C2_AHB3_GRP1_EnableClock
 |  | LL_C2_AHB3_GRP1_IsEnabledClock
 | RNGEN | LL_C2_AHB3_GRP1_DisableClock
 |  | LL_C2_AHB3_GRP1_EnableClock
 |  | LL_C2_AHB3_GRP1_IsEnabledClock
C2AHB3SMENR | AES2SMEN | LL_C2_AHB3_GRP1_DisableClockSleep
 |  | LL_C2_AHB3_GRP1_EnableClockSleep
 | FLASHSMEN | LL_C2_AHB3_GRP1_DisableClockSleep
 |  | LL_C2_AHB3_GRP1_EnableClockSleep
 | PKASMEN | LL_C2_AHB3_GRP1_DisableClockSleep
 |  | LL_C2_AHB3_GRP1_EnableClockSleep
 | RNGSMEN | LL_C2_AHB3_GRP1_DisableClockSleep
 |  | LL_C2_AHB3_GRP1_EnableClockSleep
 | SRAM2SMEN | LL_C2_AHB3_GRP1_DisableClockSleep
 |  | LL_C2_AHB3_GRP1_EnableClockSleep
C2APB1ENR1 | CRSEN | LL_C2_APB1_GRP1_DisableClock
 |  | LL_C2_APB1_GRP1_EnableClock
 |  | LL_C2_APB1_GRP1_IsEnabledClock
 | I2C1EN | LL_C2_APB1_GRP1_DisableClock
 |  | LL_C2_APB1_GRP1_EnableClock
 |  | LL_C2_APB1_GRP1_IsEnabledClock
 | I2C3EN | LL_C2_APB1_GRP1_DisableClock
 |  | LL_C2_APB1_GRP1_EnableClock
 |  | LL_C2_APB1_GRP1_IsEnabledClock
 | LCDEN | LL_C2_APB1_GRP1_DisableClock
 |  | LL_C2_APB1_GRP1_EnableClock
 |  | LL_C2_APB1_GRP1_IsEnabledClock
 | LPTIM1EN | LL_C2_APB1_GRP1_DisableClock
 |  | LL_C2_APB1_GRP1_EnableClock
 |  | LL_C2_APB1_GRP1_IsEnabledClock
 | RTCAPBEN | LL_C2_APB1_GRP1_DisableClock
 |  | LL_C2_APB1_GRP1_EnableClock
 |  | LL_C2_APB1_GRP1_IsEnabledClock
 | SPI2EN | LL_C2_APB1_GRP1_DisableClock
 |  | LL_C2_APB1_GRP1_EnableClock
 |  | LL_C2_APB1_GRP1_IsEnabledClock
 | TIM2EN | LL_C2_APB1_GRP1_DisableClock
 |  | LL_C2_APB1_GRP1_EnableClock
 |  | LL_C2_APB1_GRP1_IsEnabledClock
 | USBEN | LL_C2_APB1_GRP1_DisableClock
 |  | LL_C2_APB1_GRP1_EnableClock
 |  | LL_C2_APB1_GRP1_IsEnabledClock
C2APB1ENR2 | LPTIM2EN | LL_C2_APB1_GRP2_DisableClock
 |  | LL_C2_APB1_GRP2_EnableClock
 |  | LL_C2_APB1_GRP2_IsEnabledClock
 | LPUART1EN | LL_C2_APB1_GRP2_DisableClock
 |  | LL_C2_APB1_GRP2_EnableClock
 |  | LL_C2_APB1_GRP2_IsEnabledClock
C2APB1SMENR1 | CRSSMEN | LL_C2_APB1_GRP1_DisableClockSleep
 |  | LL_C2_APB1_GRP1_EnableClockSleep
 | I2C1SMEN | LL_C2_APB1_GRP1_DisableClockSleep
 |  | LL_C2_APB1_GRP1_EnableClockSleep
 | I2C3SMEN | LL_C2_APB1_GRP1_DisableClockSleep
 |  | LL_C2_APB1_GRP1_EnableClockSleep
 | LCDSMEN | LL_C2_APB1_GRP1_DisableClockSleep
 |  | LL_C2_APB1_GRP1_EnableClockSleep
 | LPTIM1SMEN | LL_C2_APB1_GRP1_DisableClockSleep
 |  | LL_C2_APB1_GRP1_EnableClockSleep
 | RTCAPBSMEN | LL_C2_APB1_GRP1_DisableClockSleep
 |  | LL_C2_APB1_GRP1_EnableClockSleep
 | SPI2SMEN | LL_C2_APB1_GRP1_DisableClockSleep
 |  | LL_C2_APB1_GRP1_EnableClockSleep
 | TIM2SMEN | LL_C2_APB1_GRP1_DisableClockSleep
 |  | LL_C2_APB1_GRP1_EnableClockSleep
 | USBSMEN | LL_C2_APB1_GRP1_DisableClockSleep
 |  | LL_C2_APB1_GRP1_EnableClockSleep
C2APB1SMENR2 | LPTIM2SMEN | LL_C2_APB1_GRP2_DisableClockSleep
 |  | LL_C2_APB1_GRP2_EnableClockSleep
 | LPUART1SMEN | LL_C2_APB1_GRP2_DisableClockSleep
 |  | LL_C2_APB1_GRP2_EnableClockSleep
C2APB2ENR | SAI1EN | LL_C2_APB2_GRP1_DisableClock
 |  | LL_C2_APB2_GRP1_EnableClock
 |  | LL_C2_APB2_GRP1_IsEnabledClock
 | SPI1EN | LL_C2_APB2_GRP1_DisableClock
 |  | LL_C2_APB2_GRP1_EnableClock
 |  | LL_C2_APB2_GRP1_IsEnabledClock
 | TIM16EN | LL_C2_APB2_GRP1_DisableClock
 |  | LL_C2_APB2_GRP1_EnableClock
 |  | LL_C2_APB2_GRP1_IsEnabledClock
 | TIM17EN | LL_C2_APB2_GRP1_DisableClock
 |  | LL_C2_APB2_GRP1_EnableClock
 |  | LL_C2_APB2_GRP1_IsEnabledClock
 | TIM1EN | LL_C2_APB2_GRP1_DisableClock
 |  | LL_C2_APB2_GRP1_EnableClock
 |  | LL_C2_APB2_GRP1_IsEnabledClock
 | USART1EN | LL_C2_APB2_GRP1_DisableClock
 |  | LL_C2_APB2_GRP1_EnableClock
 |  | LL_C2_APB2_GRP1_IsEnabledClock
C2APB2SMENR | SAI1SMEN | LL_C2_APB2_GRP1_DisableClockSleep
 |  | LL_C2_APB2_GRP1_EnableClockSleep
 | SPI1SMEN | LL_C2_APB2_GRP1_DisableClockSleep
 |  | LL_C2_APB2_GRP1_EnableClockSleep
 | TIM16SMEN | LL_C2_APB2_GRP1_DisableClockSleep
 |  | LL_C2_APB2_GRP1_EnableClockSleep
 | TIM17SMEN | LL_C2_APB2_GRP1_DisableClockSleep
 |  | LL_C2_APB2_GRP1_EnableClockSleep
 | TIM1SMEN | LL_C2_APB2_GRP1_DisableClockSleep
 |  | LL_C2_APB2_GRP1_EnableClockSleep
 | USART1SMEN | LL_C2_APB2_GRP1_DisableClockSleep
 |  | LL_C2_APB2_GRP1_EnableClockSleep
C2APB3ENR | 802EN | LL_C2_APB3_GRP1_DisableClock
 |  | LL_C2_APB3_GRP1_EnableClock
 |  | LL_C2_APB3_GRP1_IsEnabledClock
 | BLEEN | LL_C2_APB3_GRP1_DisableClock
 |  | LL_C2_APB3_GRP1_EnableClock
 |  | LL_C2_APB3_GRP1_IsEnabledClock
C2APB3SMENR | 802SMEN | LL_C2_APB3_GRP1_DisableClockSleep
 |  | LL_C2_APB3_GRP1_EnableClockSleep
 | BLESMEN | LL_C2_APB3_GRP1_DisableClockSleep
 |  | LL_C2_APB3_GRP1_EnableClockSleep
Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: AHB1 GRP1 PERIPH

Defines
AHB1 GRP1 PERIPH
BUS Exported Constants

Defines

#define | LL_AHB1_GRP1_PERIPH_ALL (0xFFFFFFFFU)
#define | LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
#define | LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
#define | LL_AHB1_GRP1_PERIPH_DMAMUX1 RCC_AHB1ENR_DMAMUX1EN
#define | LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1SMENR_SRAM1SMEN
#define | LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
#define | LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN

Define Documentation

#define LL_AHB1_GRP1_PERIPH_ALL (0xFFFFFFFFU)

Definition at line 75 of file stm32wbxx_ll_bus.h.

#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN

Definition at line 83 of file stm32wbxx_ll_bus.h.

Referenced by LL_CRC_DeInit().

#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN

Definition at line 77 of file stm32wbxx_ll_bus.h.

Referenced by LL_DMA_DeInit().

#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN

Definition at line 79 of file stm32wbxx_ll_bus.h.

Referenced by LL_DMA_DeInit().

#define LL_AHB1_GRP1_PERIPH_DMAMUX1 RCC_AHB1ENR_DMAMUX1EN

Definition at line 81 of file stm32wbxx_ll_bus.h.

#define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1SMENR_SRAM1SMEN

Definition at line 82 of file stm32wbxx_ll_bus.h.

#define LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN

Definition at line 84 of file stm32wbxx_ll_bus.h.

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STM32WB55xx HAL User Manual: AHB2 GRP1 PERIPH

Defines
AHB2 GRP1 PERIPH
BUS Exported Constants

Defines

#define | LL_AHB2_GRP1_PERIPH_ALL (0xFFFFFFFFU)
#define | LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN
#define | LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN
#define | LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN
#define | LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN
#define | LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN
#define | LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR_GPIOHEN
#define | LL_AHB2_GRP1_PERIPH_ADC RCC_AHB2ENR_ADCEN
#define | LL_AHB2_GRP1_PERIPH_AES1 RCC_AHB2ENR_AES1EN

Define Documentation

#define LL_AHB2_GRP1_PERIPH_ADC RCC_AHB2ENR_ADCEN

Definition at line 102 of file stm32wbxx_ll_bus.h.

Referenced by LL_ADC_CommonDeInit().

#define LL_AHB2_GRP1_PERIPH_AES1 RCC_AHB2ENR_AES1EN

Definition at line 104 of file stm32wbxx_ll_bus.h.

#define LL_AHB2_GRP1_PERIPH_ALL (0xFFFFFFFFU)

Definition at line 92 of file stm32wbxx_ll_bus.h.

#define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN

Definition at line 94 of file stm32wbxx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN

Definition at line 95 of file stm32wbxx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN

Definition at line 96 of file stm32wbxx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN

Definition at line 98 of file stm32wbxx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN

Definition at line 100 of file stm32wbxx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR_GPIOHEN

Definition at line 101 of file stm32wbxx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

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STM32WB55xx HAL User Manual: AHB3 GRP1 PERIPH

Defines
AHB3 GRP1 PERIPH
BUS Exported Constants

Defines

#define | LL_AHB3_GRP1_PERIPH_ALL (0xFFFFFFFFU)
#define | LL_AHB3_GRP1_PERIPH_QUADSPI RCC_AHB3ENR_QUADSPIEN
#define | LL_AHB3_GRP1_PERIPH_PKA RCC_AHB3ENR_PKAEN
#define | LL_AHB3_GRP1_PERIPH_AES2 RCC_AHB3ENR_AES2EN
#define | LL_AHB3_GRP1_PERIPH_RNG RCC_AHB3ENR_RNGEN
#define | LL_AHB3_GRP1_PERIPH_HSEM RCC_AHB3ENR_HSEMEN
#define | LL_AHB3_GRP1_PERIPH_IPCC RCC_AHB3ENR_IPCCEN
#define | LL_AHB3_GRP1_PERIPH_SRAM2 RCC_AHB3SMENR_SRAM2SMEN
#define | LL_AHB3_GRP1_PERIPH_FLASH RCC_AHB3ENR_FLASHEN

Define Documentation

#define LL_AHB3_GRP1_PERIPH_AES2 RCC_AHB3ENR_AES2EN

Definition at line 118 of file stm32wbxx_ll_bus.h.

#define LL_AHB3_GRP1_PERIPH_ALL (0xFFFFFFFFU)

Definition at line 113 of file stm32wbxx_ll_bus.h.

#define LL_AHB3_GRP1_PERIPH_FLASH RCC_AHB3ENR_FLASHEN

Definition at line 123 of file stm32wbxx_ll_bus.h.

#define LL_AHB3_GRP1_PERIPH_HSEM RCC_AHB3ENR_HSEMEN

Definition at line 120 of file stm32wbxx_ll_bus.h.

#define LL_AHB3_GRP1_PERIPH_IPCC RCC_AHB3ENR_IPCCEN

Definition at line 121 of file stm32wbxx_ll_bus.h.

#define LL_AHB3_GRP1_PERIPH_PKA RCC_AHB3ENR_PKAEN

Definition at line 117 of file stm32wbxx_ll_bus.h.

Referenced by LL_PKA_DeInit().

#define LL_AHB3_GRP1_PERIPH_QUADSPI RCC_AHB3ENR_QUADSPIEN

Definition at line 115 of file stm32wbxx_ll_bus.h.

#define LL_AHB3_GRP1_PERIPH_RNG RCC_AHB3ENR_RNGEN

Definition at line 119 of file stm32wbxx_ll_bus.h.

Referenced by LL_RNG_DeInit().

#define LL_AHB3_GRP1_PERIPH_SRAM2 RCC_AHB3SMENR_SRAM2SMEN

Definition at line 122 of file stm32wbxx_ll_bus.h.

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STM32WB55xx HAL User Manual: APB1 GRP1 PERIPH

Defines
APB1 GRP1 PERIPH
BUS Exported Constants

Defines

#define | LL_APB1_GRP1_PERIPH_ALL (0xFFFFFFFFU)
#define | LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN
#define | LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR1_LCDEN
#define | LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR1_RTCAPBEN
#define | LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN
#define | LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN
#define | LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN
#define | LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN
#define | LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR1_CRSEN
#define | LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR1_USBEN
#define | LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN

Define Documentation

#define LL_APB1_GRP1_PERIPH_ALL (0xFFFFFFFFU)

Definition at line 131 of file stm32wbxx_ll_bus.h.

#define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR1_CRSEN

Definition at line 146 of file stm32wbxx_ll_bus.h.

Referenced by LL_CRS_DeInit().

#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN

Definition at line 141 of file stm32wbxx_ll_bus.h.

Referenced by LL_I2C_DeInit().

#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN

Definition at line 143 of file stm32wbxx_ll_bus.h.

Referenced by LL_I2C_DeInit().

#define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR1_LCDEN

Definition at line 134 of file stm32wbxx_ll_bus.h.

#define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN

Definition at line 151 of file stm32wbxx_ll_bus.h.

Referenced by LL_LPTIM_DeInit().

#define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR1_RTCAPBEN

Definition at line 136 of file stm32wbxx_ll_bus.h.

#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN

Definition at line 139 of file stm32wbxx_ll_bus.h.

Referenced by LL_SPI_DeInit().

#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN

Definition at line 132 of file stm32wbxx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR1_USBEN

Definition at line 149 of file stm32wbxx_ll_bus.h.

#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN

Definition at line 137 of file stm32wbxx_ll_bus.h.

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STM32WB55xx HAL User Manual: APB1 GRP2 PERIPH

Defines
APB1 GRP2 PERIPH
BUS Exported Constants

Defines

#define | LL_APB1_GRP2_PERIPH_ALL (0xFFFFFFFFU)
#define | LL_APB1_GRP2_PERIPH_LPUART1 RCC_APB1ENR2_LPUART1EN
#define | LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1ENR2_LPTIM2EN

Define Documentation

#define LL_APB1_GRP2_PERIPH_ALL (0xFFFFFFFFU)

Definition at line 160 of file stm32wbxx_ll_bus.h.

#define LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1ENR2_LPTIM2EN

Definition at line 165 of file stm32wbxx_ll_bus.h.

Referenced by LL_LPTIM_DeInit().

#define LL_APB1_GRP2_PERIPH_LPUART1 RCC_APB1ENR2_LPUART1EN

Definition at line 163 of file stm32wbxx_ll_bus.h.

Referenced by LL_LPUART_DeInit().

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: APB2 GRP1 PERIPH

Defines
APB2 GRP1 PERIPH
BUS Exported Constants

Defines

#define | LL_APB2_GRP1_PERIPH_ALL (0xFFFFFFFFU)
#define | LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
#define | LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
#define | LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
#define | LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
#define | LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
#define | LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN

Define Documentation

#define LL_APB2_GRP1_PERIPH_ALL (0xFFFFFFFFU)

Definition at line 173 of file stm32wbxx_ll_bus.h.

#define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN

Definition at line 181 of file stm32wbxx_ll_bus.h.

#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN

Definition at line 176 of file stm32wbxx_ll_bus.h.

Referenced by LL_SPI_DeInit().

#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN

Definition at line 175 of file stm32wbxx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN

Definition at line 178 of file stm32wbxx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN

Definition at line 179 of file stm32wbxx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN

Definition at line 177 of file stm32wbxx_ll_bus.h.

Referenced by LL_USART_DeInit().

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: APB3 GRP1 PERIPH

Defines
APB3 GRP1 PERIPH
BUS Exported Constants

Defines

#define | LL_APB3_GRP1_PERIPH_ALL (0xFFFFFFFFU)
#define | LL_APB3_GRP1_PERIPH_RF RCC_APB3RSTR_RFRST

Define Documentation

#define LL_APB3_GRP1_PERIPH_ALL (0xFFFFFFFFU)

Definition at line 190 of file stm32wbxx_ll_bus.h.

#define LL_APB3_GRP1_PERIPH_RF RCC_APB3RSTR_RFRST

Definition at line 191 of file stm32wbxx_ll_bus.h.

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STM32WB55xx HAL User Manual: C2 AHB1 GRP1 PERIPH

Defines
C2 AHB1 GRP1 PERIPH
BUS Exported Constants

Defines

#define | LL_C2_AHB1_GRP1_PERIPH_DMA1 RCC_C2AHB1ENR_DMA1EN
#define | LL_C2_AHB1_GRP1_PERIPH_DMA2 RCC_C2AHB1ENR_DMA2EN
#define | LL_C2_AHB1_GRP1_PERIPH_DMAMUX1 RCC_C2AHB1ENR_DMAMUX1EN
#define | LL_C2_AHB1_GRP1_PERIPH_SRAM1 RCC_C2AHB1ENR_SRAM1EN
#define | LL_C2_AHB1_GRP1_PERIPH_CRC RCC_C2AHB1ENR_CRCEN
#define | LL_C2_AHB1_GRP1_PERIPH_TSC RCC_C2AHB1ENR_TSCEN

Define Documentation

#define LL_C2_AHB1_GRP1_PERIPH_CRC RCC_C2AHB1ENR_CRCEN

Definition at line 206 of file stm32wbxx_ll_bus.h.

#define LL_C2_AHB1_GRP1_PERIPH_DMA1 RCC_C2AHB1ENR_DMA1EN

Definition at line 200 of file stm32wbxx_ll_bus.h.

#define LL_C2_AHB1_GRP1_PERIPH_DMA2 RCC_C2AHB1ENR_DMA2EN

Definition at line 202 of file stm32wbxx_ll_bus.h.

#define LL_C2_AHB1_GRP1_PERIPH_DMAMUX1 RCC_C2AHB1ENR_DMAMUX1EN

Definition at line 204 of file stm32wbxx_ll_bus.h.

#define LL_C2_AHB1_GRP1_PERIPH_SRAM1 RCC_C2AHB1ENR_SRAM1EN

Definition at line 205 of file stm32wbxx_ll_bus.h.

#define LL_C2_AHB1_GRP1_PERIPH_TSC RCC_C2AHB1ENR_TSCEN

Definition at line 207 of file stm32wbxx_ll_bus.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: C2 AHB2 GRP1 PERIPH

Defines
C2 AHB2 GRP1 PERIPH
BUS Exported Constants

Defines

#define | LL_C2_AHB2_GRP1_PERIPH_GPIOA RCC_C2AHB2ENR_GPIOAEN
#define | LL_C2_AHB2_GRP1_PERIPH_GPIOB RCC_C2AHB2ENR_GPIOBEN
#define | LL_C2_AHB2_GRP1_PERIPH_GPIOC RCC_C2AHB2ENR_GPIOCEN
#define | LL_C2_AHB2_GRP1_PERIPH_GPIOD RCC_C2AHB2ENR_GPIODEN
#define | LL_C2_AHB2_GRP1_PERIPH_GPIOE RCC_C2AHB2ENR_GPIOEEN
#define | LL_C2_AHB2_GRP1_PERIPH_GPIOH RCC_C2AHB2ENR_GPIOHEN
#define | LL_C2_AHB2_GRP1_PERIPH_ADC RCC_C2AHB2ENR_ADCEN
#define | LL_C2_AHB2_GRP1_PERIPH_AES1 RCC_C2AHB2ENR_AES1EN

Define Documentation

#define LL_C2_AHB2_GRP1_PERIPH_ADC RCC_C2AHB2ENR_ADCEN

Definition at line 224 of file stm32wbxx_ll_bus.h.

#define LL_C2_AHB2_GRP1_PERIPH_AES1 RCC_C2AHB2ENR_AES1EN

Definition at line 226 of file stm32wbxx_ll_bus.h.

#define LL_C2_AHB2_GRP1_PERIPH_GPIOA RCC_C2AHB2ENR_GPIOAEN

Definition at line 216 of file stm32wbxx_ll_bus.h.

#define LL_C2_AHB2_GRP1_PERIPH_GPIOB RCC_C2AHB2ENR_GPIOBEN

Definition at line 217 of file stm32wbxx_ll_bus.h.

#define LL_C2_AHB2_GRP1_PERIPH_GPIOC RCC_C2AHB2ENR_GPIOCEN

Definition at line 218 of file stm32wbxx_ll_bus.h.

#define LL_C2_AHB2_GRP1_PERIPH_GPIOD RCC_C2AHB2ENR_GPIODEN

Definition at line 220 of file stm32wbxx_ll_bus.h.

#define LL_C2_AHB2_GRP1_PERIPH_GPIOE RCC_C2AHB2ENR_GPIOEEN

Definition at line 222 of file stm32wbxx_ll_bus.h.

#define LL_C2_AHB2_GRP1_PERIPH_GPIOH RCC_C2AHB2ENR_GPIOHEN

Definition at line 223 of file stm32wbxx_ll_bus.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: C2 AHB3 GRP1 PERIPH

Defines
C2 AHB3 GRP1 PERIPH
BUS Exported Constants

Defines

#define | LL_C2_AHB3_GRP1_PERIPH_PKA RCC_C2AHB3ENR_PKAEN
#define | LL_C2_AHB3_GRP1_PERIPH_AES2 RCC_C2AHB3ENR_AES2EN
#define | LL_C2_AHB3_GRP1_PERIPH_RNG RCC_C2AHB3ENR_RNGEN
#define | LL_C2_AHB3_GRP1_PERIPH_HSEM RCC_C2AHB3ENR_HSEMEN
#define | LL_C2_AHB3_GRP1_PERIPH_IPCC RCC_C2AHB3ENR_IPCCEN
#define | LL_C2_AHB3_GRP1_PERIPH_FLASH RCC_C2AHB3ENR_FLASHEN
#define | LL_C2_AHB3_GRP1_PERIPH_SRAM2 RCC_C2AHB3SMENR_SRAM2SMEN

Define Documentation

#define LL_C2_AHB3_GRP1_PERIPH_AES2 RCC_C2AHB3ENR_AES2EN

Definition at line 237 of file stm32wbxx_ll_bus.h.

#define LL_C2_AHB3_GRP1_PERIPH_FLASH RCC_C2AHB3ENR_FLASHEN

Definition at line 241 of file stm32wbxx_ll_bus.h.

#define LL_C2_AHB3_GRP1_PERIPH_HSEM RCC_C2AHB3ENR_HSEMEN

Definition at line 239 of file stm32wbxx_ll_bus.h.

#define LL_C2_AHB3_GRP1_PERIPH_IPCC RCC_C2AHB3ENR_IPCCEN

Definition at line 240 of file stm32wbxx_ll_bus.h.

#define LL_C2_AHB3_GRP1_PERIPH_PKA RCC_C2AHB3ENR_PKAEN

Definition at line 236 of file stm32wbxx_ll_bus.h.

#define LL_C2_AHB3_GRP1_PERIPH_RNG RCC_C2AHB3ENR_RNGEN

Definition at line 238 of file stm32wbxx_ll_bus.h.

#define LL_C2_AHB3_GRP1_PERIPH_SRAM2 RCC_C2AHB3SMENR_SRAM2SMEN

Definition at line 242 of file stm32wbxx_ll_bus.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: C2 APB1 GRP1 PERIPH

Defines
C2 APB1 GRP1 PERIPH
BUS Exported Constants

Defines

#define | LL_C2_APB1_GRP1_PERIPH_TIM2 RCC_C2APB1ENR1_TIM2EN
#define | LL_C2_APB1_GRP1_PERIPH_LCD RCC_C2APB1ENR1_LCDEN
#define | LL_C2_APB1_GRP1_PERIPH_RTCAPB RCC_C2APB1ENR1_RTCAPBEN
#define | LL_C2_APB1_GRP1_PERIPH_SPI2 RCC_C2APB1ENR1_SPI2EN
#define | LL_C2_APB1_GRP1_PERIPH_I2C1 RCC_C2APB1ENR1_I2C1EN
#define | LL_C2_APB1_GRP1_PERIPH_I2C3 RCC_C2APB1ENR1_I2C3EN
#define | LL_C2_APB1_GRP1_PERIPH_CRS RCC_C2APB1ENR1_CRSEN
#define | LL_C2_APB1_GRP1_PERIPH_USB RCC_C2APB1ENR1_USBEN
#define | LL_C2_APB1_GRP1_PERIPH_LPTIM1 RCC_C2APB1ENR1_LPTIM1EN

Define Documentation

#define LL_C2_APB1_GRP1_PERIPH_CRS RCC_C2APB1ENR1_CRSEN

Definition at line 262 of file stm32wbxx_ll_bus.h.

#define LL_C2_APB1_GRP1_PERIPH_I2C1 RCC_C2APB1ENR1_I2C1EN

Definition at line 259 of file stm32wbxx_ll_bus.h.

#define LL_C2_APB1_GRP1_PERIPH_I2C3 RCC_C2APB1ENR1_I2C3EN

Definition at line 261 of file stm32wbxx_ll_bus.h.

#define LL_C2_APB1_GRP1_PERIPH_LCD RCC_C2APB1ENR1_LCDEN

Definition at line 253 of file stm32wbxx_ll_bus.h.

#define LL_C2_APB1_GRP1_PERIPH_LPTIM1 RCC_C2APB1ENR1_LPTIM1EN

Definition at line 265 of file stm32wbxx_ll_bus.h.

#define LL_C2_APB1_GRP1_PERIPH_RTCAPB RCC_C2APB1ENR1_RTCAPBEN

Definition at line 255 of file stm32wbxx_ll_bus.h.

#define LL_C2_APB1_GRP1_PERIPH_SPI2 RCC_C2APB1ENR1_SPI2EN

Definition at line 257 of file stm32wbxx_ll_bus.h.

#define LL_C2_APB1_GRP1_PERIPH_TIM2 RCC_C2APB1ENR1_TIM2EN

Definition at line 251 of file stm32wbxx_ll_bus.h.

#define LL_C2_APB1_GRP1_PERIPH_USB RCC_C2APB1ENR1_USBEN

Definition at line 263 of file stm32wbxx_ll_bus.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: C2 APB1 GRP2 PERIPH

Defines
C2 APB1 GRP2 PERIPH
BUS Exported Constants

Defines

#define | LL_C2_APB1_GRP2_PERIPH_LPUART1 RCC_C2APB1ENR2_LPUART1EN
#define | LL_C2_APB1_GRP2_PERIPH_LPTIM2 RCC_C2APB1ENR2_LPTIM2EN

Define Documentation

#define LL_C2_APB1_GRP2_PERIPH_LPTIM2 RCC_C2APB1ENR2_LPTIM2EN

Definition at line 277 of file stm32wbxx_ll_bus.h.

#define LL_C2_APB1_GRP2_PERIPH_LPUART1 RCC_C2APB1ENR2_LPUART1EN

Definition at line 275 of file stm32wbxx_ll_bus.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: C2 APB2 GRP1 PERIPH

Defines
C2 APB2 GRP1 PERIPH
BUS Exported Constants

Defines

#define | LL_C2_APB2_GRP1_PERIPH_TIM1 RCC_C2APB2ENR_TIM1EN
#define | LL_C2_APB2_GRP1_PERIPH_SPI1 RCC_C2APB2ENR_SPI1EN
#define | LL_C2_APB2_GRP1_PERIPH_USART1 RCC_C2APB2ENR_USART1EN
#define | LL_C2_APB2_GRP1_PERIPH_TIM16 RCC_C2APB2ENR_TIM16EN
#define | LL_C2_APB2_GRP1_PERIPH_TIM17 RCC_C2APB2ENR_TIM17EN
#define | LL_C2_APB2_GRP1_PERIPH_SAI1 RCC_C2APB2ENR_SAI1EN

Define Documentation

#define LL_C2_APB2_GRP1_PERIPH_SAI1 RCC_C2APB2ENR_SAI1EN

Definition at line 292 of file stm32wbxx_ll_bus.h.

#define LL_C2_APB2_GRP1_PERIPH_SPI1 RCC_C2APB2ENR_SPI1EN

Definition at line 287 of file stm32wbxx_ll_bus.h.

#define LL_C2_APB2_GRP1_PERIPH_TIM1 RCC_C2APB2ENR_TIM1EN

Definition at line 286 of file stm32wbxx_ll_bus.h.

#define LL_C2_APB2_GRP1_PERIPH_TIM16 RCC_C2APB2ENR_TIM16EN

Definition at line 289 of file stm32wbxx_ll_bus.h.

#define LL_C2_APB2_GRP1_PERIPH_TIM17 RCC_C2APB2ENR_TIM17EN

Definition at line 290 of file stm32wbxx_ll_bus.h.

#define LL_C2_APB2_GRP1_PERIPH_USART1 RCC_C2APB2ENR_USART1EN

Definition at line 288 of file stm32wbxx_ll_bus.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: C2 APB3 GRP1 PERIPH

Defines
C2 APB3 GRP1 PERIPH
BUS Exported Constants

Defines

#define | LL_C2_APB3_GRP1_PERIPH_BLE RCC_C2APB3ENR_BLEEN
#define | LL_C2_APB3_GRP1_PERIPH_802 RCC_C2APB3ENR_802EN

Define Documentation

#define LL_C2_APB3_GRP1_PERIPH_802 RCC_C2APB3ENR_802EN

Definition at line 303 of file stm32wbxx_ll_bus.h.

#define LL_C2_APB3_GRP1_PERIPH_BLE RCC_C2APB3ENR_BLEEN

Definition at line 302 of file stm32wbxx_ll_bus.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: AHB1

Functions
AHB1
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_AHB1_GRP1_EnableClock (uint32_t Periphs)
Enable AHB1 peripherals clock.
__STATIC_INLINE uint32_t | LL_AHB1_GRP1_IsEnabledClock (uint32_t Periphs)
Check if AHB1 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_AHB1_GRP1_DisableClock (uint32_t Periphs)
Disable AHB1 peripherals clock.
__STATIC_INLINE void | LL_AHB1_GRP1_ForceReset (uint32_t Periphs)
Force AHB1 peripherals reset.
__STATIC_INLINE void | LL_AHB1_GRP1_ReleaseReset (uint32_t Periphs)
Release AHB1 peripherals reset.
__STATIC_INLINE void | LL_AHB1_GRP1_EnableClockSleep (uint32_t Periphs)
Enable AHB1 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_AHB1_GRP1_DisableClockSleep (uint32_t Periphs)
Disable AHB1 peripherals clock during Low Power (Sleep) mode.

Function Documentation

__STATIC_INLINE void LL_AHB1_GRP1_DisableClock ( uint32_t Periphs )

Disable AHB1 peripherals clock.

Reference Manual to LL API cross reference:
AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock
AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock
AHB1ENR DMAMUX1EN LL_AHB1_GRP1_DisableClock
AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock
AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_DMAMUX1
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_TSC
Return values:
None

Definition at line 384 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep ( uint32_t Periphs )

Disable AHB1 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
AHB1SMENR DMA1SMEN LL_AHB1_GRP1_DisableClockSleep
AHB1SMENR DMA2SMEN LL_AHB1_GRP1_DisableClockSleep
AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_DisableClockSleep
AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockSleep
AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockSleep
AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_DMAMUX1
  • LL_AHB1_GRP1_PERIPH_SRAM1
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_TSC
Return values:
None

Definition at line 474 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_AHB1_GRP1_EnableClock ( uint32_t Periphs )

Enable AHB1 peripherals clock.

Reference Manual to LL API cross reference:
AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock
AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock
AHB1ENR DMAMUX1EN LL_AHB1_GRP1_EnableClock
AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock
AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_DMAMUX1
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_TSC
Return values:
None

Definition at line 340 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep ( uint32_t Periphs )

Enable AHB1 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
AHB1SMENR DMA1SMEN LL_AHB1_GRP1_EnableClockSleep
AHB1SMENR DMA2SMEN LL_AHB1_GRP1_EnableClockSleep
AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_EnableClockSleep
AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockSleep
AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockSleep
AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_DMAMUX1
  • LL_AHB1_GRP1_PERIPH_SRAM1
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_TSC
Return values:
None

Definition at line 448 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_AHB1_GRP1_ForceReset ( uint32_t Periphs )

Force AHB1 peripherals reset.

Reference Manual to LL API cross reference:
AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset
AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset
AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ForceReset
AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset
AHB1RSTR TSCRST LL_AHB1_GRP1_ForceReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_ALL
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_DMAMUX1
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_TSC
Return values:
None

Definition at line 405 of file stm32wbxx_ll_bus.h.

Referenced by LL_CRC_DeInit(), and LL_DMA_DeInit().

__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock ( uint32_t Periphs )

Check if AHB1 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR DMAMUX1EN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_DMAMUX1
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_TSC
Return values:
uint32_t

Definition at line 364 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset ( uint32_t Periphs )

Release AHB1 peripherals reset.

Reference Manual to LL API cross reference:
AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR TSCRST LL_AHB1_GRP1_ReleaseReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_ALL
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_DMAMUX1
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_TSC
Return values:
None

Definition at line 426 of file stm32wbxx_ll_bus.h.

Referenced by LL_CRC_DeInit(), and LL_DMA_DeInit().

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: AHB2

Functions
AHB2
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_AHB2_GRP1_EnableClock (uint32_t Periphs)
Enable AHB2 peripherals clock.
__STATIC_INLINE uint32_t | LL_AHB2_GRP1_IsEnabledClock (uint32_t Periphs)
Check if AHB2 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_AHB2_GRP1_DisableClock (uint32_t Periphs)
Disable AHB2 peripherals clock.
__STATIC_INLINE void | LL_AHB2_GRP1_ForceReset (uint32_t Periphs)
Force AHB2 peripherals reset.
__STATIC_INLINE void | LL_AHB2_GRP1_ReleaseReset (uint32_t Periphs)
Release AHB2 peripherals reset.
__STATIC_INLINE void | LL_AHB2_GRP1_EnableClockSleep (uint32_t Periphs)
Enable AHB2 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_AHB2_GRP1_DisableClockSleep (uint32_t Periphs)
Disable AHB2 peripherals clock during Low Power (Sleep) mode.

Function Documentation

__STATIC_INLINE void LL_AHB2_GRP1_DisableClock ( uint32_t Periphs )

Disable AHB2 peripherals clock.

Reference Manual to LL API cross reference:
AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock
AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock
AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock
AHB2ENR GPIODEN LL_AHB2_GRP1_DisableClock
AHB2ENR GPIOEEN LL_AHB2_GRP1_DisableClock
AHB2ENR GPIOHEN LL_AHB2_GRP1_DisableClock
AHB2ENR ADCEN LL_AHB2_GRP1_DisableClock
AHB2ENR AES1EN LL_AHB2_GRP1_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB2_GRP1_PERIPH_GPIOA
  • LL_AHB2_GRP1_PERIPH_GPIOB
  • LL_AHB2_GRP1_PERIPH_GPIOC
  • LL_AHB2_GRP1_PERIPH_GPIOD
  • LL_AHB2_GRP1_PERIPH_GPIOE
  • LL_AHB2_GRP1_PERIPH_GPIOH
  • LL_AHB2_GRP1_PERIPH_ADC
  • LL_AHB2_GRP1_PERIPH_AES1
Return values:
None

Definition at line 564 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_AHB2_GRP1_DisableClockSleep ( uint32_t Periphs )

Disable AHB2 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
AHB2SMENR GPIOASMEN LL_AHB2_GRP1_DisableClockSleep
AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_DisableClockSleep
AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_DisableClockSleep
AHB2SMENR GPIODSMEN LL_AHB2_GRP1_DisableClockSleep
AHB2SMENR GPIOESMEN LL_AHB2_GRP1_DisableClockSleep
AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_DisableClockSleep
AHB2SMENR ADCSMEN LL_AHB2_GRP1_DisableClockSleep
AHB2SMENR AES1SMEN LL_AHB2_GRP1_DisableClockSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB2_GRP1_PERIPH_GPIOA
  • LL_AHB2_GRP1_PERIPH_GPIOB
  • LL_AHB2_GRP1_PERIPH_GPIOC
  • LL_AHB2_GRP1_PERIPH_GPIOD
  • LL_AHB2_GRP1_PERIPH_GPIOE
  • LL_AHB2_GRP1_PERIPH_GPIOH
  • LL_AHB2_GRP1_PERIPH_ADC
  • LL_AHB2_GRP1_PERIPH_AES1
Return values:
None

Definition at line 674 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_AHB2_GRP1_EnableClock ( uint32_t Periphs )

Enable AHB2 peripherals clock.

Reference Manual to LL API cross reference:
AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock
AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock
AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock
AHB2ENR GPIODEN LL_AHB2_GRP1_EnableClock
AHB2ENR GPIOEEN LL_AHB2_GRP1_EnableClock
AHB2ENR GPIOHEN LL_AHB2_GRP1_EnableClock
AHB2ENR ADCEN LL_AHB2_GRP1_EnableClock
AHB2ENR AES1EN LL_AHB2_GRP1_EnableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB2_GRP1_PERIPH_GPIOA
  • LL_AHB2_GRP1_PERIPH_GPIOB
  • LL_AHB2_GRP1_PERIPH_GPIOC
  • LL_AHB2_GRP1_PERIPH_GPIOD
  • LL_AHB2_GRP1_PERIPH_GPIOE
  • LL_AHB2_GRP1_PERIPH_GPIOH
  • LL_AHB2_GRP1_PERIPH_ADC
  • LL_AHB2_GRP1_PERIPH_AES1
Return values:
None

Definition at line 508 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_AHB2_GRP1_EnableClockSleep ( uint32_t Periphs )

Enable AHB2 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
AHB2SMENR GPIOASMEN LL_AHB2_GRP1_EnableClockSleep
AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_EnableClockSleep
AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_EnableClockSleep
AHB2SMENR GPIODSMEN LL_AHB2_GRP1_EnableClockSleep
AHB2SMENR GPIOESMEN LL_AHB2_GRP1_EnableClockSleep
AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_EnableClockSleep
AHB2SMENR ADCSMEN LL_AHB2_GRP1_EnableClockSleep
AHB2SMENR AES1SMEN LL_AHB2_GRP1_EnableClockSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB2_GRP1_PERIPH_GPIOA
  • LL_AHB2_GRP1_PERIPH_GPIOB
  • LL_AHB2_GRP1_PERIPH_GPIOC
  • LL_AHB2_GRP1_PERIPH_GPIOD
  • LL_AHB2_GRP1_PERIPH_GPIOE
  • LL_AHB2_GRP1_PERIPH_GPIOH
  • LL_AHB2_GRP1_PERIPH_ADC
  • LL_AHB2_GRP1_PERIPH_AES1
Return values:
None

Definition at line 644 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_AHB2_GRP1_ForceReset ( uint32_t Periphs )

Force AHB2 peripherals reset.

Reference Manual to LL API cross reference:
AHB2RSTR GPIOARST LL_AHB2_GRP1_ForceReset
AHB2RSTR GPIOBRST LL_AHB2_GRP1_ForceReset
AHB2RSTR GPIOCRST LL_AHB2_GRP1_ForceReset
AHB2RSTR GPIODRST LL_AHB2_GRP1_ForceReset
AHB2RSTR GPIOERST LL_AHB2_GRP1_ForceReset
AHB2RSTR GPIOHRST LL_AHB2_GRP1_ForceReset
AHB2RSTR ADCRST LL_AHB2_GRP1_ForceReset
AHB2RSTR AES1RST LL_AHB2_GRP1_ForceReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB2_GRP1_PERIPH_ALL
  • LL_AHB2_GRP1_PERIPH_GPIOA
  • LL_AHB2_GRP1_PERIPH_GPIOB
  • LL_AHB2_GRP1_PERIPH_GPIOC
  • LL_AHB2_GRP1_PERIPH_GPIOD
  • LL_AHB2_GRP1_PERIPH_GPIOE
  • LL_AHB2_GRP1_PERIPH_GPIOH
  • LL_AHB2_GRP1_PERIPH_ADC
  • LL_AHB2_GRP1_PERIPH_AES1
Return values:
None

Definition at line 591 of file stm32wbxx_ll_bus.h.

Referenced by LL_ADC_CommonDeInit(), and LL_GPIO_DeInit().

__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock ( uint32_t Periphs )

Check if AHB2 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR GPIODEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR GPIOEEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR GPIOHEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR ADCEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR AES1EN LL_AHB2_GRP1_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB2_GRP1_PERIPH_GPIOA
  • LL_AHB2_GRP1_PERIPH_GPIOB
  • LL_AHB2_GRP1_PERIPH_GPIOC
  • LL_AHB2_GRP1_PERIPH_GPIOD
  • LL_AHB2_GRP1_PERIPH_GPIOE
  • LL_AHB2_GRP1_PERIPH_GPIOH
  • LL_AHB2_GRP1_PERIPH_ADC
  • LL_AHB2_GRP1_PERIPH_AES1
Return values:
uint32_t

Definition at line 538 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset ( uint32_t Periphs )

Release AHB2 peripherals reset.

Reference Manual to LL API cross reference:
AHB2RSTR GPIOARST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR GPIOBRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR GPIOCRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR GPIODRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR GPIOERST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR GPIOHRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR ADCRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR AES1RST LL_AHB2_GRP1_ReleaseReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB2_GRP1_PERIPH_ALL
  • LL_AHB2_GRP1_PERIPH_GPIOA
  • LL_AHB2_GRP1_PERIPH_GPIOB
  • LL_AHB2_GRP1_PERIPH_GPIOC
  • LL_AHB2_GRP1_PERIPH_GPIOD
  • LL_AHB2_GRP1_PERIPH_GPIOE
  • LL_AHB2_GRP1_PERIPH_GPIOH
  • LL_AHB2_GRP1_PERIPH_ADC
  • LL_AHB2_GRP1_PERIPH_AES1
Return values:
None

Definition at line 618 of file stm32wbxx_ll_bus.h.

Referenced by LL_ADC_CommonDeInit(), and LL_GPIO_DeInit().

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: AHB3

Functions
AHB3
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_AHB3_GRP1_EnableClock (uint32_t Periphs)
Enable AHB3 peripherals clock.
__STATIC_INLINE uint32_t | LL_AHB3_GRP1_IsEnabledClock (uint32_t Periphs)
Check if AHB3 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_AHB3_GRP1_DisableClock (uint32_t Periphs)
Disable AHB3 peripherals clock.
__STATIC_INLINE void | LL_AHB3_GRP1_ForceReset (uint32_t Periphs)
Force AHB3 peripherals reset.
__STATIC_INLINE void | LL_AHB3_GRP1_ReleaseReset (uint32_t Periphs)
Release AHB3 peripherals reset.
__STATIC_INLINE void | LL_AHB3_GRP1_EnableClockSleep (uint32_t Periphs)
Enable AHB3 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_AHB3_GRP1_DisableClockSleep (uint32_t Periphs)
Disable AHB3 peripherals clock during Low Power (Sleep) mode.

Function Documentation

__STATIC_INLINE void LL_AHB3_GRP1_DisableClock ( uint32_t Periphs )

Disable AHB3 peripherals clock.

Reference Manual to LL API cross reference:
AHB3ENR QUADSPIEN LL_AHB3_GRP1_DisableClock
AHB3ENR PKAEN LL_AHB3_GRP1_DisableClock
AHB3ENR AES2EN LL_AHB3_GRP1_DisableClock
AHB3ENR RNGEN LL_AHB3_GRP1_DisableClock
AHB3ENR HSEMEN LL_AHB3_GRP1_DisableClock
AHB3ENR IPCCEN LL_AHB3_GRP1_DisableClock
AHB3ENR FLASHEN LL_AHB3_GRP1_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB3_GRP1_PERIPH_QUADSPI
  • LL_AHB3_GRP1_PERIPH_PKA
  • LL_AHB3_GRP1_PERIPH_AES2
  • LL_AHB3_GRP1_PERIPH_RNG
  • LL_AHB3_GRP1_PERIPH_HSEM
  • LL_AHB3_GRP1_PERIPH_IPCC
  • LL_AHB3_GRP1_PERIPH_FLASH
Return values:
None

Definition at line 758 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_AHB3_GRP1_DisableClockSleep ( uint32_t Periphs )

Disable AHB3 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
AHB3SMENR QUADSPISMEN LL_AHB3_GRP1_DisableClockSleep
AHB3SMENR PKASMEN LL_AHB3_GRP1_DisableClockSleep
AHB3SMENR AES2SMEN LL_AHB3_GRP1_DisableClockSleep
AHB3SMENR RNGSMEN LL_AHB3_GRP1_DisableClockSleep
AHB3SMENR SRAM2SMEN LL_AHB3_GRP1_DisableClockSleep
AHB3SMENR FLASHSMEN LL_AHB3_GRP1_DisableClockSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB3_GRP1_PERIPH_QUADSPI
  • LL_AHB3_GRP1_PERIPH_PKA
  • LL_AHB3_GRP1_PERIPH_AES2
  • LL_AHB3_GRP1_PERIPH_RNG
  • LL_AHB3_GRP1_PERIPH_SRAM2
  • LL_AHB3_GRP1_PERIPH_FLASH
Return values:
None

Definition at line 856 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_AHB3_GRP1_EnableClock ( uint32_t Periphs )

Enable AHB3 peripherals clock.

Reference Manual to LL API cross reference:
AHB3ENR QUADSPIEN LL_AHB3_GRP1_EnableClock
AHB3ENR PKAEN LL_AHB3_GRP1_EnableClock
AHB3ENR AES2EN LL_AHB3_GRP1_EnableClock
AHB3ENR RNGEN LL_AHB3_GRP1_EnableClock
AHB3ENR HSEMEN LL_AHB3_GRP1_EnableClock
AHB3ENR IPCCEN LL_AHB3_GRP1_EnableClock
AHB3ENR FLASHEN LL_AHB3_GRP1_EnableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB3_GRP1_PERIPH_QUADSPI
  • LL_AHB3_GRP1_PERIPH_PKA
  • LL_AHB3_GRP1_PERIPH_AES2
  • LL_AHB3_GRP1_PERIPH_RNG
  • LL_AHB3_GRP1_PERIPH_HSEM
  • LL_AHB3_GRP1_PERIPH_IPCC
  • LL_AHB3_GRP1_PERIPH_FLASH
Return values:
None

Definition at line 706 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_AHB3_GRP1_EnableClockSleep ( uint32_t Periphs )

Enable AHB3 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
AHB3SMENR QUADSPISMEN LL_AHB3_GRP1_EnableClockSleep
AHB3SMENR PKASMEN LL_AHB3_GRP1_EnableClockSleep
AHB3SMENR AES2SMEN LL_AHB3_GRP1_EnableClockSleep
AHB3SMENR RNGSMEN LL_AHB3_GRP1_EnableClockSleep
AHB3SMENR SRAM2SMEN LL_AHB3_GRP1_EnableClockSleep
AHB3SMENR FLASHSMEN LL_AHB3_GRP1_EnableClockSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB3_GRP1_PERIPH_QUADSPI
  • LL_AHB3_GRP1_PERIPH_PKA
  • LL_AHB3_GRP1_PERIPH_AES2
  • LL_AHB3_GRP1_PERIPH_RNG
  • LL_AHB3_GRP1_PERIPH_SRAM2
  • LL_AHB3_GRP1_PERIPH_FLASH
Return values:
None

Definition at line 830 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_AHB3_GRP1_ForceReset ( uint32_t Periphs )

Force AHB3 peripherals reset.

Reference Manual to LL API cross reference:
AHB3RSTR QUADSPIRST LL_AHB3_GRP1_ForceReset
AHB3RSTR PKARST LL_AHB3_GRP1_ForceReset
AHB3RSTR AES2RST LL_AHB3_GRP1_ForceReset
AHB3RSTR RNGRST LL_AHB3_GRP1_ForceReset
AHB3RSTR HSEMRST LL_AHB3_GRP1_ForceReset
AHB3RSTR IPCCRST LL_AHB3_GRP1_ForceReset
AHB3RSTR FLASHRST LL_AHB3_GRP1_ForceReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB3_GRP1_PERIPH_ALL
  • LL_AHB3_GRP1_PERIPH_QUADSPI
  • LL_AHB3_GRP1_PERIPH_PKA
  • LL_AHB3_GRP1_PERIPH_AES2
  • LL_AHB3_GRP1_PERIPH_RNG
  • LL_AHB3_GRP1_PERIPH_HSEM
  • LL_AHB3_GRP1_PERIPH_IPCC
  • LL_AHB3_GRP1_PERIPH_FLASH
Return values:
None

Definition at line 783 of file stm32wbxx_ll_bus.h.

Referenced by LL_PKA_DeInit(), and LL_RNG_DeInit().

__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock ( uint32_t Periphs )

Check if AHB3 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
AHB3ENR QUADSPIEN LL_AHB3_GRP1_IsEnabledClock
AHB3ENR PKAEN LL_AHB3_GRP1_IsEnabledClock
AHB3ENR AES2EN LL_AHB3_GRP1_IsEnabledClock
AHB3ENR RNGEN LL_AHB3_GRP1_IsEnabledClock
AHB3ENR HSEMEN LL_AHB3_GRP1_IsEnabledClock
AHB3ENR IPCCEN LL_AHB3_GRP1_IsEnabledClock
AHB3ENR FLASHEN LL_AHB3_GRP1_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB3_GRP1_PERIPH_QUADSPI
  • LL_AHB3_GRP1_PERIPH_PKA
  • LL_AHB3_GRP1_PERIPH_AES2
  • LL_AHB3_GRP1_PERIPH_RNG
  • LL_AHB3_GRP1_PERIPH_HSEM
  • LL_AHB3_GRP1_PERIPH_IPCC
  • LL_AHB3_GRP1_PERIPH_FLASH
Return values:
uint32_t

Definition at line 734 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset ( uint32_t Periphs )

Release AHB3 peripherals reset.

Reference Manual to LL API cross reference:
AHB3RSTR QUADSPIRST LL_AHB3_GRP1_ReleaseReset
AHB3RSTR PKARST LL_AHB3_GRP1_ReleaseReset
AHB3RSTR AES2RST LL_AHB3_GRP1_ReleaseReset
AHB3RSTR RNGRST LL_AHB3_GRP1_ReleaseReset
AHB3RSTR HSEMRST LL_AHB3_GRP1_ReleaseReset
AHB3RSTR IPCCRST LL_AHB3_GRP1_ReleaseReset
AHB3RSTR FLASHRST LL_AHB3_GRP1_ReleaseReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB2_GRP1_PERIPH_ALL
  • LL_AHB3_GRP1_PERIPH_QUADSPI
  • LL_AHB3_GRP1_PERIPH_PKA
  • LL_AHB3_GRP1_PERIPH_AES2
  • LL_AHB3_GRP1_PERIPH_RNG
  • LL_AHB3_GRP1_PERIPH_HSEM
  • LL_AHB3_GRP1_PERIPH_IPCC
  • LL_AHB3_GRP1_PERIPH_FLASH
Return values:
None

Definition at line 808 of file stm32wbxx_ll_bus.h.

Referenced by LL_PKA_DeInit(), and LL_RNG_DeInit().

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: APB1

Functions
APB1
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_APB1_GRP1_EnableClock (uint32_t Periphs)
Enable APB1 peripherals clock.
__STATIC_INLINE void | LL_APB1_GRP2_EnableClock (uint32_t Periphs)
Enable APB1 peripherals clock.
__STATIC_INLINE uint32_t | LL_APB1_GRP1_IsEnabledClock (uint32_t Periphs)
Check if APB1 peripheral clock is enabled or not.
__STATIC_INLINE uint32_t | LL_APB1_GRP2_IsEnabledClock (uint32_t Periphs)
Check if APB1 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_APB1_GRP1_DisableClock (uint32_t Periphs)
Disable APB1 peripherals clock.
__STATIC_INLINE void | LL_APB1_GRP2_DisableClock (uint32_t Periphs)
Disable APB1 peripherals clock.
__STATIC_INLINE void | LL_APB1_GRP1_ForceReset (uint32_t Periphs)
Force APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP2_ForceReset (uint32_t Periphs)
Force APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP1_ReleaseReset (uint32_t Periphs)
Release APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP2_ReleaseReset (uint32_t Periphs)
Release APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP1_EnableClockSleep (uint32_t Periphs)
Enable APB1 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_APB1_GRP2_EnableClockSleep (uint32_t Periphs)
Enable APB1 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_APB1_GRP1_DisableClockSleep (uint32_t Periphs)
Disable APB1 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_APB1_GRP2_DisableClockSleep (uint32_t Periphs)
Disable APB1 peripherals clock during Low Power (Sleep) mode.

Function Documentation

__STATIC_INLINE void LL_APB1_GRP1_DisableClock ( uint32_t Periphs )

Disable APB1 peripherals clock.

Reference Manual to LL API cross reference:
APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock
APB1ENR1 LCDEN LL_APB1_GRP1_DisableClock
APB1ENR1 RTCAPBEN LL_APB1_GRP1_DisableClock
APB1ENR1 SPI2EN LL_APB1_GRP1_DisableClock
APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock
APB1ENR1 I2C3EN LL_APB1_GRP1_DisableClock
APB1ENR1 CRSEN LL_APB1_GRP1_DisableClock
APB1ENR1 USBEN LL_APB1_GRP1_DisableClock
APB1ENR1 LPTIM1EN LL_APB1_GRP1_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_TIM2
  • LL_APB1_GRP1_PERIPH_LCD
  • LL_APB1_GRP1_PERIPH_RTCAPB
  • LL_APB1_GRP1_PERIPH_WWDG
  • LL_APB1_GRP1_PERIPH_SPI2
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C3
  • LL_APB1_GRP1_PERIPH_CRS
  • LL_APB1_GRP1_PERIPH_USB
  • LL_APB1_GRP1_PERIPH_LPTIM1
Return values:
None

Definition at line 989 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep ( uint32_t Periphs )

Disable APB1 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockSleep
APB1SMENR1 LCDSMEN LL_APB1_GRP1_DisableClockSleep
APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_DisableClockSleep
APB1SMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockSleep
APB1SMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockSleep
APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockSleep
APB1SMENR1 I2C3SMEN LL_APB1_GRP1_DisableClockSleep
APB1SMENR1 CRSSMEN LL_APB1_GRP1_DisableClockSleep
APB1SMENR1 USBSMEN LL_APB1_GRP1_DisableClockSleep
APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_DisableClockSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_TIM2
  • LL_APB1_GRP1_PERIPH_LCD
  • LL_APB1_GRP1_PERIPH_RTCAPB
  • LL_APB1_GRP1_PERIPH_WWDG
  • LL_APB1_GRP1_PERIPH_SPI2
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C3
  • LL_APB1_GRP1_PERIPH_CRS
  • LL_APB1_GRP1_PERIPH_USB
  • LL_APB1_GRP1_PERIPH_LPTIM1
Return values:
None

Definition at line 1169 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP1_EnableClock ( uint32_t Periphs )

Enable APB1 peripherals clock.

Reference Manual to LL API cross reference:
APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock
APB1ENR1 LCDEN LL_APB1_GRP1_EnableClock
APB1ENR1 RTCAPBEN LL_APB1_GRP1_EnableClock
APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock
APB1ENR1 SPI2EN LL_APB1_GRP1_EnableClock
APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock
APB1ENR1 I2C3EN LL_APB1_GRP1_EnableClock
APB1ENR1 CRSEN LL_APB1_GRP1_EnableClock
APB1ENR1 USBEN LL_APB1_GRP1_EnableClock
APB1ENR1 LPTIM1EN LL_APB1_GRP1_EnableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_TIM2
  • LL_APB1_GRP1_PERIPH_LCD
  • LL_APB1_GRP1_PERIPH_RTCAPB
  • LL_APB1_GRP1_PERIPH_WWDG
  • LL_APB1_GRP1_PERIPH_SPI2
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C3
  • LL_APB1_GRP1_PERIPH_CRS
  • LL_APB1_GRP1_PERIPH_USB
  • LL_APB1_GRP1_PERIPH_LPTIM1
Return values:
None

Definition at line 894 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep ( uint32_t Periphs )

Enable APB1 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockSleep
APB1SMENR1 LCDSMEN LL_APB1_GRP1_EnableClockSleep
APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_EnableClockSleep
APB1SMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockSleep
APB1SMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockSleep
APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockSleep
APB1SMENR1 I2C3SMEN LL_APB1_GRP1_EnableClockSleep
APB1SMENR1 CRSSMEN LL_APB1_GRP1_EnableClockSleep
APB1SMENR1 USBSMEN LL_APB1_GRP1_EnableClockSleep
APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_EnableClockSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_TIM2
  • LL_APB1_GRP1_PERIPH_LCD
  • LL_APB1_GRP1_PERIPH_RTCAPB
  • LL_APB1_GRP1_PERIPH_WWDG
  • LL_APB1_GRP1_PERIPH_SPI2
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C3
  • LL_APB1_GRP1_PERIPH_CRS
  • LL_APB1_GRP1_PERIPH_USB
  • LL_APB1_GRP1_PERIPH_LPTIM1
Return values:
None

Definition at line 1117 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP1_ForceReset ( uint32_t Periphs )

Force APB1 peripherals reset.

Reference Manual to LL API cross reference:
APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset
APB1RSTR1 LCDRST LL_APB1_GRP1_ForceReset
APB1RSTR1 SPI2RST LL_APB1_GRP1_ForceReset
APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset
APB1RSTR1 I2C3RST LL_APB1_GRP1_ForceReset
APB1RSTR1 CRSRST LL_APB1_GRP1_ForceReset
APB1RSTR1 USBRST LL_APB1_GRP1_ForceReset
APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ForceReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_ALL
  • LL_APB1_GRP1_PERIPH_TIM2
  • LL_APB1_GRP1_PERIPH_LCD
  • LL_APB1_GRP1_PERIPH_SPI2
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C3
  • LL_APB1_GRP1_PERIPH_CRS
  • LL_APB1_GRP1_PERIPH_USB
  • LL_APB1_GRP1_PERIPH_LPTIM1
Return values:
None

Definition at line 1030 of file stm32wbxx_ll_bus.h.

Referenced by LL_CRS_DeInit(), LL_I2C_DeInit(), LL_LPTIM_DeInit(), LL_SPI_DeInit(), and LL_TIM_DeInit().

__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock ( uint32_t Periphs )

Check if APB1 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 LCDEN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 RTCAPBEN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 CRSEN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 USBEN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_TIM2
  • LL_APB1_GRP1_PERIPH_LCD
  • LL_APB1_GRP1_PERIPH_RTCAPB
  • LL_APB1_GRP1_PERIPH_WWDG
  • LL_APB1_GRP1_PERIPH_SPI2
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C3
  • LL_APB1_GRP1_PERIPH_CRS
  • LL_APB1_GRP1_PERIPH_USB
  • LL_APB1_GRP1_PERIPH_LPTIM1
Return values:
uint32_t

Definition at line 946 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset ( uint32_t Periphs )

Release APB1 peripherals reset.

Reference Manual to LL API cross reference:
APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 LCDRST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 I2C3RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 CRSRST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 USBRST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ReleaseReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_ALL
  • LL_APB1_GRP1_PERIPH_TIM2
  • LL_APB1_GRP1_PERIPH_LCD
  • LL_APB1_GRP1_PERIPH_SPI2
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C3
  • LL_APB1_GRP1_PERIPH_CRS
  • LL_APB1_GRP1_PERIPH_USB
  • LL_APB1_GRP1_PERIPH_LPTIM1
Return values:
None

Definition at line 1072 of file stm32wbxx_ll_bus.h.

Referenced by LL_CRS_DeInit(), LL_I2C_DeInit(), LL_LPTIM_DeInit(), LL_SPI_DeInit(), and LL_TIM_DeInit().

__STATIC_INLINE void LL_APB1_GRP2_DisableClock ( uint32_t Periphs )

Disable APB1 peripherals clock.

Reference Manual to LL API cross reference:
APB1ENR2 LPUART1EN LL_APB1_GRP2_DisableClock
APB1ENR2 LPTIM2EN LL_APB1_GRP2_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP2_PERIPH_LPUART1
  • LL_APB1_GRP2_PERIPH_LPTIM2
Return values:
None

Definition at line 1003 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP2_DisableClockSleep ( uint32_t Periphs )

Disable APB1 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_DisableClockSleep
APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP2_PERIPH_LPUART1
  • LL_APB1_GRP2_PERIPH_LPTIM2
Return values:
None

Definition at line 1183 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP2_EnableClock ( uint32_t Periphs )

Enable APB1 peripherals clock.

Reference Manual to LL API cross reference:
APB1ENR2 LPUART1EN LL_APB1_GRP2_EnableClock
APB1ENR2 LPTIM2EN LL_APB1_GRP2_EnableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP2_PERIPH_LPUART1
  • LL_APB1_GRP2_PERIPH_LPTIM2
Return values:
None

Definition at line 912 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP2_EnableClockSleep ( uint32_t Periphs )

Enable APB1 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_EnableClockSleep
APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP2_PERIPH_LPUART1
  • LL_APB1_GRP2_PERIPH_LPTIM2
Return values:
None

Definition at line 1135 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP2_ForceReset ( uint32_t Periphs )

Force APB1 peripherals reset.

Reference Manual to LL API cross reference:
APB1RSTR2 LPUART1RST LL_APB1_GRP2_ForceReset
APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ForceReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP2_PERIPH_ALL
  • LL_APB1_GRP2_PERIPH_LPUART1
  • LL_APB1_GRP2_PERIPH_LPTIM2
Return values:
None

Definition at line 1045 of file stm32wbxx_ll_bus.h.

Referenced by LL_LPTIM_DeInit(), and LL_LPUART_DeInit().

__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock ( uint32_t Periphs )

Check if APB1 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
APB1ENR2 LPUART1EN LL_APB1_GRP2_IsEnabledClock
APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP2_PERIPH_LPUART1
  • LL_APB1_GRP2_PERIPH_LPTIM2
Return values:
uint32_t

Definition at line 960 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset ( uint32_t Periphs )

Release APB1 peripherals reset.

Reference Manual to LL API cross reference:
APB1RSTR2 LPUART1RST LL_APB1_GRP2_ReleaseReset
APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ReleaseReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP2_PERIPH_ALL
  • LL_APB1_GRP2_PERIPH_LPUART1
  • LL_APB1_GRP2_PERIPH_LPTIM2
Return values:
None

Definition at line 1087 of file stm32wbxx_ll_bus.h.

Referenced by LL_LPTIM_DeInit(), and LL_LPUART_DeInit().

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: APB2

Functions
APB2
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_APB2_GRP1_EnableClock (uint32_t Periphs)
Enable APB2 peripherals clock.
__STATIC_INLINE uint32_t | LL_APB2_GRP1_IsEnabledClock (uint32_t Periphs)
Check if APB2 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_APB2_GRP1_DisableClock (uint32_t Periphs)
Disable APB2 peripherals clock.
__STATIC_INLINE void | LL_APB2_GRP1_ForceReset (uint32_t Periphs)
Force APB2 peripherals reset.
__STATIC_INLINE void | LL_APB2_GRP1_ReleaseReset (uint32_t Periphs)
Release APB2 peripherals reset.
__STATIC_INLINE void | LL_APB2_GRP1_EnableClockSleep (uint32_t Periphs)
Enable APB2 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_APB2_GRP1_DisableClockSleep (uint32_t Periphs)
Disable APB2 peripherals clock during Low Power (Sleep) mode.

Function Documentation

__STATIC_INLINE void LL_APB2_GRP1_DisableClock ( uint32_t Periphs )

Disable APB2 peripherals clock.

Reference Manual to LL API cross reference:
APB2ENR TIM1EN LL_APB2_GRP1_DisableClock
APB2ENR SPI1EN LL_APB2_GRP1_DisableClock
APB2ENR USART1EN LL_APB2_GRP1_DisableClock
APB2ENR TIM16EN LL_APB2_GRP1_DisableClock
APB2ENR TIM17EN LL_APB2_GRP1_DisableClock
APB2ENR SAI1EN LL_APB2_GRP1_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17
  • LL_APB2_GRP1_PERIPH_SAI1
Return values:
None

Definition at line 1261 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep ( uint32_t Periphs )

Disable APB2 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockSleep
APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockSleep
APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockSleep
APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockSleep
APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockSleep
APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17
  • LL_APB2_GRP1_PERIPH_SAI1
Return values:
None

Definition at line 1355 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_APB2_GRP1_EnableClock ( uint32_t Periphs )

Enable APB2 peripherals clock.

Reference Manual to LL API cross reference:
APB2ENR TIM1EN LL_APB2_GRP1_EnableClock
APB2ENR SPI1EN LL_APB2_GRP1_EnableClock
APB2ENR USART1EN LL_APB2_GRP1_EnableClock
APB2ENR TIM16EN LL_APB2_GRP1_EnableClock
APB2ENR TIM17EN LL_APB2_GRP1_EnableClock
APB2ENR SAI1EN LL_APB2_GRP1_EnableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17
  • LL_APB2_GRP1_PERIPH_SAI1
Return values:
None

Definition at line 1213 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep ( uint32_t Periphs )

Enable APB2 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockSleep
APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockSleep
APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockSleep
APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockSleep
APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockSleep
APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17
  • LL_APB2_GRP1_PERIPH_SAI1
Return values:
None

Definition at line 1329 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_APB2_GRP1_ForceReset ( uint32_t Periphs )

Force APB2 peripherals reset.

Reference Manual to LL API cross reference:
APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset
APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset
APB2RSTR USART1RST LL_APB2_GRP1_ForceReset
APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset
APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset
APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_ALL
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17
  • LL_APB2_GRP1_PERIPH_SAI1
Return values:
None

Definition at line 1284 of file stm32wbxx_ll_bus.h.

Referenced by LL_SPI_DeInit(), LL_TIM_DeInit(), and LL_USART_DeInit().

__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock ( uint32_t Periphs )

Check if APB2 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock
APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock
APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock
APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock
APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock
APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17
  • LL_APB2_GRP1_PERIPH_SAI1
Return values:
uint32_t

Definition at line 1239 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset ( uint32_t Periphs )

Release APB2 peripherals reset.

Reference Manual to LL API cross reference:
APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset
APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset
APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset
APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset
APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset
APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_ALL
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_USART1
  • LL_APB2_GRP1_PERIPH_TIM16
  • LL_APB2_GRP1_PERIPH_TIM17
  • LL_APB2_GRP1_PERIPH_SAI1
Return values:
None

Definition at line 1307 of file stm32wbxx_ll_bus.h.

Referenced by LL_SPI_DeInit(), LL_TIM_DeInit(), and LL_USART_DeInit().

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: APB3

Functions
APB3
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_APB3_GRP1_ForceReset (uint32_t Periphs)
Force APB3 peripherals reset.
__STATIC_INLINE void | LL_APB3_GRP1_ReleaseReset (uint32_t Periphs)
Release APB3 peripherals reset.

Function Documentation

__STATIC_INLINE void LL_APB3_GRP1_ForceReset ( uint32_t Periphs )

Force APB3 peripherals reset.

Reference Manual to LL API cross reference:
APB3RSTR RFRST LL_APB3_GRP1_ForceReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB3_GRP1_PERIPH_RF
Return values:
None

Definition at line 1375 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_APB3_GRP1_ReleaseReset ( uint32_t Periphs )

Release APB3 peripherals reset.

Reference Manual to LL API cross reference:
APB3RSTR RFRST LL_APB3_GRP1_ReleaseReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB3_GRP1_PERIPH_RF
Return values:
None

Definition at line 1387 of file stm32wbxx_ll_bus.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: C2 AHB1

Functions
C2 AHB1
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_C2_AHB1_GRP1_EnableClock (uint32_t Periphs)
Enable C2AHB1 peripherals clock.
__STATIC_INLINE uint32_t | LL_C2_AHB1_GRP1_IsEnabledClock (uint32_t Periphs)
Check if C2AHB1 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_C2_AHB1_GRP1_DisableClock (uint32_t Periphs)
Disable C2AHB1 peripherals clock.
__STATIC_INLINE void | LL_C2_AHB1_GRP1_EnableClockSleep (uint32_t Periphs)
Enable C2AHB1 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_C2_AHB1_GRP1_DisableClockSleep (uint32_t Periphs)
Disable C2AHB1 peripherals clock during Low Power (Sleep) mode.

Function Documentation

__STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClock ( uint32_t Periphs )

Disable C2AHB1 peripherals clock.

Reference Manual to LL API cross reference:
C2AHB1ENR DMA1EN LL_C2_AHB1_GRP1_DisableClock
C2AHB1ENR DMA2EN LL_C2_AHB1_GRP1_DisableClock
C2AHB1ENR DMAMUX1EN LL_C2_AHB1_GRP1_DisableClock
C2AHB1ENR SRAM1EN LL_C2_AHB1_GRP1_DisableClock
C2AHB1ENR CRCEN LL_C2_AHB1_GRP1_DisableClock
C2AHB1ENR TSCEN LL_C2_AHB1_GRP1_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_AHB1_GRP1_PERIPH_DMA1
  • LL_C2_AHB1_GRP1_PERIPH_DMA2
  • LL_C2_AHB1_GRP1_PERIPH_DMAMUX1
  • LL_C2_AHB1_GRP1_PERIPH_SRAM1
  • LL_C2_AHB1_GRP1_PERIPH_CRC
  • LL_C2_AHB1_GRP1_PERIPH_TSC
Return values:
None

Definition at line 1467 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClockSleep ( uint32_t Periphs )

Disable C2AHB1 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
C2AHB1SMENR DMA1SMEN LL_C2_AHB1_GRP1_DisableClockSleep
C2AHB1SMENR DMA2SMEN LL_C2_AHB1_GRP1_DisableClockSleep
C2AHB1SMENR DMAMUX1SMEN LL_C2_AHB1_GRP1_DisableClockSleep
C2AHB1ENR SRAM1SMEN LL_C2_AHB1_GRP1_DisableClockSleep
C2AHB1SMENR CRCSMEN LL_C2_AHB1_GRP1_DisableClockSleep
C2AHB1SMENR TSCSMEN LL_C2_AHB1_GRP1_DisableClockSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_AHB1_GRP1_PERIPH_DMA1
  • LL_C2_AHB1_GRP1_PERIPH_DMA2
  • LL_C2_AHB1_GRP1_PERIPH_DMAMUX1
  • LL_C2_AHB1_GRP1_PERIPH_SRAM1
  • LL_C2_AHB1_GRP1_PERIPH_CRC
  • LL_C2_AHB1_GRP1_PERIPH_TSC
Return values:
None

Definition at line 1517 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClock ( uint32_t Periphs )

Enable C2AHB1 peripherals clock.

Reference Manual to LL API cross reference:
C2AHB1ENR DMA1EN LL_C2_AHB1_GRP1_EnableClock
C2AHB1ENR DMA2EN LL_C2_AHB1_GRP1_EnableClock
C2AHB1ENR DMAMUX1EN LL_C2_AHB1_GRP1_EnableClock
C2AHB1ENR SRAM1EN LL_C2_AHB1_GRP1_EnableClock
C2AHB1ENR CRCEN LL_C2_AHB1_GRP1_EnableClock
C2AHB1ENR TSCEN LL_C2_AHB1_GRP1_EnableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_AHB1_GRP1_PERIPH_DMA1
  • LL_C2_AHB1_GRP1_PERIPH_DMA2
  • LL_C2_AHB1_GRP1_PERIPH_DMAMUX1
  • LL_C2_AHB1_GRP1_PERIPH_SRAM1
  • LL_C2_AHB1_GRP1_PERIPH_CRC
  • LL_C2_AHB1_GRP1_PERIPH_TSC
Return values:
None

Definition at line 1417 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClockSleep ( uint32_t Periphs )

Enable C2AHB1 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
C2AHB1SMENR DMA1SMEN LL_C2_AHB1_GRP1_EnableClockSleep
C2AHB1SMENR DMA2SMEN LL_C2_AHB1_GRP1_EnableClockSleep
C2AHB1SMENR DMAMUX1SMEN LL_C2_AHB1_GRP1_EnableClockSleep
C2AHB1ENR SRAM1SMEN LL_C2_AHB1_GRP1_EnableClockSleep
C2AHB1SMENR CRCSMEN LL_C2_AHB1_GRP1_EnableClockSleep
C2AHB1SMENR TSCSMEN LL_C2_AHB1_GRP1_EnableClockSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_AHB1_GRP1_PERIPH_DMA1
  • LL_C2_AHB1_GRP1_PERIPH_DMA2
  • LL_C2_AHB1_GRP1_PERIPH_DMAMUX1
  • LL_C2_AHB1_GRP1_PERIPH_SRAM1
  • LL_C2_AHB1_GRP1_PERIPH_CRC
  • LL_C2_AHB1_GRP1_PERIPH_TSC
Return values:
None

Definition at line 1490 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE uint32_t LL_C2_AHB1_GRP1_IsEnabledClock ( uint32_t Periphs )

Check if C2AHB1 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
C2AHB1ENR DMA1EN LL_C2_AHB1_GRP1_IsEnabledClock
C2AHB1ENR DMA2EN LL_C2_AHB1_GRP1_IsEnabledClock
C2AHB1ENR DMAMUX1EN LL_C2_AHB1_GRP1_IsEnabledClock
C2AHB1ENR SRAM1EN LL_C2_AHB1_GRP1_IsEnabledClock
C2AHB1ENR CRCEN LL_C2_AHB1_GRP1_IsEnabledClock
C2AHB1ENR TSCEN LL_C2_AHB1_GRP1_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_AHB1_GRP1_PERIPH_DMA1
  • LL_C2_AHB1_GRP1_PERIPH_DMA2
  • LL_C2_AHB1_GRP1_PERIPH_DMAMUX1
  • LL_C2_AHB1_GRP1_PERIPH_SRAM1
  • LL_C2_AHB1_GRP1_PERIPH_CRC
  • LL_C2_AHB1_GRP1_PERIPH_TSC
Return values:
uint32_t

Definition at line 1444 of file stm32wbxx_ll_bus.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: C2 AHB2

Functions
C2 AHB2
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_C2_AHB2_GRP1_EnableClock (uint32_t Periphs)
Enable C2AHB2 peripherals clock.
__STATIC_INLINE uint32_t | LL_C2_AHB2_GRP1_IsEnabledClock (uint32_t Periphs)
Check if C2AHB2 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_C2_AHB2_GRP1_DisableClock (uint32_t Periphs)
Disable C2AHB2 peripherals clock.
__STATIC_INLINE void | LL_C2_AHB2_GRP1_EnableClockSleep (uint32_t Periphs)
Enable C2AHB2 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_C2_AHB2_GRP1_DisableClockSleep (uint32_t Periphs)
Disable C2AHB2 peripherals clock during Low Power (Sleep) mode.

Function Documentation

__STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClock ( uint32_t Periphs )

Disable C2AHB2 peripherals clock.

Reference Manual to LL API cross reference:
C2AHB2ENR GPIOAEN LL_C2_AHB2_GRP1_DisableClock
C2AHB2ENR GPIOBEN LL_C2_AHB2_GRP1_DisableClock
C2AHB2ENR GPIOCEN LL_C2_AHB2_GRP1_DisableClock
C2AHB2ENR GPIODEN LL_C2_AHB2_GRP1_DisableClock
C2AHB2ENR GPIOEEN LL_C2_AHB2_GRP1_DisableClock
C2AHB2ENR GPIOHEN LL_C2_AHB2_GRP1_DisableClock
C2AHB2ENR ADCEN LL_C2_AHB2_GRP1_DisableClock
C2AHB2ENR AES1EN LL_C2_AHB2_GRP1_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_AHB2_GRP1_PERIPH_GPIOA
  • LL_C2_AHB2_GRP1_PERIPH_GPIOB
  • LL_C2_AHB2_GRP1_PERIPH_GPIOC
  • LL_C2_AHB2_GRP1_PERIPH_GPIOD
  • LL_C2_AHB2_GRP1_PERIPH_GPIOE
  • LL_C2_AHB2_GRP1_PERIPH_GPIOH
  • LL_C2_AHB2_GRP1_PERIPH_ADC
  • LL_C2_AHB2_GRP1_PERIPH_AES1
Return values:
None

Definition at line 1607 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClockSleep ( uint32_t Periphs )

Disable C2AHB2 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
C2AHB2SMENR GPIOASMEN LL_C2_AHB2_GRP1_DisableClockSleep
C2AHB2SMENR GPIOBSMEN LL_C2_AHB2_GRP1_DisableClockSleep
C2AHB2SMENR GPIOCSMEN LL_C2_AHB2_GRP1_DisableClockSleep
C2AHB2SMENR GPIODSMEN LL_C2_AHB2_GRP1_DisableClockSleep
C2AHB2SMENR GPIOESMEN LL_C2_AHB2_GRP1_DisableClockSleep
C2AHB2SMENR GPIOHSMEN LL_C2_AHB2_GRP1_DisableClockSleep
C2AHB2SMENR ADCSMEN LL_C2_AHB2_GRP1_DisableClockSleep
C2AHB2SMENR AES1SMEN LL_C2_AHB2_GRP1_DisableClockSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_AHB2_GRP1_PERIPH_GPIOA
  • LL_C2_AHB2_GRP1_PERIPH_GPIOB
  • LL_C2_AHB2_GRP1_PERIPH_GPIOC
  • LL_C2_AHB2_GRP1_PERIPH_GPIOD
  • LL_C2_AHB2_GRP1_PERIPH_GPIOE
  • LL_C2_AHB2_GRP1_PERIPH_GPIOH
  • LL_C2_AHB2_GRP1_PERIPH_ADC
  • LL_C2_AHB2_GRP1_PERIPH_AES1
Return values:
None

Definition at line 1663 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClock ( uint32_t Periphs )

Enable C2AHB2 peripherals clock.

Reference Manual to LL API cross reference:
C2AHB2ENR GPIOAEN LL_C2_AHB2_GRP1_EnableClock
C2AHB2ENR GPIOBEN LL_C2_AHB2_GRP1_EnableClock
C2AHB2ENR GPIOCEN LL_C2_AHB2_GRP1_EnableClock
C2AHB2ENR GPIODEN LL_C2_AHB2_GRP1_EnableClock
C2AHB2ENR GPIOEEN LL_C2_AHB2_GRP1_EnableClock
C2AHB2ENR GPIOHEN LL_C2_AHB2_GRP1_EnableClock
C2AHB2ENR ADCEN LL_C2_AHB2_GRP1_EnableClock
C2AHB2ENR AES1EN LL_C2_AHB2_GRP1_EnableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_AHB2_GRP1_PERIPH_GPIOA
  • LL_C2_AHB2_GRP1_PERIPH_GPIOB
  • LL_C2_AHB2_GRP1_PERIPH_GPIOC
  • LL_C2_AHB2_GRP1_PERIPH_GPIOD
  • LL_C2_AHB2_GRP1_PERIPH_GPIOE
  • LL_C2_AHB2_GRP1_PERIPH_GPIOH
  • LL_C2_AHB2_GRP1_PERIPH_ADC
  • LL_C2_AHB2_GRP1_PERIPH_AES1
Return values:
None

Definition at line 1551 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClockSleep ( uint32_t Periphs )

Enable C2AHB2 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
C2AHB2SMENR GPIOASMEN LL_C2_AHB2_GRP1_EnableClockSleep
C2AHB2SMENR GPIOBSMEN LL_C2_AHB2_GRP1_EnableClockSleep
C2AHB2SMENR GPIOCSMEN LL_C2_AHB2_GRP1_EnableClockSleep
C2AHB2SMENR GPIODSMEN LL_C2_AHB2_GRP1_EnableClockSleep
C2AHB2SMENR GPIOESMEN LL_C2_AHB2_GRP1_EnableClockSleep
C2AHB2SMENR GPIOHSMEN LL_C2_AHB2_GRP1_EnableClockSleep
C2AHB2SMENR ADCSMEN LL_C2_AHB2_GRP1_EnableClockSleep
C2AHB2SMENR AES1SMEN LL_C2_AHB2_GRP1_EnableClockSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_AHB2_GRP1_PERIPH_GPIOA
  • LL_C2_AHB2_GRP1_PERIPH_GPIOB
  • LL_C2_AHB2_GRP1_PERIPH_GPIOC
  • LL_C2_AHB2_GRP1_PERIPH_GPIOD
  • LL_C2_AHB2_GRP1_PERIPH_GPIOE
  • LL_C2_AHB2_GRP1_PERIPH_GPIOH
  • LL_C2_AHB2_GRP1_PERIPH_ADC
  • LL_C2_AHB2_GRP1_PERIPH_AES1
Return values:
None

Definition at line 1633 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE uint32_t LL_C2_AHB2_GRP1_IsEnabledClock ( uint32_t Periphs )

Check if C2AHB2 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
C2AHB2ENR GPIOAEN LL_C2_AHB2_GRP1_IsEnabledClock
C2AHB2ENR GPIOBEN LL_C2_AHB2_GRP1_IsEnabledClock
C2AHB2ENR GPIOCEN LL_C2_AHB2_GRP1_IsEnabledClock
C2AHB2ENR GPIODEN LL_C2_AHB2_GRP1_IsEnabledClock
C2AHB2ENR GPIOEEN LL_C2_AHB2_GRP1_IsEnabledClock
C2AHB2ENR GPIOHEN LL_C2_AHB2_GRP1_IsEnabledClock
C2AHB2ENR ADCEN LL_C2_AHB2_GRP1_IsEnabledClock
C2AHB2ENR AES1EN LL_C2_AHB2_GRP1_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_AHB2_GRP1_PERIPH_GPIOA
  • LL_C2_AHB2_GRP1_PERIPH_GPIOB
  • LL_C2_AHB2_GRP1_PERIPH_GPIOC
  • LL_C2_AHB2_GRP1_PERIPH_GPIOD
  • LL_C2_AHB2_GRP1_PERIPH_GPIOE
  • LL_C2_AHB2_GRP1_PERIPH_GPIOH
  • LL_C2_AHB2_GRP1_PERIPH_ADC
  • LL_C2_AHB2_GRP1_PERIPH_AES1
Return values:
uint32_t

Definition at line 1581 of file stm32wbxx_ll_bus.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: C2 AHB3

Functions
C2 AHB3
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_C2_AHB3_GRP1_EnableClock (uint32_t Periphs)
Enable C2AHB3 peripherals clock.
__STATIC_INLINE uint32_t | LL_C2_AHB3_GRP1_IsEnabledClock (uint32_t Periphs)
Check if C2AHB3 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_C2_AHB3_GRP1_DisableClock (uint32_t Periphs)
Disable C2AHB3 peripherals clock.
__STATIC_INLINE void | LL_C2_AHB3_GRP1_EnableClockSleep (uint32_t Periphs)
Enable C2AHB3 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_C2_AHB3_GRP1_DisableClockSleep (uint32_t Periphs)
Disable C2AHB3 peripherals clock during Low Power (Sleep) mode.

Function Documentation

__STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClock ( uint32_t Periphs )

Disable C2AHB3 peripherals clock.

Reference Manual to LL API cross reference:
C2AHB3ENR PKAEN LL_C2_AHB3_GRP1_DisableClock
C2AHB3ENR AES2EN LL_C2_AHB3_GRP1_DisableClock
C2AHB3ENR RNGEN LL_C2_AHB3_GRP1_DisableClock
C2AHB3ENR HSEMEN LL_C2_AHB3_GRP1_DisableClock
C2AHB3ENR IPCCEN LL_C2_AHB3_GRP1_DisableClock
C2AHB3ENR FLASHEN LL_C2_AHB3_GRP1_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_AHB3_GRP1_PERIPH_PKA
  • LL_C2_AHB3_GRP1_PERIPH_AES2
  • LL_C2_AHB3_GRP1_PERIPH_RNG
  • LL_C2_AHB3_GRP1_PERIPH_HSEM
  • LL_C2_AHB3_GRP1_PERIPH_IPCC
  • LL_C2_AHB3_GRP1_PERIPH_FLASH
Return values:
None

Definition at line 1741 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClockSleep ( uint32_t Periphs )

Disable C2AHB3 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
C2AHB3SMENR PKASMEN LL_C2_AHB3_GRP1_DisableClockSleep
C2AHB3SMENR AES2SMEN LL_C2_AHB3_GRP1_DisableClockSleep
C2AHB3SMENR RNGSMEN LL_C2_AHB3_GRP1_DisableClockSleep
C2AHB3SMENR SRAM2SMEN LL_C2_AHB3_GRP1_DisableClockSleep
C2AHB3SMENR FLASHSMEN LL_C2_AHB3_GRP1_DisableClockSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_AHB3_GRP1_PERIPH_PKA
  • LL_C2_AHB3_GRP1_PERIPH_AES2
  • LL_C2_AHB3_GRP1_PERIPH_RNG
  • LL_C2_AHB3_GRP1_PERIPH_SRAM2
  • LL_C2_AHB3_GRP1_PERIPH_FLASH
Return values:
None

Definition at line 1785 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClock ( uint32_t Periphs )

Enable C2AHB3 peripherals clock.

Reference Manual to LL API cross reference:
C2AHB3ENR PKAEN LL_C2_AHB3_GRP1_EnableClock
C2AHB3ENR AES2EN LL_C2_AHB3_GRP1_EnableClock
C2AHB3ENR RNGEN LL_C2_AHB3_GRP1_EnableClock
C2AHB3ENR HSEMEN LL_C2_AHB3_GRP1_EnableClock
C2AHB3ENR IPCCEN LL_C2_AHB3_GRP1_EnableClock
C2AHB3ENR FLASHEN LL_C2_AHB3_GRP1_EnableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_AHB3_GRP1_PERIPH_PKA
  • LL_C2_AHB3_GRP1_PERIPH_AES2
  • LL_C2_AHB3_GRP1_PERIPH_RNG
  • LL_C2_AHB3_GRP1_PERIPH_HSEM
  • LL_C2_AHB3_GRP1_PERIPH_IPCC
  • LL_C2_AHB3_GRP1_PERIPH_FLASH
Return values:
None

Definition at line 1693 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClockSleep ( uint32_t Periphs )

Enable C2AHB3 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
C2AHB3SMENR PKASMEN LL_C2_AHB3_GRP1_EnableClockSleep
C2AHB3SMENR AES2SMEN LL_C2_AHB3_GRP1_EnableClockSleep
C2AHB3SMENR RNGSMEN LL_C2_AHB3_GRP1_EnableClockSleep
C2AHB3SMENR SRAM2SMEN LL_C2_AHB3_GRP1_EnableClockSleep
C2AHB3SMENR FLASHSMEN LL_C2_AHB3_GRP1_EnableClockSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_AHB3_GRP1_PERIPH_PKA
  • LL_C2_AHB3_GRP1_PERIPH_AES2
  • LL_C2_AHB3_GRP1_PERIPH_RNG
  • LL_C2_AHB3_GRP1_PERIPH_SRAM2
  • LL_C2_AHB3_GRP1_PERIPH_FLASH
Return values:
None

Definition at line 1761 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE uint32_t LL_C2_AHB3_GRP1_IsEnabledClock ( uint32_t Periphs )

Check if C2AHB3 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
C2AHB3ENR PKAEN LL_C2_AHB3_GRP1_IsEnabledClock
C2AHB3ENR AES2EN LL_C2_AHB3_GRP1_IsEnabledClock
C2AHB3ENR RNGEN LL_C2_AHB3_GRP1_IsEnabledClock
C2AHB3ENR HSEMEN LL_C2_AHB3_GRP1_IsEnabledClock
C2AHB3ENR IPCCEN LL_C2_AHB3_GRP1_IsEnabledClock
C2AHB3ENR FLASHEN LL_C2_AHB3_GRP1_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_AHB3_GRP1_PERIPH_PKA
  • LL_C2_AHB3_GRP1_PERIPH_AES2
  • LL_C2_AHB3_GRP1_PERIPH_RNG
  • LL_C2_AHB3_GRP1_PERIPH_HSEM
  • LL_C2_AHB3_GRP1_PERIPH_IPCC
  • LL_C2_AHB3_GRP1_PERIPH_FLASH
Return values:
uint32_t

Definition at line 1719 of file stm32wbxx_ll_bus.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: C2 APB1

Functions
C2 APB1
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_C2_APB1_GRP1_EnableClock (uint32_t Periphs)
Enable C2APB1 peripherals clock.
__STATIC_INLINE void | LL_C2_APB1_GRP2_EnableClock (uint32_t Periphs)
Enable C2APB1 peripherals clock.
__STATIC_INLINE uint32_t | LL_C2_APB1_GRP1_IsEnabledClock (uint32_t Periphs)
Check if C2APB1 peripheral clock is enabled or not.
__STATIC_INLINE uint32_t | LL_C2_APB1_GRP2_IsEnabledClock (uint32_t Periphs)
Check if C2APB1 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_C2_APB1_GRP1_DisableClock (uint32_t Periphs)
Disable C2APB1 peripherals clock.
__STATIC_INLINE void | LL_C2_APB1_GRP2_DisableClock (uint32_t Periphs)
Disable C2APB1 peripherals clock.
__STATIC_INLINE void | LL_C2_APB1_GRP1_EnableClockSleep (uint32_t Periphs)
Enable C2APB1 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_C2_APB1_GRP2_EnableClockSleep (uint32_t Periphs)
Enable C2APB1 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_C2_APB1_GRP1_DisableClockSleep (uint32_t Periphs)
Disable C2APB1 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_C2_APB1_GRP2_DisableClockSleep (uint32_t Periphs)
Disable C2APB1 peripherals clock during Low Power (Sleep) mode.

Function Documentation

__STATIC_INLINE void LL_C2_APB1_GRP1_DisableClock ( uint32_t Periphs )

Disable C2APB1 peripherals clock.

Reference Manual to LL API cross reference:
C2APB1ENR1 TIM2EN LL_C2_APB1_GRP1_DisableClock
C2APB1ENR1 LCDEN LL_C2_APB1_GRP1_DisableClock
C2APB1ENR1 RTCAPBEN LL_C2_APB1_GRP1_DisableClock
C2APB1ENR1 SPI2EN LL_C2_APB1_GRP1_DisableClock
C2APB1ENR1 I2C1EN LL_C2_APB1_GRP1_DisableClock
C2APB1ENR1 I2C3EN LL_C2_APB1_GRP1_DisableClock
C2APB1ENR1 CRSEN LL_C2_APB1_GRP1_DisableClock
C2APB1ENR1 USBEN LL_C2_APB1_GRP1_DisableClock
C2APB1ENR1 LPTIM1EN LL_C2_APB1_GRP1_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_APB1_GRP1_PERIPH_TIM2
  • LL_C2_APB1_GRP1_PERIPH_LCD
  • LL_C2_APB1_GRP1_PERIPH_RTCAPB
  • LL_C2_APB1_GRP1_PERIPH_SPI2
  • LL_C2_APB1_GRP1_PERIPH_I2C1
  • LL_C2_APB1_GRP1_PERIPH_I2C3
  • LL_C2_APB1_GRP1_PERIPH_CRS
  • LL_C2_APB1_GRP1_PERIPH_USB
  • LL_C2_APB1_GRP1_PERIPH_LPTIM1
Return values:
None

Definition at line 1913 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_C2_APB1_GRP1_DisableClockSleep ( uint32_t Periphs )

Disable C2APB1 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
C2APB1SMENR1 TIM2SMEN LL_C2_APB1_GRP1_DisableClockSleep
C2APB1SMENR1 LCDSMEN LL_C2_APB1_GRP1_DisableClockSleep
C2APB1SMENR1 RTCAPBSMEN LL_C2_APB1_GRP1_DisableClockSleep
C2APB1SMENR1 SPI2SMEN LL_C2_APB1_GRP1_DisableClockSleep
C2APB1SMENR1 I2C1SMEN LL_C2_APB1_GRP1_DisableClockSleep
C2APB1SMENR1 I2C3SMEN LL_C2_APB1_GRP1_DisableClockSleep
C2APB1SMENR1 CRSSMEN LL_C2_APB1_GRP1_DisableClockSleep
C2APB1SMENR1 USBSMEN LL_C2_APB1_GRP1_DisableClockSleep
C2APB1SMENR1 LPTIM1SMEN LL_C2_APB1_GRP1_DisableClockSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_APB1_GRP1_PERIPH_TIM2
  • LL_C2_APB1_GRP1_PERIPH_LCD
  • LL_C2_APB1_GRP1_PERIPH_RTCAPB
  • LL_C2_APB1_GRP1_PERIPH_SPI2
  • LL_C2_APB1_GRP1_PERIPH_I2C1
  • LL_C2_APB1_GRP1_PERIPH_I2C3
  • LL_C2_APB1_GRP1_PERIPH_CRS
  • LL_C2_APB1_GRP1_PERIPH_USB
  • LL_C2_APB1_GRP1_PERIPH_LPTIM1
Return values:
None

Definition at line 2005 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_C2_APB1_GRP1_EnableClock ( uint32_t Periphs )

Enable C2APB1 peripherals clock.

Reference Manual to LL API cross reference:
C2APB1ENR1 TIM2EN LL_C2_APB1_GRP1_EnableClock
C2APB1ENR1 LCDEN LL_C2_APB1_GRP1_EnableClock
C2APB1ENR1 RTCAPBEN LL_C2_APB1_GRP1_EnableClock
C2APB1ENR1 SPI2EN LL_C2_APB1_GRP1_EnableClock
C2APB1ENR1 I2C1EN LL_C2_APB1_GRP1_EnableClock
C2APB1ENR1 I2C3EN LL_C2_APB1_GRP1_EnableClock
C2APB1ENR1 CRSEN LL_C2_APB1_GRP1_EnableClock
C2APB1ENR1 USBEN LL_C2_APB1_GRP1_EnableClock
C2APB1ENR1 LPTIM1EN LL_C2_APB1_GRP1_EnableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_APB1_GRP1_PERIPH_TIM2
  • LL_C2_APB1_GRP1_PERIPH_LCD
  • LL_C2_APB1_GRP1_PERIPH_RTCAPB
  • LL_C2_APB1_GRP1_PERIPH_SPI2
  • LL_C2_APB1_GRP1_PERIPH_I2C1
  • LL_C2_APB1_GRP1_PERIPH_I2C3
  • LL_C2_APB1_GRP1_PERIPH_CRS
  • LL_C2_APB1_GRP1_PERIPH_USB
  • LL_C2_APB1_GRP1_PERIPH_LPTIM1
Return values:
None

Definition at line 1821 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_C2_APB1_GRP1_EnableClockSleep ( uint32_t Periphs )

Enable C2APB1 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
C2APB1SMENR1 TIM2SMEN LL_C2_APB1_GRP1_EnableClockSleep
C2APB1SMENR1 LCDSMEN LL_C2_APB1_GRP1_EnableClockSleep
C2APB1SMENR1 RTCAPBSMEN LL_C2_APB1_GRP1_EnableClockSleep
C2APB1SMENR1 SPI2SMEN LL_C2_APB1_GRP1_EnableClockSleep
C2APB1SMENR1 I2C1SMEN LL_C2_APB1_GRP1_EnableClockSleep
C2APB1SMENR1 I2C3SMEN LL_C2_APB1_GRP1_EnableClockSleep
C2APB1SMENR1 CRSSMEN LL_C2_APB1_GRP1_EnableClockSleep
C2APB1SMENR1 USBSMEN LL_C2_APB1_GRP1_EnableClockSleep
C2APB1SMENR1 LPTIM1SMEN LL_C2_APB1_GRP1_EnableClockSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_APB1_GRP1_PERIPH_TIM2
  • LL_C2_APB1_GRP1_PERIPH_LCD
  • LL_C2_APB1_GRP1_PERIPH_RTCAPB
  • LL_C2_APB1_GRP1_PERIPH_SPI2
  • LL_C2_APB1_GRP1_PERIPH_I2C1
  • LL_C2_APB1_GRP1_PERIPH_I2C3
  • LL_C2_APB1_GRP1_PERIPH_CRS
  • LL_C2_APB1_GRP1_PERIPH_USB
  • LL_C2_APB1_GRP1_PERIPH_LPTIM1
Return values:
None

Definition at line 1955 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE uint32_t LL_C2_APB1_GRP1_IsEnabledClock ( uint32_t Periphs )

Check if C2APB1 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
C2APB1ENR1 TIM2EN LL_C2_APB1_GRP1_IsEnabledClock
C2APB1ENR1 LCDEN LL_C2_APB1_GRP1_IsEnabledClock
C2APB1ENR1 RTCAPBEN LL_C2_APB1_GRP1_IsEnabledClock
C2APB1ENR1 SPI2EN LL_C2_APB1_GRP1_IsEnabledClock
C2APB1ENR1 I2C1EN LL_C2_APB1_GRP1_IsEnabledClock
C2APB1ENR1 I2C3EN LL_C2_APB1_GRP1_IsEnabledClock
C2APB1ENR1 CRSEN LL_C2_APB1_GRP1_IsEnabledClock
C2APB1ENR1 USBEN LL_C2_APB1_GRP1_IsEnabledClock
C2APB1ENR1 LPTIM1EN LL_C2_APB1_GRP1_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_APB1_GRP1_PERIPH_TIM2
  • LL_C2_APB1_GRP1_PERIPH_LCD
  • LL_C2_APB1_GRP1_PERIPH_RTCAPB
  • LL_C2_APB1_GRP1_PERIPH_SPI2
  • LL_C2_APB1_GRP1_PERIPH_I2C1
  • LL_C2_APB1_GRP1_PERIPH_I2C3
  • LL_C2_APB1_GRP1_PERIPH_CRS
  • LL_C2_APB1_GRP1_PERIPH_USB
  • LL_C2_APB1_GRP1_PERIPH_LPTIM1
Return values:
uint32_t

Definition at line 1871 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_C2_APB1_GRP2_DisableClock ( uint32_t Periphs )

Disable C2APB1 peripherals clock.

Reference Manual to LL API cross reference:
C2APB1ENR2 LPUART1EN LL_C2_APB1_GRP2_DisableClock
C2APB1ENR2 LPTIM2EN LL_C2_APB1_GRP2_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_APB1_GRP2_PERIPH_LPUART1
  • LL_C2_APB1_GRP2_PERIPH_LPTIM2
Return values:
None

Definition at line 1927 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_C2_APB1_GRP2_DisableClockSleep ( uint32_t Periphs )

Disable C2APB1 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
C2APB1SMENR2 LPUART1SMEN LL_C2_APB1_GRP2_DisableClockSleep
C2APB1SMENR2 LPTIM2SMEN LL_C2_APB1_GRP2_DisableClockSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_APB1_GRP2_PERIPH_LPUART1
  • LL_C2_APB1_GRP2_PERIPH_LPTIM2
Return values:
None

Definition at line 2019 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_C2_APB1_GRP2_EnableClock ( uint32_t Periphs )

Enable C2APB1 peripherals clock.

Reference Manual to LL API cross reference:
C2APB1ENR2 LPUART1EN LL_C2_APB1_GRP2_EnableClock
C2APB1ENR2 LPTIM2EN LL_C2_APB1_GRP2_EnableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_APB1_GRP2_PERIPH_LPUART1
  • LL_C2_APB1_GRP2_PERIPH_LPTIM2
Return values:
None

Definition at line 1839 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_C2_APB1_GRP2_EnableClockSleep ( uint32_t Periphs )

Enable C2APB1 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
C2APB1SMENR2 LPUART1SMEN LL_C2_APB1_GRP2_EnableClockSleep
C2APB1SMENR2 LPTIM2SMEN LL_C2_APB1_GRP2_EnableClockSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_APB1_GRP2_PERIPH_LPUART1
  • LL_C2_APB1_GRP2_PERIPH_LPTIM2
Return values:
None

Definition at line 1973 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE uint32_t LL_C2_APB1_GRP2_IsEnabledClock ( uint32_t Periphs )

Check if C2APB1 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
C2APB1ENR2 LPUART1EN LL_C2_APB1_GRP2_IsEnabledClock
C2APB1ENR2 LPTIM2EN LL_C2_APB1_GRP2_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_APB1_GRP2_PERIPH_LPUART1
  • LL_C2_APB1_GRP2_PERIPH_LPTIM2
Return values:
uint32_t

Definition at line 1885 of file stm32wbxx_ll_bus.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: C2 APB2

Functions
C2 APB2
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_C2_APB2_GRP1_EnableClock (uint32_t Periphs)
Enable C2APB2 peripherals clock.
__STATIC_INLINE uint32_t | LL_C2_APB2_GRP1_IsEnabledClock (uint32_t Periphs)
Check if C2APB2 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_C2_APB2_GRP1_DisableClock (uint32_t Periphs)
Disable C2APB2 peripherals clock.
__STATIC_INLINE void | LL_C2_APB2_GRP1_EnableClockSleep (uint32_t Periphs)
Enable C2APB2 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_C2_APB2_GRP1_DisableClockSleep (uint32_t Periphs)
Disable C2APB2 peripherals clock during Low Power (Sleep) mode.

Function Documentation

__STATIC_INLINE void LL_C2_APB2_GRP1_DisableClock ( uint32_t Periphs )

Disable C2APB2 peripherals clock.

Reference Manual to LL API cross reference:
C2APB2ENR TIM1EN LL_C2_APB2_GRP1_DisableClock
C2APB2ENR SPI1EN LL_C2_APB2_GRP1_DisableClock
C2APB2ENR USART1EN LL_C2_APB2_GRP1_DisableClock
C2APB2ENR TIM16EN LL_C2_APB2_GRP1_DisableClock
C2APB2ENR TIM17EN LL_C2_APB2_GRP1_DisableClock
C2APB2ENR SAI1EN LL_C2_APB2_GRP1_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_APB2_GRP1_PERIPH_TIM1
  • LL_C2_APB2_GRP1_PERIPH_SPI1
  • LL_C2_APB2_GRP1_PERIPH_USART1
  • LL_C2_APB2_GRP1_PERIPH_TIM16
  • LL_C2_APB2_GRP1_PERIPH_TIM17
  • LL_C2_APB2_GRP1_PERIPH_SAI1
Return values:
None

Definition at line 2097 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_C2_APB2_GRP1_DisableClockSleep ( uint32_t Periphs )

Disable C2APB2 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
C2APB2SMENR TIM1SMEN LL_C2_APB2_GRP1_DisableClockSleep
C2APB2SMENR SPI1SMEN LL_C2_APB2_GRP1_DisableClockSleep
C2APB2SMENR USART1SMEN LL_C2_APB2_GRP1_DisableClockSleep
C2APB2SMENR TIM16SMEN LL_C2_APB2_GRP1_DisableClockSleep
C2APB2SMENR TIM17SMEN LL_C2_APB2_GRP1_DisableClockSleep
C2APB2SMENR SAI1SMEN LL_C2_APB2_GRP1_DisableClockSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_APB2_GRP1_PERIPH_TIM1
  • LL_C2_APB2_GRP1_PERIPH_SPI1
  • LL_C2_APB2_GRP1_PERIPH_USART1
  • LL_C2_APB2_GRP1_PERIPH_TIM16
  • LL_C2_APB2_GRP1_PERIPH_TIM17
  • LL_C2_APB2_GRP1_PERIPH_SAI1
Return values:
None

Definition at line 2145 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_C2_APB2_GRP1_EnableClock ( uint32_t Periphs )

Enable C2APB2 peripherals clock.

Reference Manual to LL API cross reference:
C2APB2ENR TIM1EN LL_C2_APB2_GRP1_EnableClock
C2APB2ENR SPI1EN LL_C2_APB2_GRP1_EnableClock
C2APB2ENR USART1EN LL_C2_APB2_GRP1_EnableClock
C2APB2ENR TIM16EN LL_C2_APB2_GRP1_EnableClock
C2APB2ENR TIM17EN LL_C2_APB2_GRP1_EnableClock
C2APB2ENR SAI1EN LL_C2_APB2_GRP1_EnableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_APB2_GRP1_PERIPH_TIM1
  • LL_C2_APB2_GRP1_PERIPH_SPI1
  • LL_C2_APB2_GRP1_PERIPH_USART1
  • LL_C2_APB2_GRP1_PERIPH_TIM16
  • LL_C2_APB2_GRP1_PERIPH_TIM17
  • LL_C2_APB2_GRP1_PERIPH_SAI1
Return values:
None

Definition at line 2049 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_C2_APB2_GRP1_EnableClockSleep ( uint32_t Periphs )

Enable C2APB2 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
C2APB2SMENR TIM1SMEN LL_C2_APB2_GRP1_EnableClockSleep
C2APB2SMENR SPI1SMEN LL_C2_APB2_GRP1_EnableClockSleep
C2APB2SMENR USART1SMEN LL_C2_APB2_GRP1_EnableClockSleep
C2APB2SMENR TIM16SMEN LL_C2_APB2_GRP1_EnableClockSleep
C2APB2SMENR TIM17SMEN LL_C2_APB2_GRP1_EnableClockSleep
C2APB2SMENR SAI1SMEN LL_C2_APB2_GRP1_EnableClockSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_APB2_GRP1_PERIPH_TIM1
  • LL_C2_APB2_GRP1_PERIPH_SPI1
  • LL_C2_APB2_GRP1_PERIPH_USART1
  • LL_C2_APB2_GRP1_PERIPH_TIM16
  • LL_C2_APB2_GRP1_PERIPH_TIM17
  • LL_C2_APB2_GRP1_PERIPH_SAI1
Return values:
None

Definition at line 2119 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE uint32_t LL_C2_APB2_GRP1_IsEnabledClock ( uint32_t Periphs )

Check if C2APB2 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
C2APB2ENR TIM1EN LL_C2_APB2_GRP1_IsEnabledClock
C2APB2ENR SPI1EN LL_C2_APB2_GRP1_IsEnabledClock
C2APB2ENR USART1EN LL_C2_APB2_GRP1_IsEnabledClock
C2APB2ENR TIM16EN LL_C2_APB2_GRP1_IsEnabledClock
C2APB2ENR TIM17EN LL_C2_APB2_GRP1_IsEnabledClock
C2APB2ENR SAI1EN LL_C2_APB2_GRP1_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_APB2_GRP1_PERIPH_TIM1
  • LL_C2_APB2_GRP1_PERIPH_SPI1
  • LL_C2_APB2_GRP1_PERIPH_USART1
  • LL_C2_APB2_GRP1_PERIPH_TIM16
  • LL_C2_APB2_GRP1_PERIPH_TIM17
  • LL_C2_APB2_GRP1_PERIPH_SAI1
Return values:
uint32_t

Definition at line 2075 of file stm32wbxx_ll_bus.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: C2 APB3

Functions
C2 APB3
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_C2_APB3_GRP1_EnableClock (uint32_t Periphs)
Enable C2APB3 peripherals clock.
__STATIC_INLINE uint32_t | LL_C2_APB3_GRP1_IsEnabledClock (uint32_t Periphs)
Check if C2APB3 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_C2_APB3_GRP1_DisableClock (uint32_t Periphs)
Disable C2APB3 peripherals clock.
__STATIC_INLINE void | LL_C2_APB3_GRP1_EnableClockSleep (uint32_t Periphs)
Enable C2APB3 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_C2_APB3_GRP1_DisableClockSleep (uint32_t Periphs)
Disable C2APB3 peripherals clock during Low Power (Sleep) mode.

Function Documentation

__STATIC_INLINE void LL_C2_APB3_GRP1_DisableClock ( uint32_t Periphs )

Disable C2APB3 peripherals clock.

Reference Manual to LL API cross reference:
C2APB3ENR BLEEN LL_C2_APB3_GRP1_DisableClock
C2APB3ENR 802EN LL_C2_APB3_GRP1_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_APB3_GRP1_PERIPH_BLE
  • LL_C2_APB3_GRP1_PERIPH_802
Return values:
None

Definition at line 2199 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_C2_APB3_GRP1_DisableClockSleep ( uint32_t Periphs )

Disable C2APB3 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
C2APB3SMENR BLESMEN LL_C2_APB3_GRP1_DisableClockSleep
C2APB3SMENR 802SMEN LL_C2_APB3_GRP1_DisableClockSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_APB3_GRP1_PERIPH_BLE
  • LL_C2_APB3_GRP1_PERIPH_802
Return values:
None

Definition at line 2231 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_C2_APB3_GRP1_EnableClock ( uint32_t Periphs )

Enable C2APB3 peripherals clock.

Reference Manual to LL API cross reference:
C2APB3ENR BLEEN LL_C2_APB3_GRP1_EnableClock
C2APB3ENR 802EN LL_C2_APB3_GRP1_EnableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_APB3_GRP1_PERIPH_BLE
  • LL_C2_APB3_GRP1_PERIPH_802
Return values:
None

Definition at line 2167 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE void LL_C2_APB3_GRP1_EnableClockSleep ( uint32_t Periphs )

Enable C2APB3 peripherals clock during Low Power (Sleep) mode.

Reference Manual to LL API cross reference:
C2APB3SMENR BLESMEN LL_C2_APB3_GRP1_EnableClockSleep
C2APB3SMENR 802SMEN LL_C2_APB3_GRP1_EnableClockSleep
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_APB3_GRP1_PERIPH_BLE
  • LL_C2_APB3_GRP1_PERIPH_802
Return values:
None

Definition at line 2213 of file stm32wbxx_ll_bus.h.

__STATIC_INLINE uint32_t LL_C2_APB3_GRP1_IsEnabledClock ( uint32_t Periphs )

Check if C2APB3 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
C2APB3ENR BLEEN LL_C2_APB3_GRP1_IsEnabledClock
C2APB3ENR 802EN LL_C2_APB3_GRP1_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_APB3_GRP1_PERIPH_BLE
  • LL_C2_APB3_GRP1_PERIPH_802
Return values:
uint32_t

Definition at line 2185 of file stm32wbxx_ll_bus.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: COMP

Modules
COMP
STM32WBxx_LL_Driver

Modules

COMP Private Constants
COMP Exported Init structure
COMP Exported Constants
COMP Exported Macros
COMP Exported Functions
COMP_LL_Private_Macros

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for COMP registers.

Register | Bit | Function
CSR | BLANKING | LL_COMP_GetOutputBlankingSource
 |  | LL_COMP_SetOutputBlankingSource
 | BRGEN | LL_COMP_ConfigInputs
 |  | LL_COMP_GetInputMinus
 |  | LL_COMP_SetInputMinus
 | EN | LL_COMP_Disable
 |  | LL_COMP_Enable
 |  | LL_COMP_IsEnabled
 | HYST | LL_COMP_GetInputHysteresis
 |  | LL_COMP_SetInputHysteresis
 | INMSEL | LL_COMP_ConfigInputs
 |  | LL_COMP_GetInputMinus
 |  | LL_COMP_SetInputMinus
 | INPSEL | LL_COMP_ConfigInputs
 |  | LL_COMP_GetInputPlus
 |  | LL_COMP_SetInputPlus
 | LOCK | LL_COMP_IsLocked
 |  | LL_COMP_Lock
 | POLARITY | LL_COMP_GetOutputPolarity
 |  | LL_COMP_SetOutputPolarity
 | PWRMODE | LL_COMP_GetPowerMode
 |  | LL_COMP_SetPowerMode
 | SCALEN | LL_COMP_ConfigInputs
 |  | LL_COMP_GetInputMinus
 |  | LL_COMP_SetInputMinus
 | VALUE | LL_COMP_ReadOutputLevel
 | WINMODE | LL_COMP_GetCommonWindowMode
 |  | LL_COMP_SetCommonWindowMode
Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: COMP Private Constants

Defines
COMP Private Constants
COMP

Defines

#define LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS (30UL) /* Value equivalent to POSITION_VAL(COMP_CSR_VALUE) */

Define Documentation

#define LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS (30UL) /* Value equivalent to POSITION_VAL(COMP_CSR_VALUE) */

Definition at line 49 of file stm32wbxx_ll_comp.h.

Referenced by LL_COMP_ReadOutputLevel().

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LL_COMP_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_COMP_InitTypeDef Struct Reference
COMP Exported Init structure

Structure definition of some features of COMP instance. More...

#include <stm32wbxx_ll_comp.h>

Data Fields

uint32_t | PowerMode
uint32_t | InputPlus
uint32_t | InputMinus
uint32_t | InputHysteresis
uint32_t | OutputPolarity
uint32_t | OutputBlankingSource

Detailed Description

Structure definition of some features of COMP instance.

Definition at line 65 of file stm32wbxx_ll_comp.h.

Field Documentation

uint32_t LL_COMP_InitTypeDef::InputHysteresis

Set comparator hysteresis mode of the input minus. This parameter can be a value of Comparator input - Hysteresis

This feature can be modified afterwards using unitary function LL_COMP_SetInputHysteresis().

Definition at line 82 of file stm32wbxx_ll_comp.h.

Referenced by LL_COMP_Init(), and LL_COMP_StructInit().

uint32_t LL_COMP_InitTypeDef::InputMinus

Set comparator input minus (inverting input). This parameter can be a value of Comparator inputs - Input minus (input inverting) selection

This feature can be modified afterwards using unitary function LL_COMP_SetInputMinus().

Definition at line 77 of file stm32wbxx_ll_comp.h.

Referenced by LL_COMP_Init(), and LL_COMP_StructInit().

uint32_t LL_COMP_InitTypeDef::InputPlus

Set comparator input plus (non-inverting input). This parameter can be a value of Comparator inputs - Input plus (input non-inverting) selection

This feature can be modified afterwards using unitary function LL_COMP_SetInputPlus().

Definition at line 72 of file stm32wbxx_ll_comp.h.

Referenced by LL_COMP_Init(), and LL_COMP_StructInit().

uint32_t LL_COMP_InitTypeDef::OutputBlankingSource

Set comparator blanking source. This parameter can be a value of Comparator output - Blanking source

This feature can be modified afterwards using unitary function LL_COMP_SetOutputBlankingSource().

Definition at line 92 of file stm32wbxx_ll_comp.h.

Referenced by LL_COMP_Init(), and LL_COMP_StructInit().

uint32_t LL_COMP_InitTypeDef::OutputPolarity

Set comparator output polarity. This parameter can be a value of Comparator output - Output polarity

This feature can be modified afterwards using unitary function LL_COMP_SetOutputPolarity().

Definition at line 87 of file stm32wbxx_ll_comp.h.

Referenced by LL_COMP_Init(), and LL_COMP_StructInit().

uint32_t LL_COMP_InitTypeDef::PowerMode

Set comparator operating mode to adjust power and speed. This parameter can be a value of Comparator modes - Power mode

This feature can be modified afterwards using unitary function LL_COMP_SetPowerMode().

Definition at line 67 of file stm32wbxx_ll_comp.h.

Referenced by LL_COMP_Init(), and LL_COMP_StructInit().

The documentation for this struct was generated from the following file:
  • stm32wbxx_ll_comp.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Comparator common modes - Window mode

Defines
Comparator common modes - Window mode
COMP Exported Constants

Defines

#define | LL_COMP_WINDOWMODE_DISABLE (0x00000000UL)
#define | LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE)

Define Documentation

#define LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE)

Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible).

Definition at line 113 of file stm32wbxx_ll_comp.h.

#define LL_COMP_WINDOWMODE_DISABLE (0x00000000UL)

Window mode disable: Comparators 1 and 2 are independent

Definition at line 112 of file stm32wbxx_ll_comp.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Comparator modes - Power mode

Defines
Comparator modes - Power mode
COMP Exported Constants

Defines

#define | LL_COMP_POWERMODE_HIGHSPEED (0x00000000UL)
#define | LL_COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0)
#define | LL_COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_PWRMODE_1 | COMP_CSR_PWRMODE_0)

Define Documentation

#define LL_COMP_POWERMODE_HIGHSPEED (0x00000000UL)

COMP power mode to high speed

Definition at line 121 of file stm32wbxx_ll_comp.h.

#define LL_COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0)

COMP power mode to medium speed

Definition at line 122 of file stm32wbxx_ll_comp.h.

#define LL_COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_PWRMODE_1 | COMP_CSR_PWRMODE_0)

COMP power mode to ultra-low power

Definition at line 123 of file stm32wbxx_ll_comp.h.

Referenced by LL_COMP_StructInit().

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Comparator inputs - Input plus (input non-inverting) selection

Defines
Comparator inputs - Input plus (input non-inverting) selection
COMP Exported Constants

Defines

#define | LL_COMP_INPUT_PLUS_IO1 (0x00000000UL)
#define | LL_COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0)
#define | LL_COMP_INPUT_PLUS_IO3 (COMP_CSR_INPSEL_1)

Define Documentation

#define LL_COMP_INPUT_PLUS_IO1 (0x00000000UL)

Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2)

Definition at line 131 of file stm32wbxx_ll_comp.h.

Referenced by LL_COMP_StructInit().

#define LL_COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0)

Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2)

Definition at line 132 of file stm32wbxx_ll_comp.h.

#define LL_COMP_INPUT_PLUS_IO3 (COMP_CSR_INPSEL_1)

Comparator input plus connected to IO3 (pin PA1 for COMP1, pin PA3 for COMP2)

Definition at line 133 of file stm32wbxx_ll_comp.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Comparator inputs - Input minus (input inverting) selection

Defines
Comparator inputs - Input minus (input inverting) selection
COMP Exported Constants

Defines

#define | LL_COMP_INPUT_MINUS_1_4VREFINT ( COMP_CSR_SCALEN | COMP_CSR_BRGEN)
#define | LL_COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)
#define | LL_COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)
#define | LL_COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN )
#define | LL_COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 )
#define | LL_COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)
#define | LL_COMP_INPUT_MINUS_IO3 ( COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)
#define | LL_COMP_INPUT_MINUS_IO4 (COMP_CSR_INMESEL_1 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)
#define | LL_COMP_INPUT_MINUS_IO5 (COMP_CSR_INMESEL_1 | COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)

Define Documentation

#define LL_COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)

Comparator input minus connected to 1/2 VrefInt

Definition at line 142 of file stm32wbxx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_1_4VREFINT ( COMP_CSR_SCALEN | COMP_CSR_BRGEN)

Comparator input minus connected to 1/4 VrefInt

Definition at line 141 of file stm32wbxx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)

Comparator input minus connected to 3/4 VrefInt

Definition at line 143 of file stm32wbxx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 )

Comparator input minus connected to IO1 (pin PA9 for COMP1, pin PB3 for COMP2)

Definition at line 145 of file stm32wbxx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)

Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PB7 for COMP2)

Definition at line 146 of file stm32wbxx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_IO3 ( COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)

Comparator input minus connected to IO3 (pin PA0 for COMP1, pin PA2 for COMP2)

Definition at line 147 of file stm32wbxx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_IO4 (COMP_CSR_INMESEL_1 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)

Comparator input minus connected to IO4 (pin PA4 for COMP1, pin PA4 for COMP2)

Definition at line 148 of file stm32wbxx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_IO5 (COMP_CSR_INMESEL_1 | COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)

Comparator input minus connected to IO5 (pin PA5 for COMP1, pin PA5 for COMP2)

Definition at line 149 of file stm32wbxx_ll_comp.h.

#define LL_COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN )

Comparator input minus connected to VrefInt

Definition at line 144 of file stm32wbxx_ll_comp.h.

Referenced by LL_COMP_StructInit().

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Comparator input - Hysteresis

Defines
Comparator input - Hysteresis
COMP Exported Constants

Defines

#define | LL_COMP_HYSTERESIS_NONE (0x00000000UL)
#define | LL_COMP_HYSTERESIS_LOW ( COMP_CSR_HYST_0)
#define | LL_COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1 )
#define | LL_COMP_HYSTERESIS_HIGH (COMP_CSR_HYST_1 | COMP_CSR_HYST_0)

Define Documentation

#define LL_COMP_HYSTERESIS_HIGH (COMP_CSR_HYST_1 | COMP_CSR_HYST_0)

Hysteresis level high

Definition at line 160 of file stm32wbxx_ll_comp.h.

#define LL_COMP_HYSTERESIS_LOW ( COMP_CSR_HYST_0)

Hysteresis level low

Definition at line 158 of file stm32wbxx_ll_comp.h.

#define LL_COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1 )

Hysteresis level medium

Definition at line 159 of file stm32wbxx_ll_comp.h.

#define LL_COMP_HYSTERESIS_NONE (0x00000000UL)

No hysteresis

Definition at line 157 of file stm32wbxx_ll_comp.h.

Referenced by LL_COMP_StructInit().

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Comparator output - Output polarity

Defines
Comparator output - Output polarity
COMP Exported Constants

Defines

#define | LL_COMP_OUTPUTPOL_NONINVERTED (0x00000000UL)
#define | LL_COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY)

Define Documentation

#define LL_COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY)

COMP output polarity is inverted: comparator output is low when the plus (non-inverting) input is at a lower voltage than the minus (inverting) input

Definition at line 169 of file stm32wbxx_ll_comp.h.

#define LL_COMP_OUTPUTPOL_NONINVERTED (0x00000000UL)

COMP output polarity is not inverted: comparator output is high when the plus (non-inverting) input is at a higher voltage than the minus (inverting) input

Definition at line 168 of file stm32wbxx_ll_comp.h.

Referenced by LL_COMP_StructInit().

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Comparator output - Blanking source

Defines
Comparator output - Blanking source
COMP Exported Constants

Defines

#define | LL_COMP_BLANKINGSRC_NONE (0x00000000UL)
#define | LL_COMP_BLANKINGSRC_TIM1_OC5 (COMP_CSR_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM2_OC3 (COMP_CSR_BLANKING_1)

Define Documentation

#define LL_COMP_BLANKINGSRC_NONE (0x00000000UL)

Comparator output without blanking

Definition at line 177 of file stm32wbxx_ll_comp.h.

Referenced by LL_COMP_StructInit().

#define LL_COMP_BLANKINGSRC_TIM1_OC5 (COMP_CSR_BLANKING_0)

Comparator output blanking source TIM1 OC5 (common to all COMP instances: COMP1, COMP2)

Definition at line 179 of file stm32wbxx_ll_comp.h.

#define LL_COMP_BLANKINGSRC_TIM2_OC3 (COMP_CSR_BLANKING_1)

Comparator output blanking source TIM2 OC3 (common to all COMP instances: COMP1, COMP2)

Definition at line 180 of file stm32wbxx_ll_comp.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Comparator output - Output level

Defines
Comparator output - Output level
COMP Exported Constants

Defines

#define | LL_COMP_OUTPUT_LEVEL_LOW (0x00000000UL)
#define | LL_COMP_OUTPUT_LEVEL_HIGH (0x00000001UL)

Define Documentation

#define LL_COMP_OUTPUT_LEVEL_HIGH (0x00000001UL)

Comparator output level high (if the polarity is not inverted, otherwise to be complemented)

Definition at line 189 of file stm32wbxx_ll_comp.h.

#define LL_COMP_OUTPUT_LEVEL_LOW (0x00000000UL)

Comparator output level low (if the polarity is not inverted, otherwise to be complemented)

Definition at line 188 of file stm32wbxx_ll_comp.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Definitions of COMP hardware constraints delays

Defines
Definitions of COMP hardware constraints delays
COMP Exported Constants

Defines

#define | LL_COMP_DELAY_STARTUP_US ( 80UL)
#define | LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US ( 200UL)

Detailed Description

Note:
Only COMP peripheral HW delays are defined in COMP LL driver driver, not timeout values. For details on delays values, refer to descriptions in source code above each literal definition.

Define Documentation

#define LL_COMP_DELAY_STARTUP_US ( 80UL)

Delay for COMP startup time

Definition at line 207 of file stm32wbxx_ll_comp.h.

#define LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US ( 200UL)

Delay for COMP voltage scaler stabilization time

Definition at line 215 of file stm32wbxx_ll_comp.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Common write and read registers macro

Defines
Common write and read registers macro
COMP Exported Macros

Defines

#define | LL_COMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
Write a value in COMP register.
#define | LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
Read a value in COMP register.

Define Documentation

#define LL_COMP_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG((__INSTANCE__)->__REG__)

Read a value in COMP register.

Parameters:
__INSTANCE__ | comparator instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 248 of file stm32wbxx_ll_comp.h.

#define LL_COMP_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))

Write a value in COMP register.

Parameters:
__INSTANCE__ | comparator instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 240 of file stm32wbxx_ll_comp.h.

Referenced by LL_COMP_DeInit().

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: COMP helper macro

Defines
COMP helper macro
COMP Exported Macros

Defines

#define __LL_COMP_COMMON_INSTANCE(__COMPx__) (COMP12_COMMON)
Helper macro to select the COMP common instance to which is belonging the selected COMP instance.

Define Documentation

#define __LL_COMP_COMMON_INSTANCE ( __COMPx__ ) (COMP12_COMMON)

Helper macro to select the COMP common instance to which is belonging the selected COMP instance.

Note:
COMP common register instance can be used to set parameters common to several COMP instances. Refer to functions having argument "COMPxy_COMMON" as parameter.
Parameters:
__COMPx__ COMP instance
Return values:
COMP common instance or value "0" if there is no COMP common instance.

Definition at line 266 of file stm32wbxx_ll_comp.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Configuration of COMP hierarchical scope: common to several COMP instances

Functions
Configuration of COMP hierarchical scope: common to several COMP instances
COMP Exported Functions

Functions

__STATIC_INLINE void | LL_COMP_SetCommonWindowMode (COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode)
Set window mode of a pair of comparators instances (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
__STATIC_INLINE uint32_t | LL_COMP_GetCommonWindowMode (COMP_Common_TypeDef *COMPxy_COMMON)
Get window mode of a pair of comparators instances (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).

Function Documentation

__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode ( COMP_Common_TypeDef * COMPxy_COMMON )

Get window mode of a pair of comparators instances (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).

Reference Manual to LL API cross reference:
CSR WINMODE LL_COMP_GetCommonWindowMode
Parameters:
COMPxy_COMMON Comparator common instance (can be set directly from CMSIS definition or by using helper macro __LL_COMP_COMMON_INSTANCE() )
Return values:
Returned value can be one of the following values:
  • LL_COMP_WINDOWMODE_DISABLE
  • LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON

Definition at line 314 of file stm32wbxx_ll_comp.h.

__STATIC_INLINE void LL_COMP_SetCommonWindowMode | ( | COMP_Common_TypeDef * | COMPxy_COMMON,
 |  | uint32_t | WindowMode
 | ) |  |

Set window mode of a pair of comparators instances (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).

Reference Manual to LL API cross reference:
CSR WINMODE LL_COMP_SetCommonWindowMode
Parameters:
COMPxy_COMMON Comparator common instance (can be set directly from CMSIS definition or by using helper macro __LL_COMP_COMMON_INSTANCE() )
WindowMode This parameter can be one of the following values:
  • LL_COMP_WINDOWMODE_DISABLE
  • LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
Return values:
None

Definition at line 297 of file stm32wbxx_ll_comp.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Configuration of comparator modes

Functions
Configuration of comparator modes
COMP Exported Functions

Functions

__STATIC_INLINE void | LL_COMP_SetPowerMode (COMP_TypeDef *COMPx, uint32_t PowerMode)
Set comparator instance operating mode to adjust power and speed.
__STATIC_INLINE uint32_t | LL_COMP_GetPowerMode (COMP_TypeDef *COMPx)
Get comparator instance operating mode to adjust power and speed.

Function Documentation

__STATIC_INLINE uint32_t LL_COMP_GetPowerMode ( COMP_TypeDef * COMPx )

Get comparator instance operating mode to adjust power and speed.

Reference Manual to LL API cross reference:
CSR PWRMODE LL_COMP_GetPowerMode
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_POWERMODE_HIGHSPEED
  • LL_COMP_POWERMODE_MEDIUMSPEED
  • LL_COMP_POWERMODE_ULTRALOWPOWER

Definition at line 351 of file stm32wbxx_ll_comp.h.

__STATIC_INLINE void LL_COMP_SetPowerMode | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | PowerMode
 | ) |  |

Set comparator instance operating mode to adjust power and speed.

Reference Manual to LL API cross reference:
CSR PWRMODE LL_COMP_SetPowerMode
Parameters:
COMPx Comparator instance
PowerMode This parameter can be one of the following values:
  • LL_COMP_POWERMODE_HIGHSPEED
  • LL_COMP_POWERMODE_MEDIUMSPEED
  • LL_COMP_POWERMODE_ULTRALOWPOWER
Return values:
None

Definition at line 337 of file stm32wbxx_ll_comp.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Configuration of comparator inputs

Functions
Configuration of comparator inputs
COMP Exported Functions

Functions

__STATIC_INLINE void | LL_COMP_ConfigInputs (COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputPlus)
Set comparator inputs minus (inverting) and plus (non-inverting).
__STATIC_INLINE void | LL_COMP_SetInputPlus (COMP_TypeDef *COMPx, uint32_t InputPlus)
Set comparator input plus (non-inverting).
__STATIC_INLINE uint32_t | LL_COMP_GetInputPlus (COMP_TypeDef *COMPx)
Get comparator input plus (non-inverting).
__STATIC_INLINE void | LL_COMP_SetInputMinus (COMP_TypeDef *COMPx, uint32_t InputMinus)
Set comparator input minus (inverting).
__STATIC_INLINE uint32_t | LL_COMP_GetInputMinus (COMP_TypeDef *COMPx)
Get comparator input minus (inverting).
__STATIC_INLINE void | LL_COMP_SetInputHysteresis (COMP_TypeDef *COMPx, uint32_t InputHysteresis)
Set comparator instance hysteresis mode of the input minus (inverting input).
__STATIC_INLINE uint32_t | LL_COMP_GetInputHysteresis (COMP_TypeDef *COMPx)
Get comparator instance hysteresis mode of the minus (inverting) input.

Function Documentation

__STATIC_INLINE void LL_COMP_ConfigInputs | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | InputMinus,
 |  | uint32_t | InputPlus
 | ) |  |

Set comparator inputs minus (inverting) and plus (non-inverting).

Note:
In case of comparator input selected to be connected to IO: GPIO pins are specific to each comparator instance. Refer to description of parameters or to reference manual.
On this STM32 serie, scaler bridge is configurable: to optimize power consumption, this function enables the voltage scaler bridge only when required (when selecting comparator input based on VrefInt: VrefInt or subdivision of VrefInt).
  • For scaler bridge power consumption values, refer to device datasheet, parameter "IDDA(SCALER)".
  • Voltage scaler requires a delay for voltage stabilization. Refer to device datasheet, parameter "tSTART_SCALER".
  • Scaler bridge is common for all comparator instances, therefore if at least one of the comparator instance is requiring the scaler bridge, it remains enabled.
Reference Manual to LL API cross reference:
CSR INMSEL LL_COMP_ConfigInputs
CSR INPSEL LL_COMP_ConfigInputs
CSR BRGEN LL_COMP_ConfigInputs
CSR SCALEN LL_COMP_ConfigInputs
Parameters:
COMPx Comparator instance
InputMinus This parameter can be one of the following values:
  • LL_COMP_INPUT_MINUS_1_4VREFINT
  • LL_COMP_INPUT_MINUS_1_2VREFINT
  • LL_COMP_INPUT_MINUS_3_4VREFINT
  • LL_COMP_INPUT_MINUS_VREFINT
  • LL_COMP_INPUT_MINUS_IO1
  • LL_COMP_INPUT_MINUS_IO2
  • LL_COMP_INPUT_MINUS_IO3
  • LL_COMP_INPUT_MINUS_IO4
  • LL_COMP_INPUT_MINUS_IO5
InputPlus This parameter can be one of the following values:
  • LL_COMP_INPUT_PLUS_IO1
  • LL_COMP_INPUT_PLUS_IO2
  • LL_COMP_INPUT_PLUS_IO3 (*)
(*) Parameter not available on all devices.
Return values:
None

Definition at line 404 of file stm32wbxx_ll_comp.h.

__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis ( COMP_TypeDef * COMPx )

Get comparator instance hysteresis mode of the minus (inverting) input.

Reference Manual to LL API cross reference:
CSR HYST LL_COMP_GetInputHysteresis
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_HYSTERESIS_NONE
  • LL_COMP_HYSTERESIS_LOW
  • LL_COMP_HYSTERESIS_MEDIUM
  • LL_COMP_HYSTERESIS_HIGH

Definition at line 539 of file stm32wbxx_ll_comp.h.

__STATIC_INLINE uint32_t LL_COMP_GetInputMinus ( COMP_TypeDef * COMPx )

Get comparator input minus (inverting).

Note:
In case of comparator input selected to be connected to IO: GPIO pins are specific to each comparator instance. Refer to description of parameters or to reference manual.
Reference Manual to LL API cross reference:
CSR INMSEL LL_COMP_GetInputMinus
CSR BRGEN LL_COMP_GetInputMinus
CSR SCALEN LL_COMP_GetInputMinus
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_INPUT_MINUS_1_4VREFINT
  • LL_COMP_INPUT_MINUS_1_2VREFINT
  • LL_COMP_INPUT_MINUS_3_4VREFINT
  • LL_COMP_INPUT_MINUS_VREFINT
  • LL_COMP_INPUT_MINUS_IO1
  • LL_COMP_INPUT_MINUS_IO2
  • LL_COMP_INPUT_MINUS_IO3
  • LL_COMP_INPUT_MINUS_IO4
  • LL_COMP_INPUT_MINUS_IO5

Definition at line 508 of file stm32wbxx_ll_comp.h.

__STATIC_INLINE uint32_t LL_COMP_GetInputPlus ( COMP_TypeDef * COMPx )

Get comparator input plus (non-inverting).

Note:
In case of comparator input selected to be connected to IO: GPIO pins are specific to each comparator instance. Refer to description of parameters or to reference manual.
Reference Manual to LL API cross reference:
CSR INPSEL LL_COMP_GetInputPlus
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_INPUT_PLUS_IO1
  • LL_COMP_INPUT_PLUS_IO2
  • LL_COMP_INPUT_PLUS_IO3 (*)
(*) Parameter not available on all devices.

Definition at line 445 of file stm32wbxx_ll_comp.h.

__STATIC_INLINE void LL_COMP_SetInputHysteresis | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | InputHysteresis
 | ) |  |

Set comparator instance hysteresis mode of the input minus (inverting input).

Reference Manual to LL API cross reference:
CSR HYST LL_COMP_SetInputHysteresis
Parameters:
COMPx Comparator instance
InputHysteresis This parameter can be one of the following values:
  • LL_COMP_HYSTERESIS_NONE
  • LL_COMP_HYSTERESIS_LOW
  • LL_COMP_HYSTERESIS_MEDIUM
  • LL_COMP_HYSTERESIS_HIGH
Return values:
None

Definition at line 524 of file stm32wbxx_ll_comp.h.

__STATIC_INLINE void LL_COMP_SetInputMinus | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | InputMinus
 | ) |  |

Set comparator input minus (inverting).

Note:
In case of comparator input selected to be connected to IO: GPIO pins are specific to each comparator instance. Refer to description of parameters or to reference manual.
On this STM32 serie, scaler bridge is configurable: to optimize power consumption, this function enables the voltage scaler bridge only when required (when selecting comparator input based on VrefInt: VrefInt or subdivision of VrefInt).
  • For scaler bridge power consumption values, refer to device datasheet, parameter "IDDA(SCALER)".
  • Voltage scaler requires a delay for voltage stabilization. Refer to device datasheet, parameter "tSTART_SCALER".
  • Scaler bridge is common for all comparator instances, therefore if at least one of the comparator instance is requiring the scaler bridge, it remains enabled.
Reference Manual to LL API cross reference:
CSR INMSEL LL_COMP_SetInputMinus
CSR BRGEN LL_COMP_SetInputMinus
CSR SCALEN LL_COMP_SetInputMinus
Parameters:
COMPx Comparator instance
InputMinus This parameter can be one of the following values:
  • LL_COMP_INPUT_MINUS_1_4VREFINT
  • LL_COMP_INPUT_MINUS_1_2VREFINT
  • LL_COMP_INPUT_MINUS_3_4VREFINT
  • LL_COMP_INPUT_MINUS_VREFINT
  • LL_COMP_INPUT_MINUS_IO1
  • LL_COMP_INPUT_MINUS_IO2
  • LL_COMP_INPUT_MINUS_IO3
  • LL_COMP_INPUT_MINUS_IO4
  • LL_COMP_INPUT_MINUS_IO5
Return values:
None

Definition at line 483 of file stm32wbxx_ll_comp.h.

__STATIC_INLINE void LL_COMP_SetInputPlus | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | InputPlus
 | ) |  |

Set comparator input plus (non-inverting).

Note:
In case of comparator input selected to be connected to IO: GPIO pins are specific to each comparator instance. Refer to description of parameters or to reference manual.
Reference Manual to LL API cross reference:
CSR INPSEL LL_COMP_SetInputPlus
Parameters:
COMPx Comparator instance
InputPlus This parameter can be one of the following values:
  • LL_COMP_INPUT_PLUS_IO1
  • LL_COMP_INPUT_PLUS_IO2
  • LL_COMP_INPUT_PLUS_IO3 (*)
(*) Parameter not available on all devices.
Return values:
None

Definition at line 426 of file stm32wbxx_ll_comp.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Configuration of comparator output

Functions
Configuration of comparator output
COMP Exported Functions

Functions

__STATIC_INLINE void | LL_COMP_SetOutputPolarity (COMP_TypeDef *COMPx, uint32_t OutputPolarity)
Set comparator instance output polarity.
__STATIC_INLINE uint32_t | LL_COMP_GetOutputPolarity (COMP_TypeDef *COMPx)
Get comparator instance output polarity.
__STATIC_INLINE void | LL_COMP_SetOutputBlankingSource (COMP_TypeDef *COMPx, uint32_t BlankingSource)
Set comparator instance blanking source.
__STATIC_INLINE uint32_t | LL_COMP_GetOutputBlankingSource (COMP_TypeDef *COMPx)
Get comparator instance blanking source.

Function Documentation

__STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource ( COMP_TypeDef * COMPx )

Get comparator instance blanking source.

Note:
Availability of parameters of blanking source from timer depends on timers availability on the selected device.
Blanking source may be specific to each comparator instance. Refer to description of parameters or to reference manual.
Reference Manual to LL API cross reference:
CSR BLANKING LL_COMP_GetOutputBlankingSource
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_BLANKINGSRC_NONE
  • LL_COMP_BLANKINGSRC_TIM1_OC5 (1)
  • LL_COMP_BLANKINGSRC_TIM2_OC3 (1)
(1) Parameter availability depending on timer availability on the selected device.

Definition at line 617 of file stm32wbxx_ll_comp.h.

__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity ( COMP_TypeDef * COMPx )

Get comparator instance output polarity.

Reference Manual to LL API cross reference:
CSR POLARITY LL_COMP_GetOutputPolarity
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_OUTPUTPOL_NONINVERTED
  • LL_COMP_OUTPUTPOL_INVERTED

Definition at line 574 of file stm32wbxx_ll_comp.h.

__STATIC_INLINE void LL_COMP_SetOutputBlankingSource | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | BlankingSource
 | ) |  |

Set comparator instance blanking source.

Note:
Blanking source may be specific to each comparator instance. Refer to description of parameters or to reference manual.
Availability of parameters of blanking source from timer depends on timers availability on the selected device.
Reference Manual to LL API cross reference:
CSR BLANKING LL_COMP_SetOutputBlankingSource
Parameters:
COMPx Comparator instance
BlankingSource This parameter can be one of the following values:
  • LL_COMP_BLANKINGSRC_NONE
  • LL_COMP_BLANKINGSRC_TIM1_OC5 (1)
  • LL_COMP_BLANKINGSRC_TIM2_OC3 (1)
(1) Parameter availability depending on timer availability on the selected device.
Return values:
None

Definition at line 596 of file stm32wbxx_ll_comp.h.

__STATIC_INLINE void LL_COMP_SetOutputPolarity | ( | COMP_TypeDef * | COMPx,
 |  | uint32_t | OutputPolarity
 | ) |  |

Set comparator instance output polarity.

Reference Manual to LL API cross reference:
CSR POLARITY LL_COMP_SetOutputPolarity
Parameters:
COMPx Comparator instance
OutputPolarity This parameter can be one of the following values:
  • LL_COMP_OUTPUTPOL_NONINVERTED
  • LL_COMP_OUTPUTPOL_INVERTED
Return values:
None

Definition at line 561 of file stm32wbxx_ll_comp.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Operation on comparator instance

Functions
Operation on comparator instance
COMP Exported Functions

Functions

__STATIC_INLINE void | LL_COMP_Enable (COMP_TypeDef *COMPx)
Enable comparator instance.
__STATIC_INLINE void | LL_COMP_Disable (COMP_TypeDef *COMPx)
Disable comparator instance.
__STATIC_INLINE uint32_t | LL_COMP_IsEnabled (COMP_TypeDef *COMPx)
Get comparator enable state (0: COMP is disabled, 1: COMP is enabled)
__STATIC_INLINE void | LL_COMP_Lock (COMP_TypeDef *COMPx)
Lock comparator instance.
__STATIC_INLINE uint32_t | LL_COMP_IsLocked (COMP_TypeDef *COMPx)
Get comparator lock state (0: COMP is unlocked, 1: COMP is locked).
__STATIC_INLINE uint32_t | LL_COMP_ReadOutputLevel (COMP_TypeDef *COMPx)
Read comparator instance output level.

Function Documentation

__STATIC_INLINE void LL_COMP_Disable ( COMP_TypeDef * COMPx )

Disable comparator instance.

Reference Manual to LL API cross reference:
CSR EN LL_COMP_Disable
Parameters:
COMPx Comparator instance
Return values:
None

Definition at line 650 of file stm32wbxx_ll_comp.h.

__STATIC_INLINE void LL_COMP_Enable ( COMP_TypeDef * COMPx )

Enable comparator instance.

Note:
After enable from off state, comparator requires a delay to reach reach propagation delay specification. Refer to device datasheet, parameter "tSTART".
Reference Manual to LL API cross reference:
CSR EN LL_COMP_Enable
Parameters:
COMPx Comparator instance
Return values:
None

Definition at line 639 of file stm32wbxx_ll_comp.h.

__STATIC_INLINE uint32_t LL_COMP_IsEnabled ( COMP_TypeDef * COMPx )

Get comparator enable state (0: COMP is disabled, 1: COMP is enabled)

Reference Manual to LL API cross reference:
CSR EN LL_COMP_IsEnabled
Parameters:
COMPx Comparator instance
Return values:
State of bit (1 or 0).

Definition at line 662 of file stm32wbxx_ll_comp.h.

__STATIC_INLINE uint32_t LL_COMP_IsLocked ( COMP_TypeDef * COMPx )

Get comparator lock state (0: COMP is unlocked, 1: COMP is locked).

Note:
Once locked, comparator configuration can be accessed in read-only.
The only way to unlock the comparator is a device hardware reset.
Reference Manual to LL API cross reference:
CSR LOCK LL_COMP_IsLocked
Parameters:
COMPx Comparator instance
Return values:
State of bit (1 or 0).

Definition at line 689 of file stm32wbxx_ll_comp.h.

Referenced by LL_COMP_DeInit(), and LL_COMP_Init().

__STATIC_INLINE void LL_COMP_Lock ( COMP_TypeDef * COMPx )

Lock comparator instance.

Note:
Once locked, comparator configuration can be accessed in read-only.
The only way to unlock the comparator is a device hardware reset.
Reference Manual to LL API cross reference:
CSR LOCK LL_COMP_Lock
Parameters:
COMPx Comparator instance
Return values:
None

Definition at line 675 of file stm32wbxx_ll_comp.h.

__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel ( COMP_TypeDef * COMPx )

Read comparator instance output level.

Note:
The comparator output level depends on the selected polarity (Refer to function LL_COMP_SetOutputPolarity()). If the comparator polarity is not inverted:
  • Comparator output is low when the input plus is at a lower voltage than the input minus
  • Comparator output is high when the input plus is at a higher voltage than the input minus If the comparator polarity is inverted:
  • Comparator output is high when the input plus is at a lower voltage than the input minus
  • Comparator output is low when the input plus is at a higher voltage than the input minus
Reference Manual to LL API cross reference:
CSR VALUE LL_COMP_ReadOutputLevel
Parameters:
COMPx Comparator instance
Return values:
Returned value can be one of the following values:
  • LL_COMP_OUTPUT_LEVEL_LOW
  • LL_COMP_OUTPUT_LEVEL_HIGH

Definition at line 714 of file stm32wbxx_ll_comp.h.

References LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
COMP Exported Functions

Functions

ErrorStatus | LL_COMP_DeInit (COMP_TypeDef *COMPx)
De-initialize registers of the selected COMP instance to their default reset values.
ErrorStatus | LL_COMP_Init (COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct)
Initialize some features of COMP instance.
void | LL_COMP_StructInit (LL_COMP_InitTypeDef *COMP_InitStruct)
Set each LL_COMP_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_COMP_DeInit ( COMP_TypeDef * COMPx )

De-initialize registers of the selected COMP instance to their default reset values.

Note:
If comparator is locked, de-initialization by software is not possible. The only way to unlock the comparator is a device hardware reset.
Parameters:
COMPx COMP instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: COMP registers are de-initialized
  • ERROR: COMP registers are not de-initialized

Definition at line 129 of file stm32wbxx_ll_comp.c.

References assert_param, LL_COMP_IsLocked(), and LL_COMP_WriteReg.

ErrorStatus LL_COMP_Init | ( | COMP_TypeDef * | COMPx,
 |  | LL_COMP_InitTypeDef * | COMP_InitStruct
 | ) |  |

Initialize some features of COMP instance.

Note:
This function configures features of the selected COMP instance. Some features are also available at scope COMP common instance (common to several COMP instances). Refer to functions having argument "COMPxy_COMMON" as parameter.
Parameters:
COMPx | COMP instance
COMP_InitStruct | Pointer to a LL_COMP_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: COMP registers are initialized
  • ERROR: COMP registers are not initialized

Definition at line 166 of file stm32wbxx_ll_comp.c.

References assert_param, LL_COMP_InitTypeDef::InputHysteresis, LL_COMP_InitTypeDef::InputMinus, LL_COMP_InitTypeDef::InputPlus, IS_LL_COMP_INPUT_HYSTERESIS, IS_LL_COMP_INPUT_MINUS, IS_LL_COMP_INPUT_PLUS, IS_LL_COMP_OUTPUT_BLANKING_SOURCE, IS_LL_COMP_OUTPUT_POLARITY, IS_LL_COMP_POWER_MODE, LL_COMP_IsLocked(), LL_COMP_InitTypeDef::OutputBlankingSource, LL_COMP_InitTypeDef::OutputPolarity, and LL_COMP_InitTypeDef::PowerMode.

void LL_COMP_StructInit ( LL_COMP_InitTypeDef * COMP_InitStruct )

Set each LL_COMP_InitTypeDef field to default value.

Parameters:
COMP_InitStruct Pointer to a LL_COMP_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 225 of file stm32wbxx_ll_comp.c.

References LL_COMP_InitTypeDef::InputHysteresis, LL_COMP_InitTypeDef::InputMinus, LL_COMP_InitTypeDef::InputPlus, LL_COMP_BLANKINGSRC_NONE, LL_COMP_HYSTERESIS_NONE, LL_COMP_INPUT_MINUS_VREFINT, LL_COMP_INPUT_PLUS_IO1, LL_COMP_OUTPUTPOL_NONINVERTED, LL_COMP_POWERMODE_ULTRALOWPOWER, LL_COMP_InitTypeDef::OutputBlankingSource, LL_COMP_InitTypeDef::OutputPolarity, and LL_COMP_InitTypeDef::PowerMode.

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STM32WB55xx HAL User Manual: COMP_LL_Private_Macros

Defines
COMP_LL_Private_Macros
COMP

Defines

#define | IS_LL_COMP_POWER_MODE(__POWER_MODE__)
#define | IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)
#define | IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)
#define | IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__)
#define | IS_LL_COMP_OUTPUT_POLARITY(__POLARITY__)
#define | IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__OUTPUT_BLANKING_SOURCE__)

Define Documentation

#define IS_LL_COMP_INPUT_HYSTERESIS ( __INPUT_HYSTERESIS__ )
Value:
(   ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_NONE)                      \
   || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_LOW)                       \
   || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_MEDIUM)                    \
   || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_HIGH)                      \
  )

Definition at line 84 of file stm32wbxx_ll_comp.c.

Referenced by LL_COMP_Init().

#define IS_LL_COMP_INPUT_MINUS | ( | __COMP_INSTANCE__,
 |  | __INPUT_MINUS__
 | ) |
Value:
(   ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT)                    \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT)                    \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT)                    \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT)                       \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1)                           \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2)                           \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO3)                           \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO4)                           \
   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO5)                           \
  )

Definition at line 72 of file stm32wbxx_ll_comp.c.

Referenced by LL_COMP_Init().

#define IS_LL_COMP_INPUT_PLUS | ( | __COMP_INSTANCE__,
 |  | __INPUT_PLUS__
 | ) |
Value:
(   ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1)                             \
   || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2)                             \
   || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO3)                             \
  )

Definition at line 62 of file stm32wbxx_ll_comp.c.

Referenced by LL_COMP_Init().

#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE ( __OUTPUT_BLANKING_SOURCE__ )
Value:
(   ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE)               \
   || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5)           \
   || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3)           \
  )

Definition at line 96 of file stm32wbxx_ll_comp.c.

Referenced by LL_COMP_Init().

#define IS_LL_COMP_OUTPUT_POLARITY ( __POLARITY__ )
Value:
(   ((__POLARITY__) == LL_COMP_OUTPUTPOL_NONINVERTED)                        \
   || ((__POLARITY__) == LL_COMP_OUTPUTPOL_INVERTED)                           \
  )

Definition at line 91 of file stm32wbxx_ll_comp.c.

Referenced by LL_COMP_Init().

#define IS_LL_COMP_POWER_MODE ( __POWER_MODE__ )
Value:
(   ((__POWER_MODE__) == LL_COMP_POWERMODE_HIGHSPEED)                        \
   || ((__POWER_MODE__) == LL_COMP_POWERMODE_MEDIUMSPEED)                      \
   || ((__POWER_MODE__) == LL_COMP_POWERMODE_ULTRALOWPOWER)                    \
  )

Definition at line 52 of file stm32wbxx_ll_comp.c.

Referenced by LL_COMP_Init().

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STM32WB55xx HAL User Manual: CORTEX

Modules
CORTEX
STM32WBxx_LL_Driver

Modules

CORTEX Exported Constants
CORTEX Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for CORTEX registers.

Register | Bit | Function
MPU_CTRL | ENABLE | LL_MPU_Disable
 |  | LL_MPU_Enable
 |  | LL_MPU_IsEnabled
MPU_RASR | AP | LL_MPU_ConfigRegion
 | B | LL_MPU_ConfigRegion
 | C | LL_MPU_ConfigRegion
 | ENABLE | LL_MPU_DisableRegion
 |  | LL_MPU_EnableRegion
 | S | LL_MPU_ConfigRegion
 | SIZE | LL_MPU_ConfigRegion
 | XN | LL_MPU_ConfigRegion
MPU_RBAR | ADDR | LL_MPU_ConfigRegion
 | REGION | LL_MPU_ConfigRegion
MPU_RNR | REGION | LL_MPU_ConfigRegion
 |  | LL_MPU_DisableRegion
SCB_CPUID | ARCHITECTURE | LL_CPUID_GetConstant
 | IMPLEMENTER | LL_CPUID_GetImplementer
 | PARTNO | LL_CPUID_GetParNo
 | REVISION | LL_CPUID_GetRevision
 | VARIANT | LL_CPUID_GetVariant
SCB_SCR | SEVEONPEND | LL_LPM_DisableEventOnPend
 |  | LL_LPM_EnableEventOnPend
 | SLEEPDEEP | LL_LPM_EnableDeepSleep
 |  | LL_LPM_EnableSleep
 | SLEEPONEXIT | LL_LPM_DisableSleepOnExit
 |  | LL_LPM_EnableSleepOnExit
SCB_SHCSR | MEMFAULTENA | LL_HANDLER_DisableFault
 |  | LL_HANDLER_EnableFault
STK_CTRL | CLKSOURCE | LL_SYSTICK_GetClkSource
 |  | LL_SYSTICK_SetClkSource
 | COUNTFLAG | LL_SYSTICK_IsActiveCounterFlag
 | TICKINT | LL_SYSTICK_DisableIT
 |  | LL_SYSTICK_EnableIT
 |  | LL_SYSTICK_IsEnabledIT
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STM32WB55xx HAL User Manual: SYSTICK Clock Source

Defines
SYSTICK Clock Source
CORTEX Exported Constants

Defines

#define | LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
#define | LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk

Define Documentation

#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk

AHB clock selected as SysTick clock source.

Definition at line 71 of file stm32wbxx_ll_cortex.h.

Referenced by LL_SYSTICK_GetClkSource(), and LL_SYSTICK_SetClkSource().

#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U

AHB clock divided by 8 selected as SysTick clock source.

Definition at line 70 of file stm32wbxx_ll_cortex.h.

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STM32WB55xx HAL User Manual: Handler Fault type

Defines
Handler Fault type
CORTEX Exported Constants

Defines

#define | LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk
#define | LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk
#define | LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk

Define Documentation

#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk

Bus fault

Definition at line 80 of file stm32wbxx_ll_cortex.h.

#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk

Memory management fault

Definition at line 81 of file stm32wbxx_ll_cortex.h.

#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk

Usage fault

Definition at line 79 of file stm32wbxx_ll_cortex.h.

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STM32WB55xx HAL User Manual: MPU Control

Defines
MPU Control
CORTEX Exported Constants

Defines

#define | LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U
#define | LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk
#define | LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
#define | LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)

Define Documentation

#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk

Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers

Definition at line 92 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)

Enable NMI and privileged SW access

Definition at line 94 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U

Disable NMI and privileged SW access

Definition at line 91 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk

Enable privileged software access to default memory map

Definition at line 93 of file stm32wbxx_ll_cortex.h.

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STM32WB55xx HAL User Manual: MPU Region Number

Defines
MPU Region Number
CORTEX Exported Constants

Defines

#define | LL_MPU_REGION_NUMBER0 0x00U
#define | LL_MPU_REGION_NUMBER1 0x01U
#define | LL_MPU_REGION_NUMBER2 0x02U
#define | LL_MPU_REGION_NUMBER3 0x03U
#define | LL_MPU_REGION_NUMBER4 0x04U
#define | LL_MPU_REGION_NUMBER5 0x05U
#define | LL_MPU_REGION_NUMBER6 0x06U
#define | LL_MPU_REGION_NUMBER7 0x07U

Define Documentation

#define LL_MPU_REGION_NUMBER0 0x00U

REGION Number 0

Definition at line 102 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER1 0x01U

REGION Number 1

Definition at line 103 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER2 0x02U

REGION Number 2

Definition at line 104 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER3 0x03U

REGION Number 3

Definition at line 105 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER4 0x04U

REGION Number 4

Definition at line 106 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER5 0x05U

REGION Number 5

Definition at line 107 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER6 0x06U

REGION Number 6

Definition at line 108 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_REGION_NUMBER7 0x07U

REGION Number 7

Definition at line 109 of file stm32wbxx_ll_cortex.h.

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STM32WB55xx HAL User Manual: MPU Region Size

Defines
MPU Region Size
CORTEX Exported Constants

Defines

#define | LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos)

Define Documentation

#define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos)

128B Size of the MPU protection region

Definition at line 119 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos)

128KB Size of the MPU protection region

Definition at line 129 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos)

128MB Size of the MPU protection region

Definition at line 139 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos)

16KB Size of the MPU protection region

Definition at line 126 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos)

16MB Size of the MPU protection region

Definition at line 136 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos)

1GB Size of the MPU protection region

Definition at line 142 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos)

1KB Size of the MPU protection region

Definition at line 122 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos)

1MB Size of the MPU protection region

Definition at line 132 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos)

256B Size of the MPU protection region

Definition at line 120 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos)

256KB Size of the MPU protection region

Definition at line 130 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos)

256MB Size of the MPU protection region

Definition at line 140 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos)

2GB Size of the MPU protection region

Definition at line 143 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos)

2KB Size of the MPU protection region

Definition at line 123 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos)

2MB Size of the MPU protection region

Definition at line 133 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos)

32B Size of the MPU protection region

Definition at line 117 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos)

32KB Size of the MPU protection region

Definition at line 127 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos)

32MB Size of the MPU protection region

Definition at line 137 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos)

4GB Size of the MPU protection region

Definition at line 144 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos)

4KB Size of the MPU protection region

Definition at line 124 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos)

4MB Size of the MPU protection region

Definition at line 134 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos)

512B Size of the MPU protection region

Definition at line 121 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos)

512KB Size of the MPU protection region

Definition at line 131 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos)

512MB Size of the MPU protection region

Definition at line 141 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos)

64B Size of the MPU protection region

Definition at line 118 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos)

64KB Size of the MPU protection region

Definition at line 128 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos)

64MB Size of the MPU protection region

Definition at line 138 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos)

8KB Size of the MPU protection region

Definition at line 125 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos)

8MB Size of the MPU protection region

Definition at line 135 of file stm32wbxx_ll_cortex.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: MPU Region Privileges

Defines
MPU Region Privileges
CORTEX Exported Constants

Defines

#define | LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos)

Define Documentation

#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos)

RW privileged & user (Full access)

Definition at line 155 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos)

No access

Definition at line 152 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos)

RO privileged (privileged read only)

Definition at line 156 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos)

RO privileged & user (read only)

Definition at line 157 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos)

RW privileged (privileged access only)

Definition at line 153 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos)

RW privileged - RO user (Write in a user program generates a fault)

Definition at line 154 of file stm32wbxx_ll_cortex.h.

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STM32WB55xx HAL User Manual: MPU TEX Level

Defines
MPU TEX Level
CORTEX Exported Constants

Defines

#define | LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos)
#define | LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos)
#define | LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos)
#define | LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos)

Define Documentation

#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos)

b000 for TEX bits

Definition at line 165 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos)

b001 for TEX bits

Definition at line 166 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos)

b010 for TEX bits

Definition at line 167 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos)

b100 for TEX bits

Definition at line 168 of file stm32wbxx_ll_cortex.h.

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STM32WB55xx HAL User Manual: MPU Instruction Access

Defines
MPU Instruction Access
CORTEX Exported Constants

Defines

#define | LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U
#define | LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk

Define Documentation

#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk

Instruction fetches disabled

Definition at line 177 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U

Instruction fetches enabled

Definition at line 176 of file stm32wbxx_ll_cortex.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: MPU Shareable Access

Defines
MPU Shareable Access
CORTEX Exported Constants

Defines

#define | LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk
#define | LL_MPU_ACCESS_NOT_SHAREABLE 0x00U

Define Documentation

#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U

Not Shareable memory attribute

Definition at line 186 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk

Shareable memory attribute

Definition at line 185 of file stm32wbxx_ll_cortex.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: MPU Cacheable Access

Defines
MPU Cacheable Access
CORTEX Exported Constants

Defines

#define | LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk
#define | LL_MPU_ACCESS_NOT_CACHEABLE 0x00U

Define Documentation

#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk

Cacheable memory attribute

Definition at line 194 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U

Not Cacheable memory attribute

Definition at line 195 of file stm32wbxx_ll_cortex.h.

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STM32WB55xx HAL User Manual: MPU Bufferable Access

Defines
MPU Bufferable Access
CORTEX Exported Constants

Defines

#define | LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk
#define | LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U

Define Documentation

#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk

Bufferable memory attribute

Definition at line 203 of file stm32wbxx_ll_cortex.h.

#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U

Not Bufferable memory attribute

Definition at line 204 of file stm32wbxx_ll_cortex.h.

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STM32WB55xx HAL User Manual: SYSTICK

Functions
SYSTICK
CORTEX Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_SYSTICK_IsActiveCounterFlag (void)
This function checks if the Systick counter flag is active or not.
__STATIC_INLINE void | LL_SYSTICK_SetClkSource (uint32_t Source)
Configures the SysTick clock source.
__STATIC_INLINE uint32_t | LL_SYSTICK_GetClkSource (void)
Get the SysTick clock source.
__STATIC_INLINE void | LL_SYSTICK_EnableIT (void)
Enable SysTick exception request.
__STATIC_INLINE void | LL_SYSTICK_DisableIT (void)
Disable SysTick exception request.
__STATIC_INLINE uint32_t | LL_SYSTICK_IsEnabledIT (void)
Checks if the SYSTICK interrupt is enabled or disabled.

Function Documentation

__STATIC_INLINE void LL_SYSTICK_DisableIT ( void )

Disable SysTick exception request.

Reference Manual to LL API cross reference:
STK_CTRL TICKINT LL_SYSTICK_DisableIT
Return values:
None

Definition at line 282 of file stm32wbxx_ll_cortex.h.

__STATIC_INLINE void LL_SYSTICK_EnableIT ( void )

Enable SysTick exception request.

Reference Manual to LL API cross reference:
STK_CTRL TICKINT LL_SYSTICK_EnableIT
Return values:
None

Definition at line 272 of file stm32wbxx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource ( void )

Get the SysTick clock source.

Reference Manual to LL API cross reference:
STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
Return values:
Returned value can be one of the following values:
  • LL_SYSTICK_CLKSOURCE_HCLK_DIV8
  • LL_SYSTICK_CLKSOURCE_HCLK

Definition at line 262 of file stm32wbxx_ll_cortex.h.

References LL_SYSTICK_CLKSOURCE_HCLK.

__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag ( void )

This function checks if the Systick counter flag is active or not.

Note:
It can be used in timeout function on application side.
Reference Manual to LL API cross reference:
STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
Return values:
State of bit (1 or 0).

Definition at line 230 of file stm32wbxx_ll_cortex.h.

Referenced by LL_RTC_EnterInitMode(), and LL_RTC_WaitForSynchro().

__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT ( void )

Checks if the SYSTICK interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
Return values:
State of bit (1 or 0).

Definition at line 292 of file stm32wbxx_ll_cortex.h.

__STATIC_INLINE void LL_SYSTICK_SetClkSource ( uint32_t Source )

Configures the SysTick clock source.

Reference Manual to LL API cross reference:
STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
Parameters:
Source This parameter can be one of the following values:
  • LL_SYSTICK_CLKSOURCE_HCLK_DIV8
  • LL_SYSTICK_CLKSOURCE_HCLK
Return values:
None

Definition at line 243 of file stm32wbxx_ll_cortex.h.

References LL_SYSTICK_CLKSOURCE_HCLK.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LOW POWER MODE

Functions
LOW POWER MODE
CORTEX Exported Functions

Functions

__STATIC_INLINE void | LL_LPM_EnableSleep (void)
Processor uses sleep as its low power mode.
__STATIC_INLINE void | LL_LPM_EnableDeepSleep (void)
Processor uses deep sleep as its low power mode.
__STATIC_INLINE void | LL_LPM_EnableSleepOnExit (void)
Configures sleep-on-exit when returning from Handler mode to Thread mode.
__STATIC_INLINE void | LL_LPM_DisableSleepOnExit (void)
Do not sleep when returning to Thread mode.
__STATIC_INLINE void | LL_LPM_EnableEventOnPend (void)
Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.
__STATIC_INLINE void | LL_LPM_DisableEventOnPend (void)
Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.

Function Documentation

__STATIC_INLINE void LL_LPM_DisableEventOnPend ( void )

Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.

Reference Manual to LL API cross reference:
SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
Return values:
None

Definition at line 369 of file stm32wbxx_ll_cortex.h.

__STATIC_INLINE void LL_LPM_DisableSleepOnExit ( void )

Do not sleep when returning to Thread mode.

Reference Manual to LL API cross reference:
SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
Return values:
None

Definition at line 345 of file stm32wbxx_ll_cortex.h.

__STATIC_INLINE void LL_LPM_EnableDeepSleep ( void )

Processor uses deep sleep as its low power mode.

Reference Manual to LL API cross reference:
SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
Return values:
None

Definition at line 321 of file stm32wbxx_ll_cortex.h.

__STATIC_INLINE void LL_LPM_EnableEventOnPend ( void )

Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.

Reference Manual to LL API cross reference:
SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
Return values:
None

Definition at line 357 of file stm32wbxx_ll_cortex.h.

__STATIC_INLINE void LL_LPM_EnableSleep ( void )

Processor uses sleep as its low power mode.

Reference Manual to LL API cross reference:
SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
Return values:
None

Definition at line 310 of file stm32wbxx_ll_cortex.h.

__STATIC_INLINE void LL_LPM_EnableSleepOnExit ( void )

Configures sleep-on-exit when returning from Handler mode to Thread mode.

Note:
Setting this bit to 1 enables an interrupt-driven application to avoid returning to an empty main application.
Reference Manual to LL API cross reference:
SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
Return values:
None

Definition at line 334 of file stm32wbxx_ll_cortex.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: HANDLER

Functions
HANDLER
CORTEX Exported Functions

Functions

__STATIC_INLINE void | LL_HANDLER_EnableFault (uint32_t Fault)
Enable a fault in System handler control register (SHCSR)
__STATIC_INLINE void | LL_HANDLER_DisableFault (uint32_t Fault)
Disable a fault in System handler control register (SHCSR)

Function Documentation

__STATIC_INLINE void LL_HANDLER_DisableFault ( uint32_t Fault )

Disable a fault in System handler control register (SHCSR)

Reference Manual to LL API cross reference:
SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
Parameters:
Fault This parameter can be a combination of the following values:
  • LL_HANDLER_FAULT_USG
  • LL_HANDLER_FAULT_BUS
  • LL_HANDLER_FAULT_MEM
Return values:
None

Definition at line 407 of file stm32wbxx_ll_cortex.h.

__STATIC_INLINE void LL_HANDLER_EnableFault ( uint32_t Fault )

Enable a fault in System handler control register (SHCSR)

Reference Manual to LL API cross reference:
SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
Parameters:
Fault This parameter can be a combination of the following values:
  • LL_HANDLER_FAULT_USG
  • LL_HANDLER_FAULT_BUS
  • LL_HANDLER_FAULT_MEM
Return values:
None

Definition at line 392 of file stm32wbxx_ll_cortex.h.

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STM32WB55xx HAL User Manual: MCU INFO

Functions
MCU INFO
CORTEX Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_CPUID_GetImplementer (void)
Get Implementer code.
__STATIC_INLINE uint32_t | LL_CPUID_GetVariant (void)
Get Variant number (The r value in the rnpn product revision identifier)
__STATIC_INLINE uint32_t | LL_CPUID_GetConstant (void)
Get Constant number.
__STATIC_INLINE uint32_t | LL_CPUID_GetParNo (void)
Get Part number.
__STATIC_INLINE uint32_t | LL_CPUID_GetRevision (void)
Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)

Function Documentation

__STATIC_INLINE uint32_t LL_CPUID_GetConstant ( void )

Get Constant number.

Reference Manual to LL API cross reference:
SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
Return values:
Value should be equal to 0xF for Cortex-M4 devices

Definition at line 446 of file stm32wbxx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_CPUID_GetImplementer ( void )

Get Implementer code.

Reference Manual to LL API cross reference:
SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
Return values:
Value should be equal to 0x41 for ARM

Definition at line 426 of file stm32wbxx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_CPUID_GetParNo ( void )

Get Part number.

Reference Manual to LL API cross reference:
SCB_CPUID PARTNO LL_CPUID_GetParNo
Return values:
Value should be equal to 0xC24 for Cortex-M4

Definition at line 456 of file stm32wbxx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_CPUID_GetRevision ( void )

Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)

Reference Manual to LL API cross reference:
SCB_CPUID REVISION LL_CPUID_GetRevision
Return values:
Value between 0 and 255 (0x1: patch 1)

Definition at line 466 of file stm32wbxx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_CPUID_GetVariant ( void )

Get Variant number (The r value in the rnpn product revision identifier)

Reference Manual to LL API cross reference:
SCB_CPUID VARIANT LL_CPUID_GetVariant
Return values:
Value between 0 and 255 (0x0: revision 0)

Definition at line 436 of file stm32wbxx_ll_cortex.h.

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STM32WB55xx HAL User Manual: MPU

Functions
MPU
CORTEX Exported Functions

Functions

__STATIC_INLINE void | LL_MPU_Enable (uint32_t Options)
Enable MPU with input options.
__STATIC_INLINE void | LL_MPU_Disable (void)
Disable MPU.
__STATIC_INLINE uint32_t | LL_MPU_IsEnabled (void)
Check if MPU is enabled or not.
__STATIC_INLINE void | LL_MPU_EnableRegion (uint32_t Region)
Enable a MPU region.
__STATIC_INLINE void | LL_MPU_ConfigRegion (uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
Configure and enable a region.
__STATIC_INLINE void | LL_MPU_DisableRegion (uint32_t Region)
Disable a region.

Function Documentation

__STATIC_INLINE void LL_MPU_ConfigRegion | ( | uint32_t | Region,
 |  | uint32_t | SubRegionDisable,
 |  | uint32_t | Address,
 |  | uint32_t | Attributes
 | ) |  |

Configure and enable a region.

Reference Manual to LL API cross reference:
MPU_RNR REGION LL_MPU_ConfigRegion
MPU_RBAR REGION LL_MPU_ConfigRegion
MPU_RBAR ADDR LL_MPU_ConfigRegion
MPU_RASR XN LL_MPU_ConfigRegion
MPU_RASR AP LL_MPU_ConfigRegion
MPU_RASR S LL_MPU_ConfigRegion
MPU_RASR C LL_MPU_ConfigRegion
MPU_RASR B LL_MPU_ConfigRegion
MPU_RASR SIZE LL_MPU_ConfigRegion
Parameters:
Region This parameter can be one of the following values:
  • LL_MPU_REGION_NUMBER0
  • LL_MPU_REGION_NUMBER1
  • LL_MPU_REGION_NUMBER2
  • LL_MPU_REGION_NUMBER3
  • LL_MPU_REGION_NUMBER4
  • LL_MPU_REGION_NUMBER5
  • LL_MPU_REGION_NUMBER6
  • LL_MPU_REGION_NUMBER7
Address | Value of region base address
SubRegionDisable | Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
Attributes This parameter can be a combination of the following values:
  • LL_MPU_REGION_SIZE_32B or LL_MPU_REGION_SIZE_64B or LL_MPU_REGION_SIZE_128B or LL_MPU_REGION_SIZE_256B or LL_MPU_REGION_SIZE_512B or LL_MPU_REGION_SIZE_1KB or LL_MPU_REGION_SIZE_2KB or LL_MPU_REGION_SIZE_4KB or LL_MPU_REGION_SIZE_8KB or LL_MPU_REGION_SIZE_16KB or LL_MPU_REGION_SIZE_32KB or LL_MPU_REGION_SIZE_64KB or LL_MPU_REGION_SIZE_128KB or LL_MPU_REGION_SIZE_256KB or LL_MPU_REGION_SIZE_512KB or LL_MPU_REGION_SIZE_1MB or LL_MPU_REGION_SIZE_2MB or LL_MPU_REGION_SIZE_4MB or LL_MPU_REGION_SIZE_8MB or LL_MPU_REGION_SIZE_16MB or LL_MPU_REGION_SIZE_32MB or LL_MPU_REGION_SIZE_64MB or LL_MPU_REGION_SIZE_128MB or LL_MPU_REGION_SIZE_256MB or LL_MPU_REGION_SIZE_512MB or LL_MPU_REGION_SIZE_1GB or LL_MPU_REGION_SIZE_2GB or LL_MPU_REGION_SIZE_4GB
  • LL_MPU_REGION_NO_ACCESS or LL_MPU_REGION_PRIV_RW or LL_MPU_REGION_PRIV_RW_URO or LL_MPU_REGION_FULL_ACCESS or LL_MPU_REGION_PRIV_RO or LL_MPU_REGION_PRIV_RO_URO
  • LL_MPU_TEX_LEVEL0 or LL_MPU_TEX_LEVEL1 or LL_MPU_TEX_LEVEL2 or LL_MPU_TEX_LEVEL4
  • LL_MPU_INSTRUCTION_ACCESS_ENABLE or LL_MPU_INSTRUCTION_ACCESS_DISABLE
  • LL_MPU_ACCESS_SHAREABLE or LL_MPU_ACCESS_NOT_SHAREABLE
  • LL_MPU_ACCESS_CACHEABLE or LL_MPU_ACCESS_NOT_CACHEABLE
  • LL_MPU_ACCESS_BUFFERABLE or LL_MPU_ACCESS_NOT_BUFFERABLE
Return values:
None

Definition at line 583 of file stm32wbxx_ll_cortex.h.

__STATIC_INLINE void LL_MPU_Disable ( void )

Disable MPU.

Reference Manual to LL API cross reference:
MPU_CTRL ENABLE LL_MPU_Disable
Return values:
None

Definition at line 505 of file stm32wbxx_ll_cortex.h.

__STATIC_INLINE void LL_MPU_DisableRegion ( uint32_t Region )

Disable a region.

Reference Manual to LL API cross reference:
MPU_RNR REGION LL_MPU_DisableRegion
MPU_RASR ENABLE LL_MPU_DisableRegion
Parameters:
Region This parameter can be one of the following values:
  • LL_MPU_REGION_NUMBER0
  • LL_MPU_REGION_NUMBER1
  • LL_MPU_REGION_NUMBER2
  • LL_MPU_REGION_NUMBER3
  • LL_MPU_REGION_NUMBER4
  • LL_MPU_REGION_NUMBER5
  • LL_MPU_REGION_NUMBER6
  • LL_MPU_REGION_NUMBER7
Return values:
None

Definition at line 608 of file stm32wbxx_ll_cortex.h.

__STATIC_INLINE void LL_MPU_Enable ( uint32_t Options )

Enable MPU with input options.

Reference Manual to LL API cross reference:
MPU_CTRL ENABLE LL_MPU_Enable
Parameters:
Options This parameter can be one of the following values:
  • LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
  • LL_MPU_CTRL_HARDFAULT_NMI
  • LL_MPU_CTRL_PRIVILEGED_DEFAULT
  • LL_MPU_CTRL_HFNMI_PRIVDEF
Return values:
None

Definition at line 490 of file stm32wbxx_ll_cortex.h.

__STATIC_INLINE void LL_MPU_EnableRegion ( uint32_t Region )

Enable a MPU region.

Reference Manual to LL API cross reference:
MPU_RASR ENABLE LL_MPU_EnableRegion
Parameters:
Region This parameter can be one of the following values:
  • LL_MPU_REGION_NUMBER0
  • LL_MPU_REGION_NUMBER1
  • LL_MPU_REGION_NUMBER2
  • LL_MPU_REGION_NUMBER3
  • LL_MPU_REGION_NUMBER4
  • LL_MPU_REGION_NUMBER5
  • LL_MPU_REGION_NUMBER6
  • LL_MPU_REGION_NUMBER7
Return values:
None

Definition at line 537 of file stm32wbxx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_MPU_IsEnabled ( void )

Check if MPU is enabled or not.

Reference Manual to LL API cross reference:
MPU_CTRL ENABLE LL_MPU_IsEnabled
Return values:
State of bit (1 or 0).

Definition at line 518 of file stm32wbxx_ll_cortex.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CRC

Modules
CRC
STM32WBxx_LL_Driver

Modules

CRC Exported Constants
CRC Exported Macros
CRC Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for CRC registers.

Register | Bit | Function
CR | POLYSIZE | LL_CRC_GetPolynomialSize
 |  | LL_CRC_SetPolynomialSize
 | RESET | LL_CRC_ResetCRCCalculationUnit
 | REV_IN | LL_CRC_GetInputDataReverseMode
 |  | LL_CRC_SetInputDataReverseMode
 | REV_OUT | LL_CRC_GetOutputDataReverseMode
 |  | LL_CRC_SetOutputDataReverseMode
DR | DR | LL_CRC_FeedData16
 |  | LL_CRC_FeedData32
 |  | LL_CRC_FeedData8
 |  | LL_CRC_ReadData16
 |  | LL_CRC_ReadData32
 |  | LL_CRC_ReadData7
 |  | LL_CRC_ReadData8
IDR | IDR | LL_CRC_Read_IDR
 |  | LL_CRC_Write_IDR
INIT | INIT | LL_CRC_GetInitialData
 |  | LL_CRC_SetInitialData
POL | POL | LL_CRC_GetPolynomialCoef
 |  | LL_CRC_SetPolynomialCoef
Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Polynomial length

Defines
Polynomial length
CRC Exported Constants

Defines

#define | LL_CRC_POLYLENGTH_32B 0x00000000U
#define | LL_CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0
#define | LL_CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1
#define | LL_CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0)

Define Documentation

#define LL_CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0

16 bits Polynomial size

Definition at line 56 of file stm32wbxx_ll_crc.h.

#define LL_CRC_POLYLENGTH_32B 0x00000000U

32 bits Polynomial size

Definition at line 55 of file stm32wbxx_ll_crc.h.

#define LL_CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0)

7 bits Polynomial size

Definition at line 58 of file stm32wbxx_ll_crc.h.

#define LL_CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1

8 bits Polynomial size

Definition at line 57 of file stm32wbxx_ll_crc.h.

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STM32WB55xx HAL User Manual: Input Data Reverse

Defines
Input Data Reverse
CRC Exported Constants

Defines

#define | LL_CRC_INDATA_REVERSE_NONE 0x00000000U
#define | LL_CRC_INDATA_REVERSE_BYTE CRC_CR_REV_IN_0
#define | LL_CRC_INDATA_REVERSE_HALFWORD CRC_CR_REV_IN_1
#define | LL_CRC_INDATA_REVERSE_WORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0)

Define Documentation

#define LL_CRC_INDATA_REVERSE_BYTE CRC_CR_REV_IN_0

Input Data bit reversal done by byte

Definition at line 67 of file stm32wbxx_ll_crc.h.

#define LL_CRC_INDATA_REVERSE_HALFWORD CRC_CR_REV_IN_1

Input Data bit reversal done by half-word

Definition at line 68 of file stm32wbxx_ll_crc.h.

#define LL_CRC_INDATA_REVERSE_NONE 0x00000000U

Input Data bit order not affected

Definition at line 66 of file stm32wbxx_ll_crc.h.

#define LL_CRC_INDATA_REVERSE_WORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0)

Input Data bit reversal done by word

Definition at line 69 of file stm32wbxx_ll_crc.h.

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STM32WB55xx HAL User Manual: Output Data Reverse

Defines
Output Data Reverse
CRC Exported Constants

Defines

#define | LL_CRC_OUTDATA_REVERSE_NONE 0x00000000U
#define | LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT

Define Documentation

#define LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT

Output Data bit reversal done by bit

Definition at line 78 of file stm32wbxx_ll_crc.h.

#define LL_CRC_OUTDATA_REVERSE_NONE 0x00000000U

Output Data bit order not affected

Definition at line 77 of file stm32wbxx_ll_crc.h.

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STM32WB55xx HAL User Manual: Default CRC generating polynomial value

Defines
Default CRC generating polynomial value
CRC Exported Constants

Normal representation of this polynomial value is X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 . More...

Defines

#define LL_CRC_DEFAULT_CRC32_POLY 0x04C11DB7U

Detailed Description

Normal representation of this polynomial value is X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 .

Define Documentation

#define LL_CRC_DEFAULT_CRC32_POLY 0x04C11DB7U

Default CRC generating polynomial value

Definition at line 88 of file stm32wbxx_ll_crc.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Default CRC computation initialization value

Defines
Default CRC computation initialization value
CRC Exported Constants

Defines

#define LL_CRC_DEFAULT_CRC_INITVALUE 0xFFFFFFFFU

Define Documentation

#define LL_CRC_DEFAULT_CRC_INITVALUE 0xFFFFFFFFU

Default CRC computation initialization value

Definition at line 96 of file stm32wbxx_ll_crc.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
CRC Exported Macros

Defines

#define | LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__)
Write a value in CRC register.
#define | LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in CRC register.

Define Documentation

#define LL_CRC_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in CRC register.

Parameters:
__INSTANCE__ | CRC Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 129 of file stm32wbxx_ll_crc.h.

#define LL_CRC_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, __VALUE__)

Write a value in CRC register.

Parameters:
__INSTANCE__ | CRC Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 121 of file stm32wbxx_ll_crc.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CRC Configuration functions

Functions
CRC Configuration functions
CRC Exported Functions

Functions

__STATIC_INLINE void | LL_CRC_ResetCRCCalculationUnit (CRC_TypeDef *CRCx)
Reset the CRC calculation unit.
__STATIC_INLINE void | LL_CRC_SetPolynomialSize (CRC_TypeDef *CRCx, uint32_t PolySize)
Configure size of the polynomial.
__STATIC_INLINE uint32_t | LL_CRC_GetPolynomialSize (CRC_TypeDef *CRCx)
Return size of the polynomial.
__STATIC_INLINE void | LL_CRC_SetInputDataReverseMode (CRC_TypeDef *CRCx, uint32_t ReverseMode)
Configure the reversal of the bit order of the input data.
__STATIC_INLINE uint32_t | LL_CRC_GetInputDataReverseMode (CRC_TypeDef *CRCx)
Return type of reversal for input data bit order.
__STATIC_INLINE void | LL_CRC_SetOutputDataReverseMode (CRC_TypeDef *CRCx, uint32_t ReverseMode)
Configure the reversal of the bit order of the Output data.
__STATIC_INLINE uint32_t | LL_CRC_GetOutputDataReverseMode (CRC_TypeDef *CRCx)
Configure the reversal of the bit order of the Output data.
__STATIC_INLINE void | LL_CRC_SetInitialData (CRC_TypeDef *CRCx, uint32_t InitCrc)
Initialize the Programmable initial CRC value.
__STATIC_INLINE uint32_t | LL_CRC_GetInitialData (CRC_TypeDef *CRCx)
Return current Initial CRC value.
__STATIC_INLINE void | LL_CRC_SetPolynomialCoef (CRC_TypeDef *CRCx, uint32_t PolynomCoef)
Initialize the Programmable polynomial value (coefficients of the polynomial to be used for CRC calculation).
__STATIC_INLINE uint32_t | LL_CRC_GetPolynomialCoef (CRC_TypeDef *CRCx)
Return current Programmable polynomial value.

Function Documentation

__STATIC_INLINE uint32_t LL_CRC_GetInitialData ( CRC_TypeDef * CRCx )

Return current Initial CRC value.

Note:
If the CRC size is less than 32 bits, the least significant bits are used to read the correct value
Reference Manual to LL API cross reference:
INIT INIT LL_CRC_GetInitialData
Parameters:
CRCx CRC Instance
Return values:
Value programmed in Programmable initial CRC value register

Definition at line 274 of file stm32wbxx_ll_crc.h.

__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode ( CRC_TypeDef * CRCx )

Return type of reversal for input data bit order.

Reference Manual to LL API cross reference:
CR REV_IN LL_CRC_GetInputDataReverseMode
Parameters:
CRCx CRC Instance
Return values:
Returned value can be one of the following values:
  • LL_CRC_INDATA_REVERSE_NONE
  • LL_CRC_INDATA_REVERSE_BYTE
  • LL_CRC_INDATA_REVERSE_HALFWORD
  • LL_CRC_INDATA_REVERSE_WORD

Definition at line 219 of file stm32wbxx_ll_crc.h.

__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode ( CRC_TypeDef * CRCx )

Configure the reversal of the bit order of the Output data.

Reference Manual to LL API cross reference:
CR REV_OUT LL_CRC_GetOutputDataReverseMode
Parameters:
CRCx CRC Instance
Return values:
Returned value can be one of the following values:
  • LL_CRC_OUTDATA_REVERSE_NONE
  • LL_CRC_OUTDATA_REVERSE_BIT

Definition at line 246 of file stm32wbxx_ll_crc.h.

__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef ( CRC_TypeDef * CRCx )

Return current Programmable polynomial value.

Note:
Please check Reference Manual and existing Errata Sheets, regarding possible limitations for Polynomial values usage. For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
Reference Manual to LL API cross reference:
POL POL LL_CRC_GetPolynomialCoef
Parameters:
CRCx CRC Instance
Return values:
Value programmed in Programmable Polynomial value register

Definition at line 305 of file stm32wbxx_ll_crc.h.

__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize ( CRC_TypeDef * CRCx )

Return size of the polynomial.

Reference Manual to LL API cross reference:
CR POLYSIZE LL_CRC_GetPolynomialSize
Parameters:
CRCx CRC Instance
Return values:
Returned value can be one of the following values:
  • LL_CRC_POLYLENGTH_32B
  • LL_CRC_POLYLENGTH_16B
  • LL_CRC_POLYLENGTH_8B
  • LL_CRC_POLYLENGTH_7B

Definition at line 188 of file stm32wbxx_ll_crc.h.

__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit ( CRC_TypeDef * CRCx )

Reset the CRC calculation unit.

Note:
If Programmable Initial CRC value feature is available, also set the Data Register to the value stored in the CRC_INIT register, otherwise, reset Data Register to its default value.
Reference Manual to LL API cross reference:
CR RESET LL_CRC_ResetCRCCalculationUnit
Parameters:
CRCx CRC Instance
Return values:
None

Definition at line 157 of file stm32wbxx_ll_crc.h.

__STATIC_INLINE void LL_CRC_SetInitialData | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | InitCrc
 | ) |  |

Initialize the Programmable initial CRC value.

Note:
If the CRC size is less than 32 bits, the least significant bits are used to write the correct value
LL_CRC_DEFAULT_CRC_INITVALUE could be used as value for InitCrc parameter.
Reference Manual to LL API cross reference:
INIT INIT LL_CRC_SetInitialData
Parameters:
CRCx | CRC Instance
InitCrc | Value to be programmed in Programmable initial CRC value register
Return values:
None

Definition at line 261 of file stm32wbxx_ll_crc.h.

__STATIC_INLINE void LL_CRC_SetInputDataReverseMode | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | ReverseMode
 | ) |  |

Configure the reversal of the bit order of the input data.

Reference Manual to LL API cross reference:
CR REV_IN LL_CRC_SetInputDataReverseMode
Parameters:
CRCx CRC Instance
ReverseMode This parameter can be one of the following values:
  • LL_CRC_INDATA_REVERSE_NONE
  • LL_CRC_INDATA_REVERSE_BYTE
  • LL_CRC_INDATA_REVERSE_HALFWORD
  • LL_CRC_INDATA_REVERSE_WORD
Return values:
None

Definition at line 204 of file stm32wbxx_ll_crc.h.

__STATIC_INLINE void LL_CRC_SetOutputDataReverseMode | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | ReverseMode
 | ) |  |

Configure the reversal of the bit order of the Output data.

Reference Manual to LL API cross reference:
CR REV_OUT LL_CRC_SetOutputDataReverseMode
Parameters:
CRCx CRC Instance
ReverseMode This parameter can be one of the following values:
  • LL_CRC_OUTDATA_REVERSE_NONE
  • LL_CRC_OUTDATA_REVERSE_BIT
Return values:
None

Definition at line 233 of file stm32wbxx_ll_crc.h.

__STATIC_INLINE void LL_CRC_SetPolynomialCoef | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | PolynomCoef
 | ) |  |

Initialize the Programmable polynomial value (coefficients of the polynomial to be used for CRC calculation).

Note:
LL_CRC_DEFAULT_CRC32_POLY could be used as value for PolynomCoef parameter.
Please check Reference Manual and existing Errata Sheets, regarding possible limitations for Polynomial values usage. For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
Reference Manual to LL API cross reference:
POL POL LL_CRC_SetPolynomialCoef
Parameters:
CRCx | CRC Instance
PolynomCoef | Value to be programmed in Programmable Polynomial value register
Return values:
None

Definition at line 291 of file stm32wbxx_ll_crc.h.

__STATIC_INLINE void LL_CRC_SetPolynomialSize | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | PolySize
 | ) |  |

Configure size of the polynomial.

Reference Manual to LL API cross reference:
CR POLYSIZE LL_CRC_SetPolynomialSize
Parameters:
CRCx CRC Instance
PolySize This parameter can be one of the following values:
  • LL_CRC_POLYLENGTH_32B
  • LL_CRC_POLYLENGTH_16B
  • LL_CRC_POLYLENGTH_8B
  • LL_CRC_POLYLENGTH_7B
Return values:
None

Definition at line 173 of file stm32wbxx_ll_crc.h.

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STM32WB55xx HAL User Manual: Data_Management

Functions
Data_Management
CRC Exported Functions

Functions

__STATIC_INLINE void | LL_CRC_FeedData32 (CRC_TypeDef *CRCx, uint32_t InData)
Write given 32-bit data to the CRC calculator.
__STATIC_INLINE void | LL_CRC_FeedData16 (CRC_TypeDef *CRCx, uint16_t InData)
Write given 16-bit data to the CRC calculator.
__STATIC_INLINE void | LL_CRC_FeedData8 (CRC_TypeDef *CRCx, uint8_t InData)
Write given 8-bit data to the CRC calculator.
__STATIC_INLINE uint32_t | LL_CRC_ReadData32 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint16_t | LL_CRC_ReadData16 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint8_t | LL_CRC_ReadData8 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint8_t | LL_CRC_ReadData7 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint32_t | LL_CRC_Read_IDR (CRC_TypeDef *CRCx)
Return data stored in the Independent Data(IDR) register.
__STATIC_INLINE void | LL_CRC_Write_IDR (CRC_TypeDef *CRCx, uint32_t InData)
Store data in the Independent Data(IDR) register.

Function Documentation

__STATIC_INLINE void LL_CRC_FeedData16 | ( | CRC_TypeDef * | CRCx,
 |  | uint16_t | InData
 | ) |  |

Write given 16-bit data to the CRC calculator.

Reference Manual to LL API cross reference:
DR DR LL_CRC_FeedData16
Parameters:
CRCx | CRC Instance
InData | 16 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFF
Return values:
None

Definition at line 337 of file stm32wbxx_ll_crc.h.

__STATIC_INLINE void LL_CRC_FeedData32 | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | InData
 | ) |  |

Write given 32-bit data to the CRC calculator.

Reference Manual to LL API cross reference:
DR DR LL_CRC_FeedData32
Parameters:
CRCx | CRC Instance
InData | value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
Return values:
None

Definition at line 325 of file stm32wbxx_ll_crc.h.

__STATIC_INLINE void LL_CRC_FeedData8 | ( | CRC_TypeDef * | CRCx,
 |  | uint8_t | InData
 | ) |  |

Write given 8-bit data to the CRC calculator.

Reference Manual to LL API cross reference:
DR DR LL_CRC_FeedData8
Parameters:
CRCx | CRC Instance
InData | 8 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFF
Return values:
None

Definition at line 352 of file stm32wbxx_ll_crc.h.

__STATIC_INLINE uint32_t LL_CRC_Read_IDR ( CRC_TypeDef * CRCx )

Return data stored in the Independent Data(IDR) register.

Note:
This register can be used as a temporary storage location for one 32-bit long data.
Reference Manual to LL API cross reference:
IDR IDR LL_CRC_Read_IDR
Parameters:
CRCx CRC Instance
Return values:
Value stored in CRC_IDR register (General-purpose 32-bit data register).

Definition at line 411 of file stm32wbxx_ll_crc.h.

__STATIC_INLINE uint16_t LL_CRC_ReadData16 ( CRC_TypeDef * CRCx )

Return current CRC calculation result.

16 bits value is returned.

Note:
This function is expected to be used in a 16 bits CRC polynomial size context.
Reference Manual to LL API cross reference:
DR DR LL_CRC_ReadData16
Parameters:
CRCx CRC Instance
Return values:
Current CRC calculation result as stored in CRC_DR register (16 bits).

Definition at line 375 of file stm32wbxx_ll_crc.h.

__STATIC_INLINE uint32_t LL_CRC_ReadData32 ( CRC_TypeDef * CRCx )

Return current CRC calculation result.

32 bits value is returned.

Reference Manual to LL API cross reference:
DR DR LL_CRC_ReadData32
Parameters:
CRCx CRC Instance
Return values:
Current CRC calculation result as stored in CRC_DR register (32 bits).

Definition at line 363 of file stm32wbxx_ll_crc.h.

__STATIC_INLINE uint8_t LL_CRC_ReadData7 ( CRC_TypeDef * CRCx )

Return current CRC calculation result.

7 bits value is returned.

Note:
This function is expected to be used in a 7 bits CRC polynomial size context.
Reference Manual to LL API cross reference:
DR DR LL_CRC_ReadData7
Parameters:
CRCx CRC Instance
Return values:
Current CRC calculation result as stored in CRC_DR register (7 bits).

Definition at line 399 of file stm32wbxx_ll_crc.h.

__STATIC_INLINE uint8_t LL_CRC_ReadData8 ( CRC_TypeDef * CRCx )

Return current CRC calculation result.

8 bits value is returned.

Note:
This function is expected to be used in a 8 bits CRC polynomial size context.
Reference Manual to LL API cross reference:
DR DR LL_CRC_ReadData8
Parameters:
CRCx CRC Instance
Return values:
Current CRC calculation result as stored in CRC_DR register (8 bits).

Definition at line 387 of file stm32wbxx_ll_crc.h.

__STATIC_INLINE void LL_CRC_Write_IDR | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | InData
 | ) |  |

Store data in the Independent Data(IDR) register.

Note:
This register can be used as a temporary storage location for one 32-bit long data.
Reference Manual to LL API cross reference:
IDR IDR LL_CRC_Write_IDR
Parameters:
CRCx | CRC Instance
InData | value to be stored in CRC_IDR register (32-bit) between Min_Data=0 and Max_Data=0xFFFFFFFF
Return values:
None

Definition at line 424 of file stm32wbxx_ll_crc.h.

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STM32WB55xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CRC Exported Functions

Functions

ErrorStatus LL_CRC_DeInit (CRC_TypeDef *CRCx)
De-initialize CRC registers (Registers restored to their default values).

Function Documentation

ErrorStatus LL_CRC_DeInit ( CRC_TypeDef * CRCx )

De-initialize CRC registers (Registers restored to their default values).

Parameters:
CRCx CRC Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: CRC registers are de-initialized
  • ERROR: CRC registers are not de-initialized

Definition at line 63 of file stm32wbxx_ll_crc.c.

References assert_param, LL_AHB1_GRP1_ForceReset(), LL_AHB1_GRP1_PERIPH_CRC, and LL_AHB1_GRP1_ReleaseReset().

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STM32WB55xx HAL User Manual: CRS

Modules
CRS
STM32WBxx_LL_Driver

Modules

CRS Private Constants
CRS Exported Constants
CRS Exported Macros
CRS Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for CRS registers.

Register | Bit | Function
CFGR | FELIM | LL_CRS_ConfigSynchronization
 |  | LL_CRS_GetFreqErrorLimit
 |  | LL_CRS_SetFreqErrorLimit
 | RELOAD | LL_CRS_ConfigSynchronization
 |  | LL_CRS_GetReloadCounter
 |  | LL_CRS_SetReloadCounter
 | SYNCDIV | LL_CRS_ConfigSynchronization
 |  | LL_CRS_GetSyncDivider
 |  | LL_CRS_SetSyncDivider
 | SYNCPOL | LL_CRS_ConfigSynchronization
 |  | LL_CRS_GetSyncPolarity
 |  | LL_CRS_SetSyncPolarity
 | SYNCSRC | LL_CRS_ConfigSynchronization
 |  | LL_CRS_GetSyncSignalSource
 |  | LL_CRS_SetSyncSignalSource
CR | AUTOTRIMEN | LL_CRS_DisableAutoTrimming
 |  | LL_CRS_EnableAutoTrimming
 |  | LL_CRS_IsEnabledAutoTrimming
 | CEN | LL_CRS_DisableFreqErrorCounter
 |  | LL_CRS_EnableFreqErrorCounter
 |  | LL_CRS_IsEnabledFreqErrorCounter
 | ERRIE | LL_CRS_DisableIT_ERR
 |  | LL_CRS_EnableIT_ERR
 |  | LL_CRS_IsEnabledIT_ERR
 | ESYNCIE | LL_CRS_DisableIT_ESYNC
 |  | LL_CRS_EnableIT_ESYNC
 |  | LL_CRS_IsEnabledIT_ESYNC
 | SWSYNC | LL_CRS_GenerateEvent_SWSYNC
 | SYNCOKIE | LL_CRS_DisableIT_SYNCOK
 |  | LL_CRS_EnableIT_SYNCOK
 |  | LL_CRS_IsEnabledIT_SYNCOK
 | SYNCWARNIE | LL_CRS_DisableIT_SYNCWARN
 |  | LL_CRS_EnableIT_SYNCWARN
 |  | LL_CRS_IsEnabledIT_SYNCWARN
 | TRIM | LL_CRS_ConfigSynchronization
 |  | LL_CRS_GetHSI48SmoothTrimming
 |  | LL_CRS_SetHSI48SmoothTrimming
ICR | ERRC | LL_CRS_ClearFlag_ERR
 | ESYNCC | LL_CRS_ClearFlag_ESYNC
 | SYNCOKC | LL_CRS_ClearFlag_SYNCOK
 | SYNCWARNC | LL_CRS_ClearFlag_SYNCWARN
ISR | ERRF | LL_CRS_IsActiveFlag_ERR
 | ESYNCF | LL_CRS_IsActiveFlag_ESYNC
 | FECAP | LL_CRS_GetFreqErrorCapture
 | FEDIR | LL_CRS_GetFreqErrorDirection
 | SYNCERR | LL_CRS_IsActiveFlag_SYNCERR
 | SYNCMISS | LL_CRS_IsActiveFlag_SYNCMISS
 | SYNCOKF | LL_CRS_IsActiveFlag_SYNCOK
 | SYNCWARNF | LL_CRS_IsActiveFlag_SYNCWARN
 | TRIMOVF | LL_CRS_IsActiveFlag_TRIMOVF
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STM32WB55xx HAL User Manual: CRS Private Constants

Defines
CRS Private Constants
CRS

Defines

#define | CRS_POSITION_TRIM (CRS_CR_TRIM_Pos) /* bit position in CR reg */
#define | CRS_POSITION_FECAP (CRS_ISR_FECAP_Pos) /* bit position in ISR reg */
#define | CRS_POSITION_FELIM (CRS_CFGR_FELIM_Pos) /* bit position in CFGR reg */

Define Documentation

#define CRS_POSITION_FECAP (CRS_ISR_FECAP_Pos) /* bit position in ISR reg */

Definition at line 51 of file stm32wbxx_ll_crs.h.

Referenced by LL_CRS_GetFreqErrorCapture().

#define CRS_POSITION_FELIM (CRS_CFGR_FELIM_Pos) /* bit position in CFGR reg */

Definition at line 52 of file stm32wbxx_ll_crs.h.

Referenced by LL_CRS_ConfigSynchronization(), LL_CRS_GetFreqErrorLimit(), and LL_CRS_SetFreqErrorLimit().

#define CRS_POSITION_TRIM (CRS_CR_TRIM_Pos) /* bit position in CR reg */

Definition at line 50 of file stm32wbxx_ll_crs.h.

Referenced by LL_CRS_GetHSI48SmoothTrimming(), and LL_CRS_SetHSI48SmoothTrimming().

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
CRS Exported Constants

Flags defines which can be used with LL_CRS_ReadReg function. More...

Defines

#define | LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF
#define | LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF
#define | LL_CRS_ISR_ERRF CRS_ISR_ERRF
#define | LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF
#define | LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR
#define | LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS
#define | LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF

Detailed Description

Flags defines which can be used with LL_CRS_ReadReg function.

Define Documentation

#define LL_CRS_ISR_ERRF CRS_ISR_ERRF

Definition at line 73 of file stm32wbxx_ll_crs.h.

#define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF

Definition at line 74 of file stm32wbxx_ll_crs.h.

#define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR

Definition at line 75 of file stm32wbxx_ll_crs.h.

#define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS

Definition at line 76 of file stm32wbxx_ll_crs.h.

#define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF

Definition at line 71 of file stm32wbxx_ll_crs.h.

#define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF

Definition at line 72 of file stm32wbxx_ll_crs.h.

#define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF

Definition at line 77 of file stm32wbxx_ll_crs.h.

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STM32WB55xx HAL User Manual: IT Defines

Defines
IT Defines
CRS Exported Constants

IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions. More...

Defines

#define | LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE
#define | LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE
#define | LL_CRS_CR_ERRIE CRS_CR_ERRIE
#define | LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE

Detailed Description

IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions.

Define Documentation

#define LL_CRS_CR_ERRIE CRS_CR_ERRIE

Definition at line 88 of file stm32wbxx_ll_crs.h.

#define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE

Definition at line 89 of file stm32wbxx_ll_crs.h.

#define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE

Definition at line 86 of file stm32wbxx_ll_crs.h.

#define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE

Definition at line 87 of file stm32wbxx_ll_crs.h.

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STM32WB55xx HAL User Manual: Synchronization Signal Divider

Defines
Synchronization Signal Divider
CRS Exported Constants

Defines

#define | LL_CRS_SYNC_DIV_1 0x00000000U
#define | LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0
#define | LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1
#define | LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0)
#define | LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2
#define | LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0)
#define | LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1)
#define | LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV

Define Documentation

#define LL_CRS_SYNC_DIV_1 0x00000000U

Synchro Signal not divided (default)

Definition at line 97 of file stm32wbxx_ll_crs.h.

#define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV

Synchro Signal divided by 128

Definition at line 104 of file stm32wbxx_ll_crs.h.

#define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2

Synchro Signal divided by 16

Definition at line 101 of file stm32wbxx_ll_crs.h.

#define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0

Synchro Signal divided by 2

Definition at line 98 of file stm32wbxx_ll_crs.h.

#define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0)

Synchro Signal divided by 32

Definition at line 102 of file stm32wbxx_ll_crs.h.

#define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1

Synchro Signal divided by 4

Definition at line 99 of file stm32wbxx_ll_crs.h.

#define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1)

Synchro Signal divided by 64

Definition at line 103 of file stm32wbxx_ll_crs.h.

#define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0)

Synchro Signal divided by 8

Definition at line 100 of file stm32wbxx_ll_crs.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Synchronization Signal Source

Defines
Synchronization Signal Source
CRS Exported Constants

Defines

#define | LL_CRS_SYNC_SOURCE_GPIO 0x00000000U
#define | LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0
#define | LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1

Define Documentation

#define LL_CRS_SYNC_SOURCE_GPIO 0x00000000U

Synchro Signal soucre GPIO

Definition at line 112 of file stm32wbxx_ll_crs.h.

#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0

Synchro Signal source LSE

Definition at line 113 of file stm32wbxx_ll_crs.h.

#define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1

Synchro Signal source USB SOF (default)

Definition at line 114 of file stm32wbxx_ll_crs.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Synchronization Signal Polarity

Defines
Synchronization Signal Polarity
CRS Exported Constants

Defines

#define | LL_CRS_SYNC_POLARITY_RISING 0x00000000U
#define | LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL

Define Documentation

#define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL

Synchro Active on falling edge

Definition at line 123 of file stm32wbxx_ll_crs.h.

#define LL_CRS_SYNC_POLARITY_RISING 0x00000000U

Synchro Active on rising edge (default)

Definition at line 122 of file stm32wbxx_ll_crs.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Frequency Error Direction

Defines
Frequency Error Direction
CRS Exported Constants

Defines

#define | LL_CRS_FREQ_ERROR_DIR_UP 0x00000000U
#define | LL_CRS_FREQ_ERROR_DIR_DOWN CRS_ISR_FEDIR

Define Documentation

#define LL_CRS_FREQ_ERROR_DIR_DOWN CRS_ISR_FEDIR

Downcounting direction, the actual frequency is below the target

Definition at line 132 of file stm32wbxx_ll_crs.h.

#define LL_CRS_FREQ_ERROR_DIR_UP 0x00000000U

Upcounting direction, the actual frequency is above the target

Definition at line 131 of file stm32wbxx_ll_crs.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Default Values

Defines
Default Values
CRS Exported Constants

Defines

#define | LL_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU
Reset value of the RELOAD field.
#define | LL_CRS_ERRORLIMIT_DEFAULT 0x00000022U
Reset value of Frequency error limit.
#define | LL_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U
Reset value of the HSI48 Calibration field.

Define Documentation

#define LL_CRS_ERRORLIMIT_DEFAULT 0x00000022U

Reset value of Frequency error limit.

Definition at line 150 of file stm32wbxx_ll_crs.h.

#define LL_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U

Reset value of the HSI48 Calibration field.

Note:
The default value is 32, which corresponds to the middle of the trimming interval. The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value corresponds to a higher output frequency

Definition at line 158 of file stm32wbxx_ll_crs.h.

#define LL_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU

Reset value of the RELOAD field.

Note:
The reset value of the RELOAD field corresponds to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB)

Definition at line 145 of file stm32wbxx_ll_crs.h.

Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
CRS Exported Macros

Defines

#define | LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in CRS register.
#define | LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in CRS register.

Define Documentation

#define LL_CRS_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in CRS register.

Parameters:
__INSTANCE__ | CRS Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 191 of file stm32wbxx_ll_crs.h.

#define LL_CRS_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in CRS register.

Parameters:
__INSTANCE__ | CRS Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 183 of file stm32wbxx_ll_crs.h.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Exported_Macros_Calculate_Reload

Defines
Exported_Macros_Calculate_Reload
CRS Exported Macros

Defines

#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
Macro to calculate reload value to be set in CRS register according to target and sync frequencies.

Define Documentation

#define __LL_CRS_CALC_CALCULATE_RELOADVALUE | ( | __FTARGET__,
 |  | __FSYNC__
 | ) | (((__FTARGET__) / (__FSYNC__)) - 1U)

Macro to calculate reload value to be set in CRS register according to target and sync frequencies.

Note:
The RELOAD value should be selected according to the ratio between the target frequency and the frequency of the synchronization source after prescaling. It is then decreased by one in order to reach the expected synchronization on the zero value. The formula is the following: RELOAD = (fTARGET / fSYNC) -1
Parameters:
__FTARGET__ | Target frequency (value in Hz)
__FSYNC__ | Synchronization signal frequency (value in Hz)
Return values:
Reload value (in Hz)

Definition at line 211 of file stm32wbxx_ll_crs.h.

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STM32WB55xx HAL User Manual: Configuration

Functions
Configuration
CRS Exported Functions

Functions

__STATIC_INLINE void | LL_CRS_EnableFreqErrorCounter (void)
Enable Frequency error counter.
__STATIC_INLINE void | LL_CRS_DisableFreqErrorCounter (void)
Disable Frequency error counter.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledFreqErrorCounter (void)
Check if Frequency error counter is enabled or not.
__STATIC_INLINE void | LL_CRS_EnableAutoTrimming (void)
Enable Automatic trimming counter.
__STATIC_INLINE void | LL_CRS_DisableAutoTrimming (void)
Disable Automatic trimming counter.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledAutoTrimming (void)
Check if Automatic trimming is enabled or not.
__STATIC_INLINE void | LL_CRS_SetHSI48SmoothTrimming (uint32_t Value)
Set HSI48 oscillator smooth trimming.
__STATIC_INLINE uint32_t | LL_CRS_GetHSI48SmoothTrimming (void)
Get HSI48 oscillator smooth trimming.
__STATIC_INLINE void | LL_CRS_SetReloadCounter (uint32_t Value)
Set counter reload value.
__STATIC_INLINE uint32_t | LL_CRS_GetReloadCounter (void)
Get counter reload value.
__STATIC_INLINE void | LL_CRS_SetFreqErrorLimit (uint32_t Value)
Set frequency error limit.
__STATIC_INLINE uint32_t | LL_CRS_GetFreqErrorLimit (void)
Get frequency error limit.
__STATIC_INLINE void | LL_CRS_SetSyncDivider (uint32_t Divider)
Set division factor for SYNC signal.
__STATIC_INLINE uint32_t | LL_CRS_GetSyncDivider (void)
Get division factor for SYNC signal.
__STATIC_INLINE void | LL_CRS_SetSyncSignalSource (uint32_t Source)
Set SYNC signal source.
__STATIC_INLINE uint32_t | LL_CRS_GetSyncSignalSource (void)
Get SYNC signal source.
__STATIC_INLINE void | LL_CRS_SetSyncPolarity (uint32_t Polarity)
Set input polarity for the SYNC signal source.
__STATIC_INLINE uint32_t | LL_CRS_GetSyncPolarity (void)
Get input polarity for the SYNC signal source.
__STATIC_INLINE void | LL_CRS_ConfigSynchronization (uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
Configure CRS for the synchronization.

Function Documentation

__STATIC_INLINE void LL_CRS_ConfigSynchronization | ( | uint32_t | HSI48CalibrationValue,
 |  | uint32_t | ErrorLimitValue,
 |  | uint32_t | ReloadValue,
 |  | uint32_t | Settings
 | ) |  |

Configure CRS for the synchronization.

Reference Manual to LL API cross reference:
CR TRIM LL_CRS_ConfigSynchronization
CFGR RELOAD LL_CRS_ConfigSynchronization
CFGR FELIM LL_CRS_ConfigSynchronization
CFGR SYNCDIV LL_CRS_ConfigSynchronization
CFGR SYNCSRC LL_CRS_ConfigSynchronization
CFGR SYNCPOL LL_CRS_ConfigSynchronization
Parameters:
HSI48CalibrationValue | a number between Min_Data = 0 and Max_Data = 63
ErrorLimitValue | a number between Min_Data = 0 and Max_Data = 0xFFFF
ReloadValue | a number between Min_Data = 0 and Max_Data = 255
Settings This parameter can be a combination of the following values:
  • LL_CRS_SYNC_DIV_1 or LL_CRS_SYNC_DIV_2 or LL_CRS_SYNC_DIV_4 or LL_CRS_SYNC_DIV_8 or LL_CRS_SYNC_DIV_16 or LL_CRS_SYNC_DIV_32 or LL_CRS_SYNC_DIV_64 or LL_CRS_SYNC_DIV_128
  • LL_CRS_SYNC_SOURCE_GPIO or LL_CRS_SYNC_SOURCE_LSE or LL_CRS_SYNC_SOURCE_USB
  • LL_CRS_SYNC_POLARITY_RISING or LL_CRS_SYNC_POLARITY_FALLING
Return values:
None

Definition at line 466 of file stm32wbxx_ll_crs.h.

References CRS_POSITION_FELIM.

__STATIC_INLINE void LL_CRS_DisableAutoTrimming ( void )

Disable Automatic trimming counter.

Reference Manual to LL API cross reference:
CR AUTOTRIMEN LL_CRS_DisableAutoTrimming
Return values:
None

Definition at line 276 of file stm32wbxx_ll_crs.h.

__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter ( void )

Disable Frequency error counter.

Reference Manual to LL API cross reference:
CR CEN LL_CRS_DisableFreqErrorCounter
Return values:
None

Definition at line 246 of file stm32wbxx_ll_crs.h.

__STATIC_INLINE void LL_CRS_EnableAutoTrimming ( void )

Enable Automatic trimming counter.

Reference Manual to LL API cross reference:
CR AUTOTRIMEN LL_CRS_EnableAutoTrimming
Return values:
None

Definition at line 266 of file stm32wbxx_ll_crs.h.

__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter ( void )

Enable Frequency error counter.

Note:
When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
Reference Manual to LL API cross reference:
CR CEN LL_CRS_EnableFreqErrorCounter
Return values:
None

Definition at line 236 of file stm32wbxx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit ( void )

Get frequency error limit.

Reference Manual to LL API cross reference:
CFGR FELIM LL_CRS_GetFreqErrorLimit
Return values:
A number between Min_Data = 0 and Max_Data = 255

Definition at line 354 of file stm32wbxx_ll_crs.h.

References CRS_POSITION_FELIM.

__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming ( void )

Get HSI48 oscillator smooth trimming.

Reference Manual to LL API cross reference:
CR TRIM LL_CRS_GetHSI48SmoothTrimming
Return values:
a number between Min_Data = 0 and Max_Data = 63

Definition at line 309 of file stm32wbxx_ll_crs.h.

References CRS_POSITION_TRIM.

Referenced by HAL_RCCEx_CRSGetSynchronizationInfo().

__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter ( void )

Get counter reload value.

Reference Manual to LL API cross reference:
CFGR RELOAD LL_CRS_GetReloadCounter
Return values:
a number between Min_Data = 0 and Max_Data = 0xFFFF

Definition at line 332 of file stm32wbxx_ll_crs.h.

Referenced by HAL_RCCEx_CRSGetSynchronizationInfo().

__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider ( void )

Get division factor for SYNC signal.

Reference Manual to LL API cross reference:
CFGR SYNCDIV LL_CRS_GetSyncDivider
Return values:
Returned value can be one of the following values:
  • LL_CRS_SYNC_DIV_1
  • LL_CRS_SYNC_DIV_2
  • LL_CRS_SYNC_DIV_4
  • LL_CRS_SYNC_DIV_8
  • LL_CRS_SYNC_DIV_16
  • LL_CRS_SYNC_DIV_32
  • LL_CRS_SYNC_DIV_64
  • LL_CRS_SYNC_DIV_128

Definition at line 391 of file stm32wbxx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity ( void )

Get input polarity for the SYNC signal source.

Reference Manual to LL API cross reference:
CFGR SYNCPOL LL_CRS_GetSyncPolarity
Return values:
Returned value can be one of the following values:
  • LL_CRS_SYNC_POLARITY_RISING
  • LL_CRS_SYNC_POLARITY_FALLING

Definition at line 443 of file stm32wbxx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource ( void )

Get SYNC signal source.

Reference Manual to LL API cross reference:
CFGR SYNCSRC LL_CRS_GetSyncSignalSource
Return values:
Returned value can be one of the following values:
  • LL_CRS_SYNC_SOURCE_GPIO
  • LL_CRS_SYNC_SOURCE_LSE
  • LL_CRS_SYNC_SOURCE_USB

Definition at line 418 of file stm32wbxx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming ( void )

Check if Automatic trimming is enabled or not.

Reference Manual to LL API cross reference:
CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming
Return values:
State of bit (1 or 0).

Definition at line 286 of file stm32wbxx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter ( void )

Check if Frequency error counter is enabled or not.

Reference Manual to LL API cross reference:
CR CEN LL_CRS_IsEnabledFreqErrorCounter
Return values:
State of bit (1 or 0).

Definition at line 256 of file stm32wbxx_ll_crs.h.

__STATIC_INLINE void LL_CRS_SetFreqErrorLimit ( uint32_t Value )

Set frequency error limit.

Reference Manual to LL API cross reference:
CFGR FELIM LL_CRS_SetFreqErrorLimit
Parameters:
Value a number between Min_Data = 0 and Max_Data = 255
Note:
Default value can be set thanks to LL_CRS_ERRORLIMIT_DEFAULT
Return values:
None

Definition at line 344 of file stm32wbxx_ll_crs.h.

References CRS_POSITION_FELIM.

__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming ( uint32_t Value )

Set HSI48 oscillator smooth trimming.

Note:
When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
Reference Manual to LL API cross reference:
CR TRIM LL_CRS_SetHSI48SmoothTrimming
Parameters:
Value a number between Min_Data = 0 and Max_Data = 63
Note:
Default value can be set thanks to LL_CRS_HSI48CALIBRATION_DEFAULT
Return values:
None

Definition at line 299 of file stm32wbxx_ll_crs.h.

References CRS_POSITION_TRIM.

__STATIC_INLINE void LL_CRS_SetReloadCounter ( uint32_t Value )

Set counter reload value.

Reference Manual to LL API cross reference:
CFGR RELOAD LL_CRS_SetReloadCounter
Parameters:
Value a number between Min_Data = 0 and Max_Data = 0xFFFF
Note:
Default value can be set thanks to LL_CRS_RELOADVALUE_DEFAULT Otherwise it can be calculated in using macro __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
Return values:
None

Definition at line 322 of file stm32wbxx_ll_crs.h.

__STATIC_INLINE void LL_CRS_SetSyncDivider ( uint32_t Divider )

Set division factor for SYNC signal.

Reference Manual to LL API cross reference:
CFGR SYNCDIV LL_CRS_SetSyncDivider
Parameters:
Divider This parameter can be one of the following values:
  • LL_CRS_SYNC_DIV_1
  • LL_CRS_SYNC_DIV_2
  • LL_CRS_SYNC_DIV_4
  • LL_CRS_SYNC_DIV_8
  • LL_CRS_SYNC_DIV_16
  • LL_CRS_SYNC_DIV_32
  • LL_CRS_SYNC_DIV_64
  • LL_CRS_SYNC_DIV_128
Return values:
None

Definition at line 373 of file stm32wbxx_ll_crs.h.

__STATIC_INLINE void LL_CRS_SetSyncPolarity ( uint32_t Polarity )

Set input polarity for the SYNC signal source.

Reference Manual to LL API cross reference:
CFGR SYNCPOL LL_CRS_SetSyncPolarity
Parameters:
Polarity This parameter can be one of the following values:
  • LL_CRS_SYNC_POLARITY_RISING
  • LL_CRS_SYNC_POLARITY_FALLING
Return values:
None

Definition at line 431 of file stm32wbxx_ll_crs.h.

__STATIC_INLINE void LL_CRS_SetSyncSignalSource ( uint32_t Source )

Set SYNC signal source.

Reference Manual to LL API cross reference:
CFGR SYNCSRC LL_CRS_SetSyncSignalSource
Parameters:
Source This parameter can be one of the following values:
  • LL_CRS_SYNC_SOURCE_GPIO
  • LL_CRS_SYNC_SOURCE_LSE
  • LL_CRS_SYNC_SOURCE_USB
Return values:
None

Definition at line 405 of file stm32wbxx_ll_crs.h.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CRS_Management

Functions
CRS_Management
CRS Exported Functions

Functions

__STATIC_INLINE void | LL_CRS_GenerateEvent_SWSYNC (void)
Generate software SYNC event.
__STATIC_INLINE uint32_t | LL_CRS_GetFreqErrorDirection (void)
Get the frequency error direction latched in the time of the last SYNC event.
__STATIC_INLINE uint32_t | LL_CRS_GetFreqErrorCapture (void)
Get the frequency error counter value latched in the time of the last SYNC event.

Function Documentation

__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC ( void )

Generate software SYNC event.

Reference Manual to LL API cross reference:
CR SWSYNC LL_CRS_GenerateEvent_SWSYNC
Return values:
None

Definition at line 487 of file stm32wbxx_ll_crs.h.

Referenced by HAL_RCCEx_CRSSoftwareSynchronizationGenerate().

__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture ( void )

Get the frequency error counter value latched in the time of the last SYNC event.

Reference Manual to LL API cross reference:
ISR FECAP LL_CRS_GetFreqErrorCapture
Return values:
A number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 510 of file stm32wbxx_ll_crs.h.

References CRS_POSITION_FECAP.

Referenced by HAL_RCCEx_CRSGetSynchronizationInfo().

__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection ( void )

Get the frequency error direction latched in the time of the last SYNC event.

Reference Manual to LL API cross reference:
ISR FEDIR LL_CRS_GetFreqErrorDirection
Return values:
Returned value can be one of the following values:
  • LL_CRS_FREQ_ERROR_DIR_UP
  • LL_CRS_FREQ_ERROR_DIR_DOWN

Definition at line 500 of file stm32wbxx_ll_crs.h.

Referenced by HAL_RCCEx_CRSGetSynchronizationInfo().

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FLAG_Management

Functions
FLAG_Management
CRS Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_SYNCOK (void)
Check if SYNC event OK signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_SYNCWARN (void)
Check if SYNC warning signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_ERR (void)
Check if Synchronization or trimming error signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_ESYNC (void)
Check if Expected SYNC signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_SYNCERR (void)
Check if SYNC error signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_SYNCMISS (void)
Check if SYNC missed error signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_TRIMOVF (void)
Check if Trimming overflow or underflow occurred or not.
__STATIC_INLINE void | LL_CRS_ClearFlag_SYNCOK (void)
Clear the SYNC event OK flag.
__STATIC_INLINE void | LL_CRS_ClearFlag_SYNCWARN (void)
Clear the SYNC warning flag.
__STATIC_INLINE void | LL_CRS_ClearFlag_ERR (void)
Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also the ERR flag.
__STATIC_INLINE void | LL_CRS_ClearFlag_ESYNC (void)
Clear Expected SYNC flag.

Function Documentation

__STATIC_INLINE void LL_CRS_ClearFlag_ERR ( void )

Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also the ERR flag.

Reference Manual to LL API cross reference:
ICR ERRC LL_CRS_ClearFlag_ERR
Return values:
None

Definition at line 619 of file stm32wbxx_ll_crs.h.

Referenced by HAL_RCCEx_CRS_IRQHandler().

__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC ( void )

Clear Expected SYNC flag.

Reference Manual to LL API cross reference:
ICR ESYNCC LL_CRS_ClearFlag_ESYNC
Return values:
None

Definition at line 629 of file stm32wbxx_ll_crs.h.

Referenced by HAL_RCCEx_CRS_IRQHandler().

__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK ( void )

Clear the SYNC event OK flag.

Reference Manual to LL API cross reference:
ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK
Return values:
None

Definition at line 598 of file stm32wbxx_ll_crs.h.

Referenced by HAL_RCCEx_CRS_IRQHandler().

__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN ( void )

Clear the SYNC warning flag.

Reference Manual to LL API cross reference:
ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN
Return values:
None

Definition at line 608 of file stm32wbxx_ll_crs.h.

Referenced by HAL_RCCEx_CRS_IRQHandler().

__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR ( void )

Check if Synchronization or trimming error signal occurred or not.

Reference Manual to LL API cross reference:
ISR ERRF LL_CRS_IsActiveFlag_ERR
Return values:
State of bit (1 or 0).

Definition at line 548 of file stm32wbxx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC ( void )

Check if Expected SYNC signal occurred or not.

Reference Manual to LL API cross reference:
ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC
Return values:
State of bit (1 or 0).

Definition at line 558 of file stm32wbxx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR ( void )

Check if SYNC error signal occurred or not.

Reference Manual to LL API cross reference:
ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR
Return values:
State of bit (1 or 0).

Definition at line 568 of file stm32wbxx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS ( void )

Check if SYNC missed error signal occurred or not.

Reference Manual to LL API cross reference:
ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS
Return values:
State of bit (1 or 0).

Definition at line 578 of file stm32wbxx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK ( void )

Check if SYNC event OK signal occurred or not.

Reference Manual to LL API cross reference:
ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK
Return values:
State of bit (1 or 0).

Definition at line 528 of file stm32wbxx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN ( void )

Check if SYNC warning signal occurred or not.

Reference Manual to LL API cross reference:
ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN
Return values:
State of bit (1 or 0).

Definition at line 538 of file stm32wbxx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF ( void )

Check if Trimming overflow or underflow occurred or not.

Reference Manual to LL API cross reference:
ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF
Return values:
State of bit (1 or 0).

Definition at line 588 of file stm32wbxx_ll_crs.h.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IT_Management

Functions
IT_Management
CRS Exported Functions

Functions

__STATIC_INLINE void | LL_CRS_EnableIT_SYNCOK (void)
Enable SYNC event OK interrupt.
__STATIC_INLINE void | LL_CRS_DisableIT_SYNCOK (void)
Disable SYNC event OK interrupt.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledIT_SYNCOK (void)
Check if SYNC event OK interrupt is enabled or not.
__STATIC_INLINE void | LL_CRS_EnableIT_SYNCWARN (void)
Enable SYNC warning interrupt.
__STATIC_INLINE void | LL_CRS_DisableIT_SYNCWARN (void)
Disable SYNC warning interrupt.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledIT_SYNCWARN (void)
Check if SYNC warning interrupt is enabled or not.
__STATIC_INLINE void | LL_CRS_EnableIT_ERR (void)
Enable Synchronization or trimming error interrupt.
__STATIC_INLINE void | LL_CRS_DisableIT_ERR (void)
Disable Synchronization or trimming error interrupt.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledIT_ERR (void)
Check if Synchronization or trimming error interrupt is enabled or not.
__STATIC_INLINE void | LL_CRS_EnableIT_ESYNC (void)
Enable Expected SYNC interrupt.
__STATIC_INLINE void | LL_CRS_DisableIT_ESYNC (void)
Disable Expected SYNC interrupt.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledIT_ESYNC (void)
Check if Expected SYNC interrupt is enabled or not.

Function Documentation

__STATIC_INLINE void LL_CRS_DisableIT_ERR ( void )

Disable Synchronization or trimming error interrupt.

Reference Manual to LL API cross reference:
CR ERRIE LL_CRS_DisableIT_ERR
Return values:
None

Definition at line 717 of file stm32wbxx_ll_crs.h.

__STATIC_INLINE void LL_CRS_DisableIT_ESYNC ( void )

Disable Expected SYNC interrupt.

Reference Manual to LL API cross reference:
CR ESYNCIE LL_CRS_DisableIT_ESYNC
Return values:
None

Definition at line 747 of file stm32wbxx_ll_crs.h.

__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK ( void )

Disable SYNC event OK interrupt.

Reference Manual to LL API cross reference:
CR SYNCOKIE LL_CRS_DisableIT_SYNCOK
Return values:
None

Definition at line 657 of file stm32wbxx_ll_crs.h.

__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN ( void )

Disable SYNC warning interrupt.

Reference Manual to LL API cross reference:
CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN
Return values:
None

Definition at line 687 of file stm32wbxx_ll_crs.h.

__STATIC_INLINE void LL_CRS_EnableIT_ERR ( void )

Enable Synchronization or trimming error interrupt.

Reference Manual to LL API cross reference:
CR ERRIE LL_CRS_EnableIT_ERR
Return values:
None

Definition at line 707 of file stm32wbxx_ll_crs.h.

__STATIC_INLINE void LL_CRS_EnableIT_ESYNC ( void )

Enable Expected SYNC interrupt.

Reference Manual to LL API cross reference:
CR ESYNCIE LL_CRS_EnableIT_ESYNC
Return values:
None

Definition at line 737 of file stm32wbxx_ll_crs.h.

__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK ( void )

Enable SYNC event OK interrupt.

Reference Manual to LL API cross reference:
CR SYNCOKIE LL_CRS_EnableIT_SYNCOK
Return values:
None

Definition at line 647 of file stm32wbxx_ll_crs.h.

__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN ( void )

Enable SYNC warning interrupt.

Reference Manual to LL API cross reference:
CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN
Return values:
None

Definition at line 677 of file stm32wbxx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR ( void )

Check if Synchronization or trimming error interrupt is enabled or not.

Reference Manual to LL API cross reference:
CR ERRIE LL_CRS_IsEnabledIT_ERR
Return values:
State of bit (1 or 0).

Definition at line 727 of file stm32wbxx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC ( void )

Check if Expected SYNC interrupt is enabled or not.

Reference Manual to LL API cross reference:
CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC
Return values:
State of bit (1 or 0).

Definition at line 757 of file stm32wbxx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK ( void )

Check if SYNC event OK interrupt is enabled or not.

Reference Manual to LL API cross reference:
CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK
Return values:
State of bit (1 or 0).

Definition at line 667 of file stm32wbxx_ll_crs.h.

__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN ( void )

Check if SYNC warning interrupt is enabled or not.

Reference Manual to LL API cross reference:
CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN
Return values:
State of bit (1 or 0).

Definition at line 697 of file stm32wbxx_ll_crs.h.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CRS Exported Functions

Functions

ErrorStatus LL_CRS_DeInit (void)
De-Initializes CRS peripheral registers to their default reset values.

Function Documentation

ErrorStatus LL_CRS_DeInit ( void )

De-Initializes CRS peripheral registers to their default reset values.

Return values:
An ErrorStatus enumeration value:
  • SUCCESS: CRS registers are de-initialized
  • ERROR: not applicable

Definition at line 56 of file stm32wbxx_ll_crs.c.

References LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_CRS, and LL_APB1_GRP1_ReleaseReset().

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DMA

Modules
DMA
STM32WBxx_LL_Driver

Modules

DMA Private Macros
DMA Exported Init structure
DMA Exported Constants
DMA Exported Macros
DMA Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for DMA registers.

Register | Bit | Function
CCR | CIRC | LL_DMA_ConfigTransfer
 |  | LL_DMA_GetMode
 |  | LL_DMA_SetMode
 | DIR | LL_DMA_ConfigTransfer
 |  | LL_DMA_GetDataTransferDirection
 |  | LL_DMA_SetDataTransferDirection
 | EN | LL_DMA_DisableChannel
 |  | LL_DMA_EnableChannel
 |  | LL_DMA_IsEnabledChannel
 | HTIE | LL_DMA_DisableIT_HT
 |  | LL_DMA_EnableIT_HT
 |  | LL_DMA_IsEnabledIT_HT
 | MEM2MEM | LL_DMA_ConfigTransfer
 |  | LL_DMA_GetDataTransferDirection
 |  | LL_DMA_SetDataTransferDirection
 | MINC | LL_DMA_ConfigTransfer
 |  | LL_DMA_GetMemoryIncMode
 |  | LL_DMA_SetMemoryIncMode
 | MSIZE | LL_DMA_ConfigTransfer
 |  | LL_DMA_GetMemorySize
 |  | LL_DMA_SetMemorySize
 | PINC | LL_DMA_ConfigTransfer
 |  | LL_DMA_GetPeriphIncMode
 |  | LL_DMA_SetPeriphIncMode
 | PL | LL_DMA_ConfigTransfer
 |  | LL_DMA_GetChannelPriorityLevel
 |  | LL_DMA_SetChannelPriorityLevel
 | PSIZE | LL_DMA_ConfigTransfer
 |  | LL_DMA_GetPeriphSize
 |  | LL_DMA_SetPeriphSize
 | TCIE | LL_DMA_DisableIT_TC
 |  | LL_DMA_EnableIT_TC
 |  | LL_DMA_IsEnabledIT_TC
 | TEIE | LL_DMA_DisableIT_TE
 |  | LL_DMA_EnableIT_TE
 |  | LL_DMA_IsEnabledIT_TE
CMAR | MA | LL_DMA_ConfigAddresses
 |  | LL_DMA_GetM2MDstAddress
 |  | LL_DMA_GetMemoryAddress
 |  | LL_DMA_SetM2MDstAddress
 |  | LL_DMA_SetMemoryAddress
CNDTR | NDT | LL_DMA_GetDataLength
 |  | LL_DMA_SetDataLength
CPAR | PA | LL_DMA_ConfigAddresses
 |  | LL_DMA_GetM2MSrcAddress
 |  | LL_DMA_GetPeriphAddress
 |  | LL_DMA_SetM2MSrcAddress
 |  | LL_DMA_SetPeriphAddress
CxCR | DMAREQ_ID | LL_DMA_GetPeriphRequest
 |  | LL_DMA_SetPeriphRequest
IFCR | CGIF1 | LL_DMA_ClearFlag_GI1
 | CGIF2 | LL_DMA_ClearFlag_GI2
 | CGIF3 | LL_DMA_ClearFlag_GI3
 | CGIF4 | LL_DMA_ClearFlag_GI4
 | CGIF5 | LL_DMA_ClearFlag_GI5
 | CGIF6 | LL_DMA_ClearFlag_GI6
 | CGIF7 | LL_DMA_ClearFlag_GI7
 | CHTIF1 | LL_DMA_ClearFlag_HT1
 | CHTIF2 | LL_DMA_ClearFlag_HT2
 | CHTIF3 | LL_DMA_ClearFlag_HT3
 | CHTIF4 | LL_DMA_ClearFlag_HT4
 | CHTIF5 | LL_DMA_ClearFlag_HT5
 | CHTIF6 | LL_DMA_ClearFlag_HT6
 | CHTIF7 | LL_DMA_ClearFlag_HT7
 | CTCIF1 | LL_DMA_ClearFlag_TC1
 | CTCIF2 | LL_DMA_ClearFlag_TC2
 | CTCIF3 | LL_DMA_ClearFlag_TC3
 | CTCIF4 | LL_DMA_ClearFlag_TC4
 | CTCIF5 | LL_DMA_ClearFlag_TC5
 | CTCIF6 | LL_DMA_ClearFlag_TC6
 | CTCIF7 | LL_DMA_ClearFlag_TC7
 | CTEIF1 | LL_DMA_ClearFlag_TE1
 | CTEIF2 | LL_DMA_ClearFlag_TE2
 | CTEIF3 | LL_DMA_ClearFlag_TE3
 | CTEIF4 | LL_DMA_ClearFlag_TE4
 | CTEIF5 | LL_DMA_ClearFlag_TE5
 | CTEIF6 | LL_DMA_ClearFlag_TE6
 | CTEIF7 | LL_DMA_ClearFlag_TE7
ISR | GIF1 | LL_DMA_IsActiveFlag_GI1
 | GIF2 | LL_DMA_IsActiveFlag_GI2
 | GIF3 | LL_DMA_IsActiveFlag_GI3
 | GIF4 | LL_DMA_IsActiveFlag_GI4
 | GIF5 | LL_DMA_IsActiveFlag_GI5
 | GIF6 | LL_DMA_IsActiveFlag_GI6
 | GIF7 | LL_DMA_IsActiveFlag_GI7
 | HTIF1 | LL_DMA_IsActiveFlag_HT1
 | HTIF2 | LL_DMA_IsActiveFlag_HT2
 | HTIF3 | LL_DMA_IsActiveFlag_HT3
 | HTIF4 | LL_DMA_IsActiveFlag_HT4
 | HTIF5 | LL_DMA_IsActiveFlag_HT5
 | HTIF6 | LL_DMA_IsActiveFlag_HT6
 | HTIF7 | LL_DMA_IsActiveFlag_HT7
 | TCIF1 | LL_DMA_IsActiveFlag_TC1
 | TCIF2 | LL_DMA_IsActiveFlag_TC2
 | TCIF3 | LL_DMA_IsActiveFlag_TC3
 | TCIF4 | LL_DMA_IsActiveFlag_TC4
 | TCIF5 | LL_DMA_IsActiveFlag_TC5
 | TCIF6 | LL_DMA_IsActiveFlag_TC6
 | TCIF7 | LL_DMA_IsActiveFlag_TC7
 | TEIF1 | LL_DMA_IsActiveFlag_TE1
 | TEIF2 | LL_DMA_IsActiveFlag_TE2
 | TEIF3 | LL_DMA_IsActiveFlag_TE3
 | TEIF4 | LL_DMA_IsActiveFlag_TE4
 | TEIF5 | LL_DMA_IsActiveFlag_TE5
 | TEIF6 | LL_DMA_IsActiveFlag_TE6
 | TEIF7 | LL_DMA_IsActiveFlag_TE7
Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DMA Private Macros

Defines
DMA Private Macros
DMA

Defines

#define | IS_LL_DMA_DIRECTION(__VALUE__)
#define | IS_LL_DMA_MODE(__VALUE__)
#define | IS_LL_DMA_PERIPHINCMODE(__VALUE__)
#define | IS_LL_DMA_MEMORYINCMODE(__VALUE__)
#define | IS_LL_DMA_PERIPHDATASIZE(__VALUE__)
#define | IS_LL_DMA_MEMORYDATASIZE(__VALUE__)
#define | IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
#define | IS_LL_DMA_PERIPHREQUEST(__VALUE__) ((__VALUE__) <= 40U)
#define | IS_LL_DMA_PRIORITY(__VALUE__)
#define | IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)
#define | __LL_DMA_INSTANCE_TO_CHANNEL(__DMA_INSTANCE__, __CHANNEL_INDEX__) (((__DMA_INSTANCE__) == DMA1) ? (DMA1_Channel1 + (__CHANNEL_INDEX__)) : (DMA2_Channel1 + (__CHANNEL_INDEX__)))
Helper macro to convert DMA Instance and index into DMA channel.
#define | __LL_DMA_INSTANCE_TO_DMAMUX_CCR(__DMA_INSTANCE__, __CHANNEL_INDEX__) (((__DMA_INSTANCE__) == DMA1) ? (DMAMUX1_Channel0 + (__CHANNEL_INDEX__)) : (DMAMUX1_Channel7 + (__CHANNEL_INDEX__)))
Helper macro to convert DMA Instance and index into DMAMUX channel.

Define Documentation

#define __LL_DMA_INSTANCE_TO_CHANNEL | ( | __DMA_INSTANCE__,
 |  | __CHANNEL_INDEX__
 | ) | (((__DMA_INSTANCE__) == DMA1) ? (DMA1_Channel1 + (__CHANNEL_INDEX__)) : (DMA2_Channel1 + (__CHANNEL_INDEX__)))

Helper macro to convert DMA Instance and index into DMA channel.

Parameters:
__DMA_INSTANCE__ | DMAx
__CHANNEL_INDEX__ | 0 to 6 to map DMAx_Channel1 to DMAx_Channel7
Return values:
Pointer to the DMA channel

Definition at line 57 of file stm32wbxx_ll_dma.h.

Referenced by LL_DMA_ConfigAddresses(), LL_DMA_ConfigTransfer(), LL_DMA_DisableChannel(), LL_DMA_DisableIT_HT(), LL_DMA_DisableIT_TC(), LL_DMA_DisableIT_TE(), LL_DMA_EnableChannel(), LL_DMA_EnableIT_HT(), LL_DMA_EnableIT_TC(), LL_DMA_EnableIT_TE(), LL_DMA_GetChannelPriorityLevel(), LL_DMA_GetDataLength(), LL_DMA_GetDataTransferDirection(), LL_DMA_GetM2MDstAddress(), LL_DMA_GetM2MSrcAddress(), LL_DMA_GetMemoryAddress(), LL_DMA_GetMemoryIncMode(), LL_DMA_GetMemorySize(), LL_DMA_GetMode(), LL_DMA_GetPeriphAddress(), LL_DMA_GetPeriphIncMode(), LL_DMA_GetPeriphSize(), LL_DMA_IsEnabledChannel(), LL_DMA_IsEnabledIT_HT(), LL_DMA_IsEnabledIT_TC(), LL_DMA_IsEnabledIT_TE(), LL_DMA_SetChannelPriorityLevel(), LL_DMA_SetDataLength(), LL_DMA_SetDataTransferDirection(), LL_DMA_SetM2MDstAddress(), LL_DMA_SetM2MSrcAddress(), LL_DMA_SetMemoryAddress(), LL_DMA_SetMemoryIncMode(), LL_DMA_SetMemorySize(), LL_DMA_SetMode(), LL_DMA_SetPeriphAddress(), LL_DMA_SetPeriphIncMode(), and LL_DMA_SetPeriphSize().

#define __LL_DMA_INSTANCE_TO_DMAMUX_CCR | ( | __DMA_INSTANCE__,
 |  | __CHANNEL_INDEX__
 | ) | (((__DMA_INSTANCE__) == DMA1) ? (DMAMUX1_Channel0 + (__CHANNEL_INDEX__)) : (DMAMUX1_Channel7 + (__CHANNEL_INDEX__)))

Helper macro to convert DMA Instance and index into DMAMUX channel.

Note:
DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. #if defined (DMA2) DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. #endif
Parameters:
__DMA_INSTANCE__ | DMAx
__CHANNEL_INDEX__ | 0 to 6 to map DMAx_Channel1 to DMAx_Channel7
Return values:
Pointer to the DMA channel

Definition at line 75 of file stm32wbxx_ll_dma.h.

Referenced by LL_DMA_GetPeriphRequest(), and LL_DMA_SetPeriphRequest().

#define IS_LL_DMA_ALL_CHANNEL_INSTANCE | ( | INSTANCE,
 |  | CHANNEL
 | ) |
Value:
((((INSTANCE) == DMA1) && \
                                                         (((CHANNEL) == LL_DMA_CHANNEL_1) || \
                                                          ((CHANNEL) == LL_DMA_CHANNEL_2) || \
                                                          ((CHANNEL) == LL_DMA_CHANNEL_3) || \
                                                          ((CHANNEL) == LL_DMA_CHANNEL_4) || \
                                                          ((CHANNEL) == LL_DMA_CHANNEL_5) || \
                                                          ((CHANNEL) == LL_DMA_CHANNEL_6) || \
                                                          ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
                                                         (((INSTANCE) == DMA2) && \
                                                         (((CHANNEL) == LL_DMA_CHANNEL_1) || \
                                                          ((CHANNEL) == LL_DMA_CHANNEL_2) || \
                                                          ((CHANNEL) == LL_DMA_CHANNEL_3) || \
                                                          ((CHANNEL) == LL_DMA_CHANNEL_4) || \
                                                          ((CHANNEL) == LL_DMA_CHANNEL_5) || \
                                                          ((CHANNEL) == LL_DMA_CHANNEL_6) || \
                                                          ((CHANNEL) == LL_DMA_CHANNEL_7))))

Definition at line 79 of file stm32wbxx_ll_dma.c.

Referenced by LL_DMA_DeInit(), and LL_DMA_Init().

#define IS_LL_DMA_DIRECTION ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
                                                 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
                                                 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))

Definition at line 47 of file stm32wbxx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_MEMORYDATASIZE ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_MDATAALIGN_BYTE)      || \
                                                 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD)  || \
                                                 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))

Definition at line 64 of file stm32wbxx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_MEMORYINCMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
                                                 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))

Definition at line 57 of file stm32wbxx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_MODE_NORMAL) || \
                                                 ((__VALUE__) == LL_DMA_MODE_CIRCULAR))

Definition at line 51 of file stm32wbxx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_NBDATA ( __VALUE__ ) ((__VALUE__) <= 0x0000FFFFU)

Definition at line 68 of file stm32wbxx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_PERIPHDATASIZE ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_PDATAALIGN_BYTE)      || \
                                                 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD)  || \
                                                 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))

Definition at line 60 of file stm32wbxx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_PERIPHINCMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
                                                 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))

Definition at line 54 of file stm32wbxx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_PERIPHREQUEST ( __VALUE__ ) ((__VALUE__) <= 40U)

Definition at line 70 of file stm32wbxx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_PRIORITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_PRIORITY_LOW)    || \
                                                 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
                                                 ((__VALUE__) == LL_DMA_PRIORITY_HIGH)   || \
                                                 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))

Definition at line 72 of file stm32wbxx_ll_dma.c.

Referenced by LL_DMA_Init().

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LL_DMA_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_DMA_InitTypeDef Struct Reference
DMA Exported Init structure

#include <stm32wbxx_ll_dma.h>

Data Fields

uint32_t | PeriphOrM2MSrcAddress
uint32_t | MemoryOrM2MDstAddress
uint32_t | Direction
uint32_t | Mode
uint32_t | PeriphOrM2MSrcIncMode
uint32_t | MemoryOrM2MDstIncMode
uint32_t | PeriphOrM2MSrcDataSize
uint32_t | MemoryOrM2MDstDataSize
uint32_t | NbData
uint32_t | PeriphRequest
uint32_t | Priority

Detailed Description

Definition at line 90 of file stm32wbxx_ll_dma.h.

Field Documentation

uint32_t LL_DMA_InitTypeDef::Direction

Specifies if the data will be transferred from memory to peripheral, from memory to memory or from peripheral to memory. This parameter can be a value of Transfer Direction

This feature can be modified afterwards using unitary function LL_DMA_SetDataTransferDirection().

Definition at line 102 of file stm32wbxx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::MemoryOrM2MDstAddress

Specifies the memory base address for DMA transfer or as Destination base address in case of memory to memory transfer direction.

This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.

Definition at line 97 of file stm32wbxx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::MemoryOrM2MDstDataSize

Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) in case of memory to memory transfer direction. This parameter can be a value of Memory data alignment

This feature can be modified afterwards using unitary function LL_DMA_SetMemorySize().

Definition at line 133 of file stm32wbxx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::MemoryOrM2MDstIncMode

Specifies whether the Memory address or Destination address in case of memory to memory transfer direction is incremented or not. This parameter can be a value of Memory increment mode

This feature can be modified afterwards using unitary function LL_DMA_SetMemoryIncMode().

Definition at line 121 of file stm32wbxx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::Mode

Specifies the normal or circular operation mode. This parameter can be a value of Transfer mode

Note:
: The circular buffer mode cannot be used if the memory to memory data transfer direction is configured on the selected Channel

This feature can be modified afterwards using unitary function LL_DMA_SetMode().

Definition at line 108 of file stm32wbxx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::NbData

Specifies the number of data to transfer, in data unit. The data unit is equal to the source buffer configuration set in PeripheralSize or MemorySize parameters depending in the transfer direction. This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF

This feature can be modified afterwards using unitary function LL_DMA_SetDataLength().

Definition at line 139 of file stm32wbxx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::PeriphOrM2MSrcAddress

Specifies the peripheral base address for DMA transfer or as Source base address in case of memory to memory transfer direction.

This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.

Definition at line 92 of file stm32wbxx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::PeriphOrM2MSrcDataSize

Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) in case of memory to memory transfer direction. This parameter can be a value of Peripheral data alignment

This feature can be modified afterwards using unitary function LL_DMA_SetPeriphSize().

Definition at line 127 of file stm32wbxx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::PeriphOrM2MSrcIncMode

Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction is incremented or not. This parameter can be a value of Peripheral increment mode

This feature can be modified afterwards using unitary function LL_DMA_SetPeriphIncMode().

Definition at line 115 of file stm32wbxx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::PeriphRequest

Specifies the peripheral request. This parameter can be a value of Transfer request

This feature can be modified afterwards using unitary function LL_DMA_SetPeriphRequest().

Definition at line 146 of file stm32wbxx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::Priority

Specifies the channel priority level. This parameter can be a value of Transfer Priority level

This feature can be modified afterwards using unitary function LL_DMA_SetChannelPriorityLevel().

Definition at line 151 of file stm32wbxx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

The documentation for this struct was generated from the following file:
  • stm32wbxx_ll_dma.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
DMA Exported Constants

Flags defines which can be used with LL_DMA_WriteReg function. More...

Defines

#define | LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1
#define | LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1
#define | LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1
#define | LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1
#define | LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2
#define | LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2
#define | LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2
#define | LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2
#define | LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3
#define | LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3
#define | LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3
#define | LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3
#define | LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4
#define | LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4
#define | LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4
#define | LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4
#define | LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5
#define | LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5
#define | LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5
#define | LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5
#define | LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6
#define | LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6
#define | LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6
#define | LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6
#define | LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7
#define | LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7
#define | LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7
#define | LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7

Detailed Description

Flags defines which can be used with LL_DMA_WriteReg function.

Define Documentation

#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1

Channel 1 global flag

Definition at line 170 of file stm32wbxx_ll_dma.h.

#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2

Channel 2 global flag

Definition at line 174 of file stm32wbxx_ll_dma.h.

#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3

Channel 3 global flag

Definition at line 178 of file stm32wbxx_ll_dma.h.

#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4

Channel 4 global flag

Definition at line 182 of file stm32wbxx_ll_dma.h.

#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5

Channel 5 global flag

Definition at line 186 of file stm32wbxx_ll_dma.h.

#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6

Channel 6 global flag

Definition at line 190 of file stm32wbxx_ll_dma.h.

#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7

Channel 7 global flag

Definition at line 194 of file stm32wbxx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1

Channel 1 half transfer flag

Definition at line 172 of file stm32wbxx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2

Channel 2 half transfer flag

Definition at line 176 of file stm32wbxx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3

Channel 3 half transfer flag

Definition at line 180 of file stm32wbxx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4

Channel 4 half transfer flag

Definition at line 184 of file stm32wbxx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5

Channel 5 half transfer flag

Definition at line 188 of file stm32wbxx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6

Channel 6 half transfer flag

Definition at line 192 of file stm32wbxx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7

Channel 7 half transfer flag

Definition at line 196 of file stm32wbxx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1

Channel 1 transfer complete flag

Definition at line 171 of file stm32wbxx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2

Channel 2 transfer complete flag

Definition at line 175 of file stm32wbxx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3

Channel 3 transfer complete flag

Definition at line 179 of file stm32wbxx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4

Channel 4 transfer complete flag

Definition at line 183 of file stm32wbxx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5

Channel 5 transfer complete flag

Definition at line 187 of file stm32wbxx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6

Channel 6 transfer complete flag

Definition at line 191 of file stm32wbxx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7

Channel 7 transfer complete flag

Definition at line 195 of file stm32wbxx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1

Channel 1 transfer error flag

Definition at line 173 of file stm32wbxx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2

Channel 2 transfer error flag

Definition at line 177 of file stm32wbxx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3

Channel 3 transfer error flag

Definition at line 181 of file stm32wbxx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4

Channel 4 transfer error flag

Definition at line 185 of file stm32wbxx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5

Channel 5 transfer error flag

Definition at line 189 of file stm32wbxx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6

Channel 6 transfer error flag

Definition at line 193 of file stm32wbxx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7

Channel 7 transfer error flag

Definition at line 197 of file stm32wbxx_ll_dma.h.

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STM32WB55xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
DMA Exported Constants

Flags defines which can be used with LL_DMA_ReadReg function. More...

Defines

#define | LL_DMA_ISR_GIF1 DMA_ISR_GIF1
#define | LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1
#define | LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1
#define | LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1
#define | LL_DMA_ISR_GIF2 DMA_ISR_GIF2
#define | LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2
#define | LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2
#define | LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2
#define | LL_DMA_ISR_GIF3 DMA_ISR_GIF3
#define | LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3
#define | LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3
#define | LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3
#define | LL_DMA_ISR_GIF4 DMA_ISR_GIF4
#define | LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4
#define | LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4
#define | LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4
#define | LL_DMA_ISR_GIF5 DMA_ISR_GIF5
#define | LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5
#define | LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5
#define | LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5
#define | LL_DMA_ISR_GIF6 DMA_ISR_GIF6
#define | LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6
#define | LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6
#define | LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6
#define | LL_DMA_ISR_GIF7 DMA_ISR_GIF7
#define | LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7
#define | LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7
#define | LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7

Detailed Description

Flags defines which can be used with LL_DMA_ReadReg function.

Define Documentation

#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1

Channel 1 global flag

Definition at line 206 of file stm32wbxx_ll_dma.h.

#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2

Channel 2 global flag

Definition at line 210 of file stm32wbxx_ll_dma.h.

#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3

Channel 3 global flag

Definition at line 214 of file stm32wbxx_ll_dma.h.

#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4

Channel 4 global flag

Definition at line 218 of file stm32wbxx_ll_dma.h.

#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5

Channel 5 global flag

Definition at line 222 of file stm32wbxx_ll_dma.h.

#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6

Channel 6 global flag

Definition at line 226 of file stm32wbxx_ll_dma.h.

#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7

Channel 7 global flag

Definition at line 230 of file stm32wbxx_ll_dma.h.

#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1

Channel 1 half transfer flag

Definition at line 208 of file stm32wbxx_ll_dma.h.

#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2

Channel 2 half transfer flag

Definition at line 212 of file stm32wbxx_ll_dma.h.

#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3

Channel 3 half transfer flag

Definition at line 216 of file stm32wbxx_ll_dma.h.

#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4

Channel 4 half transfer flag

Definition at line 220 of file stm32wbxx_ll_dma.h.

#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5

Channel 5 half transfer flag

Definition at line 224 of file stm32wbxx_ll_dma.h.

#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6

Channel 6 half transfer flag

Definition at line 228 of file stm32wbxx_ll_dma.h.

#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7

Channel 7 half transfer flag

Definition at line 232 of file stm32wbxx_ll_dma.h.

#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1

Channel 1 transfer complete flag

Definition at line 207 of file stm32wbxx_ll_dma.h.

#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2

Channel 2 transfer complete flag

Definition at line 211 of file stm32wbxx_ll_dma.h.

#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3

Channel 3 transfer complete flag

Definition at line 215 of file stm32wbxx_ll_dma.h.

#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4

Channel 4 transfer complete flag

Definition at line 219 of file stm32wbxx_ll_dma.h.

#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5

Channel 5 transfer complete flag

Definition at line 223 of file stm32wbxx_ll_dma.h.

#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6

Channel 6 transfer complete flag

Definition at line 227 of file stm32wbxx_ll_dma.h.

#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7

Channel 7 transfer complete flag

Definition at line 231 of file stm32wbxx_ll_dma.h.

#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1

Channel 1 transfer error flag

Definition at line 209 of file stm32wbxx_ll_dma.h.

#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2

Channel 2 transfer error flag

Definition at line 213 of file stm32wbxx_ll_dma.h.

#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3

Channel 3 transfer error flag

Definition at line 217 of file stm32wbxx_ll_dma.h.

#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4

Channel 4 transfer error flag

Definition at line 221 of file stm32wbxx_ll_dma.h.

#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5

Channel 5 transfer error flag

Definition at line 225 of file stm32wbxx_ll_dma.h.

#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6

Channel 6 transfer error flag

Definition at line 229 of file stm32wbxx_ll_dma.h.

#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7

Channel 7 transfer error flag

Definition at line 233 of file stm32wbxx_ll_dma.h.

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STM32WB55xx HAL User Manual: IT Defines

Defines
IT Defines
DMA Exported Constants

IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions. More...

Defines

#define | LL_DMA_CCR_TCIE DMA_CCR_TCIE
#define | LL_DMA_CCR_HTIE DMA_CCR_HTIE
#define | LL_DMA_CCR_TEIE DMA_CCR_TEIE

Detailed Description

IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions.

Define Documentation

#define LL_DMA_CCR_HTIE DMA_CCR_HTIE

Half Transfer interrupt

Definition at line 243 of file stm32wbxx_ll_dma.h.

#define LL_DMA_CCR_TCIE DMA_CCR_TCIE

Transfer complete interrupt

Definition at line 242 of file stm32wbxx_ll_dma.h.

#define LL_DMA_CCR_TEIE DMA_CCR_TEIE

Transfer error interrupt

Definition at line 244 of file stm32wbxx_ll_dma.h.

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STM32WB55xx HAL User Manual: CHANNEL

Defines
CHANNEL
DMA Exported Constants

Defines

#define | LL_DMA_CHANNEL_1 0x00000001U
#define | LL_DMA_CHANNEL_2 0x00000002U
#define | LL_DMA_CHANNEL_3 0x00000003U
#define | LL_DMA_CHANNEL_4 0x00000004U
#define | LL_DMA_CHANNEL_5 0x00000005U
#define | LL_DMA_CHANNEL_6 0x00000006U
#define | LL_DMA_CHANNEL_7 0x00000007U
#define | LL_DMA_CHANNEL_ALL 0xFFFF0000U

Define Documentation

#define LL_DMA_CHANNEL_1 0x00000001U

DMA Channel 1

Definition at line 252 of file stm32wbxx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_2 0x00000002U

DMA Channel 2

Definition at line 253 of file stm32wbxx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_3 0x00000003U

DMA Channel 3

Definition at line 254 of file stm32wbxx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_4 0x00000004U

DMA Channel 4

Definition at line 255 of file stm32wbxx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_5 0x00000005U

DMA Channel 5

Definition at line 256 of file stm32wbxx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_6 0x00000006U

DMA Channel 6

Definition at line 257 of file stm32wbxx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_7 0x00000007U

DMA Channel 7

Definition at line 258 of file stm32wbxx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_ALL 0xFFFF0000U

DMA Channel all (used only for function LL_DMA_DeInit().

Definition at line 260 of file stm32wbxx_ll_dma.h.

Referenced by LL_DMA_DeInit().

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STM32WB55xx HAL User Manual: Transfer Direction

Defines
Transfer Direction
DMA Exported Constants

Defines

#define | LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U
#define | LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR
#define | LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM

Define Documentation

#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM

Memory to memory direction

Definition at line 271 of file stm32wbxx_ll_dma.h.

#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR

Memory to peripheral direction

Definition at line 270 of file stm32wbxx_ll_dma.h.

Referenced by LL_DMA_ConfigAddresses().

#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U

Peripheral to memory direction

Definition at line 269 of file stm32wbxx_ll_dma.h.

Referenced by LL_DMA_StructInit().

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STM32WB55xx HAL User Manual: Transfer mode

Defines
Transfer mode
DMA Exported Constants

Defines

#define | LL_DMA_MODE_NORMAL 0x00000000U
#define | LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC

Define Documentation

#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC

Circular Mode

Definition at line 280 of file stm32wbxx_ll_dma.h.

#define LL_DMA_MODE_NORMAL 0x00000000U

Normal Mode

Definition at line 279 of file stm32wbxx_ll_dma.h.

Referenced by LL_DMA_StructInit().

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Peripheral increment mode

Defines
Peripheral increment mode
DMA Exported Constants

Defines

#define | LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC
#define | LL_DMA_PERIPH_NOINCREMENT 0x00000000U

Define Documentation

#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC

Peripheral increment mode Enable

Definition at line 288 of file stm32wbxx_ll_dma.h.

#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U

Peripheral increment mode Disable

Definition at line 289 of file stm32wbxx_ll_dma.h.

Referenced by LL_DMA_StructInit().

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STM32WB55xx HAL User Manual: Memory increment mode

Defines
Memory increment mode
DMA Exported Constants

Defines

#define | LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC
#define | LL_DMA_MEMORY_NOINCREMENT 0x00000000U

Define Documentation

#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC

Memory increment mode Enable

Definition at line 297 of file stm32wbxx_ll_dma.h.

#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U

Memory increment mode Disable

Definition at line 298 of file stm32wbxx_ll_dma.h.

Referenced by LL_DMA_StructInit().

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STM32WB55xx HAL User Manual: Peripheral data alignment

Defines
Peripheral data alignment
DMA Exported Constants

Defines

#define | LL_DMA_PDATAALIGN_BYTE 0x00000000U
#define | LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0
#define | LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1

Define Documentation

#define LL_DMA_PDATAALIGN_BYTE 0x00000000U

Peripheral data alignment : Byte

Definition at line 306 of file stm32wbxx_ll_dma.h.

Referenced by LL_DMA_StructInit().

#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0

Peripheral data alignment : HalfWord

Definition at line 307 of file stm32wbxx_ll_dma.h.

#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1

Peripheral data alignment : Word

Definition at line 308 of file stm32wbxx_ll_dma.h.

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STM32WB55xx HAL User Manual: Memory data alignment

Defines
Memory data alignment
DMA Exported Constants

Defines

#define | LL_DMA_MDATAALIGN_BYTE 0x00000000U
#define | LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0
#define | LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1

Define Documentation

#define LL_DMA_MDATAALIGN_BYTE 0x00000000U

Memory data alignment : Byte

Definition at line 316 of file stm32wbxx_ll_dma.h.

Referenced by LL_DMA_StructInit().

#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0

Memory data alignment : HalfWord

Definition at line 317 of file stm32wbxx_ll_dma.h.

#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1

Memory data alignment : Word

Definition at line 318 of file stm32wbxx_ll_dma.h.

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STM32WB55xx HAL User Manual: Transfer Priority level

Defines
Transfer Priority level
DMA Exported Constants

Defines

#define | LL_DMA_PRIORITY_LOW 0x00000000U
#define | LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0
#define | LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1
#define | LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL

Define Documentation

#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1

Priority level : High

Definition at line 328 of file stm32wbxx_ll_dma.h.

#define LL_DMA_PRIORITY_LOW 0x00000000U

Priority level : Low

Definition at line 326 of file stm32wbxx_ll_dma.h.

Referenced by LL_DMA_StructInit().

#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0

Priority level : Medium

Definition at line 327 of file stm32wbxx_ll_dma.h.

#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL

Priority level : Very_High

Definition at line 329 of file stm32wbxx_ll_dma.h.

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STM32WB55xx HAL User Manual: Common Write and read registers macros

Defines
Common Write and read registers macros
DMA Exported Macros

Defines

#define | LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in DMA register.
#define | LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in DMA register.

Define Documentation

#define LL_DMA_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in DMA register.

Parameters:
__INSTANCE__ | DMA Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 361 of file stm32wbxx_ll_dma.h.

#define LL_DMA_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in DMA register.

Parameters:
__INSTANCE__ | DMA Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 353 of file stm32wbxx_ll_dma.h.

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STM32WB55xx HAL User Manual: Convert DMAxChannely

Defines
Convert DMAxChannely
DMA Exported Macros

Defines

#define | __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
Convert DMAx_Channely into DMAx.
#define | __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)
Convert DMAx_Channely into LL_DMA_CHANNEL_y.
#define | __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)
Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely.

Define Documentation

#define __LL_DMA_GET_CHANNEL ( __CHANNEL_INSTANCE__ )
Value:
(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
 LL_DMA_CHANNEL_7)

Convert DMAx_Channely into LL_DMA_CHANNEL_y.

Parameters:
__CHANNEL_INSTANCE__ DMAx_Channely
Return values:
LL_DMA_CHANNEL_y

Definition at line 388 of file stm32wbxx_ll_dma.h.

#define __LL_DMA_GET_CHANNEL_INSTANCE | ( | __DMA_INSTANCE__,
 |  | __CHANNEL__
 | ) |
Value:
((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
 DMA2_Channel7)

Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely.

Parameters:
__DMA_INSTANCE__ | DMAx
__CHANNEL__ | LL_DMA_CHANNEL_y
Return values:
DMAx_Channely

Definition at line 436 of file stm32wbxx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define __LL_DMA_GET_INSTANCE ( __CHANNEL_INSTANCE__ ) (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)

Convert DMAx_Channely into DMAx.

Parameters:
__CHANNEL_INSTANCE__ DMAx_Channely
Return values:
DMAx

Definition at line 375 of file stm32wbxx_ll_dma.h.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Configuration

Functions
Configuration
DMA Exported Functions

Functions

__STATIC_INLINE void | LL_DMA_EnableChannel (DMA_TypeDef *DMAx, uint32_t Channel)
Enable DMA channel.
__STATIC_INLINE void | LL_DMA_DisableChannel (DMA_TypeDef *DMAx, uint32_t Channel)
Disable DMA channel.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledChannel (DMA_TypeDef *DMAx, uint32_t Channel)
Check if DMA channel is enabled or disabled.
__STATIC_INLINE void | LL_DMA_ConfigTransfer (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
Configure all parameters link to DMA transfer.
__STATIC_INLINE void | LL_DMA_SetDataTransferDirection (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
Set Data transfer direction (read from peripheral or from memory).
__STATIC_INLINE uint32_t | LL_DMA_GetDataTransferDirection (DMA_TypeDef *DMAx, uint32_t Channel)
Get Data transfer direction (read from peripheral or from memory).
__STATIC_INLINE void | LL_DMA_SetMode (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
Set DMA mode circular or normal.
__STATIC_INLINE uint32_t | LL_DMA_GetMode (DMA_TypeDef *DMAx, uint32_t Channel)
Get DMA mode circular or normal.
__STATIC_INLINE void | LL_DMA_SetPeriphIncMode (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
Set Peripheral increment mode.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphIncMode (DMA_TypeDef *DMAx, uint32_t Channel)
Get Peripheral increment mode.
__STATIC_INLINE void | LL_DMA_SetMemoryIncMode (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
Set Memory increment mode.
__STATIC_INLINE uint32_t | LL_DMA_GetMemoryIncMode (DMA_TypeDef *DMAx, uint32_t Channel)
Get Memory increment mode.
__STATIC_INLINE void | LL_DMA_SetPeriphSize (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
Set Peripheral size.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphSize (DMA_TypeDef *DMAx, uint32_t Channel)
Get Peripheral size.
__STATIC_INLINE void | LL_DMA_SetMemorySize (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
Set Memory size.
__STATIC_INLINE uint32_t | LL_DMA_GetMemorySize (DMA_TypeDef *DMAx, uint32_t Channel)
Get Memory size.
__STATIC_INLINE void | LL_DMA_SetChannelPriorityLevel (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
Set Channel priority level.
__STATIC_INLINE uint32_t | LL_DMA_GetChannelPriorityLevel (DMA_TypeDef *DMAx, uint32_t Channel)
Get Channel priority level.
__STATIC_INLINE void | LL_DMA_SetDataLength (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
Set Number of data to transfer.
__STATIC_INLINE uint32_t | LL_DMA_GetDataLength (DMA_TypeDef *DMAx, uint32_t Channel)
Get Number of data to transfer.
__STATIC_INLINE void | LL_DMA_ConfigAddresses (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
Configure the Source and Destination addresses.
__STATIC_INLINE void | LL_DMA_SetMemoryAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory address.
__STATIC_INLINE void | LL_DMA_SetPeriphAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
Set the Peripheral address.
__STATIC_INLINE uint32_t | LL_DMA_GetMemoryAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get Memory address.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get Peripheral address.
__STATIC_INLINE void | LL_DMA_SetM2MSrcAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory to Memory Source address.
__STATIC_INLINE void | LL_DMA_SetM2MDstAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory to Memory Destination address.
__STATIC_INLINE uint32_t | LL_DMA_GetM2MSrcAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get the Memory to Memory Source address.
__STATIC_INLINE uint32_t | LL_DMA_GetM2MDstAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get the Memory to Memory Destination address.
__STATIC_INLINE void | LL_DMA_SetPeriphRequest (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
Set DMA request for DMA Channels on DMAMUX Channel x.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphRequest (DMA_TypeDef *DMAx, uint32_t Channel)
Get DMA request for DMA Channels on DMAMUX Channel x.

Function Documentation

__STATIC_INLINE void LL_DMA_ConfigAddresses | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | Direction
 | ) |  |

Configure the Source and Destination addresses.

Note:
This API must not be called when the DMA channel is enabled.
Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
Reference Manual to LL API cross reference:
CPAR PA LL_DMA_ConfigAddresses
CMAR MA LL_DMA_ConfigAddresses
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
SrcAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
DstAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Direction This parameter can be one of the following values:
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY
  • LL_DMA_DIRECTION_MEMORY_TO_PERIPH
  • LL_DMA_DIRECTION_MEMORY_TO_MEMORY
Return values:
None

Definition at line 984 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_CHANNEL, and LL_DMA_DIRECTION_MEMORY_TO_PERIPH.

__STATIC_INLINE void LL_DMA_ConfigTransfer | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Configuration
 | ) |  |

Configure all parameters link to DMA transfer.

Reference Manual to LL API cross reference:
CCR DIR LL_DMA_ConfigTransfer
CCR MEM2MEM LL_DMA_ConfigTransfer
CCR CIRC LL_DMA_ConfigTransfer
CCR PINC LL_DMA_ConfigTransfer
CCR MINC LL_DMA_ConfigTransfer
CCR PSIZE LL_DMA_ConfigTransfer
CCR MSIZE LL_DMA_ConfigTransfer
CCR PL LL_DMA_ConfigTransfer
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Configuration This parameter must be a combination of all the following values:
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH or LL_DMA_DIRECTION_MEMORY_TO_MEMORY
  • LL_DMA_MODE_NORMAL or LL_DMA_MODE_CIRCULAR
  • LL_DMA_PERIPH_INCREMENT or LL_DMA_PERIPH_NOINCREMENT
  • LL_DMA_MEMORY_INCREMENT or LL_DMA_MEMORY_NOINCREMENT
  • LL_DMA_PDATAALIGN_BYTE or LL_DMA_PDATAALIGN_HALFWORD or LL_DMA_PDATAALIGN_WORD
  • LL_DMA_MDATAALIGN_BYTE or LL_DMA_MDATAALIGN_HALFWORD or LL_DMA_MDATAALIGN_WORD
  • LL_DMA_PRIORITY_LOW or LL_DMA_PRIORITY_MEDIUM or LL_DMA_PRIORITY_HIGH or LL_DMA_PRIORITY_VERYHIGH
Return values:
None

Definition at line 580 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_CHANNEL.

Referenced by LL_DMA_Init().

__STATIC_INLINE void LL_DMA_DisableChannel | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Disable DMA channel.

Reference Manual to LL API cross reference:
CCR EN LL_DMA_DisableChannel
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 526 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_CHANNEL.

__STATIC_INLINE void LL_DMA_EnableChannel | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Enable DMA channel.

Reference Manual to LL API cross reference:
CCR EN LL_DMA_EnableChannel
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 507 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_CHANNEL.

__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Channel priority level.

Reference Manual to LL API cross reference:
CCR PL LL_DMA_GetChannelPriorityLevel
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_PRIORITY_LOW
  • LL_DMA_PRIORITY_MEDIUM
  • LL_DMA_PRIORITY_HIGH
  • LL_DMA_PRIORITY_VERYHIGH

Definition at line 910 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_CHANNEL.

__STATIC_INLINE uint32_t LL_DMA_GetDataLength | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Number of data to transfer.

Note:
Once the channel is enabled, the return value indicate the remaining bytes to be transmitted.
Reference Manual to LL API cross reference:
CNDTR NDT LL_DMA_GetDataLength
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

Definition at line 955 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_CHANNEL.

__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Data transfer direction (read from peripheral or from memory).

Reference Manual to LL API cross reference:
CCR DIR LL_DMA_GetDataTransferDirection
CCR MEM2MEM LL_DMA_GetDataTransferDirection
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY
  • LL_DMA_DIRECTION_MEMORY_TO_PERIPH
  • LL_DMA_DIRECTION_MEMORY_TO_MEMORY

Definition at line 630 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_CHANNEL.

__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get the Memory to Memory Destination address.

Note:
Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
Reference Manual to LL API cross reference:
CMAR MA LL_DMA_GetM2MDstAddress
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

Definition at line 1164 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_CHANNEL.

__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get the Memory to Memory Source address.

Note:
Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
Reference Manual to LL API cross reference:
CPAR PA LL_DMA_GetM2MSrcAddress
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

Definition at line 1144 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_CHANNEL.

__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Memory address.

Note:
Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
Reference Manual to LL API cross reference:
CMAR MA LL_DMA_GetMemoryAddress
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

Definition at line 1060 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_CHANNEL.

__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Memory increment mode.

Reference Manual to LL API cross reference:
CCR MINC LL_DMA_GetMemoryIncMode
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_MEMORY_INCREMENT
  • LL_DMA_MEMORY_NOINCREMENT

Definition at line 767 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_CHANNEL.

__STATIC_INLINE uint32_t LL_DMA_GetMemorySize | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Memory size.

Reference Manual to LL API cross reference:
CCR MSIZE LL_DMA_GetMemorySize
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_MDATAALIGN_BYTE
  • LL_DMA_MDATAALIGN_HALFWORD
  • LL_DMA_MDATAALIGN_WORD

Definition at line 861 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_CHANNEL.

__STATIC_INLINE uint32_t LL_DMA_GetMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get DMA mode circular or normal.

Reference Manual to LL API cross reference:
CCR CIRC LL_DMA_GetMode
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_MODE_NORMAL
  • LL_DMA_MODE_CIRCULAR

Definition at line 677 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_CHANNEL.

__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Peripheral address.

Note:
Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
Reference Manual to LL API cross reference:
CPAR PA LL_DMA_GetPeriphAddress
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

Definition at line 1080 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_CHANNEL.

__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Peripheral increment mode.

Reference Manual to LL API cross reference:
CCR PINC LL_DMA_GetPeriphIncMode
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_PERIPH_INCREMENT
  • LL_DMA_PERIPH_NOINCREMENT

Definition at line 722 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_CHANNEL.

__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get DMA request for DMA Channels on DMAMUX Channel x.

Note:
DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. #if defined(DMA2) DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. #endif
Reference Manual to LL API cross reference:
CxCR DMAREQ_ID LL_DMA_GetPeriphRequest
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_DMAMUX_REQ_MEM2MEM
  • LL_DMAMUX_REQ_GENERATOR0
  • LL_DMAMUX_REQ_GENERATOR1
  • LL_DMAMUX_REQ_GENERATOR2
  • LL_DMAMUX_REQ_GENERATOR3
  • LL_DMAMUX_REQ_ADC1
  • LL_DMAMUX_REQ_SPI1_RX
  • LL_DMAMUX_REQ_SPI1_TX
  • LL_DMAMUX_REQ_SPI2_RX
  • LL_DMAMUX_REQ_SPI2_TX
  • LL_DMAMUX_REQ_I2C1_RX
  • LL_DMAMUX_REQ_I2C1_TX
  • LL_DMAMUX_REQ_I2C3_RX
  • LL_DMAMUX_REQ_I2C3_TX
  • LL_DMAMUX_REQ_USART1_RX
  • LL_DMAMUX_REQ_USART1_TX
  • LL_DMAMUX_REQ_LPUART1_RX
  • LL_DMAMUX_REQ_LPUART1_TX
  • LL_DMAMUX_REQ_SAI1_A
  • LL_DMAMUX_REQ_SAI1_B
  • LL_DMAMUX_REQ_QUADSPI
  • LL_DMAMUX_REQ_TIM1_CH1
  • LL_DMAMUX_REQ_TIM1_CH2
  • LL_DMAMUX_REQ_TIM1_CH3
  • LL_DMAMUX_REQ_TIM1_CH4
  • LL_DMAMUX_REQ_TIM1_UP
  • LL_DMAMUX_REQ_TIM1_TRIG
  • LL_DMAMUX_REQ_TIM1_COM
  • LL_DMAMUX_REQ_TIM2_CH1
  • LL_DMAMUX_REQ_TIM2_CH2
  • LL_DMAMUX_REQ_TIM2_CH3
  • LL_DMAMUX_REQ_TIM2_CH4
  • LL_DMAMUX_REQ_TIM2_UP
  • LL_DMAMUX_REQ_TIM16_CH1
  • LL_DMAMUX_REQ_TIM16_UP
  • LL_DMAMUX_REQ_TIM17_CH1
  • LL_DMAMUX_REQ_TIM17_UP
  • LL_DMAMUX_REQ_AES1_IN
  • LL_DMAMUX_REQ_AES1_OUT
  • LL_DMAMUX_REQ_AES2_IN
  • LL_DMAMUX_REQ_AES2_OUT

Definition at line 1293 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_DMAMUX_CCR.

__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Peripheral size.

Reference Manual to LL API cross reference:
CCR PSIZE LL_DMA_GetPeriphSize
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_PDATAALIGN_BYTE
  • LL_DMA_PDATAALIGN_HALFWORD
  • LL_DMA_PDATAALIGN_WORD

Definition at line 814 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_CHANNEL.

__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Check if DMA channel is enabled or disabled.

Reference Manual to LL API cross reference:
CCR EN LL_DMA_IsEnabledChannel
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
State of bit (1 or 0).

Definition at line 545 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_CHANNEL.

__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Priority
 | ) |  |

Set Channel priority level.

Reference Manual to LL API cross reference:
CCR PL LL_DMA_SetChannelPriorityLevel
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Priority This parameter can be one of the following values:
  • LL_DMA_PRIORITY_LOW
  • LL_DMA_PRIORITY_MEDIUM
  • LL_DMA_PRIORITY_HIGH
  • LL_DMA_PRIORITY_VERYHIGH
Return values:
None

Definition at line 886 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_CHANNEL.

__STATIC_INLINE void LL_DMA_SetDataLength | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | NbData
 | ) |  |

Set Number of data to transfer.

Note:
This action has no effect if channel is enabled.
Reference Manual to LL API cross reference:
CNDTR NDT LL_DMA_SetDataLength
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
NbData | Between Min_Data = 0 and Max_Data = 0x0000FFFF
Return values:
None

Definition at line 933 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_CHANNEL.

Referenced by LL_DMA_Init().

__STATIC_INLINE void LL_DMA_SetDataTransferDirection | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Direction
 | ) |  |

Set Data transfer direction (read from peripheral or from memory).

Reference Manual to LL API cross reference:
CCR DIR LL_DMA_SetDataTransferDirection
CCR MEM2MEM LL_DMA_SetDataTransferDirection
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Direction This parameter can be one of the following values:
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY
  • LL_DMA_DIRECTION_MEMORY_TO_PERIPH
  • LL_DMA_DIRECTION_MEMORY_TO_MEMORY
Return values:
None

Definition at line 606 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_CHANNEL.

__STATIC_INLINE void LL_DMA_SetM2MDstAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | MemoryAddress
 | ) |  |

Set the Memory to Memory Destination address.

Note:
Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
This API must not be called when the DMA channel is enabled.
Reference Manual to LL API cross reference:
CMAR MA LL_DMA_SetM2MDstAddress
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
MemoryAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Return values:
None

Definition at line 1124 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_CHANNEL.

__STATIC_INLINE void LL_DMA_SetM2MSrcAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | MemoryAddress
 | ) |  |

Set the Memory to Memory Source address.

Note:
Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
This API must not be called when the DMA channel is enabled.
Reference Manual to LL API cross reference:
CPAR PA LL_DMA_SetM2MSrcAddress
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
MemoryAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Return values:
None

Definition at line 1102 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_CHANNEL.

__STATIC_INLINE void LL_DMA_SetMemoryAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | MemoryAddress
 | ) |  |

Set the Memory address.

Note:
Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
This API must not be called when the DMA channel is enabled.
Reference Manual to LL API cross reference:
CMAR MA LL_DMA_SetMemoryAddress
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
MemoryAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Return values:
None

Definition at line 1018 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_CHANNEL.

Referenced by LL_DMA_Init().

__STATIC_INLINE void LL_DMA_SetMemoryIncMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | MemoryOrM2MDstIncMode
 | ) |  |

Set Memory increment mode.

Reference Manual to LL API cross reference:
CCR MINC LL_DMA_SetMemoryIncMode
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
MemoryOrM2MDstIncMode This parameter can be one of the following values:
  • LL_DMA_MEMORY_INCREMENT
  • LL_DMA_MEMORY_NOINCREMENT
Return values:
None

Definition at line 745 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_CHANNEL.

__STATIC_INLINE void LL_DMA_SetMemorySize | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | MemoryOrM2MDstDataSize
 | ) |  |

Set Memory size.

Reference Manual to LL API cross reference:
CCR MSIZE LL_DMA_SetMemorySize
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
MemoryOrM2MDstDataSize This parameter can be one of the following values:
  • LL_DMA_MDATAALIGN_BYTE
  • LL_DMA_MDATAALIGN_HALFWORD
  • LL_DMA_MDATAALIGN_WORD
Return values:
None

Definition at line 838 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_CHANNEL.

__STATIC_INLINE void LL_DMA_SetMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Mode
 | ) |  |

Set DMA mode circular or normal.

Note:
The circular buffer mode cannot be used if the memory-to-memory data transfer is configured on the selected Channel.
Reference Manual to LL API cross reference:
CCR CIRC LL_DMA_SetMode
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Mode This parameter can be one of the following values:
  • LL_DMA_MODE_NORMAL
  • LL_DMA_MODE_CIRCULAR
Return values:
None

Definition at line 655 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_CHANNEL.

__STATIC_INLINE void LL_DMA_SetPeriphAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | PeriphAddress
 | ) |  |

Set the Peripheral address.

Note:
Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
This API must not be called when the DMA channel is enabled.
Reference Manual to LL API cross reference:
CPAR PA LL_DMA_SetPeriphAddress
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
PeriphAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Return values:
None

Definition at line 1040 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_CHANNEL.

Referenced by LL_DMA_Init().

__STATIC_INLINE void LL_DMA_SetPeriphIncMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | PeriphOrM2MSrcIncMode
 | ) |  |

Set Peripheral increment mode.

Reference Manual to LL API cross reference:
CCR PINC LL_DMA_SetPeriphIncMode
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
PeriphOrM2MSrcIncMode This parameter can be one of the following values:
  • LL_DMA_PERIPH_INCREMENT
  • LL_DMA_PERIPH_NOINCREMENT
Return values:
None

Definition at line 700 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_CHANNEL.

__STATIC_INLINE void LL_DMA_SetPeriphRequest | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Request
 | ) |  |

Set DMA request for DMA Channels on DMAMUX Channel x.

Note:
DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. #if defined(DMA2) DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. #endif
Reference Manual to LL API cross reference:
CxCR DMAREQ_ID LL_DMA_SetPeriphRequest
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Request This parameter can be one of the following values:
  • LL_DMAMUX_REQ_MEM2MEM
  • LL_DMAMUX_REQ_GENERATOR0
  • LL_DMAMUX_REQ_GENERATOR1
  • LL_DMAMUX_REQ_GENERATOR2
  • LL_DMAMUX_REQ_GENERATOR3
  • LL_DMAMUX_REQ_ADC1
  • LL_DMAMUX_REQ_SPI1_RX
  • LL_DMAMUX_REQ_SPI1_TX
  • LL_DMAMUX_REQ_SPI2_RX
  • LL_DMAMUX_REQ_SPI2_TX
  • LL_DMAMUX_REQ_I2C1_RX
  • LL_DMAMUX_REQ_I2C1_TX
  • LL_DMAMUX_REQ_I2C3_RX
  • LL_DMAMUX_REQ_I2C3_TX
  • LL_DMAMUX_REQ_USART1_RX
  • LL_DMAMUX_REQ_USART1_TX
  • LL_DMAMUX_REQ_LPUART1_RX
  • LL_DMAMUX_REQ_LPUART1_TX
  • LL_DMAMUX_REQ_SAI1_A
  • LL_DMAMUX_REQ_SAI1_B
  • LL_DMAMUX_REQ_QUADSPI
  • LL_DMAMUX_REQ_TIM1_CH1
  • LL_DMAMUX_REQ_TIM1_CH2
  • LL_DMAMUX_REQ_TIM1_CH3
  • LL_DMAMUX_REQ_TIM1_CH4
  • LL_DMAMUX_REQ_TIM1_UP
  • LL_DMAMUX_REQ_TIM1_TRIG
  • LL_DMAMUX_REQ_TIM1_COM
  • LL_DMAMUX_REQ_TIM2_CH1
  • LL_DMAMUX_REQ_TIM2_CH2
  • LL_DMAMUX_REQ_TIM2_CH3
  • LL_DMAMUX_REQ_TIM2_CH4
  • LL_DMAMUX_REQ_TIM2_UP
  • LL_DMAMUX_REQ_TIM16_CH1
  • LL_DMAMUX_REQ_TIM16_UP
  • LL_DMAMUX_REQ_TIM17_CH1
  • LL_DMAMUX_REQ_TIM17_UP
  • LL_DMAMUX_REQ_AES1_IN
  • LL_DMAMUX_REQ_AES1_OUT
  • LL_DMAMUX_REQ_AES2_IN
  • LL_DMAMUX_REQ_AES2_OUT
Return values:
None

Definition at line 1229 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_DMAMUX_CCR.

Referenced by LL_DMA_DeInit(), and LL_DMA_Init().

__STATIC_INLINE void LL_DMA_SetPeriphSize | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | PeriphOrM2MSrcDataSize
 | ) |  |

Set Peripheral size.

Reference Manual to LL API cross reference:
CCR PSIZE LL_DMA_SetPeriphSize
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
PeriphOrM2MSrcDataSize This parameter can be one of the following values:
  • LL_DMA_PDATAALIGN_BYTE
  • LL_DMA_PDATAALIGN_HALFWORD
  • LL_DMA_PDATAALIGN_WORD
Return values:
None

Definition at line 791 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_CHANNEL.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FLAG_Management

Functions
FLAG_Management
DMA Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI1 (DMA_TypeDef *DMAx)
Get Channel 1 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI2 (DMA_TypeDef *DMAx)
Get Channel 2 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI3 (DMA_TypeDef *DMAx)
Get Channel 3 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI4 (DMA_TypeDef *DMAx)
Get Channel 4 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI5 (DMA_TypeDef *DMAx)
Get Channel 5 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI6 (DMA_TypeDef *DMAx)
Get Channel 6 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI7 (DMA_TypeDef *DMAx)
Get Channel 7 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC1 (DMA_TypeDef *DMAx)
Get Channel 1 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC2 (DMA_TypeDef *DMAx)
Get Channel 2 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC3 (DMA_TypeDef *DMAx)
Get Channel 3 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC4 (DMA_TypeDef *DMAx)
Get Channel 4 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC5 (DMA_TypeDef *DMAx)
Get Channel 5 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC6 (DMA_TypeDef *DMAx)
Get Channel 6 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC7 (DMA_TypeDef *DMAx)
Get Channel 7 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT1 (DMA_TypeDef *DMAx)
Get Channel 1 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT2 (DMA_TypeDef *DMAx)
Get Channel 2 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT3 (DMA_TypeDef *DMAx)
Get Channel 3 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT4 (DMA_TypeDef *DMAx)
Get Channel 4 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT5 (DMA_TypeDef *DMAx)
Get Channel 5 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT6 (DMA_TypeDef *DMAx)
Get Channel 6 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT7 (DMA_TypeDef *DMAx)
Get Channel 7 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE1 (DMA_TypeDef *DMAx)
Get Channel 1 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE2 (DMA_TypeDef *DMAx)
Get Channel 2 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE3 (DMA_TypeDef *DMAx)
Get Channel 3 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE4 (DMA_TypeDef *DMAx)
Get Channel 4 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE5 (DMA_TypeDef *DMAx)
Get Channel 5 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE6 (DMA_TypeDef *DMAx)
Get Channel 6 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE7 (DMA_TypeDef *DMAx)
Get Channel 7 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI1 (DMA_TypeDef *DMAx)
Clear Channel 1 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI2 (DMA_TypeDef *DMAx)
Clear Channel 2 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI3 (DMA_TypeDef *DMAx)
Clear Channel 3 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI4 (DMA_TypeDef *DMAx)
Clear Channel 4 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI5 (DMA_TypeDef *DMAx)
Clear Channel 5 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI6 (DMA_TypeDef *DMAx)
Clear Channel 6 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI7 (DMA_TypeDef *DMAx)
Clear Channel 7 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC1 (DMA_TypeDef *DMAx)
Clear Channel 1 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC2 (DMA_TypeDef *DMAx)
Clear Channel 2 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC3 (DMA_TypeDef *DMAx)
Clear Channel 3 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC4 (DMA_TypeDef *DMAx)
Clear Channel 4 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC5 (DMA_TypeDef *DMAx)
Clear Channel 5 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC6 (DMA_TypeDef *DMAx)
Clear Channel 6 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC7 (DMA_TypeDef *DMAx)
Clear Channel 7 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT1 (DMA_TypeDef *DMAx)
Clear Channel 1 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT2 (DMA_TypeDef *DMAx)
Clear Channel 2 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT3 (DMA_TypeDef *DMAx)
Clear Channel 3 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT4 (DMA_TypeDef *DMAx)
Clear Channel 4 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT5 (DMA_TypeDef *DMAx)
Clear Channel 5 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT6 (DMA_TypeDef *DMAx)
Clear Channel 6 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT7 (DMA_TypeDef *DMAx)
Clear Channel 7 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE1 (DMA_TypeDef *DMAx)
Clear Channel 1 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE2 (DMA_TypeDef *DMAx)
Clear Channel 2 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE3 (DMA_TypeDef *DMAx)
Clear Channel 3 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE4 (DMA_TypeDef *DMAx)
Clear Channel 4 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE5 (DMA_TypeDef *DMAx)
Clear Channel 5 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE6 (DMA_TypeDef *DMAx)
Clear Channel 6 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE7 (DMA_TypeDef *DMAx)
Clear Channel 7 transfer error flag.

Function Documentation

__STATIC_INLINE void LL_DMA_ClearFlag_GI1 ( DMA_TypeDef * DMAx )

Clear Channel 1 global interrupt flag.

Reference Manual to LL API cross reference:
IFCR CGIF1 LL_DMA_ClearFlag_GI1
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1620 of file stm32wbxx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_GI2 ( DMA_TypeDef * DMAx )

Clear Channel 2 global interrupt flag.

Reference Manual to LL API cross reference:
IFCR CGIF2 LL_DMA_ClearFlag_GI2
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1631 of file stm32wbxx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_GI3 ( DMA_TypeDef * DMAx )

Clear Channel 3 global interrupt flag.

Reference Manual to LL API cross reference:
IFCR CGIF3 LL_DMA_ClearFlag_GI3
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1642 of file stm32wbxx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_GI4 ( DMA_TypeDef * DMAx )

Clear Channel 4 global interrupt flag.

Reference Manual to LL API cross reference:
IFCR CGIF4 LL_DMA_ClearFlag_GI4
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1653 of file stm32wbxx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_GI5 ( DMA_TypeDef * DMAx )

Clear Channel 5 global interrupt flag.

Reference Manual to LL API cross reference:
IFCR CGIF5 LL_DMA_ClearFlag_GI5
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1664 of file stm32wbxx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_GI6 ( DMA_TypeDef * DMAx )

Clear Channel 6 global interrupt flag.

Reference Manual to LL API cross reference:
IFCR CGIF6 LL_DMA_ClearFlag_GI6
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1675 of file stm32wbxx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_GI7 ( DMA_TypeDef * DMAx )

Clear Channel 7 global interrupt flag.

Reference Manual to LL API cross reference:
IFCR CGIF7 LL_DMA_ClearFlag_GI7
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1686 of file stm32wbxx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_HT1 ( DMA_TypeDef * DMAx )

Clear Channel 1 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF1 LL_DMA_ClearFlag_HT1
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1774 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT2 ( DMA_TypeDef * DMAx )

Clear Channel 2 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF2 LL_DMA_ClearFlag_HT2
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1785 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT3 ( DMA_TypeDef * DMAx )

Clear Channel 3 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF3 LL_DMA_ClearFlag_HT3
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1796 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT4 ( DMA_TypeDef * DMAx )

Clear Channel 4 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF4 LL_DMA_ClearFlag_HT4
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1807 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT5 ( DMA_TypeDef * DMAx )

Clear Channel 5 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF5 LL_DMA_ClearFlag_HT5
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1818 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT6 ( DMA_TypeDef * DMAx )

Clear Channel 6 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF6 LL_DMA_ClearFlag_HT6
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1829 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT7 ( DMA_TypeDef * DMAx )

Clear Channel 7 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF7 LL_DMA_ClearFlag_HT7
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1840 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC1 ( DMA_TypeDef * DMAx )

Clear Channel 1 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF1 LL_DMA_ClearFlag_TC1
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1697 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC2 ( DMA_TypeDef * DMAx )

Clear Channel 2 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF2 LL_DMA_ClearFlag_TC2
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1708 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC3 ( DMA_TypeDef * DMAx )

Clear Channel 3 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF3 LL_DMA_ClearFlag_TC3
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1719 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC4 ( DMA_TypeDef * DMAx )

Clear Channel 4 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF4 LL_DMA_ClearFlag_TC4
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1730 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC5 ( DMA_TypeDef * DMAx )

Clear Channel 5 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF5 LL_DMA_ClearFlag_TC5
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1741 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC6 ( DMA_TypeDef * DMAx )

Clear Channel 6 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF6 LL_DMA_ClearFlag_TC6
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1752 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC7 ( DMA_TypeDef * DMAx )

Clear Channel 7 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF7 LL_DMA_ClearFlag_TC7
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1763 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE1 ( DMA_TypeDef * DMAx )

Clear Channel 1 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF1 LL_DMA_ClearFlag_TE1
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1851 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE2 ( DMA_TypeDef * DMAx )

Clear Channel 2 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF2 LL_DMA_ClearFlag_TE2
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1862 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE3 ( DMA_TypeDef * DMAx )

Clear Channel 3 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF3 LL_DMA_ClearFlag_TE3
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1873 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE4 ( DMA_TypeDef * DMAx )

Clear Channel 4 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF4 LL_DMA_ClearFlag_TE4
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1884 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE5 ( DMA_TypeDef * DMAx )

Clear Channel 5 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF5 LL_DMA_ClearFlag_TE5
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1895 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE6 ( DMA_TypeDef * DMAx )

Clear Channel 6 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF6 LL_DMA_ClearFlag_TE6
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1906 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE7 ( DMA_TypeDef * DMAx )

Clear Channel 7 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF7 LL_DMA_ClearFlag_TE7
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1917 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1 ( DMA_TypeDef * DMAx )

Get Channel 1 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF1 LL_DMA_IsActiveFlag_GI1
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1312 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2 ( DMA_TypeDef * DMAx )

Get Channel 2 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF2 LL_DMA_IsActiveFlag_GI2
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1323 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3 ( DMA_TypeDef * DMAx )

Get Channel 3 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF3 LL_DMA_IsActiveFlag_GI3
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1334 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4 ( DMA_TypeDef * DMAx )

Get Channel 4 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF4 LL_DMA_IsActiveFlag_GI4
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1345 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5 ( DMA_TypeDef * DMAx )

Get Channel 5 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF5 LL_DMA_IsActiveFlag_GI5
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1356 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6 ( DMA_TypeDef * DMAx )

Get Channel 6 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF6 LL_DMA_IsActiveFlag_GI6
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1367 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7 ( DMA_TypeDef * DMAx )

Get Channel 7 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF7 LL_DMA_IsActiveFlag_GI7
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1378 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1 ( DMA_TypeDef * DMAx )

Get Channel 1 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF1 LL_DMA_IsActiveFlag_HT1
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1466 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2 ( DMA_TypeDef * DMAx )

Get Channel 2 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF2 LL_DMA_IsActiveFlag_HT2
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1477 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3 ( DMA_TypeDef * DMAx )

Get Channel 3 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF3 LL_DMA_IsActiveFlag_HT3
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1488 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4 ( DMA_TypeDef * DMAx )

Get Channel 4 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF4 LL_DMA_IsActiveFlag_HT4
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1499 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5 ( DMA_TypeDef * DMAx )

Get Channel 5 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF5 LL_DMA_IsActiveFlag_HT5
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1510 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6 ( DMA_TypeDef * DMAx )

Get Channel 6 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF6 LL_DMA_IsActiveFlag_HT6
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1521 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7 ( DMA_TypeDef * DMAx )

Get Channel 7 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF7 LL_DMA_IsActiveFlag_HT7
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1532 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1 ( DMA_TypeDef * DMAx )

Get Channel 1 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF1 LL_DMA_IsActiveFlag_TC1
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1389 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2 ( DMA_TypeDef * DMAx )

Get Channel 2 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF2 LL_DMA_IsActiveFlag_TC2
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1400 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3 ( DMA_TypeDef * DMAx )

Get Channel 3 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF3 LL_DMA_IsActiveFlag_TC3
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1411 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4 ( DMA_TypeDef * DMAx )

Get Channel 4 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF4 LL_DMA_IsActiveFlag_TC4
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1422 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5 ( DMA_TypeDef * DMAx )

Get Channel 5 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF5 LL_DMA_IsActiveFlag_TC5
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1433 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6 ( DMA_TypeDef * DMAx )

Get Channel 6 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF6 LL_DMA_IsActiveFlag_TC6
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1444 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7 ( DMA_TypeDef * DMAx )

Get Channel 7 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF7 LL_DMA_IsActiveFlag_TC7
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1455 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1 ( DMA_TypeDef * DMAx )

Get Channel 1 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF1 LL_DMA_IsActiveFlag_TE1
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1543 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2 ( DMA_TypeDef * DMAx )

Get Channel 2 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF2 LL_DMA_IsActiveFlag_TE2
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1554 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3 ( DMA_TypeDef * DMAx )

Get Channel 3 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF3 LL_DMA_IsActiveFlag_TE3
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1565 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4 ( DMA_TypeDef * DMAx )

Get Channel 4 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF4 LL_DMA_IsActiveFlag_TE4
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1576 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5 ( DMA_TypeDef * DMAx )

Get Channel 5 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF5 LL_DMA_IsActiveFlag_TE5
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1587 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6 ( DMA_TypeDef * DMAx )

Get Channel 6 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF6 LL_DMA_IsActiveFlag_TE6
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1598 of file stm32wbxx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7 ( DMA_TypeDef * DMAx )

Get Channel 7 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF7 LL_DMA_IsActiveFlag_TE7
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1609 of file stm32wbxx_ll_dma.h.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IT_Management

Functions
IT_Management
DMA Exported Functions

Functions

__STATIC_INLINE void | LL_DMA_EnableIT_TC (DMA_TypeDef *DMAx, uint32_t Channel)
Enable Transfer complete interrupt.
__STATIC_INLINE void | LL_DMA_EnableIT_HT (DMA_TypeDef *DMAx, uint32_t Channel)
Enable Half transfer interrupt.
__STATIC_INLINE void | LL_DMA_EnableIT_TE (DMA_TypeDef *DMAx, uint32_t Channel)
Enable Transfer error interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_TC (DMA_TypeDef *DMAx, uint32_t Channel)
Disable Transfer complete interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_HT (DMA_TypeDef *DMAx, uint32_t Channel)
Disable Half transfer interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_TE (DMA_TypeDef *DMAx, uint32_t Channel)
Disable Transfer error interrupt.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_TC (DMA_TypeDef *DMAx, uint32_t Channel)
Check if Transfer complete Interrupt is enabled.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_HT (DMA_TypeDef *DMAx, uint32_t Channel)
Check if Half transfer Interrupt is enabled.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_TE (DMA_TypeDef *DMAx, uint32_t Channel)
Check if Transfer error Interrupt is enabled.

Function Documentation

__STATIC_INLINE void LL_DMA_DisableIT_HT | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Disable Half transfer interrupt.

Reference Manual to LL API cross reference:
CCR HTIE LL_DMA_DisableIT_HT
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 2019 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_CHANNEL.

__STATIC_INLINE void LL_DMA_DisableIT_TC | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Disable Transfer complete interrupt.

Reference Manual to LL API cross reference:
CCR TCIE LL_DMA_DisableIT_TC
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 2000 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_CHANNEL.

__STATIC_INLINE void LL_DMA_DisableIT_TE | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Disable Transfer error interrupt.

Reference Manual to LL API cross reference:
CCR TEIE LL_DMA_DisableIT_TE
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 2038 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_CHANNEL.

__STATIC_INLINE void LL_DMA_EnableIT_HT | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Enable Half transfer interrupt.

Reference Manual to LL API cross reference:
CCR HTIE LL_DMA_EnableIT_HT
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 1962 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_CHANNEL.

__STATIC_INLINE void LL_DMA_EnableIT_TC | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Enable Transfer complete interrupt.

Reference Manual to LL API cross reference:
CCR TCIE LL_DMA_EnableIT_TC
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 1943 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_CHANNEL.

__STATIC_INLINE void LL_DMA_EnableIT_TE | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Enable Transfer error interrupt.

Reference Manual to LL API cross reference:
CCR TEIE LL_DMA_EnableIT_TE
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 1981 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_CHANNEL.

__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Check if Half transfer Interrupt is enabled.

Reference Manual to LL API cross reference:
CCR HTIE LL_DMA_IsEnabledIT_HT
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
State of bit (1 or 0).

Definition at line 2077 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_CHANNEL.

__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Check if Transfer complete Interrupt is enabled.

Reference Manual to LL API cross reference:
CCR TCIE LL_DMA_IsEnabledIT_TC
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
State of bit (1 or 0).

Definition at line 2057 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_CHANNEL.

__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Check if Transfer error Interrupt is enabled.

Reference Manual to LL API cross reference:
CCR TEIE LL_DMA_IsEnabledIT_TE
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
State of bit (1 or 0).

Definition at line 2097 of file stm32wbxx_ll_dma.h.

References __LL_DMA_INSTANCE_TO_CHANNEL.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
DMA Exported Functions

Functions

ErrorStatus | LL_DMA_DeInit (DMA_TypeDef *DMAx, uint32_t Channel)
De-initialize the DMA registers to their default reset values.
ErrorStatus | LL_DMA_Init (DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
void | LL_DMA_StructInit (LL_DMA_InitTypeDef *DMA_InitStruct)
Set each LL_DMA_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_DMA_DeInit | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

De-initialize the DMA registers to their default reset values.

Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
  • LL_DMA_CHANNEL_ALL
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: DMA registers are de-initialized
  • ERROR: DMA registers are not de-initialized

Definition at line 152 of file stm32wbxx_ll_dma.c.

References __LL_DMA_GET_CHANNEL_INSTANCE, assert_param, IS_LL_DMA_ALL_CHANNEL_INSTANCE, LL_AHB1_GRP1_ForceReset(), LL_AHB1_GRP1_PERIPH_DMA1, LL_AHB1_GRP1_PERIPH_DMA2, LL_AHB1_GRP1_ReleaseReset(), LL_DMA_CHANNEL_1, LL_DMA_CHANNEL_2, LL_DMA_CHANNEL_3, LL_DMA_CHANNEL_4, LL_DMA_CHANNEL_5, LL_DMA_CHANNEL_6, LL_DMA_CHANNEL_7, LL_DMA_CHANNEL_ALL, LL_DMA_ClearFlag_GI1(), LL_DMA_ClearFlag_GI2(), LL_DMA_ClearFlag_GI3(), LL_DMA_ClearFlag_GI4(), LL_DMA_ClearFlag_GI5(), LL_DMA_ClearFlag_GI6(), LL_DMA_ClearFlag_GI7(), LL_DMA_SetPeriphRequest(), and LL_DMAMUX_REQ_MEM2MEM.

ErrorStatus LL_DMA_Init | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | LL_DMA_InitTypeDef * | DMA_InitStruct
 | ) |  |

Initialize the DMA registers according to the specified parameters in DMA_InitStruct.

Note:
To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
  • __LL_DMA_GET_INSTANCE
  • __LL_DMA_GET_CHANNEL
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
DMA_InitStruct | pointer to a LL_DMA_InitTypeDef structure.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: DMA registers are initialized
  • ERROR: Not applicable

Definition at line 268 of file stm32wbxx_ll_dma.c.

References assert_param, LL_DMA_InitTypeDef::Direction, IS_LL_DMA_ALL_CHANNEL_INSTANCE, IS_LL_DMA_DIRECTION, IS_LL_DMA_MEMORYDATASIZE, IS_LL_DMA_MEMORYINCMODE, IS_LL_DMA_MODE, IS_LL_DMA_NBDATA, IS_LL_DMA_PERIPHDATASIZE, IS_LL_DMA_PERIPHINCMODE, IS_LL_DMA_PERIPHREQUEST, IS_LL_DMA_PRIORITY, LL_DMA_ConfigTransfer(), LL_DMA_SetDataLength(), LL_DMA_SetMemoryAddress(), LL_DMA_SetPeriphAddress(), LL_DMA_SetPeriphRequest(), LL_DMA_InitTypeDef::MemoryOrM2MDstAddress, LL_DMA_InitTypeDef::MemoryOrM2MDstDataSize, LL_DMA_InitTypeDef::MemoryOrM2MDstIncMode, LL_DMA_InitTypeDef::Mode, LL_DMA_InitTypeDef::NbData, LL_DMA_InitTypeDef::PeriphOrM2MSrcAddress, LL_DMA_InitTypeDef::PeriphOrM2MSrcDataSize, LL_DMA_InitTypeDef::PeriphOrM2MSrcIncMode, LL_DMA_InitTypeDef::PeriphRequest, and LL_DMA_InitTypeDef::Priority.

void LL_DMA_StructInit ( LL_DMA_InitTypeDef * DMA_InitStruct )

Set each LL_DMA_InitTypeDef field to default value.

Parameters:
DMA_InitStruct Pointer to a LL_DMA_InitTypeDef structure.
Return values:
None

Definition at line 336 of file stm32wbxx_ll_dma.c.

References LL_DMA_InitTypeDef::Direction, LL_DMA_DIRECTION_PERIPH_TO_MEMORY, LL_DMA_MDATAALIGN_BYTE, LL_DMA_MEMORY_NOINCREMENT, LL_DMA_MODE_NORMAL, LL_DMA_PDATAALIGN_BYTE, LL_DMA_PERIPH_NOINCREMENT, LL_DMA_PRIORITY_LOW, LL_DMAMUX_REQ_MEM2MEM, LL_DMA_InitTypeDef::MemoryOrM2MDstAddress, LL_DMA_InitTypeDef::MemoryOrM2MDstDataSize, LL_DMA_InitTypeDef::MemoryOrM2MDstIncMode, LL_DMA_InitTypeDef::Mode, LL_DMA_InitTypeDef::NbData, LL_DMA_InitTypeDef::PeriphOrM2MSrcAddress, LL_DMA_InitTypeDef::PeriphOrM2MSrcDataSize, LL_DMA_InitTypeDef::PeriphOrM2MSrcIncMode, LL_DMA_InitTypeDef::PeriphRequest, and LL_DMA_InitTypeDef::Priority.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DMAMUX

Modules
DMAMUX
STM32WBxx_LL_Driver

Modules

DMAMUX Private Constants
DMAMUX Exported Constants
DMAMUX Exported Macros
DMAMUX Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for DMAMUX registers.

Register | Bit | Function
CFR | CSOF0 | LL_DMAMUX_ClearFlag_SO0
 | CSOF1 | LL_DMAMUX_ClearFlag_SO1
 | CSOF10 | LL_DMAMUX_ClearFlag_SO10
 | CSOF11 | LL_DMAMUX_ClearFlag_SO11
 | CSOF12 | LL_DMAMUX_ClearFlag_SO12
 | CSOF13 | LL_DMAMUX_ClearFlag_SO13
 | CSOF2 | LL_DMAMUX_ClearFlag_SO2
 | CSOF3 | LL_DMAMUX_ClearFlag_SO3
 | CSOF4 | LL_DMAMUX_ClearFlag_SO4
 | CSOF5 | LL_DMAMUX_ClearFlag_SO5
 | CSOF6 | LL_DMAMUX_ClearFlag_SO6
 | CSOF7 | LL_DMAMUX_ClearFlag_SO7
 | CSOF8 | LL_DMAMUX_ClearFlag_SO8
 | CSOF9 | LL_DMAMUX_ClearFlag_SO9
CSR | SOF0 | LL_DMAMUX_IsActiveFlag_SO0
 | SOF1 | LL_DMAMUX_IsActiveFlag_SO1
 | SOF10 | LL_DMAMUX_IsActiveFlag_SO10
 | SOF11 | LL_DMAMUX_IsActiveFlag_SO11
 | SOF12 | LL_DMAMUX_IsActiveFlag_SO12
 | SOF13 | LL_DMAMUX_IsActiveFlag_SO13
 | SOF2 | LL_DMAMUX_IsActiveFlag_SO2
 | SOF3 | LL_DMAMUX_IsActiveFlag_SO3
 | SOF4 | LL_DMAMUX_IsActiveFlag_SO4
 | SOF5 | LL_DMAMUX_IsActiveFlag_SO5
 | SOF6 | LL_DMAMUX_IsActiveFlag_SO6
 | SOF7 | LL_DMAMUX_IsActiveFlag_SO7
 | SOF8 | LL_DMAMUX_IsActiveFlag_SO8
 | SOF9 | LL_DMAMUX_IsActiveFlag_SO9
CxCR | DMAREQ_ID | LL_DMAMUX_GetRequestID
 |  | LL_DMAMUX_SetRequestID
 | EGE | LL_DMAMUX_DisableEventGeneration
 |  | LL_DMAMUX_EnableEventGeneration
 |  | LL_DMAMUX_IsEnabledEventGeneration
 | NBREQ | LL_DMAMUX_GetSyncRequestNb
 |  | LL_DMAMUX_SetSyncRequestNb
 | SE | LL_DMAMUX_DisableSync
 |  | LL_DMAMUX_EnableSync
 |  | LL_DMAMUX_IsEnabledSync
 | SOIE | LL_DMAMUX_DisableIT_SO
 |  | LL_DMAMUX_EnableIT_SO
 |  | LL_DMAMUX_IsEnabledIT_SO
 | SPOL | LL_DMAMUX_GetSyncPolarity
 |  | LL_DMAMUX_SetSyncPolarity
 | SYNC_ID | LL_DMAMUX_GetSyncID
 |  | LL_DMAMUX_SetSyncID
RGCFR | COF0 | LL_DMAMUX_ClearFlag_RGO0
 | COF1 | LL_DMAMUX_ClearFlag_RGO1
 | COF2 | LL_DMAMUX_ClearFlag_RGO2
 | COF3 | LL_DMAMUX_ClearFlag_RGO3
RGSR | OF0 | LL_DMAMUX_IsActiveFlag_RGO0
 | OF1 | LL_DMAMUX_IsActiveFlag_RGO1
 | OF2 | LL_DMAMUX_IsActiveFlag_RGO2
 | OF3 | LL_DMAMUX_IsActiveFlag_RGO3
RGxCR | GE | LL_DMAMUX_DisableRequestGen
 |  | LL_DMAMUX_EnableRequestGen
 |  | LL_DMAMUX_IsEnabledRequestGen
 | GNBREQ | LL_DMAMUX_GetGenRequestNb
 |  | LL_DMAMUX_SetGenRequestNb
 | GPOL | LL_DMAMUX_GetRequestGenPolarity
 |  | LL_DMAMUX_SetRequestGenPolarity
 | OIE | LL_DMAMUX_DisableIT_RGO
 |  | LL_DMAMUX_EnableIT_RGO
 |  | LL_DMAMUX_IsEnabledIT_RGO
 | SIG_ID | LL_DMAMUX_GetRequestSignalID
 |  | LL_DMAMUX_SetRequestSignalID
Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DMAMUX Private Constants

Defines
DMAMUX Private Constants
DMAMUX

Defines

#define | DMAMUX_CCR_SIZE 0x00000004UL
#define | DMAMUX_RGCR_SIZE 0x00000004UL

Define Documentation

#define DMAMUX_CCR_SIZE 0x00000004UL

Definition at line 48 of file stm32wbxx_ll_dmamux.h.

#define DMAMUX_RGCR_SIZE 0x00000004UL

Definition at line 51 of file stm32wbxx_ll_dmamux.h.

Referenced by LL_DMAMUX_DisableRequestGen(), LL_DMAMUX_EnableRequestGen(), LL_DMAMUX_GetGenRequestNb(), LL_DMAMUX_GetRequestGenPolarity(), LL_DMAMUX_GetRequestSignalID(), LL_DMAMUX_IsEnabledRequestGen(), LL_DMAMUX_SetGenRequestNb(), LL_DMAMUX_SetRequestGenPolarity(), and LL_DMAMUX_SetRequestSignalID().

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
DMAMUX Exported Constants

Flags defines which can be used with LL_DMAMUX_WriteReg function. More...

Defines

#define | LL_DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0
#define | LL_DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1
#define | LL_DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2
#define | LL_DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3
#define | LL_DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4
#define | LL_DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5
#define | LL_DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6
#define | LL_DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7
#define | LL_DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8
#define | LL_DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9
#define | LL_DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10
#define | LL_DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11
#define | LL_DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12
#define | LL_DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13
#define | LL_DMAMUX_RGCFR_RGCOF0 DMAMUX_RGCFR_COF0
#define | LL_DMAMUX_RGCFR_RGCOF1 DMAMUX_RGCFR_COF1
#define | LL_DMAMUX_RGCFR_RGCOF2 DMAMUX_RGCFR_COF2
#define | LL_DMAMUX_RGCFR_RGCOF3 DMAMUX_RGCFR_COF3

Detailed Description

Flags defines which can be used with LL_DMAMUX_WriteReg function.

Define Documentation

#define LL_DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0

Synchronization Event Overrun Flag Channel 0

Definition at line 66 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1

Synchronization Event Overrun Flag Channel 1

Definition at line 67 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10

Synchronization Event Overrun Flag Channel 10

Definition at line 77 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11

Synchronization Event Overrun Flag Channel 11

Definition at line 78 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12

Synchronization Event Overrun Flag Channel 12

Definition at line 79 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13

Synchronization Event Overrun Flag Channel 13

Definition at line 80 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2

Synchronization Event Overrun Flag Channel 2

Definition at line 68 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3

Synchronization Event Overrun Flag Channel 3

Definition at line 69 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4

Synchronization Event Overrun Flag Channel 4

Definition at line 70 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5

Synchronization Event Overrun Flag Channel 5

Definition at line 71 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6

Synchronization Event Overrun Flag Channel 6

Definition at line 72 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7

Synchronization Event Overrun Flag Channel 7

Definition at line 74 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8

Synchronization Event Overrun Flag Channel 8

Definition at line 75 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9

Synchronization Event Overrun Flag Channel 9

Definition at line 76 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_RGCFR_RGCOF0 DMAMUX_RGCFR_COF0

Request Generator 0 Trigger Event Overrun Flag

Definition at line 82 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_RGCFR_RGCOF1 DMAMUX_RGCFR_COF1

Request Generator 1 Trigger Event Overrun Flag

Definition at line 83 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_RGCFR_RGCOF2 DMAMUX_RGCFR_COF2

Request Generator 2 Trigger Event Overrun Flag

Definition at line 84 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_RGCFR_RGCOF3 DMAMUX_RGCFR_COF3

Request Generator 3 Trigger Event Overrun Flag

Definition at line 85 of file stm32wbxx_ll_dmamux.h.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
DMAMUX Exported Constants

Flags defines which can be used with LL_DMAMUX_ReadReg function. More...

Defines

#define | LL_DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0
#define | LL_DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1
#define | LL_DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2
#define | LL_DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3
#define | LL_DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4
#define | LL_DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5
#define | LL_DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6
#define | LL_DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7
#define | LL_DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8
#define | LL_DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9
#define | LL_DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10
#define | LL_DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11
#define | LL_DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12
#define | LL_DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13
#define | LL_DMAMUX_RGSR_RGOF0 DMAMUX_RGSR_OF0
#define | LL_DMAMUX_RGSR_RGOF1 DMAMUX_RGSR_OF1
#define | LL_DMAMUX_RGSR_RGOF2 DMAMUX_RGSR_OF2
#define | LL_DMAMUX_RGSR_RGOF3 DMAMUX_RGSR_OF3

Detailed Description

Flags defines which can be used with LL_DMAMUX_ReadReg function.

Define Documentation

#define LL_DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0

Synchronization Event Overrun Flag Channel 0

Definition at line 94 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1

Synchronization Event Overrun Flag Channel 1

Definition at line 95 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10

Synchronization Event Overrun Flag Channel 10

Definition at line 105 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11

Synchronization Event Overrun Flag Channel 11

Definition at line 106 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12

Synchronization Event Overrun Flag Channel 12

Definition at line 107 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13

Synchronization Event Overrun Flag Channel 13

Definition at line 108 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2

Synchronization Event Overrun Flag Channel 2

Definition at line 96 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3

Synchronization Event Overrun Flag Channel 3

Definition at line 97 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4

Synchronization Event Overrun Flag Channel 4

Definition at line 98 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5

Synchronization Event Overrun Flag Channel 5

Definition at line 99 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6

Synchronization Event Overrun Flag Channel 6

Definition at line 100 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7

Synchronization Event Overrun Flag Channel 7

Definition at line 102 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8

Synchronization Event Overrun Flag Channel 8

Definition at line 103 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9

Synchronization Event Overrun Flag Channel 9

Definition at line 104 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_RGSR_RGOF0 DMAMUX_RGSR_OF0

Request Generator 0 Trigger Event Overrun Flag

Definition at line 110 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_RGSR_RGOF1 DMAMUX_RGSR_OF1

Request Generator 1 Trigger Event Overrun Flag

Definition at line 111 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_RGSR_RGOF2 DMAMUX_RGSR_OF2

Request Generator 2 Trigger Event Overrun Flag

Definition at line 112 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_RGSR_RGOF3 DMAMUX_RGSR_OF3

Request Generator 3 Trigger Event Overrun Flag

Definition at line 113 of file stm32wbxx_ll_dmamux.h.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IT Defines

Defines
IT Defines
DMAMUX Exported Constants

IT defines which can be used with LL_DMA_ReadReg and LL_DMAMUX_WriteReg functions. More...

Defines

#define | LL_DMAMUX_CCR_SOIE DMAMUX_CxCR_SOIE
#define | LL_DMAMUX_RGCR_RGOIE DMAMUX_RGxCR_OIE

Detailed Description

IT defines which can be used with LL_DMA_ReadReg and LL_DMAMUX_WriteReg functions.

Define Documentation

#define LL_DMAMUX_CCR_SOIE DMAMUX_CxCR_SOIE

Synchronization Event Overrun Interrupt

Definition at line 122 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_RGCR_RGOIE DMAMUX_RGxCR_OIE

Request Generation Trigger Event Overrun Interrupt

Definition at line 123 of file stm32wbxx_ll_dmamux.h.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Transfer request

Defines
Transfer request
DMAMUX Exported Constants

Defines

#define | LL_DMAMUX_REQ_MEM2MEM 0x00000000U
#define | LL_DMAMUX_REQ_GENERATOR0 0x00000001U
#define | LL_DMAMUX_REQ_GENERATOR1 0x00000002U
#define | LL_DMAMUX_REQ_GENERATOR2 0x00000003U
#define | LL_DMAMUX_REQ_GENERATOR3 0x00000004U
#define | LL_DMAMUX_REQ_ADC1 0x00000005U
#define | LL_DMAMUX_REQ_SPI1_RX 0x00000006U
#define | LL_DMAMUX_REQ_SPI1_TX 0x00000007U
#define | LL_DMAMUX_REQ_SPI2_RX 0x00000008U
#define | LL_DMAMUX_REQ_SPI2_TX 0x00000009U
#define | LL_DMAMUX_REQ_I2C1_RX 0x0000000AU
#define | LL_DMAMUX_REQ_I2C1_TX 0x0000000BU
#define | LL_DMAMUX_REQ_I2C3_RX 0x0000000CU
#define | LL_DMAMUX_REQ_I2C3_TX 0x0000000DU
#define | LL_DMAMUX_REQ_USART1_RX 0x0000000EU
#define | LL_DMAMUX_REQ_USART1_TX 0x0000000FU
#define | LL_DMAMUX_REQ_LPUART1_RX 0x00000010U
#define | LL_DMAMUX_REQ_LPUART1_TX 0x00000011U
#define | LL_DMAMUX_REQ_SAI1_A 0x00000012U
#define | LL_DMAMUX_REQ_SAI1_B 0x00000013U
#define | LL_DMAMUX_REQ_QUADSPI 0x00000014U
#define | LL_DMAMUX_REQ_TIM1_CH1 0x00000015U
#define | LL_DMAMUX_REQ_TIM1_CH2 0x00000016U
#define | LL_DMAMUX_REQ_TIM1_CH3 0x00000017U
#define | LL_DMAMUX_REQ_TIM1_CH4 0x00000018U
#define | LL_DMAMUX_REQ_TIM1_UP 0x00000019U
#define | LL_DMAMUX_REQ_TIM1_TRIG 0x0000001AU
#define | LL_DMAMUX_REQ_TIM1_COM 0x0000001BU
#define | LL_DMAMUX_REQ_TIM2_CH1 0x0000001CU
#define | LL_DMAMUX_REQ_TIM2_CH2 0x0000001DU
#define | LL_DMAMUX_REQ_TIM2_CH3 0x0000001EU
#define | LL_DMAMUX_REQ_TIM2_CH4 0x0000001FU
#define | LL_DMAMUX_REQ_TIM2_UP 0x00000020U
#define | LL_DMAMUX_REQ_TIM16_CH1 0x00000021U
#define | LL_DMAMUX_REQ_TIM16_UP 0x00000022U
#define | LL_DMAMUX_REQ_TIM17_CH1 0x00000023U
#define | LL_DMAMUX_REQ_TIM17_UP 0x00000024U
#define | LL_DMAMUX_REQ_AES1_IN 0x00000025U
#define | LL_DMAMUX_REQ_AES1_OUT 0x00000026U
#define | LL_DMAMUX_REQ_AES2_IN 0x00000027U
#define | LL_DMAMUX_REQ_AES2_OUT 0x00000028U

Define Documentation

#define LL_DMAMUX_REQ_ADC1 0x00000005U

DMAMUX ADC1 request

Definition at line 136 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_AES1_IN 0x00000025U

DMAMUX AES1_IN request

Definition at line 179 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_AES1_OUT 0x00000026U

DMAMUX AES1_OUT request

Definition at line 180 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_AES2_IN 0x00000027U

DMAMUX AES2_IN request

Definition at line 182 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_AES2_OUT 0x00000028U

DMAMUX AES2_OUT request

Definition at line 183 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GENERATOR0 0x00000001U

DMAMUX request generator 0

Definition at line 132 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GENERATOR1 0x00000002U

DMAMUX request generator 1

Definition at line 133 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GENERATOR2 0x00000003U

DMAMUX request generator 2

Definition at line 134 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GENERATOR3 0x00000004U

DMAMUX request generator 3

Definition at line 135 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_I2C1_RX 0x0000000AU

DMAMUX I2C1 RX request

Definition at line 143 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_I2C1_TX 0x0000000BU

DMAMUX I2C1 TX request

Definition at line 144 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_I2C3_RX 0x0000000CU

DMAMUX I2C3 RX request

Definition at line 146 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_I2C3_TX 0x0000000DU

DMAMUX I2C3 TX request

Definition at line 147 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_LPUART1_RX 0x00000010U

DMAMUX LPUART1 RX request

Definition at line 152 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_LPUART1_TX 0x00000011U

DMAMUX LPUART1 TX request

Definition at line 153 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_MEM2MEM 0x00000000U

memory to memory transfer

Definition at line 131 of file stm32wbxx_ll_dmamux.h.

Referenced by LL_DMA_DeInit(), and LL_DMA_StructInit().

#define LL_DMAMUX_REQ_QUADSPI 0x00000014U

DMAMUX QUADSPI request

Definition at line 160 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_SAI1_A 0x00000012U

DMAMUX SAI1 A request

Definition at line 156 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_SAI1_B 0x00000013U

DMAMUX SAI1 B request

Definition at line 157 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_SPI1_RX 0x00000006U

DMAMUX SPI1 RX request

Definition at line 137 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_SPI1_TX 0x00000007U

DMAMUX SPI1 TX request

Definition at line 138 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_SPI2_RX 0x00000008U

DMAMUX SPI2 RX request

Definition at line 140 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_SPI2_TX 0x00000009U

DMAMUX SPI2 TX request

Definition at line 141 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM16_CH1 0x00000021U

DMAMUX TIM16 CH1 request

Definition at line 174 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM16_UP 0x00000022U

DMAMUX TIM16 UP request

Definition at line 175 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM17_CH1 0x00000023U

DMAMUX TIM17 CH1 request

Definition at line 176 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM17_UP 0x00000024U

DMAMUX TIM17 UP request

Definition at line 177 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM1_CH1 0x00000015U

DMAMUX TIM1 CH1 request

Definition at line 162 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM1_CH2 0x00000016U

DMAMUX TIM1 CH2 request

Definition at line 163 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM1_CH3 0x00000017U

DMAMUX TIM1 CH3 request

Definition at line 164 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM1_CH4 0x00000018U

DMAMUX TIM1 CH4 request

Definition at line 165 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM1_COM 0x0000001BU

DMAMUX TIM1 COM request

Definition at line 168 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM1_TRIG 0x0000001AU

DMAMUX TIM1 TRIG request

Definition at line 167 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM1_UP 0x00000019U

DMAMUX TIM1 UP request

Definition at line 166 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM2_CH1 0x0000001CU

DMAMUX TIM2 CH1 request

Definition at line 169 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM2_CH2 0x0000001DU

DMAMUX TIM2 CH2 request

Definition at line 170 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM2_CH3 0x0000001EU

DMAMUX TIM2 CH3 request

Definition at line 171 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM2_CH4 0x0000001FU

DMAMUX TIM2 CH4 request

Definition at line 172 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_TIM2_UP 0x00000020U

DMAMUX TIM2 UP request

Definition at line 173 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_USART1_RX 0x0000000EU

DMAMUX USART1 RX request

Definition at line 149 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_USART1_TX 0x0000000FU

DMAMUX USART1 TX request

Definition at line 150 of file stm32wbxx_ll_dmamux.h.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DMAMUX Channel

Defines
DMAMUX Channel
DMAMUX Exported Constants

Defines

#define | LL_DMAMUX_CHANNEL_0 0x00000000U
#define | LL_DMAMUX_CHANNEL_1 0x00000001U
#define | LL_DMAMUX_CHANNEL_2 0x00000002U
#define | LL_DMAMUX_CHANNEL_3 0x00000003U
#define | LL_DMAMUX_CHANNEL_4 0x00000004U
#define | LL_DMAMUX_CHANNEL_5 0x00000005U
#define | LL_DMAMUX_CHANNEL_6 0x00000006U
#define | LL_DMAMUX_CHANNEL_7 0x00000007U
#define | LL_DMAMUX_CHANNEL_8 0x00000008U
#define | LL_DMAMUX_CHANNEL_9 0x00000009U
#define | LL_DMAMUX_CHANNEL_10 0x0000000AU
#define | LL_DMAMUX_CHANNEL_11 0x0000000BU
#define | LL_DMAMUX_CHANNEL_12 0x0000000CU
#define | LL_DMAMUX_CHANNEL_13 0x0000000DU

Define Documentation

#define LL_DMAMUX_CHANNEL_0 0x00000000U

DMAMUX Channel 0 connected to DMA1 Channel 1

Definition at line 191 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_1 0x00000001U

DMAMUX Channel 1 connected to DMA1 Channel 2

Definition at line 192 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_10 0x0000000AU

DMAMUX Channel 10 connected to DMA2 Channel 4

Definition at line 202 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_11 0x0000000BU

DMAMUX Channel 11 connected to DMA2 Channel 5

Definition at line 203 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_12 0x0000000CU

DMAMUX Channel 12 connected to DMA2 Channel 6

Definition at line 204 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_13 0x0000000DU

DMAMUX Channel 13 connected to DMA2 Channel 7

Definition at line 205 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_2 0x00000002U

DMAMUX Channel 2 connected to DMA1 Channel 3

Definition at line 193 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_3 0x00000003U

DMAMUX Channel 3 connected to DMA1 Channel 4

Definition at line 194 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_4 0x00000004U

DMAMUX Channel 4 connected to DMA1 Channel 5

Definition at line 195 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_5 0x00000005U

DMAMUX Channel 5 connected to DMA1 Channel 6

Definition at line 196 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_6 0x00000006U

DMAMUX Channel 6 connected to DMA1 Channel 7

Definition at line 197 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_7 0x00000007U

DMAMUX Channel 7 connected to DMA2 Channel 1

Definition at line 199 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_8 0x00000008U

DMAMUX Channel 8 connected to DMA2 Channel 2

Definition at line 200 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_CHANNEL_9 0x00000009U

DMAMUX Channel 9 connected to DMA2 Channel 3

Definition at line 201 of file stm32wbxx_ll_dmamux.h.

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STM32WB55xx HAL User Manual: Synchronization Signal Polarity

Defines
Synchronization Signal Polarity
DMAMUX Exported Constants

Defines

#define | LL_DMAMUX_SYNC_NO_EVENT 0x00000000U
#define | LL_DMAMUX_SYNC_POL_RISING DMAMUX_CxCR_SPOL_0
#define | LL_DMAMUX_SYNC_POL_FALLING DMAMUX_CxCR_SPOL_1
#define | LL_DMAMUX_SYNC_POL_RISING_FALLING (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1)

Define Documentation

#define LL_DMAMUX_SYNC_NO_EVENT 0x00000000U

All requests are blocked

Definition at line 214 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_POL_FALLING DMAMUX_CxCR_SPOL_1

Synchronization on event on falling edge

Definition at line 216 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_POL_RISING DMAMUX_CxCR_SPOL_0

Synchronization on event on rising edge

Definition at line 215 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_POL_RISING_FALLING (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1)

Synchronization on event on rising and falling edge

Definition at line 217 of file stm32wbxx_ll_dmamux.h.

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STM32WB55xx HAL User Manual: Synchronization Signal Event

Defines
Synchronization Signal Event
DMAMUX Exported Constants

Defines

#define | LL_DMAMUX_SYNC_EXTI_LINE0 0x00000000U
#define | LL_DMAMUX_SYNC_EXTI_LINE1 DMAMUX_CxCR_SYNC_ID_0
#define | LL_DMAMUX_SYNC_EXTI_LINE2 DMAMUX_CxCR_SYNC_ID_1
#define | LL_DMAMUX_SYNC_EXTI_LINE3 (DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_EXTI_LINE4 DMAMUX_CxCR_SYNC_ID_2
#define | LL_DMAMUX_SYNC_EXTI_LINE5 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_EXTI_LINE6 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1)
#define | LL_DMAMUX_SYNC_EXTI_LINE7 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_EXTI_LINE8 DMAMUX_CxCR_SYNC_ID_3
#define | LL_DMAMUX_SYNC_EXTI_LINE9 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_EXTI_LINE10 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1)
#define | LL_DMAMUX_SYNC_EXTI_LINE11 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_EXTI_LINE12 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2)
#define | LL_DMAMUX_SYNC_EXTI_LINE13 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_EXTI_LINE14 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1)
#define | LL_DMAMUX_SYNC_EXTI_LINE15 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_DMAMUX_CH0 DMAMUX_CxCR_SYNC_ID_4
#define | LL_DMAMUX_SYNC_DMAMUX_CH1 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_LPTIM1_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1)
#define | LL_DMAMUX_SYNC_LPTIM2_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)

Define Documentation

#define LL_DMAMUX_SYNC_DMAMUX_CH0 DMAMUX_CxCR_SYNC_ID_4

Synchronization signal from DMAMUX channel0 Event

Definition at line 241 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_DMAMUX_CH1 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_0)

Synchronization signal from DMAMUX channel1 Event

Definition at line 242 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE0 0x00000000U

Synchronization signal from EXTI Line0

Definition at line 225 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE1 DMAMUX_CxCR_SYNC_ID_0

Synchronization signal from EXTI Line1

Definition at line 226 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE10 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1)

Synchronization signal from EXTI Line10

Definition at line 235 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE11 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)

Synchronization signal from EXTI Line11

Definition at line 236 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE12 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2)

Synchronization signal from EXTI Line12

Definition at line 237 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE13 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0)

Synchronization signal from EXTI Line13

Definition at line 238 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE14 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1)

Synchronization signal from EXTI Line14

Definition at line 239 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE15 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)

Synchronization signal from EXTI Line15

Definition at line 240 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE2 DMAMUX_CxCR_SYNC_ID_1

Synchronization signal from EXTI Line2

Definition at line 227 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE3 (DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)

Synchronization signal from EXTI Line3

Definition at line 228 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE4 DMAMUX_CxCR_SYNC_ID_2

Synchronization signal from EXTI Line4

Definition at line 229 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE5 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0)

Synchronization signal from EXTI Line5

Definition at line 230 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE6 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1)

Synchronization signal from EXTI Line6

Definition at line 231 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE7 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)

Synchronization signal from EXTI Line7

Definition at line 232 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE8 DMAMUX_CxCR_SYNC_ID_3

Synchronization signal from EXTI Line8

Definition at line 233 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_EXTI_LINE9 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_0)

Synchronization signal from EXTI Line9

Definition at line 234 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_LPTIM1_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1)

Synchronization signal from LPTIM1 Ouput

Definition at line 243 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_SYNC_LPTIM2_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)

Synchronization signal from LPTIM2 Ouput

Definition at line 244 of file stm32wbxx_ll_dmamux.h.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Request Generator Channel

Defines
Request Generator Channel
DMAMUX Exported Constants

Defines

#define | LL_DMAMUX_REQ_GEN_0 0x00000000U
#define | LL_DMAMUX_REQ_GEN_1 0x00000001U
#define | LL_DMAMUX_REQ_GEN_2 0x00000002U
#define | LL_DMAMUX_REQ_GEN_3 0x00000003U

Define Documentation

#define LL_DMAMUX_REQ_GEN_0 0x00000000U

Definition at line 252 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_1 0x00000001U

Definition at line 253 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_2 0x00000002U

Definition at line 254 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_3 0x00000003U

Definition at line 255 of file stm32wbxx_ll_dmamux.h.

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STM32WB55xx HAL User Manual: External Request Signal Generation Polarity

Defines
External Request Signal Generation Polarity
DMAMUX Exported Constants

Defines

#define | LL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U
#define | LL_DMAMUX_REQ_GEN_POL_RISING DMAMUX_RGxCR_GPOL_0
#define | LL_DMAMUX_REQ_GEN_POL_FALLING DMAMUX_RGxCR_GPOL_1
#define | LL_DMAMUX_REQ_GEN_POL_RISING_FALLING (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1)

Define Documentation

#define LL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U

No external DMA request generation

Definition at line 263 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_POL_FALLING DMAMUX_RGxCR_GPOL_1

External DMA request generation on event on falling edge

Definition at line 265 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_POL_RISING DMAMUX_RGxCR_GPOL_0

External DMA request generation on event on rising edge

Definition at line 264 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1)

External DMA request generation on rising and falling edge

Definition at line 266 of file stm32wbxx_ll_dmamux.h.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: External Request Signal Generation

Defines
External Request Signal Generation
DMAMUX Exported Constants

Defines

#define | LL_DMAMUX_REQ_GEN_EXTI_LINE0 0x00000000U
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE1 DMAMUX_RGxCR_SIG_ID_0
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE2 DMAMUX_RGxCR_SIG_ID_1
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE3 (DMAMUX_RGxCR_SIG_ID_1 |DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE4 DMAMUX_RGxCR_SIG_ID_2
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE5 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE6 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE7 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE8 DMAMUX_RGxCR_SIG_ID_3
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE9 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE10 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE11 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE12 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE13 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE14 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE15 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_DMAMUX_CH0 DMAMUX_RGxCR_SIG_ID_4
#define | LL_DMAMUX_REQ_GEN_DMAMUX_CH1 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_LPTIM1_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1)
#define | LL_DMAMUX_REQ_GEN_LPTIM2_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)

Define Documentation

#define LL_DMAMUX_REQ_GEN_DMAMUX_CH0 DMAMUX_RGxCR_SIG_ID_4

Request signal generation from DMAMUX channel0 Event

Definition at line 290 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_DMAMUX_CH1 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_0)

Request signal generation from DMAMUX channel1 Event

Definition at line 291 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE0 0x00000000U

Request signal generation from EXTI Line0

Definition at line 274 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE1 DMAMUX_RGxCR_SIG_ID_0

Request signal generation from EXTI Line1

Definition at line 275 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE10 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1)

Request signal generation from EXTI Line10

Definition at line 284 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE11 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)

Request signal generation from EXTI Line11

Definition at line 285 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE12 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2)

Request signal generation from EXTI Line12

Definition at line 286 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE13 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0)

Request signal generation from EXTI Line13

Definition at line 287 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE14 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1)

Request signal generation from EXTI Line14

Definition at line 288 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE15 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)

Request signal generation from EXTI Line15

Definition at line 289 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE2 DMAMUX_RGxCR_SIG_ID_1

Request signal generation from EXTI Line2

Definition at line 276 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE3 (DMAMUX_RGxCR_SIG_ID_1 |DMAMUX_RGxCR_SIG_ID_0)

Request signal generation from EXTI Line3

Definition at line 277 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE4 DMAMUX_RGxCR_SIG_ID_2

Request signal generation from EXTI Line4

Definition at line 278 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE5 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0)

Request signal generation from EXTI Line5

Definition at line 279 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE6 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1)

Request signal generation from EXTI Line6

Definition at line 280 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE7 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)

Request signal generation from EXTI Line7

Definition at line 281 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE8 DMAMUX_RGxCR_SIG_ID_3

Request signal generation from EXTI Line8

Definition at line 282 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_EXTI_LINE9 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_0)

Request signal generation from EXTI Line9

Definition at line 283 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_LPTIM1_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1)

Request signal generation from LPTIM1 Ouput

Definition at line 292 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_REQ_GEN_LPTIM2_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)

Request signal generation from LPTIM2 Ouput

Definition at line 293 of file stm32wbxx_ll_dmamux.h.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Common Write and read registers macros

Defines
Common Write and read registers macros
DMAMUX Exported Macros

Defines

#define | LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in DMAMUX register.
#define | LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in DMAMUX register.

Define Documentation

#define LL_DMAMUX_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in DMAMUX register.

Parameters:
__INSTANCE__ | DMAMUX Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 325 of file stm32wbxx_ll_dmamux.h.

#define LL_DMAMUX_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in DMAMUX register.

Parameters:
__INSTANCE__ | DMAMUX Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 317 of file stm32wbxx_ll_dmamux.h.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Configuration

Functions
Configuration
DMAMUX Exported Functions

Functions

__STATIC_INLINE void | LL_DMAMUX_SetRequestID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request)
Set DMAMUX request ID for DMAMUX Channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetRequestID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Get DMAMUX request ID for DMAMUX Channel x.
__STATIC_INLINE void | LL_DMAMUX_SetSyncRequestNb (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb)
Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetSyncRequestNb (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
__STATIC_INLINE void | LL_DMAMUX_SetSyncPolarity (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity)
Set the polarity of the signal on which the DMA request is synchronized.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetSyncPolarity (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Get the polarity of the signal on which the DMA request is synchronized.
__STATIC_INLINE void | LL_DMAMUX_EnableEventGeneration (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Enable the Event Generation on DMAMUX channel x.
__STATIC_INLINE void | LL_DMAMUX_DisableEventGeneration (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Disable the Event Generation on DMAMUX channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledEventGeneration (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Check if the Event Generation on DMAMUX channel x is enabled or disabled.
__STATIC_INLINE void | LL_DMAMUX_EnableSync (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Enable the synchronization mode.
__STATIC_INLINE void | LL_DMAMUX_DisableSync (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Disable the synchronization mode.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledSync (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Check if the synchronization mode is enabled or disabled.
__STATIC_INLINE void | LL_DMAMUX_SetSyncID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID)
Set DMAMUX synchronization ID on DMAMUX Channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetSyncID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Get DMAMUX synchronization ID on DMAMUX Channel x.
__STATIC_INLINE void | LL_DMAMUX_EnableRequestGen (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Enable the Request Generator.
__STATIC_INLINE void | LL_DMAMUX_DisableRequestGen (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Disable the Request Generator.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledRequestGen (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Check if the Request Generator is enabled or disabled.
__STATIC_INLINE void | LL_DMAMUX_SetRequestGenPolarity (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity)
Set the polarity of the signal on which the DMA request is generated.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetRequestGenPolarity (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Get the polarity of the signal on which the DMA request is generated.
__STATIC_INLINE void | LL_DMAMUX_SetGenRequestNb (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb)
Set the number of DMA request that will be autorized after a generation event.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetGenRequestNb (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Get the number of DMA request that will be autorized after a generation event.
__STATIC_INLINE void | LL_DMAMUX_SetRequestSignalID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID)
Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetRequestSignalID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Get DMAMUX external Request Signal ID set on DMAMUX Channel x.

Function Documentation

__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Disable the Event Generation on DMAMUX channel x.

Reference Manual to LL API cross reference:
CxCR EGE LL_DMAMUX_DisableEventGeneration
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6 #if defined(DMA2)
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13 #endif
Return values:
None

Definition at line 661 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_DisableRequestGen | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel
 | ) |  |

Disable the Request Generator.

Reference Manual to LL API cross reference:
RGxCR GE LL_DMAMUX_DisableRequestGen
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
Return values:
None

Definition at line 910 of file stm32wbxx_ll_dmamux.h.

References DMAMUX_RGCR_SIZE.

__STATIC_INLINE void LL_DMAMUX_DisableSync | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Disable the synchronization mode.

Reference Manual to LL API cross reference:
CxCR SE LL_DMAMUX_DisableSync
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6 #if defined(DMA2)
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13 #endif
Return values:
None

Definition at line 748 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Enable the Event Generation on DMAMUX channel x.

Reference Manual to LL API cross reference:
CxCR EGE LL_DMAMUX_EnableEventGeneration
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6 #if defined(DMA2)
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13 #endif
Return values:
None

Definition at line 632 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_EnableRequestGen | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel
 | ) |  |

Enable the Request Generator.

Reference Manual to LL API cross reference:
RGxCR GE LL_DMAMUX_EnableRequestGen
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
Return values:
None

Definition at line 893 of file stm32wbxx_ll_dmamux.h.

References DMAMUX_RGCR_SIZE.

__STATIC_INLINE void LL_DMAMUX_EnableSync | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Enable the synchronization mode.

Reference Manual to LL API cross reference:
CxCR SE LL_DMAMUX_EnableSync
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6 #if defined(DMA2)
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13 #endif
Return values:
None

Definition at line 719 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel
 | ) |  |

Get the number of DMA request that will be autorized after a generation event.

Reference Manual to LL API cross reference:
RGxCR GNBREQ LL_DMAMUX_GetGenRequestNb
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
Return values:
Between Min_Data = 1 and Max_Data = 32

Definition at line 1006 of file stm32wbxx_ll_dmamux.h.

References DMAMUX_RGCR_SIZE.

__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel
 | ) |  |

Get the polarity of the signal on which the DMA request is generated.

Reference Manual to LL API cross reference:
RGxCR GPOL LL_DMAMUX_GetRequestGenPolarity
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
Return values:
Returned value can be one of the following values:
  • LL_DMAMUX_REQ_GEN_NO_EVENT
  • LL_DMAMUX_REQ_GEN_POL_RISING
  • LL_DMAMUX_REQ_GEN_POL_FALLING
  • LL_DMAMUX_REQ_GEN_POL_RISING_FALLING

Definition at line 970 of file stm32wbxx_ll_dmamux.h.

References DMAMUX_RGCR_SIZE.

__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Get DMAMUX request ID for DMAMUX Channel x.

Note:
DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. #if defined(DMA2) DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. #endif
Reference Manual to LL API cross reference:
CxCR DMAREQ_ID LL_DMAMUX_GetRequestID
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13
Return values:
Returned value can be one of the following values:
  • LL_DMAMUX_REQ_MEM2MEM
  • LL_DMAMUX_REQ_GENERATOR0
  • LL_DMAMUX_REQ_GENERATOR1
  • LL_DMAMUX_REQ_GENERATOR2
  • LL_DMAMUX_REQ_GENERATOR3
  • LL_DMAMUX_REQ_ADC1
  • LL_DMAMUX_REQ_SPI1_RX
  • LL_DMAMUX_REQ_SPI1_TX
  • LL_DMAMUX_REQ_SPI2_RX
  • LL_DMAMUX_REQ_SPI2_TX
  • LL_DMAMUX_REQ_I2C1_RX
  • LL_DMAMUX_REQ_I2C1_TX
  • LL_DMAMUX_REQ_I2C3_RX
  • LL_DMAMUX_REQ_I2C3_TX
  • LL_DMAMUX_REQ_USART1_RX
  • LL_DMAMUX_REQ_USART1_TX
  • LL_DMAMUX_REQ_LPUART1_RX
  • LL_DMAMUX_REQ_LPUART1_TX
  • LL_DMAMUX_REQ_SAI1_A
  • LL_DMAMUX_REQ_SAI1_B
  • LL_DMAMUX_REQ_QUADSPI
  • LL_DMAMUX_REQ_TIM1_CH1
  • LL_DMAMUX_REQ_TIM1_CH2
  • LL_DMAMUX_REQ_TIM1_CH3
  • LL_DMAMUX_REQ_TIM1_CH4
  • LL_DMAMUX_REQ_TIM1_UP
  • LL_DMAMUX_REQ_TIM1_TRIG
  • LL_DMAMUX_REQ_TIM1_COM
  • LL_DMAMUX_REQ_TIM2_CH1
  • LL_DMAMUX_REQ_TIM2_CH2
  • LL_DMAMUX_REQ_TIM2_CH3
  • LL_DMAMUX_REQ_TIM2_CH4
  • LL_DMAMUX_REQ_TIM2_UP
  • LL_DMAMUX_REQ_TIM16_CH1
  • LL_DMAMUX_REQ_TIM16_UP
  • LL_DMAMUX_REQ_TIM17_CH1
  • LL_DMAMUX_REQ_TIM17_UP
  • LL_DMAMUX_REQ_AES1_IN
  • LL_DMAMUX_REQ_AES1_OUT
  • LL_DMAMUX_REQ_AES2_IN
  • LL_DMAMUX_REQ_AES2_OUT

Definition at line 483 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel
 | ) |  |

Get DMAMUX external Request Signal ID set on DMAMUX Channel x.

Reference Manual to LL API cross reference:
RGxCR SIG_ID LL_DMAMUX_GetRequestSignalID
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
Return values:
Returned value can be one of the following values:
  • LL_DMAMUX_REQ_GEN_EXTI_LINE0
  • LL_DMAMUX_REQ_GEN_EXTI_LINE1
  • LL_DMAMUX_REQ_GEN_EXTI_LINE2
  • LL_DMAMUX_REQ_GEN_EXTI_LINE3
  • LL_DMAMUX_REQ_GEN_EXTI_LINE4
  • LL_DMAMUX_REQ_GEN_EXTI_LINE5
  • LL_DMAMUX_REQ_GEN_EXTI_LINE6
  • LL_DMAMUX_REQ_GEN_EXTI_LINE7
  • LL_DMAMUX_REQ_GEN_EXTI_LINE8
  • LL_DMAMUX_REQ_GEN_EXTI_LINE9
  • LL_DMAMUX_REQ_GEN_EXTI_LINE10
  • LL_DMAMUX_REQ_GEN_EXTI_LINE11
  • LL_DMAMUX_REQ_GEN_EXTI_LINE12
  • LL_DMAMUX_REQ_GEN_EXTI_LINE13
  • LL_DMAMUX_REQ_GEN_EXTI_LINE14
  • LL_DMAMUX_REQ_GEN_EXTI_LINE15
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH0
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH1
  • LL_DMAMUX_REQ_GEN_LPTIM1_OUT
  • LL_DMAMUX_REQ_GEN_LPTIM2_OUT

Definition at line 1081 of file stm32wbxx_ll_dmamux.h.

References DMAMUX_RGCR_SIZE.

__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Get DMAMUX synchronization ID on DMAMUX Channel x.

Reference Manual to LL API cross reference:
CxCR SYNC_ID LL_DMAMUX_GetSyncID
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6 #if defined(DMA2)
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13 #endif
Return values:
Returned value can be one of the following values:
  • LL_DMAMUX_SYNC_EXTI_LINE0
  • LL_DMAMUX_SYNC_EXTI_LINE1
  • LL_DMAMUX_SYNC_EXTI_LINE2
  • LL_DMAMUX_SYNC_EXTI_LINE3
  • LL_DMAMUX_SYNC_EXTI_LINE4
  • LL_DMAMUX_SYNC_EXTI_LINE5
  • LL_DMAMUX_SYNC_EXTI_LINE6
  • LL_DMAMUX_SYNC_EXTI_LINE7
  • LL_DMAMUX_SYNC_EXTI_LINE8
  • LL_DMAMUX_SYNC_EXTI_LINE9
  • LL_DMAMUX_SYNC_EXTI_LINE10
  • LL_DMAMUX_SYNC_EXTI_LINE11
  • LL_DMAMUX_SYNC_EXTI_LINE12
  • LL_DMAMUX_SYNC_EXTI_LINE13
  • LL_DMAMUX_SYNC_EXTI_LINE14
  • LL_DMAMUX_SYNC_EXTI_LINE15
  • LL_DMAMUX_SYNC_DMAMUX_CH0
  • LL_DMAMUX_SYNC_DMAMUX_CH1
  • LL_DMAMUX_SYNC_LPTIM1_OUT
  • LL_DMAMUX_SYNC_LPTIM2_OUT

Definition at line 876 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Get the polarity of the signal on which the DMA request is synchronized.

Reference Manual to LL API cross reference:
CxCR SPOL LL_DMAMUX_GetSyncPolarity
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6 #if defined(DMA2)
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13 #endif
Return values:
Returned value can be one of the following values:
  • LL_DMAMUX_SYNC_NO_EVENT
  • LL_DMAMUX_SYNC_POL_RISING
  • LL_DMAMUX_SYNC_POL_FALLING
  • LL_DMAMUX_SYNC_POL_RISING_FALLING

Definition at line 603 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.

Reference Manual to LL API cross reference:
CxCR NBREQ LL_DMAMUX_GetSyncRequestNb
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13
Return values:
Between Min_Data = 1 and Max_Data = 32

Definition at line 538 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Check if the Event Generation on DMAMUX channel x is enabled or disabled.

Reference Manual to LL API cross reference:
CxCR EGE LL_DMAMUX_IsEnabledEventGeneration
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6 #if defined(DMA2)
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13 #endif
Return values:
State of bit (1 or 0).

Definition at line 690 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel
 | ) |  |

Check if the Request Generator is enabled or disabled.

Reference Manual to LL API cross reference:
RGxCR GE LL_DMAMUX_IsEnabledRequestGen
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
Return values:
State of bit (1 or 0).

Definition at line 927 of file stm32wbxx_ll_dmamux.h.

References DMAMUX_RGCR_SIZE.

__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Check if the synchronization mode is enabled or disabled.

Reference Manual to LL API cross reference:
CxCR SE LL_DMAMUX_IsEnabledSync
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6 #if defined(DMA2)
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13 #endif
Return values:
State of bit (1 or 0).

Definition at line 777 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel,
 |  | uint32_t | RequestNb
 | ) |  |

Set the number of DMA request that will be autorized after a generation event.

Note:
This field can only be written when Generator is disabled.
Reference Manual to LL API cross reference:
RGxCR GNBREQ LL_DMAMUX_SetGenRequestNb
Parameters:
DMAMUXx | DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
RequestNb | This parameter must be a value between Min_Data = 1 and Max_Data = 32.
Return values:
None

Definition at line 989 of file stm32wbxx_ll_dmamux.h.

References DMAMUX_RGCR_SIZE.

__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel,
 |  | uint32_t | Polarity
 | ) |  |

Set the polarity of the signal on which the DMA request is generated.

Reference Manual to LL API cross reference:
RGxCR GPOL LL_DMAMUX_SetRequestGenPolarity
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
Polarity This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_NO_EVENT
  • LL_DMAMUX_REQ_GEN_POL_RISING
  • LL_DMAMUX_REQ_GEN_POL_FALLING
  • LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
Return values:
None

Definition at line 949 of file stm32wbxx_ll_dmamux.h.

References DMAMUX_RGCR_SIZE.

__STATIC_INLINE void LL_DMAMUX_SetRequestID | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel,
 |  | uint32_t | Request
 | ) |  |

Set DMAMUX request ID for DMAMUX Channel x.

Note:
DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. #if defined(DMA2) DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. #endif
Reference Manual to LL API cross reference:
CxCR DMAREQ_ID LL_DMAMUX_SetRequestID
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6 #if defined(DMA2)
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13 #endif
Request This parameter can be one of the following values:
  • LL_DMAMUX_REQ_MEM2MEM
  • LL_DMAMUX_REQ_GENERATOR0
  • LL_DMAMUX_REQ_GENERATOR1
  • LL_DMAMUX_REQ_GENERATOR2
  • LL_DMAMUX_REQ_GENERATOR3
  • LL_DMAMUX_REQ_ADC1
  • LL_DMAMUX_REQ_SPI1_RX
  • LL_DMAMUX_REQ_SPI1_TX
  • LL_DMAMUX_REQ_SPI2_RX
  • LL_DMAMUX_REQ_SPI2_TX
  • LL_DMAMUX_REQ_I2C1_RX
  • LL_DMAMUX_REQ_I2C1_TX
  • LL_DMAMUX_REQ_I2C3_RX
  • LL_DMAMUX_REQ_I2C3_TX
  • LL_DMAMUX_REQ_USART1_RX
  • LL_DMAMUX_REQ_USART1_TX
  • LL_DMAMUX_REQ_LPUART1_RX
  • LL_DMAMUX_REQ_LPUART1_TX
  • LL_DMAMUX_REQ_SAI1_A
  • LL_DMAMUX_REQ_SAI1_B
  • LL_DMAMUX_REQ_QUADSPI
  • LL_DMAMUX_REQ_TIM1_CH1
  • LL_DMAMUX_REQ_TIM1_CH2
  • LL_DMAMUX_REQ_TIM1_CH3
  • LL_DMAMUX_REQ_TIM1_CH4
  • LL_DMAMUX_REQ_TIM1_UP
  • LL_DMAMUX_REQ_TIM1_TRIG
  • LL_DMAMUX_REQ_TIM1_COM
  • LL_DMAMUX_REQ_TIM2_CH1
  • LL_DMAMUX_REQ_TIM2_CH2
  • LL_DMAMUX_REQ_TIM2_CH3
  • LL_DMAMUX_REQ_TIM2_CH4
  • LL_DMAMUX_REQ_TIM2_UP
  • LL_DMAMUX_REQ_TIM16_CH1
  • LL_DMAMUX_REQ_TIM16_UP
  • LL_DMAMUX_REQ_TIM17_CH1
  • LL_DMAMUX_REQ_TIM17_UP
  • LL_DMAMUX_REQ_AES1_IN
  • LL_DMAMUX_REQ_AES1_OUT
  • LL_DMAMUX_REQ_AES2_IN
  • LL_DMAMUX_REQ_AES2_OUT
Return values:
None

Definition at line 411 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel,
 |  | uint32_t | RequestSignalID
 | ) |  |

Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x.

Reference Manual to LL API cross reference:
RGxCR SIG_ID LL_DMAMUX_SetRequestSignalID
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
RequestSignalID This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_EXTI_LINE0
  • LL_DMAMUX_REQ_GEN_EXTI_LINE1
  • LL_DMAMUX_REQ_GEN_EXTI_LINE2
  • LL_DMAMUX_REQ_GEN_EXTI_LINE3
  • LL_DMAMUX_REQ_GEN_EXTI_LINE4
  • LL_DMAMUX_REQ_GEN_EXTI_LINE5
  • LL_DMAMUX_REQ_GEN_EXTI_LINE6
  • LL_DMAMUX_REQ_GEN_EXTI_LINE7
  • LL_DMAMUX_REQ_GEN_EXTI_LINE8
  • LL_DMAMUX_REQ_GEN_EXTI_LINE9
  • LL_DMAMUX_REQ_GEN_EXTI_LINE10
  • LL_DMAMUX_REQ_GEN_EXTI_LINE11
  • LL_DMAMUX_REQ_GEN_EXTI_LINE12
  • LL_DMAMUX_REQ_GEN_EXTI_LINE13
  • LL_DMAMUX_REQ_GEN_EXTI_LINE14
  • LL_DMAMUX_REQ_GEN_EXTI_LINE15
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH0
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH1
  • LL_DMAMUX_REQ_GEN_LPTIM1_OUT
  • LL_DMAMUX_REQ_GEN_LPTIM2_OUT
Return values:
None

Definition at line 1044 of file stm32wbxx_ll_dmamux.h.

References DMAMUX_RGCR_SIZE.

__STATIC_INLINE void LL_DMAMUX_SetSyncID | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel,
 |  | uint32_t | SyncID
 | ) |  |

Set DMAMUX synchronization ID on DMAMUX Channel x.

Reference Manual to LL API cross reference:
CxCR SYNC_ID LL_DMAMUX_SetSyncID
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6 #if defined(DMA2)
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13 #endif
SyncID This parameter can be one of the following values:
  • LL_DMAMUX_SYNC_EXTI_LINE0
  • LL_DMAMUX_SYNC_EXTI_LINE1
  • LL_DMAMUX_SYNC_EXTI_LINE2
  • LL_DMAMUX_SYNC_EXTI_LINE3
  • LL_DMAMUX_SYNC_EXTI_LINE4
  • LL_DMAMUX_SYNC_EXTI_LINE5
  • LL_DMAMUX_SYNC_EXTI_LINE6
  • LL_DMAMUX_SYNC_EXTI_LINE7
  • LL_DMAMUX_SYNC_EXTI_LINE8
  • LL_DMAMUX_SYNC_EXTI_LINE9
  • LL_DMAMUX_SYNC_EXTI_LINE10
  • LL_DMAMUX_SYNC_EXTI_LINE11
  • LL_DMAMUX_SYNC_EXTI_LINE12
  • LL_DMAMUX_SYNC_EXTI_LINE13
  • LL_DMAMUX_SYNC_EXTI_LINE14
  • LL_DMAMUX_SYNC_EXTI_LINE15
  • LL_DMAMUX_SYNC_DMAMUX_CH0
  • LL_DMAMUX_SYNC_DMAMUX_CH1
  • LL_DMAMUX_SYNC_LPTIM1_OUT
  • LL_DMAMUX_SYNC_LPTIM2_OUT
Return values:
None

Definition at line 827 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel,
 |  | uint32_t | Polarity
 | ) |  |

Set the polarity of the signal on which the DMA request is synchronized.

Reference Manual to LL API cross reference:
CxCR SPOL LL_DMAMUX_SetSyncPolarity
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13
Polarity This parameter can be one of the following values:
  • LL_DMAMUX_SYNC_NO_EVENT
  • LL_DMAMUX_SYNC_POL_RISING
  • LL_DMAMUX_SYNC_POL_FALLING
  • LL_DMAMUX_SYNC_POL_RISING_FALLING
Return values:
None

Definition at line 570 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel,
 |  | uint32_t | RequestNb
 | ) |  |

Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.

Reference Manual to LL API cross reference:
CxCR NBREQ LL_DMAMUX_SetSyncRequestNb
Parameters:
DMAMUXx | DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13
RequestNb | This parameter must be a value between Min_Data = 1 and Max_Data = 32.
Return values:
None

Definition at line 511 of file stm32wbxx_ll_dmamux.h.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FLAG_Management

Functions
FLAG_Management
DMAMUX Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO0 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 0.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO1 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 1.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO2 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 2.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO3 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 3.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO4 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 4.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO5 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 5.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO6 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 6.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO7 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 7.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO8 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 8.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO9 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 9.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO10 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 10.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO11 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 11.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO12 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 12.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO13 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 13.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO0 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 0 Trigger Event Overrun Flag.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO1 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 1 Trigger Event Overrun Flag.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO2 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 2 Trigger Event Overrun Flag.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO3 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 3 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO0 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 0.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO1 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 1.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO2 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 2.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO3 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 3.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO4 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 4.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO5 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 5.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO6 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 6.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO7 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 7.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO8 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 8.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO9 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 9.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO10 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 10.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO11 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 11.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO12 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 12.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO13 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 13.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO0 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 0 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO1 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 1 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO2 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 2 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO3 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 3 Trigger Event Overrun Flag.

Function Documentation

__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Request Generator 0 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGCFR COF0 LL_DMAMUX_ClearFlag_RGO0
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1485 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Request Generator 1 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGCFR COF1 LL_DMAMUX_ClearFlag_RGO1
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1497 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Request Generator 2 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGCFR COF2 LL_DMAMUX_ClearFlag_RGO2
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1509 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Request Generator 3 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGCFR COF3 LL_DMAMUX_ClearFlag_RGO3
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1521 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 0.

Reference Manual to LL API cross reference:
CFR CSOF0 LL_DMAMUX_ClearFlag_SO0
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1317 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 1.

Reference Manual to LL API cross reference:
CFR CSOF1 LL_DMAMUX_ClearFlag_SO1
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1329 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 10.

Reference Manual to LL API cross reference:
CFR CSOF10 LL_DMAMUX_ClearFlag_SO10
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1437 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 11.

Reference Manual to LL API cross reference:
CFR CSOF11 LL_DMAMUX_ClearFlag_SO11
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1449 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 12.

Reference Manual to LL API cross reference:
CFR CSOF12 LL_DMAMUX_ClearFlag_SO12
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1461 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 13.

Reference Manual to LL API cross reference:
CFR CSOF13 LL_DMAMUX_ClearFlag_SO13
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1473 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 2.

Reference Manual to LL API cross reference:
CFR CSOF2 LL_DMAMUX_ClearFlag_SO2
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1341 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 3.

Reference Manual to LL API cross reference:
CFR CSOF3 LL_DMAMUX_ClearFlag_SO3
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1353 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 4.

Reference Manual to LL API cross reference:
CFR CSOF4 LL_DMAMUX_ClearFlag_SO4
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1365 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 5.

Reference Manual to LL API cross reference:
CFR CSOF5 LL_DMAMUX_ClearFlag_SO5
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1377 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 6.

Reference Manual to LL API cross reference:
CFR CSOF6 LL_DMAMUX_ClearFlag_SO6
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1389 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 7.

Reference Manual to LL API cross reference:
CFR CSOF7 LL_DMAMUX_ClearFlag_SO7
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1401 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 8.

Reference Manual to LL API cross reference:
CFR CSOF8 LL_DMAMUX_ClearFlag_SO8
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1413 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Clear Synchronization Event Overrun Flag Channel 9.

Reference Manual to LL API cross reference:
CFR CSOF9 LL_DMAMUX_ClearFlag_SO9
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
None

Definition at line 1425 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Request Generator 0 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGSR OF0 LL_DMAMUX_IsActiveFlag_RGO0
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1269 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Request Generator 1 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGSR OF1 LL_DMAMUX_IsActiveFlag_RGO1
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1281 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Request Generator 2 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGSR OF2 LL_DMAMUX_IsActiveFlag_RGO2
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1293 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Request Generator 3 Trigger Event Overrun Flag.

Reference Manual to LL API cross reference:
RGSR OF3 LL_DMAMUX_IsActiveFlag_RGO3
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1305 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 0.

Reference Manual to LL API cross reference:
CSR SOF0 LL_DMAMUX_IsActiveFlag_SO0
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1101 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 1.

Reference Manual to LL API cross reference:
CSR SOF1 LL_DMAMUX_IsActiveFlag_SO1
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1113 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 10.

Reference Manual to LL API cross reference:
CSR SOF10 LL_DMAMUX_IsActiveFlag_SO10
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1221 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 11.

Reference Manual to LL API cross reference:
CSR SOF11 LL_DMAMUX_IsActiveFlag_SO11
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1233 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 12.

Reference Manual to LL API cross reference:
CSR SOF12 LL_DMAMUX_IsActiveFlag_SO12
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1245 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 13.

Reference Manual to LL API cross reference:
CSR SOF13 LL_DMAMUX_IsActiveFlag_SO13
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1257 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 2.

Reference Manual to LL API cross reference:
CSR SOF2 LL_DMAMUX_IsActiveFlag_SO2
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1125 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 3.

Reference Manual to LL API cross reference:
CSR SOF3 LL_DMAMUX_IsActiveFlag_SO3
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1137 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 4.

Reference Manual to LL API cross reference:
CSR SOF4 LL_DMAMUX_IsActiveFlag_SO4
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1149 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 5.

Reference Manual to LL API cross reference:
CSR SOF5 LL_DMAMUX_IsActiveFlag_SO5
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1161 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 6.

Reference Manual to LL API cross reference:
CSR SOF6 LL_DMAMUX_IsActiveFlag_SO6
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1173 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 7.

Reference Manual to LL API cross reference:
CSR SOF7 LL_DMAMUX_IsActiveFlag_SO7
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1185 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 8.

Reference Manual to LL API cross reference:
CSR SOF8 LL_DMAMUX_IsActiveFlag_SO8
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1197 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9 ( DMAMUX_Channel_TypeDef * DMAMUXx )

Get Synchronization Event Overrun Flag Channel 9.

Reference Manual to LL API cross reference:
CSR SOF9 LL_DMAMUX_IsActiveFlag_SO9
Parameters:
DMAMUXx DMAMUXx DMAMUXx Instance
Return values:
State of bit (1 or 0).

Definition at line 1209 of file stm32wbxx_ll_dmamux.h.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IT_Management

Functions
IT_Management
DMAMUX Exported Functions

Functions

__STATIC_INLINE void | LL_DMAMUX_EnableIT_SO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
__STATIC_INLINE void | LL_DMAMUX_DisableIT_SO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledIT_SO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
__STATIC_INLINE void | LL_DMAMUX_EnableIT_RGO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
__STATIC_INLINE void | LL_DMAMUX_DisableIT_RGO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledIT_RGO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.

Function Documentation

__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel
 | ) |  |

Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.

Reference Manual to LL API cross reference:
RGxCR OIE LL_DMAMUX_DisableIT_RGO
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
Return values:
None

Definition at line 1650 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_DisableIT_SO | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x.

Reference Manual to LL API cross reference:
CxCR SOIE LL_DMAMUX_DisableIT_SO
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6 #if defined(DMA2)
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13 #endif
Return values:
None

Definition at line 1587 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel
 | ) |  |

Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.

Reference Manual to LL API cross reference:
RGxCR OIE LL_DMAMUX_EnableIT_RGO
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
Return values:
None

Definition at line 1633 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE void LL_DMAMUX_EnableIT_SO | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x.

Reference Manual to LL API cross reference:
CxCR SOIE LL_DMAMUX_EnableIT_SO
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6 #if defined(DMA2)
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13 #endif
Return values:
None

Definition at line 1558 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | RequestGenChannel
 | ) |  |

Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.

Reference Manual to LL API cross reference:
RGxCR OIE LL_DMAMUX_IsEnabledIT_RGO
Parameters:
DMAMUXx DMAMUXx Instance
RequestGenChannel This parameter can be one of the following values:
  • LL_DMAMUX_REQ_GEN_0
  • LL_DMAMUX_REQ_GEN_1
  • LL_DMAMUX_REQ_GEN_2
  • LL_DMAMUX_REQ_GEN_3
Return values:
State of bit (1 or 0).

Definition at line 1667 of file stm32wbxx_ll_dmamux.h.

__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO | ( | DMAMUX_Channel_TypeDef * | DMAMUXx,
 |  | uint32_t | Channel
 | ) |  |

Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.

Reference Manual to LL API cross reference:
CxCR SOIE LL_DMAMUX_IsEnabledIT_SO
Parameters:
DMAMUXx DMAMUXx Instance
Channel This parameter can be one of the following values:
  • LL_DMAMUX_CHANNEL_0
  • LL_DMAMUX_CHANNEL_1
  • LL_DMAMUX_CHANNEL_2
  • LL_DMAMUX_CHANNEL_3
  • LL_DMAMUX_CHANNEL_4
  • LL_DMAMUX_CHANNEL_5
  • LL_DMAMUX_CHANNEL_6 #if defined(DMA2)
  • LL_DMAMUX_CHANNEL_7
  • LL_DMAMUX_CHANNEL_8
  • LL_DMAMUX_CHANNEL_9
  • LL_DMAMUX_CHANNEL_10
  • LL_DMAMUX_CHANNEL_11
  • LL_DMAMUX_CHANNEL_12
  • LL_DMAMUX_CHANNEL_13 #endif
Return values:
State of bit (1 or 0).

Definition at line 1616 of file stm32wbxx_ll_dmamux.h.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: EXTI

Modules
EXTI
STM32WBxx_LL_Driver

Modules

EXTI Private Macros
EXTI Exported Init structure
EXTI Exported Constants
EXTI Exported Macros
EXTI Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for EXTI registers.

Register | Bit | Function
C2EMR1 | EMx | LL_C2_EXTI_DisableEvent_0_31
 |  | LL_C2_EXTI_EnableEvent_0_31
 |  | LL_C2_EXTI_IsEnabledEvent_0_31
C2EMR2 | EMx | LL_C2_EXTI_DisableEvent_32_63
 |  | LL_C2_EXTI_EnableEvent_32_63
C2IMR1 | IMx | LL_C2_EXTI_DisableIT_0_31
 |  | LL_C2_EXTI_EnableIT_0_31
 |  | LL_C2_EXTI_IsEnabledIT_0_31
C2IMR2 | IMx | LL_C2_EXTI_DisableIT_32_63
 |  | LL_C2_EXTI_EnableIT_32_63
 |  | LL_C2_EXTI_IsEnabledIT_32_63
EMR1 | EMx | LL_EXTI_DisableEvent_0_31
 |  | LL_EXTI_EnableEvent_0_31
 |  | LL_EXTI_IsEnabledEvent_0_31
EMR2 | EMx | LL_C2_EXTI_IsEnabledEvent_32_63
 |  | LL_EXTI_DisableEvent_32_63
 |  | LL_EXTI_EnableEvent_32_63
 |  | LL_EXTI_IsEnabledEvent_32_63
FTSR1 | FTx | LL_EXTI_DisableFallingTrig_0_31
 |  | LL_EXTI_EnableFallingTrig_0_31
 |  | LL_EXTI_IsEnabledFallingTrig_0_31
FTSR2 | FTx | LL_EXTI_DisableFallingTrig_32_63
 |  | LL_EXTI_EnableFallingTrig_32_63
 |  | LL_EXTI_IsEnabledFallingTrig_32_63
IMR1 | IMx | LL_EXTI_DisableIT_0_31
 |  | LL_EXTI_EnableIT_0_31
 |  | LL_EXTI_IsEnabledIT_0_31
IMR2 | IMx | LL_EXTI_DisableIT_32_63
 |  | LL_EXTI_EnableIT_32_63
 |  | LL_EXTI_IsEnabledIT_32_63
PR1 | PIFx | LL_EXTI_ClearFlag_0_31
 |  | LL_EXTI_IsActiveFlag_0_31
 |  | LL_EXTI_ReadFlag_0_31
PR2 | PIFx | LL_EXTI_ClearFlag_32_63
 |  | LL_EXTI_IsActiveFlag_32_63
 |  | LL_EXTI_ReadFlag_32_63
RTSR1 | RTx | LL_EXTI_DisableRisingTrig_0_31
 |  | LL_EXTI_EnableRisingTrig_0_31
 |  | LL_EXTI_IsEnabledRisingTrig_0_31
RTSR2 | RTx | LL_EXTI_DisableRisingTrig_32_63
 |  | LL_EXTI_EnableRisingTrig_32_63
 |  | LL_EXTI_IsEnabledRisingTrig_32_63
SWIER1 | SWIx | LL_EXTI_GenerateSWI_0_31
SWIER2 | SWIx | LL_EXTI_GenerateSWI_32_63
Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: EXTI Private Macros

Defines
EXTI Private Macros
EXTI

Defines

#define | IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
#define | IS_LL_EXTI_LINE_32_63(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U)
#define | IS_LL_EXTI_MODE(__VALUE__)
#define | IS_LL_EXTI_TRIGGER(__VALUE__)

Define Documentation

#define IS_LL_EXTI_LINE_0_31 ( __VALUE__ ) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)

Definition at line 47 of file stm32wbxx_ll_exti.c.

Referenced by LL_EXTI_Init().

#define IS_LL_EXTI_LINE_32_63 ( __VALUE__ ) (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U)

Definition at line 48 of file stm32wbxx_ll_exti.c.

Referenced by LL_EXTI_Init().

#define IS_LL_EXTI_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_EXTI_MODE_IT)            \
                                                   || ((__VALUE__) == LL_EXTI_MODE_EVENT)         \
                                                   || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))

Definition at line 50 of file stm32wbxx_ll_exti.c.

Referenced by LL_EXTI_Init().

#define IS_LL_EXTI_TRIGGER ( __VALUE__ )
Value:
(((__VALUE__) == LL_EXTI_TRIGGER_NONE)       \
                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_RISING)     \
                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING)    \
                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))

Definition at line 55 of file stm32wbxx_ll_exti.c.

Referenced by LL_EXTI_Init().

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LL_EXTI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_EXTI_InitTypeDef Struct Reference
EXTI Exported Init structure

#include <stm32wbxx_ll_exti.h>

Data Fields

uint32_t | Line_0_31
uint32_t | Line_32_63
FunctionalState | LineCommand
uint8_t | Mode
uint8_t | Trigger

Detailed Description

Definition at line 58 of file stm32wbxx_ll_exti.h.

Field Documentation

uint32_t LL_EXTI_InitTypeDef::Line_0_31

Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31 This parameter can be any combination of LINE

Definition at line 61 of file stm32wbxx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

uint32_t LL_EXTI_InitTypeDef::Line_32_63

Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63 This parameter can be any combination of LINE

Definition at line 64 of file stm32wbxx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

FunctionalState LL_EXTI_InitTypeDef::LineCommand

Specifies the new state of the selected EXTI lines. This parameter can be set either to ENABLE or DISABLE

Definition at line 67 of file stm32wbxx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

uint8_t LL_EXTI_InitTypeDef::Mode

Specifies the mode for the EXTI lines. This parameter can be a value of Mode.

Definition at line 70 of file stm32wbxx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

uint8_t LL_EXTI_InitTypeDef::Trigger

Specifies the trigger signal active edge for the EXTI lines. This parameter can be a value of Edge Trigger.

Definition at line 73 of file stm32wbxx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

The documentation for this struct was generated from the following file:
  • stm32wbxx_ll_exti.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LINE

Defines
LINE
EXTI Exported Constants

Defines

#define | LL_EXTI_LINE_0 EXTI_IMR1_IM0
#define | LL_EXTI_LINE_1 EXTI_IMR1_IM1
#define | LL_EXTI_LINE_2 EXTI_IMR1_IM2
#define | LL_EXTI_LINE_3 EXTI_IMR1_IM3
#define | LL_EXTI_LINE_4 EXTI_IMR1_IM4
#define | LL_EXTI_LINE_5 EXTI_IMR1_IM5
#define | LL_EXTI_LINE_6 EXTI_IMR1_IM6
#define | LL_EXTI_LINE_7 EXTI_IMR1_IM7
#define | LL_EXTI_LINE_8 EXTI_IMR1_IM8
#define | LL_EXTI_LINE_9 EXTI_IMR1_IM9
#define | LL_EXTI_LINE_10 EXTI_IMR1_IM10
#define | LL_EXTI_LINE_11 EXTI_IMR1_IM11
#define | LL_EXTI_LINE_12 EXTI_IMR1_IM12
#define | LL_EXTI_LINE_13 EXTI_IMR1_IM13
#define | LL_EXTI_LINE_14 EXTI_IMR1_IM14
#define | LL_EXTI_LINE_15 EXTI_IMR1_IM15
#define | LL_EXTI_LINE_16 EXTI_IMR1_IM16
#define | LL_EXTI_LINE_17 EXTI_IMR1_IM17
#define | LL_EXTI_LINE_18 EXTI_IMR1_IM18
#define | LL_EXTI_LINE_19 EXTI_IMR1_IM19
#define | LL_EXTI_LINE_20 EXTI_IMR1_IM20
#define | LL_EXTI_LINE_21 EXTI_IMR1_IM21
#define | LL_EXTI_LINE_22 EXTI_IMR1_IM22
#define | LL_EXTI_LINE_23 EXTI_IMR1_IM23
#define | LL_EXTI_LINE_24 EXTI_IMR1_IM24
#define | LL_EXTI_LINE_25 EXTI_IMR1_IM25
#define | LL_EXTI_LINE_28 EXTI_IMR1_IM28
#define | LL_EXTI_LINE_29 EXTI_IMR1_IM29
#define | LL_EXTI_LINE_30 EXTI_IMR1_IM30
#define | LL_EXTI_LINE_31 EXTI_IMR1_IM31
#define | LL_EXTI_LINE_ALL_0_31
#define | LL_EXTI_LINE_33 EXTI_IMR2_IM33
#define | LL_EXTI_LINE_36 EXTI_IMR2_IM36
#define | LL_EXTI_LINE_37 EXTI_IMR2_IM37
#define | LL_EXTI_LINE_38 EXTI_IMR2_IM38
#define | LL_EXTI_LINE_39 EXTI_IMR2_IM39
#define | LL_EXTI_LINE_40 EXTI_IMR2_IM40
#define | LL_EXTI_LINE_41 EXTI_IMR2_IM41
#define | LL_EXTI_LINE_42 EXTI_IMR2_IM42
#define | LL_EXTI_LINE_43 EXTI_IMR2_IM43
#define | LL_EXTI_LINE_44 EXTI_IMR2_IM44
#define | LL_EXTI_LINE_45 EXTI_IMR2_IM45
#define | LL_EXTI_LINE_46 EXTI_IMR2_IM46
#define | LL_EXTI_LINE_48 EXTI_IMR2_IM48
#define | LL_EXTI_LINE_ALL_32_63
#define | LL_EXTI_LINE_ALL (0xFFFFFFFFU)
#define | LL_EXTI_LINE_NONE (0x00000000U)

Define Documentation

#define LL_EXTI_LINE_0 EXTI_IMR1_IM0

Extended line 0

Definition at line 90 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_1 EXTI_IMR1_IM1

Extended line 1

Definition at line 91 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_10 EXTI_IMR1_IM10

Extended line 10

Definition at line 100 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_11 EXTI_IMR1_IM11

Extended line 11

Definition at line 101 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_12 EXTI_IMR1_IM12

Extended line 12

Definition at line 102 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_13 EXTI_IMR1_IM13

Extended line 13

Definition at line 103 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_14 EXTI_IMR1_IM14

Extended line 14

Definition at line 104 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_15 EXTI_IMR1_IM15

Extended line 15

Definition at line 105 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_16 EXTI_IMR1_IM16

Extended line 16

Definition at line 106 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_17 EXTI_IMR1_IM17

Extended line 17

Definition at line 107 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_18 EXTI_IMR1_IM18

Extended line 18

Definition at line 108 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_19 EXTI_IMR1_IM19

Extended line 19

Definition at line 109 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_2 EXTI_IMR1_IM2

Extended line 2

Definition at line 92 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_20 EXTI_IMR1_IM20

Extended line 20

Definition at line 110 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_21 EXTI_IMR1_IM21

Extended line 21

Definition at line 111 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_22 EXTI_IMR1_IM22

Extended line 22

Definition at line 112 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_23 EXTI_IMR1_IM23

Extended line 23

Definition at line 113 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_24 EXTI_IMR1_IM24

Extended line 24

Definition at line 114 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_25 EXTI_IMR1_IM25

Extended line 25

Definition at line 115 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_28 EXTI_IMR1_IM28

Extended line 28

Definition at line 116 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_29 EXTI_IMR1_IM29

Extended line 29

Definition at line 117 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_3 EXTI_IMR1_IM3

Extended line 3

Definition at line 93 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_30 EXTI_IMR1_IM30

Extended line 30

Definition at line 118 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_31 EXTI_IMR1_IM31

Extended line 31

Definition at line 119 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_33 EXTI_IMR2_IM33

Extended line 33

Definition at line 131 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_36 EXTI_IMR2_IM36

Extended line 36

Definition at line 132 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_37 EXTI_IMR2_IM37

Extended line 37

Definition at line 133 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_38 EXTI_IMR2_IM38

Extended line 38

Definition at line 134 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_39 EXTI_IMR2_IM39

Extended line 39

Definition at line 135 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_4 EXTI_IMR1_IM4

Extended line 4

Definition at line 94 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_40 EXTI_IMR2_IM40

Extended line 40

Definition at line 136 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_41 EXTI_IMR2_IM41

Extended line 41

Definition at line 137 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_42 EXTI_IMR2_IM42

Extended line 42

Definition at line 138 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_43 EXTI_IMR2_IM43

Extended line 43

Definition at line 140 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_44 EXTI_IMR2_IM44

Extended line 44

Definition at line 142 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_45 EXTI_IMR2_IM45

Extended line 45

Definition at line 143 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_46 EXTI_IMR2_IM46

Extended line 46

Definition at line 144 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_48 EXTI_IMR2_IM48

Extended line 48

Definition at line 145 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_5 EXTI_IMR1_IM5

Extended line 5

Definition at line 95 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_6 EXTI_IMR1_IM6

Extended line 6

Definition at line 96 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_7 EXTI_IMR1_IM7

Extended line 7

Definition at line 97 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_8 EXTI_IMR1_IM8

Extended line 8

Definition at line 98 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_9 EXTI_IMR1_IM9

Extended line 9

Definition at line 99 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_ALL (0xFFFFFFFFU)

All Extended line

Definition at line 160 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_ALL_0_31
Value:
(LL_EXTI_LINE_0 | LL_EXTI_LINE_1 | LL_EXTI_LINE_2 | \
                                        LL_EXTI_LINE_3 | LL_EXTI_LINE_4 | LL_EXTI_LINE_5 | \
                                        LL_EXTI_LINE_6 | LL_EXTI_LINE_7 | LL_EXTI_LINE_8 | \
                                        LL_EXTI_LINE_9 | LL_EXTI_LINE_10 | LL_EXTI_LINE_11 | \
                                        LL_EXTI_LINE_12 | LL_EXTI_LINE_13 | LL_EXTI_LINE_14 | \
                                        LL_EXTI_LINE_15 | LL_EXTI_LINE_16 | LL_EXTI_LINE_17 | \
                                        LL_EXTI_LINE_18 | LL_EXTI_LINE_19 | LL_EXTI_LINE_20 | \
                                        LL_EXTI_LINE_21 | LL_EXTI_LINE_22 | LL_EXTI_LINE_23 | \
                                        LL_EXTI_LINE_24 | LL_EXTI_LINE_25 | LL_EXTI_LINE_28 | \
                                        LL_EXTI_LINE_29 | LL_EXTI_LINE_30 | LL_EXTI_LINE_31)

All Extended line not reserved

Definition at line 120 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_ALL_32_63
Value:
(LL_EXTI_LINE_33 | LL_EXTI_LINE_36 | LL_EXTI_LINE_37 | \
                                        LL_EXTI_LINE_38 | LL_EXTI_LINE_39 | LL_EXTI_LINE_40 | \
                                        LL_EXTI_LINE_41 | LL_EXTI_LINE_42 | LL_EXTI_LINE_43 | \
                                        LL_EXTI_LINE_44 | LL_EXTI_LINE_45 | LL_EXTI_LINE_46 | \
                                        LL_EXTI_LINE_48)

All Extended line not reserved

Definition at line 147 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_LINE_NONE (0x00000000U)

None Extended line

Definition at line 163 of file stm32wbxx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Mode

Defines
Mode
EXTI Exported Constants

Defines

#define | LL_EXTI_MODE_IT ((uint8_t)0x00U)
#define | LL_EXTI_MODE_EVENT ((uint8_t)0x01U)
#define | LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U)

Define Documentation

#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U)

Event Mode

Definition at line 175 of file stm32wbxx_ll_exti.h.

Referenced by LL_EXTI_Init().

#define LL_EXTI_MODE_IT ((uint8_t)0x00U)

Interrupt Mode

Definition at line 174 of file stm32wbxx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U)

Interrupt & Event Mode

Definition at line 176 of file stm32wbxx_ll_exti.h.

Referenced by LL_EXTI_Init().

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Edge Trigger

Defines
Edge Trigger
EXTI Exported Constants

Defines

#define | LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U)
#define | LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U)
#define | LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U)
#define | LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U)

Define Documentation

#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U)

Trigger Falling Mode

Definition at line 186 of file stm32wbxx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U)

No Trigger Mode

Definition at line 184 of file stm32wbxx_ll_exti.h.

Referenced by LL_EXTI_Init().

#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U)

Trigger Rising Mode

Definition at line 185 of file stm32wbxx_ll_exti.h.

Referenced by LL_EXTI_Init().

#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U)

Trigger Rising & Falling Mode

Definition at line 187 of file stm32wbxx_ll_exti.h.

Referenced by LL_EXTI_Init().

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
EXTI Exported Macros

Defines

#define | LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
Write a value in EXTI register.
#define | LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
Read a value in EXTI register.

Define Documentation

#define LL_EXTI_ReadReg ( __REG__ ) READ_REG(EXTI->__REG__)

Read a value in EXTI register.

Parameters:
__REG__ Register to be read
Return values:
Register value

Definition at line 223 of file stm32wbxx_ll_exti.h.

#define LL_EXTI_WriteReg | ( | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(EXTI->__REG__, (__VALUE__))

Write a value in EXTI register.

Parameters:
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 216 of file stm32wbxx_ll_exti.h.

Referenced by LL_EXTI_DeInit().

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IT_Management

Functions
IT_Management
EXTI Exported Functions

Functions

__STATIC_INLINE void | LL_EXTI_EnableIT_0_31 (uint32_t ExtiLine)
Enable ExtiLine Interrupt request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_C2_EXTI_EnableIT_0_31 (uint32_t ExtiLine)
Enable ExtiLine Interrupt request for Lines in range 0 to 31 for cpu2.
__STATIC_INLINE void | LL_EXTI_EnableIT_32_63 (uint32_t ExtiLine)
Enable ExtiLine Interrupt request for Lines in range 32 to 63.
__STATIC_INLINE void | LL_C2_EXTI_EnableIT_32_63 (uint32_t ExtiLine)
Enable ExtiLine Interrupt request for Lines in range 32 to 63 for cpu2.
__STATIC_INLINE void | LL_EXTI_DisableIT_0_31 (uint32_t ExtiLine)
Disable ExtiLine Interrupt request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_C2_EXTI_DisableIT_0_31 (uint32_t ExtiLine)
Disable ExtiLine Interrupt request for Lines in range 0 to 31 for cpu2.
__STATIC_INLINE void | LL_EXTI_DisableIT_32_63 (uint32_t ExtiLine)
Disable ExtiLine Interrupt request for Lines in range 32 to 63.
__STATIC_INLINE void | LL_C2_EXTI_DisableIT_32_63 (uint32_t ExtiLine)
Disable ExtiLine Interrupt request for Lines in range 32 to 63 for cpu2.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledIT_0_31 (uint32_t ExtiLine)
Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_C2_EXTI_IsEnabledIT_0_31 (uint32_t ExtiLine)
Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 for cpu2.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledIT_32_63 (uint32_t ExtiLine)
Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_C2_EXTI_IsEnabledIT_32_63 (uint32_t ExtiLine)
Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63 for cpu2.

Function Documentation

__STATIC_INLINE void LL_C2_EXTI_DisableIT_0_31 ( uint32_t ExtiLine )

Disable ExtiLine Interrupt request for Lines in range 0 to 31 for cpu2.

Reference Manual to LL API cross reference:
C2IMR1 IMx LL_C2_EXTI_DisableIT_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_23
  • LL_EXTI_LINE_24
  • LL_EXTI_LINE_25
  • LL_EXTI_LINE_28
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
  • LL_EXTI_LINE_ALL_0_31
Return values:
None

Definition at line 458 of file stm32wbxx_ll_exti.h.

__STATIC_INLINE void LL_C2_EXTI_DisableIT_32_63 ( uint32_t ExtiLine )

Disable ExtiLine Interrupt request for Lines in range 32 to 63 for cpu2.

Reference Manual to LL API cross reference:
C2IMR2 IMx LL_C2_EXTI_DisableIT_32_63
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_33
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_37
  • LL_EXTI_LINE_38
  • LL_EXTI_LINE_39
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
  • LL_EXTI_LINE_42
  • LL_EXTI_LINE_43 (*)
  • LL_EXTI_LINE_44
  • LL_EXTI_LINE_45
  • LL_EXTI_LINE_46
  • LL_EXTI_LINE_48
  • LL_EXTI_LINE_ALL_32_63 (*) value not defined in all devices
Return values:
None

Definition at line 510 of file stm32wbxx_ll_exti.h.

__STATIC_INLINE void LL_C2_EXTI_EnableIT_0_31 ( uint32_t ExtiLine )

Enable ExtiLine Interrupt request for Lines in range 0 to 31 for cpu2.

Reference Manual to LL API cross reference:
C2IMR1 IMx LL_C2_EXTI_EnableIT_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_23
  • LL_EXTI_LINE_24
  • LL_EXTI_LINE_25
  • LL_EXTI_LINE_28
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
  • LL_EXTI_LINE_ALL_0_31
Return values:
None

Definition at line 322 of file stm32wbxx_ll_exti.h.

__STATIC_INLINE void LL_C2_EXTI_EnableIT_32_63 ( uint32_t ExtiLine )

Enable ExtiLine Interrupt request for Lines in range 32 to 63 for cpu2.

Reference Manual to LL API cross reference:
C2IMR2 IMx LL_C2_EXTI_EnableIT_32_63
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_33
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_37
  • LL_EXTI_LINE_38
  • LL_EXTI_LINE_39
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
  • LL_EXTI_LINE_42
  • LL_EXTI_LINE_43 (*)
  • LL_EXTI_LINE_44
  • LL_EXTI_LINE_45
  • LL_EXTI_LINE_46
  • LL_EXTI_LINE_48
  • LL_EXTI_LINE_ALL_32_63 (*) value not defined in all devices
Return values:
None

Definition at line 374 of file stm32wbxx_ll_exti.h.

__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_0_31 ( uint32_t ExtiLine )

Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 for cpu2.

Reference Manual to LL API cross reference:
C2IMR1 IMx LL_C2_EXTI_IsEnabledIT_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_23
  • LL_EXTI_LINE_24
  • LL_EXTI_LINE_25
  • LL_EXTI_LINE_28
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
  • LL_EXTI_LINE_ALL_0_31
Return values:
State of bit (1 or 0).

Definition at line 594 of file stm32wbxx_ll_exti.h.

__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_32_63 ( uint32_t ExtiLine )

Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63 for cpu2.

Reference Manual to LL API cross reference:
C2IMR2 IMx LL_C2_EXTI_IsEnabledIT_32_63
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_33
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_37
  • LL_EXTI_LINE_38
  • LL_EXTI_LINE_39
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
  • LL_EXTI_LINE_42
  • LL_EXTI_LINE_43 (*)
  • LL_EXTI_LINE_44
  • LL_EXTI_LINE_45
  • LL_EXTI_LINE_46
  • LL_EXTI_LINE_48
  • LL_EXTI_LINE_ALL_32_63 (*) value not defined in all devices
Return values:
State of bit (1 or 0).

Definition at line 646 of file stm32wbxx_ll_exti.h.

__STATIC_INLINE void LL_EXTI_DisableIT_0_31 ( uint32_t ExtiLine )

Disable ExtiLine Interrupt request for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
IMR1 IMx LL_EXTI_DisableIT_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_23
  • LL_EXTI_LINE_24
  • LL_EXTI_LINE_25
  • LL_EXTI_LINE_28
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
  • LL_EXTI_LINE_ALL_0_31
Return values:
None

Definition at line 416 of file stm32wbxx_ll_exti.h.

Referenced by HAL_COMP_Init(), and LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_DisableIT_32_63 ( uint32_t ExtiLine )

Disable ExtiLine Interrupt request for Lines in range 32 to 63.

Reference Manual to LL API cross reference:
IMR2 IMx LL_EXTI_DisableIT_32_63
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_33
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_37
  • LL_EXTI_LINE_38
  • LL_EXTI_LINE_39
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
  • LL_EXTI_LINE_42
  • LL_EXTI_LINE_43 (*)
  • LL_EXTI_LINE_44
  • LL_EXTI_LINE_45
  • LL_EXTI_LINE_46
  • LL_EXTI_LINE_48
  • LL_EXTI_LINE_ALL_32_63 (*) value not defined in all devices
Return values:
None

Definition at line 484 of file stm32wbxx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableIT_0_31 ( uint32_t ExtiLine )

Enable ExtiLine Interrupt request for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
IMR1 IMx LL_EXTI_EnableIT_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_23
  • LL_EXTI_LINE_24
  • LL_EXTI_LINE_25
  • LL_EXTI_LINE_28
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
  • LL_EXTI_LINE_ALL_0_31
Return values:
None

Definition at line 280 of file stm32wbxx_ll_exti.h.

Referenced by HAL_COMP_Init(), and LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableIT_32_63 ( uint32_t ExtiLine )

Enable ExtiLine Interrupt request for Lines in range 32 to 63.

Reference Manual to LL API cross reference:
IMR2 IMx LL_EXTI_EnableIT_32_63
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_33
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_37
  • LL_EXTI_LINE_38
  • LL_EXTI_LINE_39
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
  • LL_EXTI_LINE_42
  • LL_EXTI_LINE_43 (*)
  • LL_EXTI_LINE_44
  • LL_EXTI_LINE_45
  • LL_EXTI_LINE_46
  • LL_EXTI_LINE_48
  • LL_EXTI_LINE_ALL_32_63 (*) value not defined in all devices
Return values:
None

Definition at line 348 of file stm32wbxx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31 ( uint32_t ExtiLine )

Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
IMR1 IMx LL_EXTI_IsEnabledIT_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_22
  • LL_EXTI_LINE_23
  • LL_EXTI_LINE_24
  • LL_EXTI_LINE_25
  • LL_EXTI_LINE_28
  • LL_EXTI_LINE_29
  • LL_EXTI_LINE_30
  • LL_EXTI_LINE_31
  • LL_EXTI_LINE_ALL_0_31
Return values:
State of bit (1 or 0).

Definition at line 552 of file stm32wbxx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63 ( uint32_t ExtiLine )

Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63.

Reference Manual to LL API cross reference:
IMR2 IMx LL_EXTI_IsEnabledIT_32_63
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_33
  • LL_EXTI_LINE_36
  • LL_EXTI_LINE_37
  • LL_EXTI_LINE_38
  • LL_EXTI_LINE_39
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
  • LL_EXTI_LINE_42
  • LL_EXTI_LINE_43 (*)
  • LL_EXTI_LINE_44
  • LL_EXTI_LINE_45
  • LL_EXTI_LINE_46
  • LL_EXTI_LINE_48
  • LL_EXTI_LINE_ALL_32_63 (*) value not defined in all devices
Return values:
State of bit (1 or 0).

Definition at line 620 of file stm32wbxx_ll_exti.h.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Event_Management

Functions
Event_Management
EXTI Exported Functions

Functions

__STATIC_INLINE void | LL_EXTI_EnableEvent_0_31 (uint32_t ExtiLine)
Enable ExtiLine Event request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_C2_EXTI_EnableEvent_0_31 (uint32_t ExtiLine)
Enable ExtiLine Event request for Lines in range 0 to 31 for cpu2.
__STATIC_INLINE void | LL_EXTI_EnableEvent_32_63 (uint32_t ExtiLine)
Enable ExtiLine Event request for Lines in range 32 to 63.
__STATIC_INLINE void | LL_C2_EXTI_EnableEvent_32_63 (uint32_t ExtiLine)
Enable ExtiLine Event request for Lines in range 32 to 63 for cpu2.
__STATIC_INLINE void | LL_EXTI_DisableEvent_0_31 (uint32_t ExtiLine)
Disable ExtiLine Event request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_C2_EXTI_DisableEvent_0_31 (uint32_t ExtiLine)
Disable ExtiLine Event request for Lines in range 0 to 31 for cpu2.
__STATIC_INLINE void | LL_EXTI_DisableEvent_32_63 (uint32_t ExtiLine)
Disable ExtiLine Event request for Lines in range 32 to 63.
__STATIC_INLINE void | LL_C2_EXTI_DisableEvent_32_63 (uint32_t ExtiLine)
Disable ExtiLine Event request for Lines in range 32 to 63 for cpu2.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledEvent_0_31 (uint32_t ExtiLine)
Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_C2_EXTI_IsEnabledEvent_0_31 (uint32_t ExtiLine)
Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 for cpu2.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledEvent_32_63 (uint32_t ExtiLine)
Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_C2_EXTI_IsEnabledEvent_32_63 (uint32_t ExtiLine)
Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63 for cpu2.

Function Documentation

__STATIC_INLINE void LL_C2_EXTI_DisableEvent_0_31 ( uint32_t ExtiLine )

Disable ExtiLine Event request for Lines in range 0 to 31 for cpu2.

Reference Manual to LL API cross reference:
C2EMR1 EMx LL_C2_EXTI_DisableEvent_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_ALL_0_31
Return values:
None

Definition at line 814 of file stm32wbxx_ll_exti.h.

__STATIC_INLINE void LL_C2_EXTI_DisableEvent_32_63 ( uint32_t ExtiLine )

Disable ExtiLine Event request for Lines in range 32 to 63 for cpu2.

Reference Manual to LL API cross reference:
C2EMR2 EMx LL_C2_EXTI_DisableEvent_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
  • LL_EXTI_LINE_ALL_32_63
Return values:
None

Definition at line 842 of file stm32wbxx_ll_exti.h.

__STATIC_INLINE void LL_C2_EXTI_EnableEvent_0_31 ( uint32_t ExtiLine )

Enable ExtiLine Event request for Lines in range 0 to 31 for cpu2.

Reference Manual to LL API cross reference:
C2EMR1 EMx LL_C2_EXTI_EnableEvent_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_ALL_0_31
Return values:
None

Definition at line 720 of file stm32wbxx_ll_exti.h.

__STATIC_INLINE void LL_C2_EXTI_EnableEvent_32_63 ( uint32_t ExtiLine )

Enable ExtiLine Event request for Lines in range 32 to 63 for cpu2.

Reference Manual to LL API cross reference:
C2EMR2 EMx LL_C2_EXTI_EnableEvent_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
  • LL_EXTI_LINE_ALL_32_63
Return values:
None

Definition at line 748 of file stm32wbxx_ll_exti.h.

__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_0_31 ( uint32_t ExtiLine )

Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 for cpu2.

Reference Manual to LL API cross reference:
C2EMR1 EMx LL_C2_EXTI_IsEnabledEvent_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_ALL_0_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
State of bit (1 or 0).

Definition at line 910 of file stm32wbxx_ll_exti.h.

__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_32_63 ( uint32_t ExtiLine )

Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63 for cpu2.

Reference Manual to LL API cross reference:
EMR2 EMx LL_C2_EXTI_IsEnabledEvent_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
  • LL_EXTI_LINE_ALL_32_63
Return values:
State of bit (1 or 0).

Definition at line 938 of file stm32wbxx_ll_exti.h.

__STATIC_INLINE void LL_EXTI_DisableEvent_0_31 ( uint32_t ExtiLine )

Disable ExtiLine Event request for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
EMR1 EMx LL_EXTI_DisableEvent_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_ALL_0_31
Return values:
None

Definition at line 781 of file stm32wbxx_ll_exti.h.

Referenced by HAL_COMP_Init(), and LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_DisableEvent_32_63 ( uint32_t ExtiLine )

Disable ExtiLine Event request for Lines in range 32 to 63.

Reference Manual to LL API cross reference:
EMR2 EMx LL_EXTI_DisableEvent_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
  • LL_EXTI_LINE_ALL_32_63
Return values:
None

Definition at line 828 of file stm32wbxx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableEvent_0_31 ( uint32_t ExtiLine )

Enable ExtiLine Event request for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
EMR1 EMx LL_EXTI_EnableEvent_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_ALL_0_31
Return values:
None

Definition at line 687 of file stm32wbxx_ll_exti.h.

Referenced by HAL_COMP_Init(), and LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableEvent_32_63 ( uint32_t ExtiLine )

Enable ExtiLine Event request for Lines in range 32 to 63.

Reference Manual to LL API cross reference:
EMR2 EMx LL_EXTI_EnableEvent_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
  • LL_EXTI_LINE_ALL_32_63
Return values:
None

Definition at line 734 of file stm32wbxx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31 ( uint32_t ExtiLine )

Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
EMR1 EMx LL_EXTI_IsEnabledEvent_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_ALL_0_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
State of bit (1 or 0).

Definition at line 876 of file stm32wbxx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63 ( uint32_t ExtiLine )

Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63.

Reference Manual to LL API cross reference:
EMR2 EMx LL_EXTI_IsEnabledEvent_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
  • LL_EXTI_LINE_ALL_32_63
Return values:
State of bit (1 or 0).

Definition at line 924 of file stm32wbxx_ll_exti.h.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Rising_Trigger_Management

Functions
Rising_Trigger_Management
EXTI Exported Functions

Functions

__STATIC_INLINE void | LL_EXTI_EnableRisingTrig_0_31 (uint32_t ExtiLine)
Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableRisingTrig_32_63 (uint32_t ExtiLine)
Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_DisableRisingTrig_0_31 (uint32_t ExtiLine)
Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableRisingTrig_32_63 (uint32_t ExtiLine)
Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledRisingTrig_0_31 (uint32_t ExtiLine)
Check if rising edge trigger is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledRisingTrig_32_63 (uint32_t ExtiLine)
Check if rising edge trigger is enabled for Lines in range 32 to 63.

Function Documentation

__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31 ( uint32_t ExtiLine )

Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a rising edge on a configurable interrupt line occurs during a write operation in the EXTI_RTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
RTSR1 RTx LL_EXTI_DisableRisingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_31
Return values:
None

Definition at line 1049 of file stm32wbxx_ll_exti.h.

Referenced by HAL_COMP_Init(), and LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63 ( uint32_t ExtiLine )

Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a rising edge on a configurable interrupt line occurs during a write operation in the EXTI_RTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
RTSR2 RTx LL_EXTI_DisableRisingTrig_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_33
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
Return values:
None

Definition at line 1071 of file stm32wbxx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31 ( uint32_t ExtiLine )

Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a rising edge on a configurable interrupt line occurs during a write operation in the EXTI_RTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
RTSR1 RTx LL_EXTI_EnableRisingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_31
Return values:
None

Definition at line 987 of file stm32wbxx_ll_exti.h.

Referenced by HAL_COMP_Init(), and LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63 ( uint32_t ExtiLine )

Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a rising edge on a configurable interrupt line occurs during a write operation in the EXTI_RTSR register, the pending bit is not set.Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
RTSR2 RTx LL_EXTI_EnableRisingTrig_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_33
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
Return values:
None

Definition at line 1008 of file stm32wbxx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31 ( uint32_t ExtiLine )

Check if rising edge trigger is enabled for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
RTSR1 RTx LL_EXTI_IsEnabledRisingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_31
Return values:
State of bit (1 or 0).

Definition at line 1105 of file stm32wbxx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63 ( uint32_t ExtiLine )

Check if rising edge trigger is enabled for Lines in range 32 to 63.

Reference Manual to LL API cross reference:
RTSR2 RTx LL_EXTI_IsEnabledRisingTrig_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_33
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
Return values:
State of bit (1 or 0).

Definition at line 1119 of file stm32wbxx_ll_exti.h.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Falling_Trigger_Management

Functions
Falling_Trigger_Management
EXTI Exported Functions

Functions

__STATIC_INLINE void | LL_EXTI_EnableFallingTrig_0_31 (uint32_t ExtiLine)
Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableFallingTrig_32_63 (uint32_t ExtiLine)
Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_DisableFallingTrig_0_31 (uint32_t ExtiLine)
Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableFallingTrig_32_63 (uint32_t ExtiLine)
Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledFallingTrig_0_31 (uint32_t ExtiLine)
Check if falling edge trigger is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledFallingTrig_32_63 (uint32_t ExtiLine)
Check if falling edge trigger is enabled for Lines in range 32 to 63.

Function Documentation

__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31 ( uint32_t ExtiLine )

Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a Falling edge on a configurable interrupt line occurs during a write operation in the EXTI_FTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
FTSR1 FTx LL_EXTI_DisableFallingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 1231 of file stm32wbxx_ll_exti.h.

Referenced by HAL_COMP_Init(), and LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63 ( uint32_t ExtiLine )

Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a Falling edge on a configurable interrupt line occurs during a write operation in the EXTI_FTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
FTSR2 FTx LL_EXTI_DisableFallingTrig_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_33
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
Return values:
None

Definition at line 1251 of file stm32wbxx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31 ( uint32_t ExtiLine )

Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a falling edge on a configurable interrupt line occurs during a write operation in the EXTI_FTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
FTSR1 FTx LL_EXTI_EnableFallingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 1169 of file stm32wbxx_ll_exti.h.

Referenced by HAL_COMP_Init(), and LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63 ( uint32_t ExtiLine )

Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a Falling edge on a configurable interrupt line occurs during a write operation in the EXTI_FTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
FTSR2 FTx LL_EXTI_EnableFallingTrig_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_33
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
Return values:
None

Definition at line 1190 of file stm32wbxx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31 ( uint32_t ExtiLine )

Check if falling edge trigger is enabled for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
FTSR1 FTx LL_EXTI_IsEnabledFallingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
State of bit (1 or 0).

Definition at line 1286 of file stm32wbxx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63 ( uint32_t ExtiLine )

Check if falling edge trigger is enabled for Lines in range 32 to 63.

Reference Manual to LL API cross reference:
FTSR2 FTx LL_EXTI_IsEnabledFallingTrig_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_33
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
Return values:
State of bit (1 or 0).

Definition at line 1300 of file stm32wbxx_ll_exti.h.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Software_Interrupt_Management

Functions
Software_Interrupt_Management
EXTI Exported Functions

Functions

__STATIC_INLINE void | LL_EXTI_GenerateSWI_0_31 (uint32_t ExtiLine)
Generate a software Interrupt Event for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_GenerateSWI_32_63 (uint32_t ExtiLine)
Generate a software Interrupt Event for Lines in range 32 to 63.

Function Documentation

__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31 ( uint32_t ExtiLine )

Generate a software Interrupt Event for Lines in range 0 to 31.

Note:
If the interrupt is enabled on this line in the EXTI_IMR1, writing a 1 to this bit when it is at '0' sets the corresponding pending bit in EXTI_PR1 resulting in an interrupt request generation. This bit is cleared by clearing the corresponding bit in the EXTI_PR1 register (by writing a 1 into the bit)
Reference Manual to LL API cross reference:
SWIER1 SWIx LL_EXTI_GenerateSWI_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 1348 of file stm32wbxx_ll_exti.h.

__STATIC_INLINE void LL_EXTI_GenerateSWI_32_63 ( uint32_t ExtiLine )

Generate a software Interrupt Event for Lines in range 32 to 63.

Note:
If the interrupt is enabled on this line inthe EXTI_IMR2, writing a 1 to this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2 resulting in an interrupt request generation. This bit is cleared by clearing the corresponding bit in the EXTI_PR2 register (by writing a 1 into the bit)
Reference Manual to LL API cross reference:
SWIER2 SWIx LL_EXTI_GenerateSWI_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_33
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
Return values:
None

Definition at line 1367 of file stm32wbxx_ll_exti.h.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Flag_Management

Functions
Flag_Management
EXTI Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_EXTI_IsActiveFlag_0_31 (uint32_t ExtiLine)
Check if the ExtLine Flag is set or not for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsActiveFlag_32_63 (uint32_t ExtiLine)
Check if the ExtLine Flag is set or not for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_ReadFlag_0_31 (uint32_t ExtiLine)
Read ExtLine Combination Flag for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_ReadFlag_32_63 (uint32_t ExtiLine)
Read ExtLine Combination Flag for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_ClearFlag_0_31 (uint32_t ExtiLine)
Clear ExtLine Flags for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_ClearFlag_32_63 (uint32_t ExtiLine)
Clear ExtLine Flags for Lines in range 32 to 63.

Function Documentation

__STATIC_INLINE void LL_EXTI_ClearFlag_0_31 ( uint32_t ExtiLine )

Clear ExtLine Flags for Lines in range 0 to 31.

Note:
This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
PR1 PIFx LL_EXTI_ClearFlag_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_31
Return values:
None

Definition at line 1515 of file stm32wbxx_ll_exti.h.

Referenced by HAL_COMP_Init(), and HAL_COMP_IRQHandler().

__STATIC_INLINE void LL_EXTI_ClearFlag_32_63 ( uint32_t ExtiLine )

Clear ExtLine Flags for Lines in range 32 to 63.

Note:
This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
PR2 PIFx LL_EXTI_ClearFlag_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_33
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
Return values:
None

Definition at line 1531 of file stm32wbxx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31 ( uint32_t ExtiLine )

Check if the ExtLine Flag is set or not for Lines in range 0 to 31.

Note:
This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
PR1 PIFx LL_EXTI_IsActiveFlag_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_31
Return values:
State of bit (1 or 0).

Definition at line 1411 of file stm32wbxx_ll_exti.h.

Referenced by HAL_COMP_IRQHandler().

__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63 ( uint32_t ExtiLine )

Check if the ExtLine Flag is set or not for Lines in range 32 to 63.

Note:
This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
PR2 PIFx LL_EXTI_IsActiveFlag_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_33
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
Return values:
State of bit (1 or 0).

Definition at line 1427 of file stm32wbxx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31 ( uint32_t ExtiLine )

Read ExtLine Combination Flag for Lines in range 0 to 31.

Note:
This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
PR1 PIFx LL_EXTI_ReadFlag_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_20
  • LL_EXTI_LINE_21
  • LL_EXTI_LINE_31
Return values:
@note This bit is set when the selected edge event arrives on the interrupt

Definition at line 1463 of file stm32wbxx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_32_63 ( uint32_t ExtiLine )

Read ExtLine Combination Flag for Lines in range 32 to 63.

Note:
This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
PR2 PIFx LL_EXTI_ReadFlag_32_63
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_33
  • LL_EXTI_LINE_40
  • LL_EXTI_LINE_41
Return values:
@note This bit is set when the selected edge event arrives on the interrupt

Definition at line 1479 of file stm32wbxx_ll_exti.h.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
EXTI Exported Functions

Functions

ErrorStatus | LL_EXTI_DeInit (void)
De-initialize the EXTI registers to their default reset values.
ErrorStatus | LL_EXTI_Init (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
void | LL_EXTI_StructInit (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Set each LL_EXTI_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_EXTI_DeInit ( void )

De-initialize the EXTI registers to their default reset values.

Return values:
An ErrorStatus enumeration value:
  • SUCCESS: EXTI registers are de-initialized
  • ERROR: not applicable

Definition at line 81 of file stm32wbxx_ll_exti.c.

References LL_EXTI_WriteReg.

ErrorStatus LL_EXTI_Init ( LL_EXTI_InitTypeDef * EXTI_InitStruct )

Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.

Parameters:
EXTI_InitStruct pointer to a LL_EXTI_InitTypeDef structure.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: EXTI registers are initialized
  • ERROR: not applicable

Definition at line 133 of file stm32wbxx_ll_exti.c.

References assert_param, IS_LL_EXTI_LINE_0_31, IS_LL_EXTI_LINE_32_63, IS_LL_EXTI_MODE, IS_LL_EXTI_TRIGGER, LL_EXTI_InitTypeDef::Line_0_31, LL_EXTI_InitTypeDef::Line_32_63, LL_EXTI_InitTypeDef::LineCommand, LL_EXTI_DisableEvent_0_31(), LL_EXTI_DisableEvent_32_63(), LL_EXTI_DisableFallingTrig_0_31(), LL_EXTI_DisableFallingTrig_32_63(), LL_EXTI_DisableIT_0_31(), LL_EXTI_DisableIT_32_63(), LL_EXTI_DisableRisingTrig_0_31(), LL_EXTI_DisableRisingTrig_32_63(), LL_EXTI_EnableEvent_0_31(), LL_EXTI_EnableEvent_32_63(), LL_EXTI_EnableFallingTrig_0_31(), LL_EXTI_EnableFallingTrig_32_63(), LL_EXTI_EnableIT_0_31(), LL_EXTI_EnableIT_32_63(), LL_EXTI_EnableRisingTrig_0_31(), LL_EXTI_EnableRisingTrig_32_63(), LL_EXTI_LINE_NONE, LL_EXTI_MODE_EVENT, LL_EXTI_MODE_IT, LL_EXTI_MODE_IT_EVENT, LL_EXTI_TRIGGER_FALLING, LL_EXTI_TRIGGER_NONE, LL_EXTI_TRIGGER_RISING, LL_EXTI_TRIGGER_RISING_FALLING, LL_EXTI_InitTypeDef::Mode, and LL_EXTI_InitTypeDef::Trigger.

void LL_EXTI_StructInit ( LL_EXTI_InitTypeDef * EXTI_InitStruct )

Set each LL_EXTI_InitTypeDef field to default value.

Parameters:
EXTI_InitStruct Pointer to a LL_EXTI_InitTypeDef structure.
Return values:
None

Definition at line 270 of file stm32wbxx_ll_exti.c.

References LL_EXTI_InitTypeDef::Line_0_31, LL_EXTI_InitTypeDef::Line_32_63, LL_EXTI_InitTypeDef::LineCommand, LL_EXTI_LINE_NONE, LL_EXTI_MODE_IT, LL_EXTI_TRIGGER_FALLING, LL_EXTI_InitTypeDef::Mode, and LL_EXTI_InitTypeDef::Trigger.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: GPIO

Modules
GPIO
STM32WBxx_LL_Driver

Modules

GPIO Private Macros

MISRA C:2012 deviation rule has been granted for following rules: Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..] which may be out of array bounds [..,UNKNOWN] in following APIs: LL_GPIO_GetAFPin_0_7 LL_GPIO_SetAFPin_0_7 LL_GPIO_SetAFPin_8_15 LL_GPIO_GetAFPin_8_15.

GPIO Exported Init structures
GPIO Exported Constants
GPIO Exported Macros
GPIO Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for GPIO registers.

Register | Bit | Function
AFRH | AFSELy | LL_GPIO_GetAFPin_8_15
 |  | LL_GPIO_SetAFPin_8_15
AFRL | AFSELy | LL_GPIO_GetAFPin_0_7
 |  | LL_GPIO_SetAFPin_0_7
BRR | BRy | LL_GPIO_ResetOutputPin
BSRR | BSy | LL_GPIO_SetOutputPin
IDR | IDy | LL_GPIO_IsInputPinSet
 |  | LL_GPIO_ReadInputPort
LCKR | LCKK | LL_GPIO_IsAnyPinLocked
 |  | LL_GPIO_LockPin
 | LCKy | LL_GPIO_IsPinLocked
MODER | MODEy | LL_GPIO_GetPinMode
 |  | LL_GPIO_SetPinMode
ODR | ODy | LL_GPIO_IsOutputPinSet
 |  | LL_GPIO_ReadOutputPort
 |  | LL_GPIO_TogglePin
 |  | LL_GPIO_WriteOutputPort
OSPEEDR | OSPEEDy | LL_GPIO_GetPinSpeed
 |  | LL_GPIO_SetPinSpeed
OTYPER | OTy | LL_GPIO_GetPinOutputType
 |  | LL_GPIO_SetPinOutputType
PUPDR | PUPDy | LL_GPIO_GetPinPull
 |  | LL_GPIO_SetPinPull
Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: GPIO Private Macros

Defines
GPIO Private Macros
GPIO

MISRA C:2012 deviation rule has been granted for following rules: Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..] which may be out of array bounds [..,UNKNOWN] in following APIs: LL_GPIO_GetAFPin_0_7 LL_GPIO_SetAFPin_0_7 LL_GPIO_SetAFPin_8_15 LL_GPIO_GetAFPin_8_15. More...

Defines

#define | IS_LL_GPIO_PIN(__VALUE__) (((0x00u) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
#define | IS_LL_GPIO_MODE(__VALUE__)
#define | IS_LL_GPIO_OUTPUT_TYPE(__VALUE__)
#define | IS_LL_GPIO_SPEED(__VALUE__)
#define | IS_LL_GPIO_PULL(__VALUE__)
#define | IS_LL_GPIO_ALTERNATE(__VALUE__)

Detailed Description

MISRA C:2012 deviation rule has been granted for following rules: Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..] which may be out of array bounds [..,UNKNOWN] in following APIs: LL_GPIO_GetAFPin_0_7 LL_GPIO_SetAFPin_0_7 LL_GPIO_SetAFPin_8_15 LL_GPIO_GetAFPin_8_15.

MISRA C:2012 deviation rule has been granted for following rules: Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of range of the shift operator in following API : LL_GPIO_Init.

Define Documentation

#define IS_LL_GPIO_ALTERNATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_GPIO_AF_0  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_1  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_2  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_3  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_4  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_5  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_6  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_7  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_8  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_9  )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_10 )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_11 )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_12 )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_13 )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_14 )   ||\
                                            ((__VALUE__) == LL_GPIO_AF_15 ))

Definition at line 71 of file stm32wbxx_ll_gpio.c.

Referenced by LL_GPIO_Init().

#define IS_LL_GPIO_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_GPIO_MODE_INPUT)     ||\
                                            ((__VALUE__) == LL_GPIO_MODE_OUTPUT)    ||\
                                            ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\
                                            ((__VALUE__) == LL_GPIO_MODE_ANALOG))

Definition at line 54 of file stm32wbxx_ll_gpio.c.

Referenced by LL_GPIO_Init().

#define IS_LL_GPIO_OUTPUT_TYPE ( __VALUE__ )
Value:
(((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL)  ||\
                                            ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))

Definition at line 59 of file stm32wbxx_ll_gpio.c.

Referenced by LL_GPIO_Init().

#define IS_LL_GPIO_PIN ( __VALUE__ ) (((0x00u) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))

Definition at line 52 of file stm32wbxx_ll_gpio.c.

Referenced by LL_GPIO_Init().

#define IS_LL_GPIO_PULL ( __VALUE__ )
Value:
(((__VALUE__) == LL_GPIO_PULL_NO)   ||\
                                            ((__VALUE__) == LL_GPIO_PULL_UP)   ||\
                                            ((__VALUE__) == LL_GPIO_PULL_DOWN))

Definition at line 67 of file stm32wbxx_ll_gpio.c.

Referenced by LL_GPIO_Init().

#define IS_LL_GPIO_SPEED ( __VALUE__ )
Value:
(((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW)       ||\
                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM)    ||\
                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH)      ||\
                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH))

Definition at line 62 of file stm32wbxx_ll_gpio.c.

Referenced by LL_GPIO_Init().

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LL_GPIO_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_GPIO_InitTypeDef Struct Reference
GPIO Exported Init structures

LL GPIO Init Structure definition. More...

#include <stm32wbxx_ll_gpio.h>

Data Fields

uint32_t | Pin
uint32_t | Mode
uint32_t | Speed
uint32_t | OutputType
uint32_t | Pull
uint32_t | Alternate

Detailed Description

LL GPIO Init Structure definition.

Definition at line 72 of file stm32wbxx_ll_gpio.h.

Field Documentation

uint32_t LL_GPIO_InitTypeDef::Alternate

Specifies the Peripheral to be connected to the selected pins. This parameter can be a value of Alternate Function.

GPIO HW configuration can be modified afterwards using unitary function LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().

Definition at line 97 of file stm32wbxx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

uint32_t LL_GPIO_InitTypeDef::Mode

Specifies the operating mode for the selected pins. This parameter can be a value of Mode.

GPIO HW configuration can be modified afterwards using unitary function LL_GPIO_SetPinMode().

Definition at line 77 of file stm32wbxx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

uint32_t LL_GPIO_InitTypeDef::OutputType

Specifies the operating output type for the selected pins. This parameter can be a value of Output Type.

GPIO HW configuration can be modified afterwards using unitary function LL_GPIO_SetPinOutputType().

Definition at line 87 of file stm32wbxx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

uint32_t LL_GPIO_InitTypeDef::Pin

Specifies the GPIO pins to be configured. This parameter can be any value of PIN

Definition at line 74 of file stm32wbxx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

uint32_t LL_GPIO_InitTypeDef::Pull

Specifies the operating Pull-up/Pull down for the selected pins. This parameter can be a value of Pull Up Pull Down.

GPIO HW configuration can be modified afterwards using unitary function LL_GPIO_SetPinPull().

Definition at line 92 of file stm32wbxx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

uint32_t LL_GPIO_InitTypeDef::Speed

Specifies the speed for the selected pins. This parameter can be a value of Output Speed.

GPIO HW configuration can be modified afterwards using unitary function LL_GPIO_SetPinSpeed().

Definition at line 82 of file stm32wbxx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

The documentation for this struct was generated from the following file:
  • stm32wbxx_ll_gpio.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PIN

Defines
PIN
GPIO Exported Constants

Defines

#define | LL_GPIO_PIN_0 GPIO_BSRR_BS0
#define | LL_GPIO_PIN_1 GPIO_BSRR_BS1
#define | LL_GPIO_PIN_2 GPIO_BSRR_BS2
#define | LL_GPIO_PIN_3 GPIO_BSRR_BS3
#define | LL_GPIO_PIN_4 GPIO_BSRR_BS4
#define | LL_GPIO_PIN_5 GPIO_BSRR_BS5
#define | LL_GPIO_PIN_6 GPIO_BSRR_BS6
#define | LL_GPIO_PIN_7 GPIO_BSRR_BS7
#define | LL_GPIO_PIN_8 GPIO_BSRR_BS8
#define | LL_GPIO_PIN_9 GPIO_BSRR_BS9
#define | LL_GPIO_PIN_10 GPIO_BSRR_BS10
#define | LL_GPIO_PIN_11 GPIO_BSRR_BS11
#define | LL_GPIO_PIN_12 GPIO_BSRR_BS12
#define | LL_GPIO_PIN_13 GPIO_BSRR_BS13
#define | LL_GPIO_PIN_14 GPIO_BSRR_BS14
#define | LL_GPIO_PIN_15 GPIO_BSRR_BS15
#define | LL_GPIO_PIN_ALL

Define Documentation

#define LL_GPIO_PIN_0 GPIO_BSRR_BS0

Select pin 0

Definition at line 116 of file stm32wbxx_ll_gpio.h.

#define LL_GPIO_PIN_1 GPIO_BSRR_BS1

Select pin 1

Definition at line 117 of file stm32wbxx_ll_gpio.h.

#define LL_GPIO_PIN_10 GPIO_BSRR_BS10

Select pin 10

Definition at line 126 of file stm32wbxx_ll_gpio.h.

#define LL_GPIO_PIN_11 GPIO_BSRR_BS11

Select pin 11

Definition at line 127 of file stm32wbxx_ll_gpio.h.

#define LL_GPIO_PIN_12 GPIO_BSRR_BS12

Select pin 12

Definition at line 128 of file stm32wbxx_ll_gpio.h.

#define LL_GPIO_PIN_13 GPIO_BSRR_BS13

Select pin 13

Definition at line 129 of file stm32wbxx_ll_gpio.h.

#define LL_GPIO_PIN_14 GPIO_BSRR_BS14

Select pin 14

Definition at line 130 of file stm32wbxx_ll_gpio.h.

#define LL_GPIO_PIN_15 GPIO_BSRR_BS15

Select pin 15

Definition at line 131 of file stm32wbxx_ll_gpio.h.

#define LL_GPIO_PIN_2 GPIO_BSRR_BS2

Select pin 2

Definition at line 118 of file stm32wbxx_ll_gpio.h.

#define LL_GPIO_PIN_3 GPIO_BSRR_BS3

Select pin 3

Definition at line 119 of file stm32wbxx_ll_gpio.h.

#define LL_GPIO_PIN_4 GPIO_BSRR_BS4

Select pin 4

Definition at line 120 of file stm32wbxx_ll_gpio.h.

#define LL_GPIO_PIN_5 GPIO_BSRR_BS5

Select pin 5

Definition at line 121 of file stm32wbxx_ll_gpio.h.

#define LL_GPIO_PIN_6 GPIO_BSRR_BS6

Select pin 6

Definition at line 122 of file stm32wbxx_ll_gpio.h.

#define LL_GPIO_PIN_7 GPIO_BSRR_BS7

Select pin 7

Definition at line 123 of file stm32wbxx_ll_gpio.h.

#define LL_GPIO_PIN_8 GPIO_BSRR_BS8

Select pin 8

Definition at line 124 of file stm32wbxx_ll_gpio.h.

#define LL_GPIO_PIN_9 GPIO_BSRR_BS9

Select pin 9

Definition at line 125 of file stm32wbxx_ll_gpio.h.

#define LL_GPIO_PIN_ALL
Value:
(GPIO_BSRR_BS0 | GPIO_BSRR_BS1  | GPIO_BSRR_BS2  | \
                                           GPIO_BSRR_BS3  | GPIO_BSRR_BS4  | GPIO_BSRR_BS5  | \
                                           GPIO_BSRR_BS6  | GPIO_BSRR_BS7  | GPIO_BSRR_BS8  | \
                                           GPIO_BSRR_BS9  | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \
                                           GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \
                                           GPIO_BSRR_BS15)

Select all pins

Definition at line 132 of file stm32wbxx_ll_gpio.h.

Referenced by LL_GPIO_StructInit().

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Mode

Defines
Mode
GPIO Exported Constants

Defines

#define | LL_GPIO_MODE_INPUT (0x00000000U)
#define | LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0
#define | LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1
#define | LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0

Define Documentation

#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1

Select alternate function mode

Definition at line 147 of file stm32wbxx_ll_gpio.h.

Referenced by LL_GPIO_Init().

#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0

Select analog mode

Definition at line 148 of file stm32wbxx_ll_gpio.h.

Referenced by LL_GPIO_StructInit().

#define LL_GPIO_MODE_INPUT (0x00000000U)

Select input mode

Definition at line 145 of file stm32wbxx_ll_gpio.h.

#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0

Select output mode

Definition at line 146 of file stm32wbxx_ll_gpio.h.

Referenced by LL_GPIO_Init().

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Output Type

Defines
Output Type
GPIO Exported Constants

Defines

#define | LL_GPIO_OUTPUT_PUSHPULL (0x00000000U)
#define | LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT0

Define Documentation

#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT0

Select open-drain as output type

Definition at line 157 of file stm32wbxx_ll_gpio.h.

#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U)

Select push-pull as output type

Definition at line 156 of file stm32wbxx_ll_gpio.h.

Referenced by LL_GPIO_StructInit().

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Output Speed

Defines
Output Speed
GPIO Exported Constants

Defines

#define | LL_GPIO_SPEED_FREQ_LOW (0x00000000U)
#define | LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEED0_0
#define | LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEED0_1
#define | LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDR_OSPEED0

Define Documentation

#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEED0_1

Select I/O fast output speed

Definition at line 167 of file stm32wbxx_ll_gpio.h.

#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U)

Select I/O low output speed

Definition at line 165 of file stm32wbxx_ll_gpio.h.

Referenced by LL_GPIO_StructInit().

#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEED0_0

Select I/O medium output speed

Definition at line 166 of file stm32wbxx_ll_gpio.h.

#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDR_OSPEED0

Select I/O high output speed

Definition at line 168 of file stm32wbxx_ll_gpio.h.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Pull Up Pull Down

Defines
Pull Up Pull Down
GPIO Exported Constants

Defines

#define | LL_GPIO_PULL_NO (0x00000000U)
#define | LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0
#define | LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1

Define Documentation

#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1

Select I/O pull down

Definition at line 178 of file stm32wbxx_ll_gpio.h.

#define LL_GPIO_PULL_NO (0x00000000U)

Select I/O no pull

Definition at line 176 of file stm32wbxx_ll_gpio.h.

Referenced by LL_GPIO_StructInit().

#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0

Select I/O pull up

Definition at line 177 of file stm32wbxx_ll_gpio.h.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Alternate Function

Defines
Alternate Function
GPIO Exported Constants

Defines

#define | LL_GPIO_AF_0 (0x0000000U)
#define | LL_GPIO_AF_1 (0x0000001U)
#define | LL_GPIO_AF_2 (0x0000002U)
#define | LL_GPIO_AF_3 (0x0000003U)
#define | LL_GPIO_AF_4 (0x0000004U)
#define | LL_GPIO_AF_5 (0x0000005U)
#define | LL_GPIO_AF_6 (0x0000006U)
#define | LL_GPIO_AF_7 (0x0000007U)
#define | LL_GPIO_AF_8 (0x0000008U)
#define | LL_GPIO_AF_9 (0x0000009U)
#define | LL_GPIO_AF_10 (0x000000AU)
#define | LL_GPIO_AF_11 (0x000000BU)
#define | LL_GPIO_AF_12 (0x000000CU)
#define | LL_GPIO_AF_13 (0x000000DU)
#define | LL_GPIO_AF_14 (0x000000EU)
#define | LL_GPIO_AF_15 (0x000000FU)

Define Documentation

#define LL_GPIO_AF_0 (0x0000000U)

Select alternate function 0

Definition at line 186 of file stm32wbxx_ll_gpio.h.

Referenced by LL_GPIO_StructInit().

#define LL_GPIO_AF_1 (0x0000001U)

Select alternate function 1

Definition at line 187 of file stm32wbxx_ll_gpio.h.

#define LL_GPIO_AF_10 (0x000000AU)

Select alternate function 10

Definition at line 196 of file stm32wbxx_ll_gpio.h.

#define LL_GPIO_AF_11 (0x000000BU)

Select alternate function 11

Definition at line 197 of file stm32wbxx_ll_gpio.h.

#define LL_GPIO_AF_12 (0x000000CU)

Select alternate function 12

Definition at line 198 of file stm32wbxx_ll_gpio.h.

#define LL_GPIO_AF_13 (0x000000DU)

Select alternate function 13

Definition at line 199 of file stm32wbxx_ll_gpio.h.

#define LL_GPIO_AF_14 (0x000000EU)

Select alternate function 14

Definition at line 200 of file stm32wbxx_ll_gpio.h.

#define LL_GPIO_AF_15 (0x000000FU)

Select alternate function 15

Definition at line 201 of file stm32wbxx_ll_gpio.h.

#define LL_GPIO_AF_2 (0x0000002U)

Select alternate function 2

Definition at line 188 of file stm32wbxx_ll_gpio.h.

#define LL_GPIO_AF_3 (0x0000003U)

Select alternate function 3

Definition at line 189 of file stm32wbxx_ll_gpio.h.

#define LL_GPIO_AF_4 (0x0000004U)

Select alternate function 4

Definition at line 190 of file stm32wbxx_ll_gpio.h.

#define LL_GPIO_AF_5 (0x0000005U)

Select alternate function 5

Definition at line 191 of file stm32wbxx_ll_gpio.h.

#define LL_GPIO_AF_6 (0x0000006U)

Select alternate function 6

Definition at line 192 of file stm32wbxx_ll_gpio.h.

#define LL_GPIO_AF_7 (0x0000007U)

Select alternate function 7

Definition at line 193 of file stm32wbxx_ll_gpio.h.

#define LL_GPIO_AF_8 (0x0000008U)

Select alternate function 8

Definition at line 194 of file stm32wbxx_ll_gpio.h.

#define LL_GPIO_AF_9 (0x0000009U)

Select alternate function 9

Definition at line 195 of file stm32wbxx_ll_gpio.h.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
GPIO Exported Macros

Defines

#define | LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in GPIO register.
#define | LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in GPIO register.

Define Documentation

#define LL_GPIO_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in GPIO register.

Parameters:
__INSTANCE__ | GPIO Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 234 of file stm32wbxx_ll_gpio.h.

#define LL_GPIO_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in GPIO register.

Parameters:
__INSTANCE__ | GPIO Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 226 of file stm32wbxx_ll_gpio.h.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Port Configuration

Functions
Port Configuration
GPIO Exported Functions

Functions

__STATIC_INLINE void | LL_GPIO_SetPinMode (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
Configure gpio mode for a dedicated pin on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinMode (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio mode for a dedicated pin on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinOutputType (GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
Configure gpio output type for several pins on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinOutputType (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio output type for several pins on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinSpeed (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
Configure gpio speed for a dedicated pin on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinSpeed (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio speed for a dedicated pin on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinPull (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinPull (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio pull-up or pull-down for a dedicated pin on a dedicated port.
__STATIC_INLINE void | LL_GPIO_SetAFPin_0_7 (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetAFPin_0_7 (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
__STATIC_INLINE void | LL_GPIO_SetAFPin_8_15 (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetAFPin_8_15 (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
__STATIC_INLINE void | LL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Lock configuration of several pins for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsPinLocked (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return 1 if all pins passed as parameter, of a dedicated port, are locked.
__STATIC_INLINE uint32_t | LL_GPIO_IsAnyPinLocked (GPIO_TypeDef *GPIOx)
Return 1 if one of the pin of a dedicated port is locked.

Function Documentation

__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7 | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.

Reference Manual to LL API cross reference:
AFRL AFSELy LL_GPIO_GetAFPin_0_7
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
Return values:
Returned value can be one of the following values:
  • LL_GPIO_AF_0
  • LL_GPIO_AF_1
  • LL_GPIO_AF_2
  • LL_GPIO_AF_3
  • LL_GPIO_AF_4
  • LL_GPIO_AF_5
  • LL_GPIO_AF_6
  • LL_GPIO_AF_7
  • LL_GPIO_AF_8
  • LL_GPIO_AF_9
  • LL_GPIO_AF_10
  • LL_GPIO_AF_11
  • LL_GPIO_AF_12
  • LL_GPIO_AF_13
  • LL_GPIO_AF_14
  • LL_GPIO_AF_15

Definition at line 602 of file stm32wbxx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15 | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.

Note:
Possible values are from AF0 to AF15 depending on target.
Reference Manual to LL API cross reference:
AFRH AFSELy LL_GPIO_GetAFPin_8_15
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Return values:
Returned value can be one of the following values:
  • LL_GPIO_AF_0
  • LL_GPIO_AF_1
  • LL_GPIO_AF_2
  • LL_GPIO_AF_3
  • LL_GPIO_AF_4
  • LL_GPIO_AF_5
  • LL_GPIO_AF_6
  • LL_GPIO_AF_7
  • LL_GPIO_AF_8
  • LL_GPIO_AF_9
  • LL_GPIO_AF_10
  • LL_GPIO_AF_11
  • LL_GPIO_AF_12
  • LL_GPIO_AF_13
  • LL_GPIO_AF_14
  • LL_GPIO_AF_15

Definition at line 680 of file stm32wbxx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_GetPinMode | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio mode for a dedicated pin on dedicated port.

Note:
I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
MODER MODEy LL_GPIO_GetPinMode
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Return values:
Returned value can be one of the following values:
  • LL_GPIO_MODE_INPUT
  • LL_GPIO_MODE_OUTPUT
  • LL_GPIO_MODE_ALTERNATE
  • LL_GPIO_MODE_ANALOG

Definition at line 316 of file stm32wbxx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio output type for several pins on dedicated port.

Note:
Output type as to be set when gpio pin is in output or alternate modes. Possible type are Push-pull or Open-drain.
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
OTYPER OTy LL_GPIO_GetPinOutputType
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
Returned value can be one of the following values:
  • LL_GPIO_OUTPUT_PUSHPULL
  • LL_GPIO_OUTPUT_OPENDRAIN

Definition at line 385 of file stm32wbxx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_GetPinPull | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio pull-up or pull-down for a dedicated pin on a dedicated port.

Note:
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
PUPDR PUPDy LL_GPIO_GetPinPull
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Return values:
Returned value can be one of the following values:
  • LL_GPIO_PULL_NO
  • LL_GPIO_PULL_UP
  • LL_GPIO_PULL_DOWN

Definition at line 525 of file stm32wbxx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio speed for a dedicated pin on dedicated port.

Note:
I/O speed can be Low, Medium, Fast or High speed.
Warning: only one pin can be passed as parameter.
Refer to datasheet for frequency specifications and the power supply and load conditions for each speed.
Reference Manual to LL API cross reference:
OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Return values:
Returned value can be one of the following values:
  • LL_GPIO_SPEED_FREQ_LOW
  • LL_GPIO_SPEED_FREQ_MEDIUM
  • LL_GPIO_SPEED_FREQ_HIGH
  • LL_GPIO_SPEED_FREQ_VERY_HIGH

Definition at line 459 of file stm32wbxx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked ( GPIO_TypeDef * GPIOx )

Return 1 if one of the pin of a dedicated port is locked.

else return 0.

Reference Manual to LL API cross reference:
LCKR LCKK LL_GPIO_IsAnyPinLocked
Parameters:
GPIOx GPIO Port
Return values:
State of bit (1 or 0).

Definition at line 762 of file stm32wbxx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Return 1 if all pins passed as parameter, of a dedicated port, are locked.

else Return 0.

Reference Manual to LL API cross reference:
LCKR LCKy LL_GPIO_IsPinLocked
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
State of bit (1 or 0).

Definition at line 751 of file stm32wbxx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_LockPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Lock configuration of several pins for a dedicated port.

Note:
When the lock sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next reset.
Each lock bit freezes a specific configuration register (control and alternate function registers).
Reference Manual to LL API cross reference:
LCKR LCKK LL_GPIO_LockPin
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
None

Definition at line 716 of file stm32wbxx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_SetAFPin_0_7 | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin,
 |  | uint32_t | Alternate
 | ) |  |

Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.

Note:
Possible values are from AF0 to AF15 depending on target.
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
AFRL AFSELy LL_GPIO_SetAFPin_0_7
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
Alternate This parameter can be one of the following values:
  • LL_GPIO_AF_0
  • LL_GPIO_AF_1
  • LL_GPIO_AF_2
  • LL_GPIO_AF_3
  • LL_GPIO_AF_4
  • LL_GPIO_AF_5
  • LL_GPIO_AF_6
  • LL_GPIO_AF_7
  • LL_GPIO_AF_8
  • LL_GPIO_AF_9
  • LL_GPIO_AF_10
  • LL_GPIO_AF_11
  • LL_GPIO_AF_12
  • LL_GPIO_AF_13
  • LL_GPIO_AF_14
  • LL_GPIO_AF_15
Return values:
None

Definition at line 565 of file stm32wbxx_ll_gpio.h.

Referenced by LL_GPIO_Init().

__STATIC_INLINE void LL_GPIO_SetAFPin_8_15 | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin,
 |  | uint32_t | Alternate
 | ) |  |

Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.

Note:
Possible values are from AF0 to AF15 depending on target.
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
AFRH AFSELy LL_GPIO_SetAFPin_8_15
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Alternate This parameter can be one of the following values:
  • LL_GPIO_AF_0
  • LL_GPIO_AF_1
  • LL_GPIO_AF_2
  • LL_GPIO_AF_3
  • LL_GPIO_AF_4
  • LL_GPIO_AF_5
  • LL_GPIO_AF_6
  • LL_GPIO_AF_7
  • LL_GPIO_AF_8
  • LL_GPIO_AF_9
  • LL_GPIO_AF_10
  • LL_GPIO_AF_11
  • LL_GPIO_AF_12
  • LL_GPIO_AF_13
  • LL_GPIO_AF_14
  • LL_GPIO_AF_15
Return values:
None

Definition at line 642 of file stm32wbxx_ll_gpio.h.

Referenced by LL_GPIO_Init().

__STATIC_INLINE void LL_GPIO_SetPinMode | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin,
 |  | uint32_t | Mode
 | ) |  |

Configure gpio mode for a dedicated pin on dedicated port.

Note:
I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
MODER MODEy LL_GPIO_SetPinMode
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Mode This parameter can be one of the following values:
  • LL_GPIO_MODE_INPUT
  • LL_GPIO_MODE_OUTPUT
  • LL_GPIO_MODE_ALTERNATE
  • LL_GPIO_MODE_ANALOG
Return values:
None

Definition at line 282 of file stm32wbxx_ll_gpio.h.

Referenced by LL_GPIO_Init().

__STATIC_INLINE void LL_GPIO_SetPinOutputType | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask,
 |  | uint32_t | OutputType
 | ) |  |

Configure gpio output type for several pins on dedicated port.

Note:
Output type as to be set when gpio pin is in output or alternate modes. Possible type are Push-pull or Open-drain.
Reference Manual to LL API cross reference:
OTYPER OTy LL_GPIO_SetPinOutputType
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
OutputType This parameter can be one of the following values:
  • LL_GPIO_OUTPUT_PUSHPULL
  • LL_GPIO_OUTPUT_OPENDRAIN
Return values:
None

Definition at line 351 of file stm32wbxx_ll_gpio.h.

Referenced by LL_GPIO_Init().

__STATIC_INLINE void LL_GPIO_SetPinPull | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin,
 |  | uint32_t | Pull
 | ) |  |

Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.

Note:
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
PUPDR PUPDy LL_GPIO_SetPinPull
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Pull This parameter can be one of the following values:
  • LL_GPIO_PULL_NO
  • LL_GPIO_PULL_UP
  • LL_GPIO_PULL_DOWN
Return values:
None

Definition at line 493 of file stm32wbxx_ll_gpio.h.

Referenced by LL_GPIO_Init().

__STATIC_INLINE void LL_GPIO_SetPinSpeed | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin,
 |  | uint32_t | Speed
 | ) |  |

Configure gpio speed for a dedicated pin on dedicated port.

Note:
I/O speed can be Low, Medium, Fast or High speed.
Warning: only one pin can be passed as parameter.
Refer to datasheet for frequency specifications and the power supply and load conditions for each speed.
Reference Manual to LL API cross reference:
OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Speed This parameter can be one of the following values:
  • LL_GPIO_SPEED_FREQ_LOW
  • LL_GPIO_SPEED_FREQ_MEDIUM
  • LL_GPIO_SPEED_FREQ_HIGH
  • LL_GPIO_SPEED_FREQ_VERY_HIGH
Return values:
None

Definition at line 422 of file stm32wbxx_ll_gpio.h.

Referenced by LL_GPIO_Init().

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Access

Functions
Data Access
GPIO Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_GPIO_ReadInputPort (GPIO_TypeDef *GPIOx)
Return full input data register value for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsInputPinSet (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return if input data level for several pins of dedicated port is high or low.
__STATIC_INLINE void | LL_GPIO_WriteOutputPort (GPIO_TypeDef *GPIOx, uint32_t PortValue)
Write output data register for the port.
__STATIC_INLINE uint32_t | LL_GPIO_ReadOutputPort (GPIO_TypeDef *GPIOx)
Return full output data register value for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsOutputPinSet (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return if input data level for several pins of dedicated port is high or low.
__STATIC_INLINE void | LL_GPIO_SetOutputPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Set several pins to high level on dedicated gpio port.
__STATIC_INLINE void | LL_GPIO_ResetOutputPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Set several pins to low level on dedicated gpio port.
__STATIC_INLINE void | LL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Toggle data value for several pin of dedicated port.

Function Documentation

__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Return if input data level for several pins of dedicated port is high or low.

Reference Manual to LL API cross reference:
IDR IDy LL_GPIO_IsInputPinSet
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
State of bit (1 or 0).

Definition at line 810 of file stm32wbxx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Return if input data level for several pins of dedicated port is high or low.

Reference Manual to LL API cross reference:
ODR ODy LL_GPIO_IsOutputPinSet
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
State of bit (1 or 0).

Definition at line 862 of file stm32wbxx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort ( GPIO_TypeDef * GPIOx )

Return full input data register value for a dedicated port.

Reference Manual to LL API cross reference:
IDR IDy LL_GPIO_ReadInputPort
Parameters:
GPIOx GPIO Port
Return values:
Input data register value of port

Definition at line 781 of file stm32wbxx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort ( GPIO_TypeDef * GPIOx )

Return full output data register value for a dedicated port.

Reference Manual to LL API cross reference:
ODR ODy LL_GPIO_ReadOutputPort
Parameters:
GPIOx GPIO Port
Return values:
Output data register value of port

Definition at line 833 of file stm32wbxx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_ResetOutputPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Set several pins to low level on dedicated gpio port.

Reference Manual to LL API cross reference:
BRR BRy LL_GPIO_ResetOutputPin
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
None

Definition at line 920 of file stm32wbxx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_SetOutputPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Set several pins to high level on dedicated gpio port.

Reference Manual to LL API cross reference:
BSRR BSy LL_GPIO_SetOutputPin
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
None

Definition at line 891 of file stm32wbxx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_TogglePin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Toggle data value for several pin of dedicated port.

Reference Manual to LL API cross reference:
ODR ODy LL_GPIO_TogglePin
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
None

Definition at line 949 of file stm32wbxx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_WriteOutputPort | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PortValue
 | ) |  |

Write output data register for the port.

Reference Manual to LL API cross reference:
ODR ODy LL_GPIO_WriteOutputPort
Parameters:
GPIOx | GPIO Port
PortValue | Level value for each pin of the port
Return values:
None

Definition at line 822 of file stm32wbxx_ll_gpio.h.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
GPIO Exported Functions

Functions

ErrorStatus | LL_GPIO_DeInit (GPIO_TypeDef *GPIOx)
De-initialize GPIO registers (Registers restored to their default values).
ErrorStatus | LL_GPIO_Init (GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
void | LL_GPIO_StructInit (LL_GPIO_InitTypeDef *GPIO_InitStruct)
Set each LL_GPIO_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_GPIO_DeInit ( GPIO_TypeDef * GPIOx )

De-initialize GPIO registers (Registers restored to their default values).

Parameters:
GPIOx GPIO Port
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: GPIO registers are de-initialized
  • ERROR: Wrong GPIO Port

Definition at line 109 of file stm32wbxx_ll_gpio.c.

References assert_param, LL_AHB2_GRP1_ForceReset(), LL_AHB2_GRP1_PERIPH_GPIOA, LL_AHB2_GRP1_PERIPH_GPIOB, LL_AHB2_GRP1_PERIPH_GPIOC, LL_AHB2_GRP1_PERIPH_GPIOD, LL_AHB2_GRP1_PERIPH_GPIOE, LL_AHB2_GRP1_PERIPH_GPIOH, and LL_AHB2_GRP1_ReleaseReset().

ErrorStatus LL_GPIO_Init | ( | GPIO_TypeDef * | GPIOx,
 |  | LL_GPIO_InitTypeDef * | GPIO_InitStruct
 | ) |  |

Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.

Parameters:
GPIOx | GPIO Port
GPIO_InitStruct | pointer to a LL_GPIO_InitTypeDef structure that contains the configuration information for the specified GPIO peripheral.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
  • ERROR: Not applicable

Definition at line 170 of file stm32wbxx_ll_gpio.c.

References LL_GPIO_InitTypeDef::Alternate, assert_param, IS_LL_GPIO_ALTERNATE, IS_LL_GPIO_MODE, IS_LL_GPIO_OUTPUT_TYPE, IS_LL_GPIO_PIN, IS_LL_GPIO_PULL, IS_LL_GPIO_SPEED, LL_GPIO_MODE_ALTERNATE, LL_GPIO_MODE_OUTPUT, LL_GPIO_SetAFPin_0_7(), LL_GPIO_SetAFPin_8_15(), LL_GPIO_SetPinMode(), LL_GPIO_SetPinOutputType(), LL_GPIO_SetPinPull(), LL_GPIO_SetPinSpeed(), LL_GPIO_InitTypeDef::Mode, LL_GPIO_InitTypeDef::OutputType, LL_GPIO_InitTypeDef::Pin, LL_GPIO_InitTypeDef::Pull, and LL_GPIO_InitTypeDef::Speed.

void LL_GPIO_StructInit ( LL_GPIO_InitTypeDef * GPIO_InitStruct )

Set each LL_GPIO_InitTypeDef field to default value.

Parameters:
GPIO_InitStruct pointer to a LL_GPIO_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 246 of file stm32wbxx_ll_gpio.c.

References LL_GPIO_InitTypeDef::Alternate, LL_GPIO_AF_0, LL_GPIO_MODE_ANALOG, LL_GPIO_OUTPUT_PUSHPULL, LL_GPIO_PIN_ALL, LL_GPIO_PULL_NO, LL_GPIO_SPEED_FREQ_LOW, LL_GPIO_InitTypeDef::Mode, LL_GPIO_InitTypeDef::OutputType, LL_GPIO_InitTypeDef::Pin, LL_GPIO_InitTypeDef::Pull, and LL_GPIO_InitTypeDef::Speed.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: HSEM

Modules
HSEM
STM32WBxx_LL_Driver

Modules

HSEM Exported Constants
HSEM Exported Macros
HSEM Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for HSEM registers.

Register | Bit | Function
C1ICR | ISEM | LL_HSEM_ClearFlag_C1ICR
C1IER | ISEM | LL_HSEM_DisableIT_C1IER
 |  | LL_HSEM_EnableIT_C1IER
 |  | LL_HSEM_IsEnabledIT_C1IER
C1ISR | ISEM | LL_HSEM_IsActiveFlag_C1ISR
C1MISR | ISEM | LL_HSEM_IsActiveFlag_C1MISR
C2ICR | ISEM | LL_HSEM_ClearFlag_C2ICR
C2IER | ISEM | LL_HSEM_DisableIT_C2IER
 |  | LL_HSEM_EnableIT_C2IER
 |  | LL_HSEM_IsEnabledIT_C2IER
C2ISR | ISEM | LL_HSEM_IsActiveFlag_C2ISR
C2MISR | ISEM | LL_HSEM_IsActiveFlag_C2MISR
CR | KEY | LL_HSEM_ResetAllLock
KEYR | KEY | LL_HSEM_GetKey
 |  | LL_HSEM_SetKey
R | COREID | LL_HSEM_2StepLock
 |  | LL_HSEM_GetCoreId
 |  | LL_HSEM_SetLock
 | LOCK | LL_HSEM_2StepLock
 |  | LL_HSEM_GetStatus
 |  | LL_HSEM_IsSemaphoreLocked
 |  | LL_HSEM_ReleaseLock
 |  | LL_HSEM_SetLock
 | PROCID | LL_HSEM_2StepLock
 |  | LL_HSEM_GetProcessId
 |  | LL_HSEM_SetLock
RLR | COREID | LL_HSEM_1StepLock
 | LOCK | LL_HSEM_1StepLock
 | PROCID | LL_HSEM_1StepLock
Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: COREID Defines

Defines
COREID Defines
HSEM Exported Constants

Defines

#define | LL_HSEM_COREID_NONE 0U
#define | LL_HSEM_COREID_CPU1 HSEM_CR_COREID_CPU1
#define | LL_HSEM_COREID_CPU2 HSEM_CR_COREID_CPU2
#define | LL_HSEM_COREID HSEM_CR_COREID_CURRENT

Define Documentation

#define LL_HSEM_COREID HSEM_CR_COREID_CURRENT

Definition at line 59 of file stm32wbxx_ll_hsem.h.

Referenced by LL_HSEM_1StepLock(), LL_HSEM_2StepLock(), LL_HSEM_ReleaseLock(), and LL_HSEM_SetLock().

#define LL_HSEM_COREID_CPU1 HSEM_CR_COREID_CPU1

Definition at line 57 of file stm32wbxx_ll_hsem.h.

#define LL_HSEM_COREID_CPU2 HSEM_CR_COREID_CPU2

Definition at line 58 of file stm32wbxx_ll_hsem.h.

#define LL_HSEM_COREID_NONE 0U

Definition at line 56 of file stm32wbxx_ll_hsem.h.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
HSEM Exported Constants

Flags defines which can be used with LL_HSEM_ReadReg function. More...

Defines

#define | LL_HSEM_SEMAPHORE_0 HSEM_C1IER_ISE0
#define | LL_HSEM_SEMAPHORE_1 HSEM_C1IER_ISE1
#define | LL_HSEM_SEMAPHORE_2 HSEM_C1IER_ISE2
#define | LL_HSEM_SEMAPHORE_3 HSEM_C1IER_ISE3
#define | LL_HSEM_SEMAPHORE_4 HSEM_C1IER_ISE4
#define | LL_HSEM_SEMAPHORE_5 HSEM_C1IER_ISE5
#define | LL_HSEM_SEMAPHORE_6 HSEM_C1IER_ISE6
#define | LL_HSEM_SEMAPHORE_7 HSEM_C1IER_ISE7
#define | LL_HSEM_SEMAPHORE_8 HSEM_C1IER_ISE8
#define | LL_HSEM_SEMAPHORE_9 HSEM_C1IER_ISE9
#define | LL_HSEM_SEMAPHORE_10 HSEM_C1IER_ISE10
#define | LL_HSEM_SEMAPHORE_11 HSEM_C1IER_ISE11
#define | LL_HSEM_SEMAPHORE_12 HSEM_C1IER_ISE12
#define | LL_HSEM_SEMAPHORE_13 HSEM_C1IER_ISE13
#define | LL_HSEM_SEMAPHORE_14 HSEM_C1IER_ISE14
#define | LL_HSEM_SEMAPHORE_15 HSEM_C1IER_ISE15
#define | LL_HSEM_SEMAPHORE_16 HSEM_C1IER_ISE16
#define | LL_HSEM_SEMAPHORE_17 HSEM_C1IER_ISE17
#define | LL_HSEM_SEMAPHORE_18 HSEM_C1IER_ISE18
#define | LL_HSEM_SEMAPHORE_19 HSEM_C1IER_ISE19
#define | LL_HSEM_SEMAPHORE_20 HSEM_C1IER_ISE20
#define | LL_HSEM_SEMAPHORE_21 HSEM_C1IER_ISE21
#define | LL_HSEM_SEMAPHORE_22 HSEM_C1IER_ISE22
#define | LL_HSEM_SEMAPHORE_23 HSEM_C1IER_ISE23
#define | LL_HSEM_SEMAPHORE_24 HSEM_C1IER_ISE24
#define | LL_HSEM_SEMAPHORE_25 HSEM_C1IER_ISE25
#define | LL_HSEM_SEMAPHORE_26 HSEM_C1IER_ISE26
#define | LL_HSEM_SEMAPHORE_27 HSEM_C1IER_ISE27
#define | LL_HSEM_SEMAPHORE_28 HSEM_C1IER_ISE28
#define | LL_HSEM_SEMAPHORE_29 HSEM_C1IER_ISE29
#define | LL_HSEM_SEMAPHORE_30 HSEM_C1IER_ISE30
#define | LL_HSEM_SEMAPHORE_31 HSEM_C1IER_ISE31
#define | LL_HSEM_SEMAPHORE_ALL 0xFFFFFFFFU

Detailed Description

Flags defines which can be used with LL_HSEM_ReadReg function.

Define Documentation

#define LL_HSEM_SEMAPHORE_0 HSEM_C1IER_ISE0

Definition at line 69 of file stm32wbxx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_1 HSEM_C1IER_ISE1

Definition at line 70 of file stm32wbxx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_10 HSEM_C1IER_ISE10

Definition at line 79 of file stm32wbxx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_11 HSEM_C1IER_ISE11

Definition at line 80 of file stm32wbxx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_12 HSEM_C1IER_ISE12

Definition at line 81 of file stm32wbxx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_13 HSEM_C1IER_ISE13

Definition at line 82 of file stm32wbxx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_14 HSEM_C1IER_ISE14

Definition at line 83 of file stm32wbxx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_15 HSEM_C1IER_ISE15

Definition at line 84 of file stm32wbxx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_16 HSEM_C1IER_ISE16

Definition at line 85 of file stm32wbxx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_17 HSEM_C1IER_ISE17

Definition at line 86 of file stm32wbxx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_18 HSEM_C1IER_ISE18

Definition at line 87 of file stm32wbxx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_19 HSEM_C1IER_ISE19

Definition at line 88 of file stm32wbxx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_2 HSEM_C1IER_ISE2

Definition at line 71 of file stm32wbxx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_20 HSEM_C1IER_ISE20

Definition at line 89 of file stm32wbxx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_21 HSEM_C1IER_ISE21

Definition at line 90 of file stm32wbxx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_22 HSEM_C1IER_ISE22

Definition at line 91 of file stm32wbxx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_23 HSEM_C1IER_ISE23

Definition at line 92 of file stm32wbxx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_24 HSEM_C1IER_ISE24

Definition at line 93 of file stm32wbxx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_25 HSEM_C1IER_ISE25

Definition at line 94 of file stm32wbxx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_26 HSEM_C1IER_ISE26

Definition at line 95 of file stm32wbxx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_27 HSEM_C1IER_ISE27

Definition at line 96 of file stm32wbxx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_28 HSEM_C1IER_ISE28

Definition at line 97 of file stm32wbxx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_29 HSEM_C1IER_ISE29

Definition at line 98 of file stm32wbxx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_3 HSEM_C1IER_ISE3

Definition at line 72 of file stm32wbxx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_30 HSEM_C1IER_ISE30

Definition at line 99 of file stm32wbxx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_31 HSEM_C1IER_ISE31

Definition at line 100 of file stm32wbxx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_4 HSEM_C1IER_ISE4

Definition at line 73 of file stm32wbxx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_5 HSEM_C1IER_ISE5

Definition at line 74 of file stm32wbxx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_6 HSEM_C1IER_ISE6

Definition at line 75 of file stm32wbxx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_7 HSEM_C1IER_ISE7

Definition at line 76 of file stm32wbxx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_8 HSEM_C1IER_ISE8

Definition at line 77 of file stm32wbxx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_9 HSEM_C1IER_ISE9

Definition at line 78 of file stm32wbxx_ll_hsem.h.

#define LL_HSEM_SEMAPHORE_ALL 0xFFFFFFFFU

Definition at line 101 of file stm32wbxx_ll_hsem.h.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
HSEM Exported Macros

Defines

#define | LL_HSEM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in HSEM register.
#define | LL_HSEM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in HSEM register.

Define Documentation

#define LL_HSEM_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in HSEM register.

Parameters:
__INSTANCE__ | HSEM Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 134 of file stm32wbxx_ll_hsem.h.

#define LL_HSEM_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in HSEM register.

Parameters:
__INSTANCE__ | HSEM Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 126 of file stm32wbxx_ll_hsem.h.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data_Management

Functions
Data_Management
HSEM Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_HSEM_IsSemaphoreLocked (HSEM_TypeDef *HSEMx, uint32_t Semaphore)
Return 1 if the semaphore is locked, else return 0.
__STATIC_INLINE uint32_t | LL_HSEM_GetCoreId (HSEM_TypeDef *HSEMx, uint32_t Semaphore)
Get core id.
__STATIC_INLINE uint32_t | LL_HSEM_GetProcessId (HSEM_TypeDef *HSEMx, uint32_t Semaphore)
Get process id.
__STATIC_INLINE void | LL_HSEM_SetLock (HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
Get the lock by writing in R register.
__STATIC_INLINE uint32_t | LL_HSEM_2StepLock (HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
Get the lock with 2-step lock.
__STATIC_INLINE uint32_t | LL_HSEM_1StepLock (HSEM_TypeDef *HSEMx, uint32_t Semaphore)
Get the lock with 1-step lock.
__STATIC_INLINE void | LL_HSEM_ReleaseLock (HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
Release the lock of the semaphore.
__STATIC_INLINE uint32_t | LL_HSEM_GetStatus (HSEM_TypeDef *HSEMx, uint32_t Semaphore)
Get the lock status of the semaphore.
__STATIC_INLINE void | LL_HSEM_SetKey (HSEM_TypeDef *HSEMx, uint32_t key)
Set the key.
__STATIC_INLINE uint32_t | LL_HSEM_GetKey (HSEM_TypeDef *HSEMx)
Get the key.
__STATIC_INLINE void | LL_HSEM_ResetAllLock (HSEM_TypeDef *HSEMx, uint32_t key, uint32_t core)
Release all semaphore with the same core id.

Function Documentation

__STATIC_INLINE uint32_t LL_HSEM_1StepLock | ( | HSEM_TypeDef * | HSEMx,
 |  | uint32_t | Semaphore
 | ) |  |

Get the lock with 1-step lock.

Reference Manual to LL API cross reference:
RLR LOCK LL_HSEM_1StepLock
Reference Manual to LL API cross reference:
RLR COREID LL_HSEM_1StepLock
Reference Manual to LL API cross reference:
RLR PROCID LL_HSEM_1StepLock
Parameters:
HSEMx | HSEM Instance.
Semaphore | Semaphore number. Value between Min_Data=0 and Max_Data=31
Return values:
1 lock fail, 0 lock successful or already locked by same core

Definition at line 233 of file stm32wbxx_ll_hsem.h.

References LL_HSEM_COREID.

__STATIC_INLINE uint32_t LL_HSEM_2StepLock | ( | HSEM_TypeDef * | HSEMx,
 |  | uint32_t | Semaphore,
 |  | uint32_t | process
 | ) |  |

Get the lock with 2-step lock.

Reference Manual to LL API cross reference:
R LOCK LL_HSEM_2StepLock
Reference Manual to LL API cross reference:
R COREID LL_HSEM_2StepLock
Reference Manual to LL API cross reference:
R PROCID LL_HSEM_2StepLock
Parameters:
HSEMx | HSEM Instance.
Semaphore | Semaphore number. Value between Min_Data=0 and Max_Data=31
process | Process id. Value between Min_Data=0 and Max_Data=255
Return values:
1 lock fail, 0 lock successful or already locked by same process and core

Definition at line 218 of file stm32wbxx_ll_hsem.h.

References LL_HSEM_COREID.

__STATIC_INLINE uint32_t LL_HSEM_GetCoreId | ( | HSEM_TypeDef * | HSEMx,
 |  | uint32_t | Semaphore
 | ) |  |

Get core id.

Reference Manual to LL API cross reference:
R COREID LL_HSEM_GetCoreId
Parameters:
HSEMx | HSEM Instance.
Semaphore | Semaphore number. Value between Min_Data=0 and Max_Data=31
Return values:
Returned value can be one of the following values:
  • LL_HSEM_COREID_NONE
  • LL_HSEM_COREID_CPU1
  • LL_HSEM_COREID_CPU2

Definition at line 175 of file stm32wbxx_ll_hsem.h.

__STATIC_INLINE uint32_t LL_HSEM_GetKey ( HSEM_TypeDef * HSEMx )

Get the key.

Reference Manual to LL API cross reference:
KEYR KEY LL_HSEM_GetKey
Parameters:
HSEMx HSEM Instance.
Return values:
key to unlock all semaphore from the same core

Definition at line 281 of file stm32wbxx_ll_hsem.h.

__STATIC_INLINE uint32_t LL_HSEM_GetProcessId | ( | HSEM_TypeDef * | HSEMx,
 |  | uint32_t | Semaphore
 | ) |  |

Get process id.

Reference Manual to LL API cross reference:
R PROCID LL_HSEM_GetProcessId
Parameters:
HSEMx | HSEM Instance.
Semaphore | Semaphore number. Value between Min_Data=0 and Max_Data=31
Return values:
Process number. Value between Min_Data=0 and Max_Data=255

Definition at line 187 of file stm32wbxx_ll_hsem.h.

__STATIC_INLINE uint32_t LL_HSEM_GetStatus | ( | HSEM_TypeDef * | HSEMx,
 |  | uint32_t | Semaphore
 | ) |  |

Get the lock status of the semaphore.

Reference Manual to LL API cross reference:
R LOCK LL_HSEM_GetStatus
Parameters:
HSEMx | HSEM Instance.
Semaphore | Semaphore number. Value between Min_Data=0 and Max_Data=31
Return values:
0 semaphore is free, 1 semaphore is locked

Definition at line 258 of file stm32wbxx_ll_hsem.h.

__STATIC_INLINE uint32_t LL_HSEM_IsSemaphoreLocked | ( | HSEM_TypeDef * | HSEMx,
 |  | uint32_t | Semaphore
 | ) |  |

Return 1 if the semaphore is locked, else return 0.

Reference Manual to LL API cross reference:
R LOCK LL_HSEM_IsSemaphoreLocked
Parameters:
HSEMx | HSEM Instance.
Semaphore | Semaphore number. Value between Min_Data=0 and Max_Data=31
Return values:
State of bit (1 or 0).

Definition at line 160 of file stm32wbxx_ll_hsem.h.

__STATIC_INLINE void LL_HSEM_ReleaseLock | ( | HSEM_TypeDef * | HSEMx,
 |  | uint32_t | Semaphore,
 |  | uint32_t | process
 | ) |  |

Release the lock of the semaphore.

Note:
In case of LL_HSEM_1StepLock usage to lock a semaphore, the process is 0.
Reference Manual to LL API cross reference:
R LOCK LL_HSEM_ReleaseLock
Parameters:
HSEMx | HSEM Instance.
Semaphore | Semaphore number. Value between Min_Data=0 and Max_Data=31
process | Process number. Value between Min_Data=0 and Max_Data=255
Return values:
None

Definition at line 247 of file stm32wbxx_ll_hsem.h.

References LL_HSEM_COREID.

__STATIC_INLINE void LL_HSEM_ResetAllLock | ( | HSEM_TypeDef * | HSEMx,
 |  | uint32_t | key,
 |  | uint32_t | core
 | ) |  |

Release all semaphore with the same core id.

Reference Manual to LL API cross reference:
CR KEY LL_HSEM_ResetAllLock
Parameters:
HSEMx | HSEM Instance.
key | Key value.
core This parameter can be one of the following values:
  • LL_HSEM_COREID_CPU1
  • LL_HSEM_COREID_CPU2
Return values:
None

Definition at line 296 of file stm32wbxx_ll_hsem.h.

__STATIC_INLINE void LL_HSEM_SetKey | ( | HSEM_TypeDef * | HSEMx,
 |  | uint32_t | key
 | ) |  |

Set the key.

Reference Manual to LL API cross reference:
KEYR KEY LL_HSEM_SetKey
Parameters:
HSEMx | HSEM Instance.
key | Key value.
Return values:
None

Definition at line 270 of file stm32wbxx_ll_hsem.h.

__STATIC_INLINE void LL_HSEM_SetLock | ( | HSEM_TypeDef * | HSEMx,
 |  | uint32_t | Semaphore,
 |  | uint32_t | process
 | ) |  |

Get the lock by writing in R register.

Note:
The R register has to be read to determined if the lock is taken.
Reference Manual to LL API cross reference:
R LOCK LL_HSEM_SetLock
Reference Manual to LL API cross reference:
R COREID LL_HSEM_SetLock
Reference Manual to LL API cross reference:
R PROCID LL_HSEM_SetLock
Parameters:
HSEMx | HSEM Instance.
Semaphore | Semaphore number. Value between Min_Data=0 and Max_Data=31
process | Process id. Value between Min_Data=0 and Max_Data=255
Return values:
None

Definition at line 203 of file stm32wbxx_ll_hsem.h.

References LL_HSEM_COREID.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IT_Management

Functions
IT_Management
HSEM Exported Functions

Functions

__STATIC_INLINE void | LL_HSEM_EnableIT_C1IER (HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
Enable interrupt.
__STATIC_INLINE void | LL_HSEM_DisableIT_C1IER (HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
Disable interrupt.
__STATIC_INLINE uint32_t | LL_HSEM_IsEnabledIT_C1IER (HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
Check if interrupt is enabled.
__STATIC_INLINE void | LL_HSEM_EnableIT_C2IER (HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
Enable interrupt.
__STATIC_INLINE void | LL_HSEM_DisableIT_C2IER (HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
Disable interrupt.
__STATIC_INLINE uint32_t | LL_HSEM_IsEnabledIT_C2IER (HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
Check if interrupt is enabled.

Function Documentation

__STATIC_INLINE void LL_HSEM_DisableIT_C1IER | ( | HSEM_TypeDef * | HSEMx,
 |  | uint32_t | SemaphoreMask
 | ) |  |

Disable interrupt.

Reference Manual to LL API cross reference:
C1IER ISEM LL_HSEM_DisableIT_C1IER
Parameters:
HSEMx HSEM Instance.
SemaphoreMask This parameter can be a combination of the following values:
  • LL_HSEM_SEMAPHORE_0
  • LL_HSEM_SEMAPHORE_1
  • LL_HSEM_SEMAPHORE_2
  • LL_HSEM_SEMAPHORE_3
  • LL_HSEM_SEMAPHORE_4
  • LL_HSEM_SEMAPHORE_5
  • LL_HSEM_SEMAPHORE_6
  • LL_HSEM_SEMAPHORE_7
  • LL_HSEM_SEMAPHORE_8
  • LL_HSEM_SEMAPHORE_9
  • LL_HSEM_SEMAPHORE_10
  • LL_HSEM_SEMAPHORE_11
  • LL_HSEM_SEMAPHORE_12
  • LL_HSEM_SEMAPHORE_13
  • LL_HSEM_SEMAPHORE_14
  • LL_HSEM_SEMAPHORE_15
  • LL_HSEM_SEMAPHORE_16
  • LL_HSEM_SEMAPHORE_17
  • LL_HSEM_SEMAPHORE_18
  • LL_HSEM_SEMAPHORE_19
  • LL_HSEM_SEMAPHORE_20
  • LL_HSEM_SEMAPHORE_21
  • LL_HSEM_SEMAPHORE_22
  • LL_HSEM_SEMAPHORE_23
  • LL_HSEM_SEMAPHORE_24
  • LL_HSEM_SEMAPHORE_25
  • LL_HSEM_SEMAPHORE_26
  • LL_HSEM_SEMAPHORE_27
  • LL_HSEM_SEMAPHORE_28
  • LL_HSEM_SEMAPHORE_29
  • LL_HSEM_SEMAPHORE_30
  • LL_HSEM_SEMAPHORE_31
  • LL_HSEM_SEMAPHORE_ALL
Return values:
None

Definition at line 394 of file stm32wbxx_ll_hsem.h.

__STATIC_INLINE void LL_HSEM_DisableIT_C2IER | ( | HSEM_TypeDef * | HSEMx,
 |  | uint32_t | SemaphoreMask
 | ) |  |

Disable interrupt.

Reference Manual to LL API cross reference:
C2IER ISEM LL_HSEM_DisableIT_C2IER
Parameters:
HSEMx HSEM Instance.
SemaphoreMask This parameter can be a combination of the following values:
  • LL_HSEM_SEMAPHORE_0
  • LL_HSEM_SEMAPHORE_1
  • LL_HSEM_SEMAPHORE_2
  • LL_HSEM_SEMAPHORE_3
  • LL_HSEM_SEMAPHORE_4
  • LL_HSEM_SEMAPHORE_5
  • LL_HSEM_SEMAPHORE_6
  • LL_HSEM_SEMAPHORE_7
  • LL_HSEM_SEMAPHORE_8
  • LL_HSEM_SEMAPHORE_9
  • LL_HSEM_SEMAPHORE_10
  • LL_HSEM_SEMAPHORE_11
  • LL_HSEM_SEMAPHORE_12
  • LL_HSEM_SEMAPHORE_13
  • LL_HSEM_SEMAPHORE_14
  • LL_HSEM_SEMAPHORE_15
  • LL_HSEM_SEMAPHORE_16
  • LL_HSEM_SEMAPHORE_17
  • LL_HSEM_SEMAPHORE_18
  • LL_HSEM_SEMAPHORE_19
  • LL_HSEM_SEMAPHORE_20
  • LL_HSEM_SEMAPHORE_21
  • LL_HSEM_SEMAPHORE_22
  • LL_HSEM_SEMAPHORE_23
  • LL_HSEM_SEMAPHORE_24
  • LL_HSEM_SEMAPHORE_25
  • LL_HSEM_SEMAPHORE_26
  • LL_HSEM_SEMAPHORE_27
  • LL_HSEM_SEMAPHORE_28
  • LL_HSEM_SEMAPHORE_29
  • LL_HSEM_SEMAPHORE_30
  • LL_HSEM_SEMAPHORE_31
  • LL_HSEM_SEMAPHORE_ALL
Return values:
None

Definition at line 529 of file stm32wbxx_ll_hsem.h.

__STATIC_INLINE void LL_HSEM_EnableIT_C1IER | ( | HSEM_TypeDef * | HSEMx,
 |  | uint32_t | SemaphoreMask
 | ) |  |

Enable interrupt.

Reference Manual to LL API cross reference:
C1IER ISEM LL_HSEM_EnableIT_C1IER
Parameters:
HSEMx HSEM Instance.
SemaphoreMask This parameter can be a combination of the following values:
  • LL_HSEM_SEMAPHORE_0
  • LL_HSEM_SEMAPHORE_1
  • LL_HSEM_SEMAPHORE_2
  • LL_HSEM_SEMAPHORE_3
  • LL_HSEM_SEMAPHORE_4
  • LL_HSEM_SEMAPHORE_5
  • LL_HSEM_SEMAPHORE_6
  • LL_HSEM_SEMAPHORE_7
  • LL_HSEM_SEMAPHORE_8
  • LL_HSEM_SEMAPHORE_9
  • LL_HSEM_SEMAPHORE_10
  • LL_HSEM_SEMAPHORE_11
  • LL_HSEM_SEMAPHORE_12
  • LL_HSEM_SEMAPHORE_13
  • LL_HSEM_SEMAPHORE_14
  • LL_HSEM_SEMAPHORE_15
  • LL_HSEM_SEMAPHORE_16
  • LL_HSEM_SEMAPHORE_17
  • LL_HSEM_SEMAPHORE_18
  • LL_HSEM_SEMAPHORE_19
  • LL_HSEM_SEMAPHORE_20
  • LL_HSEM_SEMAPHORE_21
  • LL_HSEM_SEMAPHORE_22
  • LL_HSEM_SEMAPHORE_23
  • LL_HSEM_SEMAPHORE_24
  • LL_HSEM_SEMAPHORE_25
  • LL_HSEM_SEMAPHORE_26
  • LL_HSEM_SEMAPHORE_27
  • LL_HSEM_SEMAPHORE_28
  • LL_HSEM_SEMAPHORE_29
  • LL_HSEM_SEMAPHORE_30
  • LL_HSEM_SEMAPHORE_31
  • LL_HSEM_SEMAPHORE_ALL
Return values:
None

Definition at line 349 of file stm32wbxx_ll_hsem.h.

__STATIC_INLINE void LL_HSEM_EnableIT_C2IER | ( | HSEM_TypeDef * | HSEMx,
 |  | uint32_t | SemaphoreMask
 | ) |  |

Enable interrupt.

Reference Manual to LL API cross reference:
C2IER ISEM LL_HSEM_EnableIT_C2IER
Parameters:
HSEMx HSEM Instance.
SemaphoreMask This parameter can be a combination of the following values:
  • LL_HSEM_SEMAPHORE_0
  • LL_HSEM_SEMAPHORE_1
  • LL_HSEM_SEMAPHORE_2
  • LL_HSEM_SEMAPHORE_3
  • LL_HSEM_SEMAPHORE_4
  • LL_HSEM_SEMAPHORE_5
  • LL_HSEM_SEMAPHORE_6
  • LL_HSEM_SEMAPHORE_7
  • LL_HSEM_SEMAPHORE_8
  • LL_HSEM_SEMAPHORE_9
  • LL_HSEM_SEMAPHORE_10
  • LL_HSEM_SEMAPHORE_11
  • LL_HSEM_SEMAPHORE_12
  • LL_HSEM_SEMAPHORE_13
  • LL_HSEM_SEMAPHORE_14
  • LL_HSEM_SEMAPHORE_15
  • LL_HSEM_SEMAPHORE_16
  • LL_HSEM_SEMAPHORE_17
  • LL_HSEM_SEMAPHORE_18
  • LL_HSEM_SEMAPHORE_19
  • LL_HSEM_SEMAPHORE_20
  • LL_HSEM_SEMAPHORE_21
  • LL_HSEM_SEMAPHORE_22
  • LL_HSEM_SEMAPHORE_23
  • LL_HSEM_SEMAPHORE_24
  • LL_HSEM_SEMAPHORE_25
  • LL_HSEM_SEMAPHORE_26
  • LL_HSEM_SEMAPHORE_27
  • LL_HSEM_SEMAPHORE_28
  • LL_HSEM_SEMAPHORE_29
  • LL_HSEM_SEMAPHORE_30
  • LL_HSEM_SEMAPHORE_31
  • LL_HSEM_SEMAPHORE_ALL
Return values:
None

Definition at line 484 of file stm32wbxx_ll_hsem.h.

__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C1IER | ( | HSEM_TypeDef * | HSEMx,
 |  | uint32_t | SemaphoreMask
 | ) |  |

Check if interrupt is enabled.

Reference Manual to LL API cross reference:
C1IER ISEM LL_HSEM_IsEnabledIT_C1IER
Parameters:
HSEMx HSEM Instance.
SemaphoreMask This parameter can be a combination of the following values:
  • LL_HSEM_SEMAPHORE_0
  • LL_HSEM_SEMAPHORE_1
  • LL_HSEM_SEMAPHORE_2
  • LL_HSEM_SEMAPHORE_3
  • LL_HSEM_SEMAPHORE_4
  • LL_HSEM_SEMAPHORE_5
  • LL_HSEM_SEMAPHORE_6
  • LL_HSEM_SEMAPHORE_7
  • LL_HSEM_SEMAPHORE_8
  • LL_HSEM_SEMAPHORE_9
  • LL_HSEM_SEMAPHORE_10
  • LL_HSEM_SEMAPHORE_11
  • LL_HSEM_SEMAPHORE_12
  • LL_HSEM_SEMAPHORE_13
  • LL_HSEM_SEMAPHORE_14
  • LL_HSEM_SEMAPHORE_15
  • LL_HSEM_SEMAPHORE_16
  • LL_HSEM_SEMAPHORE_17
  • LL_HSEM_SEMAPHORE_18
  • LL_HSEM_SEMAPHORE_19
  • LL_HSEM_SEMAPHORE_20
  • LL_HSEM_SEMAPHORE_21
  • LL_HSEM_SEMAPHORE_22
  • LL_HSEM_SEMAPHORE_23
  • LL_HSEM_SEMAPHORE_24
  • LL_HSEM_SEMAPHORE_25
  • LL_HSEM_SEMAPHORE_26
  • LL_HSEM_SEMAPHORE_27
  • LL_HSEM_SEMAPHORE_28
  • LL_HSEM_SEMAPHORE_29
  • LL_HSEM_SEMAPHORE_30
  • LL_HSEM_SEMAPHORE_31
  • LL_HSEM_SEMAPHORE_ALL
Return values:
State of bit (1 or 0).

Definition at line 439 of file stm32wbxx_ll_hsem.h.

__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C2IER | ( | HSEM_TypeDef * | HSEMx,
 |  | uint32_t | SemaphoreMask
 | ) |  |

Check if interrupt is enabled.

Reference Manual to LL API cross reference:
C2IER ISEM LL_HSEM_IsEnabledIT_C2IER
Parameters:
HSEMx HSEM Instance.
SemaphoreMask This parameter can be a combination of the following values:
  • LL_HSEM_SEMAPHORE_0
  • LL_HSEM_SEMAPHORE_1
  • LL_HSEM_SEMAPHORE_2
  • LL_HSEM_SEMAPHORE_3
  • LL_HSEM_SEMAPHORE_4
  • LL_HSEM_SEMAPHORE_5
  • LL_HSEM_SEMAPHORE_6
  • LL_HSEM_SEMAPHORE_7
  • LL_HSEM_SEMAPHORE_8
  • LL_HSEM_SEMAPHORE_9
  • LL_HSEM_SEMAPHORE_10
  • LL_HSEM_SEMAPHORE_11
  • LL_HSEM_SEMAPHORE_12
  • LL_HSEM_SEMAPHORE_13
  • LL_HSEM_SEMAPHORE_14
  • LL_HSEM_SEMAPHORE_15
  • LL_HSEM_SEMAPHORE_16
  • LL_HSEM_SEMAPHORE_17
  • LL_HSEM_SEMAPHORE_18
  • LL_HSEM_SEMAPHORE_19
  • LL_HSEM_SEMAPHORE_20
  • LL_HSEM_SEMAPHORE_21
  • LL_HSEM_SEMAPHORE_22
  • LL_HSEM_SEMAPHORE_23
  • LL_HSEM_SEMAPHORE_24
  • LL_HSEM_SEMAPHORE_25
  • LL_HSEM_SEMAPHORE_26
  • LL_HSEM_SEMAPHORE_27
  • LL_HSEM_SEMAPHORE_28
  • LL_HSEM_SEMAPHORE_29
  • LL_HSEM_SEMAPHORE_30
  • LL_HSEM_SEMAPHORE_31
  • LL_HSEM_SEMAPHORE_ALL
Return values:
State of bit (1 or 0).

Definition at line 574 of file stm32wbxx_ll_hsem.h.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FLAG_Management

Functions
FLAG_Management
HSEM Exported Functions

Functions

__STATIC_INLINE void | LL_HSEM_ClearFlag_C1ICR (HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
Clear interrupt status.
__STATIC_INLINE uint32_t | LL_HSEM_IsActiveFlag_C1ISR (HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
Get interrupt status from ISR register.
__STATIC_INLINE uint32_t | LL_HSEM_IsActiveFlag_C1MISR (HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
Get interrupt status from MISR register.
__STATIC_INLINE void | LL_HSEM_ClearFlag_C2ICR (HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
Clear interrupt status.
__STATIC_INLINE uint32_t | LL_HSEM_IsActiveFlag_C2ISR (HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
Get interrupt status from ISR register.
__STATIC_INLINE uint32_t | LL_HSEM_IsActiveFlag_C2MISR (HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
Get interrupt status from MISR register.

Function Documentation

__STATIC_INLINE void LL_HSEM_ClearFlag_C1ICR | ( | HSEM_TypeDef * | HSEMx,
 |  | uint32_t | SemaphoreMask
 | ) |  |

Clear interrupt status.

Reference Manual to LL API cross reference:
C1ICR ISEM LL_HSEM_ClearFlag_C1ICR
Parameters:
HSEMx HSEM Instance.
SemaphoreMask This parameter can be a combination of the following values:
  • LL_HSEM_SEMAPHORE_0
  • LL_HSEM_SEMAPHORE_1
  • LL_HSEM_SEMAPHORE_2
  • LL_HSEM_SEMAPHORE_3
  • LL_HSEM_SEMAPHORE_4
  • LL_HSEM_SEMAPHORE_5
  • LL_HSEM_SEMAPHORE_6
  • LL_HSEM_SEMAPHORE_7
  • LL_HSEM_SEMAPHORE_8
  • LL_HSEM_SEMAPHORE_9
  • LL_HSEM_SEMAPHORE_10
  • LL_HSEM_SEMAPHORE_11
  • LL_HSEM_SEMAPHORE_12
  • LL_HSEM_SEMAPHORE_13
  • LL_HSEM_SEMAPHORE_14
  • LL_HSEM_SEMAPHORE_15
  • LL_HSEM_SEMAPHORE_16
  • LL_HSEM_SEMAPHORE_17
  • LL_HSEM_SEMAPHORE_18
  • LL_HSEM_SEMAPHORE_19
  • LL_HSEM_SEMAPHORE_20
  • LL_HSEM_SEMAPHORE_21
  • LL_HSEM_SEMAPHORE_22
  • LL_HSEM_SEMAPHORE_23
  • LL_HSEM_SEMAPHORE_24
  • LL_HSEM_SEMAPHORE_25
  • LL_HSEM_SEMAPHORE_26
  • LL_HSEM_SEMAPHORE_27
  • LL_HSEM_SEMAPHORE_28
  • LL_HSEM_SEMAPHORE_29
  • LL_HSEM_SEMAPHORE_30
  • LL_HSEM_SEMAPHORE_31
  • LL_HSEM_SEMAPHORE_ALL
Return values:
None

Definition at line 626 of file stm32wbxx_ll_hsem.h.

__STATIC_INLINE void LL_HSEM_ClearFlag_C2ICR | ( | HSEM_TypeDef * | HSEMx,
 |  | uint32_t | SemaphoreMask
 | ) |  |

Clear interrupt status.

Reference Manual to LL API cross reference:
C2ICR ISEM LL_HSEM_ClearFlag_C2ICR
Parameters:
HSEMx HSEM Instance.
SemaphoreMask This parameter can be a combination of the following values:
  • LL_HSEM_SEMAPHORE_0
  • LL_HSEM_SEMAPHORE_1
  • LL_HSEM_SEMAPHORE_2
  • LL_HSEM_SEMAPHORE_3
  • LL_HSEM_SEMAPHORE_4
  • LL_HSEM_SEMAPHORE_5
  • LL_HSEM_SEMAPHORE_6
  • LL_HSEM_SEMAPHORE_7
  • LL_HSEM_SEMAPHORE_8
  • LL_HSEM_SEMAPHORE_9
  • LL_HSEM_SEMAPHORE_10
  • LL_HSEM_SEMAPHORE_11
  • LL_HSEM_SEMAPHORE_12
  • LL_HSEM_SEMAPHORE_13
  • LL_HSEM_SEMAPHORE_14
  • LL_HSEM_SEMAPHORE_15
  • LL_HSEM_SEMAPHORE_16
  • LL_HSEM_SEMAPHORE_17
  • LL_HSEM_SEMAPHORE_18
  • LL_HSEM_SEMAPHORE_19
  • LL_HSEM_SEMAPHORE_20
  • LL_HSEM_SEMAPHORE_21
  • LL_HSEM_SEMAPHORE_22
  • LL_HSEM_SEMAPHORE_23
  • LL_HSEM_SEMAPHORE_24
  • LL_HSEM_SEMAPHORE_25
  • LL_HSEM_SEMAPHORE_26
  • LL_HSEM_SEMAPHORE_27
  • LL_HSEM_SEMAPHORE_28
  • LL_HSEM_SEMAPHORE_29
  • LL_HSEM_SEMAPHORE_30
  • LL_HSEM_SEMAPHORE_31
  • LL_HSEM_SEMAPHORE_ALL
Return values:
None

Definition at line 761 of file stm32wbxx_ll_hsem.h.

__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR | ( | HSEM_TypeDef * | HSEMx,
 |  | uint32_t | SemaphoreMask
 | ) |  |

Get interrupt status from ISR register.

Reference Manual to LL API cross reference:
C1ISR ISEM LL_HSEM_IsActiveFlag_C1ISR
Parameters:
HSEMx HSEM Instance.
SemaphoreMask This parameter can be a combination of the following values:
  • LL_HSEM_SEMAPHORE_0
  • LL_HSEM_SEMAPHORE_1
  • LL_HSEM_SEMAPHORE_2
  • LL_HSEM_SEMAPHORE_3
  • LL_HSEM_SEMAPHORE_4
  • LL_HSEM_SEMAPHORE_5
  • LL_HSEM_SEMAPHORE_6
  • LL_HSEM_SEMAPHORE_7
  • LL_HSEM_SEMAPHORE_8
  • LL_HSEM_SEMAPHORE_9
  • LL_HSEM_SEMAPHORE_10
  • LL_HSEM_SEMAPHORE_11
  • LL_HSEM_SEMAPHORE_12
  • LL_HSEM_SEMAPHORE_13
  • LL_HSEM_SEMAPHORE_14
  • LL_HSEM_SEMAPHORE_15
  • LL_HSEM_SEMAPHORE_16
  • LL_HSEM_SEMAPHORE_17
  • LL_HSEM_SEMAPHORE_18
  • LL_HSEM_SEMAPHORE_19
  • LL_HSEM_SEMAPHORE_20
  • LL_HSEM_SEMAPHORE_21
  • LL_HSEM_SEMAPHORE_22
  • LL_HSEM_SEMAPHORE_23
  • LL_HSEM_SEMAPHORE_24
  • LL_HSEM_SEMAPHORE_25
  • LL_HSEM_SEMAPHORE_26
  • LL_HSEM_SEMAPHORE_27
  • LL_HSEM_SEMAPHORE_28
  • LL_HSEM_SEMAPHORE_29
  • LL_HSEM_SEMAPHORE_30
  • LL_HSEM_SEMAPHORE_31
  • LL_HSEM_SEMAPHORE_ALL
Return values:
State of bit (1 or 0).

Definition at line 671 of file stm32wbxx_ll_hsem.h.

__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1MISR | ( | HSEM_TypeDef * | HSEMx,
 |  | uint32_t | SemaphoreMask
 | ) |  |

Get interrupt status from MISR register.

Reference Manual to LL API cross reference:
C1MISR ISEM LL_HSEM_IsActiveFlag_C1MISR
Parameters:
HSEMx HSEM Instance.
SemaphoreMask This parameter can be a combination of the following values:
  • LL_HSEM_SEMAPHORE_0
  • LL_HSEM_SEMAPHORE_1
  • LL_HSEM_SEMAPHORE_2
  • LL_HSEM_SEMAPHORE_3
  • LL_HSEM_SEMAPHORE_4
  • LL_HSEM_SEMAPHORE_5
  • LL_HSEM_SEMAPHORE_6
  • LL_HSEM_SEMAPHORE_7
  • LL_HSEM_SEMAPHORE_8
  • LL_HSEM_SEMAPHORE_9
  • LL_HSEM_SEMAPHORE_10
  • LL_HSEM_SEMAPHORE_11
  • LL_HSEM_SEMAPHORE_12
  • LL_HSEM_SEMAPHORE_13
  • LL_HSEM_SEMAPHORE_14
  • LL_HSEM_SEMAPHORE_15
  • LL_HSEM_SEMAPHORE_16
  • LL_HSEM_SEMAPHORE_17
  • LL_HSEM_SEMAPHORE_18
  • LL_HSEM_SEMAPHORE_19
  • LL_HSEM_SEMAPHORE_20
  • LL_HSEM_SEMAPHORE_21
  • LL_HSEM_SEMAPHORE_22
  • LL_HSEM_SEMAPHORE_23
  • LL_HSEM_SEMAPHORE_24
  • LL_HSEM_SEMAPHORE_25
  • LL_HSEM_SEMAPHORE_26
  • LL_HSEM_SEMAPHORE_27
  • LL_HSEM_SEMAPHORE_28
  • LL_HSEM_SEMAPHORE_29
  • LL_HSEM_SEMAPHORE_30
  • LL_HSEM_SEMAPHORE_31
  • LL_HSEM_SEMAPHORE_ALL
Return values:
State of bit (1 or 0).

Definition at line 716 of file stm32wbxx_ll_hsem.h.

__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2ISR | ( | HSEM_TypeDef * | HSEMx,
 |  | uint32_t | SemaphoreMask
 | ) |  |

Get interrupt status from ISR register.

Reference Manual to LL API cross reference:
C2ISR ISEM LL_HSEM_IsActiveFlag_C2ISR
Parameters:
HSEMx HSEM Instance.
SemaphoreMask This parameter can be a combination of the following values:
  • LL_HSEM_SEMAPHORE_0
  • LL_HSEM_SEMAPHORE_1
  • LL_HSEM_SEMAPHORE_2
  • LL_HSEM_SEMAPHORE_3
  • LL_HSEM_SEMAPHORE_4
  • LL_HSEM_SEMAPHORE_5
  • LL_HSEM_SEMAPHORE_6
  • LL_HSEM_SEMAPHORE_7
  • LL_HSEM_SEMAPHORE_8
  • LL_HSEM_SEMAPHORE_9
  • LL_HSEM_SEMAPHORE_10
  • LL_HSEM_SEMAPHORE_11
  • LL_HSEM_SEMAPHORE_12
  • LL_HSEM_SEMAPHORE_13
  • LL_HSEM_SEMAPHORE_14
  • LL_HSEM_SEMAPHORE_15
  • LL_HSEM_SEMAPHORE_16
  • LL_HSEM_SEMAPHORE_17
  • LL_HSEM_SEMAPHORE_18
  • LL_HSEM_SEMAPHORE_19
  • LL_HSEM_SEMAPHORE_20
  • LL_HSEM_SEMAPHORE_21
  • LL_HSEM_SEMAPHORE_22
  • LL_HSEM_SEMAPHORE_23
  • LL_HSEM_SEMAPHORE_24
  • LL_HSEM_SEMAPHORE_25
  • LL_HSEM_SEMAPHORE_26
  • LL_HSEM_SEMAPHORE_27
  • LL_HSEM_SEMAPHORE_28
  • LL_HSEM_SEMAPHORE_29
  • LL_HSEM_SEMAPHORE_30
  • LL_HSEM_SEMAPHORE_31
  • LL_HSEM_SEMAPHORE_ALL
Return values:
State of bit (1 or 0).

Definition at line 806 of file stm32wbxx_ll_hsem.h.

__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2MISR | ( | HSEM_TypeDef * | HSEMx,
 |  | uint32_t | SemaphoreMask
 | ) |  |

Get interrupt status from MISR register.

Reference Manual to LL API cross reference:
C2MISR ISEM LL_HSEM_IsActiveFlag_C2MISR
Parameters:
HSEMx HSEM Instance.
SemaphoreMask This parameter can be a combination of the following values:
  • LL_HSEM_SEMAPHORE_0
  • LL_HSEM_SEMAPHORE_1
  • LL_HSEM_SEMAPHORE_2
  • LL_HSEM_SEMAPHORE_3
  • LL_HSEM_SEMAPHORE_4
  • LL_HSEM_SEMAPHORE_5
  • LL_HSEM_SEMAPHORE_6
  • LL_HSEM_SEMAPHORE_7
  • LL_HSEM_SEMAPHORE_8
  • LL_HSEM_SEMAPHORE_9
  • LL_HSEM_SEMAPHORE_10
  • LL_HSEM_SEMAPHORE_11
  • LL_HSEM_SEMAPHORE_12
  • LL_HSEM_SEMAPHORE_13
  • LL_HSEM_SEMAPHORE_14
  • LL_HSEM_SEMAPHORE_15
  • LL_HSEM_SEMAPHORE_16
  • LL_HSEM_SEMAPHORE_17
  • LL_HSEM_SEMAPHORE_18
  • LL_HSEM_SEMAPHORE_19
  • LL_HSEM_SEMAPHORE_20
  • LL_HSEM_SEMAPHORE_21
  • LL_HSEM_SEMAPHORE_22
  • LL_HSEM_SEMAPHORE_23
  • LL_HSEM_SEMAPHORE_24
  • LL_HSEM_SEMAPHORE_25
  • LL_HSEM_SEMAPHORE_26
  • LL_HSEM_SEMAPHORE_27
  • LL_HSEM_SEMAPHORE_28
  • LL_HSEM_SEMAPHORE_29
  • LL_HSEM_SEMAPHORE_30
  • LL_HSEM_SEMAPHORE_31
  • LL_HSEM_SEMAPHORE_ALL
Return values:
State of bit (1 or 0).

Definition at line 851 of file stm32wbxx_ll_hsem.h.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: I2C

Modules
I2C
STM32WBxx_LL_Driver

Modules

I2C Private Constants
I2C Private Macros
I2C Exported Init structure
I2C Exported Constants
I2C Exported Macros
I2C Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for I2C registers.

Register | Bit | Function
CR1 | ADDRIE | LL_I2C_DisableIT_ADDR
 |  | LL_I2C_EnableIT_ADDR
 |  | LL_I2C_IsEnabledIT_ADDR
 | ALERTEN | LL_I2C_DisableSMBusAlert
 |  | LL_I2C_EnableSMBusAlert
 |  | LL_I2C_IsEnabledSMBusAlert
 | ANFOFF | LL_I2C_ConfigFilters
 |  | LL_I2C_DisableAnalogFilter
 |  | LL_I2C_EnableAnalogFilter
 |  | LL_I2C_IsEnabledAnalogFilter
 | DNF | LL_I2C_ConfigFilters
 |  | LL_I2C_GetDigitalFilter
 |  | LL_I2C_SetDigitalFilter
 | ERRIE | LL_I2C_DisableIT_ERR
 |  | LL_I2C_EnableIT_ERR
 |  | LL_I2C_IsEnabledIT_ERR
 | GCEN | LL_I2C_DisableGeneralCall
 |  | LL_I2C_EnableGeneralCall
 |  | LL_I2C_IsEnabledGeneralCall
 | NACKIE | LL_I2C_DisableIT_NACK
 |  | LL_I2C_EnableIT_NACK
 |  | LL_I2C_IsEnabledIT_NACK
 | NOSTRETCH | LL_I2C_DisableClockStretching
 |  | LL_I2C_EnableClockStretching
 |  | LL_I2C_IsEnabledClockStretching
 | PE | LL_I2C_Disable
 |  | LL_I2C_Enable
 |  | LL_I2C_IsEnabled
 | PECEN | LL_I2C_DisableSMBusPEC
 |  | LL_I2C_EnableSMBusPEC
 |  | LL_I2C_IsEnabledSMBusPEC
 | RXDMAEN | LL_I2C_DisableDMAReq_RX
 |  | LL_I2C_EnableDMAReq_RX
 |  | LL_I2C_IsEnabledDMAReq_RX
 | RXIE | LL_I2C_DisableIT_RX
 |  | LL_I2C_EnableIT_RX
 |  | LL_I2C_IsEnabledIT_RX
 | SBC | LL_I2C_DisableSlaveByteControl
 |  | LL_I2C_EnableSlaveByteControl
 |  | LL_I2C_IsEnabledSlaveByteControl
 | SMBDEN | LL_I2C_GetMode
 |  | LL_I2C_SetMode
 | SMBHEN | LL_I2C_GetMode
 |  | LL_I2C_SetMode
 | STOPIE | LL_I2C_DisableIT_STOP
 |  | LL_I2C_EnableIT_STOP
 |  | LL_I2C_IsEnabledIT_STOP
 | TCIE | LL_I2C_DisableIT_TC
 |  | LL_I2C_EnableIT_TC
 |  | LL_I2C_IsEnabledIT_TC
 | TXDMAEN | LL_I2C_DisableDMAReq_TX
 |  | LL_I2C_EnableDMAReq_TX
 |  | LL_I2C_IsEnabledDMAReq_TX
 | TXIE | LL_I2C_DisableIT_TX
 |  | LL_I2C_EnableIT_TX
 |  | LL_I2C_IsEnabledIT_TX
 | WUPEN | LL_I2C_DisableWakeUpFromStop
 |  | LL_I2C_EnableWakeUpFromStop
 |  | LL_I2C_IsEnabledWakeUpFromStop
CR2 | ADD10 | LL_I2C_GetMasterAddressingMode
 |  | LL_I2C_HandleTransfer
 |  | LL_I2C_SetMasterAddressingMode
 | AUTOEND | LL_I2C_DisableAutoEndMode
 |  | LL_I2C_EnableAutoEndMode
 |  | LL_I2C_HandleTransfer
 |  | LL_I2C_IsEnabledAutoEndMode
 | HEAD10R | LL_I2C_DisableAuto10BitRead
 |  | LL_I2C_EnableAuto10BitRead
 |  | LL_I2C_HandleTransfer
 |  | LL_I2C_IsEnabledAuto10BitRead
 | NACK | LL_I2C_AcknowledgeNextData
 | NBYTES | LL_I2C_GetTransferSize
 |  | LL_I2C_HandleTransfer
 |  | LL_I2C_SetTransferSize
 | PECBYTE | LL_I2C_EnableSMBusPECCompare
 |  | LL_I2C_IsEnabledSMBusPECCompare
 | RD_WRN | LL_I2C_GetTransferRequest
 |  | LL_I2C_HandleTransfer
 |  | LL_I2C_SetTransferRequest
 | RELOAD | LL_I2C_DisableReloadMode
 |  | LL_I2C_EnableReloadMode
 |  | LL_I2C_HandleTransfer
 |  | LL_I2C_IsEnabledReloadMode
 | SADD | LL_I2C_GetSlaveAddr
 |  | LL_I2C_HandleTransfer
 |  | LL_I2C_SetSlaveAddr
 | START | LL_I2C_GenerateStartCondition
 |  | LL_I2C_HandleTransfer
 | STOP | LL_I2C_GenerateStopCondition
 |  | LL_I2C_HandleTransfer
ICR | ADDRCF | LL_I2C_ClearFlag_ADDR
 | ALERTCF | LL_I2C_ClearSMBusFlag_ALERT
 | ARLOCF | LL_I2C_ClearFlag_ARLO
 | BERRCF | LL_I2C_ClearFlag_BERR
 | NACKCF | LL_I2C_ClearFlag_NACK
 | OVRCF | LL_I2C_ClearFlag_OVR
 | PECCF | LL_I2C_ClearSMBusFlag_PECERR
 | STOPCF | LL_I2C_ClearFlag_STOP
 | TIMOUTCF | LL_I2C_ClearSMBusFlag_TIMEOUT
ISR | ADDCODE | LL_I2C_GetAddressMatchCode
 | ADDR | LL_I2C_IsActiveFlag_ADDR
 | ALERT | LL_I2C_IsActiveSMBusFlag_ALERT
 | ARLO | LL_I2C_IsActiveFlag_ARLO
 | BERR | LL_I2C_IsActiveFlag_BERR
 | BUSY | LL_I2C_IsActiveFlag_BUSY
 | DIR | LL_I2C_GetTransferDirection
 | NACKF | LL_I2C_IsActiveFlag_NACK
 | OVR | LL_I2C_IsActiveFlag_OVR
 | PECERR | LL_I2C_IsActiveSMBusFlag_PECERR
 | RXNE | LL_I2C_IsActiveFlag_RXNE
 | STOPF | LL_I2C_IsActiveFlag_STOP
 | TC | LL_I2C_IsActiveFlag_TC
 | TCR | LL_I2C_IsActiveFlag_TCR
 | TIMEOUT | LL_I2C_IsActiveSMBusFlag_TIMEOUT
 | TXE | LL_I2C_ClearFlag_TXE
 |  | LL_I2C_IsActiveFlag_TXE
 | TXIS | LL_I2C_IsActiveFlag_TXIS
OAR1 | OA1 | LL_I2C_SetOwnAddress1
 | OA1EN | LL_I2C_DisableOwnAddress1
 |  | LL_I2C_EnableOwnAddress1
 |  | LL_I2C_IsEnabledOwnAddress1
 | OA1MODE | LL_I2C_SetOwnAddress1
OAR2 | OA2 | LL_I2C_SetOwnAddress2
 | OA2EN | LL_I2C_DisableOwnAddress2
 |  | LL_I2C_EnableOwnAddress2
 |  | LL_I2C_IsEnabledOwnAddress2
 | OA2MSK | LL_I2C_SetOwnAddress2
PECR | PEC | LL_I2C_GetSMBusPEC
RXDR | RXDATA | LL_I2C_DMA_GetRegAddr
 |  | LL_I2C_ReceiveData8
TIMEOUTR | TEXTEN | LL_I2C_DisableSMBusTimeout
 |  | LL_I2C_EnableSMBusTimeout
 |  | LL_I2C_IsEnabledSMBusTimeout
 | TIDLE | LL_I2C_ConfigSMBusTimeout
 |  | LL_I2C_GetSMBusTimeoutAMode
 |  | LL_I2C_SetSMBusTimeoutAMode
 | TIMEOUTA | LL_I2C_ConfigSMBusTimeout
 |  | LL_I2C_GetSMBusTimeoutA
 |  | LL_I2C_SetSMBusTimeoutA
 | TIMEOUTB | LL_I2C_ConfigSMBusTimeout
 |  | LL_I2C_GetSMBusTimeoutB
 |  | LL_I2C_SetSMBusTimeoutB
 | TIMOUTEN | LL_I2C_DisableSMBusTimeout
 |  | LL_I2C_EnableSMBusTimeout
 |  | LL_I2C_IsEnabledSMBusTimeout
TIMINGR | PRESC | LL_I2C_GetTimingPrescaler
 | SCLDEL | LL_I2C_GetDataSetupTime
 | SCLH | LL_I2C_GetClockHighPeriod
 | SCLL | LL_I2C_GetClockLowPeriod
 | SDADEL | LL_I2C_GetDataHoldTime
 | TIMINGR | LL_I2C_SetTiming
TXDR | TXDATA | LL_I2C_DMA_GetRegAddr
 |  | LL_I2C_TransmitData8
Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: I2C Private Constants

I2C Private Constants
I2C
Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: I2C Private Macros

Defines
I2C Private Macros
I2C

Defines

#define | IS_LL_I2C_PERIPHERAL_MODE(__VALUE__)
#define | IS_LL_I2C_ANALOG_FILTER(__VALUE__)
#define | IS_LL_I2C_DIGITAL_FILTER(__VALUE__) ((__VALUE__) <= 0x0000000FU)
#define | IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU)
#define | IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__)
#define | IS_LL_I2C_OWN_ADDRSIZE(__VALUE__)

Define Documentation

#define IS_LL_I2C_ANALOG_FILTER ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2C_ANALOGFILTER_ENABLE) || \
                                                 ((__VALUE__) == LL_I2C_ANALOGFILTER_DISABLE))

Definition at line 53 of file stm32wbxx_ll_i2c.c.

Referenced by LL_I2C_Init().

#define IS_LL_I2C_DIGITAL_FILTER ( __VALUE__ ) ((__VALUE__) <= 0x0000000FU)

Definition at line 56 of file stm32wbxx_ll_i2c.c.

Referenced by LL_I2C_Init().

#define IS_LL_I2C_OWN_ADDRESS1 ( __VALUE__ ) ((__VALUE__) <= 0x000003FFU)

Definition at line 58 of file stm32wbxx_ll_i2c.c.

Referenced by LL_I2C_Init().

#define IS_LL_I2C_OWN_ADDRSIZE ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \
                                                 ((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT))

Definition at line 63 of file stm32wbxx_ll_i2c.c.

Referenced by LL_I2C_Init().

#define IS_LL_I2C_PERIPHERAL_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2C_MODE_I2C)          || \
                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_HOST)   || \
                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \
                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP))

Definition at line 48 of file stm32wbxx_ll_i2c.c.

Referenced by LL_I2C_Init().

#define IS_LL_I2C_TYPE_ACKNOWLEDGE ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2C_ACK) || \
                                                 ((__VALUE__) == LL_I2C_NACK))

Definition at line 60 of file stm32wbxx_ll_i2c.c.

Referenced by LL_I2C_Init().

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LL_I2C_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_I2C_InitTypeDef Struct Reference
I2C Exported Init structure

#include <stm32wbxx_ll_i2c.h>

Data Fields

uint32_t | PeripheralMode
uint32_t | Timing
uint32_t | AnalogFilter
uint32_t | DigitalFilter
uint32_t | OwnAddress1
uint32_t | TypeAcknowledge
uint32_t | OwnAddrSize

Detailed Description

Definition at line 67 of file stm32wbxx_ll_i2c.h.

Field Documentation

uint32_t LL_I2C_InitTypeDef::AnalogFilter

Enables or disables analog noise filter. This parameter can be a value of Analog Filter Selection

This feature can be modified afterwards using unitary functions LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter().

Definition at line 80 of file stm32wbxx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::DigitalFilter

Configures the digital noise filter. This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F

This feature can be modified afterwards using unitary function LL_I2C_SetDigitalFilter().

Definition at line 85 of file stm32wbxx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::OwnAddress1

Specifies the device own address 1. This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF

This feature can be modified afterwards using unitary function LL_I2C_SetOwnAddress1().

Definition at line 90 of file stm32wbxx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::OwnAddrSize

Specifies the device own address 1 size (7-bit or 10-bit). This parameter can be a value of Own Address 1 Length

This feature can be modified afterwards using unitary function LL_I2C_SetOwnAddress1().

Definition at line 100 of file stm32wbxx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::PeripheralMode

Specifies the peripheral mode. This parameter can be a value of Peripheral Mode

This feature can be modified afterwards using unitary function LL_I2C_SetMode().

Definition at line 69 of file stm32wbxx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::Timing

Specifies the SDA setup, hold time and the SCL high, low period values. This parameter must be set by referring to the STM32CubeMX Tool and the helper macro __LL_I2C_CONVERT_TIMINGS()

This feature can be modified afterwards using unitary function LL_I2C_SetTiming().

Definition at line 74 of file stm32wbxx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::TypeAcknowledge

Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. This parameter can be a value of Acknowledge Generation

This feature can be modified afterwards using unitary function LL_I2C_AcknowledgeNextData().

Definition at line 95 of file stm32wbxx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

The documentation for this struct was generated from the following file:
  • stm32wbxx_ll_i2c.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
I2C Exported Constants

Flags defines which can be used with LL_I2C_WriteReg function. More...

Defines

#define | LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF
#define | LL_I2C_ICR_NACKCF I2C_ICR_NACKCF
#define | LL_I2C_ICR_STOPCF I2C_ICR_STOPCF
#define | LL_I2C_ICR_BERRCF I2C_ICR_BERRCF
#define | LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF
#define | LL_I2C_ICR_OVRCF I2C_ICR_OVRCF
#define | LL_I2C_ICR_PECCF I2C_ICR_PECCF
#define | LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF
#define | LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF

Detailed Description

Flags defines which can be used with LL_I2C_WriteReg function.

Define Documentation

#define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF

Address Matched flag

Definition at line 119 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF

Alert flag

Definition at line 127 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF

Arbitration Lost flag

Definition at line 123 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF

Bus error flag

Definition at line 122 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF

Not Acknowledge flag

Definition at line 120 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF

Overrun/Underrun flag

Definition at line 124 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_ICR_PECCF I2C_ICR_PECCF

PEC error flag

Definition at line 125 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF

Stop detection flag

Definition at line 121 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF

Timeout detection flag

Definition at line 126 of file stm32wbxx_ll_i2c.h.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
I2C Exported Constants

Flags defines which can be used with LL_I2C_ReadReg function. More...

Defines

#define | LL_I2C_ISR_TXE I2C_ISR_TXE
#define | LL_I2C_ISR_TXIS I2C_ISR_TXIS
#define | LL_I2C_ISR_RXNE I2C_ISR_RXNE
#define | LL_I2C_ISR_ADDR I2C_ISR_ADDR
#define | LL_I2C_ISR_NACKF I2C_ISR_NACKF
#define | LL_I2C_ISR_STOPF I2C_ISR_STOPF
#define | LL_I2C_ISR_TC I2C_ISR_TC
#define | LL_I2C_ISR_TCR I2C_ISR_TCR
#define | LL_I2C_ISR_BERR I2C_ISR_BERR
#define | LL_I2C_ISR_ARLO I2C_ISR_ARLO
#define | LL_I2C_ISR_OVR I2C_ISR_OVR
#define | LL_I2C_ISR_PECERR I2C_ISR_PECERR
#define | LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT
#define | LL_I2C_ISR_ALERT I2C_ISR_ALERT
#define | LL_I2C_ISR_BUSY I2C_ISR_BUSY

Detailed Description

Flags defines which can be used with LL_I2C_ReadReg function.

Define Documentation

#define LL_I2C_ISR_ADDR I2C_ISR_ADDR

Address matched (slave mode)

Definition at line 139 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_ISR_ALERT I2C_ISR_ALERT

SMBus alert (SMBus mode)

Definition at line 149 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_ISR_ARLO I2C_ISR_ARLO

Arbitration lost

Definition at line 145 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_ISR_BERR I2C_ISR_BERR

Bus error

Definition at line 144 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_ISR_BUSY I2C_ISR_BUSY

Bus busy

Definition at line 150 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_ISR_NACKF I2C_ISR_NACKF

Not Acknowledge received flag

Definition at line 140 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_ISR_OVR I2C_ISR_OVR

Overrun/Underrun (slave mode)

Definition at line 146 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_ISR_PECERR I2C_ISR_PECERR

PEC Error in reception (SMBus mode)

Definition at line 147 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_ISR_RXNE I2C_ISR_RXNE

Receive data register not empty

Definition at line 138 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_ISR_STOPF I2C_ISR_STOPF

Stop detection flag

Definition at line 141 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_ISR_TC I2C_ISR_TC

Transfer Complete (master mode)

Definition at line 142 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_ISR_TCR I2C_ISR_TCR

Transfer Complete Reload

Definition at line 143 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT

Timeout detection flag (SMBus mode)

Definition at line 148 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_ISR_TXE I2C_ISR_TXE

Transmit data register empty

Definition at line 136 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_ISR_TXIS I2C_ISR_TXIS

Transmit interrupt status

Definition at line 137 of file stm32wbxx_ll_i2c.h.

Generated on Fri Sep 6 2019 11:34:50 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IT Defines

Defines
IT Defines
I2C Exported Constants

IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions. More...

Defines

#define | LL_I2C_CR1_TXIE I2C_CR1_TXIE
#define | LL_I2C_CR1_RXIE I2C_CR1_RXIE
#define | LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE
#define | LL_I2C_CR1_NACKIE I2C_CR1_NACKIE
#define | LL_I2C_CR1_STOPIE I2C_CR1_STOPIE
#define | LL_I2C_CR1_TCIE I2C_CR1_TCIE
#define | LL_I2C_CR1_ERRIE I2C_CR1_ERRIE

Detailed Description

IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions.

Define Documentation

#define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE

Address match Interrupt enable (slave only)

Definition at line 161 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE

Error interrupts enable

Definition at line 165 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE

Not acknowledge received Interrupt enable

Definition at line 162 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_CR1_RXIE I2C_CR1_RXIE

RX Interrupt enable

Definition at line 160 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE

STOP detection Interrupt enable

Definition at line 163 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_CR1_TCIE I2C_CR1_TCIE

Transfer Complete interrupt enable

Definition at line 164 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_CR1_TXIE I2C_CR1_TXIE

TX Interrupt enable

Definition at line 159 of file stm32wbxx_ll_i2c.h.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Peripheral Mode

Defines
Peripheral Mode
I2C Exported Constants

Defines

#define | LL_I2C_MODE_I2C 0x00000000U
#define | LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN
#define | LL_I2C_MODE_SMBUS_DEVICE 0x00000000U
#define | LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN

Define Documentation

#define LL_I2C_MODE_I2C 0x00000000U

I2C Master or Slave mode

Definition at line 173 of file stm32wbxx_ll_i2c.h.

Referenced by LL_I2C_StructInit().

#define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U

SMBus Device default mode (Default address not acknowledge)

Definition at line 175 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN

SMBus Device Default address acknowledge

Definition at line 176 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN

SMBus Host address acknowledge

Definition at line 174 of file stm32wbxx_ll_i2c.h.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Analog Filter Selection

Defines
Analog Filter Selection
I2C Exported Constants

Defines

#define | LL_I2C_ANALOGFILTER_ENABLE 0x00000000U
#define | LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Define Documentation

#define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Analog filter is disabled.

Definition at line 185 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U

Analog filter is enabled.

Definition at line 184 of file stm32wbxx_ll_i2c.h.

Referenced by LL_I2C_StructInit().

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Master Addressing Mode

Defines
Master Addressing Mode
I2C Exported Constants

Defines

#define | LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U
#define | LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10

Define Documentation

#define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10

Master operates in 10-bit addressing mode.

Definition at line 194 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U

Master operates in 7-bit addressing mode.

Definition at line 193 of file stm32wbxx_ll_i2c.h.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Own Address 1 Length

Defines
Own Address 1 Length
I2C Exported Constants

Defines

#define | LL_I2C_OWNADDRESS1_7BIT 0x00000000U
#define | LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE

Define Documentation

#define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE

Own address 1 is a 10-bit address.

Definition at line 203 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_OWNADDRESS1_7BIT 0x00000000U

Own address 1 is a 7-bit address.

Definition at line 202 of file stm32wbxx_ll_i2c.h.

Referenced by LL_I2C_StructInit().

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Own Address 2 Masks

Defines
Own Address 2 Masks
I2C Exported Constants

Defines

#define | LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK
#define | LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01
#define | LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02
#define | LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03
#define | LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04
#define | LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05
#define | LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06
#define | LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07

Define Documentation

#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01

Only Address2 bits[7:2] are compared.

Definition at line 212 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02

Only Address2 bits[7:3] are compared.

Definition at line 213 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03

Only Address2 bits[7:4] are compared.

Definition at line 214 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04

Only Address2 bits[7:5] are compared.

Definition at line 215 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05

Only Address2 bits[7:6] are compared.

Definition at line 216 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06

Only Address2 bits[7] are compared.

Definition at line 217 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07

No comparison is done. All Address2 are acknowledged.

Definition at line 218 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK

Own Address2 No mask.

Definition at line 211 of file stm32wbxx_ll_i2c.h.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Acknowledge Generation

Defines
Acknowledge Generation
I2C Exported Constants

Defines

#define | LL_I2C_ACK 0x00000000U
#define | LL_I2C_NACK I2C_CR2_NACK

Define Documentation

#define LL_I2C_ACK 0x00000000U

ACK is sent after current received byte.

Definition at line 226 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_NACK I2C_CR2_NACK

NACK is sent after current received byte.

Definition at line 227 of file stm32wbxx_ll_i2c.h.

Referenced by LL_I2C_StructInit().

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STM32WB55xx HAL User Manual: Slave Address Length

Defines
Slave Address Length
I2C Exported Constants

Defines

#define | LL_I2C_ADDRSLAVE_7BIT 0x00000000U
#define | LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10

Define Documentation

#define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10

Slave Address in 10-bit.

Definition at line 236 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_ADDRSLAVE_7BIT 0x00000000U

Slave Address in 7-bit.

Definition at line 235 of file stm32wbxx_ll_i2c.h.

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STM32WB55xx HAL User Manual: Transfer Request Direction

Defines
Transfer Request Direction
I2C Exported Constants

Defines

#define | LL_I2C_REQUEST_WRITE 0x00000000U
#define | LL_I2C_REQUEST_READ I2C_CR2_RD_WRN

Define Documentation

#define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN

Master request a read transfer.

Definition at line 245 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_REQUEST_WRITE 0x00000000U

Master request a write transfer.

Definition at line 244 of file stm32wbxx_ll_i2c.h.

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STM32WB55xx HAL User Manual: Transfer End Mode

Defines
Transfer End Mode
I2C Exported Constants

Defines

#define | LL_I2C_MODE_RELOAD I2C_CR2_RELOAD
#define | LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND
#define | LL_I2C_MODE_SOFTEND 0x00000000U
#define | LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD
#define | LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND
#define | LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND
#define | LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)
#define | LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)

Define Documentation

#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND

Enable I2C Automatic end mode with no HW PEC comparison.

Definition at line 254 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD

Enable I2C Reload mode.

Definition at line 253 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND

Enable SMBUS Automatic end mode with HW PEC comparison.

Definition at line 257 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)

Enable SMBUS Automatic end mode with HW PEC comparison.

Definition at line 259 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD

Enable SMBUS Automatic end mode with HW PEC comparison.

Definition at line 256 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND

Enable SMBUS Software end mode with HW PEC comparison.

Definition at line 258 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)

Enable SMBUS Software end mode with HW PEC comparison.

Definition at line 260 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_MODE_SOFTEND 0x00000000U

Enable I2C Software end mode with no HW PEC comparison.

Definition at line 255 of file stm32wbxx_ll_i2c.h.

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STM32WB55xx HAL User Manual: Start And Stop Generation

Defines
Start And Stop Generation
I2C Exported Constants

Defines

#define | LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U
#define | LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define | LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define | LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
#define | LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define | LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
#define | LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)
#define | LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)

Define Documentation

#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U

Don't Generate Stop and Start condition.

Definition at line 268 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)

Generate Restart for read request, slave 10Bit address.

Definition at line 274 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)

Generate Restart for write request, slave 10Bit address.

Definition at line 275 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)

Generate Restart for read request, slave 7Bit address.

Definition at line 272 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)

Generate Restart for write request, slave 7Bit address.

Definition at line 273 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)

Generate Start for read request.

Definition at line 270 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)

Generate Start for write request.

Definition at line 271 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)

Generate Stop condition (Size should be set to 0).

Definition at line 269 of file stm32wbxx_ll_i2c.h.

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STM32WB55xx HAL User Manual: Read Write Direction

Defines
Read Write Direction
I2C Exported Constants

Defines

#define | LL_I2C_DIRECTION_WRITE 0x00000000U
#define | LL_I2C_DIRECTION_READ I2C_ISR_DIR

Define Documentation

#define LL_I2C_DIRECTION_READ I2C_ISR_DIR

Read transfer request by master, slave enters transmitter mode.

Definition at line 284 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_DIRECTION_WRITE 0x00000000U

Write transfer request by master, slave enters receiver mode.

Definition at line 283 of file stm32wbxx_ll_i2c.h.

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STM32WB55xx HAL User Manual: DMA Register Data

Defines
DMA Register Data
I2C Exported Constants

Defines

#define | LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U
#define | LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U

Define Documentation

#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U

Get address of data register used for reception

Definition at line 293 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U

Get address of data register used for transmission

Definition at line 292 of file stm32wbxx_ll_i2c.h.

Referenced by LL_I2C_DMA_GetRegAddr().

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STM32WB55xx HAL User Manual: SMBus TimeoutA Mode SCL SDA Timeout

Defines
SMBus TimeoutA Mode SCL SDA Timeout
I2C Exported Constants

Defines

#define | LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U
#define | LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE

Define Documentation

#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U

TimeoutA is used to detect SCL low level timeout.

Definition at line 301 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE

TimeoutA is used to detect both SCL and SDA high level timeout.

Definition at line 302 of file stm32wbxx_ll_i2c.h.

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STM32WB55xx HAL User Manual: SMBus Timeout Selection

Defines
SMBus Timeout Selection
I2C Exported Constants

Defines

#define | LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN
#define | LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN
#define | LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)

Define Documentation

#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)

TimeoutA and TimeoutB (extended clock) enable bits

Definition at line 312 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN

TimeoutA enable bit

Definition at line 310 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN

TimeoutB (extended clock) enable bit

Definition at line 311 of file stm32wbxx_ll_i2c.h.

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STM32WB55xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
I2C Exported Macros

Defines

#define | LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in I2C register.
#define | LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in I2C register.

Define Documentation

#define LL_I2C_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in I2C register.

Parameters:
__INSTANCE__ | I2C Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 345 of file stm32wbxx_ll_i2c.h.

#define LL_I2C_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in I2C register.

Parameters:
__INSTANCE__ | I2C Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 337 of file stm32wbxx_ll_i2c.h.

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STM32WB55xx HAL User Manual: Convert SDA SCL timings

Defines
Convert SDA SCL timings
I2C Exported Macros

Defines

#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__)
Configure the SDA setup, hold time and the SCL high, low period.

Define Documentation

#define __LL_I2C_CONVERT_TIMINGS | ( | __PRESCALER__,
 |  | __DATA_SETUP_TIME__,
 |  | __DATA_HOLD_TIME__,
 |  | __CLOCK_HIGH_PERIOD__,
 |  | __CLOCK_LOW_PERIOD__
 | ) |
Value:
((((uint32_t)(__PRESCALER__)         << I2C_TIMINGR_PRESC_Pos)  & I2C_TIMINGR_PRESC)   | \
         (((uint32_t)(__DATA_SETUP_TIME__)   << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL)  | \
         (((uint32_t)(__DATA_HOLD_TIME__)    << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL)  | \
         (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos)   & I2C_TIMINGR_SCLH)    | \
         (((uint32_t)(__CLOCK_LOW_PERIOD__)  << I2C_TIMINGR_SCLL_Pos)   & I2C_TIMINGR_SCLL))

Configure the SDA setup, hold time and the SCL high, low period.

Parameters:
__PRESCALER__ | This parameter must be a value between Min_Data=0 and Max_Data=0xF.
__DATA_SETUP_TIME__ | This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc)
__DATA_HOLD_TIME__ | This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc)
__CLOCK_HIGH_PERIOD__ | This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc)
__CLOCK_LOW_PERIOD__ | This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc)
Return values:
Value between Min_Data=0 and Max_Data=0xFFFFFFFF

Definition at line 362 of file stm32wbxx_ll_i2c.h.

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STM32WB55xx HAL User Manual: Configuration

Functions
Configuration
I2C Exported Functions

Functions

__STATIC_INLINE void | LL_I2C_Enable (I2C_TypeDef *I2Cx)
Enable I2C peripheral (PE = 1).
__STATIC_INLINE void | LL_I2C_Disable (I2C_TypeDef *I2Cx)
Disable I2C peripheral (PE = 0).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabled (I2C_TypeDef *I2Cx)
Check if the I2C peripheral is enabled or disabled.
__STATIC_INLINE void | LL_I2C_ConfigFilters (I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
Configure Noise Filters (Analog and Digital).
__STATIC_INLINE void | LL_I2C_SetDigitalFilter (I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
Configure Digital Noise Filter.
__STATIC_INLINE uint32_t | LL_I2C_GetDigitalFilter (I2C_TypeDef *I2Cx)
Get the current Digital Noise Filter configuration.
__STATIC_INLINE void | LL_I2C_EnableAnalogFilter (I2C_TypeDef *I2Cx)
Enable Analog Noise Filter.
__STATIC_INLINE void | LL_I2C_DisableAnalogFilter (I2C_TypeDef *I2Cx)
Disable Analog Noise Filter.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledAnalogFilter (I2C_TypeDef *I2Cx)
Check if Analog Noise Filter is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableDMAReq_TX (I2C_TypeDef *I2Cx)
Enable DMA transmission requests.
__STATIC_INLINE void | LL_I2C_DisableDMAReq_TX (I2C_TypeDef *I2Cx)
Disable DMA transmission requests.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledDMAReq_TX (I2C_TypeDef *I2Cx)
Check if DMA transmission requests are enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableDMAReq_RX (I2C_TypeDef *I2Cx)
Enable DMA reception requests.
__STATIC_INLINE void | LL_I2C_DisableDMAReq_RX (I2C_TypeDef *I2Cx)
Disable DMA reception requests.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledDMAReq_RX (I2C_TypeDef *I2Cx)
Check if DMA reception requests are enabled or disabled.
__STATIC_INLINE uint32_t | LL_I2C_DMA_GetRegAddr (I2C_TypeDef *I2Cx, uint32_t Direction)
Get the data register address used for DMA transfer.
__STATIC_INLINE void | LL_I2C_EnableClockStretching (I2C_TypeDef *I2Cx)
Enable Clock stretching.
__STATIC_INLINE void | LL_I2C_DisableClockStretching (I2C_TypeDef *I2Cx)
Disable Clock stretching.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledClockStretching (I2C_TypeDef *I2Cx)
Check if Clock stretching is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableSlaveByteControl (I2C_TypeDef *I2Cx)
Enable hardware byte control in slave mode.
__STATIC_INLINE void | LL_I2C_DisableSlaveByteControl (I2C_TypeDef *I2Cx)
Disable hardware byte control in slave mode.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSlaveByteControl (I2C_TypeDef *I2Cx)
Check if hardware byte control in slave mode is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableWakeUpFromStop (I2C_TypeDef *I2Cx)
Enable Wakeup from STOP.
__STATIC_INLINE void | LL_I2C_DisableWakeUpFromStop (I2C_TypeDef *I2Cx)
Disable Wakeup from STOP.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledWakeUpFromStop (I2C_TypeDef *I2Cx)
Check if Wakeup from STOP is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableGeneralCall (I2C_TypeDef *I2Cx)
Enable General Call.
__STATIC_INLINE void | LL_I2C_DisableGeneralCall (I2C_TypeDef *I2Cx)
Disable General Call.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledGeneralCall (I2C_TypeDef *I2Cx)
Check if General Call is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetMasterAddressingMode (I2C_TypeDef *I2Cx, uint32_t AddressingMode)
Configure the Master to operate in 7-bit or 10-bit addressing mode.
__STATIC_INLINE uint32_t | LL_I2C_GetMasterAddressingMode (I2C_TypeDef *I2Cx)
Get the Master addressing mode.
__STATIC_INLINE void | LL_I2C_SetOwnAddress1 (I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
Set the Own Address1.
__STATIC_INLINE void | LL_I2C_EnableOwnAddress1 (I2C_TypeDef *I2Cx)
Enable acknowledge on Own Address1 match address.
__STATIC_INLINE void | LL_I2C_DisableOwnAddress1 (I2C_TypeDef *I2Cx)
Disable acknowledge on Own Address1 match address.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledOwnAddress1 (I2C_TypeDef *I2Cx)
Check if Own Address1 acknowledge is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetOwnAddress2 (I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
Set the 7bits Own Address2.
__STATIC_INLINE void | LL_I2C_EnableOwnAddress2 (I2C_TypeDef *I2Cx)
Enable acknowledge on Own Address2 match address.
__STATIC_INLINE void | LL_I2C_DisableOwnAddress2 (I2C_TypeDef *I2Cx)
Disable acknowledge on Own Address2 match address.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledOwnAddress2 (I2C_TypeDef *I2Cx)
Check if Own Address1 acknowledge is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetTiming (I2C_TypeDef *I2Cx, uint32_t Timing)
Configure the SDA setup, hold time and the SCL high, low period.
__STATIC_INLINE uint32_t | LL_I2C_GetTimingPrescaler (I2C_TypeDef *I2Cx)
Get the Timing Prescaler setting.
__STATIC_INLINE uint32_t | LL_I2C_GetClockLowPeriod (I2C_TypeDef *I2Cx)
Get the SCL low period setting.
__STATIC_INLINE uint32_t | LL_I2C_GetClockHighPeriod (I2C_TypeDef *I2Cx)
Get the SCL high period setting.
__STATIC_INLINE uint32_t | LL_I2C_GetDataHoldTime (I2C_TypeDef *I2Cx)
Get the SDA hold time.
__STATIC_INLINE uint32_t | LL_I2C_GetDataSetupTime (I2C_TypeDef *I2Cx)
Get the SDA setup time.
__STATIC_INLINE void | LL_I2C_SetMode (I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
Configure peripheral mode.
__STATIC_INLINE uint32_t | LL_I2C_GetMode (I2C_TypeDef *I2Cx)
Get peripheral mode.
__STATIC_INLINE void | LL_I2C_EnableSMBusAlert (I2C_TypeDef *I2Cx)
Enable SMBus alert (Host or Device mode)
__STATIC_INLINE void | LL_I2C_DisableSMBusAlert (I2C_TypeDef *I2Cx)
Disable SMBus alert (Host or Device mode)
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusAlert (I2C_TypeDef *I2Cx)
Check if SMBus alert (Host or Device mode) is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableSMBusPEC (I2C_TypeDef *I2Cx)
Enable SMBus Packet Error Calculation (PEC).
__STATIC_INLINE void | LL_I2C_DisableSMBusPEC (I2C_TypeDef *I2Cx)
Disable SMBus Packet Error Calculation (PEC).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusPEC (I2C_TypeDef *I2Cx)
Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
__STATIC_INLINE void | LL_I2C_ConfigSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode, uint32_t TimeoutB)
Configure the SMBus Clock Timeout.
__STATIC_INLINE void | LL_I2C_SetSMBusTimeoutA (I2C_TypeDef *I2Cx, uint32_t TimeoutA)
Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusTimeoutA (I2C_TypeDef *I2Cx)
Get the SMBus Clock TimeoutA setting.
__STATIC_INLINE void | LL_I2C_SetSMBusTimeoutAMode (I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
Set the SMBus Clock TimeoutA mode.
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusTimeoutAMode (I2C_TypeDef *I2Cx)
Get the SMBus Clock TimeoutA mode.
__STATIC_INLINE void | LL_I2C_SetSMBusTimeoutB (I2C_TypeDef *I2Cx, uint32_t TimeoutB)
Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusTimeoutB (I2C_TypeDef *I2Cx)
Get the SMBus Extented Cumulative Clock TimeoutB setting.
__STATIC_INLINE void | LL_I2C_EnableSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
Enable the SMBus Clock Timeout.
__STATIC_INLINE void | LL_I2C_DisableSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
Disable the SMBus Clock Timeout.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
Check if the SMBus Clock Timeout is enabled or disabled.

Function Documentation

__STATIC_INLINE void LL_I2C_ConfigFilters | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | AnalogFilter,
 |  | uint32_t | DigitalFilter
 | ) |  |

Configure Noise Filters (Analog and Digital).

Note:
If the analog filter is also enabled, the digital filter is added to analog filter. The filters can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CR1 ANFOFF LL_I2C_ConfigFilters
CR1 DNF LL_I2C_ConfigFilters
Parameters:
I2Cx | I2C Instance.
AnalogFilter This parameter can be one of the following values:
  • LL_I2C_ANALOGFILTER_ENABLE
  • LL_I2C_ANALOGFILTER_DISABLE
DigitalFilter | This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). This parameter is used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
Return values:
None

Definition at line 436 of file stm32wbxx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TimeoutA,
 |  | uint32_t | TimeoutAMode,
 |  | uint32_t | TimeoutB
 | ) |  |

Configure the SMBus Clock Timeout.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
Reference Manual to LL API cross reference:
TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout
TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout
TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout
Parameters:
I2Cx | I2C Instance.
TimeoutA | This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
TimeoutAMode This parameter can be one of the following values:
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
TimeoutB
Return values:
None

Definition at line 1083 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_Disable ( I2C_TypeDef * I2Cx )

Disable I2C peripheral (PE = 0).

Note:
When PE = 0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles.
Reference Manual to LL API cross reference:
CR1 PE LL_I2C_Disable
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 405 of file stm32wbxx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_DisableAnalogFilter ( I2C_TypeDef * I2Cx )

Disable Analog Noise Filter.

Note:
This filter can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CR1 ANFOFF LL_I2C_DisableAnalogFilter
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 487 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableClockStretching ( I2C_TypeDef * I2Cx )

Disable Clock stretching.

Note:
This bit can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CR1 NOSTRETCH LL_I2C_DisableClockStretching
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 616 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableDMAReq_RX ( I2C_TypeDef * I2Cx )

Disable DMA reception requests.

Reference Manual to LL API cross reference:
CR1 RXDMAEN LL_I2C_DisableDMAReq_RX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 553 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableDMAReq_TX ( I2C_TypeDef * I2Cx )

Disable DMA transmission requests.

Reference Manual to LL API cross reference:
CR1 TXDMAEN LL_I2C_DisableDMAReq_TX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 520 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableGeneralCall ( I2C_TypeDef * I2Cx )

Disable General Call.

Note:
When disabled the Address 0x00 is NACKed.
Reference Manual to LL API cross reference:
CR1 GCEN LL_I2C_DisableGeneralCall
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 724 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableOwnAddress1 ( I2C_TypeDef * I2Cx )

Disable acknowledge on Own Address1 match address.

Reference Manual to LL API cross reference:
OAR1 OA1EN LL_I2C_DisableOwnAddress1
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 801 of file stm32wbxx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_DisableOwnAddress2 ( I2C_TypeDef * I2Cx )

Disable acknowledge on Own Address2 match address.

Reference Manual to LL API cross reference:
OAR2 OA2EN LL_I2C_DisableOwnAddress2
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 857 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableSlaveByteControl ( I2C_TypeDef * I2Cx )

Disable hardware byte control in slave mode.

Reference Manual to LL API cross reference:
CR1 SBC LL_I2C_DisableSlaveByteControl
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 649 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableSMBusAlert ( I2C_TypeDef * I2Cx )

Disable SMBus alert (Host or Device mode)

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
SMBus Device mode:
  • SMBus Alert pin is not drived (can be used as a standard GPIO) and Alert Response Address Header acknowledge is disabled. SMBus Host mode:
  • SMBus Alert pin management is not supported.
Reference Manual to LL API cross reference:
CR1 ALERTEN LL_I2C_DisableSMBusAlert
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1010 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableSMBusPEC ( I2C_TypeDef * I2Cx )

Disable SMBus Packet Error Calculation (PEC).

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 PECEN LL_I2C_DisableSMBusPEC
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1049 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableSMBusTimeout | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | ClockTimeout
 | ) |  |

Disable the SMBus Clock Timeout.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout
TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout
Parameters:
I2Cx I2C Instance.
ClockTimeout This parameter can be one of the following values:
  • LL_I2C_SMBUS_TIMEOUTA
  • LL_I2C_SMBUS_TIMEOUTB
  • LL_I2C_SMBUS_ALL_TIMEOUT
Return values:
None

Definition at line 1209 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableWakeUpFromStop ( I2C_TypeDef * I2Cx )

Disable Wakeup from STOP.

Note:
Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not WakeUpFromStop feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 WUPEN LL_I2C_DisableWakeUpFromStop
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 687 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | Direction
 | ) |  |

Get the data register address used for DMA transfer.

Reference Manual to LL API cross reference:
TXDR TXDATA LL_I2C_DMA_GetRegAddr
RXDR RXDATA LL_I2C_DMA_GetRegAddr
Parameters:
I2Cx I2C Instance
Direction This parameter can be one of the following values:
  • LL_I2C_DMA_REG_DATA_TRANSMIT
  • LL_I2C_DMA_REG_DATA_RECEIVE
Return values:
Address of data register

Definition at line 579 of file stm32wbxx_ll_i2c.h.

References LL_I2C_DMA_REG_DATA_TRANSMIT.

__STATIC_INLINE void LL_I2C_Enable ( I2C_TypeDef * I2Cx )

Enable I2C peripheral (PE = 1).

Reference Manual to LL API cross reference:
CR1 PE LL_I2C_Enable
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 391 of file stm32wbxx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_EnableAnalogFilter ( I2C_TypeDef * I2Cx )

Enable Analog Noise Filter.

Note:
This filter can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CR1 ANFOFF LL_I2C_EnableAnalogFilter
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 475 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableClockStretching ( I2C_TypeDef * I2Cx )

Enable Clock stretching.

Note:
This bit can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CR1 NOSTRETCH LL_I2C_EnableClockStretching
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 604 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableDMAReq_RX ( I2C_TypeDef * I2Cx )

Enable DMA reception requests.

Reference Manual to LL API cross reference:
CR1 RXDMAEN LL_I2C_EnableDMAReq_RX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 542 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableDMAReq_TX ( I2C_TypeDef * I2Cx )

Enable DMA transmission requests.

Reference Manual to LL API cross reference:
CR1 TXDMAEN LL_I2C_EnableDMAReq_TX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 509 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableGeneralCall ( I2C_TypeDef * I2Cx )

Enable General Call.

Note:
When enabled the Address 0x00 is ACKed.
Reference Manual to LL API cross reference:
CR1 GCEN LL_I2C_EnableGeneralCall
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 712 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableOwnAddress1 ( I2C_TypeDef * I2Cx )

Enable acknowledge on Own Address1 match address.

Reference Manual to LL API cross reference:
OAR1 OA1EN LL_I2C_EnableOwnAddress1
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 790 of file stm32wbxx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_EnableOwnAddress2 ( I2C_TypeDef * I2Cx )

Enable acknowledge on Own Address2 match address.

Reference Manual to LL API cross reference:
OAR2 OA2EN LL_I2C_EnableOwnAddress2
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 846 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableSlaveByteControl ( I2C_TypeDef * I2Cx )

Enable hardware byte control in slave mode.

Reference Manual to LL API cross reference:
CR1 SBC LL_I2C_EnableSlaveByteControl
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 638 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableSMBusAlert ( I2C_TypeDef * I2Cx )

Enable SMBus alert (Host or Device mode)

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
SMBus Device mode:
  • SMBus Alert pin is drived low and Alert Response Address Header acknowledge is enabled. SMBus Host mode:
  • SMBus Alert pin management is supported.
Reference Manual to LL API cross reference:
CR1 ALERTEN LL_I2C_EnableSMBusAlert
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 992 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableSMBusPEC ( I2C_TypeDef * I2Cx )

Enable SMBus Packet Error Calculation (PEC).

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 PECEN LL_I2C_EnableSMBusPEC
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1036 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableSMBusTimeout | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | ClockTimeout
 | ) |  |

Enable the SMBus Clock Timeout.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout
TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout
Parameters:
I2Cx I2C Instance.
ClockTimeout This parameter can be one of the following values:
  • LL_I2C_SMBUS_TIMEOUTA
  • LL_I2C_SMBUS_TIMEOUTB
  • LL_I2C_SMBUS_ALL_TIMEOUT
Return values:
None

Definition at line 1191 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableWakeUpFromStop ( I2C_TypeDef * I2Cx )

Enable Wakeup from STOP.

Note:
Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not WakeUpFromStop feature is supported by the I2Cx Instance.
This bit can only be programmed when Digital Filter is disabled.
Reference Manual to LL API cross reference:
CR1 WUPEN LL_I2C_EnableWakeUpFromStop
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 674 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod ( I2C_TypeDef * I2Cx )

Get the SCL high period setting.

Reference Manual to LL API cross reference:
TIMINGR SCLH LL_I2C_GetClockHighPeriod
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 915 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod ( I2C_TypeDef * I2Cx )

Get the SCL low period setting.

Reference Manual to LL API cross reference:
TIMINGR SCLL LL_I2C_GetClockLowPeriod
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 904 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime ( I2C_TypeDef * I2Cx )

Get the SDA hold time.

Reference Manual to LL API cross reference:
TIMINGR SDADEL LL_I2C_GetDataHoldTime
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x0 and Max_Data=0xF

Definition at line 926 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime ( I2C_TypeDef * I2Cx )

Get the SDA setup time.

Reference Manual to LL API cross reference:
TIMINGR SCLDEL LL_I2C_GetDataSetupTime
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x0 and Max_Data=0xF

Definition at line 937 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter ( I2C_TypeDef * I2Cx )

Get the current Digital Noise Filter configuration.

Reference Manual to LL API cross reference:
CR1 DNF LL_I2C_GetDigitalFilter
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x0 and Max_Data=0xF

Definition at line 463 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode ( I2C_TypeDef * I2Cx )

Get the Master addressing mode.

Reference Manual to LL API cross reference:
CR2 ADD10 LL_I2C_GetMasterAddressingMode
Parameters:
I2Cx I2C Instance.
Return values:
Returned value can be one of the following values:
  • LL_I2C_ADDRESSING_MODE_7BIT
  • LL_I2C_ADDRESSING_MODE_10BIT

Definition at line 763 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetMode ( I2C_TypeDef * I2Cx )

Get peripheral mode.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 SMBHEN LL_I2C_GetMode
CR1 SMBDEN LL_I2C_GetMode
Parameters:
I2Cx I2C Instance.
Return values:
Returned value can be one of the following values:
  • LL_I2C_MODE_I2C
  • LL_I2C_MODE_SMBUS_HOST
  • LL_I2C_MODE_SMBUS_DEVICE
  • LL_I2C_MODE_SMBUS_DEVICE_ARP

Definition at line 974 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA ( I2C_TypeDef * I2Cx )

Get the SMBus Clock TimeoutA setting.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0 and Max_Data=0xFFF

Definition at line 1113 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode ( I2C_TypeDef * I2Cx )

Get the SMBus Clock TimeoutA mode.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode
Parameters:
I2Cx I2C Instance.
Return values:
Returned value can be one of the following values:
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH

Definition at line 1145 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB ( I2C_TypeDef * I2Cx )

Get the SMBus Extented Cumulative Clock TimeoutB setting.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0 and Max_Data=0xFFF

Definition at line 1173 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler ( I2C_TypeDef * I2Cx )

Get the Timing Prescaler setting.

Reference Manual to LL API cross reference:
TIMINGR PRESC LL_I2C_GetTimingPrescaler
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x0 and Max_Data=0xF

Definition at line 893 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabled ( I2C_TypeDef * I2Cx )

Check if the I2C peripheral is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 PE LL_I2C_IsEnabled
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 416 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter ( I2C_TypeDef * I2Cx )

Check if Analog Noise Filter is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 498 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching ( I2C_TypeDef * I2Cx )

Check if Clock stretching is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 627 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX ( I2C_TypeDef * I2Cx )

Check if DMA reception requests are enabled or disabled.

Reference Manual to LL API cross reference:
CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 564 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX ( I2C_TypeDef * I2Cx )

Check if DMA transmission requests are enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 531 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall ( I2C_TypeDef * I2Cx )

Check if General Call is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 GCEN LL_I2C_IsEnabledGeneralCall
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 735 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1 ( I2C_TypeDef * I2Cx )

Check if Own Address1 acknowledge is enabled or disabled.

Reference Manual to LL API cross reference:
OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 812 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2 ( I2C_TypeDef * I2Cx )

Check if Own Address1 acknowledge is enabled or disabled.

Reference Manual to LL API cross reference:
OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 868 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl ( I2C_TypeDef * I2Cx )

Check if hardware byte control in slave mode is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 SBC LL_I2C_IsEnabledSlaveByteControl
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 660 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert ( I2C_TypeDef * I2Cx )

Check if SMBus alert (Host or Device mode) is enabled or disabled.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1023 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC ( I2C_TypeDef * I2Cx )

Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 PECEN LL_I2C_IsEnabledSMBusPEC
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1062 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | ClockTimeout
 | ) |  |

Check if the SMBus Clock Timeout is enabled or disabled.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout
TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout
Parameters:
I2Cx I2C Instance.
ClockTimeout This parameter can be one of the following values:
  • LL_I2C_SMBUS_TIMEOUTA
  • LL_I2C_SMBUS_TIMEOUTB
  • LL_I2C_SMBUS_ALL_TIMEOUT
Return values:
State of bit (1 or 0).

Definition at line 1227 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop ( I2C_TypeDef * I2Cx )

Check if Wakeup from STOP is enabled or disabled.

Note:
Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not WakeUpFromStop feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 700 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetDigitalFilter | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | DigitalFilter
 | ) |  |

Configure Digital Noise Filter.

Note:
If the analog filter is also enabled, the digital filter is added to analog filter. This filter can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CR1 DNF LL_I2C_SetDigitalFilter
Parameters:
I2Cx | I2C Instance.
DigitalFilter | This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). This parameter is used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
Return values:
None

Definition at line 452 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetMasterAddressingMode | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | AddressingMode
 | ) |  |

Configure the Master to operate in 7-bit or 10-bit addressing mode.

Note:
Changing this bit is not allowed, when the START bit is set.
Reference Manual to LL API cross reference:
CR2 ADD10 LL_I2C_SetMasterAddressingMode
Parameters:
I2Cx I2C Instance.
AddressingMode This parameter can be one of the following values:
  • LL_I2C_ADDRESSING_MODE_7BIT
  • LL_I2C_ADDRESSING_MODE_10BIT
Return values:
None

Definition at line 750 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetMode | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | PeripheralMode
 | ) |  |

Configure peripheral mode.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 SMBHEN LL_I2C_SetMode
CR1 SMBDEN LL_I2C_SetMode
Parameters:
I2Cx I2C Instance.
PeripheralMode This parameter can be one of the following values:
  • LL_I2C_MODE_I2C
  • LL_I2C_MODE_SMBUS_HOST
  • LL_I2C_MODE_SMBUS_DEVICE
  • LL_I2C_MODE_SMBUS_DEVICE_ARP
Return values:
None

Definition at line 956 of file stm32wbxx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_SetOwnAddress1 | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | OwnAddress1,
 |  | uint32_t | OwnAddrSize
 | ) |  |

Set the Own Address1.

Reference Manual to LL API cross reference:
OAR1 OA1 LL_I2C_SetOwnAddress1
OAR1 OA1MODE LL_I2C_SetOwnAddress1
Parameters:
I2Cx | I2C Instance.
OwnAddress1 | This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
OwnAddrSize This parameter can be one of the following values:
  • LL_I2C_OWNADDRESS1_7BIT
  • LL_I2C_OWNADDRESS1_10BIT
Return values:
None

Definition at line 779 of file stm32wbxx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_SetOwnAddress2 | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | OwnAddress2,
 |  | uint32_t | OwnAddrMask
 | ) |  |

Set the 7bits Own Address2.

Note:
This action has no effect if own address2 is enabled.
Reference Manual to LL API cross reference:
OAR2 OA2 LL_I2C_SetOwnAddress2
OAR2 OA2MSK LL_I2C_SetOwnAddress2
Parameters:
I2Cx | I2C Instance.
OwnAddress2 | Value between Min_Data=0 and Max_Data=0x7F.
OwnAddrMask This parameter can be one of the following values:
  • LL_I2C_OWNADDRESS2_NOMASK
  • LL_I2C_OWNADDRESS2_MASK01
  • LL_I2C_OWNADDRESS2_MASK02
  • LL_I2C_OWNADDRESS2_MASK03
  • LL_I2C_OWNADDRESS2_MASK04
  • LL_I2C_OWNADDRESS2_MASK05
  • LL_I2C_OWNADDRESS2_MASK06
  • LL_I2C_OWNADDRESS2_MASK07
Return values:
None

Definition at line 835 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TimeoutA
 | ) |  |

Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
These bits can only be programmed when TimeoutA is disabled.
Reference Manual to LL API cross reference:
TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA
Parameters:
I2Cx | I2C Instance.
TimeoutA | This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
Return values:
None

Definition at line 1100 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TimeoutAMode
 | ) |  |

Set the SMBus Clock TimeoutA mode.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
This bit can only be programmed when TimeoutA is disabled.
Reference Manual to LL API cross reference:
TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode
Parameters:
I2Cx I2C Instance.
TimeoutAMode This parameter can be one of the following values:
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
Return values:
None

Definition at line 1130 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TimeoutB
 | ) |  |

Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
These bits can only be programmed when TimeoutB is disabled.
Reference Manual to LL API cross reference:
TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB
Parameters:
I2Cx | I2C Instance.
TimeoutB | This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
Return values:
None

Definition at line 1160 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetTiming | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | Timing
 | ) |  |

Configure the SDA setup, hold time and the SCL high, low period.

Note:
This bit can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
TIMINGR TIMINGR LL_I2C_SetTiming
Parameters:
I2Cx | I2C Instance.
Timing | This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
Note:
This parameter is computed with the STM32CubeMX Tool.
Return values:
None

Definition at line 882 of file stm32wbxx_ll_i2c.h.

Referenced by LL_I2C_Init().

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IT_Management

Functions
IT_Management
I2C Exported Functions

Functions

__STATIC_INLINE void | LL_I2C_EnableIT_TX (I2C_TypeDef *I2Cx)
Enable TXIS interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_TX (I2C_TypeDef *I2Cx)
Disable TXIS interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_TX (I2C_TypeDef *I2Cx)
Check if the TXIS Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_RX (I2C_TypeDef *I2Cx)
Enable RXNE interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_RX (I2C_TypeDef *I2Cx)
Disable RXNE interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_RX (I2C_TypeDef *I2Cx)
Check if the RXNE Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_ADDR (I2C_TypeDef *I2Cx)
Enable Address match interrupt (slave mode only).
__STATIC_INLINE void | LL_I2C_DisableIT_ADDR (I2C_TypeDef *I2Cx)
Disable Address match interrupt (slave mode only).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_ADDR (I2C_TypeDef *I2Cx)
Check if Address match interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_NACK (I2C_TypeDef *I2Cx)
Enable Not acknowledge received interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_NACK (I2C_TypeDef *I2Cx)
Disable Not acknowledge received interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_NACK (I2C_TypeDef *I2Cx)
Check if Not acknowledge received interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_STOP (I2C_TypeDef *I2Cx)
Enable STOP detection interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_STOP (I2C_TypeDef *I2Cx)
Disable STOP detection interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_STOP (I2C_TypeDef *I2Cx)
Check if STOP detection interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_TC (I2C_TypeDef *I2Cx)
Enable Transfer Complete interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_TC (I2C_TypeDef *I2Cx)
Disable Transfer Complete interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_TC (I2C_TypeDef *I2Cx)
Check if Transfer Complete interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_ERR (I2C_TypeDef *I2Cx)
Enable Error interrupts.
__STATIC_INLINE void | LL_I2C_DisableIT_ERR (I2C_TypeDef *I2Cx)
Disable Error interrupts.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_ERR (I2C_TypeDef *I2Cx)
Check if Error interrupts are enabled or disabled.

Function Documentation

__STATIC_INLINE void LL_I2C_DisableIT_ADDR ( I2C_TypeDef * I2Cx )

Disable Address match interrupt (slave mode only).

Reference Manual to LL API cross reference:
CR1 ADDRIE LL_I2C_DisableIT_ADDR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1323 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_ERR ( I2C_TypeDef * I2Cx )

Disable Error interrupts.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Any of these errors will generate interrupt : Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) SMBus Timeout detection (TIMEOUT) SMBus PEC error detection (PECERR) SMBus Alert pin event detection (ALERT)
Reference Manual to LL API cross reference:
CR1 ERRIE LL_I2C_DisableIT_ERR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1479 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_NACK ( I2C_TypeDef * I2Cx )

Disable Not acknowledge received interrupt.

Reference Manual to LL API cross reference:
CR1 NACKIE LL_I2C_DisableIT_NACK
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1356 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_RX ( I2C_TypeDef * I2Cx )

Disable RXNE interrupt.

Reference Manual to LL API cross reference:
CR1 RXIE LL_I2C_DisableIT_RX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1290 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_STOP ( I2C_TypeDef * I2Cx )

Disable STOP detection interrupt.

Reference Manual to LL API cross reference:
CR1 STOPIE LL_I2C_DisableIT_STOP
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1389 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_TC ( I2C_TypeDef * I2Cx )

Disable Transfer Complete interrupt.

Note:
Any of these events will generate interrupt : Transfer Complete (TC) Transfer Complete Reload (TCR)
Reference Manual to LL API cross reference:
CR1 TCIE LL_I2C_DisableIT_TC
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1428 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_TX ( I2C_TypeDef * I2Cx )

Disable TXIS interrupt.

Reference Manual to LL API cross reference:
CR1 TXIE LL_I2C_DisableIT_TX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1257 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_ADDR ( I2C_TypeDef * I2Cx )

Enable Address match interrupt (slave mode only).

Reference Manual to LL API cross reference:
CR1 ADDRIE LL_I2C_EnableIT_ADDR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1312 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_ERR ( I2C_TypeDef * I2Cx )

Enable Error interrupts.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Any of these errors will generate interrupt : Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) SMBus Timeout detection (TIMEOUT) SMBus PEC error detection (PECERR) SMBus Alert pin event detection (ALERT)
Reference Manual to LL API cross reference:
CR1 ERRIE LL_I2C_EnableIT_ERR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1459 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_NACK ( I2C_TypeDef * I2Cx )

Enable Not acknowledge received interrupt.

Reference Manual to LL API cross reference:
CR1 NACKIE LL_I2C_EnableIT_NACK
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1345 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_RX ( I2C_TypeDef * I2Cx )

Enable RXNE interrupt.

Reference Manual to LL API cross reference:
CR1 RXIE LL_I2C_EnableIT_RX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1279 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_STOP ( I2C_TypeDef * I2Cx )

Enable STOP detection interrupt.

Reference Manual to LL API cross reference:
CR1 STOPIE LL_I2C_EnableIT_STOP
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1378 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_TC ( I2C_TypeDef * I2Cx )

Enable Transfer Complete interrupt.

Note:
Any of these events will generate interrupt : Transfer Complete (TC) Transfer Complete Reload (TCR)
Reference Manual to LL API cross reference:
CR1 TCIE LL_I2C_EnableIT_TC
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1414 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_TX ( I2C_TypeDef * I2Cx )

Enable TXIS interrupt.

Reference Manual to LL API cross reference:
CR1 TXIE LL_I2C_EnableIT_TX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1246 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR ( I2C_TypeDef * I2Cx )

Check if Address match interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1334 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR ( I2C_TypeDef * I2Cx )

Check if Error interrupts are enabled or disabled.

Reference Manual to LL API cross reference:
CR1 ERRIE LL_I2C_IsEnabledIT_ERR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1490 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK ( I2C_TypeDef * I2Cx )

Check if Not acknowledge received interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 NACKIE LL_I2C_IsEnabledIT_NACK
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1367 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX ( I2C_TypeDef * I2Cx )

Check if the RXNE Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 RXIE LL_I2C_IsEnabledIT_RX
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1301 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP ( I2C_TypeDef * I2Cx )

Check if STOP detection interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 STOPIE LL_I2C_IsEnabledIT_STOP
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1400 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC ( I2C_TypeDef * I2Cx )

Check if Transfer Complete interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TCIE LL_I2C_IsEnabledIT_TC
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1439 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX ( I2C_TypeDef * I2Cx )

Check if the TXIS Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TXIE LL_I2C_IsEnabledIT_TX
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1268 of file stm32wbxx_ll_i2c.h.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FLAG_management

Functions
FLAG_management
I2C Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TXE (I2C_TypeDef *I2Cx)
Indicate the status of Transmit data register empty flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TXIS (I2C_TypeDef *I2Cx)
Indicate the status of Transmit interrupt flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_RXNE (I2C_TypeDef *I2Cx)
Indicate the status of Receive data register not empty flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_ADDR (I2C_TypeDef *I2Cx)
Indicate the status of Address matched flag (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_NACK (I2C_TypeDef *I2Cx)
Indicate the status of Not Acknowledge received flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_STOP (I2C_TypeDef *I2Cx)
Indicate the status of Stop detection flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TC (I2C_TypeDef *I2Cx)
Indicate the status of Transfer complete flag (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TCR (I2C_TypeDef *I2Cx)
Indicate the status of Transfer complete flag (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_BERR (I2C_TypeDef *I2Cx)
Indicate the status of Bus error flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_ARLO (I2C_TypeDef *I2Cx)
Indicate the status of Arbitration lost flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_OVR (I2C_TypeDef *I2Cx)
Indicate the status of Overrun/Underrun flag (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_PECERR (I2C_TypeDef *I2Cx)
Indicate the status of SMBus PEC error flag in reception.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_TIMEOUT (I2C_TypeDef *I2Cx)
Indicate the status of SMBus Timeout detection flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_ALERT (I2C_TypeDef *I2Cx)
Indicate the status of SMBus alert flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_BUSY (I2C_TypeDef *I2Cx)
Indicate the status of Bus Busy flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_ADDR (I2C_TypeDef *I2Cx)
Clear Address Matched flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_NACK (I2C_TypeDef *I2Cx)
Clear Not Acknowledge flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_STOP (I2C_TypeDef *I2Cx)
Clear Stop detection flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_TXE (I2C_TypeDef *I2Cx)
Clear Transmit data register empty flag (TXE).
__STATIC_INLINE void | LL_I2C_ClearFlag_BERR (I2C_TypeDef *I2Cx)
Clear Bus error flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_ARLO (I2C_TypeDef *I2Cx)
Clear Arbitration lost flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_OVR (I2C_TypeDef *I2Cx)
Clear Overrun/Underrun flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_PECERR (I2C_TypeDef *I2Cx)
Clear SMBus PEC error flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_TIMEOUT (I2C_TypeDef *I2Cx)
Clear SMBus Timeout detection flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_ALERT (I2C_TypeDef *I2Cx)
Clear SMBus Alert flag.

Function Documentation

__STATIC_INLINE void LL_I2C_ClearFlag_ADDR ( I2C_TypeDef * I2Cx )

Clear Address Matched flag.

Reference Manual to LL API cross reference:
ICR ADDRCF LL_I2C_ClearFlag_ADDR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1711 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_ARLO ( I2C_TypeDef * I2Cx )

Clear Arbitration lost flag.

Reference Manual to LL API cross reference:
ICR ARLOCF LL_I2C_ClearFlag_ARLO
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1767 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_BERR ( I2C_TypeDef * I2Cx )

Clear Bus error flag.

Reference Manual to LL API cross reference:
ICR BERRCF LL_I2C_ClearFlag_BERR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1756 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_NACK ( I2C_TypeDef * I2Cx )

Clear Not Acknowledge flag.

Reference Manual to LL API cross reference:
ICR NACKCF LL_I2C_ClearFlag_NACK
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1722 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_OVR ( I2C_TypeDef * I2Cx )

Clear Overrun/Underrun flag.

Reference Manual to LL API cross reference:
ICR OVRCF LL_I2C_ClearFlag_OVR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1778 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_STOP ( I2C_TypeDef * I2Cx )

Clear Stop detection flag.

Reference Manual to LL API cross reference:
ICR STOPCF LL_I2C_ClearFlag_STOP
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1733 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_TXE ( I2C_TypeDef * I2Cx )

Clear Transmit data register empty flag (TXE).

Note:
This bit can be clear by software in order to flush the transmit data register (TXDR).
Reference Manual to LL API cross reference:
ISR TXE LL_I2C_ClearFlag_TXE
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1745 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT ( I2C_TypeDef * I2Cx )

Clear SMBus Alert flag.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1817 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR ( I2C_TypeDef * I2Cx )

Clear SMBus PEC error flag.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
ICR PECCF LL_I2C_ClearSMBusFlag_PECERR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1791 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT ( I2C_TypeDef * I2Cx )

Clear SMBus Timeout detection flag.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1804 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR ( I2C_TypeDef * I2Cx )

Indicate the status of Address matched flag (slave mode).

Note:
RESET: Clear default value. SET: When the received slave address matched with one of the enabled slave address.
Reference Manual to LL API cross reference:
ISR ADDR LL_I2C_IsActiveFlag_ADDR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1550 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO ( I2C_TypeDef * I2Cx )

Indicate the status of Arbitration lost flag.

Note:
RESET: Clear default value. SET: When arbitration lost.
Reference Manual to LL API cross reference:
ISR ARLO LL_I2C_IsActiveFlag_ARLO
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1628 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR ( I2C_TypeDef * I2Cx )

Indicate the status of Bus error flag.

Note:
RESET: Clear default value. SET: When a misplaced Start or Stop condition is detected.
Reference Manual to LL API cross reference:
ISR BERR LL_I2C_IsActiveFlag_BERR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1615 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY ( I2C_TypeDef * I2Cx )

Indicate the status of Bus Busy flag.

Note:
RESET: Clear default value. SET: When a Start condition is detected.
Reference Manual to LL API cross reference:
ISR BUSY LL_I2C_IsActiveFlag_BUSY
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1700 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK ( I2C_TypeDef * I2Cx )

Indicate the status of Not Acknowledge received flag.

Note:
RESET: Clear default value. SET: When a NACK is received after a byte transmission.
Reference Manual to LL API cross reference:
ISR NACKF LL_I2C_IsActiveFlag_NACK
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1563 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR ( I2C_TypeDef * I2Cx )

Indicate the status of Overrun/Underrun flag (slave mode).

Note:
RESET: Clear default value. SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
Reference Manual to LL API cross reference:
ISR OVR LL_I2C_IsActiveFlag_OVR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1641 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE ( I2C_TypeDef * I2Cx )

Indicate the status of Receive data register not empty flag.

Note:
RESET: When Receive data register is read. SET: When the received data is copied in Receive data register.
Reference Manual to LL API cross reference:
ISR RXNE LL_I2C_IsActiveFlag_RXNE
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1537 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP ( I2C_TypeDef * I2Cx )

Indicate the status of Stop detection flag.

Note:
RESET: Clear default value. SET: When a Stop condition is detected.
Reference Manual to LL API cross reference:
ISR STOPF LL_I2C_IsActiveFlag_STOP
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1576 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC ( I2C_TypeDef * I2Cx )

Indicate the status of Transfer complete flag (master mode).

Note:
RESET: Clear default value. SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
Reference Manual to LL API cross reference:
ISR TC LL_I2C_IsActiveFlag_TC
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1589 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR ( I2C_TypeDef * I2Cx )

Indicate the status of Transfer complete flag (master mode).

Note:
RESET: Clear default value. SET: When RELOAD=1 and NBYTES date have been transferred.
Reference Manual to LL API cross reference:
ISR TCR LL_I2C_IsActiveFlag_TCR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1602 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE ( I2C_TypeDef * I2Cx )

Indicate the status of Transmit data register empty flag.

Note:
RESET: When next data is written in Transmit data register. SET: When Transmit data register is empty.
Reference Manual to LL API cross reference:
ISR TXE LL_I2C_IsActiveFlag_TXE
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1511 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS ( I2C_TypeDef * I2Cx )

Indicate the status of Transmit interrupt flag.

Note:
RESET: When next data is written in Transmit data register. SET: When Transmit data register is empty.
Reference Manual to LL API cross reference:
ISR TXIS LL_I2C_IsActiveFlag_TXIS
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1524 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT ( I2C_TypeDef * I2Cx )

Indicate the status of SMBus alert flag.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
RESET: Clear default value. SET: When SMBus host configuration, SMBus alert enabled and a falling edge event occurs on SMBA pin.
Reference Manual to LL API cross reference:
ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1687 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR ( I2C_TypeDef * I2Cx )

Indicate the status of SMBus PEC error flag in reception.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
RESET: Clear default value. SET: When the received PEC does not match with the PEC register content.
Reference Manual to LL API cross reference:
ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1656 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT ( I2C_TypeDef * I2Cx )

Indicate the status of SMBus Timeout detection flag.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
RESET: Clear default value. SET: When a timeout or extended clock timeout occurs.
Reference Manual to LL API cross reference:
ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1671 of file stm32wbxx_ll_i2c.h.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data_Management

Functions
Data_Management
I2C Exported Functions

Functions

__STATIC_INLINE void | LL_I2C_EnableAutoEndMode (I2C_TypeDef *I2Cx)
Enable automatic STOP condition generation (master mode).
__STATIC_INLINE void | LL_I2C_DisableAutoEndMode (I2C_TypeDef *I2Cx)
Disable automatic STOP condition generation (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledAutoEndMode (I2C_TypeDef *I2Cx)
Check if automatic STOP condition is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableReloadMode (I2C_TypeDef *I2Cx)
Enable reload mode (master mode).
__STATIC_INLINE void | LL_I2C_DisableReloadMode (I2C_TypeDef *I2Cx)
Disable reload mode (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledReloadMode (I2C_TypeDef *I2Cx)
Check if reload mode is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetTransferSize (I2C_TypeDef *I2Cx, uint32_t TransferSize)
Configure the number of bytes for transfer.
__STATIC_INLINE uint32_t | LL_I2C_GetTransferSize (I2C_TypeDef *I2Cx)
Get the number of bytes configured for transfer.
__STATIC_INLINE void | LL_I2C_AcknowledgeNextData (I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
__STATIC_INLINE void | LL_I2C_GenerateStartCondition (I2C_TypeDef *I2Cx)
Generate a START or RESTART condition.
__STATIC_INLINE void | LL_I2C_GenerateStopCondition (I2C_TypeDef *I2Cx)
Generate a STOP condition after the current byte transfer (master mode).
__STATIC_INLINE void | LL_I2C_EnableAuto10BitRead (I2C_TypeDef *I2Cx)
Enable automatic RESTART Read request condition for 10bit address header (master mode).
__STATIC_INLINE void | LL_I2C_DisableAuto10BitRead (I2C_TypeDef *I2Cx)
Disable automatic RESTART Read request condition for 10bit address header (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledAuto10BitRead (I2C_TypeDef *I2Cx)
Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetTransferRequest (I2C_TypeDef *I2Cx, uint32_t TransferRequest)
Configure the transfer direction (master mode).
__STATIC_INLINE uint32_t | LL_I2C_GetTransferRequest (I2C_TypeDef *I2Cx)
Get the transfer direction requested (master mode).
__STATIC_INLINE void | LL_I2C_SetSlaveAddr (I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
Configure the slave address for transfer (master mode).
__STATIC_INLINE uint32_t | LL_I2C_GetSlaveAddr (I2C_TypeDef *I2Cx)
Get the slave address programmed for transfer.
__STATIC_INLINE void | LL_I2C_HandleTransfer (I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
__STATIC_INLINE uint32_t | LL_I2C_GetTransferDirection (I2C_TypeDef *I2Cx)
Indicate the value of transfer direction (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_GetAddressMatchCode (I2C_TypeDef *I2Cx)
Return the slave matched address.
__STATIC_INLINE void | LL_I2C_EnableSMBusPECCompare (I2C_TypeDef *I2Cx)
Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusPECCompare (I2C_TypeDef *I2Cx)
Check if the SMBus Packet Error byte internal comparison is requested or not.
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusPEC (I2C_TypeDef *I2Cx)
Get the SMBus Packet Error byte calculated.
__STATIC_INLINE uint8_t | LL_I2C_ReceiveData8 (I2C_TypeDef *I2Cx)
Read Receive Data register.
__STATIC_INLINE void | LL_I2C_TransmitData8 (I2C_TypeDef *I2Cx, uint8_t Data)
Write in Transmit Data Register .

Function Documentation

__STATIC_INLINE void LL_I2C_AcknowledgeNextData | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TypeAcknowledge
 | ) |  |

Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.

Note:
Usage in Slave mode only.
Reference Manual to LL API cross reference:
CR2 NACK LL_I2C_AcknowledgeNextData
Parameters:
I2Cx I2C Instance.
TypeAcknowledge This parameter can be one of the following values:
  • LL_I2C_ACK
  • LL_I2C_NACK
Return values:
None

Definition at line 1935 of file stm32wbxx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_DisableAuto10BitRead ( I2C_TypeDef * I2Cx )

Disable automatic RESTART Read request condition for 10bit address header (master mode).

Note:
The master only sends the first 7 bits of 10bit address in Read direction.
Reference Manual to LL API cross reference:
CR2 HEAD10R LL_I2C_DisableAuto10BitRead
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1984 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableAutoEndMode ( I2C_TypeDef * I2Cx )

Disable automatic STOP condition generation (master mode).

Note:
Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
Reference Manual to LL API cross reference:
CR2 AUTOEND LL_I2C_DisableAutoEndMode
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1850 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableReloadMode ( I2C_TypeDef * I2Cx )

Disable reload mode (master mode).

Note:
The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
Reference Manual to LL API cross reference:
CR2 RELOAD LL_I2C_DisableReloadMode
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1885 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableAuto10BitRead ( I2C_TypeDef * I2Cx )

Enable automatic RESTART Read request condition for 10bit address header (master mode).

Note:
The master sends the complete 10bit slave address read sequence : Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction.
Reference Manual to LL API cross reference:
CR2 HEAD10R LL_I2C_EnableAuto10BitRead
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1972 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableAutoEndMode ( I2C_TypeDef * I2Cx )

Enable automatic STOP condition generation (master mode).

Note:
Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred. This bit has no effect in slave mode or when RELOAD bit is set.
Reference Manual to LL API cross reference:
CR2 AUTOEND LL_I2C_EnableAutoEndMode
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1838 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableReloadMode ( I2C_TypeDef * I2Cx )

Enable reload mode (master mode).

Note:
The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
Reference Manual to LL API cross reference:
CR2 RELOAD LL_I2C_EnableReloadMode
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1873 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare ( I2C_TypeDef * I2Cx )

Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received. This bit has no effect when RELOAD bit is set. This bit has no effect in device mode when SBC bit is not set.
Reference Manual to LL API cross reference:
CR2 PECBYTE LL_I2C_EnableSMBusPECCompare
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 2135 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_GenerateStartCondition ( I2C_TypeDef * I2Cx )

Generate a START or RESTART condition.

Note:
The START bit can be set even if bus is BUSY or I2C is in slave mode. This action has no effect when RELOAD is set.
Reference Manual to LL API cross reference:
CR2 START LL_I2C_GenerateStartCondition
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1948 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_GenerateStopCondition ( I2C_TypeDef * I2Cx )

Generate a STOP condition after the current byte transfer (master mode).

Reference Manual to LL API cross reference:
CR2 STOP LL_I2C_GenerateStopCondition
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1959 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode ( I2C_TypeDef * I2Cx )

Return the slave matched address.

Reference Manual to LL API cross reference:
ISR ADDCODE LL_I2C_GetAddressMatchCode
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x00 and Max_Data=0x3F

Definition at line 2119 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr ( I2C_TypeDef * I2Cx )

Get the slave address programmed for transfer.

Reference Manual to LL API cross reference:
CR2 SADD LL_I2C_GetSlaveAddr
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x0 and Max_Data=0x3F

Definition at line 2047 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC ( I2C_TypeDef * I2Cx )

Get the SMBus Packet Error byte calculated.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
PECR PEC LL_I2C_GetSMBusPEC
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 2161 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection ( I2C_TypeDef * I2Cx )

Indicate the value of transfer direction (slave mode).

Note:
RESET: Write transfer, Slave enters in receiver mode. SET: Read transfer, Slave enters in transmitter mode.
Reference Manual to LL API cross reference:
ISR DIR LL_I2C_GetTransferDirection
Parameters:
I2Cx I2C Instance.
Return values:
Returned value can be one of the following values:
  • LL_I2C_DIRECTION_WRITE
  • LL_I2C_DIRECTION_READ

Definition at line 2108 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest ( I2C_TypeDef * I2Cx )

Get the transfer direction requested (master mode).

Reference Manual to LL API cross reference:
CR2 RD_WRN LL_I2C_GetTransferRequest
Parameters:
I2Cx I2C Instance.
Return values:
Returned value can be one of the following values:
  • LL_I2C_REQUEST_WRITE
  • LL_I2C_REQUEST_READ

Definition at line 2023 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetTransferSize ( I2C_TypeDef * I2Cx )

Get the number of bytes configured for transfer.

Reference Manual to LL API cross reference:
CR2 NBYTES LL_I2C_GetTransferSize
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x0 and Max_Data=0xFF

Definition at line 1920 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_HandleTransfer | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | SlaveAddr,
 |  | uint32_t | SlaveAddrSize,
 |  | uint32_t | TransferSize,
 |  | uint32_t | EndMode,
 |  | uint32_t | Request
 | ) |  |

Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).

Reference Manual to LL API cross reference:
CR2 SADD LL_I2C_HandleTransfer
CR2 ADD10 LL_I2C_HandleTransfer
CR2 RD_WRN LL_I2C_HandleTransfer
CR2 START LL_I2C_HandleTransfer
CR2 STOP LL_I2C_HandleTransfer
CR2 RELOAD LL_I2C_HandleTransfer
CR2 NBYTES LL_I2C_HandleTransfer
CR2 AUTOEND LL_I2C_HandleTransfer
CR2 HEAD10R LL_I2C_HandleTransfer
Parameters:
I2Cx | I2C Instance.
SlaveAddr | Specifies the slave address to be programmed.
SlaveAddrSize This parameter can be one of the following values:
  • LL_I2C_ADDRSLAVE_7BIT
  • LL_I2C_ADDRSLAVE_10BIT
TransferSize | Specifies the number of bytes to be programmed. This parameter must be a value between Min_Data=0 and Max_Data=255.
EndMode This parameter can be one of the following values:
  • LL_I2C_MODE_RELOAD
  • LL_I2C_MODE_AUTOEND
  • LL_I2C_MODE_SOFTEND
  • LL_I2C_MODE_SMBUS_RELOAD
  • LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
  • LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
  • LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
  • LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
Request This parameter can be one of the following values:
  • LL_I2C_GENERATE_NOSTARTSTOP
  • LL_I2C_GENERATE_STOP
  • LL_I2C_GENERATE_START_READ
  • LL_I2C_GENERATE_START_WRITE
  • LL_I2C_GENERATE_RESTART_7BIT_READ
  • LL_I2C_GENERATE_RESTART_7BIT_WRITE
  • LL_I2C_GENERATE_RESTART_10BIT_READ
  • LL_I2C_GENERATE_RESTART_10BIT_WRITE
Return values:
None

Definition at line 2090 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead ( I2C_TypeDef * I2Cx )

Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.

Reference Manual to LL API cross reference:
CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1995 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode ( I2C_TypeDef * I2Cx )

Check if automatic STOP condition is enabled or disabled.

Reference Manual to LL API cross reference:
CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1861 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode ( I2C_TypeDef * I2Cx )

Check if reload mode is enabled or disabled.

Reference Manual to LL API cross reference:
CR2 RELOAD LL_I2C_IsEnabledReloadMode
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1896 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare ( I2C_TypeDef * I2Cx )

Check if the SMBus Packet Error byte internal comparison is requested or not.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 2148 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE uint8_t LL_I2C_ReceiveData8 ( I2C_TypeDef * I2Cx )

Read Receive Data register.

Reference Manual to LL API cross reference:
RXDR RXDATA LL_I2C_ReceiveData8
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 2172 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetSlaveAddr | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | SlaveAddr
 | ) |  |

Configure the slave address for transfer (master mode).

Note:
Changing these bits when START bit is set is not allowed.
Reference Manual to LL API cross reference:
CR2 SADD LL_I2C_SetSlaveAddr
Parameters:
I2Cx | I2C Instance.
SlaveAddr | This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
Return values:
None

Definition at line 2036 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetTransferRequest | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TransferRequest
 | ) |  |

Configure the transfer direction (master mode).

Note:
Changing these bits when START bit is set is not allowed.
Reference Manual to LL API cross reference:
CR2 RD_WRN LL_I2C_SetTransferRequest
Parameters:
I2Cx I2C Instance.
TransferRequest This parameter can be one of the following values:
  • LL_I2C_REQUEST_WRITE
  • LL_I2C_REQUEST_READ
Return values:
None

Definition at line 2010 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetTransferSize | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TransferSize
 | ) |  |

Configure the number of bytes for transfer.

Note:
Changing these bits when START bit is set is not allowed.
Reference Manual to LL API cross reference:
CR2 NBYTES LL_I2C_SetTransferSize
Parameters:
I2Cx | I2C Instance.
TransferSize | This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
Return values:
None

Definition at line 1909 of file stm32wbxx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_TransmitData8 | ( | I2C_TypeDef * | I2Cx,
 |  | uint8_t | Data
 | ) |  |

Write in Transmit Data Register .

Reference Manual to LL API cross reference:
TXDR TXDATA LL_I2C_TransmitData8
Parameters:
I2Cx | I2C Instance.
Data | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 2184 of file stm32wbxx_ll_i2c.h.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
I2C Exported Functions

Functions

ErrorStatus | LL_I2C_DeInit (I2C_TypeDef *I2Cx)
De-initialize the I2C registers to their default reset values.
ErrorStatus | LL_I2C_Init (I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
void | LL_I2C_StructInit (LL_I2C_InitTypeDef *I2C_InitStruct)
Set each LL_I2C_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_I2C_DeInit ( I2C_TypeDef * I2Cx )

De-initialize the I2C registers to their default reset values.

Parameters:
I2Cx I2C Instance.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: I2C registers are de-initialized
  • ERROR: I2C registers are not de-initialized

Definition at line 87 of file stm32wbxx_ll_i2c.c.

References assert_param, LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_I2C1, LL_APB1_GRP1_PERIPH_I2C3, and LL_APB1_GRP1_ReleaseReset().

ErrorStatus LL_I2C_Init | ( | I2C_TypeDef * | I2Cx,
 |  | LL_I2C_InitTypeDef * | I2C_InitStruct
 | ) |  |

Initialize the I2C registers according to the specified parameters in I2C_InitStruct.

Parameters:
I2Cx | I2C Instance.
I2C_InitStruct | pointer to a LL_I2C_InitTypeDef structure.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: I2C registers are initialized
  • ERROR: Not applicable

Definition at line 128 of file stm32wbxx_ll_i2c.c.

References LL_I2C_InitTypeDef::AnalogFilter, assert_param, LL_I2C_InitTypeDef::DigitalFilter, IS_LL_I2C_ANALOG_FILTER, IS_LL_I2C_DIGITAL_FILTER, IS_LL_I2C_OWN_ADDRESS1, IS_LL_I2C_OWN_ADDRSIZE, IS_LL_I2C_PERIPHERAL_MODE, IS_LL_I2C_TYPE_ACKNOWLEDGE, LL_I2C_AcknowledgeNextData(), LL_I2C_ConfigFilters(), LL_I2C_Disable(), LL_I2C_DisableOwnAddress1(), LL_I2C_Enable(), LL_I2C_EnableOwnAddress1(), LL_I2C_SetMode(), LL_I2C_SetOwnAddress1(), LL_I2C_SetTiming(), LL_I2C_InitTypeDef::OwnAddress1, LL_I2C_InitTypeDef::OwnAddrSize, LL_I2C_InitTypeDef::PeripheralMode, LL_I2C_InitTypeDef::Timing, and LL_I2C_InitTypeDef::TypeAcknowledge.

void LL_I2C_StructInit ( LL_I2C_InitTypeDef * I2C_InitStruct )

Set each LL_I2C_InitTypeDef field to default value.

Parameters:
I2C_InitStruct Pointer to a LL_I2C_InitTypeDef structure.
Return values:
None

Definition at line 196 of file stm32wbxx_ll_i2c.c.

References LL_I2C_InitTypeDef::AnalogFilter, LL_I2C_InitTypeDef::DigitalFilter, LL_I2C_ANALOGFILTER_ENABLE, LL_I2C_MODE_I2C, LL_I2C_NACK, LL_I2C_OWNADDRESS1_7BIT, LL_I2C_InitTypeDef::OwnAddress1, LL_I2C_InitTypeDef::OwnAddrSize, LL_I2C_InitTypeDef::PeripheralMode, LL_I2C_InitTypeDef::Timing, and LL_I2C_InitTypeDef::TypeAcknowledge.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IPCC

Modules
IPCC
STM32WBxx_LL_Driver

Modules

IPCC Exported Constants
IPCC Exported Macros
IPCC Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for IPCC registers.

Register | Bit | Function
C1CR | RXOIE | LL_C1_IPCC_DisableIT_RXO
 |  | LL_C1_IPCC_EnableIT_RXO
 |  | LL_C1_IPCC_IsEnabledIT_RXO
 | TXFIE | LL_C1_IPCC_DisableIT_TXF
 |  | LL_C1_IPCC_EnableIT_TXF
 |  | LL_C1_IPCC_IsEnabledIT_TXF
C1MR | CH1FM | LL_C1_IPCC_DisableTransmitChannel
 |  | LL_C1_IPCC_EnableTransmitChannel
 |  | LL_C1_IPCC_IsEnabledTransmitChannel
 | CH1OM | LL_C1_IPCC_DisableReceiveChannel
 |  | LL_C1_IPCC_EnableReceiveChannel
 |  | LL_C1_IPCC_IsEnabledReceiveChannel
 | CH2FM | LL_C1_IPCC_DisableTransmitChannel
 |  | LL_C1_IPCC_EnableTransmitChannel
 |  | LL_C1_IPCC_IsEnabledTransmitChannel
 | CH2OM | LL_C1_IPCC_DisableReceiveChannel
 |  | LL_C1_IPCC_EnableReceiveChannel
 |  | LL_C1_IPCC_IsEnabledReceiveChannel
 | CH3FM | LL_C1_IPCC_DisableTransmitChannel
 |  | LL_C1_IPCC_EnableTransmitChannel
 |  | LL_C1_IPCC_IsEnabledTransmitChannel
 | CH3OM | LL_C1_IPCC_DisableReceiveChannel
 |  | LL_C1_IPCC_EnableReceiveChannel
 |  | LL_C1_IPCC_IsEnabledReceiveChannel
 | CH4FM | LL_C1_IPCC_DisableTransmitChannel
 |  | LL_C1_IPCC_EnableTransmitChannel
 |  | LL_C1_IPCC_IsEnabledTransmitChannel
 | CH4OM | LL_C1_IPCC_DisableReceiveChannel
 |  | LL_C1_IPCC_EnableReceiveChannel
 |  | LL_C1_IPCC_IsEnabledReceiveChannel
 | CH5FM | LL_C1_IPCC_DisableTransmitChannel
 |  | LL_C1_IPCC_EnableTransmitChannel
 |  | LL_C1_IPCC_IsEnabledTransmitChannel
 | CH5OM | LL_C1_IPCC_DisableReceiveChannel
 |  | LL_C1_IPCC_EnableReceiveChannel
 |  | LL_C1_IPCC_IsEnabledReceiveChannel
 | CH6FM | LL_C1_IPCC_DisableTransmitChannel
 |  | LL_C1_IPCC_EnableTransmitChannel
 |  | LL_C1_IPCC_IsEnabledTransmitChannel
 | CH6OM | LL_C1_IPCC_DisableReceiveChannel
 |  | LL_C1_IPCC_EnableReceiveChannel
 |  | LL_C1_IPCC_IsEnabledReceiveChannel
C1SCR | CH1C | LL_C1_IPCC_ClearFlag_CHx
 | CH1S | LL_C1_IPCC_SetFlag_CHx
 | CH2C | LL_C1_IPCC_ClearFlag_CHx
 | CH2S | LL_C1_IPCC_SetFlag_CHx
 | CH3C | LL_C1_IPCC_ClearFlag_CHx
 | CH3S | LL_C1_IPCC_SetFlag_CHx
 | CH4C | LL_C1_IPCC_ClearFlag_CHx
 | CH4S | LL_C1_IPCC_SetFlag_CHx
 | CH5C | LL_C1_IPCC_ClearFlag_CHx
 | CH5S | LL_C1_IPCC_SetFlag_CHx
 | CH6C | LL_C1_IPCC_ClearFlag_CHx
 | CH6S | LL_C1_IPCC_SetFlag_CHx
C1TOC2SR | CH1F | LL_C1_IPCC_IsActiveFlag_CHx
 | CH2F | LL_C1_IPCC_IsActiveFlag_CHx
 | CH3F | LL_C1_IPCC_IsActiveFlag_CHx
 | CH4F | LL_C1_IPCC_IsActiveFlag_CHx
 | CH5F | LL_C1_IPCC_IsActiveFlag_CHx
 | CH6F | LL_C1_IPCC_IsActiveFlag_CHx
C2CR | RXOIE | LL_C2_IPCC_DisableIT_RXO
 |  | LL_C2_IPCC_EnableIT_RXO
 |  | LL_C2_IPCC_IsEnabledIT_RXO
 | TXFIE | LL_C2_IPCC_DisableIT_TXF
 |  | LL_C2_IPCC_EnableIT_TXF
 |  | LL_C2_IPCC_IsEnabledIT_TXF
C2MR | CH1FM | LL_C2_IPCC_DisableTransmitChannel
 |  | LL_C2_IPCC_EnableTransmitChannel
 |  | LL_C2_IPCC_IsEnabledTransmitChannel
 | CH1OM | LL_C2_IPCC_DisableReceiveChannel
 |  | LL_C2_IPCC_EnableReceiveChannel
 |  | LL_C2_IPCC_IsEnabledReceiveChannel
 | CH2FM | LL_C2_IPCC_DisableTransmitChannel
 |  | LL_C2_IPCC_EnableTransmitChannel
 |  | LL_C2_IPCC_IsEnabledTransmitChannel
 | CH2OM | LL_C2_IPCC_DisableReceiveChannel
 |  | LL_C2_IPCC_EnableReceiveChannel
 |  | LL_C2_IPCC_IsEnabledReceiveChannel
 | CH3FM | LL_C2_IPCC_DisableTransmitChannel
 |  | LL_C2_IPCC_EnableTransmitChannel
 |  | LL_C2_IPCC_IsEnabledTransmitChannel
 | CH3OM | LL_C2_IPCC_DisableReceiveChannel
 |  | LL_C2_IPCC_EnableReceiveChannel
 |  | LL_C2_IPCC_IsEnabledReceiveChannel
 | CH4FM | LL_C2_IPCC_DisableTransmitChannel
 |  | LL_C2_IPCC_EnableTransmitChannel
 |  | LL_C2_IPCC_IsEnabledTransmitChannel
 | CH4OM | LL_C2_IPCC_DisableReceiveChannel
 |  | LL_C2_IPCC_EnableReceiveChannel
 |  | LL_C2_IPCC_IsEnabledReceiveChannel
 | CH5FM | LL_C2_IPCC_DisableTransmitChannel
 |  | LL_C2_IPCC_EnableTransmitChannel
 |  | LL_C2_IPCC_IsEnabledTransmitChannel
 | CH5OM | LL_C2_IPCC_DisableReceiveChannel
 |  | LL_C2_IPCC_EnableReceiveChannel
 |  | LL_C2_IPCC_IsEnabledReceiveChannel
 | CH6FM | LL_C2_IPCC_DisableTransmitChannel
 |  | LL_C2_IPCC_EnableTransmitChannel
 |  | LL_C2_IPCC_IsEnabledTransmitChannel
 | CH6OM | LL_C2_IPCC_DisableReceiveChannel
 |  | LL_C2_IPCC_EnableReceiveChannel
 |  | LL_C2_IPCC_IsEnabledReceiveChannel
C2SCR | CH1C | LL_C2_IPCC_ClearFlag_CHx
 | CH1S | LL_C2_IPCC_SetFlag_CHx
 | CH2C | LL_C2_IPCC_ClearFlag_CHx
 | CH2S | LL_C2_IPCC_SetFlag_CHx
 | CH3C | LL_C2_IPCC_ClearFlag_CHx
 | CH3S | LL_C2_IPCC_SetFlag_CHx
 | CH4C | LL_C2_IPCC_ClearFlag_CHx
 | CH4S | LL_C2_IPCC_SetFlag_CHx
 | CH5C | LL_C2_IPCC_ClearFlag_CHx
 | CH5S | LL_C2_IPCC_SetFlag_CHx
 | CH6C | LL_C2_IPCC_ClearFlag_CHx
 | CH6S | LL_C2_IPCC_SetFlag_CHx
C2TOC1SR | CH1F | LL_C2_IPCC_IsActiveFlag_CHx
 | CH2F | LL_C2_IPCC_IsActiveFlag_CHx
 | CH3F | LL_C2_IPCC_IsActiveFlag_CHx
 | CH4F | LL_C2_IPCC_IsActiveFlag_CHx
 | CH5F | LL_C2_IPCC_IsActiveFlag_CHx
 | CH6F | LL_C2_IPCC_IsActiveFlag_CHx
Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
IPCC Exported Constants

Flags defines which can be used with LL_IPCC_ReadReg function. More...

Defines

#define | LL_IPCC_C1TOC2SR_CH1F IPCC_C1TOC2SR_CH1F_Msk
#define | LL_IPCC_C1TOC2SR_CH2F IPCC_C1TOC2SR_CH2F_Msk
#define | LL_IPCC_C1TOC2SR_CH3F IPCC_C1TOC2SR_CH3F_Msk
#define | LL_IPCC_C1TOC2SR_CH4F IPCC_C1TOC2SR_CH4F_Msk
#define | LL_IPCC_C1TOC2SR_CH5F IPCC_C1TOC2SR_CH5F_Msk
#define | LL_IPCC_C1TOC2SR_CH6F IPCC_C1TOC2SR_CH6F_Msk
#define | LL_IPCC_C2TOC1SR_CH1F IPCC_C2TOC1SR_CH1F_Msk
#define | LL_IPCC_C2TOC1SR_CH2F IPCC_C2TOC1SR_CH2F_Msk
#define | LL_IPCC_C2TOC1SR_CH3F IPCC_C2TOC1SR_CH3F_Msk
#define | LL_IPCC_C2TOC1SR_CH4F IPCC_C2TOC1SR_CH4F_Msk
#define | LL_IPCC_C2TOC1SR_CH5F IPCC_C2TOC1SR_CH5F_Msk
#define | LL_IPCC_C2TOC1SR_CH6F IPCC_C2TOC1SR_CH6F_Msk

Detailed Description

Flags defines which can be used with LL_IPCC_ReadReg function.

Define Documentation

#define LL_IPCC_C1TOC2SR_CH1F IPCC_C1TOC2SR_CH1F_Msk

C1 transmit to C2 receive Channel1 status flag before masking

Definition at line 55 of file stm32wbxx_ll_ipcc.h.

#define LL_IPCC_C1TOC2SR_CH2F IPCC_C1TOC2SR_CH2F_Msk

C1 transmit to C2 receive Channel2 status flag before masking

Definition at line 56 of file stm32wbxx_ll_ipcc.h.

#define LL_IPCC_C1TOC2SR_CH3F IPCC_C1TOC2SR_CH3F_Msk

C1 transmit to C2 receive Channel3 status flag before masking

Definition at line 57 of file stm32wbxx_ll_ipcc.h.

#define LL_IPCC_C1TOC2SR_CH4F IPCC_C1TOC2SR_CH4F_Msk

C1 transmit to C2 receive Channel4 status flag before masking

Definition at line 58 of file stm32wbxx_ll_ipcc.h.

#define LL_IPCC_C1TOC2SR_CH5F IPCC_C1TOC2SR_CH5F_Msk

C1 transmit to C2 receive Channel5 status flag before masking

Definition at line 59 of file stm32wbxx_ll_ipcc.h.

#define LL_IPCC_C1TOC2SR_CH6F IPCC_C1TOC2SR_CH6F_Msk

C1 transmit to C2 receive Channel6 status flag before masking

Definition at line 60 of file stm32wbxx_ll_ipcc.h.

#define LL_IPCC_C2TOC1SR_CH1F IPCC_C2TOC1SR_CH1F_Msk

C2 transmit to C1 receive Channel1 status flag before masking

Definition at line 61 of file stm32wbxx_ll_ipcc.h.

#define LL_IPCC_C2TOC1SR_CH2F IPCC_C2TOC1SR_CH2F_Msk

C2 transmit to C1 receive Channel2 status flag before masking

Definition at line 62 of file stm32wbxx_ll_ipcc.h.

#define LL_IPCC_C2TOC1SR_CH3F IPCC_C2TOC1SR_CH3F_Msk

C2 transmit to C1 receive Channel3 status flag before masking

Definition at line 63 of file stm32wbxx_ll_ipcc.h.

#define LL_IPCC_C2TOC1SR_CH4F IPCC_C2TOC1SR_CH4F_Msk

C2 transmit to C1 receive Channel4 status flag before masking

Definition at line 64 of file stm32wbxx_ll_ipcc.h.

#define LL_IPCC_C2TOC1SR_CH5F IPCC_C2TOC1SR_CH5F_Msk

C2 transmit to C1 receive Channel5 status flag before masking

Definition at line 65 of file stm32wbxx_ll_ipcc.h.

#define LL_IPCC_C2TOC1SR_CH6F IPCC_C2TOC1SR_CH6F_Msk

C2 transmit to C1 receive Channel6 status flag before masking

Definition at line 66 of file stm32wbxx_ll_ipcc.h.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Channel

Defines
Channel
IPCC Exported Constants

Defines

#define | LL_IPCC_CHANNEL_1 (0x00000001U)
#define | LL_IPCC_CHANNEL_2 (0x00000002U)
#define | LL_IPCC_CHANNEL_3 (0x00000004U)
#define | LL_IPCC_CHANNEL_4 (0x00000008U)
#define | LL_IPCC_CHANNEL_5 (0x00000010U)
#define | LL_IPCC_CHANNEL_6 (0x00000020U)

Define Documentation

#define LL_IPCC_CHANNEL_1 (0x00000001U)

IPCC Channel 1

Definition at line 75 of file stm32wbxx_ll_ipcc.h.

#define LL_IPCC_CHANNEL_2 (0x00000002U)

IPCC Channel 2

Definition at line 76 of file stm32wbxx_ll_ipcc.h.

#define LL_IPCC_CHANNEL_3 (0x00000004U)

IPCC Channel 3

Definition at line 77 of file stm32wbxx_ll_ipcc.h.

#define LL_IPCC_CHANNEL_4 (0x00000008U)

IPCC Channel 4

Definition at line 78 of file stm32wbxx_ll_ipcc.h.

#define LL_IPCC_CHANNEL_5 (0x00000010U)

IPCC Channel 5

Definition at line 79 of file stm32wbxx_ll_ipcc.h.

#define LL_IPCC_CHANNEL_6 (0x00000020U)

IPCC Channel 6

Definition at line 80 of file stm32wbxx_ll_ipcc.h.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
IPCC Exported Macros

Defines

#define | LL_IPCC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in IPCC register.
#define | LL_IPCC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in IPCC register.

Define Documentation

#define LL_IPCC_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in IPCC register.

Parameters:
__INSTANCE__ | IPCC Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 113 of file stm32wbxx_ll_ipcc.h.

#define LL_IPCC_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in IPCC register.

Parameters:
__INSTANCE__ | IPCC Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 105 of file stm32wbxx_ll_ipcc.h.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IT_Management

Functions
IT_Management
IPCC Exported Functions

Functions

__STATIC_INLINE void | LL_C1_IPCC_EnableIT_TXF (IPCC_TypeDef *IPCCx)
Enable Transmit channel free interrupt for processor 1.
__STATIC_INLINE void | LL_C1_IPCC_DisableIT_TXF (IPCC_TypeDef *IPCCx)
Disable Transmit channel free interrupt for processor 1.
__STATIC_INLINE uint32_t | LL_C1_IPCC_IsEnabledIT_TXF (IPCC_TypeDef const *const IPCCx)
Check if Transmit channel free interrupt for processor 1 is enabled.
__STATIC_INLINE void | LL_C1_IPCC_EnableIT_RXO (IPCC_TypeDef *IPCCx)
Enable Receive channel occupied interrupt for processor 1.
__STATIC_INLINE void | LL_C1_IPCC_DisableIT_RXO (IPCC_TypeDef *IPCCx)
Disable Receive channel occupied interrupt for processor 1.
__STATIC_INLINE uint32_t | LL_C1_IPCC_IsEnabledIT_RXO (IPCC_TypeDef const *const IPCCx)
Check if Receive channel occupied interrupt for processor 1 is enabled.
__STATIC_INLINE void | LL_C2_IPCC_EnableIT_TXF (IPCC_TypeDef *IPCCx)
Enable Transmit channel free interrupt for processor 2.
__STATIC_INLINE void | LL_C2_IPCC_DisableIT_TXF (IPCC_TypeDef *IPCCx)
Disable Transmit channel free interrupt for processor 2.
__STATIC_INLINE uint32_t | LL_C2_IPCC_IsEnabledIT_TXF (IPCC_TypeDef const *const IPCCx)
Check if Transmit channel free interrupt for processor 2 is enabled.
__STATIC_INLINE void | LL_C2_IPCC_EnableIT_RXO (IPCC_TypeDef *IPCCx)
Enable Receive channel occupied interrupt for processor 2.
__STATIC_INLINE void | LL_C2_IPCC_DisableIT_RXO (IPCC_TypeDef *IPCCx)
Disable Receive channel occupied interrupt for processor 2.
__STATIC_INLINE uint32_t | LL_C2_IPCC_IsEnabledIT_RXO (IPCC_TypeDef const *const IPCCx)
Check if Receive channel occupied interrupt for processor 2 is enabled.

Function Documentation

__STATIC_INLINE void LL_C1_IPCC_DisableIT_RXO ( IPCC_TypeDef * IPCCx )

Disable Receive channel occupied interrupt for processor 1.

Reference Manual to LL API cross reference:
C1CR RXOIE LL_C1_IPCC_DisableIT_RXO
Parameters:
IPCCx IPCC Instance.
Return values:
None

Definition at line 182 of file stm32wbxx_ll_ipcc.h.

__STATIC_INLINE void LL_C1_IPCC_DisableIT_TXF ( IPCC_TypeDef * IPCCx )

Disable Transmit channel free interrupt for processor 1.

Reference Manual to LL API cross reference:
C1CR TXFIE LL_C1_IPCC_DisableIT_TXF
Parameters:
IPCCx IPCC Instance.
Return values:
None

Definition at line 149 of file stm32wbxx_ll_ipcc.h.

__STATIC_INLINE void LL_C1_IPCC_EnableIT_RXO ( IPCC_TypeDef * IPCCx )

Enable Receive channel occupied interrupt for processor 1.

Reference Manual to LL API cross reference:
C1CR RXOIE LL_C1_IPCC_EnableIT_RXO
Parameters:
IPCCx IPCC Instance.
Return values:
None

Definition at line 171 of file stm32wbxx_ll_ipcc.h.

__STATIC_INLINE void LL_C1_IPCC_EnableIT_TXF ( IPCC_TypeDef * IPCCx )

Enable Transmit channel free interrupt for processor 1.

Reference Manual to LL API cross reference:
C1CR TXFIE LL_C1_IPCC_EnableIT_TXF
Parameters:
IPCCx IPCC Instance.
Return values:
None

Definition at line 138 of file stm32wbxx_ll_ipcc.h.

__STATIC_INLINE uint32_t LL_C1_IPCC_IsEnabledIT_RXO ( IPCC_TypeDef const *const IPCCx )

Check if Receive channel occupied interrupt for processor 1 is enabled.

Reference Manual to LL API cross reference:
C1CR RXOIE LL_C1_IPCC_IsEnabledIT_RXO
Parameters:
IPCCx IPCC Instance.
Return values:
State of bit (1 or 0).

Definition at line 193 of file stm32wbxx_ll_ipcc.h.

__STATIC_INLINE uint32_t LL_C1_IPCC_IsEnabledIT_TXF ( IPCC_TypeDef const *const IPCCx )

Check if Transmit channel free interrupt for processor 1 is enabled.

Reference Manual to LL API cross reference:
C1CR TXFIE LL_C1_IPCC_IsEnabledIT_TXF
Parameters:
IPCCx IPCC Instance.
Return values:
State of bit (1 or 0).

Definition at line 160 of file stm32wbxx_ll_ipcc.h.

__STATIC_INLINE void LL_C2_IPCC_DisableIT_RXO ( IPCC_TypeDef * IPCCx )

Disable Receive channel occupied interrupt for processor 2.

Reference Manual to LL API cross reference:
C2CR RXOIE LL_C2_IPCC_DisableIT_RXO
Parameters:
IPCCx IPCC Instance.
Return values:
None

Definition at line 248 of file stm32wbxx_ll_ipcc.h.

__STATIC_INLINE void LL_C2_IPCC_DisableIT_TXF ( IPCC_TypeDef * IPCCx )

Disable Transmit channel free interrupt for processor 2.

Reference Manual to LL API cross reference:
C2CR TXFIE LL_C2_IPCC_DisableIT_TXF
Parameters:
IPCCx IPCC Instance.
Return values:
None

Definition at line 215 of file stm32wbxx_ll_ipcc.h.

__STATIC_INLINE void LL_C2_IPCC_EnableIT_RXO ( IPCC_TypeDef * IPCCx )

Enable Receive channel occupied interrupt for processor 2.

Reference Manual to LL API cross reference:
C2CR RXOIE LL_C2_IPCC_EnableIT_RXO
Parameters:
IPCCx IPCC Instance.
Return values:
None

Definition at line 237 of file stm32wbxx_ll_ipcc.h.

__STATIC_INLINE void LL_C2_IPCC_EnableIT_TXF ( IPCC_TypeDef * IPCCx )

Enable Transmit channel free interrupt for processor 2.

Reference Manual to LL API cross reference:
C2CR TXFIE LL_C2_IPCC_EnableIT_TXF
Parameters:
IPCCx IPCC Instance.
Return values:
None

Definition at line 204 of file stm32wbxx_ll_ipcc.h.

__STATIC_INLINE uint32_t LL_C2_IPCC_IsEnabledIT_RXO ( IPCC_TypeDef const *const IPCCx )

Check if Receive channel occupied interrupt for processor 2 is enabled.

Reference Manual to LL API cross reference:
C2CR RXOIE LL_C2_IPCC_IsEnabledIT_RXO
Parameters:
IPCCx IPCC Instance.
Return values:
State of bit (1 or 0).

Definition at line 259 of file stm32wbxx_ll_ipcc.h.

__STATIC_INLINE uint32_t LL_C2_IPCC_IsEnabledIT_TXF ( IPCC_TypeDef const *const IPCCx )

Check if Transmit channel free interrupt for processor 2 is enabled.

Reference Manual to LL API cross reference:
C2CR TXFIE LL_C2_IPCC_IsEnabledIT_TXF
Parameters:
IPCCx IPCC Instance.
Return values:
State of bit (1 or 0).

Definition at line 226 of file stm32wbxx_ll_ipcc.h.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Configuration

Functions
Configuration
IPCC Exported Functions

Functions

__STATIC_INLINE void | LL_C1_IPCC_EnableTransmitChannel (IPCC_TypeDef *IPCCx, uint32_t Channel)
Unmask transmit channel free interrupt for processor 1.
__STATIC_INLINE void | LL_C1_IPCC_DisableTransmitChannel (IPCC_TypeDef *IPCCx, uint32_t Channel)
Mask transmit channel free interrupt for processor 1.
__STATIC_INLINE uint32_t | LL_C1_IPCC_IsEnabledTransmitChannel (IPCC_TypeDef const *const IPCCx, uint32_t Channel)
Check if Transmit channel free interrupt for processor 1 is masked.
__STATIC_INLINE void | LL_C1_IPCC_EnableReceiveChannel (IPCC_TypeDef *IPCCx, uint32_t Channel)
Unmask receive channel occupied interrupt for processor 1.
__STATIC_INLINE void | LL_C1_IPCC_DisableReceiveChannel (IPCC_TypeDef *IPCCx, uint32_t Channel)
Mask receive channel occupied interrupt for processor 1.
__STATIC_INLINE uint32_t | LL_C1_IPCC_IsEnabledReceiveChannel (IPCC_TypeDef const *const IPCCx, uint32_t Channel)
Check if Receive channel occupied interrupt for processor 1 is masked.
__STATIC_INLINE void | LL_C2_IPCC_EnableTransmitChannel (IPCC_TypeDef *IPCCx, uint32_t Channel)
Unmask transmit channel free interrupt for processor 2.
__STATIC_INLINE void | LL_C2_IPCC_DisableTransmitChannel (IPCC_TypeDef *IPCCx, uint32_t Channel)
Mask transmit channel free interrupt for processor 2.
__STATIC_INLINE uint32_t | LL_C2_IPCC_IsEnabledTransmitChannel (IPCC_TypeDef const *const IPCCx, uint32_t Channel)
Check if Transmit channel free interrupt for processor 2 is masked.
__STATIC_INLINE void | LL_C2_IPCC_EnableReceiveChannel (IPCC_TypeDef *IPCCx, uint32_t Channel)
Unmask receive channel occupied interrupt for processor 2.
__STATIC_INLINE void | LL_C2_IPCC_DisableReceiveChannel (IPCC_TypeDef *IPCCx, uint32_t Channel)
Mask receive channel occupied interrupt for processor 1.
__STATIC_INLINE uint32_t | LL_C2_IPCC_IsEnabledReceiveChannel (IPCC_TypeDef const *const IPCCx, uint32_t Channel)
Check if Receive channel occupied interrupt for processor 2 is masked.

Function Documentation

__STATIC_INLINE void LL_C1_IPCC_DisableReceiveChannel | ( | IPCC_TypeDef * | IPCCx,
 |  | uint32_t | Channel
 | ) |  |

Mask receive channel occupied interrupt for processor 1.

Reference Manual to LL API cross reference:
C1MR CH1OM LL_C1_IPCC_DisableReceiveChannel
C1MR CH2OM LL_C1_IPCC_DisableReceiveChannel
C1MR CH3OM LL_C1_IPCC_DisableReceiveChannel
C1MR CH4OM LL_C1_IPCC_DisableReceiveChannel
C1MR CH5OM LL_C1_IPCC_DisableReceiveChannel
C1MR CH6OM LL_C1_IPCC_DisableReceiveChannel
Parameters:
IPCCx IPCC Instance.
Channel This parameter can be a combination of the following values:
  • LL_IPCC_CHANNEL_1
  • LL_IPCC_CHANNEL_2
  • LL_IPCC_CHANNEL_3
  • LL_IPCC_CHANNEL_4
  • LL_IPCC_CHANNEL_5
  • LL_IPCC_CHANNEL_6
Return values:
None

Definition at line 382 of file stm32wbxx_ll_ipcc.h.

__STATIC_INLINE void LL_C1_IPCC_DisableTransmitChannel | ( | IPCC_TypeDef * | IPCCx,
 |  | uint32_t | Channel
 | ) |  |

Mask transmit channel free interrupt for processor 1.

Reference Manual to LL API cross reference:
C1MR CH1FM LL_C1_IPCC_DisableTransmitChannel
C1MR CH2FM LL_C1_IPCC_DisableTransmitChannel
C1MR CH3FM LL_C1_IPCC_DisableTransmitChannel
C1MR CH4FM LL_C1_IPCC_DisableTransmitChannel
C1MR CH5FM LL_C1_IPCC_DisableTransmitChannel
C1MR CH6FM LL_C1_IPCC_DisableTransmitChannel
Parameters:
IPCCx IPCC Instance.
Channel This parameter can be a combination of the following values:
  • LL_IPCC_CHANNEL_1
  • LL_IPCC_CHANNEL_2
  • LL_IPCC_CHANNEL_3
  • LL_IPCC_CHANNEL_4
  • LL_IPCC_CHANNEL_5
  • LL_IPCC_CHANNEL_6
Return values:
None

Definition at line 313 of file stm32wbxx_ll_ipcc.h.

__STATIC_INLINE void LL_C1_IPCC_EnableReceiveChannel | ( | IPCC_TypeDef * | IPCCx,
 |  | uint32_t | Channel
 | ) |  |

Unmask receive channel occupied interrupt for processor 1.

Reference Manual to LL API cross reference:
C1MR CH1OM LL_C1_IPCC_EnableReceiveChannel
C1MR CH2OM LL_C1_IPCC_EnableReceiveChannel
C1MR CH3OM LL_C1_IPCC_EnableReceiveChannel
C1MR CH4OM LL_C1_IPCC_EnableReceiveChannel
C1MR CH5OM LL_C1_IPCC_EnableReceiveChannel
C1MR CH6OM LL_C1_IPCC_EnableReceiveChannel
Parameters:
IPCCx IPCC Instance.
Channel This parameter can be a combination of the following values:
  • LL_IPCC_CHANNEL_1
  • LL_IPCC_CHANNEL_2
  • LL_IPCC_CHANNEL_3
  • LL_IPCC_CHANNEL_4
  • LL_IPCC_CHANNEL_5
  • LL_IPCC_CHANNEL_6
Return values:
None

Definition at line 359 of file stm32wbxx_ll_ipcc.h.

__STATIC_INLINE void LL_C1_IPCC_EnableTransmitChannel | ( | IPCC_TypeDef * | IPCCx,
 |  | uint32_t | Channel
 | ) |  |

Unmask transmit channel free interrupt for processor 1.

Reference Manual to LL API cross reference:
C1MR CH1FM LL_C1_IPCC_EnableTransmitChannel
C1MR CH2FM LL_C1_IPCC_EnableTransmitChannel
C1MR CH3FM LL_C1_IPCC_EnableTransmitChannel
C1MR CH4FM LL_C1_IPCC_EnableTransmitChannel
C1MR CH5FM LL_C1_IPCC_EnableTransmitChannel
C1MR CH6FM LL_C1_IPCC_EnableTransmitChannel
Parameters:
IPCCx IPCC Instance.
Channel This parameter can be a combination of the following values:
  • LL_IPCC_CHANNEL_1
  • LL_IPCC_CHANNEL_2
  • LL_IPCC_CHANNEL_3
  • LL_IPCC_CHANNEL_4
  • LL_IPCC_CHANNEL_5
  • LL_IPCC_CHANNEL_6
Return values:
None

Definition at line 290 of file stm32wbxx_ll_ipcc.h.

__STATIC_INLINE uint32_t LL_C1_IPCC_IsEnabledReceiveChannel | ( | IPCC_TypeDef const *const | IPCCx,
 |  | uint32_t | Channel
 | ) |  |

Check if Receive channel occupied interrupt for processor 1 is masked.

Reference Manual to LL API cross reference:
C1MR CH1OM LL_C1_IPCC_IsEnabledReceiveChannel
C1MR CH2OM LL_C1_IPCC_IsEnabledReceiveChannel
C1MR CH3OM LL_C1_IPCC_IsEnabledReceiveChannel
C1MR CH4OM LL_C1_IPCC_IsEnabledReceiveChannel
C1MR CH5OM LL_C1_IPCC_IsEnabledReceiveChannel
C1MR CH6OM LL_C1_IPCC_IsEnabledReceiveChannel
Parameters:
IPCCx IPCC Instance.
Channel This parameter can be one of the following values:
  • LL_IPCC_CHANNEL_1
  • LL_IPCC_CHANNEL_2
  • LL_IPCC_CHANNEL_3
  • LL_IPCC_CHANNEL_4
  • LL_IPCC_CHANNEL_5
  • LL_IPCC_CHANNEL_6
Return values:
State of bit (1 or 0).

Definition at line 405 of file stm32wbxx_ll_ipcc.h.

__STATIC_INLINE uint32_t LL_C1_IPCC_IsEnabledTransmitChannel | ( | IPCC_TypeDef const *const | IPCCx,
 |  | uint32_t | Channel
 | ) |  |

Check if Transmit channel free interrupt for processor 1 is masked.

Reference Manual to LL API cross reference:
C1MR CH1FM LL_C1_IPCC_IsEnabledTransmitChannel
C1MR CH2FM LL_C1_IPCC_IsEnabledTransmitChannel
C1MR CH3FM LL_C1_IPCC_IsEnabledTransmitChannel
C1MR CH4FM LL_C1_IPCC_IsEnabledTransmitChannel
C1MR CH5FM LL_C1_IPCC_IsEnabledTransmitChannel
C1MR CH6FM LL_C1_IPCC_IsEnabledTransmitChannel
Parameters:
IPCCx IPCC Instance.
Channel This parameter can be one of the following values:
  • LL_IPCC_CHANNEL_1
  • LL_IPCC_CHANNEL_2
  • LL_IPCC_CHANNEL_3
  • LL_IPCC_CHANNEL_4
  • LL_IPCC_CHANNEL_5
  • LL_IPCC_CHANNEL_6
Return values:
State of bit (1 or 0).

Definition at line 336 of file stm32wbxx_ll_ipcc.h.

__STATIC_INLINE void LL_C2_IPCC_DisableReceiveChannel | ( | IPCC_TypeDef * | IPCCx,
 |  | uint32_t | Channel
 | ) |  |

Mask receive channel occupied interrupt for processor 1.

Reference Manual to LL API cross reference:
C2MR CH1OM LL_C2_IPCC_DisableReceiveChannel
C2MR CH2OM LL_C2_IPCC_DisableReceiveChannel
C2MR CH3OM LL_C2_IPCC_DisableReceiveChannel
C2MR CH4OM LL_C2_IPCC_DisableReceiveChannel
C2MR CH5OM LL_C2_IPCC_DisableReceiveChannel
C2MR CH6OM LL_C2_IPCC_DisableReceiveChannel
Parameters:
IPCCx IPCC Instance.
Channel This parameter can be a combination of the following values:
  • LL_IPCC_CHANNEL_1
  • LL_IPCC_CHANNEL_2
  • LL_IPCC_CHANNEL_3
  • LL_IPCC_CHANNEL_4
  • LL_IPCC_CHANNEL_5
  • LL_IPCC_CHANNEL_6
Return values:
None

Definition at line 520 of file stm32wbxx_ll_ipcc.h.

__STATIC_INLINE void LL_C2_IPCC_DisableTransmitChannel | ( | IPCC_TypeDef * | IPCCx,
 |  | uint32_t | Channel
 | ) |  |

Mask transmit channel free interrupt for processor 2.

Reference Manual to LL API cross reference:
C2MR CH1FM LL_C2_IPCC_DisableTransmitChannel
C2MR CH2FM LL_C2_IPCC_DisableTransmitChannel
C2MR CH3FM LL_C2_IPCC_DisableTransmitChannel
C2MR CH4FM LL_C2_IPCC_DisableTransmitChannel
C2MR CH5FM LL_C2_IPCC_DisableTransmitChannel
C2MR CH6FM LL_C2_IPCC_DisableTransmitChannel
Parameters:
IPCCx IPCC Instance.
Channel This parameter can be a combination of the following values:
  • LL_IPCC_CHANNEL_1
  • LL_IPCC_CHANNEL_2
  • LL_IPCC_CHANNEL_3
  • LL_IPCC_CHANNEL_4
  • LL_IPCC_CHANNEL_5
  • LL_IPCC_CHANNEL_6
Return values:
None

Definition at line 451 of file stm32wbxx_ll_ipcc.h.

__STATIC_INLINE void LL_C2_IPCC_EnableReceiveChannel | ( | IPCC_TypeDef * | IPCCx,
 |  | uint32_t | Channel
 | ) |  |

Unmask receive channel occupied interrupt for processor 2.

Reference Manual to LL API cross reference:
C2MR CH1OM LL_C2_IPCC_EnableReceiveChannel
C2MR CH2OM LL_C2_IPCC_EnableReceiveChannel
C2MR CH3OM LL_C2_IPCC_EnableReceiveChannel
C2MR CH4OM LL_C2_IPCC_EnableReceiveChannel
C2MR CH5OM LL_C2_IPCC_EnableReceiveChannel
C2MR CH6OM LL_C2_IPCC_EnableReceiveChannel
Parameters:
IPCCx IPCC Instance.
Channel This parameter can be a combination of the following values:
  • LL_IPCC_CHANNEL_1
  • LL_IPCC_CHANNEL_2
  • LL_IPCC_CHANNEL_3
  • LL_IPCC_CHANNEL_4
  • LL_IPCC_CHANNEL_5
  • LL_IPCC_CHANNEL_6
Return values:
None

Definition at line 497 of file stm32wbxx_ll_ipcc.h.

__STATIC_INLINE void LL_C2_IPCC_EnableTransmitChannel | ( | IPCC_TypeDef * | IPCCx,
 |  | uint32_t | Channel
 | ) |  |

Unmask transmit channel free interrupt for processor 2.

Reference Manual to LL API cross reference:
C2MR CH1FM LL_C2_IPCC_EnableTransmitChannel
C2MR CH2FM LL_C2_IPCC_EnableTransmitChannel
C2MR CH3FM LL_C2_IPCC_EnableTransmitChannel
C2MR CH4FM LL_C2_IPCC_EnableTransmitChannel
C2MR CH5FM LL_C2_IPCC_EnableTransmitChannel
C2MR CH6FM LL_C2_IPCC_EnableTransmitChannel
Parameters:
IPCCx IPCC Instance.
Channel This parameter can be a combination of the following values:
  • LL_IPCC_CHANNEL_1
  • LL_IPCC_CHANNEL_2
  • LL_IPCC_CHANNEL_3
  • LL_IPCC_CHANNEL_4
  • LL_IPCC_CHANNEL_5
  • LL_IPCC_CHANNEL_6
Return values:
None

Definition at line 428 of file stm32wbxx_ll_ipcc.h.

__STATIC_INLINE uint32_t LL_C2_IPCC_IsEnabledReceiveChannel | ( | IPCC_TypeDef const *const | IPCCx,
 |  | uint32_t | Channel
 | ) |  |

Check if Receive channel occupied interrupt for processor 2 is masked.

Reference Manual to LL API cross reference:
C2MR CH1OM LL_C2_IPCC_IsEnabledReceiveChannel
C2MR CH2OM LL_C2_IPCC_IsEnabledReceiveChannel
C2MR CH3OM LL_C2_IPCC_IsEnabledReceiveChannel
C2MR CH4OM LL_C2_IPCC_IsEnabledReceiveChannel
C2MR CH5OM LL_C2_IPCC_IsEnabledReceiveChannel
C2MR CH6OM LL_C2_IPCC_IsEnabledReceiveChannel
Parameters:
IPCCx IPCC Instance.
Channel This parameter can be one of the following values:
  • LL_IPCC_CHANNEL_1
  • LL_IPCC_CHANNEL_2
  • LL_IPCC_CHANNEL_3
  • LL_IPCC_CHANNEL_4
  • LL_IPCC_CHANNEL_5
  • LL_IPCC_CHANNEL_6
Return values:
State of bit (1 or 0).

Definition at line 543 of file stm32wbxx_ll_ipcc.h.

__STATIC_INLINE uint32_t LL_C2_IPCC_IsEnabledTransmitChannel | ( | IPCC_TypeDef const *const | IPCCx,
 |  | uint32_t | Channel
 | ) |  |

Check if Transmit channel free interrupt for processor 2 is masked.

Reference Manual to LL API cross reference:
C2MR CH1FM LL_C2_IPCC_IsEnabledTransmitChannel
C2MR CH2FM LL_C2_IPCC_IsEnabledTransmitChannel
C2MR CH3FM LL_C2_IPCC_IsEnabledTransmitChannel
C2MR CH4FM LL_C2_IPCC_IsEnabledTransmitChannel
C2MR CH5FM LL_C2_IPCC_IsEnabledTransmitChannel
C2MR CH6FM LL_C2_IPCC_IsEnabledTransmitChannel
Parameters:
IPCCx IPCC Instance.
Channel This parameter can be one of the following values:
  • LL_IPCC_CHANNEL_1
  • LL_IPCC_CHANNEL_2
  • LL_IPCC_CHANNEL_3
  • LL_IPCC_CHANNEL_4
  • LL_IPCC_CHANNEL_5
  • LL_IPCC_CHANNEL_6
Return values:
State of bit (1 or 0).

Definition at line 474 of file stm32wbxx_ll_ipcc.h.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FLAG_Management

Functions
FLAG_Management
IPCC Exported Functions

Functions

__STATIC_INLINE void | LL_C1_IPCC_ClearFlag_CHx (IPCC_TypeDef *IPCCx, uint32_t Channel)
Clear IPCC receive channel status for processor 1.
__STATIC_INLINE void | LL_C1_IPCC_SetFlag_CHx (IPCC_TypeDef *IPCCx, uint32_t Channel)
Set IPCC transmit channel status for processor 1.
__STATIC_INLINE uint32_t | LL_C1_IPCC_IsActiveFlag_CHx (IPCC_TypeDef const *const IPCCx, uint32_t Channel)
Get channel status for processor 1.
__STATIC_INLINE void | LL_C2_IPCC_ClearFlag_CHx (IPCC_TypeDef *IPCCx, uint32_t Channel)
Clear IPCC receive channel status for processor 2.
__STATIC_INLINE void | LL_C2_IPCC_SetFlag_CHx (IPCC_TypeDef *IPCCx, uint32_t Channel)
Set IPCC transmit channel status for processor 2.
__STATIC_INLINE uint32_t | LL_C2_IPCC_IsActiveFlag_CHx (IPCC_TypeDef const *const IPCCx, uint32_t Channel)
Get channel status for processor 2.

Function Documentation

__STATIC_INLINE void LL_C1_IPCC_ClearFlag_CHx | ( | IPCC_TypeDef * | IPCCx,
 |  | uint32_t | Channel
 | ) |  |

Clear IPCC receive channel status for processor 1.

Note:
Associated with IPCC_C2TOC1SR.CHxF
Reference Manual to LL API cross reference:
C1SCR CH1C LL_C1_IPCC_ClearFlag_CHx
C1SCR CH2C LL_C1_IPCC_ClearFlag_CHx
C1SCR CH3C LL_C1_IPCC_ClearFlag_CHx
C1SCR CH4C LL_C1_IPCC_ClearFlag_CHx
C1SCR CH5C LL_C1_IPCC_ClearFlag_CHx
C1SCR CH6C LL_C1_IPCC_ClearFlag_CHx
Parameters:
IPCCx IPCC Instance.
Channel This parameter can be a combination of the following values:
  • LL_IPCC_CHANNEL_1
  • LL_IPCC_CHANNEL_2
  • LL_IPCC_CHANNEL_3
  • LL_IPCC_CHANNEL_4
  • LL_IPCC_CHANNEL_5
  • LL_IPCC_CHANNEL_6
Return values:
None

Definition at line 575 of file stm32wbxx_ll_ipcc.h.

__STATIC_INLINE uint32_t LL_C1_IPCC_IsActiveFlag_CHx | ( | IPCC_TypeDef const *const | IPCCx,
 |  | uint32_t | Channel
 | ) |  |

Get channel status for processor 1.

Reference Manual to LL API cross reference:
C1TOC2SR CH1F LL_C1_IPCC_IsActiveFlag_CHx
C1TOC2SR CH2F LL_C1_IPCC_IsActiveFlag_CHx
C1TOC2SR CH3F LL_C1_IPCC_IsActiveFlag_CHx
C1TOC2SR CH4F LL_C1_IPCC_IsActiveFlag_CHx
C1TOC2SR CH5F LL_C1_IPCC_IsActiveFlag_CHx
C1TOC2SR CH6F LL_C1_IPCC_IsActiveFlag_CHx
Parameters:
IPCCx IPCC Instance.
Channel This parameter can be one of the following values:
  • LL_IPCC_CHANNEL_1
  • LL_IPCC_CHANNEL_2
  • LL_IPCC_CHANNEL_3
  • LL_IPCC_CHANNEL_4
  • LL_IPCC_CHANNEL_5
  • LL_IPCC_CHANNEL_6
Return values:
State of bit (1 or 0).

Definition at line 622 of file stm32wbxx_ll_ipcc.h.

__STATIC_INLINE void LL_C1_IPCC_SetFlag_CHx | ( | IPCC_TypeDef * | IPCCx,
 |  | uint32_t | Channel
 | ) |  |

Set IPCC transmit channel status for processor 1.

Note:
Associated with IPCC_C1TOC2SR.CHxF
Reference Manual to LL API cross reference:
C1SCR CH1S LL_C1_IPCC_SetFlag_CHx
C1SCR CH2S LL_C1_IPCC_SetFlag_CHx
C1SCR CH3S LL_C1_IPCC_SetFlag_CHx
C1SCR CH4S LL_C1_IPCC_SetFlag_CHx
C1SCR CH5S LL_C1_IPCC_SetFlag_CHx
C1SCR CH6S LL_C1_IPCC_SetFlag_CHx
Parameters:
IPCCx IPCC Instance.
Channel This parameter can be a combination of the following values:
  • LL_IPCC_CHANNEL_1
  • LL_IPCC_CHANNEL_2
  • LL_IPCC_CHANNEL_3
  • LL_IPCC_CHANNEL_4
  • LL_IPCC_CHANNEL_5
  • LL_IPCC_CHANNEL_6
Return values:
None

Definition at line 599 of file stm32wbxx_ll_ipcc.h.

__STATIC_INLINE void LL_C2_IPCC_ClearFlag_CHx | ( | IPCC_TypeDef * | IPCCx,
 |  | uint32_t | Channel
 | ) |  |

Clear IPCC receive channel status for processor 2.

Note:
Associated with IPCC_C1TOC2SR.CHxF
Reference Manual to LL API cross reference:
C2SCR CH1C LL_C2_IPCC_ClearFlag_CHx
C2SCR CH2C LL_C2_IPCC_ClearFlag_CHx
C2SCR CH3C LL_C2_IPCC_ClearFlag_CHx
C2SCR CH4C LL_C2_IPCC_ClearFlag_CHx
C2SCR CH5C LL_C2_IPCC_ClearFlag_CHx
C2SCR CH6C LL_C2_IPCC_ClearFlag_CHx
Parameters:
IPCCx IPCC Instance.
Channel This parameter can be a combination of the following values:
  • LL_IPCC_CHANNEL_1
  • LL_IPCC_CHANNEL_2
  • LL_IPCC_CHANNEL_3
  • LL_IPCC_CHANNEL_4
  • LL_IPCC_CHANNEL_5
  • LL_IPCC_CHANNEL_6
Return values:
None

Definition at line 646 of file stm32wbxx_ll_ipcc.h.

__STATIC_INLINE uint32_t LL_C2_IPCC_IsActiveFlag_CHx | ( | IPCC_TypeDef const *const | IPCCx,
 |  | uint32_t | Channel
 | ) |  |

Get channel status for processor 2.

Reference Manual to LL API cross reference:
C2TOC1SR CH1F LL_C2_IPCC_IsActiveFlag_CHx
C2TOC1SR CH2F LL_C2_IPCC_IsActiveFlag_CHx
C2TOC1SR CH3F LL_C2_IPCC_IsActiveFlag_CHx
C2TOC1SR CH4F LL_C2_IPCC_IsActiveFlag_CHx
C2TOC1SR CH5F LL_C2_IPCC_IsActiveFlag_CHx
C2TOC1SR CH6F LL_C2_IPCC_IsActiveFlag_CHx
Parameters:
IPCCx IPCC Instance.
Channel This parameter can be one of the following values:
  • LL_IPCC_CHANNEL_1
  • LL_IPCC_CHANNEL_2
  • LL_IPCC_CHANNEL_3
  • LL_IPCC_CHANNEL_4
  • LL_IPCC_CHANNEL_5
  • LL_IPCC_CHANNEL_6
Return values:
State of bit (1 or 0).

Definition at line 693 of file stm32wbxx_ll_ipcc.h.

__STATIC_INLINE void LL_C2_IPCC_SetFlag_CHx | ( | IPCC_TypeDef * | IPCCx,
 |  | uint32_t | Channel
 | ) |  |

Set IPCC transmit channel status for processor 2.

Note:
Associated with IPCC_C2TOC1SR.CHxF
Reference Manual to LL API cross reference:
C2SCR CH1S LL_C2_IPCC_SetFlag_CHx
C2SCR CH2S LL_C2_IPCC_SetFlag_CHx
C2SCR CH3S LL_C2_IPCC_SetFlag_CHx
C2SCR CH4S LL_C2_IPCC_SetFlag_CHx
C2SCR CH5S LL_C2_IPCC_SetFlag_CHx
C2SCR CH6S LL_C2_IPCC_SetFlag_CHx
Parameters:
IPCCx IPCC Instance.
Channel This parameter can be a combination of the following values:
  • LL_IPCC_CHANNEL_1
  • LL_IPCC_CHANNEL_2
  • LL_IPCC_CHANNEL_3
  • LL_IPCC_CHANNEL_4
  • LL_IPCC_CHANNEL_5
  • LL_IPCC_CHANNEL_6
Return values:
None

Definition at line 670 of file stm32wbxx_ll_ipcc.h.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IWDG

Modules
IWDG
STM32WBxx_LL_Driver

Modules

IWDG Private Constants
IWDG Exported Constants
IWDG Exported Macros
IWDG Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for IWDG registers.

Register | Bit | Function
KR | KEY | LL_IWDG_DisableWriteAccess
 |  | LL_IWDG_Enable
 |  | LL_IWDG_EnableWriteAccess
 |  | LL_IWDG_ReloadCounter
PR | PR | LL_IWDG_GetPrescaler
 |  | LL_IWDG_SetPrescaler
RLR | RL | LL_IWDG_GetReloadCounter
 |  | LL_IWDG_SetReloadCounter
SR | PVU | LL_IWDG_IsActiveFlag_PVU
 |  | LL_IWDG_IsReady
 | RVU | LL_IWDG_IsActiveFlag_RVU
 |  | LL_IWDG_IsReady
 | WVU | LL_IWDG_IsActiveFlag_WVU
 |  | LL_IWDG_IsReady
WINR | WIN | LL_IWDG_GetWindow
 |  | LL_IWDG_SetWindow
Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IWDG Private Constants

Defines
IWDG Private Constants
IWDG

Defines

#define | LL_IWDG_KEY_RELOAD 0x0000AAAAU
#define | LL_IWDG_KEY_ENABLE 0x0000CCCCU
#define | LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U
#define | LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U

Define Documentation

#define LL_IWDG_KEY_ENABLE 0x0000CCCCU

IWDG Peripheral Enable

Definition at line 49 of file stm32wbxx_ll_iwdg.h.

Referenced by LL_IWDG_Enable().

#define LL_IWDG_KEY_RELOAD 0x0000AAAAU

IWDG Reload Counter Enable

Definition at line 48 of file stm32wbxx_ll_iwdg.h.

Referenced by LL_IWDG_ReloadCounter().

#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U

IWDG KR Write Access Disable

Definition at line 51 of file stm32wbxx_ll_iwdg.h.

Referenced by LL_IWDG_DisableWriteAccess().

#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U

IWDG KR Write Access Enable

Definition at line 50 of file stm32wbxx_ll_iwdg.h.

Referenced by LL_IWDG_EnableWriteAccess().

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
IWDG Exported Constants

Flags defines which can be used with LL_IWDG_ReadReg function. More...

Defines

#define | LL_IWDG_SR_PVU IWDG_SR_PVU
#define | LL_IWDG_SR_RVU IWDG_SR_RVU
#define | LL_IWDG_SR_WVU IWDG_SR_WVU

Detailed Description

Flags defines which can be used with LL_IWDG_ReadReg function.

Define Documentation

#define LL_IWDG_SR_PVU IWDG_SR_PVU

Watchdog prescaler value update

Definition at line 68 of file stm32wbxx_ll_iwdg.h.

#define LL_IWDG_SR_RVU IWDG_SR_RVU

Watchdog counter reload value update

Definition at line 69 of file stm32wbxx_ll_iwdg.h.

#define LL_IWDG_SR_WVU IWDG_SR_WVU

Watchdog counter window value update

Definition at line 70 of file stm32wbxx_ll_iwdg.h.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Prescaler Divider

Defines
Prescaler Divider
IWDG Exported Constants

Defines

#define | LL_IWDG_PRESCALER_4 0x00000000U
#define | LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1)
#define | LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2)
#define | LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)

Define Documentation

#define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)

Divider by 128

Definition at line 83 of file stm32wbxx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1)

Divider by 16

Definition at line 80 of file stm32wbxx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)

Divider by 256

Definition at line 84 of file stm32wbxx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)

Divider by 32

Definition at line 81 of file stm32wbxx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_4 0x00000000U

Divider by 4

Definition at line 78 of file stm32wbxx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2)

Divider by 64

Definition at line 82 of file stm32wbxx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0)

Divider by 8

Definition at line 79 of file stm32wbxx_ll_iwdg.h.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
IWDG Exported Macros

Defines

#define | LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in IWDG register.
#define | LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in IWDG register.

Define Documentation

#define LL_IWDG_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in IWDG register.

Parameters:
__INSTANCE__ | IWDG Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 117 of file stm32wbxx_ll_iwdg.h.

#define LL_IWDG_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in IWDG register.

Parameters:
__INSTANCE__ | IWDG Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 109 of file stm32wbxx_ll_iwdg.h.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Configuration

Functions
Configuration
IWDG Exported Functions

Functions

__STATIC_INLINE void | LL_IWDG_Enable (IWDG_TypeDef *IWDGx)
Start the Independent Watchdog.
__STATIC_INLINE void | LL_IWDG_ReloadCounter (IWDG_TypeDef *IWDGx)
Reloads IWDG counter with value defined in the reload register.
__STATIC_INLINE void | LL_IWDG_EnableWriteAccess (IWDG_TypeDef *IWDGx)
Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
__STATIC_INLINE void | LL_IWDG_DisableWriteAccess (IWDG_TypeDef *IWDGx)
Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
__STATIC_INLINE void | LL_IWDG_SetPrescaler (IWDG_TypeDef *IWDGx, uint32_t Prescaler)
Select the prescaler of the IWDG.
__STATIC_INLINE uint32_t | LL_IWDG_GetPrescaler (IWDG_TypeDef *IWDGx)
Get the selected prescaler of the IWDG.
__STATIC_INLINE void | LL_IWDG_SetReloadCounter (IWDG_TypeDef *IWDGx, uint32_t Counter)
Specify the IWDG down-counter reload value.
__STATIC_INLINE uint32_t | LL_IWDG_GetReloadCounter (IWDG_TypeDef *IWDGx)
Get the specified IWDG down-counter reload value.
__STATIC_INLINE void | LL_IWDG_SetWindow (IWDG_TypeDef *IWDGx, uint32_t Window)
Specify high limit of the window value to be compared to the down-counter.
__STATIC_INLINE uint32_t | LL_IWDG_GetWindow (IWDG_TypeDef *IWDGx)
Get the high limit of the window value specified.

Function Documentation

__STATIC_INLINE void LL_IWDG_DisableWriteAccess ( IWDG_TypeDef * IWDGx )

Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.

Reference Manual to LL API cross reference:
KR KEY LL_IWDG_DisableWriteAccess
Parameters:
IWDGx IWDG Instance
Return values:
None

Definition at line 175 of file stm32wbxx_ll_iwdg.h.

References LL_IWDG_KEY_WR_ACCESS_DISABLE.

__STATIC_INLINE void LL_IWDG_Enable ( IWDG_TypeDef * IWDGx )

Start the Independent Watchdog.

Note:
Except if the hardware watchdog option is selected
Reference Manual to LL API cross reference:
KR KEY LL_IWDG_Enable
Parameters:
IWDGx IWDG Instance
Return values:
None

Definition at line 142 of file stm32wbxx_ll_iwdg.h.

References LL_IWDG_KEY_ENABLE.

__STATIC_INLINE void LL_IWDG_EnableWriteAccess ( IWDG_TypeDef * IWDGx )

Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.

Reference Manual to LL API cross reference:
KR KEY LL_IWDG_EnableWriteAccess
Parameters:
IWDGx IWDG Instance
Return values:
None

Definition at line 164 of file stm32wbxx_ll_iwdg.h.

References LL_IWDG_KEY_WR_ACCESS_ENABLE.

__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler ( IWDG_TypeDef * IWDGx )

Get the selected prescaler of the IWDG.

Reference Manual to LL API cross reference:
PR PR LL_IWDG_GetPrescaler
Parameters:
IWDGx IWDG Instance
Return values:
Returned value can be one of the following values:
  • LL_IWDG_PRESCALER_4
  • LL_IWDG_PRESCALER_8
  • LL_IWDG_PRESCALER_16
  • LL_IWDG_PRESCALER_32
  • LL_IWDG_PRESCALER_64
  • LL_IWDG_PRESCALER_128
  • LL_IWDG_PRESCALER_256

Definition at line 212 of file stm32wbxx_ll_iwdg.h.

__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter ( IWDG_TypeDef * IWDGx )

Get the specified IWDG down-counter reload value.

Reference Manual to LL API cross reference:
RLR RL LL_IWDG_GetReloadCounter
Parameters:
IWDGx IWDG Instance
Return values:
Value between Min_Data=0 and Max_Data=0x0FFF

Definition at line 235 of file stm32wbxx_ll_iwdg.h.

__STATIC_INLINE uint32_t LL_IWDG_GetWindow ( IWDG_TypeDef * IWDGx )

Get the high limit of the window value specified.

Reference Manual to LL API cross reference:
WINR WIN LL_IWDG_GetWindow
Parameters:
IWDGx IWDG Instance
Return values:
Value between Min_Data=0 and Max_Data=0x0FFF

Definition at line 258 of file stm32wbxx_ll_iwdg.h.

__STATIC_INLINE void LL_IWDG_ReloadCounter ( IWDG_TypeDef * IWDGx )

Reloads IWDG counter with value defined in the reload register.

Reference Manual to LL API cross reference:
KR KEY LL_IWDG_ReloadCounter
Parameters:
IWDGx IWDG Instance
Return values:
None

Definition at line 153 of file stm32wbxx_ll_iwdg.h.

References LL_IWDG_KEY_RELOAD.

__STATIC_INLINE void LL_IWDG_SetPrescaler | ( | IWDG_TypeDef * | IWDGx,
 |  | uint32_t | Prescaler
 | ) |  |

Select the prescaler of the IWDG.

Reference Manual to LL API cross reference:
PR PR LL_IWDG_SetPrescaler
Parameters:
IWDGx IWDG Instance
Prescaler This parameter can be one of the following values:
  • LL_IWDG_PRESCALER_4
  • LL_IWDG_PRESCALER_8
  • LL_IWDG_PRESCALER_16
  • LL_IWDG_PRESCALER_32
  • LL_IWDG_PRESCALER_64
  • LL_IWDG_PRESCALER_128
  • LL_IWDG_PRESCALER_256
Return values:
None

Definition at line 194 of file stm32wbxx_ll_iwdg.h.

__STATIC_INLINE void LL_IWDG_SetReloadCounter | ( | IWDG_TypeDef * | IWDGx,
 |  | uint32_t | Counter
 | ) |  |

Specify the IWDG down-counter reload value.

Reference Manual to LL API cross reference:
RLR RL LL_IWDG_SetReloadCounter
Parameters:
IWDGx | IWDG Instance
Counter | Value between Min_Data=0 and Max_Data=0x0FFF
Return values:
None

Definition at line 224 of file stm32wbxx_ll_iwdg.h.

__STATIC_INLINE void LL_IWDG_SetWindow | ( | IWDG_TypeDef * | IWDGx,
 |  | uint32_t | Window
 | ) |  |

Specify high limit of the window value to be compared to the down-counter.

Reference Manual to LL API cross reference:
WINR WIN LL_IWDG_SetWindow
Parameters:
IWDGx | IWDG Instance
Window | Value between Min_Data=0 and Max_Data=0x0FFF
Return values:
None

Definition at line 247 of file stm32wbxx_ll_iwdg.h.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FLAG_Management

Functions
FLAG_Management
IWDG Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_PVU (IWDG_TypeDef *IWDGx)
Check if flag Prescaler Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_RVU (IWDG_TypeDef *IWDGx)
Check if flag Reload Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_WVU (IWDG_TypeDef *IWDGx)
Check if flag Window Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsReady (IWDG_TypeDef *IWDGx)
Check if all flags Prescaler, Reload & Window Value Update are reset or not.

Function Documentation

__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU ( IWDG_TypeDef * IWDGx )

Check if flag Prescaler Value Update is set or not.

Reference Manual to LL API cross reference:
SR PVU LL_IWDG_IsActiveFlag_PVU
Parameters:
IWDGx IWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 277 of file stm32wbxx_ll_iwdg.h.

__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU ( IWDG_TypeDef * IWDGx )

Check if flag Reload Value Update is set or not.

Reference Manual to LL API cross reference:
SR RVU LL_IWDG_IsActiveFlag_RVU
Parameters:
IWDGx IWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 288 of file stm32wbxx_ll_iwdg.h.

__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU ( IWDG_TypeDef * IWDGx )

Check if flag Window Value Update is set or not.

Reference Manual to LL API cross reference:
SR WVU LL_IWDG_IsActiveFlag_WVU
Parameters:
IWDGx IWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 299 of file stm32wbxx_ll_iwdg.h.

__STATIC_INLINE uint32_t LL_IWDG_IsReady ( IWDG_TypeDef * IWDGx )

Check if all flags Prescaler, Reload & Window Value Update are reset or not.

Reference Manual to LL API cross reference:
SR PVU LL_IWDG_IsReady
SR WVU LL_IWDG_IsReady
SR RVU LL_IWDG_IsReady
Parameters:
IWDGx IWDG Instance
Return values:
State of bits (1 or 0).

Definition at line 312 of file stm32wbxx_ll_iwdg.h.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPTIM

Modules | Functions
LPTIM
STM32WBxx_LL_Driver

Modules

LPTIM Private Functions
LPTIM Private Macros
LPTIM Exported Init structure
LPTIM Exported Constants
LPTIM Exported Macros
LPTIM Exported Functions

Functions

void LL_LPTIM_Disable (LPTIM_TypeDef *LPTIMx)
Disable the LPTIM instance.

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for LPTIM registers.

Register | Bit | Function
ARR | ARR | LL_LPTIM_GetAutoReload
 |  | LL_LPTIM_SetAutoReload
CFGR | CKFLT | LL_LPTIM_ConfigClock
 |  | LL_LPTIM_GetClockFilter
 | CKPOL | LL_LPTIM_ConfigClock
 |  | LL_LPTIM_GetClockPolarity
 |  | LL_LPTIM_GetEncoderMode
 |  | LL_LPTIM_SetEncoderMode
 | CKSEL | LL_LPTIM_GetClockSource
 |  | LL_LPTIM_SetClockSource
 | COUNTMODE | LL_LPTIM_GetCounterMode
 |  | LL_LPTIM_SetCounterMode
 | ENC | LL_LPTIM_DisableEncoderMode
 |  | LL_LPTIM_EnableEncoderMode
 |  | LL_LPTIM_IsEnabledEncoderMode
 | PRELOAD | LL_LPTIM_GetUpdateMode
 |  | LL_LPTIM_SetUpdateMode
 | PRESC | LL_LPTIM_GetPrescaler
 |  | LL_LPTIM_SetPrescaler
 | TIMOUT | LL_LPTIM_DisableTimeout
 |  | LL_LPTIM_EnableTimeout
 |  | LL_LPTIM_IsEnabledTimeout
 | TRGFLT | LL_LPTIM_ConfigTrigger
 |  | LL_LPTIM_GetTriggerFilter
 | TRIGEN | LL_LPTIM_ConfigTrigger
 |  | LL_LPTIM_GetTriggerPolarity
 |  | LL_LPTIM_TrigSw
 | TRIGSEL | LL_LPTIM_ConfigTrigger
 |  | LL_LPTIM_GetTriggerSource
 | WAVE | LL_LPTIM_ConfigOutput
 |  | LL_LPTIM_GetWaveform
 |  | LL_LPTIM_SetWaveform
 | WAVPOL | LL_LPTIM_ConfigOutput
 |  | LL_LPTIM_GetPolarity
 |  | LL_LPTIM_SetPolarity
CMP | CMP | LL_LPTIM_GetCompare
 |  | LL_LPTIM_SetCompare
CNT | CNT | LL_LPTIM_GetCounter
CR | CNTSTRT | LL_LPTIM_StartCounter
 | COUNTRST | LL_LPTIM_ResetCounter
 | ENABLE | LL_LPTIM_Disable
 |  | LL_LPTIM_Enable
 |  | LL_LPTIM_IsEnabled
 | RSTARE | LL_LPTIM_DisableResetAfterRead
 |  | LL_LPTIM_EnableResetAfterRead
 |  | LL_LPTIM_IsEnabledResetAfterRead
 | SNGSTRT | LL_LPTIM_StartCounter
ICR | ARRMCF | LL_LPTIM_ClearFLAG_ARRM
 | ARROKCF | LL_LPTIM_ClearFlag_ARROK
 | CMPMCF | LL_LPTIM_ClearFLAG_CMPM
 | CMPOKCF | LL_LPTIM_ClearFlag_CMPOK
 | DOWNCF | LL_LPTIM_ClearFlag_DOWN
 | EXTTRIGCF | LL_LPTIM_ClearFlag_EXTTRIG
 | UPCF | LL_LPTIM_ClearFlag_UP
IER | ARRMIE | LL_LPTIM_DisableIT_ARRM
 |  | LL_LPTIM_EnableIT_ARRM
 |  | LL_LPTIM_IsEnabledIT_ARRM
 | ARROKIE | LL_LPTIM_DisableIT_ARROK
 |  | LL_LPTIM_EnableIT_ARROK
 |  | LL_LPTIM_IsEnabledIT_ARROK
 | CMPMIE | LL_LPTIM_DisableIT_CMPM
 |  | LL_LPTIM_EnableIT_CMPM
 |  | LL_LPTIM_IsEnabledIT_CMPM
 | CMPOKIE | LL_LPTIM_DisableIT_CMPOK
 |  | LL_LPTIM_EnableIT_CMPOK
 |  | LL_LPTIM_IsEnabledIT_CMPOK
 | DOWNIE | LL_LPTIM_DisableIT_DOWN
 |  | LL_LPTIM_EnableIT_DOWN
 |  | LL_LPTIM_IsEnabledIT_DOWN
 | EXTTRIGIE | LL_LPTIM_DisableIT_EXTTRIG
 |  | LL_LPTIM_EnableIT_EXTTRIG
 |  | LL_LPTIM_IsEnabledIT_EXTTRIG
 | UPIE | LL_LPTIM_DisableIT_UP
 |  | LL_LPTIM_EnableIT_UP
 |  | LL_LPTIM_IsEnabledIT_UP
ISR | ARRM | LL_LPTIM_IsActiveFlag_ARRM
 | ARROK | LL_LPTIM_IsActiveFlag_ARROK
 | CMPM | LL_LPTIM_IsActiveFlag_CMPM
 | CMPOK | LL_LPTIM_IsActiveFlag_CMPOK
 | DOWN | LL_LPTIM_IsActiveFlag_DOWN
 | EXTTRIG | LL_LPTIM_IsActiveFlag_EXTTRIG
 | UP | LL_LPTIM_IsActiveFlag_UP
OR | OR_0 | LL_LPTIM_SetInput1Src
 |  | LL_LPTIM_SetInput2Src
 | OR_1 | LL_LPTIM_SetInput1Src

Function Documentation

void LL_LPTIM_Disable ( LPTIM_TypeDef * LPTIMx )

Disable the LPTIM instance.

Reference Manual to LL API cross reference:
CR ENABLE LL_LPTIM_Disable
Parameters:
LPTIMx Low-Power Timer instance
Note:
The following sequence is required to solve LPTIM disable HW limitation. Please check Errata Sheet ES0335 for more details under "MCU may remain stuck in LPTIM interrupt when entering Stop mode" section.
Return values:
None

Definition at line 199 of file stm32wbxx_ll_lptim.c.

References assert_param, LL_LPTIM_ClearFlag_ARROK(), LL_LPTIM_ClearFlag_CMPOK(), LL_LPTIM_DeInit(), LL_LPTIM_IsActiveFlag_ARROK(), LL_LPTIM_IsActiveFlag_CMPOK(), LL_RCC_GetLPTIMClockSource(), LL_RCC_GetSystemClocksFreq(), LL_RCC_LPTIM1_CLKSOURCE, LL_RCC_LPTIM1_CLKSOURCE_PCLK1, LL_RCC_LPTIM2_CLKSOURCE, LL_RCC_LPTIM2_CLKSOURCE_PCLK1, LL_RCC_SetLPTIMClockSource(), and LL_RCC_ClocksTypeDef::SYSCLK_Frequency.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPTIM Private Functions

Functions
LPTIM Private Functions
LPTIM | LPTIM

Functions

void | LPTIM_Disable (LPTIM_HandleTypeDef *hlptim)
Disable LPTIM HW instance.
static void | LPTIM_ResetCallback (LPTIM_HandleTypeDef *lptim)
Reset interrupt callbacks to the legacy weak callbacks.
static HAL_StatusTypeDef | LPTIM_WaitForFlag (LPTIM_HandleTypeDef *hlptim, uint32_t flag)
LPTimer Wait for flag set.

Function Documentation

void LPTIM_Disable ( LPTIM_HandleTypeDef * hlptim )

Disable LPTIM HW instance.

Parameters:
hlptim pointer to a LPTIM_HandleTypeDef structure that contains the configuration information for LPTIM module.
Note:
The following sequence is required to solve LPTIM disable HW limitation. Please check Errata Sheet ES0335 for more details under "MCU may remain stuck in LPTIM interrupt when entering Stop mode" section.
Return values:
None

Definition at line 2322 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_CLEAR_FLAG, __HAL_RCC_GET_LPTIM1_SOURCE, __HAL_RCC_GET_LPTIM2_SOURCE, __HAL_RCC_LPTIM1_CONFIG, __HAL_RCC_LPTIM1_FORCE_RESET, __HAL_RCC_LPTIM1_RELEASE_RESET, __HAL_RCC_LPTIM2_CONFIG, __HAL_RCC_LPTIM2_FORCE_RESET, __HAL_RCC_LPTIM2_RELEASE_RESET, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_WaitForFlag(), RCC_LPTIM1CLKSOURCE_PCLK1, RCC_LPTIM2CLKSOURCE_PCLK1, and __LPTIM_HandleTypeDef::State.

static void LPTIM_ResetCallback ( LPTIM_HandleTypeDef * lptim ) [static]

Reset interrupt callbacks to the legacy weak callbacks.

Parameters:
lptim pointer to a LPTIM_HandleTypeDef structure that contains the configuration information for LPTIM module.
Return values:
None

Definition at line 2276 of file stm32wbxx_hal_lptim.c.

References __LPTIM_HandleTypeDef::AutoReloadMatchCallback, __LPTIM_HandleTypeDef::AutoReloadWriteCallback, __LPTIM_HandleTypeDef::CompareMatchCallback, __LPTIM_HandleTypeDef::CompareWriteCallback, __LPTIM_HandleTypeDef::DirectionDownCallback, __LPTIM_HandleTypeDef::DirectionUpCallback, HAL_LPTIM_AutoReloadMatchCallback(), HAL_LPTIM_AutoReloadWriteCallback(), HAL_LPTIM_CompareMatchCallback(), HAL_LPTIM_CompareWriteCallback(), HAL_LPTIM_DirectionDownCallback(), HAL_LPTIM_DirectionUpCallback(), HAL_LPTIM_TriggerCallback(), and __LPTIM_HandleTypeDef::TriggerCallback.

Referenced by HAL_LPTIM_Init().

static HAL_StatusTypeDef LPTIM_WaitForFlag | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | flag
 | ) |  | [static]

LPTimer Wait for flag set.

Parameters:
hlptim | pointer to a LPTIM_HandleTypeDef structure that contains the configuration information for LPTIM module.
flag | The lptim flag
Return values:
HAL status

Definition at line 2296 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_GET_FLAG, and TIMEOUT.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), and LPTIM_Disable().

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPTIM Private Macros

Defines
LPTIM Private Macros
LPTIM

Defines

#define | IS_LL_LPTIM_CLOCK_SOURCE(__VALUE__)
#define | IS_LL_LPTIM_CLOCK_PRESCALER(__VALUE__)
#define | IS_LL_LPTIM_WAVEFORM(__VALUE__)
#define | IS_LL_LPTIM_OUTPUT_POLARITY(__VALUE__)

Define Documentation

#define IS_LL_LPTIM_CLOCK_PRESCALER ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPTIM_PRESCALER_DIV1)   \
                                             || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2)   \
                                             || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4)   \
                                             || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8)   \
                                             || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16)  \
                                             || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32)  \
                                             || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64)  \
                                             || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128))

Definition at line 53 of file stm32wbxx_ll_lptim.c.

Referenced by LL_LPTIM_Init().

#define IS_LL_LPTIM_CLOCK_SOURCE ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \
                                          || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL))

Definition at line 50 of file stm32wbxx_ll_lptim.c.

Referenced by LL_LPTIM_Init().

#define IS_LL_LPTIM_OUTPUT_POLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \
                                             || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE))

Definition at line 65 of file stm32wbxx_ll_lptim.c.

Referenced by LL_LPTIM_Init().

#define IS_LL_LPTIM_WAVEFORM ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \
                                      || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE))

Definition at line 62 of file stm32wbxx_ll_lptim.c.

Referenced by LL_LPTIM_Init().

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LL_LPTIM_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_LPTIM_InitTypeDef Struct Reference
LPTIM Exported Init structure

LPTIM Init structure definition. More...

#include <stm32wbxx_ll_lptim.h>

Data Fields

uint32_t | ClockSource
uint32_t | Prescaler
uint32_t | Waveform
uint32_t | Polarity

Detailed Description

LPTIM Init structure definition.

Definition at line 65 of file stm32wbxx_ll_lptim.h.

Field Documentation

uint32_t LL_LPTIM_InitTypeDef::ClockSource

Specifies the source of the clock used by the LPTIM instance. This parameter can be a value of Clock Source.

This feature can be modified afterwards using unitary function LL_LPTIM_SetClockSource().

Definition at line 67 of file stm32wbxx_ll_lptim.h.

Referenced by LL_LPTIM_Init(), and LL_LPTIM_StructInit().

uint32_t LL_LPTIM_InitTypeDef::Polarity

Specifies waveform polarity. This parameter can be a value of Output Polarity.

This feature can be modified afterwards using unitary function LL_LPTIM_ConfigOutput().

Definition at line 82 of file stm32wbxx_ll_lptim.h.

Referenced by LL_LPTIM_Init(), and LL_LPTIM_StructInit().

uint32_t LL_LPTIM_InitTypeDef::Prescaler

Specifies the prescaler division ratio. This parameter can be a value of Prescaler Value.

This feature can be modified afterwards using using unitary function LL_LPTIM_SetPrescaler().

Definition at line 72 of file stm32wbxx_ll_lptim.h.

Referenced by LL_LPTIM_Init(), and LL_LPTIM_StructInit().

uint32_t LL_LPTIM_InitTypeDef::Waveform

Specifies the waveform shape. This parameter can be a value of Output Waveform Type.

This feature can be modified afterwards using unitary function LL_LPTIM_ConfigOutput().

Definition at line 77 of file stm32wbxx_ll_lptim.h.

Referenced by LL_LPTIM_Init(), and LL_LPTIM_StructInit().

The documentation for this struct was generated from the following file:
  • stm32wbxx_ll_lptim.h
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STM32WB55xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
LPTIM Exported Constants

Flags defines which can be used with LL_LPTIM_ReadReg function. More...

Defines

#define | LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM
#define | LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM
#define | LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG
#define | LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK
#define | LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK
#define | LL_LPTIM_ISR_UP LPTIM_ISR_UP
#define | LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN

Detailed Description

Flags defines which can be used with LL_LPTIM_ReadReg function.

Define Documentation

#define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM

Autoreload match

Definition at line 103 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK

Autoreload register update OK

Definition at line 106 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM

Compare match

Definition at line 102 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK

Compare register update OK

Definition at line 105 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN

Counter direction change up to down

Definition at line 108 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG

External trigger edge event

Definition at line 104 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_ISR_UP LPTIM_ISR_UP

Counter direction change down to up

Definition at line 107 of file stm32wbxx_ll_lptim.h.

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STM32WB55xx HAL User Manual: IT Defines

Defines
IT Defines
LPTIM Exported Constants

IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions. More...

Defines

#define | LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE
#define | LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE
#define | LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE
#define | LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE
#define | LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE
#define | LL_LPTIM_IER_UPIE LPTIM_IER_UPIE
#define | LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE

Detailed Description

IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions.

Define Documentation

#define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE

Autoreload match Interrupt Enable

Definition at line 118 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE

Autoreload register update OK Interrupt Enable

Definition at line 121 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE

Compare match Interrupt Enable

Definition at line 117 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE

Compare register update OK Interrupt Enable

Definition at line 120 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE

Direction change to down Interrupt Enable

Definition at line 123 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE

External trigger valid edge Interrupt Enable

Definition at line 119 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE

Direction change to UP Interrupt Enable

Definition at line 122 of file stm32wbxx_ll_lptim.h.

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STM32WB55xx HAL User Manual: Operating Mode

Defines
Operating Mode
LPTIM Exported Constants

Defines

#define | LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT
#define | LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT

Define Documentation

#define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT

LP Timer starts in continuous mode

Definition at line 131 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT

LP Tilmer starts in single mode

Definition at line 132 of file stm32wbxx_ll_lptim.h.

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STM32WB55xx HAL User Manual: Update Mode

Defines
Update Mode
LPTIM Exported Constants

Defines

#define | LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U
#define | LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD

Define Documentation

#define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD

preload is enabled: registers are updated at the end of the current LPTIM period

Definition at line 141 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U

Preload is disabled: registers are updated after each APB bus write access

Definition at line 140 of file stm32wbxx_ll_lptim.h.

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STM32WB55xx HAL User Manual: Counter Mode

Defines
Counter Mode
LPTIM Exported Constants

Defines

#define | LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U
#define | LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE

Define Documentation

#define LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE

The counter is incremented following each valid clock pulse on the LPTIM external Input1

Definition at line 150 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U

The counter is incremented following each internal clock pulse

Definition at line 149 of file stm32wbxx_ll_lptim.h.

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STM32WB55xx HAL User Manual: Output Waveform Type

Defines
Output Waveform Type
LPTIM Exported Constants

Defines

#define | LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U
#define | LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE

Define Documentation

#define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U

LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINOUS or SINGLE

Definition at line 158 of file stm32wbxx_ll_lptim.h.

Referenced by LL_LPTIM_StructInit().

#define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE

LPTIM generates a Set Once waveform

Definition at line 159 of file stm32wbxx_ll_lptim.h.

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STM32WB55xx HAL User Manual: Output Polarity

Defines
Output Polarity
LPTIM Exported Constants

Defines

#define | LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U
#define | LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CFGR_WAVPOL

Define Documentation

#define LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CFGR_WAVPOL

The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers

Definition at line 168 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U

The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers

Definition at line 167 of file stm32wbxx_ll_lptim.h.

Referenced by LL_LPTIM_StructInit().

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STM32WB55xx HAL User Manual: Prescaler Value

Defines
Prescaler Value
LPTIM Exported Constants

Defines

#define | LL_LPTIM_PRESCALER_DIV1 0x00000000U
#define | LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
#define | LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
#define | LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0)
#define | LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
#define | LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0)
#define | LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1)
#define | LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC

Define Documentation

#define LL_LPTIM_PRESCALER_DIV1 0x00000000U

Prescaler division factor is set to 1

Definition at line 176 of file stm32wbxx_ll_lptim.h.

Referenced by LL_LPTIM_StructInit().

#define LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC

Prescaler division factor is set to 128

Definition at line 183 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2

Prescaler division factor is set to 16

Definition at line 180 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0

Prescaler division factor is set to 2

Definition at line 177 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0)

Prescaler division factor is set to 32

Definition at line 181 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1

Prescaler division factor is set to 4

Definition at line 178 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1)

Prescaler division factor is set to 64

Definition at line 182 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0)

Prescaler division factor is set to 8

Definition at line 179 of file stm32wbxx_ll_lptim.h.

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STM32WB55xx HAL User Manual: Trigger Source

Defines
Trigger Source
LPTIM Exported Constants

Defines

#define | LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U
#define | LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0
#define | LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1
#define | LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0)
#define | LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2
#define | LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0)
#define | LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1)
#define | LL_LPTIM_TRIG_SOURCE_COMP2 LPTIM_CFGR_TRIGSEL

Define Documentation

#define LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1)

External input trigger is connected to COMP1 output

Definition at line 202 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_COMP2 LPTIM_CFGR_TRIGSEL

External input trigger is connected to COMP2 output

Definition at line 205 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U

External input trigger is connected to TIMx_ETR input

Definition at line 191 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0

External input trigger is connected to RTC Alarm A

Definition at line 192 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1

External input trigger is connected to RTC Alarm B

Definition at line 193 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0)

External input trigger is connected to RTC Tamper 1

Definition at line 195 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2

External input trigger is connected to RTC Tamper 2

Definition at line 197 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0)

External input trigger is connected to RTC Tamper 3

Definition at line 199 of file stm32wbxx_ll_lptim.h.

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STM32WB55xx HAL User Manual: Trigger Filter

Defines
Trigger Filter
LPTIM Exported Constants

Defines

#define | LL_LPTIM_TRIG_FILTER_NONE 0x00000000U
#define | LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0
#define | LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1
#define | LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT

Define Documentation

#define LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0

Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger

Definition at line 215 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1

Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger

Definition at line 216 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT

Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger

Definition at line 217 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_TRIG_FILTER_NONE 0x00000000U

Any trigger active level change is considered as a valid trigger

Definition at line 214 of file stm32wbxx_ll_lptim.h.

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STM32WB55xx HAL User Manual: Trigger Polarity

Defines
Trigger Polarity
LPTIM Exported Constants

Defines

#define | LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0
#define | LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1
#define | LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN

Define Documentation

#define LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1

LPTIM counter starts when a falling edge is detected

Definition at line 226 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0

LPTIM counter starts when a rising edge is detected

Definition at line 225 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN

LPTIM counter starts when a rising or a falling edge is detected

Definition at line 227 of file stm32wbxx_ll_lptim.h.

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STM32WB55xx HAL User Manual: Clock Source

Defines
Clock Source
LPTIM Exported Constants

Defines

#define | LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U
#define | LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL

Define Documentation

#define LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL

LPTIM is clocked by an external clock source through the LPTIM external Input1

Definition at line 236 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U

LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)

Definition at line 235 of file stm32wbxx_ll_lptim.h.

Referenced by LL_LPTIM_StructInit().

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STM32WB55xx HAL User Manual: Clock Filter

Defines
Clock Filter
LPTIM Exported Constants

Defines

#define | LL_LPTIM_CLK_FILTER_NONE 0x00000000U
#define | LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0
#define | LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1
#define | LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT

Define Documentation

#define LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0

External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition

Definition at line 245 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1

External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition

Definition at line 246 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT

External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition

Definition at line 247 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_CLK_FILTER_NONE 0x00000000U

Any external clock signal level change is considered as a valid transition

Definition at line 244 of file stm32wbxx_ll_lptim.h.

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STM32WB55xx HAL User Manual: Clock Polarity

Defines
Clock Polarity
LPTIM Exported Constants

Defines

#define | LL_LPTIM_CLK_POLARITY_RISING 0x00000000U
#define | LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0
#define | LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1

Define Documentation

#define LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0

The falling edge is the active edge used for counting

Definition at line 256 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_CLK_POLARITY_RISING 0x00000000U

The rising edge is the active edge used for counting

Definition at line 255 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1

Both edges are active edges

Definition at line 257 of file stm32wbxx_ll_lptim.h.

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STM32WB55xx HAL User Manual: Encoder Mode

Defines
Encoder Mode
LPTIM Exported Constants

Defines

#define | LL_LPTIM_ENCODER_MODE_RISING 0x00000000U
#define | LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0
#define | LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1

Define Documentation

#define LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0

The falling edge is the active edge used for counting

Definition at line 266 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_ENCODER_MODE_RISING 0x00000000U

The rising edge is the active edge used for counting

Definition at line 265 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1

Both edges are active edges

Definition at line 267 of file stm32wbxx_ll_lptim.h.

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STM32WB55xx HAL User Manual: Input1 Source

Defines
Input1 Source
LPTIM Exported Constants

Defines

#define | LL_LPTIM_INPUT1_SRC_GPIO 0x00000000U
#define | LL_LPTIM_INPUT1_SRC_COMP1 LPTIM_OR_OR_0
#define | LL_LPTIM_INPUT1_SRC_COMP2 LPTIM_OR_OR_1
#define | LL_LPTIM_INPUT1_SRC_COMP1_COMP2 LPTIM_OR_OR

Define Documentation

#define LL_LPTIM_INPUT1_SRC_COMP1 LPTIM_OR_OR_0

For LPTIM1 and LPTIM2

Definition at line 276 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_INPUT1_SRC_COMP1_COMP2 LPTIM_OR_OR

For LPTIM2

Definition at line 278 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_INPUT1_SRC_COMP2 LPTIM_OR_OR_1

For LPTIM2

Definition at line 277 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_INPUT1_SRC_GPIO 0x00000000U

For LPTIM1 and LPTIM2

Definition at line 275 of file stm32wbxx_ll_lptim.h.

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STM32WB55xx HAL User Manual: Input2 Source

Defines
Input2 Source
LPTIM Exported Constants

Defines

#define | LL_LPTIM_INPUT2_SRC_GPIO 0x00000000U
#define | LL_LPTIM_INPUT2_SRC_COMP2 LPTIM_OR_OR_1

Define Documentation

#define LL_LPTIM_INPUT2_SRC_COMP2 LPTIM_OR_OR_1

For LPTIM1

Definition at line 287 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_INPUT2_SRC_GPIO 0x00000000U

For LPTIM1

Definition at line 286 of file stm32wbxx_ll_lptim.h.

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STM32WB55xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
LPTIM Exported Macros

Defines

#define | LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
Write a value in LPTIM register.
#define | LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
Read a value in LPTIM register.

Define Documentation

#define LL_LPTIM_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG((__INSTANCE__)->__REG__)

Read a value in LPTIM register.

Parameters:
__INSTANCE__ | LPTIM Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 320 of file stm32wbxx_ll_lptim.h.

#define LL_LPTIM_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))

Write a value in LPTIM register.

Parameters:
__INSTANCE__ | LPTIM Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 312 of file stm32wbxx_ll_lptim.h.

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STM32WB55xx HAL User Manual: Initialisation and deinitialisation functions

Functions
Initialisation and deinitialisation functions
LPTIM Exported Functions

Functions

ErrorStatus | LL_LPTIM_DeInit (LPTIM_TypeDef *LPTIMx)
Set LPTIMx registers to their reset values.
void | LL_LPTIM_StructInit (LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
Set each fields of the LPTIM_InitStruct structure to its default value.
ErrorStatus | LL_LPTIM_Init (LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
Configure the LPTIMx peripheral according to the specified parameters.
void | LL_LPTIM_Disable (LPTIM_TypeDef *LPTIMx)
Disable the LPTIM instance.

Function Documentation

ErrorStatus LL_LPTIM_DeInit ( LPTIM_TypeDef * LPTIMx )

Set LPTIMx registers to their reset values.

Parameters:
LPTIMx LP Timer instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: LPTIMx registers are de-initialized
  • ERROR: invalid LPTIMx instance

Definition at line 96 of file stm32wbxx_ll_lptim.c.

References assert_param, LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_LPTIM1, LL_APB1_GRP1_ReleaseReset(), LL_APB1_GRP2_ForceReset(), LL_APB1_GRP2_PERIPH_LPTIM2, and LL_APB1_GRP2_ReleaseReset().

Referenced by LL_LPTIM_Disable().

void LL_LPTIM_Disable ( LPTIM_TypeDef * LPTIMx )

Disable the LPTIM instance.

Reference Manual to LL API cross reference:
CR ENABLE LL_LPTIM_Disable
Parameters:
LPTIMx Low-Power Timer instance
Note:
The following sequence is required to solve LPTIM disable HW limitation. Please check Errata Sheet ES0335 for more details under "MCU may remain stuck in LPTIM interrupt when entering Stop mode" section.
Return values:
None

Definition at line 199 of file stm32wbxx_ll_lptim.c.

References assert_param, LL_LPTIM_ClearFlag_ARROK(), LL_LPTIM_ClearFlag_CMPOK(), LL_LPTIM_DeInit(), LL_LPTIM_IsActiveFlag_ARROK(), LL_LPTIM_IsActiveFlag_CMPOK(), LL_RCC_GetLPTIMClockSource(), LL_RCC_GetSystemClocksFreq(), LL_RCC_LPTIM1_CLKSOURCE, LL_RCC_LPTIM1_CLKSOURCE_PCLK1, LL_RCC_LPTIM2_CLKSOURCE, LL_RCC_LPTIM2_CLKSOURCE_PCLK1, LL_RCC_SetLPTIMClockSource(), and LL_RCC_ClocksTypeDef::SYSCLK_Frequency.

ErrorStatus LL_LPTIM_Init | ( | LPTIM_TypeDef * | LPTIMx,
 |  | LL_LPTIM_InitTypeDef * | LPTIM_InitStruct
 | ) |  |

Configure the LPTIMx peripheral according to the specified parameters.

Note:
LL_LPTIM_Init can only be called when the LPTIM instance is disabled.
LPTIMx can be disabled using unitary function LL_LPTIM_Disable().
Parameters:
LPTIMx | LP Timer Instance
LPTIM_InitStruct | pointer to a LL_LPTIM_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: LPTIMx instance has been initialized
  • ERROR: LPTIMx instance hasn't been initialized

Definition at line 148 of file stm32wbxx_ll_lptim.c.

References assert_param, LL_LPTIM_InitTypeDef::ClockSource, IS_LL_LPTIM_CLOCK_PRESCALER, IS_LL_LPTIM_CLOCK_SOURCE, IS_LL_LPTIM_OUTPUT_POLARITY, IS_LL_LPTIM_WAVEFORM, LL_LPTIM_IsEnabled(), LL_LPTIM_InitTypeDef::Polarity, LL_LPTIM_InitTypeDef::Prescaler, and LL_LPTIM_InitTypeDef::Waveform.

void LL_LPTIM_StructInit ( LL_LPTIM_InitTypeDef * LPTIM_InitStruct )

Set each fields of the LPTIM_InitStruct structure to its default value.

Parameters:
LPTIM_InitStruct pointer to a LL_LPTIM_InitTypeDef structure
Return values:
None

Definition at line 129 of file stm32wbxx_ll_lptim.c.

References LL_LPTIM_InitTypeDef::ClockSource, LL_LPTIM_CLK_SOURCE_INTERNAL, LL_LPTIM_OUTPUT_POLARITY_REGULAR, LL_LPTIM_OUTPUT_WAVEFORM_PWM, LL_LPTIM_PRESCALER_DIV1, LL_LPTIM_InitTypeDef::Polarity, LL_LPTIM_InitTypeDef::Prescaler, and LL_LPTIM_InitTypeDef::Waveform.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPTIM Configuration

Functions
LPTIM Configuration
LPTIM Exported Functions

Functions

__STATIC_INLINE void | LL_LPTIM_Enable (LPTIM_TypeDef *LPTIMx)
Enable the LPTIM instance.
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabled (LPTIM_TypeDef *LPTIMx)
Indicates whether the LPTIM instance is enabled.
__STATIC_INLINE void | LL_LPTIM_StartCounter (LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
Starts the LPTIM counter in the desired mode.
__STATIC_INLINE void | LL_LPTIM_EnableResetAfterRead (LPTIM_TypeDef *LPTIMx)
Enable reset after read.
__STATIC_INLINE void | LL_LPTIM_DisableResetAfterRead (LPTIM_TypeDef *LPTIMx)
Disable reset after read.
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledResetAfterRead (LPTIM_TypeDef *LPTIMx)
Indicate whether the reset after read feature is enabled.
__STATIC_INLINE void | LL_LPTIM_ResetCounter (LPTIM_TypeDef *LPTIMx)
Reset of the LPTIM_CNT counter register (synchronous).
__STATIC_INLINE void | LL_LPTIM_SetUpdateMode (LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
Set the LPTIM registers update mode (enable/disable register preload)
__STATIC_INLINE uint32_t | LL_LPTIM_GetUpdateMode (LPTIM_TypeDef *LPTIMx)
Get the LPTIM registers update mode.
__STATIC_INLINE void | LL_LPTIM_SetAutoReload (LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
Set the auto reload value.
__STATIC_INLINE uint32_t | LL_LPTIM_GetAutoReload (LPTIM_TypeDef *LPTIMx)
Get actual auto reload value.
__STATIC_INLINE void | LL_LPTIM_SetCompare (LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
Set the compare value.
__STATIC_INLINE uint32_t | LL_LPTIM_GetCompare (LPTIM_TypeDef *LPTIMx)
Get actual compare value.
__STATIC_INLINE uint32_t | LL_LPTIM_GetCounter (LPTIM_TypeDef *LPTIMx)
Get actual counter value.
__STATIC_INLINE void | LL_LPTIM_SetCounterMode (LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
Set the counter mode (selection of the LPTIM counter clock source).
__STATIC_INLINE uint32_t | LL_LPTIM_GetCounterMode (LPTIM_TypeDef *LPTIMx)
Get the counter mode.
__STATIC_INLINE void | LL_LPTIM_ConfigOutput (LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity)
Configure the LPTIM instance output (LPTIMx_OUT)
__STATIC_INLINE void | LL_LPTIM_SetWaveform (LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
Set waveform shape.
__STATIC_INLINE uint32_t | LL_LPTIM_GetWaveform (LPTIM_TypeDef *LPTIMx)
Get actual waveform shape.
__STATIC_INLINE void | LL_LPTIM_SetPolarity (LPTIM_TypeDef *LPTIMx, uint32_t Polarity)
Set output polarity.
__STATIC_INLINE uint32_t | LL_LPTIM_GetPolarity (LPTIM_TypeDef *LPTIMx)
Get actual output polarity.
__STATIC_INLINE void | LL_LPTIM_SetPrescaler (LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
Set actual prescaler division ratio.
__STATIC_INLINE uint32_t | LL_LPTIM_GetPrescaler (LPTIM_TypeDef *LPTIMx)
Get actual prescaler division ratio.
__STATIC_INLINE void | LL_LPTIM_SetInput1Src (LPTIM_TypeDef *LPTIMx, uint32_t Src)
Set LPTIM input 1 source (default GPIO).
__STATIC_INLINE void | LL_LPTIM_SetInput2Src (LPTIM_TypeDef *LPTIMx, uint32_t Src)
Set LPTIM input 2 source (default GPIO).

Function Documentation

__STATIC_INLINE void LL_LPTIM_ConfigOutput | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | Waveform,
 |  | uint32_t | Polarity
 | ) |  |

Configure the LPTIM instance output (LPTIMx_OUT)

Note:
This function must be called when the LPTIM instance is disabled.
Regarding the LPTIM output polarity the change takes effect immediately, so the output default value will change immediately after the polarity is re-configured, even before the timer is enabled.
Reference Manual to LL API cross reference:
CFGR WAVE LL_LPTIM_ConfigOutput
CFGR WAVPOL LL_LPTIM_ConfigOutput
Parameters:
LPTIMx Low-Power Timer instance
Waveform This parameter can be one of the following values:
  • LL_LPTIM_OUTPUT_WAVEFORM_PWM
  • LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
Polarity This parameter can be one of the following values:
  • LL_LPTIM_OUTPUT_POLARITY_REGULAR
  • LL_LPTIM_OUTPUT_POLARITY_INVERSE
Return values:
None

Definition at line 588 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_DisableResetAfterRead ( LPTIM_TypeDef * LPTIMx )

Disable reset after read.

Reference Manual to LL API cross reference:
CR RSTARE LL_LPTIM_DisableResetAfterRead
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 413 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_Enable ( LPTIM_TypeDef * LPTIMx )

Enable the LPTIM instance.

Note:
After setting the ENABLE bit, a delay of two counter clock is needed before the LPTIM instance is actually enabled.
Reference Manual to LL API cross reference:
CR ENABLE LL_LPTIM_Enable
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 360 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableResetAfterRead ( LPTIM_TypeDef * LPTIMx )

Enable reset after read.

Note:
After calling this function any read access to LPTIM_CNT register will asynchronously reset the LPTIM_CNT register content.
Reference Manual to LL API cross reference:
CR RSTARE LL_LPTIM_EnableResetAfterRead
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 402 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload ( LPTIM_TypeDef * LPTIMx )

Get actual auto reload value.

Reference Manual to LL API cross reference:
ARR ARR LL_LPTIM_GetAutoReload
Parameters:
LPTIMx Low-Power Timer instance
Return values:
AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF

Definition at line 496 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetCompare ( LPTIM_TypeDef * LPTIMx )

Get actual compare value.

Reference Manual to LL API cross reference:
CMP CMP LL_LPTIM_GetCompare
Parameters:
LPTIMx Low-Power Timer instance
Return values:
CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF

Definition at line 523 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetCounter ( LPTIM_TypeDef * LPTIMx )

Get actual counter value.

Note:
When the LPTIM instance is running with an asynchronous clock, reading the LPTIMx_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical.
Reference Manual to LL API cross reference:
CNT CNT LL_LPTIM_GetCounter
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Counter value

Definition at line 538 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode ( LPTIM_TypeDef * LPTIMx )

Get the counter mode.

Reference Manual to LL API cross reference:
CFGR COUNTMODE LL_LPTIM_GetCounterMode
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_COUNTER_MODE_INTERNAL
  • LL_LPTIM_COUNTER_MODE_EXTERNAL

Definition at line 566 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetPolarity ( LPTIM_TypeDef * LPTIMx )

Get actual output polarity.

Reference Manual to LL API cross reference:
CFGR WAVPOL LL_LPTIM_GetPolarity
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_OUTPUT_POLARITY_REGULAR
  • LL_LPTIM_OUTPUT_POLARITY_INVERSE

Definition at line 642 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler ( LPTIM_TypeDef * LPTIMx )

Get actual prescaler division ratio.

Reference Manual to LL API cross reference:
CFGR PRESC LL_LPTIM_GetPrescaler
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_PRESCALER_DIV1
  • LL_LPTIM_PRESCALER_DIV2
  • LL_LPTIM_PRESCALER_DIV4
  • LL_LPTIM_PRESCALER_DIV8
  • LL_LPTIM_PRESCALER_DIV16
  • LL_LPTIM_PRESCALER_DIV32
  • LL_LPTIM_PRESCALER_DIV64
  • LL_LPTIM_PRESCALER_DIV128

Definition at line 686 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode ( LPTIM_TypeDef * LPTIMx )

Get the LPTIM registers update mode.

Reference Manual to LL API cross reference:
CFGR PRELOAD LL_LPTIM_GetUpdateMode
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_UPDATE_MODE_IMMEDIATE
  • LL_LPTIM_UPDATE_MODE_ENDOFPERIOD

Definition at line 467 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform ( LPTIM_TypeDef * LPTIMx )

Get actual waveform shape.

Reference Manual to LL API cross reference:
CFGR WAVE LL_LPTIM_GetWaveform
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_OUTPUT_WAVEFORM_PWM
  • LL_LPTIM_OUTPUT_WAVEFORM_SETONCE

Definition at line 615 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled ( LPTIM_TypeDef * LPTIMx )

Indicates whether the LPTIM instance is enabled.

Reference Manual to LL API cross reference:
CR ENABLE LL_LPTIM_IsEnabled
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 371 of file stm32wbxx_ll_lptim.h.

Referenced by LL_LPTIM_Init().

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead ( LPTIM_TypeDef * LPTIMx )

Indicate whether the reset after read feature is enabled.

Reference Manual to LL API cross reference:
CR RSTARE LL_LPTIM_IsEnabledResetAfterRead
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 424 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_ResetCounter ( LPTIM_TypeDef * LPTIMx )

Reset of the LPTIM_CNT counter register (synchronous).

Note:
Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTIM core clock cycles (LPTIM core clock may be different from APB clock).
COUNTRST is automatically cleared by hardware
Reference Manual to LL API cross reference:
CR COUNTRST LL_LPTIM_ResetCounter
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 439 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetAutoReload | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | AutoReload
 | ) |  |

Set the auto reload value.

Note:
The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
After a write to the LPTIMx_ARR register a new write operation to the same register can only be performed when the previous write operation is completed. Any successive write before the ARROK flag is set, will lead to unpredictable results.
autoreload value be strictly greater than the compare value.
Reference Manual to LL API cross reference:
ARR ARR LL_LPTIM_SetAutoReload
Parameters:
LPTIMx | Low-Power Timer instance
AutoReload | Value between Min_Data=0x00 and Max_Data=0xFFFF
Return values:
None

Definition at line 485 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetCompare | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set the compare value.

Note:
After a write to the LPTIMx_CMP register a new write operation to the same register can only be performed when the previous write operation is completed. Any successive write before the CMPOK flag is set, will lead to unpredictable results.
Reference Manual to LL API cross reference:
CMP CMP LL_LPTIM_SetCompare
Parameters:
LPTIMx | Low-Power Timer instance
CompareValue | Value between Min_Data=0x00 and Max_Data=0xFFFF
Return values:
None

Definition at line 512 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetCounterMode | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | CounterMode
 | ) |  |

Set the counter mode (selection of the LPTIM counter clock source).

Note:
The counter mode can be set only when the LPTIM instance is disabled.
Reference Manual to LL API cross reference:
CFGR COUNTMODE LL_LPTIM_SetCounterMode
Parameters:
LPTIMx Low-Power Timer instance
CounterMode This parameter can be one of the following values:
  • LL_LPTIM_COUNTER_MODE_INTERNAL
  • LL_LPTIM_COUNTER_MODE_EXTERNAL
Return values:
None

Definition at line 553 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetInput1Src | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | Src
 | ) |  |

Set LPTIM input 1 source (default GPIO).

Reference Manual to LL API cross reference:
OR OR_0 LL_LPTIM_SetInput1Src
Reference Manual to LL API cross reference:
OR OR_1 LL_LPTIM_SetInput1Src
Parameters:
LPTIMx Low-Power Timer instance
Src This parameter can be one of the following values:
  • LL_LPTIM_INPUT1_SRC_GPIO
  • LL_LPTIM_INPUT1_SRC_COMP1
  • LL_LPTIM_INPUT1_SRC_COMP2
  • LL_LPTIM_INPUT1_SRC_COMP1_COMP2
Return values:
None

Definition at line 703 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetInput2Src | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | Src
 | ) |  |

Set LPTIM input 2 source (default GPIO).

Reference Manual to LL API cross reference:
OR OR_0 LL_LPTIM_SetInput2Src
Parameters:
LPTIMx Low-Power Timer instance
Src This parameter can be one of the following values:
  • LL_LPTIM_INPUT2_SRC_GPIO
  • LL_LPTIM_INPUT2_SRC_COMP2
Return values:
None

Definition at line 717 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetPolarity | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | Polarity
 | ) |  |

Set output polarity.

Reference Manual to LL API cross reference:
CFGR WAVPOL LL_LPTIM_SetPolarity
Parameters:
LPTIMx Low-Power Timer instance
Polarity This parameter can be one of the following values:
  • LL_LPTIM_OUTPUT_POLARITY_REGULAR
  • LL_LPTIM_OUTPUT_POLARITY_INVERSE
Return values:
None

Definition at line 629 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetPrescaler | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | Prescaler
 | ) |  |

Set actual prescaler division ratio.

Note:
This function must be called when the LPTIM instance is disabled.
When the LPTIM is configured to be clocked by an internal clock source and the LPTIM counter is configured to be updated by active edges detected on the LPTIM external Input1, the internal clock provided to the LPTIM must be not be prescaled.
Reference Manual to LL API cross reference:
CFGR PRESC LL_LPTIM_SetPrescaler
Parameters:
LPTIMx Low-Power Timer instance
Prescaler This parameter can be one of the following values:
  • LL_LPTIM_PRESCALER_DIV1
  • LL_LPTIM_PRESCALER_DIV2
  • LL_LPTIM_PRESCALER_DIV4
  • LL_LPTIM_PRESCALER_DIV8
  • LL_LPTIM_PRESCALER_DIV16
  • LL_LPTIM_PRESCALER_DIV32
  • LL_LPTIM_PRESCALER_DIV64
  • LL_LPTIM_PRESCALER_DIV128
Return values:
None

Definition at line 667 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetUpdateMode | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | UpdateMode
 | ) |  |

Set the LPTIM registers update mode (enable/disable register preload)

Note:
This function must be called when the LPTIM instance is disabled.
Reference Manual to LL API cross reference:
CFGR PRELOAD LL_LPTIM_SetUpdateMode
Parameters:
LPTIMx Low-Power Timer instance
UpdateMode This parameter can be one of the following values:
  • LL_LPTIM_UPDATE_MODE_IMMEDIATE
  • LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
Return values:
None

Definition at line 454 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetWaveform | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | Waveform
 | ) |  |

Set waveform shape.

Reference Manual to LL API cross reference:
CFGR WAVE LL_LPTIM_SetWaveform
Parameters:
LPTIMx Low-Power Timer instance
Waveform This parameter can be one of the following values:
  • LL_LPTIM_OUTPUT_WAVEFORM_PWM
  • LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
Return values:
None

Definition at line 602 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_StartCounter | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | OperatingMode
 | ) |  |

Starts the LPTIM counter in the desired mode.

Note:
LPTIM instance must be enabled before starting the counter.
It is possible to change on the fly from One Shot mode to Continuous mode.
Reference Manual to LL API cross reference:
CR CNTSTRT LL_LPTIM_StartCounter
CR SNGSTRT LL_LPTIM_StartCounter
Parameters:
LPTIMx Low-Power Timer instance
OperatingMode This parameter can be one of the following values:
  • LL_LPTIM_OPERATING_MODE_CONTINUOUS
  • LL_LPTIM_OPERATING_MODE_ONESHOT
Return values:
None

Definition at line 389 of file stm32wbxx_ll_lptim.h.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Trigger Configuration

Functions
Trigger Configuration
LPTIM Exported Functions

Functions

__STATIC_INLINE void | LL_LPTIM_EnableTimeout (LPTIM_TypeDef *LPTIMx)
Enable the timeout function.
__STATIC_INLINE void | LL_LPTIM_DisableTimeout (LPTIM_TypeDef *LPTIMx)
Disable the timeout function.
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledTimeout (LPTIM_TypeDef *LPTIMx)
Indicate whether the timeout function is enabled.
__STATIC_INLINE void | LL_LPTIM_TrigSw (LPTIM_TypeDef *LPTIMx)
Start the LPTIM counter.
__STATIC_INLINE void | LL_LPTIM_ConfigTrigger (LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
Configure the external trigger used as a trigger event for the LPTIM.
__STATIC_INLINE uint32_t | LL_LPTIM_GetTriggerSource (LPTIM_TypeDef *LPTIMx)
Get actual external trigger source.
__STATIC_INLINE uint32_t | LL_LPTIM_GetTriggerFilter (LPTIM_TypeDef *LPTIMx)
Get actual external trigger filter.
__STATIC_INLINE uint32_t | LL_LPTIM_GetTriggerPolarity (LPTIM_TypeDef *LPTIMx)
Get actual external trigger polarity.

Function Documentation

__STATIC_INLINE void LL_LPTIM_ConfigTrigger | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | Source,
 |  | uint32_t | Filter,
 |  | uint32_t | Polarity
 | ) |  |

Configure the external trigger used as a trigger event for the LPTIM.

Note:
This function must be called when the LPTIM instance is disabled.
An internal clock source must be present when a digital filter is required for the trigger.
Reference Manual to LL API cross reference:
CFGR TRIGSEL LL_LPTIM_ConfigTrigger
CFGR TRGFLT LL_LPTIM_ConfigTrigger
CFGR TRIGEN LL_LPTIM_ConfigTrigger
Parameters:
LPTIMx Low-Power Timer instance
Source This parameter can be one of the following values:
  • LL_LPTIM_TRIG_SOURCE_GPIO
  • LL_LPTIM_TRIG_SOURCE_RTCALARMA
  • LL_LPTIM_TRIG_SOURCE_RTCALARMB
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (*)
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP2
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (*)
  • LL_LPTIM_TRIG_SOURCE_COMP1 (*)
  • LL_LPTIM_TRIG_SOURCE_COMP2 (*)
(*) Value not defined in all devices.
Filter This parameter can be one of the following values:
  • LL_LPTIM_TRIG_FILTER_NONE
  • LL_LPTIM_TRIG_FILTER_2
  • LL_LPTIM_TRIG_FILTER_4
  • LL_LPTIM_TRIG_FILTER_8
Polarity This parameter can be one of the following values:
  • LL_LPTIM_TRIG_POLARITY_RISING
  • LL_LPTIM_TRIG_POLARITY_FALLING
  • LL_LPTIM_TRIG_POLARITY_RISING_FALLING
Return values:
None

Definition at line 816 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_DisableTimeout ( LPTIM_TypeDef * LPTIMx )

Disable the timeout function.

Note:
This function must be called when the LPTIM instance is disabled.
A trigger event arriving when the timer is already started will be ignored.
Reference Manual to LL API cross reference:
CFGR TIMOUT LL_LPTIM_DisableTimeout
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 756 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableTimeout ( LPTIM_TypeDef * LPTIMx )

Enable the timeout function.

Note:
This function must be called when the LPTIM instance is disabled.
The first trigger event will start the timer, any successive trigger event will reset the counter and the timer will restart.
The timeout value corresponds to the compare value; if no trigger occurs within the expected time frame, the MCU is waked-up by the compare match event.
Reference Manual to LL API cross reference:
CFGR TIMOUT LL_LPTIM_EnableTimeout
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 742 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter ( LPTIM_TypeDef * LPTIMx )

Get actual external trigger filter.

Reference Manual to LL API cross reference:
CFGR TRGFLT LL_LPTIM_GetTriggerFilter
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_TRIG_FILTER_NONE
  • LL_LPTIM_TRIG_FILTER_2
  • LL_LPTIM_TRIG_FILTER_4
  • LL_LPTIM_TRIG_FILTER_8

Definition at line 853 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity ( LPTIM_TypeDef * LPTIMx )

Get actual external trigger polarity.

Reference Manual to LL API cross reference:
CFGR TRIGEN LL_LPTIM_GetTriggerPolarity
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_TRIG_POLARITY_RISING
  • LL_LPTIM_TRIG_POLARITY_FALLING
  • LL_LPTIM_TRIG_POLARITY_RISING_FALLING

Definition at line 867 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource ( LPTIM_TypeDef * LPTIMx )

Get actual external trigger source.

Reference Manual to LL API cross reference:
CFGR TRIGSEL LL_LPTIM_GetTriggerSource
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_TRIG_SOURCE_GPIO
  • LL_LPTIM_TRIG_SOURCE_RTCALARMA
  • LL_LPTIM_TRIG_SOURCE_RTCALARMB
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (*)
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP2
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (*)
  • LL_LPTIM_TRIG_SOURCE_COMP1 (*)
  • LL_LPTIM_TRIG_SOURCE_COMP2 (*)
(*) Value not defined in all devices.

Definition at line 838 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout ( LPTIM_TypeDef * LPTIMx )

Indicate whether the timeout function is enabled.

Reference Manual to LL API cross reference:
CFGR TIMOUT LL_LPTIM_IsEnabledTimeout
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 767 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_TrigSw ( LPTIM_TypeDef * LPTIMx )

Start the LPTIM counter.

Note:
This function must be called when the LPTIM instance is disabled.
Reference Manual to LL API cross reference:
CFGR TRIGEN LL_LPTIM_TrigSw
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 779 of file stm32wbxx_ll_lptim.h.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Clock Configuration

Functions
Clock Configuration
LPTIM Exported Functions

Functions

__STATIC_INLINE void | LL_LPTIM_SetClockSource (LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
Set the source of the clock used by the LPTIM instance.
__STATIC_INLINE uint32_t | LL_LPTIM_GetClockSource (LPTIM_TypeDef *LPTIMx)
Get actual LPTIM instance clock source.
__STATIC_INLINE void | LL_LPTIM_ConfigClock (LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source.
__STATIC_INLINE uint32_t | LL_LPTIM_GetClockPolarity (LPTIM_TypeDef *LPTIMx)
Get actual clock polarity.
__STATIC_INLINE uint32_t | LL_LPTIM_GetClockFilter (LPTIM_TypeDef *LPTIMx)
Get actual clock digital filter.

Function Documentation

__STATIC_INLINE void LL_LPTIM_ConfigClock | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | ClockFilter,
 |  | uint32_t | ClockPolarity
 | ) |  |

Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source.

Note:
This function must be called when the LPTIM instance is disabled.
When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency.
An internal clock source must be present when a digital filter is required for external clock.
Reference Manual to LL API cross reference:
CFGR CKFLT LL_LPTIM_ConfigClock
CFGR CKPOL LL_LPTIM_ConfigClock
Parameters:
LPTIMx Low-Power Timer instance
ClockFilter This parameter can be one of the following values:
  • LL_LPTIM_CLK_FILTER_NONE
  • LL_LPTIM_CLK_FILTER_2
  • LL_LPTIM_CLK_FILTER_4
  • LL_LPTIM_CLK_FILTER_8
ClockPolarity This parameter can be one of the following values:
  • LL_LPTIM_CLK_POLARITY_RISING
  • LL_LPTIM_CLK_POLARITY_FALLING
  • LL_LPTIM_CLK_POLARITY_RISING_FALLING
Return values:
None

Definition at line 930 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter ( LPTIM_TypeDef * LPTIMx )

Get actual clock digital filter.

Reference Manual to LL API cross reference:
CFGR CKFLT LL_LPTIM_GetClockFilter
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_CLK_FILTER_NONE
  • LL_LPTIM_CLK_FILTER_2
  • LL_LPTIM_CLK_FILTER_4
  • LL_LPTIM_CLK_FILTER_8

Definition at line 959 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity ( LPTIM_TypeDef * LPTIMx )

Get actual clock polarity.

Reference Manual to LL API cross reference:
CFGR CKPOL LL_LPTIM_GetClockPolarity
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_CLK_POLARITY_RISING
  • LL_LPTIM_CLK_POLARITY_FALLING
  • LL_LPTIM_CLK_POLARITY_RISING_FALLING

Definition at line 944 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource ( LPTIM_TypeDef * LPTIMx )

Get actual LPTIM instance clock source.

Reference Manual to LL API cross reference:
CFGR CKSEL LL_LPTIM_GetClockSource
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_CLK_SOURCE_INTERNAL
  • LL_LPTIM_CLK_SOURCE_EXTERNAL

Definition at line 903 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetClockSource | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | ClockSource
 | ) |  |

Set the source of the clock used by the LPTIM instance.

Note:
This function must be called when the LPTIM instance is disabled.
Reference Manual to LL API cross reference:
CFGR CKSEL LL_LPTIM_SetClockSource
Parameters:
LPTIMx Low-Power Timer instance
ClockSource This parameter can be one of the following values:
  • LL_LPTIM_CLK_SOURCE_INTERNAL
  • LL_LPTIM_CLK_SOURCE_EXTERNAL
Return values:
None

Definition at line 890 of file stm32wbxx_ll_lptim.h.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Encoder Mode

Functions
Encoder Mode
LPTIM Exported Functions

Functions

__STATIC_INLINE void | LL_LPTIM_SetEncoderMode (LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
Configure the encoder mode.
__STATIC_INLINE uint32_t | LL_LPTIM_GetEncoderMode (LPTIM_TypeDef *LPTIMx)
Get actual encoder mode.
__STATIC_INLINE void | LL_LPTIM_EnableEncoderMode (LPTIM_TypeDef *LPTIMx)
Enable the encoder mode.
__STATIC_INLINE void | LL_LPTIM_DisableEncoderMode (LPTIM_TypeDef *LPTIMx)
Disable the encoder mode.
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledEncoderMode (LPTIM_TypeDef *LPTIMx)
Indicates whether the LPTIM operates in encoder mode.

Function Documentation

__STATIC_INLINE void LL_LPTIM_DisableEncoderMode ( LPTIM_TypeDef * LPTIMx )

Disable the encoder mode.

Note:
This function must be called when the LPTIM instance is disabled.
Reference Manual to LL API cross reference:
CFGR ENC LL_LPTIM_DisableEncoderMode
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1025 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableEncoderMode ( LPTIM_TypeDef * LPTIMx )

Enable the encoder mode.

Note:
This function must be called when the LPTIM instance is disabled.
In this mode the LPTIM instance must be clocked by an internal clock source. Also, the prescaler division ratio must be equal to 1.
LPTIM instance must be configured in continuous mode prior enabling the encoder mode.
Reference Manual to LL API cross reference:
CFGR ENC LL_LPTIM_EnableEncoderMode
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1013 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode ( LPTIM_TypeDef * LPTIMx )

Get actual encoder mode.

Reference Manual to LL API cross reference:
CFGR CKPOL LL_LPTIM_GetEncoderMode
Parameters:
LPTIMx Low-Power Timer instance
Return values:
Returned value can be one of the following values:
  • LL_LPTIM_ENCODER_MODE_RISING
  • LL_LPTIM_ENCODER_MODE_FALLING
  • LL_LPTIM_ENCODER_MODE_RISING_FALLING

Definition at line 997 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode ( LPTIM_TypeDef * LPTIMx )

Indicates whether the LPTIM operates in encoder mode.

Reference Manual to LL API cross reference:
CFGR ENC LL_LPTIM_IsEnabledEncoderMode
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1036 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_SetEncoderMode | ( | LPTIM_TypeDef * | LPTIMx,
 |  | uint32_t | EncoderMode
 | ) |  |

Configure the encoder mode.

Note:
This function must be called when the LPTIM instance is disabled.
Reference Manual to LL API cross reference:
CFGR CKPOL LL_LPTIM_SetEncoderMode
Parameters:
LPTIMx Low-Power Timer instance
EncoderMode This parameter can be one of the following values:
  • LL_LPTIM_ENCODER_MODE_RISING
  • LL_LPTIM_ENCODER_MODE_FALLING
  • LL_LPTIM_ENCODER_MODE_RISING_FALLING
Return values:
None

Definition at line 983 of file stm32wbxx_ll_lptim.h.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FLAG Management

Functions
FLAG Management
LPTIM Exported Functions

Functions

__STATIC_INLINE void | LL_LPTIM_ClearFLAG_CMPM (LPTIM_TypeDef *LPTIMx)
Clear the compare match flag (CMPMCF)
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_CMPM (LPTIM_TypeDef *LPTIMx)
Inform application whether a compare match interrupt has occurred.
__STATIC_INLINE void | LL_LPTIM_ClearFLAG_ARRM (LPTIM_TypeDef *LPTIMx)
Clear the autoreload match flag (ARRMCF)
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_ARRM (LPTIM_TypeDef *LPTIMx)
Inform application whether a autoreload match interrupt has occured.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Clear the external trigger valid edge flag(EXTTRIGCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Inform application whether a valid edge on the selected external trigger input has occurred.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_CMPOK (LPTIM_TypeDef *LPTIMx)
Clear the compare register update interrupt flag (CMPOKCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_CMPOK (LPTIM_TypeDef *LPTIMx)
Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_ARROK (LPTIM_TypeDef *LPTIMx)
Clear the autoreload register update interrupt flag (ARROKCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_ARROK (LPTIM_TypeDef *LPTIMx)
Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_UP (LPTIM_TypeDef *LPTIMx)
Clear the counter direction change to up interrupt flag (UPCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_UP (LPTIM_TypeDef *LPTIMx)
Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode).
__STATIC_INLINE void | LL_LPTIM_ClearFlag_DOWN (LPTIM_TypeDef *LPTIMx)
Clear the counter direction change to down interrupt flag (DOWNCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_DOWN (LPTIM_TypeDef *LPTIMx)
Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode).

Function Documentation

__STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM ( LPTIM_TypeDef * LPTIMx )

Clear the autoreload match flag (ARRMCF)

Reference Manual to LL API cross reference:
ICR ARRMCF LL_LPTIM_ClearFLAG_ARRM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1077 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK ( LPTIM_TypeDef * LPTIMx )

Clear the autoreload register update interrupt flag (ARROKCF).

Reference Manual to LL API cross reference:
ICR ARROKCF LL_LPTIM_ClearFlag_ARROK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1143 of file stm32wbxx_ll_lptim.h.

Referenced by LL_LPTIM_Disable().

__STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM ( LPTIM_TypeDef * LPTIMx )

Clear the compare match flag (CMPMCF)

Reference Manual to LL API cross reference:
ICR CMPMCF LL_LPTIM_ClearFLAG_CMPM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1055 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK ( LPTIM_TypeDef * LPTIMx )

Clear the compare register update interrupt flag (CMPOKCF).

Reference Manual to LL API cross reference:
ICR CMPOKCF LL_LPTIM_ClearFlag_CMPOK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1121 of file stm32wbxx_ll_lptim.h.

Referenced by LL_LPTIM_Disable().

__STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN ( LPTIM_TypeDef * LPTIMx )

Clear the counter direction change to down interrupt flag (DOWNCF).

Reference Manual to LL API cross reference:
ICR DOWNCF LL_LPTIM_ClearFlag_DOWN
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1187 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG ( LPTIM_TypeDef * LPTIMx )

Clear the external trigger valid edge flag(EXTTRIGCF).

Reference Manual to LL API cross reference:
ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1099 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_ClearFlag_UP ( LPTIM_TypeDef * LPTIMx )

Clear the counter direction change to up interrupt flag (UPCF).

Reference Manual to LL API cross reference:
ICR UPCF LL_LPTIM_ClearFlag_UP
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1165 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM ( LPTIM_TypeDef * LPTIMx )

Inform application whether a autoreload match interrupt has occured.

Reference Manual to LL API cross reference:
ISR ARRM LL_LPTIM_IsActiveFlag_ARRM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1088 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK ( LPTIM_TypeDef * LPTIMx )

Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed.

If so, a new one can be initiated.

Reference Manual to LL API cross reference:
ISR ARROK LL_LPTIM_IsActiveFlag_ARROK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1154 of file stm32wbxx_ll_lptim.h.

Referenced by LL_LPTIM_Disable().

__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM ( LPTIM_TypeDef * LPTIMx )

Inform application whether a compare match interrupt has occurred.

Reference Manual to LL API cross reference:
ISR CMPM LL_LPTIM_IsActiveFlag_CMPM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1066 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK ( LPTIM_TypeDef * LPTIMx )

Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed.

If so, a new one can be initiated.

Reference Manual to LL API cross reference:
ISR CMPOK LL_LPTIM_IsActiveFlag_CMPOK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1132 of file stm32wbxx_ll_lptim.h.

Referenced by LL_LPTIM_Disable().

__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN ( LPTIM_TypeDef * LPTIMx )

Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode).

Reference Manual to LL API cross reference:
ISR DOWN LL_LPTIM_IsActiveFlag_DOWN
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1198 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG ( LPTIM_TypeDef * LPTIMx )

Inform application whether a valid edge on the selected external trigger input has occurred.

Reference Manual to LL API cross reference:
ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1110 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP ( LPTIM_TypeDef * LPTIMx )

Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode).

Reference Manual to LL API cross reference:
ISR UP LL_LPTIM_IsActiveFlag_UP
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1176 of file stm32wbxx_ll_lptim.h.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Interrupt Management

Functions
Interrupt Management
LPTIM Exported Functions

Functions

__STATIC_INLINE void | LL_LPTIM_EnableIT_CMPM (LPTIM_TypeDef *LPTIMx)
Enable compare match interrupt (CMPMIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_CMPM (LPTIM_TypeDef *LPTIMx)
Disable compare match interrupt (CMPMIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_CMPM (LPTIM_TypeDef *LPTIMx)
Indicates whether the compare match interrupt (CMPMIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_ARRM (LPTIM_TypeDef *LPTIMx)
Enable autoreload match interrupt (ARRMIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_ARRM (LPTIM_TypeDef *LPTIMx)
Disable autoreload match interrupt (ARRMIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_ARRM (LPTIM_TypeDef *LPTIMx)
Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Enable external trigger valid edge interrupt (EXTTRIGIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Disable external trigger valid edge interrupt (EXTTRIGIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_CMPOK (LPTIM_TypeDef *LPTIMx)
Enable compare register write completed interrupt (CMPOKIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_CMPOK (LPTIM_TypeDef *LPTIMx)
Disable compare register write completed interrupt (CMPOKIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_CMPOK (LPTIM_TypeDef *LPTIMx)
Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_ARROK (LPTIM_TypeDef *LPTIMx)
Enable autoreload register write completed interrupt (ARROKIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_ARROK (LPTIM_TypeDef *LPTIMx)
Disable autoreload register write completed interrupt (ARROKIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_ARROK (LPTIM_TypeDef *LPTIMx)
Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_UP (LPTIM_TypeDef *LPTIMx)
Enable direction change to up interrupt (UPIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_UP (LPTIM_TypeDef *LPTIMx)
Disable direction change to up interrupt (UPIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_UP (LPTIM_TypeDef *LPTIMx)
Indicates whether the direction change to up interrupt (UPIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_DOWN (LPTIM_TypeDef *LPTIMx)
Enable direction change to down interrupt (DOWNIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_DOWN (LPTIM_TypeDef *LPTIMx)
Disable direction change to down interrupt (DOWNIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_DOWN (LPTIM_TypeDef *LPTIMx)
Indicates whether the direction change to down interrupt (DOWNIE) is enabled.

Function Documentation

__STATIC_INLINE void LL_LPTIM_DisableIT_ARRM ( LPTIM_TypeDef * LPTIMx )

Disable autoreload match interrupt (ARRMIE).

Reference Manual to LL API cross reference:
IER ARRMIE LL_LPTIM_DisableIT_ARRM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1261 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_DisableIT_ARROK ( LPTIM_TypeDef * LPTIMx )

Disable autoreload register write completed interrupt (ARROKIE).

Reference Manual to LL API cross reference:
IER ARROKIE LL_LPTIM_DisableIT_ARROK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1360 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_DisableIT_CMPM ( LPTIM_TypeDef * LPTIMx )

Disable compare match interrupt (CMPMIE).

Reference Manual to LL API cross reference:
IER CMPMIE LL_LPTIM_DisableIT_CMPM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1228 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK ( LPTIM_TypeDef * LPTIMx )

Disable compare register write completed interrupt (CMPOKIE).

Reference Manual to LL API cross reference:
IER CMPOKIE LL_LPTIM_DisableIT_CMPOK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1327 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_DisableIT_DOWN ( LPTIM_TypeDef * LPTIMx )

Disable direction change to down interrupt (DOWNIE).

Reference Manual to LL API cross reference:
IER DOWNIE LL_LPTIM_DisableIT_DOWN
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1426 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG ( LPTIM_TypeDef * LPTIMx )

Disable external trigger valid edge interrupt (EXTTRIGIE).

Reference Manual to LL API cross reference:
IER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1294 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_DisableIT_UP ( LPTIM_TypeDef * LPTIMx )

Disable direction change to up interrupt (UPIE).

Reference Manual to LL API cross reference:
IER UPIE LL_LPTIM_DisableIT_UP
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1393 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableIT_ARRM ( LPTIM_TypeDef * LPTIMx )

Enable autoreload match interrupt (ARRMIE).

Reference Manual to LL API cross reference:
IER ARRMIE LL_LPTIM_EnableIT_ARRM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1250 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableIT_ARROK ( LPTIM_TypeDef * LPTIMx )

Enable autoreload register write completed interrupt (ARROKIE).

Reference Manual to LL API cross reference:
IER ARROKIE LL_LPTIM_EnableIT_ARROK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1349 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableIT_CMPM ( LPTIM_TypeDef * LPTIMx )

Enable compare match interrupt (CMPMIE).

Reference Manual to LL API cross reference:
IER CMPMIE LL_LPTIM_EnableIT_CMPM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1217 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableIT_CMPOK ( LPTIM_TypeDef * LPTIMx )

Enable compare register write completed interrupt (CMPOKIE).

Reference Manual to LL API cross reference:
IER CMPOKIE LL_LPTIM_EnableIT_CMPOK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1316 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableIT_DOWN ( LPTIM_TypeDef * LPTIMx )

Enable direction change to down interrupt (DOWNIE).

Reference Manual to LL API cross reference:
IER DOWNIE LL_LPTIM_EnableIT_DOWN
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1415 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG ( LPTIM_TypeDef * LPTIMx )

Enable external trigger valid edge interrupt (EXTTRIGIE).

Reference Manual to LL API cross reference:
IER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1283 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE void LL_LPTIM_EnableIT_UP ( LPTIM_TypeDef * LPTIMx )

Enable direction change to up interrupt (UPIE).

Reference Manual to LL API cross reference:
IER UPIE LL_LPTIM_EnableIT_UP
Parameters:
LPTIMx Low-Power Timer instance
Return values:
None

Definition at line 1382 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM ( LPTIM_TypeDef * LPTIMx )

Indicates whether the autoreload match interrupt (ARRMIE) is enabled.

Reference Manual to LL API cross reference:
IER ARRMIE LL_LPTIM_IsEnabledIT_ARRM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1272 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK ( LPTIM_TypeDef * LPTIMx )

Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.

Reference Manual to LL API cross reference:
IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1371 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM ( LPTIM_TypeDef * LPTIMx )

Indicates whether the compare match interrupt (CMPMIE) is enabled.

Reference Manual to LL API cross reference:
IER CMPMIE LL_LPTIM_IsEnabledIT_CMPM
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1239 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK ( LPTIM_TypeDef * LPTIMx )

Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.

Reference Manual to LL API cross reference:
IER CMPOKIE LL_LPTIM_IsEnabledIT_CMPOK
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1338 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN ( LPTIM_TypeDef * LPTIMx )

Indicates whether the direction change to down interrupt (DOWNIE) is enabled.

Reference Manual to LL API cross reference:
IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1437 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG ( LPTIM_TypeDef * LPTIMx )

Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.

Reference Manual to LL API cross reference:
IER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1305 of file stm32wbxx_ll_lptim.h.

__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP ( LPTIM_TypeDef * LPTIMx )

Indicates whether the direction change to up interrupt (UPIE) is enabled.

Reference Manual to LL API cross reference:
IER UPIE LL_LPTIM_IsEnabledIT_UP
Parameters:
LPTIMx Low-Power Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1404 of file stm32wbxx_ll_lptim.h.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPUART

Modules
LPUART
STM32WBxx_LL_Driver

Modules

LPUART Private Variables
LPUART Private Constants
LPUART Private Macros
LPUART Exported Init structures
LPUART Exported Constants
LPUART Exported Macros
LPUART Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for LPUART registers.

Register | Bit | Function
BRR | BRR | LL_LPUART_GetBaudRate
 |  | LL_LPUART_SetBaudRate
CR1 | CMIE | LL_LPUART_DisableIT_CM
 |  | LL_LPUART_EnableIT_CM
 |  | LL_LPUART_IsEnabledIT_CM
 | DEAT | LL_LPUART_GetDEAssertionTime
 |  | LL_LPUART_SetDEAssertionTime
 | DEDT | LL_LPUART_GetDEDeassertionTime
 |  | LL_LPUART_SetDEDeassertionTime
 | FIFOEN | LL_LPUART_DisableFIFO
 |  | LL_LPUART_EnableFIFO
 |  | LL_LPUART_IsEnabledFIFO
 | IDLEIE | LL_LPUART_DisableIT_IDLE
 |  | LL_LPUART_EnableIT_IDLE
 |  | LL_LPUART_IsEnabledIT_IDLE
 | M | LL_LPUART_ConfigCharacter
 |  | LL_LPUART_GetDataWidth
 |  | LL_LPUART_SetDataWidth
 | MME | LL_LPUART_DisableMuteMode
 |  | LL_LPUART_EnableMuteMode
 |  | LL_LPUART_IsEnabledMuteMode
 | PCE | LL_LPUART_ConfigCharacter
 |  | LL_LPUART_GetParity
 |  | LL_LPUART_SetParity
 | PEIE | LL_LPUART_DisableIT_PE
 |  | LL_LPUART_EnableIT_PE
 |  | LL_LPUART_IsEnabledIT_PE
 | PS | LL_LPUART_ConfigCharacter
 |  | LL_LPUART_GetParity
 |  | LL_LPUART_SetParity
 | RE | LL_LPUART_DisableDirectionRx
 |  | LL_LPUART_EnableDirectionRx
 |  | LL_LPUART_GetTransferDirection
 |  | LL_LPUART_SetTransferDirection
 | RXFFIE | LL_LPUART_DisableIT_RXFF
 |  | LL_LPUART_EnableIT_RXFF
 |  | LL_LPUART_IsEnabledIT_RXFF
 | RXNEIE_RXFNEIE | LL_LPUART_DisableIT_RXNE_RXFNE
 |  | LL_LPUART_EnableIT_RXNE_RXFNE
 |  | LL_LPUART_IsEnabledIT_RXNE_RXFNE
 | TCIE | LL_LPUART_DisableIT_TC
 |  | LL_LPUART_EnableIT_TC
 |  | LL_LPUART_IsEnabledIT_TC
 | TE | LL_LPUART_DisableDirectionTx
 |  | LL_LPUART_EnableDirectionTx
 |  | LL_LPUART_GetTransferDirection
 |  | LL_LPUART_SetTransferDirection
 | TXEIE_TXFNFIE | LL_LPUART_DisableIT_TXE_TXFNF
 |  | LL_LPUART_EnableIT_TXE_TXFNF
 |  | LL_LPUART_IsEnabledIT_TXE_TXFNF
 | TXFEIE | LL_LPUART_DisableIT_TXFE
 |  | LL_LPUART_EnableIT_TXFE
 |  | LL_LPUART_IsEnabledIT_TXFE
 | UE | LL_LPUART_Disable
 |  | LL_LPUART_Enable
 |  | LL_LPUART_IsEnabled
 | UESM | LL_LPUART_DisableInStopMode
 |  | LL_LPUART_EnableInStopMode
 |  | LL_LPUART_IsEnabledInStopMode
 | WAKE | LL_LPUART_GetWakeUpMethod
 |  | LL_LPUART_SetWakeUpMethod
CR2 | ADD | LL_LPUART_ConfigNodeAddress
 |  | LL_LPUART_GetNodeAddress
 | ADDM7 | LL_LPUART_ConfigNodeAddress
 |  | LL_LPUART_GetNodeAddressLen
 | DATAINV | LL_LPUART_GetBinaryDataLogic
 |  | LL_LPUART_SetBinaryDataLogic
 | MSBFIRST | LL_LPUART_GetTransferBitOrder
 |  | LL_LPUART_SetTransferBitOrder
 | RXINV | LL_LPUART_GetRXPinLevel
 |  | LL_LPUART_SetRXPinLevel
 | STOP | LL_LPUART_ConfigCharacter
 |  | LL_LPUART_GetStopBitsLength
 |  | LL_LPUART_SetStopBitsLength
 | SWAP | LL_LPUART_GetTXRXSwap
 |  | LL_LPUART_SetTXRXSwap
 | TXINV | LL_LPUART_GetTXPinLevel
 |  | LL_LPUART_SetTXPinLevel
CR3 | CTSE | LL_LPUART_DisableCTSHWFlowCtrl
 |  | LL_LPUART_EnableCTSHWFlowCtrl
 |  | LL_LPUART_GetHWFlowCtrl
 |  | LL_LPUART_SetHWFlowCtrl
 | CTSIE | LL_LPUART_DisableIT_CTS
 |  | LL_LPUART_EnableIT_CTS
 |  | LL_LPUART_IsEnabledIT_CTS
 | DDRE | LL_LPUART_DisableDMADeactOnRxErr
 |  | LL_LPUART_EnableDMADeactOnRxErr
 |  | LL_LPUART_IsEnabledDMADeactOnRxErr
 | DEM | LL_LPUART_DisableDEMode
 |  | LL_LPUART_EnableDEMode
 |  | LL_LPUART_IsEnabledDEMode
 | DEP | LL_LPUART_GetDESignalPolarity
 |  | LL_LPUART_SetDESignalPolarity
 | DMAR | LL_LPUART_DisableDMAReq_RX
 |  | LL_LPUART_EnableDMAReq_RX
 |  | LL_LPUART_IsEnabledDMAReq_RX
 | DMAT | LL_LPUART_DisableDMAReq_TX
 |  | LL_LPUART_EnableDMAReq_TX
 |  | LL_LPUART_IsEnabledDMAReq_TX
 | EIE | LL_LPUART_DisableIT_ERROR
 |  | LL_LPUART_EnableIT_ERROR
 |  | LL_LPUART_IsEnabledIT_ERROR
 | HDSEL | LL_LPUART_DisableHalfDuplex
 |  | LL_LPUART_EnableHalfDuplex
 |  | LL_LPUART_IsEnabledHalfDuplex
 | OVRDIS | LL_LPUART_DisableOverrunDetect
 |  | LL_LPUART_EnableOverrunDetect
 |  | LL_LPUART_IsEnabledOverrunDetect
 | RTSE | LL_LPUART_DisableRTSHWFlowCtrl
 |  | LL_LPUART_EnableRTSHWFlowCtrl
 |  | LL_LPUART_GetHWFlowCtrl
 |  | LL_LPUART_SetHWFlowCtrl
 | RXFTCFG | LL_LPUART_ConfigFIFOsThreshold
 |  | LL_LPUART_GetRXFIFOThreshold
 |  | LL_LPUART_SetRXFIFOThreshold
 | RXFTIE | LL_LPUART_DisableIT_RXFT
 |  | LL_LPUART_EnableIT_RXFT
 |  | LL_LPUART_IsEnabledIT_RXFT
 | TXFTCFG | LL_LPUART_ConfigFIFOsThreshold
 |  | LL_LPUART_GetTXFIFOThreshold
 |  | LL_LPUART_SetTXFIFOThreshold
 | TXFTIE | LL_LPUART_DisableIT_TXFT
 |  | LL_LPUART_EnableIT_TXFT
 |  | LL_LPUART_IsEnabledIT_TXFT
 | WUFIE | LL_LPUART_DisableIT_WKUP
 |  | LL_LPUART_EnableIT_WKUP
 |  | LL_LPUART_IsEnabledIT_WKUP
 | WUS | LL_LPUART_GetWKUPType
 |  | LL_LPUART_SetWKUPType
ICR | CMCF | LL_LPUART_ClearFlag_CM
 | CTSCF | LL_LPUART_ClearFlag_nCTS
 | FECF | LL_LPUART_ClearFlag_FE
 | IDLECF | LL_LPUART_ClearFlag_IDLE
 | NECF | LL_LPUART_ClearFlag_NE
 | ORECF | LL_LPUART_ClearFlag_ORE
 | PECF | LL_LPUART_ClearFlag_PE
 | TCCF | LL_LPUART_ClearFlag_TC
 | TXFECF | LL_LPUART_ClearFlag_TXFE
 | WUCF | LL_LPUART_ClearFlag_WKUP
ISR | BUSY | LL_LPUART_IsActiveFlag_BUSY
 | CMF | LL_LPUART_IsActiveFlag_CM
 | CTS | LL_LPUART_IsActiveFlag_CTS
 | CTSIF | LL_LPUART_IsActiveFlag_nCTS
 | FE | LL_LPUART_IsActiveFlag_FE
 | IDLE | LL_LPUART_IsActiveFlag_IDLE
 | NE | LL_LPUART_IsActiveFlag_NE
 | ORE | LL_LPUART_IsActiveFlag_ORE
 | PE | LL_LPUART_IsActiveFlag_PE
 | REACK | LL_LPUART_IsActiveFlag_REACK
 | RWU | LL_LPUART_IsActiveFlag_RWU
 | RXFF | LL_LPUART_IsActiveFlag_RXFF
 | RXFT | LL_LPUART_IsActiveFlag_RXFT
 | RXNE_RXFNE | LL_LPUART_IsActiveFlag_RXNE_RXFNE
 | SBKF | LL_LPUART_IsActiveFlag_SBK
 | TC | LL_LPUART_IsActiveFlag_TC
 | TEACK | LL_LPUART_IsActiveFlag_TEACK
 | TXE_TXFNF | LL_LPUART_IsActiveFlag_TXE_TXFNF
 | TXFE | LL_LPUART_IsActiveFlag_TXFE
 | TXFT | LL_LPUART_IsActiveFlag_TXFT
 | WUF | LL_LPUART_IsActiveFlag_WKUP
PRESC | PRESCALER | LL_LPUART_GetPrescaler
 |  | LL_LPUART_SetPrescaler
RDR | RDR | LL_LPUART_DMA_GetRegAddr
 |  | LL_LPUART_ReceiveData8
 |  | LL_LPUART_ReceiveData9
RQR | MMRQ | LL_LPUART_RequestEnterMuteMode
 | RXFRQ | LL_LPUART_RequestRxDataFlush
 | SBKRQ | LL_LPUART_RequestBreakSending
TDR | TDR | LL_LPUART_DMA_GetRegAddr
 |  | LL_LPUART_TransmitData8
 |  | LL_LPUART_TransmitData9
Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPUART Private Variables

Variables
LPUART Private Variables
LPUART

Variables

static const uint16_t LPUART_PRESCALER_TAB []

Variable Documentation

const uint16_t LPUART_PRESCALER_TAB[] [static]
Initial value:
{
  (uint16_t)1,
  (uint16_t)2,
  (uint16_t)4,
  (uint16_t)6,
  (uint16_t)8,
  (uint16_t)10,
  (uint16_t)12,
  (uint16_t)16,
  (uint16_t)32,
  (uint16_t)64,
  (uint16_t)128,
  (uint16_t)256
}

Definition at line 47 of file stm32wbxx_ll_lpuart.h.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPUART Private Constants

Defines
LPUART Private Constants
LPUART

Defines

#define | LPUART_LPUARTDIV_FREQ_MUL 256U
#define | LPUART_BRR_MASK 0x000FFFFFU
#define | LPUART_BRR_MIN_VALUE 0x00000300U

Define Documentation

#define LPUART_BRR_MASK 0x000FFFFFU

Definition at line 72 of file stm32wbxx_ll_lpuart.h.

Referenced by LL_LPUART_GetBaudRate().

#define LPUART_BRR_MIN_VALUE 0x00000300U

Definition at line 73 of file stm32wbxx_ll_lpuart.h.

Referenced by LL_LPUART_GetBaudRate().

#define LPUART_LPUARTDIV_FREQ_MUL 256U

Definition at line 71 of file stm32wbxx_ll_lpuart.h.

Referenced by LL_LPUART_GetBaudRate().

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPUART Private Macros

Defines
LPUART Private Macros
LPUART

Defines

#define | IS_LL_LPUART_PRESCALER(__VALUE__)
#define | IS_LL_LPUART_BAUDRATE(__BAUDRATE__) (((__BAUDRATE__) <= 21300000U) && ((__BAUDRATE__) >= 8U))
#define | IS_LL_LPUART_BRR_MIN(__VALUE__) ((__VALUE__) >= 0x300U)
#define | IS_LL_LPUART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x000FFFFFU)
#define | IS_LL_LPUART_DIRECTION(__VALUE__)
#define | IS_LL_LPUART_PARITY(__VALUE__)
#define | IS_LL_LPUART_DATAWIDTH(__VALUE__)
#define | IS_LL_LPUART_STOPBITS(__VALUE__)
#define | IS_LL_LPUART_HWCONTROL(__VALUE__)

Define Documentation

#define IS_LL_LPUART_BAUDRATE ( __BAUDRATE__ ) (((__BAUDRATE__) <= 21300000U) && ((__BAUDRATE__) >= 8U))

Definition at line 79 of file stm32wbxx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

#define IS_LL_LPUART_BRR_MAX ( __VALUE__ ) ((__VALUE__) <= 0x000FFFFFU)

Definition at line 85 of file stm32wbxx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

#define IS_LL_LPUART_BRR_MIN ( __VALUE__ ) ((__VALUE__) >= 0x300U)

Definition at line 82 of file stm32wbxx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

#define IS_LL_LPUART_DATAWIDTH ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPUART_DATAWIDTH_7B) \
                                           || ((__VALUE__) == LL_LPUART_DATAWIDTH_8B) \
                                           || ((__VALUE__) == LL_LPUART_DATAWIDTH_9B))

Definition at line 96 of file stm32wbxx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

#define IS_LL_LPUART_DIRECTION ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPUART_DIRECTION_NONE) \
                                           || ((__VALUE__) == LL_LPUART_DIRECTION_RX) \
                                           || ((__VALUE__) == LL_LPUART_DIRECTION_TX) \
                                           || ((__VALUE__) == LL_LPUART_DIRECTION_TX_RX))

Definition at line 87 of file stm32wbxx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

#define IS_LL_LPUART_HWCONTROL ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPUART_HWCONTROL_NONE) \
                                           || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS) \
                                           || ((__VALUE__) == LL_LPUART_HWCONTROL_CTS) \
                                           || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS_CTS))

Definition at line 103 of file stm32wbxx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

#define IS_LL_LPUART_PARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPUART_PARITY_NONE) \
                                        || ((__VALUE__) == LL_LPUART_PARITY_EVEN) \
                                        || ((__VALUE__) == LL_LPUART_PARITY_ODD))

Definition at line 92 of file stm32wbxx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

#define IS_LL_LPUART_PRESCALER ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPUART_PRESCALER_DIV1) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV2) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV4) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV6) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV8) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV10) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV12) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV16) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV32) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV64) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV128) \
                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV256))

Definition at line 60 of file stm32wbxx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

#define IS_LL_LPUART_STOPBITS ( __VALUE__ )
Value:
(((__VALUE__) == LL_LPUART_STOPBITS_1) \
                                          || ((__VALUE__) == LL_LPUART_STOPBITS_2))

Definition at line 100 of file stm32wbxx_ll_lpuart.c.

Referenced by LL_LPUART_Init().

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LL_LPUART_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_LPUART_InitTypeDef Struct Reference
LPUART Exported Init structures

LL LPUART Init Structure definition. More...

#include <stm32wbxx_ll_lpuart.h>

Data Fields

uint32_t | PrescalerValue
uint32_t | BaudRate
uint32_t | DataWidth
uint32_t | StopBits
uint32_t | Parity
uint32_t | TransferDirection
uint32_t | HardwareFlowControl

Detailed Description

LL LPUART Init Structure definition.

Definition at line 98 of file stm32wbxx_ll_lpuart.h.

Field Documentation

uint32_t LL_LPUART_InitTypeDef::BaudRate

This field defines expected LPUART communication baud rate.

This feature can be modified afterwards using unitary function LL_LPUART_SetBaudRate().

Definition at line 105 of file stm32wbxx_ll_lpuart.h.

Referenced by LL_LPUART_Init(), and LL_LPUART_StructInit().

uint32_t LL_LPUART_InitTypeDef::DataWidth

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of Datawidth.

This feature can be modified afterwards using unitary function LL_LPUART_SetDataWidth().

Definition at line 109 of file stm32wbxx_ll_lpuart.h.

Referenced by LL_LPUART_Init(), and LL_LPUART_StructInit().

uint32_t LL_LPUART_InitTypeDef::HardwareFlowControl

Specifies whether the hardware flow control mode is enabled or disabled. This parameter can be a value of Hardware Control.

This feature can be modified afterwards using unitary function LL_LPUART_SetHWFlowCtrl().

Definition at line 129 of file stm32wbxx_ll_lpuart.h.

Referenced by LL_LPUART_Init(), and LL_LPUART_StructInit().

uint32_t LL_LPUART_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of Parity Control.

This feature can be modified afterwards using unitary function LL_LPUART_SetParity().

Definition at line 119 of file stm32wbxx_ll_lpuart.h.

Referenced by LL_LPUART_Init(), and LL_LPUART_StructInit().

uint32_t LL_LPUART_InitTypeDef::PrescalerValue

Specifies the Prescaler to compute the communication baud rate. This parameter can be a value of Clock Source Prescaler.

This feature can be modified afterwards using unitary function LL_LPUART_SetPrescaler().

Definition at line 100 of file stm32wbxx_ll_lpuart.h.

Referenced by LL_LPUART_Init(), and LL_LPUART_StructInit().

uint32_t LL_LPUART_InitTypeDef::StopBits

Specifies the number of stop bits transmitted. This parameter can be a value of Stop Bits.

This feature can be modified afterwards using unitary function LL_LPUART_SetStopBitsLength().

Definition at line 114 of file stm32wbxx_ll_lpuart.h.

Referenced by LL_LPUART_Init(), and LL_LPUART_StructInit().

uint32_t LL_LPUART_InitTypeDef::TransferDirection

Specifies whether the Receive and/or Transmit mode is enabled or disabled. This parameter can be a value of Direction.

This feature can be modified afterwards using unitary function LL_LPUART_SetTransferDirection().

Definition at line 124 of file stm32wbxx_ll_lpuart.h.

Referenced by LL_LPUART_Init(), and LL_LPUART_StructInit().

The documentation for this struct was generated from the following file:
  • stm32wbxx_ll_lpuart.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
LPUART Exported Constants

Flags defines which can be used with LL_LPUART_WriteReg function. More...

Defines

#define | LL_LPUART_ICR_PECF USART_ICR_PECF
#define | LL_LPUART_ICR_FECF USART_ICR_FECF
#define | LL_LPUART_ICR_NCF USART_ICR_NECF
#define | LL_LPUART_ICR_ORECF USART_ICR_ORECF
#define | LL_LPUART_ICR_IDLECF USART_ICR_IDLECF
#define | LL_LPUART_ICR_TXFECF USART_ICR_TXFECF
#define | LL_LPUART_ICR_TCCF USART_ICR_TCCF
#define | LL_LPUART_ICR_CTSCF USART_ICR_CTSCF
#define | LL_LPUART_ICR_CMCF USART_ICR_CMCF
#define | LL_LPUART_ICR_WUCF USART_ICR_WUCF

Detailed Description

Flags defines which can be used with LL_LPUART_WriteReg function.

Define Documentation

#define LL_LPUART_ICR_CMCF USART_ICR_CMCF

Character match flag

Definition at line 158 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF

CTS flag

Definition at line 157 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_ICR_FECF USART_ICR_FECF

Framing error flag

Definition at line 151 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF

Idle line detected flag

Definition at line 154 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_ICR_NCF USART_ICR_NECF

Noise error detected flag

Definition at line 152 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_ICR_ORECF USART_ICR_ORECF

Overrun error flag

Definition at line 153 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_ICR_PECF USART_ICR_PECF

Parity error flag

Definition at line 150 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_ICR_TCCF USART_ICR_TCCF

Transmission complete flag

Definition at line 156 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_ICR_TXFECF USART_ICR_TXFECF

TX FIFO Empty Clear flag

Definition at line 155 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_ICR_WUCF USART_ICR_WUCF

Wakeup from Stop mode flag

Definition at line 159 of file stm32wbxx_ll_lpuart.h.

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STM32WB55xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
LPUART Exported Constants

Flags defines which can be used with LL_LPUART_ReadReg function. More...

Defines

#define | LL_LPUART_ISR_PE USART_ISR_PE
#define | LL_LPUART_ISR_FE USART_ISR_FE
#define | LL_LPUART_ISR_NE USART_ISR_NE
#define | LL_LPUART_ISR_ORE USART_ISR_ORE
#define | LL_LPUART_ISR_IDLE USART_ISR_IDLE
#define | LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE
#define | LL_LPUART_ISR_TC USART_ISR_TC
#define | LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF
#define | LL_LPUART_ISR_CTSIF USART_ISR_CTSIF
#define | LL_LPUART_ISR_CTS USART_ISR_CTS
#define | LL_LPUART_ISR_BUSY USART_ISR_BUSY
#define | LL_LPUART_ISR_CMF USART_ISR_CMF
#define | LL_LPUART_ISR_SBKF USART_ISR_SBKF
#define | LL_LPUART_ISR_RWU USART_ISR_RWU
#define | LL_LPUART_ISR_WUF USART_ISR_WUF
#define | LL_LPUART_ISR_TEACK USART_ISR_TEACK
#define | LL_LPUART_ISR_REACK USART_ISR_REACK
#define | LL_LPUART_ISR_TXFE USART_ISR_TXFE
#define | LL_LPUART_ISR_RXFF USART_ISR_RXFF
#define | LL_LPUART_ISR_RXFT USART_ISR_RXFT
#define | LL_LPUART_ISR_TXFT USART_ISR_TXFT

Detailed Description

Flags defines which can be used with LL_LPUART_ReadReg function.

Define Documentation

#define LL_LPUART_ISR_BUSY USART_ISR_BUSY

Busy flag

Definition at line 178 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_ISR_CMF USART_ISR_CMF

Character match flag

Definition at line 179 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_ISR_CTS USART_ISR_CTS

CTS flag

Definition at line 177 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF

CTS interrupt flag

Definition at line 176 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_ISR_FE USART_ISR_FE

Framing error flag

Definition at line 169 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_ISR_IDLE USART_ISR_IDLE

Idle line detected flag

Definition at line 172 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_ISR_NE USART_ISR_NE

Noise detected flag

Definition at line 170 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_ISR_ORE USART_ISR_ORE

Overrun error flag

Definition at line 171 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_ISR_PE USART_ISR_PE

Parity error flag

Definition at line 168 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_ISR_REACK USART_ISR_REACK

Receive enable acknowledge flag

Definition at line 184 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_ISR_RWU USART_ISR_RWU

Receiver wakeup from Mute mode flag

Definition at line 181 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_ISR_RXFF USART_ISR_RXFF

RX FIFO full flag

Definition at line 186 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_ISR_RXFT USART_ISR_RXFT

RX FIFO threshold flag

Definition at line 187 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE

Read data register or RX FIFO not empty flag

Definition at line 173 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_ISR_SBKF USART_ISR_SBKF

Send break flag

Definition at line 180 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_ISR_TC USART_ISR_TC

Transmission complete flag

Definition at line 174 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_ISR_TEACK USART_ISR_TEACK

Transmit enable acknowledge flag

Definition at line 183 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF

Transmit data register empty or TX FIFO Not Full flag

Definition at line 175 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_ISR_TXFE USART_ISR_TXFE

TX FIFO empty flag

Definition at line 185 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_ISR_TXFT USART_ISR_TXFT

TX FIFO threshold flag

Definition at line 188 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_ISR_WUF USART_ISR_WUF

Wakeup from Stop mode flag

Definition at line 182 of file stm32wbxx_ll_lpuart.h.

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STM32WB55xx HAL User Manual: IT Defines

Defines
IT Defines
LPUART Exported Constants

IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions. More...

Defines

#define | LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE
#define | LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE
#define | LL_LPUART_CR1_TCIE USART_CR1_TCIE
#define | LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE
#define | LL_LPUART_CR1_PEIE USART_CR1_PEIE
#define | LL_LPUART_CR1_CMIE USART_CR1_CMIE
#define | LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE
#define | LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE
#define | LL_LPUART_CR3_EIE USART_CR3_EIE
#define | LL_LPUART_CR3_CTSIE USART_CR3_CTSIE
#define | LL_LPUART_CR3_WUFIE USART_CR3_WUFIE
#define | LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE
#define | LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE

Detailed Description

IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions.

Define Documentation

#define LL_LPUART_CR1_CMIE USART_CR1_CMIE

Character match interrupt enable

Definition at line 202 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE

IDLE interrupt enable

Definition at line 197 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_CR1_PEIE USART_CR1_PEIE

Parity error

Definition at line 201 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE

RX FIFO full interrupt enable

Definition at line 204 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE

Read data register and RXFIFO not empty interrupt enable

Definition at line 198 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_CR1_TCIE USART_CR1_TCIE

Transmission complete interrupt enable

Definition at line 199 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE

Transmit data register empty and TX FIFO not full interrupt enable

Definition at line 200 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE

TX FIFO empty interrupt enable

Definition at line 203 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE

CTS interrupt enable

Definition at line 206 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_CR3_EIE USART_CR3_EIE

Error interrupt enable

Definition at line 205 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE

RX FIFO threshold interrupt enable

Definition at line 209 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE

TX FIFO threshold interrupt enable

Definition at line 208 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE

Wakeup from Stop mode interrupt enable

Definition at line 207 of file stm32wbxx_ll_lpuart.h.

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STM32WB55xx HAL User Manual: FIFO Threshold

Defines
FIFO Threshold
LPUART Exported Constants

Defines

#define | LL_LPUART_FIFOTHRESHOLD_1_8 0x00000000U
#define | LL_LPUART_FIFOTHRESHOLD_1_4 0x00000001U
#define | LL_LPUART_FIFOTHRESHOLD_1_2 0x00000002U
#define | LL_LPUART_FIFOTHRESHOLD_3_4 0x00000003U
#define | LL_LPUART_FIFOTHRESHOLD_7_8 0x00000004U
#define | LL_LPUART_FIFOTHRESHOLD_8_8 0x00000005U

Define Documentation

#define LL_LPUART_FIFOTHRESHOLD_1_2 0x00000002U

FIFO reaches 1/2 of its depth

Definition at line 219 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_FIFOTHRESHOLD_1_4 0x00000001U

FIFO reaches 1/4 of its depth

Definition at line 218 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_FIFOTHRESHOLD_1_8 0x00000000U

FIFO reaches 1/8 of its depth

Definition at line 217 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_FIFOTHRESHOLD_3_4 0x00000003U

FIFO reaches 3/4 of its depth

Definition at line 220 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_FIFOTHRESHOLD_7_8 0x00000004U

FIFO reaches 7/8 of its depth

Definition at line 221 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_FIFOTHRESHOLD_8_8 0x00000005U

FIFO becomes empty for TX and full for RX

Definition at line 222 of file stm32wbxx_ll_lpuart.h.

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STM32WB55xx HAL User Manual: Direction

Defines
Direction
LPUART Exported Constants

Defines

#define | LL_LPUART_DIRECTION_NONE 0x00000000U
#define | LL_LPUART_DIRECTION_RX USART_CR1_RE
#define | LL_LPUART_DIRECTION_TX USART_CR1_TE
#define | LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)

Define Documentation

#define LL_LPUART_DIRECTION_NONE 0x00000000U

Transmitter and Receiver are disabled

Definition at line 230 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_DIRECTION_RX USART_CR1_RE

Transmitter is disabled and Receiver is enabled

Definition at line 231 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_DIRECTION_TX USART_CR1_TE

Transmitter is enabled and Receiver is disabled

Definition at line 232 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)

Transmitter and Receiver are enabled

Definition at line 233 of file stm32wbxx_ll_lpuart.h.

Referenced by LL_LPUART_StructInit().

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STM32WB55xx HAL User Manual: Parity Control

Defines
Parity Control
LPUART Exported Constants

Defines

#define | LL_LPUART_PARITY_NONE 0x00000000U
#define | LL_LPUART_PARITY_EVEN USART_CR1_PCE
#define | LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Define Documentation

#define LL_LPUART_PARITY_EVEN USART_CR1_PCE

Parity control enabled and Even Parity is selected

Definition at line 242 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_PARITY_NONE 0x00000000U

Parity control disabled

Definition at line 241 of file stm32wbxx_ll_lpuart.h.

Referenced by LL_LPUART_StructInit().

#define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Parity control enabled and Odd Parity is selected

Definition at line 243 of file stm32wbxx_ll_lpuart.h.

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STM32WB55xx HAL User Manual: Wakeup

Defines
Wakeup
LPUART Exported Constants

Defines

#define | LL_LPUART_WAKEUP_IDLELINE 0x00000000U
#define | LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE

Define Documentation

#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE

LPUART wake up from Mute mode on Address Mark

Definition at line 252 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_WAKEUP_IDLELINE 0x00000000U

LPUART wake up from Mute mode on Idle Line

Definition at line 251 of file stm32wbxx_ll_lpuart.h.

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STM32WB55xx HAL User Manual: Datawidth

Defines
Datawidth
LPUART Exported Constants

Defines

#define | LL_LPUART_DATAWIDTH_7B USART_CR1_M1
#define | LL_LPUART_DATAWIDTH_8B 0x00000000U
#define | LL_LPUART_DATAWIDTH_9B USART_CR1_M0

Define Documentation

#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1

7 bits word length : Start bit, 7 data bits, n stop bits

Definition at line 260 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_DATAWIDTH_8B 0x00000000U

8 bits word length : Start bit, 8 data bits, n stop bits

Definition at line 261 of file stm32wbxx_ll_lpuart.h.

Referenced by LL_LPUART_StructInit().

#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0

9 bits word length : Start bit, 9 data bits, n stop bits

Definition at line 262 of file stm32wbxx_ll_lpuart.h.

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STM32WB55xx HAL User Manual: Clock Source Prescaler

Defines
Clock Source Prescaler
LPUART Exported Constants

Defines

#define | LL_LPUART_PRESCALER_DIV1 0x00000000U
#define | LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0)
#define | LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1)
#define | LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)
#define | LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2)
#define | LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0)
#define | LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1)
#define | LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)
#define | LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3)
#define | LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0)
#define | LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1)
#define | LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)

Define Documentation

#define LL_LPUART_PRESCALER_DIV1 0x00000000U

Input clock not devided

Definition at line 270 of file stm32wbxx_ll_lpuart.h.

Referenced by LL_LPUART_StructInit().

#define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0)

Input clock devided by 10

Definition at line 275 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1)

Input clock devided by 12

Definition at line 276 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1)

Input clock devided by 128

Definition at line 280 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)

Input clock devided by 16

Definition at line 277 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0)

Input clock devided by 2

Definition at line 271 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)

Input clock devided by 256

Definition at line 281 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3)

Input clock devided by 32

Definition at line 278 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1)

Input clock devided by 4

Definition at line 272 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)

Input clock devided by 6

Definition at line 273 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0)

Input clock devided by 64

Definition at line 279 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2)

Input clock devided by 8

Definition at line 274 of file stm32wbxx_ll_lpuart.h.

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STM32WB55xx HAL User Manual: Stop Bits

Defines
Stop Bits
LPUART Exported Constants

Defines

#define | LL_LPUART_STOPBITS_1 0x00000000U
#define | LL_LPUART_STOPBITS_2 USART_CR2_STOP_1

Define Documentation

#define LL_LPUART_STOPBITS_1 0x00000000U

1 stop bit

Definition at line 289 of file stm32wbxx_ll_lpuart.h.

Referenced by LL_LPUART_StructInit().

#define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1

2 stop bits

Definition at line 290 of file stm32wbxx_ll_lpuart.h.

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STM32WB55xx HAL User Manual: TX RX Pins Swap

Defines
TX RX Pins Swap
LPUART Exported Constants

Defines

#define | LL_LPUART_TXRX_STANDARD 0x00000000U
#define | LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP)

Define Documentation

#define LL_LPUART_TXRX_STANDARD 0x00000000U

TX/RX pins are used as defined in standard pinout

Definition at line 298 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP)

TX and RX pins functions are swapped.

Definition at line 299 of file stm32wbxx_ll_lpuart.h.

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STM32WB55xx HAL User Manual: RX Pin Active Level Inversion

Defines
RX Pin Active Level Inversion
LPUART Exported Constants

Defines

#define | LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U
#define | LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV)

Define Documentation

#define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV)

RX pin signal values are inverted.

Definition at line 308 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U

RX pin signal works using the standard logic levels

Definition at line 307 of file stm32wbxx_ll_lpuart.h.

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STM32WB55xx HAL User Manual: TX Pin Active Level Inversion

Defines
TX Pin Active Level Inversion
LPUART Exported Constants

Defines

#define | LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U
#define | LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV)

Define Documentation

#define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV)

TX pin signal values are inverted.

Definition at line 317 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U

TX pin signal works using the standard logic levels

Definition at line 316 of file stm32wbxx_ll_lpuart.h.

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STM32WB55xx HAL User Manual: Binary Data Inversion

Defines
Binary Data Inversion
LPUART Exported Constants

Defines

#define | LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U
#define | LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV

Define Documentation

#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV

Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted.

Definition at line 326 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U

Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)

Definition at line 325 of file stm32wbxx_ll_lpuart.h.

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STM32WB55xx HAL User Manual: Bit Order

Defines
Bit Order
LPUART Exported Constants

Defines

#define | LL_LPUART_BITORDER_LSBFIRST 0x00000000U
#define | LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST

Define Documentation

#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U

data is transmitted/received with data bit 0 first, following the start bit

Definition at line 334 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST

data is transmitted/received with the MSB first, following the start bit

Definition at line 335 of file stm32wbxx_ll_lpuart.h.

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STM32WB55xx HAL User Manual: Address Length Detection

Defines
Address Length Detection
LPUART Exported Constants

Defines

#define | LL_LPUART_ADDRESS_DETECT_4B 0x00000000U
#define | LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7

Define Documentation

#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U

4-bit address detection method selected

Definition at line 343 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7

7-bit address detection (in 8-bit data mode) method selected

Definition at line 344 of file stm32wbxx_ll_lpuart.h.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Hardware Control

Defines
Hardware Control
LPUART Exported Constants

Defines

#define | LL_LPUART_HWCONTROL_NONE 0x00000000U
#define | LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE
#define | LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE
#define | LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)

Define Documentation

#define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE

CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0)

Definition at line 354 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_HWCONTROL_NONE 0x00000000U

CTS and RTS hardware flow control disabled

Definition at line 352 of file stm32wbxx_ll_lpuart.h.

Referenced by LL_LPUART_StructInit().

#define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE

RTS output enabled, data is only requested when there is space in the receive buffer

Definition at line 353 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)

CTS and RTS hardware flow control enabled

Definition at line 355 of file stm32wbxx_ll_lpuart.h.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Wakeup Activation

Defines
Wakeup Activation
LPUART Exported Constants

Defines

#define | LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U
#define | LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1
#define | LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)

Define Documentation

#define LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U

Wake up active on address match

Definition at line 363 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)

Wake up active on RXNE

Definition at line 365 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1

Wake up active on Start bit detection

Definition at line 364 of file stm32wbxx_ll_lpuart.h.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Driver Enable Polarity

Defines
Driver Enable Polarity
LPUART Exported Constants

Defines

#define | LL_LPUART_DE_POLARITY_HIGH 0x00000000U
#define | LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP

Define Documentation

#define LL_LPUART_DE_POLARITY_HIGH 0x00000000U

DE signal is active high

Definition at line 373 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP

DE signal is active low

Definition at line 374 of file stm32wbxx_ll_lpuart.h.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DMA Register Data

Defines
DMA Register Data
LPUART Exported Constants

Defines

#define | LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U
#define | LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U

Define Documentation

#define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U

Get address of data register used for reception

Definition at line 383 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U

Get address of data register used for transmission

Definition at line 382 of file stm32wbxx_ll_lpuart.h.

Referenced by LL_LPUART_DMA_GetRegAddr().

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
LPUART Exported Macros

Defines

#define | LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in LPUART register.
#define | LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in LPUART register.

Define Documentation

#define LL_LPUART_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in LPUART register.

Parameters:
__INSTANCE__ | LPUART Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 416 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in LPUART register.

Parameters:
__INSTANCE__ | LPUART Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 408 of file stm32wbxx_ll_lpuart.h.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Helper Macros

Defines
Helper Macros
LPUART Exported Macros

Defines

#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__)
Compute LPUARTDIV value according to Peripheral Clock and expected Baud Rate (20-bit value of LPUARTDIV is returned)

Define Documentation

#define __LL_LPUART_DIV | ( | __PERIPHCLK__,
 |  | __PRESCALER__,
 |  | __BAUDRATE__
 | ) |
Value:
(uint32_t)((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)])) * LPUART_LPUARTDIV_FREQ_MUL)\
                                                                                + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)

Compute LPUARTDIV value according to Peripheral Clock and expected Baud Rate (20-bit value of LPUARTDIV is returned)

Parameters:
__PERIPHCLK__ | Peripheral Clock frequency used for LPUART Instance
__PRESCALER__ This parameter can be one of the following values:
  • LL_LPUART_PRESCALER_DIV1
  • LL_LPUART_PRESCALER_DIV2
  • LL_LPUART_PRESCALER_DIV4
  • LL_LPUART_PRESCALER_DIV6
  • LL_LPUART_PRESCALER_DIV8
  • LL_LPUART_PRESCALER_DIV10
  • LL_LPUART_PRESCALER_DIV12
  • LL_LPUART_PRESCALER_DIV16
  • LL_LPUART_PRESCALER_DIV32
  • LL_LPUART_PRESCALER_DIV64
  • LL_LPUART_PRESCALER_DIV128
  • LL_LPUART_PRESCALER_DIV256
__BAUDRATE__ | Baud Rate value to achieve
Return values:
LPUARTDIV value to be used for BRR register filling

Definition at line 445 of file stm32wbxx_ll_lpuart.h.

Referenced by LL_LPUART_SetBaudRate().

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Configuration functions

Functions
Configuration functions
LPUART Exported Functions

Functions

__STATIC_INLINE void | LL_LPUART_Enable (USART_TypeDef *LPUARTx)
LPUART Enable.
__STATIC_INLINE void | LL_LPUART_Disable (USART_TypeDef *LPUARTx)
LPUART Disable.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabled (USART_TypeDef *LPUARTx)
Indicate if LPUART is enabled.
__STATIC_INLINE void | LL_LPUART_EnableFIFO (USART_TypeDef *LPUARTx)
FIFO Mode Enable.
__STATIC_INLINE void | LL_LPUART_DisableFIFO (USART_TypeDef *LPUARTx)
FIFO Mode Disable.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledFIFO (USART_TypeDef *LPUARTx)
Indicate if FIFO Mode is enabled.
__STATIC_INLINE void | LL_LPUART_SetTXFIFOThreshold (USART_TypeDef *LPUARTx, uint32_t Threshold)
Configure TX FIFO Threshold.
__STATIC_INLINE uint32_t | LL_LPUART_GetTXFIFOThreshold (USART_TypeDef *LPUARTx)
Return TX FIFO Threshold Configuration.
__STATIC_INLINE void | LL_LPUART_SetRXFIFOThreshold (USART_TypeDef *LPUARTx, uint32_t Threshold)
Configure RX FIFO Threshold.
__STATIC_INLINE uint32_t | LL_LPUART_GetRXFIFOThreshold (USART_TypeDef *LPUARTx)
Return RX FIFO Threshold Configuration.
__STATIC_INLINE void | LL_LPUART_ConfigFIFOsThreshold (USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)
Configure TX and RX FIFOs Threshold.
__STATIC_INLINE void | LL_LPUART_EnableInStopMode (USART_TypeDef *LPUARTx)
LPUART enabled in STOP Mode.
__STATIC_INLINE void | LL_LPUART_DisableInStopMode (USART_TypeDef *LPUARTx)
LPUART disabled in STOP Mode.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledInStopMode (USART_TypeDef *LPUARTx)
Indicate if LPUART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
__STATIC_INLINE void | LL_LPUART_EnableDirectionRx (USART_TypeDef *LPUARTx)
Receiver Enable (Receiver is enabled and begins searching for a start bit)
__STATIC_INLINE void | LL_LPUART_DisableDirectionRx (USART_TypeDef *LPUARTx)
Receiver Disable.
__STATIC_INLINE void | LL_LPUART_EnableDirectionTx (USART_TypeDef *LPUARTx)
Transmitter Enable.
__STATIC_INLINE void | LL_LPUART_DisableDirectionTx (USART_TypeDef *LPUARTx)
Transmitter Disable.
__STATIC_INLINE void | LL_LPUART_SetTransferDirection (USART_TypeDef *LPUARTx, uint32_t TransferDirection)
Configure simultaneously enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE uint32_t | LL_LPUART_GetTransferDirection (USART_TypeDef *LPUARTx)
Return enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE void | LL_LPUART_SetParity (USART_TypeDef *LPUARTx, uint32_t Parity)
Configure Parity (enabled/disabled and parity mode if enabled)
__STATIC_INLINE uint32_t | LL_LPUART_GetParity (USART_TypeDef *LPUARTx)
Return Parity configuration (enabled/disabled and parity mode if enabled)
__STATIC_INLINE void | LL_LPUART_SetWakeUpMethod (USART_TypeDef *LPUARTx, uint32_t Method)
Set Receiver Wake Up method from Mute mode.
__STATIC_INLINE uint32_t | LL_LPUART_GetWakeUpMethod (USART_TypeDef *LPUARTx)
Return Receiver Wake Up method from Mute mode.
__STATIC_INLINE void | LL_LPUART_SetDataWidth (USART_TypeDef *LPUARTx, uint32_t DataWidth)
Set Word length (nb of data bits, excluding start and stop bits)
__STATIC_INLINE uint32_t | LL_LPUART_GetDataWidth (USART_TypeDef *LPUARTx)
Return Word length (i.e.
__STATIC_INLINE void | LL_LPUART_EnableMuteMode (USART_TypeDef *LPUARTx)
Allow switch between Mute Mode and Active mode.
__STATIC_INLINE void | LL_LPUART_DisableMuteMode (USART_TypeDef *LPUARTx)
Prevent Mute Mode use.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledMuteMode (USART_TypeDef *LPUARTx)
Indicate if switch between Mute Mode and Active mode is allowed.
__STATIC_INLINE void | LL_LPUART_SetPrescaler (USART_TypeDef *LPUARTx, uint32_t PrescalerValue)
Configure Clock source prescaler for baudrate generator and oversampling.
__STATIC_INLINE uint32_t | LL_LPUART_GetPrescaler (USART_TypeDef *LPUARTx)
Retrieve the Clock source prescaler for baudrate generator and oversampling.
__STATIC_INLINE void | LL_LPUART_SetStopBitsLength (USART_TypeDef *LPUARTx, uint32_t StopBits)
Set the length of the stop bits.
__STATIC_INLINE uint32_t | LL_LPUART_GetStopBitsLength (USART_TypeDef *LPUARTx)
Retrieve the length of the stop bits.
__STATIC_INLINE void | LL_LPUART_ConfigCharacter (USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity, uint32_t StopBits)
Configure Character frame format (Datawidth, Parity control, Stop Bits)
__STATIC_INLINE void | LL_LPUART_SetTXRXSwap (USART_TypeDef *LPUARTx, uint32_t SwapConfig)
Configure TX/RX pins swapping setting.
__STATIC_INLINE uint32_t | LL_LPUART_GetTXRXSwap (USART_TypeDef *LPUARTx)
Retrieve TX/RX pins swapping configuration.
__STATIC_INLINE void | LL_LPUART_SetRXPinLevel (USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
Configure RX pin active level logic.
__STATIC_INLINE uint32_t | LL_LPUART_GetRXPinLevel (USART_TypeDef *LPUARTx)
Retrieve RX pin active level logic configuration.
__STATIC_INLINE void | LL_LPUART_SetTXPinLevel (USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
Configure TX pin active level logic.
__STATIC_INLINE uint32_t | LL_LPUART_GetTXPinLevel (USART_TypeDef *LPUARTx)
Retrieve TX pin active level logic configuration.
__STATIC_INLINE void | LL_LPUART_SetBinaryDataLogic (USART_TypeDef *LPUARTx, uint32_t DataLogic)
Configure Binary data logic.
__STATIC_INLINE uint32_t | LL_LPUART_GetBinaryDataLogic (USART_TypeDef *LPUARTx)
Retrieve Binary data configuration.
__STATIC_INLINE void | LL_LPUART_SetTransferBitOrder (USART_TypeDef *LPUARTx, uint32_t BitOrder)
Configure transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE uint32_t | LL_LPUART_GetTransferBitOrder (USART_TypeDef *LPUARTx)
Return transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE void | LL_LPUART_ConfigNodeAddress (USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
Set Address of the LPUART node.
__STATIC_INLINE uint32_t | LL_LPUART_GetNodeAddress (USART_TypeDef *LPUARTx)
Return 8 bit Address of the LPUART node as set in ADD field of CR2.
__STATIC_INLINE uint32_t | LL_LPUART_GetNodeAddressLen (USART_TypeDef *LPUARTx)
Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
__STATIC_INLINE void | LL_LPUART_EnableRTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Enable RTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_DisableRTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Disable RTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_EnableCTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Enable CTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_DisableCTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Disable CTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_SetHWFlowCtrl (USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
Configure HW Flow Control mode (both CTS and RTS)
__STATIC_INLINE uint32_t | LL_LPUART_GetHWFlowCtrl (USART_TypeDef *LPUARTx)
Return HW Flow Control configuration (both CTS and RTS)
__STATIC_INLINE void | LL_LPUART_EnableOverrunDetect (USART_TypeDef *LPUARTx)
Enable Overrun detection.
__STATIC_INLINE void | LL_LPUART_DisableOverrunDetect (USART_TypeDef *LPUARTx)
Disable Overrun detection.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledOverrunDetect (USART_TypeDef *LPUARTx)
Indicate if Overrun detection is enabled.
__STATIC_INLINE void | LL_LPUART_SetWKUPType (USART_TypeDef *LPUARTx, uint32_t Type)
Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE uint32_t | LL_LPUART_GetWKUPType (USART_TypeDef *LPUARTx)
Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE void | LL_LPUART_SetBaudRate (USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t BaudRate)
Configure LPUART BRR register for achieving expected Baud Rate value.
__STATIC_INLINE uint32_t | LL_LPUART_GetBaudRate (USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue)
Return current Baud Rate value, according to LPUARTDIV present in BRR register (full BRR content), and to used Peripheral Clock values.

Function Documentation

__STATIC_INLINE void LL_LPUART_ConfigCharacter | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | DataWidth,
 |  | uint32_t | Parity,
 |  | uint32_t | StopBits
 | ) |  |

Configure Character frame format (Datawidth, Parity control, Stop Bits)

Note:
Call of this function is equivalent to following function call sequence :
  • Data Width configuration using LL_LPUART_SetDataWidth() function
  • Parity Control and mode configuration using LL_LPUART_SetParity() function
  • Stop bits configuration using LL_LPUART_SetStopBitsLength() function
Reference Manual to LL API cross reference:
CR1 PS LL_LPUART_ConfigCharacter
CR1 PCE LL_LPUART_ConfigCharacter
CR1 M LL_LPUART_ConfigCharacter
CR2 STOP LL_LPUART_ConfigCharacter
Parameters:
LPUARTx LPUART Instance
DataWidth This parameter can be one of the following values:
  • LL_LPUART_DATAWIDTH_7B
  • LL_LPUART_DATAWIDTH_8B
  • LL_LPUART_DATAWIDTH_9B
Parity This parameter can be one of the following values:
  • LL_LPUART_PARITY_NONE
  • LL_LPUART_PARITY_EVEN
  • LL_LPUART_PARITY_ODD
StopBits This parameter can be one of the following values:
  • LL_LPUART_STOPBITS_1
  • LL_LPUART_STOPBITS_2
Return values:
None

Definition at line 971 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | TXThreshold,
 |  | uint32_t | RXThreshold
 | ) |  |

Configure TX and RX FIFOs Threshold.

Reference Manual to LL API cross reference:
CR3 TXFTCFG LL_LPUART_ConfigFIFOsThreshold
CR3 RXFTCFG LL_LPUART_ConfigFIFOsThreshold
Parameters:
LPUARTx LPUART Instance
TXThreshold This parameter can be one of the following values:
  • LL_LPUART_FIFOTHRESHOLD_1_8
  • LL_LPUART_FIFOTHRESHOLD_1_4
  • LL_LPUART_FIFOTHRESHOLD_1_2
  • LL_LPUART_FIFOTHRESHOLD_3_4
  • LL_LPUART_FIFOTHRESHOLD_7_8
  • LL_LPUART_FIFOTHRESHOLD_8_8
RXThreshold This parameter can be one of the following values:
  • LL_LPUART_FIFOTHRESHOLD_1_8
  • LL_LPUART_FIFOTHRESHOLD_1_4
  • LL_LPUART_FIFOTHRESHOLD_1_2
  • LL_LPUART_FIFOTHRESHOLD_3_4
  • LL_LPUART_FIFOTHRESHOLD_7_8
  • LL_LPUART_FIFOTHRESHOLD_8_8
Return values:
None

Definition at line 630 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ConfigNodeAddress | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | AddressLen,
 |  | uint32_t | NodeAddress
 | ) |  |

Set Address of the LPUART node.

Note:
This is used in multiprocessor communication during Mute mode or Stop mode, for wake up with address mark detection.
4bits address node is used when 4-bit Address Detection is selected in ADDM7. (b7-b4 should be set to 0) 8bits address node is used when 7-bit Address Detection is selected in ADDM7. (This is used in multiprocessor communication during Mute mode or Stop mode, for wake up with 7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. It may also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match)
Reference Manual to LL API cross reference:
CR2 ADD LL_LPUART_ConfigNodeAddress
CR2 ADDM7 LL_LPUART_ConfigNodeAddress
Parameters:
LPUARTx | LPUART Instance
AddressLen This parameter can be one of the following values:
  • LL_LPUART_ADDRESS_DETECT_4B
  • LL_LPUART_ADDRESS_DETECT_7B
NodeAddress | 4 or 7 bit Address of the LPUART node.
Return values:
None

Definition at line 1143 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_Disable ( USART_TypeDef * LPUARTx )

LPUART Disable.

Note:
When LPUART is disabled, LPUART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the LPUART is kept, but all the status flags, in the LPUARTx_ISR are set to their default values.
In order to go into low-power mode without generating errors on the line, the TE bit must be reset before and the software must wait for the TC bit in the LPUART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit.
Reference Manual to LL API cross reference:
CR1 UE LL_LPUART_Disable
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 490 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl ( USART_TypeDef * LPUARTx )

Disable CTS HW Flow Control.

Reference Manual to LL API cross reference:
CR3 CTSE LL_LPUART_DisableCTSHWFlowCtrl
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1216 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableDirectionRx ( USART_TypeDef * LPUARTx )

Receiver Disable.

Reference Manual to LL API cross reference:
CR1 RE LL_LPUART_DisableDirectionRx
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 689 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableDirectionTx ( USART_TypeDef * LPUARTx )

Transmitter Disable.

Reference Manual to LL API cross reference:
CR1 TE LL_LPUART_DisableDirectionTx
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 711 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableFIFO ( USART_TypeDef * LPUARTx )

FIFO Mode Disable.

Reference Manual to LL API cross reference:
CR1 FIFOEN LL_LPUART_DisableFIFO
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 523 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableInStopMode ( USART_TypeDef * LPUARTx )

LPUART disabled in STOP Mode.

Note:
When this function is disabled, LPUART is not able to wake up the MCU from Stop mode
Reference Manual to LL API cross reference:
CR1 UESM LL_LPUART_DisableInStopMode
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 655 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableMuteMode ( USART_TypeDef * LPUARTx )

Prevent Mute Mode use.

Set Receiver in active mode permanently.

Reference Manual to LL API cross reference:
CR1 MME LL_LPUART_DisableMuteMode
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 857 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableOverrunDetect ( USART_TypeDef * LPUARTx )

Disable Overrun detection.

Reference Manual to LL API cross reference:
CR3 OVRDIS LL_LPUART_DisableOverrunDetect
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1271 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl ( USART_TypeDef * LPUARTx )

Disable RTS HW Flow Control.

Reference Manual to LL API cross reference:
CR3 RTSE LL_LPUART_DisableRTSHWFlowCtrl
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1194 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_Enable ( USART_TypeDef * LPUARTx )

LPUART Enable.

Reference Manual to LL API cross reference:
CR1 UE LL_LPUART_Enable
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 471 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl ( USART_TypeDef * LPUARTx )

Enable CTS HW Flow Control.

Reference Manual to LL API cross reference:
CR3 CTSE LL_LPUART_EnableCTSHWFlowCtrl
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1205 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableDirectionRx ( USART_TypeDef * LPUARTx )

Receiver Enable (Receiver is enabled and begins searching for a start bit)

Reference Manual to LL API cross reference:
CR1 RE LL_LPUART_EnableDirectionRx
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 678 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableDirectionTx ( USART_TypeDef * LPUARTx )

Transmitter Enable.

Reference Manual to LL API cross reference:
CR1 TE LL_LPUART_EnableDirectionTx
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 700 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableFIFO ( USART_TypeDef * LPUARTx )

FIFO Mode Enable.

Reference Manual to LL API cross reference:
CR1 FIFOEN LL_LPUART_EnableFIFO
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 512 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableInStopMode ( USART_TypeDef * LPUARTx )

LPUART enabled in STOP Mode.

Note:
When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that LPUART clock selection is HSI or LSE in RCC.
Reference Manual to LL API cross reference:
CR1 UESM LL_LPUART_EnableInStopMode
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 643 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableMuteMode ( USART_TypeDef * LPUARTx )

Allow switch between Mute Mode and Active mode.

Reference Manual to LL API cross reference:
CR1 MME LL_LPUART_EnableMuteMode
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 846 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableOverrunDetect ( USART_TypeDef * LPUARTx )

Enable Overrun detection.

Reference Manual to LL API cross reference:
CR3 OVRDIS LL_LPUART_EnableOverrunDetect
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1260 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl ( USART_TypeDef * LPUARTx )

Enable RTS HW Flow Control.

Reference Manual to LL API cross reference:
CR3 RTSE LL_LPUART_EnableRTSHWFlowCtrl
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1183 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | PeriphClk,
 |  | uint32_t | PrescalerValue
 | ) |  |

Return current Baud Rate value, according to LPUARTDIV present in BRR register (full BRR content), and to used Peripheral Clock values.

Note:
In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
Reference Manual to LL API cross reference:
BRR BRR LL_LPUART_GetBaudRate
Parameters:
LPUARTx | LPUART Instance
PeriphClk | Peripheral Clock
PrescalerValue This parameter can be one of the following values:
  • LL_LPUART_PRESCALER_DIV1
  • LL_LPUART_PRESCALER_DIV2
  • LL_LPUART_PRESCALER_DIV4
  • LL_LPUART_PRESCALER_DIV6
  • LL_LPUART_PRESCALER_DIV8
  • LL_LPUART_PRESCALER_DIV10
  • LL_LPUART_PRESCALER_DIV12
  • LL_LPUART_PRESCALER_DIV16
  • LL_LPUART_PRESCALER_DIV32
  • LL_LPUART_PRESCALER_DIV64
  • LL_LPUART_PRESCALER_DIV128
  • LL_LPUART_PRESCALER_DIV256
Return values:
Baud Rate

Definition at line 1373 of file stm32wbxx_ll_lpuart.h.

References LPUART_BRR_MASK, LPUART_BRR_MIN_VALUE, and LPUART_LPUARTDIV_FREQ_MUL.

__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic ( USART_TypeDef * LPUARTx )

Retrieve Binary data configuration.

Reference Manual to LL API cross reference:
CR2 DATAINV LL_LPUART_GetBinaryDataLogic
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_BINARY_LOGIC_POSITIVE
  • LL_LPUART_BINARY_LOGIC_NEGATIVE

Definition at line 1084 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth ( USART_TypeDef * LPUARTx )

Return Word length (i.e.

nb of data bits, excluding start and stop bits)

Reference Manual to LL API cross reference:
CR1 M LL_LPUART_GetDataWidth
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_DATAWIDTH_7B
  • LL_LPUART_DATAWIDTH_8B
  • LL_LPUART_DATAWIDTH_9B

Definition at line 835 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl ( USART_TypeDef * LPUARTx )

Return HW Flow Control configuration (both CTS and RTS)

Reference Manual to LL API cross reference:
CR3 RTSE LL_LPUART_GetHWFlowCtrl
CR3 CTSE LL_LPUART_GetHWFlowCtrl
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_HWCONTROL_NONE
  • LL_LPUART_HWCONTROL_RTS
  • LL_LPUART_HWCONTROL_CTS
  • LL_LPUART_HWCONTROL_RTS_CTS

Definition at line 1249 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress ( USART_TypeDef * LPUARTx )

Return 8 bit Address of the LPUART node as set in ADD field of CR2.

Note:
If 4-bit Address Detection is selected in ADDM7, only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) If 7-bit Address Detection is selected in ADDM7, only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
Reference Manual to LL API cross reference:
CR2 ADD LL_LPUART_GetNodeAddress
Parameters:
LPUARTx LPUART Instance
Return values:
Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)

Definition at line 1159 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen ( USART_TypeDef * LPUARTx )

Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)

Reference Manual to LL API cross reference:
CR2 ADDM7 LL_LPUART_GetNodeAddressLen
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_ADDRESS_DETECT_4B
  • LL_LPUART_ADDRESS_DETECT_7B

Definition at line 1172 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetParity ( USART_TypeDef * LPUARTx )

Return Parity configuration (enabled/disabled and parity mode if enabled)

Reference Manual to LL API cross reference:
CR1 PS LL_LPUART_GetParity
CR1 PCE LL_LPUART_GetParity
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_PARITY_NONE
  • LL_LPUART_PARITY_EVEN
  • LL_LPUART_PARITY_ODD

Definition at line 779 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler ( USART_TypeDef * LPUARTx )

Retrieve the Clock source prescaler for baudrate generator and oversampling.

Reference Manual to LL API cross reference:
PRESC PRESCALER LL_LPUART_GetPrescaler
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_PRESCALER_DIV1
  • LL_LPUART_PRESCALER_DIV2
  • LL_LPUART_PRESCALER_DIV4
  • LL_LPUART_PRESCALER_DIV6
  • LL_LPUART_PRESCALER_DIV8
  • LL_LPUART_PRESCALER_DIV10
  • LL_LPUART_PRESCALER_DIV12
  • LL_LPUART_PRESCALER_DIV16
  • LL_LPUART_PRESCALER_DIV32
  • LL_LPUART_PRESCALER_DIV64
  • LL_LPUART_PRESCALER_DIV128
  • LL_LPUART_PRESCALER_DIV256

Definition at line 915 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold ( USART_TypeDef * LPUARTx )

Return RX FIFO Threshold Configuration.

Reference Manual to LL API cross reference:
CR3 RXFTCFG LL_LPUART_GetRXFIFOThreshold
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_FIFOTHRESHOLD_1_8
  • LL_LPUART_FIFOTHRESHOLD_1_4
  • LL_LPUART_FIFOTHRESHOLD_1_2
  • LL_LPUART_FIFOTHRESHOLD_3_4
  • LL_LPUART_FIFOTHRESHOLD_7_8
  • LL_LPUART_FIFOTHRESHOLD_8_8

Definition at line 604 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel ( USART_TypeDef * LPUARTx )

Retrieve RX pin active level logic configuration.

Reference Manual to LL API cross reference:
CR2 RXINV LL_LPUART_GetRXPinLevel
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_RXPIN_LEVEL_STANDARD
  • LL_LPUART_RXPIN_LEVEL_INVERTED

Definition at line 1027 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength ( USART_TypeDef * LPUARTx )

Retrieve the length of the stop bits.

Reference Manual to LL API cross reference:
CR2 STOP LL_LPUART_GetStopBitsLength
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_STOPBITS_1
  • LL_LPUART_STOPBITS_2

Definition at line 942 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder ( USART_TypeDef * LPUARTx )

Return transfer bit order (either Less or Most Significant Bit First)

Note:
MSB First means data is transmitted/received with the MSB first, following the start bit. LSB First means data is transmitted/received with data bit 0 first, following the start bit.
Reference Manual to LL API cross reference:
CR2 MSBFIRST LL_LPUART_GetTransferBitOrder
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_BITORDER_LSBFIRST
  • LL_LPUART_BITORDER_MSBFIRST

Definition at line 1115 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection ( USART_TypeDef * LPUARTx )

Return enabled/disabled states of Transmitter and Receiver.

Reference Manual to LL API cross reference:
CR1 RE LL_LPUART_GetTransferDirection
CR1 TE LL_LPUART_GetTransferDirection
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_DIRECTION_NONE
  • LL_LPUART_DIRECTION_RX
  • LL_LPUART_DIRECTION_TX
  • LL_LPUART_DIRECTION_TX_RX

Definition at line 745 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold ( USART_TypeDef * LPUARTx )

Return TX FIFO Threshold Configuration.

Reference Manual to LL API cross reference:
CR3 TXFTCFG LL_LPUART_GetTXFIFOThreshold
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_FIFOTHRESHOLD_1_8
  • LL_LPUART_FIFOTHRESHOLD_1_4
  • LL_LPUART_FIFOTHRESHOLD_1_2
  • LL_LPUART_FIFOTHRESHOLD_3_4
  • LL_LPUART_FIFOTHRESHOLD_7_8
  • LL_LPUART_FIFOTHRESHOLD_8_8

Definition at line 569 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel ( USART_TypeDef * LPUARTx )

Retrieve TX pin active level logic configuration.

Reference Manual to LL API cross reference:
CR2 TXINV LL_LPUART_GetTXPinLevel
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_TXPIN_LEVEL_STANDARD
  • LL_LPUART_TXPIN_LEVEL_INVERTED

Definition at line 1054 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap ( USART_TypeDef * LPUARTx )

Retrieve TX/RX pins swapping configuration.

Reference Manual to LL API cross reference:
CR2 SWAP LL_LPUART_GetTXRXSwap
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_TXRX_STANDARD
  • LL_LPUART_TXRX_SWAPPED

Definition at line 1000 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod ( USART_TypeDef * LPUARTx )

Return Receiver Wake Up method from Mute mode.

Reference Manual to LL API cross reference:
CR1 WAKE LL_LPUART_GetWakeUpMethod
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_WAKEUP_IDLELINE
  • LL_LPUART_WAKEUP_ADDRESSMARK

Definition at line 806 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType ( USART_TypeDef * LPUARTx )

Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)

Reference Manual to LL API cross reference:
CR3 WUS LL_LPUART_GetWKUPType
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_WAKEUP_ON_ADDRESS
  • LL_LPUART_WAKEUP_ON_STARTBIT
  • LL_LPUART_WAKEUP_ON_RXNE

Definition at line 1311 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabled ( USART_TypeDef * LPUARTx )

Indicate if LPUART is enabled.

Reference Manual to LL API cross reference:
CR1 UE LL_LPUART_IsEnabled
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 501 of file stm32wbxx_ll_lpuart.h.

Referenced by LL_LPUART_Init().

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO ( USART_TypeDef * LPUARTx )

Indicate if FIFO Mode is enabled.

Reference Manual to LL API cross reference:
CR1 FIFOEN LL_LPUART_IsEnabledFIFO
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 534 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode ( USART_TypeDef * LPUARTx )

Indicate if LPUART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)

Reference Manual to LL API cross reference:
CR1 UESM LL_LPUART_IsEnabledInStopMode
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 667 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode ( USART_TypeDef * LPUARTx )

Indicate if switch between Mute Mode and Active mode is allowed.

Reference Manual to LL API cross reference:
CR1 MME LL_LPUART_IsEnabledMuteMode
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 868 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect ( USART_TypeDef * LPUARTx )

Indicate if Overrun detection is enabled.

Reference Manual to LL API cross reference:
CR3 OVRDIS LL_LPUART_IsEnabledOverrunDetect
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1282 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetBaudRate | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | PeriphClk,
 |  | uint32_t | PrescalerValue,
 |  | uint32_t | BaudRate
 | ) |  |

Configure LPUART BRR register for achieving expected Baud Rate value.

Note:
Compute and set LPUARTDIV value in BRR Register (full BRR content) according to used Peripheral Clock and expected Baud Rate values
Peripheral clock and Baud Rate values provided as function parameters should be valid (Baud rate value != 0).
Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit, a care should be taken when generating high baud rates using high PeriphClk values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].
Reference Manual to LL API cross reference:
BRR BRR LL_LPUART_SetBaudRate
Parameters:
LPUARTx | LPUART Instance
PeriphClk | Peripheral Clock
PrescalerValue This parameter can be one of the following values:
  • LL_LPUART_PRESCALER_DIV1
  • LL_LPUART_PRESCALER_DIV2
  • LL_LPUART_PRESCALER_DIV4
  • LL_LPUART_PRESCALER_DIV6
  • LL_LPUART_PRESCALER_DIV8
  • LL_LPUART_PRESCALER_DIV10
  • LL_LPUART_PRESCALER_DIV12
  • LL_LPUART_PRESCALER_DIV16
  • LL_LPUART_PRESCALER_DIV32
  • LL_LPUART_PRESCALER_DIV64
  • LL_LPUART_PRESCALER_DIV128
  • LL_LPUART_PRESCALER_DIV256
BaudRate | Baud Rate
Return values:
None

Definition at line 1345 of file stm32wbxx_ll_lpuart.h.

References __LL_LPUART_DIV.

Referenced by LL_LPUART_Init().

__STATIC_INLINE void LL_LPUART_SetBinaryDataLogic | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | DataLogic
 | ) |  |

Configure Binary data logic.

Note:
Allow to define how Logical data from the data register are send/received : either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
Reference Manual to LL API cross reference:
CR2 DATAINV LL_LPUART_SetBinaryDataLogic
Parameters:
LPUARTx LPUART Instance
DataLogic This parameter can be one of the following values:
  • LL_LPUART_BINARY_LOGIC_POSITIVE
  • LL_LPUART_BINARY_LOGIC_NEGATIVE
Return values:
None

Definition at line 1071 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetDataWidth | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | DataWidth
 | ) |  |

Set Word length (nb of data bits, excluding start and stop bits)

Reference Manual to LL API cross reference:
CR1 M LL_LPUART_SetDataWidth
Parameters:
LPUARTx LPUART Instance
DataWidth This parameter can be one of the following values:
  • LL_LPUART_DATAWIDTH_7B
  • LL_LPUART_DATAWIDTH_8B
  • LL_LPUART_DATAWIDTH_9B
Return values:
None

Definition at line 821 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetHWFlowCtrl | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | HardwareFlowControl
 | ) |  |

Configure HW Flow Control mode (both CTS and RTS)

Reference Manual to LL API cross reference:
CR3 RTSE LL_LPUART_SetHWFlowCtrl
CR3 CTSE LL_LPUART_SetHWFlowCtrl
Parameters:
LPUARTx LPUART Instance
HardwareFlowControl This parameter can be one of the following values:
  • LL_LPUART_HWCONTROL_NONE
  • LL_LPUART_HWCONTROL_RTS
  • LL_LPUART_HWCONTROL_CTS
  • LL_LPUART_HWCONTROL_RTS_CTS
Return values:
None

Definition at line 1233 of file stm32wbxx_ll_lpuart.h.

Referenced by LL_LPUART_Init().

__STATIC_INLINE void LL_LPUART_SetParity | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Parity
 | ) |  |

Configure Parity (enabled/disabled and parity mode if enabled)

Note:
This function selects if hardware parity control (generation and detection) is enabled or disabled. When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position (depending on data width) and parity is checked on the received data.
Reference Manual to LL API cross reference:
CR1 PS LL_LPUART_SetParity
CR1 PCE LL_LPUART_SetParity
Parameters:
LPUARTx LPUART Instance
Parity This parameter can be one of the following values:
  • LL_LPUART_PARITY_NONE
  • LL_LPUART_PARITY_EVEN
  • LL_LPUART_PARITY_ODD
Return values:
None

Definition at line 764 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetPrescaler | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | PrescalerValue
 | ) |  |

Configure Clock source prescaler for baudrate generator and oversampling.

Reference Manual to LL API cross reference:
PRESC PRESCALER LL_LPUART_SetPrescaler
Parameters:
LPUARTx LPUART Instance
PrescalerValue This parameter can be one of the following values:
  • LL_LPUART_PRESCALER_DIV1
  • LL_LPUART_PRESCALER_DIV2
  • LL_LPUART_PRESCALER_DIV4
  • LL_LPUART_PRESCALER_DIV6
  • LL_LPUART_PRESCALER_DIV8
  • LL_LPUART_PRESCALER_DIV10
  • LL_LPUART_PRESCALER_DIV12
  • LL_LPUART_PRESCALER_DIV16
  • LL_LPUART_PRESCALER_DIV32
  • LL_LPUART_PRESCALER_DIV64
  • LL_LPUART_PRESCALER_DIV128
  • LL_LPUART_PRESCALER_DIV256
Return values:
None

Definition at line 892 of file stm32wbxx_ll_lpuart.h.

Referenced by LL_LPUART_Init().

__STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Threshold
 | ) |  |

Configure RX FIFO Threshold.

Reference Manual to LL API cross reference:
CR3 RXFTCFG LL_LPUART_SetRXFIFOThreshold
Parameters:
LPUARTx LPUART Instance
Threshold This parameter can be one of the following values:
  • LL_LPUART_FIFOTHRESHOLD_1_8
  • LL_LPUART_FIFOTHRESHOLD_1_4
  • LL_LPUART_FIFOTHRESHOLD_1_2
  • LL_LPUART_FIFOTHRESHOLD_3_4
  • LL_LPUART_FIFOTHRESHOLD_7_8
  • LL_LPUART_FIFOTHRESHOLD_8_8
Return values:
None

Definition at line 587 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetRXPinLevel | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | PinInvMethod
 | ) |  |

Configure RX pin active level logic.

Reference Manual to LL API cross reference:
CR2 RXINV LL_LPUART_SetRXPinLevel
Parameters:
LPUARTx LPUART Instance
PinInvMethod This parameter can be one of the following values:
  • LL_LPUART_RXPIN_LEVEL_STANDARD
  • LL_LPUART_RXPIN_LEVEL_INVERTED
Return values:
None

Definition at line 1014 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetStopBitsLength | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | StopBits
 | ) |  |

Set the length of the stop bits.

Reference Manual to LL API cross reference:
CR2 STOP LL_LPUART_SetStopBitsLength
Parameters:
LPUARTx LPUART Instance
StopBits This parameter can be one of the following values:
  • LL_LPUART_STOPBITS_1
  • LL_LPUART_STOPBITS_2
Return values:
None

Definition at line 929 of file stm32wbxx_ll_lpuart.h.

Referenced by LL_LPUART_Init().

__STATIC_INLINE void LL_LPUART_SetTransferBitOrder | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | BitOrder
 | ) |  |

Configure transfer bit order (either Less or Most Significant Bit First)

Note:
MSB First means data is transmitted/received with the MSB first, following the start bit. LSB First means data is transmitted/received with data bit 0 first, following the start bit.
Reference Manual to LL API cross reference:
CR2 MSBFIRST LL_LPUART_SetTransferBitOrder
Parameters:
LPUARTx LPUART Instance
BitOrder This parameter can be one of the following values:
  • LL_LPUART_BITORDER_LSBFIRST
  • LL_LPUART_BITORDER_MSBFIRST
Return values:
None

Definition at line 1100 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetTransferDirection | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | TransferDirection
 | ) |  |

Configure simultaneously enabled/disabled states of Transmitter and Receiver.

Reference Manual to LL API cross reference:
CR1 RE LL_LPUART_SetTransferDirection
CR1 TE LL_LPUART_SetTransferDirection
Parameters:
LPUARTx LPUART Instance
TransferDirection This parameter can be one of the following values:
  • LL_LPUART_DIRECTION_NONE
  • LL_LPUART_DIRECTION_RX
  • LL_LPUART_DIRECTION_TX
  • LL_LPUART_DIRECTION_TX_RX
Return values:
None

Definition at line 729 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Threshold
 | ) |  |

Configure TX FIFO Threshold.

Reference Manual to LL API cross reference:
CR3 TXFTCFG LL_LPUART_SetTXFIFOThreshold
Parameters:
LPUARTx LPUART Instance
Threshold This parameter can be one of the following values:
  • LL_LPUART_FIFOTHRESHOLD_1_8
  • LL_LPUART_FIFOTHRESHOLD_1_4
  • LL_LPUART_FIFOTHRESHOLD_1_2
  • LL_LPUART_FIFOTHRESHOLD_3_4
  • LL_LPUART_FIFOTHRESHOLD_7_8
  • LL_LPUART_FIFOTHRESHOLD_8_8
Return values:
None

Definition at line 552 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetTXPinLevel | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | PinInvMethod
 | ) |  |

Configure TX pin active level logic.

Reference Manual to LL API cross reference:
CR2 TXINV LL_LPUART_SetTXPinLevel
Parameters:
LPUARTx LPUART Instance
PinInvMethod This parameter can be one of the following values:
  • LL_LPUART_TXPIN_LEVEL_STANDARD
  • LL_LPUART_TXPIN_LEVEL_INVERTED
Return values:
None

Definition at line 1041 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetTXRXSwap | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | SwapConfig
 | ) |  |

Configure TX/RX pins swapping setting.

Reference Manual to LL API cross reference:
CR2 SWAP LL_LPUART_SetTXRXSwap
Parameters:
LPUARTx LPUART Instance
SwapConfig This parameter can be one of the following values:
  • LL_LPUART_TXRX_STANDARD
  • LL_LPUART_TXRX_SWAPPED
Return values:
None

Definition at line 987 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetWakeUpMethod | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Method
 | ) |  |

Set Receiver Wake Up method from Mute mode.

Reference Manual to LL API cross reference:
CR1 WAKE LL_LPUART_SetWakeUpMethod
Parameters:
LPUARTx LPUART Instance
Method This parameter can be one of the following values:
  • LL_LPUART_WAKEUP_IDLELINE
  • LL_LPUART_WAKEUP_ADDRESSMARK
Return values:
None

Definition at line 793 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetWKUPType | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Type
 | ) |  |

Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)

Reference Manual to LL API cross reference:
CR3 WUS LL_LPUART_SetWKUPType
Parameters:
LPUARTx LPUART Instance
Type This parameter can be one of the following values:
  • LL_LPUART_WAKEUP_ON_ADDRESS
  • LL_LPUART_WAKEUP_ON_STARTBIT
  • LL_LPUART_WAKEUP_ON_RXNE
Return values:
None

Definition at line 1297 of file stm32wbxx_ll_lpuart.h.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Configuration functions related to Half Duplex feature

Functions
Configuration functions related to Half Duplex feature
LPUART Exported Functions

Functions

__STATIC_INLINE void | LL_LPUART_EnableHalfDuplex (USART_TypeDef *LPUARTx)
Enable Single Wire Half-Duplex mode.
__STATIC_INLINE void | LL_LPUART_DisableHalfDuplex (USART_TypeDef *LPUARTx)
Disable Single Wire Half-Duplex mode.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledHalfDuplex (USART_TypeDef *LPUARTx)
Indicate if Single Wire Half-Duplex mode is enabled.

Function Documentation

__STATIC_INLINE void LL_LPUART_DisableHalfDuplex ( USART_TypeDef * LPUARTx )

Disable Single Wire Half-Duplex mode.

Reference Manual to LL API cross reference:
CR3 HDSEL LL_LPUART_DisableHalfDuplex
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1418 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableHalfDuplex ( USART_TypeDef * LPUARTx )

Enable Single Wire Half-Duplex mode.

Reference Manual to LL API cross reference:
CR3 HDSEL LL_LPUART_EnableHalfDuplex
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1407 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex ( USART_TypeDef * LPUARTx )

Indicate if Single Wire Half-Duplex mode is enabled.

Reference Manual to LL API cross reference:
CR3 HDSEL LL_LPUART_IsEnabledHalfDuplex
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1429 of file stm32wbxx_ll_lpuart.h.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Configuration functions related to Driver Enable feature

Functions
Configuration functions related to Driver Enable feature
LPUART Exported Functions

Functions

__STATIC_INLINE void | LL_LPUART_SetDEDeassertionTime (USART_TypeDef *LPUARTx, uint32_t Time)
Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_LPUART_GetDEDeassertionTime (USART_TypeDef *LPUARTx)
Return DEDT (Driver Enable De-Assertion Time)
__STATIC_INLINE void | LL_LPUART_SetDEAssertionTime (USART_TypeDef *LPUARTx, uint32_t Time)
Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_LPUART_GetDEAssertionTime (USART_TypeDef *LPUARTx)
Return DEAT (Driver Enable Assertion Time)
__STATIC_INLINE void | LL_LPUART_EnableDEMode (USART_TypeDef *LPUARTx)
Enable Driver Enable (DE) Mode.
__STATIC_INLINE void | LL_LPUART_DisableDEMode (USART_TypeDef *LPUARTx)
Disable Driver Enable (DE) Mode.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDEMode (USART_TypeDef *LPUARTx)
Indicate if Driver Enable (DE) Mode is enabled.
__STATIC_INLINE void | LL_LPUART_SetDESignalPolarity (USART_TypeDef *LPUARTx, uint32_t Polarity)
Select Driver Enable Polarity.
__STATIC_INLINE uint32_t | LL_LPUART_GetDESignalPolarity (USART_TypeDef *LPUARTx)
Return Driver Enable Polarity.

Function Documentation

__STATIC_INLINE void LL_LPUART_DisableDEMode ( USART_TypeDef * LPUARTx )

Disable Driver Enable (DE) Mode.

Reference Manual to LL API cross reference:
CR3 DEM LL_LPUART_DisableDEMode
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1505 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableDEMode ( USART_TypeDef * LPUARTx )

Enable Driver Enable (DE) Mode.

Reference Manual to LL API cross reference:
CR3 DEM LL_LPUART_EnableDEMode
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1494 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime ( USART_TypeDef * LPUARTx )

Return DEAT (Driver Enable Assertion Time)

Reference Manual to LL API cross reference:
CR1 DEAT LL_LPUART_GetDEAssertionTime
Parameters:
LPUARTx LPUART Instance
Return values:
Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31

Definition at line 1483 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime ( USART_TypeDef * LPUARTx )

Return DEDT (Driver Enable De-Assertion Time)

Reference Manual to LL API cross reference:
CR1 DEDT LL_LPUART_GetDEDeassertionTime
Parameters:
LPUARTx LPUART Instance
Return values:
Time value expressed on 5 bits ([4:0] bits) : c

Definition at line 1460 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity ( USART_TypeDef * LPUARTx )

Return Driver Enable Polarity.

Reference Manual to LL API cross reference:
CR3 DEP LL_LPUART_GetDESignalPolarity
Parameters:
LPUARTx LPUART Instance
Return values:
Returned value can be one of the following values:
  • LL_LPUART_DE_POLARITY_HIGH
  • LL_LPUART_DE_POLARITY_LOW

Definition at line 1543 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode ( USART_TypeDef * LPUARTx )

Indicate if Driver Enable (DE) Mode is enabled.

Reference Manual to LL API cross reference:
CR3 DEM LL_LPUART_IsEnabledDEMode
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1516 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetDEAssertionTime | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Time
 | ) |  |

Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).

Reference Manual to LL API cross reference:
CR1 DEAT LL_LPUART_SetDEAssertionTime
Parameters:
LPUARTx | LPUART Instance
Time | Value between Min_Data=0 and Max_Data=31
Return values:
None

Definition at line 1472 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetDEDeassertionTime | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Time
 | ) |  |

Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).

Reference Manual to LL API cross reference:
CR1 DEDT LL_LPUART_SetDEDeassertionTime
Parameters:
LPUARTx | LPUART Instance
Time | Value between Min_Data=0 and Max_Data=31
Return values:
None

Definition at line 1449 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_SetDESignalPolarity | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Polarity
 | ) |  |

Select Driver Enable Polarity.

Reference Manual to LL API cross reference:
CR3 DEP LL_LPUART_SetDESignalPolarity
Parameters:
LPUARTx LPUART Instance
Polarity This parameter can be one of the following values:
  • LL_LPUART_DE_POLARITY_HIGH
  • LL_LPUART_DE_POLARITY_LOW
Return values:
None

Definition at line 1530 of file stm32wbxx_ll_lpuart.h.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FLAG_Management

Defines | Functions
FLAG_Management
LPUART Exported Functions

Defines

#define | LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE
#define | LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF

Functions

__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_PE (USART_TypeDef *LPUARTx)
Check if the LPUART Parity Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_FE (USART_TypeDef *LPUARTx)
Check if the LPUART Framing Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_NE (USART_TypeDef *LPUARTx)
Check if the LPUART Noise error detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_ORE (USART_TypeDef *LPUARTx)
Check if the LPUART OverRun Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_IDLE (USART_TypeDef *LPUARTx)
Check if the LPUART IDLE line detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_RXNE_RXFNE (USART_TypeDef *LPUARTx)
Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TC (USART_TypeDef *LPUARTx)
Check if the LPUART Transmission Complete Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TXE_TXFNF (USART_TypeDef *LPUARTx)
Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_nCTS (USART_TypeDef *LPUARTx)
Check if the LPUART CTS interrupt Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_CTS (USART_TypeDef *LPUARTx)
Check if the LPUART CTS Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_BUSY (USART_TypeDef *LPUARTx)
Check if the LPUART Busy Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_CM (USART_TypeDef *LPUARTx)
Check if the LPUART Character Match Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_SBK (USART_TypeDef *LPUARTx)
Check if the LPUART Send Break Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_RWU (USART_TypeDef *LPUARTx)
Check if the LPUART Receive Wake Up from mute mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_WKUP (USART_TypeDef *LPUARTx)
Check if the LPUART Wake Up from stop mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TEACK (USART_TypeDef *LPUARTx)
Check if the LPUART Transmit Enable Acknowledge Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_REACK (USART_TypeDef *LPUARTx)
Check if the LPUART Receive Enable Acknowledge Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TXFE (USART_TypeDef *LPUARTx)
Check if the LPUART TX FIFO Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_RXFF (USART_TypeDef *LPUARTx)
Check if the LPUART RX FIFO Full Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TXFT (USART_TypeDef *LPUARTx)
Check if the LPUART TX FIFO Threshold Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_RXFT (USART_TypeDef *LPUARTx)
Check if the LPUART RX FIFO Threshold Flag is set or not.
__STATIC_INLINE void | LL_LPUART_ClearFlag_PE (USART_TypeDef *LPUARTx)
Clear Parity Error Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_FE (USART_TypeDef *LPUARTx)
Clear Framing Error Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_NE (USART_TypeDef *LPUARTx)
Clear Noise detected Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_ORE (USART_TypeDef *LPUARTx)
Clear OverRun Error Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_IDLE (USART_TypeDef *LPUARTx)
Clear IDLE line detected Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_TXFE (USART_TypeDef *LPUARTx)
Clear TX FIFO Empty Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_TC (USART_TypeDef *LPUARTx)
Clear Transmission Complete Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_nCTS (USART_TypeDef *LPUARTx)
Clear CTS Interrupt Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_CM (USART_TypeDef *LPUARTx)
Clear Character Match Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_WKUP (USART_TypeDef *LPUARTx)
Clear Wake Up from stop mode Flag.

Define Documentation

#define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE

Definition at line 1612 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF

Definition at line 1637 of file stm32wbxx_ll_lpuart.h.

Function Documentation

__STATIC_INLINE void LL_LPUART_ClearFlag_CM ( USART_TypeDef * LPUARTx )

Clear Character Match Flag.

Reference Manual to LL API cross reference:
ICR CMCF LL_LPUART_ClearFlag_CM
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1887 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_FE ( USART_TypeDef * LPUARTx )

Clear Framing Error Flag.

Reference Manual to LL API cross reference:
ICR FECF LL_LPUART_ClearFlag_FE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1810 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_IDLE ( USART_TypeDef * LPUARTx )

Clear IDLE line detected Flag.

Reference Manual to LL API cross reference:
ICR IDLECF LL_LPUART_ClearFlag_IDLE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1843 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_nCTS ( USART_TypeDef * LPUARTx )

Clear CTS Interrupt Flag.

Reference Manual to LL API cross reference:
ICR CTSCF LL_LPUART_ClearFlag_nCTS
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1876 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_NE ( USART_TypeDef * LPUARTx )

Clear Noise detected Flag.

Reference Manual to LL API cross reference:
ICR NECF LL_LPUART_ClearFlag_NE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1821 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_ORE ( USART_TypeDef * LPUARTx )

Clear OverRun Error Flag.

Reference Manual to LL API cross reference:
ICR ORECF LL_LPUART_ClearFlag_ORE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1832 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_PE ( USART_TypeDef * LPUARTx )

Clear Parity Error Flag.

Reference Manual to LL API cross reference:
ICR PECF LL_LPUART_ClearFlag_PE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1799 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_TC ( USART_TypeDef * LPUARTx )

Clear Transmission Complete Flag.

Reference Manual to LL API cross reference:
ICR TCCF LL_LPUART_ClearFlag_TC
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1865 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_TXFE ( USART_TypeDef * LPUARTx )

Clear TX FIFO Empty Flag.

Reference Manual to LL API cross reference:
ICR TXFECF LL_LPUART_ClearFlag_TXFE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1854 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_ClearFlag_WKUP ( USART_TypeDef * LPUARTx )

Clear Wake Up from stop mode Flag.

Reference Manual to LL API cross reference:
ICR WUCF LL_LPUART_ClearFlag_WKUP
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1898 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY ( USART_TypeDef * LPUARTx )

Check if the LPUART Busy Flag is set or not.

Reference Manual to LL API cross reference:
ISR BUSY LL_LPUART_IsActiveFlag_BUSY
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1678 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM ( USART_TypeDef * LPUARTx )

Check if the LPUART Character Match Flag is set or not.

Reference Manual to LL API cross reference:
ISR CMF LL_LPUART_IsActiveFlag_CM
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1689 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS ( USART_TypeDef * LPUARTx )

Check if the LPUART CTS Flag is set or not.

Reference Manual to LL API cross reference:
ISR CTS LL_LPUART_IsActiveFlag_CTS
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1667 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE ( USART_TypeDef * LPUARTx )

Check if the LPUART Framing Error Flag is set or not.

Reference Manual to LL API cross reference:
ISR FE LL_LPUART_IsActiveFlag_FE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1573 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE ( USART_TypeDef * LPUARTx )

Check if the LPUART IDLE line detected Flag is set or not.

Reference Manual to LL API cross reference:
ISR IDLE LL_LPUART_IsActiveFlag_IDLE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1606 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS ( USART_TypeDef * LPUARTx )

Check if the LPUART CTS interrupt Flag is set or not.

Reference Manual to LL API cross reference:
ISR CTSIF LL_LPUART_IsActiveFlag_nCTS
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1656 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE ( USART_TypeDef * LPUARTx )

Check if the LPUART Noise error detected Flag is set or not.

Reference Manual to LL API cross reference:
ISR NE LL_LPUART_IsActiveFlag_NE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1584 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE ( USART_TypeDef * LPUARTx )

Check if the LPUART OverRun Error Flag is set or not.

Reference Manual to LL API cross reference:
ISR ORE LL_LPUART_IsActiveFlag_ORE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1595 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE ( USART_TypeDef * LPUARTx )

Check if the LPUART Parity Error Flag is set or not.

Reference Manual to LL API cross reference:
ISR PE LL_LPUART_IsActiveFlag_PE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1562 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK ( USART_TypeDef * LPUARTx )

Check if the LPUART Receive Enable Acknowledge Flag is set or not.

Reference Manual to LL API cross reference:
ISR REACK LL_LPUART_IsActiveFlag_REACK
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1744 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU ( USART_TypeDef * LPUARTx )

Check if the LPUART Receive Wake Up from mute mode Flag is set or not.

Reference Manual to LL API cross reference:
ISR RWU LL_LPUART_IsActiveFlag_RWU
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1711 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF ( USART_TypeDef * LPUARTx )

Check if the LPUART RX FIFO Full Flag is set or not.

Reference Manual to LL API cross reference:
ISR RXFF LL_LPUART_IsActiveFlag_RXFF
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1766 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT ( USART_TypeDef * LPUARTx )

Check if the LPUART RX FIFO Threshold Flag is set or not.

Reference Manual to LL API cross reference:
ISR RXFT LL_LPUART_IsActiveFlag_RXFT
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1788 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE ( USART_TypeDef * LPUARTx )

Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not.

Reference Manual to LL API cross reference:
ISR RXNE_RXFNE LL_LPUART_IsActiveFlag_RXNE_RXFNE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1620 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK ( USART_TypeDef * LPUARTx )

Check if the LPUART Send Break Flag is set or not.

Reference Manual to LL API cross reference:
ISR SBKF LL_LPUART_IsActiveFlag_SBK
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1700 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC ( USART_TypeDef * LPUARTx )

Check if the LPUART Transmission Complete Flag is set or not.

Reference Manual to LL API cross reference:
ISR TC LL_LPUART_IsActiveFlag_TC
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1631 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK ( USART_TypeDef * LPUARTx )

Check if the LPUART Transmit Enable Acknowledge Flag is set or not.

Reference Manual to LL API cross reference:
ISR TEACK LL_LPUART_IsActiveFlag_TEACK
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1733 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF ( USART_TypeDef * LPUARTx )

Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not.

Reference Manual to LL API cross reference:
ISR TXE_TXFNF LL_LPUART_IsActiveFlag_TXE_TXFNF
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1645 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE ( USART_TypeDef * LPUARTx )

Check if the LPUART TX FIFO Empty Flag is set or not.

Reference Manual to LL API cross reference:
ISR TXFE LL_LPUART_IsActiveFlag_TXFE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1755 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT ( USART_TypeDef * LPUARTx )

Check if the LPUART TX FIFO Threshold Flag is set or not.

Reference Manual to LL API cross reference:
ISR TXFT LL_LPUART_IsActiveFlag_TXFT
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1777 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP ( USART_TypeDef * LPUARTx )

Check if the LPUART Wake Up from stop mode Flag is set or not.

Reference Manual to LL API cross reference:
ISR WUF LL_LPUART_IsActiveFlag_WKUP
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 1722 of file stm32wbxx_ll_lpuart.h.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IT_Management

Defines | Functions
IT_Management
LPUART Exported Functions

Defines

#define | LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE
#define | LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF
#define | LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE
#define | LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF
#define | LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE
#define | LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF

Functions

__STATIC_INLINE void | LL_LPUART_EnableIT_IDLE (USART_TypeDef *LPUARTx)
Enable IDLE Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_RXNE_RXFNE (USART_TypeDef *LPUARTx)
Enable RX Not Empty and RX FIFO Not Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_TC (USART_TypeDef *LPUARTx)
Enable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_TXE_TXFNF (USART_TypeDef *LPUARTx)
Enable TX Empty and TX FIFO Not Full Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_PE (USART_TypeDef *LPUARTx)
Enable Parity Error Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_CM (USART_TypeDef *LPUARTx)
Enable Character Match Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_TXFE (USART_TypeDef *LPUARTx)
Enable TX FIFO Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_RXFF (USART_TypeDef *LPUARTx)
Enable RX FIFO Full Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_ERROR (USART_TypeDef *LPUARTx)
Enable Error Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_CTS (USART_TypeDef *LPUARTx)
Enable CTS Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_WKUP (USART_TypeDef *LPUARTx)
Enable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_TXFT (USART_TypeDef *LPUARTx)
Enable TX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_RXFT (USART_TypeDef *LPUARTx)
Enable RX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_IDLE (USART_TypeDef *LPUARTx)
Disable IDLE Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_RXNE_RXFNE (USART_TypeDef *LPUARTx)
Disable RX Not Empty and RX FIFO Not Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_TC (USART_TypeDef *LPUARTx)
Disable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_TXE_TXFNF (USART_TypeDef *LPUARTx)
Disable TX Empty and TX FIFO Not Full Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_PE (USART_TypeDef *LPUARTx)
Disable Parity Error Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_CM (USART_TypeDef *LPUARTx)
Disable Character Match Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_TXFE (USART_TypeDef *LPUARTx)
Disable TX FIFO Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_RXFF (USART_TypeDef *LPUARTx)
Disable RX FIFO Full Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_ERROR (USART_TypeDef *LPUARTx)
Disable Error Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_CTS (USART_TypeDef *LPUARTx)
Disable CTS Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_WKUP (USART_TypeDef *LPUARTx)
Disable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_TXFT (USART_TypeDef *LPUARTx)
Disable TX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_RXFT (USART_TypeDef *LPUARTx)
Disable RX FIFO Threshold Interrupt.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_IDLE (USART_TypeDef *LPUARTx)
Check if the LPUART IDLE Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_RXNE_RXFNE (USART_TypeDef *LPUARTx)
Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_TC (USART_TypeDef *LPUARTx)
Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_TXE_TXFNF (USART_TypeDef *LPUARTx)
Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_PE (USART_TypeDef *LPUARTx)
Check if the LPUART Parity Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_CM (USART_TypeDef *LPUARTx)
Check if the LPUART Character Match Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_TXFE (USART_TypeDef *LPUARTx)
Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_RXFF (USART_TypeDef *LPUARTx)
Check if the LPUART RX FIFO Full Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_ERROR (USART_TypeDef *LPUARTx)
Check if the LPUART Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_CTS (USART_TypeDef *LPUARTx)
Check if the LPUART CTS Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_WKUP (USART_TypeDef *LPUARTx)
Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_TXFT (USART_TypeDef *LPUARTx)
Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_RXFT (USART_TypeDef *LPUARTx)
Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled.

Define Documentation

#define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE

Definition at line 2076 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF

Definition at line 2101 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE

Definition at line 1923 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF

Definition at line 1948 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE

Definition at line 2229 of file stm32wbxx_ll_lpuart.h.

#define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF

Definition at line 2254 of file stm32wbxx_ll_lpuart.h.

Function Documentation

__STATIC_INLINE void LL_LPUART_DisableIT_CM ( USART_TypeDef * LPUARTx )

Disable Character Match Interrupt.

Reference Manual to LL API cross reference:
CR1 CMIE LL_LPUART_DisableIT_CM
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2131 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_CTS ( USART_TypeDef * LPUARTx )

Disable CTS Interrupt.

Reference Manual to LL API cross reference:
CR3 CTSIE LL_LPUART_DisableIT_CTS
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2179 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_ERROR ( USART_TypeDef * LPUARTx )

Disable Error Interrupt.

Note:
When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
  • 0: Interrupt is inhibited
  • 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
Reference Manual to LL API cross reference:
CR3 EIE LL_LPUART_DisableIT_ERROR
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2168 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_IDLE ( USART_TypeDef * LPUARTx )

Disable IDLE Interrupt.

Reference Manual to LL API cross reference:
CR1 IDLEIE LL_LPUART_DisableIT_IDLE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2070 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_PE ( USART_TypeDef * LPUARTx )

Disable Parity Error Interrupt.

Reference Manual to LL API cross reference:
CR1 PEIE LL_LPUART_DisableIT_PE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2120 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_RXFF ( USART_TypeDef * LPUARTx )

Disable RX FIFO Full Interrupt.

Reference Manual to LL API cross reference:
CR1 RXFFIE LL_LPUART_DisableIT_RXFF
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2153 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_RXFT ( USART_TypeDef * LPUARTx )

Disable RX FIFO Threshold Interrupt.

Reference Manual to LL API cross reference:
CR3 RXFTIE LL_LPUART_DisableIT_RXFT
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2212 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE ( USART_TypeDef * LPUARTx )

Disable RX Not Empty and RX FIFO Not Empty Interrupt.

Reference Manual to LL API cross reference:
CR1 RXNEIE_RXFNEIE LL_LPUART_DisableIT_RXNE_RXFNE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2084 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_TC ( USART_TypeDef * LPUARTx )

Disable Transmission Complete Interrupt.

Reference Manual to LL API cross reference:
CR1 TCIE LL_LPUART_DisableIT_TC
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2095 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF ( USART_TypeDef * LPUARTx )

Disable TX Empty and TX FIFO Not Full Interrupt.

Reference Manual to LL API cross reference:
CR1 TXEIE_TXFNFIE LL_LPUART_DisableIT_TXE_TXFNF
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2109 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_TXFE ( USART_TypeDef * LPUARTx )

Disable TX FIFO Empty Interrupt.

Reference Manual to LL API cross reference:
CR1 TXFEIE LL_LPUART_DisableIT_TXFE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2142 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_TXFT ( USART_TypeDef * LPUARTx )

Disable TX FIFO Threshold Interrupt.

Reference Manual to LL API cross reference:
CR3 TXFTIE LL_LPUART_DisableIT_TXFT
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2201 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableIT_WKUP ( USART_TypeDef * LPUARTx )

Disable Wake Up from Stop Mode Interrupt.

Reference Manual to LL API cross reference:
CR3 WUFIE LL_LPUART_DisableIT_WKUP
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2190 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_CM ( USART_TypeDef * LPUARTx )

Enable Character Match Interrupt.

Reference Manual to LL API cross reference:
CR1 CMIE LL_LPUART_EnableIT_CM
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1978 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_CTS ( USART_TypeDef * LPUARTx )

Enable CTS Interrupt.

Reference Manual to LL API cross reference:
CR3 CTSIE LL_LPUART_EnableIT_CTS
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2026 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_ERROR ( USART_TypeDef * LPUARTx )

Enable Error Interrupt.

Note:
When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
  • 0: Interrupt is inhibited
  • 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
Reference Manual to LL API cross reference:
CR3 EIE LL_LPUART_EnableIT_ERROR
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2015 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_IDLE ( USART_TypeDef * LPUARTx )

Enable IDLE Interrupt.

Reference Manual to LL API cross reference:
CR1 IDLEIE LL_LPUART_EnableIT_IDLE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1917 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_PE ( USART_TypeDef * LPUARTx )

Enable Parity Error Interrupt.

Reference Manual to LL API cross reference:
CR1 PEIE LL_LPUART_EnableIT_PE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1967 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_RXFF ( USART_TypeDef * LPUARTx )

Enable RX FIFO Full Interrupt.

Reference Manual to LL API cross reference:
CR1 RXFFIE LL_LPUART_EnableIT_RXFF
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2000 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_RXFT ( USART_TypeDef * LPUARTx )

Enable RX FIFO Threshold Interrupt.

Reference Manual to LL API cross reference:
CR3 RXFTIE LL_LPUART_EnableIT_RXFT
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2059 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE ( USART_TypeDef * LPUARTx )

Enable RX Not Empty and RX FIFO Not Empty Interrupt.

Reference Manual to LL API cross reference:
CR1 RXNEIE_RXFNEIE LL_LPUART_EnableIT_RXNE_RXFNE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1931 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_TC ( USART_TypeDef * LPUARTx )

Enable Transmission Complete Interrupt.

Reference Manual to LL API cross reference:
CR1 TCIE LL_LPUART_EnableIT_TC
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1942 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF ( USART_TypeDef * LPUARTx )

Enable TX Empty and TX FIFO Not Full Interrupt.

Reference Manual to LL API cross reference:
CR1 TXEIE_TXFNFIE LL_LPUART_EnableIT_TXE_TXFNF
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1956 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_TXFE ( USART_TypeDef * LPUARTx )

Enable TX FIFO Empty Interrupt.

Reference Manual to LL API cross reference:
CR1 TXFEIE LL_LPUART_EnableIT_TXFE
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 1989 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_TXFT ( USART_TypeDef * LPUARTx )

Enable TX FIFO Threshold Interrupt.

Reference Manual to LL API cross reference:
CR3 TXFTIE LL_LPUART_EnableIT_TXFT
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2048 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableIT_WKUP ( USART_TypeDef * LPUARTx )

Enable Wake Up from Stop Mode Interrupt.

Reference Manual to LL API cross reference:
CR3 WUFIE LL_LPUART_EnableIT_WKUP
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2037 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM ( USART_TypeDef * LPUARTx )

Check if the LPUART Character Match Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 CMIE LL_LPUART_IsEnabledIT_CM
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2284 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS ( USART_TypeDef * LPUARTx )

Check if the LPUART CTS Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR3 CTSIE LL_LPUART_IsEnabledIT_CTS
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2328 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR ( USART_TypeDef * LPUARTx )

Check if the LPUART Error Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR3 EIE LL_LPUART_IsEnabledIT_ERROR
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2317 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE ( USART_TypeDef * LPUARTx )

Check if the LPUART IDLE Interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 IDLEIE LL_LPUART_IsEnabledIT_IDLE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2223 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE ( USART_TypeDef * LPUARTx )

Check if the LPUART Parity Error Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 PEIE LL_LPUART_IsEnabledIT_PE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2273 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF ( USART_TypeDef * LPUARTx )

Check if the LPUART RX FIFO Full Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 RXFFIE LL_LPUART_IsEnabledIT_RXFF
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2306 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT ( USART_TypeDef * LPUARTx )

Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR3 RXFTIE LL_LPUART_IsEnabledIT_RXFT
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2361 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE ( USART_TypeDef * LPUARTx )

Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 RXNEIE_RXFNEIE LL_LPUART_IsEnabledIT_RXNE_RXFNE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2237 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC ( USART_TypeDef * LPUARTx )

Check if the LPUART Transmission Complete Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TCIE LL_LPUART_IsEnabledIT_TC
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2248 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF ( USART_TypeDef * LPUARTx )

Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TXEIE_TXFNFIE LL_LPUART_IsEnabledIT_TXE_TXFNF
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2262 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE ( USART_TypeDef * LPUARTx )

Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TXFEIE LL_LPUART_IsEnabledIT_TXFE
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2295 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT ( USART_TypeDef * LPUARTx )

Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR3 TXFTIE LL_LPUART_IsEnabledIT_TXFT
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2350 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP ( USART_TypeDef * LPUARTx )

Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR3 WUFIE LL_LPUART_IsEnabledIT_WKUP
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2339 of file stm32wbxx_ll_lpuart.h.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DMA_Management

Functions
DMA_Management
LPUART Exported Functions

Functions

__STATIC_INLINE void | LL_LPUART_EnableDMAReq_RX (USART_TypeDef *LPUARTx)
Enable DMA Mode for reception.
__STATIC_INLINE void | LL_LPUART_DisableDMAReq_RX (USART_TypeDef *LPUARTx)
Disable DMA Mode for reception.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDMAReq_RX (USART_TypeDef *LPUARTx)
Check if DMA Mode is enabled for reception.
__STATIC_INLINE void | LL_LPUART_EnableDMAReq_TX (USART_TypeDef *LPUARTx)
Enable DMA Mode for transmission.
__STATIC_INLINE void | LL_LPUART_DisableDMAReq_TX (USART_TypeDef *LPUARTx)
Disable DMA Mode for transmission.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDMAReq_TX (USART_TypeDef *LPUARTx)
Check if DMA Mode is enabled for transmission.
__STATIC_INLINE void | LL_LPUART_EnableDMADeactOnRxErr (USART_TypeDef *LPUARTx)
Enable DMA Disabling on Reception Error.
__STATIC_INLINE void | LL_LPUART_DisableDMADeactOnRxErr (USART_TypeDef *LPUARTx)
Disable DMA Disabling on Reception Error.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDMADeactOnRxErr (USART_TypeDef *LPUARTx)
Indicate if DMA Disabling on Reception Error is disabled.
__STATIC_INLINE uint32_t | LL_LPUART_DMA_GetRegAddr (USART_TypeDef *LPUARTx, uint32_t Direction)
Get the LPUART data register address used for DMA transfer.

Function Documentation

__STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr ( USART_TypeDef * LPUARTx )

Disable DMA Disabling on Reception Error.

Reference Manual to LL API cross reference:
CR3 DDRE LL_LPUART_DisableDMADeactOnRxErr
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2457 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableDMAReq_RX ( USART_TypeDef * LPUARTx )

Disable DMA Mode for reception.

Reference Manual to LL API cross reference:
CR3 DMAR LL_LPUART_DisableDMAReq_RX
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2391 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_DisableDMAReq_TX ( USART_TypeDef * LPUARTx )

Disable DMA Mode for transmission.

Reference Manual to LL API cross reference:
CR3 DMAT LL_LPUART_DisableDMAReq_TX
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2424 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr | ( | USART_TypeDef * | LPUARTx,
 |  | uint32_t | Direction
 | ) |  |

Get the LPUART data register address used for DMA transfer.

Reference Manual to LL API cross reference:
RDR RDR LL_LPUART_DMA_GetRegAddr
Reference Manual to LL API cross reference:
TDR TDR LL_LPUART_DMA_GetRegAddr
Parameters:
LPUARTx LPUART Instance
Direction This parameter can be one of the following values:
  • LL_LPUART_DMA_REG_DATA_TRANSMIT
  • LL_LPUART_DMA_REG_DATA_RECEIVE
Return values:
Address of data register

Definition at line 2483 of file stm32wbxx_ll_lpuart.h.

References LL_LPUART_DMA_REG_DATA_TRANSMIT.

__STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr ( USART_TypeDef * LPUARTx )

Enable DMA Disabling on Reception Error.

Reference Manual to LL API cross reference:
CR3 DDRE LL_LPUART_EnableDMADeactOnRxErr
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2446 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableDMAReq_RX ( USART_TypeDef * LPUARTx )

Enable DMA Mode for reception.

Reference Manual to LL API cross reference:
CR3 DMAR LL_LPUART_EnableDMAReq_RX
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2380 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_EnableDMAReq_TX ( USART_TypeDef * LPUARTx )

Enable DMA Mode for transmission.

Reference Manual to LL API cross reference:
CR3 DMAT LL_LPUART_EnableDMAReq_TX
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2413 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr ( USART_TypeDef * LPUARTx )

Indicate if DMA Disabling on Reception Error is disabled.

Reference Manual to LL API cross reference:
CR3 DDRE LL_LPUART_IsEnabledDMADeactOnRxErr
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2468 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX ( USART_TypeDef * LPUARTx )

Check if DMA Mode is enabled for reception.

Reference Manual to LL API cross reference:
CR3 DMAR LL_LPUART_IsEnabledDMAReq_RX
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2402 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX ( USART_TypeDef * LPUARTx )

Check if DMA Mode is enabled for transmission.

Reference Manual to LL API cross reference:
CR3 DMAT LL_LPUART_IsEnabledDMAReq_TX
Parameters:
LPUARTx LPUART Instance
Return values:
State of bit (1 or 0).

Definition at line 2435 of file stm32wbxx_ll_lpuart.h.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data_Management

Functions
Data_Management
LPUART Exported Functions

Functions

__STATIC_INLINE uint8_t | LL_LPUART_ReceiveData8 (USART_TypeDef *LPUARTx)
Read Receiver Data register (Receive Data value, 8 bits)
__STATIC_INLINE uint16_t | LL_LPUART_ReceiveData9 (USART_TypeDef *LPUARTx)
Read Receiver Data register (Receive Data value, 9 bits)
__STATIC_INLINE void | LL_LPUART_TransmitData8 (USART_TypeDef *LPUARTx, uint8_t Value)
Write in Transmitter Data Register (Transmit Data value, 8 bits)
__STATIC_INLINE void | LL_LPUART_TransmitData9 (USART_TypeDef *LPUARTx, uint16_t Value)
Write in Transmitter Data Register (Transmit Data value, 9 bits)

Function Documentation

__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8 ( USART_TypeDef * LPUARTx )

Read Receiver Data register (Receive Data value, 8 bits)

Reference Manual to LL API cross reference:
RDR RDR LL_LPUART_ReceiveData8
Parameters:
LPUARTx LPUART Instance
Return values:
Time Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 2515 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9 ( USART_TypeDef * LPUARTx )

Read Receiver Data register (Receive Data value, 9 bits)

Reference Manual to LL API cross reference:
RDR RDR LL_LPUART_ReceiveData9
Parameters:
LPUARTx LPUART Instance
Return values:
Time Value between Min_Data=0x00 and Max_Data=0x1FF

Definition at line 2526 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_TransmitData8 | ( | USART_TypeDef * | LPUARTx,
 |  | uint8_t | Value
 | ) |  |

Write in Transmitter Data Register (Transmit Data value, 8 bits)

Reference Manual to LL API cross reference:
TDR TDR LL_LPUART_TransmitData8
Parameters:
LPUARTx | LPUART Instance
Value | between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 2538 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_TransmitData9 | ( | USART_TypeDef * | LPUARTx,
 |  | uint16_t | Value
 | ) |  |

Write in Transmitter Data Register (Transmit Data value, 9 bits)

Reference Manual to LL API cross reference:
TDR TDR LL_LPUART_TransmitData9
Parameters:
LPUARTx | LPUART Instance
Value | between Min_Data=0x00 and Max_Data=0x1FF
Return values:
None

Definition at line 2550 of file stm32wbxx_ll_lpuart.h.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Execution

Functions
Execution
LPUART Exported Functions

Functions

__STATIC_INLINE void | LL_LPUART_RequestBreakSending (USART_TypeDef *LPUARTx)
Request Break sending.
__STATIC_INLINE void | LL_LPUART_RequestEnterMuteMode (USART_TypeDef *LPUARTx)
Put LPUART in mute mode and set the RWU flag.
__STATIC_INLINE void | LL_LPUART_RequestRxDataFlush (USART_TypeDef *LPUARTx)
Request a Receive Data and FIFO flush.

Function Documentation

__STATIC_INLINE void LL_LPUART_RequestBreakSending ( USART_TypeDef * LPUARTx )

Request Break sending.

Reference Manual to LL API cross reference:
RQR SBKRQ LL_LPUART_RequestBreakSending
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2569 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_RequestEnterMuteMode ( USART_TypeDef * LPUARTx )

Put LPUART in mute mode and set the RWU flag.

Reference Manual to LL API cross reference:
RQR MMRQ LL_LPUART_RequestEnterMuteMode
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2580 of file stm32wbxx_ll_lpuart.h.

__STATIC_INLINE void LL_LPUART_RequestRxDataFlush ( USART_TypeDef * LPUARTx )

Request a Receive Data and FIFO flush.

Note:
Allows to discard the received data without reading them, and avoid an overrun condition.
Reference Manual to LL API cross reference:
RQR RXFRQ LL_LPUART_RequestRxDataFlush
Parameters:
LPUARTx LPUART Instance
Return values:
None

Definition at line 2593 of file stm32wbxx_ll_lpuart.h.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
LPUART Exported Functions

Functions

ErrorStatus | LL_LPUART_DeInit (USART_TypeDef *LPUARTx)
De-initialize LPUART registers (Registers restored to their default values).
ErrorStatus | LL_LPUART_Init (USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct)
Initialize LPUART registers according to the specified parameters in LPUART_InitStruct.
void | LL_LPUART_StructInit (LL_LPUART_InitTypeDef *LPUART_InitStruct)
Set each LL_LPUART_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_LPUART_DeInit ( USART_TypeDef * LPUARTx )

De-initialize LPUART registers (Registers restored to their default values).

Parameters:
LPUARTx LPUART Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: LPUART registers are de-initialized
  • ERROR: not applicable

Definition at line 130 of file stm32wbxx_ll_lpuart.c.

References assert_param, LL_APB1_GRP2_ForceReset(), LL_APB1_GRP2_PERIPH_LPUART1, and LL_APB1_GRP2_ReleaseReset().

ErrorStatus LL_LPUART_Init | ( | USART_TypeDef * | LPUARTx,
 |  | LL_LPUART_InitTypeDef * | LPUART_InitStruct
 | ) |  |

Initialize LPUART registers according to the specified parameters in LPUART_InitStruct.

Note:
As some bits in LPUART configuration registers can only be written when the LPUART is disabled (USART_CR1_UE bit =0), LPUART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
Baud rate value stored in LPUART_InitStruct BaudRate field, should be valid (different from 0).
Parameters:
LPUARTx | LPUART Instance
LPUART_InitStruct | pointer to a LL_LPUART_InitTypeDef structure that contains the configuration information for the specified LPUART peripheral.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: LPUART registers are initialized according to LPUART_InitStruct content
  • ERROR: Problem occurred during LPUART Registers initialization

Definition at line 166 of file stm32wbxx_ll_lpuart.c.

References assert_param, LL_LPUART_InitTypeDef::BaudRate, LL_LPUART_InitTypeDef::DataWidth, LL_LPUART_InitTypeDef::HardwareFlowControl, IS_LL_LPUART_BAUDRATE, IS_LL_LPUART_BRR_MAX, IS_LL_LPUART_BRR_MIN, IS_LL_LPUART_DATAWIDTH, IS_LL_LPUART_DIRECTION, IS_LL_LPUART_HWCONTROL, IS_LL_LPUART_PARITY, IS_LL_LPUART_PRESCALER, IS_LL_LPUART_STOPBITS, LL_LPUART_IsEnabled(), LL_LPUART_SetBaudRate(), LL_LPUART_SetHWFlowCtrl(), LL_LPUART_SetPrescaler(), LL_LPUART_SetStopBitsLength(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_LPUART1_CLKSOURCE, LL_RCC_PERIPH_FREQUENCY_NO, LL_LPUART_InitTypeDef::Parity, LL_LPUART_InitTypeDef::PrescalerValue, LL_LPUART_InitTypeDef::StopBits, and LL_LPUART_InitTypeDef::TransferDirection.

void LL_LPUART_StructInit ( LL_LPUART_InitTypeDef * LPUART_InitStruct )

Set each LL_LPUART_InitTypeDef field to default value.

Parameters:
LPUART_InitStruct pointer to a LL_LPUART_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 250 of file stm32wbxx_ll_lpuart.c.

References LL_LPUART_InitTypeDef::BaudRate, LL_LPUART_InitTypeDef::DataWidth, LL_LPUART_InitTypeDef::HardwareFlowControl, LL_LPUART_DATAWIDTH_8B, LL_LPUART_DIRECTION_TX_RX, LL_LPUART_HWCONTROL_NONE, LL_LPUART_PARITY_NONE, LL_LPUART_PRESCALER_DIV1, LL_LPUART_STOPBITS_1, LL_LPUART_InitTypeDef::Parity, LL_LPUART_InitTypeDef::PrescalerValue, LL_LPUART_InitTypeDef::StopBits, and LL_LPUART_InitTypeDef::TransferDirection.

Generated on Fri Sep 6 2019 11:34:51 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PKA

Modules
PKA
STM32WBxx_LL_Driver

Modules

PKA Private Constants
PKA Exported Init structure
PKA Exported Constants
PKA Exported Macros
PKA Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for PKA registers.

Register | Bit | Function
CLRFR | ADDRERRFC | LL_PKA_ClearFlag_ADDERR
 | PROCENDFC | LL_PKA_ClearFlag_PROCEND
 | RAMERRFC | LL_PKA_ClearFlag_RAMERR
CR | ADDRERRIE | LL_PKA_DisableIT_ADDERR
 |  | LL_PKA_EnableIT_ADDRERR
 |  | LL_PKA_IsEnabledIT_ADDRERR
 | EN | LL_PKA_Disable
 |  | LL_PKA_Enable
 |  | LL_PKA_IsEnabled
 | MODE | LL_PKA_Config
 |  | LL_PKA_GetMode
 |  | LL_PKA_SetMode
 | PROCENDIE | LL_PKA_DisableIT_PROCEND
 |  | LL_PKA_EnableIT_PROCEND
 |  | LL_PKA_IsEnabledIT_PROCEND
 | RAMERRIE | LL_PKA_DisableIT_RAMERR
 |  | LL_PKA_EnableIT_RAMERR
 |  | LL_PKA_IsEnabledIT_RAMERR
 | START | LL_PKA_Start
SR | ADDRERRF | LL_PKA_IsActiveFlag_ADDRERR
 | BUSY | LL_PKA_IsActiveFlag_BUSY
 | PROCENDF | LL_PKA_IsActiveFlag_PROCEND
 | RAMERRF | LL_PKA_IsActiveFlag_RAMERR
Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PKA Private Constants

Defines
PKA Private Constants
PKA

Defines

#define IS_LL_PKA_MODE(__VALUE__)

Define Documentation

#define IS_LL_PKA_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_PKA_MODE_MONTGOMERY_PARAM_MOD_EXP) ||\
                                      ((__VALUE__) == LL_PKA_MODE_MONTGOMERY_PARAM)          ||\
                                      ((__VALUE__) == LL_PKA_MODE_MODULAR_EXP)               ||\
                                      ((__VALUE__) == LL_PKA_MODE_MONTGOMERY_PARAM_ECC)      ||\
                                      ((__VALUE__) == LL_PKA_MODE_ECC_KP_PRIMITIVE)          ||\
                                      ((__VALUE__) == LL_PKA_MODE_ECDSA_SIGNATURE)           ||\
                                      ((__VALUE__) == LL_PKA_MODE_ECDSA_VERIFICATION)        ||\
                                      ((__VALUE__) == LL_PKA_MODE_POINT_CHECK)               ||\
                                      ((__VALUE__) == LL_PKA_MODE_RSA_CRT_EXP)               ||\
                                      ((__VALUE__) == LL_PKA_MODE_MODULAR_INV)               ||\
                                      ((__VALUE__) == LL_PKA_MODE_ARITHMETIC_ADD)            ||\
                                      ((__VALUE__) == LL_PKA_MODE_ARITHMETIC_SUB)            ||\
                                      ((__VALUE__) == LL_PKA_MODE_ARITHMETIC_MUL)            ||\
                                      ((__VALUE__) == LL_PKA_MODE_COMPARISON)                ||\
                                      ((__VALUE__) == LL_PKA_MODE_MODULAR_REDUC)             ||\
                                      ((__VALUE__) == LL_PKA_MODE_MODULAR_ADD)               ||\
                                      ((__VALUE__) == LL_PKA_MODE_MODULAR_SUB)               ||\
                                      ((__VALUE__) == LL_PKA_MODE_MONTGOMERY_MUL))

Definition at line 48 of file stm32wbxx_ll_pka.c.

Referenced by LL_PKA_Init().

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STM32WB55xx HAL User Manual: LL_PKA_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_PKA_InitTypeDef Struct Reference
PKA Exported Init structure

PKA Init structures definition. More...

#include <stm32wbxx_ll_pka.h>

Data Fields

uint32_t Mode

Detailed Description

PKA Init structures definition.

Definition at line 52 of file stm32wbxx_ll_pka.h.

Field Documentation

uint32_t LL_PKA_InitTypeDef::Mode

Specifies the PKA operation mode. This parameter can be a value of Operation Mode.

This feature can be modified afterwards using unitary function LL_PKA_SetMode().

Definition at line 54 of file stm32wbxx_ll_pka.h.

Referenced by LL_PKA_Init(), and LL_PKA_StructInit().

The documentation for this struct was generated from the following file:
  • stm32wbxx_ll_pka.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
PKA Exported Constants

Flags defines which can be used with LL_PKA_ReadReg function. More...

Defines

#define | LL_PKA_SR_ADDRERRF PKA_SR_ADDRERRF
#define | LL_PKA_SR_RAMERRF PKA_SR_RAMERRF
#define | LL_PKA_SR_PROCENDF PKA_SR_PROCENDF
#define | LL_PKA_SR_BUSY PKA_SR_BUSY

Detailed Description

Flags defines which can be used with LL_PKA_ReadReg function.

Define Documentation

#define LL_PKA_SR_ADDRERRF PKA_SR_ADDRERRF

Definition at line 74 of file stm32wbxx_ll_pka.h.

#define LL_PKA_SR_BUSY PKA_SR_BUSY

Definition at line 77 of file stm32wbxx_ll_pka.h.

#define LL_PKA_SR_PROCENDF PKA_SR_PROCENDF

Definition at line 76 of file stm32wbxx_ll_pka.h.

#define LL_PKA_SR_RAMERRF PKA_SR_RAMERRF

Definition at line 75 of file stm32wbxx_ll_pka.h.

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IT Defines

Defines
IT Defines
PKA Exported Constants

IT defines which can be used with LL_PKA_ReadReg and LL_PKA_WriteReg functions. More...

Defines

#define | LL_PKA_CR_ADDRERRIE PKA_CR_ADDRERRIE
#define | LL_PKA_CR_RAMERRIE PKA_CR_RAMERRIE
#define | LL_PKA_CR_PROCENDIE PKA_CR_PROCENDIE
#define | LL_PKA_CLRFR_PROCENDFC PKA_CLRFR_PROCENDFC
#define | LL_PKA_CLRFR_RAMERRFC PKA_CLRFR_RAMERRFC
#define | LL_PKA_CLRFR_ADDRERRFC PKA_CLRFR_ADDRERRFC

Detailed Description

IT defines which can be used with LL_PKA_ReadReg and LL_PKA_WriteReg functions.

Define Documentation

#define LL_PKA_CLRFR_ADDRERRFC PKA_CLRFR_ADDRERRFC

Definition at line 91 of file stm32wbxx_ll_pka.h.

#define LL_PKA_CLRFR_PROCENDFC PKA_CLRFR_PROCENDFC

Definition at line 89 of file stm32wbxx_ll_pka.h.

#define LL_PKA_CLRFR_RAMERRFC PKA_CLRFR_RAMERRFC

Definition at line 90 of file stm32wbxx_ll_pka.h.

#define LL_PKA_CR_ADDRERRIE PKA_CR_ADDRERRIE

Definition at line 86 of file stm32wbxx_ll_pka.h.

#define LL_PKA_CR_PROCENDIE PKA_CR_PROCENDIE

Definition at line 88 of file stm32wbxx_ll_pka.h.

#define LL_PKA_CR_RAMERRIE PKA_CR_RAMERRIE

Definition at line 87 of file stm32wbxx_ll_pka.h.

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Operation Mode

Defines
Operation Mode
PKA Exported Constants

List of opearation mode. More...

Defines

#define | LL_PKA_MODE_MONTGOMERY_PARAM_MOD_EXP ((uint32_t)0x00000000U)
#define | LL_PKA_MODE_MONTGOMERY_PARAM ((uint32_t)0x00000001U)
#define | LL_PKA_MODE_MODULAR_EXP ((uint32_t)0x00000002U)
#define | LL_PKA_MODE_MONTGOMERY_PARAM_ECC ((uint32_t)0x00000020U)
#define | LL_PKA_MODE_ECC_KP_PRIMITIVE ((uint32_t)0x00000022U)
#define | LL_PKA_MODE_ECDSA_SIGNATURE ((uint32_t)0x00000024U)
#define | LL_PKA_MODE_ECDSA_VERIFICATION ((uint32_t)0x00000026U)
#define | LL_PKA_MODE_POINT_CHECK ((uint32_t)0x00000028U)
#define | LL_PKA_MODE_RSA_CRT_EXP ((uint32_t)0x00000007U)
#define | LL_PKA_MODE_MODULAR_INV ((uint32_t)0x00000008U)
#define | LL_PKA_MODE_ARITHMETIC_ADD ((uint32_t)0x00000009U)
#define | LL_PKA_MODE_ARITHMETIC_SUB ((uint32_t)0x0000000AU)
#define | LL_PKA_MODE_ARITHMETIC_MUL ((uint32_t)0x0000000BU)
#define | LL_PKA_MODE_COMPARISON ((uint32_t)0x0000000CU)
#define | LL_PKA_MODE_MODULAR_REDUC ((uint32_t)0x0000000DU)
#define | LL_PKA_MODE_MODULAR_ADD ((uint32_t)0x0000000EU)
#define | LL_PKA_MODE_MODULAR_SUB ((uint32_t)0x0000000FU)
#define | LL_PKA_MODE_MONTGOMERY_MUL ((uint32_t)0x00000010U)

Detailed Description

List of opearation mode.

Define Documentation

#define LL_PKA_MODE_ARITHMETIC_ADD ((uint32_t)0x00000009U)

Arithmetic addition

Definition at line 110 of file stm32wbxx_ll_pka.h.

#define LL_PKA_MODE_ARITHMETIC_MUL ((uint32_t)0x0000000BU)

Arithmetic multiplication

Definition at line 112 of file stm32wbxx_ll_pka.h.

#define LL_PKA_MODE_ARITHMETIC_SUB ((uint32_t)0x0000000AU)

Arithmetic subtraction

Definition at line 111 of file stm32wbxx_ll_pka.h.

#define LL_PKA_MODE_COMPARISON ((uint32_t)0x0000000CU)

Comparison

Definition at line 113 of file stm32wbxx_ll_pka.h.

#define LL_PKA_MODE_ECC_KP_PRIMITIVE ((uint32_t)0x00000022U)

Compute the ECC kP primitive only (Montgomery parameter should be loaded)

Definition at line 104 of file stm32wbxx_ll_pka.h.

#define LL_PKA_MODE_ECDSA_SIGNATURE ((uint32_t)0x00000024U)

ECDSA signature

Definition at line 105 of file stm32wbxx_ll_pka.h.

#define LL_PKA_MODE_ECDSA_VERIFICATION ((uint32_t)0x00000026U)

ECDSA verification

Definition at line 106 of file stm32wbxx_ll_pka.h.

#define LL_PKA_MODE_MODULAR_ADD ((uint32_t)0x0000000EU)

Modular addition

Definition at line 115 of file stm32wbxx_ll_pka.h.

#define LL_PKA_MODE_MODULAR_EXP ((uint32_t)0x00000002U)

Compute modular exponentiation only (Montgomery parameter should be loaded)

Definition at line 102 of file stm32wbxx_ll_pka.h.

#define LL_PKA_MODE_MODULAR_INV ((uint32_t)0x00000008U)

Modular inversion

Definition at line 109 of file stm32wbxx_ll_pka.h.

#define LL_PKA_MODE_MODULAR_REDUC ((uint32_t)0x0000000DU)

Modular reduction

Definition at line 114 of file stm32wbxx_ll_pka.h.

#define LL_PKA_MODE_MODULAR_SUB ((uint32_t)0x0000000FU)

Modular subtraction

Definition at line 116 of file stm32wbxx_ll_pka.h.

#define LL_PKA_MODE_MONTGOMERY_MUL ((uint32_t)0x00000010U)

Montgomery multiplication

Definition at line 117 of file stm32wbxx_ll_pka.h.

#define LL_PKA_MODE_MONTGOMERY_PARAM ((uint32_t)0x00000001U)

Compute Montgomery parameter only

Definition at line 101 of file stm32wbxx_ll_pka.h.

#define LL_PKA_MODE_MONTGOMERY_PARAM_ECC ((uint32_t)0x00000020U)

Compute Montgomery parameter and compute ECC kP operation

Definition at line 103 of file stm32wbxx_ll_pka.h.

#define LL_PKA_MODE_MONTGOMERY_PARAM_MOD_EXP ((uint32_t)0x00000000U)

Compute Montgomery parameter and modular exponentiation

Definition at line 100 of file stm32wbxx_ll_pka.h.

Referenced by LL_PKA_StructInit().

#define LL_PKA_MODE_POINT_CHECK ((uint32_t)0x00000028U)

Point check

Definition at line 107 of file stm32wbxx_ll_pka.h.

#define LL_PKA_MODE_RSA_CRT_EXP ((uint32_t)0x00000007U)

RSA CRT exponentiation

Definition at line 108 of file stm32wbxx_ll_pka.h.

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
PKA Exported Macros

Defines

#define | LL_PKA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in PKA register.
#define | LL_PKA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in PKA register.

Define Documentation

#define LL_PKA_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in PKA register.

Parameters:
__INSTANCE__ | PKA Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 150 of file stm32wbxx_ll_pka.h.

#define LL_PKA_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in PKA register.

Parameters:
__INSTANCE__ | PKA Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 142 of file stm32wbxx_ll_pka.h.

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Configuration

Functions
Configuration
PKA Exported Functions

Functions

__STATIC_INLINE void | LL_PKA_Config (PKA_TypeDef *PKAx, uint32_t Mode)
Configure PKA peripheral.
__STATIC_INLINE void | LL_PKA_Enable (PKA_TypeDef *PKAx)
Enable PKA peripheral.
__STATIC_INLINE void | LL_PKA_Disable (PKA_TypeDef *PKAx)
Disable PKA peripheral.
__STATIC_INLINE uint32_t | LL_PKA_IsEnabled (PKA_TypeDef *PKAx)
Check if the PKA peripheral is enabled or disabled.
__STATIC_INLINE void | LL_PKA_SetMode (PKA_TypeDef *PKAx, uint32_t Mode)
Set PKA operating mode.
__STATIC_INLINE uint32_t | LL_PKA_GetMode (PKA_TypeDef *PKAx)
Get PKA operating mode.
__STATIC_INLINE void | LL_PKA_Start (PKA_TypeDef *PKAx)
Start the operation selected using LL_PKA_SetMode.

Function Documentation

__STATIC_INLINE void LL_PKA_Config | ( | PKA_TypeDef * | PKAx,
 |  | uint32_t | Mode
 | ) |  |

Configure PKA peripheral.

Set PKA operating mode.

Reference Manual to LL API cross reference:
CR MODE LL_PKA_Config
Parameters:
PKAx PKA Instance.
Mode This parameter can be one of the following values:
  • LL_PKA_MODE_MONTGOMERY_PARAM_MOD_EXP
  • LL_PKA_MODE_MONTGOMERY_PARAM
  • LL_PKA_MODE_MODULAR_EXP
  • LL_PKA_MODE_MONTGOMERY_PARAM_ECC
  • LL_PKA_MODE_ECC_KP_PRIMITIVE
  • LL_PKA_MODE_ECDSA_SIGNATURE
  • LL_PKA_MODE_ECDSA_VERIFICATION
  • LL_PKA_MODE_POINT_CHECK
  • LL_PKA_MODE_RSA_CRT_EXP
  • LL_PKA_MODE_MODULAR_INV
  • LL_PKA_MODE_ARITHMETIC_ADD
  • LL_PKA_MODE_ARITHMETIC_SUB
  • LL_PKA_MODE_ARITHMETIC_MUL
  • LL_PKA_MODE_COMPARISON
  • LL_PKA_MODE_MODULAR_REDUC
  • LL_PKA_MODE_MODULAR_ADD
  • LL_PKA_MODE_MODULAR_SUB
  • LL_PKA_MODE_MONTGOMERY_MUL

Definition at line 193 of file stm32wbxx_ll_pka.h.

Referenced by LL_PKA_Init().

__STATIC_INLINE void LL_PKA_Disable ( PKA_TypeDef * PKAx )

Disable PKA peripheral.

Reference Manual to LL API cross reference:
CR EN LL_PKA_Disable
Parameters:
PKAx PKA Instance.
Return values:
None

Definition at line 215 of file stm32wbxx_ll_pka.h.

__STATIC_INLINE void LL_PKA_Enable ( PKA_TypeDef * PKAx )

Enable PKA peripheral.

Reference Manual to LL API cross reference:
CR EN LL_PKA_Enable
Parameters:
PKAx PKA Instance.
Return values:
None

Definition at line 204 of file stm32wbxx_ll_pka.h.

__STATIC_INLINE uint32_t LL_PKA_GetMode ( PKA_TypeDef * PKAx )

Get PKA operating mode.

Reference Manual to LL API cross reference:
CR MODE LL_PKA_GetMode
Parameters:
PKAx PKA Instance.
Return values:
Returned value can be one of the following values:
  • LL_PKA_MODE_MONTGOMERY_PARAM_MOD_EXP
  • LL_PKA_MODE_MONTGOMERY_PARAM
  • LL_PKA_MODE_MODULAR_EXP
  • LL_PKA_MODE_MONTGOMERY_PARAM_ECC
  • LL_PKA_MODE_ECC_KP_PRIMITIVE
  • LL_PKA_MODE_ECDSA_SIGNATURE
  • LL_PKA_MODE_ECDSA_VERIFICATION
  • LL_PKA_MODE_POINT_CHECK
  • LL_PKA_MODE_RSA_CRT_EXP
  • LL_PKA_MODE_MODULAR_INV
  • LL_PKA_MODE_ARITHMETIC_ADD
  • LL_PKA_MODE_ARITHMETIC_SUB
  • LL_PKA_MODE_ARITHMETIC_MUL
  • LL_PKA_MODE_COMPARISON
  • LL_PKA_MODE_MODULAR_REDUC
  • LL_PKA_MODE_MODULAR_ADD
  • LL_PKA_MODE_MODULAR_SUB
  • LL_PKA_MODE_MONTGOMERY_MUL

Definition at line 285 of file stm32wbxx_ll_pka.h.

__STATIC_INLINE uint32_t LL_PKA_IsEnabled ( PKA_TypeDef * PKAx )

Check if the PKA peripheral is enabled or disabled.

Reference Manual to LL API cross reference:
CR EN LL_PKA_IsEnabled
Parameters:
PKAx PKA Instance.
Return values:
State of bit (1 or 0).

Definition at line 226 of file stm32wbxx_ll_pka.h.

__STATIC_INLINE void LL_PKA_SetMode | ( | PKA_TypeDef * | PKAx,
 |  | uint32_t | Mode
 | ) |  |

Set PKA operating mode.

Reference Manual to LL API cross reference:
CR MODE LL_PKA_SetMode
Parameters:
PKAx PKA Instance.
Mode This parameter can be one of the following values:
  • LL_PKA_MODE_MONTGOMERY_PARAM_MOD_EXP
  • LL_PKA_MODE_MONTGOMERY_PARAM
  • LL_PKA_MODE_MODULAR_EXP
  • LL_PKA_MODE_MONTGOMERY_PARAM_ECC
  • LL_PKA_MODE_ECC_KP_PRIMITIVE
  • LL_PKA_MODE_ECDSA_SIGNATURE
  • LL_PKA_MODE_ECDSA_VERIFICATION
  • LL_PKA_MODE_POINT_CHECK
  • LL_PKA_MODE_RSA_CRT_EXP
  • LL_PKA_MODE_MODULAR_INV
  • LL_PKA_MODE_ARITHMETIC_ADD
  • LL_PKA_MODE_ARITHMETIC_SUB
  • LL_PKA_MODE_ARITHMETIC_MUL
  • LL_PKA_MODE_COMPARISON
  • LL_PKA_MODE_MODULAR_REDUC
  • LL_PKA_MODE_MODULAR_ADD
  • LL_PKA_MODE_MODULAR_SUB
  • LL_PKA_MODE_MONTGOMERY_MUL
Return values:
None

Definition at line 256 of file stm32wbxx_ll_pka.h.

__STATIC_INLINE void LL_PKA_Start ( PKA_TypeDef * PKAx )

Start the operation selected using LL_PKA_SetMode.

Reference Manual to LL API cross reference:
CR START LL_PKA_Start
Parameters:
PKAx PKA Instance.
Return values:
None

Definition at line 296 of file stm32wbxx_ll_pka.h.

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IT_Management

Functions
IT_Management
PKA Exported Functions

Functions

__STATIC_INLINE void | LL_PKA_EnableIT_ADDRERR (PKA_TypeDef *PKAx)
Enable address error interrupt.
__STATIC_INLINE void | LL_PKA_EnableIT_RAMERR (PKA_TypeDef *PKAx)
Enable RAM error interrupt.
__STATIC_INLINE void | LL_PKA_EnableIT_PROCEND (PKA_TypeDef *PKAx)
Enable end of operation interrupt.
__STATIC_INLINE void | LL_PKA_DisableIT_ADDERR (PKA_TypeDef *PKAx)
Disable address error interrupt.
__STATIC_INLINE void | LL_PKA_DisableIT_RAMERR (PKA_TypeDef *PKAx)
Disable RAM error interrupt.
__STATIC_INLINE void | LL_PKA_DisableIT_PROCEND (PKA_TypeDef *PKAx)
Disable End of operation interrupt.
__STATIC_INLINE uint32_t | LL_PKA_IsEnabledIT_ADDRERR (PKA_TypeDef *PKAx)
Check if address error interrupt is enabled.
__STATIC_INLINE uint32_t | LL_PKA_IsEnabledIT_RAMERR (PKA_TypeDef *PKAx)
Check if RAM error interrupt is enabled.
__STATIC_INLINE uint32_t | LL_PKA_IsEnabledIT_PROCEND (PKA_TypeDef *PKAx)
Check if end of operation interrupt is enabled.

Function Documentation

__STATIC_INLINE void LL_PKA_DisableIT_ADDERR ( PKA_TypeDef * PKAx )

Disable address error interrupt.

Reference Manual to LL API cross reference:
CR ADDRERRIE LL_PKA_DisableIT_ADDERR
Parameters:
PKAx PKA Instance.
Return values:
None

Definition at line 348 of file stm32wbxx_ll_pka.h.

__STATIC_INLINE void LL_PKA_DisableIT_PROCEND ( PKA_TypeDef * PKAx )

Disable End of operation interrupt.

Reference Manual to LL API cross reference:
CR PROCENDIE LL_PKA_DisableIT_PROCEND
Parameters:
PKAx PKA Instance.
Return values:
None

Definition at line 370 of file stm32wbxx_ll_pka.h.

__STATIC_INLINE void LL_PKA_DisableIT_RAMERR ( PKA_TypeDef * PKAx )

Disable RAM error interrupt.

Reference Manual to LL API cross reference:
CR RAMERRIE LL_PKA_DisableIT_RAMERR
Parameters:
PKAx PKA Instance.
Return values:
None

Definition at line 359 of file stm32wbxx_ll_pka.h.

__STATIC_INLINE void LL_PKA_EnableIT_ADDRERR ( PKA_TypeDef * PKAx )

Enable address error interrupt.

Reference Manual to LL API cross reference:
CR ADDRERRIE LL_PKA_EnableIT_ADDRERR
Parameters:
PKAx PKA Instance.
Return values:
None

Definition at line 315 of file stm32wbxx_ll_pka.h.

__STATIC_INLINE void LL_PKA_EnableIT_PROCEND ( PKA_TypeDef * PKAx )

Enable end of operation interrupt.

Reference Manual to LL API cross reference:
CR PROCENDIE LL_PKA_EnableIT_PROCEND
Parameters:
PKAx PKA Instance.
Return values:
None

Definition at line 337 of file stm32wbxx_ll_pka.h.

__STATIC_INLINE void LL_PKA_EnableIT_RAMERR ( PKA_TypeDef * PKAx )

Enable RAM error interrupt.

Reference Manual to LL API cross reference:
CR RAMERRIE LL_PKA_EnableIT_RAMERR
Parameters:
PKAx PKA Instance.
Return values:
None

Definition at line 326 of file stm32wbxx_ll_pka.h.

__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_ADDRERR ( PKA_TypeDef * PKAx )

Check if address error interrupt is enabled.

Reference Manual to LL API cross reference:
CR ADDRERRIE LL_PKA_IsEnabledIT_ADDRERR
Parameters:
PKAx PKA Instance.
Return values:
State of bit (1 or 0).

Definition at line 381 of file stm32wbxx_ll_pka.h.

__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_PROCEND ( PKA_TypeDef * PKAx )

Check if end of operation interrupt is enabled.

Reference Manual to LL API cross reference:
CR PROCENDIE LL_PKA_IsEnabledIT_PROCEND
Parameters:
PKAx PKA Instance.
Return values:
State of bit (1 or 0).

Definition at line 403 of file stm32wbxx_ll_pka.h.

__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_RAMERR ( PKA_TypeDef * PKAx )

Check if RAM error interrupt is enabled.

Reference Manual to LL API cross reference:
CR RAMERRIE LL_PKA_IsEnabledIT_RAMERR
Parameters:
PKAx PKA Instance.
Return values:
State of bit (1 or 0).

Definition at line 392 of file stm32wbxx_ll_pka.h.

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PKA flag management

Functions
PKA flag management
PKA Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_PKA_IsActiveFlag_ADDRERR (PKA_TypeDef *PKAx)
Get PKA address error flag.
__STATIC_INLINE uint32_t | LL_PKA_IsActiveFlag_RAMERR (PKA_TypeDef *PKAx)
Get PKA RAM error flag.
__STATIC_INLINE uint32_t | LL_PKA_IsActiveFlag_PROCEND (PKA_TypeDef *PKAx)
Get PKA end of operation flag.
__STATIC_INLINE uint32_t | LL_PKA_IsActiveFlag_BUSY (PKA_TypeDef *PKAx)
Get PKA busy flag.
__STATIC_INLINE void | LL_PKA_ClearFlag_ADDERR (PKA_TypeDef *PKAx)
Clear PKA address error flag.
__STATIC_INLINE void | LL_PKA_ClearFlag_RAMERR (PKA_TypeDef *PKAx)
Clear PKA RAM error flag.
__STATIC_INLINE void | LL_PKA_ClearFlag_PROCEND (PKA_TypeDef *PKAx)
Clear PKA end of operation flag.

Function Documentation

__STATIC_INLINE void LL_PKA_ClearFlag_ADDERR ( PKA_TypeDef * PKAx )

Clear PKA address error flag.

Reference Manual to LL API cross reference:
CLRFR ADDRERRFC LL_PKA_ClearFlag_ADDERR
Parameters:
PKAx PKA Instance.
Return values:
None

Definition at line 466 of file stm32wbxx_ll_pka.h.

__STATIC_INLINE void LL_PKA_ClearFlag_PROCEND ( PKA_TypeDef * PKAx )

Clear PKA end of operation flag.

Reference Manual to LL API cross reference:
CLRFR PROCENDFC LL_PKA_ClearFlag_PROCEND
Parameters:
PKAx PKA Instance.
Return values:
None

Definition at line 488 of file stm32wbxx_ll_pka.h.

__STATIC_INLINE void LL_PKA_ClearFlag_RAMERR ( PKA_TypeDef * PKAx )

Clear PKA RAM error flag.

Reference Manual to LL API cross reference:
CLRFR RAMERRFC LL_PKA_ClearFlag_RAMERR
Parameters:
PKAx PKA Instance.
Return values:
None

Definition at line 477 of file stm32wbxx_ll_pka.h.

__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_ADDRERR ( PKA_TypeDef * PKAx )

Get PKA address error flag.

Reference Manual to LL API cross reference:
SR ADDRERRF LL_PKA_IsActiveFlag_ADDRERR
Parameters:
PKAx PKA Instance.
Return values:
State of bit (1 or 0).

Definition at line 422 of file stm32wbxx_ll_pka.h.

__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_BUSY ( PKA_TypeDef * PKAx )

Get PKA busy flag.

Reference Manual to LL API cross reference:
SR BUSY LL_PKA_IsActiveFlag_BUSY
Parameters:
PKAx PKA Instance.
Return values:
State of bit (1 or 0).

Definition at line 455 of file stm32wbxx_ll_pka.h.

__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_PROCEND ( PKA_TypeDef * PKAx )

Get PKA end of operation flag.

Reference Manual to LL API cross reference:
SR PROCENDF LL_PKA_IsActiveFlag_PROCEND
Parameters:
PKAx PKA Instance.
Return values:
State of bit (1 or 0).

Definition at line 444 of file stm32wbxx_ll_pka.h.

__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_RAMERR ( PKA_TypeDef * PKAx )

Get PKA RAM error flag.

Reference Manual to LL API cross reference:
SR RAMERRF LL_PKA_IsActiveFlag_RAMERR
Parameters:
PKAx PKA Instance.
Return values:
State of bit (1 or 0).

Definition at line 433 of file stm32wbxx_ll_pka.h.

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
PKA Exported Functions

Functions

ErrorStatus | LL_PKA_DeInit (PKA_TypeDef *PKAx)
De-initialize PKA registers (Registers restored to their default values).
ErrorStatus | LL_PKA_Init (PKA_TypeDef *PKAx, LL_PKA_InitTypeDef *PKA_InitStruct)
Initialize PKA registers according to the specified parameters in PKA_InitStruct.
void | LL_PKA_StructInit (LL_PKA_InitTypeDef *PKA_InitStruct)
Set each LL_PKA_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_PKA_DeInit ( PKA_TypeDef * PKAx )

De-initialize PKA registers (Registers restored to their default values).

Parameters:
PKAx PKA Instance.
Return values:
ErrorStatus
  • SUCCESS: PKA registers are de-initialized
  • ERROR: PKA registers are not de-initialized

Definition at line 89 of file stm32wbxx_ll_pka.c.

References assert_param, LL_AHB3_GRP1_ForceReset(), LL_AHB3_GRP1_PERIPH_PKA, and LL_AHB3_GRP1_ReleaseReset().

ErrorStatus LL_PKA_Init | ( | PKA_TypeDef * | PKAx,
 |  | LL_PKA_InitTypeDef * | PKA_InitStruct
 | ) |  |

Initialize PKA registers according to the specified parameters in PKA_InitStruct.

Parameters:
PKAx | PKA Instance.
PKA_InitStruct | pointer to a LL_PKA_InitTypeDef structure that contains the configuration information for the specified PKA peripheral.
Return values:
ErrorStatus
  • SUCCESS: PKA registers are initialized according to PKA_InitStruct content
  • ERROR: Not applicable

Definition at line 121 of file stm32wbxx_ll_pka.c.

References assert_param, IS_LL_PKA_MODE, LL_PKA_Config(), and LL_PKA_InitTypeDef::Mode.

void LL_PKA_StructInit ( LL_PKA_InitTypeDef * PKA_InitStruct )

Set each LL_PKA_InitTypeDef field to default value.

Parameters:
PKA_InitStruct pointer to a LL_PKA_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 138 of file stm32wbxx_ll_pka.c.

References LL_PKA_MODE_MONTGOMERY_PARAM_MOD_EXP, and LL_PKA_InitTypeDef::Mode.

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PWR

Modules
PWR
STM32WBxx_LL_Driver

Modules

PWR Private Constants
PWR Exported Constants
PWR Exported Macros
PWR Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for PWR registers.

Register | Bit | Function
C2CR1 | 802EWKUP | LL_C2_PWR_IsWokenUp_802_15_4
 |  | LL_C2_PWR_WakeUp_802_15_4
 | BLEEWKUP | LL_C2_PWR_IsWokenUp_BLE
 |  | LL_C2_PWR_WakeUp_BLE
 | FPDR | LL_C2_PWR_GetFlashPowerModeLPRun
 |  | LL_C2_PWR_SetFlashPowerModeLPRun
 | FPDS | LL_C2_PWR_GetFlashPowerModeSleep
 |  | LL_C2_PWR_SetFlashPowerModeSleep
 | LPMS | LL_C2_PWR_GetPowerMode
 |  | LL_C2_PWR_SetPowerMode
C2CR3 | APC | LL_C2_PWR_DisablePUPDCfg
 |  | LL_C2_PWR_EnablePUPDCfg
 |  | LL_C2_PWR_IsEnabledPUPDCfg
 | E802WUP | LL_C2_PWR_DisableIT_802WU
 |  | LL_C2_PWR_EnableIT_802WU
 |  | LL_C2_PWR_IsEnabledIT_802WU
 | EBLEWUP | LL_C2_PWR_DisableIT_BLEWU
 |  | LL_C2_PWR_EnableIT_BLEWU
 |  | LL_C2_PWR_IsEnabledIT_BLEWU
 | EIWUL | LL_C2_PWR_DisableInternWU
 |  | LL_C2_PWR_EnableInternWU
 |  | LL_C2_PWR_IsEnabledInternWU
 | EWUP1 | LL_C2_PWR_DisableWakeUpPin
 |  | LL_C2_PWR_EnableWakeUpPin
 |  | LL_C2_PWR_IsEnabledWakeUpPin
 | EWUP2 | LL_C2_PWR_DisableWakeUpPin
 |  | LL_C2_PWR_EnableWakeUpPin
 |  | LL_C2_PWR_IsEnabledWakeUpPin
 | EWUP3 | LL_C2_PWR_DisableWakeUpPin
 |  | LL_C2_PWR_EnableWakeUpPin
 |  | LL_C2_PWR_IsEnabledWakeUpPin
 | EWUP4 | LL_C2_PWR_DisableWakeUpPin
 |  | LL_C2_PWR_EnableWakeUpPin
 |  | LL_C2_PWR_IsEnabledWakeUpPin
 | EWUP5 | LL_C2_PWR_DisableWakeUpPin
 |  | LL_C2_PWR_EnableWakeUpPin
 |  | LL_C2_PWR_IsEnabledWakeUpPin
CR1 | DBP | LL_PWR_DisableBkUpAccess
 |  | LL_PWR_EnableBkUpAccess
 |  | LL_PWR_IsEnabledBkUpAccess
 | FPDR | LL_PWR_GetFlashPowerModeLPRun
 |  | LL_PWR_SetFlashPowerModeLPRun
 | FPDS | LL_PWR_GetFlashPowerModeSleep
 |  | LL_PWR_SetFlashPowerModeSleep
 | LPMS | LL_PWR_GetPowerMode
 |  | LL_PWR_SetPowerMode
 | LPR | LL_PWR_EnterLowPowerRunMode
 |  | LL_PWR_ExitLowPowerRunMode
 |  | LL_PWR_IsEnabledLowPowerRunMode
 | VOS | LL_PWR_GetRegulVoltageScaling
 |  | LL_PWR_SetRegulVoltageScaling
CR2 | PLS | LL_PWR_GetPVDLevel
 |  | LL_PWR_SetPVDLevel
 | PVDE | LL_PWR_DisablePVD
 |  | LL_PWR_EnablePVD
 |  | LL_PWR_IsEnabledPVD
 | PVME1 | LL_PWR_DisablePVM
 |  | LL_PWR_EnablePVM
 |  | LL_PWR_IsEnabledPVM
 | PVME3 | LL_PWR_DisablePVM
 |  | LL_PWR_EnablePVM
 |  | LL_PWR_IsEnabledPVM
 | USV | LL_PWR_DisableVddUSB
 |  | LL_PWR_EnableVddUSB
 |  | LL_PWR_IsEnabledVddUSB
CR3 | APC | LL_PWR_DisablePUPDCfg
 |  | LL_PWR_EnablePUPDCfg
 |  | LL_PWR_IsEnabledPUPDCfg
 | E802A | LL_PWR_DisableIT_802A
 |  | LL_PWR_EnableIT_802A
 |  | LL_PWR_IsEnabledIT_802A
 | EBLEA | LL_PWR_DisableIT_BLEA
 |  | LL_PWR_EnableIT_BLEA
 |  | LL_PWR_IsEnabledIT_BLEA
 | EBORHSMPSFB | LL_PWR_DisableIT_BORH_SMPSFB
 |  | LL_PWR_EnableIT_BORH_SMPSFB
 |  | LL_PWR_IsEnabledIT_BORH_SMPSFB
 | EC2H | LL_PWR_DisableIT_HoldCPU2
 |  | LL_PWR_EnableIT_HoldCPU2
 |  | LL_PWR_IsEnabledIT_HoldCPU2
 | ECRPE | LL_PWR_DisableIT_802A
 |  | LL_PWR_EnableIT_802A
 |  | LL_PWR_IsEnabledIT_802A
 | EIWF | LL_PWR_DisableInternWU
 |  | LL_PWR_EnableInternWU
 |  | LL_PWR_IsEnabledInternWU
 | EWUP1 | LL_PWR_DisableWakeUpPin
 |  | LL_PWR_EnableWakeUpPin
 |  | LL_PWR_IsEnabledWakeUpPin
 | EWUP2 | LL_PWR_DisableWakeUpPin
 |  | LL_PWR_EnableWakeUpPin
 |  | LL_PWR_IsEnabledWakeUpPin
 | EWUP3 | LL_PWR_DisableWakeUpPin
 |  | LL_PWR_EnableWakeUpPin
 |  | LL_PWR_IsEnabledWakeUpPin
 | EWUP4 | LL_PWR_DisableWakeUpPin
 |  | LL_PWR_EnableWakeUpPin
 |  | LL_PWR_IsEnabledWakeUpPin
 | EWUP5 | LL_PWR_DisableWakeUpPin
 |  | LL_PWR_EnableWakeUpPin
 |  | LL_PWR_IsEnabledWakeUpPin
 | RRS | LL_PWR_DisableSRAM2Retention
 |  | LL_PWR_EnableSRAM2Retention
 |  | LL_PWR_IsEnabledSRAM2Retention
CR4 | C2BOOT | LL_PWR_DisableBootC2
 |  | LL_PWR_EnableBootC2
 |  | LL_PWR_IsEnabledBootC2
 | VBE | LL_PWR_DisableBatteryCharging
 |  | LL_PWR_EnableBatteryCharging
 |  | LL_PWR_IsEnabledBatteryCharging
 | VBRS | LL_PWR_GetBattChargResistor
 |  | LL_PWR_SetBattChargResistor
 | WP1 | LL_PWR_IsWakeUpPinPolarityLow
 |  | LL_PWR_SetWakeUpPinPolarityHigh
 |  | LL_PWR_SetWakeUpPinPolarityLow
 | WP2 | LL_PWR_IsWakeUpPinPolarityLow
 |  | LL_PWR_SetWakeUpPinPolarityHigh
 |  | LL_PWR_SetWakeUpPinPolarityLow
 | WP3 | LL_PWR_IsWakeUpPinPolarityLow
 |  | LL_PWR_SetWakeUpPinPolarityHigh
 |  | LL_PWR_SetWakeUpPinPolarityLow
 | WP4 | LL_PWR_IsWakeUpPinPolarityLow
 |  | LL_PWR_SetWakeUpPinPolarityHigh
 |  | LL_PWR_SetWakeUpPinPolarityLow
 | WP5 | LL_PWR_IsWakeUpPinPolarityLow
 |  | LL_PWR_SetWakeUpPinPolarityHigh
 |  | LL_PWR_SetWakeUpPinPolarityLow
CR5 | BORHC | LL_PWR_GetBORConfig
 |  | LL_PWR_SetBORConfig
 | SMPSBEN | LL_PWR_SMPS_GetMode
 |  | LL_PWR_SMPS_SetMode
 | SMPSEN | LL_PWR_SMPS_Disable
 |  | LL_PWR_SMPS_Enable
 |  | LL_PWR_SMPS_GetMode
 |  | LL_PWR_SMPS_IsEnabled
 |  | LL_PWR_SMPS_SetMode
 | SMPSSC | LL_PWR_SMPS_GetStartupCurrent
 |  | LL_PWR_SMPS_SetStartupCurrent
 | SMPSVOS | LL_PWR_SMPS_GetOutputVoltageLevel
 |  | LL_PWR_SMPS_SetOutputVoltageLevel
EXTSCR | C1CSSF | LL_PWR_ClearFlag_C1STOP_C1STB
 | C1DS | LL_PWR_IsActiveFlag_C1DS
 | C1SBF | LL_PWR_IsActiveFlag_C1SB
 | C1STOPF | LL_PWR_IsActiveFlag_C1STOP
 | C2CSSF | LL_PWR_ClearFlag_C2STOP_C2STB
 | C2DS | LL_PWR_IsActiveFlag_C2DS
 | C2SBF | LL_PWR_IsActiveFlag_C2SB
 | C2STOPF | LL_PWR_IsActiveFlag_C2STOP
 | CCRP | LL_PWR_ClearFlag_CRP
 | CRPF | LL_PWR_IsActiveFlag_CRP
PDCRA | PD0-15 | LL_PWR_DisableGPIOPullDown
 |  | LL_PWR_EnableGPIOPullDown
 |  | LL_PWR_IsEnabledGPIOPullDown
PDCRB | PD0-15 | LL_PWR_DisableGPIOPullDown
 |  | LL_PWR_EnableGPIOPullDown
 |  | LL_PWR_IsEnabledGPIOPullDown
PDCRC | PD0-15 | LL_PWR_DisableGPIOPullDown
 |  | LL_PWR_EnableGPIOPullDown
 |  | LL_PWR_IsEnabledGPIOPullDown
PDCRD | PD0-15 | LL_PWR_DisableGPIOPullDown
 |  | LL_PWR_EnableGPIOPullDown
 |  | LL_PWR_IsEnabledGPIOPullDown
PDCRE | PD0-15 | LL_PWR_DisableGPIOPullDown
 |  | LL_PWR_EnableGPIOPullDown
 |  | LL_PWR_IsEnabledGPIOPullDown
PDCRH | PD0-15 | LL_PWR_DisableGPIOPullDown
 |  | LL_PWR_EnableGPIOPullDown
 |  | LL_PWR_IsEnabledGPIOPullDown
PUCRA | PU0-15 | LL_PWR_DisableGPIOPullUp
 |  | LL_PWR_EnableGPIOPullUp
 |  | LL_PWR_IsEnabledGPIOPullUp
PUCRB | PU0-15 | LL_PWR_DisableGPIOPullUp
 |  | LL_PWR_EnableGPIOPullUp
 |  | LL_PWR_IsEnabledGPIOPullUp
PUCRC | PU0-15 | LL_PWR_DisableGPIOPullUp
 |  | LL_PWR_EnableGPIOPullUp
 |  | LL_PWR_IsEnabledGPIOPullUp
PUCRD | PU0-15 | LL_PWR_DisableGPIOPullUp
 |  | LL_PWR_EnableGPIOPullUp
 |  | LL_PWR_IsEnabledGPIOPullUp
PUCRE | PU0-15 | LL_PWR_DisableGPIOPullUp
 |  | LL_PWR_EnableGPIOPullUp
 |  | LL_PWR_IsEnabledGPIOPullUp
PUCRH | PU0-15 | LL_PWR_DisableGPIOPullUp
 |  | LL_PWR_EnableGPIOPullUp
 |  | LL_PWR_IsEnabledGPIOPullUp
SCR | 802AF | LL_PWR_ClearFlag_802A
 | 802WU | LL_PWR_ClearFlag_802WU
 | BLEAF | LL_PWR_ClearFlag_BLEA
 | BLEWU | LL_PWR_ClearFlag_BLEWU
 | CBORHF | LL_PWR_ClearFlag_BORH
 | CC2HF | LL_PWR_ClearFlag_C2H
 |  | LL_PWR_IsActiveFlag_C2H
 | CCRPEF | LL_PWR_ClearFlag_CRPE
 | CSMPSFBF | LL_PWR_ClearFlag_SMPSFB
 | CWUF | LL_PWR_ClearFlag_WU
 | CWUF1 | LL_PWR_ClearFlag_WU1
 | CWUF2 | LL_PWR_ClearFlag_WU2
 | CWUF3 | LL_PWR_ClearFlag_WU3
 | CWUF4 | LL_PWR_ClearFlag_WU4
 | CWUF5 | LL_PWR_ClearFlag_WU5
SR1 | 802AF | LL_PWR_IsActiveFlag_802A
 | 802WUF | LL_PWR_IsActiveFlag_802WU
 | BLEAF | LL_PWR_IsActiveFlag_BLEA
 | BLEWUF | LL_PWR_IsActiveFlag_BLEWU
 | BORHF | LL_PWR_IsActiveFlag_BORH
 | CRPEF | LL_PWR_IsActiveFlag_CRPE
 | SMPSFBF | LL_PWR_IsActiveFlag_SMPSFB
 | WUF1 | LL_PWR_IsActiveFlag_WU1
 | WUF2 | LL_PWR_IsActiveFlag_WU2
 | WUF3 | LL_PWR_IsActiveFlag_WU3
 | WUF4 | LL_PWR_IsActiveFlag_WU4
 | WUF5 | LL_PWR_IsActiveFlag_WU5
 | WUFI | LL_PWR_IsActiveFlag_InternWU
SR2 | PVDO | LL_PWR_IsActiveFlag_PVDO
 | PVMO1 | LL_PWR_IsActiveFlag_PVMO1
 | PVMO3 | LL_PWR_IsActiveFlag_PVMO3
 | REGLPF | LL_PWR_IsActiveFlag_REGLPF
 | REGLPS | LL_PWR_IsActiveFlag_REGLPS
 | SMPSBF | LL_PWR_SMPS_GetEffectiveMode
 | SMPSF | LL_PWR_SMPS_GetEffectiveMode
 | VOSF | LL_PWR_IsActiveFlag_VOS
Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PWR SMPS calibration

Defines
PWR SMPS calibration
PWR Private Constants

Defines

#define | SMPS_VOLTAGE_CAL_ADDR ((uint32_t*) (0x1FFF7558UL)) /* SMPS output voltage calibration level corresponding to voltage "SMPS_VOLTAGE_CAL_VOLTAGE_MV" */
#define | SMPS_VOLTAGE_CAL_POS (8UL) /* SMPS output voltage calibration level bitfield position */
#define | SMPS_VOLTAGE_CAL (0xFUL << SMPS_VOLTAGE_CAL_POS) /* SMPS output voltage calibration level bitfield mask */
#define | SMPS_VOLTAGE_CAL_VOLTAGE_MV (1500UL) /* SMPS output voltage calibration value (unit: mV) */
#define | SMPS_VOLTAGE_BASE_MV (1200UL) /* SMPS output voltage base value (unit: mV) */
#define | SMPS_VOLTAGE_STEP_MV ( 50UL) /* SMPS output voltage step (unit: mV) */

Define Documentation

#define SMPS_VOLTAGE_BASE_MV (1200UL) /* SMPS output voltage base value (unit: mV) */

Definition at line 57 of file stm32wbxx_ll_pwr.h.

#define SMPS_VOLTAGE_CAL (0xFUL << SMPS_VOLTAGE_CAL_POS) /* SMPS output voltage calibration level bitfield mask */

Definition at line 55 of file stm32wbxx_ll_pwr.h.

Referenced by HAL_PWREx_ConfigSMPS(), LL_PWR_SMPS_GetOutputVoltageLevel(), and LL_PWR_SMPS_SetOutputVoltageLevel().

#define SMPS_VOLTAGE_CAL_ADDR ((uint32_t*) (0x1FFF7558UL)) /* SMPS output voltage calibration level corresponding to voltage "SMPS_VOLTAGE_CAL_VOLTAGE_MV" */

Definition at line 53 of file stm32wbxx_ll_pwr.h.

#define SMPS_VOLTAGE_CAL_POS (8UL) /* SMPS output voltage calibration level bitfield position */

Definition at line 54 of file stm32wbxx_ll_pwr.h.

Referenced by HAL_PWREx_ConfigSMPS(), LL_PWR_SMPS_GetOutputVoltageLevel(), and LL_PWR_SMPS_SetOutputVoltageLevel().

#define SMPS_VOLTAGE_CAL_VOLTAGE_MV (1500UL) /* SMPS output voltage calibration value (unit: mV) */

Definition at line 56 of file stm32wbxx_ll_pwr.h.

#define SMPS_VOLTAGE_STEP_MV ( 50UL) /* SMPS output voltage step (unit: mV) */

Definition at line 58 of file stm32wbxx_ll_pwr.h.

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PWR Private Constants

Modules | Defines
PWR Private Constants
PWR

Modules

PWR SMPS calibration

Defines

#define | PWR_CR1_RESET_VALUE (0x00000200)
#define | PWR_CR2_RESET_VALUE (0x00000000)
#define | PWR_CR3_RESET_VALUE (0x00008000)
#define | PWR_CR4_RESET_VALUE (0x00000000)
#define | PWR_CR5_RESET_VALUE (0x00004272)
#define | PWR_PUCRA_RESET_VALUE (0x00000000)
#define | PWR_PDCRA_RESET_VALUE (0x00000000)
#define | PWR_PUCRB_RESET_VALUE (0x00000000)
#define | PWR_PDCRB_RESET_VALUE (0x00000000)
#define | PWR_PUCRC_RESET_VALUE (0x00000000)
#define | PWR_PDCRC_RESET_VALUE (0x00000000)
#define | PWR_PUCRD_RESET_VALUE (0x00000000)
#define | PWR_PDCRD_RESET_VALUE (0x00000000)
#define | PWR_PUCRE_RESET_VALUE (0x00000000)
#define | PWR_PDCRE_RESET_VALUE (0x00000000)
#define | PWR_PUCRH_RESET_VALUE (0x00000000)
#define | PWR_PDCRH_RESET_VALUE (0x00000000)
#define | PWR_C2CR1_RESET_VALUE (0x00000000)
#define | PWR_C2CR3_RESET_VALUE (0x00008000)

Define Documentation

#define PWR_C2CR1_RESET_VALUE (0x00000000)

Definition at line 60 of file stm32wbxx_ll_pwr.c.

Referenced by LL_PWR_DeInit().

#define PWR_C2CR3_RESET_VALUE (0x00008000)

Definition at line 61 of file stm32wbxx_ll_pwr.c.

Referenced by LL_PWR_DeInit().

#define PWR_CR1_RESET_VALUE (0x00000200)

Definition at line 43 of file stm32wbxx_ll_pwr.c.

Referenced by LL_PWR_DeInit().

#define PWR_CR2_RESET_VALUE (0x00000000)

Definition at line 44 of file stm32wbxx_ll_pwr.c.

Referenced by LL_PWR_DeInit().

#define PWR_CR3_RESET_VALUE (0x00008000)

Definition at line 45 of file stm32wbxx_ll_pwr.c.

Referenced by LL_PWR_DeInit().

#define PWR_CR4_RESET_VALUE (0x00000000)

Definition at line 46 of file stm32wbxx_ll_pwr.c.

Referenced by LL_PWR_DeInit().

#define PWR_CR5_RESET_VALUE (0x00004272)

Definition at line 47 of file stm32wbxx_ll_pwr.c.

Referenced by LL_PWR_DeInit().

#define PWR_PDCRA_RESET_VALUE (0x00000000)

Definition at line 49 of file stm32wbxx_ll_pwr.c.

Referenced by LL_PWR_DeInit().

#define PWR_PDCRB_RESET_VALUE (0x00000000)

Definition at line 51 of file stm32wbxx_ll_pwr.c.

Referenced by LL_PWR_DeInit().

#define PWR_PDCRC_RESET_VALUE (0x00000000)

Definition at line 53 of file stm32wbxx_ll_pwr.c.

Referenced by LL_PWR_DeInit().

#define PWR_PDCRD_RESET_VALUE (0x00000000)

Definition at line 55 of file stm32wbxx_ll_pwr.c.

Referenced by LL_PWR_DeInit().

#define PWR_PDCRE_RESET_VALUE (0x00000000)

Definition at line 57 of file stm32wbxx_ll_pwr.c.

Referenced by LL_PWR_DeInit().

#define PWR_PDCRH_RESET_VALUE (0x00000000)

Definition at line 59 of file stm32wbxx_ll_pwr.c.

Referenced by LL_PWR_DeInit().

#define PWR_PUCRA_RESET_VALUE (0x00000000)

Definition at line 48 of file stm32wbxx_ll_pwr.c.

Referenced by LL_PWR_DeInit().

#define PWR_PUCRB_RESET_VALUE (0x00000000)

Definition at line 50 of file stm32wbxx_ll_pwr.c.

Referenced by LL_PWR_DeInit().

#define PWR_PUCRC_RESET_VALUE (0x00000000)

Definition at line 52 of file stm32wbxx_ll_pwr.c.

Referenced by LL_PWR_DeInit().

#define PWR_PUCRD_RESET_VALUE (0x00000000)

Definition at line 54 of file stm32wbxx_ll_pwr.c.

Referenced by LL_PWR_DeInit().

#define PWR_PUCRE_RESET_VALUE (0x00000000)

Definition at line 56 of file stm32wbxx_ll_pwr.c.

Referenced by LL_PWR_DeInit().

#define PWR_PUCRH_RESET_VALUE (0x00000000)

Definition at line 58 of file stm32wbxx_ll_pwr.c.

Referenced by LL_PWR_DeInit().

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
PWR Exported Constants

Flags defines which can be used with LL_PWR_WriteReg function. More...

Defines

#define | LL_PWR_SCR_CWUF PWR_SCR_CWUF
#define | LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5
#define | LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4
#define | LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3
#define | LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2
#define | LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1
#define | LL_PWR_SCR_CC2HF PWR_SCR_CC2HF
#define | LL_PWR_SCR_C802AF PWR_SCR_C802AF
#define | LL_PWR_SCR_CBLEAF PWR_SCR_CBLEAF
#define | LL_PWR_SCR_CCRPEF PWR_SCR_CCRPEF
#define | LL_PWR_SCR_C802WUF PWR_SCR_C802WUF
#define | LL_PWR_SCR_CBLEWUF PWR_SCR_CBLEWUF
#define | LL_PWR_SCR_CBORHF PWR_SCR_CBORHF
#define | LL_PWR_SCR_CSMPSFBF PWR_SCR_CSMPSFBF
#define | LL_PWR_EXTSCR_CCRPF PWR_EXTSCR_CCRPF
#define | LL_PWR_EXTSCR_C2CSSF PWR_EXTSCR_C2CSSF
#define | LL_PWR_EXTSCR_C1CSSF PWR_EXTSCR_C1CSSF

Detailed Description

Flags defines which can be used with LL_PWR_WriteReg function.

Define Documentation

#define LL_PWR_EXTSCR_C1CSSF PWR_EXTSCR_C1CSSF

Definition at line 104 of file stm32wbxx_ll_pwr.h.

Referenced by HAL_PWR_DeInit(), and LL_PWR_DeInit().

#define LL_PWR_EXTSCR_C2CSSF PWR_EXTSCR_C2CSSF

Definition at line 103 of file stm32wbxx_ll_pwr.h.

Referenced by HAL_PWR_DeInit(), and LL_PWR_DeInit().

#define LL_PWR_EXTSCR_CCRPF PWR_EXTSCR_CCRPF

Definition at line 102 of file stm32wbxx_ll_pwr.h.

Referenced by HAL_PWR_DeInit(), and LL_PWR_DeInit().

#define LL_PWR_SCR_C802AF PWR_SCR_C802AF

Definition at line 93 of file stm32wbxx_ll_pwr.h.

Referenced by HAL_PWR_DeInit(), and LL_PWR_DeInit().

#define LL_PWR_SCR_C802WUF PWR_SCR_C802WUF

Definition at line 96 of file stm32wbxx_ll_pwr.h.

Referenced by HAL_PWR_DeInit(), and LL_PWR_DeInit().

#define LL_PWR_SCR_CBLEAF PWR_SCR_CBLEAF

Definition at line 94 of file stm32wbxx_ll_pwr.h.

Referenced by HAL_PWR_DeInit(), and LL_PWR_DeInit().

#define LL_PWR_SCR_CBLEWUF PWR_SCR_CBLEWUF

Definition at line 97 of file stm32wbxx_ll_pwr.h.

Referenced by HAL_PWR_DeInit(), and LL_PWR_DeInit().

#define LL_PWR_SCR_CBORHF PWR_SCR_CBORHF

Definition at line 99 of file stm32wbxx_ll_pwr.h.

Referenced by HAL_PWR_DeInit(), and LL_PWR_DeInit().

#define LL_PWR_SCR_CC2HF PWR_SCR_CC2HF

Definition at line 92 of file stm32wbxx_ll_pwr.h.

Referenced by HAL_PWR_DeInit(), and LL_PWR_DeInit().

#define LL_PWR_SCR_CCRPEF PWR_SCR_CCRPEF

Definition at line 95 of file stm32wbxx_ll_pwr.h.

Referenced by HAL_PWR_DeInit(), and LL_PWR_DeInit().

#define LL_PWR_SCR_CSMPSFBF PWR_SCR_CSMPSFBF

Definition at line 100 of file stm32wbxx_ll_pwr.h.

Referenced by HAL_PWR_DeInit(), and LL_PWR_DeInit().

#define LL_PWR_SCR_CWUF PWR_SCR_CWUF

Definition at line 80 of file stm32wbxx_ll_pwr.h.

Referenced by HAL_PWR_DeInit(), and LL_PWR_DeInit().

#define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1

Definition at line 91 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2

Definition at line 89 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3

Definition at line 86 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4

Definition at line 84 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5

Definition at line 82 of file stm32wbxx_ll_pwr.h.

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
PWR Exported Constants

Flags defines which can be used with LL_PWR_ReadReg function. More...

Defines

#define | LL_PWR_SR1_WUFI PWR_SR1_WUFI
#define | LL_PWR_SR1_WUF5 PWR_SR1_WUF5
#define | LL_PWR_SR1_WUF4 PWR_SR1_WUF4
#define | LL_PWR_SR1_WUF3 PWR_SR1_WUF3
#define | LL_PWR_SR1_WUF2 PWR_SR1_WUF2
#define | LL_PWR_SR1_WUF1 PWR_SR1_WUF1
#define | LL_PWR_SR2_PVMO3 PWR_SR2_PVMO3
#define | LL_PWR_SR2_PVMO1 PWR_SR2_PVMO1
#define | LL_PWR_SR2_PVDO PWR_SR2_PVDO
#define | LL_PWR_SR2_VOSF PWR_SR2_VOSF
#define | LL_PWR_SR2_REGLPF PWR_SR2_REGLPF
#define | LL_PWR_SR2_REGLPS PWR_SR2_REGLPS
#define | LL_PWR_FLAG_BORH PWR_SR1_BORHF /* BORH interrupt flag */
#define | LL_PWR_FLAG_SMPS PWR_SR2_SMPSF /* SMPS step down converter ready flag */
#define | LL_PWR_FLAG_SMPSB PWR_SR2_SMPSBF /* SMPS step down converter in bypass mode flag */
#define | LL_PWR_FLAG_SMPSFB PWR_SR1_SMPSFB /* SMPS step down converter forced in bypass mode interrupt flag */
#define | LL_PWR_FLAG_BLEWU PWR_SR1_BLEWUF /* BLE wakeup interrupt flag */
#define | LL_PWR_FLAG_802WU PWR_SR1_802WUF /* 802.15.4 wakeup interrupt flag */
#define | LL_PWR_FLAG_BLEA PWR_SR1_BLEAF /* BLE end of activity interrupt flag */
#define | LL_PWR_FLAG_802A PWR_SR1_802AF /* 802.15.4 end of activity interrupt flag */
#define | LL_PWR_FLAG_CRPE PWR_SR1_CRPEF /* Critical radio phase end of activity interrupt flag */
#define | LL_PWR_FLAG_CRP PWR_EXTSCR_CRPF /* Critical radio system phase */
#define | LL_PWR_EXTSCR_C1SBF PWR_EXTSCR_C1SBF /* System standby flag for CPU1 */
#define | LL_PWR_EXTSCR_C1STOPF PWR_EXTSCR_C1STOPF /* System stop flag for CPU1 */
#define | LL_PWR_EXTSCR_C1DS PWR_EXTSCR_C1DS /* CPU1 deepsleep mode */
#define | LL_PWR_EXTSCR_C2SBF PWR_EXTSCR_C2SBF /* System standby flag for CPU2 */
#define | LL_PWR_EXTSCR_C2STOPF PWR_EXTSCR_C2STOPF /* System stop flag for CPU2 */
#define | LL_PWR_EXTSCR_C2DS PWR_EXTSCR_C2DS /* CPU2 deepsleep mode */
#define | LL_PWR_SR1_C2HF PWR_SR1_C2HF /* CPU2 hold interrupt flag */

Detailed Description

Flags defines which can be used with LL_PWR_ReadReg function.

Define Documentation

#define LL_PWR_EXTSCR_C1DS PWR_EXTSCR_C1DS /* CPU1 deepsleep mode */

Definition at line 157 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_EXTSCR_C1SBF PWR_EXTSCR_C1SBF /* System standby flag for CPU1 */

Definition at line 155 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_EXTSCR_C1STOPF PWR_EXTSCR_C1STOPF /* System stop flag for CPU1 */

Definition at line 156 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_EXTSCR_C2DS PWR_EXTSCR_C2DS /* CPU2 deepsleep mode */

Definition at line 160 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_EXTSCR_C2SBF PWR_EXTSCR_C2SBF /* System standby flag for CPU2 */

Definition at line 158 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_EXTSCR_C2STOPF PWR_EXTSCR_C2STOPF /* System stop flag for CPU2 */

Definition at line 159 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_FLAG_802A PWR_SR1_802AF /* 802.15.4 end of activity interrupt flag */

Definition at line 150 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_FLAG_802WU PWR_SR1_802WUF /* 802.15.4 wakeup interrupt flag */

Definition at line 148 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_FLAG_BLEA PWR_SR1_BLEAF /* BLE end of activity interrupt flag */

Definition at line 149 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_FLAG_BLEWU PWR_SR1_BLEWUF /* BLE wakeup interrupt flag */

Definition at line 147 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_FLAG_BORH PWR_SR1_BORHF /* BORH interrupt flag */

Definition at line 137 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_FLAG_CRP PWR_EXTSCR_CRPF /* Critical radio system phase */

Definition at line 152 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_FLAG_CRPE PWR_SR1_CRPEF /* Critical radio phase end of activity interrupt flag */

Definition at line 151 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_FLAG_SMPS PWR_SR2_SMPSF /* SMPS step down converter ready flag */

Definition at line 141 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_FLAG_SMPSB PWR_SR2_SMPSBF /* SMPS step down converter in bypass mode flag */

Definition at line 142 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_FLAG_SMPSFB PWR_SR1_SMPSFB /* SMPS step down converter forced in bypass mode interrupt flag */

Definition at line 143 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_SR1_C2HF PWR_SR1_C2HF /* CPU2 hold interrupt flag */

Definition at line 161 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_SR1_WUF1 PWR_SR1_WUF1

Definition at line 124 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_SR1_WUF2 PWR_SR1_WUF2

Definition at line 122 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_SR1_WUF3 PWR_SR1_WUF3

Definition at line 119 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_SR1_WUF4 PWR_SR1_WUF4

Definition at line 117 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_SR1_WUF5 PWR_SR1_WUF5

Definition at line 115 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_SR1_WUFI PWR_SR1_WUFI

Definition at line 113 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_SR2_PVDO PWR_SR2_PVDO

Definition at line 129 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_SR2_PVMO1 PWR_SR2_PVMO1

Definition at line 127 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_SR2_PVMO3 PWR_SR2_PVMO3

Definition at line 125 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_SR2_REGLPF PWR_SR2_REGLPF

Definition at line 133 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_SR2_REGLPS PWR_SR2_REGLPS

Definition at line 134 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_SR2_VOSF PWR_SR2_VOSF

Definition at line 131 of file stm32wbxx_ll_pwr.h.

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STM32WB55xx HAL User Manual: REGU VOLTAGE

Defines
REGU VOLTAGE
PWR Exported Constants

Defines

#define | LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR1_VOS_0) /* Regulator voltage output range 1 mode, typical output voltage at 1.2 V, system frequency up to 64 MHz. */
#define | LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR1_VOS_1) /* Regulator voltage output range 2 mode, typical output voltage at 1.0 V, system frequency up to 16 MHz. */

Define Documentation

#define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR1_VOS_0) /* Regulator voltage output range 1 mode, typical output voltage at 1.2 V, system frequency up to 64 MHz. */

Definition at line 170 of file stm32wbxx_ll_pwr.h.

Referenced by UTILS_SetFlashLatency().

#define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR1_VOS_1) /* Regulator voltage output range 2 mode, typical output voltage at 1.0 V, system frequency up to 16 MHz. */

Definition at line 171 of file stm32wbxx_ll_pwr.h.

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STM32WB55xx HAL User Manual: MODE PWR

Defines
MODE PWR
PWR Exported Constants

Defines

#define | LL_PWR_MODE_STOP0 (0x000000000U)
#define | LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_0)
#define | LL_PWR_MODE_STOP2 (PWR_CR1_LPMS_1)
#define | LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_1 | PWR_CR1_LPMS_0)
#define | LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_2)

Define Documentation

#define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_2)

Definition at line 184 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_1 | PWR_CR1_LPMS_0)

Definition at line 183 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_MODE_STOP0 (0x000000000U)

Definition at line 180 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_0)

Definition at line 181 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_MODE_STOP2 (PWR_CR1_LPMS_1)

Definition at line 182 of file stm32wbxx_ll_pwr.h.

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STM32WB55xx HAL User Manual: Flash power-down mode during low-power run mode

Defines
Flash power-down mode during low-power run mode
PWR Exported Constants

Defines

#define | LL_PWR_FLASH_LPRUN_MODE_IDLE (0x000000000U)
#define | LL_PWR_FLASH_LPRUN_MODE_POWER_DOWN (PWR_CR1_FPDR)

Define Documentation

#define LL_PWR_FLASH_LPRUN_MODE_IDLE (0x000000000U)

Definition at line 192 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_FLASH_LPRUN_MODE_POWER_DOWN (PWR_CR1_FPDR)

Definition at line 193 of file stm32wbxx_ll_pwr.h.

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STM32WB55xx HAL User Manual: Flash power-down mode during sleep mode

Defines
Flash power-down mode during sleep mode
PWR Exported Constants

Defines

#define | LL_PWR_FLASH_SLEEP_MODE_IDLE (0x000000000U)
#define | LL_PWR_FLASH_SLEEP_MODE_POWER_DOWN (PWR_CR1_FPDS)

Define Documentation

#define LL_PWR_FLASH_SLEEP_MODE_IDLE (0x000000000U)

Definition at line 201 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_FLASH_SLEEP_MODE_POWER_DOWN (PWR_CR1_FPDS)

Definition at line 202 of file stm32wbxx_ll_pwr.h.

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STM32WB55xx HAL User Manual: Peripheral voltage monitoring

Defines
Peripheral voltage monitoring
PWR Exported Constants

Defines

#define | LL_PWR_PVM_VDDUSB_1_2V (PWR_CR2_PVME1) /* Monitoring VDDUSB vs. 1.2V */
#define | LL_PWR_PVM_VDDA_1_62V (PWR_CR2_PVME3) /* Monitoring VDDA vs. 1.62V */

Define Documentation

#define LL_PWR_PVM_VDDA_1_62V (PWR_CR2_PVME3) /* Monitoring VDDA vs. 1.62V */

Definition at line 213 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_PVM_VDDUSB_1_2V (PWR_CR2_PVME1) /* Monitoring VDDUSB vs. 1.2V */

Definition at line 211 of file stm32wbxx_ll_pwr.h.

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STM32WB55xx HAL User Manual: PVDLEVEL

Defines
PVDLEVEL
PWR Exported Constants

Defines

#define | LL_PWR_PVDLEVEL_0 (0x00000000U) /* VPVD0 around 2.0 V */
#define | LL_PWR_PVDLEVEL_1 (PWR_CR2_PLS_0) /* VPVD1 around 2.2 V */
#define | LL_PWR_PVDLEVEL_2 (PWR_CR2_PLS_1) /* VPVD2 around 2.4 V */
#define | LL_PWR_PVDLEVEL_3 (PWR_CR2_PLS_1 | PWR_CR2_PLS_0) /* VPVD3 around 2.5 V */
#define | LL_PWR_PVDLEVEL_4 (PWR_CR2_PLS_2) /* VPVD4 around 2.6 V */
#define | LL_PWR_PVDLEVEL_5 (PWR_CR2_PLS_2 | PWR_CR2_PLS_0) /* VPVD5 around 2.8 V */
#define | LL_PWR_PVDLEVEL_6 (PWR_CR2_PLS_2 | PWR_CR2_PLS_1) /* VPVD6 around 2.9 V */
#define | LL_PWR_PVDLEVEL_7 (PWR_CR2_PLS_2 | PWR_CR2_PLS_1 | PWR_CR2_PLS_0) /* External input analog voltage (Compare internally to VREFINT) */

Define Documentation

#define LL_PWR_PVDLEVEL_0 (0x00000000U) /* VPVD0 around 2.0 V */

Definition at line 221 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_1 (PWR_CR2_PLS_0) /* VPVD1 around 2.2 V */

Definition at line 222 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_2 (PWR_CR2_PLS_1) /* VPVD2 around 2.4 V */

Definition at line 223 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_3 (PWR_CR2_PLS_1 | PWR_CR2_PLS_0) /* VPVD3 around 2.5 V */

Definition at line 224 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_4 (PWR_CR2_PLS_2) /* VPVD4 around 2.6 V */

Definition at line 225 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_5 (PWR_CR2_PLS_2 | PWR_CR2_PLS_0) /* VPVD5 around 2.8 V */

Definition at line 226 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_6 (PWR_CR2_PLS_2 | PWR_CR2_PLS_1) /* VPVD6 around 2.9 V */

Definition at line 227 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_7 (PWR_CR2_PLS_2 | PWR_CR2_PLS_1 | PWR_CR2_PLS_0) /* External input analog voltage (Compare internally to VREFINT) */

Definition at line 228 of file stm32wbxx_ll_pwr.h.

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STM32WB55xx HAL User Manual: WAKEUP

Defines
WAKEUP
PWR Exported Constants

Defines

#define | LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1)
#define | LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2)
#define | LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3)
#define | LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4)
#define | LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5)

Define Documentation

#define LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1)

Definition at line 236 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2)

Definition at line 238 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3)

Definition at line 241 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4)

Definition at line 243 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5)

Definition at line 245 of file stm32wbxx_ll_pwr.h.

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STM32WB55xx HAL User Manual: BATT CHARG RESISTOR

Defines
BATT CHARG RESISTOR
PWR Exported Constants

Defines

#define | LL_PWR_BATT_CHARG_RESISTOR_5K (0x00000000U)
#define | LL_PWR_BATT_CHARGRESISTOR_1_5K (PWR_CR4_VBRS)

Define Documentation

#define LL_PWR_BATT_CHARG_RESISTOR_5K (0x00000000U)

Definition at line 254 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_BATT_CHARGRESISTOR_1_5K (PWR_CR4_VBRS)

Definition at line 255 of file stm32wbxx_ll_pwr.h.

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STM32WB55xx HAL User Manual: GPIO

Defines
GPIO
PWR Exported Constants

Defines

#define | LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA)))
#define | LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))
#define | LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC)))
#define | LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD)))
#define | LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE)))
#define | LL_PWR_GPIO_H ((uint32_t)(&(PWR->PUCRH)))

Define Documentation

#define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA)))

Definition at line 263 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))

Definition at line 264 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC)))

Definition at line 265 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD)))

Definition at line 266 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE)))

Definition at line 267 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_GPIO_H ((uint32_t)(&(PWR->PUCRH)))

Definition at line 268 of file stm32wbxx_ll_pwr.h.

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STM32WB55xx HAL User Manual: GPIO BIT

Defines
GPIO BIT
PWR Exported Constants

Defines

#define | LL_PWR_GPIO_BIT_0 (PWR_PUCRC_PC0)
#define | LL_PWR_GPIO_BIT_1 (PWR_PUCRC_PC1)
#define | LL_PWR_GPIO_BIT_2 (PWR_PUCRC_PC2)
#define | LL_PWR_GPIO_BIT_3 (PWR_PUCRC_PC3)
#define | LL_PWR_GPIO_BIT_4 (PWR_PUCRC_PC4)
#define | LL_PWR_GPIO_BIT_5 (PWR_PUCRC_PC5)
#define | LL_PWR_GPIO_BIT_6 (PWR_PUCRC_PC6)
#define | LL_PWR_GPIO_BIT_7 (PWR_PUCRC_PC7)
#define | LL_PWR_GPIO_BIT_8 (PWR_PUCRC_PC8)
#define | LL_PWR_GPIO_BIT_9 (PWR_PUCRC_PC9)
#define | LL_PWR_GPIO_BIT_10 (PWR_PUCRC_PC10)
#define | LL_PWR_GPIO_BIT_11 (PWR_PUCRC_PC11)
#define | LL_PWR_GPIO_BIT_12 (PWR_PUCRC_PC12)
#define | LL_PWR_GPIO_BIT_13 (PWR_PUCRC_PC13)
#define | LL_PWR_GPIO_BIT_14 (PWR_PUCRC_PC14)
#define | LL_PWR_GPIO_BIT_15 (PWR_PUCRC_PC15)

Define Documentation

#define LL_PWR_GPIO_BIT_0 (PWR_PUCRC_PC0)

Definition at line 279 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_1 (PWR_PUCRC_PC1)

Definition at line 280 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_10 (PWR_PUCRC_PC10)

Definition at line 289 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_11 (PWR_PUCRC_PC11)

Definition at line 290 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_12 (PWR_PUCRC_PC12)

Definition at line 291 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_13 (PWR_PUCRC_PC13)

Definition at line 292 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_14 (PWR_PUCRC_PC14)

Definition at line 293 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_15 (PWR_PUCRC_PC15)

Definition at line 294 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_2 (PWR_PUCRC_PC2)

Definition at line 281 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_3 (PWR_PUCRC_PC3)

Definition at line 282 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_4 (PWR_PUCRC_PC4)

Definition at line 283 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_5 (PWR_PUCRC_PC5)

Definition at line 284 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_6 (PWR_PUCRC_PC6)

Definition at line 285 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_7 (PWR_PUCRC_PC7)

Definition at line 286 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_8 (PWR_PUCRC_PC8)

Definition at line 287 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_GPIO_BIT_9 (PWR_PUCRC_PC9)

Definition at line 288 of file stm32wbxx_ll_pwr.h.

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STM32WB55xx HAL User Manual: BOR configuration

Defines
BOR configuration
PWR Exported Constants

Defines

#define | LL_PWR_BOR_SYSTEM_RESET (0x00000000U)
#define | LL_PWR_BOR_SMPS_FORCE_BYPASS (PWR_CR5_BORHC)

Define Documentation

#define LL_PWR_BOR_SMPS_FORCE_BYPASS (PWR_CR5_BORHC)

BOR will for SMPS step down converter in bypass mode

Definition at line 322 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_BOR_SYSTEM_RESET (0x00000000U)

BOR will generate a system reset

Definition at line 321 of file stm32wbxx_ll_pwr.h.

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STM32WB55xx HAL User Manual: SMPS step down converter operating modes

Defines
SMPS step down converter operating modes
PWR Exported Constants

Defines

#define | LL_PWR_SMPS_BYPASS (PWR_SR2_SMPSBF)
#define | LL_PWR_SMPS_STEP_DOWN (PWR_SR2_SMPSF)

Define Documentation

#define LL_PWR_SMPS_BYPASS (PWR_SR2_SMPSBF)

SMPS step down in bypass mode.

Definition at line 336 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_SMPS_STEP_DOWN (PWR_SR2_SMPSF)

SMPS step down in step down mode if system low power mode is run, LP run or stop0. If system low power mode is stop1, stop2, standby, shutdown, then SMPS is forced in mode open to preserve energy stored in decoupling capacitor as long as possible.

Definition at line 337 of file stm32wbxx_ll_pwr.h.

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STM32WB55xx HAL User Manual: SMPS step down converter supply startup current selection

Defines
SMPS step down converter supply startup current selection
PWR Exported Constants

Defines

#define | LL_PWR_SMPS_STARTUP_CURRENT_80MA (0x00000000U)
#define | LL_PWR_SMPS_STARTUP_CURRENT_100MA ( PWR_CR5_SMPSSC_0)
#define | LL_PWR_SMPS_STARTUP_CURRENT_120MA ( PWR_CR5_SMPSSC_1 )
#define | LL_PWR_SMPS_STARTUP_CURRENT_140MA ( PWR_CR5_SMPSSC_1 | PWR_CR5_SMPSSC_0)
#define | LL_PWR_SMPS_STARTUP_CURRENT_160MA (PWR_CR5_SMPSSC_2 )
#define | LL_PWR_SMPS_STARTUP_CURRENT_180MA (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_0)
#define | LL_PWR_SMPS_STARTUP_CURRENT_200MA (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_1 )
#define | LL_PWR_SMPS_STARTUP_CURRENT_220MA (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_1 | PWR_CR5_SMPSSC_0)

Define Documentation

#define LL_PWR_SMPS_STARTUP_CURRENT_100MA ( PWR_CR5_SMPSSC_0)

SMPS step down converter supply startup current 100mA

Definition at line 346 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_SMPS_STARTUP_CURRENT_120MA ( PWR_CR5_SMPSSC_1 )

SMPS step down converter supply startup current 120mA

Definition at line 347 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_SMPS_STARTUP_CURRENT_140MA ( PWR_CR5_SMPSSC_1 | PWR_CR5_SMPSSC_0)

SMPS step down converter supply startup current 140mA

Definition at line 348 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_SMPS_STARTUP_CURRENT_160MA (PWR_CR5_SMPSSC_2 )

SMPS step down converter supply startup current 160mA

Definition at line 349 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_SMPS_STARTUP_CURRENT_180MA (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_0)

SMPS step down converter supply startup current 180mA

Definition at line 350 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_SMPS_STARTUP_CURRENT_200MA (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_1 )

SMPS step down converter supply startup current 200mA

Definition at line 351 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_SMPS_STARTUP_CURRENT_220MA (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_1 | PWR_CR5_SMPSSC_0)

SMPS step down converter supply startup current 220mA

Definition at line 352 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_SMPS_STARTUP_CURRENT_80MA (0x00000000U)

SMPS step down converter supply startup current 80mA

Definition at line 345 of file stm32wbxx_ll_pwr.h.

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STM32WB55xx HAL User Manual: SMPS step down converter output voltage scaling voltage level

Defines
SMPS step down converter output voltage scaling voltage level
PWR Exported Constants

Defines

#define | LL_PWR_SMPS_OUTPUT_VOLTAGE_1V20 (0x00000000U)
#define | LL_PWR_SMPS_OUTPUT_VOLTAGE_1V25 ( PWR_CR5_SMPSVOS_0)
#define | LL_PWR_SMPS_OUTPUT_VOLTAGE_1V30 ( PWR_CR5_SMPSVOS_1 )
#define | LL_PWR_SMPS_OUTPUT_VOLTAGE_1V35 ( PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0)
#define | LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40 ( PWR_CR5_SMPSVOS_2 )
#define | LL_PWR_SMPS_OUTPUT_VOLTAGE_1V45 ( PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_0)
#define | LL_PWR_SMPS_OUTPUT_VOLTAGE_1V50 ( PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1 )
#define | LL_PWR_SMPS_OUTPUT_VOLTAGE_1V55 ( PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0)
#define | LL_PWR_SMPS_OUTPUT_VOLTAGE_1V60 (PWR_CR5_SMPSVOS_3 )
#define | LL_PWR_SMPS_OUTPUT_VOLTAGE_1V65 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_0)
#define | LL_PWR_SMPS_OUTPUT_VOLTAGE_1V70 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_1 )
#define | LL_PWR_SMPS_OUTPUT_VOLTAGE_1V75 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0)
#define | LL_PWR_SMPS_OUTPUT_VOLTAGE_1V80 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 )
#define | LL_PWR_SMPS_OUTPUT_VOLTAGE_1V85 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_0)
#define | LL_PWR_SMPS_OUTPUT_VOLTAGE_1V90 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1 )

Define Documentation

#define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V20 (0x00000000U)

SMPS step down converter supply output voltage 1.20V

Definition at line 362 of file stm32wbxx_ll_pwr.h.

Referenced by LL_PWR_SMPS_GetOutputVoltageLevel().

#define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V25 ( PWR_CR5_SMPSVOS_0)

SMPS step down converter supply output voltage 1.25V

Definition at line 363 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V30 ( PWR_CR5_SMPSVOS_1 )

SMPS step down converter supply output voltage 1.30V

Definition at line 364 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V35 ( PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0)

SMPS step down converter supply output voltage 1.35V

Definition at line 365 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40 ( PWR_CR5_SMPSVOS_2 )

SMPS step down converter supply output voltage 1.40V

Definition at line 366 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V45 ( PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_0)

SMPS step down converter supply output voltage 1.45V

Definition at line 367 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V50 ( PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1 )

SMPS step down converter supply output voltage 1.50V

Definition at line 368 of file stm32wbxx_ll_pwr.h.

Referenced by HAL_PWREx_ConfigSMPS(), LL_PWR_SMPS_GetOutputVoltageLevel(), and LL_PWR_SMPS_SetOutputVoltageLevel().

#define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V55 ( PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0)

SMPS step down converter supply output voltage 1.55V

Definition at line 369 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V60 (PWR_CR5_SMPSVOS_3 )

SMPS step down converter supply output voltage 1.60V

Definition at line 370 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V65 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_0)

SMPS step down converter supply output voltage 1.65V

Definition at line 371 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V70 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_1 )

SMPS step down converter supply output voltage 1.70V

Definition at line 372 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V75 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0)

SMPS step down converter supply output voltage 1.75V

Definition at line 373 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V80 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 )

SMPS step down converter supply output voltage 1.80V

Definition at line 374 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V85 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_0)

SMPS step down converter supply output voltage 1.85V

Definition at line 375 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V90 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1 )

SMPS step down converter supply output voltage 1.90V

Definition at line 376 of file stm32wbxx_ll_pwr.h.

Referenced by LL_PWR_SMPS_GetOutputVoltageLevel().

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
PWR Exported Macros

Defines

#define | LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
Write a value in PWR register.
#define | LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
Read a value in PWR register.

Define Documentation

#define LL_PWR_ReadReg ( __REG__ ) READ_REG(PWR->__REG__)

Read a value in PWR register.

Parameters:
__REG__ Register to be read
Return values:
Register value

Definition at line 408 of file stm32wbxx_ll_pwr.h.

#define LL_PWR_WriteReg | ( | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(PWR->__REG__, (__VALUE__))

Write a value in PWR register.

Parameters:
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 401 of file stm32wbxx_ll_pwr.h.

Referenced by HAL_PWR_DeInit(), and LL_PWR_DeInit().

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Configuration

Functions
Configuration
PWR Exported Functions

Functions

__STATIC_INLINE void | LL_PWR_EnterLowPowerRunMode (void)
Switch from run main mode to run low-power mode.
__STATIC_INLINE void | LL_PWR_ExitLowPowerRunMode (void)
Switch from run main mode to low-power mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledLowPowerRunMode (void)
Check if the regulator is in low-power mode.
__STATIC_INLINE void | LL_PWR_SetRegulVoltageScaling (uint32_t VoltageScaling)
Set the main internal regulator output voltage.
__STATIC_INLINE uint32_t | LL_PWR_GetRegulVoltageScaling (void)
Get the main internal regulator output voltage.
__STATIC_INLINE void | LL_PWR_EnableBkUpAccess (void)
Enable access to the backup domain.
__STATIC_INLINE void | LL_PWR_DisableBkUpAccess (void)
Disable access to the backup domain.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledBkUpAccess (void)
Check if the backup domain is enabled.
__STATIC_INLINE void | LL_PWR_SetPowerMode (uint32_t LowPowerMode)
Set Low-Power mode.
__STATIC_INLINE uint32_t | LL_PWR_GetPowerMode (void)
Get Low-Power mode.
__STATIC_INLINE void | LL_PWR_SetFlashPowerModeLPRun (uint32_t FlashLowPowerMode)
Set flash power-down mode during low-power run mode.
__STATIC_INLINE uint32_t | LL_PWR_GetFlashPowerModeLPRun (void)
Get flash power-down mode during low-power run mode.
__STATIC_INLINE void | LL_PWR_SetFlashPowerModeSleep (uint32_t FlashLowPowerMode)
Set flash power-down mode during sleep mode.
__STATIC_INLINE uint32_t | LL_PWR_GetFlashPowerModeSleep (void)
Get flash power-down mode during sleep mode.
__STATIC_INLINE void | LL_PWR_EnableVddUSB (void)
Enable VDDUSB supply.
__STATIC_INLINE void | LL_PWR_DisableVddUSB (void)
Disable VDDUSB supply.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledVddUSB (void)
Check if VDDUSB supply is enabled.
__STATIC_INLINE void | LL_PWR_EnablePVM (uint32_t PeriphVoltage)
Enable the Power Voltage Monitoring on a peripheral.
__STATIC_INLINE void | LL_PWR_DisablePVM (uint32_t PeriphVoltage)
Disable the Power Voltage Monitoring on a peripheral.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledPVM (uint32_t PeriphVoltage)
Check if Power Voltage Monitoring is enabled on a peripheral.
__STATIC_INLINE void | LL_PWR_SetPVDLevel (uint32_t PVDLevel)
Configure the voltage threshold detected by the Power Voltage Detector.
__STATIC_INLINE uint32_t | LL_PWR_GetPVDLevel (void)
Get the voltage threshold detection.
__STATIC_INLINE void | LL_PWR_EnablePVD (void)
Enable Power Voltage Detector.
__STATIC_INLINE void | LL_PWR_DisablePVD (void)
Disable Power Voltage Detector.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledPVD (void)
Check if Power Voltage Detector is enabled.
__STATIC_INLINE void | LL_PWR_EnableInternWU (void)
Enable Internal Wake-up line.
__STATIC_INLINE void | LL_PWR_DisableInternWU (void)
Disable Internal Wake-up line.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledInternWU (void)
Check if Internal Wake-up line is enabled.
__STATIC_INLINE void | LL_PWR_EnablePUPDCfg (void)
Enable pull-up and pull-down configuration.
__STATIC_INLINE void | LL_PWR_DisablePUPDCfg (void)
Disable pull-up and pull-down configuration.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledPUPDCfg (void)
Check if pull-up and pull-down configuration is enabled.
__STATIC_INLINE void | LL_PWR_EnableSRAM2Retention (void)
Enable SRAM2 content retention in Standby mode.
__STATIC_INLINE void | LL_PWR_DisableSRAM2Retention (void)
Disable SRAM2 content retention in Standby mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledSRAM2Retention (void)
Check if SRAM2 content retention in Standby mode is enabled.
__STATIC_INLINE void | LL_PWR_EnableWakeUpPin (uint32_t WakeUpPin)
Enable the WakeUp PINx functionality.
__STATIC_INLINE void | LL_PWR_DisableWakeUpPin (uint32_t WakeUpPin)
Disable the WakeUp PINx functionality.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledWakeUpPin (uint32_t WakeUpPin)
Check if the WakeUp PINx functionality is enabled.
__STATIC_INLINE void | LL_PWR_SetBattChargResistor (uint32_t Resistor)
Set the resistor impedance.
__STATIC_INLINE uint32_t | LL_PWR_GetBattChargResistor (void)
Get the resistor impedance.
__STATIC_INLINE void | LL_PWR_EnableBatteryCharging (void)
Enable battery charging.
__STATIC_INLINE void | LL_PWR_DisableBatteryCharging (void)
Disable battery charging.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledBatteryCharging (void)
Check if battery charging is enabled.
__STATIC_INLINE void | LL_PWR_SetWakeUpPinPolarityLow (uint32_t WakeUpPin)
Set the Wake-Up pin polarity low for the event detection.
__STATIC_INLINE void | LL_PWR_SetWakeUpPinPolarityHigh (uint32_t WakeUpPin)
Set the Wake-Up pin polarity high for the event detection.
__STATIC_INLINE uint32_t | LL_PWR_IsWakeUpPinPolarityLow (uint32_t WakeUpPin)
Get the Wake-Up pin polarity for the event detection.
__STATIC_INLINE void | LL_PWR_EnableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-up state in Standby and Shutdown modes.
__STATIC_INLINE void | LL_PWR_DisableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-up state in Standby and Shutdown modes.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Check if GPIO pull-up state is enabled.
__STATIC_INLINE void | LL_PWR_EnableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-down state in Standby and Shutdown modes.
__STATIC_INLINE void | LL_PWR_DisableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-down state in Standby and Shutdown modes.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Check if GPIO pull-down state is enabled.
__STATIC_INLINE void | LL_PWR_SetBORConfig (uint32_t BORConfiguration)
Set BOR configuration.
__STATIC_INLINE uint32_t | LL_PWR_GetBORConfig (void)
Get BOR configuration.

Function Documentation

__STATIC_INLINE void LL_PWR_DisableBatteryCharging ( void )

Disable battery charging.

Reference Manual to LL API cross reference:
CR4 VBE LL_PWR_DisableBatteryCharging
Return values:
None

Definition at line 946 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableBkUpAccess ( void )

Disable access to the backup domain.

Reference Manual to LL API cross reference:
CR1 DBP LL_PWR_DisableBkUpAccess
Return values:
None

Definition at line 503 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableGPIOPullDown | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Disable GPIO pull-down state in Standby and Shutdown modes.

Note:
Some pins are not configurable for pulling in Standby and Shutdown modes. Refer to reference manual for available pins and ports.
Reference Manual to LL API cross reference:
PDCRA PD0-15 LL_PWR_DisableGPIOPullDown
PDCRB PD0-15 LL_PWR_DisableGPIOPullDown
PDCRC PD0-15 LL_PWR_DisableGPIOPullDown
PDCRD PD0-15 LL_PWR_DisableGPIOPullDown
PDCRE PD0-15 LL_PWR_DisableGPIOPullDown
PDCRH PD0-15 LL_PWR_DisableGPIOPullDown
Parameters:
GPIO This parameter can be one of the following values:
  • LL_PWR_GPIO_A
  • LL_PWR_GPIO_B
  • LL_PWR_GPIO_C
  • LL_PWR_GPIO_D
  • LL_PWR_GPIO_E
  • LL_PWR_GPIO_H
GPIONumber This parameter can be one of the following values:
  • LL_PWR_GPIO_BIT_0
  • LL_PWR_GPIO_BIT_1
  • LL_PWR_GPIO_BIT_2
  • LL_PWR_GPIO_BIT_3
  • LL_PWR_GPIO_BIT_4
  • LL_PWR_GPIO_BIT_5
  • LL_PWR_GPIO_BIT_6
  • LL_PWR_GPIO_BIT_7
  • LL_PWR_GPIO_BIT_8
  • LL_PWR_GPIO_BIT_9
  • LL_PWR_GPIO_BIT_10
  • LL_PWR_GPIO_BIT_11
  • LL_PWR_GPIO_BIT_12
  • LL_PWR_GPIO_BIT_13
  • LL_PWR_GPIO_BIT_14
  • LL_PWR_GPIO_BIT_15
Return values:
None

Definition at line 1225 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableGPIOPullUp | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Disable GPIO pull-up state in Standby and Shutdown modes.

Note:
Some pins are not configurable for pulling in Standby and Shutdown modes. Refer to reference manual for available pins and ports.
Reference Manual to LL API cross reference:
PUCRA PU0-15 LL_PWR_DisableGPIOPullUp
PUCRB PU0-15 LL_PWR_DisableGPIOPullUp
PUCRC PU0-15 LL_PWR_DisableGPIOPullUp
PUCRD PU0-15 LL_PWR_DisableGPIOPullUp
PUCRE PU0-15 LL_PWR_DisableGPIOPullUp
PUCRH PU0-15 LL_PWR_DisableGPIOPullUp
Parameters:
GPIO This parameter can be one of the following values:
  • LL_PWR_GPIO_A
  • LL_PWR_GPIO_B
  • LL_PWR_GPIO_C
  • LL_PWR_GPIO_D
  • LL_PWR_GPIO_E
  • LL_PWR_GPIO_H
GPIONumber This parameter can be one of the following values:
  • LL_PWR_GPIO_BIT_0
  • LL_PWR_GPIO_BIT_1
  • LL_PWR_GPIO_BIT_2
  • LL_PWR_GPIO_BIT_3
  • LL_PWR_GPIO_BIT_4
  • LL_PWR_GPIO_BIT_5
  • LL_PWR_GPIO_BIT_6
  • LL_PWR_GPIO_BIT_7
  • LL_PWR_GPIO_BIT_8
  • LL_PWR_GPIO_BIT_9
  • LL_PWR_GPIO_BIT_10
  • LL_PWR_GPIO_BIT_11
  • LL_PWR_GPIO_BIT_12
  • LL_PWR_GPIO_BIT_13
  • LL_PWR_GPIO_BIT_14
  • LL_PWR_GPIO_BIT_15
Return values:
None

Definition at line 1104 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableInternWU ( void )

Disable Internal Wake-up line.

Reference Manual to LL API cross reference:
CR3 EIWF LL_PWR_DisableInternWU
Return values:
None

Definition at line 765 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisablePUPDCfg ( void )

Disable pull-up and pull-down configuration.

Reference Manual to LL API cross reference:
CR3 APC LL_PWR_DisablePUPDCfg
Return values:
None

Definition at line 795 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisablePVD ( void )

Disable Power Voltage Detector.

Reference Manual to LL API cross reference:
CR2 PVDE LL_PWR_DisablePVD
Return values:
None

Definition at line 735 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisablePVM ( uint32_t PeriphVoltage )

Disable the Power Voltage Monitoring on a peripheral.

Reference Manual to LL API cross reference:
CR2 PVME1 LL_PWR_DisablePVM
CR2 PVME3 LL_PWR_DisablePVM
Parameters:
PeriphVoltage This parameter can be one of the following values:
  • LL_PWR_PVM_VDDUSB_1_2V (*)
  • LL_PWR_PVM_VDDA_1_62V
(*) Not available on devices STM32WB50xx
Return values:
None

Definition at line 662 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableSRAM2Retention ( void )

Disable SRAM2 content retention in Standby mode.

Reference Manual to LL API cross reference:
CR3 RRS LL_PWR_DisableSRAM2Retention
Return values:
None

Definition at line 825 of file stm32wbxx_ll_pwr.h.

Referenced by HAL_PWREx_DisableSRAMRetention().

__STATIC_INLINE void LL_PWR_DisableVddUSB ( void )

Disable VDDUSB supply.

Reference Manual to LL API cross reference:
CR2 USV LL_PWR_DisableVddUSB
Return values:
None

Definition at line 619 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableWakeUpPin ( uint32_t WakeUpPin )

Disable the WakeUp PINx functionality.

Reference Manual to LL API cross reference:
CR3 EWUP1 LL_PWR_DisableWakeUpPin
CR3 EWUP2 LL_PWR_DisableWakeUpPin
CR3 EWUP3 LL_PWR_DisableWakeUpPin
CR3 EWUP4 LL_PWR_DisableWakeUpPin
CR3 EWUP5 LL_PWR_DisableWakeUpPin
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2 (*)
  • LL_PWR_WAKEUP_PIN3 (*)
  • LL_PWR_WAKEUP_PIN4
  • LL_PWR_WAKEUP_PIN5 (*)
(*) Not available on devices STM32WB50xx
Return values:
None

Definition at line 879 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableBatteryCharging ( void )

Enable battery charging.

Reference Manual to LL API cross reference:
CR4 VBE LL_PWR_EnableBatteryCharging
Return values:
None

Definition at line 936 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableBkUpAccess ( void )

Enable access to the backup domain.

Reference Manual to LL API cross reference:
CR1 DBP LL_PWR_EnableBkUpAccess
Return values:
None

Definition at line 493 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableGPIOPullDown | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Enable GPIO pull-down state in Standby and Shutdown modes.

Note:
Some pins are not configurable for pulling in Standby and Shutdown modes. Refer to reference manual for available pins and ports.
Reference Manual to LL API cross reference:
PDCRA PD0-15 LL_PWR_EnableGPIOPullDown
PDCRB PD0-15 LL_PWR_EnableGPIOPullDown
PDCRC PD0-15 LL_PWR_EnableGPIOPullDown
PDCRD PD0-15 LL_PWR_EnableGPIOPullDown
PDCRE PD0-15 LL_PWR_EnableGPIOPullDown
PDCRH PD0-15 LL_PWR_EnableGPIOPullDown
Parameters:
GPIO This parameter can be one of the following values:
  • LL_PWR_GPIO_A
  • LL_PWR_GPIO_B
  • LL_PWR_GPIO_C
  • LL_PWR_GPIO_D
  • LL_PWR_GPIO_E
  • LL_PWR_GPIO_H
GPIONumber This parameter can be one of the following values:
  • LL_PWR_GPIO_BIT_0
  • LL_PWR_GPIO_BIT_1
  • LL_PWR_GPIO_BIT_2
  • LL_PWR_GPIO_BIT_3
  • LL_PWR_GPIO_BIT_4
  • LL_PWR_GPIO_BIT_5
  • LL_PWR_GPIO_BIT_6
  • LL_PWR_GPIO_BIT_7
  • LL_PWR_GPIO_BIT_8
  • LL_PWR_GPIO_BIT_9
  • LL_PWR_GPIO_BIT_10
  • LL_PWR_GPIO_BIT_11
  • LL_PWR_GPIO_BIT_12
  • LL_PWR_GPIO_BIT_13
  • LL_PWR_GPIO_BIT_14
  • LL_PWR_GPIO_BIT_15
Return values:
None

Definition at line 1184 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableGPIOPullUp | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Enable GPIO pull-up state in Standby and Shutdown modes.

Note:
Some pins are not configurable for pulling in Standby and Shutdown modes. Refer to reference manual for available pins and ports.
Reference Manual to LL API cross reference:
PUCRA PU0-15 LL_PWR_EnableGPIOPullUp
PUCRB PU0-15 LL_PWR_EnableGPIOPullUp
PUCRC PU0-15 LL_PWR_EnableGPIOPullUp
PUCRD PU0-15 LL_PWR_EnableGPIOPullUp
PUCRE PU0-15 LL_PWR_EnableGPIOPullUp
PUCRH PU0-15 LL_PWR_EnableGPIOPullUp
Parameters:
GPIO This parameter can be one of the following values:
  • LL_PWR_GPIO_A
  • LL_PWR_GPIO_B
  • LL_PWR_GPIO_C
  • LL_PWR_GPIO_D
  • LL_PWR_GPIO_E
  • LL_PWR_GPIO_H
GPIONumber This parameter can be one of the following values:
  • LL_PWR_GPIO_BIT_0
  • LL_PWR_GPIO_BIT_1
  • LL_PWR_GPIO_BIT_2
  • LL_PWR_GPIO_BIT_3
  • LL_PWR_GPIO_BIT_4
  • LL_PWR_GPIO_BIT_5
  • LL_PWR_GPIO_BIT_6
  • LL_PWR_GPIO_BIT_7
  • LL_PWR_GPIO_BIT_8
  • LL_PWR_GPIO_BIT_9
  • LL_PWR_GPIO_BIT_10
  • LL_PWR_GPIO_BIT_11
  • LL_PWR_GPIO_BIT_12
  • LL_PWR_GPIO_BIT_13
  • LL_PWR_GPIO_BIT_14
  • LL_PWR_GPIO_BIT_15
Return values:
None

Definition at line 1063 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableInternWU ( void )

Enable Internal Wake-up line.

Reference Manual to LL API cross reference:
CR3 EIWF LL_PWR_EnableInternWU
Return values:
None

Definition at line 755 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnablePUPDCfg ( void )

Enable pull-up and pull-down configuration.

Reference Manual to LL API cross reference:
CR3 APC LL_PWR_EnablePUPDCfg
Return values:
None

Definition at line 785 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnablePVD ( void )

Enable Power Voltage Detector.

Reference Manual to LL API cross reference:
CR2 PVDE LL_PWR_EnablePVD
Return values:
None

Definition at line 725 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnablePVM ( uint32_t PeriphVoltage )

Enable the Power Voltage Monitoring on a peripheral.

Reference Manual to LL API cross reference:
CR2 PVME1 LL_PWR_EnablePVM
CR2 PVME3 LL_PWR_EnablePVM
Parameters:
PeriphVoltage This parameter can be one of the following values:
  • LL_PWR_PVM_VDDUSB_1_2V (*)
  • LL_PWR_PVM_VDDA_1_62V
(*) Not available on devices STM32WB50xx
Return values:
None

Definition at line 646 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableSRAM2Retention ( void )

Enable SRAM2 content retention in Standby mode.

Reference Manual to LL API cross reference:
CR3 RRS LL_PWR_EnableSRAM2Retention
Return values:
None

Definition at line 815 of file stm32wbxx_ll_pwr.h.

Referenced by HAL_PWREx_EnableSRAMRetention().

__STATIC_INLINE void LL_PWR_EnableVddUSB ( void )

Enable VDDUSB supply.

Reference Manual to LL API cross reference:
CR2 USV LL_PWR_EnableVddUSB
Return values:
None

Definition at line 609 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableWakeUpPin ( uint32_t WakeUpPin )

Enable the WakeUp PINx functionality.

Reference Manual to LL API cross reference:
CR3 EWUP1 LL_PWR_EnableWakeUpPin
CR3 EWUP2 LL_PWR_EnableWakeUpPin
CR3 EWUP3 LL_PWR_EnableWakeUpPin
CR3 EWUP4 LL_PWR_EnableWakeUpPin
CR3 EWUP5 LL_PWR_EnableWakeUpPin
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2 (*)
  • LL_PWR_WAKEUP_PIN3 (*)
  • LL_PWR_WAKEUP_PIN4
  • LL_PWR_WAKEUP_PIN5 (*)
(*) Not available on devices STM32WB50xx
Return values:
None

Definition at line 857 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnterLowPowerRunMode ( void )

Switch from run main mode to run low-power mode.

Reference Manual to LL API cross reference:
CR1 LPR LL_PWR_EnterLowPowerRunMode
Return values:
None

Definition at line 432 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ExitLowPowerRunMode ( void )

Switch from run main mode to low-power mode.

Reference Manual to LL API cross reference:
CR1 LPR LL_PWR_ExitLowPowerRunMode
Return values:
None

Definition at line 442 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor ( void )

Get the resistor impedance.

Reference Manual to LL API cross reference:
CR4 VBRS LL_PWR_GetBattChargResistor
Return values:
Returned value can be one of the following values:
  • LL_PWR_BATT_CHARG_RESISTOR_5K
  • LL_PWR_BATT_CHARGRESISTOR_1_5K

Definition at line 926 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_GetBORConfig ( void )

Get BOR configuration.

Reference Manual to LL API cross reference:
CR5 BORHC LL_PWR_GetBORConfig
Return values:
Returned value can be one of the following values:
  • LL_PWR_BOR_SYSTEM_RESET
  • LL_PWR_BOR_SMPS_FORCE_BYPASS

Definition at line 1289 of file stm32wbxx_ll_pwr.h.

Referenced by HAL_PWREx_GetBORConfig().

__STATIC_INLINE uint32_t LL_PWR_GetFlashPowerModeLPRun ( void )

Get flash power-down mode during low-power run mode.

Reference Manual to LL API cross reference:
CR1 FPDR LL_PWR_GetFlashPowerModeLPRun
Return values:
Returned value can be one of the following values:
  • LL_PWR_FLASH_LPRUN_MODE_IDLE
  • LL_PWR_FLASH_LPRUN_MODE_POWER_DOWN

Definition at line 573 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_GetFlashPowerModeSleep ( void )

Get flash power-down mode during sleep mode.

Reference Manual to LL API cross reference:
CR1 FPDS LL_PWR_GetFlashPowerModeSleep
Return values:
Returned value can be one of the following values:
  • LL_PWR_FLASH_SLEEP_MODE_IDLE
  • LL_PWR_FLASH_SLEEP_MODE_POWER_DOWN

Definition at line 598 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_GetPowerMode ( void )

Get Low-Power mode.

Reference Manual to LL API cross reference:
CR1 LPMS LL_PWR_GetPowerMode
Return values:
Returned value can be one of the following values:
  • LL_PWR_MODE_STOP0
  • LL_PWR_MODE_STOP1
  • LL_PWR_MODE_STOP2
  • LL_PWR_MODE_STANDBY
  • LL_PWR_MODE_SHUTDOWN

Definition at line 544 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel ( void )

Get the voltage threshold detection.

Reference Manual to LL API cross reference:
CR2 PLS LL_PWR_GetPVDLevel
Return values:
Returned value can be one of the following values:
  • LL_PWR_PVDLEVEL_0
  • LL_PWR_PVDLEVEL_1
  • LL_PWR_PVDLEVEL_2
  • LL_PWR_PVDLEVEL_3
  • LL_PWR_PVDLEVEL_4
  • LL_PWR_PVDLEVEL_5
  • LL_PWR_PVDLEVEL_6
  • LL_PWR_PVDLEVEL_7

Definition at line 715 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling ( void )

Get the main internal regulator output voltage.

Reference Manual to LL API cross reference:
CR1 VOS LL_PWR_GetRegulVoltageScaling
Return values:
Returned value can be one of the following values:
  • LL_PWR_REGU_VOLTAGE_SCALE1
  • LL_PWR_REGU_VOLTAGE_SCALE2

Definition at line 482 of file stm32wbxx_ll_pwr.h.

Referenced by UTILS_SetFlashLatency().

__STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging ( void )

Check if battery charging is enabled.

Reference Manual to LL API cross reference:
CR4 VBE LL_PWR_IsEnabledBatteryCharging
Return values:
State of bit (1 or 0).

Definition at line 956 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess ( void )

Check if the backup domain is enabled.

Reference Manual to LL API cross reference:
CR1 DBP LL_PWR_IsEnabledBkUpAccess
Return values:
State of bit (1 or 0).

Definition at line 513 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Check if GPIO pull-down state is enabled.

Reference Manual to LL API cross reference:
PDCRA PD0-15 LL_PWR_IsEnabledGPIOPullDown
PDCRB PD0-15 LL_PWR_IsEnabledGPIOPullDown
PDCRC PD0-15 LL_PWR_IsEnabledGPIOPullDown
PDCRD PD0-15 LL_PWR_IsEnabledGPIOPullDown
PDCRE PD0-15 LL_PWR_IsEnabledGPIOPullDown
PDCRH PD0-15 LL_PWR_IsEnabledGPIOPullDown
Parameters:
GPIO This parameter can be one of the following values:
  • LL_PWR_GPIO_A
  • LL_PWR_GPIO_B
  • LL_PWR_GPIO_C
  • LL_PWR_GPIO_D
  • LL_PWR_GPIO_E
  • LL_PWR_GPIO_H
GPIONumber This parameter can be one of the following values:
  • LL_PWR_GPIO_BIT_0
  • LL_PWR_GPIO_BIT_1
  • LL_PWR_GPIO_BIT_2
  • LL_PWR_GPIO_BIT_3
  • LL_PWR_GPIO_BIT_4
  • LL_PWR_GPIO_BIT_5
  • LL_PWR_GPIO_BIT_6
  • LL_PWR_GPIO_BIT_7
  • LL_PWR_GPIO_BIT_8
  • LL_PWR_GPIO_BIT_9
  • LL_PWR_GPIO_BIT_10
  • LL_PWR_GPIO_BIT_11
  • LL_PWR_GPIO_BIT_12
  • LL_PWR_GPIO_BIT_13
  • LL_PWR_GPIO_BIT_14
  • LL_PWR_GPIO_BIT_15
Return values:
State of bit (1 or 0).

Definition at line 1264 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Check if GPIO pull-up state is enabled.

Reference Manual to LL API cross reference:
PUCRA PU0-15 LL_PWR_IsEnabledGPIOPullUp
PUCRB PU0-15 LL_PWR_IsEnabledGPIOPullUp
PUCRC PU0-15 LL_PWR_IsEnabledGPIOPullUp
PUCRD PU0-15 LL_PWR_IsEnabledGPIOPullUp
PUCRE PU0-15 LL_PWR_IsEnabledGPIOPullUp
PUCRH PU0-15 LL_PWR_IsEnabledGPIOPullUp
Parameters:
GPIO This parameter can be one of the following values:
  • LL_PWR_GPIO_A
  • LL_PWR_GPIO_B
  • LL_PWR_GPIO_C
  • LL_PWR_GPIO_D
  • LL_PWR_GPIO_E
  • LL_PWR_GPIO_H
GPIONumber This parameter can be one of the following values:
  • LL_PWR_GPIO_BIT_0
  • LL_PWR_GPIO_BIT_1
  • LL_PWR_GPIO_BIT_2
  • LL_PWR_GPIO_BIT_3
  • LL_PWR_GPIO_BIT_4
  • LL_PWR_GPIO_BIT_5
  • LL_PWR_GPIO_BIT_6
  • LL_PWR_GPIO_BIT_7
  • LL_PWR_GPIO_BIT_8
  • LL_PWR_GPIO_BIT_9
  • LL_PWR_GPIO_BIT_10
  • LL_PWR_GPIO_BIT_11
  • LL_PWR_GPIO_BIT_12
  • LL_PWR_GPIO_BIT_13
  • LL_PWR_GPIO_BIT_14
  • LL_PWR_GPIO_BIT_15
Return values:
State of bit (1 or 0).

Definition at line 1143 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU ( void )

Check if Internal Wake-up line is enabled.

Reference Manual to LL API cross reference:
CR3 EIWF LL_PWR_IsEnabledInternWU
Return values:
State of bit (1 or 0).

Definition at line 775 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode ( void )

Check if the regulator is in low-power mode.

Reference Manual to LL API cross reference:
CR1 LPR LL_PWR_IsEnabledLowPowerRunMode
Return values:
State of bit (1 or 0).

Definition at line 452 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg ( void )

Check if pull-up and pull-down configuration is enabled.

Reference Manual to LL API cross reference:
CR3 APC LL_PWR_IsEnabledPUPDCfg
Return values:
State of bit (1 or 0).

Definition at line 805 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD ( void )

Check if Power Voltage Detector is enabled.

Reference Manual to LL API cross reference:
CR2 PVDE LL_PWR_IsEnabledPVD
Return values:
State of bit (1 or 0).

Definition at line 745 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM ( uint32_t PeriphVoltage )

Check if Power Voltage Monitoring is enabled on a peripheral.

Reference Manual to LL API cross reference:
CR2 PVME1 LL_PWR_IsEnabledPVM
CR2 PVME3 LL_PWR_IsEnabledPVM
Parameters:
PeriphVoltage This parameter can be one of the following values:
  • LL_PWR_PVM_VDDUSB_1_2V (*)
  • LL_PWR_PVM_VDDA_1_62V
(*) Not available on devices STM32WB50xx
Return values:
State of bit (1 or 0).

Definition at line 678 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Retention ( void )

Check if SRAM2 content retention in Standby mode is enabled.

Reference Manual to LL API cross reference:
CR3 RRS LL_PWR_IsEnabledSRAM2Retention
Return values:
State of bit (1 or 0).

Definition at line 835 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB ( void )

Check if VDDUSB supply is enabled.

Reference Manual to LL API cross reference:
CR2 USV LL_PWR_IsEnabledVddUSB
Return values:
State of bit (1 or 0).

Definition at line 629 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin ( uint32_t WakeUpPin )

Check if the WakeUp PINx functionality is enabled.

Reference Manual to LL API cross reference:
CR3 EWUP1 LL_PWR_IsEnabledWakeUpPin
CR3 EWUP2 LL_PWR_IsEnabledWakeUpPin
CR3 EWUP3 LL_PWR_IsEnabledWakeUpPin
CR3 EWUP4 LL_PWR_IsEnabledWakeUpPin
CR3 EWUP5 LL_PWR_IsEnabledWakeUpPin
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2 (*)
  • LL_PWR_WAKEUP_PIN3 (*)
  • LL_PWR_WAKEUP_PIN4
  • LL_PWR_WAKEUP_PIN5 (*)
(*) Not available on devices STM32WB50xx
Return values:
State of bit (1 or 0).

Definition at line 901 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow ( uint32_t WakeUpPin )

Get the Wake-Up pin polarity for the event detection.

Reference Manual to LL API cross reference:
CR4 WP1 LL_PWR_IsWakeUpPinPolarityLow
CR4 WP2 LL_PWR_IsWakeUpPinPolarityLow
CR4 WP3 LL_PWR_IsWakeUpPinPolarityLow
CR4 WP4 LL_PWR_IsWakeUpPinPolarityLow
CR4 WP5 LL_PWR_IsWakeUpPinPolarityLow
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2 (*)
  • LL_PWR_WAKEUP_PIN3 (*)
  • LL_PWR_WAKEUP_PIN4
  • LL_PWR_WAKEUP_PIN5 (*)
(*) Not available on devices STM32WB50xx
Return values:
State of bit (1 or 0).

Definition at line 1022 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetBattChargResistor ( uint32_t Resistor )

Set the resistor impedance.

Reference Manual to LL API cross reference:
CR4 VBRS LL_PWR_SetBattChargResistor
Parameters:
Resistor This parameter can be one of the following values:
  • LL_PWR_BATT_CHARG_RESISTOR_5K
  • LL_PWR_BATT_CHARGRESISTOR_1_5K
Return values:
None

Definition at line 914 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetBORConfig ( uint32_t BORConfiguration )

Set BOR configuration.

Reference Manual to LL API cross reference:
CR5 BORHC LL_PWR_SetBORConfig
Parameters:
BORConfiguration This parameter can be one of the following values:
  • LL_PWR_BOR_SYSTEM_RESET
  • LL_PWR_BOR_SMPS_FORCE_BYPASS

Definition at line 1277 of file stm32wbxx_ll_pwr.h.

Referenced by HAL_PWREx_SetBORConfig().

__STATIC_INLINE void LL_PWR_SetFlashPowerModeLPRun ( uint32_t FlashLowPowerMode )

Set flash power-down mode during low-power run mode.

Reference Manual to LL API cross reference:
CR1 FPDR LL_PWR_SetFlashPowerModeLPRun
Parameters:
FlashLowPowerMode This parameter can be one of the following values:
  • LL_PWR_FLASH_LPRUN_MODE_IDLE
  • LL_PWR_FLASH_LPRUN_MODE_POWER_DOWN
Return values:
None

Definition at line 557 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetFlashPowerModeSleep ( uint32_t FlashLowPowerMode )

Set flash power-down mode during sleep mode.

Reference Manual to LL API cross reference:
CR1 FPDS LL_PWR_SetFlashPowerModeSleep
Parameters:
FlashLowPowerMode This parameter can be one of the following values:
  • LL_PWR_FLASH_SLEEP_MODE_IDLE
  • LL_PWR_FLASH_SLEEP_MODE_POWER_DOWN
Return values:
None

Definition at line 586 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetPowerMode ( uint32_t LowPowerMode )

Set Low-Power mode.

Reference Manual to LL API cross reference:
CR1 LPMS LL_PWR_SetPowerMode
Parameters:
LowPowerMode This parameter can be one of the following values:
  • LL_PWR_MODE_STOP0
  • LL_PWR_MODE_STOP1
  • LL_PWR_MODE_STOP2
  • LL_PWR_MODE_STANDBY
  • LL_PWR_MODE_SHUTDOWN
Return values:
None

Definition at line 529 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetPVDLevel ( uint32_t PVDLevel )

Configure the voltage threshold detected by the Power Voltage Detector.

Reference Manual to LL API cross reference:
CR2 PLS LL_PWR_SetPVDLevel
Parameters:
PVDLevel This parameter can be one of the following values:
  • LL_PWR_PVDLEVEL_0
  • LL_PWR_PVDLEVEL_1
  • LL_PWR_PVDLEVEL_2
  • LL_PWR_PVDLEVEL_3
  • LL_PWR_PVDLEVEL_4
  • LL_PWR_PVDLEVEL_5
  • LL_PWR_PVDLEVEL_6
  • LL_PWR_PVDLEVEL_7
Return values:
None

Definition at line 697 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling ( uint32_t VoltageScaling )

Set the main internal regulator output voltage.

Note:
A delay is required for the internal regulator to be ready after the voltage scaling has been changed. Check whether regulator reached the selected voltage level can be done using function LL_PWR_IsActiveFlag_VOS().
Reference Manual to LL API cross reference:
CR1 VOS LL_PWR_SetRegulVoltageScaling
Parameters:
VoltageScaling This parameter can be one of the following values:
  • LL_PWR_REGU_VOLTAGE_SCALE1
  • LL_PWR_REGU_VOLTAGE_SCALE2
Return values:
None

Definition at line 470 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh ( uint32_t WakeUpPin )

Set the Wake-Up pin polarity high for the event detection.

Reference Manual to LL API cross reference:
CR4 WP1 LL_PWR_SetWakeUpPinPolarityHigh
CR4 WP2 LL_PWR_SetWakeUpPinPolarityHigh
CR4 WP3 LL_PWR_SetWakeUpPinPolarityHigh
CR4 WP4 LL_PWR_SetWakeUpPinPolarityHigh
CR4 WP5 LL_PWR_SetWakeUpPinPolarityHigh
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2 (*)
  • LL_PWR_WAKEUP_PIN3 (*)
  • LL_PWR_WAKEUP_PIN4
  • LL_PWR_WAKEUP_PIN5 (*)
(*) Not available on devices STM32WB50xx
Return values:
None

Definition at line 1000 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow ( uint32_t WakeUpPin )

Set the Wake-Up pin polarity low for the event detection.

Reference Manual to LL API cross reference:
CR4 WP1 LL_PWR_SetWakeUpPinPolarityLow
CR4 WP2 LL_PWR_SetWakeUpPinPolarityLow
CR4 WP3 LL_PWR_SetWakeUpPinPolarityLow
CR4 WP4 LL_PWR_SetWakeUpPinPolarityLow
CR4 WP5 LL_PWR_SetWakeUpPinPolarityLow
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2 (*)
  • LL_PWR_WAKEUP_PIN3 (*)
  • LL_PWR_WAKEUP_PIN4
  • LL_PWR_WAKEUP_PIN5 (*)
(*) Not available on devices STM32WB50xx
Return values:
None

Definition at line 978 of file stm32wbxx_ll_pwr.h.

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Configuration of SMPS

Functions
Configuration of SMPS
PWR Exported Functions

Functions

__STATIC_INLINE void | LL_PWR_SMPS_SetMode (uint32_t OperatingMode)
Set SMPS operating mode.
__STATIC_INLINE uint32_t | LL_PWR_SMPS_GetMode (void)
Get SMPS operating mode.
__STATIC_INLINE uint32_t | LL_PWR_SMPS_GetEffectiveMode (void)
Get SMPS effective operating mode.
__STATIC_INLINE void | LL_PWR_SMPS_Enable (void)
SMPS step down converter enable.
__STATIC_INLINE void | LL_PWR_SMPS_Disable (void)
SMPS step down converter enable.
__STATIC_INLINE uint32_t | LL_PWR_SMPS_IsEnabled (void)
Check if the SMPS step down converter is enabled.
__STATIC_INLINE void | LL_PWR_SMPS_SetStartupCurrent (uint32_t StartupCurrent)
Set SMPS step down converter supply startup current selection.
__STATIC_INLINE uint32_t | LL_PWR_SMPS_GetStartupCurrent (void)
Get SMPS step down converter supply startup current selection.
__STATIC_INLINE void | LL_PWR_SMPS_SetOutputVoltageLevel (uint32_t OutputVoltageLevel)
Set SMPS step down converter output voltage scaling.
__STATIC_INLINE uint32_t | LL_PWR_SMPS_GetOutputVoltageLevel (void)
Get SMPS step down converter output voltage scaling.

Function Documentation

__STATIC_INLINE void LL_PWR_SMPS_Disable ( void )

SMPS step down converter enable.

Note:
This function can be used for specific usage of the SMPS, for general usage of the SMPS the function LL_PWR_SMPS_SetMode() should be used instead.
Reference Manual to LL API cross reference:
CR5 SMPSEN LL_PWR_SMPS_Disable
Return values:
None

Definition at line 1411 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SMPS_Enable ( void )

SMPS step down converter enable.

Note:
This function can be used for specific usage of the SMPS, for general usage of the SMPS the function LL_PWR_SMPS_SetMode() should be used instead.
Reference Manual to LL API cross reference:
CR5 SMPSEN LL_PWR_SMPS_Enable
Return values:
None

Definition at line 1398 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_SMPS_GetEffectiveMode ( void )

Get SMPS effective operating mode.

Note:
SMPS operating mode can be changed by hardware, therefore requested operating mode can differ from effective low power mode.
  • dependency on system low-power mode:
    • step down mode if system low power mode is run, LP run or stop0,
    • open mode if system low power mode is stop1, stop2, standby or shutdown
  • dependency on BOR level:
    • bypass mode if supply voltage drops below BOR level
This functions check flags of SMPS operating modes step down and bypass. If the SMPS is not among these 2 operating modes, then it can be in mode off or open.
Reference Manual to LL API cross reference:
SR2 SMPSF LL_PWR_SMPS_GetEffectiveMode
SR2 SMPSBF LL_PWR_SMPS_GetEffectiveMode
Return values:
Returned value can be one of the following values:
  • LL_PWR_SMPS_BYPASS
  • LL_PWR_SMPS_STEP_DOWN (1)
(1) SMPS operating mode step down or open depends on system low-power mode:
  • step down mode if system low power mode is run, LP run or stop0,
  • open mode if system low power mode is stop1, stop2, standby or shutdown

Definition at line 1385 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_SMPS_GetMode ( void )

Get SMPS operating mode.

Reference Manual to LL API cross reference:
CR5 SMPSEN LL_PWR_SMPS_GetMode
CR5 SMPSBEN LL_PWR_SMPS_GetMode
Return values:
Returned value can be one of the following values:
  • LL_PWR_SMPS_BYPASS
  • LL_PWR_SMPS_STEP_DOWN (1)
(1) SMPS operating mode step down or open depends on system low-power mode:
  • step down mode if system low power mode is run, LP run or stop0,
  • open mode if system low power mode is stop1, stop2, standby or shutdown

Definition at line 1350 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_SMPS_GetOutputVoltageLevel ( void )

Get SMPS step down converter output voltage scaling.

Note:
SMPS output voltage is calibrated in production, calibration parameters are applied to the voltage level parameter to return the effective voltage value.
Reference Manual to LL API cross reference:
CR5 SMPSVOS LL_PWR_SMPS_GetOutputVoltageLevel
Return values:
Returned value can be one of the following values:
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V20
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V25
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V30
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V35
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V45
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V50
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V55
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V60
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V65
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V70
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V75
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V80
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V85
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V90

Definition at line 1548 of file stm32wbxx_ll_pwr.h.

References LL_PWR_SMPS_OUTPUT_VOLTAGE_1V20, LL_PWR_SMPS_OUTPUT_VOLTAGE_1V50, LL_PWR_SMPS_OUTPUT_VOLTAGE_1V90, SMPS_VOLTAGE_CAL, and SMPS_VOLTAGE_CAL_POS.

__STATIC_INLINE uint32_t LL_PWR_SMPS_GetStartupCurrent ( void )

Get SMPS step down converter supply startup current selection.

Reference Manual to LL API cross reference:
CR5 SMPSSC LL_PWR_SMPS_GetStartupCurrent
Return values:
Returned value can be one of the following values:
  • LL_PWR_SMPS_STARTUP_CURRENT_80MA
  • LL_PWR_SMPS_STARTUP_CURRENT_100MA
  • LL_PWR_SMPS_STARTUP_CURRENT_120MA
  • LL_PWR_SMPS_STARTUP_CURRENT_140MA
  • LL_PWR_SMPS_STARTUP_CURRENT_160MA
  • LL_PWR_SMPS_STARTUP_CURRENT_180MA
  • LL_PWR_SMPS_STARTUP_CURRENT_200MA
  • LL_PWR_SMPS_STARTUP_CURRENT_220MA

Definition at line 1458 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_SMPS_IsEnabled ( void )

Check if the SMPS step down converter is enabled.

Reference Manual to LL API cross reference:
CR5 SMPSEN LL_PWR_SMPS_IsEnabled
Return values:
State of bit (1 or 0).

Definition at line 1421 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SMPS_SetMode ( uint32_t OperatingMode )

Set SMPS operating mode.

Note:
When SMPS step down converter SMPS mode is enabled, it is good practice to enable the BORH to monitor the supply: in this case, when the supply drops below the SMPS step down converter SMPS mode operating supply level, switching on the fly is performed automaticcaly and interruption is generated. Refer to function LL_PWR_SetBORConfig().
Occurence of SMPS step down converter forced in bypass mode can be monitored by flag and interruption. Refer to functions LL_PWR_IsActiveFlag_SMPSFB(), LL_PWR_ClearFlag_SMPSFB(), LL_PWR_EnableIT_BORH_SMPSFB().
Reference Manual to LL API cross reference:
CR5 SMPSEN LL_PWR_SMPS_SetMode
CR5 SMPSBEN LL_PWR_SMPS_SetMode
Parameters:
OperatingMode This parameter can be one of the following values:
  • LL_PWR_SMPS_BYPASS
  • LL_PWR_SMPS_STEP_DOWN (1)
(1) SMPS operating mode step down or open depends on system low-power mode:
  • step down mode if system low power mode is run, LP run or stop0,
  • open mode if system low power mode is stop1, stop2, standby or shutdown
Return values:
None

Definition at line 1329 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SMPS_SetOutputVoltageLevel ( uint32_t OutputVoltageLevel )

Set SMPS step down converter output voltage scaling.

Note:
SMPS output voltage is calibrated in production, calibration parameters are applied to the voltage level parameter to reach the requested voltage value.
Reference Manual to LL API cross reference:
CR5 SMPSVOS LL_PWR_SMPS_SetOutputVoltageLevel
Parameters:
OutputVoltageLevel This parameter can be one of the following values:
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V20
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V25
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V30
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V35
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V45
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V50
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V55
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V60
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V65
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V70
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V75
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V80
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V85
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V90
Return values:
None

Definition at line 1487 of file stm32wbxx_ll_pwr.h.

References LL_PWR_SMPS_OUTPUT_VOLTAGE_1V50, SMPS_VOLTAGE_CAL, and SMPS_VOLTAGE_CAL_POS.

__STATIC_INLINE void LL_PWR_SMPS_SetStartupCurrent ( uint32_t StartupCurrent )

Set SMPS step down converter supply startup current selection.

Reference Manual to LL API cross reference:
CR5 SMPSSC LL_PWR_SMPS_SetStartupCurrent
Parameters:
StartupCurrent This parameter can be one of the following values:
  • LL_PWR_SMPS_STARTUP_CURRENT_80MA
  • LL_PWR_SMPS_STARTUP_CURRENT_100MA
  • LL_PWR_SMPS_STARTUP_CURRENT_120MA
  • LL_PWR_SMPS_STARTUP_CURRENT_140MA
  • LL_PWR_SMPS_STARTUP_CURRENT_160MA
  • LL_PWR_SMPS_STARTUP_CURRENT_180MA
  • LL_PWR_SMPS_STARTUP_CURRENT_200MA
  • LL_PWR_SMPS_STARTUP_CURRENT_220MA
Return values:
None

Definition at line 1440 of file stm32wbxx_ll_pwr.h.

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Configuration of multicore, intended to be executed by CPU1

Functions
Configuration of multicore, intended to be executed by CPU1
PWR Exported Functions

Functions

__STATIC_INLINE void | LL_PWR_EnableBootC2 (void)
Boot CPU2 after reset or wakeup from stop or standby modes.
__STATIC_INLINE void | LL_PWR_DisableBootC2 (void)
Release bit to boot CPU2 after reset or wakeup from stop or standby modes.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledBootC2 (void)
Check if bit to boot CPU2 after reset or wakeup from stop or standby modes is set.

Function Documentation

__STATIC_INLINE void LL_PWR_DisableBootC2 ( void )

Release bit to boot CPU2 after reset or wakeup from stop or standby modes.

Reference Manual to LL API cross reference:
CR4 C2BOOT LL_PWR_DisableBootC2
Return values:
None

Definition at line 1610 of file stm32wbxx_ll_pwr.h.

Referenced by HAL_PWREx_HoldCore().

__STATIC_INLINE void LL_PWR_EnableBootC2 ( void )

Boot CPU2 after reset or wakeup from stop or standby modes.

Reference Manual to LL API cross reference:
CR4 C2BOOT LL_PWR_EnableBootC2
Return values:
None

Definition at line 1599 of file stm32wbxx_ll_pwr.h.

Referenced by HAL_PWREx_ReleaseCore().

__STATIC_INLINE uint32_t LL_PWR_IsEnabledBootC2 ( void )

Check if bit to boot CPU2 after reset or wakeup from stop or standby modes is set.

Reference Manual to LL API cross reference:
CR4 C2BOOT LL_PWR_IsEnabledBootC2
Return values:
State of bit (1 or 0)

Definition at line 1621 of file stm32wbxx_ll_pwr.h.

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Configuration of CPU2, intended to be executed by CPU2

Functions
Configuration of CPU2, intended to be executed by CPU2
PWR Exported Functions

Functions

__STATIC_INLINE void | LL_C2_PWR_SetPowerMode (uint32_t LowPowerMode)
Set Low-Power mode for CPU2.
__STATIC_INLINE uint32_t | LL_C2_PWR_GetPowerMode (void)
Get Low-Power mode for CPU2.
__STATIC_INLINE void | LL_C2_PWR_SetFlashPowerModeLPRun (uint32_t FlashLowPowerMode)
Set flash power-down mode during low-power run mode for CPU2.
__STATIC_INLINE uint32_t | LL_C2_PWR_GetFlashPowerModeLPRun (void)
Get flash power-down mode during low-power run mode for CPU2.
__STATIC_INLINE void | LL_C2_PWR_SetFlashPowerModeSleep (uint32_t FlashLowPowerMode)
Set flash power-down mode during sleep mode for CPU2.
__STATIC_INLINE uint32_t | LL_C2_PWR_GetFlashPowerModeSleep (void)
Get flash power-down mode during sleep mode for CPU2.
__STATIC_INLINE void | LL_C2_PWR_EnableInternWU (void)
Enable Internal Wake-up line for CPU2.
__STATIC_INLINE void | LL_C2_PWR_DisableInternWU (void)
Disable Internal Wake-up line for CPU2.
__STATIC_INLINE uint32_t | LL_C2_PWR_IsEnabledInternWU (void)
Check if Internal Wake-up line is enabled for CPU2.
__STATIC_INLINE void | LL_C2_PWR_EnableWakeUpPin (uint32_t WakeUpPin)
Enable the WakeUp PINx functionality.
__STATIC_INLINE void | LL_C2_PWR_DisableWakeUpPin (uint32_t WakeUpPin)
Disable the WakeUp PINx functionality.
__STATIC_INLINE uint32_t | LL_C2_PWR_IsEnabledWakeUpPin (uint32_t WakeUpPin)
Check if the WakeUp PINx functionality is enabled.
__STATIC_INLINE void | LL_C2_PWR_EnablePUPDCfg (void)
Enable pull-up and pull-down configuration for CPU2.
__STATIC_INLINE void | LL_C2_PWR_DisablePUPDCfg (void)
Disable pull-up and pull-down configuration for CPU2.
__STATIC_INLINE uint32_t | LL_C2_PWR_IsEnabledPUPDCfg (void)
Check if pull-up and pull-down configuration is enabled for CPU2.

Function Documentation

__STATIC_INLINE void LL_C2_PWR_DisableInternWU ( void )

Disable Internal Wake-up line for CPU2.

Reference Manual to LL API cross reference:
C2CR3 EIWUL LL_C2_PWR_DisableInternWU
Return values:
None

Definition at line 1735 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_C2_PWR_DisablePUPDCfg ( void )

Disable pull-up and pull-down configuration for CPU2.

Reference Manual to LL API cross reference:
C2CR3 APC LL_C2_PWR_DisablePUPDCfg
Return values:
None

Definition at line 1831 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_C2_PWR_DisableWakeUpPin ( uint32_t WakeUpPin )

Disable the WakeUp PINx functionality.

Reference Manual to LL API cross reference:
C2CR3 EWUP1 LL_C2_PWR_DisableWakeUpPin
C2CR3 EWUP2 LL_C2_PWR_DisableWakeUpPin
C2CR3 EWUP3 LL_C2_PWR_DisableWakeUpPin
C2CR3 EWUP4 LL_C2_PWR_DisableWakeUpPin
C2CR3 EWUP5 LL_C2_PWR_DisableWakeUpPin
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2 (*)
  • LL_PWR_WAKEUP_PIN3 (*)
  • LL_PWR_WAKEUP_PIN4
  • LL_PWR_WAKEUP_PIN5 (*)
(*) Not available on devices STM32WB50xx
Return values:
None

Definition at line 1789 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_C2_PWR_EnableInternWU ( void )

Enable Internal Wake-up line for CPU2.

Reference Manual to LL API cross reference:
C2CR3 EIWUL LL_C2_PWR_EnableInternWU
Return values:
None

Definition at line 1725 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_C2_PWR_EnablePUPDCfg ( void )

Enable pull-up and pull-down configuration for CPU2.

Reference Manual to LL API cross reference:
C2CR3 APC LL_C2_PWR_EnablePUPDCfg
Return values:
None

Definition at line 1821 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_C2_PWR_EnableWakeUpPin ( uint32_t WakeUpPin )

Enable the WakeUp PINx functionality.

Reference Manual to LL API cross reference:
C2CR3 EWUP1 LL_C2_PWR_EnableWakeUpPin
C2CR3 EWUP2 LL_C2_PWR_EnableWakeUpPin
C2CR3 EWUP3 LL_C2_PWR_EnableWakeUpPin
C2CR3 EWUP4 LL_C2_PWR_EnableWakeUpPin
C2CR3 EWUP5 LL_C2_PWR_EnableWakeUpPin
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2 (*)
  • LL_PWR_WAKEUP_PIN3 (*)
  • LL_PWR_WAKEUP_PIN4
  • LL_PWR_WAKEUP_PIN5 (*)
(*) Not available on devices STM32WB50xx
Return values:
None

Definition at line 1767 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_C2_PWR_GetFlashPowerModeLPRun ( void )

Get flash power-down mode during low-power run mode for CPU2.

Reference Manual to LL API cross reference:
C2CR1 FPDR LL_C2_PWR_GetFlashPowerModeLPRun
Return values:
Returned value can be one of the following values:
  • LL_PWR_FLASH_LPRUN_MODE_IDLE
  • LL_PWR_FLASH_LPRUN_MODE_POWER_DOWN

Definition at line 1689 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_C2_PWR_GetFlashPowerModeSleep ( void )

Get flash power-down mode during sleep mode for CPU2.

Reference Manual to LL API cross reference:
C2CR1 FPDS LL_C2_PWR_GetFlashPowerModeSleep
Return values:
Returned value can be one of the following values:
  • LL_PWR_FLASH_SLEEP_MODE_IDLE
  • LL_PWR_FLASH_SLEEP_MODE_POWER_DOWN

Definition at line 1714 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_C2_PWR_GetPowerMode ( void )

Get Low-Power mode for CPU2.

Reference Manual to LL API cross reference:
C2CR1 LPMS LL_C2_PWR_GetPowerMode
Return values:
Returned value can be one of the following values:
  • LL_PWR_MODE_STOP0
  • LL_PWR_MODE_STOP1
  • LL_PWR_MODE_STOP2
  • LL_PWR_MODE_STANDBY
  • LL_PWR_MODE_SHUTDOWN

Definition at line 1660 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledInternWU ( void )

Check if Internal Wake-up line is enabled for CPU2.

Reference Manual to LL API cross reference:
C2CR3 EIWUL LL_C2_PWR_IsEnabledInternWU
Return values:
State of bit (1 or 0).

Definition at line 1745 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledPUPDCfg ( void )

Check if pull-up and pull-down configuration is enabled for CPU2.

Reference Manual to LL API cross reference:
C2CR3 APC LL_C2_PWR_IsEnabledPUPDCfg
Return values:
State of bit (1 or 0).

Definition at line 1841 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledWakeUpPin ( uint32_t WakeUpPin )

Check if the WakeUp PINx functionality is enabled.

Reference Manual to LL API cross reference:
C2CR3 EWUP1 LL_C2_PWR_IsEnabledWakeUpPin
C2CR3 EWUP2 LL_C2_PWR_IsEnabledWakeUpPin
C2CR3 EWUP3 LL_C2_PWR_IsEnabledWakeUpPin
C2CR3 EWUP4 LL_C2_PWR_IsEnabledWakeUpPin
C2CR3 EWUP5 LL_C2_PWR_IsEnabledWakeUpPin
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
  • LL_PWR_WAKEUP_PIN2 (*)
  • LL_PWR_WAKEUP_PIN3 (*)
  • LL_PWR_WAKEUP_PIN4
  • LL_PWR_WAKEUP_PIN5 (*)
(*) Not available on devices STM32WB50xx
Return values:
None

Definition at line 1811 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_C2_PWR_SetFlashPowerModeLPRun ( uint32_t FlashLowPowerMode )

Set flash power-down mode during low-power run mode for CPU2.

Reference Manual to LL API cross reference:
C2CR1 FPDR LL_C2_PWR_SetFlashPowerModeLPRun
Parameters:
FlashLowPowerMode This parameter can be one of the following values:
  • LL_PWR_FLASH_LPRUN_MODE_IDLE
  • LL_PWR_FLASH_LPRUN_MODE_POWER_DOWN
Return values:
None

Definition at line 1673 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_C2_PWR_SetFlashPowerModeSleep ( uint32_t FlashLowPowerMode )

Set flash power-down mode during sleep mode for CPU2.

Reference Manual to LL API cross reference:
C2CR1 FPDS LL_C2_PWR_SetFlashPowerModeSleep
Parameters:
FlashLowPowerMode This parameter can be one of the following values:
  • LL_PWR_FLASH_SLEEP_MODE_IDLE
  • LL_PWR_FLASH_SLEEP_MODE_POWER_DOWN
Return values:
None

Definition at line 1702 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_C2_PWR_SetPowerMode ( uint32_t LowPowerMode )

Set Low-Power mode for CPU2.

Reference Manual to LL API cross reference:
C2CR1 LPMS LL_C2_PWR_SetPowerMode
Parameters:
LowPowerMode This parameter can be one of the following values:
  • LL_PWR_MODE_STOP0
  • LL_PWR_MODE_STOP1
  • LL_PWR_MODE_STOP2
  • LL_PWR_MODE_STANDBY
  • LL_PWR_MODE_SHUTDOWN
Return values:
None

Definition at line 1645 of file stm32wbxx_ll_pwr.h.

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Configuration of radio (BLE or 802.15.4) of CPU2, intended to be executed by CPU2

Functions
Configuration of radio (BLE or 802.15.4) of CPU2, intended to be executed by CPU2
PWR Exported Functions

Functions

__STATIC_INLINE void | LL_C2_PWR_WakeUp_BLE (void)
Wakeup BLE controller from its sleep mode.
__STATIC_INLINE uint32_t | LL_C2_PWR_IsWokenUp_BLE (void)
Check if the BLE controller is woken-up from low-power mode.
__STATIC_INLINE void | LL_C2_PWR_WakeUp_802_15_4 (void)
Wakeup 802.15.4 controller from its sleep mode.
__STATIC_INLINE uint32_t | LL_C2_PWR_IsWokenUp_802_15_4 (void)
Check if the 802.15.4 controller is woken-up from low-power mode.

Function Documentation

__STATIC_INLINE uint32_t LL_C2_PWR_IsWokenUp_802_15_4 ( void )

Check if the 802.15.4 controller is woken-up from low-power mode.

Reference Manual to LL API cross reference:
C2CR1 802EWKUP LL_C2_PWR_IsWokenUp_802_15_4
Return values:
State of bit (1 or 0) (value "0": 802.15.4 is not woken-up)

Definition at line 1895 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_C2_PWR_IsWokenUp_BLE ( void )

Check if the BLE controller is woken-up from low-power mode.

Reference Manual to LL API cross reference:
C2CR1 BLEEWKUP LL_C2_PWR_IsWokenUp_BLE
Return values:
State of bit (1 or 0) (value "0": BLE is not woken-up)

Definition at line 1872 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_C2_PWR_WakeUp_802_15_4 ( void )

Wakeup 802.15.4 controller from its sleep mode.

Note:
This bit is automatically reset when 802.15.4 controller exit its sleep mode.
Reference Manual to LL API cross reference:
C2CR1 802EWKUP LL_C2_PWR_WakeUp_802_15_4
Return values:
None

Definition at line 1884 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_C2_PWR_WakeUp_BLE ( void )

Wakeup BLE controller from its sleep mode.

Note:
This bit is automatically reset when BLE controller exit its sleep mode.
Reference Manual to LL API cross reference:
C2CR1 BLEEWKUP LL_C2_PWR_WakeUp_BLE
Return values:
None

Definition at line 1861 of file stm32wbxx_ll_pwr.h.

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FLAG_Management

Functions
FLAG_Management
PWR Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_InternWU (void)
Get Internal Wake-up line Flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU5 (void)
Get Wake-up Flag 5.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU4 (void)
Get Wake-up Flag 4.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU3 (void)
Get Wake-up Flag 3.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU2 (void)
Get Wake-up Flag 2.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU1 (void)
Get Wake-up Flag 1.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU (void)
Clear Wake-up Flags.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU5 (void)
Clear Wake-up Flag 5.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU4 (void)
Clear Wake-up Flag 4.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU3 (void)
Clear Wake-up Flag 3.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU2 (void)
Clear Wake-up Flag 2.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU1 (void)
Clear Wake-up Flag 1.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_PVMO3 (void)
Indicate whether VDDA voltage is below or above PVM3 threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_PVMO1 (void)
Indicate whether VDDUSB voltage is below or above PVM1 threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_PVDO (void)
Indicate whether VDD voltage is below or above the selected PVD threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_VOS (void)
Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_REGLPF (void)
Indicate whether the regulator is ready in main mode or is in low-power mode.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_REGLPS (void)
Indicate whether or not the low-power regulator is ready.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_BORH (void)
Get BORH interrupt flag.
__STATIC_INLINE void | LL_PWR_ClearFlag_BORH (void)
Clear BORH interrupt flag.

Function Documentation

__STATIC_INLINE void LL_PWR_ClearFlag_BORH ( void )

Clear BORH interrupt flag.

Reference Manual to LL API cross reference:
SCR CBORHF LL_PWR_ClearFlag_BORH
Return values:
None

Definition at line 2121 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_WU ( void )

Clear Wake-up Flags.

Reference Manual to LL API cross reference:
SCR CWUF LL_PWR_ClearFlag_WU
Return values:
None

Definition at line 1979 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_WU1 ( void )

Clear Wake-up Flag 1.

Reference Manual to LL API cross reference:
SCR CWUF1 LL_PWR_ClearFlag_WU1
Return values:
None

Definition at line 2035 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_WU2 ( void )

Clear Wake-up Flag 2.

Reference Manual to LL API cross reference:
SCR CWUF2 LL_PWR_ClearFlag_WU2
Return values:
None

Definition at line 2024 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_WU3 ( void )

Clear Wake-up Flag 3.

Reference Manual to LL API cross reference:
SCR CWUF3 LL_PWR_ClearFlag_WU3
Return values:
None

Definition at line 2012 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_WU4 ( void )

Clear Wake-up Flag 4.

Reference Manual to LL API cross reference:
SCR CWUF4 LL_PWR_ClearFlag_WU4
Return values:
None

Definition at line 2001 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_WU5 ( void )

Clear Wake-up Flag 5.

Reference Manual to LL API cross reference:
SCR CWUF5 LL_PWR_ClearFlag_WU5
Return values:
None

Definition at line 1990 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BORH ( void )

Get BORH interrupt flag.

Reference Manual to LL API cross reference:
SR1 BORHF LL_PWR_IsActiveFlag_BORH
Return values:
State of bit (1 or 0).

Definition at line 2111 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU ( void )

Get Internal Wake-up line Flag.

Reference Manual to LL API cross reference:
SR1 WUFI LL_PWR_IsActiveFlag_InternWU
Return values:
State of bit (1 or 0).

Definition at line 1913 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO ( void )

Indicate whether VDD voltage is below or above the selected PVD threshold.

Reference Manual to LL API cross reference:
SR2 PVDO LL_PWR_IsActiveFlag_PVDO
Return values:
State of bit (1 or 0).

Definition at line 2068 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO1 ( void )

Indicate whether VDDUSB voltage is below or above PVM1 threshold.

Reference Manual to LL API cross reference:
SR2 PVMO1 LL_PWR_IsActiveFlag_PVMO1
Return values:
State of bit (1 or 0).

Definition at line 2057 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO3 ( void )

Indicate whether VDDA voltage is below or above PVM3 threshold.

Reference Manual to LL API cross reference:
SR2 PVMO3 LL_PWR_IsActiveFlag_PVMO3
Return values:
State of bit (1 or 0).

Definition at line 2046 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF ( void )

Indicate whether the regulator is ready in main mode or is in low-power mode.

Note:
Take care, return value "0" means the regulator is ready. Return value "1" means the output voltage range is still changing.
Reference Manual to LL API cross reference:
SR2 REGLPF LL_PWR_IsActiveFlag_REGLPF
Return values:
State of bit (1 or 0).

Definition at line 2091 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS ( void )

Indicate whether or not the low-power regulator is ready.

Reference Manual to LL API cross reference:
SR2 REGLPS LL_PWR_IsActiveFlag_REGLPS
Return values:
State of bit (1 or 0).

Definition at line 2101 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS ( void )

Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level.

Reference Manual to LL API cross reference:
SR2 VOSF LL_PWR_IsActiveFlag_VOS
Return values:
State of bit (1 or 0).

Definition at line 2079 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1 ( void )

Get Wake-up Flag 1.

Reference Manual to LL API cross reference:
SR1 WUF1 LL_PWR_IsActiveFlag_WU1
Return values:
State of bit (1 or 0).

Definition at line 1969 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2 ( void )

Get Wake-up Flag 2.

Reference Manual to LL API cross reference:
SR1 WUF2 LL_PWR_IsActiveFlag_WU2
Return values:
State of bit (1 or 0).

Definition at line 1958 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3 ( void )

Get Wake-up Flag 3.

Reference Manual to LL API cross reference:
SR1 WUF3 LL_PWR_IsActiveFlag_WU3
Return values:
State of bit (1 or 0).

Definition at line 1946 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4 ( void )

Get Wake-up Flag 4.

Reference Manual to LL API cross reference:
SR1 WUF4 LL_PWR_IsActiveFlag_WU4
Return values:
State of bit (1 or 0).

Definition at line 1935 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5 ( void )

Get Wake-up Flag 5.

Reference Manual to LL API cross reference:
SR1 WUF5 LL_PWR_IsActiveFlag_WU5
Return values:
State of bit (1 or 0).

Definition at line 1924 of file stm32wbxx_ll_pwr.h.

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FLAG management for SMPS

Functions
FLAG management for SMPS
PWR Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_SMPSFB (void)
Get SMPS step down converter forced in bypass mode interrupt flag.
__STATIC_INLINE void | LL_PWR_ClearFlag_SMPSFB (void)
Clear SMPS step down converter forced in bypass mode interrupt flag.

Function Documentation

__STATIC_INLINE void LL_PWR_ClearFlag_SMPSFB ( void )

Clear SMPS step down converter forced in bypass mode interrupt flag.

Note:
To activate flag of SMPS step down converter forced in bypass mode by BORH, BOR must be preliminarily configured to control SMPS operating mode. Refer to function LL_PWR_SetBORConfig().
Reference Manual to LL API cross reference:
SCR CSMPSFBF LL_PWR_ClearFlag_SMPSFB
Return values:
None

Definition at line 2158 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SMPSFB ( void )

Get SMPS step down converter forced in bypass mode interrupt flag.

Note:
To activate flag of SMPS step down converter forced in bypass mode by BORH, BOR must be preliminarily configured to control SMPS operating mode. Refer to function LL_PWR_SetBORConfig().
Reference Manual to LL API cross reference:
SR1 SMPSFBF LL_PWR_IsActiveFlag_SMPSFB
Return values:
State of bit (1 or 0).

Definition at line 2144 of file stm32wbxx_ll_pwr.h.

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FLAG management for radio (BLE or 802.15.4)

Functions
FLAG management for radio (BLE or 802.15.4)
PWR Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_BLEWU (void)
Get BLE wakeup interrupt flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_802WU (void)
Get 802.15.4 wakeup interrupt flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_BLEA (void)
Get BLE end of activity interrupt flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_802A (void)
Get 802.15.4 end of activity interrupt flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_CRPE (void)
Get critical radio phase end of activity interrupt flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_CRP (void)
Get critical radio system phase flag.
__STATIC_INLINE void | LL_PWR_ClearFlag_BLEWU (void)
Clear BLE wakeup interrupt flag.
__STATIC_INLINE void | LL_PWR_ClearFlag_802WU (void)
Clear 802.15.4 wakeup interrupt flag.
__STATIC_INLINE void | LL_PWR_ClearFlag_BLEA (void)
Clear BLE end of activity interrupt flag.
__STATIC_INLINE void | LL_PWR_ClearFlag_802A (void)
Clear 802.15.4 end of activity interrupt flag.
__STATIC_INLINE void | LL_PWR_ClearFlag_CRPE (void)
Clear critical radio phase end of activity interrupt flag.
__STATIC_INLINE void | LL_PWR_ClearFlag_CRP (void)
Clear critical radio system phase flag.

Function Documentation

__STATIC_INLINE void LL_PWR_ClearFlag_802A ( void )

Clear 802.15.4 end of activity interrupt flag.

Reference Manual to LL API cross reference:
SCR 802AF LL_PWR_ClearFlag_802A
Return values:
None

Definition at line 2267 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_802WU ( void )

Clear 802.15.4 wakeup interrupt flag.

Reference Manual to LL API cross reference:
SCR 802WU LL_PWR_ClearFlag_802WU
Return values:
None

Definition at line 2247 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_BLEA ( void )

Clear BLE end of activity interrupt flag.

Reference Manual to LL API cross reference:
SCR BLEAF LL_PWR_ClearFlag_BLEA
Return values:
None

Definition at line 2257 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_BLEWU ( void )

Clear BLE wakeup interrupt flag.

Reference Manual to LL API cross reference:
SCR BLEWU LL_PWR_ClearFlag_BLEWU
Return values:
None

Definition at line 2237 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_CRP ( void )

Clear critical radio system phase flag.

Reference Manual to LL API cross reference:
EXTSCR CCRP LL_PWR_ClearFlag_CRP
Return values:
None

Definition at line 2287 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_CRPE ( void )

Clear critical radio phase end of activity interrupt flag.

Reference Manual to LL API cross reference:
SCR CCRPEF LL_PWR_ClearFlag_CRPE
Return values:
None

Definition at line 2277 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_802A ( void )

Get 802.15.4 end of activity interrupt flag.

Reference Manual to LL API cross reference:
SR1 802AF LL_PWR_IsActiveFlag_802A
Return values:
State of bit (1 or 0).

Definition at line 2207 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_802WU ( void )

Get 802.15.4 wakeup interrupt flag.

Reference Manual to LL API cross reference:
SR1 802WUF LL_PWR_IsActiveFlag_802WU
Return values:
State of bit (1 or 0).

Definition at line 2187 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BLEA ( void )

Get BLE end of activity interrupt flag.

Reference Manual to LL API cross reference:
SR1 BLEAF LL_PWR_IsActiveFlag_BLEA
Return values:
State of bit (1 or 0).

Definition at line 2197 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BLEWU ( void )

Get BLE wakeup interrupt flag.

Reference Manual to LL API cross reference:
SR1 BLEWUF LL_PWR_IsActiveFlag_BLEWU
Return values:
State of bit (1 or 0).

Definition at line 2177 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_CRP ( void )

Get critical radio system phase flag.

Reference Manual to LL API cross reference:
EXTSCR CRPF LL_PWR_IsActiveFlag_CRP
Return values:
State of bit (1 or 0).

Definition at line 2227 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_CRPE ( void )

Get critical radio phase end of activity interrupt flag.

Reference Manual to LL API cross reference:
SR1 CRPEF LL_PWR_IsActiveFlag_CRPE
Return values:
State of bit (1 or 0).

Definition at line 2217 of file stm32wbxx_ll_pwr.h.

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FLAG management for multicore

Functions
FLAG management for multicore
PWR Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_C2H (void)
Get CPU2 hold interrupt flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_C1STOP (void)
Get system stop flag for CPU1.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_C1SB (void)
Get system standby flag for CPU1.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_C1DS (void)
Get deepsleep mode for CPU1.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_C2STOP (void)
System stop flag for CPU2.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_C2SB (void)
System standby flag for CPU2.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_C2DS (void)
Get deepsleep mode for CPU2.
__STATIC_INLINE void | LL_PWR_ClearFlag_C2H (void)
Clear CPU2 hold interrupt flag.
__STATIC_INLINE void | LL_PWR_ClearFlag_C1STOP_C1STB (void)
Clear standby and stop flags for CPU1.
__STATIC_INLINE void | LL_PWR_ClearFlag_C2STOP_C2STB (void)
Clear standby and stop flags for CPU2.

Function Documentation

__STATIC_INLINE void LL_PWR_ClearFlag_C1STOP_C1STB ( void )

Clear standby and stop flags for CPU1.

Reference Manual to LL API cross reference:
EXTSCR C1CSSF LL_PWR_ClearFlag_C1STOP_C1STB
Return values:
None

Definition at line 2384 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_C2H ( void )

Clear CPU2 hold interrupt flag.

Reference Manual to LL API cross reference:
SCR CC2HF LL_PWR_ClearFlag_C2H
Return values:
None

Definition at line 2375 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_C2STOP_C2STB ( void )

Clear standby and stop flags for CPU2.

Reference Manual to LL API cross reference:
EXTSCR C2CSSF LL_PWR_ClearFlag_C2STOP_C2STB
Return values:
None

Definition at line 2394 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C1DS ( void )

Get deepsleep mode for CPU1.

Reference Manual to LL API cross reference:
EXTSCR C1DS LL_PWR_IsActiveFlag_C1DS
Return values:
State of bit (1 or 0).

Definition at line 2335 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C1SB ( void )

Get system standby flag for CPU1.

Reference Manual to LL API cross reference:
EXTSCR C1SBF LL_PWR_IsActiveFlag_C1SB
Return values:
State of bit (1 or 0).

Definition at line 2325 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C1STOP ( void )

Get system stop flag for CPU1.

Reference Manual to LL API cross reference:
EXTSCR C1STOPF LL_PWR_IsActiveFlag_C1STOP
Return values:
State of bit (1 or 0).

Definition at line 2315 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C2DS ( void )

Get deepsleep mode for CPU2.

Reference Manual to LL API cross reference:
EXTSCR C2DS LL_PWR_IsActiveFlag_C2DS
Return values:
State of bit (1 or 0).

Definition at line 2365 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C2H ( void )

Get CPU2 hold interrupt flag.

Reference Manual to LL API cross reference:
SCR CC2HF LL_PWR_IsActiveFlag_C2H
Return values:
State of bit (1 or 0).

Definition at line 2305 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C2SB ( void )

System standby flag for CPU2.

Reference Manual to LL API cross reference:
EXTSCR C2SBF LL_PWR_IsActiveFlag_C2SB
Return values:
State of bit (1 or 0).

Definition at line 2355 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C2STOP ( void )

System stop flag for CPU2.

Reference Manual to LL API cross reference:
EXTSCR C2STOPF LL_PWR_IsActiveFlag_C2STOP
Return values:
State of bit (1 or 0).

Definition at line 2345 of file stm32wbxx_ll_pwr.h.

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PWR IT management for SMPS

Functions
PWR IT management for SMPS
PWR Exported Functions

Functions

__STATIC_INLINE void | LL_PWR_EnableIT_BORH_SMPSFB (void)
Enable SMPS step down converter forced in bypass mode by BORH interrupt for CPU1.
__STATIC_INLINE void | LL_PWR_DisableIT_BORH_SMPSFB (void)
Disable SMPS step down converter forced in bypass mode by BORH interrupt for CPU1.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledIT_BORH_SMPSFB (void)
Check if SMPS step down converter forced in bypass mode by BORH interrupt is enabled for CPU1.

Function Documentation

__STATIC_INLINE void LL_PWR_DisableIT_BORH_SMPSFB ( void )

Disable SMPS step down converter forced in bypass mode by BORH interrupt for CPU1.

Reference Manual to LL API cross reference:
CR3 EBORHSMPSFB LL_PWR_DisableIT_BORH_SMPSFB
Return values:
None

Definition at line 2429 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableIT_BORH_SMPSFB ( void )

Enable SMPS step down converter forced in bypass mode by BORH interrupt for CPU1.

Note:
To activate flag of SMPS step down converter forced in bypass mode by BORH, BOR must be preliminarily configured to control SMPS operating mode. Refer to function LL_PWR_SetBORConfig().
Reference Manual to LL API cross reference:
CR3 EBORHSMPSFB LL_PWR_EnableIT_BORH_SMPSFB
Return values:
None

Definition at line 2418 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledIT_BORH_SMPSFB ( void )

Check if SMPS step down converter forced in bypass mode by BORH interrupt is enabled for CPU1.

Reference Manual to LL API cross reference:
CR3 EBORHSMPSFB LL_PWR_IsEnabledIT_BORH_SMPSFB
Return values:
State of bit (1 or 0).

Definition at line 2440 of file stm32wbxx_ll_pwr.h.

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PWR IT management for radio (BLE or 802.15.4)

Functions
PWR IT management for radio (BLE or 802.15.4)
PWR Exported Functions

Functions

__STATIC_INLINE void | LL_PWR_EnableIT_BLEA (void)
Enable BLE end of activity interrupt for CPU1.
__STATIC_INLINE void | LL_PWR_EnableIT_802A (void)
Enable 802.15.4 end of activity interrupt for CPU1.
__STATIC_INLINE void | LL_PWR_DisableIT_BLEA (void)
Disable BLE end of activity interrupt for CPU1.
__STATIC_INLINE void | LL_PWR_DisableIT_802A (void)
Disable 802.15.4 end of activity interrupt for CPU1.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledIT_BLEA (void)
Check if BLE end of activity interrupt is enabled for CPU1.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledIT_802A (void)
Check if 802.15.4 end of activity interrupt is enabled for CPU1.
__STATIC_INLINE void | LL_PWR_EnableIT_CRPE (void)
Enable critical radio phase end of activity interrupt for CPU1.
__STATIC_INLINE void | LL_PWR_DisableIT_CRPE (void)
Disable critical radio phase end of activity interrupt for CPU1.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledIT_CRPE (void)
Check if critical radio phase end of activity interrupt is enabled for CPU1.

Function Documentation

__STATIC_INLINE void LL_PWR_DisableIT_802A ( void )

Disable 802.15.4 end of activity interrupt for CPU1.

Reference Manual to LL API cross reference:
CR3 E802A LL_PWR_DisableIT_802A
Return values:
None

Definition at line 2490 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableIT_BLEA ( void )

Disable BLE end of activity interrupt for CPU1.

Reference Manual to LL API cross reference:
CR3 EBLEA LL_PWR_DisableIT_BLEA
Return values:
None

Definition at line 2480 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableIT_CRPE ( void )

Disable critical radio phase end of activity interrupt for CPU1.

Reference Manual to LL API cross reference:
CR3 ECRPE LL_PWR_DisableIT_802A
Return values:
None

Definition at line 2530 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableIT_802A ( void )

Enable 802.15.4 end of activity interrupt for CPU1.

Reference Manual to LL API cross reference:
CR3 E802A LL_PWR_EnableIT_802A
Return values:
None

Definition at line 2469 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableIT_BLEA ( void )

Enable BLE end of activity interrupt for CPU1.

Reference Manual to LL API cross reference:
CR3 EBLEA LL_PWR_EnableIT_BLEA
Return values:
None

Definition at line 2459 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableIT_CRPE ( void )

Enable critical radio phase end of activity interrupt for CPU1.

Reference Manual to LL API cross reference:
CR3 ECRPE LL_PWR_EnableIT_802A
Return values:
None

Definition at line 2520 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledIT_802A ( void )

Check if 802.15.4 end of activity interrupt is enabled for CPU1.

Reference Manual to LL API cross reference:
CR3 E802A LL_PWR_IsEnabledIT_802A
Return values:
State of bit (1 or 0).

Definition at line 2510 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledIT_BLEA ( void )

Check if BLE end of activity interrupt is enabled for CPU1.

Reference Manual to LL API cross reference:
CR3 EBLEA LL_PWR_IsEnabledIT_BLEA
Return values:
State of bit (1 or 0).

Definition at line 2500 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledIT_CRPE ( void )

Check if critical radio phase end of activity interrupt is enabled for CPU1.

Reference Manual to LL API cross reference:
CR3 ECRPE LL_PWR_IsEnabledIT_802A
Return values:
State of bit (1 or 0).

Definition at line 2540 of file stm32wbxx_ll_pwr.h.

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PWR IT management for multicore

Functions
PWR IT management for multicore
PWR Exported Functions

Functions

__STATIC_INLINE void | LL_PWR_EnableIT_HoldCPU2 (void)
Enable CPU2 hold interrupt for CPU1.
__STATIC_INLINE void | LL_PWR_DisableIT_HoldCPU2 (void)
Disable 802.15.4 host wakeup interrupt for CPU2.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledIT_HoldCPU2 (void)
Check if BLE host wakeup interrupt is enabled for CPU2.

Function Documentation

__STATIC_INLINE void LL_PWR_DisableIT_HoldCPU2 ( void )

Disable 802.15.4 host wakeup interrupt for CPU2.

Reference Manual to LL API cross reference:
CR3 EC2H LL_PWR_DisableIT_HoldCPU2
Return values:
None

Definition at line 2568 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableIT_HoldCPU2 ( void )

Enable CPU2 hold interrupt for CPU1.

Reference Manual to LL API cross reference:
CR3 EC2H LL_PWR_EnableIT_HoldCPU2
Return values:
None

Definition at line 2558 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledIT_HoldCPU2 ( void )

Check if BLE host wakeup interrupt is enabled for CPU2.

Reference Manual to LL API cross reference:
CR3 EC2H LL_PWR_IsEnabledIT_HoldCPU2
Return values:
State of bit (1 or 0).

Definition at line 2578 of file stm32wbxx_ll_pwr.h.

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PWR IT management of CPU2, intended to be executed by CPU2

Functions
PWR IT management of CPU2, intended to be executed by CPU2
PWR Exported Functions

Functions

__STATIC_INLINE void | LL_C2_PWR_EnableIT_BLEWU (void)
Enable BLE host wakeup interrupt for CPU2.
__STATIC_INLINE void | LL_C2_PWR_EnableIT_802WU (void)
Enable 802.15.4 host wakeup interrupt for CPU2.
__STATIC_INLINE void | LL_C2_PWR_DisableIT_BLEWU (void)
Disable BLE host wakeup interrupt for CPU2.
__STATIC_INLINE void | LL_C2_PWR_DisableIT_802WU (void)
Disable 802.15.4 host wakeup interrupt for CPU2.
__STATIC_INLINE uint32_t | LL_C2_PWR_IsEnabledIT_BLEWU (void)
Check if BLE host wakeup interrupt is enabled for CPU2.
__STATIC_INLINE uint32_t | LL_C2_PWR_IsEnabledIT_802WU (void)
Check if 802.15.4 host wakeup interrupt is enabled for CPU2.

Function Documentation

__STATIC_INLINE void LL_C2_PWR_DisableIT_802WU ( void )

Disable 802.15.4 host wakeup interrupt for CPU2.

Reference Manual to LL API cross reference:
C2CR3 E802WUP LL_C2_PWR_DisableIT_802WU
Return values:
None

Definition at line 2626 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_C2_PWR_DisableIT_BLEWU ( void )

Disable BLE host wakeup interrupt for CPU2.

Reference Manual to LL API cross reference:
C2CR3 EBLEWUP LL_C2_PWR_DisableIT_BLEWU
Return values:
None

Definition at line 2616 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_C2_PWR_EnableIT_802WU ( void )

Enable 802.15.4 host wakeup interrupt for CPU2.

Reference Manual to LL API cross reference:
C2CR3 E802WUP LL_C2_PWR_EnableIT_802WU
Return values:
None

Definition at line 2606 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE void LL_C2_PWR_EnableIT_BLEWU ( void )

Enable BLE host wakeup interrupt for CPU2.

Reference Manual to LL API cross reference:
C2CR3 EBLEWUP LL_C2_PWR_EnableIT_BLEWU
Return values:
None

Definition at line 2596 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledIT_802WU ( void )

Check if 802.15.4 host wakeup interrupt is enabled for CPU2.

Reference Manual to LL API cross reference:
C2CR3 E802WUP LL_C2_PWR_IsEnabledIT_802WU
Return values:
State of bit (1 or 0).

Definition at line 2646 of file stm32wbxx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledIT_BLEWU ( void )

Check if BLE host wakeup interrupt is enabled for CPU2.

Reference Manual to LL API cross reference:
C2CR3 EBLEWUP LL_C2_PWR_IsEnabledIT_BLEWU
Return values:
State of bit (1 or 0).

Definition at line 2636 of file stm32wbxx_ll_pwr.h.

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: De-initialization function

Functions
De-initialization function
PWR Exported Functions

Functions

ErrorStatus LL_PWR_DeInit (void)
De-initialize the PWR registers to their default reset values.

Function Documentation

ErrorStatus LL_PWR_DeInit ( void )

De-initialize the PWR registers to their default reset values.

Return values:
An ErrorStatus enumeration value:
  • SUCCESS: PWR registers are de-initialized
  • ERROR: not applicable

Definition at line 84 of file stm32wbxx_ll_pwr.c.

References LL_PWR_EXTSCR_C1CSSF, LL_PWR_EXTSCR_C2CSSF, LL_PWR_EXTSCR_CCRPF, LL_PWR_SCR_C802AF, LL_PWR_SCR_C802WUF, LL_PWR_SCR_CBLEAF, LL_PWR_SCR_CBLEWUF, LL_PWR_SCR_CBORHF, LL_PWR_SCR_CC2HF, LL_PWR_SCR_CCRPEF, LL_PWR_SCR_CSMPSFBF, LL_PWR_SCR_CWUF, LL_PWR_WriteReg, PWR_C2CR1_RESET_VALUE, PWR_C2CR3_RESET_VALUE, PWR_CR1_RESET_VALUE, PWR_CR2_RESET_VALUE, PWR_CR3_RESET_VALUE, PWR_CR4_RESET_VALUE, PWR_CR5_RESET_VALUE, PWR_PDCRA_RESET_VALUE, PWR_PDCRB_RESET_VALUE, PWR_PDCRC_RESET_VALUE, PWR_PDCRD_RESET_VALUE, PWR_PDCRE_RESET_VALUE, PWR_PDCRH_RESET_VALUE, PWR_PUCRA_RESET_VALUE, PWR_PUCRB_RESET_VALUE, PWR_PUCRC_RESET_VALUE, PWR_PUCRD_RESET_VALUE, PWR_PUCRE_RESET_VALUE, and PWR_PUCRH_RESET_VALUE.

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RCC

Modules
RCC
STM32WBxx_LL_Driver

Modules

RCC Private functions
RCC Private Variables
RCC Private Macros
RCC Exported Types
RCC Exported Constants
RCC Exported Macros
RCC Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for RCC registers.

Register | Bit | Function
BDCR | BDRST | LL_RCC_ForceBackupDomainReset
 |  | LL_RCC_ReleaseBackupDomainReset
 | LSCOEN | LL_RCC_LSCO_Disable
 |  | LL_RCC_LSCO_Enable
 | LSCOSEL | LL_RCC_LSCO_GetSource
 |  | LL_RCC_LSCO_SetSource
 | LSEBYP | LL_RCC_LSE_DisableBypass
 |  | LL_RCC_LSE_EnableBypass
 | LSECSSD | LL_RCC_LSE_IsCSSDetected
 | LSECSSON | LL_RCC_LSE_DisableCSS
 |  | LL_RCC_LSE_EnableCSS
 | LSEDRV | LL_RCC_LSE_GetDriveCapability
 |  | LL_RCC_LSE_SetDriveCapability
 | LSEON | LL_RCC_LSE_Disable
 |  | LL_RCC_LSE_Enable
 |  | LL_RCC_LSE_IsEnabled
 | LSERDY | LL_RCC_LSE_IsReady
 | RTCEN | LL_RCC_DisableRTC
 |  | LL_RCC_EnableRTC
 |  | LL_RCC_IsEnabledRTC
 | RTCSEL | LL_RCC_GetRTCClockSource
 |  | LL_RCC_SetRTCClockSource
CCIPR | ADCSEL | LL_RCC_GetADCClockSource
 |  | LL_RCC_SetADCClockSource
 | CLK48SEL | LL_RCC_ConfigRNGClockSource
 |  | LL_RCC_GetCLK48ClockSource
 |  | LL_RCC_GetUSBClockSource
 |  | LL_RCC_SetCLK48ClockSource
 |  | LL_RCC_SetUSBClockSource
 | I2CxSEL | LL_RCC_GetI2CClockSource
 |  | LL_RCC_SetI2CClockSource
 | LPTIMxSEL | LL_RCC_GetLPTIMClockSource
 |  | LL_RCC_SetLPTIMClockSource
 | LPUART1SEL | LL_RCC_GetLPUARTClockSource
 |  | LL_RCC_SetLPUARTClockSource
 | RNGSEL | LL_RCC_ConfigRNGClockSource
 |  | LL_RCC_GetRNGClockSource
 |  | LL_RCC_SetRNGClockSource
 | SAI1SEL | LL_RCC_GetSAIClockSource
 |  | LL_RCC_SetSAIClockSource
 | USART1SEL | LL_RCC_GetUSARTClockSource
 |  | LL_RCC_SetUSARTClockSource
CFGR | HPRE | LL_RCC_GetAHBPrescaler
 |  | LL_RCC_SetAHBPrescaler
 | HPREF | LL_RCC_IsActiveFlag_HPRE
 | MCOPRE | LL_RCC_ConfigMCO
 | MCOSEL | LL_RCC_ConfigMCO
 | PPRE1 | LL_RCC_GetAPB1Prescaler
 |  | LL_RCC_SetAPB1Prescaler
 | PPRE1F | LL_RCC_IsActiveFlag_PPRE1
 | PPRE2 | LL_RCC_GetAPB2Prescaler
 |  | LL_RCC_SetAPB2Prescaler
 | PPRE2F | LL_RCC_IsActiveFlag_PPRE2
 | STOPWUCK | LL_RCC_GetClkAfterWakeFromStop
 |  | LL_RCC_SetClkAfterWakeFromStop
 | SW | LL_RCC_SetSysClkSource
 | SWS | LL_RCC_GetSysClkSource
CICR | CSSC | LL_RCC_ClearFlag_HSECSS
 | HSERDYC | LL_RCC_ClearFlag_HSERDY
 | HSI48RDYC | LL_RCC_ClearFlag_HSI48RDY
 | HSIRDYC | LL_RCC_ClearFlag_HSIRDY
 | LSECSSC | LL_RCC_ClearFlag_LSECSS
 | LSERDYC | LL_RCC_ClearFlag_LSERDY
 | LSI1RDYC | LL_RCC_ClearFlag_LSI1RDY
 | LSI2RDYC | LL_RCC_ClearFlag_LSI2RDY
 | MSIRDYC | LL_RCC_ClearFlag_MSIRDY
 | PLLRDYC | LL_RCC_ClearFlag_PLLRDY
 | PLLSAI1RDYC | LL_RCC_ClearFlag_PLLSAI1RDY
CIER | HSERDYIE | LL_RCC_DisableIT_HSERDY
 |  | LL_RCC_EnableIT_HSERDY
 |  | LL_RCC_IsEnabledIT_HSERDY
 | HSI48RDYIE | LL_RCC_DisableIT_HSI48RDY
 |  | LL_RCC_EnableIT_HSI48RDY
 |  | LL_RCC_IsEnabledIT_HSI48RDY
 | HSIRDYIE | LL_RCC_DisableIT_HSIRDY
 |  | LL_RCC_EnableIT_HSIRDY
 |  | LL_RCC_IsEnabledIT_HSIRDY
 | LSECSSIE | LL_RCC_DisableIT_LSECSS
 |  | LL_RCC_EnableIT_LSECSS
 |  | LL_RCC_IsEnabledIT_LSECSS
 | LSERDYIE | LL_RCC_DisableIT_LSERDY
 |  | LL_RCC_EnableIT_LSERDY
 |  | LL_RCC_IsEnabledIT_LSERDY
 | LSI1RDYIE | LL_RCC_DisableIT_LSI1RDY
 |  | LL_RCC_EnableIT_LSI1RDY
 |  | LL_RCC_IsEnabledIT_LSI1RDY
 | LSI2RDYIE | LL_RCC_DisableIT_LSI2RDY
 |  | LL_RCC_EnableIT_LSI2RDY
 |  | LL_RCC_IsEnabledIT_LSI2RDY
 | MSIRDYIE | LL_RCC_DisableIT_MSIRDY
 |  | LL_RCC_EnableIT_MSIRDY
 |  | LL_RCC_IsEnabledIT_MSIRDY
 | PLLRDYIE | LL_RCC_DisableIT_PLLRDY
 |  | LL_RCC_EnableIT_PLLRDY
 |  | LL_RCC_IsEnabledIT_PLLRDY
 | PLLSAI1RDYIE | LL_RCC_DisableIT_PLLSAI1RDY
 |  | LL_RCC_EnableIT_PLLSAI1RDY
 |  | LL_RCC_IsEnabledIT_PLLSAI1RDY
CIFR | CSSF | LL_RCC_IsActiveFlag_HSECSS
 | HSERDYF | LL_RCC_IsActiveFlag_HSERDY
 | HSI48RDYF | LL_RCC_IsActiveFlag_HSI48RDY
 | HSIRDYF | LL_RCC_IsActiveFlag_HSIRDY
 | LSECSSF | LL_RCC_IsActiveFlag_LSECSS
 | LSERDYF | LL_RCC_IsActiveFlag_LSERDY
 | LSI1RDYF | LL_RCC_IsActiveFlag_LSI1RDY
 | LSI2RDYF | LL_RCC_IsActiveFlag_LSI2RDY
 | MSIRDYF | LL_RCC_IsActiveFlag_MSIRDY
 | PLLRDYF | LL_RCC_IsActiveFlag_PLLRDY
 | PLLSAI1RDYF | LL_RCC_IsActiveFlag_PLLSAI1RDY
CR | CSSON | LL_RCC_HSE_EnableCSS
 | HSEBYP | LL_RCC_HSE_DisableBypass
 |  | LL_RCC_HSE_EnableBypass
 | HSEON | LL_RCC_HSE_Disable
 |  | LL_RCC_HSE_Enable
 | HSEPRE | LL_RCC_HSE_DisableDiv2
 |  | LL_RCC_HSE_EnableDiv2
 |  | LL_RCC_HSE_IsEnabledDiv2
 | HSERDY | LL_RCC_HSE_IsReady
 | HSIASFS | LL_RCC_HSI_DisableAutoFromStop
 |  | LL_RCC_HSI_EnableAutoFromStop
 | HSIKERON | LL_RCC_HSI_DisableInStopMode
 |  | LL_RCC_HSI_EnableInStopMode
 |  | LL_RCC_HSI_IsEnabledInStopMode
 | HSION | LL_RCC_HSI_Disable
 |  | LL_RCC_HSI_Enable
 | HSIRDY | LL_RCC_HSI_IsReady
 | MSION | LL_RCC_MSI_Disable
 |  | LL_RCC_MSI_Enable
 | MSIPLLEN | LL_RCC_MSI_DisablePLLMode
 |  | LL_RCC_MSI_EnablePLLMode
 | MSIRANGE | LL_RCC_MSI_GetRange
 |  | LL_RCC_MSI_SetRange
 | MSIRDY | LL_RCC_MSI_IsReady
 | PLLON | LL_RCC_PLL_Disable
 |  | LL_RCC_PLL_Enable
 | PLLRDY | LL_RCC_PLL_IsReady
 | PLLSAI1ON | LL_RCC_PLLSAI1_Disable
 |  | LL_RCC_PLLSAI1_Enable
 | PLLSAI1RDY | LL_RCC_PLLSAI1_IsReady
CRRCR | HSI48CAL | LL_RCC_HSI48_GetCalibration
 | HSI48ON | LL_RCC_HSI48_Disable
 |  | LL_RCC_HSI48_Enable
 | HSI48RDY | LL_RCC_HSI48_IsReady
CSR | BORRSTF | LL_RCC_IsActiveFlag_BORRST
 | IWDGRSTF | LL_RCC_IsActiveFlag_IWDGRST
 | LPWRRSTF | LL_RCC_IsActiveFlag_LPWRRST
 | LSI1ON | LL_RCC_LSI1_Disable
 |  | LL_RCC_LSI1_Enable
 | LSI1RDY | LL_RCC_LSI1_IsReady
 | LSI2ON | LL_RCC_LSI2_Disable
 |  | LL_RCC_LSI2_Enable
 | LSI2RDY | LL_RCC_LSI2_IsReady
 | LSI2TRIM | LL_RCC_LSI2_GetTrimming
 |  | LL_RCC_LSI2_SetTrimming
 | OBLRSTF | LL_RCC_IsActiveFlag_OBLRST
 | PINRSTF | LL_RCC_IsActiveFlag_PINRST
 | RFRSTS | LL_RCC_IsRFUnderReset
 | RFWKPSEL | LL_RCC_GetRFWKPClockSource
 |  | LL_RCC_SetRFWKPClockSource
 | RMVF | LL_RCC_ClearResetFlags
 | SFTRSTF | LL_RCC_IsActiveFlag_SFTRST
 | WWDGRSTF | LL_RCC_IsActiveFlag_WWDGRST
EXTCFGR | C2HPRE | LL_C2_RCC_GetAHBPrescaler
 |  | LL_C2_RCC_SetAHBPrescaler
 | C2HPREF | LL_RCC_IsActiveFlag_C2HPRE
 | RFCSS | LL_RCC_GetRFClockSource
 | SHDHPRE | LL_RCC_GetAHB4Prescaler
 |  | LL_RCC_SetAHB4Prescaler
 | SHDHPREF | LL_RCC_IsActiveFlag_SHDHPRE
HSECR | HSEGMC | LL_RCC_HSE_GetCurrentControl
 |  | LL_RCC_HSE_SetCurrentControl
 | HSES | LL_RCC_HSE_GetSenseAmplifier
 |  | LL_RCC_HSE_SetSenseAmplifier
 | HSETUNE | LL_RCC_HSE_GetCapacitorTuning
 |  | LL_RCC_HSE_SetCapacitorTuning
 | UNLOCKED | LL_RCC_HSE_IsClockControlLocked
ICSCR | HSICAL | LL_RCC_HSI_GetCalibration
 | HSITRIM | LL_RCC_HSI_GetCalibTrimming
 |  | LL_RCC_HSI_SetCalibTrimming
 | MSICAL | LL_RCC_MSI_GetCalibration
 | MSITRIM | LL_RCC_MSI_GetCalibTrimming
 |  | LL_RCC_MSI_SetCalibTrimming
PLLCFGR | PLLM | LL_RCC_PLLSAI1_ConfigDomain_48M
 |  | LL_RCC_PLLSAI1_ConfigDomain_ADC
 |  | LL_RCC_PLLSAI1_ConfigDomain_SAI
 |  | LL_RCC_PLL_ConfigDomain_48M
 |  | LL_RCC_PLL_ConfigDomain_ADC
 |  | LL_RCC_PLL_ConfigDomain_SAI
 |  | LL_RCC_PLL_ConfigDomain_SYS
 |  | LL_RCC_PLL_GetDivider
 | PLLN | LL_RCC_PLL_ConfigDomain_48M
 |  | LL_RCC_PLL_ConfigDomain_ADC
 |  | LL_RCC_PLL_ConfigDomain_SAI
 |  | LL_RCC_PLL_ConfigDomain_SYS
 |  | LL_RCC_PLL_GetN
 | PLLP | LL_RCC_PLL_ConfigDomain_ADC
 |  | LL_RCC_PLL_ConfigDomain_SAI
 |  | LL_RCC_PLL_GetP
 | PLLPEN | LL_RCC_PLL_DisableDomain_ADC
 |  | LL_RCC_PLL_DisableDomain_SAI
 |  | LL_RCC_PLL_EnableDomain_ADC
 |  | LL_RCC_PLL_EnableDomain_SAI
 | PLLQ | LL_RCC_PLL_ConfigDomain_48M
 |  | LL_RCC_PLL_GetQ
 | PLLQEN | LL_RCC_PLL_DisableDomain_48M
 |  | LL_RCC_PLL_EnableDomain_48M
 | PLLR | LL_RCC_PLL_ConfigDomain_SYS
 |  | LL_RCC_PLL_GetR
 | PLLREN | LL_RCC_PLL_DisableDomain_SYS
 |  | LL_RCC_PLL_EnableDomain_SYS
 | PLLSRC | LL_RCC_PLLSAI1_ConfigDomain_48M
 |  | LL_RCC_PLLSAI1_ConfigDomain_ADC
 |  | LL_RCC_PLLSAI1_ConfigDomain_SAI
 |  | LL_RCC_PLL_ConfigDomain_48M
 |  | LL_RCC_PLL_ConfigDomain_ADC
 |  | LL_RCC_PLL_ConfigDomain_SAI
 |  | LL_RCC_PLL_ConfigDomain_SYS
 |  | LL_RCC_PLL_GetMainSource
 |  | LL_RCC_PLL_SetMainSource
PLLSAI1CFGR | PLLN | LL_RCC_PLLSAI1_ConfigDomain_48M
 |  | LL_RCC_PLLSAI1_ConfigDomain_ADC
 |  | LL_RCC_PLLSAI1_ConfigDomain_SAI
 |  | LL_RCC_PLLSAI1_GetN
 | PLLP | LL_RCC_PLLSAI1_ConfigDomain_SAI
 |  | LL_RCC_PLLSAI1_GetP
 | PLLPEN | LL_RCC_PLLSAI1_DisableDomain_SAI
 |  | LL_RCC_PLLSAI1_EnableDomain_SAI
 | PLLQ | LL_RCC_PLLSAI1_ConfigDomain_48M
 |  | LL_RCC_PLLSAI1_GetQ
 | PLLQEN | LL_RCC_PLLSAI1_DisableDomain_48M
 |  | LL_RCC_PLLSAI1_EnableDomain_48M
 | PLLR | LL_RCC_PLLSAI1_ConfigDomain_ADC
 |  | LL_RCC_PLLSAI1_GetR
 | PLLREN | LL_RCC_PLLSAI1_DisableDomain_ADC
 |  | LL_RCC_PLLSAI1_EnableDomain_ADC
SMPSCR | SMPSDIV | LL_RCC_GetSMPSPrescaler
 |  | LL_RCC_SetSMPSPrescaler
 | SMPSSEL | LL_RCC_GetSMPSClockSelection
 |  | LL_RCC_SetSMPSClockSource
 | SMPSSWS | LL_RCC_GetSMPSClockSource
Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RCC Private functions

Functions
RCC Private functions
RCC

Functions

uint32_t | RCC_PLL_GetFreqDomain_SYS (void)
Return PLL clock (PLLRCLK) frequency used for system domain.
uint32_t | RCC_PLL_GetFreqDomain_SAI (void)
Return PLL clock (PLLPCLK) frequency used for SAI domain.
uint32_t | RCC_PLL_GetFreqDomain_ADC (void)
Return PLL clock (PLLPCLK) frequency used for ADC domain.
uint32_t | RCC_PLL_GetFreqDomain_48M (void)
Return PLL clock (PLLQCLK) frequency used for 48 MHz domain.
uint32_t | RCC_PLLSAI1_GetFreqDomain_SAI (void)
Return PLLSAI1 clock (PLLSAI1PCLK) frequency used for SAI domain.
uint32_t | RCC_PLLSAI1_GetFreqDomain_48M (void)
Return PLLSAI1 clock (PLLSAI1QCLK) frequency used for 48Mhz domain.
uint32_t | RCC_PLLSAI1_GetFreqDomain_ADC (void)
Return PLLSAI1 clock (PLLSAI1RCLK) frequency used for ADC domain.
uint32_t | RCC_GetSystemClockFreq (void)
Return SYSTEM clock (SYSCLK) frequency.
uint32_t | RCC_GetHCLK1ClockFreq (uint32_t SYSCLK_Frequency)
Return HCLK1 clock frequency.
uint32_t | RCC_GetHCLK2ClockFreq (uint32_t SYSCLK_Frequency)
Return HCLK2 clock frequency.
uint32_t | RCC_GetHCLK4ClockFreq (uint32_t SYSCLK_Frequency)
Return HCLK clock frequency.
uint32_t | RCC_GetHCLK5ClockFreq (void)
Return HCLK5 clock frequency.
uint32_t | RCC_GetPCLK1ClockFreq (uint32_t HCLK_Frequency)
Return PCLK1 clock frequency.
uint32_t | RCC_GetPCLK2ClockFreq (uint32_t HCLK_Frequency)
Return PCLK2 clock frequency.

Function Documentation

uint32_t RCC_GetHCLK1ClockFreq ( uint32_t SYSCLK_Frequency )

Return HCLK1 clock frequency.

Parameters:
SYSCLK_Frequency SYSCLK clock frequency
Return values:
HCLK1 clock frequency (in Hz)

Definition at line 937 of file stm32wbxx_ll_rcc.c.

References __LL_RCC_CALC_HCLK1_FREQ, and LL_RCC_GetAHBPrescaler().

Referenced by LL_RCC_GetI2CClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetSystemClocksFreq(), and LL_RCC_GetUSARTClockFreq().

uint32_t RCC_GetHCLK2ClockFreq ( uint32_t SYSCLK_Frequency )

Return HCLK2 clock frequency.

Parameters:
SYSCLK_Frequency SYSCLK clock frequency
Return values:
HCLK2 clock frequency (in Hz)

Definition at line 948 of file stm32wbxx_ll_rcc.c.

References __LL_RCC_CALC_HCLK2_FREQ, and LL_C2_RCC_GetAHBPrescaler().

Referenced by LL_RCC_GetSystemClocksFreq().

uint32_t RCC_GetHCLK4ClockFreq ( uint32_t SYSCLK_Frequency )

Return HCLK clock frequency.

Parameters:
SYSCLK_Frequency SYSCLK clock frequency
Return values:
HCLK4 clock frequency (in Hz)

Definition at line 959 of file stm32wbxx_ll_rcc.c.

References __LL_RCC_CALC_HCLK4_FREQ, and LL_RCC_GetAHB4Prescaler().

Referenced by LL_RCC_GetSystemClocksFreq().

uint32_t RCC_GetHCLK5ClockFreq ( void )

Return HCLK5 clock frequency.

Return values:
HCLK5 clock frequency (in Hz)

Definition at line 969 of file stm32wbxx_ll_rcc.c.

References HSE_VALUE, HSI_VALUE, LL_RCC_GetRFClockSource(), LL_RCC_RF_CLKSOURCE_HSE_DIV2, and LL_RCC_RF_CLKSOURCE_HSI.

Referenced by LL_RCC_GetSystemClocksFreq().

uint32_t RCC_GetPCLK1ClockFreq ( uint32_t HCLK_Frequency )

Return PCLK1 clock frequency.

Parameters:
HCLK_Frequency HCLK clock frequency
Return values:
PCLK1 clock frequency (in Hz)

Definition at line 999 of file stm32wbxx_ll_rcc.c.

References __LL_RCC_CALC_PCLK1_FREQ, and LL_RCC_GetAPB1Prescaler().

Referenced by LL_RCC_GetI2CClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), and LL_RCC_GetSystemClocksFreq().

uint32_t RCC_GetPCLK2ClockFreq ( uint32_t HCLK_Frequency )

Return PCLK2 clock frequency.

Parameters:
HCLK_Frequency HCLK clock frequency
Return values:
PCLK2 clock frequency (in Hz)

Definition at line 1010 of file stm32wbxx_ll_rcc.c.

References __LL_RCC_CALC_PCLK2_FREQ, and LL_RCC_GetAPB2Prescaler().

Referenced by LL_RCC_GetSystemClocksFreq(), and LL_RCC_GetUSARTClockFreq().

uint32_t RCC_GetSystemClockFreq ( void )

Return SYSTEM clock (SYSCLK) frequency.

Return values:
SYSTEM clock frequency (in Hz)

Definition at line 894 of file stm32wbxx_ll_rcc.c.

References __LL_RCC_CALC_MSI_FREQ, HSE_VALUE, HSI_VALUE, LL_RCC_GetSysClkSource(), LL_RCC_HSE_IsEnabledDiv2(), LL_RCC_MSI_GetRange(), LL_RCC_SYS_CLKSOURCE_STATUS_HSE, LL_RCC_SYS_CLKSOURCE_STATUS_HSI, LL_RCC_SYS_CLKSOURCE_STATUS_MSI, LL_RCC_SYS_CLKSOURCE_STATUS_PLL, and RCC_PLL_GetFreqDomain_SYS().

Referenced by LL_RCC_GetADCClockFreq(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetSystemClocksFreq(), and LL_RCC_GetUSARTClockFreq().

uint32_t RCC_PLL_GetFreqDomain_48M ( void )

Return PLL clock (PLLQCLK) frequency used for 48 MHz domain.

Return values:
PLLQCLK clock frequency (in Hz)

Definition at line 1150 of file stm32wbxx_ll_rcc.c.

References __LL_RCC_CALC_MSI_FREQ, __LL_RCC_CALC_PLLCLK_48M_FREQ, HSE_VALUE, HSI_VALUE, LL_RCC_HSE_IsEnabledDiv2(), LL_RCC_MSI_GetRange(), LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetMainSource(), LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ(), LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLSOURCE_HSI, and LL_RCC_PLLSOURCE_MSI.

Referenced by LL_RCC_GetCLK48ClockFreq().

uint32_t RCC_PLL_GetFreqDomain_ADC ( void )

Return PLL clock (PLLPCLK) frequency used for ADC domain.

Return values:
PLLPCLK clock frequency (in Hz)

Definition at line 1106 of file stm32wbxx_ll_rcc.c.

References __LL_RCC_CALC_MSI_FREQ, __LL_RCC_CALC_PLLCLK_ADC_FREQ, HSE_VALUE, HSI_VALUE, LL_RCC_HSE_IsEnabledDiv2(), LL_RCC_MSI_GetRange(), LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetMainSource(), LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP(), LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLSOURCE_HSI, and LL_RCC_PLLSOURCE_MSI.

Referenced by LL_RCC_GetADCClockFreq().

uint32_t RCC_PLL_GetFreqDomain_SAI ( void )

Return PLL clock (PLLPCLK) frequency used for SAI domain.

Return values:
PLLPCLK clock frequency (in Hz)

Definition at line 1063 of file stm32wbxx_ll_rcc.c.

References __LL_RCC_CALC_MSI_FREQ, __LL_RCC_CALC_PLLCLK_SAI_FREQ, HSE_VALUE, HSI_VALUE, LL_RCC_HSE_IsEnabledDiv2(), LL_RCC_MSI_GetRange(), LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetMainSource(), LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP(), LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLSOURCE_HSI, and LL_RCC_PLLSOURCE_MSI.

Referenced by LL_RCC_GetSAIClockFreq().

uint32_t RCC_PLL_GetFreqDomain_SYS ( void )

Return PLL clock (PLLRCLK) frequency used for system domain.

Return values:
PLLRCLK clock frequency (in Hz)

Definition at line 1020 of file stm32wbxx_ll_rcc.c.

References __LL_RCC_CALC_MSI_FREQ, __LL_RCC_CALC_PLLCLK_FREQ, HSE_VALUE, HSI_VALUE, LL_RCC_HSE_IsEnabledDiv2(), LL_RCC_MSI_GetRange(), LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetMainSource(), LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR(), LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLSOURCE_HSI, and LL_RCC_PLLSOURCE_MSI.

Referenced by RCC_GetSystemClockFreq().

uint32_t RCC_PLLSAI1_GetFreqDomain_48M ( void )

Return PLLSAI1 clock (PLLSAI1QCLK) frequency used for 48Mhz domain.

Return values:
PLLSAI1QCLK clock frequency (in Hz)

Definition at line 1236 of file stm32wbxx_ll_rcc.c.

References __LL_RCC_CALC_MSI_FREQ, __LL_RCC_CALC_PLLSAI1_48M_FREQ, HSE_VALUE, HSI_VALUE, LL_RCC_HSE_IsEnabledDiv2(), LL_RCC_MSI_GetRange(), LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetMainSource(), LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetQ(), LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLSOURCE_HSI, and LL_RCC_PLLSOURCE_MSI.

Referenced by LL_RCC_GetCLK48ClockFreq().

uint32_t RCC_PLLSAI1_GetFreqDomain_ADC ( void )

Return PLLSAI1 clock (PLLSAI1RCLK) frequency used for ADC domain.

Return values:
PLLSAI1RCLK clock frequency (in Hz)

Definition at line 1277 of file stm32wbxx_ll_rcc.c.

References __LL_RCC_CALC_MSI_FREQ, __LL_RCC_CALC_PLLSAI1_ADC_FREQ, HSE_VALUE, HSI_VALUE, LL_RCC_HSE_IsEnabledDiv2(), LL_RCC_MSI_GetRange(), LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetMainSource(), LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetR(), LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLSOURCE_HSI, and LL_RCC_PLLSOURCE_MSI.

Referenced by LL_RCC_GetADCClockFreq().

uint32_t RCC_PLLSAI1_GetFreqDomain_SAI ( void )

Return PLLSAI1 clock (PLLSAI1PCLK) frequency used for SAI domain.

Return values:
PLLSAI1PCLK clock frequency (in Hz)

Definition at line 1194 of file stm32wbxx_ll_rcc.c.

References __LL_RCC_CALC_MSI_FREQ, __LL_RCC_CALC_PLLSAI1_SAI_FREQ, HSE_VALUE, HSI_VALUE, LL_RCC_HSE_IsEnabledDiv2(), LL_RCC_MSI_GetRange(), LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetMainSource(), LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetP(), LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLSOURCE_HSI, and LL_RCC_PLLSOURCE_MSI.

Referenced by LL_RCC_GetSAIClockFreq().

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RCC Private Variables

Defines
RCC Private Variables
RCC

Defines

#define HSE_CONTROL_UNLOCK_KEY 0xCAFECAFEU

Define Documentation

#define HSE_CONTROL_UNLOCK_KEY 0xCAFECAFEU

Definition at line 47 of file stm32wbxx_ll_rcc.h.

Referenced by LL_RCC_DeInit(), LL_RCC_HSE_SetCapacitorTuning(), LL_RCC_HSE_SetCurrentControl(), and LL_RCC_HSE_SetSenseAmplifier().

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RCC Private Macros

Defines
RCC Private Macros
RCC

Defines

#define | IS_LL_RCC_USART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_USART1_CLKSOURCE)
#define | IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE)
#define | IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_SAI1_CLKSOURCE)
#define | IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
#define | IS_LL_RCC_CLK48_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CLK48_CLKSOURCE))
#define | IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
#define | IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))

Define Documentation

#define IS_LL_RCC_ADC_CLKSOURCE ( __VALUE__ ) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))

Definition at line 73 of file stm32wbxx_ll_rcc.c.

Referenced by LL_RCC_GetADCClockFreq().

#define IS_LL_RCC_CLK48_CLKSOURCE ( __VALUE__ ) (((__VALUE__) == LL_RCC_CLK48_CLKSOURCE))

Definition at line 67 of file stm32wbxx_ll_rcc.c.

Referenced by LL_RCC_GetCLK48ClockFreq().

#define IS_LL_RCC_I2C_CLKSOURCE ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
                                            || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))

Definition at line 52 of file stm32wbxx_ll_rcc.c.

Referenced by LL_RCC_GetI2CClockFreq().

#define IS_LL_RCC_LPTIM_CLKSOURCE ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \
                                            || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE))

Definition at line 58 of file stm32wbxx_ll_rcc.c.

Referenced by LL_RCC_GetLPTIMClockFreq().

#define IS_LL_RCC_LPUART_CLKSOURCE ( __VALUE__ ) ((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE)

Definition at line 48 of file stm32wbxx_ll_rcc.c.

Referenced by LL_RCC_GetLPUARTClockFreq().

#define IS_LL_RCC_RNG_CLKSOURCE ( __VALUE__ ) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))

Definition at line 65 of file stm32wbxx_ll_rcc.c.

Referenced by LL_RCC_GetRNGClockFreq().

#define IS_LL_RCC_SAI_CLKSOURCE ( __VALUE__ ) ((__VALUE__) == LL_RCC_SAI1_CLKSOURCE)

Definition at line 62 of file stm32wbxx_ll_rcc.c.

Referenced by LL_RCC_GetSAIClockFreq().

#define IS_LL_RCC_USART_CLKSOURCE ( __VALUE__ ) ((__VALUE__) == LL_RCC_USART1_CLKSOURCE)

Definition at line 45 of file stm32wbxx_ll_rcc.c.

Referenced by LL_RCC_GetUSARTClockFreq().

#define IS_LL_RCC_USB_CLKSOURCE ( __VALUE__ ) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))

Definition at line 70 of file stm32wbxx_ll_rcc.c.

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LL_RCC_ClocksTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_RCC_ClocksTypeDef Struct Reference
Clocks Frequency Structure

RCC Clocks Frequency Structure. More...

#include <stm32wbxx_ll_rcc.h>

Data Fields

uint32_t | SYSCLK_Frequency
uint32_t | HCLK1_Frequency
uint32_t | HCLK2_Frequency
uint32_t | HCLK4_Frequency
uint32_t | HCLK5_Frequency
uint32_t | PCLK1_Frequency
uint32_t | PCLK2_Frequency

Detailed Description

RCC Clocks Frequency Structure.

Definition at line 77 of file stm32wbxx_ll_rcc.h.

Field Documentation

uint32_t LL_RCC_ClocksTypeDef::HCLK1_Frequency

HCLK1 clock frequency

Definition at line 80 of file stm32wbxx_ll_rcc.h.

Referenced by LL_RCC_GetSystemClocksFreq().

uint32_t LL_RCC_ClocksTypeDef::HCLK2_Frequency

HCLK2 clock frequency

Definition at line 81 of file stm32wbxx_ll_rcc.h.

Referenced by LL_RCC_GetSystemClocksFreq().

uint32_t LL_RCC_ClocksTypeDef::HCLK4_Frequency

HCLK4 clock frequency

Definition at line 82 of file stm32wbxx_ll_rcc.h.

Referenced by LL_RCC_GetSystemClocksFreq().

uint32_t LL_RCC_ClocksTypeDef::HCLK5_Frequency

HCLK5 clock frequency

Definition at line 83 of file stm32wbxx_ll_rcc.h.

Referenced by LL_RCC_GetSystemClocksFreq().

uint32_t LL_RCC_ClocksTypeDef::PCLK1_Frequency

PCLK1 clock frequency

Definition at line 84 of file stm32wbxx_ll_rcc.h.

Referenced by LL_RCC_GetSystemClocksFreq().

uint32_t LL_RCC_ClocksTypeDef::PCLK2_Frequency

PCLK2 clock frequency

Definition at line 85 of file stm32wbxx_ll_rcc.h.

Referenced by LL_RCC_GetSystemClocksFreq().

uint32_t LL_RCC_ClocksTypeDef::SYSCLK_Frequency

SYSCLK clock frequency

Definition at line 79 of file stm32wbxx_ll_rcc.h.

Referenced by LL_LPTIM_Disable(), and LL_RCC_GetSystemClocksFreq().

The documentation for this struct was generated from the following file:
  • stm32wbxx_ll_rcc.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Oscillator Values adaptation

Oscillator Values adaptation
RCC Exported Constants

Defines used to adapt values of different oscillators. More...

Defines used to adapt values of different oscillators.

Note:
These values could be modified in the user environment according to HW set-up.
Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
RCC Exported Constants

Flags defines which can be used with LL_RCC_WriteReg function. More...

Defines

#define | LL_RCC_CICR_LSI1RDYC RCC_CICR_LSI1RDYC
#define | LL_RCC_CICR_LSI2RDYC RCC_CICR_LSI2RDYC
#define | LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC
#define | LL_RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC
#define | LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC
#define | LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC
#define | LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC
#define | LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC
#define | LL_RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC
#define | LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC
#define | LL_RCC_CICR_CSSC RCC_CICR_CSSC

Detailed Description

Flags defines which can be used with LL_RCC_WriteReg function.

Define Documentation

#define LL_RCC_CICR_CSSC RCC_CICR_CSSC

Clock Security System Interrupt Clear

Definition at line 147 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC

HSE Ready Interrupt Clear

Definition at line 140 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC

HSI48 Ready Interrupt Clear

Definition at line 142 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC

HSI Ready Interrupt Clear

Definition at line 139 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC

LSE Clock Security System Interrupt Clear

Definition at line 146 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC

LSE Ready Interrupt Clear

Definition at line 137 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_CICR_LSI1RDYC RCC_CICR_LSI1RDYC

LSI1 Ready Interrupt Clear

Definition at line 135 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_CICR_LSI2RDYC RCC_CICR_LSI2RDYC

LSI1 Ready Interrupt Clear

Definition at line 136 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC

MSI Ready Interrupt Clear

Definition at line 138 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC

PLL Ready Interrupt Clear

Definition at line 141 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC

PLLSAI1 Ready Interrupt Clear

Definition at line 144 of file stm32wbxx_ll_rcc.h.

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STM32WB55xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
RCC Exported Constants

Flags defines which can be used with LL_RCC_ReadReg function. More...

Defines

#define | LL_RCC_CIFR_LSI1RDYF RCC_CIFR_LSI1RDYF
#define | LL_RCC_CIFR_LSI2RDYF RCC_CIFR_LSI2RDYF
#define | LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF
#define | LL_RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF
#define | LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF
#define | LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF
#define | LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF
#define | LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF
#define | LL_RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF
#define | LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF
#define | LL_RCC_CIFR_CSSF RCC_CIFR_CSSF
#define | LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF
#define | LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF
#define | LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF
#define | LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF
#define | LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF
#define | LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF
#define | LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF

Detailed Description

Flags defines which can be used with LL_RCC_ReadReg function.

Define Documentation

#define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF

Clock Security System Interrupt flag

Definition at line 168 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF

HSE Ready Interrupt flag

Definition at line 161 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF

HSI48 Ready Interrupt flag

Definition at line 163 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF

HSI Ready Interrupt flag

Definition at line 160 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF

LSE Clock Security System Interrupt flag

Definition at line 167 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF

LSE Ready Interrupt flag

Definition at line 158 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_CIFR_LSI1RDYF RCC_CIFR_LSI1RDYF

LSI1 Ready Interrupt flag

Definition at line 156 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_CIFR_LSI2RDYF RCC_CIFR_LSI2RDYF

LSI2 Ready Interrupt flag

Definition at line 157 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF

MSI Ready Interrupt flag

Definition at line 159 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF

PLL Ready Interrupt flag

Definition at line 162 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF

PLLSAI1 Ready Interrupt flag

Definition at line 165 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF

BOR reset flag

Definition at line 175 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF

Independent Watchdog reset flag

Definition at line 173 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF

Low-Power reset flag

Definition at line 169 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF

OBL reset flag

Definition at line 170 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF

PIN reset flag

Definition at line 171 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF

Software Reset flag

Definition at line 172 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF

Window watchdog reset flag

Definition at line 174 of file stm32wbxx_ll_rcc.h.

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STM32WB55xx HAL User Manual: IT Defines

Defines
IT Defines
RCC Exported Constants

IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions. More...

Defines

#define | LL_RCC_CIER_LSI1RDYIE RCC_CIER_LSI1RDYIE
#define | LL_RCC_CIER_LSI2RDYIE RCC_CIER_LSI2RDYIE
#define | LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE
#define | LL_RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE
#define | LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE
#define | LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE
#define | LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE
#define | LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE
#define | LL_RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE
#define | LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE

Detailed Description

IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions.

Define Documentation

#define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE

HSE Ready Interrupt Enable

Definition at line 189 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE

HSI48 Ready Interrupt Enable

Definition at line 191 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE

HSI Ready Interrupt Enable

Definition at line 188 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE

LSE CSS Interrupt Enable

Definition at line 195 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE

LSE Ready Interrupt Enable

Definition at line 186 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_CIER_LSI1RDYIE RCC_CIER_LSI1RDYIE

LSI1 Ready Interrupt Enable

Definition at line 184 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_CIER_LSI2RDYIE RCC_CIER_LSI2RDYIE

LSI Ready Interrupt Enable

Definition at line 185 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE

MSI Ready Interrupt Enable

Definition at line 187 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE

PLL Ready Interrupt Enable

Definition at line 190 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE

PLLSAI1 Ready Interrupt Enable

Definition at line 193 of file stm32wbxx_ll_rcc.h.

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LSE oscillator drive capability

Defines
LSE oscillator drive capability
RCC Exported Constants

Defines

#define | LL_RCC_LSEDRIVE_LOW 0x00000000U
#define | LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0
#define | LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1
#define | LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV

Define Documentation

#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV

Xtal mode higher driving capability

Definition at line 206 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_LSEDRIVE_LOW 0x00000000U

Xtal mode lower driving capability

Definition at line 203 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1

Xtal mode medium high driving capability

Definition at line 205 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0

Xtal mode medium low driving capability

Definition at line 204 of file stm32wbxx_ll_rcc.h.

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STM32WB55xx HAL User Manual: MSI clock ranges

Defines
MSI clock ranges
RCC Exported Constants

Defines

#define | LL_RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0
#define | LL_RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1
#define | LL_RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2
#define | LL_RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3
#define | LL_RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4
#define | LL_RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5
#define | LL_RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6
#define | LL_RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7
#define | LL_RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8
#define | LL_RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9
#define | LL_RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10
#define | LL_RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11

Define Documentation

#define LL_RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0

MSI = 100 KHz

Definition at line 214 of file stm32wbxx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_MSI().

#define LL_RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1

MSI = 200 KHz

Definition at line 215 of file stm32wbxx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_MSI().

#define LL_RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10

MSI = 32 MHz

Definition at line 224 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), LL_PLL_ConfigSystemClock_MSI(), and LL_RCC_GetSMPSClockFreq().

#define LL_RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11

MSI = 48 MHz

Definition at line 225 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), LL_PLL_ConfigSystemClock_MSI(), LL_RCC_GetSMPSClockFreq(), and LL_RCC_MSI_GetRange().

#define LL_RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2

MSI = 400 KHz

Definition at line 216 of file stm32wbxx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_MSI().

#define LL_RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3

MSI = 800 KHz

Definition at line 217 of file stm32wbxx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_MSI().

#define LL_RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4

MSI = 1 MHz

Definition at line 218 of file stm32wbxx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_MSI().

#define LL_RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5

MSI = 2 MHz

Definition at line 219 of file stm32wbxx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_MSI().

#define LL_RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6

MSI = 4 MHz

Definition at line 220 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_DeInit(), LL_PLL_ConfigSystemClock_MSI(), and LL_RCC_DeInit().

#define LL_RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7

MSI = 8 MHz

Definition at line 221 of file stm32wbxx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_MSI().

#define LL_RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8

MSI = 16 MHz

Definition at line 222 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), LL_PLL_ConfigSystemClock_MSI(), and LL_RCC_GetSMPSClockFreq().

#define LL_RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9

MSI = 24 MHz

Definition at line 223 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), LL_PLL_ConfigSystemClock_MSI(), and LL_RCC_GetSMPSClockFreq().

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STM32WB55xx HAL User Manual: HSE current control max limits

Defines
HSE current control max limits
RCC Exported Constants

Defines

#define | LL_RCC_HSE_CURRENTMAX_0 0x000000000U
#define | LL_RCC_HSE_CURRENTMAX_1 RCC_HSECR_HSEGMC0
#define | LL_RCC_HSE_CURRENTMAX_2 RCC_HSECR_HSEGMC1
#define | LL_RCC_HSE_CURRENTMAX_3 (RCC_HSECR_HSEGMC1|RCC_HSECR_HSEGMC0)
#define | LL_RCC_HSE_CURRENTMAX_4 RCC_HSECR_HSEGMC2
#define | LL_RCC_HSE_CURRENTMAX_5 (RCC_HSECR_HSEGMC2|RCC_HSECR_HSEGMC0)
#define | LL_RCC_HSE_CURRENTMAX_6 (RCC_HSECR_HSEGMC2|RCC_HSECR_HSEGMC1)
#define | LL_RCC_HSE_CURRENTMAX_7 (RCC_HSECR_HSEGMC2|RCC_HSECR_HSEGMC1|RCC_HSECR_HSEGMC0)

Define Documentation

#define LL_RCC_HSE_CURRENTMAX_0 0x000000000U

HSE current control max limit = 0.18 ma/V

Definition at line 234 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_HSE_CURRENTMAX_1 RCC_HSECR_HSEGMC0

HSE current control max limit = 0.57 ma/V

Definition at line 235 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_HSE_CURRENTMAX_2 RCC_HSECR_HSEGMC1

HSE current control max limit = 0.78 ma/V

Definition at line 236 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_HSE_CURRENTMAX_3 (RCC_HSECR_HSEGMC1|RCC_HSECR_HSEGMC0)

HSE current control max limit = 1.13 ma/V

Definition at line 237 of file stm32wbxx_ll_rcc.h.

Referenced by LL_RCC_DeInit().

#define LL_RCC_HSE_CURRENTMAX_4 RCC_HSECR_HSEGMC2

HSE current control max limit = 0.61 ma/V

Definition at line 238 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_HSE_CURRENTMAX_5 (RCC_HSECR_HSEGMC2|RCC_HSECR_HSEGMC0)

HSE current control max limit = 1.65 ma/V

Definition at line 239 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_HSE_CURRENTMAX_6 (RCC_HSECR_HSEGMC2|RCC_HSECR_HSEGMC1)

HSE current control max limit = 2.12 ma/V

Definition at line 240 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_HSE_CURRENTMAX_7 (RCC_HSECR_HSEGMC2|RCC_HSECR_HSEGMC1|RCC_HSECR_HSEGMC0)

HSE current control max limit = 2.84 ma/V

Definition at line 241 of file stm32wbxx_ll_rcc.h.

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STM32WB55xx HAL User Manual: HSE sense amplifier threshold

Defines
HSE sense amplifier threshold
RCC Exported Constants

Defines

#define | LL_RCC_HSEAMPTHRESHOLD_1_2 (0x000000000U)
#define | LL_RCC_HSEAMPTHRESHOLD_3_4 RCC_HSECR_HSES

Define Documentation

#define LL_RCC_HSEAMPTHRESHOLD_1_2 (0x000000000U)

HSE sense amplifier bias current factor = 1/2

Definition at line 249 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_HSEAMPTHRESHOLD_3_4 RCC_HSECR_HSES

HSE sense amplifier bias current factor = 3/4

Definition at line 250 of file stm32wbxx_ll_rcc.h.

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LSCO Selection

Defines
LSCO Selection
RCC Exported Constants

Defines

#define | LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U
#define | LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL

Define Documentation

#define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL

LSE selection for low speed clock

Definition at line 259 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U

LSI selection for low speed clock

Definition at line 258 of file stm32wbxx_ll_rcc.h.

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STM32WB55xx HAL User Manual: System clock switch

Defines
System clock switch
RCC Exported Constants

Defines

#define | LL_RCC_SYS_CLKSOURCE_MSI 0x00000000U
#define | LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_0
#define | LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_1
#define | LL_RCC_SYS_CLKSOURCE_PLL (RCC_CFGR_SW_1 | RCC_CFGR_SW_0)

Define Documentation

#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_1

HSE selection as system clock

Definition at line 269 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_0

HSI selection as system clock

Definition at line 268 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_SYS_CLKSOURCE_MSI 0x00000000U

MSI selection as system clock

Definition at line 267 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_SYS_CLKSOURCE_PLL (RCC_CFGR_SW_1 | RCC_CFGR_SW_0)

PLL selection as system clock

Definition at line 270 of file stm32wbxx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

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STM32WB55xx HAL User Manual: System clock switch status

Defines
System clock switch status
RCC Exported Constants

Defines

#define | LL_RCC_SYS_CLKSOURCE_STATUS_MSI 0x00000000U
#define | LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_0
#define | LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_1
#define | LL_RCC_SYS_CLKSOURCE_STATUS_PLL (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0)

Define Documentation

#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_1

HSE used as system clock

Definition at line 280 of file stm32wbxx_ll_rcc.h.

Referenced by RCC_GetSystemClockFreq().

#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_0

HSI used as system clock

Definition at line 279 of file stm32wbxx_ll_rcc.h.

Referenced by RCC_GetSystemClockFreq().

#define LL_RCC_SYS_CLKSOURCE_STATUS_MSI 0x00000000U

MSI used as system clock

Definition at line 278 of file stm32wbxx_ll_rcc.h.

Referenced by LL_RCC_DeInit(), and RCC_GetSystemClockFreq().

#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0)

PLL used as system clock

Definition at line 281 of file stm32wbxx_ll_rcc.h.

Referenced by RCC_GetSystemClockFreq(), and UTILS_EnablePLLAndSwitchSystem().

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RF system clock switch status

Defines
RF system clock switch status
RCC Exported Constants

Defines

#define | LL_RCC_RF_CLKSOURCE_HSI 0x00000000U
#define | LL_RCC_RF_CLKSOURCE_HSE_DIV2 RCC_EXTCFGR_RFCSS

Define Documentation

#define LL_RCC_RF_CLKSOURCE_HSE_DIV2 RCC_EXTCFGR_RFCSS

HSE divided by 2 used as RF system clock

Definition at line 290 of file stm32wbxx_ll_rcc.h.

Referenced by RCC_GetHCLK5ClockFreq().

#define LL_RCC_RF_CLKSOURCE_HSI 0x00000000U

HSI used as RF system clock

Definition at line 289 of file stm32wbxx_ll_rcc.h.

Referenced by RCC_GetHCLK5ClockFreq().

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STM32WB55xx HAL User Manual: AHB prescaler

Defines
AHB prescaler
RCC Exported Constants

Defines

#define | LL_RCC_SYSCLK_DIV_1 0x00000000U
#define | LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_3
#define | LL_RCC_SYSCLK_DIV_3 RCC_CFGR_HPRE_0
#define | LL_RCC_SYSCLK_DIV_4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0)
#define | LL_RCC_SYSCLK_DIV_5 RCC_CFGR_HPRE_1
#define | LL_RCC_SYSCLK_DIV_6 (RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0)
#define | LL_RCC_SYSCLK_DIV_8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1)
#define | LL_RCC_SYSCLK_DIV_10 (RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1)
#define | LL_RCC_SYSCLK_DIV_16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0)
#define | LL_RCC_SYSCLK_DIV_32 (RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0)
#define | LL_RCC_SYSCLK_DIV_64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2)
#define | LL_RCC_SYSCLK_DIV_128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0)
#define | LL_RCC_SYSCLK_DIV_256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1)
#define | LL_RCC_SYSCLK_DIV_512 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0)

Define Documentation

#define LL_RCC_SYSCLK_DIV_1 0x00000000U

SYSCLK not divided

Definition at line 299 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_10 (RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1)

SYSCLK divided by 10

Definition at line 306 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0)

SYSCLK divided by 128

Definition at line 310 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0)

SYSCLK divided by 16

Definition at line 307 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_3

SYSCLK divided by 2

Definition at line 300 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1)

SYSCLK divided by 256

Definition at line 311 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_3 RCC_CFGR_HPRE_0

SYSCLK divided by 3

Definition at line 301 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_32 (RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0)

SYSCLK divided by 32

Definition at line 308 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0)

SYSCLK divided by 4

Definition at line 302 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_5 RCC_CFGR_HPRE_1

SYSCLK divided by 5

Definition at line 303 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_512 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0)

SYSCLK divided by 512

Definition at line 312 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_6 (RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0)

SYSCLK divided by 6

Definition at line 304 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2)

SYSCLK divided by 64

Definition at line 309 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1)

SYSCLK divided by 8

Definition at line 305 of file stm32wbxx_ll_rcc.h.

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STM32WB55xx HAL User Manual: APB low-speed prescaler (APB1)

Defines
APB low-speed prescaler (APB1)
RCC Exported Constants

Defines

#define | LL_RCC_APB1_DIV_1 0x00000000U
#define | LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_2
#define | LL_RCC_APB1_DIV_4 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_0)
#define | LL_RCC_APB1_DIV_8 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_1)
#define | LL_RCC_APB1_DIV_16 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_1 | RCC_CFGR_PPRE1_0)

Define Documentation

#define LL_RCC_APB1_DIV_1 0x00000000U

HCLK1 not divided

Definition at line 320 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_APB1_DIV_16 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_1 | RCC_CFGR_PPRE1_0)

HCLK1 divided by 16

Definition at line 324 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_2

HCLK1 divided by 2

Definition at line 321 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_APB1_DIV_4 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_0)

HCLK1 divided by 4

Definition at line 322 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_APB1_DIV_8 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_1)

HCLK1 divided by 8

Definition at line 323 of file stm32wbxx_ll_rcc.h.

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STM32WB55xx HAL User Manual: APB high-speed prescaler (APB2)

Defines
APB high-speed prescaler (APB2)
RCC Exported Constants

Defines

#define | LL_RCC_APB2_DIV_1 0x00000000U
#define | LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_2
#define | LL_RCC_APB2_DIV_4 (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_0)
#define | LL_RCC_APB2_DIV_8 (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_1)
#define | LL_RCC_APB2_DIV_16 (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_1 | RCC_CFGR_PPRE2_0)

Define Documentation

#define LL_RCC_APB2_DIV_1 0x00000000U

HCLK1 not divided

Definition at line 332 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_APB2_DIV_16 (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_1 | RCC_CFGR_PPRE2_0)

HCLK1 divided by 16

Definition at line 336 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_2

HCLK1 divided by 2

Definition at line 333 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_APB2_DIV_4 (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_0)

HCLK1 divided by 4

Definition at line 334 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_APB2_DIV_8 (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_1)

HCLK1 divided by 8

Definition at line 335 of file stm32wbxx_ll_rcc.h.

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STM32WB55xx HAL User Manual: Wakeup from Stop and CSS backup clock selection

Defines
Wakeup from Stop and CSS backup clock selection
RCC Exported Constants

Defines

#define | LL_RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U
#define | LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK

Define Documentation

#define LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK

HSI selection after wake-up from STOP

Definition at line 345 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U

MSI selection after wake-up from STOP

Definition at line 344 of file stm32wbxx_ll_rcc.h.

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STM32WB55xx HAL User Manual: MCO1 SOURCE selection

Defines
MCO1 SOURCE selection
RCC Exported Constants

Defines

#define | LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U
#define | LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0
#define | LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1
#define | LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1)
#define | LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2
#define | LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)
#define | LL_RCC_MCO1SOURCE_LSI1 (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)
#define | LL_RCC_MCO1SOURCE_LSI2 (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)
#define | LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_3
#define | LL_RCC_MCO1SOURCE_HSI48 (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_3)
#define | LL_RCC_MCO1SOURCE_HSE_BEFORE_STAB (RCC_CFGR_MCOSEL_2|RCC_CFGR_MCOSEL_3)

Define Documentation

#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2

HSE after stabilization selection as MCO1 source

Definition at line 357 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_HSE_BEFORE_STAB (RCC_CFGR_MCOSEL_2|RCC_CFGR_MCOSEL_3)

HSE before stabilization selection as MCO1 source

Definition at line 363 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1)

HSI selection as MCO1 source

Definition at line 356 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_HSI48 (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_3)

HSI48 selection as MCO1 source

Definition at line 362 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_3

LSE selection as MCO1 source

Definition at line 361 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_LSI1 (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)

LSI1 selection as MCO1 source

Definition at line 359 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_LSI2 (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)

LSI2 selection as MCO1 source

Definition at line 360 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1

MSI selection as MCO1 source

Definition at line 355 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U

MCO output disabled, no clock on MCO

Definition at line 353 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)

Main PLL selection as MCO1 source

Definition at line 358 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0

SYSCLK selection as MCO1 source

Definition at line 354 of file stm32wbxx_ll_rcc.h.

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STM32WB55xx HAL User Manual: MCO1 prescaler

Defines
MCO1 prescaler
RCC Exported Constants

Defines

#define | LL_RCC_MCO1_DIV_1 0x00000000U
#define | LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_0
#define | LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_1
#define | LL_RCC_MCO1_DIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0)
#define | LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_2

Define Documentation

#define LL_RCC_MCO1_DIV_1 0x00000000U

MCO not divided

Definition at line 371 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_2

MCO divided by 16

Definition at line 375 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_0

MCO divided by 2

Definition at line 372 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_1

MCO divided by 4

Definition at line 373 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_MCO1_DIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0)

MCO divided by 8

Definition at line 374 of file stm32wbxx_ll_rcc.h.

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STM32WB55xx HAL User Manual: SMPS clock switch

Defines
SMPS clock switch
RCC Exported Constants

Defines

#define | LL_RCC_SMPS_CLKSOURCE_HSI 0x00000000U
#define | LL_RCC_SMPS_CLKSOURCE_MSI RCC_SMPSCR_SMPSSEL_0
#define | LL_RCC_SMPS_CLKSOURCE_HSE RCC_SMPSCR_SMPSSEL_1

Define Documentation

#define LL_RCC_SMPS_CLKSOURCE_HSE RCC_SMPSCR_SMPSSEL_1

HSE selection as SMPS clock

Definition at line 385 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_SMPS_CLKSOURCE_HSI 0x00000000U

HSI selection as SMPS clock

Definition at line 383 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_SMPS_CLKSOURCE_MSI RCC_SMPSCR_SMPSSEL_0

MSI selection as SMPS clock

Definition at line 384 of file stm32wbxx_ll_rcc.h.

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STM32WB55xx HAL User Manual: SMPS clock switch status

Defines
SMPS clock switch status
RCC Exported Constants

Defines

#define | LL_RCC_SMPS_CLKSOURCE_STATUS_HSI 0x00000000U
#define | LL_RCC_SMPS_CLKSOURCE_STATUS_MSI RCC_SMPSCR_SMPSSWS_0
#define | LL_RCC_SMPS_CLKSOURCE_STATUS_HSE RCC_SMPSCR_SMPSSWS_1
#define | LL_RCC_SMPS_CLKSOURCE_STATUS_NO_CLOCK (RCC_SMPSCR_SMPSSWS_0|RCC_SMPSCR_SMPSSWS_1)

Define Documentation

#define LL_RCC_SMPS_CLKSOURCE_STATUS_HSE RCC_SMPSCR_SMPSSWS_1

HSE used as SMPS clock

Definition at line 396 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetSMPSClockFreq().

#define LL_RCC_SMPS_CLKSOURCE_STATUS_HSI 0x00000000U

HSI used as SMPS clock

Definition at line 394 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetSMPSClockFreq().

#define LL_RCC_SMPS_CLKSOURCE_STATUS_MSI RCC_SMPSCR_SMPSSWS_0

MSI used as SMPS clock

Definition at line 395 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetSMPSClockFreq().

#define LL_RCC_SMPS_CLKSOURCE_STATUS_NO_CLOCK (RCC_SMPSCR_SMPSSWS_0|RCC_SMPSCR_SMPSSWS_1)

No Clock used as SMPS clock

Definition at line 397 of file stm32wbxx_ll_rcc.h.

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STM32WB55xx HAL User Manual: SMPS prescaler

Defines
SMPS prescaler
RCC Exported Constants

Defines

#define | LL_RCC_SMPS_DIV_0 (0x00000000U)
#define | LL_RCC_SMPS_DIV_1 RCC_SMPSCR_SMPSDIV_0
#define | LL_RCC_SMPS_DIV_2 RCC_SMPSCR_SMPSDIV_1
#define | LL_RCC_SMPS_DIV_3 (RCC_SMPSCR_SMPSDIV_0|RCC_SMPSCR_SMPSDIV_1)

Define Documentation

#define LL_RCC_SMPS_DIV_0 (0x00000000U)

SMPS clock division 0

Definition at line 406 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_SMPS_DIV_1 RCC_SMPSCR_SMPSDIV_0

SMPS clock division 1

Definition at line 407 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_SMPS_DIV_2 RCC_SMPSCR_SMPSDIV_1

SMPS clock division 2

Definition at line 408 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_SMPS_DIV_3 (RCC_SMPSCR_SMPSDIV_0|RCC_SMPSCR_SMPSDIV_1)

SMPS clock division 3

Definition at line 409 of file stm32wbxx_ll_rcc.h.

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STM32WB55xx HAL User Manual: Peripheral clock frequency

Defines
Peripheral clock frequency
RCC Exported Constants

Defines

#define | LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U
#define | LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU

Define Documentation

#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU

Frequency cannot be provided as external clock

Definition at line 423 of file stm32wbxx_ll_rcc.h.

Referenced by LL_RCC_GetADCClockFreq(), LL_RCC_GetRFWKPClockFreq(), LL_RCC_GetRTCClockFreq(), and LL_RCC_GetSAIClockFreq().

#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U

No clock enabled for the peripheral

Definition at line 422 of file stm32wbxx_ll_rcc.h.

Referenced by LL_LPUART_Init(), LL_RCC_GetADCClockFreq(), LL_RCC_GetCLK48ClockFreq(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetRFWKPClockFreq(), LL_RCC_GetRNGClockFreq(), LL_RCC_GetRTCClockFreq(), LL_RCC_GetSAIClockFreq(), LL_RCC_GetSMPSClockFreq(), LL_RCC_GetUSARTClockFreq(), and LL_USART_Init().

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STM32WB55xx HAL User Manual: USART1 CLKSOURCE

Defines
USART1 CLKSOURCE
RCC Exported Constants

Defines

#define | LL_RCC_USART1_CLKSOURCE_PCLK2 0x00000000U
#define | LL_RCC_USART1_CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0
#define | LL_RCC_USART1_CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1
#define | LL_RCC_USART1_CLKSOURCE_LSE RCC_CCIPR_USART1SEL

Define Documentation

#define LL_RCC_USART1_CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1

HSI selected as USART1 clock

Definition at line 434 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART1_CLKSOURCE_LSE RCC_CCIPR_USART1SEL

LSE selected as USART1 clock

Definition at line 435 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART1_CLKSOURCE_PCLK2 0x00000000U

PCLK2 selected as USART1 clock

Definition at line 432 of file stm32wbxx_ll_rcc.h.

Referenced by LL_RCC_GetUSARTClockFreq().

#define LL_RCC_USART1_CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0

SYSCLK selected as USART1 clock

Definition at line 433 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetUSARTClockFreq().

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STM32WB55xx HAL User Manual: LPUART1 CLKSOURCE

Defines
LPUART1 CLKSOURCE
RCC Exported Constants

Defines

#define | LL_RCC_LPUART1_CLKSOURCE_PCLK1 0x00000000U
#define | LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
#define | LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
#define | LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL

Define Documentation

#define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1

HSI selected as LPUART1 clock

Definition at line 445 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetLPUARTClockFreq().

#define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL

LSE selected as LPUART1 clock

Definition at line 446 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetLPUARTClockFreq().

#define LL_RCC_LPUART1_CLKSOURCE_PCLK1 0x00000000U

PCLK1 selected as LPUART1 clock

Definition at line 443 of file stm32wbxx_ll_rcc.h.

Referenced by LL_RCC_GetLPUARTClockFreq().

#define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0

SYCLK selected as LPUART1 clock

Definition at line 444 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetLPUARTClockFreq().

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STM32WB55xx HAL User Manual: I2Cx CLKSOURCE

Defines
I2Cx CLKSOURCE
RCC Exported Constants

Defines

#define | LL_RCC_I2C1_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (0x00000000U >> 4))
#define | LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_0 >> 4))
#define | LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_1 >> 4))
#define | LL_RCC_I2C3_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (0x00000000U >> 4))
#define | LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_0 >> 4))
#define | LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_1 >> 4))

Define Documentation

#define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_1 >> 4))

HSI selected as I2C1 clock

Definition at line 456 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C1_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (0x00000000U >> 4))

PCLK1 selected as I2C1 clock

Definition at line 454 of file stm32wbxx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_0 >> 4))

SYSCLK selected as I2C1 clock

Definition at line 455 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_1 >> 4))

HSI selected as I2C3 clock

Definition at line 460 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C3_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (0x00000000U >> 4))

PCLK1 selected as I2C3 clock

Definition at line 458 of file stm32wbxx_ll_rcc.h.

Referenced by LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_0 >> 4))

SYSCLK selected as I2C3 clock

Definition at line 459 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetI2CClockFreq().

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STM32WB55xx HAL User Manual: LPTIMx CLKSOURCE

Defines
LPTIMx CLKSOURCE
RCC Exported Constants

Defines

#define | LL_RCC_LPTIM1_CLKSOURCE_PCLK1 (uint32_t)(RCC_CCIPR_LPTIM1SEL | (0x00000000U >> 16))
#define | LL_RCC_LPTIM1_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16))
#define | LL_RCC_LPTIM1_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16))
#define | LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16))
#define | LL_RCC_LPTIM2_CLKSOURCE_PCLK1 (uint32_t)(RCC_CCIPR_LPTIM2SEL | (0x00000000U >> 16))
#define | LL_RCC_LPTIM2_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16))
#define | LL_RCC_LPTIM2_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16))
#define | LL_RCC_LPTIM2_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16))

Define Documentation

#define LL_RCC_LPTIM1_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16))

HSI selected as LPTIM1 clock

Definition at line 471 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16))

LSE selected as LPTIM1 clock

Definition at line 472 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM1_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16))

LSI selected as LPTIM1 clock

Definition at line 470 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 (uint32_t)(RCC_CCIPR_LPTIM1SEL | (0x00000000U >> 16))

PCLK1 selected as LPTIM1 clock

Definition at line 469 of file stm32wbxx_ll_rcc.h.

Referenced by LL_LPTIM_Disable(), and LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM2_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16))

HSI selected as LPTIM2 clock

Definition at line 475 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM2_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16))

LSE selected as LPTIM2 clock

Definition at line 476 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM2_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16))

LSI selected as LPTIM2 clock

Definition at line 474 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 (uint32_t)(RCC_CCIPR_LPTIM2SEL | (0x00000000U >> 16))

PCLK1 selected as LPTIM2 clock

Definition at line 473 of file stm32wbxx_ll_rcc.h.

Referenced by LL_LPTIM_Disable(), and LL_RCC_GetLPTIMClockFreq().

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STM32WB55xx HAL User Manual: SAI1 CLKSOURCE

Defines
SAI1 CLKSOURCE
RCC Exported Constants

Defines

#define | LL_RCC_SAI1_CLKSOURCE_PLLSAI1 0x00000000U
#define | LL_RCC_SAI1_CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_0
#define | LL_RCC_SAI1_CLKSOURCE_HSI RCC_CCIPR_SAI1SEL_1
#define | LL_RCC_SAI1_CLKSOURCE_PIN RCC_CCIPR_SAI1SEL

Define Documentation

#define LL_RCC_SAI1_CLKSOURCE_HSI RCC_CCIPR_SAI1SEL_1

HSI selected as SAI1 clock

Definition at line 486 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetSAIClockFreq().

#define LL_RCC_SAI1_CLKSOURCE_PIN RCC_CCIPR_SAI1SEL

External input selected as SAI1 clock

Definition at line 487 of file stm32wbxx_ll_rcc.h.

Referenced by LL_RCC_GetSAIClockFreq().

#define LL_RCC_SAI1_CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_0

PLL selected as SAI1 clock

Definition at line 485 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetSAIClockFreq().

#define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 0x00000000U

PLLSAI1 selected as SAI1 clock

Definition at line 484 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetSAIClockFreq().

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STM32WB55xx HAL User Manual: CLK48 CLKSOURCE

Defines
CLK48 CLKSOURCE
RCC Exported Constants

Defines

#define | LL_RCC_CLK48_CLKSOURCE_HSI48 0x00000000U
#define | LL_RCC_CLK48_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
#define | LL_RCC_CLK48_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
#define | LL_RCC_CLK48_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL

Define Documentation

#define LL_RCC_CLK48_CLKSOURCE_HSI48 0x00000000U

HSI48 selected as CLK48 clock

Definition at line 495 of file stm32wbxx_ll_rcc.h.

Referenced by LL_RCC_GetCLK48ClockFreq().

#define LL_RCC_CLK48_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL

MSI selected as CLK48 clock

Definition at line 500 of file stm32wbxx_ll_rcc.h.

Referenced by LL_RCC_GetCLK48ClockFreq().

#define LL_RCC_CLK48_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1

PLL selected as CLK48 clock

Definition at line 499 of file stm32wbxx_ll_rcc.h.

Referenced by LL_RCC_GetCLK48ClockFreq().

#define LL_RCC_CLK48_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0

PLLSAI1 selected as CLK48 clock

Definition at line 497 of file stm32wbxx_ll_rcc.h.

Referenced by LL_RCC_GetCLK48ClockFreq().

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STM32WB55xx HAL User Manual: USB CLKSOURCE

Defines
USB CLKSOURCE
RCC Exported Constants

Defines

#define | LL_RCC_USB_CLKSOURCE_HSI48 LL_RCC_CLK48_CLKSOURCE_HSI48
#define | LL_RCC_USB_CLKSOURCE_PLLSAI1 LL_RCC_CLK48_CLKSOURCE_PLLSAI1
#define | LL_RCC_USB_CLKSOURCE_PLL LL_RCC_CLK48_CLKSOURCE_PLL
#define | LL_RCC_USB_CLKSOURCE_MSI LL_RCC_CLK48_CLKSOURCE_MSI

Define Documentation

#define LL_RCC_USB_CLKSOURCE_HSI48 LL_RCC_CLK48_CLKSOURCE_HSI48

HSI48 selected as USB clock

Definition at line 508 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_USB_CLKSOURCE_MSI LL_RCC_CLK48_CLKSOURCE_MSI

MSI selected as USB clock

Definition at line 513 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define LL_RCC_USB_CLKSOURCE_PLL LL_RCC_CLK48_CLKSOURCE_PLL

PLL selected as USB clock

Definition at line 512 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define LL_RCC_USB_CLKSOURCE_PLLSAI1 LL_RCC_CLK48_CLKSOURCE_PLLSAI1

PLLSAI1 selected as USB clock

Definition at line 510 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

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STM32WB55xx HAL User Manual: ADC CLKSRC

Defines
ADC CLKSRC
RCC Exported Constants

Defines

#define | LL_RCC_ADC_CLKSOURCE_NONE 0x00000000U
#define | LL_RCC_ADC_CLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0
#define | LL_RCC_ADC_CLKSOURCE_PLL RCC_CCIPR_ADCSEL_1
#define | LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL

Define Documentation

#define LL_RCC_ADC_CLKSOURCE_NONE 0x00000000U

no Clock used as ADC clock

Definition at line 521 of file stm32wbxx_ll_rcc.h.

Referenced by LL_RCC_GetADCClockFreq().

#define LL_RCC_ADC_CLKSOURCE_PLL RCC_CCIPR_ADCSEL_1

PLL selected as ADC clock

Definition at line 525 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetADCClockFreq().

#define LL_RCC_ADC_CLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0

PLLSAI1 selected as ADC clock

Definition at line 523 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetADCClockFreq().

#define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL

SYSCLK selected as ADC clock

Definition at line 526 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetADCClockFreq().

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STM32WB55xx HAL User Manual: RNG CLKSRC

Defines
RNG CLKSRC
RCC Exported Constants

Defines

#define | LL_RCC_RNG_CLKSOURCE_CLK48 0x00000000U
#define | LL_RCC_RNG_CLKSOURCE_LSI RCC_CCIPR_RNGSEL_0
#define | LL_RCC_RNG_CLKSOURCE_LSE RCC_CCIPR_RNGSEL_1

Define Documentation

#define LL_RCC_RNG_CLKSOURCE_CLK48 0x00000000U

CLK48 divided by 3 selected as RNG Clock

Definition at line 534 of file stm32wbxx_ll_rcc.h.

Referenced by LL_RCC_ConfigRNGClockSource().

#define LL_RCC_RNG_CLKSOURCE_LSE RCC_CCIPR_RNGSEL_1

LSE selected as ADC clock

Definition at line 536 of file stm32wbxx_ll_rcc.h.

Referenced by LL_RCC_GetRNGClockFreq().

#define LL_RCC_RNG_CLKSOURCE_LSI RCC_CCIPR_RNGSEL_0

LSI selected as ADC clock

Definition at line 535 of file stm32wbxx_ll_rcc.h.

Referenced by LL_RCC_GetRNGClockFreq().

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STM32WB55xx HAL User Manual: USART1

Defines
USART1
RCC Exported Constants

Defines

#define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL

Define Documentation

#define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL

USART1 clock source selection bits

Definition at line 544 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_USART_Init().

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STM32WB55xx HAL User Manual: LPUART1

Defines
LPUART1
RCC Exported Constants

Defines

#define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL

Define Documentation

#define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL

LPUART1 clock source selection bits

Definition at line 553 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_LPUART_Init().

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STM32WB55xx HAL User Manual: I2C1

Defines
I2C1
RCC Exported Constants

Defines

#define | LL_RCC_I2C1_CLKSOURCE RCC_CCIPR_I2C1SEL
#define | LL_RCC_I2C3_CLKSOURCE RCC_CCIPR_I2C3SEL

Define Documentation

#define LL_RCC_I2C1_CLKSOURCE RCC_CCIPR_I2C1SEL

I2C1 clock source selection bits

Definition at line 562 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetI2CClockFreq().

#define LL_RCC_I2C3_CLKSOURCE RCC_CCIPR_I2C3SEL

I2C3 clock source selection bits

Definition at line 563 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

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STM32WB55xx HAL User Manual: LPTIM1

Defines
LPTIM1
RCC Exported Constants

Defines

#define | LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL
#define | LL_RCC_LPTIM2_CLKSOURCE RCC_CCIPR_LPTIM2SEL

Define Documentation

#define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL

LPTIM1 clock source selection bits

Definition at line 571 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), LL_LPTIM_Disable(), and LL_RCC_GetLPTIMClockFreq().

#define LL_RCC_LPTIM2_CLKSOURCE RCC_CCIPR_LPTIM2SEL

LPTIM2 clock source selection bits

Definition at line 572 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_LPTIM_Disable().

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STM32WB55xx HAL User Manual: SAI1

Defines
SAI1
RCC Exported Constants

Defines

#define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR_SAI1SEL

Define Documentation

#define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR_SAI1SEL

SAI1 clock source selection bits

Definition at line 581 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

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STM32WB55xx HAL User Manual: CLK48

Defines
CLK48
RCC Exported Constants

Defines

#define LL_RCC_CLK48_CLKSOURCE RCC_CCIPR_CLK48SEL

Define Documentation

#define LL_RCC_CLK48_CLKSOURCE RCC_CCIPR_CLK48SEL

USB clock source selection bits

Definition at line 590 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetRngCLKSource(), and LL_RCC_GetRNGClockFreq().

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STM32WB55xx HAL User Manual: USB

Defines
USB
RCC Exported Constants

Defines

#define LL_RCC_USB_CLKSOURCE LL_RCC_CLK48_CLKSOURCE

Define Documentation

#define LL_RCC_USB_CLKSOURCE LL_RCC_CLK48_CLKSOURCE

USB clock source selection bits

Definition at line 598 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

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STM32WB55xx HAL User Manual: RNG

Defines
RNG
RCC Exported Constants

Defines

#define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_RNGSEL

Define Documentation

#define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_RNGSEL

RNG clock source selection bits

Definition at line 606 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetRngCLKSource().

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STM32WB55xx HAL User Manual: ADC

Defines
ADC
RCC Exported Constants

Defines

#define LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL

Define Documentation

#define LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL

ADC clock source selection bits

Definition at line 614 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

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STM32WB55xx HAL User Manual: RTC clock source selection

Defines
RTC clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U
#define | LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0
#define | LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1
#define | LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL

Define Documentation

#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL

HSE oscillator clock divided by 32 used as RTC clock

Definition at line 625 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetRTCClockFreq().

#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0

LSE oscillator clock used as RTC clock

Definition at line 623 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetRTCClockFreq().

#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1

LSI oscillator clock used as RTC clock

Definition at line 624 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetRTCClockFreq().

#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U

No clock used as RTC clock

Definition at line 622 of file stm32wbxx_ll_rcc.h.

Referenced by LL_RCC_GetRTCClockFreq().

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STM32WB55xx HAL User Manual: RF Wakeup clock source selection

Defines
RF Wakeup clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_RFWKP_CLKSOURCE_NONE 0x00000000U
#define | LL_RCC_RFWKP_CLKSOURCE_LSE RCC_CSR_RFWKPSEL_0
#define | LL_RCC_RFWKP_CLKSOURCE_LSI RCC_CSR_RFWKPSEL_1
#define | LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024 RCC_CSR_RFWKPSEL

Define Documentation

#define LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024 RCC_CSR_RFWKPSEL

HSE oscillator clock divided by 1024 used as RF Wakeup clock

Definition at line 637 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetRFWKPClockFreq().

#define LL_RCC_RFWKP_CLKSOURCE_LSE RCC_CSR_RFWKPSEL_0

LSE oscillator clock used as RF Wakeup clock

Definition at line 635 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetRFWKPClockFreq().

#define LL_RCC_RFWKP_CLKSOURCE_LSI RCC_CSR_RFWKPSEL_1

LSI oscillator clock used as RF Wakeup clock

Definition at line 636 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetRFWKPClockFreq().

#define LL_RCC_RFWKP_CLKSOURCE_NONE 0x00000000U

No clock used as RF Wakeup clock

Definition at line 634 of file stm32wbxx_ll_rcc.h.

Referenced by LL_RCC_DeInit(), and LL_RCC_GetRFWKPClockFreq().

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STM32WB55xx HAL User Manual: PLL and PLLSAI1 entry clock source

Defines
PLL and PLLSAI1 entry clock source
RCC Exported Constants

Defines

#define | LL_RCC_PLLSOURCE_NONE 0x00000000U
#define | LL_RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_0
#define | LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_1
#define | LL_RCC_PLLSOURCE_HSE (RCC_PLLCFGR_PLLSRC_1 | RCC_PLLCFGR_PLLSRC_0)

Define Documentation

#define LL_RCC_PLLSOURCE_HSE (RCC_PLLCFGR_PLLSRC_1 | RCC_PLLCFGR_PLLSRC_0)

HSE clock selected as PLL entry clock source

Definition at line 650 of file stm32wbxx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), RCC_PLL_GetFreqDomain_48M(), RCC_PLL_GetFreqDomain_ADC(), RCC_PLL_GetFreqDomain_P(), RCC_PLL_GetFreqDomain_Q(), RCC_PLL_GetFreqDomain_SAI(), RCC_PLL_GetFreqDomain_SYS(), RCC_PLLSAI1_GetFreqDomain_48M(), RCC_PLLSAI1_GetFreqDomain_ADC(), RCC_PLLSAI1_GetFreqDomain_P(), RCC_PLLSAI1_GetFreqDomain_Q(), RCC_PLLSAI1_GetFreqDomain_R(), and RCC_PLLSAI1_GetFreqDomain_SAI().

#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_1

HSI clock selected as PLL entry clock source

Definition at line 649 of file stm32wbxx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSI(), RCC_PLL_GetFreqDomain_48M(), RCC_PLL_GetFreqDomain_ADC(), RCC_PLL_GetFreqDomain_P(), RCC_PLL_GetFreqDomain_Q(), RCC_PLL_GetFreqDomain_SAI(), RCC_PLL_GetFreqDomain_SYS(), RCC_PLLSAI1_GetFreqDomain_48M(), RCC_PLLSAI1_GetFreqDomain_ADC(), RCC_PLLSAI1_GetFreqDomain_P(), RCC_PLLSAI1_GetFreqDomain_Q(), RCC_PLLSAI1_GetFreqDomain_R(), and RCC_PLLSAI1_GetFreqDomain_SAI().

#define LL_RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_0

MSI clock selected as PLL entry clock source

Definition at line 648 of file stm32wbxx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_MSI(), RCC_PLL_GetFreqDomain_48M(), RCC_PLL_GetFreqDomain_ADC(), RCC_PLL_GetFreqDomain_P(), RCC_PLL_GetFreqDomain_Q(), RCC_PLL_GetFreqDomain_SAI(), RCC_PLL_GetFreqDomain_SYS(), RCC_PLLSAI1_GetFreqDomain_48M(), RCC_PLLSAI1_GetFreqDomain_ADC(), RCC_PLLSAI1_GetFreqDomain_P(), RCC_PLLSAI1_GetFreqDomain_Q(), RCC_PLLSAI1_GetFreqDomain_R(), and RCC_PLLSAI1_GetFreqDomain_SAI().

#define LL_RCC_PLLSOURCE_NONE 0x00000000U

No clock

Definition at line 647 of file stm32wbxx_ll_rcc.h.

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STM32WB55xx HAL User Manual: PLL and PLLSAI1 division factor

Defines
PLL and PLLSAI1 division factor
RCC Exported Constants

Defines

#define | LL_RCC_PLLM_DIV_1 0x00000000U
#define | LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0)
#define | LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1)
#define | LL_RCC_PLLM_DIV_4 ((RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0))
#define | LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2)
#define | LL_RCC_PLLM_DIV_6 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0))
#define | LL_RCC_PLLM_DIV_7 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1))
#define | LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM)

Define Documentation

#define LL_RCC_PLLM_DIV_1 0x00000000U

PLL and PLLSAI1 division factor by 1

Definition at line 658 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0)

PLL and PLLSAI1 division factor by 2

Definition at line 659 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1)

PLL and PLLSAI1 division factor by 3

Definition at line 660 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLM_DIV_4 ((RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0))

PLL and PLLSAI1 division factor by 4

Definition at line 661 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2)

PLL and PLLSAI1 division factor by 5

Definition at line 662 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLM_DIV_6 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0))

PLL and PLLSAI1 division factor by 6

Definition at line 663 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLM_DIV_7 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1))

PLL and PLLSAI1 division factor by 7

Definition at line 664 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM)

PLL and PLLSAI1 division factor by 8

Definition at line 665 of file stm32wbxx_ll_rcc.h.

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PLL division factor (PLLR)

Defines
PLL division factor (PLLR)
RCC Exported Constants

Defines

#define | LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_0)
#define | LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1)
#define | LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0)
#define | LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2)
#define | LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0)
#define | LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1)
#define | LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR)

Define Documentation

#define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_0)

Main PLL division factor for PLLCLK (system clock) by 2

Definition at line 673 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1)

Main PLL division factor for PLLCLK (system clock) by 3

Definition at line 674 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0)

Main PLL division factor for PLLCLK (system clock) by 4

Definition at line 675 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2)

Main PLL division factor for PLLCLK (system clock) by 5

Definition at line 676 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0)

Main PLL division factor for PLLCLK (system clock) by 6

Definition at line 677 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1)

Main PLL division factor for PLLCLK (system clock) by 7

Definition at line 678 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR)

Main PLL division factor for PLLCLK (system clock) by 8

Definition at line 679 of file stm32wbxx_ll_rcc.h.

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PLL division factor (PLLP)

Defines
PLL division factor (PLLP)
RCC Exported Constants

Defines

#define | LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLP_0)
#define | LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLP_1)
#define | LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1)
#define | LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLP_2)
#define | LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2)
#define | LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2)
#define | LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2)
#define | LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLP_3)
#define | LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3)
#define | LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3)
#define | LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3)
#define | LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)
#define | LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)
#define | LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)
#define | LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)
#define | LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_32 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)

Define Documentation

#define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3)

Main PLL division factor for PLLP output by 10

Definition at line 695 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3)

Main PLL division factor for PLLP output by 11

Definition at line 696 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3)

Main PLL division factor for PLLP output by 12

Definition at line 697 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)

Main PLL division factor for PLLP output by 13

Definition at line 698 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)

Main PLL division factor for PLLP output by 14

Definition at line 699 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)

Main PLL division factor for PLLP output by 15

Definition at line 700 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)

Main PLL division factor for PLLP output by 16

Definition at line 701 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP_4)

Main PLL division factor for PLLP output by 17

Definition at line 702 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_4)

Main PLL division factor for PLLP output by 18

Definition at line 703 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4)

Main PLL division factor for PLLP output by 19

Definition at line 704 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLP_0)

Main PLL division factor for PLLP output by 2

Definition at line 687 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4)

Main PLL division factor for PLLP output by 20

Definition at line 705 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)

Main PLL division factor for PLLP output by 21

Definition at line 706 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)

Main PLL division factor for PLLP output by 22

Definition at line 707 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)

Main PLL division factor for PLLP output by 23

Definition at line 708 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)

Main PLL division factor for PLLP output by 24

Definition at line 709 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)

Main PLL division factor for PLLP output by 25

Definition at line 710 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)

Main PLL division factor for PLLP output by 26

Definition at line 711 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)

Main PLL division factor for PLLP output by 27

Definition at line 712 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)

Main PLL division factor for PLLP output by 28

Definition at line 713 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)

Main PLL division factor for PLLP output by 29

Definition at line 714 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLP_1)

Main PLL division factor for PLLP output by 3

Definition at line 688 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)

Main PLL division factor for PLLP output by 30

Definition at line 715 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)

Main PLL division factor for PLLP output by 31

Definition at line 716 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_32 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)

Main PLL division factor for PLLP output by 32

Definition at line 717 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1)

Main PLL division factor for PLLP output by 4

Definition at line 689 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLP_2)

Main PLL division factor for PLLP output by 5

Definition at line 690 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2)

Main PLL division factor for PLLP output by 6

Definition at line 691 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2)

Main PLL division factor for PLLP output by 7

Definition at line 692 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2)

Main PLL division factor for PLLP output by 8

Definition at line 693 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLP_3)

Main PLL division factor for PLLP output by 9

Definition at line 694 of file stm32wbxx_ll_rcc.h.

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PLL division factor (PLLQ)

Defines
PLL division factor (PLLQ)
RCC Exported Constants

Defines

#define | LL_RCC_PLLQ_DIV_2 (RCC_PLLCFGR_PLLQ_0)
#define | LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1)
#define | LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0)
#define | LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2)
#define | LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0)
#define | LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1)
#define | LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ)

Define Documentation

#define LL_RCC_PLLQ_DIV_2 (RCC_PLLCFGR_PLLQ_0)

Main PLL division factor for PLLQ output by 2

Definition at line 725 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1)

Main PLL division factor for PLLQ output by 3

Definition at line 726 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0)

Main PLL division factor for PLLQ output by 4

Definition at line 727 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2)

Main PLL division factor for PLLQ output by 5

Definition at line 728 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0)

Main PLL division factor for PLLQ output by 6

Definition at line 729 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1)

Main PLL division factor for PLLQ output by 7

Definition at line 730 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ)

Main PLL division factor for PLLQ output by 8

Definition at line 731 of file stm32wbxx_ll_rcc.h.

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PLLSAI1 division factor (PLLQ)

Defines
PLLSAI1 division factor (PLLQ)
RCC Exported Constants

Defines

#define | LL_RCC_PLLSAI1Q_DIV_2 (RCC_PLLSAI1CFGR_PLLQ_0)
#define | LL_RCC_PLLSAI1Q_DIV_3 (RCC_PLLSAI1CFGR_PLLQ_1)
#define | LL_RCC_PLLSAI1Q_DIV_4 (RCC_PLLSAI1CFGR_PLLQ_1 | RCC_PLLSAI1CFGR_PLLQ_0)
#define | LL_RCC_PLLSAI1Q_DIV_5 (RCC_PLLSAI1CFGR_PLLQ_2)
#define | LL_RCC_PLLSAI1Q_DIV_6 (RCC_PLLSAI1CFGR_PLLQ_2 | RCC_PLLSAI1CFGR_PLLQ_0)
#define | LL_RCC_PLLSAI1Q_DIV_7 (RCC_PLLSAI1CFGR_PLLQ_2 | RCC_PLLSAI1CFGR_PLLQ_1)
#define | LL_RCC_PLLSAI1Q_DIV_8 (RCC_PLLSAI1CFGR_PLLQ_2 | RCC_PLLSAI1CFGR_PLLQ_1 | RCC_PLLSAI1CFGR_PLLQ_0)

Define Documentation

#define LL_RCC_PLLSAI1Q_DIV_2 (RCC_PLLSAI1CFGR_PLLQ_0)

PLLSAI1 division factor for PLLSAI1Q output by 2

Definition at line 740 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1Q_DIV_3 (RCC_PLLSAI1CFGR_PLLQ_1)

PLLSAI1 division factor for PLLSAI1Q output by 3

Definition at line 741 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1Q_DIV_4 (RCC_PLLSAI1CFGR_PLLQ_1 | RCC_PLLSAI1CFGR_PLLQ_0)

PLLSAI1 division factor for PLLSAI1Q output by 4

Definition at line 742 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1Q_DIV_5 (RCC_PLLSAI1CFGR_PLLQ_2)

PLLSAI1 division factor for PLLSAI1Q output by 5

Definition at line 743 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1Q_DIV_6 (RCC_PLLSAI1CFGR_PLLQ_2 | RCC_PLLSAI1CFGR_PLLQ_0)

PLLSAI1 division factor for PLLSAI1Q output by 6

Definition at line 744 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1Q_DIV_7 (RCC_PLLSAI1CFGR_PLLQ_2 | RCC_PLLSAI1CFGR_PLLQ_1)

PLLSAI1 division factor for PLLSAI1Q output by 7

Definition at line 745 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1Q_DIV_8 (RCC_PLLSAI1CFGR_PLLQ_2 | RCC_PLLSAI1CFGR_PLLQ_1 | RCC_PLLSAI1CFGR_PLLQ_0)

PLLSAI1 division factor for PLLSAI1Q output by 8

Definition at line 746 of file stm32wbxx_ll_rcc.h.

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PLLSAI1 division factor (PLLP)

Defines
PLLSAI1 division factor (PLLP)
RCC Exported Constants

Defines

#define | LL_RCC_PLLSAI1P_DIV_2 (RCC_PLLSAI1CFGR_PLLP_0)
#define | LL_RCC_PLLSAI1P_DIV_3 (RCC_PLLSAI1CFGR_PLLP_1)
#define | LL_RCC_PLLSAI1P_DIV_4 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1)
#define | LL_RCC_PLLSAI1P_DIV_5 (RCC_PLLSAI1CFGR_PLLP_2)
#define | LL_RCC_PLLSAI1P_DIV_6 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2)
#define | LL_RCC_PLLSAI1P_DIV_7 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2)
#define | LL_RCC_PLLSAI1P_DIV_8 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2)
#define | LL_RCC_PLLSAI1P_DIV_9 (RCC_PLLSAI1CFGR_PLLP_3)
#define | LL_RCC_PLLSAI1P_DIV_10 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_3)
#define | LL_RCC_PLLSAI1P_DIV_11 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3)
#define | LL_RCC_PLLSAI1P_DIV_12 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3)
#define | LL_RCC_PLLSAI1P_DIV_13 (RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3)
#define | LL_RCC_PLLSAI1P_DIV_14 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3)
#define | LL_RCC_PLLSAI1P_DIV_15 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3)
#define | LL_RCC_PLLSAI1P_DIV_16 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3)
#define | LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLP_4)
#define | LL_RCC_PLLSAI1P_DIV_18 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_4)
#define | LL_RCC_PLLSAI1P_DIV_19 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_4)
#define | LL_RCC_PLLSAI1P_DIV_20 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_4)
#define | LL_RCC_PLLSAI1P_DIV_21 (RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4)
#define | LL_RCC_PLLSAI1P_DIV_22 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4)
#define | LL_RCC_PLLSAI1P_DIV_23 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4)
#define | LL_RCC_PLLSAI1P_DIV_24 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4)
#define | LL_RCC_PLLSAI1P_DIV_25 (RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)
#define | LL_RCC_PLLSAI1P_DIV_26 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)
#define | LL_RCC_PLLSAI1P_DIV_27 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)
#define | LL_RCC_PLLSAI1P_DIV_28 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)
#define | LL_RCC_PLLSAI1P_DIV_29 (RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)
#define | LL_RCC_PLLSAI1P_DIV_30 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)
#define | LL_RCC_PLLSAI1P_DIV_31 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)
#define | LL_RCC_PLLSAI1P_DIV_32 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)

Define Documentation

#define LL_RCC_PLLSAI1P_DIV_10 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_3)

Main PLL division factor for PLLP output by 10

Definition at line 762 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1P_DIV_11 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3)

Main PLL division factor for PLLP output by 11

Definition at line 763 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1P_DIV_12 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3)

Main PLL division factor for PLLP output by 12

Definition at line 764 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1P_DIV_13 (RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3)

Main PLL division factor for PLLP output by 13

Definition at line 765 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1P_DIV_14 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3)

Main PLL division factor for PLLP output by 14

Definition at line 766 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1P_DIV_15 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3)

Main PLL division factor for PLLP output by 15

Definition at line 767 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1P_DIV_16 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3)

Main PLL division factor for PLLP output by 16

Definition at line 768 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLP_4)

Main PLL division factor for PLLP output by 17

Definition at line 769 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1P_DIV_18 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_4)

Main PLL division factor for PLLP output by 18

Definition at line 770 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1P_DIV_19 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_4)

Main PLL division factor for PLLP output by 19

Definition at line 771 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1P_DIV_2 (RCC_PLLSAI1CFGR_PLLP_0)

Main PLL division factor for PLLP output by 2

Definition at line 754 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1P_DIV_20 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_4)

Main PLL division factor for PLLP output by 20

Definition at line 772 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1P_DIV_21 (RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4)

Main PLL division factor for PLLP output by 21

Definition at line 773 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1P_DIV_22 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4)

Main PLL division factor for PLLP output by 22

Definition at line 774 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1P_DIV_23 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4)

Main PLL division factor for PLLP output by 23

Definition at line 775 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1P_DIV_24 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4)

Main PLL division factor for PLLP output by 24

Definition at line 776 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1P_DIV_25 (RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)

Main PLL division factor for PLLP output by 25

Definition at line 777 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1P_DIV_26 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)

Main PLL division factor for PLLP output by 26

Definition at line 778 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1P_DIV_27 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)

Main PLL division factor for PLLP output by 27

Definition at line 779 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1P_DIV_28 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)

Main PLL division factor for PLLP output by 28

Definition at line 780 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1P_DIV_29 (RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)

Main PLL division factor for PLLP output by 29

Definition at line 781 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1P_DIV_3 (RCC_PLLSAI1CFGR_PLLP_1)

Main PLL division factor for PLLP output by 3

Definition at line 755 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1P_DIV_30 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)

Main PLL division factor for PLLP output by 30

Definition at line 782 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1P_DIV_31 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)

Main PLL division factor for PLLP output by 31

Definition at line 783 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1P_DIV_32 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)

Main PLL division factor for PLLP output by 32

Definition at line 784 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1P_DIV_4 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1)

Main PLL division factor for PLLP output by 4

Definition at line 756 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1P_DIV_5 (RCC_PLLSAI1CFGR_PLLP_2)

Main PLL division factor for PLLP output by 5

Definition at line 757 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1P_DIV_6 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2)

Main PLL division factor for PLLP output by 6

Definition at line 758 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1P_DIV_7 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2)

Main PLL division factor for PLLP output by 7

Definition at line 759 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1P_DIV_8 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2)

Main PLL division factor for PLLP output by 8

Definition at line 760 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1P_DIV_9 (RCC_PLLSAI1CFGR_PLLP_3)

Main PLL division factor for PLLP output by 9

Definition at line 761 of file stm32wbxx_ll_rcc.h.

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PLLSAI1 division factor (PLLR)

Defines
PLLSAI1 division factor (PLLR)
RCC Exported Constants

Defines

#define | LL_RCC_PLLSAI1R_DIV_2 (RCC_PLLSAI1CFGR_PLLR_0)
#define | LL_RCC_PLLSAI1R_DIV_3 (RCC_PLLSAI1CFGR_PLLR_1)
#define | LL_RCC_PLLSAI1R_DIV_4 (RCC_PLLSAI1CFGR_PLLR_1 | RCC_PLLSAI1CFGR_PLLR_0)
#define | LL_RCC_PLLSAI1R_DIV_5 (RCC_PLLSAI1CFGR_PLLR_2)
#define | LL_RCC_PLLSAI1R_DIV_6 (RCC_PLLSAI1CFGR_PLLR_2 | RCC_PLLSAI1CFGR_PLLR_0)
#define | LL_RCC_PLLSAI1R_DIV_7 (RCC_PLLSAI1CFGR_PLLR_2 | RCC_PLLSAI1CFGR_PLLR_1)
#define | LL_RCC_PLLSAI1R_DIV_8 (RCC_PLLSAI1CFGR_PLLR_2 | RCC_PLLSAI1CFGR_PLLR_1 | RCC_PLLSAI1CFGR_PLLR_0)

Define Documentation

#define LL_RCC_PLLSAI1R_DIV_2 (RCC_PLLSAI1CFGR_PLLR_0)

PLLSAI1 division factor for PLLSAI1R output by 2

Definition at line 792 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1R_DIV_3 (RCC_PLLSAI1CFGR_PLLR_1)

PLLSAI1 division factor for PLLSAI1R output by 3

Definition at line 793 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1R_DIV_4 (RCC_PLLSAI1CFGR_PLLR_1 | RCC_PLLSAI1CFGR_PLLR_0)

PLLSAI1 division factor for PLLSAI1R output by 4

Definition at line 794 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1R_DIV_5 (RCC_PLLSAI1CFGR_PLLR_2)

PLLSAI1 division factor for PLLSAI1R output by 5

Definition at line 795 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1R_DIV_6 (RCC_PLLSAI1CFGR_PLLR_2 | RCC_PLLSAI1CFGR_PLLR_0)

PLLSAI1 division factor for PLLSAI1R output by 6

Definition at line 796 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1R_DIV_7 (RCC_PLLSAI1CFGR_PLLR_2 | RCC_PLLSAI1CFGR_PLLR_1)

PLLSAI1 division factor for PLLSAI1R output by 7

Definition at line 797 of file stm32wbxx_ll_rcc.h.

#define LL_RCC_PLLSAI1R_DIV_8 (RCC_PLLSAI1CFGR_PLLR_2 | RCC_PLLSAI1CFGR_PLLR_1 | RCC_PLLSAI1CFGR_PLLR_0)

PLLSAI1 division factor for PLLSAI1R output by 8

Definition at line 798 of file stm32wbxx_ll_rcc.h.

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
RCC Exported Macros

Defines

#define | LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
Write a value in RCC register.
#define | LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
Read a value in RCC register.

Define Documentation

#define LL_RCC_ReadReg ( __REG__ ) READ_REG(RCC->__REG__)

Read a value in RCC register.

Parameters:
__REG__ Register to be read
Return values:
Register value

Definition at line 829 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define LL_RCC_WriteReg | ( | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(RCC->__REG__, (__VALUE__))

Write a value in RCC register.

Parameters:
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 822 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_DeInit(), HAL_RCCEx_PeriphCLKConfig(), and LL_RCC_DeInit().

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Calculate frequencies

Defines
Calculate frequencies
RCC Exported Macros

Defines

#define | __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__)
Helper macro to calculate the PLLRCLK frequency on system domain.
#define | __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__)
Helper macro to calculate the PLLPCLK frequency used on SAI domain.
#define | __LL_RCC_CALC_PLLCLK_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__)
Helper macro to calculate the PLLPCLK frequency used on ADC domain.
#define | __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__)
Helper macro to calculate the PLLQCLK frequency used on 48M domain.
#define | __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__)
Helper macro to calculate the PLLSAI1PCLK frequency used for SAI domain.
#define | __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1Q__)
Helper macro to calculate the PLLSAI1QCLK frequency used on 48M domain.
#define | __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1R__)
Helper macro to calculate the PLLSAI1RCLK frequency used on ADC domain.
#define | __LL_RCC_CALC_HCLK1_FREQ(__SYSCLKFREQ__, __CPU1PRESCALER__) ((__SYSCLKFREQ__) / AHBPrescTable[((__CPU1PRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
Helper macro to calculate the HCLK1 frequency.
#define | __LL_RCC_CALC_HCLK2_FREQ(__SYSCLKFREQ__, __CPU2PRESCALER__) ((__SYSCLKFREQ__) / AHBPrescTable[((__CPU2PRESCALER__) & RCC_EXTCFGR_C2HPRE) >> RCC_EXTCFGR_C2HPRE_Pos])
Helper macro to calculate the HCLK2 frequency.
#define | __LL_RCC_CALC_HCLK4_FREQ(__SYSCLKFREQ__, __AHB4PRESCALER__) ((__SYSCLKFREQ__) / AHBPrescTable[(((__AHB4PRESCALER__) >> 4U) & RCC_EXTCFGR_SHDHPRE) >> RCC_EXTCFGR_SHDHPRE_Pos])
Helper macro to calculate the HCLK4 frequency.
#define | __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> (APBPrescTable[(((__APB1PRESCALER__) & RCC_CFGR_PPRE1_Msk) >> RCC_CFGR_PPRE1_Pos)] & 31U))
Helper macro to calculate the PCLK1 frequency (ABP1)
#define | __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> (APBPrescTable[(((__APB2PRESCALER__) & RCC_CFGR_PPRE2_Msk) >> RCC_CFGR_PPRE2_Pos)] & 31U))
Helper macro to calculate the PCLK2 frequency (ABP2)
#define | __LL_RCC_CALC_MSI_FREQ(__MSIRANGE__) MSIRangeTable[((__MSIRANGE__) & RCC_CR_MSIRANGE_Msk) >> RCC_CR_MSIRANGE_Pos]
Helper macro to calculate the MSI frequency (in Hz)

Define Documentation

#define __LL_RCC_CALC_HCLK1_FREQ | ( | __SYSCLKFREQ__,
 |  | __CPU1PRESCALER__
 | ) | ((__SYSCLKFREQ__) / AHBPrescTable[((__CPU1PRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])

Helper macro to calculate the HCLK1 frequency.

Parameters:
__SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
__CPU1PRESCALER__ This parameter can be one of the following values:
  • LL_RCC_SYSCLK_DIV_1
  • LL_RCC_SYSCLK_DIV_2
  • LL_RCC_SYSCLK_DIV_3
  • LL_RCC_SYSCLK_DIV_4
  • LL_RCC_SYSCLK_DIV_5
  • LL_RCC_SYSCLK_DIV_6
  • LL_RCC_SYSCLK_DIV_8
  • LL_RCC_SYSCLK_DIV_10
  • LL_RCC_SYSCLK_DIV_16
  • LL_RCC_SYSCLK_DIV_32
  • LL_RCC_SYSCLK_DIV_64
  • LL_RCC_SYSCLK_DIV_128
  • LL_RCC_SYSCLK_DIV_256
  • LL_RCC_SYSCLK_DIV_512
Return values:
HCLK1 clock frequency (in Hz)

Definition at line 1132 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_GetHCLKFreq(), HAL_RCCEx_GetPeriphCLKFreq(), RCC_GetHCLK1ClockFreq(), and UTILS_EnablePLLAndSwitchSystem().

#define __LL_RCC_CALC_HCLK2_FREQ | ( | __SYSCLKFREQ__,
 |  | __CPU2PRESCALER__
 | ) | ((__SYSCLKFREQ__) / AHBPrescTable[((__CPU2PRESCALER__) & RCC_EXTCFGR_C2HPRE) >> RCC_EXTCFGR_C2HPRE_Pos])

Helper macro to calculate the HCLK2 frequency.

Parameters:
__SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
__CPU2PRESCALER__ This parameter can be one of the following values:
  • LL_RCC_SYSCLK_DIV_1
  • LL_RCC_SYSCLK_DIV_2
  • LL_RCC_SYSCLK_DIV_3
  • LL_RCC_SYSCLK_DIV_4
  • LL_RCC_SYSCLK_DIV_5
  • LL_RCC_SYSCLK_DIV_6
  • LL_RCC_SYSCLK_DIV_8
  • LL_RCC_SYSCLK_DIV_10
  • LL_RCC_SYSCLK_DIV_16
  • LL_RCC_SYSCLK_DIV_32
  • LL_RCC_SYSCLK_DIV_64
  • LL_RCC_SYSCLK_DIV_128
  • LL_RCC_SYSCLK_DIV_256
  • LL_RCC_SYSCLK_DIV_512
Return values:
HCLK2 clock frequency (in Hz)

Definition at line 1154 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_GetHCLK2Freq(), LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), LL_PLL_ConfigSystemClock_MSI(), and RCC_GetHCLK2ClockFreq().

#define __LL_RCC_CALC_HCLK4_FREQ | ( | __SYSCLKFREQ__,
 |  | __AHB4PRESCALER__
 | ) | ((__SYSCLKFREQ__) / AHBPrescTable[(((__AHB4PRESCALER__) >> 4U) & RCC_EXTCFGR_SHDHPRE) >> RCC_EXTCFGR_SHDHPRE_Pos])

Helper macro to calculate the HCLK4 frequency.

Parameters:
__SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
__AHB4PRESCALER__ This parameter can be one of the following values:
  • LL_RCC_SYSCLK_DIV_1
  • LL_RCC_SYSCLK_DIV_2
  • LL_RCC_SYSCLK_DIV_3
  • LL_RCC_SYSCLK_DIV_4
  • LL_RCC_SYSCLK_DIV_5
  • LL_RCC_SYSCLK_DIV_6
  • LL_RCC_SYSCLK_DIV_8
  • LL_RCC_SYSCLK_DIV_10
  • LL_RCC_SYSCLK_DIV_16
  • LL_RCC_SYSCLK_DIV_32
  • LL_RCC_SYSCLK_DIV_64
  • LL_RCC_SYSCLK_DIV_128
  • LL_RCC_SYSCLK_DIV_256
  • LL_RCC_SYSCLK_DIV_512
Return values:
HCLK4 clock frequency (in Hz)

Definition at line 1176 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_GetHCLK4Freq(), RCC_GetHCLK4ClockFreq(), RCC_SetFlashLatencyFromMSIRange(), and UTILS_EnablePLLAndSwitchSystem().

#define __LL_RCC_CALC_MSI_FREQ ( __MSIRANGE__ ) MSIRangeTable[((__MSIRANGE__) & RCC_CR_MSIRANGE_Msk) >> RCC_CR_MSIRANGE_Pos]

Helper macro to calculate the MSI frequency (in Hz)

Note:
__MSIRANGE__can be retrieved by LL_RCC_MSI_GetRange()
Parameters:
__MSIRANGE__ This parameter can be one of the following values:
  • LL_RCC_MSIRANGE_0
  • LL_RCC_MSIRANGE_1
  • LL_RCC_MSIRANGE_2
  • LL_RCC_MSIRANGE_3
  • LL_RCC_MSIRANGE_4
  • LL_RCC_MSIRANGE_5
  • LL_RCC_MSIRANGE_6
  • LL_RCC_MSIRANGE_7
  • LL_RCC_MSIRANGE_8
  • LL_RCC_MSIRANGE_9
  • LL_RCC_MSIRANGE_10
  • LL_RCC_MSIRANGE_11
Return values:
MSI clock frequency (in Hz)

Definition at line 1223 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_GetSysClockFreq(), HAL_RCCEx_GetPeriphCLKFreq(), LL_PLL_ConfigSystemClock_MSI(), LL_RCC_GetCLK48ClockFreq(), LL_RCC_GetSMPSClockFreq(), RCC_GetSystemClockFreq(), RCC_PLL_GetFreqDomain_48M(), RCC_PLL_GetFreqDomain_ADC(), RCC_PLL_GetFreqDomain_P(), RCC_PLL_GetFreqDomain_Q(), RCC_PLL_GetFreqDomain_SAI(), RCC_PLL_GetFreqDomain_SYS(), RCC_PLLSAI1_GetFreqDomain_48M(), RCC_PLLSAI1_GetFreqDomain_ADC(), RCC_PLLSAI1_GetFreqDomain_P(), RCC_PLLSAI1_GetFreqDomain_Q(), RCC_PLLSAI1_GetFreqDomain_R(), RCC_PLLSAI1_GetFreqDomain_SAI(), and RCC_SetFlashLatencyFromMSIRange().

#define __LL_RCC_CALC_PCLK1_FREQ | ( | __HCLKFREQ__,
 |  | __APB1PRESCALER__
 | ) | ((__HCLKFREQ__) >> (APBPrescTable[(((__APB1PRESCALER__) & RCC_CFGR_PPRE1_Msk) >> RCC_CFGR_PPRE1_Pos)] & 31U))

Helper macro to calculate the PCLK1 frequency (ABP1)

Parameters:
__HCLKFREQ__ HCLK frequency
__APB1PRESCALER__ This parameter can be one of the following values:
  • LL_RCC_APB1_DIV_1
  • LL_RCC_APB1_DIV_2
  • LL_RCC_APB1_DIV_4
  • LL_RCC_APB1_DIV_8
  • LL_RCC_APB1_DIV_16
Return values:
PCLK1 clock frequency (in Hz)

Definition at line 1190 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_GetPCLK1Freq(), HAL_RCCEx_GetPeriphCLKFreq(), and RCC_GetPCLK1ClockFreq().

#define __LL_RCC_CALC_PCLK2_FREQ | ( | __HCLKFREQ__,
 |  | __APB2PRESCALER__
 | ) | ((__HCLKFREQ__) >> (APBPrescTable[(((__APB2PRESCALER__) & RCC_CFGR_PPRE2_Msk) >> RCC_CFGR_PPRE2_Pos)] & 31U))

Helper macro to calculate the PCLK2 frequency (ABP2)

Parameters:
__HCLKFREQ__ HCLK frequency
__APB2PRESCALER__ This parameter can be one of the following values:
  • LL_RCC_APB2_DIV_1
  • LL_RCC_APB2_DIV_2
  • LL_RCC_APB2_DIV_4
  • LL_RCC_APB2_DIV_8
  • LL_RCC_APB2_DIV_16
Return values:
PCLK2 clock frequency (in Hz)

Definition at line 1203 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_GetPCLK2Freq(), HAL_RCCEx_GetPeriphCLKFreq(), and RCC_GetPCLK2ClockFreq().

#define __LL_RCC_CALC_PLLCLK_48M_FREQ | ( | __INPUTFREQ__,
 |  | __PLLM__,
 |  | __PLLN__,
 |  | __PLLQ__
 | ) |
Value:
((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
                   (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U))

Helper macro to calculate the PLLQCLK frequency used on 48M domain.

Note:
ex: __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,LL_RCC_PLL_GetDivider (), LL_RCC_PLL_GetN (), LL_RCC_PLL_GetQ ());
Parameters:
__INPUTFREQ__ | PLL Input frequency (based on MSI/HSE/HSI)
__PLLM__ This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
__PLLN__ | Between Min_Data = 6 and Max_Data = 127
__PLLQ__ This parameter can be one of the following values:
  • LL_RCC_PLLQ_DIV_2
  • LL_RCC_PLLQ_DIV_3
  • LL_RCC_PLLQ_DIV_4
  • LL_RCC_PLLQ_DIV_5
  • LL_RCC_PLLQ_DIV_6
  • LL_RCC_PLLQ_DIV_7
  • LL_RCC_PLLQ_DIV_8
Return values:
PLL clock frequency (in Hz)

Definition at line 996 of file stm32wbxx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_48M(), and RCC_PLL_GetFreqDomain_Q().

#define __LL_RCC_CALC_PLLCLK_ADC_FREQ | ( | __INPUTFREQ__,
 |  | __PLLM__,
 |  | __PLLN__,
 |  | __PLLP__
 | ) |
Value:
((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
                   (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U))

Helper macro to calculate the PLLPCLK frequency used on ADC domain.

Note:
ex: __LL_RCC_CALC_PLLCLK_ADC_FREQ (HSE_VALUE,LL_RCC_PLL_GetDivider (), LL_RCC_PLL_GetN (), LL_RCC_PLL_GetP ());
Parameters:
__INPUTFREQ__ | PLL Input frequency (based on MSI/HSE/HSI)
__PLLM__ This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
__PLLN__ | Between Min_Data = 6 and Max_Data = 127
__PLLP__ This parameter can be one of the following values:
  • LL_RCC_PLLP_DIV_2
  • LL_RCC_PLLP_DIV_3
  • LL_RCC_PLLP_DIV_4
  • LL_RCC_PLLP_DIV_5
  • LL_RCC_PLLP_DIV_6
  • LL_RCC_PLLP_DIV_7
  • LL_RCC_PLLP_DIV_8
  • LL_RCC_PLLP_DIV_9
  • LL_RCC_PLLP_DIV_10
  • LL_RCC_PLLP_DIV_11
  • LL_RCC_PLLP_DIV_12
  • LL_RCC_PLLP_DIV_13
  • LL_RCC_PLLP_DIV_14
  • LL_RCC_PLLP_DIV_15
  • LL_RCC_PLLP_DIV_16
  • LL_RCC_PLLP_DIV_17
  • LL_RCC_PLLP_DIV_18
  • LL_RCC_PLLP_DIV_19
  • LL_RCC_PLLP_DIV_20
  • LL_RCC_PLLP_DIV_21
  • LL_RCC_PLLP_DIV_22
  • LL_RCC_PLLP_DIV_23
  • LL_RCC_PLLP_DIV_24
  • LL_RCC_PLLP_DIV_25
  • LL_RCC_PLLP_DIV_26
  • LL_RCC_PLLP_DIV_27
  • LL_RCC_PLLP_DIV_28
  • LL_RCC_PLLP_DIV_29
  • LL_RCC_PLLP_DIV_30
  • LL_RCC_PLLP_DIV_31
  • LL_RCC_PLLP_DIV_32
Return values:
PLL clock frequency (in Hz)

Definition at line 968 of file stm32wbxx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_ADC(), and RCC_PLL_GetFreqDomain_P().

#define __LL_RCC_CALC_PLLCLK_FREQ | ( | __INPUTFREQ__,
 |  | __PLLM__,
 |  | __PLLN__,
 |  | __PLLR__
 | ) |
Value:
((__INPUTFREQ__) * (__PLLN__)  / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
                   (((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U))

Helper macro to calculate the PLLRCLK frequency on system domain.

Note:
ex: __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,LL_RCC_PLL_GetDivider (), LL_RCC_PLL_GetN (), LL_RCC_PLL_GetR ());
Parameters:
__INPUTFREQ__ | PLL Input frequency (based on MSI/HSE/HSI)
__PLLM__ This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
__PLLN__ | Between Min_Data = 6 and Max_Data = 127
__PLLR__ This parameter can be one of the following values:
  • LL_RCC_PLLR_DIV_2
  • LL_RCC_PLLR_DIV_3
  • LL_RCC_PLLR_DIV_4
  • LL_RCC_PLLR_DIV_5
  • LL_RCC_PLLR_DIV_6
  • LL_RCC_PLLR_DIV_7
  • LL_RCC_PLLR_DIV_8
Return values:
PLL clock frequency (in Hz)

Definition at line 863 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_GetSysClockFreq(), and RCC_PLL_GetFreqDomain_SYS().

#define __LL_RCC_CALC_PLLCLK_SAI_FREQ | ( | __INPUTFREQ__,
 |  | __PLLM__,
 |  | __PLLN__,
 |  | __PLLP__
 | ) |
Value:
((__INPUTFREQ__) * (__PLLN__)  / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U))/ \
                   (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U))

Helper macro to calculate the PLLPCLK frequency used on SAI domain.

Note:
ex: __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,LL_RCC_PLL_GetDivider (), LL_RCC_PLL_GetN (), LL_RCC_PLL_GetP ());
Parameters:
__INPUTFREQ__ | PLL Input frequency (based on MSI/HSE/HSI)
__PLLM__ This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
__PLLN__ | Between Min_Data = 6 and Max_Data = 127
__PLLP__ This parameter can be one of the following values:
  • LL_RCC_PLLP_DIV_2
  • LL_RCC_PLLP_DIV_3
  • LL_RCC_PLLP_DIV_4
  • LL_RCC_PLLP_DIV_5
  • LL_RCC_PLLP_DIV_6
  • LL_RCC_PLLP_DIV_7
  • LL_RCC_PLLP_DIV_8
  • LL_RCC_PLLP_DIV_9
  • LL_RCC_PLLP_DIV_10
  • LL_RCC_PLLP_DIV_11
  • LL_RCC_PLLP_DIV_12
  • LL_RCC_PLLP_DIV_13
  • LL_RCC_PLLP_DIV_14
  • LL_RCC_PLLP_DIV_15
  • LL_RCC_PLLP_DIV_16
  • LL_RCC_PLLP_DIV_17
  • LL_RCC_PLLP_DIV_18
  • LL_RCC_PLLP_DIV_19
  • LL_RCC_PLLP_DIV_20
  • LL_RCC_PLLP_DIV_21
  • LL_RCC_PLLP_DIV_22
  • LL_RCC_PLLP_DIV_23
  • LL_RCC_PLLP_DIV_24
  • LL_RCC_PLLP_DIV_25
  • LL_RCC_PLLP_DIV_26
  • LL_RCC_PLLP_DIV_27
  • LL_RCC_PLLP_DIV_28
  • LL_RCC_PLLP_DIV_29
  • LL_RCC_PLLP_DIV_30
  • LL_RCC_PLLP_DIV_31
Return values:
PLL clock frequency (in Hz)

Definition at line 915 of file stm32wbxx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_SAI().

#define __LL_RCC_CALC_PLLSAI1_48M_FREQ | ( | __INPUTFREQ__,
 |  | __PLLM__,
 |  | __PLLSAI1N__,
 |  | __PLLSAI1Q__
 | ) |
Value:
((__INPUTFREQ__) * (__PLLSAI1N__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
                    (((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLQ_Pos) + 1U))

Helper macro to calculate the PLLSAI1QCLK frequency used on 48M domain.

Note:
ex: __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,LL_RCC_PLL_GetDivider (), LL_RCC_PLLSAI1_GetN (), LL_RCC_PLLSAI1_GetQ ());
Parameters:
__INPUTFREQ__ | PLL Input frequency (based on MSI/HSE/HSI)
__PLLM__ This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
__PLLSAI1N__ | Between 6 and 127
__PLLSAI1Q__ This parameter can be one of the following values:
  • LL_RCC_PLLSAI1Q_DIV_2
  • LL_RCC_PLLSAI1Q_DIV_3
  • LL_RCC_PLLSAI1Q_DIV_4
  • LL_RCC_PLLSAI1Q_DIV_5
  • LL_RCC_PLLSAI1Q_DIV_6
  • LL_RCC_PLLSAI1Q_DIV_7
  • LL_RCC_PLLSAI1Q_DIV_8
Return values:
PLLSAI1 clock frequency (in Hz)

Definition at line 1078 of file stm32wbxx_ll_rcc.h.

Referenced by RCC_PLLSAI1_GetFreqDomain_48M(), and RCC_PLLSAI1_GetFreqDomain_Q().

#define __LL_RCC_CALC_PLLSAI1_ADC_FREQ | ( | __INPUTFREQ__,
 |  | __PLLM__,
 |  | __PLLSAI1N__,
 |  | __PLLSAI1R__
 | ) |
Value:
((__INPUTFREQ__) * (__PLLSAI1N__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
                    (((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLR_Pos) + 1U))

Helper macro to calculate the PLLSAI1RCLK frequency used on ADC domain.

Note:
ex: __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,LL_RCC_PLL_GetDivider (), LL_RCC_PLLSAI1_GetN (), LL_RCC_PLLSAI1_GetR ());
Parameters:
__INPUTFREQ__ | PLL Input frequency (based on MSI/HSE/HSI)
__PLLM__ This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
__PLLSAI1N__ | Between 6 and 127
__PLLSAI1R__ This parameter can be one of the following values:
  • LL_RCC_PLLSAI1R_DIV_2
  • LL_RCC_PLLSAI1R_DIV_3
  • LL_RCC_PLLSAI1R_DIV_4
  • LL_RCC_PLLSAI1R_DIV_5
  • LL_RCC_PLLSAI1R_DIV_6
  • LL_RCC_PLLSAI1R_DIV_7
  • LL_RCC_PLLSAI1R_DIV_8
Return values:
PLLSAI1 clock frequency (in Hz)

Definition at line 1107 of file stm32wbxx_ll_rcc.h.

Referenced by RCC_PLLSAI1_GetFreqDomain_ADC(), and RCC_PLLSAI1_GetFreqDomain_R().

#define __LL_RCC_CALC_PLLSAI1_SAI_FREQ | ( | __INPUTFREQ__,
 |  | __PLLM__,
 |  | __PLLSAI1N__,
 |  | __PLLSAI1P__
 | ) |
Value:
((__INPUTFREQ__) * (__PLLSAI1N__)  / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
                    (((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLP_Pos) + 1U))

Helper macro to calculate the PLLSAI1PCLK frequency used for SAI domain.

Note:
ex: __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,LL_RCC_PLL_GetDivider (), LL_RCC_PLLSAI1_GetN (), LL_RCC_PLLSAI1_GetP ());
Parameters:
__INPUTFREQ__ | PLL Input frequency (based on MSI/HSE/HSI)
__PLLM__ This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
__PLLSAI1N__ | Between 6 and 127
__PLLSAI1P__ This parameter can be one of the following values:
  • LL_RCC_PLLSAI1P_DIV_2
  • LL_RCC_PLLSAI1P_DIV_3
  • LL_RCC_PLLSAI1P_DIV_4
  • LL_RCC_PLLSAI1P_DIV_5
  • LL_RCC_PLLSAI1P_DIV_6
  • LL_RCC_PLLSAI1P_DIV_7
  • LL_RCC_PLLSAI1P_DIV_8
  • LL_RCC_PLLSAI1P_DIV_9
  • LL_RCC_PLLSAI1P_DIV_10
  • LL_RCC_PLLSAI1P_DIV_11
  • LL_RCC_PLLSAI1P_DIV_12
  • LL_RCC_PLLSAI1P_DIV_13
  • LL_RCC_PLLSAI1P_DIV_14
  • LL_RCC_PLLSAI1P_DIV_15
  • LL_RCC_PLLSAI1P_DIV_16
  • LL_RCC_PLLSAI1P_DIV_17
  • LL_RCC_PLLSAI1P_DIV_18
  • LL_RCC_PLLSAI1P_DIV_19
  • LL_RCC_PLLSAI1P_DIV_20
  • LL_RCC_PLLSAI1P_DIV_21
  • LL_RCC_PLLSAI1P_DIV_22
  • LL_RCC_PLLSAI1P_DIV_23
  • LL_RCC_PLLSAI1P_DIV_24
  • LL_RCC_PLLSAI1P_DIV_25
  • LL_RCC_PLLSAI1P_DIV_26
  • LL_RCC_PLLSAI1P_DIV_27
  • LL_RCC_PLLSAI1P_DIV_28
  • LL_RCC_PLLSAI1P_DIV_29
  • LL_RCC_PLLSAI1P_DIV_30
  • LL_RCC_PLLSAI1P_DIV_31
  • LL_RCC_PLLSAI1P_DIV_32
Return values:
PLLSAI1 clock frequency (in Hz)

Definition at line 1049 of file stm32wbxx_ll_rcc.h.

Referenced by RCC_PLLSAI1_GetFreqDomain_P(), and RCC_PLLSAI1_GetFreqDomain_SAI().

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: HSE

Functions
HSE
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_HSE_EnableDiv2 (void)
Enable HSE sysclk and pll prescaler division by 2.
__STATIC_INLINE void | LL_RCC_HSE_DisableDiv2 (void)
Disable HSE sysclk and pll prescaler.
__STATIC_INLINE uint32_t | LL_RCC_HSE_IsEnabledDiv2 (void)
Get HSE sysclk and pll prescaler.
__STATIC_INLINE void | LL_RCC_HSE_EnableCSS (void)
Enable the Clock Security System.
__STATIC_INLINE void | LL_RCC_HSE_EnableBypass (void)
Enable HSE external oscillator (HSE Bypass)
__STATIC_INLINE void | LL_RCC_HSE_DisableBypass (void)
Disable HSE external oscillator (HSE Bypass)
__STATIC_INLINE void | LL_RCC_HSE_Enable (void)
Enable HSE crystal oscillator (HSE ON)
__STATIC_INLINE void | LL_RCC_HSE_Disable (void)
Disable HSE crystal oscillator (HSE ON)
__STATIC_INLINE uint32_t | LL_RCC_HSE_IsReady (void)
Check if HSE oscillator Ready.
__STATIC_INLINE uint32_t | LL_RCC_HSE_IsClockControlLocked (void)
Check if HSE clock control register is locked or not.
__STATIC_INLINE void | LL_RCC_HSE_SetCapacitorTuning (uint32_t Value)
Set HSE capacitor tuning.
__STATIC_INLINE uint32_t | LL_RCC_HSE_GetCapacitorTuning (void)
Get HSE capacitor tuning.
__STATIC_INLINE void | LL_RCC_HSE_SetCurrentControl (uint32_t CurrentMax)
Set HSE current control.
__STATIC_INLINE uint32_t | LL_RCC_HSE_GetCurrentControl (void)
Get HSE current control.
__STATIC_INLINE void | LL_RCC_HSE_SetSenseAmplifier (uint32_t SenseAmplifier)
Set HSE sense amplifier threshold.
__STATIC_INLINE uint32_t | LL_RCC_HSE_GetSenseAmplifier (void)
Get HSE current control.

Function Documentation

__STATIC_INLINE void LL_RCC_HSE_Disable ( void )

Disable HSE crystal oscillator (HSE ON)

Reference Manual to LL API cross reference:
CR HSEON LL_RCC_HSE_Disable
Return values:
None

Definition at line 1316 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_HSE_DisableBypass ( void )

Disable HSE external oscillator (HSE Bypass)

Reference Manual to LL API cross reference:
CR HSEBYP LL_RCC_HSE_DisableBypass
Return values:
None

Definition at line 1296 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_DeInit(), and LL_PLL_ConfigSystemClock_HSE().

__STATIC_INLINE void LL_RCC_HSE_DisableDiv2 ( void )

Disable HSE sysclk and pll prescaler.

Reference Manual to LL API cross reference:
CR HSEPRE LL_RCC_HSE_DisableDiv2
Return values:
None

Definition at line 1256 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_HSE_Enable ( void )

Enable HSE crystal oscillator (HSE ON)

Reference Manual to LL API cross reference:
CR HSEON LL_RCC_HSE_Enable
Return values:
None

Definition at line 1306 of file stm32wbxx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE().

__STATIC_INLINE void LL_RCC_HSE_EnableBypass ( void )

Enable HSE external oscillator (HSE Bypass)

Reference Manual to LL API cross reference:
CR HSEBYP LL_RCC_HSE_EnableBypass
Return values:
None

Definition at line 1286 of file stm32wbxx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE().

__STATIC_INLINE void LL_RCC_HSE_EnableCSS ( void )

Enable the Clock Security System.

Reference Manual to LL API cross reference:
CR CSSON LL_RCC_HSE_EnableCSS
Return values:
None

Definition at line 1276 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_EnableCSS().

__STATIC_INLINE void LL_RCC_HSE_EnableDiv2 ( void )

Enable HSE sysclk and pll prescaler division by 2.

Reference Manual to LL API cross reference:
CR HSEPRE LL_RCC_HSE_EnableDiv2
Return values:
None

Definition at line 1246 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_HSE_GetCapacitorTuning ( void )

Get HSE capacitor tuning.

Reference Manual to LL API cross reference:
HSECR HSETUNE LL_RCC_HSE_GetCapacitorTuning
Return values:
Between Min_Data = 0 and Max_Data = 63

Definition at line 1358 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_HSE_GetCurrentControl ( void )

Get HSE current control.

Reference Manual to LL API cross reference:
HSECR HSEGMC LL_RCC_HSE_GetCurrentControl
Return values:
Returned value can be one of the following values:
  • LL_RCC_HSE_CURRENTMAX_0
  • LL_RCC_HSE_CURRENTMAX_1
  • LL_RCC_HSE_CURRENTMAX_2
  • LL_RCC_HSE_CURRENTMAX_3
  • LL_RCC_HSE_CURRENTMAX_4
  • LL_RCC_HSE_CURRENTMAX_5
  • LL_RCC_HSE_CURRENTMAX_6
  • LL_RCC_HSE_CURRENTMAX_7

Definition at line 1395 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_HSE_GetSenseAmplifier ( void )

Get HSE current control.

Reference Manual to LL API cross reference:
HSECR HSES LL_RCC_HSE_GetSenseAmplifier
Return values:
Returned value can be one of the following values:
  • LL_RCC_HSEAMPTHRESHOLD_1_2
  • LL_RCC_HSEAMPTHRESHOLD_3_4

Definition at line 1420 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_HSE_IsClockControlLocked ( void )

Check if HSE clock control register is locked or not.

Reference Manual to LL API cross reference:
HSECR UNLOCKED LL_RCC_HSE_IsClockControlLocked
Return values:
State of bit (1 or 0).

Definition at line 1336 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_HSE_IsEnabledDiv2 ( void )

Get HSE sysclk and pll prescaler.

Reference Manual to LL API cross reference:
CR HSEPRE LL_RCC_HSE_IsEnabledDiv2
Return values:
None

Definition at line 1266 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_GetSysClockFreq(), RCC_GetSystemClockFreq(), RCC_PLL_GetFreqDomain_48M(), RCC_PLL_GetFreqDomain_ADC(), RCC_PLL_GetFreqDomain_P(), RCC_PLL_GetFreqDomain_Q(), RCC_PLL_GetFreqDomain_SAI(), RCC_PLL_GetFreqDomain_SYS(), RCC_PLLSAI1_GetFreqDomain_48M(), RCC_PLLSAI1_GetFreqDomain_ADC(), RCC_PLLSAI1_GetFreqDomain_P(), RCC_PLLSAI1_GetFreqDomain_Q(), RCC_PLLSAI1_GetFreqDomain_R(), and RCC_PLLSAI1_GetFreqDomain_SAI().

__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady ( void )

Check if HSE oscillator Ready.

Reference Manual to LL API cross reference:
CR HSERDY LL_RCC_HSE_IsReady
Return values:
State of bit (1 or 0).

Definition at line 1326 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_ClockConfig(), HAL_RCC_OscConfig(), HAL_RCCEx_GetPeriphCLKFreq(), LL_PLL_ConfigSystemClock_HSE(), and LL_RCC_GetSMPSClockFreq().

__STATIC_INLINE void LL_RCC_HSE_SetCapacitorTuning ( uint32_t Value )

Set HSE capacitor tuning.

Reference Manual to LL API cross reference:
HSECR HSETUNE LL_RCC_HSE_SetCapacitorTuning
Parameters:
Value Between Min_Data = 0 and Max_Data = 63
Return values:
None

Definition at line 1347 of file stm32wbxx_ll_rcc.h.

References HSE_CONTROL_UNLOCK_KEY.

__STATIC_INLINE void LL_RCC_HSE_SetCurrentControl ( uint32_t CurrentMax )

Set HSE current control.

Reference Manual to LL API cross reference:
HSECR HSEGMC LL_RCC_HSE_SetCurrentControl
Parameters:
CurrentMax This parameter can be one of the following values:
  • LL_RCC_HSE_CURRENTMAX_0
  • LL_RCC_HSE_CURRENTMAX_1
  • LL_RCC_HSE_CURRENTMAX_2
  • LL_RCC_HSE_CURRENTMAX_3
  • LL_RCC_HSE_CURRENTMAX_4
  • LL_RCC_HSE_CURRENTMAX_5
  • LL_RCC_HSE_CURRENTMAX_6
  • LL_RCC_HSE_CURRENTMAX_7

Definition at line 1376 of file stm32wbxx_ll_rcc.h.

References HSE_CONTROL_UNLOCK_KEY.

__STATIC_INLINE void LL_RCC_HSE_SetSenseAmplifier ( uint32_t SenseAmplifier )

Set HSE sense amplifier threshold.

Reference Manual to LL API cross reference:
HSECR HSES LL_RCC_HSE_SetSenseAmplifier
Parameters:
SenseAmplifier This parameter can be one of the following values:
  • LL_RCC_HSEAMPTHRESHOLD_1_2
  • LL_RCC_HSEAMPTHRESHOLD_3_4

Definition at line 1407 of file stm32wbxx_ll_rcc.h.

References HSE_CONTROL_UNLOCK_KEY.

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: HSI

Functions
HSI
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_HSI_EnableInStopMode (void)
Enable HSI even in stop mode.
__STATIC_INLINE void | LL_RCC_HSI_DisableInStopMode (void)
Disable HSI in stop mode.
__STATIC_INLINE uint32_t | LL_RCC_HSI_IsEnabledInStopMode (void)
Check if HSI in stop mode is ready.
__STATIC_INLINE void | LL_RCC_HSI_Enable (void)
Enable HSI oscillator.
__STATIC_INLINE void | LL_RCC_HSI_Disable (void)
Disable HSI oscillator.
__STATIC_INLINE uint32_t | LL_RCC_HSI_IsReady (void)
Check if HSI clock is ready.
__STATIC_INLINE void | LL_RCC_HSI_EnableAutoFromStop (void)
Enable HSI Automatic from stop mode.
__STATIC_INLINE void | LL_RCC_HSI_DisableAutoFromStop (void)
Disable HSI Automatic from stop mode.
__STATIC_INLINE uint32_t | LL_RCC_HSI_GetCalibration (void)
Get HSI Calibration value.
__STATIC_INLINE void | LL_RCC_HSI_SetCalibTrimming (uint32_t Value)
Set HSI Calibration trimming.
__STATIC_INLINE uint32_t | LL_RCC_HSI_GetCalibTrimming (void)
Get HSI Calibration trimming.

Function Documentation

__STATIC_INLINE void LL_RCC_HSI_Disable ( void )

Disable HSI oscillator.

Reference Manual to LL API cross reference:
CR HSION LL_RCC_HSI_Disable
Return values:
None

Definition at line 1478 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_HSI_DisableAutoFromStop ( void )

Disable HSI Automatic from stop mode.

Reference Manual to LL API cross reference:
CR HSIASFS LL_RCC_HSI_DisableAutoFromStop
Return values:
None

Definition at line 1508 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_HSI_DisableInStopMode ( void )

Disable HSI in stop mode.

Reference Manual to LL API cross reference:
CR HSIKERON LL_RCC_HSI_DisableInStopMode
Return values:
None

Definition at line 1448 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_HSI_Enable ( void )

Enable HSI oscillator.

Reference Manual to LL API cross reference:
CR HSION LL_RCC_HSI_Enable
Return values:
None

Definition at line 1468 of file stm32wbxx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSI().

__STATIC_INLINE void LL_RCC_HSI_EnableAutoFromStop ( void )

Enable HSI Automatic from stop mode.

Reference Manual to LL API cross reference:
CR HSIASFS LL_RCC_HSI_EnableAutoFromStop
Return values:
None

Definition at line 1498 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_HSI_EnableInStopMode ( void )

Enable HSI even in stop mode.

Note:
HSI oscillator is forced ON even in Stop mode
Reference Manual to LL API cross reference:
CR HSIKERON LL_RCC_HSI_EnableInStopMode
Return values:
None

Definition at line 1438 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration ( void )

Get HSI Calibration value.

Note:
When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value
Reference Manual to LL API cross reference:
ICSCR HSICAL LL_RCC_HSI_GetCalibration
Return values:
Between Min_Data = 0x00 and Max_Data = 0xFF

Definition at line 1519 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming ( void )

Get HSI Calibration trimming.

Reference Manual to LL API cross reference:
ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming
Return values:
Between Min_Data = 0 and Max_Data = 127

Definition at line 1543 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

__STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode ( void )

Check if HSI in stop mode is ready.

Reference Manual to LL API cross reference:
CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode
Return values:
State of bit (1 or 0).

Definition at line 1458 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady ( void )

Check if HSI clock is ready.

Reference Manual to LL API cross reference:
CR HSIRDY LL_RCC_HSI_IsReady
Return values:
State of bit (1 or 0).

Definition at line 1488 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_ClockConfig(), HAL_RCC_OscConfig(), HAL_RCCEx_GetPeriphCLKFreq(), LL_PLL_ConfigSystemClock_HSI(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetSAIClockFreq(), LL_RCC_GetSMPSClockFreq(), and LL_RCC_GetUSARTClockFreq().

__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming ( uint32_t Value )

Set HSI Calibration trimming.

Note:
user-programmable trimming value that is added to the HSICAL
Default value is 64, which, when added to the HSICAL value, should trim the HSI to 16 MHz +/- 1 %
Reference Manual to LL API cross reference:
ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming
Parameters:
Value Between Min_Data = 0 and Max_Data = 127
Return values:
None

Definition at line 1533 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_DeInit(), and LL_RCC_DeInit().

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: HSI48

Functions
HSI48
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_HSI48_Enable (void)
Enable HSI48.
__STATIC_INLINE void | LL_RCC_HSI48_Disable (void)
Disable HSI48.
__STATIC_INLINE uint32_t | LL_RCC_HSI48_IsReady (void)
Check if HSI48 oscillator Ready.
__STATIC_INLINE uint32_t | LL_RCC_HSI48_GetCalibration (void)
Get HSI48 Calibration value.

Function Documentation

__STATIC_INLINE void LL_RCC_HSI48_Disable ( void )

Disable HSI48.

Reference Manual to LL API cross reference:
CRRCR HSI48ON LL_RCC_HSI48_Disable
Return values:
None

Definition at line 1571 of file stm32wbxx_ll_rcc.h.

Referenced by LL_RCC_DeInit().

__STATIC_INLINE void LL_RCC_HSI48_Enable ( void )

Enable HSI48.

Reference Manual to LL API cross reference:
CRRCR HSI48ON LL_RCC_HSI48_Enable
Return values:
None

Definition at line 1561 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration ( void )

Get HSI48 Calibration value.

Reference Manual to LL API cross reference:
CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration
Return values:
Between Min_Data = 0x00 and Max_Data = 0x1FF

Definition at line 1591 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady ( void )

Check if HSI48 oscillator Ready.

Reference Manual to LL API cross reference:
CRRCR HSI48RDY LL_RCC_HSI48_IsReady
Return values:
State of bit (1 or 0).

Definition at line 1581 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_OscConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetCLK48ClockFreq().

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LSE

Functions
LSE
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_LSE_Enable (void)
Enable Low Speed External (LSE) crystal.
__STATIC_INLINE void | LL_RCC_LSE_Disable (void)
Disable Low Speed External (LSE) crystal.
__STATIC_INLINE uint32_t | LL_RCC_LSE_IsEnabled (void)
Check if Low Speed External (LSE) crystal has been enabled or not.
__STATIC_INLINE void | LL_RCC_LSE_EnableBypass (void)
Enable external clock source (LSE bypass).
__STATIC_INLINE void | LL_RCC_LSE_DisableBypass (void)
Disable external clock source (LSE bypass).
__STATIC_INLINE void | LL_RCC_LSE_SetDriveCapability (uint32_t LSEDrive)
Set LSE oscillator drive capability.
__STATIC_INLINE uint32_t | LL_RCC_LSE_GetDriveCapability (void)
Get LSE oscillator drive capability.
__STATIC_INLINE void | LL_RCC_LSE_EnableCSS (void)
Enable Clock security system on LSE.
__STATIC_INLINE void | LL_RCC_LSE_DisableCSS (void)
Disable Clock security system on LSE.
__STATIC_INLINE uint32_t | LL_RCC_LSE_IsReady (void)
Check if LSE oscillator Ready.
__STATIC_INLINE uint32_t | LL_RCC_LSE_IsCSSDetected (void)
Check if CSS on LSE failure Detection.

Function Documentation

__STATIC_INLINE void LL_RCC_LSE_Disable ( void )

Disable Low Speed External (LSE) crystal.

Reference Manual to LL API cross reference:
BDCR LSEON LL_RCC_LSE_Disable
Return values:
None

Definition at line 1619 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSE_DisableBypass ( void )

Disable external clock source (LSE bypass).

Reference Manual to LL API cross reference:
BDCR LSEBYP LL_RCC_LSE_DisableBypass
Return values:
None

Definition at line 1649 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSE_DisableCSS ( void )

Disable Clock security system on LSE.

Note:
Clock security system can be disabled only after a LSE failure detection. In that case it MUST be disabled by software.
Reference Manual to LL API cross reference:
BDCR LSECSSON LL_RCC_LSE_DisableCSS
Return values:
None

Definition at line 1701 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_DisableLSECSS().

__STATIC_INLINE void LL_RCC_LSE_Enable ( void )

Enable Low Speed External (LSE) crystal.

Reference Manual to LL API cross reference:
BDCR LSEON LL_RCC_LSE_Enable
Return values:
None

Definition at line 1609 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSE_EnableBypass ( void )

Enable external clock source (LSE bypass).

Reference Manual to LL API cross reference:
BDCR LSEBYP LL_RCC_LSE_EnableBypass
Return values:
None

Definition at line 1639 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSE_EnableCSS ( void )

Enable Clock security system on LSE.

Reference Manual to LL API cross reference:
BDCR LSECSSON LL_RCC_LSE_EnableCSS
Return values:
None

Definition at line 1689 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_EnableLSECSS(), and HAL_RCCEx_EnableLSECSS_IT().

__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability ( void )

Get LSE oscillator drive capability.

Reference Manual to LL API cross reference:
BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
Return values:
Returned value can be one of the following values:
  • LL_RCC_LSEDRIVE_LOW
  • LL_RCC_LSEDRIVE_MEDIUMLOW
  • LL_RCC_LSEDRIVE_MEDIUMHIGH
  • LL_RCC_LSEDRIVE_HIGH

Definition at line 1679 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected ( void )

Check if CSS on LSE failure Detection.

Reference Manual to LL API cross reference:
BDCR LSECSSD LL_RCC_LSE_IsCSSDetected
Return values:
State of bit (1 or 0).

Definition at line 1721 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_LSE_IsEnabled ( void )

Check if Low Speed External (LSE) crystal has been enabled or not.

Reference Manual to LL API cross reference:
BDCR LSEON LL_RCC_LSE_IsEnabled
Return values:
State of bit (1 or 0).

Definition at line 1629 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady ( void )

Check if LSE oscillator Ready.

Reference Manual to LL API cross reference:
BDCR LSERDY LL_RCC_LSE_IsReady
Return values:
State of bit (1 or 0).

Definition at line 1711 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_OscConfig(), HAL_RCCEx_GetPeriphCLKFreq(), HAL_RCCEx_PeriphCLKConfig(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetRFWKPClockFreq(), LL_RCC_GetRNGClockFreq(), LL_RCC_GetRTCClockFreq(), and LL_RCC_GetUSARTClockFreq().

__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability ( uint32_t LSEDrive )

Set LSE oscillator drive capability.

Note:
The oscillator is in Xtal mode when it is not in bypass mode.
Reference Manual to LL API cross reference:
BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
Parameters:
LSEDrive This parameter can be one of the following values:
  • LL_RCC_LSEDRIVE_LOW
  • LL_RCC_LSEDRIVE_MEDIUMLOW
  • LL_RCC_LSEDRIVE_MEDIUMHIGH
  • LL_RCC_LSEDRIVE_HIGH
Return values:
None

Definition at line 1665 of file stm32wbxx_ll_rcc.h.

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LSI1

Functions
LSI1
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_LSI1_Enable (void)
Enable LSI1 Oscillator.
__STATIC_INLINE void | LL_RCC_LSI1_Disable (void)
Disable LSI1 Oscillator.
__STATIC_INLINE uint32_t | LL_RCC_LSI1_IsReady (void)
Check if LSI1 is Ready.

Function Documentation

__STATIC_INLINE void LL_RCC_LSI1_Disable ( void )

Disable LSI1 Oscillator.

Reference Manual to LL API cross reference:
CSR LSI1ON LL_RCC_LSI1_Disable
Return values:
None

Definition at line 1749 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSI1_Enable ( void )

Enable LSI1 Oscillator.

Reference Manual to LL API cross reference:
CSR LSI1ON LL_RCC_LSI1_Enable
Return values:
None

Definition at line 1739 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_LSI1_IsReady ( void )

Check if LSI1 is Ready.

Reference Manual to LL API cross reference:
CSR LSI1RDY LL_RCC_LSI1_IsReady
Return values:
State of bit (1 or 0).

Definition at line 1759 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_OscConfig(), HAL_RCCEx_GetPeriphCLKFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetRFWKPClockFreq(), LL_RCC_GetRNGClockFreq(), and LL_RCC_GetRTCClockFreq().

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LSI2

Functions
LSI2
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_LSI2_Enable (void)
Enable LSI2 Oscillator.
__STATIC_INLINE void | LL_RCC_LSI2_Disable (void)
Disable LSI2 Oscillator.
__STATIC_INLINE uint32_t | LL_RCC_LSI2_IsReady (void)
Check if LSI2 is Ready.
__STATIC_INLINE void | LL_RCC_LSI2_SetTrimming (uint32_t Value)
Set LSI2 trimming value.
__STATIC_INLINE uint32_t | LL_RCC_LSI2_GetTrimming (void)
Get LSI2 trimming value.

Function Documentation

__STATIC_INLINE void LL_RCC_LSI2_Disable ( void )

Disable LSI2 Oscillator.

Reference Manual to LL API cross reference:
CSR LSI2ON LL_RCC_LSI2_Disable
Return values:
None

Definition at line 1787 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSI2_Enable ( void )

Enable LSI2 Oscillator.

Reference Manual to LL API cross reference:
CSR LSI2ON LL_RCC_LSI2_Enable
Return values:
None

Definition at line 1777 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_LSI2_GetTrimming ( void )

Get LSI2 trimming value.

Reference Manual to LL API cross reference:
CSR LSI2TRIM LL_RCC_LSI2_GetTrimming
Return values:
Between Min_Data = 0 and Max_Data = 12

Definition at line 1818 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_LSI2_IsReady ( void )

Check if LSI2 is Ready.

Reference Manual to LL API cross reference:
CSR LSI2RDY LL_RCC_LSI2_IsReady
Return values:
State of bit (1 or 0).

Definition at line 1797 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_OscConfig(), HAL_RCCEx_GetPeriphCLKFreq(), HAL_RCCEx_TrimOsc(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetRFWKPClockFreq(), LL_RCC_GetRNGClockFreq(), and LL_RCC_GetRTCClockFreq().

__STATIC_INLINE void LL_RCC_LSI2_SetTrimming ( uint32_t Value )

Set LSI2 trimming value.

Reference Manual to LL API cross reference:
CSR LSI2TRIM LL_RCC_LSI2_SetTrimming
Parameters:
Value Between Min_Data = 0 and Max_Data = 15
Return values:
None

Definition at line 1808 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_TrimOsc().

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: MSI

Functions
MSI
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_MSI_Enable (void)
Enable MSI oscillator.
__STATIC_INLINE void | LL_RCC_MSI_Disable (void)
Disable MSI oscillator.
__STATIC_INLINE uint32_t | LL_RCC_MSI_IsReady (void)
Check if MSI oscillator Ready.
__STATIC_INLINE void | LL_RCC_MSI_EnablePLLMode (void)
Enable MSI PLL-mode (Hardware auto calibration with LSE)
__STATIC_INLINE void | LL_RCC_MSI_DisablePLLMode (void)
Disable MSI-PLL mode.
__STATIC_INLINE void | LL_RCC_MSI_SetRange (uint32_t Range)
Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.
__STATIC_INLINE uint32_t | LL_RCC_MSI_GetRange (void)
Get the Internal Multi Speed oscillator (MSI) clock range in run mode.
__STATIC_INLINE uint32_t | LL_RCC_MSI_GetCalibration (void)
Get MSI Calibration value.
__STATIC_INLINE void | LL_RCC_MSI_SetCalibTrimming (uint32_t Value)
Set MSI Calibration trimming.
__STATIC_INLINE uint32_t | LL_RCC_MSI_GetCalibTrimming (void)
Get MSI Calibration trimming.

Function Documentation

__STATIC_INLINE void LL_RCC_MSI_Disable ( void )

Disable MSI oscillator.

Reference Manual to LL API cross reference:
CR MSION LL_RCC_MSI_Disable
Return values:
None

Definition at line 1846 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_MSI_DisablePLLMode ( void )

Disable MSI-PLL mode.

Note:
cleared by hardware when LSE is disabled (LSEON = 0) or when the Clock Security System on LSE detects a LSE failure
Reference Manual to LL API cross reference:
CR MSIPLLEN LL_RCC_MSI_DisablePLLMode
Return values:
None

Definition at line 1882 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_DisableMSIPLLMode().

__STATIC_INLINE void LL_RCC_MSI_Enable ( void )

Enable MSI oscillator.

Reference Manual to LL API cross reference:
CR MSION LL_RCC_MSI_Enable
Return values:
None

Definition at line 1836 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_DeInit(), LL_PLL_ConfigSystemClock_MSI(), and LL_RCC_DeInit().

__STATIC_INLINE void LL_RCC_MSI_EnablePLLMode ( void )

Enable MSI PLL-mode (Hardware auto calibration with LSE)

Note:
MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware)
hardware protection to avoid enabling MSIPLLEN if LSE is not ready
Reference Manual to LL API cross reference:
CR MSIPLLEN LL_RCC_MSI_EnablePLLMode
Return values:
None

Definition at line 1870 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_EnableMSIPLLMode().

__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration ( void )

Get MSI Calibration value.

Note:
When MSITRIM is written, MSICAL is updated with the sum of MSITRIM and the factory trim value
Reference Manual to LL API cross reference:
ICSCR MSICAL LL_RCC_MSI_GetCalibration
Return values:
Between Min_Data = 0 and Max_Data = 255

Definition at line 1946 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming ( void )

Get MSI Calibration trimming.

Reference Manual to LL API cross reference:
ICSCR MSITRIM LL_RCC_MSI_GetCalibTrimming
Return values:
Between 0 and 255

Definition at line 1968 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

__STATIC_INLINE uint32_t LL_RCC_MSI_GetRange ( void )

Get the Internal Multi Speed oscillator (MSI) clock range in run mode.

Reference Manual to LL API cross reference:
CR MSIRANGE LL_RCC_MSI_GetRange
Return values:
Returned value can be one of the following values:
  • LL_RCC_MSIRANGE_0
  • LL_RCC_MSIRANGE_1
  • LL_RCC_MSIRANGE_2
  • LL_RCC_MSIRANGE_3
  • LL_RCC_MSIRANGE_4
  • LL_RCC_MSIRANGE_5
  • LL_RCC_MSIRANGE_6
  • LL_RCC_MSIRANGE_7
  • LL_RCC_MSIRANGE_8
  • LL_RCC_MSIRANGE_9
  • LL_RCC_MSIRANGE_10
  • LL_RCC_MSIRANGE_11

Definition at line 1928 of file stm32wbxx_ll_rcc.h.

References LL_RCC_MSIRANGE_11.

Referenced by HAL_RCC_GetOscConfig(), HAL_RCC_GetSysClockFreq(), HAL_RCCEx_GetPeriphCLKFreq(), LL_PLL_ConfigSystemClock_MSI(), LL_RCC_GetCLK48ClockFreq(), LL_RCC_GetSMPSClockFreq(), RCC_GetSystemClockFreq(), RCC_PLL_GetFreqDomain_48M(), RCC_PLL_GetFreqDomain_ADC(), RCC_PLL_GetFreqDomain_P(), RCC_PLL_GetFreqDomain_Q(), RCC_PLL_GetFreqDomain_SAI(), RCC_PLL_GetFreqDomain_SYS(), RCC_PLLSAI1_GetFreqDomain_48M(), RCC_PLLSAI1_GetFreqDomain_ADC(), RCC_PLLSAI1_GetFreqDomain_P(), RCC_PLLSAI1_GetFreqDomain_Q(), RCC_PLLSAI1_GetFreqDomain_R(), and RCC_PLLSAI1_GetFreqDomain_SAI().

__STATIC_INLINE uint32_t LL_RCC_MSI_IsReady ( void )

Check if MSI oscillator Ready.

Reference Manual to LL API cross reference:
CR MSIRDY LL_RCC_MSI_IsReady
Return values:
State of bit (1 or 0).

Definition at line 1856 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_ClockConfig(), HAL_RCC_DeInit(), HAL_RCC_OscConfig(), HAL_RCCEx_GetPeriphCLKFreq(), LL_PLL_ConfigSystemClock_MSI(), LL_RCC_DeInit(), and LL_RCC_GetCLK48ClockFreq().

__STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming ( uint32_t Value )

Set MSI Calibration trimming.

Note:
user-programmable trimming value that is added to the MSICAL
Reference Manual to LL API cross reference:
ICSCR MSITRIM LL_RCC_MSI_SetCalibTrimming
Parameters:
Value Between Min_Data = 0 and Max_Data = 255
Return values:
None

Definition at line 1958 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_DeInit(), and LL_RCC_DeInit().

__STATIC_INLINE void LL_RCC_MSI_SetRange ( uint32_t Range )

Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.

Reference Manual to LL API cross reference:
CR MSIRANGE LL_RCC_MSI_SetRange
Parameters:
Range This parameter can be one of the following values:
  • LL_RCC_MSIRANGE_0
  • LL_RCC_MSIRANGE_1
  • LL_RCC_MSIRANGE_2
  • LL_RCC_MSIRANGE_3
  • LL_RCC_MSIRANGE_4
  • LL_RCC_MSIRANGE_5
  • LL_RCC_MSIRANGE_6
  • LL_RCC_MSIRANGE_7
  • LL_RCC_MSIRANGE_8
  • LL_RCC_MSIRANGE_9
  • LL_RCC_MSIRANGE_10
  • LL_RCC_MSIRANGE_11
Return values:
None

Definition at line 1906 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_DeInit(), and LL_RCC_DeInit().

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LSCO

Functions
LSCO
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_LSCO_Enable (void)
Enable Low speed clock.
__STATIC_INLINE void | LL_RCC_LSCO_Disable (void)
Disable Low speed clock.
__STATIC_INLINE void | LL_RCC_LSCO_SetSource (uint32_t Source)
Configure Low speed clock selection.
__STATIC_INLINE uint32_t | LL_RCC_LSCO_GetSource (void)
Get Low speed clock selection.

Function Documentation

__STATIC_INLINE void LL_RCC_LSCO_Disable ( void )

Disable Low speed clock.

Reference Manual to LL API cross reference:
BDCR LSCOEN LL_RCC_LSCO_Disable
Return values:
None

Definition at line 1996 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_DisableLSCO().

__STATIC_INLINE void LL_RCC_LSCO_Enable ( void )

Enable Low speed clock.

Reference Manual to LL API cross reference:
BDCR LSCOEN LL_RCC_LSCO_Enable
Return values:
None

Definition at line 1986 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource ( void )

Get Low speed clock selection.

Reference Manual to LL API cross reference:
BDCR LSCOSEL LL_RCC_LSCO_GetSource
Return values:
Returned value can be one of the following values:
  • LL_RCC_LSCO_CLKSOURCE_LSI
  • LL_RCC_LSCO_CLKSOURCE_LSE

Definition at line 2021 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSCO_SetSource ( uint32_t Source )

Configure Low speed clock selection.

Reference Manual to LL API cross reference:
BDCR LSCOSEL LL_RCC_LSCO_SetSource
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_LSCO_CLKSOURCE_LSI
  • LL_RCC_LSCO_CLKSOURCE_LSE
Return values:
None

Definition at line 2009 of file stm32wbxx_ll_rcc.h.

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: System

Functions
System
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_SetSysClkSource (uint32_t Source)
Configure the system clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSysClkSource (void)
Get the system clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetRFClockSource (void)
Get the RF clock source.
__STATIC_INLINE void | LL_RCC_SetRFWKPClockSource (uint32_t Source)
Set RF Wakeup Clock Source.
__STATIC_INLINE uint32_t | LL_RCC_GetRFWKPClockSource (void)
Get RF Wakeup Clock Source.
__STATIC_INLINE uint32_t | LL_RCC_IsRFUnderReset (void)
Check if Radio System is reset.
__STATIC_INLINE void | LL_RCC_SetAHBPrescaler (uint32_t Prescaler)
Set AHB prescaler.
__STATIC_INLINE void | LL_C2_RCC_SetAHBPrescaler (uint32_t Prescaler)
Set CPU2 AHB prescaler.
__STATIC_INLINE void | LL_RCC_SetAHB4Prescaler (uint32_t Prescaler)
Set AHB4 prescaler.
__STATIC_INLINE void | LL_RCC_SetAPB1Prescaler (uint32_t Prescaler)
Set APB1 prescaler.
__STATIC_INLINE void | LL_RCC_SetAPB2Prescaler (uint32_t Prescaler)
Set APB2 prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAHBPrescaler (void)
Get AHB prescaler.
__STATIC_INLINE uint32_t | LL_C2_RCC_GetAHBPrescaler (void)
Get C2 AHB prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAHB4Prescaler (void)
Get AHB4 prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAPB1Prescaler (void)
Get APB1 prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAPB2Prescaler (void)
Get APB2 prescaler.
__STATIC_INLINE void | LL_RCC_SetClkAfterWakeFromStop (uint32_t Clock)
Set Clock After Wake-Up From Stop mode.
__STATIC_INLINE uint32_t | LL_RCC_GetClkAfterWakeFromStop (void)
Get Clock After Wake-Up From Stop mode.

Function Documentation

__STATIC_INLINE uint32_t LL_C2_RCC_GetAHBPrescaler ( void )

Get C2 AHB prescaler.

Reference Manual to LL API cross reference:
EXTCFGR C2HPRE LL_C2_RCC_GetAHBPrescaler
Return values:
Returned value can be one of the following values:
  • LL_RCC_SYSCLK_DIV_1
  • LL_RCC_SYSCLK_DIV_2
  • LL_RCC_SYSCLK_DIV_3
  • LL_RCC_SYSCLK_DIV_4
  • LL_RCC_SYSCLK_DIV_5
  • LL_RCC_SYSCLK_DIV_6
  • LL_RCC_SYSCLK_DIV_8
  • LL_RCC_SYSCLK_DIV_10
  • LL_RCC_SYSCLK_DIV_16
  • LL_RCC_SYSCLK_DIV_32
  • LL_RCC_SYSCLK_DIV_64
  • LL_RCC_SYSCLK_DIV_128
  • LL_RCC_SYSCLK_DIV_256
  • LL_RCC_SYSCLK_DIV_512

Definition at line 2264 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_GetClockConfig(), HAL_RCC_GetHCLK2Freq(), and RCC_GetHCLK2ClockFreq().

__STATIC_INLINE void LL_C2_RCC_SetAHBPrescaler ( uint32_t Prescaler )

Set CPU2 AHB prescaler.

Reference Manual to LL API cross reference:
EXTCFGR C2HPRE LL_C2_RCC_SetAHBPrescaler
Parameters:
Prescaler This parameter can be one of the following values:
  • LL_RCC_SYSCLK_DIV_1
  • LL_RCC_SYSCLK_DIV_2
  • LL_RCC_SYSCLK_DIV_3
  • LL_RCC_SYSCLK_DIV_4
  • LL_RCC_SYSCLK_DIV_5
  • LL_RCC_SYSCLK_DIV_6
  • LL_RCC_SYSCLK_DIV_8
  • LL_RCC_SYSCLK_DIV_10
  • LL_RCC_SYSCLK_DIV_16
  • LL_RCC_SYSCLK_DIV_32
  • LL_RCC_SYSCLK_DIV_64
  • LL_RCC_SYSCLK_DIV_128
  • LL_RCC_SYSCLK_DIV_256
  • LL_RCC_SYSCLK_DIV_512
Return values:
None

Definition at line 2159 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE uint32_t LL_RCC_GetAHB4Prescaler ( void )

Get AHB4 prescaler.

Reference Manual to LL API cross reference:
EXTCFGR SHDHPRE LL_RCC_GetAHB4Prescaler
Return values:
Returned value can be one of the following values:
  • LL_RCC_SYSCLK_DIV_1
  • LL_RCC_SYSCLK_DIV_2
  • LL_RCC_SYSCLK_DIV_3
  • LL_RCC_SYSCLK_DIV_4
  • LL_RCC_SYSCLK_DIV_5
  • LL_RCC_SYSCLK_DIV_6
  • LL_RCC_SYSCLK_DIV_8
  • LL_RCC_SYSCLK_DIV_10
  • LL_RCC_SYSCLK_DIV_16
  • LL_RCC_SYSCLK_DIV_32
  • LL_RCC_SYSCLK_DIV_64
  • LL_RCC_SYSCLK_DIV_128
  • LL_RCC_SYSCLK_DIV_256
  • LL_RCC_SYSCLK_DIV_512

Definition at line 2288 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_GetClockConfig(), HAL_RCC_GetHCLK4Freq(), RCC_GetHCLK4ClockFreq(), RCC_SetFlashLatencyFromMSIRange(), and UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler ( void )

Get AHB prescaler.

Reference Manual to LL API cross reference:
CFGR HPRE LL_RCC_GetAHBPrescaler
Return values:
Returned value can be one of the following values:
  • LL_RCC_SYSCLK_DIV_1
  • LL_RCC_SYSCLK_DIV_2
  • LL_RCC_SYSCLK_DIV_3
  • LL_RCC_SYSCLK_DIV_4
  • LL_RCC_SYSCLK_DIV_5
  • LL_RCC_SYSCLK_DIV_6
  • LL_RCC_SYSCLK_DIV_8
  • LL_RCC_SYSCLK_DIV_10
  • LL_RCC_SYSCLK_DIV_16
  • LL_RCC_SYSCLK_DIV_32
  • LL_RCC_SYSCLK_DIV_64
  • LL_RCC_SYSCLK_DIV_128
  • LL_RCC_SYSCLK_DIV_256
  • LL_RCC_SYSCLK_DIV_512

Definition at line 2240 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_GetClockConfig(), HAL_RCC_GetHCLKFreq(), HAL_RCCEx_GetPeriphCLKFreq(), RCC_GetHCLK1ClockFreq(), and UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler ( void )

Get APB1 prescaler.

Reference Manual to LL API cross reference:
CFGR PPRE1 LL_RCC_GetAPB1Prescaler
Return values:
Returned value can be one of the following values:
  • LL_RCC_APB1_DIV_1
  • LL_RCC_APB1_DIV_2
  • LL_RCC_APB1_DIV_4
  • LL_RCC_APB1_DIV_8
  • LL_RCC_APB1_DIV_16

Definition at line 2303 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_GetClockConfig(), HAL_RCC_GetPCLK1Freq(), HAL_RCCEx_GetPeriphCLKFreq(), and RCC_GetPCLK1ClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler ( void )

Get APB2 prescaler.

Reference Manual to LL API cross reference:
CFGR PPRE2 LL_RCC_GetAPB2Prescaler
Return values:
Returned value can be one of the following values:
  • LL_RCC_APB2_DIV_1
  • LL_RCC_APB2_DIV_2
  • LL_RCC_APB2_DIV_4
  • LL_RCC_APB2_DIV_8
  • LL_RCC_APB2_DIV_16

Definition at line 2318 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_GetClockConfig(), HAL_RCC_GetPCLK2Freq(), HAL_RCCEx_GetPeriphCLKFreq(), and RCC_GetPCLK2ClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop ( void )

Get Clock After Wake-Up From Stop mode.

Reference Manual to LL API cross reference:
CFGR STOPWUCK LL_RCC_GetClkAfterWakeFromStop
Return values:
Returned value can be one of the following values:
  • LL_RCC_STOP_WAKEUPCLOCK_MSI
  • LL_RCC_STOP_WAKEUPCLOCK_HSI

Definition at line 2343 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_GetRFClockSource ( void )

Get the RF clock source.

Reference Manual to LL API cross reference:
EXTCFGR RFCSS LL_RCC_GetRFClockSource
Return values:
Returned value can be one of the following values:
  • LL_RCC_RF_CLKSOURCE_HSI
  • LL_RCC_RF_CLKSOURCE_HSE_DIV2

Definition at line 2070 of file stm32wbxx_ll_rcc.h.

Referenced by RCC_GetHCLK5ClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetRFWKPClockSource ( void )

Get RF Wakeup Clock Source.

Reference Manual to LL API cross reference:
CSR RFWKPSEL LL_RCC_GetRFWKPClockSource
Return values:
Returned value can be one of the following values:
  • LL_RCC_RFWKP_CLKSOURCE_NONE
  • LL_RCC_RFWKP_CLKSOURCE_LSE
  • LL_RCC_RFWKP_CLKSOURCE_LSI
  • LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024

Definition at line 2099 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetRFWKPClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource ( void )

Get the system clock source.

Reference Manual to LL API cross reference:
CFGR SWS LL_RCC_GetSysClkSource
Return values:
Returned value can be one of the following values:
  • LL_RCC_SYS_CLKSOURCE_STATUS_MSI
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSI
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSE
  • LL_RCC_SYS_CLKSOURCE_STATUS_PLL

Definition at line 2058 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_GetClockConfig(), LL_RCC_DeInit(), RCC_GetSystemClockFreq(), and UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE uint32_t LL_RCC_IsRFUnderReset ( void )

Check if Radio System is reset.

Reference Manual to LL API cross reference:
CSR RFRSTS LL_RCC_IsRFUnderReset
Return values:
State of bit (1 or 0).

Definition at line 2109 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetAHB4Prescaler ( uint32_t Prescaler )

Set AHB4 prescaler.

Reference Manual to LL API cross reference:
EXTCFGR SHDHPRE LL_RCC_SetAHB4Prescaler
Parameters:
Prescaler This parameter can be one of the following values:
  • LL_RCC_SYSCLK_DIV_1
  • LL_RCC_SYSCLK_DIV_2
  • LL_RCC_SYSCLK_DIV_3
  • LL_RCC_SYSCLK_DIV_4
  • LL_RCC_SYSCLK_DIV_5
  • LL_RCC_SYSCLK_DIV_6
  • LL_RCC_SYSCLK_DIV_8
  • LL_RCC_SYSCLK_DIV_10
  • LL_RCC_SYSCLK_DIV_16
  • LL_RCC_SYSCLK_DIV_32
  • LL_RCC_SYSCLK_DIV_64
  • LL_RCC_SYSCLK_DIV_128
  • LL_RCC_SYSCLK_DIV_256
  • LL_RCC_SYSCLK_DIV_512
Return values:
None

Definition at line 2184 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE void LL_RCC_SetAHBPrescaler ( uint32_t Prescaler )

Set AHB prescaler.

Reference Manual to LL API cross reference:
CFGR HPRE LL_RCC_SetAHBPrescaler
Parameters:
Prescaler This parameter can be one of the following values:
  • LL_RCC_SYSCLK_DIV_1
  • LL_RCC_SYSCLK_DIV_2
  • LL_RCC_SYSCLK_DIV_3
  • LL_RCC_SYSCLK_DIV_4
  • LL_RCC_SYSCLK_DIV_5
  • LL_RCC_SYSCLK_DIV_6
  • LL_RCC_SYSCLK_DIV_8
  • LL_RCC_SYSCLK_DIV_10
  • LL_RCC_SYSCLK_DIV_16
  • LL_RCC_SYSCLK_DIV_32
  • LL_RCC_SYSCLK_DIV_64
  • LL_RCC_SYSCLK_DIV_128
  • LL_RCC_SYSCLK_DIV_256
  • LL_RCC_SYSCLK_DIV_512
Return values:
None

Definition at line 2134 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE void LL_RCC_SetAPB1Prescaler ( uint32_t Prescaler )

Set APB1 prescaler.

Reference Manual to LL API cross reference:
CFGR PPRE1 LL_RCC_SetAPB1Prescaler
Parameters:
Prescaler This parameter can be one of the following values:
  • LL_RCC_APB1_DIV_1
  • LL_RCC_APB1_DIV_2
  • LL_RCC_APB1_DIV_4
  • LL_RCC_APB1_DIV_8
  • LL_RCC_APB1_DIV_16
Return values:
None

Definition at line 2200 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE void LL_RCC_SetAPB2Prescaler ( uint32_t Prescaler )

Set APB2 prescaler.

Reference Manual to LL API cross reference:
CFGR PPRE2 LL_RCC_SetAPB2Prescaler
Parameters:
Prescaler This parameter can be one of the following values:
  • LL_RCC_APB2_DIV_1
  • LL_RCC_APB2_DIV_2
  • LL_RCC_APB2_DIV_4
  • LL_RCC_APB2_DIV_8
  • LL_RCC_APB2_DIV_16
Return values:
None

Definition at line 2216 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop ( uint32_t Clock )

Set Clock After Wake-Up From Stop mode.

Reference Manual to LL API cross reference:
CFGR STOPWUCK LL_RCC_SetClkAfterWakeFromStop
Parameters:
Clock This parameter can be one of the following values:
  • LL_RCC_STOP_WAKEUPCLOCK_MSI
  • LL_RCC_STOP_WAKEUPCLOCK_HSI
Return values:
None

Definition at line 2331 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetRFWKPClockSource ( uint32_t Source )

Set RF Wakeup Clock Source.

Reference Manual to LL API cross reference:
CSR RFWKPSEL LL_RCC_SetRFWKPClockSource
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_RFWKP_CLKSOURCE_NONE
  • LL_RCC_RFWKP_CLKSOURCE_LSE
  • LL_RCC_RFWKP_CLKSOURCE_LSI
  • LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024
Return values:
None

Definition at line 2085 of file stm32wbxx_ll_rcc.h.

Referenced by LL_RCC_DeInit().

__STATIC_INLINE void LL_RCC_SetSysClkSource ( uint32_t Source )

Configure the system clock source.

Reference Manual to LL API cross reference:
CFGR SW LL_RCC_SetSysClkSource
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_SYS_CLKSOURCE_MSI
  • LL_RCC_SYS_CLKSOURCE_HSI
  • LL_RCC_SYS_CLKSOURCE_HSE
  • LL_RCC_SYS_CLKSOURCE_PLL
Return values:
None

Definition at line 2044 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and UTILS_EnablePLLAndSwitchSystem().

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMPS

Functions
SMPS
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_SetSMPSClockSource (uint32_t SMPSSource)
Configure SMPS step down converter clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSMPSClockSelection (void)
Get the SMPS clock source selection.
__STATIC_INLINE uint32_t | LL_RCC_GetSMPSClockSource (void)
Get the SMPS clock source.
__STATIC_INLINE void | LL_RCC_SetSMPSPrescaler (uint32_t Prescaler)
Set SMPS prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetSMPSPrescaler (void)
Get SMPS prescaler.

Function Documentation

__STATIC_INLINE uint32_t LL_RCC_GetSMPSClockSelection ( void )

Get the SMPS clock source selection.

Reference Manual to LL API cross reference:
SMPSCR SMPSSEL LL_RCC_GetSMPSClockSelection
Return values:
Returned value can be one of the following values:
  • LL_RCC_SMPS_CLKSOURCE_HSI
  • LL_RCC_SMPS_CLKSOURCE_MSI
  • LL_RCC_SMPS_CLKSOURCE_HSE

Definition at line 2383 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_GetSMPSClockSource ( void )

Get the SMPS clock source.

Reference Manual to LL API cross reference:
SMPSCR SMPSSWS LL_RCC_GetSMPSClockSource
Return values:
Returned value can be one of the following values:
  • LL_RCC_SMPS_CLKSOURCE_STATUS_HSI
  • LL_RCC_SMPS_CLKSOURCE_STATUS_MSI
  • LL_RCC_SMPS_CLKSOURCE_STATUS_HSE
  • LL_RCC_SMPS_CLKSOURCE_STATUS_NO_CLOCK

Definition at line 2398 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetSMPSClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetSMPSPrescaler ( void )

Get SMPS prescaler.

Reference Manual to LL API cross reference:
SMPSCR SMPSDIV LL_RCC_GetSMPSPrescaler
Return values:
Returned value can be one of the following values:
  • LL_RCC_SMPS_DIV_0
  • LL_RCC_SMPS_DIV_1
  • LL_RCC_SMPS_DIV_2
  • LL_RCC_SMPS_DIV_3

Definition at line 2427 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetSMPSClockFreq().

__STATIC_INLINE void LL_RCC_SetSMPSClockSource ( uint32_t SMPSSource )

Configure SMPS step down converter clock source.

Reference Manual to LL API cross reference:
SMPSCR SMPSSEL LL_RCC_SetSMPSClockSource
Parameters:
SMPSSource This parameter can be one of the following values:
  • LL_RCC_SMPS_CLKSOURCE_HSI
  • LL_RCC_SMPS_CLKSOURCE_MSI (*)
  • LL_RCC_SMPS_CLKSOURCE_HSE
Note:
The system must always be configured so as to get a SMPS Step Down converter clock frequency between 2 MHz and 8 MHz
(*) The MSI shall only be selected as SMPS Step Down converter clock source when a supported SMPS Step Down converter clock MSIRANGE is set (LL_RCC_MSIRANGE_8 to LL_RCC_MSIRANGE_11)
Return values:
None

Definition at line 2370 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetSMPSPrescaler ( uint32_t Prescaler )

Set SMPS prescaler.

Reference Manual to LL API cross reference:
SMPSCR SMPSDIV LL_RCC_SetSMPSPrescaler
Parameters:
Prescaler This parameter can be one of the following values:
  • LL_RCC_SMPS_DIV_0
  • LL_RCC_SMPS_DIV_1
  • LL_RCC_SMPS_DIV_2
  • LL_RCC_SMPS_DIV_3
Return values:
None

Definition at line 2413 of file stm32wbxx_ll_rcc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: MCO

Functions
MCO
RCC Exported Functions

Functions

__STATIC_INLINE void LL_RCC_ConfigMCO (uint32_t MCOxSource, uint32_t MCOxPrescaler)
Configure MCOx.

Function Documentation

__STATIC_INLINE void LL_RCC_ConfigMCO | ( | uint32_t | MCOxSource,
 |  | uint32_t | MCOxPrescaler
 | ) |  |

Configure MCOx.

Reference Manual to LL API cross reference:
CFGR MCOSEL LL_RCC_ConfigMCO
CFGR MCOPRE LL_RCC_ConfigMCO
Parameters:
MCOxSource This parameter can be one of the following values:
  • LL_RCC_MCO1SOURCE_NOCLOCK
  • LL_RCC_MCO1SOURCE_SYSCLK
  • LL_RCC_MCO1SOURCE_MSI
  • LL_RCC_MCO1SOURCE_HSI
  • LL_RCC_MCO1SOURCE_HSE
  • LL_RCC_MCO1SOURCE_HSI48
  • LL_RCC_MCO1SOURCE_PLLCLK
  • LL_RCC_MCO1SOURCE_LSI1
  • LL_RCC_MCO1SOURCE_LSI2
  • LL_RCC_MCO1SOURCE_LSE
  • LL_RCC_MCO1SOURCE_HSE_BEFORE_STAB
MCOxPrescaler This parameter can be one of the following values:
  • LL_RCC_MCO1_DIV_1
  • LL_RCC_MCO1_DIV_2
  • LL_RCC_MCO1_DIV_4
  • LL_RCC_MCO1_DIV_8
  • LL_RCC_MCO1_DIV_16
Return values:
None

Definition at line 2465 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_MCOConfig().

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Peripheral Clock Source

Functions
Peripheral Clock Source
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_SetUSARTClockSource (uint32_t USARTxSource)
Configure USARTx clock source.
__STATIC_INLINE void | LL_RCC_SetLPUARTClockSource (uint32_t LPUARTxSource)
Configure LPUART1x clock source.
__STATIC_INLINE void | LL_RCC_SetI2CClockSource (uint32_t I2CxSource)
Configure I2Cx clock source.
__STATIC_INLINE void | LL_RCC_SetLPTIMClockSource (uint32_t LPTIMxSource)
Configure LPTIMx clock source.
__STATIC_INLINE void | LL_RCC_SetSAIClockSource (uint32_t SAIxSource)
Configure SAIx clock source.
__STATIC_INLINE void | LL_RCC_SetRNGClockSource (uint32_t RNGxSource)
Configure RNG clock source.
__STATIC_INLINE void | LL_RCC_SetCLK48ClockSource (uint32_t CLK48xSource)
Configure CLK48 clock source.
__STATIC_INLINE void | LL_RCC_SetUSBClockSource (uint32_t USBxSource)
Configure USB clock source.
__STATIC_INLINE void | LL_RCC_ConfigRNGClockSource (uint32_t RNGxSource, uint32_t CLK48xSource)
Configure RNG clock source.
__STATIC_INLINE void | LL_RCC_SetADCClockSource (uint32_t ADCxSource)
Configure ADC clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetUSARTClockSource (uint32_t USARTx)
Get USARTx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetLPUARTClockSource (uint32_t LPUARTx)
Get LPUARTx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetI2CClockSource (uint32_t I2Cx)
Get I2Cx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetLPTIMClockSource (uint32_t LPTIMx)
Get LPTIMx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSAIClockSource (uint32_t SAIx)
Get SAIx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetRNGClockSource (uint32_t RNGx)
Get RNGx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetCLK48ClockSource (uint32_t CLK48x)
Get CLK48x clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetUSBClockSource (uint32_t USBx)
Get USBx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetADCClockSource (uint32_t ADCx)
Get ADCx clock source.

Function Documentation

__STATIC_INLINE void LL_RCC_ConfigRNGClockSource | ( | uint32_t | RNGxSource,
 |  | uint32_t | CLK48xSource
 | ) |  |

Configure RNG clock source.

Note:
Allow to configure the overall RNG Clock source, if CLK48 is selected as RNG Clock source, the CLK48xSource has to be configured
Reference Manual to LL API cross reference:
CCIPR RNGSEL LL_RCC_ConfigRNGClockSource
Reference Manual to LL API cross reference:
CCIPR CLK48SEL LL_RCC_ConfigRNGClockSource
Parameters:
RNGxSource This parameter can be one of the following values:
  • LL_RCC_RNG_CLKSOURCE_CLK48
  • LL_RCC_RNG_CLKSOURCE_LSI
  • LL_RCC_RNG_CLKSOURCE_LSE
CLK48xSource This parameter can be one of the following values:
  • LL_RCC_CLK48_CLKSOURCE_HSI48
  • LL_RCC_CLK48_CLKSOURCE_PLLSAI1
  • LL_RCC_CLK48_CLKSOURCE_PLL
  • LL_RCC_CLK48_CLKSOURCE_MSI
Return values:
None

Definition at line 2626 of file stm32wbxx_ll_rcc.h.

References LL_RCC_RNG_CLKSOURCE_CLK48, LL_RCC_SetCLK48ClockSource(), and LL_RCC_SetRNGClockSource().

__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource ( uint32_t ADCx )

Get ADCx clock source.

Reference Manual to LL API cross reference:
CCIPR ADCSEL LL_RCC_GetADCClockSource
Parameters:
ADCx This parameter can be one of the following values:
  • LL_RCC_ADC_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_ADC_CLKSOURCE_NONE
  • LL_RCC_ADC_CLKSOURCE_PLLSAI1
  • LL_RCC_ADC_CLKSOURCE_PLL
  • LL_RCC_ADC_CLKSOURCE_SYSCLK

Definition at line 2801 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetADCClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetCLK48ClockSource ( uint32_t CLK48x )

Get CLK48x clock source.

Reference Manual to LL API cross reference:
CCIPR CLK48SEL LL_RCC_GetCLK48ClockSource
Parameters:
CLK48x This parameter can be one of the following values:
  • LL_RCC_CLK48_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_USB_CLKSOURCE_HSI48
  • LL_RCC_USB_CLKSOURCE_PLLSAI1
  • LL_RCC_USB_CLKSOURCE_PLL
  • LL_RCC_USB_CLKSOURCE_MSI

Definition at line 2769 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetRngCLKSource(), LL_RCC_GetCLK48ClockFreq(), and LL_RCC_GetUSBClockSource().

__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource ( uint32_t I2Cx )

Get I2Cx clock source.

Reference Manual to LL API cross reference:
CCIPR I2CxSEL LL_RCC_GetI2CClockSource
Parameters:
I2Cx This parameter can be one of the following values:
  • LL_RCC_I2C1_CLKSOURCE
  • LL_RCC_I2C3_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_I2C1_CLKSOURCE_PCLK1
  • LL_RCC_I2C1_CLKSOURCE_SYSCLK
  • LL_RCC_I2C1_CLKSOURCE_HSI
  • LL_RCC_I2C3_CLKSOURCE_PCLK1
  • LL_RCC_I2C3_CLKSOURCE_SYSCLK
  • LL_RCC_I2C3_CLKSOURCE_HSI

Definition at line 2699 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetI2CClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource ( uint32_t LPTIMx )

Get LPTIMx clock source.

Reference Manual to LL API cross reference:
CCIPR LPTIMxSEL LL_RCC_GetLPTIMClockSource
Parameters:
LPTIMx This parameter can be one of the following values:
  • LL_RCC_LPTIM1_CLKSOURCE
  • LL_RCC_LPTIM2_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_LPTIM1_CLKSOURCE_PCLK1
  • LL_RCC_LPTIM1_CLKSOURCE_LSI
  • LL_RCC_LPTIM1_CLKSOURCE_HSI
  • LL_RCC_LPTIM1_CLKSOURCE_LSE
  • LL_RCC_LPTIM2_CLKSOURCE_PCLK1
  • LL_RCC_LPTIM2_CLKSOURCE_LSI
  • LL_RCC_LPTIM2_CLKSOURCE_HSI
  • LL_RCC_LPTIM2_CLKSOURCE_LSE

Definition at line 2720 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), LL_LPTIM_Disable(), and LL_RCC_GetLPTIMClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource ( uint32_t LPUARTx )

Get LPUARTx clock source.

Reference Manual to LL API cross reference:
CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource
Parameters:
LPUARTx This parameter can be one of the following values:
  • LL_RCC_LPUART1_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_LPUART1_CLKSOURCE_PCLK1
  • LL_RCC_LPUART1_CLKSOURCE_SYSCLK
  • LL_RCC_LPUART1_CLKSOURCE_HSI
  • LL_RCC_LPUART1_CLKSOURCE_LSE

Definition at line 2679 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetLPUARTClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource ( uint32_t RNGx )

Get RNGx clock source.

Reference Manual to LL API cross reference:
CCIPR RNGSEL LL_RCC_GetRNGClockSource
Parameters:
RNGx This parameter can be one of the following values:
  • LL_RCC_RNG_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_RNG_CLKSOURCE_CLK48
  • LL_RCC_RNG_CLKSOURCE_LSI
  • LL_RCC_RNG_CLKSOURCE_LSE

Definition at line 2753 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetRngCLKSource(), and LL_RCC_GetRNGClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource ( uint32_t SAIx )

Get SAIx clock source.

Reference Manual to LL API cross reference:
CCIPR SAI1SEL LL_RCC_GetSAIClockSource
Parameters:
SAIx This parameter can be one of the following values:
  • LL_RCC_SAI1_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_SAI1_CLKSOURCE_PLLSAI1
  • LL_RCC_SAI1_CLKSOURCE_PLL
  • LL_RCC_SAI1_CLKSOURCE_HSI
  • LL_RCC_SAI1_CLKSOURCE_PIN

Definition at line 2737 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetSAIClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource ( uint32_t USARTx )

Get USARTx clock source.

Reference Manual to LL API cross reference:
CCIPR USART1SEL LL_RCC_GetUSARTClockSource
Parameters:
USARTx This parameter can be one of the following values:
  • LL_RCC_USART1_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_USART1_CLKSOURCE_PCLK2
  • LL_RCC_USART1_CLKSOURCE_SYSCLK
  • LL_RCC_USART1_CLKSOURCE_HSI
  • LL_RCC_USART1_CLKSOURCE_LSE

Definition at line 2662 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetUSARTClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource ( uint32_t USBx )

Get USBx clock source.

Reference Manual to LL API cross reference:
CCIPR CLK48SEL LL_RCC_GetUSBClockSource
Parameters:
USBx This parameter can be one of the following values:
  • LL_RCC_USB_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_USB_CLKSOURCE_HSI48
  • LL_RCC_USB_CLKSOURCE_PLLSAI1
  • LL_RCC_USB_CLKSOURCE_PLL
  • LL_RCC_USB_CLKSOURCE_MSI

Definition at line 2785 of file stm32wbxx_ll_rcc.h.

References LL_RCC_GetCLK48ClockSource().

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

__STATIC_INLINE void LL_RCC_SetADCClockSource ( uint32_t ADCxSource )

Configure ADC clock source.

Reference Manual to LL API cross reference:
CCIPR ADCSEL LL_RCC_SetADCClockSource
Parameters:
ADCxSource This parameter can be one of the following values:
  • LL_RCC_ADC_CLKSOURCE_NONE
  • LL_RCC_ADC_CLKSOURCE_PLLSAI1
  • LL_RCC_ADC_CLKSOURCE_PLL
  • LL_RCC_ADC_CLKSOURCE_SYSCLK
Return values:
None

Definition at line 2646 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetCLK48ClockSource ( uint32_t CLK48xSource )

Configure CLK48 clock source.

Reference Manual to LL API cross reference:
CCIPR CLK48SEL LL_RCC_SetCLK48ClockSource
Parameters:
CLK48xSource This parameter can be one of the following values:
  • LL_RCC_CLK48_CLKSOURCE_HSI48
  • LL_RCC_CLK48_CLKSOURCE_PLLSAI1
  • LL_RCC_CLK48_CLKSOURCE_PLL
  • LL_RCC_CLK48_CLKSOURCE_MSI
Return values:
None

Definition at line 2588 of file stm32wbxx_ll_rcc.h.

Referenced by LL_RCC_ConfigRNGClockSource(), and LL_RCC_SetUSBClockSource().

__STATIC_INLINE void LL_RCC_SetI2CClockSource ( uint32_t I2CxSource )

Configure I2Cx clock source.

Reference Manual to LL API cross reference:
CCIPR I2CxSEL LL_RCC_SetI2CClockSource
Parameters:
I2CxSource This parameter can be one of the following values:
  • LL_RCC_I2C1_CLKSOURCE_PCLK1
  • LL_RCC_I2C1_CLKSOURCE_SYSCLK
  • LL_RCC_I2C1_CLKSOURCE_HSI
  • LL_RCC_I2C3_CLKSOURCE_PCLK1
  • LL_RCC_I2C3_CLKSOURCE_SYSCLK
  • LL_RCC_I2C3_CLKSOURCE_HSI
Return values:
None

Definition at line 2522 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetLPTIMClockSource ( uint32_t LPTIMxSource )

Configure LPTIMx clock source.

Reference Manual to LL API cross reference:
CCIPR LPTIMxSEL LL_RCC_SetLPTIMClockSource
Parameters:
LPTIMxSource This parameter can be one of the following values:
  • LL_RCC_LPTIM1_CLKSOURCE_PCLK1
  • LL_RCC_LPTIM1_CLKSOURCE_LSI
  • LL_RCC_LPTIM1_CLKSOURCE_HSI
  • LL_RCC_LPTIM1_CLKSOURCE_LSE
  • LL_RCC_LPTIM2_CLKSOURCE_PCLK1
  • LL_RCC_LPTIM2_CLKSOURCE_LSI
  • LL_RCC_LPTIM2_CLKSOURCE_HSI
  • LL_RCC_LPTIM2_CLKSOURCE_LSE
Return values:
None

Definition at line 2541 of file stm32wbxx_ll_rcc.h.

Referenced by LL_LPTIM_Disable().

__STATIC_INLINE void LL_RCC_SetLPUARTClockSource ( uint32_t LPUARTxSource )

Configure LPUART1x clock source.

Reference Manual to LL API cross reference:
CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource
Parameters:
LPUARTxSource This parameter can be one of the following values:
  • LL_RCC_LPUART1_CLKSOURCE_PCLK1
  • LL_RCC_LPUART1_CLKSOURCE_SYSCLK
  • LL_RCC_LPUART1_CLKSOURCE_HSI
  • LL_RCC_LPUART1_CLKSOURCE_LSE
Return values:
None

Definition at line 2504 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetRNGClockSource ( uint32_t RNGxSource )

Configure RNG clock source.

Note:
In case of CLK48 clock selected, it must be configured first thanks to LL_RCC_SetCLK48ClockSource
Reference Manual to LL API cross reference:
CCIPR RNGSEL LL_RCC_SetRNGClockSource
Parameters:
RNGxSource This parameter can be one of the following values:
  • LL_RCC_RNG_CLKSOURCE_CLK48
  • LL_RCC_RNG_CLKSOURCE_LSI
  • LL_RCC_RNG_CLKSOURCE_LSE
Return values:
None

Definition at line 2573 of file stm32wbxx_ll_rcc.h.

Referenced by LL_RCC_ConfigRNGClockSource().

__STATIC_INLINE void LL_RCC_SetSAIClockSource ( uint32_t SAIxSource )

Configure SAIx clock source.

Reference Manual to LL API cross reference:
CCIPR SAI1SEL LL_RCC_SetSAIClockSource
Parameters:
SAIxSource This parameter can be one of the following values:
  • LL_RCC_SAI1_CLKSOURCE_PLLSAI1
  • LL_RCC_SAI1_CLKSOURCE_PLL
  • LL_RCC_SAI1_CLKSOURCE_HSI
  • LL_RCC_SAI1_CLKSOURCE_PIN
Return values:
None

Definition at line 2557 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetUSARTClockSource ( uint32_t USARTxSource )

Configure USARTx clock source.

Reference Manual to LL API cross reference:
CCIPR USART1SEL LL_RCC_SetUSARTClockSource
Parameters:
USARTxSource This parameter can be one of the following values:
  • LL_RCC_USART1_CLKSOURCE_PCLK2
  • LL_RCC_USART1_CLKSOURCE_SYSCLK
  • LL_RCC_USART1_CLKSOURCE_HSI
  • LL_RCC_USART1_CLKSOURCE_LSE
Return values:
None

Definition at line 2488 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetUSBClockSource ( uint32_t USBxSource )

Configure USB clock source.

Reference Manual to LL API cross reference:
CCIPR CLK48SEL LL_RCC_SetUSBClockSource
Parameters:
USBxSource This parameter can be one of the following values:
  • LL_RCC_USB_CLKSOURCE_HSI48
  • LL_RCC_USB_CLKSOURCE_PLLSAI1
  • LL_RCC_USB_CLKSOURCE_PLL
  • LL_RCC_USB_CLKSOURCE_MSI
Return values:
None

Definition at line 2603 of file stm32wbxx_ll_rcc.h.

References LL_RCC_SetCLK48ClockSource().

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC

Functions
RTC
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_SetRTCClockSource (uint32_t Source)
Set RTC Clock Source.
__STATIC_INLINE uint32_t | LL_RCC_GetRTCClockSource (void)
Get RTC Clock Source.
__STATIC_INLINE void | LL_RCC_EnableRTC (void)
Enable RTC.
__STATIC_INLINE void | LL_RCC_DisableRTC (void)
Disable RTC.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledRTC (void)
Check if RTC has been enabled or not.
__STATIC_INLINE void | LL_RCC_ForceBackupDomainReset (void)
Force the Backup domain reset.
__STATIC_INLINE void | LL_RCC_ReleaseBackupDomainReset (void)
Release the Backup domain reset.

Function Documentation

__STATIC_INLINE void LL_RCC_DisableRTC ( void )

Disable RTC.

Reference Manual to LL API cross reference:
BDCR RTCEN LL_RCC_DisableRTC
Return values:
None

Definition at line 2861 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableRTC ( void )

Enable RTC.

Reference Manual to LL API cross reference:
BDCR RTCEN LL_RCC_EnableRTC
Return values:
None

Definition at line 2851 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ForceBackupDomainReset ( void )

Force the Backup domain reset.

Reference Manual to LL API cross reference:
BDCR BDRST LL_RCC_ForceBackupDomainReset
Return values:
None

Definition at line 2881 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource ( void )

Get RTC Clock Source.

Reference Manual to LL API cross reference:
BDCR RTCSEL LL_RCC_GetRTCClockSource
Return values:
Returned value can be one of the following values:
  • LL_RCC_RTC_CLKSOURCE_NONE
  • LL_RCC_RTC_CLKSOURCE_LSE
  • LL_RCC_RTC_CLKSOURCE_LSI
  • LL_RCC_RTC_CLKSOURCE_HSE_DIV32

Definition at line 2841 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), HAL_RCCEx_PeriphCLKConfig(), and LL_RCC_GetRTCClockFreq().

__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC ( void )

Check if RTC has been enabled or not.

Reference Manual to LL API cross reference:
BDCR RTCEN LL_RCC_IsEnabledRTC
Return values:
State of bit (1 or 0).

Definition at line 2871 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset ( void )

Release the Backup domain reset.

Reference Manual to LL API cross reference:
BDCR BDRST LL_RCC_ReleaseBackupDomainReset
Return values:
None

Definition at line 2891 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

__STATIC_INLINE void LL_RCC_SetRTCClockSource ( uint32_t Source )

Set RTC Clock Source.

Note:
Once the RTC clock source has been selected, it cannot be changed anymore unless the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset them.
Reference Manual to LL API cross reference:
BDCR RTCSEL LL_RCC_SetRTCClockSource
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_RTC_CLKSOURCE_NONE
  • LL_RCC_RTC_CLKSOURCE_LSE
  • LL_RCC_RTC_CLKSOURCE_LSI
  • LL_RCC_RTC_CLKSOURCE_HSE_DIV32
Return values:
None

Definition at line 2827 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PLL

Functions
PLL
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_PLL_Enable (void)
Enable PLL.
__STATIC_INLINE void | LL_RCC_PLL_Disable (void)
Disable PLL.
__STATIC_INLINE uint32_t | LL_RCC_PLL_IsReady (void)
Check if PLL Ready.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_SYS (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
Configure PLL used for SYSCLK Domain.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_SAI (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
Configure PLL used for SAI domain clock.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_ADC (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
Configure PLL used for ADC domain clock.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_48M (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
Configure PLL used for 48Mhz domain clock.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetN (void)
Get Main PLL multiplication factor for VCO.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetP (void)
Get Main PLL division factor for PLLP.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetQ (void)
Get Main PLL division factor for PLLQ.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetR (void)
Get Main PLL division factor for PLLR.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetDivider (void)
Get Division factor for the main PLL and other PLL.
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_SAI (void)
Enable PLL output mapped on SAI domain clock.
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_SAI (void)
Disable PLL output mapped on SAI domain clock.
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_ADC (void)
Enable PLL output mapped on ADC domain clock.
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_ADC (void)
Disable PLL output mapped on ADC domain clock.
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_48M (void)
Enable PLL output mapped on 48MHz domain clock.
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_48M (void)
Disable PLL output mapped on 48MHz domain clock.
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_SYS (void)
Enable PLL output mapped on SYSCLK domain.
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_SYS (void)
Disable PLL output mapped on SYSCLK domain.

Function Documentation

__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M | ( | uint32_t | Source,
 |  | uint32_t | PLLM,
 |  | uint32_t | PLLN,
 |  | uint32_t | PLLQ
 | ) |  |

Configure PLL used for 48Mhz domain clock.

Note:
PLL Source and PLLM Divider can be written only when PLL is disabled PLLSAI1 are disabled
PLLN/PLLQ can be written only when PLL is disabled
This can be selected for USB, RNG
Reference Manual to LL API cross reference:
PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M
PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M
PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M
PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_MSI
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
PLLM This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
PLLN Between 6 and 127
PLLQ This parameter can be one of the following values:
  • LL_RCC_PLLQ_DIV_2
  • LL_RCC_PLLQ_DIV_3
  • LL_RCC_PLLQ_DIV_4
  • LL_RCC_PLLQ_DIV_5
  • LL_RCC_PLLQ_DIV_6
  • LL_RCC_PLLQ_DIV_7
  • LL_RCC_PLLQ_DIV_8
Return values:
None

Definition at line 3138 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_ADC | ( | uint32_t | Source,
 |  | uint32_t | PLLM,
 |  | uint32_t | PLLN,
 |  | uint32_t | PLLP
 | ) |  |

Configure PLL used for ADC domain clock.

Note:
PLL Source and PLLM Divider can be written only when PLL is disabled PLLSAI1 are disabled
PLLN/PLLP can be written only when PLL is disabled
Reference Manual to LL API cross reference:
PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_ADC
PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_ADC
PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_ADC
PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_ADC
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_MSI
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
PLLM This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
PLLN Between 6 and 127
PLLP This parameter can be one of the following values:
  • LL_RCC_PLLP_DIV_2
  • LL_RCC_PLLP_DIV_3
  • LL_RCC_PLLP_DIV_4
  • LL_RCC_PLLP_DIV_5
  • LL_RCC_PLLP_DIV_6
  • LL_RCC_PLLP_DIV_7
  • LL_RCC_PLLP_DIV_8
  • LL_RCC_PLLP_DIV_9
  • LL_RCC_PLLP_DIV_10
  • LL_RCC_PLLP_DIV_11
  • LL_RCC_PLLP_DIV_12
  • LL_RCC_PLLP_DIV_13
  • LL_RCC_PLLP_DIV_14
  • LL_RCC_PLLP_DIV_15
  • LL_RCC_PLLP_DIV_16
  • LL_RCC_PLLP_DIV_17
  • LL_RCC_PLLP_DIV_18
  • LL_RCC_PLLP_DIV_19
  • LL_RCC_PLLP_DIV_20
  • LL_RCC_PLLP_DIV_21
  • LL_RCC_PLLP_DIV_22
  • LL_RCC_PLLP_DIV_23
  • LL_RCC_PLLP_DIV_24
  • LL_RCC_PLLP_DIV_25
  • LL_RCC_PLLP_DIV_26
  • LL_RCC_PLLP_DIV_27
  • LL_RCC_PLLP_DIV_28
  • LL_RCC_PLLP_DIV_29
  • LL_RCC_PLLP_DIV_30
  • LL_RCC_PLLP_DIV_31
  • LL_RCC_PLLP_DIV_32
Return values:
None

Definition at line 3097 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI | ( | uint32_t | Source,
 |  | uint32_t | PLLM,
 |  | uint32_t | PLLN,
 |  | uint32_t | PLLP
 | ) |  |

Configure PLL used for SAI domain clock.

Note:
PLL Source and PLLM Divider can be written only when PLL is disabled PLLSAI1 are disabled
PLLN/PLLP can be written only when PLL is disabled
Reference Manual to LL API cross reference:
PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI
PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI
PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI
PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SAI
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_MSI
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
PLLM This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
PLLN Between 6 and 127
PLLP This parameter can be one of the following values:
  • LL_RCC_PLLP_DIV_2
  • LL_RCC_PLLP_DIV_3
  • LL_RCC_PLLP_DIV_4
  • LL_RCC_PLLP_DIV_5
  • LL_RCC_PLLP_DIV_6
  • LL_RCC_PLLP_DIV_7
  • LL_RCC_PLLP_DIV_8
  • LL_RCC_PLLP_DIV_9
  • LL_RCC_PLLP_DIV_10
  • LL_RCC_PLLP_DIV_11
  • LL_RCC_PLLP_DIV_12
  • LL_RCC_PLLP_DIV_13
  • LL_RCC_PLLP_DIV_14
  • LL_RCC_PLLP_DIV_15
  • LL_RCC_PLLP_DIV_16
  • LL_RCC_PLLP_DIV_17
  • LL_RCC_PLLP_DIV_18
  • LL_RCC_PLLP_DIV_19
  • LL_RCC_PLLP_DIV_20
  • LL_RCC_PLLP_DIV_21
  • LL_RCC_PLLP_DIV_22
  • LL_RCC_PLLP_DIV_23
  • LL_RCC_PLLP_DIV_24
  • LL_RCC_PLLP_DIV_25
  • LL_RCC_PLLP_DIV_26
  • LL_RCC_PLLP_DIV_27
  • LL_RCC_PLLP_DIV_28
  • LL_RCC_PLLP_DIV_29
  • LL_RCC_PLLP_DIV_30
  • LL_RCC_PLLP_DIV_31
  • LL_RCC_PLLP_DIV_32
Return values:
None

Definition at line 3032 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS | ( | uint32_t | Source,
 |  | uint32_t | PLLM,
 |  | uint32_t | PLLN,
 |  | uint32_t | PLLR
 | ) |  |

Configure PLL used for SYSCLK Domain.

Note:
PLL Source and PLLM Divider can be written only when PLL is disabled PLLSAI1 are disabled
PLLN/PLLR can be written only when PLL is disabled
Reference Manual to LL API cross reference:
PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS
PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS
PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS
PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_MSI
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
PLLM This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
PLLN Between 6 and 127
PLLR This parameter can be one of the following values:
  • LL_RCC_PLLR_DIV_2
  • LL_RCC_PLLR_DIV_4
  • LL_RCC_PLLR_DIV_6
  • LL_RCC_PLLR_DIV_8
Return values:
None

Definition at line 2967 of file stm32wbxx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), and LL_PLL_ConfigSystemClock_MSI().

__STATIC_INLINE void LL_RCC_PLL_Disable ( void )

Disable PLL.

Note:
Cannot be disabled if the PLL clock is used as the system clock
Reference Manual to LL API cross reference:
CR PLLON LL_RCC_PLL_Disable
Return values:
None

Definition at line 2921 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_DisableDomain_48M ( void )

Disable PLL output mapped on 48MHz domain clock.

Note:
In order to save power, when the PLLCLK of the PLL is not used, should be 0
Reference Manual to LL API cross reference:
PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_48M
Return values:
None

Definition at line 3314 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_DisableDomain_ADC ( void )

Disable PLL output mapped on ADC domain clock.

Note:
In order to save power, when the PLLCLK of the PLL is not used, should be 0
Reference Manual to LL API cross reference:
PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_ADC
Return values:
None

Definition at line 3291 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SAI ( void )

Disable PLL output mapped on SAI domain clock.

Note:
In order to save power, when the PLLCLK of the PLL is not used, should be 0
Reference Manual to LL API cross reference:
PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_SAI
Return values:
None

Definition at line 3268 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS ( void )

Disable PLL output mapped on SYSCLK domain.

Note:
Cannot be disabled if the PLL clock is used as the system clock
In order to save power, when the PLLCLK of the PLL is not used, Main PLL should be 0
Reference Manual to LL API cross reference:
PLLCFGR PLLREN LL_RCC_PLL_DisableDomain_SYS
Return values:
None

Definition at line 3337 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_Enable ( void )

Enable PLL.

Reference Manual to LL API cross reference:
CR PLLON LL_RCC_PLL_Enable
Return values:
None

Definition at line 2910 of file stm32wbxx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE void LL_RCC_PLL_EnableDomain_48M ( void )

Enable PLL output mapped on 48MHz domain clock.

Reference Manual to LL API cross reference:
PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_48M
Return values:
None

Definition at line 3302 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_EnableDomain_ADC ( void )

Enable PLL output mapped on ADC domain clock.

Reference Manual to LL API cross reference:
PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_ADC
Return values:
None

Definition at line 3279 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SAI ( void )

Enable PLL output mapped on SAI domain clock.

Reference Manual to LL API cross reference:
PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_SAI
Return values:
None

Definition at line 3256 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS ( void )

Enable PLL output mapped on SYSCLK domain.

Reference Manual to LL API cross reference:
PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS
Return values:
None

Definition at line 3324 of file stm32wbxx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider ( void )

Get Division factor for the main PLL and other PLL.

Reference Manual to LL API cross reference:
PLLCFGR PLLM LL_RCC_PLL_GetDivider
Return values:
Returned value can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8

Definition at line 3245 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), HAL_RCC_GetSysClockFreq(), RCC_PLL_GetFreqDomain_48M(), RCC_PLL_GetFreqDomain_ADC(), RCC_PLL_GetFreqDomain_P(), RCC_PLL_GetFreqDomain_Q(), RCC_PLL_GetFreqDomain_SAI(), RCC_PLL_GetFreqDomain_SYS(), RCC_PLLSAI1_GetFreqDomain_48M(), RCC_PLLSAI1_GetFreqDomain_ADC(), RCC_PLLSAI1_GetFreqDomain_P(), RCC_PLLSAI1_GetFreqDomain_Q(), RCC_PLLSAI1_GetFreqDomain_R(), and RCC_PLLSAI1_GetFreqDomain_SAI().

__STATIC_INLINE uint32_t LL_RCC_PLL_GetN ( void )

Get Main PLL multiplication factor for VCO.

Reference Manual to LL API cross reference:
PLLCFGR PLLN LL_RCC_PLL_GetN
Return values:
Between 6 and 127

Definition at line 3149 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), HAL_RCC_GetSysClockFreq(), RCC_PLL_GetFreqDomain_48M(), RCC_PLL_GetFreqDomain_ADC(), RCC_PLL_GetFreqDomain_P(), RCC_PLL_GetFreqDomain_Q(), RCC_PLL_GetFreqDomain_SAI(), and RCC_PLL_GetFreqDomain_SYS().

__STATIC_INLINE uint32_t LL_RCC_PLL_GetP ( void )

Get Main PLL division factor for PLLP.

Note:
used for PLLSAI1CLK (SAI1 clock)
Reference Manual to LL API cross reference:
PLLCFGR PLLP LL_RCC_PLL_GetP
Return values:
Returned value can be one of the following values:
  • LL_RCC_PLLP_DIV_2
  • LL_RCC_PLLP_DIV_3
  • LL_RCC_PLLP_DIV_4
  • LL_RCC_PLLP_DIV_5
  • LL_RCC_PLLP_DIV_6
  • LL_RCC_PLLP_DIV_7
  • LL_RCC_PLLP_DIV_8
  • LL_RCC_PLLP_DIV_9
  • LL_RCC_PLLP_DIV_10
  • LL_RCC_PLLP_DIV_11
  • LL_RCC_PLLP_DIV_12
  • LL_RCC_PLLP_DIV_13
  • LL_RCC_PLLP_DIV_14
  • LL_RCC_PLLP_DIV_15
  • LL_RCC_PLLP_DIV_16
  • LL_RCC_PLLP_DIV_17
  • LL_RCC_PLLP_DIV_18
  • LL_RCC_PLLP_DIV_19
  • LL_RCC_PLLP_DIV_20
  • LL_RCC_PLLP_DIV_21
  • LL_RCC_PLLP_DIV_22
  • LL_RCC_PLLP_DIV_23
  • LL_RCC_PLLP_DIV_24
  • LL_RCC_PLLP_DIV_25
  • LL_RCC_PLLP_DIV_26
  • LL_RCC_PLLP_DIV_27
  • LL_RCC_PLLP_DIV_28
  • LL_RCC_PLLP_DIV_29
  • LL_RCC_PLLP_DIV_30
  • LL_RCC_PLLP_DIV_31
  • LL_RCC_PLLP_DIV_32

Definition at line 3191 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), RCC_PLL_GetFreqDomain_ADC(), RCC_PLL_GetFreqDomain_P(), and RCC_PLL_GetFreqDomain_SAI().

__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ ( void )

Get Main PLL division factor for PLLQ.

Note:
used for PLL48MCLK selected for USB, RNG (48 MHz clock)
Reference Manual to LL API cross reference:
PLLCFGR PLLQ LL_RCC_PLL_GetQ
Return values:
Returned value can be one of the following values:
  • LL_RCC_PLLQ_DIV_2
  • LL_RCC_PLLQ_DIV_3
  • LL_RCC_PLLQ_DIV_4
  • LL_RCC_PLLQ_DIV_5
  • LL_RCC_PLLQ_DIV_6
  • LL_RCC_PLLQ_DIV_7
  • LL_RCC_PLLQ_DIV_8

Definition at line 3209 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), RCC_PLL_GetFreqDomain_48M(), and RCC_PLL_GetFreqDomain_Q().

__STATIC_INLINE uint32_t LL_RCC_PLL_GetR ( void )

Get Main PLL division factor for PLLR.

Note:
used for PLLCLK (system clock)
Reference Manual to LL API cross reference:
PLLCFGR PLLR LL_RCC_PLL_GetR
Return values:
Returned value can be one of the following values:
  • LL_RCC_PLLR_DIV_2
  • LL_RCC_PLLR_DIV_3
  • LL_RCC_PLLR_DIV_4
  • LL_RCC_PLLR_DIV_5
  • LL_RCC_PLLR_DIV_6
  • LL_RCC_PLLR_DIV_7
  • LL_RCC_PLLR_DIV_8

Definition at line 3227 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), HAL_RCC_GetSysClockFreq(), and RCC_PLL_GetFreqDomain_SYS().

__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady ( void )

Check if PLL Ready.

Reference Manual to LL API cross reference:
CR PLLRDY LL_RCC_PLL_IsReady
Return values:
State of bit (1 or 0).

Definition at line 2931 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_ClockConfig(), HAL_RCC_DeInit(), HAL_RCC_OscConfig(), HAL_RCCEx_GetPeriphCLKFreq(), LL_RCC_DeInit(), LL_RCC_GetADCClockFreq(), LL_RCC_GetCLK48ClockFreq(), LL_RCC_GetSAIClockFreq(), UTILS_EnablePLLAndSwitchSystem(), and UTILS_PLL_IsBusy().

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PLLSAI1

Functions
PLLSAI1
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_PLLSAI1_Enable (void)
Enable PLLSAI1.
__STATIC_INLINE void | LL_RCC_PLLSAI1_Disable (void)
Disable PLLSAI1.
__STATIC_INLINE uint32_t | LL_RCC_PLLSAI1_IsReady (void)
Check if PLLSAI1 Ready.
__STATIC_INLINE void | LL_RCC_PLLSAI1_ConfigDomain_48M (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
Configure PLLSAI1 used for 48Mhz domain clock.
__STATIC_INLINE void | LL_RCC_PLLSAI1_ConfigDomain_SAI (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
Configure PLLSAI1 used for SAI domain clock.
__STATIC_INLINE void | LL_RCC_PLLSAI1_ConfigDomain_ADC (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
Configure PLLSAI1 used for ADC domain clock.
__STATIC_INLINE uint32_t | LL_RCC_PLLSAI1_GetN (void)
Get SAI1PLL multiplication factor for VCO.
__STATIC_INLINE uint32_t | LL_RCC_PLLSAI1_GetP (void)
Get SAI1PLL division factor for PLLSAI1P.
__STATIC_INLINE uint32_t | LL_RCC_PLLSAI1_GetQ (void)
Get SAI1PLL division factor for PLLQ.
__STATIC_INLINE uint32_t | LL_RCC_PLLSAI1_GetR (void)
Get PLLSAI1 division factor for PLLSAIR.
__STATIC_INLINE void | LL_RCC_PLLSAI1_EnableDomain_SAI (void)
Enable PLLSAI1 output mapped on SAI domain clock.
__STATIC_INLINE void | LL_RCC_PLLSAI1_DisableDomain_SAI (void)
Disable PLLSAI1 output mapped on SAI domain clock.
__STATIC_INLINE void | LL_RCC_PLLSAI1_EnableDomain_48M (void)
Enable PLLSAI1 output mapped on 48MHz domain clock.
__STATIC_INLINE void | LL_RCC_PLLSAI1_DisableDomain_48M (void)
Disable PLLSAI1 output mapped on 48MHz domain clock.
__STATIC_INLINE void | LL_RCC_PLLSAI1_EnableDomain_ADC (void)
Enable PLLSAI1 output mapped on ADC domain clock.
__STATIC_INLINE void | LL_RCC_PLLSAI1_DisableDomain_ADC (void)
Disable PLLSAI1 output mapped on ADC domain clock.

Function Documentation

__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M | ( | uint32_t | Source,
 |  | uint32_t | PLLM,
 |  | uint32_t | PLLN,
 |  | uint32_t | PLLQ
 | ) |  |

Configure PLLSAI1 used for 48Mhz domain clock.

Note:
PLL Source and PLLM Divider can be written only when PLL is disabled PLLSAI1 are disabled
PLLN/PLLQ can be written only when PLLSAI1 is disabled
This can be selected for USB, RNG
Reference Manual to LL API cross reference:
PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_48M
PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_48M
PLLSAI1CFGR PLLN LL_RCC_PLLSAI1_ConfigDomain_48M
PLLSAI1CFGR PLLQ LL_RCC_PLLSAI1_ConfigDomain_48M
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_MSI
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
PLLM This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
PLLN Between 6 and 127
PLLQ This parameter can be one of the following values:
  • LL_RCC_PLLSAI1Q_DIV_2
  • LL_RCC_PLLSAI1Q_DIV_3
  • LL_RCC_PLLSAI1Q_DIV_4
  • LL_RCC_PLLSAI1Q_DIV_5
  • LL_RCC_PLLSAI1Q_DIV_6
  • LL_RCC_PLLSAI1Q_DIV_7
  • LL_RCC_PLLSAI1Q_DIV_8
Return values:
None

Definition at line 3416 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC | ( | uint32_t | Source,
 |  | uint32_t | PLLM,
 |  | uint32_t | PLLN,
 |  | uint32_t | PLLR
 | ) |  |

Configure PLLSAI1 used for ADC domain clock.

Note:
PLL Source and PLLM Divider can be written only when PLL is disabled PLLSAI1 are disabled
PLLN/PLLR can be written only when PLLSAI1 is disabled
This can be selected for ADC
Reference Manual to LL API cross reference:
PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_ADC
PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_ADC
PLLSAI1CFGR PLLN LL_RCC_PLLSAI1_ConfigDomain_ADC
PLLSAI1CFGR PLLR LL_RCC_PLLSAI1_ConfigDomain_ADC
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_MSI
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
PLLM This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
PLLN Between 6 and 127
PLLR This parameter can be one of the following values:
  • LL_RCC_PLLSAI1R_DIV_2
  • LL_RCC_PLLSAI1R_DIV_3
  • LL_RCC_PLLSAI1R_DIV_4
  • LL_RCC_PLLSAI1R_DIV_5
  • LL_RCC_PLLSAI1R_DIV_6
  • LL_RCC_PLLSAI1R_DIV_7
  • LL_RCC_PLLSAI1R_DIV_8
Return values:
None

Definition at line 3523 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI | ( | uint32_t | Source,
 |  | uint32_t | PLLM,
 |  | uint32_t | PLLN,
 |  | uint32_t | PLLP
 | ) |  |

Configure PLLSAI1 used for SAI domain clock.

Note:
PLL Source and PLLM Divider can be written only when PLL is disabled PLLSAI1 are disabled
PLLN/PLLP can be written only when PLLSAI1 is disabled
This can be selected for SAI1 or SAI2 (*)
Reference Manual to LL API cross reference:
PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI
PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI
PLLSAI1CFGR PLLN LL_RCC_PLLSAI1_ConfigDomain_SAI
PLLSAI1CFGR PLLP LL_RCC_PLLSAI1_ConfigDomain_SAI
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_MSI
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
PLLM This parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
PLLN Between 6 and 127
PLLP This parameter can be one of the following values:
  • LL_RCC_PLLSAI1P_DIV_2
  • LL_RCC_PLLSAI1P_DIV_3
  • LL_RCC_PLLSAI1P_DIV_4
  • LL_RCC_PLLSAI1P_DIV_5
  • LL_RCC_PLLSAI1P_DIV_6
  • LL_RCC_PLLSAI1P_DIV_7
  • LL_RCC_PLLSAI1P_DIV_8
  • LL_RCC_PLLSAI1P_DIV_9
  • LL_RCC_PLLSAI1P_DIV_10
  • LL_RCC_PLLSAI1P_DIV_11
  • LL_RCC_PLLSAI1P_DIV_12
  • LL_RCC_PLLSAI1P_DIV_13
  • LL_RCC_PLLSAI1P_DIV_14
  • LL_RCC_PLLSAI1P_DIV_15
  • LL_RCC_PLLSAI1P_DIV_16
  • LL_RCC_PLLSAI1P_DIV_17
  • LL_RCC_PLLSAI1P_DIV_18
  • LL_RCC_PLLSAI1P_DIV_19
  • LL_RCC_PLLSAI1P_DIV_20
  • LL_RCC_PLLSAI1P_DIV_21
  • LL_RCC_PLLSAI1P_DIV_22
  • LL_RCC_PLLSAI1P_DIV_23
  • LL_RCC_PLLSAI1P_DIV_24
  • LL_RCC_PLLSAI1P_DIV_25
  • LL_RCC_PLLSAI1P_DIV_26
  • LL_RCC_PLLSAI1P_DIV_27
  • LL_RCC_PLLSAI1P_DIV_28
  • LL_RCC_PLLSAI1P_DIV_29
  • LL_RCC_PLLSAI1P_DIV_30
  • LL_RCC_PLLSAI1P_DIV_31
  • LL_RCC_PLLSAI1P_DIV_32
Return values:
None

Definition at line 3481 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI1_Disable ( void )

Disable PLLSAI1.

Reference Manual to LL API cross reference:
CR PLLSAI1ON LL_RCC_PLLSAI1_Disable
Return values:
None

Definition at line 3366 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_48M ( void )

Disable PLLSAI1 output mapped on 48MHz domain clock.

Note:
In order to save power, when of the PLLSAI1 is not used, should be 0
Reference Manual to LL API cross reference:
PLLSAI1CFGR PLLQEN LL_RCC_PLLSAI1_DisableDomain_48M
Return values:
None

Definition at line 3657 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_ADC ( void )

Disable PLLSAI1 output mapped on ADC domain clock.

Note:
In order to save power, when of the PLLSAI1 is not used, Main PLLSAI1 should be 0
Reference Manual to LL API cross reference:
PLLSAI1CFGR PLLREN LL_RCC_PLLSAI1_DisableDomain_ADC
Return values:
None

Definition at line 3679 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_SAI ( void )

Disable PLLSAI1 output mapped on SAI domain clock.

Note:
In order to save power, when of the PLLSAI1 is not used, should be 0
Reference Manual to LL API cross reference:
PLLSAI1CFGR PLLPEN LL_RCC_PLLSAI1_DisableDomain_SAI
Return values:
None

Definition at line 3635 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI1_Enable ( void )

Enable PLLSAI1.

Reference Manual to LL API cross reference:
CR PLLSAI1ON LL_RCC_PLLSAI1_Enable
Return values:
None

Definition at line 3356 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_48M ( void )

Enable PLLSAI1 output mapped on 48MHz domain clock.

Reference Manual to LL API cross reference:
PLLSAI1CFGR PLLQEN LL_RCC_PLLSAI1_EnableDomain_48M
Return values:
None

Definition at line 3645 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_ADC ( void )

Enable PLLSAI1 output mapped on ADC domain clock.

Reference Manual to LL API cross reference:
PLLSAI1CFGR PLLREN LL_RCC_PLLSAI1_EnableDomain_ADC
Return values:
None

Definition at line 3667 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_SAI ( void )

Enable PLLSAI1 output mapped on SAI domain clock.

Reference Manual to LL API cross reference:
PLLSAI1CFGR PLLPEN LL_RCC_PLLSAI1_EnableDomain_SAI
Return values:
None

Definition at line 3623 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetN ( void )

Get SAI1PLL multiplication factor for VCO.

Reference Manual to LL API cross reference:
PLLSAI1CFGR PLLN LL_RCC_PLLSAI1_GetN
Return values:
Between 6 and 127

Definition at line 3534 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), RCC_PLLSAI1_GetFreqDomain_48M(), RCC_PLLSAI1_GetFreqDomain_ADC(), RCC_PLLSAI1_GetFreqDomain_P(), RCC_PLLSAI1_GetFreqDomain_Q(), RCC_PLLSAI1_GetFreqDomain_R(), and RCC_PLLSAI1_GetFreqDomain_SAI().

__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP ( void )

Get SAI1PLL division factor for PLLSAI1P.

Note:
used for PLLSAI1CLK (SAI1 or SAI2 (*) clock).
Reference Manual to LL API cross reference:
PLLSAI1CFGR PLLP LL_RCC_PLLSAI1_GetP
Return values:
Returned value can be one of the following values:
  • LL_RCC_PLLSAI1P_DIV_2
  • LL_RCC_PLLSAI1P_DIV_3
  • LL_RCC_PLLSAI1P_DIV_4
  • LL_RCC_PLLSAI1P_DIV_5
  • LL_RCC_PLLSAI1P_DIV_6
  • LL_RCC_PLLSAI1P_DIV_7
  • LL_RCC_PLLSAI1P_DIV_8
  • LL_RCC_PLLSAI1P_DIV_9
  • LL_RCC_PLLSAI1P_DIV_10
  • LL_RCC_PLLSAI1P_DIV_11
  • LL_RCC_PLLSAI1P_DIV_12
  • LL_RCC_PLLSAI1P_DIV_13
  • LL_RCC_PLLSAI1P_DIV_14
  • LL_RCC_PLLSAI1P_DIV_15
  • LL_RCC_PLLSAI1P_DIV_16
  • LL_RCC_PLLSAI1P_DIV_17
  • LL_RCC_PLLSAI1P_DIV_18
  • LL_RCC_PLLSAI1P_DIV_19
  • LL_RCC_PLLSAI1P_DIV_20
  • LL_RCC_PLLSAI1P_DIV_21
  • LL_RCC_PLLSAI1P_DIV_22
  • LL_RCC_PLLSAI1P_DIV_23
  • LL_RCC_PLLSAI1P_DIV_24
  • LL_RCC_PLLSAI1P_DIV_25
  • LL_RCC_PLLSAI1P_DIV_26
  • LL_RCC_PLLSAI1P_DIV_27
  • LL_RCC_PLLSAI1P_DIV_28
  • LL_RCC_PLLSAI1P_DIV_29
  • LL_RCC_PLLSAI1P_DIV_30
  • LL_RCC_PLLSAI1P_DIV_31
  • LL_RCC_PLLSAI1P_DIV_32

Definition at line 3576 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), RCC_PLLSAI1_GetFreqDomain_P(), and RCC_PLLSAI1_GetFreqDomain_SAI().

__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetQ ( void )

Get SAI1PLL division factor for PLLQ.

Note:
used PLL48M2CLK selected for USB, RNG (48 MHz clock)
Reference Manual to LL API cross reference:
PLLSAI1CFGR PLLQ LL_RCC_PLLSAI1_GetQ
Return values:
Returned value can be one of the following values:
  • LL_RCC_PLLSAI1Q_DIV_2
  • LL_RCC_PLLSAI1Q_DIV_3
  • LL_RCC_PLLSAI1Q_DIV_4
  • LL_RCC_PLLSAI1Q_DIV_5
  • LL_RCC_PLLSAI1Q_DIV_6
  • LL_RCC_PLLSAI1Q_DIV_7
  • LL_RCC_PLLSAI1Q_DIV_8

Definition at line 3594 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), RCC_PLLSAI1_GetFreqDomain_48M(), and RCC_PLLSAI1_GetFreqDomain_Q().

__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetR ( void )

Get PLLSAI1 division factor for PLLSAIR.

Note:
used for PLLADC1CLK (ADC clock)
Reference Manual to LL API cross reference:
PLLSAI1CFGR PLLR LL_RCC_PLLSAI1_GetR
Return values:
Returned value can be one of the following values:
  • LL_RCC_PLLSAI1R_DIV_2
  • LL_RCC_PLLSAI1R_DIV_3
  • LL_RCC_PLLSAI1R_DIV_4
  • LL_RCC_PLLSAI1R_DIV_5
  • LL_RCC_PLLSAI1R_DIV_6
  • LL_RCC_PLLSAI1R_DIV_7
  • LL_RCC_PLLSAI1R_DIV_8

Definition at line 3612 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), RCC_PLLSAI1_GetFreqDomain_ADC(), and RCC_PLLSAI1_GetFreqDomain_R().

__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsReady ( void )

Check if PLLSAI1 Ready.

Reference Manual to LL API cross reference:
CR PLLSAI1RDY LL_RCC_PLLSAI1_IsReady
Return values:
State of bit (1 or 0).

Definition at line 3376 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_DeInit(), HAL_RCCEx_DisablePLLSAI1(), HAL_RCCEx_EnablePLLSAI1(), HAL_RCCEx_GetPeriphCLKFreq(), LL_RCC_DeInit(), LL_RCC_GetADCClockFreq(), LL_RCC_GetCLK48ClockFreq(), LL_RCC_GetSAIClockFreq(), RCCEx_PLLSAI1_ConfigNP(), RCCEx_PLLSAI1_ConfigNQ(), RCCEx_PLLSAI1_ConfigNR(), and UTILS_PLL_IsBusy().

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FLAG Management

Functions
FLAG Management
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_ClearFlag_LSI1RDY (void)
Clear LSI1 ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_LSI2RDY (void)
Clear LSI2 ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_LSERDY (void)
Clear LSE ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_MSIRDY (void)
Clear MSI ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSIRDY (void)
Clear HSI ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSERDY (void)
Clear HSE ready interrupt flag.
__STATIC_INLINE void | LL_RCC_PLL_SetMainSource (uint32_t PLLSource)
Configure PLL clock source.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetMainSource (void)
Get the oscillator used as PLL clock source.
__STATIC_INLINE void | LL_RCC_ClearFlag_PLLRDY (void)
Clear PLL ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSI48RDY (void)
Clear HSI48 ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_PLLSAI1RDY (void)
Clear PLLSAI1 ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSECSS (void)
Clear Clock security system interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_LSECSS (void)
Clear LSE Clock security system interrupt flag.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSI1RDY (void)
Check if LSI1 ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSI2RDY (void)
Check if LSI2 ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSERDY (void)
Check if LSE ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_MSIRDY (void)
Check if MSI ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSIRDY (void)
Check if HSI ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSERDY (void)
Check if HSE ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PLLRDY (void)
Check if PLL ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSI48RDY (void)
Check if HSI48 ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PLLSAI1RDY (void)
Check if PLLSAI1 ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSECSS (void)
Check if Clock security system interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSECSS (void)
Check if LSE Clock security system interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HPRE (void)
Check if HCLK1 prescaler flag value has been applied or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_C2HPRE (void)
Check if HCLK2 prescaler flag value has been applied or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_SHDHPRE (void)
Check if HCLK4 prescaler flag value has been applied or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PPRE1 (void)
Check if PLCK1 prescaler flag value has been applied or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PPRE2 (void)
Check if PLCK2 prescaler flag value has been applied or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_IWDGRST (void)
Check if RCC flag Independent Watchdog reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LPWRRST (void)
Check if RCC flag Low Power reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_OBLRST (void)
Check if RCC flag Option byte reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PINRST (void)
Check if RCC flag Pin reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_SFTRST (void)
Check if RCC flag Software reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_WWDGRST (void)
Check if RCC flag Window Watchdog reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_BORRST (void)
Check if RCC flag BOR reset is set or not.
__STATIC_INLINE void | LL_RCC_ClearResetFlags (void)
Set RMVF bit to clear the reset flags.

Function Documentation

__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS ( void )

Clear Clock security system interrupt flag.

Reference Manual to LL API cross reference:
CICR CSSC LL_RCC_ClearFlag_HSECSS
Return values:
None

Definition at line 3820 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY ( void )

Clear HSE ready interrupt flag.

Reference Manual to LL API cross reference:
CICR HSERDYC LL_RCC_ClearFlag_HSERDY
Return values:
None

Definition at line 3750 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY ( void )

Clear HSI48 ready interrupt flag.

Reference Manual to LL API cross reference:
CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
Return values:
None

Definition at line 3798 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY ( void )

Clear HSI ready interrupt flag.

Reference Manual to LL API cross reference:
CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
Return values:
None

Definition at line 3740 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS ( void )

Clear LSE Clock security system interrupt flag.

Reference Manual to LL API cross reference:
CICR LSECSSC LL_RCC_ClearFlag_LSECSS
Return values:
None

Definition at line 3830 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY ( void )

Clear LSE ready interrupt flag.

Reference Manual to LL API cross reference:
CICR LSERDYC LL_RCC_ClearFlag_LSERDY
Return values:
None

Definition at line 3720 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_LSI1RDY ( void )

Clear LSI1 ready interrupt flag.

Reference Manual to LL API cross reference:
CICR LSI1RDYC LL_RCC_ClearFlag_LSI1RDY
Return values:
None

Definition at line 3700 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_LSI2RDY ( void )

Clear LSI2 ready interrupt flag.

Reference Manual to LL API cross reference:
CICR LSI2RDYC LL_RCC_ClearFlag_LSI2RDY
Return values:
None

Definition at line 3710 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY ( void )

Clear MSI ready interrupt flag.

Reference Manual to LL API cross reference:
CICR MSIRDYC LL_RCC_ClearFlag_MSIRDY
Return values:
None

Definition at line 3730 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY ( void )

Clear PLL ready interrupt flag.

Reference Manual to LL API cross reference:
CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY
Return values:
None

Definition at line 3788 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI1RDY ( void )

Clear PLLSAI1 ready interrupt flag.

Reference Manual to LL API cross reference:
CICR PLLSAI1RDYC LL_RCC_ClearFlag_PLLSAI1RDY
Return values:
None

Definition at line 3809 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearResetFlags ( void )

Set RMVF bit to clear the reset flags.

Reference Manual to LL API cross reference:
CSR RMVF LL_RCC_ClearResetFlags
Return values:
None

Definition at line 4073 of file stm32wbxx_ll_rcc.h.

Referenced by LL_RCC_DeInit().

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST ( void )

Check if RCC flag BOR reset is set or not.

Reference Manual to LL API cross reference:
CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
Return values:
State of bit (1 or 0).

Definition at line 4063 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_C2HPRE ( void )

Check if HCLK2 prescaler flag value has been applied or not.

Reference Manual to LL API cross reference:
EXTCFGR C2HPREF LL_RCC_IsActiveFlag_C2HPRE
Return values:
State of bit (1 or 0).

Definition at line 3962 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_ClockConfig().

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HPRE ( void )

Check if HCLK1 prescaler flag value has been applied or not.

Reference Manual to LL API cross reference:
CFGR HPREF LL_RCC_IsActiveFlag_HPRE
Return values:
State of bit (1 or 0).

Definition at line 3952 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_ClockConfig().

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS ( void )

Check if Clock security system interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR CSSF LL_RCC_IsActiveFlag_HSECSS
Return values:
State of bit (1 or 0).

Definition at line 3932 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY ( void )

Check if HSE ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
Return values:
State of bit (1 or 0).

Definition at line 3890 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY ( void )

Check if HSI48 ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
Return values:
State of bit (1 or 0).

Definition at line 3910 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY ( void )

Check if HSI ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
Return values:
State of bit (1 or 0).

Definition at line 3880 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST ( void )

Check if RCC flag Independent Watchdog reset is set or not.

Reference Manual to LL API cross reference:
CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
Return values:
State of bit (1 or 0).

Definition at line 4003 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST ( void )

Check if RCC flag Low Power reset is set or not.

Reference Manual to LL API cross reference:
CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
Return values:
State of bit (1 or 0).

Definition at line 4013 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS ( void )

Check if LSE Clock security system interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS
Return values:
State of bit (1 or 0).

Definition at line 3942 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY ( void )

Check if LSE ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
Return values:
State of bit (1 or 0).

Definition at line 3860 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSI1RDY ( void )

Check if LSI1 ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR LSI1RDYF LL_RCC_IsActiveFlag_LSI1RDY
Return values:
State of bit (1 or 0).

Definition at line 3840 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSI2RDY ( void )

Check if LSI2 ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR LSI2RDYF LL_RCC_IsActiveFlag_LSI2RDY
Return values:
State of bit (1 or 0).

Definition at line 3850 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY ( void )

Check if MSI ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR MSIRDYF LL_RCC_IsActiveFlag_MSIRDY
Return values:
State of bit (1 or 0).

Definition at line 3870 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST ( void )

Check if RCC flag Option byte reset is set or not.

Reference Manual to LL API cross reference:
CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
Return values:
State of bit (1 or 0).

Definition at line 4023 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST ( void )

Check if RCC flag Pin reset is set or not.

Reference Manual to LL API cross reference:
CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
Return values:
State of bit (1 or 0).

Definition at line 4033 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY ( void )

Check if PLL ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
Return values:
State of bit (1 or 0).

Definition at line 3900 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI1RDY ( void )

Check if PLLSAI1 ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIFR PLLSAI1RDYF LL_RCC_IsActiveFlag_PLLSAI1RDY
Return values:
State of bit (1 or 0).

Definition at line 3921 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PPRE1 ( void )

Check if PLCK1 prescaler flag value has been applied or not.

Reference Manual to LL API cross reference:
CFGR PPRE1F LL_RCC_IsActiveFlag_PPRE1
Return values:
State of bit (1 or 0).

Definition at line 3983 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_ClockConfig().

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PPRE2 ( void )

Check if PLCK2 prescaler flag value has been applied or not.

Reference Manual to LL API cross reference:
CFGR PPRE2F LL_RCC_IsActiveFlag_PPRE2
Return values:
State of bit (1 or 0).

Definition at line 3993 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_ClockConfig().

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST ( void )

Check if RCC flag Software reset is set or not.

Reference Manual to LL API cross reference:
CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
Return values:
State of bit (1 or 0).

Definition at line 4043 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SHDHPRE ( void )

Check if HCLK4 prescaler flag value has been applied or not.

Reference Manual to LL API cross reference:
EXTCFGR SHDHPREF LL_RCC_IsActiveFlag_SHDHPRE
Return values:
State of bit (1 or 0).

Definition at line 3972 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_ClockConfig().

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST ( void )

Check if RCC flag Window Watchdog reset is set or not.

Reference Manual to LL API cross reference:
CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
Return values:
State of bit (1 or 0).

Definition at line 4053 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource ( void )

Get the oscillator used as PLL clock source.

Reference Manual to LL API cross reference:
PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
Return values:
Returned value can be one of the following values:
  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_MSI
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE

Definition at line 3778 of file stm32wbxx_ll_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), HAL_RCC_GetSysClockFreq(), RCC_PLL_GetFreqDomain_48M(), RCC_PLL_GetFreqDomain_ADC(), RCC_PLL_GetFreqDomain_P(), RCC_PLL_GetFreqDomain_Q(), RCC_PLL_GetFreqDomain_SAI(), RCC_PLL_GetFreqDomain_SYS(), RCC_PLLSAI1_GetFreqDomain_48M(), RCC_PLLSAI1_GetFreqDomain_ADC(), RCC_PLLSAI1_GetFreqDomain_P(), RCC_PLLSAI1_GetFreqDomain_Q(), RCC_PLLSAI1_GetFreqDomain_R(), and RCC_PLLSAI1_GetFreqDomain_SAI().

__STATIC_INLINE void LL_RCC_PLL_SetMainSource ( uint32_t PLLSource )

Configure PLL clock source.

Reference Manual to LL API cross reference:
PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource
Parameters:
PLLSource This parameter can be one of the following values:
  • LL_RCC_PLLSOURCE_MSI
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
Return values:
None

Definition at line 3764 of file stm32wbxx_ll_rcc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IT Management

Functions
IT Management
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_EnableIT_LSI1RDY (void)
Enable LSI1 ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_LSI2RDY (void)
Enable LSI2 ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_LSERDY (void)
Enable LSE ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_MSIRDY (void)
Enable MSI ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_HSIRDY (void)
Enable HSI ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_HSERDY (void)
Enable HSE ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_PLLRDY (void)
Enable PLL ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_HSI48RDY (void)
Enable HSI48 ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_PLLSAI1RDY (void)
Enable PLLSAI1 ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_LSECSS (void)
Enable LSE clock security system interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_LSI1RDY (void)
Disable LSI1 ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_LSI2RDY (void)
Disable LSI2 ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_LSERDY (void)
Disable LSE ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_MSIRDY (void)
Disable MSI ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_HSIRDY (void)
Disable HSI ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_HSERDY (void)
Disable HSE ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_PLLRDY (void)
Disable PLL ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_HSI48RDY (void)
Disable HSI48 ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_PLLSAI1RDY (void)
Disable PLLSAI1 ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_LSECSS (void)
Disable LSE clock security system interrupt.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_LSI1RDY (void)
Checks if LSI1 ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_LSI2RDY (void)
Checks if LSI2 ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_LSERDY (void)
Checks if LSE ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_MSIRDY (void)
Checks if MSI ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_HSIRDY (void)
Checks if HSI ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_HSERDY (void)
Checks if HSE ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_PLLRDY (void)
Checks if PLL ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_HSI48RDY (void)
Checks if HSI48 ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_PLLSAI1RDY (void)
Checks if PLLSAI1 ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_LSECSS (void)
Checks if LSECSS interrupt source is enabled or disabled.

Function Documentation

__STATIC_INLINE void LL_RCC_DisableIT_HSERDY ( void )

Disable HSE ready interrupt.

Reference Manual to LL API cross reference:
CIER HSERDYIE LL_RCC_DisableIT_HSERDY
Return values:
None

Definition at line 4241 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY ( void )

Disable HSI48 ready interrupt.

Reference Manual to LL API cross reference:
CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
Return values:
None

Definition at line 4261 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY ( void )

Disable HSI ready interrupt.

Reference Manual to LL API cross reference:
CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
Return values:
None

Definition at line 4231 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_LSECSS ( void )

Disable LSE clock security system interrupt.

Reference Manual to LL API cross reference:
CIER LSECSSIE LL_RCC_DisableIT_LSECSS
Return values:
None

Definition at line 4283 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_LSERDY ( void )

Disable LSE ready interrupt.

Reference Manual to LL API cross reference:
CIER LSERDYIE LL_RCC_DisableIT_LSERDY
Return values:
None

Definition at line 4211 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_LSI1RDY ( void )

Disable LSI1 ready interrupt.

Reference Manual to LL API cross reference:
CIER LSI1RDYIE LL_RCC_DisableIT_LSI1RDY
Return values:
None

Definition at line 4192 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_LSI2RDY ( void )

Disable LSI2 ready interrupt.

Reference Manual to LL API cross reference:
CIER LSI2RDYIE LL_RCC_DisableIT_LSI2RDY
Return values:
None

Definition at line 4202 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_MSIRDY ( void )

Disable MSI ready interrupt.

Reference Manual to LL API cross reference:
CIER MSIRDYIE LL_RCC_DisableIT_MSIRDY
Return values:
None

Definition at line 4221 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY ( void )

Disable PLL ready interrupt.

Reference Manual to LL API cross reference:
CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY
Return values:
None

Definition at line 4251 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_PLLSAI1RDY ( void )

Disable PLLSAI1 ready interrupt.

Reference Manual to LL API cross reference:
CIER PLLSAI1RDYIE LL_RCC_DisableIT_PLLSAI1RDY
Return values:
None

Definition at line 4272 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_HSERDY ( void )

Enable HSE ready interrupt.

Reference Manual to LL API cross reference:
CIER HSERDYIE LL_RCC_EnableIT_HSERDY
Return values:
None

Definition at line 4140 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY ( void )

Enable HSI48 ready interrupt.

Reference Manual to LL API cross reference:
CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
Return values:
None

Definition at line 4160 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY ( void )

Enable HSI ready interrupt.

Reference Manual to LL API cross reference:
CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
Return values:
None

Definition at line 4130 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_LSECSS ( void )

Enable LSE clock security system interrupt.

Reference Manual to LL API cross reference:
CIER LSECSSIE LL_RCC_EnableIT_LSECSS
Return values:
None

Definition at line 4182 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_LSERDY ( void )

Enable LSE ready interrupt.

Reference Manual to LL API cross reference:
CIER LSERDYIE LL_RCC_EnableIT_LSERDY
Return values:
None

Definition at line 4110 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_LSI1RDY ( void )

Enable LSI1 ready interrupt.

Reference Manual to LL API cross reference:
CIER LSI1RDYIE LL_RCC_EnableIT_LSI1RDY
Return values:
None

Definition at line 4091 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_LSI2RDY ( void )

Enable LSI2 ready interrupt.

Reference Manual to LL API cross reference:
CIER LSI2RDYIE LL_RCC_EnableIT_LSI2RDY
Return values:
None

Definition at line 4101 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_MSIRDY ( void )

Enable MSI ready interrupt.

Reference Manual to LL API cross reference:
CIER MSIRDYIE LL_RCC_EnableIT_MSIRDY
Return values:
None

Definition at line 4120 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY ( void )

Enable PLL ready interrupt.

Reference Manual to LL API cross reference:
CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY
Return values:
None

Definition at line 4150 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_PLLSAI1RDY ( void )

Enable PLLSAI1 ready interrupt.

Reference Manual to LL API cross reference:
CIER PLLSAI1RDYIE LL_RCC_EnableIT_PLLSAI1RDY
Return values:
None

Definition at line 4171 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY ( void )

Checks if HSE ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
Return values:
State of bit (1 or 0).

Definition at line 4342 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY ( void )

Checks if HSI48 ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY
Return values:
State of bit (1 or 0).

Definition at line 4362 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY ( void )

Checks if HSI ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
Return values:
State of bit (1 or 0).

Definition at line 4332 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS ( void )

Checks if LSECSS interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER LSECSSIE LL_RCC_IsEnabledIT_LSECSS
Return values:
State of bit (1 or 0).

Definition at line 4384 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY ( void )

Checks if LSE ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
Return values:
State of bit (1 or 0).

Definition at line 4312 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSI1RDY ( void )

Checks if LSI1 ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER LSI1RDYIE LL_RCC_IsEnabledIT_LSI1RDY
Return values:
State of bit (1 or 0).

Definition at line 4293 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSI2RDY ( void )

Checks if LSI2 ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER LSI2RDYIE LL_RCC_IsEnabledIT_LSI2RDY
Return values:
State of bit (1 or 0).

Definition at line 4303 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY ( void )

Checks if MSI ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY
Return values:
State of bit (1 or 0).

Definition at line 4322 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY ( void )

Checks if PLL ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
Return values:
State of bit (1 or 0).

Definition at line 4352 of file stm32wbxx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI1RDY ( void )

Checks if PLLSAI1 ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIER PLLSAI1RDYIE LL_RCC_IsEnabledIT_PLLSAI1RDY
Return values:
State of bit (1 or 0).

Definition at line 4373 of file stm32wbxx_ll_rcc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: De-initialization function

Functions
De-initialization function
RCC Exported Functions

Functions

ErrorStatus LL_RCC_DeInit (void)
Reset the RCC clock to the default reset state.

Function Documentation

ErrorStatus LL_RCC_DeInit ( void )

Reset the RCC clock to the default reset state.

Note:
The default reset state of the clock configuration is given below:
  • MSI ON and used as system clock source
  • HSE, HSI, HSI48, PLL and PLLSAI1 Source OFF
  • CPU1, CPU2, AHB4, APB1 and APB2 prescaler set to 1.
  • CSS, MCO OFF
  • All interrupts disabled
This function doesn't modify the configuration of the
  • Peripheral clocks
  • LSI, LSE and RTC clocks
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RCC registers are de-initialized
  • ERROR: not applicable

Definition at line 134 of file stm32wbxx_ll_rcc.c.

References HSE_CONTROL_UNLOCK_KEY, LL_RCC_ClearResetFlags(), LL_RCC_GetSysClkSource(), LL_RCC_HSE_CURRENTMAX_3, LL_RCC_HSI48_Disable(), LL_RCC_HSI_SetCalibTrimming(), LL_RCC_MSI_Enable(), LL_RCC_MSI_IsReady(), LL_RCC_MSI_SetCalibTrimming(), LL_RCC_MSI_SetRange(), LL_RCC_MSIRANGE_6, LL_RCC_PLL_IsReady(), LL_RCC_PLLSAI1_IsReady(), LL_RCC_RFWKP_CLKSOURCE_NONE, LL_RCC_SetRFWKPClockSource(), LL_RCC_SYS_CLKSOURCE_STATUS_MSI, and LL_RCC_WriteReg.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Get system and peripherals clocks frequency functions

Functions
Get system and peripherals clocks frequency functions
RCC Exported Functions

Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks and different peripheral clocks available on the device. More...

Functions

void | LL_RCC_GetSystemClocksFreq (LL_RCC_ClocksTypeDef *RCC_Clocks)
Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks.
uint32_t | LL_RCC_GetSMPSClockFreq (void)
Return SMPS clock frequency.
uint32_t | LL_RCC_GetUSARTClockFreq (uint32_t USARTxSource)
Return USARTx clock frequency.
uint32_t | LL_RCC_GetI2CClockFreq (uint32_t I2CxSource)
Return I2Cx clock frequency.
uint32_t | LL_RCC_GetLPUARTClockFreq (uint32_t LPUARTxSource)
Return LPUARTx clock frequency.
uint32_t | LL_RCC_GetLPTIMClockFreq (uint32_t LPTIMxSource)
Return LPTIMx clock frequency.
uint32_t | LL_RCC_GetSAIClockFreq (uint32_t SAIxSource)
Return SAIx clock frequency.
uint32_t | LL_RCC_GetCLK48ClockFreq (uint32_t CLK48xSource)
Return CLK48x clock frequency.
uint32_t | LL_RCC_GetUSBClockFreq (uint32_t USBxSource)
Return USBx clock frequency.
uint32_t | LL_RCC_GetRNGClockFreq (uint32_t RNGxSource)
Return RNGx clock frequency.
uint32_t | LL_RCC_GetADCClockFreq (uint32_t ADCxSource)
Return ADCx clock frequency.
uint32_t | LL_RCC_GetRTCClockFreq (void)
Return RTC & LCD clock frequency.
uint32_t | LL_RCC_GetRFWKPClockFreq (void)
Return RF Wakeup clock frequency.

Detailed Description

Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks and different peripheral clocks available on the device.

Note:
If SYSCLK source is MSI, function returns values based on MSI values(*)
If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
If SYSCLK source is PLL, function returns values based on HSE_VALUE(***) or HSI_VALUE(**) or MSI values(*) multiplied/divided by the PLL factors.
(*) MSI values are retrieved thanks to __LL_RCC_CALC_MSI_FREQ macro
(**) HSI_VALUE is a constant defined in this file (default value 16 MHz) but the real value may vary depending on the variations in voltage and temperature.
(***) HSE_VALUE is a constant defined in this file (default value 32 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may have wrong result.
The result of this function could be incorrect when using fractional value for HSE crystal.
This function can be used by the user application to compute the baud-rate for the communication peripherals or configure other parameters.

Function Documentation

uint32_t LL_RCC_GetADCClockFreq ( uint32_t ADCxSource )

Return ADCx clock frequency.

Parameters:
ADCxSource This parameter can be one of the following values:
  • LL_RCC_ADC_CLKSOURCE
Return values:
ADC clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
  • LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected

Definition at line 755 of file stm32wbxx_ll_rcc.c.

References assert_param, IS_LL_RCC_ADC_CLKSOURCE, LL_RCC_ADC_CLKSOURCE_NONE, LL_RCC_ADC_CLKSOURCE_PLL, LL_RCC_ADC_CLKSOURCE_PLLSAI1, LL_RCC_ADC_CLKSOURCE_SYSCLK, LL_RCC_GetADCClockSource(), LL_RCC_PERIPH_FREQUENCY_NA, LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_PLL_IsReady(), LL_RCC_PLLSAI1_IsReady(), RCC_GetSystemClockFreq(), RCC_PLL_GetFreqDomain_ADC(), and RCC_PLLSAI1_GetFreqDomain_ADC().

uint32_t LL_RCC_GetCLK48ClockFreq ( uint32_t CLK48xSource )

Return CLK48x clock frequency.

Parameters:
CLK48xSource This parameter can be one of the following values:
  • LL_RCC_CLK48_CLKSOURCE
Return values:
USB clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI or HSI48) or PLLs (PLL or PLLSAI1) is not ready

Definition at line 648 of file stm32wbxx_ll_rcc.c.

References __LL_RCC_CALC_MSI_FREQ, assert_param, HSI48_VALUE, IS_LL_RCC_CLK48_CLKSOURCE, LL_RCC_CLK48_CLKSOURCE_HSI48, LL_RCC_CLK48_CLKSOURCE_MSI, LL_RCC_CLK48_CLKSOURCE_PLL, LL_RCC_CLK48_CLKSOURCE_PLLSAI1, LL_RCC_GetCLK48ClockSource(), LL_RCC_HSI48_IsReady(), LL_RCC_MSI_GetRange(), LL_RCC_MSI_IsReady(), LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_PLL_IsReady(), LL_RCC_PLLSAI1_IsReady(), RCC_PLL_GetFreqDomain_48M(), and RCC_PLLSAI1_GetFreqDomain_48M().

Referenced by LL_RCC_GetRNGClockFreq(), and LL_RCC_GetUSBClockFreq().

uint32_t LL_RCC_GetI2CClockFreq ( uint32_t I2CxSource )

Return I2Cx clock frequency.

Parameters:
I2CxSource This parameter can be one of the following values:
  • LL_RCC_I2C1_CLKSOURCE
  • LL_RCC_I2C3_CLKSOURCE
Return values:
I2C clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready

Definition at line 406 of file stm32wbxx_ll_rcc.c.

References assert_param, HSI_VALUE, IS_LL_RCC_I2C_CLKSOURCE, LL_RCC_GetI2CClockSource(), LL_RCC_HSI_IsReady(), LL_RCC_I2C1_CLKSOURCE, LL_RCC_I2C1_CLKSOURCE_HSI, LL_RCC_I2C1_CLKSOURCE_PCLK1, LL_RCC_I2C1_CLKSOURCE_SYSCLK, LL_RCC_I2C3_CLKSOURCE_HSI, LL_RCC_I2C3_CLKSOURCE_PCLK1, LL_RCC_I2C3_CLKSOURCE_SYSCLK, LL_RCC_PERIPH_FREQUENCY_NO, RCC_GetHCLK1ClockFreq(), RCC_GetPCLK1ClockFreq(), and RCC_GetSystemClockFreq().

uint32_t LL_RCC_GetLPTIMClockFreq ( uint32_t LPTIMxSource )

Return LPTIMx clock frequency.

Parameters:
LPTIMxSource This parameter can be one of the following values:
  • LL_RCC_LPTIM1_CLKSOURCE
  • LL_RCC_LPTIM2_CLKSOURCE
Return values:
LPTIM clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready

Definition at line 517 of file stm32wbxx_ll_rcc.c.

References assert_param, HSI_VALUE, IS_LL_RCC_LPTIM_CLKSOURCE, LL_RCC_GetLPTIMClockSource(), LL_RCC_HSI_IsReady(), LL_RCC_LPTIM1_CLKSOURCE, LL_RCC_LPTIM1_CLKSOURCE_HSI, LL_RCC_LPTIM1_CLKSOURCE_LSE, LL_RCC_LPTIM1_CLKSOURCE_LSI, LL_RCC_LPTIM1_CLKSOURCE_PCLK1, LL_RCC_LPTIM2_CLKSOURCE_HSI, LL_RCC_LPTIM2_CLKSOURCE_LSE, LL_RCC_LPTIM2_CLKSOURCE_LSI, LL_RCC_LPTIM2_CLKSOURCE_PCLK1, LL_RCC_LSE_IsReady(), LL_RCC_LSI1_IsReady(), LL_RCC_LSI2_IsReady(), LL_RCC_PERIPH_FREQUENCY_NO, LSE_VALUE, RCC_GetHCLK1ClockFreq(), RCC_GetPCLK1ClockFreq(), and RCC_GetSystemClockFreq().

uint32_t LL_RCC_GetLPUARTClockFreq ( uint32_t LPUARTxSource )

Return LPUARTx clock frequency.

Parameters:
LPUARTxSource This parameter can be one of the following values:
  • LL_RCC_LPUART1_CLKSOURCE
Return values:
LPUART clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready

Definition at line 471 of file stm32wbxx_ll_rcc.c.

References assert_param, HSI_VALUE, IS_LL_RCC_LPUART_CLKSOURCE, LL_RCC_GetLPUARTClockSource(), LL_RCC_HSI_IsReady(), LL_RCC_LPUART1_CLKSOURCE_HSI, LL_RCC_LPUART1_CLKSOURCE_LSE, LL_RCC_LPUART1_CLKSOURCE_PCLK1, LL_RCC_LPUART1_CLKSOURCE_SYSCLK, LL_RCC_LSE_IsReady(), LL_RCC_PERIPH_FREQUENCY_NO, LSE_VALUE, RCC_GetHCLK1ClockFreq(), RCC_GetPCLK1ClockFreq(), and RCC_GetSystemClockFreq().

Referenced by LL_LPUART_Init().

uint32_t LL_RCC_GetRFWKPClockFreq ( void )

Return RF Wakeup clock frequency.

Return values:
RFWKP clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillators (LSI, LSE or HSE) are not ready
  • LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected

Definition at line 842 of file stm32wbxx_ll_rcc.c.

References HSE_VALUE, LL_RCC_GetRFWKPClockSource(), LL_RCC_LSE_IsReady(), LL_RCC_LSI1_IsReady(), LL_RCC_LSI2_IsReady(), LL_RCC_PERIPH_FREQUENCY_NA, LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024, LL_RCC_RFWKP_CLKSOURCE_LSE, LL_RCC_RFWKP_CLKSOURCE_LSI, LL_RCC_RFWKP_CLKSOURCE_NONE, and LSE_VALUE.

uint32_t LL_RCC_GetRNGClockFreq ( uint32_t RNGxSource )

Return RNGx clock frequency.

Parameters:
RNGxSource This parameter can be one of the following values:
  • LL_RCC_RNG_CLKSOURCE
Return values:
RNG clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI or HSI48) or PLLs (PLL or PLLSAI1) is not ready

Definition at line 714 of file stm32wbxx_ll_rcc.c.

References assert_param, IS_LL_RCC_RNG_CLKSOURCE, LL_RCC_CLK48_CLKSOURCE, LL_RCC_GetCLK48ClockFreq(), LL_RCC_GetRNGClockSource(), LL_RCC_LSE_IsReady(), LL_RCC_LSI1_IsReady(), LL_RCC_LSI2_IsReady(), LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_RNG_CLKSOURCE_LSE, LL_RCC_RNG_CLKSOURCE_LSI, and LSE_VALUE.

uint32_t LL_RCC_GetRTCClockFreq ( void )

Return RTC & LCD clock frequency.

Return values:
RTC clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillators (LSI, LSE or HSE) are not ready
  • LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected

Definition at line 800 of file stm32wbxx_ll_rcc.c.

References HSE_VALUE, LL_RCC_GetRTCClockSource(), LL_RCC_LSE_IsReady(), LL_RCC_LSI1_IsReady(), LL_RCC_LSI2_IsReady(), LL_RCC_PERIPH_FREQUENCY_NA, LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_RTC_CLKSOURCE_HSE_DIV32, LL_RCC_RTC_CLKSOURCE_LSE, LL_RCC_RTC_CLKSOURCE_LSI, LL_RCC_RTC_CLKSOURCE_NONE, and LSE_VALUE.

uint32_t LL_RCC_GetSAIClockFreq ( uint32_t SAIxSource )

Return SAIx clock frequency.

Parameters:
SAIxSource This parameter can be one of the following values:
  • LL_RCC_SAI1_CLKSOURCE
Return values:
SAI clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready
  • LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used

Definition at line 603 of file stm32wbxx_ll_rcc.c.

References assert_param, HSI_VALUE, IS_LL_RCC_SAI_CLKSOURCE, LL_RCC_GetSAIClockSource(), LL_RCC_HSI_IsReady(), LL_RCC_PERIPH_FREQUENCY_NA, LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_PLL_IsReady(), LL_RCC_PLLSAI1_IsReady(), LL_RCC_SAI1_CLKSOURCE_HSI, LL_RCC_SAI1_CLKSOURCE_PIN, LL_RCC_SAI1_CLKSOURCE_PLL, LL_RCC_SAI1_CLKSOURCE_PLLSAI1, RCC_PLL_GetFreqDomain_SAI(), and RCC_PLLSAI1_GetFreqDomain_SAI().

uint32_t LL_RCC_GetSMPSClockFreq ( void )

Return SMPS clock frequency.

Note:
This function is only applicable when CPU runs, When waking up from Standby mode and powering on the VCODE supply, the HSI is selected as SMPS Step Down converter clock, independent from the selection in SMPSSEL.
Return values:
SMPS clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready

Definition at line 286 of file stm32wbxx_ll_rcc.c.

References __LL_RCC_CALC_MSI_FREQ, HSE_VALUE, HSI_VALUE, LL_RCC_GetSMPSClockSource(), LL_RCC_GetSMPSPrescaler(), LL_RCC_HSE_IsReady(), LL_RCC_HSI_IsReady(), LL_RCC_MSI_GetRange(), LL_RCC_MSIRANGE_10, LL_RCC_MSIRANGE_11, LL_RCC_MSIRANGE_8, LL_RCC_MSIRANGE_9, LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_SMPS_CLKSOURCE_STATUS_HSE, LL_RCC_SMPS_CLKSOURCE_STATUS_HSI, and LL_RCC_SMPS_CLKSOURCE_STATUS_MSI.

void LL_RCC_GetSystemClocksFreq ( LL_RCC_ClocksTypeDef * RCC_Clocks )

Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks.

Note:
Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function must be called to update structure fields. Otherwise, any configuration based on this function will be incorrect.
Parameters:
RCC_Clocks pointer to a LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
Return values:
None

Definition at line 252 of file stm32wbxx_ll_rcc.c.

References LL_RCC_ClocksTypeDef::HCLK1_Frequency, LL_RCC_ClocksTypeDef::HCLK2_Frequency, LL_RCC_ClocksTypeDef::HCLK4_Frequency, LL_RCC_ClocksTypeDef::HCLK5_Frequency, LL_RCC_ClocksTypeDef::PCLK1_Frequency, LL_RCC_ClocksTypeDef::PCLK2_Frequency, RCC_GetHCLK1ClockFreq(), RCC_GetHCLK2ClockFreq(), RCC_GetHCLK4ClockFreq(), RCC_GetHCLK5ClockFreq(), RCC_GetPCLK1ClockFreq(), RCC_GetPCLK2ClockFreq(), RCC_GetSystemClockFreq(), and LL_RCC_ClocksTypeDef::SYSCLK_Frequency.

Referenced by LL_LPTIM_Disable().

uint32_t LL_RCC_GetUSARTClockFreq ( uint32_t USARTxSource )

Return USARTx clock frequency.

Parameters:
USARTxSource This parameter can be one of the following values:
  • LL_RCC_USART1_CLKSOURCE
Return values:
USART clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready

Definition at line 362 of file stm32wbxx_ll_rcc.c.

References assert_param, HSI_VALUE, IS_LL_RCC_USART_CLKSOURCE, LL_RCC_GetUSARTClockSource(), LL_RCC_HSI_IsReady(), LL_RCC_LSE_IsReady(), LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_USART1_CLKSOURCE_HSI, LL_RCC_USART1_CLKSOURCE_LSE, LL_RCC_USART1_CLKSOURCE_PCLK2, LL_RCC_USART1_CLKSOURCE_SYSCLK, LSE_VALUE, RCC_GetHCLK1ClockFreq(), RCC_GetPCLK2ClockFreq(), and RCC_GetSystemClockFreq().

Referenced by LL_USART_Init().

uint32_t LL_RCC_GetUSBClockFreq ( uint32_t USBxSource )

Return USBx clock frequency.

Parameters:
USBxSource This parameter can be one of the following values:
  • LL_RCC_CLK48_CLKSOURCE
Return values:
USB clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI or HSI48) or PLLs (PLL or PLLSAI1) is not ready

Definition at line 701 of file stm32wbxx_ll_rcc.c.

References LL_RCC_GetCLK48ClockFreq().

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RNG

Modules
RNG
STM32WBxx_LL_Driver

Modules

RNG Exported Init structures
RNG Exported Constants
RNG Exported Macros
RNG Exported Functions
RNG_LL_Private_Macros

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for RNG registers.

Register | Bit | Function
CR | CED | LL_RNG_DisableClkErrorDetect
 |  | LL_RNG_EnableClkErrorDetect
 |  | LL_RNG_IsEnabledClkErrorDetect
 | IE | LL_RNG_DisableIT
 |  | LL_RNG_EnableIT
 |  | LL_RNG_IsEnabledIT
 | RNGEN | LL_RNG_Disable
 |  | LL_RNG_Enable
 |  | LL_RNG_IsEnabled
DR | RNDATA | LL_RNG_ReadRandData32
SR | CECS | LL_RNG_IsActiveFlag_CECS
 | CEIS | LL_RNG_ClearFlag_CEIS
 |  | LL_RNG_IsActiveFlag_CEIS
 | DRDY | LL_RNG_IsActiveFlag_DRDY
 | SECS | LL_RNG_IsActiveFlag_SECS
 | SEIS | LL_RNG_ClearFlag_SEIS
 |  | LL_RNG_IsActiveFlag_SEIS
Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LL_RNG_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_RNG_InitTypeDef Struct Reference
RNG Exported Init structures

LL RNG Init Structure Definition. More...

#include <stm32wbxx_ll_rng.h>

Data Fields

uint32_t ClockErrorDetection

Detailed Description

LL RNG Init Structure Definition.

Definition at line 56 of file stm32wbxx_ll_rng.h.

Field Documentation

uint32_t LL_RNG_InitTypeDef::ClockErrorDetection

Clock error detection. This parameter can be one value of Clock Error Detection.

This parameter can be modified using unitary functions LL_RNG_EnableClkErrorDetect().

Definition at line 58 of file stm32wbxx_ll_rng.h.

Referenced by LL_RNG_Init(), and LL_RNG_StructInit().

The documentation for this struct was generated from the following file:
  • stm32wbxx_ll_rng.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Clock Error Detection

Defines
Clock Error Detection
RNG Exported Constants

Defines

#define | LL_RNG_CED_ENABLE 0x00000000U
#define | LL_RNG_CED_DISABLE RNG_CR_CED

Define Documentation

#define LL_RNG_CED_DISABLE RNG_CR_CED

Clock error detection disabled

Definition at line 77 of file stm32wbxx_ll_rng.h.

#define LL_RNG_CED_ENABLE 0x00000000U

Clock error detection enabled

Definition at line 76 of file stm32wbxx_ll_rng.h.

Referenced by LL_RNG_StructInit().

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
RNG Exported Constants

Flags defines which can be used with LL_RNG_ReadReg function. More...

Defines

#define | LL_RNG_SR_DRDY RNG_SR_DRDY
#define | LL_RNG_SR_CECS RNG_SR_CECS
#define | LL_RNG_SR_SECS RNG_SR_SECS
#define | LL_RNG_SR_CEIS RNG_SR_CEIS
#define | LL_RNG_SR_SEIS RNG_SR_SEIS

Detailed Description

Flags defines which can be used with LL_RNG_ReadReg function.

Define Documentation

#define LL_RNG_SR_CECS RNG_SR_CECS

Clock error current status

Definition at line 87 of file stm32wbxx_ll_rng.h.

#define LL_RNG_SR_CEIS RNG_SR_CEIS

Clock error interrupt status

Definition at line 89 of file stm32wbxx_ll_rng.h.

#define LL_RNG_SR_DRDY RNG_SR_DRDY

Register contains valid random data

Definition at line 86 of file stm32wbxx_ll_rng.h.

#define LL_RNG_SR_SECS RNG_SR_SECS

Seed error current status

Definition at line 88 of file stm32wbxx_ll_rng.h.

#define LL_RNG_SR_SEIS RNG_SR_SEIS

Seed error interrupt status

Definition at line 90 of file stm32wbxx_ll_rng.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IT Defines

Defines
IT Defines
RNG Exported Constants

IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros. More...

Defines

#define LL_RNG_CR_IE RNG_CR_IE

Detailed Description

IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros.

Define Documentation

#define LL_RNG_CR_IE RNG_CR_IE

RNG Interrupt enable

Definition at line 99 of file stm32wbxx_ll_rng.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
RNG Exported Macros

Defines

#define | LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in RNG register.
#define | LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in RNG register.

Define Documentation

#define LL_RNG_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in RNG register.

Parameters:
__INSTANCE__ | RNG Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 132 of file stm32wbxx_ll_rng.h.

#define LL_RNG_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in RNG register.

Parameters:
__INSTANCE__ | RNG Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 124 of file stm32wbxx_ll_rng.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RNG Configuration functions

Functions
RNG Configuration functions
RNG Exported Functions

Functions

__STATIC_INLINE void | LL_RNG_Enable (RNG_TypeDef *RNGx)
Enable Random Number Generation.
__STATIC_INLINE void | LL_RNG_Disable (RNG_TypeDef *RNGx)
Disable Random Number Generation.
__STATIC_INLINE uint32_t | LL_RNG_IsEnabled (RNG_TypeDef *RNGx)
Check if Random Number Generator is enabled.
__STATIC_INLINE void | LL_RNG_EnableClkErrorDetect (RNG_TypeDef *RNGx)
Enable Clock Error Detection.
__STATIC_INLINE void | LL_RNG_DisableClkErrorDetect (RNG_TypeDef *RNGx)
Disable RNG Clock Error Detection.
__STATIC_INLINE uint32_t | LL_RNG_IsEnabledClkErrorDetect (RNG_TypeDef *RNGx)
Check if RNG Clock Error Detection is enabled.

Function Documentation

__STATIC_INLINE void LL_RNG_Disable ( RNG_TypeDef * RNGx )

Disable Random Number Generation.

Reference Manual to LL API cross reference:
CR RNGEN LL_RNG_Disable
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 167 of file stm32wbxx_ll_rng.h.

__STATIC_INLINE void LL_RNG_DisableClkErrorDetect ( RNG_TypeDef * RNGx )

Disable RNG Clock Error Detection.

Reference Manual to LL API cross reference:
CR CED LL_RNG_DisableClkErrorDetect
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 200 of file stm32wbxx_ll_rng.h.

__STATIC_INLINE void LL_RNG_Enable ( RNG_TypeDef * RNGx )

Enable Random Number Generation.

Reference Manual to LL API cross reference:
CR RNGEN LL_RNG_Enable
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 156 of file stm32wbxx_ll_rng.h.

__STATIC_INLINE void LL_RNG_EnableClkErrorDetect ( RNG_TypeDef * RNGx )

Enable Clock Error Detection.

Reference Manual to LL API cross reference:
CR CED LL_RNG_EnableClkErrorDetect
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 189 of file stm32wbxx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsEnabled ( RNG_TypeDef * RNGx )

Check if Random Number Generator is enabled.

Reference Manual to LL API cross reference:
CR RNGEN LL_RNG_IsEnabled
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 178 of file stm32wbxx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect ( RNG_TypeDef * RNGx )

Check if RNG Clock Error Detection is enabled.

Reference Manual to LL API cross reference:
CR CED LL_RNG_IsEnabledClkErrorDetect
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 211 of file stm32wbxx_ll_rng.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FLAG Management

Functions
FLAG Management
RNG Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_DRDY (RNG_TypeDef *RNGx)
Indicate if the RNG Data ready Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_CECS (RNG_TypeDef *RNGx)
Indicate if the Clock Error Current Status Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_SECS (RNG_TypeDef *RNGx)
Indicate if the Seed Error Current Status Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_CEIS (RNG_TypeDef *RNGx)
Indicate if the Clock Error Interrupt Status Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_SEIS (RNG_TypeDef *RNGx)
Indicate if the Seed Error Interrupt Status Flag is set or not.
__STATIC_INLINE void | LL_RNG_ClearFlag_CEIS (RNG_TypeDef *RNGx)
Clear Clock Error interrupt Status (CEIS) Flag.
__STATIC_INLINE void | LL_RNG_ClearFlag_SEIS (RNG_TypeDef *RNGx)
Clear Seed Error interrupt Status (SEIS) Flag.

Function Documentation

__STATIC_INLINE void LL_RNG_ClearFlag_CEIS ( RNG_TypeDef * RNGx )

Clear Clock Error interrupt Status (CEIS) Flag.

Reference Manual to LL API cross reference:
SR CEIS LL_RNG_ClearFlag_CEIS
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 285 of file stm32wbxx_ll_rng.h.

__STATIC_INLINE void LL_RNG_ClearFlag_SEIS ( RNG_TypeDef * RNGx )

Clear Seed Error interrupt Status (SEIS) Flag.

Reference Manual to LL API cross reference:
SR SEIS LL_RNG_ClearFlag_SEIS
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 296 of file stm32wbxx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS ( RNG_TypeDef * RNGx )

Indicate if the Clock Error Current Status Flag is set or not.

Reference Manual to LL API cross reference:
SR CECS LL_RNG_IsActiveFlag_CECS
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 241 of file stm32wbxx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS ( RNG_TypeDef * RNGx )

Indicate if the Clock Error Interrupt Status Flag is set or not.

Reference Manual to LL API cross reference:
SR CEIS LL_RNG_IsActiveFlag_CEIS
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 263 of file stm32wbxx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY ( RNG_TypeDef * RNGx )

Indicate if the RNG Data ready Flag is set or not.

Reference Manual to LL API cross reference:
SR DRDY LL_RNG_IsActiveFlag_DRDY
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 230 of file stm32wbxx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS ( RNG_TypeDef * RNGx )

Indicate if the Seed Error Current Status Flag is set or not.

Reference Manual to LL API cross reference:
SR SECS LL_RNG_IsActiveFlag_SECS
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 252 of file stm32wbxx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS ( RNG_TypeDef * RNGx )

Indicate if the Seed Error Interrupt Status Flag is set or not.

Reference Manual to LL API cross reference:
SR SEIS LL_RNG_IsActiveFlag_SEIS
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 274 of file stm32wbxx_ll_rng.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IT Management

Functions
IT Management
RNG Exported Functions

Functions

__STATIC_INLINE void | LL_RNG_EnableIT (RNG_TypeDef *RNGx)
Enable Random Number Generator Interrupt (applies for either Seed error, Clock Error or Data ready interrupts)
__STATIC_INLINE void | LL_RNG_DisableIT (RNG_TypeDef *RNGx)
Disable Random Number Generator Interrupt (applies for either Seed error, Clock Error or Data ready interrupts)
__STATIC_INLINE uint32_t | LL_RNG_IsEnabledIT (RNG_TypeDef *RNGx)
Check if Random Number Generator Interrupt is enabled (applies for either Seed error, Clock Error or Data ready interrupts)

Function Documentation

__STATIC_INLINE void LL_RNG_DisableIT ( RNG_TypeDef * RNGx )

Disable Random Number Generator Interrupt (applies for either Seed error, Clock Error or Data ready interrupts)

Reference Manual to LL API cross reference:
CR IE LL_RNG_DisableIT
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 328 of file stm32wbxx_ll_rng.h.

__STATIC_INLINE void LL_RNG_EnableIT ( RNG_TypeDef * RNGx )

Enable Random Number Generator Interrupt (applies for either Seed error, Clock Error or Data ready interrupts)

Reference Manual to LL API cross reference:
CR IE LL_RNG_EnableIT
Parameters:
RNGx RNG Instance
Return values:
None

Definition at line 316 of file stm32wbxx_ll_rng.h.

__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT ( RNG_TypeDef * RNGx )

Check if Random Number Generator Interrupt is enabled (applies for either Seed error, Clock Error or Data ready interrupts)

Reference Manual to LL API cross reference:
CR IE LL_RNG_IsEnabledIT
Parameters:
RNGx RNG Instance
Return values:
State of bit (1 or 0).

Definition at line 340 of file stm32wbxx_ll_rng.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Management

Functions
Data Management
RNG Exported Functions

Functions

__STATIC_INLINE uint32_t LL_RNG_ReadRandData32 (RNG_TypeDef *RNGx)
Return32-bit Random Number value.

Function Documentation

__STATIC_INLINE uint32_t LL_RNG_ReadRandData32 ( RNG_TypeDef * RNGx )

Return32-bit Random Number value.

Reference Manual to LL API cross reference:
DR RNDATA LL_RNG_ReadRandData32
Parameters:
RNGx RNG Instance
Return values:
Generated 32-bit random value

Definition at line 359 of file stm32wbxx_ll_rng.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
RNG Exported Functions

Functions

ErrorStatus | LL_RNG_DeInit (RNG_TypeDef *RNGx)
De-initialize RNG registers (Registers restored to their default values).
ErrorStatus | LL_RNG_Init (RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct)
Initialize RNG registers according to the specified parameters in RNG_InitStruct.
void | LL_RNG_StructInit (LL_RNG_InitTypeDef *RNG_InitStruct)
Set each LL_RNG_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_RNG_DeInit ( RNG_TypeDef * RNGx )

De-initialize RNG registers (Registers restored to their default values).

Parameters:
RNGx RNG Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RNG registers are de-initialized
  • ERROR: not applicable

Definition at line 72 of file stm32wbxx_ll_rng.c.

References assert_param, LL_AHB3_GRP1_ForceReset(), LL_AHB3_GRP1_PERIPH_RNG, and LL_AHB3_GRP1_ReleaseReset().

ErrorStatus LL_RNG_Init | ( | RNG_TypeDef * | RNGx,
 |  | LL_RNG_InitTypeDef * | RNG_InitStruct
 | ) |  |

Initialize RNG registers according to the specified parameters in RNG_InitStruct.

Parameters:
RNGx | RNG Instance
RNG_InitStruct | pointer to a LL_RNG_InitTypeDef structure that contains the configuration information for the specified RNG peripheral.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RNG registers are initialized according to RNG_InitStruct content
  • ERROR: not applicable

Definition at line 93 of file stm32wbxx_ll_rng.c.

References assert_param, LL_RNG_InitTypeDef::ClockErrorDetection, and IS_LL_RNG_CED.

void LL_RNG_StructInit ( LL_RNG_InitTypeDef * RNG_InitStruct )

Set each LL_RNG_InitTypeDef field to default value.

Parameters:
RNG_InitStruct pointer to a LL_RNG_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 111 of file stm32wbxx_ll_rng.c.

References LL_RNG_InitTypeDef::ClockErrorDetection, and LL_RNG_CED_ENABLE.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RNG_LL_Private_Macros

Defines
RNG_LL_Private_Macros
RNG

Defines

#define IS_LL_RNG_CED(__MODE__)

Define Documentation

#define IS_LL_RNG_CED ( __MODE__ )
Value:
(((__MODE__) == LL_RNG_CED_ENABLE) || \
                                 ((__MODE__) == LL_RNG_CED_DISABLE))

Definition at line 48 of file stm32wbxx_ll_rng.c.

Referenced by LL_RNG_Init().

Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC

Modules
RTC
STM32WBxx_LL_Driver

Modules

RTC Private Constants
RTC Private Macros
RTC Exported Init structure
RTC Exported Constants
RTC Exported Macros
RTC Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for RTC registers.

Register | Bit | Function
ALRMAR | DT | LL_RTC_ALMA_GetDay
 |  | LL_RTC_ALMA_SetDay
 | DU | LL_RTC_ALMA_GetDay
 |  | LL_RTC_ALMA_GetWeekDay
 |  | LL_RTC_ALMA_SetDay
 |  | LL_RTC_ALMA_SetWeekDay
 | HT | LL_RTC_ALMA_ConfigTime
 |  | LL_RTC_ALMA_GetHour
 |  | LL_RTC_ALMA_GetTime
 |  | LL_RTC_ALMA_SetHour
 | HU | LL_RTC_ALMA_ConfigTime
 |  | LL_RTC_ALMA_GetHour
 |  | LL_RTC_ALMA_GetTime
 |  | LL_RTC_ALMA_SetHour
 | MNT | LL_RTC_ALMA_ConfigTime
 |  | LL_RTC_ALMA_GetMinute
 |  | LL_RTC_ALMA_GetTime
 |  | LL_RTC_ALMA_SetMinute
 | MNU | LL_RTC_ALMA_ConfigTime
 |  | LL_RTC_ALMA_GetMinute
 |  | LL_RTC_ALMA_GetTime
 |  | LL_RTC_ALMA_SetMinute
 | MSK1 | LL_RTC_ALMA_GetMask
 |  | LL_RTC_ALMA_SetMask
 | MSK2 | LL_RTC_ALMA_GetMask
 |  | LL_RTC_ALMA_SetMask
 | MSK3 | LL_RTC_ALMA_GetMask
 |  | LL_RTC_ALMA_SetMask
 | MSK4 | LL_RTC_ALMA_GetMask
 |  | LL_RTC_ALMA_SetMask
 | PM | LL_RTC_ALMA_ConfigTime
 |  | LL_RTC_ALMA_GetTimeFormat
 |  | LL_RTC_ALMA_SetTimeFormat
 | ST | LL_RTC_ALMA_ConfigTime
 |  | LL_RTC_ALMA_GetSecond
 |  | LL_RTC_ALMA_GetTime
 |  | LL_RTC_ALMA_SetSecond
 | SU | LL_RTC_ALMA_ConfigTime
 |  | LL_RTC_ALMA_GetSecond
 |  | LL_RTC_ALMA_GetTime
 |  | LL_RTC_ALMA_SetSecond
 | WDSEL | LL_RTC_ALMA_DisableWeekday
 |  | LL_RTC_ALMA_EnableWeekday
ALRMASSR | MASKSS | LL_RTC_ALMA_GetSubSecondMask
 |  | LL_RTC_ALMA_SetSubSecondMask
 | SS | LL_RTC_ALMA_GetSubSecond
 |  | LL_RTC_ALMA_SetSubSecond
ALRMBR | DT | LL_RTC_ALMB_GetDay
 |  | LL_RTC_ALMB_SetDay
 | DU | LL_RTC_ALMB_GetDay
 |  | LL_RTC_ALMB_GetWeekDay
 |  | LL_RTC_ALMB_SetDay
 |  | LL_RTC_ALMB_SetWeekDay
 | HT | LL_RTC_ALMB_ConfigTime
 |  | LL_RTC_ALMB_GetHour
 |  | LL_RTC_ALMB_GetTime
 |  | LL_RTC_ALMB_SetHour
 | HU | LL_RTC_ALMB_ConfigTime
 |  | LL_RTC_ALMB_GetHour
 |  | LL_RTC_ALMB_GetTime
 |  | LL_RTC_ALMB_SetHour
 | MNT | LL_RTC_ALMB_ConfigTime
 |  | LL_RTC_ALMB_GetMinute
 |  | LL_RTC_ALMB_GetTime
 |  | LL_RTC_ALMB_SetMinute
 | MNU | LL_RTC_ALMB_ConfigTime
 |  | LL_RTC_ALMB_GetMinute
 |  | LL_RTC_ALMB_GetTime
 |  | LL_RTC_ALMB_SetMinute
 | MSK1 | LL_RTC_ALMB_GetMask
 |  | LL_RTC_ALMB_SetMask
 | MSK2 | LL_RTC_ALMB_GetMask
 |  | LL_RTC_ALMB_SetMask
 | MSK3 | LL_RTC_ALMB_GetMask
 |  | LL_RTC_ALMB_SetMask
 | MSK4 | LL_RTC_ALMB_GetMask
 |  | LL_RTC_ALMB_SetMask
 | PM | LL_RTC_ALMB_ConfigTime
 |  | LL_RTC_ALMB_GetTimeFormat
 |  | LL_RTC_ALMB_SetTimeFormat
 | ST | LL_RTC_ALMB_ConfigTime
 |  | LL_RTC_ALMB_GetSecond
 |  | LL_RTC_ALMB_GetTime
 |  | LL_RTC_ALMB_SetSecond
 | SU | LL_RTC_ALMB_ConfigTime
 |  | LL_RTC_ALMB_GetSecond
 |  | LL_RTC_ALMB_GetTime
 |  | LL_RTC_ALMB_SetSecond
 | WDSEL | LL_RTC_ALMB_DisableWeekday
 |  | LL_RTC_ALMB_EnableWeekday
ALRMBSSR | MASKSS | LL_RTC_ALMB_GetSubSecondMask
 |  | LL_RTC_ALMB_SetSubSecondMask
 | SS | LL_RTC_ALMB_GetSubSecond
 |  | LL_RTC_ALMB_SetSubSecond
BKPxR | BKP | LL_RTC_BAK_GetRegister
 |  | LL_RTC_BAK_SetRegister
CALR | CALM | LL_RTC_CAL_GetMinus
 |  | LL_RTC_CAL_SetMinus
 | CALP | LL_RTC_CAL_IsPulseInserted
 |  | LL_RTC_CAL_SetPulse
 | CALW16 | LL_RTC_CAL_GetPeriod
 |  | LL_RTC_CAL_SetPeriod
 | CALW8 | LL_RTC_CAL_GetPeriod
 |  | LL_RTC_CAL_SetPeriod
CR | ADD1H | LL_RTC_TIME_IncHour
 | ALRAE | LL_RTC_ALMA_Disable
 |  | LL_RTC_ALMA_Enable
 | ALRAIE | LL_RTC_DisableIT_ALRA
 |  | LL_RTC_EnableIT_ALRA
 |  | LL_RTC_IsEnabledIT_ALRA
 | ALRBE | LL_RTC_ALMB_Disable
 |  | LL_RTC_ALMB_Enable
 | ALRBIE | LL_RTC_DisableIT_ALRB
 |  | LL_RTC_EnableIT_ALRB
 |  | LL_RTC_IsEnabledIT_ALRB
 | BKP | LL_RTC_TIME_DisableDayLightStore
 |  | LL_RTC_TIME_EnableDayLightStore
 |  | LL_RTC_TIME_IsDayLightStoreEnabled
 | BYPSHAD | LL_RTC_DisableShadowRegBypass
 |  | LL_RTC_EnableShadowRegBypass
 |  | LL_RTC_IsShadowRegBypassEnabled
 | COE | LL_RTC_CAL_GetOutputFreq
 |  | LL_RTC_CAL_SetOutputFreq
 | COSEL | LL_RTC_CAL_GetOutputFreq
 |  | LL_RTC_CAL_SetOutputFreq
 | FMT | LL_RTC_GetHourFormat
 |  | LL_RTC_SetHourFormat
 | ITSE | LL_RTC_TS_DisableInternalEvent
 |  | LL_RTC_TS_EnableInternalEvent
 | OSEL | LL_RTC_GetAlarmOutEvent
 |  | LL_RTC_SetAlarmOutEvent
 | POL | LL_RTC_GetOutputPolarity
 |  | LL_RTC_SetOutputPolarity
 | REFCKON | LL_RTC_DisableRefClock
 |  | LL_RTC_EnableRefClock
 | SUB1H | LL_RTC_TIME_DecHour
 | TSE | LL_RTC_TS_Disable
 |  | LL_RTC_TS_Enable
 | TSEDGE | LL_RTC_TS_GetActiveEdge
 |  | LL_RTC_TS_SetActiveEdge
 | TSIE | LL_RTC_DisableIT_TS
 |  | LL_RTC_EnableIT_TS
 |  | LL_RTC_IsEnabledIT_TS
 | WUCKSEL | LL_RTC_WAKEUP_GetClock
 |  | LL_RTC_WAKEUP_SetClock
 | WUTE | LL_RTC_WAKEUP_Disable
 |  | LL_RTC_WAKEUP_Enable
 |  | LL_RTC_WAKEUP_IsEnabled
 | WUTIE | LL_RTC_DisableIT_WUT
 |  | LL_RTC_EnableIT_WUT
 |  | LL_RTC_IsEnabledIT_WUT
DR | DT | LL_RTC_DATE_Config
 |  | LL_RTC_DATE_Get
 |  | LL_RTC_DATE_GetDay
 |  | LL_RTC_DATE_SetDay
 | DU | LL_RTC_DATE_Config
 |  | LL_RTC_DATE_Get
 |  | LL_RTC_DATE_GetDay
 |  | LL_RTC_DATE_SetDay
 | MT | LL_RTC_DATE_Config
 |  | LL_RTC_DATE_Get
 |  | LL_RTC_DATE_GetMonth
 |  | LL_RTC_DATE_SetMonth
 | MU | LL_RTC_DATE_Config
 |  | LL_RTC_DATE_Get
 |  | LL_RTC_DATE_GetMonth
 |  | LL_RTC_DATE_SetMonth
 | WDU | LL_RTC_DATE_Config
 |  | LL_RTC_DATE_Get
 |  | LL_RTC_DATE_GetWeekDay
 |  | LL_RTC_DATE_SetWeekDay
 | YT | LL_RTC_DATE_Config
 |  | LL_RTC_DATE_Get
 |  | LL_RTC_DATE_GetYear
 |  | LL_RTC_DATE_SetYear
 | YU | LL_RTC_DATE_Config
 |  | LL_RTC_DATE_Get
 |  | LL_RTC_DATE_GetYear
 |  | LL_RTC_DATE_SetYear
ISR | ALRAF | LL_RTC_ClearFlag_ALRA
 |  | LL_RTC_IsActiveFlag_ALRA
 | ALRAWF | LL_RTC_IsActiveFlag_ALRAW
 | ALRBF | LL_RTC_ClearFlag_ALRB
 |  | LL_RTC_IsActiveFlag_ALRB
 | ALRBWF | LL_RTC_IsActiveFlag_ALRBW
 | INIT | LL_RTC_DisableInitMode
 |  | LL_RTC_EnableInitMode
 | INITF | LL_RTC_IsActiveFlag_INIT
 | INITS | LL_RTC_IsActiveFlag_INITS
 | ITSF | LL_RTC_ClearFlag_ITS
 |  | LL_RTC_IsActiveFlag_ITS
 | RECALPF | LL_RTC_IsActiveFlag_RECALP
 | RSF | LL_RTC_ClearFlag_RS
 |  | LL_RTC_IsActiveFlag_RS
 | SHPF | LL_RTC_IsActiveFlag_SHP
 | TAMP1F | LL_RTC_ClearFlag_TAMP1
 |  | LL_RTC_IsActiveFlag_TAMP1
 | TAMP2F | LL_RTC_ClearFlag_TAMP2
 |  | LL_RTC_IsActiveFlag_TAMP2
 | TAMP3F | LL_RTC_ClearFlag_TAMP3
 |  | LL_RTC_IsActiveFlag_TAMP3
 | TSF | LL_RTC_ClearFlag_TS
 |  | LL_RTC_IsActiveFlag_TS
 | TSOVF | LL_RTC_ClearFlag_TSOV
 |  | LL_RTC_IsActiveFlag_TSOV
 | WUTF | LL_RTC_ClearFlag_WUT
 |  | LL_RTC_IsActiveFlag_WUT
 | WUTWF | LL_RTC_IsActiveFlag_WUTW
OR | ALARMOUTTYPE | LL_RTC_GetAlarmOutputType
 |  | LL_RTC_SetAlarmOutputType
 | OUT_RMP | LL_RTC_DisableOutRemap
 |  | LL_RTC_EnableOutRemap
PRER | PREDIV_A | LL_RTC_GetAsynchPrescaler
 |  | LL_RTC_SetAsynchPrescaler
 | PREDIV_S | LL_RTC_GetSynchPrescaler
 |  | LL_RTC_SetSynchPrescaler
SHIFTR | ADD1S | LL_RTC_TIME_Synchronize
 | SUBFS | LL_RTC_TIME_Synchronize
SSR | SS | LL_RTC_TIME_GetSubSecond
TAMPCR | TAMP1E | LL_RTC_TAMPER_Disable
 |  | LL_RTC_TAMPER_Enable
 | TAMP1IE | LL_RTC_DisableIT_TAMP1
 |  | LL_RTC_EnableIT_TAMP1
 |  | LL_RTC_IsEnabledIT_TAMP1
 | TAMP1MF | LL_RTC_TAMPER_DisableMask
 |  | LL_RTC_TAMPER_EnableMask
 | TAMP1NOERASE | LL_RTC_TAMPER_DisableEraseBKP
 |  | LL_RTC_TAMPER_EnableEraseBKP
 | TAMP1TRG | LL_RTC_TAMPER_DisableActiveLevel
 |  | LL_RTC_TAMPER_EnableActiveLevel
 | TAMP2E | LL_RTC_TAMPER_Disable
 |  | LL_RTC_TAMPER_Enable
 | TAMP2IE | LL_RTC_DisableIT_TAMP2
 |  | LL_RTC_EnableIT_TAMP2
 |  | LL_RTC_IsEnabledIT_TAMP2
 | TAMP2MF | LL_RTC_TAMPER_DisableMask
 |  | LL_RTC_TAMPER_EnableMask
 | TAMP2NOERASE | LL_RTC_TAMPER_DisableEraseBKP
 |  | LL_RTC_TAMPER_EnableEraseBKP
 | TAMP2TRG | LL_RTC_TAMPER_DisableActiveLevel
 |  | LL_RTC_TAMPER_EnableActiveLevel
 | TAMP3E | LL_RTC_TAMPER_Disable
 |  | LL_RTC_TAMPER_Enable
 | TAMP3IE | LL_RTC_DisableIT_TAMP3
 |  | LL_RTC_EnableIT_TAMP3
 |  | LL_RTC_IsEnabledIT_TAMP3
 | TAMP3MF | LL_RTC_TAMPER_DisableMask
 |  | LL_RTC_TAMPER_EnableMask
 | TAMP3NOERASE | LL_RTC_TAMPER_DisableEraseBKP
 |  | LL_RTC_TAMPER_EnableEraseBKP
 | TAMP3TRG | LL_RTC_TAMPER_DisableActiveLevel
 |  | LL_RTC_TAMPER_EnableActiveLevel
 | TAMPFLT | LL_RTC_TAMPER_GetFilterCount
 |  | LL_RTC_TAMPER_SetFilterCount
 | TAMPFREQ | LL_RTC_TAMPER_GetSamplingFreq
 |  | LL_RTC_TAMPER_SetSamplingFreq
 | TAMPIE | LL_RTC_DisableIT_TAMP
 |  | LL_RTC_EnableIT_TAMP
 |  | LL_RTC_IsEnabledIT_TAMP
 | TAMPPRCH | LL_RTC_TAMPER_GetPrecharge
 |  | LL_RTC_TAMPER_SetPrecharge
 | TAMPPUDIS | LL_RTC_TAMPER_DisablePullUp
 |  | LL_RTC_TAMPER_EnablePullUp
 | TAMPTS | LL_RTC_TS_DisableOnTamper
 |  | LL_RTC_TS_EnableOnTamper
TR | HT | LL_RTC_TIME_Config
 |  | LL_RTC_TIME_Get
 |  | LL_RTC_TIME_GetHour
 |  | LL_RTC_TIME_SetHour
 | HU | LL_RTC_TIME_Config
 |  | LL_RTC_TIME_Get
 |  | LL_RTC_TIME_GetHour
 |  | LL_RTC_TIME_SetHour
 | MNT | LL_RTC_TIME_Config
 |  | LL_RTC_TIME_Get
 |  | LL_RTC_TIME_GetMinute
 |  | LL_RTC_TIME_SetMinute
 | MNU | LL_RTC_TIME_Config
 |  | LL_RTC_TIME_Get
 |  | LL_RTC_TIME_GetMinute
 |  | LL_RTC_TIME_SetMinute
 | PM | LL_RTC_TIME_Config
 |  | LL_RTC_TIME_GetFormat
 |  | LL_RTC_TIME_SetFormat
 | ST | LL_RTC_TIME_Config
 |  | LL_RTC_TIME_Get
 |  | LL_RTC_TIME_GetSecond
 |  | LL_RTC_TIME_SetSecond
 | SU | LL_RTC_TIME_Config
 |  | LL_RTC_TIME_Get
 |  | LL_RTC_TIME_GetSecond
 |  | LL_RTC_TIME_SetSecond
TSDR | DT | LL_RTC_TS_GetDate
 |  | LL_RTC_TS_GetDay
 | DU | LL_RTC_TS_GetDate
 |  | LL_RTC_TS_GetDay
 | MT | LL_RTC_TS_GetDate
 |  | LL_RTC_TS_GetMonth
 | MU | LL_RTC_TS_GetDate
 |  | LL_RTC_TS_GetMonth
 | WDU | LL_RTC_TS_GetDate
 |  | LL_RTC_TS_GetWeekDay
TSSSR | SS | LL_RTC_TS_GetSubSecond
TSTR | HT | LL_RTC_TS_GetHour
 |  | LL_RTC_TS_GetTime
 | HU | LL_RTC_TS_GetHour
 |  | LL_RTC_TS_GetTime
 | MNT | LL_RTC_TS_GetMinute
 |  | LL_RTC_TS_GetTime
 | MNU | LL_RTC_TS_GetMinute
 |  | LL_RTC_TS_GetTime
 | PM | LL_RTC_TS_GetTimeFormat
 | ST | LL_RTC_TS_GetSecond
 |  | LL_RTC_TS_GetTime
 | SU | LL_RTC_TS_GetSecond
 |  | LL_RTC_TS_GetTime
WPR | KEY | LL_RTC_DisableWriteProtection
 |  | LL_RTC_EnableWriteProtection
WUTR | WUT | LL_RTC_WAKEUP_GetAutoReload
 |  | LL_RTC_WAKEUP_SetAutoReload
Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC Private Constants

Defines
RTC Private Constants
RTC

Defines

#define | RTC_ASYNCH_PRESC_DEFAULT 0x0000007FU
#define | RTC_SYNCH_PRESC_DEFAULT 0x000000FFU
#define | RTC_INITMODE_TIMEOUT 1000U /* 1s when tick set to 1ms */
#define | RTC_SYNCHRO_TIMEOUT 1000U /* 1s when tick set to 1ms */
#define | RTC_WRITE_PROTECTION_DISABLE ((uint8_t)0xFFU)
#define | RTC_WRITE_PROTECTION_ENABLE_1 ((uint8_t)0xCAU)
#define | RTC_WRITE_PROTECTION_ENABLE_2 ((uint8_t)0x53U)
#define | RTC_OFFSET_WEEKDAY (uint32_t)24U
#define | RTC_OFFSET_DAY (uint32_t)16U
#define | RTC_OFFSET_MONTH (uint32_t)8U
#define | RTC_OFFSET_HOUR (uint32_t)16U
#define | RTC_OFFSET_MINUTE (uint32_t)8U

Define Documentation

#define RTC_ASYNCH_PRESC_DEFAULT 0x0000007FU

Definition at line 47 of file stm32wbxx_ll_rtc.c.

Referenced by LL_RTC_StructInit().

#define RTC_INITMODE_TIMEOUT 1000U /* 1s when tick set to 1ms */

Definition at line 51 of file stm32wbxx_ll_rtc.c.

Referenced by LL_RTC_EnterInitMode().

#define RTC_OFFSET_DAY (uint32_t)16U

Definition at line 55 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_DATE_Get().

#define RTC_OFFSET_HOUR (uint32_t)16U

Definition at line 57 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_ALMA_GetTime(), LL_RTC_ALMB_GetTime(), and LL_RTC_TIME_Get().

#define RTC_OFFSET_MINUTE (uint32_t)8U

Definition at line 58 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_ALMA_GetTime(), LL_RTC_ALMB_GetTime(), and LL_RTC_TIME_Get().

#define RTC_OFFSET_MONTH (uint32_t)8U

Definition at line 56 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_DATE_Get().

#define RTC_OFFSET_WEEKDAY (uint32_t)24U

Definition at line 54 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_DATE_Get().

#define RTC_SYNCH_PRESC_DEFAULT 0x000000FFU

Definition at line 48 of file stm32wbxx_ll_rtc.c.

Referenced by LL_RTC_DeInit(), and LL_RTC_StructInit().

#define RTC_SYNCHRO_TIMEOUT 1000U /* 1s when tick set to 1ms */

Definition at line 52 of file stm32wbxx_ll_rtc.c.

Referenced by LL_RTC_WaitForSynchro().

#define RTC_WRITE_PROTECTION_DISABLE ((uint8_t)0xFFU)

Definition at line 49 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_EnableWriteProtection().

#define RTC_WRITE_PROTECTION_ENABLE_1 ((uint8_t)0xCAU)

Definition at line 50 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_DisableWriteProtection().

#define RTC_WRITE_PROTECTION_ENABLE_2 ((uint8_t)0x53U)

Definition at line 51 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_DisableWriteProtection().

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC Private Macros

Defines
RTC Private Macros
RTC

Defines

#define | IS_LL_RTC_HOURFORMAT(__VALUE__)
#define | IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FU)
#define | IS_LL_RTC_SYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FFFU)
#define | IS_LL_RTC_FORMAT(__VALUE__)
#define | IS_LL_RTC_TIME_FORMAT(__VALUE__)
#define | IS_LL_RTC_HOUR12(__HOUR__) (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))
#define | IS_LL_RTC_HOUR24(__HOUR__) ((__HOUR__) <= 23U)
#define | IS_LL_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= 59U)
#define | IS_LL_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= 59U)
#define | IS_LL_RTC_WEEKDAY(__VALUE__)
#define | IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= 1U) && ((__DAY__) <= 31U))
#define | IS_LL_RTC_MONTH(__VALUE__)
#define | IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
#define | IS_LL_RTC_ALMA_MASK(__VALUE__)
#define | IS_LL_RTC_ALMB_MASK(__VALUE__)
#define | IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__)
#define | IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__)

Define Documentation

#define IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL ( __SEL__ )
Value:
(((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) || \
                                                  ((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY))

Definition at line 120 of file stm32wbxx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init().

#define IS_LL_RTC_ALMA_MASK ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_ALMA_MASK_NONE) \
                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_DATEWEEKDAY) \
                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_HOURS) \
                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_MINUTES) \
                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_SECONDS) \
                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_ALL))

Definition at line 105 of file stm32wbxx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init().

#define IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL ( __SEL__ )
Value:
(((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) || \
                                                  ((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY))

Definition at line 123 of file stm32wbxx_ll_rtc.c.

Referenced by LL_RTC_ALMB_Init().

#define IS_LL_RTC_ALMB_MASK ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_ALMB_MASK_NONE) \
                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_DATEWEEKDAY) \
                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_HOURS) \
                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_MINUTES) \
                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_SECONDS) \
                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_ALL))

Definition at line 112 of file stm32wbxx_ll_rtc.c.

Referenced by LL_RTC_ALMB_Init().

#define IS_LL_RTC_ASYNCH_PREDIV ( __VALUE__ ) ((__VALUE__) <= 0x7FU)

Definition at line 65 of file stm32wbxx_ll_rtc.c.

Referenced by LL_RTC_Init().

#define IS_LL_RTC_DAY ( __DAY__ ) (((__DAY__) >= 1U) && ((__DAY__) <= 31U))

Definition at line 88 of file stm32wbxx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_DATE_Init().

#define IS_LL_RTC_FORMAT ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_FORMAT_BIN) \
                                  || ((__VALUE__) == LL_RTC_FORMAT_BCD))

Definition at line 69 of file stm32wbxx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), and LL_RTC_TIME_Init().

#define IS_LL_RTC_HOUR12 ( __HOUR__ ) (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))

Definition at line 75 of file stm32wbxx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_TIME_Init().

#define IS_LL_RTC_HOUR24 ( __HOUR__ ) ((__HOUR__) <= 23U)

Definition at line 76 of file stm32wbxx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_TIME_Init().

#define IS_LL_RTC_HOURFORMAT ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_HOURFORMAT_24HOUR) \
                                      || ((__VALUE__) == LL_RTC_HOURFORMAT_AMPM))

Definition at line 62 of file stm32wbxx_ll_rtc.c.

Referenced by LL_RTC_Init().

#define IS_LL_RTC_MINUTES ( __MINUTES__ ) ((__MINUTES__) <= 59U)

Definition at line 77 of file stm32wbxx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_TIME_Init().

#define IS_LL_RTC_MONTH ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_MONTH_JANUARY) \
                                 || ((__VALUE__) == LL_RTC_MONTH_FEBRUARY) \
                                 || ((__VALUE__) == LL_RTC_MONTH_MARCH) \
                                 || ((__VALUE__) == LL_RTC_MONTH_APRIL) \
                                 || ((__VALUE__) == LL_RTC_MONTH_MAY) \
                                 || ((__VALUE__) == LL_RTC_MONTH_JUNE) \
                                 || ((__VALUE__) == LL_RTC_MONTH_JULY) \
                                 || ((__VALUE__) == LL_RTC_MONTH_AUGUST) \
                                 || ((__VALUE__) == LL_RTC_MONTH_SEPTEMBER) \
                                 || ((__VALUE__) == LL_RTC_MONTH_OCTOBER) \
                                 || ((__VALUE__) == LL_RTC_MONTH_NOVEMBER) \
                                 || ((__VALUE__) == LL_RTC_MONTH_DECEMBER))

Definition at line 90 of file stm32wbxx_ll_rtc.c.

Referenced by LL_RTC_DATE_Init().

#define IS_LL_RTC_SECONDS ( __SECONDS__ ) ((__SECONDS__) <= 59U)

Definition at line 78 of file stm32wbxx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_TIME_Init().

#define IS_LL_RTC_SYNCH_PREDIV ( __VALUE__ ) ((__VALUE__) <= 0x7FFFU)

Definition at line 67 of file stm32wbxx_ll_rtc.c.

Referenced by LL_RTC_Init().

#define IS_LL_RTC_TIME_FORMAT ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_TIME_FORMAT_AM_OR_24) \
                                       || ((__VALUE__) == LL_RTC_TIME_FORMAT_PM))

Definition at line 72 of file stm32wbxx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_TIME_Init().

#define IS_LL_RTC_WEEKDAY ( __VALUE__ )
Value:
(((__VALUE__) == LL_RTC_WEEKDAY_MONDAY) \
                                   || ((__VALUE__) == LL_RTC_WEEKDAY_TUESDAY) \
                                   || ((__VALUE__) == LL_RTC_WEEKDAY_WEDNESDAY) \
                                   || ((__VALUE__) == LL_RTC_WEEKDAY_THURSDAY) \
                                   || ((__VALUE__) == LL_RTC_WEEKDAY_FRIDAY) \
                                   || ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \
                                   || ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY))

Definition at line 80 of file stm32wbxx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_DATE_Init().

#define IS_LL_RTC_YEAR ( __YEAR__ ) ((__YEAR__) <= 99U)

Definition at line 103 of file stm32wbxx_ll_rtc.c.

Referenced by LL_RTC_DATE_Init().

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LL_RTC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_RTC_InitTypeDef Struct Reference
RTC Exported Init structure

RTC Init structures definition. More...

#include <stm32wbxx_ll_rtc.h>

Data Fields

uint32_t | HourFormat
uint32_t | AsynchPrescaler
uint32_t | SynchPrescaler

Detailed Description

RTC Init structures definition.

Definition at line 83 of file stm32wbxx_ll_rtc.h.

Field Documentation

uint32_t LL_RTC_InitTypeDef::AsynchPrescaler

Specifies the RTC Asynchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F

This feature can be modified afterwards using unitary function LL_RTC_SetAsynchPrescaler().

Definition at line 91 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_Init(), and LL_RTC_StructInit().

uint32_t LL_RTC_InitTypeDef::HourFormat

Specifies the RTC Hours Format. This parameter can be a value of HOUR FORMAT

This feature can be modified afterwards using unitary function LL_RTC_SetHourFormat().

Definition at line 85 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_Init(), and LL_RTC_StructInit().

uint32_t LL_RTC_InitTypeDef::SynchPrescaler

Specifies the RTC Synchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF

This feature can be modified afterwards using unitary function LL_RTC_SetSynchPrescaler().

Definition at line 97 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_Init(), and LL_RTC_StructInit().

The documentation for this struct was generated from the following file:
  • stm32wbxx_ll_rtc.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LL_RTC_TimeTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_RTC_TimeTypeDef Struct Reference
RTC Exported Init structure

RTC Time structure definition. More...

#include <stm32wbxx_ll_rtc.h>

Data Fields

uint32_t | TimeFormat
uint8_t | Hours
uint8_t | Minutes
uint8_t | Seconds

Detailed Description

RTC Time structure definition.

Definition at line 107 of file stm32wbxx_ll_rtc.h.

Field Documentation

uint8_t LL_RTC_TimeTypeDef::Hours

Specifies the RTC Time Hours. This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the LL_RTC_TIME_FORMAT_PM is selected. This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the LL_RTC_TIME_FORMAT_AM_OR_24 is selected.

This feature can be modified afterwards using unitary function LL_RTC_TIME_SetHour().

Definition at line 114 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), LL_RTC_ALMB_StructInit(), LL_RTC_TIME_Init(), and LL_RTC_TIME_StructInit().

uint8_t LL_RTC_TimeTypeDef::Minutes

Specifies the RTC Time Minutes. This parameter must be a number between Min_Data = 0 and Max_Data = 59

This feature can be modified afterwards using unitary function LL_RTC_TIME_SetMinute().

Definition at line 120 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), LL_RTC_ALMB_StructInit(), LL_RTC_TIME_Init(), and LL_RTC_TIME_StructInit().

uint8_t LL_RTC_TimeTypeDef::Seconds

Specifies the RTC Time Seconds. This parameter must be a number between Min_Data = 0 and Max_Data = 59

This feature can be modified afterwards using unitary function LL_RTC_TIME_SetSecond().

Definition at line 125 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), LL_RTC_ALMB_StructInit(), LL_RTC_TIME_Init(), and LL_RTC_TIME_StructInit().

uint32_t LL_RTC_TimeTypeDef::TimeFormat

Specifies the RTC AM/PM Time. This parameter can be a value of TIME FORMAT

This feature can be modified afterwards using unitary function LL_RTC_TIME_SetFormat().

Definition at line 109 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), LL_RTC_ALMB_StructInit(), LL_RTC_TIME_Init(), and LL_RTC_TIME_StructInit().

The documentation for this struct was generated from the following file:
  • stm32wbxx_ll_rtc.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LL_RTC_DateTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_RTC_DateTypeDef Struct Reference
RTC Exported Init structure

RTC Date structure definition. More...

#include <stm32wbxx_ll_rtc.h>

Data Fields

uint8_t | WeekDay
uint8_t | Month
uint8_t | Day
uint8_t | Year

Detailed Description

RTC Date structure definition.

Definition at line 134 of file stm32wbxx_ll_rtc.h.

Field Documentation

uint8_t LL_RTC_DateTypeDef::Day

Specifies the RTC Date Day. This parameter must be a number between Min_Data = 1 and Max_Data = 31

This feature can be modified afterwards using unitary function LL_RTC_DATE_SetDay().

Definition at line 146 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init(), and LL_RTC_DATE_StructInit().

uint8_t LL_RTC_DateTypeDef::Month

Specifies the RTC Date Month. This parameter can be a value of MONTH

This feature can be modified afterwards using unitary function LL_RTC_DATE_SetMonth().

Definition at line 141 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init(), and LL_RTC_DATE_StructInit().

uint8_t LL_RTC_DateTypeDef::WeekDay

Specifies the RTC Date WeekDay. This parameter can be a value of WEEK DAY

This feature can be modified afterwards using unitary function LL_RTC_DATE_SetWeekDay().

Definition at line 136 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init(), and LL_RTC_DATE_StructInit().

uint8_t LL_RTC_DateTypeDef::Year

Specifies the RTC Date Year. This parameter must be a number between Min_Data = 0 and Max_Data = 99

This feature can be modified afterwards using unitary function LL_RTC_DATE_SetYear().

Definition at line 151 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init(), and LL_RTC_DATE_StructInit().

The documentation for this struct was generated from the following file:
  • stm32wbxx_ll_rtc.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LL_RTC_AlarmTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_RTC_AlarmTypeDef Struct Reference
RTC Exported Init structure

RTC Alarm structure definition. More...

#include <stm32wbxx_ll_rtc.h>

Data Fields

LL_RTC_TimeTypeDef AlarmTime
uint32_t | AlarmMask
uint32_t | AlarmDateWeekDaySel
uint8_t | AlarmDateWeekDay

Detailed Description

RTC Alarm structure definition.

Definition at line 160 of file stm32wbxx_ll_rtc.h.

Field Documentation

uint8_t LL_RTC_AlarmTypeDef::AlarmDateWeekDay

Specifies the RTC Alarm Day/WeekDay. If AlarmDateWeekDaySel set to day, this parameter must be a number between Min_Data = 1 and Max_Data = 31.

This feature can be modified afterwards using unitary function LL_RTC_ALMA_SetDay() for ALARM A or LL_RTC_ALMB_SetDay() for ALARM B.

If AlarmDateWeekDaySel set to Weekday, this parameter can be a value of WEEK DAY.

This feature can be modified afterwards using unitary function LL_RTC_ALMA_SetWeekDay() for ALARM A or LL_RTC_ALMB_SetWeekDay() for ALARM B.

Definition at line 178 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), and LL_RTC_ALMB_StructInit().

uint32_t LL_RTC_AlarmTypeDef::AlarmDateWeekDaySel

Specifies the RTC Alarm is on day or WeekDay. This parameter can be a value of RTC Alarm A Date WeekDay for ALARM A or RTC Alarm B Date WeekDay for ALARM B

This feature can be modified afterwards using unitary function LL_RTC_ALMA_EnableWeekday() or LL_RTC_ALMA_DisableWeekday() for ALARM A or LL_RTC_ALMB_EnableWeekday() or LL_RTC_ALMB_DisableWeekday() for ALARM B

Definition at line 171 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), and LL_RTC_ALMB_StructInit().

uint32_t LL_RTC_AlarmTypeDef::AlarmMask

Specifies the RTC Alarm Masks. This parameter can be a value of ALARMA MASK for ALARM A or ALARMB MASK for ALARM B.

This feature can be modified afterwards using unitary function LL_RTC_ALMA_SetMask() for ALARM A or LL_RTC_ALMB_SetMask() for ALARM B

Definition at line 164 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), and LL_RTC_ALMB_StructInit().

LL_RTC_TimeTypeDef LL_RTC_AlarmTypeDef::AlarmTime

Specifies the RTC Alarm Time members.

Definition at line 162 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMA_StructInit(), LL_RTC_ALMB_Init(), and LL_RTC_ALMB_StructInit().

The documentation for this struct was generated from the following file:
  • stm32wbxx_ll_rtc.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FORMAT

Defines
FORMAT
RTC Exported Constants

Defines

#define | LL_RTC_FORMAT_BIN 0x000000000U
#define | LL_RTC_FORMAT_BCD 0x000000001U

Define Documentation

#define LL_RTC_FORMAT_BCD 0x000000001U

BCD data format

Definition at line 206 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_FORMAT_BIN 0x000000000U

Binary data format

Definition at line 205 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), and LL_RTC_TIME_Init().

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC Alarm A Date WeekDay

Defines
RTC Alarm A Date WeekDay
RTC Exported Constants

Defines

#define | LL_RTC_ALMA_DATEWEEKDAYSEL_DATE 0x00000000U
#define | LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL

Define Documentation

#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE 0x00000000U

Alarm A Date is selected

Definition at line 214 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), and LL_RTC_ALMA_StructInit().

#define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL

Alarm A WeekDay is selected

Definition at line 215 of file stm32wbxx_ll_rtc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC Alarm B Date WeekDay

Defines
RTC Alarm B Date WeekDay
RTC Exported Constants

Defines

#define | LL_RTC_ALMB_DATEWEEKDAYSEL_DATE 0x00000000U
#define | LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL

Define Documentation

#define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE 0x00000000U

Alarm B Date is selected

Definition at line 223 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_ALMB_Init(), and LL_RTC_ALMB_StructInit().

#define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL

Alarm B WeekDay is selected

Definition at line 224 of file stm32wbxx_ll_rtc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
RTC Exported Constants

Flags defines which can be used with LL_RTC_ReadReg function. More...

Defines

#define | LL_RTC_ISR_ITSF RTC_ISR_ITSF
#define | LL_RTC_ISR_RECALPF RTC_ISR_RECALPF
#define | LL_RTC_ISR_TAMP3F RTC_ISR_TAMP3F
#define | LL_RTC_ISR_TAMP2F RTC_ISR_TAMP2F
#define | LL_RTC_ISR_TAMP1F RTC_ISR_TAMP1F
#define | LL_RTC_ISR_TSOVF RTC_ISR_TSOVF
#define | LL_RTC_ISR_TSF RTC_ISR_TSF
#define | LL_RTC_ISR_WUTF RTC_ISR_WUTF
#define | LL_RTC_ISR_ALRBF RTC_ISR_ALRBF
#define | LL_RTC_ISR_ALRAF RTC_ISR_ALRAF
#define | LL_RTC_ISR_INITF RTC_ISR_INITF
#define | LL_RTC_ISR_RSF RTC_ISR_RSF
#define | LL_RTC_ISR_INITS RTC_ISR_INITS
#define | LL_RTC_ISR_SHPF RTC_ISR_SHPF
#define | LL_RTC_ISR_WUTWF RTC_ISR_WUTWF
#define | LL_RTC_ISR_ALRBWF RTC_ISR_ALRBWF
#define | LL_RTC_ISR_ALRAWF RTC_ISR_ALRAWF

Detailed Description

Flags defines which can be used with LL_RTC_ReadReg function.

Define Documentation

#define LL_RTC_ISR_ALRAF RTC_ISR_ALRAF

Definition at line 250 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_ISR_ALRAWF RTC_ISR_ALRAWF

Definition at line 257 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_ISR_ALRBF RTC_ISR_ALRBF

Definition at line 249 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_ISR_ALRBWF RTC_ISR_ALRBWF

Definition at line 256 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_ISR_INITF RTC_ISR_INITF

Definition at line 251 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_ISR_INITS RTC_ISR_INITS

Definition at line 253 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_ISR_ITSF RTC_ISR_ITSF

Definition at line 235 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_ISR_RECALPF RTC_ISR_RECALPF

Definition at line 236 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_ISR_RSF RTC_ISR_RSF

Definition at line 252 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_ISR_SHPF RTC_ISR_SHPF

Definition at line 254 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_ISR_TAMP1F RTC_ISR_TAMP1F

Definition at line 244 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_ISR_TAMP2F RTC_ISR_TAMP2F

Definition at line 241 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_ISR_TAMP3F RTC_ISR_TAMP3F

Definition at line 238 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_ISR_TSF RTC_ISR_TSF

Definition at line 247 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_ISR_TSOVF RTC_ISR_TSOVF

Definition at line 246 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_ISR_WUTF RTC_ISR_WUTF

Definition at line 248 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_ISR_WUTWF RTC_ISR_WUTWF

Definition at line 255 of file stm32wbxx_ll_rtc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IT Defines

Defines
IT Defines
RTC Exported Constants

IT defines which can be used with LL_RTC_ReadReg and LL_RTC_WriteReg functions. More...

Defines

#define | LL_RTC_CR_TSIE RTC_CR_TSIE
#define | LL_RTC_CR_WUTIE RTC_CR_WUTIE
#define | LL_RTC_CR_ALRBIE RTC_CR_ALRBIE
#define | LL_RTC_CR_ALRAIE RTC_CR_ALRAIE
#define | LL_RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE
#define | LL_RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE
#define | LL_RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE
#define | LL_RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE

Detailed Description

IT defines which can be used with LL_RTC_ReadReg and LL_RTC_WriteReg functions.

Define Documentation

#define LL_RTC_CR_ALRAIE RTC_CR_ALRAIE

Definition at line 269 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_CR_ALRBIE RTC_CR_ALRBIE

Definition at line 268 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_CR_TSIE RTC_CR_TSIE

Definition at line 266 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_CR_WUTIE RTC_CR_WUTIE

Definition at line 267 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE

Definition at line 277 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE

Definition at line 274 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE

Definition at line 271 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE

Definition at line 279 of file stm32wbxx_ll_rtc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: WEEK DAY

Defines
WEEK DAY
RTC Exported Constants

Defines

#define | LL_RTC_WEEKDAY_MONDAY ((uint8_t)0x01U)
#define | LL_RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U)
#define | LL_RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U)
#define | LL_RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U)
#define | LL_RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U)
#define | LL_RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U)
#define | LL_RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U)

Define Documentation

#define LL_RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U)

Friday

Definition at line 291 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_WEEKDAY_MONDAY ((uint8_t)0x01U)

Monday

Definition at line 287 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_DATE_StructInit().

#define LL_RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U)

Saturday

Definition at line 292 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U)

Sunday

Definition at line 293 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U)

Thrusday

Definition at line 290 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U)

Tuesday

Definition at line 288 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U)

Wednesday

Definition at line 289 of file stm32wbxx_ll_rtc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: MONTH

Defines
MONTH
RTC Exported Constants

Defines

#define | LL_RTC_MONTH_JANUARY ((uint8_t)0x01U)
#define | LL_RTC_MONTH_FEBRUARY ((uint8_t)0x02U)
#define | LL_RTC_MONTH_MARCH ((uint8_t)0x03U)
#define | LL_RTC_MONTH_APRIL ((uint8_t)0x04U)
#define | LL_RTC_MONTH_MAY ((uint8_t)0x05U)
#define | LL_RTC_MONTH_JUNE ((uint8_t)0x06U)
#define | LL_RTC_MONTH_JULY ((uint8_t)0x07U)
#define | LL_RTC_MONTH_AUGUST ((uint8_t)0x08U)
#define | LL_RTC_MONTH_SEPTEMBER ((uint8_t)0x09U)
#define | LL_RTC_MONTH_OCTOBER ((uint8_t)0x10U)
#define | LL_RTC_MONTH_NOVEMBER ((uint8_t)0x11U)
#define | LL_RTC_MONTH_DECEMBER ((uint8_t)0x12U)

Define Documentation

#define LL_RTC_MONTH_APRIL ((uint8_t)0x04U)

April

Definition at line 304 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_MONTH_AUGUST ((uint8_t)0x08U)

August

Definition at line 308 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_MONTH_DECEMBER ((uint8_t)0x12U)

December

Definition at line 312 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_MONTH_FEBRUARY ((uint8_t)0x02U)

February

Definition at line 302 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_MONTH_JANUARY ((uint8_t)0x01U)

January

Definition at line 301 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_DATE_StructInit().

#define LL_RTC_MONTH_JULY ((uint8_t)0x07U)

July

Definition at line 307 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_MONTH_JUNE ((uint8_t)0x06U)

June

Definition at line 306 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_MONTH_MARCH ((uint8_t)0x03U)

March

Definition at line 303 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_MONTH_MAY ((uint8_t)0x05U)

May

Definition at line 305 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_MONTH_NOVEMBER ((uint8_t)0x11U)

November

Definition at line 311 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_MONTH_OCTOBER ((uint8_t)0x10U)

October

Definition at line 310 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_MONTH_SEPTEMBER ((uint8_t)0x09U)

September

Definition at line 309 of file stm32wbxx_ll_rtc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: HOUR FORMAT

Defines
HOUR FORMAT
RTC Exported Constants

Defines

#define | LL_RTC_HOURFORMAT_24HOUR 0x00000000U
#define | LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT

Define Documentation

#define LL_RTC_HOURFORMAT_24HOUR 0x00000000U

24 hour/day format

Definition at line 320 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_StructInit(), and LL_RTC_TIME_Init().

#define LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT

AM/PM hour format

Definition at line 321 of file stm32wbxx_ll_rtc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ALARM OUTPUT

Defines
ALARM OUTPUT
RTC Exported Constants

Defines

#define | LL_RTC_ALARMOUT_DISABLE 0x00000000U
#define | LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0
#define | LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1
#define | LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL

Define Documentation

#define LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0

Alarm A output enabled

Definition at line 330 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1

Alarm B output enabled

Definition at line 331 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_ALARMOUT_DISABLE 0x00000000U

Output disabled

Definition at line 329 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL

Wakeup output enabled

Definition at line 332 of file stm32wbxx_ll_rtc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ALARM OUTPUT TYPE

Defines
ALARM OUTPUT TYPE
RTC Exported Constants

Defines

#define | LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN 0x00000000U
#define | LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL RTC_OR_ALARMOUTTYPE

Define Documentation

#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN 0x00000000U

RTC_ALARM, when mapped on PC13, is open-drain output

Definition at line 340 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL RTC_OR_ALARMOUTTYPE

RTC_ALARM, when mapped on PC13, is push-pull output

Definition at line 341 of file stm32wbxx_ll_rtc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: OUTPUT POLARITY PIN

Defines
OUTPUT POLARITY PIN
RTC Exported Constants

Defines

#define | LL_RTC_OUTPUTPOLARITY_PIN_HIGH 0x00000000U
#define | LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL

Define Documentation

#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH 0x00000000U

Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)

Definition at line 349 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL

Pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)

Definition at line 350 of file stm32wbxx_ll_rtc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIME FORMAT

Defines
TIME FORMAT
RTC Exported Constants

Defines

#define | LL_RTC_TIME_FORMAT_AM_OR_24 0x00000000U
#define | LL_RTC_TIME_FORMAT_PM RTC_TR_PM

Define Documentation

#define LL_RTC_TIME_FORMAT_AM_OR_24 0x00000000U

AM or 24-hour format

Definition at line 358 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_TIME_StructInit().

#define LL_RTC_TIME_FORMAT_PM RTC_TR_PM

PM

Definition at line 359 of file stm32wbxx_ll_rtc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SHIFT SECOND

Defines
SHIFT SECOND
RTC Exported Constants

Defines

#define | LL_RTC_SHIFT_SECOND_DELAY 0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */
#define | LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */

Define Documentation

#define LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */

Definition at line 368 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_SHIFT_SECOND_DELAY 0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */

Definition at line 367 of file stm32wbxx_ll_rtc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ALARMA MASK

Defines
ALARMA MASK
RTC Exported Constants

Defines

#define | LL_RTC_ALMA_MASK_NONE 0x00000000U
#define | LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define | LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3
#define | LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2
#define | LL_RTC_ALMA_MASK_SECONDS RTC_ALRMAR_MSK1
#define | LL_RTC_ALMA_MASK_ALL (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1)

Define Documentation

#define LL_RTC_ALMA_MASK_ALL (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1)

Masks all

Definition at line 381 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4

Date/day do not care in Alarm A comparison

Definition at line 377 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3

Hours do not care in Alarm A comparison

Definition at line 378 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2

Minutes do not care in Alarm A comparison

Definition at line 379 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_ALMA_MASK_NONE 0x00000000U

No masks applied on Alarm A

Definition at line 376 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_ALMA_StructInit().

#define LL_RTC_ALMA_MASK_SECONDS RTC_ALRMAR_MSK1

Seconds do not care in Alarm A comparison

Definition at line 380 of file stm32wbxx_ll_rtc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ALARMA TIME FORMAT

Defines
ALARMA TIME FORMAT
RTC Exported Constants

Defines

#define | LL_RTC_ALMA_TIME_FORMAT_AM 0x00000000U
#define | LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM

Define Documentation

#define LL_RTC_ALMA_TIME_FORMAT_AM 0x00000000U

AM or 24-hour format

Definition at line 389 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_ALMA_StructInit().

#define LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM

PM

Definition at line 390 of file stm32wbxx_ll_rtc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ALARMB MASK

Defines
ALARMB MASK
RTC Exported Constants

Defines

#define | LL_RTC_ALMB_MASK_NONE 0x00000000U
#define | LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4
#define | LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3
#define | LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2
#define | LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1
#define | LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1)

Define Documentation

#define LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1)

Masks all

Definition at line 403 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4

Date/day do not care in Alarm B comparison

Definition at line 399 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3

Hours do not care in Alarm B comparison

Definition at line 400 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2

Minutes do not care in Alarm B comparison

Definition at line 401 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_ALMB_MASK_NONE 0x00000000U

No masks applied on Alarm B

Definition at line 398 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_ALMB_StructInit().

#define LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1

Seconds do not care in Alarm B comparison

Definition at line 402 of file stm32wbxx_ll_rtc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ALARMB TIME FORMAT

Defines
ALARMB TIME FORMAT
RTC Exported Constants

Defines

#define | LL_RTC_ALMB_TIME_FORMAT_AM 0x00000000U
#define | LL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PM

Define Documentation

#define LL_RTC_ALMB_TIME_FORMAT_AM 0x00000000U

AM or 24-hour format

Definition at line 411 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_ALMB_StructInit().

#define LL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PM

PM

Definition at line 412 of file stm32wbxx_ll_rtc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIMESTAMP EDGE

Defines
TIMESTAMP EDGE
RTC Exported Constants

Defines

#define | LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U
#define | LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE

Define Documentation

#define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE

RTC_TS input falling edge generates a time-stamp even

Definition at line 421 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U

RTC_TS input rising edge generates a time-stamp event

Definition at line 420 of file stm32wbxx_ll_rtc.h.

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STM32WB55xx HAL User Manual: TIMESTAMP TIME FORMAT

Defines
TIMESTAMP TIME FORMAT
RTC Exported Constants

Defines

#define | LL_RTC_TS_TIME_FORMAT_AM 0x00000000U
#define | LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM

Define Documentation

#define LL_RTC_TS_TIME_FORMAT_AM 0x00000000U

AM or 24-hour format

Definition at line 429 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM

PM

Definition at line 430 of file stm32wbxx_ll_rtc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TAMPER

Defines
TAMPER
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_1 RTC_TAMPCR_TAMP1E
#define | LL_RTC_TAMPER_2 RTC_TAMPCR_TAMP2E
#define | LL_RTC_TAMPER_3 RTC_TAMPCR_TAMP3E

Define Documentation

#define LL_RTC_TAMPER_1 RTC_TAMPCR_TAMP1E

RTC_TAMP1 input detection

Definition at line 439 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_TAMPER_2 RTC_TAMPCR_TAMP2E

RTC_TAMP2 input detection

Definition at line 443 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_TAMPER_3 RTC_TAMPCR_TAMP3E

RTC_TAMP3 input detection

Definition at line 447 of file stm32wbxx_ll_rtc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TAMPER MASK

Defines
TAMPER MASK
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_MASK_TAMPER1 RTC_TAMPCR_TAMP1MF
#define | LL_RTC_TAMPER_MASK_TAMPER2 RTC_TAMPCR_TAMP2MF
#define | LL_RTC_TAMPER_MASK_TAMPER3 RTC_TAMPCR_TAMP3MF

Define Documentation

#define LL_RTC_TAMPER_MASK_TAMPER1 RTC_TAMPCR_TAMP1MF

Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased

Definition at line 457 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_TAMPER_MASK_TAMPER2 RTC_TAMPCR_TAMP2MF

Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased.

Definition at line 460 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_TAMPER_MASK_TAMPER3 RTC_TAMPCR_TAMP3MF

Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased

Definition at line 463 of file stm32wbxx_ll_rtc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TAMPER NO ERASE

Defines
TAMPER NO ERASE
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_NOERASE_TAMPER1 RTC_TAMPCR_TAMP1NOERASE
#define | LL_RTC_TAMPER_NOERASE_TAMPER2 RTC_TAMPCR_TAMP2NOERASE
#define | LL_RTC_TAMPER_NOERASE_TAMPER3 RTC_TAMPCR_TAMP3NOERASE

Define Documentation

#define LL_RTC_TAMPER_NOERASE_TAMPER1 RTC_TAMPCR_TAMP1NOERASE

Tamper 1 event does not erase the backup registers.

Definition at line 473 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_TAMPER_NOERASE_TAMPER2 RTC_TAMPCR_TAMP2NOERASE

Tamper 2 event does not erase the backup registers.

Definition at line 476 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_TAMPER_NOERASE_TAMPER3 RTC_TAMPCR_TAMP3NOERASE

Tamper 3 event does not erase the backup registers.

Definition at line 479 of file stm32wbxx_ll_rtc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TAMPER DURATION

Defines
TAMPER DURATION
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U
#define | LL_RTC_TAMPER_DURATION_2RTCCLK RTC_TAMPCR_TAMPPRCH_0
#define | LL_RTC_TAMPER_DURATION_4RTCCLK RTC_TAMPCR_TAMPPRCH_1
#define | LL_RTC_TAMPER_DURATION_8RTCCLK RTC_TAMPCR_TAMPPRCH

Define Documentation

#define LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U

Tamper pins are pre-charged before sampling during 1 RTCCLK cycle

Definition at line 489 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_TAMPER_DURATION_2RTCCLK RTC_TAMPCR_TAMPPRCH_0

Tamper pins are pre-charged before sampling during 2 RTCCLK cycles

Definition at line 490 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_TAMPER_DURATION_4RTCCLK RTC_TAMPCR_TAMPPRCH_1

Tamper pins are pre-charged before sampling during 4 RTCCLK cycles

Definition at line 491 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_TAMPER_DURATION_8RTCCLK RTC_TAMPCR_TAMPPRCH

Tamper pins are pre-charged before sampling during 8 RTCCLK cycles

Definition at line 492 of file stm32wbxx_ll_rtc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TAMPER FILTER

Defines
TAMPER FILTER
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U
#define | LL_RTC_TAMPER_FILTER_2SAMPLE RTC_TAMPCR_TAMPFLT_0
#define | LL_RTC_TAMPER_FILTER_4SAMPLE RTC_TAMPCR_TAMPFLT_1
#define | LL_RTC_TAMPER_FILTER_8SAMPLE RTC_TAMPCR_TAMPFLT

Define Documentation

#define LL_RTC_TAMPER_FILTER_2SAMPLE RTC_TAMPCR_TAMPFLT_0

Tamper is activated after 2 consecutive samples at the active level

Definition at line 503 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_TAMPER_FILTER_4SAMPLE RTC_TAMPCR_TAMPFLT_1

Tamper is activated after 4 consecutive samples at the active level

Definition at line 504 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_TAMPER_FILTER_8SAMPLE RTC_TAMPCR_TAMPFLT

Tamper is activated after 8 consecutive samples at the active level.

Definition at line 505 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U

Tamper filter is disabled

Definition at line 502 of file stm32wbxx_ll_rtc.h.

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STM32WB55xx HAL User Manual: TAMPER SAMPLING FREQUENCY DIVIDER

Defines
TAMPER SAMPLING FREQUENCY DIVIDER
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U
#define | LL_RTC_TAMPER_SAMPLFREQDIV_16384 RTC_TAMPCR_TAMPFREQ_0
#define | LL_RTC_TAMPER_SAMPLFREQDIV_8192 RTC_TAMPCR_TAMPFREQ_1
#define | LL_RTC_TAMPER_SAMPLFREQDIV_4096 (RTC_TAMPCR_TAMPFREQ_1 | RTC_TAMPCR_TAMPFREQ_0)
#define | LL_RTC_TAMPER_SAMPLFREQDIV_2048 RTC_TAMPCR_TAMPFREQ_2
#define | LL_RTC_TAMPER_SAMPLFREQDIV_1024 (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_0)
#define | LL_RTC_TAMPER_SAMPLFREQDIV_512 (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_1)
#define | LL_RTC_TAMPER_SAMPLFREQDIV_256 RTC_TAMPCR_TAMPFREQ

Define Documentation

#define LL_RTC_TAMPER_SAMPLFREQDIV_1024 (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_0)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024

Definition at line 520 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_16384 RTC_TAMPCR_TAMPFREQ_0

Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384

Definition at line 516 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_2048 RTC_TAMPCR_TAMPFREQ_2

Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048

Definition at line 519 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_256 RTC_TAMPCR_TAMPFREQ

Each of the tamper inputs are sampled with a frequency = RTCCLK / 256

Definition at line 522 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U

Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768

Definition at line 515 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_4096 (RTC_TAMPCR_TAMPFREQ_1 | RTC_TAMPCR_TAMPFREQ_0)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096

Definition at line 518 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_512 (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_1)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 512

Definition at line 521 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_TAMPER_SAMPLFREQDIV_8192 RTC_TAMPCR_TAMPFREQ_1

Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192

Definition at line 517 of file stm32wbxx_ll_rtc.h.

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STM32WB55xx HAL User Manual: TAMPER ACTIVE LEVEL

Defines
TAMPER ACTIVE LEVEL
RTC Exported Constants

Defines

#define | LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 RTC_TAMPCR_TAMP1TRG
#define | LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 RTC_TAMPCR_TAMP2TRG
#define | LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 RTC_TAMPCR_TAMP3TRG

Define Documentation

#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 RTC_TAMPCR_TAMP1TRG

RTC_TAMP1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event

Definition at line 532 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 RTC_TAMPCR_TAMP2TRG

RTC_TAMP2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event

Definition at line 535 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 RTC_TAMPCR_TAMP3TRG

RTC_TAMP3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event

Definition at line 538 of file stm32wbxx_ll_rtc.h.

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STM32WB55xx HAL User Manual: WAKEUP CLOCK DIV

Defines
WAKEUP CLOCK DIV
RTC Exported Constants

Defines

#define | LL_RTC_WAKEUPCLOCK_DIV_16 0x00000000U
#define | LL_RTC_WAKEUPCLOCK_DIV_8 (RTC_CR_WUCKSEL_0)
#define | LL_RTC_WAKEUPCLOCK_DIV_4 (RTC_CR_WUCKSEL_1)
#define | LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0)
#define | LL_RTC_WAKEUPCLOCK_CKSPRE (RTC_CR_WUCKSEL_2)
#define | LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1)

Define Documentation

#define LL_RTC_WAKEUPCLOCK_CKSPRE (RTC_CR_WUCKSEL_2)

ck_spre (usually 1 Hz) clock is selected

Definition at line 551 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1)

ck_spre (usually 1 Hz) clock is selected and 2exp16 is added to the WUT counter value

Definition at line 552 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_WAKEUPCLOCK_DIV_16 0x00000000U

RTC/16 clock is selected

Definition at line 547 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0)

RTC/2 clock is selected

Definition at line 550 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_WAKEUPCLOCK_DIV_4 (RTC_CR_WUCKSEL_1)

RTC/4 clock is selected

Definition at line 549 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_WAKEUPCLOCK_DIV_8 (RTC_CR_WUCKSEL_0)

RTC/8 clock is selected

Definition at line 548 of file stm32wbxx_ll_rtc.h.

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STM32WB55xx HAL User Manual: BACKUP

Defines
BACKUP
RTC Exported Constants

Defines

#define | LL_RTC_BKP_DR0 0x00000000U
#define | LL_RTC_BKP_DR1 0x00000001U
#define | LL_RTC_BKP_DR2 0x00000002U
#define | LL_RTC_BKP_DR3 0x00000003U
#define | LL_RTC_BKP_DR4 0x00000004U
#define | LL_RTC_BKP_DR5 0x00000005U
#define | LL_RTC_BKP_DR6 0x00000006U
#define | LL_RTC_BKP_DR7 0x00000007U
#define | LL_RTC_BKP_DR8 0x00000008U
#define | LL_RTC_BKP_DR9 0x00000009U
#define | LL_RTC_BKP_DR10 0x0000000AU
#define | LL_RTC_BKP_DR11 0x0000000BU
#define | LL_RTC_BKP_DR12 0x0000000CU
#define | LL_RTC_BKP_DR13 0x0000000DU
#define | LL_RTC_BKP_DR14 0x0000000EU
#define | LL_RTC_BKP_DR15 0x0000000FU
#define | LL_RTC_BKP_DR16 0x00000010U
#define | LL_RTC_BKP_DR17 0x00000011U
#define | LL_RTC_BKP_DR18 0x00000012U
#define | LL_RTC_BKP_DR19 0x00000013U

Define Documentation

#define LL_RTC_BKP_DR0 0x00000000U

Definition at line 561 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_BKP_DR1 0x00000001U

Definition at line 562 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_BKP_DR10 0x0000000AU

Definition at line 572 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_BKP_DR11 0x0000000BU

Definition at line 573 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_BKP_DR12 0x0000000CU

Definition at line 574 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_BKP_DR13 0x0000000DU

Definition at line 575 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_BKP_DR14 0x0000000EU

Definition at line 576 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_BKP_DR15 0x0000000FU

Definition at line 577 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_BKP_DR16 0x00000010U

Definition at line 581 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_BKP_DR17 0x00000011U

Definition at line 582 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_BKP_DR18 0x00000012U

Definition at line 583 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_BKP_DR19 0x00000013U

Definition at line 584 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_BKP_DR2 0x00000002U

Definition at line 563 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_BKP_DR3 0x00000003U

Definition at line 564 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_BKP_DR4 0x00000004U

Definition at line 565 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_BKP_DR5 0x00000005U

Definition at line 567 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_BKP_DR6 0x00000006U

Definition at line 568 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_BKP_DR7 0x00000007U

Definition at line 569 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_BKP_DR8 0x00000008U

Definition at line 570 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_BKP_DR9 0x00000009U

Definition at line 571 of file stm32wbxx_ll_rtc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Calibration output

Defines
Calibration output
RTC Exported Constants

Defines

#define | LL_RTC_CALIB_OUTPUT_NONE 0x00000000U
#define | LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL)
#define | LL_RTC_CALIB_OUTPUT_512HZ (RTC_CR_COE)

Define Documentation

#define LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL)

Calibration output is 512 Hz

Definition at line 595 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_CALIB_OUTPUT_512HZ (RTC_CR_COE)

Calibration output is 1 Hz

Definition at line 596 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_CALIB_OUTPUT_NONE 0x00000000U

Calibration output disabled

Definition at line 594 of file stm32wbxx_ll_rtc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Calibration pulse insertion

Defines
Calibration pulse insertion
RTC Exported Constants

Defines

#define | LL_RTC_CALIB_INSERTPULSE_NONE 0x00000000U
#define | LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP

Define Documentation

#define LL_RTC_CALIB_INSERTPULSE_NONE 0x00000000U

No RTCCLK pulses are added

Definition at line 604 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP

One RTCCLK pulse is effectively inserted every 2exp11 pulses (frequency increased by 488.5 ppm)

Definition at line 605 of file stm32wbxx_ll_rtc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Calibration period

Defines
Calibration period
RTC Exported Constants

Defines

#define | LL_RTC_CALIB_PERIOD_32SEC 0x00000000U
#define | LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16
#define | LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8

Define Documentation

#define LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16

Use a 16-second calibration cycle period

Definition at line 614 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_CALIB_PERIOD_32SEC 0x00000000U

Use a 32-second calibration cycle period

Definition at line 613 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8

Use a 8-second calibration cycle period

Definition at line 615 of file stm32wbxx_ll_rtc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
RTC Exported Macros

Defines

#define | LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in RTC register.
#define | LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in RTC register.

Define Documentation

#define LL_RTC_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in RTC register.

Parameters:
__INSTANCE__ | RTC Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 648 of file stm32wbxx_ll_rtc.h.

#define LL_RTC_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in RTC register.

Parameters:
__INSTANCE__ | RTC Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 640 of file stm32wbxx_ll_rtc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Convert helper Macros

Defines
Convert helper Macros
RTC Exported Macros

Defines

#define | __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))
Helper macro to convert a value from 2 digit decimal format to BCD format.
#define | __LL_RTC_CONVERT_BCD2BIN(__VALUE__) (uint8_t)((((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U ) + ((__VALUE__) & (uint8_t)0x0FU))
Helper macro to convert a value from BCD format to 2 digit decimal format.

Define Documentation

#define __LL_RTC_CONVERT_BCD2BIN ( __VALUE__ ) (uint8_t)((((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U ) + ((__VALUE__) & (uint8_t)0x0FU))

Helper macro to convert a value from BCD format to 2 digit decimal format.

Parameters:
__VALUE__ BCD value to be converted
Return values:
Converted byte

Definition at line 669 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), and LL_RTC_TIME_Init().

#define __LL_RTC_CONVERT_BIN2BCD ( __VALUE__ ) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))

Helper macro to convert a value from 2 digit decimal format to BCD format.

Parameters:
__VALUE__ Byte to be converted
Return values:
Converted byte

Definition at line 662 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), and LL_RTC_TIME_Init().

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Date helper Macros

Defines
Date helper Macros
RTC Exported Macros

Defines

#define | __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)
Helper macro to retrieve weekday.
#define | __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU)
Helper macro to retrieve Year in BCD format.
#define | __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)
Helper macro to retrieve Month in BCD format.
#define | __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)
Helper macro to retrieve Day in BCD format.

Define Documentation

#define __LL_RTC_GET_DAY ( __RTC_DATE__ ) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)

Helper macro to retrieve Day in BCD format.

Parameters:
__RTC_DATE__ Value returned by LL_RTC_DATE_Get
Return values:
Day in BCD format (0x01 . . . 0x31)

Definition at line 724 of file stm32wbxx_ll_rtc.h.

#define __LL_RTC_GET_MONTH ( __RTC_DATE__ ) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)

Helper macro to retrieve Month in BCD format.

Parameters:
__RTC_DATE__ Value returned by LL_RTC_DATE_Get
Return values:
Returned value can be one of the following values:
  • LL_RTC_MONTH_JANUARY
  • LL_RTC_MONTH_FEBRUARY
  • LL_RTC_MONTH_MARCH
  • LL_RTC_MONTH_APRIL
  • LL_RTC_MONTH_MAY
  • LL_RTC_MONTH_JUNE
  • LL_RTC_MONTH_JULY
  • LL_RTC_MONTH_AUGUST
  • LL_RTC_MONTH_SEPTEMBER
  • LL_RTC_MONTH_OCTOBER
  • LL_RTC_MONTH_NOVEMBER
  • LL_RTC_MONTH_DECEMBER

Definition at line 717 of file stm32wbxx_ll_rtc.h.

#define __LL_RTC_GET_WEEKDAY ( __RTC_DATE__ ) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)

Helper macro to retrieve weekday.

Parameters:
__RTC_DATE__ Date returned by LL_RTC_DATE_Get function.
Return values:
Returned value can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY

Definition at line 691 of file stm32wbxx_ll_rtc.h.

#define __LL_RTC_GET_YEAR ( __RTC_DATE__ ) ((__RTC_DATE__) & 0x000000FFU)

Helper macro to retrieve Year in BCD format.

Parameters:
__RTC_DATE__ Value returned by LL_RTC_DATE_Get
Return values:
Year in BCD format (0x00 . . . 0x99)

Definition at line 698 of file stm32wbxx_ll_rtc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Time helper Macros

Defines
Time helper Macros
RTC Exported Macros

Defines

#define | __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)
Helper macro to retrieve hour in BCD format.
#define | __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)
Helper macro to retrieve minute in BCD format.
#define | __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU)
Helper macro to retrieve second in BCD format.

Define Documentation

#define __LL_RTC_GET_HOUR ( __RTC_TIME__ ) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)

Helper macro to retrieve hour in BCD format.

Parameters:
__RTC_TIME__ RTC time returned by LL_RTC_TIME_Get function
Return values:
Hours in BCD format (0x01. . .0x12 or between Min_Data=0x00 and Max_Data=0x23)

Definition at line 739 of file stm32wbxx_ll_rtc.h.

#define __LL_RTC_GET_MINUTE ( __RTC_TIME__ ) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)

Helper macro to retrieve minute in BCD format.

Parameters:
__RTC_TIME__ RTC time returned by LL_RTC_TIME_Get function
Return values:
Minutes in BCD format (0x00. . .0x59)

Definition at line 746 of file stm32wbxx_ll_rtc.h.

#define __LL_RTC_GET_SECOND ( __RTC_TIME__ ) ((__RTC_TIME__) & 0x000000FFU)

Helper macro to retrieve second in BCD format.

Parameters:
__RTC_TIME__ RTC time returned by LL_RTC_TIME_Get function
Return values:
Seconds in format (0x00. . .0x59)

Definition at line 753 of file stm32wbxx_ll_rtc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Configuration

Functions
Configuration
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_SetHourFormat (RTC_TypeDef *RTCx, uint32_t HourFormat)
Set Hours format (24 hour/day or AM/PM hour format)
__STATIC_INLINE uint32_t | LL_RTC_GetHourFormat (RTC_TypeDef *RTCx)
Get Hours format (24 hour/day or AM/PM hour format)
__STATIC_INLINE void | LL_RTC_SetAlarmOutEvent (RTC_TypeDef *RTCx, uint32_t AlarmOutput)
Select the flag to be routed to RTC_ALARM output.
__STATIC_INLINE uint32_t | LL_RTC_GetAlarmOutEvent (RTC_TypeDef *RTCx)
Get the flag to be routed to RTC_ALARM output.
__STATIC_INLINE void | LL_RTC_SetAlarmOutputType (RTC_TypeDef *RTCx, uint32_t Output)
Set RTC_ALARM output type (ALARM in push-pull or open-drain output)
__STATIC_INLINE uint32_t | LL_RTC_GetAlarmOutputType (RTC_TypeDef *RTCx)
Get RTC_ALARM output type (ALARM in push-pull or open-drain output)
__STATIC_INLINE void | LL_RTC_EnableInitMode (RTC_TypeDef *RTCx)
Enable initialization mode.
__STATIC_INLINE void | LL_RTC_DisableInitMode (RTC_TypeDef *RTCx)
Disable initialization mode (Free running mode)
__STATIC_INLINE void | LL_RTC_SetOutputPolarity (RTC_TypeDef *RTCx, uint32_t Polarity)
Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted)
__STATIC_INLINE uint32_t | LL_RTC_GetOutputPolarity (RTC_TypeDef *RTCx)
Get Output polarity.
__STATIC_INLINE void | LL_RTC_EnableShadowRegBypass (RTC_TypeDef *RTCx)
Enable Bypass the shadow registers.
__STATIC_INLINE void | LL_RTC_DisableShadowRegBypass (RTC_TypeDef *RTCx)
Disable Bypass the shadow registers.
__STATIC_INLINE uint32_t | LL_RTC_IsShadowRegBypassEnabled (RTC_TypeDef *RTCx)
Check if Shadow registers bypass is enabled or not.
__STATIC_INLINE void | LL_RTC_EnableRefClock (RTC_TypeDef *RTCx)
Enable RTC_REFIN reference clock detection (50 or 60 Hz)
__STATIC_INLINE void | LL_RTC_DisableRefClock (RTC_TypeDef *RTCx)
Disable RTC_REFIN reference clock detection (50 or 60 Hz)
__STATIC_INLINE void | LL_RTC_SetAsynchPrescaler (RTC_TypeDef *RTCx, uint32_t AsynchPrescaler)
Set Asynchronous prescaler factor.
__STATIC_INLINE void | LL_RTC_SetSynchPrescaler (RTC_TypeDef *RTCx, uint32_t SynchPrescaler)
Set Synchronous prescaler factor.
__STATIC_INLINE uint32_t | LL_RTC_GetAsynchPrescaler (RTC_TypeDef *RTCx)
Get Asynchronous prescaler factor.
__STATIC_INLINE uint32_t | LL_RTC_GetSynchPrescaler (RTC_TypeDef *RTCx)
Get Synchronous prescaler factor.
__STATIC_INLINE void | LL_RTC_EnableWriteProtection (RTC_TypeDef *RTCx)
Enable the write protection for RTC registers.
__STATIC_INLINE void | LL_RTC_DisableWriteProtection (RTC_TypeDef *RTCx)
Disable the write protection for RTC registers.
__STATIC_INLINE void | LL_RTC_EnableOutRemap (RTC_TypeDef *RTCx)
Enable RTC_OUT remap.
__STATIC_INLINE void | LL_RTC_DisableOutRemap (RTC_TypeDef *RTCx)
Disable RTC_OUT remap.

Function Documentation

__STATIC_INLINE void LL_RTC_DisableInitMode ( RTC_TypeDef * RTCx )

Disable initialization mode (Free running mode)

Reference Manual to LL API cross reference:
ISR INIT LL_RTC_DisableInitMode
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 883 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init(), LL_RTC_ExitInitMode(), LL_RTC_Init(), and LL_RTC_TIME_Init().

__STATIC_INLINE void LL_RTC_DisableOutRemap ( RTC_TypeDef * RTCx )

Disable RTC_OUT remap.

Reference Manual to LL API cross reference:
OR OUT_RMP LL_RTC_DisableOutRemap
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1063 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableRefClock ( RTC_TypeDef * RTCx )

Disable RTC_REFIN reference clock detection (50 or 60 Hz)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
Reference Manual to LL API cross reference:
CR REFCKON LL_RTC_DisableRefClock
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 972 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableShadowRegBypass ( RTC_TypeDef * RTCx )

Disable Bypass the shadow registers.

Reference Manual to LL API cross reference:
CR BYPSHAD LL_RTC_DisableShadowRegBypass
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 935 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableWriteProtection ( RTC_TypeDef * RTCx )

Disable the write protection for RTC registers.

Reference Manual to LL API cross reference:
WPR KEY LL_RTC_DisableWriteProtection
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1040 of file stm32wbxx_ll_rtc.h.

References RTC_WRITE_PROTECTION_ENABLE_1, and RTC_WRITE_PROTECTION_ENABLE_2.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), LL_RTC_DeInit(), LL_RTC_Init(), and LL_RTC_TIME_Init().

__STATIC_INLINE void LL_RTC_EnableInitMode ( RTC_TypeDef * RTCx )

Enable initialization mode.

Note:
Initialization mode is used to program time and date register (RTC_TR and RTC_DR) and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset.
Reference Manual to LL API cross reference:
ISR INIT LL_RTC_EnableInitMode
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 871 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_EnterInitMode().

__STATIC_INLINE void LL_RTC_EnableOutRemap ( RTC_TypeDef * RTCx )

Enable RTC_OUT remap.

Reference Manual to LL API cross reference:
OR OUT_RMP LL_RTC_EnableOutRemap
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1052 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableRefClock ( RTC_TypeDef * RTCx )

Enable RTC_REFIN reference clock detection (50 or 60 Hz)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
Reference Manual to LL API cross reference:
CR REFCKON LL_RTC_EnableRefClock
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 959 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableShadowRegBypass ( RTC_TypeDef * RTCx )

Enable Bypass the shadow registers.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR BYPSHAD LL_RTC_EnableShadowRegBypass
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 924 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableWriteProtection ( RTC_TypeDef * RTCx )

Enable the write protection for RTC registers.

Reference Manual to LL API cross reference:
WPR KEY LL_RTC_EnableWriteProtection
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1029 of file stm32wbxx_ll_rtc.h.

References RTC_WRITE_PROTECTION_DISABLE.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), LL_RTC_DeInit(), LL_RTC_Init(), and LL_RTC_TIME_Init().

__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent ( RTC_TypeDef * RTCx )

Get the flag to be routed to RTC_ALARM output.

Reference Manual to LL API cross reference:
CR OSEL LL_RTC_GetAlarmOutEvent
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_ALARMOUT_DISABLE
  • LL_RTC_ALARMOUT_ALMA
  • LL_RTC_ALARMOUT_ALMB
  • LL_RTC_ALARMOUT_WAKEUP

Definition at line 828 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType ( RTC_TypeDef * RTCx )

Get RTC_ALARM output type (ALARM in push-pull or open-drain output)

Note:
used only when RTC_ALARM is mapped on PC13
Reference Manual to LL API cross reference:
OR ALARMOUTTYPE LL_RTC_GetAlarmOutputType
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
  • LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL

Definition at line 857 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler ( RTC_TypeDef * RTCx )

Get Asynchronous prescaler factor.

Reference Manual to LL API cross reference:
PRER PREDIV_A LL_RTC_GetAsynchPrescaler
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data = 0 and Max_Data = 0x7F

Definition at line 1007 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_GetHourFormat ( RTC_TypeDef * RTCx )

Get Hours format (24 hour/day or AM/PM hour format)

Reference Manual to LL API cross reference:
CR FMT LL_RTC_GetHourFormat
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_HOURFORMAT_24HOUR
  • LL_RTC_HOURFORMAT_AMPM

Definition at line 796 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), and LL_RTC_TIME_Init().

__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity ( RTC_TypeDef * RTCx )

Get Output polarity.

Reference Manual to LL API cross reference:
CR POL LL_RTC_GetOutputPolarity
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_OUTPUTPOLARITY_PIN_HIGH
  • LL_RTC_OUTPUTPOLARITY_PIN_LOW

Definition at line 912 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler ( RTC_TypeDef * RTCx )

Get Synchronous prescaler factor.

Reference Manual to LL API cross reference:
PRER PREDIV_S LL_RTC_GetSynchPrescaler
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data = 0 and Max_Data = 0x7FFF

Definition at line 1018 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled ( RTC_TypeDef * RTCx )

Check if Shadow registers bypass is enabled or not.

Reference Manual to LL API cross reference:
CR BYPSHAD LL_RTC_IsShadowRegBypassEnabled
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 946 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init(), and LL_RTC_TIME_Init().

__STATIC_INLINE void LL_RTC_SetAlarmOutEvent | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | AlarmOutput
 | ) |  |

Select the flag to be routed to RTC_ALARM output.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR OSEL LL_RTC_SetAlarmOutEvent
Parameters:
RTCx RTC Instance
AlarmOutput This parameter can be one of the following values:
  • LL_RTC_ALARMOUT_DISABLE
  • LL_RTC_ALARMOUT_ALMA
  • LL_RTC_ALARMOUT_ALMB
  • LL_RTC_ALARMOUT_WAKEUP
Return values:
None

Definition at line 813 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_SetAlarmOutputType | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Output
 | ) |  |

Set RTC_ALARM output type (ALARM in push-pull or open-drain output)

Note:
Used only when RTC_ALARM is mapped on PC13
Reference Manual to LL API cross reference:
OR ALARMOUTTYPE LL_RTC_SetAlarmOutputType
Parameters:
RTCx RTC Instance
Output This parameter can be one of the following values:
  • LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
  • LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
Return values:
None

Definition at line 843 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_SetAsynchPrescaler | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | AsynchPrescaler
 | ) |  |

Set Asynchronous prescaler factor.

Reference Manual to LL API cross reference:
PRER PREDIV_A LL_RTC_SetAsynchPrescaler
Parameters:
RTCx | RTC Instance
AsynchPrescaler | Value between Min_Data = 0 and Max_Data = 0x7F
Return values:
None

Definition at line 984 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_Init().

__STATIC_INLINE void LL_RTC_SetHourFormat | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | HourFormat
 | ) |  |

Set Hours format (24 hour/day or AM/PM hour format)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
Reference Manual to LL API cross reference:
CR FMT LL_RTC_SetHourFormat
Parameters:
RTCx RTC Instance
HourFormat This parameter can be one of the following values:
  • LL_RTC_HOURFORMAT_24HOUR
  • LL_RTC_HOURFORMAT_AMPM
Return values:
None

Definition at line 783 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_Init().

__STATIC_INLINE void LL_RTC_SetOutputPolarity | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Polarity
 | ) |  |

Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR POL LL_RTC_SetOutputPolarity
Parameters:
RTCx RTC Instance
Polarity This parameter can be one of the following values:
  • LL_RTC_OUTPUTPOLARITY_PIN_HIGH
  • LL_RTC_OUTPUTPOLARITY_PIN_LOW
Return values:
None

Definition at line 899 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_SetSynchPrescaler | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | SynchPrescaler
 | ) |  |

Set Synchronous prescaler factor.

Reference Manual to LL API cross reference:
PRER PREDIV_S LL_RTC_SetSynchPrescaler
Parameters:
RTCx | RTC Instance
SynchPrescaler | Value between Min_Data = 0 and Max_Data = 0x7FFF
Return values:
None

Definition at line 996 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_Init().

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Time

Functions
Time
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_TIME_SetFormat (RTC_TypeDef *RTCx, uint32_t TimeFormat)
Set time format (AM/24-hour or PM notation)
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetFormat (RTC_TypeDef *RTCx)
Get time format (AM or PM notation)
__STATIC_INLINE void | LL_RTC_TIME_SetHour (RTC_TypeDef *RTCx, uint32_t Hours)
Set Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetHour (RTC_TypeDef *RTCx)
Get Hours in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_SetMinute (RTC_TypeDef *RTCx, uint32_t Minutes)
Set Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetMinute (RTC_TypeDef *RTCx)
Get Minutes in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_SetSecond (RTC_TypeDef *RTCx, uint32_t Seconds)
Set Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetSecond (RTC_TypeDef *RTCx)
Get Seconds in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_Config (RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
Set time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_Get (RTC_TypeDef *RTCx)
Get time (hour, minute and second) in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_EnableDayLightStore (RTC_TypeDef *RTCx)
Memorize whether the daylight saving time change has been performed.
__STATIC_INLINE void | LL_RTC_TIME_DisableDayLightStore (RTC_TypeDef *RTCx)
Disable memorization whether the daylight saving time change has been performed.
__STATIC_INLINE uint32_t | LL_RTC_TIME_IsDayLightStoreEnabled (RTC_TypeDef *RTCx)
Check if RTC Day Light Saving stored operation has been enabled or not.
__STATIC_INLINE void | LL_RTC_TIME_DecHour (RTC_TypeDef *RTCx)
Subtract 1 hour (winter time change)
__STATIC_INLINE void | LL_RTC_TIME_IncHour (RTC_TypeDef *RTCx)
Add 1 hour (summer time change)
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetSubSecond (RTC_TypeDef *RTCx)
Get Sub second value in the synchronous prescaler counter.
__STATIC_INLINE void | LL_RTC_TIME_Synchronize (RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction)
Synchronize to a remote clock with a high degree of precision.

Function Documentation

__STATIC_INLINE void LL_RTC_TIME_Config | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Format12_24,
 |  | uint32_t | Hours,
 |  | uint32_t | Minutes,
 |  | uint32_t | Seconds
 | ) |  |

Set time (hour, minute and second) in BCD format.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
TimeFormat and Hours should follow the same format
Reference Manual to LL API cross reference:
TR PM LL_RTC_TIME_Config
TR HT LL_RTC_TIME_Config
TR HU LL_RTC_TIME_Config
TR MNT LL_RTC_TIME_Config
TR MNU LL_RTC_TIME_Config
TR ST LL_RTC_TIME_Config
TR SU LL_RTC_TIME_Config
Parameters:
RTCx | RTC Instance
Format12_24 This parameter can be one of the following values:
  • LL_RTC_TIME_FORMAT_AM_OR_24
  • LL_RTC_TIME_FORMAT_PM
Hours | Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
Minutes | Value between Min_Data=0x00 and Max_Data=0x59
Seconds | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 1244 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_TIME_Init().

__STATIC_INLINE void LL_RTC_TIME_DecHour ( RTC_TypeDef * RTCx )

Subtract 1 hour (winter time change)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR SUB1H LL_RTC_TIME_DecHour
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1324 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore ( RTC_TypeDef * RTCx )

Disable memorization whether the daylight saving time change has been performed.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR BKP LL_RTC_TIME_DisableDayLightStore
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1301 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore ( RTC_TypeDef * RTCx )

Memorize whether the daylight saving time change has been performed.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR BKP LL_RTC_TIME_EnableDayLightStore
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1289 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TIME_Get ( RTC_TypeDef * RTCx )

Get time (hour, minute and second) in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND are available to get independently each parameter.
Reference Manual to LL API cross reference:
TR HT LL_RTC_TIME_Get
TR HU LL_RTC_TIME_Get
TR MNT LL_RTC_TIME_Get
TR MNU LL_RTC_TIME_Get
TR ST LL_RTC_TIME_Get
TR SU LL_RTC_TIME_Get
Parameters:
RTCx RTC Instance
Return values:
Combination of hours, minutes and seconds (Format: 0x00HHMMSS).

Definition at line 1272 of file stm32wbxx_ll_rtc.h.

References RTC_OFFSET_HOUR, and RTC_OFFSET_MINUTE.

__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat ( RTC_TypeDef * RTCx )

Get time format (AM or PM notation)

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
Reference Manual to LL API cross reference:
TR PM LL_RTC_TIME_GetFormat
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_TIME_FORMAT_AM_OR_24
  • LL_RTC_TIME_FORMAT_PM

Definition at line 1104 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour ( RTC_TypeDef * RTCx )

Get Hours in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert hour from BCD to Binary format
Reference Manual to LL API cross reference:
TR HT LL_RTC_TIME_GetHour
TR HU LL_RTC_TIME_GetHour
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23

Definition at line 1139 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute ( RTC_TypeDef * RTCx )

Get Minutes in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert minute from BCD to Binary format
Reference Manual to LL API cross reference:
TR MNT LL_RTC_TIME_GetMinute
TR MNU LL_RTC_TIME_GetMinute
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 1177 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond ( RTC_TypeDef * RTCx )

Get Seconds in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
Reference Manual to LL API cross reference:
TR ST LL_RTC_TIME_GetSecond
TR SU LL_RTC_TIME_GetSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 1215 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond ( RTC_TypeDef * RTCx )

Get Sub second value in the synchronous prescaler counter.

Note:
You can use both SubSeconds value and SecondFraction (PREDIV_S through LL_RTC_GetSynchPrescaler function) terms returned to convert Calendar SubSeconds value in second fraction ratio with time unit following generic formula: ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS.
Reference Manual to LL API cross reference:
SSR SS LL_RTC_TIME_GetSubSecond
Parameters:
RTCx RTC Instance
Return values:
Sub second value (number between 0 and 65535)

Definition at line 1354 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_IncHour ( RTC_TypeDef * RTCx )

Add 1 hour (summer time change)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR ADD1H LL_RTC_TIME_IncHour
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1336 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled ( RTC_TypeDef * RTCx )

Check if RTC Day Light Saving stored operation has been enabled or not.

Reference Manual to LL API cross reference:
CR BKP LL_RTC_TIME_IsDayLightStoreEnabled
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 1312 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_SetFormat | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | TimeFormat
 | ) |  |

Set time format (AM/24-hour or PM notation)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
Reference Manual to LL API cross reference:
TR PM LL_RTC_TIME_SetFormat
Parameters:
RTCx RTC Instance
TimeFormat This parameter can be one of the following values:
  • LL_RTC_TIME_FORMAT_AM_OR_24
  • LL_RTC_TIME_FORMAT_PM
Return values:
None

Definition at line 1087 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_SetHour | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Hours
 | ) |  |

Set Hours in BCD format.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert hour from binary to BCD format
Reference Manual to LL API cross reference:
TR HT LL_RTC_TIME_SetHour
TR HU LL_RTC_TIME_SetHour
Parameters:
RTCx | RTC Instance
Hours | Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
Return values:
None

Definition at line 1120 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_SetMinute | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Minutes
 | ) |  |

Set Minutes in BCD format.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
Reference Manual to LL API cross reference:
TR MNT LL_RTC_TIME_SetMinute
TR MNU LL_RTC_TIME_SetMinute
Parameters:
RTCx | RTC Instance
Minutes | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 1158 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_SetSecond | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Seconds
 | ) |  |

Set Seconds in BCD format.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
It can be written in initialization mode only (LL_RTC_EnableInitMode function)
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
Reference Manual to LL API cross reference:
TR ST LL_RTC_TIME_SetSecond
TR SU LL_RTC_TIME_SetSecond
Parameters:
RTCx | RTC Instance
Seconds | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 1196 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TIME_Synchronize | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | ShiftSecond,
 |  | uint32_t | Fraction
 | ) |  |

Synchronize to a remote clock with a high degree of precision.

Note:
This operation effectively subtracts from (delays) or advance the clock of a fraction of a second.
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
When REFCKON is set, firmware must not write to Shift control register.
Reference Manual to LL API cross reference:
SHIFTR ADD1S LL_RTC_TIME_Synchronize
SHIFTR SUBFS LL_RTC_TIME_Synchronize
Parameters:
RTCx | RTC Instance
ShiftSecond This parameter can be one of the following values:
  • LL_RTC_SHIFT_SECOND_DELAY
  • LL_RTC_SHIFT_SECOND_ADVANCE
Fraction | Number of Seconds Fractions (any value from 0 to 0x7FFF)
Return values:
None

Definition at line 1373 of file stm32wbxx_ll_rtc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Date

Functions
Date
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_DATE_SetYear (RTC_TypeDef *RTCx, uint32_t Year)
Set Year in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetYear (RTC_TypeDef *RTCx)
Get Year in BCD format.
__STATIC_INLINE void | LL_RTC_DATE_SetWeekDay (RTC_TypeDef *RTCx, uint32_t WeekDay)
Set Week day.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetWeekDay (RTC_TypeDef *RTCx)
Get Week day.
__STATIC_INLINE void | LL_RTC_DATE_SetMonth (RTC_TypeDef *RTCx, uint32_t Month)
Set Month in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetMonth (RTC_TypeDef *RTCx)
Get Month in BCD format.
__STATIC_INLINE void | LL_RTC_DATE_SetDay (RTC_TypeDef *RTCx, uint32_t Day)
Set Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetDay (RTC_TypeDef *RTCx)
Get Day in BCD format.
__STATIC_INLINE void | LL_RTC_DATE_Config (RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year)
Set date (WeekDay, Day, Month and Year) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_Get (RTC_TypeDef *RTCx)
Get date (WeekDay, Day, Month and Year) in BCD format.

Function Documentation

__STATIC_INLINE void LL_RTC_DATE_Config | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | WeekDay,
 |  | uint32_t | Day,
 |  | uint32_t | Month,
 |  | uint32_t | Year
 | ) |  |

Set date (WeekDay, Day, Month and Year) in BCD format.

Reference Manual to LL API cross reference:
DR WDU LL_RTC_DATE_Config
DR MT LL_RTC_DATE_Config
DR MU LL_RTC_DATE_Config
DR DT LL_RTC_DATE_Config
DR DU LL_RTC_DATE_Config
DR YT LL_RTC_DATE_Config
DR YU LL_RTC_DATE_Config
Parameters:
RTCx | RTC Instance
WeekDay This parameter can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY
Day | Value between Min_Data=0x01 and Max_Data=0x31
Month This parameter can be one of the following values:
  • LL_RTC_MONTH_JANUARY
  • LL_RTC_MONTH_FEBRUARY
  • LL_RTC_MONTH_MARCH
  • LL_RTC_MONTH_APRIL
  • LL_RTC_MONTH_MAY
  • LL_RTC_MONTH_JUNE
  • LL_RTC_MONTH_JULY
  • LL_RTC_MONTH_AUGUST
  • LL_RTC_MONTH_SEPTEMBER
  • LL_RTC_MONTH_OCTOBER
  • LL_RTC_MONTH_NOVEMBER
  • LL_RTC_MONTH_DECEMBER
Year | Value between Min_Data=0x00 and Max_Data=0x99
Return values:
None

Definition at line 1583 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_DATE_Init().

__STATIC_INLINE uint32_t LL_RTC_DATE_Get ( RTC_TypeDef * RTCx )

Get date (WeekDay, Day, Month and Year) in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH, and __LL_RTC_GET_DAY are available to get independently each parameter.
Reference Manual to LL API cross reference:
DR WDU LL_RTC_DATE_Get
DR MT LL_RTC_DATE_Get
DR MU LL_RTC_DATE_Get
DR DT LL_RTC_DATE_Get
DR DU LL_RTC_DATE_Get
DR YT LL_RTC_DATE_Get
DR YU LL_RTC_DATE_Get
Parameters:
RTCx RTC Instance
Return values:
Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY).

Definition at line 1611 of file stm32wbxx_ll_rtc.h.

References RTC_OFFSET_DAY, RTC_OFFSET_MONTH, and RTC_OFFSET_WEEKDAY.

__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay ( RTC_TypeDef * RTCx )

Get Day in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
Reference Manual to LL API cross reference:
DR DT LL_RTC_DATE_GetDay
DR DU LL_RTC_DATE_GetDay
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x31

Definition at line 1540 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth ( RTC_TypeDef * RTCx )

Get Month in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
Reference Manual to LL API cross reference:
DR MT LL_RTC_DATE_GetMonth
DR MU LL_RTC_DATE_GetMonth
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_MONTH_JANUARY
  • LL_RTC_MONTH_FEBRUARY
  • LL_RTC_MONTH_MARCH
  • LL_RTC_MONTH_APRIL
  • LL_RTC_MONTH_MAY
  • LL_RTC_MONTH_JUNE
  • LL_RTC_MONTH_JULY
  • LL_RTC_MONTH_AUGUST
  • LL_RTC_MONTH_SEPTEMBER
  • LL_RTC_MONTH_OCTOBER
  • LL_RTC_MONTH_NOVEMBER
  • LL_RTC_MONTH_DECEMBER

Definition at line 1507 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay ( RTC_TypeDef * RTCx )

Get Week day.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
Reference Manual to LL API cross reference:
DR WDU LL_RTC_DATE_GetWeekDay
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY

Definition at line 1453 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear ( RTC_TypeDef * RTCx )

Get Year in BCD format.

Note:
if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set before reading this bit
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format
Reference Manual to LL API cross reference:
DR YT LL_RTC_DATE_GetYear
DR YU LL_RTC_DATE_GetYear
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x99

Definition at line 1411 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DATE_SetDay | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Day
 | ) |  |

Set Day in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
Reference Manual to LL API cross reference:
DR DT LL_RTC_DATE_SetDay
DR DU LL_RTC_DATE_SetDay
Parameters:
RTCx | RTC Instance
Day | Value between Min_Data=0x01 and Max_Data=0x31
Return values:
None

Definition at line 1524 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DATE_SetMonth | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Month
 | ) |  |

Set Month in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Month from binary to BCD format
Reference Manual to LL API cross reference:
DR MT LL_RTC_DATE_SetMonth
DR MU LL_RTC_DATE_SetMonth
Parameters:
RTCx RTC Instance
Month This parameter can be one of the following values:
  • LL_RTC_MONTH_JANUARY
  • LL_RTC_MONTH_FEBRUARY
  • LL_RTC_MONTH_MARCH
  • LL_RTC_MONTH_APRIL
  • LL_RTC_MONTH_MAY
  • LL_RTC_MONTH_JUNE
  • LL_RTC_MONTH_JULY
  • LL_RTC_MONTH_AUGUST
  • LL_RTC_MONTH_SEPTEMBER
  • LL_RTC_MONTH_OCTOBER
  • LL_RTC_MONTH_NOVEMBER
  • LL_RTC_MONTH_DECEMBER
Return values:
None

Definition at line 1479 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DATE_SetWeekDay | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | WeekDay
 | ) |  |

Set Week day.

Reference Manual to LL API cross reference:
DR WDU LL_RTC_DATE_SetWeekDay
Parameters:
RTCx RTC Instance
WeekDay This parameter can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY
Return values:
None

Definition at line 1433 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DATE_SetYear | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Year
 | ) |  |

Set Year in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Year from binary to BCD format
Reference Manual to LL API cross reference:
DR YT LL_RTC_DATE_SetYear
DR YU LL_RTC_DATE_SetYear
Parameters:
RTCx | RTC Instance
Year | Value between Min_Data=0x00 and Max_Data=0x99
Return values:
None

Definition at line 1395 of file stm32wbxx_ll_rtc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ALARMA

Functions
ALARMA
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_ALMA_Enable (RTC_TypeDef *RTCx)
Enable Alarm A.
__STATIC_INLINE void | LL_RTC_ALMA_Disable (RTC_TypeDef *RTCx)
Disable Alarm A.
__STATIC_INLINE void | LL_RTC_ALMA_SetMask (RTC_TypeDef *RTCx, uint32_t Mask)
Specify the Alarm A masks.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetMask (RTC_TypeDef *RTCx)
Get the Alarm A masks.
__STATIC_INLINE void | LL_RTC_ALMA_EnableWeekday (RTC_TypeDef *RTCx)
Enable AlarmA Week day selection (DU[3:0] represents the week day.
__STATIC_INLINE void | LL_RTC_ALMA_DisableWeekday (RTC_TypeDef *RTCx)
Disable AlarmA Week day selection (DU[3:0] represents the date )
__STATIC_INLINE void | LL_RTC_ALMA_SetDay (RTC_TypeDef *RTCx, uint32_t Day)
Set ALARM A Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetDay (RTC_TypeDef *RTCx)
Get ALARM A Day in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetWeekDay (RTC_TypeDef *RTCx, uint32_t WeekDay)
Set ALARM A Weekday.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetWeekDay (RTC_TypeDef *RTCx)
Get ALARM A Weekday.
__STATIC_INLINE void | LL_RTC_ALMA_SetTimeFormat (RTC_TypeDef *RTCx, uint32_t TimeFormat)
Set Alarm A time format (AM/24-hour or PM notation)
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetTimeFormat (RTC_TypeDef *RTCx)
Get Alarm A time format (AM or PM notation)
__STATIC_INLINE void | LL_RTC_ALMA_SetHour (RTC_TypeDef *RTCx, uint32_t Hours)
Set ALARM A Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetHour (RTC_TypeDef *RTCx)
Get ALARM A Hours in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetMinute (RTC_TypeDef *RTCx, uint32_t Minutes)
Set ALARM A Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetMinute (RTC_TypeDef *RTCx)
Get ALARM A Minutes in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetSecond (RTC_TypeDef *RTCx, uint32_t Seconds)
Set ALARM A Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetSecond (RTC_TypeDef *RTCx)
Get ALARM A Seconds in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_ConfigTime (RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
Set Alarm A Time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetTime (RTC_TypeDef *RTCx)
Get Alarm B Time (hour, minute and second) in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetSubSecondMask (RTC_TypeDef *RTCx, uint32_t Mask)
Set Alarm A Mask the most-significant bits starting at this bit.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetSubSecondMask (RTC_TypeDef *RTCx)
Get Alarm A Mask the most-significant bits starting at this bit.
__STATIC_INLINE void | LL_RTC_ALMA_SetSubSecond (RTC_TypeDef *RTCx, uint32_t Subsecond)
Set Alarm A Sub seconds value.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetSubSecond (RTC_TypeDef *RTCx)
Get Alarm A Sub seconds value.

Function Documentation

__STATIC_INLINE void LL_RTC_ALMA_ConfigTime | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Format12_24,
 |  | uint32_t | Hours,
 |  | uint32_t | Minutes,
 |  | uint32_t | Seconds
 | ) |  |

Set Alarm A Time (hour, minute and second) in BCD format.

Reference Manual to LL API cross reference:
ALRMAR PM LL_RTC_ALMA_ConfigTime
ALRMAR HT LL_RTC_ALMA_ConfigTime
ALRMAR HU LL_RTC_ALMA_ConfigTime
ALRMAR MNT LL_RTC_ALMA_ConfigTime
ALRMAR MNU LL_RTC_ALMA_ConfigTime
ALRMAR ST LL_RTC_ALMA_ConfigTime
ALRMAR SU LL_RTC_ALMA_ConfigTime
Parameters:
RTCx | RTC Instance
Format12_24 This parameter can be one of the following values:
  • LL_RTC_ALMA_TIME_FORMAT_AM
  • LL_RTC_ALMA_TIME_FORMAT_PM
Hours | Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
Minutes | Value between Min_Data=0x00 and Max_Data=0x59
Seconds | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 1923 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init().

__STATIC_INLINE void LL_RTC_ALMA_Disable ( RTC_TypeDef * RTCx )

Disable Alarm A.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR ALRAE LL_RTC_ALMA_Disable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1649 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_DisableWeekday ( RTC_TypeDef * RTCx )

Disable AlarmA Week day selection (DU[3:0] represents the date )

Reference Manual to LL API cross reference:
ALRMAR WDSEL LL_RTC_ALMA_DisableWeekday
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1712 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init().

__STATIC_INLINE void LL_RTC_ALMA_Enable ( RTC_TypeDef * RTCx )

Enable Alarm A.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR ALRAE LL_RTC_ALMA_Enable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1637 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_EnableWeekday ( RTC_TypeDef * RTCx )

Enable AlarmA Week day selection (DU[3:0] represents the week day.

DT[1:0] is do not care)

Reference Manual to LL API cross reference:
ALRMAR WDSEL LL_RTC_ALMA_EnableWeekday
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 1701 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init().

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay ( RTC_TypeDef * RTCx )

Get ALARM A Day in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
Reference Manual to LL API cross reference:
ALRMAR DT LL_RTC_ALMA_GetDay
ALRMAR DU LL_RTC_ALMA_GetDay
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x31

Definition at line 1740 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour ( RTC_TypeDef * RTCx )

Get ALARM A Hours in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
Reference Manual to LL API cross reference:
ALRMAR HT LL_RTC_ALMA_GetHour
ALRMAR HU LL_RTC_ALMA_GetHour
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23

Definition at line 1835 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_ALMA_GetTime().

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask ( RTC_TypeDef * RTCx )

Get the Alarm A masks.

Reference Manual to LL API cross reference:
ALRMAR MSK4 LL_RTC_ALMA_GetMask
ALRMAR MSK3 LL_RTC_ALMA_GetMask
ALRMAR MSK2 LL_RTC_ALMA_GetMask
ALRMAR MSK1 LL_RTC_ALMA_GetMask
Parameters:
RTCx RTC Instance
Return values:
Returned value can be can be a combination of the following values:
  • LL_RTC_ALMA_MASK_NONE
  • LL_RTC_ALMA_MASK_DATEWEEKDAY
  • LL_RTC_ALMA_MASK_HOURS
  • LL_RTC_ALMA_MASK_MINUTES
  • LL_RTC_ALMA_MASK_SECONDS
  • LL_RTC_ALMA_MASK_ALL

Definition at line 1690 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute ( RTC_TypeDef * RTCx )

Get ALARM A Minutes in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
Reference Manual to LL API cross reference:
ALRMAR MNT LL_RTC_ALMA_GetMinute
ALRMAR MNU LL_RTC_ALMA_GetMinute
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 1866 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_ALMA_GetTime().

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond ( RTC_TypeDef * RTCx )

Get ALARM A Seconds in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
Reference Manual to LL API cross reference:
ALRMAR ST LL_RTC_ALMA_GetSecond
ALRMAR SU LL_RTC_ALMA_GetSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 1897 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_ALMA_GetTime().

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond ( RTC_TypeDef * RTCx )

Get Alarm A Sub seconds value.

Reference Manual to LL API cross reference:
ALRMASSR SS LL_RTC_ALMA_GetSubSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x7FFF

Definition at line 1995 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask ( RTC_TypeDef * RTCx )

Get Alarm A Mask the most-significant bits starting at this bit.

Reference Manual to LL API cross reference:
ALRMASSR MASKSS LL_RTC_ALMA_GetSubSecondMask
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xF

Definition at line 1972 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime ( RTC_TypeDef * RTCx )

Get Alarm B Time (hour, minute and second) in BCD format.

Note:
helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND are available to get independently each parameter.
Reference Manual to LL API cross reference:
ALRMAR HT LL_RTC_ALMA_GetTime
ALRMAR HU LL_RTC_ALMA_GetTime
ALRMAR MNT LL_RTC_ALMA_GetTime
ALRMAR MNU LL_RTC_ALMA_GetTime
ALRMAR ST LL_RTC_ALMA_GetTime
ALRMAR SU LL_RTC_ALMA_GetTime
Parameters:
RTCx RTC Instance
Return values:
Combination of hours, minutes and seconds.

Definition at line 1947 of file stm32wbxx_ll_rtc.h.

References LL_RTC_ALMA_GetHour(), LL_RTC_ALMA_GetMinute(), LL_RTC_ALMA_GetSecond(), RTC_OFFSET_HOUR, and RTC_OFFSET_MINUTE.

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat ( RTC_TypeDef * RTCx )

Get Alarm A time format (AM or PM notation)

Reference Manual to LL API cross reference:
ALRMAR PM LL_RTC_ALMA_GetTimeFormat
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_ALMA_TIME_FORMAT_AM
  • LL_RTC_ALMA_TIME_FORMAT_PM

Definition at line 1807 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay ( RTC_TypeDef * RTCx )

Get ALARM A Weekday.

Reference Manual to LL API cross reference:
ALRMAR DU LL_RTC_ALMA_GetWeekDay
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY

Definition at line 1780 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_SetDay | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Day
 | ) |  |

Set ALARM A Day in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
Reference Manual to LL API cross reference:
ALRMAR DT LL_RTC_ALMA_SetDay
ALRMAR DU LL_RTC_ALMA_SetDay
Parameters:
RTCx | RTC Instance
Day | Value between Min_Data=0x01 and Max_Data=0x31
Return values:
None

Definition at line 1726 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init().

__STATIC_INLINE void LL_RTC_ALMA_SetHour | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Hours
 | ) |  |

Set ALARM A Hours in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
Reference Manual to LL API cross reference:
ALRMAR HT LL_RTC_ALMA_SetHour
ALRMAR HU LL_RTC_ALMA_SetHour
Parameters:
RTCx | RTC Instance
Hours | Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
Return values:
None

Definition at line 1821 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_SetMask | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Mask
 | ) |  |

Specify the Alarm A masks.

Reference Manual to LL API cross reference:
ALRMAR MSK4 LL_RTC_ALMA_SetMask
ALRMAR MSK3 LL_RTC_ALMA_SetMask
ALRMAR MSK2 LL_RTC_ALMA_SetMask
ALRMAR MSK1 LL_RTC_ALMA_SetMask
Parameters:
RTCx RTC Instance
Mask This parameter can be a combination of the following values:
  • LL_RTC_ALMA_MASK_NONE
  • LL_RTC_ALMA_MASK_DATEWEEKDAY
  • LL_RTC_ALMA_MASK_HOURS
  • LL_RTC_ALMA_MASK_MINUTES
  • LL_RTC_ALMA_MASK_SECONDS
  • LL_RTC_ALMA_MASK_ALL
Return values:
None

Definition at line 1670 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init().

__STATIC_INLINE void LL_RTC_ALMA_SetMinute | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Minutes
 | ) |  |

Set ALARM A Minutes in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
Reference Manual to LL API cross reference:
ALRMAR MNT LL_RTC_ALMA_SetMinute
ALRMAR MNU LL_RTC_ALMA_SetMinute
Parameters:
RTCx | RTC Instance
Minutes | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 1852 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_SetSecond | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Seconds
 | ) |  |

Set ALARM A Seconds in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
Reference Manual to LL API cross reference:
ALRMAR ST LL_RTC_ALMA_SetSecond
ALRMAR SU LL_RTC_ALMA_SetSecond
Parameters:
RTCx | RTC Instance
Seconds | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 1883 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_SetSubSecond | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Subsecond
 | ) |  |

Set Alarm A Sub seconds value.

Reference Manual to LL API cross reference:
ALRMASSR SS LL_RTC_ALMA_SetSubSecond
Parameters:
RTCx | RTC Instance
Subsecond | Value between Min_Data=0x00 and Max_Data=0x7FFF
Return values:
None

Definition at line 1984 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Mask
 | ) |  |

Set Alarm A Mask the most-significant bits starting at this bit.

Note:
This register can be written only when ALRAE is reset in RTC_CR register, or in initialization mode.
Reference Manual to LL API cross reference:
ALRMASSR MASKSS LL_RTC_ALMA_SetSubSecondMask
Parameters:
RTCx | RTC Instance
Mask | Value between Min_Data=0x00 and Max_Data=0xF
Return values:
None

Definition at line 1961 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | TimeFormat
 | ) |  |

Set Alarm A time format (AM/24-hour or PM notation)

Reference Manual to LL API cross reference:
ALRMAR PM LL_RTC_ALMA_SetTimeFormat
Parameters:
RTCx RTC Instance
TimeFormat This parameter can be one of the following values:
  • LL_RTC_ALMA_TIME_FORMAT_AM
  • LL_RTC_ALMA_TIME_FORMAT_PM
Return values:
None

Definition at line 1794 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMA_SetWeekDay | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | WeekDay
 | ) |  |

Set ALARM A Weekday.

Reference Manual to LL API cross reference:
ALRMAR DU LL_RTC_ALMA_SetWeekDay
Parameters:
RTCx RTC Instance
WeekDay This parameter can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY
Return values:
None

Definition at line 1762 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_ALMA_Init().

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ALARMB

Functions
ALARMB
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_ALMB_Enable (RTC_TypeDef *RTCx)
Enable Alarm B.
__STATIC_INLINE void | LL_RTC_ALMB_Disable (RTC_TypeDef *RTCx)
Disable Alarm B.
__STATIC_INLINE void | LL_RTC_ALMB_SetMask (RTC_TypeDef *RTCx, uint32_t Mask)
Specify the Alarm B masks.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetMask (RTC_TypeDef *RTCx)
Get the Alarm B masks.
__STATIC_INLINE void | LL_RTC_ALMB_EnableWeekday (RTC_TypeDef *RTCx)
Enable AlarmB Week day selection (DU[3:0] represents the week day.
__STATIC_INLINE void | LL_RTC_ALMB_DisableWeekday (RTC_TypeDef *RTCx)
Disable AlarmB Week day selection (DU[3:0] represents the date )
__STATIC_INLINE void | LL_RTC_ALMB_SetDay (RTC_TypeDef *RTCx, uint32_t Day)
Set ALARM B Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetDay (RTC_TypeDef *RTCx)
Get ALARM B Day in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetWeekDay (RTC_TypeDef *RTCx, uint32_t WeekDay)
Set ALARM B Weekday.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetWeekDay (RTC_TypeDef *RTCx)
Get ALARM B Weekday.
__STATIC_INLINE void | LL_RTC_ALMB_SetTimeFormat (RTC_TypeDef *RTCx, uint32_t TimeFormat)
Set ALARM B time format (AM/24-hour or PM notation)
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetTimeFormat (RTC_TypeDef *RTCx)
Get ALARM B time format (AM or PM notation)
__STATIC_INLINE void | LL_RTC_ALMB_SetHour (RTC_TypeDef *RTCx, uint32_t Hours)
Set ALARM B Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetHour (RTC_TypeDef *RTCx)
Get ALARM B Hours in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetMinute (RTC_TypeDef *RTCx, uint32_t Minutes)
Set ALARM B Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetMinute (RTC_TypeDef *RTCx)
Get ALARM B Minutes in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetSecond (RTC_TypeDef *RTCx, uint32_t Seconds)
Set ALARM B Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetSecond (RTC_TypeDef *RTCx)
Get ALARM B Seconds in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_ConfigTime (RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
Set Alarm B Time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetTime (RTC_TypeDef *RTCx)
Get Alarm B Time (hour, minute and second) in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetSubSecondMask (RTC_TypeDef *RTCx, uint32_t Mask)
Set Alarm B Mask the most-significant bits starting at this bit.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetSubSecondMask (RTC_TypeDef *RTCx)
Get Alarm B Mask the most-significant bits starting at this bit.
__STATIC_INLINE void | LL_RTC_ALMB_SetSubSecond (RTC_TypeDef *RTCx, uint32_t Subsecond)
Set Alarm B Sub seconds value.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetSubSecond (RTC_TypeDef *RTCx)
Get Alarm B Sub seconds value.

Function Documentation

__STATIC_INLINE void LL_RTC_ALMB_ConfigTime | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Format12_24,
 |  | uint32_t | Hours,
 |  | uint32_t | Minutes,
 |  | uint32_t | Seconds
 | ) |  |

Set Alarm B Time (hour, minute and second) in BCD format.

Reference Manual to LL API cross reference:
ALRMBR PM LL_RTC_ALMB_ConfigTime
ALRMBR HT LL_RTC_ALMB_ConfigTime
ALRMBR HU LL_RTC_ALMB_ConfigTime
ALRMBR MNT LL_RTC_ALMB_ConfigTime
ALRMBR MNU LL_RTC_ALMB_ConfigTime
ALRMBR ST LL_RTC_ALMB_ConfigTime
ALRMBR SU LL_RTC_ALMB_ConfigTime
Parameters:
RTCx | RTC Instance
Format12_24 This parameter can be one of the following values:
  • LL_RTC_ALMB_TIME_FORMAT_AM
  • LL_RTC_ALMB_TIME_FORMAT_PM
Hours | Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
Minutes | Value between Min_Data=0x00 and Max_Data=0x59
Seconds | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 2301 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_ALMB_Init().

__STATIC_INLINE void LL_RTC_ALMB_Disable ( RTC_TypeDef * RTCx )

Disable Alarm B.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR ALRBE LL_RTC_ALMB_Disable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2027 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_DisableWeekday ( RTC_TypeDef * RTCx )

Disable AlarmB Week day selection (DU[3:0] represents the date )

Reference Manual to LL API cross reference:
ALRMBR WDSEL LL_RTC_ALMB_DisableWeekday
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2090 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_ALMB_Init().

__STATIC_INLINE void LL_RTC_ALMB_Enable ( RTC_TypeDef * RTCx )

Enable Alarm B.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR ALRBE LL_RTC_ALMB_Enable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2015 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_EnableWeekday ( RTC_TypeDef * RTCx )

Enable AlarmB Week day selection (DU[3:0] represents the week day.

DT[1:0] is do not care)

Reference Manual to LL API cross reference:
ALRMBR WDSEL LL_RTC_ALMB_EnableWeekday
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2079 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_ALMB_Init().

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay ( RTC_TypeDef * RTCx )

Get ALARM B Day in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
Reference Manual to LL API cross reference:
ALRMBR DT LL_RTC_ALMB_GetDay
ALRMBR DU LL_RTC_ALMB_GetDay
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x31

Definition at line 2118 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour ( RTC_TypeDef * RTCx )

Get ALARM B Hours in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
Reference Manual to LL API cross reference:
ALRMBR HT LL_RTC_ALMB_GetHour
ALRMBR HU LL_RTC_ALMB_GetHour
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23

Definition at line 2213 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_ALMB_GetTime().

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask ( RTC_TypeDef * RTCx )

Get the Alarm B masks.

Reference Manual to LL API cross reference:
ALRMBR MSK4 LL_RTC_ALMB_GetMask
ALRMBR MSK3 LL_RTC_ALMB_GetMask
ALRMBR MSK2 LL_RTC_ALMB_GetMask
ALRMBR MSK1 LL_RTC_ALMB_GetMask
Parameters:
RTCx RTC Instance
Return values:
Returned value can be can be a combination of the following values:
  • LL_RTC_ALMB_MASK_NONE
  • LL_RTC_ALMB_MASK_DATEWEEKDAY
  • LL_RTC_ALMB_MASK_HOURS
  • LL_RTC_ALMB_MASK_MINUTES
  • LL_RTC_ALMB_MASK_SECONDS
  • LL_RTC_ALMB_MASK_ALL

Definition at line 2068 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute ( RTC_TypeDef * RTCx )

Get ALARM B Minutes in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
Reference Manual to LL API cross reference:
ALRMBR MNT LL_RTC_ALMB_GetMinute
ALRMBR MNU LL_RTC_ALMB_GetMinute
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 2244 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_ALMB_GetTime().

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond ( RTC_TypeDef * RTCx )

Get ALARM B Seconds in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
Reference Manual to LL API cross reference:
ALRMBR ST LL_RTC_ALMB_GetSecond
ALRMBR SU LL_RTC_ALMB_GetSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 2275 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_ALMB_GetTime().

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond ( RTC_TypeDef * RTCx )

Get Alarm B Sub seconds value.

Reference Manual to LL API cross reference:
ALRMBSSR SS LL_RTC_ALMB_GetSubSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x7FFF

Definition at line 2373 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask ( RTC_TypeDef * RTCx )

Get Alarm B Mask the most-significant bits starting at this bit.

Reference Manual to LL API cross reference:
ALRMBSSR MASKSS LL_RTC_ALMB_GetSubSecondMask
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xF

Definition at line 2350 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime ( RTC_TypeDef * RTCx )

Get Alarm B Time (hour, minute and second) in BCD format.

Note:
helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND are available to get independently each parameter.
Reference Manual to LL API cross reference:
ALRMBR HT LL_RTC_ALMB_GetTime
ALRMBR HU LL_RTC_ALMB_GetTime
ALRMBR MNT LL_RTC_ALMB_GetTime
ALRMBR MNU LL_RTC_ALMB_GetTime
ALRMBR ST LL_RTC_ALMB_GetTime
ALRMBR SU LL_RTC_ALMB_GetTime
Parameters:
RTCx RTC Instance
Return values:
Combination of hours, minutes and seconds.

Definition at line 2325 of file stm32wbxx_ll_rtc.h.

References LL_RTC_ALMB_GetHour(), LL_RTC_ALMB_GetMinute(), LL_RTC_ALMB_GetSecond(), RTC_OFFSET_HOUR, and RTC_OFFSET_MINUTE.

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat ( RTC_TypeDef * RTCx )

Get ALARM B time format (AM or PM notation)

Reference Manual to LL API cross reference:
ALRMBR PM LL_RTC_ALMB_GetTimeFormat
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_ALMB_TIME_FORMAT_AM
  • LL_RTC_ALMB_TIME_FORMAT_PM

Definition at line 2185 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay ( RTC_TypeDef * RTCx )

Get ALARM B Weekday.

Reference Manual to LL API cross reference:
ALRMBR DU LL_RTC_ALMB_GetWeekDay
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY

Definition at line 2158 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_SetDay | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Day
 | ) |  |

Set ALARM B Day in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
Reference Manual to LL API cross reference:
ALRMBR DT LL_RTC_ALMB_SetDay
ALRMBR DU LL_RTC_ALMB_SetDay
Parameters:
RTCx | RTC Instance
Day | Value between Min_Data=0x01 and Max_Data=0x31
Return values:
None

Definition at line 2104 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_ALMB_Init().

__STATIC_INLINE void LL_RTC_ALMB_SetHour | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Hours
 | ) |  |

Set ALARM B Hours in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
Reference Manual to LL API cross reference:
ALRMBR HT LL_RTC_ALMB_SetHour
ALRMBR HU LL_RTC_ALMB_SetHour
Parameters:
RTCx | RTC Instance
Hours | Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
Return values:
None

Definition at line 2199 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_SetMask | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Mask
 | ) |  |

Specify the Alarm B masks.

Reference Manual to LL API cross reference:
ALRMBR MSK4 LL_RTC_ALMB_SetMask
ALRMBR MSK3 LL_RTC_ALMB_SetMask
ALRMBR MSK2 LL_RTC_ALMB_SetMask
ALRMBR MSK1 LL_RTC_ALMB_SetMask
Parameters:
RTCx RTC Instance
Mask This parameter can be a combination of the following values:
  • LL_RTC_ALMB_MASK_NONE
  • LL_RTC_ALMB_MASK_DATEWEEKDAY
  • LL_RTC_ALMB_MASK_HOURS
  • LL_RTC_ALMB_MASK_MINUTES
  • LL_RTC_ALMB_MASK_SECONDS
  • LL_RTC_ALMB_MASK_ALL
Return values:
None

Definition at line 2048 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_ALMB_Init().

__STATIC_INLINE void LL_RTC_ALMB_SetMinute | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Minutes
 | ) |  |

Set ALARM B Minutes in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
Reference Manual to LL API cross reference:
ALRMBR MNT LL_RTC_ALMB_SetMinute
ALRMBR MNU LL_RTC_ALMB_SetMinute
Parameters:
RTCx | RTC Instance
Minutes | between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 2230 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_SetSecond | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Seconds
 | ) |  |

Set ALARM B Seconds in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
Reference Manual to LL API cross reference:
ALRMBR ST LL_RTC_ALMB_SetSecond
ALRMBR SU LL_RTC_ALMB_SetSecond
Parameters:
RTCx | RTC Instance
Seconds | Value between Min_Data=0x00 and Max_Data=0x59
Return values:
None

Definition at line 2261 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_SetSubSecond | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Subsecond
 | ) |  |

Set Alarm B Sub seconds value.

Reference Manual to LL API cross reference:
ALRMBSSR SS LL_RTC_ALMB_SetSubSecond
Parameters:
RTCx | RTC Instance
Subsecond | Value between Min_Data=0x00 and Max_Data=0x7FFF
Return values:
None

Definition at line 2362 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Mask
 | ) |  |

Set Alarm B Mask the most-significant bits starting at this bit.

Note:
This register can be written only when ALRBE is reset in RTC_CR register, or in initialization mode.
Reference Manual to LL API cross reference:
ALRMBSSR MASKSS LL_RTC_ALMB_SetSubSecondMask
Parameters:
RTCx | RTC Instance
Mask | Value between Min_Data=0x00 and Max_Data=0xF
Return values:
None

Definition at line 2339 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | TimeFormat
 | ) |  |

Set ALARM B time format (AM/24-hour or PM notation)

Reference Manual to LL API cross reference:
ALRMBR PM LL_RTC_ALMB_SetTimeFormat
Parameters:
RTCx RTC Instance
TimeFormat This parameter can be one of the following values:
  • LL_RTC_ALMB_TIME_FORMAT_AM
  • LL_RTC_ALMB_TIME_FORMAT_PM
Return values:
None

Definition at line 2172 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ALMB_SetWeekDay | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | WeekDay
 | ) |  |

Set ALARM B Weekday.

Reference Manual to LL API cross reference:
ALRMBR DU LL_RTC_ALMB_SetWeekDay
Parameters:
RTCx RTC Instance
WeekDay This parameter can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY
Return values:
None

Definition at line 2140 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_ALMB_Init().

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Timestamp

Functions
Timestamp
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_TS_EnableInternalEvent (RTC_TypeDef *RTCx)
Enable internal event timestamp.
__STATIC_INLINE void | LL_RTC_TS_DisableInternalEvent (RTC_TypeDef *RTCx)
Disable internal event timestamp.
__STATIC_INLINE void | LL_RTC_TS_Enable (RTC_TypeDef *RTCx)
Enable Timestamp.
__STATIC_INLINE void | LL_RTC_TS_Disable (RTC_TypeDef *RTCx)
Disable Timestamp.
__STATIC_INLINE void | LL_RTC_TS_SetActiveEdge (RTC_TypeDef *RTCx, uint32_t Edge)
Set Time-stamp event active edge.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetActiveEdge (RTC_TypeDef *RTCx)
Get Time-stamp event active edge.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetTimeFormat (RTC_TypeDef *RTCx)
Get Timestamp AM/PM notation (AM or 24-hour format)
__STATIC_INLINE uint32_t | LL_RTC_TS_GetHour (RTC_TypeDef *RTCx)
Get Timestamp Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetMinute (RTC_TypeDef *RTCx)
Get Timestamp Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetSecond (RTC_TypeDef *RTCx)
Get Timestamp Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetTime (RTC_TypeDef *RTCx)
Get Timestamp time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetWeekDay (RTC_TypeDef *RTCx)
Get Timestamp Week day.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetMonth (RTC_TypeDef *RTCx)
Get Timestamp Month in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetDay (RTC_TypeDef *RTCx)
Get Timestamp Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetDate (RTC_TypeDef *RTCx)
Get Timestamp date (WeekDay, Day and Month) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetSubSecond (RTC_TypeDef *RTCx)
Get time-stamp sub second value.
__STATIC_INLINE void | LL_RTC_TS_EnableOnTamper (RTC_TypeDef *RTCx)
Activate timestamp on tamper detection event.
__STATIC_INLINE void | LL_RTC_TS_DisableOnTamper (RTC_TypeDef *RTCx)
Disable timestamp on tamper detection event.

Function Documentation

__STATIC_INLINE void LL_RTC_TS_Disable ( RTC_TypeDef * RTCx )

Disable Timestamp.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR TSE LL_RTC_TS_Disable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2429 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TS_DisableInternalEvent ( RTC_TypeDef * RTCx )

Disable internal event timestamp.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR ITSE LL_RTC_TS_DisableInternalEvent
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2405 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TS_DisableOnTamper ( RTC_TypeDef * RTCx )

Disable timestamp on tamper detection event.

Reference Manual to LL API cross reference:
TAMPCR TAMPTS LL_RTC_TS_DisableOnTamper
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2637 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TS_Enable ( RTC_TypeDef * RTCx )

Enable Timestamp.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR TSE LL_RTC_TS_Enable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2417 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TS_EnableInternalEvent ( RTC_TypeDef * RTCx )

Enable internal event timestamp.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR ITSE LL_RTC_TS_EnableInternalEvent
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2393 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TS_EnableOnTamper ( RTC_TypeDef * RTCx )

Activate timestamp on tamper detection event.

Reference Manual to LL API cross reference:
TAMPCR TAMPTS LL_RTC_TS_EnableOnTamper
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2626 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge ( RTC_TypeDef * RTCx )

Get Time-stamp event active edge.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR TSEDGE LL_RTC_TS_GetActiveEdge
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_TIMESTAMP_EDGE_RISING
  • LL_RTC_TIMESTAMP_EDGE_FALLING

Definition at line 2459 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetDate ( RTC_TypeDef * RTCx )

Get Timestamp date (WeekDay, Day and Month) in BCD format.

Note:
helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_MONTH, and __LL_RTC_GET_DAY are available to get independently each parameter.
Reference Manual to LL API cross reference:
TSDR WDU LL_RTC_TS_GetDate
TSDR MT LL_RTC_TS_GetDate
TSDR MU LL_RTC_TS_GetDate
TSDR DT LL_RTC_TS_GetDate
TSDR DU LL_RTC_TS_GetDate
Parameters:
RTCx RTC Instance
Return values:
Combination of Weekday, Day and Month

Definition at line 2603 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetDay ( RTC_TypeDef * RTCx )

Get Timestamp Day in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
Reference Manual to LL API cross reference:
TSDR DT LL_RTC_TS_GetDay
TSDR DU LL_RTC_TS_GetDay
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x31

Definition at line 2586 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetHour ( RTC_TypeDef * RTCx )

Get Timestamp Hours in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
Reference Manual to LL API cross reference:
TSTR HT LL_RTC_TS_GetHour
TSTR HU LL_RTC_TS_GetHour
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23

Definition at line 2485 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute ( RTC_TypeDef * RTCx )

Get Timestamp Minutes in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
Reference Manual to LL API cross reference:
TSTR MNT LL_RTC_TS_GetMinute
TSTR MNU LL_RTC_TS_GetMinute
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 2498 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth ( RTC_TypeDef * RTCx )

Get Timestamp Month in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
Reference Manual to LL API cross reference:
TSDR MT LL_RTC_TS_GetMonth
TSDR MU LL_RTC_TS_GetMonth
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_MONTH_JANUARY
  • LL_RTC_MONTH_FEBRUARY
  • LL_RTC_MONTH_MARCH
  • LL_RTC_MONTH_APRIL
  • LL_RTC_MONTH_MAY
  • LL_RTC_MONTH_JUNE
  • LL_RTC_MONTH_JULY
  • LL_RTC_MONTH_AUGUST
  • LL_RTC_MONTH_SEPTEMBER
  • LL_RTC_MONTH_OCTOBER
  • LL_RTC_MONTH_NOVEMBER
  • LL_RTC_MONTH_DECEMBER

Definition at line 2573 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond ( RTC_TypeDef * RTCx )

Get Timestamp Seconds in BCD format.

Note:
helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
Reference Manual to LL API cross reference:
TSTR ST LL_RTC_TS_GetSecond
TSTR SU LL_RTC_TS_GetSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x59

Definition at line 2511 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond ( RTC_TypeDef * RTCx )

Get time-stamp sub second value.

Reference Manual to LL API cross reference:
TSSSR SS LL_RTC_TS_GetSubSecond
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xFFFF

Definition at line 2614 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetTime ( RTC_TypeDef * RTCx )

Get Timestamp time (hour, minute and second) in BCD format.

Note:
helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND are available to get independently each parameter.
Reference Manual to LL API cross reference:
TSTR HT LL_RTC_TS_GetTime
TSTR HU LL_RTC_TS_GetTime
TSTR MNT LL_RTC_TS_GetTime
TSTR MNU LL_RTC_TS_GetTime
TSTR ST LL_RTC_TS_GetTime
TSTR SU LL_RTC_TS_GetTime
Parameters:
RTCx RTC Instance
Return values:
Combination of hours, minutes and seconds.

Definition at line 2529 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat ( RTC_TypeDef * RTCx )

Get Timestamp AM/PM notation (AM or 24-hour format)

Reference Manual to LL API cross reference:
TSTR PM LL_RTC_TS_GetTimeFormat
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_TS_TIME_FORMAT_AM
  • LL_RTC_TS_TIME_FORMAT_PM

Definition at line 2472 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay ( RTC_TypeDef * RTCx )

Get Timestamp Week day.

Reference Manual to LL API cross reference:
TSDR WDU LL_RTC_TS_GetWeekDay
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_WEEKDAY_MONDAY
  • LL_RTC_WEEKDAY_TUESDAY
  • LL_RTC_WEEKDAY_WEDNESDAY
  • LL_RTC_WEEKDAY_THURSDAY
  • LL_RTC_WEEKDAY_FRIDAY
  • LL_RTC_WEEKDAY_SATURDAY
  • LL_RTC_WEEKDAY_SUNDAY

Definition at line 2548 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TS_SetActiveEdge | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Edge
 | ) |  |

Set Time-stamp event active edge.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting
Reference Manual to LL API cross reference:
CR TSEDGE LL_RTC_TS_SetActiveEdge
Parameters:
RTCx RTC Instance
Edge This parameter can be one of the following values:
  • LL_RTC_TIMESTAMP_EDGE_RISING
  • LL_RTC_TIMESTAMP_EDGE_FALLING
Return values:
None

Definition at line 2445 of file stm32wbxx_ll_rtc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Tamper

Functions
Tamper
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_TAMPER_Enable (RTC_TypeDef *RTCx, uint32_t Tamper)
Enable RTC_TAMPx input detection.
__STATIC_INLINE void | LL_RTC_TAMPER_Disable (RTC_TypeDef *RTCx, uint32_t Tamper)
Clear RTC_TAMPx input detection.
__STATIC_INLINE void | LL_RTC_TAMPER_EnableMask (RTC_TypeDef *RTCx, uint32_t Mask)
Enable Tamper mask flag.
__STATIC_INLINE void | LL_RTC_TAMPER_DisableMask (RTC_TypeDef *RTCx, uint32_t Mask)
Disable Tamper mask flag.
__STATIC_INLINE void | LL_RTC_TAMPER_EnableEraseBKP (RTC_TypeDef *RTCx, uint32_t Tamper)
Enable backup register erase after Tamper event detection.
__STATIC_INLINE void | LL_RTC_TAMPER_DisableEraseBKP (RTC_TypeDef *RTCx, uint32_t Tamper)
Disable backup register erase after Tamper event detection.
__STATIC_INLINE void | LL_RTC_TAMPER_DisablePullUp (RTC_TypeDef *RTCx)
Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)
__STATIC_INLINE void | LL_RTC_TAMPER_EnablePullUp (RTC_TypeDef *RTCx)
Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling)
__STATIC_INLINE void | LL_RTC_TAMPER_SetPrecharge (RTC_TypeDef *RTCx, uint32_t Duration)
Set RTC_TAMPx precharge duration.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_GetPrecharge (RTC_TypeDef *RTCx)
Get RTC_TAMPx precharge duration.
__STATIC_INLINE void | LL_RTC_TAMPER_SetFilterCount (RTC_TypeDef *RTCx, uint32_t FilterCount)
Set RTC_TAMPx filter count.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_GetFilterCount (RTC_TypeDef *RTCx)
Get RTC_TAMPx filter count.
__STATIC_INLINE void | LL_RTC_TAMPER_SetSamplingFreq (RTC_TypeDef *RTCx, uint32_t SamplingFreq)
Set Tamper sampling frequency.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_GetSamplingFreq (RTC_TypeDef *RTCx)
Get Tamper sampling frequency.
__STATIC_INLINE void | LL_RTC_TAMPER_EnableActiveLevel (RTC_TypeDef *RTCx, uint32_t Tamper)
Enable Active level for Tamper input.
__STATIC_INLINE void | LL_RTC_TAMPER_DisableActiveLevel (RTC_TypeDef *RTCx, uint32_t Tamper)
Disable Active level for Tamper input.

Function Documentation

__STATIC_INLINE void LL_RTC_TAMPER_Disable | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Tamper
 | ) |  |

Clear RTC_TAMPx input detection.

Reference Manual to LL API cross reference:
TAMPCR TAMP1E LL_RTC_TAMPER_Disable
TAMPCR TAMP2E LL_RTC_TAMPER_Disable
TAMPCR TAMP3E LL_RTC_TAMPER_Disable
Parameters:
RTCx RTC Instance
Tamper This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_1 (*)
  • LL_RTC_TAMPER_2
  • LL_RTC_TAMPER_3 (*)
(*) Value not defined in all devices.
Return values:
None

Definition at line 2686 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Tamper
 | ) |  |

Disable Active level for Tamper input.

Reference Manual to LL API cross reference:
TAMPCR TAMP1TRG LL_RTC_TAMPER_DisableActiveLevel
TAMPCR TAMP2TRG LL_RTC_TAMPER_DisableActiveLevel
TAMPCR TAMP3TRG LL_RTC_TAMPER_DisableActiveLevel
Parameters:
RTCx RTC Instance
Tamper This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP3
Return values:
None

Definition at line 2934 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Tamper
 | ) |  |

Disable backup register erase after Tamper event detection.

Reference Manual to LL API cross reference:
TAMPCR TAMP1NOERASE LL_RTC_TAMPER_DisableEraseBKP
TAMPCR TAMP2NOERASE LL_RTC_TAMPER_DisableEraseBKP
TAMPCR TAMP3NOERASE LL_RTC_TAMPER_DisableEraseBKP
Parameters:
RTCx RTC Instance
Tamper This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_NOERASE_TAMPER1 (*)
  • LL_RTC_TAMPER_NOERASE_TAMPER2
  • LL_RTC_TAMPER_NOERASE_TAMPER3 (*)
(*) Value not defined in all devices.
Return values:
None

Definition at line 2767 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_DisableMask | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Mask
 | ) |  |

Disable Tamper mask flag.

Reference Manual to LL API cross reference:
TAMPCR TAMP1MF LL_RTC_TAMPER_DisableMask
TAMPCR TAMP2MF LL_RTC_TAMPER_DisableMask
TAMPCR TAMP3MF LL_RTC_TAMPER_DisableMask
Parameters:
RTCx RTC Instance
Mask This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_MASK_TAMPER1 (*)
  • LL_RTC_TAMPER_MASK_TAMPER2
  • LL_RTC_TAMPER_MASK_TAMPER3 (*)
(*) Value not defined in all devices.
Return values:
None

Definition at line 2727 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp ( RTC_TypeDef * RTCx )

Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)

Reference Manual to LL API cross reference:
TAMPCR TAMPPUDIS LL_RTC_TAMPER_DisablePullUp
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2779 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_Enable | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Tamper
 | ) |  |

Enable RTC_TAMPx input detection.

Reference Manual to LL API cross reference:
TAMPCR TAMP1E LL_RTC_TAMPER_Enable
TAMPCR TAMP2E LL_RTC_TAMPER_Enable
TAMPCR TAMP3E LL_RTC_TAMPER_Enable
Parameters:
RTCx RTC Instance
Tamper This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_1 (*)
  • LL_RTC_TAMPER_2
  • LL_RTC_TAMPER_3 (*)
(*) Value not defined in all devices.
Return values:
None

Definition at line 2666 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Tamper
 | ) |  |

Enable Active level for Tamper input.

Reference Manual to LL API cross reference:
TAMPCR TAMP1TRG LL_RTC_TAMPER_EnableActiveLevel
TAMPCR TAMP2TRG LL_RTC_TAMPER_EnableActiveLevel
TAMPCR TAMP3TRG LL_RTC_TAMPER_EnableActiveLevel
Parameters:
RTCx RTC Instance
Tamper This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP3
Return values:
None

Definition at line 2916 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Tamper
 | ) |  |

Enable backup register erase after Tamper event detection.

Reference Manual to LL API cross reference:
TAMPCR TAMP1NOERASE LL_RTC_TAMPER_EnableEraseBKP
TAMPCR TAMP2NOERASE LL_RTC_TAMPER_EnableEraseBKP
TAMPCR TAMP3NOERASE LL_RTC_TAMPER_EnableEraseBKP
Parameters:
RTCx RTC Instance
Tamper This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_NOERASE_TAMPER1 (*)
  • LL_RTC_TAMPER_NOERASE_TAMPER2
  • LL_RTC_TAMPER_NOERASE_TAMPER3 (*)
(*) Value not defined in all devices.
Return values:
None

Definition at line 2747 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_EnableMask | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Mask
 | ) |  |

Enable Tamper mask flag.

Note:
Associated Tamper IT must not enabled when tamper mask is set.
Reference Manual to LL API cross reference:
TAMPCR TAMP1MF LL_RTC_TAMPER_EnableMask
TAMPCR TAMP2MF LL_RTC_TAMPER_EnableMask
TAMPCR TAMP3MF LL_RTC_TAMPER_EnableMask
Parameters:
RTCx RTC Instance
Mask This parameter can be a combination of the following values:
  • LL_RTC_TAMPER_MASK_TAMPER1 (*)
  • LL_RTC_TAMPER_MASK_TAMPER2
  • LL_RTC_TAMPER_MASK_TAMPER3 (*)
(*) Value not defined in all devices.
Return values:
None

Definition at line 2707 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp ( RTC_TypeDef * RTCx )

Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling)

Reference Manual to LL API cross reference:
TAMPCR TAMPPUDIS LL_RTC_TAMPER_EnablePullUp
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2790 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount ( RTC_TypeDef * RTCx )

Get RTC_TAMPx filter count.

Reference Manual to LL API cross reference:
TAMPCR TAMPFLT LL_RTC_TAMPER_GetFilterCount
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_TAMPER_FILTER_DISABLE
  • LL_RTC_TAMPER_FILTER_2SAMPLE
  • LL_RTC_TAMPER_FILTER_4SAMPLE
  • LL_RTC_TAMPER_FILTER_8SAMPLE

Definition at line 2856 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge ( RTC_TypeDef * RTCx )

Get RTC_TAMPx precharge duration.

Reference Manual to LL API cross reference:
TAMPCR TAMPPRCH LL_RTC_TAMPER_GetPrecharge
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_TAMPER_DURATION_1RTCCLK
  • LL_RTC_TAMPER_DURATION_2RTCCLK
  • LL_RTC_TAMPER_DURATION_4RTCCLK
  • LL_RTC_TAMPER_DURATION_8RTCCLK

Definition at line 2823 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq ( RTC_TypeDef * RTCx )

Get Tamper sampling frequency.

Reference Manual to LL API cross reference:
TAMPCR TAMPFREQ LL_RTC_TAMPER_GetSamplingFreq
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_TAMPER_SAMPLFREQDIV_32768
  • LL_RTC_TAMPER_SAMPLFREQDIV_16384
  • LL_RTC_TAMPER_SAMPLFREQDIV_8192
  • LL_RTC_TAMPER_SAMPLFREQDIV_4096
  • LL_RTC_TAMPER_SAMPLFREQDIV_2048
  • LL_RTC_TAMPER_SAMPLFREQDIV_1024
  • LL_RTC_TAMPER_SAMPLFREQDIV_512
  • LL_RTC_TAMPER_SAMPLFREQDIV_256

Definition at line 2897 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | FilterCount
 | ) |  |

Set RTC_TAMPx filter count.

Reference Manual to LL API cross reference:
TAMPCR TAMPFLT LL_RTC_TAMPER_SetFilterCount
Parameters:
RTCx RTC Instance
FilterCount This parameter can be one of the following values:
  • LL_RTC_TAMPER_FILTER_DISABLE
  • LL_RTC_TAMPER_FILTER_2SAMPLE
  • LL_RTC_TAMPER_FILTER_4SAMPLE
  • LL_RTC_TAMPER_FILTER_8SAMPLE
Return values:
None

Definition at line 2841 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Duration
 | ) |  |

Set RTC_TAMPx precharge duration.

Reference Manual to LL API cross reference:
TAMPCR TAMPPRCH LL_RTC_TAMPER_SetPrecharge
Parameters:
RTCx RTC Instance
Duration This parameter can be one of the following values:
  • LL_RTC_TAMPER_DURATION_1RTCCLK
  • LL_RTC_TAMPER_DURATION_2RTCCLK
  • LL_RTC_TAMPER_DURATION_4RTCCLK
  • LL_RTC_TAMPER_DURATION_8RTCCLK
Return values:
None

Definition at line 2808 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | SamplingFreq
 | ) |  |

Set Tamper sampling frequency.

Reference Manual to LL API cross reference:
TAMPCR TAMPFREQ LL_RTC_TAMPER_SetSamplingFreq
Parameters:
RTCx RTC Instance
SamplingFreq This parameter can be one of the following values:
  • LL_RTC_TAMPER_SAMPLFREQDIV_32768
  • LL_RTC_TAMPER_SAMPLFREQDIV_16384
  • LL_RTC_TAMPER_SAMPLFREQDIV_8192
  • LL_RTC_TAMPER_SAMPLFREQDIV_4096
  • LL_RTC_TAMPER_SAMPLFREQDIV_2048
  • LL_RTC_TAMPER_SAMPLFREQDIV_1024
  • LL_RTC_TAMPER_SAMPLFREQDIV_512
  • LL_RTC_TAMPER_SAMPLFREQDIV_256
Return values:
None

Definition at line 2878 of file stm32wbxx_ll_rtc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Wakeup

Functions
Wakeup
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_WAKEUP_Enable (RTC_TypeDef *RTCx)
Enable Wakeup timer.
__STATIC_INLINE void | LL_RTC_WAKEUP_Disable (RTC_TypeDef *RTCx)
Disable Wakeup timer.
__STATIC_INLINE uint32_t | LL_RTC_WAKEUP_IsEnabled (RTC_TypeDef *RTCx)
Check if Wakeup timer is enabled or not.
__STATIC_INLINE void | LL_RTC_WAKEUP_SetClock (RTC_TypeDef *RTCx, uint32_t WakeupClock)
Select Wakeup clock.
__STATIC_INLINE uint32_t | LL_RTC_WAKEUP_GetClock (RTC_TypeDef *RTCx)
Get Wakeup clock.
__STATIC_INLINE void | LL_RTC_WAKEUP_SetAutoReload (RTC_TypeDef *RTCx, uint32_t Value)
Set Wakeup auto-reload value.
__STATIC_INLINE uint32_t | LL_RTC_WAKEUP_GetAutoReload (RTC_TypeDef *RTCx)
Get Wakeup auto-reload value.

Function Documentation

__STATIC_INLINE void LL_RTC_WAKEUP_Disable ( RTC_TypeDef * RTCx )

Disable Wakeup timer.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR WUTE LL_RTC_WAKEUP_Disable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2967 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_WAKEUP_Enable ( RTC_TypeDef * RTCx )

Enable Wakeup timer.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR WUTE LL_RTC_WAKEUP_Enable
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 2955 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload ( RTC_TypeDef * RTCx )

Get Wakeup auto-reload value.

Reference Manual to LL API cross reference:
WUTR WUT LL_RTC_WAKEUP_GetAutoReload
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xFFFF

Definition at line 3039 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock ( RTC_TypeDef * RTCx )

Get Wakeup clock.

Reference Manual to LL API cross reference:
CR WUCKSEL LL_RTC_WAKEUP_GetClock
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_WAKEUPCLOCK_DIV_16
  • LL_RTC_WAKEUPCLOCK_DIV_8
  • LL_RTC_WAKEUPCLOCK_DIV_4
  • LL_RTC_WAKEUPCLOCK_DIV_2
  • LL_RTC_WAKEUPCLOCK_CKSPRE
  • LL_RTC_WAKEUPCLOCK_CKSPRE_WUT

Definition at line 3015 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled ( RTC_TypeDef * RTCx )

Check if Wakeup timer is enabled or not.

Reference Manual to LL API cross reference:
CR WUTE LL_RTC_WAKEUP_IsEnabled
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 2978 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Value
 | ) |  |

Set Wakeup auto-reload value.

Note:
Bit can be written only when WUTWF is set to 1 in RTC_ISR
Reference Manual to LL API cross reference:
WUTR WUT LL_RTC_WAKEUP_SetAutoReload
Parameters:
RTCx | RTC Instance
Value | Value between Min_Data=0x00 and Max_Data=0xFFFF
Return values:
None

Definition at line 3028 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_WAKEUP_SetClock | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | WakeupClock
 | ) |  |

Select Wakeup clock.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1
Reference Manual to LL API cross reference:
CR WUCKSEL LL_RTC_WAKEUP_SetClock
Parameters:
RTCx RTC Instance
WakeupClock This parameter can be one of the following values:
  • LL_RTC_WAKEUPCLOCK_DIV_16
  • LL_RTC_WAKEUPCLOCK_DIV_8
  • LL_RTC_WAKEUPCLOCK_DIV_4
  • LL_RTC_WAKEUPCLOCK_DIV_2
  • LL_RTC_WAKEUPCLOCK_CKSPRE
  • LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
Return values:
None

Definition at line 2998 of file stm32wbxx_ll_rtc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Backup_Registers

Functions
Backup_Registers
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_BAK_SetRegister (RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)
Writes a data in a specified RTC Backup data register.
__STATIC_INLINE uint32_t | LL_RTC_BAK_GetRegister (RTC_TypeDef *RTCx, uint32_t BackupRegister)
Reads data from the specified RTC Backup data Register.

Function Documentation

__STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | BackupRegister
 | ) |  |

Reads data from the specified RTC Backup data Register.

Reference Manual to LL API cross reference:
BKPxR BKP LL_RTC_BAK_GetRegister
Parameters:
RTCx RTC Instance
BackupRegister This parameter can be one of the following values:
  • LL_RTC_BKP_DR0
  • LL_RTC_BKP_DR1
  • LL_RTC_BKP_DR2
  • LL_RTC_BKP_DR3
  • LL_RTC_BKP_DR4
  • LL_RTC_BKP_DR5
  • LL_RTC_BKP_DR6
  • LL_RTC_BKP_DR7
  • LL_RTC_BKP_DR8
  • LL_RTC_BKP_DR9
  • LL_RTC_BKP_DR10
  • LL_RTC_BKP_DR11
  • LL_RTC_BKP_DR12
  • LL_RTC_BKP_DR13
  • LL_RTC_BKP_DR14
  • LL_RTC_BKP_DR15
  • LL_RTC_BKP_DR16
  • LL_RTC_BKP_DR17
  • LL_RTC_BKP_DR18
  • LL_RTC_BKP_DR19
Return values:
Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF

Definition at line 3118 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_BAK_SetRegister | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | BackupRegister,
 |  | uint32_t | Data
 | ) |  |

Writes a data in a specified RTC Backup data register.

Reference Manual to LL API cross reference:
BKPxR BKP LL_RTC_BAK_SetRegister
Parameters:
RTCx | RTC Instance
BackupRegister This parameter can be one of the following values:
  • LL_RTC_BKP_DR0
  • LL_RTC_BKP_DR1
  • LL_RTC_BKP_DR2
  • LL_RTC_BKP_DR3
  • LL_RTC_BKP_DR4
  • LL_RTC_BKP_DR5
  • LL_RTC_BKP_DR6
  • LL_RTC_BKP_DR7
  • LL_RTC_BKP_DR8
  • LL_RTC_BKP_DR9
  • LL_RTC_BKP_DR10
  • LL_RTC_BKP_DR11
  • LL_RTC_BKP_DR12
  • LL_RTC_BKP_DR13
  • LL_RTC_BKP_DR14
  • LL_RTC_BKP_DR15
  • LL_RTC_BKP_DR16
  • LL_RTC_BKP_DR17
  • LL_RTC_BKP_DR18
  • LL_RTC_BKP_DR19
Data | Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
Return values:
None

Definition at line 3082 of file stm32wbxx_ll_rtc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Calibration

Functions
Calibration
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_CAL_SetOutputFreq (RTC_TypeDef *RTCx, uint32_t Frequency)
Set Calibration output frequency (1 Hz or 512 Hz)
__STATIC_INLINE uint32_t | LL_RTC_CAL_GetOutputFreq (RTC_TypeDef *RTCx)
Get Calibration output frequency (1 Hz or 512 Hz)
__STATIC_INLINE void | LL_RTC_CAL_SetPulse (RTC_TypeDef *RTCx, uint32_t Pulse)
Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm)
__STATIC_INLINE uint32_t | LL_RTC_CAL_IsPulseInserted (RTC_TypeDef *RTCx)
Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm)
__STATIC_INLINE void | LL_RTC_CAL_SetPeriod (RTC_TypeDef *RTCx, uint32_t Period)
Set the calibration cycle period.
__STATIC_INLINE uint32_t | LL_RTC_CAL_GetPeriod (RTC_TypeDef *RTCx)
Get the calibration cycle period.
__STATIC_INLINE void | LL_RTC_CAL_SetMinus (RTC_TypeDef *RTCx, uint32_t CalibMinus)
Set Calibration minus.
__STATIC_INLINE uint32_t | LL_RTC_CAL_GetMinus (RTC_TypeDef *RTCx)
Get Calibration minus.

Function Documentation

__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus ( RTC_TypeDef * RTCx )

Get Calibration minus.

Reference Manual to LL API cross reference:
CALR CALM LL_RTC_CAL_GetMinus
Parameters:
RTCx RTC Instance
Return values:
Value between Min_Data=0x00 and Max_Data= 0x1FF

Definition at line 3249 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq ( RTC_TypeDef * RTCx )

Get Calibration output frequency (1 Hz or 512 Hz)

Reference Manual to LL API cross reference:
CR COE LL_RTC_CAL_GetOutputFreq
CR COSEL LL_RTC_CAL_GetOutputFreq
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_CALIB_OUTPUT_NONE
  • LL_RTC_CALIB_OUTPUT_1HZ
  • LL_RTC_CALIB_OUTPUT_512HZ

Definition at line 3164 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod ( RTC_TypeDef * RTCx )

Get the calibration cycle period.

Reference Manual to LL API cross reference:
CALR CALW8 LL_RTC_CAL_GetPeriod
CALR CALW16 LL_RTC_CAL_GetPeriod
Parameters:
RTCx RTC Instance
Return values:
Returned value can be one of the following values:
  • LL_RTC_CALIB_PERIOD_32SEC
  • LL_RTC_CALIB_PERIOD_16SEC
  • LL_RTC_CALIB_PERIOD_8SEC

Definition at line 3224 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted ( RTC_TypeDef * RTCx )

Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm)

Reference Manual to LL API cross reference:
CALR CALP LL_RTC_CAL_IsPulseInserted
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3191 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_CAL_SetMinus | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | CalibMinus
 | ) |  |

Set Calibration minus.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Bit can be written only when RECALPF is set to 0 in RTC_ISR
Reference Manual to LL API cross reference:
CALR CALM LL_RTC_CAL_SetMinus
Parameters:
RTCx | RTC Instance
CalibMinus | Value between Min_Data=0x00 and Max_Data=0x1FF
Return values:
None

Definition at line 3238 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_CAL_SetOutputFreq | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Frequency
 | ) |  |

Set Calibration output frequency (1 Hz or 512 Hz)

Note:
Bits are write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR COE LL_RTC_CAL_SetOutputFreq
CR COSEL LL_RTC_CAL_SetOutputFreq
Parameters:
RTCx RTC Instance
Frequency This parameter can be one of the following values:
  • LL_RTC_CALIB_OUTPUT_NONE
  • LL_RTC_CALIB_OUTPUT_1HZ
  • LL_RTC_CALIB_OUTPUT_512HZ
Return values:
None

Definition at line 3149 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_CAL_SetPeriod | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Period
 | ) |  |

Set the calibration cycle period.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Bit can be written only when RECALPF is set to 0 in RTC_ISR
Reference Manual to LL API cross reference:
CALR CALW8 LL_RTC_CAL_SetPeriod
CALR CALW16 LL_RTC_CAL_SetPeriod
Parameters:
RTCx RTC Instance
Period This parameter can be one of the following values:
  • LL_RTC_CALIB_PERIOD_32SEC
  • LL_RTC_CALIB_PERIOD_16SEC
  • LL_RTC_CALIB_PERIOD_8SEC
Return values:
None

Definition at line 3209 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_CAL_SetPulse | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | Pulse
 | ) |  |

Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm)

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Bit can be written only when RECALPF is set to 0 in RTC_ISR
Reference Manual to LL API cross reference:
CALR CALP LL_RTC_CAL_SetPulse
Parameters:
RTCx RTC Instance
Pulse This parameter can be one of the following values:
  • LL_RTC_CALIB_INSERTPULSE_NONE
  • LL_RTC_CALIB_INSERTPULSE_SET
Return values:
None

Definition at line 3180 of file stm32wbxx_ll_rtc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FLAG_Management

Functions
FLAG_Management
RTC Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITS (RTC_TypeDef *RTCx)
Get Internal Time-stamp flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_RECALP (RTC_TypeDef *RTCx)
Get Recalibration pending Flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP3 (RTC_TypeDef *RTCx)
Get RTC_TAMP3 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP2 (RTC_TypeDef *RTCx)
Get RTC_TAMP2 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP1 (RTC_TypeDef *RTCx)
Get RTC_TAMP1 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TSOV (RTC_TypeDef *RTCx)
Get Time-stamp overflow flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TS (RTC_TypeDef *RTCx)
Get Time-stamp flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_WUT (RTC_TypeDef *RTCx)
Get Wakeup timer flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRB (RTC_TypeDef *RTCx)
Get Alarm B flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRA (RTC_TypeDef *RTCx)
Get Alarm A flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ITS (RTC_TypeDef *RTCx)
Clear Internal Time-stamp flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TAMP3 (RTC_TypeDef *RTCx)
Clear RTC_TAMP3 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TAMP2 (RTC_TypeDef *RTCx)
Clear RTC_TAMP2 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TAMP1 (RTC_TypeDef *RTCx)
Clear RTC_TAMP1 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TSOV (RTC_TypeDef *RTCx)
Clear Time-stamp overflow flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TS (RTC_TypeDef *RTCx)
Clear Time-stamp flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_WUT (RTC_TypeDef *RTCx)
Clear Wakeup timer flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ALRB (RTC_TypeDef *RTCx)
Clear Alarm B flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ALRA (RTC_TypeDef *RTCx)
Clear Alarm A flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_INIT (RTC_TypeDef *RTCx)
Get Initialization flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_RS (RTC_TypeDef *RTCx)
Get Registers synchronization flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_RS (RTC_TypeDef *RTCx)
Clear Registers synchronization flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_INITS (RTC_TypeDef *RTCx)
Get Initialization status flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_SHP (RTC_TypeDef *RTCx)
Get Shift operation pending flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_WUTW (RTC_TypeDef *RTCx)
Get Wakeup timer write flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRBW (RTC_TypeDef *RTCx)
Get Alarm B write flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRAW (RTC_TypeDef *RTCx)
Get Alarm A write flag.

Function Documentation

__STATIC_INLINE void LL_RTC_ClearFlag_ALRA ( RTC_TypeDef * RTCx )

Clear Alarm A flag.

Reference Manual to LL API cross reference:
ISR ALRAF LL_RTC_ClearFlag_ALRA
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3482 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_ALRB ( RTC_TypeDef * RTCx )

Clear Alarm B flag.

Reference Manual to LL API cross reference:
ISR ALRBF LL_RTC_ClearFlag_ALRB
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3471 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_ITS ( RTC_TypeDef * RTCx )

Clear Internal Time-stamp flag.

Reference Manual to LL API cross reference:
ISR ITSF LL_RTC_ClearFlag_ITS
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3386 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_RS ( RTC_TypeDef * RTCx )

Clear Registers synchronization flag.

Reference Manual to LL API cross reference:
ISR RSF LL_RTC_ClearFlag_RS
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3515 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_WaitForSynchro().

__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1 ( RTC_TypeDef * RTCx )

Clear RTC_TAMP1 detection flag.

Reference Manual to LL API cross reference:
ISR TAMP1F LL_RTC_ClearFlag_TAMP1
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3424 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_TAMP2 ( RTC_TypeDef * RTCx )

Clear RTC_TAMP2 detection flag.

Reference Manual to LL API cross reference:
ISR TAMP2F LL_RTC_ClearFlag_TAMP2
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3411 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_TAMP3 ( RTC_TypeDef * RTCx )

Clear RTC_TAMP3 detection flag.

Reference Manual to LL API cross reference:
ISR TAMP3F LL_RTC_ClearFlag_TAMP3
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3398 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_TS ( RTC_TypeDef * RTCx )

Clear Time-stamp flag.

Reference Manual to LL API cross reference:
ISR TSF LL_RTC_ClearFlag_TS
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3447 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_TSOV ( RTC_TypeDef * RTCx )

Clear Time-stamp overflow flag.

Reference Manual to LL API cross reference:
ISR TSOVF LL_RTC_ClearFlag_TSOV
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3436 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_ClearFlag_WUT ( RTC_TypeDef * RTCx )

Clear Wakeup timer flag.

Reference Manual to LL API cross reference:
ISR WUTF LL_RTC_ClearFlag_WUT
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3459 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA ( RTC_TypeDef * RTCx )

Get Alarm A flag.

Reference Manual to LL API cross reference:
ISR ALRAF LL_RTC_IsActiveFlag_ALRA
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3375 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW ( RTC_TypeDef * RTCx )

Get Alarm A write flag.

Reference Manual to LL API cross reference:
ISR ALRAWF LL_RTC_IsActiveFlag_ALRAW
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3572 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB ( RTC_TypeDef * RTCx )

Get Alarm B flag.

Reference Manual to LL API cross reference:
ISR ALRBF LL_RTC_IsActiveFlag_ALRB
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3364 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW ( RTC_TypeDef * RTCx )

Get Alarm B write flag.

Reference Manual to LL API cross reference:
ISR ALRBWF LL_RTC_IsActiveFlag_ALRBW
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3561 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT ( RTC_TypeDef * RTCx )

Get Initialization flag.

Reference Manual to LL API cross reference:
ISR INITF LL_RTC_IsActiveFlag_INIT
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3493 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_EnterInitMode().

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS ( RTC_TypeDef * RTCx )

Get Initialization status flag.

Reference Manual to LL API cross reference:
ISR INITS LL_RTC_IsActiveFlag_INITS
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3526 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS ( RTC_TypeDef * RTCx )

Get Internal Time-stamp flag.

Reference Manual to LL API cross reference:
ISR ITSF LL_RTC_IsActiveFlag_ITS
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3268 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP ( RTC_TypeDef * RTCx )

Get Recalibration pending Flag.

Reference Manual to LL API cross reference:
ISR RECALPF LL_RTC_IsActiveFlag_RECALP
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3279 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS ( RTC_TypeDef * RTCx )

Get Registers synchronization flag.

Reference Manual to LL API cross reference:
ISR RSF LL_RTC_IsActiveFlag_RS
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3504 of file stm32wbxx_ll_rtc.h.

Referenced by LL_RTC_WaitForSynchro().

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP ( RTC_TypeDef * RTCx )

Get Shift operation pending flag.

Reference Manual to LL API cross reference:
ISR SHPF LL_RTC_IsActiveFlag_SHP
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3537 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1 ( RTC_TypeDef * RTCx )

Get RTC_TAMP1 detection flag.

Reference Manual to LL API cross reference:
ISR TAMP1F LL_RTC_IsActiveFlag_TAMP1
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3317 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2 ( RTC_TypeDef * RTCx )

Get RTC_TAMP2 detection flag.

Reference Manual to LL API cross reference:
ISR TAMP2F LL_RTC_IsActiveFlag_TAMP2
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3304 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3 ( RTC_TypeDef * RTCx )

Get RTC_TAMP3 detection flag.

Reference Manual to LL API cross reference:
ISR TAMP3F LL_RTC_IsActiveFlag_TAMP3
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3291 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS ( RTC_TypeDef * RTCx )

Get Time-stamp flag.

Reference Manual to LL API cross reference:
ISR TSF LL_RTC_IsActiveFlag_TS
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3340 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV ( RTC_TypeDef * RTCx )

Get Time-stamp overflow flag.

Reference Manual to LL API cross reference:
ISR TSOVF LL_RTC_IsActiveFlag_TSOV
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3329 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT ( RTC_TypeDef * RTCx )

Get Wakeup timer flag.

Reference Manual to LL API cross reference:
ISR WUTF LL_RTC_IsActiveFlag_WUT
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3352 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW ( RTC_TypeDef * RTCx )

Get Wakeup timer write flag.

Reference Manual to LL API cross reference:
ISR WUTWF LL_RTC_IsActiveFlag_WUTW
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3549 of file stm32wbxx_ll_rtc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IT_Management

Functions
IT_Management
RTC Exported Functions

Functions

__STATIC_INLINE void | LL_RTC_EnableIT_TS (RTC_TypeDef *RTCx)
Enable Time-stamp interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TS (RTC_TypeDef *RTCx)
Disable Time-stamp interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_WUT (RTC_TypeDef *RTCx)
Enable Wakeup timer interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_WUT (RTC_TypeDef *RTCx)
Disable Wakeup timer interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ALRB (RTC_TypeDef *RTCx)
Enable Alarm B interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ALRB (RTC_TypeDef *RTCx)
Disable Alarm B interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ALRA (RTC_TypeDef *RTCx)
Enable Alarm A interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ALRA (RTC_TypeDef *RTCx)
Disable Alarm A interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_TAMP3 (RTC_TypeDef *RTCx)
Enable Tamper 3 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TAMP3 (RTC_TypeDef *RTCx)
Disable Tamper 3 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_TAMP2 (RTC_TypeDef *RTCx)
Enable Tamper 2 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TAMP2 (RTC_TypeDef *RTCx)
Disable Tamper 2 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_TAMP1 (RTC_TypeDef *RTCx)
Enable Tamper 1 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TAMP1 (RTC_TypeDef *RTCx)
Disable Tamper 1 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_TAMP (RTC_TypeDef *RTCx)
Enable all Tamper Interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TAMP (RTC_TypeDef *RTCx)
Disable all Tamper Interrupt.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TS (RTC_TypeDef *RTCx)
Check if Time-stamp interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_WUT (RTC_TypeDef *RTCx)
Check if Wakeup timer interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ALRB (RTC_TypeDef *RTCx)
Check if Alarm B interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ALRA (RTC_TypeDef *RTCx)
Check if Alarm A interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TAMP3 (RTC_TypeDef *RTCx)
Check if Tamper 3 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TAMP2 (RTC_TypeDef *RTCx)
Check if Tamper 2 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TAMP1 (RTC_TypeDef *RTCx)
Check if Tamper 1 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TAMP (RTC_TypeDef *RTCx)
Check if all the TAMPER interrupts are enabled or not.

Function Documentation

__STATIC_INLINE void LL_RTC_DisableIT_ALRA ( RTC_TypeDef * RTCx )

Disable Alarm A interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR ALRAIE LL_RTC_DisableIT_ALRA
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3678 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableIT_ALRB ( RTC_TypeDef * RTCx )

Disable Alarm B interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR ALRBIE LL_RTC_DisableIT_ALRB
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3654 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableIT_TAMP ( RTC_TypeDef * RTCx )

Disable all Tamper Interrupt.

Reference Manual to LL API cross reference:
TAMPCR TAMPIE LL_RTC_DisableIT_TAMP
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3772 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableIT_TAMP1 ( RTC_TypeDef * RTCx )

Disable Tamper 1 interrupt.

Reference Manual to LL API cross reference:
TAMPCR TAMP1IE LL_RTC_DisableIT_TAMP1
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3749 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableIT_TAMP2 ( RTC_TypeDef * RTCx )

Disable Tamper 2 interrupt.

Reference Manual to LL API cross reference:
TAMPCR TAMP2IE LL_RTC_DisableIT_TAMP2
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3725 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableIT_TAMP3 ( RTC_TypeDef * RTCx )

Disable Tamper 3 interrupt.

Reference Manual to LL API cross reference:
TAMPCR TAMP3IE LL_RTC_DisableIT_TAMP3
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3701 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableIT_TS ( RTC_TypeDef * RTCx )

Disable Time-stamp interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR TSIE LL_RTC_DisableIT_TS
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3604 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_DisableIT_WUT ( RTC_TypeDef * RTCx )

Disable Wakeup timer interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR WUTIE LL_RTC_DisableIT_WUT
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3629 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_ALRA ( RTC_TypeDef * RTCx )

Enable Alarm A interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR ALRAIE LL_RTC_EnableIT_ALRA
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3666 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_ALRB ( RTC_TypeDef * RTCx )

Enable Alarm B interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR ALRBIE LL_RTC_EnableIT_ALRB
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3642 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_TAMP ( RTC_TypeDef * RTCx )

Enable all Tamper Interrupt.

Reference Manual to LL API cross reference:
TAMPCR TAMPIE LL_RTC_EnableIT_TAMP
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3761 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_TAMP1 ( RTC_TypeDef * RTCx )

Enable Tamper 1 interrupt.

Reference Manual to LL API cross reference:
TAMPCR TAMP1IE LL_RTC_EnableIT_TAMP1
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3738 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_TAMP2 ( RTC_TypeDef * RTCx )

Enable Tamper 2 interrupt.

Reference Manual to LL API cross reference:
TAMPCR TAMP2IE LL_RTC_EnableIT_TAMP2
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3714 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_TAMP3 ( RTC_TypeDef * RTCx )

Enable Tamper 3 interrupt.

Reference Manual to LL API cross reference:
TAMPCR TAMP3IE LL_RTC_EnableIT_TAMP3
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3690 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_TS ( RTC_TypeDef * RTCx )

Enable Time-stamp interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR TSIE LL_RTC_EnableIT_TS
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3592 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE void LL_RTC_EnableIT_WUT ( RTC_TypeDef * RTCx )

Enable Wakeup timer interrupt.

Note:
Bit is write-protected. LL_RTC_DisableWriteProtection function should be called before.
Reference Manual to LL API cross reference:
CR WUTIE LL_RTC_EnableIT_WUT
Parameters:
RTCx RTC Instance
Return values:
None

Definition at line 3617 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA ( RTC_TypeDef * RTCx )

Check if Alarm A interrupt is enabled or not.

Reference Manual to LL API cross reference:
CR ALRAIE LL_RTC_IsEnabledIT_ALRA
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3818 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB ( RTC_TypeDef * RTCx )

Check if Alarm B interrupt is enabled or not.

Reference Manual to LL API cross reference:
CR ALRBIE LL_RTC_IsEnabledIT_ALRB
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3807 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP ( RTC_TypeDef * RTCx )

Check if all the TAMPER interrupts are enabled or not.

Reference Manual to LL API cross reference:
TAMPCR TAMPIE LL_RTC_IsEnabledIT_TAMP
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3872 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1 ( RTC_TypeDef * RTCx )

Check if Tamper 1 interrupt is enabled or not.

Reference Manual to LL API cross reference:
TAMPCR TAMP1IE LL_RTC_IsEnabledIT_TAMP1
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3859 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2 ( RTC_TypeDef * RTCx )

Check if Tamper 2 interrupt is enabled or not.

Reference Manual to LL API cross reference:
TAMPCR TAMP2IE LL_RTC_IsEnabledIT_TAMP2
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3844 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3 ( RTC_TypeDef * RTCx )

Check if Tamper 3 interrupt is enabled or not.

Reference Manual to LL API cross reference:
TAMPCR TAMP3IE LL_RTC_IsEnabledIT_TAMP3
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3830 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS ( RTC_TypeDef * RTCx )

Check if Time-stamp interrupt is enabled or not.

Reference Manual to LL API cross reference:
CR TSIE LL_RTC_IsEnabledIT_TS
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3783 of file stm32wbxx_ll_rtc.h.

__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT ( RTC_TypeDef * RTCx )

Check if Wakeup timer interrupt is enabled or not.

Reference Manual to LL API cross reference:
CR WUTIE LL_RTC_IsEnabledIT_WUT
Parameters:
RTCx RTC Instance
Return values:
State of bit (1 or 0).

Definition at line 3795 of file stm32wbxx_ll_rtc.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
RTC Exported Functions

Functions

ErrorStatus | LL_RTC_DeInit (RTC_TypeDef *RTCx)
De-Initializes the RTC registers to their default reset values.
ErrorStatus | LL_RTC_Init (RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
Initializes the RTC registers according to the specified parameters in RTC_InitStruct.
void | LL_RTC_StructInit (LL_RTC_InitTypeDef *RTC_InitStruct)
Set each LL_RTC_InitTypeDef field to default value.
ErrorStatus | LL_RTC_TIME_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
Set the RTC current time.
void | LL_RTC_TIME_StructInit (LL_RTC_TimeTypeDef *RTC_TimeStruct)
Set each LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
ErrorStatus | LL_RTC_DATE_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct)
Set the RTC current date.
void | LL_RTC_DATE_StructInit (LL_RTC_DateTypeDef *RTC_DateStruct)
Set each LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)
ErrorStatus | LL_RTC_ALMA_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the RTC Alarm A.
ErrorStatus | LL_RTC_ALMB_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the RTC Alarm B.
void | LL_RTC_ALMA_StructInit (LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).
void | LL_RTC_ALMB_StructInit (LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).
ErrorStatus | LL_RTC_EnterInitMode (RTC_TypeDef *RTCx)
Enters the RTC Initialization mode.
ErrorStatus | LL_RTC_ExitInitMode (RTC_TypeDef *RTCx)
Exit the RTC Initialization mode.
ErrorStatus | LL_RTC_WaitForSynchro (RTC_TypeDef *RTCx)
Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Function Documentation

ErrorStatus LL_RTC_ALMA_Init | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | RTC_Format,
 |  | LL_RTC_AlarmTypeDef * | RTC_AlarmStruct
 | ) |  |

Set the RTC Alarm A.

Note:
The Alarm register can only be written when the corresponding Alarm is disabled (Use LL_RTC_ALMA_Disable function).
Parameters:
RTCx | RTC Instance
RTC_Format This parameter can be one of the following values:
  • LL_RTC_FORMAT_BIN
  • LL_RTC_FORMAT_BCD
RTC_AlarmStruct | pointer to a LL_RTC_AlarmTypeDef structure that contains the alarm configuration parameters.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ALARMA registers are configured
  • ERROR: ALARMA registers are not configured

Definition at line 465 of file stm32wbxx_ll_rtc.c.

References __LL_RTC_CONVERT_BCD2BIN, __LL_RTC_CONVERT_BIN2BCD, LL_RTC_AlarmTypeDef::AlarmDateWeekDay, LL_RTC_AlarmTypeDef::AlarmDateWeekDaySel, LL_RTC_AlarmTypeDef::AlarmMask, LL_RTC_AlarmTypeDef::AlarmTime, assert_param, LL_RTC_TimeTypeDef::Hours, IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL, IS_LL_RTC_ALMA_MASK, IS_LL_RTC_DAY, IS_LL_RTC_FORMAT, IS_LL_RTC_HOUR12, IS_LL_RTC_HOUR24, IS_LL_RTC_MINUTES, IS_LL_RTC_SECONDS, IS_LL_RTC_TIME_FORMAT, IS_LL_RTC_WEEKDAY, LL_RTC_ALMA_ConfigTime(), LL_RTC_ALMA_DATEWEEKDAYSEL_DATE, LL_RTC_ALMA_DisableWeekday(), LL_RTC_ALMA_EnableWeekday(), LL_RTC_ALMA_SetDay(), LL_RTC_ALMA_SetMask(), LL_RTC_ALMA_SetWeekDay(), LL_RTC_DisableWriteProtection(), LL_RTC_EnableWriteProtection(), LL_RTC_FORMAT_BIN, LL_RTC_GetHourFormat(), LL_RTC_HOURFORMAT_24HOUR, LL_RTC_TimeTypeDef::Minutes, LL_RTC_TimeTypeDef::Seconds, and LL_RTC_TimeTypeDef::TimeFormat.

void LL_RTC_ALMA_StructInit ( LL_RTC_AlarmTypeDef * RTC_AlarmStruct )

Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).

Parameters:
RTC_AlarmStruct pointer to a LL_RTC_AlarmTypeDef structure which will be initialized.
Return values:
None

Definition at line 693 of file stm32wbxx_ll_rtc.c.

References LL_RTC_AlarmTypeDef::AlarmDateWeekDay, LL_RTC_AlarmTypeDef::AlarmDateWeekDaySel, LL_RTC_AlarmTypeDef::AlarmMask, LL_RTC_AlarmTypeDef::AlarmTime, LL_RTC_TimeTypeDef::Hours, LL_RTC_ALMA_DATEWEEKDAYSEL_DATE, LL_RTC_ALMA_MASK_NONE, LL_RTC_ALMA_TIME_FORMAT_AM, LL_RTC_TimeTypeDef::Minutes, LL_RTC_TimeTypeDef::Seconds, and LL_RTC_TimeTypeDef::TimeFormat.

ErrorStatus LL_RTC_ALMB_Init | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | RTC_Format,
 |  | LL_RTC_AlarmTypeDef * | RTC_AlarmStruct
 | ) |  |

Set the RTC Alarm B.

Note:
The Alarm register can only be written when the corresponding Alarm is disabled (LL_RTC_ALMB_Disable function).
Parameters:
RTCx | RTC Instance
RTC_Format This parameter can be one of the following values:
  • LL_RTC_FORMAT_BIN
  • LL_RTC_FORMAT_BCD
RTC_AlarmStruct | pointer to a LL_RTC_AlarmTypeDef structure that contains the alarm configuration parameters.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ALARMB registers are configured
  • ERROR: ALARMB registers are not configured

Definition at line 583 of file stm32wbxx_ll_rtc.c.

References __LL_RTC_CONVERT_BCD2BIN, __LL_RTC_CONVERT_BIN2BCD, LL_RTC_AlarmTypeDef::AlarmDateWeekDay, LL_RTC_AlarmTypeDef::AlarmDateWeekDaySel, LL_RTC_AlarmTypeDef::AlarmMask, LL_RTC_AlarmTypeDef::AlarmTime, assert_param, LL_RTC_TimeTypeDef::Hours, IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL, IS_LL_RTC_ALMB_MASK, IS_LL_RTC_DAY, IS_LL_RTC_FORMAT, IS_LL_RTC_HOUR12, IS_LL_RTC_HOUR24, IS_LL_RTC_MINUTES, IS_LL_RTC_SECONDS, IS_LL_RTC_TIME_FORMAT, IS_LL_RTC_WEEKDAY, LL_RTC_ALMB_ConfigTime(), LL_RTC_ALMB_DATEWEEKDAYSEL_DATE, LL_RTC_ALMB_DisableWeekday(), LL_RTC_ALMB_EnableWeekday(), LL_RTC_ALMB_SetDay(), LL_RTC_ALMB_SetMask(), LL_RTC_ALMB_SetWeekDay(), LL_RTC_DisableWriteProtection(), LL_RTC_EnableWriteProtection(), LL_RTC_FORMAT_BIN, LL_RTC_GetHourFormat(), LL_RTC_HOURFORMAT_24HOUR, LL_RTC_TimeTypeDef::Minutes, LL_RTC_TimeTypeDef::Seconds, and LL_RTC_TimeTypeDef::TimeFormat.

void LL_RTC_ALMB_StructInit ( LL_RTC_AlarmTypeDef * RTC_AlarmStruct )

Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).

Parameters:
RTC_AlarmStruct pointer to a LL_RTC_AlarmTypeDef structure which will be initialized.
Return values:
None

Definition at line 715 of file stm32wbxx_ll_rtc.c.

References LL_RTC_AlarmTypeDef::AlarmDateWeekDay, LL_RTC_AlarmTypeDef::AlarmDateWeekDaySel, LL_RTC_AlarmTypeDef::AlarmMask, LL_RTC_AlarmTypeDef::AlarmTime, LL_RTC_TimeTypeDef::Hours, LL_RTC_ALMB_DATEWEEKDAYSEL_DATE, LL_RTC_ALMB_MASK_NONE, LL_RTC_ALMB_TIME_FORMAT_AM, LL_RTC_TimeTypeDef::Minutes, LL_RTC_TimeTypeDef::Seconds, and LL_RTC_TimeTypeDef::TimeFormat.

ErrorStatus LL_RTC_DATE_Init | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | RTC_Format,
 |  | LL_RTC_DateTypeDef * | RTC_DateStruct
 | ) |  |

Set the RTC current date.

Parameters:
RTCx | RTC Instance
RTC_Format This parameter can be one of the following values:
  • LL_RTC_FORMAT_BIN
  • LL_RTC_FORMAT_BCD
RTC_DateStruct | pointer to a RTC_DateTypeDef structure that contains the date configuration information for the RTC.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC Day register is configured
  • ERROR: RTC Day register is not configured

Definition at line 375 of file stm32wbxx_ll_rtc.c.

References __LL_RTC_CONVERT_BCD2BIN, __LL_RTC_CONVERT_BIN2BCD, assert_param, LL_RTC_DateTypeDef::Day, IS_LL_RTC_DAY, IS_LL_RTC_FORMAT, IS_LL_RTC_MONTH, IS_LL_RTC_WEEKDAY, IS_LL_RTC_YEAR, LL_RTC_DATE_Config(), LL_RTC_DisableInitMode(), LL_RTC_DisableWriteProtection(), LL_RTC_EnableWriteProtection(), LL_RTC_EnterInitMode(), LL_RTC_FORMAT_BIN, LL_RTC_IsShadowRegBypassEnabled(), LL_RTC_WaitForSynchro(), LL_RTC_DateTypeDef::Month, LL_RTC_DateTypeDef::WeekDay, and LL_RTC_DateTypeDef::Year.

void LL_RTC_DATE_StructInit ( LL_RTC_DateTypeDef * RTC_DateStruct )

Set each LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)

Parameters:
RTC_DateStruct pointer to a LL_RTC_DateTypeDef structure which will be initialized.
Return values:
None

Definition at line 442 of file stm32wbxx_ll_rtc.c.

References LL_RTC_DateTypeDef::Day, LL_RTC_MONTH_JANUARY, LL_RTC_WEEKDAY_MONDAY, LL_RTC_DateTypeDef::Month, LL_RTC_DateTypeDef::WeekDay, and LL_RTC_DateTypeDef::Year.

ErrorStatus LL_RTC_DeInit ( RTC_TypeDef * RTCx )

De-Initializes the RTC registers to their default reset values.

Note:
This function doesn't reset the RTC Clock source and RTC Backup Data registers.
Parameters:
RTCx RTC Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC registers are de-initialized
  • ERROR: RTC registers are not de-initialized

Definition at line 149 of file stm32wbxx_ll_rtc.c.

References assert_param, LL_RTC_DisableWriteProtection(), LL_RTC_EnableWriteProtection(), LL_RTC_EnterInitMode(), LL_RTC_WaitForSynchro(), and RTC_SYNCH_PRESC_DEFAULT.

ErrorStatus LL_RTC_EnterInitMode ( RTC_TypeDef * RTCx )

Enters the RTC Initialization mode.

Note:
The RTC Initialization mode is write protected, use the LL_RTC_DisableWriteProtection before calling this function.
Parameters:
RTCx RTC Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC is in Init mode
  • ERROR: RTC is not in Init mode

Definition at line 740 of file stm32wbxx_ll_rtc.c.

References assert_param, LL_RTC_EnableInitMode(), LL_RTC_IsActiveFlag_INIT(), LL_SYSTICK_IsActiveCounterFlag(), and RTC_INITMODE_TIMEOUT.

Referenced by LL_RTC_DATE_Init(), LL_RTC_DeInit(), LL_RTC_Init(), and LL_RTC_TIME_Init().

ErrorStatus LL_RTC_ExitInitMode ( RTC_TypeDef * RTCx )

Exit the RTC Initialization mode.

Note:
When the initialization sequence is complete, the calendar restarts counting after 4 RTCCLK cycles.
The RTC Initialization mode is write protected, use the LL_RTC_DisableWriteProtection before calling this function.
Parameters:
RTCx RTC Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC exited from in Init mode
  • ERROR: Not applicable

Definition at line 784 of file stm32wbxx_ll_rtc.c.

References assert_param, and LL_RTC_DisableInitMode().

ErrorStatus LL_RTC_Init | ( | RTC_TypeDef * | RTCx,
 |  | LL_RTC_InitTypeDef * | RTC_InitStruct
 | ) |  |

Initializes the RTC registers according to the specified parameters in RTC_InitStruct.

Parameters:
RTCx | RTC Instance
RTC_InitStruct | pointer to a LL_RTC_InitTypeDef structure that contains the configuration information for the RTC peripheral.
Note:
The RTC Prescaler register is write protected and can be written in initialization mode only.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC registers are initialized
  • ERROR: RTC registers are not initialized

Definition at line 213 of file stm32wbxx_ll_rtc.c.

References assert_param, LL_RTC_InitTypeDef::AsynchPrescaler, LL_RTC_InitTypeDef::HourFormat, IS_LL_RTC_ASYNCH_PREDIV, IS_LL_RTC_HOURFORMAT, IS_LL_RTC_SYNCH_PREDIV, LL_RTC_DisableInitMode(), LL_RTC_DisableWriteProtection(), LL_RTC_EnableWriteProtection(), LL_RTC_EnterInitMode(), LL_RTC_SetAsynchPrescaler(), LL_RTC_SetHourFormat(), LL_RTC_SetSynchPrescaler(), and LL_RTC_InitTypeDef::SynchPrescaler.

void LL_RTC_StructInit ( LL_RTC_InitTypeDef * RTC_InitStruct )

Set each LL_RTC_InitTypeDef field to default value.

Parameters:
RTC_InitStruct pointer to a LL_RTC_InitTypeDef structure which will be initialized.
Return values:
None

Definition at line 252 of file stm32wbxx_ll_rtc.c.

References LL_RTC_InitTypeDef::AsynchPrescaler, LL_RTC_InitTypeDef::HourFormat, LL_RTC_HOURFORMAT_24HOUR, RTC_ASYNCH_PRESC_DEFAULT, RTC_SYNCH_PRESC_DEFAULT, and LL_RTC_InitTypeDef::SynchPrescaler.

ErrorStatus LL_RTC_TIME_Init | ( | RTC_TypeDef * | RTCx,
 |  | uint32_t | RTC_Format,
 |  | LL_RTC_TimeTypeDef * | RTC_TimeStruct
 | ) |  |

Set the RTC current time.

Parameters:
RTCx | RTC Instance
RTC_Format This parameter can be one of the following values:
  • LL_RTC_FORMAT_BIN
  • LL_RTC_FORMAT_BCD
RTC_TimeStruct | pointer to a RTC_TimeTypeDef structure that contains the time configuration information for the RTC.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC Time register is configured
  • ERROR: RTC Time register is not configured

Definition at line 272 of file stm32wbxx_ll_rtc.c.

References __LL_RTC_CONVERT_BCD2BIN, __LL_RTC_CONVERT_BIN2BCD, assert_param, LL_RTC_TimeTypeDef::Hours, IS_LL_RTC_FORMAT, IS_LL_RTC_HOUR12, IS_LL_RTC_HOUR24, IS_LL_RTC_MINUTES, IS_LL_RTC_SECONDS, IS_LL_RTC_TIME_FORMAT, LL_RTC_DisableInitMode(), LL_RTC_DisableWriteProtection(), LL_RTC_EnableWriteProtection(), LL_RTC_EnterInitMode(), LL_RTC_FORMAT_BIN, LL_RTC_GetHourFormat(), LL_RTC_HOURFORMAT_24HOUR, LL_RTC_IsShadowRegBypassEnabled(), LL_RTC_TIME_Config(), LL_RTC_WaitForSynchro(), LL_RTC_TimeTypeDef::Minutes, LL_RTC_TimeTypeDef::Seconds, and LL_RTC_TimeTypeDef::TimeFormat.

void LL_RTC_TIME_StructInit ( LL_RTC_TimeTypeDef * RTC_TimeStruct )

Set each LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).

Parameters:
RTC_TimeStruct pointer to a LL_RTC_TimeTypeDef structure which will be initialized.
Return values:
None

Definition at line 354 of file stm32wbxx_ll_rtc.c.

References LL_RTC_TimeTypeDef::Hours, LL_RTC_TIME_FORMAT_AM_OR_24, LL_RTC_TimeTypeDef::Minutes, LL_RTC_TimeTypeDef::Seconds, and LL_RTC_TimeTypeDef::TimeFormat.

ErrorStatus LL_RTC_WaitForSynchro ( RTC_TypeDef * RTCx )

Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Note:
The RTC Resynchronization mode is write protected, use the LL_RTC_DisableWriteProtection before calling this function.
To read the calendar through the shadow registers after Calendar initialization, calendar update or after wakeup from low power modes the software must first clear the RSF flag. The software must then wait until it is set again before reading the calendar, which means that the calendar registers have been correctly copied into the RTC_TR and RTC_DR shadow registers.
Parameters:
RTCx RTC Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RTC registers are synchronised
  • ERROR: RTC registers are not synchronised

Definition at line 811 of file stm32wbxx_ll_rtc.c.

References assert_param, LL_RTC_ClearFlag_RS(), LL_RTC_IsActiveFlag_RS(), LL_SYSTICK_IsActiveCounterFlag(), and RTC_SYNCHRO_TIMEOUT.

Referenced by LL_RTC_DATE_Init(), LL_RTC_DeInit(), and LL_RTC_TIME_Init().

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SPI

Modules
SPI
STM32WBxx_LL_Driver

Modules

SPI Private Constants
SPI Private Macros
SPI Exported Init structure
SPI Exported Constants
SPI Exported Macros
SPI Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for SPI registers.

Register | Bit | Function
CR1 | BIDIMODE | LL_SPI_GetTransferDirection
 |  | LL_SPI_SetTransferDirection
 | BIDIOE | LL_SPI_GetTransferDirection
 |  | LL_SPI_SetTransferDirection
 | BR | LL_SPI_GetBaudRatePrescaler
 |  | LL_SPI_SetBaudRatePrescaler
 | CPHA | LL_SPI_GetClockPhase
 |  | LL_SPI_SetClockPhase
 | CPOL | LL_SPI_GetClockPolarity
 |  | LL_SPI_SetClockPolarity
 | CRCEN | LL_SPI_DisableCRC
 |  | LL_SPI_EnableCRC
 |  | LL_SPI_IsEnabledCRC
 | CRCL | LL_SPI_GetCRCWidth
 |  | LL_SPI_SetCRCWidth
 | CRCNEXT | LL_SPI_SetCRCNext
 | LSBFIRST | LL_SPI_GetTransferBitOrder
 |  | LL_SPI_SetTransferBitOrder
 | MSTR | LL_SPI_GetMode
 |  | LL_SPI_SetMode
 | RXONLY | LL_SPI_GetTransferDirection
 |  | LL_SPI_SetTransferDirection
 | SPE | LL_SPI_Disable
 |  | LL_SPI_Enable
 |  | LL_SPI_IsEnabled
 | SSI | LL_SPI_GetMode
 |  | LL_SPI_SetMode
 | SSM | LL_SPI_GetNSSMode
 |  | LL_SPI_SetNSSMode
CR2 | DS | LL_SPI_GetDataWidth
 |  | LL_SPI_SetDataWidth
 | ERRIE | LL_SPI_DisableIT_ERR
 |  | LL_SPI_EnableIT_ERR
 |  | LL_SPI_IsEnabledIT_ERR
 | FRF | LL_SPI_GetStandard
 |  | LL_SPI_SetStandard
 | FRXTH | LL_SPI_GetRxFIFOThreshold
 |  | LL_SPI_SetRxFIFOThreshold
 | LDMARX | LL_SPI_GetDMAParity_RX
 |  | LL_SPI_SetDMAParity_RX
 | LDMATX | LL_SPI_GetDMAParity_TX
 |  | LL_SPI_SetDMAParity_TX
 | NSSP | LL_SPI_DisableNSSPulseMgt
 |  | LL_SPI_EnableNSSPulseMgt
 |  | LL_SPI_IsEnabledNSSPulse
 | RXDMAEN | LL_SPI_DisableDMAReq_RX
 |  | LL_SPI_EnableDMAReq_RX
 |  | LL_SPI_IsEnabledDMAReq_RX
 | RXNEIE | LL_SPI_DisableIT_RXNE
 |  | LL_SPI_EnableIT_RXNE
 |  | LL_SPI_IsEnabledIT_RXNE
 | SSOE | LL_SPI_GetNSSMode
 |  | LL_SPI_SetNSSMode
 | TXDMAEN | LL_SPI_DisableDMAReq_TX
 |  | LL_SPI_EnableDMAReq_TX
 |  | LL_SPI_IsEnabledDMAReq_TX
 | TXEIE | LL_SPI_DisableIT_TXE
 |  | LL_SPI_EnableIT_TXE
 |  | LL_SPI_IsEnabledIT_TXE
CRCPR | CRCPOLY | LL_SPI_GetCRCPolynomial
 |  | LL_SPI_SetCRCPolynomial
DR | DR | LL_SPI_DMA_GetRegAddr
 |  | LL_SPI_ReceiveData16
 |  | LL_SPI_ReceiveData8
 |  | LL_SPI_TransmitData16
 |  | LL_SPI_TransmitData8
RXCRCR | RXCRC | LL_SPI_GetRxCRC
SR | BSY | LL_SPI_IsActiveFlag_BSY
 | CRCERR | LL_SPI_ClearFlag_CRCERR
 |  | LL_SPI_IsActiveFlag_CRCERR
 | FRE | LL_SPI_ClearFlag_FRE
 |  | LL_SPI_IsActiveFlag_FRE
 | FRLVL | LL_SPI_GetRxFIFOLevel
 | FTLVL | LL_SPI_GetTxFIFOLevel
 | MODF | LL_SPI_ClearFlag_MODF
 |  | LL_SPI_IsActiveFlag_MODF
 | OVR | LL_SPI_ClearFlag_OVR
 |  | LL_SPI_IsActiveFlag_OVR
 | RXNE | LL_SPI_IsActiveFlag_RXNE
 | TXE | LL_SPI_IsActiveFlag_TXE
TXCRCR | TXCRC | LL_SPI_GetTxCRC
Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SPI Private Constants

Defines
SPI Private Constants
SPI

Defines

#define SPI_CR1_CLEAR_MASK

Define Documentation

#define SPI_CR1_CLEAR_MASK
Value:
(SPI_CR1_CPHA    | SPI_CR1_CPOL     | SPI_CR1_MSTR   | \
                                            SPI_CR1_BR      | SPI_CR1_LSBFIRST | SPI_CR1_SSI    | \
                                            SPI_CR1_SSM     | SPI_CR1_RXONLY   | SPI_CR1_CRCL   | \
                                            SPI_CR1_CRCNEXT | SPI_CR1_CRCEN    | SPI_CR1_BIDIOE | \
                                            SPI_CR1_BIDIMODE)

Definition at line 49 of file stm32wbxx_ll_spi.c.

Referenced by LL_SPI_Init().

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SPI Private Macros

Defines
SPI Private Macros
SPI

Defines

#define | IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__)
#define | IS_LL_SPI_MODE(__VALUE__)
#define | IS_LL_SPI_DATAWIDTH(__VALUE__)
#define | IS_LL_SPI_POLARITY(__VALUE__)
#define | IS_LL_SPI_PHASE(__VALUE__)
#define | IS_LL_SPI_NSS(__VALUE__)
#define | IS_LL_SPI_BAUDRATE(__VALUE__)
#define | IS_LL_SPI_BITORDER(__VALUE__)
#define | IS_LL_SPI_CRCCALCULATION(__VALUE__)
#define | IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)

Define Documentation

#define IS_LL_SPI_BAUDRATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2)      \
                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4)   \
                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8)   \
                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16)  \
                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32)  \
                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64)  \
                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))

Definition at line 94 of file stm32wbxx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_BITORDER ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_LSB_FIRST) \
                                       || ((__VALUE__) == LL_SPI_MSB_FIRST))

Definition at line 103 of file stm32wbxx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_CRC_POLYNOMIAL ( __VALUE__ ) ((__VALUE__) >= 0x1U)

Definition at line 109 of file stm32wbxx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_CRCCALCULATION ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
                                             || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))

Definition at line 106 of file stm32wbxx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_DATAWIDTH ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_DATAWIDTH_4BIT)     \
                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT)  \
                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT)  \
                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT)  \
                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT)  \
                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT)  \
                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))

Definition at line 70 of file stm32wbxx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_MODE_MASTER) \
                                   || ((__VALUE__) == LL_SPI_MODE_SLAVE))

Definition at line 67 of file stm32wbxx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_NSS ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_NSS_SOFT)          \
                                  || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
                                  || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))

Definition at line 90 of file stm32wbxx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_PHASE ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_PHASE_1EDGE) \
                                    || ((__VALUE__) == LL_SPI_PHASE_2EDGE))

Definition at line 87 of file stm32wbxx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_POLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_POLARITY_LOW) \
                                       || ((__VALUE__) == LL_SPI_POLARITY_HIGH))

Definition at line 84 of file stm32wbxx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_TRANSFER_DIRECTION ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_FULL_DUPLEX)       \
                                                 || ((__VALUE__) == LL_SPI_SIMPLEX_RX)     \
                                                 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
                                                 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))

Definition at line 62 of file stm32wbxx_ll_spi.c.

Referenced by LL_SPI_Init().

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LL_SPI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_SPI_InitTypeDef Struct Reference
SPI Exported Init structure

SPI Init structures definition. More...

#include <stm32wbxx_ll_spi.h>

Data Fields

uint32_t | TransferDirection
uint32_t | Mode
uint32_t | DataWidth
uint32_t | ClockPolarity
uint32_t | ClockPhase
uint32_t | NSS
uint32_t | BaudRate
uint32_t | BitOrder
uint32_t | CRCCalculation
uint32_t | CRCPoly

Detailed Description

SPI Init structures definition.

Definition at line 54 of file stm32wbxx_ll_spi.h.

Field Documentation

uint32_t LL_SPI_InitTypeDef::BaudRate

Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock. This parameter can be a value of Baud Rate Prescaler.

Note:
The communication clock is derived from the master clock. The slave clock does not need to be set.

This feature can be modified afterwards using unitary function LL_SPI_SetBaudRatePrescaler().

Definition at line 86 of file stm32wbxx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::BitOrder

Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of Transmission Bit Order.

This feature can be modified afterwards using unitary function LL_SPI_SetTransferBitOrder().

Definition at line 92 of file stm32wbxx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::ClockPhase

Specifies the clock active edge for the bit capture. This parameter can be a value of Clock Phase.

This feature can be modified afterwards using unitary function LL_SPI_SetClockPhase().

Definition at line 76 of file stm32wbxx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::ClockPolarity

Specifies the serial clock steady state. This parameter can be a value of Clock Polarity.

This feature can be modified afterwards using unitary function LL_SPI_SetClockPolarity().

Definition at line 71 of file stm32wbxx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::CRCCalculation

Specifies if the CRC calculation is enabled or not. This parameter can be a value of CRC Calculation.

This feature can be modified afterwards using unitary functions LL_SPI_EnableCRC() and LL_SPI_DisableCRC().

Definition at line 97 of file stm32wbxx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::CRCPoly

Specifies the polynomial used for the CRC calculation. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.

This feature can be modified afterwards using unitary function LL_SPI_SetCRCPolynomial().

Definition at line 102 of file stm32wbxx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::DataWidth

Specifies the SPI data width. This parameter can be a value of Datawidth.

This feature can be modified afterwards using unitary function LL_SPI_SetDataWidth().

Definition at line 66 of file stm32wbxx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::Mode

Specifies the SPI mode (Master/Slave). This parameter can be a value of Operation Mode.

This feature can be modified afterwards using unitary function LL_SPI_SetMode().

Definition at line 61 of file stm32wbxx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::NSS

Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. This parameter can be a value of Slave Select Pin Mode.

This feature can be modified afterwards using unitary function LL_SPI_SetNSSMode().

Definition at line 81 of file stm32wbxx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::TransferDirection

Specifies the SPI unidirectional or bidirectional data mode. This parameter can be a value of Transfer Mode.

This feature can be modified afterwards using unitary function LL_SPI_SetTransferDirection().

Definition at line 56 of file stm32wbxx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

The documentation for this struct was generated from the following file:
  • stm32wbxx_ll_spi.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
SPI Exported Constants

Flags defines which can be used with LL_SPI_ReadReg function. More...

Defines

#define | LL_SPI_SR_RXNE SPI_SR_RXNE
#define | LL_SPI_SR_TXE SPI_SR_TXE
#define | LL_SPI_SR_BSY SPI_SR_BSY
#define | LL_SPI_SR_CRCERR SPI_SR_CRCERR
#define | LL_SPI_SR_MODF SPI_SR_MODF
#define | LL_SPI_SR_OVR SPI_SR_OVR
#define | LL_SPI_SR_FRE SPI_SR_FRE

Detailed Description

Flags defines which can be used with LL_SPI_ReadReg function.

Define Documentation

#define LL_SPI_SR_BSY SPI_SR_BSY

Busy flag

Definition at line 125 of file stm32wbxx_ll_spi.h.

#define LL_SPI_SR_CRCERR SPI_SR_CRCERR

CRC error flag

Definition at line 126 of file stm32wbxx_ll_spi.h.

#define LL_SPI_SR_FRE SPI_SR_FRE

TI mode frame format error flag

Definition at line 129 of file stm32wbxx_ll_spi.h.

#define LL_SPI_SR_MODF SPI_SR_MODF

Mode fault flag

Definition at line 127 of file stm32wbxx_ll_spi.h.

#define LL_SPI_SR_OVR SPI_SR_OVR

Overrun flag

Definition at line 128 of file stm32wbxx_ll_spi.h.

#define LL_SPI_SR_RXNE SPI_SR_RXNE

Rx buffer not empty flag

Definition at line 123 of file stm32wbxx_ll_spi.h.

#define LL_SPI_SR_TXE SPI_SR_TXE

Tx buffer empty flag

Definition at line 124 of file stm32wbxx_ll_spi.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IT Defines

Defines
IT Defines
SPI Exported Constants

IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions. More...

Defines

#define | LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE
#define | LL_SPI_CR2_TXEIE SPI_CR2_TXEIE
#define | LL_SPI_CR2_ERRIE SPI_CR2_ERRIE

Detailed Description

IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions.

Define Documentation

#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE

Error interrupt enable

Definition at line 140 of file stm32wbxx_ll_spi.h.

#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE

Rx buffer not empty interrupt enable

Definition at line 138 of file stm32wbxx_ll_spi.h.

#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE

Tx buffer empty interrupt enable

Definition at line 139 of file stm32wbxx_ll_spi.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Operation Mode

Defines
Operation Mode
SPI Exported Constants

Defines

#define | LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
#define | LL_SPI_MODE_SLAVE 0x00000000U

Define Documentation

#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)

Master configuration

Definition at line 148 of file stm32wbxx_ll_spi.h.

#define LL_SPI_MODE_SLAVE 0x00000000U

Slave configuration

Definition at line 149 of file stm32wbxx_ll_spi.h.

Referenced by LL_SPI_StructInit().

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Serial Protocol

Defines
Serial Protocol
SPI Exported Constants

Defines

#define | LL_SPI_PROTOCOL_MOTOROLA 0x00000000U
#define | LL_SPI_PROTOCOL_TI (SPI_CR2_FRF)

Define Documentation

#define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U

Motorola mode. Used as default value

Definition at line 157 of file stm32wbxx_ll_spi.h.

#define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF)

TI mode

Definition at line 158 of file stm32wbxx_ll_spi.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Clock Phase

Defines
Clock Phase
SPI Exported Constants

Defines

#define | LL_SPI_PHASE_1EDGE 0x00000000U
#define | LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA)

Define Documentation

#define LL_SPI_PHASE_1EDGE 0x00000000U

First clock transition is the first data capture edge

Definition at line 166 of file stm32wbxx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA)

Second clock transition is the first data capture edge

Definition at line 167 of file stm32wbxx_ll_spi.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Clock Polarity

Defines
Clock Polarity
SPI Exported Constants

Defines

#define | LL_SPI_POLARITY_LOW 0x00000000U
#define | LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL)

Define Documentation

#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL)

Clock to 1 when idle

Definition at line 176 of file stm32wbxx_ll_spi.h.

#define LL_SPI_POLARITY_LOW 0x00000000U

Clock to 0 when idle

Definition at line 175 of file stm32wbxx_ll_spi.h.

Referenced by LL_SPI_StructInit().

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Baud Rate Prescaler

Defines
Baud Rate Prescaler
SPI Exported Constants

Defines

#define | LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U
#define | LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1)
#define | LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2)
#define | LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
#define | LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)

Define Documentation

#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)

BaudRate control equal to fPCLK/128

Definition at line 190 of file stm32wbxx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)

BaudRate control equal to fPCLK/16

Definition at line 187 of file stm32wbxx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U

BaudRate control equal to fPCLK/2

Definition at line 184 of file stm32wbxx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)

BaudRate control equal to fPCLK/256

Definition at line 191 of file stm32wbxx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2)

BaudRate control equal to fPCLK/32

Definition at line 188 of file stm32wbxx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0)

BaudRate control equal to fPCLK/4

Definition at line 185 of file stm32wbxx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)

BaudRate control equal to fPCLK/64

Definition at line 189 of file stm32wbxx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1)

BaudRate control equal to fPCLK/8

Definition at line 186 of file stm32wbxx_ll_spi.h.

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STM32WB55xx HAL User Manual: Transmission Bit Order

Defines
Transmission Bit Order
SPI Exported Constants

Defines

#define | LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST)
#define | LL_SPI_MSB_FIRST 0x00000000U

Define Documentation

#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST)

Data is transmitted/received with the LSB first

Definition at line 199 of file stm32wbxx_ll_spi.h.

#define LL_SPI_MSB_FIRST 0x00000000U

Data is transmitted/received with the MSB first

Definition at line 200 of file stm32wbxx_ll_spi.h.

Referenced by LL_SPI_StructInit().

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Transfer Mode

Defines
Transfer Mode
SPI Exported Constants

Defines

#define | LL_SPI_FULL_DUPLEX 0x00000000U
#define | LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY)
#define | LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE)
#define | LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)

Define Documentation

#define LL_SPI_FULL_DUPLEX 0x00000000U

Full-Duplex mode. Rx and Tx transfer on 2 lines

Definition at line 208 of file stm32wbxx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE)

Half-Duplex Rx mode. Rx transfer on 1 line

Definition at line 210 of file stm32wbxx_ll_spi.h.

#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)

Half-Duplex Tx mode. Tx transfer on 1 line

Definition at line 211 of file stm32wbxx_ll_spi.h.

#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY)

Simplex Rx mode. Rx transfer only on 1 line

Definition at line 209 of file stm32wbxx_ll_spi.h.

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STM32WB55xx HAL User Manual: Slave Select Pin Mode

Defines
Slave Select Pin Mode
SPI Exported Constants

Defines

#define | LL_SPI_NSS_SOFT (SPI_CR1_SSM)
#define | LL_SPI_NSS_HARD_INPUT 0x00000000U
#define | LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U))

Define Documentation

#define LL_SPI_NSS_HARD_INPUT 0x00000000U

NSS pin used in Input. Only used in Master mode

Definition at line 220 of file stm32wbxx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U))

NSS pin used in Output. Only used in Slave mode as chip select

Definition at line 221 of file stm32wbxx_ll_spi.h.

#define LL_SPI_NSS_SOFT (SPI_CR1_SSM)

NSS managed internally. NSS pin not used and free

Definition at line 219 of file stm32wbxx_ll_spi.h.

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STM32WB55xx HAL User Manual: Datawidth

Defines
Datawidth
SPI Exported Constants

Defines

#define | LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2)
#define | LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3)
#define | LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2)
#define | LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)

Define Documentation

#define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0)

Data length for SPI transfer: 10 bits

Definition at line 235 of file stm32wbxx_ll_spi.h.

#define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1)

Data length for SPI transfer: 11 bits

Definition at line 236 of file stm32wbxx_ll_spi.h.

#define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0)

Data length for SPI transfer: 12 bits

Definition at line 237 of file stm32wbxx_ll_spi.h.

#define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2)

Data length for SPI transfer: 13 bits

Definition at line 238 of file stm32wbxx_ll_spi.h.

#define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0)

Data length for SPI transfer: 14 bits

Definition at line 239 of file stm32wbxx_ll_spi.h.

#define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1)

Data length for SPI transfer: 15 bits

Definition at line 240 of file stm32wbxx_ll_spi.h.

#define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)

Data length for SPI transfer: 16 bits

Definition at line 241 of file stm32wbxx_ll_spi.h.

#define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1)

Data length for SPI transfer: 4 bits

Definition at line 229 of file stm32wbxx_ll_spi.h.

#define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2)

Data length for SPI transfer: 5 bits

Definition at line 230 of file stm32wbxx_ll_spi.h.

#define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0)

Data length for SPI transfer: 6 bits

Definition at line 231 of file stm32wbxx_ll_spi.h.

#define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1)

Data length for SPI transfer: 7 bits

Definition at line 232 of file stm32wbxx_ll_spi.h.

#define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)

Data length for SPI transfer: 8 bits

Definition at line 233 of file stm32wbxx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3)

Data length for SPI transfer: 9 bits

Definition at line 234 of file stm32wbxx_ll_spi.h.

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STM32WB55xx HAL User Manual: CRC Calculation

Defines
CRC Calculation
SPI Exported Constants

Defines

#define | LL_SPI_CRCCALCULATION_DISABLE 0x00000000U
#define | LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN)

Define Documentation

#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U

CRC calculation disabled

Definition at line 250 of file stm32wbxx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN)

CRC calculation enabled

Definition at line 251 of file stm32wbxx_ll_spi.h.

Referenced by LL_SPI_Init().

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CRC Length

Defines
CRC Length
SPI Exported Constants

Defines

#define | LL_SPI_CRC_8BIT 0x00000000U
#define | LL_SPI_CRC_16BIT (SPI_CR1_CRCL)

Define Documentation

#define LL_SPI_CRC_16BIT (SPI_CR1_CRCL)

16-bit CRC length

Definition at line 261 of file stm32wbxx_ll_spi.h.

#define LL_SPI_CRC_8BIT 0x00000000U

8-bit CRC length

Definition at line 260 of file stm32wbxx_ll_spi.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RX FIFO Threshold

Defines
RX FIFO Threshold
SPI Exported Constants

Defines

#define | LL_SPI_RX_FIFO_TH_HALF 0x00000000U
#define | LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH)

Define Documentation

#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U

RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit)

Definition at line 269 of file stm32wbxx_ll_spi.h.

#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH)

RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit)

Definition at line 270 of file stm32wbxx_ll_spi.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RX FIFO Level

Defines
RX FIFO Level
SPI Exported Constants

Defines

#define | LL_SPI_RX_FIFO_EMPTY 0x00000000U
#define | LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0)
#define | LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1)
#define | LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0)

Define Documentation

#define LL_SPI_RX_FIFO_EMPTY 0x00000000U

FIFO reception empty

Definition at line 278 of file stm32wbxx_ll_spi.h.

#define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0)

FIFO reception full

Definition at line 281 of file stm32wbxx_ll_spi.h.

#define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1)

FIFO reception 1/2

Definition at line 280 of file stm32wbxx_ll_spi.h.

#define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0)

FIFO reception 1/4

Definition at line 279 of file stm32wbxx_ll_spi.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TX FIFO Level

Defines
TX FIFO Level
SPI Exported Constants

Defines

#define | LL_SPI_TX_FIFO_EMPTY 0x00000000U
#define | LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0)
#define | LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1)
#define | LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0)

Define Documentation

#define LL_SPI_TX_FIFO_EMPTY 0x00000000U

FIFO transmission empty

Definition at line 289 of file stm32wbxx_ll_spi.h.

#define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0)

FIFO transmission full

Definition at line 292 of file stm32wbxx_ll_spi.h.

#define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1)

FIFO transmission 1/2

Definition at line 291 of file stm32wbxx_ll_spi.h.

#define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0)

FIFO transmission 1/4

Definition at line 290 of file stm32wbxx_ll_spi.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DMA Parity

Defines
DMA Parity
SPI Exported Constants

Defines

#define | LL_SPI_DMA_PARITY_EVEN 0x00000000U
#define | LL_SPI_DMA_PARITY_ODD 0x00000001U

Define Documentation

#define LL_SPI_DMA_PARITY_EVEN 0x00000000U

Select DMA parity Even

Definition at line 300 of file stm32wbxx_ll_spi.h.

#define LL_SPI_DMA_PARITY_ODD 0x00000001U

Select DMA parity Odd

Definition at line 301 of file stm32wbxx_ll_spi.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
SPI Exported Macros

Defines

#define | LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in SPI register.
#define | LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in SPI register.

Define Documentation

#define LL_SPI_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in SPI register.

Parameters:
__INSTANCE__ | SPI Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 335 of file stm32wbxx_ll_spi.h.

#define LL_SPI_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in SPI register.

Parameters:
__INSTANCE__ | SPI Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 327 of file stm32wbxx_ll_spi.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Configuration

Functions
Configuration
SPI Exported Functions

Functions

__STATIC_INLINE void | LL_SPI_Enable (SPI_TypeDef *SPIx)
Enable SPI peripheral.
__STATIC_INLINE void | LL_SPI_Disable (SPI_TypeDef *SPIx)
Disable SPI peripheral.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabled (SPI_TypeDef *SPIx)
Check if SPI peripheral is enabled.
__STATIC_INLINE void | LL_SPI_SetMode (SPI_TypeDef *SPIx, uint32_t Mode)
Set SPI operation mode to Master or Slave.
__STATIC_INLINE uint32_t | LL_SPI_GetMode (SPI_TypeDef *SPIx)
Get SPI operation mode (Master or Slave)
__STATIC_INLINE void | LL_SPI_SetStandard (SPI_TypeDef *SPIx, uint32_t Standard)
Set serial protocol used.
__STATIC_INLINE uint32_t | LL_SPI_GetStandard (SPI_TypeDef *SPIx)
Get serial protocol used.
__STATIC_INLINE void | LL_SPI_SetClockPhase (SPI_TypeDef *SPIx, uint32_t ClockPhase)
Set clock phase.
__STATIC_INLINE uint32_t | LL_SPI_GetClockPhase (SPI_TypeDef *SPIx)
Get clock phase.
__STATIC_INLINE void | LL_SPI_SetClockPolarity (SPI_TypeDef *SPIx, uint32_t ClockPolarity)
Set clock polarity.
__STATIC_INLINE uint32_t | LL_SPI_GetClockPolarity (SPI_TypeDef *SPIx)
Get clock polarity.
__STATIC_INLINE void | LL_SPI_SetBaudRatePrescaler (SPI_TypeDef *SPIx, uint32_t BaudRate)
Set baud rate prescaler.
__STATIC_INLINE uint32_t | LL_SPI_GetBaudRatePrescaler (SPI_TypeDef *SPIx)
Get baud rate prescaler.
__STATIC_INLINE void | LL_SPI_SetTransferBitOrder (SPI_TypeDef *SPIx, uint32_t BitOrder)
Set transfer bit order.
__STATIC_INLINE uint32_t | LL_SPI_GetTransferBitOrder (SPI_TypeDef *SPIx)
Get transfer bit order.
__STATIC_INLINE void | LL_SPI_SetTransferDirection (SPI_TypeDef *SPIx, uint32_t TransferDirection)
Set transfer direction mode.
__STATIC_INLINE uint32_t | LL_SPI_GetTransferDirection (SPI_TypeDef *SPIx)
Get transfer direction mode.
__STATIC_INLINE void | LL_SPI_SetDataWidth (SPI_TypeDef *SPIx, uint32_t DataWidth)
Set frame data width.
__STATIC_INLINE uint32_t | LL_SPI_GetDataWidth (SPI_TypeDef *SPIx)
Get frame data width.
__STATIC_INLINE void | LL_SPI_SetRxFIFOThreshold (SPI_TypeDef *SPIx, uint32_t Threshold)
Set threshold of RXFIFO that triggers an RXNE event.
__STATIC_INLINE uint32_t | LL_SPI_GetRxFIFOThreshold (SPI_TypeDef *SPIx)
Get threshold of RXFIFO that triggers an RXNE event.

Function Documentation

__STATIC_INLINE void LL_SPI_Disable ( SPI_TypeDef * SPIx )

Disable SPI peripheral.

Note:
When disabling the SPI, follow the procedure described in the Reference Manual.
Reference Manual to LL API cross reference:
CR1 SPE LL_SPI_Disable
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 371 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE void LL_SPI_Enable ( SPI_TypeDef * SPIx )

Enable SPI peripheral.

Reference Manual to LL API cross reference:
CR1 SPE LL_SPI_Enable
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 359 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler ( SPI_TypeDef * SPIx )

Get baud rate prescaler.

Reference Manual to LL API cross reference:
CR1 BR LL_SPI_GetBaudRatePrescaler
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_BAUDRATEPRESCALER_DIV2
  • LL_SPI_BAUDRATEPRESCALER_DIV4
  • LL_SPI_BAUDRATEPRESCALER_DIV8
  • LL_SPI_BAUDRATEPRESCALER_DIV16
  • LL_SPI_BAUDRATEPRESCALER_DIV32
  • LL_SPI_BAUDRATEPRESCALER_DIV64
  • LL_SPI_BAUDRATEPRESCALER_DIV128
  • LL_SPI_BAUDRATEPRESCALER_DIV256

Definition at line 538 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetClockPhase ( SPI_TypeDef * SPIx )

Get clock phase.

Reference Manual to LL API cross reference:
CR1 CPHA LL_SPI_GetClockPhase
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_PHASE_1EDGE
  • LL_SPI_PHASE_2EDGE

Definition at line 469 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity ( SPI_TypeDef * SPIx )

Get clock polarity.

Reference Manual to LL API cross reference:
CR1 CPOL LL_SPI_GetClockPolarity
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_POLARITY_LOW
  • LL_SPI_POLARITY_HIGH

Definition at line 498 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetDataWidth ( SPI_TypeDef * SPIx )

Get frame data width.

Reference Manual to LL API cross reference:
CR2 DS LL_SPI_GetDataWidth
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_DATAWIDTH_4BIT
  • LL_SPI_DATAWIDTH_5BIT
  • LL_SPI_DATAWIDTH_6BIT
  • LL_SPI_DATAWIDTH_7BIT
  • LL_SPI_DATAWIDTH_8BIT
  • LL_SPI_DATAWIDTH_9BIT
  • LL_SPI_DATAWIDTH_10BIT
  • LL_SPI_DATAWIDTH_11BIT
  • LL_SPI_DATAWIDTH_12BIT
  • LL_SPI_DATAWIDTH_13BIT
  • LL_SPI_DATAWIDTH_14BIT
  • LL_SPI_DATAWIDTH_15BIT
  • LL_SPI_DATAWIDTH_16BIT

Definition at line 652 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetMode ( SPI_TypeDef * SPIx )

Get SPI operation mode (Master or Slave)

Reference Manual to LL API cross reference:
CR1 MSTR LL_SPI_GetMode
CR1 SSI LL_SPI_GetMode
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_MODE_MASTER
  • LL_SPI_MODE_SLAVE

Definition at line 412 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold ( SPI_TypeDef * SPIx )

Get threshold of RXFIFO that triggers an RXNE event.

Reference Manual to LL API cross reference:
CR2 FRXTH LL_SPI_GetRxFIFOThreshold
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_RX_FIFO_TH_HALF
  • LL_SPI_RX_FIFO_TH_QUARTER

Definition at line 679 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetStandard ( SPI_TypeDef * SPIx )

Get serial protocol used.

Reference Manual to LL API cross reference:
CR2 FRF LL_SPI_GetStandard
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_PROTOCOL_MOTOROLA
  • LL_SPI_PROTOCOL_TI

Definition at line 440 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder ( SPI_TypeDef * SPIx )

Get transfer bit order.

Reference Manual to LL API cross reference:
CR1 LSBFIRST LL_SPI_GetTransferBitOrder
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_LSB_FIRST
  • LL_SPI_MSB_FIRST

Definition at line 566 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection ( SPI_TypeDef * SPIx )

Get transfer direction mode.

Reference Manual to LL API cross reference:
CR1 RXONLY LL_SPI_GetTransferDirection
CR1 BIDIMODE LL_SPI_GetTransferDirection
CR1 BIDIOE LL_SPI_GetTransferDirection
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_FULL_DUPLEX
  • LL_SPI_SIMPLEX_RX
  • LL_SPI_HALF_DUPLEX_RX
  • LL_SPI_HALF_DUPLEX_TX

Definition at line 603 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsEnabled ( SPI_TypeDef * SPIx )

Check if SPI peripheral is enabled.

Reference Manual to LL API cross reference:
CR1 SPE LL_SPI_IsEnabled
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 382 of file stm32wbxx_ll_spi.h.

Referenced by LL_SPI_Init().

__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | BaudRate
 | ) |  |

Set baud rate prescaler.

Note:
These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
Reference Manual to LL API cross reference:
CR1 BR LL_SPI_SetBaudRatePrescaler
Parameters:
SPIx SPI Instance
BaudRate This parameter can be one of the following values:
  • LL_SPI_BAUDRATEPRESCALER_DIV2
  • LL_SPI_BAUDRATEPRESCALER_DIV4
  • LL_SPI_BAUDRATEPRESCALER_DIV8
  • LL_SPI_BAUDRATEPRESCALER_DIV16
  • LL_SPI_BAUDRATEPRESCALER_DIV32
  • LL_SPI_BAUDRATEPRESCALER_DIV64
  • LL_SPI_BAUDRATEPRESCALER_DIV128
  • LL_SPI_BAUDRATEPRESCALER_DIV256
Return values:
None

Definition at line 519 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetClockPhase | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | ClockPhase
 | ) |  |

Set clock phase.

Note:
This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CR1 CPHA LL_SPI_SetClockPhase
Parameters:
SPIx SPI Instance
ClockPhase This parameter can be one of the following values:
  • LL_SPI_PHASE_1EDGE
  • LL_SPI_PHASE_2EDGE
Return values:
None

Definition at line 456 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetClockPolarity | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | ClockPolarity
 | ) |  |

Set clock polarity.

Note:
This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CR1 CPOL LL_SPI_SetClockPolarity
Parameters:
SPIx SPI Instance
ClockPolarity This parameter can be one of the following values:
  • LL_SPI_POLARITY_LOW
  • LL_SPI_POLARITY_HIGH
Return values:
None

Definition at line 485 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetDataWidth | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | DataWidth
 | ) |  |

Set frame data width.

Reference Manual to LL API cross reference:
CR2 DS LL_SPI_SetDataWidth
Parameters:
SPIx SPI Instance
DataWidth This parameter can be one of the following values:
  • LL_SPI_DATAWIDTH_4BIT
  • LL_SPI_DATAWIDTH_5BIT
  • LL_SPI_DATAWIDTH_6BIT
  • LL_SPI_DATAWIDTH_7BIT
  • LL_SPI_DATAWIDTH_8BIT
  • LL_SPI_DATAWIDTH_9BIT
  • LL_SPI_DATAWIDTH_10BIT
  • LL_SPI_DATAWIDTH_11BIT
  • LL_SPI_DATAWIDTH_12BIT
  • LL_SPI_DATAWIDTH_13BIT
  • LL_SPI_DATAWIDTH_14BIT
  • LL_SPI_DATAWIDTH_15BIT
  • LL_SPI_DATAWIDTH_16BIT
Return values:
None

Definition at line 628 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetMode | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Mode
 | ) |  |

Set SPI operation mode to Master or Slave.

Note:
This bit should not be changed when communication is ongoing.
Reference Manual to LL API cross reference:
CR1 MSTR LL_SPI_SetMode
CR1 SSI LL_SPI_SetMode
Parameters:
SPIx SPI Instance
Mode This parameter can be one of the following values:
  • LL_SPI_MODE_MASTER
  • LL_SPI_MODE_SLAVE
Return values:
None

Definition at line 398 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetRxFIFOThreshold | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Threshold
 | ) |  |

Set threshold of RXFIFO that triggers an RXNE event.

Reference Manual to LL API cross reference:
CR2 FRXTH LL_SPI_SetRxFIFOThreshold
Parameters:
SPIx SPI Instance
Threshold This parameter can be one of the following values:
  • LL_SPI_RX_FIFO_TH_HALF
  • LL_SPI_RX_FIFO_TH_QUARTER
Return values:
None

Definition at line 666 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetStandard | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Standard
 | ) |  |

Set serial protocol used.

Note:
This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
Reference Manual to LL API cross reference:
CR2 FRF LL_SPI_SetStandard
Parameters:
SPIx SPI Instance
Standard This parameter can be one of the following values:
  • LL_SPI_PROTOCOL_MOTOROLA
  • LL_SPI_PROTOCOL_TI
Return values:
None

Definition at line 427 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetTransferBitOrder | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | BitOrder
 | ) |  |

Set transfer bit order.

Note:
This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CR1 LSBFIRST LL_SPI_SetTransferBitOrder
Parameters:
SPIx SPI Instance
BitOrder This parameter can be one of the following values:
  • LL_SPI_LSB_FIRST
  • LL_SPI_MSB_FIRST
Return values:
None

Definition at line 553 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetTransferDirection | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | TransferDirection
 | ) |  |

Set transfer direction mode.

Note:
For Half-Duplex mode, Rx Direction is set by default. In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
Reference Manual to LL API cross reference:
CR1 RXONLY LL_SPI_SetTransferDirection
CR1 BIDIMODE LL_SPI_SetTransferDirection
CR1 BIDIOE LL_SPI_SetTransferDirection
Parameters:
SPIx SPI Instance
TransferDirection This parameter can be one of the following values:
  • LL_SPI_FULL_DUPLEX
  • LL_SPI_SIMPLEX_RX
  • LL_SPI_HALF_DUPLEX_RX
  • LL_SPI_HALF_DUPLEX_TX
Return values:
None

Definition at line 586 of file stm32wbxx_ll_spi.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CRC Management

Functions
CRC Management
SPI Exported Functions

Functions

__STATIC_INLINE void | LL_SPI_EnableCRC (SPI_TypeDef *SPIx)
Enable CRC.
__STATIC_INLINE void | LL_SPI_DisableCRC (SPI_TypeDef *SPIx)
Disable CRC.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledCRC (SPI_TypeDef *SPIx)
Check if CRC is enabled.
__STATIC_INLINE void | LL_SPI_SetCRCWidth (SPI_TypeDef *SPIx, uint32_t CRCLength)
Set CRC Length.
__STATIC_INLINE uint32_t | LL_SPI_GetCRCWidth (SPI_TypeDef *SPIx)
Get CRC Length.
__STATIC_INLINE void | LL_SPI_SetCRCNext (SPI_TypeDef *SPIx)
Set CRCNext to transfer CRC on the line.
__STATIC_INLINE void | LL_SPI_SetCRCPolynomial (SPI_TypeDef *SPIx, uint32_t CRCPoly)
Set polynomial for CRC calculation.
__STATIC_INLINE uint32_t | LL_SPI_GetCRCPolynomial (SPI_TypeDef *SPIx)
Get polynomial for CRC calculation.
__STATIC_INLINE uint32_t | LL_SPI_GetRxCRC (SPI_TypeDef *SPIx)
Get Rx CRC.
__STATIC_INLINE uint32_t | LL_SPI_GetTxCRC (SPI_TypeDef *SPIx)
Get Tx CRC.

Function Documentation

__STATIC_INLINE void LL_SPI_DisableCRC ( SPI_TypeDef * SPIx )

Disable CRC.

Note:
This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
Reference Manual to LL API cross reference:
CR1 CRCEN LL_SPI_DisableCRC
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 711 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE void LL_SPI_EnableCRC ( SPI_TypeDef * SPIx )

Enable CRC.

Note:
This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
Reference Manual to LL API cross reference:
CR1 CRCEN LL_SPI_EnableCRC
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 699 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial ( SPI_TypeDef * SPIx )

Get polynomial for CRC calculation.

Reference Manual to LL API cross reference:
CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
Parameters:
SPIx SPI Instance
Return values:
Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF

Definition at line 786 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth ( SPI_TypeDef * SPIx )

Get CRC Length.

Reference Manual to LL API cross reference:
CR1 CRCL LL_SPI_GetCRCWidth
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_CRC_8BIT
  • LL_SPI_CRC_16BIT

Definition at line 751 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetRxCRC ( SPI_TypeDef * SPIx )

Get Rx CRC.

Reference Manual to LL API cross reference:
RXCRCR RXCRC LL_SPI_GetRxCRC
Parameters:
SPIx SPI Instance
Return values:
Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF

Definition at line 797 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetTxCRC ( SPI_TypeDef * SPIx )

Get Tx CRC.

Reference Manual to LL API cross reference:
TXCRCR TXCRC LL_SPI_GetTxCRC
Parameters:
SPIx SPI Instance
Return values:
Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF

Definition at line 808 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC ( SPI_TypeDef * SPIx )

Check if CRC is enabled.

Note:
This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
Reference Manual to LL API cross reference:
CR1 CRCEN LL_SPI_IsEnabledCRC
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 723 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetCRCNext ( SPI_TypeDef * SPIx )

Set CRCNext to transfer CRC on the line.

Note:
This bit has to be written as soon as the last data is written in the SPIx_DR register.
Reference Manual to LL API cross reference:
CR1 CRCNEXT LL_SPI_SetCRCNext
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 763 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetCRCPolynomial | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | CRCPoly
 | ) |  |

Set polynomial for CRC calculation.

Reference Manual to LL API cross reference:
CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
Parameters:
SPIx | SPI Instance
CRCPoly | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
Return values:
None

Definition at line 775 of file stm32wbxx_ll_spi.h.

Referenced by LL_SPI_Init().

__STATIC_INLINE void LL_SPI_SetCRCWidth | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | CRCLength
 | ) |  |

Set CRC Length.

Note:
This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
Reference Manual to LL API cross reference:
CR1 CRCL LL_SPI_SetCRCWidth
Parameters:
SPIx SPI Instance
CRCLength This parameter can be one of the following values:
  • LL_SPI_CRC_8BIT
  • LL_SPI_CRC_16BIT
Return values:
None

Definition at line 738 of file stm32wbxx_ll_spi.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Slave Select Pin Management

Functions
Slave Select Pin Management
SPI Exported Functions

Functions

__STATIC_INLINE void | LL_SPI_SetNSSMode (SPI_TypeDef *SPIx, uint32_t NSS)
Set NSS mode.
__STATIC_INLINE uint32_t | LL_SPI_GetNSSMode (SPI_TypeDef *SPIx)
Get NSS mode.
__STATIC_INLINE void | LL_SPI_EnableNSSPulseMgt (SPI_TypeDef *SPIx)
Enable NSS pulse management.
__STATIC_INLINE void | LL_SPI_DisableNSSPulseMgt (SPI_TypeDef *SPIx)
Disable NSS pulse management.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledNSSPulse (SPI_TypeDef *SPIx)
Check if NSS pulse is enabled.

Function Documentation

__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt ( SPI_TypeDef * SPIx )

Disable NSS pulse management.

Note:
This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CR2 NSSP LL_SPI_DisableNSSPulseMgt
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 875 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt ( SPI_TypeDef * SPIx )

Enable NSS pulse management.

Note:
This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CR2 NSSP LL_SPI_EnableNSSPulseMgt
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 863 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetNSSMode ( SPI_TypeDef * SPIx )

Get NSS mode.

Reference Manual to LL API cross reference:
CR1 SSM LL_SPI_GetNSSMode
Reference Manual to LL API cross reference:
CR2 SSOE LL_SPI_GetNSSMode
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_NSS_SOFT
  • LL_SPI_NSS_HARD_INPUT
  • LL_SPI_NSS_HARD_OUTPUT

Definition at line 849 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse ( SPI_TypeDef * SPIx )

Check if NSS pulse is enabled.

Note:
This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CR2 NSSP LL_SPI_IsEnabledNSSPulse
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 887 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetNSSMode | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | NSS
 | ) |  |

Set NSS mode.

Note:
LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CR1 SSM LL_SPI_SetNSSMode
Reference Manual to LL API cross reference:
CR2 SSOE LL_SPI_SetNSSMode
Parameters:
SPIx SPI Instance
NSS This parameter can be one of the following values:
  • LL_SPI_NSS_SOFT
  • LL_SPI_NSS_HARD_INPUT
  • LL_SPI_NSS_HARD_OUTPUT
Return values:
None

Definition at line 833 of file stm32wbxx_ll_spi.h.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FLAG Management

Functions
FLAG Management
SPI Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_RXNE (SPI_TypeDef *SPIx)
Check if Rx buffer is not empty.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_TXE (SPI_TypeDef *SPIx)
Check if Tx buffer is empty.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_CRCERR (SPI_TypeDef *SPIx)
Get CRC error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_MODF (SPI_TypeDef *SPIx)
Get mode fault error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_OVR (SPI_TypeDef *SPIx)
Get overrun error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_BSY (SPI_TypeDef *SPIx)
Get busy flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_FRE (SPI_TypeDef *SPIx)
Get frame format error flag.
__STATIC_INLINE uint32_t | LL_SPI_GetRxFIFOLevel (SPI_TypeDef *SPIx)
Get FIFO reception Level.
__STATIC_INLINE uint32_t | LL_SPI_GetTxFIFOLevel (SPI_TypeDef *SPIx)
Get FIFO Transmission Level.
__STATIC_INLINE void | LL_SPI_ClearFlag_CRCERR (SPI_TypeDef *SPIx)
Clear CRC error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_MODF (SPI_TypeDef *SPIx)
Clear mode fault error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_OVR (SPI_TypeDef *SPIx)
Clear overrun error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_FRE (SPI_TypeDef *SPIx)
Clear frame format error flag.

Function Documentation

__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR ( SPI_TypeDef * SPIx )

Clear CRC error flag.

Reference Manual to LL API cross reference:
SR CRCERR LL_SPI_ClearFlag_CRCERR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1020 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE void LL_SPI_ClearFlag_FRE ( SPI_TypeDef * SPIx )

Clear frame format error flag.

Note:
Clearing this flag is done by reading SPIx_SR register
Reference Manual to LL API cross reference:
SR FRE LL_SPI_ClearFlag_FRE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1065 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE void LL_SPI_ClearFlag_MODF ( SPI_TypeDef * SPIx )

Clear mode fault error flag.

Note:
Clearing this flag is done by a read access to the SPIx_SR register followed by a write access to the SPIx_CR1 register
Reference Manual to LL API cross reference:
SR MODF LL_SPI_ClearFlag_MODF
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1033 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE void LL_SPI_ClearFlag_OVR ( SPI_TypeDef * SPIx )

Clear overrun error flag.

Note:
Clearing this flag is done by a read access to the SPIx_DR register followed by a read access to the SPIx_SR register
Reference Manual to LL API cross reference:
SR OVR LL_SPI_ClearFlag_OVR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1049 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel ( SPI_TypeDef * SPIx )

Get FIFO reception Level.

Reference Manual to LL API cross reference:
SR FRLVL LL_SPI_GetRxFIFOLevel
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_RX_FIFO_EMPTY
  • LL_SPI_RX_FIFO_QUARTER_FULL
  • LL_SPI_RX_FIFO_HALF_FULL
  • LL_SPI_RX_FIFO_FULL

Definition at line 994 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel ( SPI_TypeDef * SPIx )

Get FIFO Transmission Level.

Reference Manual to LL API cross reference:
SR FTLVL LL_SPI_GetTxFIFOLevel
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_TX_FIFO_EMPTY
  • LL_SPI_TX_FIFO_QUARTER_FULL
  • LL_SPI_TX_FIFO_HALF_FULL
  • LL_SPI_TX_FIFO_FULL

Definition at line 1009 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY ( SPI_TypeDef * SPIx )

Get busy flag.

Note:
The BSY flag is cleared under any one of the following conditions: -When the SPI is correctly disabled -When a fault is detected in Master mode (MODF bit set to 1) -In Master mode, when it finishes a data transmission and no new data is ready to be sent -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between each data transfer.
Reference Manual to LL API cross reference:
SR BSY LL_SPI_IsActiveFlag_BSY
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 968 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR ( SPI_TypeDef * SPIx )

Get CRC error flag.

Reference Manual to LL API cross reference:
SR CRCERR LL_SPI_IsActiveFlag_CRCERR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 928 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE ( SPI_TypeDef * SPIx )

Get frame format error flag.

Reference Manual to LL API cross reference:
SR FRE LL_SPI_IsActiveFlag_FRE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 979 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF ( SPI_TypeDef * SPIx )

Get mode fault error flag.

Reference Manual to LL API cross reference:
SR MODF LL_SPI_IsActiveFlag_MODF
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 939 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR ( SPI_TypeDef * SPIx )

Get overrun error flag.

Reference Manual to LL API cross reference:
SR OVR LL_SPI_IsActiveFlag_OVR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 950 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE ( SPI_TypeDef * SPIx )

Check if Rx buffer is not empty.

Reference Manual to LL API cross reference:
SR RXNE LL_SPI_IsActiveFlag_RXNE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 906 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE ( SPI_TypeDef * SPIx )

Check if Tx buffer is empty.

Reference Manual to LL API cross reference:
SR TXE LL_SPI_IsActiveFlag_TXE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 917 of file stm32wbxx_ll_spi.h.

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Interrupt Management

Functions
Interrupt Management
SPI Exported Functions

Functions

__STATIC_INLINE void | LL_SPI_EnableIT_ERR (SPI_TypeDef *SPIx)
Enable error interrupt.
__STATIC_INLINE void | LL_SPI_EnableIT_RXNE (SPI_TypeDef *SPIx)
Enable Rx buffer not empty interrupt.
__STATIC_INLINE void | LL_SPI_EnableIT_TXE (SPI_TypeDef *SPIx)
Enable Tx buffer empty interrupt.
__STATIC_INLINE void | LL_SPI_DisableIT_ERR (SPI_TypeDef *SPIx)
Disable error interrupt.
__STATIC_INLINE void | LL_SPI_DisableIT_RXNE (SPI_TypeDef *SPIx)
Disable Rx buffer not empty interrupt.
__STATIC_INLINE void | LL_SPI_DisableIT_TXE (SPI_TypeDef *SPIx)
Disable Tx buffer empty interrupt.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_ERR (SPI_TypeDef *SPIx)
Check if error interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_RXNE (SPI_TypeDef *SPIx)
Check if Rx buffer not empty interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_TXE (SPI_TypeDef *SPIx)
Check if Tx buffer empty interrupt.

Function Documentation

__STATIC_INLINE void LL_SPI_DisableIT_ERR ( SPI_TypeDef * SPIx )

Disable error interrupt.

Note:
This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
Reference Manual to LL API cross reference:
CR2 ERRIE LL_SPI_DisableIT_ERR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1121 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE void LL_SPI_DisableIT_RXNE ( SPI_TypeDef * SPIx )

Disable Rx buffer not empty interrupt.

Reference Manual to LL API cross reference:
CR2 RXNEIE LL_SPI_DisableIT_RXNE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1132 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE void LL_SPI_DisableIT_TXE ( SPI_TypeDef * SPIx )

Disable Tx buffer empty interrupt.

Reference Manual to LL API cross reference:
CR2 TXEIE LL_SPI_DisableIT_TXE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1143 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE void LL_SPI_EnableIT_ERR ( SPI_TypeDef * SPIx )

Enable error interrupt.

Note:
This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
Reference Manual to LL API cross reference:
CR2 ERRIE LL_SPI_EnableIT_ERR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1087 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE void LL_SPI_EnableIT_RXNE ( SPI_TypeDef * SPIx )

Enable Rx buffer not empty interrupt.

Reference Manual to LL API cross reference:
CR2 RXNEIE LL_SPI_EnableIT_RXNE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1098 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE void LL_SPI_EnableIT_TXE ( SPI_TypeDef * SPIx )

Enable Tx buffer empty interrupt.

Reference Manual to LL API cross reference:
CR2 TXEIE LL_SPI_EnableIT_TXE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1109 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR ( SPI_TypeDef * SPIx )

Check if error interrupt is enabled.

Reference Manual to LL API cross reference:
CR2 ERRIE LL_SPI_IsEnabledIT_ERR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1154 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE ( SPI_TypeDef * SPIx )

Check if Rx buffer not empty interrupt is enabled.

Reference Manual to LL API cross reference:
CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1165 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE ( SPI_TypeDef * SPIx )

Check if Tx buffer empty interrupt.

Reference Manual to LL API cross reference:
CR2 TXEIE LL_SPI_IsEnabledIT_TXE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1176 of file stm32wbxx_ll_spi.h.

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DMA Management

Functions
DMA Management
SPI Exported Functions

Functions

__STATIC_INLINE void | LL_SPI_EnableDMAReq_RX (SPI_TypeDef *SPIx)
Enable DMA Rx.
__STATIC_INLINE void | LL_SPI_DisableDMAReq_RX (SPI_TypeDef *SPIx)
Disable DMA Rx.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledDMAReq_RX (SPI_TypeDef *SPIx)
Check if DMA Rx is enabled.
__STATIC_INLINE void | LL_SPI_EnableDMAReq_TX (SPI_TypeDef *SPIx)
Enable DMA Tx.
__STATIC_INLINE void | LL_SPI_DisableDMAReq_TX (SPI_TypeDef *SPIx)
Disable DMA Tx.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledDMAReq_TX (SPI_TypeDef *SPIx)
Check if DMA Tx is enabled.
__STATIC_INLINE void | LL_SPI_SetDMAParity_RX (SPI_TypeDef *SPIx, uint32_t Parity)
Set parity of Last DMA reception.
__STATIC_INLINE uint32_t | LL_SPI_GetDMAParity_RX (SPI_TypeDef *SPIx)
Get parity configuration for Last DMA reception.
__STATIC_INLINE void | LL_SPI_SetDMAParity_TX (SPI_TypeDef *SPIx, uint32_t Parity)
Set parity of Last DMA transmission.
__STATIC_INLINE uint32_t | LL_SPI_GetDMAParity_TX (SPI_TypeDef *SPIx)
Get parity configuration for Last DMA transmission.
__STATIC_INLINE uint32_t | LL_SPI_DMA_GetRegAddr (SPI_TypeDef *SPIx)
Get the data register address used for DMA transfer.

Function Documentation

__STATIC_INLINE void LL_SPI_DisableDMAReq_RX ( SPI_TypeDef * SPIx )

Disable DMA Rx.

Reference Manual to LL API cross reference:
CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1206 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE void LL_SPI_DisableDMAReq_TX ( SPI_TypeDef * SPIx )

Disable DMA Tx.

Reference Manual to LL API cross reference:
CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1239 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr ( SPI_TypeDef * SPIx )

Get the data register address used for DMA transfer.

Reference Manual to LL API cross reference:
DR DR LL_SPI_DMA_GetRegAddr
Parameters:
SPIx SPI Instance
Return values:
Address of data register

Definition at line 1315 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE void LL_SPI_EnableDMAReq_RX ( SPI_TypeDef * SPIx )

Enable DMA Rx.

Reference Manual to LL API cross reference:
CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1195 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE void LL_SPI_EnableDMAReq_TX ( SPI_TypeDef * SPIx )

Enable DMA Tx.

Reference Manual to LL API cross reference:
CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 1228 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX ( SPI_TypeDef * SPIx )

Get parity configuration for Last DMA reception.

Reference Manual to LL API cross reference:
CR2 LDMARX LL_SPI_GetDMAParity_RX
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_DMA_PARITY_ODD
  • LL_SPI_DMA_PARITY_EVEN

Definition at line 1277 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX ( SPI_TypeDef * SPIx )

Get parity configuration for Last DMA transmission.

Reference Manual to LL API cross reference:
CR2 LDMATX LL_SPI_GetDMAParity_TX
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_DMA_PARITY_ODD
  • LL_SPI_DMA_PARITY_EVEN

Definition at line 1304 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX ( SPI_TypeDef * SPIx )

Check if DMA Rx is enabled.

Reference Manual to LL API cross reference:
CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1217 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX ( SPI_TypeDef * SPIx )

Check if DMA Tx is enabled.

Reference Manual to LL API cross reference:
CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1250 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetDMAParity_RX | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Parity
 | ) |  |

Set parity of Last DMA reception.

Reference Manual to LL API cross reference:
CR2 LDMARX LL_SPI_SetDMAParity_RX
Parameters:
SPIx SPI Instance
Parity This parameter can be one of the following values:
  • LL_SPI_DMA_PARITY_ODD
  • LL_SPI_DMA_PARITY_EVEN
Return values:
None

Definition at line 1264 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetDMAParity_TX | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Parity
 | ) |  |

Set parity of Last DMA transmission.

Reference Manual to LL API cross reference:
CR2 LDMATX LL_SPI_SetDMAParity_TX
Parameters:
SPIx SPI Instance
Parity This parameter can be one of the following values:
  • LL_SPI_DMA_PARITY_ODD
  • LL_SPI_DMA_PARITY_EVEN
Return values:
None

Definition at line 1291 of file stm32wbxx_ll_spi.h.

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DATA Management

Functions
DATA Management
SPI Exported Functions

Functions

__STATIC_INLINE uint8_t | LL_SPI_ReceiveData8 (SPI_TypeDef *SPIx)
Read 8-Bits in the data register.
__STATIC_INLINE uint16_t | LL_SPI_ReceiveData16 (SPI_TypeDef *SPIx)
Read 16-Bits in the data register.
__STATIC_INLINE void | LL_SPI_TransmitData8 (SPI_TypeDef *SPIx, uint8_t TxData)
Write 8-Bits in the data register.
__STATIC_INLINE void | LL_SPI_TransmitData16 (SPI_TypeDef *SPIx, uint16_t TxData)
Write 16-Bits in the data register.

Function Documentation

__STATIC_INLINE uint16_t LL_SPI_ReceiveData16 ( SPI_TypeDef * SPIx )

Read 16-Bits in the data register.

Reference Manual to LL API cross reference:
DR DR LL_SPI_ReceiveData16
Parameters:
SPIx SPI Instance
Return values:
RxData Value between Min_Data=0x00 and Max_Data=0xFFFF

Definition at line 1345 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE uint8_t LL_SPI_ReceiveData8 ( SPI_TypeDef * SPIx )

Read 8-Bits in the data register.

Reference Manual to LL API cross reference:
DR DR LL_SPI_ReceiveData8
Parameters:
SPIx SPI Instance
Return values:
RxData Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 1334 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE void LL_SPI_TransmitData16 | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | TxData
 | ) |  |

Write 16-Bits in the data register.

Reference Manual to LL API cross reference:
DR DR LL_SPI_TransmitData16
Parameters:
SPIx | SPI Instance
TxData | Value between Min_Data=0x00 and Max_Data=0xFFFF
Return values:
None

Definition at line 1374 of file stm32wbxx_ll_spi.h.

__STATIC_INLINE void LL_SPI_TransmitData8 | ( | SPI_TypeDef * | SPIx,
 |  | uint8_t | TxData
 | ) |  |

Write 8-Bits in the data register.

Reference Manual to LL API cross reference:
DR DR LL_SPI_TransmitData8
Parameters:
SPIx | SPI Instance
TxData | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 1357 of file stm32wbxx_ll_spi.h.

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SPI Exported Functions

Functions

ErrorStatus | LL_SPI_DeInit (SPI_TypeDef *SPIx)
De-initialize the SPI registers to their default reset values.
ErrorStatus | LL_SPI_Init (SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
void | LL_SPI_StructInit (LL_SPI_InitTypeDef *SPI_InitStruct)
Set each LL_SPI_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_SPI_DeInit ( SPI_TypeDef * SPIx )

De-initialize the SPI registers to their default reset values.

Parameters:
SPIx SPI Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: SPI registers are de-initialized
  • ERROR: SPI registers are not de-initialized

Definition at line 133 of file stm32wbxx_ll_spi.c.

References assert_param, LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_SPI2, LL_APB1_GRP1_ReleaseReset(), LL_APB2_GRP1_ForceReset(), LL_APB2_GRP1_PERIPH_SPI1, and LL_APB2_GRP1_ReleaseReset().

ErrorStatus LL_SPI_Init | ( | SPI_TypeDef * | SPIx,
 |  | LL_SPI_InitTypeDef * | SPI_InitStruct
 | ) |  |

Initialize the SPI registers according to the specified parameters in SPI_InitStruct.

Note:
As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
Parameters:
SPIx | SPI Instance
SPI_InitStruct | pointer to a LL_SPI_InitTypeDef structure
Return values:
An ErrorStatus enumeration value. (Return always SUCCESS)

Definition at line 176 of file stm32wbxx_ll_spi.c.

References assert_param, LL_SPI_InitTypeDef::BaudRate, LL_SPI_InitTypeDef::BitOrder, LL_SPI_InitTypeDef::ClockPhase, LL_SPI_InitTypeDef::ClockPolarity, LL_SPI_InitTypeDef::CRCCalculation, LL_SPI_InitTypeDef::CRCPoly, LL_SPI_InitTypeDef::DataWidth, IS_LL_SPI_BAUDRATE, IS_LL_SPI_BITORDER, IS_LL_SPI_CRC_POLYNOMIAL, IS_LL_SPI_CRCCALCULATION, IS_LL_SPI_DATAWIDTH, IS_LL_SPI_MODE, IS_LL_SPI_NSS, IS_LL_SPI_PHASE, IS_LL_SPI_POLARITY, IS_LL_SPI_TRANSFER_DIRECTION, LL_SPI_CRCCALCULATION_ENABLE, LL_SPI_IsEnabled(), LL_SPI_SetCRCPolynomial(), LL_SPI_InitTypeDef::Mode, LL_SPI_InitTypeDef::NSS, SPI_CR1_CLEAR_MASK, and LL_SPI_InitTypeDef::TransferDirection.

void LL_SPI_StructInit ( LL_SPI_InitTypeDef * SPI_InitStruct )

Set each LL_SPI_InitTypeDef field to default value.

Parameters:
SPI_InitStruct pointer to a LL_SPI_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 244 of file stm32wbxx_ll_spi.c.

References LL_SPI_InitTypeDef::BaudRate, LL_SPI_InitTypeDef::BitOrder, LL_SPI_InitTypeDef::ClockPhase, LL_SPI_InitTypeDef::ClockPolarity, LL_SPI_InitTypeDef::CRCCalculation, LL_SPI_InitTypeDef::CRCPoly, LL_SPI_InitTypeDef::DataWidth, LL_SPI_BAUDRATEPRESCALER_DIV2, LL_SPI_CRCCALCULATION_DISABLE, LL_SPI_DATAWIDTH_8BIT, LL_SPI_FULL_DUPLEX, LL_SPI_MODE_SLAVE, LL_SPI_MSB_FIRST, LL_SPI_NSS_HARD_INPUT, LL_SPI_PHASE_1EDGE, LL_SPI_POLARITY_LOW, LL_SPI_InitTypeDef::Mode, LL_SPI_InitTypeDef::NSS, and LL_SPI_InitTypeDef::TransferDirection.

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SYSTEM

Modules
SYSTEM
STM32WBxx_LL_Driver

Modules

SYSTEM Private Constants
SYSTEM Exported Constants
SYSTEM Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for SYSTEM registers.

Register | Bit | Function
DBGMCU_APB1FZR1 | DBG_xxxx_STOP | LL_DBGMCU_APB1_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB1_GRP1_UnFreezePeriph
DBGMCU_APB1FZR2 | DBG_xxxx_STOP | LL_DBGMCU_APB1_GRP2_FreezePeriph
 |  | LL_DBGMCU_APB1_GRP2_UnFreezePeriph
DBGMCU_APB2FZR | DBG_TIMx_STOP | LL_DBGMCU_APB2_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB2_GRP1_UnFreezePeriph
DBGMCU_C2APB1FZR1 | DBG_xxxx_STOP | LL_C2_DBGMCU_APB1_GRP1_FreezePeriph
 |  | LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph
DBGMCU_C2APB1FZR2 | DBG_xxxx_STOP | LL_C2_DBGMCU_APB1_GRP2_FreezePeriph
 |  | LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph
DBGMCU_C2APB2FZR | DBG_TIMx_STOP | LL_C2_DBGMCU_APB2_GRP1_FreezePeriph
 |  | LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph
DBGMCU_CR | DBG_SLEEP | LL_DBGMCU_DisableDBGSleepMode
 |  | LL_DBGMCU_EnableDBGSleepMode
 | DBG_STANDBY | LL_DBGMCU_DisableDBGStandbyMode
 |  | LL_DBGMCU_EnableDBGStandbyMode
 | DBG_STOP | LL_DBGMCU_DisableDBGStopMode
 |  | LL_DBGMCU_EnableDBGStopMode
 | TRACE_CLKEN | LL_DBGMCU_DisableTraceClock
 |  | LL_DBGMCU_EnableTraceClock
 |  | LL_DBGMCU_IsEnabledTraceClock
 | TRGOEN | LL_DBGMCU_DisableTriggerOutput
 |  | LL_DBGMCU_EnableTriggerOutput
DBGMCU_IDCODE | DEV_ID | LL_DBGMCU_GetDeviceID
 | REV_ID | LL_DBGMCU_GetRevisionID
FLASH_ACR | DCEN | LL_FLASH_DisableDataCache
 |  | LL_FLASH_EnableDataCache
 | DCRST | LL_FLASH_DisableDataCacheReset
 |  | LL_FLASH_EnableDataCacheReset
 | EMPTY | LL_FLASH_ClearEmptyFlag
 |  | LL_FLASH_IsEmptyFlag
 |  | LL_FLASH_SetEmptyFlag
 | ICEN | LL_FLASH_DisableInstCache
 |  | LL_FLASH_EnableInstCache
 | ICRST | LL_FLASH_DisableInstCacheReset
 |  | LL_FLASH_EnableInstCacheReset
 | LATENCY | LL_FLASH_GetLatency
 |  | LL_FLASH_SetLatency
 | PES | LL_FLASH_AllowOperation
 |  | LL_FLASH_IsOperationSuspended
 |  | LL_FLASH_SuspendOperation
 | PRFTEN | LL_FLASH_DisablePrefetch
 |  | LL_FLASH_EnablePrefetch
 |  | LL_FLASH_IsPrefetchEnabled
FLASH_C2ACR | C2PRFTEN | LL_FLASH_IsPrefetchEnabled
 | ICEN | LL_FLASH_DisableInstCache
 |  | LL_FLASH_EnableInstCache
 | ICRST | LL_FLASH_DisableInstCacheReset
 |  | LL_FLASH_EnableInstCacheReset
 | PES | LL_FLASH_AllowOperation
 |  | LL_FLASH_IsOperationSuspended
 |  | LL_FLASH_SuspendOperation
 | PRFTEN | LL_FLASH_DisablePrefetch
FLASH_C2SR | PESD | LL_FLASH_IsActiveFlag_OperationSuspended
FLASH_IPCCBR | IPCCDBA | LL_FLASH_GetIPCCBufferAddr
FLASH_SR | PESD | LL_FLASH_IsActiveFlag_OperationSuspended
FLASH_SRRVR | SBRV | LL_FLASH_GetC2BootResetVect
SYSCFG_C2IMR1 | ADCIM | LL_C2_SYSCFG_GRP1_DisableIT
 |  | LL_C2_SYSCFG_GRP1_EnableIT
 |  | LL_C2_SYSCFG_GRP1_IsEnabledIT
 | AES1IM | LL_C2_SYSCFG_GRP1_DisableIT
 |  | LL_C2_SYSCFG_GRP1_EnableIT
 |  | LL_C2_SYSCFG_GRP1_IsEnabledIT
 | COMPIM | LL_C2_SYSCFG_GRP1_DisableIT
 |  | LL_C2_SYSCFG_GRP1_EnableIT
 |  | LL_C2_SYSCFG_GRP1_IsEnabledIT
 | EXTIxIM | LL_C2_SYSCFG_GRP1_DisableIT
 |  | LL_C2_SYSCFG_GRP1_EnableIT
 |  | LL_C2_SYSCFG_GRP1_IsEnabledIT
 | FLASHIM | LL_C2_SYSCFG_GRP1_DisableIT
 |  | LL_C2_SYSCFG_GRP1_EnableIT
 |  | LL_C2_SYSCFG_GRP1_IsEnabledIT
 | PKAIM | LL_C2_SYSCFG_GRP1_DisableIT
 |  | LL_C2_SYSCFG_GRP1_EnableIT
 |  | LL_C2_SYSCFG_GRP1_IsEnabledIT
 | RCCIM | LL_C2_SYSCFG_GRP1_DisableIT
 |  | LL_C2_SYSCFG_GRP1_EnableIT
 |  | LL_C2_SYSCFG_GRP1_IsEnabledIT
 | RNGIM | LL_C2_SYSCFG_GRP1_DisableIT
 |  | LL_C2_SYSCFG_GRP1_EnableIT
 |  | LL_C2_SYSCFG_GRP1_IsEnabledIT
 | RTCALARMIM | LL_C2_SYSCFG_GRP1_DisableIT
 |  | LL_C2_SYSCFG_GRP1_EnableIT
 |  | LL_C2_SYSCFG_GRP1_IsEnabledIT
 | RTCSTAMPTAMPLSECSSIM | LL_C2_SYSCFG_GRP1_DisableIT
 |  | LL_C2_SYSCFG_GRP1_EnableIT
 | RTCWKUPIM | LL_C2_SYSCFG_GRP1_DisableIT
 |  | LL_C2_SYSCFG_GRP1_EnableIT
 |  | LL_C2_SYSCFG_GRP1_IsEnabledIT
SYSCFG_C2IMR2 | DMA1CHxIM | LL_C2_SYSCFG_GRP2_DisableIT
 |  | LL_C2_SYSCFG_GRP2_EnableIT
 |  | LL_C2_SYSCFG_GRP2_IsEnabledIT
 | DMA2CHxIM | LL_C2_SYSCFG_GRP2_DisableIT
 |  | LL_C2_SYSCFG_GRP2_EnableIT
 |  | LL_C2_SYSCFG_GRP2_IsEnabledIT
 | LCDIM | LL_C2_SYSCFG_GRP2_DisableIT
 |  | LL_C2_SYSCFG_GRP2_EnableIT
 |  | LL_C2_SYSCFG_GRP2_IsEnabledIT
 | PVDIM | LL_C2_SYSCFG_GRP2_DisableIT
 |  | LL_C2_SYSCFG_GRP2_EnableIT
 |  | LL_C2_SYSCFG_GRP2_IsEnabledIT
 | PVM1IM | LL_C2_SYSCFG_GRP2_DisableIT
 |  | LL_C2_SYSCFG_GRP2_EnableIT
 |  | LL_C2_SYSCFG_GRP2_IsEnabledIT
 | PVM3IM | LL_C2_SYSCFG_GRP2_DisableIT
 |  | LL_C2_SYSCFG_GRP2_EnableIT
 |  | LL_C2_SYSCFG_GRP2_IsEnabledIT
 | TSCIM | LL_C2_SYSCFG_GRP2_DisableIT
 |  | LL_C2_SYSCFG_GRP2_EnableIT
 |  | LL_C2_SYSCFG_GRP2_IsEnabledIT
SYSCFG_CFGR1 | ANASWVDD | LL_SYSCFG_DisableAnalogGpioSwitch
 |  | LL_SYSCFG_EnableAnalogGpioSwitch
 | BOOSTEN | LL_SYSCFG_DisableAnalogBooster
 |  | LL_SYSCFG_EnableAnalogBooster
 | FPU_IE_0 | LL_SYSCFG_DisableIT_FPU_IOC
 |  | LL_SYSCFG_EnableIT_FPU_IOC
 |  | LL_SYSCFG_IsEnabledIT_FPU_IOC
 | FPU_IE_1 | LL_SYSCFG_DisableIT_FPU_DZC
 |  | LL_SYSCFG_EnableIT_FPU_DZC
 |  | LL_SYSCFG_IsEnabledIT_FPU_DZC
 | FPU_IE_2 | LL_SYSCFG_DisableIT_FPU_UFC
 |  | LL_SYSCFG_EnableIT_FPU_UFC
 |  | LL_SYSCFG_IsEnabledIT_FPU_UFC
 | FPU_IE_3 | LL_SYSCFG_DisableIT_FPU_OFC
 |  | LL_SYSCFG_EnableIT_FPU_OFC
 |  | LL_SYSCFG_IsEnabledIT_FPU_OFC
 | FPU_IE_4 | LL_SYSCFG_DisableIT_FPU_IDC
 |  | LL_SYSCFG_EnableIT_FPU_IDC
 |  | LL_SYSCFG_IsEnabledIT_FPU_IDC
 | FPU_IE_5 | LL_SYSCFG_DisableIT_FPU_IXC
 |  | LL_SYSCFG_EnableIT_FPU_IXC
 |  | LL_SYSCFG_IsEnabledIT_FPU_IXC
 | I2C_PBx_FMP | LL_SYSCFG_DisableFastModePlus
 |  | LL_SYSCFG_EnableFastModePlus
 | I2Cx_FMP | LL_SYSCFG_DisableFastModePlus
 |  | LL_SYSCFG_EnableFastModePlus
 | SAES2 | LL_SYSCFG_DisableSecurityAccess
 |  | LL_SYSCFG_EnableSecurityAccess
 |  | LL_SYSCFG_IsEnabledSecurityAccess
 | SPKA | LL_SYSCFG_DisableSecurityAccess
 |  | LL_SYSCFG_EnableSecurityAccess
 |  | LL_SYSCFG_IsEnabledSecurityAccess
 | SRNG | LL_SYSCFG_DisableSecurityAccess
 |  | LL_SYSCFG_EnableSecurityAccess
 |  | LL_SYSCFG_IsEnabledSecurityAccess
SYSCFG_CFGR2 | CLL | LL_SYSCFG_GetTIMBreakInputs
 |  | LL_SYSCFG_SetTIMBreakInputs
 | ECCL | LL_SYSCFG_GetTIMBreakInputs
 |  | LL_SYSCFG_SetTIMBreakInputs
 | PVDL | LL_SYSCFG_GetTIMBreakInputs
 |  | LL_SYSCFG_SetTIMBreakInputs
 | SPF | LL_SYSCFG_ClearFlag_SP
 |  | LL_SYSCFG_IsActiveFlag_SP
 | SPL | LL_SYSCFG_GetTIMBreakInputs
 |  | LL_SYSCFG_SetTIMBreakInputs
SYSCFG_EXTICR1 | EXTIx | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR2 | EXTIx | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR3 | EXTIx | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR4 | EXTIx | LL_SYSCFG_GetEXTISource
 |  | LL_SYSCFG_SetEXTISource
SYSCFG_IMR1 | EXTIxIM | LL_SYSCFG_GRP1_DisableIT
 |  | LL_SYSCFG_GRP1_EnableIT
 |  | LL_SYSCFG_GRP1_IsEnabledIT
 | PVDIM | LL_SYSCFG_GRP2_EnableIT
 | PVM1IM | LL_SYSCFG_GRP2_EnableIT
 | PVM3IM | LL_SYSCFG_GRP2_EnableIT
 | TIM16IM | LL_SYSCFG_GRP1_DisableIT
 |  | LL_SYSCFG_GRP1_EnableIT
 |  | LL_SYSCFG_GRP1_IsEnabledIT
 | TIM17IM | LL_SYSCFG_GRP1_DisableIT
 |  | LL_SYSCFG_GRP1_EnableIT
 |  | LL_SYSCFG_GRP1_IsEnabledIT
 | TIM1IM | LL_SYSCFG_GRP1_DisableIT
 |  | LL_SYSCFG_GRP1_EnableIT
 |  | LL_SYSCFG_GRP1_IsEnabledIT
SYSCFG_IMR2 | PVDIM | LL_SYSCFG_GRP2_DisableIT
 |  | LL_SYSCFG_GRP2_IsEnabledIT
 | PVM1IM | LL_SYSCFG_GRP2_DisableIT
 |  | LL_SYSCFG_GRP2_IsEnabledIT
 | PVM3IM | LL_SYSCFG_GRP2_DisableIT
 |  | LL_SYSCFG_GRP2_IsEnabledIT
SYSCFG_MEMRMP | MEM_MODE | LL_SYSCFG_GetRemapMemory
 |  | LL_SYSCFG_SetRemapMemory
SYSCFG_SCSR | C2RFD | LL_SYSCFG_DisableSRAMFetch
 |  | LL_SYSCFG_IsEnabledSRAMFetch
 | SRAM2BSY | LL_SYSCFG_IsSRAM2EraseOngoing
 | SRAM2ER | LL_SYSCFG_EnableSRAM2Erase
SYSCFG_SIPCR | SAES1 | LL_SYSCFG_DisableSecurityAccess
 |  | LL_SYSCFG_EnableSecurityAccess
 |  | LL_SYSCFG_IsEnabledSecurityAccess
SYSCFG_SKR | KEY | LL_SYSCFG_LockSRAM2WRP
 |  | LL_SYSCFG_UnlockSRAM2WRP
SYSCFG_SWPR1 | PxWP | LL_SYSCFG_EnableSRAM2PageWRP_0_31
SYSCFG_SWPR2 | PxWP | LL_SYSCFG_EnableSRAM2PageWRP_32_63
VREFBUF_CCR | TRIM | LL_VREFBUF_GetTrimming
 |  | LL_VREFBUF_SetTrimming
VREFBUF_CSR | ENVR | LL_VREFBUF_Disable
 |  | LL_VREFBUF_Enable
 | HIZ | LL_VREFBUF_DisableHIZ
 |  | LL_VREFBUF_EnableHIZ
 | VRR | LL_VREFBUF_IsVREFReady
 | VRS | LL_VREFBUF_GetVoltageScaling
 |  | LL_VREFBUF_SetVoltageScaling
Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SYSTEM Private Constants

SYSTEM Private Constants
SYSTEM
Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SYSCFG REMAP

Defines
SYSCFG REMAP
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_REMAP_FLASH 0x00000000U
#define | LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0
#define | LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0)
#define | LL_SYSCFG_REMAP_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1)

Define Documentation

#define LL_SYSCFG_REMAP_FLASH 0x00000000U

Main Flash memory mapped at 0x00000000

Definition at line 77 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_REMAP_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1)

QUADSPI memory mapped at 0x00000000

Definition at line 81 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0)

SRAM1 mapped at 0x00000000

Definition at line 79 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0

System Flash memory mapped at 0x00000000

Definition at line 78 of file stm32wbxx_ll_system.h.

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SYSCFG I2C FASTMODEPLUS

Defines
SYSCFG I2C FASTMODEPLUS
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP

Define Documentation

#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP

Enable Fast Mode Plus on I2C1 pins

Definition at line 94 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP

Enable Fast Mode Plus on I2C3 pins

Definition at line 96 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP

Enable Fast Mode Plus on PB6

Definition at line 90 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP

Enable Fast Mode Plus on PB7

Definition at line 91 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP

Enable Fast Mode Plus on PB8

Definition at line 92 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP

Enable Fast Mode Plus on PB9

Definition at line 93 of file stm32wbxx_ll_system.h.

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SYSCFG EXTI PORT

Defines
SYSCFG EXTI PORT
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_EXTI_PORTA 0U
#define | LL_SYSCFG_EXTI_PORTB 1U
#define | LL_SYSCFG_EXTI_PORTC 2U
#define | LL_SYSCFG_EXTI_PORTD 3U
#define | LL_SYSCFG_EXTI_PORTE 4U
#define | LL_SYSCFG_EXTI_PORTH 7U

Define Documentation

#define LL_SYSCFG_EXTI_PORTA 0U

EXTI PORT A

Definition at line 105 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_EXTI_PORTB 1U

EXTI PORT B

Definition at line 106 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_EXTI_PORTC 2U

EXTI PORT C

Definition at line 107 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_EXTI_PORTD 3U

EXTI PORT D

Definition at line 108 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_EXTI_PORTE 4U

EXTI PORT E

Definition at line 109 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_EXTI_PORTH 7U

EXTI PORT H

Definition at line 110 of file stm32wbxx_ll_system.h.

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SYSCFG EXTI LINE

Defines
SYSCFG EXTI LINE
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_EXTI_LINE0 (uint32_t)((0x000FU << 16U) | 0U)
#define | LL_SYSCFG_EXTI_LINE1 (uint32_t)((0x00F0U << 16U) | 0U)
#define | LL_SYSCFG_EXTI_LINE2 (uint32_t)((0x0F00U << 16U) | 0U)
#define | LL_SYSCFG_EXTI_LINE3 (uint32_t)((0xF000U << 16U) | 0U)
#define | LL_SYSCFG_EXTI_LINE4 (uint32_t)((0x000FU << 16U) | 1U)
#define | LL_SYSCFG_EXTI_LINE5 (uint32_t)((0x00F0U << 16U) | 1U)
#define | LL_SYSCFG_EXTI_LINE6 (uint32_t)((0x0F00U << 16U) | 1U)
#define | LL_SYSCFG_EXTI_LINE7 (uint32_t)((0xF000U << 16U) | 1U)
#define | LL_SYSCFG_EXTI_LINE8 (uint32_t)((0x000FU << 16U) | 2U)
#define | LL_SYSCFG_EXTI_LINE9 (uint32_t)((0x00F0U << 16U) | 2U)
#define | LL_SYSCFG_EXTI_LINE10 (uint32_t)((0x0F00U << 16U) | 2U)
#define | LL_SYSCFG_EXTI_LINE11 (uint32_t)((0xF000U << 16U) | 2U)
#define | LL_SYSCFG_EXTI_LINE12 (uint32_t)((0x000FU << 16U) | 3U)
#define | LL_SYSCFG_EXTI_LINE13 (uint32_t)((0x00F0U << 16U) | 3U)
#define | LL_SYSCFG_EXTI_LINE14 (uint32_t)((0x0F00U << 16U) | 3U)
#define | LL_SYSCFG_EXTI_LINE15 (uint32_t)((0xF000U << 16U) | 3U)

Define Documentation

#define LL_SYSCFG_EXTI_LINE0 (uint32_t)((0x000FU << 16U) | 0U)

EXTI_POSITION_0 | EXTICR[0]

Definition at line 118 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE1 (uint32_t)((0x00F0U << 16U) | 0U)

EXTI_POSITION_4 | EXTICR[0]

Definition at line 119 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE10 (uint32_t)((0x0F00U << 16U) | 2U)

EXTI_POSITION_8 | EXTICR[2]

Definition at line 128 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE11 (uint32_t)((0xF000U << 16U) | 2U)

EXTI_POSITION_12 | EXTICR[2]

Definition at line 129 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE12 (uint32_t)((0x000FU << 16U) | 3U)

EXTI_POSITION_0 | EXTICR[3]

Definition at line 130 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE13 (uint32_t)((0x00F0U << 16U) | 3U)

EXTI_POSITION_4 | EXTICR[3]

Definition at line 131 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE14 (uint32_t)((0x0F00U << 16U) | 3U)

EXTI_POSITION_8 | EXTICR[3]

Definition at line 132 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE15 (uint32_t)((0xF000U << 16U) | 3U)

EXTI_POSITION_12 | EXTICR[3]

Definition at line 133 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE2 (uint32_t)((0x0F00U << 16U) | 0U)

EXTI_POSITION_8 | EXTICR[0]

Definition at line 120 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE3 (uint32_t)((0xF000U << 16U) | 0U)

EXTI_POSITION_12 | EXTICR[0]

Definition at line 121 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE4 (uint32_t)((0x000FU << 16U) | 1U)

EXTI_POSITION_0 | EXTICR[1]

Definition at line 122 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE5 (uint32_t)((0x00F0U << 16U) | 1U)

EXTI_POSITION_4 | EXTICR[1]

Definition at line 123 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE6 (uint32_t)((0x0F00U << 16U) | 1U)

EXTI_POSITION_8 | EXTICR[1]

Definition at line 124 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE7 (uint32_t)((0xF000U << 16U) | 1U)

EXTI_POSITION_12 | EXTICR[1]

Definition at line 125 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE8 (uint32_t)((0x000FU << 16U) | 2U)

EXTI_POSITION_0 | EXTICR[2]

Definition at line 126 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_EXTI_LINE9 (uint32_t)((0x00F0U << 16U) | 2U)

EXTI_POSITION_4 | EXTICR[2]

Definition at line 127 of file stm32wbxx_ll_system.h.

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SYSCFG TIMER BREAK

Defines
SYSCFG TIMER BREAK
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL
#define | LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL
#define | LL_SYSCFG_TIMBREAK_SRAM2_PARITY SYSCFG_CFGR2_SPL
#define | LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL

Define Documentation

#define LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL

Enables and locks the ECC error signal with Break Input of TIM1/16/17

Definition at line 141 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL

Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/16/17

Definition at line 148 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL

Enables and locks the PVD connection with TIM1/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface

Definition at line 143 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_TIMBREAK_SRAM2_PARITY SYSCFG_CFGR2_SPL

Enables and locks the SRAM2_PARITY error signal with Break Input of TIM1/16/17

Definition at line 146 of file stm32wbxx_ll_system.h.

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SYSCFG SRAM2 WRITE PROTECTION

Defines
SYSCFG SRAM2 WRITE PROTECTION
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR1_PAGE0
#define | LL_SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR1_PAGE1
#define | LL_SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR1_PAGE2
#define | LL_SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR1_PAGE3
#define | LL_SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR1_PAGE4
#define | LL_SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR1_PAGE5
#define | LL_SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR1_PAGE6
#define | LL_SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR1_PAGE7
#define | LL_SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR1_PAGE8
#define | LL_SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR1_PAGE9
#define | LL_SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR1_PAGE10
#define | LL_SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR1_PAGE11
#define | LL_SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR1_PAGE12
#define | LL_SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR1_PAGE13
#define | LL_SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR1_PAGE14
#define | LL_SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR1_PAGE15
#define | LL_SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR1_PAGE16
#define | LL_SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR1_PAGE17
#define | LL_SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR1_PAGE18
#define | LL_SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR1_PAGE19
#define | LL_SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR1_PAGE20
#define | LL_SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR1_PAGE21
#define | LL_SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR1_PAGE22
#define | LL_SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR1_PAGE23
#define | LL_SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR1_PAGE24
#define | LL_SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR1_PAGE25
#define | LL_SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR1_PAGE26
#define | LL_SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR1_PAGE27
#define | LL_SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR1_PAGE28
#define | LL_SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR1_PAGE29
#define | LL_SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR1_PAGE30
#define | LL_SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR1_PAGE31
#define | LL_SYSCFG_SRAM2WRP_PAGE32 SYSCFG_SWPR2_PAGE32
#define | LL_SYSCFG_SRAM2WRP_PAGE33 SYSCFG_SWPR2_PAGE33
#define | LL_SYSCFG_SRAM2WRP_PAGE34 SYSCFG_SWPR2_PAGE34
#define | LL_SYSCFG_SRAM2WRP_PAGE35 SYSCFG_SWPR2_PAGE35
#define | LL_SYSCFG_SRAM2WRP_PAGE36 SYSCFG_SWPR2_PAGE36
#define | LL_SYSCFG_SRAM2WRP_PAGE37 SYSCFG_SWPR2_PAGE37
#define | LL_SYSCFG_SRAM2WRP_PAGE38 SYSCFG_SWPR2_PAGE38
#define | LL_SYSCFG_SRAM2WRP_PAGE39 SYSCFG_SWPR2_PAGE39
#define | LL_SYSCFG_SRAM2WRP_PAGE40 SYSCFG_SWPR2_PAGE40
#define | LL_SYSCFG_SRAM2WRP_PAGE41 SYSCFG_SWPR2_PAGE41
#define | LL_SYSCFG_SRAM2WRP_PAGE42 SYSCFG_SWPR2_PAGE42
#define | LL_SYSCFG_SRAM2WRP_PAGE43 SYSCFG_SWPR2_PAGE43
#define | LL_SYSCFG_SRAM2WRP_PAGE44 SYSCFG_SWPR2_PAGE44
#define | LL_SYSCFG_SRAM2WRP_PAGE45 SYSCFG_SWPR2_PAGE45
#define | LL_SYSCFG_SRAM2WRP_PAGE46 SYSCFG_SWPR2_PAGE46
#define | LL_SYSCFG_SRAM2WRP_PAGE47 SYSCFG_SWPR2_PAGE47
#define | LL_SYSCFG_SRAM2WRP_PAGE48 SYSCFG_SWPR2_PAGE48
#define | LL_SYSCFG_SRAM2WRP_PAGE49 SYSCFG_SWPR2_PAGE49
#define | LL_SYSCFG_SRAM2WRP_PAGE50 SYSCFG_SWPR2_PAGE50
#define | LL_SYSCFG_SRAM2WRP_PAGE51 SYSCFG_SWPR2_PAGE51
#define | LL_SYSCFG_SRAM2WRP_PAGE52 SYSCFG_SWPR2_PAGE52
#define | LL_SYSCFG_SRAM2WRP_PAGE53 SYSCFG_SWPR2_PAGE53
#define | LL_SYSCFG_SRAM2WRP_PAGE54 SYSCFG_SWPR2_PAGE54
#define | LL_SYSCFG_SRAM2WRP_PAGE55 SYSCFG_SWPR2_PAGE55
#define | LL_SYSCFG_SRAM2WRP_PAGE56 SYSCFG_SWPR2_PAGE56
#define | LL_SYSCFG_SRAM2WRP_PAGE57 SYSCFG_SWPR2_PAGE57
#define | LL_SYSCFG_SRAM2WRP_PAGE58 SYSCFG_SWPR2_PAGE58
#define | LL_SYSCFG_SRAM2WRP_PAGE59 SYSCFG_SWPR2_PAGE59
#define | LL_SYSCFG_SRAM2WRP_PAGE60 SYSCFG_SWPR2_PAGE60
#define | LL_SYSCFG_SRAM2WRP_PAGE61 SYSCFG_SWPR2_PAGE61
#define | LL_SYSCFG_SRAM2WRP_PAGE62 SYSCFG_SWPR2_PAGE62
#define | LL_SYSCFG_SRAM2WRP_PAGE63 SYSCFG_SWPR2_PAGE63

Define Documentation

#define LL_SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR1_PAGE0

SRAM2A Write protection page 0

Definition at line 157 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR1_PAGE1

SRAM2A Write protection page 1

Definition at line 158 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR1_PAGE10

SRAM2A Write protection page 10

Definition at line 167 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR1_PAGE11

SRAM2A Write protection page 11

Definition at line 168 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR1_PAGE12

SRAM2A Write protection page 12

Definition at line 169 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR1_PAGE13

SRAM2A Write protection page 13

Definition at line 170 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR1_PAGE14

SRAM2A Write protection page 14

Definition at line 171 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR1_PAGE15

SRAM2A Write protection page 15

Definition at line 172 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR1_PAGE16

SRAM2A Write protection page 16

Definition at line 173 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR1_PAGE17

SRAM2A Write protection page 17

Definition at line 174 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR1_PAGE18

SRAM2A Write protection page 18

Definition at line 175 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR1_PAGE19

SRAM2A Write protection page 19

Definition at line 176 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR1_PAGE2

SRAM2A Write protection page 2

Definition at line 159 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR1_PAGE20

SRAM2A Write protection page 20

Definition at line 177 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR1_PAGE21

SRAM2A Write protection page 21

Definition at line 178 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR1_PAGE22

SRAM2A Write protection page 22

Definition at line 179 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR1_PAGE23

SRAM2A Write protection page 23

Definition at line 180 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR1_PAGE24

SRAM2A Write protection page 24

Definition at line 181 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR1_PAGE25

SRAM2A Write protection page 25

Definition at line 182 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR1_PAGE26

SRAM2A Write protection page 26

Definition at line 183 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR1_PAGE27

SRAM2A Write protection page 27

Definition at line 184 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR1_PAGE28

SRAM2A Write protection page 28

Definition at line 185 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR1_PAGE29

SRAM2A Write protection page 29

Definition at line 186 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR1_PAGE3

SRAM2A Write protection page 3

Definition at line 160 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR1_PAGE30

SRAM2A Write protection page 30

Definition at line 187 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR1_PAGE31

SRAM2A Write protection page 31

Definition at line 188 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE32 SYSCFG_SWPR2_PAGE32

SRAM2B Write protection page 32

Definition at line 190 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE33 SYSCFG_SWPR2_PAGE33

SRAM2B Write protection page 33

Definition at line 191 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE34 SYSCFG_SWPR2_PAGE34

SRAM2B Write protection page 34

Definition at line 192 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE35 SYSCFG_SWPR2_PAGE35

SRAM2B Write protection page 35

Definition at line 193 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE36 SYSCFG_SWPR2_PAGE36

SRAM2B Write protection page 36

Definition at line 194 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE37 SYSCFG_SWPR2_PAGE37

SRAM2B Write protection page 37

Definition at line 195 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE38 SYSCFG_SWPR2_PAGE38

SRAM2B Write protection page 38

Definition at line 196 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE39 SYSCFG_SWPR2_PAGE39

SRAM2B Write protection page 39

Definition at line 197 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR1_PAGE4

SRAM2A Write protection page 4

Definition at line 161 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE40 SYSCFG_SWPR2_PAGE40

SRAM2B Write protection page 40

Definition at line 198 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE41 SYSCFG_SWPR2_PAGE41

SRAM2B Write protection page 41

Definition at line 199 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE42 SYSCFG_SWPR2_PAGE42

SRAM2B Write protection page 42

Definition at line 200 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE43 SYSCFG_SWPR2_PAGE43

SRAM2B Write protection page 43

Definition at line 201 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE44 SYSCFG_SWPR2_PAGE44

SRAM2B Write protection page 44

Definition at line 202 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE45 SYSCFG_SWPR2_PAGE45

SRAM2B Write protection page 45

Definition at line 203 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE46 SYSCFG_SWPR2_PAGE46

SRAM2B Write protection page 46

Definition at line 204 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE47 SYSCFG_SWPR2_PAGE47

SRAM2B Write protection page 47

Definition at line 205 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE48 SYSCFG_SWPR2_PAGE48

SRAM2B Write protection page 48

Definition at line 206 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE49 SYSCFG_SWPR2_PAGE49

SRAM2B Write protection page 49

Definition at line 207 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR1_PAGE5

SRAM2A Write protection page 5

Definition at line 162 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE50 SYSCFG_SWPR2_PAGE50

SRAM2B Write protection page 50

Definition at line 208 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE51 SYSCFG_SWPR2_PAGE51

SRAM2B Write protection page 51

Definition at line 209 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE52 SYSCFG_SWPR2_PAGE52

SRAM2B Write protection page 52

Definition at line 210 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE53 SYSCFG_SWPR2_PAGE53

SRAM2B Write protection page 53

Definition at line 211 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE54 SYSCFG_SWPR2_PAGE54

SRAM2B Write protection page 54

Definition at line 212 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE55 SYSCFG_SWPR2_PAGE55

SRAM2B Write protection page 55

Definition at line 213 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE56 SYSCFG_SWPR2_PAGE56

SRAM2B Write protection page 56

Definition at line 214 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE57 SYSCFG_SWPR2_PAGE57

SRAM2B Write protection page 57

Definition at line 215 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE58 SYSCFG_SWPR2_PAGE58

SRAM2B Write protection page 58

Definition at line 216 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE59 SYSCFG_SWPR2_PAGE59

SRAM2B Write protection page 59

Definition at line 217 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR1_PAGE6

SRAM2A Write protection page 6

Definition at line 163 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE60 SYSCFG_SWPR2_PAGE60

SRAM2B Write protection page 60

Definition at line 218 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE61 SYSCFG_SWPR2_PAGE61

SRAM2B Write protection page 61

Definition at line 219 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE62 SYSCFG_SWPR2_PAGE62

SRAM2B Write protection page 62

Definition at line 220 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE63 SYSCFG_SWPR2_PAGE63

SRAM2B Write protection page 63

Definition at line 221 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR1_PAGE7

SRAM2A Write protection page 7

Definition at line 164 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR1_PAGE8

SRAM2A Write protection page 8

Definition at line 165 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR1_PAGE9

SRAM2A Write protection page 9

Definition at line 166 of file stm32wbxx_ll_system.h.

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SYSCFG CPU1 INTERRUPT MASK

Defines
SYSCFG CPU1 INTERRUPT MASK
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_GRP1_TIM1 SYSCFG_IMR1_TIM1IM
#define | LL_SYSCFG_GRP1_TIM16 SYSCFG_IMR1_TIM16IM
#define | LL_SYSCFG_GRP1_TIM17 SYSCFG_IMR1_TIM17IM
#define | LL_SYSCFG_GRP1_EXTI5 SYSCFG_IMR1_EXTI5IM
#define | LL_SYSCFG_GRP1_EXTI6 SYSCFG_IMR1_EXTI6IM
#define | LL_SYSCFG_GRP1_EXTI7 SYSCFG_IMR1_EXTI7IM
#define | LL_SYSCFG_GRP1_EXTI8 SYSCFG_IMR1_EXTI8IM
#define | LL_SYSCFG_GRP1_EXTI9 SYSCFG_IMR1_EXTI9IM
#define | LL_SYSCFG_GRP1_EXTI10 SYSCFG_IMR1_EXTI10IM
#define | LL_SYSCFG_GRP1_EXTI11 SYSCFG_IMR1_EXTI11IM
#define | LL_SYSCFG_GRP1_EXTI12 SYSCFG_IMR1_EXTI12IM
#define | LL_SYSCFG_GRP1_EXTI13 SYSCFG_IMR1_EXTI13IM
#define | LL_SYSCFG_GRP1_EXTI14 SYSCFG_IMR1_EXTI14IM
#define | LL_SYSCFG_GRP1_EXTI15 SYSCFG_IMR1_EXTI15IM
#define | LL_SYSCFG_GRP2_PVM1 SYSCFG_IMR2_PVM1IM
#define | LL_SYSCFG_GRP2_PVM3 SYSCFG_IMR2_PVM3IM
#define | LL_SYSCFG_GRP2_PVD SYSCFG_IMR2_PVDIM

Define Documentation

#define LL_SYSCFG_GRP1_EXTI10 SYSCFG_IMR1_EXTI10IM

Enabling of interrupt from External Interrupt Line 10 to CPU1

Definition at line 238 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_GRP1_EXTI11 SYSCFG_IMR1_EXTI11IM

Enabling of interrupt from External Interrupt Line 11 to CPU1

Definition at line 239 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_GRP1_EXTI12 SYSCFG_IMR1_EXTI12IM

Enabling of interrupt from External Interrupt Line 12 to CPU1

Definition at line 240 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_GRP1_EXTI13 SYSCFG_IMR1_EXTI13IM

Enabling of interrupt from External Interrupt Line 13 to CPU1

Definition at line 241 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_GRP1_EXTI14 SYSCFG_IMR1_EXTI14IM

Enabling of interrupt from External Interrupt Line 14 to CPU1

Definition at line 242 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_GRP1_EXTI15 SYSCFG_IMR1_EXTI15IM

Enabling of interrupt from External Interrupt Line 15 to CPU1

Definition at line 243 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_GRP1_EXTI5 SYSCFG_IMR1_EXTI5IM

Enabling of interrupt from External Interrupt Line 5 to CPU1

Definition at line 233 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_GRP1_EXTI6 SYSCFG_IMR1_EXTI6IM

Enabling of interrupt from External Interrupt Line 6 to CPU1

Definition at line 234 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_GRP1_EXTI7 SYSCFG_IMR1_EXTI7IM

Enabling of interrupt from External Interrupt Line 7 to CPU1

Definition at line 235 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_GRP1_EXTI8 SYSCFG_IMR1_EXTI8IM

Enabling of interrupt from External Interrupt Line 8 to CPU1

Definition at line 236 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_GRP1_EXTI9 SYSCFG_IMR1_EXTI9IM

Enabling of interrupt from External Interrupt Line 9 to CPU1

Definition at line 237 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_GRP1_TIM1 SYSCFG_IMR1_TIM1IM

Enabling of interrupt from Timer 1 to CPU1

Definition at line 229 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_GRP1_TIM16 SYSCFG_IMR1_TIM16IM

Enabling of interrupt from Timer 16 to CPU1

Definition at line 230 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_GRP1_TIM17 SYSCFG_IMR1_TIM17IM

Enabling of interrupt from Timer 17 to CPU1

Definition at line 231 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_GRP2_PVD SYSCFG_IMR2_PVDIM

Enabling of interrupt from Power Voltage Detector to CPU1

Definition at line 249 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_GRP2_PVM1 SYSCFG_IMR2_PVM1IM

Enabling of interrupt from Power Voltage Monitoring 1 to CPU1

Definition at line 246 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_GRP2_PVM3 SYSCFG_IMR2_PVM3IM

Enabling of interrupt from Power Voltage Monitoring 3 to CPU1

Definition at line 248 of file stm32wbxx_ll_system.h.

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SYSCFG CPU2 INTERRUPT MASK

Defines
SYSCFG CPU2 INTERRUPT MASK
SYSTEM Exported Constants

Defines

#define | LL_C2_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS SYSCFG_C2IMR1_RTCSTAMPTAMPLSECSSIM
#define | LL_C2_SYSCFG_GRP1_RTCWKUP SYSCFG_C2IMR1_RTCWKUPIM
#define | LL_C2_SYSCFG_GRP1_RTCALARM SYSCFG_C2IMR1_RTCALARMIM
#define | LL_C2_SYSCFG_GRP1_RCC SYSCFG_C2IMR1_RCCIM
#define | LL_C2_SYSCFG_GRP1_FLASH SYSCFG_C2IMR1_FLASHIM
#define | LL_C2_SYSCFG_GRP1_PKA SYSCFG_C2IMR1_PKAIM
#define | LL_C2_SYSCFG_GRP1_RNG SYSCFG_C2IMR1_RNGIM
#define | LL_C2_SYSCFG_GRP1_AES1 SYSCFG_C2IMR1_AES1IM
#define | LL_C2_SYSCFG_GRP1_COMP SYSCFG_C2IMR1_COMPIM
#define | LL_C2_SYSCFG_GRP1_ADC SYSCFG_C2IMR1_ADCIM
#define | LL_C2_SYSCFG_GRP1_EXTI0 SYSCFG_C2IMR1_EXTI0IM
#define | LL_C2_SYSCFG_GRP1_EXTI1 SYSCFG_C2IMR1_EXTI1IM
#define | LL_C2_SYSCFG_GRP1_EXTI2 SYSCFG_C2IMR1_EXTI2IM
#define | LL_C2_SYSCFG_GRP1_EXTI3 SYSCFG_C2IMR1_EXTI3IM
#define | LL_C2_SYSCFG_GRP1_EXTI4 SYSCFG_C2IMR1_EXTI4IM
#define | LL_C2_SYSCFG_GRP1_EXTI5 SYSCFG_C2IMR1_EXTI5IM
#define | LL_C2_SYSCFG_GRP1_EXTI6 SYSCFG_C2IMR1_EXTI6IM
#define | LL_C2_SYSCFG_GRP1_EXTI7 SYSCFG_C2IMR1_EXTI7IM
#define | LL_C2_SYSCFG_GRP1_EXTI8 SYSCFG_C2IMR1_EXTI8IM
#define | LL_C2_SYSCFG_GRP1_EXTI9 SYSCFG_C2IMR1_EXTI9IM
#define | LL_C2_SYSCFG_GRP1_EXTI10 SYSCFG_C2IMR1_EXTI10IM
#define | LL_C2_SYSCFG_GRP1_EXTI11 SYSCFG_C2IMR1_EXTI11IM
#define | LL_C2_SYSCFG_GRP1_EXTI12 SYSCFG_C2IMR1_EXTI12IM
#define | LL_C2_SYSCFG_GRP1_EXTI13 SYSCFG_C2IMR1_EXTI13IM
#define | LL_C2_SYSCFG_GRP1_EXTI14 SYSCFG_C2IMR1_EXTI14IM
#define | LL_C2_SYSCFG_GRP1_EXTI15 SYSCFG_C2IMR1_EXTI15IM
#define | LL_C2_SYSCFG_GRP2_DMA1CH1 SYSCFG_C2IMR2_DMA1CH1IM
#define | LL_C2_SYSCFG_GRP2_DMA1CH2 SYSCFG_C2IMR2_DMA1CH2IM
#define | LL_C2_SYSCFG_GRP2_DMA1CH3 SYSCFG_C2IMR2_DMA1CH3IM
#define | LL_C2_SYSCFG_GRP2_DMA1CH4 SYSCFG_C2IMR2_DMA1CH4IM
#define | LL_C2_SYSCFG_GRP2_DMA1CH5 SYSCFG_C2IMR2_DMA1CH5IM
#define | LL_C2_SYSCFG_GRP2_DMA1CH6 SYSCFG_C2IMR2_DMA1CH6IM
#define | LL_C2_SYSCFG_GRP2_DMA1CH7 SYSCFG_C2IMR2_DMA1CH7IM
#define | LL_C2_SYSCFG_GRP2_DMA2CH1 SYSCFG_C2IMR2_DMA2CH1IM
#define | LL_C2_SYSCFG_GRP2_DMA2CH2 SYSCFG_C2IMR2_DMA2CH2IM
#define | LL_C2_SYSCFG_GRP2_DMA2CH3 SYSCFG_C2IMR2_DMA2CH3IM
#define | LL_C2_SYSCFG_GRP2_DMA2CH4 SYSCFG_C2IMR2_DMA2CH4IM
#define | LL_C2_SYSCFG_GRP2_DMA2CH5 SYSCFG_C2IMR2_DMA2CH5IM
#define | LL_C2_SYSCFG_GRP2_DMA2CH6 SYSCFG_C2IMR2_DMA2CH6IM
#define | LL_C2_SYSCFG_GRP2_DMA2CH7 SYSCFG_C2IMR2_DMA2CH7IM
#define | LL_C2_SYSCFG_GRP2_DMAMUX1 SYSCFG_C2IMR2_DMAMUX1IM
#define | LL_C2_SYSCFG_GRP2_PVM1 SYSCFG_C2IMR2_PVM1IM
#define | LL_C2_SYSCFG_GRP2_PVM3 SYSCFG_C2IMR2_PVM3IM
#define | LL_C2_SYSCFG_GRP2_PVD SYSCFG_C2IMR2_PVDIM
#define | LL_C2_SYSCFG_GRP2_TSC SYSCFG_C2IMR2_TSCIM
#define | LL_C2_SYSCFG_GRP2_LCD SYSCFG_C2IMR2_LCDIM

Define Documentation

#define LL_C2_SYSCFG_GRP1_ADC SYSCFG_C2IMR1_ADCIM

Enabling of interrupt from Analog Digital Converter to CPU2

Definition at line 271 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP1_AES1 SYSCFG_C2IMR1_AES1IM

Enabling of interrupt from Advanced Encryption Standard 1 to CPU2

Definition at line 266 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP1_COMP SYSCFG_C2IMR1_COMPIM

Enabling of interrupt from Comparator to CPU2

Definition at line 269 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP1_EXTI0 SYSCFG_C2IMR1_EXTI0IM

Enabling of interrupt from External Interrupt Line 0 to CPU2

Definition at line 273 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP1_EXTI1 SYSCFG_C2IMR1_EXTI1IM

Enabling of interrupt from External Interrupt Line 1 to CPU2

Definition at line 274 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP1_EXTI10 SYSCFG_C2IMR1_EXTI10IM

Enabling of interrupt from External Interrupt Line 10 to CPU2

Definition at line 283 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP1_EXTI11 SYSCFG_C2IMR1_EXTI11IM

Enabling of interrupt from External Interrupt Line 11 to CPU2

Definition at line 284 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP1_EXTI12 SYSCFG_C2IMR1_EXTI12IM

Enabling of interrupt from External Interrupt Line 12 to CPU2

Definition at line 285 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP1_EXTI13 SYSCFG_C2IMR1_EXTI13IM

Enabling of interrupt from External Interrupt Line 13 to CPU2

Definition at line 286 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP1_EXTI14 SYSCFG_C2IMR1_EXTI14IM

Enabling of interrupt from External Interrupt Line 14 to CPU2

Definition at line 287 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP1_EXTI15 SYSCFG_C2IMR1_EXTI15IM

Enabling of interrupt from External Interrupt Line 15 to CPU2

Definition at line 288 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP1_EXTI2 SYSCFG_C2IMR1_EXTI2IM

Enabling of interrupt from External Interrupt Line 2 to CPU2

Definition at line 275 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP1_EXTI3 SYSCFG_C2IMR1_EXTI3IM

Enabling of interrupt from External Interrupt Line 3 to CPU2

Definition at line 276 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP1_EXTI4 SYSCFG_C2IMR1_EXTI4IM

Enabling of interrupt from External Interrupt Line 4 to CPU2

Definition at line 277 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP1_EXTI5 SYSCFG_C2IMR1_EXTI5IM

Enabling of interrupt from External Interrupt Line 5 to CPU2

Definition at line 278 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP1_EXTI6 SYSCFG_C2IMR1_EXTI6IM

Enabling of interrupt from External Interrupt Line 6 to CPU2

Definition at line 279 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP1_EXTI7 SYSCFG_C2IMR1_EXTI7IM

Enabling of interrupt from External Interrupt Line 7 to CPU2

Definition at line 280 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP1_EXTI8 SYSCFG_C2IMR1_EXTI8IM

Enabling of interrupt from External Interrupt Line 8 to CPU2

Definition at line 281 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP1_EXTI9 SYSCFG_C2IMR1_EXTI9IM

Enabling of interrupt from External Interrupt Line 9 to CPU2

Definition at line 282 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP1_FLASH SYSCFG_C2IMR1_FLASHIM

Enabling of interrupt from FLASH to CPU2

Definition at line 262 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP1_PKA SYSCFG_C2IMR1_PKAIM

Enabling of interrupt from Public Key Accelerator to CPU2

Definition at line 263 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP1_RCC SYSCFG_C2IMR1_RCCIM

Enabling of interrupt from RCC to CPU2

Definition at line 261 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP1_RNG SYSCFG_C2IMR1_RNGIM

Enabling of interrupt from Random Number Generator to CPU2

Definition at line 264 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP1_RTCALARM SYSCFG_C2IMR1_RTCALARMIM

Enabling of interrupt from RTC Alarms to CPU2

Definition at line 260 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS SYSCFG_C2IMR1_RTCSTAMPTAMPLSECSSIM

Enabling of interrupt from RTC TimeStamp, RTC Tampers and LSE Clock Security System to CPU2

Definition at line 257 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP1_RTCWKUP SYSCFG_C2IMR1_RTCWKUPIM

Enabling of interrupt from RTC Wakeup to CPU2

Definition at line 259 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP2_DMA1CH1 SYSCFG_C2IMR2_DMA1CH1IM

Enabling of interrupt from DMA1 Channel 1 to CPU2

Definition at line 290 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP2_DMA1CH2 SYSCFG_C2IMR2_DMA1CH2IM

Enabling of interrupt from DMA1 Channel 2 to CPU2

Definition at line 291 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP2_DMA1CH3 SYSCFG_C2IMR2_DMA1CH3IM

Enabling of interrupt from DMA1 Channel 3 to CPU2

Definition at line 292 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP2_DMA1CH4 SYSCFG_C2IMR2_DMA1CH4IM

Enabling of interrupt from DMA1 Channel 4 to CPU2

Definition at line 293 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP2_DMA1CH5 SYSCFG_C2IMR2_DMA1CH5IM

Enabling of interrupt from DMA1 Channel 5 to CPU2

Definition at line 294 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP2_DMA1CH6 SYSCFG_C2IMR2_DMA1CH6IM

Enabling of interrupt from DMA1 Channel 6 to CPU2

Definition at line 295 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP2_DMA1CH7 SYSCFG_C2IMR2_DMA1CH7IM

Enabling of interrupt from DMA1 Channel 7 to CPU2

Definition at line 296 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP2_DMA2CH1 SYSCFG_C2IMR2_DMA2CH1IM

Enabling of interrupt from DMA2 Channel 1 to CPU2

Definition at line 299 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP2_DMA2CH2 SYSCFG_C2IMR2_DMA2CH2IM

Enabling of interrupt from DMA2 Channel 2 to CPU2

Definition at line 300 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP2_DMA2CH3 SYSCFG_C2IMR2_DMA2CH3IM

Enabling of interrupt from DMA2 Channel 3 to CPU2

Definition at line 301 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP2_DMA2CH4 SYSCFG_C2IMR2_DMA2CH4IM

Enabling of interrupt from DMA2 Channel 4 to CPU2

Definition at line 302 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP2_DMA2CH5 SYSCFG_C2IMR2_DMA2CH5IM

Enabling of interrupt from DMA2 Channel 5 to CPU2

Definition at line 303 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP2_DMA2CH6 SYSCFG_C2IMR2_DMA2CH6IM

Enabling of interrupt from DMA2 Channel 6 to CPU2

Definition at line 304 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP2_DMA2CH7 SYSCFG_C2IMR2_DMA2CH7IM

Enabling of interrupt from DMA2 Channel 7 to CPU2

Definition at line 305 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP2_DMAMUX1 SYSCFG_C2IMR2_DMAMUX1IM

Enabling of interrupt from DMAMUX1 to CPU2

Definition at line 308 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP2_LCD SYSCFG_C2IMR2_LCDIM

Enabling of interrupt from Liquid Crystal Display to CPU2

Definition at line 316 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP2_PVD SYSCFG_C2IMR2_PVDIM

Enabling of interrupt from Power Voltage Detector to CPU2

Definition at line 313 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP2_PVM1 SYSCFG_C2IMR2_PVM1IM

Enabling of interrupt from Power Voltage Monitoring 1 to CPU2

Definition at line 310 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP2_PVM3 SYSCFG_C2IMR2_PVM3IM

Enabling of interrupt from Power Voltage Monitoring 3 to CPU2

Definition at line 312 of file stm32wbxx_ll_system.h.

#define LL_C2_SYSCFG_GRP2_TSC SYSCFG_C2IMR2_TSCIM

Enabling of interrupt from Touch Sensing Controller to CPU2

Definition at line 314 of file stm32wbxx_ll_system.h.

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SYSCFG SECURE IP ACCESS

Defines
SYSCFG SECURE IP ACCESS
SYSTEM Exported Constants

Defines

#define | LL_SYSCFG_SECURE_ACCESS_AES1 SYSCFG_SIPCR_SAES1
#define | LL_SYSCFG_SECURE_ACCESS_AES2 SYSCFG_SIPCR_SAES2
#define | LL_SYSCFG_SECURE_ACCESS_PKA SYSCFG_SIPCR_SPKA
#define | LL_SYSCFG_SECURE_ACCESS_RNG SYSCFG_SIPCR_SRNG

Define Documentation

#define LL_SYSCFG_SECURE_ACCESS_AES1 SYSCFG_SIPCR_SAES1

Enabling the security access of Advanced Encryption Standard 1 KEY[7:0]

Definition at line 326 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SECURE_ACCESS_AES2 SYSCFG_SIPCR_SAES2

Enabling the security access of Advanced Encryption Standard 2

Definition at line 328 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SECURE_ACCESS_PKA SYSCFG_SIPCR_SPKA

Enabling the security access of Public Key Accelerator

Definition at line 329 of file stm32wbxx_ll_system.h.

#define LL_SYSCFG_SECURE_ACCESS_RNG SYSCFG_SIPCR_SRNG

Enabling the security access of Random Number Generator

Definition at line 330 of file stm32wbxx_ll_system.h.

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DBGMCU CPU1 APB1 GRP1 STOP IP

Defines
DBGMCU CPU1 APB1 GRP1 STOP IP
SYSTEM Exported Constants

Defines

#define | LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP
#define | LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP
#define | LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP
#define | LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP
#define | LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP
#define | LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP
#define | LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP

Define Documentation

#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP

The I2C1 SMBus timeout is frozen

Definition at line 342 of file stm32wbxx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP

The I2C3 SMBus timeout is frozen

Definition at line 344 of file stm32wbxx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP

The independent watchdog counter clock is stopped when the core is halted

Definition at line 341 of file stm32wbxx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP

The counter clock of LPTIM1 is stopped when the core is halted

Definition at line 346 of file stm32wbxx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP

The clock of the RTC counter is stopped when the core is halted

Definition at line 339 of file stm32wbxx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP

The counter clock of TIM2 is stopped when the core is halted

Definition at line 338 of file stm32wbxx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP

The window watchdog counter clock is stopped when the core is halted

Definition at line 340 of file stm32wbxx_ll_system.h.

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STM32WB55xx HAL User Manual: DBGMCU CPU2 APB1 GRP1 STOP IP

Defines
DBGMCU CPU2 APB1 GRP1 STOP IP
SYSTEM Exported Constants

Defines

#define | LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_C2APB1FZR1_DBG_TIM2_STOP
#define | LL_C2_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_C2APB1FZR1_DBG_RTC_STOP
#define | LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_C2APB1FZR1_DBG_IWDG_STOP
#define | LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_C2APB1FZR1_DBG_I2C1_STOP
#define | LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_C2APB1FZR1_DBG_I2C3_STOP
#define | LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_C2APB1FZR1_DBG_LPTIM1_STOP

Define Documentation

#define LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_C2APB1FZR1_DBG_I2C1_STOP

The I2C1 SMBus timeout is frozen

Definition at line 357 of file stm32wbxx_ll_system.h.

#define LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_C2APB1FZR1_DBG_I2C3_STOP

The I2C3 SMBus timeout is frozen

Definition at line 359 of file stm32wbxx_ll_system.h.

#define LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_C2APB1FZR1_DBG_IWDG_STOP

The independent watchdog counter clock is stopped when the core is halted

Definition at line 356 of file stm32wbxx_ll_system.h.

#define LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_C2APB1FZR1_DBG_LPTIM1_STOP

The counter clock of LPTIM1 is stopped when the core is halted

Definition at line 361 of file stm32wbxx_ll_system.h.

#define LL_C2_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_C2APB1FZR1_DBG_RTC_STOP

The clock of the RTC counter is stopped when the core is halted

Definition at line 355 of file stm32wbxx_ll_system.h.

#define LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_C2APB1FZR1_DBG_TIM2_STOP

The counter clock of TIM2 is stopped when the core is halted

Definition at line 354 of file stm32wbxx_ll_system.h.

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STM32WB55xx HAL User Manual: DBGMCU CPU1 APB1 GRP2 STOP IP

Defines
DBGMCU CPU1 APB1 GRP2 STOP IP
SYSTEM Exported Constants

Defines

#define LL_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP

Define Documentation

#define LL_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP

The counter clock of LPTIM2 is stopped when the core is halted

Definition at line 369 of file stm32wbxx_ll_system.h.

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DBGMCU CPU2 APB1 GRP2 STOP IP

Defines
DBGMCU CPU2 APB1 GRP2 STOP IP
SYSTEM Exported Constants

Defines

#define LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_C2APB1FZR2_DBG_LPTIM2_STOP

Define Documentation

#define LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_C2APB1FZR2_DBG_LPTIM2_STOP

The counter clock of LPTIM2 is stopped when the core is halted

Definition at line 377 of file stm32wbxx_ll_system.h.

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DBGMCU CPU1 APB2 GRP1 STOP IP

Defines
DBGMCU CPU1 APB2 GRP1 STOP IP
SYSTEM Exported Constants

Defines

#define | LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP

Define Documentation

#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP

The counter clock of TIM16 is stopped when the core is halted

Definition at line 386 of file stm32wbxx_ll_system.h.

#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP

The counter clock of TIM17 is stopped when the core is halted

Definition at line 387 of file stm32wbxx_ll_system.h.

#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP

The counter clock of TIM1 is stopped when the core is halted

Definition at line 385 of file stm32wbxx_ll_system.h.

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DBGMCU CPU2 APB2 GRP1 STOP IP

Defines
DBGMCU CPU2 APB2 GRP1 STOP IP
SYSTEM Exported Constants

Defines

#define | LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_C2APB2FZR_DBG_TIM1_STOP
#define | LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_C2APB2FZR_DBG_TIM16_STOP
#define | LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_C2APB2FZR_DBG_TIM17_STOP

Define Documentation

#define LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_C2APB2FZR_DBG_TIM16_STOP

The counter clock of TIM16 is stopped when the core is halted

Definition at line 396 of file stm32wbxx_ll_system.h.

#define LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_C2APB2FZR_DBG_TIM17_STOP

The counter clock of TIM17 is stopped when the core is halted

Definition at line 397 of file stm32wbxx_ll_system.h.

#define LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_C2APB2FZR_DBG_TIM1_STOP

The counter clock of TIM1 is stopped when the core is halted

Definition at line 395 of file stm32wbxx_ll_system.h.

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: VREFBUF VOLTAGE

Defines
VREFBUF VOLTAGE
SYSTEM Exported Constants

Defines

#define | LL_VREFBUF_VOLTAGE_SCALE0 0x00000000U
#define | LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS

Define Documentation

#define LL_VREFBUF_VOLTAGE_SCALE0 0x00000000U

Voltage reference scale 0 (VREF_OUT1)

Definition at line 406 of file stm32wbxx_ll_system.h.

#define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS

Voltage reference scale 1 (VREF_OUT2)

Definition at line 407 of file stm32wbxx_ll_system.h.

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FLASH LATENCY

Defines
FLASH LATENCY
SYSTEM Exported Constants

Defines

#define | LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS
#define | LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS
#define | LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS
#define | LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS

Define Documentation

#define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS

FLASH Zero wait state

Definition at line 416 of file stm32wbxx_ll_system.h.

Referenced by UTILS_SetFlashLatency().

#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS

FLASH One wait state

Definition at line 417 of file stm32wbxx_ll_system.h.

Referenced by UTILS_SetFlashLatency().

#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS

FLASH Two wait states

Definition at line 418 of file stm32wbxx_ll_system.h.

Referenced by UTILS_SetFlashLatency().

#define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS

FLASH Three wait states

Definition at line 419 of file stm32wbxx_ll_system.h.

Referenced by UTILS_SetFlashLatency().

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SYSCFG

Defines | Functions
SYSCFG
SYSTEM Exported Functions

Defines

#define | LL_SYSCFG_EnableSRAM2PageWRP LL_SYSCFG_EnableSRAM2PageWRP_0_31
Enable SRAM2 page write protection for Pages in range 0 to 31.

Functions

__STATIC_INLINE void | LL_SYSCFG_SetRemapMemory (uint32_t Memory)
Set memory mapping at address 0x00000000.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetRemapMemory (void)
Get memory mapping at address 0x00000000.
__STATIC_INLINE void | LL_SYSCFG_EnableAnalogBooster (void)
Enable I/O analog switch voltage booster.
__STATIC_INLINE void | LL_SYSCFG_DisableAnalogBooster (void)
Disable I/O analog switch voltage booster.
__STATIC_INLINE void | LL_SYSCFG_EnableAnalogGpioSwitch (void)
Enable the Analog GPIO switch to control voltage selection when the supply voltage is supplied by VDDA.
__STATIC_INLINE void | LL_SYSCFG_DisableAnalogGpioSwitch (void)
Disable the Analog GPIO switch to control voltage selection when the supply voltage is supplied by VDDA.
__STATIC_INLINE void | LL_SYSCFG_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the I2C fast mode plus driving capability.
__STATIC_INLINE void | LL_SYSCFG_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the I2C fast mode plus driving capability.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_IOC (void)
Enable Floating Point Unit Invalid operation Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_DZC (void)
Enable Floating Point Unit Divide-by-zero Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_UFC (void)
Enable Floating Point Unit Underflow Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_OFC (void)
Enable Floating Point Unit Overflow Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_IDC (void)
Enable Floating Point Unit Input denormal Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_IXC (void)
Enable Floating Point Unit Inexact Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_IOC (void)
Disable Floating Point Unit Invalid operation Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_DZC (void)
Disable Floating Point Unit Divide-by-zero Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_UFC (void)
Disable Floating Point Unit Underflow Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_OFC (void)
Disable Floating Point Unit Overflow Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_IDC (void)
Disable Floating Point Unit Input denormal Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_IXC (void)
Disable Floating Point Unit Inexact Interrupt.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_IOC (void)
Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_DZC (void)
Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_UFC (void)
Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_OFC (void)
Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_IDC (void)
Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_IXC (void)
Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
__STATIC_INLINE void | LL_SYSCFG_SetEXTISource (uint32_t Port, uint32_t Line)
Configure source input for the EXTI external interrupt.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetEXTISource (uint32_t Line)
Get the configured defined for specific EXTI Line.
__STATIC_INLINE void | LL_SYSCFG_EnableSRAM2Erase (void)
Enable SRAM2 Erase (starts a hardware SRAM2 erase operation.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsSRAM2EraseOngoing (void)
Check if SRAM2 erase operation is on going.
__STATIC_INLINE void | LL_SYSCFG_DisableSRAMFetch (void)
Disable CPU2 SRAM fetch (execution) (This bit can be set by Firmware and will only be reset by a Hardware reset, including a reset after Standby.)
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledSRAMFetch (void)
Check if CPU2 SRAM fetch is enabled.
__STATIC_INLINE void | LL_SYSCFG_SetTIMBreakInputs (uint32_t Break)
Set connections to TIM1/16/17 Break inputs.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetTIMBreakInputs (void)
Get connections to TIM1/16/17 Break inputs.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_SP (void)
Check if SRAM2 parity error detected.
__STATIC_INLINE void | LL_SYSCFG_ClearFlag_SP (void)
Clear SRAM2 parity error flag.
__STATIC_INLINE void | LL_SYSCFG_EnableSRAM2PageWRP_0_31 (uint32_t SRAM2WRP)
__STATIC_INLINE void | LL_SYSCFG_EnableSRAM2PageWRP_32_63 (uint32_t SRAM2WRP)
Enable SRAM2 page write protection for Pages in range 32 to 63.
__STATIC_INLINE void | LL_SYSCFG_LockSRAM2WRP (void)
SRAM2 page write protection lock prior to erase.
__STATIC_INLINE void | LL_SYSCFG_UnlockSRAM2WRP (void)
SRAM2 page write protection unlock prior to erase.
__STATIC_INLINE void | LL_SYSCFG_GRP1_EnableIT (uint32_t Interrupt)
Enable CPU1 Interrupt Mask.
__STATIC_INLINE void | LL_SYSCFG_GRP2_EnableIT (uint32_t Interrupt)
Enable CPU1 Interrupt Mask.
__STATIC_INLINE void | LL_SYSCFG_GRP1_DisableIT (uint32_t Interrupt)
Disable CPU1 Interrupt Mask.
__STATIC_INLINE void | LL_SYSCFG_GRP2_DisableIT (uint32_t Interrupt)
Disable CPU1 Interrupt Mask.
__STATIC_INLINE uint32_t | LL_SYSCFG_GRP1_IsEnabledIT (uint32_t Interrupt)
Indicate if CPU1 Interrupt Mask is enabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_GRP2_IsEnabledIT (uint32_t Interrupt)
Indicate if CPU1 Interrupt Mask is enabled.
__STATIC_INLINE void | LL_C2_SYSCFG_GRP1_EnableIT (uint32_t Interrupt)
Enable CPU2 Interrupt Mask.
__STATIC_INLINE void | LL_C2_SYSCFG_GRP2_EnableIT (uint32_t Interrupt)
Enable CPU2 Interrupt Mask.
__STATIC_INLINE void | LL_C2_SYSCFG_GRP1_DisableIT (uint32_t Interrupt)
Disable CPU2 Interrupt Mask.
__STATIC_INLINE void | LL_C2_SYSCFG_GRP2_DisableIT (uint32_t Interrupt)
Disable CPU2 Interrupt Mask.
__STATIC_INLINE uint32_t | LL_C2_SYSCFG_GRP1_IsEnabledIT (uint32_t Interrupt)
Indicate if CPU2 Interrupt Mask is enabled.
__STATIC_INLINE uint32_t | LL_C2_SYSCFG_GRP2_IsEnabledIT (uint32_t Interrupt)
Indicate if CPU2 Interrupt Mask is enabled.
__STATIC_INLINE void | LL_SYSCFG_EnableSecurityAccess (uint32_t SecurityAccess)
Enable the access for security IP.
__STATIC_INLINE void | LL_SYSCFG_DisableSecurityAccess (uint32_t SecurityAccess)
Disable the access for security IP.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledSecurityAccess (uint32_t SecurityAccess)
Indicate if access for security IP is enabled.

Define Documentation

#define LL_SYSCFG_EnableSRAM2PageWRP LL_SYSCFG_EnableSRAM2PageWRP_0_31

Enable SRAM2 page write protection for Pages in range 0 to 31.

Note:
Write protection is cleared only by a system reset
Reference Manual to LL API cross reference:
SYSCFG_SWPR1 PxWP LL_SYSCFG_EnableSRAM2PageWRP_0_31
Parameters:
SRAM2WRP This parameter can be a combination of the following values:
  • LL_SYSCFG_SRAM2WRP_PAGE0
  • LL_SYSCFG_SRAM2WRP_PAGE1
  • LL_SYSCFG_SRAM2WRP_PAGE2
  • LL_SYSCFG_SRAM2WRP_PAGE3
  • LL_SYSCFG_SRAM2WRP_PAGE4
  • LL_SYSCFG_SRAM2WRP_PAGE5
  • LL_SYSCFG_SRAM2WRP_PAGE6
  • LL_SYSCFG_SRAM2WRP_PAGE7
  • LL_SYSCFG_SRAM2WRP_PAGE8
  • LL_SYSCFG_SRAM2WRP_PAGE9
  • LL_SYSCFG_SRAM2WRP_PAGE10
  • LL_SYSCFG_SRAM2WRP_PAGE11
  • LL_SYSCFG_SRAM2WRP_PAGE12
  • LL_SYSCFG_SRAM2WRP_PAGE13
  • LL_SYSCFG_SRAM2WRP_PAGE14
  • LL_SYSCFG_SRAM2WRP_PAGE15
  • LL_SYSCFG_SRAM2WRP_PAGE16
  • LL_SYSCFG_SRAM2WRP_PAGE17
  • LL_SYSCFG_SRAM2WRP_PAGE18
  • LL_SYSCFG_SRAM2WRP_PAGE19
  • LL_SYSCFG_SRAM2WRP_PAGE20
  • LL_SYSCFG_SRAM2WRP_PAGE21
  • LL_SYSCFG_SRAM2WRP_PAGE22
  • LL_SYSCFG_SRAM2WRP_PAGE23
  • LL_SYSCFG_SRAM2WRP_PAGE24
  • LL_SYSCFG_SRAM2WRP_PAGE25
  • LL_SYSCFG_SRAM2WRP_PAGE26
  • LL_SYSCFG_SRAM2WRP_PAGE27
  • LL_SYSCFG_SRAM2WRP_PAGE28
  • LL_SYSCFG_SRAM2WRP_PAGE29
  • LL_SYSCFG_SRAM2WRP_PAGE30
  • LL_SYSCFG_SRAM2WRP_PAGE31
Return values:
None

Definition at line 961 of file stm32wbxx_ll_system.h.

Function Documentation

__STATIC_INLINE void LL_C2_SYSCFG_GRP1_DisableIT ( uint32_t Interrupt )

Disable CPU2 Interrupt Mask.

Reference Manual to LL API cross reference:
SYSCFG_C2IMR1 RTCSTAMPTAMPLSECSSIM LL_C2_SYSCFG_GRP1_DisableIT
SYSCFG_C2IMR1 RTCWKUPIM LL_C2_SYSCFG_GRP1_DisableIT
SYSCFG_C2IMR1 RTCALARMIM LL_C2_SYSCFG_GRP1_DisableIT
SYSCFG_C2IMR1 RCCIM LL_C2_SYSCFG_GRP1_DisableIT
SYSCFG_C2IMR1 FLASHIM LL_C2_SYSCFG_GRP1_DisableIT
SYSCFG_C2IMR1 PKAIM LL_C2_SYSCFG_GRP1_DisableIT
SYSCFG_C2IMR1 RNGIM LL_C2_SYSCFG_GRP1_DisableIT
SYSCFG_C2IMR1 AES1IM LL_C2_SYSCFG_GRP1_DisableIT
SYSCFG_C2IMR1 COMPIM LL_C2_SYSCFG_GRP1_DisableIT
SYSCFG_C2IMR1 ADCIM LL_C2_SYSCFG_GRP1_DisableIT
SYSCFG_C2IMR1 EXTIxIM LL_C2_SYSCFG_GRP1_DisableIT
Parameters:
Interrupt This parameter can be a combination of the following values:
  • LL_C2_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS
  • LL_C2_SYSCFG_GRP1_RTCWKUP
  • LL_C2_SYSCFG_GRP1_RTCALARM
  • LL_C2_SYSCFG_GRP1_RCC
  • LL_C2_SYSCFG_GRP1_FLASH
  • LL_C2_SYSCFG_GRP1_PKA
  • LL_C2_SYSCFG_GRP1_RNG
  • LL_C2_SYSCFG_GRP1_AES1
  • LL_C2_SYSCFG_GRP1_COMP
  • LL_C2_SYSCFG_GRP1_ADC
  • LL_C2_SYSCFG_GRP1_EXTI0
  • LL_C2_SYSCFG_GRP1_EXTI1
  • LL_C2_SYSCFG_GRP1_EXTI2
  • LL_C2_SYSCFG_GRP1_EXTI3
  • LL_C2_SYSCFG_GRP1_EXTI4
  • LL_C2_SYSCFG_GRP1_EXTI5
  • LL_C2_SYSCFG_GRP1_EXTI6
  • LL_C2_SYSCFG_GRP1_EXTI7
  • LL_C2_SYSCFG_GRP1_EXTI8
  • LL_C2_SYSCFG_GRP1_EXTI9
  • LL_C2_SYSCFG_GRP1_EXTI10
  • LL_C2_SYSCFG_GRP1_EXTI11
  • LL_C2_SYSCFG_GRP1_EXTI12
  • LL_C2_SYSCFG_GRP1_EXTI13
  • LL_C2_SYSCFG_GRP1_EXTI14
  • LL_C2_SYSCFG_GRP1_EXTI15
Return values:
None

Definition at line 1292 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_C2_SYSCFG_GRP1_EnableIT ( uint32_t Interrupt )

Enable CPU2 Interrupt Mask.

Reference Manual to LL API cross reference:
SYSCFG_C2IMR1 RTCSTAMPTAMPLSECSSIM LL_C2_SYSCFG_GRP1_EnableIT
SYSCFG_C2IMR1 RTCWKUPIM LL_C2_SYSCFG_GRP1_EnableIT
SYSCFG_C2IMR1 RTCALARMIM LL_C2_SYSCFG_GRP1_EnableIT
SYSCFG_C2IMR1 RCCIM LL_C2_SYSCFG_GRP1_EnableIT
SYSCFG_C2IMR1 FLASHIM LL_C2_SYSCFG_GRP1_EnableIT
SYSCFG_C2IMR1 PKAIM LL_C2_SYSCFG_GRP1_EnableIT
SYSCFG_C2IMR1 RNGIM LL_C2_SYSCFG_GRP1_EnableIT
SYSCFG_C2IMR1 AES1IM LL_C2_SYSCFG_GRP1_EnableIT
SYSCFG_C2IMR1 COMPIM LL_C2_SYSCFG_GRP1_EnableIT
SYSCFG_C2IMR1 ADCIM LL_C2_SYSCFG_GRP1_EnableIT
SYSCFG_C2IMR1 EXTIxIM LL_C2_SYSCFG_GRP1_EnableIT
Parameters:
Interrupt This parameter can be a combination of the following values:
  • LL_C2_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS
  • LL_C2_SYSCFG_GRP1_RTCWKUP
  • LL_C2_SYSCFG_GRP1_RTCALARM
  • LL_C2_SYSCFG_GRP1_RCC
  • LL_C2_SYSCFG_GRP1_FLASH
  • LL_C2_SYSCFG_GRP1_PKA
  • LL_C2_SYSCFG_GRP1_RNG
  • LL_C2_SYSCFG_GRP1_AES1
  • LL_C2_SYSCFG_GRP1_COMP
  • LL_C2_SYSCFG_GRP1_ADC
  • LL_C2_SYSCFG_GRP1_EXTI0
  • LL_C2_SYSCFG_GRP1_EXTI1
  • LL_C2_SYSCFG_GRP1_EXTI2
  • LL_C2_SYSCFG_GRP1_EXTI3
  • LL_C2_SYSCFG_GRP1_EXTI4
  • LL_C2_SYSCFG_GRP1_EXTI5
  • LL_C2_SYSCFG_GRP1_EXTI6
  • LL_C2_SYSCFG_GRP1_EXTI7
  • LL_C2_SYSCFG_GRP1_EXTI8
  • LL_C2_SYSCFG_GRP1_EXTI9
  • LL_C2_SYSCFG_GRP1_EXTI10
  • LL_C2_SYSCFG_GRP1_EXTI11
  • LL_C2_SYSCFG_GRP1_EXTI12
  • LL_C2_SYSCFG_GRP1_EXTI13
  • LL_C2_SYSCFG_GRP1_EXTI14
  • LL_C2_SYSCFG_GRP1_EXTI15
Return values:
None

Definition at line 1208 of file stm32wbxx_ll_system.h.

__STATIC_INLINE uint32_t LL_C2_SYSCFG_GRP1_IsEnabledIT ( uint32_t Interrupt )

Indicate if CPU2 Interrupt Mask is enabled.

Reference Manual to LL API cross reference:
SYSCFG_C2IMR1 RTCSTAMPTAMPLSECSSIM LL_C2_SYSCFG_GRP1_EnableIT
SYSCFG_C2IMR1 RTCWKUPIM LL_C2_SYSCFG_GRP1_IsEnabledIT
SYSCFG_C2IMR1 RTCALARMIM LL_C2_SYSCFG_GRP1_IsEnabledIT
SYSCFG_C2IMR1 RCCIM LL_C2_SYSCFG_GRP1_IsEnabledIT
SYSCFG_C2IMR1 FLASHIM LL_C2_SYSCFG_GRP1_IsEnabledIT
SYSCFG_C2IMR1 PKAIM LL_C2_SYSCFG_GRP1_IsEnabledIT
SYSCFG_C2IMR1 RNGIM LL_C2_SYSCFG_GRP1_IsEnabledIT
SYSCFG_C2IMR1 AES1IM LL_C2_SYSCFG_GRP1_IsEnabledIT
SYSCFG_C2IMR1 COMPIM LL_C2_SYSCFG_GRP1_IsEnabledIT
SYSCFG_C2IMR1 ADCIM LL_C2_SYSCFG_GRP1_IsEnabledIT
SYSCFG_C2IMR1 EXTIxIM LL_C2_SYSCFG_GRP1_IsEnabledIT
Parameters:
Interrupt This parameter can be one of the following values:
  • LL_C2_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS
  • LL_C2_SYSCFG_GRP1_RTCWKUP
  • LL_C2_SYSCFG_GRP1_RTCALARM
  • LL_C2_SYSCFG_GRP1_RCC
  • LL_C2_SYSCFG_GRP1_FLASH
  • LL_C2_SYSCFG_GRP1_PKA
  • LL_C2_SYSCFG_GRP1_RNG
  • LL_C2_SYSCFG_GRP1_AES1
  • LL_C2_SYSCFG_GRP1_COMP
  • LL_C2_SYSCFG_GRP1_ADC
  • LL_C2_SYSCFG_GRP1_EXTI0
  • LL_C2_SYSCFG_GRP1_EXTI1
  • LL_C2_SYSCFG_GRP1_EXTI2
  • LL_C2_SYSCFG_GRP1_EXTI3
  • LL_C2_SYSCFG_GRP1_EXTI4
  • LL_C2_SYSCFG_GRP1_EXTI5
  • LL_C2_SYSCFG_GRP1_EXTI6
  • LL_C2_SYSCFG_GRP1_EXTI7
  • LL_C2_SYSCFG_GRP1_EXTI8
  • LL_C2_SYSCFG_GRP1_EXTI9
  • LL_C2_SYSCFG_GRP1_EXTI10
  • LL_C2_SYSCFG_GRP1_EXTI11
  • LL_C2_SYSCFG_GRP1_EXTI12
  • LL_C2_SYSCFG_GRP1_EXTI13
  • LL_C2_SYSCFG_GRP1_EXTI14
  • LL_C2_SYSCFG_GRP1_EXTI15
Return values:
State of bit (1 or 0).

Definition at line 1376 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_C2_SYSCFG_GRP2_DisableIT ( uint32_t Interrupt )

Disable CPU2 Interrupt Mask.

Reference Manual to LL API cross reference:
SYSCFG_C2IMR2 DMA1CHxIM LL_C2_SYSCFG_GRP2_DisableIT
SYSCFG_C2IMR2 DMA2CHxIM LL_C2_SYSCFG_GRP2_DisableIT
SYSCFG_C2IMR2 PVM1IM LL_C2_SYSCFG_GRP2_DisableIT
SYSCFG_C2IMR2 PVM3IM LL_C2_SYSCFG_GRP2_DisableIT
SYSCFG_C2IMR2 PVDIM LL_C2_SYSCFG_GRP2_DisableIT
SYSCFG_C2IMR2 TSCIM LL_C2_SYSCFG_GRP2_DisableIT
SYSCFG_C2IMR2 LCDIM LL_C2_SYSCFG_GRP2_DisableIT
Parameters:
Interrupt This parameter can be a combination of the following values:
  • LL_C2_SYSCFG_GRP2_DMA1CH1
  • LL_C2_SYSCFG_GRP2_DMA1CH2
  • LL_C2_SYSCFG_GRP2_DMA1CH3
  • LL_C2_SYSCFG_GRP2_DMA1CH4
  • LL_C2_SYSCFG_GRP2_DMA1CH5
  • LL_C2_SYSCFG_GRP2_DMA1CH6
  • LL_C2_SYSCFG_GRP2_DMA1CH7
  • LL_C2_SYSCFG_GRP2_DMA2CH1
  • LL_C2_SYSCFG_GRP2_DMA2CH2
  • LL_C2_SYSCFG_GRP2_DMA2CH3
  • LL_C2_SYSCFG_GRP2_DMA2CH4
  • LL_C2_SYSCFG_GRP2_DMA2CH5
  • LL_C2_SYSCFG_GRP2_DMA2CH6
  • LL_C2_SYSCFG_GRP2_DMA2CH7
  • LL_C2_SYSCFG_GRP2_DMAMUX1
  • LL_C2_SYSCFG_GRP2_PVM1
  • LL_C2_SYSCFG_GRP2_PVM3
  • LL_C2_SYSCFG_GRP2_PVD
  • LL_C2_SYSCFG_GRP2_TSC
  • LL_C2_SYSCFG_GRP2_LCD
Return values:
None

Definition at line 1329 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_C2_SYSCFG_GRP2_EnableIT ( uint32_t Interrupt )

Enable CPU2 Interrupt Mask.

Reference Manual to LL API cross reference:
SYSCFG_C2IMR2 DMA1CHxIM LL_C2_SYSCFG_GRP2_EnableIT
SYSCFG_C2IMR2 DMA2CHxIM LL_C2_SYSCFG_GRP2_EnableIT
SYSCFG_C2IMR2 PVM1IM LL_C2_SYSCFG_GRP2_EnableIT
SYSCFG_C2IMR2 PVM3IM LL_C2_SYSCFG_GRP2_EnableIT
SYSCFG_C2IMR2 PVDIM LL_C2_SYSCFG_GRP2_EnableIT
SYSCFG_C2IMR2 TSCIM LL_C2_SYSCFG_GRP2_EnableIT
SYSCFG_C2IMR2 LCDIM LL_C2_SYSCFG_GRP2_EnableIT
Parameters:
Interrupt This parameter can be a combination of the following values:
  • LL_C2_SYSCFG_GRP2_DMA1CH1
  • LL_C2_SYSCFG_GRP2_DMA1CH2
  • LL_C2_SYSCFG_GRP2_DMA1CH3
  • LL_C2_SYSCFG_GRP2_DMA1CH4
  • LL_C2_SYSCFG_GRP2_DMA1CH5
  • LL_C2_SYSCFG_GRP2_DMA1CH6
  • LL_C2_SYSCFG_GRP2_DMA1CH7
  • LL_C2_SYSCFG_GRP2_DMA2CH1
  • LL_C2_SYSCFG_GRP2_DMA2CH2
  • LL_C2_SYSCFG_GRP2_DMA2CH3
  • LL_C2_SYSCFG_GRP2_DMA2CH4
  • LL_C2_SYSCFG_GRP2_DMA2CH5
  • LL_C2_SYSCFG_GRP2_DMA2CH6
  • LL_C2_SYSCFG_GRP2_DMA2CH7
  • LL_C2_SYSCFG_GRP2_DMAMUX1
  • LL_C2_SYSCFG_GRP2_PVM1
  • LL_C2_SYSCFG_GRP2_PVM3
  • LL_C2_SYSCFG_GRP2_PVD
  • LL_C2_SYSCFG_GRP2_TSC
  • LL_C2_SYSCFG_GRP2_LCD
Return values:
None

Definition at line 1245 of file stm32wbxx_ll_system.h.

__STATIC_INLINE uint32_t LL_C2_SYSCFG_GRP2_IsEnabledIT ( uint32_t Interrupt )

Indicate if CPU2 Interrupt Mask is enabled.

Reference Manual to LL API cross reference:
SYSCFG_C2IMR2 DMA1CHxIM LL_C2_SYSCFG_GRP2_IsEnabledIT
SYSCFG_C2IMR2 DMA2CHxIM LL_C2_SYSCFG_GRP2_IsEnabledIT
SYSCFG_C2IMR2 PVM1IM LL_C2_SYSCFG_GRP2_IsEnabledIT
SYSCFG_C2IMR2 PVM3IM LL_C2_SYSCFG_GRP2_IsEnabledIT
SYSCFG_C2IMR2 PVDIM LL_C2_SYSCFG_GRP2_IsEnabledIT
SYSCFG_C2IMR2 TSCIM LL_C2_SYSCFG_GRP2_IsEnabledIT
SYSCFG_C2IMR2 LCDIM LL_C2_SYSCFG_GRP2_IsEnabledIT
Parameters:
Interrupt This parameter can be one of the following values:
  • LL_C2_SYSCFG_GRP2_DMA1CH1
  • LL_C2_SYSCFG_GRP2_DMA1CH2
  • LL_C2_SYSCFG_GRP2_DMA1CH3
  • LL_C2_SYSCFG_GRP2_DMA1CH4
  • LL_C2_SYSCFG_GRP2_DMA1CH5
  • LL_C2_SYSCFG_GRP2_DMA1CH6
  • LL_C2_SYSCFG_GRP2_DMA1CH7
  • LL_C2_SYSCFG_GRP2_DMA2CH1
  • LL_C2_SYSCFG_GRP2_DMA2CH2
  • LL_C2_SYSCFG_GRP2_DMA2CH3
  • LL_C2_SYSCFG_GRP2_DMA2CH4
  • LL_C2_SYSCFG_GRP2_DMA2CH5
  • LL_C2_SYSCFG_GRP2_DMA2CH6
  • LL_C2_SYSCFG_GRP2_DMA2CH7
  • LL_C2_SYSCFG_GRP2_DMAMUX1
  • LL_C2_SYSCFG_GRP2_PVM1
  • LL_C2_SYSCFG_GRP2_PVM3
  • LL_C2_SYSCFG_GRP2_PVD
  • LL_C2_SYSCFG_GRP2_TSC
  • LL_C2_SYSCFG_GRP2_LCD
Return values:
State of bit (1 or 0).

Definition at line 1413 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_ClearFlag_SP ( void )

Clear SRAM2 parity error flag.

Reference Manual to LL API cross reference:
SYSCFG_CFGR2 SPF LL_SYSCFG_ClearFlag_SP
Return values:
None

Definition at line 916 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster ( void )

Disable I/O analog switch voltage booster.

Note:
When voltage booster is enabled, I/O analog switches are supplied by a dedicated voltage booster, from VDD power domain. This is the recommended configuration with low VDDA voltage operation.
The I/O analog switch voltage booster is relevant for peripherals using I/O in analog input: ADC and COMP. However, COMP inputs have a high impedance and voltage booster do not impact performance significantly. Therefore, the voltage booster is mainly intended for usage with ADC.
Reference Manual to LL API cross reference:
SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_DisableAnalogBooster
Return values:
None

Definition at line 502 of file stm32wbxx_ll_system.h.

Referenced by HAL_SYSCFG_DisableIOBooster().

__STATIC_INLINE void LL_SYSCFG_DisableAnalogGpioSwitch ( void )

Disable the Analog GPIO switch to control voltage selection when the supply voltage is supplied by VDDA.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 ANASWVDD LL_SYSCFG_DisableAnalogGpioSwitch
Note:
Activating the gpio switch enable IOs analog switches supplied by VDDA
Return values:
None

Definition at line 526 of file stm32wbxx_ll_system.h.

Referenced by HAL_SYSCFG_DisableIOVdd().

__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus ( uint32_t ConfigFastModePlus )

Disable the I2C fast mode plus driving capability.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus
SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_DisableFastModePlus
Parameters:
ConfigFastModePlus This parameter can be a combination of the following values:
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB6
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB7
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB8
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB9
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
Return values:
None

Definition at line 562 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC ( void )

Disable Floating Point Unit Divide-by-zero Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC
Return values:
None

Definition at line 642 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC ( void )

Disable Floating Point Unit Input denormal Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC
Return values:
None

Definition at line 672 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC ( void )

Disable Floating Point Unit Invalid operation Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC
Return values:
None

Definition at line 632 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC ( void )

Disable Floating Point Unit Inexact Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC
Return values:
None

Definition at line 682 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC ( void )

Disable Floating Point Unit Overflow Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC
Return values:
None

Definition at line 662 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC ( void )

Disable Floating Point Unit Underflow Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC
Return values:
None

Definition at line 652 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_DisableSecurityAccess ( uint32_t SecurityAccess )

Disable the access for security IP.

Reference Manual to LL API cross reference:
SYSCFG_SIPCR SAES1 LL_SYSCFG_DisableSecurityAccess
SYSCFG_CFGR1 SAES2 LL_SYSCFG_DisableSecurityAccess
SYSCFG_CFGR1 SPKA LL_SYSCFG_DisableSecurityAccess
SYSCFG_CFGR1 SRNG LL_SYSCFG_DisableSecurityAccess
Parameters:
SecurityAccess This parameter can be a combination of the following values:
  • LL_SYSCFG_SECURE_ACCESS_AES1
  • LL_SYSCFG_SECURE_ACCESS_AES2
  • LL_SYSCFG_SECURE_ACCESS_PKA
  • LL_SYSCFG_SECURE_ACCESS_RNG
Return values:
None

Definition at line 1449 of file stm32wbxx_ll_system.h.

Referenced by HAL_SYSCFG_DisableSecurityAccess().

__STATIC_INLINE void LL_SYSCFG_DisableSRAMFetch ( void )

Disable CPU2 SRAM fetch (execution) (This bit can be set by Firmware and will only be reset by a Hardware reset, including a reset after Standby.)

Note:
Firmware writing 0 has no effect.
Reference Manual to LL API cross reference:
SYSCFG_SCSR C2RFD LL_SYSCFG_DisableSRAMFetch
Return values:
None

Definition at line 851 of file stm32wbxx_ll_system.h.

Referenced by HAL_SYSCFG_DisableSRAMFetch().

__STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster ( void )

Enable I/O analog switch voltage booster.

Note:
When voltage booster is enabled, I/O analog switches are supplied by a dedicated voltage booster, from VDD power domain. This is the recommended configuration with low VDDA voltage operation.
The I/O analog switch voltage booster is relevant for peripherals using I/O in analog input: ADC and COMP. However, COMP inputs have a high impedance and voltage booster do not impact performance significantly. Therefore, the voltage booster is mainly intended for usage with ADC.
Reference Manual to LL API cross reference:
SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_EnableAnalogBooster
Return values:
None

Definition at line 483 of file stm32wbxx_ll_system.h.

Referenced by HAL_SYSCFG_EnableIOBooster().

__STATIC_INLINE void LL_SYSCFG_EnableAnalogGpioSwitch ( void )

Enable the Analog GPIO switch to control voltage selection when the supply voltage is supplied by VDDA.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 ANASWVDD LL_SYSCFG_EnableAnalogGpioSwitch
Note:
Activating the gpio switch enable IOs analog switches supplied by VDDA
Return values:
None

Definition at line 514 of file stm32wbxx_ll_system.h.

Referenced by HAL_SYSCFG_EnableIOVdd().

__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus ( uint32_t ConfigFastModePlus )

Enable the I2C fast mode plus driving capability.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus
SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_EnableFastModePlus
Parameters:
ConfigFastModePlus This parameter can be a combination of the following values:
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB6
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB7
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB8
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB9
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
Return values:
None

Definition at line 544 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC ( void )

Enable Floating Point Unit Divide-by-zero Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC
Return values:
None

Definition at line 582 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC ( void )

Enable Floating Point Unit Input denormal Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC
Return values:
None

Definition at line 612 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC ( void )

Enable Floating Point Unit Invalid operation Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC
Return values:
None

Definition at line 572 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC ( void )

Enable Floating Point Unit Inexact Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC
Return values:
None

Definition at line 622 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC ( void )

Enable Floating Point Unit Overflow Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC
Return values:
None

Definition at line 602 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC ( void )

Enable Floating Point Unit Underflow Interrupt.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC
Return values:
None

Definition at line 592 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableSecurityAccess ( uint32_t SecurityAccess )

Enable the access for security IP.

Reference Manual to LL API cross reference:
SYSCFG_SIPCR SAES1 LL_SYSCFG_EnableSecurityAccess
SYSCFG_CFGR1 SAES2 LL_SYSCFG_EnableSecurityAccess
SYSCFG_CFGR1 SPKA LL_SYSCFG_EnableSecurityAccess
SYSCFG_CFGR1 SRNG LL_SYSCFG_EnableSecurityAccess
Parameters:
SecurityAccess This parameter can be a combination of the following values:
  • LL_SYSCFG_SECURE_ACCESS_AES1
  • LL_SYSCFG_SECURE_ACCESS_AES2
  • LL_SYSCFG_SECURE_ACCESS_PKA
  • LL_SYSCFG_SECURE_ACCESS_RNG
Return values:
None

Definition at line 1431 of file stm32wbxx_ll_system.h.

Referenced by HAL_SYSCFG_EnableSecurityAccess().

__STATIC_INLINE void LL_SYSCFG_EnableSRAM2Erase ( void )

Enable SRAM2 Erase (starts a hardware SRAM2 erase operation.

This bit is automatically cleared at the end of the SRAM2 erase operation.)

Note:
This bit is write-protected: setting this bit is possible only after the correct key sequence is written in the SYSCFG_SKR register.
Reference Manual to LL API cross reference:
SYSCFG_SCSR SRAM2ER LL_SYSCFG_EnableSRAM2Erase
Return values:
None

Definition at line 829 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP_0_31 ( uint32_t SRAM2WRP )

Definition at line 962 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP_32_63 ( uint32_t SRAM2WRP )

Enable SRAM2 page write protection for Pages in range 32 to 63.

Note:
Write protection is cleared only by a system reset
Reference Manual to LL API cross reference:
SYSCFG_SWPR2 PxWP LL_SYSCFG_EnableSRAM2PageWRP_32_63
Parameters:
SRAM2WRP This parameter can be a combination of the following values:
  • LL_SYSCFG_SRAM2WRP_PAGE32
  • LL_SYSCFG_SRAM2WRP_PAGE33
  • LL_SYSCFG_SRAM2WRP_PAGE34
  • LL_SYSCFG_SRAM2WRP_PAGE35
  • LL_SYSCFG_SRAM2WRP_PAGE36
  • LL_SYSCFG_SRAM2WRP_PAGE37
  • LL_SYSCFG_SRAM2WRP_PAGE38
  • LL_SYSCFG_SRAM2WRP_PAGE39
  • LL_SYSCFG_SRAM2WRP_PAGE40
  • LL_SYSCFG_SRAM2WRP_PAGE41
  • LL_SYSCFG_SRAM2WRP_PAGE42
  • LL_SYSCFG_SRAM2WRP_PAGE43
  • LL_SYSCFG_SRAM2WRP_PAGE44
  • LL_SYSCFG_SRAM2WRP_PAGE45
  • LL_SYSCFG_SRAM2WRP_PAGE46
  • LL_SYSCFG_SRAM2WRP_PAGE47
  • LL_SYSCFG_SRAM2WRP_PAGE48
  • LL_SYSCFG_SRAM2WRP_PAGE49
  • LL_SYSCFG_SRAM2WRP_PAGE50
  • LL_SYSCFG_SRAM2WRP_PAGE51
  • LL_SYSCFG_SRAM2WRP_PAGE52
  • LL_SYSCFG_SRAM2WRP_PAGE53
  • LL_SYSCFG_SRAM2WRP_PAGE54
  • LL_SYSCFG_SRAM2WRP_PAGE55
  • LL_SYSCFG_SRAM2WRP_PAGE56
  • LL_SYSCFG_SRAM2WRP_PAGE57
  • LL_SYSCFG_SRAM2WRP_PAGE58
  • LL_SYSCFG_SRAM2WRP_PAGE59
  • LL_SYSCFG_SRAM2WRP_PAGE60
  • LL_SYSCFG_SRAM2WRP_PAGE61
  • LL_SYSCFG_SRAM2WRP_PAGE62
  • LL_SYSCFG_SRAM2WRP_PAGE63
Return values:
None

Definition at line 1006 of file stm32wbxx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource ( uint32_t Line )

Get the configured defined for specific EXTI Line.

Reference Manual to LL API cross reference:
SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource
SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource
Parameters:
Line This parameter can be one of the following values:
  • LL_SYSCFG_EXTI_LINE0
  • LL_SYSCFG_EXTI_LINE1
  • LL_SYSCFG_EXTI_LINE2
  • LL_SYSCFG_EXTI_LINE3
  • LL_SYSCFG_EXTI_LINE4
  • LL_SYSCFG_EXTI_LINE5
  • LL_SYSCFG_EXTI_LINE6
  • LL_SYSCFG_EXTI_LINE7
  • LL_SYSCFG_EXTI_LINE8
  • LL_SYSCFG_EXTI_LINE9
  • LL_SYSCFG_EXTI_LINE10
  • LL_SYSCFG_EXTI_LINE11
  • LL_SYSCFG_EXTI_LINE12
  • LL_SYSCFG_EXTI_LINE13
  • LL_SYSCFG_EXTI_LINE14
  • LL_SYSCFG_EXTI_LINE15
Return values:
Returned value can be one of the following values:
  • LL_SYSCFG_EXTI_PORTA
  • LL_SYSCFG_EXTI_PORTB
  • LL_SYSCFG_EXTI_PORTC
  • LL_SYSCFG_EXTI_PORTD
  • LL_SYSCFG_EXTI_PORTE
  • LL_SYSCFG_EXTI_PORTH

Definition at line 816 of file stm32wbxx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory ( void )

Get memory mapping at address 0x00000000.

Reference Manual to LL API cross reference:
SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory
Return values:
Returned value can be one of the following values:
  • LL_SYSCFG_REMAP_FLASH
  • LL_SYSCFG_REMAP_SYSTEMFLASH
  • LL_SYSCFG_REMAP_SRAM
  • LL_SYSCFG_REMAP_QUADSPI

Definition at line 464 of file stm32wbxx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs ( void )

Get connections to TIM1/16/17 Break inputs.

Reference Manual to LL API cross reference:
SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs
SYSCFG_CFGR2 SPL LL_SYSCFG_GetTIMBreakInputs
SYSCFG_CFGR2 PVDL LL_SYSCFG_GetTIMBreakInputs
SYSCFG_CFGR2 ECCL LL_SYSCFG_GetTIMBreakInputs
Return values:
Returned value can be can be a combination of the following values:
  • LL_SYSCFG_TIMBREAK_ECC
  • LL_SYSCFG_TIMBREAK_PVD
  • LL_SYSCFG_TIMBREAK_SRAM2_PARITY
  • LL_SYSCFG_TIMBREAK_LOCKUP

Definition at line 896 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_GRP1_DisableIT ( uint32_t Interrupt )

Disable CPU1 Interrupt Mask.

Reference Manual to LL API cross reference:
SYSCFG_IMR1 TIM1IM LL_SYSCFG_GRP1_DisableIT
SYSCFG_IMR1 TIM16IM LL_SYSCFG_GRP1_DisableIT
SYSCFG_IMR1 TIM17IM LL_SYSCFG_GRP1_DisableIT
SYSCFG_IMR1 EXTIxIM LL_SYSCFG_GRP1_DisableIT
Parameters:
Interrupt This parameter can be a combination of the following values:
  • LL_SYSCFG_GRP1_TIM1
  • LL_SYSCFG_GRP1_TIM16
  • LL_SYSCFG_GRP1_TIM17
  • LL_SYSCFG_GRP1_EXTI5
  • LL_SYSCFG_GRP1_EXTI6
  • LL_SYSCFG_GRP1_EXTI7
  • LL_SYSCFG_GRP1_EXTI8
  • LL_SYSCFG_GRP1_EXTI9
  • LL_SYSCFG_GRP1_EXTI10
  • LL_SYSCFG_GRP1_EXTI11
  • LL_SYSCFG_GRP1_EXTI12
  • LL_SYSCFG_GRP1_EXTI13
  • LL_SYSCFG_GRP1_EXTI14
  • LL_SYSCFG_GRP1_EXTI15
Return values:
None

Definition at line 1101 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_GRP1_EnableIT ( uint32_t Interrupt )

Enable CPU1 Interrupt Mask.

Reference Manual to LL API cross reference:
SYSCFG_IMR1 TIM1IM LL_SYSCFG_GRP1_EnableIT
SYSCFG_IMR1 TIM16IM LL_SYSCFG_GRP1_EnableIT
SYSCFG_IMR1 TIM17IM LL_SYSCFG_GRP1_EnableIT
SYSCFG_IMR1 EXTIxIM LL_SYSCFG_GRP1_EnableIT
Parameters:
Interrupt This parameter can be a combination of the following values:
  • LL_SYSCFG_GRP1_TIM1
  • LL_SYSCFG_GRP1_TIM16
  • LL_SYSCFG_GRP1_TIM17
  • LL_SYSCFG_GRP1_EXTI5
  • LL_SYSCFG_GRP1_EXTI6
  • LL_SYSCFG_GRP1_EXTI7
  • LL_SYSCFG_GRP1_EXTI8
  • LL_SYSCFG_GRP1_EXTI9
  • LL_SYSCFG_GRP1_EXTI10
  • LL_SYSCFG_GRP1_EXTI11
  • LL_SYSCFG_GRP1_EXTI12
  • LL_SYSCFG_GRP1_EXTI13
  • LL_SYSCFG_GRP1_EXTI14
  • LL_SYSCFG_GRP1_EXTI15
Return values:
None

Definition at line 1057 of file stm32wbxx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_GRP1_IsEnabledIT ( uint32_t Interrupt )

Indicate if CPU1 Interrupt Mask is enabled.

Reference Manual to LL API cross reference:
SYSCFG_IMR1 TIM1IM LL_SYSCFG_GRP1_IsEnabledIT
SYSCFG_IMR1 TIM16IM LL_SYSCFG_GRP1_IsEnabledIT
SYSCFG_IMR1 TIM17IM LL_SYSCFG_GRP1_IsEnabledIT
SYSCFG_IMR1 EXTIxIM LL_SYSCFG_GRP1_IsEnabledIT
Parameters:
Interrupt This parameter can be one of the following values:
  • LL_SYSCFG_GRP1_TIM1
  • LL_SYSCFG_GRP1_TIM16
  • LL_SYSCFG_GRP1_TIM17
  • LL_SYSCFG_GRP1_EXTI5
  • LL_SYSCFG_GRP1_EXTI6
  • LL_SYSCFG_GRP1_EXTI7
  • LL_SYSCFG_GRP1_EXTI8
  • LL_SYSCFG_GRP1_EXTI9
  • LL_SYSCFG_GRP1_EXTI10
  • LL_SYSCFG_GRP1_EXTI11
  • LL_SYSCFG_GRP1_EXTI12
  • LL_SYSCFG_GRP1_EXTI13
  • LL_SYSCFG_GRP1_EXTI14
  • LL_SYSCFG_GRP1_EXTI15
Return values:
State of bit (1 or 0).

Definition at line 1145 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_GRP2_DisableIT ( uint32_t Interrupt )

Disable CPU1 Interrupt Mask.

Reference Manual to LL API cross reference:
SYSCFG_IMR2 PVM1IM LL_SYSCFG_GRP2_DisableIT
SYSCFG_IMR2 PVM3IM LL_SYSCFG_GRP2_DisableIT
SYSCFG_IMR2 PVDIM LL_SYSCFG_GRP2_DisableIT
Parameters:
Interrupt This parameter can be a combination of the following values:
  • LL_SYSCFG_GRP2_PVM1
  • LL_SYSCFG_GRP2_PVM3
  • LL_SYSCFG_GRP2_PVD
Return values:
None

Definition at line 1117 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_GRP2_EnableIT ( uint32_t Interrupt )

Enable CPU1 Interrupt Mask.

Reference Manual to LL API cross reference:
SYSCFG_IMR1 PVM1IM LL_SYSCFG_GRP2_EnableIT
SYSCFG_IMR1 PVM3IM LL_SYSCFG_GRP2_EnableIT
SYSCFG_IMR1 PVDIM LL_SYSCFG_GRP2_EnableIT
Parameters:
Interrupt This parameter can be a combination of the following values:
  • LL_SYSCFG_GRP2_PVM1
  • LL_SYSCFG_GRP2_PVM3
  • LL_SYSCFG_GRP2_PVD
Return values:
None

Definition at line 1073 of file stm32wbxx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_GRP2_IsEnabledIT ( uint32_t Interrupt )

Indicate if CPU1 Interrupt Mask is enabled.

Reference Manual to LL API cross reference:
SYSCFG_IMR2 PVM1IM LL_SYSCFG_GRP2_IsEnabledIT
SYSCFG_IMR2 PVM3IM LL_SYSCFG_GRP2_IsEnabledIT
SYSCFG_IMR2 PVDIM LL_SYSCFG_GRP2_IsEnabledIT
Parameters:
Interrupt This parameter can be one of the following values:
  • LL_SYSCFG_GRP2_PVM1
  • LL_SYSCFG_GRP2_PVM3
  • LL_SYSCFG_GRP2_PVD
Return values:
State of bit (1 or 0).

Definition at line 1161 of file stm32wbxx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP ( void )

Check if SRAM2 parity error detected.

Reference Manual to LL API cross reference:
SYSCFG_CFGR2 SPF LL_SYSCFG_IsActiveFlag_SP
Return values:
State of bit (1 or 0).

Definition at line 906 of file stm32wbxx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC ( void )

Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC
Return values:
State of bit (1 or 0).

Definition at line 702 of file stm32wbxx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC ( void )

Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC
Return values:
State of bit (1 or 0).

Definition at line 732 of file stm32wbxx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC ( void )

Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC
Return values:
State of bit (1 or 0).

Definition at line 692 of file stm32wbxx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC ( void )

Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC
Return values:
State of bit (1 or 0).

Definition at line 742 of file stm32wbxx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC ( void )

Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC
Return values:
State of bit (1 or 0).

Definition at line 722 of file stm32wbxx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC ( void )

Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC
Return values:
State of bit (1 or 0).

Definition at line 712 of file stm32wbxx_ll_system.h.

__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledSecurityAccess ( uint32_t SecurityAccess )

Indicate if access for security IP is enabled.

Reference Manual to LL API cross reference:
SYSCFG_SIPCR SAES1 LL_SYSCFG_IsEnabledSecurityAccess
SYSCFG_CFGR1 SAES2 LL_SYSCFG_IsEnabledSecurityAccess
SYSCFG_CFGR1 SPKA LL_SYSCFG_IsEnabledSecurityAccess
SYSCFG_CFGR1 SRNG LL_SYSCFG_IsEnabledSecurityAccess
Parameters:
SecurityAccess This parameter can be one of the following values:
  • LL_SYSCFG_SECURE_ACCESS_AES1
  • LL_SYSCFG_SECURE_ACCESS_AES2
  • LL_SYSCFG_SECURE_ACCESS_PKA
  • LL_SYSCFG_SECURE_ACCESS_RNG
Return values:
State of bit (1 or 0).

Definition at line 1467 of file stm32wbxx_ll_system.h.

Referenced by HAL_SYSCFG_IsEnabledSecurityAccess().

__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledSRAMFetch ( void )

Check if CPU2 SRAM fetch is enabled.

Reference Manual to LL API cross reference:
SYSCFG_SCSR C2RFD LL_SYSCFG_IsEnabledSRAMFetch
Return values:
State of bit (1 or 0).

Definition at line 861 of file stm32wbxx_ll_system.h.

Referenced by HAL_SYSCFG_IsEnabledSRAMFetch().

__STATIC_INLINE uint32_t LL_SYSCFG_IsSRAM2EraseOngoing ( void )

Check if SRAM2 erase operation is on going.

Reference Manual to LL API cross reference:
SYSCFG_SCSR SRAM2BSY LL_SYSCFG_IsSRAM2EraseOngoing
Return values:
State of bit (1 or 0).

Definition at line 839 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_LockSRAM2WRP ( void )

SRAM2 page write protection lock prior to erase.

Reference Manual to LL API cross reference:
SYSCFG_SKR KEY LL_SYSCFG_LockSRAM2WRP
Return values:
None

Definition at line 1016 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_SetEXTISource | ( | uint32_t | Port,
 |  | uint32_t | Line
 | ) |  |

Configure source input for the EXTI external interrupt.

Reference Manual to LL API cross reference:
SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource
SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource
Parameters:
Port This parameter can be one of the following values:
  • LL_SYSCFG_EXTI_PORTA
  • LL_SYSCFG_EXTI_PORTB
  • LL_SYSCFG_EXTI_PORTC
  • LL_SYSCFG_EXTI_PORTD
  • LL_SYSCFG_EXTI_PORTE
  • LL_SYSCFG_EXTI_PORTH
Line This parameter can be one of the following values:
  • LL_SYSCFG_EXTI_LINE0
  • LL_SYSCFG_EXTI_LINE1
  • LL_SYSCFG_EXTI_LINE2
  • LL_SYSCFG_EXTI_LINE3
  • LL_SYSCFG_EXTI_LINE4
  • LL_SYSCFG_EXTI_LINE5
  • LL_SYSCFG_EXTI_LINE6
  • LL_SYSCFG_EXTI_LINE7
  • LL_SYSCFG_EXTI_LINE8
  • LL_SYSCFG_EXTI_LINE9
  • LL_SYSCFG_EXTI_LINE10
  • LL_SYSCFG_EXTI_LINE11
  • LL_SYSCFG_EXTI_LINE12
  • LL_SYSCFG_EXTI_LINE13
  • LL_SYSCFG_EXTI_LINE14
  • LL_SYSCFG_EXTI_LINE15
Return values:
None

Definition at line 780 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_SetRemapMemory ( uint32_t Memory )

Set memory mapping at address 0x00000000.

Reference Manual to LL API cross reference:
SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory
Parameters:
Memory This parameter can be one of the following values:
  • LL_SYSCFG_REMAP_FLASH
  • LL_SYSCFG_REMAP_SYSTEMFLASH
  • LL_SYSCFG_REMAP_SRAM
  • LL_SYSCFG_REMAP_QUADSPI
Return values:
None

Definition at line 450 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs ( uint32_t Break )

Set connections to TIM1/16/17 Break inputs.

Reference Manual to LL API cross reference:
SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs
SYSCFG_CFGR2 SPL LL_SYSCFG_SetTIMBreakInputs
SYSCFG_CFGR2 PVDL LL_SYSCFG_SetTIMBreakInputs
SYSCFG_CFGR2 ECCL LL_SYSCFG_SetTIMBreakInputs
Parameters:
Break This parameter can be a combination of the following values:
  • LL_SYSCFG_TIMBREAK_ECC
  • LL_SYSCFG_TIMBREAK_PVD
  • LL_SYSCFG_TIMBREAK_SRAM2_PARITY
  • LL_SYSCFG_TIMBREAK_LOCKUP
Return values:
None

Definition at line 879 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_SYSCFG_UnlockSRAM2WRP ( void )

SRAM2 page write protection unlock prior to erase.

Reference Manual to LL API cross reference:
SYSCFG_SKR KEY LL_SYSCFG_UnlockSRAM2WRP
Return values:
None

Definition at line 1027 of file stm32wbxx_ll_system.h.

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DBGMCU

Functions
DBGMCU
SYSTEM Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_DBGMCU_GetDeviceID (void)
Return the device identifier.
__STATIC_INLINE uint32_t | LL_DBGMCU_GetRevisionID (void)
Return the device revision identifier.
__STATIC_INLINE void | LL_DBGMCU_EnableDBGSleepMode (void)
Enable the Debug Module during SLEEP mode.
__STATIC_INLINE void | LL_DBGMCU_DisableDBGSleepMode (void)
Disable the Debug Module during SLEEP mode.
__STATIC_INLINE void | LL_DBGMCU_EnableDBGStopMode (void)
Enable the Debug Module during STOP mode.
__STATIC_INLINE void | LL_DBGMCU_DisableDBGStopMode (void)
Disable the Debug Module during STOP mode.
__STATIC_INLINE void | LL_DBGMCU_EnableDBGStandbyMode (void)
Enable the Debug Module during STANDBY mode.
__STATIC_INLINE void | LL_DBGMCU_DisableDBGStandbyMode (void)
Disable the Debug Module during STANDBY mode.
__STATIC_INLINE void | LL_DBGMCU_EnableTraceClock (void)
Enable the clock for Trace port.
__STATIC_INLINE void | LL_DBGMCU_DisableTraceClock (void)
Disable the clock for Trace port.
__STATIC_INLINE uint32_t | LL_DBGMCU_IsEnabledTraceClock (void)
Indicate if the clock for Trace port is enabled.
__STATIC_INLINE void | LL_DBGMCU_EnableTriggerOutput (void)
Enable the external trigger ouput.
__STATIC_INLINE void | LL_DBGMCU_DisableTriggerOutput (void)
Disable the external trigger ouput.
__STATIC_INLINE uint32_t | LL_DBGMCU_IsEnabledTriggerOutput (void)
Indicate if the external trigger is output or input direction.
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP1_FreezePeriph (uint32_t Periphs)
Freeze CPU1 APB1 peripherals (group1 peripherals)
__STATIC_INLINE void | LL_C2_DBGMCU_APB1_GRP1_FreezePeriph (uint32_t Periphs)
Freeze CPU2 APB1 peripherals (group1 peripherals)
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP2_FreezePeriph (uint32_t Periphs)
Freeze CPU1 APB1 peripherals (group2 peripherals)
__STATIC_INLINE void | LL_C2_DBGMCU_APB1_GRP2_FreezePeriph (uint32_t Periphs)
Freeze CPU2 APB1 peripherals (group2 peripherals)
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP1_UnFreezePeriph (uint32_t Periphs)
Unfreeze CPU1 APB1 peripherals (group1 peripherals)
__STATIC_INLINE void | LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph (uint32_t Periphs)
Unfreeze CPU2 APB1 peripherals (group1 peripherals)
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP2_UnFreezePeriph (uint32_t Periphs)
Unfreeze CPU1 APB1 peripherals (group2 peripherals)
__STATIC_INLINE void | LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph (uint32_t Periphs)
Unfreeze CPU2 APB1 peripherals (group2 peripherals)
__STATIC_INLINE void | LL_DBGMCU_APB2_GRP1_FreezePeriph (uint32_t Periphs)
Freeze CPU1 APB2 peripherals.
__STATIC_INLINE void | LL_C2_DBGMCU_APB2_GRP1_FreezePeriph (uint32_t Periphs)
Freeze CPU2 APB2 peripherals.
__STATIC_INLINE void | LL_DBGMCU_APB2_GRP1_UnFreezePeriph (uint32_t Periphs)
Unfreeze CPU1 APB2 peripherals.
__STATIC_INLINE void | LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph (uint32_t Periphs)
Unfreeze CPU2 APB2 peripherals.

Detailed Description

Note:
DBGMCU is only accessible by Cortex M4 To access on DBGMCU, Cortex M0+ need to request to the Cortex M4 the action.

Function Documentation

__STATIC_INLINE void LL_C2_DBGMCU_APB1_GRP1_FreezePeriph ( uint32_t Periphs )

Freeze CPU2 APB1 peripherals (group1 peripherals)

Reference Manual to LL API cross reference:
DBGMCU_C2APB1FZR1 DBG_xxxx_STOP LL_C2_DBGMCU_APB1_GRP1_FreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP
  • LL_C2_DBGMCU_APB1_GRP1_RTC_STOP
  • LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP
  • LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP
  • LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP
  • LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP
Return values:
None

Definition at line 1661 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph ( uint32_t Periphs )

Unfreeze CPU2 APB1 peripherals (group1 peripherals)

Reference Manual to LL API cross reference:
DBGMCU_C2APB1FZR1 DBG_xxxx_STOP LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP
  • LL_C2_DBGMCU_APB1_GRP1_RTC_STOP
  • LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP
  • LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP
  • LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP
  • LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP
Return values:
None

Definition at line 1720 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_C2_DBGMCU_APB1_GRP2_FreezePeriph ( uint32_t Periphs )

Freeze CPU2 APB1 peripherals (group2 peripherals)

Reference Manual to LL API cross reference:
DBGMCU_C2APB1FZR2 DBG_xxxx_STOP LL_C2_DBGMCU_APB1_GRP2_FreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP
Return values:
None

Definition at line 1685 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph ( uint32_t Periphs )

Unfreeze CPU2 APB1 peripherals (group2 peripherals)

Reference Manual to LL API cross reference:
DBGMCU_C2APB1FZR2 DBG_xxxx_STOP LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP
Return values:
None

Definition at line 1744 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_C2_DBGMCU_APB2_GRP1_FreezePeriph ( uint32_t Periphs )

Freeze CPU2 APB2 peripherals.

Reference Manual to LL API cross reference:
DBGMCU_C2APB2FZR DBG_TIMx_STOP LL_C2_DBGMCU_APB2_GRP1_FreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP
  • LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP
  • LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP
Return values:
None

Definition at line 1772 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph ( uint32_t Periphs )

Unfreeze CPU2 APB2 peripherals.

Reference Manual to LL API cross reference:
DBGMCU_C2APB2FZR DBG_TIMx_STOP LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP
  • LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP
  • LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP
Return values:
None

Definition at line 1800 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph ( uint32_t Periphs )

Freeze CPU1 APB1 peripherals (group1 peripherals)

Reference Manual to LL API cross reference:
DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB1_GRP1_TIM2_STOP
  • LL_DBGMCU_APB1_GRP1_RTC_STOP
  • LL_DBGMCU_APB1_GRP1_WWDG_STOP
  • LL_DBGMCU_APB1_GRP1_IWDG_STOP
  • LL_DBGMCU_APB1_GRP1_I2C1_STOP
  • LL_DBGMCU_APB1_GRP1_I2C3_STOP
  • LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
Return values:
None

Definition at line 1644 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph ( uint32_t Periphs )

Unfreeze CPU1 APB1 peripherals (group1 peripherals)

Reference Manual to LL API cross reference:
DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB1_GRP1_TIM2_STOP
  • LL_DBGMCU_APB1_GRP1_RTC_STOP
  • LL_DBGMCU_APB1_GRP1_WWDG_STOP
  • LL_DBGMCU_APB1_GRP1_IWDG_STOP
  • LL_DBGMCU_APB1_GRP1_I2C1_STOP
  • LL_DBGMCU_APB1_GRP1_I2C3_STOP
  • LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
Return values:
None

Definition at line 1703 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph ( uint32_t Periphs )

Freeze CPU1 APB1 peripherals (group2 peripherals)

Reference Manual to LL API cross reference:
DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
Return values:
None

Definition at line 1673 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph ( uint32_t Periphs )

Unfreeze CPU1 APB1 peripherals (group2 peripherals)

Reference Manual to LL API cross reference:
DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
Return values:
None

Definition at line 1732 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph ( uint32_t Periphs )

Freeze CPU1 APB2 peripherals.

Reference Manual to LL API cross reference:
DBGMCU_APB2FZR DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB2_GRP1_TIM1_STOP
  • LL_DBGMCU_APB2_GRP1_TIM16_STOP
  • LL_DBGMCU_APB2_GRP1_TIM17_STOP
Return values:
None

Definition at line 1758 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph ( uint32_t Periphs )

Unfreeze CPU1 APB2 peripherals.

Reference Manual to LL API cross reference:
DBGMCU_APB2FZR DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB2_GRP1_TIM1_STOP
  • LL_DBGMCU_APB2_GRP1_TIM16_STOP
  • LL_DBGMCU_APB2_GRP1_TIM17_STOP
Return values:
None

Definition at line 1786 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode ( void )

Disable the Debug Module during SLEEP mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
Return values:
None

Definition at line 1520 of file stm32wbxx_ll_system.h.

Referenced by HAL_DBGMCU_DisableDBGSleepMode().

__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode ( void )

Disable the Debug Module during STANDBY mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
Return values:
None

Definition at line 1560 of file stm32wbxx_ll_system.h.

Referenced by HAL_DBGMCU_DisableDBGStandbyMode().

__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode ( void )

Disable the Debug Module during STOP mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
Return values:
None

Definition at line 1540 of file stm32wbxx_ll_system.h.

Referenced by HAL_DBGMCU_DisableDBGStopMode().

__STATIC_INLINE void LL_DBGMCU_DisableTraceClock ( void )

Disable the clock for Trace port.

Reference Manual to LL API cross reference:
DBGMCU_CR TRACE_CLKEN LL_DBGMCU_DisableTraceClock
Return values:
None

Definition at line 1579 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_DisableTriggerOutput ( void )

Disable the external trigger ouput.

Note:
When disable external trigger is input (state of bit 0), TRGIO pin is connected to TRGIN.
Reference Manual to LL API cross reference:
DBGMCU_CR TRGOEN LL_DBGMCU_DisableTriggerOutput
Return values:
None

Definition at line 1612 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode ( void )

Enable the Debug Module during SLEEP mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
Return values:
None

Definition at line 1510 of file stm32wbxx_ll_system.h.

Referenced by HAL_DBGMCU_EnableDBGSleepMode().

__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode ( void )

Enable the Debug Module during STANDBY mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
Return values:
None

Definition at line 1550 of file stm32wbxx_ll_system.h.

Referenced by HAL_DBGMCU_EnableDBGStandbyMode().

__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode ( void )

Enable the Debug Module during STOP mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
Return values:
None

Definition at line 1530 of file stm32wbxx_ll_system.h.

Referenced by HAL_DBGMCU_EnableDBGStopMode().

__STATIC_INLINE void LL_DBGMCU_EnableTraceClock ( void )

Enable the clock for Trace port.

Reference Manual to LL API cross reference:
DBGMCU_CR TRACE_CLKEN LL_DBGMCU_EnableTraceClock

Definition at line 1569 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_EnableTriggerOutput ( void )

Enable the external trigger ouput.

Note:
When enable the external trigger is output (state of bit 1), TRGIO pin is connected to TRGOUT.
Reference Manual to LL API cross reference:
DBGMCU_CR TRGOEN LL_DBGMCU_EnableTriggerOutput

Definition at line 1600 of file stm32wbxx_ll_system.h.

__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID ( void )

Return the device identifier.

Note:
For STM32WBxxxx devices, the device ID is 0x495
Reference Manual to LL API cross reference:
DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
Return values:
Values between Min_Data=0x00 and Max_Data=0xFFF (ex: device ID is 0x495)

Definition at line 1489 of file stm32wbxx_ll_system.h.

Referenced by HAL_GetDEVID().

__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID ( void )

Return the device revision identifier.

Note:
This field indicates the revision of the device.
Reference Manual to LL API cross reference:
DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
Return values:
Values between Min_Data=0x00 and Max_Data=0xFFFF

Definition at line 1500 of file stm32wbxx_ll_system.h.

Referenced by HAL_GetREVID().

__STATIC_INLINE uint32_t LL_DBGMCU_IsEnabledTraceClock ( void )

Indicate if the clock for Trace port is enabled.

Reference Manual to LL API cross reference:
DBGMCU_CR TRACE_CLKEN LL_DBGMCU_IsEnabledTraceClock
Return values:
State of bit (1 or 0).

Definition at line 1589 of file stm32wbxx_ll_system.h.

__STATIC_INLINE uint32_t LL_DBGMCU_IsEnabledTriggerOutput ( void )

Indicate if the external trigger is output or input direction.

Note:
When the external trigger is output (state of bit 1), TRGIO pin is connected to TRGOUT. When the external trigger is input (state of bit 0), TRGIO pin is connected to TRGIN.
Reference Manual to LL API cross reference:
DBGMCU_CR TRGOEN LL_DBGMCU_EnableTriggerOutput
Return values:
State of bit (1 or 0).

Definition at line 1626 of file stm32wbxx_ll_system.h.

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: VREFBUF

Functions
VREFBUF
SYSTEM Exported Functions

Functions

__STATIC_INLINE void | LL_VREFBUF_Enable (void)
Enable Internal voltage reference.
__STATIC_INLINE void | LL_VREFBUF_Disable (void)
Disable Internal voltage reference.
__STATIC_INLINE void | LL_VREFBUF_EnableHIZ (void)
Enable high impedance (VREF+pin is high impedance)
__STATIC_INLINE void | LL_VREFBUF_DisableHIZ (void)
Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
__STATIC_INLINE void | LL_VREFBUF_SetVoltageScaling (uint32_t Scale)
Set the Voltage reference scale.
__STATIC_INLINE uint32_t | LL_VREFBUF_GetVoltageScaling (void)
Get the Voltage reference scale.
__STATIC_INLINE uint32_t | LL_VREFBUF_IsVREFReady (void)
Check if Voltage reference buffer is ready.
__STATIC_INLINE uint32_t | LL_VREFBUF_GetTrimming (void)
Get the trimming code for VREFBUF calibration.
__STATIC_INLINE void | LL_VREFBUF_SetTrimming (uint32_t Value)
Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)

Function Documentation

__STATIC_INLINE void LL_VREFBUF_Disable ( void )

Disable Internal voltage reference.

Reference Manual to LL API cross reference:
VREFBUF_CSR ENVR LL_VREFBUF_Disable
Return values:
None

Definition at line 1829 of file stm32wbxx_ll_system.h.

Referenced by HAL_SYSCFG_DisableVREFBUF().

__STATIC_INLINE void LL_VREFBUF_DisableHIZ ( void )

Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)

Reference Manual to LL API cross reference:
VREFBUF_CSR HIZ LL_VREFBUF_DisableHIZ
Return values:
None

Definition at line 1849 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_VREFBUF_Enable ( void )

Enable Internal voltage reference.

Reference Manual to LL API cross reference:
VREFBUF_CSR ENVR LL_VREFBUF_Enable
Return values:
None

Definition at line 1819 of file stm32wbxx_ll_system.h.

Referenced by HAL_SYSCFG_EnableVREFBUF().

__STATIC_INLINE void LL_VREFBUF_EnableHIZ ( void )

Enable high impedance (VREF+pin is high impedance)

Reference Manual to LL API cross reference:
VREFBUF_CSR HIZ LL_VREFBUF_EnableHIZ
Return values:
None

Definition at line 1839 of file stm32wbxx_ll_system.h.

__STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming ( void )

Get the trimming code for VREFBUF calibration.

Reference Manual to LL API cross reference:
VREFBUF_CCR TRIM LL_VREFBUF_GetTrimming
Return values:
Between 0 and 0x3F

Definition at line 1894 of file stm32wbxx_ll_system.h.

__STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling ( void )

Get the Voltage reference scale.

Reference Manual to LL API cross reference:
VREFBUF_CSR VRS LL_VREFBUF_GetVoltageScaling
Return values:
Returned value can be one of the following values:
  • LL_VREFBUF_VOLTAGE_SCALE0
  • LL_VREFBUF_VOLTAGE_SCALE1

Definition at line 1874 of file stm32wbxx_ll_system.h.

__STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady ( void )

Check if Voltage reference buffer is ready.

Reference Manual to LL API cross reference:
VREFBUF_CSR VRR LL_VREFBUF_IsVREFReady
Return values:
State of bit (1 or 0).

Definition at line 1884 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_VREFBUF_SetTrimming ( uint32_t Value )

Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)

Reference Manual to LL API cross reference:
VREFBUF_CCR TRIM LL_VREFBUF_SetTrimming
Parameters:
Value Between 0 and 0x3F
Return values:
None

Definition at line 1905 of file stm32wbxx_ll_system.h.

Referenced by HAL_SYSCFG_VREFBUF_TrimmingConfig().

__STATIC_INLINE void LL_VREFBUF_SetVoltageScaling ( uint32_t Scale )

Set the Voltage reference scale.

Reference Manual to LL API cross reference:
VREFBUF_CSR VRS LL_VREFBUF_SetVoltageScaling
Parameters:
Scale This parameter can be one of the following values:
  • LL_VREFBUF_VOLTAGE_SCALE0
  • LL_VREFBUF_VOLTAGE_SCALE1
Return values:
None

Definition at line 1862 of file stm32wbxx_ll_system.h.

Referenced by HAL_SYSCFG_VREFBUF_VoltageScalingConfig().

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FLASH

Functions
FLASH
SYSTEM Exported Functions

Functions

__STATIC_INLINE void | LL_FLASH_SetLatency (uint32_t Latency)
Set FLASH Latency.
__STATIC_INLINE uint32_t | LL_FLASH_GetLatency (void)
Get FLASH Latency.
__STATIC_INLINE void | LL_FLASH_EnablePrefetch (void)
Enable Prefetch.
__STATIC_INLINE void | LL_FLASH_DisablePrefetch (void)
Disable Prefetch.
__STATIC_INLINE uint32_t | LL_FLASH_IsPrefetchEnabled (void)
Check if Prefetch buffer is enabled.
__STATIC_INLINE void | LL_FLASH_EnableInstCache (void)
Enable Instruction cache.
__STATIC_INLINE void | LL_FLASH_DisableInstCache (void)
Disable Instruction cache.
__STATIC_INLINE void | LL_FLASH_EnableDataCache (void)
Enable Data cache.
__STATIC_INLINE void | LL_FLASH_DisableDataCache (void)
Disable Data cache.
__STATIC_INLINE void | LL_FLASH_EnableInstCacheReset (void)
Enable Instruction cache reset.
__STATIC_INLINE void | LL_FLASH_DisableInstCacheReset (void)
Disable Instruction cache reset.
__STATIC_INLINE void | LL_FLASH_EnableDataCacheReset (void)
Enable Data cache reset.
__STATIC_INLINE void | LL_FLASH_DisableDataCacheReset (void)
Disable Data cache reset.
__STATIC_INLINE void | LL_FLASH_SuspendOperation (void)
Suspend new program or erase operation request.
__STATIC_INLINE void | LL_FLASH_AllowOperation (void)
Allow new program or erase operation request.
__STATIC_INLINE uint32_t | LL_FLASH_IsOperationSuspended (void)
Check if new program or erase operation request from CPU2 is suspended.
__STATIC_INLINE uint32_t | LL_FLASH_IsActiveFlag_OperationSuspended (void)
Check if new program or erase operation request from CPU1 or CPU2 is suspended.
__STATIC_INLINE void | LL_FLASH_SetEmptyFlag (void)
Set EMPTY flag information as Flash User area empty.
__STATIC_INLINE void | LL_FLASH_ClearEmptyFlag (void)
Clear EMPTY flag information as Flash User area programmed.
__STATIC_INLINE uint32_t | LL_FLASH_IsEmptyFlag (void)
Check if the EMPTY flag is set or reset.
__STATIC_INLINE uint32_t | LL_FLASH_GetIPCCBufferAddr (void)
Get IPCC buffer base address.
__STATIC_INLINE uint32_t | LL_FLASH_GetC2BootResetVect (void)
Get CPU2 boot reset vector.
__STATIC_INLINE uint32_t | LL_FLASH_GetUDN (void)
Return the Unique Device Number.
__STATIC_INLINE uint32_t | LL_FLASH_GetDeviceID (void)
Return the Device ID.
__STATIC_INLINE uint32_t | LL_FLASH_GetSTCompanyID (void)
Return the ST Company ID.

Function Documentation

__STATIC_INLINE void LL_FLASH_AllowOperation ( void )

Allow new program or erase operation request.

Note:
Any new Flash program and erase operation on both CPU side will be allowed until one of this bit or the same bit in Flash CPU2 access control register (FLASH_C2ACR) is set. The PESD bit in both the Flash status register (FLASH_SR) and Flash CPU2 status register (FLASH_C2SR) register will be clear when both PES bit in FLASH_ACR or FLASH_C2ACR is cleared.
Reference Manual to LL API cross reference:
FLASH_ACR PES LL_FLASH_AllowOperation
Reference Manual to LL API cross reference:
FLASH_C2ACR PES LL_FLASH_AllowOperation
Return values:
None

Definition at line 2093 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_FLASH_ClearEmptyFlag ( void )

Clear EMPTY flag information as Flash User area programmed.

Reference Manual to LL API cross reference:
FLASH_ACR EMPTY LL_FLASH_ClearEmptyFlag
Return values:
None

Definition at line 2135 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_FLASH_DisableDataCache ( void )

Disable Data cache.

Reference Manual to LL API cross reference:
FLASH_ACR DCEN LL_FLASH_DisableDataCache
Return values:
None

Definition at line 2017 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_FLASH_DisableDataCacheReset ( void )

Disable Data cache reset.

Reference Manual to LL API cross reference:
FLASH_ACR DCRST LL_FLASH_DisableDataCacheReset
Return values:
None

Definition at line 2061 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_FLASH_DisableInstCache ( void )

Disable Instruction cache.

Reference Manual to LL API cross reference:
FLASH_ACR ICEN LL_FLASH_DisableInstCache
Reference Manual to LL API cross reference:
FLASH_C2ACR ICEN LL_FLASH_DisableInstCache
Return values:
None

Definition at line 1997 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_FLASH_DisableInstCacheReset ( void )

Disable Instruction cache reset.

Reference Manual to LL API cross reference:
FLASH_ACR ICRST LL_FLASH_DisableInstCacheReset
Reference Manual to LL API cross reference:
FLASH_C2ACR ICRST LL_FLASH_DisableInstCacheReset
Return values:
None

Definition at line 2040 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_FLASH_DisablePrefetch ( void )

Disable Prefetch.

Reference Manual to LL API cross reference:
FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch
Reference Manual to LL API cross reference:
FLASH_C2ACR PRFTEN LL_FLASH_DisablePrefetch
Return values:
None

Definition at line 1964 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_FLASH_EnableDataCache ( void )

Enable Data cache.

Reference Manual to LL API cross reference:
FLASH_ACR DCEN LL_FLASH_EnableDataCache
Return values:
None

Definition at line 2007 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_FLASH_EnableDataCacheReset ( void )

Enable Data cache reset.

Note:
bit can be written only when the data cache is disabled
Reference Manual to LL API cross reference:
FLASH_ACR DCRST LL_FLASH_EnableDataCacheReset
Return values:
None

Definition at line 2051 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_FLASH_EnableInstCache ( void )

Enable Instruction cache.

Reference Manual to LL API cross reference:
FLASH_ACR ICEN LL_FLASH_EnableInstCache
Reference Manual to LL API cross reference:
FLASH_C2ACR ICEN LL_FLASH_EnableInstCache
Return values:
None

Definition at line 1986 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_FLASH_EnableInstCacheReset ( void )

Enable Instruction cache reset.

Note:
bit can be written only when the instruction cache is disabled
Reference Manual to LL API cross reference:
FLASH_ACR ICRST LL_FLASH_EnableInstCacheReset
Reference Manual to LL API cross reference:
FLASH_C2ACR ICRST LL_FLASH_EnableInstCacheReset
Return values:
None

Definition at line 2029 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_FLASH_EnablePrefetch ( void )

Enable Prefetch.

Reference Manual to LL API cross reference:
FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch
Return values:
None

Definition at line 1953 of file stm32wbxx_ll_system.h.

__STATIC_INLINE uint32_t LL_FLASH_GetC2BootResetVect ( void )

Get CPU2 boot reset vector.

Reference Manual to LL API cross reference:
FLASH_SRRVR SBRV LL_FLASH_GetC2BootResetVect
Return values:
CPU2 boot reset vector

Definition at line 2165 of file stm32wbxx_ll_system.h.

__STATIC_INLINE uint32_t LL_FLASH_GetDeviceID ( void )

Return the Device ID.

Note:
The 64-bit UID64 may be used by Firmware to derive BLE 48-bit Device Address EUI-48 or 802.15.4 64-bit Device Address EUI-64. For STM32WBxxxx devices, the device ID is 0x26
Return values:
Values between Min_Data=0x00 and Max_Data=0xFF (ex: Device ID is 0x26 fo STM32WB55x)

Definition at line 2188 of file stm32wbxx_ll_system.h.

__STATIC_INLINE uint32_t LL_FLASH_GetIPCCBufferAddr ( void )

Get IPCC buffer base address.

Reference Manual to LL API cross reference:
FLASH_IPCCBR IPCCDBA LL_FLASH_GetIPCCBufferAddr
Return values:
IPCC data buffer base address offset

Definition at line 2155 of file stm32wbxx_ll_system.h.

__STATIC_INLINE uint32_t LL_FLASH_GetLatency ( void )

Get FLASH Latency.

Reference Manual to LL API cross reference:
FLASH_ACR LATENCY LL_FLASH_GetLatency
Return values:
Returned value can be one of the following values:
  • LL_FLASH_LATENCY_0
  • LL_FLASH_LATENCY_1
  • LL_FLASH_LATENCY_2
  • LL_FLASH_LATENCY_3

Definition at line 1943 of file stm32wbxx_ll_system.h.

Referenced by UTILS_SetFlashLatency().

__STATIC_INLINE uint32_t LL_FLASH_GetSTCompanyID ( void )

Return the ST Company ID.

Note:
The 64-bit UID64 may be used by Firmware to derive BLE 48-bit Device Address EUI-48 or 802.15.4 64-bit Device Address EUI-64. For STM32WBxxxx devices, the ST Compagny ID is 0x0080E1
Return values:
Values between Min_Data=0x00 and Max_Data=0xFFFFFF (ex: ST Compagny ID is 0x0080E1)

Definition at line 2200 of file stm32wbxx_ll_system.h.

__STATIC_INLINE uint32_t LL_FLASH_GetUDN ( void )

Return the Unique Device Number.

Note:
The 64-bit UID64 may be used by Firmware to derive BLE 48-bit Device Address EUI-48 or 802.15.4 64-bit Device Address EUI-64.
Return values:
Values between Min_Data=0x00 and Max_Data=0xFFFF

Definition at line 2176 of file stm32wbxx_ll_system.h.

__STATIC_INLINE uint32_t LL_FLASH_IsActiveFlag_OperationSuspended ( void )

Check if new program or erase operation request from CPU1 or CPU2 is suspended.

Reference Manual to LL API cross reference:
FLASH_SR PESD LL_FLASH_IsActiveFlag_OperationSuspended
Reference Manual to LL API cross reference:
FLASH_C2SR PESD LL_FLASH_IsActiveFlag_OperationSuspended
Return values:
State of bit (1 or 0).

Definition at line 2115 of file stm32wbxx_ll_system.h.

__STATIC_INLINE uint32_t LL_FLASH_IsEmptyFlag ( void )

Check if the EMPTY flag is set or reset.

Reference Manual to LL API cross reference:
FLASH_ACR EMPTY LL_FLASH_IsEmptyFlag
Return values:
State of bit (1 or 0).

Definition at line 2145 of file stm32wbxx_ll_system.h.

__STATIC_INLINE uint32_t LL_FLASH_IsOperationSuspended ( void )

Check if new program or erase operation request from CPU2 is suspended.

Reference Manual to LL API cross reference:
FLASH_ACR PES LL_FLASH_IsOperationSuspended
Reference Manual to LL API cross reference:
FLASH_C2ACR PES LL_FLASH_IsOperationSuspended
Return values:
State of bit (1 or 0).

Definition at line 2104 of file stm32wbxx_ll_system.h.

__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled ( void )

Check if Prefetch buffer is enabled.

Reference Manual to LL API cross reference:
FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled
Reference Manual to LL API cross reference:
FLASH_C2ACR C2PRFTEN LL_FLASH_IsPrefetchEnabled
Return values:
State of bit (1 or 0).

Definition at line 1975 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_FLASH_SetEmptyFlag ( void )

Set EMPTY flag information as Flash User area empty.

Reference Manual to LL API cross reference:
FLASH_ACR EMPTY LL_FLASH_SetEmptyFlag
Return values:
None

Definition at line 2125 of file stm32wbxx_ll_system.h.

__STATIC_INLINE void LL_FLASH_SetLatency ( uint32_t Latency )

Set FLASH Latency.

Reference Manual to LL API cross reference:
FLASH_ACR LATENCY LL_FLASH_SetLatency
Parameters:
Latency This parameter can be one of the following values:
  • LL_FLASH_LATENCY_0
  • LL_FLASH_LATENCY_1
  • LL_FLASH_LATENCY_2
  • LL_FLASH_LATENCY_3
Return values:
None

Definition at line 1929 of file stm32wbxx_ll_system.h.

Referenced by UTILS_SetFlashLatency().

__STATIC_INLINE void LL_FLASH_SuspendOperation ( void )

Suspend new program or erase operation request.

Note:
Any new Flash program and erase operation on both CPU side will be suspended until this bit and the same bit in Flash CPU2 access control register (FLASH_C2ACR) are cleared. The PESD bit in both the Flash status register (FLASH_SR) and Flash CPU2 status register (FLASH_C2SR) register will be set when at least one PES bit in FLASH_ACR or FLASH_C2ACR is set.
Reference Manual to LL API cross reference:
FLASH_ACR PES LL_FLASH_SuspendOperation
Reference Manual to LL API cross reference:
FLASH_C2ACR PES LL_FLASH_SuspendOperation
Return values:
None

Definition at line 2077 of file stm32wbxx_ll_system.h.

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM

Modules
TIM
STM32WBxx_LL_Driver

Modules

TIM Private Functions

Private functions.

TIM Private Variables
TIM Private Constants
TIM Private Macros
TIM Exported Init structure
TIM Exported Constants
TIM Exported Macros
TIM Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for TIM registers.

Register | Bit | Function
AF1 | BKCMP1E | LL_TIM_DisableBreakInputSource
 |  | LL_TIM_EnableBreakInputSource
 | BKCMP1P | LL_TIM_SetBreakInputSourcePolarity
 | BKCMP2E | LL_TIM_DisableBreakInputSource
 |  | LL_TIM_EnableBreakInputSource
 | BKCMP2P | LL_TIM_SetBreakInputSourcePolarity
 | BKINE | LL_TIM_DisableBreakInputSource
 |  | LL_TIM_EnableBreakInputSource
 | BKINP | LL_TIM_SetBreakInputSourcePolarity
 | ETRSEL | LL_TIM_SetETRSource
AF2 | BK2CMP1E | LL_TIM_DisableBreakInputSource
 |  | LL_TIM_EnableBreakInputSource
 | BK2CMP1P | LL_TIM_SetBreakInputSourcePolarity
 | BK2CMP2E | LL_TIM_DisableBreakInputSource
 |  | LL_TIM_EnableBreakInputSource
 | BK2CMP2P | LL_TIM_SetBreakInputSourcePolarity
 | BK2INE | LL_TIM_DisableBreakInputSource
 |  | LL_TIM_EnableBreakInputSource
 | BK2INP | LL_TIM_SetBreakInputSourcePolarity
ARR | ARR | LL_TIM_GetAutoReload
 |  | LL_TIM_SetAutoReload
BDTR | AOE | LL_TIM_DisableAutomaticOutput
 |  | LL_TIM_EnableAutomaticOutput
 |  | LL_TIM_IsEnabledAutomaticOutput
 | BK2E | LL_TIM_DisableBRK2
 |  | LL_TIM_EnableBRK2
 | BK2F | LL_TIM_ConfigBRK2
 | BK2P | LL_TIM_ConfigBRK2
 | BKE | LL_TIM_DisableBRK
 |  | LL_TIM_EnableBRK
 | BKF | LL_TIM_ConfigBRK
 | BKP | LL_TIM_ConfigBRK
 | DTG | LL_TIM_OC_SetDeadTime
 | LOCK | LL_TIM_CC_SetLockLevel
 | MOE | LL_TIM_DisableAllOutputs
 |  | LL_TIM_EnableAllOutputs
 |  | LL_TIM_IsEnabledAllOutputs
 | OSSI | LL_TIM_SetOffStates
 | OSSR | LL_TIM_SetOffStates
CCER | CC1E | LL_TIM_CC_DisableChannel
 |  | LL_TIM_CC_EnableChannel
 |  | LL_TIM_CC_IsEnabledChannel
 | CC1NE | LL_TIM_CC_DisableChannel
 |  | LL_TIM_CC_EnableChannel
 |  | LL_TIM_CC_IsEnabledChannel
 | CC1NP | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPolarity
 |  | LL_TIM_IC_SetPolarity
 |  | LL_TIM_OC_GetPolarity
 |  | LL_TIM_OC_SetPolarity
 | CC1P | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPolarity
 |  | LL_TIM_IC_SetPolarity
 |  | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetPolarity
 |  | LL_TIM_OC_SetPolarity
 | CC2E | LL_TIM_CC_DisableChannel
 |  | LL_TIM_CC_EnableChannel
 |  | LL_TIM_CC_IsEnabledChannel
 | CC2NE | LL_TIM_CC_DisableChannel
 |  | LL_TIM_CC_EnableChannel
 |  | LL_TIM_CC_IsEnabledChannel
 | CC2NP | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPolarity
 |  | LL_TIM_IC_SetPolarity
 |  | LL_TIM_OC_GetPolarity
 |  | LL_TIM_OC_SetPolarity
 | CC2P | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPolarity
 |  | LL_TIM_IC_SetPolarity
 |  | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetPolarity
 |  | LL_TIM_OC_SetPolarity
 | CC3E | LL_TIM_CC_DisableChannel
 |  | LL_TIM_CC_EnableChannel
 |  | LL_TIM_CC_IsEnabledChannel
 | CC3NE | LL_TIM_CC_DisableChannel
 |  | LL_TIM_CC_EnableChannel
 |  | LL_TIM_CC_IsEnabledChannel
 | CC3NP | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPolarity
 |  | LL_TIM_IC_SetPolarity
 |  | LL_TIM_OC_GetPolarity
 |  | LL_TIM_OC_SetPolarity
 | CC3P | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPolarity
 |  | LL_TIM_IC_SetPolarity
 |  | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetPolarity
 |  | LL_TIM_OC_SetPolarity
 | CC4E | LL_TIM_CC_DisableChannel
 |  | LL_TIM_CC_EnableChannel
 |  | LL_TIM_CC_IsEnabledChannel
 | CC4NP | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPolarity
 |  | LL_TIM_IC_SetPolarity
 | CC4P | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPolarity
 |  | LL_TIM_IC_SetPolarity
 |  | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetPolarity
 |  | LL_TIM_OC_SetPolarity
 | CC5E | LL_TIM_CC_DisableChannel
 |  | LL_TIM_CC_EnableChannel
 |  | LL_TIM_CC_IsEnabledChannel
 | CC5P | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetPolarity
 |  | LL_TIM_OC_SetPolarity
 | CC6E | LL_TIM_CC_DisableChannel
 |  | LL_TIM_CC_EnableChannel
 |  | LL_TIM_CC_IsEnabledChannel
 | CC6P | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetPolarity
 |  | LL_TIM_OC_SetPolarity
CCMR1 | CC1S | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetActiveInput
 |  | LL_TIM_IC_SetActiveInput
 |  | LL_TIM_OC_ConfigOutput
 | CC2S | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetActiveInput
 |  | LL_TIM_IC_SetActiveInput
 |  | LL_TIM_OC_ConfigOutput
 | IC1F | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetFilter
 |  | LL_TIM_IC_SetFilter
 | IC1PSC | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPrescaler
 |  | LL_TIM_IC_SetPrescaler
 | IC2F | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetFilter
 |  | LL_TIM_IC_SetFilter
 | IC2PSC | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPrescaler
 |  | LL_TIM_IC_SetPrescaler
 | OC1CE | LL_TIM_OC_DisableClear
 |  | LL_TIM_OC_EnableClear
 |  | LL_TIM_OC_IsEnabledClear
 | OC1FE | LL_TIM_OC_DisableFast
 |  | LL_TIM_OC_EnableFast
 |  | LL_TIM_OC_IsEnabledFast
 | OC1M | LL_TIM_OC_GetMode
 |  | LL_TIM_OC_SetMode
 | OC1PE | LL_TIM_OC_DisablePreload
 |  | LL_TIM_OC_EnablePreload
 |  | LL_TIM_OC_IsEnabledPreload
 | OC2CE | LL_TIM_OC_DisableClear
 |  | LL_TIM_OC_EnableClear
 |  | LL_TIM_OC_IsEnabledClear
 | OC2FE | LL_TIM_OC_DisableFast
 |  | LL_TIM_OC_EnableFast
 |  | LL_TIM_OC_IsEnabledFast
 | OC2M | LL_TIM_OC_GetMode
 |  | LL_TIM_OC_SetMode
 | OC2PE | LL_TIM_OC_DisablePreload
 |  | LL_TIM_OC_EnablePreload
 |  | LL_TIM_OC_IsEnabledPreload
CCMR2 | CC3S | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetActiveInput
 |  | LL_TIM_IC_SetActiveInput
 |  | LL_TIM_OC_ConfigOutput
 | CC4S | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetActiveInput
 |  | LL_TIM_IC_SetActiveInput
 |  | LL_TIM_OC_ConfigOutput
 | IC3F | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetFilter
 |  | LL_TIM_IC_SetFilter
 | IC3PSC | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPrescaler
 |  | LL_TIM_IC_SetPrescaler
 | IC4F | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetFilter
 |  | LL_TIM_IC_SetFilter
 | IC4PSC | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPrescaler
 |  | LL_TIM_IC_SetPrescaler
 | OC3CE | LL_TIM_OC_DisableClear
 |  | LL_TIM_OC_EnableClear
 |  | LL_TIM_OC_IsEnabledClear
 | OC3FE | LL_TIM_OC_DisableFast
 |  | LL_TIM_OC_EnableFast
 |  | LL_TIM_OC_IsEnabledFast
 | OC3M | LL_TIM_OC_GetMode
 |  | LL_TIM_OC_SetMode
 | OC3PE | LL_TIM_OC_DisablePreload
 |  | LL_TIM_OC_EnablePreload
 |  | LL_TIM_OC_IsEnabledPreload
 | OC4CE | LL_TIM_OC_DisableClear
 |  | LL_TIM_OC_EnableClear
 |  | LL_TIM_OC_IsEnabledClear
 | OC4FE | LL_TIM_OC_DisableFast
 |  | LL_TIM_OC_EnableFast
 |  | LL_TIM_OC_IsEnabledFast
 | OC4M | LL_TIM_OC_GetMode
 |  | LL_TIM_OC_SetMode
 | OC4PE | LL_TIM_OC_DisablePreload
 |  | LL_TIM_OC_EnablePreload
 |  | LL_TIM_OC_IsEnabledPreload
CCMR3 | CC5S | LL_TIM_OC_ConfigOutput
 | CC6S | LL_TIM_OC_ConfigOutput
 | OC5CE | LL_TIM_OC_DisableClear
 |  | LL_TIM_OC_EnableClear
 |  | LL_TIM_OC_IsEnabledClear
 | OC5FE | LL_TIM_OC_DisableFast
 |  | LL_TIM_OC_EnableFast
 |  | LL_TIM_OC_IsEnabledFast
 | OC5M | LL_TIM_OC_GetMode
 |  | LL_TIM_OC_SetMode
 | OC5PE | LL_TIM_OC_DisablePreload
 |  | LL_TIM_OC_EnablePreload
 |  | LL_TIM_OC_IsEnabledPreload
 | OC6CE | LL_TIM_OC_DisableClear
 |  | LL_TIM_OC_EnableClear
 |  | LL_TIM_OC_IsEnabledClear
 | OC6FE | LL_TIM_OC_DisableFast
 |  | LL_TIM_OC_EnableFast
 |  | LL_TIM_OC_IsEnabledFast
 | OC6M | LL_TIM_OC_GetMode
 |  | LL_TIM_OC_SetMode
 | OC6PE | LL_TIM_OC_DisablePreload
 |  | LL_TIM_OC_EnablePreload
 |  | LL_TIM_OC_IsEnabledPreload
CCR1 | CCR1 | LL_TIM_IC_GetCaptureCH1
 |  | LL_TIM_OC_GetCompareCH1
 |  | LL_TIM_OC_SetCompareCH1
CCR2 | CCR2 | LL_TIM_IC_GetCaptureCH2
 |  | LL_TIM_OC_GetCompareCH2
 |  | LL_TIM_OC_SetCompareCH2
CCR3 | CCR3 | LL_TIM_IC_GetCaptureCH3
 |  | LL_TIM_OC_GetCompareCH3
 |  | LL_TIM_OC_SetCompareCH3
CCR4 | CCR4 | LL_TIM_IC_GetCaptureCH4
 |  | LL_TIM_OC_GetCompareCH4
 |  | LL_TIM_OC_SetCompareCH4
CCR5 | CCR5 | LL_TIM_OC_GetCompareCH5
 |  | LL_TIM_OC_SetCompareCH5
 | GC5C1 | LL_TIM_SetCH5CombinedChannels
 | GC5C2 | LL_TIM_SetCH5CombinedChannels
 | GC5C3 | LL_TIM_SetCH5CombinedChannels
CCR6 | CCR6 | LL_TIM_OC_GetCompareCH6
 |  | LL_TIM_OC_SetCompareCH6
CNT | CNT | LL_TIM_GetCounter
 |  | LL_TIM_SetCounter
CR1 | ARPE | LL_TIM_DisableARRPreload
 |  | LL_TIM_EnableARRPreload
 |  | LL_TIM_IsEnabledARRPreload
 | CEN | LL_TIM_DisableCounter
 |  | LL_TIM_EnableCounter
 |  | LL_TIM_IsEnabledCounter
 | CKD | LL_TIM_GetClockDivision
 |  | LL_TIM_SetClockDivision
 | CMS | LL_TIM_GetCounterMode
 |  | LL_TIM_SetCounterMode
 | DIR | LL_TIM_GetCounterMode
 |  | LL_TIM_GetDirection
 |  | LL_TIM_SetCounterMode
 | OPM | LL_TIM_GetOnePulseMode
 |  | LL_TIM_SetOnePulseMode
 | UDIS | LL_TIM_DisableUpdateEvent
 |  | LL_TIM_EnableUpdateEvent
 |  | LL_TIM_IsEnabledUpdateEvent
 | UIFREMAP | LL_TIM_DisableUIFRemap
 |  | LL_TIM_EnableUIFRemap
 | URS | LL_TIM_GetUpdateSource
 |  | LL_TIM_SetUpdateSource
CR2 | CCDS | LL_TIM_CC_GetDMAReqTrigger
 |  | LL_TIM_CC_SetDMAReqTrigger
 | CCPC | LL_TIM_CC_DisablePreload
 |  | LL_TIM_CC_EnablePreload
 | CCUS | LL_TIM_CC_SetUpdate
 | MMS | LL_TIM_SetTriggerOutput
 | MMS2 | LL_TIM_SetTriggerOutput2
 | OIS1 | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetIdleState
 |  | LL_TIM_OC_SetIdleState
 | OIS2 | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetIdleState
 |  | LL_TIM_OC_SetIdleState
 | OIS2N | LL_TIM_OC_GetIdleState
 |  | LL_TIM_OC_SetIdleState
 | OIS3 | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetIdleState
 |  | LL_TIM_OC_SetIdleState
 | OIS3N | LL_TIM_OC_GetIdleState
 |  | LL_TIM_OC_SetIdleState
 | OIS4 | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetIdleState
 |  | LL_TIM_OC_SetIdleState
 | OIS5 | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetIdleState
 |  | LL_TIM_OC_SetIdleState
 | OIS6 | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetIdleState
 |  | LL_TIM_OC_SetIdleState
 | TI1S | LL_TIM_IC_DisableXORCombination
 |  | LL_TIM_IC_EnableXORCombination
 |  | LL_TIM_IC_IsEnabledXORCombination
DCR | DBA | LL_TIM_ConfigDMABurst
 | DBL | LL_TIM_ConfigDMABurst
DIER | BIE | LL_TIM_DisableIT_BRK
 |  | LL_TIM_EnableIT_BRK
 |  | LL_TIM_IsEnabledIT_BRK
 | CC1DE | LL_TIM_DisableDMAReq_CC1
 |  | LL_TIM_EnableDMAReq_CC1
 |  | LL_TIM_IsEnabledDMAReq_CC1
 | CC1IE | LL_TIM_DisableIT_CC1
 |  | LL_TIM_EnableIT_CC1
 |  | LL_TIM_IsEnabledIT_CC1
 | CC2DE | LL_TIM_DisableDMAReq_CC2
 |  | LL_TIM_EnableDMAReq_CC2
 |  | LL_TIM_IsEnabledDMAReq_CC2
 | CC2IE | LL_TIM_DisableIT_CC2
 |  | LL_TIM_EnableIT_CC2
 |  | LL_TIM_IsEnabledIT_CC2
 | CC3DE | LL_TIM_DisableDMAReq_CC3
 |  | LL_TIM_EnableDMAReq_CC3
 |  | LL_TIM_IsEnabledDMAReq_CC3
 | CC3IE | LL_TIM_DisableIT_CC3
 |  | LL_TIM_EnableIT_CC3
 |  | LL_TIM_IsEnabledIT_CC3
 | CC4DE | LL_TIM_DisableDMAReq_CC4
 |  | LL_TIM_EnableDMAReq_CC4
 |  | LL_TIM_IsEnabledDMAReq_CC4
 | CC4IE | LL_TIM_DisableIT_CC4
 |  | LL_TIM_EnableIT_CC4
 |  | LL_TIM_IsEnabledIT_CC4
 | COMDE | LL_TIM_DisableDMAReq_COM
 |  | LL_TIM_EnableDMAReq_COM
 |  | LL_TIM_IsEnabledDMAReq_COM
 | COMIE | LL_TIM_DisableIT_COM
 |  | LL_TIM_EnableIT_COM
 |  | LL_TIM_IsEnabledIT_COM
 | TDE | LL_TIM_DisableDMAReq_TRIG
 |  | LL_TIM_EnableDMAReq_TRIG
 |  | LL_TIM_IsEnabledDMAReq_TRIG
 | TIE | LL_TIM_DisableIT_TRIG
 |  | LL_TIM_EnableIT_TRIG
 |  | LL_TIM_IsEnabledIT_TRIG
 | UDE | LL_TIM_DisableDMAReq_UPDATE
 |  | LL_TIM_EnableDMAReq_UPDATE
 |  | LL_TIM_IsEnabledDMAReq_UPDATE
 | UIE | LL_TIM_DisableIT_UPDATE
 |  | LL_TIM_EnableIT_UPDATE
 |  | LL_TIM_IsEnabledIT_UPDATE
EGR | B2G | LL_TIM_GenerateEvent_BRK2
 | BG | LL_TIM_GenerateEvent_BRK
 | CC1G | LL_TIM_GenerateEvent_CC1
 | CC2G | LL_TIM_GenerateEvent_CC2
 | CC3G | LL_TIM_GenerateEvent_CC3
 | CC4G | LL_TIM_GenerateEvent_CC4
 | COMG | LL_TIM_GenerateEvent_COM
 | TG | LL_TIM_GenerateEvent_TRIG
 | UG | LL_TIM_GenerateEvent_UPDATE
PSC | PSC | LL_TIM_GetPrescaler
 |  | LL_TIM_SetPrescaler
RCR | REP | LL_TIM_GetRepetitionCounter
 |  | LL_TIM_SetRepetitionCounter
SMCR | ECE | LL_TIM_DisableExternalClock
 |  | LL_TIM_EnableExternalClock
 |  | LL_TIM_IsEnabledExternalClock
 |  | LL_TIM_SetClockSource
 | ETF | LL_TIM_ConfigETR
 | ETP | LL_TIM_ConfigETR
 | ETPS | LL_TIM_ConfigETR
 | MSM | LL_TIM_DisableMasterSlaveMode
 |  | LL_TIM_EnableMasterSlaveMode
 |  | LL_TIM_IsEnabledMasterSlaveMode
 | OCCS | LL_TIM_SetOCRefClearInputSource
 | SMS | LL_TIM_SetClockSource
 |  | LL_TIM_SetEncoderMode
 |  | LL_TIM_SetSlaveMode
 | TS | LL_TIM_SetTriggerInput
SR | B2IF | LL_TIM_ClearFlag_BRK2
 |  | LL_TIM_IsActiveFlag_BRK2
 | BIF | LL_TIM_ClearFlag_BRK
 |  | LL_TIM_IsActiveFlag_BRK
 | CC1IF | LL_TIM_ClearFlag_CC1
 |  | LL_TIM_IsActiveFlag_CC1
 | CC1OF | LL_TIM_ClearFlag_CC1OVR
 |  | LL_TIM_IsActiveFlag_CC1OVR
 | CC2IF | LL_TIM_ClearFlag_CC2
 |  | LL_TIM_IsActiveFlag_CC2
 | CC2OF | LL_TIM_ClearFlag_CC2OVR
 |  | LL_TIM_IsActiveFlag_CC2OVR
 | CC3IF | LL_TIM_ClearFlag_CC3
 |  | LL_TIM_IsActiveFlag_CC3
 | CC3OF | LL_TIM_ClearFlag_CC3OVR
 |  | LL_TIM_IsActiveFlag_CC3OVR
 | CC4IF | LL_TIM_ClearFlag_CC4
 |  | LL_TIM_IsActiveFlag_CC4
 | CC4OF | LL_TIM_ClearFlag_CC4OVR
 |  | LL_TIM_IsActiveFlag_CC4OVR
 | CC5IF | LL_TIM_ClearFlag_CC5
 |  | LL_TIM_IsActiveFlag_CC5
 | CC6IF | LL_TIM_ClearFlag_CC6
 |  | LL_TIM_IsActiveFlag_CC6
 | COMIF | LL_TIM_ClearFlag_COM
 |  | LL_TIM_IsActiveFlag_COM
 | SBIF | LL_TIM_ClearFlag_SYSBRK
 |  | LL_TIM_IsActiveFlag_SYSBRK
 | TIF | LL_TIM_ClearFlag_TRIG
 |  | LL_TIM_IsActiveFlag_TRIG
 | UIF | LL_TIM_ClearFlag_UPDATE
 |  | LL_TIM_IsActiveFlag_UPDATE
TIM16_OR | TI1_RMP | LL_TIM_SetRemap
TIM17_OR | TI1_RMP | LL_TIM_SetRemap
TIM1_OR | ETR_ADC1_RMP | LL_TIM_SetRemap
 | TI1_RMP | LL_TIM_SetRemap
TIM2_OR | ITR1_RMP | LL_TIM_SetRemap
 | TI1_RMP | LL_TIM_SetRemap
 | TI4_RMP | LL_TIM_SetRemap
Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM Private Functions

Functions
TIM Private Functions
TIM

Private functions. More...

Functions

static ErrorStatus | OC1Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 1.
static ErrorStatus | OC2Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 2.
static ErrorStatus | OC3Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 3.
static ErrorStatus | OC4Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 4.
static ErrorStatus | OC5Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 5.
static ErrorStatus | OC6Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 6.
static ErrorStatus | IC1Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 1.
static ErrorStatus | IC2Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 2.
static ErrorStatus | IC3Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 3.
static ErrorStatus | IC4Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 4.

Detailed Description

Private functions.

Function Documentation

static ErrorStatus IC1Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_IC_InitTypeDef * | TIM_ICInitStruct
 | ) |  | [static]

Configure the TIMx input channel 1.

Parameters:
TIMx | Timer Instance
TIM_ICInitStruct | pointer to the the TIMx input channel 1 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1163 of file stm32wbxx_ll_tim.c.

References assert_param, LL_TIM_IC_InitTypeDef::ICActiveInput, LL_TIM_IC_InitTypeDef::ICFilter, LL_TIM_IC_InitTypeDef::ICPolarity, LL_TIM_IC_InitTypeDef::ICPrescaler, IS_LL_TIM_ACTIVEINPUT, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY, and IS_LL_TIM_ICPSC.

Referenced by LL_TIM_IC_Init().

static ErrorStatus IC2Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_IC_InitTypeDef * | TIM_ICInitStruct
 | ) |  | [static]

Configure the TIMx input channel 2.

Parameters:
TIMx | Timer Instance
TIM_ICInitStruct | pointer to the the TIMx input channel 2 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1196 of file stm32wbxx_ll_tim.c.

References assert_param, LL_TIM_IC_InitTypeDef::ICActiveInput, LL_TIM_IC_InitTypeDef::ICFilter, LL_TIM_IC_InitTypeDef::ICPolarity, LL_TIM_IC_InitTypeDef::ICPrescaler, IS_LL_TIM_ACTIVEINPUT, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY, and IS_LL_TIM_ICPSC.

Referenced by LL_TIM_IC_Init().

static ErrorStatus IC3Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_IC_InitTypeDef * | TIM_ICInitStruct
 | ) |  | [static]

Configure the TIMx input channel 3.

Parameters:
TIMx | Timer Instance
TIM_ICInitStruct | pointer to the the TIMx input channel 3 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1229 of file stm32wbxx_ll_tim.c.

References assert_param, LL_TIM_IC_InitTypeDef::ICActiveInput, LL_TIM_IC_InitTypeDef::ICFilter, LL_TIM_IC_InitTypeDef::ICPolarity, LL_TIM_IC_InitTypeDef::ICPrescaler, IS_LL_TIM_ACTIVEINPUT, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY, and IS_LL_TIM_ICPSC.

Referenced by LL_TIM_IC_Init().

static ErrorStatus IC4Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_IC_InitTypeDef * | TIM_ICInitStruct
 | ) |  | [static]

Configure the TIMx input channel 4.

Parameters:
TIMx | Timer Instance
TIM_ICInitStruct | pointer to the the TIMx input channel 4 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1262 of file stm32wbxx_ll_tim.c.

References assert_param, LL_TIM_IC_InitTypeDef::ICActiveInput, LL_TIM_IC_InitTypeDef::ICFilter, LL_TIM_IC_InitTypeDef::ICPolarity, LL_TIM_IC_InitTypeDef::ICPrescaler, IS_LL_TIM_ACTIVEINPUT, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY, and IS_LL_TIM_ICPSC.

Referenced by LL_TIM_IC_Init().

static ErrorStatus OC1Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_OC_InitTypeDef * | TIM_OCInitStruct
 | ) |  | [static]

Configure the TIMx output channel 1.

Parameters:
TIMx | Timer Instance
TIM_OCInitStruct | pointer to the the TIMx output channel 1 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 735 of file stm32wbxx_ll_tim.c.

References assert_param, LL_TIM_OC_InitTypeDef::CompareValue, IS_LL_TIM_OCIDLESTATE, IS_LL_TIM_OCMODE, IS_LL_TIM_OCPOLARITY, IS_LL_TIM_OCSTATE, LL_TIM_OC_SetCompareCH1(), LL_TIM_ReadReg, LL_TIM_WriteReg, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

Referenced by LL_TIM_OC_Init().

static ErrorStatus OC2Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_OC_InitTypeDef * | TIM_OCInitStruct
 | ) |  | [static]

Configure the TIMx output channel 2.

Parameters:
TIMx | Timer Instance
TIM_OCInitStruct | pointer to the the TIMx output channel 2 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 814 of file stm32wbxx_ll_tim.c.

References assert_param, LL_TIM_OC_InitTypeDef::CompareValue, IS_LL_TIM_OCIDLESTATE, IS_LL_TIM_OCMODE, IS_LL_TIM_OCPOLARITY, IS_LL_TIM_OCSTATE, LL_TIM_OC_SetCompareCH2(), LL_TIM_ReadReg, LL_TIM_WriteReg, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

Referenced by LL_TIM_OC_Init().

static ErrorStatus OC3Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_OC_InitTypeDef * | TIM_OCInitStruct
 | ) |  | [static]

Configure the TIMx output channel 3.

Parameters:
TIMx | Timer Instance
TIM_OCInitStruct | pointer to the the TIMx output channel 3 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 893 of file stm32wbxx_ll_tim.c.

References assert_param, LL_TIM_OC_InitTypeDef::CompareValue, IS_LL_TIM_OCIDLESTATE, IS_LL_TIM_OCMODE, IS_LL_TIM_OCPOLARITY, IS_LL_TIM_OCSTATE, LL_TIM_OC_SetCompareCH3(), LL_TIM_ReadReg, LL_TIM_WriteReg, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

Referenced by LL_TIM_OC_Init().

static ErrorStatus OC4Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_OC_InitTypeDef * | TIM_OCInitStruct
 | ) |  | [static]

Configure the TIMx output channel 4.

Parameters:
TIMx | Timer Instance
TIM_OCInitStruct | pointer to the the TIMx output channel 4 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 972 of file stm32wbxx_ll_tim.c.

References assert_param, LL_TIM_OC_InitTypeDef::CompareValue, IS_LL_TIM_OCIDLESTATE, IS_LL_TIM_OCMODE, IS_LL_TIM_OCPOLARITY, IS_LL_TIM_OCSTATE, LL_TIM_OC_SetCompareCH4(), LL_TIM_ReadReg, LL_TIM_WriteReg, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

Referenced by LL_TIM_OC_Init().

static ErrorStatus OC5Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_OC_InitTypeDef * | TIM_OCInitStruct
 | ) |  | [static]

Configure the TIMx output channel 5.

Parameters:
TIMx | Timer Instance
TIM_OCInitStruct | pointer to the the TIMx output channel 5 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1042 of file stm32wbxx_ll_tim.c.

References assert_param, LL_TIM_OC_InitTypeDef::CompareValue, IS_LL_TIM_OCIDLESTATE, IS_LL_TIM_OCMODE, IS_LL_TIM_OCPOLARITY, IS_LL_TIM_OCSTATE, LL_TIM_OC_SetCompareCH5(), LL_TIM_ReadReg, LL_TIM_WriteReg, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

Referenced by LL_TIM_OC_Init().

static ErrorStatus OC6Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_OC_InitTypeDef * | TIM_OCInitStruct
 | ) |  | [static]

Configure the TIMx output channel 6.

Parameters:
TIMx | Timer Instance
TIM_OCInitStruct | pointer to the the TIMx output channel 6 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1103 of file stm32wbxx_ll_tim.c.

References assert_param, LL_TIM_OC_InitTypeDef::CompareValue, IS_LL_TIM_OCIDLESTATE, IS_LL_TIM_OCMODE, IS_LL_TIM_OCPOLARITY, IS_LL_TIM_OCSTATE, LL_TIM_OC_SetCompareCH6(), LL_TIM_ReadReg, LL_TIM_WriteReg, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

Referenced by LL_TIM_OC_Init().

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM Private Variables

Variables
TIM Private Variables
TIM

Variables

static const uint8_t | OFFSET_TAB_CCMRx []
static const uint8_t | SHIFT_TAB_OCxx []
static const uint8_t | SHIFT_TAB_ICxx []
static const uint8_t | SHIFT_TAB_CCxP []
static const uint8_t | SHIFT_TAB_OISx []

Variable Documentation

const uint8_t OFFSET_TAB_CCMRx[] [static]
Initial value:
{
  0x00U,
  0x00U,
  0x00U,
  0x00U,
  0x04U,
  0x04U,
  0x04U,
  0x3CU,
  0x3CU
}

Definition at line 46 of file stm32wbxx_ll_tim.h.

const uint8_t SHIFT_TAB_CCxP[] [static]
Initial value:
{
  0U,
  2U,
  4U,
  6U,
  8U,
  10U,
  12U,
  16U,
  20U
}

Definition at line 85 of file stm32wbxx_ll_tim.h.

const uint8_t SHIFT_TAB_ICxx[] [static]
Initial value:
{
  0U,
  0U,
  8U,
  0U,
  0U,
  0U,
  8U,
  0U,
  0U
}

Definition at line 72 of file stm32wbxx_ll_tim.h.

const uint8_t SHIFT_TAB_OCxx[] [static]
Initial value:
{
  0U,
  0U,
  8U,
  0U,
  0U,
  0U,
  8U,
  0U,
  8U
}

Definition at line 59 of file stm32wbxx_ll_tim.h.

const uint8_t SHIFT_TAB_OISx[] [static]
Initial value:
{
  0U,
  1U,
  2U,
  3U,
  4U,
  5U,
  6U,
  8U,
  10U
}

Definition at line 98 of file stm32wbxx_ll_tim.h.

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM Private Constants

Defines
TIM Private Constants
TIM

Defines

#define | TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
#define | TIMx_AF1_BKINE TIM1_AF1_BKINE
#define | TIMx_AF1_BKCOMP1E TIM1_AF1_BKCMP1E
#define | TIMx_AF1_BKCOMP2E TIM1_AF1_BKCMP2E
#define | TIMx_AF1_BKINP TIM1_AF1_BKINP
#define | TIMx_AF1_BKCOMP1P TIM1_AF1_BKCMP1P
#define | TIMx_AF1_BKCOMP2P TIM1_AF1_BKCMP2P
#define | TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL
#define | TIMx_AF2_BK2INE TIM1_AF2_BK2INE
#define | TIMx_AF2_BK2COMP1E TIM1_AF2_BK2CMP1E
#define | TIMx_AF2_BK2COMP2E TIM1_AF2_BK2CMP2E
#define | TIMx_AF2_BK2INP TIM1_AF2_BK2INP
#define | TIMx_AF2_BK2COMP1P TIM1_AF2_BK2CMP1P
#define | TIMx_AF2_BK2COMP2P TIM1_AF2_BK2CMP2P
#define | TIMx_OR_RMP_SHIFT 16U
#define | TIMx_OR_RMP_MASK 0x0000FFFFU
#define | TIM1_OR_RMP_MASK ((TIM1_OR_ETR_ADC1_RMP | TIM1_OR_TI1_RMP) << TIMx_OR_RMP_SHIFT)
#define | TIM2_OR_RMP_MASK ((TIM2_OR_TI4_RMP | TIM2_OR_ETR_RMP | TIM2_OR_ITR1_RMP) << TIMx_OR_RMP_SHIFT)
#define | TIM16_OR_RMP_MASK (TIM16_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
#define | TIM17_OR_RMP_MASK (TIM17_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
#define | DT_DELAY_1 ((uint8_t)0x7F)
#define | DT_DELAY_2 ((uint8_t)0x3F)
#define | DT_DELAY_3 ((uint8_t)0x1F)
#define | DT_DELAY_4 ((uint8_t)0x1F)
#define | DT_RANGE_1 ((uint8_t)0x00)
#define | DT_RANGE_2 ((uint8_t)0x80)
#define | DT_RANGE_3 ((uint8_t)0xC0)
#define | DT_RANGE_4 ((uint8_t)0xE0)

Define Documentation

#define DT_DELAY_1 ((uint8_t)0x7F)

Definition at line 156 of file stm32wbxx_ll_tim.h.

#define DT_DELAY_2 ((uint8_t)0x3F)

Definition at line 157 of file stm32wbxx_ll_tim.h.

#define DT_DELAY_3 ((uint8_t)0x1F)

Definition at line 158 of file stm32wbxx_ll_tim.h.

#define DT_DELAY_4 ((uint8_t)0x1F)

Definition at line 159 of file stm32wbxx_ll_tim.h.

#define DT_RANGE_1 ((uint8_t)0x00)

Definition at line 162 of file stm32wbxx_ll_tim.h.

#define DT_RANGE_2 ((uint8_t)0x80)

Definition at line 163 of file stm32wbxx_ll_tim.h.

#define DT_RANGE_3 ((uint8_t)0xC0)

Definition at line 164 of file stm32wbxx_ll_tim.h.

#define DT_RANGE_4 ((uint8_t)0xE0)

Definition at line 165 of file stm32wbxx_ll_tim.h.

#define TIM16_OR_RMP_MASK (TIM16_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)

Definition at line 152 of file stm32wbxx_ll_tim.h.

#define TIM17_OR_RMP_MASK (TIM17_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)

Definition at line 153 of file stm32wbxx_ll_tim.h.

#define TIM1_OR_RMP_MASK ((TIM1_OR_ETR_ADC1_RMP | TIM1_OR_TI1_RMP) << TIMx_OR_RMP_SHIFT)

Definition at line 150 of file stm32wbxx_ll_tim.h.

#define TIM2_OR_RMP_MASK ((TIM2_OR_TI4_RMP | TIM2_OR_ETR_RMP | TIM2_OR_ITR1_RMP) << TIMx_OR_RMP_SHIFT)

Definition at line 151 of file stm32wbxx_ll_tim.h.

#define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)

Definition at line 120 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_SetBreakInputSourcePolarity().

#define TIMx_AF1_BKCOMP1E TIM1_AF1_BKCMP1E

BRK COMP1 enable

Definition at line 125 of file stm32wbxx_ll_tim.h.

#define TIMx_AF1_BKCOMP1P TIM1_AF1_BKCMP1P

BRK COMP1 input polarity

Definition at line 130 of file stm32wbxx_ll_tim.h.

#define TIMx_AF1_BKCOMP2E TIM1_AF1_BKCMP2E

BRK COMP2 enable

Definition at line 126 of file stm32wbxx_ll_tim.h.

#define TIMx_AF1_BKCOMP2P TIM1_AF1_BKCMP2P

BRK COMP2 input polarity

Definition at line 131 of file stm32wbxx_ll_tim.h.

#define TIMx_AF1_BKINE TIM1_AF1_BKINE

BRK BKIN input enable

Definition at line 123 of file stm32wbxx_ll_tim.h.

#define TIMx_AF1_BKINP TIM1_AF1_BKINP

BRK BKIN input polarity

Definition at line 128 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_SetBreakInputSourcePolarity().

#define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL

TIMx ETR source selection

Definition at line 133 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_SetETRSource().

#define TIMx_AF2_BK2COMP1E TIM1_AF2_BK2CMP1E

BRK2 COMP1 enable

Definition at line 138 of file stm32wbxx_ll_tim.h.

#define TIMx_AF2_BK2COMP1P TIM1_AF2_BK2CMP1P

BRK2 COMP1 input polarity

Definition at line 143 of file stm32wbxx_ll_tim.h.

#define TIMx_AF2_BK2COMP2E TIM1_AF2_BK2CMP2E

BRK2 COMP2 enable

Definition at line 139 of file stm32wbxx_ll_tim.h.

#define TIMx_AF2_BK2COMP2P TIM1_AF2_BK2CMP2P

BRK2 COMP2 input polarity

Definition at line 144 of file stm32wbxx_ll_tim.h.

#define TIMx_AF2_BK2INE TIM1_AF2_BK2INE

BRK2 BKIN2 input enable

Definition at line 136 of file stm32wbxx_ll_tim.h.

#define TIMx_AF2_BK2INP TIM1_AF2_BK2INP

BRK2 BKIN2 input polarity

Definition at line 141 of file stm32wbxx_ll_tim.h.

#define TIMx_OR_RMP_MASK 0x0000FFFFU

Definition at line 149 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_SetRemap().

#define TIMx_OR_RMP_SHIFT 16U

Definition at line 148 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_SetRemap().

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM Private Macros

Defines
TIM Private Macros
TIM

Defines

#define | IS_LL_TIM_COUNTERMODE(__VALUE__)
#define | IS_LL_TIM_CLOCKDIVISION(__VALUE__)
#define | IS_LL_TIM_OCMODE(__VALUE__)
#define | IS_LL_TIM_OCSTATE(__VALUE__)
#define | IS_LL_TIM_OCPOLARITY(__VALUE__)
#define | IS_LL_TIM_OCIDLESTATE(__VALUE__)
#define | IS_LL_TIM_ACTIVEINPUT(__VALUE__)
#define | IS_LL_TIM_ICPSC(__VALUE__)
#define | IS_LL_TIM_IC_FILTER(__VALUE__)
#define | IS_LL_TIM_IC_POLARITY(__VALUE__)
#define | IS_LL_TIM_ENCODERMODE(__VALUE__)
#define | IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__)
#define | IS_LL_TIM_OSSR_STATE(__VALUE__)
#define | IS_LL_TIM_OSSI_STATE(__VALUE__)
#define | IS_LL_TIM_LOCK_LEVEL(__VALUE__)
#define | IS_LL_TIM_BREAK_STATE(__VALUE__)
#define | IS_LL_TIM_BREAK_POLARITY(__VALUE__)
#define | IS_LL_TIM_BREAK_FILTER(__VALUE__)
#define | IS_LL_TIM_BREAK2_STATE(__VALUE__)
#define | IS_LL_TIM_BREAK2_POLARITY(__VALUE__)
#define | IS_LL_TIM_BREAK2_FILTER(__VALUE__)
#define | IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__)
#define | TIM_GET_CHANNEL_INDEX(__CHANNEL__)
Convert channel id into channel index.
#define | TIM_CALC_DTS(__TIMCLK__, __CKD__)
Calculate the deadtime sampling period(in ps).

Define Documentation

#define IS_LL_TIM_ACTIVEINPUT ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
                                          || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
                                          || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))

Definition at line 82 of file stm32wbxx_ll_tim.c.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), and LL_TIM_ENCODER_Init().

#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
                                                     || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))

Definition at line 176 of file stm32wbxx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_BREAK2_FILTER ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1)    \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2)  \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4)  \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8)  \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6)  \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8)  \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6)  \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8)  \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6)  \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8)  \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))

Definition at line 159 of file stm32wbxx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_BREAK2_POLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
                                              || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))

Definition at line 156 of file stm32wbxx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_BREAK2_STATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
                                           || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))

Definition at line 153 of file stm32wbxx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_BREAK_FILTER ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1)     \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2)  \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4)  \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8)  \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6)  \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8)  \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6)  \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8)  \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6)  \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8)  \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))

Definition at line 136 of file stm32wbxx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_BREAK_POLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
                                             || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))

Definition at line 133 of file stm32wbxx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_BREAK_STATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_BREAK_DISABLE) \
                                          || ((__VALUE__) == LL_TIM_BREAK_ENABLE))

Definition at line 130 of file stm32wbxx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_CLOCKDIVISION ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
                                            || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
                                            || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))

Definition at line 54 of file stm32wbxx_ll_tim.c.

Referenced by LL_TIM_Init().

#define IS_LL_TIM_COUNTERMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))

Definition at line 48 of file stm32wbxx_ll_tim.c.

Referenced by LL_TIM_Init().

#define IS_LL_TIM_ENCODERMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
                                          || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
                                          || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))

Definition at line 112 of file stm32wbxx_ll_tim.c.

Referenced by LL_TIM_ENCODER_Init().

#define IS_LL_TIM_IC_FILTER ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))

Definition at line 91 of file stm32wbxx_ll_tim.c.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), LL_TIM_ENCODER_Init(), and LL_TIM_HALLSENSOR_Init().

#define IS_LL_TIM_IC_POLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
                                          || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
                                          || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))

Definition at line 108 of file stm32wbxx_ll_tim.c.

Referenced by IC1Config(), IC2Config(), IC3Config(), and IC4Config().

#define IS_LL_TIM_IC_POLARITY_ENCODER ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
                                                  || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))

Definition at line 116 of file stm32wbxx_ll_tim.c.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_HALLSENSOR_Init().

#define IS_LL_TIM_ICPSC ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_ICPSC_DIV1) \
                                    || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
                                    || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
                                    || ((__VALUE__) == LL_TIM_ICPSC_DIV8))

Definition at line 86 of file stm32wbxx_ll_tim.c.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), LL_TIM_ENCODER_Init(), and LL_TIM_HALLSENSOR_Init().

#define IS_LL_TIM_LOCK_LEVEL ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
                                         || ((__VALUE__) == LL_TIM_LOCKLEVEL_1)   \
                                         || ((__VALUE__) == LL_TIM_LOCKLEVEL_2)   \
                                         || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))

Definition at line 125 of file stm32wbxx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_OCIDLESTATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
                                          || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))

Definition at line 79 of file stm32wbxx_ll_tim.c.

Referenced by OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

#define IS_LL_TIM_OCMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
                                     || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))

Definition at line 58 of file stm32wbxx_ll_tim.c.

Referenced by OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

#define IS_LL_TIM_OCPOLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
                                         || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))

Definition at line 76 of file stm32wbxx_ll_tim.c.

Referenced by OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

#define IS_LL_TIM_OCSTATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
                                      || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))

Definition at line 73 of file stm32wbxx_ll_tim.c.

Referenced by OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

#define IS_LL_TIM_OSSI_STATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OSSI_DISABLE) \
                                         || ((__VALUE__) == LL_TIM_OSSI_ENABLE))

Definition at line 122 of file stm32wbxx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_OSSR_STATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OSSR_DISABLE) \
                                         || ((__VALUE__) == LL_TIM_OSSR_ENABLE))

Definition at line 119 of file stm32wbxx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define TIM_CALC_DTS | ( | __TIMCLK__,
 |  | __CKD__
 | ) |
Value:
(((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__))         : \
   ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
   ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))

Calculate the deadtime sampling period(in ps).

Parameters:
__TIMCLK__ timer input clock frequency (in Hz).
__CKD__ This parameter can be one of the following values:
  • LL_TIM_CLOCKDIVISION_DIV1
  • LL_TIM_CLOCKDIVISION_DIV2
  • LL_TIM_CLOCKDIVISION_DIV4
Return values:
none

Definition at line 213 of file stm32wbxx_ll_tim.h.

#define TIM_GET_CHANNEL_INDEX ( __CHANNEL__ )
Value:
(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
   ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
   ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
   ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
   ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
   ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
   ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
   ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)

Convert channel id into channel index.

Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
none

Definition at line 195 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_IC_Config(), LL_TIM_IC_GetActiveInput(), LL_TIM_IC_GetFilter(), LL_TIM_IC_GetPolarity(), LL_TIM_IC_GetPrescaler(), LL_TIM_IC_SetActiveInput(), LL_TIM_IC_SetFilter(), LL_TIM_IC_SetPolarity(), LL_TIM_IC_SetPrescaler(), LL_TIM_OC_ConfigOutput(), LL_TIM_OC_DisableClear(), LL_TIM_OC_DisableFast(), LL_TIM_OC_DisablePreload(), LL_TIM_OC_EnableClear(), LL_TIM_OC_EnableFast(), LL_TIM_OC_EnablePreload(), LL_TIM_OC_GetIdleState(), LL_TIM_OC_GetMode(), LL_TIM_OC_GetPolarity(), LL_TIM_OC_IsEnabledClear(), LL_TIM_OC_IsEnabledFast(), LL_TIM_OC_IsEnabledPreload(), LL_TIM_OC_SetIdleState(), LL_TIM_OC_SetMode(), and LL_TIM_OC_SetPolarity().

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LL_TIM_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_InitTypeDef Struct Reference
TIM Exported Init structure

TIM Time Base configuration structure definition. More...

#include <stm32wbxx_ll_tim.h>

Data Fields

uint16_t | Prescaler
uint32_t | CounterMode
uint32_t | Autoreload
uint32_t | ClockDivision
uint8_t | RepetitionCounter

Detailed Description

TIM Time Base configuration structure definition.

Definition at line 231 of file stm32wbxx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_InitTypeDef::Autoreload

Specifies the auto reload value to be loaded into the active Auto-Reload Register at the next update event. This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.

This feature can be modified afterwards using unitary function LL_TIM_SetAutoReload().

Definition at line 243 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_Init(), and LL_TIM_StructInit().

uint32_t LL_TIM_InitTypeDef::ClockDivision

Specifies the clock division. This parameter can be a value of Clock Division.

This feature can be modified afterwards using unitary function LL_TIM_SetClockDivision().

Definition at line 250 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_Init(), and LL_TIM_StructInit().

uint32_t LL_TIM_InitTypeDef::CounterMode

Specifies the counter mode. This parameter can be a value of Counter Mode.

This feature can be modified afterwards using unitary function LL_TIM_SetCounterMode().

Definition at line 238 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_Init(), and LL_TIM_StructInit().

uint16_t LL_TIM_InitTypeDef::Prescaler

Specifies the prescaler value used to divide the TIM clock. This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.

This feature can be modified afterwards using unitary function LL_TIM_SetPrescaler().

Definition at line 233 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_Init(), and LL_TIM_StructInit().

uint8_t LL_TIM_InitTypeDef::RepetitionCounter

Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts from the RCR value (N). This means in PWM mode that (N+1) corresponds to:

  • the number of PWM periods in edge-aligned mode
  • the number of half PWM period in center-aligned mode This parameter must be a number between 0x00 and 0xFF.

This feature can be modified afterwards using unitary function LL_TIM_SetRepetitionCounter().

Definition at line 255 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_Init(), and LL_TIM_StructInit().

The documentation for this struct was generated from the following file:
  • stm32wbxx_ll_tim.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LL_TIM_OC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_OC_InitTypeDef Struct Reference
TIM Exported Init structure

TIM Output Compare configuration structure definition. More...

#include <stm32wbxx_ll_tim.h>

Data Fields

uint32_t | OCMode
uint32_t | OCState
uint32_t | OCNState
uint32_t | CompareValue
uint32_t | OCPolarity
uint32_t | OCNPolarity
uint32_t | OCIdleState
uint32_t | OCNIdleState

Detailed Description

TIM Output Compare configuration structure definition.

Definition at line 269 of file stm32wbxx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_OC_InitTypeDef::CompareValue

Specifies the Compare value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).

Definition at line 286 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

uint32_t LL_TIM_OC_InitTypeDef::OCIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of Output Configuration Idle State.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetIdleState().

Definition at line 302 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

uint32_t LL_TIM_OC_InitTypeDef::OCMode

Specifies the output mode. This parameter can be a value of Output Configuration Mode.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetMode().

Definition at line 271 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

uint32_t LL_TIM_OC_InitTypeDef::OCNIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of Output Configuration Idle State.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetIdleState().

Definition at line 307 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

uint32_t LL_TIM_OC_InitTypeDef::OCNPolarity

Specifies the complementary output polarity. This parameter can be a value of Output Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetPolarity().

Definition at line 296 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

uint32_t LL_TIM_OC_InitTypeDef::OCNState

Specifies the TIM complementary Output Compare state. This parameter can be a value of Output Configuration State.

This feature can be modified afterwards using unitary functions LL_TIM_CC_EnableChannel() or LL_TIM_CC_DisableChannel().

Definition at line 281 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

uint32_t LL_TIM_OC_InitTypeDef::OCPolarity

Specifies the output polarity. This parameter can be a value of Output Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetPolarity().

Definition at line 291 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

uint32_t LL_TIM_OC_InitTypeDef::OCState

Specifies the TIM Output Compare state. This parameter can be a value of Output Configuration State.

This feature can be modified afterwards using unitary functions LL_TIM_CC_EnableChannel() or LL_TIM_CC_DisableChannel().

Definition at line 276 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

The documentation for this struct was generated from the following file:
  • stm32wbxx_ll_tim.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LL_TIM_IC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_IC_InitTypeDef Struct Reference
TIM Exported Init structure

TIM Input Capture configuration structure definition. More...

#include <stm32wbxx_ll_tim.h>

Data Fields

uint32_t | ICPolarity
uint32_t | ICActiveInput
uint32_t | ICPrescaler
uint32_t | ICFilter

Detailed Description

TIM Input Capture configuration structure definition.

Definition at line 317 of file stm32wbxx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_IC_InitTypeDef::ICActiveInput

Specifies the input. This parameter can be a value of Active Input Selection.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetActiveInput().

Definition at line 325 of file stm32wbxx_ll_tim.h.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), and LL_TIM_IC_StructInit().

uint32_t LL_TIM_IC_InitTypeDef::ICFilter

Specifies the input capture filter. This parameter can be a value of Input Configuration Filter.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetFilter().

Definition at line 335 of file stm32wbxx_ll_tim.h.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), and LL_TIM_IC_StructInit().

uint32_t LL_TIM_IC_InitTypeDef::ICPolarity

Specifies the active edge of the input signal. This parameter can be a value of Input Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPolarity().

Definition at line 320 of file stm32wbxx_ll_tim.h.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), and LL_TIM_IC_StructInit().

uint32_t LL_TIM_IC_InitTypeDef::ICPrescaler

Specifies the Input Capture Prescaler. This parameter can be a value of Input Configuration Prescaler.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPrescaler().

Definition at line 330 of file stm32wbxx_ll_tim.h.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), and LL_TIM_IC_StructInit().

The documentation for this struct was generated from the following file:
  • stm32wbxx_ll_tim.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LL_TIM_ENCODER_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_ENCODER_InitTypeDef Struct Reference
TIM Exported Init structure

TIM Encoder interface configuration structure definition. More...

#include <stm32wbxx_ll_tim.h>

Data Fields

uint32_t | EncoderMode
uint32_t | IC1Polarity
uint32_t | IC1ActiveInput
uint32_t | IC1Prescaler
uint32_t | IC1Filter
uint32_t | IC2Polarity
uint32_t | IC2ActiveInput
uint32_t | IC2Prescaler
uint32_t | IC2Filter

Detailed Description

TIM Encoder interface configuration structure definition.

Definition at line 345 of file stm32wbxx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_ENCODER_InitTypeDef::EncoderMode

Specifies the encoder resolution (x2 or x4). This parameter can be a value of Encoder Mode.

This feature can be modified afterwards using unitary function LL_TIM_SetEncoderMode().

Definition at line 347 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC1ActiveInput

Specifies the TI1 input source This parameter can be a value of Active Input Selection.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetActiveInput().

Definition at line 357 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC1Filter

Specifies the TI1 input filter. This parameter can be a value of Input Configuration Filter.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetFilter().

Definition at line 367 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC1Polarity

Specifies the active edge of TI1 input. This parameter can be a value of Input Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPolarity().

Definition at line 352 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC1Prescaler

Specifies the TI1 input prescaler value. This parameter can be a value of Input Configuration Prescaler.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPrescaler().

Definition at line 362 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC2ActiveInput

Specifies the TI2 input source This parameter can be a value of Active Input Selection.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetActiveInput().

Definition at line 377 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC2Filter

Specifies the TI2 input filter. This parameter can be a value of Input Configuration Filter.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetFilter().

Definition at line 387 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC2Polarity

Specifies the active edge of TI2 input. This parameter can be a value of Input Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPolarity().

Definition at line 372 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC2Prescaler

Specifies the TI2 input prescaler value. This parameter can be a value of Input Configuration Prescaler.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPrescaler().

Definition at line 382 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

The documentation for this struct was generated from the following file:
  • stm32wbxx_ll_tim.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LL_TIM_HALLSENSOR_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_HALLSENSOR_InitTypeDef Struct Reference
TIM Exported Init structure

TIM Hall sensor interface configuration structure definition. More...

#include <stm32wbxx_ll_tim.h>

Data Fields

uint32_t | IC1Polarity
uint32_t | IC1Prescaler
uint32_t | IC1Filter
uint32_t | CommutationDelay

Detailed Description

TIM Hall sensor interface configuration structure definition.

Definition at line 397 of file stm32wbxx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_HALLSENSOR_InitTypeDef::CommutationDelay

Specifies the compare value to be loaded into the Capture Compare Register. A positive pulse (TRGO event) is generated with a programmable delay every time a change occurs on the Hall inputs. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCH2().

Definition at line 417 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init(), and LL_TIM_HALLSENSOR_StructInit().

uint32_t LL_TIM_HALLSENSOR_InitTypeDef::IC1Filter

Specifies the TI1 input filter. This parameter can be a value of Input Configuration Filter.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetFilter().

Definition at line 412 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init(), and LL_TIM_HALLSENSOR_StructInit().

uint32_t LL_TIM_HALLSENSOR_InitTypeDef::IC1Polarity

Specifies the active edge of TI1 input. This parameter can be a value of Input Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPolarity().

Definition at line 400 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init(), and LL_TIM_HALLSENSOR_StructInit().

uint32_t LL_TIM_HALLSENSOR_InitTypeDef::IC1Prescaler

Specifies the TI1 input prescaler value. Prescaler must be set to get a maximum counter period longer than the time interval between 2 consecutive changes on the Hall inputs. This parameter can be a value of Input Configuration Prescaler.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPrescaler().

Definition at line 405 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init(), and LL_TIM_HALLSENSOR_StructInit().

The documentation for this struct was generated from the following file:
  • stm32wbxx_ll_tim.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LL_TIM_BDTR_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_BDTR_InitTypeDef Struct Reference
TIM Exported Init structure

BDTR (Break and Dead Time) structure definition. More...

#include <stm32wbxx_ll_tim.h>

Data Fields

uint32_t | OSSRState
uint32_t | OSSIState
uint32_t | LockLevel
uint8_t | DeadTime
uint16_t | BreakState
uint32_t | BreakPolarity
uint32_t | BreakFilter
uint32_t | Break2State
uint32_t | Break2Polarity
uint32_t | Break2Filter
uint32_t | AutomaticOutput

Detailed Description

BDTR (Break and Dead Time) structure definition.

Definition at line 428 of file stm32wbxx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_BDTR_InitTypeDef::AutomaticOutput

Specifies whether the TIM Automatic Output feature is enabled or not. This parameter can be a value of Automatic output enable

This feature can be modified afterwards using unitary functions LL_TIM_EnableAutomaticOutput() or LL_TIM_DisableAutomaticOutput()

Note:
This bit-field can not be modified as long as LOCK level 1 has been programmed.

Definition at line 500 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::Break2Filter

Specifies the TIM Break2 Filter. This parameter can be a value of BREAK2 FILTER

This feature can be modified afterwards using unitary function LL_TIM_ConfigBRK2()

Note:
This bit-field can not be modified as long as LOCK level 1 has been programmed.

Definition at line 493 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::Break2Polarity

Specifies the TIM Break2 Input pin polarity. This parameter can be a value of BREAK2 POLARITY

This feature can be modified afterwards using unitary function LL_TIM_ConfigBRK2()

Note:
This bit-field can not be modified as long as LOCK level 1 has been programmed.

Definition at line 486 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::Break2State

Specifies whether the TIM Break2 input is enabled or not. This parameter can be a value of Break2 Enable

This feature can be modified afterwards using unitary functions LL_TIM_EnableBRK2() or LL_TIM_DisableBRK2()

Note:
This bit-field can not be modified as long as LOCK level 1 has been programmed.

Definition at line 479 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::BreakFilter

Specifies the TIM Break Filter. This parameter can be a value of break filter

This feature can be modified afterwards using unitary function LL_TIM_ConfigBRK()

Note:
This bit-field can not be modified as long as LOCK level 1 has been programmed.

Definition at line 472 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::BreakPolarity

Specifies the TIM Break Input pin polarity. This parameter can be a value of break polarity

This feature can be modified afterwards using unitary function LL_TIM_ConfigBRK()

Note:
This bit-field can not be modified as long as LOCK level 1 has been programmed.

Definition at line 465 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint16_t LL_TIM_BDTR_InitTypeDef::BreakState

Specifies whether the TIM Break input is enabled or not. This parameter can be a value of Break Enable

This feature can be modified afterwards using unitary functions LL_TIM_EnableBRK() or LL_TIM_DisableBRK()

Note:
This bit-field can not be modified as long as LOCK level 1 has been programmed.

Definition at line 458 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint8_t LL_TIM_BDTR_InitTypeDef::DeadTime

Specifies the delay time between the switching-off and the switching-on of the outputs. This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetDeadTime()

Note:
This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed.

Definition at line 450 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::LockLevel

Specifies the LOCK level parameters. This parameter can be a value of Lock Level

Note:
The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.

Definition at line 444 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::OSSIState

Specifies the Off-State used in Idle state. This parameter can be a value of OSSI

This feature can be modified afterwards using unitary function LL_TIM_SetOffStates()

Note:
This bit-field cannot be modified as long as LOCK level 2 has been programmed.

Definition at line 437 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::OSSRState

Specifies the Off-State selection used in Run mode. This parameter can be a value of OSSR

This feature can be modified afterwards using unitary function LL_TIM_SetOffStates()

Note:
This bit-field cannot be modified as long as LOCK level 2 has been programmed.

Definition at line 430 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

The documentation for this struct was generated from the following file:
  • stm32wbxx_ll_tim.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
TIM Exported Constants

Flags defines which can be used with LL_TIM_ReadReg function. More...

Defines

#define | LL_TIM_SR_UIF TIM_SR_UIF
#define | LL_TIM_SR_CC1IF TIM_SR_CC1IF
#define | LL_TIM_SR_CC2IF TIM_SR_CC2IF
#define | LL_TIM_SR_CC3IF TIM_SR_CC3IF
#define | LL_TIM_SR_CC4IF TIM_SR_CC4IF
#define | LL_TIM_SR_CC5IF TIM_SR_CC5IF
#define | LL_TIM_SR_CC6IF TIM_SR_CC6IF
#define | LL_TIM_SR_COMIF TIM_SR_COMIF
#define | LL_TIM_SR_TIF TIM_SR_TIF
#define | LL_TIM_SR_BIF TIM_SR_BIF
#define | LL_TIM_SR_B2IF TIM_SR_B2IF
#define | LL_TIM_SR_CC1OF TIM_SR_CC1OF
#define | LL_TIM_SR_CC2OF TIM_SR_CC2OF
#define | LL_TIM_SR_CC3OF TIM_SR_CC3OF
#define | LL_TIM_SR_CC4OF TIM_SR_CC4OF
#define | LL_TIM_SR_SBIF TIM_SR_SBIF

Detailed Description

Flags defines which can be used with LL_TIM_ReadReg function.

Define Documentation

#define LL_TIM_SR_B2IF TIM_SR_B2IF

Second break interrupt flag

Definition at line 532 of file stm32wbxx_ll_tim.h.

#define LL_TIM_SR_BIF TIM_SR_BIF

Break interrupt flag

Definition at line 531 of file stm32wbxx_ll_tim.h.

#define LL_TIM_SR_CC1IF TIM_SR_CC1IF

Capture/compare 1 interrupt flag

Definition at line 523 of file stm32wbxx_ll_tim.h.

#define LL_TIM_SR_CC1OF TIM_SR_CC1OF

Capture/Compare 1 overcapture flag

Definition at line 533 of file stm32wbxx_ll_tim.h.

#define LL_TIM_SR_CC2IF TIM_SR_CC2IF

Capture/compare 2 interrupt flag

Definition at line 524 of file stm32wbxx_ll_tim.h.

#define LL_TIM_SR_CC2OF TIM_SR_CC2OF

Capture/Compare 2 overcapture flag

Definition at line 534 of file stm32wbxx_ll_tim.h.

#define LL_TIM_SR_CC3IF TIM_SR_CC3IF

Capture/compare 3 interrupt flag

Definition at line 525 of file stm32wbxx_ll_tim.h.

#define LL_TIM_SR_CC3OF TIM_SR_CC3OF

Capture/Compare 3 overcapture flag

Definition at line 535 of file stm32wbxx_ll_tim.h.

#define LL_TIM_SR_CC4IF TIM_SR_CC4IF

Capture/compare 4 interrupt flag

Definition at line 526 of file stm32wbxx_ll_tim.h.

#define LL_TIM_SR_CC4OF TIM_SR_CC4OF

Capture/Compare 4 overcapture flag

Definition at line 536 of file stm32wbxx_ll_tim.h.

#define LL_TIM_SR_CC5IF TIM_SR_CC5IF

Capture/compare 5 interrupt flag

Definition at line 527 of file stm32wbxx_ll_tim.h.

#define LL_TIM_SR_CC6IF TIM_SR_CC6IF

Capture/compare 6 interrupt flag

Definition at line 528 of file stm32wbxx_ll_tim.h.

#define LL_TIM_SR_COMIF TIM_SR_COMIF

COM interrupt flag

Definition at line 529 of file stm32wbxx_ll_tim.h.

#define LL_TIM_SR_SBIF TIM_SR_SBIF

System Break interrupt flag

Definition at line 537 of file stm32wbxx_ll_tim.h.

#define LL_TIM_SR_TIF TIM_SR_TIF

Trigger interrupt flag

Definition at line 530 of file stm32wbxx_ll_tim.h.

#define LL_TIM_SR_UIF TIM_SR_UIF

Update interrupt flag

Definition at line 522 of file stm32wbxx_ll_tim.h.

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STM32WB55xx HAL User Manual: Break Enable

Defines
Break Enable
TIM Exported Constants

Defines

#define | LL_TIM_BREAK_DISABLE 0x00000000U
#define | LL_TIM_BREAK_ENABLE TIM_BDTR_BKE

Define Documentation

#define LL_TIM_BREAK_DISABLE 0x00000000U

Break function disabled

Definition at line 546 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE

Break function enabled

Definition at line 547 of file stm32wbxx_ll_tim.h.

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STM32WB55xx HAL User Manual: Break2 Enable

Defines
Break2 Enable
TIM Exported Constants

Defines

#define | LL_TIM_BREAK2_DISABLE 0x00000000U
#define | LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E

Define Documentation

#define LL_TIM_BREAK2_DISABLE 0x00000000U

Break2 function disabled

Definition at line 555 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

#define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E

Break2 function enabled

Definition at line 556 of file stm32wbxx_ll_tim.h.

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STM32WB55xx HAL User Manual: Automatic output enable

Defines
Automatic output enable
TIM Exported Constants

Defines

#define | LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U
#define | LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE

Define Documentation

#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U

MOE can be set only by software

Definition at line 564 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE

MOE can be set by software or automatically at the next update event

Definition at line 565 of file stm32wbxx_ll_tim.h.

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STM32WB55xx HAL User Manual: IT Defines

Defines
IT Defines
TIM Exported Constants

IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. More...

Defines

#define | LL_TIM_DIER_UIE TIM_DIER_UIE
#define | LL_TIM_DIER_CC1IE TIM_DIER_CC1IE
#define | LL_TIM_DIER_CC2IE TIM_DIER_CC2IE
#define | LL_TIM_DIER_CC3IE TIM_DIER_CC3IE
#define | LL_TIM_DIER_CC4IE TIM_DIER_CC4IE
#define | LL_TIM_DIER_COMIE TIM_DIER_COMIE
#define | LL_TIM_DIER_TIE TIM_DIER_TIE
#define | LL_TIM_DIER_BIE TIM_DIER_BIE

Detailed Description

IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.

Define Documentation

#define LL_TIM_DIER_BIE TIM_DIER_BIE

Break interrupt enable

Definition at line 582 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE

Capture/compare 1 interrupt enable

Definition at line 576 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE

Capture/compare 2 interrupt enable

Definition at line 577 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE

Capture/compare 3 interrupt enable

Definition at line 578 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE

Capture/compare 4 interrupt enable

Definition at line 579 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DIER_COMIE TIM_DIER_COMIE

COM interrupt enable

Definition at line 580 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DIER_TIE TIM_DIER_TIE

Trigger interrupt enable

Definition at line 581 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DIER_UIE TIM_DIER_UIE

Update interrupt enable

Definition at line 575 of file stm32wbxx_ll_tim.h.

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STM32WB55xx HAL User Manual: Update Source

Defines
Update Source
TIM Exported Constants

Defines

#define | LL_TIM_UPDATESOURCE_REGULAR 0x00000000U
#define | LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS

Define Documentation

#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS

Only counter overflow/underflow generates an update request

Definition at line 591 of file stm32wbxx_ll_tim.h.

#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U

Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request

Definition at line 590 of file stm32wbxx_ll_tim.h.

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STM32WB55xx HAL User Manual: One Pulse Mode

Defines
One Pulse Mode
TIM Exported Constants

Defines

#define | LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM
#define | LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U

Define Documentation

#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U

Counter stops counting at the next update event

Definition at line 600 of file stm32wbxx_ll_tim.h.

#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM

Counter is not stopped at update event

Definition at line 599 of file stm32wbxx_ll_tim.h.

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STM32WB55xx HAL User Manual: Counter Mode

Defines
Counter Mode
TIM Exported Constants

Defines

#define | LL_TIM_COUNTERMODE_UP 0x00000000U
#define | LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define | LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0
#define | LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1
#define | LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS

Define Documentation

#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1

The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up

Definition at line 611 of file stm32wbxx_ll_tim.h.

#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0

The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down.

Definition at line 610 of file stm32wbxx_ll_tim.h.

#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS

The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down.

Definition at line 612 of file stm32wbxx_ll_tim.h.

#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR

Counter used as downcounter

Definition at line 609 of file stm32wbxx_ll_tim.h.

#define LL_TIM_COUNTERMODE_UP 0x00000000U

Counter used as upcounter

Definition at line 608 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_StructInit().

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STM32WB55xx HAL User Manual: Clock Division

Defines
Clock Division
TIM Exported Constants

Defines

#define | LL_TIM_CLOCKDIVISION_DIV1 0x00000000U
#define | LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0
#define | LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1

Define Documentation

#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U

tDTS=tCK_INT

Definition at line 620 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_StructInit().

#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0

tDTS=2*tCK_INT

Definition at line 621 of file stm32wbxx_ll_tim.h.

#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1

tDTS=4*tCK_INT

Definition at line 622 of file stm32wbxx_ll_tim.h.

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STM32WB55xx HAL User Manual: Counter Direction

Defines
Counter Direction
TIM Exported Constants

Defines

#define | LL_TIM_COUNTERDIRECTION_UP 0x00000000U
#define | LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR

Define Documentation

#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR

Timer counter counts down

Definition at line 631 of file stm32wbxx_ll_tim.h.

#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U

Timer counter counts up

Definition at line 630 of file stm32wbxx_ll_tim.h.

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STM32WB55xx HAL User Manual: Capture Compare Update Source

Defines
Capture Compare Update Source
TIM Exported Constants

Defines

#define | LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U
#define | LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS

Define Documentation

#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS

Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI)

Definition at line 640 of file stm32wbxx_ll_tim.h.

#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U

Capture/compare control bits are updated by setting the COMG bit only

Definition at line 639 of file stm32wbxx_ll_tim.h.

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STM32WB55xx HAL User Manual: Capture Compare DMA Request

Defines
Capture Compare DMA Request
TIM Exported Constants

Defines

#define | LL_TIM_CCDMAREQUEST_CC 0x00000000U
#define | LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS

Define Documentation

#define LL_TIM_CCDMAREQUEST_CC 0x00000000U

CCx DMA request sent when CCx event occurs

Definition at line 648 of file stm32wbxx_ll_tim.h.

#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS

CCx DMA requests sent when update event occurs

Definition at line 649 of file stm32wbxx_ll_tim.h.

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STM32WB55xx HAL User Manual: Lock Level

Defines
Lock Level
TIM Exported Constants

Defines

#define | LL_TIM_LOCKLEVEL_OFF 0x00000000U
#define | LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0
#define | LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1
#define | LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK

Define Documentation

#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0

LOCK Level 1

Definition at line 658 of file stm32wbxx_ll_tim.h.

#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1

LOCK Level 2

Definition at line 659 of file stm32wbxx_ll_tim.h.

#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK

LOCK Level 3

Definition at line 660 of file stm32wbxx_ll_tim.h.

#define LL_TIM_LOCKLEVEL_OFF 0x00000000U

LOCK OFF - No bit is write protected

Definition at line 657 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

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STM32WB55xx HAL User Manual: Channel

Defines
Channel
TIM Exported Constants

Defines

#define | LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E
#define | LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE
#define | LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E
#define | LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE
#define | LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E
#define | LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE
#define | LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E
#define | LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E
#define | LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E

Define Documentation

#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E

Timer input/output channel 1

Definition at line 668 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_IC_Init(), and LL_TIM_OC_Init().

#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE

Timer complementary output channel 1

Definition at line 669 of file stm32wbxx_ll_tim.h.

#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E

Timer input/output channel 2

Definition at line 670 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_IC_Init(), and LL_TIM_OC_Init().

#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE

Timer complementary output channel 2

Definition at line 671 of file stm32wbxx_ll_tim.h.

#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E

Timer input/output channel 3

Definition at line 672 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_IC_Init(), and LL_TIM_OC_Init().

#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE

Timer complementary output channel 3

Definition at line 673 of file stm32wbxx_ll_tim.h.

#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E

Timer input/output channel 4

Definition at line 674 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_IC_Init(), and LL_TIM_OC_Init().

#define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E

Timer output channel 5

Definition at line 675 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_OC_Init().

#define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E

Timer output channel 6

Definition at line 676 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_OC_Init().

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STM32WB55xx HAL User Manual: Output Configuration State

Defines
Output Configuration State
TIM Exported Constants

Defines

#define | LL_TIM_OCSTATE_DISABLE 0x00000000U
#define | LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E

Define Documentation

#define LL_TIM_OCSTATE_DISABLE 0x00000000U

OCx is not active

Definition at line 685 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit().

#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E

OCx signal is output on the corresponding output pin

Definition at line 686 of file stm32wbxx_ll_tim.h.

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STM32WB55xx HAL User Manual: Output Configuration Mode

Defines
Output Configuration Mode
TIM Exported Constants

Defines

#define | LL_TIM_OCMODE_FROZEN 0x00000000U
#define | LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0
#define | LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1
#define | LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2
#define | LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
#define | LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3
#define | LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
#define | LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
#define | LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
#define | LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)

Define Documentation

#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0

OCyREF is forced high on compare match

Definition at line 696 of file stm32wbxx_ll_tim.h.

#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)

Asymmetric PWM mode 1

Definition at line 707 of file stm32wbxx_ll_tim.h.

#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)

Asymmetric PWM mode 2

Definition at line 708 of file stm32wbxx_ll_tim.h.

#define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)

Combined PWM mode 1

Definition at line 705 of file stm32wbxx_ll_tim.h.

#define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)

Combined PWM mode 2

Definition at line 706 of file stm32wbxx_ll_tim.h.

#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)

OCyREF is forced high

Definition at line 700 of file stm32wbxx_ll_tim.h.

#define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2

OCyREF is forced low

Definition at line 699 of file stm32wbxx_ll_tim.h.

#define LL_TIM_OCMODE_FROZEN 0x00000000U

The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level

Definition at line 695 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit().

#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1

OCyREF is forced low on compare match

Definition at line 697 of file stm32wbxx_ll_tim.h.

#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)

In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.

Definition at line 701 of file stm32wbxx_ll_tim.h.

#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)

In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive

Definition at line 702 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init().

#define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3

Retrigerrable OPM mode 1

Definition at line 703 of file stm32wbxx_ll_tim.h.

#define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)

Retrigerrable OPM mode 2

Definition at line 704 of file stm32wbxx_ll_tim.h.

#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)

OCyREF toggles on compare match

Definition at line 698 of file stm32wbxx_ll_tim.h.

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STM32WB55xx HAL User Manual: Output Configuration Polarity

Defines
Output Configuration Polarity
TIM Exported Constants

Defines

#define | LL_TIM_OCPOLARITY_HIGH 0x00000000U
#define | LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P

Define Documentation

#define LL_TIM_OCPOLARITY_HIGH 0x00000000U

OCxactive high

Definition at line 716 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit().

#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P

OCxactive low

Definition at line 717 of file stm32wbxx_ll_tim.h.

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STM32WB55xx HAL User Manual: Output Configuration Idle State

Defines
Output Configuration Idle State
TIM Exported Constants

Defines

#define | LL_TIM_OCIDLESTATE_LOW 0x00000000U
#define | LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1

Define Documentation

#define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1

OCx=1 (after a dead-time if OC is implemented) when MOE=0

Definition at line 726 of file stm32wbxx_ll_tim.h.

#define LL_TIM_OCIDLESTATE_LOW 0x00000000U

OCx=0 (after a dead-time if OC is implemented) when MOE=0

Definition at line 725 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit().

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STM32WB55xx HAL User Manual: GROUPCH5

Defines
GROUPCH5
TIM Exported Constants

Defines

#define | LL_TIM_GROUPCH5_NONE 0x00000000U
#define | LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1
#define | LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2
#define | LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3

Define Documentation

#define LL_TIM_GROUPCH5_NONE 0x00000000U

No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC

Definition at line 734 of file stm32wbxx_ll_tim.h.

#define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1

OC1REFC is the logical AND of OC1REFC and OC5REF

Definition at line 735 of file stm32wbxx_ll_tim.h.

#define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2

OC2REFC is the logical AND of OC2REFC and OC5REF

Definition at line 736 of file stm32wbxx_ll_tim.h.

#define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3

OC3REFC is the logical AND of OC3REFC and OC5REF

Definition at line 737 of file stm32wbxx_ll_tim.h.

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STM32WB55xx HAL User Manual: Active Input Selection

Defines
Active Input Selection
TIM Exported Constants

Defines

#define | LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U)
#define | LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U)
#define | LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U)

Define Documentation

#define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U)

ICx is mapped on TIx

Definition at line 745 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_ENCODER_StructInit(), and LL_TIM_IC_StructInit().

#define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U)

ICx is mapped on TIy

Definition at line 746 of file stm32wbxx_ll_tim.h.

#define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U)

ICx is mapped on TRC

Definition at line 747 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init().

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STM32WB55xx HAL User Manual: Input Configuration Prescaler

Defines
Input Configuration Prescaler
TIM Exported Constants

Defines

#define | LL_TIM_ICPSC_DIV1 0x00000000U
#define | LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U)
#define | LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U)
#define | LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U)

Define Documentation

#define LL_TIM_ICPSC_DIV1 0x00000000U

No prescaler, capture is done each time an edge is detected on the capture input

Definition at line 755 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_ENCODER_StructInit(), LL_TIM_HALLSENSOR_StructInit(), and LL_TIM_IC_StructInit().

#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U)

Capture is done once every 2 events

Definition at line 756 of file stm32wbxx_ll_tim.h.

#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U)

Capture is done once every 4 events

Definition at line 757 of file stm32wbxx_ll_tim.h.

#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U)

Capture is done once every 8 events

Definition at line 758 of file stm32wbxx_ll_tim.h.

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STM32WB55xx HAL User Manual: Input Configuration Filter

Defines
Input Configuration Filter
TIM Exported Constants

Defines

#define | LL_TIM_IC_FILTER_FDIV1 0x00000000U
#define | LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U)
#define | LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U)
#define | LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U)
#define | LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U)
#define | LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U)

Define Documentation

#define LL_TIM_IC_FILTER_FDIV1 0x00000000U

No filter, sampling is done at fDTS

Definition at line 766 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_ENCODER_StructInit(), LL_TIM_HALLSENSOR_StructInit(), and LL_TIM_IC_StructInit().

#define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)

fSAMPLING=fDTS/16, N=5

Definition at line 776 of file stm32wbxx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fDTS/16, N=6

Definition at line 777 of file stm32wbxx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)

fSAMPLING=fDTS/16, N=8

Definition at line 778 of file stm32wbxx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U)

fSAMPLING=fCK_INT, N=2

Definition at line 767 of file stm32wbxx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U)

fSAMPLING=fCK_INT, N=4

Definition at line 768 of file stm32wbxx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fCK_INT, N=8

Definition at line 769 of file stm32wbxx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U)

fSAMPLING=fDTS/2, N=6

Definition at line 770 of file stm32wbxx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fDTS/2, N=8

Definition at line 771 of file stm32wbxx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fDTS/32, N=5

Definition at line 779 of file stm32wbxx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)

fSAMPLING=fDTS/32, N=6

Definition at line 780 of file stm32wbxx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U)

fSAMPLING=fDTS/32, N=8

Definition at line 781 of file stm32wbxx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)

fSAMPLING=fDTS/4, N=6

Definition at line 772 of file stm32wbxx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fDTS/4, N=8

Definition at line 773 of file stm32wbxx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U)

fSAMPLING=fDTS/8, N=6

Definition at line 774 of file stm32wbxx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fDTS/8, N=8

Definition at line 775 of file stm32wbxx_ll_tim.h.

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STM32WB55xx HAL User Manual: Input Configuration Polarity

Defines
Input Configuration Polarity
TIM Exported Constants

Defines

#define | LL_TIM_IC_POLARITY_RISING 0x00000000U
#define | LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P
#define | LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)

Define Documentation

#define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)

The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted

Definition at line 791 of file stm32wbxx_ll_tim.h.

#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P

The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted

Definition at line 790 of file stm32wbxx_ll_tim.h.

#define LL_TIM_IC_POLARITY_RISING 0x00000000U

The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted

Definition at line 789 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_ENCODER_StructInit(), LL_TIM_HALLSENSOR_StructInit(), and LL_TIM_IC_StructInit().

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STM32WB55xx HAL User Manual: Clock Source

Defines
Clock Source
TIM Exported Constants

Defines

#define | LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U
#define | LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE

Define Documentation

#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Counter counts at each rising or falling edge on a selected input

Definition at line 800 of file stm32wbxx_ll_tim.h.

#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE

Counter counts at each rising or falling edge on the external trigger input ETR

Definition at line 801 of file stm32wbxx_ll_tim.h.

#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U

The timer is clocked by the internal clock provided from the RCC

Definition at line 799 of file stm32wbxx_ll_tim.h.

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STM32WB55xx HAL User Manual: Encoder Mode

Defines
Encoder Mode
TIM Exported Constants

Defines

#define | LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0
#define | LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1
#define | LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Define Documentation

#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0

Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level

Definition at line 809 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_ENCODER_StructInit().

#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1

Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level

Definition at line 810 of file stm32wbxx_ll_tim.h.

#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input

Definition at line 811 of file stm32wbxx_ll_tim.h.

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STM32WB55xx HAL User Manual: Trigger Output

Defines
Trigger Output
TIM Exported Constants

Defines

#define | LL_TIM_TRGO_RESET 0x00000000U
#define | LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0
#define | LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1
#define | LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
#define | LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2
#define | LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)
#define | LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)
#define | LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)

Define Documentation

#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)

CC1 capture or a compare match is used as trigger output

Definition at line 822 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0

Counter Enable signal (CNT_EN) is used as trigger output

Definition at line 820 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2

OC1REF signal is used as trigger output

Definition at line 823 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)

OC2REF signal is used as trigger output

Definition at line 824 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init().

#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)

OC3REF signal is used as trigger output

Definition at line 825 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)

OC4REF signal is used as trigger output

Definition at line 826 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TRGO_RESET 0x00000000U

UG bit from the TIMx_EGR register is used as trigger output

Definition at line 819 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1

Update event is used as trigger output

Definition at line 821 of file stm32wbxx_ll_tim.h.

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STM32WB55xx HAL User Manual: Trigger Output 2

Defines
Trigger Output 2
TIM Exported Constants

Defines

#define | LL_TIM_TRGO2_RESET 0x00000000U
#define | LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0
#define | LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1
#define | LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2
#define | LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)
#define | LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3
#define | LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)
#define | LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)
#define | LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)
#define | LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

Define Documentation

#define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

CC1 capture or a compare match is used as trigger output 2

Definition at line 837 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0

Counter Enable signal (CNT_EN) is used as trigger output 2

Definition at line 835 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2

OC1REF signal is used as trigger output 2

Definition at line 838 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)

OC2REF signal is used as trigger output 2

Definition at line 839 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)

OC3REF signal is used as trigger output 2

Definition at line 840 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

OC4REF signal is used as trigger output 2

Definition at line 841 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)

OC4REF rising or OC6REF falling edges are used as trigger output 2

Definition at line 847 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)

OC4REF or OC6REF rising edges are used as trigger output 2

Definition at line 846 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)

OC4REF rising or falling edges are used as trigger output 2

Definition at line 844 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3

OC5REF signal is used as trigger output 2

Definition at line 842 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

OC5REF rising or OC6REF falling edges are used as trigger output 2

Definition at line 849 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)

OC5REF or OC6REF rising edges are used as trigger output 2

Definition at line 848 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)

OC6REF signal is used as trigger output 2

Definition at line 843 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

OC6REF rising or falling edges are used as trigger output 2

Definition at line 845 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TRGO2_RESET 0x00000000U

UG bit from the TIMx_EGR register is used as trigger output 2

Definition at line 834 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1

Update event is used as trigger output 2

Definition at line 836 of file stm32wbxx_ll_tim.h.

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STM32WB55xx HAL User Manual: Slave Mode

Defines
Slave Mode
TIM Exported Constants

Defines

#define | LL_TIM_SLAVEMODE_DISABLED 0x00000000U
#define | LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2
#define | LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)
#define | LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)
#define | LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3

Define Documentation

#define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3

Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter

Definition at line 861 of file stm32wbxx_ll_tim.h.

#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U

Slave mode disabled

Definition at line 857 of file stm32wbxx_ll_tim.h.

#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)

Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high

Definition at line 859 of file stm32wbxx_ll_tim.h.

#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2

Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter

Definition at line 858 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init().

#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)

Trigger Mode - The counter starts at a rising edge of the trigger TRGI

Definition at line 860 of file stm32wbxx_ll_tim.h.

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STM32WB55xx HAL User Manual: Trigger Selection

Defines
Trigger Selection
TIM Exported Constants

Defines

#define | LL_TIM_TS_ITR0 0x00000000U
#define | LL_TIM_TS_ITR1 TIM_SMCR_TS_0
#define | LL_TIM_TS_ITR2 TIM_SMCR_TS_1
#define | LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
#define | LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2
#define | LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)
#define | LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)
#define | LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)

Define Documentation

#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)

Filtered external Trigger (ETRF) is used as trigger input

Definition at line 876 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TS_ITR0 0x00000000U

Internal Trigger 0 (ITR0) is used as trigger input

Definition at line 869 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0

Internal Trigger 1 (ITR1) is used as trigger input

Definition at line 870 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1

Internal Trigger 2 (ITR2) is used as trigger input

Definition at line 871 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)

Internal Trigger 3 (ITR3) is used as trigger input

Definition at line 872 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2

TI1 Edge Detector (TI1F_ED) is used as trigger input

Definition at line 873 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init().

#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)

Filtered Timer Input 1 (TI1FP1) is used as trigger input

Definition at line 874 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)

Filtered Timer Input 2 (TI12P2) is used as trigger input

Definition at line 875 of file stm32wbxx_ll_tim.h.

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: External Trigger Polarity

Defines
External Trigger Polarity
TIM Exported Constants

Defines

#define | LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U
#define | LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP

Define Documentation

#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP

ETR is inverted, active at low level or falling edge

Definition at line 885 of file stm32wbxx_ll_tim.h.

#define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U

ETR is non-inverted, active at high level or rising edge

Definition at line 884 of file stm32wbxx_ll_tim.h.

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: External Trigger Prescaler

Defines
External Trigger Prescaler
TIM Exported Constants

Defines

#define | LL_TIM_ETR_PRESCALER_DIV1 0x00000000U
#define | LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0
#define | LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1
#define | LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS

Define Documentation

#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U

ETR prescaler OFF

Definition at line 893 of file stm32wbxx_ll_tim.h.

#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0

ETR frequency is divided by 2

Definition at line 894 of file stm32wbxx_ll_tim.h.

#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1

ETR frequency is divided by 4

Definition at line 895 of file stm32wbxx_ll_tim.h.

#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS

ETR frequency is divided by 8

Definition at line 896 of file stm32wbxx_ll_tim.h.

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STM32WB55xx HAL User Manual: External Trigger Filter

Defines
External Trigger Filter
TIM Exported Constants

Defines

#define | LL_TIM_ETR_FILTER_FDIV1 0x00000000U
#define | LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0
#define | LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1
#define | LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2
#define | LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)
#define | LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3
#define | LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)
#define | LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)
#define | LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)
#define | LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF

Define Documentation

#define LL_TIM_ETR_FILTER_FDIV1 0x00000000U

No filter, sampling is done at fDTS

Definition at line 904 of file stm32wbxx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)

fSAMPLING=fDTS/16, N=6

Definition at line 914 of file stm32wbxx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)

fSAMPLING=fDTS/16, N=8

Definition at line 915 of file stm32wbxx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)

fSAMPLING=fDTS/16, N=5

Definition at line 916 of file stm32wbxx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0

fSAMPLING=fCK_INT, N=2

Definition at line 905 of file stm32wbxx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1

fSAMPLING=fCK_INT, N=4

Definition at line 906 of file stm32wbxx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)

fSAMPLING=fCK_INT, N=8

Definition at line 907 of file stm32wbxx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2

fSAMPLING=fDTS/2, N=6

Definition at line 908 of file stm32wbxx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)

fSAMPLING=fDTS/2, N=8

Definition at line 909 of file stm32wbxx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)

fSAMPLING=fDTS/32, N=5

Definition at line 917 of file stm32wbxx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)

fSAMPLING=fDTS/32, N=6

Definition at line 918 of file stm32wbxx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF

fSAMPLING=fDTS/32, N=8

Definition at line 919 of file stm32wbxx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)

fSAMPLING=fDTS/4, N=6

Definition at line 910 of file stm32wbxx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)

fSAMPLING=fDTS/4, N=8

Definition at line 911 of file stm32wbxx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3

fSAMPLING=fDTS/8, N=8

Definition at line 912 of file stm32wbxx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)

fSAMPLING=fDTS/16, N=5

Definition at line 913 of file stm32wbxx_ll_tim.h.

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STM32WB55xx HAL User Manual: External Trigger Source

Defines
External Trigger Source
TIM Exported Constants

Defines

#define | LL_TIM_ETRSOURCE_LEGACY 0x00000000U
#define | LL_TIM_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0
#define | LL_TIM_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1
#define | LL_TIM_ETRSOURCE_GPIO LL_TIM_ETRSOURCE_LEGACY
#define | LL_TIM_ETRSOURCE_ADC1_AWD1 LL_TIM_ETRSOURCE_LEGACY
#define | LL_TIM_ETRSOURCE_ADC1_AWD2 LL_TIM_ETRSOURCE_LEGACY
#define | LL_TIM_ETRSOURCE_ADC1_AWD3 LL_TIM_ETRSOURCE_LEGACY

Define Documentation

#define LL_TIM_ETRSOURCE_ADC1_AWD1 LL_TIM_ETRSOURCE_LEGACY

ETR input is connected to ADC1 analog watchdog 1 through TIMx ETR remapping capability

Definition at line 933 of file stm32wbxx_ll_tim.h.

#define LL_TIM_ETRSOURCE_ADC1_AWD2 LL_TIM_ETRSOURCE_LEGACY

ETR input is connected to ADC1 analog watchdog 2 through TIMx ETR remapping capability

Definition at line 934 of file stm32wbxx_ll_tim.h.

#define LL_TIM_ETRSOURCE_ADC1_AWD3 LL_TIM_ETRSOURCE_LEGACY

ETR input is connected to ADC1 analog watchdog 3 through TIMx ETR remapping capability

Definition at line 935 of file stm32wbxx_ll_tim.h.

#define LL_TIM_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0

ETR input is connected to COMP1_OUT

Definition at line 929 of file stm32wbxx_ll_tim.h.

#define LL_TIM_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1

ETR input is connected to COMP2_OUT

Definition at line 930 of file stm32wbxx_ll_tim.h.

#define LL_TIM_ETRSOURCE_GPIO LL_TIM_ETRSOURCE_LEGACY

ETR input is connected to GPIO through TIMx ETR remapping capability

Definition at line 932 of file stm32wbxx_ll_tim.h.

#define LL_TIM_ETRSOURCE_LEGACY 0x00000000U

ETR legacy mode

Definition at line 927 of file stm32wbxx_ll_tim.h.

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STM32WB55xx HAL User Manual: break polarity

Defines
break polarity
TIM Exported Constants

Defines

#define | LL_TIM_BREAK_POLARITY_LOW 0x00000000U
#define | LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP

Define Documentation

#define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP

Break input BRK is active high

Definition at line 944 of file stm32wbxx_ll_tim.h.

#define LL_TIM_BREAK_POLARITY_LOW 0x00000000U

Break input BRK is active low

Definition at line 943 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

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STM32WB55xx HAL User Manual: break filter

Defines
break filter
TIM Exported Constants

Defines

#define | LL_TIM_BREAK_FILTER_FDIV1 0x00000000U
#define | LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U
#define | LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U
#define | LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U
#define | LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U
#define | LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U
#define | LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U
#define | LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U
#define | LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U
#define | LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U
#define | LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U
#define | LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U
#define | LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U
#define | LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U
#define | LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U
#define | LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U

Define Documentation

#define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U

No filter, BRK acts asynchronously

Definition at line 952 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

#define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U

fSAMPLING=fDTS/16, N=5

Definition at line 962 of file stm32wbxx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U

fSAMPLING=fDTS/16, N=6

Definition at line 963 of file stm32wbxx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U

fSAMPLING=fDTS/16, N=8

Definition at line 964 of file stm32wbxx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U

fSAMPLING=fCK_INT, N=2

Definition at line 953 of file stm32wbxx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U

fSAMPLING=fCK_INT, N=4

Definition at line 954 of file stm32wbxx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U

fSAMPLING=fCK_INT, N=8

Definition at line 955 of file stm32wbxx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U

fSAMPLING=fDTS/2, N=6

Definition at line 956 of file stm32wbxx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U

fSAMPLING=fDTS/2, N=8

Definition at line 957 of file stm32wbxx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U

fSAMPLING=fDTS/32, N=5

Definition at line 965 of file stm32wbxx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U

fSAMPLING=fDTS/32, N=6

Definition at line 966 of file stm32wbxx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U

fSAMPLING=fDTS/32, N=8

Definition at line 967 of file stm32wbxx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U

fSAMPLING=fDTS/4, N=6

Definition at line 958 of file stm32wbxx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U

fSAMPLING=fDTS/4, N=8

Definition at line 959 of file stm32wbxx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U

fSAMPLING=fDTS/8, N=6

Definition at line 960 of file stm32wbxx_ll_tim.h.

#define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U

fSAMPLING=fDTS/8, N=8

Definition at line 961 of file stm32wbxx_ll_tim.h.

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STM32WB55xx HAL User Manual: BREAK2 POLARITY

Defines
BREAK2 POLARITY
TIM Exported Constants

Defines

#define | LL_TIM_BREAK2_POLARITY_LOW 0x00000000U
#define | LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P

Define Documentation

#define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P

Break input BRK2 is active high

Definition at line 976 of file stm32wbxx_ll_tim.h.

#define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U

Break input BRK2 is active low

Definition at line 975 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

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STM32WB55xx HAL User Manual: BREAK2 FILTER

Defines
BREAK2 FILTER
TIM Exported Constants

Defines

#define | LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U
#define | LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U
#define | LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U
#define | LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U
#define | LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U
#define | LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U
#define | LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U
#define | LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U
#define | LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U
#define | LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U
#define | LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U
#define | LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U
#define | LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U
#define | LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U
#define | LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U
#define | LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U

Define Documentation

#define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U

No filter, BRK acts asynchronously

Definition at line 984 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

#define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U

fSAMPLING=fDTS/16, N=5

Definition at line 994 of file stm32wbxx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U

fSAMPLING=fDTS/16, N=6

Definition at line 995 of file stm32wbxx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U

fSAMPLING=fDTS/16, N=8

Definition at line 996 of file stm32wbxx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U

fSAMPLING=fCK_INT, N=2

Definition at line 985 of file stm32wbxx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U

fSAMPLING=fCK_INT, N=4

Definition at line 986 of file stm32wbxx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U

fSAMPLING=fCK_INT, N=8

Definition at line 987 of file stm32wbxx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U

fSAMPLING=fDTS/2, N=6

Definition at line 988 of file stm32wbxx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U

fSAMPLING=fDTS/2, N=8

Definition at line 989 of file stm32wbxx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U

fSAMPLING=fDTS/32, N=5

Definition at line 997 of file stm32wbxx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U

fSAMPLING=fDTS/32, N=6

Definition at line 998 of file stm32wbxx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U

fSAMPLING=fDTS/32, N=8

Definition at line 999 of file stm32wbxx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U

fSAMPLING=fDTS/4, N=6

Definition at line 990 of file stm32wbxx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U

fSAMPLING=fDTS/4, N=8

Definition at line 991 of file stm32wbxx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U

fSAMPLING=fDTS/8, N=6

Definition at line 992 of file stm32wbxx_ll_tim.h.

#define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U

fSAMPLING=fDTS/8, N=8

Definition at line 993 of file stm32wbxx_ll_tim.h.

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: OSSI

Defines
OSSI
TIM Exported Constants

Defines

#define | LL_TIM_OSSI_DISABLE 0x00000000U
#define | LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI

Define Documentation

#define LL_TIM_OSSI_DISABLE 0x00000000U

When inactive, OCx/OCxN outputs are disabled

Definition at line 1007 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

#define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI

When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime

Definition at line 1008 of file stm32wbxx_ll_tim.h.

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: OSSR

Defines
OSSR
TIM Exported Constants

Defines

#define | LL_TIM_OSSR_DISABLE 0x00000000U
#define | LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR

Define Documentation

#define LL_TIM_OSSR_DISABLE 0x00000000U

When inactive, OCx/OCxN outputs are disabled

Definition at line 1016 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

#define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR

When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1

Definition at line 1017 of file stm32wbxx_ll_tim.h.

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: BREAK INPUT

Defines
BREAK INPUT
TIM Exported Constants

Defines

#define | LL_TIM_BREAK_INPUT_BKIN 0x00000000U
#define | LL_TIM_BREAK_INPUT_BKIN2 0x00000004U

Define Documentation

#define LL_TIM_BREAK_INPUT_BKIN 0x00000000U

TIMx_BKIN input

Definition at line 1025 of file stm32wbxx_ll_tim.h.

#define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U

TIMx_BKIN2 input

Definition at line 1026 of file stm32wbxx_ll_tim.h.

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STM32WB55xx HAL User Manual: BKIN SOURCE

Defines
BKIN SOURCE
TIM Exported Constants

Defines

#define | LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE
#define | LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_AF1_BKCMP1E
#define | LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_AF1_BKCMP2E

Define Documentation

#define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_AF1_BKCMP1E

internal signal: COMP1 output

Definition at line 1036 of file stm32wbxx_ll_tim.h.

#define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_AF1_BKCMP2E

internal signal: COMP2 output

Definition at line 1037 of file stm32wbxx_ll_tim.h.

#define LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE

BKIN input from AF controller

Definition at line 1034 of file stm32wbxx_ll_tim.h.

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: BKIN POLARITY

Defines
BKIN POLARITY
TIM Exported Constants

Defines

#define | LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP
#define | LL_TIM_BKIN_POLARITY_HIGH 0x00000000U

Define Documentation

#define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U

BRK BKIN input is active high

Definition at line 1047 of file stm32wbxx_ll_tim.h.

#define LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP

BRK BKIN input is active low

Definition at line 1046 of file stm32wbxx_ll_tim.h.

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DMA Burst Base Address

Defines
DMA Burst Base Address
TIM Exported Constants

Defines

#define | LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U
#define | LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0
#define | LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1
#define | LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2
#define | LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3
#define | LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)
#define | LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4
#define | LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2)
#define | LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3)
#define | LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0)

Define Documentation

#define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3)

TIMx_AF1 register is the DMA base address for DMA burst

Definition at line 1077 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0)

TIMx_AF2 register is the DMA base address for DMA burst

Definition at line 1078 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)

TIMx_ARR register is the DMA base address for DMA burst

Definition at line 1066 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)

TIMx_BDTR register is the DMA base address for DMA burst

Definition at line 1072 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3

TIMx_CCER register is the DMA base address for DMA burst

Definition at line 1063 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)

TIMx_CCMR1 register is the DMA base address for DMA burst

Definition at line 1061 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)

TIMx_CCMR2 register is the DMA base address for DMA burst

Definition at line 1062 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)

TIMx_CCMR3 register is the DMA base address for DMA burst

Definition at line 1074 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)

TIMx_CCR1 register is the DMA base address for DMA burst

Definition at line 1068 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)

TIMx_CCR2 register is the DMA base address for DMA burst

Definition at line 1069 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)

TIMx_CCR3 register is the DMA base address for DMA burst

Definition at line 1070 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4

TIMx_CCR4 register is the DMA base address for DMA burst

Definition at line 1071 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)

TIMx_CCR5 register is the DMA base address for DMA burst

Definition at line 1075 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)

TIMx_CCR6 register is the DMA base address for DMA burst

Definition at line 1076 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)

TIMx_CNT register is the DMA base address for DMA burst

Definition at line 1064 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U

TIMx_CR1 register is the DMA base address for DMA burst

Definition at line 1055 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0

TIMx_CR2 register is the DMA base address for DMA burst

Definition at line 1056 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0)

TIMx_DIER register is the DMA base address for DMA burst

Definition at line 1058 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)

TIMx_EGR register is the DMA base address for DMA burst

Definition at line 1060 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2)

TIMx_OR register is the DMA base address for DMA burst

Definition at line 1073 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)

TIMx_PSC register is the DMA base address for DMA burst

Definition at line 1065 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)

TIMx_RCR register is the DMA base address for DMA burst

Definition at line 1067 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1

TIMx_SMCR register is the DMA base address for DMA burst

Definition at line 1057 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2

TIMx_SR register is the DMA base address for DMA burst

Definition at line 1059 of file stm32wbxx_ll_tim.h.

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STM32WB55xx HAL User Manual: DMA Burst Length

Defines
DMA Burst Length
TIM Exported Constants

Defines

#define | LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U
#define | LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0
#define | LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1
#define | LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2
#define | LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3
#define | LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)
#define | LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4
#define | LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0)

Define Documentation

#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)

Transfer is done to 10 registers starting from the DMA burst base address

Definition at line 1095 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)

Transfer is done to 11 registers starting from the DMA burst base address

Definition at line 1096 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)

Transfer is done to 12 registers starting from the DMA burst base address

Definition at line 1097 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)

Transfer is done to 13 registers starting from the DMA burst base address

Definition at line 1098 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)

Transfer is done to 14 registers starting from the DMA burst base address

Definition at line 1099 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)

Transfer is done to 15 registers starting from the DMA burst base address

Definition at line 1100 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)

Transfer is done to 16 registers starting from the DMA burst base address

Definition at line 1101 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4

Transfer is done to 17 registers starting from the DMA burst base address

Definition at line 1102 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0)

Transfer is done to 18 registers starting from the DMA burst base address

Definition at line 1103 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U

Transfer is done to 1 register starting from the DMA burst base address

Definition at line 1086 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0

Transfer is done to 2 registers starting from the DMA burst base address

Definition at line 1087 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1

Transfer is done to 3 registers starting from the DMA burst base address

Definition at line 1088 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0)

Transfer is done to 4 registers starting from the DMA burst base address

Definition at line 1089 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2

Transfer is done to 5 registers starting from the DMA burst base address

Definition at line 1090 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)

Transfer is done to 6 registers starting from the DMA burst base address

Definition at line 1091 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)

Transfer is done to 7 registers starting from the DMA burst base address

Definition at line 1092 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)

Transfer is done to 1 registers starting from the DMA burst base address

Definition at line 1093 of file stm32wbxx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3

Transfer is done to 9 registers starting from the DMA burst base address

Definition at line 1094 of file stm32wbxx_ll_tim.h.

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STM32WB55xx HAL User Manual: TIM1 External Trigger ADC1 Remap

Defines
TIM1 External Trigger ADC1 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM1_ETR_ADC1_RMP_NC TIM1_OR_RMP_MASK
#define | LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (TIM1_OR_ETR_ADC1_RMP_0 | TIM1_OR_RMP_MASK)
#define | LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (TIM1_OR_ETR_ADC1_RMP_1 | TIM1_OR_RMP_MASK)
#define | LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (TIM1_OR_ETR_ADC1_RMP | TIM1_OR_RMP_MASK)

Define Documentation

#define LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (TIM1_OR_ETR_ADC1_RMP_0 | TIM1_OR_RMP_MASK)

TIM1_ETR is connected to ADC1 analog watchdog 1

Definition at line 1112 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (TIM1_OR_ETR_ADC1_RMP_1 | TIM1_OR_RMP_MASK)

TIM1_ETR is connected to ADC1 analog watchdog 2

Definition at line 1113 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (TIM1_OR_ETR_ADC1_RMP | TIM1_OR_RMP_MASK)

TIM1_ETR is connected to ADC1 analog watchdog 3

Definition at line 1114 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TIM1_ETR_ADC1_RMP_NC TIM1_OR_RMP_MASK

TIM1_ETR is not connected to ADC1 analog watchdog x

Definition at line 1111 of file stm32wbxx_ll_tim.h.

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STM32WB55xx HAL User Manual: TIM1 External Input Ch1 Remap

Defines
TIM1 External Input Ch1 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM1_TI1_RMP_GPIO TIM1_OR_RMP_MASK
#define | LL_TIM_TIM1_TI1_RMP_COMP1 (TIM1_OR_TI1_RMP | TIM1_OR_RMP_MASK)

Define Documentation

#define LL_TIM_TIM1_TI1_RMP_COMP1 (TIM1_OR_TI1_RMP | TIM1_OR_RMP_MASK)

TIM1 input capture 1 is connected to COMP1 output

Definition at line 1124 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TIM1_TI1_RMP_GPIO TIM1_OR_RMP_MASK

TIM1 input capture 1 is connected to GPIO

Definition at line 1122 of file stm32wbxx_ll_tim.h.

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM2 Internal Trigger1 Remap

Defines
TIM2 Internal Trigger1 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM2_ITR1_RMP_NONE TIM2_OR_RMP_MASK /* !< No internal trigger on TIM2_ITR1 */
#define | LL_TIM_TIM2_ITR1_RMP_USB_SOF (TIM2_OR_ITR1_RMP) /* !< TIM2_ITR1 is connected to USB SOF */

Define Documentation

#define LL_TIM_TIM2_ITR1_RMP_NONE TIM2_OR_RMP_MASK /* !< No internal trigger on TIM2_ITR1 */

Definition at line 1133 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TIM2_ITR1_RMP_USB_SOF (TIM2_OR_ITR1_RMP) /* !< TIM2_ITR1 is connected to USB SOF */

Definition at line 1135 of file stm32wbxx_ll_tim.h.

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM2 External Trigger Remap

Defines
TIM2 External Trigger Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM2_ETR_RMP_GPIO TIM2_OR_RMP_MASK
#define | LL_TIM_TIM2_ETR_RMP_LSE (TIM2_OR_ETR_RMP | TIM2_OR_RMP_MASK)

Define Documentation

#define LL_TIM_TIM2_ETR_RMP_GPIO TIM2_OR_RMP_MASK

TIM2_ETR is connected to GPIO

Definition at line 1144 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TIM2_ETR_RMP_LSE (TIM2_OR_ETR_RMP | TIM2_OR_RMP_MASK)

TIM2_ETR is connected to LSE

Definition at line 1145 of file stm32wbxx_ll_tim.h.

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STM32WB55xx HAL User Manual: TIM2 External Input Ch4 Remap

Defines
TIM2 External Input Ch4 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM2_TI4_RMP_GPIO TIM2_OR_RMP_MASK
#define | LL_TIM_TIM2_TI4_RMP_COMP1 (TIM2_OR_TI4_RMP_0 | TIM2_OR_RMP_MASK)
#define | LL_TIM_TIM2_TI4_RMP_COMP2 (TIM2_OR_TI4_RMP_1 | TIM2_OR_RMP_MASK)
#define | LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM2_OR_TI4_RMP | TIM2_OR_RMP_MASK)

Define Documentation

#define LL_TIM_TIM2_TI4_RMP_COMP1 (TIM2_OR_TI4_RMP_0 | TIM2_OR_RMP_MASK)

TIM2 input capture 4 is connected to COMP1_OUT

Definition at line 1155 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM2_OR_TI4_RMP | TIM2_OR_RMP_MASK)

TIM2 input capture 4 is connected to logical OR between COMP1_OUT and COMP2_OUT

Definition at line 1157 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TIM2_TI4_RMP_COMP2 (TIM2_OR_TI4_RMP_1 | TIM2_OR_RMP_MASK)

TIM2 input capture 4 is connected to COMP2_OUT

Definition at line 1156 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TIM2_TI4_RMP_GPIO TIM2_OR_RMP_MASK

TIM2 input capture 4 is connected to GPIO

Definition at line 1153 of file stm32wbxx_ll_tim.h.

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STM32WB55xx HAL User Manual: TIM16 External Input Ch1 Remap

Defines
TIM16 External Input Ch1 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM16_TI1_RMP_GPIO TIM16_OR_RMP_MASK
#define | LL_TIM_TIM16_TI1_RMP_LSI (TIM16_OR_TI1_RMP_0 | TIM16_OR_RMP_MASK)
#define | LL_TIM_TIM16_TI1_RMP_LSE (TIM16_OR_TI1_RMP_1 | TIM16_OR_RMP_MASK)
#define | LL_TIM_TIM16_TI1_RMP_RTC (TIM16_OR_TI1_RMP_1 | TIM16_OR_TI1_RMP_0 | TIM16_OR_RMP_MASK)

Define Documentation

#define LL_TIM_TIM16_TI1_RMP_GPIO TIM16_OR_RMP_MASK

TIM16 input capture 1 is connected to GPIO

Definition at line 1165 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TIM16_TI1_RMP_LSE (TIM16_OR_TI1_RMP_1 | TIM16_OR_RMP_MASK)

TIM16 input capture 1 is connected to LSE

Definition at line 1167 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TIM16_TI1_RMP_LSI (TIM16_OR_TI1_RMP_0 | TIM16_OR_RMP_MASK)

TIM16 input capture 1 is connected to LSI

Definition at line 1166 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TIM16_TI1_RMP_RTC (TIM16_OR_TI1_RMP_1 | TIM16_OR_TI1_RMP_0 | TIM16_OR_RMP_MASK)

TIM16 input capture 1 is connected to RTC wakeup interrupt

Definition at line 1168 of file stm32wbxx_ll_tim.h.

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STM32WB55xx HAL User Manual: TIM17 Timer Input Ch1 Remap

Defines
TIM17 Timer Input Ch1 Remap
TIM Exported Constants

Defines

#define | LL_TIM_TIM17_TI1_RMP_GPIO TIM17_OR_RMP_MASK
#define | LL_TIM_TIM17_TI1_RMP_MSI (TIM17_OR_TI1_RMP_0 | TIM17_OR_RMP_MASK)
#define | LL_TIM_TIM17_TI1_RMP_HSE_32 (TIM17_OR_TI1_RMP_1 | TIM17_OR_RMP_MASK)
#define | LL_TIM_TIM17_TI1_RMP_MCO (TIM17_OR_TI1_RMP | TIM17_OR_RMP_MASK)

Define Documentation

#define LL_TIM_TIM17_TI1_RMP_GPIO TIM17_OR_RMP_MASK

TIM17 input capture 1 is connected to GPIO

Definition at line 1176 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TIM17_TI1_RMP_HSE_32 (TIM17_OR_TI1_RMP_1 | TIM17_OR_RMP_MASK)

TIM17 input capture 1 is connected to HSE/32

Definition at line 1178 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TIM17_TI1_RMP_MCO (TIM17_OR_TI1_RMP | TIM17_OR_RMP_MASK)

TIM17 input capture 1 is connected to MCO

Definition at line 1179 of file stm32wbxx_ll_tim.h.

#define LL_TIM_TIM17_TI1_RMP_MSI (TIM17_OR_TI1_RMP_0 | TIM17_OR_RMP_MASK)

TIM17 input capture 1 is connected to MSI

Definition at line 1177 of file stm32wbxx_ll_tim.h.

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: OCREF clear input selection

Defines
OCREF clear input selection
TIM Exported Constants

Defines

#define | LL_TIM_OCREF_CLR_INT_OCREF_CLR 0x00000000U
#define | LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS

Define Documentation

#define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS

OCREF_CLR_INT is connected to ETRF

Definition at line 1188 of file stm32wbxx_ll_tim.h.

#define LL_TIM_OCREF_CLR_INT_OCREF_CLR 0x00000000U

OCREF_CLR_INT is connected to the OCREF_CLR input

Definition at line 1187 of file stm32wbxx_ll_tim.h.

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
TIM Exported Macros

Defines

#define | LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
Write a value in TIM register.
#define | LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
Read a value in TIM register.

Define Documentation

#define LL_TIM_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG((__INSTANCE__)->__REG__)

Read a value in TIM register.

Parameters:
__INSTANCE__ | TIM Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 1227 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), LL_TIM_HALLSENSOR_Init(), LL_TIM_Init(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

#define LL_TIM_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))

Write a value in TIM register.

Parameters:
__INSTANCE__ | TIM Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 1219 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), LL_TIM_ENCODER_Init(), LL_TIM_HALLSENSOR_Init(), LL_TIM_Init(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Exported_Macros

Defines
Exported_Macros
TIM Exported Macros

Defines

#define | __LL_TIM_GETFLAG_UIFCPY(__CNT__) (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
HELPER macro retrieving the UIFCPY flag from the counter value.
#define | __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)
HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
#define | __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
#define | __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
#define | __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)
HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
#define | __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)
HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
#define | __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
HELPER macro retrieving the ratio of the input capture prescaler.

Define Documentation

#define __LL_TIM_CALC_ARR | ( | __TIMCLK__,
 |  | __PSC__,
 |  | __FREQ__
 | ) | ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)

HELPER macro calculating the auto-reload value to achieve the required output signal frequency.

Note:
ex: __LL_TIM_CALC_ARR (1000000, LL_TIM_GetPrescaler (), 10000);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__PSC__ | prescaler
__FREQ__ | output signal frequency (in Hz)
Return values:
Auto-reload value (between Min_Data=0 and Max_Data=65535)

Definition at line 1283 of file stm32wbxx_ll_tim.h.

#define __LL_TIM_CALC_DEADTIME | ( | __TIMCLK__,
 |  | __CKD__,
 |  | __DT__
 | ) |
Value:
( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))    ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  & DT_DELAY_1) :                                               \
    (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
    (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
    (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
    0U)

HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.

Note:
ex: __LL_TIM_CALC_DEADTIME (80000000, LL_TIM_GetClockDivision (), 120);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__CKD__ This parameter can be one of the following values:
  • LL_TIM_CLOCKDIVISION_DIV1
  • LL_TIM_CLOCKDIVISION_DIV2
  • LL_TIM_CLOCKDIVISION_DIV4
__DT__ | deadtime duration (in ns)
Return values:
DTG[0:7]

Definition at line 1258 of file stm32wbxx_ll_tim.h.

#define __LL_TIM_CALC_DELAY | ( | __TIMCLK__,
 |  | __PSC__,
 |  | __DELAY__
 | ) |
Value:
((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
              / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))

HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.

Note:
ex: __LL_TIM_CALC_DELAY (1000000, LL_TIM_GetPrescaler (), 10);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__PSC__ | prescaler
__DELAY__ | timer output compare active/inactive delay (in us)
Return values:
Compare value (between Min_Data=0 and Max_Data=65535)

Definition at line 1294 of file stm32wbxx_ll_tim.h.

#define __LL_TIM_CALC_PSC | ( | __TIMCLK__,
 |  | __CNTCLK__
 | ) | (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)

HELPER macro calculating the prescaler value to achieve the required counter clock frequency.

Note:
ex: __LL_TIM_CALC_PSC (80000000, 1000000);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__CNTCLK__ | counter clock frequency (in Hz)
Return values:
Prescaler value (between Min_Data=0 and Max_Data=65535)

Definition at line 1272 of file stm32wbxx_ll_tim.h.

#define __LL_TIM_CALC_PULSE | ( | __TIMCLK__,
 |  | __PSC__,
 |  | __DELAY__,
 |  | __PULSE__
 | ) |
Value:
((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
              + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))

HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).

Note:
ex: __LL_TIM_CALC_PULSE (1000000, LL_TIM_GetPrescaler (), 10, 20);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__PSC__ | prescaler
__DELAY__ | timer output compare active/inactive delay (in us)
__PULSE__ | pulse duration (in us)
Return values:
Auto-reload value (between Min_Data=0 and Max_Data=65535)

Definition at line 1307 of file stm32wbxx_ll_tim.h.

#define __LL_TIM_GET_ICPSC_RATIO ( __ICPSC__ ) ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))

HELPER macro retrieving the ratio of the input capture prescaler.

Note:
ex: __LL_TIM_GET_ICPSC_RATIO (LL_TIM_IC_GetPrescaler ());
Parameters:
__ICPSC__ This parameter can be one of the following values:
  • LL_TIM_ICPSC_DIV1
  • LL_TIM_ICPSC_DIV2
  • LL_TIM_ICPSC_DIV4
  • LL_TIM_ICPSC_DIV8
Return values:
Input capture prescaler ratio (1, 2, 4 or 8)

Definition at line 1321 of file stm32wbxx_ll_tim.h.

#define __LL_TIM_GETFLAG_UIFCPY ( __CNT__ ) (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)

HELPER macro retrieving the UIFCPY flag from the counter value.

Note:
ex: __LL_TIM_GETFLAG_UIFCPY (LL_TIM_GetCounter ());
Relevant only if UIF flag remapping has been enabled (UIF status bit is copied to TIMx_CNT register bit 31)
Parameters:
__CNT__ Counter value
Return values:
UIF status bit

Definition at line 1244 of file stm32wbxx_ll_tim.h.

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Time Base configuration

Functions
Time Base configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_EnableCounter (TIM_TypeDef *TIMx)
Enable timer counter.
__STATIC_INLINE void | LL_TIM_DisableCounter (TIM_TypeDef *TIMx)
Disable timer counter.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledCounter (TIM_TypeDef *TIMx)
Indicates whether the timer counter is enabled.
__STATIC_INLINE void | LL_TIM_EnableUpdateEvent (TIM_TypeDef *TIMx)
Enable update event generation.
__STATIC_INLINE void | LL_TIM_DisableUpdateEvent (TIM_TypeDef *TIMx)
Disable update event generation.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledUpdateEvent (TIM_TypeDef *TIMx)
Indicates whether update event generation is enabled.
__STATIC_INLINE void | LL_TIM_SetUpdateSource (TIM_TypeDef *TIMx, uint32_t UpdateSource)
Set update event source.
__STATIC_INLINE uint32_t | LL_TIM_GetUpdateSource (TIM_TypeDef *TIMx)
Get actual event update source.
__STATIC_INLINE void | LL_TIM_SetOnePulseMode (TIM_TypeDef *TIMx, uint32_t OnePulseMode)
Set one pulse mode (one shot v.s.
__STATIC_INLINE uint32_t | LL_TIM_GetOnePulseMode (TIM_TypeDef *TIMx)
Get actual one pulse mode.
__STATIC_INLINE void | LL_TIM_SetCounterMode (TIM_TypeDef *TIMx, uint32_t CounterMode)
Set the timer counter counting mode.
__STATIC_INLINE uint32_t | LL_TIM_GetCounterMode (TIM_TypeDef *TIMx)
Get actual counter mode.
__STATIC_INLINE void | LL_TIM_EnableARRPreload (TIM_TypeDef *TIMx)
Enable auto-reload (ARR) preload.
__STATIC_INLINE void | LL_TIM_DisableARRPreload (TIM_TypeDef *TIMx)
Disable auto-reload (ARR) preload.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledARRPreload (TIM_TypeDef *TIMx)
Indicates whether auto-reload (ARR) preload is enabled.
__STATIC_INLINE void | LL_TIM_SetClockDivision (TIM_TypeDef *TIMx, uint32_t ClockDivision)
Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
__STATIC_INLINE uint32_t | LL_TIM_GetClockDivision (TIM_TypeDef *TIMx)
Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
__STATIC_INLINE void | LL_TIM_SetCounter (TIM_TypeDef *TIMx, uint32_t Counter)
Set the counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetCounter (TIM_TypeDef *TIMx)
Get the counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetDirection (TIM_TypeDef *TIMx)
Get the current direction of the counter.
__STATIC_INLINE void | LL_TIM_SetPrescaler (TIM_TypeDef *TIMx, uint32_t Prescaler)
Set the prescaler value.
__STATIC_INLINE uint32_t | LL_TIM_GetPrescaler (TIM_TypeDef *TIMx)
Get the prescaler value.
__STATIC_INLINE void | LL_TIM_SetAutoReload (TIM_TypeDef *TIMx, uint32_t AutoReload)
Set the auto-reload value.
__STATIC_INLINE uint32_t | LL_TIM_GetAutoReload (TIM_TypeDef *TIMx)
Get the auto-reload value.
__STATIC_INLINE void | LL_TIM_SetRepetitionCounter (TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
Set the repetition counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetRepetitionCounter (TIM_TypeDef *TIMx)
Get the repetition counter value.
__STATIC_INLINE void | LL_TIM_EnableUIFRemap (TIM_TypeDef *TIMx)
Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
__STATIC_INLINE void | LL_TIM_DisableUIFRemap (TIM_TypeDef *TIMx)
Disable update interrupt flag (UIF) remapping.

Function Documentation

__STATIC_INLINE void LL_TIM_DisableARRPreload ( TIM_TypeDef * TIMx )

Disable auto-reload (ARR) preload.

Reference Manual to LL API cross reference:
CR1 ARPE LL_TIM_DisableARRPreload
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1530 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableCounter ( TIM_TypeDef * TIMx )

Disable timer counter.

Reference Manual to LL API cross reference:
CR1 CEN LL_TIM_DisableCounter
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1359 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableUIFRemap ( TIM_TypeDef * TIMx )

Disable update interrupt flag (UIF) remapping.

Reference Manual to LL API cross reference:
CR1 UIFREMAP LL_TIM_DisableUIFRemap
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1723 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableUpdateEvent ( TIM_TypeDef * TIMx )

Disable update event generation.

Reference Manual to LL API cross reference:
CR1 UDIS LL_TIM_DisableUpdateEvent
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1392 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableARRPreload ( TIM_TypeDef * TIMx )

Enable auto-reload (ARR) preload.

Reference Manual to LL API cross reference:
CR1 ARPE LL_TIM_EnableARRPreload
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1519 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableCounter ( TIM_TypeDef * TIMx )

Enable timer counter.

Reference Manual to LL API cross reference:
CR1 CEN LL_TIM_EnableCounter
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1348 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableUIFRemap ( TIM_TypeDef * TIMx )

Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).

Note:
This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
Reference Manual to LL API cross reference:
CR1 UIFREMAP LL_TIM_EnableUIFRemap
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1712 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableUpdateEvent ( TIM_TypeDef * TIMx )

Enable update event generation.

Reference Manual to LL API cross reference:
CR1 UDIS LL_TIM_EnableUpdateEvent
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1381 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetAutoReload ( TIM_TypeDef * TIMx )

Get the auto-reload value.

Reference Manual to LL API cross reference:
ARR ARR LL_TIM_GetAutoReload
Note:
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Parameters:
TIMx Timer instance
Return values:
Auto-reload value

Definition at line 1672 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetClockDivision ( TIM_TypeDef * TIMx )

Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.

Note:
Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check whether or not the clock division feature is supported by the timer instance.
Reference Manual to LL API cross reference:
CR1 CKD LL_TIM_GetClockDivision
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_CLOCKDIVISION_DIV1
  • LL_TIM_CLOCKDIVISION_DIV2
  • LL_TIM_CLOCKDIVISION_DIV4

Definition at line 1576 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetCounter ( TIM_TypeDef * TIMx )

Get the counter value.

Note:
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Reference Manual to LL API cross reference:
CNT CNT LL_TIM_GetCounter
Parameters:
TIMx Timer instance
Return values:
Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)

Definition at line 1603 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetCounterMode ( TIM_TypeDef * TIMx )

Get actual counter mode.

Note:
Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to check whether or not the counter mode selection feature is supported by a timer instance.
Reference Manual to LL API cross reference:
CR1 DIR LL_TIM_GetCounterMode
CR1 CMS LL_TIM_GetCounterMode
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_COUNTERMODE_UP
  • LL_TIM_COUNTERMODE_DOWN
  • LL_TIM_COUNTERMODE_CENTER_UP
  • LL_TIM_COUNTERMODE_CENTER_DOWN
  • LL_TIM_COUNTERMODE_CENTER_UP_DOWN

Definition at line 1508 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetDirection ( TIM_TypeDef * TIMx )

Get the current direction of the counter.

Reference Manual to LL API cross reference:
CR1 DIR LL_TIM_GetDirection
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_COUNTERDIRECTION_UP
  • LL_TIM_COUNTERDIRECTION_DOWN

Definition at line 1616 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode ( TIM_TypeDef * TIMx )

Get actual one pulse mode.

Reference Manual to LL API cross reference:
CR1 OPM LL_TIM_GetOnePulseMode
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_ONEPULSEMODE_SINGLE
  • LL_TIM_ONEPULSEMODE_REPETITIVE

Definition at line 1464 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetPrescaler ( TIM_TypeDef * TIMx )

Get the prescaler value.

Reference Manual to LL API cross reference:
PSC PSC LL_TIM_GetPrescaler
Parameters:
TIMx Timer instance
Return values:
Prescaler value between Min_Data=0 and Max_Data=65535

Definition at line 1643 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter ( TIM_TypeDef * TIMx )

Get the repetition counter value.

Note:
Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a repetition counter.
Reference Manual to LL API cross reference:
RCR REP LL_TIM_GetRepetitionCounter
Parameters:
TIMx Timer instance
Return values:
Repetition counter value

Definition at line 1700 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource ( TIM_TypeDef * TIMx )

Get actual event update source.

Reference Manual to LL API cross reference:
CR1 URS LL_TIM_GetUpdateSource
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_UPDATESOURCE_REGULAR
  • LL_TIM_UPDATESOURCE_COUNTER

Definition at line 1437 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload ( TIM_TypeDef * TIMx )

Indicates whether auto-reload (ARR) preload is enabled.

Reference Manual to LL API cross reference:
CR1 ARPE LL_TIM_IsEnabledARRPreload
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1541 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter ( TIM_TypeDef * TIMx )

Indicates whether the timer counter is enabled.

Reference Manual to LL API cross reference:
CR1 CEN LL_TIM_IsEnabledCounter
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1370 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent ( TIM_TypeDef * TIMx )

Indicates whether update event generation is enabled.

Reference Manual to LL API cross reference:
CR1 UDIS LL_TIM_IsEnabledUpdateEvent
Parameters:
TIMx Timer instance
Return values:
Inverted state of bit (0 or 1).

Definition at line 1403 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetAutoReload | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | AutoReload
 | ) |  |

Set the auto-reload value.

Note:
The counter is blocked while the auto-reload value is null.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Helper macro __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
Reference Manual to LL API cross reference:
ARR ARR LL_TIM_SetAutoReload
Parameters:
TIMx | Timer instance
AutoReload | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 1659 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_Init().

__STATIC_INLINE void LL_TIM_SetClockDivision | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | ClockDivision
 | ) |  |

Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.

Note:
Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check whether or not the clock division feature is supported by the timer instance.
Reference Manual to LL API cross reference:
CR1 CKD LL_TIM_SetClockDivision
Parameters:
TIMx Timer instance
ClockDivision This parameter can be one of the following values:
  • LL_TIM_CLOCKDIVISION_DIV1
  • LL_TIM_CLOCKDIVISION_DIV2
  • LL_TIM_CLOCKDIVISION_DIV4
Return values:
None

Definition at line 1559 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetCounter | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Counter
 | ) |  |

Set the counter value.

Note:
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Reference Manual to LL API cross reference:
CNT CNT LL_TIM_SetCounter
Parameters:
TIMx | Timer instance
Counter | Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
Return values:
None

Definition at line 1590 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetCounterMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CounterMode
 | ) |  |

Set the timer counter counting mode.

Note:
Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to check whether or not the counter mode selection feature is supported by a timer instance.
Switching from Center Aligned counter mode to Edge counter mode (or reverse) requires a timer reset to avoid unexpected direction due to DIR bit readonly in center aligned mode.
Reference Manual to LL API cross reference:
CR1 DIR LL_TIM_SetCounterMode
CR1 CMS LL_TIM_SetCounterMode
Parameters:
TIMx Timer instance
CounterMode This parameter can be one of the following values:
  • LL_TIM_COUNTERMODE_UP
  • LL_TIM_COUNTERMODE_DOWN
  • LL_TIM_COUNTERMODE_CENTER_UP
  • LL_TIM_COUNTERMODE_CENTER_DOWN
  • LL_TIM_COUNTERMODE_CENTER_UP_DOWN
Return values:
None

Definition at line 1488 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetOnePulseMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | OnePulseMode
 | ) |  |

Set one pulse mode (one shot v.s.

repetitive).

Reference Manual to LL API cross reference:
CR1 OPM LL_TIM_SetOnePulseMode
Parameters:
TIMx Timer instance
OnePulseMode This parameter can be one of the following values:
  • LL_TIM_ONEPULSEMODE_SINGLE
  • LL_TIM_ONEPULSEMODE_REPETITIVE
Return values:
None

Definition at line 1451 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetPrescaler | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Prescaler
 | ) |  |

Set the prescaler value.

Note:
The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
The prescaler can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event.
Helper macro __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
Reference Manual to LL API cross reference:
PSC PSC LL_TIM_SetPrescaler
Parameters:
TIMx | Timer instance
Prescaler | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 1632 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_Init().

__STATIC_INLINE void LL_TIM_SetRepetitionCounter | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | RepetitionCounter
 | ) |  |

Set the repetition counter value.

Note:
For advanced timer instances RepetitionCounter can be up to 65535.
Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a repetition counter.
Reference Manual to LL API cross reference:
RCR REP LL_TIM_SetRepetitionCounter
Parameters:
TIMx | Timer instance
RepetitionCounter | between Min_Data=0 and Max_Data=255
Return values:
None

Definition at line 1687 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_Init().

__STATIC_INLINE void LL_TIM_SetUpdateSource | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | UpdateSource
 | ) |  |

Set update event source.

Note:
Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events generate an update interrupt or DMA request if enabled:
  • Counter overflow/underflow
  • Setting the UG bit
  • Update generation through the slave mode controller
Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter overflow/underflow generates an update interrupt or DMA request if enabled.
Reference Manual to LL API cross reference:
CR1 URS LL_TIM_SetUpdateSource
Parameters:
TIMx Timer instance
UpdateSource This parameter can be one of the following values:
  • LL_TIM_UPDATESOURCE_REGULAR
  • LL_TIM_UPDATESOURCE_COUNTER
Return values:
None

Definition at line 1424 of file stm32wbxx_ll_tim.h.

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Capture Compare configuration

Functions
Capture Compare configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_CC_EnablePreload (TIM_TypeDef *TIMx)
Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
__STATIC_INLINE void | LL_TIM_CC_DisablePreload (TIM_TypeDef *TIMx)
Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
__STATIC_INLINE void | LL_TIM_CC_SetUpdate (TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
__STATIC_INLINE void | LL_TIM_CC_SetDMAReqTrigger (TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
Set the trigger of the capture/compare DMA request.
__STATIC_INLINE uint32_t | LL_TIM_CC_GetDMAReqTrigger (TIM_TypeDef *TIMx)
Get actual trigger of the capture/compare DMA request.
__STATIC_INLINE void | LL_TIM_CC_SetLockLevel (TIM_TypeDef *TIMx, uint32_t LockLevel)
Set the lock level to freeze the configuration of several capture/compare parameters.
__STATIC_INLINE void | LL_TIM_CC_EnableChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Enable capture/compare channels.
__STATIC_INLINE void | LL_TIM_CC_DisableChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Disable capture/compare channels.
__STATIC_INLINE uint32_t | LL_TIM_CC_IsEnabledChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Indicate whether channel(s) is(are) enabled.

Function Documentation

__STATIC_INLINE void LL_TIM_CC_DisableChannel | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channels
 | ) |  |

Disable capture/compare channels.

Reference Manual to LL API cross reference:
CCER CC1E LL_TIM_CC_DisableChannel
CCER CC1NE LL_TIM_CC_DisableChannel
CCER CC2E LL_TIM_CC_DisableChannel
CCER CC2NE LL_TIM_CC_DisableChannel
CCER CC3E LL_TIM_CC_DisableChannel
CCER CC3NE LL_TIM_CC_DisableChannel
CCER CC4E LL_TIM_CC_DisableChannel
CCER CC5E LL_TIM_CC_DisableChannel
CCER CC6E LL_TIM_CC_DisableChannel
Parameters:
TIMx Timer instance
Channels This parameter can be a combination of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 1879 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_DisablePreload ( TIM_TypeDef * TIMx )

Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.

Note:
Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check whether or not a timer instance is able to generate a commutation event.
Reference Manual to LL API cross reference:
CR2 CCPC LL_TIM_CC_DisablePreload
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1759 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_EnableChannel | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channels
 | ) |  |

Enable capture/compare channels.

Reference Manual to LL API cross reference:
CCER CC1E LL_TIM_CC_EnableChannel
CCER CC1NE LL_TIM_CC_EnableChannel
CCER CC2E LL_TIM_CC_EnableChannel
CCER CC2NE LL_TIM_CC_EnableChannel
CCER CC3E LL_TIM_CC_EnableChannel
CCER CC3NE LL_TIM_CC_EnableChannel
CCER CC4E LL_TIM_CC_EnableChannel
CCER CC5E LL_TIM_CC_EnableChannel
CCER CC6E LL_TIM_CC_EnableChannel
Parameters:
TIMx Timer instance
Channels This parameter can be a combination of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 1850 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_EnablePreload ( TIM_TypeDef * TIMx )

Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.

Note:
CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs.
Only on channels that have a complementary output.
Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check whether or not a timer instance is able to generate a commutation event.
Reference Manual to LL API cross reference:
CR2 CCPC LL_TIM_CC_EnablePreload
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1746 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger ( TIM_TypeDef * TIMx )

Get actual trigger of the capture/compare DMA request.

Reference Manual to LL API cross reference:
CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_CCDMAREQUEST_CC
  • LL_TIM_CCDMAREQUEST_UPDATE

Definition at line 1802 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channels
 | ) |  |

Indicate whether channel(s) is(are) enabled.

Reference Manual to LL API cross reference:
CCER CC1E LL_TIM_CC_IsEnabledChannel
CCER CC1NE LL_TIM_CC_IsEnabledChannel
CCER CC2E LL_TIM_CC_IsEnabledChannel
CCER CC2NE LL_TIM_CC_IsEnabledChannel
CCER CC3E LL_TIM_CC_IsEnabledChannel
CCER CC3NE LL_TIM_CC_IsEnabledChannel
CCER CC4E LL_TIM_CC_IsEnabledChannel
CCER CC5E LL_TIM_CC_IsEnabledChannel
CCER CC6E LL_TIM_CC_IsEnabledChannel
Parameters:
TIMx Timer instance
Channels This parameter can be a combination of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
State of bit (1 or 0).

Definition at line 1908 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | DMAReqTrigger
 | ) |  |

Set the trigger of the capture/compare DMA request.

Reference Manual to LL API cross reference:
CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
Parameters:
TIMx Timer instance
DMAReqTrigger This parameter can be one of the following values:
  • LL_TIM_CCDMAREQUEST_CC
  • LL_TIM_CCDMAREQUEST_UPDATE
Return values:
None

Definition at line 1789 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_SetLockLevel | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | LockLevel
 | ) |  |

Set the lock level to freeze the configuration of several capture/compare parameters.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not the lock mechanism is supported by a timer instance.
Reference Manual to LL API cross reference:
BDTR LOCK LL_TIM_CC_SetLockLevel
Parameters:
TIMx Timer instance
LockLevel This parameter can be one of the following values:
  • LL_TIM_LOCKLEVEL_OFF
  • LL_TIM_LOCKLEVEL_1
  • LL_TIM_LOCKLEVEL_2
  • LL_TIM_LOCKLEVEL_3
Return values:
None

Definition at line 1821 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_SetUpdate | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CCUpdateSource
 | ) |  |

Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).

Note:
Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check whether or not a timer instance is able to generate a commutation event.
Reference Manual to LL API cross reference:
CR2 CCUS LL_TIM_CC_SetUpdate
Parameters:
TIMx Timer instance
CCUpdateSource This parameter can be one of the following values:
  • LL_TIM_CCUPDATESOURCE_COMG_ONLY
  • LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
Return values:
None

Definition at line 1775 of file stm32wbxx_ll_tim.h.

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Output channel configuration

Functions
Output channel configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_OC_ConfigOutput (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
Configure an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetMode (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
Define the behavior of the output reference signal OCxREF from which OCx and OCxN (when relevant) are derived.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetMode (TIM_TypeDef *TIMx, uint32_t Channel)
Get the output compare mode of an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetPolarity (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
Set the polarity of an output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetPolarity (TIM_TypeDef *TIMx, uint32_t Channel)
Get the polarity of an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetIdleState (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
Set the IDLE state of an output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetIdleState (TIM_TypeDef *TIMx, uint32_t Channel)
Get the IDLE state of an output channel.
__STATIC_INLINE void | LL_TIM_OC_EnableFast (TIM_TypeDef *TIMx, uint32_t Channel)
Enable fast mode for the output channel.
__STATIC_INLINE void | LL_TIM_OC_DisableFast (TIM_TypeDef *TIMx, uint32_t Channel)
Disable fast mode for the output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledFast (TIM_TypeDef *TIMx, uint32_t Channel)
Indicates whether fast mode is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_EnablePreload (TIM_TypeDef *TIMx, uint32_t Channel)
Enable compare register (TIMx_CCRx) preload for the output channel.
__STATIC_INLINE void | LL_TIM_OC_DisablePreload (TIM_TypeDef *TIMx, uint32_t Channel)
Disable compare register (TIMx_CCRx) preload for the output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledPreload (TIM_TypeDef *TIMx, uint32_t Channel)
Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_EnableClear (TIM_TypeDef *TIMx, uint32_t Channel)
Enable clearing the output channel on an external event.
__STATIC_INLINE void | LL_TIM_OC_DisableClear (TIM_TypeDef *TIMx, uint32_t Channel)
Disable clearing the output channel on an external event.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledClear (TIM_TypeDef *TIMx, uint32_t Channel)
Indicates clearing the output channel on an external event is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_SetDeadTime (TIM_TypeDef *TIMx, uint32_t DeadTime)
Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH1 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 1 (TIMx_CCR1).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH2 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 2 (TIMx_CCR2).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH3 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 3 (TIMx_CCR3).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH4 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 4 (TIMx_CCR4).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH5 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 5 (TIMx_CCR5).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH6 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 6 (TIMx_CCR6).
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH1 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR1) set for output channel 1.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH2 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR2) set for output channel 2.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH3 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR3) set for output channel 3.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH4 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR4) set for output channel 4.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH5 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR5) set for output channel 5.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH6 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR6) set for output channel 6.
__STATIC_INLINE void | LL_TIM_SetCH5CombinedChannels (TIM_TypeDef *TIMx, uint32_t GroupCH5)
Select on which reference signal the OC5REF is combined to.

Function Documentation

__STATIC_INLINE void LL_TIM_OC_ConfigOutput | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | Configuration
 | ) |  |

Configure an output channel.

Reference Manual to LL API cross reference:
CCMR1 CC1S LL_TIM_OC_ConfigOutput
CCMR1 CC2S LL_TIM_OC_ConfigOutput
CCMR2 CC3S LL_TIM_OC_ConfigOutput
CCMR2 CC4S LL_TIM_OC_ConfigOutput
CCMR3 CC5S LL_TIM_OC_ConfigOutput
CCMR3 CC6S LL_TIM_OC_ConfigOutput
CCER CC1P LL_TIM_OC_ConfigOutput
CCER CC2P LL_TIM_OC_ConfigOutput
CCER CC3P LL_TIM_OC_ConfigOutput
CCER CC4P LL_TIM_OC_ConfigOutput
CCER CC5P LL_TIM_OC_ConfigOutput
CCER CC6P LL_TIM_OC_ConfigOutput
CR2 OIS1 LL_TIM_OC_ConfigOutput
CR2 OIS2 LL_TIM_OC_ConfigOutput
CR2 OIS3 LL_TIM_OC_ConfigOutput
CR2 OIS4 LL_TIM_OC_ConfigOutput
CR2 OIS5 LL_TIM_OC_ConfigOutput
CR2 OIS6 LL_TIM_OC_ConfigOutput
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Configuration This parameter must be a combination of all the following values:
  • LL_TIM_OCPOLARITY_HIGH or LL_TIM_OCPOLARITY_LOW
  • LL_TIM_OCIDLESTATE_LOW or LL_TIM_OCIDLESTATE_HIGH
Return values:
None

Definition at line 1953 of file stm32wbxx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_DisableClear | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Disable clearing the output channel on an external event.

Note:
Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether or not a timer instance can clear the OCxREF signal on an external event.
Reference Manual to LL API cross reference:
CCMR1 OC1CE LL_TIM_OC_DisableClear
CCMR1 OC2CE LL_TIM_OC_DisableClear
CCMR2 OC3CE LL_TIM_OC_DisableClear
CCMR2 OC4CE LL_TIM_OC_DisableClear
CCMR3 OC5CE LL_TIM_OC_DisableClear
CCMR3 OC6CE LL_TIM_OC_DisableClear
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 2381 of file stm32wbxx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_DisableFast | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Disable fast mode for the output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1FE LL_TIM_OC_DisableFast
CCMR1 OC2FE LL_TIM_OC_DisableFast
CCMR2 OC3FE LL_TIM_OC_DisableFast
CCMR2 OC4FE LL_TIM_OC_DisableFast
CCMR3 OC5FE LL_TIM_OC_DisableFast
CCMR3 OC6FE LL_TIM_OC_DisableFast
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 2223 of file stm32wbxx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_DisablePreload | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Disable compare register (TIMx_CCRx) preload for the output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1PE LL_TIM_OC_DisablePreload
CCMR1 OC2PE LL_TIM_OC_DisablePreload
CCMR2 OC3PE LL_TIM_OC_DisablePreload
CCMR2 OC4PE LL_TIM_OC_DisablePreload
CCMR3 OC5PE LL_TIM_OC_DisablePreload
CCMR3 OC6PE LL_TIM_OC_DisablePreload
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 2300 of file stm32wbxx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_EnableClear | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Enable clearing the output channel on an external event.

Note:
This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether or not a timer instance can clear the OCxREF signal on an external event.
Reference Manual to LL API cross reference:
CCMR1 OC1CE LL_TIM_OC_EnableClear
CCMR1 OC2CE LL_TIM_OC_EnableClear
CCMR2 OC3CE LL_TIM_OC_EnableClear
CCMR2 OC4CE LL_TIM_OC_EnableClear
CCMR3 OC5CE LL_TIM_OC_EnableClear
CCMR3 OC6CE LL_TIM_OC_EnableClear
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 2354 of file stm32wbxx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_EnableFast | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Enable fast mode for the output channel.

Note:
Acts only if the channel is configured in PWM1 or PWM2 mode.
Reference Manual to LL API cross reference:
CCMR1 OC1FE LL_TIM_OC_EnableFast
CCMR1 OC2FE LL_TIM_OC_EnableFast
CCMR2 OC3FE LL_TIM_OC_EnableFast
CCMR2 OC4FE LL_TIM_OC_EnableFast
CCMR3 OC5FE LL_TIM_OC_EnableFast
CCMR3 OC6FE LL_TIM_OC_EnableFast
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 2197 of file stm32wbxx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_EnablePreload | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Enable compare register (TIMx_CCRx) preload for the output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1PE LL_TIM_OC_EnablePreload
CCMR1 OC2PE LL_TIM_OC_EnablePreload
CCMR2 OC3PE LL_TIM_OC_EnablePreload
CCMR2 OC4PE LL_TIM_OC_EnablePreload
CCMR3 OC5PE LL_TIM_OC_EnablePreload
CCMR3 OC6PE LL_TIM_OC_EnablePreload
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
None

Definition at line 2275 of file stm32wbxx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1 ( TIM_TypeDef * TIMx )

Get compare value (TIMx_CCR1) set for output channel 1.

Note:
In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not output channel 1 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR1 CCR1 LL_TIM_OC_GetCompareCH1
Parameters:
TIMx Timer instance
Return values:
CompareValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2540 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2 ( TIM_TypeDef * TIMx )

Get compare value (TIMx_CCR2) set for output channel 2.

Note:
In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not output channel 2 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR2 CCR2 LL_TIM_OC_GetCompareCH2
Parameters:
TIMx Timer instance
Return values:
CompareValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2556 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3 ( TIM_TypeDef * TIMx )

Get compare value (TIMx_CCR3) set for output channel 3.

Note:
In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not output channel 3 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR3 CCR3 LL_TIM_OC_GetCompareCH3
Parameters:
TIMx Timer instance
Return values:
CompareValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2572 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4 ( TIM_TypeDef * TIMx )

Get compare value (TIMx_CCR4) set for output channel 4.

Note:
In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not output channel 4 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR4 CCR4 LL_TIM_OC_GetCompareCH4
Parameters:
TIMx Timer instance
Return values:
CompareValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2588 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5 ( TIM_TypeDef * TIMx )

Get compare value (TIMx_CCR5) set for output channel 5.

Note:
Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not output channel 5 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR5 CCR5 LL_TIM_OC_GetCompareCH5
Parameters:
TIMx Timer instance
Return values:
CompareValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2601 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6 ( TIM_TypeDef * TIMx )

Get compare value (TIMx_CCR6) set for output channel 6.

Note:
Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not output channel 6 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR6 CCR6 LL_TIM_OC_GetCompareCH6
Parameters:
TIMx Timer instance
Return values:
CompareValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2614 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the IDLE state of an output channel.

Reference Manual to LL API cross reference:
CR2 OIS1 LL_TIM_OC_GetIdleState
CR2 OIS2N LL_TIM_OC_GetIdleState
CR2 OIS2 LL_TIM_OC_GetIdleState
CR2 OIS2N LL_TIM_OC_GetIdleState
CR2 OIS3 LL_TIM_OC_GetIdleState
CR2 OIS3N LL_TIM_OC_GetIdleState
CR2 OIS4 LL_TIM_OC_GetIdleState
CR2 OIS5 LL_TIM_OC_GetIdleState
CR2 OIS6 LL_TIM_OC_GetIdleState
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
Returned value can be one of the following values:
  • LL_TIM_OCIDLESTATE_LOW
  • LL_TIM_OCIDLESTATE_HIGH

Definition at line 2172 of file stm32wbxx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_GetMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the output compare mode of an output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1M LL_TIM_OC_GetMode
CCMR1 OC2M LL_TIM_OC_GetMode
CCMR2 OC3M LL_TIM_OC_GetMode
CCMR2 OC4M LL_TIM_OC_GetMode
CCMR3 OC5M LL_TIM_OC_GetMode
CCMR3 OC6M LL_TIM_OC_GetMode
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
Returned value can be one of the following values:
  • LL_TIM_OCMODE_FROZEN
  • LL_TIM_OCMODE_ACTIVE
  • LL_TIM_OCMODE_INACTIVE
  • LL_TIM_OCMODE_TOGGLE
  • LL_TIM_OCMODE_FORCED_INACTIVE
  • LL_TIM_OCMODE_FORCED_ACTIVE
  • LL_TIM_OCMODE_PWM1
  • LL_TIM_OCMODE_PWM2
  • LL_TIM_OCMODE_RETRIG_OPM1
  • LL_TIM_OCMODE_RETRIG_OPM2
  • LL_TIM_OCMODE_COMBINED_PWM1
  • LL_TIM_OCMODE_COMBINED_PWM2
  • LL_TIM_OCMODE_ASSYMETRIC_PWM1
  • LL_TIM_OCMODE_ASSYMETRIC_PWM2

Definition at line 2037 of file stm32wbxx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the polarity of an output channel.

Reference Manual to LL API cross reference:
CCER CC1P LL_TIM_OC_GetPolarity
CCER CC1NP LL_TIM_OC_GetPolarity
CCER CC2P LL_TIM_OC_GetPolarity
CCER CC2NP LL_TIM_OC_GetPolarity
CCER CC3P LL_TIM_OC_GetPolarity
CCER CC3NP LL_TIM_OC_GetPolarity
CCER CC4P LL_TIM_OC_GetPolarity
CCER CC5P LL_TIM_OC_GetPolarity
CCER CC6P LL_TIM_OC_GetPolarity
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
Returned value can be one of the following values:
  • LL_TIM_OCPOLARITY_HIGH
  • LL_TIM_OCPOLARITY_LOW

Definition at line 2103 of file stm32wbxx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Indicates clearing the output channel on an external event is enabled for the output channel.

Note:
This function enables clearing the output channel on an external event.
This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether or not a timer instance can clear the OCxREF signal on an external event.
Reference Manual to LL API cross reference:
CCMR1 OC1CE LL_TIM_OC_IsEnabledClear
CCMR1 OC2CE LL_TIM_OC_IsEnabledClear
CCMR2 OC3CE LL_TIM_OC_IsEnabledClear
CCMR2 OC4CE LL_TIM_OC_IsEnabledClear
CCMR3 OC5CE LL_TIM_OC_IsEnabledClear
CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
State of bit (1 or 0).

Definition at line 2410 of file stm32wbxx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Indicates whether fast mode is enabled for the output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1FE LL_TIM_OC_IsEnabledFast
CCMR1 OC2FE LL_TIM_OC_IsEnabledFast
CCMR2 OC3FE LL_TIM_OC_IsEnabledFast
CCMR2 OC4FE LL_TIM_OC_IsEnabledFast
CCMR3 OC5FE LL_TIM_OC_IsEnabledFast
CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
State of bit (1 or 0).

Definition at line 2249 of file stm32wbxx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload
CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload
CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload
CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload
CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload
CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Return values:
State of bit (1 or 0).

Definition at line 2325 of file stm32wbxx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_SetCompareCH1 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set compare value for output channel 1 (TIMx_CCR1).

Note:
In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not output channel 1 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR1 CCR1 LL_TIM_OC_SetCompareCH1
Parameters:
TIMx | Timer instance
CompareValue | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 2445 of file stm32wbxx_ll_tim.h.

Referenced by OC1Config().

__STATIC_INLINE void LL_TIM_OC_SetCompareCH2 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set compare value for output channel 2 (TIMx_CCR2).

Note:
In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not output channel 2 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR2 CCR2 LL_TIM_OC_SetCompareCH2
Parameters:
TIMx | Timer instance
CompareValue | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 2462 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init(), and OC2Config().

__STATIC_INLINE void LL_TIM_OC_SetCompareCH3 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set compare value for output channel 3 (TIMx_CCR3).

Note:
In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not output channel is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR3 CCR3 LL_TIM_OC_SetCompareCH3
Parameters:
TIMx | Timer instance
CompareValue | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 2479 of file stm32wbxx_ll_tim.h.

Referenced by OC3Config().

__STATIC_INLINE void LL_TIM_OC_SetCompareCH4 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set compare value for output channel 4 (TIMx_CCR4).

Note:
In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not output channel 4 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR4 CCR4 LL_TIM_OC_SetCompareCH4
Parameters:
TIMx | Timer instance
CompareValue | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 2496 of file stm32wbxx_ll_tim.h.

Referenced by OC4Config().

__STATIC_INLINE void LL_TIM_OC_SetCompareCH5 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set compare value for output channel 5 (TIMx_CCR5).

Note:
Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not output channel 5 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR5 CCR5 LL_TIM_OC_SetCompareCH5
Parameters:
TIMx | Timer instance
CompareValue | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 2510 of file stm32wbxx_ll_tim.h.

Referenced by OC5Config().

__STATIC_INLINE void LL_TIM_OC_SetCompareCH6 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set compare value for output channel 6 (TIMx_CCR6).

Note:
Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not output channel 6 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR6 CCR6 LL_TIM_OC_SetCompareCH6
Parameters:
TIMx | Timer instance
CompareValue | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 2524 of file stm32wbxx_ll_tim.h.

Referenced by OC6Config().

__STATIC_INLINE void LL_TIM_OC_SetDeadTime | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | DeadTime
 | ) |  |

Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not dead-time insertion feature is supported by a timer instance.
Helper macro __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
Reference Manual to LL API cross reference:
BDTR DTG LL_TIM_OC_SetDeadTime
Parameters:
TIMx | Timer instance
DeadTime | between Min_Data=0 and Max_Data=255
Return values:
None

Definition at line 2428 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_OC_SetIdleState | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | IdleState
 | ) |  |

Set the IDLE state of an output channel.

Note:
This function is significant only for the timer instances supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
CR2 OIS1 LL_TIM_OC_SetIdleState
CR2 OIS2N LL_TIM_OC_SetIdleState
CR2 OIS2 LL_TIM_OC_SetIdleState
CR2 OIS2N LL_TIM_OC_SetIdleState
CR2 OIS3 LL_TIM_OC_SetIdleState
CR2 OIS3N LL_TIM_OC_SetIdleState
CR2 OIS4 LL_TIM_OC_SetIdleState
CR2 OIS5 LL_TIM_OC_SetIdleState
CR2 OIS6 LL_TIM_OC_SetIdleState
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
IdleState This parameter can be one of the following values:
  • LL_TIM_OCIDLESTATE_LOW
  • LL_TIM_OCIDLESTATE_HIGH
Return values:
None

Definition at line 2140 of file stm32wbxx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_SetMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | Mode
 | ) |  |

Define the behavior of the output reference signal OCxREF from which OCx and OCxN (when relevant) are derived.

Reference Manual to LL API cross reference:
CCMR1 OC1M LL_TIM_OC_SetMode
CCMR1 OC2M LL_TIM_OC_SetMode
CCMR2 OC3M LL_TIM_OC_SetMode
CCMR2 OC4M LL_TIM_OC_SetMode
CCMR3 OC5M LL_TIM_OC_SetMode
CCMR3 OC6M LL_TIM_OC_SetMode
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Mode This parameter can be one of the following values:
  • LL_TIM_OCMODE_FROZEN
  • LL_TIM_OCMODE_ACTIVE
  • LL_TIM_OCMODE_INACTIVE
  • LL_TIM_OCMODE_TOGGLE
  • LL_TIM_OCMODE_FORCED_INACTIVE
  • LL_TIM_OCMODE_FORCED_ACTIVE
  • LL_TIM_OCMODE_PWM1
  • LL_TIM_OCMODE_PWM2
  • LL_TIM_OCMODE_RETRIG_OPM1
  • LL_TIM_OCMODE_RETRIG_OPM2
  • LL_TIM_OCMODE_COMBINED_PWM1
  • LL_TIM_OCMODE_COMBINED_PWM2
  • LL_TIM_OCMODE_ASSYMETRIC_PWM1
  • LL_TIM_OCMODE_ASSYMETRIC_PWM2
Return values:
None

Definition at line 1998 of file stm32wbxx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_SetPolarity | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | Polarity
 | ) |  |

Set the polarity of an output channel.

Reference Manual to LL API cross reference:
CCER CC1P LL_TIM_OC_SetPolarity
CCER CC1NP LL_TIM_OC_SetPolarity
CCER CC2P LL_TIM_OC_SetPolarity
CCER CC2NP LL_TIM_OC_SetPolarity
CCER CC3P LL_TIM_OC_SetPolarity
CCER CC3NP LL_TIM_OC_SetPolarity
CCER CC4P LL_TIM_OC_SetPolarity
CCER CC5P LL_TIM_OC_SetPolarity
CCER CC6P LL_TIM_OC_SetPolarity
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
Polarity This parameter can be one of the following values:
  • LL_TIM_OCPOLARITY_HIGH
  • LL_TIM_OCPOLARITY_LOW
Return values:
None

Definition at line 2071 of file stm32wbxx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | GroupCH5
 | ) |  |

Select on which reference signal the OC5REF is combined to.

Note:
Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check whether or not a timer instance supports the combined 3-phase PWM mode.
Reference Manual to LL API cross reference:
CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels
CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels
CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
Parameters:
TIMx Timer instance
GroupCH5 This parameter can be a combination of the following values:
  • LL_TIM_GROUPCH5_NONE
  • LL_TIM_GROUPCH5_OC1REFC
  • LL_TIM_GROUPCH5_OC2REFC
  • LL_TIM_GROUPCH5_OC3REFC
Return values:
None

Definition at line 2634 of file stm32wbxx_ll_tim.h.

Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Input channel configuration

Functions
Input channel configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_IC_Config (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
Configure input channel.
__STATIC_INLINE void | LL_TIM_IC_SetActiveInput (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
Set the active input.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetActiveInput (TIM_TypeDef *TIMx, uint32_t Channel)
Get the current active input.
__STATIC_INLINE void | LL_TIM_IC_SetPrescaler (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
Set the prescaler of input channel.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetPrescaler (TIM_TypeDef *TIMx, uint32_t Channel)
Get the current prescaler value acting on an input channel.
__STATIC_INLINE void | LL_TIM_IC_SetFilter (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
Set the input filter duration.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetFilter (TIM_TypeDef *TIMx, uint32_t Channel)
Get the input filter duration.
__STATIC_INLINE void | LL_TIM_IC_SetPolarity (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
Set the input channel polarity.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetPolarity (TIM_TypeDef *TIMx, uint32_t Channel)
Get the current input channel polarity.
__STATIC_INLINE void | LL_TIM_IC_EnableXORCombination (TIM_TypeDef *TIMx)
Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
__STATIC_INLINE void | LL_TIM_IC_DisableXORCombination (TIM_TypeDef *TIMx)
Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
__STATIC_INLINE uint32_t | LL_TIM_IC_IsEnabledXORCombination (TIM_TypeDef *TIMx)
Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH1 (TIM_TypeDef *TIMx)
Get captured value for input channel 1.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH2 (TIM_TypeDef *TIMx)
Get captured value for input channel 2.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH3 (TIM_TypeDef *TIMx)
Get captured value for input channel 3.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH4 (TIM_TypeDef *TIMx)
Get captured value for input channel 4.

Function Documentation

__STATIC_INLINE void LL_TIM_IC_Config | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | Configuration
 | ) |  |

Configure input channel.

Reference Manual to LL API cross reference:
CCMR1 CC1S LL_TIM_IC_Config
CCMR1 IC1PSC LL_TIM_IC_Config
CCMR1 IC1F LL_TIM_IC_Config
CCMR1 CC2S LL_TIM_IC_Config
CCMR1 IC2PSC LL_TIM_IC_Config
CCMR1 IC2F LL_TIM_IC_Config
CCMR2 CC3S LL_TIM_IC_Config
CCMR2 IC3PSC LL_TIM_IC_Config
CCMR2 IC3F LL_TIM_IC_Config
CCMR2 CC4S LL_TIM_IC_Config
CCMR2 IC4PSC LL_TIM_IC_Config
CCMR2 IC4F LL_TIM_IC_Config
CCER CC1P LL_TIM_IC_Config
CCER CC1NP LL_TIM_IC_Config
CCER CC2P LL_TIM_IC_Config
CCER CC2NP LL_TIM_IC_Config
CCER CC3P LL_TIM_IC_Config
CCER CC3NP LL_TIM_IC_Config
CCER CC4P LL_TIM_IC_Config
CCER CC4NP LL_TIM_IC_Config
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Configuration This parameter must be a combination of all the following values:
  • LL_TIM_ACTIVEINPUT_DIRECTTI or LL_TIM_ACTIVEINPUT_INDIRECTTI or LL_TIM_ACTIVEINPUT_TRC
  • LL_TIM_ICPSC_DIV1 or ... or LL_TIM_ICPSC_DIV8
  • LL_TIM_IC_FILTER_FDIV1 or ... or LL_TIM_IC_FILTER_FDIV32_N8
  • LL_TIM_IC_POLARITY_RISING or LL_TIM_IC_POLARITY_FALLING or LL_TIM_IC_POLARITY_BOTHEDGE
Return values:
None

Definition at line 2681 of file stm32wbxx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_IC_DisableXORCombination ( TIM_TypeDef * TIMx )

Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.

Note:
Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not a timer instance provides an XOR input.
Reference Manual to LL API cross reference:
CR2 TI1S LL_TIM_IC_DisableXORCombination
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 2944 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_IC_EnableXORCombination ( TIM_TypeDef * TIMx )

Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).

Note:
Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not a timer instance provides an XOR input.
Reference Manual to LL API cross reference:
CR2 TI1S LL_TIM_IC_EnableXORCombination
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 2931 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the current active input.

Reference Manual to LL API cross reference:
CCMR1 CC1S LL_TIM_IC_GetActiveInput
CCMR1 CC2S LL_TIM_IC_GetActiveInput
CCMR2 CC3S LL_TIM_IC_GetActiveInput
CCMR2 CC4S LL_TIM_IC_GetActiveInput
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Return values:
Returned value can be one of the following values:
  • LL_TIM_ACTIVEINPUT_DIRECTTI
  • LL_TIM_ACTIVEINPUT_INDIRECTTI
  • LL_TIM_ACTIVEINPUT_TRC

Definition at line 2733 of file stm32wbxx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1 ( TIM_TypeDef * TIMx )

Get captured value for input channel 1.

Note:
In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not input channel 1 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
Parameters:
TIMx Timer instance
Return values:
CapturedValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2973 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2 ( TIM_TypeDef * TIMx )

Get captured value for input channel 2.

Note:
In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not input channel 2 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
Parameters:
TIMx Timer instance
Return values:
CapturedValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2989 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3 ( TIM_TypeDef * TIMx )

Get captured value for input channel 3.

Note:
In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not input channel 3 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
Parameters:
TIMx Timer instance
Return values:
CapturedValue (between Min_Data=0 and Max_Data=65535)

Definition at line 3005 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4 ( TIM_TypeDef * TIMx )

Get captured value for input channel 4.

Note:
In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a 32 bits counter.
Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not input channel 4 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
Parameters:
TIMx Timer instance
Return values:
CapturedValue (between Min_Data=0 and Max_Data=65535)

Definition at line 3021 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the input filter duration.

Reference Manual to LL API cross reference:
CCMR1 IC1F LL_TIM_IC_GetFilter
CCMR1 IC2F LL_TIM_IC_GetFilter
CCMR2 IC3F LL_TIM_IC_GetFilter
CCMR2 IC4F LL_TIM_IC_GetFilter
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Return values:
Returned value can be one of the following values:
  • LL_TIM_IC_FILTER_FDIV1
  • LL_TIM_IC_FILTER_FDIV1_N2
  • LL_TIM_IC_FILTER_FDIV1_N4
  • LL_TIM_IC_FILTER_FDIV1_N8
  • LL_TIM_IC_FILTER_FDIV2_N6
  • LL_TIM_IC_FILTER_FDIV2_N8
  • LL_TIM_IC_FILTER_FDIV4_N6
  • LL_TIM_IC_FILTER_FDIV4_N8
  • LL_TIM_IC_FILTER_FDIV8_N6
  • LL_TIM_IC_FILTER_FDIV8_N8
  • LL_TIM_IC_FILTER_FDIV16_N5
  • LL_TIM_IC_FILTER_FDIV16_N6
  • LL_TIM_IC_FILTER_FDIV16_N8
  • LL_TIM_IC_FILTER_FDIV32_N5
  • LL_TIM_IC_FILTER_FDIV32_N6
  • LL_TIM_IC_FILTER_FDIV32_N8

Definition at line 2859 of file stm32wbxx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the current input channel polarity.

Reference Manual to LL API cross reference:
CCER CC1P LL_TIM_IC_GetPolarity
CCER CC1NP LL_TIM_IC_GetPolarity
CCER CC2P LL_TIM_IC_GetPolarity
CCER CC2NP LL_TIM_IC_GetPolarity
CCER CC3P LL_TIM_IC_GetPolarity
CCER CC3NP LL_TIM_IC_GetPolarity
CCER CC4P LL_TIM_IC_GetPolarity
CCER CC4NP LL_TIM_IC_GetPolarity
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Return values:
Returned value can be one of the following values:
  • LL_TIM_IC_POLARITY_RISING
  • LL_TIM_IC_POLARITY_FALLING
  • LL_TIM_IC_POLARITY_BOTHEDGE

Definition at line 2916 of file stm32wbxx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the current prescaler value acting on an input channel.

Reference Manual to LL API cross reference:
CCMR1 IC1PSC LL_TIM_IC_GetPrescaler
CCMR1 IC2PSC LL_TIM_IC_GetPrescaler
CCMR2 IC3PSC LL_TIM_IC_GetPrescaler
CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Return values:
Returned value can be one of the following values:
  • LL_TIM_ICPSC_DIV1
  • LL_TIM_ICPSC_DIV2
  • LL_TIM_ICPSC_DIV4
  • LL_TIM_ICPSC_DIV8

Definition at line 2784 of file stm32wbxx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination ( TIM_TypeDef * TIMx )

Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.

Note:
Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not a timer instance provides an XOR input.
Reference Manual to LL API cross reference:
CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 2957 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_IC_SetActiveInput | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ICActiveInput
 | ) |  |

Set the active input.

Reference Manual to LL API cross reference:
CCMR1 CC1S LL_TIM_IC_SetActiveInput
CCMR1 CC2S LL_TIM_IC_SetActiveInput
CCMR2 CC3S LL_TIM_IC_SetActiveInput
CCMR2 CC4S LL_TIM_IC_SetActiveInput
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
ICActiveInput This parameter can be one of the following values:
  • LL_TIM_ACTIVEINPUT_DIRECTTI
  • LL_TIM_ACTIVEINPUT_INDIRECTTI
  • LL_TIM_ACTIVEINPUT_TRC
Return values:
None

Definition at line 2709 of file stm32wbxx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_IC_SetFilter | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ICFilter
 | ) |  |

Set the input filter duration.

Reference Manual to LL API cross reference:
CCMR1 IC1F LL_TIM_IC_SetFilter
CCMR1 IC2F LL_TIM_IC_SetFilter
CCMR2 IC3F LL_TIM_IC_SetFilter
CCMR2 IC4F LL_TIM_IC_SetFilter
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
ICFilter This parameter can be one of the following values:
  • LL_TIM_IC_FILTER_FDIV1
  • LL_TIM_IC_FILTER_FDIV1_N2
  • LL_TIM_IC_FILTER_FDIV1_N4
  • LL_TIM_IC_FILTER_FDIV1_N8
  • LL_TIM_IC_FILTER_FDIV2_N6
  • LL_TIM_IC_FILTER_FDIV2_N8
  • LL_TIM_IC_FILTER_FDIV4_N6
  • LL_TIM_IC_FILTER_FDIV4_N8
  • LL_TIM_IC_FILTER_FDIV8_N6
  • LL_TIM_IC_FILTER_FDIV8_N8
  • LL_TIM_IC_FILTER_FDIV16_N5
  • LL_TIM_IC_FILTER_FDIV16_N6
  • LL_TIM_IC_FILTER_FDIV16_N8
  • LL_TIM_IC_FILTER_FDIV32_N5
  • LL_TIM_IC_FILTER_FDIV32_N6
  • LL_TIM_IC_FILTER_FDIV32_N8
Return values:
None

Definition at line 2822 of file stm32wbxx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_IC_SetPolarity | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ICPolarity
 | ) |  |

Set the input channel polarity.

Reference Manual to LL API cross reference:
CCER CC1P LL_TIM_IC_SetPolarity
CCER CC1NP LL_TIM_IC_SetPolarity
CCER CC2P LL_TIM_IC_SetPolarity
CCER CC2NP LL_TIM_IC_SetPolarity
CCER CC3P LL_TIM_IC_SetPolarity
CCER CC3NP LL_TIM_IC_SetPolarity
CCER CC4P LL_TIM_IC_SetPolarity
CCER CC4NP LL_TIM_IC_SetPolarity
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
ICPolarity This parameter can be one of the following values:
  • LL_TIM_IC_POLARITY_RISING
  • LL_TIM_IC_POLARITY_FALLING
  • LL_TIM_IC_POLARITY_BOTHEDGE
Return values:
None

Definition at line 2888 of file stm32wbxx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_IC_SetPrescaler | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ICPrescaler
 | ) |  |

Set the prescaler of input channel.

Reference Manual to LL API cross reference:
CCMR1 IC1PSC LL_TIM_IC_SetPrescaler
CCMR1 IC2PSC LL_TIM_IC_SetPrescaler
CCMR2 IC3PSC LL_TIM_IC_SetPrescaler
CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
ICPrescaler This parameter can be one of the following values:
  • LL_TIM_ICPSC_DIV1
  • LL_TIM_ICPSC_DIV2
  • LL_TIM_ICPSC_DIV4
  • LL_TIM_ICPSC_DIV8
Return values:
None

Definition at line 2759 of file stm32wbxx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Counter clock selection

Functions
Counter clock selection
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_EnableExternalClock (TIM_TypeDef *TIMx)
Enable external clock mode 2.
__STATIC_INLINE void | LL_TIM_DisableExternalClock (TIM_TypeDef *TIMx)
Disable external clock mode 2.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledExternalClock (TIM_TypeDef *TIMx)
Indicate whether external clock mode 2 is enabled.
__STATIC_INLINE void | LL_TIM_SetClockSource (TIM_TypeDef *TIMx, uint32_t ClockSource)
Set the clock source of the counter clock.
__STATIC_INLINE void | LL_TIM_SetEncoderMode (TIM_TypeDef *TIMx, uint32_t EncoderMode)
Set the encoder interface mode.

Function Documentation

__STATIC_INLINE void LL_TIM_DisableExternalClock ( TIM_TypeDef * TIMx )

Disable external clock mode 2.

Note:
Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check whether or not a timer instance supports external clock mode2.
Reference Manual to LL API cross reference:
SMCR ECE LL_TIM_DisableExternalClock
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3055 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableExternalClock ( TIM_TypeDef * TIMx )

Enable external clock mode 2.

Note:
When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check whether or not a timer instance supports external clock mode2.
Reference Manual to LL API cross reference:
SMCR ECE LL_TIM_EnableExternalClock
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3042 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock ( TIM_TypeDef * TIMx )

Indicate whether external clock mode 2 is enabled.

Note:
Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check whether or not a timer instance supports external clock mode2.
Reference Manual to LL API cross reference:
SMCR ECE LL_TIM_IsEnabledExternalClock
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3068 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetClockSource | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | ClockSource
 | ) |  |

Set the clock source of the counter clock.

Note:
when selected clock source is external clock mode 1, the timer input the external clock is applied is selected by calling the LL_TIM_SetTriggerInput() function. This timer input must be configured by calling the LL_TIM_IC_Config() function.
Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check whether or not a timer instance supports external clock mode1.
Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check whether or not a timer instance supports external clock mode2.
Reference Manual to LL API cross reference:
SMCR SMS LL_TIM_SetClockSource
SMCR ECE LL_TIM_SetClockSource
Parameters:
TIMx Timer instance
ClockSource This parameter can be one of the following values:
  • LL_TIM_CLOCKSOURCE_INTERNAL
  • LL_TIM_CLOCKSOURCE_EXT_MODE1
  • LL_TIM_CLOCKSOURCE_EXT_MODE2
Return values:
None

Definition at line 3092 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetEncoderMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | EncoderMode
 | ) |  |

Set the encoder interface mode.

Note:
Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check whether or not a timer instance supports the encoder mode.
Reference Manual to LL API cross reference:
SMCR SMS LL_TIM_SetEncoderMode
Parameters:
TIMx Timer instance
EncoderMode This parameter can be one of the following values:
  • LL_TIM_ENCODERMODE_X2_TI1
  • LL_TIM_ENCODERMODE_X2_TI2
  • LL_TIM_ENCODERMODE_X4_TI12
Return values:
None

Definition at line 3109 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init().

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Timer synchronisation configuration

Functions
Timer synchronisation configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_SetTriggerOutput (TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
Set the trigger output (TRGO) used for timer synchronization .
__STATIC_INLINE void | LL_TIM_SetTriggerOutput2 (TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
Set the trigger output 2 (TRGO2) used for ADC synchronization .
__STATIC_INLINE void | LL_TIM_SetSlaveMode (TIM_TypeDef *TIMx, uint32_t SlaveMode)
Set the synchronization mode of a slave timer.
__STATIC_INLINE void | LL_TIM_SetTriggerInput (TIM_TypeDef *TIMx, uint32_t TriggerInput)
Set the selects the trigger input to be used to synchronize the counter.
__STATIC_INLINE void | LL_TIM_EnableMasterSlaveMode (TIM_TypeDef *TIMx)
Enable the Master/Slave mode.
__STATIC_INLINE void | LL_TIM_DisableMasterSlaveMode (TIM_TypeDef *TIMx)
Disable the Master/Slave mode.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledMasterSlaveMode (TIM_TypeDef *TIMx)
Indicates whether the Master/Slave mode is enabled.
__STATIC_INLINE void | LL_TIM_ConfigETR (TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, uint32_t ETRFilter)
Configure the external trigger (ETR) input.
__STATIC_INLINE void | LL_TIM_SetETRSource (TIM_TypeDef *TIMx, uint32_t ETRSource)
Select the external trigger (ETR) input source.

Function Documentation

__STATIC_INLINE void LL_TIM_ConfigETR | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | ETRPolarity,
 |  | uint32_t | ETRPrescaler,
 |  | uint32_t | ETRFilter
 | ) |  |

Configure the external trigger (ETR) input.

Note:
Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not a timer instance provides an external trigger input.
Reference Manual to LL API cross reference:
SMCR ETP LL_TIM_ConfigETR
SMCR ETPS LL_TIM_ConfigETR
SMCR ETF LL_TIM_ConfigETR
Parameters:
TIMx Timer instance
ETRPolarity This parameter can be one of the following values:
  • LL_TIM_ETR_POLARITY_NONINVERTED
  • LL_TIM_ETR_POLARITY_INVERTED
ETRPrescaler This parameter can be one of the following values:
  • LL_TIM_ETR_PRESCALER_DIV1
  • LL_TIM_ETR_PRESCALER_DIV2
  • LL_TIM_ETR_PRESCALER_DIV4
  • LL_TIM_ETR_PRESCALER_DIV8
ETRFilter This parameter can be one of the following values:
  • LL_TIM_ETR_FILTER_FDIV1
  • LL_TIM_ETR_FILTER_FDIV1_N2
  • LL_TIM_ETR_FILTER_FDIV1_N4
  • LL_TIM_ETR_FILTER_FDIV1_N8
  • LL_TIM_ETR_FILTER_FDIV2_N6
  • LL_TIM_ETR_FILTER_FDIV2_N8
  • LL_TIM_ETR_FILTER_FDIV4_N6
  • LL_TIM_ETR_FILTER_FDIV4_N8
  • LL_TIM_ETR_FILTER_FDIV8_N6
  • LL_TIM_ETR_FILTER_FDIV8_N8
  • LL_TIM_ETR_FILTER_FDIV16_N5
  • LL_TIM_ETR_FILTER_FDIV16_N6
  • LL_TIM_ETR_FILTER_FDIV16_N8
  • LL_TIM_ETR_FILTER_FDIV32_N5
  • LL_TIM_ETR_FILTER_FDIV32_N6
  • LL_TIM_ETR_FILTER_FDIV32_N8
Return values:
None

Definition at line 3288 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode ( TIM_TypeDef * TIMx )

Disable the Master/Slave mode.

Note:
Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a slave timer.
Reference Manual to LL API cross reference:
SMCR MSM LL_TIM_DisableMasterSlaveMode
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3235 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode ( TIM_TypeDef * TIMx )

Enable the Master/Slave mode.

Note:
Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a slave timer.
Reference Manual to LL API cross reference:
SMCR MSM LL_TIM_EnableMasterSlaveMode
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3222 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode ( TIM_TypeDef * TIMx )

Indicates whether the Master/Slave mode is enabled.

Note:
Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a slave timer.
Reference Manual to LL API cross reference:
SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3248 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetETRSource | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | ETRSource
 | ) |  |

Select the external trigger (ETR) input source.

Note:
Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or not a timer instance supports ETR source selection.
When this function is called with LL_TIM_ETRSOURCE_GPIO, LL_TIM_ETRSOURCE_ADC1_AWD1, LL_TIM_ETRSOURCE_ADC1_AWD2 or LL_TIM_ETRSOURCE_ADC1_AWD3, ETR source relies on TIMx ETR remapping capability configured through the function LL_TIM_SetRemap().
Reference Manual to LL API cross reference:
AF1 ETRSEL LL_TIM_SetETRSource
Parameters:
TIMx Timer instance
ETRSource This parameter can be one of the following values:
  • LL_TIM_ETRSOURCE_GPIO
  • LL_TIM_ETRSOURCE_ADC1_AWD1
  • LL_TIM_ETRSOURCE_ADC1_AWD2
  • LL_TIM_ETRSOURCE_ADC1_AWD3
  • LL_TIM_ETRSOURCE_COMP1
  • LL_TIM_ETRSOURCE_COMP2
Return values:
None

Definition at line 3313 of file stm32wbxx_ll_tim.h.

References TIMx_AF1_ETRSEL.

__STATIC_INLINE void LL_TIM_SetSlaveMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | SlaveMode
 | ) |  |

Set the synchronization mode of a slave timer.

Note:
Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a slave timer.
Reference Manual to LL API cross reference:
SMCR SMS LL_TIM_SetSlaveMode
Parameters:
TIMx Timer instance
SlaveMode This parameter can be one of the following values:
  • LL_TIM_SLAVEMODE_DISABLED
  • LL_TIM_SLAVEMODE_RESET
  • LL_TIM_SLAVEMODE_GATED
  • LL_TIM_SLAVEMODE_TRIGGER
  • LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
Return values:
None

Definition at line 3187 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetTriggerInput | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TriggerInput
 | ) |  |

Set the selects the trigger input to be used to synchronize the counter.

Note:
Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a slave timer.
Reference Manual to LL API cross reference:
SMCR TS LL_TIM_SetTriggerInput
Parameters:
TIMx Timer instance
TriggerInput This parameter can be one of the following values:
  • LL_TIM_TS_ITR0
  • LL_TIM_TS_ITR1
  • LL_TIM_TS_ITR2
  • LL_TIM_TS_ITR3
  • LL_TIM_TS_TI1F_ED
  • LL_TIM_TS_TI1FP1
  • LL_TIM_TS_TI2FP2
  • LL_TIM_TS_ETRF
Return values:
None

Definition at line 3209 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetTriggerOutput | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TimerSynchronization
 | ) |  |

Set the trigger output (TRGO) used for timer synchronization .

Note:
Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a master timer.
Reference Manual to LL API cross reference:
CR2 MMS LL_TIM_SetTriggerOutput
Parameters:
TIMx Timer instance
TimerSynchronization This parameter can be one of the following values:
  • LL_TIM_TRGO_RESET
  • LL_TIM_TRGO_ENABLE
  • LL_TIM_TRGO_UPDATE
  • LL_TIM_TRGO_CC1IF
  • LL_TIM_TRGO_OC1REF
  • LL_TIM_TRGO_OC2REF
  • LL_TIM_TRGO_OC3REF
  • LL_TIM_TRGO_OC4REF
Return values:
None

Definition at line 3138 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetTriggerOutput2 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | ADCSynchronization
 | ) |  |

Set the trigger output 2 (TRGO2) used for ADC synchronization .

Note:
Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check whether or not a timer instance can be used for ADC synchronization.
Reference Manual to LL API cross reference:
CR2 MMS2 LL_TIM_SetTriggerOutput2
Parameters:
TIMx Timer Instance
ADCSynchronization This parameter can be one of the following values:
  • LL_TIM_TRGO2_RESET
  • LL_TIM_TRGO2_ENABLE
  • LL_TIM_TRGO2_UPDATE
  • LL_TIM_TRGO2_CC1F
  • LL_TIM_TRGO2_OC1
  • LL_TIM_TRGO2_OC2
  • LL_TIM_TRGO2_OC3
  • LL_TIM_TRGO2_OC4
  • LL_TIM_TRGO2_OC5
  • LL_TIM_TRGO2_OC6
  • LL_TIM_TRGO2_OC4_RISINGFALLING
  • LL_TIM_TRGO2_OC6_RISINGFALLING
  • LL_TIM_TRGO2_OC4_RISING_OC6_RISING
  • LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
  • LL_TIM_TRGO2_OC5_RISING_OC6_RISING
  • LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
Return values:
None

Definition at line 3168 of file stm32wbxx_ll_tim.h.

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Break function configuration

Functions
Break function configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_EnableBRK (TIM_TypeDef *TIMx)
Enable the break function.
__STATIC_INLINE void | LL_TIM_DisableBRK (TIM_TypeDef *TIMx)
Disable the break function.
__STATIC_INLINE void | LL_TIM_ConfigBRK (TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter)
Configure the break input.
__STATIC_INLINE void | LL_TIM_EnableBRK2 (TIM_TypeDef *TIMx)
Enable the break 2 function.
__STATIC_INLINE void | LL_TIM_DisableBRK2 (TIM_TypeDef *TIMx)
Disable the break 2 function.
__STATIC_INLINE void | LL_TIM_ConfigBRK2 (TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
Configure the break 2 input.
__STATIC_INLINE void | LL_TIM_SetOffStates (TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
Select the outputs off state (enabled v.s.
__STATIC_INLINE void | LL_TIM_EnableAutomaticOutput (TIM_TypeDef *TIMx)
Enable automatic output (MOE can be set by software or automatically when a break input is active).
__STATIC_INLINE void | LL_TIM_DisableAutomaticOutput (TIM_TypeDef *TIMx)
Disable automatic output (MOE can be set only by software).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledAutomaticOutput (TIM_TypeDef *TIMx)
Indicate whether automatic output is enabled.
__STATIC_INLINE void | LL_TIM_EnableAllOutputs (TIM_TypeDef *TIMx)
Enable the outputs (set the MOE bit in TIMx_BDTR register).
__STATIC_INLINE void | LL_TIM_DisableAllOutputs (TIM_TypeDef *TIMx)
Disable the outputs (reset the MOE bit in TIMx_BDTR register).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledAllOutputs (TIM_TypeDef *TIMx)
Indicates whether outputs are enabled.
__STATIC_INLINE void | LL_TIM_EnableBreakInputSource (TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
Enable the signals connected to the designated timer break input.
__STATIC_INLINE void | LL_TIM_DisableBreakInputSource (TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
Disable the signals connected to the designated timer break input.
__STATIC_INLINE void | LL_TIM_SetBreakInputSourcePolarity (TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source, uint32_t Polarity)
Set the polarity of the break signal for the timer break input.

Function Documentation

__STATIC_INLINE void LL_TIM_ConfigBRK | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | BreakPolarity,
 |  | uint32_t | BreakFilter
 | ) |  |

Configure the break input.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR BKP LL_TIM_ConfigBRK
BDTR BKF LL_TIM_ConfigBRK
Parameters:
TIMx Timer instance
BreakPolarity This parameter can be one of the following values:
  • LL_TIM_BREAK_POLARITY_LOW
  • LL_TIM_BREAK_POLARITY_HIGH
BreakFilter This parameter can be one of the following values:
  • LL_TIM_BREAK_FILTER_FDIV1
  • LL_TIM_BREAK_FILTER_FDIV1_N2
  • LL_TIM_BREAK_FILTER_FDIV1_N4
  • LL_TIM_BREAK_FILTER_FDIV1_N8
  • LL_TIM_BREAK_FILTER_FDIV2_N6
  • LL_TIM_BREAK_FILTER_FDIV2_N8
  • LL_TIM_BREAK_FILTER_FDIV4_N6
  • LL_TIM_BREAK_FILTER_FDIV4_N8
  • LL_TIM_BREAK_FILTER_FDIV8_N6
  • LL_TIM_BREAK_FILTER_FDIV8_N8
  • LL_TIM_BREAK_FILTER_FDIV16_N5
  • LL_TIM_BREAK_FILTER_FDIV16_N6
  • LL_TIM_BREAK_FILTER_FDIV16_N8
  • LL_TIM_BREAK_FILTER_FDIV32_N5
  • LL_TIM_BREAK_FILTER_FDIV32_N6
  • LL_TIM_BREAK_FILTER_FDIV32_N8
Return values:
None

Definition at line 3381 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ConfigBRK2 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Break2Polarity,
 |  | uint32_t | Break2Filter
 | ) |  |

Configure the break 2 input.

Note:
Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a second break input.
Reference Manual to LL API cross reference:
BDTR BK2P LL_TIM_ConfigBRK2
BDTR BK2F LL_TIM_ConfigBRK2
Parameters:
TIMx Timer instance
Break2Polarity This parameter can be one of the following values:
  • LL_TIM_BREAK2_POLARITY_LOW
  • LL_TIM_BREAK2_POLARITY_HIGH
Break2Filter This parameter can be one of the following values:
  • LL_TIM_BREAK2_FILTER_FDIV1
  • LL_TIM_BREAK2_FILTER_FDIV1_N2
  • LL_TIM_BREAK2_FILTER_FDIV1_N4
  • LL_TIM_BREAK2_FILTER_FDIV1_N8
  • LL_TIM_BREAK2_FILTER_FDIV2_N6
  • LL_TIM_BREAK2_FILTER_FDIV2_N8
  • LL_TIM_BREAK2_FILTER_FDIV4_N6
  • LL_TIM_BREAK2_FILTER_FDIV4_N8
  • LL_TIM_BREAK2_FILTER_FDIV8_N6
  • LL_TIM_BREAK2_FILTER_FDIV8_N8
  • LL_TIM_BREAK2_FILTER_FDIV16_N5
  • LL_TIM_BREAK2_FILTER_FDIV16_N6
  • LL_TIM_BREAK2_FILTER_FDIV16_N8
  • LL_TIM_BREAK2_FILTER_FDIV32_N5
  • LL_TIM_BREAK2_FILTER_FDIV32_N6
  • LL_TIM_BREAK2_FILTER_FDIV32_N8
Return values:
None

Definition at line 3442 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableAllOutputs ( TIM_TypeDef * TIMx )

Disable the outputs (reset the MOE bit in TIMx_BDTR register).

Note:
The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by software and is reset in case of break or break2 event.
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR MOE LL_TIM_DisableAllOutputs
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3531 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableAutomaticOutput ( TIM_TypeDef * TIMx )

Disable automatic output (MOE can be set only by software).

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR AOE LL_TIM_DisableAutomaticOutput
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3488 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableBreakInputSource | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | BreakInput,
 |  | uint32_t | Source
 | ) |  |

Disable the signals connected to the designated timer break input.

Note:
Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether or not a timer instance allows for break input selection.
Reference Manual to LL API cross reference:
AF1 BKINE LL_TIM_DisableBreakInputSource
AF1 BKCMP1E LL_TIM_DisableBreakInputSource
AF1 BKCMP2E LL_TIM_DisableBreakInputSource
AF2 BK2INE LL_TIM_DisableBreakInputSource
AF2 BK2CMP1E LL_TIM_DisableBreakInputSource
AF2 BK2CMP2E LL_TIM_DisableBreakInputSource
Parameters:
TIMx Timer instance
BreakInput This parameter can be one of the following values:
  • LL_TIM_BREAK_INPUT_BKIN
  • LL_TIM_BREAK_INPUT_BKIN2
Source This parameter can be one of the following values:
  • LL_TIM_BKIN_SOURCE_BKIN
  • LL_TIM_BKIN_SOURCE_BKCOMP1 (*)
  • LL_TIM_BKIN_SOURCE_BKCOMP2 (*)
(*) Value not defined in all devices.
Return values:
None

Definition at line 3599 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableBRK ( TIM_TypeDef * TIMx )

Disable the break function.

Reference Manual to LL API cross reference:
BDTR BKE LL_TIM_DisableBRK
Parameters:
TIMx Timer instance
Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Return values:
None

Definition at line 3347 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableBRK2 ( TIM_TypeDef * TIMx )

Disable the break 2 function.

Note:
Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a second break input.
Reference Manual to LL API cross reference:
BDTR BK2E LL_TIM_DisableBRK2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3408 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableAllOutputs ( TIM_TypeDef * TIMx )

Enable the outputs (set the MOE bit in TIMx_BDTR register).

Note:
The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by software and is reset in case of break or break2 event
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR MOE LL_TIM_EnableAllOutputs
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3516 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableAutomaticOutput ( TIM_TypeDef * TIMx )

Enable automatic output (MOE can be set by software or automatically when a break input is active).

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR AOE LL_TIM_EnableAutomaticOutput
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3475 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableBreakInputSource | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | BreakInput,
 |  | uint32_t | Source
 | ) |  |

Enable the signals connected to the designated timer break input.

Note:
Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether or not a timer instance allows for break input selection.
Reference Manual to LL API cross reference:
AF1 BKINE LL_TIM_EnableBreakInputSource
AF1 BKCMP1E LL_TIM_EnableBreakInputSource
AF1 BKCMP2E LL_TIM_EnableBreakInputSource
AF2 BK2INE LL_TIM_EnableBreakInputSource
AF2 BK2CMP1E LL_TIM_EnableBreakInputSource
AF2 BK2CMP2E LL_TIM_EnableBreakInputSource
Parameters:
TIMx Timer instance
BreakInput This parameter can be one of the following values:
  • LL_TIM_BREAK_INPUT_BKIN
  • LL_TIM_BREAK_INPUT_BKIN2
Source This parameter can be one of the following values:
  • LL_TIM_BKIN_SOURCE_BKIN
  • LL_TIM_BKIN_SOURCE_BKCOMP1 (*)
  • LL_TIM_BKIN_SOURCE_BKCOMP2 (*)
(*) Value not defined in all devices.
Return values:
None

Definition at line 3571 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableBRK ( TIM_TypeDef * TIMx )

Enable the break function.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR BKE LL_TIM_EnableBRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3334 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableBRK2 ( TIM_TypeDef * TIMx )

Enable the break 2 function.

Note:
Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a second break input.
Reference Manual to LL API cross reference:
BDTR BK2E LL_TIM_EnableBRK2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3395 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs ( TIM_TypeDef * TIMx )

Indicates whether outputs are enabled.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR MOE LL_TIM_IsEnabledAllOutputs
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3544 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput ( TIM_TypeDef * TIMx )

Indicate whether automatic output is enabled.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR AOE LL_TIM_IsEnabledAutomaticOutput
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3501 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | BreakInput,
 |  | uint32_t | Source,
 |  | uint32_t | Polarity
 | ) |  |

Set the polarity of the break signal for the timer break input.

Note:
Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether or not a timer instance allows for break input selection.
Reference Manual to LL API cross reference:
AF1 BKINP LL_TIM_SetBreakInputSourcePolarity
AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity
AF1 BKCMP2P LL_TIM_SetBreakInputSourcePolarity
AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity
AF2 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity
AF2 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity
Parameters:
TIMx Timer instance
BreakInput This parameter can be one of the following values:
  • LL_TIM_BREAK_INPUT_BKIN
  • LL_TIM_BREAK_INPUT_BKIN2
Source This parameter can be one of the following values:
  • LL_TIM_BKIN_SOURCE_BKIN
  • LL_TIM_BKIN_SOURCE_BKCOMP1 (*)
  • LL_TIM_BKIN_SOURCE_BKCOMP2 (*)
Polarity This parameter can be one of the following values:
  • LL_TIM_BKIN_POLARITY_LOW
  • LL_TIM_BKIN_POLARITY_HIGH
(*) Value not defined in all devices.
Return values:
None

Definition at line 3630 of file stm32wbxx_ll_tim.h.

References TIM_POSITION_BRK_SOURCE, and TIMx_AF1_BKINP.

__STATIC_INLINE void LL_TIM_SetOffStates | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | OffStateIdle,
 |  | uint32_t | OffStateRun
 | ) |  |

Select the outputs off state (enabled v.s.

disabled) in Idle and Run modes.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR OSSI LL_TIM_SetOffStates
BDTR OSSR LL_TIM_SetOffStates
Parameters:
TIMx Timer instance
OffStateIdle This parameter can be one of the following values:
  • LL_TIM_OSSI_DISABLE
  • LL_TIM_OSSI_ENABLE
OffStateRun This parameter can be one of the following values:
  • LL_TIM_OSSR_DISABLE
  • LL_TIM_OSSR_ENABLE
Return values:
None

Definition at line 3462 of file stm32wbxx_ll_tim.h.

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DMA burst mode configuration

Functions
DMA burst mode configuration
TIM Exported Functions

Functions

__STATIC_INLINE void LL_TIM_ConfigDMABurst (TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
Configures the timer DMA burst feature.

Function Documentation

__STATIC_INLINE void LL_TIM_ConfigDMABurst | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | DMABurstBaseAddress,
 |  | uint32_t | DMABurstLength
 | ) |  |

Configures the timer DMA burst feature.

Note:
Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or not a timer instance supports the DMA burst mode.
Reference Manual to LL API cross reference:
DCR DBL LL_TIM_ConfigDMABurst
DCR DBA LL_TIM_ConfigDMABurst
Parameters:
TIMx Timer instance
DMABurstBaseAddress This parameter can be one of the following values:
  • LL_TIM_DMABURST_BASEADDR_CR1
  • LL_TIM_DMABURST_BASEADDR_CR2
  • LL_TIM_DMABURST_BASEADDR_SMCR
  • LL_TIM_DMABURST_BASEADDR_DIER
  • LL_TIM_DMABURST_BASEADDR_SR
  • LL_TIM_DMABURST_BASEADDR_EGR
  • LL_TIM_DMABURST_BASEADDR_CCMR1
  • LL_TIM_DMABURST_BASEADDR_CCMR2
  • LL_TIM_DMABURST_BASEADDR_CCER
  • LL_TIM_DMABURST_BASEADDR_CNT
  • LL_TIM_DMABURST_BASEADDR_PSC
  • LL_TIM_DMABURST_BASEADDR_ARR
  • LL_TIM_DMABURST_BASEADDR_RCR
  • LL_TIM_DMABURST_BASEADDR_CCR1
  • LL_TIM_DMABURST_BASEADDR_CCR2
  • LL_TIM_DMABURST_BASEADDR_CCR3
  • LL_TIM_DMABURST_BASEADDR_CCR4
  • LL_TIM_DMABURST_BASEADDR_BDTR
  • LL_TIM_DMABURST_BASEADDR_OR
  • LL_TIM_DMABURST_BASEADDR_CCMR3
  • LL_TIM_DMABURST_BASEADDR_CCR5
  • LL_TIM_DMABURST_BASEADDR_CCR6
  • LL_TIM_DMABURST_BASEADDR_AF1
  • LL_TIM_DMABURST_BASEADDR_AF2
DMABurstLength This parameter can be one of the following values:
  • LL_TIM_DMABURST_LENGTH_1TRANSFER
  • LL_TIM_DMABURST_LENGTH_2TRANSFERS
  • LL_TIM_DMABURST_LENGTH_3TRANSFERS
  • LL_TIM_DMABURST_LENGTH_4TRANSFERS
  • LL_TIM_DMABURST_LENGTH_5TRANSFERS
  • LL_TIM_DMABURST_LENGTH_6TRANSFERS
  • LL_TIM_DMABURST_LENGTH_7TRANSFERS
  • LL_TIM_DMABURST_LENGTH_8TRANSFERS
  • LL_TIM_DMABURST_LENGTH_9TRANSFERS
  • LL_TIM_DMABURST_LENGTH_10TRANSFERS
  • LL_TIM_DMABURST_LENGTH_11TRANSFERS
  • LL_TIM_DMABURST_LENGTH_12TRANSFERS
  • LL_TIM_DMABURST_LENGTH_13TRANSFERS
  • LL_TIM_DMABURST_LENGTH_14TRANSFERS
  • LL_TIM_DMABURST_LENGTH_15TRANSFERS
  • LL_TIM_DMABURST_LENGTH_16TRANSFERS
  • LL_TIM_DMABURST_LENGTH_17TRANSFERS
  • LL_TIM_DMABURST_LENGTH_18TRANSFERS
Return values:
None

Definition at line 3696 of file stm32wbxx_ll_tim.h.

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Timer input remapping

Functions
Timer input remapping
TIM Exported Functions

Functions

__STATIC_INLINE void LL_TIM_SetRemap (TIM_TypeDef *TIMx, uint32_t Remap)
Remap TIM inputs (input channel, internal/external triggers).

Function Documentation

__STATIC_INLINE void LL_TIM_SetRemap | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Remap
 | ) |  |

Remap TIM inputs (input channel, internal/external triggers).

Note:
Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not a some timer inputs can be remapped.
Reference Manual to LL API cross reference:
TIM1_OR ETR_ADC1_RMP LL_TIM_SetRemap
TIM1_OR TI1_RMP LL_TIM_SetRemap
TIM2_OR ITR1_RMP LL_TIM_SetRemap
TIM2_OR TI4_RMP LL_TIM_SetRemap
TIM2_OR TI1_RMP LL_TIM_SetRemap
TIM16_OR TI1_RMP LL_TIM_SetRemap
TIM17_OR TI1_RMP LL_TIM_SetRemap
Parameters:
TIMx | Timer instance
Remap | Remap param depends on the TIMx. Description available only in CHM version of the User Manual (not in .pdf). Otherwise see Reference Manual description of OR registers.

Below description summarizes "Timer Instance" and "Remap" param combinations:

TIM1: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where

. . ADC1_RMP can be one of the following values

  • LL_TIM_TIM1_ETR_ADC1_RMP_NC
  • LL_TIM_TIM1_ETR_ADC1_RMP_AWD1
  • LL_TIM_TIM1_ETR_ADC1_RMP_AWD2
  • LL_TIM_TIM1_ETR_ADC1_RMP_AWD3

. . TI1_RMP can be one of the following values

  • LL_TIM_TIM1_TI1_RMP_GPIO
  • LL_TIM_TIM1_TI1_RMP_COMP1 (*)

TIM2: any combination of ITR1_RMP, ETR1_RMP, TI4_RMP where

ITR1_RMP can be one of the following values

  • LL_TIM_TIM2_ITR1_RMP_NONE
  • LL_TIM_TIM2_ITR1_RMP_USB_SOF (*)

. . ETR1_RMP can be one of the following values

  • LL_TIM_TIM2_ETR_RMP_GPIO
  • LL_TIM_TIM2_ETR_RMP_LSE

. . TI4_RMP can be one of the following values

  • LL_TIM_TIM2_TI4_RMP_GPIO
  • LL_TIM_TIM2_TI4_RMP_COMP1 (*)
  • LL_TIM_TIM2_TI4_RMP_COMP2 (*)
  • LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (*)

TIM16: one of the following values

  • LL_TIM_TIM16_TI1_RMP_GPIO
  • LL_TIM_TIM16_TI1_RMP_LSI
  • LL_TIM_TIM16_TI1_RMP_LSE
  • LL_TIM_TIM16_TI1_RMP_RTC

TIM17: one of the following values

  • LL_TIM_TIM17_TI1_RMP_GPIO
  • LL_TIM_TIM17_TI1_RMP_MSI
  • LL_TIM_TIM17_TI1_RMP_HSE_32
  • LL_TIM_TIM17_TI1_RMP_MCO

(*) Value not defined in all devices.

Return values:
None

Definition at line 3771 of file stm32wbxx_ll_tim.h.

References TIMx_OR_RMP_MASK, and TIMx_OR_RMP_SHIFT.

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: OCREF_Clear_Management

Functions
OCREF_Clear_Management
TIM Exported Functions

Functions

__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource (TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
Set the OCREF clear input source.

Function Documentation

__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | OCRefClearInputSource
 | ) |  |

Set the OCREF clear input source.

Note:
The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
This function can only be used in Output compare and PWM modes.
Reference Manual to LL API cross reference:
SMCR OCCS LL_TIM_SetOCRefClearInputSource
Parameters:
TIMx Timer instance
OCRefClearInputSource This parameter can be one of the following values:
  • LL_TIM_OCREF_CLR_INT_OCREF_CLR
  • LL_TIM_OCREF_CLR_INT_ETR
Return values:
None

Definition at line 3794 of file stm32wbxx_ll_tim.h.

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FLAG-Management

Functions
FLAG-Management
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_ClearFlag_UPDATE (TIM_TypeDef *TIMx)
Clear the update interrupt flag (UIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_UPDATE (TIM_TypeDef *TIMx)
Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC1 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 1 interrupt flag (CC1F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC1 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC2 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 2 interrupt flag (CC2F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC2 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC3 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 3 interrupt flag (CC3F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC3 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC4 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 4 interrupt flag (CC4F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC4 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC5 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 5 interrupt flag (CC5F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC5 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC6 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 6 interrupt flag (CC6F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC6 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_COM (TIM_TypeDef *TIMx)
Clear the commutation interrupt flag (COMIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_COM (TIM_TypeDef *TIMx)
Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_TRIG (TIM_TypeDef *TIMx)
Clear the trigger interrupt flag (TIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_TRIG (TIM_TypeDef *TIMx)
Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_BRK (TIM_TypeDef *TIMx)
Clear the break interrupt flag (BIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_BRK (TIM_TypeDef *TIMx)
Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_BRK2 (TIM_TypeDef *TIMx)
Clear the break 2 interrupt flag (B2IF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_BRK2 (TIM_TypeDef *TIMx)
Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC1OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC1OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC2OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC2OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC3OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC3OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC4OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC4OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_SYSBRK (TIM_TypeDef *TIMx)
Clear the system break interrupt flag (SBIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_SYSBRK (TIM_TypeDef *TIMx)
Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).

Function Documentation

__STATIC_INLINE void LL_TIM_ClearFlag_BRK ( TIM_TypeDef * TIMx )

Clear the break interrupt flag (BIF).

Reference Manual to LL API cross reference:
SR BIF LL_TIM_ClearFlag_BRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4009 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_BRK2 ( TIM_TypeDef * TIMx )

Clear the break 2 interrupt flag (B2IF).

Reference Manual to LL API cross reference:
SR B2IF LL_TIM_ClearFlag_BRK2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4031 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC1 ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 1 interrupt flag (CC1F).

Reference Manual to LL API cross reference:
SR CC1IF LL_TIM_ClearFlag_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3833 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).

Reference Manual to LL API cross reference:
SR CC1OF LL_TIM_ClearFlag_CC1OVR
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4053 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC2 ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 2 interrupt flag (CC2F).

Reference Manual to LL API cross reference:
SR CC2IF LL_TIM_ClearFlag_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3855 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).

Reference Manual to LL API cross reference:
SR CC2OF LL_TIM_ClearFlag_CC2OVR
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4075 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC3 ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 3 interrupt flag (CC3F).

Reference Manual to LL API cross reference:
SR CC3IF LL_TIM_ClearFlag_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3877 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).

Reference Manual to LL API cross reference:
SR CC3OF LL_TIM_ClearFlag_CC3OVR
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4097 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC4 ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 4 interrupt flag (CC4F).

Reference Manual to LL API cross reference:
SR CC4IF LL_TIM_ClearFlag_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3899 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).

Reference Manual to LL API cross reference:
SR CC4OF LL_TIM_ClearFlag_CC4OVR
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4119 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC5 ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 5 interrupt flag (CC5F).

Reference Manual to LL API cross reference:
SR CC5IF LL_TIM_ClearFlag_CC5
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3921 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC6 ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 6 interrupt flag (CC6F).

Reference Manual to LL API cross reference:
SR CC6IF LL_TIM_ClearFlag_CC6
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3943 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_COM ( TIM_TypeDef * TIMx )

Clear the commutation interrupt flag (COMIF).

Reference Manual to LL API cross reference:
SR COMIF LL_TIM_ClearFlag_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3965 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK ( TIM_TypeDef * TIMx )

Clear the system break interrupt flag (SBIF).

Reference Manual to LL API cross reference:
SR SBIF LL_TIM_ClearFlag_SYSBRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4141 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_TRIG ( TIM_TypeDef * TIMx )

Clear the trigger interrupt flag (TIF).

Reference Manual to LL API cross reference:
SR TIF LL_TIM_ClearFlag_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3987 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE ( TIM_TypeDef * TIMx )

Clear the update interrupt flag (UIF).

Reference Manual to LL API cross reference:
SR UIF LL_TIM_ClearFlag_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3811 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK ( TIM_TypeDef * TIMx )

Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).

Reference Manual to LL API cross reference:
SR BIF LL_TIM_IsActiveFlag_BRK
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4020 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2 ( TIM_TypeDef * TIMx )

Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).

Reference Manual to LL API cross reference:
SR B2IF LL_TIM_IsActiveFlag_BRK2
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4042 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1 ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC1IF LL_TIM_IsActiveFlag_CC1
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3844 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4064 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2 ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC2IF LL_TIM_IsActiveFlag_CC2
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3866 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).

Reference Manual to LL API cross reference:
SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4086 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3 ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC3IF LL_TIM_IsActiveFlag_CC3
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3888 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).

Reference Manual to LL API cross reference:
SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4108 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4 ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC4IF LL_TIM_IsActiveFlag_CC4
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3910 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).

Reference Manual to LL API cross reference:
SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4130 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5 ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC5IF LL_TIM_IsActiveFlag_CC5
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3932 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6 ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC6IF LL_TIM_IsActiveFlag_CC6
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3954 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM ( TIM_TypeDef * TIMx )

Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).

Reference Manual to LL API cross reference:
SR COMIF LL_TIM_IsActiveFlag_COM
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3976 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK ( TIM_TypeDef * TIMx )

Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).

Reference Manual to LL API cross reference:
SR SBIF LL_TIM_IsActiveFlag_SYSBRK
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4152 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG ( TIM_TypeDef * TIMx )

Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).

Reference Manual to LL API cross reference:
SR TIF LL_TIM_IsActiveFlag_TRIG
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3998 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE ( TIM_TypeDef * TIMx )

Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).

Reference Manual to LL API cross reference:
SR UIF LL_TIM_IsActiveFlag_UPDATE
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3822 of file stm32wbxx_ll_tim.h.

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IT-Management

Functions
IT-Management
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_EnableIT_UPDATE (TIM_TypeDef *TIMx)
Enable update interrupt (UIE).
__STATIC_INLINE void | LL_TIM_DisableIT_UPDATE (TIM_TypeDef *TIMx)
Disable update interrupt (UIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_UPDATE (TIM_TypeDef *TIMx)
Indicates whether the update interrupt (UIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC1 (TIM_TypeDef *TIMx)
Enable capture/compare 1 interrupt (CC1IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC1 (TIM_TypeDef *TIMx)
Disable capture/compare 1 interrupt (CC1IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC1 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC2 (TIM_TypeDef *TIMx)
Enable capture/compare 2 interrupt (CC2IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC2 (TIM_TypeDef *TIMx)
Disable capture/compare 2 interrupt (CC2IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC2 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC3 (TIM_TypeDef *TIMx)
Enable capture/compare 3 interrupt (CC3IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC3 (TIM_TypeDef *TIMx)
Disable capture/compare 3 interrupt (CC3IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC3 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC4 (TIM_TypeDef *TIMx)
Enable capture/compare 4 interrupt (CC4IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC4 (TIM_TypeDef *TIMx)
Disable capture/compare 4 interrupt (CC4IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC4 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_COM (TIM_TypeDef *TIMx)
Enable commutation interrupt (COMIE).
__STATIC_INLINE void | LL_TIM_DisableIT_COM (TIM_TypeDef *TIMx)
Disable commutation interrupt (COMIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_COM (TIM_TypeDef *TIMx)
Indicates whether the commutation interrupt (COMIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_TRIG (TIM_TypeDef *TIMx)
Enable trigger interrupt (TIE).
__STATIC_INLINE void | LL_TIM_DisableIT_TRIG (TIM_TypeDef *TIMx)
Disable trigger interrupt (TIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_TRIG (TIM_TypeDef *TIMx)
Indicates whether the trigger interrupt (TIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_BRK (TIM_TypeDef *TIMx)
Enable break interrupt (BIE).
__STATIC_INLINE void | LL_TIM_DisableIT_BRK (TIM_TypeDef *TIMx)
Disable break interrupt (BIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_BRK (TIM_TypeDef *TIMx)
Indicates whether the break interrupt (BIE) is enabled.

Function Documentation

__STATIC_INLINE void LL_TIM_DisableIT_BRK ( TIM_TypeDef * TIMx )

Disable break interrupt (BIE).

Reference Manual to LL API cross reference:
DIER BIE LL_TIM_DisableIT_BRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4412 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_CC1 ( TIM_TypeDef * TIMx )

Disable capture/compare 1 interrupt (CC1IE).

Reference Manual to LL API cross reference:
DIER CC1IE LL_TIM_DisableIT_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4214 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_CC2 ( TIM_TypeDef * TIMx )

Disable capture/compare 2 interrupt (CC2IE).

Reference Manual to LL API cross reference:
DIER CC2IE LL_TIM_DisableIT_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4247 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_CC3 ( TIM_TypeDef * TIMx )

Disable capture/compare 3 interrupt (CC3IE).

Reference Manual to LL API cross reference:
DIER CC3IE LL_TIM_DisableIT_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4280 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_CC4 ( TIM_TypeDef * TIMx )

Disable capture/compare 4 interrupt (CC4IE).

Reference Manual to LL API cross reference:
DIER CC4IE LL_TIM_DisableIT_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4313 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_COM ( TIM_TypeDef * TIMx )

Disable commutation interrupt (COMIE).

Reference Manual to LL API cross reference:
DIER COMIE LL_TIM_DisableIT_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4346 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_TRIG ( TIM_TypeDef * TIMx )

Disable trigger interrupt (TIE).

Reference Manual to LL API cross reference:
DIER TIE LL_TIM_DisableIT_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4379 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_UPDATE ( TIM_TypeDef * TIMx )

Disable update interrupt (UIE).

Reference Manual to LL API cross reference:
DIER UIE LL_TIM_DisableIT_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4181 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_BRK ( TIM_TypeDef * TIMx )

Enable break interrupt (BIE).

Reference Manual to LL API cross reference:
DIER BIE LL_TIM_EnableIT_BRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4401 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_CC1 ( TIM_TypeDef * TIMx )

Enable capture/compare 1 interrupt (CC1IE).

Reference Manual to LL API cross reference:
DIER CC1IE LL_TIM_EnableIT_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4203 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_CC2 ( TIM_TypeDef * TIMx )

Enable capture/compare 2 interrupt (CC2IE).

Reference Manual to LL API cross reference:
DIER CC2IE LL_TIM_EnableIT_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4236 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_CC3 ( TIM_TypeDef * TIMx )

Enable capture/compare 3 interrupt (CC3IE).

Reference Manual to LL API cross reference:
DIER CC3IE LL_TIM_EnableIT_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4269 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_CC4 ( TIM_TypeDef * TIMx )

Enable capture/compare 4 interrupt (CC4IE).

Reference Manual to LL API cross reference:
DIER CC4IE LL_TIM_EnableIT_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4302 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_COM ( TIM_TypeDef * TIMx )

Enable commutation interrupt (COMIE).

Reference Manual to LL API cross reference:
DIER COMIE LL_TIM_EnableIT_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4335 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_TRIG ( TIM_TypeDef * TIMx )

Enable trigger interrupt (TIE).

Reference Manual to LL API cross reference:
DIER TIE LL_TIM_EnableIT_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4368 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_UPDATE ( TIM_TypeDef * TIMx )

Enable update interrupt (UIE).

Reference Manual to LL API cross reference:
DIER UIE LL_TIM_EnableIT_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4170 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK ( TIM_TypeDef * TIMx )

Indicates whether the break interrupt (BIE) is enabled.

Reference Manual to LL API cross reference:
DIER BIE LL_TIM_IsEnabledIT_BRK
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4423 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.

Reference Manual to LL API cross reference:
DIER CC1IE LL_TIM_IsEnabledIT_CC1
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4225 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.

Reference Manual to LL API cross reference:
DIER CC2IE LL_TIM_IsEnabledIT_CC2
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4258 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.

Reference Manual to LL API cross reference:
DIER CC3IE LL_TIM_IsEnabledIT_CC3
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4291 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.

Reference Manual to LL API cross reference:
DIER CC4IE LL_TIM_IsEnabledIT_CC4
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4324 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM ( TIM_TypeDef * TIMx )

Indicates whether the commutation interrupt (COMIE) is enabled.

Reference Manual to LL API cross reference:
DIER COMIE LL_TIM_IsEnabledIT_COM
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4357 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG ( TIM_TypeDef * TIMx )

Indicates whether the trigger interrupt (TIE) is enabled.

Reference Manual to LL API cross reference:
DIER TIE LL_TIM_IsEnabledIT_TRIG
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4390 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE ( TIM_TypeDef * TIMx )

Indicates whether the update interrupt (UIE) is enabled.

Reference Manual to LL API cross reference:
DIER UIE LL_TIM_IsEnabledIT_UPDATE
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4192 of file stm32wbxx_ll_tim.h.

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DMA-Management

Functions
DMA-Management
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_EnableDMAReq_UPDATE (TIM_TypeDef *TIMx)
Enable update DMA request (UDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_UPDATE (TIM_TypeDef *TIMx)
Disable update DMA request (UDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_UPDATE (TIM_TypeDef *TIMx)
Indicates whether the update DMA request (UDE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC1 (TIM_TypeDef *TIMx)
Enable capture/compare 1 DMA request (CC1DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC1 (TIM_TypeDef *TIMx)
Disable capture/compare 1 DMA request (CC1DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC1 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC2 (TIM_TypeDef *TIMx)
Enable capture/compare 2 DMA request (CC2DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC2 (TIM_TypeDef *TIMx)
Disable capture/compare 2 DMA request (CC2DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC2 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC3 (TIM_TypeDef *TIMx)
Enable capture/compare 3 DMA request (CC3DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC3 (TIM_TypeDef *TIMx)
Disable capture/compare 3 DMA request (CC3DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC3 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC4 (TIM_TypeDef *TIMx)
Enable capture/compare 4 DMA request (CC4DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC4 (TIM_TypeDef *TIMx)
Disable capture/compare 4 DMA request (CC4DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC4 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_COM (TIM_TypeDef *TIMx)
Enable commutation DMA request (COMDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_COM (TIM_TypeDef *TIMx)
Disable commutation DMA request (COMDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_COM (TIM_TypeDef *TIMx)
Indicates whether the commutation DMA request (COMDE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_TRIG (TIM_TypeDef *TIMx)
Enable trigger interrupt (TDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_TRIG (TIM_TypeDef *TIMx)
Disable trigger interrupt (TDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_TRIG (TIM_TypeDef *TIMx)
Indicates whether the trigger interrupt (TDE) is enabled.

Function Documentation

__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1 ( TIM_TypeDef * TIMx )

Disable capture/compare 1 DMA request (CC1DE).

Reference Manual to LL API cross reference:
DIER CC1DE LL_TIM_DisableDMAReq_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4485 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2 ( TIM_TypeDef * TIMx )

Disable capture/compare 2 DMA request (CC2DE).

Reference Manual to LL API cross reference:
DIER CC2DE LL_TIM_DisableDMAReq_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4518 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3 ( TIM_TypeDef * TIMx )

Disable capture/compare 3 DMA request (CC3DE).

Reference Manual to LL API cross reference:
DIER CC3DE LL_TIM_DisableDMAReq_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4551 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4 ( TIM_TypeDef * TIMx )

Disable capture/compare 4 DMA request (CC4DE).

Reference Manual to LL API cross reference:
DIER CC4DE LL_TIM_DisableDMAReq_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4584 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_COM ( TIM_TypeDef * TIMx )

Disable commutation DMA request (COMDE).

Reference Manual to LL API cross reference:
DIER COMDE LL_TIM_DisableDMAReq_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4617 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG ( TIM_TypeDef * TIMx )

Disable trigger interrupt (TDE).

Reference Manual to LL API cross reference:
DIER TDE LL_TIM_DisableDMAReq_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4650 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE ( TIM_TypeDef * TIMx )

Disable update DMA request (UDE).

Reference Manual to LL API cross reference:
DIER UDE LL_TIM_DisableDMAReq_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4452 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1 ( TIM_TypeDef * TIMx )

Enable capture/compare 1 DMA request (CC1DE).

Reference Manual to LL API cross reference:
DIER CC1DE LL_TIM_EnableDMAReq_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4474 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2 ( TIM_TypeDef * TIMx )

Enable capture/compare 2 DMA request (CC2DE).

Reference Manual to LL API cross reference:
DIER CC2DE LL_TIM_EnableDMAReq_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4507 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3 ( TIM_TypeDef * TIMx )

Enable capture/compare 3 DMA request (CC3DE).

Reference Manual to LL API cross reference:
DIER CC3DE LL_TIM_EnableDMAReq_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4540 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4 ( TIM_TypeDef * TIMx )

Enable capture/compare 4 DMA request (CC4DE).

Reference Manual to LL API cross reference:
DIER CC4DE LL_TIM_EnableDMAReq_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4573 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_COM ( TIM_TypeDef * TIMx )

Enable commutation DMA request (COMDE).

Reference Manual to LL API cross reference:
DIER COMDE LL_TIM_EnableDMAReq_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4606 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG ( TIM_TypeDef * TIMx )

Enable trigger interrupt (TDE).

Reference Manual to LL API cross reference:
DIER TDE LL_TIM_EnableDMAReq_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4639 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE ( TIM_TypeDef * TIMx )

Enable update DMA request (UDE).

Reference Manual to LL API cross reference:
DIER UDE LL_TIM_EnableDMAReq_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4441 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.

Reference Manual to LL API cross reference:
DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4496 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.

Reference Manual to LL API cross reference:
DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4529 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.

Reference Manual to LL API cross reference:
DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4562 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.

Reference Manual to LL API cross reference:
DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4595 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM ( TIM_TypeDef * TIMx )

Indicates whether the commutation DMA request (COMDE) is enabled.

Reference Manual to LL API cross reference:
DIER COMDE LL_TIM_IsEnabledDMAReq_COM
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4628 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG ( TIM_TypeDef * TIMx )

Indicates whether the trigger interrupt (TDE) is enabled.

Reference Manual to LL API cross reference:
DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4661 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE ( TIM_TypeDef * TIMx )

Indicates whether the update DMA request (UDE) is enabled.

Reference Manual to LL API cross reference:
DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 4463 of file stm32wbxx_ll_tim.h.

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: EVENT-Management

Functions
EVENT-Management
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_GenerateEvent_UPDATE (TIM_TypeDef *TIMx)
Generate an update event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC1 (TIM_TypeDef *TIMx)
Generate Capture/Compare 1 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC2 (TIM_TypeDef *TIMx)
Generate Capture/Compare 2 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC3 (TIM_TypeDef *TIMx)
Generate Capture/Compare 3 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC4 (TIM_TypeDef *TIMx)
Generate Capture/Compare 4 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_COM (TIM_TypeDef *TIMx)
Generate commutation event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_TRIG (TIM_TypeDef *TIMx)
Generate trigger event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_BRK (TIM_TypeDef *TIMx)
Generate break event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_BRK2 (TIM_TypeDef *TIMx)
Generate break 2 event.

Function Documentation

__STATIC_INLINE void LL_TIM_GenerateEvent_BRK ( TIM_TypeDef * TIMx )

Generate break event.

Reference Manual to LL API cross reference:
EGR BG LL_TIM_GenerateEvent_BRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4756 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2 ( TIM_TypeDef * TIMx )

Generate break 2 event.

Reference Manual to LL API cross reference:
EGR B2G LL_TIM_GenerateEvent_BRK2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4767 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_CC1 ( TIM_TypeDef * TIMx )

Generate Capture/Compare 1 event.

Reference Manual to LL API cross reference:
EGR CC1G LL_TIM_GenerateEvent_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4690 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_CC2 ( TIM_TypeDef * TIMx )

Generate Capture/Compare 2 event.

Reference Manual to LL API cross reference:
EGR CC2G LL_TIM_GenerateEvent_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4701 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_CC3 ( TIM_TypeDef * TIMx )

Generate Capture/Compare 3 event.

Reference Manual to LL API cross reference:
EGR CC3G LL_TIM_GenerateEvent_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4712 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_CC4 ( TIM_TypeDef * TIMx )

Generate Capture/Compare 4 event.

Reference Manual to LL API cross reference:
EGR CC4G LL_TIM_GenerateEvent_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4723 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_COM ( TIM_TypeDef * TIMx )

Generate commutation event.

Reference Manual to LL API cross reference:
EGR COMG LL_TIM_GenerateEvent_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4734 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG ( TIM_TypeDef * TIMx )

Generate trigger event.

Reference Manual to LL API cross reference:
EGR TG LL_TIM_GenerateEvent_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4745 of file stm32wbxx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE ( TIM_TypeDef * TIMx )

Generate an update event.

Reference Manual to LL API cross reference:
EGR UG LL_TIM_GenerateEvent_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 4679 of file stm32wbxx_ll_tim.h.

Referenced by LL_TIM_Init().

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialisation and deinitialisation functions

Functions
Initialisation and deinitialisation functions
TIM Exported Functions

Functions

ErrorStatus | LL_TIM_DeInit (TIM_TypeDef *TIMx)
Set TIMx registers to their reset values.
void | LL_TIM_StructInit (LL_TIM_InitTypeDef *TIM_InitStruct)
Set the fields of the time base unit configuration data structure to their default values.
ErrorStatus | LL_TIM_Init (TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
Configure the TIMx time base unit.
void | LL_TIM_OC_StructInit (LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Set the fields of the TIMx output channel configuration data structure to their default values.
ErrorStatus | LL_TIM_OC_Init (TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Configure the TIMx output channel.
void | LL_TIM_IC_StructInit (LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Set the fields of the TIMx input channel configuration data structure to their default values.
ErrorStatus | LL_TIM_IC_Init (TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
Configure the TIMx input channel.
void | LL_TIM_ENCODER_StructInit (LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Fills each TIM_EncoderInitStruct field with its default value.
ErrorStatus | LL_TIM_ENCODER_Init (TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Configure the encoder interface of the timer instance.
void | LL_TIM_HALLSENSOR_StructInit (LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
Set the fields of the TIMx Hall sensor interface configuration data structure to their default values.
ErrorStatus | LL_TIM_HALLSENSOR_Init (TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
Configure the Hall sensor interface of the timer instance.
void | LL_TIM_BDTR_StructInit (LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
Set the fields of the Break and Dead Time configuration data structure to their default values.
ErrorStatus | LL_TIM_BDTR_Init (TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
Configure the Break and Dead Time feature of the timer instance.

Function Documentation

ErrorStatus LL_TIM_BDTR_Init | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_BDTR_InitTypeDef * | TIM_BDTRInitStruct
 | ) |  |

Configure the Break and Dead Time feature of the timer instance.

Note:
As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a second break input.
Parameters:
TIMx | Timer Instance
TIM_BDTRInitStruct | pointer to a LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: Break and Dead Time is initialized
  • ERROR: not applicable

Definition at line 667 of file stm32wbxx_ll_tim.c.

References assert_param, LL_TIM_BDTR_InitTypeDef::AutomaticOutput, LL_TIM_BDTR_InitTypeDef::Break2Filter, LL_TIM_BDTR_InitTypeDef::Break2Polarity, LL_TIM_BDTR_InitTypeDef::Break2State, LL_TIM_BDTR_InitTypeDef::BreakFilter, LL_TIM_BDTR_InitTypeDef::BreakPolarity, LL_TIM_BDTR_InitTypeDef::BreakState, LL_TIM_BDTR_InitTypeDef::DeadTime, IS_LL_TIM_AUTOMATIC_OUTPUT_STATE, IS_LL_TIM_BREAK2_FILTER, IS_LL_TIM_BREAK2_POLARITY, IS_LL_TIM_BREAK2_STATE, IS_LL_TIM_BREAK_FILTER, IS_LL_TIM_BREAK_POLARITY, IS_LL_TIM_BREAK_STATE, IS_LL_TIM_LOCK_LEVEL, IS_LL_TIM_OSSI_STATE, IS_LL_TIM_OSSR_STATE, LL_TIM_WriteReg, LL_TIM_BDTR_InitTypeDef::LockLevel, LL_TIM_BDTR_InitTypeDef::OSSIState, and LL_TIM_BDTR_InitTypeDef::OSSRState.

void LL_TIM_BDTR_StructInit ( LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct )

Set the fields of the Break and Dead Time configuration data structure to their default values.

Parameters:
TIM_BDTRInitStruct pointer to a LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
Return values:
None

Definition at line 635 of file stm32wbxx_ll_tim.c.

References LL_TIM_BDTR_InitTypeDef::AutomaticOutput, LL_TIM_BDTR_InitTypeDef::Break2Filter, LL_TIM_BDTR_InitTypeDef::Break2Polarity, LL_TIM_BDTR_InitTypeDef::Break2State, LL_TIM_BDTR_InitTypeDef::BreakFilter, LL_TIM_BDTR_InitTypeDef::BreakPolarity, LL_TIM_BDTR_InitTypeDef::BreakState, LL_TIM_BDTR_InitTypeDef::DeadTime, LL_TIM_AUTOMATICOUTPUT_DISABLE, LL_TIM_BREAK2_DISABLE, LL_TIM_BREAK2_FILTER_FDIV1, LL_TIM_BREAK2_POLARITY_LOW, LL_TIM_BREAK_DISABLE, LL_TIM_BREAK_FILTER_FDIV1, LL_TIM_BREAK_POLARITY_LOW, LL_TIM_LOCKLEVEL_OFF, LL_TIM_OSSI_DISABLE, LL_TIM_OSSR_DISABLE, LL_TIM_BDTR_InitTypeDef::LockLevel, LL_TIM_BDTR_InitTypeDef::OSSIState, and LL_TIM_BDTR_InitTypeDef::OSSRState.

ErrorStatus LL_TIM_DeInit ( TIM_TypeDef * TIMx )

Set TIMx registers to their reset values.

Parameters:
TIMx Timer instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: invalid TIMx instance

Definition at line 217 of file stm32wbxx_ll_tim.c.

References assert_param, LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_TIM2, LL_APB1_GRP1_ReleaseReset(), LL_APB2_GRP1_ForceReset(), LL_APB2_GRP1_PERIPH_TIM1, LL_APB2_GRP1_PERIPH_TIM16, LL_APB2_GRP1_PERIPH_TIM17, and LL_APB2_GRP1_ReleaseReset().

ErrorStatus LL_TIM_ENCODER_Init | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_ENCODER_InitTypeDef * | TIM_EncoderInitStruct
 | ) |  |

Configure the encoder interface of the timer instance.

Parameters:
TIMx | Timer Instance
TIM_EncoderInitStruct | pointer to a LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 466 of file stm32wbxx_ll_tim.c.

References assert_param, LL_TIM_ENCODER_InitTypeDef::EncoderMode, LL_TIM_ENCODER_InitTypeDef::IC1ActiveInput, LL_TIM_ENCODER_InitTypeDef::IC1Filter, LL_TIM_ENCODER_InitTypeDef::IC1Polarity, LL_TIM_ENCODER_InitTypeDef::IC1Prescaler, LL_TIM_ENCODER_InitTypeDef::IC2ActiveInput, LL_TIM_ENCODER_InitTypeDef::IC2Filter, LL_TIM_ENCODER_InitTypeDef::IC2Polarity, LL_TIM_ENCODER_InitTypeDef::IC2Prescaler, IS_LL_TIM_ACTIVEINPUT, IS_LL_TIM_ENCODERMODE, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY_ENCODER, IS_LL_TIM_ICPSC, LL_TIM_ReadReg, LL_TIM_SetEncoderMode(), and LL_TIM_WriteReg.

void LL_TIM_ENCODER_StructInit ( LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct )

Fills each TIM_EncoderInitStruct field with its default value.

Parameters:
TIM_EncoderInitStruct pointer to a LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
Return values:
None

Definition at line 444 of file stm32wbxx_ll_tim.c.

References LL_TIM_ENCODER_InitTypeDef::EncoderMode, LL_TIM_ENCODER_InitTypeDef::IC1ActiveInput, LL_TIM_ENCODER_InitTypeDef::IC1Filter, LL_TIM_ENCODER_InitTypeDef::IC1Polarity, LL_TIM_ENCODER_InitTypeDef::IC1Prescaler, LL_TIM_ENCODER_InitTypeDef::IC2ActiveInput, LL_TIM_ENCODER_InitTypeDef::IC2Filter, LL_TIM_ENCODER_InitTypeDef::IC2Polarity, LL_TIM_ENCODER_InitTypeDef::IC2Prescaler, LL_TIM_ACTIVEINPUT_DIRECTTI, LL_TIM_ENCODERMODE_X2_TI1, LL_TIM_IC_FILTER_FDIV1, LL_TIM_IC_POLARITY_RISING, and LL_TIM_ICPSC_DIV1.

ErrorStatus LL_TIM_HALLSENSOR_Init | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_HALLSENSOR_InitTypeDef * | TIM_HallSensorInitStruct
 | ) |  |

Configure the Hall sensor interface of the timer instance.

Note:
TIMx CH1, CH2 and CH3 inputs connected through a XOR to the TI1 input channel
TIMx slave mode controller is configured in reset mode. Selected internal trigger is TI1F_ED.
Channel 1 is configured as input, IC1 is mapped on TRC.
Captured value stored in TIMx_CCR1 correspond to the time elapsed between 2 changes on the inputs. It gives information about motor speed.
Channel 2 is configured in output PWM 2 mode.
Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
OC2REF is selected as trigger output on TRGO.
LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used when TIMx operates in Hall sensor interface mode.
Parameters:
TIMx | Timer Instance
TIM_HallSensorInitStruct | pointer to a LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 557 of file stm32wbxx_ll_tim.c.

References assert_param, LL_TIM_HALLSENSOR_InitTypeDef::CommutationDelay, LL_TIM_HALLSENSOR_InitTypeDef::IC1Filter, LL_TIM_HALLSENSOR_InitTypeDef::IC1Polarity, LL_TIM_HALLSENSOR_InitTypeDef::IC1Prescaler, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY_ENCODER, IS_LL_TIM_ICPSC, LL_TIM_ACTIVEINPUT_TRC, LL_TIM_OC_SetCompareCH2(), LL_TIM_OCMODE_PWM2, LL_TIM_ReadReg, LL_TIM_SLAVEMODE_RESET, LL_TIM_TRGO_OC2REF, LL_TIM_TS_TI1F_ED, and LL_TIM_WriteReg.

void LL_TIM_HALLSENSOR_StructInit ( LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct )

Set the fields of the TIMx Hall sensor interface configuration data structure to their default values.

Parameters:
TIM_HallSensorInitStruct pointer to a LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
Return values:
None

Definition at line 528 of file stm32wbxx_ll_tim.c.

References LL_TIM_HALLSENSOR_InitTypeDef::CommutationDelay, LL_TIM_HALLSENSOR_InitTypeDef::IC1Filter, LL_TIM_HALLSENSOR_InitTypeDef::IC1Polarity, LL_TIM_HALLSENSOR_InitTypeDef::IC1Prescaler, LL_TIM_IC_FILTER_FDIV1, LL_TIM_IC_POLARITY_RISING, and LL_TIM_ICPSC_DIV1.

ErrorStatus LL_TIM_IC_Init | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | LL_TIM_IC_InitTypeDef * | TIM_IC_InitStruct
 | ) |  |

Configure the TIMx input channel.

Parameters:
TIMx | Timer Instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
TIM_IC_InitStruct | pointer to a LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx output channel is initialized
  • ERROR: TIMx output channel is not initialized

Definition at line 414 of file stm32wbxx_ll_tim.c.

References IC1Config(), IC2Config(), IC3Config(), IC4Config(), LL_TIM_CHANNEL_CH1, LL_TIM_CHANNEL_CH2, LL_TIM_CHANNEL_CH3, and LL_TIM_CHANNEL_CH4.

void LL_TIM_IC_StructInit ( LL_TIM_IC_InitTypeDef * TIM_ICInitStruct )

Set the fields of the TIMx input channel configuration data structure to their default values.

Parameters:
TIM_ICInitStruct pointer to a LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
Return values:
None

Definition at line 392 of file stm32wbxx_ll_tim.c.

References LL_TIM_IC_InitTypeDef::ICActiveInput, LL_TIM_IC_InitTypeDef::ICFilter, LL_TIM_IC_InitTypeDef::ICPolarity, LL_TIM_IC_InitTypeDef::ICPrescaler, LL_TIM_ACTIVEINPUT_DIRECTTI, LL_TIM_IC_FILTER_FDIV1, LL_TIM_IC_POLARITY_RISING, and LL_TIM_ICPSC_DIV1.

ErrorStatus LL_TIM_Init | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_InitTypeDef * | TIM_InitStruct
 | ) |  |

Configure the TIMx time base unit.

Parameters:
TIMx | Timer Instance
TIM_InitStruct | pointer to a LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 276 of file stm32wbxx_ll_tim.c.

References assert_param, LL_TIM_InitTypeDef::Autoreload, LL_TIM_InitTypeDef::ClockDivision, LL_TIM_InitTypeDef::CounterMode, IS_LL_TIM_CLOCKDIVISION, IS_LL_TIM_COUNTERMODE, LL_TIM_GenerateEvent_UPDATE(), LL_TIM_ReadReg, LL_TIM_SetAutoReload(), LL_TIM_SetPrescaler(), LL_TIM_SetRepetitionCounter(), LL_TIM_WriteReg, LL_TIM_InitTypeDef::Prescaler, and LL_TIM_InitTypeDef::RepetitionCounter.

ErrorStatus LL_TIM_OC_Init | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | LL_TIM_OC_InitTypeDef * | TIM_OC_InitStruct
 | ) |  |

Configure the TIMx output channel.

Parameters:
TIMx | Timer Instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
  • LL_TIM_CHANNEL_CH5
  • LL_TIM_CHANNEL_CH6
TIM_OC_InitStruct | pointer to a LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx output channel is initialized
  • ERROR: TIMx output channel is not initialized

Definition at line 355 of file stm32wbxx_ll_tim.c.

References LL_TIM_CHANNEL_CH1, LL_TIM_CHANNEL_CH2, LL_TIM_CHANNEL_CH3, LL_TIM_CHANNEL_CH4, LL_TIM_CHANNEL_CH5, LL_TIM_CHANNEL_CH6, OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

void LL_TIM_OC_StructInit ( LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct )

Set the fields of the TIMx output channel configuration data structure to their default values.

Parameters:
TIM_OC_InitStruct pointer to a LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
Return values:
None

Definition at line 327 of file stm32wbxx_ll_tim.c.

References LL_TIM_OC_InitTypeDef::CompareValue, LL_TIM_OCIDLESTATE_LOW, LL_TIM_OCMODE_FROZEN, LL_TIM_OCPOLARITY_HIGH, LL_TIM_OCSTATE_DISABLE, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

void LL_TIM_StructInit ( LL_TIM_InitTypeDef * TIM_InitStruct )

Set the fields of the time base unit configuration data structure to their default values.

Parameters:
TIM_InitStruct pointer to a LL_TIM_InitTypeDef structure (time base unit configuration data structure)
Return values:
None

Definition at line 258 of file stm32wbxx_ll_tim.c.

References LL_TIM_InitTypeDef::Autoreload, LL_TIM_InitTypeDef::ClockDivision, LL_TIM_InitTypeDef::CounterMode, LL_TIM_CLOCKDIVISION_DIV1, LL_TIM_COUNTERMODE_UP, LL_TIM_InitTypeDef::Prescaler, and LL_TIM_InitTypeDef::RepetitionCounter.

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: USART

Modules
USART
STM32WBxx_LL_Driver

Modules

USART Private Variables
USART Private Constants
USART Private Macros
USART Exported Init structures
USART Exported Constants
USART Exported Macros
USART Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for USART registers.

Register | Bit | Function
BRR | BRR | LL_USART_GetBaudRate
 |  | LL_USART_SetBaudRate
CR1 | CMIE | LL_USART_DisableIT_CM
 |  | LL_USART_EnableIT_CM
 |  | LL_USART_IsEnabledIT_CM
 | DEAT | LL_USART_GetDEAssertionTime
 |  | LL_USART_SetDEAssertionTime
 | DEDT | LL_USART_GetDEDeassertionTime
 |  | LL_USART_SetDEDeassertionTime
 | EOBIE | LL_USART_DisableIT_EOB
 |  | LL_USART_EnableIT_EOB
 |  | LL_USART_IsEnabledIT_EOB
 | FIFOEN | LL_USART_DisableFIFO
 |  | LL_USART_EnableFIFO
 |  | LL_USART_IsEnabledFIFO
 | IDLEIE | LL_USART_DisableIT_IDLE
 |  | LL_USART_EnableIT_IDLE
 |  | LL_USART_IsEnabledIT_IDLE
 | M0 | LL_USART_ConfigCharacter
 |  | LL_USART_GetDataWidth
 |  | LL_USART_SetDataWidth
 | M1 | LL_USART_ConfigCharacter
 |  | LL_USART_GetDataWidth
 |  | LL_USART_SetDataWidth
 | MME | LL_USART_DisableMuteMode
 |  | LL_USART_EnableMuteMode
 |  | LL_USART_IsEnabledMuteMode
 | OVER8 | LL_USART_GetOverSampling
 |  | LL_USART_SetOverSampling
 | PCE | LL_USART_ConfigCharacter
 |  | LL_USART_GetParity
 |  | LL_USART_SetParity
 | PEIE | LL_USART_DisableIT_PE
 |  | LL_USART_EnableIT_PE
 |  | LL_USART_IsEnabledIT_PE
 | PS | LL_USART_ConfigCharacter
 |  | LL_USART_GetParity
 |  | LL_USART_SetParity
 | RE | LL_USART_DisableDirectionRx
 |  | LL_USART_EnableDirectionRx
 |  | LL_USART_GetTransferDirection
 |  | LL_USART_SetTransferDirection
 | RTOIE | LL_USART_DisableIT_RTO
 |  | LL_USART_EnableIT_RTO
 |  | LL_USART_IsEnabledIT_RTO
 | RXFFIE | LL_USART_DisableIT_RXFF
 |  | LL_USART_EnableIT_RXFF
 |  | LL_USART_IsEnabledIT_RXFF
 | RXNEIE_RXFNEIE | LL_USART_DisableIT_RXNE_RXFNE
 |  | LL_USART_EnableIT_RXNE_RXFNE
 |  | LL_USART_IsEnabledIT_RXNE_RXFNE
 | TCIE | LL_USART_DisableIT_TC
 |  | LL_USART_EnableIT_TC
 |  | LL_USART_IsEnabledIT_TC
 | TE | LL_USART_DisableDirectionTx
 |  | LL_USART_EnableDirectionTx
 |  | LL_USART_GetTransferDirection
 |  | LL_USART_SetTransferDirection
 | TXEIE_TXFNFIE | LL_USART_DisableIT_TXE_TXFNF
 |  | LL_USART_EnableIT_TXE_TXFNF
 |  | LL_USART_IsEnabledIT_TXE_TXFNF
 | TXFEIE | LL_USART_DisableIT_TXFE
 |  | LL_USART_EnableIT_TXFE
 |  | LL_USART_IsEnabledIT_TXFE
 | UE | LL_USART_Disable
 |  | LL_USART_Enable
 |  | LL_USART_IsEnabled
 | UESM | LL_USART_DisableInStopMode
 |  | LL_USART_EnableInStopMode
 |  | LL_USART_IsEnabledInStopMode
 | WAKE | LL_USART_GetWakeUpMethod
 |  | LL_USART_SetWakeUpMethod
CR2 | ABREN | LL_USART_DisableAutoBaudRate
 |  | LL_USART_EnableAutoBaudRate
 |  | LL_USART_IsEnabledAutoBaud
 | ABRMODE | LL_USART_GetAutoBaudRateMode
 |  | LL_USART_SetAutoBaudRateMode
 | ADD | LL_USART_ConfigNodeAddress
 |  | LL_USART_GetNodeAddress
 | ADDM7 | LL_USART_ConfigNodeAddress
 |  | LL_USART_GetNodeAddressLen
 | CLKEN | LL_USART_ConfigAsyncMode
 |  | LL_USART_ConfigHalfDuplexMode
 |  | LL_USART_ConfigIrdaMode
 |  | LL_USART_ConfigLINMode
 |  | LL_USART_ConfigMultiProcessMode
 |  | LL_USART_ConfigSmartcardMode
 |  | LL_USART_ConfigSyncMode
 |  | LL_USART_DisableSCLKOutput
 |  | LL_USART_EnableSCLKOutput
 |  | LL_USART_IsEnabledSCLKOutput
 | CPHA | LL_USART_ConfigClock
 |  | LL_USART_GetClockPhase
 |  | LL_USART_SetClockPhase
 | CPOL | LL_USART_ConfigClock
 |  | LL_USART_GetClockPolarity
 |  | LL_USART_SetClockPolarity
 | DATAINV | LL_USART_GetBinaryDataLogic
 |  | LL_USART_SetBinaryDataLogic
 | DIS_NSS | LL_USART_DisableSPISlaveSelect
 |  | LL_USART_EnableSPISlaveSelect
 |  | LL_USART_IsEnabledSPISlaveSelect
 | LBCL | LL_USART_ConfigClock
 |  | LL_USART_GetLastClkPulseOutput
 |  | LL_USART_SetLastClkPulseOutput
 | LBDIE | LL_USART_DisableIT_LBD
 |  | LL_USART_EnableIT_LBD
 |  | LL_USART_IsEnabledIT_LBD
 | LBDL | LL_USART_GetLINBrkDetectionLen
 |  | LL_USART_SetLINBrkDetectionLen
 | LINEN | LL_USART_ConfigAsyncMode
 |  | LL_USART_ConfigHalfDuplexMode
 |  | LL_USART_ConfigIrdaMode
 |  | LL_USART_ConfigLINMode
 |  | LL_USART_ConfigMultiProcessMode
 |  | LL_USART_ConfigSmartcardMode
 |  | LL_USART_ConfigSyncMode
 |  | LL_USART_DisableLIN
 |  | LL_USART_EnableLIN
 |  | LL_USART_IsEnabledLIN
 | MSBFIRST | LL_USART_GetTransferBitOrder
 |  | LL_USART_SetTransferBitOrder
 | RTOEN | LL_USART_DisableRxTimeout
 |  | LL_USART_EnableRxTimeout
 |  | LL_USART_IsEnabledRxTimeout
 | RXINV | LL_USART_GetRXPinLevel
 |  | LL_USART_SetRXPinLevel
 | SLVEN | LL_USART_DisableSPISlave
 |  | LL_USART_EnableSPISlave
 |  | LL_USART_IsEnabledSPISlave
 | STOP | LL_USART_ConfigCharacter
 |  | LL_USART_ConfigIrdaMode
 |  | LL_USART_ConfigLINMode
 |  | LL_USART_ConfigSmartcardMode
 |  | LL_USART_GetStopBitsLength
 |  | LL_USART_SetStopBitsLength
 | SWAP | LL_USART_GetTXRXSwap
 |  | LL_USART_SetTXRXSwap
 | TXINV | LL_USART_GetTXPinLevel
 |  | LL_USART_SetTXPinLevel
CR3 | CTSE | LL_USART_DisableCTSHWFlowCtrl
 |  | LL_USART_EnableCTSHWFlowCtrl
 |  | LL_USART_GetHWFlowCtrl
 |  | LL_USART_SetHWFlowCtrl
 | CTSIE | LL_USART_DisableIT_CTS
 |  | LL_USART_EnableIT_CTS
 |  | LL_USART_IsEnabledIT_CTS
 | DDRE | LL_USART_DisableDMADeactOnRxErr
 |  | LL_USART_EnableDMADeactOnRxErr
 |  | LL_USART_IsEnabledDMADeactOnRxErr
 | DEM | LL_USART_DisableDEMode
 |  | LL_USART_EnableDEMode
 |  | LL_USART_IsEnabledDEMode
 | DEP | LL_USART_GetDESignalPolarity
 |  | LL_USART_SetDESignalPolarity
 | DMAR | LL_USART_DisableDMAReq_RX
 |  | LL_USART_EnableDMAReq_RX
 |  | LL_USART_IsEnabledDMAReq_RX
 | DMAT | LL_USART_DisableDMAReq_TX
 |  | LL_USART_EnableDMAReq_TX
 |  | LL_USART_IsEnabledDMAReq_TX
 | EIE | LL_USART_DisableIT_ERROR
 |  | LL_USART_EnableIT_ERROR
 |  | LL_USART_IsEnabledIT_ERROR
 | HDSEL | LL_USART_ConfigAsyncMode
 |  | LL_USART_ConfigHalfDuplexMode
 |  | LL_USART_ConfigIrdaMode
 |  | LL_USART_ConfigLINMode
 |  | LL_USART_ConfigMultiProcessMode
 |  | LL_USART_ConfigSmartcardMode
 |  | LL_USART_ConfigSyncMode
 |  | LL_USART_DisableHalfDuplex
 |  | LL_USART_EnableHalfDuplex
 |  | LL_USART_IsEnabledHalfDuplex
 | IREN | LL_USART_ConfigAsyncMode
 |  | LL_USART_ConfigHalfDuplexMode
 |  | LL_USART_ConfigIrdaMode
 |  | LL_USART_ConfigLINMode
 |  | LL_USART_ConfigMultiProcessMode
 |  | LL_USART_ConfigSyncMode
 |  | LL_USART_DisableIrda
 |  | LL_USART_EnableIrda
 |  | LL_USART_IsEnabledIrda
 | IRLP | LL_USART_GetIrdaPowerMode
 |  | LL_USART_SetIrdaPowerMode
 | NACK | LL_USART_DisableSmartcardNACK
 |  | LL_USART_EnableSmartcardNACK
 |  | LL_USART_IsEnabledSmartcardNACK
 | ONEBIT | LL_USART_DisableOneBitSamp
 |  | LL_USART_EnableOneBitSamp
 |  | LL_USART_IsEnabledOneBitSamp
 | OVRDIS | LL_USART_DisableOverrunDetect
 |  | LL_USART_EnableOverrunDetect
 |  | LL_USART_IsEnabledOverrunDetect
 | RTSE | LL_USART_DisableRTSHWFlowCtrl
 |  | LL_USART_EnableRTSHWFlowCtrl
 |  | LL_USART_GetHWFlowCtrl
 |  | LL_USART_SetHWFlowCtrl
 | RXFTCFG | LL_USART_ConfigFIFOsThreshold
 |  | LL_USART_GetRXFIFOThreshold
 |  | LL_USART_SetRXFIFOThreshold
 | RXFTIE | LL_USART_DisableIT_RXFT
 |  | LL_USART_EnableIT_RXFT
 |  | LL_USART_IsEnabledIT_RXFT
 | SCARCNT | LL_USART_GetSmartcardAutoRetryCount
 |  | LL_USART_SetSmartcardAutoRetryCount
 | SCEN | LL_USART_ConfigAsyncMode
 |  | LL_USART_ConfigHalfDuplexMode
 |  | LL_USART_ConfigIrdaMode
 |  | LL_USART_ConfigLINMode
 |  | LL_USART_ConfigMultiProcessMode
 |  | LL_USART_ConfigSmartcardMode
 |  | LL_USART_ConfigSyncMode
 |  | LL_USART_DisableSmartcard
 |  | LL_USART_EnableSmartcard
 |  | LL_USART_IsEnabledSmartcard
 | TCBGTIE | LL_USART_DisableIT_TCBGT
 |  | LL_USART_EnableIT_TCBGT
 |  | LL_USART_IsEnabledIT_TCBGT
 | TXFTCFG | LL_USART_ConfigFIFOsThreshold
 |  | LL_USART_GetTXFIFOThreshold
 |  | LL_USART_SetTXFIFOThreshold
 | TXFTIE | LL_USART_DisableIT_TXFT
 |  | LL_USART_EnableIT_TXFT
 |  | LL_USART_IsEnabledIT_TXFT
 | WUFIE | LL_USART_DisableIT_WKUP
 |  | LL_USART_EnableIT_WKUP
 |  | LL_USART_IsEnabledIT_WKUP
 | WUS | LL_USART_GetWKUPType
 |  | LL_USART_SetWKUPType
GTPR | GT | LL_USART_GetSmartcardGuardTime
 |  | LL_USART_SetSmartcardGuardTime
 | PSC | LL_USART_GetIrdaPrescaler
 |  | LL_USART_GetSmartcardPrescaler
 |  | LL_USART_SetIrdaPrescaler
 |  | LL_USART_SetSmartcardPrescaler
ICR | CMCF | LL_USART_ClearFlag_CM
 | CTSCF | LL_USART_ClearFlag_nCTS
 | EOBCF | LL_USART_ClearFlag_EOB
 | FECF | LL_USART_ClearFlag_FE
 | IDLECF | LL_USART_ClearFlag_IDLE
 | LBDCF | LL_USART_ClearFlag_LBD
 | NECF | LL_USART_ClearFlag_NE
 | ORECF | LL_USART_ClearFlag_ORE
 | PECF | LL_USART_ClearFlag_PE
 | RTOCF | LL_USART_ClearFlag_RTO
 | TCBGTCF | LL_USART_ClearFlag_TCBGT
 | TCCF | LL_USART_ClearFlag_TC
 | TXFECF | LL_USART_ClearFlag_TXFE
 | UDRCF | LL_USART_ClearFlag_UDR
 | WUCF | LL_USART_ClearFlag_WKUP
ISR | ABRE | LL_USART_IsActiveFlag_ABRE
 | ABRF | LL_USART_IsActiveFlag_ABR
 | BUSY | LL_USART_IsActiveFlag_BUSY
 | CMF | LL_USART_IsActiveFlag_CM
 | CTS | LL_USART_IsActiveFlag_CTS
 | CTSIF | LL_USART_IsActiveFlag_nCTS
 | EOBF | LL_USART_IsActiveFlag_EOB
 | FE | LL_USART_IsActiveFlag_FE
 | IDLE | LL_USART_IsActiveFlag_IDLE
 | LBDF | LL_USART_IsActiveFlag_LBD
 | NE | LL_USART_IsActiveFlag_NE
 | ORE | LL_USART_IsActiveFlag_ORE
 | PE | LL_USART_IsActiveFlag_PE
 | REACK | LL_USART_IsActiveFlag_REACK
 | RTOF | LL_USART_IsActiveFlag_RTO
 | RWU | LL_USART_IsActiveFlag_RWU
 | RXFF | LL_USART_IsActiveFlag_RXFF
 | RXFT | LL_USART_IsActiveFlag_RXFT
 | RXNE_RXFNE | LL_USART_IsActiveFlag_RXNE_RXFNE
 | SBKF | LL_USART_IsActiveFlag_SBK
 | TC | LL_USART_IsActiveFlag_TC
 | TCBGT | LL_USART_IsActiveFlag_TCBGT
 | TEACK | LL_USART_IsActiveFlag_TEACK
 | TXE_TXFNF | LL_USART_IsActiveFlag_TXE_TXFNF
 | TXFE | LL_USART_IsActiveFlag_TXFE
 | TXFT | LL_USART_IsActiveFlag_TXFT
 | UDR | LL_USART_IsActiveFlag_UDR
 | WUF | LL_USART_IsActiveFlag_WKUP
PRESC | PRESCALER | LL_USART_GetPrescaler
 |  | LL_USART_SetPrescaler
RDR | RDR | LL_USART_DMA_GetRegAddr
 |  | LL_USART_ReceiveData8
 |  | LL_USART_ReceiveData9
RQR | ABRRQ | LL_USART_RequestAutoBaudRate
 | MMRQ | LL_USART_RequestEnterMuteMode
 | RXFRQ | LL_USART_RequestRxDataFlush
 | SBKRQ | LL_USART_RequestBreakSending
 | TXFRQ | LL_USART_RequestTxDataFlush
RTOR | BLEN | LL_USART_GetBlockLength
 |  | LL_USART_SetBlockLength
 | RTO | LL_USART_GetRxTimeout
 |  | LL_USART_SetRxTimeout
TDR | TDR | LL_USART_DMA_GetRegAddr
 |  | LL_USART_TransmitData8
 |  | LL_USART_TransmitData9
Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: USART Private Variables

Variables
USART Private Variables
USART

Variables

static const uint16_t USART_PRESCALER_TAB []

Variable Documentation

const uint16_t USART_PRESCALER_TAB[] [static]
Initial value:
{
  (uint16_t)1,
  (uint16_t)2,
  (uint16_t)4,
  (uint16_t)6,
  (uint16_t)8,
  (uint16_t)10,
  (uint16_t)12,
  (uint16_t)16,
  (uint16_t)32,
  (uint16_t)64,
  (uint16_t)128,
  (uint16_t)256
}

Definition at line 47 of file stm32wbxx_ll_usart.h.

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: USART Private Constants

USART Private Constants
USART
Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: USART Private Macros

Defines
USART Private Macros
USART

Defines

#define | IS_LL_USART_PRESCALER(__VALUE__)
#define | IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 8000000U)
#define | IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
#define | IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
#define | IS_LL_USART_DIRECTION(__VALUE__)
#define | IS_LL_USART_PARITY(__VALUE__)
#define | IS_LL_USART_DATAWIDTH(__VALUE__)
#define | IS_LL_USART_OVERSAMPLING(__VALUE__)
#define | IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__)
#define | IS_LL_USART_CLOCKPHASE(__VALUE__)
#define | IS_LL_USART_CLOCKPOLARITY(__VALUE__)
#define | IS_LL_USART_CLOCKOUTPUT(__VALUE__)
#define | IS_LL_USART_STOPBITS(__VALUE__)
#define | IS_LL_USART_HWCONTROL(__VALUE__)

Define Documentation

#define IS_LL_USART_BAUDRATE ( __BAUDRATE__ ) ((__BAUDRATE__) <= 8000000U)

Definition at line 73 of file stm32wbxx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_BRR_MAX ( __VALUE__ ) ((__VALUE__) <= 0x0000FFFFU)

Definition at line 79 of file stm32wbxx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_BRR_MIN ( __VALUE__ ) ((__VALUE__) >= 16U)

Definition at line 76 of file stm32wbxx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_CLOCKOUTPUT ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_CLOCK_DISABLE) \
                                         || ((__VALUE__) == LL_USART_CLOCK_ENABLE))

Definition at line 106 of file stm32wbxx_ll_usart.c.

Referenced by LL_USART_ClockInit().

#define IS_LL_USART_CLOCKPHASE ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_PHASE_1EDGE) \
                                        || ((__VALUE__) == LL_USART_PHASE_2EDGE))

Definition at line 100 of file stm32wbxx_ll_usart.c.

Referenced by LL_USART_ClockInit().

#define IS_LL_USART_CLOCKPOLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_POLARITY_LOW) \
                                           || ((__VALUE__) == LL_USART_POLARITY_HIGH))

Definition at line 103 of file stm32wbxx_ll_usart.c.

Referenced by LL_USART_ClockInit().

#define IS_LL_USART_DATAWIDTH ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_DATAWIDTH_7B) \
                                       || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
                                       || ((__VALUE__) == LL_USART_DATAWIDTH_9B))

Definition at line 90 of file stm32wbxx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_DIRECTION ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_DIRECTION_NONE) \
                                       || ((__VALUE__) == LL_USART_DIRECTION_RX) \
                                       || ((__VALUE__) == LL_USART_DIRECTION_TX) \
                                       || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))

Definition at line 81 of file stm32wbxx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_HWCONTROL ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_HWCONTROL_NONE) \
                                       || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
                                       || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
                                       || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))

Definition at line 114 of file stm32wbxx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_LASTBITCLKOUTPUT ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
                                              || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))

Definition at line 97 of file stm32wbxx_ll_usart.c.

Referenced by LL_USART_ClockInit().

#define IS_LL_USART_OVERSAMPLING ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_OVERSAMPLING_16) \
                                          || ((__VALUE__) == LL_USART_OVERSAMPLING_8))

Definition at line 94 of file stm32wbxx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_PARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_PARITY_NONE) \
                                    || ((__VALUE__) == LL_USART_PARITY_EVEN) \
                                    || ((__VALUE__) == LL_USART_PARITY_ODD))

Definition at line 86 of file stm32wbxx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_PRESCALER ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_PRESCALER_DIV1) \
                                        || ((__VALUE__) == LL_USART_PRESCALER_DIV2) \
                                        || ((__VALUE__) == LL_USART_PRESCALER_DIV4) \
                                        || ((__VALUE__) == LL_USART_PRESCALER_DIV6) \
                                        || ((__VALUE__) == LL_USART_PRESCALER_DIV8) \
                                        || ((__VALUE__) == LL_USART_PRESCALER_DIV10) \
                                        || ((__VALUE__) == LL_USART_PRESCALER_DIV12) \
                                        || ((__VALUE__) == LL_USART_PRESCALER_DIV16) \
                                        || ((__VALUE__) == LL_USART_PRESCALER_DIV32) \
                                        || ((__VALUE__) == LL_USART_PRESCALER_DIV64) \
                                        || ((__VALUE__) == LL_USART_PRESCALER_DIV128) \
                                        || ((__VALUE__) == LL_USART_PRESCALER_DIV256))

Definition at line 58 of file stm32wbxx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_STOPBITS ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_STOPBITS_0_5) \
                                      || ((__VALUE__) == LL_USART_STOPBITS_1) \
                                      || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
                                      || ((__VALUE__) == LL_USART_STOPBITS_2))

Definition at line 109 of file stm32wbxx_ll_usart.c.

Referenced by LL_USART_Init().

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LL_USART_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_USART_InitTypeDef Struct Reference
USART Exported Init structures

LL USART Init Structure definition. More...

#include <stm32wbxx_ll_usart.h>

Data Fields

uint32_t | PrescalerValue
uint32_t | BaudRate
uint32_t | DataWidth
uint32_t | StopBits
uint32_t | Parity
uint32_t | TransferDirection
uint32_t | HardwareFlowControl
uint32_t | OverSampling

Detailed Description

LL USART Init Structure definition.

Definition at line 93 of file stm32wbxx_ll_usart.h.

Field Documentation

uint32_t LL_USART_InitTypeDef::BaudRate

This field defines expected Usart communication baud rate.

This feature can be modified afterwards using unitary function LL_USART_SetBaudRate().

Definition at line 100 of file stm32wbxx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::DataWidth

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of Datawidth.

This feature can be modified afterwards using unitary function LL_USART_SetDataWidth().

Definition at line 104 of file stm32wbxx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::HardwareFlowControl

Specifies whether the hardware flow control mode is enabled or disabled. This parameter can be a value of Hardware Control.

This feature can be modified afterwards using unitary function LL_USART_SetHWFlowCtrl().

Definition at line 124 of file stm32wbxx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::OverSampling

Specifies whether USART oversampling mode is 16 or 8. This parameter can be a value of Oversampling.

This feature can be modified afterwards using unitary function LL_USART_SetOverSampling().

Definition at line 129 of file stm32wbxx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of Parity Control.

This feature can be modified afterwards using unitary function LL_USART_SetParity().

Definition at line 114 of file stm32wbxx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::PrescalerValue

Specifies the Prescaler to compute the communication baud rate. This parameter can be a value of Clock Source Prescaler.

This feature can be modified afterwards using unitary function LL_USART_SetPrescaler().

Definition at line 95 of file stm32wbxx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::StopBits

Specifies the number of stop bits transmitted. This parameter can be a value of Stop Bits.

This feature can be modified afterwards using unitary function LL_USART_SetStopBitsLength().

Definition at line 109 of file stm32wbxx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::TransferDirection

Specifies whether the Receive and/or Transmit mode is enabled or disabled. This parameter can be a value of Communication Direction.

This feature can be modified afterwards using unitary function LL_USART_SetTransferDirection().

Definition at line 119 of file stm32wbxx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

The documentation for this struct was generated from the following file:
  • stm32wbxx_ll_usart.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LL_USART_ClockInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_USART_ClockInitTypeDef Struct Reference
USART Exported Init structures

LL USART Clock Init Structure definition. More...

#include <stm32wbxx_ll_usart.h>

Data Fields

uint32_t | ClockOutput
uint32_t | ClockPolarity
uint32_t | ClockPhase
uint32_t | LastBitClockPulse

Detailed Description

LL USART Clock Init Structure definition.

Definition at line 139 of file stm32wbxx_ll_usart.h.

Field Documentation

uint32_t LL_USART_ClockInitTypeDef::ClockOutput

Specifies whether the USART clock is enabled or disabled. This parameter can be a value of Clock Signal.

USART HW configuration can be modified afterwards using unitary functions LL_USART_EnableSCLKOutput() or LL_USART_DisableSCLKOutput(). For more details, refer to description of this function.

Definition at line 141 of file stm32wbxx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_ClockStructInit().

uint32_t LL_USART_ClockInitTypeDef::ClockPhase

Specifies the clock transition on which the bit capture is made. This parameter can be a value of Clock Phase.

USART HW configuration can be modified afterwards using unitary functions LL_USART_SetClockPhase(). For more details, refer to description of this function.

Definition at line 154 of file stm32wbxx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_ClockStructInit().

uint32_t LL_USART_ClockInitTypeDef::ClockPolarity

Specifies the steady state of the serial clock. This parameter can be a value of Clock Polarity.

USART HW configuration can be modified afterwards using unitary functions LL_USART_SetClockPolarity(). For more details, refer to description of this function.

Definition at line 148 of file stm32wbxx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_ClockStructInit().

uint32_t LL_USART_ClockInitTypeDef::LastBitClockPulse

Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of Last Clock Pulse.

USART HW configuration can be modified afterwards using unitary functions LL_USART_SetLastClkPulseOutput(). For more details, refer to description of this function.

Definition at line 160 of file stm32wbxx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_ClockStructInit().

The documentation for this struct was generated from the following file:
  • stm32wbxx_ll_usart.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
USART Exported Constants

Flags defines which can be used with LL_USART_WriteReg function. More...

Defines

#define | LL_USART_ICR_PECF USART_ICR_PECF
#define | LL_USART_ICR_FECF USART_ICR_FECF
#define | LL_USART_ICR_NECF USART_ICR_NECF
#define | LL_USART_ICR_ORECF USART_ICR_ORECF
#define | LL_USART_ICR_IDLECF USART_ICR_IDLECF
#define | LL_USART_ICR_TXFECF USART_ICR_TXFECF
#define | LL_USART_ICR_TCCF USART_ICR_TCCF
#define | LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF
#define | LL_USART_ICR_LBDCF USART_ICR_LBDCF
#define | LL_USART_ICR_CTSCF USART_ICR_CTSCF
#define | LL_USART_ICR_RTOCF USART_ICR_RTOCF
#define | LL_USART_ICR_EOBCF USART_ICR_EOBCF
#define | LL_USART_ICR_UDRCF USART_ICR_UDRCF
#define | LL_USART_ICR_CMCF USART_ICR_CMCF
#define | LL_USART_ICR_WUCF USART_ICR_WUCF

Detailed Description

Flags defines which can be used with LL_USART_WriteReg function.

Define Documentation

#define LL_USART_ICR_CMCF USART_ICR_CMCF

Character match flag

Definition at line 196 of file stm32wbxx_ll_usart.h.

#define LL_USART_ICR_CTSCF USART_ICR_CTSCF

CTS flag

Definition at line 192 of file stm32wbxx_ll_usart.h.

#define LL_USART_ICR_EOBCF USART_ICR_EOBCF

End of block flag

Definition at line 194 of file stm32wbxx_ll_usart.h.

#define LL_USART_ICR_FECF USART_ICR_FECF

Framing error flag

Definition at line 184 of file stm32wbxx_ll_usart.h.

#define LL_USART_ICR_IDLECF USART_ICR_IDLECF

Idle line detected flag

Definition at line 187 of file stm32wbxx_ll_usart.h.

#define LL_USART_ICR_LBDCF USART_ICR_LBDCF

LIN break detection flag

Definition at line 191 of file stm32wbxx_ll_usart.h.

#define LL_USART_ICR_NECF USART_ICR_NECF

Noise error detected flag

Definition at line 185 of file stm32wbxx_ll_usart.h.

#define LL_USART_ICR_ORECF USART_ICR_ORECF

Overrun error flag

Definition at line 186 of file stm32wbxx_ll_usart.h.

#define LL_USART_ICR_PECF USART_ICR_PECF

Parity error flag

Definition at line 183 of file stm32wbxx_ll_usart.h.

#define LL_USART_ICR_RTOCF USART_ICR_RTOCF

Receiver timeout flag

Definition at line 193 of file stm32wbxx_ll_usart.h.

#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF

Transmission completed before guard time flag

Definition at line 190 of file stm32wbxx_ll_usart.h.

#define LL_USART_ICR_TCCF USART_ICR_TCCF

Transmission complete flag

Definition at line 189 of file stm32wbxx_ll_usart.h.

#define LL_USART_ICR_TXFECF USART_ICR_TXFECF

TX FIFO Empty Clear flag

Definition at line 188 of file stm32wbxx_ll_usart.h.

#define LL_USART_ICR_UDRCF USART_ICR_UDRCF

SPI Slave Underrun Clear flag

Definition at line 195 of file stm32wbxx_ll_usart.h.

#define LL_USART_ICR_WUCF USART_ICR_WUCF

Wakeup from Stop mode flag

Definition at line 197 of file stm32wbxx_ll_usart.h.

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
USART Exported Constants

Flags defines which can be used with LL_USART_ReadReg function. More...

Defines

#define | LL_USART_ISR_PE USART_ISR_PE
#define | LL_USART_ISR_FE USART_ISR_FE
#define | LL_USART_ISR_NE USART_ISR_NE
#define | LL_USART_ISR_ORE USART_ISR_ORE
#define | LL_USART_ISR_IDLE USART_ISR_IDLE
#define | LL_USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE
#define | LL_USART_ISR_TC USART_ISR_TC
#define | LL_USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF
#define | LL_USART_ISR_LBDF USART_ISR_LBDF
#define | LL_USART_ISR_CTSIF USART_ISR_CTSIF
#define | LL_USART_ISR_CTS USART_ISR_CTS
#define | LL_USART_ISR_RTOF USART_ISR_RTOF
#define | LL_USART_ISR_EOBF USART_ISR_EOBF
#define | LL_USART_ISR_UDR USART_ISR_UDR
#define | LL_USART_ISR_ABRE USART_ISR_ABRE
#define | LL_USART_ISR_ABRF USART_ISR_ABRF
#define | LL_USART_ISR_BUSY USART_ISR_BUSY
#define | LL_USART_ISR_CMF USART_ISR_CMF
#define | LL_USART_ISR_SBKF USART_ISR_SBKF
#define | LL_USART_ISR_RWU USART_ISR_RWU
#define | LL_USART_ISR_WUF USART_ISR_WUF
#define | LL_USART_ISR_TEACK USART_ISR_TEACK
#define | LL_USART_ISR_REACK USART_ISR_REACK
#define | LL_USART_ISR_TXFE USART_ISR_TXFE
#define | LL_USART_ISR_RXFF USART_ISR_RXFF
#define | LL_USART_ISR_TCBGT USART_ISR_TCBGT
#define | LL_USART_ISR_RXFT USART_ISR_RXFT
#define | LL_USART_ISR_TXFT USART_ISR_TXFT

Detailed Description

Flags defines which can be used with LL_USART_ReadReg function.

Define Documentation

#define LL_USART_ISR_ABRE USART_ISR_ABRE

Auto baud rate error flag

Definition at line 220 of file stm32wbxx_ll_usart.h.

#define LL_USART_ISR_ABRF USART_ISR_ABRF

Auto baud rate flag

Definition at line 221 of file stm32wbxx_ll_usart.h.

#define LL_USART_ISR_BUSY USART_ISR_BUSY

Busy flag

Definition at line 222 of file stm32wbxx_ll_usart.h.

#define LL_USART_ISR_CMF USART_ISR_CMF

Character match flag

Definition at line 223 of file stm32wbxx_ll_usart.h.

#define LL_USART_ISR_CTS USART_ISR_CTS

CTS flag

Definition at line 216 of file stm32wbxx_ll_usart.h.

#define LL_USART_ISR_CTSIF USART_ISR_CTSIF

CTS interrupt flag

Definition at line 215 of file stm32wbxx_ll_usart.h.

#define LL_USART_ISR_EOBF USART_ISR_EOBF

End of block flag

Definition at line 218 of file stm32wbxx_ll_usart.h.

#define LL_USART_ISR_FE USART_ISR_FE

Framing error flag

Definition at line 207 of file stm32wbxx_ll_usart.h.

#define LL_USART_ISR_IDLE USART_ISR_IDLE

Idle line detected flag

Definition at line 210 of file stm32wbxx_ll_usart.h.

#define LL_USART_ISR_LBDF USART_ISR_LBDF

LIN break detection flag

Definition at line 214 of file stm32wbxx_ll_usart.h.

#define LL_USART_ISR_NE USART_ISR_NE

Noise detected flag

Definition at line 208 of file stm32wbxx_ll_usart.h.

#define LL_USART_ISR_ORE USART_ISR_ORE

Overrun error flag

Definition at line 209 of file stm32wbxx_ll_usart.h.

#define LL_USART_ISR_PE USART_ISR_PE

Parity error flag

Definition at line 206 of file stm32wbxx_ll_usart.h.

#define LL_USART_ISR_REACK USART_ISR_REACK

Receive enable acknowledge flag

Definition at line 228 of file stm32wbxx_ll_usart.h.

#define LL_USART_ISR_RTOF USART_ISR_RTOF

Receiver timeout flag

Definition at line 217 of file stm32wbxx_ll_usart.h.

#define LL_USART_ISR_RWU USART_ISR_RWU

Receiver wakeup from Mute mode flag

Definition at line 225 of file stm32wbxx_ll_usart.h.

#define LL_USART_ISR_RXFF USART_ISR_RXFF

RX FIFO full flag

Definition at line 230 of file stm32wbxx_ll_usart.h.

#define LL_USART_ISR_RXFT USART_ISR_RXFT

RX FIFO threshold flag

Definition at line 232 of file stm32wbxx_ll_usart.h.

#define LL_USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE

Read data register or RX FIFO not empty flag

Definition at line 211 of file stm32wbxx_ll_usart.h.

#define LL_USART_ISR_SBKF USART_ISR_SBKF

Send break flag

Definition at line 224 of file stm32wbxx_ll_usart.h.

#define LL_USART_ISR_TC USART_ISR_TC

Transmission complete flag

Definition at line 212 of file stm32wbxx_ll_usart.h.

#define LL_USART_ISR_TCBGT USART_ISR_TCBGT

Transmission complete before guard time completion flag

Definition at line 231 of file stm32wbxx_ll_usart.h.

#define LL_USART_ISR_TEACK USART_ISR_TEACK

Transmit enable acknowledge flag

Definition at line 227 of file stm32wbxx_ll_usart.h.

#define LL_USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF

Transmit data register empty or TX FIFO Not Full flag

Definition at line 213 of file stm32wbxx_ll_usart.h.

#define LL_USART_ISR_TXFE USART_ISR_TXFE

TX FIFO empty flag

Definition at line 229 of file stm32wbxx_ll_usart.h.

#define LL_USART_ISR_TXFT USART_ISR_TXFT

TX FIFO threshold flag

Definition at line 233 of file stm32wbxx_ll_usart.h.

#define LL_USART_ISR_UDR USART_ISR_UDR

SPI Slave underrun error flag

Definition at line 219 of file stm32wbxx_ll_usart.h.

#define LL_USART_ISR_WUF USART_ISR_WUF

Wakeup from Stop mode flag

Definition at line 226 of file stm32wbxx_ll_usart.h.

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IT Defines

Defines
IT Defines
USART Exported Constants

IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions. More...

Defines

#define | LL_USART_CR1_IDLEIE USART_CR1_IDLEIE
#define | LL_USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE
#define | LL_USART_CR1_TCIE USART_CR1_TCIE
#define | LL_USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE
#define | LL_USART_CR1_PEIE USART_CR1_PEIE
#define | LL_USART_CR1_CMIE USART_CR1_CMIE
#define | LL_USART_CR1_RTOIE USART_CR1_RTOIE
#define | LL_USART_CR1_EOBIE USART_CR1_EOBIE
#define | LL_USART_CR1_TXFEIE USART_CR1_TXFEIE
#define | LL_USART_CR1_RXFFIE USART_CR1_RXFFIE
#define | LL_USART_CR2_LBDIE USART_CR2_LBDIE
#define | LL_USART_CR3_EIE USART_CR3_EIE
#define | LL_USART_CR3_CTSIE USART_CR3_CTSIE
#define | LL_USART_CR3_WUFIE USART_CR3_WUFIE
#define | LL_USART_CR3_TXFTIE USART_CR3_TXFTIE
#define | LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE
#define | LL_USART_CR3_RXFTIE USART_CR3_RXFTIE

Detailed Description

IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions.

Define Documentation

#define LL_USART_CR1_CMIE USART_CR1_CMIE

Character match interrupt enable

Definition at line 247 of file stm32wbxx_ll_usart.h.

#define LL_USART_CR1_EOBIE USART_CR1_EOBIE

End of Block interrupt enable

Definition at line 249 of file stm32wbxx_ll_usart.h.

#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE

IDLE interrupt enable

Definition at line 242 of file stm32wbxx_ll_usart.h.

#define LL_USART_CR1_PEIE USART_CR1_PEIE

Parity error

Definition at line 246 of file stm32wbxx_ll_usart.h.

#define LL_USART_CR1_RTOIE USART_CR1_RTOIE

Receiver timeout interrupt enable

Definition at line 248 of file stm32wbxx_ll_usart.h.

#define LL_USART_CR1_RXFFIE USART_CR1_RXFFIE

RX FIFO full interrupt enable

Definition at line 251 of file stm32wbxx_ll_usart.h.

#define LL_USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE

Read data register and RXFIFO not empty interrupt enable

Definition at line 243 of file stm32wbxx_ll_usart.h.

#define LL_USART_CR1_TCIE USART_CR1_TCIE

Transmission complete interrupt enable

Definition at line 244 of file stm32wbxx_ll_usart.h.

#define LL_USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE

Transmit data register empty and TX FIFO not full interrupt enable

Definition at line 245 of file stm32wbxx_ll_usart.h.

#define LL_USART_CR1_TXFEIE USART_CR1_TXFEIE

TX FIFO empty interrupt enable

Definition at line 250 of file stm32wbxx_ll_usart.h.

#define LL_USART_CR2_LBDIE USART_CR2_LBDIE

LIN break detection interrupt enable

Definition at line 252 of file stm32wbxx_ll_usart.h.

#define LL_USART_CR3_CTSIE USART_CR3_CTSIE

CTS interrupt enable

Definition at line 254 of file stm32wbxx_ll_usart.h.

#define LL_USART_CR3_EIE USART_CR3_EIE

Error interrupt enable

Definition at line 253 of file stm32wbxx_ll_usart.h.

#define LL_USART_CR3_RXFTIE USART_CR3_RXFTIE

RX FIFO threshold interrupt enable

Definition at line 258 of file stm32wbxx_ll_usart.h.

#define LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE

Transmission complete before guard time interrupt enable

Definition at line 257 of file stm32wbxx_ll_usart.h.

#define LL_USART_CR3_TXFTIE USART_CR3_TXFTIE

TX FIFO threshold interrupt enable

Definition at line 256 of file stm32wbxx_ll_usart.h.

#define LL_USART_CR3_WUFIE USART_CR3_WUFIE

Wakeup from Stop mode interrupt enable

Definition at line 255 of file stm32wbxx_ll_usart.h.

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FIFO Threshold

Defines
FIFO Threshold
USART Exported Constants

Defines

#define | LL_USART_FIFOTHRESHOLD_1_8 0x00000000U
#define | LL_USART_FIFOTHRESHOLD_1_4 0x00000001U
#define | LL_USART_FIFOTHRESHOLD_1_2 0x00000002U
#define | LL_USART_FIFOTHRESHOLD_3_4 0x00000003U
#define | LL_USART_FIFOTHRESHOLD_7_8 0x00000004U
#define | LL_USART_FIFOTHRESHOLD_8_8 0x00000005U

Define Documentation

#define LL_USART_FIFOTHRESHOLD_1_2 0x00000002U

FIFO reaches 1/2 of its depth

Definition at line 268 of file stm32wbxx_ll_usart.h.

#define LL_USART_FIFOTHRESHOLD_1_4 0x00000001U

FIFO reaches 1/4 of its depth

Definition at line 267 of file stm32wbxx_ll_usart.h.

#define LL_USART_FIFOTHRESHOLD_1_8 0x00000000U

FIFO reaches 1/8 of its depth

Definition at line 266 of file stm32wbxx_ll_usart.h.

#define LL_USART_FIFOTHRESHOLD_3_4 0x00000003U

FIFO reaches 3/4 of its depth

Definition at line 269 of file stm32wbxx_ll_usart.h.

#define LL_USART_FIFOTHRESHOLD_7_8 0x00000004U

FIFO reaches 7/8 of its depth

Definition at line 270 of file stm32wbxx_ll_usart.h.

#define LL_USART_FIFOTHRESHOLD_8_8 0x00000005U

FIFO becomes empty for TX and full for RX

Definition at line 271 of file stm32wbxx_ll_usart.h.

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STM32WB55xx HAL User Manual: Communication Direction

Defines
Communication Direction
USART Exported Constants

Defines

#define | LL_USART_DIRECTION_NONE 0x00000000U
#define | LL_USART_DIRECTION_RX USART_CR1_RE
#define | LL_USART_DIRECTION_TX USART_CR1_TE
#define | LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)

Define Documentation

#define LL_USART_DIRECTION_NONE 0x00000000U

Transmitter and Receiver are disabled

Definition at line 279 of file stm32wbxx_ll_usart.h.

#define LL_USART_DIRECTION_RX USART_CR1_RE

Transmitter is disabled and Receiver is enabled

Definition at line 280 of file stm32wbxx_ll_usart.h.

#define LL_USART_DIRECTION_TX USART_CR1_TE

Transmitter is enabled and Receiver is disabled

Definition at line 281 of file stm32wbxx_ll_usart.h.

#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)

Transmitter and Receiver are enabled

Definition at line 282 of file stm32wbxx_ll_usart.h.

Referenced by LL_USART_StructInit().

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STM32WB55xx HAL User Manual: Parity Control

Defines
Parity Control
USART Exported Constants

Defines

#define | LL_USART_PARITY_NONE 0x00000000U
#define | LL_USART_PARITY_EVEN USART_CR1_PCE
#define | LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Define Documentation

#define LL_USART_PARITY_EVEN USART_CR1_PCE

Parity control enabled and Even Parity is selected

Definition at line 291 of file stm32wbxx_ll_usart.h.

#define LL_USART_PARITY_NONE 0x00000000U

Parity control disabled

Definition at line 290 of file stm32wbxx_ll_usart.h.

Referenced by LL_USART_StructInit().

#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Parity control enabled and Odd Parity is selected

Definition at line 292 of file stm32wbxx_ll_usart.h.

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STM32WB55xx HAL User Manual: Wakeup

Defines
Wakeup
USART Exported Constants

Defines

#define | LL_USART_WAKEUP_IDLELINE 0x00000000U
#define | LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE

Define Documentation

#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE

USART wake up from Mute mode on Address Mark

Definition at line 301 of file stm32wbxx_ll_usart.h.

#define LL_USART_WAKEUP_IDLELINE 0x00000000U

USART wake up from Mute mode on Idle Line

Definition at line 300 of file stm32wbxx_ll_usart.h.

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STM32WB55xx HAL User Manual: Datawidth

Defines
Datawidth
USART Exported Constants

Defines

#define | LL_USART_DATAWIDTH_7B USART_CR1_M1
#define | LL_USART_DATAWIDTH_8B 0x00000000U
#define | LL_USART_DATAWIDTH_9B USART_CR1_M0

Define Documentation

#define LL_USART_DATAWIDTH_7B USART_CR1_M1

7 bits word length : Start bit, 7 data bits, n stop bits

Definition at line 309 of file stm32wbxx_ll_usart.h.

#define LL_USART_DATAWIDTH_8B 0x00000000U

8 bits word length : Start bit, 8 data bits, n stop bits

Definition at line 310 of file stm32wbxx_ll_usart.h.

Referenced by LL_USART_StructInit().

#define LL_USART_DATAWIDTH_9B USART_CR1_M0

9 bits word length : Start bit, 9 data bits, n stop bits

Definition at line 311 of file stm32wbxx_ll_usart.h.

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STM32WB55xx HAL User Manual: Oversampling

Defines
Oversampling
USART Exported Constants

Defines

#define | LL_USART_OVERSAMPLING_16 0x00000000U
#define | LL_USART_OVERSAMPLING_8 USART_CR1_OVER8

Define Documentation

#define LL_USART_OVERSAMPLING_16 0x00000000U

Oversampling by 16

Definition at line 319 of file stm32wbxx_ll_usart.h.

Referenced by LL_USART_StructInit().

#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8

Oversampling by 8

Definition at line 320 of file stm32wbxx_ll_usart.h.

Referenced by LL_USART_GetBaudRate(), and LL_USART_SetBaudRate().

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STM32WB55xx HAL User Manual: Clock Signal

Defines
Clock Signal
USART Exported Constants

Defines

#define | LL_USART_CLOCK_DISABLE 0x00000000U
#define | LL_USART_CLOCK_ENABLE USART_CR2_CLKEN

Define Documentation

#define LL_USART_CLOCK_DISABLE 0x00000000U

Clock signal not provided

Definition at line 330 of file stm32wbxx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_ClockStructInit().

#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN

Clock signal provided

Definition at line 331 of file stm32wbxx_ll_usart.h.

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STM32WB55xx HAL User Manual: Last Clock Pulse

Defines
Last Clock Pulse
USART Exported Constants

Defines

#define | LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U
#define | LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL

Define Documentation

#define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U

The clock pulse of the last data bit is not output to the SCLK pin

Definition at line 340 of file stm32wbxx_ll_usart.h.

Referenced by LL_USART_ClockStructInit().

#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL

The clock pulse of the last data bit is output to the SCLK pin

Definition at line 341 of file stm32wbxx_ll_usart.h.

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STM32WB55xx HAL User Manual: Clock Phase

Defines
Clock Phase
USART Exported Constants

Defines

#define | LL_USART_PHASE_1EDGE 0x00000000U
#define | LL_USART_PHASE_2EDGE USART_CR2_CPHA

Define Documentation

#define LL_USART_PHASE_1EDGE 0x00000000U

The first clock transition is the first data capture edge

Definition at line 349 of file stm32wbxx_ll_usart.h.

Referenced by LL_USART_ClockStructInit().

#define LL_USART_PHASE_2EDGE USART_CR2_CPHA

The second clock transition is the first data capture edge

Definition at line 350 of file stm32wbxx_ll_usart.h.

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STM32WB55xx HAL User Manual: Clock Polarity

Defines
Clock Polarity
USART Exported Constants

Defines

#define | LL_USART_POLARITY_LOW 0x00000000U
#define | LL_USART_POLARITY_HIGH USART_CR2_CPOL

Define Documentation

#define LL_USART_POLARITY_HIGH USART_CR2_CPOL

Steady high value on SCLK pin outside transmission window

Definition at line 359 of file stm32wbxx_ll_usart.h.

#define LL_USART_POLARITY_LOW 0x00000000U

Steady low value on SCLK pin outside transmission window

Definition at line 358 of file stm32wbxx_ll_usart.h.

Referenced by LL_USART_ClockStructInit().

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STM32WB55xx HAL User Manual: Clock Source Prescaler

Defines
Clock Source Prescaler
USART Exported Constants

Defines

#define | LL_USART_PRESCALER_DIV1 0x00000000U
#define | LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1)
#define | LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2)
#define | LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1)
#define | LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3)
#define | LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1)
#define | LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)

Define Documentation

#define LL_USART_PRESCALER_DIV1 0x00000000U

Input clock not devided

Definition at line 367 of file stm32wbxx_ll_usart.h.

Referenced by LL_USART_StructInit().

#define LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0)

Input clock devided by 10

Definition at line 372 of file stm32wbxx_ll_usart.h.

#define LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1)

Input clock devided by 12

Definition at line 373 of file stm32wbxx_ll_usart.h.

#define LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1)

Input clock devided by 128

Definition at line 377 of file stm32wbxx_ll_usart.h.

#define LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)

Input clock devided by 16

Definition at line 374 of file stm32wbxx_ll_usart.h.

#define LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0)

Input clock devided by 2

Definition at line 368 of file stm32wbxx_ll_usart.h.

#define LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)

Input clock devided by 256

Definition at line 378 of file stm32wbxx_ll_usart.h.

#define LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3)

Input clock devided by 32

Definition at line 375 of file stm32wbxx_ll_usart.h.

#define LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1)

Input clock devided by 4

Definition at line 369 of file stm32wbxx_ll_usart.h.

#define LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)

Input clock devided by 6

Definition at line 370 of file stm32wbxx_ll_usart.h.

#define LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0)

Input clock devided by 64

Definition at line 376 of file stm32wbxx_ll_usart.h.

#define LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2)

Input clock devided by 8

Definition at line 371 of file stm32wbxx_ll_usart.h.

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STM32WB55xx HAL User Manual: Stop Bits

Defines
Stop Bits
USART Exported Constants

Defines

#define | LL_USART_STOPBITS_0_5 USART_CR2_STOP_0
#define | LL_USART_STOPBITS_1 0x00000000U
#define | LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define | LL_USART_STOPBITS_2 USART_CR2_STOP_1

Define Documentation

#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0

0.5 stop bit

Definition at line 386 of file stm32wbxx_ll_usart.h.

#define LL_USART_STOPBITS_1 0x00000000U

1 stop bit

Definition at line 387 of file stm32wbxx_ll_usart.h.

Referenced by LL_USART_StructInit().

#define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)

1.5 stop bits

Definition at line 388 of file stm32wbxx_ll_usart.h.

#define LL_USART_STOPBITS_2 USART_CR2_STOP_1

2 stop bits

Definition at line 389 of file stm32wbxx_ll_usart.h.

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STM32WB55xx HAL User Manual: TX RX Pins Swap

Defines
TX RX Pins Swap
USART Exported Constants

Defines

#define | LL_USART_TXRX_STANDARD 0x00000000U
#define | LL_USART_TXRX_SWAPPED (USART_CR2_SWAP)

Define Documentation

#define LL_USART_TXRX_STANDARD 0x00000000U

TX/RX pins are used as defined in standard pinout

Definition at line 397 of file stm32wbxx_ll_usart.h.

#define LL_USART_TXRX_SWAPPED (USART_CR2_SWAP)

TX and RX pins functions are swapped.

Definition at line 398 of file stm32wbxx_ll_usart.h.

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STM32WB55xx HAL User Manual: RX Pin Active Level Inversion

Defines
RX Pin Active Level Inversion
USART Exported Constants

Defines

#define | LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U
#define | LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV)

Define Documentation

#define LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV)

RX pin signal values are inverted.

Definition at line 407 of file stm32wbxx_ll_usart.h.

#define LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U

RX pin signal works using the standard logic levels

Definition at line 406 of file stm32wbxx_ll_usart.h.

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STM32WB55xx HAL User Manual: TX Pin Active Level Inversion

Defines
TX Pin Active Level Inversion
USART Exported Constants

Defines

#define | LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U
#define | LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV)

Define Documentation

#define LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV)

TX pin signal values are inverted.

Definition at line 416 of file stm32wbxx_ll_usart.h.

#define LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U

TX pin signal works using the standard logic levels

Definition at line 415 of file stm32wbxx_ll_usart.h.

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STM32WB55xx HAL User Manual: Binary Data Inversion

Defines
Binary Data Inversion
USART Exported Constants

Defines

#define | LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U
#define | LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV

Define Documentation

#define LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV

Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted.

Definition at line 425 of file stm32wbxx_ll_usart.h.

#define LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U

Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)

Definition at line 424 of file stm32wbxx_ll_usart.h.

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STM32WB55xx HAL User Manual: Bit Order

Defines
Bit Order
USART Exported Constants

Defines

#define | LL_USART_BITORDER_LSBFIRST 0x00000000U
#define | LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST

Define Documentation

#define LL_USART_BITORDER_LSBFIRST 0x00000000U

data is transmitted/received with data bit 0 first, following the start bit

Definition at line 433 of file stm32wbxx_ll_usart.h.

#define LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST

data is transmitted/received with the MSB first, following the start bit

Definition at line 434 of file stm32wbxx_ll_usart.h.

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STM32WB55xx HAL User Manual: Autobaud Detection

Defines
Autobaud Detection
USART Exported Constants

Defines

#define | LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U
#define | LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0
#define | LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1
#define | LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0)

Define Documentation

#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0)

0x55 frame detection

Definition at line 445 of file stm32wbxx_ll_usart.h.

#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1

0x7F frame detection

Definition at line 444 of file stm32wbxx_ll_usart.h.

#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0

Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx

Definition at line 443 of file stm32wbxx_ll_usart.h.

#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U

Measurement of the start bit is used to detect the baud rate

Definition at line 442 of file stm32wbxx_ll_usart.h.

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STM32WB55xx HAL User Manual: Address Length Detection

Defines
Address Length Detection
USART Exported Constants

Defines

#define | LL_USART_ADDRESS_DETECT_4B 0x00000000U
#define | LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7

Define Documentation

#define LL_USART_ADDRESS_DETECT_4B 0x00000000U

4-bit address detection method selected

Definition at line 453 of file stm32wbxx_ll_usart.h.

#define LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7

7-bit address detection (in 8-bit data mode) method selected

Definition at line 454 of file stm32wbxx_ll_usart.h.

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STM32WB55xx HAL User Manual: Hardware Control

Defines
Hardware Control
USART Exported Constants

Defines

#define | LL_USART_HWCONTROL_NONE 0x00000000U
#define | LL_USART_HWCONTROL_RTS USART_CR3_RTSE
#define | LL_USART_HWCONTROL_CTS USART_CR3_CTSE
#define | LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)

Define Documentation

#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE

CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0)

Definition at line 464 of file stm32wbxx_ll_usart.h.

#define LL_USART_HWCONTROL_NONE 0x00000000U

CTS and RTS hardware flow control disabled

Definition at line 462 of file stm32wbxx_ll_usart.h.

Referenced by LL_USART_StructInit().

#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE

RTS output enabled, data is only requested when there is space in the receive buffer

Definition at line 463 of file stm32wbxx_ll_usart.h.

#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)

CTS and RTS hardware flow control enabled

Definition at line 465 of file stm32wbxx_ll_usart.h.

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STM32WB55xx HAL User Manual: Wakeup Activation

Defines
Wakeup Activation
USART Exported Constants

Defines

#define | LL_USART_WAKEUP_ON_ADDRESS 0x00000000U
#define | LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1
#define | LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)

Define Documentation

#define LL_USART_WAKEUP_ON_ADDRESS 0x00000000U

Wake up active on address match

Definition at line 473 of file stm32wbxx_ll_usart.h.

#define LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)

Wake up active on RXNE

Definition at line 475 of file stm32wbxx_ll_usart.h.

#define LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1

Wake up active on Start bit detection

Definition at line 474 of file stm32wbxx_ll_usart.h.

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STM32WB55xx HAL User Manual: IrDA Power

Defines
IrDA Power
USART Exported Constants

Defines

#define | LL_USART_IRDA_POWER_NORMAL 0x00000000U
#define | LL_USART_IRDA_POWER_LOW USART_CR3_IRLP

Define Documentation

#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP

IrDA low power mode

Definition at line 484 of file stm32wbxx_ll_usart.h.

#define LL_USART_IRDA_POWER_NORMAL 0x00000000U

IrDA normal power mode

Definition at line 483 of file stm32wbxx_ll_usart.h.

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STM32WB55xx HAL User Manual: LIN Break Detection Length

Defines
LIN Break Detection Length
USART Exported Constants

Defines

#define | LL_USART_LINBREAK_DETECT_10B 0x00000000U
#define | LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL

Define Documentation

#define LL_USART_LINBREAK_DETECT_10B 0x00000000U

10-bit break detection method selected

Definition at line 492 of file stm32wbxx_ll_usart.h.

#define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL

11-bit break detection method selected

Definition at line 493 of file stm32wbxx_ll_usart.h.

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STM32WB55xx HAL User Manual: Driver Enable Polarity

Defines
Driver Enable Polarity
USART Exported Constants

Defines

#define | LL_USART_DE_POLARITY_HIGH 0x00000000U
#define | LL_USART_DE_POLARITY_LOW USART_CR3_DEP

Define Documentation

#define LL_USART_DE_POLARITY_HIGH 0x00000000U

DE signal is active high

Definition at line 501 of file stm32wbxx_ll_usart.h.

#define LL_USART_DE_POLARITY_LOW USART_CR3_DEP

DE signal is active low

Definition at line 502 of file stm32wbxx_ll_usart.h.

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STM32WB55xx HAL User Manual: DMA Register Data

Defines
DMA Register Data
USART Exported Constants

Defines

#define | LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U
#define | LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U

Define Documentation

#define LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U

Get address of data register used for reception

Definition at line 511 of file stm32wbxx_ll_usart.h.

#define LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U

Get address of data register used for transmission

Definition at line 510 of file stm32wbxx_ll_usart.h.

Referenced by LL_USART_DMA_GetRegAddr().

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
USART Exported Macros

Defines

#define | LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in USART register.
#define | LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in USART register.

Define Documentation

#define LL_USART_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in USART register.

Parameters:
__INSTANCE__ | USART Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 544 of file stm32wbxx_ll_usart.h.

#define LL_USART_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in USART register.

Parameters:
__INSTANCE__ | USART Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 536 of file stm32wbxx_ll_usart.h.

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Exported_Macros_Helper

Defines
Exported_Macros_Helper
USART Exported Macros

Defines

#define | __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (((((__PERIPHCLK__)/(uint32_t)(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U) + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
#define | __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((__PERIPHCLK__)/(uint32_t)(USART_PRESCALER_TAB[(__PRESCALER__)])) + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)

Define Documentation

#define __LL_USART_DIV_SAMPLING16 | ( | __PERIPHCLK__,
 |  | __PRESCALER__,
 |  | __BAUDRATE__
 | ) | ((((__PERIPHCLK__)/(uint32_t)(USART_PRESCALER_TAB[(__PRESCALER__)])) + ((__BAUDRATE__)/2U))/(__BAUDRATE__))

Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)

Parameters:
__PERIPHCLK__ | Peripheral Clock frequency used for USART instance
__PRESCALER__ This parameter can be one of the following values:
  • LL_USART_PRESCALER_DIV1
  • LL_USART_PRESCALER_DIV2
  • LL_USART_PRESCALER_DIV4
  • LL_USART_PRESCALER_DIV6
  • LL_USART_PRESCALER_DIV8
  • LL_USART_PRESCALER_DIV10
  • LL_USART_PRESCALER_DIV12
  • LL_USART_PRESCALER_DIV16
  • LL_USART_PRESCALER_DIV32
  • LL_USART_PRESCALER_DIV64
  • LL_USART_PRESCALER_DIV128
  • LL_USART_PRESCALER_DIV256
__BAUDRATE__ | Baud rate value to achieve
Return values:
USARTDIV value to be used for BRR register filling in OverSampling_16 case

Definition at line 595 of file stm32wbxx_ll_usart.h.

Referenced by LL_USART_SetBaudRate().

#define __LL_USART_DIV_SAMPLING8 | ( | __PERIPHCLK__,
 |  | __PRESCALER__,
 |  | __BAUDRATE__
 | ) | (((((__PERIPHCLK__)/(uint32_t)(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U) + ((__BAUDRATE__)/2U))/(__BAUDRATE__))

Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)

Parameters:
__PERIPHCLK__ | Peripheral Clock frequency used for USART instance
__PRESCALER__ This parameter can be one of the following values:
  • LL_USART_PRESCALER_DIV1
  • LL_USART_PRESCALER_DIV2
  • LL_USART_PRESCALER_DIV4
  • LL_USART_PRESCALER_DIV6
  • LL_USART_PRESCALER_DIV8
  • LL_USART_PRESCALER_DIV10
  • LL_USART_PRESCALER_DIV12
  • LL_USART_PRESCALER_DIV16
  • LL_USART_PRESCALER_DIV32
  • LL_USART_PRESCALER_DIV64
  • LL_USART_PRESCALER_DIV128
  • LL_USART_PRESCALER_DIV256
__BAUDRATE__ | Baud rate value to achieve
Return values:
USARTDIV value to be used for BRR register filling in OverSampling_8 case

Definition at line 573 of file stm32wbxx_ll_usart.h.

Referenced by LL_USART_SetBaudRate().

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Configuration functions

Functions
Configuration functions
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_Enable (USART_TypeDef *USARTx)
USART Enable.
__STATIC_INLINE void | LL_USART_Disable (USART_TypeDef *USARTx)
USART Disable (all USART prescalers and outputs are disabled)
__STATIC_INLINE uint32_t | LL_USART_IsEnabled (USART_TypeDef *USARTx)
Indicate if USART is enabled.
__STATIC_INLINE void | LL_USART_EnableFIFO (USART_TypeDef *USARTx)
FIFO Mode Enable.
__STATIC_INLINE void | LL_USART_DisableFIFO (USART_TypeDef *USARTx)
FIFO Mode Disable.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledFIFO (USART_TypeDef *USARTx)
Indicate if FIFO Mode is enabled.
__STATIC_INLINE void | LL_USART_SetTXFIFOThreshold (USART_TypeDef *USARTx, uint32_t Threshold)
Configure TX FIFO Threshold.
__STATIC_INLINE uint32_t | LL_USART_GetTXFIFOThreshold (USART_TypeDef *USARTx)
Return TX FIFO Threshold Configuration.
__STATIC_INLINE void | LL_USART_SetRXFIFOThreshold (USART_TypeDef *USARTx, uint32_t Threshold)
Configure RX FIFO Threshold.
__STATIC_INLINE uint32_t | LL_USART_GetRXFIFOThreshold (USART_TypeDef *USARTx)
Return RX FIFO Threshold Configuration.
__STATIC_INLINE void | LL_USART_ConfigFIFOsThreshold (USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold)
Configure TX and RX FIFOs Threshold.
__STATIC_INLINE void | LL_USART_EnableInStopMode (USART_TypeDef *USARTx)
USART enabled in STOP Mode.
__STATIC_INLINE void | LL_USART_DisableInStopMode (USART_TypeDef *USARTx)
USART disabled in STOP Mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledInStopMode (USART_TypeDef *USARTx)
Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
__STATIC_INLINE void | LL_USART_EnableDirectionRx (USART_TypeDef *USARTx)
Receiver Enable (Receiver is enabled and begins searching for a start bit)
__STATIC_INLINE void | LL_USART_DisableDirectionRx (USART_TypeDef *USARTx)
Receiver Disable.
__STATIC_INLINE void | LL_USART_EnableDirectionTx (USART_TypeDef *USARTx)
Transmitter Enable.
__STATIC_INLINE void | LL_USART_DisableDirectionTx (USART_TypeDef *USARTx)
Transmitter Disable.
__STATIC_INLINE void | LL_USART_SetTransferDirection (USART_TypeDef *USARTx, uint32_t TransferDirection)
Configure simultaneously enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE uint32_t | LL_USART_GetTransferDirection (USART_TypeDef *USARTx)
Return enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE void | LL_USART_SetParity (USART_TypeDef *USARTx, uint32_t Parity)
Configure Parity (enabled/disabled and parity mode if enabled).
__STATIC_INLINE uint32_t | LL_USART_GetParity (USART_TypeDef *USARTx)
Return Parity configuration (enabled/disabled and parity mode if enabled)
__STATIC_INLINE void | LL_USART_SetWakeUpMethod (USART_TypeDef *USARTx, uint32_t Method)
Set Receiver Wake Up method from Mute mode.
__STATIC_INLINE uint32_t | LL_USART_GetWakeUpMethod (USART_TypeDef *USARTx)
Return Receiver Wake Up method from Mute mode.
__STATIC_INLINE void | LL_USART_SetDataWidth (USART_TypeDef *USARTx, uint32_t DataWidth)
Set Word length (i.e.
__STATIC_INLINE uint32_t | LL_USART_GetDataWidth (USART_TypeDef *USARTx)
Return Word length (i.e.
__STATIC_INLINE void | LL_USART_EnableMuteMode (USART_TypeDef *USARTx)
Allow switch between Mute Mode and Active mode.
__STATIC_INLINE void | LL_USART_DisableMuteMode (USART_TypeDef *USARTx)
Prevent Mute Mode use.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledMuteMode (USART_TypeDef *USARTx)
Indicate if switch between Mute Mode and Active mode is allowed.
__STATIC_INLINE void | LL_USART_SetOverSampling (USART_TypeDef *USARTx, uint32_t OverSampling)
Set Oversampling to 8-bit or 16-bit mode.
__STATIC_INLINE uint32_t | LL_USART_GetOverSampling (USART_TypeDef *USARTx)
Return Oversampling mode.
__STATIC_INLINE void | LL_USART_SetLastClkPulseOutput (USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
Configure if Clock pulse of the last data bit is output to the SCLK pin or not.
__STATIC_INLINE uint32_t | LL_USART_GetLastClkPulseOutput (USART_TypeDef *USARTx)
Retrieve Clock pulse of the last data bit output configuration (Last bit Clock pulse output to the SCLK pin or not)
__STATIC_INLINE void | LL_USART_SetClockPhase (USART_TypeDef *USARTx, uint32_t ClockPhase)
Select the phase of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE uint32_t | LL_USART_GetClockPhase (USART_TypeDef *USARTx)
Return phase of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE void | LL_USART_SetClockPolarity (USART_TypeDef *USARTx, uint32_t ClockPolarity)
Select the polarity of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE uint32_t | LL_USART_GetClockPolarity (USART_TypeDef *USARTx)
Return polarity of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE void | LL_USART_ConfigClock (USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
__STATIC_INLINE void | LL_USART_SetPrescaler (USART_TypeDef *USARTx, uint32_t PrescalerValue)
Configure Clock source prescaler for baudrate generator and oversampling.
__STATIC_INLINE uint32_t | LL_USART_GetPrescaler (USART_TypeDef *USARTx)
Retrieve the Clock source prescaler for baudrate generator and oversampling.
__STATIC_INLINE void | LL_USART_EnableSCLKOutput (USART_TypeDef *USARTx)
Enable Clock output on SCLK pin.
__STATIC_INLINE void | LL_USART_DisableSCLKOutput (USART_TypeDef *USARTx)
Disable Clock output on SCLK pin.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSCLKOutput (USART_TypeDef *USARTx)
Indicate if Clock output on SCLK pin is enabled.
__STATIC_INLINE void | LL_USART_SetStopBitsLength (USART_TypeDef *USARTx, uint32_t StopBits)
Set the length of the stop bits.
__STATIC_INLINE uint32_t | LL_USART_GetStopBitsLength (USART_TypeDef *USARTx)
Retrieve the length of the stop bits.
__STATIC_INLINE void | LL_USART_ConfigCharacter (USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity, uint32_t StopBits)
Configure Character frame format (Datawidth, Parity control, Stop Bits)
__STATIC_INLINE void | LL_USART_SetTXRXSwap (USART_TypeDef *USARTx, uint32_t SwapConfig)
Configure TX/RX pins swapping setting.
__STATIC_INLINE uint32_t | LL_USART_GetTXRXSwap (USART_TypeDef *USARTx)
Retrieve TX/RX pins swapping configuration.
__STATIC_INLINE void | LL_USART_SetRXPinLevel (USART_TypeDef *USARTx, uint32_t PinInvMethod)
Configure RX pin active level logic.
__STATIC_INLINE uint32_t | LL_USART_GetRXPinLevel (USART_TypeDef *USARTx)
Retrieve RX pin active level logic configuration.
__STATIC_INLINE void | LL_USART_SetTXPinLevel (USART_TypeDef *USARTx, uint32_t PinInvMethod)
Configure TX pin active level logic.
__STATIC_INLINE uint32_t | LL_USART_GetTXPinLevel (USART_TypeDef *USARTx)
Retrieve TX pin active level logic configuration.
__STATIC_INLINE void | LL_USART_SetBinaryDataLogic (USART_TypeDef *USARTx, uint32_t DataLogic)
Configure Binary data logic.
__STATIC_INLINE uint32_t | LL_USART_GetBinaryDataLogic (USART_TypeDef *USARTx)
Retrieve Binary data configuration.
__STATIC_INLINE void | LL_USART_SetTransferBitOrder (USART_TypeDef *USARTx, uint32_t BitOrder)
Configure transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE uint32_t | LL_USART_GetTransferBitOrder (USART_TypeDef *USARTx)
Return transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE void | LL_USART_EnableAutoBaudRate (USART_TypeDef *USARTx)
Enable Auto Baud-Rate Detection.
__STATIC_INLINE void | LL_USART_DisableAutoBaudRate (USART_TypeDef *USARTx)
Disable Auto Baud-Rate Detection.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledAutoBaud (USART_TypeDef *USARTx)
Indicate if Auto Baud-Rate Detection mechanism is enabled.
__STATIC_INLINE void | LL_USART_SetAutoBaudRateMode (USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
Set Auto Baud-Rate mode bits.
__STATIC_INLINE uint32_t | LL_USART_GetAutoBaudRateMode (USART_TypeDef *USARTx)
Return Auto Baud-Rate mode.
__STATIC_INLINE void | LL_USART_EnableRxTimeout (USART_TypeDef *USARTx)
Enable Receiver Timeout.
__STATIC_INLINE void | LL_USART_DisableRxTimeout (USART_TypeDef *USARTx)
Disable Receiver Timeout.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledRxTimeout (USART_TypeDef *USARTx)
Indicate if Receiver Timeout feature is enabled.
__STATIC_INLINE void | LL_USART_ConfigNodeAddress (USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
Set Address of the USART node.
__STATIC_INLINE uint32_t | LL_USART_GetNodeAddress (USART_TypeDef *USARTx)
Return 8 bit Address of the USART node as set in ADD field of CR2.
__STATIC_INLINE uint32_t | LL_USART_GetNodeAddressLen (USART_TypeDef *USARTx)
Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
__STATIC_INLINE void | LL_USART_EnableRTSHWFlowCtrl (USART_TypeDef *USARTx)
Enable RTS HW Flow Control.
__STATIC_INLINE void | LL_USART_DisableRTSHWFlowCtrl (USART_TypeDef *USARTx)
Disable RTS HW Flow Control.
__STATIC_INLINE void | LL_USART_EnableCTSHWFlowCtrl (USART_TypeDef *USARTx)
Enable CTS HW Flow Control.
__STATIC_INLINE void | LL_USART_DisableCTSHWFlowCtrl (USART_TypeDef *USARTx)
Disable CTS HW Flow Control.
__STATIC_INLINE void | LL_USART_SetHWFlowCtrl (USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
Configure HW Flow Control mode (both CTS and RTS)
__STATIC_INLINE uint32_t | LL_USART_GetHWFlowCtrl (USART_TypeDef *USARTx)
Return HW Flow Control configuration (both CTS and RTS)
__STATIC_INLINE void | LL_USART_EnableOneBitSamp (USART_TypeDef *USARTx)
Enable One bit sampling method.
__STATIC_INLINE void | LL_USART_DisableOneBitSamp (USART_TypeDef *USARTx)
Disable One bit sampling method.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledOneBitSamp (USART_TypeDef *USARTx)
Indicate if One bit sampling method is enabled.
__STATIC_INLINE void | LL_USART_EnableOverrunDetect (USART_TypeDef *USARTx)
Enable Overrun detection.
__STATIC_INLINE void | LL_USART_DisableOverrunDetect (USART_TypeDef *USARTx)
Disable Overrun detection.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledOverrunDetect (USART_TypeDef *USARTx)
Indicate if Overrun detection is enabled.
__STATIC_INLINE void | LL_USART_SetWKUPType (USART_TypeDef *USARTx, uint32_t Type)
Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE uint32_t | LL_USART_GetWKUPType (USART_TypeDef *USARTx)
Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE void | LL_USART_SetBaudRate (USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling, uint32_t BaudRate)
Configure USART BRR register for achieving expected Baud Rate value.
__STATIC_INLINE uint32_t | LL_USART_GetBaudRate (USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling)
Return current Baud Rate value, according to USARTDIV present in BRR register (full BRR content), and to used Peripheral Clock and Oversampling mode values.
__STATIC_INLINE void | LL_USART_SetRxTimeout (USART_TypeDef *USARTx, uint32_t Timeout)
Set Receiver Time Out Value (expressed in nb of bits duration)
__STATIC_INLINE uint32_t | LL_USART_GetRxTimeout (USART_TypeDef *USARTx)
Get Receiver Time Out Value (expressed in nb of bits duration)
__STATIC_INLINE void | LL_USART_SetBlockLength (USART_TypeDef *USARTx, uint32_t BlockLength)
Set Block Length value in reception.
__STATIC_INLINE uint32_t | LL_USART_GetBlockLength (USART_TypeDef *USARTx)
Get Block Length value in reception.

Function Documentation

__STATIC_INLINE void LL_USART_ConfigCharacter | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | DataWidth,
 |  | uint32_t | Parity,
 |  | uint32_t | StopBits
 | ) |  |

Configure Character frame format (Datawidth, Parity control, Stop Bits)

Note:
Call of this function is equivalent to following function call sequence :
  • Data Width configuration using LL_USART_SetDataWidth() function
  • Parity Control and mode configuration using LL_USART_SetParity() function
  • Stop bits configuration using LL_USART_SetStopBitsLength() function
Reference Manual to LL API cross reference:
CR1 PS LL_USART_ConfigCharacter
CR1 PCE LL_USART_ConfigCharacter
CR1 M0 LL_USART_ConfigCharacter
CR1 M1 LL_USART_ConfigCharacter
CR2 STOP LL_USART_ConfigCharacter
Parameters:
USARTx USART Instance
DataWidth This parameter can be one of the following values:
  • LL_USART_DATAWIDTH_7B
  • LL_USART_DATAWIDTH_8B
  • LL_USART_DATAWIDTH_9B
Parity This parameter can be one of the following values:
  • LL_USART_PARITY_NONE
  • LL_USART_PARITY_EVEN
  • LL_USART_PARITY_ODD
StopBits This parameter can be one of the following values:
  • LL_USART_STOPBITS_0_5
  • LL_USART_STOPBITS_1
  • LL_USART_STOPBITS_1_5
  • LL_USART_STOPBITS_2
Return values:
None

Definition at line 1338 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigClock | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Phase,
 |  | uint32_t | Polarity,
 |  | uint32_t | LBCPOutput
 | ) |  |

Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clock Phase configuration using LL_USART_SetClockPhase() function
  • Clock Polarity configuration using LL_USART_SetClockPolarity() function
  • Output of Last bit Clock pulse configuration using LL_USART_SetLastClkPulseOutput() function
Reference Manual to LL API cross reference:
CR2 CPHA LL_USART_ConfigClock
CR2 CPOL LL_USART_ConfigClock
CR2 LBCL LL_USART_ConfigClock
Parameters:
USARTx USART Instance
Phase This parameter can be one of the following values:
  • LL_USART_PHASE_1EDGE
  • LL_USART_PHASE_2EDGE
Polarity This parameter can be one of the following values:
  • LL_USART_POLARITY_LOW
  • LL_USART_POLARITY_HIGH
LBCPOutput This parameter can be one of the following values:
  • LL_USART_LASTCLKPULSE_NO_OUTPUT
  • LL_USART_LASTCLKPULSE_OUTPUT
Return values:
None

Definition at line 1185 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigFIFOsThreshold | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | TXThreshold,
 |  | uint32_t | RXThreshold
 | ) |  |

Configure TX and RX FIFOs Threshold.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 TXFTCFG LL_USART_ConfigFIFOsThreshold
CR3 RXFTCFG LL_USART_ConfigFIFOsThreshold
Parameters:
USARTx USART Instance
TXThreshold This parameter can be one of the following values:
  • LL_USART_FIFOTHRESHOLD_1_8
  • LL_USART_FIFOTHRESHOLD_1_4
  • LL_USART_FIFOTHRESHOLD_1_2
  • LL_USART_FIFOTHRESHOLD_3_4
  • LL_USART_FIFOTHRESHOLD_7_8
  • LL_USART_FIFOTHRESHOLD_8_8
RXThreshold This parameter can be one of the following values:
  • LL_USART_FIFOTHRESHOLD_1_8
  • LL_USART_FIFOTHRESHOLD_1_4
  • LL_USART_FIFOTHRESHOLD_1_2
  • LL_USART_FIFOTHRESHOLD_3_4
  • LL_USART_FIFOTHRESHOLD_7_8
  • LL_USART_FIFOTHRESHOLD_8_8
Return values:
None

Definition at line 791 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigNodeAddress | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | AddressLen,
 |  | uint32_t | NodeAddress
 | ) |  |

Set Address of the USART node.

Note:
This is used in multiprocessor communication during Mute mode or Stop mode, for wake up with address mark detection.
4bits address node is used when 4-bit Address Detection is selected in ADDM7. (b7-b4 should be set to 0) 8bits address node is used when 7-bit Address Detection is selected in ADDM7. (This is used in multiprocessor communication during Mute mode or Stop mode, for wake up with 7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. It may also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match)
Reference Manual to LL API cross reference:
CR2 ADD LL_USART_ConfigNodeAddress
CR2 ADDM7 LL_USART_ConfigNodeAddress
Parameters:
USARTx | USART Instance
AddressLen This parameter can be one of the following values:
  • LL_USART_ADDRESS_DETECT_4B
  • LL_USART_ADDRESS_DETECT_7B
NodeAddress | 4 or 7 bit Address of the USART node.
Return values:
None

Definition at line 1616 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_Disable ( USART_TypeDef * USARTx )

USART Disable (all USART prescalers and outputs are disabled)

Note:
When USART is disabled, USART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the USART is kept, but all the status flags, in the USARTx_ISR are set to their default values.
Reference Manual to LL API cross reference:
CR1 UE LL_USART_Disable
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 635 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableAutoBaudRate ( USART_TypeDef * USARTx )

Disable Auto Baud-Rate Detection.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 ABREN LL_USART_DisableAutoBaudRate
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1507 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl ( USART_TypeDef * USARTx )

Disable CTS HW Flow Control.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 CTSE LL_USART_DisableCTSHWFlowCtrl
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1697 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableDirectionRx ( USART_TypeDef * USARTx )

Receiver Disable.

Reference Manual to LL API cross reference:
CR1 RE LL_USART_DisableDirectionRx
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 855 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableDirectionTx ( USART_TypeDef * USARTx )

Transmitter Disable.

Reference Manual to LL API cross reference:
CR1 TE LL_USART_DisableDirectionTx
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 877 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableFIFO ( USART_TypeDef * USARTx )

FIFO Mode Disable.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 FIFOEN LL_USART_DisableFIFO
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 672 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableInStopMode ( USART_TypeDef * USARTx )

USART disabled in STOP Mode.

Note:
When this function is disabled, USART is not able to wake up the MCU from Stop mode
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 UESM LL_USART_DisableInStopMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 820 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableMuteMode ( USART_TypeDef * USARTx )

Prevent Mute Mode use.

Set Receiver in active mode permanently.

Reference Manual to LL API cross reference:
CR1 MME LL_USART_DisableMuteMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1025 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableOneBitSamp ( USART_TypeDef * USARTx )

Disable One bit sampling method.

Reference Manual to LL API cross reference:
CR3 ONEBIT LL_USART_DisableOneBitSamp
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1756 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableOverrunDetect ( USART_TypeDef * USARTx )

Disable Overrun detection.

Reference Manual to LL API cross reference:
CR3 OVRDIS LL_USART_DisableOverrunDetect
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1789 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl ( USART_TypeDef * USARTx )

Disable RTS HW Flow Control.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RTSE LL_USART_DisableRTSHWFlowCtrl
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1671 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableRxTimeout ( USART_TypeDef * USARTx )

Disable Receiver Timeout.

Reference Manual to LL API cross reference:
CR2 RTOEN LL_USART_DisableRxTimeout
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1577 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableSCLKOutput ( USART_TypeDef * USARTx )

Disable Clock output on SCLK pin.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CLKEN LL_USART_DisableSCLKOutput
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1262 of file stm32wbxx_ll_usart.h.

Referenced by LL_USART_ClockInit().

__STATIC_INLINE void LL_USART_Enable ( USART_TypeDef * USARTx )

USART Enable.

Reference Manual to LL API cross reference:
CR1 UE LL_USART_Enable
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 621 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableAutoBaudRate ( USART_TypeDef * USARTx )

Enable Auto Baud-Rate Detection.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 ABREN LL_USART_EnableAutoBaudRate
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1494 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl ( USART_TypeDef * USARTx )

Enable CTS HW Flow Control.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 CTSE LL_USART_EnableCTSHWFlowCtrl
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1684 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableDirectionRx ( USART_TypeDef * USARTx )

Receiver Enable (Receiver is enabled and begins searching for a start bit)

Reference Manual to LL API cross reference:
CR1 RE LL_USART_EnableDirectionRx
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 844 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableDirectionTx ( USART_TypeDef * USARTx )

Transmitter Enable.

Reference Manual to LL API cross reference:
CR1 TE LL_USART_EnableDirectionTx
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 866 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableFIFO ( USART_TypeDef * USARTx )

FIFO Mode Enable.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 FIFOEN LL_USART_EnableFIFO
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 659 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableInStopMode ( USART_TypeDef * USARTx )

USART enabled in STOP Mode.

Note:
When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that USART clock selection is HSI or LSE in RCC.
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 UESM LL_USART_EnableInStopMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 806 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableMuteMode ( USART_TypeDef * USARTx )

Allow switch between Mute Mode and Active mode.

Reference Manual to LL API cross reference:
CR1 MME LL_USART_EnableMuteMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1014 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableOneBitSamp ( USART_TypeDef * USARTx )

Enable One bit sampling method.

Reference Manual to LL API cross reference:
CR3 ONEBIT LL_USART_EnableOneBitSamp
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1745 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableOverrunDetect ( USART_TypeDef * USARTx )

Enable Overrun detection.

Reference Manual to LL API cross reference:
CR3 OVRDIS LL_USART_EnableOverrunDetect
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1778 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl ( USART_TypeDef * USARTx )

Enable RTS HW Flow Control.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RTSE LL_USART_EnableRTSHWFlowCtrl
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1658 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableRxTimeout ( USART_TypeDef * USARTx )

Enable Receiver Timeout.

Reference Manual to LL API cross reference:
CR2 RTOEN LL_USART_EnableRxTimeout
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1566 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableSCLKOutput ( USART_TypeDef * USARTx )

Enable Clock output on SCLK pin.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CLKEN LL_USART_EnableSCLKOutput
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1249 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode ( USART_TypeDef * USARTx )

Return Auto Baud-Rate mode.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 ABRMODE LL_USART_GetAutoBaudRateMode
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
  • LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
  • LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
  • LL_USART_AUTOBAUD_DETECT_ON_55_FRAME

Definition at line 1555 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetBaudRate | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PeriphClk,
 |  | uint32_t | PrescalerValue,
 |  | uint32_t | OverSampling
 | ) |  |

Return current Baud Rate value, according to USARTDIV present in BRR register (full BRR content), and to used Peripheral Clock and Oversampling mode values.

Note:
In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
Reference Manual to LL API cross reference:
BRR BRR LL_USART_GetBaudRate
Parameters:
USARTx | USART Instance
PeriphClk | Peripheral Clock
PrescalerValue This parameter can be one of the following values:
  • LL_USART_PRESCALER_DIV1
  • LL_USART_PRESCALER_DIV2
  • LL_USART_PRESCALER_DIV4
  • LL_USART_PRESCALER_DIV6
  • LL_USART_PRESCALER_DIV8
  • LL_USART_PRESCALER_DIV10
  • LL_USART_PRESCALER_DIV12
  • LL_USART_PRESCALER_DIV16
  • LL_USART_PRESCALER_DIV32
  • LL_USART_PRESCALER_DIV64
  • LL_USART_PRESCALER_DIV128
  • LL_USART_PRESCALER_DIV256
OverSampling This parameter can be one of the following values:
  • LL_USART_OVERSAMPLING_16
  • LL_USART_OVERSAMPLING_8
Return values:
Baud Rate

Definition at line 1912 of file stm32wbxx_ll_usart.h.

References LL_USART_OVERSAMPLING_8.

__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic ( USART_TypeDef * USARTx )

Retrieve Binary data configuration.

Reference Manual to LL API cross reference:
CR2 DATAINV LL_USART_GetBinaryDataLogic
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_BINARY_LOGIC_POSITIVE
  • LL_USART_BINARY_LOGIC_NEGATIVE

Definition at line 1450 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetBlockLength ( USART_TypeDef * USARTx )

Get Block Length value in reception.

Reference Manual to LL API cross reference:
RTOR BLEN LL_USART_GetBlockLength
Parameters:
USARTx USART Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 1983 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetClockPhase ( USART_TypeDef * USARTx )

Return phase of the clock output on the SCLK pin in synchronous mode.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CPHA LL_USART_GetClockPhase
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_PHASE_1EDGE
  • LL_USART_PHASE_2EDGE

Definition at line 1126 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetClockPolarity ( USART_TypeDef * USARTx )

Return polarity of the clock output on the SCLK pin in synchronous mode.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CPOL LL_USART_GetClockPolarity
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_POLARITY_LOW
  • LL_USART_POLARITY_HIGH

Definition at line 1157 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetDataWidth ( USART_TypeDef * USARTx )

Return Word length (i.e.

nb of data bits, excluding start and stop bits)

Reference Manual to LL API cross reference:
CR1 M0 LL_USART_GetDataWidth
CR1 M1 LL_USART_GetDataWidth
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_DATAWIDTH_7B
  • LL_USART_DATAWIDTH_8B
  • LL_USART_DATAWIDTH_9B

Definition at line 1003 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl ( USART_TypeDef * USARTx )

Return HW Flow Control configuration (both CTS and RTS)

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RTSE LL_USART_GetHWFlowCtrl
CR3 CTSE LL_USART_GetHWFlowCtrl
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_HWCONTROL_NONE
  • LL_USART_HWCONTROL_RTS
  • LL_USART_HWCONTROL_CTS
  • LL_USART_HWCONTROL_RTS_CTS

Definition at line 1734 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput ( USART_TypeDef * USARTx )

Retrieve Clock pulse of the last data bit output configuration (Last bit Clock pulse output to the SCLK pin or not)

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBCL LL_USART_GetLastClkPulseOutput
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_LASTCLKPULSE_NO_OUTPUT
  • LL_USART_LASTCLKPULSE_OUTPUT

Definition at line 1095 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetNodeAddress ( USART_TypeDef * USARTx )

Return 8 bit Address of the USART node as set in ADD field of CR2.

Note:
If 4-bit Address Detection is selected in ADDM7, only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) If 7-bit Address Detection is selected in ADDM7, only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
Reference Manual to LL API cross reference:
CR2 ADD LL_USART_GetNodeAddress
Parameters:
USARTx USART Instance
Return values:
Address of the USART node (Value between Min_Data=0 and Max_Data=255)

Definition at line 1632 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen ( USART_TypeDef * USARTx )

Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)

Reference Manual to LL API cross reference:
CR2 ADDM7 LL_USART_GetNodeAddressLen
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_ADDRESS_DETECT_4B
  • LL_USART_ADDRESS_DETECT_7B

Definition at line 1645 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetOverSampling ( USART_TypeDef * USARTx )

Return Oversampling mode.

Reference Manual to LL API cross reference:
CR1 OVER8 LL_USART_GetOverSampling
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_OVERSAMPLING_16
  • LL_USART_OVERSAMPLING_8

Definition at line 1063 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetParity ( USART_TypeDef * USARTx )

Return Parity configuration (enabled/disabled and parity mode if enabled)

Reference Manual to LL API cross reference:
CR1 PS LL_USART_GetParity
CR1 PCE LL_USART_GetParity
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_PARITY_NONE
  • LL_USART_PARITY_EVEN
  • LL_USART_PARITY_ODD

Definition at line 945 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetPrescaler ( USART_TypeDef * USARTx )

Retrieve the Clock source prescaler for baudrate generator and oversampling.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
PRESC PRESCALER LL_USART_GetPrescaler
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_PRESCALER_DIV1
  • LL_USART_PRESCALER_DIV2
  • LL_USART_PRESCALER_DIV4
  • LL_USART_PRESCALER_DIV6
  • LL_USART_PRESCALER_DIV8
  • LL_USART_PRESCALER_DIV10
  • LL_USART_PRESCALER_DIV12
  • LL_USART_PRESCALER_DIV16
  • LL_USART_PRESCALER_DIV32
  • LL_USART_PRESCALER_DIV64
  • LL_USART_PRESCALER_DIV128
  • LL_USART_PRESCALER_DIV256

Definition at line 1236 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold ( USART_TypeDef * USARTx )

Return RX FIFO Threshold Configuration.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RXFTCFG LL_USART_GetRXFIFOThreshold
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_FIFOTHRESHOLD_1_8
  • LL_USART_FIFOTHRESHOLD_1_4
  • LL_USART_FIFOTHRESHOLD_1_2
  • LL_USART_FIFOTHRESHOLD_3_4
  • LL_USART_FIFOTHRESHOLD_7_8
  • LL_USART_FIFOTHRESHOLD_8_8

Definition at line 763 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel ( USART_TypeDef * USARTx )

Retrieve RX pin active level logic configuration.

Reference Manual to LL API cross reference:
CR2 RXINV LL_USART_GetRXPinLevel
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_RXPIN_LEVEL_STANDARD
  • LL_USART_RXPIN_LEVEL_INVERTED

Definition at line 1394 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetRxTimeout ( USART_TypeDef * USARTx )

Get Receiver Time Out Value (expressed in nb of bits duration)

Reference Manual to LL API cross reference:
RTOR RTO LL_USART_GetRxTimeout
Parameters:
USARTx USART Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x00FFFFFF

Definition at line 1960 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength ( USART_TypeDef * USARTx )

Retrieve the length of the stop bits.

Reference Manual to LL API cross reference:
CR2 STOP LL_USART_GetStopBitsLength
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_STOPBITS_0_5
  • LL_USART_STOPBITS_1
  • LL_USART_STOPBITS_1_5
  • LL_USART_STOPBITS_2

Definition at line 1306 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder ( USART_TypeDef * USARTx )

Return transfer bit order (either Less or Most Significant Bit First)

Note:
MSB First means data is transmitted/received with the MSB first, following the start bit. LSB First means data is transmitted/received with data bit 0 first, following the start bit.
Reference Manual to LL API cross reference:
CR2 MSBFIRST LL_USART_GetTransferBitOrder
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_BITORDER_LSBFIRST
  • LL_USART_BITORDER_MSBFIRST

Definition at line 1481 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetTransferDirection ( USART_TypeDef * USARTx )

Return enabled/disabled states of Transmitter and Receiver.

Reference Manual to LL API cross reference:
CR1 RE LL_USART_GetTransferDirection
CR1 TE LL_USART_GetTransferDirection
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_DIRECTION_NONE
  • LL_USART_DIRECTION_RX
  • LL_USART_DIRECTION_TX
  • LL_USART_DIRECTION_TX_RX

Definition at line 911 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold ( USART_TypeDef * USARTx )

Return TX FIFO Threshold Configuration.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 TXFTCFG LL_USART_GetTXFIFOThreshold
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_FIFOTHRESHOLD_1_8
  • LL_USART_FIFOTHRESHOLD_1_4
  • LL_USART_FIFOTHRESHOLD_1_2
  • LL_USART_FIFOTHRESHOLD_3_4
  • LL_USART_FIFOTHRESHOLD_7_8
  • LL_USART_FIFOTHRESHOLD_8_8

Definition at line 724 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel ( USART_TypeDef * USARTx )

Retrieve TX pin active level logic configuration.

Reference Manual to LL API cross reference:
CR2 TXINV LL_USART_GetTXPinLevel
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_TXPIN_LEVEL_STANDARD
  • LL_USART_TXPIN_LEVEL_INVERTED

Definition at line 1421 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap ( USART_TypeDef * USARTx )

Retrieve TX/RX pins swapping configuration.

Reference Manual to LL API cross reference:
CR2 SWAP LL_USART_GetTXRXSwap
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_TXRX_STANDARD
  • LL_USART_TXRX_SWAPPED

Definition at line 1367 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod ( USART_TypeDef * USARTx )

Return Receiver Wake Up method from Mute mode.

Reference Manual to LL API cross reference:
CR1 WAKE LL_USART_GetWakeUpMethod
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_WAKEUP_IDLELINE
  • LL_USART_WAKEUP_ADDRESSMARK

Definition at line 972 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetWKUPType ( USART_TypeDef * USARTx )

Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 WUS LL_USART_GetWKUPType
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_WAKEUP_ON_ADDRESS
  • LL_USART_WAKEUP_ON_STARTBIT
  • LL_USART_WAKEUP_ON_RXNE

Definition at line 1833 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabled ( USART_TypeDef * USARTx )

Indicate if USART is enabled.

Reference Manual to LL API cross reference:
CR1 UE LL_USART_IsEnabled
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 646 of file stm32wbxx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_Init().

__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud ( USART_TypeDef * USARTx )

Indicate if Auto Baud-Rate Detection mechanism is enabled.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 ABREN LL_USART_IsEnabledAutoBaud
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1520 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO ( USART_TypeDef * USARTx )

Indicate if FIFO Mode is enabled.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 FIFOEN LL_USART_IsEnabledFIFO
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 685 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode ( USART_TypeDef * USARTx )

Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 UESM LL_USART_IsEnabledInStopMode
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 833 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode ( USART_TypeDef * USARTx )

Indicate if switch between Mute Mode and Active mode is allowed.

Reference Manual to LL API cross reference:
CR1 MME LL_USART_IsEnabledMuteMode
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1036 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp ( USART_TypeDef * USARTx )

Indicate if One bit sampling method is enabled.

Reference Manual to LL API cross reference:
CR3 ONEBIT LL_USART_IsEnabledOneBitSamp
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1767 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect ( USART_TypeDef * USARTx )

Indicate if Overrun detection is enabled.

Reference Manual to LL API cross reference:
CR3 OVRDIS LL_USART_IsEnabledOverrunDetect
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1800 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout ( USART_TypeDef * USARTx )

Indicate if Receiver Timeout feature is enabled.

Reference Manual to LL API cross reference:
CR2 RTOEN LL_USART_IsEnabledRxTimeout
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1588 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput ( USART_TypeDef * USARTx )

Indicate if Clock output on SCLK pin is enabled.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CLKEN LL_USART_IsEnabledSCLKOutput
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1275 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetAutoBaudRateMode | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | AutoBaudRateMode
 | ) |  |

Set Auto Baud-Rate mode bits.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 ABRMODE LL_USART_SetAutoBaudRateMode
Parameters:
USARTx USART Instance
AutoBaudRateMode This parameter can be one of the following values:
  • LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
  • LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
  • LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
  • LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
Return values:
None

Definition at line 1538 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetBaudRate | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PeriphClk,
 |  | uint32_t | PrescalerValue,
 |  | uint32_t | OverSampling,
 |  | uint32_t | BaudRate
 | ) |  |

Configure USART BRR register for achieving expected Baud Rate value.

Note:
Compute and set USARTDIV value in BRR Register (full BRR content) according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
Peripheral clock and Baud rate values provided as function parameters should be valid (Baud rate value != 0)
In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
Reference Manual to LL API cross reference:
BRR BRR LL_USART_SetBaudRate
Parameters:
USARTx | USART Instance
PeriphClk | Peripheral Clock
PrescalerValue This parameter can be one of the following values:
  • LL_USART_PRESCALER_DIV1
  • LL_USART_PRESCALER_DIV2
  • LL_USART_PRESCALER_DIV4
  • LL_USART_PRESCALER_DIV6
  • LL_USART_PRESCALER_DIV8
  • LL_USART_PRESCALER_DIV10
  • LL_USART_PRESCALER_DIV12
  • LL_USART_PRESCALER_DIV16
  • LL_USART_PRESCALER_DIV32
  • LL_USART_PRESCALER_DIV64
  • LL_USART_PRESCALER_DIV128
  • LL_USART_PRESCALER_DIV256
OverSampling This parameter can be one of the following values:
  • LL_USART_OVERSAMPLING_16
  • LL_USART_OVERSAMPLING_8
BaudRate | Baud Rate
Return values:
None

Definition at line 1867 of file stm32wbxx_ll_usart.h.

References __LL_USART_DIV_SAMPLING16, __LL_USART_DIV_SAMPLING8, and LL_USART_OVERSAMPLING_8.

Referenced by LL_USART_Init().

__STATIC_INLINE void LL_USART_SetBinaryDataLogic | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | DataLogic
 | ) |  |

Configure Binary data logic.

Note:
Allow to define how Logical data from the data register are send/received : either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
Reference Manual to LL API cross reference:
CR2 DATAINV LL_USART_SetBinaryDataLogic
Parameters:
USARTx USART Instance
DataLogic This parameter can be one of the following values:
  • LL_USART_BINARY_LOGIC_POSITIVE
  • LL_USART_BINARY_LOGIC_NEGATIVE
Return values:
None

Definition at line 1437 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetBlockLength | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | BlockLength
 | ) |  |

Set Block Length value in reception.

Reference Manual to LL API cross reference:
RTOR BLEN LL_USART_SetBlockLength
Parameters:
USARTx | USART Instance
BlockLength | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 1972 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetClockPhase | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | ClockPhase
 | ) |  |

Select the phase of the clock output on the SCLK pin in synchronous mode.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CPHA LL_USART_SetClockPhase
Parameters:
USARTx USART Instance
ClockPhase This parameter can be one of the following values:
  • LL_USART_PHASE_1EDGE
  • LL_USART_PHASE_2EDGE
Return values:
None

Definition at line 1111 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetClockPolarity | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | ClockPolarity
 | ) |  |

Select the polarity of the clock output on the SCLK pin in synchronous mode.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CPOL LL_USART_SetClockPolarity
Parameters:
USARTx USART Instance
ClockPolarity This parameter can be one of the following values:
  • LL_USART_POLARITY_LOW
  • LL_USART_POLARITY_HIGH
Return values:
None

Definition at line 1142 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetDataWidth | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | DataWidth
 | ) |  |

Set Word length (i.e.

nb of data bits, excluding start and stop bits)

Reference Manual to LL API cross reference:
CR1 M0 LL_USART_SetDataWidth
CR1 M1 LL_USART_SetDataWidth
Parameters:
USARTx USART Instance
DataWidth This parameter can be one of the following values:
  • LL_USART_DATAWIDTH_7B
  • LL_USART_DATAWIDTH_8B
  • LL_USART_DATAWIDTH_9B
Return values:
None

Definition at line 988 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetHWFlowCtrl | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | HardwareFlowControl
 | ) |  |

Configure HW Flow Control mode (both CTS and RTS)

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RTSE LL_USART_SetHWFlowCtrl
CR3 CTSE LL_USART_SetHWFlowCtrl
Parameters:
USARTx USART Instance
HardwareFlowControl This parameter can be one of the following values:
  • LL_USART_HWCONTROL_NONE
  • LL_USART_HWCONTROL_RTS
  • LL_USART_HWCONTROL_CTS
  • LL_USART_HWCONTROL_RTS_CTS
Return values:
None

Definition at line 1716 of file stm32wbxx_ll_usart.h.

Referenced by LL_USART_Init().

__STATIC_INLINE void LL_USART_SetLastClkPulseOutput | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | LastBitClockPulse
 | ) |  |

Configure if Clock pulse of the last data bit is output to the SCLK pin or not.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBCL LL_USART_SetLastClkPulseOutput
Parameters:
USARTx USART Instance
LastBitClockPulse This parameter can be one of the following values:
  • LL_USART_LASTCLKPULSE_NO_OUTPUT
  • LL_USART_LASTCLKPULSE_OUTPUT
Return values:
None

Definition at line 1079 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetOverSampling | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | OverSampling
 | ) |  |

Set Oversampling to 8-bit or 16-bit mode.

Reference Manual to LL API cross reference:
CR1 OVER8 LL_USART_SetOverSampling
Parameters:
USARTx USART Instance
OverSampling This parameter can be one of the following values:
  • LL_USART_OVERSAMPLING_16
  • LL_USART_OVERSAMPLING_8
Return values:
None

Definition at line 1050 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetParity | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Parity
 | ) |  |

Configure Parity (enabled/disabled and parity mode if enabled).

Note:
This function selects if hardware parity control (generation and detection) is enabled or disabled. When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position (9th or 8th bit depending on data width) and parity is checked on the received data.
Reference Manual to LL API cross reference:
CR1 PS LL_USART_SetParity
CR1 PCE LL_USART_SetParity
Parameters:
USARTx USART Instance
Parity This parameter can be one of the following values:
  • LL_USART_PARITY_NONE
  • LL_USART_PARITY_EVEN
  • LL_USART_PARITY_ODD
Return values:
None

Definition at line 930 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetPrescaler | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PrescalerValue
 | ) |  |

Configure Clock source prescaler for baudrate generator and oversampling.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
PRESC PRESCALER LL_USART_SetPrescaler
Parameters:
USARTx USART Instance
PrescalerValue This parameter can be one of the following values:
  • LL_USART_PRESCALER_DIV1
  • LL_USART_PRESCALER_DIV2
  • LL_USART_PRESCALER_DIV4
  • LL_USART_PRESCALER_DIV6
  • LL_USART_PRESCALER_DIV8
  • LL_USART_PRESCALER_DIV10
  • LL_USART_PRESCALER_DIV12
  • LL_USART_PRESCALER_DIV16
  • LL_USART_PRESCALER_DIV32
  • LL_USART_PRESCALER_DIV64
  • LL_USART_PRESCALER_DIV128
  • LL_USART_PRESCALER_DIV256
Return values:
None

Definition at line 1211 of file stm32wbxx_ll_usart.h.

Referenced by LL_USART_Init().

__STATIC_INLINE void LL_USART_SetRXFIFOThreshold | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Threshold
 | ) |  |

Configure RX FIFO Threshold.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RXFTCFG LL_USART_SetRXFIFOThreshold
Parameters:
USARTx USART Instance
Threshold This parameter can be one of the following values:
  • LL_USART_FIFOTHRESHOLD_1_8
  • LL_USART_FIFOTHRESHOLD_1_4
  • LL_USART_FIFOTHRESHOLD_1_2
  • LL_USART_FIFOTHRESHOLD_3_4
  • LL_USART_FIFOTHRESHOLD_7_8
  • LL_USART_FIFOTHRESHOLD_8_8
Return values:
None

Definition at line 744 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetRXPinLevel | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PinInvMethod
 | ) |  |

Configure RX pin active level logic.

Reference Manual to LL API cross reference:
CR2 RXINV LL_USART_SetRXPinLevel
Parameters:
USARTx USART Instance
PinInvMethod This parameter can be one of the following values:
  • LL_USART_RXPIN_LEVEL_STANDARD
  • LL_USART_RXPIN_LEVEL_INVERTED
Return values:
None

Definition at line 1381 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetRxTimeout | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Timeout
 | ) |  |

Set Receiver Time Out Value (expressed in nb of bits duration)

Reference Manual to LL API cross reference:
RTOR RTO LL_USART_SetRxTimeout
Parameters:
USARTx | USART Instance
Timeout | Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
Return values:
None

Definition at line 1949 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetStopBitsLength | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | StopBits
 | ) |  |

Set the length of the stop bits.

Reference Manual to LL API cross reference:
CR2 STOP LL_USART_SetStopBitsLength
Parameters:
USARTx USART Instance
StopBits This parameter can be one of the following values:
  • LL_USART_STOPBITS_0_5
  • LL_USART_STOPBITS_1
  • LL_USART_STOPBITS_1_5
  • LL_USART_STOPBITS_2
Return values:
None

Definition at line 1291 of file stm32wbxx_ll_usart.h.

Referenced by LL_USART_Init().

__STATIC_INLINE void LL_USART_SetTransferBitOrder | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | BitOrder
 | ) |  |

Configure transfer bit order (either Less or Most Significant Bit First)

Note:
MSB First means data is transmitted/received with the MSB first, following the start bit. LSB First means data is transmitted/received with data bit 0 first, following the start bit.
Reference Manual to LL API cross reference:
CR2 MSBFIRST LL_USART_SetTransferBitOrder
Parameters:
USARTx USART Instance
BitOrder This parameter can be one of the following values:
  • LL_USART_BITORDER_LSBFIRST
  • LL_USART_BITORDER_MSBFIRST
Return values:
None

Definition at line 1466 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetTransferDirection | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | TransferDirection
 | ) |  |

Configure simultaneously enabled/disabled states of Transmitter and Receiver.

Reference Manual to LL API cross reference:
CR1 RE LL_USART_SetTransferDirection
CR1 TE LL_USART_SetTransferDirection
Parameters:
USARTx USART Instance
TransferDirection This parameter can be one of the following values:
  • LL_USART_DIRECTION_NONE
  • LL_USART_DIRECTION_RX
  • LL_USART_DIRECTION_TX
  • LL_USART_DIRECTION_TX_RX
Return values:
None

Definition at line 895 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetTXFIFOThreshold | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Threshold
 | ) |  |

Configure TX FIFO Threshold.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 TXFTCFG LL_USART_SetTXFIFOThreshold
Parameters:
USARTx USART Instance
Threshold This parameter can be one of the following values:
  • LL_USART_FIFOTHRESHOLD_1_8
  • LL_USART_FIFOTHRESHOLD_1_4
  • LL_USART_FIFOTHRESHOLD_1_2
  • LL_USART_FIFOTHRESHOLD_3_4
  • LL_USART_FIFOTHRESHOLD_7_8
  • LL_USART_FIFOTHRESHOLD_8_8
Return values:
None

Definition at line 705 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetTXPinLevel | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PinInvMethod
 | ) |  |

Configure TX pin active level logic.

Reference Manual to LL API cross reference:
CR2 TXINV LL_USART_SetTXPinLevel
Parameters:
USARTx USART Instance
PinInvMethod This parameter can be one of the following values:
  • LL_USART_TXPIN_LEVEL_STANDARD
  • LL_USART_TXPIN_LEVEL_INVERTED
Return values:
None

Definition at line 1408 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetTXRXSwap | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | SwapConfig
 | ) |  |

Configure TX/RX pins swapping setting.

Reference Manual to LL API cross reference:
CR2 SWAP LL_USART_SetTXRXSwap
Parameters:
USARTx USART Instance
SwapConfig This parameter can be one of the following values:
  • LL_USART_TXRX_STANDARD
  • LL_USART_TXRX_SWAPPED
Return values:
None

Definition at line 1354 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetWakeUpMethod | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Method
 | ) |  |

Set Receiver Wake Up method from Mute mode.

Reference Manual to LL API cross reference:
CR1 WAKE LL_USART_SetWakeUpMethod
Parameters:
USARTx USART Instance
Method This parameter can be one of the following values:
  • LL_USART_WAKEUP_IDLELINE
  • LL_USART_WAKEUP_ADDRESSMARK
Return values:
None

Definition at line 959 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetWKUPType | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Type
 | ) |  |

Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 WUS LL_USART_SetWKUPType
Parameters:
USARTx USART Instance
Type This parameter can be one of the following values:
  • LL_USART_WAKEUP_ON_ADDRESS
  • LL_USART_WAKEUP_ON_STARTBIT
  • LL_USART_WAKEUP_ON_RXNE
Return values:
None

Definition at line 1817 of file stm32wbxx_ll_usart.h.

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Configuration functions related to Irda feature

Functions
Configuration functions related to Irda feature
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_EnableIrda (USART_TypeDef *USARTx)
Enable IrDA mode.
__STATIC_INLINE void | LL_USART_DisableIrda (USART_TypeDef *USARTx)
Disable IrDA mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIrda (USART_TypeDef *USARTx)
Indicate if IrDA mode is enabled.
__STATIC_INLINE void | LL_USART_SetIrdaPowerMode (USART_TypeDef *USARTx, uint32_t PowerMode)
Configure IrDA Power Mode (Normal or Low Power)
__STATIC_INLINE uint32_t | LL_USART_GetIrdaPowerMode (USART_TypeDef *USARTx)
Retrieve IrDA Power Mode configuration (Normal or Low Power)
__STATIC_INLINE void | LL_USART_SetIrdaPrescaler (USART_TypeDef *USARTx, uint32_t PrescalerValue)
Set Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)
__STATIC_INLINE uint32_t | LL_USART_GetIrdaPrescaler (USART_TypeDef *USARTx)
Return Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)

Function Documentation

__STATIC_INLINE void LL_USART_DisableIrda ( USART_TypeDef * USARTx )

Disable IrDA mode.

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 IREN LL_USART_DisableIrda
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2017 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIrda ( USART_TypeDef * USARTx )

Enable IrDA mode.

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 IREN LL_USART_EnableIrda
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2004 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode ( USART_TypeDef * USARTx )

Retrieve IrDA Power Mode configuration (Normal or Low Power)

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 IRLP LL_USART_GetIrdaPowerMode
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_IRDA_POWER_NORMAL
  • LL_USART_PHASE_2EDGE

Definition at line 2061 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler ( USART_TypeDef * USARTx )

Return Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR PSC LL_USART_GetIrdaPrescaler
Parameters:
USARTx USART Instance
Return values:
Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)

Definition at line 2090 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda ( USART_TypeDef * USARTx )

Indicate if IrDA mode is enabled.

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 IREN LL_USART_IsEnabledIrda
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2030 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetIrdaPowerMode | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PowerMode
 | ) |  |

Configure IrDA Power Mode (Normal or Low Power)

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 IRLP LL_USART_SetIrdaPowerMode
Parameters:
USARTx USART Instance
PowerMode This parameter can be one of the following values:
  • LL_USART_IRDA_POWER_NORMAL
  • LL_USART_IRDA_POWER_LOW
Return values:
None

Definition at line 2046 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetIrdaPrescaler | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PrescalerValue
 | ) |  |

Set Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR PSC LL_USART_SetIrdaPrescaler
Parameters:
USARTx | USART Instance
PrescalerValue | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 2076 of file stm32wbxx_ll_usart.h.

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Configuration functions related to Smartcard feature

Functions
Configuration functions related to Smartcard feature
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_EnableSmartcardNACK (USART_TypeDef *USARTx)
Enable Smartcard NACK transmission.
__STATIC_INLINE void | LL_USART_DisableSmartcardNACK (USART_TypeDef *USARTx)
Disable Smartcard NACK transmission.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSmartcardNACK (USART_TypeDef *USARTx)
Indicate if Smartcard NACK transmission is enabled.
__STATIC_INLINE void | LL_USART_EnableSmartcard (USART_TypeDef *USARTx)
Enable Smartcard mode.
__STATIC_INLINE void | LL_USART_DisableSmartcard (USART_TypeDef *USARTx)
Disable Smartcard mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSmartcard (USART_TypeDef *USARTx)
Indicate if Smartcard mode is enabled.
__STATIC_INLINE void | LL_USART_SetSmartcardAutoRetryCount (USART_TypeDef *USARTx, uint32_t AutoRetryCount)
Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardAutoRetryCount (USART_TypeDef *USARTx)
Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
__STATIC_INLINE void | LL_USART_SetSmartcardPrescaler (USART_TypeDef *USARTx, uint32_t PrescalerValue)
Set Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardPrescaler (USART_TypeDef *USARTx)
Return Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)
__STATIC_INLINE void | LL_USART_SetSmartcardGuardTime (USART_TypeDef *USARTx, uint32_t GuardTime)
Set Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardGuardTime (USART_TypeDef *USARTx)
Return Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)

Function Documentation

__STATIC_INLINE void LL_USART_DisableSmartcard ( USART_TypeDef * USARTx )

Disable Smartcard mode.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 SCEN LL_USART_DisableSmartcard
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2163 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableSmartcardNACK ( USART_TypeDef * USARTx )

Disable Smartcard NACK transmission.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 NACK LL_USART_DisableSmartcardNACK
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2124 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableSmartcard ( USART_TypeDef * USARTx )

Enable Smartcard mode.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 SCEN LL_USART_EnableSmartcard
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2150 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableSmartcardNACK ( USART_TypeDef * USARTx )

Enable Smartcard NACK transmission.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 NACK LL_USART_EnableSmartcardNACK
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2111 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount ( USART_TypeDef * USARTx )

Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount
Parameters:
USARTx USART Instance
Return values:
Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)

Definition at line 2208 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime ( USART_TypeDef * USARTx )

Return Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR GT LL_USART_GetSmartcardGuardTime
Parameters:
USARTx USART Instance
Return values:
Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)

Definition at line 2266 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler ( USART_TypeDef * USARTx )

Return Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR PSC LL_USART_GetSmartcardPrescaler
Parameters:
USARTx USART Instance
Return values:
Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)

Definition at line 2237 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard ( USART_TypeDef * USARTx )

Indicate if Smartcard mode is enabled.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 SCEN LL_USART_IsEnabledSmartcard
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2176 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK ( USART_TypeDef * USARTx )

Indicate if Smartcard NACK transmission is enabled.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 NACK LL_USART_IsEnabledSmartcardNACK
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2137 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | AutoRetryCount
 | ) |  |

Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
This bit-field specifies the number of retries in transmit and receive, in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE and PE bits set)
Reference Manual to LL API cross reference:
CR3 SCARCNT LL_USART_SetSmartcardAutoRetryCount
Parameters:
USARTx | USART Instance
AutoRetryCount | Value between Min_Data=0 and Max_Data=7
Return values:
None

Definition at line 2195 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetSmartcardGuardTime | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | GuardTime
 | ) |  |

Set Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR GT LL_USART_SetSmartcardGuardTime
Parameters:
USARTx | USART Instance
GuardTime | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 2252 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetSmartcardPrescaler | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PrescalerValue
 | ) |  |

Set Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR PSC LL_USART_SetSmartcardPrescaler
Parameters:
USARTx | USART Instance
PrescalerValue | Value between Min_Data=0 and Max_Data=31
Return values:
None

Definition at line 2223 of file stm32wbxx_ll_usart.h.

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Configuration functions related to Half Duplex feature

Functions
Configuration functions related to Half Duplex feature
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_EnableHalfDuplex (USART_TypeDef *USARTx)
Enable Single Wire Half-Duplex mode.
__STATIC_INLINE void | LL_USART_DisableHalfDuplex (USART_TypeDef *USARTx)
Disable Single Wire Half-Duplex mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledHalfDuplex (USART_TypeDef *USARTx)
Indicate if Single Wire Half-Duplex mode is enabled.

Function Documentation

__STATIC_INLINE void LL_USART_DisableHalfDuplex ( USART_TypeDef * USARTx )

Disable Single Wire Half-Duplex mode.

Note:
Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not Half-Duplex mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 HDSEL LL_USART_DisableHalfDuplex
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2300 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableHalfDuplex ( USART_TypeDef * USARTx )

Enable Single Wire Half-Duplex mode.

Note:
Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not Half-Duplex mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 HDSEL LL_USART_EnableHalfDuplex
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2287 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex ( USART_TypeDef * USARTx )

Indicate if Single Wire Half-Duplex mode is enabled.

Note:
Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not Half-Duplex mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 HDSEL LL_USART_IsEnabledHalfDuplex
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2313 of file stm32wbxx_ll_usart.h.

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Configuration functions related to SPI Slave feature

Functions
Configuration functions related to SPI Slave feature
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_EnableSPISlave (USART_TypeDef *USARTx)
Enable SPI Synchronous Slave mode.
__STATIC_INLINE void | LL_USART_DisableSPISlave (USART_TypeDef *USARTx)
Disable SPI Synchronous Slave mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSPISlave (USART_TypeDef *USARTx)
Indicate if SPI Synchronous Slave mode is enabled.
__STATIC_INLINE void | LL_USART_EnableSPISlaveSelect (USART_TypeDef *USARTx)
Enable SPI Slave Selection using NSS input pin.
__STATIC_INLINE void | LL_USART_DisableSPISlaveSelect (USART_TypeDef *USARTx)
Disable SPI Slave Selection using NSS input pin.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSPISlaveSelect (USART_TypeDef *USARTx)
Indicate if SPI Slave Selection depends on NSS input pin.

Function Documentation

__STATIC_INLINE void LL_USART_DisableSPISlave ( USART_TypeDef * USARTx )

Disable SPI Synchronous Slave mode.

Note:
Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not SPI Slave mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 SLVEN LL_USART_DisableSPISlave
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2346 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableSPISlaveSelect ( USART_TypeDef * USARTx )

Disable SPI Slave Selection using NSS input pin.

Note:
Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not SPI Slave mode feature is supported by the USARTx instance.
SPI Slave will be always selected and NSS input pin will be ignored.
Reference Manual to LL API cross reference:
CR2 DIS_NSS LL_USART_DisableSPISlaveSelect
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2388 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableSPISlave ( USART_TypeDef * USARTx )

Enable SPI Synchronous Slave mode.

Note:
Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not SPI Slave mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 SLVEN LL_USART_EnableSPISlave
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2333 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableSPISlaveSelect ( USART_TypeDef * USARTx )

Enable SPI Slave Selection using NSS input pin.

Note:
Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not SPI Slave mode feature is supported by the USARTx instance.
SPI Slave Selection depends on NSS input pin (The slave is selected when NSS is low and deselected when NSS is high).
Reference Manual to LL API cross reference:
CR2 DIS_NSS LL_USART_EnableSPISlaveSelect
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2374 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave ( USART_TypeDef * USARTx )

Indicate if SPI Synchronous Slave mode is enabled.

Note:
Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not SPI Slave mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 SLVEN LL_USART_IsEnabledSPISlave
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2359 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect ( USART_TypeDef * USARTx )

Indicate if SPI Slave Selection depends on NSS input pin.

Note:
Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not SPI Slave mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 DIS_NSS LL_USART_IsEnabledSPISlaveSelect
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2401 of file stm32wbxx_ll_usart.h.

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Configuration functions related to LIN feature

Functions
Configuration functions related to LIN feature
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_SetLINBrkDetectionLen (USART_TypeDef *USARTx, uint32_t LINBDLength)
Set LIN Break Detection Length.
__STATIC_INLINE uint32_t | LL_USART_GetLINBrkDetectionLen (USART_TypeDef *USARTx)
Return LIN Break Detection Length.
__STATIC_INLINE void | LL_USART_EnableLIN (USART_TypeDef *USARTx)
Enable LIN mode.
__STATIC_INLINE void | LL_USART_DisableLIN (USART_TypeDef *USARTx)
Disable LIN mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledLIN (USART_TypeDef *USARTx)
Indicate if LIN mode is enabled.

Function Documentation

__STATIC_INLINE void LL_USART_DisableLIN ( USART_TypeDef * USARTx )

Disable LIN mode.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_DisableLIN
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2466 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableLIN ( USART_TypeDef * USARTx )

Enable LIN mode.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_EnableLIN
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2453 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen ( USART_TypeDef * USARTx )

Return LIN Break Detection Length.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBDL LL_USART_GetLINBrkDetectionLen
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_LINBREAK_DETECT_10B
  • LL_USART_LINBREAK_DETECT_11B

Definition at line 2440 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN ( USART_TypeDef * USARTx )

Indicate if LIN mode is enabled.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_IsEnabledLIN
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2479 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | LINBDLength
 | ) |  |

Set LIN Break Detection Length.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBDL LL_USART_SetLINBrkDetectionLen
Parameters:
USARTx USART Instance
LINBDLength This parameter can be one of the following values:
  • LL_USART_LINBREAK_DETECT_10B
  • LL_USART_LINBREAK_DETECT_11B
Return values:
None

Definition at line 2425 of file stm32wbxx_ll_usart.h.

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Configuration functions related to Driver Enable feature

Functions
Configuration functions related to Driver Enable feature
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_SetDEDeassertionTime (USART_TypeDef *USARTx, uint32_t Time)
Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_USART_GetDEDeassertionTime (USART_TypeDef *USARTx)
Return DEDT (Driver Enable De-Assertion Time)
__STATIC_INLINE void | LL_USART_SetDEAssertionTime (USART_TypeDef *USARTx, uint32_t Time)
Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_USART_GetDEAssertionTime (USART_TypeDef *USARTx)
Return DEAT (Driver Enable Assertion Time)
__STATIC_INLINE void | LL_USART_EnableDEMode (USART_TypeDef *USARTx)
Enable Driver Enable (DE) Mode.
__STATIC_INLINE void | LL_USART_DisableDEMode (USART_TypeDef *USARTx)
Disable Driver Enable (DE) Mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDEMode (USART_TypeDef *USARTx)
Indicate if Driver Enable (DE) Mode is enabled.
__STATIC_INLINE void | LL_USART_SetDESignalPolarity (USART_TypeDef *USARTx, uint32_t Polarity)
Select Driver Enable Polarity.
__STATIC_INLINE uint32_t | LL_USART_GetDESignalPolarity (USART_TypeDef *USARTx)
Return Driver Enable Polarity.

Function Documentation

__STATIC_INLINE void LL_USART_DisableDEMode ( USART_TypeDef * USARTx )

Disable Driver Enable (DE) Mode.

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 DEM LL_USART_DisableDEMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2567 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableDEMode ( USART_TypeDef * USARTx )

Enable Driver Enable (DE) Mode.

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 DEM LL_USART_EnableDEMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2554 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime ( USART_TypeDef * USARTx )

Return DEAT (Driver Enable Assertion Time)

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 DEAT LL_USART_GetDEAssertionTime
Parameters:
USARTx USART Instance
Return values:
Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31

Definition at line 2541 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime ( USART_TypeDef * USARTx )

Return DEDT (Driver Enable De-Assertion Time)

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 DEDT LL_USART_GetDEDeassertionTime
Parameters:
USARTx USART Instance
Return values:
Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31

Definition at line 2514 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity ( USART_TypeDef * USARTx )

Return Driver Enable Polarity.

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 DEP LL_USART_GetDESignalPolarity
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_DE_POLARITY_HIGH
  • LL_USART_DE_POLARITY_LOW

Definition at line 2611 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode ( USART_TypeDef * USARTx )

Indicate if Driver Enable (DE) Mode is enabled.

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 DEM LL_USART_IsEnabledDEMode
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2580 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetDEAssertionTime | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Time
 | ) |  |

Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 DEAT LL_USART_SetDEAssertionTime
Parameters:
USARTx | USART Instance
Time | Value between Min_Data=0 and Max_Data=31
Return values:
None

Definition at line 2528 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetDEDeassertionTime | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Time
 | ) |  |

Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 DEDT LL_USART_SetDEDeassertionTime
Parameters:
USARTx | USART Instance
Time | Value between Min_Data=0 and Max_Data=31
Return values:
None

Definition at line 2501 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetDESignalPolarity | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Polarity
 | ) |  |

Select Driver Enable Polarity.

Note:
Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not Driver Enable feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 DEP LL_USART_SetDESignalPolarity
Parameters:
USARTx USART Instance
Polarity This parameter can be one of the following values:
  • LL_USART_DE_POLARITY_HIGH
  • LL_USART_DE_POLARITY_LOW
Return values:
None

Definition at line 2596 of file stm32wbxx_ll_usart.h.

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Advanced Configurations services

Functions
Advanced Configurations services
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_ConfigAsyncMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
__STATIC_INLINE void | LL_USART_ConfigSyncMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Synchronous Mode.
__STATIC_INLINE void | LL_USART_ConfigLINMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in LIN Mode.
__STATIC_INLINE void | LL_USART_ConfigHalfDuplexMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Half Duplex Mode.
__STATIC_INLINE void | LL_USART_ConfigSmartcardMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Smartcard Mode.
__STATIC_INLINE void | LL_USART_ConfigIrdaMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Irda Mode.
__STATIC_INLINE void | LL_USART_ConfigMultiProcessMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Multi processor Mode (several USARTs connected in a network, one of the USARTs can be the master, its TX output connected to the RX inputs of the other slaves USARTs).

Function Documentation

__STATIC_INLINE void LL_USART_ConfigAsyncMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)

Note:
In UART mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • CLKEN bit in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • IREN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear CLKEN in CR2 using LL_USART_DisableSCLKOutput() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
Other remaining configurations items related to Asynchronous Mode (as Baud Rate, Word length, Parity, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigAsyncMode
CR2 CLKEN LL_USART_ConfigAsyncMode
CR3 SCEN LL_USART_ConfigAsyncMode
CR3 IREN LL_USART_ConfigAsyncMode
CR3 HDSEL LL_USART_ConfigAsyncMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2649 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Half Duplex Mode.

Note:
In Half Duplex mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • CLKEN bit in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • IREN bit in the USART_CR3 register, This function also sets the UART/USART in Half Duplex mode.
Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not Half-Duplex mode is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear CLKEN in CR2 using LL_USART_DisableSCLKOutput() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Set HDSEL in CR3 using LL_USART_EnableHalfDuplex() function
Other remaining configurations items related to Half Duplex Mode (as Baud Rate, Word length, Parity, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigHalfDuplexMode
CR2 CLKEN LL_USART_ConfigHalfDuplexMode
CR3 HDSEL LL_USART_ConfigHalfDuplexMode
CR3 SCEN LL_USART_ConfigHalfDuplexMode
CR3 IREN LL_USART_ConfigHalfDuplexMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2763 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigIrdaMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Irda Mode.

Note:
In IRDA mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • STOP and CLKEN bits in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register. This function also sets the UART/USART in IRDA mode (IREN bit).
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear CLKEN in CR2 using LL_USART_DisableSCLKOutput() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
  • Configure STOP in CR2 using LL_USART_SetStopBitsLength() function
  • Set IREN in CR3 using LL_USART_EnableIrda() function
Other remaining configurations items related to Irda Mode (as Baud Rate, Word length, Power mode, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigIrdaMode
CR2 CLKEN LL_USART_ConfigIrdaMode
CR2 STOP LL_USART_ConfigIrdaMode
CR3 SCEN LL_USART_ConfigIrdaMode
CR3 HDSEL LL_USART_ConfigIrdaMode
CR3 IREN LL_USART_ConfigIrdaMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2846 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigLINMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in LIN Mode.

Note:
In LIN mode, the following bits must be kept cleared:
  • STOP and CLKEN bits in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • IREN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register. This function also set the UART/USART in LIN mode.
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clear CLKEN in CR2 using LL_USART_DisableSCLKOutput() function
  • Clear STOP in CR2 using LL_USART_SetStopBitsLength() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
  • Set LINEN in CR2 using LL_USART_EnableLIN() function
Other remaining configurations items related to LIN Mode (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 CLKEN LL_USART_ConfigLINMode
CR2 STOP LL_USART_ConfigLINMode
CR2 LINEN LL_USART_ConfigLINMode
CR3 IREN LL_USART_ConfigLINMode
CR3 SCEN LL_USART_ConfigLINMode
CR3 HDSEL LL_USART_ConfigLINMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2725 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigMultiProcessMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Multi processor Mode (several USARTs connected in a network, one of the USARTs can be the master, its TX output connected to the RX inputs of the other slaves USARTs).

Note:
In MultiProcessor mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • CLKEN bit in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • IREN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear CLKEN in CR2 using LL_USART_DisableSCLKOutput() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
Other remaining configurations items related to Multi processor Mode (as Baud Rate, Wake Up Method, Node address, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigMultiProcessMode
CR2 CLKEN LL_USART_ConfigMultiProcessMode
CR3 SCEN LL_USART_ConfigMultiProcessMode
CR3 HDSEL LL_USART_ConfigMultiProcessMode
CR3 IREN LL_USART_ConfigMultiProcessMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2884 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigSmartcardMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Smartcard Mode.

Note:
In Smartcard mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • IREN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register. This function also configures Stop bits to 1.5 bits and sets the USART in Smartcard mode (SCEN bit). Clock Output is also enabled (CLKEN).
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
  • Configure STOP in CR2 using LL_USART_SetStopBitsLength() function
  • Set CLKEN in CR2 using LL_USART_EnableSCLKOutput() function
  • Set SCEN in CR3 using LL_USART_EnableSmartcard() function
Other remaining configurations items related to Smartcard Mode (as Baud Rate, Word length, Parity, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigSmartcardMode
CR2 STOP LL_USART_ConfigSmartcardMode
CR2 CLKEN LL_USART_ConfigSmartcardMode
CR3 HDSEL LL_USART_ConfigSmartcardMode
CR3 SCEN LL_USART_ConfigSmartcardMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2803 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigSyncMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Synchronous Mode.

Note:
In Synchronous mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • IREN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register. This function also sets the USART in Synchronous mode.
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
  • Set CLKEN in CR2 using LL_USART_EnableSCLKOutput() function
Other remaining configurations items related to Synchronous Mode (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigSyncMode
CR2 CLKEN LL_USART_ConfigSyncMode
CR3 SCEN LL_USART_ConfigSyncMode
CR3 IREN LL_USART_ConfigSyncMode
CR3 HDSEL LL_USART_ConfigSyncMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2685 of file stm32wbxx_ll_usart.h.

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FLAG_Management

Defines | Functions
FLAG_Management
USART Exported Functions

Defines

#define | LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE
#define | LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF

Functions

__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_PE (USART_TypeDef *USARTx)
Check if the USART Parity Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_FE (USART_TypeDef *USARTx)
Check if the USART Framing Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_NE (USART_TypeDef *USARTx)
Check if the USART Noise error detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_ORE (USART_TypeDef *USARTx)
Check if the USART OverRun Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_IDLE (USART_TypeDef *USARTx)
Check if the USART IDLE line detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RXNE_RXFNE (USART_TypeDef *USARTx)
Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TC (USART_TypeDef *USARTx)
Check if the USART Transmission Complete Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TXE_TXFNF (USART_TypeDef *USARTx)
Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_LBD (USART_TypeDef *USARTx)
Check if the USART LIN Break Detection Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_nCTS (USART_TypeDef *USARTx)
Check if the USART CTS interrupt Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_CTS (USART_TypeDef *USARTx)
Check if the USART CTS Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RTO (USART_TypeDef *USARTx)
Check if the USART Receiver Time Out Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_EOB (USART_TypeDef *USARTx)
Check if the USART End Of Block Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_UDR (USART_TypeDef *USARTx)
Check if the SPI Slave Underrun error flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_ABRE (USART_TypeDef *USARTx)
Check if the USART Auto-Baud Rate Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_ABR (USART_TypeDef *USARTx)
Check if the USART Auto-Baud Rate Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_BUSY (USART_TypeDef *USARTx)
Check if the USART Busy Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_CM (USART_TypeDef *USARTx)
Check if the USART Character Match Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_SBK (USART_TypeDef *USARTx)
Check if the USART Send Break Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RWU (USART_TypeDef *USARTx)
Check if the USART Receive Wake Up from mute mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_WKUP (USART_TypeDef *USARTx)
Check if the USART Wake Up from stop mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TEACK (USART_TypeDef *USARTx)
Check if the USART Transmit Enable Acknowledge Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_REACK (USART_TypeDef *USARTx)
Check if the USART Receive Enable Acknowledge Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TXFE (USART_TypeDef *USARTx)
Check if the USART TX FIFO Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RXFF (USART_TypeDef *USARTx)
Check if the USART RX FIFO Full Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TCBGT (USART_TypeDef *USARTx)
Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TXFT (USART_TypeDef *USARTx)
Check if the USART TX FIFO Threshold Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RXFT (USART_TypeDef *USARTx)
Check if the USART RX FIFO Threshold Flag is set or not.
__STATIC_INLINE void | LL_USART_ClearFlag_PE (USART_TypeDef *USARTx)
Clear Parity Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_FE (USART_TypeDef *USARTx)
Clear Framing Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_NE (USART_TypeDef *USARTx)
Clear Noise Error detected Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_ORE (USART_TypeDef *USARTx)
Clear OverRun Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_IDLE (USART_TypeDef *USARTx)
Clear IDLE line detected Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_TXFE (USART_TypeDef *USARTx)
Clear TX FIFO Empty Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_TC (USART_TypeDef *USARTx)
Clear Transmission Complete Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_TCBGT (USART_TypeDef *USARTx)
Clear Smartcard Transmission Complete Before Guard Time Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_LBD (USART_TypeDef *USARTx)
Clear LIN Break Detection Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_nCTS (USART_TypeDef *USARTx)
Clear CTS Interrupt Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_RTO (USART_TypeDef *USARTx)
Clear Receiver Time Out Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_EOB (USART_TypeDef *USARTx)
Clear End Of Block Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_UDR (USART_TypeDef *USARTx)
Clear SPI Slave Underrun Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_CM (USART_TypeDef *USARTx)
Clear Character Match Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_WKUP (USART_TypeDef *USARTx)
Clear Wake Up from stop mode Flag.

Define Documentation

#define LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE

Definition at line 2957 of file stm32wbxx_ll_usart.h.

#define LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF

Definition at line 2984 of file stm32wbxx_ll_usart.h.

Function Documentation

__STATIC_INLINE void LL_USART_ClearFlag_CM ( USART_TypeDef * USARTx )

Clear Character Match Flag.

Reference Manual to LL API cross reference:
ICR CMCF LL_USART_ClearFlag_CM
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3402 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_EOB ( USART_TypeDef * USARTx )

Clear End Of Block Flag.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ICR EOBCF LL_USART_ClearFlag_EOB
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3378 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_FE ( USART_TypeDef * USARTx )

Clear Framing Error Flag.

Reference Manual to LL API cross reference:
ICR FECF LL_USART_ClearFlag_FE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3260 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_IDLE ( USART_TypeDef * USARTx )

Clear IDLE line detected Flag.

Reference Manual to LL API cross reference:
ICR IDLECF LL_USART_ClearFlag_IDLE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3293 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_LBD ( USART_TypeDef * USARTx )

Clear LIN Break Detection Flag.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ICR LBDCF LL_USART_ClearFlag_LBD
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3341 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_nCTS ( USART_TypeDef * USARTx )

Clear CTS Interrupt Flag.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ICR CTSCF LL_USART_ClearFlag_nCTS
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3354 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_NE ( USART_TypeDef * USARTx )

Clear Noise Error detected Flag.

Reference Manual to LL API cross reference:
ICR NECF LL_USART_ClearFlag_NE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3271 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_ORE ( USART_TypeDef * USARTx )

Clear OverRun Error Flag.

Reference Manual to LL API cross reference:
ICR ORECF LL_USART_ClearFlag_ORE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3282 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_PE ( USART_TypeDef * USARTx )

Clear Parity Error Flag.

Reference Manual to LL API cross reference:
ICR PECF LL_USART_ClearFlag_PE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3249 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_RTO ( USART_TypeDef * USARTx )

Clear Receiver Time Out Flag.

Reference Manual to LL API cross reference:
ICR RTOCF LL_USART_ClearFlag_RTO
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3365 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_TC ( USART_TypeDef * USARTx )

Clear Transmission Complete Flag.

Reference Manual to LL API cross reference:
ICR TCCF LL_USART_ClearFlag_TC
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3317 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_TCBGT ( USART_TypeDef * USARTx )

Clear Smartcard Transmission Complete Before Guard Time Flag.

Reference Manual to LL API cross reference:
ICR TCBGTCF LL_USART_ClearFlag_TCBGT
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3328 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_TXFE ( USART_TypeDef * USARTx )

Clear TX FIFO Empty Flag.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ICR TXFECF LL_USART_ClearFlag_TXFE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3306 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_UDR ( USART_TypeDef * USARTx )

Clear SPI Slave Underrun Flag.

Note:
Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not SPI Slave mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ICR UDRCF LL_USART_ClearFlag_UDR
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3391 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_WKUP ( USART_TypeDef * USARTx )

Clear Wake Up from stop mode Flag.

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ICR WUCF LL_USART_ClearFlag_WKUP
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3415 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR ( USART_TypeDef * USARTx )

Check if the USART Auto-Baud Rate Flag is set or not.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR ABRF LL_USART_IsActiveFlag_ABR
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3096 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE ( USART_TypeDef * USARTx )

Check if the USART Auto-Baud Rate Error Flag is set or not.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR ABRE LL_USART_IsActiveFlag_ABRE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3083 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY ( USART_TypeDef * USARTx )

Check if the USART Busy Flag is set or not.

Reference Manual to LL API cross reference:
ISR BUSY LL_USART_IsActiveFlag_BUSY
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3107 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM ( USART_TypeDef * USARTx )

Check if the USART Character Match Flag is set or not.

Reference Manual to LL API cross reference:
ISR CMF LL_USART_IsActiveFlag_CM
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3118 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS ( USART_TypeDef * USARTx )

Check if the USART CTS Flag is set or not.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR CTS LL_USART_IsActiveFlag_CTS
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3033 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB ( USART_TypeDef * USARTx )

Check if the USART End Of Block Flag is set or not.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR EOBF LL_USART_IsActiveFlag_EOB
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3057 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE ( USART_TypeDef * USARTx )

Check if the USART Framing Error Flag is set or not.

Reference Manual to LL API cross reference:
ISR FE LL_USART_IsActiveFlag_FE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2918 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE ( USART_TypeDef * USARTx )

Check if the USART IDLE line detected Flag is set or not.

Reference Manual to LL API cross reference:
ISR IDLE LL_USART_IsActiveFlag_IDLE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2951 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD ( USART_TypeDef * USARTx )

Check if the USART LIN Break Detection Flag is set or not.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR LBDF LL_USART_IsActiveFlag_LBD
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3007 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS ( USART_TypeDef * USARTx )

Check if the USART CTS interrupt Flag is set or not.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR CTSIF LL_USART_IsActiveFlag_nCTS
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3020 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE ( USART_TypeDef * USARTx )

Check if the USART Noise error detected Flag is set or not.

Reference Manual to LL API cross reference:
ISR NE LL_USART_IsActiveFlag_NE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2929 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE ( USART_TypeDef * USARTx )

Check if the USART OverRun Error Flag is set or not.

Reference Manual to LL API cross reference:
ISR ORE LL_USART_IsActiveFlag_ORE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2940 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE ( USART_TypeDef * USARTx )

Check if the USART Parity Error Flag is set or not.

Reference Manual to LL API cross reference:
ISR PE LL_USART_IsActiveFlag_PE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2907 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK ( USART_TypeDef * USARTx )

Check if the USART Receive Enable Acknowledge Flag is set or not.

Reference Manual to LL API cross reference:
ISR REACK LL_USART_IsActiveFlag_REACK
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3175 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO ( USART_TypeDef * USARTx )

Check if the USART Receiver Time Out Flag is set or not.

Reference Manual to LL API cross reference:
ISR RTOF LL_USART_IsActiveFlag_RTO
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3044 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU ( USART_TypeDef * USARTx )

Check if the USART Receive Wake Up from mute mode Flag is set or not.

Reference Manual to LL API cross reference:
ISR RWU LL_USART_IsActiveFlag_RWU
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3140 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF ( USART_TypeDef * USARTx )

Check if the USART RX FIFO Full Flag is set or not.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR RXFF LL_USART_IsActiveFlag_RXFF
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3201 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT ( USART_TypeDef * USARTx )

Check if the USART RX FIFO Threshold Flag is set or not.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR RXFT LL_USART_IsActiveFlag_RXFT
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3238 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE ( USART_TypeDef * USARTx )

Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR RXNE_RXFNE LL_USART_IsActiveFlag_RXNE_RXFNE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2967 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK ( USART_TypeDef * USARTx )

Check if the USART Send Break Flag is set or not.

Reference Manual to LL API cross reference:
ISR SBKF LL_USART_IsActiveFlag_SBK
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3129 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC ( USART_TypeDef * USARTx )

Check if the USART Transmission Complete Flag is set or not.

Reference Manual to LL API cross reference:
ISR TC LL_USART_IsActiveFlag_TC
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2978 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT ( USART_TypeDef * USARTx )

Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not.

Reference Manual to LL API cross reference:
ISR TCBGT LL_USART_IsActiveFlag_TCBGT
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3212 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK ( USART_TypeDef * USARTx )

Check if the USART Transmit Enable Acknowledge Flag is set or not.

Reference Manual to LL API cross reference:
ISR TEACK LL_USART_IsActiveFlag_TEACK
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3164 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF ( USART_TypeDef * USARTx )

Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR TXE_TXFNF LL_USART_IsActiveFlag_TXE_TXFNF
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2994 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE ( USART_TypeDef * USARTx )

Check if the USART TX FIFO Empty Flag is set or not.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR TXFE LL_USART_IsActiveFlag_TXFE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3188 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT ( USART_TypeDef * USARTx )

Check if the USART TX FIFO Threshold Flag is set or not.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR TXFT LL_USART_IsActiveFlag_TXFT
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3225 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR ( USART_TypeDef * USARTx )

Check if the SPI Slave Underrun error flag is set or not.

Note:
Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not SPI Slave mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR UDR LL_USART_IsActiveFlag_UDR
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3070 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP ( USART_TypeDef * USARTx )

Check if the USART Wake Up from stop mode Flag is set or not.

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
ISR WUF LL_USART_IsActiveFlag_WKUP
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3153 of file stm32wbxx_ll_usart.h.

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IT_Management

Defines | Functions
IT_Management
USART Exported Functions

Defines

#define | LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE
#define | LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF
#define | LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE
#define | LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF
#define | LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE
#define | LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF

Functions

__STATIC_INLINE void | LL_USART_EnableIT_IDLE (USART_TypeDef *USARTx)
Enable IDLE Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RXNE_RXFNE (USART_TypeDef *USARTx)
Enable RX Not Empty and RX FIFO Not Empty Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TC (USART_TypeDef *USARTx)
Enable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TXE_TXFNF (USART_TypeDef *USARTx)
Enable TX Empty and TX FIFO Not Full Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_PE (USART_TypeDef *USARTx)
Enable Parity Error Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_CM (USART_TypeDef *USARTx)
Enable Character Match Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RTO (USART_TypeDef *USARTx)
Enable Receiver Timeout Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_EOB (USART_TypeDef *USARTx)
Enable End Of Block Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TXFE (USART_TypeDef *USARTx)
Enable TX FIFO Empty Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RXFF (USART_TypeDef *USARTx)
Enable RX FIFO Full Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_LBD (USART_TypeDef *USARTx)
Enable LIN Break Detection Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_ERROR (USART_TypeDef *USARTx)
Enable Error Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_CTS (USART_TypeDef *USARTx)
Enable CTS Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_WKUP (USART_TypeDef *USARTx)
Enable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TXFT (USART_TypeDef *USARTx)
Enable TX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TCBGT (USART_TypeDef *USARTx)
Enable Smartcard Transmission Complete Before Guard Time Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RXFT (USART_TypeDef *USARTx)
Enable RX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_IDLE (USART_TypeDef *USARTx)
Disable IDLE Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RXNE_RXFNE (USART_TypeDef *USARTx)
Disable RX Not Empty and RX FIFO Not Empty Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TC (USART_TypeDef *USARTx)
Disable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TXE_TXFNF (USART_TypeDef *USARTx)
Disable TX Empty and TX FIFO Not Full Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_PE (USART_TypeDef *USARTx)
Disable Parity Error Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_CM (USART_TypeDef *USARTx)
Disable Character Match Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RTO (USART_TypeDef *USARTx)
Disable Receiver Timeout Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_EOB (USART_TypeDef *USARTx)
Disable End Of Block Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TXFE (USART_TypeDef *USARTx)
Disable TX FIFO Empty Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RXFF (USART_TypeDef *USARTx)
Disable RX FIFO Full Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_LBD (USART_TypeDef *USARTx)
Disable LIN Break Detection Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_ERROR (USART_TypeDef *USARTx)
Disable Error Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_CTS (USART_TypeDef *USARTx)
Disable CTS Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_WKUP (USART_TypeDef *USARTx)
Disable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TXFT (USART_TypeDef *USARTx)
Disable TX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TCBGT (USART_TypeDef *USARTx)
Disable Smartcard Transmission Complete Before Guard Time Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RXFT (USART_TypeDef *USARTx)
Disable RX FIFO Threshold Interrupt.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_IDLE (USART_TypeDef *USARTx)
Check if the USART IDLE Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RXNE_RXFNE (USART_TypeDef *USARTx)
Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TC (USART_TypeDef *USARTx)
Check if the USART Transmission Complete Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TXE_TXFNF (USART_TypeDef *USARTx)
Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_PE (USART_TypeDef *USARTx)
Check if the USART Parity Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_CM (USART_TypeDef *USARTx)
Check if the USART Character Match Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RTO (USART_TypeDef *USARTx)
Check if the USART Receiver Timeout Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_EOB (USART_TypeDef *USARTx)
Check if the USART End Of Block Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TXFE (USART_TypeDef *USARTx)
Check if the USART TX FIFO Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RXFF (USART_TypeDef *USARTx)
Check if the USART RX FIFO Full Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_LBD (USART_TypeDef *USARTx)
Check if the USART LIN Break Detection Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_ERROR (USART_TypeDef *USARTx)
Check if the USART Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_CTS (USART_TypeDef *USARTx)
Check if the USART CTS Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_WKUP (USART_TypeDef *USARTx)
Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TXFT (USART_TypeDef *USARTx)
Check if USART TX FIFO Threshold Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TCBGT (USART_TypeDef *USARTx)
Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RXFT (USART_TypeDef *USARTx)
Check if USART RX FIFO Threshold Interrupt is enabled or disabled.

Define Documentation

#define LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE

Definition at line 3657 of file stm32wbxx_ll_usart.h.

#define LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF

Definition at line 3684 of file stm32wbxx_ll_usart.h.

#define LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE

Definition at line 3440 of file stm32wbxx_ll_usart.h.

#define LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF

Definition at line 3467 of file stm32wbxx_ll_usart.h.

#define LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE

Definition at line 3876 of file stm32wbxx_ll_usart.h.

#define LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF

Definition at line 3903 of file stm32wbxx_ll_usart.h.

Function Documentation

__STATIC_INLINE void LL_USART_DisableIT_CM ( USART_TypeDef * USARTx )

Disable Character Match Interrupt.

Reference Manual to LL API cross reference:
CR1 CMIE LL_USART_DisableIT_CM
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3716 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_CTS ( USART_TypeDef * USARTx )

Disable CTS Interrupt.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 CTSIE LL_USART_DisableIT_CTS
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3807 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_EOB ( USART_TypeDef * USARTx )

Disable End Of Block Interrupt.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 EOBIE LL_USART_DisableIT_EOB
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3740 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_ERROR ( USART_TypeDef * USARTx )

Disable Error Interrupt.

Note:
When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). 0: Interrupt is inhibited 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
Reference Manual to LL API cross reference:
CR3 EIE LL_USART_DisableIT_ERROR
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3794 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_IDLE ( USART_TypeDef * USARTx )

Disable IDLE Interrupt.

Reference Manual to LL API cross reference:
CR1 IDLEIE LL_USART_DisableIT_IDLE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3651 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_LBD ( USART_TypeDef * USARTx )

Disable LIN Break Detection Interrupt.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBDIE LL_USART_DisableIT_LBD
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3779 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_PE ( USART_TypeDef * USARTx )

Disable Parity Error Interrupt.

Reference Manual to LL API cross reference:
CR1 PEIE LL_USART_DisableIT_PE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3705 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_RTO ( USART_TypeDef * USARTx )

Disable Receiver Timeout Interrupt.

Reference Manual to LL API cross reference:
CR1 RTOIE LL_USART_DisableIT_RTO
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3727 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_RXFF ( USART_TypeDef * USARTx )

Disable RX FIFO Full Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 RXFFIE LL_USART_DisableIT_RXFF
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3766 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_RXFT ( USART_TypeDef * USARTx )

Disable RX FIFO Threshold Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RXFTIE LL_USART_DisableIT_RXFT
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3859 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE ( USART_TypeDef * USARTx )

Disable RX Not Empty and RX FIFO Not Empty Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 RXNEIE_RXFNEIE LL_USART_DisableIT_RXNE_RXFNE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3667 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_TC ( USART_TypeDef * USARTx )

Disable Transmission Complete Interrupt.

Reference Manual to LL API cross reference:
CR1 TCIE LL_USART_DisableIT_TC
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3678 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_TCBGT ( USART_TypeDef * USARTx )

Disable Smartcard Transmission Complete Before Guard Time Interrupt.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 TCBGTIE LL_USART_DisableIT_TCBGT
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3846 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF ( USART_TypeDef * USARTx )

Disable TX Empty and TX FIFO Not Full Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 TXEIE_TXFNFIE LL_USART_DisableIT_TXE_TXFNF
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3694 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_TXFE ( USART_TypeDef * USARTx )

Disable TX FIFO Empty Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 TXFEIE LL_USART_DisableIT_TXFE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3753 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_TXFT ( USART_TypeDef * USARTx )

Disable TX FIFO Threshold Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 TXFTIE LL_USART_DisableIT_TXFT
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3833 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_WKUP ( USART_TypeDef * USARTx )

Disable Wake Up from Stop Mode Interrupt.

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 WUFIE LL_USART_DisableIT_WKUP
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3820 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_CM ( USART_TypeDef * USARTx )

Enable Character Match Interrupt.

Reference Manual to LL API cross reference:
CR1 CMIE LL_USART_EnableIT_CM
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3499 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_CTS ( USART_TypeDef * USARTx )

Enable CTS Interrupt.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 CTSIE LL_USART_EnableIT_CTS
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3588 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_EOB ( USART_TypeDef * USARTx )

Enable End Of Block Interrupt.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 EOBIE LL_USART_EnableIT_EOB
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3523 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_ERROR ( USART_TypeDef * USARTx )

Enable Error Interrupt.

Note:
When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). 0: Interrupt is inhibited 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
Reference Manual to LL API cross reference:
CR3 EIE LL_USART_EnableIT_ERROR
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3575 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_IDLE ( USART_TypeDef * USARTx )

Enable IDLE Interrupt.

Reference Manual to LL API cross reference:
CR1 IDLEIE LL_USART_EnableIT_IDLE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3434 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_LBD ( USART_TypeDef * USARTx )

Enable LIN Break Detection Interrupt.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBDIE LL_USART_EnableIT_LBD
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3560 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_PE ( USART_TypeDef * USARTx )

Enable Parity Error Interrupt.

Reference Manual to LL API cross reference:
CR1 PEIE LL_USART_EnableIT_PE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3488 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_RTO ( USART_TypeDef * USARTx )

Enable Receiver Timeout Interrupt.

Reference Manual to LL API cross reference:
CR1 RTOIE LL_USART_EnableIT_RTO
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3510 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_RXFF ( USART_TypeDef * USARTx )

Enable RX FIFO Full Interrupt.

Reference Manual to LL API cross reference:
CR1 RXFFIE LL_USART_EnableIT_RXFF
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3547 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_RXFT ( USART_TypeDef * USARTx )

Enable RX FIFO Threshold Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RXFTIE LL_USART_EnableIT_RXFT
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3640 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE ( USART_TypeDef * USARTx )

Enable RX Not Empty and RX FIFO Not Empty Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 RXNEIE_RXFNEIE LL_USART_EnableIT_RXNE_RXFNE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3450 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_TC ( USART_TypeDef * USARTx )

Enable Transmission Complete Interrupt.

Reference Manual to LL API cross reference:
CR1 TCIE LL_USART_EnableIT_TC
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3461 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_TCBGT ( USART_TypeDef * USARTx )

Enable Smartcard Transmission Complete Before Guard Time Interrupt.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 TCBGTIE LL_USART_EnableIT_TCBGT
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3627 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF ( USART_TypeDef * USARTx )

Enable TX Empty and TX FIFO Not Full Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 TXEIE_TXFNFIE LL_USART_EnableIT_TXE_TXFNF
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3477 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_TXFE ( USART_TypeDef * USARTx )

Enable TX FIFO Empty Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 TXFEIE LL_USART_EnableIT_TXFE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3536 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_TXFT ( USART_TypeDef * USARTx )

Enable TX FIFO Threshold Interrupt.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 TXFTIE LL_USART_EnableIT_TXFT
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3614 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_WKUP ( USART_TypeDef * USARTx )

Enable Wake Up from Stop Mode Interrupt.

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 WUFIE LL_USART_EnableIT_WKUP
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 3601 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM ( USART_TypeDef * USARTx )

Check if the USART Character Match Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 CMIE LL_USART_IsEnabledIT_CM
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3935 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS ( USART_TypeDef * USARTx )

Check if the USART CTS Interrupt is enabled or disabled.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 CTSIE LL_USART_IsEnabledIT_CTS
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4022 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB ( USART_TypeDef * USARTx )

Check if the USART End Of Block Interrupt is enabled or disabled.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 EOBIE LL_USART_IsEnabledIT_EOB
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3959 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR ( USART_TypeDef * USARTx )

Check if the USART Error Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR3 EIE LL_USART_IsEnabledIT_ERROR
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4009 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE ( USART_TypeDef * USARTx )

Check if the USART IDLE Interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 IDLEIE LL_USART_IsEnabledIT_IDLE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3870 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD ( USART_TypeDef * USARTx )

Check if the USART LIN Break Detection Interrupt is enabled or disabled.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBDIE LL_USART_IsEnabledIT_LBD
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3998 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE ( USART_TypeDef * USARTx )

Check if the USART Parity Error Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 PEIE LL_USART_IsEnabledIT_PE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3924 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO ( USART_TypeDef * USARTx )

Check if the USART Receiver Timeout Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 RTOIE LL_USART_IsEnabledIT_RTO
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3946 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF ( USART_TypeDef * USARTx )

Check if the USART RX FIFO Full Interrupt is enabled or disabled.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 RXFFIE LL_USART_IsEnabledIT_RXFF
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3985 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT ( USART_TypeDef * USARTx )

Check if USART RX FIFO Threshold Interrupt is enabled or disabled.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RXFTIE LL_USART_IsEnabledIT_RXFT
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4074 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE ( USART_TypeDef * USARTx )

Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 RXNEIE_RXFNEIE LL_USART_IsEnabledIT_RXNE_RXFNE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3886 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC ( USART_TypeDef * USARTx )

Check if the USART Transmission Complete Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TCIE LL_USART_IsEnabledIT_TC
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3897 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT ( USART_TypeDef * USARTx )

Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 TCBGTIE LL_USART_IsEnabledIT_TCBGT
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4061 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF ( USART_TypeDef * USARTx )

Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 TXEIE_TXFNFIE LL_USART_IsEnabledIT_TXE_TXFNF
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3913 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE ( USART_TypeDef * USARTx )

Check if the USART TX FIFO Empty Interrupt is enabled or disabled.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR1 TXFEIE LL_USART_IsEnabledIT_TXFE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 3972 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT ( USART_TypeDef * USARTx )

Check if USART TX FIFO Threshold Interrupt is enabled or disabled.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 TXFTIE LL_USART_IsEnabledIT_TXFT
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4048 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP ( USART_TypeDef * USARTx )

Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.

Note:
Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not Wake-up from Stop mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 WUFIE LL_USART_IsEnabledIT_WKUP
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4035 of file stm32wbxx_ll_usart.h.

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DMA_Management

Functions
DMA_Management
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_EnableDMAReq_RX (USART_TypeDef *USARTx)
Enable DMA Mode for reception.
__STATIC_INLINE void | LL_USART_DisableDMAReq_RX (USART_TypeDef *USARTx)
Disable DMA Mode for reception.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMAReq_RX (USART_TypeDef *USARTx)
Check if DMA Mode is enabled for reception.
__STATIC_INLINE void | LL_USART_EnableDMAReq_TX (USART_TypeDef *USARTx)
Enable DMA Mode for transmission.
__STATIC_INLINE void | LL_USART_DisableDMAReq_TX (USART_TypeDef *USARTx)
Disable DMA Mode for transmission.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMAReq_TX (USART_TypeDef *USARTx)
Check if DMA Mode is enabled for transmission.
__STATIC_INLINE void | LL_USART_EnableDMADeactOnRxErr (USART_TypeDef *USARTx)
Enable DMA Disabling on Reception Error.
__STATIC_INLINE void | LL_USART_DisableDMADeactOnRxErr (USART_TypeDef *USARTx)
Disable DMA Disabling on Reception Error.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMADeactOnRxErr (USART_TypeDef *USARTx)
Indicate if DMA Disabling on Reception Error is disabled.
__STATIC_INLINE uint32_t | LL_USART_DMA_GetRegAddr (USART_TypeDef *USARTx, uint32_t Direction)
Get the data register address used for DMA transfer.

Function Documentation

__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr ( USART_TypeDef * USARTx )

Disable DMA Disabling on Reception Error.

Reference Manual to LL API cross reference:
CR3 DDRE LL_USART_DisableDMADeactOnRxErr
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4170 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableDMAReq_RX ( USART_TypeDef * USARTx )

Disable DMA Mode for reception.

Reference Manual to LL API cross reference:
CR3 DMAR LL_USART_DisableDMAReq_RX
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4104 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableDMAReq_TX ( USART_TypeDef * USARTx )

Disable DMA Mode for transmission.

Reference Manual to LL API cross reference:
CR3 DMAT LL_USART_DisableDMAReq_TX
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4137 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Direction
 | ) |  |

Get the data register address used for DMA transfer.

Reference Manual to LL API cross reference:
RDR RDR LL_USART_DMA_GetRegAddr
Reference Manual to LL API cross reference:
TDR TDR LL_USART_DMA_GetRegAddr
Parameters:
USARTx USART Instance
Direction This parameter can be one of the following values:
  • LL_USART_DMA_REG_DATA_TRANSMIT
  • LL_USART_DMA_REG_DATA_RECEIVE
Return values:
Address of data register

Definition at line 4196 of file stm32wbxx_ll_usart.h.

References LL_USART_DMA_REG_DATA_TRANSMIT.

__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr ( USART_TypeDef * USARTx )

Enable DMA Disabling on Reception Error.

Reference Manual to LL API cross reference:
CR3 DDRE LL_USART_EnableDMADeactOnRxErr
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4159 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableDMAReq_RX ( USART_TypeDef * USARTx )

Enable DMA Mode for reception.

Reference Manual to LL API cross reference:
CR3 DMAR LL_USART_EnableDMAReq_RX
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4093 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableDMAReq_TX ( USART_TypeDef * USARTx )

Enable DMA Mode for transmission.

Reference Manual to LL API cross reference:
CR3 DMAT LL_USART_EnableDMAReq_TX
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4126 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr ( USART_TypeDef * USARTx )

Indicate if DMA Disabling on Reception Error is disabled.

Reference Manual to LL API cross reference:
CR3 DDRE LL_USART_IsEnabledDMADeactOnRxErr
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4181 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX ( USART_TypeDef * USARTx )

Check if DMA Mode is enabled for reception.

Reference Manual to LL API cross reference:
CR3 DMAR LL_USART_IsEnabledDMAReq_RX
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4115 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX ( USART_TypeDef * USARTx )

Check if DMA Mode is enabled for transmission.

Reference Manual to LL API cross reference:
CR3 DMAT LL_USART_IsEnabledDMAReq_TX
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 4148 of file stm32wbxx_ll_usart.h.

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data_Management

Functions
Data_Management
USART Exported Functions

Functions

__STATIC_INLINE uint8_t | LL_USART_ReceiveData8 (USART_TypeDef *USARTx)
Read Receiver Data register (Receive Data value, 8 bits)
__STATIC_INLINE uint16_t | LL_USART_ReceiveData9 (USART_TypeDef *USARTx)
Read Receiver Data register (Receive Data value, 9 bits)
__STATIC_INLINE void | LL_USART_TransmitData8 (USART_TypeDef *USARTx, uint8_t Value)
Write in Transmitter Data Register (Transmit Data value, 8 bits)
__STATIC_INLINE void | LL_USART_TransmitData9 (USART_TypeDef *USARTx, uint16_t Value)
Write in Transmitter Data Register (Transmit Data value, 9 bits)

Function Documentation

__STATIC_INLINE uint8_t LL_USART_ReceiveData8 ( USART_TypeDef * USARTx )

Read Receiver Data register (Receive Data value, 8 bits)

Reference Manual to LL API cross reference:
RDR RDR LL_USART_ReceiveData8
Parameters:
USARTx USART Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 4228 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE uint16_t LL_USART_ReceiveData9 ( USART_TypeDef * USARTx )

Read Receiver Data register (Receive Data value, 9 bits)

Reference Manual to LL API cross reference:
RDR RDR LL_USART_ReceiveData9
Parameters:
USARTx USART Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x1FF

Definition at line 4239 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_TransmitData8 | ( | USART_TypeDef * | USARTx,
 |  | uint8_t | Value
 | ) |  |

Write in Transmitter Data Register (Transmit Data value, 8 bits)

Reference Manual to LL API cross reference:
TDR TDR LL_USART_TransmitData8
Parameters:
USARTx | USART Instance
Value | between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 4251 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_TransmitData9 | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | Value
 | ) |  |

Write in Transmitter Data Register (Transmit Data value, 9 bits)

Reference Manual to LL API cross reference:
TDR TDR LL_USART_TransmitData9
Parameters:
USARTx | USART Instance
Value | between Min_Data=0x00 and Max_Data=0x1FF
Return values:
None

Definition at line 4263 of file stm32wbxx_ll_usart.h.

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Execution

Functions
Execution
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_RequestAutoBaudRate (USART_TypeDef *USARTx)
Request an Automatic Baud Rate measurement on next received data frame.
__STATIC_INLINE void | LL_USART_RequestBreakSending (USART_TypeDef *USARTx)
Request Break sending.
__STATIC_INLINE void | LL_USART_RequestEnterMuteMode (USART_TypeDef *USARTx)
Put USART in mute mode and set the RWU flag.
__STATIC_INLINE void | LL_USART_RequestRxDataFlush (USART_TypeDef *USARTx)
Request a Receive Data and FIFO flush.
__STATIC_INLINE void | LL_USART_RequestTxDataFlush (USART_TypeDef *USARTx)
Request a Transmit data and FIFO flush.

Function Documentation

__STATIC_INLINE void LL_USART_RequestAutoBaudRate ( USART_TypeDef * USARTx )

Request an Automatic Baud Rate measurement on next received data frame.

Note:
Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not Auto Baud Rate detection feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
RQR ABRRQ LL_USART_RequestAutoBaudRate
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4284 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_RequestBreakSending ( USART_TypeDef * USARTx )

Request Break sending.

Reference Manual to LL API cross reference:
RQR SBKRQ LL_USART_RequestBreakSending
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4295 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_RequestEnterMuteMode ( USART_TypeDef * USARTx )

Put USART in mute mode and set the RWU flag.

Reference Manual to LL API cross reference:
RQR MMRQ LL_USART_RequestEnterMuteMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4306 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_RequestRxDataFlush ( USART_TypeDef * USARTx )

Request a Receive Data and FIFO flush.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Allows to discard the received data without reading them, and avoid an overrun condition.
Reference Manual to LL API cross reference:
RQR RXFRQ LL_USART_RequestRxDataFlush
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4321 of file stm32wbxx_ll_usart.h.

__STATIC_INLINE void LL_USART_RequestTxDataFlush ( USART_TypeDef * USARTx )

Request a Transmit data and FIFO flush.

Note:
Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not FIFO mode feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
RQR TXFRQ LL_USART_RequestTxDataFlush
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 4334 of file stm32wbxx_ll_usart.h.

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
USART Exported Functions

Functions

ErrorStatus | LL_USART_DeInit (USART_TypeDef *USARTx)
De-initialize USART registers (Registers restored to their default values).
ErrorStatus | LL_USART_Init (USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
Initialize USART registers according to the specified parameters in USART_InitStruct.
void | LL_USART_StructInit (LL_USART_InitTypeDef *USART_InitStruct)
Set each LL_USART_InitTypeDef field to default value.
ErrorStatus | LL_USART_ClockInit (USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Initialize USART Clock related settings according to the specified parameters in the USART_ClockInitStruct.
void | LL_USART_ClockStructInit (LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Set each field of a LL_USART_ClockInitTypeDef type structure to default value.

Function Documentation

ErrorStatus LL_USART_ClockInit | ( | USART_TypeDef * | USARTx,
 |  | LL_USART_ClockInitTypeDef * | USART_ClockInitStruct
 | ) |  |

Initialize USART Clock related settings according to the specified parameters in the USART_ClockInitStruct.

Note:
As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
Parameters:
USARTx | USART Instance
USART_ClockInitStruct | pointer to a LL_USART_ClockInitTypeDef structure that contains the Clock configuration information for the specified USART peripheral.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
  • ERROR: Problem occurred during USART Registers initialization

Definition at line 300 of file stm32wbxx_ll_usart.c.

References assert_param, LL_USART_ClockInitTypeDef::ClockOutput, LL_USART_ClockInitTypeDef::ClockPhase, LL_USART_ClockInitTypeDef::ClockPolarity, IS_LL_USART_CLOCKOUTPUT, IS_LL_USART_CLOCKPHASE, IS_LL_USART_CLOCKPOLARITY, IS_LL_USART_LASTBITCLKOUTPUT, LL_USART_ClockInitTypeDef::LastBitClockPulse, LL_USART_CLOCK_DISABLE, LL_USART_DisableSCLKOutput(), and LL_USART_IsEnabled().

void LL_USART_ClockStructInit ( LL_USART_ClockInitTypeDef * USART_ClockInitStruct )

Set each field of a LL_USART_ClockInitTypeDef type structure to default value.

Parameters:
USART_ClockInitStruct pointer to a LL_USART_ClockInitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 359 of file stm32wbxx_ll_usart.c.

References LL_USART_ClockInitTypeDef::ClockOutput, LL_USART_ClockInitTypeDef::ClockPhase, LL_USART_ClockInitTypeDef::ClockPolarity, LL_USART_ClockInitTypeDef::LastBitClockPulse, LL_USART_CLOCK_DISABLE, LL_USART_LASTCLKPULSE_NO_OUTPUT, LL_USART_PHASE_1EDGE, and LL_USART_POLARITY_LOW.

ErrorStatus LL_USART_DeInit ( USART_TypeDef * USARTx )

De-initialize USART registers (Registers restored to their default values).

Parameters:
USARTx USART Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: USART registers are de-initialized
  • ERROR: USART registers are not de-initialized

Definition at line 141 of file stm32wbxx_ll_usart.c.

References assert_param, LL_APB2_GRP1_ForceReset(), LL_APB2_GRP1_PERIPH_USART1, and LL_APB2_GRP1_ReleaseReset().

ErrorStatus LL_USART_Init | ( | USART_TypeDef * | USARTx,
 |  | LL_USART_InitTypeDef * | USART_InitStruct
 | ) |  |

Initialize USART registers according to the specified parameters in USART_InitStruct.

Note:
As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
Parameters:
USARTx | USART Instance
USART_InitStruct | pointer to a LL_USART_InitTypeDef structure that contains the configuration information for the specified USART peripheral.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: USART registers are initialized according to USART_InitStruct content
  • ERROR: Problem occurred during USART Registers initialization

Definition at line 177 of file stm32wbxx_ll_usart.c.

References assert_param, LL_USART_InitTypeDef::BaudRate, LL_USART_InitTypeDef::DataWidth, LL_USART_InitTypeDef::HardwareFlowControl, IS_LL_USART_BAUDRATE, IS_LL_USART_BRR_MAX, IS_LL_USART_BRR_MIN, IS_LL_USART_DATAWIDTH, IS_LL_USART_DIRECTION, IS_LL_USART_HWCONTROL, IS_LL_USART_OVERSAMPLING, IS_LL_USART_PARITY, IS_LL_USART_PRESCALER, IS_LL_USART_STOPBITS, LL_RCC_GetUSARTClockFreq(), LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_USART1_CLKSOURCE, LL_USART_IsEnabled(), LL_USART_SetBaudRate(), LL_USART_SetHWFlowCtrl(), LL_USART_SetPrescaler(), LL_USART_SetStopBitsLength(), LL_USART_InitTypeDef::OverSampling, LL_USART_InitTypeDef::Parity, LL_USART_InitTypeDef::PrescalerValue, LL_USART_InitTypeDef::StopBits, and LL_USART_InitTypeDef::TransferDirection.

void LL_USART_StructInit ( LL_USART_InitTypeDef * USART_InitStruct )

Set each LL_USART_InitTypeDef field to default value.

Parameters:
USART_InitStruct pointer to a LL_USART_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 275 of file stm32wbxx_ll_usart.c.

References LL_USART_InitTypeDef::BaudRate, LL_USART_InitTypeDef::DataWidth, LL_USART_InitTypeDef::HardwareFlowControl, LL_USART_DATAWIDTH_8B, LL_USART_DIRECTION_TX_RX, LL_USART_HWCONTROL_NONE, LL_USART_OVERSAMPLING_16, LL_USART_PARITY_NONE, LL_USART_PRESCALER_DIV1, LL_USART_STOPBITS_1, LL_USART_InitTypeDef::OverSampling, LL_USART_InitTypeDef::Parity, LL_USART_InitTypeDef::PrescalerValue, LL_USART_InitTypeDef::StopBits, and LL_USART_InitTypeDef::TransferDirection.

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: UTILS Private functions

Functions
UTILS Private functions
UTILS

Functions

static uint32_t | UTILS_GetPLLOutputFrequency (uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
Function to check that PLL can be modified.
static ErrorStatus | UTILS_SetFlashLatency (uint32_t HCLK4_Frequency)
Update number of Flash wait states in line with new frequency and current voltage range.
static ErrorStatus | UTILS_EnablePLLAndSwitchSystem (uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
Function to enable PLL and switch system clock to PLL.
static ErrorStatus | UTILS_PLL_IsBusy (void)
Function to check that PLL can be modified.

Function Documentation

static ErrorStatus UTILS_EnablePLLAndSwitchSystem | ( | uint32_t | SYSCLK_Frequency,
 |  | LL_UTILS_ClkInitTypeDef * | UTILS_ClkInitStruct
 | ) |  | [static]

Function to enable PLL and switch system clock to PLL.

Parameters:
SYSCLK_Frequency | SYSCLK frequency
UTILS_ClkInitStruct | pointer to a LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: No problem to switch system to PLL
  • ERROR: Problem to switch system to PLL

Definition at line 660 of file stm32wbxx_ll_utils.c.

References __LL_RCC_CALC_HCLK1_FREQ, __LL_RCC_CALC_HCLK4_FREQ, LL_UTILS_ClkInitTypeDef::AHB4CLKDivider, LL_UTILS_ClkInitTypeDef::APB1CLKDivider, LL_UTILS_ClkInitTypeDef::APB2CLKDivider, assert_param, LL_UTILS_ClkInitTypeDef::CPU1CLKDivider, LL_UTILS_ClkInitTypeDef::CPU2CLKDivider, IS_LL_UTILS_APB1_DIV, IS_LL_UTILS_APB2_DIV, IS_LL_UTILS_SYSCLK_DIV, LL_C2_RCC_SetAHBPrescaler(), LL_RCC_GetAHB4Prescaler(), LL_RCC_GetAHBPrescaler(), LL_RCC_GetSysClkSource(), LL_RCC_PLL_Enable(), LL_RCC_PLL_EnableDomain_SYS(), LL_RCC_PLL_IsReady(), LL_RCC_SetAHB4Prescaler(), LL_RCC_SetAHBPrescaler(), LL_RCC_SetAPB1Prescaler(), LL_RCC_SetAPB2Prescaler(), LL_RCC_SetSysClkSource(), LL_RCC_SYS_CLKSOURCE_PLL, LL_RCC_SYS_CLKSOURCE_STATUS_PLL, LL_SetSystemCoreClock(), and UTILS_SetFlashLatency().

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), and LL_PLL_ConfigSystemClock_MSI().

static uint32_t UTILS_GetPLLOutputFrequency | ( | uint32_t | PLL_InputFrequency,
 |  | LL_UTILS_PLLInitTypeDef * | UTILS_PLLInitStruct
 | ) |  | [static]

Function to check that PLL can be modified.

Parameters:
PLL_InputFrequency | PLL input frequency (in Hz)
UTILS_PLLInitStruct | pointer to a LL_UTILS_PLLInitTypeDef structure that contains the configuration information for the PLL.
Return values:
PLL output frequency (in Hz)

Definition at line 598 of file stm32wbxx_ll_utils.c.

References assert_param, IS_LL_UTILS_PLL_FREQUENCY, IS_LL_UTILS_PLLM_VALUE, IS_LL_UTILS_PLLN_VALUE, IS_LL_UTILS_PLLR_VALUE, IS_LL_UTILS_PLLVCO_INPUT, IS_LL_UTILS_PLLVCO_OUTPUT, LL_UTILS_PLLInitTypeDef::PLLM, LL_UTILS_PLLInitTypeDef::PLLN, and LL_UTILS_PLLInitTypeDef::PLLR.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), and LL_PLL_ConfigSystemClock_MSI().

static ErrorStatus UTILS_PLL_IsBusy ( void ) [static]

Function to check that PLL can be modified.

Return values:
An ErrorStatus enumeration value:
  • SUCCESS: PLL modification can be done
  • ERROR: PLL is busy

Definition at line 629 of file stm32wbxx_ll_utils.c.

References LL_RCC_PLL_IsReady(), and LL_RCC_PLLSAI1_IsReady().

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), and LL_PLL_ConfigSystemClock_MSI().

static ErrorStatus UTILS_SetFlashLatency ( uint32_t HCLK4_Frequency ) [static]

Update number of Flash wait states in line with new frequency and current voltage range.

Parameters:
HCLK4_Frequency HCLK4 frequency
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: Latency has been modified
  • ERROR: Latency cannot be modified

Definition at line 521 of file stm32wbxx_ll_utils.c.

References countof, LL_FLASH_GetLatency(), LL_FLASH_LATENCY_0, LL_FLASH_LATENCY_1, LL_FLASH_LATENCY_2, LL_FLASH_LATENCY_3, LL_FLASH_SetLatency(), LL_PWR_GetRegulVoltageScaling(), LL_PWR_REGU_VOLTAGE_SCALE1, UTILS_MAX_FREQUENCY_SCALE1, and UTILS_MAX_FREQUENCY_SCALE2.

Referenced by UTILS_EnablePLLAndSwitchSystem().

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: UTILS Private Constants

Defines
UTILS Private Constants
UTILS

Defines

#define | UTILS_MAX_FREQUENCY_SCALE1 64000000U
#define | UTILS_MAX_FREQUENCY_SCALE2 16000000U
#define | UTILS_PLLVCO_INPUT_MIN 2660000U
#define | UTILS_PLLVCO_INPUT_MAX 16000000U
#define | UTILS_PLLVCO_OUTPUT_MIN 96000000U
#define | UTILS_PLLVCO_OUTPUT_MAX 344000000U
#define | UTILS_HCLK2_MAX 32000000U
#define | LL_MAX_DELAY 0xFFFFFFFFU
#define | UID_BASE_ADDRESS UID_BASE
Unique device ID register base address.
#define | FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
Flash size data register base address.
#define | PACKAGE_BASE_ADDRESS PACKAGE_BASE
Package data register base address.

Define Documentation

#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE

Flash size data register base address.

Definition at line 70 of file stm32wbxx_ll_utils.h.

Referenced by LL_GetFlashSize().

#define LL_MAX_DELAY 0xFFFFFFFFU

Definition at line 60 of file stm32wbxx_ll_utils.h.

Referenced by LL_mDelay().

#define PACKAGE_BASE_ADDRESS PACKAGE_BASE

Package data register base address.

Definition at line 75 of file stm32wbxx_ll_utils.h.

Referenced by LL_GetPackageType().

#define UID_BASE_ADDRESS UID_BASE

Unique device ID register base address.

Definition at line 65 of file stm32wbxx_ll_utils.h.

Referenced by LL_GetUID_Word0(), LL_GetUID_Word1(), and LL_GetUID_Word2().

#define UTILS_HCLK2_MAX 32000000U

HCLK2 frequency maximum at 32MHz

Definition at line 56 of file stm32wbxx_ll_utils.c.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), and LL_PLL_ConfigSystemClock_MSI().

#define UTILS_MAX_FREQUENCY_SCALE1 64000000U

Maximum frequency for system clock at power scale1, in Hz

Definition at line 44 of file stm32wbxx_ll_utils.c.

Referenced by UTILS_SetFlashLatency().

#define UTILS_MAX_FREQUENCY_SCALE2 16000000U

Maximum frequency for system clock at power scale2, in Hz

Definition at line 46 of file stm32wbxx_ll_utils.c.

Referenced by UTILS_SetFlashLatency().

#define UTILS_PLLVCO_INPUT_MAX 16000000U

Frequency max for PLLVCO input, in Hz

Definition at line 51 of file stm32wbxx_ll_utils.c.

#define UTILS_PLLVCO_INPUT_MIN 2660000U

Frequency min for PLLVCO input, in Hz

Definition at line 50 of file stm32wbxx_ll_utils.c.

#define UTILS_PLLVCO_OUTPUT_MAX 344000000U

Frequency max for PLLVCO output, in Hz

Definition at line 53 of file stm32wbxx_ll_utils.c.

#define UTILS_PLLVCO_OUTPUT_MIN 96000000U

Frequency min for PLLVCO output, in Hz

Definition at line 52 of file stm32wbxx_ll_utils.c.

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: UTILS Private Macros

Defines
UTILS Private Macros
UTILS

Defines

#define | IS_LL_UTILS_SYSCLK_DIV(__VALUE__)
#define | IS_LL_UTILS_APB1_DIV(__VALUE__)
#define | IS_LL_UTILS_APB2_DIV(__VALUE__)
#define | IS_LL_UTILS_PLLM_VALUE(__VALUE__)
#define | IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((6U <= (__VALUE__)) && ((__VALUE__) <= 127U))
#define | IS_LL_UTILS_PLLR_VALUE(__VALUE__)
#define | IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))
#define | IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))
#define | IS_LL_UTILS_PLL_FREQUENCY(__VALUE__)
#define | IS_LL_UTILS_HSE_BYPASS(__STATE__)
#define | countof(a) (sizeof(a) / sizeof(*(a)))

Define Documentation

#define countof ( a ) (sizeof(a) / sizeof(*(a)))

Definition at line 126 of file stm32wbxx_ll_utils.c.

Referenced by UTILS_SetFlashLatency().

#define IS_LL_UTILS_APB1_DIV ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_APB1_DIV_1) \
                                      || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
                                      || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
                                      || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
                                      || ((__VALUE__) == LL_RCC_APB1_DIV_16))

Definition at line 81 of file stm32wbxx_ll_utils.c.

Referenced by UTILS_EnablePLLAndSwitchSystem().

#define IS_LL_UTILS_APB2_DIV ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_APB2_DIV_1) \
                                      || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
                                      || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
                                      || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
                                      || ((__VALUE__) == LL_RCC_APB2_DIV_16))

Definition at line 87 of file stm32wbxx_ll_utils.c.

Referenced by UTILS_EnablePLLAndSwitchSystem().

#define IS_LL_UTILS_HSE_BYPASS ( __STATE__ )
Value:
(((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
                                        || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))

Definition at line 123 of file stm32wbxx_ll_utils.c.

Referenced by LL_PLL_ConfigSystemClock_HSE().

#define IS_LL_UTILS_PLL_FREQUENCY ( __VALUE__ )
Value:
((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
                                             ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2))

Definition at line 117 of file stm32wbxx_ll_utils.c.

Referenced by UTILS_GetPLLOutputFrequency().

#define IS_LL_UTILS_PLLM_VALUE ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_PLLM_DIV_1) \
                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_2) \
                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \
                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \
                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \
                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \
                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \
                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_8))

Definition at line 93 of file stm32wbxx_ll_utils.c.

Referenced by UTILS_GetPLLOutputFrequency().

#define IS_LL_UTILS_PLLN_VALUE ( __VALUE__ ) ((6U <= (__VALUE__)) && ((__VALUE__) <= 127U))

Definition at line 102 of file stm32wbxx_ll_utils.c.

Referenced by UTILS_GetPLLOutputFrequency().

#define IS_LL_UTILS_PLLR_VALUE ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_PLLR_DIV_2) \
                                        || ((__VALUE__) == LL_RCC_PLLR_DIV_3) \
                                        || ((__VALUE__) == LL_RCC_PLLR_DIV_4) \
                                        || ((__VALUE__) == LL_RCC_PLLR_DIV_5) \
                                        || ((__VALUE__) == LL_RCC_PLLR_DIV_6) \
                                        || ((__VALUE__) == LL_RCC_PLLR_DIV_7) \
                                        || ((__VALUE__) == LL_RCC_PLLR_DIV_8))

Definition at line 104 of file stm32wbxx_ll_utils.c.

Referenced by UTILS_GetPLLOutputFrequency().

#define IS_LL_UTILS_PLLVCO_INPUT ( __VALUE__ ) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))

Definition at line 112 of file stm32wbxx_ll_utils.c.

Referenced by UTILS_GetPLLOutputFrequency().

#define IS_LL_UTILS_PLLVCO_OUTPUT ( __VALUE__ ) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))

Definition at line 114 of file stm32wbxx_ll_utils.c.

Referenced by UTILS_GetPLLOutputFrequency().

#define IS_LL_UTILS_SYSCLK_DIV ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_SYSCLK_DIV_1)   \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2)   \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_3)   \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4)   \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_5)   \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_6)   \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8)   \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_10)  \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16)  \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_32)  \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64)  \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))

Definition at line 66 of file stm32wbxx_ll_utils.c.

Referenced by UTILS_EnablePLLAndSwitchSystem().

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LL_UTILS_PLLInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_UTILS_PLLInitTypeDef Struct Reference
UTILS Exported structures

UTILS PLL structure definition. More...

#include <stm32wbxx_ll_utils.h>

Data Fields

uint32_t | PLLM
uint32_t | PLLN
uint32_t | PLLR

Detailed Description

UTILS PLL structure definition.

Definition at line 95 of file stm32wbxx_ll_utils.h.

Field Documentation

uint32_t LL_UTILS_PLLInitTypeDef::PLLM

Division factor for PLL VCO input clock. This parameter can be a value of PLL and PLLSAI1 division factor

This feature can be modified afterwards using unitary function LL_RCC_PLL_ConfigDomain_SYS().

Definition at line 97 of file stm32wbxx_ll_utils.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), LL_PLL_ConfigSystemClock_MSI(), and UTILS_GetPLLOutputFrequency().

uint32_t LL_UTILS_PLLInitTypeDef::PLLN

Multiplication factor for PLL VCO output clock. This parameter must be a number between Min_Data = 6 and Max_Data = 127

This feature can be modified afterwards using unitary function LL_RCC_PLL_ConfigDomain_SYS().

Definition at line 103 of file stm32wbxx_ll_utils.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), LL_PLL_ConfigSystemClock_MSI(), and UTILS_GetPLLOutputFrequency().

uint32_t LL_UTILS_PLLInitTypeDef::PLLR

Division for the main system clock. This parameter can be a value of PLL division factor (PLLR)

This feature can be modified afterwards using unitary function LL_RCC_PLL_ConfigDomain_SYS().

Definition at line 109 of file stm32wbxx_ll_utils.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), LL_PLL_ConfigSystemClock_MSI(), and UTILS_GetPLLOutputFrequency().

The documentation for this struct was generated from the following file:
  • stm32wbxx_ll_utils.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LL_UTILS_ClkInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_UTILS_ClkInitTypeDef Struct Reference
UTILS Exported structures

UTILS System, AHB and APB buses clock configuration structure definition. More...

#include <stm32wbxx_ll_utils.h>

Data Fields

uint32_t | CPU1CLKDivider
uint32_t | CPU2CLKDivider
uint32_t | AHB4CLKDivider
uint32_t | APB1CLKDivider
uint32_t | APB2CLKDivider

Detailed Description

UTILS System, AHB and APB buses clock configuration structure definition.

Definition at line 119 of file stm32wbxx_ll_utils.h.

Field Documentation

uint32_t LL_UTILS_ClkInitTypeDef::AHB4CLKDivider

The AHBS clock (HCLK4) divider. This clock is derived from the system clock (SYSCLK). This parameter can be a value of AHB prescaler

This feature can be modified afterwards using unitary function LL_RCC_SetAHB4Prescaler().

Definition at line 133 of file stm32wbxx_ll_utils.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

uint32_t LL_UTILS_ClkInitTypeDef::APB1CLKDivider

The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK1). This parameter can be a value of APB low-speed prescaler (APB1)

This feature can be modified afterwards using unitary function LL_RCC_SetAPB1Prescaler().

Definition at line 139 of file stm32wbxx_ll_utils.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

uint32_t LL_UTILS_ClkInitTypeDef::APB2CLKDivider

The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK1). This parameter can be a value of APB high-speed prescaler (APB2)

This feature can be modified afterwards using unitary function LL_RCC_SetAPB2Prescaler().

Definition at line 145 of file stm32wbxx_ll_utils.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

uint32_t LL_UTILS_ClkInitTypeDef::CPU1CLKDivider

The CPU1 clock (HCLK1) divider. This clock is derived from the system clock (SYSCLK). This parameter can be a value of AHB prescaler

This feature can be modified afterwards using unitary function LL_RCC_SetAHBPrescaler().

Definition at line 121 of file stm32wbxx_ll_utils.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

uint32_t LL_UTILS_ClkInitTypeDef::CPU2CLKDivider

The CPU2 clock (HCLK2) divider. This clock is derived from the system clock (SYSCLK). This parameter can be a value of AHB prescaler

This feature can be modified afterwards using unitary function LL_C2_RCC_SetAHBPrescaler().

Definition at line 127 of file stm32wbxx_ll_utils.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), LL_PLL_ConfigSystemClock_MSI(), and UTILS_EnablePLLAndSwitchSystem().

The documentation for this struct was generated from the following file:
  • stm32wbxx_ll_utils.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: HSE Bypass activation

Defines
HSE Bypass activation
UTILS Exported Constants

Defines

#define | LL_UTILS_HSEBYPASS_OFF 0x00000000U
#define | LL_UTILS_HSEBYPASS_ON 0x00000001U

Define Documentation

#define LL_UTILS_HSEBYPASS_OFF 0x00000000U

HSE Bypass is not enabled

Definition at line 165 of file stm32wbxx_ll_utils.h.

#define LL_UTILS_HSEBYPASS_ON 0x00000001U

HSE Bypass is enabled

Definition at line 166 of file stm32wbxx_ll_utils.h.

Referenced by LL_PLL_ConfigSystemClock_HSE().

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PACKAGE TYPE

Defines
PACKAGE TYPE
UTILS Exported Constants

Defines

#define | LL_UTILS_PACKAGETYPE_CSP100 0x00000011U
#define | LL_UTILS_PACKAGETYPE_CSP100_C 0x00000012U
#define | LL_UTILS_PACKAGETYPE_QFN68 0x00000013U
#define | LL_UTILS_PACKAGETYPE_QFN68_C 0x00000014U
#define | LL_UTILS_PACKAGETYPE_QFN48 0x0000000AU
#define | LL_UTILS_PACKAGETYPE_QFN48_C 0x00000015U

Define Documentation

#define LL_UTILS_PACKAGETYPE_CSP100 0x00000011U

CSP100 package type

Definition at line 174 of file stm32wbxx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_CSP100_C 0x00000012U

CSP100 package type w/ capfree LDO

Definition at line 175 of file stm32wbxx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_QFN48 0x0000000AU

QFN48 package type

Definition at line 178 of file stm32wbxx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_QFN48_C 0x00000015U

QFN48 package type w/ capfree LDO

Definition at line 179 of file stm32wbxx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_QFN68 0x00000013U

QFN68 package type

Definition at line 176 of file stm32wbxx_ll_utils.h.

#define LL_UTILS_PACKAGETYPE_QFN68_C 0x00000014U

QFN68 package type w/ capfree LDO

Definition at line 177 of file stm32wbxx_ll_utils.h.

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DEVICE ELECTRONIC SIGNATURE

Functions
DEVICE ELECTRONIC SIGNATURE
UTILS Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_GetUID_Word0 (void)
Get Word0 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetUID_Word1 (void)
Get Word1 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetUID_Word2 (void)
Get Word2 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetFlashSize (void)
Get Flash memory size.
__STATIC_INLINE uint32_t | LL_GetPackageType (void)
Get Package type.

Function Documentation

__STATIC_INLINE uint32_t LL_GetFlashSize ( void )

Get Flash memory size.

Note:
This bitfield indicates the size of the device Flash memory expressed in Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
Return values:
FLASH_SIZE[15:0],: Flash memory size

Definition at line 231 of file stm32wbxx_ll_utils.h.

References FLASHSIZE_BASE_ADDRESS.

__STATIC_INLINE uint32_t LL_GetPackageType ( void )

Get Package type.

Return values:
Returned value can be one of the following values:
  • LL_UTILS_PACKAGETYPE_CSP100
  • LL_UTILS_PACKAGETYPE_CSP100_C
  • LL_UTILS_PACKAGETYPE_QFN68
  • LL_UTILS_PACKAGETYPE_QFN68_C
  • LL_UTILS_PACKAGETYPE_QFN48
  • LL_UTILS_PACKAGETYPE_QFN48_C

Definition at line 247 of file stm32wbxx_ll_utils.h.

References PACKAGE_BASE_ADDRESS.

__STATIC_INLINE uint32_t LL_GetUID_Word0 ( void )

Get Word0 of the unique device identifier (UID based on 96 bits)

Return values:
UID[31:0],: X and Y coordinates on the wafer expressed in BCD format

Definition at line 202 of file stm32wbxx_ll_utils.h.

References UID_BASE_ADDRESS.

__STATIC_INLINE uint32_t LL_GetUID_Word1 ( void )

Get Word1 of the unique device identifier (UID based on 96 bits)

Return values:
UID[63:32],: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])

Definition at line 211 of file stm32wbxx_ll_utils.h.

References UID_BASE_ADDRESS.

__STATIC_INLINE uint32_t LL_GetUID_Word2 ( void )

Get Word2 of the unique device identifier (UID based on 96 bits)

Return values:
UID[95:64],: Lot number (ASCII encoded) - LOT_NUM[55:24]

Definition at line 220 of file stm32wbxx_ll_utils.h.

References UID_BASE_ADDRESS.

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DELAY

Functions
DELAY
UTILS Exported Functions

Functions

void | LL_Init1msTick (uint32_t HCLKFrequency)
This function configures the Cortex-M SysTick source to have 1ms time base.
void | LL_mDelay (uint32_t Delay)
This function provides accurate delay (in milliseconds) based on SysTick counter flag.
__STATIC_INLINE void | LL_InitTick (uint32_t HCLKFrequency, uint32_t Ticks)
This function configures the Cortex-M SysTick source of the time base.

Function Documentation

void LL_Init1msTick ( uint32_t HCLKFrequency )

This function configures the Cortex-M SysTick source to have 1ms time base.

Note:
When a RTOS is used, it is recommended to avoid changing the Systick configuration by calling this function, for a delay use rather osDelay RTOS service.
Parameters:
HCLKFrequency HCLK frequency in Hz
Note:
HCLK frequency can be calculated thanks to RCC helper macro or function LL_RCC_GetSystemClocksFreq (HCLK1_Frequency field)
Return values:
None

Definition at line 160 of file stm32wbxx_ll_utils.c.

References LL_InitTick().

__STATIC_INLINE void LL_InitTick | ( | uint32_t | HCLKFrequency,
 |  | uint32_t | Ticks
 | ) |  |

This function configures the Cortex-M SysTick source of the time base.

Parameters:
HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro or function LL_RCC_GetSystemClocksFreq (HCLK1_Frequency field))
Note:
When a RTOS is used, it is recommended to avoid changing the SysTick configuration by calling this function, for a delay use rather osDelay RTOS service.
Parameters:
Ticks Number of ticks
Return values:
None

Definition at line 267 of file stm32wbxx_ll_utils.h.

Referenced by LL_Init1msTick().

void LL_mDelay ( uint32_t Delay )

This function provides accurate delay (in milliseconds) based on SysTick counter flag.

Note:
When a RTOS is used, it is recommended to avoid using blocking delay and use rather osDelay service.
To respect 1ms timebase, user should call LL_Init1msTick function which will configure Systick to 1ms
Parameters:
Delay specifies the delay time length, in milliseconds.
Return values:
None

Definition at line 177 of file stm32wbxx_ll_utils.c.

References LL_MAX_DELAY.

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SYSTEM

Functions
SYSTEM
UTILS Exported Functions

System Configuration functions. More...

Functions

void | LL_SetSystemCoreClock (uint32_t HCLKFrequency)
This function sets directly SystemCoreClock CMSIS variable.
ErrorStatus | LL_PLL_ConfigSystemClock_MSI (LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock with MSI as clock source of the PLL.
ErrorStatus | LL_PLL_ConfigSystemClock_HSI (LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock at maximum frequency with HSI as clock source of the PLL.
ErrorStatus | LL_PLL_ConfigSystemClock_HSE (uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock with HSE as clock source of the PLL.

Detailed Description

System Configuration functions.

 ===============================================================================
           ##### System Configuration functions #####
 ===============================================================================
    [..]
         System, HCLK1, HCLK2, AHBS, AHBRF and APB buses clocks configuration

         (+) The maximum frequency of the SYSCLK, HCLK1, HCLK4, PCLK1 and PCLK2
             is 640000000 Hz.
 ....... (+) The maximum frequency of the HCLK2 is 320000000 Hz.

Function Documentation

ErrorStatus LL_PLL_ConfigSystemClock_HSE | ( | uint32_t | HSEBypass,
 |  | LL_UTILS_PLLInitTypeDef * | UTILS_PLLInitStruct,
 |  | LL_UTILS_ClkInitTypeDef * | UTILS_ClkInitStruct
 | ) |  |

This function configures system clock with HSE as clock source of the PLL.

Note:
The application need to ensure that PLL and/or PLLSAI1 are disabled.
The application needs to ensure that PLL configuration is valid
The application needs to ensure that BUS prescalers are valid
Function is based on the following formula:
  • PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLR)
  • PLLM: ensure that the VCO input frequency ranges from 2.66 to 16 MHz (PLLVCO_input = HSE frequency / PLLM)
  • PLLN: ensure that the VCO output frequency is between 96 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
  • PLLR: ensure that max frequency at 64000000 Hz is reached (PLLVCO_output / PLLR)
Parameters:
HSEBypass This parameter can be one of the following values:
  • LL_UTILS_HSEBYPASS_ON
  • LL_UTILS_HSEBYPASS_OFF
UTILS_PLLInitStruct | pointer to a LL_UTILS_PLLInitTypeDef structure that contains the configuration information for the PLL.
UTILS_ClkInitStruct | pointer to a LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: Max frequency configuration done
  • ERROR: Max frequency configuration not done

Definition at line 438 of file stm32wbxx_ll_utils.c.

References __LL_RCC_CALC_HCLK2_FREQ, assert_param, LL_UTILS_ClkInitTypeDef::CPU2CLKDivider, HSE_VALUE, IS_LL_UTILS_HSE_BYPASS, LL_RCC_HSE_DisableBypass(), LL_RCC_HSE_Enable(), LL_RCC_HSE_EnableBypass(), LL_RCC_HSE_IsReady(), LL_RCC_PLL_ConfigDomain_SYS(), LL_RCC_PLLSOURCE_HSE, LL_UTILS_HSEBYPASS_ON, LL_UTILS_PLLInitTypeDef::PLLM, LL_UTILS_PLLInitTypeDef::PLLN, LL_UTILS_PLLInitTypeDef::PLLR, UTILS_EnablePLLAndSwitchSystem(), UTILS_GetPLLOutputFrequency(), UTILS_HCLK2_MAX, and UTILS_PLL_IsBusy().

ErrorStatus LL_PLL_ConfigSystemClock_HSI | ( | LL_UTILS_PLLInitTypeDef * | UTILS_PLLInitStruct,
 |  | LL_UTILS_ClkInitTypeDef * | UTILS_ClkInitStruct
 | ) |  |

This function configures system clock at maximum frequency with HSI as clock source of the PLL.

Note:
The application need to ensure that PLL and/or PLLSAI1 are disabled.
The application needs to ensure that PLL configuration is valid
The application needs to ensure that BUS prescalers are valid
Function is based on the following formula:
  • PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLR)
  • PLLM: ensure that the VCO input frequency ranges from 2.66 to 16 MHz (PLLVCO_input = HSI frequency / PLLM)
  • PLLN: ensure that the VCO output frequency is between 96 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
  • PLLR: ensure that max frequency at 64000000 Hz is reach (PLLVCO_output / PLLR)
Parameters:
UTILS_PLLInitStruct | pointer to a LL_UTILS_PLLInitTypeDef structure that contains the configuration information for the PLL.
UTILS_ClkInitStruct | pointer to a LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: Max frequency configuration done
  • ERROR: Max frequency configuration not done

Definition at line 369 of file stm32wbxx_ll_utils.c.

References __LL_RCC_CALC_HCLK2_FREQ, LL_UTILS_ClkInitTypeDef::CPU2CLKDivider, HSI_VALUE, LL_RCC_HSI_Enable(), LL_RCC_HSI_IsReady(), LL_RCC_PLL_ConfigDomain_SYS(), LL_RCC_PLLSOURCE_HSI, LL_UTILS_PLLInitTypeDef::PLLM, LL_UTILS_PLLInitTypeDef::PLLN, LL_UTILS_PLLInitTypeDef::PLLR, UTILS_EnablePLLAndSwitchSystem(), UTILS_GetPLLOutputFrequency(), UTILS_HCLK2_MAX, and UTILS_PLL_IsBusy().

ErrorStatus LL_PLL_ConfigSystemClock_MSI | ( | LL_UTILS_PLLInitTypeDef * | UTILS_PLLInitStruct,
 |  | LL_UTILS_ClkInitTypeDef * | UTILS_ClkInitStruct
 | ) |  |

This function configures system clock with MSI as clock source of the PLL.

Note:
The application needs to ensure that PLL and PLLSAI1 are disabled.
The application needs to ensure that PLL configuration is valid
The application needs to ensure that MSI range is valid.
The application needs to ensure that BUS prescalers are valid
Function is based on the following formula:
  • PLL output frequency = (((MSI frequency / PLLM) * PLLN) / PLLR)
  • PLLM: ensure that the VCO input frequency ranges from 2.66 to 16 MHz (PLLVCO_input = MSI frequency / PLLM)
  • PLLN: ensure that the VCO output frequency is between 96 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
  • PLLR: ensure that max frequency at 64000000 Hz is reached (PLLVCO_output / PLLR)
Parameters:
UTILS_PLLInitStruct | pointer to a LL_UTILS_PLLInitTypeDef structure that contains the configuration information for the PLL.
UTILS_ClkInitStruct | pointer to a LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: Max frequency configuration done
  • ERROR: Max frequency configuration not done

Definition at line 271 of file stm32wbxx_ll_utils.c.

References __LL_RCC_CALC_HCLK2_FREQ, __LL_RCC_CALC_MSI_FREQ, LL_UTILS_ClkInitTypeDef::CPU2CLKDivider, LL_RCC_MSI_Enable(), LL_RCC_MSI_GetRange(), LL_RCC_MSI_IsReady(), LL_RCC_MSIRANGE_0, LL_RCC_MSIRANGE_1, LL_RCC_MSIRANGE_10, LL_RCC_MSIRANGE_11, LL_RCC_MSIRANGE_2, LL_RCC_MSIRANGE_3, LL_RCC_MSIRANGE_4, LL_RCC_MSIRANGE_5, LL_RCC_MSIRANGE_6, LL_RCC_MSIRANGE_7, LL_RCC_MSIRANGE_8, LL_RCC_MSIRANGE_9, LL_RCC_PLL_ConfigDomain_SYS(), LL_RCC_PLLSOURCE_MSI, LL_UTILS_PLLInitTypeDef::PLLM, LL_UTILS_PLLInitTypeDef::PLLN, LL_UTILS_PLLInitTypeDef::PLLR, UTILS_EnablePLLAndSwitchSystem(), UTILS_GetPLLOutputFrequency(), UTILS_HCLK2_MAX, and UTILS_PLL_IsBusy().

void LL_SetSystemCoreClock ( uint32_t HCLKFrequency )

This function sets directly SystemCoreClock CMSIS variable.

Note:
Variable can be calculated also through SystemCoreClockUpdate function.
Parameters:
HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro or function LL_RCC_GetSystemClocksFreq (HCLK1_Frequency field))
Return values:
None

Definition at line 246 of file stm32wbxx_ll_utils.c.

Referenced by UTILS_EnablePLLAndSwitchSystem().

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STM32WB55xx HAL User Manual: WWDG

Modules
WWDG
STM32WBxx_LL_Driver

Modules

WWDG Exported Constants
WWDG Exported Macros
WWDG Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for WWDG registers.

Register | Bit | Function
CFR | EWI | LL_WWDG_EnableIT_EWKUP
 |  | LL_WWDG_IsEnabledIT_EWKUP
 | W | LL_WWDG_GetWindow
 |  | LL_WWDG_SetWindow
 | WDGTB | LL_WWDG_GetPrescaler
 |  | LL_WWDG_SetPrescaler
CR | T | LL_WWDG_GetCounter
 |  | LL_WWDG_SetCounter
 | WDGA | LL_WWDG_Enable
 |  | LL_WWDG_IsEnabled
SR | EWIF | LL_WWDG_ClearFlag_EWKUP
 |  | LL_WWDG_IsActiveFlag_EWKUP
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STM32WB55xx HAL User Manual: IT Defines

Defines
IT Defines
WWDG Exported Constants

IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions. More...

Defines

#define LL_WWDG_CFR_EWI WWDG_CFR_EWI

Detailed Description

IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions.

Define Documentation

#define LL_WWDG_CFR_EWI WWDG_CFR_EWI

Definition at line 55 of file stm32wbxx_ll_wwdg.h.

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STM32WB55xx HAL User Manual: PRESCALER

Defines
PRESCALER
WWDG Exported Constants

Defines

#define | LL_WWDG_PRESCALER_1 0x00000000u
#define | LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0
#define | LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1
#define | LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1)
#define | LL_WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2
#define | LL_WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0)
#define | LL_WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1)
#define | LL_WWDG_PRESCALER_128 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)

Define Documentation

#define LL_WWDG_PRESCALER_1 0x00000000u

WWDG counter clock = (PCLK1/4096)/1

Definition at line 63 of file stm32wbxx_ll_wwdg.h.

#define LL_WWDG_PRESCALER_128 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)

WWDG counter clock = (PCLK1/4096)/128

Definition at line 70 of file stm32wbxx_ll_wwdg.h.

#define LL_WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2

WWDG counter clock = (PCLK1/4096)/16

Definition at line 67 of file stm32wbxx_ll_wwdg.h.

#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0

WWDG counter clock = (PCLK1/4096)/2

Definition at line 64 of file stm32wbxx_ll_wwdg.h.

#define LL_WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0)

WWDG counter clock = (PCLK1/4096)/32

Definition at line 68 of file stm32wbxx_ll_wwdg.h.

#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1

WWDG counter clock = (PCLK1/4096)/4

Definition at line 65 of file stm32wbxx_ll_wwdg.h.

#define LL_WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1)

WWDG counter clock = (PCLK1/4096)/64

Definition at line 69 of file stm32wbxx_ll_wwdg.h.

#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1)

WWDG counter clock = (PCLK1/4096)/8

Definition at line 66 of file stm32wbxx_ll_wwdg.h.

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STM32WB55xx HAL User Manual: Common Write and read registers macros

Defines
Common Write and read registers macros
WWDG Exported Macros

Defines

#define | LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in WWDG register.
#define | LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in WWDG register.

Define Documentation

#define LL_WWDG_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in WWDG register.

Parameters:
__INSTANCE__ | WWDG Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 101 of file stm32wbxx_ll_wwdg.h.

#define LL_WWDG_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in WWDG register.

Parameters:
__INSTANCE__ | WWDG Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 93 of file stm32wbxx_ll_wwdg.h.

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STM32WB55xx HAL User Manual: Configuration

Functions
Configuration
WWDG Exported Functions

Functions

__STATIC_INLINE void | LL_WWDG_Enable (WWDG_TypeDef *WWDGx)
Enable Window Watchdog.
__STATIC_INLINE uint32_t | LL_WWDG_IsEnabled (WWDG_TypeDef *WWDGx)
Checks if Window Watchdog is enabled.
__STATIC_INLINE void | LL_WWDG_SetCounter (WWDG_TypeDef *WWDGx, uint32_t Counter)
Set the Watchdog counter value to provided value (7-bits T[6:0])
__STATIC_INLINE uint32_t | LL_WWDG_GetCounter (WWDG_TypeDef *WWDGx)
Return current Watchdog Counter Value (7 bits counter value)
__STATIC_INLINE void | LL_WWDG_SetPrescaler (WWDG_TypeDef *WWDGx, uint32_t Prescaler)
Set the time base of the prescaler (WDGTB).
__STATIC_INLINE uint32_t | LL_WWDG_GetPrescaler (WWDG_TypeDef *WWDGx)
Return current Watchdog Prescaler Value.
__STATIC_INLINE void | LL_WWDG_SetWindow (WWDG_TypeDef *WWDGx, uint32_t Window)
Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
__STATIC_INLINE uint32_t | LL_WWDG_GetWindow (WWDG_TypeDef *WWDGx)
Return current Watchdog Window Value (7 bits value)

Function Documentation

__STATIC_INLINE void LL_WWDG_Enable ( WWDG_TypeDef * WWDGx )

Enable Window Watchdog.

The watchdog is always disabled after a reset.

Note:
It is enabled by setting the WDGA bit in the WWDG_CR register, then it cannot be disabled again except by a reset. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset.
Reference Manual to LL API cross reference:
CR WDGA LL_WWDG_Enable
Parameters:
WWDGx WWDG Instance
Return values:
None

Definition at line 128 of file stm32wbxx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_GetCounter ( WWDG_TypeDef * WWDGx )

Return current Watchdog Counter Value (7 bits counter value)

Reference Manual to LL API cross reference:
CR T LL_WWDG_GetCounter
Parameters:
WWDGx WWDG Instance
Return values:
7 bit Watchdog Counter value

Definition at line 166 of file stm32wbxx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler ( WWDG_TypeDef * WWDGx )

Return current Watchdog Prescaler Value.

Reference Manual to LL API cross reference:
CFR WDGTB LL_WWDG_GetPrescaler
Parameters:
WWDGx WWDG Instance
Return values:
Returned value can be one of the following values:
  • LL_WWDG_PRESCALER_1
  • LL_WWDG_PRESCALER_2
  • LL_WWDG_PRESCALER_4
  • LL_WWDG_PRESCALER_8
  • LL_WWDG_PRESCALER_16
  • LL_WWDG_PRESCALER_32
  • LL_WWDG_PRESCALER_64
  • LL_WWDG_PRESCALER_128

Definition at line 207 of file stm32wbxx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_GetWindow ( WWDG_TypeDef * WWDGx )

Return current Watchdog Window Value (7 bits value)

Reference Manual to LL API cross reference:
CFR W LL_WWDG_GetWindow
Parameters:
WWDGx WWDG Instance
Return values:
7 bit Watchdog Window value

Definition at line 239 of file stm32wbxx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_IsEnabled ( WWDG_TypeDef * WWDGx )

Checks if Window Watchdog is enabled.

Reference Manual to LL API cross reference:
CR WDGA LL_WWDG_IsEnabled
Parameters:
WWDGx WWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 139 of file stm32wbxx_ll_wwdg.h.

__STATIC_INLINE void LL_WWDG_SetCounter | ( | WWDG_TypeDef * | WWDGx,
 |  | uint32_t | Counter
 | ) |  |

Set the Watchdog counter value to provided value (7-bits T[6:0])

Note:
When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset This counter is decremented every (4096 x 2expWDGTB) PCLK cycles A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared) Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
Reference Manual to LL API cross reference:
CR T LL_WWDG_SetCounter
Parameters:
WWDGx | WWDG Instance
Counter | 0..0x7F (7 bit counter value)
Return values:
None

Definition at line 155 of file stm32wbxx_ll_wwdg.h.

__STATIC_INLINE void LL_WWDG_SetPrescaler | ( | WWDG_TypeDef * | WWDGx,
 |  | uint32_t | Prescaler
 | ) |  |

Set the time base of the prescaler (WDGTB).

Note:
Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter is decremented every (4096 x 2expWDGTB) PCLK cycles
Reference Manual to LL API cross reference:
CFR WDGTB LL_WWDG_SetPrescaler
Parameters:
WWDGx WWDG Instance
Prescaler This parameter can be one of the following values:
  • LL_WWDG_PRESCALER_1
  • LL_WWDG_PRESCALER_2
  • LL_WWDG_PRESCALER_4
  • LL_WWDG_PRESCALER_8
  • LL_WWDG_PRESCALER_16
  • LL_WWDG_PRESCALER_32
  • LL_WWDG_PRESCALER_64
  • LL_WWDG_PRESCALER_128
Return values:
None

Definition at line 188 of file stm32wbxx_ll_wwdg.h.

__STATIC_INLINE void LL_WWDG_SetWindow | ( | WWDG_TypeDef * | WWDGx,
 |  | uint32_t | Window
 | ) |  |

Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).

Note:
This window value defines when write in the WWDG_CR register to program Watchdog counter is allowed. Watchdog counter value update must occur only when the counter value is lower than the Watchdog window register value. Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value (in the control register) is refreshed before the downcounter has reached the watchdog window register value. Physically is possible to set the Window lower then 0x40 but it is not recommended. To generate an immediate reset, it is possible to set the Counter lower than 0x40.
Reference Manual to LL API cross reference:
CFR W LL_WWDG_SetWindow
Parameters:
WWDGx | WWDG Instance
Window | 0x00..0x7F (7 bit Window value)
Return values:
None

Definition at line 228 of file stm32wbxx_ll_wwdg.h.

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FLAG_Management

Functions
FLAG_Management
WWDG Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_WWDG_IsActiveFlag_EWKUP (WWDG_TypeDef *WWDGx)
Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
__STATIC_INLINE void | LL_WWDG_ClearFlag_EWKUP (WWDG_TypeDef *WWDGx)
Clear WWDG Early Wakeup Interrupt Flag (EWIF)

Function Documentation

__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP ( WWDG_TypeDef * WWDGx )

Clear WWDG Early Wakeup Interrupt Flag (EWIF)

Reference Manual to LL API cross reference:
SR EWIF LL_WWDG_ClearFlag_EWKUP
Parameters:
WWDGx WWDG Instance
Return values:
None

Definition at line 271 of file stm32wbxx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP ( WWDG_TypeDef * WWDGx )

Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.

Note:
This bit is set by hardware when the counter has reached the value 0x40. It must be cleared by software by writing 0. A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
Reference Manual to LL API cross reference:
SR EWIF LL_WWDG_IsActiveFlag_EWKUP
Parameters:
WWDGx WWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 260 of file stm32wbxx_ll_wwdg.h.

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IT_Management

Functions
IT_Management
WWDG Exported Functions

Functions

__STATIC_INLINE void | LL_WWDG_EnableIT_EWKUP (WWDG_TypeDef *WWDGx)
Enable the Early Wakeup Interrupt.
__STATIC_INLINE uint32_t | LL_WWDG_IsEnabledIT_EWKUP (WWDG_TypeDef *WWDGx)
Check if Early Wakeup Interrupt is enabled.

Function Documentation

__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP ( WWDG_TypeDef * WWDGx )

Enable the Early Wakeup Interrupt.

Note:
When set, an interrupt occurs whenever the counter reaches value 0x40. This interrupt is only cleared by hardware after a reset
Reference Manual to LL API cross reference:
CFR EWI LL_WWDG_EnableIT_EWKUP
Parameters:
WWDGx WWDG Instance
Return values:
None

Definition at line 291 of file stm32wbxx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP ( WWDG_TypeDef * WWDGx )

Check if Early Wakeup Interrupt is enabled.

Reference Manual to LL API cross reference:
CFR EWI LL_WWDG_IsEnabledIT_EWKUP
Parameters:
WWDGx WWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 302 of file stm32wbxx_ll_wwdg.h.

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: HAL Private Constants

Defines
HAL Private Constants
HAL

Defines

#define | __STM32WBxx_HAL_VERSION_MAIN (0x01U)
STM32WBxx HAL Driver version number.
#define | __STM32WBxx_HAL_VERSION_SUB1 (0x03U)
#define | __STM32WBxx_HAL_VERSION_SUB2 (0x00U)
#define | __STM32WBxx_HAL_VERSION_RC (0x00U)
#define | __STM32WBxx_HAL_VERSION
#define | VREFBUF_TIMEOUT_VALUE 10U /* 10 ms */

Define Documentation

#define __STM32WBxx_HAL_VERSION
Value:
((__STM32WBxx_HAL_VERSION_MAIN << 24U)\
                                        |(__STM32WBxx_HAL_VERSION_SUB1 << 16U)\
                                        |(__STM32WBxx_HAL_VERSION_SUB2 << 8U )\
                                        |(__STM32WBxx_HAL_VERSION_RC))

Definition at line 62 of file stm32wbxx_hal.c.

Referenced by HAL_GetHalVersion().

#define __STM32WBxx_HAL_VERSION_MAIN (0x01U)

STM32WBxx HAL Driver version number.

[31:24] main version

Definition at line 58 of file stm32wbxx_hal.c.

#define __STM32WBxx_HAL_VERSION_RC (0x00U)

[7:0] release candidate

Definition at line 61 of file stm32wbxx_hal.c.

#define __STM32WBxx_HAL_VERSION_SUB1 (0x03U)

[23:16] sub1 version

Definition at line 59 of file stm32wbxx_hal.c.

#define __STM32WBxx_HAL_VERSION_SUB2 (0x00U)

[15:8] sub2 version

Definition at line 60 of file stm32wbxx_hal.c.

#define VREFBUF_TIMEOUT_VALUE 10U /* 10 ms */

Definition at line 68 of file stm32wbxx_hal.c.

Referenced by HAL_SYSCFG_EnableVREFBUF().

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STM32WB55xx HAL User Manual: HAL Exported Variables

Variables
HAL Exported Variables
HAL | HAL Exported Functions

Variables

__IO uint32_t | uwTick
uint32_t | uwTickPrio = (1UL << __NVIC_PRIO_BITS)
uint32_t | uwTickFreq = HAL_TICK_FREQ_DEFAULT
__IO uint32_t | uwTick
uint32_t | uwTickPrio
uint32_t | uwTickFreq

Variable Documentation

__IO uint32_t uwTick

Definition at line 80 of file stm32wbxx_hal.c.

Referenced by HAL_GetTick(), and HAL_IncTick().

__IO uint32_t uwTick

Definition at line 80 of file stm32wbxx_hal.c.

Referenced by HAL_GetTick(), and HAL_IncTick().

uint32_t uwTickFreq = HAL_TICK_FREQ_DEFAULT

Definition at line 82 of file stm32wbxx_hal.c.

Referenced by HAL_Delay(), HAL_GetTickFreq(), HAL_IncTick(), HAL_InitTick(), and HAL_SetTickFreq().

uint32_t uwTickFreq

Definition at line 82 of file stm32wbxx_hal.c.

Referenced by HAL_Delay(), HAL_GetTickFreq(), HAL_IncTick(), HAL_InitTick(), and HAL_SetTickFreq().

uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS)

Definition at line 81 of file stm32wbxx_hal.c.

Referenced by HAL_GetTickPrio(), HAL_InitTick(), HAL_RCC_DeInit(), HAL_RCC_OscConfig(), and HAL_SetTickFreq().

uint32_t uwTickPrio

Definition at line 81 of file stm32wbxx_hal.c.

Referenced by HAL_GetTickPrio(), HAL_InitTick(), HAL_RCC_DeInit(), HAL_RCC_OscConfig(), and HAL_SetTickFreq().

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STM32WB55xx HAL User Manual: Tick Frequency

Defines
Tick Frequency
HAL Exported Constants

Defines

#define | HAL_TICK_FREQ_10HZ 100U
#define | HAL_TICK_FREQ_100HZ 10U
#define | HAL_TICK_FREQ_1KHZ 1U
#define | HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ

Define Documentation

#define HAL_TICK_FREQ_100HZ 10U

Definition at line 50 of file stm32wbxx_hal.h.

#define HAL_TICK_FREQ_10HZ 100U

Definition at line 49 of file stm32wbxx_hal.h.

#define HAL_TICK_FREQ_1KHZ 1U

Definition at line 51 of file stm32wbxx_hal.h.

#define HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ

Definition at line 52 of file stm32wbxx_hal.h.

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STM32WB55xx HAL User Manual: BOOT Mode

Defines
BOOT Mode
SYSCFG Exported Constants

Defines

#define | SYSCFG_BOOT_MAINFLASH LL_SYSCFG_REMAP_FLASH
#define | SYSCFG_BOOT_SYSTEMFLASH LL_SYSCFG_REMAP_SYSTEMFLASH
#define | SYSCFG_BOOT_SRAM LL_SYSCFG_REMAP_SRAM
#define | SYSCFG_BOOT_QUADSPI LL_SYSCFG_REMAP_QUADSPI

Define Documentation

#define SYSCFG_BOOT_MAINFLASH LL_SYSCFG_REMAP_FLASH

Main Flash memory mapped at 0x00000000

Definition at line 65 of file stm32wbxx_hal.h.

#define SYSCFG_BOOT_QUADSPI LL_SYSCFG_REMAP_QUADSPI

QUADSPI memory mapped at 0x00000000

Definition at line 69 of file stm32wbxx_hal.h.

#define SYSCFG_BOOT_SRAM LL_SYSCFG_REMAP_SRAM

SRAM1 mapped at 0x00000000

Definition at line 67 of file stm32wbxx_hal.h.

#define SYSCFG_BOOT_SYSTEMFLASH LL_SYSCFG_REMAP_SYSTEMFLASH

System Flash memory mapped at 0x00000000

Definition at line 66 of file stm32wbxx_hal.h.

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STM32WB55xx HAL User Manual: FPU Interrupts

Defines
FPU Interrupts
SYSCFG Exported Constants

Defines

#define | SYSCFG_IT_FPU_IOC SYSCFG_CFGR1_FPU_IE_0
#define | SYSCFG_IT_FPU_DZC SYSCFG_CFGR1_FPU_IE_1
#define | SYSCFG_IT_FPU_UFC SYSCFG_CFGR1_FPU_IE_2
#define | SYSCFG_IT_FPU_OFC SYSCFG_CFGR1_FPU_IE_3
#define | SYSCFG_IT_FPU_IDC SYSCFG_CFGR1_FPU_IE_4
#define | SYSCFG_IT_FPU_IXC SYSCFG_CFGR1_FPU_IE_5

Define Documentation

#define SYSCFG_IT_FPU_DZC SYSCFG_CFGR1_FPU_IE_1

Floating Point Unit Divide-by-zero Interrupt

Definition at line 79 of file stm32wbxx_hal.h.

#define SYSCFG_IT_FPU_IDC SYSCFG_CFGR1_FPU_IE_4

Floating Point Unit Input denormal Interrupt

Definition at line 82 of file stm32wbxx_hal.h.

#define SYSCFG_IT_FPU_IOC SYSCFG_CFGR1_FPU_IE_0

Floating Point Unit Invalid operation Interrupt

Definition at line 78 of file stm32wbxx_hal.h.

#define SYSCFG_IT_FPU_IXC SYSCFG_CFGR1_FPU_IE_5

Floating Point Unit Inexact Interrupt

Definition at line 83 of file stm32wbxx_hal.h.

#define SYSCFG_IT_FPU_OFC SYSCFG_CFGR1_FPU_IE_3

Floating Point Unit Overflow Interrupt

Definition at line 81 of file stm32wbxx_hal.h.

#define SYSCFG_IT_FPU_UFC SYSCFG_CFGR1_FPU_IE_2

Floating Point Unit Underflow Interrupt

Definition at line 80 of file stm32wbxx_hal.h.

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STM32WB55xx HAL User Manual: SRAM2 Page Write protection (0 to 31)

Defines
SRAM2 Page Write protection (0 to 31)
SYSCFG Exported Constants

Defines

#define | SYSCFG_SRAM2WRP_PAGE0 LL_SYSCFG_SRAM2WRP_PAGE0
#define | SYSCFG_SRAM2WRP_PAGE1 LL_SYSCFG_SRAM2WRP_PAGE1
#define | SYSCFG_SRAM2WRP_PAGE2 LL_SYSCFG_SRAM2WRP_PAGE2
#define | SYSCFG_SRAM2WRP_PAGE3 LL_SYSCFG_SRAM2WRP_PAGE3
#define | SYSCFG_SRAM2WRP_PAGE4 LL_SYSCFG_SRAM2WRP_PAGE4
#define | SYSCFG_SRAM2WRP_PAGE5 LL_SYSCFG_SRAM2WRP_PAGE5
#define | SYSCFG_SRAM2WRP_PAGE6 LL_SYSCFG_SRAM2WRP_PAGE6
#define | SYSCFG_SRAM2WRP_PAGE7 LL_SYSCFG_SRAM2WRP_PAGE7
#define | SYSCFG_SRAM2WRP_PAGE8 LL_SYSCFG_SRAM2WRP_PAGE8
#define | SYSCFG_SRAM2WRP_PAGE9 LL_SYSCFG_SRAM2WRP_PAGE9
#define | SYSCFG_SRAM2WRP_PAGE10 LL_SYSCFG_SRAM2WRP_PAGE10
#define | SYSCFG_SRAM2WRP_PAGE11 LL_SYSCFG_SRAM2WRP_PAGE11
#define | SYSCFG_SRAM2WRP_PAGE12 LL_SYSCFG_SRAM2WRP_PAGE12
#define | SYSCFG_SRAM2WRP_PAGE13 LL_SYSCFG_SRAM2WRP_PAGE13
#define | SYSCFG_SRAM2WRP_PAGE14 LL_SYSCFG_SRAM2WRP_PAGE14
#define | SYSCFG_SRAM2WRP_PAGE15 LL_SYSCFG_SRAM2WRP_PAGE15
#define | SYSCFG_SRAM2WRP_PAGE16 LL_SYSCFG_SRAM2WRP_PAGE16
#define | SYSCFG_SRAM2WRP_PAGE17 LL_SYSCFG_SRAM2WRP_PAGE17
#define | SYSCFG_SRAM2WRP_PAGE18 LL_SYSCFG_SRAM2WRP_PAGE18
#define | SYSCFG_SRAM2WRP_PAGE19 LL_SYSCFG_SRAM2WRP_PAGE19
#define | SYSCFG_SRAM2WRP_PAGE20 LL_SYSCFG_SRAM2WRP_PAGE20
#define | SYSCFG_SRAM2WRP_PAGE21 LL_SYSCFG_SRAM2WRP_PAGE21
#define | SYSCFG_SRAM2WRP_PAGE22 LL_SYSCFG_SRAM2WRP_PAGE22
#define | SYSCFG_SRAM2WRP_PAGE23 LL_SYSCFG_SRAM2WRP_PAGE23
#define | SYSCFG_SRAM2WRP_PAGE24 LL_SYSCFG_SRAM2WRP_PAGE24
#define | SYSCFG_SRAM2WRP_PAGE25 LL_SYSCFG_SRAM2WRP_PAGE25
#define | SYSCFG_SRAM2WRP_PAGE26 LL_SYSCFG_SRAM2WRP_PAGE26
#define | SYSCFG_SRAM2WRP_PAGE27 LL_SYSCFG_SRAM2WRP_PAGE27
#define | SYSCFG_SRAM2WRP_PAGE28 LL_SYSCFG_SRAM2WRP_PAGE28
#define | SYSCFG_SRAM2WRP_PAGE29 LL_SYSCFG_SRAM2WRP_PAGE29
#define | SYSCFG_SRAM2WRP_PAGE30 LL_SYSCFG_SRAM2WRP_PAGE30
#define | SYSCFG_SRAM2WRP_PAGE31 LL_SYSCFG_SRAM2WRP_PAGE31

Define Documentation

#define SYSCFG_SRAM2WRP_PAGE0 LL_SYSCFG_SRAM2WRP_PAGE0

SRAM2A Write protection page 0

Definition at line 92 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE1 LL_SYSCFG_SRAM2WRP_PAGE1

SRAM2A Write protection page 1

Definition at line 93 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE10 LL_SYSCFG_SRAM2WRP_PAGE10

SRAM2A Write protection page 10

Definition at line 102 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE11 LL_SYSCFG_SRAM2WRP_PAGE11

SRAM2A Write protection page 11

Definition at line 103 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE12 LL_SYSCFG_SRAM2WRP_PAGE12

SRAM2A Write protection page 12

Definition at line 104 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE13 LL_SYSCFG_SRAM2WRP_PAGE13

SRAM2A Write protection page 13

Definition at line 105 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE14 LL_SYSCFG_SRAM2WRP_PAGE14

SRAM2A Write protection page 14

Definition at line 106 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE15 LL_SYSCFG_SRAM2WRP_PAGE15

SRAM2A Write protection page 15

Definition at line 107 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE16 LL_SYSCFG_SRAM2WRP_PAGE16

SRAM2A Write protection page 16

Definition at line 108 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE17 LL_SYSCFG_SRAM2WRP_PAGE17

SRAM2A Write protection page 17

Definition at line 109 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE18 LL_SYSCFG_SRAM2WRP_PAGE18

SRAM2A Write protection page 18

Definition at line 110 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE19 LL_SYSCFG_SRAM2WRP_PAGE19

SRAM2A Write protection page 19

Definition at line 111 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE2 LL_SYSCFG_SRAM2WRP_PAGE2

SRAM2A Write protection page 2

Definition at line 94 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE20 LL_SYSCFG_SRAM2WRP_PAGE20

SRAM2A Write protection page 20

Definition at line 112 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE21 LL_SYSCFG_SRAM2WRP_PAGE21

SRAM2A Write protection page 21

Definition at line 113 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE22 LL_SYSCFG_SRAM2WRP_PAGE22

SRAM2A Write protection page 22

Definition at line 114 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE23 LL_SYSCFG_SRAM2WRP_PAGE23

SRAM2A Write protection page 23

Definition at line 115 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE24 LL_SYSCFG_SRAM2WRP_PAGE24

SRAM2A Write protection page 24

Definition at line 116 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE25 LL_SYSCFG_SRAM2WRP_PAGE25

SRAM2A Write protection page 25

Definition at line 117 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE26 LL_SYSCFG_SRAM2WRP_PAGE26

SRAM2A Write protection page 26

Definition at line 118 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE27 LL_SYSCFG_SRAM2WRP_PAGE27

SRAM2A Write protection page 27

Definition at line 119 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE28 LL_SYSCFG_SRAM2WRP_PAGE28

SRAM2A Write protection page 28

Definition at line 120 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE29 LL_SYSCFG_SRAM2WRP_PAGE29

SRAM2A Write protection page 29

Definition at line 121 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE3 LL_SYSCFG_SRAM2WRP_PAGE3

SRAM2A Write protection page 3

Definition at line 95 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE30 LL_SYSCFG_SRAM2WRP_PAGE30

SRAM2A Write protection page 30

Definition at line 122 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE31 LL_SYSCFG_SRAM2WRP_PAGE31

SRAM2A Write protection page 31

Definition at line 123 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE4 LL_SYSCFG_SRAM2WRP_PAGE4

SRAM2A Write protection page 4

Definition at line 96 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE5 LL_SYSCFG_SRAM2WRP_PAGE5

SRAM2A Write protection page 5

Definition at line 97 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE6 LL_SYSCFG_SRAM2WRP_PAGE6

SRAM2A Write protection page 6

Definition at line 98 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE7 LL_SYSCFG_SRAM2WRP_PAGE7

SRAM2A Write protection page 7

Definition at line 99 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE8 LL_SYSCFG_SRAM2WRP_PAGE8

SRAM2A Write protection page 8

Definition at line 100 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE9 LL_SYSCFG_SRAM2WRP_PAGE9

SRAM2A Write protection page 9

Definition at line 101 of file stm32wbxx_hal.h.

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STM32WB55xx HAL User Manual: SRAM2 Page Write protection (32 to 63)

Defines
SRAM2 Page Write protection (32 to 63)
SYSCFG Exported Constants

Defines

#define | SYSCFG_SRAM2WRP_PAGE32 LL_SYSCFG_SRAM2WRP_PAGE32
#define | SYSCFG_SRAM2WRP_PAGE33 LL_SYSCFG_SRAM2WRP_PAGE33
#define | SYSCFG_SRAM2WRP_PAGE34 LL_SYSCFG_SRAM2WRP_PAGE34
#define | SYSCFG_SRAM2WRP_PAGE35 LL_SYSCFG_SRAM2WRP_PAGE35
#define | SYSCFG_SRAM2WRP_PAGE36 LL_SYSCFG_SRAM2WRP_PAGE36
#define | SYSCFG_SRAM2WRP_PAGE37 LL_SYSCFG_SRAM2WRP_PAGE37
#define | SYSCFG_SRAM2WRP_PAGE38 LL_SYSCFG_SRAM2WRP_PAGE38
#define | SYSCFG_SRAM2WRP_PAGE39 LL_SYSCFG_SRAM2WRP_PAGE39
#define | SYSCFG_SRAM2WRP_PAGE40 LL_SYSCFG_SRAM2WRP_PAGE40
#define | SYSCFG_SRAM2WRP_PAGE41 LL_SYSCFG_SRAM2WRP_PAGE41
#define | SYSCFG_SRAM2WRP_PAGE42 LL_SYSCFG_SRAM2WRP_PAGE42
#define | SYSCFG_SRAM2WRP_PAGE43 LL_SYSCFG_SRAM2WRP_PAGE43
#define | SYSCFG_SRAM2WRP_PAGE44 LL_SYSCFG_SRAM2WRP_PAGE44
#define | SYSCFG_SRAM2WRP_PAGE45 LL_SYSCFG_SRAM2WRP_PAGE45
#define | SYSCFG_SRAM2WRP_PAGE46 LL_SYSCFG_SRAM2WRP_PAGE46
#define | SYSCFG_SRAM2WRP_PAGE47 LL_SYSCFG_SRAM2WRP_PAGE47
#define | SYSCFG_SRAM2WRP_PAGE48 LL_SYSCFG_SRAM2WRP_PAGE48
#define | SYSCFG_SRAM2WRP_PAGE49 LL_SYSCFG_SRAM2WRP_PAGE49
#define | SYSCFG_SRAM2WRP_PAGE50 LL_SYSCFG_SRAM2WRP_PAGE50
#define | SYSCFG_SRAM2WRP_PAGE51 LL_SYSCFG_SRAM2WRP_PAGE51
#define | SYSCFG_SRAM2WRP_PAGE52 LL_SYSCFG_SRAM2WRP_PAGE52
#define | SYSCFG_SRAM2WRP_PAGE53 LL_SYSCFG_SRAM2WRP_PAGE53
#define | SYSCFG_SRAM2WRP_PAGE54 LL_SYSCFG_SRAM2WRP_PAGE54
#define | SYSCFG_SRAM2WRP_PAGE55 LL_SYSCFG_SRAM2WRP_PAGE55
#define | SYSCFG_SRAM2WRP_PAGE56 LL_SYSCFG_SRAM2WRP_PAGE56
#define | SYSCFG_SRAM2WRP_PAGE57 LL_SYSCFG_SRAM2WRP_PAGE57
#define | SYSCFG_SRAM2WRP_PAGE58 LL_SYSCFG_SRAM2WRP_PAGE58
#define | SYSCFG_SRAM2WRP_PAGE59 LL_SYSCFG_SRAM2WRP_PAGE59
#define | SYSCFG_SRAM2WRP_PAGE60 LL_SYSCFG_SRAM2WRP_PAGE60
#define | SYSCFG_SRAM2WRP_PAGE61 LL_SYSCFG_SRAM2WRP_PAGE61
#define | SYSCFG_SRAM2WRP_PAGE62 LL_SYSCFG_SRAM2WRP_PAGE62
#define | SYSCFG_SRAM2WRP_PAGE63 LL_SYSCFG_SRAM2WRP_PAGE63

Define Documentation

#define SYSCFG_SRAM2WRP_PAGE32 LL_SYSCFG_SRAM2WRP_PAGE32

SRAM2B Write protection page 32

Definition at line 132 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE33 LL_SYSCFG_SRAM2WRP_PAGE33

SRAM2B Write protection page 33

Definition at line 133 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE34 LL_SYSCFG_SRAM2WRP_PAGE34

SRAM2B Write protection page 34

Definition at line 134 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE35 LL_SYSCFG_SRAM2WRP_PAGE35

SRAM2B Write protection page 35

Definition at line 135 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE36 LL_SYSCFG_SRAM2WRP_PAGE36

SRAM2B Write protection page 36

Definition at line 136 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE37 LL_SYSCFG_SRAM2WRP_PAGE37

SRAM2B Write protection page 37

Definition at line 137 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE38 LL_SYSCFG_SRAM2WRP_PAGE38

SRAM2B Write protection page 38

Definition at line 138 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE39 LL_SYSCFG_SRAM2WRP_PAGE39

SRAM2B Write protection page 39

Definition at line 139 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE40 LL_SYSCFG_SRAM2WRP_PAGE40

SRAM2B Write protection page 40

Definition at line 140 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE41 LL_SYSCFG_SRAM2WRP_PAGE41

SRAM2B Write protection page 41

Definition at line 141 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE42 LL_SYSCFG_SRAM2WRP_PAGE42

SRAM2B Write protection page 42

Definition at line 142 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE43 LL_SYSCFG_SRAM2WRP_PAGE43

SRAM2B Write protection page 43

Definition at line 143 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE44 LL_SYSCFG_SRAM2WRP_PAGE44

SRAM2B Write protection page 44

Definition at line 144 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE45 LL_SYSCFG_SRAM2WRP_PAGE45

SRAM2B Write protection page 45

Definition at line 145 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE46 LL_SYSCFG_SRAM2WRP_PAGE46

SRAM2B Write protection page 46

Definition at line 146 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE47 LL_SYSCFG_SRAM2WRP_PAGE47

SRAM2B Write protection page 47

Definition at line 147 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE48 LL_SYSCFG_SRAM2WRP_PAGE48

SRAM2B Write protection page 48

Definition at line 148 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE49 LL_SYSCFG_SRAM2WRP_PAGE49

SRAM2B Write protection page 49

Definition at line 149 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE50 LL_SYSCFG_SRAM2WRP_PAGE50

SRAM2B Write protection page 50

Definition at line 150 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE51 LL_SYSCFG_SRAM2WRP_PAGE51

SRAM2B Write protection page 51

Definition at line 151 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE52 LL_SYSCFG_SRAM2WRP_PAGE52

SRAM2B Write protection page 52

Definition at line 152 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE53 LL_SYSCFG_SRAM2WRP_PAGE53

SRAM2B Write protection page 53

Definition at line 153 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE54 LL_SYSCFG_SRAM2WRP_PAGE54

SRAM2B Write protection page 54

Definition at line 154 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE55 LL_SYSCFG_SRAM2WRP_PAGE55

SRAM2B Write protection page 55

Definition at line 155 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE56 LL_SYSCFG_SRAM2WRP_PAGE56

SRAM2B Write protection page 56

Definition at line 156 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE57 LL_SYSCFG_SRAM2WRP_PAGE57

SRAM2B Write protection page 57

Definition at line 157 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE58 LL_SYSCFG_SRAM2WRP_PAGE58

SRAM2B Write protection page 58

Definition at line 158 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE59 LL_SYSCFG_SRAM2WRP_PAGE59

SRAM2B Write protection page 59

Definition at line 159 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE60 LL_SYSCFG_SRAM2WRP_PAGE60

SRAM2B Write protection page 60

Definition at line 160 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE61 LL_SYSCFG_SRAM2WRP_PAGE61

SRAM2B Write protection page 61

Definition at line 161 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE62 LL_SYSCFG_SRAM2WRP_PAGE62

SRAM2B Write protection page 62

Definition at line 162 of file stm32wbxx_hal.h.

#define SYSCFG_SRAM2WRP_PAGE63 LL_SYSCFG_SRAM2WRP_PAGE63

SRAM2B Write protection page 63

Definition at line 163 of file stm32wbxx_hal.h.

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: VREFBUF Voltage Scale

Defines
VREFBUF Voltage Scale
SYSCFG Exported Constants

Defines

#define | SYSCFG_VREFBUF_VOLTAGE_SCALE0 LL_VREFBUF_VOLTAGE_SCALE0
#define | SYSCFG_VREFBUF_VOLTAGE_SCALE1 LL_VREFBUF_VOLTAGE_SCALE1

Define Documentation

#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 LL_VREFBUF_VOLTAGE_SCALE0

Voltage reference scale 0 (VREF_OUT1)

Definition at line 173 of file stm32wbxx_hal.h.

#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 LL_VREFBUF_VOLTAGE_SCALE1

Voltage reference scale 1 (VREF_OUT2)

Definition at line 174 of file stm32wbxx_hal.h.

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: VREFBUF High Impedance

Defines
VREFBUF High Impedance
SYSCFG Exported Constants

Defines

#define | SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0x00000000U
#define | SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ

Define Documentation

#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0x00000000U

VREF_plus pin is internally connected to Voltage reference buffer output

Definition at line 183 of file stm32wbxx_hal.h.

#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ

VREF_plus pin is high impedance

Definition at line 184 of file stm32wbxx_hal.h.

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SRAM Flags

Defines
SRAM Flags
SYSCFG Exported Constants

Defines

#define | SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_SPF
#define | SYSCFG_FLAG_SRAM2_BUSY SYSCFG_SCSR_SRAM2BSY

Define Documentation

#define SYSCFG_FLAG_SRAM2_BUSY SYSCFG_SCSR_SRAM2BSY

SRAM2 busy by erase operation

Definition at line 196 of file stm32wbxx_hal.h.

#define SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_SPF

SRAM2 parity error

Definition at line 195 of file stm32wbxx_hal.h.

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Fast-mode Plus on GPIO

Defines
Fast-mode Plus on GPIO
SYSCFG Exported Constants

Defines

#define | SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP
Fast-mode Plus driving capability on a specific GPIO.
#define | SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP
#define | SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP
#define | SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP

Define Documentation

#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP

Fast-mode Plus driving capability on a specific GPIO.

Enable Fast-mode Plus on PB6

Definition at line 208 of file stm32wbxx_hal.h.

#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP

Enable Fast-mode Plus on PB7

Definition at line 209 of file stm32wbxx_hal.h.

#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP

Enable Fast-mode Plus on PB8

Definition at line 210 of file stm32wbxx_hal.h.

#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP

Enable Fast-mode Plus on PB9

Definition at line 211 of file stm32wbxx_hal.h.

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Secure IP Write Access

Defines
Secure IP Write Access
SYSCFG Exported Constants

Defines

#define | HAL_SYSCFG_SECURE_ACCESS_AES1 LL_SYSCFG_SECURE_ACCESS_AES1
#define | HAL_SYSCFG_SECURE_ACCESS_AES2 LL_SYSCFG_SECURE_ACCESS_AES2
#define | HAL_SYSCFG_SECURE_ACCESS_PKA LL_SYSCFG_SECURE_ACCESS_PKA
#define | HAL_SYSCFG_SECURE_ACCESS_RNG LL_SYSCFG_SECURE_ACCESS_RNG

Define Documentation

#define HAL_SYSCFG_SECURE_ACCESS_AES1 LL_SYSCFG_SECURE_ACCESS_AES1

Enabling the security access of Advanced Encryption Standard 1 KEY[7:0]

Definition at line 221 of file stm32wbxx_hal.h.

#define HAL_SYSCFG_SECURE_ACCESS_AES2 LL_SYSCFG_SECURE_ACCESS_AES2

Enabling the security access of Advanced Encryption Standard 2

Definition at line 223 of file stm32wbxx_hal.h.

#define HAL_SYSCFG_SECURE_ACCESS_PKA LL_SYSCFG_SECURE_ACCESS_PKA

Enabling the security access of Public Key Accelerator

Definition at line 224 of file stm32wbxx_hal.h.

#define HAL_SYSCFG_SECURE_ACCESS_RNG LL_SYSCFG_SECURE_ACCESS_RNG

Enabling the security access of Random Number Generator

Definition at line 225 of file stm32wbxx_hal.h.

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DBGMCU CPU1 APBx GRPx STOP IP

Defines
DBGMCU CPU1 APBx GRPx STOP IP
DBGMCU Exported Macros

Freeze and Unfreeze Peripherals in Debug mode. More...

Defines

#define | __HAL_DBGMCU_FREEZE_TIM2() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_TIM2_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM2() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_TIM2_STOP)
#define | __HAL_DBGMCU_FREEZE_RTC() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_RTC_STOP)
#define | __HAL_DBGMCU_UNFREEZE_RTC() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_RTC_STOP)
#define | __HAL_DBGMCU_FREEZE_WWDG() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG_STOP)
#define | __HAL_DBGMCU_UNFREEZE_WWDG() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG_STOP)
#define | __HAL_DBGMCU_FREEZE_IWDG() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP)
#define | __HAL_DBGMCU_UNFREEZE_IWDG() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP)
#define | __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_I2C1_STOP)
#define | __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_I2C1_STOP)
#define | __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_I2C3_STOP)
#define | __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_I2C3_STOP)
#define | __HAL_DBGMCU_FREEZE_LPTIM1() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP)
#define | __HAL_DBGMCU_UNFREEZE_LPTIM1() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP)
#define | __HAL_DBGMCU_FREEZE_LPTIM2() LL_DBGMCU_APB1_GRP2_FreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP)
#define | __HAL_DBGMCU_UNFREEZE_LPTIM2() LL_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM1() LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM1_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM1() LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM1_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM16() LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM16_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM16() LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM16_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM17() LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM17_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM17() LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM17_STOP)

Detailed Description

Freeze and Unfreeze Peripherals in Debug mode.

Define Documentation

#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT ( ) LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_I2C1_STOP)

Definition at line 274 of file stm32wbxx_hal.h.

#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT ( ) LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_I2C3_STOP)

Definition at line 279 of file stm32wbxx_hal.h.

#define __HAL_DBGMCU_FREEZE_IWDG ( ) LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP)

Definition at line 269 of file stm32wbxx_hal.h.

#define __HAL_DBGMCU_FREEZE_LPTIM1 ( ) LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP)

Definition at line 284 of file stm32wbxx_hal.h.

#define __HAL_DBGMCU_FREEZE_LPTIM2 ( ) LL_DBGMCU_APB1_GRP2_FreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP)

Definition at line 289 of file stm32wbxx_hal.h.

#define __HAL_DBGMCU_FREEZE_RTC ( ) LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_RTC_STOP)

Definition at line 259 of file stm32wbxx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM1 ( ) LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM1_STOP)

Definition at line 294 of file stm32wbxx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM16 ( ) LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM16_STOP)

Definition at line 299 of file stm32wbxx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM17 ( ) LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM17_STOP)

Definition at line 304 of file stm32wbxx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM2 ( ) LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_TIM2_STOP)

Definition at line 254 of file stm32wbxx_hal.h.

#define __HAL_DBGMCU_FREEZE_WWDG ( ) LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG_STOP)

Definition at line 264 of file stm32wbxx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT ( ) LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_I2C1_STOP)

Definition at line 275 of file stm32wbxx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT ( ) LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_I2C3_STOP)

Definition at line 280 of file stm32wbxx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_IWDG ( ) LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP)

Definition at line 270 of file stm32wbxx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_LPTIM1 ( ) LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP)

Definition at line 285 of file stm32wbxx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_LPTIM2 ( ) LL_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP)

Definition at line 290 of file stm32wbxx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_RTC ( ) LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_RTC_STOP)

Definition at line 260 of file stm32wbxx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM1 ( ) LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM1_STOP)

Definition at line 295 of file stm32wbxx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM16 ( ) LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM16_STOP)

Definition at line 300 of file stm32wbxx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM17 ( ) LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM17_STOP)

Definition at line 305 of file stm32wbxx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM2 ( ) LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_TIM2_STOP)

Definition at line 255 of file stm32wbxx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_WWDG ( ) LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG_STOP)

Definition at line 265 of file stm32wbxx_hal.h.

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DBGMCU CPU2 APBx GRPx STOP IP

Defines
DBGMCU CPU2 APBx GRPx STOP IP
DBGMCU Exported Macros

Defines

#define | __HAL_C2_DBGMCU_FREEZE_TIM2() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP)
#define | __HAL_C2_DBGMCU_UNFREEZE_TIM2() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP)
#define | __HAL_C2_DBGMCU_FREEZE_RTC() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP)
#define | __HAL_C2_DBGMCU_UNFREEZE_RTC() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP)
#define | __HAL_C2_DBGMCU_FREEZE_IWDG() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP)
#define | __HAL_C2_DBGMCU_UNFREEZE_IWDG() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP)
#define | __HAL_C2_DBGMCU_FREEZE_I2C1_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP)
#define | __HAL_C2_DBGMCU_UNFREEZE_I2C1_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP)
#define | __HAL_C2_DBGMCU_FREEZE_I2C3_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP)
#define | __HAL_C2_DBGMCU_UNFREEZE_I2C3_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP)
#define | __HAL_C2_DBGMCU_FREEZE_LPTIM1() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP)
#define | __HAL_C2_DBGMCU_UNFREEZE_LPTIM1() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP)
#define | __HAL_C2_DBGMCU_FREEZE_LPTIM2() LL_C2_DBGMCU_APB1_GRP2_FreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP)
#define | __HAL_C2_DBGMCU_UNFREEZE_LPTIM2() LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP)
#define | __HAL_C2_DBGMCU_FREEZE_TIM1() LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP)
#define | __HAL_C2_DBGMCU_UNFREEZE_TIM1() LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP)
#define | __HAL_C2_DBGMCU_FREEZE_TIM16() LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP)
#define | __HAL_C2_DBGMCU_UNFREEZE_TIM16() LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP)
#define | __HAL_C2_DBGMCU_FREEZE_TIM17() LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP)
#define | __HAL_C2_DBGMCU_UNFREEZE_TIM17() LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP)

Define Documentation

#define __HAL_C2_DBGMCU_FREEZE_I2C1_TIMEOUT ( ) LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP)

Definition at line 331 of file stm32wbxx_hal.h.

#define __HAL_C2_DBGMCU_FREEZE_I2C3_TIMEOUT ( ) LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP)

Definition at line 336 of file stm32wbxx_hal.h.

#define __HAL_C2_DBGMCU_FREEZE_IWDG ( ) LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP)

Definition at line 326 of file stm32wbxx_hal.h.

#define __HAL_C2_DBGMCU_FREEZE_LPTIM1 ( ) LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP)

Definition at line 341 of file stm32wbxx_hal.h.

#define __HAL_C2_DBGMCU_FREEZE_LPTIM2 ( ) LL_C2_DBGMCU_APB1_GRP2_FreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP)

Definition at line 346 of file stm32wbxx_hal.h.

#define __HAL_C2_DBGMCU_FREEZE_RTC ( ) LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP)

Definition at line 321 of file stm32wbxx_hal.h.

#define __HAL_C2_DBGMCU_FREEZE_TIM1 ( ) LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP)

Definition at line 351 of file stm32wbxx_hal.h.

#define __HAL_C2_DBGMCU_FREEZE_TIM16 ( ) LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP)

Definition at line 356 of file stm32wbxx_hal.h.

#define __HAL_C2_DBGMCU_FREEZE_TIM17 ( ) LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP)

Definition at line 361 of file stm32wbxx_hal.h.

#define __HAL_C2_DBGMCU_FREEZE_TIM2 ( ) LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP)

Definition at line 316 of file stm32wbxx_hal.h.

#define __HAL_C2_DBGMCU_UNFREEZE_I2C1_TIMEOUT ( ) LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP)

Definition at line 332 of file stm32wbxx_hal.h.

#define __HAL_C2_DBGMCU_UNFREEZE_I2C3_TIMEOUT ( ) LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP)

Definition at line 337 of file stm32wbxx_hal.h.

#define __HAL_C2_DBGMCU_UNFREEZE_IWDG ( ) LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP)

Definition at line 327 of file stm32wbxx_hal.h.

#define __HAL_C2_DBGMCU_UNFREEZE_LPTIM1 ( ) LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP)

Definition at line 342 of file stm32wbxx_hal.h.

#define __HAL_C2_DBGMCU_UNFREEZE_LPTIM2 ( ) LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP)

Definition at line 347 of file stm32wbxx_hal.h.

#define __HAL_C2_DBGMCU_UNFREEZE_RTC ( ) LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP)

Definition at line 322 of file stm32wbxx_hal.h.

#define __HAL_C2_DBGMCU_UNFREEZE_TIM1 ( ) LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP)

Definition at line 352 of file stm32wbxx_hal.h.

#define __HAL_C2_DBGMCU_UNFREEZE_TIM16 ( ) LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP)

Definition at line 357 of file stm32wbxx_hal.h.

#define __HAL_C2_DBGMCU_UNFREEZE_TIM17 ( ) LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP)

Definition at line 362 of file stm32wbxx_hal.h.

#define __HAL_C2_DBGMCU_UNFREEZE_TIM2 ( ) LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP)

Definition at line 317 of file stm32wbxx_hal.h.

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SYSCFG Exported Macros

Defines
SYSCFG Exported Macros
HAL Exported Macros

Defines

#define | __HAL_SYSCFG_REMAPMEMORY_FLASH() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_FLASH)
Main Flash memory mapped at 0x00000000.
#define | __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_SYSTEMFLASH)
System Flash memory mapped at 0x00000000.
#define | __HAL_SYSCFG_REMAPMEMORY_SRAM() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_SRAM)
Embedded SRAM mapped at 0x00000000.
#define | __HAL_SYSCFG_REMAPMEMORY_QUADSPI() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_QUADSPI)
QUADSPI mapped at 0x00000000.
#define | __HAL_SYSCFG_GET_BOOT_MODE() LL_SYSCFG_GetRemapMemory()
Return the boot mode as configured by user.
#define | __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
SRAM2 page 0 to 31 write protection enable macro.
#define | __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE(__SRAM2WRP__)
#define | __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE(__SRAM2WRP__)
SRAM2 page 32 to 63 write protection enable macro.
#define | __HAL_SYSCFG_SRAM2_WRP_UNLOCK() LL_SYSCFG_UnlockSRAM2WRP()
SRAM2 page write protection unlock prior to erase.
#define | __HAL_SYSCFG_SRAM2_ERASE() LL_SYSCFG_EnableSRAM2Erase()
SRAM2 erase.
#define | __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__)
Floating Point Unit interrupt enable/disable macros.
#define | __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__)
#define | __HAL_SYSCFG_BREAK_ECC_LOCK() LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_ECC)
SYSCFG Break ECC lock.
#define | __HAL_SYSCFG_BREAK_LOCKUP_LOCK() LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_LOCKUP)
SYSCFG Break Cortex-M4 Lockup lock.
#define | __HAL_SYSCFG_BREAK_PVD_LOCK() LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_PVD)
SYSCFG Break PVD lock.
#define | __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_SRAM2_PARITY)
SYSCFG Break SRAM2 parity lock.
#define | __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0U) ? 1U : 0U)
Check SYSCFG flag is set or not.
#define | __HAL_SYSCFG_CLEAR_FLAG() LL_SYSCFG_ClearFlag_SP()
Set the SPF bit to clear the SRAM Parity Error Flag.
#define | __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)
Fast mode Plus driving capability enable/disable macros.
#define | __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__)

Define Documentation

#define __HAL_SYSCFG_BREAK_ECC_LOCK ( ) LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_ECC)

SYSCFG Break ECC lock.

Enable and lock the connection of Flash ECC error connection to TIM1/16/17 Break input.

Note:
The selected configuration is locked and can be unlocked only by system reset.

Definition at line 451 of file stm32wbxx_hal.h.

#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK ( ) LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_LOCKUP)

SYSCFG Break Cortex-M4 Lockup lock.

Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/16/17 Break input.

Note:
The selected configuration is locked and can be unlocked only by system reset.

Definition at line 457 of file stm32wbxx_hal.h.

#define __HAL_SYSCFG_BREAK_PVD_LOCK ( ) LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_PVD)

SYSCFG Break PVD lock.

Enable and lock the PVD connection to Timer1/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register.

Note:
The selected configuration is locked and can be unlocked only by system reset.

Definition at line 463 of file stm32wbxx_hal.h.

#define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK ( ) LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_SRAM2_PARITY)

SYSCFG Break SRAM2 parity lock.

Enable and lock the SRAM2 parity error signal connection to TIM1/16/17 Break input.

Note:
The selected configuration is locked and can be unlocked by system reset.

Definition at line 469 of file stm32wbxx_hal.h.

#define __HAL_SYSCFG_CLEAR_FLAG ( ) LL_SYSCFG_ClearFlag_SP()

Set the SPF bit to clear the SRAM Parity Error Flag.

Definition at line 482 of file stm32wbxx_hal.h.

#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE ( __FASTMODEPLUS__ )
Value:
do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \
                                                                LL_SYSCFG_DisableFastModePlus(__FASTMODEPLUS__);          \
                                                               }while(0)

Definition at line 491 of file stm32wbxx_hal.h.

#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE ( __FASTMODEPLUS__ )
Value:
do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \
                                                                LL_SYSCFG_EnableFastModePlus(__FASTMODEPLUS__);           \
                                                               }while(0)

Fast mode Plus driving capability enable/disable macros.

Parameters:
__FASTMODEPLUS__ This parameter can be a value of Fast-mode Plus on GPIO

Definition at line 487 of file stm32wbxx_hal.h.

#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE ( __INTERRUPT__ )
Value:
do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
                                                                CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
                                                            }while(0)

Definition at line 443 of file stm32wbxx_hal.h.

#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE ( __INTERRUPT__ )
Value:
do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
                                                                SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
                                                            }while(0)

Floating Point Unit interrupt enable/disable macros.

Parameters:
__INTERRUPT__ This parameter can be a value of FPU Interrupts

Definition at line 439 of file stm32wbxx_hal.h.

#define __HAL_SYSCFG_GET_BOOT_MODE ( ) LL_SYSCFG_GetRemapMemory()

Return the boot mode as configured by user.

Return values:
The boot mode as configured by user. The returned value can be one of the following values:
  • SYSCFG_BOOT_MAINFLASH
  • SYSCFG_BOOT_SYSTEMFLASH
  • SYSCFG_BOOT_SRAM #if defined(LL_SYSCFG_REMAP_QUADSPI)
  • SYSCFG_BOOT_QUADSPI #endif

Definition at line 406 of file stm32wbxx_hal.h.

#define __HAL_SYSCFG_GET_FLAG ( __FLAG__ ) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0U) ? 1U : 0U)

Check SYSCFG flag is set or not.

Parameters:
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • SYSCFG_FLAG_SRAM2_PE SRAM2 Parity Error Flag
  • SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 478 of file stm32wbxx_hal.h.

#define __HAL_SYSCFG_REMAPMEMORY_FLASH ( ) LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_FLASH)

Main Flash memory mapped at 0x00000000.

Definition at line 379 of file stm32wbxx_hal.h.

#define __HAL_SYSCFG_REMAPMEMORY_QUADSPI ( ) LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_QUADSPI)

QUADSPI mapped at 0x00000000.

Definition at line 392 of file stm32wbxx_hal.h.

#define __HAL_SYSCFG_REMAPMEMORY_SRAM ( ) LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_SRAM)

Embedded SRAM mapped at 0x00000000.

Definition at line 387 of file stm32wbxx_hal.h.

#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH ( ) LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_SYSTEMFLASH)

System Flash memory mapped at 0x00000000.

Definition at line 383 of file stm32wbxx_hal.h.

#define __HAL_SYSCFG_SRAM2_ERASE ( ) LL_SYSCFG_EnableSRAM2Erase()

SRAM2 erase.

Note:
__SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM2_BUSY) may be used to check end of erase

Definition at line 434 of file stm32wbxx_hal.h.

Referenced by HAL_SYSCFG_SRAM2Erase().

#define __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE ( __SRAM2WRP__ )
Value:
do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\
                                                                LL_SYSCFG_EnableSRAM2PageWRP_0_31(__SRAM2WRP__);\
                                                            }while(0)

Definition at line 414 of file stm32wbxx_hal.h.

#define __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE

SRAM2 page 0 to 31 write protection enable macro.

Parameters:
__SRAM2WRP__ This parameter can be a combination of values of SRAM2 Page Write protection (0 to 31)
Note:
Write protection can only be disabled by a system reset

Definition at line 413 of file stm32wbxx_hal.h.

#define __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE ( __SRAM2WRP__ )
Value:
do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\
                                                                LL_SYSCFG_EnableSRAM2PageWRP_32_63(__SRAM2WRP__);\
                                                            }while(0)

SRAM2 page 32 to 63 write protection enable macro.

Parameters:
__SRAM2WRP__ This parameter can be a combination of values of SRAM2 Page Write protection (32 to 63)
Note:
Write protection can only be disabled by a system reset

Definition at line 422 of file stm32wbxx_hal.h.

#define __HAL_SYSCFG_SRAM2_WRP_UNLOCK ( ) LL_SYSCFG_UnlockSRAM2WRP()

SRAM2 page write protection unlock prior to erase.

Note:
Writing a wrong key reactivates the write protection

Definition at line 429 of file stm32wbxx_hal.h.

Referenced by HAL_SYSCFG_SRAM2Erase().

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SYSCFG Private Macros

Defines
SYSCFG Private Macros
HAL Private Macros

Defines

#define | IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__)
#define | IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFU))
#define | IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)
#define | IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__)
#define | IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
#define | IS_SYSCFG_FASTMODEPLUS(__PIN__)
#define | IS_SYSCFG_SECURITY_ACCESS(__VALUE__)

Define Documentation

#define IS_SYSCFG_FASTMODEPLUS ( __PIN__ )
Value:
((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6)  == SYSCFG_FASTMODEPLUS_PB6)  || \
                                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7)  == SYSCFG_FASTMODEPLUS_PB7)  || \
                                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8)  == SYSCFG_FASTMODEPLUS_PB8)  || \
                                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9)  == SYSCFG_FASTMODEPLUS_PB9))

Definition at line 531 of file stm32wbxx_hal.h.

#define IS_SYSCFG_FPU_INTERRUPT ( __INTERRUPT__ )
Value:
((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \
                                                         (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \
                                                         (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \
                                                         (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \
                                                         (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \
                                                         (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC))

Definition at line 512 of file stm32wbxx_hal.h.

#define IS_SYSCFG_SECURITY_ACCESS ( __VALUE__ )
Value:
((((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_AES1)  == HAL_SYSCFG_SECURE_ACCESS_AES1)  || \
                                                         (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_AES2)  == HAL_SYSCFG_SECURE_ACCESS_AES2)  || \
                                                         (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_PKA)   == HAL_SYSCFG_SECURE_ACCESS_PKA)   || \
                                                         (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_RNG)   == HAL_SYSCFG_SECURE_ACCESS_RNG))

Definition at line 537 of file stm32wbxx_hal.h.

Referenced by HAL_SYSCFG_DisableSecurityAccess(), and HAL_SYSCFG_EnableSecurityAccess().

#define IS_SYSCFG_SRAM2WRP_PAGE ( __PAGE__ ) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFU))

Definition at line 519 of file stm32wbxx_hal.h.

#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE ( __VALUE__ )
Value:
(((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
                                                         ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))

Definition at line 525 of file stm32wbxx_hal.h.

Referenced by HAL_SYSCFG_VREFBUF_HighImpedanceConfig().

#define IS_SYSCFG_VREFBUF_TRIMMING ( __VALUE__ ) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))

Definition at line 528 of file stm32wbxx_hal.h.

Referenced by HAL_SYSCFG_VREFBUF_TrimmingConfig().

#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE ( __SCALE__ )
Value:
(((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
                                                         ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1))

Definition at line 522 of file stm32wbxx_hal.h.

Referenced by HAL_SYSCFG_VREFBUF_VoltageScalingConfig().

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: HAL Private Macros

Modules | Defines
HAL Private Macros
HAL

Modules

SYSCFG Private Macros

Defines

#define IS_TICKFREQ(FREQ)

Define Documentation

#define IS_TICKFREQ ( FREQ )
Value:
(((FREQ) == HAL_TICK_FREQ_10HZ)  || \
                           ((FREQ) == HAL_TICK_FREQ_100HZ) || \
                           ((FREQ) == HAL_TICK_FREQ_1KHZ))

Definition at line 558 of file stm32wbxx_hal.h.

Referenced by HAL_SetTickFreq().

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: HAL System Configuration functions

Functions
HAL System Configuration functions
HAL Exported Functions

HAL System Configuration functions. More...

Functions

void | HAL_SYSCFG_SRAM2Erase (void)
Start a hardware SRAM2 erase operation.
void | HAL_SYSCFG_DisableSRAMFetch (void)
Disable CPU2 SRAM fetch (execution) (This bit can be set by Firmware and will only be reset by a Hardware reset, including a reset after Standby.)
uint32_t | HAL_SYSCFG_IsEnabledSRAMFetch (void)
Check if CPU2 SRAM fetch is enabled.
void | HAL_SYSCFG_VREFBUF_VoltageScalingConfig (uint32_t VoltageScaling)
Configure the internal voltage reference buffer voltage scale.
void | HAL_SYSCFG_VREFBUF_HighImpedanceConfig (uint32_t Mode)
Configure the internal voltage reference buffer high impedance mode.
void | HAL_SYSCFG_VREFBUF_TrimmingConfig (uint32_t TrimmingValue)
Tune the Internal Voltage Reference buffer (VREFBUF).
HAL_StatusTypeDef | HAL_SYSCFG_EnableVREFBUF (void)
Enable the Internal Voltage Reference buffer (VREFBUF).
void | HAL_SYSCFG_DisableVREFBUF (void)
Disable the Internal Voltage Reference buffer (VREFBUF).
void | HAL_SYSCFG_EnableIOBooster (void)
Enable the I/O analog switch voltage booster.
void | HAL_SYSCFG_DisableIOBooster (void)
Disable the I/O analog switch voltage booster.
void | HAL_SYSCFG_EnableIOVdd (void)
Enable the I/O analog switch supplied by VDD.
void | HAL_SYSCFG_DisableIOVdd (void)
Disable the I/O analog switch supplied by VDD.
void | HAL_SYSCFG_EnableSecurityAccess (uint32_t SecurityAccess)
Enable the access for security IP.
void | HAL_SYSCFG_DisableSecurityAccess (uint32_t SecurityAccess)
Disable the access for security IP.
uint32_t | HAL_SYSCFG_IsEnabledSecurityAccess (uint32_t SecurityAccess)
Indicate if access for security IP is enabled.

Detailed Description

HAL System Configuration functions.

 ===============================================================================
                 ##### HAL system configuration functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Start a hardware SRAM2 erase operation
      (+) Disable CPU2 SRAM fetch (execution)
      (+) Configure the Voltage reference buffer
      (+) Enable/Disable the Voltage reference buffer
      (+) Enable/Disable the I/O analog switch voltage booster
      (+) Enable/Disable the access for security IP (AES1, AES2, PKA, RNG)
      (+) Enable/Disable the access for security IP (AES2, PKA, RNG)

Function Documentation

void HAL_SYSCFG_DisableIOBooster ( void )

Disable the I/O analog switch voltage booster.

Return values:
None

Definition at line 722 of file stm32wbxx_hal.c.

References LL_SYSCFG_DisableAnalogBooster().

void HAL_SYSCFG_DisableIOVdd ( void )

Disable the I/O analog switch supplied by VDD.

Return values:
None

Definition at line 742 of file stm32wbxx_hal.c.

References LL_SYSCFG_DisableAnalogGpioSwitch().

void HAL_SYSCFG_DisableSecurityAccess ( uint32_t SecurityAccess )

Disable the access for security IP.

Note:
When the system is secure (ESE = 1), this register provides write access security and can only be written by the CPU2. A write access from the CPU1 will be ignored and a bus error is generated.
Parameters:
SecurityAccess This parameter can be a combination of the following values:
  • HAL_SYSCFG_SECURE_ACCESS_AES1
  • HAL_SYSCFG_SECURE_ACCESS_AES2
  • HAL_SYSCFG_SECURE_ACCESS_PKA
  • HAL_SYSCFG_SECURE_ACCESS_RNG
Return values:
None

Definition at line 779 of file stm32wbxx_hal.c.

References assert_param, IS_SYSCFG_SECURITY_ACCESS, and LL_SYSCFG_DisableSecurityAccess().

void HAL_SYSCFG_DisableSRAMFetch ( void )

Disable CPU2 SRAM fetch (execution) (This bit can be set by Firmware and will only be reset by a Hardware reset, including a reset after Standby.)

Note:
Firmware writing 0 has no effect.
Return values:
None

Definition at line 606 of file stm32wbxx_hal.c.

References LL_SYSCFG_DisableSRAMFetch().

void HAL_SYSCFG_DisableVREFBUF ( void )

Disable the Internal Voltage Reference buffer (VREFBUF).

Return values:
None

Definition at line 701 of file stm32wbxx_hal.c.

References LL_VREFBUF_Disable().

void HAL_SYSCFG_EnableIOBooster ( void )

Enable the I/O analog switch voltage booster.

Return values:
None

Definition at line 712 of file stm32wbxx_hal.c.

References LL_SYSCFG_EnableAnalogBooster().

void HAL_SYSCFG_EnableIOVdd ( void )

Enable the I/O analog switch supplied by VDD.

Note:
To be used when I/O analog switch voltage booster is not enabled
Return values:
None

Definition at line 732 of file stm32wbxx_hal.c.

References LL_SYSCFG_EnableAnalogGpioSwitch().

void HAL_SYSCFG_EnableSecurityAccess ( uint32_t SecurityAccess )

Enable the access for security IP.

Note:
When the system is secure (ESE = 1), this register provides write access security and can only be written by the CPU2. A write access from the CPU1 will be ignored and a bus error is generated.
Parameters:
SecurityAccess This parameter can be a combination of the following values:
  • HAL_SYSCFG_SECURE_ACCESS_AES1
  • HAL_SYSCFG_SECURE_ACCESS_AES2
  • HAL_SYSCFG_SECURE_ACCESS_PKA
  • HAL_SYSCFG_SECURE_ACCESS_RNG
Return values:
None

Definition at line 759 of file stm32wbxx_hal.c.

References assert_param, IS_SYSCFG_SECURITY_ACCESS, and LL_SYSCFG_EnableSecurityAccess().

HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF ( void )

Enable the Internal Voltage Reference buffer (VREFBUF).

Return values:
HAL_OK/HAL_TIMEOUT

Definition at line 675 of file stm32wbxx_hal.c.

References HAL_GetTick(), LL_VREFBUF_Enable(), and VREFBUF_TIMEOUT_VALUE.

uint32_t HAL_SYSCFG_IsEnabledSecurityAccess ( uint32_t SecurityAccess )

Indicate if access for security IP is enabled.

Parameters:
SecurityAccess This parameter can be one of the following values:
  • HAL_SYSCFG_SECURE_ACCESS_AES1
  • HAL_SYSCFG_SECURE_ACCESS_AES2
  • HAL_SYSCFG_SECURE_ACCESS_PKA
  • HAL_SYSCFG_SECURE_ACCESS_RNG
Return values:
State of bit (1 or 0).

Definition at line 796 of file stm32wbxx_hal.c.

References LL_SYSCFG_IsEnabledSecurityAccess().

uint32_t HAL_SYSCFG_IsEnabledSRAMFetch ( void )

Check if CPU2 SRAM fetch is enabled.

Return values:
State of bit (1 or 0).

Definition at line 615 of file stm32wbxx_hal.c.

References LL_SYSCFG_IsEnabledSRAMFetch().

void HAL_SYSCFG_SRAM2Erase ( void )

Start a hardware SRAM2 erase operation.

Note:
As long as SRAM2 is not erased the SRAM2ER bit will be set. This bit is automatically reset at the end of the SRAM2 erase operation.
Return values:
None

Definition at line 592 of file stm32wbxx_hal.c.

References __HAL_SYSCFG_SRAM2_ERASE, and __HAL_SYSCFG_SRAM2_WRP_UNLOCK.

void HAL_SYSCFG_VREFBUF_HighImpedanceConfig ( uint32_t Mode )

Configure the internal voltage reference buffer high impedance mode.

Parameters:
Mode specifies the high impedance mode This parameter can be one of the following values:
  • SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE : VREF+ pin is internally connect to VREFINT output.
  • SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE : VREF+ pin is high impedance.
Return values:
HAL_OK/HAL_TIMEOUT

Definition at line 647 of file stm32wbxx_hal.c.

References assert_param, and IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE.

void HAL_SYSCFG_VREFBUF_TrimmingConfig ( uint32_t TrimmingValue )

Tune the Internal Voltage Reference buffer (VREFBUF).

Parameters:
TrimmingValue specifies trimming code for VREFBUF calibration This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x3F
Return values:
None

Definition at line 662 of file stm32wbxx_hal.c.

References assert_param, IS_SYSCFG_VREFBUF_TRIMMING, and LL_VREFBUF_SetTrimming().

void HAL_SYSCFG_VREFBUF_VoltageScalingConfig ( uint32_t VoltageScaling )

Configure the internal voltage reference buffer voltage scale.

Parameters:
VoltageScaling specifies the output voltage to achieve This parameter can be one of the following values:
  • SYSCFG_VREFBUF_VOLTAGE_SCALE0 : VREF_OUT1 around 2.048 V. This requires VDDA equal to or higher than 2.4 V.
  • SYSCFG_VREFBUF_VOLTAGE_SCALE1 : VREF_OUT1 around 2.5 V. This requires VDDA equal to or higher than 2.8 V.
Return values:
None

Definition at line 631 of file stm32wbxx_hal.c.

References assert_param, IS_SYSCFG_VREFBUF_VOLTAGE_SCALE, and LL_VREFBUF_SetVoltageScaling().

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: HAL Initialization and Configuration functions

Functions
HAL Initialization and Configuration functions
HAL Exported Functions

HAL Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_Init (void)
This function is used to initialize the HAL Library; it must be the first instruction to be executed in the main program (before to call any other HAL function), it performs the following: Configure the Flash prefetch, instruction and Data caches.
HAL_StatusTypeDef | HAL_DeInit (void)
This function de-Initializes common part of the HAL and stops the source of time base.
__weak void | HAL_MspInit (void)
Initialize the MSP.
__weak void | HAL_MspDeInit (void)
DeInitializes the MSP.
__weak HAL_StatusTypeDef | HAL_InitTick (uint32_t TickPriority)
This function configures the source of the time base: The time source is configured to have 1ms time base with a dedicated Tick interrupt priority.

Detailed Description

HAL Initialization and Configuration functions.

 ===============================================================================
           ##### HAL Initialization and Configuration functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the Flash interface the NVIC allocation and initial time base
          clock configuration.
      (+) De-initialize common part of the HAL.
      (+) Configure the time base source to have 1ms time base with a dedicated
          Tick interrupt priority.
        (++) SysTick timer is used by default as source of time base, but user
             can eventually implement his proper time base source (a general purpose
             timer for example or other time source), keeping in mind that Time base
             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
             handled in milliseconds basis.
        (++) Time base configuration function (HAL_InitTick ()) is called automatically
             at the beginning of the program after reset by HAL_Init() or at any time
             when clock is configured, by HAL_RCC_ClockConfig().
        (++) Source of time base is configured  to generate interrupts at regular
             time intervals. Care must be taken if HAL_Delay() is called from a
             peripheral ISR process, the Tick interrupt line must have higher priority
            (numerically lower) than the peripheral interrupt. Otherwise the caller
            ISR process will be blocked.
       (++) functions affecting time base configurations are declared as __weak
             to make  override possible  in case of other  implementations in user file.

Function Documentation

HAL_StatusTypeDef HAL_DeInit ( void )

This function de-Initializes common part of the HAL and stops the source of time base.

Note:
This function is optional.
Return values:
HAL status

Definition at line 186 of file stm32wbxx_hal.c.

References __HAL_RCC_AHB1_FORCE_RESET, __HAL_RCC_AHB1_RELEASE_RESET, __HAL_RCC_AHB2_FORCE_RESET, __HAL_RCC_AHB2_RELEASE_RESET, __HAL_RCC_AHB3_FORCE_RESET, __HAL_RCC_AHB3_RELEASE_RESET, __HAL_RCC_APB1_FORCE_RESET, __HAL_RCC_APB1_RELEASE_RESET, __HAL_RCC_APB2_FORCE_RESET, __HAL_RCC_APB2_RELEASE_RESET, __HAL_RCC_APB3_FORCE_RESET, __HAL_RCC_APB3_RELEASE_RESET, and HAL_MspDeInit().

HAL_StatusTypeDef HAL_Init ( void )

This function is used to initialize the HAL Library; it must be the first instruction to be executed in the main program (before to call any other HAL function), it performs the following: Configure the Flash prefetch, instruction and Data caches.

Configures the SysTick to generate an interrupt each 1 millisecond, which is clocked by the MSI (at this stage, the clock is not yet configured and thus the system is running from the internal MSI at 4 MHz). Set NVIC Group Priority to 4. Calls the HAL_MspInit() callback function defined in user file "stm32wbxx_hal_msp.c" to do the global low level hardware initialization

Note:
SysTick is used as time base for the HAL_Delay() function, the application need to ensure that the SysTick time base is always set to 1 millisecond to have correct HAL operation.
Return values:
HAL status

Definition at line 143 of file stm32wbxx_hal.c.

References __HAL_FLASH_DATA_CACHE_DISABLE, __HAL_FLASH_INSTRUCTION_CACHE_DISABLE, __HAL_FLASH_PREFETCH_BUFFER_ENABLE, HAL_InitTick(), HAL_MspInit(), HAL_NVIC_SetPriorityGrouping(), NVIC_PRIORITYGROUP_4, and TICK_INT_PRIORITY.

HAL_StatusTypeDef HAL_InitTick ( uint32_t TickPriority )

This function configures the source of the time base: The time source is configured to have 1ms time base with a dedicated Tick interrupt priority.

Note:
This function is called automatically at the beginning of program after reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
In the default implementation, SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals. Care must be taken if HAL_Delay() is called from a peripheral ISR process, The SysTick interrupt must have higher priority (numerically lower) than the peripheral interrupt. Otherwise the caller ISR process will be blocked. The function is declared as __weak to be overwritten in case of other implementation in user file.
Parameters:
TickPriority Tick interrupt priority.
Return values:
HAL status

Definition at line 252 of file stm32wbxx_hal.c.

References HAL_NVIC_SetPriority(), HAL_RCC_GetHCLKFreq(), HAL_SYSTICK_Config(), uwTickFreq, and uwTickPrio.

Referenced by HAL_Init(), HAL_RCC_ClockConfig(), HAL_RCC_DeInit(), HAL_RCC_OscConfig(), and HAL_SetTickFreq().

void HAL_MspDeInit ( void )

DeInitializes the MSP.

Return values:
None

Definition at line 229 of file stm32wbxx_hal.c.

Referenced by HAL_DeInit().

void HAL_MspInit ( void )

Initialize the MSP.

Return values:
None

Definition at line 218 of file stm32wbxx_hal.c.

Referenced by HAL_Init().

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: HAL Control functions

Functions
HAL Control functions
HAL Exported Functions

HAL Control functions. More...

Functions

__weak void | HAL_IncTick (void)
This function is called to increment a global variable "uwTick" used as application time base.
__weak uint32_t | HAL_GetTick (void)
Provides a tick value in millisecond.
uint32_t | HAL_GetTickPrio (void)
This function returns a tick priority.
HAL_StatusTypeDef | HAL_SetTickFreq (uint32_t Freq)
Set new tick Freq.
uint32_t | HAL_GetTickFreq (void)
Return tick frequency.
__weak void | HAL_Delay (uint32_t Delay)
This function provides minimum delay (in milliseconds) based on variable incremented.
__weak void | HAL_SuspendTick (void)
Suspend Tick increment.
__weak void | HAL_ResumeTick (void)
Resume Tick increment.
uint32_t | HAL_GetHalVersion (void)
Returns the HAL revision.
uint32_t | HAL_GetREVID (void)
Returns the device revision identifier.
uint32_t | HAL_GetDEVID (void)
Returns the device identifier.
uint32_t | HAL_GetUIDw0 (void)
Return the first word of the unique device identifier (UID based on 96 bits)
uint32_t | HAL_GetUIDw1 (void)
Return the second word of the unique device identifier (UID based on 96 bits)
uint32_t | HAL_GetUIDw2 (void)
Return the third word of the unique device identifier (UID based on 96 bits)

Detailed Description

HAL Control functions.

 ===============================================================================
                      ##### HAL Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Provide a tick value in millisecond
      (+) Provide a blocking delay in millisecond
      (+) Suspend the time base source interrupt
      (+) Resume the time base source interrupt
      (+) Get the HAL API driver version
      (+) Get the device revision identifier
      (+) Get the device identifier
      (+) Get the unique device identifier

Function Documentation

void HAL_Delay ( uint32_t Delay )

This function provides minimum delay (in milliseconds) based on variable incremented.

Note:
In the default implementation , SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals where uwTick is incremented.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Parameters:
Delay specifies the delay time length, in milliseconds.
Return values:
None

Definition at line 385 of file stm32wbxx_hal.c.

References HAL_GetTick(), and uwTickFreq.

Referenced by HAL_PCDEx_BCD_VBUSDetect().

uint32_t HAL_GetDEVID ( void )

Returns the device identifier.

Return values:
Device identifier

Definition at line 456 of file stm32wbxx_hal.c.

References LL_DBGMCU_GetDeviceID().

uint32_t HAL_GetHalVersion ( void )

Returns the HAL revision.

Return values:
version : 0xXYZR (8bits for each decimal, R for RC)

Definition at line 438 of file stm32wbxx_hal.c.

References __STM32WBxx_HAL_VERSION.

uint32_t HAL_GetREVID ( void )

Returns the device revision identifier.

Return values:
Device revision identifier

Definition at line 447 of file stm32wbxx_hal.c.

References LL_DBGMCU_GetRevisionID().

uint32_t HAL_GetTick ( void )

Provides a tick value in millisecond.

Note:
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
tick value

Definition at line 331 of file stm32wbxx_hal.c.

References uwTick.

Referenced by ADC_ConversionStop(), ADC_Disable(), ADC_Enable(), CRYP_AESCCM_Process(), CRYP_AESGCM_Process(), CRYP_WaitOnCCFlag(), FLASH_WaitForLastOperation(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADCEx_InjectedPollForConversion(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), HAL_CRYPEx_AESGCM_GenerateAuthTAG(), HAL_Delay(), HAL_DMA_PollForTransfer(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), HAL_IRDA_Receive(), HAL_IRDA_Transmit(), HAL_IWDG_Init(), HAL_LCD_Clear(), HAL_LCD_Init(), HAL_LCD_UpdateDisplayRequest(), HAL_LCD_Write(), HAL_PCDEx_BCD_VBUSDetect(), HAL_QSPI_Abort(), HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_Init(), HAL_QSPI_MemoryMapped(), HAL_QSPI_Receive(), HAL_QSPI_Transmit(), HAL_RCC_ClockConfig(), HAL_RCC_DeInit(), HAL_RCC_OscConfig(), HAL_RCCEx_CRSWaitSynchronization(), HAL_RCCEx_DisablePLLSAI1(), HAL_RCCEx_EnablePLLSAI1(), HAL_RCCEx_PeriphCLKConfig(), HAL_RNG_GenerateRandomNumber(), HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_PollForAlarmAEvent(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_WaitForSynchro(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_PollForAlarmBEvent(), HAL_RTCEx_PollForTamper1Event(), HAL_RTCEx_PollForTamper2Event(), HAL_RTCEx_PollForTamper3Event(), HAL_RTCEx_PollForTimeStampEvent(), HAL_RTCEx_PollForWakeUpTimerEvent(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), HAL_SAI_Receive(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Transmit(), HAL_SMBUS_IsDeviceReady(), HAL_SPI_Abort(), HAL_SPI_Receive(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), HAL_SYSCFG_EnableVREFBUF(), HAL_UART_Receive(), HAL_UART_Transmit(), HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_USART_Receive(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), I2C_IsAcknowledgeFailed(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), IRDA_CheckIdleState(), IRDA_WaitOnFlagUntilTimeout(), LCD_WaitForSynchro(), PKA_PollEndOfOperation(), PKA_Process(), QSPI_WaitFlagStateUntilTimeout(), RCC_SetFlashLatency(), RCCEx_PLLSAI1_ConfigNP(), RCCEx_PLLSAI1_ConfigNQ(), RCCEx_PLLSAI1_ConfigNR(), RTC_EnterInitMode(), SMARTCARD_CheckIdleState(), SMARTCARD_WaitOnFlagUntilTimeout(), SMBUS_WaitOnFlagUntilTimeout(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_WaitFifoStateUntilTimeout(), SPI_WaitFlagStateUntilTimeout(), UART_CheckIdleState(), UART_WaitOnFlagUntilTimeout(), USART_CheckIdleState(), and USART_WaitOnFlagUntilTimeout().

uint32_t HAL_GetTickFreq ( void )

Return tick frequency.

Return values:
tick period in Hz

Definition at line 369 of file stm32wbxx_hal.c.

References uwTickFreq.

uint32_t HAL_GetTickPrio ( void )

This function returns a tick priority.

Return values:
tick priority

Definition at line 340 of file stm32wbxx_hal.c.

References uwTickPrio.

Referenced by HAL_RCC_ClockConfig().

uint32_t HAL_GetUIDw0 ( void )

Return the first word of the unique device identifier (UID based on 96 bits)

Return values:
Device identifier

Definition at line 465 of file stm32wbxx_hal.c.

uint32_t HAL_GetUIDw1 ( void )

Return the second word of the unique device identifier (UID based on 96 bits)

Return values:
Device identifier

Definition at line 474 of file stm32wbxx_hal.c.

uint32_t HAL_GetUIDw2 ( void )

Return the third word of the unique device identifier (UID based on 96 bits)

Return values:
Device identifier

Definition at line 483 of file stm32wbxx_hal.c.

void HAL_IncTick ( void )

This function is called to increment a global variable "uwTick" used as application time base.

Note:
In the default implementation, this variable is incremented each 1ms in SysTick ISR.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
None

Definition at line 320 of file stm32wbxx_hal.c.

References uwTick, and uwTickFreq.

void HAL_ResumeTick ( void )

Resume Tick increment.

Note:
In the default implementation , SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals. Once HAL_ResumeTick() is called, the SysTick interrupt will be enabled and so Tick increment is resumed.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
None

Definition at line 428 of file stm32wbxx_hal.c.

HAL_StatusTypeDef HAL_SetTickFreq ( uint32_t Freq )

Set new tick Freq.

Return values:
Status

Definition at line 349 of file stm32wbxx_hal.c.

References assert_param, HAL_InitTick(), IS_TICKFREQ, uwTickFreq, and uwTickPrio.

void HAL_SuspendTick ( void )

Suspend Tick increment.

Note:
In the default implementation , SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals. Once HAL_SuspendTick() is called, the SysTick interrupt will be disabled and so Tick increment is suspended.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
None

Definition at line 412 of file stm32wbxx_hal.c.

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: HAL Debug functions

Functions
HAL Debug functions
HAL Exported Functions

HAL Debug functions. More...

Functions

void | HAL_DBGMCU_EnableDBGSleepMode (void)
Enable the Debug Module during SLEEP mode.
void | HAL_DBGMCU_DisableDBGSleepMode (void)
Disable the Debug Module during SLEEP mode.
void | HAL_DBGMCU_EnableDBGStopMode (void)
Enable the Debug Module during STOP mode.
void | HAL_DBGMCU_DisableDBGStopMode (void)
Disable the Debug Module during STOP mode.
void | HAL_DBGMCU_EnableDBGStandbyMode (void)
Enable the Debug Module during STANDBY mode.
void | HAL_DBGMCU_DisableDBGStandbyMode (void)
Disable the Debug Module during STANDBY mode.

Detailed Description

HAL Debug functions.

 ===============================================================================
                      ##### HAL Debug functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Enable/Disable Debug module during SLEEP mode
      (+) Enable/Disable Debug module during STOP mode
      (+) Enable/Disable Debug module during STANDBY mode

Function Documentation

void HAL_DBGMCU_DisableDBGSleepMode ( void )

Disable the Debug Module during SLEEP mode.

Return values:
None

Definition at line 521 of file stm32wbxx_hal.c.

References LL_DBGMCU_DisableDBGSleepMode().

void HAL_DBGMCU_DisableDBGStandbyMode ( void )

Disable the Debug Module during STANDBY mode.

Return values:
None

Definition at line 557 of file stm32wbxx_hal.c.

References LL_DBGMCU_DisableDBGStandbyMode().

void HAL_DBGMCU_DisableDBGStopMode ( void )

Disable the Debug Module during STOP mode.

Return values:
None

Definition at line 539 of file stm32wbxx_hal.c.

References LL_DBGMCU_DisableDBGStopMode().

void HAL_DBGMCU_EnableDBGSleepMode ( void )

Enable the Debug Module during SLEEP mode.

Return values:
None

Definition at line 512 of file stm32wbxx_hal.c.

References LL_DBGMCU_EnableDBGSleepMode().

void HAL_DBGMCU_EnableDBGStandbyMode ( void )

Enable the Debug Module during STANDBY mode.

Return values:
None

Definition at line 548 of file stm32wbxx_hal.c.

References LL_DBGMCU_EnableDBGStandbyMode().

void HAL_DBGMCU_EnableDBGStopMode ( void )

Enable the Debug Module during STOP mode.

Return values:
None

Definition at line 530 of file stm32wbxx_hal.c.

References LL_DBGMCU_EnableDBGStopMode().

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC Private Constants

Defines
ADC Private Constants
ADC

Defines

#define | ADC_CFGR_FIELDS_1
#define | ADC_ENABLE_TIMEOUT (2UL)
#define | ADC_DISABLE_TIMEOUT (2UL)
#define | ADC_CONVERSION_TIME_MAX_CPU_CYCLES (653UL * 4096UL * 256UL)
#define | ADC_STOP_CONVERSION_TIMEOUT ( 5UL)
#define | ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US)

Define Documentation

#define ADC_CFGR_FIELDS_1
Value:
((ADC_CFGR_RES    | ADC_CFGR_ALIGN   |\
                             ADC_CFGR_CONT   | ADC_CFGR_OVRMOD  |\
                             ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\
                             ADC_CFGR_EXTEN  | ADC_CFGR_EXTSEL))

ADC_CFGR fields of parameters that can be updated when no regular conversion is on-going

Definition at line 321 of file stm32wbxx_hal_adc.c.

Referenced by HAL_ADC_Init().

#define ADC_CONVERSION_TIME_MAX_CPU_CYCLES (653UL * 4096UL * 256UL)

ADC conversion completion time-out value

Definition at line 342 of file stm32wbxx_hal_adc.c.

Referenced by ADC_ConversionStop().

#define ADC_DISABLE_TIMEOUT (2UL)

ADC disable time-out value

Definition at line 332 of file stm32wbxx_hal_adc.c.

Referenced by ADC_Disable().

#define ADC_ENABLE_TIMEOUT (2UL)

ADC enable time-out value

Definition at line 331 of file stm32wbxx_hal_adc.c.

Referenced by ADC_Enable().

#define ADC_STOP_CONVERSION_TIMEOUT ( 5UL)

ADC stop time-out value

Definition at line 946 of file stm32wbxx_hal_adc.h.

Referenced by ADC_ConversionStop().

#define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US)

Definition at line 951 of file stm32wbxx_hal_adc.h.

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
ADC Exported Functions

ADC Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_ADC_Init (ADC_HandleTypeDef *hadc)
Initialize the ADC peripheral and regular group according to parameters specified in structure "ADC_InitTypeDef".
HAL_StatusTypeDef | HAL_ADC_DeInit (ADC_HandleTypeDef *hadc)
Deinitialize the ADC peripheral registers to their default reset values, with deinitialization of the ADC MSP.
__weak void | HAL_ADC_MspInit (ADC_HandleTypeDef *hadc)
Initialize the ADC MSP.
__weak void | HAL_ADC_MspDeInit (ADC_HandleTypeDef *hadc)
DeInitialize the ADC MSP.
HAL_StatusTypeDef | HAL_ADC_RegisterCallback (ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
Register a User ADC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_ADC_UnRegisterCallback (ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
Unregister a ADC Callback ADC callback is redirected to the weak predefined callback.

Detailed Description

ADC Initialization and Configuration functions.

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the ADC.
      (+) De-initialize the ADC.

Function Documentation

HAL_StatusTypeDef HAL_ADC_DeInit ( ADC_HandleTypeDef * hadc )

Deinitialize the ADC peripheral registers to their default reset values, with deinitialization of the ADC MSP.

Note:
For devices with several ADCs: reset of ADC common registers is done only if all ADCs sharing the same common group are disabled. (function "HAL_ADC_MspDeInit()" is also called under the same conditions: all ADC instances use the same core clock at RCC level, disabling the core clock reset all ADC instances). If this is not the case, reset of these common parameters reset is bypassed without error reporting: it can be the intended behavior in case of reset of a single ADC while the other ADCs sharing the same common group is still running.
By default, HAL_ADC_DeInit() set ADC in mode deep power-down: this saves more power by reducing leakage currents and is particularly interesting before entering MCU low-power modes.
Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 696 of file stm32wbxx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_DISABLE_IT, __LL_ADC_COMMON_INSTANCE, __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE, ADC_CFGR_FIELDS, ADC_CLEAR_COMMON_CONTROL_REGISTER, ADC_CLEAR_ERRORCODE, ADC_ConversionStop(), ADC_Disable(), ADC_FLAG_AWD1, ADC_FLAG_AWD2, ADC_FLAG_AWD3, ADC_FLAG_EOC, ADC_FLAG_EOS, ADC_FLAG_EOSMP, ADC_FLAG_JEOC, ADC_FLAG_JEOS, ADC_FLAG_JQOVF, ADC_FLAG_OVR, ADC_FLAG_RDY, ADC_IT_AWD1, ADC_IT_AWD2, ADC_IT_AWD3, ADC_IT_EOC, ADC_IT_EOS, ADC_IT_EOSMP, ADC_IT_JEOC, ADC_IT_JEOS, ADC_IT_JQOVF, ADC_IT_OVR, ADC_IT_RDY, ADC_REGULAR_INJECTED_GROUP, ADC_SMPR1_FIELDS, assert_param, ADC_InjectionConfigTypeDef::ChannelCount, ADC_InjectionConfigTypeDef::ContextQueue, HAL_ADC_MspDeInit(), HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY, HAL_ADC_STATE_RESET, __ADC_HandleTypeDef::InjectionConfig, __ADC_HandleTypeDef::Instance, __ADC_HandleTypeDef::MspDeInitCallback, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Init ( ADC_HandleTypeDef * hadc )

Initialize the ADC peripheral and regular group according to parameters specified in structure "ADC_InitTypeDef".

Note:
As prerequisite, ADC clock must be configured at RCC top level (refer to description of RCC configuration for ADC in header of this file).
Possibility to update parameters on the fly: This function initializes the ADC MSP (HAL_ADC_MspInit()) only when coming from ADC state reset. Following calls to this function can be used to reconfigure some parameters of ADC_InitTypeDef structure on the fly, without modifying MSP configuration. If ADC MSP has to be modified again, HAL_ADC_DeInit() must be called before HAL_ADC_Init(). The setting of these parameters is conditioned to ADC state. For parameters constraints, see comments of structure "ADC_InitTypeDef".
This function configures the ADC within 2 scopes: scope of entire ADC and scope of regular group. For parameters details, see comments of structure "ADC_InitTypeDef".
Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 394 of file stm32wbxx_hal_adc.c.

References __LL_ADC_COMMON_INSTANCE, __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE, ADC_CFGR_AUTOWAIT, ADC_CFGR_CONTINUOUS, ADC_CFGR_DFSDM, ADC_CFGR_DISCONTINUOUS_NUM, ADC_CFGR_DMACONTREQ, ADC_CFGR_FIELDS_1, ADC_CFGR_FIELDS_2, ADC_CFGR_REG_DISCONTINUOUS, ADC_CLEAR_ERRORCODE, ADC_SCAN_DISABLE, ADC_SCAN_ENABLE, ADC_SOFTWARE_START, ADC_STATE_CLR_SET, assert_param, ADC_InitTypeDef::ClockPrescaler, ADC_InitTypeDef::ContinuousConvMode, __ADC_HandleTypeDef::ConvCpltCallback, __ADC_HandleTypeDef::ConvHalfCpltCallback, ADC_InitTypeDef::DataAlign, ADC_InitTypeDef::DiscontinuousConvMode, ADC_InitTypeDef::DMAContinuousRequests, __ADC_HandleTypeDef::EndOfSamplingCallback, ADC_InitTypeDef::EOCSelection, __ADC_HandleTypeDef::ErrorCallback, __ADC_HandleTypeDef::ErrorCode, ADC_InitTypeDef::ExternalTrigConv, ADC_InitTypeDef::ExternalTrigConvEdge, HAL_ADC_ConvCpltCallback(), HAL_ADC_ConvHalfCpltCallback(), HAL_ADC_ERROR_INTERNAL, HAL_ADC_ErrorCallback(), HAL_ADC_LevelOutOfWindowCallback(), HAL_ADC_MspInit(), HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_RESET, HAL_ADCEx_EndOfSamplingCallback(), HAL_ADCEx_InjectedConvCpltCallback(), HAL_ADCEx_InjectedQueueOverflowCallback(), HAL_ADCEx_LevelOutOfWindow2Callback(), HAL_ADCEx_LevelOutOfWindow3Callback(), __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::InjectedConvCpltCallback, __ADC_HandleTypeDef::InjectedQueueOverflowCallback, __ADC_HandleTypeDef::Instance, IS_ADC_CLOCKPRESCALER, IS_ADC_DATA_ALIGN, IS_ADC_EOC_SELECTION, IS_ADC_EXTTRIG, IS_ADC_EXTTRIG_EDGE, IS_ADC_OVERRUN, IS_ADC_OVERSAMPLING_RATIO, IS_ADC_REGOVERSAMPLING_MODE, IS_ADC_REGULAR_DISCONT_NUMBER, IS_ADC_REGULAR_NB_CONV, IS_ADC_RESOLUTION, IS_ADC_RIGHT_BIT_SHIFT, IS_ADC_SCAN_MODE, IS_ADC_TRIGGERED_OVERSAMPLING_MODE, __ADC_HandleTypeDef::LevelOutOfWindow2Callback, __ADC_HandleTypeDef::LevelOutOfWindow3Callback, __ADC_HandleTypeDef::LevelOutOfWindowCallback, LL_ADC_DELAY_INTERNAL_REGUL_STAB_US, LL_ADC_DisableDeepPowerDown(), LL_ADC_EnableInternalRegulator(), LL_ADC_INJ_IsConversionOngoing(), LL_ADC_IsDeepPowerDownEnabled(), LL_ADC_IsEnabled(), LL_ADC_IsInternalRegulatorEnabled(), LL_ADC_REG_IsConversionOngoing(), LL_ADC_SetCommonClock(), __ADC_HandleTypeDef::Lock, ADC_InitTypeDef::LowPowerAutoWait, __ADC_HandleTypeDef::MspInitCallback, ADC_InitTypeDef::NbrOfConversion, ADC_InitTypeDef::NbrOfDiscConversion, ADC_InitTypeDef::Overrun, ADC_InitTypeDef::Oversampling, ADC_InitTypeDef::OversamplingMode, ADC_OversamplingTypeDef::OversamplingStopReset, ADC_OversamplingTypeDef::Ratio, ADC_InitTypeDef::Resolution, ADC_OversamplingTypeDef::RightBitShift, ADC_InitTypeDef::ScanConvMode, __ADC_HandleTypeDef::State, and ADC_OversamplingTypeDef::TriggeredMode.

void HAL_ADC_MspDeInit ( ADC_HandleTypeDef * hadc )

DeInitialize the ADC MSP.

Parameters:
hadc ADC handle
Note:
All ADC instances use the same core clock at RCC level, disabling the core clock reset all ADC instances).
Return values:
None

Definition at line 915 of file stm32wbxx_hal_adc.c.

Referenced by HAL_ADC_DeInit(), and HAL_ADC_UnRegisterCallback().

void HAL_ADC_MspInit ( ADC_HandleTypeDef * hadc )

Initialize the ADC MSP.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 898 of file stm32wbxx_hal_adc.c.

Referenced by HAL_ADC_Init(), and HAL_ADC_UnRegisterCallback().

HAL_StatusTypeDef HAL_ADC_RegisterCallback | ( | ADC_HandleTypeDef * | hadc,
 |  | HAL_ADC_CallbackIDTypeDef | CallbackID,
 |  | pADC_CallbackTypeDef | pCallback
 | ) |  |

Register a User ADC Callback To be used instead of the weak predefined callback.

Parameters:
hadc | Pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
  • HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
  • HAL_ADC_ERROR_CB_ID ADC error callback ID
  • HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
  • HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID
  • HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID
  • HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
  • HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
  • HAL_ADC_MSPINIT_CB_ID MspInit callback ID
  • HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 949 of file stm32wbxx_hal_adc.c.

References __ADC_HandleTypeDef::ConvCpltCallback, __ADC_HandleTypeDef::ConvHalfCpltCallback, __ADC_HandleTypeDef::EndOfSamplingCallback, __ADC_HandleTypeDef::ErrorCallback, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_CONVERSION_COMPLETE_CB_ID, HAL_ADC_CONVERSION_HALF_CB_ID, HAL_ADC_END_OF_SAMPLING_CB_ID, HAL_ADC_ERROR_CB_ID, HAL_ADC_ERROR_INVALID_CALLBACK, HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID, HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID, HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID, HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID, HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID, HAL_ADC_MSPDEINIT_CB_ID, HAL_ADC_MSPINIT_CB_ID, HAL_ADC_STATE_READY, HAL_ADC_STATE_RESET, __ADC_HandleTypeDef::InjectedConvCpltCallback, __ADC_HandleTypeDef::InjectedQueueOverflowCallback, __ADC_HandleTypeDef::LevelOutOfWindow2Callback, __ADC_HandleTypeDef::LevelOutOfWindow3Callback, __ADC_HandleTypeDef::LevelOutOfWindowCallback, __ADC_HandleTypeDef::MspDeInitCallback, __ADC_HandleTypeDef::MspInitCallback, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_UnRegisterCallback | ( | ADC_HandleTypeDef * | hadc,
 |  | HAL_ADC_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a ADC Callback ADC callback is redirected to the weak predefined callback.

Parameters:
hadc Pointer to a ADC_HandleTypeDef structure that contains the configuration information for the specified ADC.
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
  • HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
  • HAL_ADC_ERROR_CB_ID ADC error callback ID
  • HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
  • HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID
  • HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID
  • HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
  • HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
  • HAL_ADC_MSPINIT_CB_ID MspInit callback ID
  • HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
HAL status

Definition at line 1073 of file stm32wbxx_hal_adc.c.

References __ADC_HandleTypeDef::ConvCpltCallback, __ADC_HandleTypeDef::ConvHalfCpltCallback, __ADC_HandleTypeDef::EndOfSamplingCallback, __ADC_HandleTypeDef::ErrorCallback, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ConvCpltCallback(), HAL_ADC_CONVERSION_COMPLETE_CB_ID, HAL_ADC_CONVERSION_HALF_CB_ID, HAL_ADC_ConvHalfCpltCallback(), HAL_ADC_END_OF_SAMPLING_CB_ID, HAL_ADC_ERROR_CB_ID, HAL_ADC_ERROR_INVALID_CALLBACK, HAL_ADC_ErrorCallback(), HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID, HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID, HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID, HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID, HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID, HAL_ADC_LevelOutOfWindowCallback(), HAL_ADC_MspDeInit(), HAL_ADC_MSPDEINIT_CB_ID, HAL_ADC_MspInit(), HAL_ADC_MSPINIT_CB_ID, HAL_ADC_STATE_READY, HAL_ADC_STATE_RESET, HAL_ADCEx_EndOfSamplingCallback(), HAL_ADCEx_InjectedConvCpltCallback(), HAL_ADCEx_InjectedQueueOverflowCallback(), HAL_ADCEx_LevelOutOfWindow2Callback(), HAL_ADCEx_LevelOutOfWindow3Callback(), __ADC_HandleTypeDef::InjectedConvCpltCallback, __ADC_HandleTypeDef::InjectedQueueOverflowCallback, __ADC_HandleTypeDef::LevelOutOfWindow2Callback, __ADC_HandleTypeDef::LevelOutOfWindow3Callback, __ADC_HandleTypeDef::LevelOutOfWindowCallback, __ADC_HandleTypeDef::MspDeInitCallback, __ADC_HandleTypeDef::MspInitCallback, and __ADC_HandleTypeDef::State.

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC Input and Output operation functions

Functions
ADC Input and Output operation functions
ADC Exported Functions

ADC IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_ADC_Start (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of regular group.
HAL_StatusTypeDef | HAL_ADC_Stop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_PollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for regular group conversion to be completed.
HAL_StatusTypeDef | HAL_ADC_PollForEvent (ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
Poll for ADC event.
HAL_StatusTypeDef | HAL_ADC_Start_IT (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of regular group with interruption.
HAL_StatusTypeDef | HAL_ADC_Stop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable interrution of end-of-conversion, disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_Start_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enable ADC, start conversion of regular group and transfer result through DMA.
HAL_StatusTypeDef | HAL_ADC_Stop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral.
uint32_t | HAL_ADC_GetValue (ADC_HandleTypeDef *hadc)
Get ADC regular group conversion result.
void | HAL_ADC_IRQHandler (ADC_HandleTypeDef *hadc)
Handle ADC interrupt request.
__weak void | HAL_ADC_ConvCpltCallback (ADC_HandleTypeDef *hadc)
Conversion complete callback in non-blocking mode.
__weak void | HAL_ADC_ConvHalfCpltCallback (ADC_HandleTypeDef *hadc)
Conversion DMA half-transfer callback in non-blocking mode.
__weak void | HAL_ADC_LevelOutOfWindowCallback (ADC_HandleTypeDef *hadc)
Analog watchdog 1 callback in non-blocking mode.
__weak void | HAL_ADC_ErrorCallback (ADC_HandleTypeDef *hadc)
ADC error callback in non-blocking mode (ADC conversion with interruption or transfer by DMA).

Detailed Description

ADC IO operation functions.

IO operation functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Start conversion of regular group.
      (+) Stop conversion of regular group.
      (+) Poll for conversion complete on regular group.
      (+) Poll for conversion event.
      (+) Get result of regular channel conversion.
      (+) Start conversion of regular group and enable interruptions.
      (+) Stop conversion of regular group and disable interruptions.
      (+) Handle ADC interrupt request
      (+) Start conversion of regular group and enable DMA transfer.
      (+) Stop conversion of regular group and disable ADC DMA transfer.

Function Documentation

void HAL_ADC_ConvCpltCallback ( ADC_HandleTypeDef * hadc )

Conversion complete callback in non-blocking mode.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 2260 of file stm32wbxx_hal_adc.c.

Referenced by ADC_DMAConvCplt(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), and HAL_ADC_UnRegisterCallback().

void HAL_ADC_ConvHalfCpltCallback ( ADC_HandleTypeDef * hadc )

Conversion DMA half-transfer callback in non-blocking mode.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 2275 of file stm32wbxx_hal_adc.c.

Referenced by ADC_DMAHalfConvCplt(), HAL_ADC_Init(), and HAL_ADC_UnRegisterCallback().

void HAL_ADC_ErrorCallback ( ADC_HandleTypeDef * hadc )

ADC error callback in non-blocking mode (ADC conversion with interruption or transfer by DMA).

Note:
In case of error due to overrun when using ADC with DMA transfer (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
  • Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
  • If needed, restart a new ADC conversion using function "HAL_ADC_Start_DMA()" (this function is also clearing overrun flag)
Parameters:
hadc ADC handle
Return values:
None

Definition at line 2312 of file stm32wbxx_hal_adc.c.

Referenced by ADC_DMAConvCplt(), ADC_DMAError(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), and HAL_ADC_UnRegisterCallback().

uint32_t HAL_ADC_GetValue ( ADC_HandleTypeDef * hadc )

Get ADC regular group conversion result.

Note:
Reading register DR automatically clears ADC flag EOC (ADC group regular end of unitary conversion).
This function does not clear ADC flag EOS (ADC group regular end of sequence conversion). Occurrence of flag EOS rising:
  • If sequencer is composed of 1 rank, flag EOS is equivalent to flag EOC.
  • If sequencer is composed of several ranks, during the scan sequence flag EOC only is raised, at the end of the scan sequence both flags EOC and EOS are raised. To clear this flag, either use function: in programming model IT: HAL_ADC_IRQHandler(), in programming model polling: HAL_ADC_PollForConversion() or __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
Parameters:
hadc ADC handle
Return values:
ADC group regular conversion data

Definition at line 1934 of file stm32wbxx_hal_adc.c.

References assert_param, and __ADC_HandleTypeDef::Instance.

void HAL_ADC_IRQHandler ( ADC_HandleTypeDef * hadc )

Handle ADC interrupt request.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 1951 of file stm32wbxx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_DISABLE_IT, __HAL_ADC_GET_FLAG, ADC_FLAG_AWD1, ADC_FLAG_AWD2, ADC_FLAG_AWD3, ADC_FLAG_EOC, ADC_FLAG_EOS, ADC_FLAG_EOSMP, ADC_FLAG_JEOC, ADC_FLAG_JEOS, ADC_FLAG_JQOVF, ADC_FLAG_OVR, ADC_IT_AWD1, ADC_IT_AWD2, ADC_IT_AWD3, ADC_IT_EOC, ADC_IT_EOS, ADC_IT_EOSMP, ADC_IT_JEOC, ADC_IT_JEOS, ADC_IT_JQOVF, ADC_IT_OVR, ADC_OVR_DATA_PRESERVED, assert_param, __ADC_HandleTypeDef::ConvCpltCallback, __ADC_HandleTypeDef::EndOfSamplingCallback, ADC_InitTypeDef::EOCSelection, __ADC_HandleTypeDef::ErrorCallback, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ConvCpltCallback(), HAL_ADC_ERROR_INTERNAL, HAL_ADC_ERROR_JQOVF, HAL_ADC_ERROR_OVR, HAL_ADC_ErrorCallback(), HAL_ADC_LevelOutOfWindowCallback(), HAL_ADC_STATE_AWD1, HAL_ADC_STATE_AWD2, HAL_ADC_STATE_AWD3, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_JQOVF, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_OVR, HAL_ADCEx_EndOfSamplingCallback(), HAL_ADCEx_InjectedConvCpltCallback(), HAL_ADCEx_InjectedQueueOverflowCallback(), HAL_ADCEx_LevelOutOfWindow2Callback(), HAL_ADCEx_LevelOutOfWindow3Callback(), __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::InjectedConvCpltCallback, __ADC_HandleTypeDef::InjectedQueueOverflowCallback, __ADC_HandleTypeDef::Instance, IS_ADC_EOC_SELECTION, __ADC_HandleTypeDef::LevelOutOfWindow2Callback, __ADC_HandleTypeDef::LevelOutOfWindow3Callback, __ADC_HandleTypeDef::LevelOutOfWindowCallback, LL_ADC_INJ_IsConversionOngoing(), LL_ADC_INJ_IsTriggerSourceSWStart(), LL_ADC_REG_DMA_TRANSFER_NONE, LL_ADC_REG_GetDMATransfer(), LL_ADC_REG_IsConversionOngoing(), LL_ADC_REG_IsTriggerSourceSWStart(), ADC_InitTypeDef::Overrun, and __ADC_HandleTypeDef::State.

void HAL_ADC_LevelOutOfWindowCallback ( ADC_HandleTypeDef * hadc )

Analog watchdog 1 callback in non-blocking mode.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 2290 of file stm32wbxx_hal_adc.c.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), and HAL_ADC_UnRegisterCallback().

HAL_StatusTypeDef HAL_ADC_PollForConversion | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | Timeout
 | ) |  |

Wait for regular group conversion to be completed.

Note:
ADC conversion flags EOS (end of sequence) and EOC (end of conversion) are cleared by this function, with an exception: if low power feature "LowPowerAutoWait" is enabled, flags are not cleared to not interfere with this feature until data register is read using function HAL_ADC_GetValue().
This function cannot be used in a particular setup: ADC configured in DMA mode and polling for end of each conversion (ADC init parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). In this case, DMA resets the flag EOC and polling cannot be performed on each conversion. Nevertheless, polling can still be performed on the complete sequence (ADC init parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
Parameters:
hadc | ADC handle
Timeout | Timeout value in millisecond.
Return values:
HAL status

Definition at line 1334 of file stm32wbxx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_GET_FLAG, ADC_EOC_SEQ_CONV, ADC_FLAG_EOC, ADC_FLAG_EOS, assert_param, ADC_InitTypeDef::ContinuousConvMode, ADC_InitTypeDef::EOCSelection, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_TIMEOUT, HAL_GetTick(), __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, LL_ADC_REG_IsTriggerSourceSWStart(), and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_PollForEvent | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | EventType,
 |  | uint32_t | Timeout
 | ) |  |

Poll for ADC event.

Parameters:
hadc | ADC handle
EventType the ADC event type. This parameter can be one of the following values:
  • ADC_EOSMP_EVENT ADC End of Sampling event
  • ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
  • ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families)
  • ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families)
  • ADC_OVR_EVENT ADC Overrun event
  • ADC_JQOVF_EVENT ADC Injected context queue overflow event
Timeout | Timeout value in millisecond.
Note:
The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR. Indeed, the latter is reset only if hadc->Init.Overrun field is set to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten by a new converted data as soon as OVR is cleared. To reset OVR flag once the preserved data is retrieved, the user can resort to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
Return values:
HAL status

Definition at line 1453 of file stm32wbxx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_GET_FLAG, ADC_AWD2_EVENT, ADC_AWD3_EVENT, ADC_AWD_EVENT, ADC_EOSMP_EVENT, ADC_FLAG_AWD1, ADC_FLAG_AWD2, ADC_FLAG_AWD3, ADC_FLAG_EOSMP, ADC_FLAG_JQOVF, ADC_FLAG_OVR, ADC_JQOVF_EVENT, ADC_OVR_DATA_PRESERVED, assert_param, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_JQOVF, HAL_ADC_ERROR_OVR, HAL_ADC_STATE_AWD1, HAL_ADC_STATE_AWD2, HAL_ADC_STATE_AWD3, HAL_ADC_STATE_INJ_JQOVF, HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_OVR, HAL_ADC_STATE_TIMEOUT, HAL_GetTick(), __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, IS_ADC_EVENT_TYPE, ADC_InitTypeDef::Overrun, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Start ( ADC_HandleTypeDef * hadc )

Enable ADC, start conversion of regular group.

Note:
Interruptions enabled in this function: None.
Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 1201 of file stm32wbxx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, ADC_CLEAR_ERRORCODE, ADC_Enable(), ADC_FLAG_EOC, ADC_FLAG_EOS, ADC_FLAG_OVR, ADC_STATE_CLR_SET, assert_param, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_DMA, HAL_ADC_ERROR_OVR, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_OVR, __ADC_HandleTypeDef::Instance, LL_ADC_REG_IsConversionOngoing(), LL_ADC_REG_StartConversion(), and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Start_DMA | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t * | pData,
 |  | uint32_t | Length
 | ) |  |

Enable ADC, start conversion of regular group and transfer result through DMA.

Note:
Interruptions enabled in this function: overrun (if applicable), DMA half transfer, DMA transfer complete. Each of these interruptions has its dedicated callback function.
Parameters:
hadc | ADC handle
pData | Destination Buffer address.
Length | Number of data to be transferred from ADC peripheral to memory
Return values:
HAL status.

Definition at line 1745 of file stm32wbxx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_ENABLE_IT, ADC_CLEAR_ERRORCODE, ADC_DMAConvCplt(), ADC_DMAError(), ADC_DMAHalfConvCplt(), ADC_Enable(), ADC_FLAG_EOC, ADC_FLAG_EOS, ADC_FLAG_OVR, ADC_IT_OVR, ADC_STATE_CLR_SET, assert_param, __ADC_HandleTypeDef::DMA_Handle, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_DMA, HAL_ADC_ERROR_OVR, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_OVR, HAL_DMA_Start_IT(), __ADC_HandleTypeDef::Instance, LL_ADC_REG_IsConversionOngoing(), LL_ADC_REG_StartConversion(), __ADC_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_ADC_Start_IT ( ADC_HandleTypeDef * hadc )

Enable ADC, start conversion of regular group with interruption.

Note:
Interruptions enabled in this function according to initialization setting : EOC (end of conversion), EOS (end of sequence), OVR overrun. Each of these interruptions has its dedicated callback function.
To guarantee a proper reset of all interruptions once all the needed conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure a correct stop of the IT-based conversions.
By default, HAL_ADC_Start_IT() does not enable the End Of Sampling interruption. If required (e.g. in case of oversampling with trigger mode), the user must: 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP) 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP) before calling HAL_ADC_Start_IT().
Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 1593 of file stm32wbxx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_DISABLE_IT, __HAL_ADC_ENABLE_IT, ADC_CLEAR_ERRORCODE, ADC_Enable(), ADC_EOC_SEQ_CONV, ADC_FLAG_EOC, ADC_FLAG_EOS, ADC_FLAG_OVR, ADC_IT_EOC, ADC_IT_EOS, ADC_IT_OVR, ADC_OVR_DATA_PRESERVED, ADC_STATE_CLR_SET, assert_param, ADC_InitTypeDef::EOCSelection, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_DMA, HAL_ADC_ERROR_OVR, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_OVR, __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, LL_ADC_REG_IsConversionOngoing(), LL_ADC_REG_StartConversion(), ADC_InitTypeDef::Overrun, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Stop ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral.

Note:
: ADC peripheral disable is forcing stop of potential conversion on injected group. If injected group is under use, it should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 1280 of file stm32wbxx_hal_adc.c.

References ADC_ConversionStop(), ADC_Disable(), ADC_REGULAR_INJECTED_GROUP, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, __ADC_HandleTypeDef::Instance, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Stop_DMA ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral.

Note:
: ADC peripheral disable is forcing stop of potential conversion on ADC group injected. If ADC group injected is under use, it should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 1849 of file stm32wbxx_hal_adc.c.

References __HAL_ADC_DISABLE_IT, ADC_ConversionStop(), ADC_Disable(), ADC_IT_OVR, ADC_REGULAR_INJECTED_GROUP, ADC_STATE_CLR_SET, assert_param, __ADC_HandleTypeDef::DMA_Handle, HAL_ADC_STATE_ERROR_DMA, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_DMA_Abort(), HAL_DMA_STATE_BUSY, __ADC_HandleTypeDef::Instance, __DMA_HandleTypeDef::State, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Stop_IT ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable interrution of end-of-conversion, disable ADC peripheral.

Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 1695 of file stm32wbxx_hal_adc.c.

References __HAL_ADC_DISABLE_IT, ADC_ConversionStop(), ADC_Disable(), ADC_IT_EOC, ADC_IT_EOS, ADC_IT_OVR, ADC_REGULAR_INJECTED_GROUP, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, __ADC_HandleTypeDef::Instance, and __ADC_HandleTypeDef::State.

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
ADC Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_ADC_ConfigChannel (ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
Configure a channel to be assigned to ADC group regular.
HAL_StatusTypeDef | HAL_ADC_AnalogWDGConfig (ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
Configure the analog watchdog.

Detailed Description

Peripheral Control functions.

 ===============================================================================
             ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure channels on regular group
      (+) Configure the analog watchdog

Function Documentation

HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig | ( | ADC_HandleTypeDef * | hadc,
 |  | ADC_AnalogWDGConfTypeDef * | AnalogWDGConfig
 | ) |  |

Configure the analog watchdog.

Note:
Possibility to update parameters on the fly: This function initializes the selected analog watchdog, successive calls to this function can be used to reconfigure some parameters of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting the ADC. The setting of these parameters is conditioned to ADC state. For parameters constraints, see comments of structure "ADC_AnalogWDGConfTypeDef".
On this STM32 serie, analog watchdog thresholds cannot be modified while ADC conversion is on going.
Parameters:
hadc | ADC handle
AnalogWDGConfig | Structure of ADC analog watchdog configuration
Return values:
HAL status

Definition at line 2573 of file stm32wbxx_hal_adc.c.

References __LL_ADC_ANALOGWD_CHANNEL_GROUP, __LL_ADC_CHANNEL_TO_DECIMAL_NB, ADC_ANALOGWATCHDOG_1, ADC_ANALOGWATCHDOG_2, ADC_ANALOGWATCHDOG_ALL_INJEC, ADC_ANALOGWATCHDOG_ALL_REG, ADC_ANALOGWATCHDOG_ALL_REGINJEC, ADC_ANALOGWATCHDOG_SINGLE_INJEC, ADC_ANALOGWATCHDOG_SINGLE_REG, ADC_ANALOGWATCHDOG_SINGLE_REGINJEC, ADC_AWD1THRESHOLD_SHIFT_RESOLUTION, ADC_AWD23THRESHOLD_SHIFT_RESOLUTION, ADC_GET_RESOLUTION, ADC_RESOLUTION_12B, assert_param, ADC_AnalogWDGConfTypeDef::Channel, HAL_ADC_STATE_AWD1, HAL_ADC_STATE_AWD2, HAL_ADC_STATE_AWD3, HAL_ADC_STATE_ERROR_CONFIG, ADC_AnalogWDGConfTypeDef::HighThreshold, __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, IS_ADC_ANALOG_WATCHDOG_MODE, IS_ADC_ANALOG_WATCHDOG_NUMBER, IS_ADC_CHANNEL, IS_ADC_RANGE, ADC_AnalogWDGConfTypeDef::ITMode, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_INJ, LL_ADC_AWD_ALL_CHANNELS_REG, LL_ADC_AWD_ALL_CHANNELS_REG_INJ, LL_ADC_AWD_DISABLE, LL_ADC_ClearFlag_AWD1(), LL_ADC_ClearFlag_AWD2(), LL_ADC_ClearFlag_AWD3(), LL_ADC_ConfigAnalogWDThresholds(), LL_ADC_DisableIT_AWD1(), LL_ADC_DisableIT_AWD2(), LL_ADC_DisableIT_AWD3(), LL_ADC_EnableIT_AWD1(), LL_ADC_EnableIT_AWD2(), LL_ADC_EnableIT_AWD3(), LL_ADC_GROUP_INJECTED, LL_ADC_GROUP_REGULAR, LL_ADC_GROUP_REGULAR_INJECTED, LL_ADC_INJ_IsConversionOngoing(), LL_ADC_REG_IsConversionOngoing(), LL_ADC_SetAnalogWDMonitChannels(), ADC_AnalogWDGConfTypeDef::LowThreshold, ADC_InitTypeDef::OversamplingMode, __ADC_HandleTypeDef::State, ADC_AnalogWDGConfTypeDef::WatchdogMode, and ADC_AnalogWDGConfTypeDef::WatchdogNumber.

HAL_StatusTypeDef HAL_ADC_ConfigChannel | ( | ADC_HandleTypeDef * | hadc,
 |  | ADC_ChannelConfTypeDef * | sConfig
 | ) |  |

Configure a channel to be assigned to ADC group regular.

Note:
In case of usage of internal measurement channels: Vbat/VrefInt/TempSensor. These internal paths can be disabled using function HAL_ADC_DeInit().
Possibility to update parameters on the fly: This function initializes channel into ADC group regular, following calls to this function can be used to reconfigure some parameters of structure "ADC_ChannelConfTypeDef" on the fly, without resetting the ADC. The setting of these parameters is conditioned to ADC state: Refer to comments of structure "ADC_ChannelConfTypeDef".
Parameters:
hadc | ADC handle
sConfig | Structure of ADC channel assigned to ADC group regular.
Return values:
HAL status

Definition at line 2358 of file stm32wbxx_hal_adc.c.

References __LL_ADC_CHANNEL_TO_DECIMAL_NB, __LL_ADC_COMMON_INSTANCE, __LL_ADC_DECIMAL_NB_TO_CHANNEL, __LL_ADC_IS_CHANNEL_INTERNAL, __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE, ADC_BATTERY_VOLTAGE_INSTANCE, ADC_CHANNEL_TEMPSENSOR, ADC_CHANNEL_VBAT, ADC_CHANNEL_VREFINT, ADC_DIFFERENTIAL_ENDED, ADC_GET_RESOLUTION, ADC_OFFSET_NONE, ADC_OFFSET_SHIFT_RESOLUTION, ADC_TEMPERATURE_SENSOR_INSTANCE, ADC_VREFINT_INSTANCE, assert_param, ADC_ChannelConfTypeDef::Channel, HAL_ADC_STATE_ERROR_CONFIG, __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, IS_ADC_CHANNEL, IS_ADC_DIFF_CHANNEL, IS_ADC_OFFSET_NUMBER, IS_ADC_RANGE, IS_ADC_REGULAR_RANK, IS_ADC_SAMPLE_TIME, IS_ADC_SINGLE_DIFFERENTIAL, LL_ADC_DELAY_TEMPSENSOR_STAB_US, LL_ADC_GetCommonPathInternalCh(), LL_ADC_GetOffsetChannel(), LL_ADC_INJ_IsConversionOngoing(), LL_ADC_IsEnabled(), LL_ADC_OFFSET_1, LL_ADC_OFFSET_2, LL_ADC_OFFSET_3, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE, LL_ADC_PATH_INTERNAL_TEMPSENSOR, LL_ADC_PATH_INTERNAL_VBAT, LL_ADC_PATH_INTERNAL_VREFINT, LL_ADC_REG_IsConversionOngoing(), LL_ADC_REG_SetSequencerRanks(), LL_ADC_SetChannelSamplingTime(), LL_ADC_SetChannelSingleDiff(), LL_ADC_SetCommonPathInternalCh(), LL_ADC_SetOffset(), LL_ADC_SetOffsetState(), ADC_ChannelConfTypeDef::Offset, ADC_ChannelConfTypeDef::OffsetNumber, ADC_InitTypeDef::OversamplingMode, ADC_ChannelConfTypeDef::Rank, ADC_ChannelConfTypeDef::SamplingTime, ADC_ChannelConfTypeDef::SingleDiff, and __ADC_HandleTypeDef::State.

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
ADC Exported Functions

ADC Peripheral State functions. More...

Functions

uint32_t | HAL_ADC_GetState (ADC_HandleTypeDef *hadc)
Return the ADC handle state.
uint32_t | HAL_ADC_GetError (ADC_HandleTypeDef *hadc)
Return the ADC error code.

Detailed Description

ADC Peripheral State functions.

 ===============================================================================
            ##### Peripheral state and errors functions #####
 ===============================================================================
    [..]
    This subsection provides functions to get in run-time the status of the
    peripheral.
      (+) Check the ADC state
      (+) Check the ADC error code

Function Documentation

uint32_t HAL_ADC_GetError ( ADC_HandleTypeDef * hadc )

Return the ADC error code.

Parameters:
hadc ADC handle
Return values:
ADC error code (bitfield on 32 bits)

Definition at line 2839 of file stm32wbxx_hal_adc.c.

References assert_param, __ADC_HandleTypeDef::ErrorCode, and __ADC_HandleTypeDef::Instance.

uint32_t HAL_ADC_GetState ( ADC_HandleTypeDef * hadc )

Return the ADC handle state.

Note:
ADC state machine is managed by bitfields, ADC status must be compared with states bits. For example: " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
Parameters:
hadc ADC handle
Return values:
ADC handle state (bitfield on 32 bits)

Definition at line 2825 of file stm32wbxx_hal_adc.c.

References assert_param, __ADC_HandleTypeDef::Instance, and __ADC_HandleTypeDef::State.

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC Private Functions

Functions
ADC Private Functions
ADC

Functions

HAL_StatusTypeDef | ADC_ConversionStop (ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
Stop ADC conversion.
HAL_StatusTypeDef | ADC_Enable (ADC_HandleTypeDef *hadc)
Enable the selected ADC.
HAL_StatusTypeDef | ADC_Disable (ADC_HandleTypeDef *hadc)
Disable the selected ADC.
void | ADC_DMAConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
void | ADC_DMAHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
void | ADC_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.

Function Documentation

HAL_StatusTypeDef ADC_ConversionStop | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | ConversionGroup
 | ) |  |

Stop ADC conversion.

Parameters:
hadc ADC handle
ConversionGroup ADC group regular and/or injected. This parameter can be one of the following values:
  • ADC_REGULAR_GROUP ADC regular conversion type.
  • ADC_INJECTED_GROUP ADC injected conversion type.
  • ADC_REGULAR_INJECTED_GROUP ADC regular and injected conversion type.
Return values:
HAL status.

Definition at line 2869 of file stm32wbxx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_GET_FLAG, ADC_CONVERSION_TIME_MAX_CPU_CYCLES, ADC_FLAG_JEOS, ADC_INJECTED_GROUP, ADC_REGULAR_GROUP, ADC_REGULAR_INJECTED_GROUP, ADC_STOP_CONVERSION_TIMEOUT, assert_param, ADC_InitTypeDef::ContinuousConvMode, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_GetTick(), __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, IS_ADC_CONVERSION_GROUP, LL_ADC_INJ_IsConversionOngoing(), LL_ADC_INJ_StopConversion(), LL_ADC_IsDisableOngoing(), LL_ADC_REG_IsConversionOngoing(), LL_ADC_REG_StopConversion(), ADC_InitTypeDef::LowPowerAutoWait, and __ADC_HandleTypeDef::State.

Referenced by HAL_ADC_DeInit(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

HAL_StatusTypeDef ADC_Disable ( ADC_HandleTypeDef * hadc )

Disable the selected ADC.

Note:
Prerequisite condition to use this function: ADC conversions must be stopped.
Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 3066 of file stm32wbxx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, ADC_DISABLE_TIMEOUT, ADC_FLAG_EOSMP, ADC_FLAG_RDY, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_GetTick(), __ADC_HandleTypeDef::Instance, LL_ADC_Disable(), LL_ADC_IsDisableOngoing(), LL_ADC_IsEnabled(), and __ADC_HandleTypeDef::State.

Referenced by HAL_ADC_DeInit(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

void ADC_DMAConvCplt ( DMA_HandleTypeDef * hdma )

DMA transfer complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 3124 of file stm32wbxx_hal_adc.c.

References ADC_FLAG_EOS, __ADC_HandleTypeDef::ConvCpltCallback, __ADC_HandleTypeDef::DMA_Handle, __ADC_HandleTypeDef::ErrorCallback, HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback(), HAL_ADC_STATE_ERROR_DMA, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, __ADC_HandleTypeDef::Instance, LL_ADC_REG_IsTriggerSourceSWStart(), __ADC_HandleTypeDef::State, and __DMA_HandleTypeDef::XferErrorCallback.

Referenced by HAL_ADC_Start_DMA().

void ADC_DMAError ( DMA_HandleTypeDef * hdma )

DMA error callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 3220 of file stm32wbxx_hal_adc.c.

References __ADC_HandleTypeDef::ErrorCallback, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_DMA, HAL_ADC_ErrorCallback(), HAL_ADC_STATE_ERROR_DMA, and __ADC_HandleTypeDef::State.

Referenced by HAL_ADC_Start_DMA().

void ADC_DMAHalfConvCplt ( DMA_HandleTypeDef * hdma )

DMA half transfer complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 3202 of file stm32wbxx_hal_adc.c.

References __ADC_HandleTypeDef::ConvHalfCpltCallback, and HAL_ADC_ConvHalfCpltCallback().

Referenced by HAL_ADC_Start_DMA().

HAL_StatusTypeDef ADC_Enable ( ADC_HandleTypeDef * hadc )

Enable the selected ADC.

Note:
Prerequisite condition to use this function: ADC must be disabled and voltage regulator must be enabled (done into HAL_ADC_Init()).
Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 2999 of file stm32wbxx_hal_adc.c.

References __HAL_ADC_GET_FLAG, ADC_ENABLE_TIMEOUT, ADC_FLAG_RDY, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_GetTick(), __ADC_HandleTypeDef::Instance, LL_ADC_Enable(), LL_ADC_IsEnabled(), and __ADC_HandleTypeDef::State.

Referenced by HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC States

Defines
ADC States
ADC Exported Types

Defines

#define | HAL_ADC_STATE_RESET (0x00000000UL)
HAL ADC state machine: ADC states definition (bitfields)
#define | HAL_ADC_STATE_READY (0x00000001UL)
#define | HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL)
#define | HAL_ADC_STATE_TIMEOUT (0x00000004UL)
#define | HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL)
#define | HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL)
#define | HAL_ADC_STATE_ERROR_DMA (0x00000040UL)
#define | HAL_ADC_STATE_REG_BUSY (0x00000100UL)
#define | HAL_ADC_STATE_REG_EOC (0x00000200UL)
#define | HAL_ADC_STATE_REG_OVR (0x00000400UL)
#define | HAL_ADC_STATE_REG_EOSMP (0x00000800UL)
#define | HAL_ADC_STATE_INJ_BUSY (0x00001000UL)
#define | HAL_ADC_STATE_INJ_EOC (0x00002000UL)
#define | HAL_ADC_STATE_INJ_JQOVF (0x00004000UL)
#define | HAL_ADC_STATE_AWD1 (0x00010000UL)
#define | HAL_ADC_STATE_AWD2 (0x00020000UL)
#define | HAL_ADC_STATE_AWD3 (0x00040000UL)
#define | HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL)

Define Documentation

#define HAL_ADC_STATE_AWD1 (0x00010000UL)

Out-of-window occurrence of ADC analog watchdog 1

Definition at line 343 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define HAL_ADC_STATE_AWD2 (0x00020000UL)

Out-of-window occurrence of ADC analog watchdog 2

Definition at line 344 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define HAL_ADC_STATE_AWD3 (0x00040000UL)

Out-of-window occurrence of ADC analog watchdog 3

Definition at line 345 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL)

ADC is busy due to an internal process (initialization, calibration)

Definition at line 321 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_Init(), and HAL_ADCEx_Calibration_Start().

#define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL)

Configuration error occurrence

Definition at line 326 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_PollForConversion(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define HAL_ADC_STATE_ERROR_DMA (0x00000040UL)

DMA error occurrence

Definition at line 327 of file stm32wbxx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_DMAError(), HAL_ADC_Stop_DMA(), and HAL_ADCEx_RegularStop_DMA().

#define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL)

Internal error occurrence

Definition at line 325 of file stm32wbxx_hal_adc.h.

Referenced by ADC_ConversionStop(), ADC_Disable(), ADC_DMAConvCplt(), ADC_Enable(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), and HAL_ADCEx_Calibration_Start().

#define HAL_ADC_STATE_INJ_BUSY (0x00001000UL)

A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode, external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available))

Definition at line 337 of file stm32wbxx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

#define HAL_ADC_STATE_INJ_EOC (0x00002000UL)

Conversion data available on group injected

Definition at line 339 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL)

Injected queue overflow occurrence

Definition at line 340 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), and HAL_ADCEx_EnableInjectedQueue().

#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL)

Not available on this STM32 serie: ADC in multimode slave state, controlled by another ADC master (when feature available)

Definition at line 348 of file stm32wbxx_hal_adc.h.

#define HAL_ADC_STATE_READY (0x00000001UL)

ADC peripheral ready for use

Definition at line 320 of file stm32wbxx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_DeInit(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_RegisterCallback(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADC_UnRegisterCallback(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

#define HAL_ADC_STATE_REG_BUSY (0x00000100UL)

A conversion on ADC group regular is ongoing or can occur (either by continuous mode, external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available))

Definition at line 330 of file stm32wbxx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

#define HAL_ADC_STATE_REG_EOC (0x00000200UL)

Conversion data available on group regular

Definition at line 332 of file stm32wbxx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL)

Not available on this STM32 serie: End Of Sampling flag raised

Definition at line 334 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

#define HAL_ADC_STATE_REG_OVR (0x00000400UL)

Overrun occurrence

Definition at line 333 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

#define HAL_ADC_STATE_RESET (0x00000000UL)

HAL ADC state machine: ADC states definition (bitfields)

Note:
ADC state machine is managed by bitfields, state must be compared with bit by bit. For example: " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " ADC not yet initialized or disabled

Definition at line 319 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_Init(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

#define HAL_ADC_STATE_TIMEOUT (0x00000004UL)

TimeOut occurrence

Definition at line 322 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), and HAL_ADCEx_InjectedPollForConversion().

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC Exported Types

Data Structures | Modules | Typedefs | Enumerations
ADC Exported Types
ADC

Data Structures

struct | ADC_OversamplingTypeDef
ADC group regular oversampling structure definition. More...
struct | ADC_InitTypeDef
Structure definition of ADC instance and ADC group regular. More...
struct | ADC_ChannelConfTypeDef
Structure definition of ADC channel for regular group. More...
struct | ADC_AnalogWDGConfTypeDef
Structure definition of ADC analog watchdog. More...
struct | ADC_InjectionConfigTypeDef
ADC group injected contexts queue configuration. More...
struct | __ADC_HandleTypeDef
ADC handle Structure definition. More...

Modules

ADC States

Typedefs

typedef struct __ADC_HandleTypeDef | ADC_HandleTypeDef
ADC handle Structure definition.
typedef void(* | pADC_CallbackTypeDef )(ADC_HandleTypeDef *hadc)
HAL ADC Callback pointer definition.

Enumerations

enum HAL_ADC_CallbackIDTypeDef {
HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, HAL_ADC_ERROR_CB_ID = 0x03U,
HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID = 0x05U, HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U,
HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, HAL_ADC_MSPINIT_CB_ID = 0x09U, HAL_ADC_MSPDEINIT_CB_ID = 0x0AU
}
HAL ADC Callback ID enumeration definition. More...

Typedef Documentation

typedef struct __ADC_HandleTypeDef ADC_HandleTypeDef

ADC handle Structure definition.

typedef void(* pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc)

HAL ADC Callback pointer definition.

pointer to a ADC callback function

Definition at line 408 of file stm32wbxx_hal_adc.h.

Enumeration Type Documentation

enum HAL_ADC_CallbackIDTypeDef

HAL ADC Callback ID enumeration definition.

Enumerator:
HAL_ADC_CONVERSION_COMPLETE_CB_ID

ADC conversion complete callback ID

HAL_ADC_CONVERSION_HALF_CB_ID

ADC conversion DMA half-transfer callback ID

HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID

ADC analog watchdog 1 callback ID

HAL_ADC_ERROR_CB_ID

ADC error callback ID

HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID

ADC group injected conversion complete callback ID

HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID

ADC group injected context queue overflow callback ID

HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID

ADC analog watchdog 2 callback ID

HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID

ADC analog watchdog 3 callback ID

HAL_ADC_END_OF_SAMPLING_CB_ID

ADC end of sampling callback ID

HAL_ADC_MSPINIT_CB_ID

ADC Msp Init callback ID

HAL_ADC_MSPDEINIT_CB_ID

ADC Msp DeInit callback ID

Definition at line 390 of file stm32wbxx_hal_adc.h.

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC_OversamplingTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_OversamplingTypeDef Struct Reference
ADC Exported Types

ADC group regular oversampling structure definition. More...

#include <stm32wbxx_hal_adc.h>

Data Fields

uint32_t | Ratio
uint32_t | RightBitShift
uint32_t | TriggeredMode
uint32_t | OversamplingStopReset

Detailed Description

ADC group regular oversampling structure definition.

Definition at line 50 of file stm32wbxx_hal_adc.h.

Field Documentation

uint32_t ADC_OversamplingTypeDef::OversamplingStopReset

Selects the regular oversampling mode. The oversampling is either temporary stopped or reset upon an injected sequence interruption. If oversampling is enabled on both regular and injected groups, this parameter is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE" (the oversampling buffer is zeroed during injection sequence). This parameter can be a value of Oversampling - Oversampling scope for ADC group regular

Definition at line 61 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_OversamplingTypeDef::Ratio

Configures the oversampling ratio. This parameter can be a value of Oversampling - Ratio

Definition at line 52 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_OversamplingTypeDef::RightBitShift

Configures the division coefficient for the Oversampler. This parameter can be a value of Oversampling - Data shift

Definition at line 55 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_OversamplingTypeDef::TriggeredMode

Selects the regular triggered oversampling mode. This parameter can be a value of Oversampling - Discontinuous mode

Definition at line 58 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Init().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_adc.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_InitTypeDef Struct Reference
ADC Exported Types

Structure definition of ADC instance and ADC group regular. More...

#include <stm32wbxx_hal_adc.h>

Data Fields

uint32_t | ClockPrescaler
uint32_t | Resolution
uint32_t | DataAlign
uint32_t | ScanConvMode
uint32_t | EOCSelection
FunctionalState | LowPowerAutoWait
FunctionalState | ContinuousConvMode
uint32_t | NbrOfConversion
FunctionalState | DiscontinuousConvMode
uint32_t | NbrOfDiscConversion
uint32_t | ExternalTrigConv
uint32_t | ExternalTrigConvEdge
FunctionalState | DMAContinuousRequests
uint32_t | Overrun
FunctionalState | OversamplingMode
ADC_OversamplingTypeDef Oversampling

Detailed Description

Structure definition of ADC instance and ADC group regular.

Note:
Parameters of this structure are shared within 2 scopes:
  • Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait.
  • Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling.
The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state. ADC state can be either:
  • For all parameters: ADC disabled
  • For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on group regular.
  • For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on groups regular and injected. If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).

Definition at line 87 of file stm32wbxx_hal_adc.h.

Field Documentation

uint32_t ADC_InitTypeDef::ClockPrescaler

Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler. This parameter can be a value of ADC common - Clock source. Note: The ADC clock configuration is common to all ADC instances. Note: ADC clock source and prescaler must be selected in function of system clock to not exceed ADC maximum frequency, depending on devices. Example: STM32WB55xx ADC maximum frequency is 64MHz (corresponding to 4.27Msmp/s maximum) Example: STM32WB50xx ADC maximum frequency is 32MHz (corresponding to 2.13Msmp/s maximum) For ADC maximum frequency, refer to datasheet of the selected device. Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits, AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits. Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details. Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level. Note: This parameter can be modified only if all ADC instances are disabled.

Definition at line 89 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Init().

FunctionalState ADC_InitTypeDef::ContinuousConvMode

Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular, after the first ADC conversion start trigger occurred (software start or external trigger). This parameter can be set to ENABLE or DISABLE.

Definition at line 134 of file stm32wbxx_hal_adc.h.

Referenced by ADC_ConversionStop(), HAL_ADC_Init(), and HAL_ADC_PollForConversion().

uint32_t ADC_InitTypeDef::DataAlign

Specify ADC data alignment in conversion data register (right or left). Refer to reference manual for alignments formats versus resolutions. This parameter can be a value of ADC conversion data alignment

Definition at line 107 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Init().

FunctionalState ADC_InitTypeDef::DiscontinuousConvMode

Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. This parameter can be set to ENABLE or DISABLE.

Definition at line 144 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

FunctionalState ADC_InitTypeDef::DMAContinuousRequests

Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached) or in continuous mode (DMA transfer unlimited, whatever number of conversions). This parameter can be set to ENABLE or DISABLE. Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.

Definition at line 163 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_InitTypeDef::EOCSelection

Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions. This parameter can be a value of ADC sequencer end of unitary conversion or sequence conversions.

Definition at line 119 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), and HAL_ADCEx_InjectedStart_IT().

uint32_t ADC_InitTypeDef::ExternalTrigConv

Select the external event source used to trigger ADC group regular conversion start. If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead. This parameter can be a value of ADC group regular trigger source. Caution: external trigger source is common to all ADC instances.

Definition at line 154 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_InitTypeDef::ExternalTrigConvEdge

Select the external event edge used to trigger ADC group regular conversion start. If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. This parameter can be a value of ADC group regular trigger edge (when external trigger is selected)

Definition at line 159 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Init().

FunctionalState ADC_InitTypeDef::LowPowerAutoWait

Select the dynamic low power Auto Delay: new conversion start only when the previous conversion (for ADC group regular) or previous sequence (for ADC group injected) has been retrieved by user software, using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue(). This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications. This parameter can be set to ENABLE or DISABLE. Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag to free the IRQ vector sequencer. Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. (in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...).

Definition at line 122 of file stm32wbxx_hal_adc.h.

Referenced by ADC_ConversionStop(), and HAL_ADC_Init().

uint32_t ADC_InitTypeDef::NbrOfConversion

Specify the number of ranks that will be converted within the regular group sequencer. To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 16. Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).

Definition at line 138 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_InitTypeDef::NbrOfDiscConversion

Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided. If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. This parameter must be a number between Min_Data = 1 and Max_Data = 8.

Definition at line 150 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_InitTypeDef::Overrun

Select the behavior in case of overrun: data overwritten or preserved (default). This parameter applies to ADC group regular only. This parameter can be a value of ADC group regular - Overrun behavior on conversion data. Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear). Note: Error reporting with respect to the conversion mode:

  • Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
  • Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register).

Definition at line 168 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), and HAL_ADC_Start_IT().

ADC_OversamplingTypeDef ADC_InitTypeDef::Oversampling

Specify the Oversampling parameters. Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled.

Definition at line 183 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Init().

FunctionalState ADC_InitTypeDef::OversamplingMode

Specify whether the oversampling feature is enabled or disabled. This parameter can be set to ENABLE or DISABLE. Note: This parameter can be modified only if there is no conversion is ongoing on ADC groups regular and injected

Definition at line 179 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), and HAL_ADC_Init().

uint32_t ADC_InitTypeDef::Resolution

Configure the ADC resolution. This parameter can be a value of ADC instance - Resolution

Definition at line 104 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_InitTypeDef::ScanConvMode

Configure the sequencer of ADC groups regular and injected. This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each channel in sequencer). Scan direction is upward: from rank 1 to rank 'n'. This parameter can be a value of ADC sequencer scan mode

Definition at line 111 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_adc.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC_ChannelConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_ChannelConfTypeDef Struct Reference
ADC Exported Types

Structure definition of ADC channel for regular group. More...

#include <stm32wbxx_hal_adc.h>

Data Fields

uint32_t | Channel
uint32_t | Rank
uint32_t | SamplingTime
uint32_t | SingleDiff
uint32_t | OffsetNumber
uint32_t | Offset

Detailed Description

Structure definition of ADC channel for regular group.

Note:
The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state. ADC state can be either:
  • For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff')
  • For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group.
  • For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups. If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).

Definition at line 199 of file stm32wbxx_hal_adc.h.

Field Documentation

uint32_t ADC_ChannelConfTypeDef::Channel

Specify the channel to configure into ADC regular group. This parameter can be a value of ADC instance - Channel number Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability.

Definition at line 201 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

uint32_t ADC_ChannelConfTypeDef::Offset

Define the offset to be subtracted from the raw converted data. Offset value must be a positive number. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).

Definition at line 237 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

uint32_t ADC_ChannelConfTypeDef::OffsetNumber

Select the offset number This parameter can be a value of ADC instance - Offset number Caution: Only one offset is allowed per channel. This parameter overwrites the last setting.

Definition at line 233 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

uint32_t ADC_ChannelConfTypeDef::Rank

Specify the rank in the regular group sequencer. This parameter can be a value of ADC group regular - Sequencer ranks Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions adjusted)

Definition at line 205 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

uint32_t ADC_ChannelConfTypeDef::SamplingTime

Sampling time value to be set for the selected channel. Unit: ADC clock cycles Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). This parameter can be a value of Channel - Sampling time Caution: This parameter applies to a channel that can be used into regular and/or injected group. It overwrites the last setting. Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) Refer to device datasheet for timings values.

Definition at line 210 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

uint32_t ADC_ChannelConfTypeDef::SingleDiff

Select single-ended or differential input. In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input). Only channel 'i' has to be configured, channel 'i+1' is configured automatically. This parameter must be a value of Channel - Single or differential ending Caution: This parameter applies to a channel that can be used in a regular and/or injected group. It overwrites the last setting. Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case of another parameter update on the fly)

Definition at line 221 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_adc.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC_AnalogWDGConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_AnalogWDGConfTypeDef Struct Reference
ADC Exported Types

Structure definition of ADC analog watchdog. More...

#include <stm32wbxx_hal_adc.h>

Data Fields

uint32_t | WatchdogNumber
uint32_t | WatchdogMode
uint32_t | Channel
FunctionalState | ITMode
uint32_t | HighThreshold
uint32_t | LowThreshold

Detailed Description

Structure definition of ADC analog watchdog.

Note:
The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. ADC state can be either:
  • For all parameters: ADC disabled or ADC enabled without conversion on going on ADC groups regular and injected.

Definition at line 252 of file stm32wbxx_hal_adc.h.

Field Documentation

uint32_t ADC_AnalogWDGConfTypeDef::Channel

Select which ADC channel to monitor by analog watchdog. For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored). For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE'). This parameter can be a value of ADC instance - Channel number.

Definition at line 264 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::HighThreshold

Configure the ADC analog watchdog High threshold value. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are impacted: the comparison of analog watchdog thresholds is done on oversampling final computation (after ratio and shift application): ADC data register bitfield [15:4] (12 most significant bits).

Definition at line 272 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

FunctionalState ADC_AnalogWDGConfTypeDef::ITMode

Specify whether the analog watchdog is configured in interrupt or polling mode. This parameter can be set to ENABLE or DISABLE

Definition at line 269 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::LowThreshold

Configures the ADC analog watchdog Low threshold value. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are impacted: the comparison of analog watchdog thresholds is done on oversampling final computation (after ratio and shift application): ADC data register bitfield [15:4] (12 most significant bits).

Definition at line 282 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::WatchdogMode

Configure the ADC analog watchdog mode: single/all/none channels. For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC groups regular and-or injected. For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure. Channels on ADC group regular and injected are not differentiated: Set value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no channel. This parameter can be a value of ADC Analog Watchdog Mode.

Definition at line 259 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::WatchdogNumber

Select which ADC analog watchdog is monitoring the selected channel. For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode') For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel) This parameter can be a value of Analog watchdog - Analog watchdog number.

Definition at line 254 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_adc.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC_InjectionConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_InjectionConfigTypeDef Struct Reference
ADC Exported Types

ADC group injected contexts queue configuration. More...

#include <stm32wbxx_hal_adc.h>

Data Fields

uint32_t | ContextQueue
uint32_t | ChannelCount

Detailed Description

ADC group injected contexts queue configuration.

Note:
Structure intended to be used only through structure "ADC_HandleTypeDef"

Definition at line 297 of file stm32wbxx_hal_adc.h.

Field Documentation

uint32_t ADC_InjectionConfigTypeDef::ChannelCount

Number of channels in the injected sequence

Definition at line 303 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfigTypeDef::ContextQueue

Injected channel configuration context: build-up over each HAL_ADCEx_InjectedConfigChannel() call to finally initialize JSQR register at HAL_ADCEx_InjectedConfigChannel() last call

Definition at line 299 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADCEx_InjectedConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_adc.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: __ADC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__ADC_HandleTypeDef Struct Reference
ADC Exported Types

ADC handle Structure definition. More...

#include <stm32wbxx_hal_adc.h>

Data Fields

ADC_TypeDef * | Instance
ADC_InitTypeDef Init
DMA_HandleTypeDef * DMA_Handle
HAL_LockTypeDef | Lock
__IO uint32_t | State
__IO uint32_t | ErrorCode
ADC_InjectionConfigTypeDef InjectionConfig
void(* | ConvCpltCallback )(struct __ADC_HandleTypeDef *hadc)
void(* | ConvHalfCpltCallback )(struct __ADC_HandleTypeDef *hadc)
void(* | LevelOutOfWindowCallback )(struct __ADC_HandleTypeDef *hadc)
void(* | ErrorCallback )(struct __ADC_HandleTypeDef *hadc)
void(* | InjectedConvCpltCallback )(struct __ADC_HandleTypeDef *hadc)
void(* | InjectedQueueOverflowCallback )(struct __ADC_HandleTypeDef *hadc)
void(* | LevelOutOfWindow2Callback )(struct __ADC_HandleTypeDef *hadc)
void(* | LevelOutOfWindow3Callback )(struct __ADC_HandleTypeDef *hadc)
void(* | EndOfSamplingCallback )(struct __ADC_HandleTypeDef *hadc)
void(* | MspInitCallback )(struct __ADC_HandleTypeDef *hadc)
void(* | MspDeInitCallback )(struct __ADC_HandleTypeDef *hadc)

Detailed Description

ADC handle Structure definition.

Definition at line 359 of file stm32wbxx_hal_adc.h.

Field Documentation

void(* __ADC_HandleTypeDef::ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc)

ADC conversion complete callback

Definition at line 372 of file stm32wbxx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

void(* __ADC_HandleTypeDef::ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc)

ADC conversion DMA half-transfer callback

Definition at line 373 of file stm32wbxx_hal_adc.h.

Referenced by ADC_DMAHalfConvCplt(), HAL_ADC_Init(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

DMA_HandleTypeDef* __ADC_HandleTypeDef::DMA_Handle

Pointer DMA Handler

Definition at line 366 of file stm32wbxx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_Start_DMA(), HAL_ADC_Stop_DMA(), and HAL_ADCEx_RegularStop_DMA().

void(* __ADC_HandleTypeDef::EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc)

ADC end of sampling callback

Definition at line 380 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

void(* __ADC_HandleTypeDef::ErrorCallback)(struct __ADC_HandleTypeDef *hadc)

ADC error callback

Definition at line 375 of file stm32wbxx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_DMAError(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

__IO uint32_t __ADC_HandleTypeDef::ErrorCode

ADC Error code

Definition at line 369 of file stm32wbxx_hal_adc.h.

Referenced by ADC_ConversionStop(), ADC_Disable(), ADC_DMAError(), ADC_Enable(), HAL_ADC_GetError(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADC_RegisterCallback(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_UnRegisterCallback(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

ADC_InitTypeDef __ADC_HandleTypeDef::Init

ADC initialization parameters and regular conversions setting

Definition at line 365 of file stm32wbxx_hal_adc.h.

Referenced by ADC_ConversionStop(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedPollForConversion(), and HAL_ADCEx_InjectedStart_IT().

void(* __ADC_HandleTypeDef::InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc)

ADC group injected conversion complete callback

Definition at line 376 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

void(* __ADC_HandleTypeDef::InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc)

ADC group injected context queue overflow callback

Definition at line 377 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

ADC_InjectionConfigTypeDef __ADC_HandleTypeDef::InjectionConfig

ADC injected channel configuration build-up structure

Definition at line 370 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADCEx_InjectedConfigChannel().

ADC_TypeDef* __ADC_HandleTypeDef::Instance

Register base address

Definition at line 364 of file stm32wbxx_hal_adc.h.

Referenced by ADC_ConversionStop(), ADC_Disable(), ADC_DMAConvCplt(), ADC_Enable(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_DeInit(), HAL_ADC_GetError(), HAL_ADC_GetState(), HAL_ADC_GetValue(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_GetValue(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_DisableInjectedQueue(), HAL_ADCEx_DisableVoltageRegulator(), HAL_ADCEx_EnableInjectedQueue(), HAL_ADCEx_EnterADCDeepPowerDownMode(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedGetValue(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

void(* __ADC_HandleTypeDef::LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc)

ADC analog watchdog 2 callback

Definition at line 378 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

void(* __ADC_HandleTypeDef::LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc)

ADC analog watchdog 3 callback

Definition at line 379 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

void(* __ADC_HandleTypeDef::LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc)

ADC analog watchdog 1 callback

Definition at line 374 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

HAL_LockTypeDef __ADC_HandleTypeDef::Lock

ADC locking object

Definition at line 367 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Init().

void(* __ADC_HandleTypeDef::MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc)

ADC Msp DeInit callback

Definition at line 382 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

void(* __ADC_HandleTypeDef::MspInitCallback)(struct __ADC_HandleTypeDef *hadc)

ADC Msp Init callback

Definition at line 381 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

__IO uint32_t __ADC_HandleTypeDef::State

ADC communication state (bitmap of ADC states)

Definition at line 368 of file stm32wbxx_hal_adc.h.

Referenced by ADC_ConversionStop(), ADC_Disable(), ADC_DMAConvCplt(), ADC_DMAError(), ADC_Enable(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_DeInit(), HAL_ADC_GetState(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_RegisterCallback(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADC_UnRegisterCallback(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_EnableInjectedQueue(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_adc.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC Error Code

Defines
ADC Error Code
ADC Exported Constants

Defines

#define | HAL_ADC_ERROR_NONE (0x00U)
#define | HAL_ADC_ERROR_INTERNAL (0x01U)
#define | HAL_ADC_ERROR_OVR (0x02U)
#define | HAL_ADC_ERROR_DMA (0x04U)
#define | HAL_ADC_ERROR_JQOVF (0x08U)
#define | HAL_ADC_ERROR_INVALID_CALLBACK (0x10U)

Define Documentation

#define HAL_ADC_ERROR_DMA (0x04U)

DMA transfer error

Definition at line 430 of file stm32wbxx_hal_adc.h.

Referenced by ADC_DMAError(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

#define HAL_ADC_ERROR_INTERNAL (0x01U)

ADC peripheral internal error (problem of clocking, enable/disable, erroneous state, ...)

Definition at line 427 of file stm32wbxx_hal_adc.h.

Referenced by ADC_ConversionStop(), ADC_Disable(), ADC_Enable(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), and HAL_ADCEx_Calibration_SetValue().

#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U)

Invalid Callback error

Definition at line 433 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_RegisterCallback(), and HAL_ADC_UnRegisterCallback().

#define HAL_ADC_ERROR_JQOVF (0x08U)

Injected context queue overflow error

Definition at line 431 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define HAL_ADC_ERROR_NONE (0x00U)

No error

Definition at line 426 of file stm32wbxx_hal_adc.h.

#define HAL_ADC_ERROR_OVR (0x02U)

Overrun error

Definition at line 429 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC common - Clock source

Defines
ADC common - Clock source
ADC Exported Constants

Defines

#define | ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1)
#define | ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2)
#define | ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4)
#define | ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1)
#define | ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2)
#define | ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4)
#define | ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6)
#define | ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8)
#define | ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10)
#define | ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12)
#define | ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16)
#define | ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32)
#define | ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64)
#define | ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128)
#define | ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256)

Define Documentation

#define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1)

ADC asynchronous clock without prescaler

Definition at line 446 of file stm32wbxx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10)

ADC asynchronous clock with prescaler division by 10

Definition at line 451 of file stm32wbxx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12)

ADC asynchronous clock with prescaler division by 12

Definition at line 452 of file stm32wbxx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128)

ADC asynchronous clock with prescaler division by 128

Definition at line 456 of file stm32wbxx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16)

ADC asynchronous clock with prescaler division by 16

Definition at line 453 of file stm32wbxx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2)

ADC asynchronous clock with prescaler division by 2

Definition at line 447 of file stm32wbxx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256)

ADC asynchronous clock with prescaler division by 256

Definition at line 457 of file stm32wbxx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32)

ADC asynchronous clock with prescaler division by 32

Definition at line 454 of file stm32wbxx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4)

ADC asynchronous clock with prescaler division by 4

Definition at line 448 of file stm32wbxx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6)

ADC asynchronous clock with prescaler division by 6

Definition at line 449 of file stm32wbxx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64)

ADC asynchronous clock with prescaler division by 64

Definition at line 455 of file stm32wbxx_hal_adc.h.

#define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8)

ADC asynchronous clock with prescaler division by 8

Definition at line 450 of file stm32wbxx_hal_adc.h.

#define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1)

ADC synchronous clock derived from AHB clock without prescaler

Definition at line 442 of file stm32wbxx_hal_adc.h.

#define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2)

ADC synchronous clock derived from AHB clock with prescaler division by 2

Definition at line 443 of file stm32wbxx_hal_adc.h.

#define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4)

ADC synchronous clock derived from AHB clock with prescaler division by 4

Definition at line 444 of file stm32wbxx_hal_adc.h.

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC instance - Resolution

Defines
ADC instance - Resolution
ADC Exported Constants

Defines

#define | ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B)
#define | ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B)
#define | ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B)
#define | ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B)

Define Documentation

#define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B)

ADC resolution 10 bits

Definition at line 466 of file stm32wbxx_hal_adc.h.

#define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B)

ADC resolution 12 bits

Definition at line 465 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B)

ADC resolution 6 bits

Definition at line 468 of file stm32wbxx_hal_adc.h.

#define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B)

ADC resolution 8 bits

Definition at line 467 of file stm32wbxx_hal_adc.h.

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC conversion data alignment

Defines
ADC conversion data alignment
ADC Exported Constants

Defines

#define | ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)
#define | ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT)

Define Documentation

#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT)

ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)

Definition at line 477 of file stm32wbxx_hal_adc.h.

#define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)

ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)

Definition at line 476 of file stm32wbxx_hal_adc.h.

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC sequencer scan mode

Defines
ADC sequencer scan mode
ADC Exported Constants

Defines

#define | ADC_SCAN_DISABLE (0x00000000UL)
#define | ADC_SCAN_ENABLE (0x00000001UL)

Define Documentation

#define ADC_SCAN_DISABLE (0x00000000UL)

Scan mode disabled

Definition at line 485 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_SCAN_ENABLE (0x00000001UL)

Scan mode enabled

Definition at line 486 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Init().

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC group regular trigger source

Defines
ADC group regular trigger source
ADC Exported Constants

Defines

#define | ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE)
#define | ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO)
#define | ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)
#define | ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1)
#define | ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2)
#define | ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3)
#define | ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO)
#define | ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2)
#define | ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11)

Define Documentation

#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11)

ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting).

Definition at line 503 of file stm32wbxx_hal_adc.h.

#define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1)

ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 498 of file stm32wbxx_hal_adc.h.

#define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2)

ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 499 of file stm32wbxx_hal_adc.h.

#define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3)

ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 500 of file stm32wbxx_hal_adc.h.

#define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO)

ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 496 of file stm32wbxx_hal_adc.h.

#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)

ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting).

Definition at line 497 of file stm32wbxx_hal_adc.h.

#define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2)

ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 502 of file stm32wbxx_hal_adc.h.

#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO)

ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 501 of file stm32wbxx_hal_adc.h.

#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE)

ADC group regular conversion trigger internal: SW start.

Definition at line 495 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Init().

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC group regular trigger edge (when external trigger is selected)

Defines
ADC group regular trigger edge (when external trigger is selected)
ADC Exported Constants

Defines

#define | ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL)
#define | ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING)
#define | ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING)
#define | ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING)

Define Documentation

#define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING)

ADC group regular conversion trigger polarity set to falling edge

Definition at line 513 of file stm32wbxx_hal_adc.h.

#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL)

Regular conversions hardware trigger detection disabled

Definition at line 511 of file stm32wbxx_hal_adc.h.

#define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING)

ADC group regular conversion trigger polarity set to rising edge

Definition at line 512 of file stm32wbxx_hal_adc.h.

#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING)

ADC group regular conversion trigger polarity set to both rising and falling edges

Definition at line 514 of file stm32wbxx_hal_adc.h.

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC sequencer end of unitary conversion or sequence conversions

Defines
ADC sequencer end of unitary conversion or sequence conversions
ADC Exported Constants

Defines

#define | ADC_EOC_SINGLE_CONV (ADC_ISR_EOC)
#define | ADC_EOC_SEQ_CONV (ADC_ISR_EOS)

Define Documentation

#define ADC_EOC_SEQ_CONV (ADC_ISR_EOS)

End of sequence conversions flag

Definition at line 523 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_PollForConversion(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), and HAL_ADCEx_InjectedStart_IT().

#define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC)

End of unitary conversion flag

Definition at line 522 of file stm32wbxx_hal_adc.h.

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC group regular - Overrun behavior on conversion data

Defines
ADC group regular - Overrun behavior on conversion data
ADC Exported Constants

Defines

#define | ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED)
#define | ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN)

Define Documentation

#define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN)

ADC group regular behavior in case of overrun: data overwritten

Definition at line 532 of file stm32wbxx_hal_adc.h.

#define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED)

ADC group regular behavior in case of overrun: data preserved

Definition at line 531 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), and HAL_ADC_Start_IT().

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC group regular - Sequencer ranks

Defines
ADC group regular - Sequencer ranks
ADC Exported Constants

Defines

#define | ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1)
#define | ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2)
#define | ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3)
#define | ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4)
#define | ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5)
#define | ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6)
#define | ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7)
#define | ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8)
#define | ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9)
#define | ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10)
#define | ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11)
#define | ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12)
#define | ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13)
#define | ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14)
#define | ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15)
#define | ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16)

Define Documentation

#define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1)

ADC group regular sequencer rank 1

Definition at line 540 of file stm32wbxx_hal_adc.h.

#define ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10)

ADC group regular sequencer rank 10

Definition at line 549 of file stm32wbxx_hal_adc.h.

#define ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11)

ADC group regular sequencer rank 11

Definition at line 550 of file stm32wbxx_hal_adc.h.

#define ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12)

ADC group regular sequencer rank 12

Definition at line 551 of file stm32wbxx_hal_adc.h.

#define ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13)

ADC group regular sequencer rank 13

Definition at line 552 of file stm32wbxx_hal_adc.h.

#define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14)

ADC group regular sequencer rank 14

Definition at line 553 of file stm32wbxx_hal_adc.h.

#define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15)

ADC group regular sequencer rank 15

Definition at line 554 of file stm32wbxx_hal_adc.h.

#define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16)

ADC group regular sequencer rank 16

Definition at line 555 of file stm32wbxx_hal_adc.h.

#define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2)

ADC group regular sequencer rank 2

Definition at line 541 of file stm32wbxx_hal_adc.h.

#define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3)

ADC group regular sequencer rank 3

Definition at line 542 of file stm32wbxx_hal_adc.h.

#define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4)

ADC group regular sequencer rank 4

Definition at line 543 of file stm32wbxx_hal_adc.h.

#define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5)

ADC group regular sequencer rank 5

Definition at line 544 of file stm32wbxx_hal_adc.h.

#define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6)

ADC group regular sequencer rank 6

Definition at line 545 of file stm32wbxx_hal_adc.h.

#define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7)

ADC group regular sequencer rank 7

Definition at line 546 of file stm32wbxx_hal_adc.h.

#define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8)

ADC group regular sequencer rank 8

Definition at line 547 of file stm32wbxx_hal_adc.h.

#define ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9)

ADC group regular sequencer rank 9

Definition at line 548 of file stm32wbxx_hal_adc.h.

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Channel - Sampling time

Defines
Channel - Sampling time
ADC Exported Constants

Defines

#define | ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5)
#define | ADC_SAMPLETIME_6CYCLES_5 (LL_ADC_SAMPLINGTIME_6CYCLES_5)
#define | ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5)
#define | ADC_SAMPLETIME_24CYCLES_5 (LL_ADC_SAMPLINGTIME_24CYCLES_5)
#define | ADC_SAMPLETIME_47CYCLES_5 (LL_ADC_SAMPLINGTIME_47CYCLES_5)
#define | ADC_SAMPLETIME_92CYCLES_5 (LL_ADC_SAMPLINGTIME_92CYCLES_5)
#define | ADC_SAMPLETIME_247CYCLES_5 (LL_ADC_SAMPLINGTIME_247CYCLES_5)
#define | ADC_SAMPLETIME_640CYCLES_5 (LL_ADC_SAMPLINGTIME_640CYCLES_5)

Define Documentation

#define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5)

Sampling time 12.5 ADC clock cycles

Definition at line 565 of file stm32wbxx_hal_adc.h.

#define ADC_SAMPLETIME_247CYCLES_5 (LL_ADC_SAMPLINGTIME_247CYCLES_5)

Sampling time 247.5 ADC clock cycles

Definition at line 569 of file stm32wbxx_hal_adc.h.

#define ADC_SAMPLETIME_24CYCLES_5 (LL_ADC_SAMPLINGTIME_24CYCLES_5)

Sampling time 24.5 ADC clock cycles

Definition at line 566 of file stm32wbxx_hal_adc.h.

#define ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5)

Sampling time 2.5 ADC clock cycles

Definition at line 563 of file stm32wbxx_hal_adc.h.

#define ADC_SAMPLETIME_47CYCLES_5 (LL_ADC_SAMPLINGTIME_47CYCLES_5)

Sampling time 47.5 ADC clock cycles

Definition at line 567 of file stm32wbxx_hal_adc.h.

#define ADC_SAMPLETIME_640CYCLES_5 (LL_ADC_SAMPLINGTIME_640CYCLES_5)

Sampling time 640.5 ADC clock cycles

Definition at line 570 of file stm32wbxx_hal_adc.h.

#define ADC_SAMPLETIME_6CYCLES_5 (LL_ADC_SAMPLINGTIME_6CYCLES_5)

Sampling time 6.5 ADC clock cycles

Definition at line 564 of file stm32wbxx_hal_adc.h.

#define ADC_SAMPLETIME_92CYCLES_5 (LL_ADC_SAMPLINGTIME_92CYCLES_5)

Sampling time 92.5 ADC clock cycles

Definition at line 568 of file stm32wbxx_hal_adc.h.

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC instance - Channel number

Defines
ADC instance - Channel number
ADC Exported Constants

Defines

#define | ADC_CHANNEL_0 (LL_ADC_CHANNEL_0)
#define | ADC_CHANNEL_1 (LL_ADC_CHANNEL_1)
#define | ADC_CHANNEL_2 (LL_ADC_CHANNEL_2)
#define | ADC_CHANNEL_3 (LL_ADC_CHANNEL_3)
#define | ADC_CHANNEL_4 (LL_ADC_CHANNEL_4)
#define | ADC_CHANNEL_5 (LL_ADC_CHANNEL_5)
#define | ADC_CHANNEL_6 (LL_ADC_CHANNEL_6)
#define | ADC_CHANNEL_7 (LL_ADC_CHANNEL_7)
#define | ADC_CHANNEL_8 (LL_ADC_CHANNEL_8)
#define | ADC_CHANNEL_9 (LL_ADC_CHANNEL_9)
#define | ADC_CHANNEL_10 (LL_ADC_CHANNEL_10)
#define | ADC_CHANNEL_11 (LL_ADC_CHANNEL_11)
#define | ADC_CHANNEL_12 (LL_ADC_CHANNEL_12)
#define | ADC_CHANNEL_13 (LL_ADC_CHANNEL_13)
#define | ADC_CHANNEL_14 (LL_ADC_CHANNEL_14)
#define | ADC_CHANNEL_15 (LL_ADC_CHANNEL_15)
#define | ADC_CHANNEL_16 (LL_ADC_CHANNEL_16)
#define | ADC_CHANNEL_17 (LL_ADC_CHANNEL_17)
#define | ADC_CHANNEL_18 (LL_ADC_CHANNEL_18)
#define | ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT)
#define | ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR)
#define | ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT)

Define Documentation

#define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0)

ADC external channel (channel connected to GPIO pin) ADCx_IN0

Definition at line 580 of file stm32wbxx_hal_adc.h.

#define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1)

ADC external channel (channel connected to GPIO pin) ADCx_IN1

Definition at line 581 of file stm32wbxx_hal_adc.h.

#define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10)

ADC external channel (channel connected to GPIO pin) ADCx_IN10

Definition at line 590 of file stm32wbxx_hal_adc.h.

#define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11)

ADC external channel (channel connected to GPIO pin) ADCx_IN11

Definition at line 591 of file stm32wbxx_hal_adc.h.

#define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12)

ADC external channel (channel connected to GPIO pin) ADCx_IN12

Definition at line 592 of file stm32wbxx_hal_adc.h.

#define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13)

ADC external channel (channel connected to GPIO pin) ADCx_IN13

Definition at line 593 of file stm32wbxx_hal_adc.h.

#define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14)

ADC external channel (channel connected to GPIO pin) ADCx_IN14

Definition at line 594 of file stm32wbxx_hal_adc.h.

#define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15)

ADC external channel (channel connected to GPIO pin) ADCx_IN15

Definition at line 595 of file stm32wbxx_hal_adc.h.

#define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16)

ADC external channel (channel connected to GPIO pin) ADCx_IN16

Definition at line 596 of file stm32wbxx_hal_adc.h.

#define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17)

ADC external channel (channel connected to GPIO pin) ADCx_IN17

Definition at line 597 of file stm32wbxx_hal_adc.h.

#define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18)

ADC external channel (channel connected to GPIO pin) ADCx_IN18

Definition at line 598 of file stm32wbxx_hal_adc.h.

#define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2)

ADC external channel (channel connected to GPIO pin) ADCx_IN2

Definition at line 582 of file stm32wbxx_hal_adc.h.

#define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3)

ADC external channel (channel connected to GPIO pin) ADCx_IN3

Definition at line 583 of file stm32wbxx_hal_adc.h.

#define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4)

ADC external channel (channel connected to GPIO pin) ADCx_IN4

Definition at line 584 of file stm32wbxx_hal_adc.h.

#define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5)

ADC external channel (channel connected to GPIO pin) ADCx_IN5

Definition at line 585 of file stm32wbxx_hal_adc.h.

#define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6)

ADC external channel (channel connected to GPIO pin) ADCx_IN6

Definition at line 586 of file stm32wbxx_hal_adc.h.

#define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7)

ADC external channel (channel connected to GPIO pin) ADCx_IN7

Definition at line 587 of file stm32wbxx_hal_adc.h.

#define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8)

ADC external channel (channel connected to GPIO pin) ADCx_IN8

Definition at line 588 of file stm32wbxx_hal_adc.h.

#define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9)

ADC external channel (channel connected to GPIO pin) ADCx_IN9

Definition at line 589 of file stm32wbxx_hal_adc.h.

#define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR)

ADC internal channel connected to Temperature sensor.

Definition at line 600 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT)

ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda.

Definition at line 601 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT)

ADC internal channel connected to VrefInt: Internal voltage reference.

Definition at line 599 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Analog watchdog - Analog watchdog number

Defines
Analog watchdog - Analog watchdog number
ADC Exported Constants

Defines

#define | ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1)
#define | ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2)
#define | ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3)

Define Documentation

#define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1)

ADC analog watchdog number 1

Definition at line 609 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2)

ADC analog watchdog number 2

Definition at line 610 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3)

ADC analog watchdog number 3

Definition at line 611 of file stm32wbxx_hal_adc.h.

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STM32WB55xx HAL User Manual: ADC Analog Watchdog Mode

Defines
ADC Analog Watchdog Mode
ADC Exported Constants

Defines

#define | ADC_ANALOGWATCHDOG_NONE (0x00000000UL)
#define | ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN)
#define | ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN)
#define | ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)
#define | ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN)
#define | ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN)
#define | ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)

Define Documentation

#define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN)

Analog watchdog applied to injected group all channels

Definition at line 624 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN)

Analog watchdog applied to regular group all channels

Definition at line 623 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)

Analog watchdog applied to regular and injected groups all channels

Definition at line 625 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_ANALOGWATCHDOG_NONE (0x00000000UL)

No analog watchdog selected

Definition at line 619 of file stm32wbxx_hal_adc.h.

#define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN)

Analog watchdog applied to an injected group single channel

Definition at line 621 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN)

Analog watchdog applied to a regular group single channel

Definition at line 620 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)

Analog watchdog applied to a regular and injected groups single channel

Definition at line 622 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Oversampling - Ratio

Defines
Oversampling - Ratio
ADC Exported Constants

Defines

#define | ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2)
#define | ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4)
#define | ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8)
#define | ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16)
#define | ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32)
#define | ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64)
#define | ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128)
#define | ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256)

Define Documentation

#define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128)

ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 639 of file stm32wbxx_hal_adc.h.

#define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16)

ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 636 of file stm32wbxx_hal_adc.h.

#define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2)

ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 633 of file stm32wbxx_hal_adc.h.

#define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256)

ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 640 of file stm32wbxx_hal_adc.h.

#define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32)

ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 637 of file stm32wbxx_hal_adc.h.

#define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4)

ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 634 of file stm32wbxx_hal_adc.h.

#define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64)

ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 638 of file stm32wbxx_hal_adc.h.

#define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8)

ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift)

Definition at line 635 of file stm32wbxx_hal_adc.h.

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Oversampling - Data shift

Defines
Oversampling - Data shift
ADC Exported Constants

Defines

#define | ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE)
#define | ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1)
#define | ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2)
#define | ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3)
#define | ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4)
#define | ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5)
#define | ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6)
#define | ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7)
#define | ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8)

Define Documentation

#define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1)

ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data)

Definition at line 649 of file stm32wbxx_hal_adc.h.

#define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2)

ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data)

Definition at line 650 of file stm32wbxx_hal_adc.h.

#define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3)

ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data)

Definition at line 651 of file stm32wbxx_hal_adc.h.

#define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4)

ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data)

Definition at line 652 of file stm32wbxx_hal_adc.h.

#define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5)

ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data)

Definition at line 653 of file stm32wbxx_hal_adc.h.

#define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6)

ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data)

Definition at line 654 of file stm32wbxx_hal_adc.h.

#define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7)

ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data)

Definition at line 655 of file stm32wbxx_hal_adc.h.

#define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8)

ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data)

Definition at line 656 of file stm32wbxx_hal_adc.h.

#define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE)

ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data)

Definition at line 648 of file stm32wbxx_hal_adc.h.

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Oversampling - Discontinuous mode

Defines
Oversampling - Discontinuous mode
ADC Exported Constants

Defines

#define | ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT)
#define | ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT)

Define Documentation

#define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT)

ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger)

Definition at line 665 of file stm32wbxx_hal_adc.h.

#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT)

ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger)

Definition at line 664 of file stm32wbxx_hal_adc.h.

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Oversampling - Oversampling scope for ADC group regular

Defines
Oversampling - Oversampling scope for ADC group regular
ADC Exported Constants

Defines

#define | ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED)
#define | ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED)

Define Documentation

#define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED)

Oversampling buffer maintained during injection sequence

Definition at line 673 of file stm32wbxx_hal_adc.h.

#define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED)

Oversampling buffer zeroed during injection sequence

Definition at line 674 of file stm32wbxx_hal_adc.h.

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC Event type

Defines
ADC Event type
ADC Exported Constants

Defines

#define | ADC_EOSMP_EVENT (ADC_FLAG_EOSMP)
#define | ADC_AWD1_EVENT (ADC_FLAG_AWD1)
#define | ADC_AWD2_EVENT (ADC_FLAG_AWD2)
#define | ADC_AWD3_EVENT (ADC_FLAG_AWD3)
#define | ADC_OVR_EVENT (ADC_FLAG_OVR)
#define | ADC_JQOVF_EVENT (ADC_FLAG_JQOVF)

Define Documentation

#define ADC_AWD1_EVENT (ADC_FLAG_AWD1)

ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series)

Definition at line 684 of file stm32wbxx_hal_adc.h.

#define ADC_AWD2_EVENT (ADC_FLAG_AWD2)

ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series)

Definition at line 685 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_PollForEvent().

#define ADC_AWD3_EVENT (ADC_FLAG_AWD3)

ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series)

Definition at line 686 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_PollForEvent().

#define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP)

ADC End of Sampling event

Definition at line 683 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_PollForEvent().

#define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF)

ADC Injected Context Queue Overflow event

Definition at line 688 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_PollForEvent().

#define ADC_OVR_EVENT (ADC_FLAG_OVR)

ADC overrun event

Definition at line 687 of file stm32wbxx_hal_adc.h.

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC interrupts definition

Defines
ADC interrupts definition
ADC Exported Constants

Defines

#define | ADC_IT_RDY ADC_IER_ADRDYIE
#define | ADC_IT_EOSMP ADC_IER_EOSMPIE
#define | ADC_IT_EOC ADC_IER_EOCIE
#define | ADC_IT_EOS ADC_IER_EOSIE
#define | ADC_IT_OVR ADC_IER_OVRIE
#define | ADC_IT_JEOC ADC_IER_JEOCIE
#define | ADC_IT_JEOS ADC_IER_JEOSIE
#define | ADC_IT_AWD1 ADC_IER_AWD1IE
#define | ADC_IT_AWD2 ADC_IER_AWD2IE
#define | ADC_IT_AWD3 ADC_IER_AWD3IE
#define | ADC_IT_JQOVF ADC_IER_JQOVFIE
#define | ADC_IT_AWD ADC_IT_AWD1

Define Documentation

#define ADC_IT_AWD ADC_IT_AWD1

ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog

Definition at line 709 of file stm32wbxx_hal_adc.h.

#define ADC_IT_AWD1 ADC_IER_AWD1IE

ADC Analog watchdog 1 interrupt source (main analog watchdog)

Definition at line 704 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADC_IRQHandler().

#define ADC_IT_AWD2 ADC_IER_AWD2IE

ADC Analog watchdog 2 interrupt source (additional analog watchdog)

Definition at line 705 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADC_IRQHandler().

#define ADC_IT_AWD3 ADC_IER_AWD3IE

ADC Analog watchdog 3 interrupt source (additional analog watchdog)

Definition at line 706 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADC_IRQHandler().

#define ADC_IT_EOC ADC_IER_EOCIE

ADC End of regular conversion interrupt source

Definition at line 699 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_Start_IT(), HAL_ADC_Stop_IT(), and HAL_ADCEx_RegularStop_IT().

#define ADC_IT_EOS ADC_IER_EOSIE

ADC End of regular sequence of conversions interrupt source

Definition at line 700 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_Start_IT(), HAL_ADC_Stop_IT(), and HAL_ADCEx_RegularStop_IT().

#define ADC_IT_EOSMP ADC_IER_EOSMPIE

ADC End of sampling interrupt source

Definition at line 698 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADC_IRQHandler().

#define ADC_IT_JEOC ADC_IER_JEOCIE

ADC End of injected conversion interrupt source

Definition at line 702 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_InjectedStop_IT().

#define ADC_IT_JEOS ADC_IER_JEOSIE

ADC End of injected sequence of conversions interrupt source

Definition at line 703 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_InjectedStop_IT().

#define ADC_IT_JQOVF ADC_IER_JQOVFIE

ADC Injected Context Queue Overflow interrupt source

Definition at line 707 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADC_IRQHandler().

#define ADC_IT_OVR ADC_IER_OVRIE

ADC overrun interrupt source

Definition at line 701 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

#define ADC_IT_RDY ADC_IER_ADRDYIE

ADC Ready interrupt source

Definition at line 697 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_DeInit().

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC flags definition

Defines
ADC flags definition
ADC Exported Constants

Defines

#define | ADC_FLAG_RDY ADC_ISR_ADRDY
#define | ADC_FLAG_EOSMP ADC_ISR_EOSMP
#define | ADC_FLAG_EOC ADC_ISR_EOC
#define | ADC_FLAG_EOS ADC_ISR_EOS
#define | ADC_FLAG_OVR ADC_ISR_OVR
#define | ADC_FLAG_JEOC ADC_ISR_JEOC
#define | ADC_FLAG_JEOS ADC_ISR_JEOS
#define | ADC_FLAG_AWD1 ADC_ISR_AWD1
#define | ADC_FLAG_AWD2 ADC_ISR_AWD2
#define | ADC_FLAG_AWD3 ADC_ISR_AWD3
#define | ADC_FLAG_JQOVF ADC_ISR_JQOVF

Define Documentation

#define ADC_FLAG_AWD1 ADC_ISR_AWD1

ADC Analog watchdog 1 flag (main analog watchdog)

Definition at line 725 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define ADC_FLAG_AWD2 ADC_ISR_AWD2

ADC Analog watchdog 2 flag (additional analog watchdog)

Definition at line 726 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define ADC_FLAG_AWD3 ADC_ISR_AWD3

ADC Analog watchdog 3 flag (additional analog watchdog)

Definition at line 727 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define ADC_FLAG_EOC ADC_ISR_EOC

ADC End of Regular Conversion flag

Definition at line 720 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

#define ADC_FLAG_EOS ADC_ISR_EOS

ADC End of Regular sequence of Conversions flag

Definition at line 721 of file stm32wbxx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

#define ADC_FLAG_EOSMP ADC_ISR_EOSMP

ADC End of Sampling flag

Definition at line 719 of file stm32wbxx_hal_adc.h.

Referenced by ADC_Disable(), HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define ADC_FLAG_JEOC ADC_ISR_JEOC

ADC End of Injected Conversion flag

Definition at line 723 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define ADC_FLAG_JEOS ADC_ISR_JEOS

ADC End of Injected sequence of Conversions flag

Definition at line 724 of file stm32wbxx_hal_adc.h.

Referenced by ADC_ConversionStop(), HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define ADC_FLAG_JQOVF ADC_ISR_JQOVF

ADC Injected Context Queue Overflow flag

Definition at line 728 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_InjectedStop_IT().

#define ADC_FLAG_OVR ADC_ISR_OVR

ADC overrun flag

Definition at line 722 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

#define ADC_FLAG_RDY ADC_ISR_ADRDY

ADC Ready flag

Definition at line 718 of file stm32wbxx_hal_adc.h.

Referenced by ADC_Disable(), ADC_Enable(), and HAL_ADC_DeInit().

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC Exported Constants

Modules | Defines
ADC Exported Constants
ADC

Modules

ADC Error Code
ADC common - Clock source
ADC instance - Resolution
ADC conversion data alignment
ADC sequencer scan mode
ADC group regular trigger source
ADC group regular trigger edge (when external trigger is selected)
ADC sequencer end of unitary conversion or sequence conversions
ADC group regular - Overrun behavior on conversion data
ADC group regular - Sequencer ranks
Channel - Sampling time
ADC instance - Channel number
Analog watchdog - Analog watchdog number
ADC Analog Watchdog Mode
Oversampling - Ratio
Oversampling - Data shift
Oversampling - Discontinuous mode
Oversampling - Oversampling scope for ADC group regular
ADC Event type
ADC interrupts definition
ADC flags definition

Defines

#define ADC_AWD_EVENT ADC_AWD1_EVENT

Define Documentation

#define ADC_AWD_EVENT ADC_AWD1_EVENT

ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog

Definition at line 692 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_PollForEvent().

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC Private Macros

Defines
ADC Private Macros
ADC

Defines

#define | ADC_GET_RESOLUTION(__HANDLE__) (LL_ADC_GetResolution((__HANDLE__)->Instance))
Return resolution bits in CFGR register RES[1:0] field.
#define | ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").
#define | ADC_STATE_CLR_SET MODIFY_REG
Simultaneously clear and set specific bits of the handle State.
#define | IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__))
Verify that a given value is aligned with the ADC resolution range.
#define | IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL)))
Verify the length of the scheduled regular conversions group.
#define | IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL)))
Verify the number of scheduled regular conversions in discontinuous mode.
#define | IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__)
Verify the ADC clock setting.
#define | IS_ADC_RESOLUTION(__RESOLUTION__)
Verify the ADC resolution setting.
#define | IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__)
Verify the ADC resolution setting when limited to 6 or 8 bits.
#define | IS_ADC_DATA_ALIGN(__ALIGN__)
Verify the ADC converted data alignment.
#define | IS_ADC_SCAN_MODE(__SCAN_MODE__)
Verify the ADC scan mode.
#define | IS_ADC_EXTTRIG_EDGE(__EDGE__)
Verify the ADC edge trigger setting for regular group.
#define | IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__)
Verify the ADC regular conversions external trigger.
#define | IS_ADC_EOC_SELECTION(__EOC_SELECTION__)
Verify the ADC regular conversions check for converted data availability.
#define | IS_ADC_OVERRUN(__OVR__)
Verify the ADC regular conversions overrun handling.
#define | IS_ADC_SAMPLE_TIME(__TIME__)
Verify the ADC conversions sampling time.
#define | IS_ADC_REGULAR_RANK(__CHANNEL__)
Verify the ADC regular channel setting.

Define Documentation

#define ADC_CLEAR_ERRORCODE ( __HANDLE__ ) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)

Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").

Parameters:
__HANDLE__ ADC handle
Return values:
None

Definition at line 759 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_Init(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define ADC_GET_RESOLUTION ( __HANDLE__ ) (LL_ADC_GetResolution((__HANDLE__)->Instance))

Return resolution bits in CFGR register RES[1:0] field.

Parameters:
__HANDLE__ ADC handle
Return values:
Value of bitfield RES in CFGR register.

Definition at line 751 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_STATE_CLR_SET MODIFY_REG

Simultaneously clear and set specific bits of the handle State.

Note:
ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), the first parameter is the ADC handle State, the second parameter is the bit field to clear, the third and last parameter is the bit field to set.
Return values:
None

Definition at line 768 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

#define IS_ADC_CLOCKPRESCALER ( __ADC_CLOCK__ )
Value:
(((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1)     || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2)     || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4)     || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6)     || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8)     || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10)    || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12)    || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16)    || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32)    || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64)    || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128)   || \
                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) )

Verify the ADC clock setting.

Parameters:
__ADC_CLOCK__ programmed ADC clock.
Return values:
SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid)

Definition at line 800 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_DATA_ALIGN ( __ALIGN__ )
Value:
(((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \
                                      ((__ALIGN__) == ADC_DATAALIGN_LEFT)    )

Verify the ADC converted data alignment.

Parameters:
__ALIGN__ programmed ADC converted data alignment.
Return values:
SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid)

Definition at line 839 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_EOC_SELECTION ( __EOC_SELECTION__ )
Value:
(((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV)    || \
                                                 ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV)  )

Verify the ADC regular conversions check for converted data availability.

Parameters:
__EOC_SELECTION__ converted data availability check.
Return values:
SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid)

Definition at line 881 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Init(), and HAL_ADC_IRQHandler().

#define IS_ADC_EXTTRIG | ( | __HANDLE__,
 |  | __REGTRIG__
 | ) |
Value:
(((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1)   || \
                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2)   || \
                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3)   || \
                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2)   || \
                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \
                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO)  || \
                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO)  || \
                                                 ((__REGTRIG__) == ADC_SOFTWARE_START)           )

Verify the ADC regular conversions external trigger.

Parameters:
__HANDLE__ | ADC handle
__REGTRIG__ | programmed ADC regular conversions external trigger.
Return values:
SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid)

Definition at line 866 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_EXTTRIG_EDGE ( __EDGE__ )
Value:
(((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE)         || \
                                       ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING)       || \
                                       ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING)      || \
                                       ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)  )

Verify the ADC edge trigger setting for regular group.

Parameters:
__EDGE__ programmed ADC edge trigger setting.
Return values:
SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)

Definition at line 855 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_OVERRUN ( __OVR__ )
Value:
(((__OVR__) == ADC_OVR_DATA_PRESERVED)  || \
                                 ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN)  )

Verify the ADC regular conversions overrun handling.

Parameters:
__OVR__ ADC regular conversions overrun handling.
Return values:
SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid)

Definition at line 889 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_RANGE | ( | __RESOLUTION__,
 |  | __ADC_VALUE__
 | ) | ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__))

Verify that a given value is aligned with the ADC resolution range.

Parameters:
__RESOLUTION__ | ADC resolution (12, 10, 8 or 6 bits).
__ADC_VALUE__ | value checked against the resolution.
Return values:
SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__)

Definition at line 776 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_REGULAR_DISCONT_NUMBER ( NUMBER ) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL)))

Verify the number of scheduled regular conversions in discontinuous mode.

Parameters:
NUMBER number of scheduled regular conversions in discontinuous mode.
Return values:
SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) or RESET (NUMBER is null or too large)

Definition at line 792 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_REGULAR_NB_CONV ( __LENGTH__ ) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL)))

Verify the length of the scheduled regular conversions group.

Parameters:
__LENGTH__ number of programmed conversions.
Return values:
SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large)

Definition at line 784 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_REGULAR_RANK ( __CHANNEL__ )
Value:
(((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \
                                          ((__CHANNEL__) == ADC_REGULAR_RANK_16)   )

Verify the ADC regular channel setting.

Parameters:
__CHANNEL__ programmed ADC regular channel.
Return values:
SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)

Definition at line 911 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

#define IS_ADC_RESOLUTION ( __RESOLUTION__ )
Value:
(((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
                                           ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
                                           ((__RESOLUTION__) == ADC_RESOLUTION_8B)  || \
                                           ((__RESOLUTION__) == ADC_RESOLUTION_6B)    )

Verify the ADC resolution setting.

Parameters:
__RESOLUTION__ programmed ADC resolution.
Return values:
SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)

Definition at line 821 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_RESOLUTION_8_6_BITS ( __RESOLUTION__ )
Value:
(((__RESOLUTION__) == ADC_RESOLUTION_8B) || \
                                                    ((__RESOLUTION__) == ADC_RESOLUTION_6B)   )

Verify the ADC resolution setting when limited to 6 or 8 bits.

Parameters:
__RESOLUTION__ programmed ADC resolution when limited to 6 or 8 bits.
Return values:
SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)

Definition at line 831 of file stm32wbxx_hal_adc.h.

#define IS_ADC_SAMPLE_TIME ( __TIME__ )
Value:
(((__TIME__) == ADC_SAMPLETIME_2CYCLES_5)   || \
                                      ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5)   || \
                                      ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5)  || \
                                      ((__TIME__) == ADC_SAMPLETIME_24CYCLES_5)  || \
                                      ((__TIME__) == ADC_SAMPLETIME_47CYCLES_5)  || \
                                      ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5)  || \
                                      ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \
                                      ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5)   )

Verify the ADC conversions sampling time.

Parameters:
__TIME__ ADC conversions sampling time.
Return values:
SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid)

Definition at line 897 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_SCAN_MODE ( __SCAN_MODE__ )
Value:
(((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \
                                         ((__SCAN_MODE__) == ADC_SCAN_ENABLE)    )

Verify the ADC scan mode.

Parameters:
__SCAN_MODE__ programmed ADC scan mode.
Return values:
SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid)

Definition at line 847 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Init().

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: HAL ADC macro to manage HAL ADC handle, IT and flags.

Defines
HAL ADC macro to manage HAL ADC handle, IT and flags.
ADC Exported Macros

Defines

#define | __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)
Reset ADC handle state.
#define | __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
Enable ADC interrupt.
#define | __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
Disable ADC interrupt.
#define | __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
Checks if the specified ADC interrupt source is enabled or disabled.
#define | __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
Check whether the specified ADC flag is set or not.
#define | __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR) = (__FLAG__))
Clear the specified ADC flag.

Define Documentation

#define __HAL_ADC_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR) = (__FLAG__))

Clear the specified ADC flag.

Parameters:
__HANDLE__ ADC handle
__FLAG__ ADC flag This parameter can be one of the following values:
  • ADC_FLAG_RDY ADC Ready flag
  • ADC_FLAG_EOSMP ADC End of Sampling flag
  • ADC_FLAG_EOC ADC End of Regular Conversion flag
  • ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
  • ADC_FLAG_OVR ADC overrun flag
  • ADC_FLAG_JEOC ADC End of Injected Conversion flag
  • ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag
  • ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
  • ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
  • ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
  • ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag.
Return values:
None

Definition at line 1087 of file stm32wbxx_hal_adc.h.

Referenced by ADC_ConversionStop(), ADC_Disable(), HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define __HAL_ADC_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))

Disable ADC interrupt.

Parameters:
__HANDLE__ ADC handle
__INTERRUPT__ ADC Interrupt This parameter can be one of the following values:
  • ADC_IT_RDY ADC Ready interrupt source
  • ADC_IT_EOSMP ADC End of Sampling interrupt source
  • ADC_IT_EOC ADC End of Regular Conversion interrupt source
  • ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
  • ADC_IT_OVR ADC overrun interrupt source
  • ADC_IT_JEOC ADC End of Injected Conversion interrupt source
  • ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
  • ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
  • ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
  • ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
  • ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
Return values:
None

Definition at line 1024 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_Start_IT(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

#define __HAL_ADC_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))

Enable ADC interrupt.

Parameters:
__HANDLE__ ADC handle
__INTERRUPT__ ADC Interrupt This parameter can be one of the following values:
  • ADC_IT_RDY ADC Ready interrupt source
  • ADC_IT_EOSMP ADC End of Sampling interrupt source
  • ADC_IT_EOC ADC End of Regular Conversion interrupt source
  • ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
  • ADC_IT_OVR ADC overrun interrupt source
  • ADC_IT_JEOC ADC End of Injected Conversion interrupt source
  • ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
  • ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
  • ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
  • ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
  • ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
Return values:
None

Definition at line 1003 of file stm32wbxx_hal_adc.h.

Referenced by HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_InjectedStart_IT().

#define __HAL_ADC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))

Check whether the specified ADC flag is set or not.

Parameters:
__HANDLE__ ADC handle
__FLAG__ ADC flag This parameter can be one of the following values:
  • ADC_FLAG_RDY ADC Ready flag
  • ADC_FLAG_EOSMP ADC End of Sampling flag
  • ADC_FLAG_EOC ADC End of Regular Conversion flag
  • ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
  • ADC_FLAG_OVR ADC overrun flag
  • ADC_FLAG_JEOC ADC End of Injected Conversion flag
  • ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag
  • ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
  • ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
  • ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
  • ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag.
Return values:
State of flag (TRUE or FALSE).

Definition at line 1065 of file stm32wbxx_hal_adc.h.

Referenced by ADC_ConversionStop(), ADC_Enable(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), and HAL_ADCEx_InjectedPollForConversion().

#define __HAL_ADC_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))

Checks if the specified ADC interrupt source is enabled or disabled.

Parameters:
__HANDLE__ ADC handle
__INTERRUPT__ ADC interrupt source to check This parameter can be one of the following values:
  • ADC_IT_RDY ADC Ready interrupt source
  • ADC_IT_EOSMP ADC End of Sampling interrupt source
  • ADC_IT_EOC ADC End of Regular Conversion interrupt source
  • ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
  • ADC_IT_OVR ADC overrun interrupt source
  • ADC_IT_JEOC ADC End of Injected Conversion interrupt source
  • ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
  • ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
  • ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
  • ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
  • ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
Return values:
State of interruption (SET or RESET)

Definition at line 1044 of file stm32wbxx_hal_adc.h.

#define __HAL_ADC_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                                          \
    (__HANDLE__)->State = HAL_ADC_STATE_RESET;                                 \
    (__HANDLE__)->MspInitCallback = NULL;                                      \
    (__HANDLE__)->MspDeInitCallback = NULL;                                    \
  } while(0)

Reset ADC handle state.

Parameters:
__HANDLE__ ADC handle
Return values:
None

Definition at line 974 of file stm32wbxx_hal_adc.h.

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: HAL ADC helper macro

Defines
HAL ADC helper macro
ADC Exported Macros

Defines

#define | __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))
Helper macro to get ADC channel number in decimal format from literals ADC_CHANNEL_x.
#define | __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))
Helper macro to get ADC channel in literal format ADC_CHANNEL_x from number in decimal format.
#define | __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))
Helper macro to determine whether the selected channel corresponds to literal definitions of driver.
#define | __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))
Helper macro to convert a channel defined from parameter definition of a ADC internal channel (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), to its equivalent parameter definition of a ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...).
#define | __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))
Helper macro to determine whether the internal channel selected is available on the ADC instance selected.
#define | __HAL_ADC_COMMON_INSTANCE(__ADCx__) __LL_ADC_COMMON_INSTANCE((__ADCx__))
Helper macro to select the ADC common instance to which is belonging the selected ADC instance.
#define | __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))
Helper macro to check if all ADC instances sharing the same ADC common instance are disabled.
#define | __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))
Helper macro to define the ADC conversion data full-scale digital value corresponding to the selected ADC resolution.
#define | __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__)
Helper macro to convert the ADC conversion data from a resolution to another resolution.
#define | __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__, __ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value).
#define | __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate analog reference voltage (Vref+) (unit: mVolt) from ADC conversion data of internal voltage reference VrefInt.
#define | __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.
#define | __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__, __TEMPSENSOR_TYP_CALX_V__, __TEMPSENSOR_CALX_TEMP__, __VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Define Documentation

#define __HAL_ADC_CALC_DATA_TO_VOLTAGE | ( | __VREFANALOG_VOLTAGE__,
 |  | __ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
__LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),                      \
                                (__ADC_DATA__),                                \
                                (__ADC_RESOLUTION__))

Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value).

Note:
Analog reference voltage (Vref+) must be either known from user board environment or can be calculated using ADC measurement and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
Parameters:
__VREFANALOG_VOLTAGE__ | Analog reference voltage (unit: mV)
__ADC_DATA__ | ADC conversion data (resolution 12 bits) (unit: digital value).
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • ADC_RESOLUTION_12B
  • ADC_RESOLUTION_10B
  • ADC_RESOLUTION_8B
  • ADC_RESOLUTION_6B
Return values:
ADC conversion data equivalent voltage value (unit: mVolt)

Definition at line 1404 of file stm32wbxx_hal_adc.h.

#define __HAL_ADC_CALC_TEMPERATURE | ( | __VREFANALOG_VOLTAGE__,
 |  | __TEMPSENSOR_ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
__LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),                          \
                            (__TEMPSENSOR_ADC_DATA__),                         \
                            (__ADC_RESOLUTION__))

Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Note:
Computation is using temperature sensor calibration values stored in system memory for each device during production.
Calculation formula: Temperature = ((TS_ADC_DATA - TS_CAL1) * (TS_CAL2_TEMP - TS_CAL1_TEMP)) / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP with TS_ADC_DATA = temperature sensor raw data measured by ADC Avg_Slope = (TS_CAL2 - TS_CAL1) / (TS_CAL2_TEMP - TS_CAL1_TEMP) TS_CAL1 = equivalent TS_ADC_DATA at temperature TEMP_DEGC_CAL1 (calibrated in factory) TS_CAL2 = equivalent TS_ADC_DATA at temperature TEMP_DEGC_CAL2 (calibrated in factory) Caution: Calculation relevancy under reserve that calibration parameters are correct (address and data). To calculate temperature using temperature sensor datasheet typical values (generic values less, therefore less accurate than calibrated values), use helper macro __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
As calculation input, the analog reference voltage (Vref+) must be defined as it impacts the ADC LSB equivalent voltage.
Analog reference voltage (Vref+) must be either known from user board environment or can be calculated using ADC measurement and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
On this STM32 serie, calibration data of temperature sensor corresponds to a resolution of 12 bits, this is the recommended ADC resolution to convert voltage of temperature sensor. Otherwise, this macro performs the processing to scale ADC conversion data to 12 bits.
Parameters:
__VREFANALOG_VOLTAGE__ | Analog reference voltage (unit: mV)
__TEMPSENSOR_ADC_DATA__ | ADC conversion data of internal temperature sensor (unit: digital value).
__ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. This parameter can be one of the following values:
  • ADC_RESOLUTION_12B
  • ADC_RESOLUTION_10B
  • ADC_RESOLUTION_8B
  • ADC_RESOLUTION_6B
Return values:
Temperature (unit: degree Celsius)

Definition at line 1486 of file stm32wbxx_hal_adc.h.

#define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS | ( | __TEMPSENSOR_TYP_AVGSLOPE__,
 |  | __TEMPSENSOR_TYP_CALX_V__,
 |  | __TEMPSENSOR_CALX_TEMP__,
 |  | __VREFANALOG_VOLTAGE__,
 |  | __TEMPSENSOR_ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),          \
                                      (__TEMPSENSOR_TYP_CALX_V__),             \
                                      (__TEMPSENSOR_CALX_TEMP__),              \
                                      (__VREFANALOG_VOLTAGE__),                \
                                      (__TEMPSENSOR_ADC_DATA__),               \
                                      (__ADC_RESOLUTION__))

Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Note:
Computation is using temperature sensor typical values (refer to device datasheet).
Calculation formula: Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) / Avg_Slope + CALx_TEMP with TS_ADC_DATA = temperature sensor raw data measured by ADC (unit: digital value) Avg_Slope = temperature sensor slope (unit: uV/Degree Celsius) TS_TYP_CALx_VOLT = temperature sensor digital value at temperature CALx_TEMP (unit: mV) Caution: Calculation relevancy under reserve the temperature sensor of the current device has characteristics in line with datasheet typical values. If temperature sensor calibration values are available on on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), temperature calculation will be more accurate using helper macro __LL_ADC_CALC_TEMPERATURE().
As calculation input, the analog reference voltage (Vref+) must be defined as it impacts the ADC LSB equivalent voltage.
Analog reference voltage (Vref+) must be either known from user board environment or can be calculated using ADC measurement and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
ADC measurement data must correspond to a resolution of 12bits (full scale digital value 4095). If not the case, the data must be preliminarily rescaled to an equivalent resolution of 12 bits.
Parameters:
__TEMPSENSOR_TYP_AVGSLOPE__ | Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). On STM32WB, refer to device datasheet parameter "Avg_Slope".
__TEMPSENSOR_TYP_CALX_V__ | Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). On STM32WB, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
__TEMPSENSOR_CALX_TEMP__ | Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
__VREFANALOG_VOLTAGE__ | Analog voltage reference (Vref+) voltage (unit: mV)
__TEMPSENSOR_ADC_DATA__ | ADC conversion data of internal temperature sensor (unit: digital value).
__ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. This parameter can be one of the following values:
  • ADC_RESOLUTION_12B
  • ADC_RESOLUTION_10B
  • ADC_RESOLUTION_8B
  • ADC_RESOLUTION_6B
Return values:
Temperature (unit: degree Celsius)

Definition at line 1537 of file stm32wbxx_hal_adc.h.

#define __HAL_ADC_CALC_VREFANALOG_VOLTAGE | ( | __VREFINT_ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
__LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),                     \
                                  (__ADC_RESOLUTION__))

Helper macro to calculate analog reference voltage (Vref+) (unit: mVolt) from ADC conversion data of internal voltage reference VrefInt.

Note:
Computation is using VrefInt calibration value stored in system memory for each device during production.
This voltage depends on user board environment: voltage level connected to pin Vref+. On devices with small package, the pin Vref+ is not present and internally bonded to pin Vdda.
On this STM32 serie, calibration data of internal voltage reference VrefInt corresponds to a resolution of 12 bits, this is the recommended ADC resolution to convert voltage of internal voltage reference VrefInt. Otherwise, this macro performs the processing to scale ADC conversion data to 12 bits.
Parameters:
__VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) of internal voltage reference VrefInt (unit: digital value).
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • ADC_RESOLUTION_12B
  • ADC_RESOLUTION_10B
  • ADC_RESOLUTION_8B
  • ADC_RESOLUTION_6B
Return values:
Analog reference voltage (unit: mV)

Definition at line 1436 of file stm32wbxx_hal_adc.h.

#define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL ( __CHANNEL__ ) __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))

Helper macro to convert a channel defined from parameter definition of a ADC internal channel (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), to its equivalent parameter definition of a ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...).

Note:
The channel parameter can be, additionally to a value defined from parameter definition of a ADC internal channel (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), a value defined from parameter definition of ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) or a value from functions where a channel number is returned from ADC registers.
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • ADC_CHANNEL_0
  • ADC_CHANNEL_1 (7)
  • ADC_CHANNEL_2 (7)
  • ADC_CHANNEL_3 (7)
  • ADC_CHANNEL_4 (7)
  • ADC_CHANNEL_5 (7)
  • ADC_CHANNEL_6
  • ADC_CHANNEL_7
  • ADC_CHANNEL_8
  • ADC_CHANNEL_9
  • ADC_CHANNEL_10
  • ADC_CHANNEL_11
  • ADC_CHANNEL_12
  • ADC_CHANNEL_13
  • ADC_CHANNEL_14
  • ADC_CHANNEL_15
  • ADC_CHANNEL_16
  • ADC_CHANNEL_17
  • ADC_CHANNEL_18
  • ADC_CHANNEL_VREFINT
  • ADC_CHANNEL_TEMPSENSOR
  • ADC_CHANNEL_VBAT
(7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
Return values:
Returned value can be one of the following values:
  • ADC_CHANNEL_0
  • ADC_CHANNEL_1
  • ADC_CHANNEL_2
  • ADC_CHANNEL_3
  • ADC_CHANNEL_4
  • ADC_CHANNEL_5
  • ADC_CHANNEL_6
  • ADC_CHANNEL_7
  • ADC_CHANNEL_8
  • ADC_CHANNEL_9
  • ADC_CHANNEL_10
  • ADC_CHANNEL_11
  • ADC_CHANNEL_12
  • ADC_CHANNEL_13
  • ADC_CHANNEL_14
  • ADC_CHANNEL_15
  • ADC_CHANNEL_16
  • ADC_CHANNEL_17
  • ADC_CHANNEL_18

Definition at line 1287 of file stm32wbxx_hal_adc.h.

#define __HAL_ADC_CHANNEL_TO_DECIMAL_NB ( __CHANNEL__ ) __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))

Helper macro to get ADC channel number in decimal format from literals ADC_CHANNEL_x.

Note:
Example: __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4) will return decimal number "4".
The input can be a value from functions where a channel number is returned, either defined with number or with bitfield (only one bit must be set).
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • ADC_CHANNEL_0
  • ADC_CHANNEL_1 (7)
  • ADC_CHANNEL_2 (7)
  • ADC_CHANNEL_3 (7)
  • ADC_CHANNEL_4 (7)
  • ADC_CHANNEL_5 (7)
  • ADC_CHANNEL_6
  • ADC_CHANNEL_7
  • ADC_CHANNEL_8
  • ADC_CHANNEL_9
  • ADC_CHANNEL_10
  • ADC_CHANNEL_11
  • ADC_CHANNEL_12
  • ADC_CHANNEL_13
  • ADC_CHANNEL_14
  • ADC_CHANNEL_15
  • ADC_CHANNEL_16
  • ADC_CHANNEL_17
  • ADC_CHANNEL_18
  • ADC_CHANNEL_VREFINT
  • ADC_CHANNEL_TEMPSENSOR
  • ADC_CHANNEL_VBAT
(7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
Return values:
Value between Min_Data=0 and Max_Data=18

Definition at line 1135 of file stm32wbxx_hal_adc.h.

#define __HAL_ADC_COMMON_INSTANCE ( __ADCx__ ) __LL_ADC_COMMON_INSTANCE((__ADCx__))

Helper macro to select the ADC common instance to which is belonging the selected ADC instance.

Note:
ADC common register instance can be used for:
  • Set parameters common to several ADC instances
  • Multimode (for devices with several ADC instances) Refer to functions having argument "ADCxy_COMMON" as parameter.
Parameters:
__ADCx__ ADC instance
Return values:
ADC common register instance

Definition at line 1324 of file stm32wbxx_hal_adc.h.

#define __HAL_ADC_CONVERT_DATA_RESOLUTION | ( | __DATA__,
 |  | __ADC_RESOLUTION_CURRENT__,
 |  | __ADC_RESOLUTION_TARGET__
 | ) |
Value:
__LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),                                  \
                                   (__ADC_RESOLUTION_CURRENT__),                \
                                   (__ADC_RESOLUTION_TARGET__))

Helper macro to convert the ADC conversion data from a resolution to another resolution.

Parameters:
__DATA__ ADC conversion data to be converted
__ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted This parameter can be one of the following values:
  • ADC_RESOLUTION_12B
  • ADC_RESOLUTION_10B
  • ADC_RESOLUTION_8B
  • ADC_RESOLUTION_6B
__ADC_RESOLUTION_TARGET__ Resolution of the data after conversion This parameter can be one of the following values:
  • ADC_RESOLUTION_12B
  • ADC_RESOLUTION_10B
  • ADC_RESOLUTION_8B
  • ADC_RESOLUTION_6B
Return values:
ADC conversion data to the requested resolution

Definition at line 1381 of file stm32wbxx_hal_adc.h.

#define __HAL_ADC_DECIMAL_NB_TO_CHANNEL ( __DECIMAL_NB__ ) __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))

Helper macro to get ADC channel in literal format ADC_CHANNEL_x from number in decimal format.

Note:
Example: __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4) will return a data equivalent to "ADC_CHANNEL_4".
Parameters:
__DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
Return values:
Returned value can be one of the following values:
  • ADC_CHANNEL_0
  • ADC_CHANNEL_1 (7)
  • ADC_CHANNEL_2 (7)
  • ADC_CHANNEL_3 (7)
  • ADC_CHANNEL_4 (7)
  • ADC_CHANNEL_5 (7)
  • ADC_CHANNEL_6
  • ADC_CHANNEL_7
  • ADC_CHANNEL_8
  • ADC_CHANNEL_9
  • ADC_CHANNEL_10
  • ADC_CHANNEL_11
  • ADC_CHANNEL_12
  • ADC_CHANNEL_13
  • ADC_CHANNEL_14
  • ADC_CHANNEL_15
  • ADC_CHANNEL_16
  • ADC_CHANNEL_17
  • ADC_CHANNEL_18
  • ADC_CHANNEL_VREFINT (1)
  • ADC_CHANNEL_TEMPSENSOR (4)
  • ADC_CHANNEL_VBAT (4)
(7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
(4) For ADC channel read back from ADC register, comparison with internal channel parameter to be done using helper macro __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

Definition at line 1175 of file stm32wbxx_hal_adc.h.

#define __HAL_ADC_DIGITAL_SCALE ( __ADC_RESOLUTION__ ) __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))

Helper macro to define the ADC conversion data full-scale digital value corresponding to the selected ADC resolution.

Note:
ADC conversion data full-scale corresponds to voltage range determined by analog voltage references Vref+ and Vref- (refer to reference manual).
Parameters:
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • ADC_RESOLUTION_12B
  • ADC_RESOLUTION_10B
  • ADC_RESOLUTION_8B
  • ADC_RESOLUTION_6B
Return values:
ADC conversion data full-scale digital value

Definition at line 1360 of file stm32wbxx_hal_adc.h.

#define __HAL_ADC_IS_CHANNEL_INTERNAL ( __CHANNEL__ ) __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))

Helper macro to determine whether the selected channel corresponds to literal definitions of driver.

Note:
The different literal definitions of ADC channels are:
  • ADC internal channel: ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...
  • ADC external channel (channel connected to a GPIO pin): ADC_CHANNEL_1, ADC_CHANNEL_2, ...
The channel parameter must be a value defined from literal definition of a ADC internal channel (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...), must not be a value from functions where a channel number is returned from ADC registers, because internal and external channels share the same channel number in ADC registers. The differentiation is made only with parameters definitions of driver.
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • ADC_CHANNEL_0
  • ADC_CHANNEL_1 (7)
  • ADC_CHANNEL_2 (7)
  • ADC_CHANNEL_3 (7)
  • ADC_CHANNEL_4 (7)
  • ADC_CHANNEL_5 (7)
  • ADC_CHANNEL_6
  • ADC_CHANNEL_7
  • ADC_CHANNEL_8
  • ADC_CHANNEL_9
  • ADC_CHANNEL_10
  • ADC_CHANNEL_11
  • ADC_CHANNEL_12
  • ADC_CHANNEL_13
  • ADC_CHANNEL_14
  • ADC_CHANNEL_15
  • ADC_CHANNEL_16
  • ADC_CHANNEL_17
  • ADC_CHANNEL_18
  • ADC_CHANNEL_VREFINT
  • ADC_CHANNEL_TEMPSENSOR
  • ADC_CHANNEL_VBAT
(7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
Return values:
Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.

Definition at line 1224 of file stm32wbxx_hal_adc.h.

#define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE | ( | __ADC_INSTANCE__,
 |  | __CHANNEL__
 | ) | __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))

Helper macro to determine whether the internal channel selected is available on the ADC instance selected.

Note:
The channel parameter must be a value defined from parameter definition of a ADC internal channel (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), must not be a value defined from parameter definition of ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) or a value from functions where a channel number is returned from ADC registers, because internal and external channels share the same channel number in ADC registers. The differentiation is made only with parameters definitions of driver.
Parameters:
__ADC_INSTANCE__ ADC instance
__CHANNEL__ This parameter can be one of the following values:
  • ADC_CHANNEL_VREFINT
  • ADC_CHANNEL_TEMPSENSOR
  • ADC_CHANNEL_VBAT
Return values:
Value "0" if the internal channel selected is not available on the ADC instance selected. Value "1" if the internal channel selected is available on the ADC instance selected.

Definition at line 1311 of file stm32wbxx_hal_adc.h.

#define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE ( __ADCXY_COMMON__ ) __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))

Helper macro to check if all ADC instances sharing the same ADC common instance are disabled.

Note:
This check is required by functions with setting conditioned to ADC state: All ADC instances of the ADC common group must be disabled. Refer to functions having argument "ADCxy_COMMON" as parameter.
On devices with only 1 ADC common instance, parameter of this macro is useless and can be ignored (parameter kept for compatibility with devices featuring several ADC common instances).
Parameters:
__ADCXY_COMMON__ ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
Value "0" if all ADC instances sharing the same ADC common instance are disabled. Value "1" if at least one ADC instance sharing the same ADC common instance is enabled.

Definition at line 1344 of file stm32wbxx_hal_adc.h.

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC Extended Private Constants

Defines
ADC Extended Private Constants
ADCEx

Defines

#define | ADC_JSQR_FIELDS
#define | ADC_CALIBRATION_TIMEOUT (158379UL)

Define Documentation

#define ADC_CALIBRATION_TIMEOUT (158379UL)

ADC calibration time-out value (unit: CPU cycles)

Definition at line 74 of file stm32wbxx_hal_adc_ex.c.

Referenced by HAL_ADCEx_Calibration_Start().

#define ADC_JSQR_FIELDS
Value:
((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
                           ADC_JSQR_JSQ1  | ADC_JSQR_JSQ2 |\
                           ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 ))

ADC_JSQR fields of parameters that can be updated anytime once the ADC is enabled

Definition at line 62 of file stm32wbxx_hal_adc_ex.c.

Referenced by HAL_ADCEx_InjectedConfigChannel().

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Extended Input and Output operation functions

Functions
Extended Input and Output operation functions
ADC Extended Exported Functions

Extended IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_ADCEx_Calibration_Start (ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
Perform an ADC automatic self-calibration Calibration prerequisite: ADC must be disabled (execute this function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
uint32_t | HAL_ADCEx_Calibration_GetValue (ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
Get the calibration factor.
HAL_StatusTypeDef | HAL_ADCEx_Calibration_SetValue (ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
Set the calibration factor to overwrite automatic conversion result.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of injected group.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels.
HAL_StatusTypeDef | HAL_ADCEx_InjectedPollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for injected group conversion to be completed.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart_IT (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of injected group with interruption.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop_IT (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels, disable interruption of end-of-conversion.
uint32_t | HAL_ADCEx_InjectedGetValue (ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
Get ADC injected group conversion result.
__weak void | HAL_ADCEx_InjectedConvCpltCallback (ADC_HandleTypeDef *hadc)
Injected conversion complete callback in non-blocking mode.
__weak void | HAL_ADCEx_InjectedQueueOverflowCallback (ADC_HandleTypeDef *hadc)
Injected context queue overflow callback.
__weak void | HAL_ADCEx_LevelOutOfWindow2Callback (ADC_HandleTypeDef *hadc)
Analog watchdog 2 callback in non-blocking mode.
__weak void | HAL_ADCEx_LevelOutOfWindow3Callback (ADC_HandleTypeDef *hadc)
Analog watchdog 3 callback in non-blocking mode.
__weak void | HAL_ADCEx_EndOfSamplingCallback (ADC_HandleTypeDef *hadc)
End Of Sampling callback in non-blocking mode.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral if no conversion is on going on injected group.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of ADC groups regular and injected, disable interrution of end-of-conversion, disable ADC peripheral if no conversion is on going on injected group.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral if no conversion is on going on injected group.

Detailed Description

Extended IO operation functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:

      (+) Perform the ADC self-calibration for single or differential ending.
      (+) Get calibration factors for single or differential ending.
      (+) Set calibration factors for single or differential ending.

      (+) Start conversion of ADC group injected.
      (+) Stop conversion of ADC group injected.
      (+) Poll for conversion complete on ADC group injected.
      (+) Get result of ADC group injected channel conversion.
      (+) Start conversion of ADC group injected and enable interruptions.
      (+) Stop conversion of ADC group injected and disable interruptions.

Function Documentation

uint32_t HAL_ADCEx_Calibration_GetValue | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | SingleDiff
 | ) |  |

Get the calibration factor.

Parameters:
hadc ADC handle.
SingleDiff This parameter can be only:
  • ADC_SINGLE_ENDED Channel in mode input single ended
  • ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
Return values:
Calibration value.

Definition at line 198 of file stm32wbxx_hal_adc_ex.c.

References assert_param, __ADC_HandleTypeDef::Instance, IS_ADC_SINGLE_DIFFERENTIAL, and LL_ADC_GetCalibrationFactor().

HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | SingleDiff,
 |  | uint32_t | CalibrationFactor
 | ) |  |

Set the calibration factor to overwrite automatic conversion result.

ADC must be enabled and no conversion is ongoing.

Parameters:
hadc | ADC handle
SingleDiff This parameter can be only:
  • ADC_SINGLE_ENDED Channel in mode input single ended
  • ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
CalibrationFactor | Calibration factor (coded on 7 bits maximum)
Return values:
HAL state

Definition at line 218 of file stm32wbxx_hal_adc_ex.c.

References assert_param, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_INTERNAL, HAL_ADC_STATE_ERROR_CONFIG, __ADC_HandleTypeDef::Instance, IS_ADC_CALFACT, IS_ADC_SINGLE_DIFFERENTIAL, LL_ADC_INJ_IsConversionOngoing(), LL_ADC_IsEnabled(), LL_ADC_REG_IsConversionOngoing(), LL_ADC_SetCalibrationFactor(), and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_Calibration_Start | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | SingleDiff
 | ) |  |

Perform an ADC automatic self-calibration Calibration prerequisite: ADC must be disabled (execute this function before HAL_ADC_Start() or after HAL_ADC_Stop() ).

Parameters:
hadc ADC handle
SingleDiff Selection of single-ended or differential input This parameter can be one of the following values:
  • ADC_SINGLE_ENDED Channel in mode input single ended
  • ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
Return values:
HAL status

Definition at line 124 of file stm32wbxx_hal_adc_ex.c.

References ADC_CALIBRATION_TIMEOUT, ADC_Disable(), ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, __ADC_HandleTypeDef::Instance, IS_ADC_SINGLE_DIFFERENTIAL, LL_ADC_IsCalibrationOnGoing(), LL_ADC_StartCalibration(), and __ADC_HandleTypeDef::State.

void HAL_ADCEx_EndOfSamplingCallback ( ADC_HandleTypeDef * hadc )

End Of Sampling callback in non-blocking mode.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 837 of file stm32wbxx_hal_adc_ex.c.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), and HAL_ADC_UnRegisterCallback().

void HAL_ADCEx_InjectedConvCpltCallback ( ADC_HandleTypeDef * hadc )

Injected conversion complete callback in non-blocking mode.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 772 of file stm32wbxx_hal_adc_ex.c.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), and HAL_ADC_UnRegisterCallback().

uint32_t HAL_ADCEx_InjectedGetValue | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | InjectedRank
 | ) |  |

Get ADC injected group conversion result.

Note:
Reading register JDRx automatically clears ADC flag JEOC (ADC group injected end of unitary conversion).
This function does not clear ADC flag JEOS (ADC group injected end of sequence conversion) Occurrence of flag JEOS rising:
  • If sequencer is composed of 1 rank, flag JEOS is equivalent to flag JEOC.
  • If sequencer is composed of several ranks, during the scan sequence flag JEOC only is raised, at the end of the scan sequence both flags JEOC and EOS are raised. Flag JEOS must not be cleared by this function because it would not be compliant with low power features (feature low power auto-wait, not available on all STM32 families). To clear this flag, either use function: in programming model IT: HAL_ADC_IRQHandler(), in programming model polling: HAL_ADCEx_InjectedPollForConversion() or __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
Parameters:
hadc ADC handle
InjectedRank the converted ADC injected rank. This parameter can be one of the following values:
  • ADC_INJECTED_RANK_1 ADC group injected rank 1
  • ADC_INJECTED_RANK_2 ADC group injected rank 2
  • ADC_INJECTED_RANK_3 ADC group injected rank 3
  • ADC_INJECTED_RANK_4 ADC group injected rank 4
Return values:
ADC group injected conversion data

Definition at line 737 of file stm32wbxx_hal_adc_ex.c.

References ADC_INJECTED_RANK_1, ADC_INJECTED_RANK_2, ADC_INJECTED_RANK_3, ADC_INJECTED_RANK_4, assert_param, __ADC_HandleTypeDef::Instance, and IS_ADC_INJECTED_RANK.

HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | Timeout
 | ) |  |

Wait for injected group conversion to be completed.

Parameters:
hadc | ADC handle
Timeout | Timeout value in millisecond.
Note:
Depending on hadc->Init.EOCSelection, JEOS or JEOC is checked and cleared depending on AUTDLY bit status.
Return values:
HAL status

Definition at line 425 of file stm32wbxx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_GET_FLAG, ADC_EOC_SEQ_CONV, ADC_FLAG_JEOC, ADC_FLAG_JEOS, assert_param, ADC_InitTypeDef::EOCSelection, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_TIMEOUT, HAL_GetTick(), __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, LL_ADC_INJ_IsTriggerSourceSWStart(), LL_ADC_REG_IsTriggerSourceSWStart(), and __ADC_HandleTypeDef::State.

void HAL_ADCEx_InjectedQueueOverflowCallback ( ADC_HandleTypeDef * hadc )

Injected context queue overflow callback.

Note:
This callback is called if injected context queue is enabled (parameter "QueueInjectedContext" in injected channel configuration) and if a new injected context is set when queue is full (maximum 2 contexts).
Parameters:
hadc ADC handle
Return values:
None

Definition at line 791 of file stm32wbxx_hal_adc_ex.c.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), and HAL_ADC_UnRegisterCallback().

HAL_StatusTypeDef HAL_ADCEx_InjectedStart ( ADC_HandleTypeDef * hadc )

Enable ADC, start conversion of injected group.

Note:
Interruptions enabled in this function: None.
Parameters:
hadc ADC handle.
Return values:
HAL status

Definition at line 269 of file stm32wbxx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, ADC_CLEAR_ERRORCODE, ADC_Enable(), ADC_FLAG_JEOC, ADC_FLAG_JEOS, ADC_STATE_CLR_SET, assert_param, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_JQOVF, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, __ADC_HandleTypeDef::Instance, LL_ADC_INJ_GetTrigAuto(), LL_ADC_INJ_IsConversionOngoing(), LL_ADC_INJ_StartConversion(), LL_ADC_INJ_TRIG_INDEPENDENT, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT ( ADC_HandleTypeDef * hadc )

Enable ADC, start conversion of injected group with interruption.

Note:
Interruptions enabled in this function according to initialization setting : JEOC (end of conversion) or JEOS (end of sequence)
Parameters:
hadc ADC handle.
Return values:
HAL status.

Definition at line 534 of file stm32wbxx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_DISABLE_IT, __HAL_ADC_ENABLE_IT, ADC_CLEAR_ERRORCODE, ADC_Enable(), ADC_EOC_SEQ_CONV, ADC_FLAG_JEOC, ADC_FLAG_JEOS, ADC_FLAG_JQOVF, ADC_IT_JEOC, ADC_IT_JEOS, ADC_STATE_CLR_SET, assert_param, ADC_InitTypeDef::EOCSelection, __ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_JQOVF, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, __ADC_HandleTypeDef::Init, __ADC_HandleTypeDef::Instance, LL_ADC_INJ_GetTrigAuto(), LL_ADC_INJ_IsConversionOngoing(), LL_ADC_INJ_StartConversion(), LL_ADC_INJ_TRIG_INDEPENDENT, and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_InjectedStop ( ADC_HandleTypeDef * hadc )

Stop conversion of injected channels.

Disable ADC peripheral if no regular conversion is on going.

Note:
If ADC must be disabled and if conversion is on going on regular group, function HAL_ADC_Stop must be used to stop both injected and regular groups, and disable the ADC.
If injected group mode auto-injection is enabled, function HAL_ADC_Stop must be used.
Parameters:
hadc ADC handle.
Return values:
HAL status

Definition at line 370 of file stm32wbxx_hal_adc_ex.c.

References ADC_ConversionStop(), ADC_Disable(), ADC_INJECTED_GROUP, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, __ADC_HandleTypeDef::Instance, LL_ADC_REG_IsConversionOngoing(), and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT ( ADC_HandleTypeDef * hadc )

Stop conversion of injected channels, disable interruption of end-of-conversion.

Disable ADC peripheral if no regular conversion is on going.

Note:
If ADC must be disabled and if conversion is on going on regular group, function HAL_ADC_Stop must be used to stop both injected and regular groups, and disable the ADC.
If injected group mode auto-injection is enabled, function HAL_ADC_Stop must be used.
In case of auto-injection mode, HAL_ADC_Stop() must be used.
Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 658 of file stm32wbxx_hal_adc_ex.c.

References __HAL_ADC_DISABLE_IT, ADC_ConversionStop(), ADC_Disable(), ADC_FLAG_JQOVF, ADC_INJECTED_GROUP, ADC_IT_JEOC, ADC_IT_JEOS, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, __ADC_HandleTypeDef::Instance, LL_ADC_REG_IsConversionOngoing(), and __ADC_HandleTypeDef::State.

void HAL_ADCEx_LevelOutOfWindow2Callback ( ADC_HandleTypeDef * hadc )

Analog watchdog 2 callback in non-blocking mode.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 806 of file stm32wbxx_hal_adc_ex.c.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), and HAL_ADC_UnRegisterCallback().

void HAL_ADCEx_LevelOutOfWindow3Callback ( ADC_HandleTypeDef * hadc )

Analog watchdog 3 callback in non-blocking mode.

Parameters:
hadc ADC handle
Return values:
None

Definition at line 821 of file stm32wbxx_hal_adc_ex.c.

Referenced by HAL_ADC_Init(), HAL_ADC_IRQHandler(), and HAL_ADC_UnRegisterCallback().

HAL_StatusTypeDef HAL_ADCEx_RegularStop ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral if no conversion is on going on injected group.

Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 854 of file stm32wbxx_hal_adc_ex.c.

References ADC_ConversionStop(), ADC_Disable(), ADC_REGULAR_GROUP, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, __ADC_HandleTypeDef::Instance, LL_ADC_INJ_IsConversionOngoing(), and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral if no conversion is on going on injected group.

Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 969 of file stm32wbxx_hal_adc_ex.c.

References __HAL_ADC_DISABLE_IT, ADC_ConversionStop(), ADC_Disable(), ADC_IT_OVR, ADC_REGULAR_GROUP, ADC_STATE_CLR_SET, assert_param, __ADC_HandleTypeDef::DMA_Handle, HAL_ADC_STATE_ERROR_DMA, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_DMA_Abort(), __ADC_HandleTypeDef::Instance, LL_ADC_INJ_IsConversionOngoing(), and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of ADC groups regular and injected, disable interrution of end-of-conversion, disable ADC peripheral if no conversion is on going on injected group.

Parameters:
hadc ADC handle
Return values:
HAL status.

Definition at line 912 of file stm32wbxx_hal_adc_ex.c.

References __HAL_ADC_DISABLE_IT, ADC_ConversionStop(), ADC_Disable(), ADC_IT_EOC, ADC_IT_EOS, ADC_IT_OVR, ADC_REGULAR_GROUP, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, __ADC_HandleTypeDef::Instance, LL_ADC_INJ_IsConversionOngoing(), and __ADC_HandleTypeDef::State.

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC Extended Peripheral Control functions

Functions
ADC Extended Peripheral Control functions
ADC Extended Exported Functions

ADC Extended Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_ADCEx_InjectedConfigChannel (ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected)
Configure a channel to be assigned to ADC group injected.
HAL_StatusTypeDef | HAL_ADCEx_EnableInjectedQueue (ADC_HandleTypeDef *hadc)
Enable Injected Queue.
HAL_StatusTypeDef | HAL_ADCEx_DisableInjectedQueue (ADC_HandleTypeDef *hadc)
Disable Injected Queue.
HAL_StatusTypeDef | HAL_ADCEx_DisableVoltageRegulator (ADC_HandleTypeDef *hadc)
Disable ADC voltage regulator.
HAL_StatusTypeDef | HAL_ADCEx_EnterADCDeepPowerDownMode (ADC_HandleTypeDef *hadc)
Enter ADC deep-power-down mode.

Detailed Description

ADC Extended Peripheral Control functions.

 ===============================================================================
             ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure channels on injected group
      (+) Enable or Disable Injected Queue
      (+) Disable ADC voltage regulator
      (+) Enter ADC deep-power-down mode

Function Documentation

HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue ( ADC_HandleTypeDef * hadc )

Disable Injected Queue.

Note:
This function sets CFGR register JQDIS bit in order to disable the Injected Queue. JQDIS can be written only when ADSTART and JDSTART are both equal to 0 to ensure that no regular nor injected conversion is ongoing.
Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 1560 of file stm32wbxx_hal_adc_ex.c.

References assert_param, __ADC_HandleTypeDef::Instance, LL_ADC_INJ_IsConversionOngoing(), LL_ADC_INJ_QUEUE_DISABLE, LL_ADC_INJ_SetQueueMode(), and LL_ADC_REG_IsConversionOngoing().

HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator ( ADC_HandleTypeDef * hadc )

Disable ADC voltage regulator.

Note:
Disabling voltage regulator allows to save power. This operation can be carried out only when ADC is disabled.
To enable again the voltage regulator, the user is expected to resort to HAL_ADC_Init() API.
Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 1597 of file stm32wbxx_hal_adc_ex.c.

References assert_param, __ADC_HandleTypeDef::Instance, LL_ADC_DisableInternalRegulator(), and LL_ADC_IsEnabled().

HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue ( ADC_HandleTypeDef * hadc )

Enable Injected Queue.

Note:
This function resets CFGR register JQDIS bit in order to enable the Injected Queue. JQDIS can be written only when ADSTART and JDSTART are both equal to 0 to ensure that no regular nor injected conversion is ongoing.
Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 1519 of file stm32wbxx_hal_adc_ex.c.

References assert_param, HAL_ADC_STATE_INJ_JQOVF, __ADC_HandleTypeDef::Instance, LL_ADC_INJ_IsConversionOngoing(), LL_ADC_REG_IsConversionOngoing(), and __ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode ( ADC_HandleTypeDef * hadc )

Enter ADC deep-power-down mode.

Note:
This mode is achieved in setting DEEPPWD bit and allows to save power in reducing leakage currents. It is particularly interesting before entering stop modes.
Setting DEEPPWD automatically clears ADVREGEN bit and disables the ADC voltage regulator. This means that this API encompasses HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal calibration is lost.
To exit the ADC deep-power-down mode, the user is expected to resort to HAL_ADC_Init() API as well as to relaunch a calibration with HAL_ADCEx_Calibration_Start() API or to re-apply a previously saved calibration factor.
Parameters:
hadc ADC handle
Return values:
HAL status

Definition at line 1634 of file stm32wbxx_hal_adc_ex.c.

References assert_param, __ADC_HandleTypeDef::Instance, LL_ADC_EnableDeepPowerDown(), and LL_ADC_IsEnabled().

HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel | ( | ADC_HandleTypeDef * | hadc,
 |  | ADC_InjectionConfTypeDef * | sConfigInjected
 | ) |  |

Configure a channel to be assigned to ADC group injected.

Note:
Possibility to update parameters on the fly: This function initializes injected group, following calls to this function can be used to reconfigure some parameters of structure "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC. The setting of these parameters is conditioned to ADC state: Refer to comments of structure "ADC_InjectionConfTypeDef".
In case of usage of internal measurement channels: Vbat/VrefInt/TempSensor. These internal paths can be disabled using function HAL_ADC_DeInit().
Caution: For Injected Context Queue use, a context must be fully defined before start of injected conversion. All channels are configured consecutively for the same ADC instance. Therefore, the number of calls to HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter InjectedNbrOfConversion for each context.
  • Example 1: If 1 context is intended to be used (or if there is no use of the Injected Queue Context feature) and if the context contains 3 injected ranks (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be called once for each channel (i.e. 3 times) before starting a conversion. This function must not be called to configure a 4th injected channel: it would start a new context into context queue.
  • Example 2: If 2 contexts are intended to be used and each of them contains 3 injected ranks (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and for each context (3 channels x 2 contexts = 6 calls). Conversion can start once the 1st context is set, that is after the first three HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly.
Parameters:
hadc | ADC handle
sConfigInjected | Structure of ADC injected group and ADC channel for injected group.
Return values:
HAL status

Definition at line 1097 of file stm32wbxx_hal_adc_ex.c.

References __LL_ADC_CHANNEL_TO_DECIMAL_NB, __LL_ADC_COMMON_INSTANCE, __LL_ADC_DECIMAL_NB_TO_CHANNEL, __LL_ADC_IS_CHANNEL_INTERNAL, __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE, ADC_BATTERY_VOLTAGE_INSTANCE, ADC_CFGR_INJECT_CONTEXT_QUEUE, ADC_CFGR_INJECT_DISCCONTINUOUS, ADC_CHANNEL_TEMPSENSOR, ADC_CHANNEL_VBAT, ADC_CHANNEL_VREFINT, ADC_DIFFERENTIAL_ENDED, ADC_EXTERNALTRIGINJECCONV_EDGE_NONE, ADC_GET_RESOLUTION, ADC_INJECTED_RANK_1, ADC_INJECTED_SOFTWARE_START, ADC_JSQR_FIELDS, ADC_JSQR_RK, ADC_OFFSET_NONE, ADC_OFFSET_SHIFT_RESOLUTION, ADC_SCAN_DISABLE, ADC_TEMPERATURE_SENSOR_INSTANCE, ADC_VREFINT_INSTANCE, assert_param, ADC_InjectionConfTypeDef::AutoInjectedConv, ADC_InjectionConfigTypeDef::ChannelCount, ADC_InjectionConfigTypeDef::ContextQueue, ADC_InitTypeDef::DiscontinuousConvMode, ADC_InjectionConfTypeDef::ExternalTrigInjecConv, ADC_InjectionConfTypeDef::ExternalTrigInjecConvEdge, HAL_ADC_STATE_ERROR_CONFIG, __ADC_HandleTypeDef::Init, ADC_InjectionConfTypeDef::InjecOversampling, ADC_InjectionConfTypeDef::InjecOversamplingMode, ADC_InjectionConfTypeDef::InjectedChannel, ADC_InjectionConfTypeDef::InjectedDiscontinuousConvMode, ADC_InjectionConfTypeDef::InjectedNbrOfConversion, ADC_InjectionConfTypeDef::InjectedOffset, ADC_InjectionConfTypeDef::InjectedOffsetNumber, ADC_InjectionConfTypeDef::InjectedRank, ADC_InjectionConfTypeDef::InjectedSamplingTime, ADC_InjectionConfTypeDef::InjectedSingleDiff, __ADC_HandleTypeDef::InjectionConfig, __ADC_HandleTypeDef::Instance, IS_ADC_CHANNEL, IS_ADC_DIFF_CHANNEL, IS_ADC_EXTTRIGINJEC, IS_ADC_EXTTRIGINJEC_EDGE, IS_ADC_INJECTED_NB_CONV, IS_ADC_INJECTED_RANK, IS_ADC_OFFSET_NUMBER, IS_ADC_OVERSAMPLING_RATIO, IS_ADC_RANGE, IS_ADC_RIGHT_BIT_SHIFT, IS_ADC_SAMPLE_TIME, IS_ADC_SINGLE_DIFFERENTIAL, LL_ADC_DELAY_TEMPSENSOR_STAB_US, LL_ADC_GetCommonPathInternalCh(), LL_ADC_GetOffsetChannel(), LL_ADC_INJ_IsConversionOngoing(), LL_ADC_IsEnabled(), LL_ADC_OFFSET_1, LL_ADC_OFFSET_2, LL_ADC_OFFSET_3, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE, LL_ADC_PATH_INTERNAL_TEMPSENSOR, LL_ADC_PATH_INTERNAL_VBAT, LL_ADC_PATH_INTERNAL_VREFINT, LL_ADC_REG_IsConversionOngoing(), LL_ADC_SetChannelSamplingTime(), LL_ADC_SetChannelSingleDiff(), LL_ADC_SetCommonPathInternalCh(), LL_ADC_SetOffset(), LL_ADC_SetOffsetState(), ADC_InjectionConfTypeDef::QueueInjectedContext, ADC_InjOversamplingTypeDef::Ratio, ADC_InjOversamplingTypeDef::RightBitShift, ADC_InitTypeDef::ScanConvMode, and __ADC_HandleTypeDef::State.

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC_InjOversamplingTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_InjOversamplingTypeDef Struct Reference
ADC Extended Exported Types

ADC Injected Conversion Oversampling structure definition. More...

#include <stm32wbxx_hal_adc_ex.h>

Data Fields

uint32_t | Ratio
uint32_t | RightBitShift

Detailed Description

ADC Injected Conversion Oversampling structure definition.

Definition at line 47 of file stm32wbxx_hal_adc_ex.h.

Field Documentation

uint32_t ADC_InjOversamplingTypeDef::Ratio

Configures the oversampling ratio. This parameter can be a value of Oversampling - Ratio

Definition at line 49 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjOversamplingTypeDef::RightBitShift

Configures the division coefficient for the Oversampler. This parameter can be a value of Oversampling - Data shift

Definition at line 52 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_adc_ex.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC_InjectionConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_InjectionConfTypeDef Struct Reference
ADC Extended Exported Types

Structure definition of ADC group injected and ADC channel affected to ADC group injected. More...

#include <stm32wbxx_hal_adc_ex.h>

Data Fields

uint32_t | InjectedChannel
uint32_t | InjectedRank
uint32_t | InjectedSamplingTime
uint32_t | InjectedSingleDiff
uint32_t | InjectedOffsetNumber
uint32_t | InjectedOffset
uint32_t | InjectedNbrOfConversion
FunctionalState | InjectedDiscontinuousConvMode
FunctionalState | AutoInjectedConv
FunctionalState | QueueInjectedContext
uint32_t | ExternalTrigInjecConv
uint32_t | ExternalTrigInjecConvEdge
FunctionalState | InjecOversamplingMode
ADC_InjOversamplingTypeDef InjecOversampling

Detailed Description

Structure definition of ADC group injected and ADC channel affected to ADC group injected.

Note:
Parameters of this structure are shared within 2 scopes:
  • Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset
  • Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling.
The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. ADC state can be either:
  • For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff')
  • For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group.
  • For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups.
  • For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going on ADC groups regular and injected. If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).

Definition at line 72 of file stm32wbxx_hal_adc_ex.h.

Field Documentation

FunctionalState ADC_InjectionConfTypeDef::AutoInjectedConv

Enables or disables the selected ADC group injected automatic conversion after regular one This parameter can be set to ENABLE or DISABLE. Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START) Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. To maintain JAUTO always enabled, DMA must be configured in circular mode. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 133 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::ExternalTrigInjecConv

Selects the external event used to trigger the conversion start of injected group. If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead. This parameter can be a value of ADC group injected trigger source. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 153 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::ExternalTrigInjecConvEdge

Selects the external trigger edge of injected group. This parameter can be a value of ADC group injected trigger edge (when external trigger is selected). If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 159 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

ADC_InjOversamplingTypeDef ADC_InjectionConfTypeDef::InjecOversampling

Specifies the Oversampling parameters. Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled. Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared).

Definition at line 169 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

FunctionalState ADC_InjectionConfTypeDef::InjecOversamplingMode

Specifies whether the oversampling feature is enabled or disabled. This parameter can be set to ENABLE or DISABLE. Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared).

Definition at line 165 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedChannel

Specifies the channel to configure into ADC group injected. This parameter can be a value of ADC instance - Channel number Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability.

Definition at line 74 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

FunctionalState ADC_InjectionConfTypeDef::InjectedDiscontinuousConvMode

Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. This parameter can be set to ENABLE or DISABLE. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank). Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 123 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedNbrOfConversion

Specifies the number of ranks that will be converted within the ADC group injected sequencer. To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 4. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 117 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedOffset

Defines the offset to be subtracted from the raw converted data. Offset value must be a positive number. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).

Definition at line 110 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedOffsetNumber

Selects the offset number. This parameter can be a value of ADC instance - Offset number. Caution: Only one offset is allowed per channel. This parameter overwrites the last setting.

Definition at line 106 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedRank

Specifies the rank in the ADC group injected sequencer. This parameter must be a value of ADC group injected - Sequencer ranks. Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions adjusted)

Definition at line 78 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedSamplingTime

Sampling time value to be set for the selected channel. Unit: ADC clock cycles. Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). This parameter can be a value of Channel - Sampling time. Caution: This parameter applies to a channel that can be used in a regular and/or injected group. It overwrites the last setting. Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) Refer to device datasheet for timings values.

Definition at line 83 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedSingleDiff

Selection of single-ended or differential input. In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input). Only channel 'i' has to be configured, channel 'i+1' is configured automatically. This parameter must be a value of Channel - Single or differential ending. Caution: This parameter applies to a channel that can be used in a regular and/or injected group. It overwrites the last setting. Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case of another parameter update on the fly)

Definition at line 94 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

FunctionalState ADC_InjectionConfTypeDef::QueueInjectedContext

Specifies whether the context queue feature is enabled. This parameter can be set to ENABLE or DISABLE. If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a new injected context is set when queue is full, error is triggered by interruption and through function 'HAL_ADCEx_InjectedQueueOverflowCallback'. Caution: This feature request that the sequence is fully configured before injected conversion start. Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).

Definition at line 142 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_adc_ex.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC group injected trigger source

Defines
ADC group injected trigger source
ADC Extended Exported Constants

Defines

#define | ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE)
#define | ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)
#define | ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)
#define | ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4)
#define | ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)
#define | ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1)
#define | ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)

Define Documentation

#define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)

ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting).

Definition at line 194 of file stm32wbxx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4)

ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 191 of file stm32wbxx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)

ADC group injected conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 189 of file stm32wbxx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)

ADC group injected conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting).

Definition at line 190 of file stm32wbxx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1)

ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 193 of file stm32wbxx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)

ADC group injected conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 192 of file stm32wbxx_hal_adc_ex.h.

#define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE)

Software triggers injected group conversion start

Definition at line 188 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC group injected trigger edge (when external trigger is selected)

Defines
ADC group injected trigger edge (when external trigger is selected)
ADC Extended Exported Constants

Defines

#define | ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL)
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0)
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1)
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN)

Define Documentation

#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1)

Injected conversions hardware trigger detection on the falling edge

Definition at line 204 of file stm32wbxx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL)

Injected conversions hardware trigger detection disabled

Definition at line 202 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0)

Injected conversions hardware trigger detection on the rising edge

Definition at line 203 of file stm32wbxx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN)

Injected conversions hardware trigger detection on both the rising and falling edges

Definition at line 205 of file stm32wbxx_hal_adc_ex.h.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Channel - Single or differential ending

Defines
Channel - Single or differential ending
ADC Extended Exported Constants

Defines

#define | ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED)
#define | ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED)

Define Documentation

#define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED)

ADC channel ending set to differential (literal also used to set calibration mode)

Definition at line 214 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED)

ADC channel ending set to single ended (literal also used to set calibration mode)

Definition at line 213 of file stm32wbxx_hal_adc_ex.h.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC instance - Offset number

Defines
ADC instance - Offset number
ADC Extended Exported Constants

Defines

#define | ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U)
#define | ADC_OFFSET_1 (LL_ADC_OFFSET_1)
#define | ADC_OFFSET_2 (LL_ADC_OFFSET_2)
#define | ADC_OFFSET_3 (LL_ADC_OFFSET_3)
#define | ADC_OFFSET_4 (LL_ADC_OFFSET_4)

Define Documentation

#define ADC_OFFSET_1 (LL_ADC_OFFSET_1)

ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)

Definition at line 223 of file stm32wbxx_hal_adc_ex.h.

#define ADC_OFFSET_2 (LL_ADC_OFFSET_2)

ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)

Definition at line 224 of file stm32wbxx_hal_adc_ex.h.

#define ADC_OFFSET_3 (LL_ADC_OFFSET_3)

ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)

Definition at line 225 of file stm32wbxx_hal_adc_ex.h.

#define ADC_OFFSET_4 (LL_ADC_OFFSET_4)

ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)

Definition at line 226 of file stm32wbxx_hal_adc_ex.h.

#define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U)

ADC offset disabled: no offset correction for the selected ADC channel

Definition at line 222 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC group injected - Sequencer ranks

Defines
ADC group injected - Sequencer ranks
ADC Extended Exported Constants

Defines

#define | ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1)
#define | ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2)
#define | ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3)
#define | ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4)

Define Documentation

#define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1)

ADC group injected sequencer rank 1

Definition at line 234 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel(), and HAL_ADCEx_InjectedGetValue().

#define ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2)

ADC group injected sequencer rank 2

Definition at line 235 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedGetValue().

#define ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3)

ADC group injected sequencer rank 3

Definition at line 236 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedGetValue().

#define ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4)

ADC group injected sequencer rank 4

Definition at line 237 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedGetValue().

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC instance - Groups

Defines
ADC instance - Groups
ADC Extended Exported Constants

Defines

#define | ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR)
#define | ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED)
#define | ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED)

Define Documentation

#define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED)

ADC group injected (not available on all STM32 devices)

Definition at line 246 of file stm32wbxx_hal_adc_ex.h.

Referenced by ADC_ConversionStop(), HAL_ADCEx_InjectedStop(), and HAL_ADCEx_InjectedStop_IT().

#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR)

ADC group regular (available on all STM32 devices)

Definition at line 245 of file stm32wbxx_hal_adc_ex.h.

Referenced by ADC_ConversionStop(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), and HAL_ADCEx_RegularStop_IT().

#define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED)

ADC both groups regular and injected

Definition at line 247 of file stm32wbxx_hal_adc_ex.h.

Referenced by ADC_ConversionStop(), HAL_ADC_DeInit(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), and HAL_ADC_Stop_IT().

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADCx CFGR fields

Defines
ADCx CFGR fields
ADC Extended Exported Constants

Defines

#define ADC_CFGR_FIELDS

Define Documentation

#define ADC_CFGR_FIELDS
Value:
(ADC_CFGR_AWD1CH  | ADC_CFGR_JAUTO   | ADC_CFGR_JAWD1EN |\
                            ADC_CFGR_AWD1EN  | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM     |\
                            ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN  |\
                            ADC_CFGR_AUTDLY  | ADC_CFGR_CONT    | ADC_CFGR_OVRMOD  |\
                            ADC_CFGR_EXTEN   | ADC_CFGR_EXTSEL  | ADC_CFGR_ALIGN   |\
                            ADC_CFGR_RES     | ADC_CFGR_DMACFG  | ADC_CFGR_DMAEN   )

Definition at line 255 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit().

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STM32WB55xx HAL User Manual: ADCx SMPR1 fields

Defines
ADCx SMPR1 fields
ADC Extended Exported Constants

Defines

#define ADC_SMPR1_FIELDS

Define Documentation

#define ADC_SMPR1_FIELDS
Value:
(ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\
                             ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\
                             ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\
                             ADC_SMPR1_SMP0)

Definition at line 268 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit().

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADCx CFGR sub fields

Defines
ADCx CFGR sub fields
ADC Extended Exported Constants

Defines

#define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY))

Define Documentation

#define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY))

Definition at line 281 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC Extended Private Macros

Defines
ADC Extended Private Macros
ADCEx

Defines

#define | ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL)
Test if conversion trigger of injected group is software start or external trigger.
#define | ADC_IS_INDEPENDENT(__HANDLE__) (SET)
Check whether or not ADC is independent.
#define | ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))
Set the selected injected Channel rank.
#define | ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos)
Configure ADC injected context queue.
#define | ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos)
Configure ADC discontinuous conversion mode for injected group.
#define | ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos)
Configure ADC discontinuous conversion mode for regular group.
#define | ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos)
Configure the number of discontinuous conversions for regular group.
#define | ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos)
Configure the ADC auto delay mode.
#define | ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos)
Configure ADC continuous conversion mode.
#define | ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CFGR_DMACFG_Pos)
Configure the ADC DMA continuous request.
#define | ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL))
Shift the offset with respect to the selected ADC resolution.
#define | ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL))
Shift the AWD1 threshold with respect to the selected ADC resolution.
#define | ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__)
Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution.
#define | ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__)
Clear Common Control Register.
#define | ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
Verify the ADC instance connected to the temperature sensor.
#define | ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
Verify the ADC instance connected to the battery voltage VBAT.
#define | ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
Verify the ADC instance connected to the internal voltage reference VREFINT.
#define | IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))
Verify the length of scheduled injected conversions group.
#define | IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
Calibration factor size verification (7 bits maximum).
#define | IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__)
Verify the ADC channel setting.
#define | IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__)
Verify the ADC channel setting in differential mode.
#define | IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__)
Verify the ADC single-ended input or differential mode setting.
#define | IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__)
Verify the ADC offset management setting.
#define | IS_ADC_INJECTED_RANK(__CHANNEL__)
Verify the ADC injected channel setting.
#define | IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__)
Verify the ADC injected conversions external trigger.
#define | IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__)
Verify the ADC edge trigger setting for injected group.
#define | IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__)
Verify the ADC analog watchdog setting.
#define | IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__)
Verify the ADC analog watchdog mode setting.
#define | IS_ADC_CONVERSION_GROUP(__CONVERSION__)
Verify the ADC conversion (regular or injected or both).
#define | IS_ADC_EVENT_TYPE(__EVENT__)
Verify the ADC event type.
#define | IS_ADC_OVERSAMPLING_RATIO(__RATIO__)
Verify the ADC oversampling ratio.
#define | IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__)
Verify the ADC oversampling shift.
#define | IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__)
Verify the ADC oversampling triggered mode.
#define | IS_ADC_REGOVERSAMPLING_MODE(__MODE__)
Verify the ADC oversampling regular conversion resumed or continued mode.
#define | IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET)
Verify the DFSDM mode configuration.
#define | ADC_CFGR_DFSDM(__HANDLE__) (0x0UL)
Return the DFSDM configuration mode.

Define Documentation

#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION | ( | __HANDLE__,
 |  | __THRESHOLD__
 | ) | ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL))

Shift the AWD1 threshold with respect to the selected ADC resolution.

Note:
Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0. If resolution 12 bits, no shift. If resolution 10 bits, shift of 2 ranks on the left. If resolution 8 bits, shift of 4 ranks on the left. If resolution 6 bits, shift of 6 ranks on the left. Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
Parameters:
__HANDLE__ | ADC handle
__THRESHOLD__ | Value to be shifted
Return values:
None

Definition at line 403 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION | ( | __HANDLE__,
 |  | __THRESHOLD__
 | ) |
Value:
((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0))                    ? \
   ((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \
   ((__THRESHOLD__) << 2UL)                                                                                 \
  )

Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution.

Note:
Thresholds have to be left-aligned on bit 7. If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded). If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded). If resolution 8 bits, no shift. If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0).
Parameters:
__HANDLE__ | ADC handle
__THRESHOLD__ | Value to be shifted
Return values:
None

Definition at line 417 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_BATTERY_VOLTAGE_INSTANCE ( __HANDLE__ ) (((__HANDLE__)->Instance) == ADC1)

Verify the ADC instance connected to the battery voltage VBAT.

Parameters:
__HANDLE__ ADC handle.
Return values:
SET (ADC instance is valid) or RESET (ADC instance is invalid)

Definition at line 447 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_CFGR_AUTOWAIT ( __AUTOWAIT__ ) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos)

Configure the ADC auto delay mode.

Parameters:
__AUTOWAIT__ Auto delay bit enable or disable.
Return values:
None

Definition at line 359 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define ADC_CFGR_CONTINUOUS ( __CONTINUOUS_MODE__ ) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos)

Configure ADC continuous conversion mode.

Parameters:
__CONTINUOUS_MODE__ Continuous mode.
Return values:
None

Definition at line 366 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define ADC_CFGR_DFSDM ( __HANDLE__ ) (0x0UL)

Return the DFSDM configuration mode.

Parameters:
__HANDLE__ ADC handle.
Note:
When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled). For this reason, the input parameter is the ADC handle and not the configuration parameter directly.
Return values:
DFSDM configuration mode

Definition at line 682 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define ADC_CFGR_DISCONTINUOUS_NUM ( __NBR_DISCONTINUOUS_CONV__ ) (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos)

Configure the number of discontinuous conversions for regular group.

Parameters:
__NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions.
Return values:
None

Definition at line 352 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define ADC_CFGR_DMACONTREQ ( __DMACONTREQ_MODE__ ) ((__DMACONTREQ_MODE__) << ADC_CFGR_DMACFG_Pos)

Configure the ADC DMA continuous request.

Parameters:
__DMACONTREQ_MODE__ DMA continuous request mode.
Return values:
None

Definition at line 373 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define ADC_CFGR_INJECT_CONTEXT_QUEUE ( __INJECT_CONTEXT_QUEUE_MODE__ ) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos)

Configure ADC injected context queue.

Parameters:
__INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode.
Return values:
None

Definition at line 331 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define ADC_CFGR_INJECT_DISCCONTINUOUS ( __INJECT_DISCONTINUOUS_MODE__ ) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos)

Configure ADC discontinuous conversion mode for injected group.

Parameters:
__INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode.
Return values:
None

Definition at line 338 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define ADC_CFGR_REG_DISCONTINUOUS ( __REG_DISCONTINUOUS_MODE__ ) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos)

Configure ADC discontinuous conversion mode for regular group.

Parameters:
__REG_DISCONTINUOUS_MODE__ Regular discontinuous mode.
Return values:
None

Definition at line 345 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define ADC_CLEAR_COMMON_CONTROL_REGISTER ( __HANDLE__ )
Value:
CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE | \
                                                                                ADC_CCR_PRESC  | \
                                                                                ADC_CCR_VBATEN | \
                                                                                ADC_CCR_TSEN   | \
                                                                                ADC_CCR_VREFEN )

Clear Common Control Register.

Parameters:
__HANDLE__ ADC handle.
Return values:
None

Definition at line 428 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADC_DeInit().

#define ADC_IS_INDEPENDENT ( __HANDLE__ ) (SET)

Check whether or not ADC is independent.

Parameters:
__HANDLE__ ADC handle.
Note:
When multimode feature is not available, the macro always returns SET.
Return values:
SET (ADC is independent) or RESET (ADC is not).

Definition at line 316 of file stm32wbxx_hal_adc_ex.h.

#define ADC_IS_SOFTWARE_START_INJECTED ( __HANDLE__ ) (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL)

Test if conversion trigger of injected group is software start or external trigger.

Parameters:
__HANDLE__ ADC handle.
Return values:
SET (software start) or RESET (external trigger).

Definition at line 307 of file stm32wbxx_hal_adc_ex.h.

#define ADC_JSQR_RK | ( | __CHANNELNB__,
 |  | __RANKNB__
 | ) | ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))

Set the selected injected Channel rank.

Parameters:
__CHANNELNB__ | Channel number.
__RANKNB__ | Rank number.
Return values:
None

Definition at line 324 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define ADC_OFFSET_SHIFT_RESOLUTION | ( | __HANDLE__,
 |  | __OFFSET__
 | ) | ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL))

Shift the offset with respect to the selected ADC resolution.

Note:
Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0. If resolution 12 bits, no shift. If resolution 10 bits, shift of 2 ranks on the left. If resolution 8 bits, shift of 4 ranks on the left. If resolution 6 bits, shift of 6 ranks on the left. Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
Parameters:
__HANDLE__ | ADC handle
__OFFSET__ | Value to be shifted
Return values:
None

Definition at line 388 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_TEMPERATURE_SENSOR_INSTANCE ( __HANDLE__ ) (((__HANDLE__)->Instance) == ADC1)

Verify the ADC instance connected to the temperature sensor.

Parameters:
__HANDLE__ ADC handle.
Return values:
SET (ADC instance is valid) or RESET (ADC instance is invalid)

Definition at line 440 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_VREFINT_INSTANCE ( __HANDLE__ ) (((__HANDLE__)->Instance) == ADC1)

Verify the ADC instance connected to the internal voltage reference VREFINT.

Parameters:
__HANDLE__ ADC handle.
Return values:
SET (ADC instance is valid) or RESET (ADC instance is invalid)

Definition at line 454 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_ANALOG_WATCHDOG_MODE ( __WATCHDOG_MODE__ )
Value:
(((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE)             || \
                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG)       || \
                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)     || \
                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)  || \
                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG)          || \
                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC)        || \
                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)       )

Verify the ADC analog watchdog mode setting.

Parameters:
__WATCHDOG_MODE__ programmed ADC analog watchdog mode setting.
Return values:
SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid)

Definition at line 590 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define IS_ADC_ANALOG_WATCHDOG_NUMBER ( __WATCHDOG__ )
Value:
(((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \
                                                     ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \
                                                     ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3)   )

Verify the ADC analog watchdog setting.

Parameters:
__WATCHDOG__ programmed ADC analog watchdog setting.
Return values:
SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid)

Definition at line 581 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define IS_ADC_CALFACT ( __CALIBRATION_FACTOR__ ) ((__CALIBRATION_FACTOR__) <= (0x7FU))

Calibration factor size verification (7 bits maximum).

Parameters:
__CALIBRATION_FACTOR__ Calibration factor value.
Return values:
SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)

Definition at line 468 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADCEx_Calibration_SetValue().

#define IS_ADC_CHANNEL | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
((((__HANDLE__)->Instance) == ADC1)  && \
                                                         (((__CHANNEL__) == ADC_CHANNEL_0)           || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_1)           || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_2)           || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_3)           || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_4)           || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_5)           || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_6)           || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_7)           || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_8)           || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_9)           || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_10)          || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_11)          || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_12)          || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_13)          || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_14)          || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_15)          || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_16)          || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_17)          || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_18)          || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_VREFINT)     || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR)  || \
                                                          ((__CHANNEL__) == ADC_CHANNEL_VBAT)))

Verify the ADC channel setting.

Parameters:
__HANDLE__ | ADC handle.
__CHANNEL__ | programmed ADC channel.
Return values:
SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)

Definition at line 477 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_CONVERSION_GROUP ( __CONVERSION__ )
Value:
(((__CONVERSION__) == ADC_REGULAR_GROUP)         || \
                                                 ((__CONVERSION__) == ADC_INJECTED_GROUP)        || \
                                                 ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP)  )

Verify the ADC conversion (regular or injected or both).

Parameters:
__CONVERSION__ ADC conversion group.
Return values:
SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid)

Definition at line 603 of file stm32wbxx_hal_adc_ex.h.

Referenced by ADC_ConversionStop().

#define IS_ADC_DFSDMCFG_MODE ( __HANDLE__ ) (SET)

Verify the DFSDM mode configuration.

Parameters:
__HANDLE__ ADC handle.
Note:
When DMSDFM configuration is not supported, the macro systematically reports SET. For this reason, the input parameter is the ADC handle and not the configuration parameter directly.
Return values:
SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid)

Definition at line 672 of file stm32wbxx_hal_adc_ex.h.

#define IS_ADC_DIFF_CHANNEL | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == ADC_CHANNEL_1)      || \
                                                      ((__CHANNEL__) == ADC_CHANNEL_2)      || \
                                                      ((__CHANNEL__) == ADC_CHANNEL_3)      || \
                                                      ((__CHANNEL__) == ADC_CHANNEL_4)      || \
                                                      ((__CHANNEL__) == ADC_CHANNEL_5)      || \
                                                      ((__CHANNEL__) == ADC_CHANNEL_6)      || \
                                                      ((__CHANNEL__) == ADC_CHANNEL_7)      || \
                                                      ((__CHANNEL__) == ADC_CHANNEL_8)      || \
                                                      ((__CHANNEL__) == ADC_CHANNEL_9)      || \
                                                      ((__CHANNEL__) == ADC_CHANNEL_10)     || \
                                                      ((__CHANNEL__) == ADC_CHANNEL_11)     || \
                                                      ((__CHANNEL__) == ADC_CHANNEL_12)     || \
                                                      ((__CHANNEL__) == ADC_CHANNEL_13)     || \
                                                      ((__CHANNEL__) == ADC_CHANNEL_14)     || \
                                                      ((__CHANNEL__) == ADC_CHANNEL_15)       )

Verify the ADC channel setting in differential mode.

Parameters:
__HANDLE__ | ADC handle.
__CHANNEL__ | programmed ADC channel.
Return values:
SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)

Definition at line 507 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_EVENT_TYPE ( __EVENT__ )
Value:
(((__EVENT__) == ADC_EOSMP_EVENT)  || \
                                      ((__EVENT__) == ADC_AWD_EVENT)    || \
                                      ((__EVENT__) == ADC_AWD2_EVENT)   || \
                                      ((__EVENT__) == ADC_AWD3_EVENT)   || \
                                      ((__EVENT__) == ADC_OVR_EVENT)    || \
                                      ((__EVENT__) == ADC_JQOVF_EVENT)  )

Verify the ADC event type.

Parameters:
__EVENT__ ADC event.
Return values:
SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid)

Definition at line 612 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADC_PollForEvent().

#define IS_ADC_EXTTRIGINJEC | ( | __HANDLE__,
 |  | __INJTRIG__
 | ) |
Value:
(((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO)     || \
                                                      ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4)      || \
                                                      ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO)     || \
                                                      ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1)      || \
                                                      ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15)    || \
                                                      ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2)    || \
                                                      ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START)       )

Verify the ADC injected conversions external trigger.

Parameters:
__HANDLE__ | ADC handle.
__INJTRIG__ | programmed ADC injected conversions external trigger.
Return values:
SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid)

Definition at line 558 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_EXTTRIGINJEC_EDGE ( __EDGE__ )
Value:
(((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)         || \
                                            ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING)       || \
                                            ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING)      || \
                                            ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )

Verify the ADC edge trigger setting for injected group.

Parameters:
__EDGE__ programmed ADC edge trigger setting.
Return values:
SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)

Definition at line 571 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_INJECTED_NB_CONV ( __LENGTH__ ) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))

Verify the length of scheduled injected conversions group.

Parameters:
__LENGTH__ number of programmed conversions.
Return values:
SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large)

Definition at line 461 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_INJECTED_RANK ( __CHANNEL__ )
Value:
(((__CHANNEL__) == ADC_INJECTED_RANK_1) || \
                                           ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \
                                           ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \
                                           ((__CHANNEL__) == ADC_INJECTED_RANK_4)   )

Verify the ADC injected channel setting.

Parameters:
__CHANNEL__ programmed ADC injected channel.
Return values:
SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)

Definition at line 547 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel(), and HAL_ADCEx_InjectedGetValue().

#define IS_ADC_OFFSET_NUMBER ( __OFFSET_NUMBER__ )
Value:
(((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \
                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_1)    || \
                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_2)    || \
                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_3)    || \
                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_4)      )

Verify the ADC offset management setting.

Parameters:
__OFFSET_NUMBER__ ADC offset management.
Return values:
SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid)

Definition at line 536 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_OVERSAMPLING_RATIO ( __RATIO__ )
Value:
(((__RATIO__) == ADC_OVERSAMPLING_RATIO_2   ) || \
                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4   ) || \
                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8   ) || \
                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16  ) || \
                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32  ) || \
                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64  ) || \
                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \
                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 ))

Verify the ADC oversampling ratio.

Parameters:
__RATIO__ programmed ADC oversampling ratio.
Return values:
SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid)

Definition at line 624 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_REGOVERSAMPLING_MODE ( __MODE__ )
Value:
(((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \
                                               ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) )

Verify the ADC oversampling regular conversion resumed or continued mode.

Parameters:
__MODE__ programmed ADC oversampling regular conversion resumed or continued mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 661 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_RIGHT_BIT_SHIFT ( __SHIFT__ )
Value:
(((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_1   ) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_2   ) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_3   ) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_4   ) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_5   ) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_6   ) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_7   ) || \
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_8   ))

Verify the ADC oversampling shift.

Parameters:
__SHIFT__ programmed ADC oversampling shift.
Return values:
SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)

Definition at line 638 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_SINGLE_DIFFERENTIAL ( __SING_DIFF__ )
Value:
(((__SING_DIFF__) == ADC_SINGLE_ENDED)      || \
                                                   ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED)  )

Verify the ADC single-ended input or differential mode setting.

Parameters:
__SING_DIFF__ programmed channel setting.
Return values:
SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid)

Definition at line 528 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADC_ConfigChannel(), HAL_ADCEx_Calibration_GetValue(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_Calibration_Start(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE ( __MODE__ )
Value:
(((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
                                                      ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )

Verify the ADC oversampling triggered mode.

Parameters:
__MODE__ programmed ADC oversampling triggered mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 653 of file stm32wbxx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization/de-initialization functions

Functions
Initialization/de-initialization functions
COMP Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_COMP_Init (COMP_HandleTypeDef *hcomp)
Initialize the COMP according to the specified parameters in the COMP_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP peripheral.
__weak void | HAL_COMP_MspInit (COMP_HandleTypeDef *hcomp)
Initialize the COMP MSP.
__weak void | HAL_COMP_MspDeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP MSP.
HAL_StatusTypeDef | HAL_COMP_RegisterCallback (COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback)
Register a User COMP Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_COMP_UnRegisterCallback (COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID)
Unregister a COMP Callback COMP callback is redirected to the weak predefined callback.

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions to initialize and de-initialize comparators

Function Documentation

HAL_StatusTypeDef HAL_COMP_DeInit ( COMP_HandleTypeDef * hcomp )

DeInitialize the COMP peripheral.

Note:
Deinitialization cannot be performed if the COMP configuration is locked. To unlock the configuration, perform a system reset.
Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 422 of file stm32wbxx_hal_comp.c.

References __HAL_COMP_IS_LOCKED, assert_param, HAL_COMP_MspDeInit(), HAL_COMP_STATE_RESET, __COMP_HandleTypeDef::Instance, __COMP_HandleTypeDef::MspDeInitCallback, and __COMP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_COMP_Init ( COMP_HandleTypeDef * hcomp )

Initialize the COMP according to the specified parameters in the COMP_InitTypeDef and initialize the associated handle.

Note:
If the selected comparator is locked, initialization can't be performed. To unlock the configuration, perform a system reset.
Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 233 of file stm32wbxx_hal_comp.c.

References __HAL_COMP_IS_LOCKED, assert_param, COMP_InitTypeDef::BlankingSrce, COMP_CLEAR_ERRORCODE, COMP_DELAY_VOLTAGE_SCALER_STAB_US, COMP_EXTI_EVENT, COMP_EXTI_FALLING, COMP_EXTI_IT, COMP_EXTI_RISING, COMP_GET_EXTI_LINE, COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON, HAL_COMP_MspInit(), HAL_COMP_STATE_READY, HAL_COMP_STATE_RESET, HAL_COMP_TriggerCallback(), COMP_InitTypeDef::Hysteresis, __COMP_HandleTypeDef::Init, COMP_InitTypeDef::InputMinus, COMP_InitTypeDef::InputPlus, __COMP_HandleTypeDef::Instance, IS_COMP_BLANKINGSRC_INSTANCE, IS_COMP_HYSTERESIS, IS_COMP_INPUT_MINUS, IS_COMP_INPUT_PLUS, IS_COMP_OUTPUTPOL, IS_COMP_POWERMODE, IS_COMP_TRIGGERMODE, IS_COMP_WINDOWMODE, LL_EXTI_ClearFlag_0_31(), LL_EXTI_DisableEvent_0_31(), LL_EXTI_DisableFallingTrig_0_31(), LL_EXTI_DisableIT_0_31(), LL_EXTI_DisableRisingTrig_0_31(), LL_EXTI_EnableEvent_0_31(), LL_EXTI_EnableFallingTrig_0_31(), LL_EXTI_EnableIT_0_31(), LL_EXTI_EnableRisingTrig_0_31(), __COMP_HandleTypeDef::Lock, COMP_InitTypeDef::Mode, __COMP_HandleTypeDef::MspInitCallback, COMP_InitTypeDef::OutputPol, __COMP_HandleTypeDef::State, __COMP_HandleTypeDef::TriggerCallback, COMP_InitTypeDef::TriggerMode, and COMP_InitTypeDef::WindowMode.

void HAL_COMP_MspDeInit ( COMP_HandleTypeDef * hcomp )

DeInitialize the COMP MSP.

Parameters:
hcomp COMP handle
Return values:
None

Definition at line 486 of file stm32wbxx_hal_comp.c.

Referenced by HAL_COMP_DeInit(), and HAL_COMP_UnRegisterCallback().

void HAL_COMP_MspInit ( COMP_HandleTypeDef * hcomp )

Initialize the COMP MSP.

Parameters:
hcomp COMP handle
Return values:
None

Definition at line 471 of file stm32wbxx_hal_comp.c.

Referenced by HAL_COMP_Init(), and HAL_COMP_UnRegisterCallback().

HAL_StatusTypeDef HAL_COMP_RegisterCallback | ( | COMP_HandleTypeDef * | hcomp,
 |  | HAL_COMP_CallbackIDTypeDef | CallbackID,
 |  | pCOMP_CallbackTypeDef | pCallback
 | ) |  |

Register a User COMP Callback To be used instead of the weak predefined callback.

Parameters:
hcomp | Pointer to a COMP_HandleTypeDef structure that contains the configuration information for the specified COMP.
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_COMP_TRIGGER_CB_ID Trigger callback ID
  • HAL_COMP_MSPINIT_CB_ID MspInit callback ID
  • HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 510 of file stm32wbxx_hal_comp.c.

References __COMP_HandleTypeDef::ErrorCode, HAL_COMP_ERROR_INVALID_CALLBACK, HAL_COMP_MSPDEINIT_CB_ID, HAL_COMP_MSPINIT_CB_ID, HAL_COMP_STATE_READY, HAL_COMP_STATE_RESET, HAL_COMP_TRIGGER_CB_ID, __COMP_HandleTypeDef::MspDeInitCallback, __COMP_HandleTypeDef::MspInitCallback, __COMP_HandleTypeDef::State, and __COMP_HandleTypeDef::TriggerCallback.

HAL_StatusTypeDef HAL_COMP_UnRegisterCallback | ( | COMP_HandleTypeDef * | hcomp,
 |  | HAL_COMP_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a COMP Callback COMP callback is redirected to the weak predefined callback.

Parameters:
hcomp Pointer to a COMP_HandleTypeDef structure that contains the configuration information for the specified COMP.
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_COMP_TRIGGER_CB_ID Trigger callback ID
  • HAL_COMP_MSPINIT_CB_ID MspInit callback ID
  • HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
HAL status

Definition at line 592 of file stm32wbxx_hal_comp.c.

References __COMP_HandleTypeDef::ErrorCode, HAL_COMP_ERROR_INVALID_CALLBACK, HAL_COMP_MspDeInit(), HAL_COMP_MSPDEINIT_CB_ID, HAL_COMP_MspInit(), HAL_COMP_MSPINIT_CB_ID, HAL_COMP_STATE_READY, HAL_COMP_STATE_RESET, HAL_COMP_TRIGGER_CB_ID, HAL_COMP_TriggerCallback(), __COMP_HandleTypeDef::MspDeInitCallback, __COMP_HandleTypeDef::MspInitCallback, __COMP_HandleTypeDef::State, and __COMP_HandleTypeDef::TriggerCallback.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Start-Stop operation functions

Functions
Start-Stop operation functions
COMP Exported Functions

Start-Stop operation functions. More...

Functions

HAL_StatusTypeDef | HAL_COMP_Start (COMP_HandleTypeDef *hcomp)
Start the comparator.
HAL_StatusTypeDef | HAL_COMP_Stop (COMP_HandleTypeDef *hcomp)
Stop the comparator.
void | HAL_COMP_IRQHandler (COMP_HandleTypeDef *hcomp)
Comparator IRQ handler.

Detailed Description

Start-Stop operation functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Start a comparator instance.
      (+) Stop a comparator instance.

Function Documentation

void HAL_COMP_IRQHandler ( COMP_HandleTypeDef * hcomp )

Comparator IRQ handler.

Parameters:
hcomp COMP handle
Return values:
None

Definition at line 774 of file stm32wbxx_hal_comp.c.

References COMP_EXTI_LINE_COMP1, COMP_EXTI_LINE_COMP2, COMP_GET_EXTI_LINE, HAL_COMP_TriggerCallback(), __COMP_HandleTypeDef::Instance, LL_EXTI_ClearFlag_0_31(), LL_EXTI_IsActiveFlag_0_31(), and __COMP_HandleTypeDef::TriggerCallback.

HAL_StatusTypeDef HAL_COMP_Start ( COMP_HandleTypeDef * hcomp )

Start the comparator.

Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 680 of file stm32wbxx_hal_comp.c.

References __HAL_COMP_IS_LOCKED, assert_param, COMP_DELAY_STARTUP_US, HAL_COMP_STATE_BUSY, HAL_COMP_STATE_READY, __COMP_HandleTypeDef::Instance, and __COMP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_COMP_Stop ( COMP_HandleTypeDef * hcomp )

Stop the comparator.

Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 732 of file stm32wbxx_hal_comp.c.

References __HAL_COMP_IS_LOCKED, assert_param, HAL_COMP_STATE_READY, HAL_COMP_STATE_RESET, __COMP_HandleTypeDef::Instance, and __COMP_HandleTypeDef::State.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
COMP Exported Functions

Management functions. More...

Functions

HAL_StatusTypeDef | HAL_COMP_Lock (COMP_HandleTypeDef *hcomp)
Lock the selected comparator configuration.
uint32_t | HAL_COMP_GetOutputLevel (COMP_HandleTypeDef *hcomp)
Return the output level (high or low) of the selected comparator.
__weak void | HAL_COMP_TriggerCallback (COMP_HandleTypeDef *hcomp)
Comparator trigger callback.

Detailed Description

Management functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the comparators.

Function Documentation

uint32_t HAL_COMP_GetOutputLevel ( COMP_HandleTypeDef * hcomp )

Return the output level (high or low) of the selected comparator.

The output level depends on the selected polarity. If the polarity is not inverted:

  • Comparator output is low when the input plus is at a lower voltage than the input minus
  • Comparator output is high when the input plus is at a higher voltage than the input minus If the polarity is inverted:
  • Comparator output is high when the input plus is at a lower voltage than the input minus
  • Comparator output is low when the input plus is at a higher voltage than the input minus
    Parameters:
    hcomp COMP handle
    Return values:
    Returns the selected comparator output level:
    • COMP_OUTPUT_LEVEL_LOW
    • COMP_OUTPUT_LEVEL_HIGH

Definition at line 896 of file stm32wbxx_hal_comp.c.

References assert_param, COMP_OUTPUT_LEVEL_BITOFFSET_POS, and __COMP_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_COMP_Lock ( COMP_HandleTypeDef * hcomp )

Lock the selected comparator configuration.

Note:
A system reset is required to unlock the comparator configuration.
Locking the comparator from reset state is possible if __HAL_RCC_SYSCFG_CLK_ENABLE() is being called before.
Parameters:
hcomp COMP handle
Return values:
HAL status

Definition at line 835 of file stm32wbxx_hal_comp.c.

References __HAL_COMP_IS_LOCKED, __HAL_COMP_LOCK, assert_param, HAL_COMP_STATE_BUSY_LOCKED, HAL_COMP_STATE_READY, HAL_COMP_STATE_READY_LOCKED, HAL_COMP_STATE_RESET, HAL_COMP_STATE_RESET_LOCKED, __COMP_HandleTypeDef::Instance, and __COMP_HandleTypeDef::State.

void HAL_COMP_TriggerCallback ( COMP_HandleTypeDef * hcomp )

Comparator trigger callback.

Parameters:
hcomp COMP handle
Return values:
None

Definition at line 910 of file stm32wbxx_hal_comp.c.

Referenced by HAL_COMP_Init(), HAL_COMP_IRQHandler(), and HAL_COMP_UnRegisterCallback().

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
COMP Exported Functions

Peripheral State functions. More...

Functions

HAL_COMP_StateTypeDef | HAL_COMP_GetState (COMP_HandleTypeDef *hcomp)
Return the COMP handle state.
uint32_t | HAL_COMP_GetError (COMP_HandleTypeDef *hcomp)
Return the COMP error code.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permit to get in run-time the status of the peripheral.

Function Documentation

uint32_t HAL_COMP_GetError ( COMP_HandleTypeDef * hcomp )

Return the COMP error code.

Parameters:
hcomp COMP handle
Return values:
COMP error code

Definition at line 964 of file stm32wbxx_hal_comp.c.

References assert_param, __COMP_HandleTypeDef::ErrorCode, and __COMP_HandleTypeDef::Instance.

HAL_COMP_StateTypeDef HAL_COMP_GetState ( COMP_HandleTypeDef * hcomp )

Return the COMP handle state.

Parameters:
hcomp COMP handle
Return values:
HAL state

Definition at line 944 of file stm32wbxx_hal_comp.c.

References assert_param, HAL_COMP_STATE_RESET, __COMP_HandleTypeDef::Instance, and __COMP_HandleTypeDef::State.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: COMP Exported Types

Data Structures | Defines | Typedefs | Enumerations
COMP Exported Types
COMP

Data Structures

struct | COMP_InitTypeDef
COMP Init structure definition. More...
struct | __COMP_HandleTypeDef
COMP Handle Structure definition. More...

Defines

#define | COMP_STATE_BITFIELD_LOCK (0x10U)
HAL COMP state machine: HAL COMP states definition.

Typedefs

typedef struct __COMP_HandleTypeDef | COMP_HandleTypeDef
COMP Handle Structure definition.
typedef void(* | pCOMP_CallbackTypeDef )(COMP_HandleTypeDef *hcomp)
HAL COMP Callback pointer definition.

Enumerations

enum HAL_COMP_StateTypeDef {
HAL_COMP_STATE_RESET = 0x00U, HAL_COMP_STATE_RESET_LOCKED = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), HAL_COMP_STATE_READY = 0x01U, HAL_COMP_STATE_READY_LOCKED = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK),
HAL_COMP_STATE_BUSY = 0x02U, HAL_COMP_STATE_BUSY_LOCKED = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK)
}
enum | HAL_COMP_CallbackIDTypeDef { HAL_COMP_TRIGGER_CB_ID = 0x00U, HAL_COMP_MSPINIT_CB_ID = 0x01U, HAL_COMP_MSPDEINIT_CB_ID = 0x02U }
HAL COMP Callback ID enumeration definition. More...

Define Documentation

#define COMP_STATE_BITFIELD_LOCK (0x10U)

HAL COMP state machine: HAL COMP states definition.

Definition at line 85 of file stm32wbxx_hal_comp.h.

Typedef Documentation

typedef struct __COMP_HandleTypeDef COMP_HandleTypeDef

COMP Handle Structure definition.

typedef void(* pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp)

HAL COMP Callback pointer definition.

pointer to a COMP callback function

Definition at line 131 of file stm32wbxx_hal_comp.h.

Enumeration Type Documentation

enum HAL_COMP_CallbackIDTypeDef

HAL COMP Callback ID enumeration definition.

Enumerator:
HAL_COMP_TRIGGER_CB_ID

COMP trigger callback ID

HAL_COMP_MSPINIT_CB_ID

COMP Msp Init callback ID

HAL_COMP_MSPDEINIT_CB_ID

COMP Msp DeInit callback ID

Definition at line 121 of file stm32wbxx_hal_comp.h.

enum HAL_COMP_StateTypeDef
Enumerator:
HAL_COMP_STATE_RESET

COMP not yet initialized

HAL_COMP_STATE_RESET_LOCKED

COMP not yet initialized and configuration is locked

HAL_COMP_STATE_READY

COMP initialized and ready for use

HAL_COMP_STATE_READY_LOCKED

COMP initialized but configuration is locked

HAL_COMP_STATE_BUSY

COMP is running

HAL_COMP_STATE_BUSY_LOCKED

COMP is running and configuration is locked

Definition at line 86 of file stm32wbxx_hal_comp.h.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: COMP_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
COMP_InitTypeDef Struct Reference
COMP Exported Types

COMP Init structure definition. More...

#include <stm32wbxx_hal_comp.h>

Data Fields

uint32_t | WindowMode
uint32_t | Mode
uint32_t | InputPlus
uint32_t | InputMinus
uint32_t | Hysteresis
uint32_t | OutputPol
uint32_t | BlankingSrce
uint32_t | TriggerMode

Detailed Description

COMP Init structure definition.

Definition at line 49 of file stm32wbxx_hal_comp.h.

Field Documentation

uint32_t COMP_InitTypeDef::BlankingSrce

Set comparator blanking source. This parameter can be a value of COMP blanking source

Definition at line 74 of file stm32wbxx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::Hysteresis

Set comparator hysteresis mode of the input minus. This parameter can be a value of COMP hysteresis

Definition at line 68 of file stm32wbxx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::InputMinus

Set comparator input minus (inverting input). This parameter can be a value of COMP input minus (inverting input)

Definition at line 65 of file stm32wbxx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::InputPlus

Set comparator input plus (non-inverting input). This parameter can be a value of COMP input plus (non-inverting input)

Definition at line 62 of file stm32wbxx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::Mode

Set comparator operating mode to adjust power and speed. Note: For the characteristics of comparator power modes (propagation delay and power consumption), refer to device datasheet. This parameter can be a value of COMP power mode

Definition at line 57 of file stm32wbxx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::OutputPol

Set comparator output polarity. This parameter can be a value of COMP output Polarity

Definition at line 71 of file stm32wbxx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::TriggerMode

Set the comparator output triggering External Interrupt Line (EXTI). This parameter can be a value of COMP output to EXTI

Definition at line 77 of file stm32wbxx_hal_comp.h.

Referenced by HAL_COMP_Init().

uint32_t COMP_InitTypeDef::WindowMode

Set window mode of a pair of comparators instances (2 consecutive instances odd and even COMP<x> and COMP<x+1>). Note: HAL COMP driver allows to set window mode from any COMP instance of the pair of COMP instances composing window mode. This parameter can be a value of COMP Window Mode

Definition at line 52 of file stm32wbxx_hal_comp.h.

Referenced by HAL_COMP_Init().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_comp.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: __COMP_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__COMP_HandleTypeDef Struct Reference
COMP Exported Types

COMP Handle Structure definition. More...

#include <stm32wbxx_hal_comp.h>

Data Fields

COMP_TypeDef * | Instance
COMP_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_COMP_StateTypeDef | State
__IO uint32_t | ErrorCode
void(* | TriggerCallback )(struct __COMP_HandleTypeDef *hcomp)
void(* | MspInitCallback )(struct __COMP_HandleTypeDef *hcomp)
void(* | MspDeInitCallback )(struct __COMP_HandleTypeDef *hcomp)

Detailed Description

COMP Handle Structure definition.

Definition at line 100 of file stm32wbxx_hal_comp.h.

Field Documentation

__IO uint32_t __COMP_HandleTypeDef::ErrorCode

COMP error code

Definition at line 109 of file stm32wbxx_hal_comp.h.

Referenced by HAL_COMP_GetError(), HAL_COMP_RegisterCallback(), and HAL_COMP_UnRegisterCallback().

COMP_InitTypeDef __COMP_HandleTypeDef::Init

COMP required parameters

Definition at line 106 of file stm32wbxx_hal_comp.h.

Referenced by HAL_COMP_Init().

COMP_TypeDef* __COMP_HandleTypeDef::Instance

Register base address

Definition at line 105 of file stm32wbxx_hal_comp.h.

Referenced by HAL_COMP_DeInit(), HAL_COMP_GetError(), HAL_COMP_GetOutputLevel(), HAL_COMP_GetState(), HAL_COMP_Init(), HAL_COMP_IRQHandler(), HAL_COMP_Lock(), HAL_COMP_Start(), and HAL_COMP_Stop().

HAL_LockTypeDef __COMP_HandleTypeDef::Lock

Locking object

Definition at line 107 of file stm32wbxx_hal_comp.h.

Referenced by HAL_COMP_Init().

void(* __COMP_HandleTypeDef::MspDeInitCallback)(struct __COMP_HandleTypeDef *hcomp)

COMP Msp DeInit callback

Definition at line 113 of file stm32wbxx_hal_comp.h.

Referenced by HAL_COMP_DeInit(), HAL_COMP_RegisterCallback(), and HAL_COMP_UnRegisterCallback().

void(* __COMP_HandleTypeDef::MspInitCallback)(struct __COMP_HandleTypeDef *hcomp)

COMP Msp Init callback

Definition at line 112 of file stm32wbxx_hal_comp.h.

Referenced by HAL_COMP_Init(), HAL_COMP_RegisterCallback(), and HAL_COMP_UnRegisterCallback().

__IO HAL_COMP_StateTypeDef __COMP_HandleTypeDef::State

COMP communication state

Definition at line 108 of file stm32wbxx_hal_comp.h.

Referenced by HAL_COMP_DeInit(), HAL_COMP_GetState(), HAL_COMP_Init(), HAL_COMP_Lock(), HAL_COMP_RegisterCallback(), HAL_COMP_Start(), HAL_COMP_Stop(), and HAL_COMP_UnRegisterCallback().

void(* __COMP_HandleTypeDef::TriggerCallback)(struct __COMP_HandleTypeDef *hcomp)

COMP trigger callback

Definition at line 111 of file stm32wbxx_hal_comp.h.

Referenced by HAL_COMP_Init(), HAL_COMP_IRQHandler(), HAL_COMP_RegisterCallback(), and HAL_COMP_UnRegisterCallback().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_comp.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: COMP Error Code

Defines
COMP Error Code
COMP Exported Constants

Defines

#define | HAL_COMP_ERROR_NONE (0x00UL)
#define | HAL_COMP_ERROR_INVALID_CALLBACK (0x01UL)

Define Documentation

#define HAL_COMP_ERROR_INVALID_CALLBACK (0x01UL)

Invalid Callback error

Definition at line 149 of file stm32wbxx_hal_comp.h.

Referenced by HAL_COMP_RegisterCallback(), and HAL_COMP_UnRegisterCallback().

#define HAL_COMP_ERROR_NONE (0x00UL)

No error

Definition at line 147 of file stm32wbxx_hal_comp.h.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: COMP Window Mode

Defines
COMP Window Mode
COMP Exported Constants

Defines

#define | COMP_WINDOWMODE_DISABLE (0x00000000UL)
#define | COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE)

Define Documentation

#define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE)

Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible).

Definition at line 159 of file stm32wbxx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define COMP_WINDOWMODE_DISABLE (0x00000000UL)

Window mode disable: Comparators instances pair COMP1 and COMP2 are independent

Definition at line 158 of file stm32wbxx_hal_comp.h.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: COMP power mode

Defines
COMP power mode
COMP Exported Constants

Defines

#define | COMP_POWERMODE_HIGHSPEED (0x00000000UL)
#define | COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0)
#define | COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_PWRMODE)

Define Documentation

#define COMP_POWERMODE_HIGHSPEED (0x00000000UL)

High Speed

Definition at line 170 of file stm32wbxx_hal_comp.h.

#define COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0)

Medium Speed

Definition at line 171 of file stm32wbxx_hal_comp.h.

#define COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_PWRMODE)

Ultra-low power mode

Definition at line 172 of file stm32wbxx_hal_comp.h.

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STM32WB55xx HAL User Manual: COMP input plus (non-inverting input)

Defines
COMP input plus (non-inverting input)
COMP Exported Constants

Defines

#define | COMP_INPUT_PLUS_IO1 (0x00000000UL)
#define | COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0)
#define | COMP_INPUT_PLUS_IO3 (COMP_CSR_INPSEL_1)

Define Documentation

#define COMP_INPUT_PLUS_IO1 (0x00000000UL)

Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2)

Definition at line 180 of file stm32wbxx_hal_comp.h.

#define COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0)

Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2)

Definition at line 181 of file stm32wbxx_hal_comp.h.

#define COMP_INPUT_PLUS_IO3 (COMP_CSR_INPSEL_1)

Comparator input plus connected to IO3 (pin PA1 for COMP1, pin PA3 for COMP2)

Definition at line 183 of file stm32wbxx_hal_comp.h.

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STM32WB55xx HAL User Manual: COMP input minus (inverting input)

Defines
COMP input minus (inverting input)
COMP Exported Constants

Defines

#define | COMP_INPUT_MINUS_1_4VREFINT ( COMP_CSR_SCALEN | COMP_CSR_BRGEN)
#define | COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)
#define | COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)
#define | COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN )
#define | COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 )
#define | COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)
#define | COMP_INPUT_MINUS_IO3 ( COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)
#define | COMP_INPUT_MINUS_IO4 (COMP_CSR_INMESEL_1 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)
#define | COMP_INPUT_MINUS_IO5 (COMP_CSR_INMESEL_1 | COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)

Define Documentation

#define COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)

Comparator input minus connected to 1/2 VrefInt

Definition at line 193 of file stm32wbxx_hal_comp.h.

#define COMP_INPUT_MINUS_1_4VREFINT ( COMP_CSR_SCALEN | COMP_CSR_BRGEN)

Comparator input minus connected to 1/4 VrefInt

Definition at line 192 of file stm32wbxx_hal_comp.h.

#define COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)

Comparator input minus connected to 3/4 VrefInt

Definition at line 194 of file stm32wbxx_hal_comp.h.

#define COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 )

Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB3 for COMP2)

Definition at line 196 of file stm32wbxx_hal_comp.h.

#define COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)

Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PB7 for COMP2)

Definition at line 197 of file stm32wbxx_hal_comp.h.

#define COMP_INPUT_MINUS_IO3 ( COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)

Comparator input minus connected to IO3 (pin PA0 for COMP1, pin PA2 for COMP2)

Definition at line 198 of file stm32wbxx_hal_comp.h.

#define COMP_INPUT_MINUS_IO4 (COMP_CSR_INMESEL_1 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)

Comparator input minus connected to IO4 (pin PA4 for COMP1, pin PA4 for COMP2)

Definition at line 199 of file stm32wbxx_hal_comp.h.

#define COMP_INPUT_MINUS_IO5 (COMP_CSR_INMESEL_1 | COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)

Comparator input minus connected to IO5 (pin PA5 for COMP1, pin PA5 for COMP2)

Definition at line 200 of file stm32wbxx_hal_comp.h.

#define COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN )

Comparator input minus connected to VrefInt

Definition at line 195 of file stm32wbxx_hal_comp.h.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: COMP hysteresis

Defines
COMP hysteresis
COMP Exported Constants

Defines

#define | COMP_HYSTERESIS_NONE (0x00000000UL)
#define | COMP_HYSTERESIS_LOW ( COMP_CSR_HYST_0)
#define | COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1 )
#define | COMP_HYSTERESIS_HIGH (COMP_CSR_HYST_1 | COMP_CSR_HYST_0)

Define Documentation

#define COMP_HYSTERESIS_HIGH (COMP_CSR_HYST_1 | COMP_CSR_HYST_0)

Hysteresis level high

Definition at line 211 of file stm32wbxx_hal_comp.h.

#define COMP_HYSTERESIS_LOW ( COMP_CSR_HYST_0)

Hysteresis level low

Definition at line 209 of file stm32wbxx_hal_comp.h.

#define COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1 )

Hysteresis level medium

Definition at line 210 of file stm32wbxx_hal_comp.h.

#define COMP_HYSTERESIS_NONE (0x00000000UL)

No hysteresis

Definition at line 208 of file stm32wbxx_hal_comp.h.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: COMP output Polarity

Defines
COMP output Polarity
COMP Exported Constants

Defines

#define | COMP_OUTPUTPOL_NONINVERTED (0x00000000UL)
#define | COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY)

Define Documentation

#define COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY)

COMP output level is inverted (comparator output is low when the input plus is at a higher voltage than the input minus)

Definition at line 220 of file stm32wbxx_hal_comp.h.

#define COMP_OUTPUTPOL_NONINVERTED (0x00000000UL)

COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus)

Definition at line 219 of file stm32wbxx_hal_comp.h.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: COMP blanking source

Defines
COMP blanking source
COMP Exported Constants

Defines

#define | COMP_BLANKINGSRC_NONE (0x00000000UL)
#define | COMP_BLANKINGSRC_TIM1_OC5 (COMP_CSR_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM2_OC3 (COMP_CSR_BLANKING_1)

Define Documentation

#define COMP_BLANKINGSRC_NONE (0x00000000UL)

Comparator output without blanking

Definition at line 228 of file stm32wbxx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM1_OC5 (COMP_CSR_BLANKING_0)

Comparator output blanking source TIM1 OC5 (common to all COMP instances: COMP1, COMP2)

Definition at line 230 of file stm32wbxx_hal_comp.h.

#define COMP_BLANKINGSRC_TIM2_OC3 (COMP_CSR_BLANKING_1)

Comparator output blanking source TIM2 OC3 (common to all COMP instances: COMP1, COMP2)

Definition at line 231 of file stm32wbxx_hal_comp.h.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: COMP Output Level

Defines
COMP Output Level
COMP Exported Constants

Defines

#define | COMP_OUTPUT_LEVEL_LOW (0x00000000UL)
#define | COMP_OUTPUT_LEVEL_HIGH (0x00000001UL)

Define Documentation

#define COMP_OUTPUT_LEVEL_HIGH (0x00000001UL)

Definition at line 248 of file stm32wbxx_hal_comp.h.

#define COMP_OUTPUT_LEVEL_LOW (0x00000000UL)

Definition at line 245 of file stm32wbxx_hal_comp.h.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: COMP output to EXTI

Defines
COMP output to EXTI
COMP Exported Constants

Defines

#define | COMP_TRIGGERMODE_NONE (0x00000000UL)
#define | COMP_TRIGGERMODE_IT_RISING (COMP_EXTI_IT | COMP_EXTI_RISING)
#define | COMP_TRIGGERMODE_IT_FALLING (COMP_EXTI_IT | COMP_EXTI_FALLING)
#define | COMP_TRIGGERMODE_IT_RISING_FALLING (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING)
#define | COMP_TRIGGERMODE_EVENT_RISING (COMP_EXTI_EVENT | COMP_EXTI_RISING)
#define | COMP_TRIGGERMODE_EVENT_FALLING (COMP_EXTI_EVENT | COMP_EXTI_FALLING)
#define | COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING)

Define Documentation

#define COMP_TRIGGERMODE_EVENT_FALLING (COMP_EXTI_EVENT | COMP_EXTI_FALLING)

Comparator output triggering External Interrupt Line event only (without interruption), on falling edge

Definition at line 261 of file stm32wbxx_hal_comp.h.

#define COMP_TRIGGERMODE_EVENT_RISING (COMP_EXTI_EVENT | COMP_EXTI_RISING)

Comparator output triggering External Interrupt Line event only (without interruption), on rising edge

Definition at line 260 of file stm32wbxx_hal_comp.h.

#define COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING)

Comparator output triggering External Interrupt Line event only (without interruption), on both rising and falling edges

Definition at line 262 of file stm32wbxx_hal_comp.h.

#define COMP_TRIGGERMODE_IT_FALLING (COMP_EXTI_IT | COMP_EXTI_FALLING)

Comparator output triggering External Interrupt Line event with interruption, on falling edge

Definition at line 258 of file stm32wbxx_hal_comp.h.

#define COMP_TRIGGERMODE_IT_RISING (COMP_EXTI_IT | COMP_EXTI_RISING)

Comparator output triggering External Interrupt Line event with interruption, on rising edge

Definition at line 257 of file stm32wbxx_hal_comp.h.

#define COMP_TRIGGERMODE_IT_RISING_FALLING (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING)

Comparator output triggering External Interrupt Line event with interruption, on both rising and falling edges

Definition at line 259 of file stm32wbxx_hal_comp.h.

#define COMP_TRIGGERMODE_NONE (0x00000000UL)

Comparator output triggering no External Interrupt Line

Definition at line 256 of file stm32wbxx_hal_comp.h.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: COMP Handle Management

Defines
COMP Handle Management
COMP Exported Macros

Defines

#define | __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__)
Reset COMP handle state.
#define | COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE)
Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE").
#define | __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
Enable the specified comparator.
#define | __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
Disable the specified comparator.
#define | __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK)
Lock the specified comparator configuration.
#define | __HAL_COMP_IS_LOCKED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK)
Check whether the specified comparator is locked.

Define Documentation

#define __HAL_COMP_DISABLE ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)

Disable the specified comparator.

Parameters:
__HANDLE__ COMP handle
Return values:
None

Definition at line 313 of file stm32wbxx_hal_comp.h.

#define __HAL_COMP_ENABLE ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)

Enable the specified comparator.

Parameters:
__HANDLE__ COMP handle
Return values:
None

Definition at line 306 of file stm32wbxx_hal_comp.h.

#define __HAL_COMP_IS_LOCKED ( __HANDLE__ ) (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK)

Check whether the specified comparator is locked.

Parameters:
__HANDLE__ COMP handle
Return values:
Value 0 if COMP instance is not locked, value 1 if COMP instance is locked

Definition at line 331 of file stm32wbxx_hal_comp.h.

Referenced by HAL_COMP_DeInit(), HAL_COMP_Init(), HAL_COMP_Lock(), HAL_COMP_Start(), and HAL_COMP_Stop().

#define __HAL_COMP_LOCK ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK)

Lock the specified comparator configuration.

Note:
Using this macro induce HAL COMP handle state machine being no more in line with COMP instance state. To keep HAL COMP handle state machine updated, it is recommended to use function "HAL_COMP_Lock')".
Parameters:
__HANDLE__ COMP handle
Return values:
None

Definition at line 324 of file stm32wbxx_hal_comp.h.

Referenced by HAL_COMP_Lock().

#define __HAL_COMP_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                  \
                                                      (__HANDLE__)->State = HAL_COMP_STATE_RESET;      \
                                                      (__HANDLE__)->MspInitCallback = NULL;            \
                                                      (__HANDLE__)->MspDeInitCallback = NULL;          \
                                                    } while(0)

Reset COMP handle state.

Parameters:
__HANDLE__ COMP handle
Return values:
None

Definition at line 285 of file stm32wbxx_hal_comp.h.

#define COMP_CLEAR_ERRORCODE ( __HANDLE__ ) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE)

Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE").

Parameters:
__HANDLE__ COMP handle
Return values:
None

Definition at line 299 of file stm32wbxx_hal_comp.h.

Referenced by HAL_COMP_Init().

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: COMP external interrupt line management

Defines
COMP external interrupt line management
COMP Exported Macros

Defines

#define | __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the COMP1 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the COMP1 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP1)
Generate a software interrupt on the COMP1 EXTI line.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line in event mode.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line in event mode.
#define | __HAL_COMP_COMP1_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP1)
Check whether the COMP1 EXTI line flag is set.
#define | __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP1)
Clear the COMP1 EXTI flag.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the COMP2 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the COMP2 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP2)
Generate a software interrupt on the COMP2 EXTI line.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line in event mode.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line in event mode.
#define | __HAL_COMP_COMP2_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP2)
Check whether the COMP2 EXTI line flag is set.
#define | __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP2)
Clear the COMP2 EXTI flag.

Define Documentation

#define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG ( ) LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP1)

Clear the COMP1 EXTI flag.

Return values:
None

Definition at line 423 of file stm32wbxx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT ( ) LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP1)

Disable the COMP1 EXTI line in event mode.

Return values:
None

Definition at line 411 of file stm32wbxx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE ( ) LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)

Disable the COMP1 EXTI line falling edge trigger.

Return values:
None

Definition at line 363 of file stm32wbxx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_DISABLE_IT ( ) LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP1)

Disable the COMP1 EXTI line in interrupt mode.

Return values:
None

Definition at line 393 of file stm32wbxx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE ( ) LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)

Disable the COMP1 EXTI line rising edge trigger.

Return values:
None

Definition at line 351 of file stm32wbxx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                               LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \
                                                               LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \
                                                             } while(0)

Disable the COMP1 EXTI line rising & falling edge trigger.

Return values:
None

Definition at line 378 of file stm32wbxx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT ( ) LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP1)

Enable the COMP1 EXTI line in event mode.

Return values:
None

Definition at line 405 of file stm32wbxx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE ( ) LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)

Enable the COMP1 EXTI line falling edge trigger.

Return values:
None

Definition at line 357 of file stm32wbxx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_ENABLE_IT ( ) LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP1)

Enable the COMP1 EXTI line in interrupt mode.

Return values:
None

Definition at line 387 of file stm32wbxx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE ( ) LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)

Enable the COMP1 EXTI line rising edge trigger.

Return values:
None

Definition at line 345 of file stm32wbxx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                               LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \
                                                               LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \
                                                             } while(0)

Enable the COMP1 EXTI line rising & falling edge trigger.

Return values:
None

Definition at line 369 of file stm32wbxx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT ( ) LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP1)

Generate a software interrupt on the COMP1 EXTI line.

Return values:
None

Definition at line 399 of file stm32wbxx_hal_comp.h.

#define __HAL_COMP_COMP1_EXTI_GET_FLAG ( ) LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP1)

Check whether the COMP1 EXTI line flag is set.

Return values:
RESET or SET

Definition at line 417 of file stm32wbxx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG ( ) LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP2)

Clear the COMP2 EXTI flag.

Return values:
None

Definition at line 507 of file stm32wbxx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT ( ) LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP2)

Disable the COMP2 EXTI line in event mode.

Return values:
None

Definition at line 495 of file stm32wbxx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE ( ) LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)

Disable the COMP2 EXTI line falling edge trigger.

Return values:
None

Definition at line 447 of file stm32wbxx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_DISABLE_IT ( ) LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP2)

Disable the COMP2 EXTI line in interrupt mode.

Return values:
None

Definition at line 477 of file stm32wbxx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE ( ) LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)

Disable the COMP2 EXTI line rising edge trigger.

Return values:
None

Definition at line 435 of file stm32wbxx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                               LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \
                                                               LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \
                                                             } while(0)

Disable the COMP2 EXTI line rising & falling edge trigger.

Return values:
None

Definition at line 462 of file stm32wbxx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT ( ) LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP2)

Enable the COMP2 EXTI line in event mode.

Return values:
None

Definition at line 489 of file stm32wbxx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE ( ) LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)

Enable the COMP2 EXTI line falling edge trigger.

Return values:
None

Definition at line 441 of file stm32wbxx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_ENABLE_IT ( ) LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP2)

Enable the COMP2 EXTI line in interrupt mode.

Return values:
None

Definition at line 471 of file stm32wbxx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE ( ) LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)

Enable the COMP2 EXTI line rising edge trigger.

Return values:
None

Definition at line 429 of file stm32wbxx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                               LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \
                                                               LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \
                                                             } while(0)

Enable the COMP2 EXTI line rising & falling edge trigger.

Return values:
None

Definition at line 453 of file stm32wbxx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT ( ) LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP2)

Generate a software interrupt on the COMP2 EXTI line.

Return values:
None

Definition at line 483 of file stm32wbxx_hal_comp.h.

#define __HAL_COMP_COMP2_EXTI_GET_FLAG ( ) LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP2)

Check whether the COMP2 EXTI line flag is set.

Return values:
RESET or SET

Definition at line 501 of file stm32wbxx_hal_comp.h.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: COMP EXTI Lines

Defines
COMP EXTI Lines
COMP Private Constants

Defines

#define | COMP_EXTI_LINE_COMP1 (LL_EXTI_LINE_20)
#define | COMP_EXTI_LINE_COMP2 (LL_EXTI_LINE_21)
#define | COMP_EXTI_IT (0x00000001UL)
#define | COMP_EXTI_EVENT (0x00000002UL)
#define | COMP_EXTI_RISING (0x00000010UL)
#define | COMP_EXTI_FALLING (0x00000020UL)

Define Documentation

#define COMP_EXTI_EVENT (0x00000002UL)

EXTI line event only (without interruption)

Definition at line 537 of file stm32wbxx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define COMP_EXTI_FALLING (0x00000020UL)

EXTI line event on falling edge

Definition at line 539 of file stm32wbxx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define COMP_EXTI_IT (0x00000001UL)

EXTI line event with interruption

Definition at line 536 of file stm32wbxx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define COMP_EXTI_LINE_COMP1 (LL_EXTI_LINE_20)

EXTI line 20 connected to COMP1 output

Definition at line 527 of file stm32wbxx_hal_comp.h.

Referenced by HAL_COMP_IRQHandler().

#define COMP_EXTI_LINE_COMP2 (LL_EXTI_LINE_21)

EXTI line 21 connected to COMP2 output

Definition at line 528 of file stm32wbxx_hal_comp.h.

Referenced by HAL_COMP_IRQHandler().

#define COMP_EXTI_RISING (0x00000010UL)

EXTI line event on rising edge

Definition at line 538 of file stm32wbxx_hal_comp.h.

Referenced by HAL_COMP_Init().

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: COMP Private Constants

Modules | Defines
COMP Private Constants
COMP

Modules

COMP EXTI Lines

Defines

#define | COMP_DELAY_STARTUP_US (80UL)
#define | COMP_DELAY_VOLTAGE_SCALER_STAB_US (200UL)
#define | COMP_OUTPUT_LEVEL_BITOFFSET_POS (30UL)

Define Documentation

#define COMP_DELAY_STARTUP_US (80UL)

Delay for COMP startup time

Definition at line 189 of file stm32wbxx_hal_comp.c.

Referenced by HAL_COMP_Start().

#define COMP_DELAY_VOLTAGE_SCALER_STAB_US (200UL)

Delay for COMP voltage scaler stabilization time

Definition at line 195 of file stm32wbxx_hal_comp.c.

Referenced by HAL_COMP_Init().

#define COMP_OUTPUT_LEVEL_BITOFFSET_POS (30UL)

Definition at line 197 of file stm32wbxx_hal_comp.c.

Referenced by HAL_COMP_GetOutputLevel().

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: COMP private macros to get EXTI line associated with comparators

Defines
COMP private macros to get EXTI line associated with comparators
COMP Private Macros

Defines

#define COMP_GET_EXTI_LINE(__INSTANCE__)
Get the specified EXTI line for a comparator instance.

Define Documentation

#define COMP_GET_EXTI_LINE ( __INSTANCE__ )
Value:
(((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1  \
                                             : COMP_EXTI_LINE_COMP2)

Get the specified EXTI line for a comparator instance.

Parameters:
__INSTANCE__ specifies the COMP instance.
Return values:
value of COMP EXTI Lines

Definition at line 561 of file stm32wbxx_hal_comp.h.

Referenced by HAL_COMP_Init(), and HAL_COMP_IRQHandler().

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: COMP private macros to check input parameters

Defines
COMP private macros to check input parameters
COMP Private Macros

Defines

#define | IS_COMP_WINDOWMODE(__WINDOWMODE__)
#define | IS_COMP_POWERMODE(__POWERMODE__)
#define | IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)
#define | IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)
#define | IS_COMP_HYSTERESIS(__HYSTERESIS__)
#define | IS_COMP_OUTPUTPOL(__POL__)
#define | IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__)
#define | IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) (IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__))
#define | IS_COMP_TRIGGERMODE(__MODE__)
#define | IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__)

Define Documentation

#define IS_COMP_BLANKINGSRC_INSTANCE | ( | __INSTANCE__,
 |  | __OUTPUT_BLANKING_SOURCE__
 | ) | (IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__))

Definition at line 611 of file stm32wbxx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_BLANKINGSRCE ( __OUTPUT_BLANKING_SOURCE__ )
Value:
(   ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)               \
   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5)           \
   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3)           \
  )

Definition at line 603 of file stm32wbxx_hal_comp.h.

#define IS_COMP_HYSTERESIS ( __HYSTERESIS__ )
Value:
(((__HYSTERESIS__) == COMP_HYSTERESIS_NONE)   || \
                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_LOW)    || \
                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_MEDIUM) || \
                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_HIGH))

Definition at line 595 of file stm32wbxx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_INPUT_MINUS | ( | __COMP_INSTANCE__,
 |  | __INPUT_MINUS__
 | ) |
Value:
(((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT)  || \
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT)  || \
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT)  || \
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT)     || \
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1)         || \
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2)         || \
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO3)         || \
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO4)         || \
                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO5))

Definition at line 585 of file stm32wbxx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_INPUT_PLUS | ( | __COMP_INSTANCE__,
 |  | __INPUT_PLUS__
 | ) |
Value:
(((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \
                                                               ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2) || \
                                                               ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO3))

Definition at line 577 of file stm32wbxx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_OUTPUT_LEVEL ( __OUTPUT_LEVEL__ )
Value:
(((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_LOW)     || \
                                                ((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_HIGH))

Definition at line 623 of file stm32wbxx_hal_comp.h.

#define IS_COMP_OUTPUTPOL ( __POL__ )
Value:
(((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \
                                             ((__POL__) == COMP_OUTPUTPOL_INVERTED))

Definition at line 600 of file stm32wbxx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_POWERMODE ( __POWERMODE__ )
Value:
(((__POWERMODE__) == COMP_POWERMODE_HIGHSPEED)    || \
                                             ((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED)  || \
                                             ((__POWERMODE__) == COMP_POWERMODE_ULTRALOWPOWER)  )

Definition at line 573 of file stm32wbxx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_TRIGGERMODE ( __MODE__ )
Value:
(((__MODE__) == COMP_TRIGGERMODE_NONE)                 || \
                                             ((__MODE__) == COMP_TRIGGERMODE_IT_RISING)            || \
                                             ((__MODE__) == COMP_TRIGGERMODE_IT_FALLING)           || \
                                             ((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING)    || \
                                             ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING)         || \
                                             ((__MODE__) == COMP_TRIGGERMODE_EVENT_FALLING)        || \
                                             ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING))

Definition at line 615 of file stm32wbxx_hal_comp.h.

Referenced by HAL_COMP_Init().

#define IS_COMP_WINDOWMODE ( __WINDOWMODE__ )
Value:
(((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE)                || \
                                             ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)  )

Definition at line 570 of file stm32wbxx_hal_comp.h.

Referenced by HAL_COMP_Init().

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: MPU_Region_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
MPU_Region_InitTypeDef Struct Reference
MPU Region Initialization Structure Definition

#include <stm32wbxx_hal_cortex.h>

Data Fields

uint8_t | Enable
uint8_t | Number
uint32_t | BaseAddress
uint8_t | Size
uint8_t | SubRegionDisable
uint8_t | TypeExtField
uint8_t | AccessPermission
uint8_t | DisableExec
uint8_t | IsShareable
uint8_t | IsCacheable
uint8_t | IsBufferable

Detailed Description

Definition at line 50 of file stm32wbxx_hal_cortex.h.

Field Documentation

uint8_t MPU_Region_InitTypeDef::AccessPermission

Specifies the region access permission type. This parameter can be a value of CORTEX MPU Region Permission Attributes

Definition at line 64 of file stm32wbxx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint32_t MPU_Region_InitTypeDef::BaseAddress

Specifies the base address of the region to protect.

Definition at line 56 of file stm32wbxx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::DisableExec

Specifies the instruction access status. This parameter can be a value of CORTEX MPU Instruction Access

Definition at line 66 of file stm32wbxx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::Enable

Specifies the status of the region. This parameter can be a value of CORTEX MPU Region Enable

Definition at line 52 of file stm32wbxx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::IsBufferable

Specifies the bufferable status of the protected region. This parameter can be a value of CORTEX MPU Instruction Access Bufferable

Definition at line 72 of file stm32wbxx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::IsCacheable

Specifies the cacheable status of the region protected. This parameter can be a value of CORTEX MPU Instruction Access Cacheable

Definition at line 70 of file stm32wbxx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::IsShareable

Specifies the shareability status of the protected region. This parameter can be a value of CORTEX MPU Instruction Access Shareable

Definition at line 68 of file stm32wbxx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::Number

Specifies the number of the region to protect. This parameter can be a value of CORTEX MPU Region Number

Definition at line 54 of file stm32wbxx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::Size

Specifies the size of the region to protect. This parameter can be a value of CORTEX MPU Region Size

Definition at line 58 of file stm32wbxx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::SubRegionDisable

Specifies the number of the subregion protection to disable. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF

Definition at line 60 of file stm32wbxx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

uint8_t MPU_Region_InitTypeDef::TypeExtField

Specifies the TEX field level. This parameter can be a value of CORTEX MPU TEX Levels

Definition at line 62 of file stm32wbxx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_cortex.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CORTEX Preemption Priority Group

Defines
CORTEX Preemption Priority Group
CORTEX Exported Constants

Defines

#define | NVIC_PRIORITYGROUP_0 (0x00000007U)
#define | NVIC_PRIORITYGROUP_1 (0x00000006U)
#define | NVIC_PRIORITYGROUP_2 (0x00000005U)
#define | NVIC_PRIORITYGROUP_3 (0x00000004U)
#define | NVIC_PRIORITYGROUP_4 (0x00000003U)

Define Documentation

#define NVIC_PRIORITYGROUP_0 (0x00000007U)

0 bit for pre-emption priority, 4 bits for subpriority

Definition at line 92 of file stm32wbxx_hal_cortex.h.

#define NVIC_PRIORITYGROUP_1 (0x00000006U)

1 bit for pre-emption priority, 3 bits for subpriority

Definition at line 94 of file stm32wbxx_hal_cortex.h.

#define NVIC_PRIORITYGROUP_2 (0x00000005U)

2 bits for pre-emption priority, 2 bits for subpriority

Definition at line 96 of file stm32wbxx_hal_cortex.h.

#define NVIC_PRIORITYGROUP_3 (0x00000004U)

3 bits for pre-emption priority, 1 bit for subpriority

Definition at line 98 of file stm32wbxx_hal_cortex.h.

#define NVIC_PRIORITYGROUP_4 (0x00000003U)

4 bits for pre-emption priority, 0 bit for subpriority

Definition at line 100 of file stm32wbxx_hal_cortex.h.

Referenced by HAL_Init().

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CORTEX SysTick clock source

Defines
CORTEX SysTick clock source
CORTEX Exported Constants

Defines

#define | SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
#define | SYSTICK_CLKSOURCE_HCLK 0x00000004U

Define Documentation

#define SYSTICK_CLKSOURCE_HCLK 0x00000004U

Definition at line 110 of file stm32wbxx_hal_cortex.h.

Referenced by HAL_SYSTICK_CLKSourceConfig().

#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U

Definition at line 109 of file stm32wbxx_hal_cortex.h.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CORTEX MPU HFNMI and PRIVILEGED Access control

Defines
CORTEX MPU HFNMI and PRIVILEGED Access control
CORTEX Exported Constants

Defines

#define | MPU_HFNMI_PRIVDEF_NONE 0x00000000U
#define | MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk)
#define | MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk)
#define | MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)

Define Documentation

#define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk)

Definition at line 121 of file stm32wbxx_hal_cortex.h.

#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)

Definition at line 123 of file stm32wbxx_hal_cortex.h.

#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U

Definition at line 120 of file stm32wbxx_hal_cortex.h.

#define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk)

Definition at line 122 of file stm32wbxx_hal_cortex.h.

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STM32WB55xx HAL User Manual: CORTEX MPU Region Enable

Defines
CORTEX MPU Region Enable
CORTEX Exported Constants

Defines

#define | MPU_REGION_ENABLE ((uint8_t)0x01)
#define | MPU_REGION_DISABLE ((uint8_t)0x00)

Define Documentation

#define MPU_REGION_DISABLE ((uint8_t)0x00)

Definition at line 132 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_ENABLE ((uint8_t)0x01)

Definition at line 131 of file stm32wbxx_hal_cortex.h.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CORTEX MPU Instruction Access

Defines
CORTEX MPU Instruction Access
CORTEX Exported Constants

Defines

#define | MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
#define | MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)

Define Documentation

#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)

Definition at line 141 of file stm32wbxx_hal_cortex.h.

#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)

Definition at line 140 of file stm32wbxx_hal_cortex.h.

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STM32WB55xx HAL User Manual: CORTEX MPU Instruction Access Shareable

Defines
CORTEX MPU Instruction Access Shareable
CORTEX Exported Constants

Defines

#define | MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)

Define Documentation

#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)

Definition at line 150 of file stm32wbxx_hal_cortex.h.

#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)

Definition at line 149 of file stm32wbxx_hal_cortex.h.

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STM32WB55xx HAL User Manual: CORTEX MPU Instruction Access Cacheable

Defines
CORTEX MPU Instruction Access Cacheable
CORTEX Exported Constants

Defines

#define | MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)

Define Documentation

#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)

Definition at line 158 of file stm32wbxx_hal_cortex.h.

#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)

Definition at line 159 of file stm32wbxx_hal_cortex.h.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CORTEX MPU Instruction Access Bufferable

Defines
CORTEX MPU Instruction Access Bufferable
CORTEX Exported Constants

Defines

#define | MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)

Define Documentation

#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)

Definition at line 167 of file stm32wbxx_hal_cortex.h.

#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)

Definition at line 168 of file stm32wbxx_hal_cortex.h.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CORTEX MPU TEX Levels

Defines
CORTEX MPU TEX Levels
CORTEX Exported Constants

Defines

#define | MPU_TEX_LEVEL0 ((uint8_t)0x00)
#define | MPU_TEX_LEVEL1 ((uint8_t)0x01)
#define | MPU_TEX_LEVEL2 ((uint8_t)0x02)

Define Documentation

#define MPU_TEX_LEVEL0 ((uint8_t)0x00)

Definition at line 176 of file stm32wbxx_hal_cortex.h.

#define MPU_TEX_LEVEL1 ((uint8_t)0x01)

Definition at line 177 of file stm32wbxx_hal_cortex.h.

#define MPU_TEX_LEVEL2 ((uint8_t)0x02)

Definition at line 178 of file stm32wbxx_hal_cortex.h.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CORTEX MPU Region Size

Defines
CORTEX MPU Region Size
CORTEX Exported Constants

Defines

#define | MPU_REGION_SIZE_32B ((uint8_t)0x04)
#define | MPU_REGION_SIZE_64B ((uint8_t)0x05)
#define | MPU_REGION_SIZE_128B ((uint8_t)0x06)
#define | MPU_REGION_SIZE_256B ((uint8_t)0x07)
#define | MPU_REGION_SIZE_512B ((uint8_t)0x08)
#define | MPU_REGION_SIZE_1KB ((uint8_t)0x09)
#define | MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
#define | MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
#define | MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
#define | MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
#define | MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
#define | MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
#define | MPU_REGION_SIZE_128KB ((uint8_t)0x10)
#define | MPU_REGION_SIZE_256KB ((uint8_t)0x11)
#define | MPU_REGION_SIZE_512KB ((uint8_t)0x12)
#define | MPU_REGION_SIZE_1MB ((uint8_t)0x13)
#define | MPU_REGION_SIZE_2MB ((uint8_t)0x14)
#define | MPU_REGION_SIZE_4MB ((uint8_t)0x15)
#define | MPU_REGION_SIZE_8MB ((uint8_t)0x16)
#define | MPU_REGION_SIZE_16MB ((uint8_t)0x17)
#define | MPU_REGION_SIZE_32MB ((uint8_t)0x18)
#define | MPU_REGION_SIZE_64MB ((uint8_t)0x19)
#define | MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
#define | MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
#define | MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
#define | MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
#define | MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
#define | MPU_REGION_SIZE_4GB ((uint8_t)0x1F)

Define Documentation

#define MPU_REGION_SIZE_128B ((uint8_t)0x06)

Definition at line 188 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)

Definition at line 198 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)

Definition at line 208 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)

Definition at line 195 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)

Definition at line 205 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)

Definition at line 211 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)

Definition at line 191 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)

Definition at line 201 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_SIZE_256B ((uint8_t)0x07)

Definition at line 189 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)

Definition at line 199 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)

Definition at line 209 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)

Definition at line 212 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)

Definition at line 192 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)

Definition at line 202 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_SIZE_32B ((uint8_t)0x04)

Definition at line 186 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)

Definition at line 196 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)

Definition at line 206 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)

Definition at line 213 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)

Definition at line 193 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)

Definition at line 203 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_SIZE_512B ((uint8_t)0x08)

Definition at line 190 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)

Definition at line 200 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)

Definition at line 210 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_SIZE_64B ((uint8_t)0x05)

Definition at line 187 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)

Definition at line 197 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)

Definition at line 207 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)

Definition at line 194 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)

Definition at line 204 of file stm32wbxx_hal_cortex.h.

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STM32WB55xx HAL User Manual: CORTEX MPU Region Permission Attributes

Defines
CORTEX MPU Region Permission Attributes
CORTEX Exported Constants

Defines

#define | MPU_REGION_NO_ACCESS ((uint8_t)0x00)
#define | MPU_REGION_PRIV_RW ((uint8_t)0x01)
#define | MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
#define | MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
#define | MPU_REGION_PRIV_RO ((uint8_t)0x05)
#define | MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)

Define Documentation

#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)

Definition at line 224 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)

Definition at line 221 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_PRIV_RO ((uint8_t)0x05)

Definition at line 225 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)

Definition at line 226 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_PRIV_RW ((uint8_t)0x01)

Definition at line 222 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)

Definition at line 223 of file stm32wbxx_hal_cortex.h.

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STM32WB55xx HAL User Manual: CORTEX MPU Region Number

Defines
CORTEX MPU Region Number
CORTEX Exported Constants

Defines

#define | MPU_REGION_NUMBER0 ((uint8_t)0x00)
#define | MPU_REGION_NUMBER1 ((uint8_t)0x01)
#define | MPU_REGION_NUMBER2 ((uint8_t)0x02)
#define | MPU_REGION_NUMBER3 ((uint8_t)0x03)
#define | MPU_REGION_NUMBER4 ((uint8_t)0x04)
#define | MPU_REGION_NUMBER5 ((uint8_t)0x05)
#define | MPU_REGION_NUMBER6 ((uint8_t)0x06)
#define | MPU_REGION_NUMBER7 ((uint8_t)0x07)

Define Documentation

#define MPU_REGION_NUMBER0 ((uint8_t)0x00)

Definition at line 234 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_NUMBER1 ((uint8_t)0x01)

Definition at line 235 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_NUMBER2 ((uint8_t)0x02)

Definition at line 236 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_NUMBER3 ((uint8_t)0x03)

Definition at line 237 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_NUMBER4 ((uint8_t)0x04)

Definition at line 238 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_NUMBER5 ((uint8_t)0x05)

Definition at line 239 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_NUMBER6 ((uint8_t)0x06)

Definition at line 240 of file stm32wbxx_hal_cortex.h.

#define MPU_REGION_NUMBER7 ((uint8_t)0x07)

Definition at line 241 of file stm32wbxx_hal_cortex.h.

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STM32WB55xx HAL User Manual: CORTEX Exported Macros

CORTEX Exported Macros
CORTEX
Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization and Configuration functions

Functions
Initialization and Configuration functions
CORTEX Exported Functions

Initialization and Configuration functions. More...

Functions

void | HAL_NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
Set the priority grouping field (pre-emption priority and subpriority) using the required unlock sequence.
void | HAL_NVIC_SetPriority (IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
Set the priority of an interrupt.
void | HAL_NVIC_EnableIRQ (IRQn_Type IRQn)
Enable a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_DisableIRQ (IRQn_Type IRQn)
Disable a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_SystemReset (void)
Initiate a system reset request to reset the MCU.
uint32_t | HAL_SYSTICK_Config (uint32_t TicksNumb)
Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): Counter is in free running mode to generate periodic interrupts.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and Configuration functions #####
  ==============================================================================
    [..]
      This section provides the CORTEX HAL driver functions allowing to configure Interrupts
      Systick functionalities

Function Documentation

void HAL_NVIC_DisableIRQ ( IRQn_Type IRQn )

Disable a device specific interrupt in the NVIC interrupt controller.

Parameters:
IRQn External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
Return values:
None

Definition at line 196 of file stm32wbxx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

void HAL_NVIC_EnableIRQ ( IRQn_Type IRQn )

Enable a device specific interrupt in the NVIC interrupt controller.

Parameters:
IRQn External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
Return values:
None

Definition at line 180 of file stm32wbxx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

void HAL_NVIC_SetPriority | ( | IRQn_Type | IRQn,
 |  | uint32_t | PreemptPriority,
 |  | uint32_t | SubPriority
 | ) |  |

Set the priority of an interrupt.

Parameters:
IRQn | External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
PreemptPriority | The pre-emption priority for the IRQn channel. This parameter can be a value between 0 and 15 A lower priority value indicates a higher priority
SubPriority | the subpriority level for the IRQ channel. This parameter can be a value between 0 and 15 A lower priority value indicates a higher priority.
Return values:
None

Definition at line 160 of file stm32wbxx_hal_cortex.c.

References assert_param, IS_NVIC_PREEMPTION_PRIORITY, and IS_NVIC_SUB_PRIORITY.

Referenced by HAL_InitTick().

void HAL_NVIC_SetPriorityGrouping ( uint32_t PriorityGroup )

Set the priority grouping field (pre-emption priority and subpriority) using the required unlock sequence.

Parameters:
PriorityGroup The priority grouping bits length. This parameter can be one of the following values:
  • NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority, 4 bits for subpriority
  • NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority, 3 bits for subpriority
  • NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority, 2 bits for subpriority
  • NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority, 1 bit for subpriority
  • NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority, 0 bit for subpriority
Note:
When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. The pending IRQ priority will be managed only by the subpriority.
Return values:
None

Definition at line 138 of file stm32wbxx_hal_cortex.c.

References assert_param, and IS_NVIC_PRIORITY_GROUP.

Referenced by HAL_Init().

void HAL_NVIC_SystemReset ( void )

Initiate a system reset request to reset the MCU.

Return values:
None

Definition at line 209 of file stm32wbxx_hal_cortex.c.

uint32_t HAL_SYSTICK_Config ( uint32_t TicksNumb )

Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): Counter is in free running mode to generate periodic interrupts.

Parameters:
TicksNumb Specifies the ticks Number of ticks between two interrupts.
Return values:
status,: - 0 Function succeeded.
  • 1 Function failed.

Definition at line 222 of file stm32wbxx_hal_cortex.c.

Referenced by HAL_InitTick().

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STM32WB55xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
CORTEX Exported Functions

Cortex control functions. More...

Functions

uint32_t | HAL_NVIC_GetPriorityGrouping (void)
Get the priority grouping field from the NVIC Interrupt Controller.
void | HAL_NVIC_GetPriority (IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
Get the priority of an interrupt.
void | HAL_NVIC_SetPendingIRQ (IRQn_Type IRQn)
Set Pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetPendingIRQ (IRQn_Type IRQn)
Get Pending Interrupt (read the pending register in the NVIC and return the pending bit for the specified interrupt).
void | HAL_NVIC_ClearPendingIRQ (IRQn_Type IRQn)
Clear the pending bit of an external interrupt.
void | HAL_SYSTICK_CLKSourceConfig (uint32_t CLKSource)
Configure the SysTick clock source.
void | HAL_SYSTICK_IRQHandler (void)
Handle SYSTICK interrupt request.
__weak void | HAL_SYSTICK_Callback (void)
SYSTICK callback.
void | HAL_MPU_Disable (void)
Disables the MPU.
void | HAL_MPU_Enable (uint32_t MPU_Control)
Enable the MPU.
void | HAL_MPU_ConfigRegion (MPU_Region_InitTypeDef *MPU_Init)
Initialize and configure the Region and the memory to be protected.

Detailed Description

Cortex control functions.

  ==============================================================================
                      ##### Peripheral Control functions #####
  ==============================================================================
    [..]
      This subsection provides a set of functions allowing to control the CORTEX
      (NVIC, SYSTICK, MPU) functionalities.

Function Documentation

void HAL_MPU_ConfigRegion ( MPU_Region_InitTypeDef * MPU_Init )

Initialize and configure the Region and the memory to be protected.

Parameters:
MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains the initialization and configuration information.
Return values:
None

Definition at line 425 of file stm32wbxx_hal_cortex.c.

References MPU_Region_InitTypeDef::AccessPermission, assert_param, MPU_Region_InitTypeDef::BaseAddress, MPU_Region_InitTypeDef::DisableExec, MPU_Region_InitTypeDef::Enable, IS_MPU_ACCESS_BUFFERABLE, IS_MPU_ACCESS_CACHEABLE, IS_MPU_ACCESS_SHAREABLE, IS_MPU_INSTRUCTION_ACCESS, IS_MPU_REGION_ENABLE, IS_MPU_REGION_NUMBER, IS_MPU_REGION_PERMISSION_ATTRIBUTE, IS_MPU_REGION_SIZE, IS_MPU_SUB_REGION_DISABLE, IS_MPU_TEX_LEVEL, MPU_Region_InitTypeDef::IsBufferable, MPU_Region_InitTypeDef::IsCacheable, MPU_Region_InitTypeDef::IsShareable, MPU_Region_InitTypeDef::Number, MPU_Region_InitTypeDef::Size, MPU_Region_InitTypeDef::SubRegionDisable, and MPU_Region_InitTypeDef::TypeExtField.

void HAL_MPU_Disable ( void )

Disables the MPU.

Return values:
None

Definition at line 383 of file stm32wbxx_hal_cortex.c.

void HAL_MPU_Enable ( uint32_t MPU_Control )

Enable the MPU.

Parameters:
MPU_Control,: Specifies the control mode of the MPU during hard fault, NMI, FAULTMASK and privileged access to the default memory This parameter can be one of the following values:
  • MPU_HFNMI_PRIVDEF_NONE
  • MPU_HARDFAULT_NMI
  • MPU_PRIVILEGED_DEFAULT
  • MPU_HFNMI_PRIVDEF
Return values:
None

Definition at line 406 of file stm32wbxx_hal_cortex.c.

void HAL_NVIC_ClearPendingIRQ ( IRQn_Type IRQn )

Clear the pending bit of an external interrupt.

Parameters:
IRQn External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
Return values:
None

Definition at line 327 of file stm32wbxx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

uint32_t HAL_NVIC_GetPendingIRQ ( IRQn_Type IRQn )

Get Pending Interrupt (read the pending register in the NVIC and return the pending bit for the specified interrupt).

Parameters:
IRQn External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
Return values:
status,: - 0 Interrupt status is not pending.
  • 1 Interrupt status is pending.

Definition at line 311 of file stm32wbxx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

void HAL_NVIC_GetPriority | ( | IRQn_Type | IRQn,
 |  | uint32_t | PriorityGroup,
 |  | uint32_t * | pPreemptPriority,
 |  | uint32_t * | pSubPriority
 | ) |  |

Get the priority of an interrupt.

Parameters:
IRQn | External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
PriorityGroup the priority grouping bits length. This parameter can be one of the following values:
  • NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority, 4 bits for subpriority
  • NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority, 3 bits for subpriority
  • NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority, 2 bits for subpriority
  • NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority, 1 bit for subpriority
  • NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority, 0 bit for subpriority
pPreemptPriority | Pointer on the Preemptive priority value (starting from 0).
pSubPriority | Pointer on the Subpriority value (starting from 0).
Return values:
None

Definition at line 278 of file stm32wbxx_hal_cortex.c.

References assert_param, and IS_NVIC_PRIORITY_GROUP.

uint32_t HAL_NVIC_GetPriorityGrouping ( void )

Get the priority grouping field from the NVIC Interrupt Controller.

Return values:
Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)

Definition at line 251 of file stm32wbxx_hal_cortex.c.

void HAL_NVIC_SetPendingIRQ ( IRQn_Type IRQn )

Set Pending bit of an external interrupt.

Parameters:
IRQn External interrupt number This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
Return values:
None

Definition at line 293 of file stm32wbxx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

void HAL_SYSTICK_Callback ( void )

SYSTICK callback.

Return values:
None

Definition at line 371 of file stm32wbxx_hal_cortex.c.

Referenced by HAL_SYSTICK_IRQHandler().

void HAL_SYSTICK_CLKSourceConfig ( uint32_t CLKSource )

Configure the SysTick clock source.

Parameters:
CLKSource specifies the SysTick clock source. This parameter can be one of the following values:
  • SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
  • SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
Return values:
None

Definition at line 344 of file stm32wbxx_hal_cortex.c.

References assert_param, IS_SYSTICK_CLK_SOURCE, and SYSTICK_CLKSOURCE_HCLK.

void HAL_SYSTICK_IRQHandler ( void )

Handle SYSTICK interrupt request.

Return values:
None

Definition at line 362 of file stm32wbxx_hal_cortex.c.

References HAL_SYSTICK_Callback().

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CORTEX Private Macros

Defines
CORTEX Private Macros
CORTEX

Defines

#define | IS_NVIC_PRIORITY_GROUP(GROUP)
#define | IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
#define | IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
#define | IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn)
#define | IS_SYSTICK_CLK_SOURCE(SOURCE)
#define | IS_MPU_REGION_ENABLE(STATE)
#define | IS_MPU_INSTRUCTION_ACCESS(STATE)
#define | IS_MPU_ACCESS_SHAREABLE(STATE)
#define | IS_MPU_ACCESS_CACHEABLE(STATE)
#define | IS_MPU_ACCESS_BUFFERABLE(STATE)
#define | IS_MPU_TEX_LEVEL(TYPE)
#define | IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE)
#define | IS_MPU_REGION_NUMBER(NUMBER)
#define | IS_MPU_REGION_SIZE(SIZE)
#define | IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)

Define Documentation

#define IS_MPU_ACCESS_BUFFERABLE ( STATE )
Value:
(((STATE) == MPU_ACCESS_BUFFERABLE) || \
                                                   ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))

Definition at line 342 of file stm32wbxx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_ACCESS_CACHEABLE ( STATE )
Value:
(((STATE) == MPU_ACCESS_CACHEABLE) || \
                                                   ((STATE) == MPU_ACCESS_NOT_CACHEABLE))

Definition at line 339 of file stm32wbxx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_ACCESS_SHAREABLE ( STATE )
Value:
(((STATE) == MPU_ACCESS_SHAREABLE) || \
                                                   ((STATE) == MPU_ACCESS_NOT_SHAREABLE))

Definition at line 336 of file stm32wbxx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_INSTRUCTION_ACCESS ( STATE )
Value:
(((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
                                                   ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))

Definition at line 333 of file stm32wbxx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_REGION_ENABLE ( STATE )
Value:
(((STATE) == MPU_REGION_ENABLE) || \
                                                   ((STATE) == MPU_REGION_DISABLE))

Definition at line 330 of file stm32wbxx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_REGION_NUMBER ( NUMBER )
Value:
(((NUMBER) == MPU_REGION_NUMBER0) || \
                                                   ((NUMBER) == MPU_REGION_NUMBER1) || \
                                                   ((NUMBER) == MPU_REGION_NUMBER2) || \
                                                   ((NUMBER) == MPU_REGION_NUMBER3) || \
                                                   ((NUMBER) == MPU_REGION_NUMBER4) || \
                                                   ((NUMBER) == MPU_REGION_NUMBER5) || \
                                                   ((NUMBER) == MPU_REGION_NUMBER6) || \
                                                   ((NUMBER) == MPU_REGION_NUMBER7))

Definition at line 356 of file stm32wbxx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_REGION_PERMISSION_ATTRIBUTE ( TYPE )
Value:
(((TYPE) == MPU_REGION_NO_ACCESS)   || \
                                                   ((TYPE) == MPU_REGION_PRIV_RW)     || \
                                                   ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
                                                   ((TYPE) == MPU_REGION_FULL_ACCESS) || \
                                                   ((TYPE) == MPU_REGION_PRIV_RO)     || \
                                                   ((TYPE) == MPU_REGION_PRIV_RO_URO))

Definition at line 349 of file stm32wbxx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_REGION_SIZE ( SIZE )
Value:
(((SIZE) == MPU_REGION_SIZE_32B)   || \
                                                   ((SIZE) == MPU_REGION_SIZE_64B)   || \
                                                   ((SIZE) == MPU_REGION_SIZE_128B)  || \
                                                   ((SIZE) == MPU_REGION_SIZE_256B)  || \
                                                   ((SIZE) == MPU_REGION_SIZE_512B)  || \
                                                   ((SIZE) == MPU_REGION_SIZE_1KB)   || \
                                                   ((SIZE) == MPU_REGION_SIZE_2KB)   || \
                                                   ((SIZE) == MPU_REGION_SIZE_4KB)   || \
                                                   ((SIZE) == MPU_REGION_SIZE_8KB)   || \
                                                   ((SIZE) == MPU_REGION_SIZE_16KB)  || \
                                                   ((SIZE) == MPU_REGION_SIZE_32KB)  || \
                                                   ((SIZE) == MPU_REGION_SIZE_64KB)  || \
                                                   ((SIZE) == MPU_REGION_SIZE_128KB) || \
                                                   ((SIZE) == MPU_REGION_SIZE_256KB) || \
                                                   ((SIZE) == MPU_REGION_SIZE_512KB) || \
                                                   ((SIZE) == MPU_REGION_SIZE_1MB)   || \
                                                   ((SIZE) == MPU_REGION_SIZE_2MB)   || \
                                                   ((SIZE) == MPU_REGION_SIZE_4MB)   || \
                                                   ((SIZE) == MPU_REGION_SIZE_8MB)   || \
                                                   ((SIZE) == MPU_REGION_SIZE_16MB)  || \
                                                   ((SIZE) == MPU_REGION_SIZE_32MB)  || \
                                                   ((SIZE) == MPU_REGION_SIZE_64MB)  || \
                                                   ((SIZE) == MPU_REGION_SIZE_128MB) || \
                                                   ((SIZE) == MPU_REGION_SIZE_256MB) || \
                                                   ((SIZE) == MPU_REGION_SIZE_512MB) || \
                                                   ((SIZE) == MPU_REGION_SIZE_1GB)   || \
                                                   ((SIZE) == MPU_REGION_SIZE_2GB)   || \
                                                   ((SIZE) == MPU_REGION_SIZE_4GB))

Definition at line 365 of file stm32wbxx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_SUB_REGION_DISABLE ( SUBREGION ) ((SUBREGION) < (uint16_t)0x00FFU)

Definition at line 394 of file stm32wbxx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_MPU_TEX_LEVEL ( TYPE )
Value:
(((TYPE) == MPU_TEX_LEVEL0)  || \
                                                   ((TYPE) == MPU_TEX_LEVEL1)  || \
                                                   ((TYPE) == MPU_TEX_LEVEL2))

Definition at line 345 of file stm32wbxx_hal_cortex.h.

Referenced by HAL_MPU_ConfigRegion().

#define IS_NVIC_DEVICE_IRQ ( IRQ ) ((IRQ) > SysTick_IRQn)

Definition at line 324 of file stm32wbxx_hal_cortex.h.

Referenced by HAL_NVIC_ClearPendingIRQ(), HAL_NVIC_DisableIRQ(), HAL_NVIC_EnableIRQ(), HAL_NVIC_GetPendingIRQ(), and HAL_NVIC_SetPendingIRQ().

#define IS_NVIC_PREEMPTION_PRIORITY ( PRIORITY ) ((PRIORITY) < 0x10U)

Definition at line 320 of file stm32wbxx_hal_cortex.h.

Referenced by HAL_NVIC_SetPriority().

#define IS_NVIC_PRIORITY_GROUP ( GROUP )
Value:
(((GROUP) == NVIC_PRIORITYGROUP_0) || \
                                       ((GROUP) == NVIC_PRIORITYGROUP_1) || \
                                       ((GROUP) == NVIC_PRIORITYGROUP_2) || \
                                       ((GROUP) == NVIC_PRIORITYGROUP_3) || \
                                       ((GROUP) == NVIC_PRIORITYGROUP_4))

Definition at line 314 of file stm32wbxx_hal_cortex.h.

Referenced by HAL_NVIC_GetPriority(), and HAL_NVIC_SetPriorityGrouping().

#define IS_NVIC_SUB_PRIORITY ( PRIORITY ) ((PRIORITY) < 0x10U)

Definition at line 322 of file stm32wbxx_hal_cortex.h.

Referenced by HAL_NVIC_SetPriority().

#define IS_SYSTICK_CLK_SOURCE ( SOURCE )
Value:
(((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
                                                   ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))

Definition at line 326 of file stm32wbxx_hal_cortex.h.

Referenced by HAL_SYSTICK_CLKSourceConfig().

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CRC Private Functions

Functions
CRC Private Functions
CRC

Functions

static uint32_t | CRC_Handle_8 (CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
Enter 8-bit input data to the CRC calculator.
static uint32_t | CRC_Handle_16 (CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
Enter 16-bit input data to the CRC calculator.

Function Documentation

static uint32_t CRC_Handle_16 | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint16_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  | [static]

Enter 16-bit input data to the CRC calculator.

Specific data handling to optimize processing time.

Parameters:
hcrc | CRC handle
pBuffer | pointer to the input data buffer
BufferLength | input data buffer length
Return values:
uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)

Definition at line 483 of file stm32wbxx_hal_crc.c.

References CRC_HandleTypeDef::Instance.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

static uint32_t CRC_Handle_8 | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint8_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  | [static]

Enter 8-bit input data to the CRC calculator.

Specific data handling to optimize processing time.

Parameters:
hcrc | CRC handle
pBuffer | pointer to the input data buffer
BufferLength | input data buffer length
Return values:
uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)

Definition at line 432 of file stm32wbxx_hal_crc.c.

References CRC_HandleTypeDef::Instance.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CRC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_CRC_Init (CRC_HandleTypeDef *hcrc)
Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC peripheral.
__weak void | HAL_CRC_MspInit (CRC_HandleTypeDef *hcrc)
Initializes the CRC MSP.
__weak void | HAL_CRC_MspDeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
            ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the CRC according to the specified parameters
          in the CRC_InitTypeDef and create the associated handle
      (+) DeInitialize the CRC peripheral
      (+) Initialize the CRC MSP (MCU Specific Package)
      (+) DeInitialize the CRC MSP

Function Documentation

HAL_StatusTypeDef HAL_CRC_DeInit ( CRC_HandleTypeDef * hcrc )

DeInitialize the CRC peripheral.

Parameters:
hcrc CRC handle
Return values:
HAL status

Definition at line 179 of file stm32wbxx_hal_crc.c.

References __HAL_CRC_DR_RESET, assert_param, HAL_CRC_MspDeInit(), HAL_CRC_STATE_BUSY, HAL_CRC_STATE_RESET, CRC_HandleTypeDef::Instance, and CRC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRC_Init ( CRC_HandleTypeDef * hcrc )

Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and create the associated handle.

Parameters:
hcrc CRC handle
Return values:
HAL status

Definition at line 103 of file stm32wbxx_hal_crc.c.

References assert_param, CRC_POLYLENGTH_32B, CRC_InitTypeDef::CRCLength, DEFAULT_CRC32_POLY, DEFAULT_CRC_INITVALUE, DEFAULT_INIT_VALUE_ENABLE, DEFAULT_POLYNOMIAL_ENABLE, CRC_InitTypeDef::DefaultInitValueUse, CRC_InitTypeDef::DefaultPolynomialUse, CRC_InitTypeDef::GeneratingPolynomial, HAL_CRC_MspInit(), HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, HAL_CRC_STATE_RESET, HAL_CRCEx_Polynomial_Set(), CRC_HandleTypeDef::Init, CRC_InitTypeDef::InitValue, CRC_HandleTypeDef::InputDataFormat, CRC_InitTypeDef::InputDataInversionMode, CRC_HandleTypeDef::Instance, IS_CRC_INPUTDATA_FORMAT, IS_CRC_INPUTDATA_INVERSION_MODE, IS_CRC_OUTPUTDATA_INVERSION_MODE, IS_DEFAULT_INIT_VALUE, IS_DEFAULT_POLYNOMIAL, CRC_HandleTypeDef::Lock, CRC_InitTypeDef::OutputDataInversionMode, and CRC_HandleTypeDef::State.

void HAL_CRC_MspDeInit ( CRC_HandleTypeDef * hcrc )

DeInitialize the CRC MSP.

Parameters:
hcrc CRC handle
Return values:
None

Definition at line 238 of file stm32wbxx_hal_crc.c.

Referenced by HAL_CRC_DeInit().

void HAL_CRC_MspInit ( CRC_HandleTypeDef * hcrc )

Initializes the CRC MSP.

Parameters:
hcrc CRC handle
Return values:
None

Definition at line 223 of file stm32wbxx_hal_crc.c.

Referenced by HAL_CRC_Init().

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
CRC Exported Functions

management functions. More...

Functions

uint32_t | HAL_CRC_Accumulate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with the previously computed CRC as initialization value.
uint32_t | HAL_CRC_Calculate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with hcrc->Instance->INIT as initialization value.

Detailed Description

management functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
          using combination of the previous CRC value and the new one.

       [..]  or

      (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
          independently of the previous CRC value.

Function Documentation

uint32_t HAL_CRC_Accumulate | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  |

Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with the previously computed CRC as initialization value.

Parameters:
hcrc | CRC handle
pBuffer | pointer to the input data buffer, exact input data format is provided by hcrc->InputDataFormat.
BufferLength | input data buffer length (number of bytes if pBuffer type is * uint8_t, number of half-words if pBuffer type is * uint16_t, number of words if pBuffer type is * uint32_t).
Note:
By default, the API expects a uint32_t pointer as input buffer parameter. Input buffer pointers with other types simply need to be cast in uint32_t and the API will internally adjust its input data processing based on the handle field hcrc->InputDataFormat.
Return values:
uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)

Definition at line 287 of file stm32wbxx_hal_crc.c.

References CRC_Handle_16(), CRC_Handle_8(), CRC_INPUTDATA_FORMAT_BYTES, CRC_INPUTDATA_FORMAT_HALFWORDS, CRC_INPUTDATA_FORMAT_WORDS, HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::InputDataFormat, CRC_HandleTypeDef::Instance, and CRC_HandleTypeDef::State.

uint32_t HAL_CRC_Calculate | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  |

Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with hcrc->Instance->INIT as initialization value.

Parameters:
hcrc | CRC handle
pBuffer | pointer to the input data buffer, exact input data format is provided by hcrc->InputDataFormat.
BufferLength | input data buffer length (number of bytes if pBuffer type is * uint8_t, number of half-words if pBuffer type is * uint16_t, number of words if pBuffer type is * uint32_t).
Note:
By default, the API expects a uint32_t pointer as input buffer parameter. Input buffer pointers with other types simply need to be cast in uint32_t and the API will internally adjust its input data processing based on the handle field hcrc->InputDataFormat.
Return values:
uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)

Definition at line 339 of file stm32wbxx_hal_crc.c.

References __HAL_CRC_DR_RESET, CRC_Handle_16(), CRC_Handle_8(), CRC_INPUTDATA_FORMAT_BYTES, CRC_INPUTDATA_FORMAT_HALFWORDS, CRC_INPUTDATA_FORMAT_WORDS, HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::InputDataFormat, CRC_HandleTypeDef::Instance, and CRC_HandleTypeDef::State.

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STM32WB55xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
CRC Exported Functions

Peripheral State functions. More...

Functions

HAL_CRC_StateTypeDef HAL_CRC_GetState (CRC_HandleTypeDef *hcrc)
Return the CRC handle state.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral.

Function Documentation

HAL_CRC_StateTypeDef HAL_CRC_GetState ( CRC_HandleTypeDef * hcrc )

Return the CRC handle state.

Parameters:
hcrc CRC handle
Return values:
HAL state

Definition at line 406 of file stm32wbxx_hal_crc.c.

References CRC_HandleTypeDef::State.

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STM32WB55xx HAL User Manual: CRC Exported Types

Data Structures | Enumerations
CRC Exported Types
CRC

Data Structures

struct | CRC_InitTypeDef
CRC Init Structure definition. More...
struct | CRC_HandleTypeDef
CRC Handle Structure definition. More...

Enumerations

enum HAL_CRC_StateTypeDef {
HAL_CRC_STATE_RESET = 0x00U, HAL_CRC_STATE_READY = 0x01U, HAL_CRC_STATE_BUSY = 0x02U, HAL_CRC_STATE_TIMEOUT = 0x03U,
HAL_CRC_STATE_ERROR = 0x04U
}
CRC HAL State Structure definition. More...

Enumeration Type Documentation

enum HAL_CRC_StateTypeDef

CRC HAL State Structure definition.

Enumerator:
HAL_CRC_STATE_RESET

CRC not yet initialized or disabled

HAL_CRC_STATE_READY

CRC initialized and ready for use

HAL_CRC_STATE_BUSY

CRC internal process is ongoing

HAL_CRC_STATE_TIMEOUT

CRC timeout state

HAL_CRC_STATE_ERROR

CRC error state

Definition at line 47 of file stm32wbxx_hal_crc.h.

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STM32WB55xx HAL User Manual: CRC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CRC_InitTypeDef Struct Reference
CRC Exported Types

CRC Init Structure definition. More...

#include <stm32wbxx_hal_crc.h>

Data Fields

uint8_t | DefaultPolynomialUse
uint8_t | DefaultInitValueUse
uint32_t | GeneratingPolynomial
uint32_t | CRCLength
uint32_t | InitValue
uint32_t | InputDataInversionMode
uint32_t | OutputDataInversionMode

Detailed Description

CRC Init Structure definition.

Definition at line 59 of file stm32wbxx_hal_crc.h.

Field Documentation

uint32_t CRC_InitTypeDef::CRCLength

This parameter is a value of Polynomial sizes to configure the peripheral and indicates CRC length. Value can be either one of

  • CRC_POLYLENGTH_32B (32-bit CRC),
  • CRC_POLYLENGTH_16B (16-bit CRC),
  • CRC_POLYLENGTH_8B (8-bit CRC),
  • CRC_POLYLENGTH_7B (7-bit CRC).

Definition at line 77 of file stm32wbxx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint8_t CRC_InitTypeDef::DefaultInitValueUse

This parameter is a value of Indicates whether or not default init value is used and indicates if default init value is used. If set to DEFAULT_INIT_VALUE_ENABLE, resort to default 0xFFFFFFFF value. In that case, there is no need to set InitValue field. If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set.

Definition at line 67 of file stm32wbxx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint8_t CRC_InitTypeDef::DefaultPolynomialUse

This parameter is a value of Indicates whether or not default polynomial is used and indicates if default polynomial is used. If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1. In that case, there is no need to set GeneratingPolynomial field. If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set.

Definition at line 61 of file stm32wbxx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_InitTypeDef::GeneratingPolynomial

Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree respectively equal to 7, 8, 16 or 32. This field is written in normal representation, e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65. No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE.

Definition at line 72 of file stm32wbxx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_InitTypeDef::InitValue

Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse is set to DEFAULT_INIT_VALUE_ENABLE.

Definition at line 84 of file stm32wbxx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_InitTypeDef::InputDataInversionMode

This parameter is a value of Input Data Inversion Modes and specifies input data inversion mode. Can be either one of the following values

  • CRC_INPUTDATA_INVERSION_NONE no input data inversion
  • CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
  • CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
  • CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458

Definition at line 87 of file stm32wbxx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_InitTypeDef::OutputDataInversionMode

This parameter is a value of Output Data Inversion Modes and specifies output data (i.e. CRC) inversion mode. Can be either

  • CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion,
  • CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted into 0x22CC4488

Definition at line 94 of file stm32wbxx_hal_crc.h.

Referenced by HAL_CRC_Init().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_crc.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CRC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CRC_HandleTypeDef Struct Reference
CRC Exported Types

CRC Handle Structure definition. More...

#include <stm32wbxx_hal_crc.h>

Data Fields

CRC_TypeDef * | Instance
CRC_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_CRC_StateTypeDef | State
uint32_t | InputDataFormat

Detailed Description

CRC Handle Structure definition.

Definition at line 103 of file stm32wbxx_hal_crc.h.

Field Documentation

CRC_InitTypeDef CRC_HandleTypeDef::Init

CRC configuration parameters

Definition at line 107 of file stm32wbxx_hal_crc.h.

Referenced by HAL_CRC_Init().

uint32_t CRC_HandleTypeDef::InputDataFormat

This parameter is a value of Input Buffer Format and specifies input data format. Can be either

  • CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes (8-bit data)
  • CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of half-words (16-bit data)
  • CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words (32-bit data)

Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error must occur if InputBufferFormat is not one of the three values listed above

Definition at line 113 of file stm32wbxx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), HAL_CRC_Calculate(), and HAL_CRC_Init().

CRC_TypeDef* CRC_HandleTypeDef::Instance

Register base address

Definition at line 105 of file stm32wbxx_hal_crc.h.

Referenced by CRC_Handle_16(), CRC_Handle_8(), HAL_CRC_Accumulate(), HAL_CRC_Calculate(), HAL_CRC_DeInit(), HAL_CRC_Init(), HAL_CRCEx_Input_Data_Reverse(), HAL_CRCEx_Output_Data_Reverse(), and HAL_CRCEx_Polynomial_Set().

HAL_LockTypeDef CRC_HandleTypeDef::Lock

CRC Locking object

Definition at line 109 of file stm32wbxx_hal_crc.h.

Referenced by HAL_CRC_Init().

__IO HAL_CRC_StateTypeDef CRC_HandleTypeDef::State

CRC communication state

Definition at line 111 of file stm32wbxx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), HAL_CRC_Calculate(), HAL_CRC_DeInit(), HAL_CRC_GetState(), HAL_CRC_Init(), HAL_CRCEx_Input_Data_Reverse(), and HAL_CRCEx_Output_Data_Reverse().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_crc.h
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STM32WB55xx HAL User Manual: Default CRC generating polynomial

Defines
Default CRC generating polynomial
CRC Exported Constants

Defines

#define DEFAULT_CRC32_POLY 0x04C11DB7U

Define Documentation

#define DEFAULT_CRC32_POLY 0x04C11DB7U

X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1

Definition at line 134 of file stm32wbxx_hal_crc.h.

Referenced by HAL_CRC_Init().

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STM32WB55xx HAL User Manual: Default CRC computation initialization value

Defines
Default CRC computation initialization value
CRC Exported Constants

Defines

#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU

Define Documentation

#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU

Initial CRC default value

Definition at line 142 of file stm32wbxx_hal_crc.h.

Referenced by HAL_CRC_Init().

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STM32WB55xx HAL User Manual: Indicates whether or not default polynomial is used

Defines
Indicates whether or not default polynomial is used
CRC Exported Constants

Defines

#define | DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U)
#define | DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U)

Define Documentation

#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U)

Disable default generating polynomial 0x04C11DB7

Definition at line 151 of file stm32wbxx_hal_crc.h.

#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U)

Enable default generating polynomial 0x04C11DB7

Definition at line 150 of file stm32wbxx_hal_crc.h.

Referenced by HAL_CRC_Init().

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Indicates whether or not default init value is used

Defines
Indicates whether or not default init value is used
CRC Exported Constants

Defines

#define | DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U)
#define | DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U)

Define Documentation

#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U)

Disable initial CRC default value

Definition at line 160 of file stm32wbxx_hal_crc.h.

#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U)

Enable initial CRC default value

Definition at line 159 of file stm32wbxx_hal_crc.h.

Referenced by HAL_CRC_Init().

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STM32WB55xx HAL User Manual: Polynomial sizes to configure the peripheral

Defines
Polynomial sizes to configure the peripheral
CRC Exported Constants

Defines

#define | CRC_POLYLENGTH_32B 0x00000000U
#define | CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0
#define | CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1
#define | CRC_POLYLENGTH_7B CRC_CR_POLYSIZE

Define Documentation

#define CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0

Resort to a 16-bit long generating polynomial

Definition at line 169 of file stm32wbxx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define CRC_POLYLENGTH_32B 0x00000000U

Resort to a 32-bit long generating polynomial

Definition at line 168 of file stm32wbxx_hal_crc.h.

Referenced by HAL_CRC_Init(), and HAL_CRCEx_Polynomial_Set().

#define CRC_POLYLENGTH_7B CRC_CR_POLYSIZE

Resort to a 7-bit long generating polynomial

Definition at line 171 of file stm32wbxx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1

Resort to a 8-bit long generating polynomial

Definition at line 170 of file stm32wbxx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

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STM32WB55xx HAL User Manual: CRC polynomial possible sizes actual definitions

Defines
CRC polynomial possible sizes actual definitions
CRC Exported Constants

Defines

#define | HAL_CRC_LENGTH_32B 32U
#define | HAL_CRC_LENGTH_16B 16U
#define | HAL_CRC_LENGTH_8B 8U
#define | HAL_CRC_LENGTH_7B 7U

Define Documentation

#define HAL_CRC_LENGTH_16B 16U

16-bit long CRC

Definition at line 180 of file stm32wbxx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define HAL_CRC_LENGTH_32B 32U

32-bit long CRC

Definition at line 179 of file stm32wbxx_hal_crc.h.

#define HAL_CRC_LENGTH_7B 7U

7-bit long CRC

Definition at line 182 of file stm32wbxx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define HAL_CRC_LENGTH_8B 8U

8-bit long CRC

Definition at line 181 of file stm32wbxx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

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STM32WB55xx HAL User Manual: Input Buffer Format

Defines
Input Buffer Format
CRC Exported Constants

Defines

#define | CRC_INPUTDATA_FORMAT_UNDEFINED 0x00000000U
#define | CRC_INPUTDATA_FORMAT_BYTES 0x00000001U
#define | CRC_INPUTDATA_FORMAT_HALFWORDS 0x00000002U
#define | CRC_INPUTDATA_FORMAT_WORDS 0x00000003U

Define Documentation

#define CRC_INPUTDATA_FORMAT_BYTES 0x00000001U

Input data in byte format

Definition at line 195 of file stm32wbxx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

#define CRC_INPUTDATA_FORMAT_HALFWORDS 0x00000002U

Input data in half-word format

Definition at line 196 of file stm32wbxx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

#define CRC_INPUTDATA_FORMAT_UNDEFINED 0x00000000U

Undefined input data format

Definition at line 194 of file stm32wbxx_hal_crc.h.

#define CRC_INPUTDATA_FORMAT_WORDS 0x00000003U

Input data in word format

Definition at line 197 of file stm32wbxx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), and HAL_CRC_Calculate().

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STM32WB55xx HAL User Manual: CRC API aliases

Defines
CRC API aliases
CRC Exported Constants

Defines

#define | HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse
#define | HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse

Define Documentation

#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse

Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility

Definition at line 205 of file stm32wbxx_hal_crc.h.

#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse

Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility

Definition at line 206 of file stm32wbxx_hal_crc.h.

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STM32WB55xx HAL User Manual: CRC Exported Macros

Defines
CRC Exported Macros
CRC

Defines

#define | __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
Reset CRC handle state.
#define | __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
Reset CRC Data Register.
#define | __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
Set CRC INIT non-default value.
#define | __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
Store data in the Independent Data (ID) register.
#define | __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
Return the data stored in the Independent Data (ID) register.

Define Documentation

#define __HAL_CRC_DR_RESET ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)

Reset CRC Data Register.

Parameters:
__HANDLE__ CRC handle
Return values:
None

Definition at line 231 of file stm32wbxx_hal_crc.h.

Referenced by HAL_CRC_Calculate(), and HAL_CRC_DeInit().

#define __HAL_CRC_GET_IDR ( __HANDLE__ ) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)

Return the data stored in the Independent Data (ID) register.

Parameters:
__HANDLE__ CRC handle
Note:
Refer to the Reference Manual to get the authorized __VALUE__ length in bits
Return values:
Value of the ID register

Definition at line 256 of file stm32wbxx_hal_crc.h.

#define __HAL_CRC_INITIALCRCVALUE_CONFIG | ( | __HANDLE__,
 |  | __INIT__
 | ) | ((__HANDLE__)->Instance->INIT = (__INIT__))

Set CRC INIT non-default value.

Parameters:
__HANDLE__ | CRC handle
__INIT__ | 32-bit initial value
Return values:
None

Definition at line 239 of file stm32wbxx_hal_crc.h.

#define __HAL_CRC_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)

Reset CRC handle state.

Parameters:
__HANDLE__ CRC handle.
Return values:
None

Definition at line 224 of file stm32wbxx_hal_crc.h.

#define __HAL_CRC_SET_IDR | ( | __HANDLE__,
 |  | __VALUE__
 | ) | (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))

Store data in the Independent Data (ID) register.

Parameters:
__HANDLE__ | CRC handle
__VALUE__ | Value to be stored in the ID register
Note:
Refer to the Reference Manual to get the authorized __VALUE__ length in bits
Return values:
None

Definition at line 248 of file stm32wbxx_hal_crc.h.

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STM32WB55xx HAL User Manual: CRC Private Macros

Defines
CRC Private Macros
CRC

Defines

#define | IS_DEFAULT_POLYNOMIAL(DEFAULT)
#define | IS_DEFAULT_INIT_VALUE(VALUE)
#define | IS_CRC_POL_LENGTH(LENGTH)
#define | IS_CRC_INPUTDATA_FORMAT(FORMAT)

Define Documentation

#define IS_CRC_INPUTDATA_FORMAT ( FORMAT )
Value:
(((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES)     || \
                                                   ((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
                                                   ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))

Definition at line 279 of file stm32wbxx_hal_crc.h.

Referenced by HAL_CRC_Init().

#define IS_CRC_POL_LENGTH ( LENGTH )
Value:
(((LENGTH) == CRC_POLYLENGTH_32B) || \
                                       ((LENGTH) == CRC_POLYLENGTH_16B) || \
                                       ((LENGTH) == CRC_POLYLENGTH_8B)  || \
                                       ((LENGTH) == CRC_POLYLENGTH_7B))

Definition at line 274 of file stm32wbxx_hal_crc.h.

Referenced by HAL_CRCEx_Polynomial_Set().

#define IS_DEFAULT_INIT_VALUE ( VALUE )
Value:
(((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
                                       ((VALUE) == DEFAULT_INIT_VALUE_DISABLE))

Definition at line 271 of file stm32wbxx_hal_crc.h.

Referenced by HAL_CRC_Init().

#define IS_DEFAULT_POLYNOMIAL ( DEFAULT )
Value:
(((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
                                        ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))

Definition at line 267 of file stm32wbxx_hal_crc.h.

Referenced by HAL_CRC_Init().

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STM32WB55xx HAL User Manual: Extended Initialization/de-initialization functions

Functions
Extended Initialization/de-initialization functions
CRC Extended Exported Functions

Extended Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_CRCEx_Polynomial_Set (CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
Initialize the CRC polynomial if different from default one.
HAL_StatusTypeDef | HAL_CRCEx_Input_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
Set the Reverse Input data mode.
HAL_StatusTypeDef | HAL_CRCEx_Output_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
Set the Reverse Output data mode.

Detailed Description

Extended Initialization and Configuration functions.

 ===============================================================================
            ##### Extended configuration functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure the generating polynomial
      (+) Configure the input data inversion
      (+) Configure the output data inversion

Function Documentation

HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | InputReverseMode
 | ) |  |

Set the Reverse Input data mode.

Parameters:
hcrc CRC handle
InputReverseMode Input Data inversion mode. This parameter can be one of the following values:
  • CRC_INPUTDATA_INVERSION_NONE no change in bit order (default value)
  • CRC_INPUTDATA_INVERSION_BYTE Byte-wise bit reversal
  • CRC_INPUTDATA_INVERSION_HALFWORD HalfWord-wise bit reversal
  • CRC_INPUTDATA_INVERSION_WORD Word-wise bit reversal
Return values:
HAL status

Definition at line 159 of file stm32wbxx_hal_crc_ex.c.

References assert_param, HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::Instance, IS_CRC_INPUTDATA_INVERSION_MODE, and CRC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | OutputReverseMode
 | ) |  |

Set the Reverse Output data mode.

Parameters:
hcrc CRC handle
OutputReverseMode Output Data inversion mode. This parameter can be one of the following values:
  • CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion (default value)
  • CRC_OUTPUTDATA_INVERSION_ENABLE bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD)
Return values:
HAL status

Definition at line 185 of file stm32wbxx_hal_crc_ex.c.

References assert_param, HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::Instance, IS_CRC_OUTPUTDATA_INVERSION_MODE, and CRC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | Pol,
 |  | uint32_t | PolyLength
 | ) |  |

Initialize the CRC polynomial if different from default one.

Parameters:
hcrc CRC handle
Pol CRC generating polynomial (7, 8, 16 or 32-bit long). This parameter is written in normal representation, e.g.
  • for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
  • for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
PolyLength CRC polynomial length. This parameter can be one of the following values:
  • CRC_POLYLENGTH_7B 7-bit long CRC (generating polynomial of degree 7)
  • CRC_POLYLENGTH_8B 8-bit long CRC (generating polynomial of degree 8)
  • CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16)
  • CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32)
Return values:
HAL status

Definition at line 89 of file stm32wbxx_hal_crc_ex.c.

References assert_param, CRC_POLYLENGTH_16B, CRC_POLYLENGTH_32B, CRC_POLYLENGTH_7B, CRC_POLYLENGTH_8B, HAL_CRC_LENGTH_16B, HAL_CRC_LENGTH_7B, HAL_CRC_LENGTH_8B, CRC_HandleTypeDef::Instance, and IS_CRC_POL_LENGTH.

Referenced by HAL_CRC_Init().

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STM32WB55xx HAL User Manual: Input Data Inversion Modes

Defines
Input Data Inversion Modes
CRC Extended Exported Constants

Defines

#define | CRC_INPUTDATA_INVERSION_NONE 0x00000000U
#define | CRC_INPUTDATA_INVERSION_BYTE CRC_CR_REV_IN_0
#define | CRC_INPUTDATA_INVERSION_HALFWORD CRC_CR_REV_IN_1
#define | CRC_INPUTDATA_INVERSION_WORD CRC_CR_REV_IN

Define Documentation

#define CRC_INPUTDATA_INVERSION_BYTE CRC_CR_REV_IN_0

Byte-wise input data inversion

Definition at line 49 of file stm32wbxx_hal_crc_ex.h.

#define CRC_INPUTDATA_INVERSION_HALFWORD CRC_CR_REV_IN_1

HalfWord-wise input data inversion

Definition at line 50 of file stm32wbxx_hal_crc_ex.h.

#define CRC_INPUTDATA_INVERSION_NONE 0x00000000U

No input data inversion

Definition at line 48 of file stm32wbxx_hal_crc_ex.h.

#define CRC_INPUTDATA_INVERSION_WORD CRC_CR_REV_IN

Word-wise input data inversion

Definition at line 51 of file stm32wbxx_hal_crc_ex.h.

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STM32WB55xx HAL User Manual: Output Data Inversion Modes

Defines
Output Data Inversion Modes
CRC Extended Exported Constants

Defines

#define | CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U
#define | CRC_OUTPUTDATA_INVERSION_ENABLE CRC_CR_REV_OUT

Define Documentation

#define CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U

No output data inversion

Definition at line 59 of file stm32wbxx_hal_crc_ex.h.

#define CRC_OUTPUTDATA_INVERSION_ENABLE CRC_CR_REV_OUT

Bit-wise output data inversion

Definition at line 60 of file stm32wbxx_hal_crc_ex.h.

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STM32WB55xx HAL User Manual: CRC Extended Exported Macros

Defines
CRC Extended Exported Macros
CRCEx

Defines

#define | __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
Set CRC output reversal.
#define | __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
Unset CRC output reversal.
#define | __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
Set CRC non-default polynomial.

Define Documentation

#define __HAL_CRC_OUTPUTREVERSAL_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))

Unset CRC output reversal.

Parameters:
__HANDLE__ CRC handle
Return values:
None

Definition at line 86 of file stm32wbxx_hal_crc_ex.h.

#define __HAL_CRC_OUTPUTREVERSAL_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)

Set CRC output reversal.

Parameters:
__HANDLE__ CRC handle
Return values:
None

Definition at line 79 of file stm32wbxx_hal_crc_ex.h.

#define __HAL_CRC_POLYNOMIAL_CONFIG | ( | __HANDLE__,
 |  | __POLYNOMIAL__
 | ) | ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))

Set CRC non-default polynomial.

Parameters:
__HANDLE__ | CRC handle
__POLYNOMIAL__ | 7, 8, 16 or 32-bit polynomial
Return values:
None

Definition at line 94 of file stm32wbxx_hal_crc_ex.h.

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STM32WB55xx HAL User Manual: CRC Extended Private Macros

Defines
CRC Extended Private Macros
CRCEx

Defines

#define | IS_CRC_INPUTDATA_INVERSION_MODE(MODE)
#define | IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE)

Define Documentation

#define IS_CRC_INPUTDATA_INVERSION_MODE ( MODE )
Value:
(((MODE) == CRC_INPUTDATA_INVERSION_NONE)     || \
                                                   ((MODE) == CRC_INPUTDATA_INVERSION_BYTE)     || \
                                                   ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
                                                   ((MODE) == CRC_INPUTDATA_INVERSION_WORD))

Definition at line 105 of file stm32wbxx_hal_crc_ex.h.

Referenced by HAL_CRC_Init(), and HAL_CRCEx_Input_Data_Reverse().

#define IS_CRC_OUTPUTDATA_INVERSION_MODE ( MODE )
Value:
(((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
                                                   ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))

Definition at line 110 of file stm32wbxx_hal_crc_ex.h.

Referenced by HAL_CRC_Init(), and HAL_CRCEx_Output_Data_Reverse().

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STM32WB55xx HAL User Manual: HAL CRYP Callback ID enumeration definition

Enumerations
HAL CRYP Callback ID enumeration definition
CRYP Exported Types

HAL CRYP Callback ID enumeration definition. More...

Enumerations

enum HAL_CRYP_CallbackIDTypeDef {
HAL_CRYP_MSPINIT_CB_ID = 0x00U, HAL_CRYP_MSPDEINIT_CB_ID = 0x01U, HAL_CRYP_INPUT_COMPLETE_CB_ID = 0x02U, HAL_CRYP_OUTPUT_COMPLETE_CB_ID = 0x03U,
HAL_CRYP_ERROR_CB_ID = 0x04U
}

Detailed Description

HAL CRYP Callback ID enumeration definition.

Enumeration Type Documentation

enum HAL_CRYP_CallbackIDTypeDef
Enumerator:
HAL_CRYP_MSPINIT_CB_ID

CRYP MspInit callback ID

HAL_CRYP_MSPDEINIT_CB_ID

CRYP MspDeInit callback ID

HAL_CRYP_INPUT_COMPLETE_CB_ID

CRYP Input FIFO transfer completed callback ID

HAL_CRYP_OUTPUT_COMPLETE_CB_ID

CRYP Output FIFO transfer completed callback ID

HAL_CRYP_ERROR_CB_ID

CRYP Error callback ID

Definition at line 202 of file stm32wbxx_hal_cryp.h.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: HAL CRYP Callback pointer definition

Typedefs
HAL CRYP Callback pointer definition
CRYP Exported Types

HAL CRYP Callback pointer definition. More...

Typedefs

typedef void(* pCRYP_CallbackTypeDef )(CRYP_HandleTypeDef *hcryp)

Detailed Description

HAL CRYP Callback pointer definition.

Typedef Documentation

typedef void(* pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp)

pointer to a common CRYP callback function

Definition at line 219 of file stm32wbxx_hal_cryp.h.

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STM32WB55xx HAL User Manual: CRYP Exported Types

Data Structures | Modules | Typedefs | Enumerations
CRYP Exported Types
CRYP

Data Structures

struct | CRYP_ConfigTypeDef
CRYP Init Structure definition. More...
struct | __CRYP_HandleTypeDef
CRYP handle Structure definition. More...

Modules

HAL CRYP Callback ID enumeration definition

HAL CRYP Callback ID enumeration definition.

HAL CRYP Callback pointer definition

HAL CRYP Callback pointer definition.

Typedefs

typedef struct __CRYP_HandleTypeDef | CRYP_HandleTypeDef
CRYP handle Structure definition.

Enumerations

enum | HAL_CRYP_STATETypeDef { HAL_CRYP_STATE_RESET = 0x00U, HAL_CRYP_STATE_READY = 0x01U, HAL_CRYP_STATE_BUSY = 0x02U }
CRYP State Structure definition. More...

Typedef Documentation

typedef struct __CRYP_HandleTypeDef CRYP_HandleTypeDef

CRYP handle Structure definition.

Enumeration Type Documentation

enum HAL_CRYP_STATETypeDef

CRYP State Structure definition.

Enumerator:
HAL_CRYP_STATE_RESET

CRYP not yet initialized or disabled

HAL_CRYP_STATE_READY

CRYP initialized and ready for use

HAL_CRYP_STATE_BUSY

CRYP BUSY, internal processing is ongoing

Definition at line 81 of file stm32wbxx_hal_cryp.h.

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STM32WB55xx HAL User Manual: CRYP_ConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CRYP_ConfigTypeDef Struct Reference
CRYP Exported Types

CRYP Init Structure definition. More...

#include <stm32wbxx_hal_cryp.h>

Data Fields

uint32_t | DataType
uint32_t | KeySize
uint32_t * | pKey
uint32_t * | pInitVect
uint32_t | Algorithm
uint32_t * | Header
uint32_t | HeaderSize
uint32_t * | B0
uint32_t | DataWidthUnit
uint32_t | KeyIVConfigSkip

Detailed Description

CRYP Init Structure definition.

Definition at line 52 of file stm32wbxx_hal_cryp.h.

Field Documentation

uint32_t CRYP_ConfigTypeDef::Algorithm

DES/ TDES Algorithm ECB/CBC AES Algorithm ECB/CBC/CTR/GCM or CCM This parameter can be a value of CRYP Algorithm Mode

Definition at line 61 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AESCCM_Process_IT(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_SetDMAConfig(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_GetConfig(), HAL_CRYP_Init(), HAL_CRYP_IRQHandler(), and HAL_CRYP_SetConfig().

uint32_t* CRYP_ConfigTypeDef::B0

B0 is first authentication block used only in AES CCM mode

Definition at line 68 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), HAL_CRYP_GetConfig(), and HAL_CRYP_SetConfig().

uint32_t CRYP_ConfigTypeDef::DataType

32-bit data, 16-bit data, 8-bit data or 1-bit string. This parameter can be a value of CRYP Data Type

Definition at line 54 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_GCMCCM_SetHeaderPhase(), HAL_CRYP_GetConfig(), HAL_CRYP_Init(), and HAL_CRYP_SetConfig().

uint32_t CRYP_ConfigTypeDef::DataWidthUnit

Data With Unit, this parameter can be value of CRYP Data Width Unit

Definition at line 69 of file stm32wbxx_hal_cryp.h.

Referenced by HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_GetConfig(), and HAL_CRYP_SetConfig().

uint32_t* CRYP_ConfigTypeDef::Header

used only in AES GCM and CCM Algorithm for authentication, GCM : also known as Additional Authentication Data CCM : named B1 composed of the associated data length and Associated Data.

Definition at line 64 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_IT(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetHeaderPhase_IT(), HAL_CRYP_GetConfig(), and HAL_CRYP_SetConfig().

uint32_t CRYP_ConfigTypeDef::HeaderSize

The size of header buffer in word

Definition at line 67 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_IT(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetHeaderPhase_IT(), HAL_CRYP_GetConfig(), HAL_CRYP_IRQHandler(), HAL_CRYP_SetConfig(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

uint32_t CRYP_ConfigTypeDef::KeyIVConfigSkip

CRYP peripheral Key and IV configuration skip, to config Key and Initialization Vector only once and to skip configuration for consecutive processings. This parameter can be a value of CRYP Key and IV Configuration Skip Mode

Definition at line 70 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), HAL_CRYP_Encrypt_DMA(), and HAL_CRYP_Init().

uint32_t CRYP_ConfigTypeDef::KeySize

Used only in AES mode : 128, 192 or 256 bit key length in CRYP1. 128 or 256 bit key length in TinyAES This parameter can be a value of CRYP Key Size

Definition at line 56 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_GetConfig(), HAL_CRYP_Init(), and HAL_CRYP_SetConfig().

uint32_t* CRYP_ConfigTypeDef::pInitVect

The initialization vector used also as initialization counter in CTR mode

Definition at line 59 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_GetConfig(), and HAL_CRYP_SetConfig().

uint32_t* CRYP_ConfigTypeDef::pKey

The key used for encryption/decryption

Definition at line 58 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_SetKey(), HAL_CRYP_GetConfig(), and HAL_CRYP_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_cryp.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: __CRYP_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__CRYP_HandleTypeDef Struct Reference
CRYP Exported Types

CRYP handle Structure definition. More...

#include <stm32wbxx_hal_cryp.h>

Data Fields

AES_TypeDef * | Instance
CRYP_ConfigTypeDef Init
FunctionalState | AutoKeyDerivation
uint32_t * | pCrypInBuffPtr
uint32_t * | pCrypOutBuffPtr
__IO uint16_t | CrypHeaderCount
__IO uint16_t | CrypInCount
__IO uint16_t | CrypOutCount
uint16_t | Size
uint32_t | Phase
DMA_HandleTypeDef * hdmain
DMA_HandleTypeDef * hdmaout
HAL_LockTypeDef | Lock
__IO HAL_CRYP_STATETypeDef | State
__IO uint32_t | ErrorCode
uint32_t | KeyIVConfig
uint32_t | SizesSum
void(* | InCpltCallback )(struct __CRYP_HandleTypeDef *hcryp)
void(* | OutCpltCallback )(struct __CRYP_HandleTypeDef *hcryp)
void(* | ErrorCallback )(struct __CRYP_HandleTypeDef *hcryp)
void(* | MspInitCallback )(struct __CRYP_HandleTypeDef *hcryp)
void(* | MspDeInitCallback )(struct __CRYP_HandleTypeDef *hcryp)

Detailed Description

CRYP handle Structure definition.

Definition at line 106 of file stm32wbxx_hal_cryp.h.

Field Documentation

FunctionalState __CRYP_HandleTypeDef::AutoKeyDerivation

Used only in TinyAES to allow to bypass or not key write-up before decryption. This parameter can be a value of ENABLE/DISABLE

Definition at line 115 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), HAL_CRYPEx_DisableAutoKeyDerivation(), and HAL_CRYPEx_EnableAutoKeyDerivation().

__IO uint16_t __CRYP_HandleTypeDef::CrypHeaderCount

Counter of header data

Definition at line 122 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetHeaderPhase_IT(), HAL_CRYP_DeInit(), and HAL_CRYP_IRQHandler().

__IO uint16_t __CRYP_HandleTypeDef::CrypInCount

Counter of input data

Definition at line 124 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_DeInit(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), and HAL_CRYP_Encrypt_IT().

__IO uint16_t __CRYP_HandleTypeDef::CrypOutCount

Counter of output data

Definition at line 126 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Encrypt(), CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetPayloadPhase_IT(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_DeInit(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), and HAL_CRYP_Encrypt_IT().

void(* __CRYP_HandleTypeDef::ErrorCallback)(struct __CRYP_HandleTypeDef *hcryp)

CRYP Error callback

Definition at line 152 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process_DMA(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_DMAError(), CRYP_DMAOutCplt(), CRYP_SetDMAConfig(), HAL_CRYP_Init(), HAL_CRYP_RegisterCallback(), and HAL_CRYP_UnRegisterCallback().

__IO uint32_t __CRYP_HandleTypeDef::ErrorCode

CRYP peripheral error code

Definition at line 140 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_DMAError(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_SetDMAConfig(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_GetConfig(), HAL_CRYP_GetError(), HAL_CRYP_Init(), HAL_CRYP_IRQHandler(), HAL_CRYP_RegisterCallback(), HAL_CRYP_SetConfig(), HAL_CRYP_UnRegisterCallback(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), HAL_CRYPEx_AESGCM_GenerateAuthTAG(), HAL_CRYPEx_DisableAutoKeyDerivation(), and HAL_CRYPEx_EnableAutoKeyDerivation().

DMA_HandleTypeDef* __CRYP_HandleTypeDef::hdmain

CRYP In DMA handle parameters

Definition at line 132 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_SetDMAConfig().

DMA_HandleTypeDef* __CRYP_HandleTypeDef::hdmaout

CRYP Out DMA handle parameters

Definition at line 134 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_SetDMAConfig().

void(* __CRYP_HandleTypeDef::InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp)

CRYP Input FIFO transfer completed callback

Definition at line 150 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_AES_IT(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_IT(), CRYP_DMAInCplt(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), HAL_CRYP_Init(), HAL_CRYP_RegisterCallback(), and HAL_CRYP_UnRegisterCallback().

CRYP_ConfigTypeDef __CRYP_HandleTypeDef::Init

CRYP required parameters

Definition at line 113 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_SetDMAConfig(), CRYP_SetKey(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_GetConfig(), HAL_CRYP_Init(), HAL_CRYP_IRQHandler(), HAL_CRYP_SetConfig(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

AES_TypeDef* __CRYP_HandleTypeDef::Instance

AES Register base address

Definition at line 111 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_DMAInCplt(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_SetDMAConfig(), CRYP_SetKey(), CRYP_WaitOnCCFlag(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_Init(), HAL_CRYP_IRQHandler(), HAL_CRYP_SetConfig(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

uint32_t __CRYP_HandleTypeDef::KeyIVConfig

CRYP peripheral Key and IV configuration flag, used when configuration can be skipped

Definition at line 142 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), HAL_CRYP_Encrypt_DMA(), and HAL_CRYP_Init().

HAL_LockTypeDef __CRYP_HandleTypeDef::Lock

CRYP locking object

Definition at line 136 of file stm32wbxx_hal_cryp.h.

Referenced by HAL_CRYP_Init().

void(* __CRYP_HandleTypeDef::MspDeInitCallback)(struct __CRYP_HandleTypeDef *hcryp)

CRYP Msp DeInit callback

Definition at line 155 of file stm32wbxx_hal_cryp.h.

Referenced by HAL_CRYP_DeInit(), HAL_CRYP_RegisterCallback(), and HAL_CRYP_UnRegisterCallback().

void(* __CRYP_HandleTypeDef::MspInitCallback)(struct __CRYP_HandleTypeDef *hcryp)

CRYP Msp Init callback

Definition at line 154 of file stm32wbxx_hal_cryp.h.

Referenced by HAL_CRYP_Init(), HAL_CRYP_RegisterCallback(), and HAL_CRYP_UnRegisterCallback().

void(* __CRYP_HandleTypeDef::OutCpltCallback)(struct __CRYP_HandleTypeDef *hcryp)

CRYP Output FIFO transfer completed callback

Definition at line 151 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_AES_IT(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetPayloadPhase_IT(), HAL_CRYP_Init(), HAL_CRYP_RegisterCallback(), and HAL_CRYP_UnRegisterCallback().

uint32_t* __CRYP_HandleTypeDef::pCrypInBuffPtr

Pointer to CRYP processing (encryption, decryption,...) buffer

Definition at line 118 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt_IT(), CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), and HAL_CRYP_Encrypt_IT().

uint32_t* __CRYP_HandleTypeDef::pCrypOutBuffPtr

Pointer to CRYP processing (encryption, decryption,...) buffer

Definition at line 120 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt_DMA(), CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetPayloadPhase_IT(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), and HAL_CRYP_Encrypt_IT().

uint32_t __CRYP_HandleTypeDef::Phase

CRYP peripheral phase

Definition at line 130 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AES_IT(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_DeInit(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_Init(), HAL_CRYP_SetConfig(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

uint16_t __CRYP_HandleTypeDef::Size

length of input data in words

Definition at line 128 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AES_IT(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), and HAL_CRYP_Encrypt_IT().

uint32_t __CRYP_HandleTypeDef::SizesSum

Sum of successive payloads lengths (in bytes), stored for a single signature computation after several messages processing

Definition at line 145 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

__IO HAL_CRYP_STATETypeDef __CRYP_HandleTypeDef::State

CRYP peripheral state

Definition at line 138 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_DMAError(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_DeInit(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_GetConfig(), HAL_CRYP_GetState(), HAL_CRYP_Init(), HAL_CRYP_RegisterCallback(), HAL_CRYP_SetConfig(), HAL_CRYP_UnRegisterCallback(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), HAL_CRYPEx_AESGCM_GenerateAuthTAG(), HAL_CRYPEx_DisableAutoKeyDerivation(), and HAL_CRYPEx_EnableAutoKeyDerivation().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_cryp.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CRYP Error Definition

Defines
CRYP Error Definition
CRYP Exported Constants

Defines

#define | HAL_CRYP_ERROR_NONE 0x00000000U
#define | HAL_CRYP_ERROR_WRITE 0x00000001U
#define | HAL_CRYP_ERROR_READ 0x00000002U
#define | HAL_CRYP_ERROR_DMA 0x00000004U
#define | HAL_CRYP_ERROR_BUSY 0x00000008U
#define | HAL_CRYP_ERROR_TIMEOUT 0x00000010U
#define | HAL_CRYP_ERROR_NOT_SUPPORTED 0x00000020U
#define | HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U
#define | HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U)

Define Documentation

#define HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U

Sequence are not respected only for GCM or CCM

Definition at line 246 of file stm32wbxx_hal_cryp.h.

Referenced by HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

#define HAL_CRYP_ERROR_BUSY 0x00000008U

Busy flag error

Definition at line 243 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_AES_IT(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_GetConfig(), HAL_CRYP_SetConfig(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), HAL_CRYPEx_AESGCM_GenerateAuthTAG(), HAL_CRYPEx_DisableAutoKeyDerivation(), and HAL_CRYPEx_EnableAutoKeyDerivation().

#define HAL_CRYP_ERROR_DMA 0x00000004U

DMA error

Definition at line 242 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_DMAError(), and CRYP_SetDMAConfig().

#define HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U)

Invalid Callback error

Definition at line 248 of file stm32wbxx_hal_cryp.h.

Referenced by HAL_CRYP_RegisterCallback(), and HAL_CRYP_UnRegisterCallback().

#define HAL_CRYP_ERROR_NONE 0x00000000U

No error

Definition at line 239 of file stm32wbxx_hal_cryp.h.

Referenced by HAL_CRYP_Init(), and HAL_CRYP_SetConfig().

#define HAL_CRYP_ERROR_NOT_SUPPORTED 0x00000020U

Not supported mode

Definition at line 245 of file stm32wbxx_hal_cryp.h.

Referenced by HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), and HAL_CRYP_Encrypt_IT().

#define HAL_CRYP_ERROR_READ 0x00000002U

Read error

Definition at line 241 of file stm32wbxx_hal_cryp.h.

Referenced by HAL_CRYP_IRQHandler().

#define HAL_CRYP_ERROR_TIMEOUT 0x00000010U

Timeout error

Definition at line 244 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

#define HAL_CRYP_ERROR_WRITE 0x00000001U

Write error

Definition at line 240 of file stm32wbxx_hal_cryp.h.

Referenced by HAL_CRYP_IRQHandler().

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CRYP Data Width Unit

Defines
CRYP Data Width Unit
CRYP Exported Constants

Defines

#define | CRYP_DATAWIDTHUNIT_WORD 0x00000000U
#define | CRYP_DATAWIDTHUNIT_BYTE 0x00000001U

Define Documentation

#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U

By default, size unit is byte

Definition at line 260 of file stm32wbxx_hal_cryp.h.

#define CRYP_DATAWIDTHUNIT_WORD 0x00000000U

By default, size unit is word

Definition at line 259 of file stm32wbxx_hal_cryp.h.

Referenced by HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), and HAL_CRYP_Encrypt_IT().

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CRYP Algorithm Mode

Defines
CRYP Algorithm Mode
CRYP Exported Constants

Defines

#define | CRYP_AES_ECB 0x00000000U
#define | CRYP_AES_CBC AES_CR_CHMOD_0
#define | CRYP_AES_CTR AES_CR_CHMOD_1
#define | CRYP_AES_GCM_GMAC (AES_CR_CHMOD_0 | AES_CR_CHMOD_1)
#define | CRYP_AES_CCM AES_CR_CHMOD_2

Define Documentation

#define CRYP_AES_CBC AES_CR_CHMOD_0

Cipher block chaining algorithm

Definition at line 271 of file stm32wbxx_hal_cryp.h.

Referenced by HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), and HAL_CRYP_Encrypt_IT().

#define CRYP_AES_CCM AES_CR_CHMOD_2

Counter with Cipher Mode

Definition at line 274 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_AESCCM_Process_IT(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), and HAL_CRYP_IRQHandler().

#define CRYP_AES_CTR AES_CR_CHMOD_1

Counter mode chaining algorithm

Definition at line 272 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), and HAL_CRYP_Encrypt_IT().

#define CRYP_AES_ECB 0x00000000U

Electronic codebook chaining algorithm

Definition at line 270 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), and HAL_CRYP_Encrypt_IT().

#define CRYP_AES_GCM_GMAC (AES_CR_CHMOD_0 | AES_CR_CHMOD_1)

Galois counter mode - Galois message authentication code

Definition at line 273 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_AESCCM_Process_IT(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_SetDMAConfig(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), and HAL_CRYP_IRQHandler().

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CRYP Key Size

Defines
CRYP Key Size
CRYP Exported Constants

Defines

#define | CRYP_KEYSIZE_128B 0x00000000U
#define | CRYP_KEYSIZE_256B AES_CR_KEYSIZE

Define Documentation

#define CRYP_KEYSIZE_128B 0x00000000U

128-bit long key

Definition at line 284 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_SetKey().

#define CRYP_KEYSIZE_256B AES_CR_KEYSIZE

256-bit long key

Definition at line 285 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_SetKey().

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CRYP Data Type

Defines
CRYP Data Type
CRYP Exported Constants

Defines

#define | CRYP_DATATYPE_32B 0x00000000U
#define | CRYP_DATATYPE_16B AES_CR_DATATYPE_0
#define | CRYP_DATATYPE_8B AES_CR_DATATYPE_1
#define | CRYP_DATATYPE_1B AES_CR_DATATYPE

Define Documentation

#define CRYP_DATATYPE_16B AES_CR_DATATYPE_0

16-bit data type (half-word swapping)

Definition at line 296 of file stm32wbxx_hal_cryp.h.

#define CRYP_DATATYPE_1B AES_CR_DATATYPE

1-bit data type (bit swapping)

Definition at line 298 of file stm32wbxx_hal_cryp.h.

#define CRYP_DATATYPE_32B 0x00000000U

32-bit data type (no swapping)

Definition at line 295 of file stm32wbxx_hal_cryp.h.

#define CRYP_DATATYPE_8B AES_CR_DATATYPE_1

8-bit data type (byte swapping)

Definition at line 297 of file stm32wbxx_hal_cryp.h.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CRYP Interrupt

Defines
CRYP Interrupt
CRYP Exported Constants

Defines

#define | CRYP_IT_CCFIE AES_CR_CCFIE
#define | CRYP_IT_ERRIE AES_CR_ERRIE
#define | CRYP_IT_WRERR AES_SR_WRERR
#define | CRYP_IT_RDERR AES_SR_RDERR
#define | CRYP_IT_CCF AES_SR_CCF

Define Documentation

#define CRYP_IT_CCF AES_SR_CCF

Computation completed

Definition at line 312 of file stm32wbxx_hal_cryp.h.

Referenced by HAL_CRYP_IRQHandler().

#define CRYP_IT_CCFIE AES_CR_CCFIE

Computation Complete interrupt enable

Definition at line 308 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt_IT(), CRYP_AES_IT(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_IT(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), HAL_CRYP_IRQHandler(), and HAL_CRYPEx_AESCCM_GenerateAuthTAG().

#define CRYP_IT_ERRIE AES_CR_ERRIE

Error interrupt enable

Definition at line 309 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt_IT(), CRYP_AES_IT(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_IT(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), HAL_CRYP_IRQHandler(), and HAL_CRYPEx_AESCCM_GenerateAuthTAG().

#define CRYP_IT_RDERR AES_SR_RDERR

Read Error

Definition at line 311 of file stm32wbxx_hal_cryp.h.

Referenced by HAL_CRYP_IRQHandler().

#define CRYP_IT_WRERR AES_SR_WRERR

Write Error

Definition at line 310 of file stm32wbxx_hal_cryp.h.

Referenced by HAL_CRYP_IRQHandler().

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CRYP Flags

Defines
CRYP Flags
CRYP Exported Constants

Defines

#define | CRYP_FLAG_BUSY AES_SR_BUSY
#define | CRYP_FLAG_WRERR AES_SR_WRERR
#define | CRYP_FLAG_RDERR AES_SR_RDERR
#define | CRYP_FLAG_CCF AES_SR_CCF
#define | CRYP_CCF_CLEAR AES_CR_CCFC
#define | CRYP_ERR_CLEAR AES_CR_ERRC

Define Documentation

#define CRYP_CCF_CLEAR AES_CR_CCFC

Computation Complete Flag Clear

Definition at line 328 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_DMAError(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), HAL_CRYP_IRQHandler(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

#define CRYP_ERR_CLEAR AES_CR_ERRC

Error Flag Clear

Definition at line 329 of file stm32wbxx_hal_cryp.h.

Referenced by HAL_CRYP_SetConfig().

#define CRYP_FLAG_BUSY AES_SR_BUSY

GCM process suspension forbidden

Definition at line 323 of file stm32wbxx_hal_cryp.h.

#define CRYP_FLAG_CCF AES_SR_CCF

Computation completed

Definition at line 326 of file stm32wbxx_hal_cryp.h.

#define CRYP_FLAG_RDERR AES_SR_RDERR

Read error

Definition at line 325 of file stm32wbxx_hal_cryp.h.

#define CRYP_FLAG_WRERR AES_SR_WRERR

Write Error

Definition at line 324 of file stm32wbxx_hal_cryp.h.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CRYP Key and IV Configuration Skip Mode

Defines
CRYP Key and IV Configuration Skip Mode
CRYP Exported Constants

Defines

#define | CRYP_KEYIVCONFIG_ALWAYS 0x00000000U
#define | CRYP_KEYIVCONFIG_ONCE 0x00000001U

Define Documentation

#define CRYP_KEYIVCONFIG_ALWAYS 0x00000000U

Peripheral Key and IV configuration to do systematically

Definition at line 339 of file stm32wbxx_hal_cryp.h.

#define CRYP_KEYIVCONFIG_ONCE 0x00000001U

Peripheral Key and IV configuration to do only once

Definition at line 340 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), and HAL_CRYP_Encrypt_DMA().

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CRYP Exported Macros

Defines
CRYP Exported Macros
CRYP

Defines

#define | __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__)
Reset CRYP handle state.
#define | __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= AES_CR_EN)
Enable/Disable the CRYP peripheral.
#define | __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~AES_CR_EN)
#define | CRYP_FLAG_MASK 0x0000001FU
Check whether the specified CRYP status flag is set or not.
#define | __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
#define | __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT((__HANDLE__)->Instance->CR, (__FLAG__))
Clear the CRYP pending status flag.
#define | __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified CRYP interrupt source is enabled or not.
#define | __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified CRYP interrupt is set or not.
#define | __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
Enable the CRYP interrupt.
#define | __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
Disable the CRYP interrupt.

Define Documentation

#define __HAL_CRYP_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | SET_BIT((__HANDLE__)->Instance->CR, (__FLAG__))

Clear the CRYP pending status flag.

Parameters:
__HANDLE__ specifies the CRYP handle.
__FLAG__ specifies the flag to clear. This parameter can be one of the following values:
  • CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
  • CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
Return values:
None

Definition at line 412 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_DMAError(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), HAL_CRYP_IRQHandler(), HAL_CRYP_SetConfig(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

#define __HAL_CRYP_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~AES_CR_EN)

Definition at line 377 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), HAL_CRYP_DeInit(), HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

#define __HAL_CRYP_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))

Disable the CRYP interrupt.

Parameters:
__HANDLE__ specifies the CRYP handle.
__INTERRUPT__ CRYP Interrupt. This parameter can be one of the following values for TinyAES:
  • CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
  • CRYP_IT_CCFIE Computation Complete interrupt This parameter can be one of the following values for CRYP: @ CRYP_IT_INI : Input FIFO service interrupt mask. @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
Return values:
None

Definition at line 469 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_AES_IT(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_IT(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), and HAL_CRYPEx_AESCCM_GenerateAuthTAG().

#define __HAL_CRYP_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= AES_CR_EN)

Enable/Disable the CRYP peripheral.

Parameters:
__HANDLE__ specifies the CRYP handle.
Return values:
None

Definition at line 376 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), and CRYP_SetDMAConfig().

#define __HAL_CRYP_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))

Enable the CRYP interrupt.

Parameters:
__HANDLE__ specifies the CRYP handle.
__INTERRUPT__ CRYP Interrupt. This parameter can be one of the following values for TinyAES:
  • CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
  • CRYP_IT_CCFIE Computation Complete interrupt This parameter can be one of the following values for CRYP: @ CRYP_IT_INI : Input FIFO service interrupt mask. @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
Return values:
None

Definition at line 454 of file stm32wbxx_hal_cryp.h.

Referenced by CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt_IT(), CRYP_AESCCM_Process_IT(), and CRYP_AESGCM_Process_IT().

#define __HAL_CRYP_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))

Definition at line 401 of file stm32wbxx_hal_cryp.h.

Referenced by HAL_CRYP_IRQHandler().

#define __HAL_CRYP_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))

Check whether the specified CRYP interrupt is set or not.

Parameters:
__HANDLE__ specifies the CRYP handle.
__INTERRUPT__ specifies the interrupt to check. This parameter can be one of the following values for TinyAES:
  • CRYP_IT_WRERR Write Error
  • CRYP_IT_RDERR Read Error
  • CRYP_IT_CCF Computation Complete This parameter can be one of the following values for CRYP:
  • CRYP_IT_INI: Input FIFO service masked interrupt status
  • CRYP_IT_OUTI: Output FIFO service masked interrupt status
Return values:
The state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 439 of file stm32wbxx_hal_cryp.h.

#define __HAL_CRYP_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))

Check whether the specified CRYP interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the CRYP handle.
__INTERRUPT__ CRYP interrupt source to check This parameter can be one of the following values for TinyAES:
  • CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
  • CRYP_IT_CCFIE Computation Complete interrupt
Return values:
State of interruption (TRUE or FALSE).

Definition at line 424 of file stm32wbxx_hal_cryp.h.

Referenced by HAL_CRYP_IRQHandler().

#define __HAL_CRYP_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{\
                                                      (__HANDLE__)->State = HAL_CRYP_STATE_RESET;\
                                                      (__HANDLE__)->MspInitCallback = NULL;\
                                                      (__HANDLE__)->MspDeInitCallback = NULL;\
                                                     }while(0U)

Reset CRYP handle state.

Parameters:
__HANDLE__ specifies the CRYP handle.
Return values:
None

Definition at line 361 of file stm32wbxx_hal_cryp.h.

#define CRYP_FLAG_MASK 0x0000001FU

Check whether the specified CRYP status flag is set or not.

Parameters:
__HANDLE__ specifies the CRYP handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values for TinyAES:
  • CRYP_FLAG_BUSY GCM process suspension forbidden
  • CRYP_IT_WRERR Write Error
  • CRYP_IT_RDERR Read Error
  • CRYP_IT_CCF Computation Complete This parameter can be one of the following values for CRYP:
  • CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data or a key preparation (for AES decryption).
  • CRYP_FLAG_IFEM: Input FIFO is empty
  • CRYP_FLAG_IFNF: Input FIFO is not full
  • CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending
  • CRYP_FLAG_OFNE: Output FIFO is not empty
  • CRYP_FLAG_OFFU: Output FIFO is full
  • CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
Return values:
The state of __FLAG__ (TRUE or FALSE).

Definition at line 400 of file stm32wbxx_hal_cryp.h.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CRYP Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_CRYP_Init (CRYP_HandleTypeDef *hcryp)
Initializes the CRYP according to the specified parameters in the CRYP_ConfigTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_CRYP_DeInit (CRYP_HandleTypeDef *hcryp)
De-Initializes the CRYP peripheral.
HAL_StatusTypeDef | HAL_CRYP_SetConfig (CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
Configure the CRYP according to the specified parameters in the CRYP_ConfigTypeDef.
HAL_StatusTypeDef | HAL_CRYP_GetConfig (CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
Get CRYP Configuration parameters in associated handle.
__weak void | HAL_CRYP_MspInit (CRYP_HandleTypeDef *hcryp)
Initializes the CRYP MSP.
__weak void | HAL_CRYP_MspDeInit (CRYP_HandleTypeDef *hcryp)
DeInitializes CRYP MSP.
HAL_StatusTypeDef | HAL_CRYP_RegisterCallback (CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback)
Register a User CRYP Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_CRYP_UnRegisterCallback (CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID)
Unregister an CRYP Callback CRYP callback is redirected to the weak predefined callback.

Detailed Description

Initialization and Configuration functions.

  ========================================================================================
     ##### Initialization, de-initialization and Set and Get configuration functions #####
  ========================================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the CRYP
      (+) DeInitialize the CRYP
      (+) Initialize the CRYP MSP
      (+) DeInitialize the CRYP MSP
      (+) configure CRYP (HAL_CRYP_SetConfig) with the specified parameters in the CRYP_ConfigTypeDef
          Parameters which are configured in This section are :
          (+) Key size
          (+) Data Type : 32,16, 8 or 1bit
          (+) AlgoMode :
              - for CRYP1 peripheral :
                 ECB and CBC in DES/TDES Standard
                 ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard.
              - for TinyAES2 peripheral, only ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard are supported.
      (+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef

Function Documentation

HAL_StatusTypeDef HAL_CRYP_DeInit ( CRYP_HandleTypeDef * hcryp )

De-Initializes the CRYP peripheral.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 509 of file stm32wbxx_hal_cryp.c.

References __HAL_CRYP_DISABLE, CRYP_PHASE_READY, __CRYP_HandleTypeDef::CrypHeaderCount, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, HAL_CRYP_MspDeInit(), HAL_CRYP_STATE_RESET, __CRYP_HandleTypeDef::MspDeInitCallback, __CRYP_HandleTypeDef::Phase, and __CRYP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRYP_GetConfig | ( | CRYP_HandleTypeDef * | hcryp,
 |  | CRYP_ConfigTypeDef * | pConf
 | ) |  |

Get CRYP Configuration parameters in associated handle.

Parameters:
pConf | pointer to a CRYP_ConfigTypeDef structure
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 633 of file stm32wbxx_hal_cryp.c.

References CRYP_ConfigTypeDef::Algorithm, CRYP_ConfigTypeDef::B0, CRYP_ConfigTypeDef::DataType, CRYP_ConfigTypeDef::DataWidthUnit, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, CRYP_ConfigTypeDef::Header, CRYP_ConfigTypeDef::HeaderSize, __CRYP_HandleTypeDef::Init, CRYP_ConfigTypeDef::KeySize, CRYP_ConfigTypeDef::pInitVect, CRYP_ConfigTypeDef::pKey, and __CRYP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRYP_Init ( CRYP_HandleTypeDef * hcryp )

Initializes the CRYP according to the specified parameters in the CRYP_ConfigTypeDef and creates the associated handle.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 441 of file stm32wbxx_hal_cryp.c.

References CRYP_ConfigTypeDef::Algorithm, assert_param, CRYP_PHASE_READY, CRYP_ConfigTypeDef::DataType, __CRYP_HandleTypeDef::ErrorCallback, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_NONE, HAL_CRYP_ErrorCallback(), HAL_CRYP_InCpltCallback(), HAL_CRYP_MspInit(), HAL_CRYP_OutCpltCallback(), HAL_CRYP_STATE_READY, HAL_CRYP_STATE_RESET, __CRYP_HandleTypeDef::InCpltCallback, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, IS_CRYP_ALGORITHM, IS_CRYP_DATATYPE, IS_CRYP_INIT, IS_CRYP_KEYSIZE, __CRYP_HandleTypeDef::KeyIVConfig, CRYP_ConfigTypeDef::KeyIVConfigSkip, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::Lock, __CRYP_HandleTypeDef::MspInitCallback, __CRYP_HandleTypeDef::OutCpltCallback, __CRYP_HandleTypeDef::Phase, and __CRYP_HandleTypeDef::State.

void HAL_CRYP_MspDeInit ( CRYP_HandleTypeDef * hcryp )

DeInitializes CRYP MSP.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
None

Definition at line 701 of file stm32wbxx_hal_cryp.c.

Referenced by HAL_CRYP_DeInit(), and HAL_CRYP_UnRegisterCallback().

void HAL_CRYP_MspInit ( CRYP_HandleTypeDef * hcryp )

Initializes the CRYP MSP.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
None

Definition at line 685 of file stm32wbxx_hal_cryp.c.

Referenced by HAL_CRYP_Init(), and HAL_CRYP_UnRegisterCallback().

HAL_StatusTypeDef HAL_CRYP_RegisterCallback | ( | CRYP_HandleTypeDef * | hcryp,
 |  | HAL_CRYP_CallbackIDTypeDef | CallbackID,
 |  | pCRYP_CallbackTypeDef | pCallback
 | ) |  |

Register a User CRYP Callback To be used instead of the weak predefined callback.

Parameters:
hcryp | cryp handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
  • HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
  • HAL_CRYP_ERROR_CB_ID Error callback ID
  • HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
  • HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
status

Definition at line 726 of file stm32wbxx_hal_cryp.c.

References __CRYP_HandleTypeDef::ErrorCallback, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_CB_ID, HAL_CRYP_ERROR_INVALID_CALLBACK, HAL_CRYP_INPUT_COMPLETE_CB_ID, HAL_CRYP_MSPDEINIT_CB_ID, HAL_CRYP_MSPINIT_CB_ID, HAL_CRYP_OUTPUT_COMPLETE_CB_ID, HAL_CRYP_STATE_READY, HAL_CRYP_STATE_RESET, __CRYP_HandleTypeDef::InCpltCallback, __CRYP_HandleTypeDef::MspDeInitCallback, __CRYP_HandleTypeDef::MspInitCallback, __CRYP_HandleTypeDef::OutCpltCallback, and __CRYP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRYP_SetConfig | ( | CRYP_HandleTypeDef * | hcryp,
 |  | CRYP_ConfigTypeDef * | pConf
 | ) |  |

Configure the CRYP according to the specified parameters in the CRYP_ConfigTypeDef.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure
pConf | pointer to a CRYP_ConfigTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 562 of file stm32wbxx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, CRYP_ConfigTypeDef::Algorithm, assert_param, CRYP_ConfigTypeDef::B0, CRYP_ERR_CLEAR, CRYP_PHASE_READY, CRYP_ConfigTypeDef::DataType, CRYP_ConfigTypeDef::DataWidthUnit, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ERROR_NONE, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, CRYP_ConfigTypeDef::Header, CRYP_ConfigTypeDef::HeaderSize, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, IS_CRYP_ALGORITHM, IS_CRYP_DATATYPE, IS_CRYP_KEYSIZE, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, CRYP_ConfigTypeDef::pKey, and __CRYP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback | ( | CRYP_HandleTypeDef * | hcryp,
 |  | HAL_CRYP_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an CRYP Callback CRYP callback is redirected to the weak predefined callback.

Parameters:
hcryp cryp handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
  • HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
  • HAL_CRYP_ERROR_CB_ID Error callback ID
  • HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
  • HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
status

Definition at line 819 of file stm32wbxx_hal_cryp.c.

References __CRYP_HandleTypeDef::ErrorCallback, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_CB_ID, HAL_CRYP_ERROR_INVALID_CALLBACK, HAL_CRYP_ErrorCallback(), HAL_CRYP_InCpltCallback(), HAL_CRYP_INPUT_COMPLETE_CB_ID, HAL_CRYP_MspDeInit(), HAL_CRYP_MSPDEINIT_CB_ID, HAL_CRYP_MspInit(), HAL_CRYP_MSPINIT_CB_ID, HAL_CRYP_OutCpltCallback(), HAL_CRYP_OUTPUT_COMPLETE_CB_ID, HAL_CRYP_STATE_READY, HAL_CRYP_STATE_RESET, __CRYP_HandleTypeDef::InCpltCallback, __CRYP_HandleTypeDef::MspDeInitCallback, __CRYP_HandleTypeDef::MspInitCallback, __CRYP_HandleTypeDef::OutCpltCallback, and __CRYP_HandleTypeDef::State.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Encryption Decryption functions

Functions
Encryption Decryption functions
CRYP Exported Functions

Encryption Decryption functions. More...

Functions

HAL_StatusTypeDef | HAL_CRYP_Encrypt (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
Encryption mode.
HAL_StatusTypeDef | HAL_CRYP_Decrypt (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
Decryption mode.
HAL_StatusTypeDef | HAL_CRYP_Encrypt_IT (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Encryption in interrupt mode.
HAL_StatusTypeDef | HAL_CRYP_Decrypt_IT (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Decryption in interrupt mode.
HAL_StatusTypeDef | HAL_CRYP_Encrypt_DMA (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Encryption in DMA mode.
HAL_StatusTypeDef | HAL_CRYP_Decrypt_DMA (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Decryption in DMA mode.

Detailed Description

Encryption Decryption functions.

  ==============================================================================
                      ##### Encrypt Decrypt  functions #####
  ==============================================================================
    [..]  This section provides API allowing to Encrypt/Decrypt Data following
          Standard DES/TDES or AES, and Algorithm configured by the user:
      (+) Standard DES/TDES only supported by CRYP1 peripheral, below list of Algorithm supported :
           - Electronic Code Book(ECB)
           - Cipher Block Chaining (CBC)
      (+) Standard AES  supported by CRYP1 peripheral & TinyAES, list of Algorithm supported:
           - Electronic Code Book(ECB)
           - Cipher Block Chaining (CBC)
           - Counter mode (CTR)
           - Cipher Block Chaining (CBC)
           - Counter mode (CTR)
           - Galois/counter mode (GCM)
           - Counter with Cipher Block Chaining-Message(CCM)
    [..]  Three processing functions are available:
      (+) Polling mode : HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
      (+) Interrupt mode : HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
      (+) DMA mode : HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA

Function Documentation

HAL_StatusTypeDef HAL_CRYP_Decrypt | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t * | Input,
 |  | uint16_t | Size,
 |  | uint32_t * | Output,
 |  | uint32_t | Timeout
 | ) |  |

Decryption mode.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Input | Pointer to the input buffer (ciphertext )
Size | Length of the plaintext buffer in word.
Output | Pointer to the output buffer(plaintext)
Timeout | Specify Timeout value
Return values:
HAL status

Definition at line 1293 of file stm32wbxx_hal_cryp.c.

References assert_param, CRYP_AES_CBC, CRYP_AES_CCM, CRYP_AES_CTR, CRYP_AES_Decrypt(), CRYP_AES_ECB, CRYP_AES_GCM_GMAC, CRYP_AESCCM_Process(), CRYP_AESGCM_Process(), CRYP_DATAWIDTHUNIT_WORD, CRYP_OPERATINGMODE_DECRYPT, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, CRYP_ConfigTypeDef::DataWidthUnit, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ERROR_NOT_SUPPORTED, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, IS_CRYP_BUFFERSIZE, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t * | Input,
 |  | uint16_t | Size,
 |  | uint32_t * | Output
 | ) |  |

Decryption in DMA mode.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Input | Pointer to the input buffer (ciphertext )
Size | Length of the plaintext buffer in word
Output | Pointer to the output buffer(plaintext)
Return values:
HAL status

Definition at line 1738 of file stm32wbxx_hal_cryp.c.

References assert_param, CRYP_AES_CBC, CRYP_AES_CCM, CRYP_AES_CTR, CRYP_AES_Decrypt_DMA(), CRYP_AES_ECB, CRYP_AES_GCM_GMAC, CRYP_AESCCM_Process_DMA(), CRYP_AESGCM_Process_DMA(), CRYP_DATAWIDTHUNIT_WORD, CRYP_OPERATINGMODE_DECRYPT, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, CRYP_ConfigTypeDef::DataWidthUnit, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ERROR_NOT_SUPPORTED, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, IS_CRYP_BUFFERSIZE, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRYP_Decrypt_IT | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t * | Input,
 |  | uint16_t | Size,
 |  | uint32_t * | Output
 | ) |  |

Decryption in interrupt mode.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Input | Pointer to the input buffer (ciphertext )
Size | Length of the plaintext buffer in word.
Output | Pointer to the output buffer(plaintext)
Return values:
HAL status

Definition at line 1502 of file stm32wbxx_hal_cryp.c.

References assert_param, CRYP_AES_CBC, CRYP_AES_CCM, CRYP_AES_CTR, CRYP_AES_Decrypt_IT(), CRYP_AES_ECB, CRYP_AES_GCM_GMAC, CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_IT(), CRYP_DATAWIDTHUNIT_WORD, CRYP_OPERATINGMODE_DECRYPT, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, CRYP_ConfigTypeDef::DataWidthUnit, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ERROR_NOT_SUPPORTED, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, IS_CRYP_BUFFERSIZE, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Phase, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRYP_Encrypt | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t * | Input,
 |  | uint16_t | Size,
 |  | uint32_t * | Output,
 |  | uint32_t | Timeout
 | ) |  |

Encryption mode.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Input | Pointer to the input buffer (plaintext)
Size | Length of the plaintext buffer in word.
Output | Pointer to the output buffer(ciphertext)
Timeout | Specify Timeout value
Return values:
HAL status

Definition at line 1193 of file stm32wbxx_hal_cryp.c.

References assert_param, CRYP_AES_CBC, CRYP_AES_CCM, CRYP_AES_CTR, CRYP_AES_ECB, CRYP_AES_Encrypt(), CRYP_AES_GCM_GMAC, CRYP_AESCCM_Process(), CRYP_AESGCM_Process(), CRYP_DATAWIDTHUNIT_WORD, CRYP_OPERATINGMODE_ENCRYPT, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, CRYP_ConfigTypeDef::DataWidthUnit, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ERROR_NOT_SUPPORTED, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, IS_CRYP_BUFFERSIZE, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t * | Input,
 |  | uint16_t | Size,
 |  | uint32_t * | Output
 | ) |  |

Encryption in DMA mode.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Input | Pointer to the input buffer (plaintext)
Size | Length of the plaintext buffer in word.
Output | Pointer to the output buffer(ciphertext)
Return values:
HAL status

Definition at line 1611 of file stm32wbxx_hal_cryp.c.

References CRYP_ConfigTypeDef::Algorithm, assert_param, CRYP_AES_CBC, CRYP_AES_CCM, CRYP_AES_CTR, CRYP_AES_ECB, CRYP_AES_GCM_GMAC, CRYP_AESCCM_Process_DMA(), CRYP_AESGCM_Process_DMA(), CRYP_DATAWIDTHUNIT_WORD, CRYP_KEYIVCONFIG_ONCE, CRYP_OPERATINGMODE_ENCRYPT, CRYP_PHASE_PROCESS, CRYP_SetDMAConfig(), CRYP_SetKey(), __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, CRYP_ConfigTypeDef::DataWidthUnit, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ERROR_NOT_SUPPORTED, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, IS_CRYP_BUFFERSIZE, __CRYP_HandleTypeDef::KeyIVConfig, CRYP_ConfigTypeDef::KeyIVConfigSkip, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRYP_Encrypt_IT | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t * | Input,
 |  | uint16_t | Size,
 |  | uint32_t * | Output
 | ) |  |

Encryption in interrupt mode.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Input | Pointer to the input buffer (plaintext)
Size | Length of the plaintext buffer in word
Output | Pointer to the output buffer(ciphertext)
Return values:
HAL status

Definition at line 1392 of file stm32wbxx_hal_cryp.c.

References assert_param, CRYP_AES_CBC, CRYP_AES_CCM, CRYP_AES_CTR, CRYP_AES_ECB, CRYP_AES_Encrypt_IT(), CRYP_AES_GCM_GMAC, CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_IT(), CRYP_DATAWIDTHUNIT_WORD, CRYP_OPERATINGMODE_ENCRYPT, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, CRYP_ConfigTypeDef::DataWidthUnit, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ERROR_NOT_SUPPORTED, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, IS_CRYP_BUFFERSIZE, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Phase, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CRYP IRQ handler management

Functions
CRYP IRQ handler management
CRYP Exported Functions

CRYP IRQ handler. More...

Functions

void | HAL_CRYP_IRQHandler (CRYP_HandleTypeDef *hcryp)
This function handles cryptographic interrupt request.
uint32_t | HAL_CRYP_GetError (CRYP_HandleTypeDef *hcryp)
Return the CRYP error code.
HAL_CRYP_STATETypeDef | HAL_CRYP_GetState (CRYP_HandleTypeDef *hcryp)
Returns the CRYP state.
__weak void | HAL_CRYP_InCpltCallback (CRYP_HandleTypeDef *hcryp)
Input FIFO transfer completed callback.
__weak void | HAL_CRYP_OutCpltCallback (CRYP_HandleTypeDef *hcryp)
Output FIFO transfer completed callback.
__weak void | HAL_CRYP_ErrorCallback (CRYP_HandleTypeDef *hcryp)
CRYP error callback.

Detailed Description

CRYP IRQ handler.

  ==============================================================================
                ##### CRYP IRQ handler management #####
  ==============================================================================
[..]  This section provides CRYP IRQ handler and callback functions.
      (+) HAL_CRYP_IRQHandler CRYP interrupt request
      (+) HAL_CRYP_InCpltCallback input data transfer complete callback
      (+) HAL_CRYP_OutCpltCallback output data transfer complete callback
      (+) HAL_CRYP_ErrorCallback  CRYP error callback
      (+) HAL_CRYP_GetState return the CRYP state
      (+) HAL_CRYP_GetError return the CRYP error code

Function Documentation

void HAL_CRYP_ErrorCallback ( CRYP_HandleTypeDef * hcryp )

CRYP error callback.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Return values:
None

Definition at line 1965 of file stm32wbxx_hal_cryp.c.

Referenced by CRYP_AES_IT(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process_DMA(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_DMAError(), CRYP_DMAOutCplt(), CRYP_SetDMAConfig(), HAL_CRYP_Init(), and HAL_CRYP_UnRegisterCallback().

uint32_t HAL_CRYP_GetError ( CRYP_HandleTypeDef * hcryp )

Return the CRYP error code.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for the CRYP peripheral
Return values:
CRYP error code

Definition at line 1911 of file stm32wbxx_hal_cryp.c.

References __CRYP_HandleTypeDef::ErrorCode.

HAL_CRYP_STATETypeDef HAL_CRYP_GetState ( CRYP_HandleTypeDef * hcryp )

Returns the CRYP state.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Return values:
HAL state

Definition at line 1922 of file stm32wbxx_hal_cryp.c.

References __CRYP_HandleTypeDef::State.

void HAL_CRYP_InCpltCallback ( CRYP_HandleTypeDef * hcryp )

Input FIFO transfer completed callback.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Return values:
None

Definition at line 1933 of file stm32wbxx_hal_cryp.c.

Referenced by CRYP_AES_IT(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_IT(), CRYP_DMAInCplt(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), HAL_CRYP_Init(), and HAL_CRYP_UnRegisterCallback().

void HAL_CRYP_IRQHandler ( CRYP_HandleTypeDef * hcryp )

This function handles cryptographic interrupt request.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
None

Definition at line 1847 of file stm32wbxx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_GET_FLAG, __HAL_CRYP_GET_IT_SOURCE, CRYP_ConfigTypeDef::Algorithm, CRYP_AES_CCM, CRYP_AES_GCM_GMAC, CRYP_AES_IT(), CRYP_CCF_CLEAR, CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), CRYP_IT_CCF, CRYP_IT_CCFIE, CRYP_IT_ERRIE, CRYP_IT_RDERR, CRYP_IT_WRERR, CRYP_PHASE_HEADER, __CRYP_HandleTypeDef::CrypHeaderCount, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_READ, HAL_CRYP_ERROR_WRITE, CRYP_ConfigTypeDef::HeaderSize, __CRYP_HandleTypeDef::Init, and __CRYP_HandleTypeDef::Instance.

void HAL_CRYP_OutCpltCallback ( CRYP_HandleTypeDef * hcryp )

Output FIFO transfer completed callback.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Return values:
None

Definition at line 1949 of file stm32wbxx_hal_cryp.c.

Referenced by CRYP_AES_IT(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetPayloadPhase_IT(), HAL_CRYP_Init(), and HAL_CRYP_UnRegisterCallback().

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CRYP Private macros to check input parameters

Defines
CRYP Private macros to check input parameters
CRYP Private Macros

Defines

#define | IS_CRYP_ALGORITHM(ALGORITHM)
#define | IS_CRYP_KEYSIZE(KEYSIZE)
#define | IS_CRYP_DATATYPE(DATATYPE)
#define | IS_CRYP_INIT(CONFIG)
#define | IS_CRYP_BUFFERSIZE(ALGO, DATAWIDTH, SIZE)

Define Documentation

#define IS_CRYP_ALGORITHM ( ALGORITHM )
Value:
(((ALGORITHM) == CRYP_AES_ECB)      || \
                                      ((ALGORITHM)  == CRYP_AES_CBC)     || \
                                      ((ALGORITHM)  == CRYP_AES_CTR)     || \
                                      ((ALGORITHM)  == CRYP_AES_GCM_GMAC)|| \
                                      ((ALGORITHM)  == CRYP_AES_CCM))

Definition at line 550 of file stm32wbxx_hal_cryp.h.

Referenced by HAL_CRYP_Init(), and HAL_CRYP_SetConfig().

#define IS_CRYP_BUFFERSIZE | ( | ALGO,
 |  | DATAWIDTH,
 |  | SIZE
 | ) |
Value:
(((((ALGO) == CRYP_AES_ECB) || ((ALGO) == CRYP_AES_CBC) || ((ALGO) == CRYP_AES_CTR)) && \
            ((((DATAWIDTH) == CRYP_DATAWIDTHUNIT_WORD) && (((SIZE) % 4U) == 0U))           || \
             (((DATAWIDTH) == CRYP_DATAWIDTHUNIT_BYTE) && (((SIZE) % 16U) == 0U))))        || \
        (((ALGO)== CRYP_AES_GCM_GMAC) || ((ALGO) == CRYP_AES_CCM)))

Definition at line 568 of file stm32wbxx_hal_cryp.h.

Referenced by HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), and HAL_CRYP_Encrypt_IT().

#define IS_CRYP_DATATYPE ( DATATYPE )
Value:
(((DATATYPE) == CRYP_DATATYPE_32B) || \
                                   ((DATATYPE) == CRYP_DATATYPE_16B) || \
                                   ((DATATYPE) == CRYP_DATATYPE_8B)  || \
                                   ((DATATYPE) == CRYP_DATATYPE_1B))

Definition at line 560 of file stm32wbxx_hal_cryp.h.

Referenced by HAL_CRYP_Init(), and HAL_CRYP_SetConfig().

#define IS_CRYP_INIT ( CONFIG )
Value:
(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \
                             ((CONFIG) == CRYP_KEYIVCONFIG_ONCE))

Definition at line 565 of file stm32wbxx_hal_cryp.h.

Referenced by HAL_CRYP_Init().

#define IS_CRYP_KEYSIZE ( KEYSIZE )
Value:
(((KEYSIZE) == CRYP_KEYSIZE_128B)   || \
                                 ((KEYSIZE) == CRYP_KEYSIZE_256B))

Definition at line 557 of file stm32wbxx_hal_cryp.h.

Referenced by HAL_CRYP_Init(), and HAL_CRYP_SetConfig().

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CRYP Private Macros

Modules | Defines
CRYP Private Macros
CRYP

Modules

CRYP Private macros to check input parameters

Defines

#define CRYP_SET_PHASE(__HANDLE__, __PHASE__)

Define Documentation

#define CRYP_SET_PHASE | ( | __HANDLE__,
 |  | __PHASE__
 | ) |
Value:
do{(__HANDLE__)->Instance->CR &= (uint32_t)(~AES_CR_GCMPH);\
                                                  (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
                                                 }while(0U)

Definition at line 348 of file stm32wbxx_hal_cryp.c.

Referenced by CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_GCMCCM_SetHeaderPhase(), and CRYP_GCMCCM_SetHeaderPhase_DMA().

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CRYP Private Constants

CRYP Private Constants
CRYP
Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CRYP Private Defines

Defines
CRYP Private Defines
CRYP

Defines

#define | CRYP_TIMEOUT_KEYPREPARATION 82U /* The latency of key preparation operation is 82 clock cycles.*/
#define | CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/
#define | CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/
#define | CRYP_PHASE_READY 0x00000001U
#define | CRYP_PHASE_PROCESS 0x00000002U
#define | CRYP_OPERATINGMODE_ENCRYPT 0x00000000U
#define | CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0
#define | CRYP_OPERATINGMODE_DECRYPT AES_CR_MODE_1
#define | CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT AES_CR_MODE
#define | CRYP_PHASE_INIT 0x00000000U
#define | CRYP_PHASE_HEADER AES_CR_GCMPH_0
#define | CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1
#define | CRYP_PHASE_FINAL AES_CR_GCMPH
#define | CRYP_CCM_CTR1_0 0x07FFFFFFU
#define | CRYP_CCM_CTR1_1 0xFFFFFF00U
#define | CRYP_CCM_CTR1_2 0x00000001U

Define Documentation

#define CRYP_CCM_CTR1_0 0x07FFFFFFU

Definition at line 335 of file stm32wbxx_hal_cryp.c.

#define CRYP_CCM_CTR1_1 0xFFFFFF00U

Definition at line 336 of file stm32wbxx_hal_cryp.c.

#define CRYP_CCM_CTR1_2 0x00000001U

Definition at line 337 of file stm32wbxx_hal_cryp.c.

#define CRYP_OPERATINGMODE_DECRYPT AES_CR_MODE_1

Decryption (Mode 3)

Definition at line 327 of file stm32wbxx_hal_cryp.c.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), and HAL_CRYP_Decrypt_IT().

#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U

Encryption mode(Mode 1)

Definition at line 325 of file stm32wbxx_hal_cryp.c.

Referenced by CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_DMAOutCplt(), CRYP_GCMCCM_SetHeaderPhase_IT(), CRYP_GCMCCM_SetPayloadPhase_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), and HAL_CRYP_Encrypt_IT().

#define CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0

Key derivation mode only used when performing ECB and CBC decryptions (Mode 2)

Definition at line 326 of file stm32wbxx_hal_cryp.c.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), and CRYP_AES_Decrypt_IT().

#define CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT AES_CR_MODE

Key derivation and decryption only used when performing ECB and CBC decryptions (Mode 4)

Definition at line 328 of file stm32wbxx_hal_cryp.c.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), and CRYP_AES_Decrypt_IT().

#define CRYP_PHASE_FINAL AES_CR_GCMPH

GCM/GMAC or CCM final phase

Definition at line 332 of file stm32wbxx_hal_cryp.c.

#define CRYP_PHASE_HEADER AES_CR_GCMPH_0

GCM/GMAC or CCM header phase

Definition at line 330 of file stm32wbxx_hal_cryp.c.

Referenced by CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_IT(), CRYP_GCMCCM_SetHeaderPhase(), CRYP_GCMCCM_SetHeaderPhase_DMA(), and HAL_CRYP_IRQHandler().

#define CRYP_PHASE_INIT 0x00000000U

GCM/GMAC (or CCM) init phase

Definition at line 329 of file stm32wbxx_hal_cryp.c.

Referenced by CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), and CRYP_AESGCM_Process_IT().

#define CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1

GCM(/CCM) payload phase

Definition at line 331 of file stm32wbxx_hal_cryp.c.

Referenced by CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), and CRYP_GCMCCM_SetHeaderPhase_IT().

#define CRYP_PHASE_PROCESS 0x00000002U

CRYP peripheral is in processing phase

Definition at line 319 of file stm32wbxx_hal_cryp.c.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), CRYP_GCMCCM_SetHeaderPhase_IT(), and HAL_CRYP_Encrypt_DMA().

#define CRYP_PHASE_READY 0x00000001U

CRYP peripheral is ready for initialization.

Definition at line 318 of file stm32wbxx_hal_cryp.c.

Referenced by HAL_CRYP_DeInit(), HAL_CRYP_Init(), and HAL_CRYP_SetConfig().

#define CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/

Definition at line 316 of file stm32wbxx_hal_cryp.c.

Referenced by CRYP_AESCCM_Process_DMA(), CRYP_AESGCM_Process_DMA(), CRYP_DMAOutCplt(), and CRYP_GCMCCM_SetHeaderPhase_DMA().

#define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/

Definition at line 315 of file stm32wbxx_hal_cryp.c.

Referenced by CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process_DMA(), and CRYP_AESGCM_Process_IT().

#define CRYP_TIMEOUT_KEYPREPARATION 82U /* The latency of key preparation operation is 82 clock cycles.*/

Definition at line 314 of file stm32wbxx_hal_cryp.c.

Referenced by CRYP_AES_Decrypt_DMA(), and CRYP_AES_Decrypt_IT().

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CRYP Private Variables

CRYP Private Variables
CRYP
Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CRYP Private Functions

Functions
CRYP Private Functions
CRYP

Functions

static void | CRYP_SetDMAConfig (CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
Set the DMA configuration and start the DMA transfer.
static void | CRYP_DMAInCplt (DMA_HandleTypeDef *hdma)
DMA CRYP input data process complete callback.
static void | CRYP_DMAOutCplt (DMA_HandleTypeDef *hdma)
DMA CRYP output data process complete callback.
static void | CRYP_DMAError (DMA_HandleTypeDef *hdma)
DMA CRYP communication error callback.
static void | CRYP_SetKey (CRYP_HandleTypeDef *hcryp, uint32_t KeySize)
Writes Key in Key registers.
static void | CRYP_AES_IT (CRYP_HandleTypeDef *hcryp)
Handle CRYP block input/output data handling under interruption.
static HAL_StatusTypeDef | CRYP_GCMCCM_SetHeaderPhase (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Sets the header phase in polling mode.
static void | CRYP_GCMCCM_SetPayloadPhase_IT (CRYP_HandleTypeDef *hcryp)
Sets the payload phase in interrupt mode.
static void | CRYP_GCMCCM_SetHeaderPhase_IT (CRYP_HandleTypeDef *hcryp)
Sets the header phase in interrupt mode.
static HAL_StatusTypeDef | CRYP_GCMCCM_SetHeaderPhase_DMA (CRYP_HandleTypeDef *hcryp)
Sets the header phase when using DMA in process.
static HAL_StatusTypeDef | CRYP_AESGCM_Process_DMA (CRYP_HandleTypeDef *hcryp)
Encryption/Decryption process in AES GCM mode and prepare the authentication TAG using DMA.
static HAL_StatusTypeDef | CRYP_AESGCM_Process_IT (CRYP_HandleTypeDef *hcryp)
Encryption/Decryption process in AES GCM mode and prepare the authentication TAG in interrupt mode.
static HAL_StatusTypeDef | CRYP_AESGCM_Process (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Encryption/Decryption process in AES GCM mode and prepare the authentication TAG.
static HAL_StatusTypeDef | CRYP_AESCCM_Process (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
AES CCM encryption/decryption processing in polling mode for TinyAES peripheral, no encrypt/decrypt performed, only authentication preparation.
static HAL_StatusTypeDef | CRYP_AESCCM_Process_IT (CRYP_HandleTypeDef *hcryp)
AES CCM encryption/decryption process in interrupt mode for TinyAES peripheral, no encrypt/decrypt performed, only authentication preparation.
static HAL_StatusTypeDef | CRYP_AESCCM_Process_DMA (CRYP_HandleTypeDef *hcryp)
AES CCM encryption/decryption process in DMA mode for TinyAES peripheral, no encrypt/decrypt performed, only authentication preparation.
static void | CRYP_AES_ProcessData (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Process Data: Write Input data in polling mode and used in AES functions.
static HAL_StatusTypeDef | CRYP_AES_Encrypt (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Encryption in ECB/CBC & CTR Algorithm with AES Standard.
static HAL_StatusTypeDef | CRYP_AES_Decrypt (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Decryption in ECB/CBC & CTR mode with AES Standard.
static HAL_StatusTypeDef | CRYP_AES_Decrypt_IT (CRYP_HandleTypeDef *hcryp)
Decryption in ECB/CBC & CTR mode with AES Standard using interrupt mode.
static HAL_StatusTypeDef | CRYP_AES_Encrypt_IT (CRYP_HandleTypeDef *hcryp)
Encryption in ECB/CBC & CTR mode with AES Standard using interrupt mode.
static HAL_StatusTypeDef | CRYP_AES_Decrypt_DMA (CRYP_HandleTypeDef *hcryp)
Decryption in ECB/CBC & CTR mode with AES Standard using DMA mode.
static HAL_StatusTypeDef | CRYP_WaitOnCCFlag (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Handle CRYP hardware block Timeout when waiting for CCF flag to be raised.

Function Documentation

static HAL_StatusTypeDef CRYP_AES_Decrypt | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | Timeout
 | ) |  | [static]

Decryption in ECB/CBC & CTR mode with AES Standard.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure
Timeout | Specify Timeout value
Return values:
HAL status

Definition at line 2140 of file stm32wbxx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_ConfigTypeDef::Algorithm, __CRYP_HandleTypeDef::AutoKeyDerivation, CRYP_AES_CTR, CRYP_AES_ECB, CRYP_AES_ProcessData(), CRYP_CCF_CLEAR, CRYP_KEYIVCONFIG_ONCE, CRYP_OPERATINGMODE_DECRYPT, CRYP_OPERATINGMODE_KEYDERIVATION, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT, CRYP_PHASE_PROCESS, CRYP_SetKey(), CRYP_WaitOnCCFlag(), __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::KeyIVConfig, CRYP_ConfigTypeDef::KeyIVConfigSkip, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Decrypt().

static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA ( CRYP_HandleTypeDef * hcryp ) [static]

Decryption in ECB/CBC & CTR mode with AES Standard using DMA mode.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 2385 of file stm32wbxx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_ConfigTypeDef::Algorithm, __CRYP_HandleTypeDef::AutoKeyDerivation, CRYP_AES_CTR, CRYP_AES_ECB, CRYP_CCF_CLEAR, CRYP_KEYIVCONFIG_ONCE, CRYP_OPERATINGMODE_DECRYPT, CRYP_OPERATINGMODE_KEYDERIVATION, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT, CRYP_PHASE_PROCESS, CRYP_SetDMAConfig(), CRYP_SetKey(), CRYP_TIMEOUT_KEYPREPARATION, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::KeyIVConfig, CRYP_ConfigTypeDef::KeyIVConfigSkip, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Decrypt_DMA().

static HAL_StatusTypeDef CRYP_AES_Decrypt_IT ( CRYP_HandleTypeDef * hcryp ) [static]

Decryption in ECB/CBC & CTR mode with AES Standard using interrupt mode.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 2256 of file stm32wbxx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, __HAL_CRYP_ENABLE_IT, CRYP_ConfigTypeDef::Algorithm, __CRYP_HandleTypeDef::AutoKeyDerivation, CRYP_AES_CTR, CRYP_AES_ECB, CRYP_CCF_CLEAR, CRYP_IT_CCFIE, CRYP_IT_ERRIE, CRYP_KEYIVCONFIG_ONCE, CRYP_OPERATINGMODE_DECRYPT, CRYP_OPERATINGMODE_KEYDERIVATION, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT, CRYP_PHASE_PROCESS, CRYP_SetKey(), CRYP_TIMEOUT_KEYPREPARATION, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::KeyIVConfig, CRYP_ConfigTypeDef::KeyIVConfigSkip, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Decrypt_IT().

static HAL_StatusTypeDef CRYP_AES_Encrypt | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | Timeout
 | ) |  | [static]

Encryption in ECB/CBC & CTR Algorithm with AES Standard.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure
Timeout | specify Timeout value
Return values:
HAL status

Definition at line 1993 of file stm32wbxx_hal_cryp.c.

References __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_ConfigTypeDef::Algorithm, CRYP_AES_ECB, CRYP_AES_ProcessData(), CRYP_KEYIVCONFIG_ONCE, CRYP_PHASE_PROCESS, CRYP_SetKey(), __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::KeyIVConfig, CRYP_ConfigTypeDef::KeyIVConfigSkip, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Encrypt().

static HAL_StatusTypeDef CRYP_AES_Encrypt_IT ( CRYP_HandleTypeDef * hcryp ) [static]

Encryption in ECB/CBC & CTR mode with AES Standard using interrupt mode.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 2063 of file stm32wbxx_hal_cryp.c.

References __HAL_CRYP_ENABLE, __HAL_CRYP_ENABLE_IT, CRYP_ConfigTypeDef::Algorithm, CRYP_AES_ECB, CRYP_IT_CCFIE, CRYP_IT_ERRIE, CRYP_KEYIVCONFIG_ONCE, CRYP_PHASE_PROCESS, CRYP_SetKey(), __CRYP_HandleTypeDef::CrypInCount, HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::KeyIVConfig, CRYP_ConfigTypeDef::KeyIVConfigSkip, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Encrypt_IT().

static void CRYP_AES_IT ( CRYP_HandleTypeDef * hcryp ) [static]

Handle CRYP block input/output data handling under interruption.

Note:
The function is called under interruption only, once interruptions have been enabled by HAL_CRYP_Encrypt_IT or HAL_CRYP_Decrypt_IT.
Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Return values:
HAL status

Definition at line 2806 of file stm32wbxx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE, __HAL_CRYP_DISABLE_IT, CRYP_CCF_CLEAR, CRYP_IT_CCFIE, CRYP_IT_ERRIE, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, __CRYP_HandleTypeDef::ErrorCallback, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ErrorCallback(), HAL_CRYP_InCpltCallback(), HAL_CRYP_OutCpltCallback(), HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::InCpltCallback, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::OutCpltCallback, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Phase, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_IRQHandler().

static void CRYP_AES_ProcessData | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | Timeout
 | ) |  | [static]

Process Data: Write Input data in polling mode and used in AES functions.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Timeout | Specify Timeout value
Return values:
None

Definition at line 2743 of file stm32wbxx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE, CRYP_CCF_CLEAR, CRYP_WaitOnCCFlag(), __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, __CRYP_HandleTypeDef::ErrorCallback, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_ErrorCallback(), HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, and __CRYP_HandleTypeDef::State.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Encrypt(), CRYP_AESCCM_Process(), and CRYP_AESGCM_Process().

static HAL_StatusTypeDef CRYP_AESCCM_Process | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | Timeout
 | ) |  | [static]

AES CCM encryption/decryption processing in polling mode for TinyAES peripheral, no encrypt/decrypt performed, only authentication preparation.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Timeout | Timeout duration
Return values:
HAL status

Definition at line 3696 of file stm32wbxx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_ConfigTypeDef::B0, CRYP_AES_ProcessData(), CRYP_CCF_CLEAR, CRYP_GCMCCM_SetHeaderPhase(), CRYP_KEYIVCONFIG_ONCE, CRYP_OPERATINGMODE_DECRYPT, CRYP_PHASE_INIT, CRYP_PHASE_PAYLOAD, CRYP_PHASE_PROCESS, CRYP_SET_PHASE, CRYP_SetKey(), CRYP_WaitOnCCFlag(), __CRYP_HandleTypeDef::CrypHeaderCount, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_READY, HAL_GetTick(), __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::KeyIVConfig, CRYP_ConfigTypeDef::KeyIVConfigSkip, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Phase, __CRYP_HandleTypeDef::Size, __CRYP_HandleTypeDef::SizesSum, and __CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Decrypt(), and HAL_CRYP_Encrypt().

static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA ( CRYP_HandleTypeDef * hcryp ) [static]

AES CCM encryption/decryption process in DMA mode for TinyAES peripheral, no encrypt/decrypt performed, only authentication preparation.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 4193 of file stm32wbxx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_ConfigTypeDef::B0, CRYP_CCF_CLEAR, CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_KEYIVCONFIG_ONCE, CRYP_OPERATINGMODE_DECRYPT, CRYP_PHASE_INIT, CRYP_PHASE_PAYLOAD, CRYP_PHASE_PROCESS, CRYP_SET_PHASE, CRYP_SetDMAConfig(), CRYP_SetKey(), CRYP_TIMEOUT_GCMCCMHEADERPHASE, CRYP_TIMEOUT_GCMCCMINITPHASE, __CRYP_HandleTypeDef::CrypHeaderCount, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, __CRYP_HandleTypeDef::ErrorCallback, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_ErrorCallback(), HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::KeyIVConfig, CRYP_ConfigTypeDef::KeyIVConfigSkip, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Phase, __CRYP_HandleTypeDef::Size, __CRYP_HandleTypeDef::SizesSum, and __CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Decrypt_DMA(), and HAL_CRYP_Encrypt_DMA().

static HAL_StatusTypeDef CRYP_AESCCM_Process_IT ( CRYP_HandleTypeDef * hcryp ) [static]

AES CCM encryption/decryption process in interrupt mode for TinyAES peripheral, no encrypt/decrypt performed, only authentication preparation.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 3893 of file stm32wbxx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE, __HAL_CRYP_DISABLE_IT, __HAL_CRYP_ENABLE, __HAL_CRYP_ENABLE_IT, CRYP_ConfigTypeDef::Algorithm, CRYP_ConfigTypeDef::B0, CRYP_AES_CCM, CRYP_AES_GCM_GMAC, CRYP_CCF_CLEAR, CRYP_IT_CCFIE, CRYP_IT_ERRIE, CRYP_KEYIVCONFIG_ONCE, CRYP_OPERATINGMODE_DECRYPT, CRYP_OPERATINGMODE_ENCRYPT, CRYP_PHASE_HEADER, CRYP_PHASE_INIT, CRYP_PHASE_PAYLOAD, CRYP_PHASE_PROCESS, CRYP_SET_PHASE, CRYP_SetKey(), CRYP_TIMEOUT_GCMCCMINITPHASE, __CRYP_HandleTypeDef::CrypHeaderCount, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_InCpltCallback(), HAL_CRYP_STATE_READY, CRYP_ConfigTypeDef::Header, CRYP_ConfigTypeDef::HeaderSize, __CRYP_HandleTypeDef::InCpltCallback, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::KeyIVConfig, CRYP_ConfigTypeDef::KeyIVConfigSkip, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::Phase, __CRYP_HandleTypeDef::Size, __CRYP_HandleTypeDef::SizesSum, and __CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Decrypt_IT(), and HAL_CRYP_Encrypt_IT().

static HAL_StatusTypeDef CRYP_AESGCM_Process | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | Timeout
 | ) |  | [static]

Encryption/Decryption process in AES GCM mode and prepare the authentication TAG.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Timeout | Timeout duration
Return values:
HAL status

Definition at line 2957 of file stm32wbxx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_AES_ProcessData(), CRYP_CCF_CLEAR, CRYP_GCMCCM_SetHeaderPhase(), CRYP_KEYIVCONFIG_ONCE, CRYP_OPERATINGMODE_ENCRYPT, CRYP_PHASE_INIT, CRYP_PHASE_PAYLOAD, CRYP_PHASE_PROCESS, CRYP_SET_PHASE, CRYP_SetKey(), CRYP_WaitOnCCFlag(), __CRYP_HandleTypeDef::CrypHeaderCount, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, __CRYP_HandleTypeDef::ErrorCallback, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_ErrorCallback(), HAL_CRYP_STATE_READY, HAL_GetTick(), __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::KeyIVConfig, CRYP_ConfigTypeDef::KeyIVConfigSkip, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, __CRYP_HandleTypeDef::Size, __CRYP_HandleTypeDef::SizesSum, and __CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Decrypt(), and HAL_CRYP_Encrypt().

static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA ( CRYP_HandleTypeDef * hcryp ) [static]

Encryption/Decryption process in AES GCM mode and prepare the authentication TAG using DMA.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 3483 of file stm32wbxx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_CCF_CLEAR, CRYP_GCMCCM_SetHeaderPhase_DMA(), CRYP_KEYIVCONFIG_ONCE, CRYP_OPERATINGMODE_ENCRYPT, CRYP_PHASE_INIT, CRYP_PHASE_PAYLOAD, CRYP_PHASE_PROCESS, CRYP_SET_PHASE, CRYP_SetDMAConfig(), CRYP_SetKey(), CRYP_TIMEOUT_GCMCCMHEADERPHASE, CRYP_TIMEOUT_GCMCCMINITPHASE, __CRYP_HandleTypeDef::CrypHeaderCount, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, __CRYP_HandleTypeDef::ErrorCallback, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_ErrorCallback(), HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::KeyIVConfig, CRYP_ConfigTypeDef::KeyIVConfigSkip, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, __CRYP_HandleTypeDef::Size, __CRYP_HandleTypeDef::SizesSum, and __CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Decrypt_DMA(), and HAL_CRYP_Encrypt_DMA().

static HAL_StatusTypeDef CRYP_AESGCM_Process_IT ( CRYP_HandleTypeDef * hcryp ) [static]

Encryption/Decryption process in AES GCM mode and prepare the authentication TAG in interrupt mode.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
HAL status

Definition at line 3158 of file stm32wbxx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE, __HAL_CRYP_DISABLE_IT, __HAL_CRYP_ENABLE, __HAL_CRYP_ENABLE_IT, CRYP_CCF_CLEAR, CRYP_IT_CCFIE, CRYP_IT_ERRIE, CRYP_KEYIVCONFIG_ONCE, CRYP_OPERATINGMODE_ENCRYPT, CRYP_PHASE_HEADER, CRYP_PHASE_INIT, CRYP_PHASE_PAYLOAD, CRYP_PHASE_PROCESS, CRYP_SET_PHASE, CRYP_SetKey(), CRYP_TIMEOUT_GCMCCMINITPHASE, __CRYP_HandleTypeDef::CrypHeaderCount, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_InCpltCallback(), HAL_CRYP_STATE_READY, CRYP_ConfigTypeDef::Header, CRYP_ConfigTypeDef::HeaderSize, __CRYP_HandleTypeDef::InCpltCallback, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::KeyIVConfig, CRYP_ConfigTypeDef::KeyIVConfigSkip, CRYP_ConfigTypeDef::KeySize, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::Phase, CRYP_ConfigTypeDef::pInitVect, __CRYP_HandleTypeDef::Size, __CRYP_HandleTypeDef::SizesSum, and __CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_Decrypt_IT(), and HAL_CRYP_Encrypt_IT().

static void CRYP_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA CRYP communication error callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 2650 of file stm32wbxx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, CRYP_CCF_CLEAR, __CRYP_HandleTypeDef::ErrorCallback, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_DMA, HAL_CRYP_ErrorCallback(), HAL_CRYP_STATE_READY, and __CRYP_HandleTypeDef::State.

Referenced by CRYP_SetDMAConfig().

static void CRYP_DMAInCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA CRYP input data process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 2502 of file stm32wbxx_hal_cryp.c.

References HAL_CRYP_InCpltCallback(), __CRYP_HandleTypeDef::InCpltCallback, and __CRYP_HandleTypeDef::Instance.

Referenced by CRYP_SetDMAConfig().

static void CRYP_DMAOutCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA CRYP output data process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 2524 of file stm32wbxx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE, CRYP_ConfigTypeDef::Algorithm, CRYP_AES_CCM, CRYP_AES_GCM_GMAC, CRYP_CCF_CLEAR, CRYP_OPERATINGMODE_DECRYPT, CRYP_OPERATINGMODE_ENCRYPT, CRYP_TIMEOUT_GCMCCMHEADERPHASE, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, __CRYP_HandleTypeDef::ErrorCallback, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_ErrorCallback(), HAL_CRYP_OutCpltCallback(), HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::OutCpltCallback, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

Referenced by CRYP_SetDMAConfig().

static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | Timeout
 | ) |  | [static]

Sets the header phase in polling mode.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module(Header & HeaderSize)
Timeout | Timeout value
Return values:
state

Definition at line 4550 of file stm32wbxx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_ConfigTypeDef::Algorithm, CRYP_AES_GCM_GMAC, CRYP_CCF_CLEAR, CRYP_PHASE_HEADER, CRYP_SET_PHASE, CRYP_WaitOnCCFlag(), __CRYP_HandleTypeDef::CrypHeaderCount, CRYP_ConfigTypeDef::DataType, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_READY, CRYP_ConfigTypeDef::Header, CRYP_ConfigTypeDef::HeaderSize, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, and __CRYP_HandleTypeDef::State.

Referenced by CRYP_AESCCM_Process(), and CRYP_AESGCM_Process().

static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA ( CRYP_HandleTypeDef * hcryp ) [static]

Sets the header phase when using DMA in process.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module(Header & HeaderSize)
Return values:
None

Definition at line 4681 of file stm32wbxx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE, __HAL_CRYP_ENABLE, CRYP_CCF_CLEAR, CRYP_PHASE_HEADER, CRYP_SET_PHASE, CRYP_TIMEOUT_GCMCCMHEADERPHASE, __CRYP_HandleTypeDef::CrypHeaderCount, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_READY, CRYP_ConfigTypeDef::Header, CRYP_ConfigTypeDef::HeaderSize, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, and __CRYP_HandleTypeDef::State.

Referenced by CRYP_AESCCM_Process_DMA(), and CRYP_AESGCM_Process_DMA().

static void CRYP_GCMCCM_SetHeaderPhase_IT ( CRYP_HandleTypeDef * hcryp ) [static]

Sets the header phase in interrupt mode.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module(Header & HeaderSize)
Return values:
None

Definition at line 4830 of file stm32wbxx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE_IT, CRYP_ConfigTypeDef::Algorithm, CRYP_AES_CCM, CRYP_AES_GCM_GMAC, CRYP_CCF_CLEAR, CRYP_IT_CCFIE, CRYP_IT_ERRIE, CRYP_OPERATINGMODE_DECRYPT, CRYP_OPERATINGMODE_ENCRYPT, CRYP_PHASE_PAYLOAD, CRYP_PHASE_PROCESS, __CRYP_HandleTypeDef::CrypHeaderCount, __CRYP_HandleTypeDef::CrypInCount, HAL_CRYP_InCpltCallback(), HAL_CRYP_STATE_READY, CRYP_ConfigTypeDef::Header, CRYP_ConfigTypeDef::HeaderSize, __CRYP_HandleTypeDef::InCpltCallback, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::Phase, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_IRQHandler().

static void CRYP_GCMCCM_SetPayloadPhase_IT ( CRYP_HandleTypeDef * hcryp ) [static]

Sets the payload phase in interrupt mode.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
Return values:
state

Definition at line 4402 of file stm32wbxx_hal_cryp.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE_IT, CRYP_ConfigTypeDef::Algorithm, CRYP_AES_CCM, CRYP_AES_GCM_GMAC, CRYP_CCF_CLEAR, CRYP_IT_CCFIE, CRYP_IT_ERRIE, CRYP_OPERATINGMODE_DECRYPT, CRYP_OPERATINGMODE_ENCRYPT, __CRYP_HandleTypeDef::CrypInCount, __CRYP_HandleTypeDef::CrypOutCount, HAL_CRYP_InCpltCallback(), HAL_CRYP_OutCpltCallback(), HAL_CRYP_STATE_READY, __CRYP_HandleTypeDef::InCpltCallback, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::KeyIVConfig, __CRYP_HandleTypeDef::OutCpltCallback, __CRYP_HandleTypeDef::pCrypInBuffPtr, __CRYP_HandleTypeDef::pCrypOutBuffPtr, __CRYP_HandleTypeDef::Phase, __CRYP_HandleTypeDef::Size, and __CRYP_HandleTypeDef::State.

Referenced by HAL_CRYP_IRQHandler().

static void CRYP_SetDMAConfig | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | inputaddr,
 |  | uint16_t | Size,
 |  | uint32_t | outputaddr
 | ) |  | [static]

Set the DMA configuration and start the DMA transfer.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
inputaddr | address of the input buffer
Size | size of the input buffer, must be a multiple of 16.
outputaddr | address of the output buffer
Return values:
None

Definition at line 2682 of file stm32wbxx_hal_cryp.c.

References __HAL_CRYP_ENABLE, CRYP_ConfigTypeDef::Algorithm, CRYP_AES_GCM_GMAC, CRYP_DMAError(), CRYP_DMAInCplt(), CRYP_DMAOutCplt(), __CRYP_HandleTypeDef::ErrorCallback, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_DMA, HAL_CRYP_ErrorCallback(), HAL_DMA_Start_IT(), __CRYP_HandleTypeDef::hdmain, __CRYP_HandleTypeDef::hdmaout, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

Referenced by CRYP_AES_Decrypt_DMA(), CRYP_AESCCM_Process_DMA(), CRYP_AESGCM_Process_DMA(), and HAL_CRYP_Encrypt_DMA().

static void CRYP_SetKey | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | KeySize
 | ) |  | [static]

Writes Key in Key registers.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
KeySize | Size of Key
Note:
If pKey is NULL, the Key registers are not written. This configuration occurs when the key is written out of HAL scope.
Return values:
None

Definition at line 2921 of file stm32wbxx_hal_cryp.c.

References CRYP_KEYSIZE_128B, CRYP_KEYSIZE_256B, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, and CRYP_ConfigTypeDef::pKey.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_Decrypt_DMA(), CRYP_AES_Decrypt_IT(), CRYP_AES_Encrypt(), CRYP_AES_Encrypt_IT(), CRYP_AESCCM_Process(), CRYP_AESCCM_Process_DMA(), CRYP_AESCCM_Process_IT(), CRYP_AESGCM_Process(), CRYP_AESGCM_Process_DMA(), CRYP_AESGCM_Process_IT(), and HAL_CRYP_Encrypt_DMA().

static HAL_StatusTypeDef CRYP_WaitOnCCFlag | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle CRYP hardware block Timeout when waiting for CCF flag to be raised.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 4984 of file stm32wbxx_hal_cryp.c.

References HAL_GetTick(), and __CRYP_HandleTypeDef::Instance.

Referenced by CRYP_AES_Decrypt(), CRYP_AES_ProcessData(), CRYP_AESCCM_Process(), CRYP_AESGCM_Process(), and CRYP_GCMCCM_SetHeaderPhase().

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CRYPEx Private Types

CRYPEx Private Types
CRYPEx
Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CRYPEx Private Variables

CRYPEx Private Variables
CRYPEx
Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CRYPEx Private Constants

CRYPEx Private Constants
CRYPEx
Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CRYPEx Private Macros

CRYPEx Private Macros
CRYPEx
Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CRYPEx Private Functions

CRYPEx Private Functions
CRYPEx
Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Extended AES processing functions

Functions
Extended AES processing functions
CRYPEx Exported Functions

Extended processing functions. More...

Functions

HAL_StatusTypeDef | HAL_CRYPEx_AESGCM_GenerateAuthTAG (CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
generate the GCM authentication TAG.
HAL_StatusTypeDef | HAL_CRYPEx_AESCCM_GenerateAuthTAG (CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
AES CCM Authentication TAG generation.

Detailed Description

Extended processing functions.

  ==============================================================================
              ##### Extended AES processing functions #####
  ==============================================================================
    [..]  This section provides functions allowing to generate the authentication
          TAG in Polling mode
      (#)HAL_CRYPEx_AESGCM_GenerateAuthTAG
      (#)HAL_CRYPEx_AESCCM_GenerateAuthTAG
         they should be used after Encrypt/Decrypt operation.

Function Documentation

HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t * | AuthTag,
 |  | uint32_t | Timeout
 | ) |  |

AES CCM Authentication TAG generation.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
AuthTag | Pointer to the authentication buffer
Timeout | Timeout duration
Return values:
HAL status

Definition at line 213 of file stm32wbxx_hal_cryp_ex.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE, __HAL_CRYP_DISABLE_IT, CRYP_CCF_CLEAR, CRYP_IT_CCFIE, CRYP_IT_ERRIE, CRYP_OPERATINGMODE_ENCRYPT, CRYP_PHASE_FINAL, CRYPEx_PHASE_FINAL, CRYPEx_PHASE_PROCESS, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, HAL_GetTick(), __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::Phase, and __CRYP_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG | ( | CRYP_HandleTypeDef * | hcryp,
 |  | uint32_t * | AuthTag,
 |  | uint32_t | Timeout
 | ) |  |

generate the GCM authentication TAG.

Parameters:
hcryp | pointer to a CRYP_HandleTypeDef structure that contains the configuration information for CRYP module
AuthTag | Pointer to the authentication buffer
Timeout | Timeout duration
Return values:
HAL status

Definition at line 99 of file stm32wbxx_hal_cryp_ex.c.

References __HAL_CRYP_CLEAR_FLAG, __HAL_CRYP_DISABLE, CRYP_CCF_CLEAR, CRYP_OPERATINGMODE_ENCRYPT, CRYP_PHASE_FINAL, CRYPEx_PHASE_FINAL, CRYPEx_PHASE_PROCESS, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE, HAL_CRYP_ERROR_BUSY, HAL_CRYP_ERROR_TIMEOUT, HAL_CRYP_STATE_BUSY, HAL_CRYP_STATE_READY, HAL_GetTick(), CRYP_ConfigTypeDef::HeaderSize, __CRYP_HandleTypeDef::Init, __CRYP_HandleTypeDef::Instance, __CRYP_HandleTypeDef::Phase, __CRYP_HandleTypeDef::SizesSum, and __CRYP_HandleTypeDef::State.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Extended AES Key Derivations functions

Functions
Extended AES Key Derivations functions
CRYPEx Exported Functions

Extended Key Derivations functions. More...

Functions

void | HAL_CRYPEx_EnableAutoKeyDerivation (CRYP_HandleTypeDef *hcryp)
AES enable key derivation functions.
void | HAL_CRYPEx_DisableAutoKeyDerivation (CRYP_HandleTypeDef *hcryp)
AES disable key derivation functions.

Detailed Description

Extended Key Derivations functions.

  ==============================================================================
              ##### Key Derivation functions #####
  ==============================================================================
    [..]  This section provides functions allowing to Enable or Disable the
          the AutoKeyDerivation parameter in CRYP_HandleTypeDef structure
          These function are allowed only in TinyAES peripheral.

Function Documentation

void HAL_CRYPEx_DisableAutoKeyDerivation ( CRYP_HandleTypeDef * hcryp )

AES disable key derivation functions.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure.

Definition at line 350 of file stm32wbxx_hal_cryp_ex.c.

References __CRYP_HandleTypeDef::AutoKeyDerivation, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_STATE_READY, and __CRYP_HandleTypeDef::State.

void HAL_CRYPEx_EnableAutoKeyDerivation ( CRYP_HandleTypeDef * hcryp )

AES enable key derivation functions.

Parameters:
hcryp pointer to a CRYP_HandleTypeDef structure.

Definition at line 334 of file stm32wbxx_hal_cryp_ex.c.

References __CRYP_HandleTypeDef::AutoKeyDerivation, __CRYP_HandleTypeDef::ErrorCode, HAL_CRYP_ERROR_BUSY, HAL_CRYP_STATE_READY, and __CRYP_HandleTypeDef::State.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CRYPEx_Private_Defines

Defines
CRYPEx_Private_Defines
CRYPEx

Defines

#define | CRYP_PHASE_INIT 0x00000000U
#define | CRYP_PHASE_HEADER AES_CR_GCMPH_0
#define | CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1
#define | CRYP_PHASE_FINAL AES_CR_GCMPH
#define | CRYP_OPERATINGMODE_ENCRYPT 0x00000000U
#define | CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0
#define | CRYP_OPERATINGMODE_DECRYPT AES_CR_MODE_1
#define | CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT AES_CR_MODE
#define | CRYPEx_PHASE_PROCESS 0x02U
#define | CRYPEx_PHASE_FINAL 0x03U
#define | CRYP_CCM_CTR0_0 0x07FFFFFFU
#define | CRYP_CCM_CTR0_3 0xFFFFFF00U

Define Documentation

#define CRYP_CCM_CTR0_0 0x07FFFFFFU

Definition at line 58 of file stm32wbxx_hal_cryp_ex.c.

#define CRYP_CCM_CTR0_3 0xFFFFFF00U

Definition at line 59 of file stm32wbxx_hal_cryp_ex.c.

#define CRYP_OPERATINGMODE_DECRYPT AES_CR_MODE_1

Decryption

Definition at line 51 of file stm32wbxx_hal_cryp_ex.c.

#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U

Encryption mode

Definition at line 49 of file stm32wbxx_hal_cryp_ex.c.

Referenced by HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

#define CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0

Key derivation mode only used when performing ECB and CBC decryptions

Definition at line 50 of file stm32wbxx_hal_cryp_ex.c.

#define CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT AES_CR_MODE

Key derivation and decryption only used when performing ECB and CBC decryptions

Definition at line 52 of file stm32wbxx_hal_cryp_ex.c.

#define CRYP_PHASE_FINAL AES_CR_GCMPH

GCM/GMAC or CCM final phase

Definition at line 47 of file stm32wbxx_hal_cryp_ex.c.

Referenced by HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

#define CRYP_PHASE_HEADER AES_CR_GCMPH_0

GCM/GMAC or CCM header phase

Definition at line 45 of file stm32wbxx_hal_cryp_ex.c.

#define CRYP_PHASE_INIT 0x00000000U

GCM/GMAC (or CCM) init phase

Definition at line 44 of file stm32wbxx_hal_cryp_ex.c.

#define CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1

GCM(/CCM) payload phase

Definition at line 46 of file stm32wbxx_hal_cryp_ex.c.

#define CRYPEx_PHASE_FINAL 0x03U

CRYP peripheral is in final phase this is relevant only with CCM and GCM modes

Definition at line 55 of file stm32wbxx_hal_cryp_ex.c.

Referenced by HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

#define CRYPEx_PHASE_PROCESS 0x02U

CRYP peripheral is in processing phase

Definition at line 54 of file stm32wbxx_hal_cryp_ex.c.

Referenced by HAL_CRYPEx_AESCCM_GenerateAuthTAG(), and HAL_CRYPEx_AESGCM_GenerateAuthTAG().

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DMA Private Functions

Functions
DMA Private Functions
DMA

Functions

static void | DMA_SetConfig (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Sets the DMA Transfer parameter.
static void | DMA_CalcDMAMUXChannelBaseAndMask (DMA_HandleTypeDef *hdma)
Updates the DMA handle with the DMAMUX channel and status mask depending on channel number.
static void | DMA_CalcDMAMUXRequestGenBaseAndMask (DMA_HandleTypeDef *hdma)
Updates the DMA handle with the DMAMUX request generator params.

Function Documentation

static void DMA_CalcDMAMUXChannelBaseAndMask ( DMA_HandleTypeDef * hdma ) [static]

Updates the DMA handle with the DMAMUX channel and status mask depending on channel number.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
None

Definition at line 1056 of file stm32wbxx_hal_dma.c.

References __DMA_HandleTypeDef::ChannelIndex, __DMA_HandleTypeDef::DMAmuxChannel, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, and __DMA_HandleTypeDef::Instance.

Referenced by HAL_DMA_DeInit(), and HAL_DMA_Init().

static void DMA_CalcDMAMUXRequestGenBaseAndMask ( DMA_HandleTypeDef * hdma ) [static]

Updates the DMA handle with the DMAMUX request generator params.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
None

Definition at line 1088 of file stm32wbxx_hal_dma.c.

References __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::Init, and DMA_InitTypeDef::Request.

Referenced by HAL_DMA_DeInit(), and HAL_DMA_Init().

static void DMA_SetConfig | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | DataLength
 | ) |  | [static]

Sets the DMA Transfer parameter.

Parameters:
hdma | Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
SrcAddress | The source memory Buffer address
DstAddress | The destination memory Buffer address
DataLength | The length of data to be transferred from source to destination
Return values:
HAL status

Definition at line 1013 of file stm32wbxx_hal_dma.c.

References __DMA_HandleTypeDef::ChannelIndex, DMA_InitTypeDef::Direction, DMA_MEMORY_TO_PERIPH, __DMA_HandleTypeDef::DmaBaseAddress, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::Init, and __DMA_HandleTypeDef::Instance.

Referenced by HAL_DMA_Start(), and HAL_DMA_Start_IT().

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
DMA Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_DMA_Init (DMA_HandleTypeDef *hdma)
Initialize the DMA according to the specified parameters in the DMA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_DMA_DeInit (DMA_HandleTypeDef *hdma)
DeInitialize the DMA peripheral.

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
             ##### Initialization and de-initialization functions  #####
 ===============================================================================
    [..]
    This section provides functions allowing to initialize the DMA Channel source
    and destination addresses, incrementation and data sizes, transfer direction,
    circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
    [..]
    The HAL_DMA_Init() function follows the DMA configuration procedures as described in
    reference manual.

Function Documentation

HAL_StatusTypeDef HAL_DMA_DeInit ( DMA_HandleTypeDef * hdma )

DeInitialize the DMA peripheral.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
HAL status

Definition at line 268 of file stm32wbxx_hal_dma.c.

References __HAL_DMA_DISABLE, assert_param, __DMA_HandleTypeDef::ChannelIndex, DMA_CalcDMAMUXChannelBaseAndMask(), DMA_CalcDMAMUXRequestGenBaseAndMask(), DMA_REQUEST_GENERATOR3, __DMA_HandleTypeDef::DmaBaseAddress, __DMA_HandleTypeDef::DMAmuxChannel, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_DMA_STATE_RESET, __DMA_HandleTypeDef::Init, __DMA_HandleTypeDef::Instance, DMA_InitTypeDef::Request, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_DMA_Init ( DMA_HandleTypeDef * hdma )

Initialize the DMA according to the specified parameters in the DMA_InitTypeDef and initialize the associated handle.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
HAL status

Definition at line 151 of file stm32wbxx_hal_dma.c.

References assert_param, __DMA_HandleTypeDef::ChannelIndex, DMA_InitTypeDef::Direction, DMA_CalcDMAMUXChannelBaseAndMask(), DMA_CalcDMAMUXRequestGenBaseAndMask(), DMA_MEMORY_TO_MEMORY, DMA_REQUEST_GENERATOR3, DMA_REQUEST_MEM2MEM, __DMA_HandleTypeDef::DmaBaseAddress, __DMA_HandleTypeDef::DMAmuxChannel, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::Init, __DMA_HandleTypeDef::Instance, IS_DMA_ALL_REQUEST, IS_DMA_DIRECTION, IS_DMA_MEMORY_DATA_SIZE, IS_DMA_MEMORY_INC_STATE, IS_DMA_MODE, IS_DMA_PERIPHERAL_DATA_SIZE, IS_DMA_PERIPHERAL_INC_STATE, IS_DMA_PRIORITY, __DMA_HandleTypeDef::Lock, DMA_InitTypeDef::MemDataAlignment, DMA_InitTypeDef::MemInc, DMA_InitTypeDef::Mode, DMA_InitTypeDef::PeriphDataAlignment, DMA_InitTypeDef::PeriphInc, DMA_InitTypeDef::Priority, DMA_InitTypeDef::Request, and __DMA_HandleTypeDef::State.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
DMA Exported Functions

Input and Output operation functions. More...

Functions

HAL_StatusTypeDef | HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Start_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA_Abort (DMA_HandleTypeDef *hdma)
Abort the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Abort_IT (DMA_HandleTypeDef *hdma)
Aborts the DMA Transfer in Interrupt mode.
HAL_StatusTypeDef | HAL_DMA_PollForTransfer (DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
Polling for transfer complete.
void | HAL_DMA_IRQHandler (DMA_HandleTypeDef *hdma)
Handle DMA interrupt request.
HAL_StatusTypeDef | HAL_DMA_RegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void(*pCallback)(DMA_HandleTypeDef *_hdma))
Register callbacks.
HAL_StatusTypeDef | HAL_DMA_UnRegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
UnRegister callbacks.

Detailed Description

Input and Output operation functions.

 ===============================================================================
                      #####  IO operation functions  #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure the source, destination address and data length and Start DMA transfer
      (+) Configure the source, destination address and data length and
          Start DMA transfer with interrupt
      (+) Abort DMA transfer
      (+) Poll for transfer complete
      (+) Handle DMA interrupt request

Function Documentation

HAL_StatusTypeDef HAL_DMA_Abort ( DMA_HandleTypeDef * hdma )

Abort the DMA Transfer.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
HAL status

Definition at line 501 of file stm32wbxx_hal_dma.c.

References __HAL_DMA_DISABLE, __HAL_DMA_DISABLE_IT, __DMA_HandleTypeDef::ChannelIndex, DMA_IT_HT, DMA_IT_TC, DMA_IT_TE, __DMA_HandleTypeDef::DmaBaseAddress, __DMA_HandleTypeDef::DMAmuxChannel, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NO_XFER, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, and __DMA_HandleTypeDef::State.

Referenced by HAL_ADC_Stop_DMA(), HAL_ADCEx_RegularStop_DMA(), HAL_IRDA_Abort(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortTransmit(), HAL_IRDA_DMAStop(), HAL_QSPI_Abort(), HAL_SAI_Abort(), HAL_SAI_DMAStop(), HAL_SMARTCARD_Abort(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortTransmit(), HAL_SPI_Abort(), HAL_SPI_DMAStop(), HAL_UART_Abort(), HAL_UART_AbortReceive(), HAL_UART_AbortTransmit(), HAL_UART_DMAStop(), HAL_USART_Abort(), HAL_USART_DMAStop(), HAL_USART_Receive_DMA(), and HAL_USART_TransmitReceive_DMA().

HAL_StatusTypeDef HAL_DMA_Abort_IT ( DMA_HandleTypeDef * hdma )

Aborts the DMA Transfer in Interrupt mode.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
HAL status

Definition at line 563 of file stm32wbxx_hal_dma.c.

References __HAL_DMA_DISABLE, __HAL_DMA_DISABLE_IT, __DMA_HandleTypeDef::ChannelIndex, DMA_IT_HT, DMA_IT_TC, DMA_IT_TE, __DMA_HandleTypeDef::DmaBaseAddress, __DMA_HandleTypeDef::DMAmuxChannel, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NO_XFER, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::State, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_IRQHandler(), HAL_QSPI_Abort_IT(), HAL_QSPI_IRQHandler(), HAL_SAI_IRQHandler(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_IRQHandler(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive_IT(), HAL_UART_AbortTransmit_IT(), HAL_UART_IRQHandler(), HAL_USART_Abort_IT(), HAL_USART_IRQHandler(), and I2C_ITError().

void HAL_DMA_IRQHandler ( DMA_HandleTypeDef * hdma )

Handle DMA interrupt request.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
None

Definition at line 752 of file stm32wbxx_hal_dma.c.

References __HAL_DMA_DISABLE_IT, __DMA_HandleTypeDef::ChannelIndex, DMA_FLAG_HT1, DMA_FLAG_TC1, DMA_FLAG_TE1, DMA_IT_HT, DMA_IT_TC, DMA_IT_TE, __DMA_HandleTypeDef::DmaBaseAddress, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_TE, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::Instance, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_DMA_PollForTransfer | ( | DMA_HandleTypeDef * | hdma,
 |  | HAL_DMA_LevelCompleteTypeDef | CompleteLevel,
 |  | uint32_t | Timeout
 | ) |  |

Polling for transfer complete.

Parameters:
hdma | Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
CompleteLevel | Specifies the DMA level complete.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 624 of file stm32wbxx_hal_dma.c.

References __DMA_HandleTypeDef::ChannelIndex, DMA_FLAG_HT1, DMA_FLAG_TC1, DMA_FLAG_TE1, __DMA_HandleTypeDef::DmaBaseAddress, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NO_XFER, HAL_DMA_ERROR_NOT_SUPPORTED, HAL_DMA_ERROR_REQGEN, HAL_DMA_ERROR_SYNC, HAL_DMA_ERROR_TE, HAL_DMA_ERROR_TIMEOUT, HAL_DMA_FULL_TRANSFER, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, HAL_GetTick(), __DMA_HandleTypeDef::Instance, and __DMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA_RegisterCallback | ( | DMA_HandleTypeDef * | hdma,
 |  | HAL_DMA_CallbackIDTypeDef | CallbackID,
 |  | void(*)(DMA_HandleTypeDef *_hdma) | pCallback
 | ) |  |

Register callbacks.

Parameters:
hdma | Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
CallbackID | User Callback identifer a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
pCallback | Pointer to private callbacsk function which has pointer to a DMA_HandleTypeDef structure as parameter.
Return values:
HAL status

Definition at line 846 of file stm32wbxx_hal_dma.c.

References HAL_DMA_STATE_READY, HAL_DMA_XFER_ABORT_CB_ID, HAL_DMA_XFER_CPLT_CB_ID, HAL_DMA_XFER_ERROR_CB_ID, HAL_DMA_XFER_HALFCPLT_CB_ID, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_DMA_Start | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | DataLength
 | ) |  |

Start the DMA Transfer.

Parameters:
hdma | Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
SrcAddress | The source memory Buffer address
DstAddress | The destination memory Buffer address
DataLength | The length of data to be transferred from source to destination
Return values:
HAL status

Definition at line 389 of file stm32wbxx_hal_dma.c.

References __HAL_DMA_DISABLE, __HAL_DMA_ENABLE, assert_param, DMA_SetConfig(), __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, IS_DMA_BUFFER_SIZE, and __DMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA_Start_IT | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | DataLength
 | ) |  |

Start the DMA Transfer with interrupt enabled.

Parameters:
hdma | Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
SrcAddress | The source memory Buffer address
DstAddress | The destination memory Buffer address
DataLength | The length of data to be transferred from source to destination
Return values:
HAL status

Definition at line 432 of file stm32wbxx_hal_dma.c.

References __HAL_DMA_DISABLE, __HAL_DMA_DISABLE_IT, __HAL_DMA_ENABLE, __HAL_DMA_ENABLE_IT, assert_param, DMA_IT_HT, DMA_IT_TC, DMA_IT_TE, DMA_SetConfig(), __DMA_HandleTypeDef::DMAmuxChannel, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, IS_DMA_BUFFER_SIZE, __DMA_HandleTypeDef::State, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Referenced by CRYP_SetDMAConfig(), HAL_ADC_Start_DMA(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Transmit_DMA(), HAL_SAI_Receive_DMA(), HAL_SAI_Transmit_DMA(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive_DMA(), I2C_DMAMasterReceiveCplt(), and I2C_DMAMasterTransmitCplt().

HAL_StatusTypeDef HAL_DMA_UnRegisterCallback | ( | DMA_HandleTypeDef * | hdma,
 |  | HAL_DMA_CallbackIDTypeDef | CallbackID
 | ) |  |

UnRegister callbacks.

Parameters:
hdma | Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
CallbackID | User Callback identifer a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
Return values:
HAL status

Definition at line 897 of file stm32wbxx_hal_dma.c.

References HAL_DMA_STATE_READY, HAL_DMA_XFER_ABORT_CB_ID, HAL_DMA_XFER_ALL_CB_ID, HAL_DMA_XFER_CPLT_CB_ID, HAL_DMA_XFER_ERROR_CB_ID, HAL_DMA_XFER_HALFCPLT_CB_ID, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
DMA Exported Functions

Peripheral State and Errors functions. More...

Functions

HAL_DMA_StateTypeDef | HAL_DMA_GetState (DMA_HandleTypeDef *hdma)
Return the DMA handle state.
uint32_t | HAL_DMA_GetError (DMA_HandleTypeDef *hdma)
Return the DMA error code.

Detailed Description

Peripheral State and Errors functions.

 ===============================================================================
            ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Check the DMA state
      (+) Get error code

Function Documentation

uint32_t HAL_DMA_GetError ( DMA_HandleTypeDef * hdma )

Return the DMA error code.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
DMA Error Code

Definition at line 987 of file stm32wbxx_hal_dma.c.

References __DMA_HandleTypeDef::ErrorCode.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortTransmit(), HAL_IRDA_DMAStop(), HAL_SMARTCARD_Abort(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortTransmit(), HAL_UART_Abort(), HAL_UART_AbortReceive(), HAL_UART_AbortTransmit(), HAL_UART_DMAStop(), HAL_USART_Abort(), and HAL_USART_DMAStop().

HAL_DMA_StateTypeDef HAL_DMA_GetState ( DMA_HandleTypeDef * hdma )

Return the DMA handle state.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
HAL state

Definition at line 975 of file stm32wbxx_hal_dma.c.

References __DMA_HandleTypeDef::State.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DMA Exported Types

Data Structures | Typedefs | Enumerations
DMA Exported Types
DMA

Data Structures

struct | DMA_InitTypeDef
DMA Configuration Structure definition. More...
struct | __DMA_HandleTypeDef
DMA handle Structure definition. More...

Typedefs

typedef struct __DMA_HandleTypeDef | DMA_HandleTypeDef
DMA handle Structure definition.

Enumerations

enum | HAL_DMA_StateTypeDef { HAL_DMA_STATE_RESET = 0x00U, HAL_DMA_STATE_READY = 0x01U, HAL_DMA_STATE_BUSY = 0x02U, HAL_DMA_STATE_TIMEOUT = 0x03U }
HAL DMA State structures definition. More...
enum | HAL_DMA_LevelCompleteTypeDef { HAL_DMA_FULL_TRANSFER = 0x00U, HAL_DMA_HALF_TRANSFER = 0x01U }
HAL DMA Error Code structure definition. More...
enum HAL_DMA_CallbackIDTypeDef {
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, HAL_DMA_XFER_ERROR_CB_ID = 0x02U, HAL_DMA_XFER_ABORT_CB_ID = 0x03U,
HAL_DMA_XFER_ALL_CB_ID = 0x04U
}
HAL DMA Callback ID structure definition. More...

Typedef Documentation

typedef struct __DMA_HandleTypeDef DMA_HandleTypeDef

DMA handle Structure definition.

Enumeration Type Documentation

enum HAL_DMA_CallbackIDTypeDef

HAL DMA Callback ID structure definition.

Enumerator:
HAL_DMA_XFER_CPLT_CB_ID

Full transfer

HAL_DMA_XFER_HALFCPLT_CB_ID

Half transfer

HAL_DMA_XFER_ERROR_CB_ID

Error

HAL_DMA_XFER_ABORT_CB_ID

Abort

HAL_DMA_XFER_ALL_CB_ID

All

Definition at line 102 of file stm32wbxx_hal_dma.h.

enum HAL_DMA_LevelCompleteTypeDef

HAL DMA Error Code structure definition.

Enumerator:
HAL_DMA_FULL_TRANSFER

Full transfer

HAL_DMA_HALF_TRANSFER

Half Transfer

Definition at line 92 of file stm32wbxx_hal_dma.h.

enum HAL_DMA_StateTypeDef

HAL DMA State structures definition.

Enumerator:
HAL_DMA_STATE_RESET

DMA not yet initialized or disabled

HAL_DMA_STATE_READY

DMA initialized and ready for use

HAL_DMA_STATE_BUSY

DMA process is ongoing

HAL_DMA_STATE_TIMEOUT

DMA timeout state

Definition at line 81 of file stm32wbxx_hal_dma.h.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DMA_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DMA_InitTypeDef Struct Reference
DMA Exported Types

DMA Configuration Structure definition. More...

#include <stm32wbxx_hal_dma.h>

Data Fields

uint32_t | Request
uint32_t | Direction
uint32_t | PeriphInc
uint32_t | MemInc
uint32_t | PeriphDataAlignment
uint32_t | MemDataAlignment
uint32_t | Mode
uint32_t | Priority

Detailed Description

DMA Configuration Structure definition.

Definition at line 48 of file stm32wbxx_hal_dma.h.

Field Documentation

uint32_t DMA_InitTypeDef::Direction

Specifies if the data will be transferred from memory to peripheral, from memory to memory or from peripheral to memory. This parameter can be a value of DMA Data transfer direction

Definition at line 53 of file stm32wbxx_hal_dma.h.

Referenced by DMA_SetConfig(), HAL_DMA_Init(), HAL_QSPI_Receive_DMA(), and HAL_QSPI_Transmit_DMA().

uint32_t DMA_InitTypeDef::MemDataAlignment

Specifies the Memory data width. This parameter can be a value of DMA Memory data size

Definition at line 66 of file stm32wbxx_hal_dma.h.

Referenced by HAL_DMA_Init(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

uint32_t DMA_InitTypeDef::MemInc

Specifies whether the memory address register should be incremented or not. This parameter can be a value of DMA Memory incremented mode

Definition at line 60 of file stm32wbxx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::Mode

Specifies the operation mode of the DMAy Channelx. This parameter can be a value of DMA mode

Note:
The circular buffer mode cannot be used if the memory-to-memory data transfer is configured on the selected Channel

Definition at line 69 of file stm32wbxx_hal_dma.h.

Referenced by HAL_DMA_Init(), SAI_DMARxCplt(), and SAI_DMATxCplt().

uint32_t DMA_InitTypeDef::PeriphDataAlignment

Specifies the Peripheral data width. This parameter can be a value of DMA Peripheral data size

Definition at line 63 of file stm32wbxx_hal_dma.h.

Referenced by HAL_DMA_Init(), HAL_QSPI_Receive_DMA(), and HAL_QSPI_Transmit_DMA().

uint32_t DMA_InitTypeDef::PeriphInc

Specifies whether the Peripheral address register should be incremented or not. This parameter can be a value of DMA Peripheral incremented mode

Definition at line 57 of file stm32wbxx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::Priority

Specifies the software priority for the DMAy Channelx. This parameter can be a value of DMA Priority level

Definition at line 74 of file stm32wbxx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::Request

Specifies the request selected for the specified channel. This parameter can be a value of DMA request

Definition at line 50 of file stm32wbxx_hal_dma.h.

Referenced by DMA_CalcDMAMUXRequestGenBaseAndMask(), HAL_DMA_DeInit(), and HAL_DMA_Init().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_dma.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: __DMA_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__DMA_HandleTypeDef Struct Reference
DMA Exported Types

DMA handle Structure definition. More...

#include <stm32wbxx_hal_dma.h>

Data Fields

DMA_Channel_TypeDef * | Instance
DMA_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_DMA_StateTypeDef | State
void * | Parent
void(* | XferCpltCallback )(struct __DMA_HandleTypeDef *hdma)
void(* | XferHalfCpltCallback )(struct __DMA_HandleTypeDef *hdma)
void(* | XferErrorCallback )(struct __DMA_HandleTypeDef *hdma)
void(* | XferAbortCallback )(struct __DMA_HandleTypeDef *hdma)
__IO uint32_t | ErrorCode
DMA_TypeDef * | DmaBaseAddress
uint32_t | ChannelIndex
DMAMUX_Channel_TypeDef * | DMAmuxChannel
DMAMUX_ChannelStatus_TypeDef * | DMAmuxChannelStatus
uint32_t | DMAmuxChannelStatusMask
DMAMUX_RequestGen_TypeDef * | DMAmuxRequestGen
DMAMUX_RequestGenStatus_TypeDef * | DMAmuxRequestGenStatus
uint32_t | DMAmuxRequestGenStatusMask

Detailed Description

DMA handle Structure definition.

Definition at line 115 of file stm32wbxx_hal_dma.h.

Field Documentation

uint32_t __DMA_HandleTypeDef::ChannelIndex

DMA Channel Index

Definition at line 139 of file stm32wbxx_hal_dma.h.

Referenced by DMA_CalcDMAMUXChannelBaseAndMask(), DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

DMA_TypeDef* __DMA_HandleTypeDef::DmaBaseAddress

DMA Channel Base Address

Definition at line 137 of file stm32wbxx_hal_dma.h.

Referenced by DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

DMAMUX_Channel_TypeDef* __DMA_HandleTypeDef::DMAmuxChannel

Register base address

Definition at line 141 of file stm32wbxx_hal_dma.h.

Referenced by DMA_CalcDMAMUXChannelBaseAndMask(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_Start_IT(), HAL_DMAEx_ConfigMuxSync(), and HAL_DMAEx_MUX_IRQHandler().

DMAMUX_ChannelStatus_TypeDef* __DMA_HandleTypeDef::DMAmuxChannelStatus

DMAMUX Channels Status Base Address

Definition at line 143 of file stm32wbxx_hal_dma.h.

Referenced by DMA_CalcDMAMUXChannelBaseAndMask(), DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_PollForTransfer(), and HAL_DMAEx_MUX_IRQHandler().

uint32_t __DMA_HandleTypeDef::DMAmuxChannelStatusMask

DMAMUX Channel Status Mask

Definition at line 145 of file stm32wbxx_hal_dma.h.

Referenced by DMA_CalcDMAMUXChannelBaseAndMask(), DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_PollForTransfer(), and HAL_DMAEx_MUX_IRQHandler().

DMAMUX_RequestGen_TypeDef* __DMA_HandleTypeDef::DMAmuxRequestGen

DMAMUX request generator Base Address

Definition at line 147 of file stm32wbxx_hal_dma.h.

Referenced by DMA_CalcDMAMUXRequestGenBaseAndMask(), DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_PollForTransfer(), HAL_DMA_Start_IT(), HAL_DMAEx_ConfigMuxRequestGenerator(), HAL_DMAEx_DisableMuxRequestGenerator(), HAL_DMAEx_EnableMuxRequestGenerator(), and HAL_DMAEx_MUX_IRQHandler().

DMAMUX_RequestGenStatus_TypeDef* __DMA_HandleTypeDef::DMAmuxRequestGenStatus

DMAMUX request generator Address

Definition at line 149 of file stm32wbxx_hal_dma.h.

Referenced by DMA_CalcDMAMUXRequestGenBaseAndMask(), DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_PollForTransfer(), and HAL_DMAEx_MUX_IRQHandler().

uint32_t __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask

DMAMUX request generator Status mask

Definition at line 151 of file stm32wbxx_hal_dma.h.

Referenced by DMA_CalcDMAMUXRequestGenBaseAndMask(), DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_PollForTransfer(), and HAL_DMAEx_MUX_IRQHandler().

__IO uint32_t __DMA_HandleTypeDef::ErrorCode

DMA Error code

Definition at line 135 of file stm32wbxx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_GetError(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_PollForTransfer(), HAL_DMA_Start(), HAL_DMA_Start_IT(), HAL_DMAEx_MUX_IRQHandler(), and I2C_ITError().

DMA_InitTypeDef __DMA_HandleTypeDef::Init

DMA communication parameters

Definition at line 119 of file stm32wbxx_hal_dma.h.

Referenced by DMA_CalcDMAMUXRequestGenBaseAndMask(), DMA_SetConfig(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Transmit_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), SAI_DMARxCplt(), and SAI_DMATxCplt().

DMA_Channel_TypeDef* __DMA_HandleTypeDef::Instance

Register base address

Definition at line 117 of file stm32wbxx_hal_dma.h.

Referenced by DMA_CalcDMAMUXChannelBaseAndMask(), DMA_SetConfig(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_PollForTransfer(), HAL_DMAEx_ConfigMuxRequestGenerator(), HAL_DMAEx_ConfigMuxSync(), HAL_DMAEx_DisableMuxRequestGenerator(), HAL_DMAEx_EnableMuxRequestGenerator(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Transmit_DMA(), IRDA_DMAReceiveCplt(), IRDA_DMATransmitCplt(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), UART_DMAReceiveCplt(), UART_DMATransmitCplt(), USART_DMAReceiveCplt(), and USART_DMATransmitCplt().

HAL_LockTypeDef __DMA_HandleTypeDef::Lock

DMA locking object

Definition at line 121 of file stm32wbxx_hal_dma.h.

Referenced by HAL_DMA_Init().

void* __DMA_HandleTypeDef::Parent

Parent object state

Definition at line 125 of file stm32wbxx_hal_dma.h.

Referenced by IRDA_DMAAbortOnError(), IRDA_DMAError(), IRDA_DMAReceiveCplt(), IRDA_DMAReceiveHalfCplt(), IRDA_DMARxAbortCallback(), IRDA_DMATransmitCplt(), IRDA_DMATransmitHalfCplt(), IRDA_DMATxAbortCallback(), IRDA_DMATxOnlyAbortCallback(), QSPI_DMAAbortCplt(), QSPI_DMAError(), QSPI_DMARxCplt(), QSPI_DMARxHalfCplt(), QSPI_DMATxCplt(), QSPI_DMATxHalfCplt(), SMARTCARD_DMAAbortOnError(), SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), SMARTCARD_DMATransmitCplt(), SMARTCARD_DMATxAbortCallback(), SMARTCARD_DMATxOnlyAbortCallback(), UART_DMAAbortOnError(), UART_DMAError(), UART_DMAReceiveCplt(), UART_DMARxAbortCallback(), UART_DMARxHalfCplt(), UART_DMATransmitCplt(), UART_DMATxAbortCallback(), UART_DMATxHalfCplt(), UART_DMATxOnlyAbortCallback(), USART_DMAAbortOnError(), USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxAbortCallback(), USART_DMARxHalfCplt(), USART_DMATransmitCplt(), USART_DMATxAbortCallback(), and USART_DMATxHalfCplt().

__IO HAL_DMA_StateTypeDef __DMA_HandleTypeDef::State

DMA transfer state

Definition at line 123 of file stm32wbxx_hal_dma.h.

Referenced by HAL_ADC_Stop_DMA(), HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_GetState(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_PollForTransfer(), HAL_DMA_RegisterCallback(), HAL_DMA_Start(), HAL_DMA_Start_IT(), HAL_DMA_UnRegisterCallback(), HAL_DMAEx_ConfigMuxRequestGenerator(), HAL_DMAEx_ConfigMuxSync(), HAL_DMAEx_DisableMuxRequestGenerator(), and HAL_DMAEx_EnableMuxRequestGenerator().

void(* __DMA_HandleTypeDef::XferAbortCallback)(struct __DMA_HandleTypeDef *hdma)

DMA transfer abort callback

Definition at line 133 of file stm32wbxx_hal_dma.h.

Referenced by HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_RegisterCallback(), HAL_DMA_UnRegisterCallback(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_QSPI_Abort_IT(), HAL_QSPI_IRQHandler(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Transmit_DMA(), HAL_SAI_IRQHandler(), HAL_SAI_Receive_DMA(), HAL_SAI_Transmit_DMA(), HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_IRQHandler(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_IRQHandler(), I2C_DMAAbort(), I2C_ITError(), IRDA_DMARxAbortCallback(), IRDA_DMATxAbortCallback(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMATxAbortCallback(), SPI_DMARxAbortCallback(), SPI_DMATxAbortCallback(), UART_DMARxAbortCallback(), UART_DMATxAbortCallback(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

void(* __DMA_HandleTypeDef::XferCpltCallback)(struct __DMA_HandleTypeDef *hdma)

DMA transfer complete callback

Definition at line 127 of file stm32wbxx_hal_dma.h.

Referenced by CRYP_SetDMAConfig(), HAL_ADC_Start_DMA(), HAL_DMA_DeInit(), HAL_DMA_IRQHandler(), HAL_DMA_RegisterCallback(), HAL_DMA_UnRegisterCallback(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Transmit_DMA(), HAL_SAI_Receive_DMA(), HAL_SAI_Transmit_DMA(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

void(* __DMA_HandleTypeDef::XferErrorCallback)(struct __DMA_HandleTypeDef *hdma)

DMA transfer error callback

Definition at line 131 of file stm32wbxx_hal_dma.h.

Referenced by ADC_DMAConvCplt(), CRYP_SetDMAConfig(), HAL_ADC_Start_DMA(), HAL_DMA_DeInit(), HAL_DMA_IRQHandler(), HAL_DMA_RegisterCallback(), HAL_DMA_UnRegisterCallback(), HAL_DMAEx_MUX_IRQHandler(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Transmit_DMA(), HAL_SAI_Receive_DMA(), HAL_SAI_Transmit_DMA(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

void(* __DMA_HandleTypeDef::XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma)

DMA Half transfer complete callback

Definition at line 129 of file stm32wbxx_hal_dma.h.

Referenced by HAL_ADC_Start_DMA(), HAL_DMA_DeInit(), HAL_DMA_IRQHandler(), HAL_DMA_RegisterCallback(), HAL_DMA_Start_IT(), HAL_DMA_UnRegisterCallback(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Transmit_DMA(), HAL_SAI_Receive_DMA(), HAL_SAI_Transmit_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_dma.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DMA Error Code

Defines
DMA Error Code
DMA Exported Constants

Defines

#define | HAL_DMA_ERROR_NONE 0x00000000U
#define | HAL_DMA_ERROR_TE 0x00000001U
#define | HAL_DMA_ERROR_NO_XFER 0x00000004U
#define | HAL_DMA_ERROR_TIMEOUT 0x00000020U
#define | HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U
#define | HAL_DMA_ERROR_SYNC 0x00000200U
#define | HAL_DMA_ERROR_REQGEN 0x00000400U

Define Documentation

#define HAL_DMA_ERROR_NO_XFER 0x00000004U

Abort requested with no Xfer ongoing

Definition at line 168 of file stm32wbxx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), and HAL_DMA_PollForTransfer().

#define HAL_DMA_ERROR_NONE 0x00000000U

No error

Definition at line 166 of file stm32wbxx_hal_dma.h.

Referenced by HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_Start(), and HAL_DMA_Start_IT().

#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U

Not supported mode

Definition at line 170 of file stm32wbxx_hal_dma.h.

Referenced by HAL_DMA_PollForTransfer().

#define HAL_DMA_ERROR_REQGEN 0x00000400U

DMAMUX request generator overrun error

Definition at line 172 of file stm32wbxx_hal_dma.h.

Referenced by HAL_DMA_PollForTransfer(), and HAL_DMAEx_MUX_IRQHandler().

#define HAL_DMA_ERROR_SYNC 0x00000200U

DMAMUX sync overrun error

Definition at line 171 of file stm32wbxx_hal_dma.h.

Referenced by HAL_DMA_PollForTransfer(), and HAL_DMAEx_MUX_IRQHandler().

#define HAL_DMA_ERROR_TE 0x00000001U

Transfer error

Definition at line 167 of file stm32wbxx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define HAL_DMA_ERROR_TIMEOUT 0x00000020U

Timeout error

Definition at line 169 of file stm32wbxx_hal_dma.h.

Referenced by HAL_DMA_PollForTransfer(), HAL_IRDA_Abort(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortTransmit(), HAL_IRDA_DMAStop(), HAL_SMARTCARD_Abort(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortTransmit(), HAL_UART_Abort(), HAL_UART_AbortReceive(), HAL_UART_AbortTransmit(), HAL_UART_DMAStop(), HAL_USART_Abort(), and HAL_USART_DMAStop().

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DMA request

Defines
DMA request
DMA Exported Constants

Defines

#define | DMA_REQUEST_MEM2MEM LL_DMAMUX_REQ_MEM2MEM
#define | DMA_REQUEST_GENERATOR0 LL_DMAMUX_REQ_GENERATOR0
#define | DMA_REQUEST_GENERATOR1 LL_DMAMUX_REQ_GENERATOR1
#define | DMA_REQUEST_GENERATOR2 LL_DMAMUX_REQ_GENERATOR2
#define | DMA_REQUEST_GENERATOR3 LL_DMAMUX_REQ_GENERATOR3
#define | DMA_REQUEST_ADC1 LL_DMAMUX_REQ_ADC1
#define | DMA_REQUEST_SPI1_RX LL_DMAMUX_REQ_SPI1_RX
#define | DMA_REQUEST_SPI1_TX LL_DMAMUX_REQ_SPI1_TX
#define | DMA_REQUEST_SPI2_RX LL_DMAMUX_REQ_SPI2_RX
#define | DMA_REQUEST_SPI2_TX LL_DMAMUX_REQ_SPI2_TX
#define | DMA_REQUEST_I2C1_RX LL_DMAMUX_REQ_I2C1_RX
#define | DMA_REQUEST_I2C1_TX LL_DMAMUX_REQ_I2C1_TX
#define | DMA_REQUEST_I2C3_RX LL_DMAMUX_REQ_I2C3_RX
#define | DMA_REQUEST_I2C3_TX LL_DMAMUX_REQ_I2C3_TX
#define | DMA_REQUEST_USART1_RX LL_DMAMUX_REQ_USART1_RX
#define | DMA_REQUEST_USART1_TX LL_DMAMUX_REQ_USART1_TX
#define | DMA_REQUEST_LPUART1_RX LL_DMAMUX_REQ_LPUART1_RX
#define | DMA_REQUEST_LPUART1_TX LL_DMAMUX_REQ_LPUART1_TX
#define | DMA_REQUEST_SAI1_A LL_DMAMUX_REQ_SAI1_A
#define | DMA_REQUEST_SAI1_B LL_DMAMUX_REQ_SAI1_B
#define | DMA_REQUEST_QUADSPI LL_DMAMUX_REQ_QUADSPI
#define | DMA_REQUEST_TIM1_CH1 LL_DMAMUX_REQ_TIM1_CH1
#define | DMA_REQUEST_TIM1_CH2 LL_DMAMUX_REQ_TIM1_CH2
#define | DMA_REQUEST_TIM1_CH3 LL_DMAMUX_REQ_TIM1_CH3
#define | DMA_REQUEST_TIM1_CH4 LL_DMAMUX_REQ_TIM1_CH4
#define | DMA_REQUEST_TIM1_UP LL_DMAMUX_REQ_TIM1_UP
#define | DMA_REQUEST_TIM1_TRIG LL_DMAMUX_REQ_TIM1_TRIG
#define | DMA_REQUEST_TIM1_COM LL_DMAMUX_REQ_TIM1_COM
#define | DMA_REQUEST_TIM2_CH1 LL_DMAMUX_REQ_TIM2_CH1
#define | DMA_REQUEST_TIM2_CH2 LL_DMAMUX_REQ_TIM2_CH2
#define | DMA_REQUEST_TIM2_CH3 LL_DMAMUX_REQ_TIM2_CH3
#define | DMA_REQUEST_TIM2_CH4 LL_DMAMUX_REQ_TIM2_CH4
#define | DMA_REQUEST_TIM2_UP LL_DMAMUX_REQ_TIM2_UP
#define | DMA_REQUEST_TIM16_CH1 LL_DMAMUX_REQ_TIM16_CH1
#define | DMA_REQUEST_TIM16_UP LL_DMAMUX_REQ_TIM16_UP
#define | DMA_REQUEST_TIM17_CH1 LL_DMAMUX_REQ_TIM17_CH1
#define | DMA_REQUEST_TIM17_UP LL_DMAMUX_REQ_TIM17_UP
#define | DMA_REQUEST_AES1_IN LL_DMAMUX_REQ_AES1_IN
#define | DMA_REQUEST_AES1_OUT LL_DMAMUX_REQ_AES1_OUT
#define | DMA_REQUEST_AES2_IN LL_DMAMUX_REQ_AES2_IN
#define | DMA_REQUEST_AES2_OUT LL_DMAMUX_REQ_AES2_OUT

Define Documentation

#define DMA_REQUEST_ADC1 LL_DMAMUX_REQ_ADC1

DMAMUX ADC1 request

Definition at line 189 of file stm32wbxx_hal_dma.h.

#define DMA_REQUEST_AES1_IN LL_DMAMUX_REQ_AES1_IN

DMAMUX AES1 IN request

Definition at line 234 of file stm32wbxx_hal_dma.h.

#define DMA_REQUEST_AES1_OUT LL_DMAMUX_REQ_AES1_OUT

DMAMUX AES1 OUT request

Definition at line 235 of file stm32wbxx_hal_dma.h.

#define DMA_REQUEST_AES2_IN LL_DMAMUX_REQ_AES2_IN

DMAMUX AES2 IN request

Definition at line 237 of file stm32wbxx_hal_dma.h.

#define DMA_REQUEST_AES2_OUT LL_DMAMUX_REQ_AES2_OUT

DMAMUX AES2 OUT request

Definition at line 238 of file stm32wbxx_hal_dma.h.

#define DMA_REQUEST_GENERATOR0 LL_DMAMUX_REQ_GENERATOR0

DMAMUX request generator 0

Definition at line 184 of file stm32wbxx_hal_dma.h.

#define DMA_REQUEST_GENERATOR1 LL_DMAMUX_REQ_GENERATOR1

DMAMUX request generator 1

Definition at line 185 of file stm32wbxx_hal_dma.h.

#define DMA_REQUEST_GENERATOR2 LL_DMAMUX_REQ_GENERATOR2

DMAMUX request generator 2

Definition at line 186 of file stm32wbxx_hal_dma.h.

#define DMA_REQUEST_GENERATOR3 LL_DMAMUX_REQ_GENERATOR3

DMAMUX request generator 3

Definition at line 187 of file stm32wbxx_hal_dma.h.

Referenced by HAL_DMA_DeInit(), and HAL_DMA_Init().

#define DMA_REQUEST_I2C1_RX LL_DMAMUX_REQ_I2C1_RX

DMAMUX I2C1 RX request

Definition at line 196 of file stm32wbxx_hal_dma.h.

#define DMA_REQUEST_I2C1_TX LL_DMAMUX_REQ_I2C1_TX

DMAMUX I2C1 TX request

Definition at line 197 of file stm32wbxx_hal_dma.h.

#define DMA_REQUEST_I2C3_RX LL_DMAMUX_REQ_I2C3_RX

DMAMUX I2C3 RX request

Definition at line 198 of file stm32wbxx_hal_dma.h.

#define DMA_REQUEST_I2C3_TX LL_DMAMUX_REQ_I2C3_TX

DMAMUX I2C3 TX request

Definition at line 199 of file stm32wbxx_hal_dma.h.

#define DMA_REQUEST_LPUART1_RX LL_DMAMUX_REQ_LPUART1_RX

DMAMUX LP_UART1_RX request

Definition at line 204 of file stm32wbxx_hal_dma.h.

#define DMA_REQUEST_LPUART1_TX LL_DMAMUX_REQ_LPUART1_TX

DMAMUX LP_UART1_RX request

Definition at line 205 of file stm32wbxx_hal_dma.h.

#define DMA_REQUEST_MEM2MEM LL_DMAMUX_REQ_MEM2MEM

memory to memory transfer

Definition at line 182 of file stm32wbxx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define DMA_REQUEST_QUADSPI LL_DMAMUX_REQ_QUADSPI

DMAMUX QUADSPI request

Definition at line 212 of file stm32wbxx_hal_dma.h.

#define DMA_REQUEST_SAI1_A LL_DMAMUX_REQ_SAI1_A

DMAMUX SAI1 A request

Definition at line 208 of file stm32wbxx_hal_dma.h.

#define DMA_REQUEST_SAI1_B LL_DMAMUX_REQ_SAI1_B

DMAMUX SAI1 B request

Definition at line 209 of file stm32wbxx_hal_dma.h.

#define DMA_REQUEST_SPI1_RX LL_DMAMUX_REQ_SPI1_RX

DMAMUX SPI1 RX request

Definition at line 191 of file stm32wbxx_hal_dma.h.

#define DMA_REQUEST_SPI1_TX LL_DMAMUX_REQ_SPI1_TX

DMAMUX SPI1 TX request

Definition at line 192 of file stm32wbxx_hal_dma.h.

#define DMA_REQUEST_SPI2_RX LL_DMAMUX_REQ_SPI2_RX

DMAMUX SPI2 RX request

Definition at line 193 of file stm32wbxx_hal_dma.h.

#define DMA_REQUEST_SPI2_TX LL_DMAMUX_REQ_SPI2_TX

DMAMUX SPI2 TX request

Definition at line 194 of file stm32wbxx_hal_dma.h.

#define DMA_REQUEST_TIM16_CH1 LL_DMAMUX_REQ_TIM16_CH1

DMAMUX TIM16 CH1 request

Definition at line 228 of file stm32wbxx_hal_dma.h.

#define DMA_REQUEST_TIM16_UP LL_DMAMUX_REQ_TIM16_UP

DMAMUX TIM16 UP request

Definition at line 229 of file stm32wbxx_hal_dma.h.

#define DMA_REQUEST_TIM17_CH1 LL_DMAMUX_REQ_TIM17_CH1

DMAMUX TIM17 CH1 request

Definition at line 231 of file stm32wbxx_hal_dma.h.

#define DMA_REQUEST_TIM17_UP LL_DMAMUX_REQ_TIM17_UP

DMAMUX TIM17 UP request

Definition at line 232 of file stm32wbxx_hal_dma.h.

#define DMA_REQUEST_TIM1_CH1 LL_DMAMUX_REQ_TIM1_CH1

DMAMUX TIM1 CH1 request

Definition at line 214 of file stm32wbxx_hal_dma.h.

#define DMA_REQUEST_TIM1_CH2 LL_DMAMUX_REQ_TIM1_CH2

DMAMUX TIM1 CH2 request

Definition at line 215 of file stm32wbxx_hal_dma.h.

#define DMA_REQUEST_TIM1_CH3 LL_DMAMUX_REQ_TIM1_CH3

DMAMUX TIM1 CH3 request

Definition at line 216 of file stm32wbxx_hal_dma.h.

#define DMA_REQUEST_TIM1_CH4 LL_DMAMUX_REQ_TIM1_CH4

DMAMUX TIM1 CH4 request

Definition at line 217 of file stm32wbxx_hal_dma.h.

#define DMA_REQUEST_TIM1_COM LL_DMAMUX_REQ_TIM1_COM

DMAMUX TIM1 COM request

Definition at line 220 of file stm32wbxx_hal_dma.h.

#define DMA_REQUEST_TIM1_TRIG LL_DMAMUX_REQ_TIM1_TRIG

DMAMUX TIM1 TRIG request

Definition at line 219 of file stm32wbxx_hal_dma.h.

#define DMA_REQUEST_TIM1_UP LL_DMAMUX_REQ_TIM1_UP

DMAMUX TIM1 UP request

Definition at line 218 of file stm32wbxx_hal_dma.h.

#define DMA_REQUEST_TIM2_CH1 LL_DMAMUX_REQ_TIM2_CH1

DMAMUX TIM2 CH1 request

Definition at line 222 of file stm32wbxx_hal_dma.h.

#define DMA_REQUEST_TIM2_CH2 LL_DMAMUX_REQ_TIM2_CH2

DMAMUX TIM2 CH2 request

Definition at line 223 of file stm32wbxx_hal_dma.h.

#define DMA_REQUEST_TIM2_CH3 LL_DMAMUX_REQ_TIM2_CH3

DMAMUX TIM2 CH3 request

Definition at line 224 of file stm32wbxx_hal_dma.h.

#define DMA_REQUEST_TIM2_CH4 LL_DMAMUX_REQ_TIM2_CH4

DMAMUX TIM2 CH4 request

Definition at line 225 of file stm32wbxx_hal_dma.h.

#define DMA_REQUEST_TIM2_UP LL_DMAMUX_REQ_TIM2_UP

DMAMUX TIM2 UP request

Definition at line 226 of file stm32wbxx_hal_dma.h.

#define DMA_REQUEST_USART1_RX LL_DMAMUX_REQ_USART1_RX

DMAMUX USART1 RX request

Definition at line 201 of file stm32wbxx_hal_dma.h.

#define DMA_REQUEST_USART1_TX LL_DMAMUX_REQ_USART1_TX

DMAMUX USART1 TX request

Definition at line 202 of file stm32wbxx_hal_dma.h.

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STM32WB55xx HAL User Manual: DMA Data transfer direction

Defines
DMA Data transfer direction
DMA Exported Constants

Defines

#define | DMA_PERIPH_TO_MEMORY LL_DMA_DIRECTION_PERIPH_TO_MEMORY
#define | DMA_MEMORY_TO_PERIPH LL_DMA_DIRECTION_MEMORY_TO_PERIPH
#define | DMA_MEMORY_TO_MEMORY LL_DMA_DIRECTION_MEMORY_TO_MEMORY

Define Documentation

#define DMA_MEMORY_TO_MEMORY LL_DMA_DIRECTION_MEMORY_TO_MEMORY

Memory to memory direction

Definition at line 248 of file stm32wbxx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define DMA_MEMORY_TO_PERIPH LL_DMA_DIRECTION_MEMORY_TO_PERIPH

Memory to peripheral direction

Definition at line 247 of file stm32wbxx_hal_dma.h.

Referenced by DMA_SetConfig(), and HAL_QSPI_Transmit_DMA().

#define DMA_PERIPH_TO_MEMORY LL_DMA_DIRECTION_PERIPH_TO_MEMORY

Peripheral to memory direction

Definition at line 246 of file stm32wbxx_hal_dma.h.

Referenced by HAL_QSPI_Receive_DMA().

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STM32WB55xx HAL User Manual: DMA Peripheral incremented mode

Defines
DMA Peripheral incremented mode
DMA Exported Constants

Defines

#define | DMA_PINC_ENABLE LL_DMA_PERIPH_INCREMENT
#define | DMA_PINC_DISABLE LL_DMA_PERIPH_NOINCREMENT

Define Documentation

#define DMA_PINC_DISABLE LL_DMA_PERIPH_NOINCREMENT

Peripheral increment mode Disable

Definition at line 257 of file stm32wbxx_hal_dma.h.

#define DMA_PINC_ENABLE LL_DMA_PERIPH_INCREMENT

Peripheral increment mode Enable

Definition at line 256 of file stm32wbxx_hal_dma.h.

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STM32WB55xx HAL User Manual: DMA Memory incremented mode

Defines
DMA Memory incremented mode
DMA Exported Constants

Defines

#define | DMA_MINC_ENABLE LL_DMA_MEMORY_INCREMENT
#define | DMA_MINC_DISABLE LL_DMA_MEMORY_NOINCREMENT

Define Documentation

#define DMA_MINC_DISABLE LL_DMA_MEMORY_NOINCREMENT

Memory increment mode Disable

Definition at line 266 of file stm32wbxx_hal_dma.h.

#define DMA_MINC_ENABLE LL_DMA_MEMORY_INCREMENT

Memory increment mode Enable

Definition at line 265 of file stm32wbxx_hal_dma.h.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DMA Peripheral data size

Defines
DMA Peripheral data size
DMA Exported Constants

Defines

#define | DMA_PDATAALIGN_BYTE LL_DMA_PDATAALIGN_BYTE
#define | DMA_PDATAALIGN_HALFWORD LL_DMA_PDATAALIGN_HALFWORD
#define | DMA_PDATAALIGN_WORD LL_DMA_PDATAALIGN_WORD

Define Documentation

#define DMA_PDATAALIGN_BYTE LL_DMA_PDATAALIGN_BYTE

Peripheral data alignment : Byte

Definition at line 274 of file stm32wbxx_hal_dma.h.

Referenced by HAL_QSPI_Receive_DMA(), and HAL_QSPI_Transmit_DMA().

#define DMA_PDATAALIGN_HALFWORD LL_DMA_PDATAALIGN_HALFWORD

Peripheral data alignment : HalfWord

Definition at line 275 of file stm32wbxx_hal_dma.h.

Referenced by HAL_QSPI_Receive_DMA(), and HAL_QSPI_Transmit_DMA().

#define DMA_PDATAALIGN_WORD LL_DMA_PDATAALIGN_WORD

Peripheral data alignment : Word

Definition at line 276 of file stm32wbxx_hal_dma.h.

Referenced by HAL_QSPI_Receive_DMA(), and HAL_QSPI_Transmit_DMA().

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DMA Memory data size

Defines
DMA Memory data size
DMA Exported Constants

Defines

#define | DMA_MDATAALIGN_BYTE LL_DMA_MDATAALIGN_BYTE
#define | DMA_MDATAALIGN_HALFWORD LL_DMA_MDATAALIGN_HALFWORD
#define | DMA_MDATAALIGN_WORD LL_DMA_MDATAALIGN_WORD

Define Documentation

#define DMA_MDATAALIGN_BYTE LL_DMA_MDATAALIGN_BYTE

Memory data alignment : Byte

Definition at line 284 of file stm32wbxx_hal_dma.h.

#define DMA_MDATAALIGN_HALFWORD LL_DMA_MDATAALIGN_HALFWORD

Memory data alignment : HalfWord

Definition at line 285 of file stm32wbxx_hal_dma.h.

Referenced by HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

#define DMA_MDATAALIGN_WORD LL_DMA_MDATAALIGN_WORD

Memory data alignment : Word

Definition at line 286 of file stm32wbxx_hal_dma.h.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DMA mode

Defines
DMA mode
DMA Exported Constants

Defines

#define | DMA_NORMAL LL_DMA_MODE_NORMAL
#define | DMA_CIRCULAR LL_DMA_MODE_CIRCULAR

Define Documentation

#define DMA_CIRCULAR LL_DMA_MODE_CIRCULAR

Circular mode

Definition at line 295 of file stm32wbxx_hal_dma.h.

Referenced by SAI_DMARxCplt(), and SAI_DMATxCplt().

#define DMA_NORMAL LL_DMA_MODE_NORMAL

Normal mode

Definition at line 294 of file stm32wbxx_hal_dma.h.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DMA Priority level

Defines
DMA Priority level
DMA Exported Constants

Defines

#define | DMA_PRIORITY_LOW LL_DMA_PRIORITY_LOW
#define | DMA_PRIORITY_MEDIUM LL_DMA_PRIORITY_MEDIUM
#define | DMA_PRIORITY_HIGH LL_DMA_PRIORITY_HIGH
#define | DMA_PRIORITY_VERY_HIGH LL_DMA_PRIORITY_VERYHIGH

Define Documentation

#define DMA_PRIORITY_HIGH LL_DMA_PRIORITY_HIGH

Priority level : High

Definition at line 305 of file stm32wbxx_hal_dma.h.

#define DMA_PRIORITY_LOW LL_DMA_PRIORITY_LOW

Priority level : Low

Definition at line 303 of file stm32wbxx_hal_dma.h.

#define DMA_PRIORITY_MEDIUM LL_DMA_PRIORITY_MEDIUM

Priority level : Medium

Definition at line 304 of file stm32wbxx_hal_dma.h.

#define DMA_PRIORITY_VERY_HIGH LL_DMA_PRIORITY_VERYHIGH

Priority level : Very_High

Definition at line 306 of file stm32wbxx_hal_dma.h.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DMA interrupt enable definitions

Defines
DMA interrupt enable definitions
DMA Exported Constants

Defines

#define | DMA_IT_TC LL_DMA_CCR_TCIE
#define | DMA_IT_HT LL_DMA_CCR_HTIE
#define | DMA_IT_TE LL_DMA_CCR_TEIE

Define Documentation

#define DMA_IT_HT LL_DMA_CCR_HTIE

Half Transfer interrupt

Definition at line 316 of file stm32wbxx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_IRQHandler(), and HAL_DMA_Start_IT().

#define DMA_IT_TC LL_DMA_CCR_TCIE

Transfer complete interrupt

Definition at line 315 of file stm32wbxx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_IRQHandler(), and HAL_DMA_Start_IT().

#define DMA_IT_TE LL_DMA_CCR_TEIE

Transfer error interrupt

Definition at line 317 of file stm32wbxx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_IRQHandler(), and HAL_DMA_Start_IT().

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DMA flag definitions

Defines
DMA flag definitions
DMA Exported Constants

Defines

#define | DMA_FLAG_GL1 LL_DMA_ISR_GIF1
#define | DMA_FLAG_TC1 LL_DMA_ISR_TCIF1
#define | DMA_FLAG_HT1 LL_DMA_ISR_HTIF1
#define | DMA_FLAG_TE1 LL_DMA_ISR_TEIF1
#define | DMA_FLAG_GL2 LL_DMA_ISR_GIF2
#define | DMA_FLAG_TC2 LL_DMA_ISR_TCIF2
#define | DMA_FLAG_HT2 LL_DMA_ISR_HTIF2
#define | DMA_FLAG_TE2 LL_DMA_ISR_TEIF2
#define | DMA_FLAG_GL3 LL_DMA_ISR_GIF3
#define | DMA_FLAG_TC3 LL_DMA_ISR_TCIF3
#define | DMA_FLAG_HT3 LL_DMA_ISR_HTIF3
#define | DMA_FLAG_TE3 LL_DMA_ISR_TEIF3
#define | DMA_FLAG_GL4 LL_DMA_ISR_GIF4
#define | DMA_FLAG_TC4 LL_DMA_ISR_TCIF4
#define | DMA_FLAG_HT4 LL_DMA_ISR_HTIF4
#define | DMA_FLAG_TE4 LL_DMA_ISR_TEIF4
#define | DMA_FLAG_GL5 LL_DMA_ISR_GIF5
#define | DMA_FLAG_TC5 LL_DMA_ISR_TCIF5
#define | DMA_FLAG_HT5 LL_DMA_ISR_HTIF5
#define | DMA_FLAG_TE5 LL_DMA_ISR_TEIF5
#define | DMA_FLAG_GL6 LL_DMA_ISR_GIF6
#define | DMA_FLAG_TC6 LL_DMA_ISR_TCIF6
#define | DMA_FLAG_HT6 LL_DMA_ISR_HTIF6
#define | DMA_FLAG_TE6 LL_DMA_ISR_TEIF6
#define | DMA_FLAG_GL7 LL_DMA_ISR_GIF7
#define | DMA_FLAG_TC7 LL_DMA_ISR_TCIF7
#define | DMA_FLAG_HT7 LL_DMA_ISR_HTIF7
#define | DMA_FLAG_TE7 LL_DMA_ISR_TEIF7

Define Documentation

#define DMA_FLAG_GL1 LL_DMA_ISR_GIF1

Channel 1 global flag

Definition at line 325 of file stm32wbxx_hal_dma.h.

#define DMA_FLAG_GL2 LL_DMA_ISR_GIF2

Channel 2 global flag

Definition at line 329 of file stm32wbxx_hal_dma.h.

#define DMA_FLAG_GL3 LL_DMA_ISR_GIF3

Channel 3 global flag

Definition at line 333 of file stm32wbxx_hal_dma.h.

#define DMA_FLAG_GL4 LL_DMA_ISR_GIF4

Channel 4 global flag

Definition at line 337 of file stm32wbxx_hal_dma.h.

#define DMA_FLAG_GL5 LL_DMA_ISR_GIF5

Channel 5 global flag

Definition at line 341 of file stm32wbxx_hal_dma.h.

#define DMA_FLAG_GL6 LL_DMA_ISR_GIF6

Channel 6 global flag

Definition at line 345 of file stm32wbxx_hal_dma.h.

#define DMA_FLAG_GL7 LL_DMA_ISR_GIF7

Channel 7 global flag

Definition at line 349 of file stm32wbxx_hal_dma.h.

#define DMA_FLAG_HT1 LL_DMA_ISR_HTIF1

Channel 1 half transfer flag

Definition at line 327 of file stm32wbxx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define DMA_FLAG_HT2 LL_DMA_ISR_HTIF2

Channel 2 half transfer flag

Definition at line 331 of file stm32wbxx_hal_dma.h.

#define DMA_FLAG_HT3 LL_DMA_ISR_HTIF3

Channel 3 half transfer flag

Definition at line 335 of file stm32wbxx_hal_dma.h.

#define DMA_FLAG_HT4 LL_DMA_ISR_HTIF4

Channel 4 half transfer flag

Definition at line 339 of file stm32wbxx_hal_dma.h.

#define DMA_FLAG_HT5 LL_DMA_ISR_HTIF5

Channel 5 half transfer flag

Definition at line 343 of file stm32wbxx_hal_dma.h.

#define DMA_FLAG_HT6 LL_DMA_ISR_HTIF6

Channel 6 half transfer flag

Definition at line 347 of file stm32wbxx_hal_dma.h.

#define DMA_FLAG_HT7 LL_DMA_ISR_HTIF7

Channel 7 half transfer flag

Definition at line 351 of file stm32wbxx_hal_dma.h.

#define DMA_FLAG_TC1 LL_DMA_ISR_TCIF1

Channel 1 transfer complete flag

Definition at line 326 of file stm32wbxx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define DMA_FLAG_TC2 LL_DMA_ISR_TCIF2

Channel 2 transfer complete flag

Definition at line 330 of file stm32wbxx_hal_dma.h.

#define DMA_FLAG_TC3 LL_DMA_ISR_TCIF3

Channel 3 transfer complete flag

Definition at line 334 of file stm32wbxx_hal_dma.h.

#define DMA_FLAG_TC4 LL_DMA_ISR_TCIF4

Channel 4 transfer complete flag

Definition at line 338 of file stm32wbxx_hal_dma.h.

#define DMA_FLAG_TC5 LL_DMA_ISR_TCIF5

Channel 5 transfer complete flag

Definition at line 342 of file stm32wbxx_hal_dma.h.

#define DMA_FLAG_TC6 LL_DMA_ISR_TCIF6

Channel 6 transfer complete flag

Definition at line 346 of file stm32wbxx_hal_dma.h.

#define DMA_FLAG_TC7 LL_DMA_ISR_TCIF7

Channel 7 transfer complete flag

Definition at line 350 of file stm32wbxx_hal_dma.h.

#define DMA_FLAG_TE1 LL_DMA_ISR_TEIF1

Channel 1 transfer error flag

Definition at line 328 of file stm32wbxx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define DMA_FLAG_TE2 LL_DMA_ISR_TEIF2

Channel 2 transfer error flag

Definition at line 332 of file stm32wbxx_hal_dma.h.

#define DMA_FLAG_TE3 LL_DMA_ISR_TEIF3

Channel 3 transfer error flag

Definition at line 336 of file stm32wbxx_hal_dma.h.

#define DMA_FLAG_TE4 LL_DMA_ISR_TEIF4

Channel 4 transfer error flag

Definition at line 340 of file stm32wbxx_hal_dma.h.

#define DMA_FLAG_TE5 LL_DMA_ISR_TEIF5

Channel 5 transfer error flag

Definition at line 344 of file stm32wbxx_hal_dma.h.

#define DMA_FLAG_TE6 LL_DMA_ISR_TEIF6

Channel 6 transfer error flag

Definition at line 348 of file stm32wbxx_hal_dma.h.

#define DMA_FLAG_TE7 LL_DMA_ISR_TEIF7

Channel 7 transfer error flag

Definition at line 352 of file stm32wbxx_hal_dma.h.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DMA Exported Macros

Defines
DMA Exported Macros
DMA

Defines

#define | __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
Reset DMA handle state.
#define | __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
Enable the specified DMA Channel.
#define | __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
Disable the specified DMA Channel.
#define | __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel transfer complete flag.
#define | __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel half transfer complete flag.
#define | __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel transfer error flag.
#define | __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel Global interrupt flag.
#define | __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)
Get the DMA Channel pending flags.
#define | __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the DMA Channel pending flags.
#define | __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
Enable the specified DMA Channel interrupts.
#define | __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
Disable the specified DMA Channel interrupts.
#define | __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
Check whether the specified DMA Channel interrupt is enabled or not.
#define | __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
Return the number of remaining data units in the current DMA Channel transfer.

Define Documentation

#define __HAL_DMA_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
(((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
 (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))

Clear the DMA Channel pending flags.

Parameters:
__HANDLE__ DMA handle
__FLAG__ specifies the flag to clear. This parameter can be any combination of the following values:
  • DMA_FLAG_TCx: Transfer complete flag
  • DMA_FLAG_HTx: Half transfer complete flag
  • DMA_FLAG_TEx: Transfer error flag
  • DMA_FLAG_GLx: Global interrupt flag Where x can be from 1 to 7 to select the DMA Channel x flag.
Return values:
None

Definition at line 546 of file stm32wbxx_hal_dma.h.

#define __HAL_DMA_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)

Disable the specified DMA Channel.

Parameters:
__HANDLE__ DMA handle
Return values:
None

Definition at line 384 of file stm32wbxx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Start(), HAL_DMA_Start_IT(), and HAL_QSPI_IRQHandler().

#define __HAL_DMA_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))

Disable the specified DMA Channel interrupts.

Parameters:
__HANDLE__ DMA handle
__INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • DMA_IT_TC: Transfer complete interrupt mask
  • DMA_IT_HT: Half transfer complete interrupt mask
  • DMA_IT_TE: Transfer error interrupt mask
Return values:
None

Definition at line 574 of file stm32wbxx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_IRQHandler(), and HAL_DMA_Start_IT().

#define __HAL_DMA_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)

Enable the specified DMA Channel.

Parameters:
__HANDLE__ DMA handle
Return values:
None

Definition at line 377 of file stm32wbxx_hal_dma.h.

Referenced by HAL_DMA_Start(), and HAL_DMA_Start_IT().

#define __HAL_DMA_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))

Enable the specified DMA Channel interrupts.

Parameters:
__HANDLE__ DMA handle
__INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • DMA_IT_TC: Transfer complete interrupt mask
  • DMA_IT_HT: Half transfer complete interrupt mask
  • DMA_IT_TE: Transfer error interrupt mask
Return values:
None

Definition at line 562 of file stm32wbxx_hal_dma.h.

Referenced by HAL_DMA_Start_IT().

#define __HAL_DMA_GET_COUNTER ( __HANDLE__ ) ((__HANDLE__)->Instance->CNDTR)

Return the number of remaining data units in the current DMA Channel transfer.

Parameters:
__HANDLE__ DMA handle
Return values:
The number of remaining data units in the current DMA Channel transfer.

Definition at line 593 of file stm32wbxx_hal_dma.h.

Referenced by I2C_DMASlaveReceiveCplt(), I2C_ITSlaveCplt(), and I2C_Slave_ISR_DMA().

#define __HAL_DMA_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
(((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
 (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))

Get the DMA Channel pending flags.

Parameters:
__HANDLE__ DMA handle
__FLAG__ Get the specified flag. This parameter can be any combination of the following values:
  • DMA_FLAG_TCx: Transfer complete flag
  • DMA_FLAG_HTx: Half transfer complete flag
  • DMA_FLAG_TEx: Transfer error flag
  • DMA_FLAG_GLx: Global interrupt flag Where x can be from 1 to 7 to select the DMA Channel x flag.
Return values:
The state of FLAG (SET or RESET).

Definition at line 527 of file stm32wbxx_hal_dma.h.

#define __HAL_DMA_GET_GI_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\
   DMA_ISR_GIF7)

Return the current DMA Channel Global interrupt flag.

Parameters:
__HANDLE__ DMA handle
Return values:
The specified transfer error flag index.

Definition at line 489 of file stm32wbxx_hal_dma.h.

#define __HAL_DMA_GET_HT_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\
   DMA_FLAG_HT7)

Return the current DMA Channel half transfer complete flag.

Parameters:
__HANDLE__ DMA handle
Return values:
The specified half transfer complete flag index.

Definition at line 427 of file stm32wbxx_hal_dma.h.

#define __HAL_DMA_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))

Check whether the specified DMA Channel interrupt is enabled or not.

Parameters:
__HANDLE__ DMA handle
__INTERRUPT__ specifies the DMA interrupt source to check. This parameter can be one of the following values:
  • DMA_IT_TC: Transfer complete interrupt mask
  • DMA_IT_HT: Half transfer complete interrupt mask
  • DMA_IT_TE: Transfer error interrupt mask
Return values:
The state of DMA_IT (SET or RESET).

Definition at line 586 of file stm32wbxx_hal_dma.h.

#define __HAL_DMA_GET_TC_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\
   DMA_FLAG_TC7)

Return the current DMA Channel transfer complete flag.

Parameters:
__HANDLE__ DMA handle
Return values:
The specified transfer complete flag index.

Definition at line 396 of file stm32wbxx_hal_dma.h.

#define __HAL_DMA_GET_TE_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\
   DMA_FLAG_TE7)

Return the current DMA Channel transfer error flag.

Parameters:
__HANDLE__ DMA handle
Return values:
The specified transfer error flag index.

Definition at line 458 of file stm32wbxx_hal_dma.h.

#define __HAL_DMA_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)

Reset DMA handle state.

Parameters:
__HANDLE__ DMA handle
Return values:
None

Definition at line 370 of file stm32wbxx_hal_dma.h.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DMA Private Macros

Defines
DMA Private Macros
DMA

Defines

#define | IS_DMA_DIRECTION(DIRECTION)
#define | IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
#define | IS_DMA_PERIPHERAL_INC_STATE(STATE)
#define | IS_DMA_MEMORY_INC_STATE(STATE)
#define | IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_REQUEST_AES2_OUT)
#define | IS_DMA_PERIPHERAL_DATA_SIZE(SIZE)
#define | IS_DMA_MEMORY_DATA_SIZE(SIZE)
#define | IS_DMA_MODE(MODE)
#define | IS_DMA_PRIORITY(PRIORITY)

Define Documentation

#define IS_DMA_ALL_REQUEST ( REQUEST ) ((REQUEST) <= DMA_REQUEST_AES2_OUT)

Definition at line 667 of file stm32wbxx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_BUFFER_SIZE ( SIZE ) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))

Definition at line 658 of file stm32wbxx_hal_dma.h.

Referenced by HAL_DMA_Start(), and HAL_DMA_Start_IT().

#define IS_DMA_DIRECTION ( DIRECTION )
Value:
(((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
                                                 ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
                                                 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))

Definition at line 654 of file stm32wbxx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_MEMORY_DATA_SIZE ( SIZE )
Value:
(((SIZE) == DMA_MDATAALIGN_BYTE)     || \
                                                 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
                                                 ((SIZE) == DMA_MDATAALIGN_WORD ))

Definition at line 673 of file stm32wbxx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_MEMORY_INC_STATE ( STATE )
Value:
(((STATE) == DMA_MINC_ENABLE)   || \
                                                 ((STATE) == DMA_MINC_DISABLE))

Definition at line 663 of file stm32wbxx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_MODE ( MODE )
Value:
(((MODE) == DMA_NORMAL )  || \
                                                 ((MODE) == DMA_CIRCULAR))

Definition at line 677 of file stm32wbxx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_PERIPHERAL_DATA_SIZE ( SIZE )
Value:
(((SIZE) == DMA_PDATAALIGN_BYTE)     || \
                                                 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
                                                 ((SIZE) == DMA_PDATAALIGN_WORD))

Definition at line 669 of file stm32wbxx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_PERIPHERAL_INC_STATE ( STATE )
Value:
(((STATE) == DMA_PINC_ENABLE)   || \
                                                 ((STATE) == DMA_PINC_DISABLE))

Definition at line 660 of file stm32wbxx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_PRIORITY ( PRIORITY )
Value:
(((PRIORITY) == DMA_PRIORITY_LOW )   || \
                                                 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
                                                 ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
                                                 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))

Definition at line 680 of file stm32wbxx_hal_dma.h.

Referenced by HAL_DMA_Init().

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DMAEx Extended features functions

Functions
DMAEx Extended features functions
DMAEx Exported Functions

Extended features functions. More...

Functions

HAL_StatusTypeDef | HAL_DMAEx_ConfigMuxSync (DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
Configure the DMAMUX synchronization parameters for a given DMA channel (instance).
HAL_StatusTypeDef | HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
Configure the DMAMUX request generator block used by the given DMA channel (instance).
HAL_StatusTypeDef | HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
Enable the DMAMUX request generator block used by the given DMA channel (instance).
HAL_StatusTypeDef | HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
Disable the DMAMUX request generator block used by the given DMA channel (instance).
void | HAL_DMAEx_MUX_IRQHandler (DMA_HandleTypeDef *hdma)
Handles DMAMUX interrupt request.

Detailed Description

Extended features functions.

 ===============================================================================
                #####  Extended features functions  #####
 ===============================================================================
    [..]  This section provides functions allowing to:

    (+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
    (+) Configure the DMAMUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
       Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
       to respectively enable/disable the request generator.

Function Documentation

HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator | ( | DMA_HandleTypeDef * | hdma,
 |  | HAL_DMA_MuxRequestGeneratorConfigTypeDef * | pRequestGeneratorConfig
 | ) |  |

Configure the DMAMUX request generator block used by the given DMA channel (instance).

Parameters:
hdma | Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA channel.
pRequestGeneratorConfig | Pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef : contains the request generator parameters.
Return values:
HAL status

Definition at line 142 of file stm32wbxx_hal_dma_ex.c.

References assert_param, __DMA_HandleTypeDef::DMAmuxRequestGen, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::Instance, IS_DMAMUX_REQUEST_GEN_POLARITY, IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER, IS_DMAMUX_REQUEST_GEN_SIGNAL_ID, HAL_DMA_MuxRequestGeneratorConfigTypeDef::Polarity, HAL_DMA_MuxRequestGeneratorConfigTypeDef::RequestNumber, HAL_DMA_MuxRequestGeneratorConfigTypeDef::SignalID, and __DMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync | ( | DMA_HandleTypeDef * | hdma,
 |  | HAL_DMA_MuxSyncConfigTypeDef * | pSyncConfig
 | ) |  |

Configure the DMAMUX synchronization parameters for a given DMA channel (instance).

Parameters:
hdma | Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA channel.
pSyncConfig | Pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters
Return values:
HAL status

Definition at line 95 of file stm32wbxx_hal_dma_ex.c.

References assert_param, __DMA_HandleTypeDef::DMAmuxChannel, HAL_DMA_MuxSyncConfigTypeDef::EventEnable, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::Instance, IS_DMAMUX_SYNC_EVENT, IS_DMAMUX_SYNC_POLARITY, IS_DMAMUX_SYNC_REQUEST_NUMBER, IS_DMAMUX_SYNC_SIGNAL_ID, IS_DMAMUX_SYNC_STATE, HAL_DMA_MuxSyncConfigTypeDef::RequestNumber, __DMA_HandleTypeDef::State, HAL_DMA_MuxSyncConfigTypeDef::SyncEnable, HAL_DMA_MuxSyncConfigTypeDef::SyncPolarity, and HAL_DMA_MuxSyncConfigTypeDef::SyncSignalID.

HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator ( DMA_HandleTypeDef * hdma )

Disable the DMAMUX request generator block used by the given DMA channel (instance).

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA channel.
Return values:
HAL status

Definition at line 208 of file stm32wbxx_hal_dma_ex.c.

References assert_param, __DMA_HandleTypeDef::DMAmuxRequestGen, HAL_DMA_STATE_RESET, __DMA_HandleTypeDef::Instance, and __DMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator ( DMA_HandleTypeDef * hdma )

Enable the DMAMUX request generator block used by the given DMA channel (instance).

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA channel.
Return values:
HAL status

Definition at line 181 of file stm32wbxx_hal_dma_ex.c.

References assert_param, __DMA_HandleTypeDef::DMAmuxRequestGen, HAL_DMA_STATE_RESET, __DMA_HandleTypeDef::Instance, and __DMA_HandleTypeDef::State.

void HAL_DMAEx_MUX_IRQHandler ( DMA_HandleTypeDef * hdma )

Handles DMAMUX interrupt request.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA channel.
Return values:
None

Definition at line 235 of file stm32wbxx_hal_dma_ex.c.

References __DMA_HandleTypeDef::DMAmuxChannel, __DMA_HandleTypeDef::DMAmuxChannelStatus, __DMA_HandleTypeDef::DMAmuxChannelStatusMask, __DMA_HandleTypeDef::DMAmuxRequestGen, __DMA_HandleTypeDef::DMAmuxRequestGenStatus, __DMA_HandleTypeDef::DMAmuxRequestGenStatusMask, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_REQGEN, HAL_DMA_ERROR_SYNC, and __DMA_HandleTypeDef::XferErrorCallback.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: HAL_DMA_MuxSyncConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HAL_DMA_MuxSyncConfigTypeDef Struct Reference
DMAEx Exported Types

HAL DMA Synchro definition. More...

#include <stm32wbxx_hal_dma_ex.h>

Data Fields

uint32_t | SyncSignalID
uint32_t | SyncPolarity
FunctionalState | SyncEnable
FunctionalState | EventEnable
uint32_t | RequestNumber

Detailed Description

HAL DMA Synchro definition.

HAL DMAMUX Synchronization configuration structure definition

Definition at line 53 of file stm32wbxx_hal_dma_ex.h.

Field Documentation

FunctionalState HAL_DMA_MuxSyncConfigTypeDef::EventEnable

Specifies if an event shall be generated once the RequestNumber is reached. This parameter can take the value ENABLE or DISABLE

Definition at line 64 of file stm32wbxx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

uint32_t HAL_DMA_MuxSyncConfigTypeDef::RequestNumber

Specifies the number of DMA request that will be authorized after a sync event This parameter must be a number between Min_Data = 1 and Max_Data = 32

Definition at line 67 of file stm32wbxx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

FunctionalState HAL_DMA_MuxSyncConfigTypeDef::SyncEnable

Specifies if the synchronization shall be enabled or disabled This parameter can take the value ENABLE or DISABLE

Definition at line 61 of file stm32wbxx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

uint32_t HAL_DMA_MuxSyncConfigTypeDef::SyncPolarity

Specifies the polarity of the signal on which the DMA request is synchronized. This parameter can be a value of DMAMUX SyncPolarity selection

Definition at line 58 of file stm32wbxx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

uint32_t HAL_DMA_MuxSyncConfigTypeDef::SyncSignalID

Specifies the synchronization signal gating the DMA request in periodic mode. This parameter can be a value of DMAMUX SyncSignalID selection

Definition at line 55 of file stm32wbxx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_dma_ex.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: HAL_DMA_MuxRequestGeneratorConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
HAL_DMA_MuxRequestGeneratorConfigTypeDef Struct Reference
DMAEx Exported Types

HAL DMAMUX request generator parameters structure definition. More...

#include <stm32wbxx_hal_dma_ex.h>

Data Fields

uint32_t | SignalID
uint32_t | Polarity
uint32_t | RequestNumber

Detailed Description

HAL DMAMUX request generator parameters structure definition.

Definition at line 77 of file stm32wbxx_hal_dma_ex.h.

Field Documentation

uint32_t HAL_DMA_MuxRequestGeneratorConfigTypeDef::Polarity

Specifies the polarity of the signal on which the request is generated. This parameter can be a value of DMAMUX RequestGeneneratorPolarity selection

Definition at line 82 of file stm32wbxx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxRequestGenerator().

uint32_t HAL_DMA_MuxRequestGeneratorConfigTypeDef::RequestNumber

Specifies the number of DMA request that will be generated after a signal event This parameter must be a number between Min_Data = 1 and Max_Data = 32

Definition at line 85 of file stm32wbxx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxRequestGenerator().

uint32_t HAL_DMA_MuxRequestGeneratorConfigTypeDef::SignalID

Specifies the ID of the signal used for DMAMUX request generator This parameter can be a value of DMAMUX SignalGeneratorID selection

Definition at line 79 of file stm32wbxx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxRequestGenerator().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_dma_ex.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DMAMUX SyncSignalID selection

Defines
DMAMUX SyncSignalID selection
DMAEx Exported Constants

Defines

#define | HAL_DMAMUX1_SYNC_EXTI0 LL_DMAMUX_SYNC_EXTI_LINE0
#define | HAL_DMAMUX1_SYNC_EXTI1 LL_DMAMUX_SYNC_EXTI_LINE1
#define | HAL_DMAMUX1_SYNC_EXTI2 LL_DMAMUX_SYNC_EXTI_LINE2
#define | HAL_DMAMUX1_SYNC_EXTI3 LL_DMAMUX_SYNC_EXTI_LINE3
#define | HAL_DMAMUX1_SYNC_EXTI4 LL_DMAMUX_SYNC_EXTI_LINE4
#define | HAL_DMAMUX1_SYNC_EXTI5 LL_DMAMUX_SYNC_EXTI_LINE5
#define | HAL_DMAMUX1_SYNC_EXTI6 LL_DMAMUX_SYNC_EXTI_LINE6
#define | HAL_DMAMUX1_SYNC_EXTI7 LL_DMAMUX_SYNC_EXTI_LINE7
#define | HAL_DMAMUX1_SYNC_EXTI8 LL_DMAMUX_SYNC_EXTI_LINE8
#define | HAL_DMAMUX1_SYNC_EXTI9 LL_DMAMUX_SYNC_EXTI_LINE9
#define | HAL_DMAMUX1_SYNC_EXTI10 LL_DMAMUX_SYNC_EXTI_LINE10
#define | HAL_DMAMUX1_SYNC_EXTI11 LL_DMAMUX_SYNC_EXTI_LINE11
#define | HAL_DMAMUX1_SYNC_EXTI12 LL_DMAMUX_SYNC_EXTI_LINE12
#define | HAL_DMAMUX1_SYNC_EXTI13 LL_DMAMUX_SYNC_EXTI_LINE13
#define | HAL_DMAMUX1_SYNC_EXTI14 LL_DMAMUX_SYNC_EXTI_LINE14
#define | HAL_DMAMUX1_SYNC_EXTI15 LL_DMAMUX_SYNC_EXTI_LINE15
#define | HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT LL_DMAMUX_SYNC_DMAMUX_CH0
#define | HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT LL_DMAMUX_SYNC_DMAMUX_CH1
#define | HAL_DMAMUX1_SYNC_LPTIM1_OUT LL_DMAMUX_SYNC_LPTIM1_OUT
#define | HAL_DMAMUX1_SYNC_LPTIM2_OUT LL_DMAMUX_SYNC_LPTIM2_OUT

Define Documentation

#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT LL_DMAMUX_SYNC_DMAMUX_CH0

Synchronization Signal is DMAMUX1 Channel0 Event

Definition at line 118 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT LL_DMAMUX_SYNC_DMAMUX_CH1

Synchronization Signal is DMAMUX1 Channel1 Event

Definition at line 119 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI0 LL_DMAMUX_SYNC_EXTI_LINE0

Synchronization Signal is EXTI0 IT

Definition at line 102 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI1 LL_DMAMUX_SYNC_EXTI_LINE1

Synchronization Signal is EXTI1 IT

Definition at line 103 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI10 LL_DMAMUX_SYNC_EXTI_LINE10

Synchronization Signal is EXTI10 IT

Definition at line 112 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI11 LL_DMAMUX_SYNC_EXTI_LINE11

Synchronization Signal is EXTI11 IT

Definition at line 113 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI12 LL_DMAMUX_SYNC_EXTI_LINE12

Synchronization Signal is EXTI12 IT

Definition at line 114 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI13 LL_DMAMUX_SYNC_EXTI_LINE13

Synchronization Signal is EXTI13 IT

Definition at line 115 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI14 LL_DMAMUX_SYNC_EXTI_LINE14

Synchronization Signal is EXTI14 IT

Definition at line 116 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI15 LL_DMAMUX_SYNC_EXTI_LINE15

Synchronization Signal is EXTI15 IT

Definition at line 117 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI2 LL_DMAMUX_SYNC_EXTI_LINE2

Synchronization Signal is EXTI2 IT

Definition at line 104 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI3 LL_DMAMUX_SYNC_EXTI_LINE3

Synchronization Signal is EXTI3 IT

Definition at line 105 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI4 LL_DMAMUX_SYNC_EXTI_LINE4

Synchronization Signal is EXTI4 IT

Definition at line 106 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI5 LL_DMAMUX_SYNC_EXTI_LINE5

Synchronization Signal is EXTI5 IT

Definition at line 107 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI6 LL_DMAMUX_SYNC_EXTI_LINE6

Synchronization Signal is EXTI6 IT

Definition at line 108 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI7 LL_DMAMUX_SYNC_EXTI_LINE7

Synchronization Signal is EXTI7 IT

Definition at line 109 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI8 LL_DMAMUX_SYNC_EXTI_LINE8

Synchronization Signal is EXTI8 IT

Definition at line 110 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_EXTI9 LL_DMAMUX_SYNC_EXTI_LINE9

Synchronization Signal is EXTI9 IT

Definition at line 111 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_LPTIM1_OUT LL_DMAMUX_SYNC_LPTIM1_OUT

Synchronization Signal is LPTIM1 OUT

Definition at line 120 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX1_SYNC_LPTIM2_OUT LL_DMAMUX_SYNC_LPTIM2_OUT

Synchronization Signal is LPTIM2 OUT

Definition at line 121 of file stm32wbxx_hal_dma_ex.h.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DMAMUX SyncPolarity selection

Defines
DMAMUX SyncPolarity selection
DMAEx Exported Constants

Defines

#define | HAL_DMAMUX_SYNC_NO_EVENT LL_DMAMUX_SYNC_NO_EVENT
#define | HAL_DMAMUX_SYNC_RISING LL_DMAMUX_SYNC_POL_RISING
#define | HAL_DMAMUX_SYNC_FALLING LL_DMAMUX_SYNC_POL_FALLING
#define | HAL_DMAMUX_SYNC_RISING_FALLING LL_DMAMUX_SYNC_POL_RISING_FALLING

Define Documentation

#define HAL_DMAMUX_SYNC_FALLING LL_DMAMUX_SYNC_POL_FALLING

synchronize with falling edge events

Definition at line 132 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX_SYNC_NO_EVENT LL_DMAMUX_SYNC_NO_EVENT

block synchronization events

Definition at line 130 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX_SYNC_RISING LL_DMAMUX_SYNC_POL_RISING

synchronize with rising edge events

Definition at line 131 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX_SYNC_RISING_FALLING LL_DMAMUX_SYNC_POL_RISING_FALLING

synchronize with rising and falling edge events

Definition at line 133 of file stm32wbxx_hal_dma_ex.h.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DMAMUX SignalGeneratorID selection

Defines
DMAMUX SignalGeneratorID selection
DMAEx Exported Constants

Defines

#define | HAL_DMAMUX1_REQ_GEN_EXTI0 LL_DMAMUX_REQ_GEN_EXTI_LINE0
#define | HAL_DMAMUX1_REQ_GEN_EXTI1 LL_DMAMUX_REQ_GEN_EXTI_LINE1
#define | HAL_DMAMUX1_REQ_GEN_EXTI2 LL_DMAMUX_REQ_GEN_EXTI_LINE2
#define | HAL_DMAMUX1_REQ_GEN_EXTI3 LL_DMAMUX_REQ_GEN_EXTI_LINE3
#define | HAL_DMAMUX1_REQ_GEN_EXTI4 LL_DMAMUX_REQ_GEN_EXTI_LINE4
#define | HAL_DMAMUX1_REQ_GEN_EXTI5 LL_DMAMUX_REQ_GEN_EXTI_LINE5
#define | HAL_DMAMUX1_REQ_GEN_EXTI6 LL_DMAMUX_REQ_GEN_EXTI_LINE6
#define | HAL_DMAMUX1_REQ_GEN_EXTI7 LL_DMAMUX_REQ_GEN_EXTI_LINE7
#define | HAL_DMAMUX1_REQ_GEN_EXTI8 LL_DMAMUX_REQ_GEN_EXTI_LINE8
#define | HAL_DMAMUX1_REQ_GEN_EXTI9 LL_DMAMUX_REQ_GEN_EXTI_LINE9
#define | HAL_DMAMUX1_REQ_GEN_EXTI10 LL_DMAMUX_REQ_GEN_EXTI_LINE10
#define | HAL_DMAMUX1_REQ_GEN_EXTI11 LL_DMAMUX_REQ_GEN_EXTI_LINE11
#define | HAL_DMAMUX1_REQ_GEN_EXTI12 LL_DMAMUX_REQ_GEN_EXTI_LINE12
#define | HAL_DMAMUX1_REQ_GEN_EXTI13 LL_DMAMUX_REQ_GEN_EXTI_LINE13
#define | HAL_DMAMUX1_REQ_GEN_EXTI14 LL_DMAMUX_REQ_GEN_EXTI_LINE14
#define | HAL_DMAMUX1_REQ_GEN_EXTI15 LL_DMAMUX_REQ_GEN_EXTI_LINE15
#define | HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH0
#define | HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH1
#define | HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT LL_DMAMUX_REQ_GEN_LPTIM1_OUT
#define | HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT LL_DMAMUX_REQ_GEN_LPTIM2_OUT

Define Documentation

#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH0

Request generator Signal is DMAMUX1 Channel0 Event

Definition at line 158 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH1

Request generator Signal is DMAMUX1 Channel1 Event

Definition at line 159 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI0 LL_DMAMUX_REQ_GEN_EXTI_LINE0

Request generator Signal is EXTI0 IT

Definition at line 142 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI1 LL_DMAMUX_REQ_GEN_EXTI_LINE1

Request generator Signal is EXTI1 IT

Definition at line 143 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI10 LL_DMAMUX_REQ_GEN_EXTI_LINE10

Request generator Signal is EXTI10 IT

Definition at line 152 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI11 LL_DMAMUX_REQ_GEN_EXTI_LINE11

Request generator Signal is EXTI11 IT

Definition at line 153 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI12 LL_DMAMUX_REQ_GEN_EXTI_LINE12

Request generator Signal is EXTI12 IT

Definition at line 154 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI13 LL_DMAMUX_REQ_GEN_EXTI_LINE13

Request generator Signal is EXTI13 IT

Definition at line 155 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI14 LL_DMAMUX_REQ_GEN_EXTI_LINE14

Request generator Signal is EXTI14 IT

Definition at line 156 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI15 LL_DMAMUX_REQ_GEN_EXTI_LINE15

Request generator Signal is EXTI15 IT

Definition at line 157 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI2 LL_DMAMUX_REQ_GEN_EXTI_LINE2

Request generator Signal is EXTI2 IT

Definition at line 144 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI3 LL_DMAMUX_REQ_GEN_EXTI_LINE3

Request generator Signal is EXTI3 IT

Definition at line 145 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI4 LL_DMAMUX_REQ_GEN_EXTI_LINE4

Request generator Signal is EXTI4 IT

Definition at line 146 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI5 LL_DMAMUX_REQ_GEN_EXTI_LINE5

Request generator Signal is EXTI5 IT

Definition at line 147 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI6 LL_DMAMUX_REQ_GEN_EXTI_LINE6

Request generator Signal is EXTI6 IT

Definition at line 148 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI7 LL_DMAMUX_REQ_GEN_EXTI_LINE7

Request generator Signal is EXTI7 IT

Definition at line 149 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI8 LL_DMAMUX_REQ_GEN_EXTI_LINE8

Request generator Signal is EXTI8 IT

Definition at line 150 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_EXTI9 LL_DMAMUX_REQ_GEN_EXTI_LINE9

Request generator Signal is EXTI9 IT

Definition at line 151 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT LL_DMAMUX_REQ_GEN_LPTIM1_OUT

Request generator Signal is LPTIM1 OUT

Definition at line 160 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT LL_DMAMUX_REQ_GEN_LPTIM2_OUT

Request generator Signal is LPTIM2 OUT

Definition at line 161 of file stm32wbxx_hal_dma_ex.h.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DMAMUX RequestGeneneratorPolarity selection

Defines
DMAMUX RequestGeneneratorPolarity selection
DMAEx Exported Constants

Defines

#define | HAL_DMAMUX_REQ_GEN_NO_EVENT LL_DMAMUX_REQ_GEN_NO_EVENT
#define | HAL_DMAMUX_REQ_GEN_RISING LL_DMAMUX_REQ_GEN_POL_RISING
#define | HAL_DMAMUX_REQ_GEN_FALLING LL_DMAMUX_REQ_GEN_POL_FALLING
#define | HAL_DMAMUX_REQ_GEN_RISING_FALLING LL_DMAMUX_REQ_GEN_POL_RISING_FALLING

Define Documentation

#define HAL_DMAMUX_REQ_GEN_FALLING LL_DMAMUX_REQ_GEN_POL_FALLING

generate request on falling edge events

Definition at line 172 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX_REQ_GEN_NO_EVENT LL_DMAMUX_REQ_GEN_NO_EVENT

block request generator events

Definition at line 170 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX_REQ_GEN_RISING LL_DMAMUX_REQ_GEN_POL_RISING

generate request on rising edge events

Definition at line 171 of file stm32wbxx_hal_dma_ex.h.

#define HAL_DMAMUX_REQ_GEN_RISING_FALLING LL_DMAMUX_REQ_GEN_POL_RISING_FALLING

generate request on rising and falling edge events

Definition at line 173 of file stm32wbxx_hal_dma_ex.h.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DMAEx Private Macros

Defines
DMAEx Private Macros
DMAEx

DMAEx private macros. More...

Defines

#define | IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_LPTIM2_OUT)
#define | IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
#define | IS_DMAMUX_SYNC_POLARITY(POLARITY)
#define | IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE))
#define | IS_DMAMUX_SYNC_EVENT(EVENT)
#define | IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT)
#define | IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
#define | IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY)

Detailed Description

DMAEx private macros.

Define Documentation

#define IS_DMAMUX_REQUEST_GEN_POLARITY ( POLARITY )
Value:
(((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT)    || \
                                                                 ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING)      || \
                                                                 ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING)     || \
                                                                 ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING))

Definition at line 241 of file stm32wbxx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxRequestGenerator().

#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER ( REQUEST_NUMBER ) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))

Definition at line 239 of file stm32wbxx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxRequestGenerator().

#define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID ( SIGNAL_ID ) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT)

Definition at line 237 of file stm32wbxx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxRequestGenerator().

#define IS_DMAMUX_SYNC_EVENT ( EVENT )
Value:
(((EVENT) == DISABLE)   || \
                                                                 ((EVENT) == ENABLE))

Definition at line 234 of file stm32wbxx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

#define IS_DMAMUX_SYNC_POLARITY ( POLARITY )
Value:
(((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT)     || \
                                                                 ((POLARITY) == HAL_DMAMUX_SYNC_RISING)       || \
                                                                 ((POLARITY) == HAL_DMAMUX_SYNC_FALLING)      || \
                                                                 ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))

Definition at line 227 of file stm32wbxx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

#define IS_DMAMUX_SYNC_REQUEST_NUMBER ( REQUEST_NUMBER ) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))

Definition at line 225 of file stm32wbxx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

#define IS_DMAMUX_SYNC_SIGNAL_ID ( SIGNAL_ID ) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_LPTIM2_OUT)

Definition at line 223 of file stm32wbxx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

#define IS_DMAMUX_SYNC_STATE ( SYNC ) (((SYNC) == DISABLE) || ((SYNC) == ENABLE))

Definition at line 232 of file stm32wbxx_hal_dma_ex.h.

Referenced by HAL_DMAEx_ConfigMuxSync().

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: EXTI Private Constants

Defines
EXTI Private Constants
EXTI

MISRA C:2012 deviation rule has been granted for following rule: Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out of bounds [0,3] in following API : HAL_EXTI_SetConfigLine HAL_EXTI_GetConfigLine HAL_EXTI_ClearConfigLine. More...

Defines

#define | EXTI_MODE_OFFSET 0x04u /* 0x10: offset between CPU IMR/EMR registers */
#define | EXTI_CONFIG_OFFSET 0x08u /* 0x20: offset between CPU Rising/Falling configuration registers */
#define | EXTI_PROPERTY_SHIFT 24u
EXTI Line property definition.
#define | EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT)
#define | EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
#define | EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
#define | EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)
#define | EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
#define | EXTI_EVENT_PRESENCE_SHIFT 28u
EXTI Event presence definition.
#define | EXTI_EVENT (0x01uL << EXTI_EVENT_PRESENCE_SHIFT)
#define | EXTI_EVENT_PRESENCE_MASK (EXTI_EVENT)
#define | EXTI_REG_SHIFT 16u
EXTI Register and bit usage.
#define | EXTI_REG1 (0x00uL << EXTI_REG_SHIFT)
#define | EXTI_REG2 (0x01uL << EXTI_REG_SHIFT)
#define | EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2)
#define | EXTI_PIN_MASK 0x0000001Fu
#define | EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
EXTI Mask for interrupt & event mode.
#define | EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
EXTI Mask for trigger possibilities.
#define | EXTI_LINE_NB 49uL
EXTI Line number.

Detailed Description

MISRA C:2012 deviation rule has been granted for following rule: Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out of bounds [0,3] in following API : HAL_EXTI_SetConfigLine HAL_EXTI_GetConfigLine HAL_EXTI_ClearConfigLine.

Define Documentation

#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)

Definition at line 204 of file stm32wbxx_hal_exti.h.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

#define EXTI_CONFIG_OFFSET 0x08u /* 0x20: offset between CPU Rising/Falling configuration registers */

Definition at line 110 of file stm32wbxx_hal_exti.c.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_ClearPending(), HAL_EXTI_GenerateSWI(), HAL_EXTI_GetConfigLine(), HAL_EXTI_GetPending(), HAL_EXTI_IRQHandler(), and HAL_EXTI_SetConfigLine().

#define EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT)

Definition at line 203 of file stm32wbxx_hal_exti.h.

#define EXTI_EVENT (0x01uL << EXTI_EVENT_PRESENCE_SHIFT)

Definition at line 213 of file stm32wbxx_hal_exti.h.

Referenced by HAL_EXTI_SetConfigLine().

#define EXTI_EVENT_PRESENCE_MASK (EXTI_EVENT)

Definition at line 214 of file stm32wbxx_hal_exti.h.

#define EXTI_EVENT_PRESENCE_SHIFT 28u

EXTI Event presence definition.

Definition at line 212 of file stm32wbxx_hal_exti.h.

#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)

Definition at line 205 of file stm32wbxx_hal_exti.h.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

#define EXTI_LINE_NB 49uL

EXTI Line number.

Definition at line 238 of file stm32wbxx_hal_exti.h.

#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)

EXTI Mask for interrupt & event mode.

Definition at line 228 of file stm32wbxx_hal_exti.h.

#define EXTI_MODE_OFFSET 0x04u /* 0x10: offset between CPU IMR/EMR registers */

Definition at line 109 of file stm32wbxx_hal_exti.c.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

#define EXTI_PIN_MASK 0x0000001Fu

Definition at line 223 of file stm32wbxx_hal_exti.h.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_ClearPending(), HAL_EXTI_GenerateSWI(), HAL_EXTI_GetConfigLine(), HAL_EXTI_GetPending(), HAL_EXTI_IRQHandler(), and HAL_EXTI_SetConfigLine().

#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)

Definition at line 207 of file stm32wbxx_hal_exti.h.

#define EXTI_PROPERTY_SHIFT 24u

EXTI Line property definition.

Definition at line 202 of file stm32wbxx_hal_exti.h.

#define EXTI_REG1 (0x00uL << EXTI_REG_SHIFT)

Definition at line 220 of file stm32wbxx_hal_exti.h.

#define EXTI_REG2 (0x01uL << EXTI_REG_SHIFT)

Definition at line 221 of file stm32wbxx_hal_exti.h.

#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2)

Definition at line 222 of file stm32wbxx_hal_exti.h.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_ClearPending(), HAL_EXTI_GenerateSWI(), HAL_EXTI_GetConfigLine(), HAL_EXTI_GetPending(), HAL_EXTI_IRQHandler(), and HAL_EXTI_SetConfigLine().

#define EXTI_REG_SHIFT 16u

EXTI Register and bit usage.

Definition at line 219 of file stm32wbxx_hal_exti.h.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_ClearPending(), HAL_EXTI_GenerateSWI(), HAL_EXTI_GetConfigLine(), HAL_EXTI_GetPending(), HAL_EXTI_IRQHandler(), and HAL_EXTI_SetConfigLine().

#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)

Definition at line 206 of file stm32wbxx_hal_exti.h.

#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)

EXTI Mask for trigger possibilities.

Definition at line 233 of file stm32wbxx_hal_exti.h.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: EXTI Exported Types

Data Structures | Enumerations
EXTI Exported Types
EXTI

Data Structures

struct | EXTI_HandleTypeDef
EXTI Handle structure definition. More...
struct | EXTI_ConfigTypeDef
EXTI Configuration structure definition. More...

Enumerations

enum | EXTI_CallbackIDTypeDef { HAL_EXTI_COMMON_CB_ID = 0x00U }

Enumeration Type Documentation

enum EXTI_CallbackIDTypeDef
Enumerator:
HAL_EXTI_COMMON_CB_ID

Definition at line 45 of file stm32wbxx_hal_exti.h.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: EXTI_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
EXTI_HandleTypeDef Struct Reference
EXTI Exported Types

EXTI Handle structure definition. More...

#include <stm32wbxx_hal_exti.h>

Data Fields

uint32_t | Line
void(* | PendingCallback )(void)

Detailed Description

EXTI Handle structure definition.

Definition at line 54 of file stm32wbxx_hal_exti.h.

Field Documentation

uint32_t EXTI_HandleTypeDef::Line

Exti line number

Definition at line 56 of file stm32wbxx_hal_exti.h.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_ClearPending(), HAL_EXTI_GenerateSWI(), HAL_EXTI_GetConfigLine(), HAL_EXTI_GetHandle(), HAL_EXTI_GetPending(), HAL_EXTI_IRQHandler(), and HAL_EXTI_SetConfigLine().

void(* EXTI_HandleTypeDef::PendingCallback)(void)

Exti pending callback

Definition at line 57 of file stm32wbxx_hal_exti.h.

Referenced by HAL_EXTI_IRQHandler(), and HAL_EXTI_RegisterCallback().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_exti.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: EXTI_ConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
EXTI_ConfigTypeDef Struct Reference
EXTI Exported Types

EXTI Configuration structure definition. More...

#include <stm32wbxx_hal_exti.h>

Data Fields

uint32_t | Line
uint32_t | Mode
uint32_t | Trigger
uint32_t | GPIOSel

Detailed Description

EXTI Configuration structure definition.

Definition at line 63 of file stm32wbxx_hal_exti.h.

Field Documentation

uint32_t EXTI_ConfigTypeDef::GPIOSel

The Exti GPIO multiplexer selection to be configured. This parameter is only possible for line 0 to 15. It can be a value of EXTI GPIOSel

Definition at line 71 of file stm32wbxx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

uint32_t EXTI_ConfigTypeDef::Line

The Exti line to be configured. This parameter can be a value of EXTI Line

Definition at line 65 of file stm32wbxx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

uint32_t EXTI_ConfigTypeDef::Mode

The Exit Mode to be configured for a core. This parameter can be a combination of EXTI Mode

Definition at line 67 of file stm32wbxx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

uint32_t EXTI_ConfigTypeDef::Trigger

The Exti Trigger to be configured. This parameter can be a value of EXTI Trigger

Definition at line 69 of file stm32wbxx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_exti.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: EXTI Line

Defines
EXTI Line
EXTI Exported Constants

Defines

#define | EXTI_LINE_0 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x00u)
#define | EXTI_LINE_1 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x01u)
#define | EXTI_LINE_2 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x02u)
#define | EXTI_LINE_3 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x03u)
#define | EXTI_LINE_4 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x04u)
#define | EXTI_LINE_5 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x05u)
#define | EXTI_LINE_6 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x06u)
#define | EXTI_LINE_7 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x07u)
#define | EXTI_LINE_8 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x08u)
#define | EXTI_LINE_9 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x09u)
#define | EXTI_LINE_10 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Au)
#define | EXTI_LINE_11 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Bu)
#define | EXTI_LINE_12 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Cu)
#define | EXTI_LINE_13 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Du)
#define | EXTI_LINE_14 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Eu)
#define | EXTI_LINE_15 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Fu)
#define | EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10u)
#define | EXTI_LINE_17 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x11u)
#define | EXTI_LINE_18 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x12u)
#define | EXTI_LINE_19 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x13u)
#define | EXTI_LINE_20 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x14u)
#define | EXTI_LINE_21 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x15u)
#define | EXTI_LINE_22 (EXTI_DIRECT | EXTI_REG1 | 0x16u)
#define | EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17u)
#define | EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18u)
#define | EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19u)
#define | EXTI_LINE_26 (EXTI_RESERVED | EXTI_REG1 | 0x1Au)
#define | EXTI_LINE_27 (EXTI_RESERVED | EXTI_REG1 | 0x1Bu)
#define | EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1Cu)
#define | EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | 0x1Du)
#define | EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | 0x1Eu)
#define | EXTI_LINE_31 (EXTI_CONFIG | EXTI_REG1 | 0x1Fu)
#define | EXTI_LINE_32 (EXTI_RESERVED | EXTI_REG2 | 0x00u)
#define | EXTI_LINE_33 (EXTI_CONFIG | EXTI_REG2 | 0x01u)
#define | EXTI_LINE_34 (EXTI_RESERVED | EXTI_REG2 | 0x02u)
#define | EXTI_LINE_35 (EXTI_RESERVED | EXTI_REG2 | 0x03u)
#define | EXTI_LINE_36 (EXTI_DIRECT | EXTI_REG2 | 0x04u)
#define | EXTI_LINE_37 (EXTI_DIRECT | EXTI_REG2 | 0x05u)
#define | EXTI_LINE_38 (EXTI_DIRECT | EXTI_REG2 | 0x06u)
#define | EXTI_LINE_39 (EXTI_DIRECT | EXTI_REG2 | 0x07u)
#define | EXTI_LINE_40 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | 0x08u)
#define | EXTI_LINE_41 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | 0x09u)
#define | EXTI_LINE_42 (EXTI_DIRECT | EXTI_REG2 | 0x0Au)
#define | EXTI_LINE_43 (EXTI_DIRECT | EXTI_REG2 | 0x0Bu)
#define | EXTI_LINE_44 (EXTI_DIRECT | EXTI_REG2 | 0x0Cu)
#define | EXTI_LINE_45 (EXTI_DIRECT | EXTI_REG2 | 0x0Du)
#define | EXTI_LINE_46 (EXTI_DIRECT | EXTI_REG2 | 0x0Eu)
#define | EXTI_LINE_47 (EXTI_RESERVED | EXTI_REG2 | 0x0Fu)
#define | EXTI_LINE_48 (EXTI_DIRECT | EXTI_REG2 | 0x10u)

Define Documentation

#define EXTI_LINE_0 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x00u)

Definition at line 88 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_1 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x01u)

Definition at line 89 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_10 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Au)

Definition at line 98 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_11 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Bu)

Definition at line 99 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_12 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Cu)

Definition at line 100 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_13 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Du)

Definition at line 101 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_14 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Eu)

Definition at line 102 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_15 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Fu)

Definition at line 103 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10u)

Definition at line 104 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_17 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x11u)

Definition at line 105 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x12u)

Definition at line 106 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x13u)

Definition at line 107 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_2 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x02u)

Definition at line 90 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x14u)

Definition at line 108 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x15u)

Definition at line 109 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_22 (EXTI_DIRECT | EXTI_REG1 | 0x16u)

Definition at line 110 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17u)

Definition at line 111 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18u)

Definition at line 112 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19u)

Definition at line 113 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_26 (EXTI_RESERVED | EXTI_REG1 | 0x1Au)

Definition at line 114 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_27 (EXTI_RESERVED | EXTI_REG1 | 0x1Bu)

Definition at line 115 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1Cu)

Definition at line 116 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | 0x1Du)

Definition at line 117 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_3 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x03u)

Definition at line 91 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | 0x1Eu)

Definition at line 118 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_31 (EXTI_CONFIG | EXTI_REG1 | 0x1Fu)

Definition at line 119 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_32 (EXTI_RESERVED | EXTI_REG2 | 0x00u)

Definition at line 120 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_33 (EXTI_CONFIG | EXTI_REG2 | 0x01u)

Definition at line 121 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_34 (EXTI_RESERVED | EXTI_REG2 | 0x02u)

Definition at line 122 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_35 (EXTI_RESERVED | EXTI_REG2 | 0x03u)

Definition at line 123 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_36 (EXTI_DIRECT | EXTI_REG2 | 0x04u)

Definition at line 124 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_37 (EXTI_DIRECT | EXTI_REG2 | 0x05u)

Definition at line 125 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_38 (EXTI_DIRECT | EXTI_REG2 | 0x06u)

Definition at line 126 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_39 (EXTI_DIRECT | EXTI_REG2 | 0x07u)

Definition at line 127 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_4 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x04u)

Definition at line 92 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_40 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | 0x08u)

Definition at line 128 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_41 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | 0x09u)

Definition at line 129 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_42 (EXTI_DIRECT | EXTI_REG2 | 0x0Au)

Definition at line 130 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_43 (EXTI_DIRECT | EXTI_REG2 | 0x0Bu)

Definition at line 132 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_44 (EXTI_DIRECT | EXTI_REG2 | 0x0Cu)

Definition at line 136 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_45 (EXTI_DIRECT | EXTI_REG2 | 0x0Du)

Definition at line 137 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_46 (EXTI_DIRECT | EXTI_REG2 | 0x0Eu)

Definition at line 138 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_47 (EXTI_RESERVED | EXTI_REG2 | 0x0Fu)

Definition at line 139 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_48 (EXTI_DIRECT | EXTI_REG2 | 0x10u)

Definition at line 140 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_5 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x05u)

Definition at line 93 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_6 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x06u)

Definition at line 94 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_7 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x07u)

Definition at line 95 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_8 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x08u)

Definition at line 96 of file stm32wbxx_hal_exti.h.

#define EXTI_LINE_9 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x09u)

Definition at line 97 of file stm32wbxx_hal_exti.h.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: EXTI Mode

Defines
EXTI Mode
EXTI Exported Constants

Defines

#define | EXTI_MODE_NONE 0x00000000u
#define | EXTI_MODE_INTERRUPT 0x00000001u
#define | EXTI_MODE_EVENT 0x00000002u

Define Documentation

#define EXTI_MODE_EVENT 0x00000002u

Definition at line 150 of file stm32wbxx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

#define EXTI_MODE_INTERRUPT 0x00000001u

Definition at line 149 of file stm32wbxx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

#define EXTI_MODE_NONE 0x00000000u

Definition at line 148 of file stm32wbxx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine().

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: EXTI Trigger

Defines
EXTI Trigger
EXTI Exported Constants

Defines

#define | EXTI_TRIGGER_NONE 0x00000000u
#define | EXTI_TRIGGER_RISING 0x00000001u
#define | EXTI_TRIGGER_FALLING 0x00000002u
#define | EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)

Define Documentation

#define EXTI_TRIGGER_FALLING 0x00000002u

Definition at line 160 of file stm32wbxx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

#define EXTI_TRIGGER_NONE 0x00000000u

Definition at line 158 of file stm32wbxx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine().

#define EXTI_TRIGGER_RISING 0x00000001u

Definition at line 159 of file stm32wbxx_hal_exti.h.

Referenced by HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)

Definition at line 161 of file stm32wbxx_hal_exti.h.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: EXTI GPIOSel

Defines
EXTI GPIOSel
EXTI Exported Constants

Defines

#define | EXTI_GPIOA 0x00000000u
#define | EXTI_GPIOB 0x00000001u
#define | EXTI_GPIOC 0x00000002u
#define | EXTI_GPIOD 0x00000003u
#define | EXTI_GPIOE 0x00000004u
#define | EXTI_GPIOH 0x00000007u

Define Documentation

#define EXTI_GPIOA 0x00000000u

Definition at line 170 of file stm32wbxx_hal_exti.h.

#define EXTI_GPIOB 0x00000001u

Definition at line 171 of file stm32wbxx_hal_exti.h.

#define EXTI_GPIOC 0x00000002u

Definition at line 172 of file stm32wbxx_hal_exti.h.

#define EXTI_GPIOD 0x00000003u

Definition at line 174 of file stm32wbxx_hal_exti.h.

#define EXTI_GPIOE 0x00000004u

Definition at line 176 of file stm32wbxx_hal_exti.h.

#define EXTI_GPIOH 0x00000007u

Definition at line 177 of file stm32wbxx_hal_exti.h.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: EXTI Exported Macros

EXTI Exported Macros
EXTI
Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: EXTI Private Macros

Defines
EXTI Private Macros
EXTI

Defines

#define | IS_EXTI_LINE(__LINE__)
#define | IS_EXTI_MODE(__LINE__)
#define | IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
#define | IS_EXTI_PENDING_EDGE(__LINE__) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING)
#define | IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u)
#define | IS_EXTI_GPIO_PORT(__PORT__)
#define | IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)

Define Documentation

#define IS_EXTI_CONFIG_LINE ( __LINE__ ) (((__LINE__) & EXTI_CONFIG) != 0x00u)

Definition at line 262 of file stm32wbxx_hal_exti.h.

Referenced by HAL_EXTI_ClearPending(), HAL_EXTI_GenerateSWI(), and HAL_EXTI_GetPending().

#define IS_EXTI_GPIO_PIN ( __PIN__ ) ((__PIN__) < 16u)

Definition at line 279 of file stm32wbxx_hal_exti.h.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_GetConfigLine(), and HAL_EXTI_SetConfigLine().

#define IS_EXTI_GPIO_PORT ( __PORT__ )
Value:
(((__PORT__) == EXTI_GPIOA) || \
                                         ((__PORT__) == EXTI_GPIOB) || \
                                         ((__PORT__) == EXTI_GPIOC) || \
                                         ((__PORT__) == EXTI_GPIOD) || \
                                         ((__PORT__) == EXTI_GPIOE) || \
                                         ((__PORT__) == EXTI_GPIOH))

Definition at line 265 of file stm32wbxx_hal_exti.h.

Referenced by HAL_EXTI_SetConfigLine().

#define IS_EXTI_LINE ( __LINE__ )
Value:
((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \
                                        ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT)   || \
                                         (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG)   || \
                                         (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO))    && \
                                         (((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK))      < \
                                         (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))))

Definition at line 248 of file stm32wbxx_hal_exti.h.

Referenced by HAL_EXTI_ClearConfigLine(), HAL_EXTI_ClearPending(), HAL_EXTI_GenerateSWI(), HAL_EXTI_GetConfigLine(), HAL_EXTI_GetHandle(), HAL_EXTI_GetPending(), and HAL_EXTI_SetConfigLine().

#define IS_EXTI_MODE ( __LINE__ )
Value:
((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \
                                         (((__LINE__) & ~EXTI_MODE_MASK) == 0x00u))

Definition at line 255 of file stm32wbxx_hal_exti.h.

Referenced by HAL_EXTI_SetConfigLine().

#define IS_EXTI_PENDING_EDGE ( __LINE__ ) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING)

Definition at line 260 of file stm32wbxx_hal_exti.h.

Referenced by HAL_EXTI_ClearPending(), and HAL_EXTI_GetPending().

#define IS_EXTI_TRIGGER ( __LINE__ ) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)

Definition at line 258 of file stm32wbxx_hal_exti.h.

Referenced by HAL_EXTI_SetConfigLine().

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Configuration functions

Functions
Configuration functions
EXTI Exported Functions

Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_EXTI_SetConfigLine (EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
Set configuration of a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_GetConfigLine (EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
Get configuration of a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_ClearConfigLine (EXTI_HandleTypeDef *hexti)
Clear whole configuration of a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_RegisterCallback (EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void(*pPendingCbfn)(void))
Register callback for a dedicaated Exti line.
HAL_StatusTypeDef | HAL_EXTI_GetHandle (EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
Store line number as handle private field.

Detailed Description

Configuration functions.

 ===============================================================================
              ##### Configuration functions #####
 ===============================================================================

Function Documentation

HAL_StatusTypeDef HAL_EXTI_ClearConfigLine ( EXTI_HandleTypeDef * hexti )

Clear whole configuration of a dedicated Exti line.

Parameters:
hexti Exti handle.
Return values:
HAL Status.

Definition at line 370 of file stm32wbxx_hal_exti.c.

References assert_param, EXTI_CONFIG, EXTI_CONFIG_OFFSET, EXTI_GPIO, EXTI_MODE_OFFSET, EXTI_PIN_MASK, EXTI_REG_MASK, EXTI_REG_SHIFT, IS_EXTI_GPIO_PIN, IS_EXTI_LINE, and EXTI_HandleTypeDef::Line.

HAL_StatusTypeDef HAL_EXTI_GetConfigLine | ( | EXTI_HandleTypeDef * | hexti,
 |  | EXTI_ConfigTypeDef * | pExtiConfig
 | ) |  |

Get configuration of a dedicated Exti line.

Parameters:
hexti | Exti handle.
pExtiConfig | Pointer on structure to store Exti configuration.
Return values:
HAL Status.

Definition at line 267 of file stm32wbxx_hal_exti.c.

References assert_param, EXTI_CONFIG, EXTI_CONFIG_OFFSET, EXTI_GPIO, EXTI_MODE_EVENT, EXTI_MODE_INTERRUPT, EXTI_MODE_NONE, EXTI_MODE_OFFSET, EXTI_PIN_MASK, EXTI_REG_MASK, EXTI_REG_SHIFT, EXTI_TRIGGER_FALLING, EXTI_TRIGGER_NONE, EXTI_TRIGGER_RISING, EXTI_ConfigTypeDef::GPIOSel, IS_EXTI_GPIO_PIN, IS_EXTI_LINE, EXTI_HandleTypeDef::Line, EXTI_ConfigTypeDef::Line, EXTI_ConfigTypeDef::Mode, and EXTI_ConfigTypeDef::Trigger.

HAL_StatusTypeDef HAL_EXTI_GetHandle | ( | EXTI_HandleTypeDef * | hexti,
 |  | uint32_t | ExtiLine
 | ) |  |

Store line number as handle private field.

Parameters:
hexti | Exti handle.
ExtiLine | Exti line number. This parameter can be from 0 to EXTI_LINE_NB.
Return values:
HAL Status.

Definition at line 462 of file stm32wbxx_hal_exti.c.

References assert_param, IS_EXTI_LINE, and EXTI_HandleTypeDef::Line.

HAL_StatusTypeDef HAL_EXTI_RegisterCallback | ( | EXTI_HandleTypeDef * | hexti,
 |  | EXTI_CallbackIDTypeDef | CallbackID,
 |  | void(*)(void) | pPendingCbfn
 | ) |  |

Register callback for a dedicaated Exti line.

Parameters:
hexti | Exti handle.
CallbackID User callback identifier. This parameter can be one of
  • EXTI_CallbackIDTypeDef values.
pPendingCbfn | function pointer to be stored as callback.
Return values:
HAL Status.

Definition at line 436 of file stm32wbxx_hal_exti.c.

References HAL_EXTI_COMMON_CB_ID, and EXTI_HandleTypeDef::PendingCallback.

HAL_StatusTypeDef HAL_EXTI_SetConfigLine | ( | EXTI_HandleTypeDef * | hexti,
 |  | EXTI_ConfigTypeDef * | pExtiConfig
 | ) |  |

Set configuration of a dedicated Exti line.

Parameters:
hexti | Exti handle.
pExtiConfig | Pointer on EXTI configuration to be set.
Return values:
HAL Status.

Definition at line 142 of file stm32wbxx_hal_exti.c.

References assert_param, EXTI_CONFIG, EXTI_CONFIG_OFFSET, EXTI_EVENT, EXTI_GPIO, EXTI_MODE_EVENT, EXTI_MODE_INTERRUPT, EXTI_MODE_OFFSET, EXTI_PIN_MASK, EXTI_REG_MASK, EXTI_REG_SHIFT, EXTI_TRIGGER_FALLING, EXTI_TRIGGER_RISING, EXTI_ConfigTypeDef::GPIOSel, IS_EXTI_GPIO_PIN, IS_EXTI_GPIO_PORT, IS_EXTI_LINE, IS_EXTI_MODE, IS_EXTI_TRIGGER, EXTI_HandleTypeDef::Line, EXTI_ConfigTypeDef::Line, EXTI_ConfigTypeDef::Mode, and EXTI_ConfigTypeDef::Trigger.

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STM32WB55xx HAL User Manual: IO operation functions

Functions
IO operation functions
EXTI Exported Functions

IO operation functions. More...

Functions

void | HAL_EXTI_IRQHandler (EXTI_HandleTypeDef *hexti)
Handle EXTI interrupt request.
uint32_t | HAL_EXTI_GetPending (EXTI_HandleTypeDef *hexti, uint32_t Edge)
Get interrupt pending bit of a dedicated line.
void | HAL_EXTI_ClearPending (EXTI_HandleTypeDef *hexti, uint32_t Edge)
Clear interrupt pending bit of a dedicated line.
void | HAL_EXTI_GenerateSWI (EXTI_HandleTypeDef *hexti)
Generate a software interrupt for a dedicated line.

Detailed Description

IO operation functions.

EXTI IO functions.

 ===============================================================================
                       ##### IO operation functions #####
 ===============================================================================

Function Documentation

void HAL_EXTI_ClearPending | ( | EXTI_HandleTypeDef * | hexti,
 |  | uint32_t | Edge
 | ) |  |

Clear interrupt pending bit of a dedicated line.

Parameters:
hexti Exti handle.
Edge Specify which pending edge as to be clear. This parameter can be one of the following values:
  • EXTI_TRIGGER_RISING_FALLING This parameter is kept for compatibility with other series.
Return values:
None.

Definition at line 577 of file stm32wbxx_hal_exti.c.

References assert_param, EXTI_CONFIG_OFFSET, EXTI_PIN_MASK, EXTI_REG_MASK, EXTI_REG_SHIFT, IS_EXTI_CONFIG_LINE, IS_EXTI_LINE, IS_EXTI_PENDING_EDGE, and EXTI_HandleTypeDef::Line.

void HAL_EXTI_GenerateSWI ( EXTI_HandleTypeDef * hexti )

Generate a software interrupt for a dedicated line.

Parameters:
hexti Exti handle.
Return values:
None.

Definition at line 605 of file stm32wbxx_hal_exti.c.

References assert_param, EXTI_CONFIG_OFFSET, EXTI_PIN_MASK, EXTI_REG_MASK, EXTI_REG_SHIFT, IS_EXTI_CONFIG_LINE, IS_EXTI_LINE, and EXTI_HandleTypeDef::Line.

uint32_t HAL_EXTI_GetPending | ( | EXTI_HandleTypeDef * | hexti,
 |  | uint32_t | Edge
 | ) |  |

Get interrupt pending bit of a dedicated line.

Parameters:
hexti Exti handle.
Edge Specify which pending edge as to be checked. This parameter can be one of the following values:
  • EXTI_TRIGGER_RISING_FALLING This parameter is kept for compatibility with other series.
Return values:
1 if interrupt is pending else 0.

Definition at line 541 of file stm32wbxx_hal_exti.c.

References assert_param, EXTI_CONFIG_OFFSET, EXTI_PIN_MASK, EXTI_REG_MASK, EXTI_REG_SHIFT, IS_EXTI_CONFIG_LINE, IS_EXTI_LINE, IS_EXTI_PENDING_EDGE, and EXTI_HandleTypeDef::Line.

void HAL_EXTI_IRQHandler ( EXTI_HandleTypeDef * hexti )

Handle EXTI interrupt request.

Parameters:
hexti Exti handle.
Return values:
none.

Definition at line 503 of file stm32wbxx_hal_exti.c.

References EXTI_CONFIG_OFFSET, EXTI_PIN_MASK, EXTI_REG_MASK, EXTI_REG_SHIFT, EXTI_HandleTypeDef::Line, and EXTI_HandleTypeDef::PendingCallback.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FLASH Private Variables

Variables
FLASH Private Variables
FLASH

Variables

FLASH_ProcessTypeDef pFlash
Variable used for Program/Erase sectors under interruption.

Variable Documentation

FLASH_ProcessTypeDef pFlash
Initial value:
 {.Lock = HAL_UNLOCKED,
                               .ErrorCode = HAL_FLASH_ERROR_NONE,
                               .ProcedureOnGoing = 0U,
                               .Address = 0U,
                               .Page = 0U,
                               .NbPagesToErase = 0U
                              }

Variable used for Program/Erase sectors under interruption.

Definition at line 124 of file stm32wbxx_hal_flash.c.

Referenced by HAL_FLASHEx_Erase(), HAL_FLASHEx_Erase_IT(), and HAL_FLASHEx_OBProgram().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FLASH Private Functions

Functions
FLASH Private Functions
FLASH

Functions

static void | FLASH_Program_DoubleWord (uint32_t Address, uint64_t Data)
Program double-word (64-bit) at a specified address.
static void | FLASH_Program_Fast (uint32_t Address, uint32_t DataAddress)
Fast program a 32 row double-word (64-bit) at a specified address.
HAL_StatusTypeDef | FLASH_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH operation to complete.

Function Documentation

static void FLASH_Program_DoubleWord | ( | uint32_t | Address,
 |  | uint64_t | Data
 | ) |  | [static]

Program double-word (64-bit) at a specified address.

Parameters:
Address | Specifies the address to be programmed.
Data | Specifies the data to be programmed.
Return values:
None

Definition at line 665 of file stm32wbxx_hal_flash.c.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

static __RAM_FUNC void FLASH_Program_Fast | ( | uint32_t | Address,
 |  | uint32_t | DataAddress
 | ) |  | [static]

Fast program a 32 row double-word (64-bit) at a specified address.

Parameters:
Address | Specifies the address to be programmed.
DataAddress | Specifies the address where the data are stored.
Return values:
None

Definition at line 687 of file stm32wbxx_hal_flash.c.

References __HAL_FLASH_GET_FLAG, FLASH_FLAG_BSY, and FLASH_NB_DOUBLE_WORDS_IN_ROW.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

HAL_StatusTypeDef FLASH_WaitForLastOperation ( uint32_t Timeout )

Wait for a FLASH operation to complete.

Parameters:
Timeout Maximum flash operation timeout
Return values:
HAL_StatusTypeDef HAL Status

Definition at line 607 of file stm32wbxx_hal_flash.c.

References __HAL_FLASH_CLEAR_FLAG, __HAL_FLASH_GET_FLAG, FLASH_ProcessTypeDef::ErrorCode, FLASH_FLAG_BSY, FLASH_FLAG_CFGBSY, FLASH_FLAG_EOP, FLASH_FLAG_SR_ERRORS, and HAL_GetTick().

Referenced by FLASH_OB_ProceedWriteOperation(), HAL_FLASH_Program(), HAL_FLASH_Program_IT(), HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

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STM32WB55xx HAL User Manual: Programming operation functions

Functions
Programming operation functions
FLASH Exported Functions

Programming operation functions. More...

Functions

HAL_StatusTypeDef | HAL_FLASH_Program (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program double word or fast program of a row at a specified address.
HAL_StatusTypeDef | HAL_FLASH_Program_IT (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program double word or fast program of a row at a specified address with interrupt enabled.
void | HAL_FLASH_IRQHandler (void)
Handle FLASH interrupt request.
__weak void | HAL_FLASH_EndOfOperationCallback (uint32_t ReturnValue)
FLASH end of operation interrupt callback.
__weak void | HAL_FLASH_OperationErrorCallback (uint32_t ReturnValue)
FLASH operation error interrupt callback.

Detailed Description

Programming operation functions.

 ===============================================================================
                  ##### Programming operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the FLASH
    program operations.

Function Documentation

void HAL_FLASH_EndOfOperationCallback ( uint32_t ReturnValue )

FLASH end of operation interrupt callback.

Parameters:
ReturnValue The value saved in this parameter depends on the ongoing procedure Mass Erase: 0 Page Erase: Page which has been erased Program: Address which was selected for data program
Return values:
None

Definition at line 397 of file stm32wbxx_hal_flash.c.

Referenced by HAL_FLASH_IRQHandler().

void HAL_FLASH_IRQHandler ( void )

Handle FLASH interrupt request.

Return values:
None

Definition at line 300 of file stm32wbxx_hal_flash.c.

References __HAL_FLASH_CLEAR_FLAG, __HAL_FLASH_DISABLE_IT, __HAL_FLASH_GET_FLAG, FLASH_ProcessTypeDef::Address, FLASH_ProcessTypeDef::ErrorCode, FLASH_FLAG_EOP, FLASH_FLAG_SR_ERRORS, FLASH_IT_EOP, FLASH_IT_OPERR, FLASH_PageErase(), FLASH_TYPEERASE_MASSERASE, FLASH_TYPEERASE_PAGES, FLASH_TYPENONE, FLASH_TYPEPROGRAM_DOUBLEWORD, FLASH_TYPEPROGRAM_FAST, HAL_FLASH_EndOfOperationCallback(), HAL_FLASH_OperationErrorCallback(), FLASH_ProcessTypeDef::NbPagesToErase, FLASH_ProcessTypeDef::Page, and FLASH_ProcessTypeDef::ProcedureOnGoing.

void HAL_FLASH_OperationErrorCallback ( uint32_t ReturnValue )

FLASH operation error interrupt callback.

Parameters:
ReturnValue The value saved in this parameter depends on the ongoing procedure Mass Erase: 0 Page Erase: Page number which returned an error Program: Address which was selected for data program
Return values:
None

Definition at line 415 of file stm32wbxx_hal_flash.c.

Referenced by HAL_FLASH_IRQHandler().

HAL_StatusTypeDef HAL_FLASH_Program | ( | uint32_t | TypeProgram,
 |  | uint32_t | Address,
 |  | uint64_t | Data
 | ) |  |

Program double word or fast program of a row at a specified address.

Note:
Before any operation, it is possible to check there is no operation suspended by call HAL_FLASHEx_IsOperationSuspended()
Parameters:
TypeProgram | Indicate the way to program at a specified address This parameter can be a value of FLASH Program Type
Address | Specifies the address to be programmed.
Data | Specifies the data to be programmed This parameter is the data for the double word program and the address where are stored the data for the row fast program.
Return values:
HAL_StatusTypeDef HAL Status

Definition at line 178 of file stm32wbxx_hal_flash.c.

References assert_param, FLASH_ProcessTypeDef::ErrorCode, FLASH_Program_DoubleWord(), FLASH_Program_Fast(), FLASH_TIMEOUT_VALUE, FLASH_TYPEPROGRAM_DOUBLEWORD, FLASH_WaitForLastOperation(), HAL_FLASH_ERROR_NONE, IS_ADDR_ALIGNED_64BITS, IS_FLASH_FAST_PROGRAM_ADDRESS, IS_FLASH_PROGRAM_ADDRESS, and IS_FLASH_TYPEPROGRAM.

HAL_StatusTypeDef HAL_FLASH_Program_IT | ( | uint32_t | TypeProgram,
 |  | uint32_t | Address,
 |  | uint64_t | Data
 | ) |  |

Program double word or fast program of a row at a specified address with interrupt enabled.

Note:
Before any operation, it is possible to check there is no operation suspended by call HAL_FLASHEx_IsOperationSuspended()
Parameters:
TypeProgram | Indicate the way to program at a specified address. This parameter can be a value of FLASH Program Type
Address | Specifies the address to be programmed.
Data | Specifies the data to be programmed This parameter is the data for the double word program and the address where are stored the data for the row fast program.
Return values:
HAL Status

Definition at line 242 of file stm32wbxx_hal_flash.c.

References __HAL_FLASH_ENABLE_IT, FLASH_ProcessTypeDef::Address, assert_param, FLASH_ProcessTypeDef::ErrorCode, FLASH_IT_EOP, FLASH_IT_OPERR, FLASH_Program_DoubleWord(), FLASH_Program_Fast(), FLASH_TIMEOUT_VALUE, FLASH_TYPEPROGRAM_DOUBLEWORD, FLASH_WaitForLastOperation(), HAL_FLASH_ERROR_NONE, IS_ADDR_ALIGNED_64BITS, IS_FLASH_FAST_PROGRAM_ADDRESS, IS_FLASH_PROGRAM_ADDRESS, IS_FLASH_TYPEPROGRAM, and FLASH_ProcessTypeDef::ProcedureOnGoing.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
FLASH Exported Functions

Management functions. More...

Functions

HAL_StatusTypeDef | HAL_FLASH_Unlock (void)
Unlock the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_Lock (void)
Lock the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_OB_Unlock (void)
Unlock the FLASH Option Bytes Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Lock (void)
Lock the FLASH Option Bytes Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Launch (void)
Launch the option byte loading.

Detailed Description

Management functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the FLASH
    memory operations.

Function Documentation

HAL_StatusTypeDef HAL_FLASH_Lock ( void )

Lock the FLASH control register access.

Return values:
HAL Status

Definition at line 472 of file stm32wbxx_hal_flash.c.

HAL_StatusTypeDef HAL_FLASH_OB_Launch ( void )

Launch the option byte loading.

Return values:
HAL Status

Definition at line 539 of file stm32wbxx_hal_flash.c.

HAL_StatusTypeDef HAL_FLASH_OB_Lock ( void )

Lock the FLASH Option Bytes Registers access.

Return values:
HAL Status

Definition at line 518 of file stm32wbxx_hal_flash.c.

HAL_StatusTypeDef HAL_FLASH_OB_Unlock ( void )

Unlock the FLASH Option Bytes Registers access.

Return values:
HAL Status

Definition at line 493 of file stm32wbxx_hal_flash.c.

References FLASH_OPTKEY1, and FLASH_OPTKEY2.

HAL_StatusTypeDef HAL_FLASH_Unlock ( void )

Unlock the FLASH control register access.

Return values:
HAL Status

Definition at line 448 of file stm32wbxx_hal_flash.c.

References FLASH_KEY1, and FLASH_KEY2.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
FLASH Exported Functions

Peripheral Errors functions. More...

Functions

uint32_t HAL_FLASH_GetError (void)
Get the specific FLASH error flag.

Detailed Description

Peripheral Errors functions.

 ===============================================================================
                ##### Peripheral Errors functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time Errors of the FLASH peripheral.

Function Documentation

uint32_t HAL_FLASH_GetError ( void )

Get the specific FLASH error flag.

Return values:
FLASH_ErrorCode The returned value can be
  • HAL_FLASH_ERROR_NONE No error set
  • HAL_FLASH_ERROR_OP FLASH Operation error
  • HAL_FLASH_ERROR_PROG FLASH Programming error
  • HAL_FLASH_ERROR_WRP FLASH Write protection error
  • HAL_FLASH_ERROR_PGA FLASH Programming alignment error
  • HAL_FLASH_ERROR_SIZ FLASH Size error
  • HAL_FLASH_ERROR_PGS FLASH Programming sequence error
  • HAL_FLASH_ERROR_MIS FLASH Fast programming data miss error
  • HAL_FLASH_ERROR_FAST FLASH Fast programming error
  • HAL_FLASH_ERROR_RD FLASH Read Protection error (PCROP)
  • HAL_FLASH_ERROR_OPTV FLASH Option validity error

Definition at line 583 of file stm32wbxx_hal_flash.c.

References FLASH_ProcessTypeDef::ErrorCode.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FLASH_EraseInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FLASH_EraseInitTypeDef Struct Reference
FLASH Exported Types

FLASH Erase structure definition. More...

#include <stm32wbxx_hal_flash.h>

Data Fields

uint32_t | TypeErase
uint32_t | Page
uint32_t | NbPages

Detailed Description

FLASH Erase structure definition.

Definition at line 47 of file stm32wbxx_hal_flash.h.

Field Documentation

uint32_t FLASH_EraseInitTypeDef::NbPages

Number of pages to be erased. This parameter must be a value between 1 and (FLASH_PAGE_NB - value of initial page)

Definition at line 53 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

uint32_t FLASH_EraseInitTypeDef::Page

Initial Flash page to erase when page erase is enabled This parameter must be a value between 0 and (FLASH_PAGE_NB - 1)

Definition at line 51 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

uint32_t FLASH_EraseInitTypeDef::TypeErase

Mass erase or page erase. This parameter can be a value of FLASH Erase Type

Definition at line 49 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_flash.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FLASH_OBProgramInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FLASH_OBProgramInitTypeDef Struct Reference
FLASH Exported Types

FLASH Option Bytes Program structure definition. More...

#include <stm32wbxx_hal_flash.h>

Data Fields

uint32_t | OptionType
uint32_t | WRPArea
uint32_t | WRPStartOffset
uint32_t | WRPEndOffset
uint32_t | RDPLevel
uint32_t | UserType
uint32_t | UserConfig
uint32_t | PCROPConfig
uint32_t | PCROP1AStartAddr
uint32_t | PCROP1AEndAddr
uint32_t | PCROP1BStartAddr
uint32_t | PCROP1BEndAddr
uint32_t | SecureFlashStartAddr
uint32_t | SecureRAM2aStartAddr
uint32_t | SecureRAM2bStartAddr
uint32_t | SecureMode
uint32_t | C2BootRegion
uint32_t | C2SecureBootVectAddr
uint32_t | IPCCdataBufAddr

Detailed Description

FLASH Option Bytes Program structure definition.

Definition at line 60 of file stm32wbxx_hal_flash.h.

Field Documentation

uint32_t FLASH_OBProgramInitTypeDef::C2BootRegion

CPU2 Secure Boot memory region(used for OPTIONBYTE_C2_BOOT_VECT). This parameter can be a value of CPU2 Option Bytes Reset Boot Vector

Definition at line 104 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_OB_SecureConfig(), and HAL_FLASHEx_OBGetConfig().

uint32_t FLASH_OBProgramInitTypeDef::C2SecureBootVectAddr

CPU2 Secure Boot reset vector (used for OPTIONBYTE_C2_BOOT_VECT). This parameter contains the CPU2 boot reset start address within the selected memory region. Make sure this parameter is word aligned.

Definition at line 106 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_OB_SecureConfig(), and HAL_FLASHEx_OBGetConfig().

uint32_t FLASH_OBProgramInitTypeDef::IPCCdataBufAddr

IPCC mailbox data buffer base address (used for OPTIONBYTE_IPCC_BUF_ADDR). This parameter contains the IPCC mailbox data buffer start address area in SRAM2. Make sure this parameter is double-word aligned.

Definition at line 109 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::OptionType

Option byte to be configured. This parameter can be a combination of the values of FLASH Option Bytes Type

Definition at line 62 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_OB_SecureConfig(), HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::PCROP1AEndAddr

PCROP Zone A End address (used for OPTIONBYTE_PCROP). It represents first address of end block to protect. Make sure this parameter is multiple of PCROP granularity

Definition at line 89 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::PCROP1AStartAddr

PCROP Zone A Start address (used for OPTIONBYTE_PCROP). It represents first address of start block to protect. Make sure this parameter is multiple of PCROP granularity

Definition at line 87 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::PCROP1BEndAddr

PCROP Zone B End address (used for OPTIONBYTE_PCROP). It represents first address of end block to protect. Make sure this parameter is multiple of PCROP granularity

Definition at line 93 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::PCROP1BStartAddr

PCROP Zone B Start address (used for OPTIONBYTE_PCROP). It represents first address of start block to protect. Make sure this parameter is multiple of PCROP granularity

Definition at line 91 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::PCROPConfig

Configuration of the PCROP (used for OPTIONBYTE_PCROP). This parameter must be a combination of values of FLASH PCROP ZONE and FLASH Option Bytes PCROP On RDP Level Type

Definition at line 84 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::RDPLevel

Set the read protection level (used for OPTIONBYTE_RDP). This parameter can be a value of FLASH Option Bytes Read Protection

Definition at line 71 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::SecureFlashStartAddr

Secure Flash start address (used for OPTIONBYTE_SECURE_MODE). This parameter must be a value between begin and end of Flash bank => Contains the start address of the first 4kB page of the secure Flash area

Definition at line 95 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_OB_SecureConfig(), and HAL_FLASHEx_OBGetConfig().

uint32_t FLASH_OBProgramInitTypeDef::SecureMode

Secure mode activated or desactivated. This parameter can be a value of Option Bytes FLASH Secure mode

Definition at line 102 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_OB_SecureConfig(), and HAL_FLASHEx_OBGetConfig().

uint32_t FLASH_OBProgramInitTypeDef::SecureRAM2aStartAddr

Secure Backup RAM2a start address (used for OPTIONBYTE_SECURE_MODE). This parameter can be a value of RAM2A address range in secure mode

Definition at line 98 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_OB_SecureConfig(), and HAL_FLASHEx_OBGetConfig().

uint32_t FLASH_OBProgramInitTypeDef::SecureRAM2bStartAddr

Secure non-Backup RAM2b start address (used for OPTIONBYTE_SECURE_MODE) This parameter can be a value of RAM2B address range in secure mode

Definition at line 100 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_OB_SecureConfig(), and HAL_FLASHEx_OBGetConfig().

uint32_t FLASH_OBProgramInitTypeDef::UserConfig

Value of the user option byte (used for OPTIONBYTE_USER). This parameter can be a combination of the values of FLASH Option Bytes Automatic Gain Control Trimming, FLASH Option Bytes User BOR Level FLASH Option Bytes User Reset On Stop, FLASH Option Bytes User Reset On Standby, FLASH Option Bytes User Reset On Shutdown, FLASH Option Bytes User IWDG Type, FLASH Option Bytes User IWDG Mode On Stop, FLASH Option Bytes User IWDG Mode On Standby, FLASH Option Bytes User WWDG Type, FLASH Option Bytes User BOOT1 Type, FLASH Option Bytes SRAM2 parity check, FLASH Option Bytes SRAM2 erase when system reset, FLASH Option Bytes User Software BOOT0, FLASH Option Bytes User nBOOT0 option bit

Definition at line 75 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::UserType

User option byte(s) to be configured (used for OPTIONBYTE_USER). This parameter can be a combination of FLASH Option Bytes User Type

Definition at line 73 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::WRPArea

Write protection area to be programmed (used for OPTIONBYTE_WRP). Only one WRP area could be programmed at the same time. This parameter can be value of FLASH WRP Area

Definition at line 64 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::WRPEndOffset

Write protection end offset (used for OPTIONBYTE_WRP). This parameter must be a value between WRPStartOffset and (max number of pages - 1)

Definition at line 69 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::WRPStartOffset

Write protection start offset (used for OPTIONBYTE_WRP). This parameter must be a value between 0 and (max number of pages - 1)

Definition at line 67 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_flash.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FLASH_ProcessTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FLASH_ProcessTypeDef Struct Reference
FLASH Exported Types

FLASH handle Structure definition. More...

#include <stm32wbxx_hal_flash.h>

Data Fields

HAL_LockTypeDef | Lock
uint32_t | ErrorCode
uint32_t | ProcedureOnGoing
uint32_t | Address
uint32_t | Page
uint32_t | NbPagesToErase

Detailed Description

FLASH handle Structure definition.

Definition at line 117 of file stm32wbxx_hal_flash.h.

Field Documentation

uint32_t FLASH_ProcessTypeDef::Address

Definition at line 122 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASH_Program_IT().

uint32_t FLASH_ProcessTypeDef::ErrorCode

Definition at line 120 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation(), HAL_FLASH_GetError(), HAL_FLASH_IRQHandler(), HAL_FLASH_Program(), HAL_FLASH_Program_IT(), HAL_FLASHEx_Erase(), HAL_FLASHEx_Erase_IT(), and HAL_FLASHEx_OBProgram().

HAL_LockTypeDef FLASH_ProcessTypeDef::Lock

Definition at line 119 of file stm32wbxx_hal_flash.h.

uint32_t FLASH_ProcessTypeDef::NbPagesToErase

Definition at line 124 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASHEx_Erase_IT().

uint32_t FLASH_ProcessTypeDef::Page

Definition at line 123 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASHEx_Erase_IT().

uint32_t FLASH_ProcessTypeDef::ProcedureOnGoing

Definition at line 121 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_flash.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FLASH Keys

Defines
FLASH Keys
FLASH Exported Constants

Defines

#define | FLASH_KEY1 0x45670123U
#define | FLASH_KEY2 0xCDEF89ABU
#define | FLASH_OPTKEY1 0x08192A3BU
#define | FLASH_OPTKEY2 0x4C5D6E7FU

Define Documentation

#define FLASH_KEY1 0x45670123U

Flash key1

Definition at line 139 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASH_Unlock().

#define FLASH_KEY2 0xCDEF89ABU

Flash key2: used with FLASH_KEY1 to unlock the FLASH registers access

Definition at line 140 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASH_Unlock().

#define FLASH_OPTKEY1 0x08192A3BU

Flash option byte key1

Definition at line 143 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASH_OB_Unlock().

#define FLASH_OPTKEY2 0x4C5D6E7FU

Flash option byte key2: used with FLASH_OPTKEY1 to allow option bytes operations

Definition at line 144 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASH_OB_Unlock().

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STM32WB55xx HAL User Manual: FLASH Latency

Defines
FLASH Latency
FLASH Exported Constants

Defines

#define | FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS
#define | FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS
#define | FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS
#define | FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS

Define Documentation

#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS

FLASH Zero wait state

Definition at line 153 of file stm32wbxx_hal_flash.h.

Referenced by RCC_SetFlashLatency().

#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS

FLASH One wait state

Definition at line 154 of file stm32wbxx_hal_flash.h.

Referenced by RCC_SetFlashLatency().

#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS

FLASH Two wait states

Definition at line 155 of file stm32wbxx_hal_flash.h.

Referenced by RCC_SetFlashLatency().

#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS

FLASH Three wait states

Definition at line 156 of file stm32wbxx_hal_flash.h.

Referenced by RCC_SetFlashLatency().

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STM32WB55xx HAL User Manual: FLASH Interrupts Definition

Defines
FLASH Interrupts Definition
FLASH Flags Definition

FLASH Interrupt definition. More...

Defines

#define | FLASH_IT_EOP FLASH_CR_EOPIE
#define | FLASH_IT_OPERR FLASH_CR_ERRIE
#define | FLASH_IT_RDERR FLASH_CR_RDERRIE
#define | FLASH_IT_ECCC (FLASH_ECCR_ECCCIE >> FLASH_ECCR_ECCCIE_Pos)

Detailed Description

FLASH Interrupt definition.

Define Documentation

#define FLASH_IT_ECCC (FLASH_ECCR_ECCCIE >> FLASH_ECCR_ECCCIE_Pos)

ECC Correction Interrupt source

Definition at line 198 of file stm32wbxx_hal_flash.h.

#define FLASH_IT_EOP FLASH_CR_EOPIE

End of FLASH Operation Interrupt source

Definition at line 195 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define FLASH_IT_OPERR FLASH_CR_ERRIE

Error Interrupt source

Definition at line 196 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define FLASH_IT_RDERR FLASH_CR_RDERRIE

PCROP Read Error Interrupt source

Definition at line 197 of file stm32wbxx_hal_flash.h.

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STM32WB55xx HAL User Manual: FLASH Error

Defines
FLASH Error
FLASH Flags Definition

Defines

#define | HAL_FLASH_ERROR_NONE 0x00000000U
#define | HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR
#define | HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR
#define | HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR
#define | HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR
#define | HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR
#define | HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR
#define | HAL_FLASH_ERROR_MIS FLASH_FLAG_MISERR
#define | HAL_FLASH_ERROR_FAST FLASH_FLAG_FASTERR
#define | HAL_FLASH_ERROR_RD FLASH_FLAG_RDERR
#define | HAL_FLASH_ERROR_OPTV FLASH_FLAG_OPTVERR

Define Documentation

#define HAL_FLASH_ERROR_FAST FLASH_FLAG_FASTERR

Definition at line 214 of file stm32wbxx_hal_flash.h.

#define HAL_FLASH_ERROR_MIS FLASH_FLAG_MISERR

Definition at line 213 of file stm32wbxx_hal_flash.h.

#define HAL_FLASH_ERROR_NONE 0x00000000U

Definition at line 206 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASH_Program(), HAL_FLASH_Program_IT(), HAL_FLASHEx_Erase(), HAL_FLASHEx_Erase_IT(), and HAL_FLASHEx_OBProgram().

#define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR

Definition at line 207 of file stm32wbxx_hal_flash.h.

#define HAL_FLASH_ERROR_OPTV FLASH_FLAG_OPTVERR

Definition at line 216 of file stm32wbxx_hal_flash.h.

#define HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR

Definition at line 210 of file stm32wbxx_hal_flash.h.

#define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR

Definition at line 212 of file stm32wbxx_hal_flash.h.

#define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR

Definition at line 208 of file stm32wbxx_hal_flash.h.

#define HAL_FLASH_ERROR_RD FLASH_FLAG_RDERR

Definition at line 215 of file stm32wbxx_hal_flash.h.

#define HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR

Definition at line 211 of file stm32wbxx_hal_flash.h.

#define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR

Definition at line 209 of file stm32wbxx_hal_flash.h.

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STM32WB55xx HAL User Manual: FLASH Erase Type

Defines
FLASH Erase Type
FLASH Flags Definition

Defines

#define | FLASH_TYPEERASE_PAGES FLASH_CR_PER
#define | FLASH_TYPEERASE_MASSERASE FLASH_CR_MER

Define Documentation

#define FLASH_TYPEERASE_MASSERASE FLASH_CR_MER

Flash mass erase activation

Definition at line 225 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

#define FLASH_TYPEERASE_PAGES FLASH_CR_PER

Pages erase only

Definition at line 224 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler().

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STM32WB55xx HAL User Manual: FLASH Program Type

Defines
FLASH Program Type
FLASH Flags Definition

Defines

#define | FLASH_TYPEPROGRAM_DOUBLEWORD FLASH_CR_PG
#define | FLASH_TYPEPROGRAM_FAST FLASH_CR_FSTPG

Define Documentation

#define FLASH_TYPEPROGRAM_DOUBLEWORD FLASH_CR_PG

Program a double-word (64-bit) at a specified address.

Definition at line 233 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

#define FLASH_TYPEPROGRAM_FAST FLASH_CR_FSTPG

Fast program a 64 row double-word (64-bit) at a specified address. And another 64 row double-word (64-bit) will be programmed

Definition at line 234 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler().

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STM32WB55xx HAL User Manual: FLASH Option Bytes Type

Defines
FLASH Option Bytes Type
FLASH Flags Definition

Defines

#define | OPTIONBYTE_WRP 0x00000001U
#define | OPTIONBYTE_RDP 0x00000002U
#define | OPTIONBYTE_USER 0x00000004U
#define | OPTIONBYTE_PCROP 0x00000008U
#define | OPTIONBYTE_IPCC_BUF_ADDR 0x00000010U
#define | OPTIONBYTE_C2_BOOT_VECT 0x00000100U
#define | OPTIONBYTE_SECURE_MODE 0x00000200U
#define | OPTIONBYTE_ALL

Define Documentation

#define OPTIONBYTE_ALL
Value:
(OPTIONBYTE_WRP   | OPTIONBYTE_RDP           | OPTIONBYTE_USER         | \
                                         OPTIONBYTE_PCROP | OPTIONBYTE_IPCC_BUF_ADDR | OPTIONBYTE_C2_BOOT_VECT | \
                                         OPTIONBYTE_SECURE_MODE)

All option byte configuration

Definition at line 250 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig().

#define OPTIONBYTE_C2_BOOT_VECT 0x00000100U

CPU2 Secure Boot reset vector

Definition at line 248 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_OB_SecureConfig(), and HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_IPCC_BUF_ADDR 0x00000010U

IPCC mailbox buffer address configuration

Definition at line 247 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_PCROP 0x00000008U

PCROP option byte configuration

Definition at line 246 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_RDP 0x00000002U

RDP option byte configuration

Definition at line 244 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_SECURE_MODE 0x00000200U

Secure mode on activated or not

Definition at line 249 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_OB_SecureConfig(), and HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_USER 0x00000004U

User option byte configuration

Definition at line 245 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_WRP 0x00000001U

WRP option byte configuration

Definition at line 243 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASHEx_OBProgram().

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STM32WB55xx HAL User Manual: FLASH WRP Area

Defines
FLASH WRP Area
FLASH Flags Definition

Defines

#define | OB_WRPAREA_BANK1_AREAA 0x00000000U
#define | OB_WRPAREA_BANK1_AREAB 0x00000001U

Define Documentation

#define OB_WRPAREA_BANK1_AREAA 0x00000000U

Flash Area A

Definition at line 260 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_OB_GetWRP(), FLASH_OB_WRPConfig(), and HAL_FLASHEx_OBGetConfig().

#define OB_WRPAREA_BANK1_AREAB 0x00000001U

Flash Area B

Definition at line 261 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig().

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STM32WB55xx HAL User Manual: FLASH Option Bytes Read Protection

Defines
FLASH Option Bytes Read Protection
FLASH Flags Definition

Defines

#define | OB_RDP_LEVEL_0 0x000000AAU
#define | OB_RDP_LEVEL_1 0x000000BBU
#define | OB_RDP_LEVEL_2 0x000000CCU

Define Documentation

#define OB_RDP_LEVEL_0 0x000000AAU

Definition at line 269 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_OB_GetRDP().

#define OB_RDP_LEVEL_1 0x000000BBU

Definition at line 270 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_OB_GetRDP().

#define OB_RDP_LEVEL_2 0x000000CCU

Warning: When enabling read protection level 2 it's no more possible to go back to level 1 or 0

Definition at line 271 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_OB_GetRDP().

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STM32WB55xx HAL User Manual: FLASH Option Bytes User Type

Defines
FLASH Option Bytes User Type
FLASH Flags Definition

Defines

#define | OB_USER_BOR_LEV FLASH_OPTR_BOR_LEV
#define | OB_USER_nRST_STOP FLASH_OPTR_nRST_STOP
#define | OB_USER_nRST_STDBY FLASH_OPTR_nRST_STDBY
#define | OB_USER_nRST_SHDW FLASH_OPTR_nRST_SHDW
#define | OB_USER_IWDG_SW FLASH_OPTR_IWDG_SW
#define | OB_USER_IWDG_STOP FLASH_OPTR_IWDG_STOP
#define | OB_USER_IWDG_STDBY FLASH_OPTR_IWDG_STDBY
#define | OB_USER_WWDG_SW FLASH_OPTR_WWDG_SW
#define | OB_USER_nBOOT1 FLASH_OPTR_nBOOT1
#define | OB_USER_SRAM2PE FLASH_OPTR_SRAM2PE
#define | OB_USER_SRAM2RST FLASH_OPTR_SRAM2RST
#define | OB_USER_nSWBOOT0 FLASH_OPTR_nSWBOOT0
#define | OB_USER_nBOOT0 FLASH_OPTR_nBOOT0
#define | OB_USER_AGC_TRIM FLASH_OPTR_AGC_TRIM
#define | OB_USER_ALL

Define Documentation

#define OB_USER_AGC_TRIM FLASH_OPTR_AGC_TRIM

Automatic Gain Control Trimming

Definition at line 293 of file stm32wbxx_hal_flash.h.

#define OB_USER_ALL
Value:
(OB_USER_BOR_LEV    | OB_USER_nRST_STOP | OB_USER_nRST_STDBY | \
                                         OB_USER_nRST_SHDW  | OB_USER_IWDG_SW   | OB_USER_IWDG_STOP  | \
                                         OB_USER_IWDG_STDBY | OB_USER_WWDG_SW   | OB_USER_nBOOT1     | \
                                         OB_USER_SRAM2PE    | OB_USER_SRAM2RST  | OB_USER_nSWBOOT0   | \
                                         OB_USER_nBOOT0     | OB_USER_AGC_TRIM)

all option bits

Definition at line 294 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_OB_GetUser(), and HAL_FLASHEx_OBGetConfig().

#define OB_USER_BOR_LEV FLASH_OPTR_BOR_LEV

BOR reset Level

Definition at line 280 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASHEx_OBProgram().

#define OB_USER_IWDG_STDBY FLASH_OPTR_IWDG_STDBY

Independent watchdog counter freeze in standby mode

Definition at line 286 of file stm32wbxx_hal_flash.h.

#define OB_USER_IWDG_STOP FLASH_OPTR_IWDG_STOP

Independent watchdog counter freeze in stop mode

Definition at line 285 of file stm32wbxx_hal_flash.h.

#define OB_USER_IWDG_SW FLASH_OPTR_IWDG_SW

Independent watchdog selection

Definition at line 284 of file stm32wbxx_hal_flash.h.

#define OB_USER_nBOOT0 FLASH_OPTR_nBOOT0

nBOOT0 option bit

Definition at line 292 of file stm32wbxx_hal_flash.h.

#define OB_USER_nBOOT1 FLASH_OPTR_nBOOT1

Boot configuration

Definition at line 288 of file stm32wbxx_hal_flash.h.

#define OB_USER_nRST_SHDW FLASH_OPTR_nRST_SHDW

Reset generated when entering the shutdown mode

Definition at line 283 of file stm32wbxx_hal_flash.h.

#define OB_USER_nRST_STDBY FLASH_OPTR_nRST_STDBY

Reset generated when entering the standby mode

Definition at line 282 of file stm32wbxx_hal_flash.h.

#define OB_USER_nRST_STOP FLASH_OPTR_nRST_STOP

Reset generated when entering the stop mode

Definition at line 281 of file stm32wbxx_hal_flash.h.

#define OB_USER_nSWBOOT0 FLASH_OPTR_nSWBOOT0

Software BOOT0

Definition at line 291 of file stm32wbxx_hal_flash.h.

#define OB_USER_SRAM2PE FLASH_OPTR_SRAM2PE

SRAM2 parity check enable

Definition at line 289 of file stm32wbxx_hal_flash.h.

#define OB_USER_SRAM2RST FLASH_OPTR_SRAM2RST

SRAM2 erase when system reset

Definition at line 290 of file stm32wbxx_hal_flash.h.

#define OB_USER_WWDG_SW FLASH_OPTR_WWDG_SW

Window watchdog selection

Definition at line 287 of file stm32wbxx_hal_flash.h.

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STM32WB55xx HAL User Manual: FLASH Option Bytes Automatic Gain Control Trimming

Defines
FLASH Option Bytes Automatic Gain Control Trimming
FLASH Flags Definition

Defines

#define | OB_AGC_TRIM_0 0x00000000U
#define | OB_AGC_TRIM_1 FLASH_OPTR_AGC_TRIM_0
#define | OB_AGC_TRIM_2 FLASH_OPTR_AGC_TRIM_1
#define | OB_AGC_TRIM_3 (FLASH_OPTR_AGC_TRIM_1 | FLASH_OPTR_AGC_TRIM_0)
#define | OB_AGC_TRIM_4 FLASH_OPTR_AGC_TRIM_2
#define | OB_AGC_TRIM_5 (FLASH_OPTR_AGC_TRIM_2 | FLASH_OPTR_AGC_TRIM_0)
#define | OB_AGC_TRIM_6 (FLASH_OPTR_AGC_TRIM_2 | FLASH_OPTR_AGC_TRIM_1)
#define | OB_AGC_TRIM_7 (FLASH_OPTR_AGC_TRIM_2 | FLASH_OPTR_AGC_TRIM_1 | FLASH_OPTR_AGC_TRIM_0)

Define Documentation

#define OB_AGC_TRIM_0 0x00000000U

Automatic Gain Control Trimming Value 0

Definition at line 307 of file stm32wbxx_hal_flash.h.

#define OB_AGC_TRIM_1 FLASH_OPTR_AGC_TRIM_0

Automatic Gain Control Trimming Value 1

Definition at line 308 of file stm32wbxx_hal_flash.h.

#define OB_AGC_TRIM_2 FLASH_OPTR_AGC_TRIM_1

Automatic Gain Control Trimming Value 2

Definition at line 309 of file stm32wbxx_hal_flash.h.

#define OB_AGC_TRIM_3 (FLASH_OPTR_AGC_TRIM_1 | FLASH_OPTR_AGC_TRIM_0)

Automatic Gain Control Trimming Value 3

Definition at line 310 of file stm32wbxx_hal_flash.h.

#define OB_AGC_TRIM_4 FLASH_OPTR_AGC_TRIM_2

Automatic Gain Control Trimming Value 4

Definition at line 311 of file stm32wbxx_hal_flash.h.

#define OB_AGC_TRIM_5 (FLASH_OPTR_AGC_TRIM_2 | FLASH_OPTR_AGC_TRIM_0)

Automatic Gain Control Trimming Value 5

Definition at line 312 of file stm32wbxx_hal_flash.h.

#define OB_AGC_TRIM_6 (FLASH_OPTR_AGC_TRIM_2 | FLASH_OPTR_AGC_TRIM_1)

Automatic Gain Control Trimming Value 6

Definition at line 313 of file stm32wbxx_hal_flash.h.

#define OB_AGC_TRIM_7 (FLASH_OPTR_AGC_TRIM_2 | FLASH_OPTR_AGC_TRIM_1 | FLASH_OPTR_AGC_TRIM_0)

Automatic Gain Control Trimming Value 7

Definition at line 314 of file stm32wbxx_hal_flash.h.

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STM32WB55xx HAL User Manual: FLASH Option Bytes User BOR Level

Defines
FLASH Option Bytes User BOR Level
FLASH Flags Definition

Defines

#define | OB_BOR_LEVEL_0 0x00000000U
#define | OB_BOR_LEVEL_1 FLASH_OPTR_BOR_LEV_0
#define | OB_BOR_LEVEL_2 FLASH_OPTR_BOR_LEV_1
#define | OB_BOR_LEVEL_3 (FLASH_OPTR_BOR_LEV_0 | FLASH_OPTR_BOR_LEV_1)
#define | OB_BOR_LEVEL_4 FLASH_OPTR_BOR_LEV_2

Define Documentation

#define OB_BOR_LEVEL_0 0x00000000U

Reset level threshold is around 1.7V

Definition at line 322 of file stm32wbxx_hal_flash.h.

#define OB_BOR_LEVEL_1 FLASH_OPTR_BOR_LEV_0

Reset level threshold is around 2.0V

Definition at line 323 of file stm32wbxx_hal_flash.h.

#define OB_BOR_LEVEL_2 FLASH_OPTR_BOR_LEV_1

Reset level threshold is around 2.2V

Definition at line 324 of file stm32wbxx_hal_flash.h.

#define OB_BOR_LEVEL_3 (FLASH_OPTR_BOR_LEV_0 | FLASH_OPTR_BOR_LEV_1)

Reset level threshold is around 2.5V

Definition at line 325 of file stm32wbxx_hal_flash.h.

#define OB_BOR_LEVEL_4 FLASH_OPTR_BOR_LEV_2

Reset level threshold is around 2.8V

Definition at line 326 of file stm32wbxx_hal_flash.h.

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STM32WB55xx HAL User Manual: FLASH Option Bytes User Reset On Stop

Defines
FLASH Option Bytes User Reset On Stop
FLASH Flags Definition

Defines

#define | OB_STOP_RST 0x00000000U
#define | OB_STOP_NORST FLASH_OPTR_nRST_STOP

Define Documentation

#define OB_STOP_NORST FLASH_OPTR_nRST_STOP

No reset generated when entering the stop mode

Definition at line 335 of file stm32wbxx_hal_flash.h.

#define OB_STOP_RST 0x00000000U

Reset generated when entering the stop mode

Definition at line 334 of file stm32wbxx_hal_flash.h.

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STM32WB55xx HAL User Manual: FLASH Option Bytes User Reset On Standby

Defines
FLASH Option Bytes User Reset On Standby
FLASH Flags Definition

Defines

#define | OB_STANDBY_RST 0x00000000U
#define | OB_STANDBY_NORST FLASH_OPTR_nRST_STDBY

Define Documentation

#define OB_STANDBY_NORST FLASH_OPTR_nRST_STDBY

No reset generated when entering the standby mode

Definition at line 344 of file stm32wbxx_hal_flash.h.

#define OB_STANDBY_RST 0x00000000U

Reset generated when entering the standby mode

Definition at line 343 of file stm32wbxx_hal_flash.h.

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STM32WB55xx HAL User Manual: FLASH Option Bytes User Reset On Shutdown

Defines
FLASH Option Bytes User Reset On Shutdown
FLASH Flags Definition

Defines

#define | OB_SHUTDOWN_RST 0x00000000U
#define | OB_SHUTDOWN_NORST FLASH_OPTR_nRST_SHDW

Define Documentation

#define OB_SHUTDOWN_NORST FLASH_OPTR_nRST_SHDW

No reset generated when entering the shutdown mode

Definition at line 353 of file stm32wbxx_hal_flash.h.

#define OB_SHUTDOWN_RST 0x00000000U

Reset generated when entering the shutdown mode

Definition at line 352 of file stm32wbxx_hal_flash.h.

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STM32WB55xx HAL User Manual: FLASH Option Bytes User IWDG Type

Defines
FLASH Option Bytes User IWDG Type
FLASH Flags Definition

Defines

#define | OB_IWDG_HW 0x00000000U
#define | OB_IWDG_SW FLASH_OPTR_IWDG_SW

Define Documentation

#define OB_IWDG_HW 0x00000000U

Hardware independent watchdog

Definition at line 361 of file stm32wbxx_hal_flash.h.

#define OB_IWDG_SW FLASH_OPTR_IWDG_SW

Software independent watchdog

Definition at line 362 of file stm32wbxx_hal_flash.h.

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STM32WB55xx HAL User Manual: FLASH Option Bytes User IWDG Mode On Stop

Defines
FLASH Option Bytes User IWDG Mode On Stop
FLASH Flags Definition

Defines

#define | OB_IWDG_STOP_FREEZE 0x00000000U
#define | OB_IWDG_STOP_RUN FLASH_OPTR_IWDG_STOP

Define Documentation

#define OB_IWDG_STOP_FREEZE 0x00000000U

Independent watchdog counter is frozen in Stop mode

Definition at line 370 of file stm32wbxx_hal_flash.h.

#define OB_IWDG_STOP_RUN FLASH_OPTR_IWDG_STOP

Independent watchdog counter is running in Stop mode

Definition at line 371 of file stm32wbxx_hal_flash.h.

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STM32WB55xx HAL User Manual: FLASH Option Bytes User IWDG Mode On Standby

Defines
FLASH Option Bytes User IWDG Mode On Standby
FLASH Flags Definition

Defines

#define | OB_IWDG_STDBY_FREEZE 0x00000000U
#define | OB_IWDG_STDBY_RUN FLASH_OPTR_IWDG_STDBY

Define Documentation

#define OB_IWDG_STDBY_FREEZE 0x00000000U

Independent watchdog counter is frozen in Standby mode

Definition at line 379 of file stm32wbxx_hal_flash.h.

#define OB_IWDG_STDBY_RUN FLASH_OPTR_IWDG_STDBY

Independent watchdog counter is running in Standby mode

Definition at line 380 of file stm32wbxx_hal_flash.h.

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STM32WB55xx HAL User Manual: FLASH Option Bytes User WWDG Type

Defines
FLASH Option Bytes User WWDG Type
FLASH Flags Definition

Defines

#define | OB_WWDG_HW 0x00000000U
#define | OB_WWDG_SW FLASH_OPTR_WWDG_SW

Define Documentation

#define OB_WWDG_HW 0x00000000U

Hardware window watchdog

Definition at line 388 of file stm32wbxx_hal_flash.h.

#define OB_WWDG_SW FLASH_OPTR_WWDG_SW

Software window watchdog

Definition at line 389 of file stm32wbxx_hal_flash.h.

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STM32WB55xx HAL User Manual: FLASH Option Bytes SRAM2 parity check

Defines
FLASH Option Bytes SRAM2 parity check
FLASH Flags Definition

Defines

#define | OB_SRAM2_PARITY_ENABLE 0x00000000U
#define | OB_SRAM2_PARITY_DISABLE FLASH_OPTR_SRAM2PE

Define Documentation

#define OB_SRAM2_PARITY_DISABLE FLASH_OPTR_SRAM2PE

SRAM2 parity check disable

Definition at line 398 of file stm32wbxx_hal_flash.h.

#define OB_SRAM2_PARITY_ENABLE 0x00000000U

SRAM2 parity check enable

Definition at line 397 of file stm32wbxx_hal_flash.h.

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STM32WB55xx HAL User Manual: FLASH Option Bytes SRAM2 erase when system reset

Defines
FLASH Option Bytes SRAM2 erase when system reset
FLASH Flags Definition

Defines

#define | OB_SRAM2_RST_ERASE 0x00000000U
#define | OB_SRAM2_RST_NOT_ERASE FLASH_OPTR_SRAM2RST

Define Documentation

#define OB_SRAM2_RST_ERASE 0x00000000U

SRAM2 erased when a system reset

Definition at line 406 of file stm32wbxx_hal_flash.h.

#define OB_SRAM2_RST_NOT_ERASE FLASH_OPTR_SRAM2RST

SRAM2 is not erased when a system reset

Definition at line 407 of file stm32wbxx_hal_flash.h.

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STM32WB55xx HAL User Manual: FLASH Option Bytes User BOOT1 Type

Defines
FLASH Option Bytes User BOOT1 Type
FLASH Flags Definition

Defines

#define | OB_BOOT1_SRAM 0x00000000U
#define | OB_BOOT1_SYSTEM FLASH_OPTR_nBOOT1

Define Documentation

#define OB_BOOT1_SRAM 0x00000000U

Embedded SRAM is selected as boot space (if BOOT0=1)

Definition at line 415 of file stm32wbxx_hal_flash.h.

#define OB_BOOT1_SYSTEM FLASH_OPTR_nBOOT1

System memory is selected as boot space (if BOOT0=1)

Definition at line 416 of file stm32wbxx_hal_flash.h.

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STM32WB55xx HAL User Manual: FLASH Option Bytes User Software BOOT0

Defines
FLASH Option Bytes User Software BOOT0
FLASH Flags Definition

Defines

#define | OB_BOOT0_FROM_OB 0x00000000U
#define | OB_BOOT0_FROM_PIN FLASH_OPTR_nSWBOOT0

Define Documentation

#define OB_BOOT0_FROM_OB 0x00000000U

BOOT0 taken from the option bit nBOOT0

Definition at line 424 of file stm32wbxx_hal_flash.h.

#define OB_BOOT0_FROM_PIN FLASH_OPTR_nSWBOOT0

BOOT0 taken from PH3/BOOT0 pin

Definition at line 425 of file stm32wbxx_hal_flash.h.

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STM32WB55xx HAL User Manual: FLASH Option Bytes User nBOOT0 option bit

Defines
FLASH Option Bytes User nBOOT0 option bit
FLASH Flags Definition

Defines

#define | OB_BOOT0_RESET 0x00000000U
#define | OB_BOOT0_SET FLASH_OPTR_nBOOT0

Define Documentation

#define OB_BOOT0_RESET 0x00000000U

nBOOT0 = 0

Definition at line 433 of file stm32wbxx_hal_flash.h.

#define OB_BOOT0_SET FLASH_OPTR_nBOOT0

nBOOT0 = 1

Definition at line 434 of file stm32wbxx_hal_flash.h.

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STM32WB55xx HAL User Manual: FLASH PCROP ZONE

Defines
FLASH PCROP ZONE
FLASH Flags Definition

Defines

#define | OB_PCROP_ZONE_A 0x00000001U
#define | OB_PCROP_ZONE_B 0x00000002U

Define Documentation

#define OB_PCROP_ZONE_A 0x00000001U

PCROP Zone A

Definition at line 442 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_OB_PCROP1AConfig(), HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

#define OB_PCROP_ZONE_B 0x00000002U

PCROP Zone B

Definition at line 443 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

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STM32WB55xx HAL User Manual: FLASH Option Bytes PCROP On RDP Level Type

Defines
FLASH Option Bytes PCROP On RDP Level Type
FLASH Flags Definition

Defines

#define | OB_PCROP_RDP_NOT_ERASE 0x00000000U
#define | OB_PCROP_RDP_ERASE FLASH_PCROP1AER_PCROP_RDP

Define Documentation

#define OB_PCROP_RDP_ERASE FLASH_PCROP1AER_PCROP_RDP

PCROP area is erased when the RDP level is decreased from Level 1 to Level 0 (full mass erase)

Definition at line 453 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_OB_PCROP1AConfig(), and HAL_FLASHEx_OBProgram().

#define OB_PCROP_RDP_NOT_ERASE 0x00000000U

PCROP area is not erased when the RDP level is decreased from Level 1 to Level 0

Definition at line 451 of file stm32wbxx_hal_flash.h.

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STM32WB55xx HAL User Manual: Option Bytes FLASH Secure mode

Defines
Option Bytes FLASH Secure mode
FLASH Flags Definition

Defines

#define | SYSTEM_NOT_IN_SECURE_MODE 0x00000000U
#define | SYSTEM_IN_SECURE_MODE FLASH_OPTR_ESE

Define Documentation

#define SYSTEM_IN_SECURE_MODE FLASH_OPTR_ESE

Secure mode : Security enabled

Definition at line 463 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_OB_SecureConfig().

#define SYSTEM_NOT_IN_SECURE_MODE 0x00000000U

Unsecure mode: Security disabled

Definition at line 462 of file stm32wbxx_hal_flash.h.

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STM32WB55xx HAL User Manual: CPU2 Option Bytes Reset Boot Vector

Defines
CPU2 Option Bytes Reset Boot Vector
FLASH Flags Definition

Defines

#define | OB_C2_BOOT_FROM_SRAM 0x00000000U
#define | OB_C2_BOOT_FROM_FLASH FLASH_SRRVR_C2OPT

Define Documentation

#define OB_C2_BOOT_FROM_FLASH FLASH_SRRVR_C2OPT

CPU2 boot from Flash

Definition at line 472 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_OB_GetC2BootResetConfig(), and FLASH_OB_SecureConfig().

#define OB_C2_BOOT_FROM_SRAM 0x00000000U

CPU2 boot from Sram

Definition at line 471 of file stm32wbxx_hal_flash.h.

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STM32WB55xx HAL User Manual: FLASH Flags Definition

Modules | Defines
FLASH Flags Definition
FLASH Exported Constants

Modules

FLASH Interrupts Definition

FLASH Interrupt definition.

FLASH Error
FLASH Erase Type
FLASH Program Type
FLASH Option Bytes Type
FLASH WRP Area
FLASH Option Bytes Read Protection
FLASH Option Bytes User Type
FLASH Option Bytes Automatic Gain Control Trimming
FLASH Option Bytes User BOR Level
FLASH Option Bytes User Reset On Stop
FLASH Option Bytes User Reset On Standby
FLASH Option Bytes User Reset On Shutdown
FLASH Option Bytes User IWDG Type
FLASH Option Bytes User IWDG Mode On Stop
FLASH Option Bytes User IWDG Mode On Standby
FLASH Option Bytes User WWDG Type
FLASH Option Bytes SRAM2 parity check
FLASH Option Bytes SRAM2 erase when system reset
FLASH Option Bytes User BOOT1 Type
FLASH Option Bytes User Software BOOT0
FLASH Option Bytes User nBOOT0 option bit
FLASH PCROP ZONE
FLASH Option Bytes PCROP On RDP Level Type
Option Bytes FLASH Secure mode
CPU2 Option Bytes Reset Boot Vector

Defines

#define | FLASH_FLAG_EOP FLASH_SR_EOP
#define | FLASH_FLAG_OPERR FLASH_SR_OPERR
#define | FLASH_FLAG_PROGERR FLASH_SR_PROGERR
#define | FLASH_FLAG_WRPERR FLASH_SR_WRPERR
#define | FLASH_FLAG_PGAERR FLASH_SR_PGAERR
#define | FLASH_FLAG_SIZERR FLASH_SR_SIZERR
#define | FLASH_FLAG_PGSERR FLASH_SR_PGSERR
#define | FLASH_FLAG_MISERR FLASH_SR_MISERR
#define | FLASH_FLAG_FASTERR FLASH_SR_FASTERR
#define | FLASH_FLAG_OPTNV FLASH_SR_OPTNV
#define | FLASH_FLAG_RDERR FLASH_SR_RDERR
#define | FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR
#define | FLASH_FLAG_BSY FLASH_SR_BSY
#define | FLASH_FLAG_CFGBSY FLASH_SR_CFGBSY
#define | FLASH_FLAG_PESD FLASH_SR_PESD
#define | FLASH_FLAG_ECCC FLASH_ECCR_ECCC
#define | FLASH_FLAG_ECCD FLASH_ECCR_ECCD
#define | FLASH_FLAG_SR_ERRORS
#define | FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)
#define | FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_ECCR_ERRORS)

Define Documentation

#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_ECCR_ERRORS)

Definition at line 189 of file stm32wbxx_hal_flash.h.

#define FLASH_FLAG_BSY FLASH_SR_BSY

FLASH Busy flag

Definition at line 176 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_Program_Fast(), and FLASH_WaitForLastOperation().

#define FLASH_FLAG_CFGBSY FLASH_SR_CFGBSY

FLASH Programming/erase configuration busy

Definition at line 177 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation().

#define FLASH_FLAG_ECCC FLASH_ECCR_ECCC

FLASH ECC correction

Definition at line 179 of file stm32wbxx_hal_flash.h.

#define FLASH_FLAG_ECCD FLASH_ECCR_ECCD

FLASH ECC detection

Definition at line 180 of file stm32wbxx_hal_flash.h.

#define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)

Definition at line 187 of file stm32wbxx_hal_flash.h.

#define FLASH_FLAG_EOP FLASH_SR_EOP

FLASH End of operation flag

Definition at line 164 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

#define FLASH_FLAG_FASTERR FLASH_SR_FASTERR

FLASH Fast programming error flag

Definition at line 172 of file stm32wbxx_hal_flash.h.

#define FLASH_FLAG_MISERR FLASH_SR_MISERR

FLASH Fast programming data miss error flag

Definition at line 171 of file stm32wbxx_hal_flash.h.

#define FLASH_FLAG_OPERR FLASH_SR_OPERR

FLASH Operation error flag

Definition at line 165 of file stm32wbxx_hal_flash.h.

#define FLASH_FLAG_OPTNV FLASH_SR_OPTNV

FLASH User Option OPTVAL indication

Definition at line 173 of file stm32wbxx_hal_flash.h.

#define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR

FLASH Option validity error flag

Definition at line 175 of file stm32wbxx_hal_flash.h.

#define FLASH_FLAG_PESD FLASH_SR_PESD

FLASH Programming/erase operation suspended

Definition at line 178 of file stm32wbxx_hal_flash.h.

#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR

FLASH Programming alignment error flag

Definition at line 168 of file stm32wbxx_hal_flash.h.

#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR

FLASH Programming sequence error flag

Definition at line 170 of file stm32wbxx_hal_flash.h.

#define FLASH_FLAG_PROGERR FLASH_SR_PROGERR

FLASH Programming error flag

Definition at line 166 of file stm32wbxx_hal_flash.h.

#define FLASH_FLAG_RDERR FLASH_SR_RDERR

FLASH PCROP read error flag

Definition at line 174 of file stm32wbxx_hal_flash.h.

#define FLASH_FLAG_SIZERR FLASH_SR_SIZERR

FLASH Size error flag

Definition at line 169 of file stm32wbxx_hal_flash.h.

#define FLASH_FLAG_SR_ERRORS
Value:
(FLASH_FLAG_OPERR   | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \
                                         FLASH_FLAG_PGAERR  | FLASH_FLAG_SIZERR  | FLASH_FLAG_PGSERR | \
                                         FLASH_FLAG_MISERR  | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR  | \
                                         FLASH_FLAG_OPTVERR)

All SR error flags

Definition at line 182 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR

FLASH Write protection error flag

Definition at line 167 of file stm32wbxx_hal_flash.h.

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STM32WB55xx HAL User Manual: RAM2A address range in secure mode

Defines
RAM2A address range in secure mode
FLASH Exported Constants

Defines

#define | SRAM2A_START_SECURE_ADDR_0 (SRAM2A_BASE + 0x0000U) /* When in secure mode (SRAM2A_BASE + 0x0000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_1 (SRAM2A_BASE + 0x0400U) /* When in secure mode (SRAM2A_BASE + 0x0400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_2 (SRAM2A_BASE + 0x0800U) /* When in secure mode (SRAM2A_BASE + 0x0800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_3 (SRAM2A_BASE + 0x0C00U) /* When in secure mode (SRAM2A_BASE + 0x0C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_4 (SRAM2A_BASE + 0x1000U) /* When in secure mode (SRAM2A_BASE + 0x1000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_5 (SRAM2A_BASE + 0x1400U) /* When in secure mode (SRAM2A_BASE + 0x1400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_6 (SRAM2A_BASE + 0x1800U) /* When in secure mode (SRAM2A_BASE + 0x1800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_7 (SRAM2A_BASE + 0x1C00U) /* When in secure mode (SRAM2A_BASE + 0x1C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_8 (SRAM2A_BASE + 0x2000U) /* When in secure mode (SRAM2A_BASE + 0x2000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_9 (SRAM2A_BASE + 0x2400U) /* When in secure mode (SRAM2A_BASE + 0x2400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_10 (SRAM2A_BASE + 0x2800U) /* When in secure mode (SRAM2A_BASE + 0x2800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_11 (SRAM2A_BASE + 0x2C00U) /* When in secure mode (SRAM2A_BASE + 0x2C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_12 (SRAM2A_BASE + 0x3000U) /* When in secure mode (SRAM2A_BASE + 0x3000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_13 (SRAM2A_BASE + 0x3400U) /* When in secure mode (SRAM2A_BASE + 0x3400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_14 (SRAM2A_BASE + 0x3800U) /* When in secure mode (SRAM2A_BASE + 0x3800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_15 (SRAM2A_BASE + 0x3C00U) /* When in secure mode (SRAM2A_BASE + 0x3C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_16 (SRAM2A_BASE + 0x4000U) /* When in secure mode (SRAM2A_BASE + 0x4000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_17 (SRAM2A_BASE + 0x4400U) /* When in secure mode (SRAM2A_BASE + 0x4400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_18 (SRAM2A_BASE + 0x4800U) /* When in secure mode (SRAM2A_BASE + 0x4800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_19 (SRAM2A_BASE + 0x4C00U) /* When in secure mode (SRAM2A_BASE + 0x4C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_20 (SRAM2A_BASE + 0x5000U) /* When in secure mode (SRAM2A_BASE + 0x5000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_21 (SRAM2A_BASE + 0x5400U) /* When in secure mode (SRAM2A_BASE + 0x5400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_22 (SRAM2A_BASE + 0x5800U) /* When in secure mode (SRAM2A_BASE + 0x5800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_23 (SRAM2A_BASE + 0x5C00U) /* When in secure mode (SRAM2A_BASE + 0x5C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_24 (SRAM2A_BASE + 0x6000U) /* When in secure mode (SRAM2A_BASE + 0x6000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_25 (SRAM2A_BASE + 0x6400U) /* When in secure mode (SRAM2A_BASE + 0x6400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_26 (SRAM2A_BASE + 0x6800U) /* When in secure mode (SRAM2A_BASE + 0x6800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_27 (SRAM2A_BASE + 0x6C00U) /* When in secure mode (SRAM2A_BASE + 0x6C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_28 (SRAM2A_BASE + 0x7000U) /* When in secure mode (SRAM2A_BASE + 0x7000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_29 (SRAM2A_BASE + 0x7400U) /* When in secure mode (SRAM2A_BASE + 0x7400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_30 (SRAM2A_BASE + 0x7800U) /* When in secure mode (SRAM2A_BASE + 0x7800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_31 (SRAM2A_BASE + 0x7C00U) /* When in secure mode (SRAM2A_BASE + 0x7C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_FULL_UNSECURE (SRAM2A_BASE + 0x8000U) /* The RAM2A is accessible to M0 Plus and M4 */

Define Documentation

#define SRAM2A_FULL_UNSECURE (SRAM2A_BASE + 0x8000U) /* The RAM2A is accessible to M0 Plus and M4 */

Definition at line 516 of file stm32wbxx_hal_flash.h.

#define SRAM2A_START_SECURE_ADDR_0 (SRAM2A_BASE + 0x0000U) /* When in secure mode (SRAM2A_BASE + 0x0000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 484 of file stm32wbxx_hal_flash.h.

#define SRAM2A_START_SECURE_ADDR_1 (SRAM2A_BASE + 0x0400U) /* When in secure mode (SRAM2A_BASE + 0x0400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 485 of file stm32wbxx_hal_flash.h.

#define SRAM2A_START_SECURE_ADDR_10 (SRAM2A_BASE + 0x2800U) /* When in secure mode (SRAM2A_BASE + 0x2800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 494 of file stm32wbxx_hal_flash.h.

#define SRAM2A_START_SECURE_ADDR_11 (SRAM2A_BASE + 0x2C00U) /* When in secure mode (SRAM2A_BASE + 0x2C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 495 of file stm32wbxx_hal_flash.h.

#define SRAM2A_START_SECURE_ADDR_12 (SRAM2A_BASE + 0x3000U) /* When in secure mode (SRAM2A_BASE + 0x3000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 496 of file stm32wbxx_hal_flash.h.

#define SRAM2A_START_SECURE_ADDR_13 (SRAM2A_BASE + 0x3400U) /* When in secure mode (SRAM2A_BASE + 0x3400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 497 of file stm32wbxx_hal_flash.h.

#define SRAM2A_START_SECURE_ADDR_14 (SRAM2A_BASE + 0x3800U) /* When in secure mode (SRAM2A_BASE + 0x3800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 498 of file stm32wbxx_hal_flash.h.

#define SRAM2A_START_SECURE_ADDR_15 (SRAM2A_BASE + 0x3C00U) /* When in secure mode (SRAM2A_BASE + 0x3C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 499 of file stm32wbxx_hal_flash.h.

#define SRAM2A_START_SECURE_ADDR_16 (SRAM2A_BASE + 0x4000U) /* When in secure mode (SRAM2A_BASE + 0x4000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 500 of file stm32wbxx_hal_flash.h.

#define SRAM2A_START_SECURE_ADDR_17 (SRAM2A_BASE + 0x4400U) /* When in secure mode (SRAM2A_BASE + 0x4400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 501 of file stm32wbxx_hal_flash.h.

#define SRAM2A_START_SECURE_ADDR_18 (SRAM2A_BASE + 0x4800U) /* When in secure mode (SRAM2A_BASE + 0x4800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 502 of file stm32wbxx_hal_flash.h.

#define SRAM2A_START_SECURE_ADDR_19 (SRAM2A_BASE + 0x4C00U) /* When in secure mode (SRAM2A_BASE + 0x4C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 503 of file stm32wbxx_hal_flash.h.

#define SRAM2A_START_SECURE_ADDR_2 (SRAM2A_BASE + 0x0800U) /* When in secure mode (SRAM2A_BASE + 0x0800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 486 of file stm32wbxx_hal_flash.h.

#define SRAM2A_START_SECURE_ADDR_20 (SRAM2A_BASE + 0x5000U) /* When in secure mode (SRAM2A_BASE + 0x5000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 504 of file stm32wbxx_hal_flash.h.

#define SRAM2A_START_SECURE_ADDR_21 (SRAM2A_BASE + 0x5400U) /* When in secure mode (SRAM2A_BASE + 0x5400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 505 of file stm32wbxx_hal_flash.h.

#define SRAM2A_START_SECURE_ADDR_22 (SRAM2A_BASE + 0x5800U) /* When in secure mode (SRAM2A_BASE + 0x5800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 506 of file stm32wbxx_hal_flash.h.

#define SRAM2A_START_SECURE_ADDR_23 (SRAM2A_BASE + 0x5C00U) /* When in secure mode (SRAM2A_BASE + 0x5C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 507 of file stm32wbxx_hal_flash.h.

#define SRAM2A_START_SECURE_ADDR_24 (SRAM2A_BASE + 0x6000U) /* When in secure mode (SRAM2A_BASE + 0x6000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 508 of file stm32wbxx_hal_flash.h.

#define SRAM2A_START_SECURE_ADDR_25 (SRAM2A_BASE + 0x6400U) /* When in secure mode (SRAM2A_BASE + 0x6400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 509 of file stm32wbxx_hal_flash.h.

#define SRAM2A_START_SECURE_ADDR_26 (SRAM2A_BASE + 0x6800U) /* When in secure mode (SRAM2A_BASE + 0x6800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 510 of file stm32wbxx_hal_flash.h.

#define SRAM2A_START_SECURE_ADDR_27 (SRAM2A_BASE + 0x6C00U) /* When in secure mode (SRAM2A_BASE + 0x6C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 511 of file stm32wbxx_hal_flash.h.

#define SRAM2A_START_SECURE_ADDR_28 (SRAM2A_BASE + 0x7000U) /* When in secure mode (SRAM2A_BASE + 0x7000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 512 of file stm32wbxx_hal_flash.h.

#define SRAM2A_START_SECURE_ADDR_29 (SRAM2A_BASE + 0x7400U) /* When in secure mode (SRAM2A_BASE + 0x7400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 513 of file stm32wbxx_hal_flash.h.

#define SRAM2A_START_SECURE_ADDR_3 (SRAM2A_BASE + 0x0C00U) /* When in secure mode (SRAM2A_BASE + 0x0C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 487 of file stm32wbxx_hal_flash.h.

#define SRAM2A_START_SECURE_ADDR_30 (SRAM2A_BASE + 0x7800U) /* When in secure mode (SRAM2A_BASE + 0x7800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 514 of file stm32wbxx_hal_flash.h.

#define SRAM2A_START_SECURE_ADDR_31 (SRAM2A_BASE + 0x7C00U) /* When in secure mode (SRAM2A_BASE + 0x7C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 515 of file stm32wbxx_hal_flash.h.

#define SRAM2A_START_SECURE_ADDR_4 (SRAM2A_BASE + 0x1000U) /* When in secure mode (SRAM2A_BASE + 0x1000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 488 of file stm32wbxx_hal_flash.h.

#define SRAM2A_START_SECURE_ADDR_5 (SRAM2A_BASE + 0x1400U) /* When in secure mode (SRAM2A_BASE + 0x1400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 489 of file stm32wbxx_hal_flash.h.

#define SRAM2A_START_SECURE_ADDR_6 (SRAM2A_BASE + 0x1800U) /* When in secure mode (SRAM2A_BASE + 0x1800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 490 of file stm32wbxx_hal_flash.h.

#define SRAM2A_START_SECURE_ADDR_7 (SRAM2A_BASE + 0x1C00U) /* When in secure mode (SRAM2A_BASE + 0x1C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 491 of file stm32wbxx_hal_flash.h.

#define SRAM2A_START_SECURE_ADDR_8 (SRAM2A_BASE + 0x2000U) /* When in secure mode (SRAM2A_BASE + 0x2000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 492 of file stm32wbxx_hal_flash.h.

#define SRAM2A_START_SECURE_ADDR_9 (SRAM2A_BASE + 0x2400U) /* When in secure mode (SRAM2A_BASE + 0x2400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 493 of file stm32wbxx_hal_flash.h.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RAM2B address range in secure mode

Defines
RAM2B address range in secure mode
FLASH Exported Constants

Defines

#define | SRAM2B_START_SECURE_ADDR_0 (SRAM2B_BASE + 0x0000U) /* When in secure mode (SRAM2B_BASE + 0x0000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_1 (SRAM2B_BASE + 0x0400U) /* When in secure mode (SRAM2B_BASE + 0x0400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_2 (SRAM2B_BASE + 0x0800U) /* When in secure mode (SRAM2B_BASE + 0x0800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_3 (SRAM2B_BASE + 0x0C00U) /* When in secure mode (SRAM2B_BASE + 0x0C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_4 (SRAM2B_BASE + 0x1000U) /* When in secure mode (SRAM2B_BASE + 0x1000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_5 (SRAM2B_BASE + 0x1400U) /* When in secure mode (SRAM2B_BASE + 0x1400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_6 (SRAM2B_BASE + 0x1800U) /* When in secure mode (SRAM2B_BASE + 0x1800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_7 (SRAM2B_BASE + 0x1C00U) /* When in secure mode (SRAM2B_BASE + 0x1C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_8 (SRAM2B_BASE + 0x2000U) /* When in secure mode (SRAM2B_BASE + 0x2000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_9 (SRAM2B_BASE + 0x2400U) /* When in secure mode (SRAM2B_BASE + 0x2400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_10 (SRAM2B_BASE + 0x2800U) /* When in secure mode (SRAM2B_BASE + 0x2800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_11 (SRAM2B_BASE + 0x2C00U) /* When in secure mode (SRAM2B_BASE + 0x2C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_12 (SRAM2B_BASE + 0x3000U) /* When in secure mode (SRAM2B_BASE + 0x3000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_13 (SRAM2B_BASE + 0x3400U) /* When in secure mode (SRAM2B_BASE + 0x3400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_14 (SRAM2B_BASE + 0x3800U) /* When in secure mode (SRAM2B_BASE + 0x3800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_15 (SRAM2B_BASE + 0x3C00U) /* When in secure mode (SRAM2B_BASE + 0x3C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_16 (SRAM2B_BASE + 0x4000U) /* When in secure mode (SRAM2B_BASE + 0x4000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_17 (SRAM2B_BASE + 0x4400U) /* When in secure mode (SRAM2B_BASE + 0x4400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_18 (SRAM2B_BASE + 0x4800U) /* When in secure mode (SRAM2B_BASE + 0x4800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_19 (SRAM2B_BASE + 0x4C00U) /* When in secure mode (SRAM2B_BASE + 0x4C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_20 (SRAM2B_BASE + 0x5000U) /* When in secure mode (SRAM2B_BASE + 0x5000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_21 (SRAM2B_BASE + 0x5400U) /* When in secure mode (SRAM2B_BASE + 0x5400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_22 (SRAM2B_BASE + 0x5800U) /* When in secure mode (SRAM2B_BASE + 0x5800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_23 (SRAM2B_BASE + 0x5C00U) /* When in secure mode (SRAM2B_BASE + 0x5C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_24 (SRAM2B_BASE + 0x6000U) /* When in secure mode (SRAM2B_BASE + 0x6000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_25 (SRAM2B_BASE + 0x6400U) /* When in secure mode (SRAM2B_BASE + 0x6400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_26 (SRAM2B_BASE + 0x6800U) /* When in secure mode (SRAM2B_BASE + 0x6800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_27 (SRAM2B_BASE + 0x6C00U) /* When in secure mode (SRAM2B_BASE + 0x6C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_28 (SRAM2B_BASE + 0x7000U) /* When in secure mode (SRAM2B_BASE + 0x7000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_29 (SRAM2B_BASE + 0x7400U) /* When in secure mode (SRAM2B_BASE + 0x7400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_30 (SRAM2B_BASE + 0x7800U) /* When in secure mode (SRAM2B_BASE + 0x7800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_31 (SRAM2B_BASE + 0x7C00U) /* When in secure mode (SRAM2B_BASE + 0x7C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_FULL_UNSECURE (SRAM2B_BASE + 0x8000U) /* The RAM2B is accessible to M0 Plus and M4 */

Define Documentation

#define SRAM2B_FULL_UNSECURE (SRAM2B_BASE + 0x8000U) /* The RAM2B is accessible to M0 Plus and M4 */

Definition at line 558 of file stm32wbxx_hal_flash.h.

#define SRAM2B_START_SECURE_ADDR_0 (SRAM2B_BASE + 0x0000U) /* When in secure mode (SRAM2B_BASE + 0x0000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 526 of file stm32wbxx_hal_flash.h.

#define SRAM2B_START_SECURE_ADDR_1 (SRAM2B_BASE + 0x0400U) /* When in secure mode (SRAM2B_BASE + 0x0400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 527 of file stm32wbxx_hal_flash.h.

#define SRAM2B_START_SECURE_ADDR_10 (SRAM2B_BASE + 0x2800U) /* When in secure mode (SRAM2B_BASE + 0x2800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 536 of file stm32wbxx_hal_flash.h.

#define SRAM2B_START_SECURE_ADDR_11 (SRAM2B_BASE + 0x2C00U) /* When in secure mode (SRAM2B_BASE + 0x2C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 537 of file stm32wbxx_hal_flash.h.

#define SRAM2B_START_SECURE_ADDR_12 (SRAM2B_BASE + 0x3000U) /* When in secure mode (SRAM2B_BASE + 0x3000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 538 of file stm32wbxx_hal_flash.h.

#define SRAM2B_START_SECURE_ADDR_13 (SRAM2B_BASE + 0x3400U) /* When in secure mode (SRAM2B_BASE + 0x3400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 539 of file stm32wbxx_hal_flash.h.

#define SRAM2B_START_SECURE_ADDR_14 (SRAM2B_BASE + 0x3800U) /* When in secure mode (SRAM2B_BASE + 0x3800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 540 of file stm32wbxx_hal_flash.h.

#define SRAM2B_START_SECURE_ADDR_15 (SRAM2B_BASE + 0x3C00U) /* When in secure mode (SRAM2B_BASE + 0x3C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 541 of file stm32wbxx_hal_flash.h.

#define SRAM2B_START_SECURE_ADDR_16 (SRAM2B_BASE + 0x4000U) /* When in secure mode (SRAM2B_BASE + 0x4000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 542 of file stm32wbxx_hal_flash.h.

#define SRAM2B_START_SECURE_ADDR_17 (SRAM2B_BASE + 0x4400U) /* When in secure mode (SRAM2B_BASE + 0x4400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 543 of file stm32wbxx_hal_flash.h.

#define SRAM2B_START_SECURE_ADDR_18 (SRAM2B_BASE + 0x4800U) /* When in secure mode (SRAM2B_BASE + 0x4800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 544 of file stm32wbxx_hal_flash.h.

#define SRAM2B_START_SECURE_ADDR_19 (SRAM2B_BASE + 0x4C00U) /* When in secure mode (SRAM2B_BASE + 0x4C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 545 of file stm32wbxx_hal_flash.h.

#define SRAM2B_START_SECURE_ADDR_2 (SRAM2B_BASE + 0x0800U) /* When in secure mode (SRAM2B_BASE + 0x0800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 528 of file stm32wbxx_hal_flash.h.

#define SRAM2B_START_SECURE_ADDR_20 (SRAM2B_BASE + 0x5000U) /* When in secure mode (SRAM2B_BASE + 0x5000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 546 of file stm32wbxx_hal_flash.h.

#define SRAM2B_START_SECURE_ADDR_21 (SRAM2B_BASE + 0x5400U) /* When in secure mode (SRAM2B_BASE + 0x5400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 547 of file stm32wbxx_hal_flash.h.

#define SRAM2B_START_SECURE_ADDR_22 (SRAM2B_BASE + 0x5800U) /* When in secure mode (SRAM2B_BASE + 0x5800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 548 of file stm32wbxx_hal_flash.h.

#define SRAM2B_START_SECURE_ADDR_23 (SRAM2B_BASE + 0x5C00U) /* When in secure mode (SRAM2B_BASE + 0x5C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 549 of file stm32wbxx_hal_flash.h.

#define SRAM2B_START_SECURE_ADDR_24 (SRAM2B_BASE + 0x6000U) /* When in secure mode (SRAM2B_BASE + 0x6000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 550 of file stm32wbxx_hal_flash.h.

#define SRAM2B_START_SECURE_ADDR_25 (SRAM2B_BASE + 0x6400U) /* When in secure mode (SRAM2B_BASE + 0x6400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 551 of file stm32wbxx_hal_flash.h.

#define SRAM2B_START_SECURE_ADDR_26 (SRAM2B_BASE + 0x6800U) /* When in secure mode (SRAM2B_BASE + 0x6800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 552 of file stm32wbxx_hal_flash.h.

#define SRAM2B_START_SECURE_ADDR_27 (SRAM2B_BASE + 0x6C00U) /* When in secure mode (SRAM2B_BASE + 0x6C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 553 of file stm32wbxx_hal_flash.h.

#define SRAM2B_START_SECURE_ADDR_28 (SRAM2B_BASE + 0x7000U) /* When in secure mode (SRAM2B_BASE + 0x7000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 554 of file stm32wbxx_hal_flash.h.

#define SRAM2B_START_SECURE_ADDR_29 (SRAM2B_BASE + 0x7400U) /* When in secure mode (SRAM2B_BASE + 0x7400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 555 of file stm32wbxx_hal_flash.h.

#define SRAM2B_START_SECURE_ADDR_3 (SRAM2B_BASE + 0x0C00U) /* When in secure mode (SRAM2B_BASE + 0x0C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 529 of file stm32wbxx_hal_flash.h.

#define SRAM2B_START_SECURE_ADDR_30 (SRAM2B_BASE + 0x7800U) /* When in secure mode (SRAM2B_BASE + 0x7800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 556 of file stm32wbxx_hal_flash.h.

#define SRAM2B_START_SECURE_ADDR_31 (SRAM2B_BASE + 0x7C00U) /* When in secure mode (SRAM2B_BASE + 0x7C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 557 of file stm32wbxx_hal_flash.h.

#define SRAM2B_START_SECURE_ADDR_4 (SRAM2B_BASE + 0x1000U) /* When in secure mode (SRAM2B_BASE + 0x1000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 530 of file stm32wbxx_hal_flash.h.

#define SRAM2B_START_SECURE_ADDR_5 (SRAM2B_BASE + 0x1400U) /* When in secure mode (SRAM2B_BASE + 0x1400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 531 of file stm32wbxx_hal_flash.h.

#define SRAM2B_START_SECURE_ADDR_6 (SRAM2B_BASE + 0x1800U) /* When in secure mode (SRAM2B_BASE + 0x1800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 532 of file stm32wbxx_hal_flash.h.

#define SRAM2B_START_SECURE_ADDR_7 (SRAM2B_BASE + 0x1C00U) /* When in secure mode (SRAM2B_BASE + 0x1C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 533 of file stm32wbxx_hal_flash.h.

#define SRAM2B_START_SECURE_ADDR_8 (SRAM2B_BASE + 0x2000U) /* When in secure mode (SRAM2B_BASE + 0x2000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 534 of file stm32wbxx_hal_flash.h.

#define SRAM2B_START_SECURE_ADDR_9 (SRAM2B_BASE + 0x2400U) /* When in secure mode (SRAM2B_BASE + 0x2400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */

Definition at line 535 of file stm32wbxx_hal_flash.h.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FLASH Exported Macros

Defines
FLASH Exported Macros
FLASH

macros to control FLASH features More...

Defines

#define | __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__))
Set the FLASH Latency.
#define | __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)
Get the FLASH Latency.
#define | __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
Enable the FLASH prefetch buffer.
#define | __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
Disable the FLASH prefetch buffer.
#define | __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN)
Enable the FLASH instruction cache.
#define | __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN)
Disable the FLASH instruction cache.
#define | __HAL_FLASH_DATA_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_DCEN)
Enable the FLASH data cache.
#define | __HAL_FLASH_DATA_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN)
Disable the FLASH data cache.
#define | __HAL_FLASH_INSTRUCTION_CACHE_RESET()
Reset the FLASH instruction Cache.
#define | __HAL_FLASH_DATA_CACHE_RESET()
Reset the FLASH data Cache.

Detailed Description

macros to control FLASH features

Define Documentation

#define __HAL_FLASH_DATA_CACHE_DISABLE ( ) CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN)

Disable the FLASH data cache.

Return values:
none

Definition at line 631 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_FlushCaches(), and HAL_Init().

#define __HAL_FLASH_DATA_CACHE_ENABLE ( ) SET_BIT(FLASH->ACR, FLASH_ACR_DCEN)

Enable the FLASH data cache.

Return values:
none

Definition at line 625 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_FlushCaches().

#define __HAL_FLASH_DATA_CACHE_RESET ( )
Value:
do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);   \
                                                     CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \
                                                   } while (0)

Reset the FLASH data Cache.

Note:
This function must be used only when the data Cache is disabled.
Return values:
None

Definition at line 647 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_FlushCaches().

#define __HAL_FLASH_GET_LATENCY ( ) READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)

Get the FLASH Latency.

Return values:
FLASH Latency Returned value can be one of the following values :
  • FLASH_LATENCY_0 FLASH Zero wait state
  • FLASH_LATENCY_1 FLASH One wait state
  • FLASH_LATENCY_2 FLASH Two wait states
  • FLASH_LATENCY_3 FLASH Three wait states

Definition at line 595 of file stm32wbxx_hal_flash.h.

Referenced by HAL_RCC_ClockConfig(), HAL_RCC_GetClockConfig(), and RCC_SetFlashLatency().

#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE ( ) CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN)

Disable the FLASH instruction cache.

Return values:
none

Definition at line 619 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_FlushCaches(), and HAL_Init().

#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE ( ) SET_BIT(FLASH->ACR, FLASH_ACR_ICEN)

Enable the FLASH instruction cache.

Return values:
none

Definition at line 613 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_FlushCaches().

#define __HAL_FLASH_INSTRUCTION_CACHE_RESET ( )
Value:
do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);   \
                                                     CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
                                                   } while (0)

Reset the FLASH instruction Cache.

Note:
This function must be used only when the Instruction Cache is disabled.
Return values:
None

Definition at line 638 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_FlushCaches().

#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE ( ) CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)

Disable the FLASH prefetch buffer.

Return values:
None

Definition at line 607 of file stm32wbxx_hal_flash.h.

#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE ( ) SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)

Enable the FLASH prefetch buffer.

Return values:
None

Definition at line 601 of file stm32wbxx_hal_flash.h.

Referenced by HAL_Init().

#define __HAL_FLASH_SET_LATENCY ( __LATENCY__ ) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__))

Set the FLASH Latency.

Parameters:
__LATENCY__ FLASH Latency This parameter can be one of the following values :
  • FLASH_LATENCY_0 FLASH Zero wait state
  • FLASH_LATENCY_1 FLASH One wait state
  • FLASH_LATENCY_2 FLASH Two wait states
  • FLASH_LATENCY_3 FLASH Three wait states
Return values:
None

Definition at line 584 of file stm32wbxx_hal_flash.h.

Referenced by HAL_RCC_ClockConfig(), and RCC_SetFlashLatency().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FLASH Interrupts Macros

Defines
FLASH Interrupts Macros
FLASH

macros to handle FLASH interrupts More...

Defines

#define | __HAL_FLASH_ENABLE_IT(__INTERRUPT__)
Enable the specified FLASH interrupt.
#define | __HAL_FLASH_DISABLE_IT(__INTERRUPT__)
Disable the specified FLASH interrupt.
#define | __HAL_FLASH_GET_FLAG(__FLAG__)
Check whether the specified FLASH flag is set or not.
#define | __HAL_FLASH_CLEAR_FLAG(__FLAG__)
Clear the FLASH's pending flags.

Detailed Description

macros to handle FLASH interrupts

Define Documentation

#define __HAL_FLASH_CLEAR_FLAG ( __FLAG__ )
Value:
do { if(((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS)) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS))); }\
                                                     if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); }\
                                                   } while(0)

Clear the FLASH's pending flags.

Parameters:
__FLAG__ specifies the FLASH flags to clear. This parameter can be any combination of the following values:
  • FLASH_FLAG_EOP FLASH End of Operation flag
  • FLASH_FLAG_OPERR FLASH Operation error flag
  • FLASH_FLAG_PROGERR FLASH Programming error flag
  • FLASH_FLAG_WRPERR FLASH Write protection error flag
  • FLASH_FLAG_PGAERR FLASH Programming alignment error flag
  • FLASH_FLAG_SIZERR FLASH Size error flag
  • FLASH_FLAG_PGSERR FLASH Programming sequence error flag
  • FLASH_FLAG_MISERR FLASH Fast programming data miss error flag
  • FLASH_FLAG_FASTERR FLASH Fast programming error flag
  • FLASH_FLAG_RDERR FLASH PCROP read error flag
  • FLASH_FLAG_OPTVERR FLASH Option validity error flag
  • FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected
  • FLASH_FLAG_ECCD FLASH two ECC errors have been detected
  • FLASH_FLAG_SR_ERRORS FLASH All SR errors flags
  • FLASH_FLAG_ECCR_ERRORS FLASH All ECCR errors flags
  • FLASH_FLAG_ALL_ERRORS FLASH All errors flags
Return values:
None

Definition at line 736 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

#define __HAL_FLASH_DISABLE_IT ( __INTERRUPT__ )
Value:
do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCCIE); }\
                                                     if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
                                                   } while(0)

Disable the specified FLASH interrupt.

Parameters:
__INTERRUPT__ FLASH interrupt This parameter can be any combination of the following values:
  • FLASH_IT_EOP End of FLASH Operation Interrupt
  • FLASH_IT_OPERR Error Interrupt
  • FLASH_IT_RDERR PCROP Read Error Interrupt
  • FLASH_IT_ECCC ECC Correction Interrupt
Return values:
none

Definition at line 684 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler().

#define __HAL_FLASH_ENABLE_IT ( __INTERRUPT__ )
Value:
do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCCIE); }\
                                                     if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
                                                   } while(0)

Enable the specified FLASH interrupt.

Parameters:
__INTERRUPT__ FLASH interrupt This parameter can be any combination of the following values:
  • FLASH_IT_EOP End of FLASH Operation Interrupt
  • FLASH_IT_OPERR Error Interrupt
  • FLASH_IT_RDERR PCROP Read Error Interrupt
  • FLASH_IT_ECCC ECC Correction Interrupt
Return values:
none

Definition at line 670 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define __HAL_FLASH_GET_FLAG ( __FLAG__ )
Value:
((((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS)) != 0U) ? \
                                                 (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__))  : \
                                                 (READ_BIT(FLASH->SR,   (__FLAG__)) == (__FLAG__)))

Check whether the specified FLASH flag is set or not.

Parameters:
__FLAG__ specifies the FLASH flag to check. This parameter can be one of the following values:
  • FLASH_FLAG_EOP FLASH End of Operation flag
  • FLASH_FLAG_OPERR FLASH Operation error flag
  • FLASH_FLAG_PROGERR FLASH Programming error flag
  • FLASH_FLAG_WRPERR FLASH Write protection error flag
  • FLASH_FLAG_PGAERR FLASH Programming alignment error flag
  • FLASH_FLAG_SIZERR FLASH Size error flag
  • FLASH_FLAG_PGSERR FLASH Programming sequence error flag
  • FLASH_FLAG_MISERR FLASH Fast programming data miss error flag
  • FLASH_FLAG_FASTERR FLASH Fast programming error flag
  • FLASH_FLAG_OPTNV FLASH User Option OPTVAL indication
  • FLASH_FLAG_RDERR FLASH PCROP read error flag
  • FLASH_FLAG_OPTVERR FLASH Option validity error flag
  • FLASH_FLAG_BSY FLASH write/erase operations in progress flag
  • FLASH_FLAG_CFGBSY Programming/erase configuration busy
  • FLASH_FLAG_PESD FLASH Programming/erase operation suspended
  • FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected
  • FLASH_FLAG_ECCD FLASH two ECC errors have been detected
Return values:
The new state of FLASH_FLAG (SET or RESET).

Definition at line 711 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_Program_Fast(), FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FLASH Exported Variables

Variables
FLASH Exported Variables
FLASH

Variables

FLASH_ProcessTypeDef pFlash
Variable used for Program/Erase sectors under interruption.

Variable Documentation

FLASH_ProcessTypeDef pFlash

Variable used for Program/Erase sectors under interruption.

Definition at line 124 of file stm32wbxx_hal_flash.c.

Referenced by HAL_FLASHEx_Erase(), HAL_FLASHEx_Erase_IT(), and HAL_FLASHEx_OBProgram().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FLASH Private Types

Functions
FLASH Private Types
FLASH

Functions

HAL_StatusTypeDef FLASH_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH operation to complete.

Function Documentation

HAL_StatusTypeDef FLASH_WaitForLastOperation ( uint32_t Timeout )

Wait for a FLASH operation to complete.

Parameters:
Timeout Maximum flash operation timeout
Return values:
HAL_StatusTypeDef HAL Status

Definition at line 607 of file stm32wbxx_hal_flash.c.

References __HAL_FLASH_CLEAR_FLAG, __HAL_FLASH_GET_FLAG, FLASH_ProcessTypeDef::ErrorCode, FLASH_FLAG_BSY, FLASH_FLAG_CFGBSY, FLASH_FLAG_EOP, FLASH_FLAG_SR_ERRORS, and HAL_GetTick().

Referenced by FLASH_OB_ProceedWriteOperation(), HAL_FLASH_Program(), HAL_FLASH_Program_IT(), HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FLASH Private Constants

Defines
FLASH Private Constants
FLASH

Defines

#define | FLASH_NB_DOUBLE_WORDS_IN_ROW 64
#define | FLASH_END_ADDR (FLASH_BASE + FLASH_SIZE - 1U)
#define | FLASH_BANK_SIZE FLASH_SIZE
#define | FLASH_PAGE_SIZE 0x00001000U
#define | FLASH_PAGE_NB (FLASH_SIZE / FLASH_PAGE_SIZE)
#define | FLASH_TIMEOUT_VALUE 1000U
#define | FLASH_PCROP_GRANULARITY_OFFSET 11U
#define | FLASH_PCROP_GRANULARITY (1UL << FLASH_PCROP_GRANULARITY_OFFSET)
#define | FLASH_TYPENONE 0x00000000U

Define Documentation

#define FLASH_BANK_SIZE FLASH_SIZE

FLASH Bank Size

Definition at line 816 of file stm32wbxx_hal_flash.h.

#define FLASH_END_ADDR (FLASH_BASE + FLASH_SIZE - 1U)

Definition at line 814 of file stm32wbxx_hal_flash.h.

#define FLASH_NB_DOUBLE_WORDS_IN_ROW 64

Definition at line 111 of file stm32wbxx_hal_flash.c.

Referenced by FLASH_Program_Fast().

#define FLASH_PAGE_NB (FLASH_SIZE / FLASH_PAGE_SIZE)

Definition at line 818 of file stm32wbxx_hal_flash.h.

#define FLASH_PAGE_SIZE 0x00001000U

FLASH Page Size, 4 KBytes

Definition at line 817 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_OB_GetSecureMemoryConfig(), and FLASH_OB_SecureConfig().

#define FLASH_PCROP_GRANULARITY (1UL << FLASH_PCROP_GRANULARITY_OFFSET)

FLASH Code Readout Protection granularity, 2 KBytes

Definition at line 822 of file stm32wbxx_hal_flash.h.

#define FLASH_PCROP_GRANULARITY_OFFSET 11U

FLASH Code Readout Protection granularity offset

Definition at line 821 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_OB_GetPCROP(), FLASH_OB_PCROP1AConfig(), and FLASH_OB_PCROP1BConfig().

#define FLASH_TIMEOUT_VALUE 1000U

FLASH Execution Timeout, 1 s

Definition at line 819 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_OB_ProceedWriteOperation(), HAL_FLASH_Program(), HAL_FLASH_Program_IT(), HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

#define FLASH_TYPENONE 0x00000000U

No Programmation Procedure On Going

Definition at line 824 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SRAM memory size

Defines
SRAM memory size
FLASH

Defines

#define | SRAM_SECURE_PAGE_GRANULARITY_OFFSET 10U
#define | SRAM_SECURE_PAGE_GRANULARITY (1UL << FLASH_PCROP_GRANULARITY_OFFSET)

Define Documentation

#define SRAM_SECURE_PAGE_GRANULARITY (1UL << FLASH_PCROP_GRANULARITY_OFFSET)

Secure SRAM2A and SRAM2B Protection granularity, 1KBytes

Definition at line 833 of file stm32wbxx_hal_flash.h.

#define SRAM_SECURE_PAGE_GRANULARITY_OFFSET 10U

Secure SRAM2A and SRAM2B Protection granularity offset

Definition at line 832 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_OB_GetSecureMemoryConfig(), and FLASH_OB_SecureConfig().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FLASH Private Macros

Defines
FLASH Private Macros
FLASH

Defines

#define | IS_FLASH_MAIN_MEM_ADDRESS(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 1UL)))
#define | IS_FLASH_FAST_PROGRAM_ADDRESS(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 256UL)) && (((__VALUE__) % 256UL) == 0UL))
#define | IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 8UL)) && (((__VALUE__) % 8UL) == 0UL))
#define | IS_FLASH_PROGRAM_OTP_ADDRESS(__VALUE__) (((__VALUE__) >= OTP_AREA_BASE) && ((__VALUE__) <= (OTP_AREA_END_ADDR + 1UL - 8UL)) && (((__VALUE__) % 8UL) == 0UL))
#define | IS_FLASH_PROGRAM_ADDRESS(__VALUE__) (IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__VALUE__) || IS_FLASH_PROGRAM_OTP_ADDRESS(__VALUE__))
#define | IS_FLASH_PAGE(__VALUE__) ((__VALUE__) < FLASH_PAGE_NB)
#define | IS_ADDR_ALIGNED_64BITS(__VALUE__) (((__VALUE__) & 0x7U) == (0x00UL))
#define | IS_FLASH_TYPEERASE(__VALUE__)
#define | IS_FLASH_TYPEPROGRAM(__VALUE__)
#define | IS_OB_SFSA_START_ADDR(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= FLASH_END_ADDR) && (((__VALUE__) & ~(uint32_t)0xFFFU) == (__VALUE__)))
#define | IS_OB_SBRSA_START_ADDR(__VALUE__) (((__VALUE__) >= SRAM2A_BASE) && ((__VALUE__) <= (SRAM2A_BASE + SRAM2A_SIZE - 1U)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__)))
#define | IS_OB_SNBRSA_START_ADDR(__VALUE__) (((__VALUE__) >= SRAM2B_BASE) && ((__VALUE__) <= (SRAM2B_BASE + SRAM2B_SIZE - 1U)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__)))
#define | IS_OB_SECURE_MODE(__VALUE__) (((__VALUE__) == SYSTEM_IN_SECURE_MODE) || ((__VALUE__) == SYSTEM_NOT_IN_SECURE_MODE))
#define | IS_OPTIONBYTE(__VALUE__)
#define | IS_OB_WRPAREA(__VALUE__) (((__VALUE__) == OB_WRPAREA_BANK1_AREAA) || ((__VALUE__) == OB_WRPAREA_BANK1_AREAB))
#define | IS_OB_RDP_LEVEL(__VALUE__)
#define | IS_OB_USER_TYPE(__VALUE__)
#define | IS_OB_USER_CONFIG(__TYPE__, __VALUE__)
#define | IS_OB_USER_AGC_TRIMMING(__VALUE__)
#define | IS_OB_USER_BOR_LEVEL(__VALUE__)
#define | IS_OB_PCROP_CONFIG(__VALUE__) (((__VALUE__) & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | OB_PCROP_RDP_ERASE)) == 0U)
#define | IS_OB_IPCC_BUF_ADDR(__VALUE__) (IS_OB_SBRSA_START_ADDR(__VALUE__) || IS_OB_SNBRSA_START_ADDR(__VALUE__))
#define | IS_OB_BOOT_VECTOR_ADDR(__VALUE__)
#define | IS_OB_BOOT_REGION(__VALUE__) (((__VALUE__) == OB_C2_BOOT_FROM_FLASH) || ((__VALUE__) == OB_C2_BOOT_FROM_SRAM))
#define | IS_OB_SECURE_CONFIG(__VALUE__) (((__VALUE__) & ~(OB_SECURE_CONFIG_MEMORY | OB_SECURE_CONFIG_BOOT_RESET)) == 0U)
#define | IS_FLASH_LATENCY(__VALUE__)

Define Documentation

#define IS_ADDR_ALIGNED_64BITS ( __VALUE__ ) (((__VALUE__) & 0x7U) == (0x00UL))

Definition at line 854 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

#define IS_FLASH_FAST_PROGRAM_ADDRESS ( __VALUE__ ) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 256UL)) && (((__VALUE__) % 256UL) == 0UL))

Definition at line 844 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

#define IS_FLASH_LATENCY ( __VALUE__ )
Value:
(((__VALUE__) == FLASH_LATENCY_0) || \
                                                     ((__VALUE__) == FLASH_LATENCY_1) || \
                                                     ((__VALUE__) == FLASH_LATENCY_2) || \
                                                     ((__VALUE__) == FLASH_LATENCY_3))

Definition at line 918 of file stm32wbxx_hal_flash.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_FLASH_MAIN_MEM_ADDRESS ( __VALUE__ ) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 1UL)))

Definition at line 842 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_OB_PCROP1AConfig(), and FLASH_OB_PCROP1BConfig().

#define IS_FLASH_PAGE ( __VALUE__ ) ((__VALUE__) < FLASH_PAGE_NB)

Definition at line 852 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_OB_WRPConfig(), and FLASH_PageErase().

#define IS_FLASH_PROGRAM_ADDRESS ( __VALUE__ ) (IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__VALUE__) || IS_FLASH_PROGRAM_OTP_ADDRESS(__VALUE__))

Definition at line 850 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

#define IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS ( __VALUE__ ) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 8UL)) && (((__VALUE__) % 8UL) == 0UL))

Definition at line 846 of file stm32wbxx_hal_flash.h.

#define IS_FLASH_PROGRAM_OTP_ADDRESS ( __VALUE__ ) (((__VALUE__) >= OTP_AREA_BASE) && ((__VALUE__) <= (OTP_AREA_END_ADDR + 1UL - 8UL)) && (((__VALUE__) % 8UL) == 0UL))

Definition at line 848 of file stm32wbxx_hal_flash.h.

#define IS_FLASH_TYPEERASE ( __VALUE__ )
Value:
(((__VALUE__) == FLASH_TYPEERASE_PAGES) || \
                                                     ((__VALUE__) == FLASH_TYPEERASE_MASSERASE))

Definition at line 856 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

#define IS_FLASH_TYPEPROGRAM ( __VALUE__ )
Value:
(((__VALUE__) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \
                                                     ((__VALUE__) == FLASH_TYPEPROGRAM_FAST))

Definition at line 859 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

#define IS_OB_BOOT_REGION ( __VALUE__ ) (((__VALUE__) == OB_C2_BOOT_FROM_FLASH) || ((__VALUE__) == OB_C2_BOOT_FROM_SRAM))

Definition at line 914 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_OB_SecureConfig().

#define IS_OB_BOOT_VECTOR_ADDR ( __VALUE__ )
Value:
((((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 1U)))    || \
                                                     (((__VALUE__) >= SRAM1_BASE) && ((__VALUE__) <= (SRAM1_BASE + SRAM1_SIZE - 1U)))    || \
                                                     (((__VALUE__) >= SRAM2A_BASE) && ((__VALUE__) <= (SRAM2A_BASE + SRAM2A_SIZE - 1U))) || \
                                                     (((__VALUE__) >= SRAM2B_BASE) && ((__VALUE__) <= (SRAM2B_BASE + SRAM2B_SIZE - 1U))))

Definition at line 909 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_OB_SecureConfig().

#define IS_OB_IPCC_BUF_ADDR ( __VALUE__ ) (IS_OB_SBRSA_START_ADDR(__VALUE__) || IS_OB_SNBRSA_START_ADDR(__VALUE__))

Definition at line 907 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_OB_IPCCBufferAddrConfig().

#define IS_OB_PCROP_CONFIG ( __VALUE__ ) (((__VALUE__) & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | OB_PCROP_RDP_ERASE)) == 0U)

Definition at line 905 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_OB_PCROP1AConfig(), and HAL_FLASHEx_OBProgram().

#define IS_OB_RDP_LEVEL ( __VALUE__ )
Value:
(((__VALUE__) == OB_RDP_LEVEL_0)   ||\
                                                     ((__VALUE__) == OB_RDP_LEVEL_1)   ||\
                                                     ((__VALUE__) == OB_RDP_LEVEL_2))

Definition at line 872 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_OB_OptrConfig().

#define IS_OB_SBRSA_START_ADDR ( __VALUE__ ) (((__VALUE__) >= SRAM2A_BASE) && ((__VALUE__) <= (SRAM2A_BASE + SRAM2A_SIZE - 1U)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__)))

Definition at line 863 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_OB_SecureConfig().

#define IS_OB_SECURE_CONFIG ( __VALUE__ ) (((__VALUE__) & ~(OB_SECURE_CONFIG_MEMORY | OB_SECURE_CONFIG_BOOT_RESET)) == 0U)

Definition at line 916 of file stm32wbxx_hal_flash.h.

#define IS_OB_SECURE_MODE ( __VALUE__ ) (((__VALUE__) == SYSTEM_IN_SECURE_MODE) || ((__VALUE__) == SYSTEM_NOT_IN_SECURE_MODE))

Definition at line 865 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_OB_SecureConfig().

#define IS_OB_SFSA_START_ADDR ( __VALUE__ ) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= FLASH_END_ADDR) && (((__VALUE__) & ~(uint32_t)0xFFFU) == (__VALUE__)))

Definition at line 862 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_OB_SecureConfig().

#define IS_OB_SNBRSA_START_ADDR ( __VALUE__ ) (((__VALUE__) >= SRAM2B_BASE) && ((__VALUE__) <= (SRAM2B_BASE + SRAM2B_SIZE - 1U)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__)))

Definition at line 864 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_OB_SecureConfig().

#define IS_OB_USER_AGC_TRIMMING ( __VALUE__ )
Value:
(((__VALUE__) == OB_AGC_TRIM_0) || ((__VALUE__) == OB_AGC_TRIM_1) || \
                                                     ((__VALUE__) == OB_AGC_TRIM_2) || ((__VALUE__) == OB_AGC_TRIM_3) || \
                                                     ((__VALUE__) == OB_AGC_TRIM_4) || ((__VALUE__) == OB_AGC_TRIM_5) || \
                                                     ((__VALUE__) == OB_AGC_TRIM_6) || ((__VALUE__) == OB_AGC_TRIM_7))

Definition at line 896 of file stm32wbxx_hal_flash.h.

#define IS_OB_USER_BOR_LEVEL ( __VALUE__ )
Value:
(((__VALUE__) == OB_BOR_LEVEL_0) || ((__VALUE__) == OB_BOR_LEVEL_1) || \
                                                     ((__VALUE__) == OB_BOR_LEVEL_2) || ((__VALUE__) == OB_BOR_LEVEL_3) || \
                                                     ((__VALUE__) == OB_BOR_LEVEL_4))

Definition at line 901 of file stm32wbxx_hal_flash.h.

#define IS_OB_USER_CONFIG | ( | __TYPE__,
 |  | __VALUE__
 | ) |
Value:
((((__TYPE__) & OB_USER_BOR_LEV) == OB_USER_BOR_LEV) \
                                                      ? ((((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_0) || \
                                                         (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_1) || \
                                                         (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_2) || \
                                                         (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_3) || \
                                                         (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_4)) \
                                                      : ((((__TYPE__) & OB_USER_AGC_TRIM) == OB_USER_AGC_TRIM) \
                                                       ? ((((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_0) || \
                                                          (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_1) || \
                                                          (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_2) || \
                                                          (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_3) || \
                                                          (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_4) || \
                                                          (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_5) || \
                                                          (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_6) || \
                                                          (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_7)) \
                                                       : ((~(__TYPE__) & (__VALUE__)) == 0U)))

Definition at line 879 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_OB_OptrConfig().

#define IS_OB_USER_TYPE ( __VALUE__ )
Value:
((((__VALUE__) & OB_USER_ALL) != 0U) && \
                                                     (((__VALUE__) & ~OB_USER_ALL) == 0U))

Definition at line 876 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_OB_OptrConfig().

#define IS_OB_WRPAREA ( __VALUE__ ) (((__VALUE__) == OB_WRPAREA_BANK1_AREAA) || ((__VALUE__) == OB_WRPAREA_BANK1_AREAB))

Definition at line 870 of file stm32wbxx_hal_flash.h.

Referenced by FLASH_OB_GetWRP(), and FLASH_OB_WRPConfig().

#define IS_OPTIONBYTE ( __VALUE__ )
Value:
(((__VALUE__) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP | \
                                                              OPTIONBYTE_IPCC_BUF_ADDR | OPTIONBYTE_C2_BOOT_VECT | OPTIONBYTE_SECURE_MODE)))

Definition at line 867 of file stm32wbxx_hal_flash.h.

Referenced by HAL_FLASHEx_OBProgram().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FLASHEx Private Functions

Functions
FLASHEx Private Functions
FLASHEx

Functions

static void | FLASH_MassErase (void)
Mass erase of FLASH memory.
static void | FLASH_AcknowledgePageErase (void)
Acknlowldge the page erase operation.
static void | FLASH_FlushCaches (void)
Flush the instruction and data caches.
static void | FLASH_OB_WRPConfig (uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset)
Configure the write protection of the desired pages.
static void | FLASH_OB_OptrConfig (uint32_t UserType, uint32_t UserConfig, uint32_t RDPLevel)
Set user & RDP configuration.
static void | FLASH_OB_PCROP1AConfig (uint32_t PCROPConfig, uint32_t PCROP1AStartAddr, uint32_t PCROP1AEndAddr)
Configure the Zone 1A Proprietary code readout protection of the desired addresses, and erase configuration on RDP regression.
static void | FLASH_OB_PCROP1BConfig (uint32_t PCROP1BStartAddr, uint32_t PCROP1BEndAddr)
Configure the Zone 1B Proprietary code readout protection of the desired addresses.
static void | FLASH_OB_IPCCBufferAddrConfig (uint32_t IPCCDataBufAddr)
Program the FLASH IPCC data buffer address.
static void | FLASH_OB_SecureConfig (FLASH_OBProgramInitTypeDef *pOBParam)
Configure the secure start address of the different memories (FLASH and SRAM2), the secure mode and the CPU2 Secure Boot reset vector.
static void | FLASH_OB_GetWRP (uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRDPEndOffset)
Return the FLASH Write Protection Option Bytes value.
static uint32_t | FLASH_OB_GetRDP (void)
Return the FLASH Read Protection level.
static uint32_t | FLASH_OB_GetUser (void)
Return the FLASH User Option Byte value.
static void | FLASH_OB_GetPCROP (uint32_t *PCROPConfig, uint32_t *PCROP1AStartAddr, uint32_t *PCROP1AEndAddr, uint32_t *PCROP1BStartAddr, uint32_t *PCROP1BEndAddr)
Return the FLASH Write Protection Option Bytes value.
static uint32_t | FLASH_OB_GetIPCCBufferAddr (void)
Return the FLASH IPCC data buffer base address Option Byte value.
static void | FLASH_OB_GetSecureMemoryConfig (uint32_t *SecureFlashStartAddr, uint32_t *SecureRAM2aStartAddr, uint32_t *SecureRAM2bStartAddr, uint32_t *SecureMode)
Return the Secure Flash start address, Secure Backup RAM2a start address, Secure non-Backup RAM2b start address and the SecureMode.
static void | FLASH_OB_GetC2BootResetConfig (uint32_t *C2BootResetVectAddr, uint32_t *C2BootResetRegion)
Return the CPU2 Secure Boot reset vector address and the CPU2 Secure Boot Region.
static HAL_StatusTypeDef | FLASH_OB_ProceedWriteOperation (void)
Proceed the OB Write Operation.
void | FLASH_PageErase (uint32_t Page)
Erase the specified FLASH memory page.

Function Documentation

static void FLASH_AcknowledgePageErase ( void ) [static]

Acknlowldge the page erase operation.

Return values:
None

Definition at line 574 of file stm32wbxx_hal_flash_ex.c.

Referenced by HAL_FLASHEx_Erase().

static void FLASH_FlushCaches ( void ) [static]

Flush the instruction and data caches.

Return values:
None

Definition at line 545 of file stm32wbxx_hal_flash_ex.c.

References __HAL_FLASH_DATA_CACHE_DISABLE, __HAL_FLASH_DATA_CACHE_ENABLE, __HAL_FLASH_DATA_CACHE_RESET, __HAL_FLASH_INSTRUCTION_CACHE_DISABLE, __HAL_FLASH_INSTRUCTION_CACHE_ENABLE, and __HAL_FLASH_INSTRUCTION_CACHE_RESET.

Referenced by HAL_FLASHEx_Erase().

static void FLASH_MassErase ( void ) [static]

Mass erase of FLASH memory.

Return values:
None

Definition at line 520 of file stm32wbxx_hal_flash_ex.c.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

static void FLASH_OB_GetC2BootResetConfig | ( | uint32_t * | C2BootResetVectAddr,
 |  | uint32_t * | C2BootResetRegion
 | ) |  | [static]

Return the CPU2 Secure Boot reset vector address and the CPU2 Secure Boot Region.

Parameters:
C2BootResetVectAddr | Specifies the address where to copied the CPU2 Secure Boot reset vector address
C2BootResetRegion | Specifies the Secure Boot reset memory region
Return values:
None

Definition at line 1003 of file stm32wbxx_hal_flash_ex.c.

References OB_C2_BOOT_FROM_FLASH.

Referenced by HAL_FLASHEx_OBGetConfig().

static uint32_t FLASH_OB_GetIPCCBufferAddr ( void ) [static]

Return the FLASH IPCC data buffer base address Option Byte value.

Return values:
Returned value is the IPCC data buffer start address area in SRAM2.

Definition at line 957 of file stm32wbxx_hal_flash_ex.c.

Referenced by HAL_FLASHEx_OBGetConfig().

static void FLASH_OB_GetPCROP | ( | uint32_t * | PCROPConfig,
 |  | uint32_t * | PCROP1AStartAddr,
 |  | uint32_t * | PCROP1AEndAddr,
 |  | uint32_t * | PCROP1BStartAddr,
 |  | uint32_t * | PCROP1BEndAddr
 | ) |  | [static]

Return the FLASH Write Protection Option Bytes value.

Parameters:
PCROPConfig | [out] Specifies the address where to copied the configuration of PCROP_RDP option
PCROP1AStartAddr | [out] Specifies the address where to copied the start address of the Zone 1A Proprietary code readout protection
PCROP1AEndAddr | [out] Specifies the address where to copied the end address of the Zone 1A Proprietary code readout protection
PCROP1BStartAddr | [out] Specifies the address where to copied the start address of the Zone 1B Proprietary code readout protection
PCROP1BEndAddr | [out] Specifies the address where to copied the end address of the Zone 1B Proprietary code readout protection
Return values:
None

Definition at line 934 of file stm32wbxx_hal_flash_ex.c.

References FLASH_PCROP_GRANULARITY_OFFSET.

Referenced by HAL_FLASHEx_OBGetConfig().

static uint32_t FLASH_OB_GetRDP ( void ) [static]

Return the FLASH Read Protection level.

Return values:
FLASH ReadOut Protection Status: This return value can be one of the following values:
  • OB_RDP_LEVEL_0 No protection
  • OB_RDP_LEVEL_1 Read protection of the memory
  • OB_RDP_LEVEL_2 Full chip protection

Definition at line 881 of file stm32wbxx_hal_flash_ex.c.

References OB_RDP_LEVEL_0, OB_RDP_LEVEL_1, and OB_RDP_LEVEL_2.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

static void FLASH_OB_GetSecureMemoryConfig | ( | uint32_t * | SecureFlashStartAddr,
 |  | uint32_t * | SecureRAM2aStartAddr,
 |  | uint32_t * | SecureRAM2bStartAddr,
 |  | uint32_t * | SecureMode
 | ) |  | [static]

Return the Secure Flash start address, Secure Backup RAM2a start address, Secure non-Backup RAM2b start address and the SecureMode.

Parameters:
SecureFlashStartAddr | Specifies the address where to copied the Secure Flash start address
SecureRAM2aStartAddr | Specifies the address where to copied the Secure Backup RAM2a start address
SecureRAM2bStartAddr | Specifies the address where to copied the Secure non-Backup RAM2b start address
SecureMode Specifies the address where to copied the Secure Mode. This return value can be one of the following values:
  • SYSTEM_IN_SECURE_MODE : Security enabled
  • SYSTEM_NOT_IN_SECURE_MODE : Security disabled
Return values:
None

Definition at line 973 of file stm32wbxx_hal_flash_ex.c.

References FLASH_PAGE_SIZE, and SRAM_SECURE_PAGE_GRANULARITY_OFFSET.

Referenced by HAL_FLASHEx_OBGetConfig().

static uint32_t FLASH_OB_GetUser ( void ) [static]

Return the FLASH User Option Byte value.

Return values:
This return value can be a combination of all the following values:
  • OB_BOR_LEVEL_0 or OB_BOR_LEVEL_1 or ... or OB_BOR_LEVEL_4
  • OB_STOP_RST or OB_STOP_RST
  • OB_STANDBY_RST or OB_STANDBY_NORST
  • OB_SHUTDOWN_RST or OB_SHUTDOWN_NORST
  • OB_IWDG_SW or OB_IWDG_HW
  • OB_IWDG_STOP_FREEZE or OB_IWDG_STOP_RUN
  • OB_IWDG_STDBY_FREEZE or OB_IWDG_STDBY_RUN
  • OB_WWDG_SW or OB_WWDG_HW
  • OB_BOOT1_SRAM or OB_BOOT1_SYSTEM
  • OB_SRAM2_PARITY_ENABLE or OB_SRAM2_PARITY_DISABLE
  • OB_SRAM2_RST_ERASE or OB_SRAM2_RST_NOT_ERASE
  • OB_BOOT0_FROM_OB or OB_BOOT0_FROM_PIN
  • OB_BOOT0_RESET or OB_BOOT0_SET
  • OB_AGC_TRIM_0 or OB_AGC_TRIM_1 or ... or OB_AGC_TRIM_7

Definition at line 913 of file stm32wbxx_hal_flash_ex.c.

References OB_USER_ALL.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

static void FLASH_OB_GetWRP | ( | uint32_t | WRPArea,
 |  | uint32_t * | WRPStartOffset,
 |  | uint32_t * | WRDPEndOffset
 | ) |  | [static]

Return the FLASH Write Protection Option Bytes value.

Parameters:
[in] WRPArea Specifies the area to be returned. This parameter can be one of the following values:
  • OB_WRPAREA_BANK1_AREAA Flash Bank 1 Area A
  • OB_WRPAREA_BANK1_AREAB Flash Bank 1 Area B
[out] | WRPStartOffset | Specifies the address where to copied the start page of the write protected area
[out] | WRDPEndOffset | Specifies the address where to copied the end page of the write protected area
Return values:
None

Definition at line 855 of file stm32wbxx_hal_flash_ex.c.

References assert_param, IS_OB_WRPAREA, and OB_WRPAREA_BANK1_AREAA.

Referenced by HAL_FLASHEx_OBGetConfig().

static void FLASH_OB_IPCCBufferAddrConfig ( uint32_t IPCCDataBufAddr ) [static]

Program the FLASH IPCC data buffer address.

Note:
To configure the extra user option bytes, the option lock bit OPTLOCK must be cleared with the call of the HAL_FLASH_OB_Unlock() function.
To validate the extra user option bytes, the option bytes must be reloaded through the call of the HAL_FLASH_OB_Launch() function.
Parameters:
IPCCDataBufAddr IPCC data buffer start address area in SRAM2 This parameter must be the double-word aligned
Return values:
None

Definition at line 767 of file stm32wbxx_hal_flash_ex.c.

References assert_param, and IS_OB_IPCC_BUF_ADDR.

Referenced by HAL_FLASHEx_OBProgram().

static void FLASH_OB_OptrConfig | ( | uint32_t | UserType,
 |  | uint32_t | UserConfig,
 |  | uint32_t | RDPLevel
 | ) |  | [static]

Set user & RDP configuration.

Note:
!!! Warning : When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 !!!
Parameters:
UserType The FLASH User Option Bytes to be modified This parameter can be a combination of all the following values:
  • OB_USER_BOR_LEV or OB_USER_nRST_STOP or OB_USER_nRST_STDBY or
  • OB_USER_nRST_SHDW or OB_USER_IWDG_SW or OB_USER_IWDG_STOP or
  • OB_USER_IWDG_STDBY or OB_USER_WWDG_SW or OB_USER_nBOOT1 or
  • OB_USER_SRAM2PE or OB_USER_SRAM2RST or OB_USER_nSWBOOT0 or
  • OB_USER_nBOOT0 or OB_USER_AGC_TRIM or OB_USER_ALL
UserConfig The FLASH User Option Bytes values. This parameter can be a combination of all the following values:
  • OB_BOR_LEVEL_0 or OB_BOR_LEVEL_1 or ... or OB_BOR_LEVEL_4
  • OB_STOP_RST or OB_STOP_NORST
  • OB_STANDBY_RST or OB_STANDBY_NORST
  • OB_SHUTDOWN_RST or OB_SHUTDOWN_NORST
  • OB_IWDG_SW or OB_IWDG_HW
  • OB_IWDG_STOP_FREEZE or OB_IWDG_STOP_RUN
  • OB_IWDG_STDBY_FREEZE or OB_IWDG_STDBY_RUN
  • OB_WWDG_SW or OB_WWDG_HW
  • OB_BOOT1_SRAM or OB_BOOT1_SYSTEM
  • OB_SRAM2_PARITY_ENABLE or OB_SRAM2_PARITY_DISABLE
  • OB_SRAM2_RST_ERASE or OB_SRAM2_RST_NOT_ERASE
  • OB_BOOT0_FROM_OB or OB_BOOT0_FROM_PIN
  • OB_BOOT0_RESET or OB_BOOT0_SET
  • OB_AGC_TRIM_0 or OB_AGC_TRIM_1 or ... or OB_AGC_TRIM_7
RDPLevel,: specifies the read protection level. This parameter can be one of the following values:
  • OB_RDP_LEVEL_0 No protection
  • OB_RDP_LEVEL_1 Read protection of the memory
  • OB_RDP_LEVEL_2 Full chip protection
Return values:
None

Definition at line 656 of file stm32wbxx_hal_flash_ex.c.

References assert_param, IS_OB_RDP_LEVEL, IS_OB_USER_CONFIG, and IS_OB_USER_TYPE.

Referenced by HAL_FLASHEx_OBProgram().

static void FLASH_OB_PCROP1AConfig | ( | uint32_t | PCROPConfig,
 |  | uint32_t | PCROP1AStartAddr,
 |  | uint32_t | PCROP1AEndAddr
 | ) |  | [static]

Configure the Zone 1A Proprietary code readout protection of the desired addresses, and erase configuration on RDP regression.

Note:
To configure the PCROP options, the option lock bit OPTLOCK must be cleared with the call of the HAL_FLASH_OB_Unlock() function.
To validate the PCROP options, the option bytes must be reloaded through the call of the HAL_FLASH_OB_Launch() function.
Parameters:
PCROPConfig,: specifies the erase configuration (OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE) on RDP level 1 regression.
PCROP1AStartAddr | Specifies the Zone 1A Start address of the Proprietary code readout protection This parameter can be an address between begin and end of the flash
PCROP1AEndAddr | Specifies the Zone 1A end address of the Proprietary code readout protection This parameter can be an address between PCROP1AStartAddr and end of the flash
Return values:
None

Definition at line 686 of file stm32wbxx_hal_flash_ex.c.

References assert_param, FLASH_PCROP_GRANULARITY_OFFSET, IS_FLASH_MAIN_MEM_ADDRESS, IS_OB_PCROP_CONFIG, OB_PCROP_RDP_ERASE, and OB_PCROP_ZONE_A.

Referenced by HAL_FLASHEx_OBProgram().

static void FLASH_OB_PCROP1BConfig | ( | uint32_t | PCROP1BStartAddr,
 |  | uint32_t | PCROP1BEndAddr
 | ) |  | [static]

Configure the Zone 1B Proprietary code readout protection of the desired addresses.

Note:
To configure the PCROP options, the option lock bit OPTLOCK must be cleared with the call of the HAL_FLASH_OB_Unlock() function.
To validate the PCROP options, the option bytes must be reloaded through the call of the HAL_FLASH_OB_Launch() function.
Parameters:
PCROP1BStartAddr | Specifies the Zone 1BStart address of the Proprietary code readout protection This parameter can be an address between begin and end of the flash
PCROP1BEndAddr | Specifies the Zone 1B end address of the Proprietary code readout protection This parameter can be an address between PCROP1BStartAddr and end of the flash
Return values:
None

Definition at line 737 of file stm32wbxx_hal_flash_ex.c.

References assert_param, FLASH_PCROP_GRANULARITY_OFFSET, and IS_FLASH_MAIN_MEM_ADDRESS.

Referenced by HAL_FLASHEx_OBProgram().

static HAL_StatusTypeDef FLASH_OB_ProceedWriteOperation ( void ) [static]

Proceed the OB Write Operation.

Return values:
HAL Status

Definition at line 1021 of file stm32wbxx_hal_flash_ex.c.

References FLASH_TIMEOUT_VALUE, and FLASH_WaitForLastOperation().

Referenced by HAL_FLASHEx_OBProgram().

static void FLASH_OB_SecureConfig ( FLASH_OBProgramInitTypeDef * pOBParam ) [static]

Configure the secure start address of the different memories (FLASH and SRAM2), the secure mode and the CPU2 Secure Boot reset vector.

Note:
To configure the PCROP options, the option lock bit OPTLOCK must be cleared with the call of the HAL_FLASH_OB_Unlock() function.
Parameters:
pOBParam Pointer to an FLASH_OBProgramInitTypeDef structure that contains the configuration information for the programming
Return values:
void

Definition at line 784 of file stm32wbxx_hal_flash_ex.c.

References assert_param, FLASH_OBProgramInitTypeDef::C2BootRegion, FLASH_OBProgramInitTypeDef::C2SecureBootVectAddr, FLASH_PAGE_SIZE, IS_OB_BOOT_REGION, IS_OB_BOOT_VECTOR_ADDR, IS_OB_SBRSA_START_ADDR, IS_OB_SECURE_MODE, IS_OB_SFSA_START_ADDR, IS_OB_SNBRSA_START_ADDR, OB_C2_BOOT_FROM_FLASH, OPTIONBYTE_C2_BOOT_VECT, OPTIONBYTE_SECURE_MODE, FLASH_OBProgramInitTypeDef::OptionType, FLASH_OBProgramInitTypeDef::SecureFlashStartAddr, FLASH_OBProgramInitTypeDef::SecureMode, FLASH_OBProgramInitTypeDef::SecureRAM2aStartAddr, FLASH_OBProgramInitTypeDef::SecureRAM2bStartAddr, SRAM_SECURE_PAGE_GRANULARITY_OFFSET, and SYSTEM_IN_SECURE_MODE.

Referenced by HAL_FLASHEx_OBProgram().

static void FLASH_OB_WRPConfig | ( | uint32_t | WRPArea,
 |  | uint32_t | WRPStartOffset,
 |  | uint32_t | WRDPEndOffset
 | ) |  | [static]

Configure the write protection of the desired pages.

Note:
When WRP is active in a zone, it cannot be erased or programmed. Consequently, a software mass erase cannot be performed if one zone is write-protected.
When the memory read protection level is selected (RDP level = 1), it is not possible to program or erase Flash memory if the CPU debug features are connected (JTAG or single wire) or boot code is being executed from RAM or System flash, even if WRP is not activated.
To configure the WRP options, the option lock bit OPTLOCK must be cleared with the call of the HAL_FLASH_OB_Unlock() function.
To validate the WRP options, the option bytes must be reloaded through the call of the HAL_FLASH_OB_Launch() function.
Parameters:
WRPArea Specifies the area to be configured. This parameter can be one of the following values:
  • OB_WRPAREA_BANK1_AREAA Flash Bank 1 Area A
  • OB_WRPAREA_BANK1_AREAB Flash Bank 1 Area B
WRPStartOffset | Specifies the start page of the write protected area This parameter can be page number between 0 and (max number of pages in the Flash - 1)
WRDPEndOffset | Specifies the end page of the write protected area This parameter can be page number between WRPStartOffset and (max number of pages in the Flash - 1)
Return values:
None

Definition at line 602 of file stm32wbxx_hal_flash_ex.c.

References assert_param, IS_FLASH_PAGE, IS_OB_WRPAREA, and OB_WRPAREA_BANK1_AREAA.

Referenced by HAL_FLASHEx_OBProgram().

void FLASH_PageErase ( uint32_t Page )

Erase the specified FLASH memory page.

Parameters:
Page FLASH page to erase This parameter must be a value between 0 and (max number of pages in Flash - 1)
Return values:
None

Definition at line 532 of file stm32wbxx_hal_flash_ex.c.

References assert_param, and IS_FLASH_PAGE.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Extended IO operation functions

Functions
Extended IO operation functions
FLASH Extended Exported Functions

Extended IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_FLASHEx_Erase (FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
Perform a mass erase or erase the specified FLASH memory pages.
HAL_StatusTypeDef | HAL_FLASHEx_Erase_IT (FLASH_EraseInitTypeDef *pEraseInit)
Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.
HAL_StatusTypeDef | HAL_FLASHEx_OBProgram (FLASH_OBProgramInitTypeDef *pOBInit)
Program Option bytes.
void | HAL_FLASHEx_OBGetConfig (FLASH_OBProgramInitTypeDef *pOBInit)
Get the Option bytes configuration.
uint32_t | HAL_FLASHEx_FlashEmptyCheck (void)
Flash Empty check.
void | HAL_FLASHEx_ForceFlashEmpty (uint32_t FlashEmpty)
Force Empty check value.
void | HAL_FLASHEx_SuspendOperation (void)
Suspend new program or erase operation request.
void | HAL_FLASHEx_AllowOperation (void)
Allow new program or erase operation request.
uint32_t | HAL_FLASHEx_IsOperationSuspended (void)
Check if new program or erase operation request from CPU1 or CPU2 is suspended.

Detailed Description

Extended IO operation functions.

 ===============================================================================
                ##### Extended programming operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the Extended FLASH
    programming operations Operations.

Function Documentation

void HAL_FLASHEx_AllowOperation ( void )

Allow new program or erase operation request.

Note:
Any new Flash program and erase operation on both CPU side will be allowed until one of this bit or the same bit in Flash CPU2 access control register (FLASH_C2ACR) is set. The PESD bit in both the Flash status register (FLASH_SR) and Flash CPU2 status register (FLASH_C2SR) register will be clear when both PES bit in FLASH_ACR or FLASH_C2ACR is cleared.
Return values:
None

Definition at line 475 of file stm32wbxx_hal_flash_ex.c.

HAL_StatusTypeDef HAL_FLASHEx_Erase | ( | FLASH_EraseInitTypeDef * | pEraseInit,
 |  | uint32_t * | PageError
 | ) |  |

Perform a mass erase or erase the specified FLASH memory pages.

Note:
Before any operation, it is possible to check there is no operation suspended by call HAL_FLASHEx_IsOperationSuspended()
Parameters:
[in] | pEraseInit | Pointer to an FLASH_EraseInitTypeDef structure that contains the configuration information for the erasing.
[out] | PageError | Pointer to variable that contains the configuration information on faulty page in case of error (0xFFFFFFFF means that all the pages have been correctly erased)
Return values:
HAL Status

Definition at line 152 of file stm32wbxx_hal_flash_ex.c.

References assert_param, FLASH_ProcessTypeDef::ErrorCode, FLASH_AcknowledgePageErase(), FLASH_FlushCaches(), FLASH_MassErase(), FLASH_PageErase(), FLASH_TIMEOUT_VALUE, FLASH_TYPEERASE_MASSERASE, FLASH_WaitForLastOperation(), HAL_FLASH_ERROR_NONE, IS_FLASH_TYPEERASE, FLASH_EraseInitTypeDef::NbPages, FLASH_EraseInitTypeDef::Page, pFlash, and FLASH_EraseInitTypeDef::TypeErase.

HAL_StatusTypeDef HAL_FLASHEx_Erase_IT ( FLASH_EraseInitTypeDef * pEraseInit )

Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.

Note:
Before any operation, it is possible to check there is no operation suspended by call HAL_FLASHEx_IsOperationSuspended()
Parameters:
pEraseInit Pointer to an FLASH_EraseInitTypeDef structure that contains the configuration information for the erasing.
Return values:
HAL Status

Definition at line 224 of file stm32wbxx_hal_flash_ex.c.

References __HAL_FLASH_ENABLE_IT, assert_param, FLASH_ProcessTypeDef::ErrorCode, FLASH_IT_EOP, FLASH_IT_OPERR, FLASH_MassErase(), FLASH_PageErase(), FLASH_TIMEOUT_VALUE, FLASH_TYPEERASE_MASSERASE, FLASH_WaitForLastOperation(), HAL_FLASH_ERROR_NONE, IS_FLASH_TYPEERASE, FLASH_EraseInitTypeDef::NbPages, FLASH_ProcessTypeDef::NbPagesToErase, FLASH_EraseInitTypeDef::Page, FLASH_ProcessTypeDef::Page, pFlash, FLASH_ProcessTypeDef::ProcedureOnGoing, and FLASH_EraseInitTypeDef::TypeErase.

uint32_t HAL_FLASHEx_FlashEmptyCheck ( void )

Flash Empty check.

Note:
This API checks if first location in Flash is programmed or not. This check is done once by Option Byte Loader.
Return values:
Returned value can be one of the following values:
  • FLASH_PROG_NOT_EMPTY 1st location in Flash is programmed
  • FLASH_PROG_EMPTY 1st location in Flash is empty

Definition at line 428 of file stm32wbxx_hal_flash_ex.c.

void HAL_FLASHEx_ForceFlashEmpty ( uint32_t FlashEmpty )

Force Empty check value.

Note:
Allows to modify program empty check value in order to force this information in Flash Interface, for all next reset that do not launch Option Byte Loader.
Parameters:
FlashEmpty Specifies the empty check value This parameter can be one of the following values:
  • FLASH_PROG_NOT_EMPTY 1st location in Flash is programmed
  • FLASH_PROG_EMPTY 1st location in Flash is empty
Return values:
None

Definition at line 445 of file stm32wbxx_hal_flash_ex.c.

References assert_param, and IS_FLASH_EMPTY_CHECK.

uint32_t HAL_FLASHEx_IsOperationSuspended ( void )

Check if new program or erase operation request from CPU1 or CPU2 is suspended.

Note:
Any new Flash program and erase operation on both CPU side will be allowed until one of this bit or the same bit in Flash CPU2 access control register (FLASH_C2ACR) is set. The PESD bit in both the Flash status register (FLASH_SR) and Flash CPU2 status register (FLASH_C2SR) register will be cleared when both PES bit in FLASH_ACR and FLASH_C2ACR are cleared.
Return values:
Status
  • 0 : No suspended flash operation
  • 1 : Flash operation is suspended

Definition at line 491 of file stm32wbxx_hal_flash_ex.c.

void HAL_FLASHEx_OBGetConfig ( FLASH_OBProgramInitTypeDef * pOBInit )

Get the Option bytes configuration.

Note:
warning: this API only read flash register, it does not reflect any change that would have been programmed between previous Option byte loading and current call.
Parameters:
pOBInit Pointer to an FLASH_OBProgramInitTypeDef structure that contains the configuration information. The fields pOBInit->WRPArea and pOBInit->PCROPConfig should indicate which area is requested for the WRP and PCROP.
Return values:
None

Definition at line 389 of file stm32wbxx_hal_flash_ex.c.

References FLASH_OBProgramInitTypeDef::C2BootRegion, FLASH_OBProgramInitTypeDef::C2SecureBootVectAddr, FLASH_OB_GetC2BootResetConfig(), FLASH_OB_GetIPCCBufferAddr(), FLASH_OB_GetPCROP(), FLASH_OB_GetRDP(), FLASH_OB_GetSecureMemoryConfig(), FLASH_OB_GetUser(), FLASH_OB_GetWRP(), FLASH_OBProgramInitTypeDef::IPCCdataBufAddr, OB_PCROP_ZONE_A, OB_PCROP_ZONE_B, OB_USER_ALL, OB_WRPAREA_BANK1_AREAA, OB_WRPAREA_BANK1_AREAB, OPTIONBYTE_ALL, FLASH_OBProgramInitTypeDef::OptionType, FLASH_OBProgramInitTypeDef::PCROP1AEndAddr, FLASH_OBProgramInitTypeDef::PCROP1AStartAddr, FLASH_OBProgramInitTypeDef::PCROP1BEndAddr, FLASH_OBProgramInitTypeDef::PCROP1BStartAddr, FLASH_OBProgramInitTypeDef::PCROPConfig, FLASH_OBProgramInitTypeDef::RDPLevel, FLASH_OBProgramInitTypeDef::SecureFlashStartAddr, FLASH_OBProgramInitTypeDef::SecureMode, FLASH_OBProgramInitTypeDef::SecureRAM2aStartAddr, FLASH_OBProgramInitTypeDef::SecureRAM2bStartAddr, FLASH_OBProgramInitTypeDef::UserConfig, FLASH_OBProgramInitTypeDef::UserType, FLASH_OBProgramInitTypeDef::WRPArea, FLASH_OBProgramInitTypeDef::WRPEndOffset, and FLASH_OBProgramInitTypeDef::WRPStartOffset.

HAL_StatusTypeDef HAL_FLASHEx_OBProgram ( FLASH_OBProgramInitTypeDef * pOBInit )

Program Option bytes.

Parameters:
pOBInit Pointer to an FLASH_OBProgramInitTypeDef structure that contains the configuration information for the programming.
Note:
To configure any option bytes, the option lock bit OPTLOCK must be cleared with the call of HAL_FLASH_OB_Unlock() function.
New option bytes configuration will be taken into account only
  • after an option bytes launch through the call of HAL_FLASH_OB_Launch()
  • a Power On Reset
  • an exit from Standby or Shutdown mode.
Return values:
HAL Status

Definition at line 288 of file stm32wbxx_hal_flash_ex.c.

References assert_param, FLASH_ProcessTypeDef::ErrorCode, FLASH_OB_GetRDP(), FLASH_OB_GetUser(), FLASH_OB_IPCCBufferAddrConfig(), FLASH_OB_OptrConfig(), FLASH_OB_PCROP1AConfig(), FLASH_OB_PCROP1BConfig(), FLASH_OB_ProceedWriteOperation(), FLASH_OB_SecureConfig(), FLASH_OB_WRPConfig(), HAL_FLASH_ERROR_NONE, FLASH_OBProgramInitTypeDef::IPCCdataBufAddr, IS_OB_PCROP_CONFIG, IS_OPTIONBYTE, OB_PCROP_RDP_ERASE, OB_PCROP_ZONE_A, OB_PCROP_ZONE_B, OB_USER_BOR_LEV, OPTIONBYTE_C2_BOOT_VECT, OPTIONBYTE_IPCC_BUF_ADDR, OPTIONBYTE_PCROP, OPTIONBYTE_RDP, OPTIONBYTE_SECURE_MODE, OPTIONBYTE_USER, OPTIONBYTE_WRP, FLASH_OBProgramInitTypeDef::OptionType, FLASH_OBProgramInitTypeDef::PCROP1AEndAddr, FLASH_OBProgramInitTypeDef::PCROP1AStartAddr, FLASH_OBProgramInitTypeDef::PCROP1BEndAddr, FLASH_OBProgramInitTypeDef::PCROP1BStartAddr, FLASH_OBProgramInitTypeDef::PCROPConfig, pFlash, FLASH_OBProgramInitTypeDef::RDPLevel, FLASH_OBProgramInitTypeDef::UserConfig, FLASH_OBProgramInitTypeDef::UserType, FLASH_OBProgramInitTypeDef::WRPArea, FLASH_OBProgramInitTypeDef::WRPEndOffset, and FLASH_OBProgramInitTypeDef::WRPStartOffset.

void HAL_FLASHEx_SuspendOperation ( void )

Suspend new program or erase operation request.

Note:
Any new Flash program and erase operation on both CPU side will be suspended until this bit and the same bit in Flash CPU2 access control register (FLASH_C2ACR) are cleared. The PESD bit in both the Flash status register (FLASH_SR) and Flash CPU2 status register (FLASH_C2SR) register will be set when at least one PES bit in FLASH_ACR or FLASH_C2ACR is set.
Return values:
None

Definition at line 461 of file stm32wbxx_hal_flash_ex.c.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FLASHEx Empty Check

Defines
FLASHEx Empty Check
FLASH Exported Constants

Defines

#define | FLASH_PROG_NOT_EMPTY 0x00000000U
#define | FLASH_PROG_EMPTY FLASH_ACR_EMPTY

Define Documentation

#define FLASH_PROG_EMPTY FLASH_ACR_EMPTY

1st location in Flash is empty

Definition at line 48 of file stm32wbxx_hal_flash_ex.h.

#define FLASH_PROG_NOT_EMPTY 0x00000000U

1st location in Flash is programmed

Definition at line 47 of file stm32wbxx_hal_flash_ex.h.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FLASHEx Private Macros

Defines
FLASHEx Private Macros
FLASHEx

Defines

#define IS_FLASH_EMPTY_CHECK(__VALUE__) (((__VALUE__) == FLASH_PROG_EMPTY) || ((__VALUE__) == FLASH_PROG_NOT_EMPTY))

Define Documentation

#define IS_FLASH_EMPTY_CHECK ( __VALUE__ ) (((__VALUE__) == FLASH_PROG_EMPTY) || ((__VALUE__) == FLASH_PROG_NOT_EMPTY))

Definition at line 87 of file stm32wbxx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_ForceFlashEmpty().

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STM32WB55xx HAL User Manual: GPIO Private Constants

Defines
GPIO Private Constants
GPIO

MISRA C:2012 deviation rule has been granted for following rules: Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of range of the shift operator in following API : HAL_GPIO_Init HAL_GPIO_DeInit. More...

Defines

#define | GPIO_MODE (0x00000003u)
#define | EXTI_MODE (0x10000000u)
#define | GPIO_MODE_IT (0x00010000u)
#define | GPIO_MODE_EVT (0x00020000u)
#define | RISING_EDGE (0x00100000u)
#define | FALLING_EDGE (0x00200000u)
#define | GPIO_OUTPUT_TYPE (0x00000010u)
#define | GPIO_NUMBER (16u)

Detailed Description

MISRA C:2012 deviation rule has been granted for following rules: Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of range of the shift operator in following API : HAL_GPIO_Init HAL_GPIO_DeInit.

Define Documentation

#define EXTI_MODE (0x10000000u)

Definition at line 130 of file stm32wbxx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define FALLING_EDGE (0x00200000u)

Definition at line 134 of file stm32wbxx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE (0x00000003u)

Definition at line 129 of file stm32wbxx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_EVT (0x00020000u)

Definition at line 132 of file stm32wbxx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_IT (0x00010000u)

Definition at line 131 of file stm32wbxx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_NUMBER (16u)

Definition at line 137 of file stm32wbxx_hal_gpio.c.

#define GPIO_OUTPUT_TYPE (0x00000010u)

Definition at line 135 of file stm32wbxx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define RISING_EDGE (0x00100000u)

Definition at line 133 of file stm32wbxx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

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STM32WB55xx HAL User Manual: GPIO Exported Types

Data Structures | Enumerations
GPIO Exported Types
GPIO

Data Structures

struct | GPIO_InitTypeDef
GPIO Init structure definition. More...

Enumerations

enum | GPIO_PinState { GPIO_PIN_RESET = 0U, GPIO_PIN_SET }
GPIO Bit SET and Bit RESET enumeration. More...

Enumeration Type Documentation

enum GPIO_PinState

GPIO Bit SET and Bit RESET enumeration.

Enumerator:
GPIO_PIN_RESET
GPIO_PIN_SET

Definition at line 69 of file stm32wbxx_hal_gpio.h.

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STM32WB55xx HAL User Manual: GPIO_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
GPIO_InitTypeDef Struct Reference
GPIO Exported Types

GPIO Init structure definition. More...

#include <stm32wbxx_hal_gpio.h>

Data Fields

uint32_t | Pin
uint32_t | Mode
uint32_t | Pull
uint32_t | Speed
uint32_t | Alternate

Detailed Description

GPIO Init structure definition.

Definition at line 48 of file stm32wbxx_hal_gpio.h.

Field Documentation

uint32_t GPIO_InitTypeDef::Alternate

Peripheral to be connected to the selected pins This parameter can be a value of GPIOEx Alternate function selection

Definition at line 62 of file stm32wbxx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), HAL_RCC_MCOConfig(), HAL_RCCEx_EnableLSCO(), and HAL_RCCEx_LSCOConfig().

uint32_t GPIO_InitTypeDef::Mode

Specifies the operating mode for the selected pins. This parameter can be a value of GPIO mode

Definition at line 53 of file stm32wbxx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), HAL_RCC_MCOConfig(), HAL_RCCEx_EnableLSCO(), and HAL_RCCEx_LSCOConfig().

uint32_t GPIO_InitTypeDef::Pin

Specifies the GPIO pins to be configured. This parameter can be any value of GPIO pins

Definition at line 50 of file stm32wbxx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), HAL_RCC_MCOConfig(), HAL_RCCEx_EnableLSCO(), and HAL_RCCEx_LSCOConfig().

uint32_t GPIO_InitTypeDef::Pull

Specifies the Pull-up or Pull-Down activation for the selected pins. This parameter can be a value of GPIO pull

Definition at line 56 of file stm32wbxx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), HAL_RCC_MCOConfig(), HAL_RCCEx_EnableLSCO(), and HAL_RCCEx_LSCOConfig().

uint32_t GPIO_InitTypeDef::Speed

Specifies the speed for the selected pins. This parameter can be a value of GPIO speed

Definition at line 59 of file stm32wbxx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), HAL_RCC_MCOConfig(), HAL_RCCEx_EnableLSCO(), and HAL_RCCEx_LSCOConfig().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_gpio.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: GPIO pins

Defines
GPIO pins
GPIO Exported Constants

Defines

#define | GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
#define | GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
#define | GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
#define | GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
#define | GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
#define | GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
#define | GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
#define | GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
#define | GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
#define | GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
#define | GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
#define | GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
#define | GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
#define | GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
#define | GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
#define | GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
#define | GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
#define | GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */

Define Documentation

#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */

Definition at line 85 of file stm32wbxx_hal_gpio.h.

#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */

Definition at line 86 of file stm32wbxx_hal_gpio.h.

#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */

Definition at line 95 of file stm32wbxx_hal_gpio.h.

#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */

Definition at line 96 of file stm32wbxx_hal_gpio.h.

#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */

Definition at line 97 of file stm32wbxx_hal_gpio.h.

#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */

Definition at line 98 of file stm32wbxx_hal_gpio.h.

#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */

Definition at line 99 of file stm32wbxx_hal_gpio.h.

#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */

Definition at line 100 of file stm32wbxx_hal_gpio.h.

#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */

Definition at line 87 of file stm32wbxx_hal_gpio.h.

#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */

Definition at line 88 of file stm32wbxx_hal_gpio.h.

#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */

Definition at line 89 of file stm32wbxx_hal_gpio.h.

#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */

Definition at line 90 of file stm32wbxx_hal_gpio.h.

#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */

Definition at line 91 of file stm32wbxx_hal_gpio.h.

#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */

Definition at line 92 of file stm32wbxx_hal_gpio.h.

#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */

Definition at line 93 of file stm32wbxx_hal_gpio.h.

#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */

Definition at line 94 of file stm32wbxx_hal_gpio.h.

#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */

Definition at line 101 of file stm32wbxx_hal_gpio.h.

#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */

Definition at line 103 of file stm32wbxx_hal_gpio.h.

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STM32WB55xx HAL User Manual: GPIO mode

Defines
GPIO mode
GPIO Exported Constants

GPIO Configuration Mode Elements values convention: 0xX0yz00YZ. More...

Defines

#define | GPIO_MODE_INPUT (0x00000000u)
#define | GPIO_MODE_OUTPUT_PP (0x00000001u)
#define | GPIO_MODE_OUTPUT_OD (0x00000011u)
#define | GPIO_MODE_AF_PP (0x00000002u)
#define | GPIO_MODE_AF_OD (0x00000012u)
#define | GPIO_MODE_ANALOG (0x00000003u)
#define | GPIO_MODE_IT_RISING (0x10110000u)
#define | GPIO_MODE_IT_FALLING (0x10210000u)
#define | GPIO_MODE_IT_RISING_FALLING (0x10310000u)
#define | GPIO_MODE_EVT_RISING (0x10120000u)
#define | GPIO_MODE_EVT_FALLING (0x10220000u)
#define | GPIO_MODE_EVT_RISING_FALLING (0x10320000u)

Detailed Description

GPIO Configuration Mode Elements values convention: 0xX0yz00YZ.

  • X : GPIO mode or EXTI Mode
  • y : External IT or Event trigger detection
  • z : IO configuration on External IT or Event
  • Y : Output type (Push Pull or Open Drain)
  • Z : IO Direction mode (Input, Output, Alternate or Analog)

Define Documentation

#define GPIO_MODE_AF_OD (0x00000012u)

Alternate Function Open Drain Mode

Definition at line 122 of file stm32wbxx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_AF_PP (0x00000002u)

Alternate Function Push Pull Mode

Definition at line 121 of file stm32wbxx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), HAL_RCC_MCOConfig(), HAL_RCCEx_EnableLSCO(), and HAL_RCCEx_LSCOConfig().

#define GPIO_MODE_ANALOG (0x00000003u)

Analog Mode

Definition at line 123 of file stm32wbxx_hal_gpio.h.

#define GPIO_MODE_EVT_FALLING (0x10220000u)

External Event Mode with Falling edge trigger detection

Definition at line 128 of file stm32wbxx_hal_gpio.h.

#define GPIO_MODE_EVT_RISING (0x10120000u)

External Event Mode with Rising edge trigger detection

Definition at line 127 of file stm32wbxx_hal_gpio.h.

#define GPIO_MODE_EVT_RISING_FALLING (0x10320000u)

External Event Mode with Rising/Falling edge trigger detection

Definition at line 129 of file stm32wbxx_hal_gpio.h.

#define GPIO_MODE_INPUT (0x00000000u)

Input Floating Mode

Definition at line 118 of file stm32wbxx_hal_gpio.h.

#define GPIO_MODE_IT_FALLING (0x10210000u)

External Interrupt Mode with Falling edge trigger detection

Definition at line 125 of file stm32wbxx_hal_gpio.h.

#define GPIO_MODE_IT_RISING (0x10110000u)

External Interrupt Mode with Rising edge trigger detection

Definition at line 124 of file stm32wbxx_hal_gpio.h.

#define GPIO_MODE_IT_RISING_FALLING (0x10310000u)

External Interrupt Mode with Rising/Falling edge trigger detection

Definition at line 126 of file stm32wbxx_hal_gpio.h.

#define GPIO_MODE_OUTPUT_OD (0x00000011u)

Output Open Drain Mode

Definition at line 120 of file stm32wbxx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_OUTPUT_PP (0x00000001u)

Output Push Pull Mode

Definition at line 119 of file stm32wbxx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: GPIO speed

Defines
GPIO speed
GPIO Exported Constants

GPIO Output Maximum frequency. More...

Defines

#define | GPIO_SPEED_FREQ_LOW (0x00000000u)
#define | GPIO_SPEED_FREQ_MEDIUM (0x00000001u)
#define | GPIO_SPEED_FREQ_HIGH (0x00000002u)
#define | GPIO_SPEED_FREQ_VERY_HIGH (0x00000003u)

Detailed Description

GPIO Output Maximum frequency.

Define Documentation

#define GPIO_SPEED_FREQ_HIGH (0x00000002u)

High speed

Definition at line 140 of file stm32wbxx_hal_gpio.h.

#define GPIO_SPEED_FREQ_LOW (0x00000000u)

Low speed

Definition at line 138 of file stm32wbxx_hal_gpio.h.

#define GPIO_SPEED_FREQ_MEDIUM (0x00000001u)

Medium speed

Definition at line 139 of file stm32wbxx_hal_gpio.h.

#define GPIO_SPEED_FREQ_VERY_HIGH (0x00000003u)

Very high speed

Definition at line 141 of file stm32wbxx_hal_gpio.h.

Referenced by HAL_RCC_MCOConfig(), HAL_RCCEx_EnableLSCO(), and HAL_RCCEx_LSCOConfig().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: GPIO pull

Defines
GPIO pull
GPIO Exported Constants

GPIO Pull-Up or Pull-Down Activation. More...

Defines

#define | GPIO_NOPULL (0x00000000u)
#define | GPIO_PULLUP (0x00000001u)
#define | GPIO_PULLDOWN (0x00000002u)

Detailed Description

GPIO Pull-Up or Pull-Down Activation.

Define Documentation

#define GPIO_NOPULL (0x00000000u)

No Pull-up or Pull-down activation

Definition at line 150 of file stm32wbxx_hal_gpio.h.

Referenced by HAL_RCC_MCOConfig(), HAL_RCCEx_EnableLSCO(), and HAL_RCCEx_LSCOConfig().

#define GPIO_PULLDOWN (0x00000002u)

Pull-down activation

Definition at line 152 of file stm32wbxx_hal_gpio.h.

#define GPIO_PULLUP (0x00000001u)

Pull-up activation

Definition at line 151 of file stm32wbxx_hal_gpio.h.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: GPIO Exported Macros

Defines
GPIO Exported Macros
GPIO

Defines

#define | __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
Check whether the specified EXTI line flag is set or not.
#define | __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
Clear the EXTI's line pending flags.
#define | __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
Check whether the specified EXTI line is asserted or not.
#define | __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
Clear the EXTI's line pending bits.
#define | __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__))
Generate a Software interrupt on selected EXTI line.

Define Documentation

#define __HAL_GPIO_EXTI_CLEAR_FLAG ( __EXTI_LINE__ ) (EXTI->PR1 = (__EXTI_LINE__))

Clear the EXTI's line pending flags.

Parameters:
__EXTI_LINE__ specifies the EXTI lines flags to clear. This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
Return values:
None

Definition at line 180 of file stm32wbxx_hal_gpio.h.

#define __HAL_GPIO_EXTI_CLEAR_IT ( __EXTI_LINE__ ) (EXTI->PR1 = (__EXTI_LINE__))

Clear the EXTI's line pending bits.

Parameters:
__EXTI_LINE__ specifies the EXTI lines to clear. This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
Return values:
None

Definition at line 196 of file stm32wbxx_hal_gpio.h.

Referenced by HAL_GPIO_EXTI_IRQHandler().

#define __HAL_GPIO_EXTI_GENERATE_SWIT ( __EXTI_LINE__ ) (EXTI->SWIER1 |= (__EXTI_LINE__))

Generate a Software interrupt on selected EXTI line.

Parameters:
__EXTI_LINE__ specifies the EXTI line to check. This parameter can be GPIO_PIN_x where x can be(0..15)
Return values:
None

Definition at line 204 of file stm32wbxx_hal_gpio.h.

#define __HAL_GPIO_EXTI_GET_FLAG ( __EXTI_LINE__ ) (EXTI->PR1 & (__EXTI_LINE__))

Check whether the specified EXTI line flag is set or not.

Parameters:
__EXTI_LINE__ specifies the EXTI line flag to check. This parameter can be GPIO_PIN_x where x can be(0..15)
Return values:
The new state of __EXTI_LINE__ (SET or RESET).

Definition at line 172 of file stm32wbxx_hal_gpio.h.

#define __HAL_GPIO_EXTI_GET_IT ( __EXTI_LINE__ ) (EXTI->PR1 & (__EXTI_LINE__))

Check whether the specified EXTI line is asserted or not.

Parameters:
__EXTI_LINE__ specifies the EXTI line to check. This parameter can be GPIO_PIN_x where x can be(0..15)
Return values:
The new state of __EXTI_LINE__ (SET or RESET).

Definition at line 188 of file stm32wbxx_hal_gpio.h.

Referenced by HAL_GPIO_EXTI_IRQHandler().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: GPIO Private Macros

Defines
GPIO Private Macros
GPIO

Defines

#define | IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define | IS_GPIO_PIN(__PIN__)
#define | IS_GPIO_MODE(__MODE__)
#define | IS_GPIO_SPEED(__SPEED__)
#define | IS_GPIO_PULL(__PULL__)

Define Documentation

#define IS_GPIO_MODE ( __MODE__ )
Value:
(((__MODE__) == GPIO_MODE_INPUT)              ||\
                                     ((__MODE__) == GPIO_MODE_OUTPUT_PP)          ||\
                                     ((__MODE__) == GPIO_MODE_OUTPUT_OD)          ||\
                                     ((__MODE__) == GPIO_MODE_AF_PP)              ||\
                                     ((__MODE__) == GPIO_MODE_AF_OD)              ||\
                                     ((__MODE__) == GPIO_MODE_IT_RISING)          ||\
                                     ((__MODE__) == GPIO_MODE_IT_FALLING)         ||\
                                     ((__MODE__) == GPIO_MODE_IT_RISING_FALLING)  ||\
                                     ((__MODE__) == GPIO_MODE_EVT_RISING)         ||\
                                     ((__MODE__) == GPIO_MODE_EVT_FALLING)        ||\
                                     ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
                                     ((__MODE__) == GPIO_MODE_ANALOG))

Definition at line 219 of file stm32wbxx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define IS_GPIO_PIN ( __PIN__ )
Value:
((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00u) &&\
                                     (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00u))

Definition at line 216 of file stm32wbxx_hal_gpio.h.

Referenced by HAL_GPIO_DeInit(), HAL_GPIO_Init(), HAL_GPIO_LockPin(), HAL_GPIO_ReadPin(), HAL_GPIO_TogglePin(), and HAL_GPIO_WritePin().

#define IS_GPIO_PIN_ACTION ( ACTION ) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))

Definition at line 214 of file stm32wbxx_hal_gpio.h.

Referenced by HAL_GPIO_WritePin().

#define IS_GPIO_PULL ( __PULL__ )
Value:
(((__PULL__) == GPIO_NOPULL)   ||\
                                     ((__PULL__) == GPIO_PULLUP)   || \
                                     ((__PULL__) == GPIO_PULLDOWN))

Definition at line 237 of file stm32wbxx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define IS_GPIO_SPEED ( __SPEED__ )
Value:
(((__SPEED__) == GPIO_SPEED_FREQ_LOW)       ||\
                                     ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM)    ||\
                                     ((__SPEED__) == GPIO_SPEED_FREQ_HIGH)      ||\
                                     ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH))

Definition at line 232 of file stm32wbxx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization/de-initialization functions

Functions
Initialization/de-initialization functions
GPIO Exported Functions

Initialization and Configuration functions. More...

Functions

void | HAL_GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
void | HAL_GPIO_DeInit (GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
De-initialize the GPIOx peripheral registers to their default reset values.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================

Function Documentation

void HAL_GPIO_DeInit | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | GPIO_Pin
 | ) |  |

De-initialize the GPIOx peripheral registers to their default reset values.

Parameters:
GPIOx | where x can be (A..H) to select the GPIO peripheral for STM32WBxx family
GPIO_Pin | specifies the port bit to be written. This parameter can be one of GPIO_PIN_x where x can be (0..15).
Return values:
None

Definition at line 292 of file stm32wbxx_hal_gpio.c.

References assert_param, GPIO_GET_INDEX, and IS_GPIO_PIN.

void HAL_GPIO_Init | ( | GPIO_TypeDef * | GPIOx,
 |  | GPIO_InitTypeDef * | GPIO_Init
 | ) |  |

Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.

Parameters:
GPIOx | where x can be (A..H) to select the GPIO peripheral for STM32WBxx family
GPIO_Init | pointer to a GPIO_InitTypeDef structure that contains the configuration information for the specified GPIO peripheral.
Return values:
None

Definition at line 170 of file stm32wbxx_hal_gpio.c.

References GPIO_InitTypeDef::Alternate, assert_param, EXTI_MODE, FALLING_EDGE, GPIO_GET_INDEX, GPIO_MODE, GPIO_MODE_AF_OD, GPIO_MODE_AF_PP, GPIO_MODE_EVT, GPIO_MODE_IT, GPIO_MODE_OUTPUT_OD, GPIO_MODE_OUTPUT_PP, GPIO_OUTPUT_TYPE, IS_GPIO_AF, IS_GPIO_MODE, IS_GPIO_PIN, IS_GPIO_PULL, IS_GPIO_SPEED, GPIO_InitTypeDef::Mode, GPIO_InitTypeDef::Pin, GPIO_InitTypeDef::Pull, RISING_EDGE, and GPIO_InitTypeDef::Speed.

Referenced by HAL_RCC_MCOConfig(), HAL_RCCEx_EnableLSCO(), and HAL_RCCEx_LSCOConfig().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IO operation functions

Functions
IO operation functions
GPIO Exported Functions

IO operation functions. More...

Functions

GPIO_PinState | HAL_GPIO_ReadPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Read the specified input port pin.
void | HAL_GPIO_WritePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
Set or clear the selected data port bit.
void | HAL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Toggle the specified GPIO pin.
HAL_StatusTypeDef | HAL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Lock GPIO Pins configuration registers.
void | HAL_GPIO_EXTI_IRQHandler (uint16_t GPIO_Pin)
Handle EXTI interrupt request.
__weak void | HAL_GPIO_EXTI_Callback (uint16_t GPIO_Pin)
EXTI line detection callback.

Detailed Description

IO operation functions.

GPIO Read, Write, Toggle, Lock and EXTI management functions.

 ===============================================================================
                       ##### IO operation functions #####
 ===============================================================================

Function Documentation

void HAL_GPIO_EXTI_Callback ( uint16_t GPIO_Pin )

EXTI line detection callback.

Parameters:
GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
Return values:
None

Definition at line 505 of file stm32wbxx_hal_gpio.c.

Referenced by HAL_GPIO_EXTI_IRQHandler().

void HAL_GPIO_EXTI_IRQHandler ( uint16_t GPIO_Pin )

Handle EXTI interrupt request.

Parameters:
GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
Return values:
None

Definition at line 490 of file stm32wbxx_hal_gpio.c.

References __HAL_GPIO_EXTI_CLEAR_IT, __HAL_GPIO_EXTI_GET_IT, and HAL_GPIO_EXTI_Callback().

HAL_StatusTypeDef HAL_GPIO_LockPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Lock GPIO Pins configuration registers.

Note:
The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
The configuration of the locked GPIO pins can no longer be modified until the next reset.
Parameters:
GPIOx | where x can be (A..H) to select the GPIO peripheral for STM32WBxx family
GPIO_Pin | specifies the port bits to be locked. This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
Return values:
None

Definition at line 455 of file stm32wbxx_hal_gpio.c.

References assert_param, and IS_GPIO_PIN.

GPIO_PinState HAL_GPIO_ReadPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Read the specified input port pin.

Parameters:
GPIOx | where x can be (A..F) to select the GPIO peripheral for STM32WBxx family
GPIO_Pin | specifies the port bit to read. This parameter can be GPIO_PIN_x where x can be (0..15).
Return values:
The input port pin value.

Definition at line 373 of file stm32wbxx_hal_gpio.c.

References assert_param, GPIO_PIN_RESET, GPIO_PIN_SET, and IS_GPIO_PIN.

void HAL_GPIO_TogglePin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Toggle the specified GPIO pin.

Parameters:
GPIOx | where x can be (A..H) to select the GPIO peripheral for STM32WBxx family
GPIO_Pin | specifies the pin to be toggled.
Return values:
None

Definition at line 429 of file stm32wbxx_hal_gpio.c.

References assert_param, and IS_GPIO_PIN.

void HAL_GPIO_WritePin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin,
 |  | GPIO_PinState | PinState
 | ) |  |

Set or clear the selected data port bit.

Note:
This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify accesses. In this way, there is no risk of an IRQ occurring between the read and the modify access.
Parameters:
GPIOx | where x can be (A..F) to select the GPIO peripheral for STM32WBxx family
GPIO_Pin | specifies the port bit to be written. This parameter can be one of GPIO_PIN_x where x can be (0..15).
PinState specifies the value to be written to the selected bit. This parameter can be one of the GPIO_PinState enum values:
  • GPIO_PIN_RESET: to clear the port pin
  • GPIO_PIN_SET: to set the port pin
Return values:
None

Definition at line 407 of file stm32wbxx_hal_gpio.c.

References assert_param, GPIO_PIN_RESET, IS_GPIO_PIN, and IS_GPIO_PIN_ACTION.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: GPIOEx Alternate function selection

Defines
GPIOEx Alternate function selection
GPIOEx Exported Constants

Defines

#define | GPIO_AF0_MCO ((uint8_t)0x00)
AF 0 selection.
#define | GPIO_AF0_LSCO ((uint8_t)0x00)
#define | GPIO_AF0_JTMS_SWDIO ((uint8_t)0x00)
#define | GPIO_AF0_JTCK_SWCLK ((uint8_t)0x00)
#define | GPIO_AF0_JTDI ((uint8_t)0x00)
#define | GPIO_AF0_RTC_OUT ((uint8_t)0x00)
#define | GPIO_AF0_JTD_TRACE ((uint8_t)0x00)
#define | GPIO_AF0_NJTRST ((uint8_t)0x00)
#define | GPIO_AF0_RTC_REFIN ((uint8_t)0x00)
#define | GPIO_AF0_TRACED0 ((uint8_t)0x00)
#define | GPIO_AF0_TRACED1 ((uint8_t)0x00)
#define | GPIO_AF0_TRACED2 ((uint8_t)0x00)
#define | GPIO_AF0_TRACED3 ((uint8_t)0x00)
#define | GPIO_AF0_TRIG_INOUT ((uint8_t)0x00)
#define | GPIO_AF0_TRACECK ((uint8_t)0x00)
#define | GPIO_AF0_SYS ((uint8_t)0x00)
#define | GPIO_AF1_TIM1 ((uint8_t)0x01)
AF 1 selection.
#define | GPIO_AF1_TIM2 ((uint8_t)0x01)
#define | GPIO_AF1_LPTIM1 ((uint8_t)0x01)
#define | GPIO_AF2_TIM2 ((uint8_t)0x02)
AF 2 selection.
#define | GPIO_AF2_TIM1 ((uint8_t)0x02)
#define | GPIO_AF3_SAI1 ((uint8_t)0x03)
AF 3 selection.
#define | GPIO_AF3_SPI2 ((uint8_t)0x03)
#define | GPIO_AF3_TIM1 ((uint8_t)0x03)
#define | GPIO_AF4_I2C1 ((uint8_t)0x04)
AF 4 selection.
#define | GPIO_AF4_I2C3 ((uint8_t)0x04)
#define | GPIO_AF5_SPI1 ((uint8_t)0x05)
AF 5 selection.
#define | GPIO_AF5_SPI2 ((uint8_t)0x05)
#define | GPIO_AF6_MCO ((uint8_t)0x06)
AF 6 selection.
#define | GPIO_AF6_LSCO ((uint8_t)0x06)
#define | GPIO_AF6_RF_DTB0 ((uint8_t)0x06)
#define | GPIO_AF6_RF_DTB1 ((uint8_t)0x06)
#define | GPIO_AF6_RF_DTB2 ((uint8_t)0x06)
#define | GPIO_AF6_RF_DTB3 ((uint8_t)0x06)
#define | GPIO_AF6_RF_DTB4 ((uint8_t)0x06)
#define | GPIO_AF6_RF_DTB5 ((uint8_t)0x06)
#define | GPIO_AF6_RF_DTB6 ((uint8_t)0x06)
#define | GPIO_AF6_RF_DTB7 ((uint8_t)0x06)
#define | GPIO_AF6_RF_DTB8 ((uint8_t)0x06)
#define | GPIO_AF6_RF_DTB9 ((uint8_t)0x06)
#define | GPIO_AF6_RF_DTB10 ((uint8_t)0x06)
#define | GPIO_AF6_RF_DTB11 ((uint8_t)0x06)
#define | GPIO_AF6_RF_DTB12 ((uint8_t)0x06)
#define | GPIO_AF6_RF_DTB13 ((uint8_t)0x06)
#define | GPIO_AF6_RF_DTB14 ((uint8_t)0x06)
#define | GPIO_AF6_RF_DTB15 ((uint8_t)0x06)
#define | GPIO_AF6_RF_DTB16 ((uint8_t)0x06)
#define | GPIO_AF6_RF_DTB17 ((uint8_t)0x06)
#define | GPIO_AF6_RF_DTB18 ((uint8_t)0x06)
#define | GPIO_AF6_RF_MISO ((uint8_t)0x06)
#define | GPIO_AF6_RF_MOSI ((uint8_t)0x06)
#define | GPIO_AF6_RF_SCK ((uint8_t)0x06)
#define | GPIO_AF6_RF_NSS ((uint8_t)0x06)
#define | GPIO_AF7_USART1 ((uint8_t)0x07)
AF 7 selection.
#define | GPIO_AF8_LPUART1 ((uint8_t)0x08)
AF 8 selection.
#define | GPIO_AF8_IR ((uint8_t)0x08)
#define | GPIO_AF9_TSC ((uint8_t)0x09)
AF 9 selection.
#define | GPIO_AF10_QUADSPI ((uint8_t)0x0a)
AF 10 selection.
#define | GPIO_AF10_USB ((uint8_t)0x0a)
#define | GPIO_AF11_LCD ((uint8_t)0x0b)
AF 11 selection.
#define | GPIO_AF12_COMP1 ((uint8_t)0x0c)
AF 12 selection.
#define | GPIO_AF12_COMP2 ((uint8_t)0x0c)
#define | GPIO_AF12_TIM1 ((uint8_t)0x0c)
#define | GPIO_AF13_SAI1 ((uint8_t)0x0d)
AF 13 selection.
#define | GPIO_AF14_TIM2 ((uint8_t)0x0e)
AF 14 selection.
#define | GPIO_AF14_TIM16 ((uint8_t)0x0e)
#define | GPIO_AF14_TIM17 ((uint8_t)0x0e)
#define | GPIO_AF14_LPTIM2 ((uint8_t)0x0e)
#define | GPIO_AF15_EVENTOUT ((uint8_t)0x0f)
AF 15 selection.
#define | IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0f)

Define Documentation

#define GPIO_AF0_JTCK_SWCLK ((uint8_t)0x00)

JTCK-SWCLK Alternate Function mapping

Definition at line 234 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF0_JTD_TRACE ((uint8_t)0x00)

JTDO-TRACESWO Alternate Function mapping

Definition at line 237 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF0_JTDI ((uint8_t)0x00)

JTDI Alternate Function mapping

Definition at line 235 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF0_JTMS_SWDIO ((uint8_t)0x00)

JTMS-SWDIO Alternate Function mapping

Definition at line 233 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF0_LSCO ((uint8_t)0x00)

LSCO Alternate Function mapping

Definition at line 232 of file stm32wbxx_hal_gpio_ex.h.

Referenced by HAL_RCCEx_EnableLSCO(), and HAL_RCCEx_LSCOConfig().

#define GPIO_AF0_MCO ((uint8_t)0x00)

AF 0 selection.

MCO Alternate Function mapping

Definition at line 231 of file stm32wbxx_hal_gpio_ex.h.

Referenced by HAL_RCC_MCOConfig().

#define GPIO_AF0_NJTRST ((uint8_t)0x00)

NJTRST Alternate Function mapping

Definition at line 238 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF0_RTC_OUT ((uint8_t)0x00)

RCT_OUT Alternate Function mapping

Definition at line 236 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF0_RTC_REFIN ((uint8_t)0x00)

RTC_REFIN Alternate Function mapping

Definition at line 239 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF0_SYS ((uint8_t)0x00)

System Function mapping

Definition at line 246 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF0_TRACECK ((uint8_t)0x00)

TRACECK Alternate Function mapping

Definition at line 245 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF0_TRACED0 ((uint8_t)0x00)

TRACED0 Alternate Function mapping

Definition at line 240 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF0_TRACED1 ((uint8_t)0x00)

TRACED1 Alternate Function mapping

Definition at line 241 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF0_TRACED2 ((uint8_t)0x00)

TRACED2 Alternate Function mapping

Definition at line 242 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF0_TRACED3 ((uint8_t)0x00)

TRACED3 Alternate Function mapping

Definition at line 243 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF0_TRIG_INOUT ((uint8_t)0x00)

TRIG_INOUT Alternate Function mapping

Definition at line 244 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF10_QUADSPI ((uint8_t)0x0a)

AF 10 selection.

QUADSPI Alternate Function mapping

Definition at line 326 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF10_USB ((uint8_t)0x0a)

USB Alternate Function mapping

Definition at line 327 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF11_LCD ((uint8_t)0x0b)

AF 11 selection.

LCD Alternate Function mapping

Definition at line 332 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF12_COMP1 ((uint8_t)0x0c)

AF 12 selection.

COMP1 Alternate Function mapping

Definition at line 337 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF12_COMP2 ((uint8_t)0x0c)

COMP2 Alternate Function mapping

Definition at line 338 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF12_TIM1 ((uint8_t)0x0c)

TIM1 Alternate Function mapping

Definition at line 339 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF13_SAI1 ((uint8_t)0x0d)

AF 13 selection.

SAI1 Alternate Function mapping

Definition at line 344 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF14_LPTIM2 ((uint8_t)0x0e)

LPTIM2 Alternate Function mapping

Definition at line 352 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF14_TIM16 ((uint8_t)0x0e)

TIM16 Alternate Function mapping

Definition at line 350 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF14_TIM17 ((uint8_t)0x0e)

TIM17 Alternate Function mapping

Definition at line 351 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF14_TIM2 ((uint8_t)0x0e)

AF 14 selection.

TIM2 Alternate Function mapping

Definition at line 349 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF15_EVENTOUT ((uint8_t)0x0f)

AF 15 selection.

EVENTOUT Alternate Function mapping

Definition at line 359 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF1_LPTIM1 ((uint8_t)0x01)

LPTIM1 Alternate Function mapping

Definition at line 253 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF1_TIM1 ((uint8_t)0x01)

AF 1 selection.

TIM1 Alternate Function mapping

Definition at line 251 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF1_TIM2 ((uint8_t)0x01)

TIM2 Alternate Function mapping

Definition at line 252 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF2_TIM1 ((uint8_t)0x02)

TIM1 Alternate Function mapping

Definition at line 260 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF2_TIM2 ((uint8_t)0x02)

AF 2 selection.

TIM2 Alternate Function mapping

Definition at line 259 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF3_SAI1 ((uint8_t)0x03)

AF 3 selection.

SAI1_CK1 Alternate Function mapping

Definition at line 264 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF3_SPI2 ((uint8_t)0x03)

SPI2 Alternate Function mapping

Definition at line 265 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF3_TIM1 ((uint8_t)0x03)

TIM1 Alternate Function mapping

Definition at line 266 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF4_I2C1 ((uint8_t)0x04)

AF 4 selection.

I2C1 Alternate Function mapping

Definition at line 271 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF4_I2C3 ((uint8_t)0x04)

I2C3 Alternate Function mapping

Definition at line 272 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF5_SPI1 ((uint8_t)0x05)

AF 5 selection.

SPI1 Alternate Function mapping

Definition at line 277 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF5_SPI2 ((uint8_t)0x05)

SPI2 Alternate Function mapping

Definition at line 278 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF6_LSCO ((uint8_t)0x06)

LSCO Alternate Function mapping

Definition at line 283 of file stm32wbxx_hal_gpio_ex.h.

Referenced by HAL_RCCEx_LSCOConfig().

#define GPIO_AF6_MCO ((uint8_t)0x06)

AF 6 selection.

MCO Alternate Function mapping

Definition at line 282 of file stm32wbxx_hal_gpio_ex.h.

Referenced by HAL_RCC_MCOConfig().

#define GPIO_AF6_RF_DTB0 ((uint8_t)0x06)

RF_DTB0 Alternate Function mapping

Definition at line 284 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF6_RF_DTB1 ((uint8_t)0x06)

RF_DTB1 Alternate Function mapping

Definition at line 285 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF6_RF_DTB10 ((uint8_t)0x06)

RF_DTB10 Alternate Function mapping

Definition at line 294 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF6_RF_DTB11 ((uint8_t)0x06)

RF_DTB11 Alternate Function mapping

Definition at line 295 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF6_RF_DTB12 ((uint8_t)0x06)

RF_DTB12 Alternate Function mapping

Definition at line 296 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF6_RF_DTB13 ((uint8_t)0x06)

RF_DTB13 Alternate Function mapping

Definition at line 297 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF6_RF_DTB14 ((uint8_t)0x06)

RF_DTB14 Alternate Function mapping

Definition at line 298 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF6_RF_DTB15 ((uint8_t)0x06)

RF_DTB15 Alternate Function mapping

Definition at line 299 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF6_RF_DTB16 ((uint8_t)0x06)

RF_DTB16 Alternate Function mapping

Definition at line 300 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF6_RF_DTB17 ((uint8_t)0x06)

RF_DTB17 Alternate Function mapping

Definition at line 301 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF6_RF_DTB18 ((uint8_t)0x06)

RF_DTB18 Alternate Function mapping

Definition at line 302 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF6_RF_DTB2 ((uint8_t)0x06)

RF_DTB2 Alternate Function mapping

Definition at line 286 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF6_RF_DTB3 ((uint8_t)0x06)

RF_DTB3 Alternate Function mapping

Definition at line 287 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF6_RF_DTB4 ((uint8_t)0x06)

RF_DTB4 Alternate Function mapping

Definition at line 288 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF6_RF_DTB5 ((uint8_t)0x06)

RF_DTB5 Alternate Function mapping

Definition at line 289 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF6_RF_DTB6 ((uint8_t)0x06)

RF_DTB6 Alternate Function mapping

Definition at line 290 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF6_RF_DTB7 ((uint8_t)0x06)

RF_DTB7 Alternate Function mapping

Definition at line 291 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF6_RF_DTB8 ((uint8_t)0x06)

RF_DTB8 Alternate Function mapping

Definition at line 292 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF6_RF_DTB9 ((uint8_t)0x06)

RF_DTB9 Alternate Function mapping

Definition at line 293 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF6_RF_MISO ((uint8_t)0x06)

RF_MISO Alternate Function mapping

Definition at line 303 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF6_RF_MOSI ((uint8_t)0x06)

RF_MOSI Alternate Function mapping

Definition at line 304 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF6_RF_NSS ((uint8_t)0x06)

RF_NSS Alternate Function mapping

Definition at line 306 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF6_RF_SCK ((uint8_t)0x06)

RF_SCK Alternate Function mapping

Definition at line 305 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF7_USART1 ((uint8_t)0x07)

AF 7 selection.

USART1 Alternate Function mapping

Definition at line 310 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF8_IR ((uint8_t)0x08)

IR Alternate Function mapping

Definition at line 316 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF8_LPUART1 ((uint8_t)0x08)

AF 8 selection.

LPUART1 Alternate Function mapping

Definition at line 315 of file stm32wbxx_hal_gpio_ex.h.

#define GPIO_AF9_TSC ((uint8_t)0x09)

AF 9 selection.

TSC Alternate Function mapping

Definition at line 321 of file stm32wbxx_hal_gpio_ex.h.

#define IS_GPIO_AF ( AF ) ((AF) <= (uint8_t)0x0f)

Definition at line 361 of file stm32wbxx_hal_gpio_ex.h.

Referenced by HAL_GPIO_Init().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: GPIOEx Get Port Index

Defines
GPIOEx Get Port Index
GPIOEx Exported Macros

Defines

#define GPIO_GET_INDEX(__GPIOx__)

Define Documentation

#define GPIO_GET_INDEX ( __GPIOx__ )
Value:
(((__GPIOx__) == (GPIOA))? 0uL :\
                                      ((__GPIOx__) == (GPIOB))? 1uL :\
                                      ((__GPIOx__) == (GPIOC))? 2uL :\
                                      ((__GPIOx__) == (GPIOD))? 3uL :\
                                      ((__GPIOx__) == (GPIOE))? 4uL : 7uL)

Definition at line 384 of file stm32wbxx_hal_gpio_ex.h.

Referenced by HAL_GPIO_DeInit(), and HAL_GPIO_Init().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Take and Release functions

Functions
Take and Release functions
HSEM Exported Functions

HSEM Take and Release functions. More...

Functions

HAL_StatusTypeDef | HAL_HSEM_Take (uint32_t SemID, uint32_t ProcessID)
Take a semaphore in 2 Step mode.
HAL_StatusTypeDef | HAL_HSEM_FastTake (uint32_t SemID)
Fast Take a semaphore with 1 Step mode.
uint32_t | HAL_HSEM_IsSemTaken (uint32_t SemID)
Check semaphore state Taken or not.
void | HAL_HSEM_Release (uint32_t SemID, uint32_t ProcessID)
Release a semaphore.
void | HAL_HSEM_ReleaseAll (uint32_t Key, uint32_t CoreID)
Release All semaphore used by a given Master .

Detailed Description

HSEM Take and Release functions.

 ==============================================================================
              ##### HSEM Take and Release functions #####
 ==============================================================================
[..] This section provides functions allowing to:
      (+) Take a semaphore with 2 Step method
      (+) Fast Take a semaphore with 1 Step method
      (+) Check semaphore state Taken or not
      (+) Release a semaphore
      (+) Release all semaphore at once

Function Documentation

HAL_StatusTypeDef HAL_HSEM_FastTake ( uint32_t SemID )

Fast Take a semaphore with 1 Step mode.

Parameters:
SemID,: semaphore ID from 0 to 31
Return values:
HAL status

Definition at line 176 of file stm32wbxx_hal_hsem.c.

References assert_param, and IS_HSEM_SEMID.

uint32_t HAL_HSEM_IsSemTaken ( uint32_t SemID )

Check semaphore state Taken or not.

Parameters:
SemID,: semaphore ID
Return values:
HAL HSEM state

Definition at line 196 of file stm32wbxx_hal_hsem.c.

void HAL_HSEM_Release | ( | uint32_t | SemID,
 |  | uint32_t | ProcessID
 | ) |  |

Release a semaphore.

Parameters:
SemID,: semaphore ID from 0 to 31
ProcessID,: Process ID from 0 to 255
Return values:
None

Definition at line 208 of file stm32wbxx_hal_hsem.c.

References assert_param, IS_HSEM_PROCESSID, and IS_HSEM_SEMID.

void HAL_HSEM_ReleaseAll | ( | uint32_t | Key,
 |  | uint32_t | CoreID
 | ) |  |

Release All semaphore used by a given Master .

Parameters:
Key,: Semaphore Key , value from 0 to 0xFFFF
CoreID,: CoreID of the CPU that is using semaphores to be released
Return values:
None

Definition at line 225 of file stm32wbxx_hal_hsem.c.

References assert_param, IS_HSEM_COREID, and IS_HSEM_KEY.

HAL_StatusTypeDef HAL_HSEM_Take | ( | uint32_t | SemID,
 |  | uint32_t | ProcessID
 | ) |  |

Take a semaphore in 2 Step mode.

Parameters:
SemID,: semaphore ID from 0 to 31
ProcessID,: Process ID from 0 to 255
Return values:
HAL status

Definition at line 151 of file stm32wbxx_hal_hsem.c.

References assert_param, IS_HSEM_PROCESSID, and IS_HSEM_SEMID.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: HSEM Set and Get Key functions

Functions
HSEM Set and Get Key functions
HSEM Exported Functions

HSEM Set and Get Key functions. More...

Functions

void | HAL_HSEM_SetClearKey (uint32_t Key)
Set semaphore Key .
uint32_t | HAL_HSEM_GetClearKey (void)
Get semaphore Key .

Detailed Description

HSEM Set and Get Key functions.

  ==============================================================================
              ##### HSEM Set and Get Key functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Set semaphore Key
      (+) Get semaphore Key

Function Documentation

uint32_t HAL_HSEM_GetClearKey ( void )

Get semaphore Key .

Return values:
Semaphore Key , value from 0 to 0xFFFF

Definition at line 269 of file stm32wbxx_hal_hsem.c.

void HAL_HSEM_SetClearKey ( uint32_t Key )

Set semaphore Key .

Parameters:
Key,: Semaphore Key , value from 0 to 0xFFFF
Return values:
None

Definition at line 257 of file stm32wbxx_hal_hsem.c.

References assert_param, and IS_HSEM_KEY.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: HSEM IRQ handler management

Functions
HSEM IRQ handler management
HSEM Exported Functions

HSEM Notification functions. More...

Functions

void | HAL_HSEM_ActivateNotification (uint32_t SemMask)
Activate Semaphore release Notification for a given Semaphores Mask .
void | HAL_HSEM_DeactivateNotification (uint32_t SemMask)
Deactivate Semaphore release Notification for a given Semaphores Mask .
void | HAL_HSEM_IRQHandler (void)
This function handles HSEM interrupt request.
__weak void | HAL_HSEM_FreeCallback (uint32_t SemMask)
Semaphore Released Callback.

Detailed Description

HSEM Notification functions.

  ==============================================================================
      ##### HSEM IRQ handler management and Notification functions #####
  ==============================================================================
[..]  This section provides HSEM IRQ handler and Notification function.

Function Documentation

void HAL_HSEM_ActivateNotification ( uint32_t SemMask )

Activate Semaphore release Notification for a given Semaphores Mask .

Parameters:
SemMask,: Mask of Released semaphores
Return values:
Semaphore Key

Definition at line 296 of file stm32wbxx_hal_hsem.c.

void HAL_HSEM_DeactivateNotification ( uint32_t SemMask )

Deactivate Semaphore release Notification for a given Semaphores Mask .

Parameters:
SemMask,: Mask of Released semaphores
Return values:
Semaphore Key

Definition at line 306 of file stm32wbxx_hal_hsem.c.

void HAL_HSEM_FreeCallback ( uint32_t SemMask )

Semaphore Released Callback.

Parameters:
SemMask,: Mask of Released semaphores
Return values:
None

Definition at line 336 of file stm32wbxx_hal_hsem.c.

Referenced by HAL_HSEM_IRQHandler().

void HAL_HSEM_IRQHandler ( void )

This function handles HSEM interrupt request.

Return values:
None

Definition at line 315 of file stm32wbxx_hal_hsem.c.

References HAL_HSEM_FreeCallback().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: HSEM Exported Macros

Defines
HSEM Exported Macros
HSEM

Defines

#define | __HAL_HSEM_SEMID_TO_MASK(__SEMID__) (1 << (__SEMID__))
SemID to mask helper Macro.
#define | __HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->IER |= (__SEM_MASK__))
Enables the specified HSEM interrupts.
#define | __HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->IER &= ~(__SEM_MASK__))
Disables the specified HSEM interrupts.
#define | __HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->MISR)
Checks whether interrupt has occurred or not for semaphores specified by a mask.
#define | __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->ISR)
Get the semaphores release status flags.
#define | __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->ICR |= (__SEM_MASK__))
Clears the HSEM Interrupt flags.

Define Documentation

#define __HAL_HSEM_CLEAR_FLAG ( __SEM_MASK__ ) (HSEM->ICR |= (__SEM_MASK__))

Clears the HSEM Interrupt flags.

Parameters:
__SEM_MASK__,: semaphores Mask
Return values:
None.

Definition at line 112 of file stm32wbxx_hal_hsem.h.

#define __HAL_HSEM_DISABLE_IT ( __SEM_MASK__ ) (HSEM->IER &= ~(__SEM_MASK__))

Disables the specified HSEM interrupts.

Parameters:
__SEM_MASK__,: semaphores Mask
Return values:
None.

Definition at line 73 of file stm32wbxx_hal_hsem.h.

#define __HAL_HSEM_ENABLE_IT ( __SEM_MASK__ ) (HSEM->IER |= (__SEM_MASK__))

Enables the specified HSEM interrupts.

Parameters:
__SEM_MASK__,: semaphores Mask
Return values:
None.

Definition at line 61 of file stm32wbxx_hal_hsem.h.

#define __HAL_HSEM_GET_FLAG ( __SEM_MASK__ ) ((__SEM_MASK__) & HSEM->ISR)

Get the semaphores release status flags.

Parameters:
__SEM_MASK__,: semaphores Mask
Return values:
semaphores Mask : Semaphores where Release flags rise.

Definition at line 99 of file stm32wbxx_hal_hsem.h.

#define __HAL_HSEM_GET_IT ( __SEM_MASK__ ) ((__SEM_MASK__) & HSEM->MISR)

Checks whether interrupt has occurred or not for semaphores specified by a mask.

Parameters:
__SEM_MASK__,: semaphores Mask
Return values:
semaphores Mask : Semaphores where an interrupt occurred.

Definition at line 86 of file stm32wbxx_hal_hsem.h.

#define __HAL_HSEM_SEMID_TO_MASK ( __SEMID__ ) (1 << (__SEMID__))

SemID to mask helper Macro.

Parameters:
__SEMID__,: semaphore ID from 0 to 31
Return values:
Semaphore Mask.

Definition at line 49 of file stm32wbxx_hal_hsem.h.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: HSEM Private Macros

Defines
HSEM Private Macros
HSEM

Defines

#define | IS_HSEM_SEMID(__SEMID__) ((__SEMID__) <= HSEM_SEMID_MAX )
#define | IS_HSEM_PROCESSID(__PROCESSID__) ((__PROCESSID__) <= HSEM_PROCESSID_MAX )
#define | IS_HSEM_KEY(__KEY__) ((__KEY__) <= HSEM_CLEAR_KEY_MAX )
#define | IS_HSEM_COREID(__COREID__)

Define Documentation

#define IS_HSEM_COREID ( __COREID__ )
Value:
(((__COREID__) == HSEM_CPU1_COREID) || \
                                    ((__COREID__) == HSEM_CPU2_COREID))

Definition at line 188 of file stm32wbxx_hal_hsem.h.

Referenced by HAL_HSEM_ReleaseAll().

#define IS_HSEM_KEY ( __KEY__ ) ((__KEY__) <= HSEM_CLEAR_KEY_MAX )

Definition at line 186 of file stm32wbxx_hal_hsem.h.

Referenced by HAL_HSEM_ReleaseAll(), and HAL_HSEM_SetClearKey().

#define IS_HSEM_PROCESSID ( __PROCESSID__ ) ((__PROCESSID__) <= HSEM_PROCESSID_MAX )

Definition at line 184 of file stm32wbxx_hal_hsem.h.

Referenced by HAL_HSEM_Release(), and HAL_HSEM_Take().

#define IS_HSEM_SEMID ( __SEMID__ ) ((__SEMID__) <= HSEM_SEMID_MAX )

Definition at line 182 of file stm32wbxx_hal_hsem.h.

Referenced by HAL_HSEM_FastTake(), HAL_HSEM_Release(), and HAL_HSEM_Take().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: I2C Private Define

Defines
I2C Private Define
I2C

Defines

#define | TIMING_CLEAR_MASK (0xF0FFFFFFU)
#define | I2C_TIMEOUT_ADDR (10000U)
#define | I2C_TIMEOUT_BUSY (25U)
#define | I2C_TIMEOUT_DIR (25U)
#define | I2C_TIMEOUT_RXNE (25U)
#define | I2C_TIMEOUT_STOPF (25U)
#define | I2C_TIMEOUT_TC (25U)
#define | I2C_TIMEOUT_TCR (25U)
#define | I2C_TIMEOUT_TXIS (25U)
#define | I2C_TIMEOUT_FLAG (25U)
#define | MAX_NBYTE_SIZE 255U
#define | SlaveAddr_SHIFT 7U
#define | SlaveAddr_MSK 0x06U
#define | I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY))))
#define | I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
#define | I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))
#define | I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))
#define | I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))
#define | I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))
#define | I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM))
#define | I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM))
#define | I2C_XFER_TX_IT (0x00000001U)
#define | I2C_XFER_RX_IT (0x00000002U)
#define | I2C_XFER_LISTEN_IT (0x00000004U)
#define | I2C_XFER_ERROR_IT (0x00000011U)
#define | I2C_XFER_CPLT_IT (0x00000012U)
#define | I2C_XFER_RELOAD_IT (0x00000012U)
#define | I2C_NO_OPTION_FRAME (0xFFFF0000U)

Define Documentation

#define I2C_NO_OPTION_FRAME (0xFFFF0000U)

Definition at line 363 of file stm32wbxx_hal_i2c.c.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMASlaveReceiveCplt(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))

Master Busy RX, combinaison of State LSB and Mode enum

Definition at line 346 of file stm32wbxx_hal_i2c.c.

Referenced by HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), and I2C_ITMasterSeqCplt().

#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))

Master Busy TX, combinaison of State LSB and Mode enum

Definition at line 345 of file stm32wbxx_hal_i2c.c.

Referenced by HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), and I2C_ITMasterSeqCplt().

#define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM))

Memory Busy RX, combinaison of State LSB and Mode enum

Definition at line 350 of file stm32wbxx_hal_i2c.c.

#define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM))

Memory Busy TX, combinaison of State LSB and Mode enum

Definition at line 349 of file stm32wbxx_hal_i2c.c.

#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY))))

Mask State define, keep only RX and TX bits

Definition at line 343 of file stm32wbxx_hal_i2c.c.

Referenced by HAL_I2C_DisableListen_IT().

#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))

Default Value

Definition at line 344 of file stm32wbxx_hal_i2c.c.

Referenced by HAL_I2C_DeInit(), HAL_I2C_Init(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), and I2C_ITSlaveCplt().

#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))

Slave Busy RX, combinaison of State LSB and Mode enum

Definition at line 348 of file stm32wbxx_hal_i2c.c.

Referenced by I2C_ITSlaveSeqCplt().

#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))

Slave Busy TX, combinaison of State LSB and Mode enum

Definition at line 347 of file stm32wbxx_hal_i2c.c.

Referenced by I2C_ITSlaveSeqCplt().

#define I2C_TIMEOUT_ADDR (10000U)

10 s

Definition at line 328 of file stm32wbxx_hal_i2c.c.

#define I2C_TIMEOUT_BUSY (25U)

25 ms

Definition at line 329 of file stm32wbxx_hal_i2c.c.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), and HAL_I2C_Mem_Write().

#define I2C_TIMEOUT_DIR (25U)

25 ms

Definition at line 330 of file stm32wbxx_hal_i2c.c.

#define I2C_TIMEOUT_FLAG (25U)

25 ms

Definition at line 336 of file stm32wbxx_hal_i2c.c.

Referenced by HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), and HAL_I2C_Mem_Write_IT().

#define I2C_TIMEOUT_RXNE (25U)

25 ms

Definition at line 331 of file stm32wbxx_hal_i2c.c.

#define I2C_TIMEOUT_STOPF (25U)

25 ms

Definition at line 332 of file stm32wbxx_hal_i2c.c.

#define I2C_TIMEOUT_TC (25U)

25 ms

Definition at line 333 of file stm32wbxx_hal_i2c.c.

#define I2C_TIMEOUT_TCR (25U)

25 ms

Definition at line 334 of file stm32wbxx_hal_i2c.c.

#define I2C_TIMEOUT_TXIS (25U)

25 ms

Definition at line 335 of file stm32wbxx_hal_i2c.c.

#define I2C_XFER_CPLT_IT (0x00000012U)

Definition at line 359 of file stm32wbxx_hal_i2c.c.

Referenced by HAL_I2C_Master_Abort_IT(), I2C_Disable_IRQ(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_Enable_IRQ(), and I2C_Master_ISR_DMA().

#define I2C_XFER_ERROR_IT (0x00000011U)

Definition at line 358 of file stm32wbxx_hal_i2c.c.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), I2C_Disable_IRQ(), and I2C_Enable_IRQ().

#define I2C_XFER_LISTEN_IT (0x00000004U)

Definition at line 356 of file stm32wbxx_hal_i2c.c.

Referenced by HAL_I2C_DisableListen_IT(), HAL_I2C_EnableListen_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_ITAddrCplt(), I2C_ITError(), I2C_ITListenCplt(), and I2C_ITSlaveCplt().

#define I2C_XFER_RELOAD_IT (0x00000012U)

Definition at line 360 of file stm32wbxx_hal_i2c.c.

Referenced by I2C_Disable_IRQ(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), and I2C_Enable_IRQ().

#define I2C_XFER_RX_IT (0x00000002U)

Definition at line 355 of file stm32wbxx_hal_i2c.c.

Referenced by HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSeqCplt(), I2C_ITSlaveCplt(), and I2C_ITSlaveSeqCplt().

#define I2C_XFER_TX_IT (0x00000001U)

Definition at line 354 of file stm32wbxx_hal_i2c.c.

Referenced by HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit_IT(), I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSeqCplt(), I2C_ITSlaveCplt(), and I2C_ITSlaveSeqCplt().

#define MAX_NBYTE_SIZE 255U

Definition at line 338 of file stm32wbxx_hal_i2c.c.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

#define SlaveAddr_MSK 0x06U

Definition at line 340 of file stm32wbxx_hal_i2c.c.

Referenced by I2C_ITAddrCplt().

#define SlaveAddr_SHIFT 7U

Definition at line 339 of file stm32wbxx_hal_i2c.c.

Referenced by I2C_ITAddrCplt().

#define TIMING_CLEAR_MASK (0xF0FFFFFFU)

I2C TIMING clear register Mask

Definition at line 327 of file stm32wbxx_hal_i2c.c.

Referenced by HAL_I2C_Init().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: I2C Private Functions

Functions
I2C Private Functions
I2C

Functions

static void | I2C_DMAMasterTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C master transmit process complete callback.
static void | I2C_DMAMasterReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C master receive process complete callback.
static void | I2C_DMASlaveTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C slave transmit process complete callback.
static void | I2C_DMASlaveReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C slave receive process complete callback.
static void | I2C_DMAError (DMA_HandleTypeDef *hdma)
DMA I2C communication error callback.
static void | I2C_DMAAbort (DMA_HandleTypeDef *hdma)
DMA I2C communication abort callback (To be called at end of DMA Abort procedure).
static void | I2C_ITAddrCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Address complete process callback.
static void | I2C_ITMasterSeqCplt (I2C_HandleTypeDef *hi2c)
I2C Master sequential complete process.
static void | I2C_ITSlaveSeqCplt (I2C_HandleTypeDef *hi2c)
I2C Slave sequential complete process.
static void | I2C_ITMasterCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Master complete process.
static void | I2C_ITSlaveCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Slave complete process.
static void | I2C_ITListenCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Listen complete process.
static void | I2C_ITError (I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
I2C interrupts error process.
static HAL_StatusTypeDef | I2C_RequestMemoryWrite (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
Master sends target device address followed by internal memory address for write request.
static HAL_StatusTypeDef | I2C_RequestMemoryRead (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
Master sends target device address followed by internal memory address for read request.
static HAL_StatusTypeDef | I2C_Master_ISR_IT (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
static HAL_StatusTypeDef | I2C_Slave_ISR_IT (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
static HAL_StatusTypeDef | I2C_Master_ISR_DMA (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
static HAL_StatusTypeDef | I2C_Slave_ISR_DMA (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
static HAL_StatusTypeDef | I2C_WaitOnFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout.
static HAL_StatusTypeDef | I2C_WaitOnTXISFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of TXIS flag.
static HAL_StatusTypeDef | I2C_WaitOnRXNEFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of RXNE flag.
static HAL_StatusTypeDef | I2C_WaitOnSTOPFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of STOP flag.
static HAL_StatusTypeDef | I2C_IsAcknowledgeFailed (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles Acknowledge failed detection during an I2C Communication.
static void | I2C_Enable_IRQ (I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
Manage the enabling of Interrupts.
static void | I2C_Disable_IRQ (I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
Manage the disabling of Interrupts.
static void | I2C_Flush_TXDR (I2C_HandleTypeDef *hi2c)
I2C Tx data register flush process.
static void | I2C_TransferConfig (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
static void | I2C_ConvertOtherXferOptions (I2C_HandleTypeDef *hi2c)
Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions.

Function Documentation

static void I2C_ConvertOtherXferOptions ( I2C_HandleTypeDef * hi2c ) [static]

Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions.

Parameters:
hi2c I2C handle.
Return values:
None

Definition at line 6466 of file stm32wbxx_hal_i2c.c.

References I2C_FIRST_AND_LAST_FRAME, I2C_FIRST_FRAME, I2C_OTHER_AND_LAST_FRAME, I2C_OTHER_FRAME, and __I2C_HandleTypeDef::XferOptions.

Referenced by HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), and HAL_I2C_Master_Seq_Transmit_IT().

static void I2C_Disable_IRQ | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | InterruptRequest
 | ) |  | [static]

Manage the disabling of Interrupts.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
InterruptRequest | Value of I2C Interrupt configuration definition.
Return values:
None

Definition at line 6403 of file stm32wbxx_hal_i2c.c.

References __HAL_I2C_DISABLE_IT, HAL_I2C_STATE_LISTEN, I2C_IT_ADDRI, I2C_IT_ERRI, I2C_IT_NACKI, I2C_IT_RXI, I2C_IT_STOPI, I2C_IT_TCI, I2C_IT_TXI, I2C_XFER_CPLT_IT, I2C_XFER_ERROR_IT, I2C_XFER_LISTEN_IT, I2C_XFER_RELOAD_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, and __I2C_HandleTypeDef::State.

Referenced by HAL_I2C_DisableListen_IT(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), I2C_ITAddrCplt(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSeqCplt(), I2C_ITSlaveCplt(), and I2C_ITSlaveSeqCplt().

static void I2C_DMAAbort ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C communication abort callback (To be called at end of DMA Abort procedure).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 6040 of file stm32wbxx_hal_i2c.c.

References __I2C_HandleTypeDef::AbortCpltCallback, __I2C_HandleTypeDef::ErrorCallback, HAL_I2C_AbortCpltCallback(), HAL_I2C_ErrorCallback(), HAL_I2C_STATE_ABORT, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, __I2C_HandleTypeDef::hdmatx, __I2C_HandleTypeDef::State, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), and I2C_ITError().

static void I2C_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C communication error callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 6023 of file stm32wbxx_hal_i2c.c.

References HAL_I2C_ERROR_DMA, I2C_ITError(), and __I2C_HandleTypeDef::Instance.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Transmit_DMA(), and HAL_I2C_Slave_Transmit_DMA().

static void I2C_DMAMasterReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C master receive process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 5948 of file stm32wbxx_hal_i2c.c.

References HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, __I2C_HandleTypeDef::hdmarx, I2C_Enable_IRQ(), I2C_ITError(), I2C_XFER_CPLT_IT, I2C_XFER_RELOAD_IT, __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::XferCount, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), and HAL_I2C_Mem_Read_DMA().

static void I2C_DMAMasterTransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C master transmit process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 5873 of file stm32wbxx_hal_i2c.c.

References HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, __I2C_HandleTypeDef::hdmatx, I2C_Enable_IRQ(), I2C_ITError(), I2C_XFER_CPLT_IT, I2C_XFER_RELOAD_IT, __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::XferCount, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), and HAL_I2C_Mem_Write_DMA().

static void I2C_DMASlaveReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C slave receive process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 5996 of file stm32wbxx_hal_i2c.c.

References __HAL_DMA_GET_COUNTER, __I2C_HandleTypeDef::hdmarx, I2C_ITSlaveSeqCplt(), I2C_NO_OPTION_FRAME, __I2C_HandleTypeDef::Instance, and __I2C_HandleTypeDef::XferOptions.

Referenced by HAL_I2C_Slave_Receive_DMA(), and HAL_I2C_Slave_Seq_Receive_DMA().

static void I2C_DMASlaveTransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C slave transmit process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 5921 of file stm32wbxx_hal_i2c.c.

References I2C_FIRST_FRAME, I2C_ITSlaveSeqCplt(), I2C_NEXT_FRAME, __I2C_HandleTypeDef::Instance, and __I2C_HandleTypeDef::XferOptions.

Referenced by HAL_I2C_Slave_Seq_Transmit_DMA(), and HAL_I2C_Slave_Transmit_DMA().

static void I2C_Enable_IRQ | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | InterruptRequest
 | ) |  | [static]

Manage the enabling of Interrupts.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
InterruptRequest | Value of I2C Interrupt configuration definition.
Return values:
None

Definition at line 6332 of file stm32wbxx_hal_i2c.c.

References __HAL_I2C_ENABLE_IT, I2C_IT_ADDRI, I2C_IT_ERRI, I2C_IT_NACKI, I2C_IT_RXI, I2C_IT_STOPI, I2C_IT_TCI, I2C_IT_TXI, I2C_Master_ISR_DMA(), I2C_Slave_ISR_DMA(), I2C_XFER_CPLT_IT, I2C_XFER_ERROR_IT, I2C_XFER_LISTEN_IT, I2C_XFER_RELOAD_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, and __I2C_HandleTypeDef::XferISR.

Referenced by HAL_I2C_EnableListen_IT(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), and I2C_Master_ISR_DMA().

static void I2C_Flush_TXDR ( I2C_HandleTypeDef * hi2c ) [static]

I2C Tx data register flush process.

Parameters:
hi2c I2C handle.
Return values:
None

Definition at line 5852 of file stm32wbxx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, I2C_FLAG_TXE, I2C_FLAG_TXIS, and __I2C_HandleTypeDef::Instance.

Referenced by I2C_IsAcknowledgeFailed(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

static HAL_StatusTypeDef I2C_IsAcknowledgeFailed | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles Acknowledge failed detection during an I2C Communication.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 6245 of file stm32wbxx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_TIMEOUT, HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_FLAG_AF, I2C_FLAG_STOPF, I2C_Flush_TXDR(), I2C_RESET_CR2, __I2C_HandleTypeDef::Mode, and __I2C_HandleTypeDef::State.

Referenced by I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

static void I2C_ITAddrCplt | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags
 | ) |  | [static]

I2C Address complete process callback.

Parameters:
hi2c | I2C handle.
ITFlags | Interrupt flags to handle.
Return values:
None

Definition at line 5223 of file stm32wbxx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::AddrCallback, I2C_InitTypeDef::AddressingMode, __I2C_HandleTypeDef::AddrEventCount, HAL_I2C_AddrCallback(), HAL_I2C_STATE_LISTEN, I2C_ADDRESSINGMODE_10BIT, I2C_Disable_IRQ(), I2C_FLAG_ADDR, I2C_GET_ADDR_MATCH, I2C_GET_DIR, I2C_GET_OWN_ADDRESS1, I2C_GET_OWN_ADDRESS2, I2C_XFER_LISTEN_IT, __I2C_HandleTypeDef::Init, SlaveAddr_MSK, SlaveAddr_SHIFT, and __I2C_HandleTypeDef::State.

Referenced by I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

static void I2C_ITError | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ErrorCode
 | ) |  | [static]

I2C interrupts error process.

Parameters:
hi2c | I2C handle.
ErrorCode | Error code to handle.
Return values:
None

Definition at line 5734 of file stm32wbxx_hal_i2c.c.

References __I2C_HandleTypeDef::AbortCpltCallback, __I2C_HandleTypeDef::ErrorCallback, __DMA_HandleTypeDef::ErrorCode, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_I2C_AbortCpltCallback(), HAL_I2C_ErrorCallback(), HAL_I2C_MODE_NONE, HAL_I2C_STATE_ABORT, HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, __I2C_HandleTypeDef::hdmatx, I2C_Disable_IRQ(), I2C_DMAAbort(), I2C_NO_OPTION_FRAME, I2C_Slave_ISR_IT(), I2C_STATE_NONE, I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferOptions.

Referenced by HAL_I2C_ER_IRQHandler(), I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

static void I2C_ITListenCplt | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags
 | ) |  | [static]

I2C Listen complete process.

Parameters:
hi2c | I2C handle.
ITFlags | Interrupt flags to handle.
Return values:
None

Definition at line 5683 of file stm32wbxx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ListenCpltCallback(), HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_CHECK_FLAG, I2C_Disable_IRQ(), I2C_FLAG_AF, I2C_FLAG_RXNE, I2C_NO_OPTION_FRAME, I2C_STATE_NONE, I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::ListenCpltCallback, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

Referenced by I2C_ITSlaveCplt(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

static void I2C_ITMasterCplt | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags
 | ) |  | [static]

I2C Master complete process.

Parameters:
hi2c | I2C handle.
ITFlags | Interrupt flags to handle.
Return values:
None

Definition at line 5427 of file stm32wbxx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MasterRxCpltCallback(), HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MemRxCpltCallback(), HAL_I2C_MemTxCpltCallback(), HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_ABORT, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_CHECK_FLAG, I2C_Disable_IRQ(), I2C_FLAG_AF, I2C_FLAG_STOPF, I2C_Flush_TXDR(), I2C_ITError(), I2C_NO_OPTION_FRAME, I2C_RESET_CR2, I2C_STATE_NONE, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::MasterRxCpltCallback, __I2C_HandleTypeDef::MasterTxCpltCallback, __I2C_HandleTypeDef::MemRxCpltCallback, __I2C_HandleTypeDef::MemTxCpltCallback, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferOptions.

Referenced by I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

static void I2C_ITMasterSeqCplt ( I2C_HandleTypeDef * hi2c ) [static]

I2C Master sequential complete process.

Parameters:
hi2c I2C handle.
Return values:
None

Definition at line 5318 of file stm32wbxx_hal_i2c.c.

References HAL_I2C_MasterRxCpltCallback(), HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_Disable_IRQ(), I2C_STATE_MASTER_BUSY_RX, I2C_STATE_MASTER_BUSY_TX, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::MasterRxCpltCallback, __I2C_HandleTypeDef::MasterTxCpltCallback, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, and __I2C_HandleTypeDef::XferISR.

Referenced by I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

static void I2C_ITSlaveCplt | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags
 | ) |  | [static]

I2C Slave complete process.

Parameters:
hi2c | I2C handle.
ITFlags | Interrupt flags to handle.
Return values:
None

Definition at line 5546 of file stm32wbxx_hal_i2c.c.

References __HAL_DMA_GET_COUNTER, __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_ListenCpltCallback(), HAL_I2C_MODE_NONE, HAL_I2C_SlaveRxCpltCallback(), HAL_I2C_SlaveTxCpltCallback(), HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, __I2C_HandleTypeDef::hdmatx, I2C_CHECK_FLAG, I2C_CHECK_IT_SOURCE, I2C_Disable_IRQ(), I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_Flush_TXDR(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITSlaveSeqCplt(), I2C_NO_OPTION_FRAME, I2C_RESET_CR2, I2C_STATE_NONE, I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::ListenCpltCallback, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::SlaveRxCpltCallback, __I2C_HandleTypeDef::SlaveTxCpltCallback, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

Referenced by I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

static void I2C_ITSlaveSeqCplt ( I2C_HandleTypeDef * hi2c ) [static]

I2C Slave sequential complete process.

Parameters:
hi2c I2C handle.
Return values:
None

Definition at line 5371 of file stm32wbxx_hal_i2c.c.

References HAL_I2C_MODE_NONE, HAL_I2C_SlaveRxCpltCallback(), HAL_I2C_SlaveTxCpltCallback(), HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, I2C_Disable_IRQ(), I2C_STATE_SLAVE_BUSY_RX, I2C_STATE_SLAVE_BUSY_TX, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::SlaveRxCpltCallback, __I2C_HandleTypeDef::SlaveTxCpltCallback, and __I2C_HandleTypeDef::State.

Referenced by I2C_DMASlaveReceiveCplt(), I2C_DMASlaveTransmitCplt(), I2C_ITSlaveCplt(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

static HAL_StatusTypeDef I2C_Master_ISR_DMA | ( | struct __I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags,
 |  | uint32_t | ITSources
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
ITFlags | Interrupt flags to handle.
ITSources | Interrupt sources enabled.
Return values:
HAL status

Definition at line 4868 of file stm32wbxx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_DISABLE_IT, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_SIZE, HAL_I2C_STATE_BUSY_RX, I2C_AUTOEND_MODE, I2C_CHECK_FLAG, I2C_CHECK_IT_SOURCE, I2C_Enable_IRQ(), I2C_FLAG_AF, I2C_FLAG_STOPF, I2C_FLAG_TC, I2C_FLAG_TCR, I2C_Flush_TXDR(), I2C_GET_STOP_MODE, I2C_IT_NACKI, I2C_IT_STOPI, I2C_IT_TCI, I2C_ITError(), I2C_ITMasterCplt(), I2C_ITMasterSeqCplt(), I2C_NO_OPTION_FRAME, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_CPLT_IT, __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), and I2C_Enable_IRQ().

static HAL_StatusTypeDef I2C_Master_ISR_IT | ( | struct __I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags,
 |  | uint32_t | ITSources
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
ITFlags | Interrupt flags to handle.
ITSources | Interrupt sources enabled.
Return values:
HAL status

Definition at line 4595 of file stm32wbxx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_SIZE, I2C_AUTOEND_MODE, I2C_CHECK_FLAG, I2C_CHECK_IT_SOURCE, I2C_FLAG_AF, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_FLAG_TC, I2C_FLAG_TCR, I2C_FLAG_TXIS, I2C_Flush_TXDR(), I2C_GET_STOP_MODE, I2C_IT_NACKI, I2C_IT_RXI, I2C_IT_STOPI, I2C_IT_TCI, I2C_IT_TXI, I2C_ITError(), I2C_ITMasterCplt(), I2C_ITMasterSeqCplt(), I2C_NO_OPTION_FRAME, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_TransferConfig(), __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_IT(), and HAL_I2C_Mem_Write_IT().

static HAL_StatusTypeDef I2C_RequestMemoryRead | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Master sends target device address followed by internal memory address for read request.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 5176 of file stm32wbxx_hal_i2c.c.

References I2C_FLAG_TC, I2C_GENERATE_START_WRITE, I2C_MEM_ADD_LSB, I2C_MEM_ADD_MSB, I2C_MEMADD_SIZE_8BIT, I2C_SOFTEND_MODE, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), and __I2C_HandleTypeDef::Instance.

Referenced by HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), and HAL_I2C_Mem_Read_IT().

static HAL_StatusTypeDef I2C_RequestMemoryWrite | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Master sends target device address followed by internal memory address for write request.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 5123 of file stm32wbxx_hal_i2c.c.

References I2C_FLAG_TCR, I2C_GENERATE_START_WRITE, I2C_MEM_ADD_LSB, I2C_MEM_ADD_MSB, I2C_MEMADD_SIZE_8BIT, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), and __I2C_HandleTypeDef::Instance.

Referenced by HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), and HAL_I2C_Mem_Write_IT().

static HAL_StatusTypeDef I2C_Slave_ISR_DMA | ( | struct __I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags,
 |  | uint32_t | ITSources
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
ITFlags | Interrupt flags to handle.
ITSources | Interrupt sources enabled.
Return values:
HAL status

Definition at line 5003 of file stm32wbxx_hal_i2c.c.

References __HAL_DMA_GET_COUNTER, __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, __I2C_HandleTypeDef::hdmarx, __I2C_HandleTypeDef::hdmatx, I2C_CHECK_FLAG, I2C_CHECK_IT_SOURCE, I2C_FIRST_AND_LAST_FRAME, I2C_FIRST_FRAME, I2C_FLAG_ADDR, I2C_FLAG_AF, I2C_FLAG_STOPF, I2C_Flush_TXDR(), I2C_IT_ADDRI, I2C_IT_NACKI, I2C_IT_STOPI, I2C_ITAddrCplt(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_ITSlaveSeqCplt(), I2C_NEXT_FRAME, I2C_NO_OPTION_FRAME, __I2C_HandleTypeDef::State, and __I2C_HandleTypeDef::XferOptions.

Referenced by HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Transmit_DMA(), and I2C_Enable_IRQ().

static HAL_StatusTypeDef I2C_Slave_ISR_IT | ( | struct __I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | ITFlags,
 |  | uint32_t | ITSources
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
ITFlags | Interrupt flags to handle.
ITSources | Interrupt sources enabled.
Return values:
HAL status

Definition at line 4732 of file stm32wbxx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, I2C_CHECK_FLAG, I2C_CHECK_IT_SOURCE, I2C_FIRST_AND_LAST_FRAME, I2C_FIRST_FRAME, I2C_FLAG_ADDR, I2C_FLAG_AF, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_FLAG_TXIS, I2C_Flush_TXDR(), I2C_IT_ADDRI, I2C_IT_NACKI, I2C_IT_RXI, I2C_IT_STOPI, I2C_IT_TXI, I2C_ITAddrCplt(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_ITSlaveSeqCplt(), I2C_NEXT_FRAME, I2C_NO_OPTION_FRAME, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_EnableListen_IT(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit_IT(), and I2C_ITError().

static void I2C_TransferConfig | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t | Size,
 |  | uint32_t | Mode,
 |  | uint32_t | Request
 | ) |  | [static]

Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).

Parameters:
hi2c | I2C handle.
DevAddress | Specifies the slave address to be programmed.
Size | Specifies the number of bytes to be programmed. This parameter must be a value between 0 and 255.
Mode New state of the I2C START condition generation. This parameter can be one of the following values:
  • I2C_RELOAD_MODE Enable Reload mode .
  • I2C_AUTOEND_MODE Enable Automatic end mode.
  • I2C_SOFTEND_MODE Enable Software end mode.
Request New state of the I2C START condition generation. This parameter can be one of the following values:
  • I2C_NO_STARTSTOP Don't Generate stop and start condition.
  • I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
  • I2C_GENERATE_START_READ Generate Restart for read request.
  • I2C_GENERATE_START_WRITE Generate Restart for write request.
Return values:
None

Definition at line 6313 of file stm32wbxx_hal_i2c.c.

References assert_param, __I2C_HandleTypeDef::Instance, IS_TRANSFER_MODE, and IS_TRANSFER_REQUEST.

Referenced by HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles I2C Communication Timeout.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Flag | Specifies the I2C flag to check.
Status | The new Flag status (SET or RESET).
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 6081 of file stm32wbxx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_TIMEOUT, HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::Mode, and __I2C_HandleTypeDef::State.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles I2C Communication Timeout for specific usage of RXNE flag.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 6182 of file stm32wbxx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_TIMEOUT, HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_IsAcknowledgeFailed(), I2C_RESET_CR2, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::State, and __I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_Master_Receive(), and HAL_I2C_Slave_Receive().

static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles I2C Communication Timeout for specific usage of STOP flag.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 6148 of file stm32wbxx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_TIMEOUT, HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_FLAG_STOPF, I2C_IsAcknowledgeFailed(), __I2C_HandleTypeDef::Mode, and __I2C_HandleTypeDef::State.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Receive(), and HAL_I2C_Slave_Transmit().

static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles I2C Communication Timeout for specific usage of TXIS flag.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 6111 of file stm32wbxx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_TIMEOUT, HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_FLAG_TXIS, I2C_IsAcknowledgeFailed(), __I2C_HandleTypeDef::Mode, and __I2C_HandleTypeDef::State.

Referenced by HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Transmit(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
I2C Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_I2C_Init (I2C_HandleTypeDef *hi2c)
Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C peripheral.
__weak void | HAL_I2C_MspInit (I2C_HandleTypeDef *hi2c)
Initialize the I2C MSP.
__weak void | HAL_I2C_MspDeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C MSP.
HAL_StatusTypeDef | HAL_I2C_RegisterCallback (I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)
Register a User I2C Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_I2C_UnRegisterCallback (I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
Unregister an I2C Callback I2C callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_I2C_RegisterAddrCallback (I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
Register the Slave Address Match I2C Callback To be used instead of the weak HAL_I2C_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_I2C_UnRegisterAddrCallback (I2C_HandleTypeDef *hi2c)
UnRegister the Slave Address Match I2C Callback Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          deinitialize the I2Cx peripheral:

      (+) User must Implement HAL_I2C_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).

      (+) Call the function HAL_I2C_Init() to configure the selected device with
          the selected configuration:
        (++) Clock Timing
        (++) Own Address 1
        (++) Addressing mode (Master, Slave)
        (++) Dual Addressing mode
        (++) Own Address 2
        (++) Own Address 2 Mask
        (++) General call mode
        (++) Nostretch mode

      (+) Call the function HAL_I2C_DeInit() to restore the default configuration
          of the selected I2Cx peripheral.

Function Documentation

HAL_StatusTypeDef HAL_I2C_DeInit ( I2C_HandleTypeDef * hi2c )

DeInitialize the I2C peripheral.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL status

Definition at line 578 of file stm32wbxx_hal_i2c.c.

References __HAL_I2C_DISABLE, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MspDeInit(), HAL_I2C_STATE_BUSY, HAL_I2C_STATE_RESET, I2C_STATE_NONE, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::MspDeInitCallback, __I2C_HandleTypeDef::PreviousState, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_Init ( I2C_HandleTypeDef * hi2c )

Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and initialize the associated handle.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL status

Definition at line 469 of file stm32wbxx_hal_i2c.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, __I2C_HandleTypeDef::AbortCpltCallback, __I2C_HandleTypeDef::AddrCallback, I2C_InitTypeDef::AddressingMode, assert_param, I2C_InitTypeDef::DualAddressMode, __I2C_HandleTypeDef::ErrorCallback, __I2C_HandleTypeDef::ErrorCode, I2C_InitTypeDef::GeneralCallMode, HAL_I2C_AbortCpltCallback(), HAL_I2C_AddrCallback(), HAL_I2C_ERROR_NONE, HAL_I2C_ErrorCallback(), HAL_I2C_ListenCpltCallback(), HAL_I2C_MasterRxCpltCallback(), HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MemRxCpltCallback(), HAL_I2C_MemTxCpltCallback(), HAL_I2C_MODE_NONE, HAL_I2C_MspInit(), HAL_I2C_SlaveRxCpltCallback(), HAL_I2C_SlaveTxCpltCallback(), HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, HAL_I2C_STATE_RESET, I2C_ADDRESSINGMODE_10BIT, I2C_ADDRESSINGMODE_7BIT, I2C_DUALADDRESS_ENABLE, I2C_STATE_NONE, __I2C_HandleTypeDef::Init, __I2C_HandleTypeDef::Instance, IS_I2C_ADDRESSING_MODE, IS_I2C_DUAL_ADDRESS, IS_I2C_GENERAL_CALL, IS_I2C_NO_STRETCH, IS_I2C_OWN_ADDRESS1, IS_I2C_OWN_ADDRESS2, IS_I2C_OWN_ADDRESS2_MASK, __I2C_HandleTypeDef::ListenCpltCallback, __I2C_HandleTypeDef::Lock, __I2C_HandleTypeDef::MasterRxCpltCallback, __I2C_HandleTypeDef::MasterTxCpltCallback, __I2C_HandleTypeDef::MemRxCpltCallback, __I2C_HandleTypeDef::MemTxCpltCallback, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::MspInitCallback, I2C_InitTypeDef::NoStretchMode, I2C_InitTypeDef::OwnAddress1, I2C_InitTypeDef::OwnAddress2, I2C_InitTypeDef::OwnAddress2Masks, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::SlaveRxCpltCallback, __I2C_HandleTypeDef::SlaveTxCpltCallback, __I2C_HandleTypeDef::State, I2C_InitTypeDef::Timing, and TIMING_CLEAR_MASK.

void HAL_I2C_MspDeInit ( I2C_HandleTypeDef * hi2c )

DeInitialize the I2C MSP.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 640 of file stm32wbxx_hal_i2c.c.

Referenced by HAL_I2C_DeInit(), and HAL_I2C_UnRegisterCallback().

void HAL_I2C_MspInit ( I2C_HandleTypeDef * hi2c )

Initialize the I2C MSP.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 624 of file stm32wbxx_hal_i2c.c.

Referenced by HAL_I2C_Init(), and HAL_I2C_UnRegisterCallback().

HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback | ( | I2C_HandleTypeDef * | hi2c,
 |  | pI2C_AddrCallbackTypeDef | pCallback
 | ) |  |

Register the Slave Address Match I2C Callback To be used instead of the weak HAL_I2C_AddrCallback() predefined callback.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pCallback | pointer to the Address Match Callback function
Return values:
HAL status

Definition at line 906 of file stm32wbxx_hal_i2c.c.

References __I2C_HandleTypeDef::AddrCallback, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_INVALID_CALLBACK, HAL_I2C_STATE_READY, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_RegisterCallback | ( | I2C_HandleTypeDef * | hi2c,
 |  | HAL_I2C_CallbackIDTypeDef | CallbackID,
 |  | pI2C_CallbackTypeDef | pCallback
 | ) |  |

Register a User I2C Callback To be used instead of the weak predefined callback.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
  • HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
  • HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
  • HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
  • HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
  • HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
  • HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
  • HAL_I2C_ERROR_CB_ID Error callback ID
  • HAL_I2C_ABORT_CB_ID Abort callback ID
  • HAL_I2C_MSPINIT_CB_ID MspInit callback ID
  • HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 672 of file stm32wbxx_hal_i2c.c.

References __I2C_HandleTypeDef::AbortCpltCallback, __I2C_HandleTypeDef::ErrorCallback, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ABORT_CB_ID, HAL_I2C_ERROR_CB_ID, HAL_I2C_ERROR_INVALID_CALLBACK, HAL_I2C_LISTEN_COMPLETE_CB_ID, HAL_I2C_MASTER_RX_COMPLETE_CB_ID, HAL_I2C_MASTER_TX_COMPLETE_CB_ID, HAL_I2C_MEM_RX_COMPLETE_CB_ID, HAL_I2C_MEM_TX_COMPLETE_CB_ID, HAL_I2C_MSPDEINIT_CB_ID, HAL_I2C_MSPINIT_CB_ID, HAL_I2C_SLAVE_RX_COMPLETE_CB_ID, HAL_I2C_SLAVE_TX_COMPLETE_CB_ID, HAL_I2C_STATE_READY, HAL_I2C_STATE_RESET, __I2C_HandleTypeDef::ListenCpltCallback, __I2C_HandleTypeDef::MasterRxCpltCallback, __I2C_HandleTypeDef::MasterTxCpltCallback, __I2C_HandleTypeDef::MemRxCpltCallback, __I2C_HandleTypeDef::MemTxCpltCallback, __I2C_HandleTypeDef::MspDeInitCallback, __I2C_HandleTypeDef::MspInitCallback, __I2C_HandleTypeDef::SlaveRxCpltCallback, __I2C_HandleTypeDef::SlaveTxCpltCallback, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback ( I2C_HandleTypeDef * hi2c )

UnRegister the Slave Address Match I2C Callback Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL status

Definition at line 945 of file stm32wbxx_hal_i2c.c.

References __I2C_HandleTypeDef::AddrCallback, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_AddrCallback(), HAL_I2C_ERROR_INVALID_CALLBACK, HAL_I2C_STATE_READY, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_UnRegisterCallback | ( | I2C_HandleTypeDef * | hi2c,
 |  | HAL_I2C_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an I2C Callback I2C callback is redirected to the weak predefined callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
CallbackID ID of the callback to be unregistered This parameter can be one of the following values: This parameter can be one of the following values:
  • HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
  • HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
  • HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
  • HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
  • HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
  • HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
  • HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
  • HAL_I2C_ERROR_CB_ID Error callback ID
  • HAL_I2C_ABORT_CB_ID Abort callback ID
  • HAL_I2C_MSPINIT_CB_ID MspInit callback ID
  • HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
HAL status

Definition at line 799 of file stm32wbxx_hal_i2c.c.

References __I2C_HandleTypeDef::AbortCpltCallback, __I2C_HandleTypeDef::ErrorCallback, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ABORT_CB_ID, HAL_I2C_AbortCpltCallback(), HAL_I2C_ERROR_CB_ID, HAL_I2C_ERROR_INVALID_CALLBACK, HAL_I2C_ErrorCallback(), HAL_I2C_LISTEN_COMPLETE_CB_ID, HAL_I2C_ListenCpltCallback(), HAL_I2C_MASTER_RX_COMPLETE_CB_ID, HAL_I2C_MASTER_TX_COMPLETE_CB_ID, HAL_I2C_MasterRxCpltCallback(), HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MEM_RX_COMPLETE_CB_ID, HAL_I2C_MEM_TX_COMPLETE_CB_ID, HAL_I2C_MemRxCpltCallback(), HAL_I2C_MemTxCpltCallback(), HAL_I2C_MspDeInit(), HAL_I2C_MSPDEINIT_CB_ID, HAL_I2C_MspInit(), HAL_I2C_MSPINIT_CB_ID, HAL_I2C_SLAVE_RX_COMPLETE_CB_ID, HAL_I2C_SLAVE_TX_COMPLETE_CB_ID, HAL_I2C_SlaveRxCpltCallback(), HAL_I2C_SlaveTxCpltCallback(), HAL_I2C_STATE_READY, HAL_I2C_STATE_RESET, __I2C_HandleTypeDef::ListenCpltCallback, __I2C_HandleTypeDef::MasterRxCpltCallback, __I2C_HandleTypeDef::MasterTxCpltCallback, __I2C_HandleTypeDef::MemRxCpltCallback, __I2C_HandleTypeDef::MemTxCpltCallback, __I2C_HandleTypeDef::MspDeInitCallback, __I2C_HandleTypeDef::MspInitCallback, __I2C_HandleTypeDef::SlaveRxCpltCallback, __I2C_HandleTypeDef::SlaveTxCpltCallback, and __I2C_HandleTypeDef::State.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
I2C Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_I2C_Master_Transmit (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Receive (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Mem_Write (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Write an amount of data in blocking mode to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Read an amount of data in blocking mode from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with Interrupt to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Read an amount of data in non-blocking mode with Interrupt from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with DMA to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Reads an amount of data in non-blocking mode with DMA from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_IsDeviceReady (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Checks if target device is ready for communication.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_EnableListen_IT (I2C_HandleTypeDef *hi2c)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_DisableListen_IT (I2C_HandleTypeDef *hi2c)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Abort_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
Abort a master I2C IT or DMA process communication with Interrupt.

Detailed Description

Data transfers functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the I2C data
    transfers.

    (#) There are two modes of transfer:
       (++) Blocking mode : The communication is performed in the polling mode.
            The status of all data processing is returned by the same function
            after finishing transfer.
       (++) No-Blocking mode : The communication is performed using Interrupts
            or DMA. These functions return the status of the transfer startup.
            The end of the data processing will be indicated through the
            dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
            using DMA mode.

    (#) Blocking mode functions are :
        (++) HAL_I2C_Master_Transmit()
        (++) HAL_I2C_Master_Receive()
        (++) HAL_I2C_Slave_Transmit()
        (++) HAL_I2C_Slave_Receive()
        (++) HAL_I2C_Mem_Write()
        (++) HAL_I2C_Mem_Read()
        (++) HAL_I2C_IsDeviceReady()

    (#) No-Blocking mode functions with Interrupt are :
        (++) HAL_I2C_Master_Transmit_IT()
        (++) HAL_I2C_Master_Receive_IT()
        (++) HAL_I2C_Slave_Transmit_IT()
        (++) HAL_I2C_Slave_Receive_IT()
        (++) HAL_I2C_Mem_Write_IT()
        (++) HAL_I2C_Mem_Read_IT()
        (++) HAL_I2C_Master_Seq_Transmit_IT()
        (++) HAL_I2C_Master_Seq_Receive_IT()
        (++) HAL_I2C_Slave_Seq_Transmit_IT()
        (++) HAL_I2C_Slave_Seq_Receive_IT()
        (++) HAL_I2C_EnableListen_IT()
        (++) HAL_I2C_DisableListen_IT()
        (++) HAL_I2C_Master_Abort_IT()

    (#) No-Blocking mode functions with DMA are :
        (++) HAL_I2C_Master_Transmit_DMA()
        (++) HAL_I2C_Master_Receive_DMA()
        (++) HAL_I2C_Slave_Transmit_DMA()
        (++) HAL_I2C_Slave_Receive_DMA()
        (++) HAL_I2C_Mem_Write_DMA()
        (++) HAL_I2C_Mem_Read_DMA()
        (++) HAL_I2C_Master_Seq_Transmit_DMA()
        (++) HAL_I2C_Master_Seq_Receive_DMA()
        (++) HAL_I2C_Slave_Seq_Transmit_DMA()
        (++) HAL_I2C_Slave_Seq_Receive_DMA()

    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
        (++) HAL_I2C_MasterTxCpltCallback()
        (++) HAL_I2C_MasterRxCpltCallback()
        (++) HAL_I2C_SlaveTxCpltCallback()
        (++) HAL_I2C_SlaveRxCpltCallback()
        (++) HAL_I2C_MemTxCpltCallback()
        (++) HAL_I2C_MemRxCpltCallback()
        (++) HAL_I2C_AddrCallback()
        (++) HAL_I2C_ListenCpltCallback()
        (++) HAL_I2C_ErrorCallback()
        (++) HAL_I2C_AbortCpltCallback()

Function Documentation

HAL_StatusTypeDef HAL_I2C_DisableListen_IT ( I2C_HandleTypeDef * hi2c )

Disable the Address listen mode with Interrupt.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C
Return values:
HAL status

Definition at line 4214 of file stm32wbxx_hal_i2c.c.

References HAL_I2C_MODE_NONE, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, I2C_Disable_IRQ(), I2C_STATE_MSK, I2C_XFER_LISTEN_IT, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, and __I2C_HandleTypeDef::XferISR.

HAL_StatusTypeDef HAL_I2C_EnableListen_IT ( I2C_HandleTypeDef * hi2c )

Enable the Address listen mode with Interrupt.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL status

Definition at line 4190 of file stm32wbxx_hal_i2c.c.

References HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, I2C_Enable_IRQ(), I2C_Slave_ISR_IT(), I2C_XFER_LISTEN_IT, __I2C_HandleTypeDef::State, and __I2C_HandleTypeDef::XferISR.

HAL_StatusTypeDef HAL_I2C_IsDeviceReady | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint32_t | Trials,
 |  | uint32_t | Timeout
 | ) |  |

Checks if target device is ready for communication.

Note:
This function is used with Memory devices
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
Trials | Number of trials
Timeout | Timeout duration
Return values:
HAL status

Definition at line 3014 of file stm32wbxx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, I2C_InitTypeDef::AddressingMode, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_TIMEOUT, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, I2C_FLAG_AF, I2C_FLAG_BUSY, I2C_FLAG_STOPF, I2C_GENERATE_START, I2C_WaitOnFlagUntilTimeout(), __I2C_HandleTypeDef::Init, __I2C_HandleTypeDef::Instance, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_Master_Abort_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress
 | ) |  |

Abort a master I2C IT or DMA process communication with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
Return values:
HAL status

Definition at line 4247 of file stm32wbxx_hal_i2c.c.

References HAL_I2C_MODE_MASTER, HAL_I2C_STATE_ABORT, I2C_AUTOEND_MODE, I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_GENERATE_STOP, I2C_TransferConfig(), I2C_XFER_CPLT_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Mode, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_Master_Receive | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receives in master mode an amount of data in blocking mode.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1174 of file stm32wbxx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_FLAG_BUSY, I2C_FLAG_STOPF, I2C_FLAG_TCR, I2C_GENERATE_START_READ, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RESET_CR2, I2C_TIMEOUT_BUSY, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in master mode an amount of data in non-blocking mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1929 of file stm32wbxx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, I2C_AUTOEND_MODE, I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_READ, I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_ERROR_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Receive_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in master mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1619 of file stm32wbxx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_READ, I2C_Master_ISR_IT(), I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_RX_IT, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 3486 of file stm32wbxx_hal_i2c.c.

References assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, I2C_AUTOEND_MODE, I2C_ConvertOtherXferOptions(), I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_Enable_IRQ(), I2C_GENERATE_START_READ, I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_STATE_MASTER_BUSY_RX, I2C_TransferConfig(), I2C_XFER_ERROR_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, IS_I2C_TRANSFER_OPTIONS_REQUEST, IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 3402 of file stm32wbxx_hal_i2c.c.

References assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_ConvertOtherXferOptions(), I2C_Enable_IRQ(), I2C_GENERATE_START_READ, I2C_Master_ISR_IT(), I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_STATE_MASTER_BUSY_RX, I2C_TransferConfig(), I2C_XFER_RX_IT, IS_I2C_TRANSFER_OPTIONS_REQUEST, IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 3240 of file stm32wbxx_hal_i2c.c.

References assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmatx, I2C_AUTOEND_MODE, I2C_ConvertOtherXferOptions(), I2C_DMAError(), I2C_DMAMasterTransmitCplt(), I2C_Enable_IRQ(), I2C_GENERATE_START_WRITE, I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_STATE_MASTER_BUSY_TX, I2C_TransferConfig(), I2C_XFER_ERROR_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, IS_I2C_TRANSFER_OPTIONS_REQUEST, IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 3156 of file stm32wbxx_hal_i2c.c.

References assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_ConvertOtherXferOptions(), I2C_Enable_IRQ(), I2C_GENERATE_START_WRITE, I2C_Master_ISR_IT(), I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_STATE_MASTER_BUSY_TX, I2C_TransferConfig(), I2C_XFER_TX_IT, IS_I2C_TRANSFER_OPTIONS_REQUEST, IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::PreviousState, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Transmit | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmits in master mode an amount of data in blocking mode.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1060 of file stm32wbxx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_FLAG_BUSY, I2C_FLAG_STOPF, I2C_FLAG_TCR, I2C_GENERATE_START_WRITE, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RESET_CR2, I2C_TIMEOUT_BUSY, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in master mode an amount of data in non-blocking mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1786 of file stm32wbxx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmatx, I2C_AUTOEND_MODE, I2C_DMAError(), I2C_DMAMasterTransmitCplt(), I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_WRITE, I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_ERROR_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in master mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1550 of file stm32wbxx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_WRITE, I2C_Master_ISR_IT(), I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_TransferConfig(), I2C_XFER_TX_IT, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Read | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Read an amount of data in blocking mode from a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 2415 of file stm32wbxx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_FLAG_BUSY, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_FLAG_TCR, I2C_GENERATE_START_READ, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RequestMemoryRead(), I2C_RESET_CR2, I2C_TIMEOUT_BUSY, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), __I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Reads an amount of data in non-blocking mode with DMA from a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be read
Return values:
HAL status

Definition at line 2873 of file stm32wbxx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_GetTick(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, I2C_AUTOEND_MODE, I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_READ, I2C_Master_ISR_DMA(), I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_RequestMemoryRead(), I2C_TIMEOUT_FLAG, I2C_TransferConfig(), I2C_XFER_ERROR_IT, __I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Read_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Read an amount of data in non-blocking mode with Interrupt from a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2639 of file stm32wbxx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_GENERATE_START_READ, I2C_Master_ISR_IT(), I2C_NO_OPTION_FRAME, I2C_RELOAD_MODE, I2C_RequestMemoryRead(), I2C_TIMEOUT_FLAG, I2C_TransferConfig(), I2C_XFER_RX_IT, IS_I2C_MEMADD_SIZE, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Write | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Write an amount of data in blocking mode to a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 2280 of file stm32wbxx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_FLAG_BUSY, I2C_FLAG_STOPF, I2C_FLAG_TCR, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RequestMemoryWrite(), I2C_RESET_CR2, I2C_TIMEOUT_BUSY, I2C_TransferConfig(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), __I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Write an amount of data in non-blocking mode with DMA to a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2729 of file stm32wbxx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_GetTick(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmatx, I2C_AUTOEND_MODE, I2C_DMAError(), I2C_DMAMasterTransmitCplt(), I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_Master_ISR_DMA(), I2C_NO_OPTION_FRAME, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RequestMemoryWrite(), I2C_TIMEOUT_FLAG, I2C_TransferConfig(), I2C_XFER_ERROR_IT, __I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Write_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Write an amount of data in non-blocking mode with Interrupt to a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2548 of file stm32wbxx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_AUTOEND_MODE, I2C_Enable_IRQ(), I2C_FLAG_BUSY, I2C_Master_ISR_IT(), I2C_NO_OPTION_FRAME, I2C_NO_STARTSTOP, I2C_RELOAD_MODE, I2C_RequestMemoryWrite(), I2C_TIMEOUT_FLAG, I2C_TransferConfig(), I2C_XFER_TX_IT, IS_I2C_MEMADD_SIZE, MAX_NBYTE_SIZE, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Receive | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive in slave mode an amount of data in blocking mode.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1424 of file stm32wbxx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_FLAG_ADDR, I2C_FLAG_BUSY, I2C_FLAG_DIR, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, and __I2C_HandleTypeDef::XferISR.

HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in slave mode an amount of data in non-blocking mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2173 of file stm32wbxx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmarx, I2C_DMAError(), I2C_DMASlaveReceiveCplt(), I2C_Enable_IRQ(), I2C_NO_OPTION_FRAME, I2C_Slave_ISR_DMA(), I2C_XFER_LISTEN_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in slave mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1735 of file stm32wbxx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_Enable_IRQ(), I2C_NO_OPTION_FRAME, I2C_Slave_ISR_IT(), I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 4015 of file stm32wbxx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, __I2C_HandleTypeDef::hdmarx, __I2C_HandleTypeDef::hdmatx, I2C_DIRECTION_TRANSMIT, I2C_Disable_IRQ(), I2C_DMAAbort(), I2C_DMAError(), I2C_DMASlaveReceiveCplt(), I2C_Enable_IRQ(), I2C_FLAG_ADDR, I2C_GET_DIR, I2C_Slave_ISR_DMA(), I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, IS_I2C_TRANSFER_OPTIONS_REQUEST, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 3920 of file stm32wbxx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, __I2C_HandleTypeDef::hdmatx, I2C_DIRECTION_TRANSMIT, I2C_Disable_IRQ(), I2C_DMAAbort(), I2C_Enable_IRQ(), I2C_FLAG_ADDR, I2C_GET_DIR, I2C_Slave_ISR_IT(), I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, IS_I2C_TRANSFER_OPTIONS_REQUEST, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 3741 of file stm32wbxx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, __I2C_HandleTypeDef::hdmarx, __I2C_HandleTypeDef::hdmatx, I2C_DIRECTION_RECEIVE, I2C_Disable_IRQ(), I2C_DMAAbort(), I2C_DMAError(), I2C_DMASlaveTransmitCplt(), I2C_Enable_IRQ(), I2C_FLAG_ADDR, I2C_GET_DIR, I2C_Slave_ISR_DMA(), I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, IS_I2C_TRANSFER_OPTIONS_REQUEST, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C Sequential Transfer Options
Return values:
HAL status

Definition at line 3646 of file stm32wbxx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, assert_param, __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, __I2C_HandleTypeDef::hdmarx, I2C_DIRECTION_RECEIVE, I2C_Disable_IRQ(), I2C_DMAAbort(), I2C_Enable_IRQ(), I2C_FLAG_ADDR, I2C_GET_DIR, I2C_Slave_ISR_IT(), I2C_XFER_LISTEN_IT, I2C_XFER_RX_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, IS_I2C_TRANSFER_OPTIONS_REQUEST, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Transmit | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmits in slave mode an amount of data in blocking mode.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1287 of file stm32wbxx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, I2C_InitTypeDef::AddressingMode, __I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_ADDRESSINGMODE_10BIT, I2C_FLAG_ADDR, I2C_FLAG_BUSY, I2C_FLAG_DIR, I2C_FLAG_STOPF, I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_WaitOnTXISFlagUntilTimeout(), __I2C_HandleTypeDef::Init, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, and __I2C_HandleTypeDef::XferISR.

HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in slave mode an amount of data in non-blocking mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2070 of file stm32wbxx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_DMA, HAL_I2C_ERROR_DMA_PARAM, HAL_I2C_ERROR_INVALID_PARAM, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::hdmatx, I2C_DMAError(), I2C_DMASlaveTransmitCplt(), I2C_Enable_IRQ(), I2C_NO_OPTION_FRAME, I2C_Slave_ISR_DMA(), I2C_XFER_LISTEN_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in slave mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1686 of file stm32wbxx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_Enable_IRQ(), I2C_NO_OPTION_FRAME, I2C_Slave_ISR_IT(), I2C_XFER_LISTEN_IT, I2C_XFER_TX_IT, __I2C_HandleTypeDef::Instance, __I2C_HandleTypeDef::Mode, __I2C_HandleTypeDef::pBuffPtr, __I2C_HandleTypeDef::State, __I2C_HandleTypeDef::XferCount, __I2C_HandleTypeDef::XferISR, __I2C_HandleTypeDef::XferOptions, and __I2C_HandleTypeDef::XferSize.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IRQ Handler and Callbacks

Functions
IRQ Handler and Callbacks
I2C Exported Functions

Functions

void | HAL_I2C_EV_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C event interrupt request.
void | HAL_I2C_ER_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C error interrupt request.
__weak void | HAL_I2C_MasterTxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Tx Transfer completed callback.
__weak void | HAL_I2C_MasterRxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Rx Transfer completed callback.
__weak void | HAL_I2C_SlaveTxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Tx Transfer completed callback.
__weak void | HAL_I2C_SlaveRxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Rx Transfer completed callback.
__weak void | HAL_I2C_AddrCallback (I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_I2C_ListenCpltCallback (I2C_HandleTypeDef *hi2c)
Listen Complete callback.
__weak void | HAL_I2C_MemTxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Tx Transfer completed callback.
__weak void | HAL_I2C_MemRxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Rx Transfer completed callback.
__weak void | HAL_I2C_ErrorCallback (I2C_HandleTypeDef *hi2c)
I2C error callback.
__weak void | HAL_I2C_AbortCpltCallback (I2C_HandleTypeDef *hi2c)
I2C abort callback.

Function Documentation

void HAL_I2C_AbortCpltCallback ( I2C_HandleTypeDef * hi2c )

I2C abort callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4512 of file stm32wbxx_hal_i2c.c.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterCallback(), I2C_DMAAbort(), and I2C_ITError().

void HAL_I2C_AddrCallback | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t | TransferDirection,
 |  | uint16_t | AddrMatchCode
 | ) |  |

Slave Address Match callback.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
TransferDirection | Master request Transfer Direction (Write/Read), value of I2C Transfer Direction Master Point of View
AddrMatchCode | Address Match Code
Return values:
None

Definition at line 4430 of file stm32wbxx_hal_i2c.c.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterAddrCallback(), and I2C_ITAddrCplt().

void HAL_I2C_ER_IRQHandler ( I2C_HandleTypeDef * hi2c )

This function handles I2C error interrupt request.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4316 of file stm32wbxx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_ARLO, HAL_I2C_ERROR_BERR, HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_OVR, I2C_CHECK_FLAG, I2C_CHECK_IT_SOURCE, I2C_FLAG_ARLO, I2C_FLAG_BERR, I2C_FLAG_OVR, I2C_IT_ERRI, I2C_ITError(), and __I2C_HandleTypeDef::Instance.

void HAL_I2C_ErrorCallback ( I2C_HandleTypeDef * hi2c )

I2C error callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4496 of file stm32wbxx_hal_i2c.c.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterCallback(), I2C_DMAAbort(), and I2C_ITError().

void HAL_I2C_EV_IRQHandler ( I2C_HandleTypeDef * hi2c )

This function handles I2C event interrupt request.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4297 of file stm32wbxx_hal_i2c.c.

References __I2C_HandleTypeDef::Instance, and __I2C_HandleTypeDef::XferISR.

void HAL_I2C_ListenCpltCallback ( I2C_HandleTypeDef * hi2c )

Listen Complete callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4448 of file stm32wbxx_hal_i2c.c.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterCallback(), I2C_ITListenCplt(), and I2C_ITSlaveCplt().

void HAL_I2C_MasterRxCpltCallback ( I2C_HandleTypeDef * hi2c )

Master Rx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4381 of file stm32wbxx_hal_i2c.c.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterCallback(), I2C_ITMasterCplt(), and I2C_ITMasterSeqCplt().

void HAL_I2C_MasterTxCpltCallback ( I2C_HandleTypeDef * hi2c )

Master Tx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4365 of file stm32wbxx_hal_i2c.c.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterCallback(), I2C_ITMasterCplt(), and I2C_ITMasterSeqCplt().

void HAL_I2C_MemRxCpltCallback ( I2C_HandleTypeDef * hi2c )

Memory Rx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4480 of file stm32wbxx_hal_i2c.c.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterCallback(), and I2C_ITMasterCplt().

void HAL_I2C_MemTxCpltCallback ( I2C_HandleTypeDef * hi2c )

Memory Tx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4464 of file stm32wbxx_hal_i2c.c.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterCallback(), and I2C_ITMasterCplt().

void HAL_I2C_SlaveRxCpltCallback ( I2C_HandleTypeDef * hi2c )

Slave Rx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4412 of file stm32wbxx_hal_i2c.c.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterCallback(), I2C_ITSlaveCplt(), and I2C_ITSlaveSeqCplt().

void HAL_I2C_SlaveTxCpltCallback ( I2C_HandleTypeDef * hi2c )

Slave Tx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 4396 of file stm32wbxx_hal_i2c.c.

Referenced by HAL_I2C_Init(), HAL_I2C_UnRegisterCallback(), I2C_ITSlaveCplt(), and I2C_ITSlaveSeqCplt().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Peripheral State, Mode and Error functions

Functions
Peripheral State, Mode and Error functions
I2C Exported Functions

Peripheral State, Mode and Error functions. More...

Functions

HAL_I2C_StateTypeDef | HAL_I2C_GetState (I2C_HandleTypeDef *hi2c)
Return the I2C handle state.
HAL_I2C_ModeTypeDef | HAL_I2C_GetMode (I2C_HandleTypeDef *hi2c)
Returns the I2C Master, Slave, Memory or no mode.
uint32_t | HAL_I2C_GetError (I2C_HandleTypeDef *hi2c)
Return the I2C error code.

Detailed Description

Peripheral State, Mode and Error functions.

 ===============================================================================
            ##### Peripheral State, Mode and Error functions #####
 ===============================================================================
    [..]
    This subsection permit to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

uint32_t HAL_I2C_GetError ( I2C_HandleTypeDef * hi2c )

Return the I2C error code.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
I2C Error Code

Definition at line 4570 of file stm32wbxx_hal_i2c.c.

References __I2C_HandleTypeDef::ErrorCode.

HAL_I2C_ModeTypeDef HAL_I2C_GetMode ( I2C_HandleTypeDef * hi2c )

Returns the I2C Master, Slave, Memory or no mode.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL mode

Definition at line 4559 of file stm32wbxx_hal_i2c.c.

References __I2C_HandleTypeDef::Mode.

HAL_I2C_StateTypeDef HAL_I2C_GetState ( I2C_HandleTypeDef * hi2c )

Return the I2C handle state.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL state

Definition at line 4547 of file stm32wbxx_hal_i2c.c.

References __I2C_HandleTypeDef::State.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: I2C_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
I2C_InitTypeDef Struct Reference
I2C Configuration Structure definition

#include <stm32wbxx_hal_i2c.h>

Data Fields

uint32_t | Timing
uint32_t | OwnAddress1
uint32_t | AddressingMode
uint32_t | DualAddressMode
uint32_t | OwnAddress2
uint32_t | OwnAddress2Masks
uint32_t | GeneralCallMode
uint32_t | NoStretchMode

Detailed Description

Definition at line 48 of file stm32wbxx_hal_i2c.h.

Field Documentation

uint32_t I2C_InitTypeDef::AddressingMode

Specifies if 7-bit or 10-bit addressing mode is selected. This parameter can be a value of I2C Addressing Mode

Definition at line 57 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Slave_Transmit(), and I2C_ITAddrCplt().

uint32_t I2C_InitTypeDef::DualAddressMode

Specifies if dual addressing mode is selected. This parameter can be a value of I2C Dual Addressing Mode

Definition at line 60 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::GeneralCallMode

Specifies if general call mode is selected. This parameter can be a value of I2C General Call Addressing Mode

Definition at line 69 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::NoStretchMode

Specifies if nostretch mode is selected. This parameter can be a value of I2C No-Stretch Mode

Definition at line 72 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::OwnAddress1

Specifies the first device own address. This parameter can be a 7-bit or 10-bit address.

Definition at line 54 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::OwnAddress2

Specifies the second device own address if dual addressing mode is selected This parameter can be a 7-bit address.

Definition at line 63 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::OwnAddress2Masks

Specifies the acknowledge mask address second device own address if dual addressing mode is selected This parameter can be a value of I2C Own Address2 Masks

Definition at line 66 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::Timing

Specifies the I2C_TIMINGR_register value. This parameter calculated by referring to I2C initialization section in Reference manual

Definition at line 50 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Init().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_i2c.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: HAL state structure definition

Enumerations
HAL state structure definition
I2C Exported Types | PKA Exported Types

HAL State structure definition. More...

Enumerations

enum HAL_I2C_StateTypeDef {
HAL_I2C_STATE_RESET = 0x00U, HAL_I2C_STATE_READY = 0x20U, HAL_I2C_STATE_BUSY = 0x24U, HAL_I2C_STATE_BUSY_TX = 0x21U,
HAL_I2C_STATE_BUSY_RX = 0x22U, HAL_I2C_STATE_LISTEN = 0x28U, HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU,
HAL_I2C_STATE_ABORT = 0x60U, HAL_I2C_STATE_TIMEOUT = 0xA0U, HAL_I2C_STATE_ERROR = 0xE0U
}
enum HAL_PKA_StateTypeDef { HAL_PKA_STATE_RESET = 0x00U, HAL_PKA_STATE_READY = 0x01U, HAL_PKA_STATE_BUSY = 0x02U, HAL_PKA_STATE_ERROR = 0x03U }

Detailed Description

HAL State structure definition.

HAL State structures definition.

Note:
HAL I2C State value coding follow below described bitmap :
b7-b6 Error information
00 : No Error
01 : Abort (Abort user request on going)
10 : Timeout
11 : Error
b5 Peripheral initialization status
0 : Reset (peripheral not initialized)
1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)
b4 (not used)
x : Should be set to 0
b3
0 : Ready or Busy (No Listen mode ongoing)
1 : Listen (peripheral in Address Listen Mode)
b2 Intrinsic process state
0 : Ready
1 : Busy (peripheral busy with some configuration or internal operations)
b1 Rx state
0 : Ready (no Rx operation ongoing)
1 : Busy (Rx operation ongoing)
b0 Tx state
0 : Ready (no Tx operation ongoing)
1 : Busy (Tx operation ongoing)

Enumeration Type Documentation

enum HAL_I2C_StateTypeDef
Enumerator:
HAL_I2C_STATE_RESET

Peripheral is not yet Initialized

HAL_I2C_STATE_READY

Peripheral Initialized and ready for use

HAL_I2C_STATE_BUSY

An internal process is ongoing

HAL_I2C_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_I2C_STATE_BUSY_RX

Data Reception process is ongoing

HAL_I2C_STATE_LISTEN

Address Listen Mode is ongoing

HAL_I2C_STATE_BUSY_TX_LISTEN

Address Listen Mode and Data Transmission process is ongoing

HAL_I2C_STATE_BUSY_RX_LISTEN

Address Listen Mode and Data Reception process is ongoing

HAL_I2C_STATE_ABORT

Abort user request ongoing

HAL_I2C_STATE_TIMEOUT

Timeout state

HAL_I2C_STATE_ERROR

Error

Definition at line 108 of file stm32wbxx_hal_i2c.h.

enum HAL_PKA_StateTypeDef
Enumerator:
HAL_PKA_STATE_RESET

PKA not yet initialized or disabled

HAL_PKA_STATE_READY

PKA initialized and ready for use

HAL_PKA_STATE_BUSY

PKA internal processing is ongoing

HAL_PKA_STATE_ERROR

PKA error state

Definition at line 50 of file stm32wbxx_hal_pka.h.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: HAL mode structure definition

Enumerations
HAL mode structure definition
I2C Exported Types

HAL Mode structure definition. More...

Enumerations

enum HAL_I2C_ModeTypeDef { HAL_I2C_MODE_NONE = 0x00U, HAL_I2C_MODE_MASTER = 0x10U, HAL_I2C_MODE_SLAVE = 0x20U, HAL_I2C_MODE_MEM = 0x40U }

Detailed Description

HAL Mode structure definition.

Note:
HAL I2C Mode value coding follow below described bitmap :
b7 (not used)
x : Should be set to 0
b6
0 : None
1 : Memory (HAL I2C communication is in Memory Mode)
b5
0 : None
1 : Slave (HAL I2C communication is in Slave Mode)
b4
0 : None
1 : Master (HAL I2C communication is in Master Mode)
b3-b2-b1-b0 (not used)
xxxx : Should be set to 0000

Enumeration Type Documentation

enum HAL_I2C_ModeTypeDef
Enumerator:
HAL_I2C_MODE_NONE

No I2C communication on going

HAL_I2C_MODE_MASTER

I2C communication is in Master Mode

HAL_I2C_MODE_SLAVE

I2C communication is in Slave Mode

HAL_I2C_MODE_MEM

I2C communication is in Memory Mode

Definition at line 148 of file stm32wbxx_hal_i2c.h.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: I2C Error Code definition

Defines
I2C Error Code definition
I2C Exported Types

I2C Error Code definition. More...

Defines

#define | HAL_I2C_ERROR_NONE (0x00000000U)
#define | HAL_I2C_ERROR_BERR (0x00000001U)
#define | HAL_I2C_ERROR_ARLO (0x00000002U)
#define | HAL_I2C_ERROR_AF (0x00000004U)
#define | HAL_I2C_ERROR_OVR (0x00000008U)
#define | HAL_I2C_ERROR_DMA (0x00000010U)
#define | HAL_I2C_ERROR_TIMEOUT (0x00000020U)
#define | HAL_I2C_ERROR_SIZE (0x00000040U)
#define | HAL_I2C_ERROR_DMA_PARAM (0x00000080U)
#define | HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U)
#define | HAL_I2C_ERROR_INVALID_PARAM (0x00000200U)

Detailed Description

I2C Error Code definition.

Define Documentation

#define HAL_I2C_ERROR_AF (0x00000004U)

ACKF error

Definition at line 168 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Transmit(), I2C_IsAcknowledgeFailed(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define HAL_I2C_ERROR_ARLO (0x00000002U)

ARLO error

Definition at line 167 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define HAL_I2C_ERROR_BERR (0x00000001U)

BERR error

Definition at line 166 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define HAL_I2C_ERROR_DMA (0x00000010U)

DMA transfer error

Definition at line 170 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Transmit_DMA(), I2C_DMAError(), I2C_DMAMasterReceiveCplt(), and I2C_DMAMasterTransmitCplt().

#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U)

DMA Parameter Error

Definition at line 173 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Transmit_DMA(), and HAL_I2C_Slave_Transmit_DMA().

#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U)

Invalid Callback error

Definition at line 175 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_RegisterAddrCallback(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterAddrCallback(), and HAL_I2C_UnRegisterCallback().

#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U)

Invalid Parameters error

Definition at line 177 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), and HAL_I2C_Slave_Transmit_DMA().

#define HAL_I2C_ERROR_NONE (0x00000000U)

No error

Definition at line 165 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_ER_IRQHandler(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define HAL_I2C_ERROR_OVR (0x00000008U)

OVR error

Definition at line 169 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define HAL_I2C_ERROR_SIZE (0x00000040U)

Size Management error

Definition at line 172 of file stm32wbxx_hal_i2c.h.

Referenced by I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

#define HAL_I2C_ERROR_TIMEOUT (0x00000020U)

Timeout error

Definition at line 171 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), I2C_IsAcknowledgeFailed(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: I2C handle Structure definition

Data Structures | Typedefs | Enumerations
I2C handle Structure definition
I2C Exported Types

I2C handle Structure definition. More...

Data Structures

struct | __I2C_HandleTypeDef

Typedefs

typedef struct __I2C_HandleTypeDef | I2C_HandleTypeDef
typedef void(* | pI2C_CallbackTypeDef )(I2C_HandleTypeDef *hi2c)
HAL I2C Callback pointer definition.
typedef void(* | pI2C_AddrCallbackTypeDef )(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)

Enumerations

enum HAL_I2C_CallbackIDTypeDef {
HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U,
HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, HAL_I2C_ERROR_CB_ID = 0x07U,
HAL_I2C_ABORT_CB_ID = 0x08U, HAL_I2C_MSPINIT_CB_ID = 0x09U, HAL_I2C_MSPDEINIT_CB_ID = 0x0AU
}
HAL I2C Callback ID enumeration definition. More...

Detailed Description

I2C handle Structure definition.

Typedef Documentation

typedef struct __I2C_HandleTypeDef I2C_HandleTypeDef
typedef void(* pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)

pointer to an I2C Address Match callback function

Definition at line 263 of file stm32wbxx_hal_i2c.h.

typedef void(* pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c)

HAL I2C Callback pointer definition.

pointer to an I2C callback function

Definition at line 262 of file stm32wbxx_hal_i2c.h.

Enumeration Type Documentation

enum HAL_I2C_CallbackIDTypeDef

HAL I2C Callback ID enumeration definition.

Enumerator:
HAL_I2C_MASTER_TX_COMPLETE_CB_ID

I2C Master Tx Transfer completed callback ID

HAL_I2C_MASTER_RX_COMPLETE_CB_ID

I2C Master Rx Transfer completed callback ID

HAL_I2C_SLAVE_TX_COMPLETE_CB_ID

I2C Slave Tx Transfer completed callback ID

HAL_I2C_SLAVE_RX_COMPLETE_CB_ID

I2C Slave Rx Transfer completed callback ID

HAL_I2C_LISTEN_COMPLETE_CB_ID

I2C Listen Complete callback ID

HAL_I2C_MEM_TX_COMPLETE_CB_ID

I2C Memory Tx Transfer callback ID

HAL_I2C_MEM_RX_COMPLETE_CB_ID

I2C Memory Rx Transfer completed callback ID

HAL_I2C_ERROR_CB_ID

I2C Error callback ID

HAL_I2C_ABORT_CB_ID

I2C Abort callback ID

HAL_I2C_MSPINIT_CB_ID

I2C Msp Init callback ID

HAL_I2C_MSPDEINIT_CB_ID

I2C Msp DeInit callback ID

Definition at line 242 of file stm32wbxx_hal_i2c.h.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: __I2C_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__I2C_HandleTypeDef Struct Reference
I2C handle Structure definition

#include <stm32wbxx_hal_i2c.h>

Data Fields

I2C_TypeDef * | Instance
I2C_InitTypeDef Init
uint8_t * | pBuffPtr
uint16_t | XferSize
__IO uint16_t | XferCount
__IO uint32_t | XferOptions
__IO uint32_t | PreviousState
HAL_StatusTypeDef(* | XferISR )(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_I2C_StateTypeDef | State
__IO HAL_I2C_ModeTypeDef | Mode
__IO uint32_t | ErrorCode
__IO uint32_t | AddrEventCount
void(* | MasterTxCpltCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | MasterRxCpltCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | SlaveTxCpltCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | SlaveRxCpltCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | ListenCpltCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | MemTxCpltCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | MemRxCpltCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | ErrorCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | AbortCpltCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | AddrCallback )(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
void(* | MspInitCallback )(struct __I2C_HandleTypeDef *hi2c)
void(* | MspDeInitCallback )(struct __I2C_HandleTypeDef *hi2c)

Detailed Description

Definition at line 186 of file stm32wbxx_hal_i2c.h.

Field Documentation

void(* __I2C_HandleTypeDef::AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Abort callback

Definition at line 228 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), I2C_DMAAbort(), and I2C_ITError().

void(* __I2C_HandleTypeDef::AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)

I2C Slave Address Match callback

Definition at line 230 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterAddrCallback(), HAL_I2C_UnRegisterAddrCallback(), and I2C_ITAddrCplt().

__IO uint32_t __I2C_HandleTypeDef::AddrEventCount

I2C Address Event counter

Definition at line 217 of file stm32wbxx_hal_i2c.h.

Referenced by I2C_ITAddrCplt().

void(* __I2C_HandleTypeDef::ErrorCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Error callback

Definition at line 227 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), I2C_DMAAbort(), and I2C_ITError().

__IO uint32_t __I2C_HandleTypeDef::ErrorCode

I2C Error code

Definition at line 215 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_ER_IRQHandler(), HAL_I2C_GetError(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_RegisterAddrCallback(), HAL_I2C_RegisterCallback(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), HAL_I2C_UnRegisterAddrCallback(), HAL_I2C_UnRegisterCallback(), I2C_IsAcknowledgeFailed(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), I2C_Slave_ISR_IT(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

DMA_HandleTypeDef* __I2C_HandleTypeDef::hdmarx

I2C Rx DMA handle parameters

Definition at line 207 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), I2C_DMAAbort(), I2C_DMAMasterReceiveCplt(), I2C_DMASlaveReceiveCplt(), I2C_ITError(), I2C_ITSlaveCplt(), and I2C_Slave_ISR_DMA().

DMA_HandleTypeDef* __I2C_HandleTypeDef::hdmatx

I2C Tx DMA handle parameters

Definition at line 205 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Transmit_DMA(), I2C_DMAAbort(), I2C_DMAMasterTransmitCplt(), I2C_ITError(), I2C_ITSlaveCplt(), and I2C_Slave_ISR_DMA().

I2C_InitTypeDef __I2C_HandleTypeDef::Init

I2C communication parameters

Definition at line 190 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Slave_Transmit(), and I2C_ITAddrCplt().

I2C_TypeDef* __I2C_HandleTypeDef::Instance

I2C registers base address

Definition at line 188 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_ER_IRQHandler(), HAL_I2C_EV_IRQHandler(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), HAL_I2CEx_ConfigAnalogFilter(), HAL_I2CEx_ConfigDigitalFilter(), HAL_I2CEx_DisableWakeUp(), HAL_I2CEx_EnableWakeUp(), I2C_DMAError(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_DMASlaveReceiveCplt(), I2C_DMASlaveTransmitCplt(), I2C_Flush_TXDR(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_RequestMemoryRead(), I2C_RequestMemoryWrite(), I2C_Slave_ISR_IT(), and I2C_TransferConfig().

void(* __I2C_HandleTypeDef::ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Listen Complete callback

Definition at line 224 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), I2C_ITListenCplt(), and I2C_ITSlaveCplt().

HAL_LockTypeDef __I2C_HandleTypeDef::Lock

I2C locking object

Definition at line 209 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Init().

void(* __I2C_HandleTypeDef::MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Master Rx Transfer completed callback

Definition at line 221 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), I2C_ITMasterCplt(), and I2C_ITMasterSeqCplt().

void(* __I2C_HandleTypeDef::MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Master Tx Transfer completed callback

Definition at line 220 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), I2C_ITMasterCplt(), and I2C_ITMasterSeqCplt().

void(* __I2C_HandleTypeDef::MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Memory Rx Transfer completed callback

Definition at line 226 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), and I2C_ITMasterCplt().

void(* __I2C_HandleTypeDef::MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Memory Tx Transfer completed callback

Definition at line 225 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), and I2C_ITMasterCplt().

__IO HAL_I2C_ModeTypeDef __I2C_HandleTypeDef::Mode

I2C communication mode

Definition at line 213 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_DisableListen_IT(), HAL_I2C_GetMode(), HAL_I2C_Init(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_IsAcknowledgeFailed(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSeqCplt(), I2C_ITSlaveCplt(), I2C_ITSlaveSeqCplt(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

void(* __I2C_HandleTypeDef::MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Msp DeInit callback

Definition at line 233 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_RegisterCallback(), and HAL_I2C_UnRegisterCallback().

void(* __I2C_HandleTypeDef::MspInitCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Msp Init callback

Definition at line 232 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), and HAL_I2C_UnRegisterCallback().

uint8_t* __I2C_HandleTypeDef::pBuffPtr

Pointer to I2C transfer buffer

Definition at line 192 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_IT(), and I2C_Slave_ISR_IT().

__IO uint32_t __I2C_HandleTypeDef::PreviousState

I2C communication Previous state

Definition at line 201 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_DisableListen_IT(), HAL_I2C_Init(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSeqCplt(), I2C_ITSlaveCplt(), and I2C_ITSlaveSeqCplt().

void(* __I2C_HandleTypeDef::SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Slave Rx Transfer completed callback

Definition at line 223 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), I2C_ITSlaveCplt(), and I2C_ITSlaveSeqCplt().

void(* __I2C_HandleTypeDef::SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c)

I2C Slave Tx Transfer completed callback

Definition at line 222 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), I2C_ITSlaveCplt(), and I2C_ITSlaveSeqCplt().

__IO HAL_I2C_StateTypeDef __I2C_HandleTypeDef::State

I2C communication state

Definition at line 211 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_DisableListen_IT(), HAL_I2C_EnableListen_IT(), HAL_I2C_GetState(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_RegisterAddrCallback(), HAL_I2C_RegisterCallback(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), HAL_I2C_UnRegisterAddrCallback(), HAL_I2C_UnRegisterCallback(), HAL_I2CEx_ConfigAnalogFilter(), HAL_I2CEx_ConfigDigitalFilter(), HAL_I2CEx_DisableWakeUp(), HAL_I2CEx_EnableWakeUp(), I2C_Disable_IRQ(), I2C_DMAAbort(), I2C_IsAcknowledgeFailed(), I2C_ITAddrCplt(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSeqCplt(), I2C_ITSlaveCplt(), I2C_ITSlaveSeqCplt(), I2C_Master_ISR_DMA(), I2C_Slave_ISR_DMA(), I2C_Slave_ISR_IT(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

__IO uint16_t __I2C_HandleTypeDef::XferCount

I2C transfer counter

Definition at line 196 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), and I2C_Slave_ISR_IT().

HAL_StatusTypeDef(* __I2C_HandleTypeDef::XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)

I2C transfer IRQ handler function pointer

Definition at line 203 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_DisableListen_IT(), HAL_I2C_EnableListen_IT(), HAL_I2C_EV_IRQHandler(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_Enable_IRQ(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITMasterSeqCplt(), and I2C_ITSlaveCplt().

__IO uint32_t __I2C_HandleTypeDef::XferOptions

I2C sequantial transfer options, this parameter can be a value of I2C Sequential Transfer Options

Definition at line 198 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_ConvertOtherXferOptions(), I2C_DMASlaveReceiveCplt(), I2C_DMASlaveTransmitCplt(), I2C_ITError(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

uint16_t __I2C_HandleTypeDef::XferSize

I2C transfer size

Definition at line 194 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAMasterReceiveCplt(), I2C_DMAMasterTransmitCplt(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_IT(), and I2C_WaitOnRXNEFlagUntilTimeout().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_i2c.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: I2C Sequential Transfer Options

Defines
I2C Sequential Transfer Options
I2C Exported Constants

Defines

#define | I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
#define | I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define | I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define | I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define | I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define | I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)
#define | I2C_OTHER_FRAME (0x000000AAU)
#define | I2C_OTHER_AND_LAST_FRAME (0x0000AA00U)

Define Documentation

#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)

Definition at line 285 of file stm32wbxx_hal_i2c.h.

Referenced by I2C_ConvertOtherXferOptions(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))

Definition at line 283 of file stm32wbxx_hal_i2c.h.

#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)

Definition at line 282 of file stm32wbxx_hal_i2c.h.

Referenced by I2C_ConvertOtherXferOptions(), I2C_DMASlaveTransmitCplt(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)

Definition at line 286 of file stm32wbxx_hal_i2c.h.

#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)

Definition at line 287 of file stm32wbxx_hal_i2c.h.

#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))

Definition at line 284 of file stm32wbxx_hal_i2c.h.

Referenced by I2C_DMASlaveTransmitCplt(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U)

Definition at line 293 of file stm32wbxx_hal_i2c.h.

Referenced by I2C_ConvertOtherXferOptions().

#define I2C_OTHER_FRAME (0x000000AAU)

Definition at line 292 of file stm32wbxx_hal_i2c.h.

Referenced by I2C_ConvertOtherXferOptions().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: I2C Addressing Mode

Defines
I2C Addressing Mode
I2C Exported Constants

Defines

#define | I2C_ADDRESSINGMODE_7BIT (0x00000001U)
#define | I2C_ADDRESSINGMODE_10BIT (0x00000002U)

Define Documentation

#define I2C_ADDRESSINGMODE_10BIT (0x00000002U)

Definition at line 302 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_Slave_Transmit(), and I2C_ITAddrCplt().

#define I2C_ADDRESSINGMODE_7BIT (0x00000001U)

Definition at line 301 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Init().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: I2C Dual Addressing Mode

Defines
I2C Dual Addressing Mode
I2C Exported Constants

Defines

#define | I2C_DUALADDRESS_DISABLE (0x00000000U)
#define | I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN

Define Documentation

#define I2C_DUALADDRESS_DISABLE (0x00000000U)

Definition at line 310 of file stm32wbxx_hal_i2c.h.

#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN

Definition at line 311 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Init().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: I2C Own Address2 Masks

Defines
I2C Own Address2 Masks
I2C Exported Constants

Defines

#define | I2C_OA2_NOMASK ((uint8_t)0x00U)
#define | I2C_OA2_MASK01 ((uint8_t)0x01U)
#define | I2C_OA2_MASK02 ((uint8_t)0x02U)
#define | I2C_OA2_MASK03 ((uint8_t)0x03U)
#define | I2C_OA2_MASK04 ((uint8_t)0x04U)
#define | I2C_OA2_MASK05 ((uint8_t)0x05U)
#define | I2C_OA2_MASK06 ((uint8_t)0x06U)
#define | I2C_OA2_MASK07 ((uint8_t)0x07U)

Define Documentation

#define I2C_OA2_MASK01 ((uint8_t)0x01U)

Definition at line 320 of file stm32wbxx_hal_i2c.h.

#define I2C_OA2_MASK02 ((uint8_t)0x02U)

Definition at line 321 of file stm32wbxx_hal_i2c.h.

#define I2C_OA2_MASK03 ((uint8_t)0x03U)

Definition at line 322 of file stm32wbxx_hal_i2c.h.

#define I2C_OA2_MASK04 ((uint8_t)0x04U)

Definition at line 323 of file stm32wbxx_hal_i2c.h.

#define I2C_OA2_MASK05 ((uint8_t)0x05U)

Definition at line 324 of file stm32wbxx_hal_i2c.h.

#define I2C_OA2_MASK06 ((uint8_t)0x06U)

Definition at line 325 of file stm32wbxx_hal_i2c.h.

#define I2C_OA2_MASK07 ((uint8_t)0x07U)

Definition at line 326 of file stm32wbxx_hal_i2c.h.

#define I2C_OA2_NOMASK ((uint8_t)0x00U)

Definition at line 319 of file stm32wbxx_hal_i2c.h.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: I2C General Call Addressing Mode

Defines
I2C General Call Addressing Mode
I2C Exported Constants

Defines

#define | I2C_GENERALCALL_DISABLE (0x00000000U)
#define | I2C_GENERALCALL_ENABLE I2C_CR1_GCEN

Define Documentation

#define I2C_GENERALCALL_DISABLE (0x00000000U)

Definition at line 334 of file stm32wbxx_hal_i2c.h.

#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN

Definition at line 335 of file stm32wbxx_hal_i2c.h.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: I2C No-Stretch Mode

Defines
I2C No-Stretch Mode
I2C Exported Constants

Defines

#define | I2C_NOSTRETCH_DISABLE (0x00000000U)
#define | I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH

Define Documentation

#define I2C_NOSTRETCH_DISABLE (0x00000000U)

Definition at line 343 of file stm32wbxx_hal_i2c.h.

#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH

Definition at line 344 of file stm32wbxx_hal_i2c.h.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: I2C Memory Address Size

Defines
I2C Memory Address Size
I2C Exported Constants

Defines

#define | I2C_MEMADD_SIZE_8BIT (0x00000001U)
#define | I2C_MEMADD_SIZE_16BIT (0x00000002U)

Define Documentation

#define I2C_MEMADD_SIZE_16BIT (0x00000002U)

Definition at line 353 of file stm32wbxx_hal_i2c.h.

#define I2C_MEMADD_SIZE_8BIT (0x00000001U)

Definition at line 352 of file stm32wbxx_hal_i2c.h.

Referenced by I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: I2C Transfer Direction Master Point of View

Defines
I2C Transfer Direction Master Point of View
I2C Exported Constants

Defines

#define | I2C_DIRECTION_TRANSMIT (0x00000000U)
#define | I2C_DIRECTION_RECEIVE (0x00000001U)

Define Documentation

#define I2C_DIRECTION_RECEIVE (0x00000001U)

Definition at line 362 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Seq_Transmit_DMA(), and HAL_I2C_Slave_Seq_Transmit_IT().

#define I2C_DIRECTION_TRANSMIT (0x00000000U)

Definition at line 361 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Seq_Receive_DMA(), and HAL_I2C_Slave_Seq_Receive_IT().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: I2C Reload End Mode

Defines
I2C Reload End Mode
I2C Exported Constants

Defines

#define | I2C_RELOAD_MODE I2C_CR2_RELOAD
#define | I2C_AUTOEND_MODE I2C_CR2_AUTOEND
#define | I2C_SOFTEND_MODE (0x00000000U)

Define Documentation

#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND

Definition at line 371 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

#define I2C_RELOAD_MODE I2C_CR2_RELOAD

Definition at line 370 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), and I2C_RequestMemoryWrite().

#define I2C_SOFTEND_MODE (0x00000000U)

Definition at line 372 of file stm32wbxx_hal_i2c.h.

Referenced by I2C_RequestMemoryRead().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: I2C Start or Stop Mode

Defines
I2C Start or Stop Mode
I2C Exported Constants

Defines

#define | I2C_NO_STARTSTOP (0x00000000U)
#define | I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define | I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define | I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)

Define Documentation

#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)

Definition at line 382 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), and HAL_I2C_Mem_Read_IT().

#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)

Definition at line 383 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)

Definition at line 381 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Master_Abort_IT().

#define I2C_NO_STARTSTOP (0x00000000U)

Definition at line 380 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: I2C Interrupt configuration definition

Defines
I2C Interrupt configuration definition
I2C Exported Constants

I2C Interrupt definition Elements values convention: 0xXXXXXXXX. More...

Defines

#define | I2C_IT_ERRI I2C_CR1_ERRIE
#define | I2C_IT_TCI I2C_CR1_TCIE
#define | I2C_IT_STOPI I2C_CR1_STOPIE
#define | I2C_IT_NACKI I2C_CR1_NACKIE
#define | I2C_IT_ADDRI I2C_CR1_ADDRIE
#define | I2C_IT_RXI I2C_CR1_RXIE
#define | I2C_IT_TXI I2C_CR1_TXIE

Detailed Description

I2C Interrupt definition Elements values convention: 0xXXXXXXXX.

  • XXXXXXXX : Interrupt control mask

Define Documentation

#define I2C_IT_ADDRI I2C_CR1_ADDRIE

Definition at line 398 of file stm32wbxx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_IT_ERRI I2C_CR1_ERRIE

Definition at line 394 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), I2C_Disable_IRQ(), and I2C_Enable_IRQ().

#define I2C_IT_NACKI I2C_CR1_NACKIE

Definition at line 397 of file stm32wbxx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_IT_RXI I2C_CR1_RXIE

Definition at line 399 of file stm32wbxx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Master_ISR_IT(), and I2C_Slave_ISR_IT().

#define I2C_IT_STOPI I2C_CR1_STOPIE

Definition at line 396 of file stm32wbxx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_IT_TCI I2C_CR1_TCIE

Definition at line 395 of file stm32wbxx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

#define I2C_IT_TXI I2C_CR1_TXIE

Definition at line 400 of file stm32wbxx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), I2C_Enable_IRQ(), I2C_Master_ISR_IT(), and I2C_Slave_ISR_IT().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: I2C Flag definition

Defines
I2C Flag definition
I2C Exported Constants

Defines

#define | I2C_FLAG_TXE I2C_ISR_TXE
#define | I2C_FLAG_TXIS I2C_ISR_TXIS
#define | I2C_FLAG_RXNE I2C_ISR_RXNE
#define | I2C_FLAG_ADDR I2C_ISR_ADDR
#define | I2C_FLAG_AF I2C_ISR_NACKF
#define | I2C_FLAG_STOPF I2C_ISR_STOPF
#define | I2C_FLAG_TC I2C_ISR_TC
#define | I2C_FLAG_TCR I2C_ISR_TCR
#define | I2C_FLAG_BERR I2C_ISR_BERR
#define | I2C_FLAG_ARLO I2C_ISR_ARLO
#define | I2C_FLAG_OVR I2C_ISR_OVR
#define | I2C_FLAG_PECERR I2C_ISR_PECERR
#define | I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define | I2C_FLAG_ALERT I2C_ISR_ALERT
#define | I2C_FLAG_BUSY I2C_ISR_BUSY
#define | I2C_FLAG_DIR I2C_ISR_DIR

Define Documentation

#define I2C_FLAG_ADDR I2C_ISR_ADDR

Definition at line 411 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), I2C_ITAddrCplt(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_FLAG_AF I2C_ISR_NACKF

Definition at line 412 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), I2C_IsAcknowledgeFailed(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_FLAG_ALERT I2C_ISR_ALERT

Definition at line 421 of file stm32wbxx_hal_i2c.h.

#define I2C_FLAG_ARLO I2C_ISR_ARLO

Definition at line 417 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define I2C_FLAG_BERR I2C_ISR_BERR

Definition at line 416 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define I2C_FLAG_BUSY I2C_ISR_BUSY

Definition at line 422 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), and HAL_I2C_Slave_Transmit().

#define I2C_FLAG_DIR I2C_ISR_DIR

Definition at line 423 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Receive(), and HAL_I2C_Slave_Transmit().

#define I2C_FLAG_OVR I2C_ISR_OVR

Definition at line 418 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define I2C_FLAG_PECERR I2C_ISR_PECERR

Definition at line 419 of file stm32wbxx_hal_i2c.h.

#define I2C_FLAG_RXNE I2C_ISR_RXNE

Definition at line 410 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Mem_Read(), HAL_I2C_Slave_Receive(), I2C_ITListenCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_IT(), I2C_Slave_ISR_IT(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define I2C_FLAG_STOPF I2C_ISR_STOPF

Definition at line 413 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), I2C_IsAcknowledgeFailed(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), I2C_Slave_ISR_IT(), I2C_WaitOnRXNEFlagUntilTimeout(), and I2C_WaitOnSTOPFlagUntilTimeout().

#define I2C_FLAG_TC I2C_ISR_TC

Definition at line 414 of file stm32wbxx_hal_i2c.h.

Referenced by I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), and I2C_RequestMemoryRead().

#define I2C_FLAG_TCR I2C_ISR_TCR

Definition at line 415 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), and I2C_RequestMemoryWrite().

#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT

Definition at line 420 of file stm32wbxx_hal_i2c.h.

#define I2C_FLAG_TXE I2C_ISR_TXE

Definition at line 408 of file stm32wbxx_hal_i2c.h.

Referenced by I2C_Flush_TXDR().

#define I2C_FLAG_TXIS I2C_ISR_TXIS

Definition at line 409 of file stm32wbxx_hal_i2c.h.

Referenced by I2C_Flush_TXDR(), I2C_Master_ISR_IT(), I2C_Slave_ISR_IT(), and I2C_WaitOnTXISFlagUntilTimeout().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: I2C Exported Macros

Defines
I2C Exported Macros
I2C

Defines

#define | __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)
Reset I2C handle state.
#define | __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
Enable the specified I2C interrupt.
#define | __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
Disable the specified I2C interrupt.
#define | __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified I2C interrupt source is enabled or not.
#define | I2C_FLAG_MASK (0x0001FFFFU)
Check whether the specified I2C flag is set or not.
#define | __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
#define | __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
#define | __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Enable the specified I2C peripheral.
#define | __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Disable the specified I2C peripheral.
#define | __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
Generate a Non-Acknowledge I2C peripheral in Slave mode.

Define Documentation

#define __HAL_I2C_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
(((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
                                                                                : ((__HANDLE__)->Instance->ICR = (__FLAG__)))

Clear the I2C pending flags which are cleared by writing 1 in a specific bit.

Parameters:
__HANDLE__ specifies the I2C Handle.
__FLAG__ specifies the flag to clear. This parameter can be any combination of the following values:
  • I2C_FLAG_TXE Transmit data register empty
  • I2C_FLAG_ADDR Address matched (slave mode)
  • I2C_FLAG_AF Acknowledge failure received flag
  • I2C_FLAG_STOPF STOP detection flag
  • I2C_FLAG_BERR Bus error
  • I2C_FLAG_ARLO Arbitration lost
  • I2C_FLAG_OVR Overrun/Underrun
  • I2C_FLAG_PECERR PEC error in reception
  • I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
  • I2C_FLAG_ALERT SMBus alert
Return values:
None

Definition at line 543 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2C_Slave_Transmit(), I2C_Flush_TXDR(), I2C_IsAcknowledgeFailed(), I2C_ITAddrCplt(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), I2C_Slave_ISR_IT(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define __HAL_I2C_DISABLE ( __HANDLE__ ) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))

Disable the specified I2C peripheral.

Parameters:
__HANDLE__ specifies the I2C Handle.
Return values:
None

Definition at line 556 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_Init(), HAL_I2CEx_ConfigAnalogFilter(), HAL_I2CEx_ConfigDigitalFilter(), HAL_I2CEx_DisableWakeUp(), and HAL_I2CEx_EnableWakeUp().

#define __HAL_I2C_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))

Disable the specified I2C interrupt.

Parameters:
__HANDLE__ specifies the I2C Handle.
__INTERRUPT__ specifies the interrupt source to disable. This parameter can be one of the following values:
  • I2C_IT_ERRI Errors interrupt enable
  • I2C_IT_TCI Transfer complete interrupt enable
  • I2C_IT_STOPI STOP detection interrupt enable
  • I2C_IT_NACKI NACK received interrupt enable
  • I2C_IT_ADDRI Address match interrupt enable
  • I2C_IT_RXI RX interrupt enable
  • I2C_IT_TXI TX interrupt enable
Return values:
None

Definition at line 482 of file stm32wbxx_hal_i2c.h.

Referenced by I2C_Disable_IRQ(), and I2C_Master_ISR_DMA().

#define __HAL_I2C_ENABLE ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))

Enable the specified I2C peripheral.

Parameters:
__HANDLE__ specifies the I2C Handle.
Return values:
None

Definition at line 550 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2CEx_ConfigAnalogFilter(), HAL_I2CEx_ConfigDigitalFilter(), HAL_I2CEx_DisableWakeUp(), and HAL_I2CEx_EnableWakeUp().

#define __HAL_I2C_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))

Enable the specified I2C interrupt.

Parameters:
__HANDLE__ specifies the I2C Handle.
__INTERRUPT__ specifies the interrupt source to enable. This parameter can be one of the following values:
  • I2C_IT_ERRI Errors interrupt enable
  • I2C_IT_TCI Transfer complete interrupt enable
  • I2C_IT_STOPI STOP detection interrupt enable
  • I2C_IT_NACKI NACK received interrupt enable
  • I2C_IT_ADDRI Address match interrupt enable
  • I2C_IT_RXI RX interrupt enable
  • I2C_IT_TXI TX interrupt enable
Return values:
None

Definition at line 466 of file stm32wbxx_hal_i2c.h.

Referenced by I2C_Enable_IRQ().

#define __HAL_I2C_GENERATE_NACK ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))

Generate a Non-Acknowledge I2C peripheral in Slave mode.

Parameters:
__HANDLE__ specifies the I2C Handle.
Return values:
None

Definition at line 562 of file stm32wbxx_hal_i2c.h.

#define __HAL_I2C_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)

Definition at line 524 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), I2C_Flush_TXDR(), I2C_IsAcknowledgeFailed(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXISFlagUntilTimeout().

#define __HAL_I2C_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified I2C interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the I2C Handle.
__INTERRUPT__ specifies the I2C interrupt source to check. This parameter can be one of the following values:
  • I2C_IT_ERRI Errors interrupt enable
  • I2C_IT_TCI Transfer complete interrupt enable
  • I2C_IT_STOPI STOP detection interrupt enable
  • I2C_IT_NACKI NACK received interrupt enable
  • I2C_IT_ADDRI Address match interrupt enable
  • I2C_IT_RXI RX interrupt enable
  • I2C_IT_TXI TX interrupt enable
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 498 of file stm32wbxx_hal_i2c.h.

#define __HAL_I2C_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                   \
                                                                    (__HANDLE__)->State = HAL_I2C_STATE_RESET;       \
                                                                    (__HANDLE__)->MspInitCallback = NULL;            \
                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \
                                                                  } while(0)

Reset I2C handle state.

Parameters:
__HANDLE__ specifies the I2C Handle.
Return values:
None

Definition at line 443 of file stm32wbxx_hal_i2c.h.

#define I2C_FLAG_MASK (0x0001FFFFU)

Check whether the specified I2C flag is set or not.

Parameters:
__HANDLE__ specifies the I2C Handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • I2C_FLAG_TXE Transmit data register empty
  • I2C_FLAG_TXIS Transmit interrupt status
  • I2C_FLAG_RXNE Receive data register not empty
  • I2C_FLAG_ADDR Address matched (slave mode)
  • I2C_FLAG_AF Acknowledge failure received flag
  • I2C_FLAG_STOPF STOP detection flag
  • I2C_FLAG_TC Transfer complete (master mode)
  • I2C_FLAG_TCR Transfer complete reload
  • I2C_FLAG_BERR Bus error
  • I2C_FLAG_ARLO Arbitration lost
  • I2C_FLAG_OVR Overrun/Underrun
  • I2C_FLAG_PECERR PEC error in reception
  • I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
  • I2C_FLAG_ALERT SMBus alert
  • I2C_FLAG_BUSY Bus busy
  • I2C_FLAG_DIR Transfer direction (slave mode)
Return values:
The new state of __FLAG__ (SET or RESET).

Definition at line 523 of file stm32wbxx_hal_i2c.h.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: I2C Private Constants

I2C Private Constants
I2C
Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: I2C Private Macros

Defines
I2C Private Macros
I2C

Defines

#define | IS_I2C_ADDRESSING_MODE(MODE)
#define | IS_I2C_DUAL_ADDRESS(ADDRESS)
#define | IS_I2C_OWN_ADDRESS2_MASK(MASK)
#define | IS_I2C_GENERAL_CALL(CALL)
#define | IS_I2C_NO_STRETCH(STRETCH)
#define | IS_I2C_MEMADD_SIZE(SIZE)
#define | IS_TRANSFER_MODE(MODE)
#define | IS_TRANSFER_REQUEST(REQUEST)
#define | IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)
#define | IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)
#define | I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
#define | I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U))
#define | I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U))
#define | I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define | I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
#define | I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
#define | IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define | IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
#define | I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
#define | I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define | I2C_GENERATE_START(__ADDMODE__, __ADDRESS__)
#define | I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
#define | I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)

Define Documentation

#define I2C_CHECK_FLAG | ( | __ISR__,
 |  | __FLAG__
 | ) | ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)

Definition at line 752 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), I2C_ITListenCplt(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_CHECK_IT_SOURCE | ( | __CR1__,
 |  | __IT__
 | ) | ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)

Definition at line 753 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), I2C_ITSlaveCplt(), I2C_Master_ISR_DMA(), I2C_Master_ISR_IT(), I2C_Slave_ISR_DMA(), and I2C_Slave_ISR_IT().

#define I2C_GENERATE_START | ( | __ADDMODE__,
 |  | __ADDRESS__
 | ) |
Value:
(((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
                                                          (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))

Definition at line 749 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady().

#define I2C_GET_ADDR_MATCH ( __HANDLE__ ) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U))

Definition at line 737 of file stm32wbxx_hal_i2c.h.

Referenced by I2C_ITAddrCplt().

#define I2C_GET_DIR ( __HANDLE__ ) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U))

Definition at line 738 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), and I2C_ITAddrCplt().

#define I2C_GET_OWN_ADDRESS1 ( __HANDLE__ ) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))

Definition at line 740 of file stm32wbxx_hal_i2c.h.

Referenced by I2C_ITAddrCplt().

#define I2C_GET_OWN_ADDRESS2 ( __HANDLE__ ) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))

Definition at line 741 of file stm32wbxx_hal_i2c.h.

Referenced by I2C_ITAddrCplt().

#define I2C_GET_STOP_MODE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)

Definition at line 739 of file stm32wbxx_hal_i2c.h.

Referenced by I2C_Master_ISR_DMA(), and I2C_Master_ISR_IT().

#define I2C_MEM_ADD_LSB ( __ADDRESS__ ) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))

Definition at line 747 of file stm32wbxx_hal_i2c.h.

Referenced by I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

#define I2C_MEM_ADD_MSB ( __ADDRESS__ ) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))

Definition at line 746 of file stm32wbxx_hal_i2c.h.

Referenced by I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

#define I2C_RESET_CR2 ( __HANDLE__ ) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))

Definition at line 735 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), I2C_IsAcknowledgeFailed(), I2C_ITMasterCplt(), I2C_ITSlaveCplt(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define IS_I2C_ADDRESSING_MODE ( MODE )
Value:
(((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
                                         ((MODE) == I2C_ADDRESSINGMODE_10BIT))

Definition at line 691 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_DUAL_ADDRESS ( ADDRESS )
Value:
(((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
                                         ((ADDRESS) == I2C_DUALADDRESS_ENABLE))

Definition at line 694 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_GENERAL_CALL ( CALL )
Value:
(((CALL) == I2C_GENERALCALL_DISABLE) || \
                                         ((CALL) == I2C_GENERALCALL_ENABLE))

Definition at line 706 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_MEMADD_SIZE ( SIZE )
Value:
(((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
                                         ((SIZE) == I2C_MEMADD_SIZE_16BIT))

Definition at line 712 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), and HAL_I2C_Mem_Write_IT().

#define IS_I2C_NO_STRETCH ( STRETCH )
Value:
(((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
                                         ((STRETCH) == I2C_NOSTRETCH_ENABLE))

Definition at line 709 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_OWN_ADDRESS1 ( ADDRESS1 ) ((ADDRESS1) <= 0x000003FFU)

Definition at line 743 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_OWN_ADDRESS2 ( ADDRESS2 ) ((ADDRESS2) <= (uint16_t)0x00FFU)

Definition at line 744 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_OWN_ADDRESS2_MASK ( MASK )
Value:
(((MASK) == I2C_OA2_NOMASK)  || \
                                         ((MASK) == I2C_OA2_MASK01) || \
                                         ((MASK) == I2C_OA2_MASK02) || \
                                         ((MASK) == I2C_OA2_MASK03) || \
                                         ((MASK) == I2C_OA2_MASK04) || \
                                         ((MASK) == I2C_OA2_MASK05) || \
                                         ((MASK) == I2C_OA2_MASK06) || \
                                         ((MASK) == I2C_OA2_MASK07))

Definition at line 697 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_TRANSFER_OPTIONS_REQUEST ( REQUEST )
Value:
(((REQUEST) == I2C_FIRST_FRAME)          || \
                                                   ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
                                                   ((REQUEST) == I2C_NEXT_FRAME)           || \
                                                   ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
                                                   ((REQUEST) == I2C_LAST_FRAME)           || \
                                                   ((REQUEST) == I2C_LAST_FRAME_NO_STOP)   || \
                                                   IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))

Definition at line 724 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), and HAL_I2C_Slave_Seq_Transmit_IT().

#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST ( REQUEST )
Value:
(((REQUEST) == I2C_OTHER_FRAME)     || \
                                                        ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))

Definition at line 732 of file stm32wbxx_hal_i2c.h.

Referenced by HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), and HAL_I2C_Master_Seq_Transmit_IT().

#define IS_TRANSFER_MODE ( MODE )
Value:
(((MODE) == I2C_RELOAD_MODE)   || \
                                         ((MODE) == I2C_AUTOEND_MODE) || \
                                         ((MODE) == I2C_SOFTEND_MODE))

Definition at line 715 of file stm32wbxx_hal_i2c.h.

Referenced by I2C_TransferConfig().

#define IS_TRANSFER_REQUEST ( REQUEST )
Value:
(((REQUEST) == I2C_GENERATE_STOP)        || \
                                         ((REQUEST) == I2C_GENERATE_START_READ)  || \
                                         ((REQUEST) == I2C_GENERATE_START_WRITE) || \
                                         ((REQUEST) == I2C_NO_STARTSTOP))

Definition at line 719 of file stm32wbxx_hal_i2c.h.

Referenced by I2C_TransferConfig().

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STM32WB55xx HAL User Manual: I2C Extended Private Constants

I2C Extended Private Constants
Extended features functions
Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: I2C Extended Private Macros

Defines
I2C Extended Private Macros
Extended features functions

Defines

#define | IS_I2C_ANALOG_FILTER(FILTER)
#define | IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define | IS_I2C_FASTMODEPLUS(__CONFIG__)

Define Documentation

#define IS_I2C_ANALOG_FILTER ( FILTER )
Value:
(((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
                                          ((FILTER) == I2C_ANALOGFILTER_DISABLE))

Definition at line 110 of file stm32wbxx_hal_i2c_ex.h.

Referenced by HAL_I2CEx_ConfigAnalogFilter().

#define IS_I2C_DIGITAL_FILTER ( FILTER ) ((FILTER) <= 0x0000000FU)

Definition at line 113 of file stm32wbxx_hal_i2c_ex.h.

Referenced by HAL_I2CEx_ConfigDigitalFilter().

#define IS_I2C_FASTMODEPLUS ( __CONFIG__ )
Value:
((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6))  == I2C_FASTMODEPLUS_PB6)     || \
                                         (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7))  == I2C_FASTMODEPLUS_PB7)     || \
                                         (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8))  == I2C_FASTMODEPLUS_PB8)     || \
                                         (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9))  == I2C_FASTMODEPLUS_PB9)     || \
                                         (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1)    || \
                                         (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3))

Definition at line 115 of file stm32wbxx_hal_i2c_ex.h.

Referenced by HAL_I2CEx_DisableFastModePlus(), and HAL_I2CEx_EnableFastModePlus().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: I2C Extended Private Functions

I2C Extended Private Functions
Extended features functions
Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Extended features functions

Modules | Functions
Extended features functions
I2C Extended Exported Functions

Extended features functions. More...

Modules

I2C Extended Private Constants
I2C Extended Private Macros
I2C Extended Private Functions

Functions

HAL_StatusTypeDef | HAL_I2CEx_ConfigAnalogFilter (I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
Configure I2C Analog noise filter.
HAL_StatusTypeDef | HAL_I2CEx_ConfigDigitalFilter (I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
Configure I2C Digital noise filter.
HAL_StatusTypeDef | HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
Enable I2C wakeup from Stop mode(s).
HAL_StatusTypeDef | HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
Disable I2C wakeup from Stop mode(s).
void | HAL_I2CEx_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the I2C fast mode plus driving capability.
void | HAL_I2CEx_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the I2C fast mode plus driving capability.

Detailed Description

Extended features functions.

 ===============================================================================
                      ##### Extended features functions #####
 ===============================================================================
    [..] This section provides functions allowing to:
      (+) Configure Noise Filters
      (+) Configure Wake Up Feature
      (+) Configure Fast Mode Plus

Function Documentation

HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | AnalogFilter
 | ) |  |

Configure I2C Analog noise filter.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2Cx peripheral.
AnalogFilter | New state of the Analog filter.
Return values:
HAL status

Definition at line 97 of file stm32wbxx_hal_i2c_ex.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, assert_param, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::Instance, IS_I2C_ANALOG_FILTER, and __I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | DigitalFilter
 | ) |  |

Configure I2C Digital noise filter.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2Cx peripheral.
DigitalFilter | Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
Return values:
HAL status

Definition at line 141 of file stm32wbxx_hal_i2c_ex.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, assert_param, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::Instance, IS_I2C_DIGITAL_FILTER, and __I2C_HandleTypeDef::State.

void HAL_I2CEx_DisableFastModePlus ( uint32_t ConfigFastModePlus )

Disable the I2C fast mode plus driving capability.

Parameters:
ConfigFastModePlus Selects the pin. This parameter can be one of the I2C Extended Fast Mode Plus values
Note:
For I2C1, fast mode plus driving capability can be disabled on all selected I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently on each one of the following pins PB6, PB7, PB8 and PB9.
For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
For all I2C3 pins fast mode plus driving capability can be disabled only by using I2C_FASTMODEPLUS_I2C3 parameter.
Return values:
None

Definition at line 299 of file stm32wbxx_hal_i2c_ex.c.

References assert_param, and IS_I2C_FASTMODEPLUS.

HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp ( I2C_HandleTypeDef * hi2c )

Disable I2C wakeup from Stop mode(s).

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2Cx peripheral.
Return values:
HAL status

Definition at line 231 of file stm32wbxx_hal_i2c_ex.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, assert_param, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::Instance, and __I2C_HandleTypeDef::State.

void HAL_I2CEx_EnableFastModePlus ( uint32_t ConfigFastModePlus )

Enable the I2C fast mode plus driving capability.

Parameters:
ConfigFastModePlus Selects the pin. This parameter can be one of the I2C Extended Fast Mode Plus values
Note:
For I2C1, fast mode plus driving capability can be enabled on all selected I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently on each one of the following pins PB6, PB7, PB8 and PB9.
For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
For all I2C3 pins fast mode plus driving capability can be enabled only by using I2C_FASTMODEPLUS_I2C3 parameter.
Return values:
None

Definition at line 277 of file stm32wbxx_hal_i2c_ex.c.

References assert_param, and IS_I2C_FASTMODEPLUS.

HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp ( I2C_HandleTypeDef * hi2c )

Enable I2C wakeup from Stop mode(s).

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2Cx peripheral.
Return values:
HAL status

Definition at line 192 of file stm32wbxx_hal_i2c_ex.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, assert_param, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, __I2C_HandleTypeDef::Instance, and __I2C_HandleTypeDef::State.

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STM32WB55xx HAL User Manual: I2C Extended Analog Filter

Defines
I2C Extended Analog Filter
I2C Extended Exported Constants

Defines

#define | I2C_ANALOGFILTER_ENABLE 0x00000000U
#define | I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Define Documentation

#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Definition at line 50 of file stm32wbxx_hal_i2c_ex.h.

#define I2C_ANALOGFILTER_ENABLE 0x00000000U

Definition at line 49 of file stm32wbxx_hal_i2c_ex.h.

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STM32WB55xx HAL User Manual: I2C Extended Fast Mode Plus

Defines
I2C Extended Fast Mode Plus
I2C Extended Exported Constants

Defines

#define | I2C_FMP_NOT_SUPPORTED 0xAAAA0000U
#define | I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP
#define | I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP
#define | I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP
#define | I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP
#define | I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP
#define | I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP

Define Documentation

#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP

Enable Fast Mode Plus on I2C1 pins

Definition at line 63 of file stm32wbxx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP

Enable Fast Mode Plus on I2C3 pins

Definition at line 65 of file stm32wbxx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP

Enable Fast Mode Plus on PB6

Definition at line 59 of file stm32wbxx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP

Enable Fast Mode Plus on PB7

Definition at line 60 of file stm32wbxx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP

Enable Fast Mode Plus on PB8

Definition at line 61 of file stm32wbxx_hal_i2c_ex.h.

#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP

Enable Fast Mode Plus on PB9

Definition at line 62 of file stm32wbxx_hal_i2c_ex.h.

#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U

Fast Mode Plus not supported

Definition at line 58 of file stm32wbxx_hal_i2c_ex.h.

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STM32WB55xx HAL User Manual: IPCC Private Constants

Defines
IPCC Private Constants
IPCC

Defines

#define | IPCC_ALL_RX_BUF 0x0000003FU
#define | IPCC_ALL_TX_BUF 0x003F0000U
#define | CHANNEL_INDEX_Msk 0x0000000FU

Define Documentation

#define CHANNEL_INDEX_Msk 0x0000000FU

Mask the channel index to avoid overflow

Definition at line 75 of file stm32wbxx_hal_ipcc.c.

Referenced by HAL_IPCC_ActivateNotification(), HAL_IPCC_DeActivateNotification(), HAL_IPCC_GetChannelStatus(), HAL_IPCC_NotifyCPU(), HAL_IPCC_RX_IRQHandler(), HAL_IPCC_TX_IRQHandler(), IPCC_MaskInterrupt(), and IPCC_UnmaskInterrupt().

#define IPCC_ALL_RX_BUF 0x0000003FU

Mask for all RX buffers.

Definition at line 73 of file stm32wbxx_hal_ipcc.c.

Referenced by HAL_IPCC_RX_IRQHandler(), and IPCC_Reset_Register().

#define IPCC_ALL_TX_BUF 0x003F0000U

Mask for all TX buffers.

Definition at line 74 of file stm32wbxx_hal_ipcc.c.

Referenced by HAL_IPCC_TX_IRQHandler(), and IPCC_Reset_Register().

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STM32WB55xx HAL User Manual: IPCC Private Functions

Functions
IPCC Private Functions
IPCC

Functions

void | IPCC_MaskInterrupt (uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
Mask IPCC interrupts.
void | IPCC_UnmaskInterrupt (uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
Unmask IPCC interrupts.
void | IPCC_SetDefaultCallbacks (IPCC_HandleTypeDef *hipcc)
Reset all callbacks of the handle to NULL.
void | IPCC_Reset_Register (IPCC_CommonTypeDef *Instance)
Reset IPCC register to default value for the concerned instance.

Function Documentation

void IPCC_MaskInterrupt | ( | uint32_t | ChannelIndex,
 |  | IPCC_CHANNELDirTypeDef | ChannelDir
 | ) |  |

Mask IPCC interrupts.

Parameters:
ChannelIndex Channel number This parameter can be one of the following values:
  • IPCC_CHANNEL_1: IPCC Channel 1
  • IPCC_CHANNEL_2: IPCC Channel 2
  • IPCC_CHANNEL_3: IPCC Channel 3
  • IPCC_CHANNEL_4: IPCC Channel 4
  • IPCC_CHANNEL_5: IPCC Channel 5
  • IPCC_CHANNEL_6: IPCC Channel 6
ChannelDir Channel direction

Definition at line 660 of file stm32wbxx_hal_ipcc.c.

References CHANNEL_INDEX_Msk, and IPCC_CHANNEL_DIR_TX.

Referenced by HAL_IPCC_DeActivateNotification().

void IPCC_Reset_Register ( IPCC_CommonTypeDef * Instance )

Reset IPCC register to default value for the concerned instance.

Parameters:
Instance pointer to register

Definition at line 720 of file stm32wbxx_hal_ipcc.c.

References IPCC_ALL_RX_BUF, and IPCC_ALL_TX_BUF.

Referenced by HAL_IPCC_DeInit(), and HAL_IPCC_Init().

void IPCC_SetDefaultCallbacks ( IPCC_HandleTypeDef * hipcc )

Reset all callbacks of the handle to NULL.

Parameters:
hipcc IPCC handle

Definition at line 705 of file stm32wbxx_hal_ipcc.c.

References __IPCC_HandleTypeDef::ChannelCallbackRx, __IPCC_HandleTypeDef::ChannelCallbackTx, HAL_IPCC_RxCallback(), and HAL_IPCC_TxCallback().

Referenced by HAL_IPCC_DeInit(), and HAL_IPCC_Init().

void IPCC_UnmaskInterrupt | ( | uint32_t | ChannelIndex,
 |  | IPCC_CHANNELDirTypeDef | ChannelDir
 | ) |  |

Unmask IPCC interrupts.

Parameters:
ChannelIndex Channel number This parameter can be one of the following values:
  • IPCC_CHANNEL_1: IPCC Channel 1
  • IPCC_CHANNEL_2: IPCC Channel 2
  • IPCC_CHANNEL_3: IPCC Channel 3
  • IPCC_CHANNEL_4: IPCC Channel 4
  • IPCC_CHANNEL_5: IPCC Channel 5
  • IPCC_CHANNEL_6: IPCC Channel 6
ChannelDir Channel direction

Definition at line 686 of file stm32wbxx_hal_ipcc.c.

References CHANNEL_INDEX_Msk, and IPCC_CHANNEL_DIR_TX.

Referenced by HAL_IPCC_ActivateNotification(), and HAL_IPCC_NotifyCPU().

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STM32WB55xx HAL User Manual: IPCC Channel

Defines
IPCC Channel
IPCC Exported Constants

Defines

#define | IPCC_CHANNEL_1 0x00000000U
#define | IPCC_CHANNEL_2 0x00000001U
#define | IPCC_CHANNEL_3 0x00000002U
#define | IPCC_CHANNEL_4 0x00000003U
#define | IPCC_CHANNEL_5 0x00000004U
#define | IPCC_CHANNEL_6 0x00000005U

Define Documentation

#define IPCC_CHANNEL_1 0x00000000U

Definition at line 50 of file stm32wbxx_hal_ipcc.h.

#define IPCC_CHANNEL_2 0x00000001U

Definition at line 51 of file stm32wbxx_hal_ipcc.h.

#define IPCC_CHANNEL_3 0x00000002U

Definition at line 52 of file stm32wbxx_hal_ipcc.h.

#define IPCC_CHANNEL_4 0x00000003U

Definition at line 53 of file stm32wbxx_hal_ipcc.h.

#define IPCC_CHANNEL_5 0x00000004U

Definition at line 54 of file stm32wbxx_hal_ipcc.h.

#define IPCC_CHANNEL_6 0x00000005U

Definition at line 55 of file stm32wbxx_hal_ipcc.h.

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STM32WB55xx HAL User Manual: IPCC Exported Types

Data Structures | Typedefs | Enumerations
IPCC Exported Types
IPCC

Data Structures

struct | __IPCC_HandleTypeDef
IPCC handle structure definition. More...

Typedefs

typedef struct __IPCC_HandleTypeDef | IPCC_HandleTypeDef
IPCC handle structure definition.
typedef void | ChannelCb (IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
IPCC callback typedef.

Enumerations

enum | HAL_IPCC_StateTypeDef { HAL_IPCC_STATE_RESET = 0x00U, HAL_IPCC_STATE_READY = 0x01U, HAL_IPCC_STATE_BUSY = 0x02U }
HAL IPCC State structures definition. More...
enum | IPCC_CHANNELDirTypeDef { IPCC_CHANNEL_DIR_TX = 0x00U, IPCC_CHANNEL_DIR_RX = 0x01U }
IPCC channel direction structure definition. More...
enum | IPCC_CHANNELStatusTypeDef { IPCC_CHANNEL_STATUS_FREE = 0x00U, IPCC_CHANNEL_STATUS_OCCUPIED = 0x01U }
IPCC channel status structure definition. More...

Typedef Documentation

typedef void ChannelCb(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)

IPCC callback typedef.

Definition at line 112 of file stm32wbxx_hal_ipcc.h.

typedef struct __IPCC_HandleTypeDef IPCC_HandleTypeDef

IPCC handle structure definition.

Enumeration Type Documentation

enum HAL_IPCC_StateTypeDef

HAL IPCC State structures definition.

Enumerator:
HAL_IPCC_STATE_RESET

IPCC not yet initialized or disabled

HAL_IPCC_STATE_READY

IPCC initialized and ready for use

HAL_IPCC_STATE_BUSY

IPCC internal processing is ongoing

Definition at line 72 of file stm32wbxx_hal_ipcc.h.

enum IPCC_CHANNELDirTypeDef

IPCC channel direction structure definition.

Enumerator:
IPCC_CHANNEL_DIR_TX

Channel direction Tx is used by an MCU to transmit

IPCC_CHANNEL_DIR_RX

Channel direction Rx is used by an MCU to receive

Definition at line 82 of file stm32wbxx_hal_ipcc.h.

enum IPCC_CHANNELStatusTypeDef

IPCC channel status structure definition.

Enumerator:
IPCC_CHANNEL_STATUS_FREE

Means that a new msg can be posted on that channel

IPCC_CHANNEL_STATUS_OCCUPIED

An MCU has posted a msg the other MCU hasn't retrieved

Definition at line 91 of file stm32wbxx_hal_ipcc.h.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: __IPCC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__IPCC_HandleTypeDef Struct Reference
IPCC Exported Types

IPCC handle structure definition. More...

#include <stm32wbxx_hal_ipcc.h>

Data Fields

IPCC_TypeDef * | Instance
void(* | ChannelCallbackRx [IPCC_CHANNEL_NUMBER])(struct __IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
void(* | ChannelCallbackTx [IPCC_CHANNEL_NUMBER])(struct __IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
uint32_t | callbackRequest
__IO HAL_IPCC_StateTypeDef | State

Detailed Description

IPCC handle structure definition.

Definition at line 100 of file stm32wbxx_hal_ipcc.h.

Field Documentation

uint32_t __IPCC_HandleTypeDef::callbackRequest

Store information about callback notification by channel

Definition at line 105 of file stm32wbxx_hal_ipcc.h.

Referenced by HAL_IPCC_ActivateNotification(), HAL_IPCC_DeActivateNotification(), HAL_IPCC_DeInit(), HAL_IPCC_Init(), and HAL_IPCC_NotifyCPU().

void(* __IPCC_HandleTypeDef::ChannelCallbackRx[IPCC_CHANNEL_NUMBER])(struct __IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)

Rx Callback registration table

Definition at line 103 of file stm32wbxx_hal_ipcc.h.

Referenced by HAL_IPCC_ActivateNotification(), HAL_IPCC_DeActivateNotification(), HAL_IPCC_RX_IRQHandler(), and IPCC_SetDefaultCallbacks().

void(* __IPCC_HandleTypeDef::ChannelCallbackTx[IPCC_CHANNEL_NUMBER])(struct __IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)

Tx Callback registration table

Definition at line 104 of file stm32wbxx_hal_ipcc.h.

Referenced by HAL_IPCC_ActivateNotification(), HAL_IPCC_DeActivateNotification(), HAL_IPCC_TX_IRQHandler(), and IPCC_SetDefaultCallbacks().

IPCC_TypeDef* __IPCC_HandleTypeDef::Instance

IPCC registers base address

Definition at line 102 of file stm32wbxx_hal_ipcc.h.

Referenced by HAL_IPCC_ActivateNotification(), HAL_IPCC_DeActivateNotification(), HAL_IPCC_DeInit(), HAL_IPCC_GetChannelStatus(), HAL_IPCC_Init(), and HAL_IPCC_NotifyCPU().

__IO HAL_IPCC_StateTypeDef __IPCC_HandleTypeDef::State

IPCC State: initialized or not

Definition at line 106 of file stm32wbxx_hal_ipcc.h.

Referenced by HAL_IPCC_ActivateNotification(), HAL_IPCC_DeActivateNotification(), HAL_IPCC_DeInit(), HAL_IPCC_GetState(), HAL_IPCC_Init(), and HAL_IPCC_NotifyCPU().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_ipcc.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IPCC Exported Macros

Defines
IPCC Exported Macros
IPCC

Defines

#define | __HAL_IPCC_ENABLE_IT(__HANDLE__, __CHDIRECTION__)
Enable the specified interrupt.
#define | __HAL_IPCC_DISABLE_IT(__HANDLE__, __CHDIRECTION__)
Disable the specified interrupt.
#define | __HAL_IPCC_MASK_CHANNEL_IT(__HANDLE__, __CHDIRECTION__, __CHINDEX__)
Mask the specified interrupt.
#define | __HAL_IPCC_UNMASK_CHANNEL_IT(__HANDLE__, __CHDIRECTION__, __CHINDEX__)
Unmask the specified interrupt.

Define Documentation

#define __HAL_IPCC_DISABLE_IT | ( | __HANDLE__,
 |  | __CHDIRECTION__
 | ) |
Value:
(((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
                ((__HANDLE__)->Instance->C1CR &= ~IPCC_C1CR_RXOIE) : \
                ((__HANDLE__)->Instance->C1CR &= ~IPCC_C1CR_TXFIE))

Disable the specified interrupt.

Parameters:
__HANDLE__ specifies the IPCC Handle
__CHDIRECTION__ specifies the channels Direction This parameter can be one of the following values:
  • IPCC_CHANNEL_DIR_TX Transmit channel free interrupt enable
  • IPCC_CHANNEL_DIR_RX Receive channel occupied interrupt enable

Definition at line 144 of file stm32wbxx_hal_ipcc.h.

#define __HAL_IPCC_ENABLE_IT | ( | __HANDLE__,
 |  | __CHDIRECTION__
 | ) |
Value:
(((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
                ((__HANDLE__)->Instance->C1CR |= IPCC_C1CR_RXOIE) : \
                ((__HANDLE__)->Instance->C1CR |= IPCC_C1CR_TXFIE))

Enable the specified interrupt.

Parameters:
__HANDLE__ specifies the IPCC Handle
__CHDIRECTION__ specifies the channels Direction This parameter can be one of the following values:
  • IPCC_CHANNEL_DIR_TX Transmit channel free interrupt enable
  • IPCC_CHANNEL_DIR_RX Receive channel occupied interrupt enable

Definition at line 131 of file stm32wbxx_hal_ipcc.h.

#define __HAL_IPCC_MASK_CHANNEL_IT | ( | __HANDLE__,
 |  | __CHDIRECTION__,
 |  | __CHINDEX__
 | ) |
Value:
(((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
                ((__HANDLE__)->Instance->C1MR |= (IPCC_C1MR_CH1OM_Msk << (__CHINDEX__))) : \
                ((__HANDLE__)->Instance->C1MR |= (IPCC_C1MR_CH1FM_Msk << (__CHINDEX__))))

Mask the specified interrupt.

Parameters:
__HANDLE__ specifies the IPCC Handle
__CHDIRECTION__ specifies the channels Direction This parameter can be one of the following values:
  • IPCC_CHANNEL_DIR_TX Transmit channel free interrupt enable
  • IPCC_CHANNEL_DIR_RX Receive channel occupied interrupt enable
__CHINDEX__ specifies the channels number: This parameter can be one of the following values:
  • IPCC_CHANNEL_1: IPCC Channel 1
  • IPCC_CHANNEL_2: IPCC Channel 2
  • IPCC_CHANNEL_3: IPCC Channel 3
  • IPCC_CHANNEL_4: IPCC Channel 4
  • IPCC_CHANNEL_5: IPCC Channel 5
  • IPCC_CHANNEL_6: IPCC Channel 6

Definition at line 165 of file stm32wbxx_hal_ipcc.h.

#define __HAL_IPCC_UNMASK_CHANNEL_IT | ( | __HANDLE__,
 |  | __CHDIRECTION__,
 |  | __CHINDEX__
 | ) |
Value:
(((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
                ((__HANDLE__)->Instance->C1MR &= ~(IPCC_C1MR_CH1OM_Msk << (__CHINDEX__))) : \
                ((__HANDLE__)->Instance->C1MR &= ~(IPCC_C1MR_CH1FM_Msk << (__CHINDEX__))))

Unmask the specified interrupt.

Parameters:
__HANDLE__ specifies the IPCC Handle
__CHDIRECTION__ specifies the channels Direction This parameter can be one of the following values:
  • IPCC_CHANNEL_DIR_TX Transmit channel free interrupt enable
  • IPCC_CHANNEL_DIR_RX Receive channel occupied interrupt enable
__CHINDEX__ specifies the channels number: This parameter can be one of the following values:
  • IPCC_CHANNEL_1: IPCC Channel 1
  • IPCC_CHANNEL_2: IPCC Channel 2
  • IPCC_CHANNEL_3: IPCC Channel 3
  • IPCC_CHANNEL_4: IPCC Channel 4
  • IPCC_CHANNEL_5: IPCC Channel 5
  • IPCC_CHANNEL_6: IPCC Channel 6

Definition at line 186 of file stm32wbxx_hal_ipcc.h.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization and deinitialization functions

Functions
Initialization and deinitialization functions
IPCC Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_IPCC_Init (IPCC_HandleTypeDef *hipcc)
Initialize the IPCC peripheral.
HAL_StatusTypeDef | HAL_IPCC_DeInit (IPCC_HandleTypeDef *hipcc)
DeInitialize the IPCC peripheral.
__weak void | HAL_IPCC_MspInit (IPCC_HandleTypeDef *hipcc)
Initialize the IPCC MSP.
__weak void | HAL_IPCC_MspDeInit (IPCC_HandleTypeDef *hipcc)
IPCC MSP DeInit.

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
             ##### Initialization and de-initialization functions  #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          deinitialize the IPCC peripheral:

      (+) User must Implement HAL_IPCC_MspInit() function in which he configures
          all related peripherals resources (CLOCK and NVIC ).

      (+) Call the function HAL_IPCC_Init() to configure the IPCC register.

      (+) Call the function HAL_PKA_DeInit() to restore the default configuration
          of the selected IPCC peripheral.

Function Documentation

HAL_StatusTypeDef HAL_IPCC_DeInit ( IPCC_HandleTypeDef * hipcc )

DeInitialize the IPCC peripheral.

Parameters:
hipcc IPCC handle
Return values:
HAL status

Definition at line 170 of file stm32wbxx_hal_ipcc.c.

References assert_param, __IPCC_HandleTypeDef::callbackRequest, HAL_IPCC_MspDeInit(), HAL_IPCC_STATE_BUSY, HAL_IPCC_STATE_RESET, __IPCC_HandleTypeDef::Instance, IPCC_Reset_Register(), IPCC_SetDefaultCallbacks(), and __IPCC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_IPCC_Init ( IPCC_HandleTypeDef * hipcc )

Initialize the IPCC peripheral.

Parameters:
hipcc IPCC handle
Return values:
HAL status

Definition at line 125 of file stm32wbxx_hal_ipcc.c.

References assert_param, __IPCC_HandleTypeDef::callbackRequest, HAL_IPCC_MspInit(), HAL_IPCC_STATE_READY, HAL_IPCC_STATE_RESET, __IPCC_HandleTypeDef::Instance, IPCC_Reset_Register(), IPCC_SetDefaultCallbacks(), and __IPCC_HandleTypeDef::State.

void HAL_IPCC_MspDeInit ( IPCC_HandleTypeDef * hipcc )

IPCC MSP DeInit.

Parameters:
hipcc IPCC handle
Return values:
None

Definition at line 225 of file stm32wbxx_hal_ipcc.c.

Referenced by HAL_IPCC_DeInit().

void HAL_IPCC_MspInit ( IPCC_HandleTypeDef * hipcc )

Initialize the IPCC MSP.

Parameters:
hipcc IPCC handle
Return values:
None

Definition at line 210 of file stm32wbxx_hal_ipcc.c.

Referenced by HAL_IPCC_Init().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Communication functions

Functions
Communication functions
IPCC Exported Functions

Configuration, notification and Irq handling functions. More...

Functions

HAL_StatusTypeDef | HAL_IPCC_ActivateNotification (IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir, ChannelCb cb)
Activate the callback notification on receive/transmit interrupt.
HAL_StatusTypeDef | HAL_IPCC_DeActivateNotification (IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
Remove the callback notification on receive/transmit interrupt.
IPCC_CHANNELStatusTypeDef | HAL_IPCC_GetChannelStatus (IPCC_HandleTypeDef const *const hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
Get state of IPCC channel.
HAL_StatusTypeDef | HAL_IPCC_NotifyCPU (IPCC_HandleTypeDef const *const hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
Notify remote processor.

Detailed Description

Configuration, notification and Irq handling functions.

 ===============================================================================
              ##### IO operation functions #####
 ===============================================================================
    [..]  This section provides functions to allow two MCU to communicate.

    (#) For a given channel (from 0 to IPCC_CHANNEL_NUMBER), for a given direction
        IPCC_CHANNEL_DIR_TX or IPCC_CHANNEL_DIR_RX, you can choose to communicate
        in polling mode or in interrupt mode using IPCC.
        By default, the IPCC HAL driver handle the communication in polling mode.
        By setting a callback for a channel/direction, this communication use
        the interrupt mode.

    (#) Polling mode:
       (++) To transmit information, use HAL_IPCC_NotifyCPU() with
            IPCC_CHANNEL_DIR_TX. To know when the other processor has handled
            the notification, poll the communication using HAL_IPCC_NotifyCPU
            with IPCC_CHANNEL_DIR_TX.

       (++) To receive information, poll the status of the communication with
            HAL_IPCC_GetChannelStatus with IPCC_CHANNEL_DIR_RX. To notify the other
            processor that the information has been received, use HAL_IPCC_NotifyCPU
            with IPCC_CHANNEL_DIR_RX.

    (#) Interrupt mode:
       (++) Configure a callback for the channel and the direction using HAL_IPCC_ConfigChannel().
            This callback will be triggered under interrupt.

       (++) To transmit information, use HAL_IPCC_NotifyCPU() with
            IPCC_CHANNEL_DIR_TX. The callback configured with HAL_IPCC_ConfigChannel() and
            IPCC_CHANNEL_DIR_TX will be triggered once the communication has been handled by the
            other processor.

       (++) To receive information, the callback configured with HAL_IPCC_ConfigChannel() and
            IPCC_CHANNEL_DIR_RX will be triggered on reception of a communication.To notify the other
            processor that the information has been received, use HAL_IPCC_NotifyCPU
            with IPCC_CHANNEL_DIR_RX.

       (++) HAL_IPCC_TX_IRQHandler must be added to the IPCC TX IRQHandler

       (++) HAL_IPCC_RX_IRQHandler must be added to the IPCC RX IRQHandler

Function Documentation

HAL_StatusTypeDef HAL_IPCC_ActivateNotification | ( | IPCC_HandleTypeDef * | hipcc,
 |  | uint32_t | ChannelIndex,
 |  | IPCC_CHANNELDirTypeDef | ChannelDir,
 |  | ChannelCb | cb
 | ) |  |

Activate the callback notification on receive/transmit interrupt.

Parameters:
hipcc | IPCC handle
ChannelIndex Channel number This parameter can be one of the following values:
  • IPCC_CHANNEL_1: IPCC Channel 1
  • IPCC_CHANNEL_2: IPCC Channel 2
  • IPCC_CHANNEL_3: IPCC Channel 3
  • IPCC_CHANNEL_4: IPCC Channel 4
  • IPCC_CHANNEL_5: IPCC Channel 5
  • IPCC_CHANNEL_6: IPCC Channel 6
ChannelDir | Channel direction
cb | Interrupt callback
Return values:
HAL status

Definition at line 303 of file stm32wbxx_hal_ipcc.c.

References assert_param, __IPCC_HandleTypeDef::callbackRequest, CHANNEL_INDEX_Msk, __IPCC_HandleTypeDef::ChannelCallbackRx, __IPCC_HandleTypeDef::ChannelCallbackTx, HAL_IPCC_STATE_READY, __IPCC_HandleTypeDef::Instance, IPCC_CHANNEL_DIR_RX, IPCC_CHANNEL_DIR_TX, IPCC_UnmaskInterrupt(), and __IPCC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_IPCC_DeActivateNotification | ( | IPCC_HandleTypeDef * | hipcc,
 |  | uint32_t | ChannelIndex,
 |  | IPCC_CHANNELDirTypeDef | ChannelDir
 | ) |  |

Remove the callback notification on receive/transmit interrupt.

Parameters:
hipcc | IPCC handle
ChannelIndex Channel number This parameter can be one of the following values:
  • IPCC_CHANNEL_1: IPCC Channel 1
  • IPCC_CHANNEL_2: IPCC Channel 2
  • IPCC_CHANNEL_3: IPCC Channel 3
  • IPCC_CHANNEL_4: IPCC Channel 4
  • IPCC_CHANNEL_5: IPCC Channel 5
  • IPCC_CHANNEL_6: IPCC Channel 6
ChannelDir | Channel direction
Return values:
HAL status

Definition at line 360 of file stm32wbxx_hal_ipcc.c.

References assert_param, __IPCC_HandleTypeDef::callbackRequest, CHANNEL_INDEX_Msk, __IPCC_HandleTypeDef::ChannelCallbackRx, __IPCC_HandleTypeDef::ChannelCallbackTx, HAL_IPCC_RxCallback(), HAL_IPCC_STATE_READY, HAL_IPCC_TxCallback(), __IPCC_HandleTypeDef::Instance, IPCC_CHANNEL_DIR_TX, IPCC_MaskInterrupt(), and __IPCC_HandleTypeDef::State.

IPCC_CHANNELStatusTypeDef HAL_IPCC_GetChannelStatus | ( | IPCC_HandleTypeDef const *const | hipcc,
 |  | uint32_t | ChannelIndex,
 |  | IPCC_CHANNELDirTypeDef | ChannelDir
 | ) |  |

Get state of IPCC channel.

Parameters:
hipcc | IPCC handle
ChannelIndex Channel number This parameter can be one of the following values:
  • IPCC_CHANNEL_1: IPCC Channel 1
  • IPCC_CHANNEL_2: IPCC Channel 2
  • IPCC_CHANNEL_3: IPCC Channel 3
  • IPCC_CHANNEL_4: IPCC Channel 4
  • IPCC_CHANNEL_5: IPCC Channel 5
  • IPCC_CHANNEL_6: IPCC Channel 6
ChannelDir | Channel direction
Return values:
Channel status

Definition at line 414 of file stm32wbxx_hal_ipcc.c.

References assert_param, CHANNEL_INDEX_Msk, __IPCC_HandleTypeDef::Instance, IPCC_CHANNEL_DIR_TX, IPCC_CHANNEL_STATUS_FREE, and IPCC_CHANNEL_STATUS_OCCUPIED.

HAL_StatusTypeDef HAL_IPCC_NotifyCPU | ( | IPCC_HandleTypeDef const *const | hipcc,
 |  | uint32_t | ChannelIndex,
 |  | IPCC_CHANNELDirTypeDef | ChannelDir
 | ) |  |

Notify remote processor.

Parameters:
hipcc | IPCC handle
ChannelIndex Channel number This parameter can be one of the following values:
  • IPCC_CHANNEL_1: IPCC Channel 1
  • IPCC_CHANNEL_2: IPCC Channel 2
  • IPCC_CHANNEL_3: IPCC Channel 3
  • IPCC_CHANNEL_4: IPCC Channel 4
  • IPCC_CHANNEL_5: IPCC Channel 5
  • IPCC_CHANNEL_6: IPCC Channel 6
ChannelDir | Channel direction
Return values:
HAL status

Definition at line 450 of file stm32wbxx_hal_ipcc.c.

References assert_param, __IPCC_HandleTypeDef::callbackRequest, CHANNEL_INDEX_Msk, HAL_IPCC_STATE_READY, __IPCC_HandleTypeDef::Instance, IPCC_CHANNEL_DIR_TX, IPCC_UnmaskInterrupt(), and __IPCC_HandleTypeDef::State.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Peripheral State and Error functions

Functions
Peripheral State and Error functions
IPCC Exported Functions

IPCC Peripheral State and Error functions. More...

Functions

HAL_IPCC_StateTypeDef HAL_IPCC_GetState (IPCC_HandleTypeDef const *const hipcc)
Return the IPCC handle state.

Detailed Description

IPCC Peripheral State and Error functions.

  ==============================================================================
            ##### Peripheral State and Error functions #####
  ==============================================================================
    [..]
    This subsection permit to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

HAL_IPCC_StateTypeDef HAL_IPCC_GetState ( IPCC_HandleTypeDef const *const hipcc )

Return the IPCC handle state.

Parameters:
hipcc IPCC handle
Return values:
IPCC handle state

Definition at line 631 of file stm32wbxx_hal_ipcc.c.

References __IPCC_HandleTypeDef::State.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Peripheral IRQ Handler and Callbacks

Functions
Peripheral IRQ Handler and Callbacks
IPCC Exported Functions

Functions

void | HAL_IPCC_TX_IRQHandler (IPCC_HandleTypeDef *const hipcc)
This function handles IPCC Tx Free interrupt request.
void | HAL_IPCC_RX_IRQHandler (IPCC_HandleTypeDef *const hipcc)
This function handles IPCC Rx Occupied interrupt request.
__weak void | HAL_IPCC_RxCallback (IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
Rx occupied callback.
__weak void | HAL_IPCC_TxCallback (IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
Tx free callback.

Function Documentation

void HAL_IPCC_RX_IRQHandler ( IPCC_HandleTypeDef *const hipcc )

This function handles IPCC Rx Occupied interrupt request.

Parameters:
hipcc : IPCC handle
Return values:
None

Definition at line 527 of file stm32wbxx_hal_ipcc.c.

References CHANNEL_INDEX_Msk, __IPCC_HandleTypeDef::ChannelCallbackRx, IPCC_ALL_RX_BUF, and IPCC_CHANNEL_DIR_RX.

void HAL_IPCC_RxCallback | ( | IPCC_HandleTypeDef * | hipcc,
 |  | uint32_t | ChannelIndex,
 |  | IPCC_CHANNELDirTypeDef | ChannelDir
 | ) |  |

Rx occupied callback.

Parameters:
hipcc | IPCC handle
ChannelIndex Channel number This parameter can be one of the following values:
  • IPCC_CHANNEL_1: IPCC Channel 1
  • IPCC_CHANNEL_2: IPCC Channel 2
  • IPCC_CHANNEL_3: IPCC Channel 3
  • IPCC_CHANNEL_4: IPCC Channel 4
  • IPCC_CHANNEL_5: IPCC Channel 5
  • IPCC_CHANNEL_6: IPCC Channel 6
ChannelDir | Channel direction

Definition at line 570 of file stm32wbxx_hal_ipcc.c.

Referenced by HAL_IPCC_DeActivateNotification(), and IPCC_SetDefaultCallbacks().

void HAL_IPCC_TX_IRQHandler ( IPCC_HandleTypeDef *const hipcc )

This function handles IPCC Tx Free interrupt request.

Parameters:
hipcc IPCC handle
Return values:
None

Definition at line 493 of file stm32wbxx_hal_ipcc.c.

References CHANNEL_INDEX_Msk, __IPCC_HandleTypeDef::ChannelCallbackTx, IPCC_ALL_TX_BUF, and IPCC_CHANNEL_DIR_TX.

void HAL_IPCC_TxCallback | ( | IPCC_HandleTypeDef * | hipcc,
 |  | uint32_t | ChannelIndex,
 |  | IPCC_CHANNELDirTypeDef | ChannelDir
 | ) |  |

Tx free callback.

Parameters:
hipcc | IPCC handle
ChannelIndex Channel number This parameter can be one of the following values:
  • IPCC_CHANNEL_1: IPCC Channel 1
  • IPCC_CHANNEL_2: IPCC Channel 2
  • IPCC_CHANNEL_3: IPCC Channel 3
  • IPCC_CHANNEL_4: IPCC Channel 4
  • IPCC_CHANNEL_5: IPCC Channel 5
  • IPCC_CHANNEL_6: IPCC Channel 6
ChannelDir | Channel direction

Definition at line 595 of file stm32wbxx_hal_ipcc.c.

Referenced by HAL_IPCC_DeActivateNotification(), and IPCC_SetDefaultCallbacks().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IRDA Private Constants

Defines
IRDA Private Constants
IRDA

Defines

#define | IRDA_TEACK_REACK_TIMEOUT 1000U
#define | IRDA_CR1_FIELDS
#define | USART_BRR_MIN 0x10U
#define | USART_BRR_MAX 0x0000FFFFU

Define Documentation

#define IRDA_CR1_FIELDS
Value:
((uint32_t)(USART_CR1_M | USART_CR1_PCE \
                                   | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE))

UART or USART CR1 fields of parameters set by IRDA_SetConfig API

Definition at line 209 of file stm32wbxx_hal_irda.c.

Referenced by IRDA_SetConfig().

#define IRDA_TEACK_REACK_TIMEOUT 1000U

IRDA TX or RX enable acknowledge time-out value

Definition at line 207 of file stm32wbxx_hal_irda.c.

Referenced by IRDA_CheckIdleState().

#define USART_BRR_MAX 0x0000FFFFU

USART BRR maximum authorized value

Definition at line 214 of file stm32wbxx_hal_irda.c.

Referenced by IRDA_SetConfig().

#define USART_BRR_MIN 0x10U

USART BRR minimum authorized value

Definition at line 212 of file stm32wbxx_hal_irda.c.

Referenced by IRDA_SetConfig().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IRDA Private Macros

Defines
IRDA Private Macros
IRDA

Defines

#define | IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__, __PRESCALER__) ((((__PCLK__)/IRDAPrescTable[(__PRESCALER__)]) + ((__BAUD__)/2U)) / (__BAUD__))
BRR division operation to set BRR register in 16-bit oversampling mode.
#define | IRDA_MASK_COMPUTATION(__HANDLE__)
Compute the mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U)
Ensure that IRDA Baud rate is less or equal to maximum value.
#define | IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U)
Ensure that IRDA prescaler value is strictly larger than 0.
#define | IS_IRDA_WORD_LENGTH(__LENGTH__)
Ensure that IRDA frame length is valid.
#define | IS_IRDA_PARITY(__PARITY__)
Ensure that IRDA frame parity is valid.
#define | IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
Ensure that IRDA communication mode is valid.
#define | IS_IRDA_POWERMODE(__MODE__)
Ensure that IRDA power mode is valid.
#define | IS_IRDA_CLOCKPRESCALER(__CLOCKPRESCALER__)
Ensure that IRDA clock Prescaler is valid.
#define | IS_IRDA_STATE(__STATE__)
Ensure that IRDA state is valid.
#define | IS_IRDA_MODE(__MODE__)
Ensure that IRDA associated UART/USART mode is valid.
#define | IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that IRDA sampling rate is valid.
#define | IS_IRDA_DMA_TX(__DMATX__)
Ensure that IRDA DMA TX mode is valid.
#define | IS_IRDA_DMA_RX(__DMARX__)
Ensure that IRDA DMA RX mode is valid.
#define | IS_IRDA_REQUEST_PARAMETER(__PARAM__)
Ensure that IRDA request is valid.

Define Documentation

#define IRDA_DIV_SAMPLING16 | ( | __PCLK__,
 |  | __BAUD__,
 |  | __PRESCALER__
 | ) | ((((__PCLK__)/IRDAPrescTable[(__PRESCALER__)]) + ((__BAUD__)/2U)) / (__BAUD__))

BRR division operation to set BRR register in 16-bit oversampling mode.

Parameters:
__PCLK__ | IRDA clock source.
__BAUD__ | Baud rate set by the user.
__PRESCALER__ | IRDA clock prescaler value.
Return values:
Division result

Definition at line 229 of file stm32wbxx_hal_irda.c.

Referenced by IRDA_SetConfig().

#define IRDA_MASK_COMPUTATION ( __HANDLE__ )

Compute the mask to apply to retrieve the received data according to the word length and to the parity bits activation.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None,the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.

Definition at line 702 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), and HAL_IRDA_Receive_IT().

#define IS_IRDA_BAUDRATE ( __BAUDRATE__ ) ((__BAUDRATE__) < 115201U)

Ensure that IRDA Baud rate is less or equal to maximum value.

Parameters:
__BAUDRATE__ specifies the IRDA Baudrate set by the user.
Return values:
True or False

Definition at line 747 of file stm32wbxx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_CLOCKPRESCALER ( __CLOCKPRESCALER__ )
Value:
(((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV1) || \
              ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV2)   || \
              ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV4)   || \
              ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV6)   || \
              ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV8)   || \
              ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV10)  || \
              ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV12)  || \
              ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV16)  || \
              ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV32)  || \
              ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV64)  || \
              ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV128) || \
              ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV256))

Ensure that IRDA clock Prescaler is valid.

Parameters:
__CLOCKPRESCALER__ IRDA clock Prescaler value.
Return values:
SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)

Definition at line 793 of file stm32wbxx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_DMA_RX ( __DMARX__ )
Value:
(((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
                                   ((__DMARX__) == IRDA_DMA_RX_ENABLE))

Ensure that IRDA DMA RX mode is valid.

Parameters:
__DMARX__ IRDA DMA RX mode.
Return values:
SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)

Definition at line 843 of file stm32wbxx_hal_irda.h.

#define IS_IRDA_DMA_TX ( __DMATX__ )
Value:
(((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
                                       ((__DMATX__) == IRDA_DMA_TX_ENABLE))

Ensure that IRDA DMA TX mode is valid.

Parameters:
__DMATX__ IRDA DMA TX mode.
Return values:
SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)

Definition at line 835 of file stm32wbxx_hal_irda.h.

#define IS_IRDA_MODE ( __MODE__ )
Value:
(((__MODE__) == IRDA_MODE_DISABLE) || \
                                 ((__MODE__) == IRDA_MODE_ENABLE))

Ensure that IRDA associated UART/USART mode is valid.

Parameters:
__MODE__ IRDA associated UART/USART mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 819 of file stm32wbxx_hal_irda.h.

#define IS_IRDA_ONE_BIT_SAMPLE ( __ONEBIT__ )
Value:
(((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
                                                 ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))

Ensure that IRDA sampling rate is valid.

Parameters:
__ONEBIT__ IRDA sampling rate.
Return values:
SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)

Definition at line 827 of file stm32wbxx_hal_irda.h.

#define IS_IRDA_PARITY ( __PARITY__ )
Value:
(((__PARITY__) == IRDA_PARITY_NONE) || \
                                    ((__PARITY__) == IRDA_PARITY_EVEN) || \
                                    ((__PARITY__) == IRDA_PARITY_ODD))

Ensure that IRDA frame parity is valid.

Parameters:
__PARITY__ IRDA frame parity.
Return values:
SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)

Definition at line 769 of file stm32wbxx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_POWERMODE ( __MODE__ )
Value:
(((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
                                     ((__MODE__) == IRDA_POWERMODE_NORMAL))

Ensure that IRDA power mode is valid.

Parameters:
__MODE__ IRDA power mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 785 of file stm32wbxx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_PRESCALER ( __PRESCALER__ ) ((__PRESCALER__) > 0U)

Ensure that IRDA prescaler value is strictly larger than 0.

Parameters:
__PRESCALER__ specifies the IRDA prescaler value set by the user.
Return values:
True or False

Definition at line 753 of file stm32wbxx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_REQUEST_PARAMETER ( __PARAM__ )
Value:
(((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \
                                              ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
                                              ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))

Ensure that IRDA request is valid.

Parameters:
__PARAM__ IRDA request.
Return values:
SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)

Definition at line 851 of file stm32wbxx_hal_irda.h.

#define IS_IRDA_STATE ( __STATE__ )
Value:
(((__STATE__) == IRDA_STATE_DISABLE) || \
                                  ((__STATE__) == IRDA_STATE_ENABLE))

Ensure that IRDA state is valid.

Parameters:
__STATE__ IRDA state mode.
Return values:
SET (__STATE__ is valid) or RESET (__STATE__ is invalid)

Definition at line 811 of file stm32wbxx_hal_irda.h.

#define IS_IRDA_TX_RX_MODE ( __MODE__ ) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))

Ensure that IRDA communication mode is valid.

Parameters:
__MODE__ IRDA communication mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 778 of file stm32wbxx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_WORD_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == IRDA_WORDLENGTH_7B) || \
                                         ((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
                                         ((__LENGTH__) == IRDA_WORDLENGTH_9B))

Ensure that IRDA frame length is valid.

Parameters:
__LENGTH__ IRDA frame length.
Return values:
SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

Definition at line 760 of file stm32wbxx_hal_irda.h.

Referenced by IRDA_SetConfig().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
IRDA Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_IRDA_Init (IRDA_HandleTypeDef *hirda)
Initialize the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_IRDA_DeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA peripheral.
__weak void | HAL_IRDA_MspInit (IRDA_HandleTypeDef *hirda)
Initialize the IRDA MSP.
__weak void | HAL_IRDA_MspDeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA MSP.
HAL_StatusTypeDef | HAL_IRDA_RegisterCallback (IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback)
Register a User IRDA Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_IRDA_UnRegisterCallback (IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID)
Unregister an IRDA callback IRDA callback is redirected to the weak predefined callback.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and Configuration functions #####
  ==============================================================================
  [..]
  This subsection provides a set of functions allowing to initialize the USARTx
  in asynchronous IRDA mode.
  (+) For the asynchronous mode only these parameters can be configured:
      (++) Baud Rate
      (++) Word Length
      (++) Parity: If the parity is enabled, then the MSB bit of the data written
           in the data register is transmitted but is changed by the parity bit.
      (++) Power mode
      (++) Prescaler setting
      (++) Receiver/transmitter modes

  [..]
  The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures
  (details for the procedures are available in reference manual).

Depending on the frame length defined by the M1 and M0 bits (7-bit, 8-bit or 9-bit), the possible IRDA frame formats are listed in the following table.

Table 1. IRDA frame format. +-----------------------------------------------------------------------+ | M1 bit | M0 bit | PCE bit | IRDA frame | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 0 | | SB | 8 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 0 | | SB | 9 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 0 | | SB | 7 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | +-----------------------------------------------------------------------+

Function Documentation

HAL_StatusTypeDef HAL_IRDA_DeInit ( IRDA_HandleTypeDef * hirda )

DeInitialize the IRDA peripheral.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 391 of file stm32wbxx_hal_irda.c.

References __HAL_IRDA_DISABLE, assert_param, __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_IRDA_ERROR_NONE, HAL_IRDA_MspDeInit(), HAL_IRDA_STATE_BUSY, HAL_IRDA_STATE_RESET, __IRDA_HandleTypeDef::Instance, __IRDA_HandleTypeDef::MspDeInitCallback, and __IRDA_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_IRDA_Init ( IRDA_HandleTypeDef * hirda )

Initialize the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and initialize the associated handle.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 326 of file stm32wbxx_hal_irda.c.

References __HAL_IRDA_DISABLE, __HAL_IRDA_ENABLE, assert_param, __IRDA_HandleTypeDef::gState, HAL_IRDA_MspInit(), HAL_IRDA_STATE_BUSY, HAL_IRDA_STATE_RESET, __IRDA_HandleTypeDef::Instance, IRDA_CheckIdleState(), IRDA_InitCallbacksToDefault(), IRDA_SetConfig(), __IRDA_HandleTypeDef::Lock, and __IRDA_HandleTypeDef::MspInitCallback.

void HAL_IRDA_MspDeInit ( IRDA_HandleTypeDef * hirda )

DeInitialize the IRDA MSP.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 450 of file stm32wbxx_hal_irda.c.

Referenced by HAL_IRDA_DeInit(), and HAL_IRDA_UnRegisterCallback().

void HAL_IRDA_MspInit ( IRDA_HandleTypeDef * hirda )

Initialize the IRDA MSP.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 434 of file stm32wbxx_hal_irda.c.

Referenced by HAL_IRDA_Init(), and HAL_IRDA_UnRegisterCallback().

HAL_StatusTypeDef HAL_IRDA_RegisterCallback | ( | IRDA_HandleTypeDef * | hirda,
 |  | HAL_IRDA_CallbackIDTypeDef | CallbackID,
 |  | pIRDA_CallbackTypeDef | pCallback
 | ) |  |

Register a User IRDA Callback To be used instead of the weak predefined callback.

Parameters:
hirda | irda handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
  • HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID
  • HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
  • HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_IRDA_ERROR_CB_ID Error Callback ID
  • HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
  • HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
  • HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
  • HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID
  • HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 480 of file stm32wbxx_hal_irda.c.

References __IRDA_HandleTypeDef::AbortCpltCallback, __IRDA_HandleTypeDef::AbortReceiveCpltCallback, __IRDA_HandleTypeDef::AbortTransmitCpltCallback, __IRDA_HandleTypeDef::ErrorCallback, __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_IRDA_ABORT_COMPLETE_CB_ID, HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID, HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID, HAL_IRDA_ERROR_CB_ID, HAL_IRDA_ERROR_INVALID_CALLBACK, HAL_IRDA_MSPDEINIT_CB_ID, HAL_IRDA_MSPINIT_CB_ID, HAL_IRDA_RX_COMPLETE_CB_ID, HAL_IRDA_RX_HALFCOMPLETE_CB_ID, HAL_IRDA_STATE_READY, HAL_IRDA_STATE_RESET, HAL_IRDA_TX_COMPLETE_CB_ID, HAL_IRDA_TX_HALFCOMPLETE_CB_ID, __IRDA_HandleTypeDef::MspDeInitCallback, __IRDA_HandleTypeDef::MspInitCallback, __IRDA_HandleTypeDef::RxCpltCallback, __IRDA_HandleTypeDef::RxHalfCpltCallback, __IRDA_HandleTypeDef::TxCpltCallback, and __IRDA_HandleTypeDef::TxHalfCpltCallback.

HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback | ( | IRDA_HandleTypeDef * | hirda,
 |  | HAL_IRDA_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an IRDA callback IRDA callback is redirected to the weak predefined callback.

Parameters:
hirda irda handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
  • HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID
  • HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
  • HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_IRDA_ERROR_CB_ID Error Callback ID
  • HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
  • HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
  • HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
  • HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID
  • HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID
Return values:
HAL status

Definition at line 601 of file stm32wbxx_hal_irda.c.

References __IRDA_HandleTypeDef::AbortCpltCallback, __IRDA_HandleTypeDef::AbortReceiveCpltCallback, __IRDA_HandleTypeDef::AbortTransmitCpltCallback, __IRDA_HandleTypeDef::ErrorCallback, __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_IRDA_ABORT_COMPLETE_CB_ID, HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID, HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID, HAL_IRDA_AbortCpltCallback(), HAL_IRDA_AbortReceiveCpltCallback(), HAL_IRDA_AbortTransmitCpltCallback(), HAL_IRDA_ERROR_CB_ID, HAL_IRDA_ERROR_INVALID_CALLBACK, HAL_IRDA_ErrorCallback(), HAL_IRDA_MspDeInit(), HAL_IRDA_MSPDEINIT_CB_ID, HAL_IRDA_MspInit(), HAL_IRDA_MSPINIT_CB_ID, HAL_IRDA_RX_COMPLETE_CB_ID, HAL_IRDA_RX_HALFCOMPLETE_CB_ID, HAL_IRDA_RxCpltCallback(), HAL_IRDA_RxHalfCpltCallback(), HAL_IRDA_STATE_READY, HAL_IRDA_STATE_RESET, HAL_IRDA_TX_COMPLETE_CB_ID, HAL_IRDA_TX_HALFCOMPLETE_CB_ID, HAL_IRDA_TxCpltCallback(), HAL_IRDA_TxHalfCpltCallback(), __IRDA_HandleTypeDef::MspDeInitCallback, __IRDA_HandleTypeDef::MspInitCallback, __IRDA_HandleTypeDef::RxCpltCallback, __IRDA_HandleTypeDef::RxHalfCpltCallback, __IRDA_HandleTypeDef::TxCpltCallback, and __IRDA_HandleTypeDef::TxHalfCpltCallback.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IO operation functions

Functions
IO operation functions
IRDA Exported Functions

IRDA Transmit and Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_IRDA_Transmit (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_DMAPause (IRDA_HandleTypeDef *hirda)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAResume (IRDA_HandleTypeDef *hirda)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAStop (IRDA_HandleTypeDef *hirda)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_Abort (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_Abort_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_IRDA_IRQHandler (IRDA_HandleTypeDef *hirda)
Handle IRDA interrupt request.
__weak void | HAL_IRDA_TxCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Transfer completed callback.
__weak void | HAL_IRDA_TxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Half Transfer completed callback.
__weak void | HAL_IRDA_RxCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Transfer completed callback.
__weak void | HAL_IRDA_RxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Half Transfer complete callback.
__weak void | HAL_IRDA_ErrorCallback (IRDA_HandleTypeDef *hirda)
IRDA error callback.
__weak void | HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Complete callback.
__weak void | HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Complete callback.
__weak void | HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Receive Complete callback.

Detailed Description

IRDA Transmit and Receive functions.

 ===============================================================================
                         ##### IO operation functions #####
 ===============================================================================
  [..]
    This subsection provides a set of functions allowing to manage the IRDA data transfers.

  [..]
    IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
    on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
    is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
    While receiving data, transmission should be avoided as the data to be transmitted
    could be corrupted.

    (#) There are two modes of transfer:
        (++) Blocking mode: the communication is performed in polling mode.
             The HAL status of all data processing is returned by the same function
             after finishing transfer.
        (++) Non-Blocking mode: the communication is performed using Interrupts
             or DMA, these API's return the HAL status.
             The end of the data processing will be indicated through the
             dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
             using DMA mode.
             The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
             will be executed respectively at the end of the Transmit or Receive process
             The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected

    (#) Blocking mode APIs are :
        (++) HAL_IRDA_Transmit()
        (++) HAL_IRDA_Receive()

    (#) Non Blocking mode APIs with Interrupt are :
        (++) HAL_IRDA_Transmit_IT()
        (++) HAL_IRDA_Receive_IT()
        (++) HAL_IRDA_IRQHandler()

    (#) Non Blocking mode functions with DMA are :
        (++) HAL_IRDA_Transmit_DMA()
        (++) HAL_IRDA_Receive_DMA()
        (++) HAL_IRDA_DMAPause()
        (++) HAL_IRDA_DMAResume()
        (++) HAL_IRDA_DMAStop()

    (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode:
        (++) HAL_IRDA_TxHalfCpltCallback()
        (++) HAL_IRDA_TxCpltCallback()
        (++) HAL_IRDA_RxHalfCpltCallback()
        (++) HAL_IRDA_RxCpltCallback()
        (++) HAL_IRDA_ErrorCallback()

    (#) Non-Blocking mode transfers could be aborted using Abort API's :
        (+) HAL_IRDA_Abort()
        (+) HAL_IRDA_AbortTransmit()
        (+) HAL_IRDA_AbortReceive()
        (+) HAL_IRDA_Abort_IT()
        (+) HAL_IRDA_AbortTransmit_IT()
        (+) HAL_IRDA_AbortReceive_IT()

    (#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
        (+) HAL_IRDA_AbortCpltCallback()
        (+) HAL_IRDA_AbortTransmitCpltCallback()
        (+) HAL_IRDA_AbortReceiveCpltCallback()

    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
        Errors are handled as follows :
       (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
           to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
           Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
           and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
           If user wants to abort it, Abort services should be called by user.
       (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
           This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
           Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.

Function Documentation

HAL_StatusTypeDef HAL_IRDA_Abort ( IRDA_HandleTypeDef * hirda )

Abort ongoing transfers (blocking mode).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable IRDA Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1377 of file stm32wbxx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_IRDA_ERROR_DMA, HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmarx, __IRDA_HandleTypeDef::hdmatx, __IRDA_HandleTypeDef::Instance, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, __IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_IRDA_Abort_IT ( IRDA_HandleTypeDef * hirda )

Abort ongoing transfers (Interrupt mode).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable IRDA Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1573 of file stm32wbxx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, __IRDA_HandleTypeDef::AbortCpltCallback, __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_IRDA_AbortCpltCallback(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmarx, __IRDA_HandleTypeDef::hdmatx, __IRDA_HandleTypeDef::Instance, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, IRDA_DMARxAbortCallback(), IRDA_DMATxAbortCallback(), __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, __IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_IRDA_AbortCpltCallback ( IRDA_HandleTypeDef * hirda )

IRDA Abort Complete callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2097 of file stm32wbxx_hal_irda.c.

Referenced by HAL_IRDA_Abort_IT(), HAL_IRDA_UnRegisterCallback(), IRDA_DMARxAbortCallback(), IRDA_DMATxAbortCallback(), and IRDA_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_IRDA_AbortReceive ( IRDA_HandleTypeDef * hirda )

Abort ongoing Receive transfer (blocking mode).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Note:
This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable IRDA Interrupts (Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1515 of file stm32wbxx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, __IRDA_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_IRDA_ERROR_DMA, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmarx, __IRDA_HandleTypeDef::Instance, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT ( IRDA_HandleTypeDef * hirda )

Abort ongoing Receive transfer (Interrupt mode).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Note:
This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable IRDA Interrupts (Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1783 of file stm32wbxx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, __IRDA_HandleTypeDef::AbortReceiveCpltCallback, HAL_DMA_Abort_IT(), HAL_IRDA_AbortReceiveCpltCallback(), HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmarx, __IRDA_HandleTypeDef::Instance, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, IRDA_DMARxOnlyAbortCallback(), __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_IRDA_AbortReceiveCpltCallback ( IRDA_HandleTypeDef * hirda )

IRDA Abort Receive Complete callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2129 of file stm32wbxx_hal_irda.c.

Referenced by HAL_IRDA_AbortReceive_IT(), HAL_IRDA_UnRegisterCallback(), IRDA_DMARxOnlyAbortCallback(), and IRDA_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_IRDA_AbortTransmit ( IRDA_HandleTypeDef * hirda )

Abort ongoing Transmit transfer (blocking mode).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Note:
This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable IRDA Interrupts (Tx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1463 of file stm32wbxx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_IRDA_ERROR_DMA, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmatx, __IRDA_HandleTypeDef::Instance, __IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT ( IRDA_HandleTypeDef * hirda )

Abort ongoing Transmit transfer (Interrupt mode).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Note:
This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable IRDA Interrupts (Tx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1705 of file stm32wbxx_hal_irda.c.

References __IRDA_HandleTypeDef::AbortTransmitCpltCallback, __IRDA_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_IRDA_AbortTransmitCpltCallback(), HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmatx, __IRDA_HandleTypeDef::Instance, IRDA_DMATxOnlyAbortCallback(), __IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_IRDA_AbortTransmitCpltCallback ( IRDA_HandleTypeDef * hirda )

IRDA Abort Complete callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2113 of file stm32wbxx_hal_irda.c.

Referenced by HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_UnRegisterCallback(), IRDA_DMATxOnlyAbortCallback(), and IRDA_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_IRDA_DMAPause ( IRDA_HandleTypeDef * hirda )

Pause the DMA Transfer.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 1227 of file stm32wbxx_hal_irda.c.

References __IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, __IRDA_HandleTypeDef::Instance, and __IRDA_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_IRDA_DMAResume ( IRDA_HandleTypeDef * hirda )

Resume the DMA Transfer.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 1265 of file stm32wbxx_hal_irda.c.

References __HAL_IRDA_CLEAR_OREFLAG, __IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, __IRDA_HandleTypeDef::Instance, and __IRDA_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_IRDA_DMAStop ( IRDA_HandleTypeDef * hirda )

Stop the DMA Transfer.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 1300 of file stm32wbxx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_IRDA_ERROR_DMA, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, __IRDA_HandleTypeDef::hdmarx, __IRDA_HandleTypeDef::hdmatx, __IRDA_HandleTypeDef::Instance, IRDA_EndRxTransfer(), IRDA_EndTxTransfer(), and __IRDA_HandleTypeDef::RxState.

void HAL_IRDA_ErrorCallback ( IRDA_HandleTypeDef * hirda )

IRDA error callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2081 of file stm32wbxx_hal_irda.c.

Referenced by HAL_IRDA_IRQHandler(), HAL_IRDA_UnRegisterCallback(), IRDA_DMAAbortOnError(), IRDA_DMAError(), and IRDA_InitCallbacksToDefault().

void HAL_IRDA_IRQHandler ( IRDA_HandleTypeDef * hirda )

Handle IRDA interrupt request.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 1859 of file stm32wbxx_hal_irda.c.

References __HAL_IRDA_CLEAR_IT, __IRDA_HandleTypeDef::ErrorCallback, __IRDA_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_IRDA_ERROR_FE, HAL_IRDA_ERROR_NE, HAL_IRDA_ERROR_NONE, HAL_IRDA_ERROR_ORE, HAL_IRDA_ERROR_PE, HAL_IRDA_ErrorCallback(), __IRDA_HandleTypeDef::hdmarx, __IRDA_HandleTypeDef::Instance, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, IRDA_DMAAbortOnError(), IRDA_EndRxTransfer(), IRDA_EndTransmit_IT(), IRDA_Receive_IT(), IRDA_Transmit_IT(), and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_IRDA_Receive | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. In this case, Size must reflect the number of u16 available through pData.
Parameters:
hirda | Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be received.
Timeout | Specify timeout value.
Return values:
HAL status

Definition at line 884 of file stm32wbxx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::Init, __IRDA_HandleTypeDef::Instance, IRDA_FLAG_RXNE, IRDA_MASK_COMPUTATION, IRDA_PARITY_NONE, IRDA_WaitOnFlagUntilTimeout(), IRDA_WORDLENGTH_9B, __IRDA_HandleTypeDef::Mask, IRDA_InitTypeDef::Parity, __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, __IRDA_HandleTypeDef::RxXferSize, and IRDA_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_IRDA_Receive_DMA | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in DMA mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. In this case, Size must reflect the number of u16 available through pData.
When the IRDA parity is enabled (PCE = 1), the received data contains the parity bit (MSB position).
Parameters:
hirda | Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be received.
Return values:
HAL status

Definition at line 1151 of file stm32wbxx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_IRDA_ERROR_DMA, HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmarx, __IRDA_HandleTypeDef::Instance, IRDA_DMAError(), IRDA_DMAReceiveCplt(), IRDA_DMAReceiveHalfCplt(), __IRDA_HandleTypeDef::pRxBuffPtr, __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_IRDA_Receive_IT | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in interrupt mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. In this case, Size must reflect the number of u16 available through pData.
Parameters:
hirda | Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be received.
Return values:
HAL status

Definition at line 1019 of file stm32wbxx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCode, HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::Instance, IRDA_MASK_COMPUTATION, __IRDA_HandleTypeDef::pRxBuffPtr, __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, and __IRDA_HandleTypeDef::RxXferSize.

void HAL_IRDA_RxCpltCallback ( IRDA_HandleTypeDef * hirda )

Rx Transfer completed callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2049 of file stm32wbxx_hal_irda.c.

Referenced by HAL_IRDA_UnRegisterCallback(), IRDA_DMAReceiveCplt(), IRDA_InitCallbacksToDefault(), and IRDA_Receive_IT().

void HAL_IRDA_RxHalfCpltCallback ( IRDA_HandleTypeDef * hirda )

Rx Half Transfer complete callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2065 of file stm32wbxx_hal_irda.c.

Referenced by HAL_IRDA_UnRegisterCallback(), IRDA_DMAReceiveHalfCplt(), and IRDA_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_IRDA_Transmit | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Send an amount of data in blocking mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. In this case, Size must reflect the number of u16 available through pData.
Parameters:
hirda | Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be sent.
Timeout | Specify timeout value.
Return values:
HAL status

Definition at line 795 of file stm32wbxx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_GetTick(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_TX, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::Init, __IRDA_HandleTypeDef::Instance, IRDA_FLAG_TC, IRDA_FLAG_TXE, IRDA_PARITY_NONE, IRDA_WaitOnFlagUntilTimeout(), IRDA_WORDLENGTH_9B, IRDA_InitTypeDef::Parity, __IRDA_HandleTypeDef::TxXferCount, __IRDA_HandleTypeDef::TxXferSize, and IRDA_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_IRDA_Transmit_DMA | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in DMA mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. In this case, Size must reflect the number of u16 available through pData.
Parameters:
hirda | Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData | pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be sent.
Return values:
HAL status

Definition at line 1071 of file stm32wbxx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_DMA_Start_IT(), HAL_IRDA_ERROR_DMA, HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_TX, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmatx, __IRDA_HandleTypeDef::Instance, IRDA_CLEAR_TCF, IRDA_DMAError(), IRDA_DMATransmitCplt(), IRDA_DMATransmitHalfCplt(), __IRDA_HandleTypeDef::pTxBuffPtr, __IRDA_HandleTypeDef::TxXferCount, __IRDA_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_IRDA_Transmit_IT | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in interrupt mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. In this case, Size must reflect the number of u16 available through pData.
Parameters:
hirda | Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be sent.
Return values:
HAL status

Definition at line 974 of file stm32wbxx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_TX, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::Instance, __IRDA_HandleTypeDef::pTxBuffPtr, __IRDA_HandleTypeDef::TxXferCount, and __IRDA_HandleTypeDef::TxXferSize.

void HAL_IRDA_TxCpltCallback ( IRDA_HandleTypeDef * hirda )

Tx Transfer completed callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2017 of file stm32wbxx_hal_irda.c.

Referenced by HAL_IRDA_UnRegisterCallback(), IRDA_DMATransmitCplt(), IRDA_EndTransmit_IT(), and IRDA_InitCallbacksToDefault().

void HAL_IRDA_TxHalfCpltCallback ( IRDA_HandleTypeDef * hirda )

Tx Half Transfer completed callback.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
None

Definition at line 2033 of file stm32wbxx_hal_irda.c.

Referenced by HAL_IRDA_UnRegisterCallback(), IRDA_DMATransmitHalfCplt(), and IRDA_InitCallbacksToDefault().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Peripheral State and Error functions

Functions
Peripheral State and Error functions
IRDA Exported Functions

IRDA State and Errors functions. More...

Functions

HAL_IRDA_StateTypeDef | HAL_IRDA_GetState (IRDA_HandleTypeDef *hirda)
Return the IRDA handle state.
uint32_t | HAL_IRDA_GetError (IRDA_HandleTypeDef *hirda)
Return the IRDA handle error code.

Detailed Description

IRDA State and Errors functions.

  ==============================================================================
            ##### Peripheral State and Error functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to return the State of IrDA
    communication process and also return Peripheral Errors occurred during communication process
     (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state
         of the IRDA peripheral handle.
     (+) HAL_IRDA_GetError() checks in run-time errors that could occur during
         communication.

Function Documentation

uint32_t HAL_IRDA_GetError ( IRDA_HandleTypeDef * hirda )

Return the IRDA handle error code.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
IRDA Error Code

Definition at line 2184 of file stm32wbxx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCode.

HAL_IRDA_StateTypeDef HAL_IRDA_GetState ( IRDA_HandleTypeDef * hirda )

Return the IRDA handle state.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL state

Definition at line 2168 of file stm32wbxx_hal_irda.c.

References __IRDA_HandleTypeDef::gState, and __IRDA_HandleTypeDef::RxState.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IRDA Private Functions

Functions
IRDA Private Functions
IRDA

Functions

void | IRDA_InitCallbacksToDefault (IRDA_HandleTypeDef *hirda)
Initialize the callbacks to their default values.
static HAL_StatusTypeDef | IRDA_SetConfig (IRDA_HandleTypeDef *hirda)
Configure the IRDA peripheral.
static HAL_StatusTypeDef | IRDA_CheckIdleState (IRDA_HandleTypeDef *hirda)
Check the IRDA Idle State.
static HAL_StatusTypeDef | IRDA_WaitOnFlagUntilTimeout (IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle IRDA Communication Timeout.
static void | IRDA_EndTxTransfer (IRDA_HandleTypeDef *hirda)
End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
static void | IRDA_EndRxTransfer (IRDA_HandleTypeDef *hirda)
End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
static void | IRDA_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA IRDA transmit process complete callback.
static void | IRDA_DMATransmitHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA transmit process half complete callback.
static void | IRDA_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process complete callback.
static void | IRDA_DMAReceiveHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process half complete callback.
static void | IRDA_DMAError (DMA_HandleTypeDef *hdma)
DMA IRDA communication error callback.
static void | IRDA_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA IRDA communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | IRDA_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | IRDA_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | IRDA_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Tx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | IRDA_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Rx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static void | IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda)
Send an amount of data in interrupt mode.
static void | IRDA_EndTransmit_IT (IRDA_HandleTypeDef *hirda)
Wrap up transmission in non-blocking mode.
static void | IRDA_Receive_IT (IRDA_HandleTypeDef *hirda)
Receive an amount of data in interrupt mode.

Function Documentation

static HAL_StatusTypeDef IRDA_CheckIdleState ( IRDA_HandleTypeDef * hirda ) [static]

Check the IRDA Idle State.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 2308 of file stm32wbxx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_GetTick(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::Instance, IRDA_TEACK_REACK_TIMEOUT, IRDA_WaitOnFlagUntilTimeout(), and __IRDA_HandleTypeDef::RxState.

Referenced by HAL_IRDA_Init().

static void IRDA_DMAAbortOnError ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2575 of file stm32wbxx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCallback, HAL_IRDA_ErrorCallback(), __DMA_HandleTypeDef::Parent, __IRDA_HandleTypeDef::RxXferCount, and __IRDA_HandleTypeDef::TxXferCount.

Referenced by HAL_IRDA_IRQHandler().

static void IRDA_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA communication error callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2535 of file stm32wbxx_hal_irda.c.

References __IRDA_HandleTypeDef::ErrorCallback, __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_IRDA_ERROR_DMA, HAL_IRDA_ErrorCallback(), HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, __IRDA_HandleTypeDef::Instance, IRDA_EndRxTransfer(), IRDA_EndTxTransfer(), __DMA_HandleTypeDef::Parent, __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, and __IRDA_HandleTypeDef::TxXferCount.

Referenced by HAL_IRDA_Receive_DMA(), and HAL_IRDA_Transmit_DMA().

static void IRDA_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA receive process complete callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2480 of file stm32wbxx_hal_irda.c.

References HAL_IRDA_RxCpltCallback(), HAL_IRDA_STATE_READY, __DMA_HandleTypeDef::Instance, __IRDA_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, __IRDA_HandleTypeDef::RxCpltCallback, __IRDA_HandleTypeDef::RxState, and __IRDA_HandleTypeDef::RxXferCount.

Referenced by HAL_IRDA_Receive_DMA().

static void IRDA_DMAReceiveHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA receive process half complete callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2516 of file stm32wbxx_hal_irda.c.

References HAL_IRDA_RxHalfCpltCallback(), __DMA_HandleTypeDef::Parent, and __IRDA_HandleTypeDef::RxHalfCpltCallback.

Referenced by HAL_IRDA_Receive_DMA().

static void IRDA_DMARxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Tx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2646 of file stm32wbxx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, __IRDA_HandleTypeDef::AbortCpltCallback, __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_IRDA_AbortCpltCallback(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmarx, __IRDA_HandleTypeDef::hdmatx, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, __DMA_HandleTypeDef::Parent, __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, __IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_IRDA_Abort_IT().

static void IRDA_DMARxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA Rx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2721 of file stm32wbxx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, __IRDA_HandleTypeDef::AbortReceiveCpltCallback, HAL_IRDA_AbortReceiveCpltCallback(), HAL_IRDA_STATE_READY, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, __IRDA_HandleTypeDef::RxState, and __IRDA_HandleTypeDef::RxXferCount.

Referenced by HAL_IRDA_AbortReceive_IT().

static void IRDA_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA transmit process complete callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2425 of file stm32wbxx_hal_irda.c.

References HAL_IRDA_TxCpltCallback(), __DMA_HandleTypeDef::Instance, __IRDA_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, __IRDA_HandleTypeDef::TxCpltCallback, and __IRDA_HandleTypeDef::TxXferCount.

Referenced by HAL_IRDA_Transmit_DMA().

static void IRDA_DMATransmitHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA transmit process half complete callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2461 of file stm32wbxx_hal_irda.c.

References HAL_IRDA_TxHalfCpltCallback(), __DMA_HandleTypeDef::Parent, and __IRDA_HandleTypeDef::TxHalfCpltCallback.

Referenced by HAL_IRDA_Transmit_DMA().

static void IRDA_DMATxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Rx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2598 of file stm32wbxx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, __IRDA_HandleTypeDef::AbortCpltCallback, __IRDA_HandleTypeDef::ErrorCode, __IRDA_HandleTypeDef::gState, HAL_IRDA_AbortCpltCallback(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::hdmarx, __IRDA_HandleTypeDef::hdmatx, IRDA_CLEAR_FEF, IRDA_CLEAR_NEF, IRDA_CLEAR_OREF, IRDA_CLEAR_PEF, __DMA_HandleTypeDef::Parent, __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, __IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_IRDA_Abort_IT().

static void IRDA_DMATxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA Tx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2694 of file stm32wbxx_hal_irda.c.

References __IRDA_HandleTypeDef::AbortTransmitCpltCallback, __IRDA_HandleTypeDef::gState, HAL_IRDA_AbortTransmitCpltCallback(), HAL_IRDA_STATE_READY, __DMA_HandleTypeDef::Parent, and __IRDA_HandleTypeDef::TxXferCount.

Referenced by HAL_IRDA_AbortTransmit_IT().

static void IRDA_EndRxTransfer ( IRDA_HandleTypeDef * hirda ) [static]

End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2408 of file stm32wbxx_hal_irda.c.

References HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::Instance, and __IRDA_HandleTypeDef::RxState.

Referenced by HAL_IRDA_DMAStop(), HAL_IRDA_IRQHandler(), and IRDA_DMAError().

static void IRDA_EndTransmit_IT ( IRDA_HandleTypeDef * hirda ) [static]

Wrap up transmission in non-blocking mode.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2790 of file stm32wbxx_hal_irda.c.

References __IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_READY, HAL_IRDA_TxCpltCallback(), __IRDA_HandleTypeDef::Instance, and __IRDA_HandleTypeDef::TxCpltCallback.

Referenced by HAL_IRDA_IRQHandler().

static void IRDA_EndTxTransfer ( IRDA_HandleTypeDef * hirda ) [static]

End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2392 of file stm32wbxx_hal_irda.c.

References __IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_READY, and __IRDA_HandleTypeDef::Instance.

Referenced by HAL_IRDA_DMAStop(), and IRDA_DMAError().

void IRDA_InitCallbacksToDefault ( IRDA_HandleTypeDef * hirda )

Initialize the callbacks to their default values.

Parameters:
hirda IRDA handle.
Return values:
none

Definition at line 2207 of file stm32wbxx_hal_irda.c.

References __IRDA_HandleTypeDef::AbortCpltCallback, __IRDA_HandleTypeDef::AbortReceiveCpltCallback, __IRDA_HandleTypeDef::AbortTransmitCpltCallback, __IRDA_HandleTypeDef::ErrorCallback, HAL_IRDA_AbortCpltCallback(), HAL_IRDA_AbortReceiveCpltCallback(), HAL_IRDA_AbortTransmitCpltCallback(), HAL_IRDA_ErrorCallback(), HAL_IRDA_RxCpltCallback(), HAL_IRDA_RxHalfCpltCallback(), HAL_IRDA_TxCpltCallback(), HAL_IRDA_TxHalfCpltCallback(), __IRDA_HandleTypeDef::RxCpltCallback, __IRDA_HandleTypeDef::RxHalfCpltCallback, __IRDA_HandleTypeDef::TxCpltCallback, and __IRDA_HandleTypeDef::TxHalfCpltCallback.

Referenced by HAL_IRDA_Init().

static void IRDA_Receive_IT ( IRDA_HandleTypeDef * hirda ) [static]

Receive an amount of data in interrupt mode.

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_IRDA_Receive_IT()
Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2815 of file stm32wbxx_hal_irda.c.

References __HAL_IRDA_SEND_REQ, HAL_IRDA_RxCpltCallback(), HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::Init, __IRDA_HandleTypeDef::Instance, IRDA_PARITY_NONE, IRDA_RXDATA_FLUSH_REQUEST, IRDA_WORDLENGTH_9B, __IRDA_HandleTypeDef::Mask, IRDA_InitTypeDef::Parity, __IRDA_HandleTypeDef::pRxBuffPtr, __IRDA_HandleTypeDef::RxCpltCallback, __IRDA_HandleTypeDef::RxState, __IRDA_HandleTypeDef::RxXferCount, and IRDA_InitTypeDef::WordLength.

Referenced by HAL_IRDA_IRQHandler().

static HAL_StatusTypeDef IRDA_SetConfig ( IRDA_HandleTypeDef * hirda ) [static]

Configure the IRDA peripheral.

Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 2228 of file stm32wbxx_hal_irda.c.

References assert_param, IRDA_InitTypeDef::BaudRate, IRDA_InitTypeDef::ClockPrescaler, HAL_RCC_GetPCLK2Freq(), HAL_RCC_GetSysClockFreq(), HSI_VALUE, __IRDA_HandleTypeDef::Init, __IRDA_HandleTypeDef::Instance, IRDA_CLOCKSOURCE_HSI, IRDA_CLOCKSOURCE_LSE, IRDA_CLOCKSOURCE_PCLK2, IRDA_CLOCKSOURCE_SYSCLK, IRDA_CR1_FIELDS, IRDA_DIV_SAMPLING16, IRDA_GETCLOCKSOURCE, IS_IRDA_BAUDRATE, IS_IRDA_CLOCKPRESCALER, IS_IRDA_PARITY, IS_IRDA_POWERMODE, IS_IRDA_PRESCALER, IS_IRDA_TX_RX_MODE, IS_IRDA_WORD_LENGTH, LSE_VALUE, IRDA_InitTypeDef::Mode, IRDA_InitTypeDef::Parity, IRDA_InitTypeDef::PowerMode, IRDA_InitTypeDef::Prescaler, USART_BRR_MAX, USART_BRR_MIN, and IRDA_InitTypeDef::WordLength.

Referenced by HAL_IRDA_Init().

static void IRDA_Transmit_IT ( IRDA_HandleTypeDef * hirda ) [static]

Send an amount of data in interrupt mode.

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_IRDA_Transmit_IT().
Parameters:
hirda Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2751 of file stm32wbxx_hal_irda.c.

References __IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_BUSY_TX, __IRDA_HandleTypeDef::Init, __IRDA_HandleTypeDef::Instance, IRDA_PARITY_NONE, IRDA_WORDLENGTH_9B, IRDA_InitTypeDef::Parity, __IRDA_HandleTypeDef::pTxBuffPtr, __IRDA_HandleTypeDef::TxXferCount, and IRDA_InitTypeDef::WordLength.

Referenced by HAL_IRDA_IRQHandler().

static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Tickstart,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle IRDA Communication Timeout.

Parameters:
hirda | Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Flag | Specifies the IRDA flag to check.
Status | Flag status (SET or RESET)
Tickstart | Tick start value
Timeout | Timeout duration
Return values:
HAL status

Definition at line 2359 of file stm32wbxx_hal_irda.c.

References __HAL_IRDA_GET_FLAG, __IRDA_HandleTypeDef::gState, HAL_GetTick(), HAL_IRDA_STATE_READY, __IRDA_HandleTypeDef::Instance, and __IRDA_HandleTypeDef::RxState.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), and IRDA_CheckIdleState().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IRDA Exported Types

Data Structures | Typedefs | Enumerations
IRDA Exported Types
IRDA

Data Structures

struct | IRDA_InitTypeDef
IRDA Init Structure definition. More...
struct | __IRDA_HandleTypeDef
IRDA handle Structure definition. More...

Typedefs

typedef uint32_t | HAL_IRDA_StateTypeDef
HAL IRDA State definition.
typedef struct __IRDA_HandleTypeDef | IRDA_HandleTypeDef
IRDA handle Structure definition.
typedef void(* | pIRDA_CallbackTypeDef )(IRDA_HandleTypeDef *hirda)
HAL IRDA Callback pointer definition.

Enumerations

enum IRDA_ClockSourceTypeDef {
IRDA_CLOCKSOURCE_PCLK2 = 0x01U, IRDA_CLOCKSOURCE_HSI = 0x02U, IRDA_CLOCKSOURCE_SYSCLK = 0x04U, IRDA_CLOCKSOURCE_LSE = 0x10U,
IRDA_CLOCKSOURCE_UNDEFINED = 0x20U
}
IRDA clock sources definition. More...
enum HAL_IRDA_CallbackIDTypeDef {
HAL_IRDA_TX_HALFCOMPLETE_CB_ID = 0x00U, HAL_IRDA_TX_COMPLETE_CB_ID = 0x01U, HAL_IRDA_RX_HALFCOMPLETE_CB_ID = 0x02U, HAL_IRDA_RX_COMPLETE_CB_ID = 0x03U,
HAL_IRDA_ERROR_CB_ID = 0x04U, HAL_IRDA_ABORT_COMPLETE_CB_ID = 0x05U, HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U,
HAL_IRDA_MSPINIT_CB_ID = 0x08U, HAL_IRDA_MSPDEINIT_CB_ID = 0x09U
}
HAL IRDA Callback ID enumeration definition. More...

Typedef Documentation

typedef uint32_t HAL_IRDA_StateTypeDef

HAL IRDA State definition.

Note:
HAL IRDA State value is a combination of 2 different substates: gState and RxState (see IRDA State Code Definition).
  • gState contains IRDA state information related to global Handle management and also information related to Tx operations. gState value coding follow below described bitmap : b7-b6 Error information 00 : No Error 01 : (Not Used) 10 : Timeout 11 : Error b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP not initialized. HAL IRDA Init function already called) b4-b3 (not used) xx : Should be set to 00 b2 Intrinsic process state 0 : Ready 1 : Busy (IP busy with some configuration or internal operations) b1 (not used) x : Should be set to 0 b0 Tx state 0 : Ready (no Tx operation ongoing) 1 : Busy (Tx operation ongoing)
  • RxState contains information related to Rx operations. RxState value coding follow below described bitmap : b7-b6 (not used) xx : Should be set to 00 b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP not initialized) b4-b2 (not used) xxx : Should be set to 000 b1 Rx state 0 : Ready (no Rx operation ongoing) 1 : Busy (Rx operation ongoing) b0 (not used) x : Should be set to 0.

Definition at line 118 of file stm32wbxx_hal_irda.h.

typedef struct __IRDA_HandleTypeDef IRDA_HandleTypeDef

IRDA handle Structure definition.

typedef void(* pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda)

HAL IRDA Callback pointer definition.

pointer to an IRDA callback function

Definition at line 222 of file stm32wbxx_hal_irda.h.

Enumeration Type Documentation

enum HAL_IRDA_CallbackIDTypeDef

HAL IRDA Callback ID enumeration definition.

Enumerator:
HAL_IRDA_TX_HALFCOMPLETE_CB_ID

IRDA Tx Half Complete Callback ID

HAL_IRDA_TX_COMPLETE_CB_ID

IRDA Tx Complete Callback ID

HAL_IRDA_RX_HALFCOMPLETE_CB_ID

IRDA Rx Half Complete Callback ID

HAL_IRDA_RX_COMPLETE_CB_ID

IRDA Rx Complete Callback ID

HAL_IRDA_ERROR_CB_ID

IRDA Error Callback ID

HAL_IRDA_ABORT_COMPLETE_CB_ID

IRDA Abort Complete Callback ID

HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID

IRDA Abort Transmit Complete Callback ID

HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID

IRDA Abort Receive Complete Callback ID

HAL_IRDA_MSPINIT_CB_ID

IRDA MspInit callback ID

HAL_IRDA_MSPDEINIT_CB_ID

IRDA MspDeInit callback ID

Definition at line 203 of file stm32wbxx_hal_irda.h.

enum IRDA_ClockSourceTypeDef

IRDA clock sources definition.

Enumerator:
IRDA_CLOCKSOURCE_PCLK2

PCLK2 clock source

IRDA_CLOCKSOURCE_HSI

HSI clock source

IRDA_CLOCKSOURCE_SYSCLK

SYSCLK clock source

IRDA_CLOCKSOURCE_LSE

LSE clock source

IRDA_CLOCKSOURCE_UNDEFINED

Undefined clock source

Definition at line 123 of file stm32wbxx_hal_irda.h.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IRDA_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
IRDA_InitTypeDef Struct Reference
IRDA Exported Types

IRDA Init Structure definition. More...

#include <stm32wbxx_hal_irda.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | Parity
uint32_t | Mode
uint8_t | Prescaler
uint16_t | PowerMode
uint32_t | ClockPrescaler

Detailed Description

IRDA Init Structure definition.

Definition at line 47 of file stm32wbxx_hal_irda.h.

Field Documentation

uint32_t IRDA_InitTypeDef::BaudRate

This member configures the IRDA communication baud rate. The baud rate register is computed using the following formula: Baud Rate Register = ((usart_ker_ckpres) / ((hirda->Init.BaudRate))) where usart_ker_ckpres is the IRDA input clock divided by a prescaler

Definition at line 49 of file stm32wbxx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint32_t IRDA_InitTypeDef::ClockPrescaler

Specifies the prescaler value used to divide the IRDA clock source. This parameter can be a value of Clock Prescaler.

Definition at line 74 of file stm32wbxx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint32_t IRDA_InitTypeDef::Mode

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of IRDA Transfer Mode

Definition at line 64 of file stm32wbxx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint32_t IRDA_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of IRDA Parity

Note:
When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits).

Definition at line 57 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), IRDA_SetConfig(), and IRDA_Transmit_IT().

uint16_t IRDA_InitTypeDef::PowerMode

Specifies the IRDA power mode. This parameter can be a value of IRDA Low Power

Definition at line 71 of file stm32wbxx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint8_t IRDA_InitTypeDef::Prescaler

Specifies the Prescaler value for dividing the UART/USART source clock to achieve low-power frequency.

Note:
Prescaler value 0 is forbidden

Definition at line 67 of file stm32wbxx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint32_t IRDA_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of IRDA Word Length

Definition at line 54 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), IRDA_SetConfig(), and IRDA_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_irda.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: __IRDA_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__IRDA_HandleTypeDef Struct Reference
IRDA Exported Types

IRDA handle Structure definition. More...

#include <stm32wbxx_hal_irda.h>

Data Fields

USART_TypeDef * | Instance
IRDA_InitTypeDef Init
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
__IO uint16_t | RxXferCount
uint16_t | Mask
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_IRDA_StateTypeDef | gState
__IO HAL_IRDA_StateTypeDef | RxState
uint32_t | ErrorCode
void(* | TxHalfCpltCallback )(struct __IRDA_HandleTypeDef *hirda)
void(* | TxCpltCallback )(struct __IRDA_HandleTypeDef *hirda)
void(* | RxHalfCpltCallback )(struct __IRDA_HandleTypeDef *hirda)
void(* | RxCpltCallback )(struct __IRDA_HandleTypeDef *hirda)
void(* | ErrorCallback )(struct __IRDA_HandleTypeDef *hirda)
void(* | AbortCpltCallback )(struct __IRDA_HandleTypeDef *hirda)
void(* | AbortTransmitCpltCallback )(struct __IRDA_HandleTypeDef *hirda)
void(* | AbortReceiveCpltCallback )(struct __IRDA_HandleTypeDef *hirda)
void(* | MspInitCallback )(struct __IRDA_HandleTypeDef *hirda)
void(* | MspDeInitCallback )(struct __IRDA_HandleTypeDef *hirda)

Detailed Description

IRDA handle Structure definition.

Definition at line 136 of file stm32wbxx_hal_irda.h.

Field Documentation

void(* __IRDA_HandleTypeDef::AbortCpltCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Abort Complete Callback

Definition at line 185 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_Abort_IT(), HAL_IRDA_RegisterCallback(), HAL_IRDA_UnRegisterCallback(), IRDA_DMARxAbortCallback(), IRDA_DMATxAbortCallback(), and IRDA_InitCallbacksToDefault().

void(* __IRDA_HandleTypeDef::AbortReceiveCpltCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Abort Receive Complete Callback

Definition at line 189 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_AbortReceive_IT(), HAL_IRDA_RegisterCallback(), HAL_IRDA_UnRegisterCallback(), IRDA_DMARxOnlyAbortCallback(), and IRDA_InitCallbacksToDefault().

void(* __IRDA_HandleTypeDef::AbortTransmitCpltCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Abort Transmit Complete Callback

Definition at line 187 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_RegisterCallback(), HAL_IRDA_UnRegisterCallback(), IRDA_DMATxOnlyAbortCallback(), and IRDA_InitCallbacksToDefault().

void(* __IRDA_HandleTypeDef::ErrorCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Error Callback

Definition at line 183 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler(), HAL_IRDA_RegisterCallback(), HAL_IRDA_UnRegisterCallback(), IRDA_DMAAbortOnError(), IRDA_DMAError(), and IRDA_InitCallbacksToDefault().

uint32_t __IRDA_HandleTypeDef::ErrorCode

IRDA Error code

Definition at line 172 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortTransmit(), HAL_IRDA_DeInit(), HAL_IRDA_DMAStop(), HAL_IRDA_GetError(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), HAL_IRDA_RegisterCallback(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), HAL_IRDA_UnRegisterCallback(), IRDA_CheckIdleState(), IRDA_DMAError(), IRDA_DMARxAbortCallback(), and IRDA_DMATxAbortCallback().

__IO HAL_IRDA_StateTypeDef __IRDA_HandleTypeDef::gState

IRDA state information related to global Handle management and also related to Tx operations. This parameter can be a value of HAL_IRDA_StateTypeDef

Definition at line 165 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_DeInit(), HAL_IRDA_DMAPause(), HAL_IRDA_DMAResume(), HAL_IRDA_DMAStop(), HAL_IRDA_GetState(), HAL_IRDA_Init(), HAL_IRDA_RegisterCallback(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), HAL_IRDA_UnRegisterCallback(), IRDA_CheckIdleState(), IRDA_DMAError(), IRDA_DMARxAbortCallback(), IRDA_DMATxAbortCallback(), IRDA_DMATxOnlyAbortCallback(), IRDA_EndTransmit_IT(), IRDA_EndTxTransfer(), IRDA_Transmit_IT(), and IRDA_WaitOnFlagUntilTimeout().

DMA_HandleTypeDef* __IRDA_HandleTypeDef::hdmarx

IRDA Rx DMA Handle parameters

Definition at line 161 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_DMAStop(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive_DMA(), IRDA_DMARxAbortCallback(), and IRDA_DMATxAbortCallback().

DMA_HandleTypeDef* __IRDA_HandleTypeDef::hdmatx

IRDA Tx DMA Handle parameters

Definition at line 159 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_DMAStop(), HAL_IRDA_Transmit_DMA(), IRDA_DMARxAbortCallback(), and IRDA_DMATxAbortCallback().

IRDA_InitTypeDef __IRDA_HandleTypeDef::Init

IRDA communication parameters

Definition at line 143 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), IRDA_SetConfig(), and IRDA_Transmit_IT().

USART_TypeDef* __IRDA_HandleTypeDef::Instance

USART registers base address

Definition at line 141 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_DeInit(), HAL_IRDA_DMAPause(), HAL_IRDA_DMAResume(), HAL_IRDA_DMAStop(), HAL_IRDA_Init(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_CheckIdleState(), IRDA_DMAError(), IRDA_DMAReceiveCplt(), IRDA_DMATransmitCplt(), IRDA_EndRxTransfer(), IRDA_EndTransmit_IT(), IRDA_EndTxTransfer(), IRDA_Receive_IT(), IRDA_SetConfig(), IRDA_Transmit_IT(), and IRDA_WaitOnFlagUntilTimeout().

HAL_LockTypeDef __IRDA_HandleTypeDef::Lock

Locking object

Definition at line 163 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_Init().

uint16_t __IRDA_HandleTypeDef::Mask

USART RX RDR register mask

Definition at line 157 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), and IRDA_Receive_IT().

void(* __IRDA_HandleTypeDef::MspDeInitCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Msp DeInit callback

Definition at line 194 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_DeInit(), HAL_IRDA_RegisterCallback(), and HAL_IRDA_UnRegisterCallback().

void(* __IRDA_HandleTypeDef::MspInitCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Msp Init callback

Definition at line 192 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_Init(), HAL_IRDA_RegisterCallback(), and HAL_IRDA_UnRegisterCallback().

uint8_t* __IRDA_HandleTypeDef::pRxBuffPtr

Pointer to IRDA Rx transfer Buffer

Definition at line 151 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), and IRDA_Receive_IT().

uint8_t* __IRDA_HandleTypeDef::pTxBuffPtr

Pointer to IRDA Tx transfer Buffer

Definition at line 145 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), and IRDA_Transmit_IT().

void(* __IRDA_HandleTypeDef::RxCpltCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Rx Complete Callback

Definition at line 181 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_RegisterCallback(), HAL_IRDA_UnRegisterCallback(), IRDA_DMAReceiveCplt(), IRDA_InitCallbacksToDefault(), and IRDA_Receive_IT().

void(* __IRDA_HandleTypeDef::RxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Rx Half Complete Callback

Definition at line 179 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_RegisterCallback(), HAL_IRDA_UnRegisterCallback(), IRDA_DMAReceiveHalfCplt(), and IRDA_InitCallbacksToDefault().

__IO HAL_IRDA_StateTypeDef __IRDA_HandleTypeDef::RxState

IRDA state information related to Rx operations. This parameter can be a value of HAL_IRDA_StateTypeDef

Definition at line 169 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_DeInit(), HAL_IRDA_DMAPause(), HAL_IRDA_DMAResume(), HAL_IRDA_DMAStop(), HAL_IRDA_GetState(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), IRDA_CheckIdleState(), IRDA_DMAError(), IRDA_DMAReceiveCplt(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), IRDA_DMATxAbortCallback(), IRDA_EndRxTransfer(), IRDA_Receive_IT(), and IRDA_WaitOnFlagUntilTimeout().

__IO uint16_t __IRDA_HandleTypeDef::RxXferCount

IRDA Rx Transfer Counter

Definition at line 155 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_Receive(), HAL_IRDA_Receive_IT(), IRDA_DMAAbortOnError(), IRDA_DMAError(), IRDA_DMAReceiveCplt(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), IRDA_DMATxAbortCallback(), and IRDA_Receive_IT().

uint16_t __IRDA_HandleTypeDef::RxXferSize

IRDA Rx Transfer size

Definition at line 153 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), and HAL_IRDA_Receive_IT().

void(* __IRDA_HandleTypeDef::TxCpltCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Tx Complete Callback

Definition at line 177 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_RegisterCallback(), HAL_IRDA_UnRegisterCallback(), IRDA_DMATransmitCplt(), IRDA_EndTransmit_IT(), and IRDA_InitCallbacksToDefault().

void(* __IRDA_HandleTypeDef::TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda)

IRDA Tx Half Complete Callback

Definition at line 175 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_RegisterCallback(), HAL_IRDA_UnRegisterCallback(), IRDA_DMATransmitHalfCplt(), and IRDA_InitCallbacksToDefault().

__IO uint16_t __IRDA_HandleTypeDef::TxXferCount

IRDA Tx Transfer Counter

Definition at line 149 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_DMAAbortOnError(), IRDA_DMAError(), IRDA_DMARxAbortCallback(), IRDA_DMATransmitCplt(), IRDA_DMATxAbortCallback(), IRDA_DMATxOnlyAbortCallback(), and IRDA_Transmit_IT().

uint16_t __IRDA_HandleTypeDef::TxXferSize

IRDA Tx Transfer size

Definition at line 147 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), and HAL_IRDA_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_irda.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IRDA State Code Definition

Defines
IRDA State Code Definition
IRDA Exported Constants

Defines

#define | HAL_IRDA_STATE_RESET 0x00000000U
#define | HAL_IRDA_STATE_READY 0x00000020U
#define | HAL_IRDA_STATE_BUSY 0x00000024U
#define | HAL_IRDA_STATE_BUSY_TX 0x00000021U
#define | HAL_IRDA_STATE_BUSY_RX 0x00000022U
#define | HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U
#define | HAL_IRDA_STATE_TIMEOUT 0x000000A0U
#define | HAL_IRDA_STATE_ERROR 0x000000E0U

Define Documentation

#define HAL_IRDA_STATE_BUSY 0x00000024U

An internal process is ongoing Value is allowed for gState only

Definition at line 242 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_DeInit(), and HAL_IRDA_Init().

#define HAL_IRDA_STATE_BUSY_RX 0x00000022U

Data Reception process is ongoing Value is allowed for RxState only

Definition at line 246 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_DMAPause(), HAL_IRDA_DMAResume(), HAL_IRDA_DMAStop(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), IRDA_DMAError(), and IRDA_Receive_IT().

#define HAL_IRDA_STATE_BUSY_TX 0x00000021U

Data Transmission process is ongoing Value is allowed for gState only

Definition at line 244 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_DMAPause(), HAL_IRDA_DMAResume(), HAL_IRDA_DMAStop(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_DMAError(), and IRDA_Transmit_IT().

#define HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U

Data Transmission and Reception process is ongoing Not to be used for neither gState nor RxState. Value is result of combination (Or) between gState and RxState values

Definition at line 248 of file stm32wbxx_hal_irda.h.

#define HAL_IRDA_STATE_ERROR 0x000000E0U

Error Value is allowed for gState only

Definition at line 253 of file stm32wbxx_hal_irda.h.

#define HAL_IRDA_STATE_READY 0x00000020U

Peripheral Initialized and ready for use Value is allowed for gState and RxState

Definition at line 240 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), HAL_IRDA_RegisterCallback(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), HAL_IRDA_UnRegisterCallback(), IRDA_CheckIdleState(), IRDA_DMAReceiveCplt(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), IRDA_DMATxAbortCallback(), IRDA_DMATxOnlyAbortCallback(), IRDA_EndRxTransfer(), IRDA_EndTransmit_IT(), IRDA_EndTxTransfer(), IRDA_Receive_IT(), and IRDA_WaitOnFlagUntilTimeout().

#define HAL_IRDA_STATE_RESET 0x00000000U

Peripheral is not initialized Value is allowed for gState and RxState

Definition at line 238 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_DeInit(), HAL_IRDA_Init(), HAL_IRDA_RegisterCallback(), and HAL_IRDA_UnRegisterCallback().

#define HAL_IRDA_STATE_TIMEOUT 0x000000A0U

Timeout state Value is allowed for gState only

Definition at line 251 of file stm32wbxx_hal_irda.h.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IRDA Error Code Definition

Defines
IRDA Error Code Definition
IRDA Exported Constants

Defines

#define | HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_IRDA_ERROR_PE ((uint32_t)0x00000001U)
#define | HAL_IRDA_ERROR_NE ((uint32_t)0x00000002U)
#define | HAL_IRDA_ERROR_FE ((uint32_t)0x00000004U)
#define | HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008U)
#define | HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010U)
#define | HAL_IRDA_ERROR_BUSY ((uint32_t)0x00000020U)
#define | HAL_IRDA_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U)

Define Documentation

#define HAL_IRDA_ERROR_BUSY ((uint32_t)0x00000020U)

Busy Error

Definition at line 268 of file stm32wbxx_hal_irda.h.

#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010U)

DMA transfer error

Definition at line 267 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortTransmit(), HAL_IRDA_DMAStop(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), and IRDA_DMAError().

#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004U)

frame error

Definition at line 265 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define HAL_IRDA_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U)

Invalid Callback error

Definition at line 270 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_RegisterCallback(), and HAL_IRDA_UnRegisterCallback().

#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002U)

Noise error

Definition at line 264 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000U)

No error

Definition at line 262 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_DeInit(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_CheckIdleState(), IRDA_DMARxAbortCallback(), and IRDA_DMATxAbortCallback().

#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008U)

Overrun error

Definition at line 266 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001U)

Parity error

Definition at line 263 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IRDA Word Length

Defines
IRDA Word Length
IRDA Exported Constants

Defines

#define | IRDA_WORDLENGTH_7B USART_CR1_M1
#define | IRDA_WORDLENGTH_8B 0x00000000U
#define | IRDA_WORDLENGTH_9B USART_CR1_M0

Define Documentation

#define IRDA_WORDLENGTH_7B USART_CR1_M1

7-bit long frame

Definition at line 279 of file stm32wbxx_hal_irda.h.

#define IRDA_WORDLENGTH_8B 0x00000000U

8-bit long frame

Definition at line 280 of file stm32wbxx_hal_irda.h.

#define IRDA_WORDLENGTH_9B USART_CR1_M0

9-bit long frame

Definition at line 281 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), and IRDA_Transmit_IT().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IRDA Parity

Defines
IRDA Parity
IRDA Exported Constants

Defines

#define | IRDA_PARITY_NONE 0x00000000U
#define | IRDA_PARITY_EVEN USART_CR1_PCE
#define | IRDA_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Define Documentation

#define IRDA_PARITY_EVEN USART_CR1_PCE

Even parity

Definition at line 290 of file stm32wbxx_hal_irda.h.

#define IRDA_PARITY_NONE 0x00000000U

No parity

Definition at line 289 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), and IRDA_Transmit_IT().

#define IRDA_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Odd parity

Definition at line 291 of file stm32wbxx_hal_irda.h.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IRDA Transfer Mode

Defines
IRDA Transfer Mode
IRDA Exported Constants

Defines

#define | IRDA_MODE_RX USART_CR1_RE
#define | IRDA_MODE_TX USART_CR1_TE
#define | IRDA_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)

Define Documentation

#define IRDA_MODE_RX USART_CR1_RE

RX mode

Definition at line 299 of file stm32wbxx_hal_irda.h.

#define IRDA_MODE_TX USART_CR1_TE

TX mode

Definition at line 300 of file stm32wbxx_hal_irda.h.

#define IRDA_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)

RX and TX mode

Definition at line 301 of file stm32wbxx_hal_irda.h.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IRDA Low Power

Defines
IRDA Low Power
IRDA Exported Constants

Defines

#define | IRDA_POWERMODE_NORMAL 0x00000000U
#define | IRDA_POWERMODE_LOWPOWER USART_CR3_IRLP

Define Documentation

#define IRDA_POWERMODE_LOWPOWER USART_CR3_IRLP

IRDA low power mode

Definition at line 310 of file stm32wbxx_hal_irda.h.

#define IRDA_POWERMODE_NORMAL 0x00000000U

IRDA normal power mode

Definition at line 309 of file stm32wbxx_hal_irda.h.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Clock Prescaler

Defines
Clock Prescaler
IRDA Exported Constants

Defines

#define | IRDA_PRESCALER_DIV1 0x00000000U
#define | IRDA_PRESCALER_DIV2 0x00000001U
#define | IRDA_PRESCALER_DIV4 0x00000002U
#define | IRDA_PRESCALER_DIV6 0x00000003U
#define | IRDA_PRESCALER_DIV8 0x00000004U
#define | IRDA_PRESCALER_DIV10 0x00000005U
#define | IRDA_PRESCALER_DIV12 0x00000006U
#define | IRDA_PRESCALER_DIV16 0x00000007U
#define | IRDA_PRESCALER_DIV32 0x00000008U
#define | IRDA_PRESCALER_DIV64 0x00000009U
#define | IRDA_PRESCALER_DIV128 0x0000000AU
#define | IRDA_PRESCALER_DIV256 0x0000000BU

Define Documentation

#define IRDA_PRESCALER_DIV1 0x00000000U

fclk_pres = fclk

Definition at line 318 of file stm32wbxx_hal_irda.h.

#define IRDA_PRESCALER_DIV10 0x00000005U

fclk_pres = fclk/10

Definition at line 323 of file stm32wbxx_hal_irda.h.

#define IRDA_PRESCALER_DIV12 0x00000006U

fclk_pres = fclk/12

Definition at line 324 of file stm32wbxx_hal_irda.h.

#define IRDA_PRESCALER_DIV128 0x0000000AU

fclk_pres = fclk/128

Definition at line 328 of file stm32wbxx_hal_irda.h.

#define IRDA_PRESCALER_DIV16 0x00000007U

fclk_pres = fclk/16

Definition at line 325 of file stm32wbxx_hal_irda.h.

#define IRDA_PRESCALER_DIV2 0x00000001U

fclk_pres = fclk/2

Definition at line 319 of file stm32wbxx_hal_irda.h.

#define IRDA_PRESCALER_DIV256 0x0000000BU

fclk_pres = fclk/256

Definition at line 329 of file stm32wbxx_hal_irda.h.

#define IRDA_PRESCALER_DIV32 0x00000008U

fclk_pres = fclk/32

Definition at line 326 of file stm32wbxx_hal_irda.h.

#define IRDA_PRESCALER_DIV4 0x00000002U

fclk_pres = fclk/4

Definition at line 320 of file stm32wbxx_hal_irda.h.

#define IRDA_PRESCALER_DIV6 0x00000003U

fclk_pres = fclk/6

Definition at line 321 of file stm32wbxx_hal_irda.h.

#define IRDA_PRESCALER_DIV64 0x00000009U

fclk_pres = fclk/64

Definition at line 327 of file stm32wbxx_hal_irda.h.

#define IRDA_PRESCALER_DIV8 0x00000004U

fclk_pres = fclk/8

Definition at line 322 of file stm32wbxx_hal_irda.h.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IRDA State

Defines
IRDA State
IRDA Exported Constants

Defines

#define | IRDA_STATE_DISABLE 0x00000000U
#define | IRDA_STATE_ENABLE USART_CR1_UE

Define Documentation

#define IRDA_STATE_DISABLE 0x00000000U

IRDA disabled

Definition at line 337 of file stm32wbxx_hal_irda.h.

#define IRDA_STATE_ENABLE USART_CR1_UE

IRDA enabled

Definition at line 338 of file stm32wbxx_hal_irda.h.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IRDA Mode

Defines
IRDA Mode
IRDA Exported Constants

Defines

#define | IRDA_MODE_DISABLE 0x00000000U
#define | IRDA_MODE_ENABLE USART_CR3_IREN

Define Documentation

#define IRDA_MODE_DISABLE 0x00000000U

Associated UART disabled in IRDA mode

Definition at line 346 of file stm32wbxx_hal_irda.h.

#define IRDA_MODE_ENABLE USART_CR3_IREN

Associated UART enabled in IRDA mode

Definition at line 347 of file stm32wbxx_hal_irda.h.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IRDA One Bit Sampling

Defines
IRDA One Bit Sampling
IRDA Exported Constants

Defines

#define | IRDA_ONE_BIT_SAMPLE_DISABLE 0x00000000U
#define | IRDA_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT

Define Documentation

#define IRDA_ONE_BIT_SAMPLE_DISABLE 0x00000000U

One-bit sampling disabled

Definition at line 355 of file stm32wbxx_hal_irda.h.

#define IRDA_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT

One-bit sampling enabled

Definition at line 356 of file stm32wbxx_hal_irda.h.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IRDA DMA Tx

Defines
IRDA DMA Tx
IRDA Exported Constants

Defines

#define | IRDA_DMA_TX_DISABLE 0x00000000U
#define | IRDA_DMA_TX_ENABLE USART_CR3_DMAT

Define Documentation

#define IRDA_DMA_TX_DISABLE 0x00000000U

IRDA DMA TX disabled

Definition at line 364 of file stm32wbxx_hal_irda.h.

#define IRDA_DMA_TX_ENABLE USART_CR3_DMAT

IRDA DMA TX enabled

Definition at line 365 of file stm32wbxx_hal_irda.h.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IRDA DMA Rx

Defines
IRDA DMA Rx
IRDA Exported Constants

Defines

#define | IRDA_DMA_RX_DISABLE 0x00000000U
#define | IRDA_DMA_RX_ENABLE USART_CR3_DMAR

Define Documentation

#define IRDA_DMA_RX_DISABLE 0x00000000U

IRDA DMA RX disabled

Definition at line 373 of file stm32wbxx_hal_irda.h.

#define IRDA_DMA_RX_ENABLE USART_CR3_DMAR

IRDA DMA RX enabled

Definition at line 374 of file stm32wbxx_hal_irda.h.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IRDA Request Parameters

Defines
IRDA Request Parameters
IRDA Exported Constants

Defines

#define | IRDA_AUTOBAUD_REQUEST USART_RQR_ABRRQ
#define | IRDA_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ
#define | IRDA_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ

Define Documentation

#define IRDA_AUTOBAUD_REQUEST USART_RQR_ABRRQ

Auto-Baud Rate Request

Definition at line 382 of file stm32wbxx_hal_irda.h.

#define IRDA_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ

Receive Data flush Request

Definition at line 383 of file stm32wbxx_hal_irda.h.

Referenced by IRDA_Receive_IT().

#define IRDA_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ

Transmit data flush Request

Definition at line 384 of file stm32wbxx_hal_irda.h.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IRDA Flags

Defines
IRDA Flags
IRDA Exported Constants

Elements values convention: 0xXXXX. More...

Defines

#define | IRDA_FLAG_REACK USART_ISR_REACK
#define | IRDA_FLAG_TEACK USART_ISR_TEACK
#define | IRDA_FLAG_BUSY USART_ISR_BUSY
#define | IRDA_FLAG_ABRF USART_ISR_ABRF
#define | IRDA_FLAG_ABRE USART_ISR_ABRE
#define | IRDA_FLAG_TXE USART_ISR_TXE_TXFNF
#define | IRDA_FLAG_TC USART_ISR_TC
#define | IRDA_FLAG_RXNE USART_ISR_RXNE_RXFNE
#define | IRDA_FLAG_ORE USART_ISR_ORE
#define | IRDA_FLAG_NE USART_ISR_NE
#define | IRDA_FLAG_FE USART_ISR_FE
#define | IRDA_FLAG_PE USART_ISR_PE

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the ISR register

Define Documentation

#define IRDA_FLAG_ABRE USART_ISR_ABRE

IRDA auto Baud rate error

Definition at line 398 of file stm32wbxx_hal_irda.h.

#define IRDA_FLAG_ABRF USART_ISR_ABRF

IRDA auto Baud rate flag

Definition at line 397 of file stm32wbxx_hal_irda.h.

#define IRDA_FLAG_BUSY USART_ISR_BUSY

IRDA busy flag

Definition at line 396 of file stm32wbxx_hal_irda.h.

#define IRDA_FLAG_FE USART_ISR_FE

IRDA frame error

Definition at line 404 of file stm32wbxx_hal_irda.h.

#define IRDA_FLAG_NE USART_ISR_NE

IRDA noise error

Definition at line 403 of file stm32wbxx_hal_irda.h.

#define IRDA_FLAG_ORE USART_ISR_ORE

IRDA overrun error

Definition at line 402 of file stm32wbxx_hal_irda.h.

#define IRDA_FLAG_PE USART_ISR_PE

IRDA parity error

Definition at line 405 of file stm32wbxx_hal_irda.h.

#define IRDA_FLAG_REACK USART_ISR_REACK

IRDA receive enable acknowledge flag

Definition at line 394 of file stm32wbxx_hal_irda.h.

#define IRDA_FLAG_RXNE USART_ISR_RXNE_RXFNE

IRDA read data register not empty

Definition at line 401 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_Receive().

#define IRDA_FLAG_TC USART_ISR_TC

IRDA transmission complete

Definition at line 400 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_Transmit().

#define IRDA_FLAG_TEACK USART_ISR_TEACK

IRDA transmit enable acknowledge flag

Definition at line 395 of file stm32wbxx_hal_irda.h.

#define IRDA_FLAG_TXE USART_ISR_TXE_TXFNF

IRDA transmit data register empty

Definition at line 399 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_Transmit().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IRDA Interrupts Definition

Defines
IRDA Interrupts Definition
IRDA Exported Constants

Elements values convention: 0000ZZZZ0XXYYYYYb. More...

Defines

#define | IRDA_IT_PE 0x0028U
#define | IRDA_IT_TXE 0x0727U
#define | IRDA_IT_TC 0x0626U
#define | IRDA_IT_RXNE 0x0525U
#define | IRDA_IT_IDLE 0x0424U
#define | IRDA_IT_ERR 0x0060U
#define | IRDA_IT_ORE 0x0300U
#define | IRDA_IT_NE 0x0200U
#define | IRDA_IT_FE 0x0100U

Detailed Description

Elements values convention: 0000ZZZZ0XXYYYYYb.

  • YYYYY : Interrupt source position in the XX register (5bits)
  • XX : Interrupt source register (2bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register
  • ZZZZ : Flag position in the ISR register(4bits)

Define Documentation

#define IRDA_IT_ERR 0x0060U

IRDA Error interruption

Definition at line 432 of file stm32wbxx_hal_irda.h.

#define IRDA_IT_FE 0x0100U

IRDA Frame error interruption

Definition at line 438 of file stm32wbxx_hal_irda.h.

#define IRDA_IT_IDLE 0x0424U

IRDA Idle interruption

Definition at line 424 of file stm32wbxx_hal_irda.h.

#define IRDA_IT_NE 0x0200U

IRDA Noise error interruption

Definition at line 437 of file stm32wbxx_hal_irda.h.

#define IRDA_IT_ORE 0x0300U

IRDA Overrun error interruption

Definition at line 436 of file stm32wbxx_hal_irda.h.

#define IRDA_IT_PE 0x0028U

IRDA Parity error interruption

Definition at line 420 of file stm32wbxx_hal_irda.h.

#define IRDA_IT_RXNE 0x0525U

IRDA Read data register not empty interruption

Definition at line 423 of file stm32wbxx_hal_irda.h.

#define IRDA_IT_TC 0x0626U

IRDA Transmission complete interruption

Definition at line 422 of file stm32wbxx_hal_irda.h.

#define IRDA_IT_TXE 0x0727U

IRDA Transmit data register empty interruption

Definition at line 421 of file stm32wbxx_hal_irda.h.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IRDA Interruption Clear Flags

Defines
IRDA Interruption Clear Flags
IRDA Exported Constants

Defines

#define | IRDA_CLEAR_PEF USART_ICR_PECF
#define | IRDA_CLEAR_FEF USART_ICR_FECF
#define | IRDA_CLEAR_NEF USART_ICR_NECF
#define | IRDA_CLEAR_OREF USART_ICR_ORECF
#define | IRDA_CLEAR_IDLEF USART_ICR_IDLECF
#define | IRDA_CLEAR_TCF USART_ICR_TCCF

Define Documentation

#define IRDA_CLEAR_FEF USART_ICR_FECF

Framing Error Clear Flag

Definition at line 447 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_IRQHandler(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), and IRDA_DMATxAbortCallback().

#define IRDA_CLEAR_IDLEF USART_ICR_IDLECF

IDLE line detected Clear Flag

Definition at line 450 of file stm32wbxx_hal_irda.h.

#define IRDA_CLEAR_NEF USART_ICR_NECF

Noise Error detected Clear Flag

Definition at line 448 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_IRQHandler(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), and IRDA_DMATxAbortCallback().

#define IRDA_CLEAR_OREF USART_ICR_ORECF

OverRun Error Clear Flag

Definition at line 449 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_IRQHandler(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), and IRDA_DMATxAbortCallback().

#define IRDA_CLEAR_PEF USART_ICR_PECF

Parity Error Clear Flag

Definition at line 446 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_IRQHandler(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), and IRDA_DMATxAbortCallback().

#define IRDA_CLEAR_TCF USART_ICR_TCCF

Transmission Complete Clear Flag

Definition at line 451 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_Transmit_DMA().

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IRDA interruptions flags mask

Defines
IRDA interruptions flags mask
IRDA Exported Constants

Defines

#define | IRDA_IT_MASK 0x001FU
#define | IRDA_CR_MASK 0x00E0U
#define | IRDA_CR_POS 5U
#define | IRDA_ISR_MASK 0x1F00U
#define | IRDA_ISR_POS 8U

Define Documentation

#define IRDA_CR_MASK 0x00E0U

IRDA control register mask

Definition at line 460 of file stm32wbxx_hal_irda.h.

#define IRDA_CR_POS 5U

IRDA control register position

Definition at line 461 of file stm32wbxx_hal_irda.h.

#define IRDA_ISR_MASK 0x1F00U

IRDA ISR register mask

Definition at line 462 of file stm32wbxx_hal_irda.h.

#define IRDA_ISR_POS 8U

IRDA ISR register position

Definition at line 463 of file stm32wbxx_hal_irda.h.

#define IRDA_IT_MASK 0x001FU

IRDA Interruptions flags mask

Definition at line 459 of file stm32wbxx_hal_irda.h.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IRDA Exported Macros

Defines
IRDA Exported Macros
IRDA

Defines

#define | __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)
Reset IRDA handle state.
#define | __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__)
Flush the IRDA DR register.
#define | __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified IRDA pending flag.
#define | __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
Clear the IRDA PE pending flag.
#define | __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
Clear the IRDA FE pending flag.
#define | __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
Clear the IRDA NE pending flag.
#define | __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
Clear the IRDA ORE pending flag.
#define | __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
Clear the IRDA IDLE pending flag.
#define | __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified IRDA flag is set or not.
#define | __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified IRDA interrupt.
#define | __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified IRDA interrupt.
#define | __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET)
Check whether the specified IRDA interrupt has occurred or not.
#define | __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified IRDA interrupt source is enabled or not.
#define | __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
#define | __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific IRDA request flag.
#define | __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the IRDA one bit sample method.
#define | __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
Disable the IRDA one bit sample method.
#define | __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable UART/USART associated to IRDA Handle.
#define | __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable UART/USART associated to IRDA Handle.

Define Documentation

#define __HAL_IRDA_CLEAR_FEFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)

Clear the IRDA FE pending flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 531 of file stm32wbxx_hal_irda.h.

#define __HAL_IRDA_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the specified IRDA pending flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__FLAG__ specifies the flag to check. This parameter can be any combination of the following values:
  • IRDA_CLEAR_PEF
  • IRDA_CLEAR_FEF
  • IRDA_CLEAR_NEF
  • IRDA_CLEAR_OREF
  • IRDA_CLEAR_TCF
  • IRDA_CLEAR_IDLEF
Return values:
None

Definition at line 518 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_Transmit_DMA(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), and IRDA_DMATxAbortCallback().

#define __HAL_IRDA_CLEAR_IDLEFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)

Clear the IRDA IDLE pending flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 549 of file stm32wbxx_hal_irda.h.

#define __HAL_IRDA_CLEAR_IT | ( | __HANDLE__,
 |  | __IT_CLEAR__
 | ) | ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))

Clear the specified IRDA ISR flag, in setting the proper ICR register flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__IT_CLEAR__ specifies the interrupt clear register flag that needs to be set to clear the corresponding interrupt This parameter can be one of the following values:
  • IRDA_CLEAR_PEF Parity Error Clear Flag
  • IRDA_CLEAR_FEF Framing Error Clear Flag
  • IRDA_CLEAR_NEF Noise detected Clear Flag
  • IRDA_CLEAR_OREF OverRun Error Clear Flag
  • IRDA_CLEAR_TCF Transmission Complete Clear Flag
Return values:
None

Definition at line 649 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define __HAL_IRDA_CLEAR_NEFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)

Clear the IRDA NE pending flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 537 of file stm32wbxx_hal_irda.h.

#define __HAL_IRDA_CLEAR_OREFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)

Clear the IRDA ORE pending flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 543 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_DMAResume().

#define __HAL_IRDA_CLEAR_PEFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)

Clear the IRDA PE pending flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 524 of file stm32wbxx_hal_irda.h.

#define __HAL_IRDA_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

Disable UART/USART associated to IRDA Handle.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 686 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_DeInit(), and HAL_IRDA_Init().

#define __HAL_IRDA_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
                                                           ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
                                                           ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))))

Disable the specified IRDA interrupt.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__INTERRUPT__ specifies the IRDA interrupt source to disable. This parameter can be one of the following values:
  • IRDA_IT_TXE Transmit Data Register empty interrupt
  • IRDA_IT_TC Transmission complete interrupt
  • IRDA_IT_RXNE Receive Data register not empty interrupt
  • IRDA_IT_IDLE Idle line detection interrupt
  • IRDA_IT_PE Parity Error interrupt
  • IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
Return values:
None

Definition at line 600 of file stm32wbxx_hal_irda.h.

#define __HAL_IRDA_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

Enable UART/USART associated to IRDA Handle.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 680 of file stm32wbxx_hal_irda.h.

Referenced by HAL_IRDA_Init().

#define __HAL_IRDA_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
                                                           ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
                                                           ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))))

Enable the specified IRDA interrupt.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__INTERRUPT__ specifies the IRDA interrupt source to enable. This parameter can be one of the following values:
  • IRDA_IT_TXE Transmit Data Register empty interrupt
  • IRDA_IT_TC Transmission complete interrupt
  • IRDA_IT_RXNE Receive Data register not empty interrupt
  • IRDA_IT_IDLE Idle line detection interrupt
  • IRDA_IT_PE Parity Error interrupt
  • IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
Return values:
None

Definition at line 584 of file stm32wbxx_hal_irda.h.

#define __HAL_IRDA_FLUSH_DRREGISTER ( __HANDLE__ )
Value:
do{                                                                    \
         SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
         SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
      } while(0)

Flush the IRDA DR register.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 500 of file stm32wbxx_hal_irda.h.

#define __HAL_IRDA_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))

Check whether the specified IRDA flag is set or not.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • IRDA_FLAG_REACK Receive enable acknowledge flag
  • IRDA_FLAG_TEACK Transmit enable acknowledge flag
  • IRDA_FLAG_BUSY Busy flag
  • IRDA_FLAG_ABRF Auto Baud rate detection flag
  • IRDA_FLAG_ABRE Auto Baud rate detection error flag
  • IRDA_FLAG_TXE Transmit data register empty flag
  • IRDA_FLAG_TC Transmission Complete flag
  • IRDA_FLAG_RXNE Receive data register not empty flag
  • IRDA_FLAG_ORE OverRun Error flag
  • IRDA_FLAG_NE Noise Error flag
  • IRDA_FLAG_FE Framing Error flag
  • IRDA_FLAG_PE Parity Error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 569 of file stm32wbxx_hal_irda.h.

Referenced by IRDA_WaitOnFlagUntilTimeout().

#define __HAL_IRDA_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->ISR & (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET)

Check whether the specified IRDA interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__INTERRUPT__ specifies the IRDA interrupt source to check. This parameter can be one of the following values:
  • IRDA_IT_TXE Transmit Data Register empty interrupt
  • IRDA_IT_TC Transmission complete interrupt
  • IRDA_IT_RXNE Receive Data register not empty interrupt
  • IRDA_IT_IDLE Idle line detection interrupt
  • IRDA_IT_ORE OverRun Error interrupt
  • IRDA_IT_NE Noise Error interrupt
  • IRDA_IT_FE Framing Error interrupt
  • IRDA_IT_PE Parity Error interrupt
Return values:
The new state of __IT__ (SET or RESET).

Definition at line 619 of file stm32wbxx_hal_irda.h.

#define __HAL_IRDA_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \
                                                               (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
                                                               (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)

Check whether the specified IRDA interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__INTERRUPT__ specifies the IRDA interrupt source to check. This parameter can be one of the following values:
  • IRDA_IT_TXE Transmit Data Register empty interrupt
  • IRDA_IT_TC Transmission complete interrupt
  • IRDA_IT_RXNE Receive Data register not empty interrupt
  • IRDA_IT_IDLE Idle line detection interrupt
  • IRDA_IT_ERR Framing, overrun or noise error interrupt
  • IRDA_IT_PE Parity Error interrupt
Return values:
The new state of __IT__ (SET or RESET).

Definition at line 633 of file stm32wbxx_hal_irda.h.

#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))

Disable the IRDA one bit sample method.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 674 of file stm32wbxx_hal_irda.h.

#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)

Enable the IRDA one bit sample method.

Parameters:
__HANDLE__ specifies the IRDA Handle.
Return values:
None

Definition at line 668 of file stm32wbxx_hal_irda.h.

#define __HAL_IRDA_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                   \
                                                       (__HANDLE__)->gState = HAL_IRDA_STATE_RESET;      \
                                                       (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET;     \
                                                       (__HANDLE__)->MspInitCallback = NULL;             \
                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \
                                                     } while(0)

Reset IRDA handle state.

Parameters:
__HANDLE__ IRDA handle.
Return values:
None

Definition at line 483 of file stm32wbxx_hal_irda.h.

#define __HAL_IRDA_SEND_REQ | ( | __HANDLE__,
 |  | __REQ__
 | ) | ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))

Set a specific IRDA request flag.

Parameters:
__HANDLE__ specifies the IRDA Handle.
__REQ__ specifies the request flag to set This parameter can be one of the following values:
  • IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request
  • IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request
  • IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request
Return values:
None

Definition at line 662 of file stm32wbxx_hal_irda.h.

Referenced by IRDA_Receive_IT().

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IRDAEx Private Macros

Defines
IRDAEx Private Macros
IRDAEx

Defines

#define IRDA_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the IRDA clock source.

Define Documentation

#define IRDA_GETCLOCKSOURCE | ( | __HANDLE__,
 |  | __CLOCKSOURCE__
 | ) |
Value:
do {                                                         \
    if((__HANDLE__)->Instance == USART1)                       \
    {                                                          \
       switch(__HAL_RCC_GET_USART1_SOURCE())                   \
       {                                                       \
        case RCC_USART1CLKSOURCE_PCLK2:                        \
          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2;          \
          break;                                               \
        case RCC_USART1CLKSOURCE_HSI:                          \
          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;            \
          break;                                               \
        case RCC_USART1CLKSOURCE_SYSCLK:                       \
          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;         \
          break;                                               \
        case RCC_USART1CLKSOURCE_LSE:                          \
          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;            \
          break;                                               \
        default:                                               \
          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;      \
          break;                                               \
       }                                                       \
    }                                                          \
    else                                                       \
    {                                                          \
      (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;          \
    }                                                          \
  } while(0U)

Report the IRDA clock source.

Parameters:
__HANDLE__ | specifies the IRDA Handle.
__CLOCKSOURCE__ | output variable.
Return values:
IRDA clocking source, written in __CLOCKSOURCE__.

Definition at line 55 of file stm32wbxx_hal_irda_ex.h.

Referenced by IRDA_SetConfig().

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IWDG Private Defines

Defines
IWDG Private Defines
IWDG

Defines

#define HAL_IWDG_DEFAULT_TIMEOUT 48u

Define Documentation

#define HAL_IWDG_DEFAULT_TIMEOUT 48u

Definition at line 114 of file stm32wbxx_hal_iwdg.c.

Referenced by HAL_IWDG_Init().

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IWDG_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
IWDG_InitTypeDef Struct Reference
IWDG Exported Types

IWDG Init structure definition. More...

#include <stm32wbxx_hal_iwdg.h>

Data Fields

uint32_t | Prescaler
uint32_t | Reload
uint32_t | Window

Detailed Description

IWDG Init structure definition.

Definition at line 47 of file stm32wbxx_hal_iwdg.h.

Field Documentation

uint32_t IWDG_InitTypeDef::Prescaler

Select the prescaler of the IWDG. This parameter can be a value of IWDG Prescaler

Definition at line 49 of file stm32wbxx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

uint32_t IWDG_InitTypeDef::Reload

Specifies the IWDG down-counter reload value. This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF

Definition at line 52 of file stm32wbxx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

uint32_t IWDG_InitTypeDef::Window

Specifies the window value to be compared to the down-counter. This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF

Definition at line 55 of file stm32wbxx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_iwdg.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IWDG_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
IWDG_HandleTypeDef Struct Reference
IWDG Exported Types

IWDG Handle Structure definition. More...

#include <stm32wbxx_hal_iwdg.h>

Data Fields

IWDG_TypeDef * Instance
IWDG_InitTypeDef Init

Detailed Description

IWDG Handle Structure definition.

Definition at line 63 of file stm32wbxx_hal_iwdg.h.

Field Documentation

IWDG_InitTypeDef IWDG_HandleTypeDef::Init

IWDG required parameters

Definition at line 67 of file stm32wbxx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

IWDG_TypeDef* IWDG_HandleTypeDef::Instance

Register base address

Definition at line 65 of file stm32wbxx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_iwdg.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IWDG Prescaler

Defines
IWDG Prescaler
IWDG Exported Constants

Defines

#define | IWDG_PRESCALER_4 0x00000000u
#define | IWDG_PRESCALER_8 IWDG_PR_PR_0
#define | IWDG_PRESCALER_16 IWDG_PR_PR_1
#define | IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)
#define | IWDG_PRESCALER_64 IWDG_PR_PR_2
#define | IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)
#define | IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)

Define Documentation

#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)

IWDG prescaler set to 128

Definition at line 88 of file stm32wbxx_hal_iwdg.h.

#define IWDG_PRESCALER_16 IWDG_PR_PR_1

IWDG prescaler set to 16

Definition at line 85 of file stm32wbxx_hal_iwdg.h.

#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)

IWDG prescaler set to 256

Definition at line 89 of file stm32wbxx_hal_iwdg.h.

#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)

IWDG prescaler set to 32

Definition at line 86 of file stm32wbxx_hal_iwdg.h.

#define IWDG_PRESCALER_4 0x00000000u

IWDG prescaler set to 4

Definition at line 83 of file stm32wbxx_hal_iwdg.h.

#define IWDG_PRESCALER_64 IWDG_PR_PR_2

IWDG prescaler set to 64

Definition at line 87 of file stm32wbxx_hal_iwdg.h.

#define IWDG_PRESCALER_8 IWDG_PR_PR_0

IWDG prescaler set to 8

Definition at line 84 of file stm32wbxx_hal_iwdg.h.

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STM32WB55xx HAL User Manual: IWDG Window option

Defines
IWDG Window option
IWDG Exported Constants

Defines

#define IWDG_WINDOW_DISABLE IWDG_WINR_WIN

Define Documentation

#define IWDG_WINDOW_DISABLE IWDG_WINR_WIN

Definition at line 98 of file stm32wbxx_hal_iwdg.h.

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STM32WB55xx HAL User Manual: IWDG Exported Macros

Defines
IWDG Exported Macros
IWDG

Defines

#define | __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
Enable the IWDG peripheral.
#define | __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
Reload IWDG counter with value defined in the reload register (write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers disabled).

Define Documentation

#define __HAL_IWDG_RELOAD_COUNTER ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)

Reload IWDG counter with value defined in the reload register (write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers disabled).

Parameters:
__HANDLE__ IWDG handle
Return values:
None

Definition at line 126 of file stm32wbxx_hal_iwdg.h.

Referenced by HAL_IWDG_Init(), and HAL_IWDG_Refresh().

#define __HAL_IWDG_START ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)

Enable the IWDG peripheral.

Parameters:
__HANDLE__ IWDG handle
Return values:
None

Definition at line 118 of file stm32wbxx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization and Start functions

Functions
Initialization and Start functions
IWDG Exported Functions

Initialization and Start functions. More...

Functions

HAL_StatusTypeDef HAL_IWDG_Init (IWDG_HandleTypeDef *hiwdg)
Initialize the IWDG according to the specified parameters in the IWDG_InitTypeDef and start watchdog.

Detailed Description

Initialization and Start functions.

 ===============================================================================
          ##### Initialization and Start functions #####
 ===============================================================================
 [..]  This section provides functions allowing to:
      (+) Initialize the IWDG according to the specified parameters in the
          IWDG_InitTypeDef of associated handle.
      (+) Manage Window option.
      (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
          is reloaded in order to exit function with correct time base.

Function Documentation

HAL_StatusTypeDef HAL_IWDG_Init ( IWDG_HandleTypeDef * hiwdg )

Initialize the IWDG according to the specified parameters in the IWDG_InitTypeDef and start watchdog.

Before exiting function, watchdog is refreshed in order to have correct time base.

Parameters:
hiwdg pointer to a IWDG_HandleTypeDef structure that contains the configuration information for the specified IWDG module.
Return values:
HAL status

Definition at line 154 of file stm32wbxx_hal_iwdg.c.

References __HAL_IWDG_RELOAD_COUNTER, __HAL_IWDG_START, assert_param, HAL_GetTick(), HAL_IWDG_DEFAULT_TIMEOUT, IWDG_HandleTypeDef::Init, IWDG_HandleTypeDef::Instance, IS_IWDG_PRESCALER, IS_IWDG_RELOAD, IS_IWDG_WINDOW, IWDG_ENABLE_WRITE_ACCESS, IWDG_InitTypeDef::Prescaler, IWDG_InitTypeDef::Reload, and IWDG_InitTypeDef::Window.

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STM32WB55xx HAL User Manual: IO operation functions

Functions
IO operation functions
IWDG Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef HAL_IWDG_Refresh (IWDG_HandleTypeDef *hiwdg)
Refresh the IWDG.

Detailed Description

IO operation functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
 [..]  This section provides functions allowing to:
      (+) Refresh the IWDG.

Function Documentation

HAL_StatusTypeDef HAL_IWDG_Refresh ( IWDG_HandleTypeDef * hiwdg )

Refresh the IWDG.

Parameters:
hiwdg pointer to a IWDG_HandleTypeDef structure that contains the configuration information for the specified IWDG module.
Return values:
HAL status

Definition at line 238 of file stm32wbxx_hal_iwdg.c.

References __HAL_IWDG_RELOAD_COUNTER.

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STM32WB55xx HAL User Manual: IWDG Private Constants

Defines
IWDG Private Constants
IWDG

Defines

#define | IWDG_KEY_RELOAD 0x0000AAAAu
IWDG Key Register BitMask.
#define | IWDG_KEY_ENABLE 0x0000CCCCu
#define | IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u
#define | IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u

Define Documentation

#define IWDG_KEY_ENABLE 0x0000CCCCu

IWDG Peripheral Enable

Definition at line 168 of file stm32wbxx_hal_iwdg.h.

#define IWDG_KEY_RELOAD 0x0000AAAAu

IWDG Key Register BitMask.

IWDG Reload Counter Enable

Definition at line 167 of file stm32wbxx_hal_iwdg.h.

#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u

IWDG KR Write Access Disable

Definition at line 170 of file stm32wbxx_hal_iwdg.h.

#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u

IWDG KR Write Access Enable

Definition at line 169 of file stm32wbxx_hal_iwdg.h.

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STM32WB55xx HAL User Manual: IWDG Private Macros

Defines
IWDG Private Macros
IWDG

Defines

#define | IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
#define | IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
#define | IS_IWDG_PRESCALER(__PRESCALER__)
Check IWDG prescaler value.
#define | IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
Check IWDG reload value.
#define | IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
Check IWDG window value.

Define Documentation

#define IS_IWDG_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == IWDG_PRESCALER_4)  || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_8)  || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_16) || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_32) || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_64) || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
                                               ((__PRESCALER__) == IWDG_PRESCALER_256))

Check IWDG prescaler value.

Parameters:
__PRESCALER__ IWDG prescaler value
Return values:
None

Definition at line 200 of file stm32wbxx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

#define IS_IWDG_RELOAD ( __RELOAD__ ) ((__RELOAD__) <= IWDG_RLR_RL)

Check IWDG reload value.

Parameters:
__RELOAD__ IWDG reload value
Return values:
None

Definition at line 213 of file stm32wbxx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

#define IS_IWDG_WINDOW ( __WINDOW__ ) ((__WINDOW__) <= IWDG_WINR_WIN)

Check IWDG window value.

Parameters:
__WINDOW__ IWDG window value
Return values:
None

Definition at line 220 of file stm32wbxx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

#define IWDG_DISABLE_WRITE_ACCESS ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)

Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.

Parameters:
__HANDLE__ IWDG handle
Return values:
None

Definition at line 193 of file stm32wbxx_hal_iwdg.h.

#define IWDG_ENABLE_WRITE_ACCESS ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)

Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.

Parameters:
__HANDLE__ IWDG handle
Return values:
None

Definition at line 186 of file stm32wbxx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

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STM32WB55xx HAL User Manual: LCD Private Defines

Defines
LCD Private Defines
LCD

Defines

#define LCD_TIMEOUT_VALUE 1000U

Define Documentation

#define LCD_TIMEOUT_VALUE 1000U

Definition at line 105 of file stm32wbxx_hal_lcd.c.

Referenced by HAL_LCD_Clear(), HAL_LCD_Init(), HAL_LCD_UpdateDisplayRequest(), HAL_LCD_Write(), and LCD_WaitForSynchro().

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STM32WB55xx HAL User Manual: Initialization/de-initialization methods

Functions
Initialization/de-initialization methods
LCD Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_LCD_Init (LCD_HandleTypeDef *hlcd)
Initialize the LCD peripheral according to the specified parameters in the LCD_InitStruct and initialize the associated handle.
HAL_StatusTypeDef | HAL_LCD_DeInit (LCD_HandleTypeDef *hlcd)
DeInitialize the LCD peripheral.
__weak void | HAL_LCD_MspDeInit (LCD_HandleTypeDef *hlcd)
DeInitialize the LCD MSP.
__weak void | HAL_LCD_MspInit (LCD_HandleTypeDef *hlcd)
Initialize the LCD MSP.

Detailed Description

Initialization and Configuration functions.

===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]

Function Documentation

HAL_StatusTypeDef HAL_LCD_DeInit ( LCD_HandleTypeDef * hlcd )

DeInitialize the LCD peripheral.

Parameters:
hlcd LCD handle
Return values:
HAL status

Definition at line 263 of file stm32wbxx_hal_lcd.c.

References assert_param, LCD_HandleTypeDef::ErrorCode, HAL_LCD_ERROR_NONE, HAL_LCD_MspDeInit(), HAL_LCD_STATE_BUSY, HAL_LCD_STATE_RESET, LCD_HandleTypeDef::Instance, and LCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LCD_Init ( LCD_HandleTypeDef * hlcd )

Initialize the LCD peripheral according to the specified parameters in the LCD_InitStruct and initialize the associated handle.

Note:
This function can be used only when the LCD is disabled.
Parameters:
hlcd LCD handle
Return values:
None

< Wait Until the LCD Booster is ready

Definition at line 140 of file stm32wbxx_hal_lcd.c.

References __HAL_LCD_DISABLE, __HAL_LCD_ENABLE, __HAL_LCD_GET_FLAG, assert_param, LCD_InitTypeDef::Bias, LCD_InitTypeDef::BlinkFrequency, LCD_InitTypeDef::BlinkMode, LCD_InitTypeDef::Contrast, LCD_InitTypeDef::DeadTime, LCD_InitTypeDef::Divider, LCD_InitTypeDef::Duty, LCD_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_LCD_ERROR_ENS, HAL_LCD_ERROR_NONE, HAL_LCD_ERROR_RDY, HAL_LCD_MspInit(), HAL_LCD_STATE_BUSY, HAL_LCD_STATE_READY, HAL_LCD_STATE_RESET, LCD_InitTypeDef::HighDrive, LCD_HandleTypeDef::Init, LCD_HandleTypeDef::Instance, IS_LCD_BIAS, IS_LCD_BLINK_FREQUENCY, IS_LCD_BLINK_MODE, IS_LCD_CONTRAST, IS_LCD_DEAD_TIME, IS_LCD_DIVIDER, IS_LCD_DUTY, IS_LCD_HIGH_DRIVE, IS_LCD_MUX_SEGMENT, IS_LCD_PRESCALER, IS_LCD_PULSE_ON_DURATION, IS_LCD_VOLTAGE_SOURCE, LCD_FLAG_ENS, LCD_FLAG_RDY, LCD_RAM_REGISTER0, LCD_RAM_REGISTER7, LCD_TIMEOUT_VALUE, LCD_WaitForSynchro(), LCD_HandleTypeDef::Lock, LCD_InitTypeDef::MuxSegment, LCD_InitTypeDef::Prescaler, LCD_InitTypeDef::PulseOnDuration, LCD_HandleTypeDef::State, and LCD_InitTypeDef::VoltageSource.

void HAL_LCD_MspDeInit ( LCD_HandleTypeDef * hlcd )

DeInitialize the LCD MSP.

Parameters:
hlcd LCD handle
Return values:
None

Definition at line 293 of file stm32wbxx_hal_lcd.c.

Referenced by HAL_LCD_DeInit().

void HAL_LCD_MspInit ( LCD_HandleTypeDef * hlcd )

Initialize the LCD MSP.

Parameters:
hlcd LCD handle
Return values:
None

Definition at line 308 of file stm32wbxx_hal_lcd.c.

Referenced by HAL_LCD_Init().

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STM32WB55xx HAL User Manual: IO operation methods

Functions
IO operation methods
LCD Exported Functions

LCD RAM functions. More...

Functions

HAL_StatusTypeDef | HAL_LCD_Write (LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterIndex, uint32_t RAMRegisterMask, uint32_t Data)
Write a word in the specific LCD RAM.
HAL_StatusTypeDef | HAL_LCD_Clear (LCD_HandleTypeDef *hlcd)
Clear the LCD RAM registers.
HAL_StatusTypeDef | HAL_LCD_UpdateDisplayRequest (LCD_HandleTypeDef *hlcd)
Enable the Update Display Request.

Detailed Description

LCD RAM functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
 [..] Using its double buffer memory the LCD controller ensures the coherency of the
 displayed information without having to use interrupts to control LCD_RAM
 modification.
 The application software can access the first buffer level (LCD_RAM) through
 the APB interface. Once it has modified the LCD_RAM using the HAL_LCD_Write() API,
 it sets the UDR flag in the LCD_SR register using the HAL_LCD_UpdateDisplayRequest() API.
 This UDR flag (update display request) requests the updated information to be
 moved into the second buffer level (LCD_DISPLAY).
 This operation is done synchronously with the frame (at the beginning of the
 next frame), until the update is completed, the LCD_RAM is write protected and
 the UDR flag stays high.
 Once the update is completed another flag (UDD - Update Display Done) is set and
 generates an interrupt if the UDDIE bit in the LCD_FCR register is set.
 The time it takes to update LCD_DISPLAY is, in the worst case, one odd and one
 even frame.
 The update will not occur (UDR = 1 and UDD = 0) until the display is
 enabled (LCDEN = 1).

Function Documentation

HAL_StatusTypeDef HAL_LCD_Clear ( LCD_HandleTypeDef * hlcd )

Clear the LCD RAM registers.

Parameters:
hlcd LCD handle
Return values:
None

< Wait Until the LCD is ready

Definition at line 426 of file stm32wbxx_hal_lcd.c.

References __HAL_LCD_GET_FLAG, LCD_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_LCD_ERROR_UDR, HAL_LCD_STATE_BUSY, HAL_LCD_STATE_READY, HAL_LCD_UpdateDisplayRequest(), LCD_HandleTypeDef::Instance, LCD_FLAG_UDR, LCD_RAM_REGISTER0, LCD_RAM_REGISTER15, LCD_TIMEOUT_VALUE, and LCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LCD_UpdateDisplayRequest ( LCD_HandleTypeDef * hlcd )

Enable the Update Display Request.

Parameters:
hlcd LCD handle
Note:
Each time software modifies the LCD_RAM it must set the UDR bit to transfer the updated data to the second level buffer. The UDR bit stays set until the end of the update and during this time the LCD_RAM is write protected.
When the display is disabled, the update is performed for all LCD_DISPLAY locations. When the display is enabled, the update is performed only for locations for which commons are active (depending on DUTY). For example if DUTY = 1/2, only the LCD_DISPLAY of COM0 and COM1 will be updated.
Return values:
None

< Wait Until the LCD display is done

Definition at line 482 of file stm32wbxx_hal_lcd.c.

References __HAL_LCD_CLEAR_FLAG, __HAL_LCD_GET_FLAG, LCD_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_LCD_ERROR_UDD, HAL_LCD_STATE_READY, LCD_HandleTypeDef::Instance, LCD_FLAG_UDD, LCD_TIMEOUT_VALUE, and LCD_HandleTypeDef::State.

Referenced by HAL_LCD_Clear().

HAL_StatusTypeDef HAL_LCD_Write | ( | LCD_HandleTypeDef * | hlcd,
 |  | uint32_t | RAMRegisterIndex,
 |  | uint32_t | RAMRegisterMask,
 |  | uint32_t | Data
 | ) |  |

Write a word in the specific LCD RAM.

Parameters:
hlcd | LCD handle
RAMRegisterIndex specifies the LCD RAM Register. This parameter can be one of the following values:
  • LCD_RAM_REGISTER0: LCD RAM Register 0
  • LCD_RAM_REGISTER1: LCD RAM Register 1
  • LCD_RAM_REGISTER2: LCD RAM Register 2
  • LCD_RAM_REGISTER3: LCD RAM Register 3
  • LCD_RAM_REGISTER4: LCD RAM Register 4
  • LCD_RAM_REGISTER5: LCD RAM Register 5
  • LCD_RAM_REGISTER6: LCD RAM Register 6
  • LCD_RAM_REGISTER7: LCD RAM Register 7
  • LCD_RAM_REGISTER8: LCD RAM Register 8
  • LCD_RAM_REGISTER9: LCD RAM Register 9
  • LCD_RAM_REGISTER10: LCD RAM Register 10
  • LCD_RAM_REGISTER11: LCD RAM Register 11
  • LCD_RAM_REGISTER12: LCD RAM Register 12
  • LCD_RAM_REGISTER13: LCD RAM Register 13
  • LCD_RAM_REGISTER14: LCD RAM Register 14
  • LCD_RAM_REGISTER15: LCD RAM Register 15
RAMRegisterMask | specifies the LCD RAM Register Data Mask.
Data | specifies LCD Data Value to be written.
Return values:
None

< Wait Until the LCD is ready

Definition at line 376 of file stm32wbxx_hal_lcd.c.

References __HAL_LCD_GET_FLAG, assert_param, LCD_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_LCD_ERROR_UDR, HAL_LCD_STATE_BUSY, HAL_LCD_STATE_READY, LCD_HandleTypeDef::Instance, IS_LCD_RAM_REGISTER, LCD_FLAG_UDR, LCD_TIMEOUT_VALUE, and LCD_HandleTypeDef::State.

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STM32WB55xx HAL User Manual: Peripheral State methods

Functions
Peripheral State methods
LCD Exported Functions

LCD State functions. More...

Functions

HAL_LCD_StateTypeDef | HAL_LCD_GetState (LCD_HandleTypeDef *hlcd)
Return the LCD handle state.
uint32_t | HAL_LCD_GetError (LCD_HandleTypeDef *hlcd)
Return the LCD error code.

Detailed Description

LCD State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
     This subsection provides a set of functions allowing to control the LCD:
      (+) HAL_LCD_GetState() API can be helpful to check in run-time the state of the LCD peripheral State.
      (+) HAL_LCD_GetError() API to return the LCD error code.

Function Documentation

uint32_t HAL_LCD_GetError ( LCD_HandleTypeDef * hlcd )

Return the LCD error code.

Parameters:
hlcd LCD handle
Return values:
LCD Error Code

Definition at line 552 of file stm32wbxx_hal_lcd.c.

References LCD_HandleTypeDef::ErrorCode.

HAL_LCD_StateTypeDef HAL_LCD_GetState ( LCD_HandleTypeDef * hlcd )

Return the LCD handle state.

Parameters:
hlcd LCD handle
Return values:
HAL state

Definition at line 541 of file stm32wbxx_hal_lcd.c.

References LCD_HandleTypeDef::State.

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STM32WB55xx HAL User Manual: LCD Private Functions

Functions
LCD Private Functions
LCD

Functions

HAL_StatusTypeDef LCD_WaitForSynchro (LCD_HandleTypeDef *hlcd)
Wait until the LCD FCR register is synchronized in the LCDCLK domain.

Function Documentation

HAL_StatusTypeDef LCD_WaitForSynchro ( LCD_HandleTypeDef * hlcd )

Wait until the LCD FCR register is synchronized in the LCDCLK domain.

This function must be called after any write operation to LCD_FCR register.

Return values:
None

Definition at line 574 of file stm32wbxx_hal_lcd.c.

References __HAL_LCD_GET_FLAG, LCD_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_LCD_ERROR_FCRSF, LCD_FLAG_FCRSF, and LCD_TIMEOUT_VALUE.

Referenced by HAL_LCD_Init().

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STM32WB55xx HAL User Manual: LCD Exported Types

Data Structures | Enumerations
LCD Exported Types
LCD

Data Structures

struct | LCD_InitTypeDef
LCD Init structure definition. More...
struct | LCD_HandleTypeDef
UART handle Structure definition. More...

Enumerations

enum HAL_LCD_StateTypeDef {
HAL_LCD_STATE_RESET = 0x00, HAL_LCD_STATE_READY = 0x01, HAL_LCD_STATE_BUSY = 0x02, HAL_LCD_STATE_TIMEOUT = 0x03,
HAL_LCD_STATE_ERROR = 0x04
}
HAL LCD State structures definition. More...

Enumeration Type Documentation

enum HAL_LCD_StateTypeDef

HAL LCD State structures definition.

Enumerator:
HAL_LCD_STATE_RESET

Peripheral is not yet Initialized

HAL_LCD_STATE_READY

Peripheral Initialized and ready for use

HAL_LCD_STATE_BUSY

an internal process is ongoing

HAL_LCD_STATE_TIMEOUT

Timeout state

HAL_LCD_STATE_ERROR

Error

Definition at line 82 of file stm32wbxx_hal_lcd.h.

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STM32WB55xx HAL User Manual: LCD_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LCD_InitTypeDef Struct Reference
LCD Exported Types

LCD Init structure definition. More...

#include <stm32wbxx_hal_lcd.h>

Data Fields

uint32_t | Prescaler
uint32_t | Divider
uint32_t | Duty
uint32_t | Bias
uint32_t | VoltageSource
uint32_t | Contrast
uint32_t | DeadTime
uint32_t | PulseOnDuration
uint32_t | HighDrive
uint32_t | BlinkMode
uint32_t | BlinkFrequency
uint32_t | MuxSegment

Detailed Description

LCD Init structure definition.

Definition at line 51 of file stm32wbxx_hal_lcd.h.

Field Documentation

uint32_t LCD_InitTypeDef::Bias

Configures the LCD Bias. This parameter can be one value of LCD Bias

Definition at line 59 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Init().

uint32_t LCD_InitTypeDef::BlinkFrequency

Configures the LCD Blink frequency. This parameter can be one value of LCD Blink Frequency

Definition at line 73 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Init().

uint32_t LCD_InitTypeDef::BlinkMode

Configures the LCD Blink Mode. This parameter can be one value of LCD Blink Mode

Definition at line 71 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Init().

uint32_t LCD_InitTypeDef::Contrast

Configures the LCD Contrast. This parameter can be one value of LCD Contrast

Definition at line 63 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Init().

uint32_t LCD_InitTypeDef::DeadTime

Configures the LCD Dead Time. This parameter can be one value of LCD Dead Time

Definition at line 65 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Init().

uint32_t LCD_InitTypeDef::Divider

Configures the LCD Divider. This parameter can be one value of LCD Divider

Definition at line 55 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Init().

uint32_t LCD_InitTypeDef::Duty

Configures the LCD Duty. This parameter can be one value of LCD Duty

Definition at line 57 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Init().

uint32_t LCD_InitTypeDef::HighDrive

Enable or disable the low resistance divider. This parameter can be one value of LCD High Drive

Definition at line 69 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Init().

uint32_t LCD_InitTypeDef::MuxSegment

Enable or disable mux segment. This parameter can be one value of LCD Mux Segment

Definition at line 75 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Init().

uint32_t LCD_InitTypeDef::Prescaler

Configures the LCD Prescaler. This parameter can be one value of LCD Prescaler

Definition at line 53 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Init().

uint32_t LCD_InitTypeDef::PulseOnDuration

Configures the LCD Pulse On Duration. This parameter can be one value of LCD Pulse On Duration

Definition at line 67 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Init().

uint32_t LCD_InitTypeDef::VoltageSource

Selects the LCD Voltage source. This parameter can be one value of LCD Voltage Source

Definition at line 61 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Init().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_lcd.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LCD_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LCD_HandleTypeDef Struct Reference
LCD Exported Types

UART handle Structure definition. More...

#include <stm32wbxx_hal_lcd.h>

Data Fields

LCD_TypeDef * | Instance
LCD_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_LCD_StateTypeDef | State
__IO uint32_t | ErrorCode

Detailed Description

UART handle Structure definition.

Definition at line 94 of file stm32wbxx_hal_lcd.h.

Field Documentation

__IO uint32_t LCD_HandleTypeDef::ErrorCode

Definition at line 104 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Clear(), HAL_LCD_DeInit(), HAL_LCD_GetError(), HAL_LCD_Init(), HAL_LCD_UpdateDisplayRequest(), HAL_LCD_Write(), and LCD_WaitForSynchro().

LCD_InitTypeDef LCD_HandleTypeDef::Init

Definition at line 98 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Init().

LCD_TypeDef* LCD_HandleTypeDef::Instance

Definition at line 96 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Clear(), HAL_LCD_DeInit(), HAL_LCD_Init(), HAL_LCD_UpdateDisplayRequest(), and HAL_LCD_Write().

HAL_LockTypeDef LCD_HandleTypeDef::Lock

Definition at line 100 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Init().

__IO HAL_LCD_StateTypeDef LCD_HandleTypeDef::State

Definition at line 102 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Clear(), HAL_LCD_DeInit(), HAL_LCD_GetState(), HAL_LCD_Init(), HAL_LCD_UpdateDisplayRequest(), and HAL_LCD_Write().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_lcd.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LCD Error Code

Defines
LCD Error Code
LCD Exported Constants

Defines

#define | HAL_LCD_ERROR_NONE (0x00000000U)
#define | HAL_LCD_ERROR_FCRSF (0x00000001U)
#define | HAL_LCD_ERROR_UDR (0x00000002U)
#define | HAL_LCD_ERROR_UDD (0x00000004U)
#define | HAL_LCD_ERROR_ENS (0x00000008U)
#define | HAL_LCD_ERROR_RDY (0x00000010U)

Define Documentation

#define HAL_LCD_ERROR_ENS (0x00000008U)

LCD enabled status flag timeout error

Definition at line 123 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Init().

#define HAL_LCD_ERROR_FCRSF (0x00000001U)

Synchro flag timeout error

Definition at line 120 of file stm32wbxx_hal_lcd.h.

Referenced by LCD_WaitForSynchro().

#define HAL_LCD_ERROR_NONE (0x00000000U)

No error

Definition at line 119 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_DeInit(), and HAL_LCD_Init().

#define HAL_LCD_ERROR_RDY (0x00000010U)

LCD Booster ready timeout error

Definition at line 124 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Init().

#define HAL_LCD_ERROR_UDD (0x00000004U)

Update display done flag timeout error

Definition at line 122 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_UpdateDisplayRequest().

#define HAL_LCD_ERROR_UDR (0x00000002U)

Update display request flag timeout error

Definition at line 121 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Clear(), and HAL_LCD_Write().

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LCD Prescaler

Defines
LCD Prescaler
LCD Exported Constants

Defines

#define | LCD_PRESCALER_1 (0x00000000U)
#define | LCD_PRESCALER_2 (0x00400000U)
#define | LCD_PRESCALER_4 (0x00800000U)
#define | LCD_PRESCALER_8 (0x00C00000U)
#define | LCD_PRESCALER_16 (0x01000000U)
#define | LCD_PRESCALER_32 (0x01400000U)
#define | LCD_PRESCALER_64 (0x01800000U)
#define | LCD_PRESCALER_128 (0x01C00000U)
#define | LCD_PRESCALER_256 (0x02000000U)
#define | LCD_PRESCALER_512 (0x02400000U)
#define | LCD_PRESCALER_1024 (0x02800000U)
#define | LCD_PRESCALER_2048 (0x02C00000U)
#define | LCD_PRESCALER_4096 (0x03000000U)
#define | LCD_PRESCALER_8192 (0x03400000U)
#define | LCD_PRESCALER_16384 (0x03800000U)
#define | LCD_PRESCALER_32768 (0x03C00000U)

Define Documentation

#define LCD_PRESCALER_1 (0x00000000U)

CLKPS = LCDCLK

Definition at line 132 of file stm32wbxx_hal_lcd.h.

#define LCD_PRESCALER_1024 (0x02800000U)

CLKPS = LCDCLK/1024

Definition at line 142 of file stm32wbxx_hal_lcd.h.

#define LCD_PRESCALER_128 (0x01C00000U)

CLKPS = LCDCLK/128

Definition at line 139 of file stm32wbxx_hal_lcd.h.

#define LCD_PRESCALER_16 (0x01000000U)

CLKPS = LCDCLK/16

Definition at line 136 of file stm32wbxx_hal_lcd.h.

#define LCD_PRESCALER_16384 (0x03800000U)

CLKPS = LCDCLK/16384

Definition at line 146 of file stm32wbxx_hal_lcd.h.

#define LCD_PRESCALER_2 (0x00400000U)

CLKPS = LCDCLK/2

Definition at line 133 of file stm32wbxx_hal_lcd.h.

#define LCD_PRESCALER_2048 (0x02C00000U)

CLKPS = LCDCLK/2048

Definition at line 143 of file stm32wbxx_hal_lcd.h.

#define LCD_PRESCALER_256 (0x02000000U)

CLKPS = LCDCLK/256

Definition at line 140 of file stm32wbxx_hal_lcd.h.

#define LCD_PRESCALER_32 (0x01400000U)

CLKPS = LCDCLK/32

Definition at line 137 of file stm32wbxx_hal_lcd.h.

#define LCD_PRESCALER_32768 (0x03C00000U)

CLKPS = LCDCLK/32768

Definition at line 147 of file stm32wbxx_hal_lcd.h.

#define LCD_PRESCALER_4 (0x00800000U)

CLKPS = LCDCLK/4

Definition at line 134 of file stm32wbxx_hal_lcd.h.

#define LCD_PRESCALER_4096 (0x03000000U)

CLKPS = LCDCLK/4096

Definition at line 144 of file stm32wbxx_hal_lcd.h.

#define LCD_PRESCALER_512 (0x02400000U)

CLKPS = LCDCLK/512

Definition at line 141 of file stm32wbxx_hal_lcd.h.

#define LCD_PRESCALER_64 (0x01800000U)

CLKPS = LCDCLK/64

Definition at line 138 of file stm32wbxx_hal_lcd.h.

#define LCD_PRESCALER_8 (0x00C00000U)

CLKPS = LCDCLK/8

Definition at line 135 of file stm32wbxx_hal_lcd.h.

#define LCD_PRESCALER_8192 (0x03400000U)

CLKPS = LCDCLK/8192

Definition at line 145 of file stm32wbxx_hal_lcd.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LCD Divider

Defines
LCD Divider
LCD Exported Constants

Defines

#define | LCD_DIVIDER_16 (0x00000000U)
#define | LCD_DIVIDER_17 (0x00040000U)
#define | LCD_DIVIDER_18 (0x00080000U)
#define | LCD_DIVIDER_19 (0x000C0000U)
#define | LCD_DIVIDER_20 (0x00100000U)
#define | LCD_DIVIDER_21 (0x00140000U)
#define | LCD_DIVIDER_22 (0x00180000U)
#define | LCD_DIVIDER_23 (0x001C0000U)
#define | LCD_DIVIDER_24 (0x00200000U)
#define | LCD_DIVIDER_25 (0x00240000U)
#define | LCD_DIVIDER_26 (0x00280000U)
#define | LCD_DIVIDER_27 (0x002C0000U)
#define | LCD_DIVIDER_28 (0x00300000U)
#define | LCD_DIVIDER_29 (0x00340000U)
#define | LCD_DIVIDER_30 (0x00380000U)
#define | LCD_DIVIDER_31 (0x003C0000U)

Define Documentation

#define LCD_DIVIDER_16 (0x00000000U)

LCD frequency = CLKPS/16

Definition at line 155 of file stm32wbxx_hal_lcd.h.

#define LCD_DIVIDER_17 (0x00040000U)

LCD frequency = CLKPS/17

Definition at line 156 of file stm32wbxx_hal_lcd.h.

#define LCD_DIVIDER_18 (0x00080000U)

LCD frequency = CLKPS/18

Definition at line 157 of file stm32wbxx_hal_lcd.h.

#define LCD_DIVIDER_19 (0x000C0000U)

LCD frequency = CLKPS/19

Definition at line 158 of file stm32wbxx_hal_lcd.h.

#define LCD_DIVIDER_20 (0x00100000U)

LCD frequency = CLKPS/20

Definition at line 159 of file stm32wbxx_hal_lcd.h.

#define LCD_DIVIDER_21 (0x00140000U)

LCD frequency = CLKPS/21

Definition at line 160 of file stm32wbxx_hal_lcd.h.

#define LCD_DIVIDER_22 (0x00180000U)

LCD frequency = CLKPS/22

Definition at line 161 of file stm32wbxx_hal_lcd.h.

#define LCD_DIVIDER_23 (0x001C0000U)

LCD frequency = CLKPS/23

Definition at line 162 of file stm32wbxx_hal_lcd.h.

#define LCD_DIVIDER_24 (0x00200000U)

LCD frequency = CLKPS/24

Definition at line 163 of file stm32wbxx_hal_lcd.h.

#define LCD_DIVIDER_25 (0x00240000U)

LCD frequency = CLKPS/25

Definition at line 164 of file stm32wbxx_hal_lcd.h.

#define LCD_DIVIDER_26 (0x00280000U)

LCD frequency = CLKPS/26

Definition at line 165 of file stm32wbxx_hal_lcd.h.

#define LCD_DIVIDER_27 (0x002C0000U)

LCD frequency = CLKPS/27

Definition at line 166 of file stm32wbxx_hal_lcd.h.

#define LCD_DIVIDER_28 (0x00300000U)

LCD frequency = CLKPS/28

Definition at line 167 of file stm32wbxx_hal_lcd.h.

#define LCD_DIVIDER_29 (0x00340000U)

LCD frequency = CLKPS/29

Definition at line 168 of file stm32wbxx_hal_lcd.h.

#define LCD_DIVIDER_30 (0x00380000U)

LCD frequency = CLKPS/30

Definition at line 169 of file stm32wbxx_hal_lcd.h.

#define LCD_DIVIDER_31 (0x003C0000U)

LCD frequency = CLKPS/31

Definition at line 170 of file stm32wbxx_hal_lcd.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LCD Duty

Defines
LCD Duty
LCD Exported Constants

Defines

#define | LCD_DUTY_STATIC (0x00000000U)
#define | LCD_DUTY_1_2 (LCD_CR_DUTY_0)
#define | LCD_DUTY_1_3 (LCD_CR_DUTY_1)
#define | LCD_DUTY_1_4 ((LCD_CR_DUTY_1 | LCD_CR_DUTY_0))
#define | LCD_DUTY_1_8 (LCD_CR_DUTY_2)

Define Documentation

#define LCD_DUTY_1_2 (LCD_CR_DUTY_0)

1/2 duty

Definition at line 180 of file stm32wbxx_hal_lcd.h.

#define LCD_DUTY_1_3 (LCD_CR_DUTY_1)

1/3 duty

Definition at line 181 of file stm32wbxx_hal_lcd.h.

#define LCD_DUTY_1_4 ((LCD_CR_DUTY_1 | LCD_CR_DUTY_0))

1/4 duty

Definition at line 182 of file stm32wbxx_hal_lcd.h.

#define LCD_DUTY_1_8 (LCD_CR_DUTY_2)

1/8 duty

Definition at line 183 of file stm32wbxx_hal_lcd.h.

#define LCD_DUTY_STATIC (0x00000000U)

Static duty

Definition at line 179 of file stm32wbxx_hal_lcd.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LCD Bias

Defines
LCD Bias
LCD Exported Constants

Defines

#define | LCD_BIAS_1_4 (0x00000000U)
#define | LCD_BIAS_1_2 LCD_CR_BIAS_0
#define | LCD_BIAS_1_3 LCD_CR_BIAS_1

Define Documentation

#define LCD_BIAS_1_2 LCD_CR_BIAS_0

1/2 Bias

Definition at line 193 of file stm32wbxx_hal_lcd.h.

#define LCD_BIAS_1_3 LCD_CR_BIAS_1

1/3 Bias

Definition at line 194 of file stm32wbxx_hal_lcd.h.

#define LCD_BIAS_1_4 (0x00000000U)

1/4 Bias

Definition at line 192 of file stm32wbxx_hal_lcd.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LCD Voltage Source

Defines
LCD Voltage Source
LCD Exported Constants

Defines

#define | LCD_VOLTAGESOURCE_INTERNAL (0x00000000U)
#define | LCD_VOLTAGESOURCE_EXTERNAL LCD_CR_VSEL

Define Documentation

#define LCD_VOLTAGESOURCE_EXTERNAL LCD_CR_VSEL

External voltage source for the LCD

Definition at line 203 of file stm32wbxx_hal_lcd.h.

#define LCD_VOLTAGESOURCE_INTERNAL (0x00000000U)

Internal voltage source for the LCD

Definition at line 202 of file stm32wbxx_hal_lcd.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LCD Interrupts

Defines
LCD Interrupts
LCD Exported Constants

Defines

#define | LCD_IT_SOF LCD_FCR_SOFIE
#define | LCD_IT_UDD LCD_FCR_UDDIE

Define Documentation

#define LCD_IT_SOF LCD_FCR_SOFIE

Definition at line 211 of file stm32wbxx_hal_lcd.h.

#define LCD_IT_UDD LCD_FCR_UDDIE

Definition at line 212 of file stm32wbxx_hal_lcd.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LCD Pulse On Duration

Defines
LCD Pulse On Duration
LCD Exported Constants

Defines

#define | LCD_PULSEONDURATION_0 (0x00000000U)
#define | LCD_PULSEONDURATION_1 (LCD_FCR_PON_0)
#define | LCD_PULSEONDURATION_2 (LCD_FCR_PON_1)
#define | LCD_PULSEONDURATION_3 (LCD_FCR_PON_1 | LCD_FCR_PON_0)
#define | LCD_PULSEONDURATION_4 (LCD_FCR_PON_2)
#define | LCD_PULSEONDURATION_5 (LCD_FCR_PON_2 | LCD_FCR_PON_0)
#define | LCD_PULSEONDURATION_6 (LCD_FCR_PON_2 | LCD_FCR_PON_1)
#define | LCD_PULSEONDURATION_7 (LCD_FCR_PON)

Define Documentation

#define LCD_PULSEONDURATION_0 (0x00000000U)

Pulse ON duration = 0 pulse

Definition at line 220 of file stm32wbxx_hal_lcd.h.

#define LCD_PULSEONDURATION_1 (LCD_FCR_PON_0)

Pulse ON duration = 1/CK_PS

Definition at line 221 of file stm32wbxx_hal_lcd.h.

#define LCD_PULSEONDURATION_2 (LCD_FCR_PON_1)

Pulse ON duration = 2/CK_PS

Definition at line 222 of file stm32wbxx_hal_lcd.h.

#define LCD_PULSEONDURATION_3 (LCD_FCR_PON_1 | LCD_FCR_PON_0)

Pulse ON duration = 3/CK_PS

Definition at line 223 of file stm32wbxx_hal_lcd.h.

#define LCD_PULSEONDURATION_4 (LCD_FCR_PON_2)

Pulse ON duration = 4/CK_PS

Definition at line 224 of file stm32wbxx_hal_lcd.h.

#define LCD_PULSEONDURATION_5 (LCD_FCR_PON_2 | LCD_FCR_PON_0)

Pulse ON duration = 5/CK_PS

Definition at line 225 of file stm32wbxx_hal_lcd.h.

#define LCD_PULSEONDURATION_6 (LCD_FCR_PON_2 | LCD_FCR_PON_1)

Pulse ON duration = 6/CK_PS

Definition at line 226 of file stm32wbxx_hal_lcd.h.

#define LCD_PULSEONDURATION_7 (LCD_FCR_PON)

Pulse ON duration = 7/CK_PS

Definition at line 227 of file stm32wbxx_hal_lcd.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LCD Dead Time

Defines
LCD Dead Time
LCD Exported Constants

Defines

#define | LCD_DEADTIME_0 (0x00000000U)
#define | LCD_DEADTIME_1 (LCD_FCR_DEAD_0)
#define | LCD_DEADTIME_2 (LCD_FCR_DEAD_1)
#define | LCD_DEADTIME_3 (LCD_FCR_DEAD_1 | LCD_FCR_DEAD_0)
#define | LCD_DEADTIME_4 (LCD_FCR_DEAD_2)
#define | LCD_DEADTIME_5 (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_0)
#define | LCD_DEADTIME_6 (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_1)
#define | LCD_DEADTIME_7 (LCD_FCR_DEAD)

Define Documentation

#define LCD_DEADTIME_0 (0x00000000U)

No dead Time

Definition at line 236 of file stm32wbxx_hal_lcd.h.

#define LCD_DEADTIME_1 (LCD_FCR_DEAD_0)

One Phase between different couple of Frame

Definition at line 237 of file stm32wbxx_hal_lcd.h.

#define LCD_DEADTIME_2 (LCD_FCR_DEAD_1)

Two Phase between different couple of Frame

Definition at line 238 of file stm32wbxx_hal_lcd.h.

#define LCD_DEADTIME_3 (LCD_FCR_DEAD_1 | LCD_FCR_DEAD_0)

Three Phase between different couple of Frame

Definition at line 239 of file stm32wbxx_hal_lcd.h.

#define LCD_DEADTIME_4 (LCD_FCR_DEAD_2)

Four Phase between different couple of Frame

Definition at line 240 of file stm32wbxx_hal_lcd.h.

#define LCD_DEADTIME_5 (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_0)

Five Phase between different couple of Frame

Definition at line 241 of file stm32wbxx_hal_lcd.h.

#define LCD_DEADTIME_6 (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_1)

Six Phase between different couple of Frame

Definition at line 242 of file stm32wbxx_hal_lcd.h.

#define LCD_DEADTIME_7 (LCD_FCR_DEAD)

Seven Phase between different couple of Frame

Definition at line 243 of file stm32wbxx_hal_lcd.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LCD Blink Mode

Defines
LCD Blink Mode
LCD Exported Constants

Defines

#define | LCD_BLINKMODE_OFF (0x00000000U)
#define | LCD_BLINKMODE_SEG0_COM0 (LCD_FCR_BLINK_0)
#define | LCD_BLINKMODE_SEG0_ALLCOM (LCD_FCR_BLINK_1)
#define | LCD_BLINKMODE_ALLSEG_ALLCOM (LCD_FCR_BLINK)

Define Documentation

#define LCD_BLINKMODE_ALLSEG_ALLCOM (LCD_FCR_BLINK)

Blink enabled on all SEG and all COM (all pixels)

Definition at line 255 of file stm32wbxx_hal_lcd.h.

#define LCD_BLINKMODE_OFF (0x00000000U)

Blink disabled

Definition at line 251 of file stm32wbxx_hal_lcd.h.

#define LCD_BLINKMODE_SEG0_ALLCOM (LCD_FCR_BLINK_1)

Blink enabled on SEG[0], all COM (up to 8 pixels according to the programmed duty)

Definition at line 253 of file stm32wbxx_hal_lcd.h.

#define LCD_BLINKMODE_SEG0_COM0 (LCD_FCR_BLINK_0)

Blink enabled on SEG[0], COM[0] (1 pixel)

Definition at line 252 of file stm32wbxx_hal_lcd.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LCD Blink Frequency

Defines
LCD Blink Frequency
LCD Exported Constants

Defines

#define | LCD_BLINKFREQUENCY_DIV8 (0x00000000U)
#define | LCD_BLINKFREQUENCY_DIV16 (LCD_FCR_BLINKF_0)
#define | LCD_BLINKFREQUENCY_DIV32 (LCD_FCR_BLINKF_1)
#define | LCD_BLINKFREQUENCY_DIV64 (LCD_FCR_BLINKF_1 | LCD_FCR_BLINKF_0)
#define | LCD_BLINKFREQUENCY_DIV128 (LCD_FCR_BLINKF_2)
#define | LCD_BLINKFREQUENCY_DIV256 (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_0)
#define | LCD_BLINKFREQUENCY_DIV512 (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_1)
#define | LCD_BLINKFREQUENCY_DIV1024 (LCD_FCR_BLINKF)

Define Documentation

#define LCD_BLINKFREQUENCY_DIV1024 (LCD_FCR_BLINKF)

The Blink frequency = fLCD/1024

Definition at line 270 of file stm32wbxx_hal_lcd.h.

#define LCD_BLINKFREQUENCY_DIV128 (LCD_FCR_BLINKF_2)

The Blink frequency = fLCD/128

Definition at line 267 of file stm32wbxx_hal_lcd.h.

#define LCD_BLINKFREQUENCY_DIV16 (LCD_FCR_BLINKF_0)

The Blink frequency = fLCD/16

Definition at line 264 of file stm32wbxx_hal_lcd.h.

#define LCD_BLINKFREQUENCY_DIV256 (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_0)

The Blink frequency = fLCD/256

Definition at line 268 of file stm32wbxx_hal_lcd.h.

#define LCD_BLINKFREQUENCY_DIV32 (LCD_FCR_BLINKF_1)

The Blink frequency = fLCD/32

Definition at line 265 of file stm32wbxx_hal_lcd.h.

#define LCD_BLINKFREQUENCY_DIV512 (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_1)

The Blink frequency = fLCD/512

Definition at line 269 of file stm32wbxx_hal_lcd.h.

#define LCD_BLINKFREQUENCY_DIV64 (LCD_FCR_BLINKF_1 | LCD_FCR_BLINKF_0)

The Blink frequency = fLCD/64

Definition at line 266 of file stm32wbxx_hal_lcd.h.

#define LCD_BLINKFREQUENCY_DIV8 (0x00000000U)

The Blink frequency = fLCD/8

Definition at line 263 of file stm32wbxx_hal_lcd.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LCD Contrast

Defines
LCD Contrast
LCD Exported Constants

Defines

#define | LCD_CONTRASTLEVEL_0 (0x00000000U)
#define | LCD_CONTRASTLEVEL_1 (LCD_FCR_CC_0)
#define | LCD_CONTRASTLEVEL_2 (LCD_FCR_CC_1)
#define | LCD_CONTRASTLEVEL_3 (LCD_FCR_CC_1 | LCD_FCR_CC_0)
#define | LCD_CONTRASTLEVEL_4 (LCD_FCR_CC_2)
#define | LCD_CONTRASTLEVEL_5 (LCD_FCR_CC_2 | LCD_FCR_CC_0)
#define | LCD_CONTRASTLEVEL_6 (LCD_FCR_CC_2 | LCD_FCR_CC_1)
#define | LCD_CONTRASTLEVEL_7 (LCD_FCR_CC)

Define Documentation

#define LCD_CONTRASTLEVEL_0 (0x00000000U)

Maximum Voltage = 2.60V

Definition at line 278 of file stm32wbxx_hal_lcd.h.

#define LCD_CONTRASTLEVEL_1 (LCD_FCR_CC_0)

Maximum Voltage = 2.73V

Definition at line 279 of file stm32wbxx_hal_lcd.h.

#define LCD_CONTRASTLEVEL_2 (LCD_FCR_CC_1)

Maximum Voltage = 2.86V

Definition at line 280 of file stm32wbxx_hal_lcd.h.

#define LCD_CONTRASTLEVEL_3 (LCD_FCR_CC_1 | LCD_FCR_CC_0)

Maximum Voltage = 2.99V

Definition at line 281 of file stm32wbxx_hal_lcd.h.

#define LCD_CONTRASTLEVEL_4 (LCD_FCR_CC_2)

Maximum Voltage = 3.12V

Definition at line 282 of file stm32wbxx_hal_lcd.h.

#define LCD_CONTRASTLEVEL_5 (LCD_FCR_CC_2 | LCD_FCR_CC_0)

Maximum Voltage = 3.26V

Definition at line 283 of file stm32wbxx_hal_lcd.h.

#define LCD_CONTRASTLEVEL_6 (LCD_FCR_CC_2 | LCD_FCR_CC_1)

Maximum Voltage = 3.40V

Definition at line 284 of file stm32wbxx_hal_lcd.h.

#define LCD_CONTRASTLEVEL_7 (LCD_FCR_CC)

Maximum Voltage = 3.55V

Definition at line 285 of file stm32wbxx_hal_lcd.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LCD RAMRegister

Defines
LCD RAMRegister
LCD Exported Constants

Defines

#define | LCD_RAM_REGISTER0 (0x00000000U)
#define | LCD_RAM_REGISTER1 (0x00000001U)
#define | LCD_RAM_REGISTER2 (0x00000002U)
#define | LCD_RAM_REGISTER3 (0x00000003U)
#define | LCD_RAM_REGISTER4 (0x00000004U)
#define | LCD_RAM_REGISTER5 (0x00000005U)
#define | LCD_RAM_REGISTER6 (0x00000006U)
#define | LCD_RAM_REGISTER7 (0x00000007U)
#define | LCD_RAM_REGISTER8 (0x00000008U)
#define | LCD_RAM_REGISTER9 (0x00000009U)
#define | LCD_RAM_REGISTER10 (0x0000000AU)
#define | LCD_RAM_REGISTER11 (0x0000000BU)
#define | LCD_RAM_REGISTER12 (0x0000000CU)
#define | LCD_RAM_REGISTER13 (0x0000000DU)
#define | LCD_RAM_REGISTER14 (0x0000000EU)
#define | LCD_RAM_REGISTER15 (0x0000000FU)

Define Documentation

#define LCD_RAM_REGISTER0 (0x00000000U)

LCD RAM Register 0

Definition at line 293 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Clear(), and HAL_LCD_Init().

#define LCD_RAM_REGISTER1 (0x00000001U)

LCD RAM Register 1

Definition at line 294 of file stm32wbxx_hal_lcd.h.

#define LCD_RAM_REGISTER10 (0x0000000AU)

LCD RAM Register 10

Definition at line 303 of file stm32wbxx_hal_lcd.h.

#define LCD_RAM_REGISTER11 (0x0000000BU)

LCD RAM Register 11

Definition at line 304 of file stm32wbxx_hal_lcd.h.

#define LCD_RAM_REGISTER12 (0x0000000CU)

LCD RAM Register 12

Definition at line 305 of file stm32wbxx_hal_lcd.h.

#define LCD_RAM_REGISTER13 (0x0000000DU)

LCD RAM Register 13

Definition at line 306 of file stm32wbxx_hal_lcd.h.

#define LCD_RAM_REGISTER14 (0x0000000EU)

LCD RAM Register 14

Definition at line 307 of file stm32wbxx_hal_lcd.h.

#define LCD_RAM_REGISTER15 (0x0000000FU)

LCD RAM Register 15

Definition at line 308 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Clear().

#define LCD_RAM_REGISTER2 (0x00000002U)

LCD RAM Register 2

Definition at line 295 of file stm32wbxx_hal_lcd.h.

#define LCD_RAM_REGISTER3 (0x00000003U)

LCD RAM Register 3

Definition at line 296 of file stm32wbxx_hal_lcd.h.

#define LCD_RAM_REGISTER4 (0x00000004U)

LCD RAM Register 4

Definition at line 297 of file stm32wbxx_hal_lcd.h.

#define LCD_RAM_REGISTER5 (0x00000005U)

LCD RAM Register 5

Definition at line 298 of file stm32wbxx_hal_lcd.h.

#define LCD_RAM_REGISTER6 (0x00000006U)

LCD RAM Register 6

Definition at line 299 of file stm32wbxx_hal_lcd.h.

#define LCD_RAM_REGISTER7 (0x00000007U)

LCD RAM Register 7

Definition at line 300 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Init().

#define LCD_RAM_REGISTER8 (0x00000008U)

LCD RAM Register 8

Definition at line 301 of file stm32wbxx_hal_lcd.h.

#define LCD_RAM_REGISTER9 (0x00000009U)

LCD RAM Register 9

Definition at line 302 of file stm32wbxx_hal_lcd.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LCD High Drive

Defines
LCD High Drive
LCD Exported Constants

Defines

#define | LCD_HIGHDRIVE_DISABLE ((uint32_t)0x00000000)
#define | LCD_HIGHDRIVE_ENABLE (LCD_FCR_HD)

Define Documentation

#define LCD_HIGHDRIVE_DISABLE ((uint32_t)0x00000000)

High drive disabled

Definition at line 317 of file stm32wbxx_hal_lcd.h.

#define LCD_HIGHDRIVE_ENABLE (LCD_FCR_HD)

High drive enabled

Definition at line 318 of file stm32wbxx_hal_lcd.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LCD Mux Segment

Defines
LCD Mux Segment
LCD Exported Constants

Defines

#define | LCD_MUXSEGMENT_DISABLE (0x00000000U)
#define | LCD_MUXSEGMENT_ENABLE (LCD_CR_MUX_SEG)

Define Documentation

#define LCD_MUXSEGMENT_DISABLE (0x00000000U)

SEG pin multiplexing disabled

Definition at line 327 of file stm32wbxx_hal_lcd.h.

#define LCD_MUXSEGMENT_ENABLE (LCD_CR_MUX_SEG)

SEG[31:28] are multiplexed with SEG[43:40]

Definition at line 328 of file stm32wbxx_hal_lcd.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LCD Flags Definition

Defines
LCD Flags Definition
LCD Exported Constants

Defines

#define | LCD_FLAG_ENS LCD_SR_ENS
#define | LCD_FLAG_SOF LCD_SR_SOF
#define | LCD_FLAG_UDR LCD_SR_UDR
#define | LCD_FLAG_UDD LCD_SR_UDD
#define | LCD_FLAG_RDY LCD_SR_RDY
#define | LCD_FLAG_FCRSF LCD_SR_FCRSR

Define Documentation

#define LCD_FLAG_ENS LCD_SR_ENS

LCD enabled status

Definition at line 336 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Init().

#define LCD_FLAG_FCRSF LCD_SR_FCRSR

LCD Frame Control Register Synchronization flag

Definition at line 341 of file stm32wbxx_hal_lcd.h.

Referenced by LCD_WaitForSynchro().

#define LCD_FLAG_RDY LCD_SR_RDY

Ready flag

Definition at line 340 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Init().

#define LCD_FLAG_SOF LCD_SR_SOF

Start of frame flag

Definition at line 337 of file stm32wbxx_hal_lcd.h.

#define LCD_FLAG_UDD LCD_SR_UDD

Update display done

Definition at line 339 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_UpdateDisplayRequest().

#define LCD_FLAG_UDR LCD_SR_UDR

Update display request

Definition at line 338 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Clear(), and HAL_LCD_Write().

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LCD Exported Macros

Defines
LCD Exported Macros
LCD

Defines

#define | __HAL_LCD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LCD_STATE_RESET)
Reset LCD handle state.
#define | __HAL_LCD_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN)
Enable the LCD peripheral.
#define | __HAL_LCD_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN)
Disable the LCD peripheral.
#define | __HAL_LCD_HIGHDRIVER_ENABLE(__HANDLE__)
Enable the low resistance divider.
#define | __HAL_LCD_HIGHDRIVER_DISABLE(__HANDLE__)
Disable the low resistance divider.
#define | __HAL_LCD_VOLTAGE_BUFFER_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_BUFEN)
Enable the voltage output buffer for higher driving capability.
#define | __HAL_LCD_VOLTAGE_BUFFER_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_BUFEN)
Disable the voltage output buffer for higher driving capability.
#define | __HAL_LCD_PULSEONDURATION_CONFIG(__HANDLE__, __DURATION__)
Configure the LCD pulse on duration.
#define | __HAL_LCD_DEADTIME_CONFIG(__HANDLE__, __DEADTIME__)
Configure the LCD dead time.
#define | __HAL_LCD_CONTRAST_CONFIG(__HANDLE__, __CONTRAST__)
Configure the LCD contrast.
#define | __HAL_LCD_BLINK_CONFIG(__HANDLE__, __BLINKMODE__, __BLINKFREQUENCY__)
Configure the LCD Blink mode and Blink frequency.
#define | __HAL_LCD_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified LCD interrupt.
#define | __HAL_LCD_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified LCD interrupt.
#define | __HAL_LCD_GET_IT_SOURCE(__HANDLE__, __IT__) (((__HANDLE__)->Instance->FCR) & (__IT__))
Check whether the specified LCD interrupt source is enabled or not.
#define | __HAL_LCD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check whether the specified LCD flag is set or not.
#define | __HAL_LCD_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->CLR, (__FLAG__))
Clear the specified LCD pending flag.

Define Documentation

#define __HAL_LCD_BLINK_CONFIG | ( | __HANDLE__,
 |  | __BLINKMODE__,
 |  | __BLINKFREQUENCY__
 | ) |
Value:
do {                                                                    \
                MODIFY_REG((__HANDLE__)->Instance->FCR, (LCD_FCR_BLINKF | LCD_FCR_BLINK), ((__BLINKMODE__) | (__BLINKFREQUENCY__))); \
                LCD_WaitForSynchro(__HANDLE__);                                       \
              } while(0)

Configure the LCD Blink mode and Blink frequency.

Parameters:
__HANDLE__ specifies the LCD Handle.
__BLINKMODE__ specifies the LCD blink mode. This parameter can be one of the following values:
  • LCD_BLINKMODE_OFF: Blink disabled
  • LCD_BLINKMODE_SEG0_COM0: Blink enabled on SEG[0], COM[0] (1 pixel)
  • LCD_BLINKMODE_SEG0_ALLCOM: Blink enabled on SEG[0], all COM (up to 8 pixels according to the programmed duty)
  • LCD_BLINKMODE_ALLSEG_ALLCOM: Blink enabled on all SEG and all COM (all pixels)
__BLINKFREQUENCY__ specifies the LCD blink frequency.
  • LCD_BLINKFREQUENCY_DIV8: The Blink frequency = fLcd/8
  • LCD_BLINKFREQUENCY_DIV16: The Blink frequency = fLcd/16
  • LCD_BLINKFREQUENCY_DIV32: The Blink frequency = fLcd/32
  • LCD_BLINKFREQUENCY_DIV64: The Blink frequency = fLcd/64
  • LCD_BLINKFREQUENCY_DIV128: The Blink frequency = fLcd/128
  • LCD_BLINKFREQUENCY_DIV256: The Blink frequency = fLcd/256
  • LCD_BLINKFREQUENCY_DIV512: The Blink frequency = fLcd/512
  • LCD_BLINKFREQUENCY_DIV1024: The Blink frequency = fLcd/1024
Return values:
None

Definition at line 496 of file stm32wbxx_hal_lcd.h.

#define __HAL_LCD_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | WRITE_REG((__HANDLE__)->Instance->CLR, (__FLAG__))

Clear the specified LCD pending flag.

Parameters:
__HANDLE__ specifies the LCD Handle.
__FLAG__ specifies the flag to clear. This parameter can be any combination of the following values:
  • LCD_FLAG_SOF: Start of Frame Interrupt
  • LCD_FLAG_UDD: Update Display Done Interrupt
Return values:
None

Definition at line 573 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_UpdateDisplayRequest().

#define __HAL_LCD_CONTRAST_CONFIG | ( | __HANDLE__,
 |  | __CONTRAST__
 | ) |
Value:
do {                                                                    \
                MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_CC, (__CONTRAST__));  \
                LCD_WaitForSynchro(__HANDLE__);                                       \
              } while(0)

Configure the LCD contrast.

Parameters:
__HANDLE__ specifies the LCD Handle.
__CONTRAST__ specifies the LCD Contrast. This parameter can be one of the following values:
  • LCD_CONTRASTLEVEL_0: Maximum Voltage = 2.60V
  • LCD_CONTRASTLEVEL_1: Maximum Voltage = 2.73V
  • LCD_CONTRASTLEVEL_2: Maximum Voltage = 2.86V
  • LCD_CONTRASTLEVEL_3: Maximum Voltage = 2.99V
  • LCD_CONTRASTLEVEL_4: Maximum Voltage = 3.12V
  • LCD_CONTRASTLEVEL_5: Maximum Voltage = 3.25V
  • LCD_CONTRASTLEVEL_6: Maximum Voltage = 3.38V
  • LCD_CONTRASTLEVEL_7: Maximum Voltage = 3.51V
Return values:
None

Definition at line 468 of file stm32wbxx_hal_lcd.h.

#define __HAL_LCD_DEADTIME_CONFIG | ( | __HANDLE__,
 |  | __DEADTIME__
 | ) |
Value:
do {                                                                     \
                    MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_DEAD, (__DEADTIME__)); \
                    LCD_WaitForSynchro(__HANDLE__);                                        \
                  } while(0)

Configure the LCD dead time.

Parameters:
__HANDLE__ specifies the LCD Handle.
__DEADTIME__ specifies the LCD dead time. This parameter can be one of the following values:
  • LCD_DEADTIME_0: No dead Time
  • LCD_DEADTIME_1: One Phase between different couple of Frame
  • LCD_DEADTIME_2: Two Phase between different couple of Frame
  • LCD_DEADTIME_3: Three Phase between different couple of Frame
  • LCD_DEADTIME_4: Four Phase between different couple of Frame
  • LCD_DEADTIME_5: Five Phase between different couple of Frame
  • LCD_DEADTIME_6: Six Phase between different couple of Frame
  • LCD_DEADTIME_7: Seven Phase between different couple of Frame
Return values:
None

Definition at line 447 of file stm32wbxx_hal_lcd.h.

#define __HAL_LCD_DISABLE ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN)

Disable the LCD peripheral.

Parameters:
__HANDLE__ specifies the LCD Handle.
Return values:
None

Definition at line 371 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Init().

#define __HAL_LCD_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
do {                                                       \
                    CLEAR_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__)); \
                    LCD_WaitForSynchro(__HANDLE__);                          \
                  } while(0)

Disable the specified LCD interrupt.

Parameters:
__HANDLE__ specifies the LCD Handle.
__INTERRUPT__ specifies the LCD interrupt source to be disabled. This parameter can be one of the following values:
  • LCD_IT_SOF: Start of Frame Interrupt
  • LCD_IT_UDD: Update Display Done Interrupt
Return values:
None

Definition at line 524 of file stm32wbxx_hal_lcd.h.

#define __HAL_LCD_ENABLE ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN)

Enable the LCD peripheral.

Parameters:
__HANDLE__ specifies the LCD Handle.
Return values:
None

Definition at line 365 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Init().

#define __HAL_LCD_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
do {                                                      \
                    SET_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__));  \
                    LCD_WaitForSynchro(__HANDLE__);                         \
                  } while(0)

Enable the specified LCD interrupt.

Parameters:
__HANDLE__ specifies the LCD Handle.
__INTERRUPT__ specifies the LCD interrupt source to be enabled. This parameter can be one of the following values:
  • LCD_IT_SOF: Start of Frame Interrupt
  • LCD_IT_UDD: Update Display Done Interrupt
Return values:
None

Definition at line 510 of file stm32wbxx_hal_lcd.h.

#define __HAL_LCD_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))

Check whether the specified LCD flag is set or not.

Parameters:
__HANDLE__ specifies the LCD Handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • LCD_FLAG_ENS: LCD Enabled flag. It indicates the LCD controller status.
Note:
The ENS bit is set immediately when the LCDEN bit in the LCD_CR goes from 0 to 1. On deactivation it reflects the real status of LCD so it becomes 0 at the end of the last displayed frame.
  • LCD_FLAG_SOF: Start of Frame flag. This flag is set by hardware at the beginning of a new frame, at the same time as the display data is updated.
  • LCD_FLAG_UDR: Update Display Request flag.
  • LCD_FLAG_UDD: Update Display Done flag.
  • LCD_FLAG_RDY: Step_up converter Ready flag. It indicates the status of the step-up converter.
  • LCD_FLAG_FCRSF: LCD Frame Control Register Synchronization Flag. This flag is set by hardware each time the LCD_FCR register is updated in the LCDCLK domain.
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 563 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Clear(), HAL_LCD_Init(), HAL_LCD_UpdateDisplayRequest(), HAL_LCD_Write(), and LCD_WaitForSynchro().

#define __HAL_LCD_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __IT__
 | ) | (((__HANDLE__)->Instance->FCR) & (__IT__))

Check whether the specified LCD interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the LCD Handle.
__IT__ specifies the LCD interrupt source to check. This parameter can be one of the following values:
  • LCD_IT_SOF: Start of Frame Interrupt
  • LCD_IT_UDD: Update Display Done Interrupt.
Note:
If the device is in STOP mode (PCLK not provided) UDD will not generate an interrupt even if UDDIE = 1. If the display is not enabled the UDD interrupt will never occur.
Return values:
The state of __IT__ (TRUE or FALSE).

Definition at line 541 of file stm32wbxx_hal_lcd.h.

#define __HAL_LCD_HIGHDRIVER_DISABLE ( __HANDLE__ )
Value:
do {                                                  \
                    CLEAR_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
                    LCD_WaitForSynchro(__HANDLE__);                     \
                  } while(0)

Disable the low resistance divider.

Parameters:
__HANDLE__ specifies the LCD Handle.
Return values:
None

Definition at line 392 of file stm32wbxx_hal_lcd.h.

#define __HAL_LCD_HIGHDRIVER_ENABLE ( __HANDLE__ )
Value:
do {                                                \
                    SET_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
                    LCD_WaitForSynchro(__HANDLE__);                   \
                  } while(0)

Enable the low resistance divider.

Parameters:
__HANDLE__ specifies the LCD Handle.
Note:
Displays with high internal resistance may need a longer drive time to achieve satisfactory contrast. This function is useful in this case if some additional power consumption can be tolerated.
When this mode is enabled, the PulseOn Duration (PON) have to be programmed to 1/CK_PS (LCD_PULSEONDURATION_1).
Return values:
None

Definition at line 382 of file stm32wbxx_hal_lcd.h.

#define __HAL_LCD_PULSEONDURATION_CONFIG | ( | __HANDLE__,
 |  | __DURATION__
 | ) |
Value:
do {                                                                    \
                    MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_PON, (__DURATION__)); \
                    LCD_WaitForSynchro(__HANDLE__);                                       \
                  } while(0)

Configure the LCD pulse on duration.

Parameters:
__HANDLE__ specifies the LCD Handle.
__DURATION__ specifies the LCD pulse on duration in terms of CK_PS (prescaled LCD clock period) pulses. This parameter can be one of the following values:
  • LCD_PULSEONDURATION_0: 0 pulse
  • LCD_PULSEONDURATION_1: Pulse ON duration = 1/CK_PS
  • LCD_PULSEONDURATION_2: Pulse ON duration = 2/CK_PS
  • LCD_PULSEONDURATION_3: Pulse ON duration = 3/CK_PS
  • LCD_PULSEONDURATION_4: Pulse ON duration = 4/CK_PS
  • LCD_PULSEONDURATION_5: Pulse ON duration = 5/CK_PS
  • LCD_PULSEONDURATION_6: Pulse ON duration = 6/CK_PS
  • LCD_PULSEONDURATION_7: Pulse ON duration = 7/CK_PS
Return values:
None

Definition at line 426 of file stm32wbxx_hal_lcd.h.

#define __HAL_LCD_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_LCD_STATE_RESET)

Reset LCD handle state.

Parameters:
__HANDLE__ specifies the LCD Handle.
Return values:
None

Definition at line 359 of file stm32wbxx_hal_lcd.h.

#define __HAL_LCD_VOLTAGE_BUFFER_DISABLE ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_BUFEN)

Disable the voltage output buffer for higher driving capability.

Parameters:
__HANDLE__ specifies the LCD Handle.
Return values:
None

Definition at line 408 of file stm32wbxx_hal_lcd.h.

#define __HAL_LCD_VOLTAGE_BUFFER_ENABLE ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_BUFEN)

Enable the voltage output buffer for higher driving capability.

Parameters:
__HANDLE__ specifies the LCD Handle.
Return values:
None

Definition at line 402 of file stm32wbxx_hal_lcd.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LCD Private Macros

Defines
LCD Private Macros
LCD

Defines

#define | IS_LCD_PRESCALER(__PRESCALER__)
#define | IS_LCD_DIVIDER(__DIVIDER__)
#define | IS_LCD_DUTY(__DUTY__)
#define | IS_LCD_BIAS(__BIAS__)
#define | IS_LCD_VOLTAGE_SOURCE(SOURCE)
#define | IS_LCD_PULSE_ON_DURATION(__DURATION__)
#define | IS_LCD_DEAD_TIME(__TIME__)
#define | IS_LCD_BLINK_MODE(__MODE__)
#define | IS_LCD_BLINK_FREQUENCY(__FREQUENCY__)
#define | IS_LCD_CONTRAST(__CONTRAST__)
#define | IS_LCD_RAM_REGISTER(__REGISTER__)
#define | IS_LCD_HIGH_DRIVE(__VALUE__)
#define | IS_LCD_MUX_SEGMENT(__VALUE__)

Define Documentation

#define IS_LCD_BIAS ( __BIAS__ )
Value:
(((__BIAS__) == LCD_BIAS_1_4) || \
                               ((__BIAS__) == LCD_BIAS_1_2) || \
                               ((__BIAS__) == LCD_BIAS_1_3))

Definition at line 669 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Init().

#define IS_LCD_BLINK_FREQUENCY ( __FREQUENCY__ )
Value:
(((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV8)   || \
                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV16)  || \
                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV32)  || \
                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV64)  || \
                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV128) || \
                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV256) || \
                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV512) || \
                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV1024))

Definition at line 700 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Init().

#define IS_LCD_BLINK_MODE ( __MODE__ )
Value:
(((__MODE__) == LCD_BLINKMODE_OFF)            || \
                                     ((__MODE__) == LCD_BLINKMODE_SEG0_COM0)      || \
                                     ((__MODE__) == LCD_BLINKMODE_SEG0_ALLCOM)    || \
                                     ((__MODE__) == LCD_BLINKMODE_ALLSEG_ALLCOM))

Definition at line 695 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Init().

#define IS_LCD_CONTRAST ( __CONTRAST__ )
Value:
(((__CONTRAST__) == LCD_CONTRASTLEVEL_0) || \
                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_1) || \
                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_2) || \
                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_3) || \
                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_4) || \
                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_5) || \
                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_6) || \
                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_7))

Definition at line 709 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Init().

#define IS_LCD_DEAD_TIME ( __TIME__ )
Value:
(((__TIME__) == LCD_DEADTIME_0) || \
                                    ((__TIME__) == LCD_DEADTIME_1) || \
                                    ((__TIME__) == LCD_DEADTIME_2) || \
                                    ((__TIME__) == LCD_DEADTIME_3) || \
                                    ((__TIME__) == LCD_DEADTIME_4) || \
                                    ((__TIME__) == LCD_DEADTIME_5) || \
                                    ((__TIME__) == LCD_DEADTIME_6) || \
                                    ((__TIME__) == LCD_DEADTIME_7))

Definition at line 686 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Init().

#define IS_LCD_DIVIDER ( __DIVIDER__ )
Value:
(((__DIVIDER__) == LCD_DIVIDER_16) || \
                                     ((__DIVIDER__) == LCD_DIVIDER_17) || \
                                     ((__DIVIDER__) == LCD_DIVIDER_18) || \
                                     ((__DIVIDER__) == LCD_DIVIDER_19) || \
                                     ((__DIVIDER__) == LCD_DIVIDER_20) || \
                                     ((__DIVIDER__) == LCD_DIVIDER_21) || \
                                     ((__DIVIDER__) == LCD_DIVIDER_22) || \
                                     ((__DIVIDER__) == LCD_DIVIDER_23) || \
                                     ((__DIVIDER__) == LCD_DIVIDER_24) || \
                                     ((__DIVIDER__) == LCD_DIVIDER_25) || \
                                     ((__DIVIDER__) == LCD_DIVIDER_26) || \
                                     ((__DIVIDER__) == LCD_DIVIDER_27) || \
                                     ((__DIVIDER__) == LCD_DIVIDER_28) || \
                                     ((__DIVIDER__) == LCD_DIVIDER_29) || \
                                     ((__DIVIDER__) == LCD_DIVIDER_30) || \
                                     ((__DIVIDER__) == LCD_DIVIDER_31))

Definition at line 646 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Init().

#define IS_LCD_DUTY ( __DUTY__ )
Value:
(((__DUTY__) == LCD_DUTY_STATIC)  || \
                               ((__DUTY__) == LCD_DUTY_1_2)     || \
                               ((__DUTY__) == LCD_DUTY_1_3)     || \
                               ((__DUTY__) == LCD_DUTY_1_4)     || \
                               ((__DUTY__) == LCD_DUTY_1_8))

Definition at line 663 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Init().

#define IS_LCD_HIGH_DRIVE ( __VALUE__ )
Value:
(((__VALUE__) == LCD_HIGHDRIVE_DISABLE) || \
                                      ((__VALUE__) == LCD_HIGHDRIVE_ENABLE))

Definition at line 735 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Init().

#define IS_LCD_MUX_SEGMENT ( __VALUE__ )
Value:
(((__VALUE__) == LCD_MUXSEGMENT_ENABLE) || \
                                       ((__VALUE__) == LCD_MUXSEGMENT_DISABLE))

Definition at line 738 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Init().

#define IS_LCD_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == LCD_PRESCALER_1)     || \
                                         ((__PRESCALER__) == LCD_PRESCALER_2)     || \
                                         ((__PRESCALER__) == LCD_PRESCALER_4)     || \
                                         ((__PRESCALER__) == LCD_PRESCALER_8)     || \
                                         ((__PRESCALER__) == LCD_PRESCALER_16)    || \
                                         ((__PRESCALER__) == LCD_PRESCALER_32)    || \
                                         ((__PRESCALER__) == LCD_PRESCALER_64)    || \
                                         ((__PRESCALER__) == LCD_PRESCALER_128)   || \
                                         ((__PRESCALER__) == LCD_PRESCALER_256)   || \
                                         ((__PRESCALER__) == LCD_PRESCALER_512)   || \
                                         ((__PRESCALER__) == LCD_PRESCALER_1024)  || \
                                         ((__PRESCALER__) == LCD_PRESCALER_2048)  || \
                                         ((__PRESCALER__) == LCD_PRESCALER_4096)  || \
                                         ((__PRESCALER__) == LCD_PRESCALER_8192)  || \
                                         ((__PRESCALER__) == LCD_PRESCALER_16384) || \
                                         ((__PRESCALER__) == LCD_PRESCALER_32768))

Definition at line 629 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Init().

#define IS_LCD_PULSE_ON_DURATION ( __DURATION__ )
Value:
(((__DURATION__) == LCD_PULSEONDURATION_0) || \
                                                ((__DURATION__) == LCD_PULSEONDURATION_1) || \
                                                ((__DURATION__) == LCD_PULSEONDURATION_2) || \
                                                ((__DURATION__) == LCD_PULSEONDURATION_3) || \
                                                ((__DURATION__) == LCD_PULSEONDURATION_4) || \
                                                ((__DURATION__) == LCD_PULSEONDURATION_5) || \
                                                ((__DURATION__) == LCD_PULSEONDURATION_6) || \
                                                ((__DURATION__) == LCD_PULSEONDURATION_7))

Definition at line 677 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Init().

#define IS_LCD_RAM_REGISTER ( __REGISTER__ )
Value:
(((__REGISTER__) == LCD_RAM_REGISTER0)  || \
                                           ((__REGISTER__) == LCD_RAM_REGISTER1)  || \
                                           ((__REGISTER__) == LCD_RAM_REGISTER2)  || \
                                           ((__REGISTER__) == LCD_RAM_REGISTER3)  || \
                                           ((__REGISTER__) == LCD_RAM_REGISTER4)  || \
                                           ((__REGISTER__) == LCD_RAM_REGISTER5)  || \
                                           ((__REGISTER__) == LCD_RAM_REGISTER6)  || \
                                           ((__REGISTER__) == LCD_RAM_REGISTER7)  || \
                                           ((__REGISTER__) == LCD_RAM_REGISTER8)  || \
                                           ((__REGISTER__) == LCD_RAM_REGISTER9)  || \
                                           ((__REGISTER__) == LCD_RAM_REGISTER10) || \
                                           ((__REGISTER__) == LCD_RAM_REGISTER11) || \
                                           ((__REGISTER__) == LCD_RAM_REGISTER12) || \
                                           ((__REGISTER__) == LCD_RAM_REGISTER13) || \
                                           ((__REGISTER__) == LCD_RAM_REGISTER14) || \
                                           ((__REGISTER__) == LCD_RAM_REGISTER15))

Definition at line 718 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Write().

#define IS_LCD_VOLTAGE_SOURCE ( SOURCE )
Value:
(((SOURCE) == LCD_VOLTAGESOURCE_INTERNAL) || \
                                       ((SOURCE) == LCD_VOLTAGESOURCE_EXTERNAL))

Definition at line 673 of file stm32wbxx_hal_lcd.h.

Referenced by HAL_LCD_Init().

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization/de-initialization functions

Functions
Initialization/de-initialization functions
LPTIM Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_LPTIM_Init (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_LPTIM_DeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize the LPTIM peripheral.
__weak void | HAL_LPTIM_MspInit (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM MSP.
__weak void | HAL_LPTIM_MspDeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize LPTIM MSP.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and de-initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the LPTIM according to the specified parameters in the
          LPTIM_InitTypeDef and initialize the associated handle.
      (+) DeInitialize the LPTIM peripheral.
      (+) Initialize the LPTIM MSP.
      (+) DeInitialize the LPTIM MSP.

Function Documentation

HAL_StatusTypeDef HAL_LPTIM_DeInit ( LPTIM_HandleTypeDef * hlptim )

DeInitialize the LPTIM peripheral.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 342 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, HAL_LPTIM_GetState(), HAL_LPTIM_MspDeInit(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_RESET, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::MspDeInitCallback, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Init ( LPTIM_HandleTypeDef * hlptim )

Initialize the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and initialize the associated handle.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 216 of file stm32wbxx_hal_lptim.c.

References LPTIM_TriggerConfigTypeDef::ActiveEdge, assert_param, LPTIM_InitTypeDef::Clock, LPTIM_InitTypeDef::CounterSource, HAL_LPTIM_MspInit(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_RESET, __LPTIM_HandleTypeDef::Init, LPTIM_InitTypeDef::Input1Source, LPTIM_InitTypeDef::Input2Source, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_POLARITY, IS_LPTIM_CLOCK_PRESCALER, IS_LPTIM_CLOCK_SAMPLE_TIME, IS_LPTIM_CLOCK_SOURCE, IS_LPTIM_COUNTER_SOURCE, IS_LPTIM_EXT_TRG_POLARITY, IS_LPTIM_INPUT1_SOURCE, IS_LPTIM_INPUT2_SOURCE, IS_LPTIM_OUTPUT_POLARITY, IS_LPTIM_TRG_SOURCE, IS_LPTIM_TRIG_SAMPLE_TIME, IS_LPTIM_UPDATE_MODE, __LPTIM_HandleTypeDef::Lock, LPTIM_CLOCKSOURCE_ULPTIM, LPTIM_COUNTERSOURCE_EXTERNAL, LPTIM_ResetCallback(), LPTIM_TRIGSOURCE_SOFTWARE, __LPTIM_HandleTypeDef::MspInitCallback, LPTIM_InitTypeDef::OutputPolarity, LPTIM_ULPClockConfigTypeDef::Polarity, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ULPClockConfigTypeDef::SampleTime, LPTIM_TriggerConfigTypeDef::SampleTime, LPTIM_ClockConfigTypeDef::Source, LPTIM_TriggerConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, LPTIM_InitTypeDef::Trigger, LPTIM_InitTypeDef::UltraLowPowerClock, and LPTIM_InitTypeDef::UpdateMode.

__weak void HAL_LPTIM_MspDeInit ( LPTIM_HandleTypeDef * hlptim )

DeInitialize LPTIM MSP.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 404 of file stm32wbxx_hal_lptim.c.

Referenced by HAL_LPTIM_DeInit(), and HAL_LPTIM_UnRegisterCallback().

__weak void HAL_LPTIM_MspInit ( LPTIM_HandleTypeDef * hlptim )

Initialize the LPTIM MSP.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 389 of file stm32wbxx_hal_lptim.c.

Referenced by HAL_LPTIM_Init(), and HAL_LPTIM_UnRegisterCallback().

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPTIM Start-Stop operation functions

Functions
LPTIM Start-Stop operation functions
LPTIM Exported Functions

Start-Stop operation functions. More...

Functions

HAL_StatusTypeDef | HAL_LPTIM_PWM_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM in Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode in interrupt mode.

Detailed Description

Start-Stop operation functions.

  ==============================================================================
                ##### LPTIM Start Stop operation functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Start the PWM mode.
      (+) Stop the PWM mode.
      (+) Start the One pulse mode.
      (+) Stop the One pulse mode.
      (+) Start the Set once mode.
      (+) Stop the Set once mode.
      (+) Start the Encoder mode.
      (+) Stop the Encoder mode.
      (+) Start the Timeout mode.
      (+) Stop the Timeout mode.
      (+) Start the Counter mode.
      (+) Stop the Counter mode.

Function Documentation

HAL_StatusTypeDef HAL_LPTIM_Counter_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Start the Counter mode.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1529 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, LPTIM_InitTypeDef::CounterSource, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_PRESCALERDIV1, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_ULPTIM, LPTIM_COUNTERSOURCE_EXTERNAL, LPTIM_FLAG_ARROK, LPTIM_WaitForFlag(), LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Start the Counter mode in interrupt mode.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1607 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_DISABLE, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, LPTIM_InitTypeDef::CounterSource, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_PRESCALERDIV1, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_ULPTIM, LPTIM_COUNTERSOURCE_EXTERNAL, LPTIM_FLAG_ARROK, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_WaitForFlag(), LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Counter_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the Counter mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 1577 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the Counter mode in interrupt mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 1672 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Start the Encoder interface.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1120 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_POLARITY, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC, LPTIM_FLAG_ARROK, LPTIM_PRESCALER_DIV1, LPTIM_WaitForFlag(), LPTIM_ULPClockConfigTypeDef::Polarity, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::UltraLowPowerClock.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Start the Encoder interface in interrupt mode.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1212 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_DISABLE, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_POLARITY, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC, LPTIM_FLAG_ARROK, LPTIM_IT_DOWN, LPTIM_IT_UP, LPTIM_PRESCALER_DIV1, LPTIM_WaitForFlag(), LPTIM_ULPClockConfigTypeDef::Polarity, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::UltraLowPowerClock.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the Encoder interface.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 1179 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the Encoder interface in interrupt mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 1289 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, LPTIM_IT_DOWN, LPTIM_IT_UP, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM One pulse generation.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 676 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_WaitForFlag(), and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM One pulse generation in interrupt mode.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 763 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_DISABLE, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_WaitForFlag(), LPTIM_TriggerConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM One pulse generation.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 731 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM One pulse generation in interrupt mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 848 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_PWM_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM PWM generation.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 453 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_WaitForFlag(), and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM PWM generation in interrupt mode.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF
Pulse | Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF
Return values:
HAL status

Definition at line 540 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_DISABLE, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_WaitForFlag(), LPTIM_TriggerConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_PWM_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM PWM generation.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 508 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM PWM generation in interrupt mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 625 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM in Set once mode.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 899 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_WaitForFlag(), and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM Set once mode in interrupt mode.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 986 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_DISABLE, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_WaitForFlag(), LPTIM_TriggerConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM Set once mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 954 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM Set once mode in interrupt mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 1071 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Timeout
 | ) |  |

Start the Timeout function.

Note:
The first trigger event will start the timer, any successive trigger event will reset the counter and the timer restarts.
Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Timeout | Specifies the TimeOut value to reset the counter. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1332 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_WaitForFlag(), and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Timeout
 | ) |  |

Start the Timeout function in interrupt mode.

Note:
The first trigger event will start the timer, any successive trigger event will reset the counter and the timer restarts.
Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Timeout | Specifies the TimeOut value to reset the counter. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1424 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_DISABLE, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_IT_CMPM, LPTIM_WaitForFlag(), and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the Timeout function.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 1387 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the Timeout function in interrupt mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 1493 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, LPTIM_IT_CMPM, and __LPTIM_HandleTypeDef::State.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPTIM Read operation functions

Functions
LPTIM Read operation functions
LPTIM Exported Functions

Read operation functions. More...

Functions

uint32_t | HAL_LPTIM_ReadCounter (LPTIM_HandleTypeDef *hlptim)
Return the current counter value.
uint32_t | HAL_LPTIM_ReadAutoReload (LPTIM_HandleTypeDef *hlptim)
Return the current Autoreload (Period) value.
uint32_t | HAL_LPTIM_ReadCompare (LPTIM_HandleTypeDef *hlptim)
Return the current Compare (Pulse) value.

Detailed Description

Read operation functions.

  ==============================================================================
                  ##### LPTIM Read operation functions #####
  ==============================================================================
[..]  This section provides LPTIM Reading functions.
      (+) Read the counter value.
      (+) Read the period (Auto-reload) value.
      (+) Read the pulse (Compare)value.

Function Documentation

uint32_t HAL_LPTIM_ReadAutoReload ( LPTIM_HandleTypeDef * hlptim )

Return the current Autoreload (Period) value.

Parameters:
hlptim LPTIM handle
Return values:
Autoreload value.

Definition at line 1737 of file stm32wbxx_hal_lptim.c.

References assert_param, and __LPTIM_HandleTypeDef::Instance.

uint32_t HAL_LPTIM_ReadCompare ( LPTIM_HandleTypeDef * hlptim )

Return the current Compare (Pulse) value.

Parameters:
hlptim LPTIM handle
Return values:
Compare value.

Definition at line 1750 of file stm32wbxx_hal_lptim.c.

References assert_param, and __LPTIM_HandleTypeDef::Instance.

uint32_t HAL_LPTIM_ReadCounter ( LPTIM_HandleTypeDef * hlptim )

Return the current counter value.

Parameters:
hlptim LPTIM handle
Return values:
Counter value.

Definition at line 1724 of file stm32wbxx_hal_lptim.c.

References assert_param, and __LPTIM_HandleTypeDef::Instance.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPTIM IRQ handler and callbacks

Functions
LPTIM IRQ handler and callbacks
LPTIM Exported Functions

LPTIM IRQ handler. More...

Functions

void | HAL_LPTIM_IRQHandler (LPTIM_HandleTypeDef *hlptim)
Handle LPTIM interrupt request.
__weak void | HAL_LPTIM_CompareMatchCallback (LPTIM_HandleTypeDef *hlptim)
Compare match callback in non-blocking mode.
__weak void | HAL_LPTIM_AutoReloadMatchCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload match callback in non-blocking mode.
__weak void | HAL_LPTIM_TriggerCallback (LPTIM_HandleTypeDef *hlptim)
Trigger detected callback in non-blocking mode.
__weak void | HAL_LPTIM_CompareWriteCallback (LPTIM_HandleTypeDef *hlptim)
Compare write callback in non-blocking mode.
__weak void | HAL_LPTIM_AutoReloadWriteCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload write callback in non-blocking mode.
__weak void | HAL_LPTIM_DirectionUpCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Down to Up callback in non-blocking mode.
__weak void | HAL_LPTIM_DirectionDownCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Up to Down callback in non-blocking mode.
HAL_StatusTypeDef | HAL_LPTIM_RegisterCallback (LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback)
Register a User LPTIM callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_LPTIM_UnRegisterCallback (LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID)
Unregister a LPTIM callback LLPTIM callback is redirected to the weak predefined callback.

Detailed Description

LPTIM IRQ handler.

  ==============================================================================
                      ##### LPTIM IRQ handler and callbacks  #####
  ==============================================================================
[..]  This section provides LPTIM IRQ handler and callback functions called within
      the IRQ handler:
   (+) LPTIM interrupt request handler
   (+) Compare match Callback
   (+) Auto-reload match Callback
   (+) External trigger event detection Callback
   (+) Compare register write complete Callback
   (+) Auto-reload register write complete Callback
   (+) Up-counting direction change Callback
   (+) Down-counting direction change Callback

Function Documentation

__weak void HAL_LPTIM_AutoReloadMatchCallback ( LPTIM_HandleTypeDef * hlptim )

Autoreload match callback in non-blocking mode.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 1931 of file stm32wbxx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

__weak void HAL_LPTIM_AutoReloadWriteCallback ( LPTIM_HandleTypeDef * hlptim )

Autoreload write callback in non-blocking mode.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 1976 of file stm32wbxx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

__weak void HAL_LPTIM_CompareMatchCallback ( LPTIM_HandleTypeDef * hlptim )

Compare match callback in non-blocking mode.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 1916 of file stm32wbxx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

__weak void HAL_LPTIM_CompareWriteCallback ( LPTIM_HandleTypeDef * hlptim )

Compare write callback in non-blocking mode.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 1961 of file stm32wbxx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

__weak void HAL_LPTIM_DirectionDownCallback ( LPTIM_HandleTypeDef * hlptim )

Direction counter changed from Up to Down callback in non-blocking mode.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 2006 of file stm32wbxx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

__weak void HAL_LPTIM_DirectionUpCallback ( LPTIM_HandleTypeDef * hlptim )

Direction counter changed from Down to Up callback in non-blocking mode.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 1991 of file stm32wbxx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void HAL_LPTIM_IRQHandler ( LPTIM_HandleTypeDef * hlptim )

Handle LPTIM interrupt request.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 1789 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_GET_FLAG, __HAL_LPTIM_GET_IT_SOURCE, __LPTIM_HandleTypeDef::AutoReloadMatchCallback, __LPTIM_HandleTypeDef::AutoReloadWriteCallback, __LPTIM_HandleTypeDef::CompareMatchCallback, __LPTIM_HandleTypeDef::CompareWriteCallback, __LPTIM_HandleTypeDef::DirectionDownCallback, __LPTIM_HandleTypeDef::DirectionUpCallback, HAL_LPTIM_AutoReloadMatchCallback(), HAL_LPTIM_AutoReloadWriteCallback(), HAL_LPTIM_CompareMatchCallback(), HAL_LPTIM_CompareWriteCallback(), HAL_LPTIM_DirectionDownCallback(), HAL_LPTIM_DirectionUpCallback(), HAL_LPTIM_TriggerCallback(), LPTIM_FLAG_ARRM, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPM, LPTIM_FLAG_CMPOK, LPTIM_FLAG_DOWN, LPTIM_FLAG_EXTTRIG, LPTIM_FLAG_UP, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_DOWN, LPTIM_IT_EXTTRIG, LPTIM_IT_UP, and __LPTIM_HandleTypeDef::TriggerCallback.

HAL_StatusTypeDef HAL_LPTIM_RegisterCallback | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | HAL_LPTIM_CallbackIDTypeDef | CallbackID,
 |  | pLPTIM_CallbackTypeDef | pCallback
 | ) |  |

Register a User LPTIM callback to be used instead of the weak predefined callback.

Parameters:
hlptim | LPTIM handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID
  • HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID
  • HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID
  • HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
  • HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID
  • HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID
  • HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
  • HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID
  • HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID
pCallback | pointer to the callback function
Return values:
status

Definition at line 2034 of file stm32wbxx_hal_lptim.c.

References __LPTIM_HandleTypeDef::AutoReloadMatchCallback, __LPTIM_HandleTypeDef::AutoReloadWriteCallback, __LPTIM_HandleTypeDef::CompareMatchCallback, __LPTIM_HandleTypeDef::CompareWriteCallback, __LPTIM_HandleTypeDef::DirectionDownCallback, __LPTIM_HandleTypeDef::DirectionUpCallback, HAL_LPTIM_AUTORELOAD_MATCH_CB_ID, HAL_LPTIM_AUTORELOAD_WRITE_CB_ID, HAL_LPTIM_COMPARE_MATCH_CB_ID, HAL_LPTIM_COMPARE_WRITE_CB_ID, HAL_LPTIM_DIRECTION_DOWN_CB_ID, HAL_LPTIM_DIRECTION_UP_CB_ID, HAL_LPTIM_MSPDEINIT_CB_ID, HAL_LPTIM_MSPINIT_CB_ID, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_RESET, HAL_LPTIM_TRIGGER_CB_ID, __LPTIM_HandleTypeDef::MspDeInitCallback, __LPTIM_HandleTypeDef::MspInitCallback, __LPTIM_HandleTypeDef::State, and __LPTIM_HandleTypeDef::TriggerCallback.

__weak void HAL_LPTIM_TriggerCallback ( LPTIM_HandleTypeDef * hlptim )

Trigger detected callback in non-blocking mode.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 1946 of file stm32wbxx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | HAL_LPTIM_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a LPTIM callback LLPTIM callback is redirected to the weak predefined callback.

Parameters:
hlptim LPTIM handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID
  • HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID
  • HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID
  • HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
  • HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID
  • HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID
  • HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
  • HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID
  • HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID
Return values:
status

Definition at line 2141 of file stm32wbxx_hal_lptim.c.

References __LPTIM_HandleTypeDef::AutoReloadMatchCallback, __LPTIM_HandleTypeDef::AutoReloadWriteCallback, __LPTIM_HandleTypeDef::CompareMatchCallback, __LPTIM_HandleTypeDef::CompareWriteCallback, __LPTIM_HandleTypeDef::DirectionDownCallback, __LPTIM_HandleTypeDef::DirectionUpCallback, HAL_LPTIM_AUTORELOAD_MATCH_CB_ID, HAL_LPTIM_AUTORELOAD_WRITE_CB_ID, HAL_LPTIM_AutoReloadMatchCallback(), HAL_LPTIM_AutoReloadWriteCallback(), HAL_LPTIM_COMPARE_MATCH_CB_ID, HAL_LPTIM_COMPARE_WRITE_CB_ID, HAL_LPTIM_CompareMatchCallback(), HAL_LPTIM_CompareWriteCallback(), HAL_LPTIM_DIRECTION_DOWN_CB_ID, HAL_LPTIM_DIRECTION_UP_CB_ID, HAL_LPTIM_DirectionDownCallback(), HAL_LPTIM_DirectionUpCallback(), HAL_LPTIM_MspDeInit(), HAL_LPTIM_MSPDEINIT_CB_ID, HAL_LPTIM_MspInit(), HAL_LPTIM_MSPINIT_CB_ID, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_RESET, HAL_LPTIM_TRIGGER_CB_ID, HAL_LPTIM_TriggerCallback(), __LPTIM_HandleTypeDef::MspDeInitCallback, __LPTIM_HandleTypeDef::MspInitCallback, __LPTIM_HandleTypeDef::State, and __LPTIM_HandleTypeDef::TriggerCallback.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
LPTIM Exported Functions

Peripheral State functions. More...

Functions

HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState (LPTIM_HandleTypeDef *hlptim)
Return the LPTIM handle state.

Detailed Description

Peripheral State functions.

  ==============================================================================
                      ##### Peripheral State functions #####
  ==============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral.

Function Documentation

HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState ( LPTIM_HandleTypeDef * hlptim )

Return the LPTIM handle state.

Parameters:
hlptim LPTIM handle
Return values:
HAL state

Definition at line 2249 of file stm32wbxx_hal_lptim.c.

References __LPTIM_HandleTypeDef::State.

Referenced by HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_DeInit(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop(), and HAL_LPTIM_TimeOut_Stop_IT().

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPTIM Exported Functions

Modules | Functions
LPTIM Exported Functions
LPTIM

Modules

Initialization/de-initialization functions

Initialization and Configuration functions.

LPTIM Start-Stop operation functions

Start-Stop operation functions.

LPTIM Read operation functions

Read operation functions.

LPTIM IRQ handler and callbacks

LPTIM IRQ handler.

Peripheral State functions

Peripheral State functions.

Functions

HAL_StatusTypeDef | HAL_LPTIM_Init (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_LPTIM_DeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize the LPTIM peripheral.
void | HAL_LPTIM_MspInit (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM MSP.
void | HAL_LPTIM_MspDeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize LPTIM MSP.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM in Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode in interrupt mode.
uint32_t | HAL_LPTIM_ReadCounter (LPTIM_HandleTypeDef *hlptim)
Return the current counter value.
uint32_t | HAL_LPTIM_ReadAutoReload (LPTIM_HandleTypeDef *hlptim)
Return the current Autoreload (Period) value.
uint32_t | HAL_LPTIM_ReadCompare (LPTIM_HandleTypeDef *hlptim)
Return the current Compare (Pulse) value.
void | HAL_LPTIM_IRQHandler (LPTIM_HandleTypeDef *hlptim)
Handle LPTIM interrupt request.
void | HAL_LPTIM_CompareMatchCallback (LPTIM_HandleTypeDef *hlptim)
Compare match callback in non-blocking mode.
void | HAL_LPTIM_AutoReloadMatchCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload match callback in non-blocking mode.
void | HAL_LPTIM_TriggerCallback (LPTIM_HandleTypeDef *hlptim)
Trigger detected callback in non-blocking mode.
void | HAL_LPTIM_CompareWriteCallback (LPTIM_HandleTypeDef *hlptim)
Compare write callback in non-blocking mode.
void | HAL_LPTIM_AutoReloadWriteCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload write callback in non-blocking mode.
void | HAL_LPTIM_DirectionUpCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Down to Up callback in non-blocking mode.
void | HAL_LPTIM_DirectionDownCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Up to Down callback in non-blocking mode.
HAL_StatusTypeDef | HAL_LPTIM_RegisterCallback (LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback)
Register a User LPTIM callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_LPTIM_UnRegisterCallback (LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID)
Unregister a LPTIM callback LLPTIM callback is redirected to the weak predefined callback.
HAL_LPTIM_StateTypeDef | HAL_LPTIM_GetState (LPTIM_HandleTypeDef *hlptim)
Return the LPTIM handle state.

Function Documentation

void HAL_LPTIM_AutoReloadMatchCallback ( LPTIM_HandleTypeDef * hlptim )

Autoreload match callback in non-blocking mode.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 1931 of file stm32wbxx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void HAL_LPTIM_AutoReloadWriteCallback ( LPTIM_HandleTypeDef * hlptim )

Autoreload write callback in non-blocking mode.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 1976 of file stm32wbxx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void HAL_LPTIM_CompareMatchCallback ( LPTIM_HandleTypeDef * hlptim )

Compare match callback in non-blocking mode.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 1916 of file stm32wbxx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void HAL_LPTIM_CompareWriteCallback ( LPTIM_HandleTypeDef * hlptim )

Compare write callback in non-blocking mode.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 1961 of file stm32wbxx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

HAL_StatusTypeDef HAL_LPTIM_Counter_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Start the Counter mode.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1529 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, LPTIM_InitTypeDef::CounterSource, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_PRESCALERDIV1, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_ULPTIM, LPTIM_COUNTERSOURCE_EXTERNAL, LPTIM_FLAG_ARROK, LPTIM_WaitForFlag(), LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Start the Counter mode in interrupt mode.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1607 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_DISABLE, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, LPTIM_InitTypeDef::CounterSource, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_PRESCALERDIV1, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_ULPTIM, LPTIM_COUNTERSOURCE_EXTERNAL, LPTIM_FLAG_ARROK, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_WaitForFlag(), LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Counter_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the Counter mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 1577 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the Counter mode in interrupt mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 1672 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_DeInit ( LPTIM_HandleTypeDef * hlptim )

DeInitialize the LPTIM peripheral.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 342 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, HAL_LPTIM_GetState(), HAL_LPTIM_MspDeInit(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_RESET, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::MspDeInitCallback, and __LPTIM_HandleTypeDef::State.

void HAL_LPTIM_DirectionDownCallback ( LPTIM_HandleTypeDef * hlptim )

Direction counter changed from Up to Down callback in non-blocking mode.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 2006 of file stm32wbxx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void HAL_LPTIM_DirectionUpCallback ( LPTIM_HandleTypeDef * hlptim )

Direction counter changed from Down to Up callback in non-blocking mode.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 1991 of file stm32wbxx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

HAL_StatusTypeDef HAL_LPTIM_Encoder_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Start the Encoder interface.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1120 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_POLARITY, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC, LPTIM_FLAG_ARROK, LPTIM_PRESCALER_DIV1, LPTIM_WaitForFlag(), LPTIM_ULPClockConfigTypeDef::Polarity, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::UltraLowPowerClock.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period
 | ) |  |

Start the Encoder interface in interrupt mode.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1212 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_DISABLE, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, LPTIM_InitTypeDef::Clock, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_POLARITY, IS_LPTIM_PERIOD, LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC, LPTIM_FLAG_ARROK, LPTIM_IT_DOWN, LPTIM_IT_UP, LPTIM_PRESCALER_DIV1, LPTIM_WaitForFlag(), LPTIM_ULPClockConfigTypeDef::Polarity, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ClockConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::UltraLowPowerClock.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the Encoder interface.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 1179 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the Encoder interface in interrupt mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 1289 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, LPTIM_IT_DOWN, LPTIM_IT_UP, and __LPTIM_HandleTypeDef::State.

HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState ( LPTIM_HandleTypeDef * hlptim )

Return the LPTIM handle state.

Parameters:
hlptim LPTIM handle
Return values:
HAL state

Definition at line 2249 of file stm32wbxx_hal_lptim.c.

References __LPTIM_HandleTypeDef::State.

Referenced by HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_DeInit(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop(), and HAL_LPTIM_TimeOut_Stop_IT().

HAL_StatusTypeDef HAL_LPTIM_Init ( LPTIM_HandleTypeDef * hlptim )

Initialize the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and initialize the associated handle.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 216 of file stm32wbxx_hal_lptim.c.

References LPTIM_TriggerConfigTypeDef::ActiveEdge, assert_param, LPTIM_InitTypeDef::Clock, LPTIM_InitTypeDef::CounterSource, HAL_LPTIM_MspInit(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_RESET, __LPTIM_HandleTypeDef::Init, LPTIM_InitTypeDef::Input1Source, LPTIM_InitTypeDef::Input2Source, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_CLOCK_POLARITY, IS_LPTIM_CLOCK_PRESCALER, IS_LPTIM_CLOCK_SAMPLE_TIME, IS_LPTIM_CLOCK_SOURCE, IS_LPTIM_COUNTER_SOURCE, IS_LPTIM_EXT_TRG_POLARITY, IS_LPTIM_INPUT1_SOURCE, IS_LPTIM_INPUT2_SOURCE, IS_LPTIM_OUTPUT_POLARITY, IS_LPTIM_TRG_SOURCE, IS_LPTIM_TRIG_SAMPLE_TIME, IS_LPTIM_UPDATE_MODE, __LPTIM_HandleTypeDef::Lock, LPTIM_CLOCKSOURCE_ULPTIM, LPTIM_COUNTERSOURCE_EXTERNAL, LPTIM_ResetCallback(), LPTIM_TRIGSOURCE_SOFTWARE, __LPTIM_HandleTypeDef::MspInitCallback, LPTIM_InitTypeDef::OutputPolarity, LPTIM_ULPClockConfigTypeDef::Polarity, LPTIM_ClockConfigTypeDef::Prescaler, LPTIM_ULPClockConfigTypeDef::SampleTime, LPTIM_TriggerConfigTypeDef::SampleTime, LPTIM_ClockConfigTypeDef::Source, LPTIM_TriggerConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, LPTIM_InitTypeDef::Trigger, LPTIM_InitTypeDef::UltraLowPowerClock, and LPTIM_InitTypeDef::UpdateMode.

void HAL_LPTIM_IRQHandler ( LPTIM_HandleTypeDef * hlptim )

Handle LPTIM interrupt request.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 1789 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_GET_FLAG, __HAL_LPTIM_GET_IT_SOURCE, __LPTIM_HandleTypeDef::AutoReloadMatchCallback, __LPTIM_HandleTypeDef::AutoReloadWriteCallback, __LPTIM_HandleTypeDef::CompareMatchCallback, __LPTIM_HandleTypeDef::CompareWriteCallback, __LPTIM_HandleTypeDef::DirectionDownCallback, __LPTIM_HandleTypeDef::DirectionUpCallback, HAL_LPTIM_AutoReloadMatchCallback(), HAL_LPTIM_AutoReloadWriteCallback(), HAL_LPTIM_CompareMatchCallback(), HAL_LPTIM_CompareWriteCallback(), HAL_LPTIM_DirectionDownCallback(), HAL_LPTIM_DirectionUpCallback(), HAL_LPTIM_TriggerCallback(), LPTIM_FLAG_ARRM, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPM, LPTIM_FLAG_CMPOK, LPTIM_FLAG_DOWN, LPTIM_FLAG_EXTTRIG, LPTIM_FLAG_UP, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_DOWN, LPTIM_IT_EXTTRIG, LPTIM_IT_UP, and __LPTIM_HandleTypeDef::TriggerCallback.

void HAL_LPTIM_MspDeInit ( LPTIM_HandleTypeDef * hlptim )

DeInitialize LPTIM MSP.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 404 of file stm32wbxx_hal_lptim.c.

Referenced by HAL_LPTIM_DeInit(), and HAL_LPTIM_UnRegisterCallback().

void HAL_LPTIM_MspInit ( LPTIM_HandleTypeDef * hlptim )

Initialize the LPTIM MSP.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 389 of file stm32wbxx_hal_lptim.c.

Referenced by HAL_LPTIM_Init(), and HAL_LPTIM_UnRegisterCallback().

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM One pulse generation.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 676 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_WaitForFlag(), and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM One pulse generation in interrupt mode.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 763 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_DISABLE, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_WaitForFlag(), LPTIM_TriggerConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM One pulse generation.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 731 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM One pulse generation in interrupt mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 848 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_PWM_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM PWM generation.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 453 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_WaitForFlag(), and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM PWM generation in interrupt mode.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF
Pulse | Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF
Return values:
HAL status

Definition at line 540 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_DISABLE, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_WaitForFlag(), LPTIM_TriggerConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_PWM_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM PWM generation.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 508 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM PWM generation in interrupt mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 625 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

uint32_t HAL_LPTIM_ReadAutoReload ( LPTIM_HandleTypeDef * hlptim )

Return the current Autoreload (Period) value.

Parameters:
hlptim LPTIM handle
Return values:
Autoreload value.

Definition at line 1737 of file stm32wbxx_hal_lptim.c.

References assert_param, and __LPTIM_HandleTypeDef::Instance.

uint32_t HAL_LPTIM_ReadCompare ( LPTIM_HandleTypeDef * hlptim )

Return the current Compare (Pulse) value.

Parameters:
hlptim LPTIM handle
Return values:
Compare value.

Definition at line 1750 of file stm32wbxx_hal_lptim.c.

References assert_param, and __LPTIM_HandleTypeDef::Instance.

uint32_t HAL_LPTIM_ReadCounter ( LPTIM_HandleTypeDef * hlptim )

Return the current counter value.

Parameters:
hlptim LPTIM handle
Return values:
Counter value.

Definition at line 1724 of file stm32wbxx_hal_lptim.c.

References assert_param, and __LPTIM_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_LPTIM_RegisterCallback | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | HAL_LPTIM_CallbackIDTypeDef | CallbackID,
 |  | pLPTIM_CallbackTypeDef | pCallback
 | ) |  |

Register a User LPTIM callback to be used instead of the weak predefined callback.

Parameters:
hlptim | LPTIM handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID
  • HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID
  • HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID
  • HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
  • HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID
  • HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID
  • HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
  • HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID
  • HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID
pCallback | pointer to the callback function
Return values:
status

Definition at line 2034 of file stm32wbxx_hal_lptim.c.

References __LPTIM_HandleTypeDef::AutoReloadMatchCallback, __LPTIM_HandleTypeDef::AutoReloadWriteCallback, __LPTIM_HandleTypeDef::CompareMatchCallback, __LPTIM_HandleTypeDef::CompareWriteCallback, __LPTIM_HandleTypeDef::DirectionDownCallback, __LPTIM_HandleTypeDef::DirectionUpCallback, HAL_LPTIM_AUTORELOAD_MATCH_CB_ID, HAL_LPTIM_AUTORELOAD_WRITE_CB_ID, HAL_LPTIM_COMPARE_MATCH_CB_ID, HAL_LPTIM_COMPARE_WRITE_CB_ID, HAL_LPTIM_DIRECTION_DOWN_CB_ID, HAL_LPTIM_DIRECTION_UP_CB_ID, HAL_LPTIM_MSPDEINIT_CB_ID, HAL_LPTIM_MSPINIT_CB_ID, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_RESET, HAL_LPTIM_TRIGGER_CB_ID, __LPTIM_HandleTypeDef::MspDeInitCallback, __LPTIM_HandleTypeDef::MspInitCallback, __LPTIM_HandleTypeDef::State, and __LPTIM_HandleTypeDef::TriggerCallback.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM in Set once mode.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 899 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_WaitForFlag(), and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Pulse
 | ) |  |

Start the LPTIM Set once mode in interrupt mode.

Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Pulse | Specifies the compare value. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 986 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_DISABLE, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_SINGLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_WaitForFlag(), LPTIM_TriggerConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM Set once mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 954 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the LPTIM Set once mode in interrupt mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 1071 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Init, __LPTIM_HandleTypeDef::Instance, LPTIM_IT_ARRM, LPTIM_IT_ARROK, LPTIM_IT_CMPM, LPTIM_IT_CMPOK, LPTIM_IT_EXTTRIG, LPTIM_TRIGSOURCE_SOFTWARE, LPTIM_TriggerConfigTypeDef::Source, __LPTIM_HandleTypeDef::State, and LPTIM_InitTypeDef::Trigger.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Timeout
 | ) |  |

Start the Timeout function.

Note:
The first trigger event will start the timer, any successive trigger event will reset the counter and the timer restarts.
Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Timeout | Specifies the TimeOut value to reset the counter. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1332 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_ENABLE, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_WaitForFlag(), and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | uint32_t | Period,
 |  | uint32_t | Timeout
 | ) |  |

Start the Timeout function in interrupt mode.

Note:
The first trigger event will start the timer, any successive trigger event will reset the counter and the timer restarts.
Parameters:
hlptim | LPTIM handle
Period | Specifies the Autoreload value. This parameter must be a value between 0x0000 and 0xFFFF.
Timeout | Specifies the TimeOut value to reset the counter. This parameter must be a value between 0x0000 and 0xFFFF.
Return values:
HAL status

Definition at line 1424 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_AUTORELOAD_SET, __HAL_LPTIM_CLEAR_FLAG, __HAL_LPTIM_COMPARE_SET, __HAL_LPTIM_DISABLE, __HAL_LPTIM_ENABLE, __HAL_LPTIM_ENABLE_IT, __HAL_LPTIM_START_CONTINUOUS, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, IS_LPTIM_PERIOD, IS_LPTIM_PULSE, LPTIM_FLAG_ARROK, LPTIM_FLAG_CMPOK, LPTIM_IT_CMPM, LPTIM_WaitForFlag(), and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop ( LPTIM_HandleTypeDef * hlptim )

Stop the Timeout function.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 1387 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, and __LPTIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT ( LPTIM_HandleTypeDef * hlptim )

Stop the Timeout function in interrupt mode.

Parameters:
hlptim LPTIM handle
Return values:
HAL status

Definition at line 1493 of file stm32wbxx_hal_lptim.c.

References __HAL_LPTIM_DISABLE, __HAL_LPTIM_DISABLE_IT, assert_param, HAL_LPTIM_GetState(), HAL_LPTIM_STATE_BUSY, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_TIMEOUT, __LPTIM_HandleTypeDef::Instance, LPTIM_IT_CMPM, and __LPTIM_HandleTypeDef::State.

void HAL_LPTIM_TriggerCallback ( LPTIM_HandleTypeDef * hlptim )

Trigger detected callback in non-blocking mode.

Parameters:
hlptim LPTIM handle
Return values:
None

Definition at line 1946 of file stm32wbxx_hal_lptim.c.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback | ( | LPTIM_HandleTypeDef * | hlptim,
 |  | HAL_LPTIM_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a LPTIM callback LLPTIM callback is redirected to the weak predefined callback.

Parameters:
hlptim LPTIM handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID
  • HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID
  • HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID
  • HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
  • HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID
  • HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID
  • HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
  • HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID
  • HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID
Return values:
status

Definition at line 2141 of file stm32wbxx_hal_lptim.c.

References __LPTIM_HandleTypeDef::AutoReloadMatchCallback, __LPTIM_HandleTypeDef::AutoReloadWriteCallback, __LPTIM_HandleTypeDef::CompareMatchCallback, __LPTIM_HandleTypeDef::CompareWriteCallback, __LPTIM_HandleTypeDef::DirectionDownCallback, __LPTIM_HandleTypeDef::DirectionUpCallback, HAL_LPTIM_AUTORELOAD_MATCH_CB_ID, HAL_LPTIM_AUTORELOAD_WRITE_CB_ID, HAL_LPTIM_AutoReloadMatchCallback(), HAL_LPTIM_AutoReloadWriteCallback(), HAL_LPTIM_COMPARE_MATCH_CB_ID, HAL_LPTIM_COMPARE_WRITE_CB_ID, HAL_LPTIM_CompareMatchCallback(), HAL_LPTIM_CompareWriteCallback(), HAL_LPTIM_DIRECTION_DOWN_CB_ID, HAL_LPTIM_DIRECTION_UP_CB_ID, HAL_LPTIM_DirectionDownCallback(), HAL_LPTIM_DirectionUpCallback(), HAL_LPTIM_MspDeInit(), HAL_LPTIM_MSPDEINIT_CB_ID, HAL_LPTIM_MspInit(), HAL_LPTIM_MSPINIT_CB_ID, HAL_LPTIM_STATE_READY, HAL_LPTIM_STATE_RESET, HAL_LPTIM_TRIGGER_CB_ID, HAL_LPTIM_TriggerCallback(), __LPTIM_HandleTypeDef::MspDeInitCallback, __LPTIM_HandleTypeDef::MspInitCallback, __LPTIM_HandleTypeDef::State, and __LPTIM_HandleTypeDef::TriggerCallback.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPTIM Exported Types

Data Structures | Defines | Typedefs | Enumerations
LPTIM Exported Types
LPTIM

Data Structures

struct | LPTIM_ClockConfigTypeDef
LPTIM Clock configuration definition. More...
struct | LPTIM_ULPClockConfigTypeDef
LPTIM Clock configuration definition. More...
struct | LPTIM_TriggerConfigTypeDef
LPTIM Trigger configuration definition. More...
struct | LPTIM_InitTypeDef
LPTIM Initialization Structure definition. More...
struct | __LPTIM_HandleTypeDef
LPTIM handle Structure definition. More...

Defines

#define | LPTIM_EXTI_LINE_LPTIM1 EXTI_IMR1_IM29
#define | LPTIM_EXTI_LINE_LPTIM2 EXTI_IMR1_IM30

Typedefs

typedef struct
__LPTIM_HandleTypeDef 		LPTIM_HandleTypeDef
LPTIM handle Structure definition.
typedef void(* | pLPTIM_CallbackTypeDef )(LPTIM_HandleTypeDef *hlptim)
HAL TIM Callback pointer definition.

Enumerations

enum HAL_LPTIM_StateTypeDef {
HAL_LPTIM_STATE_RESET = 0x00U, HAL_LPTIM_STATE_READY = 0x01U, HAL_LPTIM_STATE_BUSY = 0x02U, HAL_LPTIM_STATE_TIMEOUT = 0x03U,
HAL_LPTIM_STATE_ERROR = 0x04U
}
HAL LPTIM State structure definition. More...
enum HAL_LPTIM_CallbackIDTypeDef {
HAL_LPTIM_MSPINIT_CB_ID = 0x00U, HAL_LPTIM_MSPDEINIT_CB_ID = 0x01U, HAL_LPTIM_COMPARE_MATCH_CB_ID = 0x02U, HAL_LPTIM_AUTORELOAD_MATCH_CB_ID = 0x03U,
HAL_LPTIM_TRIGGER_CB_ID = 0x04U, HAL_LPTIM_COMPARE_WRITE_CB_ID = 0x05U, HAL_LPTIM_AUTORELOAD_WRITE_CB_ID = 0x06U, HAL_LPTIM_DIRECTION_UP_CB_ID = 0x07U,
HAL_LPTIM_DIRECTION_DOWN_CB_ID = 0x08U
}
HAL LPTIM Callback ID enumeration definition. More...

Define Documentation

#define LPTIM_EXTI_LINE_LPTIM1 EXTI_IMR1_IM29

External interrupt line 29 Connected to the LPTIM1 EXTI Line

Definition at line 45 of file stm32wbxx_hal_lptim.h.

#define LPTIM_EXTI_LINE_LPTIM2 EXTI_IMR1_IM30

External interrupt line 30 Connected to the LPTIM2 EXTI Line

Definition at line 46 of file stm32wbxx_hal_lptim.h.

Typedef Documentation

typedef struct __LPTIM_HandleTypeDef LPTIM_HandleTypeDef

LPTIM handle Structure definition.

typedef void(* pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim)

HAL TIM Callback pointer definition.

pointer to the LPTIM callback function

Definition at line 191 of file stm32wbxx_hal_lptim.h.

Enumeration Type Documentation

enum HAL_LPTIM_CallbackIDTypeDef

HAL LPTIM Callback ID enumeration definition.

Enumerator:
HAL_LPTIM_MSPINIT_CB_ID

LPTIM Base Msp Init Callback ID

HAL_LPTIM_MSPDEINIT_CB_ID

LPTIM Base Msp DeInit Callback ID

HAL_LPTIM_COMPARE_MATCH_CB_ID

Compare match Callback ID

HAL_LPTIM_AUTORELOAD_MATCH_CB_ID

Auto-reload match Callback ID

HAL_LPTIM_TRIGGER_CB_ID

External trigger event detection Callback ID

HAL_LPTIM_COMPARE_WRITE_CB_ID

Compare register write complete Callback ID

HAL_LPTIM_AUTORELOAD_WRITE_CB_ID

Auto-reload register write complete Callback ID

HAL_LPTIM_DIRECTION_UP_CB_ID

Up-counting direction change Callback ID

HAL_LPTIM_DIRECTION_DOWN_CB_ID

Down-counting direction change Callback ID

Definition at line 175 of file stm32wbxx_hal_lptim.h.

enum HAL_LPTIM_StateTypeDef

HAL LPTIM State structure definition.

Enumerator:
HAL_LPTIM_STATE_RESET

Peripheral not yet initialized or disabled

HAL_LPTIM_STATE_READY

Peripheral Initialized and ready for use

HAL_LPTIM_STATE_BUSY

An internal process is ongoing

HAL_LPTIM_STATE_TIMEOUT

Timeout state

HAL_LPTIM_STATE_ERROR

Internal Process is ongoing

Definition at line 130 of file stm32wbxx_hal_lptim.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPTIM_ClockConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LPTIM_ClockConfigTypeDef Struct Reference
LPTIM Exported Types

LPTIM Clock configuration definition. More...

#include <stm32wbxx_hal_lptim.h>

Data Fields

uint32_t | Source
uint32_t | Prescaler

Detailed Description

LPTIM Clock configuration definition.

Definition at line 51 of file stm32wbxx_hal_lptim.h.

Field Documentation

uint32_t LPTIM_ClockConfigTypeDef::Prescaler

Specifies the counter clock Prescaler. This parameter can be a value of LPTIM Clock Prescaler

Definition at line 56 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_ClockConfigTypeDef::Source

Selects the clock source. This parameter can be a value of LPTIM Clock Source

Definition at line 53 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_lptim.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPTIM_ULPClockConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LPTIM_ULPClockConfigTypeDef Struct Reference
LPTIM Exported Types

LPTIM Clock configuration definition. More...

#include <stm32wbxx_hal_lptim.h>

Data Fields

uint32_t | Polarity
uint32_t | SampleTime

Detailed Description

LPTIM Clock configuration definition.

Definition at line 64 of file stm32wbxx_hal_lptim.h.

Field Documentation

uint32_t LPTIM_ULPClockConfigTypeDef::Polarity

Selects the polarity of the active edge for the counter unit if the ULPTIM input is selected. Note: This parameter is used only when Ultra low power clock source is used. Note: If the polarity is configured on 'both edges', an auxiliary clock (one of the Low power oscillator) must be active. This parameter can be a value of LPTIM Clock Polarity

Definition at line 66 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_ULPClockConfigTypeDef::SampleTime

Selects the clock sampling time to configure the clock glitch filter. Note: This parameter is used only when Ultra low power clock source is used. This parameter can be a value of LPTIM Clock Sample Time

Definition at line 73 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_lptim.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPTIM_TriggerConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LPTIM_TriggerConfigTypeDef Struct Reference
LPTIM Exported Types

LPTIM Trigger configuration definition. More...

#include <stm32wbxx_hal_lptim.h>

Data Fields

uint32_t | Source
uint32_t | ActiveEdge
uint32_t | SampleTime

Detailed Description

LPTIM Trigger configuration definition.

Definition at line 82 of file stm32wbxx_hal_lptim.h.

Field Documentation

uint32_t LPTIM_TriggerConfigTypeDef::ActiveEdge

Selects the Trigger active edge. Note: This parameter is used only when an external trigger is used. This parameter can be a value of LPTIM External Trigger Polarity

Definition at line 87 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

uint32_t LPTIM_TriggerConfigTypeDef::SampleTime

Selects the trigger sampling time to configure the clock glitch filter. Note: This parameter is used only when an external trigger is used. This parameter can be a value of LPTIM Trigger Sample Time

Definition at line 91 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

uint32_t LPTIM_TriggerConfigTypeDef::Source

Selects the Trigger source. This parameter can be a value of LPTIM Trigger Source

Definition at line 84 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_lptim.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPTIM_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LPTIM_InitTypeDef Struct Reference
LPTIM Exported Types

LPTIM Initialization Structure definition. More...

#include <stm32wbxx_hal_lptim.h>

Data Fields

LPTIM_ClockConfigTypeDef Clock
LPTIM_ULPClockConfigTypeDef UltraLowPowerClock
LPTIM_TriggerConfigTypeDef Trigger
uint32_t | OutputPolarity
uint32_t | UpdateMode
uint32_t | CounterSource
uint32_t | Input1Source
uint32_t | Input2Source

Detailed Description

LPTIM Initialization Structure definition.

Definition at line 99 of file stm32wbxx_hal_lptim.h.

Field Documentation

LPTIM_ClockConfigTypeDef LPTIM_InitTypeDef::Clock

Specifies the clock parameters

Definition at line 101 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_InitTypeDef::CounterSource

Specifies whether the counter is incremented each internal event or each external event. This parameter can be a value of LPTIM Counter Source

Definition at line 114 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_InitTypeDef::Input1Source

Specifies source selected for input1 (GPIO or comparator output). This parameter can be a value of LPTIM Input1 Source

Definition at line 118 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

uint32_t LPTIM_InitTypeDef::Input2Source

Specifies source selected for input2 (GPIO or comparator output). Note: This parameter is used only for encoder feature so is used only for LPTIM1 instance. This parameter can be a value of LPTIM Input2 Source

Definition at line 121 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

uint32_t LPTIM_InitTypeDef::OutputPolarity

Specifies the Output polarity. This parameter can be a value of LPTIM Output Polarity

Definition at line 107 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

LPTIM_TriggerConfigTypeDef LPTIM_InitTypeDef::Trigger

Specifies the Trigger parameters

Definition at line 105 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

LPTIM_ULPClockConfigTypeDef LPTIM_InitTypeDef::UltraLowPowerClock

Specifies the Ultra Low Power clock parameters

Definition at line 103 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

uint32_t LPTIM_InitTypeDef::UpdateMode

Specifies whether the update of the autoreload and the compare values is done immediately or after the end of current period. This parameter can be a value of LPTIM Updating Mode

Definition at line 110 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_lptim.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: __LPTIM_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__LPTIM_HandleTypeDef Struct Reference
LPTIM Exported Types

LPTIM handle Structure definition. More...

#include <stm32wbxx_hal_lptim.h>

Data Fields

LPTIM_TypeDef * | Instance
LPTIM_InitTypeDef Init
HAL_StatusTypeDef | Status
HAL_LockTypeDef | Lock
__IO HAL_LPTIM_StateTypeDef | State
void(* | MspInitCallback )(struct __LPTIM_HandleTypeDef *hlptim)
void(* | MspDeInitCallback )(struct __LPTIM_HandleTypeDef *hlptim)
void(* | CompareMatchCallback )(struct __LPTIM_HandleTypeDef *hlptim)
void(* | AutoReloadMatchCallback )(struct __LPTIM_HandleTypeDef *hlptim)
void(* | TriggerCallback )(struct __LPTIM_HandleTypeDef *hlptim)
void(* | CompareWriteCallback )(struct __LPTIM_HandleTypeDef *hlptim)
void(* | AutoReloadWriteCallback )(struct __LPTIM_HandleTypeDef *hlptim)
void(* | DirectionUpCallback )(struct __LPTIM_HandleTypeDef *hlptim)
void(* | DirectionDownCallback )(struct __LPTIM_HandleTypeDef *hlptim)

Detailed Description

LPTIM handle Structure definition.

Definition at line 143 of file stm32wbxx_hal_lptim.h.

Field Documentation

void(* __LPTIM_HandleTypeDef::AutoReloadMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim)

Auto-reload match Callback

Definition at line 162 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_RegisterCallback(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void(* __LPTIM_HandleTypeDef::AutoReloadWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim)

Auto-reload register write complete Callback

Definition at line 165 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_RegisterCallback(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void(* __LPTIM_HandleTypeDef::CompareMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim)

Compare match Callback

Definition at line 161 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_RegisterCallback(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void(* __LPTIM_HandleTypeDef::CompareWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim)

Compare register write complete Callback

Definition at line 164 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_RegisterCallback(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void(* __LPTIM_HandleTypeDef::DirectionDownCallback)(struct __LPTIM_HandleTypeDef *hlptim)

Down-counting direction change Callback

Definition at line 167 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_RegisterCallback(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

void(* __LPTIM_HandleTypeDef::DirectionUpCallback)(struct __LPTIM_HandleTypeDef *hlptim)

Up-counting direction change Callback

Definition at line 166 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_RegisterCallback(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

LPTIM_InitTypeDef __LPTIM_HandleTypeDef::Init

LPTIM required parameters

Definition at line 150 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

LPTIM_TypeDef* __LPTIM_HandleTypeDef::Instance

Register base address

Definition at line 148 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_ReadAutoReload(), HAL_LPTIM_ReadCompare(), HAL_LPTIM_ReadCounter(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop(), HAL_LPTIM_TimeOut_Stop_IT(), and LPTIM_Disable().

HAL_LockTypeDef __LPTIM_HandleTypeDef::Lock

LPTIM locking object

Definition at line 154 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

void(* __LPTIM_HandleTypeDef::MspDeInitCallback)(struct __LPTIM_HandleTypeDef *hlptim)

LPTIM Base Msp DeInit Callback

Definition at line 160 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_DeInit(), HAL_LPTIM_RegisterCallback(), and HAL_LPTIM_UnRegisterCallback().

void(* __LPTIM_HandleTypeDef::MspInitCallback)(struct __LPTIM_HandleTypeDef *hlptim)

LPTIM Base Msp Init Callback

Definition at line 159 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Init(), HAL_LPTIM_RegisterCallback(), and HAL_LPTIM_UnRegisterCallback().

__IO HAL_LPTIM_StateTypeDef __LPTIM_HandleTypeDef::State

LPTIM peripheral state

Definition at line 156 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_DeInit(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_GetState(), HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_RegisterCallback(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop(), HAL_LPTIM_TimeOut_Stop_IT(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_Disable().

HAL_StatusTypeDef __LPTIM_HandleTypeDef::Status

LPTIM peripheral status

Definition at line 152 of file stm32wbxx_hal_lptim.h.

void(* __LPTIM_HandleTypeDef::TriggerCallback)(struct __LPTIM_HandleTypeDef *hlptim)

External trigger event detection Callback

Definition at line 163 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_RegisterCallback(), HAL_LPTIM_UnRegisterCallback(), and LPTIM_ResetCallback().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_lptim.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPTIM Clock Source

Defines
LPTIM Clock Source
LPTIM Exported Constants

Defines

#define | LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC 0x00000000U
#define | LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL

Define Documentation

#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC 0x00000000U

Definition at line 206 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), and HAL_LPTIM_Encoder_Start_IT().

#define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL

Definition at line 207 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), and HAL_LPTIM_Init().

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPTIM Clock Prescaler

Defines
LPTIM Clock Prescaler
LPTIM Exported Constants

Defines

#define | LPTIM_PRESCALER_DIV1 0x00000000U
#define | LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
#define | LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
#define | LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1)
#define | LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
#define | LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2)
#define | LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2)
#define | LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC

Define Documentation

#define LPTIM_PRESCALER_DIV1 0x00000000U

Definition at line 215 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), and HAL_LPTIM_Encoder_Start_IT().

#define LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC

Definition at line 222 of file stm32wbxx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2

Definition at line 219 of file stm32wbxx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0

Definition at line 216 of file stm32wbxx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2)

Definition at line 220 of file stm32wbxx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1

Definition at line 217 of file stm32wbxx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2)

Definition at line 221 of file stm32wbxx_hal_lptim.h.

#define LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1)

Definition at line 218 of file stm32wbxx_hal_lptim.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPTIM Output Polarity

Defines
LPTIM Output Polarity
LPTIM Exported Constants

Defines

#define | LPTIM_OUTPUTPOLARITY_HIGH 0x00000000U
#define | LPTIM_OUTPUTPOLARITY_LOW LPTIM_CFGR_WAVPOL

Define Documentation

#define LPTIM_OUTPUTPOLARITY_HIGH 0x00000000U

Definition at line 231 of file stm32wbxx_hal_lptim.h.

#define LPTIM_OUTPUTPOLARITY_LOW LPTIM_CFGR_WAVPOL

Definition at line 232 of file stm32wbxx_hal_lptim.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPTIM Clock Sample Time

Defines
LPTIM Clock Sample Time
LPTIM Exported Constants

Defines

#define | LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 0x00000000U
#define | LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0
#define | LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1
#define | LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT

Define Documentation

#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0

Definition at line 241 of file stm32wbxx_hal_lptim.h.

#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1

Definition at line 242 of file stm32wbxx_hal_lptim.h.

#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT

Definition at line 243 of file stm32wbxx_hal_lptim.h.

#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 0x00000000U

Definition at line 240 of file stm32wbxx_hal_lptim.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPTIM Clock Polarity

Defines
LPTIM Clock Polarity
LPTIM Exported Constants

Defines

#define | LPTIM_CLOCKPOLARITY_RISING 0x00000000U
#define | LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0
#define | LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1

Define Documentation

#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0

Definition at line 252 of file stm32wbxx_hal_lptim.h.

#define LPTIM_CLOCKPOLARITY_RISING 0x00000000U

Definition at line 251 of file stm32wbxx_hal_lptim.h.

#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1

Definition at line 253 of file stm32wbxx_hal_lptim.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPTIM Trigger Source

Defines
LPTIM Trigger Source
LPTIM Exported Constants

Defines

#define | LPTIM_TRIGSOURCE_SOFTWARE 0x0000FFFFU
#define | LPTIM_TRIGSOURCE_0 0x00000000U
#define | LPTIM_TRIGSOURCE_1 LPTIM_CFGR_TRIGSEL_0
#define | LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1
#define | LPTIM_TRIGSOURCE_3 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
#define | LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2
#define | LPTIM_TRIGSOURCE_5 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
#define | LPTIM_TRIGSOURCE_6 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)
#define | LPTIM_TRIGSOURCE_7 LPTIM_CFGR_TRIGSEL

Define Documentation

#define LPTIM_TRIGSOURCE_0 0x00000000U

Definition at line 262 of file stm32wbxx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_1 LPTIM_CFGR_TRIGSEL_0

Definition at line 263 of file stm32wbxx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1

Definition at line 264 of file stm32wbxx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_3 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)

Definition at line 265 of file stm32wbxx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2

Definition at line 266 of file stm32wbxx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_5 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)

Definition at line 267 of file stm32wbxx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_6 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)

Definition at line 268 of file stm32wbxx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_7 LPTIM_CFGR_TRIGSEL

Definition at line 269 of file stm32wbxx_hal_lptim.h.

#define LPTIM_TRIGSOURCE_SOFTWARE 0x0000FFFFU

Definition at line 261 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPTIM External Trigger Polarity

Defines
LPTIM External Trigger Polarity
LPTIM Exported Constants

Defines

#define | LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0
#define | LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1
#define | LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN

Define Documentation

#define LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1

Definition at line 278 of file stm32wbxx_hal_lptim.h.

#define LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0

Definition at line 277 of file stm32wbxx_hal_lptim.h.

#define LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN

Definition at line 279 of file stm32wbxx_hal_lptim.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPTIM Trigger Sample Time

Defines
LPTIM Trigger Sample Time
LPTIM Exported Constants

Defines

#define | LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 0x00000000U
#define | LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0
#define | LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1
#define | LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT

Define Documentation

#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0

Definition at line 288 of file stm32wbxx_hal_lptim.h.

#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1

Definition at line 289 of file stm32wbxx_hal_lptim.h.

#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT

Definition at line 290 of file stm32wbxx_hal_lptim.h.

#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 0x00000000U

Definition at line 287 of file stm32wbxx_hal_lptim.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPTIM Updating Mode

Defines
LPTIM Updating Mode
LPTIM Exported Constants

Defines

#define | LPTIM_UPDATE_IMMEDIATE 0x00000000U
#define | LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD

Define Documentation

#define LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD

Definition at line 300 of file stm32wbxx_hal_lptim.h.

#define LPTIM_UPDATE_IMMEDIATE 0x00000000U

Definition at line 299 of file stm32wbxx_hal_lptim.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPTIM Counter Source

Defines
LPTIM Counter Source
LPTIM Exported Constants

Defines

#define | LPTIM_COUNTERSOURCE_INTERNAL 0x00000000U
#define | LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE

Define Documentation

#define LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE

Definition at line 310 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), and HAL_LPTIM_Init().

#define LPTIM_COUNTERSOURCE_INTERNAL 0x00000000U

Definition at line 309 of file stm32wbxx_hal_lptim.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPTIM Input1 Source

Defines
LPTIM Input1 Source
LPTIM Exported Constants

Defines

#define | LPTIM_INPUT1SOURCE_GPIO 0x00000000U
#define | LPTIM_INPUT1SOURCE_COMP1 LPTIM_OR_OR_0
#define | LPTIM_INPUT1SOURCE_COMP2 LPTIM_OR_OR_1
#define | LPTIM_INPUT1SOURCE_COMP1_COMP2 LPTIM_OR_OR

Define Documentation

#define LPTIM_INPUT1SOURCE_COMP1 LPTIM_OR_OR_0

For LPTIM1 and LPTIM2

Definition at line 320 of file stm32wbxx_hal_lptim.h.

#define LPTIM_INPUT1SOURCE_COMP1_COMP2 LPTIM_OR_OR

For LPTIM2

Definition at line 322 of file stm32wbxx_hal_lptim.h.

#define LPTIM_INPUT1SOURCE_COMP2 LPTIM_OR_OR_1

For LPTIM2

Definition at line 321 of file stm32wbxx_hal_lptim.h.

#define LPTIM_INPUT1SOURCE_GPIO 0x00000000U

For LPTIM1 and LPTIM2

Definition at line 319 of file stm32wbxx_hal_lptim.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPTIM Input2 Source

Defines
LPTIM Input2 Source
LPTIM Exported Constants

Defines

#define | LPTIM_INPUT2SOURCE_GPIO 0x00000000U
#define | LPTIM_INPUT2SOURCE_COMP2 LPTIM_OR_OR_1

Define Documentation

#define LPTIM_INPUT2SOURCE_COMP2 LPTIM_OR_OR_1

For LPTIM1

Definition at line 332 of file stm32wbxx_hal_lptim.h.

#define LPTIM_INPUT2SOURCE_GPIO 0x00000000U

For LPTIM1

Definition at line 331 of file stm32wbxx_hal_lptim.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPTIM Flags Definition

Defines
LPTIM Flags Definition
LPTIM Exported Constants

Defines

#define | LPTIM_FLAG_DOWN LPTIM_ISR_DOWN
#define | LPTIM_FLAG_UP LPTIM_ISR_UP
#define | LPTIM_FLAG_ARROK LPTIM_ISR_ARROK
#define | LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK
#define | LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG
#define | LPTIM_FLAG_ARRM LPTIM_ISR_ARRM
#define | LPTIM_FLAG_CMPM LPTIM_ISR_CMPM

Define Documentation

#define LPTIM_FLAG_ARRM LPTIM_ISR_ARRM

Definition at line 346 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_ARROK LPTIM_ISR_ARROK

Definition at line 343 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), and LPTIM_Disable().

#define LPTIM_FLAG_CMPM LPTIM_ISR_CMPM

Definition at line 347 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK

Definition at line 344 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), and LPTIM_Disable().

#define LPTIM_FLAG_DOWN LPTIM_ISR_DOWN

Definition at line 341 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG

Definition at line 345 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define LPTIM_FLAG_UP LPTIM_ISR_UP

Definition at line 342 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPTIM Interrupts Definition

Defines
LPTIM Interrupts Definition
LPTIM Exported Constants

Defines

#define | LPTIM_IT_DOWN LPTIM_IER_DOWNIE
#define | LPTIM_IT_UP LPTIM_IER_UPIE
#define | LPTIM_IT_ARROK LPTIM_IER_ARROKIE
#define | LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE
#define | LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE
#define | LPTIM_IT_ARRM LPTIM_IER_ARRMIE
#define | LPTIM_IT_CMPM LPTIM_IER_CMPMIE

Define Documentation

#define LPTIM_IT_ARRM LPTIM_IER_ARRMIE

Definition at line 360 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

#define LPTIM_IT_ARROK LPTIM_IER_ARROKIE

Definition at line 357 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

#define LPTIM_IT_CMPM LPTIM_IER_CMPMIE

Definition at line 361 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start_IT(), and HAL_LPTIM_TimeOut_Stop_IT().

#define LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE

Definition at line 358 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

#define LPTIM_IT_DOWN LPTIM_IER_DOWNIE

Definition at line 355 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop_IT(), and HAL_LPTIM_IRQHandler().

#define LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE

Definition at line 359 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_SetOnce_Stop_IT().

#define LPTIM_IT_UP LPTIM_IER_UPIE

Definition at line 356 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop_IT(), and HAL_LPTIM_IRQHandler().

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPTIM Exported Macros

Defines
LPTIM Exported Macros
LPTIM

Defines

#define | __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__)
Reset LPTIM handle state.
#define | __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
Enable the LPTIM peripheral.
#define | __HAL_LPTIM_DISABLE(__HANDLE__) LPTIM_Disable(__HANDLE__)
Disable the LPTIM peripheral.
#define | __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)
Start the LPTIM peripheral in Continuous mode.
#define | __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)
Start the LPTIM peripheral in single mode.
#define | __HAL_LPTIM_RESET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_COUNTRST)
Reset the LPTIM Counter register in synchronous mode.
#define | __HAL_LPTIM_RESET_COUNTER_AFTERREAD(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_RSTARE)
Reset after read of the LPTIM Counter register in asynchronous mode.
#define | __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
Write the passed parameter in the Autoreload register.
#define | __HAL_LPTIM_COMPARE_SET(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
Write the passed parameter in the Compare register.
#define | __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
Check whether the specified LPTIM flag is set or not.
#define | __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified LPTIM flag.
#define | __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enable the specified LPTIM interrupt.
#define | __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
Disable the specified LPTIM interrupt.
#define | __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified LPTIM interrupt source is enabled or not.
#define | __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() (EXTI->IMR1 |= LPTIM_EXTI_LINE_LPTIM1)
Enable the LPTIM1 EXTI line in interrupt mode.
#define | __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(LPTIM_EXTI_LINE_LPTIM1))
Disable the LPTIM1 EXTI line in interrupt mode.
#define | __HAL_LPTIM_LPTIM1_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= LPTIM_EXTI_LINE_LPTIM1)
Enable the LPTIM1 EXTI line in event mode.
#define | __HAL_LPTIM_LPTIM1_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(LPTIM_EXTI_LINE_LPTIM1))
Disable the LPTIM1 EXTI line in event mode.
#define | __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT() (EXTI->IMR1 |= LPTIM_EXTI_LINE_LPTIM2)
Enable the LPTIM2 EXTI line in interrupt mode.
#define | __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(LPTIM_EXTI_LINE_LPTIM2))
Disable the LPTIM2 EXTI line in interrupt mode.
#define | __HAL_LPTIM_LPTIM2_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= LPTIM_EXTI_LINE_LPTIM2)
Enable the LPTIM2 EXTI line in event mode.
#define | __HAL_LPTIM_LPTIM2_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(LPTIM_EXTI_LINE_LPTIM2))
Disable the LPTIM2 EXTI line in event mode.

Define Documentation

#define __HAL_LPTIM_AUTORELOAD_SET | ( | __HANDLE__,
 |  | __VALUE__
 | ) | ((__HANDLE__)->Instance->ARR = (__VALUE__))

Write the passed parameter in the Autoreload register.

Parameters:
__HANDLE__ | LPTIM handle
__VALUE__ | Autoreload value
Return values:
None
Note:
The ARR register can only be modified when the LPTIM instance is enabled.

Definition at line 442 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the specified LPTIM flag.

Parameters:
__HANDLE__ LPTIM handle.
__FLAG__ LPTIM flag to clear. This parameter can be a value of:
  • LPTIM_FLAG_DOWN : Counter direction change up Flag.
  • LPTIM_FLAG_UP : Counter direction change down to up Flag.
  • LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
  • LPTIM_FLAG_CMPOK : Compare register update OK Flag.
  • LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
  • LPTIM_FLAG_ARRM : Autoreload match Flag.
  • LPTIM_FLAG_CMPM : Compare match Flag.
Return values:
None.

Definition at line 483 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_IRQHandler(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), and LPTIM_Disable().

#define __HAL_LPTIM_COMPARE_SET | ( | __HANDLE__,
 |  | __VALUE__
 | ) | ((__HANDLE__)->Instance->CMP = (__VALUE__))

Write the passed parameter in the Compare register.

Parameters:
__HANDLE__ | LPTIM handle
__VALUE__ | Compare value
Return values:
None
Note:
The CMP register can only be modified when the LPTIM instance is enabled.

Definition at line 451 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_DISABLE ( __HANDLE__ ) LPTIM_Disable(__HANDLE__)

Disable the LPTIM peripheral.

Parameters:
__HANDLE__ LPTIM handle
Note:
The following sequence is required to solve LPTIM disable HW limitation. Please check Errata Sheet ES0335 for more details under "MCU may remain stuck in LPTIM interrupt when entering Stop mode" section.
Please call HAL_LPTIM_GetState() after a call to __HAL_LPTIM_DISABLE to check for TIMEOUT.
Return values:
None

Definition at line 406 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_DeInit(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop(), and HAL_LPTIM_TimeOut_Stop_IT().

#define __HAL_LPTIM_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))

Disable the specified LPTIM interrupt.

Parameters:
__HANDLE__ LPTIM handle.
__INTERRUPT__ LPTIM interrupt to set. This parameter can be a value of:
  • LPTIM_IT_DOWN : Counter direction change up Interrupt.
  • LPTIM_IT_UP : Counter direction change down to up Interrupt.
  • LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
  • LPTIM_IT_CMPOK : Compare register update OK Interrupt.
  • LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
  • LPTIM_IT_ARRM : Autoreload match Interrupt.
  • LPTIM_IT_CMPM : Compare match Interrupt.
Return values:
None.
Note:
The LPTIM interrupts can only be disabled when the LPTIM instance is disabled.

Definition at line 517 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_SetOnce_Stop_IT(), and HAL_LPTIM_TimeOut_Stop_IT().

#define __HAL_LPTIM_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))

Enable the LPTIM peripheral.

Parameters:
__HANDLE__ LPTIM handle
Return values:
None

Definition at line 394 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))

Enable the specified LPTIM interrupt.

Parameters:
__HANDLE__ LPTIM handle.
__INTERRUPT__ LPTIM interrupt to set. This parameter can be a value of:
  • LPTIM_IT_DOWN : Counter direction change up Interrupt.
  • LPTIM_IT_UP : Counter direction change down to up Interrupt.
  • LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
  • LPTIM_IT_CMPOK : Compare register update OK Interrupt.
  • LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
  • LPTIM_IT_ARRM : Autoreload match Interrupt.
  • LPTIM_IT_CMPM : Compare match Interrupt.
Return values:
None.
Note:
The LPTIM interrupts can only be enabled when the LPTIM instance is disabled.

Definition at line 500 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start_IT(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))

Check whether the specified LPTIM flag is set or not.

Parameters:
__HANDLE__ LPTIM handle
__FLAG__ LPTIM flag to check This parameter can be a value of:
  • LPTIM_FLAG_DOWN : Counter direction change up Flag.
  • LPTIM_FLAG_UP : Counter direction change down to up Flag.
  • LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
  • LPTIM_FLAG_CMPOK : Compare register update OK Flag.
  • LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
  • LPTIM_FLAG_ARRM : Autoreload match Flag.
  • LPTIM_FLAG_CMPM : Compare match Flag.
Return values:
The state of the specified flag (SET or RESET).

Definition at line 467 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler(), and LPTIM_WaitForFlag().

#define __HAL_LPTIM_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified LPTIM interrupt source is enabled or not.

Parameters:
__HANDLE__ LPTIM handle.
__INTERRUPT__ LPTIM interrupt to check. This parameter can be a value of:
  • LPTIM_IT_DOWN : Counter direction change up Interrupt.
  • LPTIM_IT_UP : Counter direction change down to up Interrupt.
  • LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
  • LPTIM_IT_CMPOK : Compare register update OK Interrupt.
  • LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
  • LPTIM_IT_ARRM : Autoreload match Interrupt.
  • LPTIM_IT_CMPM : Compare match Interrupt.
Return values:
Interrupt status.

Definition at line 534 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_IRQHandler().

#define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_EVENT ( ) (EXTI->EMR1 &= ~(LPTIM_EXTI_LINE_LPTIM1))

Disable the LPTIM1 EXTI line in event mode.

Return values:
None

Definition at line 559 of file stm32wbxx_hal_lptim.h.

#define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT ( ) (EXTI->IMR1 &= ~(LPTIM_EXTI_LINE_LPTIM1))

Disable the LPTIM1 EXTI line in interrupt mode.

Return values:
None

Definition at line 546 of file stm32wbxx_hal_lptim.h.

#define __HAL_LPTIM_LPTIM1_EXTI_ENABLE_EVENT ( ) (EXTI->EMR1 |= LPTIM_EXTI_LINE_LPTIM1)

Enable the LPTIM1 EXTI line in event mode.

Return values:
None

Definition at line 553 of file stm32wbxx_hal_lptim.h.

#define __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT ( ) (EXTI->IMR1 |= LPTIM_EXTI_LINE_LPTIM1)

Enable the LPTIM1 EXTI line in interrupt mode.

Return values:
None

Definition at line 540 of file stm32wbxx_hal_lptim.h.

#define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_EVENT ( ) (EXTI->EMR1 &= ~(LPTIM_EXTI_LINE_LPTIM2))

Disable the LPTIM2 EXTI line in event mode.

Return values:
None

Definition at line 584 of file stm32wbxx_hal_lptim.h.

#define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT ( ) (EXTI->IMR1 &= ~(LPTIM_EXTI_LINE_LPTIM2))

Disable the LPTIM2 EXTI line in interrupt mode.

Return values:
None

Definition at line 571 of file stm32wbxx_hal_lptim.h.

#define __HAL_LPTIM_LPTIM2_EXTI_ENABLE_EVENT ( ) (EXTI->EMR1 |= LPTIM_EXTI_LINE_LPTIM2)

Enable the LPTIM2 EXTI line in event mode.

Return values:
None

Definition at line 578 of file stm32wbxx_hal_lptim.h.

#define __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT ( ) (EXTI->IMR1 |= LPTIM_EXTI_LINE_LPTIM2)

Enable the LPTIM2 EXTI line in interrupt mode.

Return values:
None

Definition at line 565 of file stm32wbxx_hal_lptim.h.

#define __HAL_LPTIM_RESET_COUNTER ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= LPTIM_CR_COUNTRST)

Reset the LPTIM Counter register in synchronous mode.

Parameters:
__HANDLE__ LPTIM handle
Return values:
None

Definition at line 426 of file stm32wbxx_hal_lptim.h.

#define __HAL_LPTIM_RESET_COUNTER_AFTERREAD ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= LPTIM_CR_RSTARE)

Reset after read of the LPTIM Counter register in asynchronous mode.

Parameters:
__HANDLE__ LPTIM handle
Return values:
None

Definition at line 433 of file stm32wbxx_hal_lptim.h.

#define __HAL_LPTIM_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do {                                                        \
                                                      (__HANDLE__)->State             = HAL_LPTIM_STATE_RESET; \
                                                      (__HANDLE__)->MspInitCallback   = NULL;                  \
                                                      (__HANDLE__)->MspDeInitCallback = NULL;                  \
                                                     } while(0)

Reset LPTIM handle state.

Parameters:
__HANDLE__ LPTIM handle
Return values:
None

Definition at line 380 of file stm32wbxx_hal_lptim.h.

#define __HAL_LPTIM_START_CONTINUOUS ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)

Start the LPTIM peripheral in Continuous mode.

Parameters:
__HANDLE__ LPTIM handle
Return values:
None

Definition at line 413 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define __HAL_LPTIM_START_SINGLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)

Start the LPTIM peripheral in single mode.

Parameters:
__HANDLE__ LPTIM handle
Return values:
None

Definition at line 419 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_SetOnce_Start(), and HAL_LPTIM_SetOnce_Start_IT().

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPTIM Private Types

LPTIM Private Types
LPTIM
Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPTIM Private Variables

LPTIM Private Variables
LPTIM
Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPTIM Private Constants

LPTIM Private Constants
LPTIM
Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPTIM Private Macros

Defines
LPTIM Private Macros
LPTIM

Defines

#define | IS_LPTIM_CLOCK_SOURCE(__SOURCE__)
#define | IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__)
#define | IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)
#define | IS_LPTIM_OUTPUT_POLARITY(__POLARITY__)
#define | IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__)
#define | IS_LPTIM_CLOCK_POLARITY(__POLARITY__)
#define | IS_LPTIM_TRG_SOURCE(__TRIG__)
#define | IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__)
#define | IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__)
#define | IS_LPTIM_UPDATE_MODE(__MODE__)
#define | IS_LPTIM_COUNTER_SOURCE(__SOURCE__)
#define | IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFUL)
#define | IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL)
#define | IS_LPTIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0x0000FFFFUL)
#define | IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL)
#define | IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__)
#define | IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__)

Define Documentation

#define IS_LPTIM_AUTORELOAD ( __AUTORELOAD__ ) ((__AUTORELOAD__) <= 0x0000FFFFUL)

Definition at line 766 of file stm32wbxx_hal_lptim.h.

#define IS_LPTIM_CLOCK_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING)  || \
                                                 ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
                                                 ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))

Definition at line 737 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), and HAL_LPTIM_Init().

#define IS_LPTIM_CLOCK_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1  ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV2  ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV4  ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV8  ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV16 ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV32 ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV64 ) || \
                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV128))

Definition at line 718 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_CLOCK_PRESCALERDIV1 ( __PRESCALER__ ) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)

Definition at line 727 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), and HAL_LPTIM_Counter_Start_IT().

#define IS_LPTIM_CLOCK_SAMPLE_TIME ( __SAMPLETIME__ )
Value:
(((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
                                                    ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS)     || \
                                                    ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS)     || \
                                                    ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))

Definition at line 732 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_CLOCK_SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
                                                 ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))

Definition at line 714 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_COMPARE ( __COMPARE__ ) ((__COMPARE__) <= 0x0000FFFFUL)

Definition at line 768 of file stm32wbxx_hal_lptim.h.

#define IS_LPTIM_COUNTER_SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
                                                 ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))

Definition at line 763 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_EXT_TRG_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING         ) || \
                                                 ((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING        ) || \
                                                 ((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))

Definition at line 751 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_INPUT1_SOURCE | ( | __INSTANCE__,
 |  | __SOURCE__
 | ) |
Value:
((((__INSTANCE__) == LPTIM1) &&                       \
     (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) ||        \
      ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1)))        \
     ||                                                   \
     (((__INSTANCE__) == LPTIM2) &&                       \
     (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) ||        \
      ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) ||       \
      ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) ||       \
      ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2))))

Definition at line 774 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_INPUT2_SOURCE | ( | __INSTANCE__,
 |  | __SOURCE__
 | ) |
Value:
(((__INSTANCE__) == LPTIM1) &&                       \
     (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) ||        \
      ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2)))

Definition at line 785 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_OUTPUT_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \
                                                 ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))

Definition at line 729 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_PERIOD ( __PERIOD__ ) ((__PERIOD__) <= 0x0000FFFFUL)

Definition at line 770 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define IS_LPTIM_PULSE ( __PULSE__ ) ((__PULSE__) <= 0x0000FFFFUL)

Definition at line 772 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_TimeOut_Start(), and HAL_LPTIM_TimeOut_Start_IT().

#define IS_LPTIM_TRG_SOURCE ( __TRIG__ )
Value:
(((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_5) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_6) || \
                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_7))

Definition at line 741 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_TRIG_SAMPLE_TIME ( __SAMPLETIME__ )
Value:
(((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
                                                   ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS    ) || \
                                                   ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS    ) || \
                                                   ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS    ))

Definition at line 755 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

#define IS_LPTIM_UPDATE_MODE ( __MODE__ )
Value:
(((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
                                                 ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))

Definition at line 760 of file stm32wbxx_hal_lptim.h.

Referenced by HAL_LPTIM_Init().

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPTIM

Modules | Defines
LPTIM
STM32WBxx_HAL_Driver

LPTIM HAL module driver. More...

Modules

LPTIM Exported Functions
LPTIM Private Functions
LPTIM Exported Types
LPTIM Exported Constants
LPTIM Exported Macros
LPTIM Private Types
LPTIM Private Variables
LPTIM Private Constants
LPTIM Private Macros

Defines

#define TIMEOUT 1000UL /* Timeout is 1s */

Detailed Description

LPTIM HAL module driver.

Define Documentation

#define TIMEOUT 1000UL /* Timeout is 1s */

Definition at line 178 of file stm32wbxx_hal_lptim.c.

Referenced by LPTIM_WaitForFlag().

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PCD Private Macros

Defines
PCD Private Macros
PCD

Defines

#define | PCD_MIN(a, b) (((a) < (b)) ? (a) : (b))
#define | PCD_MAX(a, b) (((a) > (b)) ? (a) : (b))
#define | USB_CNTRX_NBLK_MSK (0x1FU << 10)
#define | USB_CNTRX_BLSIZE (0x1U << 15)
#define | PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue))
#define | PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))
#define | USB_EP0StartXfer USB_EPStartXfer
#define | PCD_SET_EPTYPE(USBx, bEpNum, wType)
sets the type in the endpoint register(bits EP_TYPE[1:0])
#define | PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)
gets the type in the endpoint register(bits EP_TYPE[1:0])
#define | PCD_FreeUserBuffer(USBx, bEpNum, bDir)
free buffer used from the application realizing it to the line toggles bit SW_BUF in the double buffered endpoint register
#define | PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState)
sets the status for tx transfer (bits STAT_TX[1:0]).
#define | PCD_SET_EP_RX_STATUS(USBx, bEpNum, wState)
sets the status for rx transfer (bits STAT_TX[1:0])
#define | PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx)
sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
#define | PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)
gets the status for tx/rx transfer (bits STAT_TX[1:0] /STAT_RX[1:0])
#define | PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)
#define | PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
sets directly the VALID tx/rx-status into the endpoint register
#define | PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
#define | PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum)
checks stall condition in an endpoint.
#define | PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum)
#define | PCD_SET_EP_KIND(USBx, bEpNum)
set & clear EP_KIND bit.
#define | PCD_CLEAR_EP_KIND(USBx, bEpNum)
#define | PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
Sets/clears directly STATUS_OUT bit in the endpoint register.
#define | PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
#define | PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
Sets/clears directly EP_KIND bit in the endpoint register.
#define | PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
#define | PCD_CLEAR_RX_EP_CTR(USBx, bEpNum)
Clears bit CTR_RX / CTR_TX in the endpoint register.
#define | PCD_CLEAR_TX_EP_CTR(USBx, bEpNum)
#define | PCD_RX_DTOG(USBx, bEpNum)
Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
#define | PCD_TX_DTOG(USBx, bEpNum)
#define | PCD_CLEAR_RX_DTOG(USBx, bEpNum)
Clears DTOG_RX / DTOG_TX bit in the endpoint register.
#define | PCD_CLEAR_TX_DTOG(USBx, bEpNum)
#define | PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr)
Sets address in an endpoint register.
#define | PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
Gets address in an endpoint register.
#define | PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
#define | PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
#define | PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr)
sets address of the tx/rx buffer.
#define | PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr)
#define | PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
Gets address of the tx/rx buffer.
#define | PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))
#define | PCD_CALC_BLK32(pdwReg, wCount, wNBlocks)
Sets counter of rx buffer with no.
#define | PCD_CALC_BLK2(pdwReg, wCount, wNBlocks)
#define | PCD_SET_EP_CNT_RX_REG(pdwReg, wCount)
#define | PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount)
#define | PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount)
sets counter for the tx/rx buffer.
#define | PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount)
#define | PCD_GET_EP_TX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU)
gets counter of the tx buffer.
#define | PCD_GET_EP_RX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU)
#define | PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr)
Sets buffer 0/1 address in a double buffer endpoint.
#define | PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr)
#define | PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr)
Sets addresses in a double buffer endpoint.
#define | PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
Gets buffer 0/1 address of a double buffer endpoint.
#define | PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
#define | PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount)
Gets buffer 0/1 address of a double buffer endpoint.
#define | PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount)
#define | PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount)
#define | PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
Gets buffer 0/1 rx/tx counter for double buffering.
#define | PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))

Define Documentation

#define PCD_CALC_BLK2 | ( | pdwReg,
 |  | wCount,
 |  | wNBlocks
 | ) |
Value:
do { \
    (wNBlocks) = (wCount) >> 1; \
    if (((wCount) & 0x1U) != 0U) \
    { \
      (wNBlocks)++; \
    } \
    *(pdwReg) = (uint16_t)((wNBlocks) << 10); \
  } while(0) /* PCD_CALC_BLK2 */

Definition at line 755 of file stm32wbxx_hal_pcd.h.

#define PCD_CALC_BLK32 | ( | pdwReg,
 |  | wCount,
 |  | wNBlocks
 | ) |
Value:
do { \
    (wNBlocks) = (wCount) >> 5; \
    *(pdwReg) = (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \
  } while(0) /* PCD_CALC_BLK32 */

Sets counter of rx buffer with no.

of blocks.

Parameters:
pdwReg | Register pointer
wCount | Counter.
wNBlocks | no. of Blocks.
Return values:
None

Definition at line 750 of file stm32wbxx_hal_pcd.h.

#define PCD_CLEAR_EP_DBUF | ( | USBx,
 |  | bEpNum
 | ) | PCD_CLEAR_EP_KIND((USBx), (bEpNum))

Definition at line 610 of file stm32wbxx_hal_pcd.h.

#define PCD_CLEAR_EP_KIND | ( | USBx,
 |  | bEpNum
 | ) |
Value:
do { \
    register uint16_t _wRegVal; \
    \
    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \
    \
    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
  } while(0) /* PCD_CLEAR_EP_KIND */

Definition at line 586 of file stm32wbxx_hal_pcd.h.

#define PCD_CLEAR_OUT_STATUS | ( | USBx,
 |  | bEpNum
 | ) | PCD_CLEAR_EP_KIND((USBx), (bEpNum))

Definition at line 601 of file stm32wbxx_hal_pcd.h.

#define PCD_CLEAR_RX_DTOG | ( | USBx,
 |  | bEpNum
 | ) |
Value:
do { \
    register uint16_t _wRegVal; \
    \
    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
    \
    if ((_wRegVal & USB_EP_DTOG_RX) != 0U)\
    { \
      PCD_RX_DTOG((USBx), (bEpNum)); \
    } \
  } while(0) /* PCD_CLEAR_RX_DTOG */

Clears DTOG_RX / DTOG_TX bit in the endpoint register.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
None

Definition at line 661 of file stm32wbxx_hal_pcd.h.

#define PCD_CLEAR_RX_EP_CTR | ( | USBx,
 |  | bEpNum
 | ) |
Value:
do { \
    register uint16_t _wRegVal; \
    \
    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \
    \
    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_TX)); \
  } while(0) /* PCD_CLEAR_RX_EP_CTR */

Clears bit CTR_RX / CTR_TX in the endpoint register.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
None

Definition at line 618 of file stm32wbxx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_CLEAR_TX_DTOG | ( | USBx,
 |  | bEpNum
 | ) |
Value:
do { \
    register uint16_t _wRegVal; \
    \
    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
    \
    if ((_wRegVal & USB_EP_DTOG_TX) != 0U)\
    { \
      PCD_TX_DTOG((USBx), (bEpNum)); \
    } \
  } while(0) /* PCD_CLEAR_TX_DTOG */

Definition at line 672 of file stm32wbxx_hal_pcd.h.

#define PCD_CLEAR_TX_EP_CTR | ( | USBx,
 |  | bEpNum
 | ) |
Value:
do { \
    register uint16_t _wRegVal; \
    \
    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \
    \
    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX)); \
  } while(0) /* PCD_CLEAR_TX_EP_CTR */

Definition at line 626 of file stm32wbxx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_EP_RX_CNT | ( | USBx,
 |  | bEpNum
 | ) | ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))

Definition at line 707 of file stm32wbxx_hal_pcd.h.

#define PCD_EP_TX_CNT | ( | USBx,
 |  | bEpNum
 | ) | ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))

Definition at line 706 of file stm32wbxx_hal_pcd.h.

#define PCD_FreeUserBuffer | ( | USBx,
 |  | bEpNum,
 |  | bDir
 | ) |
Value:
do { \
  if ((bDir) == 0U) \
  { \
    /* OUT double buffered endpoint */ \
    PCD_TX_DTOG((USBx), (bEpNum)); \
  } \
  else if ((bDir) == 1U) \
  { \
    /* IN double buffered endpoint */ \
    PCD_RX_DTOG((USBx), (bEpNum)); \
  } \
} while(0)

free buffer used from the application realizing it to the line toggles bit SW_BUF in the double buffered endpoint register

Parameters:
USBx USB device.
bEpNum,bDir
Return values:
None

Definition at line 445 of file stm32wbxx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_GET_ENDPOINT | ( | USBx,
 |  | bEpNum
 | ) | (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))

Definition at line 415 of file stm32wbxx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_GET_EP_ADDRESS | ( | USBx,
 |  | bEpNum
 | ) | ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))

Gets address in an endpoint register.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
None

Definition at line 704 of file stm32wbxx_hal_pcd.h.

#define PCD_GET_EP_DBUF0_ADDR | ( | USBx,
 |  | bEpNum
 | ) | (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))

Gets buffer 0/1 address of a double buffer endpoint.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
None

Definition at line 857 of file stm32wbxx_hal_pcd.h.

#define PCD_GET_EP_DBUF0_CNT | ( | USBx,
 |  | bEpNum
 | ) | (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))

Gets buffer 0/1 rx/tx counter for double buffering.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
None

Definition at line 917 of file stm32wbxx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_GET_EP_DBUF1_ADDR | ( | USBx,
 |  | bEpNum
 | ) | (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))

Definition at line 858 of file stm32wbxx_hal_pcd.h.

#define PCD_GET_EP_DBUF1_CNT | ( | USBx,
 |  | bEpNum
 | ) | (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))

Definition at line 918 of file stm32wbxx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_GET_EP_RX_ADDRESS | ( | USBx,
 |  | bEpNum
 | ) | ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))

Definition at line 741 of file stm32wbxx_hal_pcd.h.

#define PCD_GET_EP_RX_CNT | ( | USBx,
 |  | bEpNum
 | ) | ((uint32_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU)

Definition at line 822 of file stm32wbxx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_GET_EP_RX_STALL_STATUS | ( | USBx,
 |  | bEpNum
 | ) |
Value:
(PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \
                                   == USB_EP_RX_STALL)

Definition at line 569 of file stm32wbxx_hal_pcd.h.

#define PCD_GET_EP_RX_STATUS | ( | USBx,
 |  | bEpNum
 | ) | ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)

Definition at line 550 of file stm32wbxx_hal_pcd.h.

#define PCD_GET_EP_TX_ADDRESS | ( | USBx,
 |  | bEpNum
 | ) | ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))

Gets address of the tx/rx buffer.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
address of the buffer.

Definition at line 740 of file stm32wbxx_hal_pcd.h.

#define PCD_GET_EP_TX_CNT | ( | USBx,
 |  | bEpNum
 | ) | ((uint32_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU)

gets counter of the tx buffer.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
Counter value

Definition at line 821 of file stm32wbxx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_GET_EP_TX_STALL_STATUS | ( | USBx,
 |  | bEpNum
 | ) |
Value:
(PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \
                                   == USB_EP_TX_STALL)

checks stall condition in an endpoint.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
TRUE = endpoint in stall condition.

Definition at line 567 of file stm32wbxx_hal_pcd.h.

#define PCD_GET_EP_TX_STATUS | ( | USBx,
 |  | bEpNum
 | ) | ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)

gets the status for tx/rx transfer (bits STAT_TX[1:0] /STAT_RX[1:0])

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
status

Definition at line 549 of file stm32wbxx_hal_pcd.h.

#define PCD_GET_EPTYPE | ( | USBx,
 |  | bEpNum
 | ) | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)

gets the type in the endpoint register(bits EP_TYPE[1:0])

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
Endpoint Type

Definition at line 436 of file stm32wbxx_hal_pcd.h.

#define PCD_MAX | ( | a,
 |  | b
 | ) | (((a) > (b)) ? (a) : (b))

Definition at line 80 of file stm32wbxx_hal_pcd.c.

#define PCD_MIN | ( | a,
 |  | b
 | ) | (((a) < (b)) ? (a) : (b))

Definition at line 79 of file stm32wbxx_hal_pcd.c.

#define PCD_RX_DTOG | ( | USBx,
 |  | bEpNum
 | ) |
Value:
do { \
    register uint16_t _wEPVal; \
    \
    _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
    \
    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_RX)); \
  } while(0) /* PCD_RX_DTOG */

Toggles DTOG_RX / DTOG_TX bit in the endpoint register.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
None

Definition at line 640 of file stm32wbxx_hal_pcd.h.

#define PCD_SET_ENDPOINT | ( | USBx,
 |  | bEpNum,
 |  | wRegValue
 | ) | (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue))

Definition at line 412 of file stm32wbxx_hal_pcd.h.

#define PCD_SET_EP_ADDRESS | ( | USBx,
 |  | bEpNum,
 |  | bAddr
 | ) |
Value:
do { \
    register uint16_t _wRegVal; \
    \
    _wRegVal = (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \
    \
    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
  } while(0) /* PCD_SET_EP_ADDRESS */

Sets address in an endpoint register.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
bAddr | Address.
Return values:
None

Definition at line 690 of file stm32wbxx_hal_pcd.h.

#define PCD_SET_EP_CNT_RX_REG | ( | pdwReg,
 |  | wCount
 | ) |
Value:
do { \
    uint32_t wNBlocks; \
    if ((wCount) == 0U) \
    { \
      *(pdwReg) &= (uint16_t)~USB_CNTRX_NBLK_MSK; \
      *(pdwReg) |= USB_CNTRX_BLSIZE; \
    } \
    else if((wCount) < 62U) \
    { \
      PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
    } \
    else \
    { \
      PCD_CALC_BLK32((pdwReg),(wCount), wNBlocks); \
    } \
  } while(0) /* PCD_SET_EP_CNT_RX_REG */

Definition at line 764 of file stm32wbxx_hal_pcd.h.

#define PCD_SET_EP_DBUF | ( | USBx,
 |  | bEpNum
 | ) | PCD_SET_EP_KIND((USBx), (bEpNum))

Sets/clears directly EP_KIND bit in the endpoint register.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
None

Definition at line 609 of file stm32wbxx_hal_pcd.h.

#define PCD_SET_EP_DBUF0_ADDR | ( | USBx,
 |  | bEpNum,
 |  | wBuf0Addr
 | ) |
Value:
do { \
    PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)); \
  } while(0) /* PCD_SET_EP_DBUF0_ADDR */

Sets buffer 0/1 address in a double buffer endpoint.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
wBuf0Addr | buffer 0 address.
Return values:
Counter value

Definition at line 831 of file stm32wbxx_hal_pcd.h.

#define PCD_SET_EP_DBUF0_CNT | ( | USBx,
 |  | bEpNum,
 |  | bDir,
 |  | wCount
 | ) |
Value:
do { \
    if ((bDir) == 0U) \
      /* OUT endpoint */ \
    { \
      PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum), (wCount)); \
    } \
    else \
    { \
      if ((bDir) == 1U) \
      { \
        /* IN endpoint */ \
        PCD_SET_EP_TX_CNT((USBx), (bEpNum), (wCount)); \
      } \
    } \
  } while(0) /* SetEPDblBuf0Count*/

Gets buffer 0/1 address of a double buffer endpoint.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
bDir | endpoint dir EP_DBUF_OUT = OUT EP_DBUF_IN = IN
wCount,: Counter value
Return values:
None

Definition at line 869 of file stm32wbxx_hal_pcd.h.

#define PCD_SET_EP_DBUF1_ADDR | ( | USBx,
 |  | bEpNum,
 |  | wBuf1Addr
 | ) |
Value:
do { \
    PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)); \
  } while(0) /* PCD_SET_EP_DBUF1_ADDR */

Definition at line 834 of file stm32wbxx_hal_pcd.h.

#define PCD_SET_EP_DBUF1_CNT | ( | USBx,
 |  | bEpNum,
 |  | bDir,
 |  | wCount
 | ) |
Value:
do { \
    register uint32_t _wBase = (uint32_t)(USBx); \
    uint16_t *_wEPRegVal; \
    \
    if ((bDir) == 0U) \
    { \
      /* OUT endpoint */ \
      PCD_SET_EP_RX_CNT((USBx), (bEpNum), (wCount)); \
    } \
    else \
    { \
      if ((bDir) == 1U) \
      { \
        /* IN endpoint */ \
        _wBase += (uint32_t)(USBx)->BTABLE; \
        _wEPRegVal = (uint16_t *)(_wBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
        *_wEPRegVal = (uint16_t)(wCount); \
      } \
    } \
  } while(0) /* SetEPDblBuf1Count */

Definition at line 885 of file stm32wbxx_hal_pcd.h.

#define PCD_SET_EP_DBUF_ADDR | ( | USBx,
 |  | bEpNum,
 |  | wBuf0Addr,
 |  | wBuf1Addr
 | ) |
Value:
do { \
    PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr)); \
    PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr)); \
  } while(0) /* PCD_SET_EP_DBUF_ADDR */

Sets addresses in a double buffer endpoint.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
wBuf0Addr,: buffer 0 address.
wBuf1Addr | = buffer 1 address.
Return values:
None

Definition at line 846 of file stm32wbxx_hal_pcd.h.

#define PCD_SET_EP_DBUF_CNT | ( | USBx,
 |  | bEpNum,
 |  | bDir,
 |  | wCount
 | ) |
Value:
do { \
    PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
    PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
  } while(0) /* PCD_SET_EP_DBUF_CNT  */

Definition at line 906 of file stm32wbxx_hal_pcd.h.

#define PCD_SET_EP_KIND | ( | USBx,
 |  | bEpNum
 | ) |
Value:
do { \
    register uint16_t _wRegVal; \
    \
    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
    \
    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_KIND)); \
  } while(0) /* PCD_SET_EP_KIND */

set & clear EP_KIND bit.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
None

Definition at line 578 of file stm32wbxx_hal_pcd.h.

#define PCD_SET_EP_RX_ADDRESS | ( | USBx,
 |  | bEpNum,
 |  | wAddr
 | ) |
Value:
do { \
  register uint16_t *_wRegVal; \
  register uint32_t _wRegBase = (uint32_t)USBx; \
  \
  _wRegBase += (uint32_t)(USBx)->BTABLE; \
  _wRegVal = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \
  *_wRegVal = ((wAddr) >> 1) << 1; \
} while(0) /* PCD_SET_EP_RX_ADDRESS */

Definition at line 725 of file stm32wbxx_hal_pcd.h.

#define PCD_SET_EP_RX_CNT | ( | USBx,
 |  | bEpNum,
 |  | wCount
 | ) |
Value:
do { \
    register uint32_t _wRegBase = (uint32_t)(USBx); \
    uint16_t *_wRegVal; \
    \
    _wRegBase += (uint32_t)(USBx)->BTABLE; \
    _wRegVal = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
    PCD_SET_EP_CNT_RX_REG(_wRegVal, (wCount)); \
} while(0)

Definition at line 806 of file stm32wbxx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_SET_EP_RX_DBUF0_CNT | ( | USBx,
 |  | bEpNum,
 |  | wCount
 | ) |
Value:
do { \
     register uint32_t _wRegBase = (uint32_t)(USBx); \
     uint16_t *pdwReg; \
     \
    _wRegBase += (uint32_t)(USBx)->BTABLE; \
    pdwReg = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
    PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount)); \
  } while(0)

Definition at line 781 of file stm32wbxx_hal_pcd.h.

#define PCD_SET_EP_RX_STATUS | ( | USBx,
 |  | bEpNum,
 |  | wState
 | ) |
Value:
do { \
    register uint16_t _wRegVal; \
    \
    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \
    /* toggle first bit ? */ \
    if ((USB_EPRX_DTOG1 & (wState))!= 0U) \
    { \
       _wRegVal ^= USB_EPRX_DTOG1; \
    } \
    /* toggle second bit ? */ \
    if ((USB_EPRX_DTOG2 & (wState))!= 0U) \
    { \
       _wRegVal ^= USB_EPRX_DTOG2; \
    } \
    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
  } while(0) /* PCD_SET_EP_RX_STATUS */

sets the status for rx transfer (bits STAT_TX[1:0])

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
wState | new state
Return values:
None

Definition at line 489 of file stm32wbxx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_SET_EP_RX_VALID | ( | USBx,
 |  | bEpNum
 | ) | (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))

Definition at line 559 of file stm32wbxx_hal_pcd.h.

#define PCD_SET_EP_TX_ADDRESS | ( | USBx,
 |  | bEpNum,
 |  | wAddr
 | ) |
Value:
do { \
  register uint16_t *_wRegVal; \
  register uint32_t _wRegBase = (uint32_t)USBx; \
  \
  _wRegBase += (uint32_t)(USBx)->BTABLE; \
  _wRegVal = (uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \
  *_wRegVal = ((wAddr) >> 1) << 1; \
} while(0) /* PCD_SET_EP_TX_ADDRESS */

sets address of the tx/rx buffer.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
wAddr | address to be set (must be word aligned).
Return values:
None

Definition at line 716 of file stm32wbxx_hal_pcd.h.

#define PCD_SET_EP_TX_CNT | ( | USBx,
 |  | bEpNum,
 |  | wCount
 | ) |
Value:
do { \
    register uint32_t _wRegBase = (uint32_t)(USBx); \
    uint16_t *_wRegVal; \
    \
    _wRegBase += (uint32_t)(USBx)->BTABLE; \
    _wRegVal = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
    *_wRegVal = (uint16_t)(wCount); \
} while(0)

sets counter for the tx/rx buffer.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
wCount | Counter value.
Return values:
None

Definition at line 797 of file stm32wbxx_hal_pcd.h.

#define PCD_SET_EP_TX_STATUS | ( | USBx,
 |  | bEpNum,
 |  | wState
 | ) |
Value:
do { \
   register uint16_t _wRegVal; \
   \
    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \
   /* toggle first bit ? */ \
   if ((USB_EPTX_DTOG1 & (wState))!= 0U) \
   { \
      _wRegVal ^= USB_EPTX_DTOG1; \
   } \
   /* toggle second bit ?  */ \
   if ((USB_EPTX_DTOG2 & (wState))!= 0U) \
   { \
      _wRegVal ^= USB_EPTX_DTOG2; \
   } \
   PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
  } while(0) /* PCD_SET_EP_TX_STATUS */

sets the status for tx transfer (bits STAT_TX[1:0]).

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
wState | new state
Return values:
None

Definition at line 465 of file stm32wbxx_hal_pcd.h.

#define PCD_SET_EP_TX_VALID | ( | USBx,
 |  | bEpNum
 | ) | (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))

sets directly the VALID tx/rx-status into the endpoint register

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
None

Definition at line 558 of file stm32wbxx_hal_pcd.h.

#define PCD_SET_EP_TXRX_STATUS | ( | USBx,
 |  | bEpNum,
 |  | wStaterx,
 |  | wStatetx
 | ) |
Value:
do { \
    register uint16_t _wRegVal; \
    \
    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \
    /* toggle first bit ? */ \
    if ((USB_EPRX_DTOG1 & (wStaterx))!= 0U) \
    { \
      _wRegVal ^= USB_EPRX_DTOG1; \
    } \
    /* toggle second bit ? */ \
    if ((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \
    { \
      _wRegVal ^= USB_EPRX_DTOG2; \
    } \
    /* toggle first bit ? */ \
    if ((USB_EPTX_DTOG1 & (wStatetx))!= 0U) \
    { \
      _wRegVal ^= USB_EPTX_DTOG1; \
    } \
    /* toggle second bit ?  */ \
    if ((USB_EPTX_DTOG2 & (wStatetx))!= 0U) \
    { \
      _wRegVal ^= USB_EPTX_DTOG2; \
    } \
    \
    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
  } while(0) /* PCD_SET_EP_TXRX_STATUS */

sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
wStaterx | new state.
wStatetx | new state.
Return values:
None

Definition at line 514 of file stm32wbxx_hal_pcd.h.

#define PCD_SET_EPTYPE | ( | USBx,
 |  | bEpNum,
 |  | wType
 | ) |
Value:
(PCD_SET_ENDPOINT((USBx), (bEpNum), \
                                             ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))

sets the type in the endpoint register(bits EP_TYPE[1:0])

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
wType | Endpoint Type.
Return values:
None

Definition at line 427 of file stm32wbxx_hal_pcd.h.

#define PCD_SET_OUT_STATUS | ( | USBx,
 |  | bEpNum
 | ) | PCD_SET_EP_KIND((USBx), (bEpNum))

Sets/clears directly STATUS_OUT bit in the endpoint register.

Parameters:
USBx | USB peripheral instance register address.
bEpNum | Endpoint Number.
Return values:
None

Definition at line 600 of file stm32wbxx_hal_pcd.h.

#define PCD_TX_DTOG | ( | USBx,
 |  | bEpNum
 | ) |
Value:
do { \
    register uint16_t _wEPVal; \
    \
    _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
    \
    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_TX)); \
  } while(0) /* PCD_TX_DTOG */

Definition at line 648 of file stm32wbxx_hal_pcd.h.

#define USB_CNTRX_BLSIZE (0x1U << 15)

Definition at line 409 of file stm32wbxx_hal_pcd.h.

#define USB_CNTRX_NBLK_MSK (0x1FU << 10)

Definition at line 408 of file stm32wbxx_hal_pcd.h.

#define USB_EP0StartXfer USB_EPStartXfer

Definition at line 418 of file stm32wbxx_hal_pcd.h.

Referenced by HAL_PCD_EP_Receive(), and HAL_PCD_EP_Transmit().

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PCD Private Functions

Functions
PCD Private Functions
PCD

Functions

static HAL_StatusTypeDef PCD_EP_ISR_Handler (PCD_HandleTypeDef *hpcd)
This function handles PCD Endpoint interrupt request.

Function Documentation

static HAL_StatusTypeDef PCD_EP_ISR_Handler ( PCD_HandleTypeDef * hpcd ) [static]

This function handles PCD Endpoint interrupt request.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 1659 of file stm32wbxx_hal_pcd.c.

References __PCD_HandleTypeDef::DataInStageCallback, __PCD_HandleTypeDef::DataOutStageCallback, HAL_PCD_DataInStageCallback(), HAL_PCD_DataOutStageCallback(), HAL_PCD_EP_Receive(), HAL_PCD_EP_Transmit(), HAL_PCD_SetupStageCallback(), __PCD_HandleTypeDef::IN_ep, __PCD_HandleTypeDef::Instance, __PCD_HandleTypeDef::OUT_ep, PCD_CLEAR_RX_EP_CTR, PCD_CLEAR_TX_EP_CTR, PCD_ENDP0, PCD_FreeUserBuffer, PCD_GET_ENDPOINT, PCD_GET_EP_DBUF0_CNT, PCD_GET_EP_DBUF1_CNT, PCD_GET_EP_RX_CNT, PCD_GET_EP_TX_CNT, PCD_SET_EP_RX_CNT, PCD_SET_EP_RX_STATUS, __PCD_HandleTypeDef::Setup, __PCD_HandleTypeDef::SetupStageCallback, and __PCD_HandleTypeDef::USB_Address.

Referenced by HAL_PCD_IRQHandler().

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: HAL USB OTG PCD Callback ID enumeration definition

Enumerations
HAL USB OTG PCD Callback ID enumeration definition
Initialization and de-initialization functions

HAL USB OTG PCD Callback ID enumeration definition. More...

Enumerations

enum HAL_PCD_CallbackIDTypeDef {
HAL_PCD_SOF_CB_ID = 0x01, HAL_PCD_SETUPSTAGE_CB_ID = 0x02, HAL_PCD_RESET_CB_ID = 0x03, HAL_PCD_SUSPEND_CB_ID = 0x04,
HAL_PCD_RESUME_CB_ID = 0x05, HAL_PCD_CONNECT_CB_ID = 0x06, HAL_PCD_DISCONNECT_CB_ID = 0x07, HAL_PCD_MSPINIT_CB_ID = 0x08,
HAL_PCD_MSPDEINIT_CB_ID = 0x09
}

Detailed Description

HAL USB OTG PCD Callback ID enumeration definition.

Enumeration Type Documentation

enum HAL_PCD_CallbackIDTypeDef
Enumerator:
HAL_PCD_SOF_CB_ID

USB PCD SOF callback ID

HAL_PCD_SETUPSTAGE_CB_ID

USB PCD Setup Stage callback ID

HAL_PCD_RESET_CB_ID

USB PCD Reset callback ID

HAL_PCD_SUSPEND_CB_ID

USB PCD Suspend callback ID

HAL_PCD_RESUME_CB_ID

USB PCD Resume callback ID

HAL_PCD_CONNECT_CB_ID

USB PCD Connect callback ID

HAL_PCD_DISCONNECT_CB_ID

USB PCD Disconnect callback ID

HAL_PCD_MSPINIT_CB_ID

USB PCD MspInit callback ID

HAL_PCD_MSPDEINIT_CB_ID

USB PCD MspDeInit callback ID

Definition at line 228 of file stm32wbxx_hal_pcd.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: HAL USB OTG PCD Callback pointer definition

Typedefs
HAL USB OTG PCD Callback pointer definition
Initialization and de-initialization functions

HAL USB OTG PCD Callback pointer definition. More...

Typedefs

typedef void(* | pPCD_CallbackTypeDef )(PCD_HandleTypeDef *hpcd)
typedef void(* | pPCD_DataOutStageCallbackTypeDef )(PCD_HandleTypeDef *hpcd, uint8_t epnum)
typedef void(* | pPCD_DataInStageCallbackTypeDef )(PCD_HandleTypeDef *hpcd, uint8_t epnum)
typedef void(* | pPCD_IsoOutIncpltCallbackTypeDef )(PCD_HandleTypeDef *hpcd, uint8_t epnum)
typedef void(* | pPCD_IsoInIncpltCallbackTypeDef )(PCD_HandleTypeDef *hpcd, uint8_t epnum)
typedef void(* | pPCD_LpmCallbackTypeDef )(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
typedef void(* | pPCD_BcdCallbackTypeDef )(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)

Detailed Description

HAL USB OTG PCD Callback pointer definition.

Typedef Documentation

typedef void(* pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)

pointer to USB OTG PCD BCD callback

Definition at line 257 of file stm32wbxx_hal_pcd.h.

typedef void(* pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd)

pointer to a common USB OTG PCD callback function

Definition at line 251 of file stm32wbxx_hal_pcd.h.

typedef void(* pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum)

pointer to USB OTG PCD Data IN Stage callback

Definition at line 253 of file stm32wbxx_hal_pcd.h.

typedef void(* pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum)

pointer to USB OTG PCD Data OUT Stage callback

Definition at line 252 of file stm32wbxx_hal_pcd.h.

typedef void(* pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum)

pointer to USB OTG PCD ISO IN Incomplete callback

Definition at line 255 of file stm32wbxx_hal_pcd.h.

typedef void(* pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum)

pointer to USB OTG PCD ISO OUT Incomplete callback

Definition at line 254 of file stm32wbxx_hal_pcd.h.

typedef void(* pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)

pointer to USB OTG PCD LPM callback

Definition at line 256 of file stm32wbxx_hal_pcd.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization and de-initialization functions

Modules | Functions
Initialization and de-initialization functions
PCD Exported Functions

Initialization and Configuration functions. More...

Modules

HAL USB OTG PCD Callback ID enumeration definition

HAL USB OTG PCD Callback ID enumeration definition.

HAL USB OTG PCD Callback pointer definition

HAL USB OTG PCD Callback pointer definition.

Functions

HAL_StatusTypeDef | HAL_PCD_Init (PCD_HandleTypeDef *hpcd)
Initializes the PCD according to the specified parameters in the PCD_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd)
DeInitializes the PCD peripheral.
__weak void | HAL_PCD_MspInit (PCD_HandleTypeDef *hpcd)
Initializes the PCD MSP.
__weak void | HAL_PCD_MspDeInit (PCD_HandleTypeDef *hpcd)
DeInitializes PCD MSP.
HAL_StatusTypeDef | HAL_PCD_RegisterCallback (PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback)
Register a User USB PCD Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterCallback (PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID)
Unregister an USB PCD Callback USB PCD callabck is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterDataOutStageCallback (PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback)
Register USB PCD Data OUT Stage Callback To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterDataOutStageCallback (PCD_HandleTypeDef *hpcd)
UnRegister the USB PCD Data OUT Stage Callback USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterDataInStageCallback (PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback)
Register USB PCD Data IN Stage Callback To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterDataInStageCallback (PCD_HandleTypeDef *hpcd)
UnRegister the USB PCD Data IN Stage Callback USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterIsoOutIncpltCallback (PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback)
Register USB PCD Iso OUT incomplete Callback To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterIsoOutIncpltCallback (PCD_HandleTypeDef *hpcd)
UnRegister the USB PCD Iso OUT incomplete Callback USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterIsoInIncpltCallback (PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback)
Register USB PCD Iso IN incomplete Callback To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterIsoInIncpltCallback (PCD_HandleTypeDef *hpcd)
UnRegister the USB PCD Iso IN incomplete Callback USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterBcdCallback (PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback)
Register USB PCD BCD Callback To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterBcdCallback (PCD_HandleTypeDef *hpcd)
UnRegister the USB PCD BCD Callback USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterLpmCallback (PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback)
Register USB PCD LPM Callback To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterLpmCallback (PCD_HandleTypeDef *hpcd)
UnRegister the USB PCD LPM Callback USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
            ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:

Function Documentation

HAL_StatusTypeDef HAL_PCD_DeInit ( PCD_HandleTypeDef * hpcd )

DeInitializes the PCD peripheral.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 216 of file stm32wbxx_hal_pcd.c.

References HAL_PCD_MspDeInit(), HAL_PCD_STATE_BUSY, HAL_PCD_STATE_RESET, HAL_PCD_Stop(), __PCD_HandleTypeDef::MspDeInitCallback, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_Init ( PCD_HandleTypeDef * hpcd )

Initializes the PCD according to the specified parameters in the PCD_InitTypeDef and initialize the associated handle.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 120 of file stm32wbxx_hal_pcd.c.

References __HAL_PCD_DISABLE, assert_param, __PCD_HandleTypeDef::BCDCallback, __PCD_HandleTypeDef::ConnectCallback, __PCD_HandleTypeDef::DataInStageCallback, __PCD_HandleTypeDef::DataOutStageCallback, __PCD_HandleTypeDef::DisconnectCallback, HAL_PCD_ConnectCallback(), HAL_PCD_DataInStageCallback(), HAL_PCD_DataOutStageCallback(), HAL_PCD_DisconnectCallback(), HAL_PCD_ISOINIncompleteCallback(), HAL_PCD_ISOOUTIncompleteCallback(), HAL_PCD_MspInit(), HAL_PCD_ResetCallback(), HAL_PCD_ResumeCallback(), HAL_PCD_SetupStageCallback(), HAL_PCD_SOFCallback(), HAL_PCD_STATE_BUSY, HAL_PCD_STATE_READY, HAL_PCD_STATE_RESET, HAL_PCD_SuspendCallback(), HAL_PCDEx_ActivateLPM(), HAL_PCDEx_BCD_Callback(), HAL_PCDEx_LPM_Callback(), __PCD_HandleTypeDef::IN_ep, __PCD_HandleTypeDef::Init, __PCD_HandleTypeDef::Instance, __PCD_HandleTypeDef::ISOINIncompleteCallback, __PCD_HandleTypeDef::ISOOUTIncompleteCallback, __PCD_HandleTypeDef::Lock, __PCD_HandleTypeDef::LPMCallback, __PCD_HandleTypeDef::MspInitCallback, __PCD_HandleTypeDef::OUT_ep, __PCD_HandleTypeDef::ResetCallback, __PCD_HandleTypeDef::ResumeCallback, __PCD_HandleTypeDef::SetupStageCallback, __PCD_HandleTypeDef::SOFCallback, __PCD_HandleTypeDef::State, __PCD_HandleTypeDef::SuspendCallback, and __PCD_HandleTypeDef::USB_Address.

void HAL_PCD_MspDeInit ( PCD_HandleTypeDef * hpcd )

DeInitializes PCD MSP.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 267 of file stm32wbxx_hal_pcd.c.

Referenced by HAL_PCD_DeInit(), and HAL_PCD_UnRegisterCallback().

void HAL_PCD_MspInit ( PCD_HandleTypeDef * hpcd )

Initializes the PCD MSP.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 252 of file stm32wbxx_hal_pcd.c.

Referenced by HAL_PCD_Init(), and HAL_PCD_UnRegisterCallback().

HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | pPCD_BcdCallbackTypeDef | pCallback
 | ) |  |

Register USB PCD BCD Callback To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback.

Parameters:
hpcd | PCD handle
pCallback | pointer to the USB PCD BCD Callback function
Return values:
HAL status

Definition at line 798 of file stm32wbxx_hal_pcd.c.

References __PCD_HandleTypeDef::BCDCallback, __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_RegisterCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | HAL_PCD_CallbackIDTypeDef | CallbackID,
 |  | pPCD_CallbackTypeDef | pCallback
 | ) |  |

Register a User USB PCD Callback To be used instead of the weak predefined callback.

Parameters:
hpcd | USB PCD handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
  • HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
  • HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
  • HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
  • HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
  • HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
  • HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
  • HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
  • HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 296 of file stm32wbxx_hal_pcd.c.

References __PCD_HandleTypeDef::ConnectCallback, __PCD_HandleTypeDef::DisconnectCallback, __PCD_HandleTypeDef::ErrorCode, HAL_PCD_CONNECT_CB_ID, HAL_PCD_DISCONNECT_CB_ID, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_MSPDEINIT_CB_ID, HAL_PCD_MSPINIT_CB_ID, HAL_PCD_RESET_CB_ID, HAL_PCD_RESUME_CB_ID, HAL_PCD_SETUPSTAGE_CB_ID, HAL_PCD_SOF_CB_ID, HAL_PCD_STATE_READY, HAL_PCD_STATE_RESET, HAL_PCD_SUSPEND_CB_ID, __PCD_HandleTypeDef::MspDeInitCallback, __PCD_HandleTypeDef::MspInitCallback, __PCD_HandleTypeDef::ResetCallback, __PCD_HandleTypeDef::ResumeCallback, __PCD_HandleTypeDef::SetupStageCallback, __PCD_HandleTypeDef::SOFCallback, __PCD_HandleTypeDef::State, and __PCD_HandleTypeDef::SuspendCallback.

HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | pPCD_DataInStageCallbackTypeDef | pCallback
 | ) |  |

Register USB PCD Data IN Stage Callback To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback.

Parameters:
hpcd | PCD handle
pCallback | pointer to the USB PCD Data IN Stage Callback function
Return values:
HAL status

Definition at line 579 of file stm32wbxx_hal_pcd.c.

References __PCD_HandleTypeDef::DataInStageCallback, __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | pPCD_DataOutStageCallbackTypeDef | pCallback
 | ) |  |

Register USB PCD Data OUT Stage Callback To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback.

Parameters:
hpcd | PCD handle
pCallback | pointer to the USB PCD Data OUT Stage Callback function
Return values:
HAL status

Definition at line 506 of file stm32wbxx_hal_pcd.c.

References __PCD_HandleTypeDef::DataOutStageCallback, __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | pPCD_IsoInIncpltCallbackTypeDef | pCallback
 | ) |  |

Register USB PCD Iso IN incomplete Callback To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback.

Parameters:
hpcd | PCD handle
pCallback | pointer to the USB PCD Iso IN incomplete Callback function
Return values:
HAL status

Definition at line 725 of file stm32wbxx_hal_pcd.c.

References __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, __PCD_HandleTypeDef::ISOINIncompleteCallback, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | pPCD_IsoOutIncpltCallbackTypeDef | pCallback
 | ) |  |

Register USB PCD Iso OUT incomplete Callback To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback.

Parameters:
hpcd | PCD handle
pCallback | pointer to the USB PCD Iso OUT incomplete Callback function
Return values:
HAL status

Definition at line 652 of file stm32wbxx_hal_pcd.c.

References __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, __PCD_HandleTypeDef::ISOOUTIncompleteCallback, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | pPCD_LpmCallbackTypeDef | pCallback
 | ) |  |

Register USB PCD LPM Callback To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback.

Parameters:
hpcd | PCD handle
pCallback | pointer to the USB PCD LPM Callback function
Return values:
HAL status

Definition at line 871 of file stm32wbxx_hal_pcd.c.

References __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, __PCD_HandleTypeDef::LPMCallback, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback ( PCD_HandleTypeDef * hpcd )

UnRegister the USB PCD BCD Callback USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 838 of file stm32wbxx_hal_pcd.c.

References __PCD_HandleTypeDef::BCDCallback, __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, HAL_PCDEx_BCD_Callback(), and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_UnRegisterCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | HAL_PCD_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an USB PCD Callback USB PCD callabck is redirected to the weak predefined callback.

Parameters:
hpcd USB PCD handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
  • HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
  • HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
  • HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
  • HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
  • HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
  • HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
  • HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
  • HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
HAL status

Definition at line 407 of file stm32wbxx_hal_pcd.c.

References __PCD_HandleTypeDef::ConnectCallback, __PCD_HandleTypeDef::DisconnectCallback, __PCD_HandleTypeDef::ErrorCode, HAL_PCD_CONNECT_CB_ID, HAL_PCD_ConnectCallback(), HAL_PCD_DISCONNECT_CB_ID, HAL_PCD_DisconnectCallback(), HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_MspDeInit(), HAL_PCD_MSPDEINIT_CB_ID, HAL_PCD_MspInit(), HAL_PCD_MSPINIT_CB_ID, HAL_PCD_RESET_CB_ID, HAL_PCD_ResetCallback(), HAL_PCD_RESUME_CB_ID, HAL_PCD_ResumeCallback(), HAL_PCD_SETUPSTAGE_CB_ID, HAL_PCD_SetupStageCallback(), HAL_PCD_SOF_CB_ID, HAL_PCD_SOFCallback(), HAL_PCD_STATE_READY, HAL_PCD_STATE_RESET, HAL_PCD_SUSPEND_CB_ID, HAL_PCD_SuspendCallback(), __PCD_HandleTypeDef::MspDeInitCallback, __PCD_HandleTypeDef::MspInitCallback, __PCD_HandleTypeDef::ResetCallback, __PCD_HandleTypeDef::ResumeCallback, __PCD_HandleTypeDef::SetupStageCallback, __PCD_HandleTypeDef::SOFCallback, __PCD_HandleTypeDef::State, and __PCD_HandleTypeDef::SuspendCallback.

HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback ( PCD_HandleTypeDef * hpcd )

UnRegister the USB PCD Data IN Stage Callback USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 619 of file stm32wbxx_hal_pcd.c.

References __PCD_HandleTypeDef::DataInStageCallback, __PCD_HandleTypeDef::ErrorCode, HAL_PCD_DataInStageCallback(), HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback ( PCD_HandleTypeDef * hpcd )

UnRegister the USB PCD Data OUT Stage Callback USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 546 of file stm32wbxx_hal_pcd.c.

References __PCD_HandleTypeDef::DataOutStageCallback, __PCD_HandleTypeDef::ErrorCode, HAL_PCD_DataOutStageCallback(), HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback ( PCD_HandleTypeDef * hpcd )

UnRegister the USB PCD Iso IN incomplete Callback USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 765 of file stm32wbxx_hal_pcd.c.

References __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_ISOINIncompleteCallback(), HAL_PCD_STATE_READY, __PCD_HandleTypeDef::ISOINIncompleteCallback, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback ( PCD_HandleTypeDef * hpcd )

UnRegister the USB PCD Iso OUT incomplete Callback USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 692 of file stm32wbxx_hal_pcd.c.

References __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_ISOOUTIncompleteCallback(), HAL_PCD_STATE_READY, __PCD_HandleTypeDef::ISOOUTIncompleteCallback, and __PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback ( PCD_HandleTypeDef * hpcd )

UnRegister the USB PCD LPM Callback USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 911 of file stm32wbxx_hal_pcd.c.

References __PCD_HandleTypeDef::ErrorCode, HAL_PCD_ERROR_INVALID_CALLBACK, HAL_PCD_STATE_READY, HAL_PCDEx_LPM_Callback(), __PCD_HandleTypeDef::LPMCallback, and __PCD_HandleTypeDef::State.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
PCD Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_PCD_Start (PCD_HandleTypeDef *hpcd)
Start the USB device.
HAL_StatusTypeDef | HAL_PCD_Stop (PCD_HandleTypeDef *hpcd)
Stop the USB device.
void | HAL_PCD_IRQHandler (PCD_HandleTypeDef *hpcd)
This function handles PCD interrupt request.
__weak void | HAL_PCD_DataOutStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data OUT stage callback.
__weak void | HAL_PCD_DataInStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data IN stage callback.
__weak void | HAL_PCD_SetupStageCallback (PCD_HandleTypeDef *hpcd)
Setup stage callback.
__weak void | HAL_PCD_SOFCallback (PCD_HandleTypeDef *hpcd)
USB Start Of Frame callback.
__weak void | HAL_PCD_ResetCallback (PCD_HandleTypeDef *hpcd)
USB Reset callback.
__weak void | HAL_PCD_SuspendCallback (PCD_HandleTypeDef *hpcd)
Suspend event callback.
__weak void | HAL_PCD_ResumeCallback (PCD_HandleTypeDef *hpcd)
Resume event callback.
__weak void | HAL_PCD_ISOOUTIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO OUT callback.
__weak void | HAL_PCD_ISOINIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO IN callback.
__weak void | HAL_PCD_ConnectCallback (PCD_HandleTypeDef *hpcd)
Connection event callback.
__weak void | HAL_PCD_DisconnectCallback (PCD_HandleTypeDef *hpcd)
Disconnection event callback.

Detailed Description

Data transfers functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the PCD data
    transfers.

Function Documentation

void HAL_PCD_ConnectCallback ( PCD_HandleTypeDef * hpcd )

Connection event callback.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 1264 of file stm32wbxx_hal_pcd.c.

Referenced by HAL_PCD_Init(), and HAL_PCD_UnRegisterCallback().

void HAL_PCD_DataInStageCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | epnum
 | ) |  |

Data IN stage callback.

Parameters:
hpcd | PCD handle
epnum | endpoint number
Return values:
None

Definition at line 1140 of file stm32wbxx_hal_pcd.c.

Referenced by HAL_PCD_Init(), HAL_PCD_UnRegisterDataInStageCallback(), and PCD_EP_ISR_Handler().

void HAL_PCD_DataOutStageCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | epnum
 | ) |  |

Data OUT stage callback.

Parameters:
hpcd | PCD handle
epnum | endpoint number
Return values:
None

Definition at line 1123 of file stm32wbxx_hal_pcd.c.

Referenced by HAL_PCD_Init(), HAL_PCD_UnRegisterDataOutStageCallback(), and PCD_EP_ISR_Handler().

void HAL_PCD_DisconnectCallback ( PCD_HandleTypeDef * hpcd )

Disconnection event callback.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 1279 of file stm32wbxx_hal_pcd.c.

Referenced by HAL_PCD_Init(), and HAL_PCD_UnRegisterCallback().

void HAL_PCD_IRQHandler ( PCD_HandleTypeDef * hpcd )

This function handles PCD interrupt request.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 994 of file stm32wbxx_hal_pcd.c.

References __HAL_PCD_CLEAR_FLAG, __HAL_PCD_GET_FLAG, __PCD_HandleTypeDef::BESL, HAL_PCD_ResetCallback(), HAL_PCD_ResumeCallback(), HAL_PCD_SetAddress(), HAL_PCD_SOFCallback(), HAL_PCD_SuspendCallback(), HAL_PCDEx_LPM_Callback(), __PCD_HandleTypeDef::Instance, LPM_L0, LPM_L1, __PCD_HandleTypeDef::LPM_State, __PCD_HandleTypeDef::LPMCallback, PCD_EP_ISR_Handler(), PCD_LPM_L0_ACTIVE, PCD_LPM_L1_ACTIVE, __PCD_HandleTypeDef::ResetCallback, __PCD_HandleTypeDef::ResumeCallback, __PCD_HandleTypeDef::SOFCallback, and __PCD_HandleTypeDef::SuspendCallback.

void HAL_PCD_ISOINIncompleteCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | epnum
 | ) |  |

Incomplete ISO IN callback.

Parameters:
hpcd | PCD handle
epnum | endpoint number
Return values:
None

Definition at line 1248 of file stm32wbxx_hal_pcd.c.

Referenced by HAL_PCD_Init(), and HAL_PCD_UnRegisterIsoInIncpltCallback().

void HAL_PCD_ISOOUTIncompleteCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | epnum
 | ) |  |

Incomplete ISO OUT callback.

Parameters:
hpcd | PCD handle
epnum | endpoint number
Return values:
None

Definition at line 1231 of file stm32wbxx_hal_pcd.c.

Referenced by HAL_PCD_Init(), and HAL_PCD_UnRegisterIsoOutIncpltCallback().

void HAL_PCD_ResetCallback ( PCD_HandleTypeDef * hpcd )

USB Reset callback.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 1185 of file stm32wbxx_hal_pcd.c.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), and HAL_PCD_UnRegisterCallback().

void HAL_PCD_ResumeCallback ( PCD_HandleTypeDef * hpcd )

Resume event callback.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 1215 of file stm32wbxx_hal_pcd.c.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), and HAL_PCD_UnRegisterCallback().

void HAL_PCD_SetupStageCallback ( PCD_HandleTypeDef * hpcd )

Setup stage callback.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 1155 of file stm32wbxx_hal_pcd.c.

Referenced by HAL_PCD_Init(), HAL_PCD_UnRegisterCallback(), and PCD_EP_ISR_Handler().

void HAL_PCD_SOFCallback ( PCD_HandleTypeDef * hpcd )

USB Start Of Frame callback.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 1170 of file stm32wbxx_hal_pcd.c.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), and HAL_PCD_UnRegisterCallback().

HAL_StatusTypeDef HAL_PCD_Start ( PCD_HandleTypeDef * hpcd )

Start the USB device.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 962 of file stm32wbxx_hal_pcd.c.

References __HAL_PCD_ENABLE, and __PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_Stop ( PCD_HandleTypeDef * hpcd )

Stop the USB device.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 976 of file stm32wbxx_hal_pcd.c.

References __HAL_PCD_DISABLE, and __PCD_HandleTypeDef::Instance.

Referenced by HAL_PCD_DeInit().

void HAL_PCD_SuspendCallback ( PCD_HandleTypeDef * hpcd )

Suspend event callback.

Parameters:
hpcd PCD handle
Return values:
None

Definition at line 1200 of file stm32wbxx_hal_pcd.c.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), and HAL_PCD_UnRegisterCallback().

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
PCD Exported Functions

management functions More...

Functions

HAL_StatusTypeDef | HAL_PCD_DevConnect (PCD_HandleTypeDef *hpcd)
Connect the USB device.
HAL_StatusTypeDef | HAL_PCD_DevDisconnect (PCD_HandleTypeDef *hpcd)
Disconnect the USB device.
HAL_StatusTypeDef | HAL_PCD_SetAddress (PCD_HandleTypeDef *hpcd, uint8_t address)
Set the USB Device address.
HAL_StatusTypeDef | HAL_PCD_EP_Open (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
Open and configure an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Close (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Deactivate an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Receive (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Receive an amount of data.
uint32_t | HAL_PCD_EP_GetRxCount (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Get Received Data Size.
HAL_StatusTypeDef | HAL_PCD_EP_Transmit (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Send an amount of data.
HAL_StatusTypeDef | HAL_PCD_EP_SetStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Set a STALL condition over an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_ClrStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Clear a STALL condition over in an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Flush (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Flush an endpoint.
HAL_StatusTypeDef | HAL_PCD_ActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
Activate remote wakeup signalling.
HAL_StatusTypeDef | HAL_PCD_DeActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
De-activate remote wakeup signalling.

Detailed Description

management functions

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the PCD data
    transfers.

Function Documentation

HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup ( PCD_HandleTypeDef * hpcd )

Activate remote wakeup signalling.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 1596 of file stm32wbxx_hal_pcd.c.

References __PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup ( PCD_HandleTypeDef * hpcd )

De-activate remote wakeup signalling.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 1606 of file stm32wbxx_hal_pcd.c.

References __PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_DevConnect ( PCD_HandleTypeDef * hpcd )

Connect the USB device.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 1313 of file stm32wbxx_hal_pcd.c.

References __PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_DevDisconnect ( PCD_HandleTypeDef * hpcd )

Disconnect the USB device.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 1326 of file stm32wbxx_hal_pcd.c.

References __PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_EP_Close | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Deactivate an endpoint.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
Return values:
HAL status

Definition at line 1400 of file stm32wbxx_hal_pcd.c.

References __PCD_HandleTypeDef::IN_ep, __PCD_HandleTypeDef::Instance, and __PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_ClrStall | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Clear a STALL condition over in an endpoint.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
Return values:
HAL status

Definition at line 1546 of file stm32wbxx_hal_pcd.c.

References __PCD_HandleTypeDef::IN_ep, __PCD_HandleTypeDef::Init, __PCD_HandleTypeDef::Instance, and __PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_Flush | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Flush an endpoint.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
Return values:
HAL status

Definition at line 1582 of file stm32wbxx_hal_pcd.c.

uint32_t HAL_PCD_EP_GetRxCount | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Get Received Data Size.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
Return values:
Data Size

Definition at line 1462 of file stm32wbxx_hal_pcd.c.

References __PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_Open | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr,
 |  | uint16_t | ep_mps,
 |  | uint8_t | ep_type
 | ) |  |

Open and configure an endpoint.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
ep_mps | endpoint max packet size
ep_type | endpoint type
Return values:
HAL status

Definition at line 1356 of file stm32wbxx_hal_pcd.c.

References __PCD_HandleTypeDef::IN_ep, __PCD_HandleTypeDef::Instance, and __PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_Receive | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr,
 |  | uint8_t * | pBuf,
 |  | uint32_t | len
 | ) |  |

Receive an amount of data.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
pBuf | pointer to the reception buffer
len | amount of data to be received
Return values:
HAL status

Definition at line 1431 of file stm32wbxx_hal_pcd.c.

References __PCD_HandleTypeDef::Instance, __PCD_HandleTypeDef::OUT_ep, and USB_EP0StartXfer.

Referenced by PCD_EP_ISR_Handler().

HAL_StatusTypeDef HAL_PCD_EP_SetStall | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Set a STALL condition over an endpoint.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
Return values:
HAL status

Definition at line 1505 of file stm32wbxx_hal_pcd.c.

References __PCD_HandleTypeDef::IN_ep, __PCD_HandleTypeDef::Init, __PCD_HandleTypeDef::Instance, __PCD_HandleTypeDef::OUT_ep, and __PCD_HandleTypeDef::Setup.

HAL_StatusTypeDef HAL_PCD_EP_Transmit | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr,
 |  | uint8_t * | pBuf,
 |  | uint32_t | len
 | ) |  |

Send an amount of data.

Parameters:
hpcd | PCD handle
ep_addr | endpoint address
pBuf | pointer to the transmission buffer
len | amount of data to be sent
Return values:
HAL status

Definition at line 1474 of file stm32wbxx_hal_pcd.c.

References __PCD_HandleTypeDef::IN_ep, __PCD_HandleTypeDef::Instance, and USB_EP0StartXfer.

Referenced by PCD_EP_ISR_Handler().

HAL_StatusTypeDef HAL_PCD_SetAddress | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | address
 | ) |  |

Set the USB Device address.

Parameters:
hpcd | PCD handle
address | new device address
Return values:
HAL status

Definition at line 1340 of file stm32wbxx_hal_pcd.c.

References __PCD_HandleTypeDef::Instance, and __PCD_HandleTypeDef::USB_Address.

Referenced by HAL_PCD_IRQHandler().

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
PCD Exported Functions

Peripheral State functions. More...

Functions

PCD_StateTypeDef HAL_PCD_GetState (PCD_HandleTypeDef *hpcd)
Return the PCD handle state.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

PCD_StateTypeDef HAL_PCD_GetState ( PCD_HandleTypeDef * hpcd )

Return the PCD handle state.

Parameters:
hpcd PCD handle
Return values:
HAL state

Definition at line 1635 of file stm32wbxx_hal_pcd.c.

References __PCD_HandleTypeDef::State.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PCD Exported Types

Data Structures | Typedefs | Enumerations
PCD Exported Types
PCD

Data Structures

struct | __PCD_HandleTypeDef
PCD Handle Structure definition. More...

Typedefs

typedef USB_TypeDef | PCD_TypeDef
typedef USB_CfgTypeDef | PCD_InitTypeDef
typedef USB_EPTypeDef | PCD_EPTypeDef
typedef struct __PCD_HandleTypeDef | PCD_HandleTypeDef
PCD Handle Structure definition.

Enumerations

enum PCD_StateTypeDef {
HAL_PCD_STATE_RESET = 0x00, HAL_PCD_STATE_READY = 0x01, HAL_PCD_STATE_ERROR = 0x02, HAL_PCD_STATE_BUSY = 0x03,
HAL_PCD_STATE_TIMEOUT = 0x04
}
PCD State structure definition. More...
enum | PCD_LPM_StateTypeDef { LPM_L0 = 0x00, LPM_L1 = 0x01, LPM_L2 = 0x02, LPM_L3 = 0x03 }
enum | PCD_LPM_MsgTypeDef { PCD_LPM_L0_ACTIVE = 0x00, PCD_LPM_L1_ACTIVE = 0x01 }
enum PCD_BCD_MsgTypeDef {
PCD_BCD_ERROR = 0xFF, PCD_BCD_CONTACT_DETECTION = 0xFE, PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD, PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC,
PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB, PCD_BCD_DISCOVERY_COMPLETED = 0x00
}

Typedef Documentation

typedef USB_EPTypeDef PCD_EPTypeDef

Definition at line 90 of file stm32wbxx_hal_pcd.h.

typedef struct __PCD_HandleTypeDef PCD_HandleTypeDef

PCD Handle Structure definition.

typedef USB_CfgTypeDef PCD_InitTypeDef

Definition at line 89 of file stm32wbxx_hal_pcd.h.

typedef USB_TypeDef PCD_TypeDef

Definition at line 88 of file stm32wbxx_hal_pcd.h.

Enumeration Type Documentation

enum PCD_BCD_MsgTypeDef
Enumerator:
PCD_BCD_ERROR
PCD_BCD_CONTACT_DETECTION
PCD_BCD_STD_DOWNSTREAM_PORT
PCD_BCD_CHARGING_DOWNSTREAM_PORT
PCD_BCD_DEDICATED_CHARGING_PORT
PCD_BCD_DISCOVERY_COMPLETED

Definition at line 73 of file stm32wbxx_hal_pcd.h.

enum PCD_LPM_MsgTypeDef
Enumerator:
PCD_LPM_L0_ACTIVE
PCD_LPM_L1_ACTIVE

Definition at line 67 of file stm32wbxx_hal_pcd.h.

enum PCD_LPM_StateTypeDef
Enumerator:
LPM_L0
LPM_L1
LPM_L2
LPM_L3

Definition at line 59 of file stm32wbxx_hal_pcd.h.

enum PCD_StateTypeDef

PCD State structure definition.

Enumerator:
HAL_PCD_STATE_RESET
HAL_PCD_STATE_READY
HAL_PCD_STATE_ERROR
HAL_PCD_STATE_BUSY
HAL_PCD_STATE_TIMEOUT

Definition at line 49 of file stm32wbxx_hal_pcd.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: __PCD_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__PCD_HandleTypeDef Struct Reference
PCD Exported Types

PCD Handle Structure definition. More...

#include <stm32wbxx_hal_pcd.h>

Data Fields

PCD_TypeDef * Instance
PCD_InitTypeDef Init
__IO uint8_t | USB_Address
PCD_EPTypeDef | IN_ep [8]
PCD_EPTypeDef | OUT_ep [8]
HAL_LockTypeDef | Lock
__IO PCD_StateTypeDef | State
__IO uint32_t | ErrorCode
uint32_t | Setup [12]
PCD_LPM_StateTypeDef LPM_State
uint32_t | BESL
uint32_t | lpm_active
uint32_t | battery_charging_active
void * | pData
void(* | SOFCallback )(struct __PCD_HandleTypeDef *hpcd)
void(* | SetupStageCallback )(struct __PCD_HandleTypeDef *hpcd)
void(* | ResetCallback )(struct __PCD_HandleTypeDef *hpcd)
void(* | SuspendCallback )(struct __PCD_HandleTypeDef *hpcd)
void(* | ResumeCallback )(struct __PCD_HandleTypeDef *hpcd)
void(* | ConnectCallback )(struct __PCD_HandleTypeDef *hpcd)
void(* | DisconnectCallback )(struct __PCD_HandleTypeDef *hpcd)
void(* | DataOutStageCallback )(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum)
void(* | DataInStageCallback )(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum)
void(* | ISOOUTIncompleteCallback )(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum)
void(* | ISOINIncompleteCallback )(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum)
void(* | BCDCallback )(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
void(* | LPMCallback )(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
void(* | MspInitCallback )(struct __PCD_HandleTypeDef *hpcd)
void(* | MspDeInitCallback )(struct __PCD_HandleTypeDef *hpcd)

Detailed Description

PCD Handle Structure definition.

Definition at line 97 of file stm32wbxx_hal_pcd.h.

Field Documentation

uint32_t __PCD_HandleTypeDef::battery_charging_active

Enable or disable Battery charging. This parameter can be set to ENABLE or DISABLE

Definition at line 118 of file stm32wbxx_hal_pcd.h.

Referenced by HAL_PCDEx_ActivateBCD(), and HAL_PCDEx_DeActivateBCD().

void(* __PCD_HandleTypeDef::BCDCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)

USB OTG PCD BCD callback

Definition at line 135 of file stm32wbxx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_RegisterBcdCallback(), HAL_PCD_UnRegisterBcdCallback(), and HAL_PCDEx_BCD_VBUSDetect().

uint32_t __PCD_HandleTypeDef::BESL

Definition at line 112 of file stm32wbxx_hal_pcd.h.

Referenced by HAL_PCD_IRQHandler().

void(* __PCD_HandleTypeDef::ConnectCallback)(struct __PCD_HandleTypeDef *hpcd)

USB OTG PCD Connect callback

Definition at line 128 of file stm32wbxx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_RegisterCallback(), and HAL_PCD_UnRegisterCallback().

void(* __PCD_HandleTypeDef::DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum)

USB OTG PCD Data IN Stage callback

Definition at line 132 of file stm32wbxx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_RegisterDataInStageCallback(), HAL_PCD_UnRegisterDataInStageCallback(), and PCD_EP_ISR_Handler().

void(* __PCD_HandleTypeDef::DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum)

USB OTG PCD Data OUT Stage callback

Definition at line 131 of file stm32wbxx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_RegisterDataOutStageCallback(), HAL_PCD_UnRegisterDataOutStageCallback(), and PCD_EP_ISR_Handler().

void(* __PCD_HandleTypeDef::DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd)

USB OTG PCD Disconnect callback

Definition at line 129 of file stm32wbxx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_RegisterCallback(), and HAL_PCD_UnRegisterCallback().

__IO uint32_t __PCD_HandleTypeDef::ErrorCode

PCD Error code

Definition at line 109 of file stm32wbxx_hal_pcd.h.

Referenced by HAL_PCD_RegisterBcdCallback(), HAL_PCD_RegisterCallback(), HAL_PCD_RegisterDataInStageCallback(), HAL_PCD_RegisterDataOutStageCallback(), HAL_PCD_RegisterIsoInIncpltCallback(), HAL_PCD_RegisterIsoOutIncpltCallback(), HAL_PCD_RegisterLpmCallback(), HAL_PCD_UnRegisterBcdCallback(), HAL_PCD_UnRegisterCallback(), HAL_PCD_UnRegisterDataInStageCallback(), HAL_PCD_UnRegisterDataOutStageCallback(), HAL_PCD_UnRegisterIsoInIncpltCallback(), HAL_PCD_UnRegisterIsoOutIncpltCallback(), and HAL_PCD_UnRegisterLpmCallback().

PCD_EPTypeDef __PCD_HandleTypeDef::IN_ep[8]

IN endpoint parameters

Definition at line 105 of file stm32wbxx_hal_pcd.h.

Referenced by HAL_PCD_EP_Close(), HAL_PCD_EP_ClrStall(), HAL_PCD_EP_Open(), HAL_PCD_EP_SetStall(), HAL_PCD_EP_Transmit(), HAL_PCD_Init(), HAL_PCDEx_PMAConfig(), and PCD_EP_ISR_Handler().

PCD_InitTypeDef __PCD_HandleTypeDef::Init

PCD required parameters

Definition at line 103 of file stm32wbxx_hal_pcd.h.

Referenced by HAL_PCD_EP_ClrStall(), HAL_PCD_EP_SetStall(), and HAL_PCD_Init().

PCD_TypeDef* __PCD_HandleTypeDef::Instance

Register base address

Definition at line 102 of file stm32wbxx_hal_pcd.h.

Referenced by HAL_PCD_ActivateRemoteWakeup(), HAL_PCD_DeActivateRemoteWakeup(), HAL_PCD_DevConnect(), HAL_PCD_DevDisconnect(), HAL_PCD_EP_Close(), HAL_PCD_EP_ClrStall(), HAL_PCD_EP_Open(), HAL_PCD_EP_Receive(), HAL_PCD_EP_SetStall(), HAL_PCD_EP_Transmit(), HAL_PCD_Init(), HAL_PCD_IRQHandler(), HAL_PCD_SetAddress(), HAL_PCD_Start(), HAL_PCD_Stop(), HAL_PCDEx_ActivateBCD(), HAL_PCDEx_ActivateLPM(), HAL_PCDEx_BCD_VBUSDetect(), HAL_PCDEx_DeActivateBCD(), HAL_PCDEx_DeActivateLPM(), and PCD_EP_ISR_Handler().

void(* __PCD_HandleTypeDef::ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum)

USB OTG PCD ISO IN Incomplete callback

Definition at line 134 of file stm32wbxx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_RegisterIsoInIncpltCallback(), and HAL_PCD_UnRegisterIsoInIncpltCallback().

void(* __PCD_HandleTypeDef::ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum)

USB OTG PCD ISO OUT Incomplete callback

Definition at line 133 of file stm32wbxx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_RegisterIsoOutIncpltCallback(), and HAL_PCD_UnRegisterIsoOutIncpltCallback().

HAL_LockTypeDef __PCD_HandleTypeDef::Lock

PCD peripheral status

Definition at line 107 of file stm32wbxx_hal_pcd.h.

Referenced by HAL_PCD_Init().

uint32_t __PCD_HandleTypeDef::lpm_active

Enable or disable the Link Power Management . This parameter can be set to ENABLE or DISABLE

Definition at line 115 of file stm32wbxx_hal_pcd.h.

Referenced by HAL_PCDEx_ActivateLPM(), and HAL_PCDEx_DeActivateLPM().

PCD_LPM_StateTypeDef __PCD_HandleTypeDef::LPM_State

LPM State

Definition at line 111 of file stm32wbxx_hal_pcd.h.

Referenced by HAL_PCD_IRQHandler(), and HAL_PCDEx_ActivateLPM().

void(* __PCD_HandleTypeDef::LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)

USB OTG PCD LPM callback

Definition at line 136 of file stm32wbxx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), HAL_PCD_RegisterLpmCallback(), and HAL_PCD_UnRegisterLpmCallback().

void(* __PCD_HandleTypeDef::MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd)

USB OTG PCD Msp DeInit callback

Definition at line 139 of file stm32wbxx_hal_pcd.h.

Referenced by HAL_PCD_DeInit(), HAL_PCD_RegisterCallback(), and HAL_PCD_UnRegisterCallback().

void(* __PCD_HandleTypeDef::MspInitCallback)(struct __PCD_HandleTypeDef *hpcd)

USB OTG PCD Msp Init callback

Definition at line 138 of file stm32wbxx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_RegisterCallback(), and HAL_PCD_UnRegisterCallback().

PCD_EPTypeDef __PCD_HandleTypeDef::OUT_ep[8]

OUT endpoint parameters

Definition at line 106 of file stm32wbxx_hal_pcd.h.

Referenced by HAL_PCD_EP_Close(), HAL_PCD_EP_ClrStall(), HAL_PCD_EP_GetRxCount(), HAL_PCD_EP_Open(), HAL_PCD_EP_Receive(), HAL_PCD_EP_SetStall(), HAL_PCD_Init(), HAL_PCDEx_PMAConfig(), and PCD_EP_ISR_Handler().

void* __PCD_HandleTypeDef::pData

Pointer to upper stack Handler

Definition at line 120 of file stm32wbxx_hal_pcd.h.

void(* __PCD_HandleTypeDef::ResetCallback)(struct __PCD_HandleTypeDef *hpcd)

USB OTG PCD Reset callback

Definition at line 125 of file stm32wbxx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), HAL_PCD_RegisterCallback(), and HAL_PCD_UnRegisterCallback().

void(* __PCD_HandleTypeDef::ResumeCallback)(struct __PCD_HandleTypeDef *hpcd)

USB OTG PCD Resume callback

Definition at line 127 of file stm32wbxx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), HAL_PCD_RegisterCallback(), and HAL_PCD_UnRegisterCallback().

uint32_t __PCD_HandleTypeDef::Setup[12]

Setup packet buffer

Definition at line 110 of file stm32wbxx_hal_pcd.h.

Referenced by HAL_PCD_EP_SetStall(), and PCD_EP_ISR_Handler().

void(* __PCD_HandleTypeDef::SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd)

USB OTG PCD Setup Stage callback

Definition at line 124 of file stm32wbxx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_RegisterCallback(), HAL_PCD_UnRegisterCallback(), and PCD_EP_ISR_Handler().

void(* __PCD_HandleTypeDef::SOFCallback)(struct __PCD_HandleTypeDef *hpcd)

USB OTG PCD SOF callback

Definition at line 123 of file stm32wbxx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), HAL_PCD_RegisterCallback(), and HAL_PCD_UnRegisterCallback().

__IO PCD_StateTypeDef __PCD_HandleTypeDef::State

PCD communication state

Definition at line 108 of file stm32wbxx_hal_pcd.h.

Referenced by HAL_PCD_DeInit(), HAL_PCD_GetState(), HAL_PCD_Init(), HAL_PCD_RegisterBcdCallback(), HAL_PCD_RegisterCallback(), HAL_PCD_RegisterDataInStageCallback(), HAL_PCD_RegisterDataOutStageCallback(), HAL_PCD_RegisterIsoInIncpltCallback(), HAL_PCD_RegisterIsoOutIncpltCallback(), HAL_PCD_RegisterLpmCallback(), HAL_PCD_UnRegisterBcdCallback(), HAL_PCD_UnRegisterCallback(), HAL_PCD_UnRegisterDataInStageCallback(), HAL_PCD_UnRegisterDataOutStageCallback(), HAL_PCD_UnRegisterIsoInIncpltCallback(), HAL_PCD_UnRegisterIsoOutIncpltCallback(), and HAL_PCD_UnRegisterLpmCallback().

void(* __PCD_HandleTypeDef::SuspendCallback)(struct __PCD_HandleTypeDef *hpcd)

USB OTG PCD Suspend callback

Definition at line 126 of file stm32wbxx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), HAL_PCD_RegisterCallback(), and HAL_PCD_UnRegisterCallback().

__IO uint8_t __PCD_HandleTypeDef::USB_Address

USB Address

Definition at line 104 of file stm32wbxx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_SetAddress(), and PCD_EP_ISR_Handler().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_pcd.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PCD Speed

Defines
PCD Speed
PCD Exported Constants

Defines

#define PCD_SPEED_FULL USBD_FS_SPEED

Define Documentation

#define PCD_SPEED_FULL USBD_FS_SPEED

Definition at line 158 of file stm32wbxx_hal_pcd.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PCD PHY Module

Defines
PCD PHY Module
PCD Exported Constants

Defines

#define | PCD_PHY_ULPI 1U
#define | PCD_PHY_EMBEDDED 2U
#define | PCD_PHY_UTMI 3U

Define Documentation

#define PCD_PHY_EMBEDDED 2U

Definition at line 167 of file stm32wbxx_hal_pcd.h.

#define PCD_PHY_ULPI 1U

Definition at line 166 of file stm32wbxx_hal_pcd.h.

#define PCD_PHY_UTMI 3U

Definition at line 168 of file stm32wbxx_hal_pcd.h.

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STM32WB55xx HAL User Manual: PCD Error Code definition

Defines
PCD Error Code definition
PCD Exported Constants

PCD Error Code definition. More...

Defines

#define HAL_PCD_ERROR_INVALID_CALLBACK (0x00000010U)

Detailed Description

PCD Error Code definition.

Define Documentation

#define HAL_PCD_ERROR_INVALID_CALLBACK (0x00000010U)

Invalid Callback error

Definition at line 178 of file stm32wbxx_hal_pcd.h.

Referenced by HAL_PCD_RegisterBcdCallback(), HAL_PCD_RegisterCallback(), HAL_PCD_RegisterDataInStageCallback(), HAL_PCD_RegisterDataOutStageCallback(), HAL_PCD_RegisterIsoInIncpltCallback(), HAL_PCD_RegisterIsoOutIncpltCallback(), HAL_PCD_RegisterLpmCallback(), HAL_PCD_UnRegisterBcdCallback(), HAL_PCD_UnRegisterCallback(), HAL_PCD_UnRegisterDataInStageCallback(), HAL_PCD_UnRegisterDataOutStageCallback(), HAL_PCD_UnRegisterIsoInIncpltCallback(), HAL_PCD_UnRegisterIsoOutIncpltCallback(), and HAL_PCD_UnRegisterLpmCallback().

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PCD Exported Macros

Defines
PCD Exported Macros
PCD

macros to handle interrupts and specific clock configurations More...

Defines

#define | __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#define | __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))
#define | __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR1 |= USB_WAKEUP_EXTI_LINE
#define | __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR1 &= ~(USB_WAKEUP_EXTI_LINE)

Detailed Description

macros to handle interrupts and specific clock configurations

Define Documentation

#define __HAL_PCD_CLEAR_FLAG | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))

Definition at line 199 of file stm32wbxx_hal_pcd.h.

Referenced by HAL_PCD_IRQHandler().

#define __HAL_PCD_DISABLE ( __HANDLE__ ) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)

Definition at line 197 of file stm32wbxx_hal_pcd.h.

Referenced by HAL_PCD_Init(), and HAL_PCD_Stop().

#define __HAL_PCD_ENABLE ( __HANDLE__ ) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)

Definition at line 196 of file stm32wbxx_hal_pcd.h.

Referenced by HAL_PCD_Start().

#define __HAL_PCD_GET_FLAG | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))

Definition at line 198 of file stm32wbxx_hal_pcd.h.

Referenced by HAL_PCD_IRQHandler().

#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT ( ) EXTI->IMR1 &= ~(USB_WAKEUP_EXTI_LINE)

Definition at line 202 of file stm32wbxx_hal_pcd.h.

#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT ( ) EXTI->IMR1 |= USB_WAKEUP_EXTI_LINE

Definition at line 201 of file stm32wbxx_hal_pcd.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: USB EXTI line interrupt

Defines
USB EXTI line interrupt
PCD Private Constants

Defines

#define USB_WAKEUP_EXTI_LINE (0x1U << 28)

Define Documentation

#define USB_WAKEUP_EXTI_LINE (0x1U << 28)

USB FS EXTI Line WakeUp Interrupt

Definition at line 356 of file stm32wbxx_hal_pcd.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PCD EP0 MPS

Defines
PCD EP0 MPS
PCD Private Constants

Defines

#define | PCD_EP0MPS_64 DEP0CTL_MPS_64
#define | PCD_EP0MPS_32 DEP0CTL_MPS_32
#define | PCD_EP0MPS_16 DEP0CTL_MPS_16
#define | PCD_EP0MPS_08 DEP0CTL_MPS_8

Define Documentation

#define PCD_EP0MPS_08 DEP0CTL_MPS_8

Definition at line 369 of file stm32wbxx_hal_pcd.h.

#define PCD_EP0MPS_16 DEP0CTL_MPS_16

Definition at line 368 of file stm32wbxx_hal_pcd.h.

#define PCD_EP0MPS_32 DEP0CTL_MPS_32

Definition at line 367 of file stm32wbxx_hal_pcd.h.

#define PCD_EP0MPS_64 DEP0CTL_MPS_64

Definition at line 366 of file stm32wbxx_hal_pcd.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PCD ENDP

Defines
PCD ENDP
PCD Private Constants

Defines

#define | PCD_ENDP0 0U
#define | PCD_ENDP1 1U
#define | PCD_ENDP2 2U
#define | PCD_ENDP3 3U
#define | PCD_ENDP4 4U
#define | PCD_ENDP5 5U
#define | PCD_ENDP6 6U
#define | PCD_ENDP7 7U

Define Documentation

#define PCD_ENDP0 0U

Definition at line 377 of file stm32wbxx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_ENDP1 1U

Definition at line 378 of file stm32wbxx_hal_pcd.h.

#define PCD_ENDP2 2U

Definition at line 379 of file stm32wbxx_hal_pcd.h.

#define PCD_ENDP3 3U

Definition at line 380 of file stm32wbxx_hal_pcd.h.

#define PCD_ENDP4 4U

Definition at line 381 of file stm32wbxx_hal_pcd.h.

#define PCD_ENDP5 5U

Definition at line 382 of file stm32wbxx_hal_pcd.h.

#define PCD_ENDP6 6U

Definition at line 383 of file stm32wbxx_hal_pcd.h.

#define PCD_ENDP7 7U

Definition at line 384 of file stm32wbxx_hal_pcd.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PCD Endpoint Kind

Defines
PCD Endpoint Kind
PCD Private Constants

Defines

#define | PCD_SNG_BUF 0U
#define | PCD_DBL_BUF 1U

Define Documentation

#define PCD_DBL_BUF 1U

Definition at line 393 of file stm32wbxx_hal_pcd.h.

#define PCD_SNG_BUF 0U

Definition at line 392 of file stm32wbxx_hal_pcd.h.

Referenced by HAL_PCDEx_PMAConfig().

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
PCDEx Exported Functions

PCDEx control functions. More...

Functions

HAL_StatusTypeDef | HAL_PCDEx_PMAConfig (PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pmaadress)
Configure PMA for EP.
HAL_StatusTypeDef | HAL_PCDEx_ActivateBCD (PCD_HandleTypeDef *hpcd)
Activate BatteryCharging feature.
HAL_StatusTypeDef | HAL_PCDEx_DeActivateBCD (PCD_HandleTypeDef *hpcd)
Deactivate BatteryCharging feature.
void | HAL_PCDEx_BCD_VBUSDetect (PCD_HandleTypeDef *hpcd)
Handle BatteryCharging Process.
HAL_StatusTypeDef | HAL_PCDEx_ActivateLPM (PCD_HandleTypeDef *hpcd)
Activate LPM feature.
HAL_StatusTypeDef | HAL_PCDEx_DeActivateLPM (PCD_HandleTypeDef *hpcd)
Deactivate LPM feature.
__weak void | HAL_PCDEx_LPM_Callback (PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
Send LPM message to user layer callback.
__weak void | HAL_PCDEx_BCD_Callback (PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
Send BatteryCharging message to user layer callback.

Detailed Description

PCDEx control functions.

 ===============================================================================
                 ##### Extended features functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Update FIFO configuration

Function Documentation

HAL_StatusTypeDef HAL_PCDEx_ActivateBCD ( PCD_HandleTypeDef * hpcd )

Activate BatteryCharging feature.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 123 of file stm32wbxx_hal_pcd_ex.c.

References __PCD_HandleTypeDef::battery_charging_active, and __PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCDEx_ActivateLPM ( PCD_HandleTypeDef * hpcd )

Activate LPM feature.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 254 of file stm32wbxx_hal_pcd_ex.c.

References __PCD_HandleTypeDef::Instance, __PCD_HandleTypeDef::lpm_active, LPM_L0, and __PCD_HandleTypeDef::LPM_State.

Referenced by HAL_PCD_Init().

void HAL_PCDEx_BCD_Callback | ( | PCD_HandleTypeDef * | hpcd,
 |  | PCD_BCD_MsgTypeDef | msg
 | ) |  |

Send BatteryCharging message to user layer callback.

Parameters:
hpcd | PCD handle
msg | LPM message
Return values:
HAL status

Definition at line 309 of file stm32wbxx_hal_pcd_ex.c.

Referenced by HAL_PCD_Init(), HAL_PCD_UnRegisterBcdCallback(), and HAL_PCDEx_BCD_VBUSDetect().

void HAL_PCDEx_BCD_VBUSDetect ( PCD_HandleTypeDef * hpcd )

Handle BatteryCharging Process.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 160 of file stm32wbxx_hal_pcd_ex.c.

References __PCD_HandleTypeDef::BCDCallback, HAL_Delay(), HAL_GetTick(), HAL_PCDEx_BCD_Callback(), HAL_PCDEx_DeActivateBCD(), __PCD_HandleTypeDef::Instance, PCD_BCD_CHARGING_DOWNSTREAM_PORT, PCD_BCD_CONTACT_DETECTION, PCD_BCD_DEDICATED_CHARGING_PORT, PCD_BCD_DISCOVERY_COMPLETED, PCD_BCD_ERROR, and PCD_BCD_STD_DOWNSTREAM_PORT.

HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD ( PCD_HandleTypeDef * hpcd )

Deactivate BatteryCharging feature.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 144 of file stm32wbxx_hal_pcd_ex.c.

References __PCD_HandleTypeDef::battery_charging_active, and __PCD_HandleTypeDef::Instance.

Referenced by HAL_PCDEx_BCD_VBUSDetect().

HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM ( PCD_HandleTypeDef * hpcd )

Deactivate LPM feature.

Parameters:
hpcd PCD handle
Return values:
HAL status

Definition at line 272 of file stm32wbxx_hal_pcd_ex.c.

References __PCD_HandleTypeDef::Instance, and __PCD_HandleTypeDef::lpm_active.

void HAL_PCDEx_LPM_Callback | ( | PCD_HandleTypeDef * | hpcd,
 |  | PCD_LPM_MsgTypeDef | msg
 | ) |  |

Send LPM message to user layer callback.

Parameters:
hpcd | PCD handle
msg | LPM message
Return values:
HAL status

Definition at line 292 of file stm32wbxx_hal_pcd_ex.c.

Referenced by HAL_PCD_Init(), HAL_PCD_IRQHandler(), and HAL_PCD_UnRegisterLpmCallback().

HAL_StatusTypeDef HAL_PCDEx_PMAConfig | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint16_t | ep_addr,
 |  | uint16_t | ep_kind,
 |  | uint32_t | pmaadress
 | ) |  |

Configure PMA for EP.

Parameters:
hpcd | Device instance
ep_addr | endpoint address
ep_kind | endpoint Kind USB_SNG_BUF: Single Buffer used USB_DBL_BUF: Double Buffer used
pmaadress,: EP address in The PMA: In case of single buffer endpoint this parameter is 16-bit value providing the address in PMA allocated to endpoint. In case of double buffer endpoint this parameter is a 32-bit value providing the endpoint buffer 0 address in the LSB part of 32-bit value and endpoint buffer 1 address in the MSB part of 32-bit value.
Return values:
HAL status

Definition at line 81 of file stm32wbxx_hal_pcd_ex.c.

References __PCD_HandleTypeDef::IN_ep, __PCD_HandleTypeDef::OUT_ep, and PCD_SNG_BUF.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PKA Private Define

Defines
PKA Private Define
PKA

Defines

#define PKA_RAM_SIZE 894U

Define Documentation

#define PKA_RAM_SIZE 894U

Definition at line 265 of file stm32wbxx_hal_pka.c.

Referenced by HAL_PKA_RAMReset().

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STM32WB55xx HAL User Manual: PKA Private Functions

Functions
PKA Private Functions
PKA

Functions

uint32_t | PKA_GetMode (PKA_HandleTypeDef *hpka)
Get PKA operating mode.
HAL_StatusTypeDef | PKA_PollEndOfOperation (PKA_HandleTypeDef *hpka, uint32_t Timeout, uint32_t Tickstart)
Wait for operation completion or timeout.
uint32_t | PKA_CheckError (PKA_HandleTypeDef *hpka, uint32_t mode)
Return a hal error code based on PKA error flags.
uint32_t | PKA_GetBitSize_u8 (uint32_t byteNumber)
Get number of bits inside an array of u8.
uint32_t | PKA_GetOptBitSize_u8 (uint32_t byteNumber, uint8_t msb)
Get optimal number of bits inside an array of u8.
uint32_t | PKA_GetBitSize_u32 (uint32_t wordNumber)
Get number of bits inside an array of u32.
uint32_t | PKA_GetArraySize_u8 (uint32_t bitSize)
Get number of uint8_t element in an array of bitSize bits.
void | PKA_Memcpy_u32_to_u8 (uint8_t dst[], __IO const uint32_t src[], size_t n)
Copy uint32_t array to uint8_t array to fit PKA number representation.
void | PKA_Memcpy_u8_to_u32 (__IO uint32_t dst[], const uint8_t src[], size_t n)
Copy uint8_t array to uint32_t array to fit PKA number representation.
void | PKA_Memcpy_u32_to_u32 (__IO uint32_t dst[], __IO const uint32_t src[], size_t n)
Copy uint32_t array to uint32_t array.
HAL_StatusTypeDef | PKA_Process (PKA_HandleTypeDef *hpka, uint32_t mode, uint32_t Timeout)
Generic function to start a PKA operation in blocking mode.
HAL_StatusTypeDef | PKA_Process_IT (PKA_HandleTypeDef *hpka, uint32_t mode)
Generic function to start a PKA operation in non-blocking mode with Interrupt.
void | PKA_ModExp_Set (PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in)
Set input parameters.
void | PKA_ModExpFastMode_Set (PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in)
Set input parameters.
void | PKA_ECDSASign_Set (PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in)
Set input parameters.
void | PKA_ECDSAVerif_Set (PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in)
Set input parameters.
void | PKA_RSACRTExp_Set (PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in)
Set input parameters.
void | PKA_PointCheck_Set (PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in)
Set input parameters.
void | PKA_ECCMul_Set (PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in)
Set input parameters.
void | PKA_ECCMulFastMode_Set (PKA_HandleTypeDef *hpka, PKA_ECCMulFastModeInTypeDef *in)
Set input parameters.
void | PKA_ModRed_Set (PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in)
Set input parameters.
void | PKA_ModInv_Set (PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in)
Set input parameters.
void | PKA_MontgomeryParam_Set (PKA_HandleTypeDef *hpka, const uint32_t size, const uint8_t *pOp1)
Set input parameters.
void | PKA_ARI_Set (PKA_HandleTypeDef *hpka, const uint32_t size, const uint32_t *pOp1, const uint32_t *pOp2, const uint8_t *pOp3)
Generic function to set input parameters.

Function Documentation

void PKA_ARI_Set | ( | PKA_HandleTypeDef * | hpka,
 |  | const uint32_t | size,
 |  | const uint32_t * | pOp1,
 |  | const uint32_t * | pOp2,
 |  | const uint8_t * | pOp3
 | ) |  |

Generic function to set input parameters.

Parameters:
hpka | PKA handle
size | Size of the operand
pOp1 | Generic pointer to input data
pOp2 | Generic pointer to input data
pOp3 | Generic pointer to input data

Definition at line 2391 of file stm32wbxx_hal_pka.c.

References __PKA_HandleTypeDef::Instance, PKA_GetBitSize_u32(), PKA_Memcpy_u32_to_u32(), and PKA_Memcpy_u8_to_u32().

Referenced by HAL_PKA_Add(), HAL_PKA_Add_IT(), HAL_PKA_Cmp(), HAL_PKA_Cmp_IT(), HAL_PKA_ModAdd(), HAL_PKA_ModAdd_IT(), HAL_PKA_ModSub(), HAL_PKA_ModSub_IT(), HAL_PKA_MontgomeryMul(), HAL_PKA_MontgomeryMul_IT(), HAL_PKA_Mul(), HAL_PKA_Mul_IT(), HAL_PKA_Sub(), and HAL_PKA_Sub_IT().

uint32_t PKA_CheckError | ( | PKA_HandleTypeDef * | hpka,
 |  | uint32_t | mode
 | ) |  |

Return a hal error code based on PKA error flags.

Parameters:
hpka | PKA handle
mode | PKA operating mode
Return values:
error code

Definition at line 1722 of file stm32wbxx_hal_pka.c.

References __HAL_PKA_GET_FLAG, HAL_PKA_ERROR_ADDRERR, HAL_PKA_ERROR_NONE, HAL_PKA_ERROR_OPERATION, HAL_PKA_ERROR_RAMERR, __PKA_HandleTypeDef::Instance, PKA_FLAG_ADDRERR, PKA_FLAG_RAMERR, and PKA_MODE_ECDSA_SIGNATURE.

Referenced by PKA_Process().

void PKA_ECCMul_Set | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_ECCMulInTypeDef * | in
 | ) |  |

Set input parameters.

Parameters:
hpka | PKA handle
in | Input information

Definition at line 2250 of file stm32wbxx_hal_pka.c.

References PKA_ECCMulInTypeDef::coefA, PKA_ECCMulInTypeDef::coefSign, __PKA_HandleTypeDef::Instance, PKA_ECCMulInTypeDef::modulus, PKA_ECCMulInTypeDef::modulusSize, PKA_GetOptBitSize_u8(), PKA_Memcpy_u8_to_u32(), PKA_ECCMulInTypeDef::pointX, PKA_ECCMulInTypeDef::pointY, PKA_ECCMulInTypeDef::scalarMul, and PKA_ECCMulInTypeDef::scalarMulSize.

Referenced by HAL_PKA_ECCMul(), and HAL_PKA_ECCMul_IT().

void PKA_ECCMulFastMode_Set | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_ECCMulFastModeInTypeDef * | in
 | ) |  |

Set input parameters.

Parameters:
hpka | PKA handle
in | Input information

Definition at line 2287 of file stm32wbxx_hal_pka.c.

References PKA_ECCMulFastModeInTypeDef::coefA, PKA_ECCMulFastModeInTypeDef::coefSign, __PKA_HandleTypeDef::Instance, PKA_ECCMulFastModeInTypeDef::modulus, PKA_ECCMulFastModeInTypeDef::modulusSize, PKA_GetOptBitSize_u8(), PKA_Memcpy_u32_to_u32(), PKA_Memcpy_u8_to_u32(), PKA_ECCMulFastModeInTypeDef::pMontgomeryParam, PKA_ECCMulFastModeInTypeDef::pointX, PKA_ECCMulFastModeInTypeDef::pointY, PKA_ECCMulFastModeInTypeDef::scalarMul, and PKA_ECCMulFastModeInTypeDef::scalarMulSize.

Referenced by HAL_PKA_ECCMulFastMode(), and HAL_PKA_ECCMulFastMode_IT().

void PKA_ECDSASign_Set | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_ECDSASignInTypeDef * | in
 | ) |  |

Set input parameters.

Parameters:
hpka | PKA handle
in | Input information

Definition at line 2075 of file stm32wbxx_hal_pka.c.

References PKA_ECDSASignInTypeDef::basePointX, PKA_ECDSASignInTypeDef::basePointY, PKA_ECDSASignInTypeDef::coef, PKA_ECDSASignInTypeDef::coefSign, PKA_ECDSASignInTypeDef::hash, __PKA_HandleTypeDef::Instance, PKA_ECDSASignInTypeDef::integer, PKA_ECDSASignInTypeDef::modulus, PKA_ECDSASignInTypeDef::modulusSize, PKA_GetOptBitSize_u8(), PKA_Memcpy_u8_to_u32(), PKA_ECDSASignInTypeDef::primeOrder, PKA_ECDSASignInTypeDef::primeOrderSize, and PKA_ECDSASignInTypeDef::privateKey.

Referenced by HAL_PKA_ECDSASign(), and HAL_PKA_ECDSASign_IT().

void PKA_ECDSAVerif_Set | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_ECDSAVerifInTypeDef * | in
 | ) |  |

Set input parameters.

Parameters:
hpka | PKA handle
in | Input information

Definition at line 2124 of file stm32wbxx_hal_pka.c.

References PKA_ECDSAVerifInTypeDef::basePointX, PKA_ECDSAVerifInTypeDef::basePointY, PKA_ECDSAVerifInTypeDef::coef, PKA_ECDSAVerifInTypeDef::coefSign, PKA_ECDSAVerifInTypeDef::hash, __PKA_HandleTypeDef::Instance, PKA_ECDSAVerifInTypeDef::modulus, PKA_ECDSAVerifInTypeDef::modulusSize, PKA_GetOptBitSize_u8(), PKA_Memcpy_u8_to_u32(), PKA_ECDSAVerifInTypeDef::pPubKeyCurvePtX, PKA_ECDSAVerifInTypeDef::pPubKeyCurvePtY, PKA_ECDSAVerifInTypeDef::primeOrder, PKA_ECDSAVerifInTypeDef::primeOrderSize, PKA_ECDSAVerifInTypeDef::RSign, and PKA_ECDSAVerifInTypeDef::SSign.

Referenced by HAL_PKA_ECDSAVerif(), and HAL_PKA_ECDSAVerif_IT().

uint32_t PKA_GetArraySize_u8 ( uint32_t bitSize )

Get number of uint8_t element in an array of bitSize bits.

Parameters:
bitSize Number of bits in an array

Definition at line 1789 of file stm32wbxx_hal_pka.c.

uint32_t PKA_GetBitSize_u32 ( uint32_t wordNumber )

Get number of bits inside an array of u32.

Parameters:
wordNumber Number of u32 inside the array

Definition at line 1779 of file stm32wbxx_hal_pka.c.

Referenced by PKA_ARI_Set(), PKA_ModInv_Set(), and PKA_ModRed_Set().

uint32_t PKA_GetBitSize_u8 ( uint32_t byteNumber )

Get number of bits inside an array of u8.

Parameters:
byteNumber Number of u8 inside the array

Definition at line 1755 of file stm32wbxx_hal_pka.c.

Referenced by PKA_ModExp_Set(), PKA_ModExpFastMode_Set(), PKA_ModRed_Set(), and PKA_RSACRTExp_Set().

uint32_t PKA_GetMode ( PKA_HandleTypeDef * hpka )

Get PKA operating mode.

Parameters:
hpka PKA handle
Return values:
Return the current mode

Definition at line 1686 of file stm32wbxx_hal_pka.c.

References __PKA_HandleTypeDef::Instance.

Referenced by HAL_PKA_IRQHandler().

uint32_t PKA_GetOptBitSize_u8 | ( | uint32_t | byteNumber,
 |  | uint8_t | msb
 | ) |  |

Get optimal number of bits inside an array of u8.

Parameters:
byteNumber | Number of u8 inside the array
msb | Most significant uint8_t of the array

Definition at line 1766 of file stm32wbxx_hal_pka.c.

Referenced by PKA_ECCMul_Set(), PKA_ECCMulFastMode_Set(), PKA_ECDSASign_Set(), PKA_ECDSAVerif_Set(), PKA_MontgomeryParam_Set(), and PKA_PointCheck_Set().

void PKA_Memcpy_u32_to_u32 | ( | __IO uint32_t | dst[],
 |  | __IO const uint32_t | src[],
 |  | size_t | n
 | ) |  |

Copy uint32_t array to uint32_t array.

Parameters:
dst | Pointer to destination
src | Pointer to source
n | Number of u32 to be handled
Return values:
dst

Definition at line 1902 of file stm32wbxx_hal_pka.c.

Referenced by HAL_PKA_Arithmetic_GetResult(), HAL_PKA_MontgomeryParam_GetResult(), PKA_ARI_Set(), PKA_ECCMulFastMode_Set(), PKA_ModExpFastMode_Set(), PKA_ModInv_Set(), and PKA_ModRed_Set().

void PKA_Memcpy_u32_to_u8 | ( | uint8_t | dst[],
 |  | __IO const uint32_t | src[],
 |  | size_t | n
 | ) |  |

Copy uint32_t array to uint8_t array to fit PKA number representation.

Parameters:
dst | Pointer to destination
src | Pointer to source
n | Number of uint8_t to copy
Return values:
dst

Definition at line 1804 of file stm32wbxx_hal_pka.c.

Referenced by HAL_PKA_ECCMul_GetResult(), HAL_PKA_ECDSASign_GetResult(), HAL_PKA_ModExp_GetResult(), and HAL_PKA_RSACRTExp_GetResult().

void PKA_Memcpy_u8_to_u32 | ( | __IO uint32_t | dst[],
 |  | const uint8_t | src[],
 |  | size_t | n
 | ) |  |

Copy uint8_t array to uint32_t array to fit PKA number representation.

Parameters:
dst | Pointer to destination
src | Pointer to source
n | Number of uint8_t to copy (must be multiple of 4)
Return values:
dst

Definition at line 1854 of file stm32wbxx_hal_pka.c.

Referenced by PKA_ARI_Set(), PKA_ECCMul_Set(), PKA_ECCMulFastMode_Set(), PKA_ECDSASign_Set(), PKA_ECDSAVerif_Set(), PKA_ModExp_Set(), PKA_ModExpFastMode_Set(), PKA_ModInv_Set(), PKA_ModRed_Set(), PKA_MontgomeryParam_Set(), PKA_PointCheck_Set(), and PKA_RSACRTExp_Set().

void PKA_ModExp_Set | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_ModExpInTypeDef * | in
 | ) |  |

Set input parameters.

Parameters:
hpka | PKA handle
in | Input information

Definition at line 2019 of file stm32wbxx_hal_pka.c.

References PKA_ModExpInTypeDef::expSize, __PKA_HandleTypeDef::Instance, PKA_ModExpInTypeDef::OpSize, PKA_ModExpInTypeDef::pExp, PKA_GetBitSize_u8(), PKA_Memcpy_u8_to_u32(), PKA_ModExpInTypeDef::pMod, and PKA_ModExpInTypeDef::pOp1.

Referenced by HAL_PKA_ModExp(), and HAL_PKA_ModExp_IT().

void PKA_ModExpFastMode_Set | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_ModExpFastModeInTypeDef * | in
 | ) |  |

Set input parameters.

Parameters:
hpka | PKA handle
in | Input information

Definition at line 2045 of file stm32wbxx_hal_pka.c.

References PKA_ModExpFastModeInTypeDef::expSize, __PKA_HandleTypeDef::Instance, PKA_ModExpFastModeInTypeDef::OpSize, PKA_ModExpFastModeInTypeDef::pExp, PKA_GetBitSize_u8(), PKA_Memcpy_u32_to_u32(), PKA_Memcpy_u8_to_u32(), PKA_ModExpFastModeInTypeDef::pMod, PKA_ModExpFastModeInTypeDef::pMontgomeryParam, and PKA_ModExpFastModeInTypeDef::pOp1.

Referenced by HAL_PKA_ModExpFastMode(), and HAL_PKA_ModExpFastMode_IT().

void PKA_ModInv_Set | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_ModInvInTypeDef * | in
 | ) |  |

Set input parameters.

Parameters:
hpka | PKA handle
in | Input information

Definition at line 2328 of file stm32wbxx_hal_pka.c.

References __PKA_HandleTypeDef::Instance, PKA_GetBitSize_u32(), PKA_Memcpy_u32_to_u32(), PKA_Memcpy_u8_to_u32(), PKA_ModInvInTypeDef::pMod, PKA_ModInvInTypeDef::pOp1, and PKA_ModInvInTypeDef::size.

Referenced by HAL_PKA_ModInv(), and HAL_PKA_ModInv_IT().

void PKA_ModRed_Set | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_ModRedInTypeDef * | in
 | ) |  |

Set input parameters.

Parameters:
hpka | PKA handle
in | Input information

Definition at line 2347 of file stm32wbxx_hal_pka.c.

References __PKA_HandleTypeDef::Instance, PKA_ModRedInTypeDef::modSize, PKA_ModRedInTypeDef::OpSize, PKA_GetBitSize_u32(), PKA_GetBitSize_u8(), PKA_Memcpy_u32_to_u32(), PKA_Memcpy_u8_to_u32(), PKA_ModRedInTypeDef::pMod, and PKA_ModRedInTypeDef::pOp1.

Referenced by HAL_PKA_ModRed(), and HAL_PKA_ModRed_IT().

void PKA_MontgomeryParam_Set | ( | PKA_HandleTypeDef * | hpka,
 |  | const uint32_t | size,
 |  | const uint8_t * | pOp1
 | ) |  |

Set input parameters.

Parameters:
hpka | PKA handle
size | Size of the operand
pOp1 | Generic pointer to input data

Definition at line 2370 of file stm32wbxx_hal_pka.c.

References __PKA_HandleTypeDef::Instance, PKA_GetOptBitSize_u8(), and PKA_Memcpy_u8_to_u32().

Referenced by HAL_PKA_MontgomeryParam(), and HAL_PKA_MontgomeryParam_IT().

void PKA_PointCheck_Set | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_PointCheckInTypeDef * | in
 | ) |  |

Set input parameters.

Parameters:
hpka | PKA handle
in | Input information

Definition at line 2216 of file stm32wbxx_hal_pka.c.

References PKA_PointCheckInTypeDef::coefA, PKA_PointCheckInTypeDef::coefB, PKA_PointCheckInTypeDef::coefSign, __PKA_HandleTypeDef::Instance, PKA_PointCheckInTypeDef::modulus, PKA_PointCheckInTypeDef::modulusSize, PKA_GetOptBitSize_u8(), PKA_Memcpy_u8_to_u32(), PKA_PointCheckInTypeDef::pointX, and PKA_PointCheckInTypeDef::pointY.

Referenced by HAL_PKA_PointCheck(), and HAL_PKA_PointCheck_IT().

HAL_StatusTypeDef PKA_PollEndOfOperation | ( | PKA_HandleTypeDef * | hpka,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  |

Wait for operation completion or timeout.

Parameters:
hpka | PKA handle
Timeout | Timeout duration in millisecond.
Tickstart | Tick start value
Return values:
HAL status

Definition at line 1699 of file stm32wbxx_hal_pka.c.

References HAL_GetTick(), and __PKA_HandleTypeDef::Instance.

Referenced by PKA_Process().

HAL_StatusTypeDef PKA_Process | ( | PKA_HandleTypeDef * | hpka,
 |  | uint32_t | mode,
 |  | uint32_t | Timeout
 | ) |  |

Generic function to start a PKA operation in blocking mode.

Parameters:
hpka | PKA handle
mode | PKA operation
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1927 of file stm32wbxx_hal_pka.c.

References __PKA_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_PKA_ERROR_NONE, HAL_PKA_ERROR_TIMEOUT, HAL_PKA_STATE_BUSY, HAL_PKA_STATE_READY, __PKA_HandleTypeDef::Instance, PKA_CheckError(), PKA_PollEndOfOperation(), and __PKA_HandleTypeDef::State.

Referenced by HAL_PKA_Add(), HAL_PKA_Cmp(), HAL_PKA_ECCMul(), HAL_PKA_ECCMulFastMode(), HAL_PKA_ECDSASign(), HAL_PKA_ECDSAVerif(), HAL_PKA_ModAdd(), HAL_PKA_ModExp(), HAL_PKA_ModExpFastMode(), HAL_PKA_ModInv(), HAL_PKA_ModRed(), HAL_PKA_ModSub(), HAL_PKA_MontgomeryMul(), HAL_PKA_MontgomeryParam(), HAL_PKA_Mul(), HAL_PKA_PointCheck(), HAL_PKA_RSACRTExp(), and HAL_PKA_Sub().

HAL_StatusTypeDef PKA_Process_IT | ( | PKA_HandleTypeDef * | hpka,
 |  | uint32_t | mode
 | ) |  |

Generic function to start a PKA operation in non-blocking mode with Interrupt.

Parameters:
hpka | PKA handle
mode | PKA operation
Return values:
HAL status

Definition at line 1989 of file stm32wbxx_hal_pka.c.

References __PKA_HandleTypeDef::ErrorCode, HAL_PKA_ERROR_NONE, HAL_PKA_STATE_BUSY, HAL_PKA_STATE_READY, __PKA_HandleTypeDef::Instance, and __PKA_HandleTypeDef::State.

Referenced by HAL_PKA_Add_IT(), HAL_PKA_Cmp_IT(), HAL_PKA_ECCMul_IT(), HAL_PKA_ECCMulFastMode_IT(), HAL_PKA_ECDSASign_IT(), HAL_PKA_ECDSAVerif_IT(), HAL_PKA_ModAdd_IT(), HAL_PKA_ModExp_IT(), HAL_PKA_ModExpFastMode_IT(), HAL_PKA_ModInv_IT(), HAL_PKA_ModRed_IT(), HAL_PKA_ModSub_IT(), HAL_PKA_MontgomeryMul_IT(), HAL_PKA_MontgomeryParam_IT(), HAL_PKA_Mul_IT(), HAL_PKA_PointCheck_IT(), HAL_PKA_RSACRTExp_IT(), and HAL_PKA_Sub_IT().

void PKA_RSACRTExp_Set | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_RSACRTExpInTypeDef * | in
 | ) |  |

Set input parameters.

Parameters:
hpka | PKA handle
in | Input information

Definition at line 2181 of file stm32wbxx_hal_pka.c.

References __PKA_HandleTypeDef::Instance, PKA_GetBitSize_u8(), PKA_Memcpy_u8_to_u32(), PKA_RSACRTExpInTypeDef::popA, PKA_RSACRTExpInTypeDef::pOpDp, PKA_RSACRTExpInTypeDef::pOpDq, PKA_RSACRTExpInTypeDef::pOpQinv, PKA_RSACRTExpInTypeDef::pPrimeP, PKA_RSACRTExpInTypeDef::pPrimeQ, and PKA_RSACRTExpInTypeDef::size.

Referenced by HAL_PKA_RSACRTExp(), and HAL_PKA_RSACRTExp_IT().

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
PKA Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_PKA_Init (PKA_HandleTypeDef *hpka)
Initialize the PKA according to the specified parameters in the PKA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_PKA_DeInit (PKA_HandleTypeDef *hpka)
DeInitialize the PKA peripheral.
__weak void | HAL_PKA_MspInit (PKA_HandleTypeDef *hpka)
Initialize the PKA MSP.
__weak void | HAL_PKA_MspDeInit (PKA_HandleTypeDef *hpka)
DeInitialize the PKA MSP.
HAL_StatusTypeDef | HAL_PKA_RegisterCallback (PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID, pPKA_CallbackTypeDef pCallback)
Register a User PKA Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_PKA_UnRegisterCallback (PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID)
Unregister a PKA Callback PKA callback is redirected to the weak predefined callback.

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
             ##### Initialization and de-initialization functions  #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          deinitialize the PKAx peripheral:

      (+) User must implement HAL_PKA_MspInit() function in which he configures
          all related peripherals resources (CLOCK, IT and NVIC ).

      (+) Call the function HAL_PKA_Init() to configure the selected device with
          the selected configuration:
        (++) Security level

      (+) Call the function HAL_PKA_DeInit() to restore the default configuration
          of the selected PKAx peripheral.

Function Documentation

HAL_StatusTypeDef HAL_PKA_DeInit ( PKA_HandleTypeDef * hpka )

DeInitialize the PKA peripheral.

Parameters:
hpka PKA handle
Return values:
HAL status

Definition at line 399 of file stm32wbxx_hal_pka.c.

References assert_param, __PKA_HandleTypeDef::ErrorCode, HAL_PKA_ERROR_NONE, HAL_PKA_MspDeInit(), HAL_PKA_STATE_BUSY, HAL_PKA_STATE_RESET, __PKA_HandleTypeDef::Instance, __PKA_HandleTypeDef::MspDeInitCallback, and __PKA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PKA_Init ( PKA_HandleTypeDef * hpka )

Initialize the PKA according to the specified parameters in the PKA_InitTypeDef and initialize the associated handle.

Parameters:
hpka PKA handle
Return values:
HAL status

Definition at line 340 of file stm32wbxx_hal_pka.c.

References assert_param, __PKA_HandleTypeDef::ErrorCallback, __PKA_HandleTypeDef::ErrorCode, HAL_PKA_ERROR_NONE, HAL_PKA_ErrorCallback(), HAL_PKA_MspInit(), HAL_PKA_OperationCpltCallback(), HAL_PKA_STATE_BUSY, HAL_PKA_STATE_READY, HAL_PKA_STATE_RESET, __PKA_HandleTypeDef::Instance, __PKA_HandleTypeDef::MspInitCallback, __PKA_HandleTypeDef::OperationCpltCallback, and __PKA_HandleTypeDef::State.

void HAL_PKA_MspDeInit ( PKA_HandleTypeDef * hpka )

DeInitialize the PKA MSP.

Parameters:
hpka PKA handle
Return values:
None

Definition at line 466 of file stm32wbxx_hal_pka.c.

Referenced by HAL_PKA_DeInit(), and HAL_PKA_UnRegisterCallback().

void HAL_PKA_MspInit ( PKA_HandleTypeDef * hpka )

Initialize the PKA MSP.

Parameters:
hpka PKA handle
Return values:
None

Definition at line 451 of file stm32wbxx_hal_pka.c.

Referenced by HAL_PKA_Init(), and HAL_PKA_UnRegisterCallback().

HAL_StatusTypeDef HAL_PKA_RegisterCallback | ( | PKA_HandleTypeDef * | hpka,
 |  | HAL_PKA_CallbackIDTypeDef | CallbackID,
 |  | pPKA_CallbackTypeDef | pCallback
 | ) |  |

Register a User PKA Callback To be used instead of the weak predefined callback.

Parameters:
hpka | Pointer to a PKA_HandleTypeDef structure that contains the configuration information for the specified PKA.
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_PKA_OPERATION_COMPLETE_CB_ID End of operation callback ID
  • HAL_PKA_ERROR_CB_ID Error callback ID
  • HAL_PKA_MSPINIT_CB_ID MspInit callback ID
  • HAL_PKA_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 491 of file stm32wbxx_hal_pka.c.

References __PKA_HandleTypeDef::ErrorCallback, __PKA_HandleTypeDef::ErrorCode, HAL_PKA_ERROR_CB_ID, HAL_PKA_ERROR_INVALID_CALLBACK, HAL_PKA_MSPDEINIT_CB_ID, HAL_PKA_MSPINIT_CB_ID, HAL_PKA_OPERATION_COMPLETE_CB_ID, HAL_PKA_STATE_READY, HAL_PKA_STATE_RESET, __PKA_HandleTypeDef::MspDeInitCallback, __PKA_HandleTypeDef::MspInitCallback, __PKA_HandleTypeDef::OperationCpltCallback, and __PKA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PKA_UnRegisterCallback | ( | PKA_HandleTypeDef * | hpka,
 |  | HAL_PKA_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a PKA Callback PKA callback is redirected to the weak predefined callback.

Parameters:
hpka Pointer to a PKA_HandleTypeDef structure that contains the configuration information for the specified PKA.
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_PKA_OPERATION_COMPLETE_CB_ID End of operation callback ID
  • HAL_PKA_ERROR_CB_ID Error callback ID
  • HAL_PKA_MSPINIT_CB_ID MspInit callback ID
  • HAL_PKA_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
HAL status

Definition at line 578 of file stm32wbxx_hal_pka.c.

References __PKA_HandleTypeDef::ErrorCallback, __PKA_HandleTypeDef::ErrorCode, HAL_PKA_ERROR_CB_ID, HAL_PKA_ERROR_INVALID_CALLBACK, HAL_PKA_ErrorCallback(), HAL_PKA_MspDeInit(), HAL_PKA_MSPDEINIT_CB_ID, HAL_PKA_MspInit(), HAL_PKA_MSPINIT_CB_ID, HAL_PKA_OPERATION_COMPLETE_CB_ID, HAL_PKA_OperationCpltCallback(), HAL_PKA_STATE_READY, HAL_PKA_STATE_RESET, __PKA_HandleTypeDef::MspDeInitCallback, __PKA_HandleTypeDef::MspInitCallback, __PKA_HandleTypeDef::OperationCpltCallback, and __PKA_HandleTypeDef::State.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IO operation functions

Functions
IO operation functions
PKA Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_PKA_ModExp (PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in, uint32_t Timeout)
Modular exponentiation in blocking mode.
HAL_StatusTypeDef | HAL_PKA_ModExp_IT (PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in)
Modular exponentiation in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_PKA_ModExpFastMode (PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in, uint32_t Timeout)
Modular exponentiation in blocking mode.
HAL_StatusTypeDef | HAL_PKA_ModExpFastMode_IT (PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in)
Modular exponentiation in non-blocking mode with Interrupt.
void | HAL_PKA_ModExp_GetResult (PKA_HandleTypeDef *hpka, uint8_t *pRes)
Retrieve operation result.
HAL_StatusTypeDef | HAL_PKA_ECDSASign (PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in, uint32_t Timeout)
Sign a message using elliptic curves over prime fields in blocking mode.
HAL_StatusTypeDef | HAL_PKA_ECDSASign_IT (PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in)
Sign a message using elliptic curves over prime fields in non-blocking mode with Interrupt.
void | HAL_PKA_ECDSASign_GetResult (PKA_HandleTypeDef *hpka, PKA_ECDSASignOutTypeDef *out, PKA_ECDSASignOutExtParamTypeDef *outExt)
Retrieve operation result.
HAL_StatusTypeDef | HAL_PKA_ECDSAVerif (PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in, uint32_t Timeout)
Verify the validity of a signature using elliptic curves over prime fields in blocking mode.
HAL_StatusTypeDef | HAL_PKA_ECDSAVerif_IT (PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in)
Verify the validity of a signature using elliptic curves over prime fields in non-blocking mode with Interrupt.
uint32_t | HAL_PKA_ECDSAVerif_IsValidSignature (PKA_HandleTypeDef const *const hpka)
Return the result of the ECDSA verification operation.
HAL_StatusTypeDef | HAL_PKA_RSACRTExp (PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in, uint32_t Timeout)
RSA CRT exponentiation in blocking mode.
HAL_StatusTypeDef | HAL_PKA_RSACRTExp_IT (PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in)
RSA CRT exponentiation in non-blocking mode with Interrupt.
void | HAL_PKA_RSACRTExp_GetResult (PKA_HandleTypeDef *hpka, uint8_t *pRes)
Retrieve operation result.
HAL_StatusTypeDef | HAL_PKA_PointCheck (PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in, uint32_t Timeout)
Point on elliptic curve check in blocking mode.
HAL_StatusTypeDef | HAL_PKA_PointCheck_IT (PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in)
Point on elliptic curve check in non-blocking mode with Interrupt.
uint32_t | HAL_PKA_PointCheck_IsOnCurve (PKA_HandleTypeDef const *const hpka)
Return the result of the point check operation.
HAL_StatusTypeDef | HAL_PKA_ECCMul (PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in, uint32_t Timeout)
ECC scalar multiplication in blocking mode.
HAL_StatusTypeDef | HAL_PKA_ECCMul_IT (PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in)
ECC scalar multiplication in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_PKA_ECCMulFastMode (PKA_HandleTypeDef *hpka, PKA_ECCMulFastModeInTypeDef *in, uint32_t Timeout)
ECC scalar multiplication in blocking mode.
HAL_StatusTypeDef | HAL_PKA_ECCMulFastMode_IT (PKA_HandleTypeDef *hpka, PKA_ECCMulFastModeInTypeDef *in)
ECC scalar multiplication in non-blocking mode with Interrupt.
void | HAL_PKA_ECCMul_GetResult (PKA_HandleTypeDef *hpka, PKA_ECCMulOutTypeDef *out)
Retrieve operation result.
HAL_StatusTypeDef | HAL_PKA_Add (PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in, uint32_t Timeout)
Arithmetic addition in blocking mode.
HAL_StatusTypeDef | HAL_PKA_Add_IT (PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in)
Arithmetic addition in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_PKA_Sub (PKA_HandleTypeDef *hpka, PKA_SubInTypeDef *in, uint32_t Timeout)
Arithmetic substraction in blocking mode.
HAL_StatusTypeDef | HAL_PKA_Sub_IT (PKA_HandleTypeDef *hpka, PKA_SubInTypeDef *in)
Arithmetic substraction in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_PKA_Mul (PKA_HandleTypeDef *hpka, PKA_MulInTypeDef *in, uint32_t Timeout)
Arithmetic multiplication in blocking mode.
HAL_StatusTypeDef | HAL_PKA_Mul_IT (PKA_HandleTypeDef *hpka, PKA_MulInTypeDef *in)
Arithmetic multiplication in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_PKA_Cmp (PKA_HandleTypeDef *hpka, PKA_CmpInTypeDef *in, uint32_t Timeout)
Comparison in blocking mode.
HAL_StatusTypeDef | HAL_PKA_Cmp_IT (PKA_HandleTypeDef *hpka, PKA_CmpInTypeDef *in)
Comparison in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_PKA_ModAdd (PKA_HandleTypeDef *hpka, PKA_ModAddInTypeDef *in, uint32_t Timeout)
Modular addition in blocking mode.
HAL_StatusTypeDef | HAL_PKA_ModAdd_IT (PKA_HandleTypeDef *hpka, PKA_ModAddInTypeDef *in)
Modular addition in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_PKA_ModInv (PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in, uint32_t Timeout)
Modular inversion in blocking mode.
HAL_StatusTypeDef | HAL_PKA_ModInv_IT (PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in)
Modular inversion in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_PKA_ModSub (PKA_HandleTypeDef *hpka, PKA_ModSubInTypeDef *in, uint32_t Timeout)
Modular substraction in blocking mode.
HAL_StatusTypeDef | HAL_PKA_ModSub_IT (PKA_HandleTypeDef *hpka, PKA_ModSubInTypeDef *in)
Modular substraction in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_PKA_ModRed (PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in, uint32_t Timeout)
Modular reduction in blocking mode.
HAL_StatusTypeDef | HAL_PKA_ModRed_IT (PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in)
Modular reduction in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_PKA_MontgomeryMul (PKA_HandleTypeDef *hpka, PKA_MontgomeryMulInTypeDef *in, uint32_t Timeout)
Montgomery multiplication in blocking mode.
HAL_StatusTypeDef | HAL_PKA_MontgomeryMul_IT (PKA_HandleTypeDef *hpka, PKA_MontgomeryMulInTypeDef *in)
Montgomery multiplication in non-blocking mode with Interrupt.
void | HAL_PKA_Arithmetic_GetResult (PKA_HandleTypeDef *hpka, uint32_t *pRes)
Retrieve operation result.
HAL_StatusTypeDef | HAL_PKA_MontgomeryParam (PKA_HandleTypeDef *hpka, PKA_MontgomeryParamInTypeDef *in, uint32_t Timeout)
Montgomery parameter computation in blocking mode.
HAL_StatusTypeDef | HAL_PKA_MontgomeryParam_IT (PKA_HandleTypeDef *hpka, PKA_MontgomeryParamInTypeDef *in)
Montgomery parameter computation in non-blocking mode with Interrupt.
void | HAL_PKA_MontgomeryParam_GetResult (PKA_HandleTypeDef *hpka, uint32_t *pRes)
Retrieve operation result.
HAL_StatusTypeDef | HAL_PKA_Abort (PKA_HandleTypeDef *hpka)
Abort any ongoing operation.
void | HAL_PKA_RAMReset (PKA_HandleTypeDef *hpka)
Reset the PKA RAM.
void | HAL_PKA_IRQHandler (PKA_HandleTypeDef *hpka)
This function handles PKA event interrupt request.
__weak void | HAL_PKA_OperationCpltCallback (PKA_HandleTypeDef *hpka)
Process completed callback.
__weak void | HAL_PKA_ErrorCallback (PKA_HandleTypeDef *hpka)
Error callback.

Detailed Description

IO operation functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the PKA operations.

    (#) There are two modes of operation:

       (++) Blocking mode : The operation is performed in the polling mode.
            These functions return when data operation is completed.
       (++) No-Blocking mode : The operation is performed using Interrupts.
            These functions return immediatly.
            The end of the operation is indicated by HAL_PKA_ErrorCallback in case of error.
            The end of the operation is indicated by HAL_PKA_OperationCpltCallback in case of success.
            To stop any operation in interrupt mode, use HAL_PKA_Abort().

    (#) Blocking mode functions are :

        (++) HAL_PKA_ModExp()
        (++) HAL_PKA_ModExpFastMode()
        (++) HAL_PKA_ModExp_GetResult();

        (++) HAL_PKA_ECDSASign()
        (++) HAL_PKA_ECDSASign_GetResult();

        (++) HAL_PKA_ECDSAVerif()
        (++) HAL_PKA_ECDSAVerif_IsValidSignature();

        (++) HAL_PKA_RSACRTExp()
        (++) HAL_PKA_RSACRTExp_GetResult();

        (++) HAL_PKA_PointCheck()
        (++) HAL_PKA_PointCheck_IsOnCurve();

        (++) HAL_PKA_ECCMul()
        (++) HAL_PKA_ECCMulFastMode()
        (++) HAL_PKA_ECCMul_GetResult();

        (++) HAL_PKA_Add()
        (++) HAL_PKA_Sub()
        (++) HAL_PKA_Cmp()
        (++) HAL_PKA_Mul()
        (++) HAL_PKA_ModAdd()
        (++) HAL_PKA_ModSub()
        (++) HAL_PKA_ModInv()
        (++) HAL_PKA_ModRed()
        (++) HAL_PKA_MontgomeryMul()
        (++) HAL_PKA_Arithmetic_GetResult(P);

        (++) HAL_PKA_MontgomeryParam()
        (++) HAL_PKA_MontgomeryParam_GetResult();

    (#) No-Blocking mode functions with Interrupt are :

        (++) HAL_PKA_ModExp_IT();
        (++) HAL_PKA_ModExpFastMode_IT();
        (++) HAL_PKA_ModExp_GetResult();

        (++) HAL_PKA_ECDSASign_IT();
        (++) HAL_PKA_ECDSASign_GetResult();

        (++) HAL_PKA_ECDSAVerif_IT();
        (++) HAL_PKA_ECDSAVerif_IsValidSignature();

        (++) HAL_PKA_RSACRTExp_IT();
        (++) HAL_PKA_RSACRTExp_GetResult();

        (++) HAL_PKA_PointCheck_IT();
        (++) HAL_PKA_PointCheck_IsOnCurve();

        (++) HAL_PKA_ECCMul_IT();
        (++) HAL_PKA_ECCMulFastMode_IT();
        (++) HAL_PKA_ECCMul_GetResult();

        (++) HAL_PKA_Add_IT();
        (++) HAL_PKA_Sub_IT();
        (++) HAL_PKA_Cmp_IT();
        (++) HAL_PKA_Mul_IT();
        (++) HAL_PKA_ModAdd_IT();
        (++) HAL_PKA_ModSub_IT();
        (++) HAL_PKA_ModInv_IT();
        (++) HAL_PKA_ModRed_IT();
        (++) HAL_PKA_MontgomeryMul_IT();
        (++) HAL_PKA_Arithmetic_GetResult();

        (++) HAL_PKA_MontgomeryParam_IT();
        (++) HAL_PKA_MontgomeryParam_GetResult();

        (++) HAL_PKA_Abort();

Function Documentation

HAL_StatusTypeDef HAL_PKA_Abort ( PKA_HandleTypeDef * hpka )

Abort any ongoing operation.

Parameters:
hpka PKA handle
Return values:
HAL status

Definition at line 1494 of file stm32wbxx_hal_pka.c.

References __PKA_HandleTypeDef::ErrorCode, HAL_PKA_ERROR_NONE, HAL_PKA_STATE_READY, __PKA_HandleTypeDef::Instance, and __PKA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PKA_Add | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_AddInTypeDef * | in,
 |  | uint32_t | Timeout
 | ) |  |

Arithmetic addition in blocking mode.

Parameters:
hpka | PKA handle
in | Input information
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1107 of file stm32wbxx_hal_pka.c.

References PKA_ARI_Set(), PKA_MODE_ARITHMETIC_ADD, PKA_Process(), PKA_AddInTypeDef::pOp1, PKA_AddInTypeDef::pOp2, and PKA_AddInTypeDef::size.

HAL_StatusTypeDef HAL_PKA_Add_IT | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_AddInTypeDef * | in
 | ) |  |

Arithmetic addition in non-blocking mode with Interrupt.

Parameters:
hpka | PKA handle
in | Input information
Return values:
HAL status

Definition at line 1122 of file stm32wbxx_hal_pka.c.

References PKA_ARI_Set(), PKA_MODE_ARITHMETIC_ADD, PKA_Process_IT(), PKA_AddInTypeDef::pOp1, PKA_AddInTypeDef::pOp2, and PKA_AddInTypeDef::size.

void HAL_PKA_Arithmetic_GetResult | ( | PKA_HandleTypeDef * | hpka,
 |  | uint32_t * | pRes
 | ) |  |

Retrieve operation result.

Parameters:
hpka | PKA handle
pRes | Pointer to memory location to receive the result of the operation

Definition at line 1384 of file stm32wbxx_hal_pka.c.

References __PKA_HandleTypeDef::Instance, PKA_Memcpy_u32_to_u32(), PKA_MODE_ARITHMETIC_ADD, PKA_MODE_ARITHMETIC_MUL, PKA_MODE_ARITHMETIC_SUB, PKA_MODE_COMPARISON, PKA_MODE_MODULAR_ADD, PKA_MODE_MODULAR_INV, PKA_MODE_MODULAR_RED, PKA_MODE_MODULAR_SUB, and PKA_MODE_MONTGOMERY_MUL.

HAL_StatusTypeDef HAL_PKA_Cmp | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_CmpInTypeDef * | in,
 |  | uint32_t | Timeout
 | ) |  |

Comparison in blocking mode.

Parameters:
hpka | PKA handle
in | Input information
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1200 of file stm32wbxx_hal_pka.c.

References PKA_ARI_Set(), PKA_MODE_COMPARISON, PKA_Process(), PKA_AddInTypeDef::pOp1, PKA_AddInTypeDef::pOp2, and PKA_AddInTypeDef::size.

HAL_StatusTypeDef HAL_PKA_Cmp_IT | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_CmpInTypeDef * | in
 | ) |  |

Comparison in non-blocking mode with Interrupt.

Parameters:
hpka | PKA handle
in | Input information
Return values:
HAL status

Definition at line 1215 of file stm32wbxx_hal_pka.c.

References PKA_ARI_Set(), PKA_MODE_COMPARISON, PKA_Process_IT(), PKA_AddInTypeDef::pOp1, PKA_AddInTypeDef::pOp2, and PKA_AddInTypeDef::size.

HAL_StatusTypeDef HAL_PKA_ECCMul | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_ECCMulInTypeDef * | in,
 |  | uint32_t | Timeout
 | ) |  |

ECC scalar multiplication in blocking mode.

Parameters:
hpka | PKA handle
in | Input information
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1023 of file stm32wbxx_hal_pka.c.

References PKA_ECCMul_Set(), PKA_MODE_ECC_MUL, and PKA_Process().

void HAL_PKA_ECCMul_GetResult | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_ECCMulOutTypeDef * | out
 | ) |  |

Retrieve operation result.

Parameters:
hpka | PKA handle
out | Output information
Return values:
HAL status

Definition at line 1084 of file stm32wbxx_hal_pka.c.

References __PKA_HandleTypeDef::Instance, PKA_Memcpy_u32_to_u8(), PKA_ECDSASignOutExtParamTypeDef::ptX, and PKA_ECDSASignOutExtParamTypeDef::ptY.

HAL_StatusTypeDef HAL_PKA_ECCMul_IT | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_ECCMulInTypeDef * | in
 | ) |  |

ECC scalar multiplication in non-blocking mode with Interrupt.

Parameters:
hpka | PKA handle
in | Input information
Return values:
HAL status

Definition at line 1038 of file stm32wbxx_hal_pka.c.

References PKA_ECCMul_Set(), PKA_MODE_ECC_MUL, and PKA_Process_IT().

HAL_StatusTypeDef HAL_PKA_ECCMulFastMode | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_ECCMulFastModeInTypeDef * | in,
 |  | uint32_t | Timeout
 | ) |  |

ECC scalar multiplication in blocking mode.

Parameters:
hpka | PKA handle
in | Input information
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1054 of file stm32wbxx_hal_pka.c.

References PKA_ECCMulFastMode_Set(), PKA_MODE_ECC_MUL_FAST_MODE, and PKA_Process().

HAL_StatusTypeDef HAL_PKA_ECCMulFastMode_IT | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_ECCMulFastModeInTypeDef * | in
 | ) |  |

ECC scalar multiplication in non-blocking mode with Interrupt.

Parameters:
hpka | PKA handle
in | Input information
Return values:
HAL status

Definition at line 1069 of file stm32wbxx_hal_pka.c.

References PKA_ECCMulFastMode_Set(), PKA_MODE_ECC_MUL_FAST_MODE, and PKA_Process_IT().

HAL_StatusTypeDef HAL_PKA_ECDSASign | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_ECDSASignInTypeDef * | in,
 |  | uint32_t | Timeout
 | ) |  |

Sign a message using elliptic curves over prime fields in blocking mode.

Parameters:
hpka | PKA handle
in | Input information
Timeout | Timeout duration
Return values:
HAL status

Definition at line 834 of file stm32wbxx_hal_pka.c.

References PKA_ECDSASign_Set(), PKA_MODE_ECDSA_SIGNATURE, and PKA_Process().

void HAL_PKA_ECDSASign_GetResult | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_ECDSASignOutTypeDef * | out,
 |  | PKA_ECDSASignOutExtParamTypeDef * | outExt
 | ) |  |

Retrieve operation result.

Parameters:
hpka | PKA handle
out | Output information
outExt | Additionnal Output information (facultative)

Definition at line 864 of file stm32wbxx_hal_pka.c.

References __PKA_HandleTypeDef::Instance, PKA_Memcpy_u32_to_u8(), PKA_ECDSASignOutExtParamTypeDef::ptX, PKA_ECDSASignOutExtParamTypeDef::ptY, PKA_ECDSASignOutTypeDef::RSign, and PKA_ECDSASignOutTypeDef::SSign.

HAL_StatusTypeDef HAL_PKA_ECDSASign_IT | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_ECDSASignInTypeDef * | in
 | ) |  |

Sign a message using elliptic curves over prime fields in non-blocking mode with Interrupt.

Parameters:
hpka | PKA handle
in | Input information
Return values:
HAL status

Definition at line 849 of file stm32wbxx_hal_pka.c.

References PKA_ECDSASign_Set(), PKA_MODE_ECDSA_SIGNATURE, and PKA_Process_IT().

HAL_StatusTypeDef HAL_PKA_ECDSAVerif | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_ECDSAVerifInTypeDef * | in,
 |  | uint32_t | Timeout
 | ) |  |

Verify the validity of a signature using elliptic curves over prime fields in blocking mode.

Parameters:
hpka | PKA handle
in | Input information
Timeout | Timeout duration
Return values:
HAL status

Definition at line 892 of file stm32wbxx_hal_pka.c.

References PKA_ECDSAVerif_Set(), PKA_MODE_ECDSA_VERIFICATION, and PKA_Process().

uint32_t HAL_PKA_ECDSAVerif_IsValidSignature ( PKA_HandleTypeDef const *const hpka )

Return the result of the ECDSA verification operation.

Parameters:
hpka PKA handle
Return values:
1 if signature is verified, 0 in other case

Definition at line 921 of file stm32wbxx_hal_pka.c.

References __PKA_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PKA_ECDSAVerif_IT | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_ECDSAVerifInTypeDef * | in
 | ) |  |

Verify the validity of a signature using elliptic curves over prime fields in non-blocking mode with Interrupt.

Parameters:
hpka | PKA handle
in | Input information
Return values:
HAL status

Definition at line 907 of file stm32wbxx_hal_pka.c.

References PKA_ECDSAVerif_Set(), PKA_MODE_ECDSA_VERIFICATION, and PKA_Process_IT().

void HAL_PKA_ErrorCallback ( PKA_HandleTypeDef * hpka )

Error callback.

Parameters:
hpka PKA handle
Return values:
None

Definition at line 1619 of file stm32wbxx_hal_pka.c.

Referenced by HAL_PKA_Init(), HAL_PKA_IRQHandler(), and HAL_PKA_UnRegisterCallback().

void HAL_PKA_IRQHandler ( PKA_HandleTypeDef * hpka )

This function handles PKA event interrupt request.

Parameters:
hpka PKA handle
Return values:
None

Definition at line 1537 of file stm32wbxx_hal_pka.c.

References __HAL_PKA_CLEAR_FLAG, __HAL_PKA_GET_FLAG, __HAL_PKA_GET_IT_SOURCE, __PKA_HandleTypeDef::ErrorCallback, __PKA_HandleTypeDef::ErrorCode, HAL_PKA_ERROR_ADDRERR, HAL_PKA_ERROR_NONE, HAL_PKA_ERROR_OPERATION, HAL_PKA_ERROR_RAMERR, HAL_PKA_ErrorCallback(), HAL_PKA_OperationCpltCallback(), HAL_PKA_STATE_READY, __PKA_HandleTypeDef::Instance, __PKA_HandleTypeDef::OperationCpltCallback, PKA_FLAG_ADDRERR, PKA_FLAG_PROCEND, PKA_FLAG_RAMERR, PKA_GetMode(), PKA_IT_ADDRERR, PKA_IT_PROCEND, PKA_IT_RAMERR, PKA_MODE_ECDSA_SIGNATURE, and __PKA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PKA_ModAdd | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_ModAddInTypeDef * | in,
 |  | uint32_t | Timeout
 | ) |  |

Modular addition in blocking mode.

Parameters:
hpka | PKA handle
in | Input information
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1231 of file stm32wbxx_hal_pka.c.

References PKA_ARI_Set(), PKA_MODE_MODULAR_ADD, PKA_Process(), PKA_ModAddInTypeDef::pOp1, PKA_ModAddInTypeDef::pOp2, PKA_ModAddInTypeDef::pOp3, and PKA_ModAddInTypeDef::size.

HAL_StatusTypeDef HAL_PKA_ModAdd_IT | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_ModAddInTypeDef * | in
 | ) |  |

Modular addition in non-blocking mode with Interrupt.

Parameters:
hpka | PKA handle
in | Input information
Return values:
HAL status

Definition at line 1246 of file stm32wbxx_hal_pka.c.

References PKA_ARI_Set(), PKA_MODE_MODULAR_ADD, PKA_Process_IT(), PKA_ModAddInTypeDef::pOp1, PKA_ModAddInTypeDef::pOp2, PKA_ModAddInTypeDef::pOp3, and PKA_ModAddInTypeDef::size.

HAL_StatusTypeDef HAL_PKA_ModExp | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_ModExpInTypeDef * | in,
 |  | uint32_t | Timeout
 | ) |  |

Modular exponentiation in blocking mode.

Parameters:
hpka | PKA handle
in | Input information
Timeout | Timeout duration
Return values:
HAL status

Definition at line 755 of file stm32wbxx_hal_pka.c.

References PKA_MODE_MODULAR_EXP, PKA_ModExp_Set(), and PKA_Process().

void HAL_PKA_ModExp_GetResult | ( | PKA_HandleTypeDef * | hpka,
 |  | uint8_t * | pRes
 | ) |  |

Retrieve operation result.

Parameters:
hpka | PKA handle
pRes | Output buffer
Return values:
HAL status

Definition at line 816 of file stm32wbxx_hal_pka.c.

References __PKA_HandleTypeDef::Instance, and PKA_Memcpy_u32_to_u8().

HAL_StatusTypeDef HAL_PKA_ModExp_IT | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_ModExpInTypeDef * | in
 | ) |  |

Modular exponentiation in non-blocking mode with Interrupt.

Parameters:
hpka | PKA handle
in | Input information
Return values:
HAL status

Definition at line 770 of file stm32wbxx_hal_pka.c.

References PKA_MODE_MODULAR_EXP, PKA_ModExp_Set(), and PKA_Process_IT().

HAL_StatusTypeDef HAL_PKA_ModExpFastMode | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_ModExpFastModeInTypeDef * | in,
 |  | uint32_t | Timeout
 | ) |  |

Modular exponentiation in blocking mode.

Parameters:
hpka | PKA handle
in | Input information
Timeout | Timeout duration
Return values:
HAL status

Definition at line 786 of file stm32wbxx_hal_pka.c.

References PKA_MODE_MODULAR_EXP_FAST_MODE, PKA_ModExpFastMode_Set(), and PKA_Process().

HAL_StatusTypeDef HAL_PKA_ModExpFastMode_IT | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_ModExpFastModeInTypeDef * | in
 | ) |  |

Modular exponentiation in non-blocking mode with Interrupt.

Parameters:
hpka | PKA handle
in | Input information
Return values:
HAL status

Definition at line 801 of file stm32wbxx_hal_pka.c.

References PKA_MODE_MODULAR_EXP_FAST_MODE, PKA_ModExpFastMode_Set(), and PKA_Process_IT().

HAL_StatusTypeDef HAL_PKA_ModInv | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_ModInvInTypeDef * | in,
 |  | uint32_t | Timeout
 | ) |  |

Modular inversion in blocking mode.

Parameters:
hpka | PKA handle
in | Input information
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1262 of file stm32wbxx_hal_pka.c.

References PKA_MODE_MODULAR_INV, PKA_ModInv_Set(), and PKA_Process().

HAL_StatusTypeDef HAL_PKA_ModInv_IT | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_ModInvInTypeDef * | in
 | ) |  |

Modular inversion in non-blocking mode with Interrupt.

Parameters:
hpka | PKA handle
in | Input information
Return values:
HAL status

Definition at line 1277 of file stm32wbxx_hal_pka.c.

References PKA_MODE_MODULAR_INV, PKA_ModInv_Set(), and PKA_Process_IT().

HAL_StatusTypeDef HAL_PKA_ModRed | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_ModRedInTypeDef * | in,
 |  | uint32_t | Timeout
 | ) |  |

Modular reduction in blocking mode.

Parameters:
hpka | PKA handle
in | Input information
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1324 of file stm32wbxx_hal_pka.c.

References PKA_MODE_MODULAR_RED, PKA_ModRed_Set(), and PKA_Process().

HAL_StatusTypeDef HAL_PKA_ModRed_IT | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_ModRedInTypeDef * | in
 | ) |  |

Modular reduction in non-blocking mode with Interrupt.

Parameters:
hpka | PKA handle
in | Input information
Return values:
HAL status

Definition at line 1339 of file stm32wbxx_hal_pka.c.

References PKA_MODE_MODULAR_RED, PKA_ModRed_Set(), and PKA_Process_IT().

HAL_StatusTypeDef HAL_PKA_ModSub | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_ModSubInTypeDef * | in,
 |  | uint32_t | Timeout
 | ) |  |

Modular substraction in blocking mode.

Parameters:
hpka | PKA handle
in | Input information
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1293 of file stm32wbxx_hal_pka.c.

References PKA_ARI_Set(), PKA_MODE_MODULAR_SUB, PKA_Process(), PKA_ModAddInTypeDef::pOp1, PKA_ModAddInTypeDef::pOp2, PKA_ModAddInTypeDef::pOp3, and PKA_ModAddInTypeDef::size.

HAL_StatusTypeDef HAL_PKA_ModSub_IT | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_ModSubInTypeDef * | in
 | ) |  |

Modular substraction in non-blocking mode with Interrupt.

Parameters:
hpka | PKA handle
in | Input information
Return values:
HAL status

Definition at line 1308 of file stm32wbxx_hal_pka.c.

References PKA_ARI_Set(), PKA_MODE_MODULAR_SUB, PKA_Process_IT(), PKA_ModAddInTypeDef::pOp1, PKA_ModAddInTypeDef::pOp2, PKA_ModAddInTypeDef::pOp3, and PKA_ModAddInTypeDef::size.

HAL_StatusTypeDef HAL_PKA_MontgomeryMul | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_MontgomeryMulInTypeDef * | in,
 |  | uint32_t | Timeout
 | ) |  |

Montgomery multiplication in blocking mode.

Parameters:
hpka | PKA handle
in | Input information
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1355 of file stm32wbxx_hal_pka.c.

References PKA_ARI_Set(), PKA_MODE_MONTGOMERY_MUL, PKA_Process(), PKA_ModAddInTypeDef::pOp1, PKA_ModAddInTypeDef::pOp2, PKA_ModAddInTypeDef::pOp3, and PKA_ModAddInTypeDef::size.

HAL_StatusTypeDef HAL_PKA_MontgomeryMul_IT | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_MontgomeryMulInTypeDef * | in
 | ) |  |

Montgomery multiplication in non-blocking mode with Interrupt.

Parameters:
hpka | PKA handle
in | Input information
Return values:
HAL status

Definition at line 1370 of file stm32wbxx_hal_pka.c.

References PKA_ARI_Set(), PKA_MODE_MONTGOMERY_MUL, PKA_Process_IT(), PKA_ModAddInTypeDef::pOp1, PKA_ModAddInTypeDef::pOp2, PKA_ModAddInTypeDef::pOp3, and PKA_ModAddInTypeDef::size.

HAL_StatusTypeDef HAL_PKA_MontgomeryParam | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_MontgomeryParamInTypeDef * | in,
 |  | uint32_t | Timeout
 | ) |  |

Montgomery parameter computation in blocking mode.

Parameters:
hpka | PKA handle
in | Input information
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1448 of file stm32wbxx_hal_pka.c.

References PKA_MODE_MONTGOMERY_PARAM, PKA_MontgomeryParam_Set(), PKA_Process(), PKA_MontgomeryParamInTypeDef::pOp1, and PKA_MontgomeryParamInTypeDef::size.

void HAL_PKA_MontgomeryParam_GetResult | ( | PKA_HandleTypeDef * | hpka,
 |  | uint32_t * | pRes
 | ) |  |

Retrieve operation result.

Parameters:
hpka | PKA handle
pRes | pointer to buffer where the result will be copied
Return values:
HAL status

Definition at line 1478 of file stm32wbxx_hal_pka.c.

References __PKA_HandleTypeDef::Instance, and PKA_Memcpy_u32_to_u32().

HAL_StatusTypeDef HAL_PKA_MontgomeryParam_IT | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_MontgomeryParamInTypeDef * | in
 | ) |  |

Montgomery parameter computation in non-blocking mode with Interrupt.

Parameters:
hpka | PKA handle
in | Input information
Return values:
HAL status

Definition at line 1463 of file stm32wbxx_hal_pka.c.

References PKA_MODE_MONTGOMERY_PARAM, PKA_MontgomeryParam_Set(), PKA_Process_IT(), PKA_MontgomeryParamInTypeDef::pOp1, and PKA_MontgomeryParamInTypeDef::size.

HAL_StatusTypeDef HAL_PKA_Mul | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_MulInTypeDef * | in,
 |  | uint32_t | Timeout
 | ) |  |

Arithmetic multiplication in blocking mode.

Parameters:
hpka | PKA handle
in | Input information
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1169 of file stm32wbxx_hal_pka.c.

References PKA_ARI_Set(), PKA_MODE_ARITHMETIC_MUL, PKA_Process(), PKA_AddInTypeDef::pOp1, PKA_AddInTypeDef::pOp2, and PKA_AddInTypeDef::size.

HAL_StatusTypeDef HAL_PKA_Mul_IT | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_MulInTypeDef * | in
 | ) |  |

Arithmetic multiplication in non-blocking mode with Interrupt.

Parameters:
hpka | PKA handle
in | Input information
Return values:
HAL status

Definition at line 1184 of file stm32wbxx_hal_pka.c.

References PKA_ARI_Set(), PKA_MODE_ARITHMETIC_MUL, PKA_Process_IT(), PKA_AddInTypeDef::pOp1, PKA_AddInTypeDef::pOp2, and PKA_AddInTypeDef::size.

void HAL_PKA_OperationCpltCallback ( PKA_HandleTypeDef * hpka )

Process completed callback.

Parameters:
hpka PKA handle
Return values:
None

Definition at line 1604 of file stm32wbxx_hal_pka.c.

Referenced by HAL_PKA_Init(), HAL_PKA_IRQHandler(), and HAL_PKA_UnRegisterCallback().

HAL_StatusTypeDef HAL_PKA_PointCheck | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_PointCheckInTypeDef * | in,
 |  | uint32_t | Timeout
 | ) |  |

Point on elliptic curve check in blocking mode.

Parameters:
hpka | PKA handle
in | Input information
Timeout | Timeout duration
Return values:
HAL status

Definition at line 981 of file stm32wbxx_hal_pka.c.

References PKA_MODE_POINT_CHECK, PKA_PointCheck_Set(), and PKA_Process().

uint32_t HAL_PKA_PointCheck_IsOnCurve ( PKA_HandleTypeDef const *const hpka )

Return the result of the point check operation.

Parameters:
hpka PKA handle
Return values:
1 if point is on curve, 0 in other case

Definition at line 1010 of file stm32wbxx_hal_pka.c.

References __PKA_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PKA_PointCheck_IT | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_PointCheckInTypeDef * | in
 | ) |  |

Point on elliptic curve check in non-blocking mode with Interrupt.

Parameters:
hpka | PKA handle
in | Input information
Return values:
HAL status

Definition at line 996 of file stm32wbxx_hal_pka.c.

References PKA_MODE_POINT_CHECK, PKA_PointCheck_Set(), and PKA_Process_IT().

void HAL_PKA_RAMReset ( PKA_HandleTypeDef * hpka )

Reset the PKA RAM.

Parameters:
hpka PKA handle
Return values:
None

Definition at line 1520 of file stm32wbxx_hal_pka.c.

References __PKA_HandleTypeDef::Instance, and PKA_RAM_SIZE.

HAL_StatusTypeDef HAL_PKA_RSACRTExp | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_RSACRTExpInTypeDef * | in,
 |  | uint32_t | Timeout
 | ) |  |

RSA CRT exponentiation in blocking mode.

Parameters:
hpka | PKA handle
in | Input information
Timeout | Timeout duration
Return values:
HAL status

Definition at line 934 of file stm32wbxx_hal_pka.c.

References PKA_MODE_RSA_CRT_EXP, PKA_Process(), and PKA_RSACRTExp_Set().

void HAL_PKA_RSACRTExp_GetResult | ( | PKA_HandleTypeDef * | hpka,
 |  | uint8_t * | pRes
 | ) |  |

Retrieve operation result.

Parameters:
hpka | PKA handle
pRes | Pointer to memory location to receive the result of the operation
Return values:
HAL status

Definition at line 964 of file stm32wbxx_hal_pka.c.

References __PKA_HandleTypeDef::Instance, and PKA_Memcpy_u32_to_u8().

HAL_StatusTypeDef HAL_PKA_RSACRTExp_IT | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_RSACRTExpInTypeDef * | in
 | ) |  |

RSA CRT exponentiation in non-blocking mode with Interrupt.

Parameters:
hpka | PKA handle
in | Input information
Return values:
HAL status

Definition at line 949 of file stm32wbxx_hal_pka.c.

References PKA_MODE_RSA_CRT_EXP, PKA_Process_IT(), and PKA_RSACRTExp_Set().

HAL_StatusTypeDef HAL_PKA_Sub | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_SubInTypeDef * | in,
 |  | uint32_t | Timeout
 | ) |  |

Arithmetic substraction in blocking mode.

Parameters:
hpka | PKA handle
in | Input information
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1138 of file stm32wbxx_hal_pka.c.

References PKA_ARI_Set(), PKA_MODE_ARITHMETIC_SUB, PKA_Process(), PKA_AddInTypeDef::pOp1, PKA_AddInTypeDef::pOp2, and PKA_AddInTypeDef::size.

HAL_StatusTypeDef HAL_PKA_Sub_IT | ( | PKA_HandleTypeDef * | hpka,
 |  | PKA_SubInTypeDef * | in
 | ) |  |

Arithmetic substraction in non-blocking mode with Interrupt.

Parameters:
hpka | PKA handle
in | Input information
Return values:
HAL status

Definition at line 1153 of file stm32wbxx_hal_pka.c.

References PKA_ARI_Set(), PKA_MODE_ARITHMETIC_SUB, PKA_Process_IT(), PKA_AddInTypeDef::pOp1, PKA_AddInTypeDef::pOp2, and PKA_AddInTypeDef::size.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Peripheral State and Error functions

Functions
Peripheral State and Error functions
PKA Exported Functions

Peripheral State and Error functions. More...

Functions

HAL_PKA_StateTypeDef | HAL_PKA_GetState (PKA_HandleTypeDef *hpka)
Return the PKA handle state.
uint32_t | HAL_PKA_GetError (PKA_HandleTypeDef *hpka)
Return the PKA error code.

Detailed Description

Peripheral State and Error functions.

 ===============================================================================
            ##### Peripheral State and Error functions #####
 ===============================================================================
    [..]
    This subsection permit to get in run-time the status of the peripheral.

Function Documentation

uint32_t HAL_PKA_GetError ( PKA_HandleTypeDef * hpka )

Return the PKA error code.

Parameters:
hpka PKA handle
Return values:
PKA error code

Definition at line 1663 of file stm32wbxx_hal_pka.c.

References __PKA_HandleTypeDef::ErrorCode.

HAL_PKA_StateTypeDef HAL_PKA_GetState ( PKA_HandleTypeDef * hpka )

Return the PKA handle state.

Parameters:
hpka PKA handle
Return values:
HAL status

Definition at line 1652 of file stm32wbxx_hal_pka.c.

References __PKA_HandleTypeDef::State.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: HAL callback ID enumeration

Enumerations
HAL callback ID enumeration
PKA Exported Types

Enumerations

enum HAL_PKA_CallbackIDTypeDef { HAL_PKA_OPERATION_COMPLETE_CB_ID = 0x00U, HAL_PKA_ERROR_CB_ID = 0x01U, HAL_PKA_MSPINIT_CB_ID = 0x02U, HAL_PKA_MSPDEINIT_CB_ID = 0x03U }

Enumeration Type Documentation

enum HAL_PKA_CallbackIDTypeDef
Enumerator:
HAL_PKA_OPERATION_COMPLETE_CB_ID

PKA End of operation callback ID

HAL_PKA_ERROR_CB_ID

PKA Error callback ID

HAL_PKA_MSPINIT_CB_ID

PKA Msp Init callback ID

HAL_PKA_MSPDEINIT_CB_ID

PKA Msp DeInit callback ID

Definition at line 67 of file stm32wbxx_hal_pka.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PKA Error Code definition

Defines
PKA Error Code definition
PKA Exported Types

PKA Error Code definition. More...

Defines

#define | HAL_PKA_ERROR_NONE (0x00000000U)
#define | HAL_PKA_ERROR_ADDRERR (0x00000001U)
#define | HAL_PKA_ERROR_RAMERR (0x00000002U)
#define | HAL_PKA_ERROR_TIMEOUT (0x00000004U)
#define | HAL_PKA_ERROR_OPERATION (0x00000008U)
#define | HAL_PKA_ERROR_INVALID_CALLBACK (0x00000010U)

Detailed Description

PKA Error Code definition.

Define Documentation

#define HAL_PKA_ERROR_ADDRERR (0x00000001U)

Definition at line 86 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_IRQHandler(), and PKA_CheckError().

#define HAL_PKA_ERROR_INVALID_CALLBACK (0x00000010U)

Invalid Callback error

Definition at line 91 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_RegisterCallback(), and HAL_PKA_UnRegisterCallback().

#define HAL_PKA_ERROR_NONE (0x00000000U)

Definition at line 85 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_Abort(), HAL_PKA_DeInit(), HAL_PKA_Init(), HAL_PKA_IRQHandler(), PKA_CheckError(), PKA_Process(), and PKA_Process_IT().

#define HAL_PKA_ERROR_OPERATION (0x00000008U)

Definition at line 89 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_IRQHandler(), and PKA_CheckError().

#define HAL_PKA_ERROR_RAMERR (0x00000002U)

Definition at line 87 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_IRQHandler(), and PKA_CheckError().

#define HAL_PKA_ERROR_TIMEOUT (0x00000004U)

Definition at line 88 of file stm32wbxx_hal_pka.h.

Referenced by PKA_Process().

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PKA handle Structure definition

Data Structures | Typedefs
PKA handle Structure definition
PKA Exported Types

PKA handle Structure definition. More...

Data Structures

struct | __PKA_HandleTypeDef

Typedefs

typedef struct __PKA_HandleTypeDef | PKA_HandleTypeDef

Detailed Description

PKA handle Structure definition.

Typedef Documentation

typedef struct __PKA_HandleTypeDef PKA_HandleTypeDef
Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: __PKA_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__PKA_HandleTypeDef Struct Reference
PKA handle Structure definition

#include <stm32wbxx_hal_pka.h>

Data Fields

PKA_TypeDef * | Instance
__IO HAL_PKA_StateTypeDef | State
__IO uint32_t | ErrorCode
void(* | OperationCpltCallback )(struct __PKA_HandleTypeDef *hpka)
void(* | ErrorCallback )(struct __PKA_HandleTypeDef *hpka)
void(* | MspInitCallback )(struct __PKA_HandleTypeDef *hpka)
void(* | MspDeInitCallback )(struct __PKA_HandleTypeDef *hpka)

Detailed Description

Definition at line 102 of file stm32wbxx_hal_pka.h.

Field Documentation

void(* __PKA_HandleTypeDef::ErrorCallback)(struct __PKA_HandleTypeDef *hpka)

PKA Error callback

Definition at line 109 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_Init(), HAL_PKA_IRQHandler(), HAL_PKA_RegisterCallback(), and HAL_PKA_UnRegisterCallback().

__IO uint32_t __PKA_HandleTypeDef::ErrorCode

PKA Error code

Definition at line 106 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_Abort(), HAL_PKA_DeInit(), HAL_PKA_GetError(), HAL_PKA_Init(), HAL_PKA_IRQHandler(), HAL_PKA_RegisterCallback(), HAL_PKA_UnRegisterCallback(), PKA_Process(), and PKA_Process_IT().

PKA_TypeDef* __PKA_HandleTypeDef::Instance

Register base address

Definition at line 104 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_Abort(), HAL_PKA_Arithmetic_GetResult(), HAL_PKA_DeInit(), HAL_PKA_ECCMul_GetResult(), HAL_PKA_ECDSASign_GetResult(), HAL_PKA_ECDSAVerif_IsValidSignature(), HAL_PKA_Init(), HAL_PKA_IRQHandler(), HAL_PKA_ModExp_GetResult(), HAL_PKA_MontgomeryParam_GetResult(), HAL_PKA_PointCheck_IsOnCurve(), HAL_PKA_RAMReset(), HAL_PKA_RSACRTExp_GetResult(), PKA_ARI_Set(), PKA_CheckError(), PKA_ECCMul_Set(), PKA_ECCMulFastMode_Set(), PKA_ECDSASign_Set(), PKA_ECDSAVerif_Set(), PKA_GetMode(), PKA_ModExp_Set(), PKA_ModExpFastMode_Set(), PKA_ModInv_Set(), PKA_ModRed_Set(), PKA_MontgomeryParam_Set(), PKA_PointCheck_Set(), PKA_PollEndOfOperation(), PKA_Process(), PKA_Process_IT(), and PKA_RSACRTExp_Set().

void(* __PKA_HandleTypeDef::MspDeInitCallback)(struct __PKA_HandleTypeDef *hpka)

PKA Msp DeInit callback

Definition at line 111 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_DeInit(), HAL_PKA_RegisterCallback(), and HAL_PKA_UnRegisterCallback().

void(* __PKA_HandleTypeDef::MspInitCallback)(struct __PKA_HandleTypeDef *hpka)

PKA Msp Init callback

Definition at line 110 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_Init(), HAL_PKA_RegisterCallback(), and HAL_PKA_UnRegisterCallback().

void(* __PKA_HandleTypeDef::OperationCpltCallback)(struct __PKA_HandleTypeDef *hpka)

PKA End of operation callback

Definition at line 108 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_Init(), HAL_PKA_IRQHandler(), HAL_PKA_RegisterCallback(), and HAL_PKA_UnRegisterCallback().

__IO HAL_PKA_StateTypeDef __PKA_HandleTypeDef::State

PKA state

Definition at line 105 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_Abort(), HAL_PKA_DeInit(), HAL_PKA_GetState(), HAL_PKA_Init(), HAL_PKA_IRQHandler(), HAL_PKA_RegisterCallback(), HAL_PKA_UnRegisterCallback(), PKA_Process(), and PKA_Process_IT().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_pka.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PKA Callback pointer definition

Typedefs
PKA Callback pointer definition
PKA Exported Types

PKA Callback pointer definition. More...

Typedefs

typedef void(* pPKA_CallbackTypeDef )(PKA_HandleTypeDef *hpka)

Detailed Description

PKA Callback pointer definition.

Typedef Documentation

typedef void(* pPKA_CallbackTypeDef)(PKA_HandleTypeDef *hpka)

Pointer to a PKA callback function

Definition at line 123 of file stm32wbxx_hal_pka.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PKA operation structure definition

Data Structures | Typedefs
PKA operation structure definition
PKA Exported Types

Input and output data definition. More...

Data Structures

struct | PKA_ECCMulFastModeInTypeDef
struct | PKA_ECCMulInTypeDef
struct | PKA_PointCheckInTypeDef
struct | PKA_RSACRTExpInTypeDef
struct | PKA_ECDSAVerifInTypeDef
struct | PKA_ECDSASignInTypeDef
struct | PKA_ECDSASignOutTypeDef
struct | PKA_ECDSASignOutExtParamTypeDef
struct | PKA_ModExpInTypeDef
struct | PKA_ModExpFastModeInTypeDef
struct | PKA_MontgomeryParamInTypeDef
struct | PKA_AddInTypeDef
struct | PKA_ModInvInTypeDef
struct | PKA_ModRedInTypeDef
struct | PKA_ModAddInTypeDef

Typedefs

typedef struct
PKA_ECDSASignOutExtParamTypeDef 		PKA_ECCMulOutTypeDef
typedef struct PKA_AddInTypeDef | PKA_SubInTypeDef
typedef struct PKA_AddInTypeDef | PKA_MulInTypeDef
typedef struct PKA_AddInTypeDef | PKA_CmpInTypeDef
typedef struct PKA_ModAddInTypeDef | PKA_ModSubInTypeDef
typedef struct PKA_ModAddInTypeDef | PKA_MontgomeryMulInTypeDef

Detailed Description

Input and output data definition.

Typedef Documentation

typedef struct PKA_AddInTypeDef PKA_CmpInTypeDef
typedef struct PKA_ECDSASignOutExtParamTypeDef PKA_ECCMulOutTypeDef
typedef struct PKA_ModAddInTypeDef PKA_ModSubInTypeDef
typedef struct PKA_ModAddInTypeDef PKA_MontgomeryMulInTypeDef
typedef struct PKA_AddInTypeDef PKA_MulInTypeDef
typedef struct PKA_AddInTypeDef PKA_SubInTypeDef
Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PKA_ECCMulFastModeInTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PKA_ECCMulFastModeInTypeDef Struct Reference
PKA operation structure definition

#include <stm32wbxx_hal_pka.h>

Data Fields

uint32_t | scalarMulSize
uint32_t | modulusSize
uint32_t | coefSign
const uint8_t * | coefA
const uint8_t * | modulus
const uint8_t * | pointX
const uint8_t * | pointY
const uint8_t * | scalarMul
const uint32_t * | pMontgomeryParam

Detailed Description

Definition at line 132 of file stm32wbxx_hal_pka.h.

Field Documentation

const uint8_t* PKA_ECCMulFastModeInTypeDef::coefA

Pointer to curve coefficient |a| (Array of modulusSize elements)

Definition at line 137 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECCMulFastMode_Set().

uint32_t PKA_ECCMulFastModeInTypeDef::coefSign

Curve coefficient a sign

Definition at line 136 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECCMulFastMode_Set().

const uint8_t* PKA_ECCMulFastModeInTypeDef::modulus

Pointer to curve modulus value p (Array of modulusSize elements)

Definition at line 138 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECCMulFastMode_Set().

uint32_t PKA_ECCMulFastModeInTypeDef::modulusSize

Number of element in modulus, coefA, pointX and pointY arrays

Definition at line 135 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECCMulFastMode_Set().

const uint32_t* PKA_ECCMulFastModeInTypeDef::pMontgomeryParam

Pointer to Montgomery parameter (Array of modulusSize/4 elements)

Definition at line 142 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECCMulFastMode_Set().

const uint8_t* PKA_ECCMulFastModeInTypeDef::pointX

Pointer to point P coordinate xP (Array of modulusSize elements)

Definition at line 139 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECCMulFastMode_Set().

const uint8_t* PKA_ECCMulFastModeInTypeDef::pointY

Pointer to point P coordinate yP (Array of modulusSize elements)

Definition at line 140 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECCMulFastMode_Set().

const uint8_t* PKA_ECCMulFastModeInTypeDef::scalarMul

Pointer to scalar multiplier k (Array of scalarMulSize elements)

Definition at line 141 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECCMulFastMode_Set().

uint32_t PKA_ECCMulFastModeInTypeDef::scalarMulSize

Number of element in scalarMul array

Definition at line 134 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECCMulFastMode_Set().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_pka.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PKA_ECCMulInTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PKA_ECCMulInTypeDef Struct Reference
PKA operation structure definition

#include <stm32wbxx_hal_pka.h>

Data Fields

uint32_t | scalarMulSize
uint32_t | modulusSize
uint32_t | coefSign
const uint8_t * | coefA
const uint8_t * | modulus
const uint8_t * | pointX
const uint8_t * | pointY
const uint8_t * | scalarMul

Detailed Description

Definition at line 145 of file stm32wbxx_hal_pka.h.

Field Documentation

const uint8_t* PKA_ECCMulInTypeDef::coefA

Pointer to curve coefficient |a| (Array of modulusSize elements)

Definition at line 150 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECCMul_Set().

uint32_t PKA_ECCMulInTypeDef::coefSign

Curve coefficient a sign

Definition at line 149 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECCMul_Set().

const uint8_t* PKA_ECCMulInTypeDef::modulus

Pointer to curve modulus value p (Array of modulusSize elements)

Definition at line 151 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECCMul_Set().

uint32_t PKA_ECCMulInTypeDef::modulusSize

Number of element in modulus, coefA, pointX and pointY arrays

Definition at line 148 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECCMul_Set().

const uint8_t* PKA_ECCMulInTypeDef::pointX

Pointer to point P coordinate xP (Array of modulusSize elements)

Definition at line 152 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECCMul_Set().

const uint8_t* PKA_ECCMulInTypeDef::pointY

Pointer to point P coordinate yP (Array of modulusSize elements)

Definition at line 153 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECCMul_Set().

const uint8_t* PKA_ECCMulInTypeDef::scalarMul

Pointer to scalar multiplier k (Array of scalarMulSize elements)

Definition at line 154 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECCMul_Set().

uint32_t PKA_ECCMulInTypeDef::scalarMulSize

Number of element in scalarMul array

Definition at line 147 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECCMul_Set().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_pka.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PKA_PointCheckInTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PKA_PointCheckInTypeDef Struct Reference
PKA operation structure definition

#include <stm32wbxx_hal_pka.h>

Data Fields

uint32_t | modulusSize
uint32_t | coefSign
const uint8_t * | coefA
const uint8_t * | coefB
const uint8_t * | modulus
const uint8_t * | pointX
const uint8_t * | pointY

Detailed Description

Definition at line 157 of file stm32wbxx_hal_pka.h.

Field Documentation

const uint8_t* PKA_PointCheckInTypeDef::coefA

Pointer to curve coefficient |a| (Array of modulusSize elements)

Definition at line 161 of file stm32wbxx_hal_pka.h.

Referenced by PKA_PointCheck_Set().

const uint8_t* PKA_PointCheckInTypeDef::coefB

Pointer to curve coefficient b (Array of modulusSize elements)

Definition at line 162 of file stm32wbxx_hal_pka.h.

Referenced by PKA_PointCheck_Set().

uint32_t PKA_PointCheckInTypeDef::coefSign

Curve coefficient a sign

Definition at line 160 of file stm32wbxx_hal_pka.h.

Referenced by PKA_PointCheck_Set().

const uint8_t* PKA_PointCheckInTypeDef::modulus

Pointer to curve modulus value p (Array of modulusSize elements)

Definition at line 163 of file stm32wbxx_hal_pka.h.

Referenced by PKA_PointCheck_Set().

uint32_t PKA_PointCheckInTypeDef::modulusSize

Number of element in coefA, coefB, modulus, pointX and pointY arrays

Definition at line 159 of file stm32wbxx_hal_pka.h.

Referenced by PKA_PointCheck_Set().

const uint8_t* PKA_PointCheckInTypeDef::pointX

Pointer to point P coordinate xP (Array of modulusSize elements)

Definition at line 164 of file stm32wbxx_hal_pka.h.

Referenced by PKA_PointCheck_Set().

const uint8_t* PKA_PointCheckInTypeDef::pointY

Pointer to point P coordinate yP (Array of modulusSize elements)

Definition at line 165 of file stm32wbxx_hal_pka.h.

Referenced by PKA_PointCheck_Set().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_pka.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PKA_RSACRTExpInTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PKA_RSACRTExpInTypeDef Struct Reference
PKA operation structure definition

#include <stm32wbxx_hal_pka.h>

Data Fields

uint32_t | size
const uint8_t * | pOpDp
const uint8_t * | pOpDq
const uint8_t * | pOpQinv
const uint8_t * | pPrimeP
const uint8_t * | pPrimeQ
const uint8_t * | popA

Detailed Description

Definition at line 168 of file stm32wbxx_hal_pka.h.

Field Documentation

const uint8_t* PKA_RSACRTExpInTypeDef::popA

Pointer to operand A (Array of size elements)

Definition at line 176 of file stm32wbxx_hal_pka.h.

Referenced by PKA_RSACRTExp_Set().

const uint8_t* PKA_RSACRTExpInTypeDef::pOpDp

Pointer to operand dP (Array of size/2 elements)

Definition at line 171 of file stm32wbxx_hal_pka.h.

Referenced by PKA_RSACRTExp_Set().

const uint8_t* PKA_RSACRTExpInTypeDef::pOpDq

Pointer to operand dQ (Array of size/2 elements)

Definition at line 172 of file stm32wbxx_hal_pka.h.

Referenced by PKA_RSACRTExp_Set().

const uint8_t* PKA_RSACRTExpInTypeDef::pOpQinv

Pointer to operand qinv (Array of size/2 elements)

Definition at line 173 of file stm32wbxx_hal_pka.h.

Referenced by PKA_RSACRTExp_Set().

const uint8_t* PKA_RSACRTExpInTypeDef::pPrimeP

Pointer to prime p (Array of size/2 elements)

Definition at line 174 of file stm32wbxx_hal_pka.h.

Referenced by PKA_RSACRTExp_Set().

const uint8_t* PKA_RSACRTExpInTypeDef::pPrimeQ

Pointer to prime Q (Array of size/2 elements)

Definition at line 175 of file stm32wbxx_hal_pka.h.

Referenced by PKA_RSACRTExp_Set().

uint32_t PKA_RSACRTExpInTypeDef::size

Number of element in popA array

Definition at line 170 of file stm32wbxx_hal_pka.h.

Referenced by PKA_RSACRTExp_Set().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_pka.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PKA_ECDSAVerifInTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PKA_ECDSAVerifInTypeDef Struct Reference
PKA operation structure definition

#include <stm32wbxx_hal_pka.h>

Data Fields

uint32_t | primeOrderSize
uint32_t | modulusSize
uint32_t | coefSign
const uint8_t * | coef
const uint8_t * | modulus
const uint8_t * | basePointX
const uint8_t * | basePointY
const uint8_t * | pPubKeyCurvePtX
const uint8_t * | pPubKeyCurvePtY
const uint8_t * | RSign
const uint8_t * | SSign
const uint8_t * | hash
const uint8_t * | primeOrder

Detailed Description

Definition at line 179 of file stm32wbxx_hal_pka.h.

Field Documentation

const uint8_t* PKA_ECDSAVerifInTypeDef::basePointX

Pointer to curve base point xG (Array of modulusSize elements)

Definition at line 186 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECDSAVerif_Set().

const uint8_t* PKA_ECDSAVerifInTypeDef::basePointY

Pointer to curve base point yG (Array of modulusSize elements)

Definition at line 187 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECDSAVerif_Set().

const uint8_t* PKA_ECDSAVerifInTypeDef::coef

Pointer to curve coefficient |a| (Array of modulusSize elements)

Definition at line 184 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECDSAVerif_Set().

uint32_t PKA_ECDSAVerifInTypeDef::coefSign

Curve coefficient a sign

Definition at line 183 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECDSAVerif_Set().

const uint8_t* PKA_ECDSAVerifInTypeDef::hash

Pointer to hash of the message e (Array of primeOrderSize elements)

Definition at line 192 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECDSAVerif_Set().

const uint8_t* PKA_ECDSAVerifInTypeDef::modulus

Pointer to curve modulus value p (Array of modulusSize elements)

Definition at line 185 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECDSAVerif_Set().

uint32_t PKA_ECDSAVerifInTypeDef::modulusSize

Number of element in modulus array

Definition at line 182 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECDSAVerif_Set().

const uint8_t* PKA_ECDSAVerifInTypeDef::pPubKeyCurvePtX

Pointer to public-key curve point xQ (Array of modulusSize elements)

Definition at line 188 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECDSAVerif_Set().

const uint8_t* PKA_ECDSAVerifInTypeDef::pPubKeyCurvePtY

Pointer to public-key curve point yQ (Array of modulusSize elements)

Definition at line 189 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECDSAVerif_Set().

const uint8_t* PKA_ECDSAVerifInTypeDef::primeOrder

Pointer to order of the curve n (Array of primeOrderSize elements)

Definition at line 193 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECDSAVerif_Set().

uint32_t PKA_ECDSAVerifInTypeDef::primeOrderSize

Number of element in primeOrder array

Definition at line 181 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECDSAVerif_Set().

const uint8_t* PKA_ECDSAVerifInTypeDef::RSign

Pointer to signature part r (Array of primeOrderSize elements)

Definition at line 190 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECDSAVerif_Set().

const uint8_t* PKA_ECDSAVerifInTypeDef::SSign

Pointer to signature part s (Array of primeOrderSize elements)

Definition at line 191 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECDSAVerif_Set().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_pka.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PKA_ECDSASignInTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PKA_ECDSASignInTypeDef Struct Reference
PKA operation structure definition

#include <stm32wbxx_hal_pka.h>

Data Fields

uint32_t | primeOrderSize
uint32_t | modulusSize
uint32_t | coefSign
const uint8_t * | coef
const uint8_t * | modulus
const uint8_t * | integer
const uint8_t * | basePointX
const uint8_t * | basePointY
const uint8_t * | hash
const uint8_t * | privateKey
const uint8_t * | primeOrder

Detailed Description

Definition at line 196 of file stm32wbxx_hal_pka.h.

Field Documentation

const uint8_t* PKA_ECDSASignInTypeDef::basePointX

Pointer to curve base point xG (Array of modulusSize elements)

Definition at line 204 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECDSASign_Set().

const uint8_t* PKA_ECDSASignInTypeDef::basePointY

Pointer to curve base point yG (Array of modulusSize elements)

Definition at line 205 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECDSASign_Set().

const uint8_t* PKA_ECDSASignInTypeDef::coef

Pointer to curve coefficient |a| (Array of modulusSize elements)

Definition at line 201 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECDSASign_Set().

uint32_t PKA_ECDSASignInTypeDef::coefSign

Curve coefficient a sign

Definition at line 200 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECDSASign_Set().

const uint8_t* PKA_ECDSASignInTypeDef::hash

Pointer to hash of the message (Array of primeOrderSize elements)

Definition at line 206 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECDSASign_Set().

const uint8_t* PKA_ECDSASignInTypeDef::integer

Pointer to random integer k (Array of primeOrderSize elements)

Definition at line 203 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECDSASign_Set().

const uint8_t* PKA_ECDSASignInTypeDef::modulus

Pointer to curve modulus value p (Array of modulusSize elements)

Definition at line 202 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECDSASign_Set().

uint32_t PKA_ECDSASignInTypeDef::modulusSize

Number of element in modulus array

Definition at line 199 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECDSASign_Set().

const uint8_t* PKA_ECDSASignInTypeDef::primeOrder

Pointer to order of the curve n (Array of primeOrderSize elements)

Definition at line 208 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECDSASign_Set().

uint32_t PKA_ECDSASignInTypeDef::primeOrderSize

Number of element in primeOrder array

Definition at line 198 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECDSASign_Set().

const uint8_t* PKA_ECDSASignInTypeDef::privateKey

Pointer to private key d (Array of primeOrderSize elements)

Definition at line 207 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ECDSASign_Set().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_pka.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PKA_ECDSASignOutTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PKA_ECDSASignOutTypeDef Struct Reference
PKA operation structure definition

#include <stm32wbxx_hal_pka.h>

Data Fields

uint8_t * | RSign
uint8_t * | SSign

Detailed Description

Definition at line 211 of file stm32wbxx_hal_pka.h.

Field Documentation

uint8_t* PKA_ECDSASignOutTypeDef::RSign

Pointer to signature part r (Array of modulusSize elements)

Definition at line 213 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_ECDSASign_GetResult().

uint8_t* PKA_ECDSASignOutTypeDef::SSign

Pointer to signature part s (Array of modulusSize elements)

Definition at line 214 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_ECDSASign_GetResult().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_pka.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PKA_ECDSASignOutExtParamTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PKA_ECDSASignOutExtParamTypeDef Struct Reference
PKA operation structure definition

#include <stm32wbxx_hal_pka.h>

Data Fields

uint8_t * | ptX
uint8_t * | ptY

Detailed Description

Definition at line 217 of file stm32wbxx_hal_pka.h.

Field Documentation

uint8_t* PKA_ECDSASignOutExtParamTypeDef::ptX

Pointer to point P coordinate xP (Array of modulusSize elements)

Definition at line 219 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_ECCMul_GetResult(), and HAL_PKA_ECDSASign_GetResult().

uint8_t* PKA_ECDSASignOutExtParamTypeDef::ptY

Pointer to point P coordinate yP (Array of modulusSize elements)

Definition at line 220 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_ECCMul_GetResult(), and HAL_PKA_ECDSASign_GetResult().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_pka.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PKA_ModExpInTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PKA_ModExpInTypeDef Struct Reference
PKA operation structure definition

#include <stm32wbxx_hal_pka.h>

Data Fields

uint32_t | expSize
uint32_t | OpSize
const uint8_t * | pExp
const uint8_t * | pOp1
const uint8_t * | pMod

Detailed Description

Definition at line 223 of file stm32wbxx_hal_pka.h.

Field Documentation

uint32_t PKA_ModExpInTypeDef::expSize

Number of element in pExp array

Definition at line 225 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ModExp_Set().

uint32_t PKA_ModExpInTypeDef::OpSize

Number of element in pOp1 and pMod arrays

Definition at line 226 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ModExp_Set().

const uint8_t* PKA_ModExpInTypeDef::pExp

Pointer to Exponent (Array of expSize elements)

Definition at line 227 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ModExp_Set().

const uint8_t* PKA_ModExpInTypeDef::pMod

Pointer to modulus (Array of OpSize elements)

Definition at line 229 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ModExp_Set().

const uint8_t* PKA_ModExpInTypeDef::pOp1

Pointer to Operand (Array of OpSize elements)

Definition at line 228 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ModExp_Set().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_pka.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PKA_ModExpFastModeInTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PKA_ModExpFastModeInTypeDef Struct Reference
PKA operation structure definition

#include <stm32wbxx_hal_pka.h>

Data Fields

uint32_t | expSize
uint32_t | OpSize
const uint8_t * | pExp
const uint8_t * | pOp1
const uint8_t * | pMod
const uint32_t * | pMontgomeryParam

Detailed Description

Definition at line 232 of file stm32wbxx_hal_pka.h.

Field Documentation

uint32_t PKA_ModExpFastModeInTypeDef::expSize

Number of element in pExp and pMontgomeryParam arrays

Definition at line 234 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ModExpFastMode_Set().

uint32_t PKA_ModExpFastModeInTypeDef::OpSize

Number of element in pOp1 and pMod arrays

Definition at line 235 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ModExpFastMode_Set().

const uint8_t* PKA_ModExpFastModeInTypeDef::pExp

Pointer to Exponent (Array of expSize elements)

Definition at line 236 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ModExpFastMode_Set().

const uint8_t* PKA_ModExpFastModeInTypeDef::pMod

Pointer to modulus (Array of OpSize elements)

Definition at line 238 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ModExpFastMode_Set().

const uint32_t* PKA_ModExpFastModeInTypeDef::pMontgomeryParam

Pointer to Montgomery parameter (Array of expSize/4 elements)

Definition at line 239 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ModExpFastMode_Set().

const uint8_t* PKA_ModExpFastModeInTypeDef::pOp1

Pointer to Operand (Array of OpSize elements)

Definition at line 237 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ModExpFastMode_Set().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_pka.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PKA_MontgomeryParamInTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PKA_MontgomeryParamInTypeDef Struct Reference
PKA operation structure definition

#include <stm32wbxx_hal_pka.h>

Data Fields

uint32_t | size
const uint8_t * | pOp1

Detailed Description

Definition at line 242 of file stm32wbxx_hal_pka.h.

Field Documentation

const uint8_t* PKA_MontgomeryParamInTypeDef::pOp1

Pointer to Operand (Array of size elements)

Definition at line 245 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_MontgomeryParam(), and HAL_PKA_MontgomeryParam_IT().

uint32_t PKA_MontgomeryParamInTypeDef::size

Number of element in pOp1 array

Definition at line 244 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_MontgomeryParam(), and HAL_PKA_MontgomeryParam_IT().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_pka.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PKA_AddInTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PKA_AddInTypeDef Struct Reference
PKA operation structure definition

#include <stm32wbxx_hal_pka.h>

Data Fields

uint32_t | size
const uint32_t * | pOp1
const uint32_t * | pOp2

Detailed Description

Definition at line 248 of file stm32wbxx_hal_pka.h.

Field Documentation

const uint32_t* PKA_AddInTypeDef::pOp1

Pointer to Operand 1 (Array of size elements)

Definition at line 251 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_Add(), HAL_PKA_Add_IT(), HAL_PKA_Cmp(), HAL_PKA_Cmp_IT(), HAL_PKA_Mul(), HAL_PKA_Mul_IT(), HAL_PKA_Sub(), and HAL_PKA_Sub_IT().

const uint32_t* PKA_AddInTypeDef::pOp2

Pointer to Operand 2 (Array of size elements)

Definition at line 252 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_Add(), HAL_PKA_Add_IT(), HAL_PKA_Cmp(), HAL_PKA_Cmp_IT(), HAL_PKA_Mul(), HAL_PKA_Mul_IT(), HAL_PKA_Sub(), and HAL_PKA_Sub_IT().

uint32_t PKA_AddInTypeDef::size

Number of element in pOp1 and pOp2 arrays

Definition at line 250 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_Add(), HAL_PKA_Add_IT(), HAL_PKA_Cmp(), HAL_PKA_Cmp_IT(), HAL_PKA_Mul(), HAL_PKA_Mul_IT(), HAL_PKA_Sub(), and HAL_PKA_Sub_IT().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_pka.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PKA_ModInvInTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PKA_ModInvInTypeDef Struct Reference
PKA operation structure definition

#include <stm32wbxx_hal_pka.h>

Data Fields

uint32_t | size
const uint32_t * | pOp1
const uint8_t * | pMod

Detailed Description

Definition at line 255 of file stm32wbxx_hal_pka.h.

Field Documentation

const uint8_t* PKA_ModInvInTypeDef::pMod

Pointer to modulus value n (Array of size*4 elements)

Definition at line 259 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ModInv_Set().

const uint32_t* PKA_ModInvInTypeDef::pOp1

Pointer to Operand 1 (Array of size elements)

Definition at line 258 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ModInv_Set().

uint32_t PKA_ModInvInTypeDef::size

Number of element in pOp1 array

Definition at line 257 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ModInv_Set().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_pka.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PKA_ModRedInTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PKA_ModRedInTypeDef Struct Reference
PKA operation structure definition

#include <stm32wbxx_hal_pka.h>

Data Fields

uint32_t | OpSize
uint32_t | modSize
const uint32_t * | pOp1
const uint8_t * | pMod

Detailed Description

Definition at line 262 of file stm32wbxx_hal_pka.h.

Field Documentation

uint32_t PKA_ModRedInTypeDef::modSize

Number of element in pMod array

Definition at line 265 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ModRed_Set().

uint32_t PKA_ModRedInTypeDef::OpSize

Number of element in pOp1 array

Definition at line 264 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ModRed_Set().

const uint8_t* PKA_ModRedInTypeDef::pMod

Pointer to modulus value n (Array of modSize elements)

Definition at line 267 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ModRed_Set().

const uint32_t* PKA_ModRedInTypeDef::pOp1

Pointer to Operand 1 (Array of OpSize elements)

Definition at line 266 of file stm32wbxx_hal_pka.h.

Referenced by PKA_ModRed_Set().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_pka.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PKA_ModAddInTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PKA_ModAddInTypeDef Struct Reference
PKA operation structure definition

#include <stm32wbxx_hal_pka.h>

Data Fields

uint32_t | size
const uint32_t * | pOp1
const uint32_t * | pOp2
const uint8_t * | pOp3

Detailed Description

Definition at line 270 of file stm32wbxx_hal_pka.h.

Field Documentation

const uint32_t* PKA_ModAddInTypeDef::pOp1

Pointer to Operand 1 (Array of size elements)

Definition at line 273 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_ModAdd(), HAL_PKA_ModAdd_IT(), HAL_PKA_ModSub(), HAL_PKA_ModSub_IT(), HAL_PKA_MontgomeryMul(), and HAL_PKA_MontgomeryMul_IT().

const uint32_t* PKA_ModAddInTypeDef::pOp2

Pointer to Operand 2 (Array of size elements)

Definition at line 274 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_ModAdd(), HAL_PKA_ModAdd_IT(), HAL_PKA_ModSub(), HAL_PKA_ModSub_IT(), HAL_PKA_MontgomeryMul(), and HAL_PKA_MontgomeryMul_IT().

const uint8_t* PKA_ModAddInTypeDef::pOp3

Pointer to Operand 3 (Array of size*4 elements)

Definition at line 275 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_ModAdd(), HAL_PKA_ModAdd_IT(), HAL_PKA_ModSub(), HAL_PKA_ModSub_IT(), HAL_PKA_MontgomeryMul(), and HAL_PKA_MontgomeryMul_IT().

uint32_t PKA_ModAddInTypeDef::size

Number of element in pOp1 and pOp2 arrays

Definition at line 272 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_ModAdd(), HAL_PKA_ModAdd_IT(), HAL_PKA_ModSub(), HAL_PKA_ModSub_IT(), HAL_PKA_MontgomeryMul(), and HAL_PKA_MontgomeryMul_IT().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_pka.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PKA mode

Defines
PKA mode
PKA Exported Constants

Defines

#define | PKA_MODE_MONTGOMERY_PARAM (0x00000001U)
#define | PKA_MODE_MODULAR_EXP (0x00000000U)
#define | PKA_MODE_MODULAR_EXP_FAST_MODE (0x00000002U)
#define | PKA_MODE_ECC_MUL (0x00000020U)
#define | PKA_MODE_ECC_MUL_FAST_MODE (0x00000022U)
#define | PKA_MODE_ECDSA_SIGNATURE (0x00000024U)
#define | PKA_MODE_ECDSA_VERIFICATION (0x00000026U)
#define | PKA_MODE_POINT_CHECK (0x00000028U)
#define | PKA_MODE_RSA_CRT_EXP (0x00000007U)
#define | PKA_MODE_MODULAR_INV (0x00000008U)
#define | PKA_MODE_ARITHMETIC_ADD (0x00000009U)
#define | PKA_MODE_ARITHMETIC_SUB (0x0000000AU)
#define | PKA_MODE_ARITHMETIC_MUL (0x0000000BU)
#define | PKA_MODE_COMPARISON (0x0000000CU)
#define | PKA_MODE_MODULAR_RED (0x0000000DU)
#define | PKA_MODE_MODULAR_ADD (0x0000000EU)
#define | PKA_MODE_MODULAR_SUB (0x0000000FU)
#define | PKA_MODE_MONTGOMERY_MUL (0x00000010U)

Define Documentation

#define PKA_MODE_ARITHMETIC_ADD (0x00000009U)

Definition at line 304 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_Add(), HAL_PKA_Add_IT(), and HAL_PKA_Arithmetic_GetResult().

#define PKA_MODE_ARITHMETIC_MUL (0x0000000BU)

Definition at line 306 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_Arithmetic_GetResult(), HAL_PKA_Mul(), and HAL_PKA_Mul_IT().

#define PKA_MODE_ARITHMETIC_SUB (0x0000000AU)

Definition at line 305 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_Arithmetic_GetResult(), HAL_PKA_Sub(), and HAL_PKA_Sub_IT().

#define PKA_MODE_COMPARISON (0x0000000CU)

Definition at line 307 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_Arithmetic_GetResult(), HAL_PKA_Cmp(), and HAL_PKA_Cmp_IT().

#define PKA_MODE_ECC_MUL (0x00000020U)

Definition at line 297 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_ECCMul(), and HAL_PKA_ECCMul_IT().

#define PKA_MODE_ECC_MUL_FAST_MODE (0x00000022U)

Definition at line 298 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_ECCMulFastMode(), and HAL_PKA_ECCMulFastMode_IT().

#define PKA_MODE_ECDSA_SIGNATURE (0x00000024U)

Definition at line 299 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_ECDSASign(), HAL_PKA_ECDSASign_IT(), HAL_PKA_IRQHandler(), and PKA_CheckError().

#define PKA_MODE_ECDSA_VERIFICATION (0x00000026U)

Definition at line 300 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_ECDSAVerif(), and HAL_PKA_ECDSAVerif_IT().

#define PKA_MODE_MODULAR_ADD (0x0000000EU)

Definition at line 309 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_Arithmetic_GetResult(), HAL_PKA_ModAdd(), and HAL_PKA_ModAdd_IT().

#define PKA_MODE_MODULAR_EXP (0x00000000U)

Definition at line 295 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_ModExp(), and HAL_PKA_ModExp_IT().

#define PKA_MODE_MODULAR_EXP_FAST_MODE (0x00000002U)

Definition at line 296 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_ModExpFastMode(), and HAL_PKA_ModExpFastMode_IT().

#define PKA_MODE_MODULAR_INV (0x00000008U)

Definition at line 303 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_Arithmetic_GetResult(), HAL_PKA_ModInv(), and HAL_PKA_ModInv_IT().

#define PKA_MODE_MODULAR_RED (0x0000000DU)

Definition at line 308 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_Arithmetic_GetResult(), HAL_PKA_ModRed(), and HAL_PKA_ModRed_IT().

#define PKA_MODE_MODULAR_SUB (0x0000000FU)

Definition at line 310 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_Arithmetic_GetResult(), HAL_PKA_ModSub(), and HAL_PKA_ModSub_IT().

#define PKA_MODE_MONTGOMERY_MUL (0x00000010U)

Definition at line 311 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_Arithmetic_GetResult(), HAL_PKA_MontgomeryMul(), and HAL_PKA_MontgomeryMul_IT().

#define PKA_MODE_MONTGOMERY_PARAM (0x00000001U)

Definition at line 294 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_MontgomeryParam(), and HAL_PKA_MontgomeryParam_IT().

#define PKA_MODE_POINT_CHECK (0x00000028U)

Definition at line 301 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_PointCheck(), and HAL_PKA_PointCheck_IT().

#define PKA_MODE_RSA_CRT_EXP (0x00000007U)

Definition at line 302 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_RSACRTExp(), and HAL_PKA_RSACRTExp_IT().

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PKA Interrupt configuration definition

Defines
PKA Interrupt configuration definition
PKA Exported Constants

PKA Interrupt definition. More...

Defines

#define | PKA_IT_PROCEND PKA_CR_PROCENDIE
#define | PKA_IT_ADDRERR PKA_CR_ADDRERRIE
#define | PKA_IT_RAMERR PKA_CR_RAMERRIE

Detailed Description

PKA Interrupt definition.

Define Documentation

#define PKA_IT_ADDRERR PKA_CR_ADDRERRIE

Definition at line 321 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_IRQHandler().

#define PKA_IT_PROCEND PKA_CR_PROCENDIE

Definition at line 320 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_IRQHandler().

#define PKA_IT_RAMERR PKA_CR_RAMERRIE

Definition at line 322 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_IRQHandler().

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PKA Flag definition

Defines
PKA Flag definition
PKA Exported Constants

Defines

#define | PKA_FLAG_PROCEND PKA_SR_PROCENDF
#define | PKA_FLAG_ADDRERR PKA_SR_ADDRERRF
#define | PKA_FLAG_RAMERR PKA_SR_RAMERRF

Define Documentation

#define PKA_FLAG_ADDRERR PKA_SR_ADDRERRF

Definition at line 331 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_IRQHandler(), and PKA_CheckError().

#define PKA_FLAG_PROCEND PKA_SR_PROCENDF

Definition at line 330 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_IRQHandler().

#define PKA_FLAG_RAMERR PKA_SR_RAMERRF

Definition at line 332 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_IRQHandler(), and PKA_CheckError().

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PKA Exported Macros

Defines
PKA Exported Macros
PKA

Defines

#define | __HAL_PKA_RESET_HANDLE_STATE(__HANDLE__)
Reset PKA handle state.
#define | __HAL_PKA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the specified PKA interrupt.
#define | __HAL_PKA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= (~(__INTERRUPT__)))
Disable the specified PKA interrupt.
#define | __HAL_PKA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified PKA interrupt source is enabled or not.
#define | __HAL_PKA_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
Check whether the specified PKA flag is set or not.
#define | __HAL_PKA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
Clear the PKA pending flags which are cleared by writing 1 in a specific bit.
#define | __HAL_PKA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR, PKA_CR_EN))
Enable the specified PKA peripheral.
#define | __HAL_PKA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR, PKA_CR_EN))
Disable the specified PKA peripheral.
#define | __HAL_PKA_START(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR, PKA_CR_START))
Start a PKA operation.

Define Documentation

#define __HAL_PKA_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->CLRFR = (__FLAG__))

Clear the PKA pending flags which are cleared by writing 1 in a specific bit.

Parameters:
__HANDLE__ specifies the PKA Handle
__FLAG__ specifies the flag to clear. This parameter can be any combination of the following values:
  • PKA_FLAG_PROCEND End Of Operation
  • PKA_FLAG_ADDRERR Address error
  • PKA_FLAG_RAMERR RAM error
Return values:
None

Definition at line 414 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_IRQHandler().

#define __HAL_PKA_DISABLE ( __HANDLE__ ) (CLEAR_BIT((__HANDLE__)->Instance->CR, PKA_CR_EN))

Disable the specified PKA peripheral.

Parameters:
__HANDLE__ specifies the PKA Handle
Return values:
None

Definition at line 426 of file stm32wbxx_hal_pka.h.

#define __HAL_PKA_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR &= (~(__INTERRUPT__)))

Disable the specified PKA interrupt.

Parameters:
__HANDLE__ specifies the PKA Handle
__INTERRUPT__ specifies the interrupt source to disable. This parameter can be one of the following values:
  • PKA_IT_PROCEND End Of Operation interrupt enable
  • PKA_IT_ADDRERR Address error interrupt enable
  • PKA_IT_RAMERR RAM error interrupt enable
Return values:
None

Definition at line 381 of file stm32wbxx_hal_pka.h.

#define __HAL_PKA_ENABLE ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->CR, PKA_CR_EN))

Enable the specified PKA peripheral.

Parameters:
__HANDLE__ specifies the PKA Handle
Return values:
None

Definition at line 420 of file stm32wbxx_hal_pka.h.

#define __HAL_PKA_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))

Enable the specified PKA interrupt.

Parameters:
__HANDLE__ specifies the PKA Handle
__INTERRUPT__ specifies the interrupt source to enable. This parameter can be one of the following values:
  • PKA_IT_PROCEND End Of Operation interrupt enable
  • PKA_IT_ADDRERR Address error interrupt enable
  • PKA_IT_RAMERR RAM error interrupt enable
Return values:
None

Definition at line 370 of file stm32wbxx_hal_pka.h.

#define __HAL_PKA_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)

Check whether the specified PKA flag is set or not.

Parameters:
__HANDLE__ specifies the PKA Handle
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • PKA_FLAG_PROCEND End Of Operation
  • PKA_FLAG_ADDRERR Address error
  • PKA_FLAG_RAMERR RAM error
Return values:
The new state of __FLAG__ (SET or RESET)

Definition at line 403 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_IRQHandler(), and PKA_CheckError().

#define __HAL_PKA_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified PKA interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the PKA Handle
__INTERRUPT__ specifies the PKA interrupt source to check. This parameter can be one of the following values:
  • PKA_IT_PROCEND End Of Operation interrupt enable
  • PKA_IT_ADDRERR Address error interrupt enable
  • PKA_IT_RAMERR RAM error interrupt enable
Return values:
The new state of __INTERRUPT__ (SET or RESET)

Definition at line 392 of file stm32wbxx_hal_pka.h.

Referenced by HAL_PKA_IRQHandler().

#define __HAL_PKA_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                   \
                                                                    (__HANDLE__)->State = HAL_PKA_STATE_RESET;       \
                                                                    (__HANDLE__)->MspInitCallback = NULL;            \
                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \
                                                                  } while(0)

Reset PKA handle state.

Parameters:
__HANDLE__ specifies the PKA Handle
Return values:
None

Definition at line 352 of file stm32wbxx_hal_pka.h.

#define __HAL_PKA_START ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->CR, PKA_CR_START))

Start a PKA operation.

Parameters:
__HANDLE__ specifies the PKA Handle
Return values:
None

Definition at line 432 of file stm32wbxx_hal_pka.h.

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STM32WB55xx HAL User Manual: PWR_PVDTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PWR_PVDTypeDef Struct Reference
PWR Exported Types

PWR PVD configuration structure definition. More...

#include <stm32wbxx_hal_pwr.h>

Data Fields

uint32_t | PVDLevel
uint32_t | Mode

Detailed Description

PWR PVD configuration structure definition.

Definition at line 52 of file stm32wbxx_hal_pwr.h.

Field Documentation

uint32_t PWR_PVDTypeDef::Mode

Mode: Specifies the operating mode for the selected pins. This parameter can be a value of PWR PVD interrupt and event mode.

Definition at line 57 of file stm32wbxx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

uint32_t PWR_PVDTypeDef::PVDLevel

PVDLevel: Specifies the PVD detection level. This parameter can be a value of Power Voltage Detector Level selection.

Definition at line 54 of file stm32wbxx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_pwr.h
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STM32WB55xx HAL User Manual: Power Voltage Detector Level selection

Defines
Power Voltage Detector Level selection
PWR Exported Constants

Defines

#define | PWR_PVDLEVEL_0 (0x00000000U)
#define | PWR_PVDLEVEL_1 ( PWR_CR2_PLS_0)
#define | PWR_PVDLEVEL_2 ( PWR_CR2_PLS_1 )
#define | PWR_PVDLEVEL_3 ( PWR_CR2_PLS_1 | PWR_CR2_PLS_0)
#define | PWR_PVDLEVEL_4 (PWR_CR2_PLS_2 )
#define | PWR_PVDLEVEL_5 (PWR_CR2_PLS_2 | PWR_CR2_PLS_0)
#define | PWR_PVDLEVEL_6 (PWR_CR2_PLS_2 | PWR_CR2_PLS_1 )
#define | PWR_PVDLEVEL_7 (PWR_CR2_PLS_2 | PWR_CR2_PLS_1 | PWR_CR2_PLS_0)

Detailed Description

Note:
Refer datasheet for selection voltage value

Define Documentation

#define PWR_PVDLEVEL_0 (0x00000000U)

PVD threshold around 2.0 V

Definition at line 74 of file stm32wbxx_hal_pwr.h.

#define PWR_PVDLEVEL_1 ( PWR_CR2_PLS_0)

PVD threshold around 2.2 V

Definition at line 75 of file stm32wbxx_hal_pwr.h.

#define PWR_PVDLEVEL_2 ( PWR_CR2_PLS_1 )

PVD threshold around 2.4 V

Definition at line 76 of file stm32wbxx_hal_pwr.h.

#define PWR_PVDLEVEL_3 ( PWR_CR2_PLS_1 | PWR_CR2_PLS_0)

PVD threshold around 2.5 V

Definition at line 77 of file stm32wbxx_hal_pwr.h.

#define PWR_PVDLEVEL_4 (PWR_CR2_PLS_2 )

PVD threshold around 2.6 V

Definition at line 78 of file stm32wbxx_hal_pwr.h.

#define PWR_PVDLEVEL_5 (PWR_CR2_PLS_2 | PWR_CR2_PLS_0)

PVD threshold around 2.8 V

Definition at line 79 of file stm32wbxx_hal_pwr.h.

#define PWR_PVDLEVEL_6 (PWR_CR2_PLS_2 | PWR_CR2_PLS_1 )

PVD threshold around 2.9 V

Definition at line 80 of file stm32wbxx_hal_pwr.h.

#define PWR_PVDLEVEL_7 (PWR_CR2_PLS_2 | PWR_CR2_PLS_1 | PWR_CR2_PLS_0)

External input analog voltage (compared internally to VREFINT)

Definition at line 81 of file stm32wbxx_hal_pwr.h.

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STM32WB55xx HAL User Manual: PWR PVD interrupt and event mode

Defines
PWR PVD interrupt and event mode
PWR Exported Constants

Defines

#define | PWR_PVD_MODE_NORMAL (0x00000000U)
#define | PWR_PVD_MODE_IT_RISING (PVD_MODE_IT | PVD_RISING_EDGE)
#define | PWR_PVD_MODE_IT_FALLING (PVD_MODE_IT | PVD_FALLING_EDGE)
#define | PWR_PVD_MODE_IT_RISING_FALLING (PVD_MODE_IT | PVD_RISING_FALLING_EDGE)

Define Documentation

#define PWR_PVD_MODE_IT_FALLING (PVD_MODE_IT | PVD_FALLING_EDGE)

External Interrupt Mode with Falling edge trigger detection

Definition at line 94 of file stm32wbxx_hal_pwr.h.

#define PWR_PVD_MODE_IT_RISING (PVD_MODE_IT | PVD_RISING_EDGE)

External Interrupt Mode with Rising edge trigger detection

Definition at line 93 of file stm32wbxx_hal_pwr.h.

#define PWR_PVD_MODE_IT_RISING_FALLING (PVD_MODE_IT | PVD_RISING_FALLING_EDGE)

External Interrupt Mode with Rising/Falling edge trigger detection

Definition at line 95 of file stm32wbxx_hal_pwr.h.

#define PWR_PVD_MODE_NORMAL (0x00000000U)

Basic mode is used

Definition at line 91 of file stm32wbxx_hal_pwr.h.

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STM32WB55xx HAL User Manual: PWR Low Power Mode Selection

Defines
PWR Low Power Mode Selection
PWR Exported Constants

Defines

#define | PWR_LOWPOWERMODE_STOP0 (0x00000000u)
#define | PWR_LOWPOWERMODE_STOP1 (PWR_CR1_LPMS_0)
#define | PWR_LOWPOWERMODE_STOP2 (PWR_CR1_LPMS_1)
#define | PWR_LOWPOWERMODE_STANDBY (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1)
#define | PWR_LOWPOWERMODE_SHUTDOWN (PWR_CR1_LPMS_2)

Define Documentation

#define PWR_LOWPOWERMODE_SHUTDOWN (PWR_CR1_LPMS_2)

Shutdown mode

Definition at line 110 of file stm32wbxx_hal_pwr.h.

Referenced by HAL_PWREx_EnterSHUTDOWNMode().

#define PWR_LOWPOWERMODE_STANDBY (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1)

Standby mode

Definition at line 109 of file stm32wbxx_hal_pwr.h.

Referenced by HAL_PWR_EnterSTANDBYMode().

#define PWR_LOWPOWERMODE_STOP0 (0x00000000u)

Stop 0: stop mode with main regulator

Definition at line 106 of file stm32wbxx_hal_pwr.h.

Referenced by HAL_PWREx_EnterSTOP0Mode().

#define PWR_LOWPOWERMODE_STOP1 (PWR_CR1_LPMS_0)

Stop 1: stop mode with low power regulator

Definition at line 107 of file stm32wbxx_hal_pwr.h.

Referenced by HAL_PWREx_EnterSTOP1Mode().

#define PWR_LOWPOWERMODE_STOP2 (PWR_CR1_LPMS_1)

Stop 2: stop mode with low power regulator and VDD12I interruptible digital core domain supply OFF (less peripherals activated than low power mode stop 1 to reduce power consumption)

Definition at line 108 of file stm32wbxx_hal_pwr.h.

Referenced by HAL_PWREx_EnterSTOP2Mode().

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STM32WB55xx HAL User Manual: PWR regulator mode

Defines
PWR regulator mode
PWR Exported Constants

Defines

#define | PWR_MAINREGULATOR_ON (0x00000000U)
#define | PWR_LOWPOWERREGULATOR_ON (PWR_CR1_LPR)

Define Documentation

#define PWR_LOWPOWERREGULATOR_ON (PWR_CR1_LPR)

Regulator in low-power mode

Definition at line 119 of file stm32wbxx_hal_pwr.h.

Referenced by HAL_PWR_EnterSTOPMode().

#define PWR_MAINREGULATOR_ON (0x00000000U)

Regulator in main mode

Definition at line 118 of file stm32wbxx_hal_pwr.h.

Referenced by HAL_PWR_EnterSLEEPMode().

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STM32WB55xx HAL User Manual: PWR SLEEP mode entry

Defines
PWR SLEEP mode entry
PWR Exported Constants

Defines

#define | PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
#define | PWR_SLEEPENTRY_WFE ((uint8_t)0x02)

Define Documentation

#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)

Wait For Event instruction to enter Sleep mode

Definition at line 128 of file stm32wbxx_hal_pwr.h.

#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)

Wait For Interruption instruction to enter Sleep mode

Definition at line 127 of file stm32wbxx_hal_pwr.h.

Referenced by HAL_PWR_EnterSLEEPMode().

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STM32WB55xx HAL User Manual: PWR STOP mode entry

Defines
PWR STOP mode entry
PWR Exported Constants

Defines

#define | PWR_STOPENTRY_WFI ((uint8_t)0x01)
#define | PWR_STOPENTRY_WFE ((uint8_t)0x02)

Define Documentation

#define PWR_STOPENTRY_WFE ((uint8_t)0x02)

Wait For Event instruction to enter Stop mode

Definition at line 137 of file stm32wbxx_hal_pwr.h.

#define PWR_STOPENTRY_WFI ((uint8_t)0x01)

Wait For Interruption instruction to enter Stop mode

Definition at line 136 of file stm32wbxx_hal_pwr.h.

Referenced by HAL_PWREx_EnterSTOP0Mode(), HAL_PWREx_EnterSTOP1Mode(), and HAL_PWREx_EnterSTOP2Mode().

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STM32WB55xx HAL User Manual: PWR Register Reset Values

Defines
PWR Register Reset Values
PWR Private Defines

Defines

#define | PWR_CR1_RESET_VALUE (0x00000200U)
#define | PWR_CR2_RESET_VALUE (0x00000000U)
#define | PWR_CR3_RESET_VALUE (0x00008000U)
#define | PWR_CR4_RESET_VALUE (0x00000000U)
#define | PWR_CR5_RESET_VALUE (0x00004204U)
#define | PWR_PUCRA_RESET_VALUE (0x00000000U)
#define | PWR_PDCRA_RESET_VALUE (0x00000000U)
#define | PWR_PUCRB_RESET_VALUE (0x00000000U)
#define | PWR_PDCRB_RESET_VALUE (0x00000000U)
#define | PWR_PUCRC_RESET_VALUE (0x00000000U)
#define | PWR_PDCRC_RESET_VALUE (0x00000000U)
#define | PWR_PUCRD_RESET_VALUE (0x00000000U)
#define | PWR_PDCRD_RESET_VALUE (0x00000000U)
#define | PWR_PUCRE_RESET_VALUE (0x00000000U)
#define | PWR_PDCRE_RESET_VALUE (0x00000000U)
#define | PWR_PUCRH_RESET_VALUE (0x00000000U)
#define | PWR_PDCRH_RESET_VALUE (0x00000000U)
#define | PWR_C2CR1_RESET_VALUE (0x00000000U)
#define | PWR_C2CR3_RESET_VALUE (0x00008000U)

Define Documentation

#define PWR_C2CR1_RESET_VALUE (0x00000000U)

Definition at line 68 of file stm32wbxx_hal_pwr.c.

Referenced by HAL_PWR_DeInit().

#define PWR_C2CR3_RESET_VALUE (0x00008000U)

Definition at line 69 of file stm32wbxx_hal_pwr.c.

Referenced by HAL_PWR_DeInit().

#define PWR_CR1_RESET_VALUE (0x00000200U)

Definition at line 51 of file stm32wbxx_hal_pwr.c.

Referenced by HAL_PWR_DeInit().

#define PWR_CR2_RESET_VALUE (0x00000000U)

Definition at line 52 of file stm32wbxx_hal_pwr.c.

Referenced by HAL_PWR_DeInit().

#define PWR_CR3_RESET_VALUE (0x00008000U)

Definition at line 53 of file stm32wbxx_hal_pwr.c.

Referenced by HAL_PWR_DeInit().

#define PWR_CR4_RESET_VALUE (0x00000000U)

Definition at line 54 of file stm32wbxx_hal_pwr.c.

Referenced by HAL_PWR_DeInit().

#define PWR_CR5_RESET_VALUE (0x00004204U)

Definition at line 55 of file stm32wbxx_hal_pwr.c.

Referenced by HAL_PWR_DeInit().

#define PWR_PDCRA_RESET_VALUE (0x00000000U)

Definition at line 57 of file stm32wbxx_hal_pwr.c.

Referenced by HAL_PWR_DeInit().

#define PWR_PDCRB_RESET_VALUE (0x00000000U)

Definition at line 59 of file stm32wbxx_hal_pwr.c.

Referenced by HAL_PWR_DeInit().

#define PWR_PDCRC_RESET_VALUE (0x00000000U)

Definition at line 61 of file stm32wbxx_hal_pwr.c.

Referenced by HAL_PWR_DeInit().

#define PWR_PDCRD_RESET_VALUE (0x00000000U)

Definition at line 63 of file stm32wbxx_hal_pwr.c.

Referenced by HAL_PWR_DeInit().

#define PWR_PDCRE_RESET_VALUE (0x00000000U)

Definition at line 65 of file stm32wbxx_hal_pwr.c.

Referenced by HAL_PWR_DeInit().

#define PWR_PDCRH_RESET_VALUE (0x00000000U)

Definition at line 67 of file stm32wbxx_hal_pwr.c.

Referenced by HAL_PWR_DeInit().

#define PWR_PUCRA_RESET_VALUE (0x00000000U)

Definition at line 56 of file stm32wbxx_hal_pwr.c.

Referenced by HAL_PWR_DeInit().

#define PWR_PUCRB_RESET_VALUE (0x00000000U)

Definition at line 58 of file stm32wbxx_hal_pwr.c.

Referenced by HAL_PWR_DeInit().

#define PWR_PUCRC_RESET_VALUE (0x00000000U)

Definition at line 60 of file stm32wbxx_hal_pwr.c.

Referenced by HAL_PWR_DeInit().

#define PWR_PUCRD_RESET_VALUE (0x00000000U)

Definition at line 62 of file stm32wbxx_hal_pwr.c.

Referenced by HAL_PWR_DeInit().

#define PWR_PUCRE_RESET_VALUE (0x00000000U)

Definition at line 64 of file stm32wbxx_hal_pwr.c.

Referenced by HAL_PWR_DeInit().

#define PWR_PUCRH_RESET_VALUE (0x00000000U)

Definition at line 66 of file stm32wbxx_hal_pwr.c.

Referenced by HAL_PWR_DeInit().

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STM32WB55xx HAL User Manual: PWR PVD external interrupt line

Defines
PWR PVD external interrupt line
PWR Private Defines

Defines

#define PWR_EXTI_LINE_PVD (LL_EXTI_LINE_16)

Define Documentation

#define PWR_EXTI_LINE_PVD (LL_EXTI_LINE_16)

External interrupt line 16 Connected to the PWR PVD

Definition at line 154 of file stm32wbxx_hal_pwr.h.

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STM32WB55xx HAL User Manual: PWR PVD Mode Mask

Defines
PWR PVD Mode Mask
PWR Private Defines

Defines

#define | PVD_MODE_IT (0x00010000U)
#define | PVD_RISING_EDGE (0x00000001U)
#define | PVD_FALLING_EDGE (0x00000002U)
#define | PVD_RISING_FALLING_EDGE (0x00000003U)

Define Documentation

#define PVD_FALLING_EDGE (0x00000002U)

Mask for falling edge set as PVD trigger

Definition at line 166 of file stm32wbxx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define PVD_MODE_IT (0x00010000U)

Mask for interruption yielded by PVD threshold crossing

Definition at line 164 of file stm32wbxx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define PVD_RISING_EDGE (0x00000001U)

Mask for rising edge set as PVD trigger

Definition at line 165 of file stm32wbxx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define PVD_RISING_FALLING_EDGE (0x00000003U)

Mask for rising and falling edges set as PVD trigger

Definition at line 167 of file stm32wbxx_hal_pwr.h.

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STM32WB55xx HAL User Manual: PWR PVM external interrupts lines

Defines
PWR PVM external interrupts lines
PWR Private Defines

Defines

#define | PWR_EXTI_LINE_PVM1 (LL_EXTI_LINE_31)
#define | PWR_EXTI_LINE_PVM3 (LL_EXTI_LINE_33)

Define Documentation

#define PWR_EXTI_LINE_PVM1 (LL_EXTI_LINE_31)

External interrupt line 31 Connected to PVM1

Definition at line 418 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_EXTI_LINE_PVM3 (LL_EXTI_LINE_33)

External interrupt line 33 Connected to PVM3

Definition at line 420 of file stm32wbxx_hal_pwr_ex.h.

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STM32WB55xx HAL User Manual: PWR PVM Mode Mask

Defines
PWR PVM Mode Mask
PWR Private Defines

Defines

#define | PVM_MODE_IT (0x00010000U)
#define | PVM_MODE_EVT (0x00020000U)
#define | PVM_RISING_EDGE (0x00000001U)
#define | PVM_FALLING_EDGE (0x00000002U)
#define | PVM_RISING_FALLING_EDGE (0x00000003U)

Define Documentation

#define PVM_FALLING_EDGE (0x00000002U)

Mask for falling edge set as PVM trigger

Definition at line 433 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define PVM_MODE_EVT (0x00020000U)

Mask for event yielded by PVM threshold crossing

Definition at line 431 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define PVM_MODE_IT (0x00010000U)

Mask for interruption yielded by PVM threshold crossing

Definition at line 430 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define PVM_RISING_EDGE (0x00000001U)

Mask for rising edge set as PVM trigger

Definition at line 432 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define PVM_RISING_FALLING_EDGE (0x00000003U)

Mask for rising and falling edges set as PVM trigger

Definition at line 434 of file stm32wbxx_hal_pwr_ex.h.

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STM32WB55xx HAL User Manual: PWR Exported Macros

Defines
PWR Exported Macros
PWR

Defines

#define | __HAL_PWR_GET_FLAG(__FLAG__)
Check whether or not a specific PWR flag is set.
#define | __HAL_PWR_CLEAR_FLAG(__FLAG__)
Clear a specific PWR flag.
#define | __HAL_PWR_PVD_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(PWR_EXTI_LINE_PVD)
Enable the PVD Extended Interrupt C1 Line.
#define | __HAL_PWR_PVD_EXTIC2_ENABLE_IT() LL_C2_EXTI_EnableIT_0_31(PWR_EXTI_LINE_PVD)
Enable the PVD Extended Interrupt C2 Line.
#define | __HAL_PWR_PVD_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt C1 Line.
#define | __HAL_PWR_PVD_EXTIC2_DISABLE_IT() LL_C2_EXTI_DisableIT_0_31(PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt C2 Line.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(PWR_EXTI_LINE_PVD)
Enable the PVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableFallingTrig_0_31(PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(PWR_EXTI_LINE_PVD)
Enable the PVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableRisingTrig_0_31(PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the PVD Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the PVD Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(PWR_EXTI_LINE_PVD)
Generate a Software interrupt on selected EXTI line.
#define | __HAL_PWR_PVD_EXTI_GET_FLAG() LL_EXTI_ReadFlag_0_31(PWR_EXTI_LINE_PVD)
Check whether or not the PVD EXTI interrupt flag is set.
#define | __HAL_PWR_PVD_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(PWR_EXTI_LINE_PVD)
Clear the PVD EXTI interrupt flag.

Define Documentation

#define __HAL_PWR_CLEAR_FLAG ( __FLAG__ )
Value:
( ((((uint8_t)(__FLAG__)) >> 5U) == 1U) ?\
                                         ( (((uint8_t)(__FLAG__)) == PWR_FLAG_WU) ?\
                                         (PWR->SCR  = (__FLAG__)) : (PWR->SCR = (1U << ((__FLAG__) & 31U))) ) :\
                                         ( (((uint8_t)(__FLAG__)) == PWR_FLAG_CRITICAL_RF_PHASE) ?\
                                         SET_BIT (PWR->EXTSCR, PWR_EXTSCR_CCRPF) : ( ((((uint8_t)((__FLAG__)) & 31U) <= PWR_EXTSCR_C1STOPF_Pos) ?\
                                         SET_BIT (PWR->EXTSCR, PWR_EXTSCR_C1CSSF): SET_BIT (PWR->EXTSCR, PWR_EXTSCR_C2CSSF)) ) ))

Clear a specific PWR flag.

Note:
Clearing of flags {PWR_FLAG_STOP, PWR_FLAG_SB} and flags {PWR_FLAG_C2STOP, PWR_FLAG_C2SB} are grouped: clearing of one flag also clears the other one.
Parameters:
__FLAG__ specifies the flag to clear. This parameter can be one of the following values:

/--------------------------------SCR (SRR)------------------------------/

  • PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event was received from the WKUP pin 1.
  • PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event was received from the WKUP pin 2.
  • PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event was received from the WKUP pin 3.
  • PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event was received from the WKUP pin 4.
  • PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event was received from the WKUP pin 5.
  • PWR_FLAG_WU Encompasses all five Wake Up Flags.
  • PWR_FLAG_BHWF Clear BLE_Host Wakeup Flag.
  • PWR_FLAG_FRCBYPI Clear SMPS Forced in Bypass Interrupt Flag.
  • PWR_FLAG_RFPHASEI RF Phase Interrupt Clear.
  • PWR_FLAG_BLEACTI BLE Activity Interrupt Clear.
  • PWR_FLAG_802ACTI 802.15.4. Activity Interrupt Clear.
  • PWR_FLAG_HOLDC2I CPU2 on-Hold Interrupt Clear.

/----------------------------EXTSCR--------------------------/

  • PWR_FLAG_STOP System Stop Flag for CPU1.
  • PWR_FLAG_SB System Standby Flag for CPU1.
  • PWR_FLAG_C2STOP System Stop Flag for CPU2.
  • PWR_FLAG_C2SB System Standby Flag for CPU2.
  • PWR_FLAG_CRITICAL_RF_PHASE RF phase Flag.
Return values:
None

Definition at line 283 of file stm32wbxx_hal_pwr.h.

#define __HAL_PWR_GET_FLAG ( __FLAG__ )
Value:
( ((((uint8_t)(__FLAG__)) >> 5U) == 1U)  ?\
                                      (PWR->SR1 & (1U << ((__FLAG__) & 31U))) :\
                                      ((((((uint8_t)(__FLAG__)) >> 5U) == 2U)) ?\
                                      (PWR->SR2 & (1U << ((__FLAG__) & 31U))) :\
                                      (PWR->EXTSCR & (1U << ((__FLAG__) & 31U))) ) )

Check whether or not a specific PWR flag is set.

Parameters:
__FLAG__ specifies the flag to check. This parameter can be one of the following values:

/--------------------------------SR1-------------------------------/

  • PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event was received from the WKUP pin 1.
  • PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event was received from the WKUP pin 2.
  • PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event was received from the WKUP pin 3.
  • PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event was received from the WKUP pin 4.
  • PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event was received from the WKUP pin 5.
  • PWR_FLAG_BHWF BLE_Host WakeUp Flag
  • PWR_FLAG_FRCBYPI SMPS Forced in Bypass Interrupt Flag
  • PWR_FLAG_RFPHASEI Radio Phase Interrupt Flag
  • PWR_FLAG_BLEACTI BLE Activity Interrupt Flag
  • PWR_FLAG_802ACTI 802.15.4 Activity Interrupt Flag
  • PWR_FLAG_HOLDC2I CPU2 on-Hold Interrupt Flag
  • PWR_FLAG_WUFI Wake-Up Flag Internal. Set when a wakeup is detected on the internal wakeup line.
  • PWR_FLAG_SMPSRDYF SMPS Ready Flag
  • PWR_FLAG_SMPSBYPF SMPS Bypass Flag

/--------------------------------SR2-------------------------------/

  • PWR_FLAG_REGLPS Low Power Regulator Started. Indicates whether or not the low-power regulator is ready.
  • PWR_FLAG_REGLPF Low Power Regulator Flag. Indicates whether the regulator is ready in main mode or is in low-power mode.
  • PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready in the selected voltage range or is still changing to the required voltage level.
  • PWR_FLAG_PVDO Power Voltage Detector Output. Indicates whether VDD voltage is below or above the selected PVD threshold.
  • PWR_FLAG_PVMO1 Peripheral Voltage Monitoring Output 1. Indicates whether VDDUSB voltage is is below or above PVM1 threshold (applicable when USB feature is supported).
  • PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3. Indicates whether VDDA voltage is is below or above PVM3 threshold.

/----------------------------EXTSCR--------------------------/

  • PWR_FLAG_STOP System Stop Flag for CPU1.
  • PWR_FLAG_SB System Standby Flag for CPU1.
  • PWR_FLAG_C2STOP System Stop Flag for CPU2.
  • PWR_FLAG_C2SB System Standby Flag for CPU2.
  • PWR_FLAG_CRITICAL_RF_PHASE Critical radio system phase flag.
  • PWR_FLAG_C1DEEPSLEEP CPU1 DeepSleep Flag.
  • PWR_FLAG_C2DEEPSLEEP CPU2 DeepSleep Flag.
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 238 of file stm32wbxx_hal_pwr.h.

#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG ( ) LL_EXTI_ClearFlag_0_31(PWR_EXTI_LINE_PVD)

Clear the PVD EXTI interrupt flag.

Return values:
None

Definition at line 388 of file stm32wbxx_hal_pwr.h.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE ( ) LL_EXTI_DisableRisingTrig_0_31(PWR_EXTI_LINE_PVD)

Disable the PVD Extended Interrupt Falling Trigger.

Note:
PVD flag polarity is inverted compared to EXTI line, therefore EXTI rising and falling logic edges are inverted versus PVD voltage edges.
Return values:
None

Definition at line 349 of file stm32wbxx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_DISABLE_IT ( ) LL_EXTI_DisableIT_0_31(PWR_EXTI_LINE_PVD)

Disable the PVD Extended Interrupt C1 Line.

Return values:
None

Definition at line 307 of file stm32wbxx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE ( ) LL_EXTI_DisableFallingTrig_0_31(PWR_EXTI_LINE_PVD)

Disable the PVD Extended Interrupt Rising Trigger.

Note:
PVD flag polarity is inverted compared to EXTI line, therefore EXTI rising and falling logic edges are inverted versus PVD voltage edges.
Return values:
None

Definition at line 332 of file stm32wbxx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                    \
    __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();             \
    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();            \
  } while(0)

Disable the PVD Extended Interrupt Rising & Falling Trigger.

Return values:
None

Definition at line 366 of file stm32wbxx_hal_pwr.h.

#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE ( ) LL_EXTI_EnableFallingTrig_0_31(PWR_EXTI_LINE_PVD)

Enable the PVD Extended Interrupt Falling Trigger.

Note:
PVD flag polarity is inverted compared to EXTI line, therefore EXTI rising and falling logic edges are inverted versus PVD voltage edges.
Return values:
None

Definition at line 340 of file stm32wbxx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_ENABLE_IT ( ) LL_EXTI_EnableIT_0_31(PWR_EXTI_LINE_PVD)

Enable the PVD Extended Interrupt C1 Line.

Return values:
None

Definition at line 294 of file stm32wbxx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE ( ) LL_EXTI_EnableRisingTrig_0_31(PWR_EXTI_LINE_PVD)

Enable the PVD Extended Interrupt Rising Trigger.

Note:
PVD flag polarity is inverted compared to EXTI line, therefore EXTI rising and falling logic edges are inverted versus PVD voltage edges.
Return values:
None

Definition at line 324 of file stm32wbxx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                   \
    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();             \
    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();            \
  } while(0)

Enable the PVD Extended Interrupt Rising & Falling Trigger.

Return values:
None

Definition at line 356 of file stm32wbxx_hal_pwr.h.

#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT ( ) LL_EXTI_GenerateSWI_0_31(PWR_EXTI_LINE_PVD)

Generate a Software interrupt on selected EXTI line.

Return values:
None

Definition at line 376 of file stm32wbxx_hal_pwr.h.

#define __HAL_PWR_PVD_EXTI_GET_FLAG ( ) LL_EXTI_ReadFlag_0_31(PWR_EXTI_LINE_PVD)

Check whether or not the PVD EXTI interrupt flag is set.

Return values:
EXTI PVD Line Status.

Definition at line 382 of file stm32wbxx_hal_pwr.h.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

#define __HAL_PWR_PVD_EXTIC2_DISABLE_IT ( ) LL_C2_EXTI_DisableIT_0_31(PWR_EXTI_LINE_PVD)

Disable the PVD Extended Interrupt C2 Line.

Return values:
None

Definition at line 313 of file stm32wbxx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTIC2_ENABLE_IT ( ) LL_C2_EXTI_EnableIT_0_31(PWR_EXTI_LINE_PVD)

Enable the PVD Extended Interrupt C2 Line.

Return values:
None

Definition at line 300 of file stm32wbxx_hal_pwr.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PWR Private Macros

Defines
PWR Private Macros
PWR

Defines

#define | IS_PWR_PVD_LEVEL(LEVEL)
#define | IS_PWR_PVD_MODE(MODE)
#define | IS_PWR_REGULATOR(REGULATOR)
#define | IS_PWR_SLEEP_ENTRY(ENTRY)
#define | IS_PWR_STOP_ENTRY(ENTRY)

Define Documentation

#define IS_PWR_PVD_LEVEL ( LEVEL )
Value:
(((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
                                 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
                                 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
                                 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))

Definition at line 400 of file stm32wbxx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define IS_PWR_PVD_MODE ( MODE )
Value:
(((MODE) == PWR_PVD_MODE_NORMAL)              ||\
                                ((MODE) == PWR_PVD_MODE_IT_RISING)           ||\
                                ((MODE) == PWR_PVD_MODE_IT_FALLING)          ||\
                                ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING))

Definition at line 405 of file stm32wbxx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define IS_PWR_REGULATOR ( REGULATOR )
Value:
(((REGULATOR) == PWR_MAINREGULATOR_ON)    || \
                                                   ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))

Definition at line 412 of file stm32wbxx_hal_pwr.h.

Referenced by HAL_PWR_EnterSLEEPMode(), and HAL_PWR_EnterSTOPMode().

#define IS_PWR_SLEEP_ENTRY ( ENTRY )
Value:
(((ENTRY) == PWR_SLEEPENTRY_WFI) || \
                                                   ((ENTRY) == PWR_SLEEPENTRY_WFE))

Definition at line 416 of file stm32wbxx_hal_pwr.h.

Referenced by HAL_PWR_EnterSLEEPMode().

#define IS_PWR_STOP_ENTRY ( ENTRY )
Value:
(((ENTRY) == PWR_STOPENTRY_WFI) || \
                                                   ((ENTRY) == PWR_STOPENTRY_WFE))

Definition at line 419 of file stm32wbxx_hal_pwr.h.

Referenced by HAL_PWREx_EnterSTOP0Mode(), HAL_PWREx_EnterSTOP1Mode(), and HAL_PWREx_EnterSTOP2Mode().

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
PWR Exported Functions

Initialization and de-initialization functions. More...

Functions

void | HAL_PWR_DeInit (void)
Deinitialize the HAL PWR peripheral registers to their default reset values.
void | HAL_PWR_EnableBkUpAccess (void)
Enable access to the backup domain (RTC registers, RTC backup data registers).
void | HAL_PWR_DisableBkUpAccess (void)
Disable access to the backup domain (RTC registers, RTC backup data registers).

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]

Function Documentation

void HAL_PWR_DeInit ( void )

Deinitialize the HAL PWR peripheral registers to their default reset values.

Return values:
None

Definition at line 101 of file stm32wbxx_hal_pwr.c.

References LL_PWR_EXTSCR_C1CSSF, LL_PWR_EXTSCR_C2CSSF, LL_PWR_EXTSCR_CCRPF, LL_PWR_SCR_C802AF, LL_PWR_SCR_C802WUF, LL_PWR_SCR_CBLEAF, LL_PWR_SCR_CBLEWUF, LL_PWR_SCR_CBORHF, LL_PWR_SCR_CC2HF, LL_PWR_SCR_CCRPEF, LL_PWR_SCR_CSMPSFBF, LL_PWR_SCR_CWUF, LL_PWR_WriteReg, PWR_C2CR1_RESET_VALUE, PWR_C2CR3_RESET_VALUE, PWR_CR1_RESET_VALUE, PWR_CR2_RESET_VALUE, PWR_CR3_RESET_VALUE, PWR_CR4_RESET_VALUE, PWR_CR5_RESET_VALUE, PWR_PDCRA_RESET_VALUE, PWR_PDCRB_RESET_VALUE, PWR_PDCRC_RESET_VALUE, PWR_PDCRD_RESET_VALUE, PWR_PDCRE_RESET_VALUE, PWR_PDCRH_RESET_VALUE, PWR_PUCRA_RESET_VALUE, PWR_PUCRB_RESET_VALUE, PWR_PUCRC_RESET_VALUE, PWR_PUCRD_RESET_VALUE, PWR_PUCRE_RESET_VALUE, and PWR_PUCRH_RESET_VALUE.

void HAL_PWR_DisableBkUpAccess ( void )

Disable access to the backup domain (RTC registers, RTC backup data registers).

Return values:
None

Definition at line 173 of file stm32wbxx_hal_pwr.c.

Referenced by HAL_RCCEx_DisableLSCO(), HAL_RCCEx_EnableLSCO(), and HAL_RCCEx_LSCOConfig().

void HAL_PWR_EnableBkUpAccess ( void )

Enable access to the backup domain (RTC registers, RTC backup data registers).

Note:
After reset, the backup domain is protected against possible unwanted write accesses.
RTCSEL that sets the RTC clock source selection is in the RTC back-up domain. In order to set or modify the RTC clock, the backup domain access must be disabled.
LSEON bit that switches on and off the LSE crystal belongs as well to the back-up domain.
Return values:
None

Definition at line 163 of file stm32wbxx_hal_pwr.c.

Referenced by HAL_RCC_OscConfig(), HAL_RCCEx_DisableLSCO(), HAL_RCCEx_EnableLSCO(), HAL_RCCEx_LSCOConfig(), and HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
PWR Exported Functions

Low Power modes configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
Configure the voltage threshold detected by the Power Voltage Detector (PVD).
void | HAL_PWR_EnablePVD (void)
Enables the Power Voltage Detector(PVD).
void | HAL_PWR_DisablePVD (void)
Disables the Power Voltage Detector(PVD).
void | HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity)
Enable the WakeUp PINx functionality.
void | HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
Disable the WakeUp PINx functionality.
void | HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
Enter Sleep or Low-power Sleep mode.
void | HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
Enter Stop mode.
void | HAL_PWR_EnterSTANDBYMode (void)
Enter Standby mode.
void | HAL_PWR_EnableSleepOnExit (void)
Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.
void | HAL_PWR_DisableSleepOnExit (void)
Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
void | HAL_PWR_EnableSEVOnPend (void)
Enable CORTEX M4 SEVONPEND bit.
void | HAL_PWR_DisableSEVOnPend (void)
Disable CORTEX M4 SEVONPEND bit.
__weak void | HAL_PWR_PVDCallback (void)
PWR PVD interrupt callback.

Detailed Description

Low Power modes configuration functions.

 ===============================================================================
                 ##### Peripheral Control functions #####
 ===============================================================================

    [..]
     *** PVD configuration ***
    =========================
    [..]
      (+) The PVD is used to monitor the VDD power supply by comparing it to a
          threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2 register).
      (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower
          than the PVD threshold. This event is internally connected to the EXTI
          line16 and can generate an interrupt if enabled. This is done through
          __HAL_PVD_EXTI_ENABLE_IT() macro.
      (+) The PVD is stopped in Standby mode.

    *** WakeUp pin configuration ***
    ================================
    [..]
      (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode.
          The polarity of these pins can be set to configure event detection on high
          level (rising edge) or low level (falling edge).

    *** Low Power modes configuration ***
    =====================================
    [..]
      The devices feature 8 low-power modes:

      (+) Low-power Run mode: core and peripherals are running, main regulator off, low power regulator on.

      (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and low power regulators on.
      (+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator off, low power regulator on.

      (+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on.
      (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on.
      (+) Stop 2 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on, reduced set of waking up IPs compared to Stop 1 mode.

      (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on.
      (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off.

      (+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off.

   *** Low-power run mode ***
   ==========================
    [..]
      (+) Entry: (from main run mode)
          (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz.
      (+) Exit:
          (++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMode() API. Only
               then can the system clock frequency be increased above 2 MHz.

   *** Sleep mode / Low-power sleep mode ***
   =========================================
    [..]
      (+) Entry:
          The Sleep mode / Low-power Sleep mode is entered thru HAL_PWR_EnterSLEEPMode() API
          in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered.
          (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
          (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).
          In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand.
          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction

      (+) WFI Exit:
        (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
             controller (NVIC) or any wake-up event.

      (+) WFE Exit:
        (++) Any wake-up event such as an EXTI line configured in event mode.

    [..]  When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event,
          the MCU is in Low-power Run mode.

   *** Stop 0, Stop 1 and Stop 2 modes ***
   ===============================
    [..]
      (+) Entry:
          The Stop 0, Stop 1 or Stop 2 modes are entered thru the following API's:
          (++) HAL_PWREx_EnterSTOP0Mode() for mode 0, HAL_PWREx_EnterSTOP1Mode() for mode 1, HAL_PWREx_EnterSTOP2Mode() for mode 2
               or for porting reasons HAL_PWR_EnterSTOPMode().

      (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
          (++) PWR_MAINREGULATOR_ON: Regulator in main mode (STOP0 mode)
          (++) PWR_LOWPOWERREGULATOR_ON: Regulator in low-power mode (STOP1 mode)
      (+) Exit (interrupt or event-triggered, specified when entering STOP mode):
          (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
          (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction
      (+) WFI Exit:
          (++) Any EXTI Line (Internal or External) configured in Interrupt mode.
          (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts
               when programmed in wakeup mode.
      (+) WFE Exit:
          (++) Any EXTI Line (Internal or External) configured in Event mode.

       [..]
          When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run mode
          depending on the LPR bit setting.
          When exiting Stop 2 mode, the MCU is in Run mode.

   *** Standby mode ***
   ====================
    [..] The Standby mode offers two options:
      (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low power mode).
          SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers
          and Standby circuitry.
      (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disabled).
          SRAM and register contents are lost except for the RTC registers, RTC backup registers
          and Standby circuitry.

      (++) Entry:
          (+++) The Standby mode is entered thru HAL_PWR_EnterSTANDBYMode() API.
                SRAM1 and register contents are lost except for registers in the Backup domain and
                Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
                To enable this feature, the user can resort to HAL_PWREx_EnableBKRAMContentRetention() API
                to set RRS bit.
      (++) Exit:
          (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
                external reset in NRST pin, IWDG reset.
    [..] After waking up from Standby mode, program execution restarts in the same way as after a Reset.

    *** Shutdown mode ***
   ======================
    [..]
      In Shutdown mode,
        voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared.
        SRAM and registers contents are lost except for backup domain registers.
      (+) Entry:
          The Shutdown mode is entered thru HAL_PWREx_EnterSHUTDOWNMode() API.
      (+) Exit:
          (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
               external reset in NRST pin.
    [..] After waking up from Shutdown mode, program execution restarts in the same way as after a Reset.

   *** Auto-wakeup (AWU) from low-power mode ***
   =============================================
    [..]
      The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
      Wakeup event, a tamper event or a time-stamp event, without depending on
      an external interrupt (Auto-wakeup mode).

      (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes

        (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
             configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.

        (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
             is necessary to configure the RTC to detect the tamper or time stamp event using the
             HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.

        (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
              configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.

Function Documentation

HAL_StatusTypeDef HAL_PWR_ConfigPVD ( PWR_PVDTypeDef * sConfigPVD )

Configure the voltage threshold detected by the Power Voltage Detector (PVD).

Parameters:
sConfigPVD pointer to a PWR_PVDTypeDef structure that contains the PVD configuration information.
Note:
Refer to the electrical characteristics of your device datasheet for more details about the voltage thresholds corresponding to each detection level.
If "sConfigPVD->Mode" is set to PVD_MODE_IT, wake-up target is set by default to wake-up target CPU1. To select wake-up target to CPU2, additional configuration must be performed using macro "__HAL_PWR_PVD_EXTIC2_ENABLE_IT()" (and optionally, to select CPU2 only (not both CPU1 and CPU2): "__HAL_PWR_PVD_EXTI_DISABLE_IT()").
Return values:
None

Definition at line 363 of file stm32wbxx_hal_pwr.c.

References __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE, __HAL_PWR_PVD_EXTI_DISABLE_IT, __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE, __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE, __HAL_PWR_PVD_EXTI_ENABLE_IT, __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE, __HAL_PWR_PVD_EXTIC2_DISABLE_IT, assert_param, IS_PWR_PVD_LEVEL, IS_PWR_PVD_MODE, PWR_PVDTypeDef::Mode, PVD_FALLING_EDGE, PVD_MODE_IT, PVD_RISING_EDGE, and PWR_PVDTypeDef::PVDLevel.

void HAL_PWR_DisablePVD ( void )

Disables the Power Voltage Detector(PVD).

Return values:
None

Definition at line 417 of file stm32wbxx_hal_pwr.c.

void HAL_PWR_DisableSEVOnPend ( void )

Disable CORTEX M4 SEVONPEND bit.

Note:
Clear SEVONPEND bit of SCR register. When this bit is set, this causes WFE to wake up when an interrupt moves from inactive to pended.
Return values:
None

Definition at line 682 of file stm32wbxx_hal_pwr.c.

void HAL_PWR_DisableSleepOnExit ( void )

Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.

Note:
Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor re-enters SLEEP mode when an interruption handling is over.
Return values:
None

Definition at line 656 of file stm32wbxx_hal_pwr.c.

void HAL_PWR_DisableWakeUpPin ( uint32_t WakeUpPinx )

Disable the WakeUp PINx functionality.

Parameters:
WakeUpPinx Specifies the Power Wake-Up pin to disable. This parameter can be one of the following values:
  • PWR_WAKEUP_PIN1: An event on PA0 PIN wakes-up the system from Standby mode.
  • PWR_WAKEUP_PIN2: An event on PC13 PIN wakes-up the system from Standby mode.
  • PWR_WAKEUP_PIN3: An event on PC12 PIN wakes-up the system from Standby mode.
  • PWR_WAKEUP_PIN4: An event on PA2 PIN wakes-up the system from Standby mode.
  • PWR_WAKEUP_PIN5: An event on PC5 PIN wakes-up the system from Standby mode.
Return values:
None

Definition at line 464 of file stm32wbxx_hal_pwr.c.

References assert_param, and IS_PWR_WAKEUP_PIN.

void HAL_PWR_EnablePVD ( void )

Enables the Power Voltage Detector(PVD).

Return values:
None

Definition at line 407 of file stm32wbxx_hal_pwr.c.

void HAL_PWR_EnableSEVOnPend ( void )

Enable CORTEX M4 SEVONPEND bit.

Note:
Set SEVONPEND bit of SCR register. When this bit is set, this causes WFE to wake up when an interrupt moves from inactive to pended.
Return values:
None

Definition at line 669 of file stm32wbxx_hal_pwr.c.

void HAL_PWR_EnableSleepOnExit ( void )

Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.

Note:
Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor re-enters SLEEP mode when an interruption handling is over. Setting this bit is useful when the processor is expected to run only on interruptions handling.
Return values:
None

Definition at line 644 of file stm32wbxx_hal_pwr.c.

void HAL_PWR_EnableWakeUpPin ( uint32_t WakeUpPinPolarity )

Enable the WakeUp PINx functionality.

Parameters:
WakeUpPinPolarity Specifies which Wake-Up pin to enable. This parameter can be one of the following legacy values which set the default polarity i.e. detection on high level (rising edge):
  • PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
or one of the following value where the user can explicitly specify the enabled pin and the chosen polarity:
  • PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
  • PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
  • PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
  • PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
  • PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
Note:
PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
Return values:
None

Definition at line 441 of file stm32wbxx_hal_pwr.c.

References assert_param, IS_PWR_WAKEUP_PIN, and PWR_WUP_POLARITY_SHIFT.

void HAL_PWR_EnterSLEEPMode | ( | uint32_t | Regulator,
 |  | uint8_t | SLEEPEntry
 | ) |  |

Enter Sleep or Low-power Sleep mode.

Note:
In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode.
Parameters:
Regulator Specifies the regulator state in Sleep/Low-power Sleep mode. This parameter can be one of the following values:
  • PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)
  • PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode)
Note:
Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the Flash in power-down mode in setting the SLEEP_PD bit in FLASH_ACR register. Additionally, the clock frequency must be reduced below 2 MHz. Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must be done before calling HAL_PWR_EnterSLEEPMode() API.
When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API.
Parameters:
SLEEPEntry Specifies if Sleep mode is entered with WFI or WFE instruction. This parameter can be one of the following values:
  • PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction
  • PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction
Note:
When WFI entry is used, tick interrupt have to be disabled if not desired as the interrupt wake up source.
Return values:
None

Definition at line 495 of file stm32wbxx_hal_pwr.c.

References assert_param, HAL_PWREx_DisableLowPowerRunMode(), HAL_PWREx_EnableLowPowerRunMode(), IS_PWR_REGULATOR, IS_PWR_SLEEP_ENTRY, PWR_MAINREGULATOR_ON, and PWR_SLEEPENTRY_WFI.

void HAL_PWR_EnterSTANDBYMode ( void )

Enter Standby mode.

Note:
In Standby mode, the PLL, the HSI, the MSI and the HSE oscillators are switched off. The voltage regulator is disabled, except when BKRAM content is preserved in which case the regulator is in low-power mode. SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry. BKRAM content can be preserved if the bit RRS is set in PWR_CR3 register. To enable this feature, the user can resort to HAL_PWREx_EnableBKRAMContentRetention() API to set RRS bit. The BOR is available.
The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state. HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the same. These states are effective in Standby mode only if APC bit is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
According to system power policy, system entering in Standby mode is depending on other CPU power mode.
Return values:
None

Definition at line 613 of file stm32wbxx_hal_pwr.c.

References PWR_LOWPOWERMODE_STANDBY.

void HAL_PWR_EnterSTOPMode | ( | uint32_t | Regulator,
 |  | uint8_t | STOPEntry
 | ) |  |

Enter Stop mode.

Note:
This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running on devices where only "Stop mode" is mentioned with main or low power regulator ON.
In Stop mode, all I/O pins keep the same state as in Run mode.
All clocks in the VCORE domain are stopped; the PLL, the MSI, the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated only to the peripheral requesting it. SRAM1, SRAM2 and register contents are preserved. The BOR is available. The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1).
When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register is set; the MSI oscillator is selected if STOPWUCK is cleared.
When the voltage regulator operates in low power mode (Stop 1), an additional startup delay is incurred when waking up. By keeping the internal regulator ON during Stop mode (Stop 0), the consumption is higher although the startup time is reduced.
Case of Stop0 mode with SMPS: Before entering Stop 0 mode with SMPS Step Down converter enabled, the HSI16 must be kept on by enabling HSI kernel clock (set HSIKERON register bit).
According to system power policy, system entering in Stop mode is depending on other CPU power mode.
Parameters:
Regulator Specifies the regulator state in Stop mode. This parameter can be one of the following values:
  • PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON)
  • PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power regulator ON)
STOPEntry Specifies Stop 0, Stop 1 or Stop 2 mode is entered with WFI or WFE instruction. This parameter can be one of the following values:
  • PWR_STOPENTRY_WFI Enter Stop 0 or Stop 1 mode with WFI instruction.
  • PWR_STOPENTRY_WFE Enter Stop 0 or Stop 1 mode with WFE instruction.
Return values:
None

Definition at line 577 of file stm32wbxx_hal_pwr.c.

References assert_param, HAL_PWREx_EnterSTOP0Mode(), HAL_PWREx_EnterSTOP1Mode(), IS_PWR_REGULATOR, and PWR_LOWPOWERREGULATOR_ON.

void HAL_PWR_PVDCallback ( void )

PWR PVD interrupt callback.

Return values:
None

Definition at line 693 of file stm32wbxx_hal_pwr.c.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

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STM32WB55xx HAL User Manual: PWR Extended Flag Setting Time Out Value

Defines
PWR Extended Flag Setting Time Out Value
PWR Extended Private Defines

Defines

#define PWR_FLAG_SETTING_DELAY_US 50U

Define Documentation

#define PWR_FLAG_SETTING_DELAY_US 50U

Time out value for REGLPF and VOSF flags setting

Definition at line 49 of file stm32wbxx_hal_pwr_ex.c.

Referenced by HAL_PWREx_ControlVoltageScaling(), and HAL_PWREx_DisableLowPowerRunMode().

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STM32WB55xx HAL User Manual: PWR Extended Private Defines

Modules | Defines
PWR Extended Private Defines
PWREx

Modules

PWR Extended Flag Setting Time Out Value

Defines

#define | PWR_PORTE_AVAILABLE_PINS (PWR_GPIO_BIT_4 | PWR_GPIO_BIT_3 | PWR_GPIO_BIT_2 | PWR_GPIO_BIT_1 | PWR_GPIO_BIT_0)
#define | PWR_PORTH_AVAILABLE_PINS (PWR_GPIO_BIT_3 | PWR_GPIO_BIT_1 | PWR_GPIO_BIT_0)

Define Documentation

#define PWR_PORTE_AVAILABLE_PINS (PWR_GPIO_BIT_4 | PWR_GPIO_BIT_3 | PWR_GPIO_BIT_2 | PWR_GPIO_BIT_1 | PWR_GPIO_BIT_0)

Definition at line 43 of file stm32wbxx_hal_pwr_ex.c.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define PWR_PORTH_AVAILABLE_PINS (PWR_GPIO_BIT_3 | PWR_GPIO_BIT_1 | PWR_GPIO_BIT_0)

Definition at line 44 of file stm32wbxx_hal_pwr_ex.c.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

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STM32WB55xx HAL User Manual: PWR_PVMTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PWR_PVMTypeDef Struct Reference
PWR Extended Exported Types

PWR PVM configuration structure definition. More...

#include <stm32wbxx_hal_pwr_ex.h>

Data Fields

uint32_t | PVMType
uint32_t | Mode
uint32_t | WakeupTarget

Detailed Description

PWR PVM configuration structure definition.

Definition at line 50 of file stm32wbxx_hal_pwr_ex.h.

Field Documentation

uint32_t PWR_PVMTypeDef::Mode

Mode: Specifies the operating mode for the selected pins. This parameter can be a value of PWR PVM interrupt and event mode.

Definition at line 58 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

uint32_t PWR_PVMTypeDef::PVMType

PVMType: Specifies which voltage is monitored and against which threshold. This parameter can be a value of Peripheral Voltage Monitoring type.

  • PWR_PVM_1 Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported).
  • PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V.

Definition at line 52 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

uint32_t PWR_PVMTypeDef::WakeupTarget

Specifies the Wakeup Target This parameter can be a value of PWR Wakeup Target Definition

Definition at line 60 of file stm32wbxx_hal_pwr_ex.h.

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_pwr_ex.h
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STM32WB55xx HAL User Manual: PWR_SMPSTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PWR_SMPSTypeDef Struct Reference
PWR Extended Exported Types

PWR SMPS step down configuration structure definition. More...

#include <stm32wbxx_hal_pwr_ex.h>

Data Fields

uint32_t | StartupCurrent
uint32_t | OutputVoltage

Detailed Description

PWR SMPS step down configuration structure definition.

Definition at line 68 of file stm32wbxx_hal_pwr_ex.h.

Field Documentation

uint32_t PWR_SMPSTypeDef::OutputVoltage

SMPS step down converter output voltage scaling voltage level. This parameter can be a value of SMPS step down converter output voltage scaling voltage level

Definition at line 73 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigSMPS().

uint32_t PWR_SMPSTypeDef::StartupCurrent

SMPS step down converter supply startup current selection. This parameter can be a value of SMPS step down converter supply startup current selection.

Definition at line 70 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigSMPS().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_pwr_ex.h
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STM32WB55xx HAL User Manual: Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants

Defines
Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants
PWR Extended Exported Constants

Defines

#define PWR_WUP_POLARITY_SHIFT 0x05U

Define Documentation

#define PWR_WUP_POLARITY_SHIFT 0x05U

Internal constant used to retrieve wakeup pin polarity

Definition at line 91 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWR_EnableWakeUpPin(), and HAL_PWREx_EnableWakeUpPin().

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PWR wake-up pins

Defines
PWR wake-up pins
PWR Extended Exported Constants

Defines

#define | PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1
#define | PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2
#define | PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3
#define | PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4
#define | PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5
#define | PWR_WAKEUP_PIN1_LOW ((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1)
#define | PWR_WAKEUP_PIN2_LOW ((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2)
#define | PWR_WAKEUP_PIN3_LOW ((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3)
#define | PWR_WAKEUP_PIN4_LOW ((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4)
#define | PWR_WAKEUP_PIN5_LOW ((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5)

Define Documentation

#define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1

Wakeup pin 1 (with high level polarity)

Definition at line 100 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN1_LOW ((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1)

Wakeup pin 1 (with low level polarity)

Definition at line 112 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2

Wakeup pin 2 (with high level polarity)

Definition at line 102 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN2_LOW ((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2)

Wakeup pin 2 (with low level polarity)

Definition at line 114 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3

Wakeup pin 3 (with high level polarity)

Definition at line 105 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN3_LOW ((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3)

Wakeup pin 3 (with low level polarity)

Definition at line 117 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4

Wakeup pin 4 (with high level polarity)

Definition at line 107 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN4_LOW ((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4)

Wakeup pin 4 (with low level polarity)

Definition at line 119 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5

Wakeup pin 5 (with high level polarity)

Definition at line 109 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN5_LOW ((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5)

Wakeup pin 5 (with low level polarity)

Definition at line 121 of file stm32wbxx_hal_pwr_ex.h.

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STM32WB55xx HAL User Manual: PWREx Pin Polarity configuration

Defines
PWREx Pin Polarity configuration
PWR Extended Exported Constants

Defines

#define | PWR_PIN_POLARITY_HIGH 0x00000000U
#define | PWR_PIN_POLARITY_LOW 0x00000001U

Define Documentation

#define PWR_PIN_POLARITY_HIGH 0x00000000U

Definition at line 143 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_PIN_POLARITY_LOW 0x00000001U

Definition at line 144 of file stm32wbxx_hal_pwr_ex.h.

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STM32WB55xx HAL User Manual: Peripheral Voltage Monitoring type

Defines
Peripheral Voltage Monitoring type
PWR Extended Exported Constants

Defines

#define | PWR_PVM_1 PWR_CR2_PVME1
#define | PWR_PVM_3 PWR_CR2_PVME3

Define Documentation

#define PWR_PVM_1 PWR_CR2_PVME1

Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported)

Definition at line 153 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM(), HAL_PWREx_DisablePVM1(), and HAL_PWREx_EnablePVM1().

#define PWR_PVM_3 PWR_CR2_PVME3

Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V

Definition at line 155 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM(), HAL_PWREx_DisablePVM3(), and HAL_PWREx_EnablePVM3().

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STM32WB55xx HAL User Manual: PWR PVM interrupt and event mode

Defines
PWR PVM interrupt and event mode
PWR Extended Exported Constants

Defines

#define | PWR_PVM_MODE_NORMAL (0x00000000U)
#define | PWR_PVM_MODE_IT_RISING (PVM_MODE_IT | PVM_RISING_EDGE)
#define | PWR_PVM_MODE_IT_FALLING (PVM_MODE_IT | PVM_FALLING_EDGE)
#define | PWR_PVM_MODE_IT_RISING_FALLING (PVM_MODE_IT | PVM_RISING_FALLING_EDGE)
#define | PWR_PVM_MODE_EVENT_RISING (PVM_MODE_EVT | PVM_RISING_EDGE)
#define | PWR_PVM_MODE_EVENT_FALLING (PVM_MODE_EVT | PVM_FALLING_EDGE)
#define | PWR_PVM_MODE_EVENT_RISING_FALLING (PVM_MODE_EVT | PVM_RISING_FALLING_EDGE)

Define Documentation

#define PWR_PVM_MODE_EVENT_FALLING (PVM_MODE_EVT | PVM_FALLING_EDGE)

Event Mode with Falling edge trigger detection

Definition at line 170 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_PVM_MODE_EVENT_RISING (PVM_MODE_EVT | PVM_RISING_EDGE)

Event Mode with Rising edge trigger detection

Definition at line 169 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_PVM_MODE_EVENT_RISING_FALLING (PVM_MODE_EVT | PVM_RISING_FALLING_EDGE)

Event Mode with Rising/Falling edge trigger detection

Definition at line 171 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_PVM_MODE_IT_FALLING (PVM_MODE_IT | PVM_FALLING_EDGE)

External Interrupt Mode with Falling edge trigger detection

Definition at line 166 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_PVM_MODE_IT_RISING (PVM_MODE_IT | PVM_RISING_EDGE)

External Interrupt Mode with Rising edge trigger detection

Definition at line 165 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_PVM_MODE_IT_RISING_FALLING (PVM_MODE_IT | PVM_RISING_FALLING_EDGE)

External Interrupt Mode with Rising/Falling edge trigger detection

Definition at line 167 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_PVM_MODE_NORMAL (0x00000000U)

basic mode is used

Definition at line 163 of file stm32wbxx_hal_pwr_ex.h.

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STM32WB55xx HAL User Manual: Flash Power Down modes

Defines
Flash Power Down modes
PWR Extended Exported Constants

Defines

#define | PWR_FLASHPD_LPRUN PWR_CR1_FPDR
#define | PWR_FLASHPD_LPSLEEP PWR_CR1_FPDS

Define Documentation

#define PWR_FLASHPD_LPRUN PWR_CR1_FPDR

Enable Flash power down in low power run mode

Definition at line 179 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_EnableFlashPowerDown().

#define PWR_FLASHPD_LPSLEEP PWR_CR1_FPDS

Enable Flash power down in low power sleep mode

Definition at line 180 of file stm32wbxx_hal_pwr_ex.h.

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STM32WB55xx HAL User Manual: PWR Regulator voltage scale

Defines
PWR Regulator voltage scale
PWR Extended Exported Constants

Defines

#define | PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0
#define | PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1

Define Documentation

#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0

Regulator voltage output range 1 mode, typical output voltage at 1.2 V, system frequency up to 64 MHz

Definition at line 189 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ControlVoltageScaling(), RCC_SetFlashLatency(), and RCC_SetFlashLatencyFromMSIRange().

#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1

Regulator voltage output range 2 mode, typical output voltage at 1.0 V, system frequency up to 16 MHz

Definition at line 190 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ControlVoltageScaling().

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STM32WB55xx HAL User Manual: PWR battery charging resistor selection

Defines
PWR battery charging resistor selection
PWR Extended Exported Constants

Defines

#define | PWR_BATTERY_CHARGING_RESISTOR_5 (0x00000000U)
#define | PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS

Define Documentation

#define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS

VBAT charging through a 1.5 kOhms resistor

Definition at line 203 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_BATTERY_CHARGING_RESISTOR_5 (0x00000000U)

VBAT charging through a 5 kOhms resistor

Definition at line 202 of file stm32wbxx_hal_pwr_ex.h.

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STM32WB55xx HAL User Manual: PWR battery charging

Defines
PWR battery charging
PWR Extended Exported Constants

Defines

#define | PWR_BATTERY_CHARGING_DISABLE (0x00000000U)
#define | PWR_BATTERY_CHARGING_ENABLE PWR_CR4_VBE

Define Documentation

#define PWR_BATTERY_CHARGING_DISABLE (0x00000000U)

Definition at line 211 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_BATTERY_CHARGING_ENABLE PWR_CR4_VBE

Definition at line 212 of file stm32wbxx_hal_pwr_ex.h.

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STM32WB55xx HAL User Manual: GPIO bit number for I/O setting in standby/shutdown mode

Defines
GPIO bit number for I/O setting in standby/shutdown mode
PWR Extended Exported Constants

Defines

#define | PWR_GPIO_BIT_0 PWR_PUCRA_PA0
#define | PWR_GPIO_BIT_1 PWR_PUCRA_PA1
#define | PWR_GPIO_BIT_2 PWR_PUCRA_PA2
#define | PWR_GPIO_BIT_3 PWR_PUCRA_PA3
#define | PWR_GPIO_BIT_4 PWR_PUCRA_PA4
#define | PWR_GPIO_BIT_5 PWR_PUCRA_PA5
#define | PWR_GPIO_BIT_6 PWR_PUCRA_PA6
#define | PWR_GPIO_BIT_7 PWR_PUCRA_PA7
#define | PWR_GPIO_BIT_8 PWR_PUCRA_PA8
#define | PWR_GPIO_BIT_9 PWR_PUCRA_PA9
#define | PWR_GPIO_BIT_10 PWR_PUCRA_PA10
#define | PWR_GPIO_BIT_11 PWR_PUCRA_PA11
#define | PWR_GPIO_BIT_12 PWR_PUCRA_PA12
#define | PWR_GPIO_BIT_13 PWR_PUCRA_PA13
#define | PWR_GPIO_BIT_14 PWR_PDCRC_PC14
#define | PWR_GPIO_BIT_15 PWR_PUCRC_PC15

Define Documentation

#define PWR_GPIO_BIT_0 PWR_PUCRA_PA0

GPIO port I/O pin 0

Definition at line 220 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_1 PWR_PUCRA_PA1

GPIO port I/O pin 1

Definition at line 221 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_10 PWR_PUCRA_PA10

GPIO port I/O pin 10

Definition at line 230 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_11 PWR_PUCRA_PA11

GPIO port I/O pin 11

Definition at line 231 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_12 PWR_PUCRA_PA12

GPIO port I/O pin 12

Definition at line 232 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_13 PWR_PUCRA_PA13

GPIO port I/O pin 14

Definition at line 233 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_14 PWR_PDCRC_PC14

GPIO port I/O pin 14

Definition at line 234 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_15 PWR_PUCRC_PC15

GPIO port I/O pin 15

Definition at line 235 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_2 PWR_PUCRA_PA2

GPIO port I/O pin 2

Definition at line 222 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_3 PWR_PUCRA_PA3

GPIO port I/O pin 3

Definition at line 223 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_4 PWR_PUCRA_PA4

GPIO port I/O pin 4

Definition at line 224 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_5 PWR_PUCRA_PA5

GPIO port I/O pin 5

Definition at line 225 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_6 PWR_PUCRA_PA6

GPIO port I/O pin 6

Definition at line 226 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_7 PWR_PUCRA_PA7

GPIO port I/O pin 7

Definition at line 227 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_8 PWR_PUCRA_PA8

GPIO port I/O pin 8

Definition at line 228 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_GPIO_BIT_9 PWR_PUCRA_PA9

GPIO port I/O pin 9

Definition at line 229 of file stm32wbxx_hal_pwr_ex.h.

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STM32WB55xx HAL User Manual: GPIO port

Defines
GPIO port
PWR Extended Exported Constants

Defines

#define | PWR_GPIO_A 0x00000000U
#define | PWR_GPIO_B 0x00000001U
#define | PWR_GPIO_C 0x00000002U
#define | PWR_GPIO_D 0x00000003U
#define | PWR_GPIO_E 0x00000004U
#define | PWR_GPIO_H 0x00000007U

Define Documentation

#define PWR_GPIO_A 0x00000000U

GPIO port A

Definition at line 243 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define PWR_GPIO_B 0x00000001U

GPIO port B

Definition at line 244 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define PWR_GPIO_C 0x00000002U

GPIO port C

Definition at line 245 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define PWR_GPIO_D 0x00000003U

GPIO port D

Definition at line 247 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define PWR_GPIO_E 0x00000004U

GPIO port E

Definition at line 249 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define PWR_GPIO_H 0x00000007U

GPIO port H

Definition at line 250 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

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STM32WB55xx HAL User Manual: BOR configuration

Defines
BOR configuration
PWR Extended Exported Constants

Defines

#define | PWR_BOR_SYSTEM_RESET (LL_PWR_BOR_SYSTEM_RESET)
#define | PWR_BOR_SMPS_FORCE_BYPASS (LL_PWR_BOR_SMPS_FORCE_BYPASS)

Define Documentation

#define PWR_BOR_SMPS_FORCE_BYPASS (LL_PWR_BOR_SMPS_FORCE_BYPASS)

BOR will for SMPS step down converter in bypass mode

Definition at line 260 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_BOR_SYSTEM_RESET (LL_PWR_BOR_SYSTEM_RESET)

BOR will generate a system reset

Definition at line 259 of file stm32wbxx_hal_pwr_ex.h.

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STM32WB55xx HAL User Manual: SMPS step down converter operating modes

Defines
SMPS step down converter operating modes
PWR Extended Exported Constants

Defines

#define | PWR_SMPS_BYPASS (PWR_SR2_SMPSBF)
#define | PWR_SMPS_STEP_DOWN (PWR_SR2_SMPSF)

Define Documentation

#define PWR_SMPS_BYPASS (PWR_SR2_SMPSBF)

SMPS step down in bypass mode

Definition at line 274 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_SMPS_STEP_DOWN (PWR_SR2_SMPSF)

SMPS step down in step down mode if system low power mode is run, LP run or stop0. If system low power mode is stop1, stop2, standby, shutdown, then SMPS is forced in mode open to preserve energy stored in decoupling capacitor as long as possible.

Definition at line 275 of file stm32wbxx_hal_pwr_ex.h.

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STM32WB55xx HAL User Manual: SMPS step down converter supply startup current selection

Defines
SMPS step down converter supply startup current selection
PWR Extended Exported Constants

Defines

#define | PWR_SMPS_STARTUP_CURRENT_80MA (0x00000000U)
#define | PWR_SMPS_STARTUP_CURRENT_100MA ( PWR_CR5_SMPSSC_0)
#define | PWR_SMPS_STARTUP_CURRENT_120MA ( PWR_CR5_SMPSSC_1 )
#define | PWR_SMPS_STARTUP_CURRENT_140MA ( PWR_CR5_SMPSSC_1 | PWR_CR5_SMPSSC_0)
#define | PWR_SMPS_STARTUP_CURRENT_160MA (PWR_CR5_SMPSSC_2 )
#define | PWR_SMPS_STARTUP_CURRENT_180MA (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_0)
#define | PWR_SMPS_STARTUP_CURRENT_200MA (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_1 )
#define | PWR_SMPS_STARTUP_CURRENT_220MA (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_1 | PWR_CR5_SMPSSC_0)

Define Documentation

#define PWR_SMPS_STARTUP_CURRENT_100MA ( PWR_CR5_SMPSSC_0)

SMPS step down converter supply startup current 100mA

Definition at line 284 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_SMPS_STARTUP_CURRENT_120MA ( PWR_CR5_SMPSSC_1 )

SMPS step down converter supply startup current 120mA

Definition at line 285 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_SMPS_STARTUP_CURRENT_140MA ( PWR_CR5_SMPSSC_1 | PWR_CR5_SMPSSC_0)

SMPS step down converter supply startup current 140mA

Definition at line 286 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_SMPS_STARTUP_CURRENT_160MA (PWR_CR5_SMPSSC_2 )

SMPS step down converter supply startup current 160mA

Definition at line 287 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_SMPS_STARTUP_CURRENT_180MA (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_0)

SMPS step down converter supply startup current 180mA

Definition at line 288 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_SMPS_STARTUP_CURRENT_200MA (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_1 )

SMPS step down converter supply startup current 200mA

Definition at line 289 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_SMPS_STARTUP_CURRENT_220MA (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_1 | PWR_CR5_SMPSSC_0)

SMPS step down converter supply startup current 220mA

Definition at line 290 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_SMPS_STARTUP_CURRENT_80MA (0x00000000U)

SMPS step down converter supply startup current 80mA

Definition at line 283 of file stm32wbxx_hal_pwr_ex.h.

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STM32WB55xx HAL User Manual: SMPS step down converter output voltage scaling voltage level

Defines
SMPS step down converter output voltage scaling voltage level
PWR Extended Exported Constants

Defines

#define | PWR_SMPS_OUTPUT_VOLTAGE_1V20 (0x00000000U)
#define | PWR_SMPS_OUTPUT_VOLTAGE_1V25 ( PWR_CR5_SMPSVOS_0)
#define | PWR_SMPS_OUTPUT_VOLTAGE_1V30 ( PWR_CR5_SMPSVOS_1 )
#define | PWR_SMPS_OUTPUT_VOLTAGE_1V35 ( PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0)
#define | PWR_SMPS_OUTPUT_VOLTAGE_1V40 ( PWR_CR5_SMPSVOS_2 )
#define | PWR_SMPS_OUTPUT_VOLTAGE_1V45 ( PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_0)
#define | PWR_SMPS_OUTPUT_VOLTAGE_1V50 ( PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1 )
#define | PWR_SMPS_OUTPUT_VOLTAGE_1V55 ( PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0)
#define | PWR_SMPS_OUTPUT_VOLTAGE_1V60 (PWR_CR5_SMPSVOS_3 )
#define | PWR_SMPS_OUTPUT_VOLTAGE_1V65 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_0)
#define | PWR_SMPS_OUTPUT_VOLTAGE_1V70 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_1 )
#define | PWR_SMPS_OUTPUT_VOLTAGE_1V75 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0)
#define | PWR_SMPS_OUTPUT_VOLTAGE_1V80 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 )
#define | PWR_SMPS_OUTPUT_VOLTAGE_1V85 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_0)
#define | PWR_SMPS_OUTPUT_VOLTAGE_1V90 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1 )

Define Documentation

#define PWR_SMPS_OUTPUT_VOLTAGE_1V20 (0x00000000U)

SMPS step down converter supply output voltage 1.20V

Definition at line 300 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_SMPS_OUTPUT_VOLTAGE_1V25 ( PWR_CR5_SMPSVOS_0)

SMPS step down converter supply output voltage 1.25V

Definition at line 301 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_SMPS_OUTPUT_VOLTAGE_1V30 ( PWR_CR5_SMPSVOS_1 )

SMPS step down converter supply output voltage 1.30V

Definition at line 302 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_SMPS_OUTPUT_VOLTAGE_1V35 ( PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0)

SMPS step down converter supply output voltage 1.35V

Definition at line 303 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_SMPS_OUTPUT_VOLTAGE_1V40 ( PWR_CR5_SMPSVOS_2 )

SMPS step down converter supply output voltage 1.40V

Definition at line 304 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_SMPS_OUTPUT_VOLTAGE_1V45 ( PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_0)

SMPS step down converter supply output voltage 1.45V

Definition at line 305 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_SMPS_OUTPUT_VOLTAGE_1V50 ( PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1 )

SMPS step down converter supply output voltage 1.50V

Definition at line 306 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_SMPS_OUTPUT_VOLTAGE_1V55 ( PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0)

SMPS step down converter supply output voltage 1.55V

Definition at line 307 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_SMPS_OUTPUT_VOLTAGE_1V60 (PWR_CR5_SMPSVOS_3 )

SMPS step down converter supply output voltage 1.60V

Definition at line 308 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_SMPS_OUTPUT_VOLTAGE_1V65 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_0)

SMPS step down converter supply output voltage 1.65V

Definition at line 309 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_SMPS_OUTPUT_VOLTAGE_1V70 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_1 )

SMPS step down converter supply output voltage 1.70V

Definition at line 310 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_SMPS_OUTPUT_VOLTAGE_1V75 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0)

SMPS step down converter supply output voltage 1.75V

Definition at line 311 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_SMPS_OUTPUT_VOLTAGE_1V80 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 )

SMPS step down converter supply output voltage 1.80V

Definition at line 312 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_SMPS_OUTPUT_VOLTAGE_1V85 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_0)

SMPS step down converter supply output voltage 1.85V

Definition at line 313 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_SMPS_OUTPUT_VOLTAGE_1V90 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1 )

SMPS step down converter supply output voltage 1.90V

Definition at line 314 of file stm32wbxx_hal_pwr_ex.h.

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STM32WB55xx HAL User Manual: PWR Status Flags

Defines
PWR Status Flags
PWR Extended Exported Constants

Elements values convention: 0000 0000 0XXY YYYYb. More...

Defines

#define | PWR_FLAG_WUF1 (0x0020U)
#define | PWR_FLAG_WUF2 (0x0021U)
#define | PWR_FLAG_WUF3 (0x0022U)
#define | PWR_FLAG_WUF4 (0x0023U)
#define | PWR_FLAG_WUF5 (0x0024U)
#define | PWR_FLAG_WU PWR_SR1_WUF
#define | PWR_FLAG_FRCBYPI (0x0027U)
#define | PWR_FLAG_BHWF (0x0029U)
#define | PWR_FLAG_RFPHASEI (0x002BU)
#define | PWR_FLAG_BLEACTI (0x002CU)
#define | PWR_FLAG_802ACTI (0x002DU)
#define | PWR_FLAG_HOLDC2I (0x002EU)
#define | PWR_FLAG_WUFI (0x002FU)
#define | PWR_FLAG_SMPSRDYF (0x0040U)
#define | PWR_FLAG_SMPSBYPF (0x0041U)
#define | PWR_FLAG_REGLPS (0x0048U)
#define | PWR_FLAG_REGLPF (0x0049U)
#define | PWR_FLAG_VOSF (0x004AU)
#define | PWR_FLAG_PVDO (0x004BU)
#define | PWR_FLAG_PVMO1 (0x004CU)
#define | PWR_FLAG_PVMO3 (0x004EU)
#define | PWR_FLAG_SB (0x0068U)
#define | PWR_FLAG_STOP (0x0069U)
#define | PWR_FLAG_C2SB (0x006AU)
#define | PWR_FLAG_C2STOP (0x006BU)
#define | PWR_FLAG_CRITICAL_RF_PHASE (0x006DU)
#define | PWR_FLAG_C1DEEPSLEEP (0x006EU)
#define | PWR_FLAG_C2DEEPSLEEP (0x006FU)

Detailed Description

Elements values convention: 0000 0000 0XXY YYYYb.

  • Y YYYY : Flag position in the XX register (5 bits)
  • XX : Status register (2 bits)
    • 01: SR1 register
    • 10: SR2 register
    • 11: C2_SCR register The only exception is PWR_FLAG_WUF, encompassing all wake-up flags and set to PWR_SR1_WUF.

Define Documentation

#define PWR_FLAG_802ACTI (0x002DU)

802.15.4 Activity Interrupt Flag

Definition at line 351 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_FLAG_BHWF (0x0029U)

BLE_Host WakeUp Flag

Definition at line 348 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_FLAG_BLEACTI (0x002CU)

BLE Activity Interrupt Flag

Definition at line 350 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_FLAG_C1DEEPSLEEP (0x006EU)

CPU1 DeepSleep Flag

Definition at line 380 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_FLAG_C2DEEPSLEEP (0x006FU)

CPU2 DeepSleep Flag

Definition at line 381 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_FLAG_C2SB (0x006AU)

System Standby flag for CPU2

Definition at line 376 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_FLAG_C2STOP (0x006BU)

System Stop flag for CPU2

Definition at line 377 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_FLAG_CRITICAL_RF_PHASE (0x006DU)

Critical radio system phase flag

Definition at line 379 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_FLAG_FRCBYPI (0x0027U)

SMPS Forced in Bypass Interrupt Flag

Definition at line 346 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_FLAG_HOLDC2I (0x002EU)

CPU2 on-Hold Interrupt Flag

Definition at line 352 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_FLAG_PVDO (0x004BU)

Power Voltage Detector output flag

Definition at line 367 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_FLAG_PVMO1 (0x004CU)

Power Voltage Monitoring 1 output flag

Definition at line 369 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_FLAG_PVMO3 (0x004EU)

Power Voltage Monitoring 3 output flag

Definition at line 370 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_FLAG_REGLPF (0x0049U)

Low-power regulator flag

Definition at line 362 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_FLAG_REGLPS (0x0048U)

Low-power regulator start flag

Definition at line 361 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_FLAG_RFPHASEI (0x002BU)

Radio Phase Interrupt Flag

Definition at line 349 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_FLAG_SB (0x0068U)

System Standby flag for CPU1

Definition at line 373 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_FLAG_SMPSBYPF (0x0041U)

SMPS Bypass Flag

Definition at line 358 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_FLAG_SMPSRDYF (0x0040U)

SMPS Ready Flag

Definition at line 357 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_FLAG_STOP (0x0069U)

System Stop flag for CPU1

Definition at line 374 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_FLAG_VOSF (0x004AU)

Voltage scaling flag

Definition at line 365 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_FLAG_WU PWR_SR1_WUF

Encompass wakeup event on all wakeup pins

Definition at line 343 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_FLAG_WUF1 (0x0020U)

Wakeup event on wakeup pin 1

Definition at line 332 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_FLAG_WUF2 (0x0021U)

Wakeup event on wakeup pin 2

Definition at line 334 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_FLAG_WUF3 (0x0022U)

Wakeup event on wakeup pin 3

Definition at line 337 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_FLAG_WUF4 (0x0023U)

Wakeup event on wakeup pin 4

Definition at line 339 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_FLAG_WUF5 (0x0024U)

Wakeup event on wakeup pin 5

Definition at line 341 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_FLAG_WUFI (0x002FU)

Wakeup on internal wakeup line

Definition at line 353 of file stm32wbxx_hal_pwr_ex.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PWR Wakeup Target Definition

Defines
PWR Wakeup Target Definition
PWR Extended Exported Constants

Defines

#define | PWR_WAKEUPTARGET_CPU1 (0x00000001U)
#define | PWR_WAKEUPTARGET_CPU2 (0x00000002U)
#define | PWR_WAKEUPTARGET_ALL_CPU (PWR_WAKEUPTARGET_CPU1 | PWR_WAKEUPTARGET_CPU2)
#define | PWR_WAKEUPTARGET_RF (0x00000004U)

Define Documentation

#define PWR_WAKEUPTARGET_ALL_CPU (PWR_WAKEUPTARGET_CPU1 | PWR_WAKEUPTARGET_CPU2)

Definition at line 391 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_WAKEUPTARGET_CPU1 (0x00000001U)

Definition at line 389 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_WAKEUPTARGET_CPU2 (0x00000002U)

Definition at line 390 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_WAKEUPTARGET_RF (0x00000004U)

Definition at line 392 of file stm32wbxx_hal_pwr_ex.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PWREx Core definition

Defines
PWREx Core definition
PWR Extended Exported Constants

Defines

#define | PWR_CORE_CPU1 (0x00000000U)
#define | PWR_CORE_CPU2 (0x00000001U)

Define Documentation

#define PWR_CORE_CPU1 (0x00000000U)

Definition at line 400 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_CORE_CPU2 (0x00000001U)

Definition at line 401 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_EnableWakeUpPin().

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PWR Extended Exported Constants

Modules | Defines
PWR Extended Exported Constants
PWREx

Modules

Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants
PWR wake-up pins
PWREx Pin Polarity configuration
Peripheral Voltage Monitoring type
PWR PVM interrupt and event mode
Flash Power Down modes
PWR Regulator voltage scale
PWR battery charging resistor selection
PWR battery charging
GPIO bit number for I/O setting in standby/shutdown mode
GPIO port
BOR configuration
SMPS step down converter operating modes
SMPS step down converter supply startup current selection
SMPS step down converter output voltage scaling voltage level
PWR Status Flags

Elements values convention: 0000 0000 0XXY YYYYb.

PWR Wakeup Target Definition
PWREx Core definition

Defines

#define | PWR_WAKEUP_PIN1 PWR_CR3_EWUP1
#define | PWR_WAKEUP_PIN2 PWR_CR3_EWUP2
#define | PWR_WAKEUP_PIN3 PWR_CR3_EWUP3
#define | PWR_WAKEUP_PIN4 PWR_CR3_EWUP4
#define | PWR_WAKEUP_PIN5 PWR_CR3_EWUP5

Define Documentation

#define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1

Wakeup pin 1 (with high level polarity)

Definition at line 128 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2

Wakeup pin 2 (with high level polarity)

Definition at line 130 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3

Wakeup pin 3 (with high level polarity)

Definition at line 133 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4

Wakeup pin 4 (with high level polarity)

Definition at line 135 of file stm32wbxx_hal_pwr_ex.h.

#define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5

Wakeup pin 5 (with high level polarity)

Definition at line 137 of file stm32wbxx_hal_pwr_ex.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PWR Extended Exported Macros

Defines
PWR Extended Exported Macros
PWREx

Defines

#define | __HAL_PWR_PVM1_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(PWR_EXTI_LINE_PVM1)
Enable the PVM1 Extended Interrupt C1 Line.
#define | __HAL_PWR_PVM1_EXTIC2_ENABLE_IT() LL_C2_EXTI_EnableIT_0_31(PWR_EXTI_LINE_PVM1)
Enable the PVM1 Extended Interrupt C2 Line.
#define | __HAL_PWR_PVM1_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(PWR_EXTI_LINE_PVM1)
Disable the PVM1 Extended Interrupt C1 Line.
#define | __HAL_PWR_PVM1_EXTIC2_DISABLE_IT() LL_C2_EXTI_DisableIT_0_31(PWR_EXTI_LINE_PVM1)
Disable the PVM1 Extended Interrupt C2 Line.
#define | __HAL_PWR_PVM1_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(PWR_EXTI_LINE_PVM1)
Enable the PVM1 Event C1 Line.
#define | __HAL_PWR_PVM1_EXTIC2_ENABLE_EVENT() LL_C2_EXTI_EnableEvent_0_31(PWR_EXTI_LINE_PVM1)
Enable the PVM1 Event C2 Line.
#define | __HAL_PWR_PVM1_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(PWR_EXTI_LINE_PVM1)
Disable the PVM1 Event C1 Line.
#define | __HAL_PWR_PVM1_EXTIC2_DISABLE_EVENT() LL_C2_EXTI_DisableEvent_0_31(PWR_EXTI_LINE_PVM1)
Disable the PVM1 Event C2 Line.
#define | __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(PWR_EXTI_LINE_PVM1)
Enable the PVM1 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(PWR_EXTI_LINE_PVM1)
Disable the PVM1 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(PWR_EXTI_LINE_PVM1)
Enable the PVM1 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(PWR_EXTI_LINE_PVM1)
Disable the PVM1 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE()
PVM1 EXTI line configuration: set rising & falling edge trigger.
#define | __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the PVM1 Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(PWR_EXTI_LINE_PVM1)
Generate a Software interrupt on selected EXTI line.
#define | __HAL_PWR_PVM1_EXTI_GET_FLAG() LL_EXTI_ReadFlag_0_31(PWR_EXTI_LINE_PVM1)
Check whether the specified PVM1 EXTI interrupt flag is set or not.
#define | __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(PWR_EXTI_LINE_PVM1)
Clear the PVM1 EXTI flag.
#define | __HAL_PWR_PVM3_EXTI_ENABLE_IT() LL_EXTI_EnableIT_32_63(PWR_EXTI_LINE_PVM3)
Enable the PVM3 Extended Interrupt C1 Line.
#define | __HAL_PWR_PVM3_EXTIC2_ENABLE_IT() LL_C2_EXTI_EnableIT_32_63(PWR_EXTI_LINE_PVM3)
Enable the PVM3 Extended Interrupt C2 Line.
#define | __HAL_PWR_PVM3_EXTI_DISABLE_IT() LL_EXTI_DisableIT_32_63(PWR_EXTI_LINE_PVM3)
Disable the PVM3 Extended Interrupt C1 Line.
#define | __HAL_PWR_PVM3_EXTIC2_DISABLE_IT() LL_C2_EXTI_DisableIT_32_63(PWR_EXTI_LINE_PVM3)
Disable the PVM3 Extended Interrupt C2 Line.
#define | __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_32_63(PWR_EXTI_LINE_PVM3)
Enable the PVM3 Event C1 Line.
#define | __HAL_PWR_PVM3_EXTIC2_ENABLE_EVENT() LL_C2_EXTI_EnableEvent_32_63(PWR_EXTI_LINE_PVM3)
Enable the PVM3 Event C2 Line.
#define | __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_32_63(PWR_EXTI_LINE_PVM3)
Disable the PVM3 Event C1 Line.
#define | __HAL_PWR_PVM3_EXTIC2_DISABLE_EVENT() LL_C2_EXTI_DisableEvent_32_63(PWR_EXTI_LINE_PVM3)
Disable the PVM3 Event C2 Line.
#define | __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_32_63(PWR_EXTI_LINE_PVM3)
Enable the PVM3 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_32_63(PWR_EXTI_LINE_PVM3)
Disable the PVM3 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_32_63(PWR_EXTI_LINE_PVM3)
Enable the PVM3 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_32_63(PWR_EXTI_LINE_PVM3)
Disable the PVM3 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE()
PVM3 EXTI line configuration: set rising & falling edge trigger.
#define | __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the PVM3 Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_32_63(PWR_EXTI_LINE_PVM3)
Generate a Software interrupt on selected EXTI line.
#define | __HAL_PWR_PVM3_EXTI_GET_FLAG() LL_EXTI_ReadFlag_32_63(PWR_EXTI_LINE_PVM3)
Check whether the specified PVM3 EXTI interrupt flag is set or not.
#define | __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_32_63(PWR_EXTI_LINE_PVM3)
Clear the PVM3 EXTI flag.
#define | __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__)
Configure the main internal regulator output voltage.
#define | __HAL_C2_PWR_WAKEUP_BLE() LL_C2_PWR_WakeUp_BLE()
Wakeup BLE controller from its sleep mode.
#define | __HAL_C2_PWR_WAKEUP_802_15_4() LL_C2_PWR_WakeUp_802_15_4()
Wakeup 802.15.4 controller from its sleep mode.

Define Documentation

#define __HAL_C2_PWR_WAKEUP_802_15_4 ( ) LL_C2_PWR_WakeUp_802_15_4()

Wakeup 802.15.4 controller from its sleep mode.

Note:
This bit is automatically reset when 802.15.4 controller exit its sleep mode.
Return values:
None

Definition at line 729 of file stm32wbxx_hal_pwr_ex.h.

#define __HAL_C2_PWR_WAKEUP_BLE ( ) LL_C2_PWR_WakeUp_BLE()

Wakeup BLE controller from its sleep mode.

Note:
This bit is automatically reset when 802.15.4 controller exit its sleep mode.
Return values:
None

Definition at line 721 of file stm32wbxx_hal_pwr_ex.h.

#define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG ( ) LL_EXTI_ClearFlag_0_31(PWR_EXTI_LINE_PVM1)

Clear the PVM1 EXTI flag.

Return values:
None

Definition at line 566 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

#define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT ( ) LL_EXTI_DisableEvent_0_31(PWR_EXTI_LINE_PVM1)

Disable the PVM1 Event C1 Line.

Return values:
None

Definition at line 489 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE ( ) LL_EXTI_DisableFallingTrig_0_31(PWR_EXTI_LINE_PVM1)

Disable the PVM1 Extended Interrupt Falling Trigger.

Note:
PVM1 flag polarity is inverted compared to EXTI line, therefore EXTI rising and falling logic edges are inverted versus PVM1 voltage edges.
Return values:
None

Definition at line 528 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM1_EXTI_DISABLE_IT ( ) LL_EXTI_DisableIT_0_31(PWR_EXTI_LINE_PVM1)

Disable the PVM1 Extended Interrupt C1 Line.

Return values:
None

Definition at line 465 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE ( ) LL_EXTI_DisableRisingTrig_0_31(PWR_EXTI_LINE_PVM1)

Disable the PVM1 Extended Interrupt Rising Trigger.

Note:
PVM1 flag polarity is inverted compared to EXTI line, therefore EXTI rising and falling logic edges are inverted versus PVM1 voltage edges.
Return values:
None

Definition at line 511 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                     \
    __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE();             \
    __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE();            \
  } while(0)

Disable the PVM1 Extended Interrupt Rising & Falling Trigger.

Return values:
None

Definition at line 544 of file stm32wbxx_hal_pwr_ex.h.

#define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT ( ) LL_EXTI_EnableEvent_0_31(PWR_EXTI_LINE_PVM1)

Enable the PVM1 Event C1 Line.

Return values:
None

Definition at line 477 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE ( ) LL_EXTI_EnableFallingTrig_0_31(PWR_EXTI_LINE_PVM1)

Enable the PVM1 Extended Interrupt Falling Trigger.

Note:
PVM1 flag polarity is inverted compared to EXTI line, therefore EXTI rising and falling logic edges are inverted versus PVM1 voltage edges.
Return values:
None

Definition at line 519 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM1_EXTI_ENABLE_IT ( ) LL_EXTI_EnableIT_0_31(PWR_EXTI_LINE_PVM1)

Enable the PVM1 Extended Interrupt C1 Line.

Return values:
None

Definition at line 453 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE ( ) LL_EXTI_EnableRisingTrig_0_31(PWR_EXTI_LINE_PVM1)

Enable the PVM1 Extended Interrupt Rising Trigger.

Note:
PVM1 flag polarity is inverted compared to EXTI line, therefore EXTI rising and falling logic edges are inverted versus PVM1 voltage edges.
Return values:
None

Definition at line 503 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                    \
    __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE();             \
    __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();            \
  } while(0)

PVM1 EXTI line configuration: set rising & falling edge trigger.

Return values:
None

Definition at line 534 of file stm32wbxx_hal_pwr_ex.h.

#define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT ( ) LL_EXTI_GenerateSWI_0_31(PWR_EXTI_LINE_PVM1)

Generate a Software interrupt on selected EXTI line.

Return values:
None

Definition at line 554 of file stm32wbxx_hal_pwr_ex.h.

#define __HAL_PWR_PVM1_EXTI_GET_FLAG ( ) LL_EXTI_ReadFlag_0_31(PWR_EXTI_LINE_PVM1)

Check whether the specified PVM1 EXTI interrupt flag is set or not.

Return values:
EXTI PVM1 Line Status.

Definition at line 560 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

#define __HAL_PWR_PVM1_EXTIC2_DISABLE_EVENT ( ) LL_C2_EXTI_DisableEvent_0_31(PWR_EXTI_LINE_PVM1)

Disable the PVM1 Event C2 Line.

Return values:
None

Definition at line 495 of file stm32wbxx_hal_pwr_ex.h.

#define __HAL_PWR_PVM1_EXTIC2_DISABLE_IT ( ) LL_C2_EXTI_DisableIT_0_31(PWR_EXTI_LINE_PVM1)

Disable the PVM1 Extended Interrupt C2 Line.

Return values:
None

Definition at line 471 of file stm32wbxx_hal_pwr_ex.h.

#define __HAL_PWR_PVM1_EXTIC2_ENABLE_EVENT ( ) LL_C2_EXTI_EnableEvent_0_31(PWR_EXTI_LINE_PVM1)

Enable the PVM1 Event C2 Line.

Return values:
None

Definition at line 483 of file stm32wbxx_hal_pwr_ex.h.

#define __HAL_PWR_PVM1_EXTIC2_ENABLE_IT ( ) LL_C2_EXTI_EnableIT_0_31(PWR_EXTI_LINE_PVM1)

Enable the PVM1 Extended Interrupt C2 Line.

Return values:
None

Definition at line 459 of file stm32wbxx_hal_pwr_ex.h.

#define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG ( ) LL_EXTI_ClearFlag_32_63(PWR_EXTI_LINE_PVM3)

Clear the PVM3 EXTI flag.

Return values:
None

Definition at line 687 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

#define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT ( ) LL_EXTI_DisableEvent_32_63(PWR_EXTI_LINE_PVM3)

Disable the PVM3 Event C1 Line.

Return values:
None

Definition at line 610 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE ( ) LL_EXTI_DisableFallingTrig_32_63(PWR_EXTI_LINE_PVM3)

Disable the PVM3 Extended Interrupt Falling Trigger.

Note:
PVM3 flag polarity is inverted compared to EXTI line, therefore EXTI rising and falling logic edges are inverted versus PVM3 voltage edges.
Return values:
None

Definition at line 649 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM3_EXTI_DISABLE_IT ( ) LL_EXTI_DisableIT_32_63(PWR_EXTI_LINE_PVM3)

Disable the PVM3 Extended Interrupt C1 Line.

Return values:
None

Definition at line 586 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE ( ) LL_EXTI_DisableRisingTrig_32_63(PWR_EXTI_LINE_PVM3)

Disable the PVM3 Extended Interrupt Rising Trigger.

Note:
PVM3 flag polarity is inverted compared to EXTI line, therefore EXTI rising and falling logic edges are inverted versus PVM3 voltage edges.
Return values:
None

Definition at line 632 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                     \
    __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();             \
    __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE();            \
  } while(0)

Disable the PVM3 Extended Interrupt Rising & Falling Trigger.

Return values:
None

Definition at line 665 of file stm32wbxx_hal_pwr_ex.h.

#define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT ( ) LL_EXTI_EnableEvent_32_63(PWR_EXTI_LINE_PVM3)

Enable the PVM3 Event C1 Line.

Return values:
None

Definition at line 598 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE ( ) LL_EXTI_EnableFallingTrig_32_63(PWR_EXTI_LINE_PVM3)

Enable the PVM3 Extended Interrupt Falling Trigger.

Note:
PVM3 flag polarity is inverted compared to EXTI line, therefore EXTI rising and falling logic edges are inverted versus PVM3 voltage edges.
Return values:
None

Definition at line 640 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM3_EXTI_ENABLE_IT ( ) LL_EXTI_EnableIT_32_63(PWR_EXTI_LINE_PVM3)

Enable the PVM3 Extended Interrupt C1 Line.

Return values:
None

Definition at line 574 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE ( ) LL_EXTI_EnableRisingTrig_32_63(PWR_EXTI_LINE_PVM3)

Enable the PVM3 Extended Interrupt Rising Trigger.

Note:
PVM3 flag polarity is inverted compared to EXTI line, therefore EXTI rising and falling logic edges are inverted versus PVM3 voltage edges.
Return values:
None

Definition at line 624 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                    \
    __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();             \
    __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();            \
  } while(0)

PVM3 EXTI line configuration: set rising & falling edge trigger.

Return values:
None

Definition at line 655 of file stm32wbxx_hal_pwr_ex.h.

#define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT ( ) LL_EXTI_GenerateSWI_32_63(PWR_EXTI_LINE_PVM3)

Generate a Software interrupt on selected EXTI line.

Return values:
None

Definition at line 675 of file stm32wbxx_hal_pwr_ex.h.

#define __HAL_PWR_PVM3_EXTI_GET_FLAG ( ) LL_EXTI_ReadFlag_32_63(PWR_EXTI_LINE_PVM3)

Check whether the specified PVM3 EXTI interrupt flag is set or not.

Return values:
EXTI PVM3 Line Status.

Definition at line 681 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

#define __HAL_PWR_PVM3_EXTIC2_DISABLE_EVENT ( ) LL_C2_EXTI_DisableEvent_32_63(PWR_EXTI_LINE_PVM3)

Disable the PVM3 Event C2 Line.

Return values:
None

Definition at line 616 of file stm32wbxx_hal_pwr_ex.h.

#define __HAL_PWR_PVM3_EXTIC2_DISABLE_IT ( ) LL_C2_EXTI_DisableIT_32_63(PWR_EXTI_LINE_PVM3)

Disable the PVM3 Extended Interrupt C2 Line.

Return values:
None

Definition at line 592 of file stm32wbxx_hal_pwr_ex.h.

#define __HAL_PWR_PVM3_EXTIC2_ENABLE_EVENT ( ) LL_C2_EXTI_EnableEvent_32_63(PWR_EXTI_LINE_PVM3)

Enable the PVM3 Event C2 Line.

Return values:
None

Definition at line 604 of file stm32wbxx_hal_pwr_ex.h.

#define __HAL_PWR_PVM3_EXTIC2_ENABLE_IT ( ) LL_C2_EXTI_EnableIT_32_63(PWR_EXTI_LINE_PVM3)

Enable the PVM3 Extended Interrupt C2 Line.

Return values:
None

Definition at line 580 of file stm32wbxx_hal_pwr_ex.h.

#define __HAL_PWR_VOLTAGESCALING_CONFIG ( __REGULATOR__ )
Value:
do {                                                     \
                                                            __IO uint32_t tmpreg;                               \
                                                            MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \
                                                            /* Delay after an RCC peripheral clock enabling */  \
                                                            tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS);           \
                                                            UNUSED(tmpreg);                                     \
                                                          } while(0)

Configure the main internal regulator output voltage.

Parameters:
__REGULATOR__ specifies the regulator output voltage to achieve a tradeoff between performance and power consumption. This parameter can be one of the following values:
  • PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, typical output voltage at 1.2 V, system frequency up to 64 MHz.
  • PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode, typical output voltage at 1.0 V, system frequency up to 16 MHz.
Note:
This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check whether or not VOSF flag is cleared when moving from range 2 to range 1. User may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting.
Return values:
None

Definition at line 706 of file stm32wbxx_hal_pwr_ex.h.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Extended Peripheral Control functions

Functions
Extended Peripheral Control functions
PWR Extended Exported Functions

Extended Peripheral Control functions. More...

Functions

uint32_t | HAL_PWREx_GetVoltageRange (void)
Return Voltage Scaling Range.
HAL_StatusTypeDef | HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling)
Configure the main internal regulator output voltage.
void | HAL_PWREx_EnableBatteryCharging (uint32_t ResistorSelection)
Enable battery charging.
void | HAL_PWREx_DisableBatteryCharging (void)
Disable battery charging.
void | HAL_PWREx_EnableVddUSB (void)
Enable VDDUSB supply.
void | HAL_PWREx_DisableVddUSB (void)
Disable VDDUSB supply.
void | HAL_PWREx_EnableInternalWakeUpLine (void)
Enable Internal Wake-up Line.
void | HAL_PWREx_DisableInternalWakeUpLine (void)
Disable Internal Wake-up Line.
void | HAL_PWREx_EnableBORH_SMPSBypassIT (void)
Enable BORH and SMPS step down converter forced in bypass mode interrupt for CPU1.
void | HAL_PWREx_DisableBORH_SMPSBypassIT (void)
Disable BORH and SMPS step down converter forced in bypass mode interrupt for CPU1.
void | HAL_PWREx_EnableRFPhaseIT (void)
Enable RF Phase interrupt.
void | HAL_PWREx_DisableRFPhaseIT (void)
Disable RF Phase interrupt.
void | HAL_PWREx_EnableBLEActivityIT (void)
Enable BLE Activity interrupt.
void | HAL_PWREx_DisableBLEActivityIT (void)
Disable BLE Activity interrupt.
void | HAL_PWREx_Enable802ActivityIT (void)
Enable 802.15.4 Activity interrupt.
void | HAL_PWREx_Disable802ActivityIT (void)
Disable 802.15.4 Activity interrupt.
void | HAL_PWREx_EnableHOLDC2IT (void)
Enable CPU2 on-Hold interrupt.
void | HAL_PWREx_DisableHOLDC2IT (void)
Disable CPU2 on-Hold interrupt.
HAL_StatusTypeDef | HAL_PWREx_EnableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-up state in Standby and Shutdown modes.
HAL_StatusTypeDef | HAL_PWREx_DisableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-up state in Standby mode and Shutdown modes.
HAL_StatusTypeDef | HAL_PWREx_EnableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-down state in Standby and Shutdown modes.
HAL_StatusTypeDef | HAL_PWREx_DisableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-down state in Standby and Shutdown modes.
void | HAL_PWREx_EnablePullUpPullDownConfig (void)
Enable pull-up and pull-down configuration.
void | HAL_PWREx_DisablePullUpPullDownConfig (void)
Disable pull-up and pull-down configuration.
void | HAL_PWREx_SetBORConfig (uint32_t BORConfiguration)
Set BOR configuration.
uint32_t | HAL_PWREx_GetBORConfig (void)
Get BOR configuration.
void | HAL_PWREx_HoldCore (uint32_t CPU)
Hold the CPU and their allocated peripherals after reset or wakeup from stop or standby.
void | HAL_PWREx_ReleaseCore (uint32_t CPU)
Release Cortex CPU2 and allocated peripherals after reset or wakeup from stop or standby.
void | HAL_PWREx_EnableSRAMRetention (void)
Enable BKRAM content retention in Standby mode.
void | HAL_PWREx_DisableSRAMRetention (void)
Disable BKRAM content retention in Standby mode.
void | HAL_PWREx_EnableFlashPowerDown (uint32_t PowerMode)
Enable Flash Power Down.
void | HAL_PWREx_DisableFlashPowerDown (uint32_t PowerMode)
Disable Flash Power Down.
void | HAL_PWREx_EnablePVM1 (void)
Enable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
void | HAL_PWREx_DisablePVM1 (void)
Disable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
void | HAL_PWREx_EnablePVM3 (void)
Enable the Power Voltage Monitoring 3: VDDA versus 1.62V.
void | HAL_PWREx_DisablePVM3 (void)
Disable the Power Voltage Monitoring 3: VDDA versus 1.62V.
HAL_StatusTypeDef | HAL_PWREx_ConfigPVM (PWR_PVMTypeDef *sConfigPVM)
Configure the Peripheral Voltage Monitoring (PVM).
HAL_StatusTypeDef | HAL_PWREx_ConfigSMPS (PWR_SMPSTypeDef *sConfigSMPS)
Configure the SMPS step down converter.
void | HAL_PWREx_SMPS_SetMode (uint32_t OperatingMode)
Set SMPS operating mode.
uint32_t | HAL_PWREx_SMPS_GetEffectiveMode (void)
Get SMPS effective operating mode.
void | HAL_PWREx_EnableWakeUpPin (uint32_t WakeUpPinPolarity, uint32_t wakeupTarget)
Enable the WakeUp PINx functionality.
uint32_t | HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag)
Get the Wake-Up pin flag.
HAL_StatusTypeDef | HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag)
Clear the Wake-Up pin flag.
void | HAL_PWREx_EnableLowPowerRunMode (void)
Enter Low-power Run mode.
HAL_StatusTypeDef | HAL_PWREx_DisableLowPowerRunMode (void)
Exit Low-power Run mode.
void | HAL_PWREx_EnterSTOP0Mode (uint8_t STOPEntry)
Enter Stop 0 mode.
void | HAL_PWREx_EnterSTOP1Mode (uint8_t STOPEntry)
Enter Stop 1 mode.
void | HAL_PWREx_EnterSTOP2Mode (uint8_t STOPEntry)
Enter Stop 2 mode.
void | HAL_PWREx_EnterSHUTDOWNMode (void)
Enter Shutdown mode.
void | HAL_PWREx_PVD_PVM_IRQHandler (void)
This function handles the PWR PVD/PVMx interrupt request.
__weak void | HAL_PWREx_PVM1Callback (void)
PWR PVM1 interrupt callback.
__weak void | HAL_PWREx_PVM3Callback (void)
PWR PVM3 interrupt callback.

Detailed Description

Extended Peripheral Control functions.

 ===============================================================================
              ##### Extended Peripheral Initialization and de-initialization functions #####
 ===============================================================================
    [..]

Function Documentation

HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag ( uint32_t WakeUpFlag )

Clear the Wake-Up pin flag.

Parameters:
WakeUpFlag specifies the Wake-Up PIN flag to clear. This parameter can be one of the following values:
  • PWR_FLAG_WUF1: A wakeup event was received from PA0.
  • PWR_FLAG_WUF2: A wakeup event was received from PC13.
  • PWR_FLAG_WUF3: A wakeup event was received from PC12.
  • PWR_FLAG_WUF4: A wakeup event was received from PA2.
  • PWR_FLAG_WUF5: A wakeup event was received from PC5.
Return values:
HAL status.

Definition at line 1015 of file stm32wbxx_hal_pwr_ex.c.

HAL_StatusTypeDef HAL_PWREx_ConfigPVM ( PWR_PVMTypeDef * sConfigPVM )

Configure the Peripheral Voltage Monitoring (PVM).

Parameters:
sConfigPVM pointer to a PWR_PVMTypeDef structure that contains the PVM configuration information.
Note:
The API configures a single PVM according to the information contained in the input structure. To configure several PVMs, the API must be singly called for each PVM used.
Refer to the electrical characteristics of your device datasheet for more details about the voltage thresholds corresponding to each detection level and to each monitored supply.
Return values:
HAL status

Definition at line 759 of file stm32wbxx_hal_pwr_ex.c.

References __HAL_PWR_PVM1_EXTI_DISABLE_EVENT, __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE, __HAL_PWR_PVM1_EXTI_DISABLE_IT, __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE, __HAL_PWR_PVM1_EXTI_ENABLE_EVENT, __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE, __HAL_PWR_PVM1_EXTI_ENABLE_IT, __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE, __HAL_PWR_PVM3_EXTI_DISABLE_EVENT, __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE, __HAL_PWR_PVM3_EXTI_DISABLE_IT, __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE, __HAL_PWR_PVM3_EXTI_ENABLE_EVENT, __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE, __HAL_PWR_PVM3_EXTI_ENABLE_IT, __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE, assert_param, IS_PWR_PVM_MODE, IS_PWR_PVM_TYPE, PWR_PVMTypeDef::Mode, PVM_FALLING_EDGE, PVM_MODE_EVT, PVM_MODE_IT, PVM_RISING_EDGE, PWR_PVMTypeDef::PVMType, PWR_PVM_1, and PWR_PVM_3.

HAL_StatusTypeDef HAL_PWREx_ConfigSMPS ( PWR_SMPSTypeDef * sConfigSMPS )

Configure the SMPS step down converter.

Note:
SMPS output voltage is calibrated in production, calibration parameters are applied to the voltage level parameter to reach the requested voltage value.
Parameters:
sConfigSMPS pointer to a PWR_SMPSTypeDef structure that contains the SMPS configuration information.
Note:
To set and enable SMPS operating mode, refer to function "HAL_PWREx_SMPS_SetMode()".
Return values:
HAL status

Definition at line 857 of file stm32wbxx_hal_pwr_ex.c.

References assert_param, IS_PWR_SMPS_OUTPUT_VOLTAGE, IS_PWR_SMPS_STARTUP_CURRENT, LL_PWR_SMPS_OUTPUT_VOLTAGE_1V50, PWR_SMPSTypeDef::OutputVoltage, SMPS_VOLTAGE_CAL, SMPS_VOLTAGE_CAL_POS, and PWR_SMPSTypeDef::StartupCurrent.

HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling ( uint32_t VoltageScaling )

Configure the main internal regulator output voltage.

Parameters:
VoltageScaling specifies the regulator output voltage to achieve a tradeoff between performance and power consumption. This parameter can be one of the following values:
  • PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, typical output voltage at 1.2 V, system frequency up to 64 MHz.
  • PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode, typical output voltage at 1.0 V, system frequency up to 16 MHz.
Note:
When moving from Range 1 to Range 2, the system frequency must be decreased to a value below 16 MHz before calling HAL_PWREx_ControlVoltageScaling() API. When moving from Range 2 to Range 1, the system frequency can be increased to a value up to 64 MHz after calling HAL_PWREx_ControlVoltageScaling() API.
When moving from Range 2 to Range 1, the API waits for VOSF flag to be cleared before returning the status. If the flag is not cleared within 50 microseconds, HAL_TIMEOUT status is reported.
Return values:
HAL Status

Definition at line 112 of file stm32wbxx_hal_pwr_ex.c.

References assert_param, IS_PWR_VOLTAGE_SCALING_RANGE, PWR_FLAG_SETTING_DELAY_US, PWR_REGULATOR_VOLTAGE_SCALE1, and PWR_REGULATOR_VOLTAGE_SCALE2.

void HAL_PWREx_Disable802ActivityIT ( void )

Disable 802.15.4 Activity interrupt.

Return values:
None

Definition at line 298 of file stm32wbxx_hal_pwr_ex.c.

void HAL_PWREx_DisableBatteryCharging ( void )

Disable battery charging.

Return values:
None

Definition at line 178 of file stm32wbxx_hal_pwr_ex.c.

void HAL_PWREx_DisableBLEActivityIT ( void )

Disable BLE Activity interrupt.

Return values:
None

Definition at line 279 of file stm32wbxx_hal_pwr_ex.c.

void HAL_PWREx_DisableBORH_SMPSBypassIT ( void )

Disable BORH and SMPS step down converter forced in bypass mode interrupt for CPU1.

Return values:
None

Definition at line 241 of file stm32wbxx_hal_pwr_ex.c.

void HAL_PWREx_DisableFlashPowerDown ( uint32_t PowerMode )

Disable Flash Power Down.

Note:
This API allows to disable flash power down capabilities in low power run and low power sleep modes.
Parameters:
PowerMode this can be a combination of following values:
  • PWR_FLASHPD_LPRUN
  • PWR_FLASHPD_LPSLEEP
Return values:
None

Definition at line 697 of file stm32wbxx_hal_pwr_ex.c.

References assert_param, and IS_PWR_FLASH_POWERDOWN.

HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Disable GPIO pull-down state in Standby and Shutdown modes.

Note:
Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O in pull-down state in Standby and Shutdown modes.
Even if a PDy bit to reset is reserved, the other PDy bits entered as input parameter at the same time are reset.
Parameters:
GPIO | Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H to select the GPIO peripheral.
GPIONumber | Specify the I/O pins numbers. This parameter can be one of the following values: PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less I/O pins are available) or the logical OR of several of them to reset several bits for a given port in a single API call.
Return values:
HAL Status

Definition at line 520 of file stm32wbxx_hal_pwr_ex.c.

References assert_param, IS_PWR_GPIO, IS_PWR_GPIO_BIT_NUMBER, PWR_GPIO_A, PWR_GPIO_B, PWR_GPIO_C, PWR_GPIO_D, PWR_GPIO_E, PWR_GPIO_H, PWR_PORTE_AVAILABLE_PINS, and PWR_PORTH_AVAILABLE_PINS.

HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Disable GPIO pull-up state in Standby mode and Shutdown modes.

Note:
Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O in pull-up state in Standby and Shutdown modes.
Even if a PUy bit to reset is reserved, the other PUy bits entered as input parameter at the same time are reset.
Parameters:
GPIO | Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H to select the GPIO peripheral.
GPIONumber | Specify the I/O pins numbers. This parameter can be one of the following values: PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less I/O pins are available) or the logical OR of several of them to reset several bits for a given port in a single API call.
Return values:
HAL Status

Definition at line 402 of file stm32wbxx_hal_pwr_ex.c.

References assert_param, IS_PWR_GPIO, IS_PWR_GPIO_BIT_NUMBER, PWR_GPIO_A, PWR_GPIO_B, PWR_GPIO_C, PWR_GPIO_D, PWR_GPIO_E, PWR_GPIO_H, PWR_PORTE_AVAILABLE_PINS, and PWR_PORTH_AVAILABLE_PINS.

void HAL_PWREx_DisableHOLDC2IT ( void )

Disable CPU2 on-Hold interrupt.

Return values:
None

Definition at line 316 of file stm32wbxx_hal_pwr_ex.c.

void HAL_PWREx_DisableInternalWakeUpLine ( void )

Disable Internal Wake-up Line.

Return values:
None

Definition at line 220 of file stm32wbxx_hal_pwr_ex.c.

HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode ( void )

Exit Low-power Run mode.

Note:
Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode returns HAL_TIMEOUT status). The system clock frequency can then be increased above 2 MHz.
Return values:
HAL Status

Definition at line 1053 of file stm32wbxx_hal_pwr_ex.c.

References PWR_FLAG_SETTING_DELAY_US.

Referenced by HAL_PWR_EnterSLEEPMode().

void HAL_PWREx_DisablePullUpPullDownConfig ( void )

Disable pull-up and pull-down configuration.

Note:
When APC bit is cleared, the I/O pull-up and pull-down configurations defined in PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes.
Return values:
None

Definition at line 578 of file stm32wbxx_hal_pwr_ex.c.

void HAL_PWREx_DisablePVM1 ( void )

Disable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.

Return values:
None

Definition at line 720 of file stm32wbxx_hal_pwr_ex.c.

References PWR_PVM_1.

void HAL_PWREx_DisablePVM3 ( void )

Disable the Power Voltage Monitoring 3: VDDA versus 1.62V.

Return values:
None

Definition at line 739 of file stm32wbxx_hal_pwr_ex.c.

References PWR_PVM_3.

void HAL_PWREx_DisableRFPhaseIT ( void )

Disable RF Phase interrupt.

Return values:
None

Definition at line 260 of file stm32wbxx_hal_pwr_ex.c.

void HAL_PWREx_DisableSRAMRetention ( void )

Disable BKRAM content retention in Standby mode.

Note:
When RRS bit is reset, SRAM is powered off in Standby mode and its content is lost.
Return values:
None

Definition at line 659 of file stm32wbxx_hal_pwr_ex.c.

References LL_PWR_DisableSRAM2Retention().

void HAL_PWREx_DisableVddUSB ( void )

Disable VDDUSB supply.

Return values:
None

Definition at line 199 of file stm32wbxx_hal_pwr_ex.c.

void HAL_PWREx_Enable802ActivityIT ( void )

Enable 802.15.4 Activity interrupt.

Return values:
None

Definition at line 289 of file stm32wbxx_hal_pwr_ex.c.

void HAL_PWREx_EnableBatteryCharging ( uint32_t ResistorSelection )

Enable battery charging.

When VDD is present, charge the external battery on VBAT thru an internal resistor.

Parameters:
ResistorSelection specifies the resistor impedance. This parameter can be one of the following values:
  • PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor
  • PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor
Return values:
None

Definition at line 163 of file stm32wbxx_hal_pwr_ex.c.

References assert_param, and IS_PWR_BATTERY_RESISTOR_SELECT.

void HAL_PWREx_EnableBLEActivityIT ( void )

Enable BLE Activity interrupt.

Return values:
None

Definition at line 270 of file stm32wbxx_hal_pwr_ex.c.

void HAL_PWREx_EnableBORH_SMPSBypassIT ( void )

Enable BORH and SMPS step down converter forced in bypass mode interrupt for CPU1.

Return values:
None

Definition at line 231 of file stm32wbxx_hal_pwr_ex.c.

void HAL_PWREx_EnableFlashPowerDown ( uint32_t PowerMode )

Enable Flash Power Down.

Note:
This API allows to enable flash power down capabilities in low power run and low power sleep modes.
Parameters:
PowerMode this can be a combination of following values:
  • PWR_FLASHPD_LPRUN
  • PWR_FLASHPD_LPSLEEP
Return values:
None

Definition at line 674 of file stm32wbxx_hal_pwr_ex.c.

References assert_param, IS_PWR_FLASH_POWERDOWN, and PWR_FLASHPD_LPRUN.

HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Enable GPIO pull-down state in Standby and Shutdown modes.

Note:
Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in pull-down state in Standby and Shutdown modes.
This state is effective in Standby and Shutdown modes only if APC bit is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
The configuration is lost when exiting the Shutdown mode due to the power-on reset, maintained when exiting the Standby mode.
To avoid any conflict at Standby and Shutdown modes exits, the corresponding PUy bit of PWR_PUCRx register is cleared unless it is reserved.
Even if a PDy bit to set is reserved, the other PDy bits entered as input parameter at the same time are set.
Parameters:
GPIO | Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H to select the GPIO peripheral.
GPIONumber | Specify the I/O pins numbers. This parameter can be one of the following values: PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less I/O pins are available) or the logical OR of several of them to set several bits for a given port in a single API call.
Return values:
HAL Status

Definition at line 462 of file stm32wbxx_hal_pwr_ex.c.

References assert_param, IS_PWR_GPIO, IS_PWR_GPIO_BIT_NUMBER, PWR_GPIO_A, PWR_GPIO_B, PWR_GPIO_C, PWR_GPIO_D, PWR_GPIO_E, PWR_GPIO_H, PWR_PORTE_AVAILABLE_PINS, and PWR_PORTH_AVAILABLE_PINS.

HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp | ( | uint32_t | GPIO,
 |  | uint32_t | GPIONumber
 | ) |  |

Enable GPIO pull-up state in Standby and Shutdown modes.

Note:
Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in pull-up state in Standby and Shutdown modes.
This state is effective in Standby and Shutdown modes only if APC bit is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
The configuration is lost when exiting the Shutdown mode due to the power-on reset, maintained when exiting the Standby mode.
To avoid any conflict at Standby and Shutdown modes exits, the corresponding PDy bit of PWR_PDCRx register is cleared unless it is reserved.
Even if a PUy bit to set is reserved, the other PUy bits entered as input parameter at the same time are set.
Parameters:
GPIO | Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H to select the GPIO peripheral.
GPIONumber | Specify the I/O pins numbers. This parameter can be one of the following values: PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less I/O pins are available) or the logical OR of several of them to set several bits for a given port in a single API call.
Return values:
HAL Status

Definition at line 344 of file stm32wbxx_hal_pwr_ex.c.

References assert_param, IS_PWR_GPIO, IS_PWR_GPIO_BIT_NUMBER, PWR_GPIO_A, PWR_GPIO_B, PWR_GPIO_C, PWR_GPIO_D, PWR_GPIO_E, PWR_GPIO_H, PWR_PORTE_AVAILABLE_PINS, and PWR_PORTH_AVAILABLE_PINS.

void HAL_PWREx_EnableHOLDC2IT ( void )

Enable CPU2 on-Hold interrupt.

Return values:
None

Definition at line 307 of file stm32wbxx_hal_pwr_ex.c.

void HAL_PWREx_EnableInternalWakeUpLine ( void )

Enable Internal Wake-up Line.

Return values:
None

Definition at line 211 of file stm32wbxx_hal_pwr_ex.c.

void HAL_PWREx_EnableLowPowerRunMode ( void )

Enter Low-power Run mode.

Note:
In Low-power Run mode, all I/O pins keep the same state as in Run mode.
When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the Flash in power-down mode in setting the RUN_PD bit in FLASH_ACR register. Additionally, the clock frequency must be reduced below 2 MHz. Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must be done before calling HAL_PWREx_EnableLowPowerRunMode() API.
Return values:
None

Definition at line 1038 of file stm32wbxx_hal_pwr_ex.c.

Referenced by HAL_PWR_EnterSLEEPMode().

void HAL_PWREx_EnablePullUpPullDownConfig ( void )

Enable pull-up and pull-down configuration.

Note:
When APC bit is set, the I/O pull-up and pull-down configurations defined in PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes.
Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher). HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there is no conflict when setting PUy or PDy bit.
Return values:
None

Definition at line 567 of file stm32wbxx_hal_pwr_ex.c.

void HAL_PWREx_EnablePVM1 ( void )

Enable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.

Return values:
None

Definition at line 711 of file stm32wbxx_hal_pwr_ex.c.

References PWR_PVM_1.

void HAL_PWREx_EnablePVM3 ( void )

Enable the Power Voltage Monitoring 3: VDDA versus 1.62V.

Return values:
None

Definition at line 730 of file stm32wbxx_hal_pwr_ex.c.

References PWR_PVM_3.

void HAL_PWREx_EnableRFPhaseIT ( void )

Enable RF Phase interrupt.

Return values:
None

Definition at line 251 of file stm32wbxx_hal_pwr_ex.c.

void HAL_PWREx_EnableSRAMRetention ( void )

Enable BKRAM content retention in Standby mode.

Note:
When RRS bit is set, SRAM is powered by the low-power regulator in Standby mode and its content is kept.
Return values:
None

Definition at line 648 of file stm32wbxx_hal_pwr_ex.c.

References LL_PWR_EnableSRAM2Retention().

void HAL_PWREx_EnableVddUSB ( void )

Enable VDDUSB supply.

Note:
Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present.
Return values:
None

Definition at line 190 of file stm32wbxx_hal_pwr_ex.c.

void HAL_PWREx_EnableWakeUpPin | ( | uint32_t | WakeUpPinPolarity,
 |  | uint32_t | wakeupTarget
 | ) |  |

Enable the WakeUp PINx functionality.

Parameters:
WakeUpPinPolarity Specifies which Wake-Up pin to enable. This parameter can be one of the following legacy values which set the default polarity i.e. detection on high level (rising edge):
  • PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
or one of the following value where the user can explicitly specify the enabled pin and the chosen polarity:
  • PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
  • PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
  • PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
  • PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
  • PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
wakeupTarget Specifies the wake-up target
  • PWR_CORE_CPU1
  • PWR_CORE_CPU2
Note:
PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
Return values:
None

Definition at line 969 of file stm32wbxx_hal_pwr_ex.c.

References assert_param, IS_PWR_WAKEUP_PIN, PWR_CORE_CPU2, and PWR_WUP_POLARITY_SHIFT.

void HAL_PWREx_EnterSHUTDOWNMode ( void )

Enter Shutdown mode.

Note:
In Shutdown mode, the PLL, the HSI, the MSI, the LSI and the HSE oscillators are switched off. The voltage regulator is disabled and Vcore domain is powered off. SRAM1, SRAM2, BKRAM and registers contents are lost except for registers in the Backup domain. The BOR is not available.
The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
According to system power policy, system entering in Shutdown mode is depending on other CPU power mode.
Return values:
None

Definition at line 1263 of file stm32wbxx_hal_pwr_ex.c.

References PWR_LOWPOWERMODE_SHUTDOWN.

void HAL_PWREx_EnterSTOP0Mode ( uint8_t STOPEntry )

Enter Stop 0 mode.

Note:
In Stop 0 mode, main and low voltage regulators are ON.
In Stop 0 mode, all I/O pins keep the same state as in Run mode.
All clocks in the VCORE domain are stopped; the PLL, the MSI, the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated only to the peripheral requesting it. SRAM1, SRAM2 and register contents are preserved. The BOR is available.
When exiting Stop 0 mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register is set; the MSI oscillator is selected if STOPWUCK is cleared.
By keeping the internal regulator ON during Stop 0 mode, the consumption is higher although the startup time is reduced.
Case of Stop0 mode with SMPS: Before entering Stop 0 mode with SMPS Step Down converter enabled, the HSI16 must be kept on by enabling HSI kernel clock (set HSIKERON register bit).
According to system power policy, system entering in Stop mode is depending on other CPU power mode.
Parameters:
STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. This parameter can be one of the following values:
  • PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
  • PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
Return values:
None

Definition at line 1102 of file stm32wbxx_hal_pwr_ex.c.

References assert_param, IS_PWR_STOP_ENTRY, PWR_LOWPOWERMODE_STOP0, and PWR_STOPENTRY_WFI.

Referenced by HAL_PWR_EnterSTOPMode().

void HAL_PWREx_EnterSTOP1Mode ( uint8_t STOPEntry )

Enter Stop 1 mode.

Note:
In Stop 1 mode, only low power voltage regulator is ON.
In Stop 1 mode, all I/O pins keep the same state as in Run mode.
All clocks in the VCORE domain are stopped; the PLL, the MSI, the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated only to the peripheral requesting it. SRAM1, SRAM2 and register contents are preserved. The BOR is available.
When exiting Stop 1 mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register is set; the MSI oscillator is selected if STOPWUCK is cleared.
Due to low power mode, an additional startup delay is incurred when waking up from Stop 1 mode.
According to system power policy, system entering in Stop mode is depending on other CPU power mode.
Parameters:
STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. This parameter can be one of the following values:
  • PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
  • PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
Return values:
None

Definition at line 1156 of file stm32wbxx_hal_pwr_ex.c.

References assert_param, IS_PWR_STOP_ENTRY, PWR_LOWPOWERMODE_STOP1, and PWR_STOPENTRY_WFI.

Referenced by HAL_PWR_EnterSTOPMode().

void HAL_PWREx_EnterSTOP2Mode ( uint8_t STOPEntry )

Enter Stop 2 mode.

Note:
In Stop 2 mode, only low power voltage regulator is ON.
In Stop 2 mode, all I/O pins keep the same state as in Run mode.
All clocks in the VCORE domain are stopped, the PLL, the MSI, the HSI and the HSE oscillators are disabled. Some peripherals with wakeup capability (LCD, LPTIM1, I2C3 and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after receiving the frame if it is not a wakeup frame. In this case the HSI clock is propagated only to the peripheral requesting it. SRAM1, SRAM2 and register contents are preserved. The BOR is available. The voltage regulator is set in low-power mode but LPR bit must be cleared to enter stop 2 mode. Otherwise, Stop 1 mode is entered.
When exiting Stop 2 mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register is set; the MSI oscillator is selected if STOPWUCK is cleared.
Case of Stop2 mode and debugger probe attached: a workaround should be applied. Issue specified in "ES0394 - STM32WB55Cx/Rx/Vx device errata": 2.2.9 Incomplete Stop 2 mode entry after a wakeup from debug upon EXTI line 48 event "With the JTAG debugger enabled on GPIO pins and after a wakeup from debug triggered by an event on EXTI line 48 (CDBGPWRUPREQ), the device may enter in a state in which attempts to enter Stop 2 mode are not fully effective ..." Workaround implementation example using LL driver: LL_EXTI_DisableIT_32_63(LL_EXTI_LINE_48); LL_C2_EXTI_DisableIT_32_63(LL_EXTI_LINE_48);
According to system power policy, system entering in Stop mode is depending on other CPU power mode.
Parameters:
STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. This parameter can be one of the following values:
  • PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
  • PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
Return values:
None

Definition at line 1219 of file stm32wbxx_hal_pwr_ex.c.

References assert_param, IS_PWR_STOP_ENTRY, PWR_LOWPOWERMODE_STOP2, and PWR_STOPENTRY_WFI.

uint32_t HAL_PWREx_GetBORConfig ( void )

Get BOR configuration.

Return values:
Returned value can be one of the following values:
  • PWR_BOR_SYSTEM_RESET
  • PWR_BOR_SMPS_FORCE_BYPASS

Definition at line 603 of file stm32wbxx_hal_pwr_ex.c.

References LL_PWR_GetBORConfig().

uint32_t HAL_PWREx_GetVoltageRange ( void )

Return Voltage Scaling Range.

Return values:
VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2)

Definition at line 87 of file stm32wbxx_hal_pwr_ex.c.

Referenced by RCC_SetFlashLatencyFromMSIRange().

uint32_t HAL_PWREx_GetWakeupFlag ( uint32_t WakeUpFlag )

Get the Wake-Up pin flag.

Parameters:
WakeUpFlag specifies the Wake-Up PIN flag to check. This parameter can be one of the following values:
  • PWR_FLAG_WUF1: A wakeup event was received from PA0.
  • PWR_FLAG_WUF2: A wakeup event was received from PC13.
  • PWR_FLAG_WUF3: A wakeup event was received from PC12.
  • PWR_FLAG_WUF4: A wakeup event was received from PA2.
  • PWR_FLAG_WUF5: A wakeup event was received from PC5.
Return values:
The Wake-Up pin flag.

Definition at line 999 of file stm32wbxx_hal_pwr_ex.c.

void HAL_PWREx_HoldCore ( uint32_t CPU )

Hold the CPU and their allocated peripherals after reset or wakeup from stop or standby.

Parameters:
CPU,: Specifies the core to be held. This parameter can be one of the following values:
  • PWR_CORE_CPU2: Hold CPU2 and set CPU1 as master.
Note:
Hold CPU2 with CPU1 as master by default.
Return values:
None

Definition at line 618 of file stm32wbxx_hal_pwr_ex.c.

References assert_param, IS_PWR_CORE_HOLD_RELEASE, and LL_PWR_DisableBootC2().

void HAL_PWREx_PVD_PVM_IRQHandler ( void )

This function handles the PWR PVD/PVMx interrupt request.

Note:
This API should be called under the PVD_PVM_IRQHandler().
Return values:
None

Definition at line 1292 of file stm32wbxx_hal_pwr_ex.c.

References __HAL_PWR_PVD_EXTI_CLEAR_FLAG, __HAL_PWR_PVD_EXTI_GET_FLAG, __HAL_PWR_PVM1_EXTI_CLEAR_FLAG, __HAL_PWR_PVM1_EXTI_GET_FLAG, __HAL_PWR_PVM3_EXTI_CLEAR_FLAG, __HAL_PWR_PVM3_EXTI_GET_FLAG, HAL_PWR_PVDCallback(), HAL_PWREx_PVM1Callback(), and HAL_PWREx_PVM3Callback().

void HAL_PWREx_PVM1Callback ( void )

PWR PVM1 interrupt callback.

Return values:
None

Definition at line 1331 of file stm32wbxx_hal_pwr_ex.c.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

void HAL_PWREx_PVM3Callback ( void )

PWR PVM3 interrupt callback.

Return values:
None

Definition at line 1343 of file stm32wbxx_hal_pwr_ex.c.

Referenced by HAL_PWREx_PVD_PVM_IRQHandler().

void HAL_PWREx_ReleaseCore ( uint32_t CPU )

Release Cortex CPU2 and allocated peripherals after reset or wakeup from stop or standby.

Parameters:
CPU,: Specifies the core to be released. This parameter can be one of the following values:
  • PWR_CORE_CPU2: Release the CPU2 from holding.
Return values:
None

Definition at line 633 of file stm32wbxx_hal_pwr_ex.c.

References assert_param, IS_PWR_CORE_HOLD_RELEASE, and LL_PWR_EnableBootC2().

void HAL_PWREx_SetBORConfig ( uint32_t BORConfiguration )

Set BOR configuration.

Parameters:
BORConfiguration This parameter can be one of the following values:
  • PWR_BOR_SYSTEM_RESET
  • PWR_BOR_SMPS_FORCE_BYPASS

Definition at line 592 of file stm32wbxx_hal_pwr_ex.c.

References LL_PWR_SetBORConfig().

uint32_t HAL_PWREx_SMPS_GetEffectiveMode ( void )

Get SMPS effective operating mode.

Note:
SMPS operating mode can be changed by hardware, therefore requested operating mode can differ from effective low power mode.
  • dependency on system low-power mode:
    • step down mode if system low power mode is run, LP run or stop,
    • open mode if system low power mode is stop1, stop2, standby or shutdown
  • dependency on BOR level:
    • bypass mode if supply voltage drops below BOR level
This functions check flags of SMPS operating modes step down and bypass. If the SMPS is not among these 2 operating modes, then it can be in mode off or open.
Return values:
Returned value can be one of the following values:
  • PWR_SMPS_BYPASS
  • PWR_SMPS_STEP_DOWN (1)
(1) SMPS operating mode step down or open depends on system low-power mode:
  • step down mode if system low power mode is run, LP run or stop,
  • open mode if system low power mode is stop1, stop2, standby or shutdown

Definition at line 941 of file stm32wbxx_hal_pwr_ex.c.

void HAL_PWREx_SMPS_SetMode ( uint32_t OperatingMode )

Set SMPS operating mode.

Parameters:
OperatingMode This parameter can be one of the following values:
  • PWR_SMPS_BYPASS
  • PWR_SMPS_STEP_DOWN (1)
(1) SMPS operating mode step down or open depends on system low-power mode:
  • step down mode if system low power mode is run, LP run or stop,
  • open mode if system low power mode is stop1, stop2, standby or shutdown
Return values:
None

Definition at line 916 of file stm32wbxx_hal_pwr_ex.c.

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PWR Extended Private Macros

Defines
PWR Extended Private Macros
PWREx

Defines

#define | IS_PWR_WAKEUP_PIN(PIN)
#define | IS_PWR_WAKEUP_PIN_POLARITY(POLARITY)
#define | IS_PWR_PVM_TYPE(TYPE)
#define | IS_PWR_PVM_MODE(MODE)
#define | IS_PWR_FLASH_POWERDOWN(__MODE__)
#define | IS_PWR_VOLTAGE_SCALING_RANGE(RANGE)
#define | IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR)
#define | IS_PWR_BATTERY_CHARGING(CHARGING)
#define | IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00)
#define | IS_PWR_GPIO(GPIO)
#define | IS_PWR_SMPS_MODE(SMPS_MODE)
#define | IS_PWR_SMPS_STARTUP_CURRENT(SMPS_STARTUP_CURRENT)
#define | IS_PWR_SMPS_OUTPUT_VOLTAGE(SMPS_OUTPUT_VOLTAGE)
#define | IS_PWR_CORE(CPU) (((CPU) == PWR_CORE_CPU1) || ((CPU) == PWR_CORE_CPU2))
#define | IS_PWR_CORE_HOLD_RELEASE(CPU) ((CPU) == PWR_CORE_CPU2)

Define Documentation

#define IS_PWR_BATTERY_CHARGING ( CHARGING )
Value:
(((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\
                                           ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE))

Definition at line 786 of file stm32wbxx_hal_pwr_ex.h.

#define IS_PWR_BATTERY_RESISTOR_SELECT ( RESISTOR )
Value:
(((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
                                                  ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))

Definition at line 783 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_EnableBatteryCharging().

#define IS_PWR_CORE ( CPU ) (((CPU) == PWR_CORE_CPU1) || ((CPU) == PWR_CORE_CPU2))

Definition at line 837 of file stm32wbxx_hal_pwr_ex.h.

#define IS_PWR_CORE_HOLD_RELEASE ( CPU ) ((CPU) == PWR_CORE_CPU2)

Definition at line 839 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_HoldCore(), and HAL_PWREx_ReleaseCore().

#define IS_PWR_FLASH_POWERDOWN ( __MODE__ )
Value:
((((__MODE__) & (PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP)) != 0x00u) && \
                                             (((__MODE__) & ~(PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP)) == 0x00u))

Definition at line 775 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableFlashPowerDown(), and HAL_PWREx_EnableFlashPowerDown().

#define IS_PWR_GPIO ( GPIO )
Value:
(((GPIO) == PWR_GPIO_A) ||\
                           ((GPIO) == PWR_GPIO_B) ||\
                           ((GPIO) == PWR_GPIO_C) ||\
                           ((GPIO) == PWR_GPIO_D) ||\
                           ((GPIO) == PWR_GPIO_E) ||\
                           ((GPIO) == PWR_GPIO_H))

Definition at line 793 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define IS_PWR_GPIO_BIT_NUMBER ( BIT_NUMBER ) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00)

Definition at line 790 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown(), and HAL_PWREx_EnableGPIOPullUp().

#define IS_PWR_PVM_MODE ( MODE )
Value:
(((MODE) == PWR_PVM_MODE_NORMAL)              ||\
                                ((MODE) == PWR_PVM_MODE_IT_RISING)           ||\
                                ((MODE) == PWR_PVM_MODE_IT_FALLING)          ||\
                                ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING)   ||\
                                ((MODE) == PWR_PVM_MODE_EVENT_RISING)        ||\
                                ((MODE) == PWR_PVM_MODE_EVENT_FALLING)       ||\
                                ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING))

Definition at line 767 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define IS_PWR_PVM_TYPE ( TYPE )
Value:
(((TYPE) == PWR_PVM_1) ||\
                               ((TYPE) == PWR_PVM_3))

Definition at line 761 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigPVM().

#define IS_PWR_SMPS_MODE ( SMPS_MODE )
Value:
(((SMPS_MODE) == PWR_SMPS_BYPASS)    ||\
                                     ((SMPS_MODE) == PWR_SMPS_STEP_DOWN))

Definition at line 808 of file stm32wbxx_hal_pwr_ex.h.

#define IS_PWR_SMPS_OUTPUT_VOLTAGE ( SMPS_OUTPUT_VOLTAGE )
Value:
(((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V20) ||\
                                                         ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V25) ||\
                                                         ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V30) ||\
                                                         ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V35) ||\
                                                         ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V40) ||\
                                                         ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V45) ||\
                                                         ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V50) ||\
                                                         ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V55) ||\
                                                         ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V60) ||\
                                                         ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V65) ||\
                                                         ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V70) ||\
                                                         ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V75) ||\
                                                         ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V80) ||\
                                                         ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V85) ||\
                                                         ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V90))

Definition at line 820 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigSMPS().

#define IS_PWR_SMPS_STARTUP_CURRENT ( SMPS_STARTUP_CURRENT )
Value:
(((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_80MA)  ||\
                                                           ((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_100MA) ||\
                                                           ((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_120MA) ||\
                                                           ((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_140MA) ||\
                                                           ((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_160MA) ||\
                                                           ((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_180MA) ||\
                                                           ((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_200MA) ||\
                                                           ((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_220MA))

Definition at line 811 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ConfigSMPS().

#define IS_PWR_VOLTAGE_SCALING_RANGE ( RANGE )
Value:
(((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
                                             ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))

Definition at line 779 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWREx_ControlVoltageScaling().

#define IS_PWR_WAKEUP_PIN ( PIN )
Value:
(((PIN) == PWR_WAKEUP_PIN1_HIGH) || \
                                ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \
                                ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \
                                ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \
                                ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \
                                ((PIN) == PWR_WAKEUP_PIN1_LOW) || \
                                ((PIN) == PWR_WAKEUP_PIN2_LOW) || \
                                ((PIN) == PWR_WAKEUP_PIN3_LOW) || \
                                ((PIN) == PWR_WAKEUP_PIN4_LOW) || \
                                ((PIN) == PWR_WAKEUP_PIN5_LOW))

Definition at line 740 of file stm32wbxx_hal_pwr_ex.h.

Referenced by HAL_PWR_DisableWakeUpPin(), HAL_PWR_EnableWakeUpPin(), and HAL_PWREx_EnableWakeUpPin().

#define IS_PWR_WAKEUP_PIN_POLARITY ( POLARITY )
Value:
(((POLARITY) == PWR_PIN_POLARITY_HIGH) || \
                                               ((POLARITY) == PWR_PIN_POLARITY_LOW))

Definition at line 757 of file stm32wbxx_hal_pwr_ex.h.

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: QSPI Private Constants

Defines
QSPI Private Constants
QSPI

Defines

#define | QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE 0x00000000U
#define | QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0)
#define | QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1)
#define | QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE)

Define Documentation

#define QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1)

Automatic polling mode

Definition at line 231 of file stm32wbxx_hal_qspi.c.

Referenced by HAL_QSPI_AutoPolling(), and HAL_QSPI_AutoPolling_IT().

#define QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0)

Indirect read mode

Definition at line 230 of file stm32wbxx_hal_qspi.c.

Referenced by HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), and HAL_QSPI_Receive_IT().

#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE 0x00000000U

Indirect write mode

Definition at line 229 of file stm32wbxx_hal_qspi.c.

Referenced by HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), and HAL_QSPI_Transmit_IT().

#define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE)

Memory-mapped mode

Definition at line 232 of file stm32wbxx_hal_qspi.c.

Referenced by HAL_QSPI_MemoryMapped(), and QSPI_Config().

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: QSPI Private Macros

Defines
QSPI Private Macros
QSPI

Defines

#define | IS_QSPI_FUNCTIONAL_MODE(MODE)
#define | IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU)
#define | IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 16U))
#define | IS_QSPI_SSHIFT(SSHIFT)
#define | IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U))
#define | IS_QSPI_CS_HIGH_TIME(CSHTIME)
#define | IS_QSPI_CLOCK_MODE(CLKMODE)
#define | IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU)
#define | IS_QSPI_ADDRESS_SIZE(ADDR_SIZE)
#define | IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE)
#define | IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U)
#define | IS_QSPI_INSTRUCTION_MODE(MODE)
#define | IS_QSPI_ADDRESS_MODE(MODE)
#define | IS_QSPI_ALTERNATE_BYTES_MODE(MODE)
#define | IS_QSPI_DATA_MODE(MODE)
#define | IS_QSPI_DDR_MODE(DDR_MODE)
#define | IS_QSPI_SIOO_MODE(SIOO_MODE)
#define | IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
#define | IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U))
#define | IS_QSPI_MATCH_MODE(MODE)
#define | IS_QSPI_AUTOMATIC_STOP(APMS)
#define | IS_QSPI_TIMEOUT_ACTIVATION(TCEN)
#define | IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU)

Define Documentation

#define IS_QSPI_ADDRESS_MODE ( MODE )
Value:
(((MODE) == QSPI_ADDRESS_NONE)    || \
                                            ((MODE) == QSPI_ADDRESS_1_LINE)  || \
                                            ((MODE) == QSPI_ADDRESS_2_LINES) || \
                                            ((MODE) == QSPI_ADDRESS_4_LINES))

Definition at line 652 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_ADDRESS_SIZE ( ADDR_SIZE )
Value:
(((ADDR_SIZE) == QSPI_ADDRESS_8_BITS)  || \
                                            ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
                                            ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
                                            ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))

Definition at line 635 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_ALTERNATE_BYTES_MODE ( MODE )
Value:
(((MODE) == QSPI_ALTERNATE_BYTES_NONE)    || \
                                            ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE)  || \
                                            ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
                                            ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))

Definition at line 657 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_ALTERNATE_BYTES_SIZE ( SIZE )
Value:
(((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS)  || \
                                            ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
                                            ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
                                            ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))

Definition at line 640 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_AUTOMATIC_STOP ( APMS )
Value:
(((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
                                            ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))

Definition at line 680 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling_IT().

#define IS_QSPI_CLOCK_MODE ( CLKMODE )
Value:
(((CLKMODE) == QSPI_CLOCK_MODE_0) || \
                                            ((CLKMODE) == QSPI_CLOCK_MODE_3))

Definition at line 630 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

#define IS_QSPI_CLOCK_PRESCALER ( PRESCALER ) ((PRESCALER) <= 0xFFU)

Definition at line 612 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

#define IS_QSPI_CS_HIGH_TIME ( CSHTIME )
Value:
(((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))

Definition at line 621 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

#define IS_QSPI_DATA_MODE ( MODE )
Value:
(((MODE) == QSPI_DATA_NONE)    || \
                                            ((MODE) == QSPI_DATA_1_LINE)  || \
                                            ((MODE) == QSPI_DATA_2_LINES) || \
                                            ((MODE) == QSPI_DATA_4_LINES))

Definition at line 662 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_DDR_MODE ( DDR_MODE )
Value:
(((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
                                            ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))

Definition at line 667 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_DUMMY_CYCLES ( DCY ) ((DCY) <= 31U)

Definition at line 645 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_FIFO_THRESHOLD ( THR ) (((THR) > 0U) && ((THR) <= 16U))

Definition at line 614 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

#define IS_QSPI_FLASH_SIZE ( FSIZE ) (((FSIZE) <= 31U))

Definition at line 619 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

#define IS_QSPI_FUNCTIONAL_MODE ( MODE )
Value:
(((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \
                                       ((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ)  || \
                                       ((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING)   || \
                                       ((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))

Definition at line 241 of file stm32wbxx_hal_qspi.c.

Referenced by QSPI_Config().

#define IS_QSPI_INSTRUCTION ( INSTRUCTION ) ((INSTRUCTION) <= 0xFFU)

Definition at line 633 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_INSTRUCTION_MODE ( MODE )
Value:
(((MODE) == QSPI_INSTRUCTION_NONE)    || \
                                            ((MODE) == QSPI_INSTRUCTION_1_LINE)  || \
                                            ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
                                            ((MODE) == QSPI_INSTRUCTION_4_LINES))

Definition at line 647 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_INTERVAL ( INTERVAL ) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)

Definition at line 673 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), and HAL_QSPI_AutoPolling_IT().

#define IS_QSPI_MATCH_MODE ( MODE )
Value:
(((MODE) == QSPI_MATCH_MODE_AND) || \
                                            ((MODE) == QSPI_MATCH_MODE_OR))

Definition at line 677 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), and HAL_QSPI_AutoPolling_IT().

#define IS_QSPI_SIOO_MODE ( SIOO_MODE )
Value:
(((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
                                            ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))

Definition at line 670 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

#define IS_QSPI_SSHIFT ( SSHIFT )
Value:
(((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
                                            ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))

Definition at line 616 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

#define IS_QSPI_STATUS_BYTES_SIZE ( SIZE ) (((SIZE) >= 1U) && ((SIZE) <= 4U))

Definition at line 675 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), and HAL_QSPI_AutoPolling_IT().

#define IS_QSPI_TIMEOUT_ACTIVATION ( TCEN )
Value:
(((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
                                            ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))

Definition at line 683 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_MemoryMapped().

#define IS_QSPI_TIMEOUT_PERIOD ( PERIOD ) ((PERIOD) <= 0xFFFFU)

Definition at line 686 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_MemoryMapped().

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization/de-initialization functions

Functions
Initialization/de-initialization functions
QSPI Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi)
Initialize the QSPI mode according to the specified parameters in the QSPI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi)
De-Initialize the QSPI peripheral.
__weak void | HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi)
Initialize the QSPI MSP.
__weak void | HAL_QSPI_MspDeInit (QSPI_HandleTypeDef *hqspi)
DeInitialize the QSPI MSP.

Detailed Description

Initialization and Configuration functions.

===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to :
      (+) Initialize the QuadSPI.
      (+) De-initialize the QuadSPI.

Function Documentation

HAL_StatusTypeDef HAL_QSPI_DeInit ( QSPI_HandleTypeDef * hqspi )

De-Initialize the QSPI peripheral.

Parameters:
hqspi : QSPI handle
Return values:
HAL status

Definition at line 387 of file stm32wbxx_hal_qspi.c.

References __HAL_QSPI_DISABLE, __QSPI_HandleTypeDef::ErrorCode, HAL_QSPI_ERROR_NONE, HAL_QSPI_MspDeInit(), HAL_QSPI_STATE_RESET, __QSPI_HandleTypeDef::MspDeInitCallback, and __QSPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_QSPI_Init ( QSPI_HandleTypeDef * hqspi )

Initialize the QSPI mode according to the specified parameters in the QSPI_InitTypeDef and initialize the associated handle.

Parameters:
hqspi : QSPI handle
Return values:
HAL status

Definition at line 289 of file stm32wbxx_hal_qspi.c.

References __HAL_QSPI_ENABLE, __QSPI_HandleTypeDef::AbortCpltCallback, assert_param, QSPI_InitTypeDef::ChipSelectHighTime, QSPI_InitTypeDef::ClockMode, QSPI_InitTypeDef::ClockPrescaler, __QSPI_HandleTypeDef::CmdCpltCallback, __QSPI_HandleTypeDef::ErrorCallback, __QSPI_HandleTypeDef::ErrorCode, QSPI_InitTypeDef::FifoThreshold, __QSPI_HandleTypeDef::FifoThresholdCallback, QSPI_InitTypeDef::FlashSize, HAL_GetTick(), HAL_QSPI_AbortCpltCallback(), HAL_QSPI_CmdCpltCallback(), HAL_QSPI_ERROR_NONE, HAL_QSPI_ErrorCallback(), HAL_QSPI_FifoThresholdCallback(), HAL_QSPI_MspInit(), HAL_QSPI_RxCpltCallback(), HAL_QSPI_RxHalfCpltCallback(), HAL_QSPI_SetTimeout(), HAL_QSPI_STATE_READY, HAL_QSPI_STATE_RESET, HAL_QSPI_StatusMatchCallback(), HAL_QSPI_TIMEOUT_DEFAULT_VALUE, HAL_QSPI_TimeOutCallback(), HAL_QSPI_TxCpltCallback(), HAL_QSPI_TxHalfCpltCallback(), __QSPI_HandleTypeDef::Init, __QSPI_HandleTypeDef::Instance, IS_QSPI_CLOCK_MODE, IS_QSPI_CLOCK_PRESCALER, IS_QSPI_CS_HIGH_TIME, IS_QSPI_FIFO_THRESHOLD, IS_QSPI_FLASH_SIZE, IS_QSPI_SSHIFT, __QSPI_HandleTypeDef::Lock, __QSPI_HandleTypeDef::MspInitCallback, QSPI_FLAG_BUSY, QSPI_WaitFlagStateUntilTimeout(), __QSPI_HandleTypeDef::RxCpltCallback, __QSPI_HandleTypeDef::RxHalfCpltCallback, QSPI_InitTypeDef::SampleShifting, __QSPI_HandleTypeDef::State, __QSPI_HandleTypeDef::StatusMatchCallback, __QSPI_HandleTypeDef::Timeout, __QSPI_HandleTypeDef::TimeOutCallback, __QSPI_HandleTypeDef::TxCpltCallback, and __QSPI_HandleTypeDef::TxHalfCpltCallback.

void HAL_QSPI_MspDeInit ( QSPI_HandleTypeDef * hqspi )

DeInitialize the QSPI MSP.

Parameters:
hqspi : QSPI handle
Return values:
None

Definition at line 446 of file stm32wbxx_hal_qspi.c.

Referenced by HAL_QSPI_DeInit(), and HAL_QSPI_UnRegisterCallback().

void HAL_QSPI_MspInit ( QSPI_HandleTypeDef * hqspi )

Initialize the QSPI MSP.

Parameters:
hqspi : QSPI handle
Return values:
None

Definition at line 431 of file stm32wbxx_hal_qspi.c.

Referenced by HAL_QSPI_Init(), and HAL_QSPI_UnRegisterCallback().

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
QSPI Exported Functions

QSPI Transmit/Receive functions. More...

Functions

void | HAL_QSPI_IRQHandler (QSPI_HandleTypeDef *hqspi)
Handle QSPI interrupt request.
HAL_StatusTypeDef | HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
Set the command configuration.
HAL_StatusTypeDef | HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
Set the command configuration in interrupt mode.
HAL_StatusTypeDef | HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Send an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Receive an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Send an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
Configure the QSPI Automatic Polling Mode in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_AutoPolling_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
Configure the QSPI Automatic Polling Mode in non-blocking mode.
HAL_StatusTypeDef | HAL_QSPI_MemoryMapped (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
Configure the Memory Mapped mode.
__weak void | HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi)
Transfer Error callback.
__weak void | HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi)
Abort completed callback.
__weak void | HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi)
Command completed callback.
__weak void | HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi)
Rx Transfer completed callback.
__weak void | HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi)
Tx Transfer completed callback.
__weak void | HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi)
Rx Half Transfer completed callback.
__weak void | HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi)
Tx Half Transfer completed callback.
__weak void | HAL_QSPI_FifoThresholdCallback (QSPI_HandleTypeDef *hqspi)
FIFO Threshold callback.
__weak void | HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi)
Status Match callback.
__weak void | HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi)
Timeout callback.
HAL_StatusTypeDef | HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback)
Register a User QSPI Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId)
Unregister a User QSPI Callback QSPI Callback is redirected to the weak (surcharged) predefined callback.

Detailed Description

QSPI Transmit/Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to :
      (+) Handle the interrupts.
      (+) Handle the command sequence.
      (+) Transmit data in blocking, interrupt or DMA mode.
      (+) Receive data in blocking, interrupt or DMA mode.
      (+) Manage the auto-polling functional mode.
      (+) Manage the memory-mapped functional mode.

Function Documentation

void HAL_QSPI_AbortCpltCallback ( QSPI_HandleTypeDef * hqspi )

Abort completed callback.

Parameters:
hqspi : QSPI handle
Return values:
None

Definition at line 1849 of file stm32wbxx_hal_qspi.c.

Referenced by HAL_QSPI_Abort_IT(), HAL_QSPI_Init(), HAL_QSPI_IRQHandler(), and HAL_QSPI_UnRegisterCallback().

HAL_StatusTypeDef HAL_QSPI_AutoPolling | ( | QSPI_HandleTypeDef * | hqspi,
 |  | QSPI_CommandTypeDef * | cmd,
 |  | QSPI_AutoPollingTypeDef * | cfg,
 |  | uint32_t | Timeout
 | ) |  |

Configure the QSPI Automatic Polling Mode in blocking mode.

Parameters:
hqspi | : QSPI handle
cmd | : structure that contains the command configuration information.
cfg | : structure that contains the polling configuration information.
Timeout | : Timeout duration
Note:
This function is used only in Automatic Polling Mode
Return values:
HAL status

Definition at line 1547 of file stm32wbxx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, QSPI_CommandTypeDef::AddressMode, QSPI_CommandTypeDef::AddressSize, QSPI_CommandTypeDef::AlternateByteMode, QSPI_CommandTypeDef::AlternateBytesSize, assert_param, QSPI_CommandTypeDef::DataMode, QSPI_CommandTypeDef::DdrMode, QSPI_CommandTypeDef::DummyCycles, __QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_AUTO_POLLING, HAL_QSPI_STATE_READY, __QSPI_HandleTypeDef::Instance, QSPI_CommandTypeDef::Instruction, QSPI_CommandTypeDef::InstructionMode, QSPI_AutoPollingTypeDef::Interval, IS_QSPI_ADDRESS_MODE, IS_QSPI_ADDRESS_SIZE, IS_QSPI_ALTERNATE_BYTES_MODE, IS_QSPI_ALTERNATE_BYTES_SIZE, IS_QSPI_DATA_MODE, IS_QSPI_DDR_MODE, IS_QSPI_DUMMY_CYCLES, IS_QSPI_INSTRUCTION, IS_QSPI_INSTRUCTION_MODE, IS_QSPI_INTERVAL, IS_QSPI_MATCH_MODE, IS_QSPI_SIOO_MODE, IS_QSPI_STATUS_BYTES_SIZE, QSPI_AutoPollingTypeDef::Mask, QSPI_AutoPollingTypeDef::Match, QSPI_AutoPollingTypeDef::MatchMode, QSPI_CommandTypeDef::NbData, QSPI_ADDRESS_NONE, QSPI_ALTERNATE_BYTES_NONE, QSPI_AUTOMATIC_STOP_ENABLE, QSPI_Config(), QSPI_FLAG_BUSY, QSPI_FLAG_SM, QSPI_FUNCTIONAL_MODE_AUTO_POLLING, QSPI_INSTRUCTION_NONE, QSPI_WaitFlagStateUntilTimeout(), QSPI_CommandTypeDef::SIOOMode, __QSPI_HandleTypeDef::State, and QSPI_AutoPollingTypeDef::StatusBytesSize.

HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT | ( | QSPI_HandleTypeDef * | hqspi,
 |  | QSPI_CommandTypeDef * | cmd,
 |  | QSPI_AutoPollingTypeDef * | cfg
 | ) |  |

Configure the QSPI Automatic Polling Mode in non-blocking mode.

Parameters:
hqspi | : QSPI handle
cmd | : structure that contains the command configuration information.
cfg | : structure that contains the polling configuration information.
Note:
This function is used only in Automatic Polling Mode
Return values:
HAL status

Definition at line 1646 of file stm32wbxx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_ENABLE_IT, QSPI_CommandTypeDef::AddressMode, QSPI_CommandTypeDef::AddressSize, QSPI_CommandTypeDef::AlternateByteMode, QSPI_CommandTypeDef::AlternateBytesSize, assert_param, QSPI_AutoPollingTypeDef::AutomaticStop, QSPI_CommandTypeDef::DataMode, QSPI_CommandTypeDef::DdrMode, QSPI_CommandTypeDef::DummyCycles, __QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_AUTO_POLLING, HAL_QSPI_STATE_READY, __QSPI_HandleTypeDef::Instance, QSPI_CommandTypeDef::Instruction, QSPI_CommandTypeDef::InstructionMode, QSPI_AutoPollingTypeDef::Interval, IS_QSPI_ADDRESS_MODE, IS_QSPI_ADDRESS_SIZE, IS_QSPI_ALTERNATE_BYTES_MODE, IS_QSPI_ALTERNATE_BYTES_SIZE, IS_QSPI_AUTOMATIC_STOP, IS_QSPI_DATA_MODE, IS_QSPI_DDR_MODE, IS_QSPI_DUMMY_CYCLES, IS_QSPI_INSTRUCTION, IS_QSPI_INSTRUCTION_MODE, IS_QSPI_INTERVAL, IS_QSPI_MATCH_MODE, IS_QSPI_SIOO_MODE, IS_QSPI_STATUS_BYTES_SIZE, QSPI_AutoPollingTypeDef::Mask, QSPI_AutoPollingTypeDef::Match, QSPI_AutoPollingTypeDef::MatchMode, QSPI_CommandTypeDef::NbData, QSPI_ADDRESS_NONE, QSPI_ALTERNATE_BYTES_NONE, QSPI_Config(), QSPI_FLAG_BUSY, QSPI_FLAG_SM, QSPI_FLAG_TE, QSPI_FUNCTIONAL_MODE_AUTO_POLLING, QSPI_INSTRUCTION_NONE, QSPI_IT_SM, QSPI_IT_TE, QSPI_WaitFlagStateUntilTimeout(), QSPI_CommandTypeDef::SIOOMode, __QSPI_HandleTypeDef::State, QSPI_AutoPollingTypeDef::StatusBytesSize, and __QSPI_HandleTypeDef::Timeout.

void HAL_QSPI_CmdCpltCallback ( QSPI_HandleTypeDef * hqspi )

Command completed callback.

Parameters:
hqspi : QSPI handle
Return values:
None

Definition at line 1864 of file stm32wbxx_hal_qspi.c.

Referenced by HAL_QSPI_Init(), HAL_QSPI_IRQHandler(), and HAL_QSPI_UnRegisterCallback().

HAL_StatusTypeDef HAL_QSPI_Command | ( | QSPI_HandleTypeDef * | hqspi,
 |  | QSPI_CommandTypeDef * | cmd,
 |  | uint32_t | Timeout
 | ) |  |

Set the command configuration.

Parameters:
hqspi | : QSPI handle
cmd | : structure that contains the command configuration information
Timeout | : Timeout duration
Note:
This function is used only in Indirect Read or Write Modes
Return values:
HAL status

Definition at line 774 of file stm32wbxx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, QSPI_CommandTypeDef::AddressMode, QSPI_CommandTypeDef::AddressSize, QSPI_CommandTypeDef::AlternateByteMode, QSPI_CommandTypeDef::AlternateBytesSize, assert_param, QSPI_CommandTypeDef::DataMode, QSPI_CommandTypeDef::DdrMode, QSPI_CommandTypeDef::DummyCycles, __QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY, HAL_QSPI_STATE_READY, QSPI_CommandTypeDef::Instruction, QSPI_CommandTypeDef::InstructionMode, IS_QSPI_ADDRESS_MODE, IS_QSPI_ADDRESS_SIZE, IS_QSPI_ALTERNATE_BYTES_MODE, IS_QSPI_ALTERNATE_BYTES_SIZE, IS_QSPI_DATA_MODE, IS_QSPI_DDR_MODE, IS_QSPI_DUMMY_CYCLES, IS_QSPI_INSTRUCTION, IS_QSPI_INSTRUCTION_MODE, IS_QSPI_SIOO_MODE, QSPI_ADDRESS_NONE, QSPI_ALTERNATE_BYTES_NONE, QSPI_Config(), QSPI_DATA_NONE, QSPI_FLAG_BUSY, QSPI_FLAG_TC, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE, QSPI_INSTRUCTION_NONE, QSPI_WaitFlagStateUntilTimeout(), QSPI_CommandTypeDef::SIOOMode, and __QSPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_QSPI_Command_IT | ( | QSPI_HandleTypeDef * | hqspi,
 |  | QSPI_CommandTypeDef * | cmd
 | ) |  |

Set the command configuration in interrupt mode.

Parameters:
hqspi | : QSPI handle
cmd | : structure that contains the command configuration information
Note:
This function is used only in Indirect Read or Write Modes
Return values:
HAL status

Definition at line 862 of file stm32wbxx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_ENABLE_IT, QSPI_CommandTypeDef::AddressMode, QSPI_CommandTypeDef::AddressSize, QSPI_CommandTypeDef::AlternateByteMode, QSPI_CommandTypeDef::AlternateBytesSize, assert_param, QSPI_CommandTypeDef::DataMode, QSPI_CommandTypeDef::DdrMode, QSPI_CommandTypeDef::DummyCycles, __QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY, HAL_QSPI_STATE_READY, QSPI_CommandTypeDef::Instruction, QSPI_CommandTypeDef::InstructionMode, IS_QSPI_ADDRESS_MODE, IS_QSPI_ADDRESS_SIZE, IS_QSPI_ALTERNATE_BYTES_MODE, IS_QSPI_ALTERNATE_BYTES_SIZE, IS_QSPI_DATA_MODE, IS_QSPI_DDR_MODE, IS_QSPI_DUMMY_CYCLES, IS_QSPI_INSTRUCTION, IS_QSPI_INSTRUCTION_MODE, IS_QSPI_SIOO_MODE, QSPI_ADDRESS_NONE, QSPI_ALTERNATE_BYTES_NONE, QSPI_Config(), QSPI_DATA_NONE, QSPI_FLAG_BUSY, QSPI_FLAG_TC, QSPI_FLAG_TE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE, QSPI_INSTRUCTION_NONE, QSPI_IT_TC, QSPI_IT_TE, QSPI_WaitFlagStateUntilTimeout(), QSPI_CommandTypeDef::SIOOMode, __QSPI_HandleTypeDef::State, and __QSPI_HandleTypeDef::Timeout.

void HAL_QSPI_ErrorCallback ( QSPI_HandleTypeDef * hqspi )

Transfer Error callback.

Parameters:
hqspi : QSPI handle
Return values:
None

Definition at line 1834 of file stm32wbxx_hal_qspi.c.

Referenced by HAL_QSPI_Init(), HAL_QSPI_IRQHandler(), HAL_QSPI_UnRegisterCallback(), and QSPI_DMAAbortCplt().

void HAL_QSPI_FifoThresholdCallback ( QSPI_HandleTypeDef * hqspi )

FIFO Threshold callback.

Parameters:
hqspi : QSPI handle
Return values:
None

Definition at line 1939 of file stm32wbxx_hal_qspi.c.

Referenced by HAL_QSPI_Init(), HAL_QSPI_IRQHandler(), and HAL_QSPI_UnRegisterCallback().

void HAL_QSPI_IRQHandler ( QSPI_HandleTypeDef * hqspi )

Handle QSPI interrupt request.

Parameters:
hqspi : QSPI handle
Return values:
None

Definition at line 485 of file stm32wbxx_hal_qspi.c.

References __HAL_DMA_DISABLE, __HAL_QSPI_DISABLE_IT, __HAL_QSPI_GET_FLAG, __QSPI_HandleTypeDef::AbortCpltCallback, __QSPI_HandleTypeDef::CmdCpltCallback, __QSPI_HandleTypeDef::ErrorCallback, __QSPI_HandleTypeDef::ErrorCode, __QSPI_HandleTypeDef::FifoThresholdCallback, HAL_DMA_Abort_IT(), HAL_QSPI_AbortCpltCallback(), HAL_QSPI_CmdCpltCallback(), HAL_QSPI_ERROR_DMA, HAL_QSPI_ERROR_NONE, HAL_QSPI_ERROR_TRANSFER, HAL_QSPI_ErrorCallback(), HAL_QSPI_FifoThresholdCallback(), HAL_QSPI_RxCpltCallback(), HAL_QSPI_STATE_ABORT, HAL_QSPI_STATE_BUSY, HAL_QSPI_STATE_BUSY_INDIRECT_RX, HAL_QSPI_STATE_BUSY_INDIRECT_TX, HAL_QSPI_STATE_READY, HAL_QSPI_StatusMatchCallback(), HAL_QSPI_TimeOutCallback(), HAL_QSPI_TxCpltCallback(), __QSPI_HandleTypeDef::hdma, __QSPI_HandleTypeDef::Instance, __QSPI_HandleTypeDef::pRxBuffPtr, __QSPI_HandleTypeDef::pTxBuffPtr, QSPI_DMAAbortCplt(), QSPI_FLAG_FT, QSPI_FLAG_SM, QSPI_FLAG_TC, QSPI_FLAG_TE, QSPI_FLAG_TO, QSPI_IT_FT, QSPI_IT_SM, QSPI_IT_TC, QSPI_IT_TE, QSPI_IT_TO, __QSPI_HandleTypeDef::RxCpltCallback, __QSPI_HandleTypeDef::RxXferCount, __QSPI_HandleTypeDef::State, __QSPI_HandleTypeDef::StatusMatchCallback, __QSPI_HandleTypeDef::TimeOutCallback, __QSPI_HandleTypeDef::TxCpltCallback, __QSPI_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_QSPI_MemoryMapped | ( | QSPI_HandleTypeDef * | hqspi,
 |  | QSPI_CommandTypeDef * | cmd,
 |  | QSPI_MemoryMappedTypeDef * | cfg
 | ) |  |

Configure the Memory Mapped mode.

Parameters:
hqspi | : QSPI handle
cmd | : structure that contains the command configuration information.
cfg | : structure that contains the memory mapped configuration information.
Note:
This function is used only in Memory mapped Mode
Return values:
HAL status

Definition at line 1749 of file stm32wbxx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_ENABLE_IT, QSPI_CommandTypeDef::AddressMode, QSPI_CommandTypeDef::AddressSize, QSPI_CommandTypeDef::AlternateByteMode, QSPI_CommandTypeDef::AlternateBytesSize, assert_param, QSPI_CommandTypeDef::DataMode, QSPI_CommandTypeDef::DdrMode, QSPI_CommandTypeDef::DummyCycles, __QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_MEM_MAPPED, HAL_QSPI_STATE_READY, __QSPI_HandleTypeDef::Instance, QSPI_CommandTypeDef::Instruction, QSPI_CommandTypeDef::InstructionMode, IS_QSPI_ADDRESS_MODE, IS_QSPI_ADDRESS_SIZE, IS_QSPI_ALTERNATE_BYTES_MODE, IS_QSPI_ALTERNATE_BYTES_SIZE, IS_QSPI_DATA_MODE, IS_QSPI_DDR_MODE, IS_QSPI_DUMMY_CYCLES, IS_QSPI_INSTRUCTION, IS_QSPI_INSTRUCTION_MODE, IS_QSPI_SIOO_MODE, IS_QSPI_TIMEOUT_ACTIVATION, IS_QSPI_TIMEOUT_PERIOD, QSPI_ADDRESS_NONE, QSPI_ALTERNATE_BYTES_NONE, QSPI_Config(), QSPI_FLAG_BUSY, QSPI_FLAG_TO, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED, QSPI_INSTRUCTION_NONE, QSPI_IT_TO, QSPI_TIMEOUT_COUNTER_ENABLE, QSPI_WaitFlagStateUntilTimeout(), QSPI_CommandTypeDef::SIOOMode, __QSPI_HandleTypeDef::State, __QSPI_HandleTypeDef::Timeout, QSPI_MemoryMappedTypeDef::TimeOutActivation, and QSPI_MemoryMappedTypeDef::TimeOutPeriod.

HAL_StatusTypeDef HAL_QSPI_Receive | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint8_t * | pData,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hqspi | : QSPI handle
pData | : pointer to data buffer
Timeout | : Timeout duration
Note:
This function is used only in Indirect Read Mode
Return values:
HAL status

Definition at line 1044 of file stm32wbxx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_QSPI_ERROR_INVALID_PARAM, HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_INDIRECT_RX, HAL_QSPI_STATE_READY, __QSPI_HandleTypeDef::Instance, __QSPI_HandleTypeDef::pRxBuffPtr, QSPI_FLAG_FT, QSPI_FLAG_TC, QSPI_FUNCTIONAL_MODE_INDIRECT_READ, QSPI_WaitFlagStateUntilTimeout(), __QSPI_HandleTypeDef::RxXferCount, __QSPI_HandleTypeDef::RxXferSize, and __QSPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_QSPI_Receive_DMA | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint8_t * | pData
 | ) |  |

Receive an amount of data in non-blocking mode with DMA.

Parameters:
hqspi | : QSPI handle
pData | : pointer to data buffer.
Note:
This function is used only in Indirect Read Mode
If DMA peripheral access is configured as halfword, the number of data and the fifo threshold should be aligned on halfword
If DMA peripheral access is configured as word, the number of data and the fifo threshold should be aligned on word
Return values:
HAL status

Definition at line 1401 of file stm32wbxx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_ENABLE_IT, DMA_InitTypeDef::Direction, DMA_PDATAALIGN_BYTE, DMA_PDATAALIGN_HALFWORD, DMA_PDATAALIGN_WORD, DMA_PERIPH_TO_MEMORY, __QSPI_HandleTypeDef::ErrorCode, QSPI_InitTypeDef::FifoThreshold, HAL_DMA_Start_IT(), HAL_QSPI_ERROR_DMA, HAL_QSPI_ERROR_INVALID_PARAM, HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_INDIRECT_RX, HAL_QSPI_STATE_READY, __QSPI_HandleTypeDef::hdma, __QSPI_HandleTypeDef::Init, __DMA_HandleTypeDef::Init, __QSPI_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, DMA_InitTypeDef::PeriphDataAlignment, __QSPI_HandleTypeDef::pRxBuffPtr, QSPI_DMAError(), QSPI_DMARxCplt(), QSPI_DMARxHalfCplt(), QSPI_FLAG_TC, QSPI_FLAG_TE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ, QSPI_IT_TE, __QSPI_HandleTypeDef::RxXferCount, __QSPI_HandleTypeDef::RxXferSize, __QSPI_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_QSPI_Receive_IT | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint8_t * | pData
 | ) |  |

Receive an amount of data in non-blocking mode with interrupt.

Parameters:
hqspi | : QSPI handle
pData | : pointer to data buffer
Note:
This function is used only in Indirect Read Mode
Return values:
HAL status

Definition at line 1189 of file stm32wbxx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_ENABLE_IT, __QSPI_HandleTypeDef::ErrorCode, HAL_QSPI_ERROR_INVALID_PARAM, HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_INDIRECT_RX, HAL_QSPI_STATE_READY, __QSPI_HandleTypeDef::Instance, __QSPI_HandleTypeDef::pRxBuffPtr, QSPI_FLAG_TC, QSPI_FLAG_TE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ, QSPI_IT_FT, QSPI_IT_TC, QSPI_IT_TE, __QSPI_HandleTypeDef::RxXferCount, __QSPI_HandleTypeDef::RxXferSize, and __QSPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_QSPI_RegisterCallback | ( | QSPI_HandleTypeDef * | hqspi,
 |  | HAL_QSPI_CallbackIDTypeDef | CallbackId,
 |  | pQSPI_CallbackTypeDef | pCallback
 | ) |  |

Register a User QSPI Callback To be used instead of the weak (surcharged) predefined callback.

Parameters:
hqspi | : QSPI handle
CallbackId : ID of the callback to be registered This parameter can be one of the following values:
  • HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID
  • HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID
  • HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID
  • HAL_QSPI_CMD_CPLT_CB_ID QSPI Command Complete Callback ID
  • HAL_QSPI_RX_CPLT_CB_ID QSPI Rx Complete Callback ID
  • HAL_QSPI_TX_CPLT_CB_ID QSPI Tx Complete Callback ID
  • HAL_QSPI_RX_HALF_CPLT_CB_ID QSPI Rx Half Complete Callback ID
  • HAL_QSPI_TX_HALF_CPLT_CB_ID QSPI Tx Half Complete Callback ID
  • HAL_QSPI_STATUS_MATCH_CB_ID QSPI Status Match Callback ID
  • HAL_QSPI_TIMEOUT_CB_ID QSPI Timeout Callback ID
  • HAL_QSPI_MSP_INIT_CB_ID QSPI MspInit callback ID
  • HAL_QSPI_MSP_DEINIT_CB_ID QSPI MspDeInit callback ID
pCallback | : pointer to the Callback function
Return values:
status

Definition at line 2000 of file stm32wbxx_hal_qspi.c.

References __QSPI_HandleTypeDef::AbortCpltCallback, __QSPI_HandleTypeDef::CmdCpltCallback, __QSPI_HandleTypeDef::ErrorCallback, __QSPI_HandleTypeDef::ErrorCode, __QSPI_HandleTypeDef::FifoThresholdCallback, HAL_QSPI_ABORT_CB_ID, HAL_QSPI_CMD_CPLT_CB_ID, HAL_QSPI_ERROR_CB_ID, HAL_QSPI_ERROR_INVALID_CALLBACK, HAL_QSPI_FIFO_THRESHOLD_CB_ID, HAL_QSPI_MSP_DEINIT_CB_ID, HAL_QSPI_MSP_INIT_CB_ID, HAL_QSPI_RX_CPLT_CB_ID, HAL_QSPI_RX_HALF_CPLT_CB_ID, HAL_QSPI_STATE_READY, HAL_QSPI_STATE_RESET, HAL_QSPI_STATUS_MATCH_CB_ID, HAL_QSPI_TIMEOUT_CB_ID, HAL_QSPI_TX_CPLT_CB_ID, HAL_QSPI_TX_HALF_CPLT_CB_ID, __QSPI_HandleTypeDef::MspDeInitCallback, __QSPI_HandleTypeDef::MspInitCallback, __QSPI_HandleTypeDef::RxCpltCallback, __QSPI_HandleTypeDef::RxHalfCpltCallback, __QSPI_HandleTypeDef::State, __QSPI_HandleTypeDef::StatusMatchCallback, __QSPI_HandleTypeDef::TimeOutCallback, __QSPI_HandleTypeDef::TxCpltCallback, and __QSPI_HandleTypeDef::TxHalfCpltCallback.

void HAL_QSPI_RxCpltCallback ( QSPI_HandleTypeDef * hqspi )

Rx Transfer completed callback.

Parameters:
hqspi : QSPI handle
Return values:
None

Definition at line 1879 of file stm32wbxx_hal_qspi.c.

Referenced by HAL_QSPI_Init(), HAL_QSPI_IRQHandler(), and HAL_QSPI_UnRegisterCallback().

void HAL_QSPI_RxHalfCpltCallback ( QSPI_HandleTypeDef * hqspi )

Rx Half Transfer completed callback.

Parameters:
hqspi : QSPI handle
Return values:
None

Definition at line 1909 of file stm32wbxx_hal_qspi.c.

Referenced by HAL_QSPI_Init(), HAL_QSPI_UnRegisterCallback(), and QSPI_DMARxHalfCplt().

void HAL_QSPI_StatusMatchCallback ( QSPI_HandleTypeDef * hqspi )

Status Match callback.

Parameters:
hqspi : QSPI handle
Return values:
None

Definition at line 1954 of file stm32wbxx_hal_qspi.c.

Referenced by HAL_QSPI_Init(), HAL_QSPI_IRQHandler(), and HAL_QSPI_UnRegisterCallback().

void HAL_QSPI_TimeOutCallback ( QSPI_HandleTypeDef * hqspi )

Timeout callback.

Parameters:
hqspi : QSPI handle
Return values:
None

Definition at line 1969 of file stm32wbxx_hal_qspi.c.

Referenced by HAL_QSPI_Init(), HAL_QSPI_IRQHandler(), and HAL_QSPI_UnRegisterCallback().

HAL_StatusTypeDef HAL_QSPI_Transmit | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint8_t * | pData,
 |  | uint32_t | Timeout
 | ) |  |

Transmit an amount of data in blocking mode.

Parameters:
hqspi | : QSPI handle
pData | : pointer to data buffer
Timeout | : Timeout duration
Note:
This function is used only in Indirect Write Mode
Return values:
HAL status

Definition at line 961 of file stm32wbxx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_QSPI_ERROR_INVALID_PARAM, HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_INDIRECT_TX, HAL_QSPI_STATE_READY, __QSPI_HandleTypeDef::Instance, __QSPI_HandleTypeDef::pTxBuffPtr, QSPI_FLAG_FT, QSPI_FLAG_TC, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE, QSPI_WaitFlagStateUntilTimeout(), __QSPI_HandleTypeDef::State, __QSPI_HandleTypeDef::TxXferCount, and __QSPI_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_QSPI_Transmit_DMA | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint8_t * | pData
 | ) |  |

Send an amount of data in non-blocking mode with DMA.

Parameters:
hqspi | : QSPI handle
pData | : pointer to data buffer
Note:
This function is used only in Indirect Write Mode
If DMA peripheral access is configured as halfword, the number of data and the fifo threshold should be aligned on halfword
If DMA peripheral access is configured as word, the number of data and the fifo threshold should be aligned on word
Return values:
HAL status

Definition at line 1257 of file stm32wbxx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_ENABLE_IT, DMA_InitTypeDef::Direction, DMA_MEMORY_TO_PERIPH, DMA_PDATAALIGN_BYTE, DMA_PDATAALIGN_HALFWORD, DMA_PDATAALIGN_WORD, __QSPI_HandleTypeDef::ErrorCode, QSPI_InitTypeDef::FifoThreshold, HAL_DMA_Start_IT(), HAL_QSPI_ERROR_DMA, HAL_QSPI_ERROR_INVALID_PARAM, HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_INDIRECT_TX, HAL_QSPI_STATE_READY, __QSPI_HandleTypeDef::hdma, __QSPI_HandleTypeDef::Init, __DMA_HandleTypeDef::Init, __QSPI_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, DMA_InitTypeDef::PeriphDataAlignment, __QSPI_HandleTypeDef::pTxBuffPtr, QSPI_DMAError(), QSPI_DMATxCplt(), QSPI_DMATxHalfCplt(), QSPI_FLAG_TC, QSPI_FLAG_TE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE, QSPI_IT_TE, __QSPI_HandleTypeDef::State, __QSPI_HandleTypeDef::TxXferCount, __QSPI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_QSPI_Transmit_IT | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint8_t * | pData
 | ) |  |

Send an amount of data in non-blocking mode with interrupt.

Parameters:
hqspi | : QSPI handle
pData | : pointer to data buffer
Note:
This function is used only in Indirect Write Mode
Return values:
HAL status

Definition at line 1129 of file stm32wbxx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_ENABLE_IT, __QSPI_HandleTypeDef::ErrorCode, HAL_QSPI_ERROR_INVALID_PARAM, HAL_QSPI_ERROR_NONE, HAL_QSPI_STATE_BUSY_INDIRECT_TX, HAL_QSPI_STATE_READY, __QSPI_HandleTypeDef::Instance, __QSPI_HandleTypeDef::pTxBuffPtr, QSPI_FLAG_TC, QSPI_FLAG_TE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE, QSPI_IT_FT, QSPI_IT_TC, QSPI_IT_TE, __QSPI_HandleTypeDef::State, __QSPI_HandleTypeDef::TxXferCount, and __QSPI_HandleTypeDef::TxXferSize.

void HAL_QSPI_TxCpltCallback ( QSPI_HandleTypeDef * hqspi )

Tx Transfer completed callback.

Parameters:
hqspi : QSPI handle
Return values:
None

Definition at line 1894 of file stm32wbxx_hal_qspi.c.

Referenced by HAL_QSPI_Init(), HAL_QSPI_IRQHandler(), and HAL_QSPI_UnRegisterCallback().

void HAL_QSPI_TxHalfCpltCallback ( QSPI_HandleTypeDef * hqspi )

Tx Half Transfer completed callback.

Parameters:
hqspi : QSPI handle
Return values:
None

Definition at line 1924 of file stm32wbxx_hal_qspi.c.

Referenced by HAL_QSPI_Init(), HAL_QSPI_UnRegisterCallback(), and QSPI_DMATxHalfCplt().

HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback | ( | QSPI_HandleTypeDef * | hqspi,
 |  | HAL_QSPI_CallbackIDTypeDef | CallbackId
 | ) |  |

Unregister a User QSPI Callback QSPI Callback is redirected to the weak (surcharged) predefined callback.

Parameters:
hqspi : QSPI handle
CallbackId : ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID
  • HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID
  • HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID
  • HAL_QSPI_CMD_CPLT_CB_ID QSPI Command Complete Callback ID
  • HAL_QSPI_RX_CPLT_CB_ID QSPI Rx Complete Callback ID
  • HAL_QSPI_TX_CPLT_CB_ID QSPI Tx Complete Callback ID
  • HAL_QSPI_RX_HALF_CPLT_CB_ID QSPI Rx Half Complete Callback ID
  • HAL_QSPI_TX_HALF_CPLT_CB_ID QSPI Tx Half Complete Callback ID
  • HAL_QSPI_STATUS_MATCH_CB_ID QSPI Status Match Callback ID
  • HAL_QSPI_TIMEOUT_CB_ID QSPI Timeout Callback ID
  • HAL_QSPI_MSP_INIT_CB_ID QSPI MspInit callback ID
  • HAL_QSPI_MSP_DEINIT_CB_ID QSPI MspDeInit callback ID
Return values:
status

Definition at line 2113 of file stm32wbxx_hal_qspi.c.

References __QSPI_HandleTypeDef::AbortCpltCallback, __QSPI_HandleTypeDef::CmdCpltCallback, __QSPI_HandleTypeDef::ErrorCallback, __QSPI_HandleTypeDef::ErrorCode, __QSPI_HandleTypeDef::FifoThresholdCallback, HAL_QSPI_ABORT_CB_ID, HAL_QSPI_AbortCpltCallback(), HAL_QSPI_CMD_CPLT_CB_ID, HAL_QSPI_CmdCpltCallback(), HAL_QSPI_ERROR_CB_ID, HAL_QSPI_ERROR_INVALID_CALLBACK, HAL_QSPI_ErrorCallback(), HAL_QSPI_FIFO_THRESHOLD_CB_ID, HAL_QSPI_FifoThresholdCallback(), HAL_QSPI_MSP_DEINIT_CB_ID, HAL_QSPI_MSP_INIT_CB_ID, HAL_QSPI_MspDeInit(), HAL_QSPI_MspInit(), HAL_QSPI_RX_CPLT_CB_ID, HAL_QSPI_RX_HALF_CPLT_CB_ID, HAL_QSPI_RxCpltCallback(), HAL_QSPI_RxHalfCpltCallback(), HAL_QSPI_STATE_READY, HAL_QSPI_STATE_RESET, HAL_QSPI_STATUS_MATCH_CB_ID, HAL_QSPI_StatusMatchCallback(), HAL_QSPI_TIMEOUT_CB_ID, HAL_QSPI_TimeOutCallback(), HAL_QSPI_TX_CPLT_CB_ID, HAL_QSPI_TX_HALF_CPLT_CB_ID, HAL_QSPI_TxCpltCallback(), HAL_QSPI_TxHalfCpltCallback(), __QSPI_HandleTypeDef::MspDeInitCallback, __QSPI_HandleTypeDef::MspInitCallback, __QSPI_HandleTypeDef::RxCpltCallback, __QSPI_HandleTypeDef::RxHalfCpltCallback, __QSPI_HandleTypeDef::State, __QSPI_HandleTypeDef::StatusMatchCallback, __QSPI_HandleTypeDef::TimeOutCallback, __QSPI_HandleTypeDef::TxCpltCallback, and __QSPI_HandleTypeDef::TxHalfCpltCallback.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Peripheral Control and State functions

Functions
Peripheral Control and State functions
QSPI Exported Functions

QSPI control and State functions. More...

Functions

HAL_QSPI_StateTypeDef | HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi)
Return the QSPI handle state.
uint32_t | HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi)
Return the QSPI error code.
HAL_StatusTypeDef | HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi)
Abort the current transmission.
HAL_StatusTypeDef | HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi)
Abort the current transmission (non-blocking function)
void | HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
Set QSPI timeout.
HAL_StatusTypeDef | HAL_QSPI_SetFifoThreshold (QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
Set QSPI Fifo threshold.
uint32_t | HAL_QSPI_GetFifoThreshold (QSPI_HandleTypeDef *hqspi)
Get QSPI Fifo threshold.

Detailed Description

QSPI control and State functions.

 ===============================================================================
                  ##### Peripheral Control and State functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to :
      (+) Check in run-time the state of the driver.
      (+) Check the error code set during last operation.
      (+) Abort any operation.

Function Documentation

HAL_StatusTypeDef HAL_QSPI_Abort ( QSPI_HandleTypeDef * hqspi )

Abort the current transmission.

Parameters:
hqspi : QSPI handle
Return values:
HAL status

Definition at line 2248 of file stm32wbxx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __QSPI_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_GetTick(), HAL_QSPI_ERROR_DMA, HAL_QSPI_STATE_READY, __QSPI_HandleTypeDef::hdma, __QSPI_HandleTypeDef::Instance, QSPI_FLAG_BUSY, QSPI_FLAG_TC, QSPI_WaitFlagStateUntilTimeout(), __QSPI_HandleTypeDef::State, and __QSPI_HandleTypeDef::Timeout.

HAL_StatusTypeDef HAL_QSPI_Abort_IT ( QSPI_HandleTypeDef * hqspi )

Abort the current transmission (non-blocking function)

Parameters:
hqspi : QSPI handle
Return values:
HAL status

Definition at line 2304 of file stm32wbxx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_DISABLE_IT, __HAL_QSPI_ENABLE_IT, __QSPI_HandleTypeDef::AbortCpltCallback, HAL_DMA_Abort_IT(), HAL_QSPI_AbortCpltCallback(), HAL_QSPI_STATE_ABORT, HAL_QSPI_STATE_READY, __QSPI_HandleTypeDef::hdma, __QSPI_HandleTypeDef::Instance, QSPI_DMAAbortCplt(), QSPI_FLAG_TC, QSPI_IT_FT, QSPI_IT_SM, QSPI_IT_TC, QSPI_IT_TE, QSPI_IT_TO, __QSPI_HandleTypeDef::State, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by QSPI_DMAError().

uint32_t HAL_QSPI_GetError ( QSPI_HandleTypeDef * hqspi )

Return the QSPI error code.

Parameters:
hqspi : QSPI handle
Return values:
QSPI Error Code

Definition at line 2238 of file stm32wbxx_hal_qspi.c.

References __QSPI_HandleTypeDef::ErrorCode.

uint32_t HAL_QSPI_GetFifoThreshold ( QSPI_HandleTypeDef * hqspi )

Get QSPI Fifo threshold.

Parameters:
hqspi : QSPI handle.
Return values:
Fifo threshold (value between 1 and 16)

Definition at line 2402 of file stm32wbxx_hal_qspi.c.

References __QSPI_HandleTypeDef::Instance.

HAL_QSPI_StateTypeDef HAL_QSPI_GetState ( QSPI_HandleTypeDef * hqspi )

Return the QSPI handle state.

Parameters:
hqspi : QSPI handle
Return values:
HAL state

Definition at line 2227 of file stm32wbxx_hal_qspi.c.

References __QSPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint32_t | Threshold
 | ) |  |

Set QSPI Fifo threshold.

Parameters:
hqspi | : QSPI handle.
Threshold | : Threshold of the Fifo (value between 1 and 16).
Return values:
HAL status

Definition at line 2370 of file stm32wbxx_hal_qspi.c.

References QSPI_InitTypeDef::FifoThreshold, HAL_QSPI_STATE_READY, __QSPI_HandleTypeDef::Init, __QSPI_HandleTypeDef::Instance, and __QSPI_HandleTypeDef::State.

void HAL_QSPI_SetTimeout | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint32_t | Timeout
 | ) |  |

Set QSPI timeout.

Parameters:
hqspi | : QSPI handle.
Timeout | : Timeout for the QSPI memory access.
Return values:
None

Definition at line 2360 of file stm32wbxx_hal_qspi.c.

References __QSPI_HandleTypeDef::Timeout.

Referenced by HAL_QSPI_Init().

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: QSPI Private Functions

Functions
QSPI Private Functions
QSPI

Functions

static void | QSPI_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA QSPI receive process complete callback.
static void | QSPI_DMATxCplt (DMA_HandleTypeDef *hdma)
DMA QSPI transmit process complete callback.
static void | QSPI_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA QSPI receive process half complete callback.
static void | QSPI_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA QSPI transmit process half complete callback.
static void | QSPI_DMAError (DMA_HandleTypeDef *hdma)
DMA QSPI communication error callback.
static void | QSPI_DMAAbortCplt (DMA_HandleTypeDef *hdma)
DMA QSPI abort complete callback.
static HAL_StatusTypeDef | QSPI_WaitFlagStateUntilTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout)
Wait for a flag state until timeout.
static void | QSPI_Config (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)
Configure the communication registers.

Function Documentation

static void QSPI_Config | ( | QSPI_HandleTypeDef * | hqspi,
 |  | QSPI_CommandTypeDef * | cmd,
 |  | uint32_t | FunctionalMode
 | ) |  | [static]

Configure the communication registers.

Parameters:
hqspi | : QSPI handle
cmd | : structure that contains the command configuration information
FunctionalMode : functional mode to configured This parameter can be one of the following values:
  • QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
  • QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
  • QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
  • QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
Return values:
None

Definition at line 2581 of file stm32wbxx_hal_qspi.c.

References QSPI_CommandTypeDef::Address, QSPI_CommandTypeDef::AddressMode, QSPI_CommandTypeDef::AddressSize, QSPI_CommandTypeDef::AlternateByteMode, QSPI_CommandTypeDef::AlternateBytes, QSPI_CommandTypeDef::AlternateBytesSize, assert_param, QSPI_CommandTypeDef::DataMode, QSPI_CommandTypeDef::DdrMode, QSPI_CommandTypeDef::DummyCycles, __QSPI_HandleTypeDef::Instance, QSPI_CommandTypeDef::Instruction, QSPI_CommandTypeDef::InstructionMode, IS_QSPI_FUNCTIONAL_MODE, QSPI_CommandTypeDef::NbData, QSPI_ADDRESS_NONE, QSPI_ALTERNATE_BYTES_NONE, QSPI_DATA_NONE, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED, QSPI_INSTRUCTION_NONE, and QSPI_CommandTypeDef::SIOOMode.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and HAL_QSPI_MemoryMapped().

static void QSPI_DMAAbortCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA QSPI abort complete callback.

Parameters:
hdma : DMA handle
Return values:
None

Definition at line 2505 of file stm32wbxx_hal_qspi.c.

References __HAL_QSPI_CLEAR_FLAG, __HAL_QSPI_ENABLE_IT, __QSPI_HandleTypeDef::ErrorCallback, HAL_QSPI_ErrorCallback(), HAL_QSPI_STATE_ABORT, HAL_QSPI_STATE_READY, __QSPI_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, QSPI_FLAG_TC, QSPI_IT_TC, __QSPI_HandleTypeDef::RxXferCount, __QSPI_HandleTypeDef::State, and __QSPI_HandleTypeDef::TxXferCount.

Referenced by HAL_QSPI_Abort_IT(), and HAL_QSPI_IRQHandler().

static void QSPI_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA QSPI communication error callback.

Parameters:
hdma : DMA handle
Return values:
None

Definition at line 2484 of file stm32wbxx_hal_qspi.c.

References __QSPI_HandleTypeDef::ErrorCode, HAL_QSPI_Abort_IT(), HAL_QSPI_ERROR_DMA, __QSPI_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, __QSPI_HandleTypeDef::RxXferCount, and __QSPI_HandleTypeDef::TxXferCount.

Referenced by HAL_QSPI_Receive_DMA(), and HAL_QSPI_Transmit_DMA().

static void QSPI_DMARxCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA QSPI receive process complete callback.

Parameters:
hdma : DMA handle
Return values:
None

Definition at line 2424 of file stm32wbxx_hal_qspi.c.

References __HAL_QSPI_ENABLE_IT, __DMA_HandleTypeDef::Parent, QSPI_IT_TC, and __QSPI_HandleTypeDef::RxXferCount.

Referenced by HAL_QSPI_Receive_DMA().

static void QSPI_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA QSPI receive process half complete callback.

Parameters:
hdma : DMA handle
Return values:
None

Definition at line 2452 of file stm32wbxx_hal_qspi.c.

References HAL_QSPI_RxHalfCpltCallback(), __DMA_HandleTypeDef::Parent, and __QSPI_HandleTypeDef::RxHalfCpltCallback.

Referenced by HAL_QSPI_Receive_DMA().

static void QSPI_DMATxCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA QSPI transmit process complete callback.

Parameters:
hdma : DMA handle
Return values:
None

Definition at line 2438 of file stm32wbxx_hal_qspi.c.

References __HAL_QSPI_ENABLE_IT, __DMA_HandleTypeDef::Parent, QSPI_IT_TC, and __QSPI_HandleTypeDef::TxXferCount.

Referenced by HAL_QSPI_Transmit_DMA().

static void QSPI_DMATxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA QSPI transmit process half complete callback.

Parameters:
hdma : DMA handle
Return values:
None

Definition at line 2468 of file stm32wbxx_hal_qspi.c.

References HAL_QSPI_TxHalfCpltCallback(), __DMA_HandleTypeDef::Parent, and __QSPI_HandleTypeDef::TxHalfCpltCallback.

Referenced by HAL_QSPI_Transmit_DMA().

static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout | ( | QSPI_HandleTypeDef * | hqspi,
 |  | uint32_t | Flag,
 |  | FlagStatus | State,
 |  | uint32_t | Tickstart,
 |  | uint32_t | Timeout
 | ) |  | [static]

Wait for a flag state until timeout.

Parameters:
hqspi | : QSPI handle
Flag | : Flag checked
State | : Value of the flag expected
Tickstart | : Tick start value
Timeout | : Duration of the timeout
Return values:
HAL status

Definition at line 2548 of file stm32wbxx_hal_qspi.c.

References __HAL_QSPI_GET_FLAG, __QSPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_QSPI_ERROR_TIMEOUT, HAL_QSPI_STATE_ERROR, and __QSPI_HandleTypeDef::State.

Referenced by HAL_QSPI_Abort(), HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_Init(), HAL_QSPI_MemoryMapped(), HAL_QSPI_Receive(), and HAL_QSPI_Transmit().

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: QSPI Exported Types

Data Structures | Typedefs | Enumerations
QSPI Exported Types
QSPI

Data Structures

struct | QSPI_InitTypeDef
QSPI Init structure definition. More...
struct | __QSPI_HandleTypeDef
QSPI Handle Structure definition. More...
struct | QSPI_CommandTypeDef
QSPI Command structure definition. More...
struct | QSPI_AutoPollingTypeDef
QSPI Auto Polling mode configuration structure definition. More...
struct | QSPI_MemoryMappedTypeDef
QSPI Memory Mapped mode configuration structure definition. More...

Typedefs

typedef struct __QSPI_HandleTypeDef | QSPI_HandleTypeDef
QSPI Handle Structure definition.
typedef void(* | pQSPI_CallbackTypeDef )(QSPI_HandleTypeDef *hqspi)
HAL QSPI Callback pointer definition.

Enumerations

enum HAL_QSPI_StateTypeDef {
HAL_QSPI_STATE_RESET = 0x00U, HAL_QSPI_STATE_READY = 0x01U, HAL_QSPI_STATE_BUSY = 0x02U, HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U,
HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, HAL_QSPI_STATE_ABORT = 0x08U,
HAL_QSPI_STATE_ERROR = 0x04U
}
HAL QSPI State structures definition. More...
enum HAL_QSPI_CallbackIDTypeDef {
HAL_QSPI_ERROR_CB_ID = 0x00U, HAL_QSPI_ABORT_CB_ID = 0x01U, HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U, HAL_QSPI_CMD_CPLT_CB_ID = 0x03U,
HAL_QSPI_RX_CPLT_CB_ID = 0x04U, HAL_QSPI_TX_CPLT_CB_ID = 0x05U, HAL_QSPI_RX_HALF_CPLT_CB_ID = 0x06U, HAL_QSPI_TX_HALF_CPLT_CB_ID = 0x07U,
HAL_QSPI_STATUS_MATCH_CB_ID = 0x08U, HAL_QSPI_TIMEOUT_CB_ID = 0x09U, HAL_QSPI_MSP_INIT_CB_ID = 0x0AU, HAL_QSPI_MSP_DEINIT_CB_ID = 0x0B0
}
HAL QSPI Callback ID enumeration definition. More...

Typedef Documentation

typedef void(* pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi)

HAL QSPI Callback pointer definition.

Definition at line 212 of file stm32wbxx_hal_qspi.h.

typedef struct __QSPI_HandleTypeDef QSPI_HandleTypeDef

QSPI Handle Structure definition.

Enumeration Type Documentation

enum HAL_QSPI_CallbackIDTypeDef

HAL QSPI Callback ID enumeration definition.

Enumerator:
HAL_QSPI_ERROR_CB_ID

QSPI Error Callback ID

HAL_QSPI_ABORT_CB_ID

QSPI Abort Callback ID

HAL_QSPI_FIFO_THRESHOLD_CB_ID

QSPI FIFO Threshold Callback ID

HAL_QSPI_CMD_CPLT_CB_ID

QSPI Command Complete Callback ID

HAL_QSPI_RX_CPLT_CB_ID

QSPI Rx Complete Callback ID

HAL_QSPI_TX_CPLT_CB_ID

QSPI Tx Complete Callback ID

HAL_QSPI_RX_HALF_CPLT_CB_ID

QSPI Rx Half Complete Callback ID

HAL_QSPI_TX_HALF_CPLT_CB_ID

QSPI Tx Half Complete Callback ID

HAL_QSPI_STATUS_MATCH_CB_ID

QSPI Status Match Callback ID

HAL_QSPI_TIMEOUT_CB_ID

QSPI Timeout Callback ID

HAL_QSPI_MSP_INIT_CB_ID

QSPI MspInit Callback ID

HAL_QSPI_MSP_DEINIT_CB_ID

QSPI MspDeInit Callback ID

Definition at line 192 of file stm32wbxx_hal_qspi.h.

enum HAL_QSPI_StateTypeDef

HAL QSPI State structures definition.

Enumerator:
HAL_QSPI_STATE_RESET

Peripheral not initialized

HAL_QSPI_STATE_READY

Peripheral initialized and ready for use

HAL_QSPI_STATE_BUSY

Peripheral in indirect mode and busy

HAL_QSPI_STATE_BUSY_INDIRECT_TX

Peripheral in indirect mode with transmission ongoing

HAL_QSPI_STATE_BUSY_INDIRECT_RX

Peripheral in indirect mode with reception ongoing

HAL_QSPI_STATE_BUSY_AUTO_POLLING

Peripheral in auto polling mode ongoing

HAL_QSPI_STATE_BUSY_MEM_MAPPED

Peripheral in memory mapped mode ongoing

HAL_QSPI_STATE_ABORT

Peripheral with abort request ongoing

HAL_QSPI_STATE_ERROR

Peripheral in error

Definition at line 72 of file stm32wbxx_hal_qspi.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: QSPI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
QSPI_InitTypeDef Struct Reference
QSPI Exported Types

QSPI Init structure definition. More...

#include <stm32wbxx_hal_qspi.h>

Data Fields

uint32_t | ClockPrescaler
uint32_t | FifoThreshold
uint32_t | SampleShifting
uint32_t | FlashSize
uint32_t | ChipSelectHighTime
uint32_t | ClockMode

Detailed Description

QSPI Init structure definition.

Definition at line 48 of file stm32wbxx_hal_qspi.h.

Field Documentation

uint32_t QSPI_InitTypeDef::ChipSelectHighTime

Definition at line 62 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

uint32_t QSPI_InitTypeDef::ClockMode

Definition at line 65 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

uint32_t QSPI_InitTypeDef::ClockPrescaler

Definition at line 50 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

uint32_t QSPI_InitTypeDef::FifoThreshold

Definition at line 52 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Init(), HAL_QSPI_Receive_DMA(), HAL_QSPI_SetFifoThreshold(), and HAL_QSPI_Transmit_DMA().

uint32_t QSPI_InitTypeDef::FlashSize

Definition at line 57 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

uint32_t QSPI_InitTypeDef::SampleShifting

Definition at line 54 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_qspi.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: __QSPI_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__QSPI_HandleTypeDef Struct Reference
QSPI Exported Types

QSPI Handle Structure definition. More...

#include <stm32wbxx_hal_qspi.h>

Data Fields

QUADSPI_TypeDef * | Instance
QSPI_InitTypeDef Init
uint8_t * | pTxBuffPtr
__IO uint32_t | TxXferSize
__IO uint32_t | TxXferCount
uint8_t * | pRxBuffPtr
__IO uint32_t | RxXferSize
__IO uint32_t | RxXferCount
DMA_HandleTypeDef * hdma
__IO HAL_LockTypeDef | Lock
__IO HAL_QSPI_StateTypeDef | State
__IO uint32_t | ErrorCode
uint32_t | Timeout
void(* | ErrorCallback )(struct __QSPI_HandleTypeDef *hqspi)
void(* | AbortCpltCallback )(struct __QSPI_HandleTypeDef *hqspi)
void(* | FifoThresholdCallback )(struct __QSPI_HandleTypeDef *hqspi)
void(* | CmdCpltCallback )(struct __QSPI_HandleTypeDef *hqspi)
void(* | RxCpltCallback )(struct __QSPI_HandleTypeDef *hqspi)
void(* | TxCpltCallback )(struct __QSPI_HandleTypeDef *hqspi)
void(* | RxHalfCpltCallback )(struct __QSPI_HandleTypeDef *hqspi)
void(* | TxHalfCpltCallback )(struct __QSPI_HandleTypeDef *hqspi)
void(* | StatusMatchCallback )(struct __QSPI_HandleTypeDef *hqspi)
void(* | TimeOutCallback )(struct __QSPI_HandleTypeDef *hqspi)
void(* | MspInitCallback )(struct __QSPI_HandleTypeDef *hqspi)
void(* | MspDeInitCallback )(struct __QSPI_HandleTypeDef *hqspi)

Detailed Description

QSPI Handle Structure definition.

Definition at line 89 of file stm32wbxx_hal_qspi.h.

Field Documentation

void(* __QSPI_HandleTypeDef::AbortCpltCallback)(struct __QSPI_HandleTypeDef *hqspi)

Definition at line 109 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Abort_IT(), HAL_QSPI_Init(), HAL_QSPI_IRQHandler(), HAL_QSPI_RegisterCallback(), and HAL_QSPI_UnRegisterCallback().

void(* __QSPI_HandleTypeDef::CmdCpltCallback)(struct __QSPI_HandleTypeDef *hqspi)

Definition at line 111 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Init(), HAL_QSPI_IRQHandler(), HAL_QSPI_RegisterCallback(), and HAL_QSPI_UnRegisterCallback().

void(* __QSPI_HandleTypeDef::ErrorCallback)(struct __QSPI_HandleTypeDef *hqspi)

Definition at line 108 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Init(), HAL_QSPI_IRQHandler(), HAL_QSPI_RegisterCallback(), HAL_QSPI_UnRegisterCallback(), and QSPI_DMAAbortCplt().

__IO uint32_t __QSPI_HandleTypeDef::ErrorCode

Definition at line 105 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Abort(), HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_DeInit(), HAL_QSPI_GetError(), HAL_QSPI_Init(), HAL_QSPI_IRQHandler(), HAL_QSPI_MemoryMapped(), HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Receive_IT(), HAL_QSPI_RegisterCallback(), HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), HAL_QSPI_Transmit_IT(), HAL_QSPI_UnRegisterCallback(), QSPI_DMAError(), and QSPI_WaitFlagStateUntilTimeout().

void(* __QSPI_HandleTypeDef::FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi)

Definition at line 110 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Init(), HAL_QSPI_IRQHandler(), HAL_QSPI_RegisterCallback(), and HAL_QSPI_UnRegisterCallback().

DMA_HandleTypeDef* __QSPI_HandleTypeDef::hdma

Definition at line 102 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Abort(), HAL_QSPI_Abort_IT(), HAL_QSPI_IRQHandler(), HAL_QSPI_Receive_DMA(), and HAL_QSPI_Transmit_DMA().

QSPI_InitTypeDef __QSPI_HandleTypeDef::Init

Definition at line 95 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Init(), HAL_QSPI_Receive_DMA(), HAL_QSPI_SetFifoThreshold(), and HAL_QSPI_Transmit_DMA().

QUADSPI_TypeDef* __QSPI_HandleTypeDef::Instance

Definition at line 94 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Abort(), HAL_QSPI_Abort_IT(), HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_GetFifoThreshold(), HAL_QSPI_Init(), HAL_QSPI_IRQHandler(), HAL_QSPI_MemoryMapped(), HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Receive_IT(), HAL_QSPI_SetFifoThreshold(), HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), HAL_QSPI_Transmit_IT(), QSPI_Config(), QSPI_DMAAbortCplt(), and QSPI_DMAError().

__IO HAL_LockTypeDef __QSPI_HandleTypeDef::Lock

Definition at line 103 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

void(* __QSPI_HandleTypeDef::MspDeInitCallback)(struct __QSPI_HandleTypeDef *hqspi)

Definition at line 120 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_DeInit(), HAL_QSPI_RegisterCallback(), and HAL_QSPI_UnRegisterCallback().

void(* __QSPI_HandleTypeDef::MspInitCallback)(struct __QSPI_HandleTypeDef *hqspi)

Definition at line 119 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Init(), HAL_QSPI_RegisterCallback(), and HAL_QSPI_UnRegisterCallback().

uint8_t* __QSPI_HandleTypeDef::pRxBuffPtr

Definition at line 99 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_IRQHandler(), HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), and HAL_QSPI_Receive_IT().

uint8_t* __QSPI_HandleTypeDef::pTxBuffPtr

Definition at line 96 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_IRQHandler(), HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), and HAL_QSPI_Transmit_IT().

void(* __QSPI_HandleTypeDef::RxCpltCallback)(struct __QSPI_HandleTypeDef *hqspi)

Definition at line 112 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Init(), HAL_QSPI_IRQHandler(), HAL_QSPI_RegisterCallback(), and HAL_QSPI_UnRegisterCallback().

void(* __QSPI_HandleTypeDef::RxHalfCpltCallback)(struct __QSPI_HandleTypeDef *hqspi)

Definition at line 114 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Init(), HAL_QSPI_RegisterCallback(), HAL_QSPI_UnRegisterCallback(), and QSPI_DMARxHalfCplt().

__IO uint32_t __QSPI_HandleTypeDef::RxXferCount

Definition at line 101 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_IRQHandler(), HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Receive_IT(), QSPI_DMAAbortCplt(), QSPI_DMAError(), and QSPI_DMARxCplt().

__IO uint32_t __QSPI_HandleTypeDef::RxXferSize

Definition at line 100 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), and HAL_QSPI_Receive_IT().

__IO HAL_QSPI_StateTypeDef __QSPI_HandleTypeDef::State

Definition at line 104 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Abort(), HAL_QSPI_Abort_IT(), HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_DeInit(), HAL_QSPI_GetState(), HAL_QSPI_Init(), HAL_QSPI_IRQHandler(), HAL_QSPI_MemoryMapped(), HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Receive_IT(), HAL_QSPI_RegisterCallback(), HAL_QSPI_SetFifoThreshold(), HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), HAL_QSPI_Transmit_IT(), HAL_QSPI_UnRegisterCallback(), QSPI_DMAAbortCplt(), and QSPI_WaitFlagStateUntilTimeout().

void(* __QSPI_HandleTypeDef::StatusMatchCallback)(struct __QSPI_HandleTypeDef *hqspi)

Definition at line 116 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Init(), HAL_QSPI_IRQHandler(), HAL_QSPI_RegisterCallback(), and HAL_QSPI_UnRegisterCallback().

uint32_t __QSPI_HandleTypeDef::Timeout

Definition at line 106 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Abort(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command_IT(), HAL_QSPI_Init(), HAL_QSPI_MemoryMapped(), and HAL_QSPI_SetTimeout().

void(* __QSPI_HandleTypeDef::TimeOutCallback)(struct __QSPI_HandleTypeDef *hqspi)

Definition at line 117 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Init(), HAL_QSPI_IRQHandler(), HAL_QSPI_RegisterCallback(), and HAL_QSPI_UnRegisterCallback().

void(* __QSPI_HandleTypeDef::TxCpltCallback)(struct __QSPI_HandleTypeDef *hqspi)

Definition at line 113 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Init(), HAL_QSPI_IRQHandler(), HAL_QSPI_RegisterCallback(), and HAL_QSPI_UnRegisterCallback().

void(* __QSPI_HandleTypeDef::TxHalfCpltCallback)(struct __QSPI_HandleTypeDef *hqspi)

Definition at line 115 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Init(), HAL_QSPI_RegisterCallback(), HAL_QSPI_UnRegisterCallback(), and QSPI_DMATxHalfCplt().

__IO uint32_t __QSPI_HandleTypeDef::TxXferCount

Definition at line 98 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_IRQHandler(), HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), HAL_QSPI_Transmit_IT(), QSPI_DMAAbortCplt(), QSPI_DMAError(), and QSPI_DMATxCplt().

__IO uint32_t __QSPI_HandleTypeDef::TxXferSize

Definition at line 97 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), and HAL_QSPI_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_qspi.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: QSPI_CommandTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
QSPI_CommandTypeDef Struct Reference
QSPI Exported Types

QSPI Command structure definition. More...

#include <stm32wbxx_hal_qspi.h>

Data Fields

uint32_t | Instruction
uint32_t | Address
uint32_t | AlternateBytes
uint32_t | AddressSize
uint32_t | AlternateBytesSize
uint32_t | DummyCycles
uint32_t | InstructionMode
uint32_t | AddressMode
uint32_t | AlternateByteMode
uint32_t | DataMode
uint32_t | NbData
uint32_t | DdrMode
uint32_t | SIOOMode

Detailed Description

QSPI Command structure definition.

Definition at line 127 of file stm32wbxx_hal_qspi.h.

Field Documentation

uint32_t QSPI_CommandTypeDef::Address

Definition at line 131 of file stm32wbxx_hal_qspi.h.

Referenced by QSPI_Config().

uint32_t QSPI_CommandTypeDef::AddressMode

Definition at line 143 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::AddressSize

Definition at line 135 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::AlternateByteMode

Definition at line 145 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::AlternateBytes

Definition at line 133 of file stm32wbxx_hal_qspi.h.

Referenced by QSPI_Config().

uint32_t QSPI_CommandTypeDef::AlternateBytesSize

Definition at line 137 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::DataMode

Definition at line 147 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::DdrMode

Definition at line 152 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::DummyCycles

Definition at line 139 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::Instruction

Definition at line 129 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::InstructionMode

Definition at line 141 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::NbData

Definition at line 149 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), and QSPI_Config().

uint32_t QSPI_CommandTypeDef::SIOOMode

Definition at line 154 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_qspi.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: QSPI_AutoPollingTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
QSPI_AutoPollingTypeDef Struct Reference
QSPI Exported Types

QSPI Auto Polling mode configuration structure definition. More...

#include <stm32wbxx_hal_qspi.h>

Data Fields

uint32_t | Match
uint32_t | Mask
uint32_t | Interval
uint32_t | StatusBytesSize
uint32_t | MatchMode
uint32_t | AutomaticStop

Detailed Description

QSPI Auto Polling mode configuration structure definition.

Definition at line 161 of file stm32wbxx_hal_qspi.h.

Field Documentation

uint32_t QSPI_AutoPollingTypeDef::AutomaticStop

Definition at line 173 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling_IT().

uint32_t QSPI_AutoPollingTypeDef::Interval

Definition at line 167 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), and HAL_QSPI_AutoPolling_IT().

uint32_t QSPI_AutoPollingTypeDef::Mask

Definition at line 165 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), and HAL_QSPI_AutoPolling_IT().

uint32_t QSPI_AutoPollingTypeDef::Match

Definition at line 163 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), and HAL_QSPI_AutoPolling_IT().

uint32_t QSPI_AutoPollingTypeDef::MatchMode

Definition at line 171 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), and HAL_QSPI_AutoPolling_IT().

uint32_t QSPI_AutoPollingTypeDef::StatusBytesSize

Definition at line 169 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), and HAL_QSPI_AutoPolling_IT().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_qspi.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: QSPI_MemoryMappedTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
QSPI_MemoryMappedTypeDef Struct Reference
QSPI Exported Types

QSPI Memory Mapped mode configuration structure definition. More...

#include <stm32wbxx_hal_qspi.h>

Data Fields

uint32_t | TimeOutPeriod
uint32_t | TimeOutActivation

Detailed Description

QSPI Memory Mapped mode configuration structure definition.

Definition at line 180 of file stm32wbxx_hal_qspi.h.

Field Documentation

uint32_t QSPI_MemoryMappedTypeDef::TimeOutActivation

Definition at line 184 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_MemoryMapped().

uint32_t QSPI_MemoryMappedTypeDef::TimeOutPeriod

Definition at line 182 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_MemoryMapped().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_qspi.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: QSPI Error Code

Defines
QSPI Error Code
QSPI Exported Constants

Defines

#define | HAL_QSPI_ERROR_NONE 0x00000000U
#define | HAL_QSPI_ERROR_TIMEOUT 0x00000001U
#define | HAL_QSPI_ERROR_TRANSFER 0x00000002U
#define | HAL_QSPI_ERROR_DMA 0x00000004U
#define | HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U
#define | HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U

Define Documentation

#define HAL_QSPI_ERROR_DMA 0x00000004U

DMA transfer error

Definition at line 229 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Abort(), HAL_QSPI_IRQHandler(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Transmit_DMA(), and QSPI_DMAError().

#define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U

Invalid callback error

Definition at line 232 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_RegisterCallback(), and HAL_QSPI_UnRegisterCallback().

#define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U

Invalid parameters error

Definition at line 230 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Receive_IT(), HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), and HAL_QSPI_Transmit_IT().

#define HAL_QSPI_ERROR_NONE 0x00000000U

No error

Definition at line 226 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_DeInit(), HAL_QSPI_Init(), HAL_QSPI_IRQHandler(), HAL_QSPI_MemoryMapped(), HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Receive_IT(), HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), and HAL_QSPI_Transmit_IT().

#define HAL_QSPI_ERROR_TIMEOUT 0x00000001U

Timeout error

Definition at line 227 of file stm32wbxx_hal_qspi.h.

Referenced by QSPI_WaitFlagStateUntilTimeout().

#define HAL_QSPI_ERROR_TRANSFER 0x00000002U

Transfer error

Definition at line 228 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_IRQHandler().

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STM32WB55xx HAL User Manual: QSPI Sample Shifting

Defines
QSPI Sample Shifting
QSPI Exported Constants

Defines

#define | QSPI_SAMPLE_SHIFTING_NONE 0x00000000U
#define | QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT)

Define Documentation

#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT)

1/2 clock cycle shift to sample data

Definition at line 242 of file stm32wbxx_hal_qspi.h.

#define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U

No clock cycle shift to sample data

Definition at line 241 of file stm32wbxx_hal_qspi.h.

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STM32WB55xx HAL User Manual: QSPI ChipSelect High Time

Defines
QSPI ChipSelect High Time
QSPI Exported Constants

Defines

#define | QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U
#define | QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0)
#define | QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1)
#define | QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1)
#define | QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2)
#define | QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0)
#define | QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1)
#define | QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT)

Define Documentation

#define QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U

nCS stay high for at least 1 clock cycle between commands

Definition at line 250 of file stm32wbxx_hal_qspi.h.

#define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0)

nCS stay high for at least 2 clock cycles between commands

Definition at line 251 of file stm32wbxx_hal_qspi.h.

#define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1)

nCS stay high for at least 3 clock cycles between commands

Definition at line 252 of file stm32wbxx_hal_qspi.h.

#define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1)

nCS stay high for at least 4 clock cycles between commands

Definition at line 253 of file stm32wbxx_hal_qspi.h.

#define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2)

nCS stay high for at least 5 clock cycles between commands

Definition at line 254 of file stm32wbxx_hal_qspi.h.

#define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0)

nCS stay high for at least 6 clock cycles between commands

Definition at line 255 of file stm32wbxx_hal_qspi.h.

#define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1)

nCS stay high for at least 7 clock cycles between commands

Definition at line 256 of file stm32wbxx_hal_qspi.h.

#define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT)

nCS stay high for at least 8 clock cycles between commands

Definition at line 257 of file stm32wbxx_hal_qspi.h.

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STM32WB55xx HAL User Manual: QSPI Clock Mode

Defines
QSPI Clock Mode
QSPI Exported Constants

Defines

#define | QSPI_CLOCK_MODE_0 0x00000000U
#define | QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE)

Define Documentation

#define QSPI_CLOCK_MODE_0 0x00000000U

Clk stays low while nCS is released

Definition at line 265 of file stm32wbxx_hal_qspi.h.

#define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE)

Clk goes high while nCS is released

Definition at line 266 of file stm32wbxx_hal_qspi.h.

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STM32WB55xx HAL User Manual: QSPI Address Size

Defines
QSPI Address Size
QSPI Exported Constants

Defines

#define | QSPI_ADDRESS_8_BITS 0x00000000U
#define | QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0)
#define | QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1)
#define | QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE)

Define Documentation

#define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0)

16-bit address

Definition at line 275 of file stm32wbxx_hal_qspi.h.

#define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1)

24-bit address

Definition at line 276 of file stm32wbxx_hal_qspi.h.

#define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE)

32-bit address

Definition at line 277 of file stm32wbxx_hal_qspi.h.

#define QSPI_ADDRESS_8_BITS 0x00000000U

8-bit address

Definition at line 274 of file stm32wbxx_hal_qspi.h.

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STM32WB55xx HAL User Manual: QSPI Alternate Bytes Size

Defines
QSPI Alternate Bytes Size
QSPI Exported Constants

Defines

#define | QSPI_ALTERNATE_BYTES_8_BITS 0x00000000U
#define | QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0)
#define | QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1)
#define | QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE)

Define Documentation

#define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0)

16-bit alternate bytes

Definition at line 286 of file stm32wbxx_hal_qspi.h.

#define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1)

24-bit alternate bytes

Definition at line 287 of file stm32wbxx_hal_qspi.h.

#define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE)

32-bit alternate bytes

Definition at line 288 of file stm32wbxx_hal_qspi.h.

#define QSPI_ALTERNATE_BYTES_8_BITS 0x00000000U

8-bit alternate bytes

Definition at line 285 of file stm32wbxx_hal_qspi.h.

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STM32WB55xx HAL User Manual: QSPI Instruction Mode

Defines
QSPI Instruction Mode
QSPI Exported Constants

Defines

#define | QSPI_INSTRUCTION_NONE 0x00000000U
#define | QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0)
#define | QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1)
#define | QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE)

Define Documentation

#define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0)

Instruction on a single line

Definition at line 297 of file stm32wbxx_hal_qspi.h.

#define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1)

Instruction on two lines

Definition at line 298 of file stm32wbxx_hal_qspi.h.

#define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE)

Instruction on four lines

Definition at line 299 of file stm32wbxx_hal_qspi.h.

#define QSPI_INSTRUCTION_NONE 0x00000000U

No instruction

Definition at line 296 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: QSPI Address Mode

Defines
QSPI Address Mode
QSPI Exported Constants

Defines

#define | QSPI_ADDRESS_NONE 0x00000000U
#define | QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0)
#define | QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1)
#define | QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE)

Define Documentation

#define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0)

Address on a single line

Definition at line 308 of file stm32wbxx_hal_qspi.h.

#define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1)

Address on two lines

Definition at line 309 of file stm32wbxx_hal_qspi.h.

#define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE)

Address on four lines

Definition at line 310 of file stm32wbxx_hal_qspi.h.

#define QSPI_ADDRESS_NONE 0x00000000U

No address

Definition at line 307 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: QSPI Alternate Bytes Mode

Defines
QSPI Alternate Bytes Mode
QSPI Exported Constants

Defines

#define | QSPI_ALTERNATE_BYTES_NONE 0x00000000U
#define | QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0)
#define | QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1)
#define | QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE)

Define Documentation

#define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0)

Alternate bytes on a single line

Definition at line 319 of file stm32wbxx_hal_qspi.h.

#define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1)

Alternate bytes on two lines

Definition at line 320 of file stm32wbxx_hal_qspi.h.

#define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE)

Alternate bytes on four lines

Definition at line 321 of file stm32wbxx_hal_qspi.h.

#define QSPI_ALTERNATE_BYTES_NONE 0x00000000U

No alternate bytes

Definition at line 318 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), and QSPI_Config().

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: QSPI Data Mode

Defines
QSPI Data Mode
QSPI Exported Constants

Defines

#define | QSPI_DATA_NONE 0x00000000U
#define | QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0)
#define | QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1)
#define | QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE)

Define Documentation

#define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0)

Data on a single line

Definition at line 330 of file stm32wbxx_hal_qspi.h.

#define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1)

Data on two lines

Definition at line 331 of file stm32wbxx_hal_qspi.h.

#define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE)

Data on four lines

Definition at line 332 of file stm32wbxx_hal_qspi.h.

#define QSPI_DATA_NONE 0x00000000U

No data

Definition at line 329 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Command(), HAL_QSPI_Command_IT(), and QSPI_Config().

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: QSPI DDR Mode

Defines
QSPI DDR Mode
QSPI Exported Constants

Defines

#define | QSPI_DDR_MODE_DISABLE 0x00000000U
#define | QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM)

Define Documentation

#define QSPI_DDR_MODE_DISABLE 0x00000000U

Double data rate mode disabled

Definition at line 340 of file stm32wbxx_hal_qspi.h.

#define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM)

Double data rate mode enabled

Definition at line 341 of file stm32wbxx_hal_qspi.h.

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STM32WB55xx HAL User Manual: QSPI Send Instruction Mode

Defines
QSPI Send Instruction Mode
QSPI Exported Constants

Defines

#define | QSPI_SIOO_INST_EVERY_CMD 0x00000000U
#define | QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO)

Define Documentation

#define QSPI_SIOO_INST_EVERY_CMD 0x00000000U

Send instruction on every transaction

Definition at line 349 of file stm32wbxx_hal_qspi.h.

#define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO)

Send instruction only for the first command

Definition at line 350 of file stm32wbxx_hal_qspi.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: QSPI Match Mode

Defines
QSPI Match Mode
QSPI Exported Constants

Defines

#define | QSPI_MATCH_MODE_AND 0x00000000U
#define | QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM)

Define Documentation

#define QSPI_MATCH_MODE_AND 0x00000000U

AND match mode between unmasked bits

Definition at line 358 of file stm32wbxx_hal_qspi.h.

#define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM)

OR match mode between unmasked bits

Definition at line 359 of file stm32wbxx_hal_qspi.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: QSPI Automatic Stop

Defines
QSPI Automatic Stop
QSPI Exported Constants

Defines

#define | QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U
#define | QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS)

Define Documentation

#define QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U

AutoPolling stops only with abort or QSPI disabling

Definition at line 367 of file stm32wbxx_hal_qspi.h.

#define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS)

AutoPolling stops as soon as there is a match

Definition at line 368 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling().

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: QSPI Timeout Activation

Defines
QSPI Timeout Activation
QSPI Exported Constants

Defines

#define | QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U
#define | QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN)

Define Documentation

#define QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U

Timeout counter disabled, nCS remains active

Definition at line 376 of file stm32wbxx_hal_qspi.h.

#define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN)

Timeout counter enabled, nCS released when timeout expires

Definition at line 377 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_MemoryMapped().

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: QSPI Flags

Defines
QSPI Flags
QSPI Exported Constants

Defines

#define | QSPI_FLAG_BUSY QUADSPI_SR_BUSY
#define | QSPI_FLAG_TO QUADSPI_SR_TOF
#define | QSPI_FLAG_SM QUADSPI_SR_SMF
#define | QSPI_FLAG_FT QUADSPI_SR_FTF
#define | QSPI_FLAG_TC QUADSPI_SR_TCF
#define | QSPI_FLAG_TE QUADSPI_SR_TEF

Define Documentation

#define QSPI_FLAG_BUSY QUADSPI_SR_BUSY

Busy flag: operation is ongoing

Definition at line 385 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Abort(), HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_Init(), and HAL_QSPI_MemoryMapped().

#define QSPI_FLAG_FT QUADSPI_SR_FTF

Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete

Definition at line 388 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_IRQHandler(), HAL_QSPI_Receive(), and HAL_QSPI_Transmit().

#define QSPI_FLAG_SM QUADSPI_SR_SMF

Status match flag: received data matches in autopolling mode

Definition at line 387 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), and HAL_QSPI_IRQHandler().

#define QSPI_FLAG_TC QUADSPI_SR_TCF

Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted

Definition at line 389 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Abort(), HAL_QSPI_Abort_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_IRQHandler(), HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Receive_IT(), HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), HAL_QSPI_Transmit_IT(), and QSPI_DMAAbortCplt().

#define QSPI_FLAG_TE QUADSPI_SR_TEF

Transfer error flag: invalid address is being accessed

Definition at line 390 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command_IT(), HAL_QSPI_IRQHandler(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Receive_IT(), HAL_QSPI_Transmit_DMA(), and HAL_QSPI_Transmit_IT().

#define QSPI_FLAG_TO QUADSPI_SR_TOF

Timeout flag: timeout occurs in memory-mapped mode

Definition at line 386 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_IRQHandler(), and HAL_QSPI_MemoryMapped().

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: QSPI Interrupts

Defines
QSPI Interrupts
QSPI Exported Constants

Defines

#define | QSPI_IT_TO QUADSPI_CR_TOIE
#define | QSPI_IT_SM QUADSPI_CR_SMIE
#define | QSPI_IT_FT QUADSPI_CR_FTIE
#define | QSPI_IT_TC QUADSPI_CR_TCIE
#define | QSPI_IT_TE QUADSPI_CR_TEIE

Define Documentation

#define QSPI_IT_FT QUADSPI_CR_FTIE

Interrupt on the fifo threshold flag

Definition at line 400 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Abort_IT(), HAL_QSPI_IRQHandler(), HAL_QSPI_Receive_IT(), and HAL_QSPI_Transmit_IT().

#define QSPI_IT_SM QUADSPI_CR_SMIE

Interrupt on the status match flag

Definition at line 399 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Abort_IT(), HAL_QSPI_AutoPolling_IT(), and HAL_QSPI_IRQHandler().

#define QSPI_IT_TC QUADSPI_CR_TCIE

Interrupt on the transfer complete flag

Definition at line 401 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Abort_IT(), HAL_QSPI_Command_IT(), HAL_QSPI_IRQHandler(), HAL_QSPI_Receive_IT(), HAL_QSPI_Transmit_IT(), QSPI_DMAAbortCplt(), QSPI_DMARxCplt(), and QSPI_DMATxCplt().

#define QSPI_IT_TE QUADSPI_CR_TEIE

Interrupt on the transfer error flag

Definition at line 402 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Abort_IT(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command_IT(), HAL_QSPI_IRQHandler(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Receive_IT(), HAL_QSPI_Transmit_DMA(), and HAL_QSPI_Transmit_IT().

#define QSPI_IT_TO QUADSPI_CR_TOIE

Interrupt on the timeout flag

Definition at line 398 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Abort_IT(), HAL_QSPI_IRQHandler(), and HAL_QSPI_MemoryMapped().

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: QSPI Timeout definition

Defines
QSPI Timeout definition
QSPI Exported Constants

QSPI Timeout definition. More...

Defines

#define HAL_QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */

Detailed Description

QSPI Timeout definition.

Define Documentation

#define HAL_QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */

Definition at line 411 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: QSPI Exported Macros

Defines
QSPI Exported Macros
QSPI

Defines

#define | __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__)
Reset QSPI handle state.
#define | __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
Enable the QSPI peripheral.
#define | __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
Disable the QSPI peripheral.
#define | __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
Enable the specified QSPI interrupt.
#define | __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
Disable the specified QSPI interrupt.
#define | __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified QSPI interrupt source is enabled or not.
#define | __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)
Check whether the selected QSPI flag is set or not.
#define | __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
Clears the specified QSPI's flag status.

Define Documentation

#define __HAL_QSPI_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))

Clears the specified QSPI's flag status.

Parameters:
__HANDLE__ : specifies the QSPI Handle.
__FLAG__ : specifies the QSPI clear register flag that needs to be set This parameter can be one of the following values:
  • QSPI_FLAG_TO: QSPI Timeout flag
  • QSPI_FLAG_SM: QSPI Status match flag
  • QSPI_FLAG_TC: QSPI Transfer complete flag
  • QSPI_FLAG_TE: QSPI Transfer error flag
Return values:
None

Definition at line 515 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Abort(), HAL_QSPI_Abort_IT(), HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Receive_IT(), HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA(), HAL_QSPI_Transmit_IT(), and QSPI_DMAAbortCplt().

#define __HAL_QSPI_DISABLE ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)

Disable the QSPI peripheral.

Parameters:
__HANDLE__ : specifies the QSPI Handle.
Return values:
None

Definition at line 448 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_DeInit().

#define __HAL_QSPI_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))

Disable the specified QSPI interrupt.

Parameters:
__HANDLE__ : specifies the QSPI Handle.
__INTERRUPT__ : specifies the QSPI interrupt source to disable. This parameter can be one of the following values:
  • QSPI_IT_TO: QSPI Timeout interrupt
  • QSPI_IT_SM: QSPI Status match interrupt
  • QSPI_IT_FT: QSPI FIFO threshold interrupt
  • QSPI_IT_TC: QSPI Transfer complete interrupt
  • QSPI_IT_TE: QSPI Transfer error interrupt
Return values:
None

Definition at line 475 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Abort_IT(), and HAL_QSPI_IRQHandler().

#define __HAL_QSPI_ENABLE ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)

Enable the QSPI peripheral.

Parameters:
__HANDLE__ : specifies the QSPI Handle.
Return values:
None

Definition at line 442 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Init().

#define __HAL_QSPI_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))

Enable the specified QSPI interrupt.

Parameters:
__HANDLE__ : specifies the QSPI Handle.
__INTERRUPT__ : specifies the QSPI interrupt source to enable. This parameter can be one of the following values:
  • QSPI_IT_TO: QSPI Timeout interrupt
  • QSPI_IT_SM: QSPI Status match interrupt
  • QSPI_IT_FT: QSPI FIFO threshold interrupt
  • QSPI_IT_TC: QSPI Transfer complete interrupt
  • QSPI_IT_TE: QSPI Transfer error interrupt
Return values:
None

Definition at line 461 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_Abort_IT(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command_IT(), HAL_QSPI_MemoryMapped(), HAL_QSPI_Receive_DMA(), HAL_QSPI_Receive_IT(), HAL_QSPI_Transmit_DMA(), HAL_QSPI_Transmit_IT(), QSPI_DMAAbortCplt(), QSPI_DMARxCplt(), and QSPI_DMATxCplt().

#define __HAL_QSPI_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)

Check whether the selected QSPI flag is set or not.

Parameters:
__HANDLE__ : specifies the QSPI Handle.
__FLAG__ : specifies the QSPI flag to check. This parameter can be one of the following values:
  • QSPI_FLAG_BUSY: QSPI Busy flag
  • QSPI_FLAG_TO: QSPI Timeout flag
  • QSPI_FLAG_SM: QSPI Status match flag
  • QSPI_FLAG_FT: QSPI FIFO threshold flag
  • QSPI_FLAG_TC: QSPI Transfer complete flag
  • QSPI_FLAG_TE: QSPI Transfer error flag
Return values:
None

Definition at line 503 of file stm32wbxx_hal_qspi.h.

Referenced by HAL_QSPI_IRQHandler(), and QSPI_WaitFlagStateUntilTimeout().

#define __HAL_QSPI_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))

Check whether the specified QSPI interrupt source is enabled or not.

Parameters:
__HANDLE__ : specifies the QSPI Handle.
__INTERRUPT__ : specifies the QSPI interrupt source to check. This parameter can be one of the following values:
  • QSPI_IT_TO: QSPI Timeout interrupt
  • QSPI_IT_SM: QSPI Status match interrupt
  • QSPI_IT_FT: QSPI FIFO threshold interrupt
  • QSPI_IT_TC: QSPI Transfer complete interrupt
  • QSPI_IT_TE: QSPI Transfer error interrupt
Return values:
The new state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 488 of file stm32wbxx_hal_qspi.h.

#define __HAL_QSPI_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do {                                              \
                                                                  (__HANDLE__)->State = HAL_QSPI_STATE_RESET; \
                                                                  (__HANDLE__)->MspInitCallback = NULL;       \
                                                                  (__HANDLE__)->MspDeInitCallback = NULL;     \
                                                               } while(0)

Reset QSPI handle state.

Parameters:
__HANDLE__ : QSPI handle.
Return values:
None

Definition at line 429 of file stm32wbxx_hal_qspi.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RCC Private Constants

Defines
RCC Private Constants
RCC | RCCEx

Defines

#define | HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
#define | HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
#define | MSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
#define | LSI1_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
#define | LSI2_TIMEOUT_VALUE (3U) /* to be adjusted with DS */
#define | HSI48_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
#define | PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
#define | PLLSAI1_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
#define | PRESCALER_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
#define | LATENCY_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
#define | CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */
#define | PLLSOURCE_NONE (0U)
#define | MEGA_HZ 1000000U /* Division factor to convert Hz in Mhz */
#define | CR_REG_INDEX 1U
#define | BDCR_REG_INDEX 2U
#define | CSR_REG_INDEX 3U
#define | CRRCR_REG_INDEX 4U
#define | RCC_FLAG_MASK 0x1FU
#define | RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
#define | RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
#define | CLK48_MASK 0x10000000U

Define Documentation

#define BDCR_REG_INDEX 2U

Definition at line 48 of file stm32wbxx_hal_rcc.h.

#define CLK48_MASK 0x10000000U

Definition at line 52 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetRngCLKSource().

#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */

Definition at line 82 of file stm32wbxx_hal_rcc.c.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_DeInit().

#define CR_REG_INDEX 1U

Definition at line 47 of file stm32wbxx_hal_rcc.h.

#define CRRCR_REG_INDEX 4U

Definition at line 50 of file stm32wbxx_hal_rcc.h.

#define CSR_REG_INDEX 3U

Definition at line 49 of file stm32wbxx_hal_rcc.h.

#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT

Definition at line 72 of file stm32wbxx_hal_rcc.c.

Referenced by HAL_RCC_OscConfig().

#define HSI48_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */

Definition at line 77 of file stm32wbxx_hal_rcc.c.

Referenced by HAL_RCC_OscConfig().

#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */

Definition at line 73 of file stm32wbxx_hal_rcc.c.

Referenced by HAL_RCC_OscConfig().

#define LATENCY_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */

Definition at line 81 of file stm32wbxx_hal_rcc.c.

Referenced by HAL_RCC_ClockConfig(), and RCC_SetFlashLatency().

#define LSI1_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */

Definition at line 75 of file stm32wbxx_hal_rcc.c.

Referenced by HAL_RCC_OscConfig().

#define LSI2_TIMEOUT_VALUE (3U) /* to be adjusted with DS */

Definition at line 76 of file stm32wbxx_hal_rcc.c.

Referenced by HAL_RCC_OscConfig().

#define MEGA_HZ 1000000U /* Division factor to convert Hz in Mhz */

Definition at line 85 of file stm32wbxx_hal_rcc.c.

Referenced by RCC_SetFlashLatencyFromMSIRange().

#define MSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */

Definition at line 74 of file stm32wbxx_hal_rcc.c.

Referenced by HAL_RCC_DeInit(), and HAL_RCC_OscConfig().

#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */

Definition at line 78 of file stm32wbxx_hal_rcc.c.

Referenced by HAL_RCC_DeInit(), and HAL_RCC_OscConfig().

#define PLLSAI1_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */

Definition at line 79 of file stm32wbxx_hal_rcc.c.

Referenced by HAL_RCC_DeInit().

#define PLLSOURCE_NONE (0U)

Definition at line 84 of file stm32wbxx_hal_rcc.c.

Referenced by HAL_RCC_OscConfig().

#define PRESCALER_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */

Definition at line 80 of file stm32wbxx_hal_rcc.c.

Referenced by HAL_RCC_ClockConfig().

#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))

Definition at line 49 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))

Definition at line 46 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_FLAG_MASK 0x1FU

Definition at line 52 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RCC Private Macros

Defines
RCC Private Macros
RCC

Defines

#define | __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define | MCO1_GPIO_PORT GPIOA
#define | MCO1_PIN GPIO_PIN_8
#define | __MCO2_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
#define | MCO2_GPIO_PORT GPIOB
#define | MCO2_PIN GPIO_PIN_6
#define | __MCO3_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define | MCO3_GPIO_PORT GPIOA
#define | MCO3_PIN GPIO_PIN_15
#define | RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (uint32_t)(__HAL_RCC_PLLSOURCE__)))
#define | __COUNTOF(_A_) (sizeof(_A_) / sizeof(*(_A_)))
#define | IS_RCC_OSCILLATORTYPE(__OSCILLATOR__)
#define | IS_RCC_HSE(__HSE__)
#define | IS_RCC_LSE(__LSE__)
#define | IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
#define | IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)127U)
#define | IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
#define | IS_RCC_LSI2_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)15U)
#define | IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))
#define | IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)255U)
#define | IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))
#define | IS_RCC_PLL(__PLL__)
#define | IS_RCC_PLLSOURCE(__SOURCE__)
#define | IS_RCC_PLLM_VALUE(__VALUE__)
#define | IS_RCC_PLLN_VALUE(__VALUE__) ((6U <= (__VALUE__)) && ((__VALUE__) <= 127U))
#define | IS_RCC_PLLP_VALUE(__VALUE__) ((RCC_PLLP_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLP_DIV32))
#define | IS_RCC_PLLQ_VALUE(__VALUE__) ((RCC_PLLQ_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLQ_DIV8))
#define | IS_RCC_PLLR_VALUE(__VALUE__) ((RCC_PLLR_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLR_DIV8))
#define | IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__)
#define | IS_RCC_MSI_CLOCK_RANGE(__RANGE__)
#define | IS_RCC_CLOCKTYPE(__CLK__)
#define | IS_RCC_SYSCLKSOURCE(__SOURCE__)
#define | IS_RCC_HCLKx(__HCLK__)
#define | IS_RCC_PCLKx(__PCLK__)
#define | IS_RCC_RTCCLKSOURCE(__SOURCE__)
#define | IS_RCC_MCO(__MCOX__) ( ((__MCOX__) == RCC_MCO1) || ((__MCOX__) == RCC_MCO2) || ((__MCOX__) == RCC_MCO3) )
#define | IS_RCC_MCO1SOURCE(__SOURCE__)
#define | IS_RCC_MCO2SOURCE(__SOURCE__) IS_RCC_MCO1SOURCE((__SOURCE__))
#define | IS_RCC_MCO3SOURCE(__SOURCE__) IS_RCC_MCO1SOURCE((__SOURCE__))
#define | IS_RCC_MCODIV(__DIV__)
#define | IS_RCC_LSE_DRIVE(__DRIVE__)
#define | IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__)

Define Documentation

#define __COUNTOF ( _A_ ) (sizeof(_A_) / sizeof(*(_A_)))

Definition at line 109 of file stm32wbxx_hal_rcc.c.

Referenced by RCC_SetFlashLatency().

#define __MCO1_CLK_ENABLE ( ) __HAL_RCC_GPIOA_CLK_ENABLE()

Definition at line 94 of file stm32wbxx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define __MCO2_CLK_ENABLE ( ) __HAL_RCC_GPIOB_CLK_ENABLE()

Definition at line 98 of file stm32wbxx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define __MCO3_CLK_ENABLE ( ) __HAL_RCC_GPIOA_CLK_ENABLE()

Definition at line 102 of file stm32wbxx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define IS_RCC_CLOCKTYPE ( __CLK__ )
Value:
((1U <= (__CLK__)) && ((__CLK__) <= (RCC_CLOCKTYPE_SYSCLK | \
                                                                         RCC_CLOCKTYPE_HCLK  | \
                                                                         RCC_CLOCKTYPE_PCLK1 | \
                                                                         RCC_CLOCKTYPE_PCLK2 | \
                                                                         RCC_CLOCKTYPE_HCLK2 | \
                                                                         RCC_CLOCKTYPE_HCLK4)))

Definition at line 140 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_HCLKx ( __HCLK__ )
Value:
(((__HCLK__) == RCC_SYSCLK_DIV1)   || ((__HCLK__) == RCC_SYSCLK_DIV2)   || ((__HCLK__) == RCC_SYSCLK_DIV3)   || \
                               ((__HCLK__) == RCC_SYSCLK_DIV4)   || ((__HCLK__) == RCC_SYSCLK_DIV5)   || ((__HCLK__) == RCC_SYSCLK_DIV6)   || \
                               ((__HCLK__) == RCC_SYSCLK_DIV8)   || ((__HCLK__) == RCC_SYSCLK_DIV10)  || ((__HCLK__) == RCC_SYSCLK_DIV16)  || \
                               ((__HCLK__) == RCC_SYSCLK_DIV32)  || ((__HCLK__) == RCC_SYSCLK_DIV64)  || ((__HCLK__) == RCC_SYSCLK_DIV128) || \
                               ((__HCLK__) == RCC_SYSCLK_DIV256) || ((__HCLK__) == RCC_SYSCLK_DIV512))

Definition at line 152 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_HSE ( __HSE__ )
Value:
(((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
                              ((__HSE__) == RCC_HSE_BYPASS))

Definition at line 72 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_HSI ( __HSI__ ) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))

Definition at line 78 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_HSI48 ( __HSI48__ ) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))

Definition at line 93 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_HSI_CALIBRATION_VALUE ( __VALUE__ ) ((__VALUE__) <= (uint32_t)127U)

Definition at line 80 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_LSE ( __LSE__ )
Value:
(((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
                              ((__LSE__) == RCC_LSE_BYPASS))

Definition at line 75 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_LSE_DRIVE ( __DRIVE__ )
Value:
(((__DRIVE__) == RCC_LSEDRIVE_LOW)        || \
                                     ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW)  || \
                                     ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \
                                     ((__DRIVE__) == RCC_LSEDRIVE_HIGH))

Definition at line 191 of file stm32wbxx_hal_rcc.h.

#define IS_RCC_LSI ( __LSI__ ) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))

Definition at line 82 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_LSI2_CALIBRATION_VALUE ( __VALUE__ ) ((__VALUE__) <= (uint32_t)15U)

Definition at line 84 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_MCO ( __MCOX__ ) ( ((__MCOX__) == RCC_MCO1) || ((__MCOX__) == RCC_MCO2) || ((__MCOX__) == RCC_MCO3) )

Definition at line 167 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define IS_RCC_MCO1SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
                                       ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
                                       ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
                                       ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
                                       ((__SOURCE__) == RCC_MCO1SOURCE_LSI1) || \
                                       ((__SOURCE__) == RCC_MCO1SOURCE_LSI2) || \
                                       ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \
                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSI48))

Definition at line 169 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define IS_RCC_MCO2SOURCE ( __SOURCE__ ) IS_RCC_MCO1SOURCE((__SOURCE__))

Definition at line 180 of file stm32wbxx_hal_rcc.h.

#define IS_RCC_MCO3SOURCE ( __SOURCE__ ) IS_RCC_MCO1SOURCE((__SOURCE__))

Definition at line 181 of file stm32wbxx_hal_rcc.h.

#define IS_RCC_MCODIV ( __DIV__ )
Value:
(((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \
                                ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \
                                ((__DIV__) == RCC_MCODIV_16))

Definition at line 184 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define IS_RCC_MSI ( __MSI__ ) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))

Definition at line 87 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_MSI_CLOCK_RANGE ( __RANGE__ )
Value:
(((__RANGE__) == RCC_MSIRANGE_0)  || \
                                           ((__RANGE__) == RCC_MSIRANGE_1)  || \
                                           ((__RANGE__) == RCC_MSIRANGE_2)  || \
                                           ((__RANGE__) == RCC_MSIRANGE_3)  || \
                                           ((__RANGE__) == RCC_MSIRANGE_4)  || \
                                           ((__RANGE__) == RCC_MSIRANGE_5)  || \
                                           ((__RANGE__) == RCC_MSIRANGE_6)  || \
                                           ((__RANGE__) == RCC_MSIRANGE_7)  || \
                                           ((__RANGE__) == RCC_MSIRANGE_8)  || \
                                           ((__RANGE__) == RCC_MSIRANGE_9)  || \
                                           ((__RANGE__) == RCC_MSIRANGE_10) || \
                                           ((__RANGE__) == RCC_MSIRANGE_11))

Definition at line 127 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and RCC_SetFlashLatencyFromMSIRange().

#define IS_RCC_MSICALIBRATION_VALUE ( __VALUE__ ) ((__VALUE__) <= (uint32_t)255U)

Definition at line 90 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_OSCILLATORTYPE ( __OSCILLATOR__ )
Value:
(((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE)                             || \
                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE)  == RCC_OSCILLATORTYPE_HSE)  || \
                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI)  == RCC_OSCILLATORTYPE_HSI)  || \
                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \
                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI)  == RCC_OSCILLATORTYPE_MSI)  || \
                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI1) == RCC_OSCILLATORTYPE_LSI1) || \
                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI2) == RCC_OSCILLATORTYPE_LSI2) || \
                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE)  == RCC_OSCILLATORTYPE_LSE))

Definition at line 62 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PCLKx ( __PCLK__ )
Value:
(((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
                                ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
                                ((__PCLK__) == RCC_HCLK_DIV16))

Definition at line 158 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_PLL ( __PLL__ )
Value:
(((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \
                             ((__PLL__) == RCC_PLL_ON))

Definition at line 96 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLM_VALUE ( __VALUE__ )
Value:
(((__VALUE__) == RCC_PLLM_DIV1)  || \
                                      ((__VALUE__) == RCC_PLLM_DIV2)  || \
                                      ((__VALUE__) == RCC_PLLM_DIV3)  || \
                                      ((__VALUE__) == RCC_PLLM_DIV4)  || \
                                      ((__VALUE__) == RCC_PLLM_DIV5)  || \
                                      ((__VALUE__) == RCC_PLLM_DIV6)  || \
                                      ((__VALUE__) == RCC_PLLM_DIV7)  || \
                                      ((__VALUE__) == RCC_PLLM_DIV8))

Definition at line 104 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLN_VALUE ( __VALUE__ ) ((6U <= (__VALUE__)) && ((__VALUE__) <= 127U))

Definition at line 113 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), HAL_RCCEx_EnablePLLSAI1(), RCCEx_PLLSAI1_ConfigNP(), RCCEx_PLLSAI1_ConfigNQ(), and RCCEx_PLLSAI1_ConfigNR().

#define IS_RCC_PLLP_VALUE ( __VALUE__ ) ((RCC_PLLP_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLP_DIV32))

Definition at line 115 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), HAL_RCCEx_EnablePLLSAI1(), and RCCEx_PLLSAI1_ConfigNP().

#define IS_RCC_PLLQ_VALUE ( __VALUE__ ) ((RCC_PLLQ_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLQ_DIV8))

Definition at line 117 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), HAL_RCCEx_EnablePLLSAI1(), and RCCEx_PLLSAI1_ConfigNQ().

#define IS_RCC_PLLR_VALUE ( __VALUE__ ) ((RCC_PLLR_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLR_DIV8))

Definition at line 119 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), HAL_RCCEx_EnablePLLSAI1(), and RCCEx_PLLSAI1_ConfigNR().

#define IS_RCC_PLLSAI1CLOCKOUT_VALUE ( __VALUE__ )
Value:
(((((__VALUE__) & RCC_PLLSAI1_ADCCLK) == RCC_PLLSAI1_ADCCLK) || \
                                                (((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK)  || \
                                                (((__VALUE__) & RCC_PLLSAI1_USBCLK) == RCC_PLLSAI1_USBCLK)) && \
                                                (((__VALUE__) & ~(RCC_PLLSAI1_ADCCLK|RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_USBCLK)) == 0U))

Definition at line 122 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCCEx_EnablePLLSAI1(), RCCEx_PLLSAI1_ConfigNP(), RCCEx_PLLSAI1_ConfigNQ(), and RCCEx_PLLSAI1_ConfigNR().

#define IS_RCC_PLLSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_PLLSOURCE_NONE) || \
                                      ((__SOURCE__) == RCC_PLLSOURCE_MSI)  || \
                                      ((__SOURCE__) == RCC_PLLSOURCE_HSI)  || \
                                      ((__SOURCE__) == RCC_PLLSOURCE_HSE))

Definition at line 99 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_RTCCLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \
                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))

Definition at line 162 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_STOP_WAKEUPCLOCK ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \
                                             ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI))

Definition at line 196 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCCEx_WakeUpStopCLKConfig().

#define IS_RCC_SYSCLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \
                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))

Definition at line 147 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define MCO1_GPIO_PORT GPIOA

Definition at line 95 of file stm32wbxx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define MCO1_PIN GPIO_PIN_8

Definition at line 96 of file stm32wbxx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define MCO2_GPIO_PORT GPIOB

Definition at line 99 of file stm32wbxx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define MCO2_PIN GPIO_PIN_6

Definition at line 100 of file stm32wbxx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define MCO3_GPIO_PORT GPIOA

Definition at line 103 of file stm32wbxx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define MCO3_PIN GPIO_PIN_15

Definition at line 104 of file stm32wbxx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define RCC_PLL_OSCSOURCE_CONFIG ( __HAL_RCC_PLLSOURCE__ ) (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (uint32_t)(__HAL_RCC_PLLSOURCE__)))

Definition at line 106 of file stm32wbxx_hal_rcc.c.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RCC Private Variables

RCC Private Variables
RCC
Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RCC Private Functions

Functions
RCC Private Functions
RCC

Functions

static HAL_StatusTypeDef | RCC_SetFlashLatencyFromMSIRange (uint32_t MSI_Range)
Update number of Flash wait states in line with MSI range and current voltage range.
static HAL_StatusTypeDef | RCC_SetFlashLatency (uint32_t Flash_ClkSrcFreq, uint32_t VCORE_Voltage)
Update number of Flash wait states.

Function Documentation

static HAL_StatusTypeDef RCC_SetFlashLatency | ( | uint32_t | Flash_ClkSrcFreq,
 |  | uint32_t | VCORE_Voltage
 | ) |  | [static]

Update number of Flash wait states.

Parameters:
Flash_ClkSrcFreq | Flash Clock Source (in MHz)
VCORE_Voltage | Current Vcore voltage (PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2)
Return values:
HAL status

Definition at line 1709 of file stm32wbxx_hal_rcc.c.

References __COUNTOF, __HAL_FLASH_GET_LATENCY, __HAL_FLASH_SET_LATENCY, FLASH_LATENCY_0, FLASH_LATENCY_1, FLASH_LATENCY_2, FLASH_LATENCY_3, HAL_GetTick(), LATENCY_TIMEOUT_VALUE, and PWR_REGULATOR_VOLTAGE_SCALE1.

Referenced by RCC_SetFlashLatencyFromMSIRange().

static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange ( uint32_t MSI_Range ) [static]

Update number of Flash wait states in line with MSI range and current voltage range.

Parameters:
MSI_Range MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_11
Return values:
HAL status

Definition at line 1676 of file stm32wbxx_hal_rcc.c.

References __LL_RCC_CALC_HCLK4_FREQ, __LL_RCC_CALC_MSI_FREQ, assert_param, HAL_PWREx_GetVoltageRange(), IS_RCC_MSI_CLOCK_RANGE, LL_RCC_GetAHB4Prescaler(), MEGA_HZ, PWR_REGULATOR_VOLTAGE_SCALE1, RCC_MSIRANGE_11, and RCC_SetFlashLatency().

Referenced by HAL_RCC_OscConfig().

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
RCC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_RCC_DeInit (void)
Reset the RCC clock configuration to the default reset state.
HAL_StatusTypeDef | HAL_RCC_OscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Initialize the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.
HAL_StatusTypeDef | HAL_RCC_ClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
Initialize the CPU, AHB and APB buses clocks according to the specified parameters in the RCC_ClkInitStruct.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
           ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]
      This section provides functions allowing to configure the internal and external oscillators
      (HSE, HSI, LSE, MSI, LSI1, LSI2, PLL, CSS and MCO) and the System buses clocks (SYSCLK, HCLK1, HCLK2, HCLK4, PCLK1
       and PCLK2).

    [..] Internal/external clock and PLL configuration
         (+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through
             the PLL as System clock source.

         (+) MSI (Mutiple Speed Internal): Its frequency is software trimmable from 100KHZ to 48MHZ.
             It can be used to generate the clock for the USB FS (48 MHz).
             The number of flash wait states is automatically adjusted when MSI range is updated with
             @ref HAL_RCC_OscConfig() and the MSI is used as System clock source.

         (+) LSI1/LSI2 (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC
             clock source.

         (+) HSE (high-speed external): 32 MHz crystal oscillator used directly or
             through the PLL as System clock source. Can be used also optionally as RTC clock source.

         (+) LSE (low-speed external): 32.768 KHz oscillator used optionally as RTC clock source
             or the RF system Auto-wakeup from Stop and Standby modes.

         (+) PLL (clocked by HSI, HSE or MSI) providing up to three independent output clocks:
           (++) The first output is used to generate the high speed system clock (up to 64MHz).
           (++) The second output is used to generate the clock for the USB FS (48 MHz),
                the random analog generator (<=48 MHz)
           (++) The third output is used to generate an accurate clock to achieve
                high-quality audio performance on SAI interface.

         (+) PLLSAI1 (clocked by HSI, HSE or MSI) providing up to three independent output clocks:
           (++) The first output is used to generate SAR ADC clock.
           (++) The second output is used to generate the clock for the USB FS (48 MHz),
                the random analog generator (<=48 MHz).
           (++) The Third output is used to generate an accurate clock to achieve
                high-quality audio performance on SAI interface.

         (+) CSS (Clock security system): once enabled, if a HSE clock failure occurs
            (HSE used directly or through PLL as System clock source), the System clock
             is automatically switched to MSI or the HSI oscillator (depending on the
             STOPWUCK configuration) and an interrupt is generated if enabled.
             The interrupt is linked to the CPU1 and CPU2 NMI (Non-Maskable Interrupt) exception vector.

         (+) LSECSS: once enabled, if a LSE clock failure occurs, the LSE
             clock is no longer supplied to the RTC but no hardware action is made to the registers. If the
             MSI was in PLL-mode, this mode is disabled.
             In Standby mode a wakeup is generated. In other modes an interrupt can be sent to wakeup
             the software

         (+) MCO (microcontroller clock output): used to output MSI, LSI1, LSI2, HSI, LSE, HSE (before and
             after stabilization), SYSCLK, HSI48 or main PLL clock (through a configurable prescaler) on PA8, PB6 & PA15 pins.

    [..] System, AHB and APB buses clocks configuration
         (+) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI,
             HSE and main PLL.
             The AHB clock (HCLK1) is derived from System clock through configurable
             prescaler and used to clock the CPU, memory and peripherals mapped
             on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
             from AHB clock through configurable prescalers and used to clock
             the peripherals mapped on these buses. You can use
             "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
             The AHB4 clock (HCLK4) is derived from System clock through configurable
             prescaler and used to clock the FLASH

         -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:

           (+@) SAI: the SAI clock can be derived either from a specific PLL (PLLSAI1) or (PLLSYS) or
                from an external clock mapped on the SAI_CKIN pin.
                You have to use @ref HAL_RCCEx_PeriphCLKConfig() function to configure this clock.
           (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
                divided by 32.
                You have to use @ref __HAL_RCC_RTC_ENABLE() and @ref HAL_RCCEx_PeriphCLKConfig() function
                to configure this clock.
           (+@) USB FS and RNG: USB FS requires a frequency equal to 48 MHz
                to work correctly, while RNG peripherals requires a frequency
                equal or lower than to 48 MHz. This clock is derived of the main PLL or PLLSAI1
                through PLLQ divider. You have to enable the peripheral clock and use
                @ref HAL_RCCEx_PeriphCLKConfig() function to configure this clock.
           (+@) IWDG clock which is always the LSI clock.

         (+) The maximum frequency of the SYSCLK, HCLK1, HCLK4, PCLK1 and PCLK2 is 64 MHz.
             The maximum frequency of the HCLK2 is 32 MHz.
             The clock source frequency should be adapted depending on the device voltage range
             as listed in the Reference Manual "Clock source frequency versus voltage scaling" chapter.

Table 1. HCLK4 clock frequency. +-------------------------------------------------------+ | Latency | HCLK4 clock frequency (MHz) | | |-------------------------------------| | | voltage range 1 | voltage range 2 | | | 1.2 V | 1.0 V | |-----------------|------------------|------------------| |0WS(1 CPU cycles)| HCLK4 <= 18 | HCLK4 <= 6 | |-----------------|------------------|------------------| |1WS(2 CPU cycles)| HCLK4 <= 36 | HCLK4 <= 12 | |-----------------|------------------|------------------| |2WS(3 CPU cycles)| HCLK4 <= 54 | HCLK4 <= 16 | |-----------------|------------------|------------------| |3WS(4 CPU cycles)| HCLK4 <= 64 | HCLK4 <= n.a. | |-----------------|------------------|------------------|

Function Documentation

HAL_StatusTypeDef HAL_RCC_ClockConfig | ( | RCC_ClkInitTypeDef * | RCC_ClkInitStruct,
 |  | uint32_t | FLatency
 | ) |  |

Initialize the CPU, AHB and APB buses clocks according to the specified parameters in the RCC_ClkInitStruct.

Parameters:
RCC_ClkInitStruct pointer to a RCC_ClkInitTypeDef structure that contains the configuration information for the RCC peripheral.
FLatency FLASH Latency This parameter can be one of the following values:
  • FLASH_LATENCY_0 FLASH 0 Latency cycle
  • FLASH_LATENCY_1 FLASH 1 Latency cycle
  • FLASH_LATENCY_2 FLASH 2 Latency cycle
  • FLASH_LATENCY_3 FLASH 3 Latency cycle
Note:
The SystemCoreClock CMSIS variable is used to store System Clock Frequency and updated by HAL_RCC_GetHCLKFreq() function called within this function
The MSI is used by default as system clock source after startup from Reset, wake-up from STANDBY mode. After restart from Reset, the MSI frequency is set to its default value 4 MHz.
The HSI can be selected as system clock source after from STOP modes or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source is ready.
You can use HAL_RCC_GetClockConfig() function to know which clock is currently used as system clock source.
Depending on the device voltage range, the software has to set correctly HPRE[3:0] bits to ensure that HCLK1 not exceed the maximum allowed frequency (for more details refer to section above "Initialization/de-initialization functions")
Return values:
None

Definition at line 1010 of file stm32wbxx_hal_rcc.c.

References __HAL_FLASH_GET_LATENCY, __HAL_FLASH_SET_LATENCY, __HAL_RCC_GET_SYSCLK_SOURCE, RCC_ClkInitTypeDef::AHBCLK2Divider, RCC_ClkInitTypeDef::AHBCLK4Divider, RCC_ClkInitTypeDef::AHBCLKDivider, RCC_ClkInitTypeDef::APB1CLKDivider, RCC_ClkInitTypeDef::APB2CLKDivider, assert_param, CLOCKSWITCH_TIMEOUT_VALUE, RCC_ClkInitTypeDef::ClockType, HAL_GetTick(), HAL_GetTickPrio(), HAL_InitTick(), IS_FLASH_LATENCY, IS_RCC_CLOCKTYPE, IS_RCC_HCLKx, IS_RCC_PCLKx, IS_RCC_SYSCLKSOURCE, LATENCY_TIMEOUT_VALUE, LL_C2_RCC_SetAHBPrescaler(), LL_RCC_HSE_IsReady(), LL_RCC_HSI_IsReady(), LL_RCC_IsActiveFlag_C2HPRE(), LL_RCC_IsActiveFlag_HPRE(), LL_RCC_IsActiveFlag_PPRE1(), LL_RCC_IsActiveFlag_PPRE2(), LL_RCC_IsActiveFlag_SHDHPRE(), LL_RCC_MSI_IsReady(), LL_RCC_PLL_IsReady(), LL_RCC_SetAHB4Prescaler(), LL_RCC_SetAHBPrescaler(), LL_RCC_SetAPB1Prescaler(), LL_RCC_SetAPB2Prescaler(), LL_RCC_SetSysClkSource(), PRESCALER_TIMEOUT_VALUE, RCC_CLOCKTYPE_HCLK, RCC_CLOCKTYPE_HCLK2, RCC_CLOCKTYPE_HCLK4, RCC_CLOCKTYPE_PCLK1, RCC_CLOCKTYPE_PCLK2, RCC_CLOCKTYPE_SYSCLK, RCC_SYSCLKSOURCE_HSE, RCC_SYSCLKSOURCE_MSI, RCC_SYSCLKSOURCE_PLLCLK, and RCC_ClkInitTypeDef::SYSCLKSource.

HAL_StatusTypeDef HAL_RCC_DeInit ( void )

Reset the RCC clock configuration to the default reset state.

Note:
The default reset state of the clock configuration is given below:
  • MSI ON and used as system clock source
  • HSE, HSI, PLL, PLLSAI1
  • HCLK1, HCLK2, HCLK4, PCLK1 and PCLK2 prescalers set to 1.
  • CSS, MCO OFF
  • All interrupts disabled
This function doesn't modify the configuration of the
  • Peripheral clocks
  • LSI, LSE and RTC clocks
Return values:
HAL status

Definition at line 268 of file stm32wbxx_hal_rcc.c.

References CLOCKSWITCH_TIMEOUT_VALUE, HAL_GetTick(), HAL_InitTick(), LL_RCC_HSE_DisableBypass(), LL_RCC_HSI_SetCalibTrimming(), LL_RCC_MSI_Enable(), LL_RCC_MSI_IsReady(), LL_RCC_MSI_SetCalibTrimming(), LL_RCC_MSI_SetRange(), LL_RCC_MSIRANGE_6, LL_RCC_PLL_IsReady(), LL_RCC_PLLSAI1_IsReady(), LL_RCC_WriteReg, MSI_TIMEOUT_VALUE, MSI_VALUE, PLL_TIMEOUT_VALUE, PLLSAI1_TIMEOUT_VALUE, and uwTickPrio.

HAL_StatusTypeDef HAL_RCC_OscConfig ( RCC_OscInitTypeDef * RCC_OscInitStruct )

Initialize the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.

Parameters:
RCC_OscInitStruct pointer to a RCC_OscInitTypeDef structure that contains the configuration information for the RCC Oscillators.
Note:
The PLL is not disabled when used as system clock.
Return values:
HAL status

Definition at line 383 of file stm32wbxx_hal_rcc.c.

References __HAL_RCC_GET_MSI_RANGE, __HAL_RCC_GET_PLL_OSCSOURCE, __HAL_RCC_GET_SYSCLK_SOURCE, __HAL_RCC_HSE_CONFIG, __HAL_RCC_HSI48_DISABLE, __HAL_RCC_HSI48_ENABLE, __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST, __HAL_RCC_HSI_DISABLE, __HAL_RCC_HSI_ENABLE, __HAL_RCC_LSE_CONFIG, __HAL_RCC_LSI1_DISABLE, __HAL_RCC_LSI1_ENABLE, __HAL_RCC_LSI2_CALIBRATIONVALUE_ADJUST, __HAL_RCC_LSI2_DISABLE, __HAL_RCC_LSI2_ENABLE, __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST, __HAL_RCC_MSI_DISABLE, __HAL_RCC_MSI_ENABLE, __HAL_RCC_MSI_RANGE_CONFIG, __HAL_RCC_PLL_CONFIG, __HAL_RCC_PLL_DISABLE, __HAL_RCC_PLL_ENABLE, __HAL_RCC_PLLCLKOUT_DISABLE, __HAL_RCC_PLLCLKOUT_ENABLE, assert_param, HAL_GetTick(), HAL_InitTick(), HAL_PWR_EnableBkUpAccess(), HSE_TIMEOUT_VALUE, RCC_OscInitTypeDef::HSEState, HSI48_TIMEOUT_VALUE, RCC_OscInitTypeDef::HSI48State, HSI_TIMEOUT_VALUE, RCC_OscInitTypeDef::HSICalibrationValue, RCC_OscInitTypeDef::HSIState, IS_RCC_HSE, IS_RCC_HSI, IS_RCC_HSI48, IS_RCC_HSI_CALIBRATION_VALUE, IS_RCC_LSE, IS_RCC_LSI, IS_RCC_LSI2_CALIBRATION_VALUE, IS_RCC_MSI, IS_RCC_MSI_CLOCK_RANGE, IS_RCC_MSICALIBRATION_VALUE, IS_RCC_OSCILLATORTYPE, IS_RCC_PLL, IS_RCC_PLLM_VALUE, IS_RCC_PLLN_VALUE, IS_RCC_PLLP_VALUE, IS_RCC_PLLQ_VALUE, IS_RCC_PLLR_VALUE, IS_RCC_PLLSOURCE, LL_RCC_HSE_IsReady(), LL_RCC_HSI48_IsReady(), LL_RCC_HSI_IsReady(), LL_RCC_LSE_IsReady(), LL_RCC_LSI1_IsReady(), LL_RCC_LSI2_IsReady(), LL_RCC_MSI_IsReady(), LL_RCC_PLL_IsReady(), RCC_OscInitTypeDef::LSEState, LSI1_TIMEOUT_VALUE, LSI2_TIMEOUT_VALUE, RCC_OscInitTypeDef::LSI2CalibrationValue, RCC_OscInitTypeDef::LSIState, MSI_TIMEOUT_VALUE, RCC_OscInitTypeDef::MSICalibrationValue, RCC_OscInitTypeDef::MSIClockRange, RCC_OscInitTypeDef::MSIState, RCC_OscInitTypeDef::OscillatorType, RCC_OscInitTypeDef::PLL, PLL_TIMEOUT_VALUE, RCC_PLLInitTypeDef::PLLM, RCC_PLLInitTypeDef::PLLN, RCC_PLLInitTypeDef::PLLP, RCC_PLLInitTypeDef::PLLQ, RCC_PLLInitTypeDef::PLLR, RCC_PLLInitTypeDef::PLLSource, PLLSOURCE_NONE, RCC_PLLInitTypeDef::PLLState, RCC_DBP_TIMEOUT_VALUE, RCC_HSE_OFF, RCC_HSI48_OFF, RCC_HSI_OFF, RCC_LSE_OFF, RCC_LSE_TIMEOUT_VALUE, RCC_LSI_OFF, RCC_MSI_OFF, RCC_OSCILLATORTYPE_HSE, RCC_OSCILLATORTYPE_HSI, RCC_OSCILLATORTYPE_HSI48, RCC_OSCILLATORTYPE_LSE, RCC_OSCILLATORTYPE_LSI1, RCC_OSCILLATORTYPE_LSI2, RCC_OSCILLATORTYPE_MSI, RCC_PLL_NONE, RCC_PLL_OFF, RCC_PLL_ON, RCC_PLL_SAI1CLK, RCC_PLL_SYSCLK, RCC_PLL_USBCLK, RCC_PLLSOURCE_HSE, RCC_PLLSOURCE_HSI, RCC_PLLSOURCE_MSI, RCC_SetFlashLatencyFromMSIRange(), RCC_SYSCLKSOURCE_STATUS_HSE, RCC_SYSCLKSOURCE_STATUS_HSI, RCC_SYSCLKSOURCE_STATUS_MSI, RCC_SYSCLKSOURCE_STATUS_PLLCLK, and uwTickPrio.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
RCC Exported Functions

RCC clocks control functions. More...

Functions

void | HAL_RCC_MCOConfig (uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
Select the clock source to output on MCO1 pin(PA8) or MC02 pin (PB6) or MCO3 pin (PA15).
uint32_t | HAL_RCC_GetSysClockFreq (void)
Return the SYSCLK frequency.
uint32_t | HAL_RCC_GetHCLKFreq (void)
Return the HCLK frequency.
uint32_t | HAL_RCC_GetHCLK2Freq (void)
Return the HCLK2 frequency.
uint32_t | HAL_RCC_GetHCLK4Freq (void)
Return the HCLK4 frequency.
uint32_t | HAL_RCC_GetPCLK1Freq (void)
Return the PCLK1 frequency.
uint32_t | HAL_RCC_GetPCLK2Freq (void)
Return the PCLK2 frequency.
void | HAL_RCC_GetOscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Configure the RCC_OscInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_GetClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
Configure the RCC_ClkInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_EnableCSS (void)
Enable the Clock Security System.
void | HAL_RCC_NMI_IRQHandler (void)
Handle the RCC HSE Clock Security System interrupt request.
__weak void | HAL_RCC_CSSCallback (void)
Handle the RCC HSE Clock Security System interrupt callback.

Detailed Description

RCC clocks control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to:

    (+) Ouput clock to MCO pin.
    (+) Retrieve current clock frequencies.
    (+) Enable the Clock Security System.

Function Documentation

void HAL_RCC_CSSCallback ( void )

Handle the RCC HSE Clock Security System interrupt callback.

Return values:
none

Definition at line 1649 of file stm32wbxx_hal_rcc.c.

Referenced by HAL_RCC_NMI_IRQHandler().

void HAL_RCC_EnableCSS ( void )

Enable the Clock Security System.

Note:
If a failure is detected on the HSE oscillator clock, this oscillator is automatically disabled and an interrupt is generated to inform the software about the failure (Clock Security System Interrupt, CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to CPU1 and CPU2 NMI (Non-Maskable Interrupt) exception vector.
The Clock Security System can only be cleared by reset.
Return values:
None

Definition at line 1622 of file stm32wbxx_hal_rcc.c.

References LL_RCC_HSE_EnableCSS().

void HAL_RCC_GetClockConfig | ( | RCC_ClkInitTypeDef * | RCC_ClkInitStruct,
 |  | uint32_t * | pFLatency
 | ) |  |

Configure the RCC_ClkInitStruct according to the internal RCC configuration registers.

Parameters:
RCC_ClkInitStruct | Pointer to a RCC_ClkInitTypeDef structure that will be configured.
pFLatency | Pointer on the Flash Latency.
Return values:
None

Definition at line 1580 of file stm32wbxx_hal_rcc.c.

References __HAL_FLASH_GET_LATENCY, RCC_ClkInitTypeDef::AHBCLK2Divider, RCC_ClkInitTypeDef::AHBCLK4Divider, RCC_ClkInitTypeDef::AHBCLKDivider, RCC_ClkInitTypeDef::APB1CLKDivider, RCC_ClkInitTypeDef::APB2CLKDivider, assert_param, RCC_ClkInitTypeDef::ClockType, LL_C2_RCC_GetAHBPrescaler(), LL_RCC_GetAHB4Prescaler(), LL_RCC_GetAHBPrescaler(), LL_RCC_GetAPB1Prescaler(), LL_RCC_GetAPB2Prescaler(), LL_RCC_GetSysClkSource(), RCC_CLOCKTYPE_HCLK, RCC_CLOCKTYPE_HCLK4, RCC_CLOCKTYPE_PCLK1, RCC_CLOCKTYPE_PCLK2, RCC_CLOCKTYPE_SYSCLK, and RCC_ClkInitTypeDef::SYSCLKSource.

uint32_t HAL_RCC_GetHCLK2Freq ( void )

Return the HCLK2 frequency.

Return values:
HCLK2 frequency in Hz

Definition at line 1423 of file stm32wbxx_hal_rcc.c.

References __LL_RCC_CALC_HCLK2_FREQ, HAL_RCC_GetSysClockFreq(), and LL_C2_RCC_GetAHBPrescaler().

uint32_t HAL_RCC_GetHCLK4Freq ( void )

Return the HCLK4 frequency.

Return values:
HCLK4 frequency in Hz

Definition at line 1433 of file stm32wbxx_hal_rcc.c.

References __LL_RCC_CALC_HCLK4_FREQ, HAL_RCC_GetSysClockFreq(), and LL_RCC_GetAHB4Prescaler().

uint32_t HAL_RCC_GetHCLKFreq ( void )

Return the HCLK frequency.

Return values:
HCLK frequency in Hz

Definition at line 1413 of file stm32wbxx_hal_rcc.c.

References __LL_RCC_CALC_HCLK1_FREQ, HAL_RCC_GetSysClockFreq(), and LL_RCC_GetAHBPrescaler().

Referenced by HAL_InitTick(), HAL_RCC_GetPCLK1Freq(), and HAL_RCC_GetPCLK2Freq().

void HAL_RCC_GetOscConfig ( RCC_OscInitTypeDef * RCC_OscInitStruct )

Configure the RCC_OscInitStruct according to the internal RCC configuration registers.

Parameters:
RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that will be configured.
Return values:
None

Definition at line 1470 of file stm32wbxx_hal_rcc.c.

References assert_param, RCC_OscInitTypeDef::HSEState, RCC_OscInitTypeDef::HSI48State, RCC_OscInitTypeDef::HSICalibrationValue, RCC_OscInitTypeDef::HSIState, LL_RCC_HSI_GetCalibTrimming(), LL_RCC_MSI_GetCalibTrimming(), LL_RCC_MSI_GetRange(), LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetMainSource(), LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP(), LL_RCC_PLL_GetQ(), LL_RCC_PLL_GetR(), RCC_OscInitTypeDef::LSEState, RCC_OscInitTypeDef::LSIState, RCC_OscInitTypeDef::MSICalibrationValue, RCC_OscInitTypeDef::MSIClockRange, RCC_OscInitTypeDef::MSIState, RCC_OscInitTypeDef::OscillatorType, RCC_OscInitTypeDef::PLL, RCC_PLLInitTypeDef::PLLM, RCC_PLLInitTypeDef::PLLN, RCC_PLLInitTypeDef::PLLP, RCC_PLLInitTypeDef::PLLQ, RCC_PLLInitTypeDef::PLLR, RCC_PLLInitTypeDef::PLLSource, RCC_PLLInitTypeDef::PLLState, RCC_HSE_BYPASS, RCC_HSE_OFF, RCC_HSE_ON, RCC_HSI48_OFF, RCC_HSI48_ON, RCC_HSI_OFF, RCC_HSI_ON, RCC_LSE_BYPASS, RCC_LSE_OFF, RCC_LSE_ON, RCC_LSI_OFF, RCC_LSI_ON, RCC_MSI_OFF, RCC_MSI_ON, RCC_OSCILLATORTYPE_HSE, RCC_OSCILLATORTYPE_HSI, RCC_OSCILLATORTYPE_HSI48, RCC_OSCILLATORTYPE_LSI1, RCC_OSCILLATORTYPE_LSI2, RCC_OSCILLATORTYPE_MSI, RCC_PLL_OFF, and RCC_PLL_ON.

uint32_t HAL_RCC_GetPCLK1Freq ( void )

Return the PCLK1 frequency.

Note:
Each time PCLK1 changes, this function must be called to update the right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
Return values:
PCLK1 frequency in Hz

Definition at line 1445 of file stm32wbxx_hal_rcc.c.

References __LL_RCC_CALC_PCLK1_FREQ, HAL_RCC_GetHCLKFreq(), and LL_RCC_GetAPB1Prescaler().

Referenced by UART_SetConfig().

uint32_t HAL_RCC_GetPCLK2Freq ( void )

Return the PCLK2 frequency.

Note:
Each time PCLK2 changes, this function must be called to update the right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
Return values:
PCLK2 frequency in Hz

Definition at line 1457 of file stm32wbxx_hal_rcc.c.

References __LL_RCC_CALC_PCLK2_FREQ, HAL_RCC_GetHCLKFreq(), and LL_RCC_GetAPB2Prescaler().

Referenced by IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

uint32_t HAL_RCC_GetSysClockFreq ( void )

Return the SYSCLK frequency.

Note:
The system computed by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the selected clock source:
If SYSCLK source is MSI, function returns values based on MSI range
If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
If SYSCLK source is PLL, function returns values based on HSE_VALUE(**), HSI_VALUE(*) or MSI Value multiplied/divided by the PLL factors.
(*) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value 16 MHz) but the real value may vary depending on the variations in voltage and temperature.
(**) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value 32 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may have wrong result.
The result of this function could be not correct when using fractional value for HSE crystal.
This function can be used by the user application to compute the baudrate for the communication peripherals or configure other parameters.
Each time SYSCLK changes, this function must be called to update the right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
Return values:
SYSCLK frequency

Definition at line 1350 of file stm32wbxx_hal_rcc.c.

References __HAL_RCC_GET_SYSCLK_SOURCE, __LL_RCC_CALC_MSI_FREQ, __LL_RCC_CALC_PLLCLK_FREQ, HSE_VALUE, HSI_VALUE, LL_RCC_HSE_IsEnabledDiv2(), LL_RCC_MSI_GetRange(), LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetMainSource(), LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR(), RCC_PLLSOURCE_HSE, RCC_PLLSOURCE_HSI, RCC_PLLSOURCE_MSI, RCC_SYSCLKSOURCE_STATUS_HSE, RCC_SYSCLKSOURCE_STATUS_HSI, and RCC_SYSCLKSOURCE_STATUS_MSI.

Referenced by HAL_RCC_GetHCLK2Freq(), HAL_RCC_GetHCLK4Freq(), HAL_RCC_GetHCLKFreq(), HAL_RCCEx_GetPeriphCLKFreq(), IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

void HAL_RCC_MCOConfig | ( | uint32_t | RCC_MCOx,
 |  | uint32_t | RCC_MCOSource,
 |  | uint32_t | RCC_MCODiv
 | ) |  |

Select the clock source to output on MCO1 pin(PA8) or MC02 pin (PB6) or MCO3 pin (PA15).

Note:
PA8, PB6 or PA15 should be configured in alternate function mode.
Parameters:
RCC_MCOx specifies the output direction for the clock source.
  • RCC_MCO1 Clock source to output on MCO1 pin(PA8)
  • RCC_MCO2 Clock source to output on MCO2 pin(PB6)
  • RCC_MCO3 Clock source to output on MCO3 pin(PA15)
RCC_MCOSource specifies the clock source to output. This parameter can be one of the following values:
  • RCC_MCO1SOURCE_NOCLOCK MCO output disabled, no clock on MCO
  • RCC_MCO1SOURCE_SYSCLK system clock selected as MCO source
  • RCC_MCO1SOURCE_MSI MSI clock selected as MCO source
  • RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
  • RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee
  • RCC_MCO1SOURCE_PLLCLK main PLL clock selected as MCO source
  • RCC_MCO1SOURCE_LSI1 LSI1 clock selected as MCO source
  • RCC_MCO1SOURCE_LSI2 LSI2 clock selected as MCO source
  • RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
  • RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48
  • RCC_MCO1SOURCE_HSE_BEFORE_STAB HSE clock before stabilization selected as MCO source
RCC_MCODiv specifies the MCO prescaler. This parameter can be one of the following values:
  • RCC_MCODIV_1 no division applied to MCO clock
  • RCC_MCODIV_2 division by 2 applied to MCO clock
  • RCC_MCODIV_4 division by 4 applied to MCO clock
  • RCC_MCODIV_8 division by 8 applied to MCO clock
  • RCC_MCODIV_16 division by 16 applied to MCO clock
Return values:
None

Definition at line 1270 of file stm32wbxx_hal_rcc.c.

References __MCO1_CLK_ENABLE, __MCO2_CLK_ENABLE, __MCO3_CLK_ENABLE, GPIO_InitTypeDef::Alternate, assert_param, GPIO_AF0_MCO, GPIO_AF6_MCO, GPIO_MODE_AF_PP, GPIO_NOPULL, GPIO_SPEED_FREQ_VERY_HIGH, HAL_GPIO_Init(), IS_RCC_MCO, IS_RCC_MCO1SOURCE, IS_RCC_MCODIV, LL_RCC_ConfigMCO(), MCO1_GPIO_PORT, MCO1_PIN, MCO2_GPIO_PORT, MCO2_PIN, MCO3_GPIO_PORT, MCO3_PIN, GPIO_InitTypeDef::Mode, GPIO_InitTypeDef::Pin, GPIO_InitTypeDef::Pull, RCC_MCO1, RCC_MCO2, and GPIO_InitTypeDef::Speed.

void HAL_RCC_NMI_IRQHandler ( void )

Handle the RCC HSE Clock Security System interrupt request.

Note:
This API should be called under the NMI_Handler().
Return values:
None

Definition at line 1632 of file stm32wbxx_hal_rcc.c.

References __HAL_RCC_CLEAR_IT, __HAL_RCC_GET_IT, HAL_RCC_CSSCallback(), and RCC_IT_HSECSS.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RCC_PLLInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_PLLInitTypeDef Struct Reference
RCC Exported Types

RCC PLL configuration structure definition. More...

#include <stm32wbxx_hal_rcc.h>

Data Fields

uint32_t | PLLState
uint32_t | PLLSource
uint32_t | PLLM
uint32_t | PLLN
uint32_t | PLLP
uint32_t | PLLQ
uint32_t | PLLR

Detailed Description

RCC PLL configuration structure definition.

Definition at line 211 of file stm32wbxx_hal_rcc.h.

Field Documentation

uint32_t RCC_PLLInitTypeDef::PLLM

PLLM: Division factor for PLL VCO input clock. This parameter must be a value of PLLM Clock Divider

Definition at line 219 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLN

PLLN: Multiplication factor for PLL VCO output clock. This parameter must be a number between Min_Data = 6 and Max_Data = 127

Definition at line 222 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLP

PLLP: Division factor for SAI & ADC clock. This parameter must be a value of PLLP Clock Divider

Definition at line 225 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLQ

PLLQ: Division factor for RNG and USB clocks. This parameter must be a value of PLLQ Clock Divider

Definition at line 228 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLR

PLLR: Division for the main system clock. User have to set the PLLR parameter correctly to not exceed max frequency 64MHZ. This parameter must be a value of PLLR Clock Divider

Definition at line 231 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLSource

RCC_PLLSource: PLL entry clock source. This parameter must be a value of PLL Clock Source

Definition at line 216 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLState

The new state of the PLL. This parameter must be a value of PLL Config

Definition at line 213 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_rcc.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RCC_OscInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_OscInitTypeDef Struct Reference
RCC Exported Types

RCC Internal/External Oscillator (HSE, HSI, HSI48, MSI, LSE and LSI) configuration structure definition. More...

#include <stm32wbxx_hal_rcc.h>

Data Fields

uint32_t | OscillatorType
uint32_t | HSEState
uint32_t | LSEState
uint32_t | HSIState
uint32_t | HSICalibrationValue
uint32_t | LSIState
uint32_t | LSI2CalibrationValue
uint32_t | MSIState
uint32_t | MSICalibrationValue
uint32_t | MSIClockRange
uint32_t | HSI48State
RCC_PLLInitTypeDef PLL

Detailed Description

RCC Internal/External Oscillator (HSE, HSI, HSI48, MSI, LSE and LSI) configuration structure definition.

Definition at line 240 of file stm32wbxx_hal_rcc.h.

Field Documentation

uint32_t RCC_OscInitTypeDef::HSEState

The new state of the HSE. This parameter can be a value of HSE Config

Definition at line 245 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::HSI48State

The new state of the HSI48 . This parameter can be a value of HSI48 Config

Definition at line 271 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::HSICalibrationValue

The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).

Definition at line 254 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::HSIState

The new state of the HSI. This parameter can be a value of HSI Config

Definition at line 251 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::LSEState

The new state of the LSE. This parameter can be a value of LSE Config

Definition at line 248 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::LSI2CalibrationValue

The LSI2 calibration trimming value . This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 259 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::LSIState

The new state of the LSI. This parameter can be a value of LSI Config

Definition at line 256 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::MSICalibrationValue

The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT). This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF

Definition at line 265 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::MSIClockRange

The MSI frequency range. This parameter can be a value of MSI Clock Range

Definition at line 268 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::MSIState

The new state of the MSI. This parameter can be a value of MSI Config

Definition at line 262 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::OscillatorType

The oscillators to be configured. This parameter can be a combination of Oscillator Type

Definition at line 242 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

RCC_PLLInitTypeDef RCC_OscInitTypeDef::PLL

Main PLL structure parameters

Definition at line 274 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_rcc.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RCC_ClkInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_ClkInitTypeDef Struct Reference
RCC Exported Types

RCC System, AHB and APB buses clock configuration structure definition. More...

#include <stm32wbxx_hal_rcc.h>

Data Fields

uint32_t | ClockType
uint32_t | SYSCLKSource
uint32_t | AHBCLKDivider
uint32_t | APB1CLKDivider
uint32_t | APB2CLKDivider
uint32_t | AHBCLK2Divider
uint32_t | AHBCLK4Divider

Detailed Description

RCC System, AHB and APB buses clock configuration structure definition.

Definition at line 281 of file stm32wbxx_hal_rcc.h.

Field Documentation

uint32_t RCC_ClkInitTypeDef::AHBCLK2Divider

The AHB clock (HCLK2) divider. This clock is derived from the system clock (SYSCLK). This parameter can be a value of AHB Clock Source

Definition at line 298 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::AHBCLK4Divider

The AHB shared clock (HCLK4) divider. This clock is derived from the system clock (SYSCLK). This parameter can be a value of AHB Clock Source

Definition at line 301 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::AHBCLKDivider

The AHBx clock (HCLK1) divider. This clock is derived from the system clock (SYSCLK). This parameter can be a value of AHB Clock Source

Definition at line 289 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::APB1CLKDivider

The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of APB1 Clock Source

Definition at line 292 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::APB2CLKDivider

The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of APB1 Clock Source

Definition at line 295 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::ClockType

The clock to be configured. This parameter can be a combination of System Clock Type

Definition at line 283 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::SYSCLKSource

The clock source used as system clock (SYSCLK). This parameter can be a value of System Clock Source

Definition at line 286 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_rcc.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Timeout Values

Defines
Timeout Values
RCC Exported Constants

Defines

#define | RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
#define | RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT /* LSE timeout in ms */

Define Documentation

#define RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */

Definition at line 318 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT /* LSE timeout in ms */

Definition at line 319 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Oscillator Type

Defines
Oscillator Type
RCC Exported Constants

Defines

#define | RCC_OSCILLATORTYPE_NONE 0x00000000U
#define | RCC_OSCILLATORTYPE_HSE 0x00000001U
#define | RCC_OSCILLATORTYPE_HSI 0x00000002U
#define | RCC_OSCILLATORTYPE_LSE 0x00000004U
#define | RCC_OSCILLATORTYPE_LSI1 0x00000008U
#define | RCC_OSCILLATORTYPE_LSI2 0x00000010U
#define | RCC_OSCILLATORTYPE_MSI 0x00000020U
#define | RCC_OSCILLATORTYPE_HSI48 0x00000040U

Define Documentation

#define RCC_OSCILLATORTYPE_HSE 0x00000001U

HSE to configure

Definition at line 328 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_HSI 0x00000002U

HSI to configure

Definition at line 329 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_HSI48 0x00000040U

HSI48 to configure

Definition at line 334 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_LSE 0x00000004U

LSE to configure

Definition at line 330 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_LSI1 0x00000008U

LSI1 to configure

Definition at line 331 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_LSI2 0x00000010U

LSI2 to configure

Definition at line 332 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), HAL_RCC_OscConfig(), and HAL_RCCEx_TrimOsc().

#define RCC_OSCILLATORTYPE_MSI 0x00000020U

MSI to configure

Definition at line 333 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_NONE 0x00000000U

Oscillator configuration unchanged

Definition at line 327 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: HSE Config

Defines
HSE Config
RCC Exported Constants

Defines

#define | RCC_HSE_OFF 0x00000000U
#define | RCC_HSE_ON RCC_CR_HSEON
#define | RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))

Define Documentation

#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))

External clock source for HSE clock

Definition at line 344 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

#define RCC_HSE_OFF 0x00000000U

HSE clock deactivation

Definition at line 342 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_HSE_ON RCC_CR_HSEON

HSE clock activation

Definition at line 343 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LSE Config

Defines
LSE Config
RCC Exported Constants

Defines

#define | RCC_LSE_OFF 0x00000000U
#define | RCC_LSE_ON RCC_BDCR_LSEON
#define | RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))

Define Documentation

#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))

External clock source for LSE clock

Definition at line 354 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

#define RCC_LSE_OFF 0x00000000U

LSE clock deactivation

Definition at line 352 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_LSE_ON RCC_BDCR_LSEON

LSE clock activation

Definition at line 353 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: HSI Config

Defines
HSI Config
RCC Exported Constants

Defines

#define | RCC_HSI_OFF 0x00000000U
#define | RCC_HSI_ON RCC_CR_HSION
#define | RCC_HSICALIBRATION_DEFAULT 64U

Define Documentation

#define RCC_HSI_OFF 0x00000000U

HSI clock deactivation

Definition at line 362 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_HSI_ON RCC_CR_HSION

HSI clock activation

Definition at line 363 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

#define RCC_HSICALIBRATION_DEFAULT 64U

Default HSI calibration trimming value

Definition at line 365 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LSI Config

Defines
LSI Config
RCC Exported Constants

Defines

#define | RCC_LSI_OFF 0x00000000U
#define | RCC_LSI_ON (RCC_CSR_LSI1ON | RCC_CSR_LSI2ON)

Define Documentation

#define RCC_LSI_OFF 0x00000000U

LSI clock deactivation

Definition at line 373 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_LSI_ON (RCC_CSR_LSI1ON | RCC_CSR_LSI2ON)

LSI1 or LSI2 clock activation

Definition at line 374 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: MSI Config

Defines
MSI Config
RCC Exported Constants

Defines

#define | RCC_MSI_OFF 0x00000000U
#define | RCC_MSI_ON RCC_CR_MSION
#define | RCC_MSICALIBRATION_DEFAULT 0U

Define Documentation

#define RCC_MSI_OFF 0x00000000U

MSI clock deactivation

Definition at line 382 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_MSI_ON RCC_CR_MSION

MSI clock activation

Definition at line 383 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

#define RCC_MSICALIBRATION_DEFAULT 0U

Default MSI calibration trimming value

Definition at line 385 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: HSI48 Config

Defines
HSI48 Config
RCC Exported Constants

Defines

#define | RCC_HSI48_OFF 0x00000000U
#define | RCC_HSI48_ON RCC_CRRCR_HSI48ON

Define Documentation

#define RCC_HSI48_OFF 0x00000000U

HSI48 clock deactivation

Definition at line 394 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_HSI48_ON RCC_CRRCR_HSI48ON

HSI48 clock activation

Definition at line 395 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PLL Config

Defines
PLL Config
RCC Exported Constants

Defines

#define | RCC_PLL_NONE 0x00000000U
#define | RCC_PLL_OFF 0x00000001U
#define | RCC_PLL_ON 0x00000002U

Define Documentation

#define RCC_PLL_NONE 0x00000000U

PLL configuration unchanged

Definition at line 404 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define RCC_PLL_OFF 0x00000001U

PLL deactivation

Definition at line 405 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_PLL_ON 0x00000002U

PLL activation

Definition at line 406 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PLLM Clock Divider

Defines
PLLM Clock Divider
RCC Exported Constants

Defines

#define | RCC_PLLM_DIV1 LL_RCC_PLLM_DIV_1
#define | RCC_PLLM_DIV2 LL_RCC_PLLM_DIV_2
#define | RCC_PLLM_DIV3 LL_RCC_PLLM_DIV_3
#define | RCC_PLLM_DIV4 LL_RCC_PLLM_DIV_4
#define | RCC_PLLM_DIV5 LL_RCC_PLLM_DIV_5
#define | RCC_PLLM_DIV6 LL_RCC_PLLM_DIV_6
#define | RCC_PLLM_DIV7 LL_RCC_PLLM_DIV_7
#define | RCC_PLLM_DIV8 LL_RCC_PLLM_DIV_8

Define Documentation

#define RCC_PLLM_DIV1 LL_RCC_PLLM_DIV_1

PLLM division factor = 1

Definition at line 414 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLM_DIV2 LL_RCC_PLLM_DIV_2

PLLM division factor = 2

Definition at line 415 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLM_DIV3 LL_RCC_PLLM_DIV_3

PLLM division factor = 3

Definition at line 416 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLM_DIV4 LL_RCC_PLLM_DIV_4

PLLM division factor = 4

Definition at line 417 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLM_DIV5 LL_RCC_PLLM_DIV_5

PLLM division factor = 5

Definition at line 418 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLM_DIV6 LL_RCC_PLLM_DIV_6

PLLM division factor = 6

Definition at line 419 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLM_DIV7 LL_RCC_PLLM_DIV_7

PLLM division factor = 7

Definition at line 420 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLM_DIV8 LL_RCC_PLLM_DIV_8

PLLM division factor = 8

Definition at line 421 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PLLP Clock Divider

Defines
PLLP Clock Divider
RCC Exported Constants

Defines

#define | RCC_PLLP_DIV2 LL_RCC_PLLP_DIV_2
#define | RCC_PLLP_DIV3 LL_RCC_PLLP_DIV_3
#define | RCC_PLLP_DIV4 LL_RCC_PLLP_DIV_4
#define | RCC_PLLP_DIV5 LL_RCC_PLLP_DIV_5
#define | RCC_PLLP_DIV6 LL_RCC_PLLP_DIV_6
#define | RCC_PLLP_DIV7 LL_RCC_PLLP_DIV_7
#define | RCC_PLLP_DIV8 LL_RCC_PLLP_DIV_8
#define | RCC_PLLP_DIV9 LL_RCC_PLLP_DIV_9
#define | RCC_PLLP_DIV10 LL_RCC_PLLP_DIV_10
#define | RCC_PLLP_DIV11 LL_RCC_PLLP_DIV_11
#define | RCC_PLLP_DIV12 LL_RCC_PLLP_DIV_12
#define | RCC_PLLP_DIV13 LL_RCC_PLLP_DIV_13
#define | RCC_PLLP_DIV14 LL_RCC_PLLP_DIV_14
#define | RCC_PLLP_DIV15 LL_RCC_PLLP_DIV_15
#define | RCC_PLLP_DIV16 LL_RCC_PLLP_DIV_16
#define | RCC_PLLP_DIV17 LL_RCC_PLLP_DIV_17
#define | RCC_PLLP_DIV18 LL_RCC_PLLP_DIV_18
#define | RCC_PLLP_DIV19 LL_RCC_PLLP_DIV_19
#define | RCC_PLLP_DIV20 LL_RCC_PLLP_DIV_20
#define | RCC_PLLP_DIV21 LL_RCC_PLLP_DIV_21
#define | RCC_PLLP_DIV22 LL_RCC_PLLP_DIV_22
#define | RCC_PLLP_DIV23 LL_RCC_PLLP_DIV_23
#define | RCC_PLLP_DIV24 LL_RCC_PLLP_DIV_24
#define | RCC_PLLP_DIV25 LL_RCC_PLLP_DIV_25
#define | RCC_PLLP_DIV26 LL_RCC_PLLP_DIV_26
#define | RCC_PLLP_DIV27 LL_RCC_PLLP_DIV_27
#define | RCC_PLLP_DIV28 LL_RCC_PLLP_DIV_28
#define | RCC_PLLP_DIV29 LL_RCC_PLLP_DIV_29
#define | RCC_PLLP_DIV30 LL_RCC_PLLP_DIV_30
#define | RCC_PLLP_DIV31 LL_RCC_PLLP_DIV_31
#define | RCC_PLLP_DIV32 LL_RCC_PLLP_DIV_32

Define Documentation

#define RCC_PLLP_DIV10 LL_RCC_PLLP_DIV_10

PLLP division factor = 10

Definition at line 437 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLP_DIV11 LL_RCC_PLLP_DIV_11

PLLP division factor = 11

Definition at line 438 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLP_DIV12 LL_RCC_PLLP_DIV_12

PLLP division factor = 12

Definition at line 439 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLP_DIV13 LL_RCC_PLLP_DIV_13

PLLP division factor = 13

Definition at line 440 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLP_DIV14 LL_RCC_PLLP_DIV_14

PLLP division factor = 14

Definition at line 441 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLP_DIV15 LL_RCC_PLLP_DIV_15

PLLP division factor = 15

Definition at line 442 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLP_DIV16 LL_RCC_PLLP_DIV_16

PLLP division factor = 16

Definition at line 443 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLP_DIV17 LL_RCC_PLLP_DIV_17

PLLP division factor = 17

Definition at line 444 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLP_DIV18 LL_RCC_PLLP_DIV_18

PLLP division factor = 18

Definition at line 445 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLP_DIV19 LL_RCC_PLLP_DIV_19

PLLP division factor = 19

Definition at line 446 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLP_DIV2 LL_RCC_PLLP_DIV_2

PLLP division factor = 2

Definition at line 429 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLP_DIV20 LL_RCC_PLLP_DIV_20

PLLP division factor = 20

Definition at line 447 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLP_DIV21 LL_RCC_PLLP_DIV_21

PLLP division factor = 21

Definition at line 448 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLP_DIV22 LL_RCC_PLLP_DIV_22

PLLP division factor = 22

Definition at line 449 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLP_DIV23 LL_RCC_PLLP_DIV_23

PLLP division factor = 23

Definition at line 450 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLP_DIV24 LL_RCC_PLLP_DIV_24

PLLP division factor = 24

Definition at line 451 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLP_DIV25 LL_RCC_PLLP_DIV_25

PLLP division factor = 25

Definition at line 452 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLP_DIV26 LL_RCC_PLLP_DIV_26

PLLP division factor = 26

Definition at line 453 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLP_DIV27 LL_RCC_PLLP_DIV_27

PLLP division factor = 27

Definition at line 454 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLP_DIV28 LL_RCC_PLLP_DIV_28

PLLP division factor = 28

Definition at line 455 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLP_DIV29 LL_RCC_PLLP_DIV_29

PLLP division factor = 29

Definition at line 456 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLP_DIV3 LL_RCC_PLLP_DIV_3

PLLP division factor = 3

Definition at line 430 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLP_DIV30 LL_RCC_PLLP_DIV_30

PLLP division factor = 30

Definition at line 457 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLP_DIV31 LL_RCC_PLLP_DIV_31

PLLP division factor = 31

Definition at line 458 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLP_DIV32 LL_RCC_PLLP_DIV_32

PLLP division factor = 32

Definition at line 459 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLP_DIV4 LL_RCC_PLLP_DIV_4

PLLP division factor = 4

Definition at line 431 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLP_DIV5 LL_RCC_PLLP_DIV_5

PLLP division factor = 5

Definition at line 432 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLP_DIV6 LL_RCC_PLLP_DIV_6

PLLP division factor = 6

Definition at line 433 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLP_DIV7 LL_RCC_PLLP_DIV_7

PLLP division factor = 7

Definition at line 434 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLP_DIV8 LL_RCC_PLLP_DIV_8

PLLP division factor = 8

Definition at line 435 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLP_DIV9 LL_RCC_PLLP_DIV_9

PLLP division factor = 9

Definition at line 436 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PLLQ Clock Divider

Defines
PLLQ Clock Divider
RCC Exported Constants

Defines

#define | RCC_PLLQ_DIV2 LL_RCC_PLLQ_DIV_2
#define | RCC_PLLQ_DIV3 LL_RCC_PLLQ_DIV_3
#define | RCC_PLLQ_DIV4 LL_RCC_PLLQ_DIV_4
#define | RCC_PLLQ_DIV5 LL_RCC_PLLQ_DIV_5
#define | RCC_PLLQ_DIV6 LL_RCC_PLLQ_DIV_6
#define | RCC_PLLQ_DIV7 LL_RCC_PLLQ_DIV_7
#define | RCC_PLLQ_DIV8 LL_RCC_PLLQ_DIV_8

Define Documentation

#define RCC_PLLQ_DIV2 LL_RCC_PLLQ_DIV_2

PLLQ division factor = 2

Definition at line 467 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLQ_DIV3 LL_RCC_PLLQ_DIV_3

PLLQ division factor = 3

Definition at line 468 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLQ_DIV4 LL_RCC_PLLQ_DIV_4

PLLQ division factor = 4

Definition at line 469 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLQ_DIV5 LL_RCC_PLLQ_DIV_5

PLLQ division factor = 5

Definition at line 470 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLQ_DIV6 LL_RCC_PLLQ_DIV_6

PLLQ division factor = 6

Definition at line 471 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLQ_DIV7 LL_RCC_PLLQ_DIV_7

PLLQ division factor = 7

Definition at line 472 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLQ_DIV8 LL_RCC_PLLQ_DIV_8

PLLQ division factor = 8

Definition at line 473 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PLLR Clock Divider

Defines
PLLR Clock Divider
RCC Exported Constants

Defines

#define | RCC_PLLR_DIV2 LL_RCC_PLLR_DIV_2
#define | RCC_PLLR_DIV3 LL_RCC_PLLR_DIV_3
#define | RCC_PLLR_DIV4 LL_RCC_PLLR_DIV_4
#define | RCC_PLLR_DIV5 LL_RCC_PLLR_DIV_5
#define | RCC_PLLR_DIV6 LL_RCC_PLLR_DIV_6
#define | RCC_PLLR_DIV7 LL_RCC_PLLR_DIV_7
#define | RCC_PLLR_DIV8 LL_RCC_PLLR_DIV_8

Define Documentation

#define RCC_PLLR_DIV2 LL_RCC_PLLR_DIV_2

PLLR division factor = 2

Definition at line 481 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLR_DIV3 LL_RCC_PLLR_DIV_3

PLLR division factor = 3

Definition at line 482 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLR_DIV4 LL_RCC_PLLR_DIV_4

PLLR division factor = 4

Definition at line 483 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLR_DIV5 LL_RCC_PLLR_DIV_5

PLLR division factor = 5

Definition at line 484 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLR_DIV6 LL_RCC_PLLR_DIV_6

PLLR division factor = 6

Definition at line 485 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLR_DIV7 LL_RCC_PLLR_DIV_7

PLLR division factor = 7

Definition at line 486 of file stm32wbxx_hal_rcc.h.

#define RCC_PLLR_DIV8 LL_RCC_PLLR_DIV_8

PLLR division factor = 8

Definition at line 487 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PLL Clock Source

Defines
PLL Clock Source
RCC Exported Constants

Defines

#define | RCC_PLLSOURCE_NONE LL_RCC_PLLSOURCE_NONE
#define | RCC_PLLSOURCE_MSI LL_RCC_PLLSOURCE_MSI
#define | RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSI
#define | RCC_PLLSOURCE_HSE LL_RCC_PLLSOURCE_HSE

Define Documentation

#define RCC_PLLSOURCE_HSE LL_RCC_PLLSOURCE_HSE

HSE clock selected as PLL entry clock source

Definition at line 498 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetSysClockFreq(), and HAL_RCC_OscConfig().

#define RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSI

HSI clock selected as PLL entry clock source

Definition at line 497 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetSysClockFreq(), and HAL_RCC_OscConfig().

#define RCC_PLLSOURCE_MSI LL_RCC_PLLSOURCE_MSI

MSI clock selected as PLL entry clock source

Definition at line 496 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetSysClockFreq(), and HAL_RCC_OscConfig().

#define RCC_PLLSOURCE_NONE LL_RCC_PLLSOURCE_NONE

No clock selected as PLL entry clock source

Definition at line 495 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PLL Clock Output

Defines
PLL Clock Output
RCC Exported Constants

Defines

#define | RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN
#define | RCC_PLL_USBCLK RCC_PLLCFGR_PLLQEN
#define | RCC_PLL_RNGCLK RCC_PLLCFGR_PLLQEN
#define | RCC_PLL_SAI1CLK RCC_PLLCFGR_PLLPEN
#define | RCC_PLL_ADCCLK RCC_PLLCFGR_PLLPEN

Define Documentation

#define RCC_PLL_ADCCLK RCC_PLLCFGR_PLLPEN

PLLADCCLK selection from main PLL

Definition at line 512 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_PLL_RNGCLK RCC_PLLCFGR_PLLQEN

PLLRNGCLK selection from main PLL

Definition at line 508 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_PLL_SAI1CLK RCC_PLLCFGR_PLLPEN

PLLSAI1CLK selection from main PLL

Definition at line 510 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN

PLLCLK selection from main PLL

Definition at line 506 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define RCC_PLL_USBCLK RCC_PLLCFGR_PLLQEN

PLLUSBCLK selection from main PLL

Definition at line 507 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PLLSAI1 Clock Output

Defines
PLLSAI1 Clock Output
RCC Exported Constants

Defines

#define | RCC_PLLSAI1_ADCCLK RCC_PLLSAI1CFGR_PLLREN
#define | RCC_PLLSAI1_USBCLK RCC_PLLSAI1CFGR_PLLQEN
#define | RCC_PLLSAI1_SAI1CLK RCC_PLLSAI1CFGR_PLLPEN

Define Documentation

#define RCC_PLLSAI1_ADCCLK RCC_PLLSAI1CFGR_PLLREN

PLLADCCLK selection from PLLSAI1

Definition at line 521 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCCEx_DisablePLLSAI1().

#define RCC_PLLSAI1_SAI1CLK RCC_PLLSAI1CFGR_PLLPEN

PLLSAI1CLK selection from PLLSAI1

Definition at line 523 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCCEx_DisablePLLSAI1().

#define RCC_PLLSAI1_USBCLK RCC_PLLSAI1CFGR_PLLQEN

USBCLK selection from PLLSAI1

Definition at line 522 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCCEx_DisablePLLSAI1().

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: MSI Clock Range

Defines
MSI Clock Range
RCC Exported Constants

Defines

#define | RCC_MSIRANGE_0 LL_RCC_MSIRANGE_0
#define | RCC_MSIRANGE_1 LL_RCC_MSIRANGE_1
#define | RCC_MSIRANGE_2 LL_RCC_MSIRANGE_2
#define | RCC_MSIRANGE_3 LL_RCC_MSIRANGE_3
#define | RCC_MSIRANGE_4 LL_RCC_MSIRANGE_4
#define | RCC_MSIRANGE_5 LL_RCC_MSIRANGE_5
#define | RCC_MSIRANGE_6 LL_RCC_MSIRANGE_6
#define | RCC_MSIRANGE_7 LL_RCC_MSIRANGE_7
#define | RCC_MSIRANGE_8 LL_RCC_MSIRANGE_8
#define | RCC_MSIRANGE_9 LL_RCC_MSIRANGE_9
#define | RCC_MSIRANGE_10 LL_RCC_MSIRANGE_10
#define | RCC_MSIRANGE_11 LL_RCC_MSIRANGE_11

Define Documentation

#define RCC_MSIRANGE_0 LL_RCC_MSIRANGE_0

MSI = 100 KHz

Definition at line 532 of file stm32wbxx_hal_rcc.h.

#define RCC_MSIRANGE_1 LL_RCC_MSIRANGE_1

MSI = 200 KHz

Definition at line 533 of file stm32wbxx_hal_rcc.h.

#define RCC_MSIRANGE_10 LL_RCC_MSIRANGE_10

MSI = 32 MHz

Definition at line 542 of file stm32wbxx_hal_rcc.h.

#define RCC_MSIRANGE_11 LL_RCC_MSIRANGE_11

MSI = 48 MHz

Definition at line 543 of file stm32wbxx_hal_rcc.h.

Referenced by RCC_SetFlashLatencyFromMSIRange().

#define RCC_MSIRANGE_2 LL_RCC_MSIRANGE_2

MSI = 400 KHz

Definition at line 534 of file stm32wbxx_hal_rcc.h.

#define RCC_MSIRANGE_3 LL_RCC_MSIRANGE_3

MSI = 800 KHz

Definition at line 535 of file stm32wbxx_hal_rcc.h.

#define RCC_MSIRANGE_4 LL_RCC_MSIRANGE_4

MSI = 1 MHz

Definition at line 536 of file stm32wbxx_hal_rcc.h.

#define RCC_MSIRANGE_5 LL_RCC_MSIRANGE_5

MSI = 2 MHz

Definition at line 537 of file stm32wbxx_hal_rcc.h.

#define RCC_MSIRANGE_6 LL_RCC_MSIRANGE_6

MSI = 4 MHz

Definition at line 538 of file stm32wbxx_hal_rcc.h.

#define RCC_MSIRANGE_7 LL_RCC_MSIRANGE_7

MSI = 8 MHz

Definition at line 539 of file stm32wbxx_hal_rcc.h.

#define RCC_MSIRANGE_8 LL_RCC_MSIRANGE_8

MSI = 16 MHz

Definition at line 540 of file stm32wbxx_hal_rcc.h.

#define RCC_MSIRANGE_9 LL_RCC_MSIRANGE_9

MSI = 24 MHz

Definition at line 541 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: System Clock Type

Defines
System Clock Type
RCC Exported Constants

Defines

#define | RCC_CLOCKTYPE_SYSCLK 0x00000001U
#define | RCC_CLOCKTYPE_HCLK 0x00000002U
#define | RCC_CLOCKTYPE_PCLK1 0x00000004U
#define | RCC_CLOCKTYPE_PCLK2 0x00000008U
#define | RCC_CLOCKTYPE_HCLK2 0x00000020U
#define | RCC_CLOCKTYPE_HCLK4 0x00000040U

Define Documentation

#define RCC_CLOCKTYPE_HCLK 0x00000002U

HCLK to configure

Definition at line 552 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

#define RCC_CLOCKTYPE_HCLK2 0x00000020U

HCLK2 to configure

Definition at line 555 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define RCC_CLOCKTYPE_HCLK4 0x00000040U

HCLK4 to configure

Definition at line 556 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

#define RCC_CLOCKTYPE_PCLK1 0x00000004U

PCLK1 to configure

Definition at line 553 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

#define RCC_CLOCKTYPE_PCLK2 0x00000008U

PCLK2 to configure

Definition at line 554 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

#define RCC_CLOCKTYPE_SYSCLK 0x00000001U

SYSCLK to configure

Definition at line 551 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: System Clock Source

Defines
System Clock Source
RCC Exported Constants

Defines

#define | RCC_SYSCLKSOURCE_MSI LL_RCC_SYS_CLKSOURCE_MSI
#define | RCC_SYSCLKSOURCE_HSI LL_RCC_SYS_CLKSOURCE_HSI
#define | RCC_SYSCLKSOURCE_HSE LL_RCC_SYS_CLKSOURCE_HSE
#define | RCC_SYSCLKSOURCE_PLLCLK LL_RCC_SYS_CLKSOURCE_PLL

Define Documentation

#define RCC_SYSCLKSOURCE_HSE LL_RCC_SYS_CLKSOURCE_HSE

HSE selection as system clock

Definition at line 566 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define RCC_SYSCLKSOURCE_HSI LL_RCC_SYS_CLKSOURCE_HSI

HSI selection as system clock

Definition at line 565 of file stm32wbxx_hal_rcc.h.

#define RCC_SYSCLKSOURCE_MSI LL_RCC_SYS_CLKSOURCE_MSI

MSI selection as system clock

Definition at line 564 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define RCC_SYSCLKSOURCE_PLLCLK LL_RCC_SYS_CLKSOURCE_PLL

PLL selection as system clock

Definition at line 567 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

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STM32WB55xx HAL User Manual: System Clock Source Status

Defines
System Clock Source Status
RCC Exported Constants | RCCEx Exported Constants

Defines

#define | RCC_SYSCLKSOURCE_STATUS_MSI LL_RCC_SYS_CLKSOURCE_STATUS_MSI
#define | RCC_SYSCLKSOURCE_STATUS_HSI LL_RCC_SYS_CLKSOURCE_STATUS_HSI
#define | RCC_SYSCLKSOURCE_STATUS_HSE LL_RCC_SYS_CLKSOURCE_STATUS_HSE
#define | RCC_SYSCLKSOURCE_STATUS_PLLCLK LL_RCC_SYS_CLKSOURCE_STATUS_PLL
#define | RCC_SMPSCLKSOURCE_STATUS_HSI LL_RCC_SMPS_CLKSOURCE_STATUS_HSI
#define | RCC_SMPSCLKSOURCE_STATUS_MSI LL_RCC_SMPS_CLKSOURCE_STATUS_MSI
#define | RCC_SMPSCLKSOURCE_STATUS_HSE LL_RCC_SMPS_CLKSOURCE_STATUS_HSE

Define Documentation

#define RCC_SMPSCLKSOURCE_STATUS_HSE LL_RCC_SMPS_CLKSOURCE_STATUS_HSE

HSE selection as smps clock

Definition at line 597 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_SMPSCLKSOURCE_STATUS_HSI LL_RCC_SMPS_CLKSOURCE_STATUS_HSI

HSI selection as smps clock

Definition at line 595 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_SMPSCLKSOURCE_STATUS_MSI LL_RCC_SMPS_CLKSOURCE_STATUS_MSI

MSI selection as smps clock

Definition at line 596 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_SYSCLKSOURCE_STATUS_HSE LL_RCC_SYS_CLKSOURCE_STATUS_HSE

HSE used as system clock

Definition at line 577 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetSysClockFreq(), and HAL_RCC_OscConfig().

#define RCC_SYSCLKSOURCE_STATUS_HSI LL_RCC_SYS_CLKSOURCE_STATUS_HSI

HSI used as system clock

Definition at line 576 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetSysClockFreq(), and HAL_RCC_OscConfig().

#define RCC_SYSCLKSOURCE_STATUS_MSI LL_RCC_SYS_CLKSOURCE_STATUS_MSI

MSI used as system clock

Definition at line 575 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_GetSysClockFreq(), and HAL_RCC_OscConfig().

#define RCC_SYSCLKSOURCE_STATUS_PLLCLK LL_RCC_SYS_CLKSOURCE_STATUS_PLL

PLL used as system clock

Definition at line 578 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

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STM32WB55xx HAL User Manual: AHB Clock Source

Defines
AHB Clock Source
RCC Exported Constants

Defines

#define | RCC_SYSCLK_DIV1 LL_RCC_SYSCLK_DIV_1
#define | RCC_SYSCLK_DIV2 LL_RCC_SYSCLK_DIV_2
#define | RCC_SYSCLK_DIV3 LL_RCC_SYSCLK_DIV_3
#define | RCC_SYSCLK_DIV4 LL_RCC_SYSCLK_DIV_4
#define | RCC_SYSCLK_DIV5 LL_RCC_SYSCLK_DIV_5
#define | RCC_SYSCLK_DIV6 LL_RCC_SYSCLK_DIV_6
#define | RCC_SYSCLK_DIV8 LL_RCC_SYSCLK_DIV_8
#define | RCC_SYSCLK_DIV10 LL_RCC_SYSCLK_DIV_10
#define | RCC_SYSCLK_DIV16 LL_RCC_SYSCLK_DIV_16
#define | RCC_SYSCLK_DIV32 LL_RCC_SYSCLK_DIV_32
#define | RCC_SYSCLK_DIV64 LL_RCC_SYSCLK_DIV_64
#define | RCC_SYSCLK_DIV128 LL_RCC_SYSCLK_DIV_128
#define | RCC_SYSCLK_DIV256 LL_RCC_SYSCLK_DIV_256
#define | RCC_SYSCLK_DIV512 LL_RCC_SYSCLK_DIV_512

Define Documentation

#define RCC_SYSCLK_DIV1 LL_RCC_SYSCLK_DIV_1

SYSCLK not divided

Definition at line 586 of file stm32wbxx_hal_rcc.h.

#define RCC_SYSCLK_DIV10 LL_RCC_SYSCLK_DIV_10

SYSCLK divided by 10

Definition at line 593 of file stm32wbxx_hal_rcc.h.

#define RCC_SYSCLK_DIV128 LL_RCC_SYSCLK_DIV_128

SYSCLK divided by 128

Definition at line 597 of file stm32wbxx_hal_rcc.h.

#define RCC_SYSCLK_DIV16 LL_RCC_SYSCLK_DIV_16

SYSCLK divided by 16

Definition at line 594 of file stm32wbxx_hal_rcc.h.

#define RCC_SYSCLK_DIV2 LL_RCC_SYSCLK_DIV_2

SYSCLK divided by 2

Definition at line 587 of file stm32wbxx_hal_rcc.h.

#define RCC_SYSCLK_DIV256 LL_RCC_SYSCLK_DIV_256

SYSCLK divided by 256

Definition at line 598 of file stm32wbxx_hal_rcc.h.

#define RCC_SYSCLK_DIV3 LL_RCC_SYSCLK_DIV_3

SYSCLK divided by 3

Definition at line 588 of file stm32wbxx_hal_rcc.h.

#define RCC_SYSCLK_DIV32 LL_RCC_SYSCLK_DIV_32

SYSCLK divided by 32

Definition at line 595 of file stm32wbxx_hal_rcc.h.

#define RCC_SYSCLK_DIV4 LL_RCC_SYSCLK_DIV_4

SYSCLK divided by 4

Definition at line 589 of file stm32wbxx_hal_rcc.h.

#define RCC_SYSCLK_DIV5 LL_RCC_SYSCLK_DIV_5

SYSCLK divided by 5

Definition at line 590 of file stm32wbxx_hal_rcc.h.

#define RCC_SYSCLK_DIV512 LL_RCC_SYSCLK_DIV_512

SYSCLK divided by 512

Definition at line 599 of file stm32wbxx_hal_rcc.h.

#define RCC_SYSCLK_DIV6 LL_RCC_SYSCLK_DIV_6

SYSCLK divided by 6

Definition at line 591 of file stm32wbxx_hal_rcc.h.

#define RCC_SYSCLK_DIV64 LL_RCC_SYSCLK_DIV_64

SYSCLK divided by 64

Definition at line 596 of file stm32wbxx_hal_rcc.h.

#define RCC_SYSCLK_DIV8 LL_RCC_SYSCLK_DIV_8

SYSCLK divided by 8

Definition at line 592 of file stm32wbxx_hal_rcc.h.

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STM32WB55xx HAL User Manual: APB1 Clock Source

Defines
APB1 Clock Source
RCC Exported Constants

Defines

#define | RCC_HCLK_DIV1 LL_RCC_APB1_DIV_1
#define | RCC_HCLK_DIV2 LL_RCC_APB1_DIV_2
#define | RCC_HCLK_DIV4 LL_RCC_APB1_DIV_4
#define | RCC_HCLK_DIV8 LL_RCC_APB1_DIV_8
#define | RCC_HCLK_DIV16 LL_RCC_APB1_DIV_16

Define Documentation

#define RCC_HCLK_DIV1 LL_RCC_APB1_DIV_1

HCLK not divided

Definition at line 607 of file stm32wbxx_hal_rcc.h.

#define RCC_HCLK_DIV16 LL_RCC_APB1_DIV_16

HCLK divided by 16

Definition at line 611 of file stm32wbxx_hal_rcc.h.

#define RCC_HCLK_DIV2 LL_RCC_APB1_DIV_2

HCLK divided by 2

Definition at line 608 of file stm32wbxx_hal_rcc.h.

#define RCC_HCLK_DIV4 LL_RCC_APB1_DIV_4

HCLK divided by 4

Definition at line 609 of file stm32wbxx_hal_rcc.h.

#define RCC_HCLK_DIV8 LL_RCC_APB1_DIV_8

HCLK divided by 8

Definition at line 610 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC Clock Source

Defines
RTC Clock Source
RCC Exported Constants

Defines

#define | RCC_RTCCLKSOURCE_NONE LL_RCC_RTC_CLKSOURCE_NONE
#define | RCC_RTCCLKSOURCE_LSE LL_RCC_RTC_CLKSOURCE_LSE
#define | RCC_RTCCLKSOURCE_LSI LL_RCC_RTC_CLKSOURCE_LSI
#define | RCC_RTCCLKSOURCE_HSE_DIV32 LL_RCC_RTC_CLKSOURCE_HSE_DIV32

Define Documentation

#define RCC_RTCCLKSOURCE_HSE_DIV32 LL_RCC_RTC_CLKSOURCE_HSE_DIV32

HSE oscillator clock divided by 32 used as RTC clock

Definition at line 622 of file stm32wbxx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_LSE LL_RCC_RTC_CLKSOURCE_LSE

LSE oscillator clock used as RTC clock

Definition at line 620 of file stm32wbxx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_LSI LL_RCC_RTC_CLKSOURCE_LSI

LSI oscillator clock used as RTC clock

Definition at line 621 of file stm32wbxx_hal_rcc.h.

#define RCC_RTCCLKSOURCE_NONE LL_RCC_RTC_CLKSOURCE_NONE

No clock used as RTC clock

Definition at line 619 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

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STM32WB55xx HAL User Manual: MCO Index

Defines
MCO Index
RCC Exported Constants

Defines

#define | RCC_MCO1 0x00000000U
#define | RCC_MCO2 0x00000001U
#define | RCC_MCO3 0x00000002U
#define | RCC_MCO RCC_MCO1

Define Documentation

#define RCC_MCO RCC_MCO1

MCO1 to be compliant with other families with 1 MCO

Definition at line 634 of file stm32wbxx_hal_rcc.h.

#define RCC_MCO1 0x00000000U

MCO1 index

Definition at line 630 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define RCC_MCO2 0x00000001U

MCO2 index

Definition at line 631 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define RCC_MCO3 0x00000002U

MCO3 index

Definition at line 632 of file stm32wbxx_hal_rcc.h.

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STM32WB55xx HAL User Manual: MCO1 Clock Source

Defines
MCO1 Clock Source
RCC Exported Constants

Defines

#define | RCC_MCO1SOURCE_NOCLOCK LL_RCC_MCO1SOURCE_NOCLOCK
#define | RCC_MCO1SOURCE_SYSCLK LL_RCC_MCO1SOURCE_SYSCLK
#define | RCC_MCO1SOURCE_MSI LL_RCC_MCO1SOURCE_MSI
#define | RCC_MCO1SOURCE_HSI LL_RCC_MCO1SOURCE_HSI
#define | RCC_MCO1SOURCE_HSE LL_RCC_MCO1SOURCE_HSE
#define | RCC_MCO1SOURCE_PLLCLK LL_RCC_MCO1SOURCE_PLLCLK
#define | RCC_MCO1SOURCE_LSI1 LL_RCC_MCO1SOURCE_LSI1
#define | RCC_MCO1SOURCE_LSI2 LL_RCC_MCO1SOURCE_LSI2
#define | RCC_MCO1SOURCE_LSE LL_RCC_MCO1SOURCE_LSE
#define | RCC_MCO1SOURCE_HSI48 LL_RCC_MCO1SOURCE_HSI48
#define | RCC_MCO1SOURCE_HSE_BEFORE_STAB LL_RCC_MCO1SOURCE_HSE_BEFORE_STAB

Define Documentation

#define RCC_MCO1SOURCE_HSE LL_RCC_MCO1SOURCE_HSE

HSE after stabilization selection as MCO1 source

Definition at line 646 of file stm32wbxx_hal_rcc.h.

#define RCC_MCO1SOURCE_HSE_BEFORE_STAB LL_RCC_MCO1SOURCE_HSE_BEFORE_STAB

HSE before stabilization selection as MCO1 source

Definition at line 652 of file stm32wbxx_hal_rcc.h.

#define RCC_MCO1SOURCE_HSI LL_RCC_MCO1SOURCE_HSI

HSI selection as MCO1 source

Definition at line 645 of file stm32wbxx_hal_rcc.h.

#define RCC_MCO1SOURCE_HSI48 LL_RCC_MCO1SOURCE_HSI48

HSI48 selection as MCO1 source

Definition at line 651 of file stm32wbxx_hal_rcc.h.

#define RCC_MCO1SOURCE_LSE LL_RCC_MCO1SOURCE_LSE

LSE selection as MCO1 source

Definition at line 650 of file stm32wbxx_hal_rcc.h.

#define RCC_MCO1SOURCE_LSI1 LL_RCC_MCO1SOURCE_LSI1

LSI1 selection as MCO1 source

Definition at line 648 of file stm32wbxx_hal_rcc.h.

#define RCC_MCO1SOURCE_LSI2 LL_RCC_MCO1SOURCE_LSI2

LSI2 selection as MCO1 source

Definition at line 649 of file stm32wbxx_hal_rcc.h.

#define RCC_MCO1SOURCE_MSI LL_RCC_MCO1SOURCE_MSI

MSI selection as MCO1 source

Definition at line 644 of file stm32wbxx_hal_rcc.h.

#define RCC_MCO1SOURCE_NOCLOCK LL_RCC_MCO1SOURCE_NOCLOCK

MCO1 output disabled, no clock on MCO1

Definition at line 642 of file stm32wbxx_hal_rcc.h.

#define RCC_MCO1SOURCE_PLLCLK LL_RCC_MCO1SOURCE_PLLCLK

PLLCLK selection as MCO1 source

Definition at line 647 of file stm32wbxx_hal_rcc.h.

#define RCC_MCO1SOURCE_SYSCLK LL_RCC_MCO1SOURCE_SYSCLK

SYSCLK selection as MCO1 source

Definition at line 643 of file stm32wbxx_hal_rcc.h.

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STM32WB55xx HAL User Manual: MCO Clock Prescaler

Defines
MCO Clock Prescaler
RCC Exported Constants

Defines

#define | RCC_MCODIV_1 LL_RCC_MCO1_DIV_1
#define | RCC_MCODIV_2 LL_RCC_MCO1_DIV_2
#define | RCC_MCODIV_4 LL_RCC_MCO1_DIV_4
#define | RCC_MCODIV_8 LL_RCC_MCO1_DIV_8
#define | RCC_MCODIV_16 LL_RCC_MCO1_DIV_16

Define Documentation

#define RCC_MCODIV_1 LL_RCC_MCO1_DIV_1

MCO not divided

Definition at line 661 of file stm32wbxx_hal_rcc.h.

#define RCC_MCODIV_16 LL_RCC_MCO1_DIV_16

MCO divided by 16

Definition at line 665 of file stm32wbxx_hal_rcc.h.

#define RCC_MCODIV_2 LL_RCC_MCO1_DIV_2

MCO divided by 2

Definition at line 662 of file stm32wbxx_hal_rcc.h.

#define RCC_MCODIV_4 LL_RCC_MCO1_DIV_4

MCO divided by 4

Definition at line 663 of file stm32wbxx_hal_rcc.h.

#define RCC_MCODIV_8 LL_RCC_MCO1_DIV_8

MCO divided by 8

Definition at line 664 of file stm32wbxx_hal_rcc.h.

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STM32WB55xx HAL User Manual: HSE bias current factor

Defines
HSE bias current factor
RCC Exported Constants

Defines

#define | RCC_HSEAMPTHRESHOLD_1_2 LL_RCC_HSEAMPTHRESHOLD_1_2
#define | RCC_HSEAMPTHRESHOLD_3_4 LL_RCC_HSEAMPTHRESHOLD_3_4

Define Documentation

#define RCC_HSEAMPTHRESHOLD_1_2 LL_RCC_HSEAMPTHRESHOLD_1_2

HSE bias current factor 1/2

Definition at line 673 of file stm32wbxx_hal_rcc.h.

#define RCC_HSEAMPTHRESHOLD_3_4 LL_RCC_HSEAMPTHRESHOLD_3_4

HSE bias current factor 3/4

Definition at line 674 of file stm32wbxx_hal_rcc.h.

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STM32WB55xx HAL User Manual: HSE current max limit

Defines
HSE current max limit
RCC Exported Constants

Defines

#define | RCC_HSE_CURRENTMAX_0 LL_RCC_HSE_CURRENTMAX_0
#define | RCC_HSE_CURRENTMAX_1 LL_RCC_HSE_CURRENTMAX_1
#define | RCC_HSE_CURRENTMAX_2 LL_RCC_HSE_CURRENTMAX_2
#define | RCC_HSE_CURRENTMAX_3 LL_RCC_HSE_CURRENTMAX_3
#define | RCC_HSE_CURRENTMAX_4 LL_RCC_HSE_CURRENTMAX_4
#define | RCC_HSE_CURRENTMAX_5 LL_RCC_HSE_CURRENTMAX_5
#define | RCC_HSE_CURRENTMAX_6 LL_RCC_HSE_CURRENTMAX_6
#define | RCC_HSE_CURRENTMAX_7 LL_RCC_HSE_CURRENTMAX_7

Define Documentation

#define RCC_HSE_CURRENTMAX_0 LL_RCC_HSE_CURRENTMAX_0

HSE current max limit 0.18 mA/V

Definition at line 683 of file stm32wbxx_hal_rcc.h.

#define RCC_HSE_CURRENTMAX_1 LL_RCC_HSE_CURRENTMAX_1

HSE current max limit 0.57 mA/V

Definition at line 684 of file stm32wbxx_hal_rcc.h.

#define RCC_HSE_CURRENTMAX_2 LL_RCC_HSE_CURRENTMAX_2

HSE current max limit 0.78 mA/V

Definition at line 685 of file stm32wbxx_hal_rcc.h.

#define RCC_HSE_CURRENTMAX_3 LL_RCC_HSE_CURRENTMAX_3

HSE current max limit 1.13 mA/V

Definition at line 686 of file stm32wbxx_hal_rcc.h.

#define RCC_HSE_CURRENTMAX_4 LL_RCC_HSE_CURRENTMAX_4

HSE current max limit 0.61 mA/V

Definition at line 687 of file stm32wbxx_hal_rcc.h.

#define RCC_HSE_CURRENTMAX_5 LL_RCC_HSE_CURRENTMAX_5

HSE current max limit 1.65 mA/V

Definition at line 688 of file stm32wbxx_hal_rcc.h.

#define RCC_HSE_CURRENTMAX_6 LL_RCC_HSE_CURRENTMAX_6

HSE current max limit 2.12 mA/V

Definition at line 689 of file stm32wbxx_hal_rcc.h.

#define RCC_HSE_CURRENTMAX_7 LL_RCC_HSE_CURRENTMAX_7

HSE current max limit 2.84 mA/V

Definition at line 690 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Interrupts

Defines
Interrupts
RCC Exported Constants

Defines

#define | RCC_IT_LSI1RDY LL_RCC_CIFR_LSI1RDYF
#define | RCC_IT_LSI2RDY LL_RCC_CIFR_LSI2RDYF
#define | RCC_IT_LSERDY LL_RCC_CIFR_LSERDYF
#define | RCC_IT_MSIRDY LL_RCC_CIFR_MSIRDYF
#define | RCC_IT_HSIRDY LL_RCC_CIFR_HSIRDYF
#define | RCC_IT_HSERDY LL_RCC_CIFR_HSERDYF
#define | RCC_IT_PLLRDY LL_RCC_CIFR_PLLRDYF
#define | RCC_IT_PLLSAI1RDY LL_RCC_CIFR_PLLSAI1RDYF
#define | RCC_IT_HSECSS LL_RCC_CIFR_CSSF
#define | RCC_IT_LSECSS LL_RCC_CIFR_LSECSSF
#define | RCC_IT_HSI48RDY LL_RCC_CIFR_HSI48RDYF

Define Documentation

#define RCC_IT_HSECSS LL_RCC_CIFR_CSSF

HSE Clock Security System Interrupt flag

Definition at line 709 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_NMI_IRQHandler().

#define RCC_IT_HSERDY LL_RCC_CIFR_HSERDYF

HSE Ready Interrupt flag

Definition at line 704 of file stm32wbxx_hal_rcc.h.

#define RCC_IT_HSI48RDY LL_RCC_CIFR_HSI48RDYF

HSI48 Ready Interrupt flag

Definition at line 711 of file stm32wbxx_hal_rcc.h.

#define RCC_IT_HSIRDY LL_RCC_CIFR_HSIRDYF

HSI Ready Interrupt flag

Definition at line 703 of file stm32wbxx_hal_rcc.h.

#define RCC_IT_LSECSS LL_RCC_CIFR_LSECSSF

LSE Clock Security System Interrupt flag

Definition at line 710 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCCEx_DisableLSECSS(), HAL_RCCEx_EnableLSECSS_IT(), and HAL_RCCEx_LSECSS_IRQHandler().

#define RCC_IT_LSERDY LL_RCC_CIFR_LSERDYF

LSE Ready Interrupt flag

Definition at line 701 of file stm32wbxx_hal_rcc.h.

#define RCC_IT_LSI1RDY LL_RCC_CIFR_LSI1RDYF

LSI1 Ready Interrupt flag

Definition at line 699 of file stm32wbxx_hal_rcc.h.

#define RCC_IT_LSI2RDY LL_RCC_CIFR_LSI2RDYF

LSI2 Ready Interrupt flag

Definition at line 700 of file stm32wbxx_hal_rcc.h.

#define RCC_IT_MSIRDY LL_RCC_CIFR_MSIRDYF

MSI Ready Interrupt flag

Definition at line 702 of file stm32wbxx_hal_rcc.h.

#define RCC_IT_PLLRDY LL_RCC_CIFR_PLLRDYF

PLL Ready Interrupt flag

Definition at line 705 of file stm32wbxx_hal_rcc.h.

#define RCC_IT_PLLSAI1RDY LL_RCC_CIFR_PLLSAI1RDYF

PLLSAI1 Ready Interrupt flag

Definition at line 707 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Flags

Defines
Flags
RCC Exported Constants

Elements values convention: XXXYYYYYb. More...

Defines

#define | RCC_FLAG_MSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos)
#define | RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)
#define | RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)
#define | RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)
#define | RCC_FLAG_PLLSAI1RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI1RDY_Pos)
#define | RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)
#define | RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos)
#define | RCC_FLAG_LSI1RDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSI1RDY_Pos)
#define | RCC_FLAG_LSI2RDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSI2RDY_Pos)
#define | RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos)
#define | RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)
#define | RCC_FLAG_BORRST ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos)
#define | RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)
#define | RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)
#define | RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)
#define | RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)
#define | RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos)

Detailed Description

Elements values convention: XXXYYYYYb.

  • YYYYY : Flag position in the register
  • XXX : Register index
    • 001: CR register
    • 010: BDCR register
    • 011: CSR register
    • 100: CRRCR register

Define Documentation

#define RCC_FLAG_BORRST ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos)

BOR reset flag

Definition at line 743 of file stm32wbxx_hal_rcc.h.

#define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)

HSE Ready flag

Definition at line 730 of file stm32wbxx_hal_rcc.h.

#define RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos)

HSI48 Ready flag

Definition at line 750 of file stm32wbxx_hal_rcc.h.

#define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)

HSI Ready flag

Definition at line 729 of file stm32wbxx_hal_rcc.h.

#define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)

Watchdog reset flag

Definition at line 745 of file stm32wbxx_hal_rcc.h.

#define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)

Low-Power reset flag

Definition at line 747 of file stm32wbxx_hal_rcc.h.

#define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos)

LSE Clock Security System failure detection flag

Definition at line 736 of file stm32wbxx_hal_rcc.h.

#define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)

LSE Ready flag

Definition at line 735 of file stm32wbxx_hal_rcc.h.

#define RCC_FLAG_LSI1RDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSI1RDY_Pos)

LSI1 Ready flag

Definition at line 739 of file stm32wbxx_hal_rcc.h.

#define RCC_FLAG_LSI2RDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSI2RDY_Pos)

LSI2 Ready flag

Definition at line 740 of file stm32wbxx_hal_rcc.h.

#define RCC_FLAG_MSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos)

MSI Ready flag

Definition at line 728 of file stm32wbxx_hal_rcc.h.

#define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos)

Option Byte Loader reset flag

Definition at line 741 of file stm32wbxx_hal_rcc.h.

#define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)

Pin reset flag (NRST pin)

Definition at line 742 of file stm32wbxx_hal_rcc.h.

#define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)

PLL Ready flag

Definition at line 731 of file stm32wbxx_hal_rcc.h.

#define RCC_FLAG_PLLSAI1RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI1RDY_Pos)

PLLSAI1 Ready flag

Definition at line 732 of file stm32wbxx_hal_rcc.h.

#define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)

Software Reset flag

Definition at line 744 of file stm32wbxx_hal_rcc.h.

#define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)

Window watchdog reset flag

Definition at line 746 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LSE Drive Configuration

Defines
LSE Drive Configuration
RCC Exported Constants

Defines

#define | RCC_LSEDRIVE_LOW LL_RCC_LSEDRIVE_LOW
#define | RCC_LSEDRIVE_MEDIUMLOW LL_RCC_LSEDRIVE_MEDIUMLOW
#define | RCC_LSEDRIVE_MEDIUMHIGH LL_RCC_LSEDRIVE_MEDIUMHIGH
#define | RCC_LSEDRIVE_HIGH LL_RCC_LSEDRIVE_HIGH

Define Documentation

#define RCC_LSEDRIVE_HIGH LL_RCC_LSEDRIVE_HIGH

LSE high drive capability

Definition at line 762 of file stm32wbxx_hal_rcc.h.

#define RCC_LSEDRIVE_LOW LL_RCC_LSEDRIVE_LOW

LSE low drive capability

Definition at line 759 of file stm32wbxx_hal_rcc.h.

#define RCC_LSEDRIVE_MEDIUMHIGH LL_RCC_LSEDRIVE_MEDIUMHIGH

LSE medium high drive capability

Definition at line 761 of file stm32wbxx_hal_rcc.h.

#define RCC_LSEDRIVE_MEDIUMLOW LL_RCC_LSEDRIVE_MEDIUMLOW

LSE medium low drive capability

Definition at line 760 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Wake-Up from STOP Clock

Defines
Wake-Up from STOP Clock
RCC Exported Constants

Defines

#define | RCC_STOP_WAKEUPCLOCK_MSI LL_RCC_STOP_WAKEUPCLOCK_MSI
#define | RCC_STOP_WAKEUPCLOCK_HSI LL_RCC_STOP_WAKEUPCLOCK_HSI

Define Documentation

#define RCC_STOP_WAKEUPCLOCK_HSI LL_RCC_STOP_WAKEUPCLOCK_HSI

HSI selection after wake-up from STOP

Definition at line 771 of file stm32wbxx_hal_rcc.h.

#define RCC_STOP_WAKEUPCLOCK_MSI LL_RCC_STOP_WAKEUPCLOCK_MSI

MSI selection after wake-up from STOP

Definition at line 770 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: AHB1 Peripheral Clock Enable Disable

Defines
AHB1 Peripheral Clock Enable Disable
RCC Exported Macros

Enable or disable the AHB1 peripheral clock. More...

Defines

#define | __HAL_RCC_DMA1_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1)
#define | __HAL_RCC_DMA2_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA2)
#define | __HAL_RCC_DMAMUX1_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMAMUX1)
#define | __HAL_RCC_CRC_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_CRC)
#define | __HAL_RCC_TSC_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_TSC)
#define | __HAL_RCC_DMA1_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_DMA1)
#define | __HAL_RCC_DMA2_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_DMA2)
#define | __HAL_RCC_DMAMUX1_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_DMAMUX1)
#define | __HAL_RCC_CRC_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_CRC)
#define | __HAL_RCC_TSC_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_TSC)
#define | __HAL_RCC_C2DMA1_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMA1)
#define | __HAL_RCC_C2DMA2_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMA2)
#define | __HAL_RCC_C2DMAMUX1_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1)
#define | __HAL_RCC_C2SRAM1_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_SRAM1)
#define | __HAL_RCC_C2CRC_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_CRC)
#define | __HAL_RCC_C2TSC_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_TSC)
#define | __HAL_RCC_C2DMA1_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_DMA1)
#define | __HAL_RCC_C2DMA2_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_DMA2)
#define | __HAL_RCC_C2DMAMUX1_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1)
#define | __HAL_RCC_C2SRAM1_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_SRAM1)
#define | __HAL_RCC_C2CRC_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_CRC)
#define | __HAL_RCC_C2TSC_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_TSC)

Detailed Description

Enable or disable the AHB1 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_C2CRC_CLK_DISABLE ( ) LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_CRC)

Definition at line 1195 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2CRC_CLK_ENABLE ( ) LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_CRC)

Definition at line 1186 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2DMA1_CLK_DISABLE ( ) LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_DMA1)

Definition at line 1189 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2DMA1_CLK_ENABLE ( ) LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMA1)

Definition at line 1180 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2DMA2_CLK_DISABLE ( ) LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_DMA2)

Definition at line 1191 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2DMA2_CLK_ENABLE ( ) LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMA2)

Definition at line 1182 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2DMAMUX1_CLK_DISABLE ( ) LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1)

Definition at line 1193 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2DMAMUX1_CLK_ENABLE ( ) LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1)

Definition at line 1184 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2SRAM1_CLK_DISABLE ( ) LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_SRAM1)

Definition at line 1194 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2SRAM1_CLK_ENABLE ( ) LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_SRAM1)

Definition at line 1185 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TSC_CLK_DISABLE ( ) LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_TSC)

Definition at line 1196 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TSC_CLK_ENABLE ( ) LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_TSC)

Definition at line 1187 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_CRC_CLK_DISABLE ( ) LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_CRC)

Definition at line 807 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_CRC_CLK_ENABLE ( ) LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_CRC)

Definition at line 799 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_DMA1_CLK_DISABLE ( ) LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_DMA1)

Definition at line 802 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_DMA1_CLK_ENABLE ( ) LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1)

Definition at line 794 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_DMA2_CLK_DISABLE ( ) LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_DMA2)

Definition at line 804 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_DMA2_CLK_ENABLE ( ) LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA2)

Definition at line 796 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_DMAMUX1_CLK_DISABLE ( ) LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_DMAMUX1)

Definition at line 806 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_DMAMUX1_CLK_ENABLE ( ) LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMAMUX1)

Definition at line 798 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TSC_CLK_DISABLE ( ) LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_TSC)

Definition at line 808 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TSC_CLK_ENABLE ( ) LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_TSC)

Definition at line 800 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: AHB2 Peripheral Clock Enable Disable

Defines
AHB2 Peripheral Clock Enable Disable
RCC Exported Macros

Enable or disable the AHB2 peripheral clock. More...

Defines

#define | __HAL_RCC_GPIOA_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA)
#define | __HAL_RCC_GPIOB_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB)
#define | __HAL_RCC_GPIOC_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOC)
#define | __HAL_RCC_GPIOD_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOD)
#define | __HAL_RCC_GPIOE_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOE)
#define | __HAL_RCC_GPIOH_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOH)
#define | __HAL_RCC_ADC_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_ADC)
#define | __HAL_RCC_AES1_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_AES1)
#define | __HAL_RCC_GPIOA_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOA)
#define | __HAL_RCC_GPIOB_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOB)
#define | __HAL_RCC_GPIOC_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOC)
#define | __HAL_RCC_GPIOD_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOD)
#define | __HAL_RCC_GPIOE_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOE)
#define | __HAL_RCC_GPIOH_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOH)
#define | __HAL_RCC_ADC_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_ADC)
#define | __HAL_RCC_AES1_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_AES1)
#define | __HAL_RCC_C2GPIOA_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA)
#define | __HAL_RCC_C2GPIOB_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB)
#define | __HAL_RCC_C2GPIOC_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC)
#define | __HAL_RCC_C2GPIOD_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOD)
#define | __HAL_RCC_C2GPIOE_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE)
#define | __HAL_RCC_C2GPIOH_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH)
#define | __HAL_RCC_C2ADC_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_ADC)
#define | __HAL_RCC_C2AES1_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_AES1)
#define | __HAL_RCC_C2GPIOA_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA)
#define | __HAL_RCC_C2GPIOB_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB)
#define | __HAL_RCC_C2GPIOC_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC)
#define | __HAL_RCC_C2GPIOD_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOD)
#define | __HAL_RCC_C2GPIOE_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE)
#define | __HAL_RCC_C2GPIOH_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH)
#define | __HAL_RCC_C2ADC_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_ADC)
#define | __HAL_RCC_C2AES1_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_AES1)

Detailed Description

Enable or disable the AHB2 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_ADC_CLK_DISABLE ( ) LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_ADC)

Definition at line 845 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_ADC_CLK_ENABLE ( ) LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_ADC)

Definition at line 832 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_AES1_CLK_DISABLE ( ) LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_AES1)

Definition at line 848 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_AES1_CLK_ENABLE ( ) LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_AES1)

Definition at line 834 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2ADC_CLK_DISABLE ( ) LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_ADC)

Definition at line 1231 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2ADC_CLK_ENABLE ( ) LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_ADC)

Definition at line 1218 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2AES1_CLK_DISABLE ( ) LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_AES1)

Definition at line 1233 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2AES1_CLK_ENABLE ( ) LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_AES1)

Definition at line 1220 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOA_CLK_DISABLE ( ) LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA)

Definition at line 1223 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOA_CLK_ENABLE ( ) LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA)

Definition at line 1210 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOB_CLK_DISABLE ( ) LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB)

Definition at line 1224 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOB_CLK_ENABLE ( ) LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB)

Definition at line 1211 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOC_CLK_DISABLE ( ) LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC)

Definition at line 1225 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOC_CLK_ENABLE ( ) LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC)

Definition at line 1212 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOD_CLK_DISABLE ( ) LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOD)

Definition at line 1227 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOD_CLK_ENABLE ( ) LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOD)

Definition at line 1214 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOE_CLK_DISABLE ( ) LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE)

Definition at line 1229 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOE_CLK_ENABLE ( ) LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE)

Definition at line 1216 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOH_CLK_DISABLE ( ) LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH)

Definition at line 1230 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOH_CLK_ENABLE ( ) LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH)

Definition at line 1217 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOA_CLK_DISABLE ( ) LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOA)

Definition at line 836 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOA_CLK_ENABLE ( ) LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA)

Definition at line 822 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOB_CLK_DISABLE ( ) LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOB)

Definition at line 837 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOB_CLK_ENABLE ( ) LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB)

Definition at line 823 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOC_CLK_DISABLE ( ) LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOC)

Definition at line 838 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOC_CLK_ENABLE ( ) LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOC)

Definition at line 824 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOD_CLK_DISABLE ( ) LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOD)

Definition at line 840 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOD_CLK_ENABLE ( ) LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOD)

Definition at line 827 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOE_CLK_DISABLE ( ) LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOE)

Definition at line 842 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOE_CLK_ENABLE ( ) LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOE)

Definition at line 829 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOH_CLK_DISABLE ( ) LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOH)

Definition at line 843 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOH_CLK_ENABLE ( ) LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOH)

Definition at line 830 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: AHB3 Peripheral Clock Enable Disable

Defines
AHB3 Peripheral Clock Enable Disable
RCC Exported Macros

Enable or disable the AHB3 peripheral clock. More...

Defines

#define | __HAL_RCC_QUADSPI_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_QUADSPI)
#define | __HAL_RCC_PKA_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PKA)
#define | __HAL_RCC_AES2_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_AES2)
#define | __HAL_RCC_RNG_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_RNG)
#define | __HAL_RCC_HSEM_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_HSEM)
#define | __HAL_RCC_IPCC_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_IPCC)
#define | __HAL_RCC_FLASH_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_FLASH)
#define | __HAL_RCC_QUADSPI_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_QUADSPI)
#define | __HAL_RCC_PKA_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_PKA)
#define | __HAL_RCC_AES2_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_AES2)
#define | __HAL_RCC_RNG_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_RNG)
#define | __HAL_RCC_HSEM_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_HSEM)
#define | __HAL_RCC_IPCC_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_IPCC)
#define | __HAL_RCC_FLASH_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_FLASH)
#define | __HAL_RCC_C2PKA_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_PKA)
#define | __HAL_RCC_C2AES2_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_AES2)
#define | __HAL_RCC_C2RNG_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_RNG)
#define | __HAL_RCC_C2HSEM_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_HSEM)
#define | __HAL_RCC_C2IPCC_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_IPCC)
#define | __HAL_RCC_C2FLASH_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_FLASH)
#define | __HAL_RCC_C2PKA_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_PKA)
#define | __HAL_RCC_C2AES2_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_AES2)
#define | __HAL_RCC_C2RNG_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_RNG)
#define | __HAL_RCC_C2HSEM_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_HSEM)
#define | __HAL_RCC_C2IPCC_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_IPCC)
#define | __HAL_RCC_C2FLASH_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_FLASH)

Detailed Description

Enable or disable the AHB3 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_AES2_CLK_DISABLE ( ) LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_AES2)

Definition at line 877 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_AES2_CLK_ENABLE ( ) LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_AES2)

Definition at line 867 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2AES2_CLK_DISABLE ( ) LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_AES2)

Definition at line 1256 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2AES2_CLK_ENABLE ( ) LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_AES2)

Definition at line 1249 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2FLASH_CLK_DISABLE ( ) LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_FLASH)

Definition at line 1260 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2FLASH_CLK_ENABLE ( ) LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_FLASH)

Definition at line 1253 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2HSEM_CLK_DISABLE ( ) LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_HSEM)

Definition at line 1258 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2HSEM_CLK_ENABLE ( ) LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_HSEM)

Definition at line 1251 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2IPCC_CLK_DISABLE ( ) LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_IPCC)

Definition at line 1259 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2IPCC_CLK_ENABLE ( ) LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_IPCC)

Definition at line 1252 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2PKA_CLK_DISABLE ( ) LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_PKA)

Definition at line 1255 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2PKA_CLK_ENABLE ( ) LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_PKA)

Definition at line 1248 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2RNG_CLK_DISABLE ( ) LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_RNG)

Definition at line 1257 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2RNG_CLK_ENABLE ( ) LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_RNG)

Definition at line 1250 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_FLASH_CLK_DISABLE ( ) LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_FLASH)

Definition at line 881 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_FLASH_CLK_ENABLE ( ) LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_FLASH)

Definition at line 871 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_HSEM_CLK_DISABLE ( ) LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_HSEM)

Definition at line 879 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_HSEM_CLK_ENABLE ( ) LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_HSEM)

Definition at line 869 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_IPCC_CLK_DISABLE ( ) LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_IPCC)

Definition at line 880 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_IPCC_CLK_ENABLE ( ) LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_IPCC)

Definition at line 870 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_PKA_CLK_DISABLE ( ) LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_PKA)

Definition at line 876 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_PKA_CLK_ENABLE ( ) LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PKA)

Definition at line 866 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_QUADSPI_CLK_DISABLE ( ) LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_QUADSPI)

Definition at line 874 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_QUADSPI_CLK_ENABLE ( ) LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_QUADSPI)

Definition at line 864 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_RNG_CLK_DISABLE ( ) LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_RNG)

Definition at line 878 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_RNG_CLK_ENABLE ( ) LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_RNG)

Definition at line 868 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: APB1 Peripheral Clock Enable Disable

Defines
APB1 Peripheral Clock Enable Disable
RCC Exported Macros

Enable or disable the APB1 peripheral clock. More...

Defines

#define | __HAL_RCC_RTCAPB_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_RTCAPB)
#define | __HAL_RCC_WWDG_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_WWDG)
#define | __HAL_RCC_TIM2_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2)
#define | __HAL_RCC_LCD_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LCD)
#define | __HAL_RCC_SPI2_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI2)
#define | __HAL_RCC_I2C1_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C1)
#define | __HAL_RCC_I2C3_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C3)
#define | __HAL_RCC_CRS_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_CRS)
#define | __HAL_RCC_USB_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USB)
#define | __HAL_RCC_LPTIM1_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LPTIM1)
#define | __HAL_RCC_LPTIM2_CLK_ENABLE() LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_LPTIM2)
#define | __HAL_RCC_LPUART1_CLK_ENABLE() LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_LPUART1)
#define | __HAL_RCC_RTCAPB_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_RTCAPB)
#define | __HAL_RCC_TIM2_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM2)
#define | __HAL_RCC_LCD_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_LCD)
#define | __HAL_RCC_SPI2_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_SPI2)
#define | __HAL_RCC_I2C1_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C1)
#define | __HAL_RCC_I2C3_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C3)
#define | __HAL_RCC_CRS_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_CRS)
#define | __HAL_RCC_USB_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_USB)
#define | __HAL_RCC_LPTIM1_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_LPTIM1)
#define | __HAL_RCC_LPTIM2_CLK_DISABLE() LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_LPTIM2)
#define | __HAL_RCC_LPUART1_CLK_DISABLE() LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_LPUART1)
#define | __HAL_RCC_C2RTCAPB_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB)
#define | __HAL_RCC_C2TIM2_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_TIM2)
#define | __HAL_RCC_C2LCD_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_LCD)
#define | __HAL_RCC_C2SPI2_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_SPI2)
#define | __HAL_RCC_C2I2C1_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_I2C1)
#define | __HAL_RCC_C2I2C3_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_I2C3)
#define | __HAL_RCC_C2CRS_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_CRS)
#define | __HAL_RCC_C2USB_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_USB)
#define | __HAL_RCC_C2LPTIM1_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1)
#define | __HAL_RCC_C2LPTIM2_CLK_ENABLE() LL_C2_APB1_GRP2_EnableClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2)
#define | __HAL_RCC_C2LPUART1_CLK_ENABLE() LL_C2_APB1_GRP2_EnableClock(LL_C2_APB1_GRP2_PERIPH_LPUART1)
#define | __HAL_RCC_C2RTCAPB_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB)
#define | __HAL_RCC_C2TIM2_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_TIM2)
#define | __HAL_RCC_C2LCD_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_LCD)
#define | __HAL_RCC_C2SPI2_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_SPI2)
#define | __HAL_RCC_C2I2C1_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_I2C1)
#define | __HAL_RCC_C2I2C3_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_I2C3)
#define | __HAL_RCC_C2CRS_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_CRS)
#define | __HAL_RCC_C2USB_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_USB)
#define | __HAL_RCC_C2LPTIM1_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1)
#define | __HAL_RCC_C2LPTIM2_CLK_DISABLE() LL_C2_APB1_GRP2_DisableClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2)
#define | __HAL_RCC_C2LPUART1_CLK_DISABLE() LL_C2_APB1_GRP2_DisableClock(LL_C2_APB1_GRP2_PERIPH_LPUART1)

Detailed Description

Enable or disable the APB1 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_C2CRS_CLK_DISABLE ( ) LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_CRS)

Definition at line 1312 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2CRS_CLK_ENABLE ( ) LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_CRS)

Definition at line 1287 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2I2C1_CLK_DISABLE ( ) LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_I2C1)

Definition at line 1307 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2I2C1_CLK_ENABLE ( ) LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_I2C1)

Definition at line 1282 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2I2C3_CLK_DISABLE ( ) LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_I2C3)

Definition at line 1309 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2I2C3_CLK_ENABLE ( ) LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_I2C3)

Definition at line 1284 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2LCD_CLK_DISABLE ( ) LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_LCD)

Definition at line 1302 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2LCD_CLK_ENABLE ( ) LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_LCD)

Definition at line 1277 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2LPTIM1_CLK_DISABLE ( ) LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1)

Definition at line 1317 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2LPTIM1_CLK_ENABLE ( ) LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1)

Definition at line 1292 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2LPTIM2_CLK_DISABLE ( ) LL_C2_APB1_GRP2_DisableClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2)

Definition at line 1319 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2LPTIM2_CLK_ENABLE ( ) LL_C2_APB1_GRP2_EnableClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2)

Definition at line 1294 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2LPUART1_CLK_DISABLE ( ) LL_C2_APB1_GRP2_DisableClock(LL_C2_APB1_GRP2_PERIPH_LPUART1)

Definition at line 1321 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2LPUART1_CLK_ENABLE ( ) LL_C2_APB1_GRP2_EnableClock(LL_C2_APB1_GRP2_PERIPH_LPUART1)

Definition at line 1296 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2RTCAPB_CLK_DISABLE ( ) LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB)

Definition at line 1299 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2RTCAPB_CLK_ENABLE ( ) LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB)

Definition at line 1274 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2SPI2_CLK_DISABLE ( ) LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_SPI2)

Definition at line 1305 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2SPI2_CLK_ENABLE ( ) LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_SPI2)

Definition at line 1280 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TIM2_CLK_DISABLE ( ) LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_TIM2)

Definition at line 1300 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TIM2_CLK_ENABLE ( ) LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_TIM2)

Definition at line 1275 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2USB_CLK_DISABLE ( ) LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_USB)

Definition at line 1315 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2USB_CLK_ENABLE ( ) LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_USB)

Definition at line 1290 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_CRS_CLK_DISABLE ( ) LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_CRS)

Definition at line 933 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_CRS_CLK_ENABLE ( ) LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_CRS)

Definition at line 909 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_I2C1_CLK_DISABLE ( ) LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C1)

Definition at line 928 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_I2C1_CLK_ENABLE ( ) LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C1)

Definition at line 904 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_I2C3_CLK_DISABLE ( ) LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C3)

Definition at line 930 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_I2C3_CLK_ENABLE ( ) LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C3)

Definition at line 906 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_LCD_CLK_DISABLE ( ) LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_LCD)

Definition at line 923 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_LCD_CLK_ENABLE ( ) LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LCD)

Definition at line 899 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_CLK_DISABLE ( ) LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_LPTIM1)

Definition at line 938 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_CLK_ENABLE ( ) LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LPTIM1)

Definition at line 914 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_CLK_DISABLE ( ) LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_LPTIM2)

Definition at line 940 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_CLK_ENABLE ( ) LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_LPTIM2)

Definition at line 915 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_LPUART1_CLK_DISABLE ( ) LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_LPUART1)

Definition at line 942 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_LPUART1_CLK_ENABLE ( ) LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_LPUART1)

Definition at line 917 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_RTCAPB_CLK_DISABLE ( ) LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_RTCAPB)

Definition at line 920 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_RTCAPB_CLK_ENABLE ( ) LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_RTCAPB)

Definition at line 895 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_SPI2_CLK_DISABLE ( ) LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_SPI2)

Definition at line 926 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_SPI2_CLK_ENABLE ( ) LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI2)

Definition at line 902 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM2_CLK_DISABLE ( ) LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM2)

Definition at line 921 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM2_CLK_ENABLE ( ) LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2)

Definition at line 897 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_USB_CLK_DISABLE ( ) LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_USB)

Definition at line 936 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_USB_CLK_ENABLE ( ) LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USB)

Definition at line 912 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_WWDG_CLK_ENABLE ( ) LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_WWDG)

Definition at line 896 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: APB2 Peripheral Clock Enable Disable

Defines
APB2 Peripheral Clock Enable Disable
RCC Exported Macros

Enable or disable the APB2 peripheral clock. More...

Defines

#define | __HAL_RCC_TIM1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM1)
#define | __HAL_RCC_SPI1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI1)
#define | __HAL_RCC_USART1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1)
#define | __HAL_RCC_TIM16_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM16)
#define | __HAL_RCC_TIM17_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM17)
#define | __HAL_RCC_SAI1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SAI1)
#define | __HAL_RCC_TIM1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM1)
#define | __HAL_RCC_SPI1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SPI1)
#define | __HAL_RCC_USART1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_USART1)
#define | __HAL_RCC_TIM16_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM16)
#define | __HAL_RCC_TIM17_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM17)
#define | __HAL_RCC_SAI1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SAI1)
#define | __HAL_RCC_C2TIM1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_TIM1)
#define | __HAL_RCC_C2SPI1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_SPI1)
#define | __HAL_RCC_C2USART1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_USART1)
#define | __HAL_RCC_C2TIM16_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_TIM16)
#define | __HAL_RCC_C2TIM17_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_TIM17)
#define | __HAL_RCC_C2SAI1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_SAI1)
#define | __HAL_RCC_C2TIM1_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_TIM1)
#define | __HAL_RCC_C2SPI1_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_SPI1)
#define | __HAL_RCC_C2USART1_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_USART1)
#define | __HAL_RCC_C2TIM16_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_TIM16)
#define | __HAL_RCC_C2TIM17_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_TIM17)
#define | __HAL_RCC_C2SAI1_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_SAI1)

Detailed Description

Enable or disable the APB2 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_C2SAI1_CLK_DISABLE ( ) LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_SAI1)

Definition at line 1351 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2SAI1_CLK_ENABLE ( ) LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_SAI1)

Definition at line 1342 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2SPI1_CLK_DISABLE ( ) LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_SPI1)

Definition at line 1346 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2SPI1_CLK_ENABLE ( ) LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_SPI1)

Definition at line 1337 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TIM16_CLK_DISABLE ( ) LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_TIM16)

Definition at line 1348 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TIM16_CLK_ENABLE ( ) LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_TIM16)

Definition at line 1339 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TIM17_CLK_DISABLE ( ) LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_TIM17)

Definition at line 1349 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TIM17_CLK_ENABLE ( ) LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_TIM17)

Definition at line 1340 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TIM1_CLK_DISABLE ( ) LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_TIM1)

Definition at line 1345 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TIM1_CLK_ENABLE ( ) LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_TIM1)

Definition at line 1336 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2USART1_CLK_DISABLE ( ) LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_USART1)

Definition at line 1347 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2USART1_CLK_ENABLE ( ) LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_USART1)

Definition at line 1338 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_SAI1_CLK_DISABLE ( ) LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SAI1)

Definition at line 972 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_SAI1_CLK_ENABLE ( ) LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SAI1)

Definition at line 963 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_SPI1_CLK_DISABLE ( ) LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SPI1)

Definition at line 967 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_SPI1_CLK_ENABLE ( ) LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI1)

Definition at line 958 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM16_CLK_DISABLE ( ) LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM16)

Definition at line 969 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM16_CLK_ENABLE ( ) LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM16)

Definition at line 960 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM17_CLK_DISABLE ( ) LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM17)

Definition at line 970 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM17_CLK_ENABLE ( ) LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM17)

Definition at line 961 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM1_CLK_DISABLE ( ) LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM1)

Definition at line 966 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM1_CLK_ENABLE ( ) LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM1)

Definition at line 957 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_USART1_CLK_DISABLE ( ) LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_USART1)

Definition at line 968 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_USART1_CLK_ENABLE ( ) LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1)

Definition at line 959 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: AHB1 Peripheral Clock Enabled or Disabled Status

Defines
AHB1 Peripheral Clock Enabled or Disabled Status
RCC Exported Macros

Check whether the AHB1 peripheral clock is enabled or not. More...

Defines

#define | __HAL_RCC_DMA1_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA1)
#define | __HAL_RCC_DMA2_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA2)
#define | __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMAMUX1)
#define | __HAL_RCC_CRC_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_CRC)
#define | __HAL_RCC_TSC_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_TSC)
#define | __HAL_RCC_DMA1_IS_CLK_DISABLED() !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA1))
#define | __HAL_RCC_DMA2_IS_CLK_DISABLED() !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA2))
#define | __HAL_RCC_DMAMUX1_IS_CLK_DISABLED() !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMAMUX1))
#define | __HAL_RCC_CRC_IS_CLK_DISABLED() !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_CRC))
#define | __HAL_RCC_TSC_IS_CLK_DISABLED() !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_TSC))
#define | __HAL_RCC_C2DMA1_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMA1)
#define | __HAL_RCC_C2DMA2_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMA2)
#define | __HAL_RCC_C2DMAMUX1_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1)
#define | __HAL_RCC_C2SRAM1_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_SRAM1)
#define | __HAL_RCC_C2CRC_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_CRC)
#define | __HAL_RCC_C2TSC_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_TSC)
#define | __HAL_RCC_C2DMA1_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMA1))
#define | __HAL_RCC_C2DMA2_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMA2))
#define | __HAL_RCC_C2DMAMUX1_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1))
#define | __HAL_RCC_C2SRAM1_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_SRAM1))
#define | __HAL_RCC_C2CRC_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_CRC))
#define | __HAL_RCC_C2TSC_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_TSC))

Detailed Description

Check whether the AHB1 peripheral clock is enabled or not.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_C2CRC_IS_CLK_DISABLED ( ) !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_CRC))

Definition at line 1400 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2CRC_IS_CLK_ENABLED ( ) LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_CRC)

Definition at line 1391 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2DMA1_IS_CLK_DISABLED ( ) !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMA1))

Definition at line 1394 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2DMA1_IS_CLK_ENABLED ( ) LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMA1)

Definition at line 1385 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2DMA2_IS_CLK_DISABLED ( ) !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMA2))

Definition at line 1396 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2DMA2_IS_CLK_ENABLED ( ) LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMA2)

Definition at line 1387 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2DMAMUX1_IS_CLK_DISABLED ( ) !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1))

Definition at line 1398 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2DMAMUX1_IS_CLK_ENABLED ( ) LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1)

Definition at line 1389 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2SRAM1_IS_CLK_DISABLED ( ) !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_SRAM1))

Definition at line 1399 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2SRAM1_IS_CLK_ENABLED ( ) LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_SRAM1)

Definition at line 1390 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TSC_IS_CLK_DISABLED ( ) !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_TSC))

Definition at line 1401 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TSC_IS_CLK_ENABLED ( ) LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_TSC)

Definition at line 1392 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_CRC_IS_CLK_DISABLED ( ) !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_CRC))

Definition at line 1000 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_CRC_IS_CLK_ENABLED ( ) LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_CRC)

Definition at line 992 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_DMA1_IS_CLK_DISABLED ( ) !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA1))

Definition at line 995 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_DMA1_IS_CLK_ENABLED ( ) LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA1)

Definition at line 987 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_DMA2_IS_CLK_DISABLED ( ) !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA2))

Definition at line 997 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_DMA2_IS_CLK_ENABLED ( ) LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA2)

Definition at line 989 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED ( ) !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMAMUX1))

Definition at line 999 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED ( ) LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMAMUX1)

Definition at line 991 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TSC_IS_CLK_DISABLED ( ) !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_TSC))

Definition at line 1001 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TSC_IS_CLK_ENABLED ( ) LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_TSC)

Definition at line 993 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: AHB2 Peripheral Clock Enabled or Disabled Status

Defines
AHB2 Peripheral Clock Enabled or Disabled Status
RCC Exported Macros

Check whether the AHB2 peripheral clock is enabled or not. More...

Defines

#define | __HAL_RCC_GPIOA_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOA)
#define | __HAL_RCC_GPIOB_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOB)
#define | __HAL_RCC_GPIOC_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOC)
#define | __HAL_RCC_GPIOD_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOD)
#define | __HAL_RCC_GPIOE_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOE)
#define | __HAL_RCC_GPIOH_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOH)
#define | __HAL_RCC_ADC_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_ADC)
#define | __HAL_RCC_AES1_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_AES1)
#define | __HAL_RCC_GPIOA_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOA))
#define | __HAL_RCC_GPIOB_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOB))
#define | __HAL_RCC_GPIOC_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOC))
#define | __HAL_RCC_GPIOD_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOD))
#define | __HAL_RCC_GPIOE_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOE))
#define | __HAL_RCC_GPIOH_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOH))
#define | __HAL_RCC_ADC_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_ADC))
#define | __HAL_RCC_AES1_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_AES1))
#define | __HAL_RCC_C2GPIOA_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA)
#define | __HAL_RCC_C2GPIOB_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB)
#define | __HAL_RCC_C2GPIOC_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC)
#define | __HAL_RCC_C2GPIOD_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOD)
#define | __HAL_RCC_C2GPIOE_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE)
#define | __HAL_RCC_C2GPIOH_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH)
#define | __HAL_RCC_C2ADC_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_ADC)
#define | __HAL_RCC_C2AES1_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_AES1)
#define | __HAL_RCC_C2GPIOA_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA))
#define | __HAL_RCC_C2GPIOB_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB))
#define | __HAL_RCC_C2GPIOC_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC))
#define | __HAL_RCC_C2GPIOD_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOD))
#define | __HAL_RCC_C2GPIOE_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE))
#define | __HAL_RCC_C2GPIOH_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH))
#define | __HAL_RCC_C2ADC_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_ADC))
#define | __HAL_RCC_C2AES1_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_AES1))

Detailed Description

Check whether the AHB2 peripheral clock is enabled or not.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_ADC_IS_CLK_DISABLED ( ) !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_ADC))

Definition at line 1036 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_ADC_IS_CLK_ENABLED ( ) LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_ADC)

Definition at line 1023 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_AES1_IS_CLK_DISABLED ( ) !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_AES1))

Definition at line 1038 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_AES1_IS_CLK_ENABLED ( ) LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_AES1)

Definition at line 1025 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2ADC_IS_CLK_DISABLED ( ) !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_ADC))

Definition at line 1436 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2ADC_IS_CLK_ENABLED ( ) LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_ADC)

Definition at line 1423 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2AES1_IS_CLK_DISABLED ( ) !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_AES1))

Definition at line 1438 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2AES1_IS_CLK_ENABLED ( ) LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_AES1)

Definition at line 1425 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOA_IS_CLK_DISABLED ( ) !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA))

Definition at line 1428 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOA_IS_CLK_ENABLED ( ) LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA)

Definition at line 1415 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOB_IS_CLK_DISABLED ( ) !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB))

Definition at line 1429 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOB_IS_CLK_ENABLED ( ) LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB)

Definition at line 1416 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOC_IS_CLK_DISABLED ( ) !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC))

Definition at line 1430 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOC_IS_CLK_ENABLED ( ) LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC)

Definition at line 1417 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOD_IS_CLK_DISABLED ( ) !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOD))

Definition at line 1432 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOD_IS_CLK_ENABLED ( ) LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOD)

Definition at line 1419 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOE_IS_CLK_DISABLED ( ) !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE))

Definition at line 1434 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOE_IS_CLK_ENABLED ( ) LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE)

Definition at line 1421 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOH_IS_CLK_DISABLED ( ) !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH))

Definition at line 1435 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOH_IS_CLK_ENABLED ( ) LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH)

Definition at line 1422 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOA_IS_CLK_DISABLED ( ) !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOA))

Definition at line 1028 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOA_IS_CLK_ENABLED ( ) LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOA)

Definition at line 1015 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOB_IS_CLK_DISABLED ( ) !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOB))

Definition at line 1029 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOB_IS_CLK_ENABLED ( ) LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOB)

Definition at line 1016 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOC_IS_CLK_DISABLED ( ) !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOC))

Definition at line 1030 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOC_IS_CLK_ENABLED ( ) LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOC)

Definition at line 1017 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOD_IS_CLK_DISABLED ( ) !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOD))

Definition at line 1032 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOD_IS_CLK_ENABLED ( ) LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOD)

Definition at line 1019 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOE_IS_CLK_DISABLED ( ) !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOE))

Definition at line 1034 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOE_IS_CLK_ENABLED ( ) LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOE)

Definition at line 1021 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOH_IS_CLK_DISABLED ( ) !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOH))

Definition at line 1035 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOH_IS_CLK_ENABLED ( ) LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOH)

Definition at line 1022 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: AHB3 Peripheral Clock Enabled or Disabled Status

Defines
AHB3 Peripheral Clock Enabled or Disabled Status
RCC Exported Macros

Check whether the AHB3 peripheral clock is enabled or not. More...

Defines

#define | __HAL_RCC_QUADSPI_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_QUADSPI)
#define | __HAL_RCC_PKA_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_PKA)
#define | __HAL_RCC_AES2_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_AES2)
#define | __HAL_RCC_RNG_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_RNG)
#define | __HAL_RCC_HSEM_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_HSEM)
#define | __HAL_RCC_IPCC_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_IPCC)
#define | __HAL_RCC_FLASH_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_FLASH)
#define | __HAL_RCC_QUADSPI_IS_CLK_DISABLED() !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_QUADSPI))
#define | __HAL_RCC_PKA_IS_CLK_DISABLED() !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_PKA))
#define | __HAL_RCC_AES2_IS_CLK_DISABLED() !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_AES2))
#define | __HAL_RCC_RNG_IS_CLK_DISABLED() !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_RNG))
#define | __HAL_RCC_HSEM_IS_CLK_DISABLED() !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_HSEM))
#define | __HAL_RCC_IPCC_IS_CLK_DISABLED() !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_IPCC))
#define | __HAL_RCC_FLASH_IS_CLK_DISABLED() !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_FLASH))
#define | __HAL_RCC_C2PKA_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_PKA)
#define | __HAL_RCC_C2AES2_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_AES2)
#define | __HAL_RCC_C2RNG_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_RNG)
#define | __HAL_RCC_C2HSEM_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_HSEM)
#define | __HAL_RCC_C2IPCC_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_IPCC)
#define | __HAL_RCC_C2FLASH_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_FLASH)
#define | __HAL_RCC_C2PKA_IS_CLK_DISABLED() !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_PKA))
#define | __HAL_RCC_C2AES2_IS_CLK_DISABLED() !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_AES2))
#define | __HAL_RCC_C2RNG_IS_CLK_DISABLED() !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_RNG))
#define | __HAL_RCC_C2HSEM_IS_CLK_DISABLED() !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_HSEM))
#define | __HAL_RCC_C2IPCC_IS_CLK_DISABLED() !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_IPCC))
#define | __HAL_RCC_C2FLASH_IS_CLK_DISABLED() !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_FLASH))

Detailed Description

Check whether the AHB3 peripheral clock is enabled or not.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_AES2_IS_CLK_DISABLED ( ) !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_AES2))

Definition at line 1067 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_AES2_IS_CLK_ENABLED ( ) LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_AES2)

Definition at line 1057 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2AES2_IS_CLK_DISABLED ( ) !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_AES2))

Definition at line 1461 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2AES2_IS_CLK_ENABLED ( ) LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_AES2)

Definition at line 1454 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2FLASH_IS_CLK_DISABLED ( ) !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_FLASH))

Definition at line 1465 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2FLASH_IS_CLK_ENABLED ( ) LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_FLASH)

Definition at line 1458 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2HSEM_IS_CLK_DISABLED ( ) !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_HSEM))

Definition at line 1463 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2HSEM_IS_CLK_ENABLED ( ) LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_HSEM)

Definition at line 1456 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2IPCC_IS_CLK_DISABLED ( ) !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_IPCC))

Definition at line 1464 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2IPCC_IS_CLK_ENABLED ( ) LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_IPCC)

Definition at line 1457 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2PKA_IS_CLK_DISABLED ( ) !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_PKA))

Definition at line 1460 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2PKA_IS_CLK_ENABLED ( ) LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_PKA)

Definition at line 1453 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2RNG_IS_CLK_DISABLED ( ) !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_RNG))

Definition at line 1462 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2RNG_IS_CLK_ENABLED ( ) LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_RNG)

Definition at line 1455 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_FLASH_IS_CLK_DISABLED ( ) !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_FLASH))

Definition at line 1071 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_FLASH_IS_CLK_ENABLED ( ) LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_FLASH)

Definition at line 1061 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_HSEM_IS_CLK_DISABLED ( ) !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_HSEM))

Definition at line 1069 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_HSEM_IS_CLK_ENABLED ( ) LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_HSEM)

Definition at line 1059 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_IPCC_IS_CLK_DISABLED ( ) !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_IPCC))

Definition at line 1070 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_IPCC_IS_CLK_ENABLED ( ) LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_IPCC)

Definition at line 1060 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_PKA_IS_CLK_DISABLED ( ) !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_PKA))

Definition at line 1066 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_PKA_IS_CLK_ENABLED ( ) LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_PKA)

Definition at line 1056 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_QUADSPI_IS_CLK_DISABLED ( ) !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_QUADSPI))

Definition at line 1064 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_QUADSPI_IS_CLK_ENABLED ( ) LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_QUADSPI)

Definition at line 1054 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_RNG_IS_CLK_DISABLED ( ) !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_RNG))

Definition at line 1068 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_RNG_IS_CLK_ENABLED ( ) LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_RNG)

Definition at line 1058 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: APB1 Peripheral Clock Enabled or Disabled Status

Defines
APB1 Peripheral Clock Enabled or Disabled Status
RCC Exported Macros

Check whether the APB1 peripheral clock is enabled or not. More...

Defines

#define | __HAL_RCC_RTCAPB_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_RTCAPB)
#define | __HAL_RCC_WWDG_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_WWDG)
#define | __HAL_RCC_TIM2_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM2)
#define | __HAL_RCC_LCD_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LCD)
#define | __HAL_RCC_SPI2_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_SPI2)
#define | __HAL_RCC_I2C1_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C1)
#define | __HAL_RCC_I2C3_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C3)
#define | __HAL_RCC_CRS_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_CRS)
#define | __HAL_RCC_USB_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_USB)
#define | __HAL_RCC_LPTIM1_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LPTIM1)
#define | __HAL_RCC_LPTIM2_IS_CLK_ENABLED() LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPTIM2)
#define | __HAL_RCC_LPUART1_IS_CLK_ENABLED() LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPUART1)
#define | __HAL_RCC_RTCAPB_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_RTCAPB))
#define | __HAL_RCC_WWDG_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_WWDG))
#define | __HAL_RCC_TIM2_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM2))
#define | __HAL_RCC_LCD_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LCD))
#define | __HAL_RCC_SPI2_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_SPI2))
#define | __HAL_RCC_I2C1_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C1))
#define | __HAL_RCC_I2C3_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C3))
#define | __HAL_RCC_CRS_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_CRS))
#define | __HAL_RCC_USB_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_USB))
#define | __HAL_RCC_LPTIM1_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LPTIM1))
#define | __HAL_RCC_LPTIM2_IS_CLK_DISABLED() !(LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPTIM2))
#define | __HAL_RCC_LPUART1_IS_CLK_DISABLED() !(LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPUART1))
#define | __HAL_RCC_C2RTCAPB_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB)
#define | __HAL_RCC_C2TIM2_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_TIM2)
#define | __HAL_RCC_C2LCD_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LCD)
#define | __HAL_RCC_C2SPI2_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_SPI2)
#define | __HAL_RCC_C2I2C1_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C1)
#define | __HAL_RCC_C2I2C3_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C3)
#define | __HAL_RCC_C2CRS_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_CRS)
#define | __HAL_RCC_C2USB_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_USB)
#define | __HAL_RCC_C2LPTIM1_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1)
#define | __HAL_RCC_C2LPTIM2_IS_CLK_ENABLED() LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2)
#define | __HAL_RCC_C2LPUART1_IS_CLK_ENABLED() LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP2_PERIPH_LPUART1)
#define | __HAL_RCC_C2RTCAPB_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB))
#define | __HAL_RCC_C2TIM2_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_TIM2))
#define | __HAL_RCC_C2LCD_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LCD))
#define | __HAL_RCC_C2SPI2_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_SPI2))
#define | __HAL_RCC_C2I2C1_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C1))
#define | __HAL_RCC_C2I2C3_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C3))
#define | __HAL_RCC_C2CRS_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_CRS))
#define | __HAL_RCC_C2USB_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_USB))
#define | __HAL_RCC_C2LPTIM1_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1))
#define | __HAL_RCC_C2LPTIM2_IS_CLK_DISABLED() !(LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2))
#define | __HAL_RCC_C2LPUART1_IS_CLK_DISABLED() !(LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1))

Detailed Description

Check whether the APB1 peripheral clock is enabled or not.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_C2CRS_IS_CLK_DISABLED ( ) !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_CRS))

Definition at line 1517 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2CRS_IS_CLK_ENABLED ( ) LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_CRS)

Definition at line 1492 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2I2C1_IS_CLK_DISABLED ( ) !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C1))

Definition at line 1512 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2I2C1_IS_CLK_ENABLED ( ) LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C1)

Definition at line 1487 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2I2C3_IS_CLK_DISABLED ( ) !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C3))

Definition at line 1514 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2I2C3_IS_CLK_ENABLED ( ) LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C3)

Definition at line 1489 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2LCD_IS_CLK_DISABLED ( ) !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LCD))

Definition at line 1507 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2LCD_IS_CLK_ENABLED ( ) LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LCD)

Definition at line 1482 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2LPTIM1_IS_CLK_DISABLED ( ) !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1))

Definition at line 1522 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2LPTIM1_IS_CLK_ENABLED ( ) LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1)

Definition at line 1497 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2LPTIM2_IS_CLK_DISABLED ( ) !(LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2))

Definition at line 1524 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2LPTIM2_IS_CLK_ENABLED ( ) LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2)

Definition at line 1499 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2LPUART1_IS_CLK_DISABLED ( ) !(LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1))

Definition at line 1526 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2LPUART1_IS_CLK_ENABLED ( ) LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP2_PERIPH_LPUART1)

Definition at line 1501 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2RTCAPB_IS_CLK_DISABLED ( ) !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB))

Definition at line 1504 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2RTCAPB_IS_CLK_ENABLED ( ) LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB)

Definition at line 1479 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2SPI2_IS_CLK_DISABLED ( ) !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_SPI2))

Definition at line 1510 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2SPI2_IS_CLK_ENABLED ( ) LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_SPI2)

Definition at line 1485 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TIM2_IS_CLK_DISABLED ( ) !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_TIM2))

Definition at line 1505 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TIM2_IS_CLK_ENABLED ( ) LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_TIM2)

Definition at line 1480 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2USB_IS_CLK_DISABLED ( ) !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_USB))

Definition at line 1520 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2USB_IS_CLK_ENABLED ( ) LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_USB)

Definition at line 1495 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_CRS_IS_CLK_DISABLED ( ) !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_CRS))

Definition at line 1125 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_CRS_IS_CLK_ENABLED ( ) LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_CRS)

Definition at line 1099 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_I2C1_IS_CLK_DISABLED ( ) !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C1))

Definition at line 1120 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_I2C1_IS_CLK_ENABLED ( ) LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C1)

Definition at line 1094 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_I2C3_IS_CLK_DISABLED ( ) !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C3))

Definition at line 1122 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_I2C3_IS_CLK_ENABLED ( ) LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C3)

Definition at line 1096 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_LCD_IS_CLK_DISABLED ( ) !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LCD))

Definition at line 1115 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_LCD_IS_CLK_ENABLED ( ) LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LCD)

Definition at line 1089 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED ( ) !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LPTIM1))

Definition at line 1130 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED ( ) LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LPTIM1)

Definition at line 1104 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED ( ) !(LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPTIM2))

Definition at line 1132 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED ( ) LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPTIM2)

Definition at line 1106 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_LPUART1_IS_CLK_DISABLED ( ) !(LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPUART1))

Definition at line 1134 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_LPUART1_IS_CLK_ENABLED ( ) LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPUART1)

Definition at line 1108 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED ( ) !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_RTCAPB))

Definition at line 1111 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED ( ) LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_RTCAPB)

Definition at line 1085 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_SPI2_IS_CLK_DISABLED ( ) !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_SPI2))

Definition at line 1118 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_SPI2_IS_CLK_ENABLED ( ) LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_SPI2)

Definition at line 1092 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM2_IS_CLK_DISABLED ( ) !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM2))

Definition at line 1113 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM2_IS_CLK_ENABLED ( ) LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM2)

Definition at line 1087 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_USB_IS_CLK_DISABLED ( ) !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_USB))

Definition at line 1128 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_USB_IS_CLK_ENABLED ( ) LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_USB)

Definition at line 1102 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_WWDG_IS_CLK_DISABLED ( ) !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_WWDG))

Definition at line 1112 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_WWDG_IS_CLK_ENABLED ( ) LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_WWDG)

Definition at line 1086 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: APB2 Peripheral Clock Enabled or Disabled Status

Defines
APB2 Peripheral Clock Enabled or Disabled Status
RCC Exported Macros

Check whether the APB2 peripheral clock is enabled or not. More...

Defines

#define | __HAL_RCC_TIM1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM1)
#define | __HAL_RCC_SPI1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SPI1)
#define | __HAL_RCC_USART1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_USART1)
#define | __HAL_RCC_TIM16_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM16)
#define | __HAL_RCC_TIM17_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM17)
#define | __HAL_RCC_SAI1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SAI1)
#define | __HAL_RCC_TIM1_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM1))
#define | __HAL_RCC_SPI1_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SPI1))
#define | __HAL_RCC_USART1_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_USART1))
#define | __HAL_RCC_TIM16_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM16))
#define | __HAL_RCC_TIM17_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM17))
#define | __HAL_RCC_SAI1_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SAI1))
#define | __HAL_RCC_C2TIM1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM1)
#define | __HAL_RCC_C2SPI1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SPI1)
#define | __HAL_RCC_C2USART1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_USART1)
#define | __HAL_RCC_C2TIM16_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM16)
#define | __HAL_RCC_C2TIM17_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM17)
#define | __HAL_RCC_C2SAI1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SAI1)
#define | __HAL_RCC_C2TIM1_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM1))
#define | __HAL_RCC_C2SPI1_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SPI1))
#define | __HAL_RCC_C2USART1_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_USART1))
#define | __HAL_RCC_C2TIM16_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM16))
#define | __HAL_RCC_C2TIM17_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM17))
#define | __HAL_RCC_C2SAI1_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SAI1))

Detailed Description

Check whether the APB2 peripheral clock is enabled or not.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_C2SAI1_IS_CLK_DISABLED ( ) !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SAI1))

Definition at line 1556 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2SAI1_IS_CLK_ENABLED ( ) LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SAI1)

Definition at line 1547 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2SPI1_IS_CLK_DISABLED ( ) !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SPI1))

Definition at line 1551 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2SPI1_IS_CLK_ENABLED ( ) LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SPI1)

Definition at line 1542 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TIM16_IS_CLK_DISABLED ( ) !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM16))

Definition at line 1553 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TIM16_IS_CLK_ENABLED ( ) LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM16)

Definition at line 1544 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TIM17_IS_CLK_DISABLED ( ) !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM17))

Definition at line 1554 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TIM17_IS_CLK_ENABLED ( ) LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM17)

Definition at line 1545 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TIM1_IS_CLK_DISABLED ( ) !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM1))

Definition at line 1550 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TIM1_IS_CLK_ENABLED ( ) LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM1)

Definition at line 1541 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2USART1_IS_CLK_DISABLED ( ) !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_USART1))

Definition at line 1552 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2USART1_IS_CLK_ENABLED ( ) LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_USART1)

Definition at line 1543 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_SAI1_IS_CLK_DISABLED ( ) !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SAI1))

Definition at line 1165 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_SAI1_IS_CLK_ENABLED ( ) LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SAI1)

Definition at line 1155 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_SPI1_IS_CLK_DISABLED ( ) !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SPI1))

Definition at line 1160 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_SPI1_IS_CLK_ENABLED ( ) LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SPI1)

Definition at line 1150 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM16_IS_CLK_DISABLED ( ) !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM16))

Definition at line 1162 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM16_IS_CLK_ENABLED ( ) LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM16)

Definition at line 1152 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM17_IS_CLK_DISABLED ( ) !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM17))

Definition at line 1163 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM17_IS_CLK_ENABLED ( ) LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM17)

Definition at line 1153 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM1_IS_CLK_DISABLED ( ) !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM1))

Definition at line 1159 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM1_IS_CLK_ENABLED ( ) LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM1)

Definition at line 1149 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_USART1_IS_CLK_DISABLED ( ) !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_USART1))

Definition at line 1161 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_USART1_IS_CLK_ENABLED ( ) LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_USART1)

Definition at line 1151 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: APB3 Peripheral Clock Enable Disable

Defines
APB3 Peripheral Clock Enable Disable
RCC Exported Macros

Enable or disable the APB3 peripheral clock. More...

Defines

#define | __HAL_RCC_C2BLE_CLK_ENABLE() LL_C2_APB3_GRP1_EnableClock(LL_C2_APB3_GRP1_PERIPH_BLE)
#define | __HAL_RCC_C2802_CLK_ENABLE() LL_C2_APB3_GRP1_EnableClock(LL_C2_APB3_GRP1_PERIPH_802)
#define | __HAL_RCC_C2BLE_CLK_DISABLE() LL_C2_APB3_GRP1_DisableClock(LL_C2_APB3_GRP1_PERIPH_BLE)
#define | __HAL_RCC_C2802_CLK_DISABLE() LL_C2_APB3_GRP1_DisableClock(LL_C2_APB3_GRP1_PERIPH_802)

Detailed Description

Enable or disable the APB3 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_C2802_CLK_DISABLE ( ) LL_C2_APB3_GRP1_DisableClock(LL_C2_APB3_GRP1_PERIPH_802)

Definition at line 1370 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2802_CLK_ENABLE ( ) LL_C2_APB3_GRP1_EnableClock(LL_C2_APB3_GRP1_PERIPH_802)

Definition at line 1367 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2BLE_CLK_DISABLE ( ) LL_C2_APB3_GRP1_DisableClock(LL_C2_APB3_GRP1_PERIPH_BLE)

Definition at line 1369 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2BLE_CLK_ENABLE ( ) LL_C2_APB3_GRP1_EnableClock(LL_C2_APB3_GRP1_PERIPH_BLE)

Definition at line 1366 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: APB3 Peripheral Clock Enabled or Disabled Status

Defines
APB3 Peripheral Clock Enabled or Disabled Status
RCC Exported Macros

Check whether the APB3 peripheral clock is enabled or not. More...

Defines

#define | __HAL_RCC_C2BLE_IS_CLK_ENABLED() LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_BLE)
#define | __HAL_RCC_C2802_IS_CLK_ENABLED() LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_802)
#define | __HAL_RCC_C2BLE_IS_CLK_DISABLED() !(LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_BLE))
#define | __HAL_RCC_C2802_IS_CLK_DISABLED() !(LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_802))

Detailed Description

Check whether the APB3 peripheral clock is enabled or not.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_C2802_IS_CLK_DISABLED ( ) !(LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_802))

Definition at line 1576 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2802_IS_CLK_ENABLED ( ) LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_802)

Definition at line 1573 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2BLE_IS_CLK_DISABLED ( ) !(LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_BLE))

Definition at line 1575 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2BLE_IS_CLK_ENABLED ( ) LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_BLE)

Definition at line 1572 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: AHB1 Peripheral Force Release Reset

Defines
AHB1 Peripheral Force Release Reset
RCC Exported Macros

Force or release AHB1 peripheral reset. More...

Defines

#define | __HAL_RCC_AHB1_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_ALL)
#define | __HAL_RCC_DMA1_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1)
#define | __HAL_RCC_DMA2_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2)
#define | __HAL_RCC_DMAMUX1_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMAMUX1)
#define | __HAL_RCC_CRC_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CRC)
#define | __HAL_RCC_TSC_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_TSC)
#define | __HAL_RCC_AHB1_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ALL)
#define | __HAL_RCC_DMA1_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1)
#define | __HAL_RCC_DMA2_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2)
#define | __HAL_RCC_DMAMUX1_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMAMUX1)
#define | __HAL_RCC_CRC_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC)
#define | __HAL_RCC_TSC_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_TSC)

Detailed Description

Force or release AHB1 peripheral reset.

Define Documentation

#define __HAL_RCC_AHB1_FORCE_RESET ( ) LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_ALL)

Definition at line 1587 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_AHB1_RELEASE_RESET ( ) LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ALL)

Definition at line 1597 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_CRC_FORCE_RESET ( ) LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CRC)

Definition at line 1593 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_CRC_RELEASE_RESET ( ) LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC)

Definition at line 1603 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_DMA1_FORCE_RESET ( ) LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1)

Definition at line 1588 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_DMA1_RELEASE_RESET ( ) LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1)

Definition at line 1598 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_DMA2_FORCE_RESET ( ) LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2)

Definition at line 1590 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_DMA2_RELEASE_RESET ( ) LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2)

Definition at line 1600 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_DMAMUX1_FORCE_RESET ( ) LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMAMUX1)

Definition at line 1592 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_DMAMUX1_RELEASE_RESET ( ) LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMAMUX1)

Definition at line 1602 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TSC_FORCE_RESET ( ) LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_TSC)

Definition at line 1594 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TSC_RELEASE_RESET ( ) LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_TSC)

Definition at line 1604 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: AHB2 Peripheral Force Release Reset

Defines
AHB2 Peripheral Force Release Reset
RCC Exported Macros

Force or release AHB2 peripheral reset. More...

Defines

#define | __HAL_RCC_AHB2_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ALL)
#define | __HAL_RCC_GPIOA_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOA)
#define | __HAL_RCC_GPIOB_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOB)
#define | __HAL_RCC_GPIOC_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOC)
#define | __HAL_RCC_GPIOD_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOD)
#define | __HAL_RCC_GPIOE_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOE)
#define | __HAL_RCC_GPIOH_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOH)
#define | __HAL_RCC_ADC_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC)
#define | __HAL_RCC_AES1_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_AES1)
#define | __HAL_RCC_AHB2_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ALL)
#define | __HAL_RCC_GPIOA_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOA)
#define | __HAL_RCC_GPIOB_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOB)
#define | __HAL_RCC_GPIOC_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOC)
#define | __HAL_RCC_GPIOD_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOD)
#define | __HAL_RCC_GPIOE_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOE)
#define | __HAL_RCC_GPIOH_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOH)
#define | __HAL_RCC_ADC_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC)
#define | __HAL_RCC_AES1_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_AES1)

Detailed Description

Force or release AHB2 peripheral reset.

Define Documentation

#define __HAL_RCC_ADC_FORCE_RESET ( ) LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC)

Definition at line 1624 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_ADC_RELEASE_RESET ( ) LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC)

Definition at line 1638 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_AES1_FORCE_RESET ( ) LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_AES1)

Definition at line 1626 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_AES1_RELEASE_RESET ( ) LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_AES1)

Definition at line 1640 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_AHB2_FORCE_RESET ( ) LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ALL)

Definition at line 1615 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_AHB2_RELEASE_RESET ( ) LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ALL)

Definition at line 1629 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_GPIOA_FORCE_RESET ( ) LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOA)

Definition at line 1616 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOA_RELEASE_RESET ( ) LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOA)

Definition at line 1630 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOB_FORCE_RESET ( ) LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOB)

Definition at line 1617 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOB_RELEASE_RESET ( ) LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOB)

Definition at line 1631 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOC_FORCE_RESET ( ) LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOC)

Definition at line 1618 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOC_RELEASE_RESET ( ) LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOC)

Definition at line 1632 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOD_FORCE_RESET ( ) LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOD)

Definition at line 1620 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOD_RELEASE_RESET ( ) LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOD)

Definition at line 1634 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOE_FORCE_RESET ( ) LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOE)

Definition at line 1622 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOE_RELEASE_RESET ( ) LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOE)

Definition at line 1636 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOH_FORCE_RESET ( ) LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOH)

Definition at line 1623 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOH_RELEASE_RESET ( ) LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOH)

Definition at line 1637 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: AHB3 Peripheral Force Release Reset

Defines
AHB3 Peripheral Force Release Reset
RCC Exported Macros

Force or release AHB3 peripheral reset. More...

Defines

#define | __HAL_RCC_AHB3_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ALL)
#define | __HAL_RCC_QUADSPI_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_QUADSPI)
#define | __HAL_RCC_PKA_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_PKA)
#define | __HAL_RCC_AES2_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_AES2)
#define | __HAL_RCC_RNG_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_RNG)
#define | __HAL_RCC_HSEM_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_HSEM)
#define | __HAL_RCC_IPCC_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_IPCC)
#define | __HAL_RCC_FLASH_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_FLASH)
#define | __HAL_RCC_AHB3_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ALL)
#define | __HAL_RCC_QUADSPI_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_QUADSPI)
#define | __HAL_RCC_PKA_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_PKA)
#define | __HAL_RCC_AES2_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_AES2)
#define | __HAL_RCC_RNG_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_RNG)
#define | __HAL_RCC_HSEM_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_HSEM)
#define | __HAL_RCC_IPCC_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_IPCC)
#define | __HAL_RCC_FLASH_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_FLASH)

Detailed Description

Force or release AHB3 peripheral reset.

Define Documentation

#define __HAL_RCC_AES2_FORCE_RESET ( ) LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_AES2)

Definition at line 1656 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_AES2_RELEASE_RESET ( ) LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_AES2)

Definition at line 1667 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_AHB3_FORCE_RESET ( ) LL_AHB3_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ALL)

Definition at line 1651 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_AHB3_RELEASE_RESET ( ) LL_AHB3_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ALL)

Definition at line 1662 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_FLASH_FORCE_RESET ( ) LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_FLASH)

Definition at line 1660 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_FLASH_RELEASE_RESET ( ) LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_FLASH)

Definition at line 1671 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_HSEM_FORCE_RESET ( ) LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_HSEM)

Definition at line 1658 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_HSEM_RELEASE_RESET ( ) LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_HSEM)

Definition at line 1669 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_IPCC_FORCE_RESET ( ) LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_IPCC)

Definition at line 1659 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_IPCC_RELEASE_RESET ( ) LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_IPCC)

Definition at line 1670 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_PKA_FORCE_RESET ( ) LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_PKA)

Definition at line 1655 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_PKA_RELEASE_RESET ( ) LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_PKA)

Definition at line 1666 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_QUADSPI_FORCE_RESET ( ) LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_QUADSPI)

Definition at line 1653 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_QUADSPI_RELEASE_RESET ( ) LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_QUADSPI)

Definition at line 1664 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_RNG_FORCE_RESET ( ) LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_RNG)

Definition at line 1657 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_RNG_RELEASE_RESET ( ) LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_RNG)

Definition at line 1668 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: APB1 Peripheral Force Release Reset

Defines
APB1 Peripheral Force Release Reset
RCC Exported Macros

Force or release APB1 peripheral reset. More...

Defines

#define | __HAL_RCC_APB1L_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_ALL)
#define | __HAL_RCC_TIM2_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2)
#define | __HAL_RCC_LCD_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LCD)
#define | __HAL_RCC_SPI2_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2)
#define | __HAL_RCC_I2C1_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1)
#define | __HAL_RCC_I2C3_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3)
#define | __HAL_RCC_CRS_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_CRS)
#define | __HAL_RCC_USB_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USB)
#define | __HAL_RCC_LPTIM1_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1)
#define | __HAL_RCC_APB1H_FORCE_RESET() LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_ALL)
#define | __HAL_RCC_LPUART1_FORCE_RESET() LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPUART1)
#define | __HAL_RCC_LPTIM2_FORCE_RESET() LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPTIM2)
#define | __HAL_RCC_APB1_FORCE_RESET()
#define | __HAL_RCC_APB1L_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_ALL)
#define | __HAL_RCC_TIM2_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2)
#define | __HAL_RCC_LCD_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LCD)
#define | __HAL_RCC_SPI2_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2)
#define | __HAL_RCC_I2C1_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1)
#define | __HAL_RCC_I2C3_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3)
#define | __HAL_RCC_CRS_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_CRS)
#define | __HAL_RCC_USB_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USB)
#define | __HAL_RCC_LPTIM1_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1)
#define | __HAL_RCC_APB1H_RELEASE_RESET() LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_ALL)
#define | __HAL_RCC_LPUART1_RELEASE_RESET() LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPUART1)
#define | __HAL_RCC_LPTIM2_RELEASE_RESET() LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPTIM2)
#define | __HAL_RCC_APB1_RELEASE_RESET()

Detailed Description

Force or release APB1 peripheral reset.

Define Documentation

#define __HAL_RCC_APB1_FORCE_RESET ( )
Value:
do { \
                                           __HAL_RCC_APB1L_FORCE_RESET();\
                                           __HAL_RCC_APB1H_FORCE_RESET();\
                                        } while(0U)

Definition at line 1707 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_APB1_RELEASE_RESET ( )
Value:
do { \
                                           __HAL_RCC_APB1L_RELEASE_RESET();\
                                           __HAL_RCC_APB1H_RELEASE_RESET();\
                                        } while(0U)

Definition at line 1738 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_APB1H_FORCE_RESET ( ) LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_ALL)

Definition at line 1701 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_APB1H_RELEASE_RESET ( ) LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_ALL)

Definition at line 1732 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_APB1L_FORCE_RESET ( ) LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_ALL)

Definition at line 1681 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_APB1L_RELEASE_RESET ( ) LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_ALL)

Definition at line 1712 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_CRS_FORCE_RESET ( ) LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_CRS)

Definition at line 1694 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCCEx_CRSConfig().

#define __HAL_RCC_CRS_RELEASE_RESET ( ) LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_CRS)

Definition at line 1725 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCCEx_CRSConfig().

#define __HAL_RCC_I2C1_FORCE_RESET ( ) LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1)

Definition at line 1689 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_I2C1_RELEASE_RESET ( ) LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1)

Definition at line 1720 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_I2C3_FORCE_RESET ( ) LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3)

Definition at line 1691 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_I2C3_RELEASE_RESET ( ) LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3)

Definition at line 1722 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_LCD_FORCE_RESET ( ) LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LCD)

Definition at line 1684 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_LCD_RELEASE_RESET ( ) LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LCD)

Definition at line 1715 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_FORCE_RESET ( ) LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1)

Definition at line 1699 of file stm32wbxx_hal_rcc.h.

Referenced by LPTIM_Disable().

#define __HAL_RCC_LPTIM1_RELEASE_RESET ( ) LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1)

Definition at line 1730 of file stm32wbxx_hal_rcc.h.

Referenced by LPTIM_Disable().

#define __HAL_RCC_LPTIM2_FORCE_RESET ( ) LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPTIM2)

Definition at line 1705 of file stm32wbxx_hal_rcc.h.

Referenced by LPTIM_Disable().

#define __HAL_RCC_LPTIM2_RELEASE_RESET ( ) LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPTIM2)

Definition at line 1736 of file stm32wbxx_hal_rcc.h.

Referenced by LPTIM_Disable().

#define __HAL_RCC_LPUART1_FORCE_RESET ( ) LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPUART1)

Definition at line 1703 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_LPUART1_RELEASE_RESET ( ) LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPUART1)

Definition at line 1734 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_SPI2_FORCE_RESET ( ) LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2)

Definition at line 1687 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_SPI2_RELEASE_RESET ( ) LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2)

Definition at line 1718 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM2_FORCE_RESET ( ) LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2)

Definition at line 1682 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM2_RELEASE_RESET ( ) LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2)

Definition at line 1713 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_USB_FORCE_RESET ( ) LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USB)

Definition at line 1697 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_USB_RELEASE_RESET ( ) LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USB)

Definition at line 1728 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: APB2 Peripheral Force Release Reset

Defines
APB2 Peripheral Force Release Reset
RCC Exported Macros

Force or release APB2 peripheral reset. More...

Defines

#define | __HAL_RCC_APB2_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ALL)
#define | __HAL_RCC_TIM1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1)
#define | __HAL_RCC_SPI1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1)
#define | __HAL_RCC_USART1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1)
#define | __HAL_RCC_TIM16_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16)
#define | __HAL_RCC_TIM17_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17)
#define | __HAL_RCC_SAI1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SAI1)
#define | __HAL_RCC_APB2_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ALL)
#define | __HAL_RCC_TIM1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1)
#define | __HAL_RCC_SPI1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1)
#define | __HAL_RCC_USART1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1)
#define | __HAL_RCC_TIM16_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16)
#define | __HAL_RCC_TIM17_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17)
#define | __HAL_RCC_SAI1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SAI1)

Detailed Description

Force or release APB2 peripheral reset.

Define Documentation

#define __HAL_RCC_APB2_FORCE_RESET ( ) LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ALL)

Definition at line 1750 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_APB2_RELEASE_RESET ( ) LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ALL)

Definition at line 1760 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_SAI1_FORCE_RESET ( ) LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SAI1)

Definition at line 1757 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_SAI1_RELEASE_RESET ( ) LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SAI1)

Definition at line 1767 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_SPI1_FORCE_RESET ( ) LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1)

Definition at line 1752 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_SPI1_RELEASE_RESET ( ) LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1)

Definition at line 1762 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM16_FORCE_RESET ( ) LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16)

Definition at line 1754 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM16_RELEASE_RESET ( ) LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16)

Definition at line 1764 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM17_FORCE_RESET ( ) LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17)

Definition at line 1755 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM17_RELEASE_RESET ( ) LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17)

Definition at line 1765 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM1_FORCE_RESET ( ) LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1)

Definition at line 1751 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM1_RELEASE_RESET ( ) LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1)

Definition at line 1761 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_USART1_FORCE_RESET ( ) LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1)

Definition at line 1753 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_USART1_RELEASE_RESET ( ) LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1)

Definition at line 1763 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: APB3 Peripheral Force Release Reset

Defines
APB3 Peripheral Force Release Reset
RCC Exported Macros

Force or release APB3 peripheral reset. More...

Defines

#define | __HAL_RCC_APB3_FORCE_RESET() LL_APB3_GRP1_ForceReset(LL_APB3_GRP1_PERIPH_ALL)
#define | __HAL_RCC_RF_FORCE_RESET() LL_APB3_GRP1_ForceReset(LL_APB3_GRP1_PERIPH_RF)
#define | __HAL_RCC_APB3_RELEASE_RESET() LL_APB3_GRP1_ReleaseReset(LL_APB3_GRP1_PERIPH_ALL)
#define | __HAL_RCC_RF_RELEASE_RESET() LL_APB3_GRP1_ReleaseReset(LL_APB3_GRP1_PERIPH_RF)

Detailed Description

Force or release APB3 peripheral reset.

Define Documentation

#define __HAL_RCC_APB3_FORCE_RESET ( ) LL_APB3_GRP1_ForceReset(LL_APB3_GRP1_PERIPH_ALL)

Definition at line 1777 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_APB3_RELEASE_RESET ( ) LL_APB3_GRP1_ReleaseReset(LL_APB3_GRP1_PERIPH_ALL)

Definition at line 1780 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_RF_FORCE_RESET ( ) LL_APB3_GRP1_ForceReset(LL_APB3_GRP1_PERIPH_RF)

Definition at line 1778 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_RF_RELEASE_RESET ( ) LL_APB3_GRP1_ReleaseReset(LL_APB3_GRP1_PERIPH_RF)

Definition at line 1781 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: AHB1 Peripheral Clock Sleep Enable Disable

Defines
AHB1 Peripheral Clock Sleep Enable Disable
RCC Exported Macros

Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. More...

Defines

#define | __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_DMA1)
#define | __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_DMA2)
#define | __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_DMAMUX1)
#define | __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_SRAM1)
#define | __HAL_RCC_CRC_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_CRC)
#define | __HAL_RCC_TSC_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_TSC)
#define | __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_DMA1)
#define | __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_DMA2)
#define | __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_DMAMUX1)
#define | __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_SRAM1)
#define | __HAL_RCC_CRC_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_CRC)
#define | __HAL_RCC_TSC_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_TSC)
#define | __HAL_RCC_C2DMA1_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA1)
#define | __HAL_RCC_C2DMA2_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA2)
#define | __HAL_RCC_C2DMAMUX1_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1)
#define | __HAL_RCC_C2SRAM1_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_SRAM1)
#define | __HAL_RCC_C2CRC_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_CRC)
#define | __HAL_RCC_C2TSC_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_TSC)
#define | __HAL_RCC_C2DMA1_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA1)
#define | __HAL_RCC_C2DMA2_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA2)
#define | __HAL_RCC_C2DMAMUX1_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1)
#define | __HAL_RCC_C2SRAM1_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_SRAM1)
#define | __HAL_RCC_C2CRC_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_CRC)
#define | __HAL_RCC_C2TSC_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_TSC)

Detailed Description

Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_C2CRC_CLK_SLEEP_DISABLE ( ) LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_CRC)

Definition at line 1829 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2CRC_CLK_SLEEP_ENABLE ( ) LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_CRC)

Definition at line 1819 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2DMA1_CLK_SLEEP_DISABLE ( ) LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA1)

Definition at line 1822 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2DMA1_CLK_SLEEP_ENABLE ( ) LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA1)

Definition at line 1813 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2DMA2_CLK_SLEEP_DISABLE ( ) LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA2)

Definition at line 1824 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2DMA2_CLK_SLEEP_ENABLE ( ) LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA2)

Definition at line 1815 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2DMAMUX1_CLK_SLEEP_DISABLE ( ) LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1)

Definition at line 1826 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2DMAMUX1_CLK_SLEEP_ENABLE ( ) LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1)

Definition at line 1817 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2SRAM1_CLK_SLEEP_DISABLE ( ) LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_SRAM1)

Definition at line 1827 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2SRAM1_CLK_SLEEP_ENABLE ( ) LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_SRAM1)

Definition at line 1818 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TSC_CLK_SLEEP_DISABLE ( ) LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_TSC)

Definition at line 1830 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TSC_CLK_SLEEP_ENABLE ( ) LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_TSC)

Definition at line 1820 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE ( ) LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_CRC)

Definition at line 1810 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE ( ) LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_CRC)

Definition at line 1801 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE ( ) LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_DMA1)

Definition at line 1804 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE ( ) LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_DMA1)

Definition at line 1795 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE ( ) LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_DMA2)

Definition at line 1806 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE ( ) LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_DMA2)

Definition at line 1797 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE ( ) LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_DMAMUX1)

Definition at line 1808 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE ( ) LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_DMAMUX1)

Definition at line 1799 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE ( ) LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_SRAM1)

Definition at line 1809 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE ( ) LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_SRAM1)

Definition at line 1800 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TSC_CLK_SLEEP_DISABLE ( ) LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_TSC)

Definition at line 1811 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TSC_CLK_SLEEP_ENABLE ( ) LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_TSC)

Definition at line 1802 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: AHB2 Peripheral Clock Sleep Enable Disable

Defines
AHB2 Peripheral Clock Sleep Enable Disable
RCC Exported Macros

Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. More...

Defines

#define | __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOA)
#define | __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOB)
#define | __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOC)
#define | __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOD)
#define | __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOE)
#define | __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOH)
#define | __HAL_RCC_ADC_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_ADC)
#define | __HAL_RCC_AES1_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_AES1)
#define | __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOA)
#define | __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOB)
#define | __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOC)
#define | __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOD)
#define | __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOE)
#define | __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOH)
#define | __HAL_RCC_ADC_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_ADC)
#define | __HAL_RCC_AES1_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_AES1)
#define | __HAL_RCC_C2GPIOA_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOA)
#define | __HAL_RCC_C2GPIOB_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOB)
#define | __HAL_RCC_C2GPIOC_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOC)
#define | __HAL_RCC_C2GPIOD_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOD)
#define | __HAL_RCC_C2GPIOE_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOE)
#define | __HAL_RCC_C2GPIOH_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOH)
#define | __HAL_RCC_C2ADC_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_ADC)
#define | __HAL_RCC_C2AES1_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_AES1)
#define | __HAL_RCC_C2GPIOA_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOA)
#define | __HAL_RCC_C2GPIOB_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOB)
#define | __HAL_RCC_C2GPIOC_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOC)
#define | __HAL_RCC_C2GPIOD_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOD)
#define | __HAL_RCC_C2GPIOE_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOE)
#define | __HAL_RCC_C2GPIOH_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOH)
#define | __HAL_RCC_C2ADC_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_ADC)
#define | __HAL_RCC_C2AES1_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_AES1)

Detailed Description

Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_ADC_CLK_SLEEP_DISABLE ( ) LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_ADC)

Definition at line 1865 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_ADC_CLK_SLEEP_ENABLE ( ) LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_ADC)

Definition at line 1852 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_AES1_CLK_SLEEP_DISABLE ( ) LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_AES1)

Definition at line 1867 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_AES1_CLK_SLEEP_ENABLE ( ) LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_AES1)

Definition at line 1854 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2ADC_CLK_SLEEP_DISABLE ( ) LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_ADC)

Definition at line 1891 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2ADC_CLK_SLEEP_ENABLE ( ) LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_ADC)

Definition at line 1878 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2AES1_CLK_SLEEP_DISABLE ( ) LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_AES1)

Definition at line 1893 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2AES1_CLK_SLEEP_ENABLE ( ) LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_AES1)

Definition at line 1880 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOA_CLK_SLEEP_DISABLE ( ) LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOA)

Definition at line 1883 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOA_CLK_SLEEP_ENABLE ( ) LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOA)

Definition at line 1870 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOB_CLK_SLEEP_DISABLE ( ) LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOB)

Definition at line 1884 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOB_CLK_SLEEP_ENABLE ( ) LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOB)

Definition at line 1871 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOC_CLK_SLEEP_DISABLE ( ) LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOC)

Definition at line 1885 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOC_CLK_SLEEP_ENABLE ( ) LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOC)

Definition at line 1872 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOD_CLK_SLEEP_DISABLE ( ) LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOD)

Definition at line 1887 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOD_CLK_SLEEP_ENABLE ( ) LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOD)

Definition at line 1874 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOE_CLK_SLEEP_DISABLE ( ) LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOE)

Definition at line 1889 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOE_CLK_SLEEP_ENABLE ( ) LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOE)

Definition at line 1876 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOH_CLK_SLEEP_DISABLE ( ) LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOH)

Definition at line 1890 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOH_CLK_SLEEP_ENABLE ( ) LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOH)

Definition at line 1877 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE ( ) LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOA)

Definition at line 1857 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE ( ) LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOA)

Definition at line 1844 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE ( ) LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOB)

Definition at line 1858 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE ( ) LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOB)

Definition at line 1845 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE ( ) LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOC)

Definition at line 1859 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE ( ) LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOC)

Definition at line 1846 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE ( ) LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOD)

Definition at line 1861 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE ( ) LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOD)

Definition at line 1848 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE ( ) LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOE)

Definition at line 1863 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE ( ) LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOE)

Definition at line 1850 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE ( ) LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOH)

Definition at line 1864 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE ( ) LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOH)

Definition at line 1851 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: AHB3 Peripheral Clock Sleep Enable Disable

Defines
AHB3 Peripheral Clock Sleep Enable Disable
RCC Exported Macros

Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. More...

Defines

#define | __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_QUADSPI)
#define | __HAL_RCC_PKA_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_PKA)
#define | __HAL_RCC_AES2_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_AES2)
#define | __HAL_RCC_RNG_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_RNG)
#define | __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_SRAM2)
#define | __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_FLASH)
#define | __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_QUADSPI)
#define | __HAL_RCC_PKA_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_PKA)
#define | __HAL_RCC_AES2_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_AES2)
#define | __HAL_RCC_RNG_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_RNG)
#define | __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_SRAM2)
#define | __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_FLASH)
#define | __HAL_RCC_C2PKA_CLK_SLEEP_ENABLE() LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_PKA)
#define | __HAL_RCC_C2AES2_CLK_SLEEP_ENABLE() LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_AES2)
#define | __HAL_RCC_C2RNG_CLK_SLEEP_ENABLE() LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_RNG)
#define | __HAL_RCC_C2SRAM2_CLK_SLEEP_ENABLE() LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_SRAM2)
#define | __HAL_RCC_C2FLASH_CLK_SLEEP_ENABLE() LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_FLASH)
#define | __HAL_RCC_C2PKA_CLK_SLEEP_DISABLE() LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_PKA)
#define | __HAL_RCC_C2AES2_CLK_SLEEP_DISABLE() LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_AES2)
#define | __HAL_RCC_C2RNG_CLK_SLEEP_DISABLE() LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_RNG)
#define | __HAL_RCC_C2SRAM2_CLK_SLEEP_DISABLE() LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_SRAM2)
#define | __HAL_RCC_C2FLASH_CLK_SLEEP_DISABLE() LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_FLASH)

Detailed Description

Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_AES2_CLK_SLEEP_DISABLE ( ) LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_AES2)

Definition at line 1921 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_AES2_CLK_SLEEP_ENABLE ( ) LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_AES2)

Definition at line 1912 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2AES2_CLK_SLEEP_DISABLE ( ) LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_AES2)

Definition at line 1933 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2AES2_CLK_SLEEP_ENABLE ( ) LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_AES2)

Definition at line 1927 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2FLASH_CLK_SLEEP_DISABLE ( ) LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_FLASH)

Definition at line 1936 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2FLASH_CLK_SLEEP_ENABLE ( ) LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_FLASH)

Definition at line 1930 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2PKA_CLK_SLEEP_DISABLE ( ) LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_PKA)

Definition at line 1932 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2PKA_CLK_SLEEP_ENABLE ( ) LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_PKA)

Definition at line 1926 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2RNG_CLK_SLEEP_DISABLE ( ) LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_RNG)

Definition at line 1934 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2RNG_CLK_SLEEP_ENABLE ( ) LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_RNG)

Definition at line 1928 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2SRAM2_CLK_SLEEP_DISABLE ( ) LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_SRAM2)

Definition at line 1935 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2SRAM2_CLK_SLEEP_ENABLE ( ) LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_SRAM2)

Definition at line 1929 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE ( ) LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_FLASH)

Definition at line 1924 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE ( ) LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_FLASH)

Definition at line 1915 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_PKA_CLK_SLEEP_DISABLE ( ) LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_PKA)

Definition at line 1920 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_PKA_CLK_SLEEP_ENABLE ( ) LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_PKA)

Definition at line 1911 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE ( ) LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_QUADSPI)

Definition at line 1918 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE ( ) LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_QUADSPI)

Definition at line 1909 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE ( ) LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_RNG)

Definition at line 1922 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE ( ) LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_RNG)

Definition at line 1913 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE ( ) LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_SRAM2)

Definition at line 1923 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE ( ) LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_SRAM2)

Definition at line 1914 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: APB1 Peripheral Clock Sleep Enable Disable

Defines
APB1 Peripheral Clock Sleep Enable Disable
RCC Exported Macros

Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. More...

Defines

#define | __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_TIM2)
#define | __HAL_RCC_LCD_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_LCD)
#define | __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_RTCAPB)
#define | __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_WWDG)
#define | __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_SPI2)
#define | __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_I2C1)
#define | __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_I2C3)
#define | __HAL_RCC_CRS_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_CRS)
#define | __HAL_RCC_USB_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_USB)
#define | __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_LPTIM1)
#define | __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() LL_APB1_GRP2_EnableClockSleep(LL_APB1_GRP2_PERIPH_LPUART1)
#define | __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() LL_APB1_GRP2_EnableClockSleep(LL_APB1_GRP2_PERIPH_LPTIM2)
#define | __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_TIM2)
#define | __HAL_RCC_LCD_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_LCD)
#define | __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_RTCAPB)
#define | __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_WWDG)
#define | __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_SPI2)
#define | __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_I2C1)
#define | __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_I2C3)
#define | __HAL_RCC_CRS_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_CRS)
#define | __HAL_RCC_USB_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_USB)
#define | __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_LPTIM1)
#define | __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() LL_APB1_GRP2_DisableClockSleep(LL_APB1_GRP2_PERIPH_LPUART1)
#define | __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() LL_APB1_GRP2_DisableClockSleep(LL_APB1_GRP2_PERIPH_LPTIM2)
#define | __HAL_RCC_C2TIM2_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_TIM2)
#define | __HAL_RCC_C2LCD_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_LCD)
#define | __HAL_RCC_C2RTCAPB_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_RTCAPB)
#define | __HAL_RCC_C2SPI2_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_SPI2)
#define | __HAL_RCC_C2I2C1_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C1)
#define | __HAL_RCC_C2I2C3_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C3)
#define | __HAL_RCC_C2CRS_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_CRS)
#define | __HAL_RCC_C2USB_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_USB)
#define | __HAL_RCC_C2LPTIM1_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_LPTIM1)
#define | __HAL_RCC_C2LPUART1_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP2_EnableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPUART1)
#define | __HAL_RCC_C2LPTIM2_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP2_EnableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPTIM2)
#define | __HAL_RCC_C2TIM2_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_TIM2)
#define | __HAL_RCC_C2LCD_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_LCD)
#define | __HAL_RCC_C2RTCAPB_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_RTCAPB)
#define | __HAL_RCC_C2SPI2_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_SPI2)
#define | __HAL_RCC_C2I2C1_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C1)
#define | __HAL_RCC_C2I2C3_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C3)
#define | __HAL_RCC_C2CRS_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_CRS)
#define | __HAL_RCC_C2USB_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_USB)
#define | __HAL_RCC_C2LPTIM1_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_LPTIM1)
#define | __HAL_RCC_C2LPUART1_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP2_DisableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPUART1)
#define | __HAL_RCC_C2LPTIM2_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP2_DisableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPTIM2)

Detailed Description

Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_C2CRS_CLK_SLEEP_DISABLE ( ) LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_CRS)

Definition at line 2037 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2CRS_CLK_SLEEP_ENABLE ( ) LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_CRS)

Definition at line 2013 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2I2C1_CLK_SLEEP_DISABLE ( ) LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C1)

Definition at line 2032 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2I2C1_CLK_SLEEP_ENABLE ( ) LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C1)

Definition at line 2008 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2I2C3_CLK_SLEEP_DISABLE ( ) LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C3)

Definition at line 2034 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2I2C3_CLK_SLEEP_ENABLE ( ) LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C3)

Definition at line 2010 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2LCD_CLK_SLEEP_DISABLE ( ) LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_LCD)

Definition at line 2026 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2LCD_CLK_SLEEP_ENABLE ( ) LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_LCD)

Definition at line 2002 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2LPTIM1_CLK_SLEEP_DISABLE ( ) LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_LPTIM1)

Definition at line 2042 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2LPTIM1_CLK_SLEEP_ENABLE ( ) LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_LPTIM1)

Definition at line 2018 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2LPTIM2_CLK_SLEEP_DISABLE ( ) LL_C2_APB1_GRP2_DisableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPTIM2)

Definition at line 2046 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2LPTIM2_CLK_SLEEP_ENABLE ( ) LL_C2_APB1_GRP2_EnableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPTIM2)

Definition at line 2022 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2LPUART1_CLK_SLEEP_DISABLE ( ) LL_C2_APB1_GRP2_DisableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPUART1)

Definition at line 2044 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2LPUART1_CLK_SLEEP_ENABLE ( ) LL_C2_APB1_GRP2_EnableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPUART1)

Definition at line 2020 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2RTCAPB_CLK_SLEEP_DISABLE ( ) LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_RTCAPB)

Definition at line 2028 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2RTCAPB_CLK_SLEEP_ENABLE ( ) LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_RTCAPB)

Definition at line 2004 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2SPI2_CLK_SLEEP_DISABLE ( ) LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_SPI2)

Definition at line 2030 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2SPI2_CLK_SLEEP_ENABLE ( ) LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_SPI2)

Definition at line 2006 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TIM2_CLK_SLEEP_DISABLE ( ) LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_TIM2)

Definition at line 2024 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TIM2_CLK_SLEEP_ENABLE ( ) LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_TIM2)

Definition at line 2000 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2USB_CLK_SLEEP_DISABLE ( ) LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_USB)

Definition at line 2040 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2USB_CLK_SLEEP_ENABLE ( ) LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_USB)

Definition at line 2016 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE ( ) LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_CRS)

Definition at line 1989 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE ( ) LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_CRS)

Definition at line 1964 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE ( ) LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_I2C1)

Definition at line 1984 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE ( ) LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_I2C1)

Definition at line 1959 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE ( ) LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_I2C3)

Definition at line 1986 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE ( ) LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_I2C3)

Definition at line 1961 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_LCD_CLK_SLEEP_DISABLE ( ) LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_LCD)

Definition at line 1977 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_LCD_CLK_SLEEP_ENABLE ( ) LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_LCD)

Definition at line 1952 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE ( ) LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_LPTIM1)

Definition at line 1994 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE ( ) LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_LPTIM1)

Definition at line 1969 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE ( ) LL_APB1_GRP2_DisableClockSleep(LL_APB1_GRP2_PERIPH_LPTIM2)

Definition at line 1998 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE ( ) LL_APB1_GRP2_EnableClockSleep(LL_APB1_GRP2_PERIPH_LPTIM2)

Definition at line 1973 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE ( ) LL_APB1_GRP2_DisableClockSleep(LL_APB1_GRP2_PERIPH_LPUART1)

Definition at line 1996 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE ( ) LL_APB1_GRP2_EnableClockSleep(LL_APB1_GRP2_PERIPH_LPUART1)

Definition at line 1971 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE ( ) LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_RTCAPB)

Definition at line 1979 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE ( ) LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_RTCAPB)

Definition at line 1954 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE ( ) LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_SPI2)

Definition at line 1982 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE ( ) LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_SPI2)

Definition at line 1957 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE ( ) LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_TIM2)

Definition at line 1975 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE ( ) LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_TIM2)

Definition at line 1950 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_USB_CLK_SLEEP_DISABLE ( ) LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_USB)

Definition at line 1992 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_USB_CLK_SLEEP_ENABLE ( ) LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_USB)

Definition at line 1967 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE ( ) LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_WWDG)

Definition at line 1980 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE ( ) LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_WWDG)

Definition at line 1955 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: APB2 Peripheral Clock Sleep Enable Disable

Defines
APB2 Peripheral Clock Sleep Enable Disable
RCC Exported Macros

Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. More...

Defines

#define | __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_TIM1)
#define | __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_SPI1)
#define | __HAL_RCC_USART1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_USART1)
#define | __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_TIM16)
#define | __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_TIM17)
#define | __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_SAI1)
#define | __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_TIM1)
#define | __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_SPI1)
#define | __HAL_RCC_USART1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_USART1)
#define | __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_TIM16)
#define | __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_TIM17)
#define | __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_SAI1)
#define | __HAL_RCC_C2TIM1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM1)
#define | __HAL_RCC_C2SPI1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_SPI1)
#define | __HAL_RCC_C2USART1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_USART1)
#define | __HAL_RCC_C2TIM16_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM16)
#define | __HAL_RCC_C2TIM17_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM17)
#define | __HAL_RCC_C2SAI1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_SAI1)
#define | __HAL_RCC_C2TIM1_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM1)
#define | __HAL_RCC_C2SPI1_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_SPI1)
#define | __HAL_RCC_C2USART1_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_USART1)
#define | __HAL_RCC_C2TIM16_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM16)
#define | __HAL_RCC_C2TIM17_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM17)
#define | __HAL_RCC_C2SAI1_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_SAI1)

Detailed Description

Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_C2SAI1_CLK_SLEEP_DISABLE ( ) LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_SAI1)

Definition at line 2093 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2SAI1_CLK_SLEEP_ENABLE ( ) LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_SAI1)

Definition at line 2084 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2SPI1_CLK_SLEEP_DISABLE ( ) LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_SPI1)

Definition at line 2088 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2SPI1_CLK_SLEEP_ENABLE ( ) LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_SPI1)

Definition at line 2079 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TIM16_CLK_SLEEP_DISABLE ( ) LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM16)

Definition at line 2090 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TIM16_CLK_SLEEP_ENABLE ( ) LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM16)

Definition at line 2081 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TIM17_CLK_SLEEP_DISABLE ( ) LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM17)

Definition at line 2091 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TIM17_CLK_SLEEP_ENABLE ( ) LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM17)

Definition at line 2082 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TIM1_CLK_SLEEP_DISABLE ( ) LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM1)

Definition at line 2087 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TIM1_CLK_SLEEP_ENABLE ( ) LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM1)

Definition at line 2078 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2USART1_CLK_SLEEP_DISABLE ( ) LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_USART1)

Definition at line 2089 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2USART1_CLK_SLEEP_ENABLE ( ) LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_USART1)

Definition at line 2080 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE ( ) LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_SAI1)

Definition at line 2075 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE ( ) LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_SAI1)

Definition at line 2066 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE ( ) LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_SPI1)

Definition at line 2070 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE ( ) LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_SPI1)

Definition at line 2061 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE ( ) LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_TIM16)

Definition at line 2072 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE ( ) LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_TIM16)

Definition at line 2063 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE ( ) LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_TIM17)

Definition at line 2073 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE ( ) LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_TIM17)

Definition at line 2064 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE ( ) LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_TIM1)

Definition at line 2069 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE ( ) LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_TIM1)

Definition at line 2060 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE ( ) LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_USART1)

Definition at line 2071 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE ( ) LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_USART1)

Definition at line 2062 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: AHB1 Peripheral Clock Sleep Enabled or Disabled Status

Defines
AHB1 Peripheral Clock Sleep Enabled or Disabled Status
RCC Exported Macros

Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not. More...

Defines

#define | __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != RESET)
#define | __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != RESET)
#define | __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != RESET)
#define | __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != RESET)
#define | __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != RESET)
#define | __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != RESET)
#define | __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == RESET)
#define | __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == RESET)
#define | __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == RESET)
#define | __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == RESET)
#define | __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == RESET)
#define | __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == RESET)
#define | __HAL_RCC_C2DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMA1SMEN) != RESET)
#define | __HAL_RCC_C2DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMA2SMEN) != RESET)
#define | __HAL_RCC_C2DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMAMUX1SMEN) != RESET)
#define | __HAL_RCC_C2SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_SRAM1SMEN) != RESET)
#define | __HAL_RCC_C2CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_CRCSMEN) != RESET)
#define | __HAL_RCC_C2TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_TSCSMEN) != RESET)
#define | __HAL_RCC_C2DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMA1SMEN) == RESET)
#define | __HAL_RCC_C2DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMA2SMEN) == RESET)
#define | __HAL_RCC_C2DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMAMUX1SMEN) == RESET)
#define | __HAL_RCC_C2SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_SRAM1SMEN) == RESET)
#define | __HAL_RCC_C2CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_CRCSMEN) == RESET)
#define | __HAL_RCC_C2TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_TSCSMEN) == RESET)

Detailed Description

Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_C2CRC_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_CRCSMEN) == RESET)

Definition at line 2140 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2CRC_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_CRCSMEN) != RESET)

Definition at line 2131 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2DMA1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMA1SMEN) == RESET)

Definition at line 2134 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2DMA1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMA1SMEN) != RESET)

Definition at line 2125 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2DMA2_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMA2SMEN) == RESET)

Definition at line 2136 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2DMA2_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMA2SMEN) != RESET)

Definition at line 2127 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2DMAMUX1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMAMUX1SMEN) == RESET)

Definition at line 2138 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2DMAMUX1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMAMUX1SMEN) != RESET)

Definition at line 2129 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2SRAM1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_SRAM1SMEN) == RESET)

Definition at line 2139 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2SRAM1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_SRAM1SMEN) != RESET)

Definition at line 2130 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TSC_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_TSCSMEN) == RESET)

Definition at line 2141 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TSC_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_TSCSMEN) != RESET)

Definition at line 2132 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == RESET)

Definition at line 2122 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != RESET)

Definition at line 2113 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == RESET)

Definition at line 2116 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != RESET)

Definition at line 2107 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == RESET)

Definition at line 2118 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != RESET)

Definition at line 2109 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == RESET)

Definition at line 2120 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != RESET)

Definition at line 2111 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == RESET)

Definition at line 2121 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != RESET)

Definition at line 2112 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == RESET)

Definition at line 2123 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != RESET)

Definition at line 2114 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: AHB2 Peripheral Clock Sleep Enabled or Disabled Status

Defines
AHB2 Peripheral Clock Sleep Enabled or Disabled Status
RCC Exported Macros

Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not. More...

Defines

#define | __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != RESET)
#define | __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != RESET)
#define | __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != RESET)
#define | __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != RESET)
#define | __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != RESET)
#define | __HAL_RCC_AES1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AES1SMEN) != RESET)
#define | __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == RESET)
#define | __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == RESET)
#define | __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == RESET)
#define | __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == RESET)
#define | __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == RESET)
#define | __HAL_RCC_AES1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AES1SMEN) == RESET)
#define | __HAL_RCC_C2GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOASMEN) != RESET)
#define | __HAL_RCC_C2GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOBSMEN) != RESET)
#define | __HAL_RCC_C2GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOCSMEN) != RESET)
#define | __HAL_RCC_C2GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIODSMEN) != RESET)
#define | __HAL_RCC_C2GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOESMEN) != RESET)
#define | __HAL_RCC_C2GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOHSMEN) != RESET)
#define | __HAL_RCC_C2ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_ADCSMEN) != RESET)
#define | __HAL_RCC_C2AES1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_AES1SMEN) != RESET)
#define | __HAL_RCC_C2GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOASMEN) == RESET)
#define | __HAL_RCC_C2GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOBSMEN) == RESET)
#define | __HAL_RCC_C2GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOCSMEN) == RESET)
#define | __HAL_RCC_C2GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIODSMEN) == RESET)
#define | __HAL_RCC_C2GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOESMEN) == RESET)
#define | __HAL_RCC_C2GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOHSMEN) == RESET)
#define | __HAL_RCC_C2ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_ADCSMEN) == RESET)
#define | __HAL_RCC_C2AES1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_AES1SMEN) == RESET)

Detailed Description

Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == RESET)

Definition at line 2175 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != RESET)

Definition at line 2162 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_AES1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AES1SMEN) == RESET)

Definition at line 2177 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_AES1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AES1SMEN) != RESET)

Definition at line 2164 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2ADC_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_ADCSMEN) == RESET)

Definition at line 2201 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2ADC_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_ADCSMEN) != RESET)

Definition at line 2188 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2AES1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_AES1SMEN) == RESET)

Definition at line 2203 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2AES1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_AES1SMEN) != RESET)

Definition at line 2190 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOA_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOASMEN) == RESET)

Definition at line 2193 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOA_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOASMEN) != RESET)

Definition at line 2180 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOB_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOBSMEN) == RESET)

Definition at line 2194 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOB_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOBSMEN) != RESET)

Definition at line 2181 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOC_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOCSMEN) == RESET)

Definition at line 2195 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOC_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOCSMEN) != RESET)

Definition at line 2182 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOD_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIODSMEN) == RESET)

Definition at line 2197 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOD_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIODSMEN) != RESET)

Definition at line 2184 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOE_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOESMEN) == RESET)

Definition at line 2199 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOE_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOESMEN) != RESET)

Definition at line 2186 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOH_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOHSMEN) == RESET)

Definition at line 2200 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2GPIOH_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOHSMEN) != RESET)

Definition at line 2187 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == RESET)

Definition at line 2167 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != RESET)

Definition at line 2154 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == RESET)

Definition at line 2168 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != RESET)

Definition at line 2155 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == RESET)

Definition at line 2169 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != RESET)

Definition at line 2156 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == RESET)

Definition at line 2171 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != RESET)

Definition at line 2158 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == RESET)

Definition at line 2173 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != RESET)

Definition at line 2160 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == RESET)

Definition at line 2174 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != RESET)

Definition at line 2161 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: AHB3 Peripheral Clock Sleep Enabled or Disabled Status

Defines
AHB3 Peripheral Clock Sleep Enabled or Disabled Status
RCC Exported Macros

Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not. More...

Defines

#define | __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QUADSPISMEN) != RESET)
#define | __HAL_RCC_PKA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_PKASMEN) != RESET)
#define | __HAL_RCC_AES2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_AES2SMEN) != RESET)
#define | __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_RNGSMEN) != RESET)
#define | __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_SRAM2SMEN) != RESET)
#define | __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FLASHSMEN) != RESET)
#define | __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QUADSPISMEN) == RESET)
#define | __HAL_RCC_PKA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_PKASMEN) == RESET)
#define | __HAL_RCC_AES2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_AES2SMEN) == RESET)
#define | __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_RNGSMEN) == RESET)
#define | __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_SRAM2SMEN) == RESET)
#define | __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FLASHSMEN) == RESET)
#define | __HAL_RCC_C2PKA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_PKASMEN) != RESET)
#define | __HAL_RCC_C2AES2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_AES2SMEN) != RESET)
#define | __HAL_RCC_C2RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_RNGSMEN) != RESET)
#define | __HAL_RCC_C2SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_SRAM2SMEN) != RESET)
#define | __HAL_RCC_C2FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_FLASHSMEN) != RESET)
#define | __HAL_RCC_C2PKA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_PKASMEN) == RESET)
#define | __HAL_RCC_C2AES2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_AES2SMEN) == RESET)
#define | __HAL_RCC_C2RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_RNGSMEN) == RESET)
#define | __HAL_RCC_C2SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_SRAM2SMEN) == RESET)
#define | __HAL_RCC_C2FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_FLASHSMEN) == RESET)

Detailed Description

Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_AES2_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_AES2SMEN) == RESET)

Definition at line 2230 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_AES2_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_AES2SMEN) != RESET)

Definition at line 2221 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2AES2_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_AES2SMEN) == RESET)

Definition at line 2242 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2AES2_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_AES2SMEN) != RESET)

Definition at line 2236 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2FLASH_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_FLASHSMEN) == RESET)

Definition at line 2245 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2FLASH_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_FLASHSMEN) != RESET)

Definition at line 2239 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2PKA_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_PKASMEN) == RESET)

Definition at line 2241 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2PKA_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_PKASMEN) != RESET)

Definition at line 2235 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2RNG_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_RNGSMEN) == RESET)

Definition at line 2243 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2RNG_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_RNGSMEN) != RESET)

Definition at line 2237 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2SRAM2_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_SRAM2SMEN) == RESET)

Definition at line 2244 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2SRAM2_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_SRAM2SMEN) != RESET)

Definition at line 2238 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FLASHSMEN) == RESET)

Definition at line 2233 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FLASHSMEN) != RESET)

Definition at line 2224 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_PKA_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_PKASMEN) == RESET)

Definition at line 2229 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_PKA_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_PKASMEN) != RESET)

Definition at line 2220 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QUADSPISMEN) == RESET)

Definition at line 2227 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QUADSPISMEN) != RESET)

Definition at line 2218 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_RNGSMEN) == RESET)

Definition at line 2231 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_RNGSMEN) != RESET)

Definition at line 2222 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_SRAM2SMEN) == RESET)

Definition at line 2232 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_SRAM2SMEN) != RESET)

Definition at line 2223 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: APB1 Peripheral Clock Sleep Enabled or Disabled Status

Defines
APB1 Peripheral Clock Sleep Enabled or Disabled Status
RCC Exported Macros

Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not. More...

Defines

#define | __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != RESET)
#define | __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != RESET)
#define | __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != RESET)
#define | __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != RESET)
#define | __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != RESET)
#define | __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != RESET)
#define | __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != RESET)
#define | __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != RESET)
#define | __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) != RESET)
#define | __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != RESET)
#define | __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != RESET)
#define | __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != RESET)
#define | __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == RESET)
#define | __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == RESET)
#define | __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == RESET)
#define | __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == RESET)
#define | __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == RESET)
#define | __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == RESET)
#define | __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == RESET)
#define | __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == RESET)
#define | __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) == RESET)
#define | __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == RESET)
#define | __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == RESET)
#define | __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == RESET)
#define | __HAL_RCC_C2TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_TIM2SMEN) != RESET)
#define | __HAL_RCC_C2LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_LCDSMEN) != RESET)
#define | __HAL_RCC_C2RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_RTCAPBSMEN) != RESET)
#define | __HAL_RCC_C2SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_SPI2SMEN) != RESET)
#define | __HAL_RCC_C2I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_I2C1SMEN) != RESET)
#define | __HAL_RCC_C2I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_I2C3SMEN) != RESET)
#define | __HAL_RCC_C2CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_CRSSMEN) != RESET)
#define | __HAL_RCC_C2USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_USBSMEN) != RESET)
#define | __HAL_RCC_C2LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_LPTIM1SMEN) != RESET)
#define | __HAL_RCC_C2LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR2, RCC_C2APB1SMENR2_LPUART1SMEN) != RESET)
#define | __HAL_RCC_C2LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR2, RCC_C2APB1SMENR2_LPTIM2SMEN) != RESET)
#define | __HAL_RCC_C2TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_TIM2SMEN) == RESET)
#define | __HAL_RCC_C2LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_LCDSMEN) == RESET)
#define | __HAL_RCC_C2RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_RTCAPBSMEN) == RESET)
#define | __HAL_RCC_C2SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_SPI2SMEN) == RESET)
#define | __HAL_RCC_C2I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_I2C1SMEN) == RESET)
#define | __HAL_RCC_C2I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_I2C3SMEN) == RESET)
#define | __HAL_RCC_C2CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_CRSSMEN) == RESET)
#define | __HAL_RCC_C2USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_USBSMEN) == RESET)
#define | __HAL_RCC_C2LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_LPTIM1SMEN) == RESET)
#define | __HAL_RCC_C2LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR2, RCC_C2APB1SMENR2_LPUART1SMEN) == RESET)
#define | __HAL_RCC_C2LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR2, RCC_C2APB1SMENR2_LPTIM2SMEN) == RESET)

Detailed Description

Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_C2CRS_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_CRSSMEN) == RESET)

Definition at line 2346 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2CRS_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_CRSSMEN) != RESET)

Definition at line 2322 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2I2C1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_I2C1SMEN) == RESET)

Definition at line 2341 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2I2C1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_I2C1SMEN) != RESET)

Definition at line 2317 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2I2C3_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_I2C3SMEN) == RESET)

Definition at line 2343 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2I2C3_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_I2C3SMEN) != RESET)

Definition at line 2319 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2LCD_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_LCDSMEN) == RESET)

Definition at line 2335 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2LCD_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_LCDSMEN) != RESET)

Definition at line 2311 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2LPTIM1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_LPTIM1SMEN) == RESET)

Definition at line 2351 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2LPTIM1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_LPTIM1SMEN) != RESET)

Definition at line 2327 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2LPTIM2_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->C2APB1SMENR2, RCC_C2APB1SMENR2_LPTIM2SMEN) == RESET)

Definition at line 2355 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2LPTIM2_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->C2APB1SMENR2, RCC_C2APB1SMENR2_LPTIM2SMEN) != RESET)

Definition at line 2331 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2LPUART1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->C2APB1SMENR2, RCC_C2APB1SMENR2_LPUART1SMEN) == RESET)

Definition at line 2353 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2LPUART1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->C2APB1SMENR2, RCC_C2APB1SMENR2_LPUART1SMEN) != RESET)

Definition at line 2329 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2RTCAPB_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_RTCAPBSMEN) == RESET)

Definition at line 2337 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2RTCAPB_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_RTCAPBSMEN) != RESET)

Definition at line 2313 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2SPI2_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_SPI2SMEN) == RESET)

Definition at line 2339 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2SPI2_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_SPI2SMEN) != RESET)

Definition at line 2315 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TIM2_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_TIM2SMEN) == RESET)

Definition at line 2333 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TIM2_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_TIM2SMEN) != RESET)

Definition at line 2309 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2USB_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_USBSMEN) == RESET)

Definition at line 2349 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2USB_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_USBSMEN) != RESET)

Definition at line 2325 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == RESET)

Definition at line 2298 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != RESET)

Definition at line 2273 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == RESET)

Definition at line 2293 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != RESET)

Definition at line 2268 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == RESET)

Definition at line 2295 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != RESET)

Definition at line 2270 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == RESET)

Definition at line 2286 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != RESET)

Definition at line 2261 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == RESET)

Definition at line 2303 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != RESET)

Definition at line 2278 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == RESET)

Definition at line 2307 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != RESET)

Definition at line 2282 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == RESET)

Definition at line 2305 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != RESET)

Definition at line 2280 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == RESET)

Definition at line 2288 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != RESET)

Definition at line 2263 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == RESET)

Definition at line 2291 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != RESET)

Definition at line 2266 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == RESET)

Definition at line 2284 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != RESET)

Definition at line 2259 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) == RESET)

Definition at line 2301 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) != RESET)

Definition at line 2276 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == RESET)

Definition at line 2289 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != RESET)

Definition at line 2264 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: APB2 Peripheral Clock Sleep Enabled or Disabled Status

Defines
APB2 Peripheral Clock Sleep Enabled or Disabled Status
RCC Exported Macros

Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not. More...

Defines

#define | __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != RESET)
#define | __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != RESET)
#define | __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != RESET)
#define | __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != RESET)
#define | __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != RESET)
#define | __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != RESET)
#define | __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == RESET)
#define | __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == RESET)
#define | __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == RESET)
#define | __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == RESET)
#define | __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == RESET)
#define | __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == RESET)
#define | __HAL_RCC_C2TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM1SMEN) != RESET)
#define | __HAL_RCC_C2SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SPI1SMEN) != RESET)
#define | __HAL_RCC_C2USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_USART1SMEN) != RESET)
#define | __HAL_RCC_C2TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM16SMEN) != RESET)
#define | __HAL_RCC_C2TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM17SMEN) != RESET)
#define | __HAL_RCC_C2SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SAI1SMEN) != RESET)
#define | __HAL_RCC_C2TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM1SMEN) == RESET)
#define | __HAL_RCC_C2SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SPI1SMEN) == RESET)
#define | __HAL_RCC_C2USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_USART1SMEN) == RESET)
#define | __HAL_RCC_C2TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM16SMEN) == RESET)
#define | __HAL_RCC_C2TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM17SMEN) == RESET)
#define | __HAL_RCC_C2SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SAI1SMEN) == RESET)

Detailed Description

Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_C2SAI1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SAI1SMEN) == RESET)

Definition at line 2401 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2SAI1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SAI1SMEN) != RESET)

Definition at line 2392 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2SPI1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SPI1SMEN) == RESET)

Definition at line 2396 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2SPI1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SPI1SMEN) != RESET)

Definition at line 2387 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TIM16_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM16SMEN) == RESET)

Definition at line 2398 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TIM16_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM16SMEN) != RESET)

Definition at line 2389 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TIM17_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM17SMEN) == RESET)

Definition at line 2399 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TIM17_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM17SMEN) != RESET)

Definition at line 2390 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TIM1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM1SMEN) == RESET)

Definition at line 2395 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2TIM1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM1SMEN) != RESET)

Definition at line 2386 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2USART1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_USART1SMEN) == RESET)

Definition at line 2397 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2USART1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_USART1SMEN) != RESET)

Definition at line 2388 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == RESET)

Definition at line 2383 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != RESET)

Definition at line 2374 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == RESET)

Definition at line 2378 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != RESET)

Definition at line 2369 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == RESET)

Definition at line 2380 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != RESET)

Definition at line 2371 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == RESET)

Definition at line 2381 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != RESET)

Definition at line 2372 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == RESET)

Definition at line 2377 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != RESET)

Definition at line 2368 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == RESET)

Definition at line 2379 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != RESET)

Definition at line 2370 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: APB3 Peripheral Clock Sleep Enable Disable

Defines
APB3 Peripheral Clock Sleep Enable Disable
RCC Exported Macros

Enable or disable the APB3 peripheral clock during Low Power (Sleep) mode. More...

Defines

#define | __HAL_RCC_C2BLE_CLK_SLEEP_ENABLE() LL_C2_APB3_GRP1_EnableClockSleep(LL_C2_APB3_GRP1_PERIPH_BLE)
#define | __HAL_RCC_C2802_CLK_SLEEP_ENABLE() LL_C2_APB3_GRP1_EnableClockSleep(LL_C2_APB3_GRP1_PERIPH_802)
#define | __HAL_RCC_C2BLE_CLK_SLEEP_DISABLE() LL_C2_APB3_GRP1_DisableClockSleep(LL_C2_APB3_GRP1_PERIPH_BLE)
#define | __HAL_RCC_C2802_CLK_SLEEP_DISABLE() LL_C2_APB3_GRP1_DisableClockSleep(LL_C2_APB3_GRP1_PERIPH_802)

Detailed Description

Enable or disable the APB3 peripheral clock during Low Power (Sleep) mode.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_C2802_CLK_SLEEP_DISABLE ( ) LL_C2_APB3_GRP1_DisableClockSleep(LL_C2_APB3_GRP1_PERIPH_802)

Definition at line 2419 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2802_CLK_SLEEP_ENABLE ( ) LL_C2_APB3_GRP1_EnableClockSleep(LL_C2_APB3_GRP1_PERIPH_802)

Definition at line 2416 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2BLE_CLK_SLEEP_DISABLE ( ) LL_C2_APB3_GRP1_DisableClockSleep(LL_C2_APB3_GRP1_PERIPH_BLE)

Definition at line 2418 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2BLE_CLK_SLEEP_ENABLE ( ) LL_C2_APB3_GRP1_EnableClockSleep(LL_C2_APB3_GRP1_PERIPH_BLE)

Definition at line 2415 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: APB3 Peripheral Clock Sleep Enabled or Disabled Status

Defines
APB3 Peripheral Clock Sleep Enabled or Disabled Status
RCC Exported Macros

Check whether the APB3 peripheral clock during Low Power (Sleep) mode is enabled or not. More...

Defines

#define | __HAL_RCC_C2BLE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_BLESMEN) != RESET)
#define | __HAL_RCC_C2802_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_802SMEN) != RESET)
#define | __HAL_RCC_C2BLE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_BLESMEN) == RESET)
#define | __HAL_RCC_C2802_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_802SMEN) == RESET)

Detailed Description

Check whether the APB3 peripheral clock during Low Power (Sleep) mode is enabled or not.

Note:
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.

Define Documentation

#define __HAL_RCC_C2802_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_802SMEN) == RESET)

Definition at line 2436 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2802_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_802SMEN) != RESET)

Definition at line 2433 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2BLE_IS_CLK_SLEEP_DISABLED ( ) (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_BLESMEN) == RESET)

Definition at line 2435 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_C2BLE_IS_CLK_SLEEP_ENABLED ( ) (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_BLESMEN) != RESET)

Definition at line 2432 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RCC Backup Domain Reset

Defines
RCC Backup Domain Reset
RCC Exported Macros

Defines

#define | __HAL_RCC_BACKUPRESET_FORCE() LL_RCC_ForceBackupDomainReset()
Macros to force or release the Backup domain reset.
#define | __HAL_RCC_BACKUPRESET_RELEASE() LL_RCC_ReleaseBackupDomainReset()

Define Documentation

#define __HAL_RCC_BACKUPRESET_FORCE ( ) LL_RCC_ForceBackupDomainReset()

Macros to force or release the Backup domain reset.

Note:
This function resets the RTC peripheral (including the backup registers) and the RTC clock source selection in RCC_CSR register.
The BKPSRAM is not affected by this reset.
Return values:
None

Definition at line 2451 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_BACKUPRESET_RELEASE ( ) LL_RCC_ReleaseBackupDomainReset()

Definition at line 2452 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RCC RTC Clock Configuration

Defines
RCC RTC Clock Configuration
RCC Exported Macros

Defines

#define | __HAL_RCC_RTC_ENABLE() LL_RCC_EnableRTC()
Macros to enable or disable the RTC clock.
#define | __HAL_RCC_RTC_DISABLE() LL_RCC_DisableRTC()

Define Documentation

#define __HAL_RCC_RTC_DISABLE ( ) LL_RCC_DisableRTC()

Definition at line 2471 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_RTC_ENABLE ( ) LL_RCC_EnableRTC()

Macros to enable or disable the RTC clock.

Note:
As the RTC is in the Backup domain and write access is denied to this domain after reset, you have to enable write access using HAL_PWR_EnableBkUpAccess() function before to configure the RTC (to be done once after reset).
These macros must be used after the RTC clock source was selected.
Return values:
None

Definition at line 2470 of file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Flags Interrupts Management

Defines
Flags Interrupts Management
RCC Exported Macros

macros to manage the specified RCC Flags and interrupts. More...

Defines

#define | __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
Enable RCC interrupt.
#define | __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
Disable RCC interrupt.
#define | __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
Clear RCC interrupt pending bits (Perform Byte access to RCC_CICR[17:0] bits to clear the selected interrupt pending bits.
#define | __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the RCC interrupt has occurred or not.
#define | __HAL_RCC_CLEAR_RESET_FLAGS() LL_RCC_ClearResetFlags()
Set RMVF bit to clear the reset flags.
#define | __HAL_RCC_GET_FLAG(__FLAG__)
Check whether the selected RCC flag is set or not.

Detailed Description

macros to manage the specified RCC Flags and interrupts.

Define Documentation

#define __HAL_RCC_CLEAR_IT ( __INTERRUPT__ ) (RCC->CICR = (__INTERRUPT__))

Clear RCC interrupt pending bits (Perform Byte access to RCC_CICR[17:0] bits to clear the selected interrupt pending bits.

Parameters:
__INTERRUPT__ specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:
  • RCC_IT_LSI1RDY LSI1 ready interrupt clear
  • RCC_IT_LSERDY LSE ready interrupt clear
  • RCC_IT_MSIRDY HSI ready interrupt clear
  • RCC_IT_HSIRDY HSI ready interrupt clear
  • RCC_IT_HSERDY HSE ready interrupt clear
  • RCC_IT_PLLRDY Main PLL ready interrupt clear
  • RCC_IT_PLLRDY PLLSAI1 ready interrupt clear
  • RCC_IT_HSECSS HSE Clock security system interrupt clear
  • RCC_IT_LSECSS LSE Clock security system interrupt clear
  • RCC_IT_HSI48RDY PLLHSI48 ready interrupt clear
  • RCC_IT_LSI2RDY LSI2 ready interrupt clear

Definition at line 3072 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_NMI_IRQHandler(), and HAL_RCCEx_LSECSS_IRQHandler().

#define __HAL_RCC_CLEAR_RESET_FLAGS ( ) LL_RCC_ClearResetFlags()

Set RMVF bit to clear the reset flags.

The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.

Return values:
None

Definition at line 3097 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_DISABLE_IT ( __INTERRUPT__ ) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))

Disable RCC interrupt.

Parameters:
__INTERRUPT__ specifies the RCC interrupt sources to be disabled. This parameter can be any combination of the following values:
  • RCC_IT_LSI1RDY LSI1 ready interrupt enable
  • RCC_IT_LSERDY LSE ready interrupt enable
  • RCC_IT_MSIRDY HSI ready interrupt enable
  • RCC_IT_HSIRDY HSI ready interrupt enable
  • RCC_IT_HSERDY HSE ready interrupt enable
  • RCC_IT_PLLRDY Main PLL ready interrupt enable
  • RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt enable
  • RCC_IT_LSECSS LSE Clock security system interrupt enable
  • RCC_IT_HSI48RDY PLLHSI48 ready interrupt enable
  • RCC_IT_LSI2RDY LSI2 ready interrupt enable
Return values:
None

Definition at line 3054 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCCEx_DisableLSECSS().

#define __HAL_RCC_ENABLE_IT ( __INTERRUPT__ ) SET_BIT(RCC->CIER, (__INTERRUPT__))

Enable RCC interrupt.

Parameters:
__INTERRUPT__ specifies the RCC interrupt sources to be enabled. This parameter can be any combination of the following values:
  • RCC_IT_LSI1RDY LSI1 ready interrupt enable
  • RCC_IT_LSERDY LSE ready interrupt enable
  • RCC_IT_MSIRDY HSI ready interrupt enable
  • RCC_IT_HSIRDY HSI ready interrupt enable
  • RCC_IT_HSERDY HSE ready interrupt enable
  • RCC_IT_PLLRDY Main PLL ready interrupt enable
  • RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt enable
  • RCC_IT_LSECSS LSE Clock security system interrupt enable
  • RCC_IT_HSI48RDY PLLHSI48 ready interrupt enable
  • RCC_IT_LSI2RDY LSI2 ready interrupt enable
Return values:
None

Definition at line 3037 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCCEx_EnableLSECSS_IT().

#define __HAL_RCC_GET_FLAG ( __FLAG__ )
Value:
(((((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR :                     \
                                        ((((__FLAG__) >> 5U) == CRRCR_REG_INDEX) ? RCC->CRRCR :                  \
                                        ((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR :                   \
                                        ((((__FLAG__) >> 5U) == CSR_REG_INDEX) ? RCC->CSR : RCC->CIFR)))) &    \
                                        (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) \
                                         ? 1U : 0U)

Check whether the selected RCC flag is set or not.

Parameters:
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • RCC_FLAG_MSIRDY MSI oscillator clock ready
  • RCC_FLAG_HSIRDY HSI oscillator clock ready
  • RCC_FLAG_HSERDY HSE oscillator clock ready
  • RCC_FLAG_PLLRDY Main PLL clock ready
  • RCC_FLAG_PLLRDY PLLSAI1 clock ready
  • RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48
  • RCC_FLAG_LSERDY LSE oscillator clock ready
  • RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection
  • RCC_FLAG_LSI1RDY LSI1 oscillator clock ready
  • RCC_FLAG_LSI2RDY LSI2 oscillator clock ready
  • RCC_FLAG_BORRST BOR reset
  • RCC_FLAG_OBLRST OBLRST reset
  • RCC_FLAG_PINRST Pin reset
  • RCC_FLAG_SFTRST Software reset
  • RCC_FLAG_IWDGRST Independent Watchdog reset
  • RCC_FLAG_WWDGRST Window Watchdog reset
  • RCC_FLAG_LPWRRST Low Power reset
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 3121 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GET_IT ( __INTERRUPT__ ) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))

Check whether the RCC interrupt has occurred or not.

Parameters:
__INTERRUPT__ specifies the RCC interrupt source to check. This parameter can be one of the following values:
  • RCC_IT_LSI1RDY LSI1 ready interrupt flag
  • RCC_IT_LSERDY LSE ready interrupt flag
  • RCC_IT_MSIRDY HSI ready interrupt flag
  • RCC_IT_HSIRDY HSI ready interrupt flag
  • RCC_IT_HSERDY HSE ready interrupt flag
  • RCC_IT_PLLRDY Main PLL ready interrupt flag
  • RCC_IT_PLLRDY PLLSAI1 ready interrupt flag
  • RCC_IT_HSECSS HSE Clock security system interrupt flag
  • RCC_IT_LSECSS LSE Clock security system interrupt flag
  • RCC_IT_HSI48RDY PLLHSI48 ready interrupt flag
  • RCC_IT_LSI2RDY LSI2 ready interrupt flag
Return values:
The new state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 3090 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_NMI_IRQHandler(), and HAL_RCCEx_LSECSS_IRQHandler().

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RCC Exported Macros

Modules | Defines
RCC Exported Macros
RCC

Modules

AHB1 Peripheral Clock Enable Disable

Enable or disable the AHB1 peripheral clock.

AHB2 Peripheral Clock Enable Disable

Enable or disable the AHB2 peripheral clock.

AHB3 Peripheral Clock Enable Disable

Enable or disable the AHB3 peripheral clock.

APB1 Peripheral Clock Enable Disable

Enable or disable the APB1 peripheral clock.

APB2 Peripheral Clock Enable Disable

Enable or disable the APB2 peripheral clock.

AHB1 Peripheral Clock Enabled or Disabled Status

Check whether the AHB1 peripheral clock is enabled or not.

AHB2 Peripheral Clock Enabled or Disabled Status

Check whether the AHB2 peripheral clock is enabled or not.

AHB3 Peripheral Clock Enabled or Disabled Status

Check whether the AHB3 peripheral clock is enabled or not.

APB1 Peripheral Clock Enabled or Disabled Status

Check whether the APB1 peripheral clock is enabled or not.

APB2 Peripheral Clock Enabled or Disabled Status

Check whether the APB2 peripheral clock is enabled or not.

APB3 Peripheral Clock Enable Disable

Enable or disable the APB3 peripheral clock.

APB3 Peripheral Clock Enabled or Disabled Status

Check whether the APB3 peripheral clock is enabled or not.

AHB1 Peripheral Force Release Reset

Force or release AHB1 peripheral reset.

AHB2 Peripheral Force Release Reset

Force or release AHB2 peripheral reset.

AHB3 Peripheral Force Release Reset

Force or release AHB3 peripheral reset.

APB1 Peripheral Force Release Reset

Force or release APB1 peripheral reset.

APB2 Peripheral Force Release Reset

Force or release APB2 peripheral reset.

APB3 Peripheral Force Release Reset

Force or release APB3 peripheral reset.

AHB1 Peripheral Clock Sleep Enable Disable

Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.

AHB2 Peripheral Clock Sleep Enable Disable

Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.

AHB3 Peripheral Clock Sleep Enable Disable

Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.

APB1 Peripheral Clock Sleep Enable Disable

Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.

APB2 Peripheral Clock Sleep Enable Disable

Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.

AHB1 Peripheral Clock Sleep Enabled or Disabled Status

Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not.

AHB2 Peripheral Clock Sleep Enabled or Disabled Status

Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not.

AHB3 Peripheral Clock Sleep Enabled or Disabled Status

Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not.

APB1 Peripheral Clock Sleep Enabled or Disabled Status

Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.

APB2 Peripheral Clock Sleep Enabled or Disabled Status

Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.

APB3 Peripheral Clock Sleep Enable Disable

Enable or disable the APB3 peripheral clock during Low Power (Sleep) mode.

APB3 Peripheral Clock Sleep Enabled or Disabled Status

Check whether the APB3 peripheral clock during Low Power (Sleep) mode is enabled or not.

RCC Backup Domain Reset
RCC RTC Clock Configuration
Flags Interrupts Management

macros to manage the specified RCC Flags and interrupts.

Defines

#define | __HAL_RCC_HSI_ENABLE() LL_RCC_HSI_Enable()
Macros to enable the Internal High Speed oscillator (HSI).
#define | __HAL_RCC_HSI_DISABLE() LL_RCC_HSI_Disable()
Macro to disable the Internal High Speed oscillator (HSI).
#define | __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) LL_RCC_HSI_SetCalibTrimming(__HSICALIBRATIONVALUE__)
Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
#define | __HAL_RCC_HSIAUTOMATIC_START_ENABLE() LL_RCC_HSI_EnableAutoFromStop()
Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI) in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup.
#define | __HAL_RCC_HSIAUTOMATIC_START_DISABLE() LL_RCC_HSI_DisableAutoFromStop()
#define | __HAL_RCC_HSISTOP_ENABLE() LL_RCC_HSI_EnableInStopMode()
Macros to enable or disable the force of the Internal High Speed oscillator (HSI) in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
#define | __HAL_RCC_HSISTOP_DISABLE() LL_RCC_HSI_DisableInStopMode()
#define | __HAL_RCC_MSI_ENABLE() LL_RCC_MSI_Enable()
Macros to enable or disable the Internal Multi Speed oscillator (MSI).
#define | __HAL_RCC_MSI_DISABLE() LL_RCC_MSI_Disable()
#define | __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) LL_RCC_MSI_SetCalibTrimming(__MSICALIBRATIONVALUE__)
Macro to adjust the Internal Multi Speed oscillator (MSI) calibration value.
#define | __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) LL_RCC_MSI_SetRange(__MSIRANGEVALUE__)
Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode.
#define | __HAL_RCC_GET_MSI_RANGE() LL_RCC_MSI_GetRange()
Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode.
#define | __HAL_RCC_LSI1_ENABLE() LL_RCC_LSI1_Enable()
Macros to enable or disable the Internal Low Speed oscillator (LSI1).
#define | __HAL_RCC_LSI1_DISABLE() LL_RCC_LSI1_Disable()
#define | __HAL_RCC_LSI2_ENABLE() LL_RCC_LSI2_Enable()
Macros to enable or disable the Internal Low Speed oscillator (LSI2).
#define | __HAL_RCC_LSI2_DISABLE() LL_RCC_LSI2_Disable()
#define | __HAL_RCC_LSI2_CALIBRATIONVALUE_ADJUST(__LSI2TRIMMINGVALUE__) LL_RCC_LSI2_SetTrimming(__LSI2TRIMMINGVALUE__)
Macro to adjust the Internal Low Speed oscillator (LSI2) calibration value.
#define | __HAL_RCC_HSE_CONFIG(__STATE__)
Macro to configure the External High Speed oscillator (HSE).
#define | __HAL_RCC_HSE_DIV2_ENABLE() LL_RCC_HSE_EnableDiv2()
Macros to enable or disable the HSE Prescaler.
#define | __HAL_RCC_HSE_DIV2_DISABLE() LL_RCC_HSE_DisableDiv2()
#define | __HAL_RCC_LSE_CONFIG(__STATE__)
Macro to configure the External Low Speed oscillator (LSE).
#define | __HAL_RCC_HSI48_ENABLE() LL_RCC_HSI48_Enable()
Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48).
#define | __HAL_RCC_HSI48_DISABLE() LL_RCC_HSI48_Disable()
#define | __HAL_RCC_HSE_AMPCONFIG(__HSE_AMPTHRES__) LL_RCC_HSE_SetSenseAmplifier(__HSE_AMPTHRES__)
Macros to configure HSE sense amplifier threshold.
#define | __HAL_RCC_HSE_CURRENTCONFIG(__HSE_CURRENTMAX__) LL_RCC_HSE_SetCurrentControl(__HSE_CURRENTMAX__)
Macros to configure HSE current control.
#define | __HAL_RCC_HSE_CAPACITORTUNING(__HSE_LOAD_CAPACITANCE__) LL_RCC_HSE_SetCapacitorTuning(__HSE_LOAD_CAPACITANCE__)
Macros to configure HSE capacitor tuning.
#define | __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) LL_RCC_SetRTCClockSource(__RTC_CLKSOURCE__)
Macros to configure the RTC clock (RTCCLK).
#define | __HAL_RCC_GET_RTC_SOURCE() LL_RCC_GetRTCClockSource()
Macro to get the RTC clock source.
#define | __HAL_RCC_PLL_ENABLE() LL_RCC_PLL_Enable()
Macros to enable or disable the main PLL.
#define | __HAL_RCC_PLL_DISABLE() LL_RCC_PLL_Disable()
#define | __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
Macro to configure the PLL clock source.
#define | __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
Macro to configure the PLL multiplication factor.
#define | __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__, __PLLR__)
Macro to configure the main PLL clock source, multiplication and division factors.
#define | __HAL_RCC_GET_PLL_OSCSOURCE() LL_RCC_PLL_GetMainSource()
Macro to get the oscillator used as PLL clock source.
#define | __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_USBCLK, RCC_PLL_SAI1CLK)
#define | __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
#define | __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_USBCLK, RCC_PLL_SAI1CLK)
#define | __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) LL_RCC_SetSysClkSource(__SYSCLKSOURCE__)
Macro to configure the system clock source.
#define | __HAL_RCC_GET_SYSCLK_SOURCE() LL_RCC_GetSysClkSource()
Macro to get the clock source used as system clock.
#define | __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) LL_RCC_LSE_SetDriveCapability(__LSEDRIVE__)
Macro to configure the External Low Speed oscillator (LSE) drive capability.
#define | __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) LL_RCC_SetClkAfterWakeFromStop(__STOPWUCLK__)
Macro to configure the wake up from stop clock.
#define | __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) LL_RCC_ConfigMCO((__MCOCLKSOURCE__), (__MCODIV__))
Macro to configure the MCO clock.

Define Documentation

#define __HAL_RCC_GET_MSI_RANGE ( ) LL_RCC_MSI_GetRange()

Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode.

Return values:
MSI clock range. This parameter must be one of the following values:
  • RCC_MSIRANGE_0 MSI clock is around 100 KHz
  • RCC_MSIRANGE_1 MSI clock is around 200 KHz
  • RCC_MSIRANGE_2 MSI clock is around 400 KHz
  • RCC_MSIRANGE_3 MSI clock is around 800 KHz
  • RCC_MSIRANGE_4 MSI clock is around 1 MHz
  • RCC_MSIRANGE_5 MSI clock is around 2 MHz
  • RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset)
  • RCC_MSIRANGE_7 MSI clock is around 8 MHz
  • RCC_MSIRANGE_8 MSI clock is around 16 MHz
  • RCC_MSIRANGE_9 MSI clock is around 24 MHz
  • RCC_MSIRANGE_10 MSI clock is around 32 MHz
  • RCC_MSIRANGE_11 MSI clock is around 48 MHz

Definition at line 2606 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_GET_PLL_OSCSOURCE ( ) LL_RCC_PLL_GetMainSource()

Macro to get the oscillator used as PLL clock source.

Return values:
The oscillator used as PLL clock source. The returned value can be one of the following:
  • RCC_PLLSOURCE_NONE No oscillator is used as PLL clock source.
  • RCC_PLLSOURCE_MSI MSI oscillator is used as PLL clock source.
  • RCC_PLLSOURCE_HSI HSI oscillator is used as PLL clock source.
  • RCC_PLLSOURCE_HSE HSE oscillator is used as PLL clock source.

Definition at line 2910 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_GET_PLLCLKOUT_CONFIG ( __PLLCLOCKOUT__ ) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))

Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_USBCLK, RCC_PLL_SAI1CLK)

Parameters:
__PLLCLOCKOUT__ specifies the output PLL clock to be checked. This parameter can be one of the following values:
  • RCC_PLL_SAI1CLK This clock is used to generate an accurate clock to achieve high-quality audio performance on SAI interface
  • RCC_PLL_ADCCLK same
  • RCC_PLL_USBCLK This Clock is used to generate the clock for the USB FS (48 MHz)
  • RCC_PLL_RNGCLK same
  • RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 64MHz)
Return values:
SET / RESET

Definition at line 2941 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_GET_RTC_SOURCE ( ) LL_RCC_GetRTCClockSource()

Macro to get the RTC clock source.

Return values:
The returned value can be one of the following:
  • RCC_RTCCLKSOURCE_NONE none clock selected as RTC clock.
  • RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
  • RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
  • RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected

Definition at line 2808 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_SYSCLK_SOURCE ( ) LL_RCC_GetSysClkSource()

Macro to get the clock source used as system clock.

Return values:
The clock source used as system clock. The returned value can be one of the following:
  • RCC_SYSCLKSOURCE_STATUS_MSI MSI used as system clock.
  • RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock.
  • RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock.
  • RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock.

Definition at line 2963 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), HAL_RCC_GetSysClockFreq(), and HAL_RCC_OscConfig().

#define __HAL_RCC_HSE_AMPCONFIG ( __HSE_AMPTHRES__ ) LL_RCC_HSE_SetSenseAmplifier(__HSE_AMPTHRES__)

Macros to configure HSE sense amplifier threshold.

Note:
to configure HSE sense amplifier, first disable HSE using __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF) macro.
Parameters:
__HSE_AMPTHRES__ specifies the HSE sense amplifier threshold. This parameter can be one of the following values:
  • RCC_HSEAMPTHRESHOLD_1_2 HSE bias current factor 1/2.
  • RCC_HSEAMPTHRESHOLD_3_4 HSE bias current factor 3/4.
Return values:
None

Definition at line 2743 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_HSE_CAPACITORTUNING ( __HSE_LOAD_CAPACITANCE__ ) LL_RCC_HSE_SetCapacitorTuning(__HSE_LOAD_CAPACITANCE__)

Macros to configure HSE capacitor tuning.

Note:
to configure HSE current control, first disable HSE using __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF) macro.
Parameters:
__HSE_LOAD_CAPACITANCE__ specifies the HSE capacitor value. This Value Between Min_Data = 0 and Max_Data = 63
Return values:
None

Definition at line 2771 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_HSE_CONFIG ( __STATE__ )
Value:
do {                                     \
                      if((__STATE__) == RCC_HSE_ON)          \
                      {                                      \
                       LL_RCC_HSE_Enable();                  \
                      }                                      \
                      else if((__STATE__) == RCC_HSE_BYPASS) \
                      {                                      \
                        LL_RCC_HSE_EnableBypass();           \
                        LL_RCC_HSE_Enable();                 \
                      }                                      \
                      else                                   \
                      {                                      \
                        LL_RCC_HSE_Disable();                \
                        LL_RCC_HSE_DisableBypass();          \
                      }                                      \
                    } while(0U)

Macro to configure the External High Speed oscillator (HSE).

Note:
Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro. User should request a transition to HSE Off first and then HSE On or HSE Bypass.
After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application software should wait on HSERDY flag to be set indicating that HSE clock is stable and can be used to clock the PLL and/or system clock.
HSE state can not be changed if it is used directly or through the PLL as system clock. In this case, you have to select another source of the system clock then change the HSE state (ex. disable it).
The HSE is stopped by hardware when entering STOP and STANDBY modes.
This function reset the CSSON bit, so if the clock security system(CSS) was previously enabled you have to enable it again after calling this function.
Parameters:
__STATE__ specifies the new state of the HSE. This parameter can be one of the following values:
  • RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after 6 HSE oscillator clock cycles.
  • RCC_HSE_ON Turn ON the HSE oscillator.
  • RCC_HSE_BYPASS HSE oscillator bypassed with external clock.
Return values:
None

Definition at line 2659 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSE_CURRENTCONFIG ( __HSE_CURRENTMAX__ ) LL_RCC_HSE_SetCurrentControl(__HSE_CURRENTMAX__)

Macros to configure HSE current control.

Note:
to configure HSE current control, first disable HSE using __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF) macro.
Parameters:
__HSE_CURRENTMAX__ specifies the HSE current max limit. This parameter can be one of the following values:
  • RCC_HSE_CURRENTMAX_0 HSE current max limit 0.18 mA/V.
  • RCC_HSE_CURRENTMAX_1 HSE current max limit 0.57 mA/V.
  • RCC_HSE_CURRENTMAX_2 HSE current max limit 0.78 mA/V.
  • RCC_HSE_CURRENTMAX_3 HSE current max limit 1.13 mA/V.
  • RCC_HSE_CURRENTMAX_4 HSE current max limit 0.61 mA/V.
  • RCC_HSE_CURRENTMAX_5 HSE current max limit 1.65 mA/V.
  • RCC_HSE_CURRENTMAX_6 HSE current max limit 2.12 mA/V.
  • RCC_HSE_CURRENTMAX_7 HSE current max limit 2.84 mA/V.
Return values:
None

Definition at line 2761 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_HSE_DIV2_DISABLE ( ) LL_RCC_HSE_DisableDiv2()

Definition at line 2682 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_HSE_DIV2_ENABLE ( ) LL_RCC_HSE_EnableDiv2()

Macros to enable or disable the HSE Prescaler.

Note:
HSE div2 could be used as Sysclk or PLL entry in Range2
Return values:
None

Definition at line 2681 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_HSI48_DISABLE ( ) LL_RCC_HSI48_Disable()

Definition at line 2731 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI48_ENABLE ( ) LL_RCC_HSI48_Enable()

Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48).

Note:
The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
After enabling the HSI48, the application software should wait on HSI48RDY flag to be set indicating that HSI48 clock is stable. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 2730 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST ( __HSICALIBRATIONVALUE__ ) LL_RCC_HSI_SetCalibTrimming(__HSICALIBRATIONVALUE__)

Macro to adjust the Internal High Speed oscillator (HSI) calibration value.

Note:
The calibration is used to compensate for the variations in voltage and temperature that influence the frequency of the internal HSI RC.
Parameters:
__HSICALIBRATIONVALUE__ specifies the calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). This parameter must be a number between Min_data=0 and Max_Data=127.
Return values:
None

Definition at line 2506 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI_DISABLE ( ) LL_RCC_HSI_Disable()

Macro to disable the Internal High Speed oscillator (HSI).

Note:
HSI can not be stopped if it is used as system clock source. In this case, you have to select another source of the system clock then stop the HSI.
When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator clock cycles.
Return values:
None

Definition at line 2496 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI_ENABLE ( ) LL_RCC_HSI_Enable()

Macros to enable the Internal High Speed oscillator (HSI).

Note:
The HSI is stopped by hardware when entering STOP, STANDBY or SHUTDOWN modes. It is enabled by hardware to force the HSI oscillator ON when STOPWUCK=1 or HSIASFS = 1 when leaving Stop modes, or in case of failure of the HSE crystal oscillator and Security System CSS is enabled.
After enabling the HSI, the application software should wait on HSIRDY flag to be set indicating that HSI clock is stable and can be used as system clock source.
Return values:
None

Definition at line 2487 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSIAUTOMATIC_START_DISABLE ( ) LL_RCC_HSI_DisableAutoFromStop()

Definition at line 2516 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_HSIAUTOMATIC_START_ENABLE ( ) LL_RCC_HSI_EnableAutoFromStop()

Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI) in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup.

Note:
The enable of this function has not effect on the HSION bit. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 2515 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_HSISTOP_DISABLE ( ) LL_RCC_HSI_DisableInStopMode()

Definition at line 2527 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_HSISTOP_ENABLE ( ) LL_RCC_HSI_EnableInStopMode()

Macros to enable or disable the force of the Internal High Speed oscillator (HSI) in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.

Note:
Keeping the HSI ON in STOP mode allows to avoid slowing down the communication speed because of the HSI startup time.
The enable of this function has not effect on the HSION bit.
Return values:
None

Definition at line 2526 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_LSE_CONFIG ( __STATE__ )
Value:
do {                                       \
                      if((__STATE__) == RCC_LSE_ON)            \
                      {                                        \
                        LL_RCC_LSE_Enable();                   \
                      }                                        \
                      else if((__STATE__) == RCC_LSE_BYPASS)   \
                      {                                        \
                        LL_RCC_LSE_EnableBypass();             \
                        LL_RCC_LSE_Enable();                   \
                      }                                        \
                      else                                     \
                      {                                        \
                        LL_RCC_LSE_Disable();                  \
                        LL_RCC_LSE_DisableBypass();            \
                      }                                        \
                    } while(0U)

Macro to configure the External Low Speed oscillator (LSE).

Note:
Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. User should request a transition to LSE Off first and then LSE On or LSE Bypass.
As the LSE is in the Backup domain and write access is denied to this domain after reset, you have to enable write access using HAL_PWR_EnableBkUpAccess() function before to configure the LSE (to be done once after reset).
After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application software should wait on LSERDY flag to be set indicating that LSE clock is stable and can be used to clock the RTC.
Parameters:
__STATE__ specifies the new state of the LSE. This parameter can be one of the following values:
  • RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after 6 LSE oscillator clock cycles.
  • RCC_LSE_ON Turn ON the LSE oscillator.
  • RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
Return values:
None

Definition at line 2704 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_LSEDRIVE_CONFIG ( __LSEDRIVE__ ) LL_RCC_LSE_SetDriveCapability(__LSEDRIVE__)

Macro to configure the External Low Speed oscillator (LSE) drive capability.

Note:
As the LSE is in the Backup domain and write access is denied to this domain after reset, you have to enable write access using HAL_PWR_EnableBkUpAccess() function before to configure the LSE (to be done once after reset).
Parameters:
__LSEDRIVE__ specifies the new state of the LSE drive capability. This parameter can be one of the following values:
  • RCC_LSEDRIVE_LOW LSE oscillator low drive capability.
  • RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability.
  • RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability.
  • RCC_LSEDRIVE_HIGH LSE oscillator high drive capability.
Return values:
None

Definition at line 2979 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_LSI1_DISABLE ( ) LL_RCC_LSI1_Disable()

Definition at line 2616 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_LSI1_ENABLE ( ) LL_RCC_LSI1_Enable()

Macros to enable or disable the Internal Low Speed oscillator (LSI1).

Note:
After enabling the LSI1, the application software should wait on LSI1RDY flag to be set indicating that LSI1 clock is stable and can be used to clock the IWDG and/or the RTC.
Return values:
None

Definition at line 2615 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_LSI2_CALIBRATIONVALUE_ADJUST ( __LSI2TRIMMINGVALUE__ ) LL_RCC_LSI2_SetTrimming(__LSI2TRIMMINGVALUE__)

Macro to adjust the Internal Low Speed oscillator (LSI2) calibration value.

Note:
The calibration is used to compensate for the variations in voltage and temperature that influence the frequency of the internal HSI RC.
Parameters:
__LSI2TRIMMINGVALUE__ specifies the calibration trimming value This parameter must be a number between Min_data=0 and Max_Data=15.
Return values:
None

Definition at line 2634 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_LSI2_DISABLE ( ) LL_RCC_LSI2_Disable()

Definition at line 2625 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_LSI2_ENABLE ( ) LL_RCC_LSI2_Enable()

Macros to enable or disable the Internal Low Speed oscillator (LSI2).

Note:
After enabling the LSI2, the application software should wait on LSI2RDY flag to be set indicating that LSI2 clock is stable and can be used to clock the IWDG and/or the RTC.
Return values:
None

Definition at line 2624 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_MCO1_CONFIG | ( | __MCOCLKSOURCE__,
 |  | __MCODIV__
 | ) | LL_RCC_ConfigMCO((__MCOCLKSOURCE__), (__MCODIV__))

Macro to configure the MCO clock.

Parameters:
__MCOCLKSOURCE__ specifies the MCO clock source. This parameter can be one of the following values:
  • RCC_MCO1SOURCE_NOCLOCK MCO output disabled
  • RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source
  • RCC_MCO1SOURCE_MSI MSI clock selected as MCO source
  • RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
  • RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee
  • RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source
  • RCC_MCO1SOURCE_LSI1 LSI1 clock selected as MCO source
  • RCC_MCO1SOURCE_LSI2 LSI2 clock selected as MCO source
  • RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
  • RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source
__MCODIV__ specifies the MCO clock prescaler. This parameter can be one of the following values:
  • RCC_MCODIV_1 MCO clock source is divided by 1
  • RCC_MCODIV_2 MCO clock source is divided by 2
  • RCC_MCODIV_4 MCO clock source is divided by 4
  • RCC_MCODIV_8 MCO clock source is divided by 8
  • RCC_MCODIV_16 MCO clock source is divided by 16

Definition at line 3014 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST ( __MSICALIBRATIONVALUE__ ) LL_RCC_MSI_SetCalibTrimming(__MSICALIBRATIONVALUE__)

Macro to adjust the Internal Multi Speed oscillator (MSI) calibration value.

Note:
The calibration is used to compensate for the variations in voltage and temperature that influence the frequency of the internal MSI RC. Refer to the Application Note AN3300 for more details on how to calibrate the MSI.
Parameters:
__MSICALIBRATIONVALUE__ specifies the calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT). This parameter must be a number between 0 and 255.
Return values:
None

Definition at line 2559 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_MSI_DISABLE ( ) LL_RCC_MSI_Disable()

Definition at line 2547 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_MSI_ENABLE ( ) LL_RCC_MSI_Enable()

Macros to enable or disable the Internal Multi Speed oscillator (MSI).

Note:
The MSI is stopped by hardware when entering STOP and STANDBY modes. It is used (enabled by hardware) as system clock source after startup from Reset, wakeup from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
MSI can not be stopped if it is used as system clock source. In this case, you have to select another source of the system clock then stop the MSI.
After enabling the MSI, the application software should wait on MSIRDY flag to be set indicating that MSI clock is stable and can be used as system clock source.
When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator clock cycles.
Return values:
None

Definition at line 2546 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_MSI_RANGE_CONFIG ( __MSIRANGEVALUE__ ) LL_RCC_MSI_SetRange(__MSIRANGEVALUE__)

Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode.

Note:
After restart from Reset , the MSI clock is around 4 MHz. After stop the startup clock can be MSI (at any of its possible frequencies, the one that was used before entering stop mode) or HSI. After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz).
MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready (MSIRDY=1).
The MSI clock range after reset can be modified on the fly.
Parameters:
__MSIRANGEVALUE__ specifies the MSI clock range. This parameter must be one of the following values:
  • RCC_MSIRANGE_0 MSI clock is around 100 KHz
  • RCC_MSIRANGE_1 MSI clock is around 200 KHz
  • RCC_MSIRANGE_2 MSI clock is around 400 KHz
  • RCC_MSIRANGE_3 MSI clock is around 800 KHz
  • RCC_MSIRANGE_4 MSI clock is around 1 MHz
  • RCC_MSIRANGE_5 MSI clock is around 2MHz
  • RCC_MSIRANGE_6 MSI clock is around 4MHz (default after Reset)
  • RCC_MSIRANGE_7 MSI clock is around 8 MHz
  • RCC_MSIRANGE_8 MSI clock is around 16 MHz
  • RCC_MSIRANGE_9 MSI clock is around 24 MHz
  • RCC_MSIRANGE_10 MSI clock is around 32 MHz
  • RCC_MSIRANGE_11 MSI clock is around 48 MHz
Return values:
None

Definition at line 2587 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PLL_CONFIG | ( | __PLLSOURCE__,
 |  | __PLLM__,
 |  | __PLLN__,
 |  | __PLLP__,
 |  | __PLLQ__,
 |  | __PLLR__
 | ) |
Value:
MODIFY_REG( RCC->PLLCFGR,                                                   \
                             (RCC_PLLCFGR_PLLSRC                              |               \
                              RCC_PLLCFGR_PLLM                                |               \
                              RCC_PLLCFGR_PLLN                                |               \
                              RCC_PLLCFGR_PLLP                                |               \
                              RCC_PLLCFGR_PLLQ                                |               \
                              RCC_PLLCFGR_PLLR),                                              \
                             ((uint32_t) (__PLLSOURCE__)                      |               \
                              (uint32_t) (__PLLM__)                           |               \
                              (uint32_t) ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) |               \
                              (uint32_t) (__PLLP__)                           |               \
                              (uint32_t) (__PLLQ__)                           |               \
                              (uint32_t) (__PLLR__)))

Macro to configure the main PLL clock source, multiplication and division factors.

Note:
This function must be used only when the main PLL is disabled.
Parameters:
__PLLSOURCE__ specifies the PLL entry clock source. This parameter can be one of the following values:
  • RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
  • RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry
  • RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
  • RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
Note:
This clock source is common for the main PLL and audio PLL (PLL and PLLSAI1).
Parameters:
__PLLM__ specifies the division factor for PLL VCO input clock. This parameter must be a value of PLLM Clock Divider.
Note:
You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 2.66 to 16 MHz. It is recommended to select a frequency of 16 MHz to limit PLL jitter.
Parameters:
__PLLN__ specifies the multiplication factor for PLL VCO output clock. This parameter must be a number between 6 and 127.
Note:
You have to set the PLLN parameter correctly to ensure that the VCO output frequency is between 96 and 344 MHz.
Parameters:
__PLLP__ | specifies the division factor for ADC and SAI1 clock. This parameter must be a value of PLLP Clock Divider.
__PLLQ__ | specifies the division factor for USB and RNG clocks. This parameter must be a value of PLLQ Clock Divider
Note:
If the USB FS is used in your application, you have to set the PLLQ parameter correctly to have 48 MHz clock for the USB. However, the RNG need a frequency lower than or equal to 48 MHz to work correctly.
Parameters:
__PLLR__ specifies the division factor for the main system clock. This parameter must be a value of PLLR Clock Divider
Note:
You have to set the PLLR parameter correctly to not exceed 48 MHZ.
Return values:
None

Definition at line 2887 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PLL_DISABLE ( ) LL_RCC_PLL_Disable()

Definition at line 2819 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PLL_ENABLE ( ) LL_RCC_PLL_Enable()

Macros to enable or disable the main PLL.

Note:
After enabling the main PLL, the application software should wait on PLLRDY flag to be set indicating that PLL clock is stable and can be used as system clock source.
The main PLL can not be disabled if it is used as system clock source
The main PLL is disabled by hardware when entering STOP and STANDBY modes.
Return values:
None

Definition at line 2818 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PLL_PLLM_CONFIG ( __PLLM__ ) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))

Macro to configure the PLL multiplication factor.

Note:
This function must be used only when the main PLL is disabled.
Parameters:
__PLLM__ specifies the division factor for PLL VCO input clock This parameter must be a value of PLLM Clock Divider.
Note:
You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 4 to 16 MHz. It is recommended to select a frequency of 16 MHz to limit PLL jitter.
Return values:
None

Definition at line 2846 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_PLL_PLLSOURCE_CONFIG ( __PLLSOURCE__ ) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))

Macro to configure the PLL clock source.

Note:
This function must be used only when the main PLL is disabled.
Parameters:
__PLLSOURCE__ specifies the PLL entry clock source. This parameter can be one of the following values:
  • RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
  • RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry
  • RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
  • RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
Note:
This clock source is common for the main PLL and audio PLL (PLL and PLLSAI1).
Return values:
None

Definition at line 2833 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_PLLCLKOUT_DISABLE ( __PLLCLOCKOUT__ ) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))

Definition at line 2928 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PLLCLKOUT_ENABLE ( __PLLCLOCKOUT__ ) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))

Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_USBCLK, RCC_PLL_SAI1CLK)

Note:
Enabling/disabling clock outputs RCC_PLL_SAI1CLK and RCC_PLL_USBCLK can be done at anytime without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot be stopped if used as System Clock.
Parameters:
__PLLCLOCKOUT__ specifies the PLL clock to be output. This parameter can be one or a combination of the following values:
  • RCC_PLL_SAI1CLK This clock is used to generate the clock for SAI
  • RCC_PLL_ADCCLK This clock is used to generate the clock for ADC
  • RCC_PLL_USBCLK This Clock is used to generate the clock for the USB FS (48 MHz)
  • RCC_PLL_RNGCLK This clock is used to generate the clock for RNG
  • RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 64MHz)
Return values:
None

Definition at line 2926 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_RTC_CONFIG ( __RTC_CLKSOURCE__ ) LL_RCC_SetRTCClockSource(__RTC_CLKSOURCE__)

Macros to configure the RTC clock (RTCCLK).

Note:
As the RTC clock configuration bits are in the Backup domain and write access is denied to this domain after reset, you have to enable write access using the Power Backup Access macro before to configure the RTC clock source (to be done once after reset).
Once the RTC clock is configured it cannot be changed unless the Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by a Power On Reset (POR).
Parameters:
__RTC_CLKSOURCE__ specifies the RTC clock source. This parameter can be one of the following values:*
  • RCC_RTCCLKSOURCE_NONE none clock selected as RTC clock.
  • RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
  • RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
  • RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected
Note:
If the LSE or LSI is used as RTC clock source, the RTC continues to work in STOP and STANDBY modes, and can be used as wakeup source. However, when the HSE clock is used as RTC clock source, the RTC cannot be used in STOP and STANDBY modes.
The maximum input clock frequency for RTC is 1MHz (when using HSE as RTC clock source).
Return values:
None

Definition at line 2798 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_SYSCLK_CONFIG ( __SYSCLKSOURCE__ ) LL_RCC_SetSysClkSource(__SYSCLKSOURCE__)

Macro to configure the system clock source.

Parameters:
__SYSCLKSOURCE__ specifies the system clock source. This parameter can be one of the following values:
  • RCC_SYSCLKSOURCE_MSI MSI oscillator is used as system clock source.
  • RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
  • RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
  • RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
Return values:
None

Definition at line 2953 of file stm32wbxx_hal_rcc.h.

#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG ( __STOPWUCLK__ ) LL_RCC_SetClkAfterWakeFromStop(__STOPWUCLK__)

Macro to configure the wake up from stop clock.

Parameters:
__STOPWUCLK__ specifies the clock source used after wake up from stop. This parameter can be one of the following values:
  • RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source
  • RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source
Return values:
None

Definition at line 2989 of file stm32wbxx_hal_rcc.h.

Referenced by HAL_RCCEx_WakeUpStopCLKConfig().

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RCCEx Private Constants

Defines
RCCEx Private Constants
RCCEx

Defines

#define | PLLSAI1_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
#define | PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
#define | CLOCKSMPS_TIMEOUT_VALUE (5000U) /* 5 s */
#define | __LSCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define | LSCO1_GPIO_PORT GPIOA
#define | LSCO1_PIN GPIO_PIN_2
#define | __LSCO2_CLK_ENABLE() __HAL_RCC_GPIOH_CLK_ENABLE()
#define | LSCO2_GPIO_PORT GPIOH
#define | LSCO2_PIN GPIO_PIN_3
#define | __LSCO3_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
#define | LSCO3_GPIO_PORT GPIOC
#define | LSCO3_PIN GPIO_PIN_12
#define | LSI2_TIMEOUT_VALUE (3U) /* to be adjusted with DS */

Define Documentation

#define __LSCO1_CLK_ENABLE ( ) __HAL_RCC_GPIOA_CLK_ENABLE()

Definition at line 50 of file stm32wbxx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_EnableLSCO(), and HAL_RCCEx_LSCOConfig().

#define __LSCO2_CLK_ENABLE ( ) __HAL_RCC_GPIOH_CLK_ENABLE()

Definition at line 54 of file stm32wbxx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_LSCOConfig().

#define __LSCO3_CLK_ENABLE ( ) __HAL_RCC_GPIOC_CLK_ENABLE()

Definition at line 58 of file stm32wbxx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_LSCOConfig().

#define CLOCKSMPS_TIMEOUT_VALUE (5000U) /* 5 s */

Definition at line 48 of file stm32wbxx_hal_rcc_ex.c.

#define LSCO1_GPIO_PORT GPIOA

Definition at line 51 of file stm32wbxx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_EnableLSCO(), and HAL_RCCEx_LSCOConfig().

#define LSCO1_PIN GPIO_PIN_2

Definition at line 52 of file stm32wbxx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_EnableLSCO(), and HAL_RCCEx_LSCOConfig().

#define LSCO2_GPIO_PORT GPIOH

Definition at line 55 of file stm32wbxx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_LSCOConfig().

#define LSCO2_PIN GPIO_PIN_3

Definition at line 56 of file stm32wbxx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_LSCOConfig().

#define LSCO3_GPIO_PORT GPIOC

Definition at line 59 of file stm32wbxx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_LSCOConfig().

#define LSCO3_PIN GPIO_PIN_12

Definition at line 60 of file stm32wbxx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_LSCOConfig().

#define LSI2_TIMEOUT_VALUE (3U) /* to be adjusted with DS */

Definition at line 62 of file stm32wbxx_hal_rcc_ex.c.

#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */

Definition at line 46 of file stm32wbxx_hal_rcc_ex.c.

#define PLLSAI1_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */

Definition at line 45 of file stm32wbxx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_DisablePLLSAI1(), HAL_RCCEx_EnablePLLSAI1(), RCCEx_PLLSAI1_ConfigNP(), RCCEx_PLLSAI1_ConfigNQ(), and RCCEx_PLLSAI1_ConfigNR().

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RCCEx Private Functions

Functions
RCCEx Private Functions
RCCEx

Functions

static HAL_StatusTypeDef | RCCEx_PLLSAI1_ConfigNP (RCC_PLLSAI1InitTypeDef *PLLSAI1)
Configure the parameters N & P of PLLSAI1 and enable PLLSAI1 output clock(s).
static HAL_StatusTypeDef | RCCEx_PLLSAI1_ConfigNQ (RCC_PLLSAI1InitTypeDef *PLLSAI1)
Configure the parameters N & Q of PLLSAI1 and enable PLLSAI1 output clock(s).
static HAL_StatusTypeDef | RCCEx_PLLSAI1_ConfigNR (RCC_PLLSAI1InitTypeDef *PLLSAI1)
Configure the parameters N & R of PLLSAI1 and enable PLLSAI1 output clock(s).
static uint32_t | RCC_PLL_GetFreqDomain_P (void)
Return PLL clock (PLLPCLK) frequency used for SAI domain.
static uint32_t | RCC_PLL_GetFreqDomain_Q (void)
Return PLL clock (PLLQCLK) frequency used for 48 MHz domain.
static uint32_t | RCC_PLLSAI1_GetFreqDomain_R (void)
Return PLLSAI1 clock (PLLSAI1RCLK) frequency used for ADC domain.
static uint32_t | RCC_PLLSAI1_GetFreqDomain_P (void)
Return PLLSAI1 clock (PLLSAI1PCLK) frequency used for SAI domain.
static uint32_t | RCC_PLLSAI1_GetFreqDomain_Q (void)
Return PLLSAI1 clock (PLLSAI1QCLK) frequency used for 48Mhz domain.

Function Documentation

static uint32_t RCC_PLL_GetFreqDomain_P ( void ) [static]

Return PLL clock (PLLPCLK) frequency used for SAI domain.

Return values:
PLLPCLK clock frequency (in Hz)

Definition at line 2128 of file stm32wbxx_hal_rcc_ex.c.

References __LL_RCC_CALC_MSI_FREQ, __LL_RCC_CALC_PLLCLK_ADC_FREQ, HSE_VALUE, HSI_VALUE, LL_RCC_HSE_IsEnabledDiv2(), LL_RCC_MSI_GetRange(), LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetMainSource(), LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP(), LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLSOURCE_HSI, and LL_RCC_PLLSOURCE_MSI.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

static uint32_t RCC_PLL_GetFreqDomain_Q ( void ) [static]

Return PLL clock (PLLQCLK) frequency used for 48 MHz domain.

Return values:
PLLQCLK clock frequency (in Hz)

Definition at line 2171 of file stm32wbxx_hal_rcc_ex.c.

References __LL_RCC_CALC_MSI_FREQ, __LL_RCC_CALC_PLLCLK_48M_FREQ, HSE_VALUE, HSI_VALUE, LL_RCC_HSE_IsEnabledDiv2(), LL_RCC_MSI_GetRange(), LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetMainSource(), LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ(), LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLSOURCE_HSI, and LL_RCC_PLLSOURCE_MSI.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

static uint32_t RCC_PLLSAI1_GetFreqDomain_P ( void ) [static]

Return PLLSAI1 clock (PLLSAI1PCLK) frequency used for SAI domain.

Return values:
PLLSAI1PCLK clock frequency (in Hz)

Definition at line 2256 of file stm32wbxx_hal_rcc_ex.c.

References __LL_RCC_CALC_MSI_FREQ, __LL_RCC_CALC_PLLSAI1_SAI_FREQ, HSE_VALUE, HSI_VALUE, LL_RCC_HSE_IsEnabledDiv2(), LL_RCC_MSI_GetRange(), LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetMainSource(), LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetP(), LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLSOURCE_HSI, and LL_RCC_PLLSOURCE_MSI.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

static uint32_t RCC_PLLSAI1_GetFreqDomain_Q ( void ) [static]

Return PLLSAI1 clock (PLLSAI1QCLK) frequency used for 48Mhz domain.

Return values:
PLLSAI1QCLK clock frequency (in Hz)

Definition at line 2297 of file stm32wbxx_hal_rcc_ex.c.

References __LL_RCC_CALC_MSI_FREQ, __LL_RCC_CALC_PLLSAI1_48M_FREQ, HSE_VALUE, HSI_VALUE, LL_RCC_HSE_IsEnabledDiv2(), LL_RCC_MSI_GetRange(), LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetMainSource(), LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetQ(), LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLSOURCE_HSI, and LL_RCC_PLLSOURCE_MSI.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

static uint32_t RCC_PLLSAI1_GetFreqDomain_R ( void ) [static]

Return PLLSAI1 clock (PLLSAI1RCLK) frequency used for ADC domain.

Return values:
PLLSAI1RCLK clock frequency (in Hz)

Definition at line 2215 of file stm32wbxx_hal_rcc_ex.c.

References __LL_RCC_CALC_MSI_FREQ, __LL_RCC_CALC_PLLSAI1_ADC_FREQ, HSE_VALUE, HSI_VALUE, LL_RCC_HSE_IsEnabledDiv2(), LL_RCC_MSI_GetRange(), LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetMainSource(), LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetR(), LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLSOURCE_HSI, and LL_RCC_PLLSOURCE_MSI.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNP ( RCC_PLLSAI1InitTypeDef * PLLSAI1 ) [static]

Configure the parameters N & P of PLLSAI1 and enable PLLSAI1 output clock(s).

Parameters:
PLLSAI1 pointer to an RCC_PLLSAI1InitTypeDef structure that contains the configuration parameters N & P as well as PLLSAI1 output clock(s)
Note:
PLLSAI1 is temporary disable to apply new parameters
Return values:
HAL status

Definition at line 1927 of file stm32wbxx_hal_rcc_ex.c.

References __HAL_RCC_PLLSAI1_DISABLE, __HAL_RCC_PLLSAI1_DIVP_CONFIG, __HAL_RCC_PLLSAI1_ENABLE, __HAL_RCC_PLLSAI1_MULN_CONFIG, __HAL_RCC_PLLSAI1CLKOUT_ENABLE, assert_param, HAL_GetTick(), IS_RCC_PLLN_VALUE, IS_RCC_PLLP_VALUE, IS_RCC_PLLSAI1CLOCKOUT_VALUE, LL_RCC_PLLSAI1_IsReady(), RCC_PLLSAI1InitTypeDef::PLLN, RCC_PLLSAI1InitTypeDef::PLLP, PLLSAI1_TIMEOUT_VALUE, and RCC_PLLSAI1InitTypeDef::PLLSAI1ClockOut.

Referenced by HAL_RCCEx_PeriphCLKConfig().

static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNQ ( RCC_PLLSAI1InitTypeDef * PLLSAI1 ) [static]

Configure the parameters N & Q of PLLSAI1 and enable PLLSAI1 output clock(s).

Parameters:
PLLSAI1 pointer to an RCC_PLLSAI1InitTypeDef structure that contains the configuration parameters N & Q as well as PLLSAI1 output clock(s)
Note:
PLLSAI1 is temporary disable to apply new parameters
Return values:
HAL status

Definition at line 1996 of file stm32wbxx_hal_rcc_ex.c.

References __HAL_RCC_PLLSAI1_DISABLE, __HAL_RCC_PLLSAI1_DIVQ_CONFIG, __HAL_RCC_PLLSAI1_ENABLE, __HAL_RCC_PLLSAI1_MULN_CONFIG, __HAL_RCC_PLLSAI1CLKOUT_ENABLE, assert_param, HAL_GetTick(), IS_RCC_PLLN_VALUE, IS_RCC_PLLQ_VALUE, IS_RCC_PLLSAI1CLOCKOUT_VALUE, LL_RCC_PLLSAI1_IsReady(), RCC_PLLSAI1InitTypeDef::PLLN, RCC_PLLSAI1InitTypeDef::PLLQ, PLLSAI1_TIMEOUT_VALUE, and RCC_PLLSAI1InitTypeDef::PLLSAI1ClockOut.

Referenced by HAL_RCCEx_PeriphCLKConfig().

static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNR ( RCC_PLLSAI1InitTypeDef * PLLSAI1 ) [static]

Configure the parameters N & R of PLLSAI1 and enable PLLSAI1 output clock(s).

Parameters:
PLLSAI1 pointer to an RCC_PLLSAI1InitTypeDef structure that contains the configuration parameters N & R as well as PLLSAI1 output clock(s)
Note:
PLLSAI1 is temporary disable to apply new parameters
Return values:
HAL status

Definition at line 2064 of file stm32wbxx_hal_rcc_ex.c.

References __HAL_RCC_PLLSAI1_DISABLE, __HAL_RCC_PLLSAI1_DIVR_CONFIG, __HAL_RCC_PLLSAI1_ENABLE, __HAL_RCC_PLLSAI1_MULN_CONFIG, __HAL_RCC_PLLSAI1CLKOUT_ENABLE, assert_param, HAL_GetTick(), IS_RCC_PLLN_VALUE, IS_RCC_PLLR_VALUE, IS_RCC_PLLSAI1CLOCKOUT_VALUE, LL_RCC_PLLSAI1_IsReady(), RCC_PLLSAI1InitTypeDef::PLLN, RCC_PLLSAI1InitTypeDef::PLLR, PLLSAI1_TIMEOUT_VALUE, and RCC_PLLSAI1InitTypeDef::PLLSAI1ClockOut.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Extended Peripheral Control functions

Functions
Extended Peripheral Control functions
RCCEx Exported Functions

Extended Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_RCCEx_PeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Initialize the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.
void | HAL_RCCEx_GetPeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
uint32_t | HAL_RCCEx_GetPeriphCLKFreq (uint32_t PeriphClk)
Return the peripheral clock frequency for peripherals with clock source.
uint32_t | HAL_RCCEx_GetRngCLKSource (void)
Return the RNG clock source.

Detailed Description

Extended Peripheral Control functions.

 ===============================================================================
                ##### Extended Peripheral Control functions  #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the RCC Clocks
    frequencies.
    [..]
    (@) Important note: Care must be taken when @ref HAL_RCCEx_PeriphCLKConfig() is used to
        select the RTC clock source; in this case the Backup domain will be reset in
        order to modify the RTC Clock source, as consequence RTC registers (including
        the backup registers) and RCC_BDCR register are set to their reset values.

Function Documentation

void HAL_RCCEx_GetPeriphCLKConfig ( RCC_PeriphCLKInitTypeDef * PeriphClkInit )

Get the RCC_ClkInitStruct according to the internal RCC configuration registers.

Parameters:
PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that returns the configuration information for the Extended Peripherals clocks(SAI1, LPTIM1, LPTIM2, I2C1, I2C3, LPUART1, USART1, RTC, ADCx, USB, RNG, RFWKP, SMPS).
Return values:
None

Definition at line 440 of file stm32wbxx_hal_rcc_ex.c.

References __HAL_RCC_GET_ADC_SOURCE, __HAL_RCC_GET_I2C1_SOURCE, __HAL_RCC_GET_I2C3_SOURCE, __HAL_RCC_GET_LPTIM1_SOURCE, __HAL_RCC_GET_LPTIM2_SOURCE, __HAL_RCC_GET_LPUART1_SOURCE, __HAL_RCC_GET_RFWAKEUP_SOURCE, __HAL_RCC_GET_RTC_SOURCE, __HAL_RCC_GET_SAI1_SOURCE, __HAL_RCC_GET_SMPS_DIV, __HAL_RCC_GET_SMPS_SOURCE, __HAL_RCC_GET_USART1_SOURCE, __HAL_RCC_GET_USB_SOURCE, RCC_PeriphCLKInitTypeDef::AdcClockSelection, HAL_RCCEx_GetRngCLKSource(), RCC_PeriphCLKInitTypeDef::I2c1ClockSelection, RCC_PeriphCLKInitTypeDef::I2c3ClockSelection, LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetP(), LL_RCC_PLLSAI1_GetQ(), LL_RCC_PLLSAI1_GetR(), RCC_PeriphCLKInitTypeDef::Lptim1ClockSelection, RCC_PeriphCLKInitTypeDef::Lptim2ClockSelection, RCC_PeriphCLKInitTypeDef::Lpuart1ClockSelection, RCC_PeriphCLKInitTypeDef::PeriphClockSelection, RCC_PLLSAI1InitTypeDef::PLLN, RCC_PLLSAI1InitTypeDef::PLLP, RCC_PLLSAI1InitTypeDef::PLLQ, RCC_PLLSAI1InitTypeDef::PLLR, RCC_PeriphCLKInitTypeDef::PLLSAI1, RCC_PERIPHCLK_ADC, RCC_PERIPHCLK_I2C1, RCC_PERIPHCLK_I2C3, RCC_PERIPHCLK_LPTIM2, RCC_PERIPHCLK_LPUART1, RCC_PERIPHCLK_RFWAKEUP, RCC_PERIPHCLK_SAI1, RCC_PERIPHCLK_SMPS, RCC_PERIPHCLK_USART1, RCC_PERIPHCLK_USB, RCC_PeriphCLKInitTypeDef::RFWakeUpClockSelection, RCC_PeriphCLKInitTypeDef::RngClockSelection, RCC_PeriphCLKInitTypeDef::RTCClockSelection, RCC_PeriphCLKInitTypeDef::Sai1ClockSelection, RCC_PeriphCLKInitTypeDef::SmpsClockSelection, RCC_PeriphCLKInitTypeDef::SmpsDivSelection, RCC_PeriphCLKInitTypeDef::Usart1ClockSelection, and RCC_PeriphCLKInitTypeDef::UsbClockSelection.

uint32_t HAL_RCCEx_GetPeriphCLKFreq ( uint32_t PeriphClk )

Return the peripheral clock frequency for peripherals with clock source.

Note:
Return 0 if peripheral clock identifier not managed by this API
Parameters:
PeriphClk Peripheral clock identifier This parameter can be one of the following values:
  • RCC_PERIPHCLK_RTC RTC peripheral clock
  • RCC_PERIPHCLK_ADC ADC peripheral clock
  • RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
  • RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
  • RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock
  • RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock
  • RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
  • RCC_PERIPHCLK_RNG RNG peripheral clock
  • RCC_PERIPHCLK_SAI1 SAI1 peripheral clock
  • RCC_PERIPHCLK_USART1 USART1 peripheral clock
  • RCC_PERIPHCLK_USB USB peripheral clock
  • RCC_PERIPHCLK_RFWAKEUP RFWKP peripheral clock
  • RCC_PERIPHCLK_SMPS SMPS peripheral clock
Return values:
Frequency in Hz

Definition at line 546 of file stm32wbxx_hal_rcc_ex.c.

References __LL_RCC_CALC_HCLK1_FREQ, __LL_RCC_CALC_MSI_FREQ, __LL_RCC_CALC_PCLK1_FREQ, __LL_RCC_CALC_PCLK2_FREQ, assert_param, EXTERNAL_SAI1_CLOCK_VALUE, HAL_RCC_GetSysClockFreq(), HAL_RCCEx_GetRngCLKSource(), HSE_VALUE, HSI48_VALUE, HSI_VALUE, IS_RCC_PERIPHCLOCK, LL_RCC_ADC_CLKSOURCE, LL_RCC_ADC_CLKSOURCE_PLL, LL_RCC_ADC_CLKSOURCE_PLLSAI1, LL_RCC_ADC_CLKSOURCE_SYSCLK, LL_RCC_GetADCClockSource(), LL_RCC_GetAHBPrescaler(), LL_RCC_GetAPB1Prescaler(), LL_RCC_GetAPB2Prescaler(), LL_RCC_GetI2CClockSource(), LL_RCC_GetLPTIMClockSource(), LL_RCC_GetLPUARTClockSource(), LL_RCC_GetRFWKPClockSource(), LL_RCC_GetRTCClockSource(), LL_RCC_GetSAIClockSource(), LL_RCC_GetSMPSClockSource(), LL_RCC_GetSMPSPrescaler(), LL_RCC_GetUSARTClockSource(), LL_RCC_GetUSBClockSource(), LL_RCC_HSE_IsReady(), LL_RCC_HSI48_IsReady(), LL_RCC_HSI_IsReady(), LL_RCC_I2C1_CLKSOURCE, LL_RCC_I2C1_CLKSOURCE_HSI, LL_RCC_I2C1_CLKSOURCE_SYSCLK, LL_RCC_I2C3_CLKSOURCE, LL_RCC_I2C3_CLKSOURCE_HSI, LL_RCC_I2C3_CLKSOURCE_SYSCLK, LL_RCC_LPTIM1_CLKSOURCE, LL_RCC_LPTIM1_CLKSOURCE_HSI, LL_RCC_LPTIM1_CLKSOURCE_LSE, LL_RCC_LPTIM1_CLKSOURCE_LSI, LL_RCC_LPTIM2_CLKSOURCE, LL_RCC_LPTIM2_CLKSOURCE_HSI, LL_RCC_LPTIM2_CLKSOURCE_LSE, LL_RCC_LPTIM2_CLKSOURCE_LSI, LL_RCC_LPUART1_CLKSOURCE, LL_RCC_LPUART1_CLKSOURCE_HSI, LL_RCC_LPUART1_CLKSOURCE_LSE, LL_RCC_LPUART1_CLKSOURCE_SYSCLK, LL_RCC_LSE_IsReady(), LL_RCC_LSI1_IsReady(), LL_RCC_LSI2_IsReady(), LL_RCC_MSI_GetRange(), LL_RCC_MSI_IsReady(), LL_RCC_MSIRANGE_10, LL_RCC_MSIRANGE_11, LL_RCC_MSIRANGE_8, LL_RCC_MSIRANGE_9, LL_RCC_PLL_IsReady(), LL_RCC_PLLSAI1_IsReady(), LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024, LL_RCC_RFWKP_CLKSOURCE_LSE, LL_RCC_RFWKP_CLKSOURCE_LSI, LL_RCC_RTC_CLKSOURCE_HSE_DIV32, LL_RCC_RTC_CLKSOURCE_LSE, LL_RCC_RTC_CLKSOURCE_LSI, LL_RCC_SAI1_CLKSOURCE, LL_RCC_SAI1_CLKSOURCE_HSI, LL_RCC_SAI1_CLKSOURCE_PLL, LL_RCC_SAI1_CLKSOURCE_PLLSAI1, LL_RCC_SMPS_CLKSOURCE_STATUS_HSE, LL_RCC_SMPS_CLKSOURCE_STATUS_HSI, LL_RCC_SMPS_CLKSOURCE_STATUS_MSI, LL_RCC_USART1_CLKSOURCE, LL_RCC_USART1_CLKSOURCE_HSI, LL_RCC_USART1_CLKSOURCE_LSE, LL_RCC_USART1_CLKSOURCE_SYSCLK, LL_RCC_USB_CLKSOURCE, LL_RCC_USB_CLKSOURCE_MSI, LL_RCC_USB_CLKSOURCE_PLL, LL_RCC_USB_CLKSOURCE_PLLSAI1, LSE_VALUE, RCC_PERIPHCLK_ADC, RCC_PERIPHCLK_I2C1, RCC_PERIPHCLK_I2C3, RCC_PERIPHCLK_LPTIM1, RCC_PERIPHCLK_LPTIM2, RCC_PERIPHCLK_LPUART1, RCC_PERIPHCLK_RFWAKEUP, RCC_PERIPHCLK_RNG, RCC_PERIPHCLK_RTC, RCC_PERIPHCLK_SAI1, RCC_PERIPHCLK_SMPS, RCC_PERIPHCLK_USART1, RCC_PERIPHCLK_USB, RCC_PLL_GetFreqDomain_P(), RCC_PLL_GetFreqDomain_Q(), RCC_PLLSAI1_GetFreqDomain_P(), RCC_PLLSAI1_GetFreqDomain_Q(), RCC_PLLSAI1_GetFreqDomain_R(), RCC_RNGCLKSOURCE_LSE, RCC_RNGCLKSOURCE_LSI, RCC_RNGCLKSOURCE_MSI, and RCC_RNGCLKSOURCE_PLL.

Referenced by HAL_SAI_Init().

uint32_t HAL_RCCEx_GetRngCLKSource ( void )

Return the RNG clock source.

Return values:
The RNG clock source can be one of the following values:
  • RCC_RNGCLKSOURCE_HSI48 HSI48 clock divided by 3 selected as RNG clock
  • RCC_RNGCLKSOURCE_PLL PLL "Q" clock divided by 3 selected as RNG clock
  • RCC_RNGCLKSOURCE_MSI MSI clock divided by 3 selected as RNG clock
  • RCC_RNGCLKSOURCE_LSI LSI clock selected as RNG clock
  • RCC_RNGCLKSOURCE_LSE LSE clock selected as RNG clock

Definition at line 1111 of file stm32wbxx_hal_rcc_ex.c.

References CLK48_MASK, LL_RCC_CLK48_CLKSOURCE, LL_RCC_GetCLK48ClockSource(), LL_RCC_GetRNGClockSource(), LL_RCC_RNG_CLKSOURCE, and RCC_RNGCLKSOURCE_CLK48.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig ( RCC_PeriphCLKInitTypeDef * PeriphClkInit )

Initialize the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.

Parameters:
PeriphClkInit pointer to a RCC_PeriphCLKInitTypeDef structure that contains a field PeriphClockSelection which can be a combination of the following values:
  • RCC_PERIPHCLK_USART1 USART1 peripheral clock
  • RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
  • RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
  • RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
  • RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock
  • RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock
  • RCC_PERIPHCLK_SAI1 SAI1 peripheral clock
  • RCC_PERIPHCLK_USB USB peripheral clock
  • RCC_PERIPHCLK_RNG RNG peripheral clock
  • RCC_PERIPHCLK_ADC ADC peripheral clock
  • RCC_PERIPHCLK_RTC RTC peripheral clock
  • RCC_PERIPHCLK_RFWAKEUP RFWKP peripheral clock
  • RCC_PERIPHCLK_SMPS SMPS peripheral clock
Note:
Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select the RTC clock source: in this case the access to Backup domain is enabled.
Return values:
HAL status

Definition at line 148 of file stm32wbxx_hal_rcc_ex.c.

References __HAL_RCC_ADC_CONFIG, __HAL_RCC_I2C1_CONFIG, __HAL_RCC_I2C3_CONFIG, __HAL_RCC_LPTIM1_CONFIG, __HAL_RCC_LPTIM2_CONFIG, __HAL_RCC_LPUART1_CONFIG, __HAL_RCC_PLLCLKOUT_ENABLE, __HAL_RCC_RFWAKEUP_CONFIG, __HAL_RCC_RNG_CONFIG, __HAL_RCC_SAI1_CONFIG, __HAL_RCC_SMPS_CONFIG, __HAL_RCC_SMPS_DIV_CONFIG, __HAL_RCC_USART1_CONFIG, __HAL_RCC_USB_CONFIG, RCC_PeriphCLKInitTypeDef::AdcClockSelection, assert_param, HAL_GetTick(), HAL_PWR_EnableBkUpAccess(), RCC_PeriphCLKInitTypeDef::I2c1ClockSelection, RCC_PeriphCLKInitTypeDef::I2c3ClockSelection, IS_RCC_ADCCLKSOURCE, IS_RCC_I2C1CLKSOURCE, IS_RCC_I2C3CLKSOURCE, IS_RCC_LPTIM1CLK, IS_RCC_LPTIM2CLK, IS_RCC_LPUART1CLKSOURCE, IS_RCC_PERIPHCLOCK, IS_RCC_RFWKPCLKSOURCE, IS_RCC_RNGCLKSOURCE, IS_RCC_RTCCLKSOURCE, IS_RCC_SAI1CLK, IS_RCC_SMPSCLKDIV, IS_RCC_SMPSCLKSOURCE, IS_RCC_USART1CLKSOURCE, IS_RCC_USBCLKSOURCE, LL_RCC_ForceBackupDomainReset(), LL_RCC_GetRTCClockSource(), LL_RCC_LSE_IsEnabled(), LL_RCC_LSE_IsReady(), LL_RCC_ReadReg, LL_RCC_ReleaseBackupDomainReset(), LL_RCC_SetRTCClockSource(), LL_RCC_WriteReg, RCC_PeriphCLKInitTypeDef::Lptim1ClockSelection, RCC_PeriphCLKInitTypeDef::Lptim2ClockSelection, RCC_PeriphCLKInitTypeDef::Lpuart1ClockSelection, RCC_PeriphCLKInitTypeDef::PeriphClockSelection, RCC_PeriphCLKInitTypeDef::PLLSAI1, RCC_ADCCLKSOURCE_PLL, RCC_ADCCLKSOURCE_PLLSAI1, RCC_LSE_TIMEOUT_VALUE, RCC_PERIPHCLK_ADC, RCC_PERIPHCLK_I2C1, RCC_PERIPHCLK_I2C3, RCC_PERIPHCLK_LPTIM1, RCC_PERIPHCLK_LPTIM2, RCC_PERIPHCLK_LPUART1, RCC_PERIPHCLK_RFWAKEUP, RCC_PERIPHCLK_RNG, RCC_PERIPHCLK_RTC, RCC_PERIPHCLK_SAI1, RCC_PERIPHCLK_SMPS, RCC_PERIPHCLK_USART1, RCC_PERIPHCLK_USB, RCC_PLL_ADCCLK, RCC_PLL_RNGCLK, RCC_PLL_SAI1CLK, RCC_PLL_USBCLK, RCC_RNGCLKSOURCE_PLL, RCC_RTCCLKSOURCE_NONE, RCC_SAI1CLKSOURCE_HSI, RCC_SAI1CLKSOURCE_PIN, RCC_SAI1CLKSOURCE_PLL, RCC_SAI1CLKSOURCE_PLLSAI1, RCC_USBCLKSOURCE_PLL, RCC_USBCLKSOURCE_PLLSAI1, RCCEx_PLLSAI1_ConfigNP(), RCCEx_PLLSAI1_ConfigNQ(), RCCEx_PLLSAI1_ConfigNR(), RCC_PeriphCLKInitTypeDef::RFWakeUpClockSelection, RCC_PeriphCLKInitTypeDef::RngClockSelection, RCC_PeriphCLKInitTypeDef::RTCClockSelection, RCC_PeriphCLKInitTypeDef::Sai1ClockSelection, RCC_PeriphCLKInitTypeDef::SmpsClockSelection, RCC_PeriphCLKInitTypeDef::SmpsDivSelection, RCC_PeriphCLKInitTypeDef::Usart1ClockSelection, and RCC_PeriphCLKInitTypeDef::UsbClockSelection.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Extended Clock management functions

Functions
Extended Clock management functions
RCCEx Exported Functions

Extended Clock management functions. More...

Functions

HAL_StatusTypeDef | HAL_RCCEx_EnablePLLSAI1 (RCC_PLLSAI1InitTypeDef *PLLSAI1Init)
Enable PLLSAI1.
HAL_StatusTypeDef | HAL_RCCEx_DisablePLLSAI1 (void)
Disable PLLSAI1.
void | HAL_RCCEx_WakeUpStopCLKConfig (uint32_t WakeUpClk)
Configure the oscillator clock source for wakeup from Stop and CSS backup clock.
void | HAL_RCCEx_EnableLSECSS (void)
Enable the LSE Clock Security System.
void | HAL_RCCEx_DisableLSECSS (void)
Disable the LSE Clock Security System.
void | HAL_RCCEx_EnableLSECSS_IT (void)
Enable the LSE Clock Security System Interrupt & corresponding EXTI line.
void | HAL_RCCEx_LSECSS_IRQHandler (void)
Handle the RCC LSE Clock Security System interrupt request.
__weak void | HAL_RCCEx_LSECSS_Callback (void)
RCCEx LSE Clock Security System interrupt callback.
void | HAL_RCCEx_LSCOConfig (uint32_t RCC_LSCOx, uint32_t RCC_LSCOSource)
Select the clock source to output on LSCO1 pin(PA2) or LSC02 pin (PH3) or LSCO3 pin (PC12).
void | HAL_RCCEx_EnableLSCO (uint32_t LSCOSource)
Select the Low Speed clock source to output on LSCO pin (PA2).
void | HAL_RCCEx_DisableLSCO (void)
Disable the Low Speed clock output.
void | HAL_RCCEx_EnableMSIPLLMode (void)
Enable the PLL-mode of the MSI.
void | HAL_RCCEx_DisableMSIPLLMode (void)
Disable the PLL-mode of the MSI.
HAL_StatusTypeDef | HAL_RCCEx_TrimOsc (uint32_t OscillatorType)
Set trimming value.

Detailed Description

Extended Clock management functions.

 ===============================================================================
                ##### Extended clock management functions  #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the
    activation or deactivation of MSI PLL-mode, PLLSAI1, PLLSAI12, LSE CSS,
    Low speed clock output and clock after wake-up from STOP mode.

Function Documentation

void HAL_RCCEx_DisableLSCO ( void )

Disable the Low Speed clock output.

Return values:
None

Definition at line 1463 of file stm32wbxx_hal_rcc_ex.c.

References HAL_PWR_DisableBkUpAccess(), HAL_PWR_EnableBkUpAccess(), and LL_RCC_LSCO_Disable().

void HAL_RCCEx_DisableLSECSS ( void )

Disable the LSE Clock Security System.

Note:
LSE Clock Security System can only be disabled after a LSE failure detection.
Return values:
None

Definition at line 1276 of file stm32wbxx_hal_rcc_ex.c.

References __HAL_RCC_DISABLE_IT, LL_RCC_LSE_DisableCSS(), and RCC_IT_LSECSS.

void HAL_RCCEx_DisableMSIPLLMode ( void )

Disable the PLL-mode of the MSI.

Note:
PLL-mode of the MSI is automatically reset when LSE oscillator is disabled.
Return values:
None

Definition at line 1504 of file stm32wbxx_hal_rcc_ex.c.

References LL_RCC_MSI_DisablePLLMode().

HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1 ( void )

Disable PLLSAI1.

Return values:
HAL status

Definition at line 1212 of file stm32wbxx_hal_rcc_ex.c.

References __HAL_RCC_PLLSAI1_DISABLE, __HAL_RCC_PLLSAI1CLKOUT_DISABLE, HAL_GetTick(), LL_RCC_PLLSAI1_IsReady(), PLLSAI1_TIMEOUT_VALUE, RCC_PLLSAI1_ADCCLK, RCC_PLLSAI1_SAI1CLK, and RCC_PLLSAI1_USBCLK.

void HAL_RCCEx_EnableLSCO ( uint32_t LSCOSource )

Select the Low Speed clock source to output on LSCO pin (PA2).

Parameters:
LSCOSource specifies the Low Speed clock source to output. This parameter can be one of the following values:
  • RCC_LSCOSOURCE_LSI LSI clock selected as LSCO source
  • RCC_LSCOSOURCE_LSE LSE clock selected as LSCO source
Return values:
None

Definition at line 1421 of file stm32wbxx_hal_rcc_ex.c.

References __LSCO1_CLK_ENABLE, GPIO_InitTypeDef::Alternate, assert_param, GPIO_AF0_LSCO, GPIO_MODE_AF_PP, GPIO_NOPULL, GPIO_SPEED_FREQ_VERY_HIGH, HAL_GPIO_Init(), HAL_PWR_DisableBkUpAccess(), HAL_PWR_EnableBkUpAccess(), IS_RCC_LSCOSOURCE, LSCO1_GPIO_PORT, LSCO1_PIN, GPIO_InitTypeDef::Mode, GPIO_InitTypeDef::Pin, GPIO_InitTypeDef::Pull, and GPIO_InitTypeDef::Speed.

void HAL_RCCEx_EnableLSECSS ( void )

Enable the LSE Clock Security System.

Note:
Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC clock with HAL_RCCEx_PeriphCLKConfig().
Return values:
None

Definition at line 1266 of file stm32wbxx_hal_rcc_ex.c.

References LL_RCC_LSE_EnableCSS().

void HAL_RCCEx_EnableLSECSS_IT ( void )

Enable the LSE Clock Security System Interrupt & corresponding EXTI line.

Note:
LSE Clock Security System Interrupt is mapped on RTC EXTI line 18
Return values:
None

Definition at line 1289 of file stm32wbxx_hal_rcc_ex.c.

References __HAL_RCC_ENABLE_IT, __HAL_RCC_LSECSS_EXTI_ENABLE_IT, __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE, LL_RCC_LSE_EnableCSS(), and RCC_IT_LSECSS.

void HAL_RCCEx_EnableMSIPLLMode ( void )

Enable the PLL-mode of the MSI.

Note:
Prior to enable the PLL-mode of the MSI for automatic hardware calibration LSE oscillator is to be enabled with HAL_RCC_OscConfig().
Return values:
None

Definition at line 1494 of file stm32wbxx_hal_rcc_ex.c.

References LL_RCC_MSI_EnablePLLMode().

HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1 ( RCC_PLLSAI1InitTypeDef * PLLSAI1Init )

Enable PLLSAI1.

Parameters:
PLLSAI1Init pointer to an RCC_PLLSAI1InitTypeDef structure that contains the configuration information for the PLLSAI1
Return values:
HAL status

Definition at line 1152 of file stm32wbxx_hal_rcc_ex.c.

References __HAL_RCC_PLLSAI1_CONFIG, __HAL_RCC_PLLSAI1_DISABLE, __HAL_RCC_PLLSAI1_ENABLE, __HAL_RCC_PLLSAI1CLKOUT_ENABLE, assert_param, HAL_GetTick(), IS_RCC_PLLN_VALUE, IS_RCC_PLLP_VALUE, IS_RCC_PLLQ_VALUE, IS_RCC_PLLR_VALUE, IS_RCC_PLLSAI1CLOCKOUT_VALUE, LL_RCC_PLLSAI1_IsReady(), RCC_PLLSAI1InitTypeDef::PLLN, RCC_PLLSAI1InitTypeDef::PLLP, RCC_PLLSAI1InitTypeDef::PLLQ, RCC_PLLSAI1InitTypeDef::PLLR, PLLSAI1_TIMEOUT_VALUE, and RCC_PLLSAI1InitTypeDef::PLLSAI1ClockOut.

void HAL_RCCEx_LSCOConfig | ( | uint32_t | RCC_LSCOx,
 |  | uint32_t | RCC_LSCOSource
 | ) |  |

Select the clock source to output on LSCO1 pin(PA2) or LSC02 pin (PH3) or LSCO3 pin (PC12).

Note:
PA2, PH3 or PC12 should be configured in alternate function mode.
Parameters:
RCC_LSCOx specifies the output direction for the clock source.
  • RCC_LSCO1 Clock source to output on LSCO1 pin(PA2)
  • RCC_LSCO2 Clock source to output on LSCO2 pin(PH13)
  • RCC_LSCO3 Clock source to output on LSCO3 pin(PC12)
RCC_LSCOSource specifies the clock source to output. This parameter can be one of the following values:
  • RCC_LSCOSOURCE_LSI LSI clock selected as LSCO source
  • RCC_LSCOSOURCE_LSE LSE clock selected as LSCO source
Return values:
None
Note:
LSCO should be disable with HAL_RCCEx_DisableLSCO

Definition at line 1346 of file stm32wbxx_hal_rcc_ex.c.

References __LSCO1_CLK_ENABLE, __LSCO2_CLK_ENABLE, __LSCO3_CLK_ENABLE, GPIO_InitTypeDef::Alternate, assert_param, GPIO_AF0_LSCO, GPIO_AF6_LSCO, GPIO_MODE_AF_PP, GPIO_NOPULL, GPIO_SPEED_FREQ_VERY_HIGH, HAL_GPIO_Init(), HAL_PWR_DisableBkUpAccess(), HAL_PWR_EnableBkUpAccess(), IS_RCC_LSCO, IS_RCC_LSCOSOURCE, LSCO1_GPIO_PORT, LSCO1_PIN, LSCO2_GPIO_PORT, LSCO2_PIN, LSCO3_GPIO_PORT, LSCO3_PIN, GPIO_InitTypeDef::Mode, GPIO_InitTypeDef::Pin, GPIO_InitTypeDef::Pull, RCC_LSCO1, RCC_LSCO2, and GPIO_InitTypeDef::Speed.

void HAL_RCCEx_LSECSS_Callback ( void )

RCCEx LSE Clock Security System interrupt callback.

Return values:
none

Definition at line 1325 of file stm32wbxx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_LSECSS_IRQHandler().

void HAL_RCCEx_LSECSS_IRQHandler ( void )

Handle the RCC LSE Clock Security System interrupt request.

Return values:
None

Definition at line 1308 of file stm32wbxx_hal_rcc_ex.c.

References __HAL_RCC_CLEAR_IT, __HAL_RCC_GET_IT, HAL_RCCEx_LSECSS_Callback(), and RCC_IT_LSECSS.

HAL_StatusTypeDef HAL_RCCEx_TrimOsc ( uint32_t OscillatorType )

Set trimming value.

Parameters:
OscillatorType Specifies the oscillator to be trimmed This parameter can be one of the following values:
  • RCC_OSCILLATORTYPE_LSI2 LSI2 oscillator selected. When disabling and re-enabling the LSI2 there is no need for re-trimming Trimming is only needed once after a NRST reset. Trimming values comes from factory trimmed flash location (0x1FFF7548).
Note:
The LSI2 oscillator must be disabled before calling this trimming function through HAL_RCC_OscConfig
Return values:
HAL status

Definition at line 1520 of file stm32wbxx_hal_rcc_ex.c.

References assert_param, FTLSI2TRIM, IS_RCC_TRIMOSC, LL_RCC_LSI2_IsReady(), LL_RCC_LSI2_SetTrimming(), and RCC_OSCILLATORTYPE_LSI2.

void HAL_RCCEx_WakeUpStopCLKConfig ( uint32_t WakeUpClk )

Configure the oscillator clock source for wakeup from Stop and CSS backup clock.

Parameters:
WakeUpClk Wakeup clock This parameter can be one of the following values:
  • RCC_STOP_WAKEUPCLOCK_MSI MSI oscillator selection
  • RCC_STOP_WAKEUPCLOCK_HSI HSI oscillator selection
Note:
This function shall not be called after the Clock Security System on HSE has been enabled.
Return values:
None

Definition at line 1252 of file stm32wbxx_hal_rcc_ex.c.

References __HAL_RCC_WAKEUPSTOP_CLK_CONFIG, assert_param, and IS_RCC_STOP_WAKEUPCLOCK.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Extended Clock Recovery System Control functions

Functions
Extended Clock Recovery System Control functions
RCCEx Exported Functions

Extended Clock Recovery System Control functions. More...

Functions

void | HAL_RCCEx_CRSConfig (RCC_CRSInitTypeDef *pInit)
Start automatic synchronization for polling mode.
void | HAL_RCCEx_CRSSoftwareSynchronizationGenerate (void)
Generate the software synchronization event.
void | HAL_RCCEx_CRSGetSynchronizationInfo (RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
Return synchronization info.
uint32_t | HAL_RCCEx_CRSWaitSynchronization (uint32_t Timeout)
Wait for CRS Synchronization status.
void | HAL_RCCEx_CRS_IRQHandler (void)
Handle the Clock Recovery System interrupt request.
__weak void | HAL_RCCEx_CRS_SyncOkCallback (void)
RCCEx Clock Recovery System SYNCOK interrupt callback.
__weak void | HAL_RCCEx_CRS_SyncWarnCallback (void)
RCCEx Clock Recovery System SYNCWARN interrupt callback.
__weak void | HAL_RCCEx_CRS_ExpectedSyncCallback (void)
RCCEx Clock Recovery System Expected SYNC interrupt callback.
__weak void | HAL_RCCEx_CRS_ErrorCallback (uint32_t Error)
RCCEx Clock Recovery System Error interrupt callback.

Detailed Description

Extended Clock Recovery System Control functions.

 ===============================================================================
                ##### Extended Clock Recovery System Control functions  #####
 ===============================================================================
    [..]
      For devices with Clock Recovery System feature (CRS), RCC Extention HAL driver can be used as follows:

      (#) In System clock config, HSI48 needs to be enabled

      (#) Enable CRS clock in IP MSP init which will use CRS functions

      (#) Call CRS functions as follows:
          (##) Prepare synchronization configuration necessary for HSI48 calibration
              (+++) Default values can be set for frequency Error Measurement (reload and error limit)
                        and also HSI48 oscillator smooth trimming.
              (+++) Macro @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
                        directly reload value with target and sychronization frequencies values
          (##) Call function @ref HAL_RCCEx_CRSConfig which
              (+++) Resets CRS registers to their default values.
              (+++) Configures CRS registers with synchronization configuration
              (+++) Enables automatic calibration and frequency error counter feature
           Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
           periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
           provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
           precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
           should be used as SYNC signal.

          (##) A polling function is provided to wait for complete synchronization
              (+++) Call function @ref HAL_RCCEx_CRSWaitSynchronization()
              (+++) According to CRS status, user can decide to adjust again the calibration or continue
                        application if synchronization is OK

      (#) User can retrieve information related to synchronization in calling function
            @ref HAL_RCCEx_CRSGetSynchronizationInfo()

      (#) Regarding synchronization status and synchronization information, user can try a new calibration
           in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
           Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value),
           it means that the actual frequency is lower than the target (and so, that the TRIM value should be
           incremented), while when it is detected during the upcounting phase it means that the actual frequency
           is higher (and that the TRIM value should be decremented).

      (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go
          through CRS Handler (CRS_IRQn/CRS_IRQHandler)
              (++) Call function @ref HAL_RCCEx_CRSConfig()
              (++) Enable CRS_IRQn (thanks to NVIC functions)
              (++) Enable CRS interrupt (@ref __HAL_RCC_CRS_ENABLE_IT)
              (++) Implement CRS status management in the following user callbacks called from
                   HAL_RCCEx_CRS_IRQHandler():
                   (+++) @ref HAL_RCCEx_CRS_SyncOkCallback()
                   (+++) @ref HAL_RCCEx_CRS_SyncWarnCallback()
                   (+++) @ref HAL_RCCEx_CRS_ExpectedSyncCallback()
                   (+++) @ref HAL_RCCEx_CRS_ErrorCallback()

      (#) To force a SYNC EVENT, user can use the function @ref HAL_RCCEx_CRSSoftwareSynchronizationGenerate().
          This function can be called before calling @ref HAL_RCCEx_CRSConfig (for instance in Systick handler)

Function Documentation

void HAL_RCCEx_CRS_ErrorCallback ( uint32_t Error )

RCCEx Clock Recovery System Error interrupt callback.

Parameters:
Error Combination of Error status. This parameter can be a combination of the following values:
  • RCC_CRS_SYNCERR
  • RCC_CRS_SYNCMISS
  • RCC_CRS_TRIMOVF
Return values:
none

Definition at line 1894 of file stm32wbxx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_CRS_IRQHandler().

void HAL_RCCEx_CRS_ExpectedSyncCallback ( void )

RCCEx Clock Recovery System Expected SYNC interrupt callback.

Return values:
none

Definition at line 1878 of file stm32wbxx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_CRS_IRQHandler().

void HAL_RCCEx_CRS_IRQHandler ( void )

Handle the Clock Recovery System interrupt request.

Return values:
None

Definition at line 1791 of file stm32wbxx_hal_rcc_ex.c.

References HAL_RCCEx_CRS_ErrorCallback(), HAL_RCCEx_CRS_ExpectedSyncCallback(), HAL_RCCEx_CRS_SyncOkCallback(), HAL_RCCEx_CRS_SyncWarnCallback(), LL_CRS_ClearFlag_ERR(), LL_CRS_ClearFlag_ESYNC(), LL_CRS_ClearFlag_SYNCOK(), LL_CRS_ClearFlag_SYNCWARN(), RCC_CRS_FLAG_ERR, RCC_CRS_FLAG_ESYNC, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS, RCC_CRS_FLAG_SYNCOK, RCC_CRS_FLAG_SYNCWARN, RCC_CRS_FLAG_TRIMOVF, RCC_CRS_IT_ERR, RCC_CRS_IT_ESYNC, RCC_CRS_IT_SYNCOK, RCC_CRS_IT_SYNCWARN, RCC_CRS_NONE, RCC_CRS_SYNCERR, RCC_CRS_SYNCMISS, and RCC_CRS_TRIMOVF.

void HAL_RCCEx_CRS_SyncOkCallback ( void )

RCCEx Clock Recovery System SYNCOK interrupt callback.

Return values:
none

Definition at line 1856 of file stm32wbxx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_CRS_IRQHandler().

void HAL_RCCEx_CRS_SyncWarnCallback ( void )

RCCEx Clock Recovery System SYNCWARN interrupt callback.

Return values:
none

Definition at line 1867 of file stm32wbxx_hal_rcc_ex.c.

Referenced by HAL_RCCEx_CRS_IRQHandler().

void HAL_RCCEx_CRSConfig ( RCC_CRSInitTypeDef * pInit )

Start automatic synchronization for polling mode.

Parameters:
pInit Pointer on RCC_CRSInitTypeDef structure
Return values:
None

Definition at line 1622 of file stm32wbxx_hal_rcc_ex.c.

References __HAL_RCC_CRS_FORCE_RESET, __HAL_RCC_CRS_RELEASE_RESET, assert_param, RCC_CRSInitTypeDef::ErrorLimitValue, RCC_CRSInitTypeDef::HSI48CalibrationValue, IS_RCC_CRS_ERRORLIMIT, IS_RCC_CRS_HSI48CALIBRATION, IS_RCC_CRS_RELOADVALUE, IS_RCC_CRS_SYNC_DIV, IS_RCC_CRS_SYNC_POLARITY, IS_RCC_CRS_SYNC_SOURCE, RCC_CRSInitTypeDef::Polarity, RCC_CRSInitTypeDef::Prescaler, RCC_CRSInitTypeDef::ReloadValue, and RCC_CRSInitTypeDef::Source.

void HAL_RCCEx_CRSGetSynchronizationInfo ( RCC_CRSSynchroInfoTypeDef * pSynchroInfo )

Return synchronization info.

Parameters:
pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
Return values:
None

Definition at line 1674 of file stm32wbxx_hal_rcc_ex.c.

References assert_param, RCC_CRSSynchroInfoTypeDef::FreqErrorCapture, RCC_CRSSynchroInfoTypeDef::FreqErrorDirection, RCC_CRSSynchroInfoTypeDef::HSI48CalibrationValue, LL_CRS_GetFreqErrorCapture(), LL_CRS_GetFreqErrorDirection(), LL_CRS_GetHSI48SmoothTrimming(), LL_CRS_GetReloadCounter(), and RCC_CRSSynchroInfoTypeDef::ReloadValue.

void HAL_RCCEx_CRSSoftwareSynchronizationGenerate ( void )

Generate the software synchronization event.

Return values:
None

Definition at line 1664 of file stm32wbxx_hal_rcc_ex.c.

References LL_CRS_GenerateEvent_SWSYNC().

uint32_t HAL_RCCEx_CRSWaitSynchronization ( uint32_t Timeout )

Wait for CRS Synchronization status.

Parameters:
Timeout Duration of the timeout
Note:
Timeout is based on the maximum time to receive a SYNC event based on synchronization frequency.
If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
Return values:
Combination of Synchronization status This parameter can be a combination of the following values:
  • RCC_CRS_TIMEOUT
  • RCC_CRS_SYNCOK
  • RCC_CRS_SYNCWARN
  • RCC_CRS_SYNCERR
  • RCC_CRS_SYNCMISS
  • RCC_CRS_TRIMOVF

Definition at line 1707 of file stm32wbxx_hal_rcc_ex.c.

References __HAL_RCC_CRS_CLEAR_FLAG, __HAL_RCC_CRS_GET_FLAG, HAL_GetTick(), RCC_CRS_FLAG_ESYNC, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS, RCC_CRS_FLAG_SYNCOK, RCC_CRS_FLAG_SYNCWARN, RCC_CRS_FLAG_TRIMOVF, RCC_CRS_NONE, RCC_CRS_SYNCERR, RCC_CRS_SYNCMISS, RCC_CRS_SYNCOK, RCC_CRS_SYNCWARN, RCC_CRS_TIMEOUT, and RCC_CRS_TRIMOVF.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RCC_PLLSAI1InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_PLLSAI1InitTypeDef Struct Reference
RCCEx Exported Types

PLLSAI1 Clock structure definition. More...

#include <stm32wbxx_hal_rcc_ex.h>

Data Fields

uint32_t | PLLN
uint32_t | PLLP
uint32_t | PLLQ
uint32_t | PLLR
uint32_t | PLLSAI1ClockOut

Detailed Description

PLLSAI1 Clock structure definition.

Definition at line 241 of file stm32wbxx_hal_rcc_ex.h.

Field Documentation

uint32_t RCC_PLLSAI1InitTypeDef::PLLN

PLLN: specifies the multiplication factor for PLLSAI1 VCO output clock. This parameter must be a number between Min_Data=6 and Max_Data=127.

Definition at line 244 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI1(), HAL_RCCEx_GetPeriphCLKConfig(), RCCEx_PLLSAI1_ConfigNP(), RCCEx_PLLSAI1_ConfigNQ(), and RCCEx_PLLSAI1_ConfigNR().

uint32_t RCC_PLLSAI1InitTypeDef::PLLP

PLLP: specifies the division factor for SAI clock. This parameter must be a value of PLLP Clock Divider

Definition at line 247 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI1(), HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLLSAI1_ConfigNP().

uint32_t RCC_PLLSAI1InitTypeDef::PLLQ

PLLQ: specifies the division factor for USB/RNG clock. This parameter must be a value of PLLQ Clock Divider

Definition at line 250 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI1(), HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLLSAI1_ConfigNQ().

uint32_t RCC_PLLSAI1InitTypeDef::PLLR

PLLR: specifies the division factor for ADC clock. This parameter must be a value of PLLR Clock Divider

Definition at line 253 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI1(), HAL_RCCEx_GetPeriphCLKConfig(), and RCCEx_PLLSAI1_ConfigNR().

uint32_t RCC_PLLSAI1InitTypeDef::PLLSAI1ClockOut

PLLSAI1ClockOut: specifies PLLSAI1 output clock to be enabled. This parameter must be a value of PLLSAI1 Clock Output

Definition at line 256 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI1(), RCCEx_PLLSAI1_ConfigNP(), RCCEx_PLLSAI1_ConfigNQ(), and RCCEx_PLLSAI1_ConfigNR().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_rcc_ex.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RCC_PeriphCLKInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_PeriphCLKInitTypeDef Struct Reference
RCCEx Exported Types

RCC extended clocks structure definition. More...

#include <stm32wbxx_hal_rcc_ex.h>

Data Fields

uint32_t | PeriphClockSelection
RCC_PLLSAI1InitTypeDef PLLSAI1
uint32_t | Usart1ClockSelection
uint32_t | Lpuart1ClockSelection
uint32_t | I2c1ClockSelection
uint32_t | I2c3ClockSelection
uint32_t | Lptim1ClockSelection
uint32_t | Lptim2ClockSelection
uint32_t | Sai1ClockSelection
uint32_t | UsbClockSelection
uint32_t | RngClockSelection
uint32_t | AdcClockSelection
uint32_t | RTCClockSelection
uint32_t | RFWakeUpClockSelection
uint32_t | SmpsClockSelection
uint32_t | SmpsDivSelection

Detailed Description

RCC extended clocks structure definition.

Definition at line 264 of file stm32wbxx_hal_rcc_ex.h.

Field Documentation

uint32_t RCC_PeriphCLKInitTypeDef::AdcClockSelection

Specifies ADC interface clock source. This parameter can be a value of ADC Clock Source

Definition at line 309 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::I2c1ClockSelection

Specifies I2C1 clock source. This parameter can be a value of I2C1 Clock Source

Definition at line 283 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::I2c3ClockSelection

Specifies I2C3 clock source. This parameter can be a value of I2C3 Clock Source

Definition at line 287 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Lptim1ClockSelection

Specifies LPTIM1 clock source. This parameter can be a value of LPTIM1 Clock Source

Definition at line 291 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Lptim2ClockSelection

Specifies LPTIM2 clock source. This parameter can be a value of LPTIM2 Clock Source

Definition at line 294 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Lpuart1ClockSelection

Specifies LPUART1 clock source. This parameter can be a value of LPUART1 Clock Source

Definition at line 279 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::PeriphClockSelection

The Extended Clock to be configured. This parameter can be a value of Periph Clock Selection

Definition at line 266 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

RCC_PLLSAI1InitTypeDef RCC_PeriphCLKInitTypeDef::PLLSAI1

PLLSAI1 structure parameters. This parameter will be used only when PLLSAI1 is selected as Clock Source for SAI, USB/RNG or ADC

Definition at line 270 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::RFWakeUpClockSelection

Specifies RF Wake-up clock source. This parameter can be a value of RF WKP Clock Source

Definition at line 315 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::RngClockSelection

Specifies RNG clock source (warning: same source for USB). This parameter can be a value of RNG Clock Source

Definition at line 305 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::RTCClockSelection

Specifies RTC clock source (also used for LCD). This parameter can be a value of RTC Clock Source

Definition at line 312 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Sai1ClockSelection

Specifies SAI1 clock source. This parameter can be a value of SAI1 Clock Source

Definition at line 298 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::SmpsClockSelection

Specifies SMPS clock source. This parameter can be a value of SMPS Clock Source

Definition at line 319 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::SmpsDivSelection

Specifies SMPS clock division factor. This parameter can be a value of SMPS Clock Division Factor

Definition at line 322 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::Usart1ClockSelection

Specifies USART1 clock source. This parameter can be a value of USART1 Clock Source

Definition at line 275 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::UsbClockSelection

Specifies USB clock source (warning: same source for RNG). This parameter can be a value of USB Clock Source

Definition at line 302 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_rcc_ex.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RCC_CRSInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_CRSInitTypeDef Struct Reference
RCCEx Exported Types

RCC_CRS Init structure definition. More...

#include <stm32wbxx_hal_rcc_ex.h>

Data Fields

uint32_t | Prescaler
uint32_t | Source
uint32_t | Polarity
uint32_t | ReloadValue
uint32_t | ErrorLimitValue
uint32_t | HSI48CalibrationValue

Detailed Description

RCC_CRS Init structure definition.

Definition at line 332 of file stm32wbxx_hal_rcc_ex.h.

Field Documentation

uint32_t RCC_CRSInitTypeDef::ErrorLimitValue

Specifies the value to be used to evaluate the captured frequency error value. This parameter must be a number between Min_Data=0 and Max_Data=0xFF or a value of RCCEx CRS ErrorLimitDefault

Definition at line 347 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

uint32_t RCC_CRSInitTypeDef::HSI48CalibrationValue

Specifies a user-programmable trimming value to the HSI48 oscillator. This parameter must be a number between Min_Data=0 and Max_Data=0x3F or a value of RCCEx CRS HSI48CalibrationDefault

Definition at line 350 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

uint32_t RCC_CRSInitTypeDef::Polarity

Specifies the input polarity for the SYNC signal source. This parameter can be a value of RCCEx CRS SynchroPolarity

Definition at line 340 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

uint32_t RCC_CRSInitTypeDef::Prescaler

Specifies the division factor of the SYNC signal. This parameter can be a value of RCCEx CRS SynchroDivider

Definition at line 334 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

uint32_t RCC_CRSInitTypeDef::ReloadValue

Specifies the value to be loaded in the frequency error counter with each SYNC event. It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) This parameter must be a number between Min_Data=0 and Max_Data=0xFFFF or a value of RCCEx CRS ReloadValueDefault .

Definition at line 343 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

uint32_t RCC_CRSInitTypeDef::Source

Specifies the SYNC signal source. This parameter can be a value of RCCEx CRS SynchroSource

Definition at line 337 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_rcc_ex.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RCC_CRSSynchroInfoTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_CRSSynchroInfoTypeDef Struct Reference
RCCEx Exported Types

RCC_CRS Synchronization structure definition. More...

#include <stm32wbxx_hal_rcc_ex.h>

Data Fields

uint32_t | ReloadValue
uint32_t | HSI48CalibrationValue
uint32_t | FreqErrorCapture
uint32_t | FreqErrorDirection

Detailed Description

RCC_CRS Synchronization structure definition.

Definition at line 358 of file stm32wbxx_hal_rcc_ex.h.

Field Documentation

uint32_t RCC_CRSSynchroInfoTypeDef::FreqErrorCapture

Specifies the value loaded in the .FECAP, the frequency error counter value latched in the time of the last SYNC event. This parameter must be a number between Min_Data=0 and Max_Data=0xFFFF

Definition at line 366 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSGetSynchronizationInfo().

uint32_t RCC_CRSSynchroInfoTypeDef::FreqErrorDirection

Specifies the value loaded in the .FEDIR, the counting direction of the frequency error counter latched in the time of the last SYNC event. It shows whether the actual frequency is below or above the target. This parameter must be a value of RCCEx CRS FreqErrorDirection

Definition at line 370 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSGetSynchronizationInfo().

uint32_t RCC_CRSSynchroInfoTypeDef::HSI48CalibrationValue

Specifies value loaded in HSI48 oscillator smooth trimming. This parameter must be a number between Min_Data=0 and Max_Data=0x3F

Definition at line 363 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSGetSynchronizationInfo().

uint32_t RCC_CRSSynchroInfoTypeDef::ReloadValue

Specifies the value loaded in the Counter reload value. This parameter must be a number between Min_Data=0 and Max_Data=0xFFFF

Definition at line 360 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSGetSynchronizationInfo().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_rcc_ex.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LSCO Index

Defines
LSCO Index
RCCEx Exported Constants

Defines

#define | RCC_LSCO1 0x00000000U
#define | RCC_LSCO2 0x00000001U
#define | RCC_LSCO3 0x00000002U

Define Documentation

#define RCC_LSCO1 0x00000000U

LSCO1 index

Definition at line 390 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_LSCOConfig().

#define RCC_LSCO2 0x00000001U

LSCO2 index

Definition at line 391 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_LSCOConfig().

#define RCC_LSCO3 0x00000002U

LSCO3 index

Definition at line 392 of file stm32wbxx_hal_rcc_ex.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Low Speed Clock Source

Defines
Low Speed Clock Source
RCCEx Exported Constants

Defines

#define | RCC_LSCOSOURCE_LSI LL_RCC_LSCO_CLKSOURCE_LSI
#define | RCC_LSCOSOURCE_LSE LL_RCC_LSCO_CLKSOURCE_LSE

Define Documentation

#define RCC_LSCOSOURCE_LSE LL_RCC_LSCO_CLKSOURCE_LSE

LSE selection for low speed clock output

Definition at line 402 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_LSCOSOURCE_LSI LL_RCC_LSCO_CLKSOURCE_LSI

LSI selection for low speed clock output

Definition at line 401 of file stm32wbxx_hal_rcc_ex.h.

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STM32WB55xx HAL User Manual: Periph Clock Selection

Defines
Periph Clock Selection
RCCEx Exported Constants

Defines

#define | RCC_PERIPHCLK_USART1 0x00000001U
#define | RCC_PERIPHCLK_LPUART1 0x00000002U
#define | RCC_PERIPHCLK_I2C1 0x00000004U
#define | RCC_PERIPHCLK_I2C3 0x00000008U
#define | RCC_PERIPHCLK_LPTIM1 0x00000010U
#define | RCC_PERIPHCLK_LPTIM2 0x00000020U
#define | RCC_PERIPHCLK_SAI1 0x00000040U
#define | RCC_PERIPHCLK_CLK48SEL 0x00000100U
#define | RCC_PERIPHCLK_USB RCC_PERIPHCLK_CLK48SEL
#define | RCC_PERIPHCLK_RNG 0x00000200U
#define | RCC_PERIPHCLK_ADC 0x00000400U
#define | RCC_PERIPHCLK_RTC 0x00000800U
#define | RCC_PERIPHCLK_RFWAKEUP 0x00001000U
#define | RCC_PERIPHCLK_SMPS 0x00002000U

Define Documentation

#define RCC_PERIPHCLK_ADC 0x00000400U

ADC Peripheral Clock Selection

Definition at line 426 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_CLK48SEL 0x00000100U

48 MHz clock source selection

Definition at line 423 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_PERIPHCLK_I2C1 0x00000004U

I2C1 Peripheral Clock Selection

Definition at line 414 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_I2C3 0x00000008U

I2C3 Peripheral Clock Selection

Definition at line 416 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_LPTIM1 0x00000010U

LPTIM1 Peripheral Clock Selection

Definition at line 418 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_LPTIM2 0x00000020U

LPTIM2 Peripheral Clock Selection

Definition at line 419 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_LPUART1 0x00000002U

LPUART1 Peripheral Clock Selection

Definition at line 412 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_RFWAKEUP 0x00001000U

RF Wakeup Peripheral Clock Selection

Definition at line 428 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_RNG 0x00000200U

RNG Peripheral Clock Selection

Definition at line 425 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_RTC 0x00000800U

RTC Peripheral Clock Selection

Definition at line 427 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_SAI1 0x00000040U

SAI1 Peripheral Clock Selection

Definition at line 421 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), HAL_RCCEx_PeriphCLKConfig(), and HAL_SAI_Init().

#define RCC_PERIPHCLK_SMPS 0x00002000U

SMPS Peripheral Clock Selection

Definition at line 430 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_USART1 0x00000001U

USART1 Peripheral Clock Selection

Definition at line 410 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_USB RCC_PERIPHCLK_CLK48SEL

USB Peripheral Clock Selection

Definition at line 424 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: USART1 Clock Source

Defines
USART1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_USART1CLKSOURCE_PCLK2 LL_RCC_USART1_CLKSOURCE_PCLK2
#define | RCC_USART1CLKSOURCE_SYSCLK LL_RCC_USART1_CLKSOURCE_SYSCLK
#define | RCC_USART1CLKSOURCE_HSI LL_RCC_USART1_CLKSOURCE_HSI
#define | RCC_USART1CLKSOURCE_LSE LL_RCC_USART1_CLKSOURCE_LSE

Define Documentation

#define RCC_USART1CLKSOURCE_HSI LL_RCC_USART1_CLKSOURCE_HSI

HSI clock selected as USART 1 clock

Definition at line 441 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_USART1CLKSOURCE_LSE LL_RCC_USART1_CLKSOURCE_LSE

LSE clock selected as USART 1 clock

Definition at line 442 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_USART1CLKSOURCE_PCLK2 LL_RCC_USART1_CLKSOURCE_PCLK2

APB2 clock selected as USART 1 clock

Definition at line 439 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_USART1CLKSOURCE_SYSCLK LL_RCC_USART1_CLKSOURCE_SYSCLK

SYSCLK clock selected as USART 1 clock

Definition at line 440 of file stm32wbxx_hal_rcc_ex.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPUART1 Clock Source

Defines
LPUART1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_LPUART1CLKSOURCE_PCLK1 LL_RCC_LPUART1_CLKSOURCE_PCLK1
#define | RCC_LPUART1CLKSOURCE_SYSCLK LL_RCC_LPUART1_CLKSOURCE_SYSCLK
#define | RCC_LPUART1CLKSOURCE_HSI LL_RCC_LPUART1_CLKSOURCE_HSI
#define | RCC_LPUART1CLKSOURCE_LSE LL_RCC_LPUART1_CLKSOURCE_LSE

Define Documentation

#define RCC_LPUART1CLKSOURCE_HSI LL_RCC_LPUART1_CLKSOURCE_HSI

HSI clock selected as LPUART 1 clock

Definition at line 453 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_LPUART1CLKSOURCE_LSE LL_RCC_LPUART1_CLKSOURCE_LSE

LSE clock selected as LPUART 1 clock

Definition at line 454 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_LPUART1CLKSOURCE_PCLK1 LL_RCC_LPUART1_CLKSOURCE_PCLK1

APB1 clock selected as LPUART 1 clock

Definition at line 451 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_LPUART1CLKSOURCE_SYSCLK LL_RCC_LPUART1_CLKSOURCE_SYSCLK

SYSCLK clock selected as LPUART 1 clock

Definition at line 452 of file stm32wbxx_hal_rcc_ex.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: I2C1 Clock Source

Defines
I2C1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_I2C1CLKSOURCE_PCLK1 LL_RCC_I2C1_CLKSOURCE_PCLK1
#define | RCC_I2C1CLKSOURCE_SYSCLK LL_RCC_I2C1_CLKSOURCE_SYSCLK
#define | RCC_I2C1CLKSOURCE_HSI LL_RCC_I2C1_CLKSOURCE_HSI

Define Documentation

#define RCC_I2C1CLKSOURCE_HSI LL_RCC_I2C1_CLKSOURCE_HSI

HSI clock selected as I2C1 clock

Definition at line 465 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_I2C1CLKSOURCE_PCLK1 LL_RCC_I2C1_CLKSOURCE_PCLK1

APB1 clock selected as I2C1 clock

Definition at line 463 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_I2C1CLKSOURCE_SYSCLK LL_RCC_I2C1_CLKSOURCE_SYSCLK

SYSCLK clock selected as I2C1 clock

Definition at line 464 of file stm32wbxx_hal_rcc_ex.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: I2C3 Clock Source

Defines
I2C3 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_I2C3CLKSOURCE_PCLK1 LL_RCC_I2C3_CLKSOURCE_PCLK1
#define | RCC_I2C3CLKSOURCE_SYSCLK LL_RCC_I2C3_CLKSOURCE_SYSCLK
#define | RCC_I2C3CLKSOURCE_HSI LL_RCC_I2C3_CLKSOURCE_HSI

Define Documentation

#define RCC_I2C3CLKSOURCE_HSI LL_RCC_I2C3_CLKSOURCE_HSI

HSI clock selected as I2C3 clock

Definition at line 476 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_I2C3CLKSOURCE_PCLK1 LL_RCC_I2C3_CLKSOURCE_PCLK1

APB1 clock selected as I2C3 clock

Definition at line 474 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_I2C3CLKSOURCE_SYSCLK LL_RCC_I2C3_CLKSOURCE_SYSCLK

SYSCLK clock selected as I2C3 clock

Definition at line 475 of file stm32wbxx_hal_rcc_ex.h.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAI1 Clock Source

Defines
SAI1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_SAI1CLKSOURCE_PLLSAI1 LL_RCC_SAI1_CLKSOURCE_PLLSAI1
#define | RCC_SAI1CLKSOURCE_PLL LL_RCC_SAI1_CLKSOURCE_PLL
#define | RCC_SAI1CLKSOURCE_HSI LL_RCC_SAI1_CLKSOURCE_HSI
#define | RCC_SAI1CLKSOURCE_PIN LL_RCC_SAI1_CLKSOURCE_PIN

Define Documentation

#define RCC_SAI1CLKSOURCE_HSI LL_RCC_SAI1_CLKSOURCE_HSI

HSI clock selected as SAI1 clock

Definition at line 488 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI1CLKSOURCE_PIN LL_RCC_SAI1_CLKSOURCE_PIN

External PIN clock selected as SAI1 clock

Definition at line 489 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI1CLKSOURCE_PLL LL_RCC_SAI1_CLKSOURCE_PLL

PLL "P" clock selected as SAI1 clock

Definition at line 487 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_SAI1CLKSOURCE_PLLSAI1 LL_RCC_SAI1_CLKSOURCE_PLLSAI1

PLLSAI "P" clock selected as SAI1 clock

Definition at line 486 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPTIM1 Clock Source

Defines
LPTIM1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_LPTIM1CLKSOURCE_PCLK1 LL_RCC_LPTIM1_CLKSOURCE_PCLK1
#define | RCC_LPTIM1CLKSOURCE_LSI LL_RCC_LPTIM1_CLKSOURCE_LSI
#define | RCC_LPTIM1CLKSOURCE_HSI LL_RCC_LPTIM1_CLKSOURCE_HSI
#define | RCC_LPTIM1CLKSOURCE_LSE LL_RCC_LPTIM1_CLKSOURCE_LSE

Define Documentation

#define RCC_LPTIM1CLKSOURCE_HSI LL_RCC_LPTIM1_CLKSOURCE_HSI

HSI clock selected as LPTIM1 clock

Definition at line 500 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_LPTIM1CLKSOURCE_LSE LL_RCC_LPTIM1_CLKSOURCE_LSE

LSE clock selected as LPTIM1 clock

Definition at line 501 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_LPTIM1CLKSOURCE_LSI LL_RCC_LPTIM1_CLKSOURCE_LSI

LSI clock selected as LPTIM1 clock

Definition at line 499 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_LPTIM1CLKSOURCE_PCLK1 LL_RCC_LPTIM1_CLKSOURCE_PCLK1

APB1 clock selected as LPTIM1 clock

Definition at line 498 of file stm32wbxx_hal_rcc_ex.h.

Referenced by LPTIM_Disable().

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: LPTIM2 Clock Source

Defines
LPTIM2 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_LPTIM2CLKSOURCE_PCLK1 LL_RCC_LPTIM2_CLKSOURCE_PCLK1
#define | RCC_LPTIM2CLKSOURCE_LSI LL_RCC_LPTIM2_CLKSOURCE_LSI
#define | RCC_LPTIM2CLKSOURCE_HSI LL_RCC_LPTIM2_CLKSOURCE_HSI
#define | RCC_LPTIM2CLKSOURCE_LSE LL_RCC_LPTIM2_CLKSOURCE_LSE

Define Documentation

#define RCC_LPTIM2CLKSOURCE_HSI LL_RCC_LPTIM2_CLKSOURCE_HSI

HSI clock selected as LPTIM2 clock

Definition at line 511 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_LPTIM2CLKSOURCE_LSE LL_RCC_LPTIM2_CLKSOURCE_LSE

LSE clock selected as LPTIM2 clock

Definition at line 512 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_LPTIM2CLKSOURCE_LSI LL_RCC_LPTIM2_CLKSOURCE_LSI

LSI clock selected as LPTIM2 clock

Definition at line 510 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_LPTIM2CLKSOURCE_PCLK1 LL_RCC_LPTIM2_CLKSOURCE_PCLK1

APB1 clock selected as LPTIM2 clock

Definition at line 509 of file stm32wbxx_hal_rcc_ex.h.

Referenced by LPTIM_Disable().

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STM32WB55xx HAL User Manual: RNG Clock Source

Defines
RNG Clock Source
RCCEx Exported Constants

Defines

#define | RCC_RNGCLKSOURCE_HSI48 (CLK48_MASK | LL_RCC_CLK48_CLKSOURCE_HSI48)
#define | RCC_RNGCLKSOURCE_PLL (CLK48_MASK | LL_RCC_CLK48_CLKSOURCE_PLL)
#define | RCC_RNGCLKSOURCE_MSI (CLK48_MASK | LL_RCC_CLK48_CLKSOURCE_MSI)
#define | RCC_RNGCLKSOURCE_CLK48 LL_RCC_RNG_CLKSOURCE_CLK48
#define | RCC_RNGCLKSOURCE_LSI LL_RCC_RNG_CLKSOURCE_LSI
#define | RCC_RNGCLKSOURCE_LSE LL_RCC_RNG_CLKSOURCE_LSE

Define Documentation

#define RCC_RNGCLKSOURCE_CLK48 LL_RCC_RNG_CLKSOURCE_CLK48

CLK48 divided by 3 selected as RNG Clock

Definition at line 523 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetRngCLKSource().

#define RCC_RNGCLKSOURCE_HSI48 (CLK48_MASK | LL_RCC_CLK48_CLKSOURCE_HSI48)

HSI48 clock divided by 3 selected as RNG clock

Definition at line 520 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_RNGCLKSOURCE_LSE LL_RCC_RNG_CLKSOURCE_LSE

LSE clock selected as RNG clock

Definition at line 525 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_RNGCLKSOURCE_LSI LL_RCC_RNG_CLKSOURCE_LSI

LSI clock selected as RNG clock

Definition at line 524 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_RNGCLKSOURCE_MSI (CLK48_MASK | LL_RCC_CLK48_CLKSOURCE_MSI)

MSI clock divided by 3 selected as RNG clock

Definition at line 522 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_RNGCLKSOURCE_PLL (CLK48_MASK | LL_RCC_CLK48_CLKSOURCE_PLL)

PLL "Q" clock divided by 3 selected as RNG clock

Definition at line 521 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

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STM32WB55xx HAL User Manual: USB Clock Source

Defines
USB Clock Source
RCCEx Exported Constants

Defines

#define | RCC_USBCLKSOURCE_HSI48 LL_RCC_USB_CLKSOURCE_HSI48
#define | RCC_USBCLKSOURCE_PLLSAI1 LL_RCC_USB_CLKSOURCE_PLLSAI1
#define | RCC_USBCLKSOURCE_PLL LL_RCC_USB_CLKSOURCE_PLL
#define | RCC_USBCLKSOURCE_MSI LL_RCC_USB_CLKSOURCE_MSI

Define Documentation

#define RCC_USBCLKSOURCE_HSI48 LL_RCC_USB_CLKSOURCE_HSI48

HSI48 clock selected as USB clock

Definition at line 533 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_USBCLKSOURCE_MSI LL_RCC_USB_CLKSOURCE_MSI

MSI clock selected as USB clock

Definition at line 536 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_USBCLKSOURCE_PLL LL_RCC_USB_CLKSOURCE_PLL

PLL "Q" clock selected as USB clock

Definition at line 535 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_USBCLKSOURCE_PLLSAI1 LL_RCC_USB_CLKSOURCE_PLLSAI1

PLLSAI1 "Q" clock selected as USB clock

Definition at line 534 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

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STM32WB55xx HAL User Manual: ADC Clock Source

Defines
ADC Clock Source
RCCEx Exported Constants

Defines

#define | RCC_ADCCLKSOURCE_NONE LL_RCC_ADC_CLKSOURCE_NONE
#define | RCC_ADCCLKSOURCE_PLLSAI1 LL_RCC_ADC_CLKSOURCE_PLLSAI1
#define | RCC_ADCCLKSOURCE_PLL LL_RCC_ADC_CLKSOURCE_PLL
#define | RCC_ADCCLKSOURCE_SYSCLK LL_RCC_ADC_CLKSOURCE_SYSCLK

Define Documentation

#define RCC_ADCCLKSOURCE_NONE LL_RCC_ADC_CLKSOURCE_NONE

None clock selected as ADC clock

Definition at line 545 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_ADCCLKSOURCE_PLL LL_RCC_ADC_CLKSOURCE_PLL

PLL "P" clock selected as ADC clock

Definition at line 549 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_ADCCLKSOURCE_PLLSAI1 LL_RCC_ADC_CLKSOURCE_PLLSAI1

PLLSAI1 "R" clock selected as ADC clock

Definition at line 547 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define RCC_ADCCLKSOURCE_SYSCLK LL_RCC_ADC_CLKSOURCE_SYSCLK

SYSCLK clock selected as ADC clock

Definition at line 550 of file stm32wbxx_hal_rcc_ex.h.

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STM32WB55xx HAL User Manual: HCLK RF Clock Source

Defines
HCLK RF Clock Source
RCCEx Exported Constants

Defines

#define | RCC_HCLK5SOURCE_HSI 0x00000001U
#define | RCC_HCLK5SOURCE_HSE 0x00000002U

Define Documentation

#define RCC_HCLK5SOURCE_HSE 0x00000002U

HSE clock divided by 2 selected as Radio Domain clock

Definition at line 561 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_HCLK5SOURCE_HSI 0x00000001U

HSI clock not divided selected as Radio Domain clock

Definition at line 560 of file stm32wbxx_hal_rcc_ex.h.

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STM32WB55xx HAL User Manual: RF WKP Clock Source

Defines
RF WKP Clock Source
RCCEx Exported Constants

Defines

#define | RCC_RFWKPCLKSOURCE_NONE LL_RCC_RFWKP_CLKSOURCE_NONE
#define | RCC_RFWKPCLKSOURCE_LSE LL_RCC_RFWKP_CLKSOURCE_LSE
#define | RCC_RFWKPCLKSOURCE_LSI LL_RCC_RFWKP_CLKSOURCE_LSI
#define | RCC_RFWKPCLKSOURCE_HSE_DIV1024 LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024

Define Documentation

#define RCC_RFWKPCLKSOURCE_HSE_DIV1024 LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024

HSE clock divided by 1024 selected as RF system wakeup clock

Definition at line 574 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_RFWKPCLKSOURCE_LSE LL_RCC_RFWKP_CLKSOURCE_LSE

LSE clock selected as RF system wakeup clock

Definition at line 572 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_RFWKPCLKSOURCE_LSI LL_RCC_RFWKP_CLKSOURCE_LSI

LSI clock selected as RF system wakeup clock

Definition at line 573 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_RFWKPCLKSOURCE_NONE LL_RCC_RFWKP_CLKSOURCE_NONE

None clock selected as RF system wakeup clock

Definition at line 571 of file stm32wbxx_hal_rcc_ex.h.

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STM32WB55xx HAL User Manual: SMPS Clock Source

Defines
SMPS Clock Source
RCCEx Exported Constants

Defines

#define | RCC_SMPSCLKSOURCE_HSI LL_RCC_SMPS_CLKSOURCE_HSI
#define | RCC_SMPSCLKSOURCE_MSI LL_RCC_SMPS_CLKSOURCE_MSI
#define | RCC_SMPSCLKSOURCE_HSE LL_RCC_SMPS_CLKSOURCE_HSE

Define Documentation

#define RCC_SMPSCLKSOURCE_HSE LL_RCC_SMPS_CLKSOURCE_HSE

HSE selection as smps clock

Definition at line 587 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_SMPSCLKSOURCE_HSI LL_RCC_SMPS_CLKSOURCE_HSI

HSI selection as smps clock

Definition at line 585 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_SMPSCLKSOURCE_MSI LL_RCC_SMPS_CLKSOURCE_MSI

MSI selection as smps clock

Definition at line 586 of file stm32wbxx_hal_rcc_ex.h.

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STM32WB55xx HAL User Manual: SMPS Clock Division Factor

Defines
SMPS Clock Division Factor
RCCEx Exported Constants

Defines

#define | RCC_SMPSCLKDIV_RANGE0 LL_RCC_SMPS_DIV_0
#define | RCC_SMPSCLKDIV_RANGE1 LL_RCC_SMPS_DIV_1
#define | RCC_SMPSCLKDIV_RANGE2 LL_RCC_SMPS_DIV_2
#define | RCC_SMPSCLKDIV_RANGE3 LL_RCC_SMPS_DIV_3

Define Documentation

#define RCC_SMPSCLKDIV_RANGE0 LL_RCC_SMPS_DIV_0

PLLM division factor = 0

Definition at line 605 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_SMPSCLKDIV_RANGE1 LL_RCC_SMPS_DIV_1

PLLM division factor = 1

Definition at line 606 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_SMPSCLKDIV_RANGE2 LL_RCC_SMPS_DIV_2

PLLM division factor = 2

Definition at line 607 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_SMPSCLKDIV_RANGE3 LL_RCC_SMPS_DIV_3

PLLM division factor = 3

Definition at line 608 of file stm32wbxx_hal_rcc_ex.h.

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STM32WB55xx HAL User Manual: RCC LSE CSS external interrupt line

Defines
RCC LSE CSS external interrupt line
RCCEx Exported Constants

Defines

#define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM18

Define Documentation

#define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM18

External interrupt line 18 connected to the LSE CSS EXTI Line

Definition at line 617 of file stm32wbxx_hal_rcc_ex.h.

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STM32WB55xx HAL User Manual: RCCEx CRS Status

Defines
RCCEx CRS Status
RCCEx Exported Constants

Defines

#define | RCC_CRS_NONE 0x00000000U
#define | RCC_CRS_TIMEOUT 0x00000001U
#define | RCC_CRS_SYNCOK 0x00000002U
#define | RCC_CRS_SYNCWARN 0x00000004U
#define | RCC_CRS_SYNCERR 0x00000008U
#define | RCC_CRS_SYNCMISS 0x00000010U
#define | RCC_CRS_TRIMOVF 0x00000020U

Define Documentation

#define RCC_CRS_NONE 0x00000000U

CRS status none

Definition at line 628 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_SYNCERR 0x00000008U

CRS status synchronization error

Definition at line 632 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_SYNCMISS 0x00000010U

CRS status synchronization missed

Definition at line 633 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_SYNCOK 0x00000002U

CRS status synchronization success

Definition at line 630 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_SYNCWARN 0x00000004U

CRS status synchronization warning

Definition at line 631 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_TIMEOUT 0x00000001U

CRS status timeout

Definition at line 629 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_TRIMOVF 0x00000020U

CRS status trimming overflow or underflow

Definition at line 634 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

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STM32WB55xx HAL User Manual: RCCEx CRS SynchroSource

Defines
RCCEx CRS SynchroSource
RCCEx Exported Constants

Defines

#define | RCC_CRS_SYNC_SOURCE_GPIO LL_CRS_SYNC_SOURCE_GPIO
#define | RCC_CRS_SYNC_SOURCE_LSE LL_CRS_SYNC_SOURCE_LSE
#define | RCC_CRS_SYNC_SOURCE_USB LL_CRS_SYNC_SOURCE_USB

Define Documentation

#define RCC_CRS_SYNC_SOURCE_GPIO LL_CRS_SYNC_SOURCE_GPIO

Synchro Signal source GPIO

Definition at line 642 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_SOURCE_LSE LL_CRS_SYNC_SOURCE_LSE

Synchro Signal source LSE

Definition at line 643 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_SOURCE_USB LL_CRS_SYNC_SOURCE_USB

Synchro Signal source USB SOF (default)

Definition at line 644 of file stm32wbxx_hal_rcc_ex.h.

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STM32WB55xx HAL User Manual: RCCEx CRS SynchroDivider

Defines
RCCEx CRS SynchroDivider
RCCEx Exported Constants

Defines

#define | RCC_CRS_SYNC_DIV1 LL_CRS_SYNC_DIV_1
#define | RCC_CRS_SYNC_DIV2 LL_CRS_SYNC_DIV_2
#define | RCC_CRS_SYNC_DIV4 LL_CRS_SYNC_DIV_4
#define | RCC_CRS_SYNC_DIV8 LL_CRS_SYNC_DIV_8
#define | RCC_CRS_SYNC_DIV16 LL_CRS_SYNC_DIV_16
#define | RCC_CRS_SYNC_DIV32 LL_CRS_SYNC_DIV_32
#define | RCC_CRS_SYNC_DIV64 LL_CRS_SYNC_DIV_64
#define | RCC_CRS_SYNC_DIV128 LL_CRS_SYNC_DIV_128

Define Documentation

#define RCC_CRS_SYNC_DIV1 LL_CRS_SYNC_DIV_1

Synchro Signal not divided (default)

Definition at line 652 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_DIV128 LL_CRS_SYNC_DIV_128

Synchro Signal divided by 128

Definition at line 659 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_DIV16 LL_CRS_SYNC_DIV_16

Synchro Signal divided by 16

Definition at line 656 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_DIV2 LL_CRS_SYNC_DIV_2

Synchro Signal divided by 2

Definition at line 653 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_DIV32 LL_CRS_SYNC_DIV_32

Synchro Signal divided by 32

Definition at line 657 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_DIV4 LL_CRS_SYNC_DIV_4

Synchro Signal divided by 4

Definition at line 654 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_DIV64 LL_CRS_SYNC_DIV_64

Synchro Signal divided by 64

Definition at line 658 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_DIV8 LL_CRS_SYNC_DIV_8

Synchro Signal divided by 8

Definition at line 655 of file stm32wbxx_hal_rcc_ex.h.

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STM32WB55xx HAL User Manual: RCCEx CRS SynchroPolarity

Defines
RCCEx CRS SynchroPolarity
RCCEx Exported Constants

Defines

#define | RCC_CRS_SYNC_POLARITY_RISING LL_CRS_SYNC_POLARITY_RISING
#define | RCC_CRS_SYNC_POLARITY_FALLING LL_CRS_SYNC_POLARITY_FALLING

Define Documentation

#define RCC_CRS_SYNC_POLARITY_FALLING LL_CRS_SYNC_POLARITY_FALLING

Synchro Active on falling edge

Definition at line 668 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_CRS_SYNC_POLARITY_RISING LL_CRS_SYNC_POLARITY_RISING

Synchro Active on rising edge (default)

Definition at line 667 of file stm32wbxx_hal_rcc_ex.h.

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STM32WB55xx HAL User Manual: RCCEx CRS ReloadValueDefault

Defines
RCCEx CRS ReloadValueDefault
RCCEx Exported Constants

Defines

#define RCC_CRS_RELOADVALUE_DEFAULT LL_CRS_RELOADVALUE_DEFAULT

Define Documentation

#define RCC_CRS_RELOADVALUE_DEFAULT LL_CRS_RELOADVALUE_DEFAULT

The reset value of the RELOAD field corresponds to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB).

Definition at line 676 of file stm32wbxx_hal_rcc_ex.h.

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STM32WB55xx HAL User Manual: RCCEx CRS ErrorLimitDefault

Defines
RCCEx CRS ErrorLimitDefault
RCCEx Exported Constants

Defines

#define RCC_CRS_ERRORLIMIT_DEFAULT LL_CRS_ERRORLIMIT_DEFAULT

Define Documentation

#define RCC_CRS_ERRORLIMIT_DEFAULT LL_CRS_ERRORLIMIT_DEFAULT

Default Frequency error limit

Definition at line 685 of file stm32wbxx_hal_rcc_ex.h.

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STM32WB55xx HAL User Manual: RCCEx CRS HSI48CalibrationDefault

Defines
RCCEx CRS HSI48CalibrationDefault
RCCEx Exported Constants

Defines

#define RCC_CRS_HSI48CALIBRATION_DEFAULT LL_CRS_HSI48CALIBRATION_DEFAULT

Define Documentation

#define RCC_CRS_HSI48CALIBRATION_DEFAULT LL_CRS_HSI48CALIBRATION_DEFAULT

The default value is 32, which corresponds to the middle of the trimming interval. The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value corresponds to a higher output frequency

Definition at line 693 of file stm32wbxx_hal_rcc_ex.h.

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STM32WB55xx HAL User Manual: RCCEx CRS FreqErrorDirection

Defines
RCCEx CRS FreqErrorDirection
RCCEx Exported Constants

Defines

#define | RCC_CRS_FREQERRORDIR_UP LL_CRS_FREQ_ERROR_DIR_UP
#define | RCC_CRS_FREQERRORDIR_DOWN LL_CRS_FREQ_ERROR_DIR_DOWN

Define Documentation

#define RCC_CRS_FREQERRORDIR_DOWN LL_CRS_FREQ_ERROR_DIR_DOWN

Downcounting direction, the actual frequency is below the target

Definition at line 704 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_CRS_FREQERRORDIR_UP LL_CRS_FREQ_ERROR_DIR_UP

Upcounting direction, the actual frequency is above the target

Definition at line 703 of file stm32wbxx_hal_rcc_ex.h.

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STM32WB55xx HAL User Manual: RCCEx CRS Interrupt Sources

Defines
RCCEx CRS Interrupt Sources
RCCEx Exported Constants

Defines

#define | RCC_CRS_IT_SYNCOK LL_CRS_CR_SYNCOKIE
#define | RCC_CRS_IT_SYNCWARN LL_CRS_CR_SYNCWARNIE
#define | RCC_CRS_IT_ERR LL_CRS_CR_ERRIE
#define | RCC_CRS_IT_ESYNC LL_CRS_CR_ESYNCIE
#define | RCC_CRS_IT_SYNCERR LL_CRS_CR_ERRIE
#define | RCC_CRS_IT_SYNCMISS LL_CRS_CR_ERRIE
#define | RCC_CRS_IT_TRIMOVF LL_CRS_CR_ERRIE

Define Documentation

#define RCC_CRS_IT_ERR LL_CRS_CR_ERRIE

Error

Definition at line 714 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler().

#define RCC_CRS_IT_ESYNC LL_CRS_CR_ESYNCIE

Expected SYNC

Definition at line 715 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler().

#define RCC_CRS_IT_SYNCERR LL_CRS_CR_ERRIE

SYNC error

Definition at line 716 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_CRS_IT_SYNCMISS LL_CRS_CR_ERRIE

SYNC missed

Definition at line 717 of file stm32wbxx_hal_rcc_ex.h.

#define RCC_CRS_IT_SYNCOK LL_CRS_CR_SYNCOKIE

SYNC event OK

Definition at line 712 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler().

#define RCC_CRS_IT_SYNCWARN LL_CRS_CR_SYNCWARNIE

SYNC warning

Definition at line 713 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler().

#define RCC_CRS_IT_TRIMOVF LL_CRS_CR_ERRIE

Trimming overflow or underflow

Definition at line 718 of file stm32wbxx_hal_rcc_ex.h.

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STM32WB55xx HAL User Manual: RCCEx CRS Flags

Defines
RCCEx CRS Flags
RCCEx Exported Constants

Defines

#define | RCC_CRS_FLAG_SYNCOK LL_CRS_ISR_SYNCOKF
#define | RCC_CRS_FLAG_SYNCWARN LL_CRS_ISR_SYNCWARNF
#define | RCC_CRS_FLAG_ERR LL_CRS_ISR_ERRF
#define | RCC_CRS_FLAG_ESYNC LL_CRS_ISR_ESYNCF
#define | RCC_CRS_FLAG_SYNCERR LL_CRS_ISR_SYNCERR
#define | RCC_CRS_FLAG_SYNCMISS LL_CRS_ISR_SYNCMISS
#define | RCC_CRS_FLAG_TRIMOVF LL_CRS_ISR_TRIMOVF

Define Documentation

#define RCC_CRS_FLAG_ERR LL_CRS_ISR_ERRF

Error flag

Definition at line 729 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler().

#define RCC_CRS_FLAG_ESYNC LL_CRS_ISR_ESYNCF

Expected SYNC flag

Definition at line 730 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_FLAG_SYNCERR LL_CRS_ISR_SYNCERR

SYNC error

Definition at line 731 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_FLAG_SYNCMISS LL_CRS_ISR_SYNCMISS

SYNC missed

Definition at line 732 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_FLAG_SYNCOK LL_CRS_ISR_SYNCOKF

SYNC event OK flag

Definition at line 727 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_FLAG_SYNCWARN LL_CRS_ISR_SYNCWARNF

SYNC warning flag

Definition at line 728 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

#define RCC_CRS_FLAG_TRIMOVF LL_CRS_ISR_TRIMOVF

Trimming overflow or underflow

Definition at line 733 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRS_IRQHandler(), and HAL_RCCEx_CRSWaitSynchronization().

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STM32WB55xx HAL User Manual: Flags Interrupts Management

Defines
Flags Interrupts Management
RCCEx Exported Macros

macros to manage the specified RCC Flags and interrupts. More...

Defines

#define | __HAL_RCC_PLLSAI1_ENABLE_IT() LL_RCC_EnableIT_PLLSAI1RDY()
Enable PLLSAI1RDY interrupt.
#define | __HAL_RCC_PLLSAI1_DISABLE_IT() LL_RCC_DisableIT_PLLSAI1RDY()
Disable PLLSAI1RDY interrupt.
#define | __HAL_RCC_PLLSAI1_CLEAR_IT() LL_RCC_ClearFlag_PLLSAI1RDY()
Clear the PLLSAI1RDY interrupt pending bit.
#define | __HAL_RCC_PLLSAI1_GET_IT_SOURCE() LL_RCC_IsActiveFlag_PLLSAI1RDY()
Check whether PLLSAI1RDY interrupt has occurred or not.
#define | __HAL_RCC_PLLSAI1_GET_FLAG() LL_RCC_PLLSAI1_IsReady()
Check whether the PLLSAI1RDY flag is set or not.
#define | __HAL_RCC_LSECSS_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(RCC_EXTI_LINE_LSECSS)
Enable the RCC LSE CSS Extended Interrupt C1 Line.
#define | __HAL_C2_RCC_LSECSS_EXTI_ENABLE_IT() LL_C2_EXTI_EnableIT_0_31(RCC_EXTI_LINE_LSECSS)
Enable the RCC LSE CSS Extended Interrupt C2 Line.
#define | __HAL_RCC_LSECSS_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(RCC_EXTI_LINE_LSECSS)
Disable the RCC LSE CSS Extended Interrupt C1 Line.
#define | __HAL_C2_RCC_LSECSS_EXTI_DISABLE_IT() LL_C2_EXTI_DisableIT_0_31(RCC_EXTI_LINE_LSECSS)
Disable the RCC LSE CSS Extended Interrupt C2 Line.
#define | __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(RCC_EXTI_LINE_LSECSS)
Enable the RCC LSE CSS Event C1 Line.
#define | __HAL_C2_RCC_LSECSS_EXTI_ENABLE_EVENT() LL_C2_EXTI_EnableEvent_0_31(RCC_EXTI_LINE_LSECSS)
Enable the RCC LSE CSS Event C2 Line.
#define | __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(RCC_EXTI_LINE_LSECSS)
Disable the RCC LSE CSS Event C1 Line.
#define | __HAL_C2_RCC_LSECSS_EXTI_DISABLE_EVENT() LL_C2_EXTI_DisableEvent_0_31(RCC_EXTI_LINE_LSECSS)
Disable the RCC LSE CSS Event C2 Line.
#define | __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(RCC_EXTI_LINE_LSECSS)
Enable the RCC LSE CSS Extended Interrupt Falling Trigger.
#define | __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(RCC_EXTI_LINE_LSECSS)
Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
#define | __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(RCC_EXTI_LINE_LSECSS)
Enable the RCC LSE CSS Extended Interrupt Rising Trigger.
#define | __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(RCC_EXTI_LINE_LSECSS)
Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
#define | __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
#define | __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
#define | __HAL_RCC_LSECSS_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_0_31(RCC_EXTI_LINE_LSECSS)
Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
#define | __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(RCC_EXTI_LINE_LSECSS)
Clear the RCC LSE CSS EXTI flag.
#define | __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(RCC_EXTI_LINE_LSECSS)
Generate a Software interrupt on the RCC LSE CSS EXTI line.
#define | __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
Enable the specified CRS interrupts.
#define | __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__))
Disable the specified CRS interrupts.
#define | __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the CRS interrupt has occurred or not.
#define | __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__)
Clear the CRS interrupt pending bits.
#define | __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
Check whether the specified CRS flag is set or not.
#define | __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__)
Clear the CRS specified FLAG.

Detailed Description

macros to manage the specified RCC Flags and interrupts.

Define Documentation

#define __HAL_C2_RCC_LSECSS_EXTI_DISABLE_EVENT ( ) LL_C2_EXTI_DisableEvent_0_31(RCC_EXTI_LINE_LSECSS)

Disable the RCC LSE CSS Event C2 Line.

Return values:
None.

Definition at line 1293 of file stm32wbxx_hal_rcc_ex.h.

#define __HAL_C2_RCC_LSECSS_EXTI_DISABLE_IT ( ) LL_C2_EXTI_DisableIT_0_31(RCC_EXTI_LINE_LSECSS)

Disable the RCC LSE CSS Extended Interrupt C2 Line.

Return values:
None

Definition at line 1269 of file stm32wbxx_hal_rcc_ex.h.

#define __HAL_C2_RCC_LSECSS_EXTI_ENABLE_EVENT ( ) LL_C2_EXTI_EnableEvent_0_31(RCC_EXTI_LINE_LSECSS)

Enable the RCC LSE CSS Event C2 Line.

Return values:
None.

Definition at line 1281 of file stm32wbxx_hal_rcc_ex.h.

#define __HAL_C2_RCC_LSECSS_EXTI_ENABLE_IT ( ) LL_C2_EXTI_EnableIT_0_31(RCC_EXTI_LINE_LSECSS)

Enable the RCC LSE CSS Extended Interrupt C2 Line.

Return values:
None

Definition at line 1257 of file stm32wbxx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_CLEAR_FLAG ( __FLAG__ )
Value:
do { \
                                                 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \
                                                 { \
                                                   WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
                                                 } \
                                                 else \
                                                 { \
                                                   WRITE_REG(CRS->ICR, (__FLAG__)); \
                                                 } \
                                               } while(0)

Clear the CRS specified FLAG.

Parameters:
__FLAG__ specifies the flag to clear. This parameter can be one of the following values:
  • RCC_CRS_FLAG_SYNCOK SYNC event OK
  • RCC_CRS_FLAG_SYNCWARN SYNC warning
  • RCC_CRS_FLAG_ERR Error
  • RCC_CRS_FLAG_ESYNC Expected SYNC
  • RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
  • RCC_CRS_FLAG_SYNCERR SYNC error
  • RCC_CRS_FLAG_SYNCMISS SYNC missed
Note:
RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
Return values:
None

Definition at line 1444 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSWaitSynchronization().

#define __HAL_RCC_CRS_CLEAR_IT ( __INTERRUPT__ )
Value:
do { \
                                                 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \
                                                 { \
                                                   WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
                                                 } \
                                                 else \
                                                 { \
                                                   WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
                                                 } \
                                               } while(0)

Clear the CRS interrupt pending bits.

Parameters:
__INTERRUPT__ specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:
  • RCC_CRS_IT_SYNCOK SYNC event OK interrupt
  • RCC_CRS_IT_SYNCWARN SYNC warning interrupt
  • RCC_CRS_IT_ERR Synchronization or trimming error interrupt
  • RCC_CRS_IT_ESYNC Expected SYNC interrupt
  • RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt
  • RCC_CRS_IT_SYNCERR SYNC error interrupt
  • RCC_CRS_IT_SYNCMISS SYNC missed interrupt

Definition at line 1404 of file stm32wbxx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_DISABLE_IT ( __INTERRUPT__ ) CLEAR_BIT(CRS->CR, (__INTERRUPT__))

Disable the specified CRS interrupts.

Parameters:
__INTERRUPT__ specifies the CRS interrupt sources to be disabled. This parameter can be any combination of the following values:
  • RCC_CRS_IT_SYNCOK SYNC event OK interrupt
  • RCC_CRS_IT_SYNCWARN SYNC warning interrupt
  • RCC_CRS_IT_ERR Synchronization or trimming error interrupt
  • RCC_CRS_IT_ESYNC Expected SYNC interrupt
Return values:
None

Definition at line 1380 of file stm32wbxx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_ENABLE_IT ( __INTERRUPT__ ) SET_BIT(CRS->CR, (__INTERRUPT__))

Enable the specified CRS interrupts.

Parameters:
__INTERRUPT__ specifies the CRS interrupt sources to be enabled. This parameter can be any combination of the following values:
  • RCC_CRS_IT_SYNCOK SYNC event OK interrupt
  • RCC_CRS_IT_SYNCWARN SYNC warning interrupt
  • RCC_CRS_IT_ERR Synchronization or trimming error interrupt
  • RCC_CRS_IT_ESYNC Expected SYNC interrupt
Return values:
None

Definition at line 1368 of file stm32wbxx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_GET_FLAG ( __FLAG__ ) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))

Check whether the specified CRS flag is set or not.

Parameters:
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • RCC_CRS_FLAG_SYNCOK SYNC event OK
  • RCC_CRS_FLAG_SYNCWARN SYNC warning
  • RCC_CRS_FLAG_ERR Error
  • RCC_CRS_FLAG_ESYNC Expected SYNC
  • RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
  • RCC_CRS_FLAG_SYNCERR SYNC error
  • RCC_CRS_FLAG_SYNCMISS SYNC missed
Return values:
The new state of _FLAG_ (TRUE or FALSE).

Definition at line 1428 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSWaitSynchronization().

#define __HAL_RCC_CRS_GET_IT_SOURCE ( __INTERRUPT__ ) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET)

Check whether the CRS interrupt has occurred or not.

Parameters:
__INTERRUPT__ specifies the CRS interrupt source to check. This parameter can be one of the following values:
  • RCC_CRS_IT_SYNCOK SYNC event OK interrupt
  • RCC_CRS_IT_SYNCWARN SYNC warning interrupt
  • RCC_CRS_IT_ERR Synchronization or trimming error interrupt
  • RCC_CRS_IT_ESYNC Expected SYNC interrupt
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 1391 of file stm32wbxx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG ( ) LL_EXTI_ClearFlag_0_31(RCC_EXTI_LINE_LSECSS)

Clear the RCC LSE CSS EXTI flag.

Return values:
None.

Definition at line 1349 of file stm32wbxx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT ( ) LL_EXTI_DisableEvent_0_31(RCC_EXTI_LINE_LSECSS)

Disable the RCC LSE CSS Event C1 Line.

Return values:
None.

Definition at line 1287 of file stm32wbxx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE ( ) LL_EXTI_DisableFallingTrig_0_31(RCC_EXTI_LINE_LSECSS)

Disable the RCC LSE CSS Extended Interrupt Falling Trigger.

Return values:
None.

Definition at line 1305 of file stm32wbxx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT ( ) LL_EXTI_DisableIT_0_31(RCC_EXTI_LINE_LSECSS)

Disable the RCC LSE CSS Extended Interrupt C1 Line.

Return values:
None

Definition at line 1263 of file stm32wbxx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE ( ) LL_EXTI_DisableRisingTrig_0_31(RCC_EXTI_LINE_LSECSS)

Disable the RCC LSE CSS Extended Interrupt Rising Trigger.

Return values:
None.

Definition at line 1317 of file stm32wbxx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                       \
    __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE();             \
    __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE();            \
  } while(0)

Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.

Return values:
None.

Definition at line 1333 of file stm32wbxx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT ( ) LL_EXTI_EnableEvent_0_31(RCC_EXTI_LINE_LSECSS)

Enable the RCC LSE CSS Event C1 Line.

Return values:
None.

Definition at line 1275 of file stm32wbxx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE ( ) LL_EXTI_EnableFallingTrig_0_31(RCC_EXTI_LINE_LSECSS)

Enable the RCC LSE CSS Extended Interrupt Falling Trigger.

Return values:
None.

Definition at line 1299 of file stm32wbxx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT ( ) LL_EXTI_EnableIT_0_31(RCC_EXTI_LINE_LSECSS)

Enable the RCC LSE CSS Extended Interrupt C1 Line.

Return values:
None

Definition at line 1251 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnableLSECSS_IT().

#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE ( ) LL_EXTI_EnableRisingTrig_0_31(RCC_EXTI_LINE_LSECSS)

Enable the RCC LSE CSS Extended Interrupt Rising Trigger.

Return values:
None.

Definition at line 1311 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnableLSECSS_IT().

#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do {                                                      \
    __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();             \
    __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE();            \
  } while(0)

Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.

Return values:
None.

Definition at line 1323 of file stm32wbxx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT ( ) LL_EXTI_GenerateSWI_0_31(RCC_EXTI_LINE_LSECSS)

Generate a Software interrupt on the RCC LSE CSS EXTI line.

Return values:
None.

Definition at line 1355 of file stm32wbxx_hal_rcc_ex.h.

#define __HAL_RCC_LSECSS_EXTI_GET_FLAG ( ) LL_EXTI_IsActiveFlag_0_31(RCC_EXTI_LINE_LSECSS)

Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.

Return values:
EXTI RCC LSE CSS Line Status.

Definition at line 1343 of file stm32wbxx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI1_CLEAR_IT ( ) LL_RCC_ClearFlag_PLLSAI1RDY()

Clear the PLLSAI1RDY interrupt pending bit.

Return values:
None

Definition at line 1234 of file stm32wbxx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI1_DISABLE_IT ( ) LL_RCC_DisableIT_PLLSAI1RDY()

Disable PLLSAI1RDY interrupt.

Return values:
None

Definition at line 1229 of file stm32wbxx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI1_ENABLE_IT ( ) LL_RCC_EnableIT_PLLSAI1RDY()

Enable PLLSAI1RDY interrupt.

Return values:
None

Definition at line 1224 of file stm32wbxx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI1_GET_FLAG ( ) LL_RCC_PLLSAI1_IsReady()

Check whether the PLLSAI1RDY flag is set or not.

Return values:
TRUE or FALSE.

Definition at line 1244 of file stm32wbxx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI1_GET_IT_SOURCE ( ) LL_RCC_IsActiveFlag_PLLSAI1RDY()

Check whether PLLSAI1RDY interrupt has occurred or not.

Return values:
TRUE or FALSE.

Definition at line 1239 of file stm32wbxx_hal_rcc_ex.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RCCEx CRS Extended Features

Defines
RCCEx CRS Extended Features
RCCEx Exported Macros

Defines

#define | __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() LL_CRS_EnableFreqErrorCounter()
Enable the oscillator clock for frequency error counter.
#define | __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() LL_CRS_DisableFreqErrorCounter()
Disable the oscillator clock for frequency error counter.
#define | __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() LL_CRS_EnableAutoTrimming()
Enable the automatic hardware adjustement of TRIM bits.
#define | __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() LL_CRS_DisableAutoTrimming()
Enable or disable the automatic hardware adjustement of TRIM bits.
#define | __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) __LL_CRS_CALC_CALCULATE_RELOADVALUE((__FTARGET__),(__FSYNC__))
Macro to calculate reload value to be set in CRS register according to target and sync frequencies.

Define Documentation

#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE ( ) LL_CRS_DisableAutoTrimming()

Enable or disable the automatic hardware adjustement of TRIM bits.

Return values:
None

Definition at line 1488 of file stm32wbxx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE ( ) LL_CRS_EnableAutoTrimming()

Enable the automatic hardware adjustement of TRIM bits.

Note:
When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
Return values:
None

Definition at line 1482 of file stm32wbxx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE ( ) LL_CRS_DisableFreqErrorCounter()

Disable the oscillator clock for frequency error counter.

Return values:
None

Definition at line 1475 of file stm32wbxx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE ( ) LL_CRS_EnableFreqErrorCounter()

Enable the oscillator clock for frequency error counter.

Note:
when the CEN bit is set the CRS_CFGR register becomes write-protected.
Return values:
None

Definition at line 1469 of file stm32wbxx_hal_rcc_ex.h.

#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE | ( | __FTARGET__,
 |  | __FSYNC__
 | ) | __LL_CRS_CALC_CALCULATE_RELOADVALUE((__FTARGET__),(__FSYNC__))

Macro to calculate reload value to be set in CRS register according to target and sync frequencies.

Note:
The RELOAD value should be selected according to the ratio between the target frequency and the frequency of the synchronization source after prescaling. It is then decreased by one in order to reach the expected synchronization on the zero value. The formula is the following: RELOAD = (fTARGET / fSYNC) -1
Parameters:
__FTARGET__ | Target frequency (value in Hz)
__FSYNC__ | Synchronization signal frequency (value in Hz)
Return values:
None

Definition at line 1500 of file stm32wbxx_hal_rcc_ex.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RCCEx Exported Macros

Modules | Defines
RCCEx Exported Macros
RCCEx

Modules

Flags Interrupts Management

macros to manage the specified RCC Flags and interrupts.

RCCEx CRS Extended Features

Defines

#define | __HAL_RCC_PLLSAI1_CONFIG(__PLLN__, __PLLP__, __PLLQ__, __PLLR__)
Macro to configure the PLLSAI1 clock multiplication and division factors.
#define | __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLN__) MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLN, (__PLLN__) << RCC_PLLSAI1CFGR_PLLN_Pos)
Macro to configure the PLLSAI1 clock multiplication factor N.
#define | __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLP__) MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLP, (__PLLP__))
Macro to configure the PLLSAI1 clock division factor P.
#define | __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLQ__) MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLQ, (__PLLQ__))
Macro to configure the PLLSAI1 clock division factor Q.
#define | __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLR__) MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLR, (__PLLR__))
Macro to configure the PLLSAI1 clock division factor R.
#define | __HAL_RCC_PLLSAI1_ENABLE() LL_RCC_PLLSAI1_Enable()
Macros to enable the PLLSAI1.
#define | __HAL_RCC_PLLSAI1_DISABLE() LL_RCC_PLLSAI1_Disable()
Macros to disable the PLLSAI1.
#define | __HAL_RCC_PLLSAI1CLKOUT_ENABLE(__PLLSAI1_CLOCKOUT__) SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
Macros to enable each clock output (RCC_PLLSAI1_SAI1CLK, RCC_PLLSAI1_USBCLK and RCC_PLLSAI1_ADCCLK).
#define | __HAL_RCC_PLLSAI1CLKOUT_DISABLE(__PLLSAI1_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
Macros to disable each clock output (RCC_PLLSAI1_SAI1CLK, RCC_PLLSAI1_USBCLK and RCC_PLLSAI1_ADCCLK).
#define | __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__) READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
Macro to get clock output enable status (RCC_PLLSAI1_SAI1CLK, RCC_PLLSAI1_USBCLK and RCC_PLLSAI1_ADCCLK).
#define | __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__) LL_RCC_SetSAIClockSource(__SAI1_CLKSOURCE__)
Macro to configure the SAI1 clock source.
#define | __HAL_RCC_GET_SAI1_SOURCE() LL_RCC_GetSAIClockSource(LL_RCC_SAI1_CLKSOURCE)
Macro to get the SAI1 clock source.
#define | __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) LL_RCC_SetI2CClockSource(__I2C1_CLKSOURCE__)
Macro to configure the I2C1 clock (I2C1CLK).
#define | __HAL_RCC_GET_I2C1_SOURCE() LL_RCC_GetI2CClockSource(LL_RCC_I2C1_CLKSOURCE)
Macro to get the I2C1 clock source.
#define | __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) LL_RCC_SetI2CClockSource(__I2C3_CLKSOURCE__)
Macro to configure the I2C3 clock (I2C3CLK).
#define | __HAL_RCC_GET_I2C3_SOURCE() LL_RCC_GetI2CClockSource(LL_RCC_I2C3_CLKSOURCE)
Macro to get the I2C3 clock source.
#define | __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) LL_RCC_SetUSARTClockSource(__USART1_CLKSOURCE__)
Macro to configure the USART1 clock (USART1CLK).
#define | __HAL_RCC_GET_USART1_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_USART1_CLKSOURCE)
Macro to get the USART1 clock source.
#define | __HAL_RCC_LPUART1_CONFIG(__LPUART_CLKSOURCE__) LL_RCC_SetLPUARTClockSource(__LPUART_CLKSOURCE__)
Macro to configure the LPUART clock (LPUARTCLK).
#define | __HAL_RCC_GET_LPUART1_SOURCE() LL_RCC_GetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE)
Macro to get the LPUART clock source.
#define | __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) LL_RCC_SetLPTIMClockSource(__LPTIM1_CLKSOURCE__)
Macro to configure the LPTIM1 clock (LPTIM1CLK).
#define | __HAL_RCC_GET_LPTIM1_SOURCE() LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE)
Macro to get the LPTIM1 clock source.
#define | __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) LL_RCC_SetLPTIMClockSource(__LPTIM2_CLKSOURCE__)
Macro to configure the LPTIM2 clock (LPTIM2CLK).
#define | __HAL_RCC_GET_LPTIM2_SOURCE() LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE)
Macro to get the LPTIM2 clock source.
#define | __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__)
Macro to configure the RNG clock.
#define | __HAL_RCC_GET_RNG_SOURCE() LL_RCC_GetRNGClockSource(LL_RCC_RNG_CLKSOURCE)
Macro to get the direct RNG clock.
#define | __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) LL_RCC_SetUSBClockSource(__USB_CLKSOURCE__)
Macro to configure the USB clock (USBCLK).
#define | __HAL_RCC_GET_USB_SOURCE() LL_RCC_GetUSBClockSource(LL_RCC_USB_CLKSOURCE)
Macro to get the USB clock source.
#define | __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) LL_RCC_SetADCClockSource(__ADC_CLKSOURCE__)
Macro to configure the ADC interface clock.
#define | __HAL_RCC_GET_ADC_SOURCE() LL_RCC_GetADCClockSource(LL_RCC_ADC_CLKSOURCE)
Macro to get the ADC clock source.
#define | __HAL_RCC_RFWAKEUP_CONFIG(__RFWKP_CLKSOURCE__) LL_RCC_SetRFWKPClockSource(__RFWKP_CLKSOURCE__)
Macro to configure the RFWKP interface clock.
#define | __HAL_RCC_GET_RFWAKEUP_SOURCE() LL_RCC_GetRFWKPClockSource()
Macro to get the RFWKP clock source.
#define | __HAL_RCC_SMPS_DIV_CONFIG(__SMPSCLKDIV__) LL_RCC_SetSMPSPrescaler(__SMPSCLKDIV__)
Macro to configure the SMPS clock division factor.
#define | __HAL_RCC_GET_SMPS_DIV() LL_RCC_GetSMPSPrescaler()
Macro to get the SMPS clock division factor.
#define | __HAL_RCC_SMPS_CONFIG(__SMPS_CLKSOURCE__) LL_RCC_SetSMPSClockSource(__SMPS_CLKSOURCE__)
Macro to configure the SMPS interface clock.
#define | __HAL_RCC_GET_SMPS_SOURCE() LL_RCC_GetSMPSClockSelection()
Macro to get the SMPS clock source.
#define | __HAL_RCC_GET_SMPS_SOURCE_STATUS() LL_RCC_GetSMPSClockSource()
Macro to get the SMPS clock source.

Define Documentation

#define __HAL_RCC_ADC_CONFIG ( __ADC_CLKSOURCE__ ) LL_RCC_SetADCClockSource(__ADC_CLKSOURCE__)

Macro to configure the ADC interface clock.

Parameters:
__ADC_CLKSOURCE__ specifies the ADC digital interface clock source. This parameter can be one of the following values:
  • RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock
  • RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock
  • RCC_ADCCLKSOURCE_PLL PLL Clock selected as ADC clock
  • RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock
Return values:
None

Definition at line 1129 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_GET_ADC_SOURCE ( ) LL_RCC_GetADCClockSource(LL_RCC_ADC_CLKSOURCE)

Macro to get the ADC clock source.

Return values:
The clock source can be one of the following values:
  • RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock
  • RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock
  • RCC_ADCCLKSOURCE_PLL PLL Clock selected as ADC clock
  • RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock

Definition at line 1138 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_I2C1_SOURCE ( ) LL_RCC_GetI2CClockSource(LL_RCC_I2C1_CLKSOURCE)

Macro to get the I2C1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock

Definition at line 947 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_I2C3_SOURCE ( ) LL_RCC_GetI2CClockSource(LL_RCC_I2C3_CLKSOURCE)

Macro to get the I2C3 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock
  • RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
  • RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock

Definition at line 967 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_LPTIM1_SOURCE ( ) LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE)

Macro to get the LPTIM1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_LPTIM1CLKSOURCE_PCLK1 PCLK selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock

Definition at line 1033 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and LPTIM_Disable().

#define __HAL_RCC_GET_LPTIM2_SOURCE ( ) LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE)

Macro to get the LPTIM2 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_LPTIM2CLKSOURCE_PCLK1 PCLK selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_HSI System Clock selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock

Definition at line 1054 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and LPTIM_Disable().

#define __HAL_RCC_GET_LPUART1_SOURCE ( ) LL_RCC_GetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE)

Macro to get the LPUART clock source.

Return values:
The clock source can be one of the following values:
  • RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock

Definition at line 1011 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG ( __PLLSAI1_CLOCKOUT__ ) READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))

Macro to get clock output enable status (RCC_PLLSAI1_SAI1CLK, RCC_PLLSAI1_USBCLK and RCC_PLLSAI1_ADCCLK).

Parameters:
__PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output. This parameter can be one or a combination of the following values:
  • RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve high-quality audio performance on SAI interface
  • RCC_PLLSAI1_ADCCLK Clock used to clock ADC peripheral
  • RCC_PLLSAI1_USBCLK This clock is used to generate the clock for the USB Device (48 MHz)
Return values:
SET / RESET

Definition at line 900 of file stm32wbxx_hal_rcc_ex.h.

#define __HAL_RCC_GET_RFWAKEUP_SOURCE ( ) LL_RCC_GetRFWKPClockSource()

Macro to get the RFWKP clock source.

This parameter can be one of the following values:

  • RCC_RFWKPCLKSOURCE_NONE No clock selected as RFWKP clock
  • RCC_RFWKPCLKSOURCE_LSE LSE Clock selected as RFWKP clock
  • RCC_RFWKPCLKSOURCE_LSI LSI Clock selected as RFWKP clock
  • RCC_RFWKPCLKSOURCE_HSE_DIV1024 HSE div1024 Clock selected as RFWKP clock

Definition at line 1158 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_RNG_SOURCE ( ) LL_RCC_GetRNGClockSource(LL_RCC_RNG_CLKSOURCE)

Macro to get the direct RNG clock.

Note:
HAL_RCCEx_GetRngCLKSource can also be called to get direct of indirect (48 MHz clock source) RNG clock source.
Return values:
The RNG clock source can be one of the following values:
  • RCC_RNGCLKSOURCE_CLK48 CLK48 divided by 3 selected as RNG Clock
  • RCC_RNGCLKSOURCE_LSI LSI selected as RNG clock
  • RCC_RNGCLKSOURCE_LSE LSE selected as RNG clock

Definition at line 1095 of file stm32wbxx_hal_rcc_ex.h.

#define __HAL_RCC_GET_SAI1_SOURCE ( ) LL_RCC_GetSAIClockSource(LL_RCC_SAI1_CLKSOURCE)

Macro to get the SAI1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock
  • RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock
  • RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI clock
  • RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK)
None

Definition at line 927 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_SMPS_DIV ( ) LL_RCC_GetSMPSPrescaler()

Macro to get the SMPS clock division factor.

This parameter can be one of the following values:

  • RCC_SMPSCLKDIV_RANGE0 1st divider factor value
  • RCC_SMPSCLKDIV_RANGE1 2nd divider factor value
  • RCC_SMPSCLKDIV_RANGE2 3th divider factor value
  • RCC_SMPSCLKDIV_RANGE3 4th divider factor value

Definition at line 1185 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_SMPS_SOURCE ( ) LL_RCC_GetSMPSClockSelection()

Macro to get the SMPS clock source.

This parameter can be one of the following values:

  • RCC_SMPSCLKSOURCE_HSI HSI clock selected as SMPS clock
  • RCC_SMPSCLKSOURCE_MSI MSI Clock selected as SMPS clock
  • RCC_SMPSCLKSOURCE_HSE HSE Clock selected as SMPS clock

Definition at line 1204 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_SMPS_SOURCE_STATUS ( ) LL_RCC_GetSMPSClockSource()

Macro to get the SMPS clock source.

This parameter can be one of the following values:

  • RCC_SMPSCLKSOURCE_STATUS_HSI HSI clock selected as SMPS clock
  • RCC_SMPSCLKSOURCE_STATUS_MSI MSI Clock selected as SMPS clock
  • RCC_SMPSCLKSOURCE_STATUS_HSE HSE Clock selected as SMPS clock

Definition at line 1212 of file stm32wbxx_hal_rcc_ex.h.

#define __HAL_RCC_GET_USART1_SOURCE ( ) LL_RCC_GetUSARTClockSource(LL_RCC_USART1_CLKSOURCE)

Macro to get the USART1 clock source.

Return values:
The clock source can be one of the following values:
  • RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
  • RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
  • RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
  • RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock

Definition at line 989 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_USB_SOURCE ( ) LL_RCC_GetUSBClockSource(LL_RCC_USB_CLKSOURCE)

Macro to get the USB clock source.

Return values:
The clock source can be one of the following values:
  • RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48
  • RCC_USBCLKSOURCE_MSI MSI selected as USB clock
  • RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock
  • RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock

Definition at line 1118 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_I2C1_CONFIG ( __I2C1_CLKSOURCE__ ) LL_RCC_SetI2CClockSource(__I2C1_CLKSOURCE__)

Macro to configure the I2C1 clock (I2C1CLK).

Parameters:
__I2C1_CLKSOURCE__ specifies the I2C1 clock source. This parameter can be one of the following values:
  • RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
Return values:
None

Definition at line 939 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_I2C3_CONFIG ( __I2C3_CLKSOURCE__ ) LL_RCC_SetI2CClockSource(__I2C3_CLKSOURCE__)

Macro to configure the I2C3 clock (I2C3CLK).

Parameters:
__I2C3_CLKSOURCE__ specifies the I2C3 clock source. This parameter can be one of the following values:
  • RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock
  • RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
  • RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
Return values:
None

Definition at line 959 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_LPTIM1_CONFIG ( __LPTIM1_CLKSOURCE__ ) LL_RCC_SetLPTIMClockSource(__LPTIM1_CLKSOURCE__)

Macro to configure the LPTIM1 clock (LPTIM1CLK).

Parameters:
__LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. This parameter can be one of the following values:
  • RCC_LPTIM1CLKSOURCE_PCLK1 PCLK selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock
Return values:
None

Definition at line 1024 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig(), and LPTIM_Disable().

#define __HAL_RCC_LPTIM2_CONFIG ( __LPTIM2_CLKSOURCE__ ) LL_RCC_SetLPTIMClockSource(__LPTIM2_CLKSOURCE__)

Macro to configure the LPTIM2 clock (LPTIM2CLK).

Parameters:
__LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source. This parameter can be one of the following values:
  • RCC_LPTIM2CLKSOURCE_PCLK1 PCLK selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_HSI LSI selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock
Return values:
None

Definition at line 1045 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig(), and LPTIM_Disable().

#define __HAL_RCC_LPUART1_CONFIG ( __LPUART_CLKSOURCE__ ) LL_RCC_SetLPUARTClockSource(__LPUART_CLKSOURCE__)

Macro to configure the LPUART clock (LPUARTCLK).

Parameters:
__LPUART_CLKSOURCE__ specifies the LPUART clock source. This parameter can be one of the following values:
  • RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
Return values:
None

Definition at line 1002 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_PLLSAI1_CONFIG | ( | __PLLN__,
 |  | __PLLP__,
 |  | __PLLQ__,
 |  | __PLLR__
 | ) |
Value:
MODIFY_REG(RCC->PLLSAI1CFGR, \
                             (RCC_PLLSAI1CFGR_PLLN | RCC_PLLSAI1CFGR_PLLP | RCC_PLLSAI1CFGR_PLLQ | RCC_PLLSAI1CFGR_PLLR), \
                             (((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | (__PLLP__) | (__PLLQ__) | (__PLLR__)))

Macro to configure the PLLSAI1 clock multiplication and division factors.

Note:
This function must be used only when the PLLSAI1 is disabled.
PLLSAI1 clock source is common with the main PLL (configured through __HAL_RCC_PLL_CONFIG() macro)
Parameters:
__PLLN__ specifies the multiplication factor for PLLSAI1 VCO output clock. This parameter must be a number between 6 and 127.
Note:
You have to set the PLLN parameter correctly to ensure that the VCO output frequency is between 96 and 344 MHz. PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLN
Parameters:
__PLLP__ | specifies the division factor for SAI clock. This parameter must be a number in the range (RCC_PLLP_DIV2 to RCC_PLLP_DIV32). SAI clock frequency = f(PLLSAI1) / PLLP
__PLLQ__ | specifies the division factor for USB/RNG clock. This parameter must be in the range (RCC_PLLQ_DIV2 to RCC_PLLQ_DIV8). USB/RNG clock frequency = f(PLLSAI1) / PLLQ
__PLLR__ | specifies the division factor for SAR ADC clock. This parameter must be in the range (RCC_PLLR_DIV2 to RCC_PLLR_DIV8). ADC clock frequency = f(PLLSAI1) / PLLR
Return values:
None

Definition at line 779 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI1().

#define __HAL_RCC_PLLSAI1_DISABLE ( ) LL_RCC_PLLSAI1_Disable()

Macros to disable the PLLSAI1.

Note:
The PLLSAI1 is disabled by hardware when entering STOP and STANDBY modes.
Return values:
None

Definition at line 861 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_DisablePLLSAI1(), HAL_RCCEx_EnablePLLSAI1(), RCCEx_PLLSAI1_ConfigNP(), RCCEx_PLLSAI1_ConfigNQ(), and RCCEx_PLLSAI1_ConfigNR().

#define __HAL_RCC_PLLSAI1_DIVP_CONFIG ( __PLLP__ ) MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLP, (__PLLP__))

Macro to configure the PLLSAI1 clock division factor P.

Note:
This function must be used only when the PLLSAI1 is disabled.
PLLSAI1 clock source is common with the main PLL (configured through __HAL_RCC_PLL_CONFIG() macro)
Parameters:
__PLLP__ specifies the division factor for SAI clock. This parameter must be a number in range (RCC_PLLP_DIV2 to RCC_PLLP_DIV32). Use to set SAI clock frequency = f(PLLSAI1) / PLLP
Return values:
None

Definition at line 815 of file stm32wbxx_hal_rcc_ex.h.

Referenced by RCCEx_PLLSAI1_ConfigNP().

#define __HAL_RCC_PLLSAI1_DIVQ_CONFIG ( __PLLQ__ ) MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLQ, (__PLLQ__))

Macro to configure the PLLSAI1 clock division factor Q.

Note:
This function must be used only when the PLLSAI1 is disabled.
PLLSAI1 clock source is common with the main PLL (configured through __HAL_RCC_PLL_CONFIG() macro)
Parameters:
__PLLQ__ specifies the division factor for USB clock. This parameter must be in the range (RCC_PLLQ_DIV2 to RCC_PLLQ_DIV8). Use to set USB clock frequency = f(PLLSAI1) / PLLQ
Return values:
None

Definition at line 831 of file stm32wbxx_hal_rcc_ex.h.

Referenced by RCCEx_PLLSAI1_ConfigNQ().

#define __HAL_RCC_PLLSAI1_DIVR_CONFIG ( __PLLR__ ) MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLR, (__PLLR__))

Macro to configure the PLLSAI1 clock division factor R.

Note:
This function must be used only when the PLLSAI1 is disabled.
PLLSAI1 clock source is common with the main PLL (configured through __HAL_RCC_PLL_CONFIG() macro)
Parameters:
__PLLR__ specifies the division factor for ADC clock. This parameter must be in the range (RCC_PLLR_DIV2 to RCC_PLLR_DIV8). Use to set ADC clock frequency = f(PLLSAI1) / PLLR
Return values:
None

Definition at line 846 of file stm32wbxx_hal_rcc_ex.h.

Referenced by RCCEx_PLLSAI1_ConfigNR().

#define __HAL_RCC_PLLSAI1_ENABLE ( ) LL_RCC_PLLSAI1_Enable()

Macros to enable the PLLSAI1.

Note:
The PLLSAI1 is disabled by hardware when entering STOP and STANDBY modes.
Return values:
None

Definition at line 854 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI1(), RCCEx_PLLSAI1_ConfigNP(), RCCEx_PLLSAI1_ConfigNQ(), and RCCEx_PLLSAI1_ConfigNR().

#define __HAL_RCC_PLLSAI1_MULN_CONFIG ( __PLLN__ ) MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLN, (__PLLN__) << RCC_PLLSAI1CFGR_PLLN_Pos)

Macro to configure the PLLSAI1 clock multiplication factor N.

Note:
This function must be used only when the PLLSAI1 is disabled.
PLLSAI1 clock source is common with the main PLL (configured through __HAL_RCC_PLL_CONFIG() macro)
Parameters:
__PLLN__ specifies the multiplication factor for PLLSAI1 VCO output clock. This parameter must be a number between Min_Data=6 and Max_Data=127.
Note:
You have to set the PLLN parameter correctly to ensure that the VCO output frequency is between 96 and 344 MHz. Use to set PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLN
Return values:
None

Definition at line 799 of file stm32wbxx_hal_rcc_ex.h.

Referenced by RCCEx_PLLSAI1_ConfigNP(), RCCEx_PLLSAI1_ConfigNQ(), and RCCEx_PLLSAI1_ConfigNR().

#define __HAL_RCC_PLLSAI1CLKOUT_DISABLE ( __PLLSAI1_CLOCKOUT__ ) CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))

Macros to disable each clock output (RCC_PLLSAI1_SAI1CLK, RCC_PLLSAI1_USBCLK and RCC_PLLSAI1_ADCCLK).

Note:
Enabling and disabling those clocks can be done without the need to stop the PLL. This is mainly used to save Power.
Parameters:
__PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output. This parameter can be one or a combination of the following values:
  • RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve high-quality audio performance on SAI interface
  • RCC_PLLSAI1_ADCCLK Clock used to clock ADC peripheral
  • RCC_PLLSAI1_USBCLK This clock is used to generate the clock for the USB Device (48 MHz)
Return values:
None

Definition at line 889 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_DisablePLLSAI1().

#define __HAL_RCC_PLLSAI1CLKOUT_ENABLE ( __PLLSAI1_CLOCKOUT__ ) SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))

Macros to enable each clock output (RCC_PLLSAI1_SAI1CLK, RCC_PLLSAI1_USBCLK and RCC_PLLSAI1_ADCCLK).

Note:
Enabling and disabling those clocks can be done without the need to stop the PLL. This is mainly used to save Power.
Parameters:
__PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output. This parameter can be one or a combination of the following values:
  • RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve high-quality audio performance on SAI interface
  • RCC_PLLSAI1_ADCCLK Clock used to clock ADC peripheral
  • RCC_PLLSAI1_USBCLK This clock is used to generate the clock for the USB Device (48 MHz)
Return values:
None

Definition at line 875 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI1(), RCCEx_PLLSAI1_ConfigNP(), RCCEx_PLLSAI1_ConfigNQ(), and RCCEx_PLLSAI1_ConfigNR().

#define __HAL_RCC_RFWAKEUP_CONFIG ( __RFWKP_CLKSOURCE__ ) LL_RCC_SetRFWKPClockSource(__RFWKP_CLKSOURCE__)

Macro to configure the RFWKP interface clock.

Parameters:
__RFWKP_CLKSOURCE__ specifies the RFWKP digital interface clock source. This parameter can be one of the following values:
  • RCC_RFWKPCLKSOURCE_NONE No clock selected as RFWKP clock
  • RCC_RFWKPCLKSOURCE_LSE LSE Clock selected as RFWKP clock
  • RCC_RFWKPCLKSOURCE_LSI LSI Clock selected as RFWKP clock
  • RCC_RFWKPCLKSOURCE_HSE_DIV1024 HSE div1024 Clock selected as RFWKP clock
Return values:
None

Definition at line 1149 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_RNG_CONFIG ( __RNG_CLKSOURCE__ )
Value:
do {                                                      \
    if (((__RNG_CLKSOURCE__) == RCC_RNGCLKSOURCE_LSI)       \
     || ((__RNG_CLKSOURCE__) == RCC_RNGCLKSOURCE_LSE)       \
     || ((__RNG_CLKSOURCE__) == RCC_RNGCLKSOURCE_CLK48))    \
    {                                                       \
     LL_RCC_SetRNGClockSource((__RNG_CLKSOURCE__));         \
    }                                                       \
    else                                                    \
    {                                                       \
      uint32_t tmp = (__RNG_CLKSOURCE__) &(~CLK48_MASK);   \
      LL_RCC_SetRNGClockSource(RCC_RNGCLKSOURCE_CLK48);     \
      LL_RCC_SetCLK48ClockSource(tmp);                      \
    }                                                       \
  } while(0U)

Macro to configure the RNG clock.

Note:
USB and RNG peripherals share the same 48MHz clock source.
Parameters:
__RNG_CLKSOURCE__ specifies the RNG clock source. This parameter can be one of the following values:
  • RCC_RNGCLKSOURCE_HSI48 HSI48 clock divided by 3 selected as RNG clock
  • RCC_RNGCLKSOURCE_PLL PLL "Q" clock divided by 3 selected as RNG clock
  • RCC_RNGCLKSOURCE_MSI MSI clock divided by 3 selected as RNG clock
  • RCC_RNGCLKSOURCE_CLK48 CLK48 divided by 3 selected as RNG Clock (default HSI48)
  • RCC_RNGCLKSOURCE_LSI LSI clock selected as RNG clock
  • RCC_RNGCLKSOURCE_LSE LSE clock selected as RNG clock
Return values:
None

Definition at line 1071 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SAI1_CONFIG ( __SAI1_CLKSOURCE__ ) LL_RCC_SetSAIClockSource(__SAI1_CLKSOURCE__)

Macro to configure the SAI1 clock source.

Parameters:
__SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived from the PLLSAI1, system PLL, HSI or external clock (through a dedicated pin). This parameter can be one of the following values:
  • RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock
  • RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock
  • RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI clock
  • RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK)
Return values:
None

Definition at line 915 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SMPS_CONFIG ( __SMPS_CLKSOURCE__ ) LL_RCC_SetSMPSClockSource(__SMPS_CLKSOURCE__)

Macro to configure the SMPS interface clock.

Parameters:
__SMPS_CLKSOURCE__ specifies the SMPS digital interface clock source. This parameter can be one of the following values:
  • RCC_SMPSCLKSOURCE_HSI HSI clock selected as SMPS clock
  • RCC_SMPSCLKSOURCE_MSI MSI Clock selected as SMPS clock
  • RCC_SMPSCLKSOURCE_HSE HSE Clock selected as SMPS clock
Return values:
None

Definition at line 1196 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SMPS_DIV_CONFIG ( __SMPSCLKDIV__ ) LL_RCC_SetSMPSPrescaler(__SMPSCLKDIV__)

Macro to configure the SMPS clock division factor.

Parameters:
__SMPSCLKDIV__ specifies the division factor for SMPS clock. This parameter can be one of the following values:
  • RCC_SMPSCLKDIV_RANGE0 1st divider factor value
  • RCC_SMPSCLKDIV_RANGE1 2nd divider factor value
  • RCC_SMPSCLKDIV_RANGE2 3th divider factor value
  • RCC_SMPSCLKDIV_RANGE3 4th divider factor value
Note:
divider value predefined by HW depending of SMPS clock source
Return values:
None

Definition at line 1174 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_USART1_CONFIG ( __USART1_CLKSOURCE__ ) LL_RCC_SetUSARTClockSource(__USART1_CLKSOURCE__)

Macro to configure the USART1 clock (USART1CLK).

Parameters:
__USART1_CLKSOURCE__ specifies the USART1 clock source. This parameter can be one of the following values:
  • RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
  • RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
  • RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
  • RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
Return values:
None

Definition at line 980 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_USB_CONFIG ( __USB_CLKSOURCE__ ) LL_RCC_SetUSBClockSource(__USB_CLKSOURCE__)

Macro to configure the USB clock (USBCLK).

Note:
USB and RNG peripherals share the same 48MHz clock source.
Parameters:
__USB_CLKSOURCE__ specifies the USB clock source. This parameter can be one of the following values:
  • RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48
  • RCC_USBCLKSOURCE_MSI MSI selected as USB clock
  • RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock
  • RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock
Return values:
None

Definition at line 1109 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RCCEx_Private_Macros

Defines
RCCEx_Private_Macros
RCCEx

Defines

#define | IS_RCC_LSCO(__LSCOX__) ( ((__LSCOX__) == RCC_LSCO1) || ((__LSCOX__) == RCC_LSCO2) || ((__LSCOX__) == RCC_LSCO3) )
#define | IS_RCC_LSCOSOURCE(__SOURCE__)
#define | IS_RCC_PERIPHCLOCK(__SELECTION__)
#define | IS_RCC_USART1CLKSOURCE(__SOURCE__)
#define | IS_RCC_LPUART1CLKSOURCE(__SOURCE__)
#define | IS_RCC_I2C1CLKSOURCE(__SOURCE__)
#define | IS_RCC_I2C3CLKSOURCE(__SOURCE__)
#define | IS_RCC_SAI1CLK(__SOURCE__)
#define | IS_RCC_LPTIM1CLK(__SOURCE__)
#define | IS_RCC_LPTIM2CLK(__SOURCE__)
#define | IS_RCC_RNGCLKSOURCE(__SOURCE__)
#define | IS_RCC_USBCLKSOURCE(__SOURCE__)
#define | IS_RCC_ADCCLKSOURCE(__SOURCE__)
#define | IS_RCC_RFWKPCLKSOURCE(__SOURCE__)
#define | IS_RCC_SMPSCLKDIV(__DIV__)
#define | IS_RCC_SMPSCLKSOURCE(__SOURCE__)
#define | IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((6U <= (__VALUE__)) && ((__VALUE__) <= 127U))
#define | IS_RCC_PLLSAI1P_VALUE(__VALUE__) ((RCC_PLLP_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLP_DIV32))
#define | IS_RCC_PLLSAI1Q_VALUE(__VALUE__) ((RCC_PLLQ_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLQ_DIV8))
#define | IS_RCC_PLLSAI1R_VALUE(__VALUE__) ((RCC_PLLR_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLR_DIV8))
#define | IS_RCC_TRIMOSC(__VALUE__) ((__VALUE__) == RCC_OSCILLATORTYPE_LSI2)
#define | IS_RCC_CRS_SYNC_SOURCE(__SOURCE__)
#define | IS_RCC_CRS_SYNC_DIV(__DIV__)
#define | IS_RCC_CRS_SYNC_POLARITY(__POLARITY__)
#define | IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU))
#define | IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU))
#define | IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
#define | IS_RCC_CRS_FREQERRORDIR(__DIR__)

Define Documentation

#define IS_RCC_ADCCLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \
                ((__SOURCE__) == RCC_ADCCLKSOURCE_PLL) || \
                ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \
                ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))

Definition at line 162 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_CRS_ERRORLIMIT ( __VALUE__ ) (((__VALUE__) <= 0xFFU))

Definition at line 220 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

#define IS_RCC_CRS_FREQERRORDIR ( __DIR__ )
Value:
(((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
                                            ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))

Definition at line 224 of file stm32wbxx_hal_rcc_ex.h.

#define IS_RCC_CRS_HSI48CALIBRATION ( __VALUE__ ) (((__VALUE__) <= 0x3FU))

Definition at line 222 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

#define IS_RCC_CRS_RELOADVALUE ( __VALUE__ ) (((__VALUE__) <= 0xFFFFU))

Definition at line 218 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

#define IS_RCC_CRS_SYNC_DIV ( __DIV__ )
Value:
(((__DIV__) == RCC_CRS_SYNC_DIV1)  || ((__DIV__) == RCC_CRS_SYNC_DIV2)  || \
                                            ((__DIV__) == RCC_CRS_SYNC_DIV4)  || ((__DIV__) == RCC_CRS_SYNC_DIV8)  || \
                                            ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
                                            ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))

Definition at line 210 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

#define IS_RCC_CRS_SYNC_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
                                                ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))

Definition at line 215 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

#define IS_RCC_CRS_SYNC_SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \
                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE)  || \
                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))

Definition at line 206 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_CRSConfig().

#define IS_RCC_I2C1CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
                ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
                ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))

Definition at line 108 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_I2C3CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \
                ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
                ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))

Definition at line 114 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_LPTIM1CLK ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \
                ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI)  || \
                ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI)  || \
                ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE))

Definition at line 128 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_LPTIM2CLK ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \
                ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI)  || \
                ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI)  || \
                ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE))

Definition at line 134 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_LPUART1CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1)  || \
                ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
                ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE)    || \
                ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))

Definition at line 101 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_LSCO ( __LSCOX__ ) ( ((__LSCOX__) == RCC_LSCO1) || ((__LSCOX__) == RCC_LSCO2) || ((__LSCOX__) == RCC_LSCO3) )

Definition at line 62 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_LSCOConfig().

#define IS_RCC_LSCOSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \
                                       ((__SOURCE__) == RCC_LSCOSOURCE_LSE))

Definition at line 64 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnableLSCO(), and HAL_RCCEx_LSCOConfig().

#define IS_RCC_PERIPHCLOCK ( __SELECTION__ )
Value:
((((__SELECTION__) & RCC_PERIPHCLK_USART1)   == RCC_PERIPHCLK_USART1)  || \
                (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)  || \
                (((__SELECTION__) & RCC_PERIPHCLK_I2C1)      == RCC_PERIPHCLK_I2C1)   || \
                (((__SELECTION__) & RCC_PERIPHCLK_I2C3)     == RCC_PERIPHCLK_I2C3)    || \
                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)   == RCC_PERIPHCLK_LPTIM1)  || \
                (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)   == RCC_PERIPHCLK_LPTIM2)  || \
                (((__SELECTION__) & RCC_PERIPHCLK_SAI1)     == RCC_PERIPHCLK_SAI1)    || \
                (((__SELECTION__) & RCC_PERIPHCLK_USB)      == RCC_PERIPHCLK_USB)     || \
                (((__SELECTION__) & RCC_PERIPHCLK_RNG)      == RCC_PERIPHCLK_RNG)     || \
                (((__SELECTION__) & RCC_PERIPHCLK_ADC)      == RCC_PERIPHCLK_ADC)     || \
                (((__SELECTION__) & RCC_PERIPHCLK_RTC)      == RCC_PERIPHCLK_RTC)     || \
                (((__SELECTION__) & RCC_PERIPHCLK_RFWAKEUP) == RCC_PERIPHCLK_RFWAKEUP)|| \
                (((__SELECTION__) & RCC_PERIPHCLK_SMPS)     == RCC_PERIPHCLK_SMPS))

Definition at line 68 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_PLLSAI1N_VALUE ( __VALUE__ ) ((6U <= (__VALUE__)) && ((__VALUE__) <= 127U))

Definition at line 194 of file stm32wbxx_hal_rcc_ex.h.

#define IS_RCC_PLLSAI1P_VALUE ( __VALUE__ ) ((RCC_PLLP_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLP_DIV32))

Definition at line 196 of file stm32wbxx_hal_rcc_ex.h.

#define IS_RCC_PLLSAI1Q_VALUE ( __VALUE__ ) ((RCC_PLLQ_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLQ_DIV8))

Definition at line 198 of file stm32wbxx_hal_rcc_ex.h.

#define IS_RCC_PLLSAI1R_VALUE ( __VALUE__ ) ((RCC_PLLR_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLR_DIV8))

Definition at line 200 of file stm32wbxx_hal_rcc_ex.h.

#define IS_RCC_RFWKPCLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_RFWKPCLKSOURCE_NONE) || \
                ((__SOURCE__) == RCC_RFWKPCLKSOURCE_LSE) || \
                ((__SOURCE__) == RCC_RFWKPCLKSOURCE_LSI) || \
                ((__SOURCE__) == RCC_RFWKPCLKSOURCE_HSE_DIV1024))

Definition at line 174 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_RNGCLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48)   || \
                ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL)     || \
                ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI)     || \
                ((__SOURCE__) == RCC_RNGCLKSOURCE_CLK48)   || \
                ((__SOURCE__) == RCC_RNGCLKSOURCE_LSI)     || \
                ((__SOURCE__) == RCC_RNGCLKSOURCE_LSE))

Definition at line 140 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_SAI1CLK ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \
                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \
                ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI)     || \
                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))

Definition at line 121 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_SMPSCLKDIV ( __DIV__ )
Value:
(((__DIV__) == RCC_SMPSCLKDIV_RANGE0) || \
                ((__DIV__) == RCC_SMPSCLKDIV_RANGE1) || \
                ((__DIV__) == RCC_SMPSCLKDIV_RANGE2) || \
                ((__DIV__) == RCC_SMPSCLKDIV_RANGE3))

Definition at line 181 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_SMPSCLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_SMPSCLKSOURCE_HSI)    || \
                ((__SOURCE__) == RCC_SMPSCLKSOURCE_MSI)    || \
                ((__SOURCE__) == RCC_SMPSCLKSOURCE_HSE))

Definition at line 187 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_TRIMOSC ( __VALUE__ ) ((__VALUE__) == RCC_OSCILLATORTYPE_LSI2)

Definition at line 203 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_TrimOsc().

#define IS_RCC_USART1CLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2)  || \
                ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
                ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE)    || \
                ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))

Definition at line 94 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_USBCLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_USBCLKSOURCE_HSI48)   || \
                ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \
                ((__SOURCE__) == RCC_USBCLKSOURCE_PLL)     || \
                ((__SOURCE__) == RCC_USBCLKSOURCE_MSI))

Definition at line 149 of file stm32wbxx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RNG Private Constants

Defines
RNG Private Constants
RNG

Defines

#define RNG_TIMEOUT_VALUE 2U

Define Documentation

#define RNG_TIMEOUT_VALUE 2U

Definition at line 118 of file stm32wbxx_hal_rng.c.

Referenced by HAL_RNG_GenerateRandomNumber().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RNG_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RNG_InitTypeDef Struct Reference
RNG Init Structure definition

#include <stm32wbxx_hal_rng.h>

Data Fields

uint32_t ClockErrorDetection

Detailed Description

Definition at line 51 of file stm32wbxx_hal_rng.h.

Field Documentation

uint32_t RNG_InitTypeDef::ClockErrorDetection

CED Clock error detection

Definition at line 53 of file stm32wbxx_hal_rng.h.

Referenced by HAL_RNG_Init().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_rng.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RNG State Structure definition

Enumerations
RNG State Structure definition
RNG Exported Types

Enumerations

enum HAL_RNG_StateTypeDef {
HAL_RNG_STATE_RESET = 0x00U, HAL_RNG_STATE_READY = 0x01U, HAL_RNG_STATE_BUSY = 0x02U, HAL_RNG_STATE_TIMEOUT = 0x03U,
HAL_RNG_STATE_ERROR = 0x04U
}

Enumeration Type Documentation

enum HAL_RNG_StateTypeDef
Enumerator:
HAL_RNG_STATE_RESET

RNG not yet initialized or disabled

HAL_RNG_STATE_READY

RNG initialized and ready for use

HAL_RNG_STATE_BUSY

RNG internal process is ongoing

HAL_RNG_STATE_TIMEOUT

RNG timeout state

HAL_RNG_STATE_ERROR

RNG error state

Definition at line 63 of file stm32wbxx_hal_rng.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RNG Handle Structure definition

Data Structures | Typedefs | Enumerations
RNG Handle Structure definition
RNG Exported Types

Data Structures

struct | __RNG_HandleTypeDef

Typedefs

typedef struct __RNG_HandleTypeDef | RNG_HandleTypeDef
typedef void(* | pRNG_CallbackTypeDef )(RNG_HandleTypeDef *hrng)
HAL RNG Callback pointer definition.
typedef void(* | pRNG_ReadyDataCallbackTypeDef )(RNG_HandleTypeDef *hrng, uint32_t random32bit)

Enumerations

enum | HAL_RNG_CallbackIDTypeDef { HAL_RNG_ERROR_CB_ID = 0x00U, HAL_RNG_MSPINIT_CB_ID = 0x01U, HAL_RNG_MSPDEINIT_CB_ID = 0x02U }
HAL RNG Callback ID enumeration definition. More...

Typedef Documentation

typedef void(* pRNG_CallbackTypeDef)(RNG_HandleTypeDef *hrng)

HAL RNG Callback pointer definition.

pointer to a common RNG callback function

Definition at line 124 of file stm32wbxx_hal_rng.h.

typedef void(* pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t random32bit)

pointer to an RNG Data Ready specific callback function

Definition at line 125 of file stm32wbxx_hal_rng.h.

typedef struct __RNG_HandleTypeDef RNG_HandleTypeDef

Enumeration Type Documentation

enum HAL_RNG_CallbackIDTypeDef

HAL RNG Callback ID enumeration definition.

Enumerator:
HAL_RNG_ERROR_CB_ID

RNG Error Callback ID

HAL_RNG_MSPINIT_CB_ID

RNG MspInit callback ID

HAL_RNG_MSPDEINIT_CB_ID

RNG MspDeInit callback ID

Definition at line 112 of file stm32wbxx_hal_rng.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: __RNG_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__RNG_HandleTypeDef Struct Reference
RNG Handle Structure definition

#include <stm32wbxx_hal_rng.h>

Data Fields

RNG_TypeDef * | Instance
RNG_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_RNG_StateTypeDef | State
__IO uint32_t | ErrorCode
uint32_t | RandomNumber
void(* | ReadyDataCallback )(struct __RNG_HandleTypeDef *hrng, uint32_t random32bit)
void(* | ErrorCallback )(struct __RNG_HandleTypeDef *hrng)
void(* | MspInitCallback )(struct __RNG_HandleTypeDef *hrng)
void(* | MspDeInitCallback )(struct __RNG_HandleTypeDef *hrng)

Detailed Description

Definition at line 81 of file stm32wbxx_hal_rng.h.

Field Documentation

void(* __RNG_HandleTypeDef::ErrorCallback)(struct __RNG_HandleTypeDef *hrng)

RNG Error Callback

Definition at line 100 of file stm32wbxx_hal_rng.h.

Referenced by HAL_RNG_Init(), HAL_RNG_IRQHandler(), HAL_RNG_RegisterCallback(), and HAL_RNG_UnRegisterCallback().

__IO uint32_t __RNG_HandleTypeDef::ErrorCode

RNG Error code

Definition at line 94 of file stm32wbxx_hal_rng.h.

Referenced by HAL_RNG_DeInit(), HAL_RNG_GenerateRandomNumber(), HAL_RNG_GenerateRandomNumber_IT(), HAL_RNG_GetError(), HAL_RNG_Init(), HAL_RNG_IRQHandler(), HAL_RNG_RegisterCallback(), HAL_RNG_RegisterReadyDataCallback(), HAL_RNG_UnRegisterCallback(), and HAL_RNG_UnRegisterReadyDataCallback().

RNG_InitTypeDef __RNG_HandleTypeDef::Init

RNG configuration parameters

Definition at line 88 of file stm32wbxx_hal_rng.h.

Referenced by HAL_RNG_Init().

RNG_TypeDef* __RNG_HandleTypeDef::Instance

Register base address

Definition at line 86 of file stm32wbxx_hal_rng.h.

Referenced by HAL_RNG_DeInit(), HAL_RNG_GenerateRandomNumber(), HAL_RNG_Init(), and HAL_RNG_IRQHandler().

HAL_LockTypeDef __RNG_HandleTypeDef::Lock

RNG locking object

Definition at line 90 of file stm32wbxx_hal_rng.h.

Referenced by HAL_RNG_Init().

void(* __RNG_HandleTypeDef::MspDeInitCallback)(struct __RNG_HandleTypeDef *hrng)

RNG Msp DeInit callback

Definition at line 103 of file stm32wbxx_hal_rng.h.

Referenced by HAL_RNG_DeInit(), HAL_RNG_RegisterCallback(), and HAL_RNG_UnRegisterCallback().

void(* __RNG_HandleTypeDef::MspInitCallback)(struct __RNG_HandleTypeDef *hrng)

RNG Msp Init callback

Definition at line 102 of file stm32wbxx_hal_rng.h.

Referenced by HAL_RNG_Init(), HAL_RNG_RegisterCallback(), and HAL_RNG_UnRegisterCallback().

uint32_t __RNG_HandleTypeDef::RandomNumber

Last Generated RNG Data

Definition at line 96 of file stm32wbxx_hal_rng.h.

Referenced by HAL_RNG_GenerateRandomNumber(), HAL_RNG_IRQHandler(), and HAL_RNG_ReadLastRandomNumber().

void(* __RNG_HandleTypeDef::ReadyDataCallback)(struct __RNG_HandleTypeDef *hrng, uint32_t random32bit)

RNG Data Ready Callback

Definition at line 99 of file stm32wbxx_hal_rng.h.

Referenced by HAL_RNG_Init(), HAL_RNG_IRQHandler(), HAL_RNG_RegisterReadyDataCallback(), and HAL_RNG_UnRegisterReadyDataCallback().

__IO HAL_RNG_StateTypeDef __RNG_HandleTypeDef::State

RNG communication state

Definition at line 92 of file stm32wbxx_hal_rng.h.

Referenced by HAL_RNG_DeInit(), HAL_RNG_GenerateRandomNumber(), HAL_RNG_GenerateRandomNumber_IT(), HAL_RNG_GetState(), HAL_RNG_Init(), HAL_RNG_IRQHandler(), HAL_RNG_RegisterCallback(), HAL_RNG_RegisterReadyDataCallback(), HAL_RNG_UnRegisterCallback(), and HAL_RNG_UnRegisterReadyDataCallback().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_rng.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RNG Interrupt definition

Defines
RNG Interrupt definition
RNG Exported Constants

Defines

#define | RNG_IT_DRDY RNG_SR_DRDY
#define | RNG_IT_CEI RNG_SR_CEIS
#define | RNG_IT_SEI RNG_SR_SEIS

Define Documentation

#define RNG_IT_CEI RNG_SR_CEIS

Clock error interrupt

Definition at line 146 of file stm32wbxx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define RNG_IT_DRDY RNG_SR_DRDY

Data Ready interrupt

Definition at line 145 of file stm32wbxx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define RNG_IT_SEI RNG_SR_SEIS

Seed error interrupt

Definition at line 147 of file stm32wbxx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RNG Flag definition

Defines
RNG Flag definition
RNG Exported Constants

Defines

#define | RNG_FLAG_DRDY RNG_SR_DRDY
#define | RNG_FLAG_CECS RNG_SR_CECS
#define | RNG_FLAG_SECS RNG_SR_SECS

Define Documentation

#define RNG_FLAG_CECS RNG_SR_CECS

Clock error current status

Definition at line 156 of file stm32wbxx_hal_rng.h.

#define RNG_FLAG_DRDY RNG_SR_DRDY

Data ready

Definition at line 155 of file stm32wbxx_hal_rng.h.

Referenced by HAL_RNG_GenerateRandomNumber().

#define RNG_FLAG_SECS RNG_SR_SECS

Seed error current status

Definition at line 157 of file stm32wbxx_hal_rng.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RNG Clock Error Detection

Defines
RNG Clock Error Detection
RNG Exported Constants

Defines

#define | RNG_CED_ENABLE 0x00000000U
#define | RNG_CED_DISABLE RNG_CR_CED

Define Documentation

#define RNG_CED_DISABLE RNG_CR_CED

Clock error detection Disabled

Definition at line 166 of file stm32wbxx_hal_rng.h.

#define RNG_CED_ENABLE 0x00000000U

Clock error detection Enabled

Definition at line 165 of file stm32wbxx_hal_rng.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RNG Error Definition

Defines
RNG Error Definition
RNG Exported Constants

Defines

#define | HAL_RNG_ERROR_NONE 0x00000000U
#define | HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U
#define | HAL_RNG_ERROR_TIMEOUT 0x00000002U
#define | HAL_RNG_ERROR_BUSY 0x00000004U
#define | HAL_RNG_ERROR_SEED 0x00000008U
#define | HAL_RNG_ERROR_CLOCK 0x00000010U

Define Documentation

#define HAL_RNG_ERROR_BUSY 0x00000004U

Busy error

Definition at line 179 of file stm32wbxx_hal_rng.h.

Referenced by HAL_RNG_GenerateRandomNumber(), and HAL_RNG_GenerateRandomNumber_IT().

#define HAL_RNG_ERROR_CLOCK 0x00000010U

Clock error

Definition at line 181 of file stm32wbxx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U

Invalid Callback error

Definition at line 176 of file stm32wbxx_hal_rng.h.

Referenced by HAL_RNG_RegisterCallback(), HAL_RNG_RegisterReadyDataCallback(), HAL_RNG_UnRegisterCallback(), and HAL_RNG_UnRegisterReadyDataCallback().

#define HAL_RNG_ERROR_NONE 0x00000000U

No error

Definition at line 174 of file stm32wbxx_hal_rng.h.

Referenced by HAL_RNG_DeInit(), and HAL_RNG_Init().

#define HAL_RNG_ERROR_SEED 0x00000008U

Seed error

Definition at line 180 of file stm32wbxx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define HAL_RNG_ERROR_TIMEOUT 0x00000002U

Timeout error

Definition at line 178 of file stm32wbxx_hal_rng.h.

Referenced by HAL_RNG_GenerateRandomNumber().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RNG Exported Macros

Defines
RNG Exported Macros
RNG

Defines

#define | __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__)
Reset RNG handle state.
#define | __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)
Enables the RNG peripheral.
#define | __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
Disables the RNG peripheral.
#define | __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check the selected RNG flag status.
#define | __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */
Clears the selected RNG flag status.
#define | __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)
Enables the RNG interrupts.
#define | __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
Disables the RNG interrupts.
#define | __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
Checks whether the specified RNG interrupt has occurred or not.
#define | __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
Clear the RNG interrupt status flags.

Define Documentation

#define __HAL_RNG_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | /* dummy macro */

Clears the selected RNG flag status.

Parameters:
__HANDLE__ | RNG handle
__FLAG__ | RNG flag to clear
Note:
WARNING: This is a dummy macro for HAL code alignment, flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
Return values:
None

Definition at line 243 of file stm32wbxx_hal_rng.h.

#define __HAL_RNG_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))

Clear the RNG interrupt status flags.

Parameters:
__HANDLE__ RNG Handle
__INTERRUPT__ specifies the RNG interrupt status flag to clear. This parameter can be one of the following values:
  • RNG_IT_CEI: Clock error interrupt
  • RNG_IT_SEI: Seed error interrupt
Note:
RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.
Return values:
None

Definition at line 281 of file stm32wbxx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define __HAL_RNG_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)

Disables the RNG peripheral.

Parameters:
__HANDLE__ RNG Handle
Return values:
None

Definition at line 221 of file stm32wbxx_hal_rng.h.

#define __HAL_RNG_DISABLE_IT ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)

Disables the RNG interrupts.

Parameters:
__HANDLE__ RNG Handle
Return values:
None

Definition at line 257 of file stm32wbxx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define __HAL_RNG_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)

Enables the RNG peripheral.

Parameters:
__HANDLE__ RNG Handle
Return values:
None

Definition at line 214 of file stm32wbxx_hal_rng.h.

Referenced by HAL_RNG_Init().

#define __HAL_RNG_ENABLE_IT ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)

Enables the RNG interrupts.

Parameters:
__HANDLE__ RNG Handle
Return values:
None

Definition at line 250 of file stm32wbxx_hal_rng.h.

Referenced by HAL_RNG_GenerateRandomNumber_IT().

#define __HAL_RNG_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))

Check the selected RNG flag status.

Parameters:
__HANDLE__ RNG Handle
__FLAG__ RNG flag This parameter can be one of the following values:
  • RNG_FLAG_DRDY: Data ready
  • RNG_FLAG_CECS: Clock error current status
  • RNG_FLAG_SECS: Seed error current status
Return values:
The new state of __FLAG__ (SET or RESET).

Definition at line 233 of file stm32wbxx_hal_rng.h.

Referenced by HAL_RNG_GenerateRandomNumber().

#define __HAL_RNG_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))

Checks whether the specified RNG interrupt has occurred or not.

Parameters:
__HANDLE__ RNG Handle
__INTERRUPT__ specifies the RNG interrupt status flag to check. This parameter can be one of the following values:
  • RNG_IT_DRDY: Data ready interrupt
  • RNG_IT_CEI: Clock error interrupt
  • RNG_IT_SEI: Seed error interrupt
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 269 of file stm32wbxx_hal_rng.h.

Referenced by HAL_RNG_IRQHandler().

#define __HAL_RNG_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                   \
                                                       (__HANDLE__)->State = HAL_RNG_STATE_RESET;       \
                                                       (__HANDLE__)->MspInitCallback = NULL;            \
                                                       (__HANDLE__)->MspDeInitCallback = NULL;          \
                                                    } while(0U)

Reset RNG handle state.

Parameters:
__HANDLE__ RNG Handle
Return values:
None

Definition at line 200 of file stm32wbxx_hal_rng.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization and configuration functions

Functions
Initialization and configuration functions
RNG Exported Functions

Initialization and configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_RNG_Init (RNG_HandleTypeDef *hrng)
Initializes the RNG peripheral and creates the associated handle.
HAL_StatusTypeDef | HAL_RNG_DeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG peripheral.
__weak void | HAL_RNG_MspInit (RNG_HandleTypeDef *hrng)
Initializes the RNG MSP.
__weak void | HAL_RNG_MspDeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG MSP.
HAL_StatusTypeDef | HAL_RNG_RegisterCallback (RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback)
Register a User RNG Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_RNG_UnRegisterCallback (RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID)
Unregister an RNG Callback RNG callabck is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_RNG_RegisterReadyDataCallback (RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback)
Register Data Ready RNG Callback To be used instead of the weak HAL_RNG_ReadyDataCallback() predefined callback.
HAL_StatusTypeDef | HAL_RNG_UnRegisterReadyDataCallback (RNG_HandleTypeDef *hrng)
UnRegister the Data Ready RNG Callback Data Ready RNG Callback is redirected to the weak HAL_RNG_ReadyDataCallback() predefined callback.

Detailed Description

Initialization and configuration functions.

 ===============================================================================
          ##### Initialization and configuration functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the RNG according to the specified parameters
          in the RNG_InitTypeDef and create the associated handle
      (+) DeInitialize the RNG peripheral
      (+) Initialize the RNG MSP
      (+) DeInitialize RNG MSP

Function Documentation

HAL_StatusTypeDef HAL_RNG_DeInit ( RNG_HandleTypeDef * hrng )

DeInitializes the RNG peripheral.

Parameters:
hrng pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
HAL status

Definition at line 219 of file stm32wbxx_hal_rng.c.

References __RNG_HandleTypeDef::ErrorCode, HAL_RNG_ERROR_NONE, HAL_RNG_MspDeInit(), HAL_RNG_STATE_RESET, __RNG_HandleTypeDef::Instance, __RNG_HandleTypeDef::MspDeInitCallback, and __RNG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RNG_Init ( RNG_HandleTypeDef * hrng )

Initializes the RNG peripheral and creates the associated handle.

Parameters:
hrng pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
HAL status

Definition at line 155 of file stm32wbxx_hal_rng.c.

References __HAL_RNG_ENABLE, assert_param, RNG_InitTypeDef::ClockErrorDetection, __RNG_HandleTypeDef::ErrorCallback, __RNG_HandleTypeDef::ErrorCode, HAL_RNG_ERROR_NONE, HAL_RNG_ErrorCallback(), HAL_RNG_MspInit(), HAL_RNG_ReadyDataCallback(), HAL_RNG_STATE_BUSY, HAL_RNG_STATE_READY, HAL_RNG_STATE_RESET, __RNG_HandleTypeDef::Init, __RNG_HandleTypeDef::Instance, IS_RNG_CED, __RNG_HandleTypeDef::Lock, __RNG_HandleTypeDef::MspInitCallback, __RNG_HandleTypeDef::ReadyDataCallback, and __RNG_HandleTypeDef::State.

void HAL_RNG_MspDeInit ( RNG_HandleTypeDef * hrng )

DeInitializes the RNG MSP.

Parameters:
hrng pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
None

Definition at line 282 of file stm32wbxx_hal_rng.c.

Referenced by HAL_RNG_DeInit(), and HAL_RNG_UnRegisterCallback().

void HAL_RNG_MspInit ( RNG_HandleTypeDef * hrng )

Initializes the RNG MSP.

Parameters:
hrng pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
None

Definition at line 267 of file stm32wbxx_hal_rng.c.

Referenced by HAL_RNG_Init(), and HAL_RNG_UnRegisterCallback().

HAL_StatusTypeDef HAL_RNG_RegisterCallback | ( | RNG_HandleTypeDef * | hrng,
 |  | HAL_RNG_CallbackIDTypeDef | CallbackID,
 |  | pRNG_CallbackTypeDef | pCallback
 | ) |  |

Register a User RNG Callback To be used instead of the weak predefined callback.

Parameters:
hrng | RNG handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_RNG_ERROR_CB_ID Error callback ID
  • HAL_RNG_MSPINIT_CB_ID MspInit callback ID
  • HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 304 of file stm32wbxx_hal_rng.c.

References __RNG_HandleTypeDef::ErrorCallback, __RNG_HandleTypeDef::ErrorCode, HAL_RNG_ERROR_CB_ID, HAL_RNG_ERROR_INVALID_CALLBACK, HAL_RNG_MSPDEINIT_CB_ID, HAL_RNG_MSPINIT_CB_ID, HAL_RNG_STATE_READY, HAL_RNG_STATE_RESET, __RNG_HandleTypeDef::MspDeInitCallback, __RNG_HandleTypeDef::MspInitCallback, and __RNG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback | ( | RNG_HandleTypeDef * | hrng,
 |  | pRNG_ReadyDataCallbackTypeDef | pCallback
 | ) |  |

Register Data Ready RNG Callback To be used instead of the weak HAL_RNG_ReadyDataCallback() predefined callback.

Parameters:
hrng | RNG handle
pCallback | pointer to the Data Ready Callback function
Return values:
HAL status

Definition at line 456 of file stm32wbxx_hal_rng.c.

References __RNG_HandleTypeDef::ErrorCode, HAL_RNG_ERROR_INVALID_CALLBACK, HAL_RNG_STATE_READY, __RNG_HandleTypeDef::ReadyDataCallback, and __RNG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RNG_UnRegisterCallback | ( | RNG_HandleTypeDef * | hrng,
 |  | HAL_RNG_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an RNG Callback RNG callabck is redirected to the weak predefined callback.

Parameters:
hrng RNG handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_RNG_ERROR_CB_ID Error callback ID
  • HAL_RNG_MSPINIT_CB_ID MspInit callback ID
  • HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
HAL status

Definition at line 385 of file stm32wbxx_hal_rng.c.

References __RNG_HandleTypeDef::ErrorCallback, __RNG_HandleTypeDef::ErrorCode, HAL_RNG_ERROR_CB_ID, HAL_RNG_ERROR_INVALID_CALLBACK, HAL_RNG_ErrorCallback(), HAL_RNG_MspDeInit(), HAL_RNG_MSPDEINIT_CB_ID, HAL_RNG_MspInit(), HAL_RNG_MSPINIT_CB_ID, HAL_RNG_STATE_READY, HAL_RNG_STATE_RESET, __RNG_HandleTypeDef::MspDeInitCallback, __RNG_HandleTypeDef::MspInitCallback, and __RNG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback ( RNG_HandleTypeDef * hrng )

UnRegister the Data Ready RNG Callback Data Ready RNG Callback is redirected to the weak HAL_RNG_ReadyDataCallback() predefined callback.

Parameters:
hrng RNG handle
Return values:
HAL status

Definition at line 492 of file stm32wbxx_hal_rng.c.

References __RNG_HandleTypeDef::ErrorCode, HAL_RNG_ERROR_INVALID_CALLBACK, HAL_RNG_ReadyDataCallback(), HAL_RNG_STATE_READY, __RNG_HandleTypeDef::ReadyDataCallback, and __RNG_HandleTypeDef::State.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
RNG Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber (RNG_HandleTypeDef *hrng, uint32_t *random32bit)
Generates a 32-bit random number.
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber_IT (RNG_HandleTypeDef *hrng)
Generates a 32-bit random number in interrupt mode.
void | HAL_RNG_IRQHandler (RNG_HandleTypeDef *hrng)
Handles RNG interrupt request.
uint32_t | HAL_RNG_ReadLastRandomNumber (RNG_HandleTypeDef *hrng)
Read latest generated random number.
__weak void | HAL_RNG_ReadyDataCallback (RNG_HandleTypeDef *hrng, uint32_t random32bit)
Data Ready callback in non-blocking mode.
__weak void | HAL_RNG_ErrorCallback (RNG_HandleTypeDef *hrng)
RNG error callbacks.

Detailed Description

Peripheral Control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Get the 32 bit Random number
      (+) Get the 32 bit Random number with interrupt enabled
      (+) Handle RNG interrupt request

Function Documentation

void HAL_RNG_ErrorCallback ( RNG_HandleTypeDef * hrng )

RNG error callbacks.

Parameters:
hrng pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
None

Definition at line 764 of file stm32wbxx_hal_rng.c.

Referenced by HAL_RNG_Init(), HAL_RNG_IRQHandler(), and HAL_RNG_UnRegisterCallback().

HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber | ( | RNG_HandleTypeDef * | hrng,
 |  | uint32_t * | random32bit
 | ) |  |

Generates a 32-bit random number.

Note:
This function checks value of RNG_FLAG_DRDY flag to know if valid random number is available in the DR register (RNG_FLAG_DRDY flag set whenever a random number is available through the RNG_DR register). After transitioning from 0 to 1 (random number available), RNG_FLAG_DRDY flag remains high until output buffer becomes empty after reading four words from the RNG_DR register, i.e. further function calls will immediately return a new u32 random number (additional words are available and can be read by the application, till RNG_FLAG_DRDY flag remains high).
When no more random number data is available in DR register, RNG_FLAG_DRDY flag is automatically cleared.
Parameters:
hrng | pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
random32bit | pointer to generated random number variable if successful.
Return values:
HAL status

Definition at line 556 of file stm32wbxx_hal_rng.c.

References __HAL_RNG_GET_FLAG, __RNG_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_RNG_ERROR_BUSY, HAL_RNG_ERROR_TIMEOUT, HAL_RNG_STATE_BUSY, HAL_RNG_STATE_READY, __RNG_HandleTypeDef::Instance, __RNG_HandleTypeDef::RandomNumber, RNG_FLAG_DRDY, RNG_TIMEOUT_VALUE, and __RNG_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT ( RNG_HandleTypeDef * hrng )

Generates a 32-bit random number in interrupt mode.

Parameters:
hrng pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
HAL status

Definition at line 610 of file stm32wbxx_hal_rng.c.

References __HAL_RNG_ENABLE_IT, __RNG_HandleTypeDef::ErrorCode, HAL_RNG_ERROR_BUSY, HAL_RNG_STATE_BUSY, HAL_RNG_STATE_READY, and __RNG_HandleTypeDef::State.

void HAL_RNG_IRQHandler ( RNG_HandleTypeDef * hrng )

Handles RNG interrupt request.

Note:
In the case of a clock error, the RNG is no more able to generate random numbers because the PLL48CLK clock is not correct. User has to check that the clock controller is correctly configured to provide the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT(). The clock error has no impact on the previously generated random numbers, and the RNG_DR register contents can be used.
In the case of a seed error, the generation of random numbers is interrupted as long as the SECS bit is '1'. If a number is available in the RNG_DR register, it must not be used because it may not have enough entropy. In this case, it is recommended to clear the SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable the RNG peripheral to reinitialize and restart the RNG.
User-written HAL_RNG_ErrorCallback() API is called once whether SEIS or CEIS are set.
Parameters:
hrng pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
None

Definition at line 659 of file stm32wbxx_hal_rng.c.

References __HAL_RNG_CLEAR_IT, __HAL_RNG_DISABLE_IT, __HAL_RNG_GET_IT, __RNG_HandleTypeDef::ErrorCallback, __RNG_HandleTypeDef::ErrorCode, HAL_RNG_ERROR_CLOCK, HAL_RNG_ERROR_SEED, HAL_RNG_ErrorCallback(), HAL_RNG_ReadyDataCallback(), HAL_RNG_STATE_ERROR, HAL_RNG_STATE_READY, __RNG_HandleTypeDef::Instance, __RNG_HandleTypeDef::RandomNumber, __RNG_HandleTypeDef::ReadyDataCallback, RNG_IT_CEI, RNG_IT_DRDY, RNG_IT_SEI, and __RNG_HandleTypeDef::State.

uint32_t HAL_RNG_ReadLastRandomNumber ( RNG_HandleTypeDef * hrng )

Read latest generated random number.

Parameters:
hrng pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
random value

Definition at line 731 of file stm32wbxx_hal_rng.c.

References __RNG_HandleTypeDef::RandomNumber.

void HAL_RNG_ReadyDataCallback | ( | RNG_HandleTypeDef * | hrng,
 |  | uint32_t | random32bit
 | ) |  |

Data Ready callback in non-blocking mode.

Note:
When RNG_FLAG_DRDY flag value is set, first random number has been read from DR register in IRQ Handler and is provided as callback parameter. Depending on valid data available in the conditioning output buffer, additional words can be read by the application from DR register till DRDY bit remains high.
Parameters:
hrng | pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
random32bit | generated random number.
Return values:
None

Definition at line 748 of file stm32wbxx_hal_rng.c.

Referenced by HAL_RNG_Init(), HAL_RNG_IRQHandler(), and HAL_RNG_UnRegisterReadyDataCallback().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
RNG Exported Functions

Peripheral State functions. More...

Functions

HAL_RNG_StateTypeDef | HAL_RNG_GetState (RNG_HandleTypeDef *hrng)
Returns the RNG state.
uint32_t | HAL_RNG_GetError (RNG_HandleTypeDef *hrng)
Return the RNG handle error code.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

uint32_t HAL_RNG_GetError ( RNG_HandleTypeDef * hrng )

Return the RNG handle error code.

Parameters:
hrng,: pointer to a RNG_HandleTypeDef structure.
Return values:
RNG Error Code

Definition at line 808 of file stm32wbxx_hal_rng.c.

References __RNG_HandleTypeDef::ErrorCode.

HAL_RNG_StateTypeDef HAL_RNG_GetState ( RNG_HandleTypeDef * hrng )

Returns the RNG state.

Parameters:
hrng pointer to a RNG_HandleTypeDef structure that contains the configuration information for RNG.
Return values:
HAL state

Definition at line 798 of file stm32wbxx_hal_rng.c.

References __RNG_HandleTypeDef::State.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RNG Private Macros

Defines
RNG Private Macros
RNG

Defines

#define | IS_RNG_IT(IT)
#define | IS_RNG_FLAG(FLAG)
#define | IS_RNG_CED(__MODE__)
Verify the RNG Clock Error Detection mode.

Define Documentation

#define IS_RNG_CED ( __MODE__ )
Value:
(((__MODE__) == RNG_CED_ENABLE) || \
                                ((__MODE__) == RNG_CED_DISABLE))

Verify the RNG Clock Error Detection mode.

Parameters:
__MODE__ RNG Clock Error Detection mode
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 357 of file stm32wbxx_hal_rng.h.

Referenced by HAL_RNG_Init().

#define IS_RNG_FLAG ( FLAG )
Value:
(((FLAG) == RNG_FLAG_DRDY) || \
                            ((FLAG) == RNG_FLAG_CECS) || \
                            ((FLAG) == RNG_FLAG_SECS))

Definition at line 348 of file stm32wbxx_hal_rng.h.

#define IS_RNG_IT ( IT )
Value:
(((IT) == RNG_IT_CEI) || \
                       ((IT) == RNG_IT_SEI))

Definition at line 345 of file stm32wbxx_hal_rng.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC Exported Types

Data Structures | Typedefs | Enumerations
RTC Exported Types
RTC

Data Structures

struct | RTC_InitTypeDef
RTC Configuration Structure definition. More...
struct | RTC_TimeTypeDef
RTC Time structure definition. More...
struct | RTC_DateTypeDef
RTC Date structure definition. More...
struct | RTC_AlarmTypeDef
RTC Alarm structure definition. More...
struct | __RTC_HandleTypeDef
RTC Handle Structure definition. More...

Typedefs

typedef struct __RTC_HandleTypeDef | RTC_HandleTypeDef
RTC Handle Structure definition.
typedef void(* | pRTC_CallbackTypeDef )(RTC_HandleTypeDef *hrtc)
HAL RTC Callback pointer definition.

Enumerations

enum HAL_RTCStateTypeDef {
HAL_RTC_STATE_RESET = 0x00U, HAL_RTC_STATE_READY = 0x01U, HAL_RTC_STATE_BUSY = 0x02U, HAL_RTC_STATE_TIMEOUT = 0x03U,
HAL_RTC_STATE_ERROR = 0x04U
}
HAL State structures definition. More...
enum HAL_RTC_CallbackIDTypeDef {
HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00U, HAL_RTC_ALARM_B_EVENT_CB_ID = 0x01U, HAL_RTC_TIMESTAMP_EVENT_CB_ID = 0x02U, HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03U,
HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04U, HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05U, HAL_RTC_TAMPER3_EVENT_CB_ID = 0x06U, HAL_RTC_MSPINIT_CB_ID = 0x0EU,
HAL_RTC_MSPDEINIT_CB_ID = 0x0FU
}
HAL LPTIM Callback ID enumeration definition. More...

Typedef Documentation

typedef void(* pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc)

HAL RTC Callback pointer definition.

pointer to an RTC callback function

Definition at line 230 of file stm32wbxx_hal_rtc.h.

typedef struct __RTC_HandleTypeDef RTC_HandleTypeDef

RTC Handle Structure definition.

Enumeration Type Documentation

enum HAL_RTC_CallbackIDTypeDef

HAL LPTIM Callback ID enumeration definition.

Enumerator:
HAL_RTC_ALARM_A_EVENT_CB_ID

RTC Alarm A Event Callback ID

HAL_RTC_ALARM_B_EVENT_CB_ID

RTC Alarm B Event Callback ID

HAL_RTC_TIMESTAMP_EVENT_CB_ID

RTC TimeStamp Event Callback ID

HAL_RTC_WAKEUPTIMER_EVENT_CB_ID

RTC WakeUp Timer Event Callback ID

HAL_RTC_TAMPER1_EVENT_CB_ID

RTC Tamper 1 Callback ID

HAL_RTC_TAMPER2_EVENT_CB_ID

RTC Tamper 2 Callback ID

HAL_RTC_TAMPER3_EVENT_CB_ID

RTC Tamper 3 Callback ID

HAL_RTC_MSPINIT_CB_ID

RTC Msp Init callback ID

HAL_RTC_MSPDEINIT_CB_ID

RTC Msp DeInit callback ID

Definition at line 210 of file stm32wbxx_hal_rtc.h.

enum HAL_RTCStateTypeDef

HAL State structures definition.

Enumerator:
HAL_RTC_STATE_RESET

RTC not yet initialized or disabled

HAL_RTC_STATE_READY

RTC initialized and ready for use

HAL_RTC_STATE_BUSY

RTC process is ongoing

HAL_RTC_STATE_TIMEOUT

RTC timeout state

HAL_RTC_STATE_ERROR

RTC error state

Definition at line 50 of file stm32wbxx_hal_rtc.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_InitTypeDef Struct Reference
RTC Exported Types

RTC Configuration Structure definition. More...

#include <stm32wbxx_hal_rtc.h>

Data Fields

uint32_t | HourFormat
uint32_t | AsynchPrediv
uint32_t | SynchPrediv
uint32_t | OutPut
uint32_t | OutPutRemap
uint32_t | OutPutPolarity
uint32_t | OutPutType

Detailed Description

RTC Configuration Structure definition.

Definition at line 63 of file stm32wbxx_hal_rtc.h.

Field Documentation

uint32_t RTC_InitTypeDef::AsynchPrediv

Specifies the RTC Asynchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F

Definition at line 68 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::HourFormat

Specifies the RTC Hour Format. This parameter can be a value of RTC Hour Formats

Definition at line 65 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::OutPut

Specifies which signal will be routed to the RTC output. This parameter can be a value of RTCEx Output Selection Definition

Definition at line 74 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::OutPutPolarity

Specifies the polarity of the output signal. This parameter can be a value of RTC Output Polarity Definitions

Definition at line 80 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::OutPutRemap

Specifies the remap for RTC output. This parameter can be a value of RTC Output ALARM OUT Remap

Definition at line 77 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::OutPutType

Specifies the RTC Output Pin mode. This parameter can be a value of RTC Output Type ALARM OUT

Definition at line 83 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::SynchPrediv

Specifies the RTC Synchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF

Definition at line 71 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_Init().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_rtc.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC_TimeTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_TimeTypeDef Struct Reference
RTC Exported Types

RTC Time structure definition. More...

#include <stm32wbxx_hal_rtc.h>

Data Fields

uint8_t | Hours
uint8_t | Minutes
uint8_t | Seconds
uint8_t | TimeFormat
uint32_t | SubSeconds
uint32_t | SecondFraction
uint32_t | DayLightSaving
uint32_t | StoreOperation

Detailed Description

RTC Time structure definition.

Definition at line 90 of file stm32wbxx_hal_rtc.h.

Field Documentation

uint32_t RTC_TimeTypeDef::DayLightSaving

Specifies RTC_DayLightSaveOperation: the value of hour adjustment. This parameter can be a value of RTC DayLightSaving Definitions

Definition at line 115 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_SetTime().

uint8_t RTC_TimeTypeDef::Hours

Specifies the RTC Time Hour. This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected. This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected

Definition at line 92 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_TimeTypeDef::Minutes

Specifies the RTC Time Minutes. This parameter must be a number between Min_Data = 0 and Max_Data = 59

Definition at line 96 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

uint32_t RTC_TimeTypeDef::SecondFraction

Specifies the range or granularity of Sub Second register content corresponding to Synchronous pre-scaler factor value (PREDIV_S) This parameter corresponds to a time unit range between [0-1] Second with [1 Sec / SecondFraction +1] granularity. This field will be used only by HAL_RTC_GetTime function

Definition at line 109 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_GetTime().

uint8_t RTC_TimeTypeDef::Seconds

Specifies the RTC Time Seconds. This parameter must be a number between Min_Data = 0 and Max_Data = 59

Definition at line 99 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

uint32_t RTC_TimeTypeDef::StoreOperation

Specifies RTC_StoreOperation value to be written in the BCK bit in CR register to store the operation. This parameter can be a value of RTC StoreOperation Definitions

Definition at line 118 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_SetTime().

uint32_t RTC_TimeTypeDef::SubSeconds

Specifies the RTC_SSR RTC Sub Second register content. This parameter corresponds to a time unit range between [0-1] Second with [1 Sec / SecondFraction +1] granularity

Definition at line 105 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_TimeTypeDef::TimeFormat

Specifies the RTC AM/PM Time. This parameter can be a value of RTC AM PM Definitions

Definition at line 102 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_rtc.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC_DateTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_DateTypeDef Struct Reference
RTC Exported Types

RTC Date structure definition. More...

#include <stm32wbxx_hal_rtc.h>

Data Fields

uint8_t | WeekDay
uint8_t | Month
uint8_t | Date
uint8_t | Year

Detailed Description

RTC Date structure definition.

Definition at line 126 of file stm32wbxx_hal_rtc.h.

Field Documentation

uint8_t RTC_DateTypeDef::Date

Specifies the RTC Date. This parameter must be a number between Min_Data = 1 and Max_Data = 31

Definition at line 134 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_DateTypeDef::Month

Specifies the RTC Date Month (in BCD format). This parameter can be a value of RTC Month Date Definitions

Definition at line 131 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_DateTypeDef::WeekDay

Specifies the RTC Date WeekDay. This parameter can be a value of RTC WeekDay Definitions

Definition at line 128 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_DateTypeDef::Year

Specifies the RTC Date Year. This parameter must be a number between Min_Data = 0 and Max_Data = 99

Definition at line 137 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_rtc.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC_AlarmTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_AlarmTypeDef Struct Reference
RTC Exported Types

RTC Alarm structure definition. More...

#include <stm32wbxx_hal_rtc.h>

Data Fields

RTC_TimeTypeDef AlarmTime
uint32_t | AlarmMask
uint32_t | AlarmSubSecondMask
uint32_t | AlarmDateWeekDaySel
uint8_t | AlarmDateWeekDay
uint32_t | Alarm

Detailed Description

RTC Alarm structure definition.

Definition at line 145 of file stm32wbxx_hal_rtc.h.

Field Documentation

uint32_t RTC_AlarmTypeDef::Alarm

Specifies the alarm . This parameter can be a value of RTC Alarms Definitions

Definition at line 162 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

uint8_t RTC_AlarmTypeDef::AlarmDateWeekDay

Specifies the RTC Alarm Date/WeekDay. If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range. If the Alarm WeekDay is selected, this parameter can be a value of RTC WeekDay Definitions

Definition at line 158 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

uint32_t RTC_AlarmTypeDef::AlarmDateWeekDaySel

Specifies the RTC Alarm is on Date or WeekDay. This parameter can be a value of RTC AlarmDateWeekDay Definitions

Definition at line 155 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

uint32_t RTC_AlarmTypeDef::AlarmMask

Specifies the RTC Alarm Masks. This parameter can be a value of RTC AlarmMask Definitions

Definition at line 149 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

uint32_t RTC_AlarmTypeDef::AlarmSubSecondMask

Specifies the RTC Alarm SubSeconds Masks. This parameter can be a value of RTC Alarm Sub Seconds Masks Definitions

Definition at line 152 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

RTC_TimeTypeDef RTC_AlarmTypeDef::AlarmTime

Specifies the RTC Alarm Time members

Definition at line 147 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_rtc.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: __RTC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__RTC_HandleTypeDef Struct Reference
RTC Exported Types

RTC Handle Structure definition. More...

#include <stm32wbxx_hal_rtc.h>

Data Fields

RTC_TypeDef * | Instance
RTC_InitTypeDef Init
HAL_LockTypeDef | Lock
__IO HAL_RTCStateTypeDef | State
void(* | AlarmAEventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | AlarmBEventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | TimeStampEventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | WakeUpTimerEventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | Tamper1EventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | Tamper2EventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | Tamper3EventCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | MspInitCallback )(struct __RTC_HandleTypeDef *hrtc)
void(* | MspDeInitCallback )(struct __RTC_HandleTypeDef *hrtc)

Detailed Description

RTC Handle Structure definition.

Definition at line 170 of file stm32wbxx_hal_rtc.h.

Field Documentation

void(* __RTC_HandleTypeDef::AlarmAEventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Alarm A Event callback

Definition at line 184 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_Init(), HAL_RTC_RegisterCallback(), and HAL_RTC_UnRegisterCallback().

void(* __RTC_HandleTypeDef::AlarmBEventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Alarm B Event callback

Definition at line 186 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_Init(), HAL_RTC_RegisterCallback(), and HAL_RTC_UnRegisterCallback().

RTC_InitTypeDef __RTC_HandleTypeDef::Init

RTC required parameters

Definition at line 177 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_Init().

RTC_TypeDef* __RTC_HandleTypeDef::Instance

Register base address

Definition at line 175 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_DeInit(), HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_Init(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTC_WaitForSynchro(), HAL_RTCEx_BKUPRead(), HAL_RTCEx_BKUPWrite(), HAL_RTCEx_DeactivateRefClock(), HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_DisableBypassShadow(), HAL_RTCEx_EnableBypassShadow(), HAL_RTCEx_GetTimeStamp(), HAL_RTCEx_GetWakeUpTimer(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetRefClock(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTamper(), HAL_RTCEx_SetTamper_IT(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), and RTC_EnterInitMode().

HAL_LockTypeDef __RTC_HandleTypeDef::Lock

RTC locking object

Definition at line 179 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_Init().

void(* __RTC_HandleTypeDef::MspDeInitCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Msp DeInit callback

Definition at line 200 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_DeInit(), HAL_RTC_Init(), HAL_RTC_RegisterCallback(), and HAL_RTC_UnRegisterCallback().

void(* __RTC_HandleTypeDef::MspInitCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Msp Init callback

Definition at line 198 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), and HAL_RTC_UnRegisterCallback().

__IO HAL_RTCStateTypeDef __RTC_HandleTypeDef::State

Time communication state

Definition at line 181 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_GetState(), HAL_RTC_Init(), HAL_RTC_PollForAlarmAEvent(), HAL_RTC_RegisterCallback(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTC_UnRegisterCallback(), HAL_RTCEx_DeactivateCalibrationOutPut(), HAL_RTCEx_DeactivateInternalTimeStamp(), HAL_RTCEx_DeactivateRefClock(), HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_DisableBypassShadow(), HAL_RTCEx_EnableBypassShadow(), HAL_RTCEx_PollForAlarmBEvent(), HAL_RTCEx_PollForTamper1Event(), HAL_RTCEx_PollForTamper2Event(), HAL_RTCEx_PollForTamper3Event(), HAL_RTCEx_PollForTimeStampEvent(), HAL_RTCEx_PollForWakeUpTimerEvent(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetInternalTimeStamp(), HAL_RTCEx_SetRefClock(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTamper(), HAL_RTCEx_SetTamper_IT(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), HAL_RTCEx_TamperTimeStampIRQHandler(), and HAL_RTCEx_WakeUpTimerIRQHandler().

void(* __RTC_HandleTypeDef::Tamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Tamper 1 Event callback

Definition at line 192 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperTimeStampIRQHandler().

void(* __RTC_HandleTypeDef::Tamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Tamper 2 Event callback

Definition at line 194 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperTimeStampIRQHandler().

void(* __RTC_HandleTypeDef::Tamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC Tamper 3 Event callback

Definition at line 196 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperTimeStampIRQHandler().

void(* __RTC_HandleTypeDef::TimeStampEventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC TimeStamp Event callback

Definition at line 188 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperTimeStampIRQHandler().

void(* __RTC_HandleTypeDef::WakeUpTimerEventCallback)(struct __RTC_HandleTypeDef *hrtc)

RTC WakeUpTimer Event callback

Definition at line 190 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_RegisterCallback(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_WakeUpTimerIRQHandler().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_rtc.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC Hour Formats

Defines
RTC Hour Formats
RTC Exported Constants

Defines

#define | RTC_HOURFORMAT_24 ((uint32_t)0x00000000U)
#define | RTC_HOURFORMAT_12 ((uint32_t)RTC_CR_FMT)

Define Documentation

#define RTC_HOURFORMAT_12 ((uint32_t)RTC_CR_FMT)

Definition at line 246 of file stm32wbxx_hal_rtc.h.

#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000U)

Definition at line 245 of file stm32wbxx_hal_rtc.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC Output Polarity Definitions

Defines
RTC Output Polarity Definitions
RTC Exported Constants

Defines

#define | RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000U)
#define | RTC_OUTPUT_POLARITY_LOW ((uint32_t)RTC_CR_POL)

Define Documentation

#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000U)

Definition at line 256 of file stm32wbxx_hal_rtc.h.

#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)RTC_CR_POL)

Definition at line 257 of file stm32wbxx_hal_rtc.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC Output Type ALARM OUT

Defines
RTC Output Type ALARM OUT
RTC Exported Constants

Defines

#define | RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000U)
#define | RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)RTC_OR_ALARMOUTTYPE)

Define Documentation

#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000U)

Definition at line 266 of file stm32wbxx_hal_rtc.h.

#define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)RTC_OR_ALARMOUTTYPE)

Definition at line 267 of file stm32wbxx_hal_rtc.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC Output ALARM OUT Remap

Defines
RTC Output ALARM OUT Remap
RTC Exported Constants

Defines

#define | RTC_OUTPUT_REMAP_NONE ((uint32_t)0x00000000U)
#define | RTC_OUTPUT_REMAP_POS1 ((uint32_t)RTC_OR_OUT_RMP)

Define Documentation

#define RTC_OUTPUT_REMAP_NONE ((uint32_t)0x00000000U)

Definition at line 276 of file stm32wbxx_hal_rtc.h.

#define RTC_OUTPUT_REMAP_POS1 ((uint32_t)RTC_OR_OUT_RMP)

Definition at line 277 of file stm32wbxx_hal_rtc.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC AM PM Definitions

Defines
RTC AM PM Definitions
RTC Exported Constants

Defines

#define | RTC_HOURFORMAT12_AM ((uint8_t)0x00U)
#define | RTC_HOURFORMAT12_PM ((uint8_t)0x40U)

Define Documentation

#define RTC_HOURFORMAT12_AM ((uint8_t)0x00U)

Definition at line 285 of file stm32wbxx_hal_rtc.h.

#define RTC_HOURFORMAT12_PM ((uint8_t)0x40U)

Definition at line 286 of file stm32wbxx_hal_rtc.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC DayLightSaving Definitions

Defines
RTC DayLightSaving Definitions
RTC Exported Constants

Defines

#define | RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)RTC_CR_SUB1H)
#define | RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)RTC_CR_ADD1H)
#define | RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000U)

Define Documentation

#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)RTC_CR_ADD1H)

Definition at line 296 of file stm32wbxx_hal_rtc.h.

#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000U)

Definition at line 297 of file stm32wbxx_hal_rtc.h.

#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)RTC_CR_SUB1H)

Definition at line 295 of file stm32wbxx_hal_rtc.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC StoreOperation Definitions

Defines
RTC StoreOperation Definitions
RTC Exported Constants

Defines

#define | RTC_STOREOPERATION_RESET ((uint32_t)0x00000000U)
#define | RTC_STOREOPERATION_SET ((uint32_t)RTC_CR_BKP)

Define Documentation

#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000U)

Definition at line 306 of file stm32wbxx_hal_rtc.h.

#define RTC_STOREOPERATION_SET ((uint32_t)RTC_CR_BKP)

Definition at line 307 of file stm32wbxx_hal_rtc.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC Input Parameter Format Definitions

Defines
RTC Input Parameter Format Definitions
RTC Exported Constants

Defines

#define | RTC_FORMAT_BIN ((uint32_t)0x000000000U)
#define | RTC_FORMAT_BCD ((uint32_t)0x000000001U)

Define Documentation

#define RTC_FORMAT_BCD ((uint32_t)0x000000001U)

Definition at line 317 of file stm32wbxx_hal_rtc.h.

#define RTC_FORMAT_BIN ((uint32_t)0x000000000U)

Definition at line 316 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC Month Date Definitions

Defines
RTC Month Date Definitions
RTC Exported Constants

Defines

#define | RTC_MONTH_JANUARY ((uint8_t)0x01U)
#define | RTC_MONTH_FEBRUARY ((uint8_t)0x02U)
#define | RTC_MONTH_MARCH ((uint8_t)0x03U)
#define | RTC_MONTH_APRIL ((uint8_t)0x04U)
#define | RTC_MONTH_MAY ((uint8_t)0x05U)
#define | RTC_MONTH_JUNE ((uint8_t)0x06U)
#define | RTC_MONTH_JULY ((uint8_t)0x07U)
#define | RTC_MONTH_AUGUST ((uint8_t)0x08U)
#define | RTC_MONTH_SEPTEMBER ((uint8_t)0x09U)
#define | RTC_MONTH_OCTOBER ((uint8_t)0x10U)
#define | RTC_MONTH_NOVEMBER ((uint8_t)0x11U)
#define | RTC_MONTH_DECEMBER ((uint8_t)0x12U)

Define Documentation

#define RTC_MONTH_APRIL ((uint8_t)0x04U)

Definition at line 331 of file stm32wbxx_hal_rtc.h.

#define RTC_MONTH_AUGUST ((uint8_t)0x08U)

Definition at line 335 of file stm32wbxx_hal_rtc.h.

#define RTC_MONTH_DECEMBER ((uint8_t)0x12U)

Definition at line 339 of file stm32wbxx_hal_rtc.h.

#define RTC_MONTH_FEBRUARY ((uint8_t)0x02U)

Definition at line 329 of file stm32wbxx_hal_rtc.h.

#define RTC_MONTH_JANUARY ((uint8_t)0x01U)

Definition at line 328 of file stm32wbxx_hal_rtc.h.

#define RTC_MONTH_JULY ((uint8_t)0x07U)

Definition at line 334 of file stm32wbxx_hal_rtc.h.

#define RTC_MONTH_JUNE ((uint8_t)0x06U)

Definition at line 333 of file stm32wbxx_hal_rtc.h.

#define RTC_MONTH_MARCH ((uint8_t)0x03U)

Definition at line 330 of file stm32wbxx_hal_rtc.h.

#define RTC_MONTH_MAY ((uint8_t)0x05U)

Definition at line 332 of file stm32wbxx_hal_rtc.h.

#define RTC_MONTH_NOVEMBER ((uint8_t)0x11U)

Definition at line 338 of file stm32wbxx_hal_rtc.h.

#define RTC_MONTH_OCTOBER ((uint8_t)0x10U)

Definition at line 337 of file stm32wbxx_hal_rtc.h.

#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09U)

Definition at line 336 of file stm32wbxx_hal_rtc.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC WeekDay Definitions

Defines
RTC WeekDay Definitions
RTC Exported Constants

Defines

#define | RTC_WEEKDAY_MONDAY ((uint8_t)0x01U)
#define | RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U)
#define | RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U)
#define | RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U)
#define | RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U)
#define | RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U)
#define | RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U)

Define Documentation

#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U)

Definition at line 352 of file stm32wbxx_hal_rtc.h.

#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01U)

Definition at line 348 of file stm32wbxx_hal_rtc.h.

#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U)

Definition at line 353 of file stm32wbxx_hal_rtc.h.

#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U)

Definition at line 354 of file stm32wbxx_hal_rtc.h.

#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U)

Definition at line 351 of file stm32wbxx_hal_rtc.h.

#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U)

Definition at line 349 of file stm32wbxx_hal_rtc.h.

#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U)

Definition at line 350 of file stm32wbxx_hal_rtc.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC AlarmDateWeekDay Definitions

Defines
RTC AlarmDateWeekDay Definitions
RTC Exported Constants

Defines

#define | RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000U)
#define | RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL

Define Documentation

#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000U)

Definition at line 363 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL

Definition at line 364 of file stm32wbxx_hal_rtc.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC AlarmMask Definitions

Defines
RTC AlarmMask Definitions
RTC Exported Constants

Defines

#define | RTC_ALARMMASK_NONE ((uint32_t)0x00000000U)
#define | RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define | RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
#define | RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
#define | RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
#define | RTC_ALARMMASK_ALL

Define Documentation

#define RTC_ALARMMASK_ALL
Value:
((uint32_t) (RTC_ALARMMASK_NONE        | \
                                                     RTC_ALARMMASK_DATEWEEKDAY | \
                                                     RTC_ALARMMASK_HOURS       | \
                                                     RTC_ALARMMASK_MINUTES     | \
                                                     RTC_ALARMMASK_SECONDS))

Definition at line 378 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm().

#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4

Definition at line 374 of file stm32wbxx_hal_rtc.h.

#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3

Definition at line 375 of file stm32wbxx_hal_rtc.h.

#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2

Definition at line 376 of file stm32wbxx_hal_rtc.h.

#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000U)

Definition at line 373 of file stm32wbxx_hal_rtc.h.

#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1

Definition at line 377 of file stm32wbxx_hal_rtc.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC Alarms Definitions

Defines
RTC Alarms Definitions
RTC Exported Constants

Defines

#define | RTC_ALARM_A RTC_CR_ALRAE
#define | RTC_ALARM_B RTC_CR_ALRBE

Define Documentation

#define RTC_ALARM_A RTC_CR_ALRAE

Definition at line 391 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_ALARM_B RTC_CR_ALRBE

Definition at line 392 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC Alarm Sub Seconds Masks Definitions

Defines
RTC Alarm Sub Seconds Masks Definitions
RTC Exported Constants

Defines

#define | RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000U)
#define | RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0
#define | RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1
#define | RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1))
#define | RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2
#define | RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2))
#define | RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t) (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2))
#define | RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2))
#define | RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3
#define | RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3))
#define | RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t) (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3))
#define | RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3))
#define | RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t) (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3))
#define | RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3))
#define | RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t) (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3))
#define | RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS

Define Documentation

#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000U)

All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm

Definition at line 402 of file stm32wbxx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS

SS[14:0] are compared and must match to activate alarm.

Definition at line 433 of file stm32wbxx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t) (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3))

SS[14] is don't care in Alarm comparison.Only SS[13:0] are compared

Definition at line 431 of file stm32wbxx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0

SS[14:1] are don't care in Alarm comparison. Only SS[0] is compared.

Definition at line 405 of file stm32wbxx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t) (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3))

SS[14:10] are don't care in Alarm comparison. Only SS[9:0] are compared

Definition at line 423 of file stm32wbxx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3))

SS[14:11] are don't care in Alarm comparison. Only SS[10:0] are compared

Definition at line 425 of file stm32wbxx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t) (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3))

SS[14:12] are don't care in Alarm comparison.Only SS[11:0] are compared

Definition at line 427 of file stm32wbxx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3))

SS[14:13] are don't care in Alarm comparison. Only SS[12:0] are compared

Definition at line 429 of file stm32wbxx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1

SS[14:2] are don't care in Alarm comparison. Only SS[1:0] are compared

Definition at line 407 of file stm32wbxx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1))

SS[14:3] are don't care in Alarm comparison. Only SS[2:0] are compared

Definition at line 409 of file stm32wbxx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2

SS[14:4] are don't care in Alarm comparison. Only SS[3:0] are compared

Definition at line 411 of file stm32wbxx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2))

SS[14:5] are don't care in Alarm comparison. Only SS[4:0] are compared

Definition at line 413 of file stm32wbxx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t) (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2))

SS[14:6] are don't care in Alarm comparison. Only SS[5:0] are compared

Definition at line 415 of file stm32wbxx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2))

SS[14:7] are don't care in Alarm ` comparison. Only SS[6:0] are compared

Definition at line 417 of file stm32wbxx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3

SS[14:8] are don't care in Alarm comparison. Only SS[7:0] are compared

Definition at line 419 of file stm32wbxx_hal_rtc.h.

#define RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3))

SS[14:9] are don't care in Alarm comparison. Only SS[8:0] are compared

Definition at line 421 of file stm32wbxx_hal_rtc.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC Interrupts Definitions

Defines
RTC Interrupts Definitions
RTC Exported Constants

Defines

#define | RTC_IT_TS ((uint32_t)RTC_CR_TSIE)
#define | RTC_IT_WUT ((uint32_t)RTC_CR_WUTIE)
#define | RTC_IT_ALRA ((uint32_t)RTC_CR_ALRAIE)
#define | RTC_IT_ALRB ((uint32_t)RTC_CR_ALRBIE)
#define | RTC_IT_TAMP ((uint32_t)RTC_TAMPCR_TAMPIE)
#define | RTC_IT_TAMP1 ((uint32_t)RTC_TAMPCR_TAMP1IE)
#define | RTC_IT_TAMP2 ((uint32_t)RTC_TAMPCR_TAMP2IE)

Define Documentation

#define RTC_IT_ALRA ((uint32_t)RTC_CR_ALRAIE)

Enable Alarm A Interrupt

Definition at line 444 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_IT_ALRB ((uint32_t)RTC_CR_ALRBIE)

Enable Alarm B Interrupt

Definition at line 445 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_IT_TAMP ((uint32_t)RTC_TAMPCR_TAMPIE)

Enable all Tamper Interrupt

Definition at line 446 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateTamper(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_IT_TAMP1 ((uint32_t)RTC_TAMPCR_TAMP1IE)

Enable Tamper 1 Interrupt

Definition at line 448 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateTamper(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_IT_TAMP2 ((uint32_t)RTC_TAMPCR_TAMP2IE)

Enable Tamper 2 Interrupt

Definition at line 450 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateTamper(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_IT_TS ((uint32_t)RTC_CR_TSIE)

Enable Timestamp Interrupt

Definition at line 442 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_IT_WUT ((uint32_t)RTC_CR_WUTIE)

Enable Wakeup timer Interrupt

Definition at line 443 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC Flags Definitions

Defines
RTC Flags Definitions
RTC Exported Constants

Defines

#define | RTC_FLAG_RECALPF ((uint32_t)RTC_ISR_RECALPF)
#define | RTC_FLAG_TAMP2F ((uint32_t)RTC_ISR_TAMP2F)
#define | RTC_FLAG_TAMP1F ((uint32_t)RTC_ISR_TAMP1F)
#define | RTC_FLAG_TSOVF ((uint32_t)RTC_ISR_TSOVF)
#define | RTC_FLAG_TSF ((uint32_t)RTC_ISR_TSF)
#define | RTC_FLAG_ITSF ((uint32_t)RTC_ISR_ITSF)
#define | RTC_FLAG_WUTF ((uint32_t)RTC_ISR_WUTF)
#define | RTC_FLAG_ALRBF ((uint32_t)RTC_ISR_ALRBF)
#define | RTC_FLAG_ALRAF ((uint32_t)RTC_ISR_ALRAF)
#define | RTC_FLAG_INITF ((uint32_t)RTC_ISR_INITF)
#define | RTC_FLAG_RSF ((uint32_t)RTC_ISR_RSF)
#define | RTC_FLAG_INITS ((uint32_t)RTC_ISR_INITS)
#define | RTC_FLAG_SHPF ((uint32_t)RTC_ISR_SHPF)
#define | RTC_FLAG_WUTWF ((uint32_t)RTC_ISR_WUTWF)
#define | RTC_FLAG_ALRBWF ((uint32_t)RTC_ISR_ALRBWF)
#define | RTC_FLAG_ALRAWF ((uint32_t)RTC_ISR_ALRAWF)

Define Documentation

#define RTC_FLAG_ALRAF ((uint32_t)RTC_ISR_ALRAF)

Definition at line 471 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_PollForAlarmAEvent(), and HAL_RTC_SetAlarm_IT().

#define RTC_FLAG_ALRAWF ((uint32_t)RTC_ISR_ALRAWF)

Definition at line 478 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_FLAG_ALRBF ((uint32_t)RTC_ISR_ALRBF)

Definition at line 470 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_SetAlarm_IT(), and HAL_RTCEx_PollForAlarmBEvent().

#define RTC_FLAG_ALRBWF ((uint32_t)RTC_ISR_ALRBWF)

Definition at line 477 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_FLAG_INITF ((uint32_t)RTC_ISR_INITF)

Definition at line 472 of file stm32wbxx_hal_rtc.h.

#define RTC_FLAG_INITS ((uint32_t)RTC_ISR_INITS)

Definition at line 474 of file stm32wbxx_hal_rtc.h.

#define RTC_FLAG_ITSF ((uint32_t)RTC_ISR_ITSF)

Definition at line 467 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTCEx_GetTimeStamp(), and HAL_RTCEx_SetInternalTimeStamp().

#define RTC_FLAG_RECALPF ((uint32_t)RTC_ISR_RECALPF)

Definition at line 459 of file stm32wbxx_hal_rtc.h.

#define RTC_FLAG_RSF ((uint32_t)RTC_ISR_RSF)

Definition at line 473 of file stm32wbxx_hal_rtc.h.

#define RTC_FLAG_SHPF ((uint32_t)RTC_ISR_SHPF)

Definition at line 475 of file stm32wbxx_hal_rtc.h.

#define RTC_FLAG_TAMP1F ((uint32_t)RTC_ISR_TAMP1F)

Definition at line 462 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTCEx_PollForTamper1Event(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_FLAG_TAMP2F ((uint32_t)RTC_ISR_TAMP2F)

Definition at line 460 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTCEx_PollForTamper2Event(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_FLAG_TSF ((uint32_t)RTC_ISR_TSF)

Definition at line 465 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTCEx_GetTimeStamp(), HAL_RTCEx_PollForTimeStampEvent(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define RTC_FLAG_TSOVF ((uint32_t)RTC_ISR_TSOVF)

Definition at line 464 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTCEx_PollForTimeStampEvent(), HAL_RTCEx_SetTimeStamp(), and HAL_RTCEx_SetTimeStamp_IT().

#define RTC_FLAG_WUTF ((uint32_t)RTC_ISR_WUTF)

Definition at line 469 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTCEx_PollForWakeUpTimerEvent(), HAL_RTCEx_SetWakeUpTimer_IT(), and HAL_RTCEx_WakeUpTimerIRQHandler().

#define RTC_FLAG_WUTWF ((uint32_t)RTC_ISR_WUTWF)

Definition at line 476 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC Exported Macros

Defines
RTC Exported Macros
RTC

Defines

#define | __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__)
Reset RTC handle state.
#define | __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)
Disable the write protection for RTC registers.
#define | __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)
Enable the write protection for RTC registers.
#define | __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
Enable the RTC ALARMA peripheral.
#define | __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
Disable the RTC ALARMA peripheral.
#define | __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
Enable the RTC ALARMB peripheral.
#define | __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
Disable the RTC ALARMB peripheral.
#define | __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) != 0U)? 1U : 0U)
Check whether the specified RTC Alarm interrupt has occurred or not.
#define | __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
Check whether the specified RTC Alarm interrupt has been enabled or not.
#define | __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U)
Get the selected RTC Alarm's flag status.
#define | __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT) | ((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Alarm's pending flags.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable interrupt on the RTC Alarm associated Exti line by core 1.
#define | __HAL_RTC_ALARM_EXTIC2_ENABLE_IT() (EXTI->C2IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable interrupt on the RTC Alarm associated Exti line by core 2.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable interrupt on the RTC Alarm associated Exti line by core 1.
#define | __HAL_RTC_ALARM_EXTIC2_DISABLE_IT() (EXTI->C2IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable interrupt on the RTC Alarm associated Exti line by core 2.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable event on the RTC Alarm associated Exti line by core 1.
#define | __HAL_RTC_ALARM_EXTIC2_ENABLE_EVENT() (EXTI->C2EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable event on the RTC Alarm associated Exti line by core 2.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable event on the RTC Alarm associated Exti line by core 1.
#define | __HAL_RTC_ALARM_EXTIC2_DISABLE_EVENT() (EXTI->C2EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable event on the RTC Alarm associated Exti line by core 2.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable rising edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable rising edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR1 & RTC_EXTI_LINE_ALARM_EVENT)
Check whether the RTC Alarm associated Exti line interrupt flag is set or notby core 1.
#define | __HAL_RTC_ALARM_EXTIC2_GET_FLAG() (EXTI->PR2 & RTC_EXTI_LINE_ALARM_EVENT)
Check whether the RTC Alarm associated Exti line interrupt flag is set or not by core 2.
#define | __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR1 = (RTC_EXTI_LINE_ALARM_EVENT))
Clear the RTC Alarm associated Exti line flag.
#define | __HAL_RTC_ALARM_EXTIC2_CLEAR_FLAG() (EXTI->PR2 = (RTC_EXTI_LINE_ALARM_EVENT))
Clear the RTC Alarm associated Exti line flag.
#define | __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_ALARM_EVENT)
Generate a Software interrupt on RTC Alarm associated Exti line.

Define Documentation

#define __HAL_RTC_ALARM_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT) | ((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))

Clear the RTC Alarm's pending flags.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC Alarm Flag sources to clear. This parameter can be:
  • RTC_FLAG_ALRAF
  • RTC_FLAG_ALRBF
Return values:
None

Definition at line 621 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_PollForAlarmAEvent(), HAL_RTC_SetAlarm_IT(), and HAL_RTCEx_PollForAlarmBEvent().

#define __HAL_RTC_ALARM_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))

Disable the RTC Alarm interrupt.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • RTC_IT_ALRA: Alarm A interrupt
  • RTC_IT_ALRB: Alarm B interrupt
Return values:
None

Definition at line 575 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), and HAL_RTC_SetAlarm().

#define __HAL_RTC_ALARM_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))

Enable the RTC Alarm interrupt.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • RTC_IT_ALRA: Alarm A interrupt
  • RTC_IT_ALRB: Alarm B interrupt
Return values:
None

Definition at line 564 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG ( ) (EXTI->PR1 = (RTC_EXTI_LINE_ALARM_EVENT))

Clear the RTC Alarm associated Exti line flag.

Return values:
None.

Definition at line 734 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler().

#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT ( ) (EXTI->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))

Disable event on the RTC Alarm associated Exti line by core 1.

Return values:
None.

Definition at line 664 of file stm32wbxx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE ( ) (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))

Disable falling edge trigger on the RTC Alarm associated Exti line.

Return values:
None.

Definition at line 683 of file stm32wbxx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_DISABLE_IT ( ) (EXTI->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))

Disable interrupt on the RTC Alarm associated Exti line by core 1.

Return values:
None

Definition at line 639 of file stm32wbxx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE ( ) (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))

Disable rising edge trigger on the RTC Alarm associated Exti line.

Return values:
None.

Definition at line 695 of file stm32wbxx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                             __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();  \
                                                             __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \
                                                           } while(0U)

Disable rising & falling edge trigger on the RTC Alarm associated Exti line.

Return values:
None.

Definition at line 712 of file stm32wbxx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT ( ) (EXTI->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)

Enable event on the RTC Alarm associated Exti line by core 1.

Return values:
None.

Definition at line 652 of file stm32wbxx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE ( ) (EXTI->FTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)

Enable falling edge trigger on the RTC Alarm associated Exti line.

Return values:
None.

Definition at line 677 of file stm32wbxx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_ENABLE_IT ( ) (EXTI->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)

Enable interrupt on the RTC Alarm associated Exti line by core 1.

Return values:
None

Definition at line 627 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE ( ) (EXTI->RTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)

Enable rising edge trigger on the RTC Alarm associated Exti line.

Return values:
None.

Definition at line 689 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                             __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();  \
                                                             __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \
                                                           } while(0U)

Enable rising & falling edge trigger on the RTC Alarm associated Exti line.

Return values:
None.

Definition at line 703 of file stm32wbxx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT ( ) (EXTI->SWIER1 |= RTC_EXTI_LINE_ALARM_EVENT)

Generate a Software interrupt on RTC Alarm associated Exti line.

Return values:
None.

Definition at line 747 of file stm32wbxx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_GET_FLAG ( ) (EXTI->PR1 & RTC_EXTI_LINE_ALARM_EVENT)

Check whether the RTC Alarm associated Exti line interrupt flag is set or notby core 1.

Return values:
Line Status.

Definition at line 722 of file stm32wbxx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTIC2_CLEAR_FLAG ( ) (EXTI->PR2 = (RTC_EXTI_LINE_ALARM_EVENT))

Clear the RTC Alarm associated Exti line flag.

Return values:
None.

Definition at line 740 of file stm32wbxx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTIC2_DISABLE_EVENT ( ) (EXTI->C2EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))

Disable event on the RTC Alarm associated Exti line by core 2.

Return values:
None.

Definition at line 670 of file stm32wbxx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTIC2_DISABLE_IT ( ) (EXTI->C2IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))

Disable interrupt on the RTC Alarm associated Exti line by core 2.

Return values:
None

Definition at line 645 of file stm32wbxx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTIC2_ENABLE_EVENT ( ) (EXTI->C2EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)

Enable event on the RTC Alarm associated Exti line by core 2.

Return values:
None.

Definition at line 658 of file stm32wbxx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTIC2_ENABLE_IT ( ) (EXTI->C2IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)

Enable interrupt on the RTC Alarm associated Exti line by core 2.

Return values:
None

Definition at line 633 of file stm32wbxx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTIC2_GET_FLAG ( ) (EXTI->PR2 & RTC_EXTI_LINE_ALARM_EVENT)

Check whether the RTC Alarm associated Exti line interrupt flag is set or not by core 2.

Return values:
Line Status.

Definition at line 728 of file stm32wbxx_hal_rtc.h.

#define __HAL_RTC_ALARM_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U)

Get the selected RTC Alarm's flag status.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC Alarm Flag sources to check. This parameter can be:
  • RTC_FLAG_ALRAF
  • RTC_FLAG_ALRBF
  • RTC_FLAG_ALRAWF
  • RTC_FLAG_ALRBWF
Return values:
None

Definition at line 610 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeactivateAlarm(), HAL_RTC_PollForAlarmAEvent(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTCEx_PollForAlarmBEvent().

#define __HAL_RTC_ALARM_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) != 0U)? 1U : 0U)

Check whether the specified RTC Alarm interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Alarm interrupt sources to check. This parameter can be:
  • RTC_IT_ALRA: Alarm A interrupt
  • RTC_IT_ALRB: Alarm B interrupt
Return values:
None

Definition at line 586 of file stm32wbxx_hal_rtc.h.

#define __HAL_RTC_ALARM_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)

Check whether the specified RTC Alarm interrupt has been enabled or not.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Alarm interrupt sources to check. This parameter can be:
  • RTC_IT_ALRA: Alarm A interrupt
  • RTC_IT_ALRB: Alarm B interrupt
Return values:
None

Definition at line 597 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler().

#define __HAL_RTC_ALARMA_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))

Disable the RTC ALARMA peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 539 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARMA_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))

Enable the RTC ALARMA peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 532 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARMB_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))

Disable the RTC ALARMB peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 553 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARMB_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))

Enable the RTC ALARMB peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 546 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{\
                                                      (__HANDLE__)->State = HAL_RTC_STATE_RESET;\
                                                      (__HANDLE__)->MspInitCallback = NULL;\
                                                      (__HANDLE__)->MspDeInitCallback = NULL;\
                                                     }while(0)

Reset RTC handle state.

Parameters:
__HANDLE__ RTC handle.
Return values:
None

Definition at line 497 of file stm32wbxx_hal_rtc.h.

#define __HAL_RTC_WRITEPROTECTION_DISABLE ( __HANDLE__ )
Value:
do{                                       \
                            (__HANDLE__)->Instance->WPR = 0xCAU;   \
                            (__HANDLE__)->Instance->WPR = 0x53U;   \
                          } while(0U)

Disable the write protection for RTC registers.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 511 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_Init(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_DeactivateCalibrationOutPut(), HAL_RTCEx_DeactivateInternalTimeStamp(), HAL_RTCEx_DeactivateRefClock(), HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_DisableBypassShadow(), HAL_RTCEx_EnableBypassShadow(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetInternalTimeStamp(), HAL_RTCEx_SetRefClock(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WRITEPROTECTION_ENABLE ( __HANDLE__ )
Value:
do{                                       \
                            (__HANDLE__)->Instance->WPR = 0xFFU;   \
                          } while(0U)

Enable the write protection for RTC registers.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 522 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_Init(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_DeactivateCalibrationOutPut(), HAL_RTCEx_DeactivateInternalTimeStamp(), HAL_RTCEx_DeactivateRefClock(), HAL_RTCEx_DeactivateTimeStamp(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_DisableBypassShadow(), HAL_RTCEx_EnableBypassShadow(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetInternalTimeStamp(), HAL_RTCEx_SetRefClock(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
RTC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_RTC_Init (RTC_HandleTypeDef *hrtc)
Initialize the RTC peripheral.
HAL_StatusTypeDef | HAL_RTC_DeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC peripheral.
HAL_StatusTypeDef | HAL_RTC_RegisterCallback (RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback)
Register a User RTC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_RTC_UnRegisterCallback (RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID)
Unregister an RTC Callback RTC callabck is redirected to the weak predefined callback.
__weak void | HAL_RTC_MspInit (RTC_HandleTypeDef *hrtc)
Initialize the RTC MSP.
__weak void | HAL_RTC_MspDeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
   [..] This section provides functions allowing to initialize and configure the
         RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
         RTC registers Write protection, enter and exit the RTC initialization mode,
         RTC registers synchronization check and reference clock detection enable.
         (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
             It is split into 2 programmable prescalers to minimize power consumption.
             (++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler.
             (++) When both prescalers are used, it is recommended to configure the
                 asynchronous prescaler to a high value to minimize power consumption.
         (#) All RTC registers are Write protected. Writing to the RTC registers
             is enabled by writing a key into the Write Protection register, RTC_WPR.
         (#) To configure the RTC Calendar, user application should enter
             initialization mode. In this mode, the calendar counter is stopped
             and its value can be updated. When the initialization sequence is
             complete, the calendar restarts counting after 4 RTCCLK cycles.
         (#) To read the calendar through the shadow registers after Calendar
             initialization, calendar update or after wakeup from low power modes
             the software must first clear the RSF flag. The software must then
             wait until it is set again before reading the calendar, which means
             that the calendar registers have been correctly copied into the
             RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function
             implements the above software sequence (RSF clear and RSF check).

Function Documentation

HAL_StatusTypeDef HAL_RTC_DeInit ( RTC_HandleTypeDef * hrtc )

DeInitialize the RTC peripheral.

Parameters:
hrtc RTC handle
Note:
This function doesn't reset the RTC Backup Data registers.
Return values:
HAL status

Definition at line 357 of file stm32wbxx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_MspDeInit(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_RESET, HAL_RTC_STATE_TIMEOUT, HAL_RTC_WaitForSynchro(), __RTC_HandleTypeDef::Instance, __RTC_HandleTypeDef::MspDeInitCallback, RTC_EnterInitMode(), RTC_TIMEOUT_VALUE, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_Init ( RTC_HandleTypeDef * hrtc )

Initialize the RTC peripheral.

Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 231 of file stm32wbxx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, __RTC_HandleTypeDef::AlarmAEventCallback, __RTC_HandleTypeDef::AlarmBEventCallback, assert_param, RTC_InitTypeDef::AsynchPrediv, HAL_RTC_AlarmAEventCallback(), HAL_RTC_MspDeInit(), HAL_RTC_MspInit(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_STATE_RESET, HAL_RTC_WaitForSynchro(), HAL_RTCEx_AlarmBEventCallback(), HAL_RTCEx_Tamper1EventCallback(), HAL_RTCEx_Tamper2EventCallback(), HAL_RTCEx_Tamper3EventCallback(), HAL_RTCEx_TimeStampEventCallback(), HAL_RTCEx_WakeUpTimerEventCallback(), RTC_InitTypeDef::HourFormat, __RTC_HandleTypeDef::Init, __RTC_HandleTypeDef::Instance, IS_RTC_ASYNCH_PREDIV, IS_RTC_HOUR_FORMAT, IS_RTC_OUTPUT, IS_RTC_OUTPUT_POL, IS_RTC_OUTPUT_REMAP, IS_RTC_OUTPUT_TYPE, IS_RTC_SYNCH_PREDIV, __RTC_HandleTypeDef::Lock, __RTC_HandleTypeDef::MspDeInitCallback, __RTC_HandleTypeDef::MspInitCallback, RTC_InitTypeDef::OutPut, RTC_InitTypeDef::OutPutPolarity, RTC_InitTypeDef::OutPutRemap, RTC_InitTypeDef::OutPutType, RTC_EnterInitMode(), __RTC_HandleTypeDef::State, RTC_InitTypeDef::SynchPrediv, __RTC_HandleTypeDef::Tamper1EventCallback, __RTC_HandleTypeDef::Tamper2EventCallback, __RTC_HandleTypeDef::Tamper3EventCallback, __RTC_HandleTypeDef::TimeStampEventCallback, and __RTC_HandleTypeDef::WakeUpTimerEventCallback.

void HAL_RTC_MspDeInit ( RTC_HandleTypeDef * hrtc )

DeInitialize the RTC MSP.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 708 of file stm32wbxx_hal_rtc.c.

Referenced by HAL_RTC_DeInit(), HAL_RTC_Init(), and HAL_RTC_UnRegisterCallback().

void HAL_RTC_MspInit ( RTC_HandleTypeDef * hrtc )

Initialize the RTC MSP.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 693 of file stm32wbxx_hal_rtc.c.

Referenced by HAL_RTC_Init(), and HAL_RTC_UnRegisterCallback().

HAL_StatusTypeDef HAL_RTC_RegisterCallback | ( | RTC_HandleTypeDef * | hrtc,
 |  | HAL_RTC_CallbackIDTypeDef | CallbackID,
 |  | pRTC_CallbackTypeDef | pCallback
 | ) |  |

Register a User RTC Callback To be used instead of the weak predefined callback.

Parameters:
hrtc | RTC handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID
  • HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID
  • HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID
  • HAL_RTC_WAKEUPTIMER_EVENT_CB_ID WakeUp Timer Event Callback ID
  • HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID (*)
  • HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID
  • HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID (*)
  • HAL_RTC_MSPINIT_CB_ID Msp Init callback ID
  • HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID
(*) Value not defined in all devices.
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 488 of file stm32wbxx_hal_rtc.c.

References __RTC_HandleTypeDef::AlarmAEventCallback, __RTC_HandleTypeDef::AlarmBEventCallback, HAL_RTC_ALARM_A_EVENT_CB_ID, HAL_RTC_ALARM_B_EVENT_CB_ID, HAL_RTC_MSPDEINIT_CB_ID, HAL_RTC_MSPINIT_CB_ID, HAL_RTC_STATE_READY, HAL_RTC_STATE_RESET, HAL_RTC_TAMPER1_EVENT_CB_ID, HAL_RTC_TAMPER2_EVENT_CB_ID, HAL_RTC_TAMPER3_EVENT_CB_ID, HAL_RTC_TIMESTAMP_EVENT_CB_ID, HAL_RTC_WAKEUPTIMER_EVENT_CB_ID, __RTC_HandleTypeDef::MspDeInitCallback, __RTC_HandleTypeDef::MspInitCallback, __RTC_HandleTypeDef::State, __RTC_HandleTypeDef::Tamper1EventCallback, __RTC_HandleTypeDef::Tamper2EventCallback, __RTC_HandleTypeDef::Tamper3EventCallback, __RTC_HandleTypeDef::TimeStampEventCallback, and __RTC_HandleTypeDef::WakeUpTimerEventCallback.

HAL_StatusTypeDef HAL_RTC_UnRegisterCallback | ( | RTC_HandleTypeDef * | hrtc,
 |  | HAL_RTC_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an RTC Callback RTC callabck is redirected to the weak predefined callback.

Parameters:
hrtc RTC handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID
  • HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID
  • HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID
  • HAL_RTC_WAKEUPTIMER_EVENT_CB_ID WakeUp Timer Event Callback ID
  • HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID (*)
  • HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID
  • HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID (*)
  • HAL_RTC_MSPINIT_CB_ID Msp Init callback ID
  • HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID
(*) Value not defined in all devices.
Return values:
HAL status

Definition at line 600 of file stm32wbxx_hal_rtc.c.

References __RTC_HandleTypeDef::AlarmAEventCallback, __RTC_HandleTypeDef::AlarmBEventCallback, HAL_RTC_ALARM_A_EVENT_CB_ID, HAL_RTC_ALARM_B_EVENT_CB_ID, HAL_RTC_AlarmAEventCallback(), HAL_RTC_MspDeInit(), HAL_RTC_MSPDEINIT_CB_ID, HAL_RTC_MspInit(), HAL_RTC_MSPINIT_CB_ID, HAL_RTC_STATE_READY, HAL_RTC_STATE_RESET, HAL_RTC_TAMPER1_EVENT_CB_ID, HAL_RTC_TAMPER2_EVENT_CB_ID, HAL_RTC_TAMPER3_EVENT_CB_ID, HAL_RTC_TIMESTAMP_EVENT_CB_ID, HAL_RTC_WAKEUPTIMER_EVENT_CB_ID, HAL_RTCEx_AlarmBEventCallback(), HAL_RTCEx_Tamper1EventCallback(), HAL_RTCEx_Tamper2EventCallback(), HAL_RTCEx_Tamper3EventCallback(), HAL_RTCEx_TimeStampEventCallback(), HAL_RTCEx_WakeUpTimerEventCallback(), __RTC_HandleTypeDef::MspDeInitCallback, __RTC_HandleTypeDef::MspInitCallback, __RTC_HandleTypeDef::State, __RTC_HandleTypeDef::Tamper1EventCallback, __RTC_HandleTypeDef::Tamper2EventCallback, __RTC_HandleTypeDef::Tamper3EventCallback, __RTC_HandleTypeDef::TimeStampEventCallback, and __RTC_HandleTypeDef::WakeUpTimerEventCallback.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC Time and Date functions

Functions
RTC Time and Date functions
RTC Exported Functions

RTC Time and Date functions. More...

Functions

HAL_StatusTypeDef | HAL_RTC_SetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Set RTC current time.
HAL_StatusTypeDef | HAL_RTC_GetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Get RTC current time.
HAL_StatusTypeDef | HAL_RTC_SetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Set RTC current date.
HAL_StatusTypeDef | HAL_RTC_GetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Get RTC current date.

Detailed Description

RTC Time and Date functions.

 ===============================================================================
                 ##### RTC Time and Date functions #####
 ===============================================================================

 [..] This section provides functions allowing to configure Time and Date features

Function Documentation

HAL_StatusTypeDef HAL_RTC_GetDate | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_DateTypeDef * | sDate,
 |  | uint32_t | Format
 | ) |  |

Get RTC current date.

Parameters:
hrtc | RTC handle
sDate | Pointer to Date structure
Format Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Note:
You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values in the higher-order calendar shadow registers to ensure consistency between the time and date values. Reading RTC current time locks the values in calendar shadow registers until Current date is read.
Return values:
HAL status

Definition at line 1033 of file stm32wbxx_hal_rtc.c.

References assert_param, RTC_DateTypeDef::Date, __RTC_HandleTypeDef::Instance, IS_RTC_FORMAT, RTC_DateTypeDef::Month, RTC_Bcd2ToByte(), RTC_DR_RESERVED_MASK, RTC_FORMAT_BIN, RTC_DateTypeDef::WeekDay, and RTC_DateTypeDef::Year.

HAL_StatusTypeDef HAL_RTC_GetTime | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TimeTypeDef * | sTime,
 |  | uint32_t | Format
 | ) |  |

Get RTC current time.

Parameters:
hrtc | RTC handle
sTime | Pointer to Time structure with Hours, Minutes and Seconds fields returned with input format (BIN or BCD), also SubSeconds field returning the RTC_SSR register content and SecondFraction field the Synchronous pre-scaler factor to be used for second fraction ratio computation.
Format Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Note:
You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds value in second fraction ratio with time unit following generic formula: Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values in the higher-order calendar shadow registers to ensure consistency between the time and date values. Reading RTC current time locks the values in calendar shadow registers until Current date is read to ensure consistency between the time and date values.
Return values:
HAL status

Definition at line 880 of file stm32wbxx_hal_rtc.c.

References assert_param, RTC_TimeTypeDef::Hours, __RTC_HandleTypeDef::Instance, IS_RTC_FORMAT, RTC_TimeTypeDef::Minutes, RTC_Bcd2ToByte(), RTC_FORMAT_BIN, RTC_TR_RESERVED_MASK, RTC_TimeTypeDef::SecondFraction, RTC_TimeTypeDef::Seconds, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

HAL_StatusTypeDef HAL_RTC_SetDate | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_DateTypeDef * | sDate,
 |  | uint32_t | Format
 | ) |  |

Set RTC current date.

Parameters:
hrtc | RTC handle
sDate | Pointer to date structure
Format specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 924 of file stm32wbxx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, RTC_DateTypeDef::Date, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_WaitForSynchro(), __RTC_HandleTypeDef::Instance, IS_RTC_DATE, IS_RTC_FORMAT, IS_RTC_MONTH, IS_RTC_WEEKDAY, IS_RTC_YEAR, RTC_DateTypeDef::Month, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_DR_RESERVED_MASK, RTC_EnterInitMode(), RTC_FORMAT_BIN, __RTC_HandleTypeDef::State, RTC_DateTypeDef::WeekDay, and RTC_DateTypeDef::Year.

HAL_StatusTypeDef HAL_RTC_SetTime | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TimeTypeDef * | sTime,
 |  | uint32_t | Format
 | ) |  |

Set RTC current time.

Parameters:
hrtc | RTC handle
sTime | Pointer to Time structure
Format Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 746 of file stm32wbxx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, RTC_TimeTypeDef::DayLightSaving, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_WaitForSynchro(), RTC_TimeTypeDef::Hours, __RTC_HandleTypeDef::Instance, IS_RTC_DAYLIGHT_SAVING, IS_RTC_FORMAT, IS_RTC_HOUR12, IS_RTC_HOUR24, IS_RTC_HOURFORMAT12, IS_RTC_MINUTES, IS_RTC_SECONDS, IS_RTC_STORE_OPERATION, RTC_TimeTypeDef::Minutes, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_EnterInitMode(), RTC_FORMAT_BIN, RTC_TR_RESERVED_MASK, RTC_TimeTypeDef::Seconds, __RTC_HandleTypeDef::State, RTC_TimeTypeDef::StoreOperation, and RTC_TimeTypeDef::TimeFormat.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC Alarm functions

Functions
RTC Alarm functions
RTC Exported Functions

RTC Alarm functions. More...

Functions

HAL_StatusTypeDef | HAL_RTC_SetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_SetAlarm_IT (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm with Interrupt.
HAL_StatusTypeDef | HAL_RTC_DeactivateAlarm (RTC_HandleTypeDef *hrtc, uint32_t Alarm)
Deactivate the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_GetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
Get the RTC Alarm value and masks.
void | HAL_RTC_AlarmIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Alarm interrupt request.
__weak void | HAL_RTC_AlarmAEventCallback (RTC_HandleTypeDef *hrtc)
Alarm A callback.
HAL_StatusTypeDef | HAL_RTC_PollForAlarmAEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle AlarmA Polling request.

Detailed Description

RTC Alarm functions.

 ===============================================================================
                 ##### RTC Alarm functions #####
 ===============================================================================

 [..] This section provides functions allowing to configure Alarm feature

Function Documentation

void HAL_RTC_AlarmAEventCallback ( RTC_HandleTypeDef * hrtc )

Alarm A callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1653 of file stm32wbxx_hal_rtc.c.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_Init(), and HAL_RTC_UnRegisterCallback().

void HAL_RTC_AlarmIRQHandler ( RTC_HandleTypeDef * hrtc )

Handle Alarm interrupt request.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1604 of file stm32wbxx_hal_rtc.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_EXTI_CLEAR_FLAG, __HAL_RTC_ALARM_GET_FLAG, __HAL_RTC_ALARM_GET_IT_SOURCE, __RTC_HandleTypeDef::AlarmAEventCallback, __RTC_HandleTypeDef::AlarmBEventCallback, HAL_RTC_AlarmAEventCallback(), HAL_RTC_STATE_READY, HAL_RTCEx_AlarmBEventCallback(), RTC_FLAG_ALRAF, RTC_FLAG_ALRBF, RTC_IT_ALRA, RTC_IT_ALRB, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_DeactivateAlarm | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Alarm
 | ) |  |

Deactivate the specified RTC Alarm.

Parameters:
hrtc RTC handle
Alarm Specifies the Alarm. This parameter can be one of the following values:
  • RTC_ALARM_A: AlarmA
  • RTC_ALARM_B: AlarmB
Return values:
HAL status

Definition at line 1450 of file stm32wbxx_hal_rtc.c.

References __HAL_RTC_ALARM_DISABLE_IT, __HAL_RTC_ALARM_GET_FLAG, __HAL_RTC_ALARMA_DISABLE, __HAL_RTC_ALARMB_DISABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, IS_RTC_ALARM, RTC_ALARM_A, RTC_FLAG_ALRAWF, RTC_FLAG_ALRBWF, RTC_IT_ALRA, RTC_IT_ALRB, RTC_TIMEOUT_VALUE, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_GetAlarm | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_AlarmTypeDef * | sAlarm,
 |  | uint32_t | Alarm,
 |  | uint32_t | Format
 | ) |  |

Get the RTC Alarm value and masks.

Parameters:
hrtc | RTC handle
sAlarm | Pointer to Date structure
Alarm Specifies the Alarm. This parameter can be one of the following values:
  • RTC_ALARM_A: AlarmA
  • RTC_ALARM_B: AlarmB
Format Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 1544 of file stm32wbxx_hal_rtc.c.

References RTC_AlarmTypeDef::Alarm, RTC_AlarmTypeDef::AlarmDateWeekDay, RTC_AlarmTypeDef::AlarmDateWeekDaySel, RTC_AlarmTypeDef::AlarmMask, RTC_AlarmTypeDef::AlarmTime, assert_param, RTC_TimeTypeDef::Hours, __RTC_HandleTypeDef::Instance, IS_RTC_ALARM, IS_RTC_FORMAT, RTC_TimeTypeDef::Minutes, RTC_ALARM_A, RTC_ALARM_B, RTC_ALARMMASK_ALL, RTC_Bcd2ToByte(), RTC_FORMAT_BIN, RTC_TimeTypeDef::Seconds, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle AlarmA Polling request.

Parameters:
hrtc | RTC handle
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1669 of file stm32wbxx_hal_rtc.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_ALRAF, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_SetAlarm | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_AlarmTypeDef * | sAlarm,
 |  | uint32_t | Format
 | ) |  |

Set the specified RTC Alarm.

Parameters:
hrtc | RTC handle
sAlarm | Pointer to Alarm structure
Format Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 1087 of file stm32wbxx_hal_rtc.c.

References __HAL_RTC_ALARM_DISABLE_IT, __HAL_RTC_ALARM_GET_FLAG, __HAL_RTC_ALARMA_DISABLE, __HAL_RTC_ALARMA_ENABLE, __HAL_RTC_ALARMB_DISABLE, __HAL_RTC_ALARMB_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, RTC_AlarmTypeDef::Alarm, RTC_AlarmTypeDef::AlarmDateWeekDay, RTC_AlarmTypeDef::AlarmDateWeekDaySel, RTC_AlarmTypeDef::AlarmMask, RTC_AlarmTypeDef::AlarmSubSecondMask, RTC_AlarmTypeDef::AlarmTime, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_TimeTypeDef::Hours, __RTC_HandleTypeDef::Instance, IS_RTC_ALARM, IS_RTC_ALARM_DATE_WEEKDAY_DATE, IS_RTC_ALARM_DATE_WEEKDAY_SEL, IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY, IS_RTC_ALARM_MASK, IS_RTC_ALARM_SUB_SECOND_MASK, IS_RTC_ALARM_SUB_SECOND_VALUE, IS_RTC_FORMAT, IS_RTC_HOUR12, IS_RTC_HOUR24, IS_RTC_HOURFORMAT12, IS_RTC_MINUTES, IS_RTC_SECONDS, RTC_TimeTypeDef::Minutes, RTC_ALARM_A, RTC_ALARMDATEWEEKDAYSEL_DATE, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_FLAG_ALRAWF, RTC_FLAG_ALRBWF, RTC_FORMAT_BIN, RTC_IT_ALRA, RTC_IT_ALRB, RTC_TIMEOUT_VALUE, RTC_TimeTypeDef::Seconds, __RTC_HandleTypeDef::State, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

HAL_StatusTypeDef HAL_RTC_SetAlarm_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_AlarmTypeDef * | sAlarm,
 |  | uint32_t | Format
 | ) |  |

Set the specified RTC Alarm with Interrupt.

Parameters:
hrtc | RTC handle
sAlarm | Pointer to Alarm structure
Format Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Note:
The Alarm register can only be written when the corresponding Alarm is disabled (Use the HAL_RTC_DeactivateAlarm()).
The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
Return values:
HAL status

Definition at line 1268 of file stm32wbxx_hal_rtc.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_ENABLE_IT, __HAL_RTC_ALARM_EXTI_ENABLE_IT, __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE, __HAL_RTC_ALARM_GET_FLAG, __HAL_RTC_ALARMA_DISABLE, __HAL_RTC_ALARMA_ENABLE, __HAL_RTC_ALARMB_DISABLE, __HAL_RTC_ALARMB_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, RTC_AlarmTypeDef::Alarm, RTC_AlarmTypeDef::AlarmDateWeekDay, RTC_AlarmTypeDef::AlarmDateWeekDaySel, RTC_AlarmTypeDef::AlarmMask, RTC_AlarmTypeDef::AlarmSubSecondMask, RTC_AlarmTypeDef::AlarmTime, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_TimeTypeDef::Hours, __RTC_HandleTypeDef::Instance, IS_RTC_ALARM, IS_RTC_ALARM_DATE_WEEKDAY_DATE, IS_RTC_ALARM_DATE_WEEKDAY_SEL, IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY, IS_RTC_ALARM_MASK, IS_RTC_ALARM_SUB_SECOND_MASK, IS_RTC_ALARM_SUB_SECOND_VALUE, IS_RTC_FORMAT, IS_RTC_HOUR12, IS_RTC_HOUR24, IS_RTC_HOURFORMAT12, IS_RTC_MINUTES, IS_RTC_SECONDS, RTC_TimeTypeDef::Minutes, RTC_ALARM_A, RTC_ALARMDATEWEEKDAYSEL_DATE, RTC_Bcd2ToByte(), RTC_ByteToBcd2(), RTC_FLAG_ALRAF, RTC_FLAG_ALRAWF, RTC_FLAG_ALRBF, RTC_FLAG_ALRBWF, RTC_FORMAT_BIN, RTC_IT_ALRA, RTC_IT_ALRB, RTC_TIMEOUT_VALUE, RTC_TimeTypeDef::Seconds, __RTC_HandleTypeDef::State, RTC_TimeTypeDef::SubSeconds, and RTC_TimeTypeDef::TimeFormat.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
RTC Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef HAL_RTC_WaitForSynchro (RTC_HandleTypeDef *hrtc)
Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Detailed Description

Peripheral Control functions.

 ===============================================================================
                     ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Wait for RTC Time and Date Synchronization

Function Documentation

HAL_StatusTypeDef HAL_RTC_WaitForSynchro ( RTC_HandleTypeDef * hrtc )

Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Note:
The RTC Resynchronization mode is write protected, use the __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
To read the calendar through the shadow registers after Calendar initialization, calendar update or after wakeup from low power modes the software must first clear the RSF flag. The software must then wait until it is set again before reading the calendar, which means that the calendar registers have been correctly copied into the RTC_TR and RTC_DR shadow registers.
Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 1728 of file stm32wbxx_hal_rtc.c.

References HAL_GetTick(), __RTC_HandleTypeDef::Instance, RTC_RSF_MASK, and RTC_TIMEOUT_VALUE.

Referenced by HAL_RTC_DeInit(), HAL_RTC_Init(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), and HAL_RTCEx_SetSynchroShift().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
RTC Exported Functions

Peripheral State functions. More...

Functions

HAL_RTCStateTypeDef HAL_RTC_GetState (RTC_HandleTypeDef *hrtc)
Return the RTC handle state.

Detailed Description

Peripheral State functions.

 ===============================================================================
                     ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Get RTC state

Function Documentation

HAL_RTCStateTypeDef HAL_RTC_GetState ( RTC_HandleTypeDef * hrtc )

Return the RTC handle state.

Parameters:
hrtc RTC handle
Return values:
HAL state

Definition at line 1772 of file stm32wbxx_hal_rtc.c.

References __RTC_HandleTypeDef::State.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC Private Constants

Defines
RTC Private Constants
RTC

Defines

#define | RTC_TR_RESERVED_MASK
#define | RTC_DR_RESERVED_MASK
#define | RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU)
#define | RTC_RSF_MASK ((uint32_t)~(RTC_ISR_INIT | RTC_ISR_RSF))
#define | RTC_TIMEOUT_VALUE 1000U
#define | RTC_EXTI_LINE_ALARM_EVENT (LL_EXTI_LINE_17)

Define Documentation

#define RTC_DR_RESERVED_MASK
Value:
((uint32_t) (RTC_DR_YT | RTC_DR_YU | RTC_DR_WDU | \
                                           RTC_DR_MT | RTC_DR_MU | RTC_DR_DT  | \
                                           RTC_DR_DU))

Definition at line 842 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and HAL_RTCEx_GetTimeStamp().

#define RTC_EXTI_LINE_ALARM_EVENT (LL_EXTI_LINE_17)

External interrupt line connected to the RTC Alarm event

Definition at line 850 of file stm32wbxx_hal_rtc.h.

#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU)

Definition at line 845 of file stm32wbxx_hal_rtc.h.

Referenced by RTC_EnterInitMode().

#define RTC_RSF_MASK ((uint32_t)~(RTC_ISR_INIT | RTC_ISR_RSF))

Definition at line 846 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_WaitForSynchro().

#define RTC_TIMEOUT_VALUE 1000U

Definition at line 848 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_WaitForSynchro(), HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), and RTC_EnterInitMode().

#define RTC_TR_RESERVED_MASK
Value:
((uint32_t) (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | \
                                           RTC_TR_MNT | RTC_TR_MNU| RTC_TR_ST | \
                                           RTC_TR_SU))

Definition at line 839 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_GetTime(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC Private macros to check input parameters

Defines
RTC Private macros to check input parameters
RTC Private Macros

Defines

#define | IS_RTC_HOUR_FORMAT(FORMAT)
#define | IS_RTC_OUTPUT_POL(POL)
#define | IS_RTC_OUTPUT_TYPE(TYPE)
#define | IS_RTC_OUTPUT_REMAP(REMAP)
#define | IS_RTC_HOURFORMAT12(PM)
#define | IS_RTC_DAYLIGHT_SAVING(SAVE)
#define | IS_RTC_STORE_OPERATION(OPERATION)
#define | IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
#define | IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99U)
#define | IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1U) && ((MONTH) <= (uint32_t)12U))
#define | IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1U) && ((DATE) <= (uint32_t)31U))
#define | IS_RTC_WEEKDAY(WEEKDAY)
#define | IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t)0U) && ((DATE) <= (uint32_t)31U))
#define | IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY)
#define | IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL)
#define | IS_RTC_ALARM_MASK(MASK) (((MASK) & ~(RTC_ALARMMASK_ALL)) == 0U)
#define | IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
#define | IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS)
#define | IS_RTC_ALARM_SUB_SECOND_MASK(MASK)
#define | IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FU)
#define | IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFFU)
#define | IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0U) && ((HOUR) <= (uint32_t)12U))
#define | IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23U)
#define | IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59U)
#define | IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59U)

Define Documentation

#define IS_RTC_ALARM ( ALARM ) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))

Definition at line 918 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_DATE_WEEKDAY_DATE ( DATE ) (((DATE) >(uint32_t)0U) && ((DATE) <= (uint32_t)31U))

Definition at line 903 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_DATE_WEEKDAY_SEL ( SEL )
Value:
(((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
                                            ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))

Definition at line 913 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY ( WEEKDAY )
Value:
(((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
                                                    ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))

Definition at line 905 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_MASK ( MASK ) (((MASK) & ~(RTC_ALARMMASK_ALL)) == 0U)

Definition at line 916 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_SUB_SECOND_MASK ( MASK )
Value:
(((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
                                              ((MASK) == RTC_ALARMSUBSECONDMASK_NONE))

Definition at line 922 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ALARM_SUB_SECOND_VALUE ( VALUE ) ((VALUE) <= RTC_ALRMASSR_SS)

Definition at line 920 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ASYNCH_PREDIV ( PREDIV ) ((PREDIV) <= (uint32_t)0x7FU)

Definition at line 939 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_DATE ( DATE ) (((DATE) >= (uint32_t)1U) && ((DATE) <= (uint32_t)31U))

Definition at line 893 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_SetDate().

#define IS_RTC_DAYLIGHT_SAVING ( SAVE )
Value:
(((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
                                      ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
                                      ((SAVE) == RTC_DAYLIGHTSAVING_NONE))

Definition at line 880 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_SetTime().

#define IS_RTC_FORMAT ( FORMAT ) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))

Definition at line 887 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

#define IS_RTC_HOUR12 ( HOUR ) (((HOUR) > (uint32_t)0U) && ((HOUR) <= (uint32_t)12U))

Definition at line 943 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_HOUR24 ( HOUR ) ((HOUR) <= (uint32_t)23U)

Definition at line 945 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_HOUR_FORMAT ( FORMAT )
Value:
(((FORMAT) == RTC_HOURFORMAT_12) || \
                                        ((FORMAT) == RTC_HOURFORMAT_24))

Definition at line 865 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_HOURFORMAT12 ( PM )
Value:
(((PM) == RTC_HOURFORMAT12_AM) || \
                                  ((PM) == RTC_HOURFORMAT12_PM))

Definition at line 877 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_MINUTES ( MINUTES ) ((MINUTES) <= (uint32_t)59U)

Definition at line 947 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_MONTH ( MONTH ) (((MONTH) >= (uint32_t)1U) && ((MONTH) <= (uint32_t)12U))

Definition at line 891 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_SetDate().

#define IS_RTC_OUTPUT_POL ( POL )
Value:
(((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
                                ((POL) == RTC_OUTPUT_POLARITY_LOW))

Definition at line 868 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_OUTPUT_REMAP ( REMAP )
Value:
(((REMAP) == RTC_OUTPUT_REMAP_NONE) || \
                                      ((REMAP) == RTC_OUTPUT_REMAP_POS1))

Definition at line 874 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_OUTPUT_TYPE ( TYPE )
Value:
(((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
                                  ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))

Definition at line 871 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_SECONDS ( SECONDS ) ((SECONDS) <= (uint32_t)59U)

Definition at line 949 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_STORE_OPERATION ( OPERATION )
Value:
(((OPERATION) == RTC_STOREOPERATION_RESET) || \
                                           ((OPERATION) == RTC_STOREOPERATION_SET))

Definition at line 884 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_SetTime().

#define IS_RTC_SYNCH_PREDIV ( PREDIV ) ((PREDIV) <= (uint32_t)0x7FFFU)

Definition at line 941 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_WEEKDAY ( WEEKDAY )
Value:
(((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
                                 ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
                                 ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
                                 ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
                                 ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
                                 ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
                                 ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))

Definition at line 895 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_SetDate().

#define IS_RTC_YEAR ( YEAR ) ((YEAR) <= (uint32_t)99U)

Definition at line 889 of file stm32wbxx_hal_rtc.h.

Referenced by HAL_RTC_SetDate().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC Private Functions

Functions
RTC Private Functions
RTC

Functions

HAL_StatusTypeDef | RTC_EnterInitMode (RTC_HandleTypeDef *hrtc)
Enter the RTC Initialization mode.
uint8_t | RTC_ByteToBcd2 (uint8_t Value)
Convert a 2 digit decimal to BCD format.
uint8_t | RTC_Bcd2ToByte (uint8_t Value)
Convert from 2 digit BCD to Binary.

Function Documentation

uint8_t RTC_Bcd2ToByte ( uint8_t Value )

Convert from 2 digit BCD to Binary.

Parameters:
Value BCD value to be converted
Return values:
Converted word

Definition at line 1844 of file stm32wbxx_hal_rtc.c.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), and HAL_RTCEx_GetTimeStamp().

uint8_t RTC_ByteToBcd2 ( uint8_t Value )

Convert a 2 digit decimal to BCD format.

Parameters:
Value Byte to be converted
Return values:
Converted byte

Definition at line 1825 of file stm32wbxx_hal_rtc.c.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), and HAL_RTC_SetTime().

HAL_StatusTypeDef RTC_EnterInitMode ( RTC_HandleTypeDef * hrtc )

Enter the RTC Initialization mode.

Note:
The RTC Initialization mode is write protected, use the __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 1795 of file stm32wbxx_hal_rtc.c.

References HAL_GetTick(), __RTC_HandleTypeDef::Instance, RTC_INIT_MASK, and RTC_TIMEOUT_VALUE.

Referenced by HAL_RTC_DeInit(), HAL_RTC_Init(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_DeactivateRefClock(), and HAL_RTCEx_SetRefClock().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTCEx Private Constants

Defines
RTCEx Private Constants
RTCEx

Defines

#define | RTC_TAMPCR_MASK
#define | RTC_FLAGS_MASK
#define | RTC_TAMPCR_TAMPXE ((uint32_t) (RTC_TAMPCR_TAMP3E | RTC_TAMPCR_TAMP2E | RTC_TAMPCR_TAMP1E))
#define | RTC_TAMPCR_TAMPXIE
#define | RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT (EXTI_IMR1_IM18)
#define | RTC_EXTI_LINE_WAKEUPTIMER_EVENT (EXTI_IMR1_IM19)

Define Documentation

#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT (EXTI_IMR1_IM18)

External interrupt line 18 Connected to the RTC Tamper and Time Stamp events

Definition at line 1202 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT (EXTI_IMR1_IM19)

External interrupt line 19 Connected to the RTC Wakeup event

Definition at line 1203 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_FLAGS_MASK
Value:
((uint32_t) (RTC_FLAG_RECALPF | RTC_FLAG_TAMP3F | RTC_FLAG_TAMP2F | \
                                             RTC_FLAG_TAMP1F| RTC_FLAG_TSOVF | RTC_FLAG_TSF       | \
                                             RTC_FLAG_WUTF | RTC_FLAG_ALRBF | RTC_FLAG_ALRAF      | \
                                             RTC_FLAG_INITF | RTC_FLAG_RSF                        | \
                                             RTC_FLAG_INITS | RTC_FLAG_SHPF | RTC_FLAG_WUTWF      | \
                                             RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF))

Definition at line 1177 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_TAMPCR_MASK
Value:
((uint32_t)RTC_TAMPCR_TAMPTS    |\
                                       (uint32_t)RTC_TAMPCR_TAMPFREQ  | (uint32_t)RTC_TAMPCR_TAMPFLT      | (uint32_t)RTC_TAMPCR_TAMPPRCH |\
                                       (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE                                       |\
                                       (uint32_t)RTC_TAMPCR_TAMP1IE   | (uint32_t)RTC_TAMPCR_TAMP1NOERASE | (uint32_t)RTC_TAMPCR_TAMP1MF  |\
                                       (uint32_t)RTC_TAMPCR_TAMP2IE   | (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP2MF  |\
                                       (uint32_t)RTC_TAMPCR_TAMP3IE   | (uint32_t)RTC_TAMPCR_TAMP3NOERASE | (uint32_t)RTC_TAMPCR_TAMP3MF)

Definition at line 124 of file stm32wbxx_hal_rtc_ex.c.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define RTC_TAMPCR_TAMPXE ((uint32_t) (RTC_TAMPCR_TAMP3E | RTC_TAMPCR_TAMP2E | RTC_TAMPCR_TAMP1E))

Definition at line 1184 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_TAMPCR_TAMPXIE
Value:
((uint32_t) (RTC_TAMPER1_INTERRUPT | RTC_TAMPER2_INTERRUPT | \
                                           RTC_TAMPER3_INTERRUPT | RTC_ALL_TAMPER_INTERRUPT))

Definition at line 1185 of file stm32wbxx_hal_rtc_ex.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC_TamperTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_TamperTypeDef Struct Reference
RTCEx Exported Types

RTC Tamper structure definition. More...

#include <stm32wbxx_hal_rtc_ex.h>

Data Fields

uint32_t | Tamper
uint32_t | Interrupt
uint32_t | Trigger
uint32_t | NoErase
uint32_t | MaskFlag
uint32_t | Filter
uint32_t | SamplingFrequency
uint32_t | PrechargeDuration
uint32_t | TamperPullUp
uint32_t | TimeStampOnTamperDetection

Detailed Description

RTC Tamper structure definition.

Definition at line 48 of file stm32wbxx_hal_rtc_ex.h.

Field Documentation

uint32_t RTC_TamperTypeDef::Filter

Specifies the RTC Filter Tamper. This parameter can be a value of RTCEx Tamper Filter Definitions

Definition at line 65 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::Interrupt

Specifies the Tamper Interrupt. This parameter can be a value of RTCEx Tamper Interrupt Definitions

Definition at line 53 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::MaskFlag

Specifies the Tamper Flag masking. This parameter can be a value of RTCEx Tamper MaskFlag Definitions

Definition at line 62 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::NoErase

Specifies the Tamper no erase mode. This parameter can be a value of RTCEx Tamper EraseBackUp Definitions

Definition at line 59 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::PrechargeDuration

Specifies the Precharge Duration . This parameter can be a value of RTCEx Tamper Pin Precharge Duration Definitions

Definition at line 71 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::SamplingFrequency

Specifies the sampling frequency. This parameter can be a value of RTCEx Tamper Sampling Frequencies Definitions

Definition at line 68 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::Tamper

Specifies the Tamper Pin. This parameter can be a value of RTCEx Tamper Pins Definition

Definition at line 50 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::TamperPullUp

Specifies the Tamper PullUp . This parameter can be a value of RTCEx Tamper Pull UP Definitions

Definition at line 74 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::TimeStampOnTamperDetection

Specifies the TimeStampOnTamperDetection. This parameter can be a value of RTCEx Tamper TimeStampOnTamperDetection Definitions

Definition at line 77 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::Trigger

Specifies the Tamper Trigger. This parameter can be a value of RTCEx Tamper Trigger Definitions

Definition at line 56 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_rtc_ex.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTCEx Output Selection Definition

Defines
RTCEx Output Selection Definition
RTCEx Exported Constants

Defines

#define | RTC_OUTPUT_DISABLE ((uint32_t)0x00000000U)
#define | RTC_OUTPUT_ALARMA ((uint32_t)RTC_CR_OSEL_0)
#define | RTC_OUTPUT_ALARMB ((uint32_t)RTC_CR_OSEL_1)
#define | RTC_OUTPUT_WAKEUP ((uint32_t)RTC_CR_OSEL)

Define Documentation

#define RTC_OUTPUT_ALARMA ((uint32_t)RTC_CR_OSEL_0)

Definition at line 93 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_OUTPUT_ALARMB ((uint32_t)RTC_CR_OSEL_1)

Definition at line 94 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000U)

Definition at line 92 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_OUTPUT_WAKEUP ((uint32_t)RTC_CR_OSEL)

Definition at line 95 of file stm32wbxx_hal_rtc_ex.h.

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STM32WB55xx HAL User Manual: RTCEx Backup Registers Definition

Defines
RTCEx Backup Registers Definition
RTCEx Exported Constants

Defines

#define | RTC_BKP_DR0 ((uint32_t)0x00000000U)
#define | RTC_BKP_DR1 ((uint32_t)0x00000001U)
#define | RTC_BKP_DR2 ((uint32_t)0x00000002U)
#define | RTC_BKP_DR3 ((uint32_t)0x00000003U)
#define | RTC_BKP_DR4 ((uint32_t)0x00000004U)
#define | RTC_BKP_DR5 ((uint32_t)0x00000005U)
#define | RTC_BKP_DR6 ((uint32_t)0x00000006U)
#define | RTC_BKP_DR7 ((uint32_t)0x00000007U)
#define | RTC_BKP_DR8 ((uint32_t)0x00000008U)
#define | RTC_BKP_DR9 ((uint32_t)0x00000009U)
#define | RTC_BKP_DR10 ((uint32_t)0x0000000AU)
#define | RTC_BKP_DR11 ((uint32_t)0x0000000BU)
#define | RTC_BKP_DR12 ((uint32_t)0x0000000CU)
#define | RTC_BKP_DR13 ((uint32_t)0x0000000DU)
#define | RTC_BKP_DR14 ((uint32_t)0x0000000EU)
#define | RTC_BKP_DR15 ((uint32_t)0x0000000FU)
#define | RTC_BKP_DR16 ((uint32_t)0x00000010U)
#define | RTC_BKP_DR17 ((uint32_t)0x00000011U)
#define | RTC_BKP_DR18 ((uint32_t)0x00000012U)
#define | RTC_BKP_DR19 ((uint32_t)0x00000013U)

Define Documentation

#define RTC_BKP_DR0 ((uint32_t)0x00000000U)

Definition at line 104 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_BKP_DR1 ((uint32_t)0x00000001U)

Definition at line 105 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_BKP_DR10 ((uint32_t)0x0000000AU)

Definition at line 114 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_BKP_DR11 ((uint32_t)0x0000000BU)

Definition at line 115 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_BKP_DR12 ((uint32_t)0x0000000CU)

Definition at line 116 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_BKP_DR13 ((uint32_t)0x0000000DU)

Definition at line 117 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_BKP_DR14 ((uint32_t)0x0000000EU)

Definition at line 118 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_BKP_DR15 ((uint32_t)0x0000000FU)

Definition at line 119 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_BKP_DR16 ((uint32_t)0x00000010U)

Definition at line 120 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_BKP_DR17 ((uint32_t)0x00000011U)

Definition at line 121 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_BKP_DR18 ((uint32_t)0x00000012U)

Definition at line 122 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_BKP_DR19 ((uint32_t)0x00000013U)

Definition at line 123 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_BKP_DR2 ((uint32_t)0x00000002U)

Definition at line 106 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_BKP_DR3 ((uint32_t)0x00000003U)

Definition at line 107 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_BKP_DR4 ((uint32_t)0x00000004U)

Definition at line 108 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_BKP_DR5 ((uint32_t)0x00000005U)

Definition at line 109 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_BKP_DR6 ((uint32_t)0x00000006U)

Definition at line 110 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_BKP_DR7 ((uint32_t)0x00000007U)

Definition at line 111 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_BKP_DR8 ((uint32_t)0x00000008U)

Definition at line 112 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_BKP_DR9 ((uint32_t)0x00000009U)

Definition at line 113 of file stm32wbxx_hal_rtc_ex.h.

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STM32WB55xx HAL User Manual: RTCEx Time Stamp Edges definition

Defines
RTCEx Time Stamp Edges definition
RTCEx Exported Constants

Defines

#define | RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000U)
#define | RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE

Define Documentation

#define RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE

Definition at line 134 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000U)

Definition at line 133 of file stm32wbxx_hal_rtc_ex.h.

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STM32WB55xx HAL User Manual: RTCEx TimeStamp Pin Selection

Defines
RTCEx TimeStamp Pin Selection
RTCEx Exported Constants

Defines

#define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000U)

Define Documentation

#define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000U)

Definition at line 143 of file stm32wbxx_hal_rtc_ex.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTCEx Tamper Pins Definition

Defines
RTCEx Tamper Pins Definition
RTCEx Exported Constants

Defines

#define | RTC_TAMPER_1 RTC_TAMPCR_TAMP1E
#define | RTC_TAMPER_2 RTC_TAMPCR_TAMP2E
#define | RTC_TAMPER_3 RTC_TAMPCR_TAMP3E

Define Documentation

#define RTC_TAMPER_1 RTC_TAMPCR_TAMP1E

Definition at line 154 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define RTC_TAMPER_2 RTC_TAMPCR_TAMP2E

Definition at line 157 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define RTC_TAMPER_3 RTC_TAMPCR_TAMP3E

Definition at line 160 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTCEx Tamper Interrupt Definitions

Defines
RTCEx Tamper Interrupt Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPER1_INTERRUPT RTC_TAMPCR_TAMP1IE
#define | RTC_TAMPER2_INTERRUPT RTC_TAMPCR_TAMP2IE
#define | RTC_TAMPER3_INTERRUPT RTC_TAMPCR_TAMP3IE
#define | RTC_ALL_TAMPER_INTERRUPT RTC_TAMPCR_TAMPIE

Define Documentation

#define RTC_ALL_TAMPER_INTERRUPT RTC_TAMPCR_TAMPIE

Definition at line 180 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_TAMPER1_INTERRUPT RTC_TAMPCR_TAMP1IE

Definition at line 171 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_TAMPER2_INTERRUPT RTC_TAMPCR_TAMP2IE

Definition at line 175 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_TAMPER3_INTERRUPT RTC_TAMPCR_TAMP3IE

Definition at line 178 of file stm32wbxx_hal_rtc_ex.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTCEx Tamper Trigger Definitions

Defines
RTCEx Tamper Trigger Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000U)
#define | RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002U)
#define | RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE
#define | RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE

Define Documentation

#define RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002U)

Definition at line 189 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE

Definition at line 191 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE

Definition at line 190 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000U)

Definition at line 188 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTCEx Tamper EraseBackUp Definitions

Defines
RTCEx Tamper EraseBackUp Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPER_ERASE_BACKUP_ENABLE ((uint32_t)0x00000000U)
#define | RTC_TAMPER_ERASE_BACKUP_DISABLE ((uint32_t)0x00020000U)

Define Documentation

#define RTC_TAMPER_ERASE_BACKUP_DISABLE ((uint32_t)0x00020000U)

Definition at line 201 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_TAMPER_ERASE_BACKUP_ENABLE ((uint32_t)0x00000000U)

Definition at line 200 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTCEx Tamper MaskFlag Definitions

Defines
RTCEx Tamper MaskFlag Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPERMASK_FLAG_DISABLE ((uint32_t)0x00000000U)
#define | RTC_TAMPERMASK_FLAG_ENABLE ((uint32_t)0x00040000U)

Define Documentation

#define RTC_TAMPERMASK_FLAG_DISABLE ((uint32_t)0x00000000U)

Definition at line 209 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define RTC_TAMPERMASK_FLAG_ENABLE ((uint32_t)0x00040000U)

Definition at line 210 of file stm32wbxx_hal_rtc_ex.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTCEx Tamper Filter Definitions

Defines
RTCEx Tamper Filter Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000U)
#define | RTC_TAMPERFILTER_2SAMPLE RTC_TAMPCR_TAMPFLT_0
#define | RTC_TAMPERFILTER_4SAMPLE RTC_TAMPCR_TAMPFLT_1
#define | RTC_TAMPERFILTER_8SAMPLE RTC_TAMPCR_TAMPFLT

Define Documentation

#define RTC_TAMPERFILTER_2SAMPLE RTC_TAMPCR_TAMPFLT_0

Tamper is activated after 2 consecutive samples at the active level

Definition at line 221 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_TAMPERFILTER_4SAMPLE RTC_TAMPCR_TAMPFLT_1

Tamper is activated after 4 consecutive samples at the active level

Definition at line 223 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_TAMPERFILTER_8SAMPLE RTC_TAMPCR_TAMPFLT

Tamper is activated after 8 consecutive samples at the active leve.

Definition at line 225 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000U)

Tamper filter is disabled

Definition at line 219 of file stm32wbxx_hal_rtc_ex.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTCEx Tamper Sampling Frequencies Definitions

Defines
RTCEx Tamper Sampling Frequencies Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000U)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 RTC_TAMPCR_TAMPFREQ_0
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 RTC_TAMPCR_TAMPFREQ_1
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 ((uint32_t) (RTC_TAMPCR_TAMPFREQ_0 | RTC_TAMPCR_TAMPFREQ_1))
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 RTC_TAMPCR_TAMPFREQ_2
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 ((uint32_t) (RTC_TAMPCR_TAMPFREQ_0 | RTC_TAMPCR_TAMPFREQ_2))
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 ((uint32_t) (RTC_TAMPCR_TAMPFREQ_1 | RTC_TAMPCR_TAMPFREQ_2))
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256

Define Documentation

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 ((uint32_t) (RTC_TAMPCR_TAMPFREQ_0 | RTC_TAMPCR_TAMPFREQ_2))

Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024

Definition at line 245 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 RTC_TAMPCR_TAMPFREQ_0

Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384

Definition at line 237 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 RTC_TAMPCR_TAMPFREQ_2

Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048

Definition at line 243 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256
Value:
((uint32_t) (RTC_TAMPCR_TAMPFREQ_0 | RTC_TAMPCR_TAMPFREQ_1 | \
                                                 RTC_TAMPCR_TAMPFREQ_2))

Each of the tamper inputs are sampled with a frequency = RTCCLK / 256

Definition at line 249 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000U)

Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768

Definition at line 235 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 ((uint32_t) (RTC_TAMPCR_TAMPFREQ_0 | RTC_TAMPCR_TAMPFREQ_1))

Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096

Definition at line 241 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 ((uint32_t) (RTC_TAMPCR_TAMPFREQ_1 | RTC_TAMPCR_TAMPFREQ_2))

Each of the tamper inputs are sampled with a frequency = RTCCLK / 512

Definition at line 247 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 RTC_TAMPCR_TAMPFREQ_1

Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192

Definition at line 239 of file stm32wbxx_hal_rtc_ex.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTCEx Tamper Pin Precharge Duration Definitions

Defines
RTCEx Tamper Pin Precharge Duration Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000U)
#define | RTC_TAMPERPRECHARGEDURATION_2RTCCLK RTC_TAMPCR_TAMPPRCH_0
#define | RTC_TAMPERPRECHARGEDURATION_4RTCCLK RTC_TAMPCR_TAMPPRCH_1
#define | RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)(RTC_TAMPCR_TAMPPRCH_0 | RTC_TAMPCR_TAMPPRCH_1))

Define Documentation

#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000U)

Tamper pins are pre-charged before sampling during 1 RTCCLK cycle

Definition at line 260 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK RTC_TAMPCR_TAMPPRCH_0

Tamper pins are pre-charged before sampling during 2 RTCCLK cycles

Definition at line 262 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK RTC_TAMPCR_TAMPPRCH_1

Tamper pins are pre-charged before sampling during 4 RTCCLK cycles

Definition at line 264 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)(RTC_TAMPCR_TAMPPRCH_0 | RTC_TAMPCR_TAMPPRCH_1))

Tamper pins are pre-charged before sampling during 8 RTCCLK cycles

Definition at line 266 of file stm32wbxx_hal_rtc_ex.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTCEx Tamper TimeStampOnTamperDetection Definitions

Defines
RTCEx Tamper TimeStampOnTamperDetection Definitions
RTCEx Exported Constants

Defines

#define | RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_TAMPCR_TAMPTS
#define | RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000U)

Define Documentation

#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000U)

TimeStamp on Tamper Detection event is not saved

Definition at line 277 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_TAMPCR_TAMPTS

TimeStamp on Tamper Detection event saved

Definition at line 276 of file stm32wbxx_hal_rtc_ex.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTCEx Tamper Pull UP Definitions

Defines
RTCEx Tamper Pull UP Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000U)
#define | RTC_TAMPER_PULLUP_DISABLE RTC_TAMPCR_TAMPPUDIS

Define Documentation

#define RTC_TAMPER_PULLUP_DISABLE RTC_TAMPCR_TAMPPUDIS

Tamper pins pre-charge is disabled

Definition at line 287 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000U)

Tamper pins are pre-charged before sampling

Definition at line 286 of file stm32wbxx_hal_rtc_ex.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTCEx Wakeup Timer Definitions

Defines
RTCEx Wakeup Timer Definitions
RTCEx Exported Constants

Defines

#define | RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000U)
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t) (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1))
#define | RTC_WAKEUPCLOCK_CK_SPRE_16BITS RTC_CR_WUCKSEL_2
#define | RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t) (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2))

Define Documentation

#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS RTC_CR_WUCKSEL_2

Definition at line 300 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t) (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2))

Definition at line 301 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000U)

Definition at line 296 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t) (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1))

Definition at line 299 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1

Definition at line 298 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0

Definition at line 297 of file stm32wbxx_hal_rtc_ex.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTCEx Smooth calib period Definitions

Defines
RTCEx Smooth calib period Definitions
RTCEx Exported Constants

Defines

#define | RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000U)
#define | RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16
#define | RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8

Define Documentation

#define RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16

If RTCCLK = 32768 Hz, Smooth calibation period is 16s, else 2exp19 RTCCLK pulses

Definition at line 311 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000U)

If RTCCLK = 32768 Hz, Smooth calibation period is 32s, else 2exp20 RTCCLK pulses

Definition at line 309 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8

If RTCCLK = 32768 Hz, Smooth calibation period is 8s, else 2exp18 RTCCLK pulses

Definition at line 313 of file stm32wbxx_hal_rtc_ex.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTCEx Smooth calib Plus pulses Definitions

Defines
RTCEx Smooth calib Plus pulses Definitions
RTCEx Exported Constants

Defines

#define | RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP
#define | RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000U)

Define Documentation

#define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000U)

The number of RTCCLK pulses subbstited during a 32-second window = CALM[8:0]

Definition at line 326 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP

The number of RTCCLK pulses added during a X -second window = Y - CALM[8:0] with Y = 512, 256, 128 when X = 32, 16, 8

Definition at line 323 of file stm32wbxx_hal_rtc_ex.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTCEx Calib Output selection Definitions

Defines
RTCEx Calib Output selection Definitions
RTCEx Exported Constants

Defines

#define | RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000U)
#define | RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL

Define Documentation

#define RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL

Definition at line 336 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000U)

Definition at line 335 of file stm32wbxx_hal_rtc_ex.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTCEx Add 1 Second Parameter Definitions

Defines
RTCEx Add 1 Second Parameter Definitions
RTCEx Exported Constants

Defines

#define | RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000U)
#define | RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S

Define Documentation

#define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000U)

Definition at line 346 of file stm32wbxx_hal_rtc_ex.h.

#define RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S

Definition at line 347 of file stm32wbxx_hal_rtc_ex.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTCEx Interrupts Definitions

Defines
RTCEx Interrupts Definitions
RTCEx Exported Constants

Defines

#define RTC_IT_TAMP3 ((uint32_t)RTC_TAMPCR_TAMP3IE)

Define Documentation

#define RTC_IT_TAMP3 ((uint32_t)RTC_TAMPCR_TAMP3IE)

Enable Tamper 3 Interrupt

Definition at line 355 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateTamper(), and HAL_RTCEx_TamperTimeStampIRQHandler().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTCEx Flags Definitions

Defines
RTCEx Flags Definitions
RTCEx Exported Constants

Defines

#define RTC_FLAG_TAMP3F ((uint32_t)RTC_ISR_TAMP3F)

Define Documentation

#define RTC_FLAG_TAMP3F ((uint32_t)RTC_ISR_TAMP3F)

Definition at line 365 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_PollForTamper3Event(), and HAL_RTCEx_TamperTimeStampIRQHandler().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC WakeUp Timer

Defines
RTC WakeUp Timer
RTCEx Exported Macros

Defines

#define | __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
Enable the RTC WakeUp Timer peripheral.
#define | __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
Disable the RTC WakeUp Timer peripheral.
#define | __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC WakeUpTimer interrupt.
#define | __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC WakeUpTimer interrupt.
#define | __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != 0U) ? 1U : 0U)
Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
#define | __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
#define | __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)
Get the selected RTC WakeUpTimer's flag status.
#define | __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Wake Up timer's pending flags.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable interrupt on the RTC WakeUp Timer associated Exti line of core 1.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable interrupt on the RTC WakeUp Timer associated Exti line of core 1.
#define | __HAL_RTC_WAKEUPTIMER_EXTIC2_ENABLE_IT() (EXTI->C2IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable interrupt on the RTC WakeUp Timer associated Exti line of core 2.
#define | __HAL_RTC_WAKEUPTIMER_EXTIC2_DISABLE_IT() (EXTI->C2IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable interrupt on the RTC WakeUp Timer associated Exti line of core 2.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable event on the RTC WakeUp Timer associated Exti line of core 1.
#define | __HAL_RTC_WAKEUPTIMER_EXTIC2_ENABLE_EVENT() (EXTI->C2EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable event on the RTC WakeUp Timer associated Exti line of core 2.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable event on the RTC WakeUp Timer associated Exti line of core 1.
#define | __HAL_RTC_WAKEUPTIMER_EXTIC2_DISABLE_EVENT() (EXTI->C2EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable event on the RTC WakeUp Timer associated Exti line of core 2.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not of core 1.
#define | __HAL_RTC_WAKEUPTIMER_EXTIC2_GET_FLAG() (EXTI->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not of core 2.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Clear the RTC WakeUp Timer associated Exti line flag of core 1.
#define | __HAL_RTC_WAKEUPTIMER_EXTIC2_CLEAR_FLAG() (EXTI->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Clear the RTC WakeUp Timer associated Exti line flag of core 2.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.

Define Documentation

#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))

Clear the RTC Wake Up timer's pending flags.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC WakeUpTimer Flag to clear. This parameter can be:
  • RTC_FLAG_WUTF
Return values:
None

Definition at line 457 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_PollForWakeUpTimerEvent(), HAL_RTCEx_SetWakeUpTimer_IT(), and HAL_RTCEx_WakeUpTimerIRQHandler().

#define __HAL_RTC_WAKEUPTIMER_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))

Disable the RTC WakeUp Timer peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 396 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))

Disable the RTC WakeUpTimer interrupt.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be disabled. This parameter can be:
  • RTC_IT_WUT: WakeUpTimer interrupt
Return values:
None

Definition at line 416 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer().

#define __HAL_RTC_WAKEUPTIMER_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))

Enable the RTC WakeUp Timer peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 389 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))

Enable the RTC WakeUpTimer interrupt.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled. This parameter can be:
  • RTC_IT_WUT: WakeUpTimer interrupt
Return values:
None

Definition at line 406 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG ( ) (EXTI->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Clear the RTC WakeUp Timer associated Exti line flag of core 1.

Return values:
None.

Definition at line 574 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_WakeUpTimerIRQHandler().

#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT ( ) (EXTI->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable event on the RTC WakeUp Timer associated Exti line of core 1.

Return values:
None.

Definition at line 502 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE ( ) (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.

Return values:
None.

Definition at line 522 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT ( ) (EXTI->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable interrupt on the RTC WakeUp Timer associated Exti line of core 1.

Return values:
None

Definition at line 469 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE ( ) (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.

Return values:
None.

Definition at line 534 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                                   __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();  \
                                                                   __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); \
                                                                  } while(0U)

Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.

This parameter can be:

Return values:
None

Definition at line 551 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT ( ) (EXTI->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable event on the RTC WakeUp Timer associated Exti line of core 1.

Return values:
None.

Definition at line 489 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE ( ) (EXTI->FTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable falling edge trigger on the RTC WakeUp Timer associated Exti line.

Return values:
None.

Definition at line 516 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT ( ) (EXTI->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable interrupt on the RTC WakeUp Timer associated Exti line of core 1.

Return values:
None

Definition at line 463 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE ( ) (EXTI->RTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.

Return values:
None.

Definition at line 528 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer_IT().

#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                                   __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();  \
                                                                   __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); \
                                                                 } while(0U)

Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.

Return values:
None

Definition at line 541 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT ( ) (EXTI->SWIER1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.

Return values:
None.

Definition at line 588 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG ( ) (EXTI->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not of core 1.

Return values:
Line Status.

Definition at line 560 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTIC2_CLEAR_FLAG ( ) (EXTI->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Clear the RTC WakeUp Timer associated Exti line flag of core 2.

Return values:
None.

Definition at line 580 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTIC2_DISABLE_EVENT ( ) (EXTI->C2EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable event on the RTC WakeUp Timer associated Exti line of core 2.

Return values:
None.

Definition at line 508 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTIC2_DISABLE_IT ( ) (EXTI->C2IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

Disable interrupt on the RTC WakeUp Timer associated Exti line of core 2.

Return values:
None

Definition at line 482 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTIC2_ENABLE_EVENT ( ) (EXTI->C2EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable event on the RTC WakeUp Timer associated Exti line of core 2.

Return values:
None.

Definition at line 495 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTIC2_ENABLE_IT ( ) (EXTI->C2IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Enable interrupt on the RTC WakeUp Timer associated Exti line of core 2.

Return values:
None

Definition at line 476 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_EXTIC2_GET_FLAG ( ) (EXTI->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not of core 2.

Return values:
Line Status.

Definition at line 566 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)

Get the selected RTC WakeUpTimer's flag status.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC WakeUpTimer Flag is pending or not. This parameter can be:
  • RTC_FLAG_WUTF
  • RTC_FLAG_WUTWF
Return values:
None

Definition at line 447 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateWakeUpTimer(), HAL_RTCEx_PollForWakeUpTimerEvent(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), and HAL_RTCEx_WakeUpTimerIRQHandler().

#define __HAL_RTC_WAKEUPTIMER_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != 0U) ? 1U : 0U)

Check whether the specified RTC WakeUpTimer interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC WakeUpTimer interrupt to check. This parameter can be:
  • RTC_IT_WUT: WakeUpTimer interrupt
Return values:
None

Definition at line 426 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)

Check whether the specified RTC Wake Up timer interrupt has been enabled or not.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check. This parameter can be:
  • RTC_IT_WUT: WakeUpTimer interrupt
Return values:
None

Definition at line 436 of file stm32wbxx_hal_rtc_ex.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC Timestamp

Defines
RTC Timestamp
RTCEx Exported Macros

Defines

#define | __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
Enable the RTC TimeStamp peripheral.
#define | __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
Disable the RTC TimeStamp peripheral.
#define | __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC TimeStamp interrupt.
#define | __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC TimeStamp interrupt.
#define | __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != 0U) ? 1U : 0U)
Check whether the specified RTC TimeStamp interrupt has occurred or not.
#define | __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
Check whether the specified RTC Time Stamp interrupt has been enabled or not.
#define | __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)
Get the selected RTC TimeStamp's flag status.
#define | __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Time Stamp's pending flags.

Define Documentation

#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))

Clear the RTC Time Stamp's pending flags.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC TimeStamp Flag to clear. This parameter can be:
  • RTC_FLAG_TSF
  • RTC_FLAG_TSOVF
Return values:
None

Definition at line 673 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_GetTimeStamp(), HAL_RTCEx_PollForTimeStampEvent(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define __HAL_RTC_TIMESTAMP_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))

Disable the RTC TimeStamp peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 611 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_TIMESTAMP_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))

Disable the RTC TimeStamp interrupt.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC TimeStamp interrupt source to be disabled. This parameter can be:
  • RTC_IT_TS: TimeStamp interrupt
Return values:
None

Definition at line 631 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateTimeStamp().

#define __HAL_RTC_TIMESTAMP_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))

Enable the RTC TimeStamp peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 604 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTimeStamp(), and HAL_RTCEx_SetTimeStamp_IT().

#define __HAL_RTC_TIMESTAMP_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))

Enable the RTC TimeStamp interrupt.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC TimeStamp interrupt source to be enabled. This parameter can be:
  • RTC_IT_TS: TimeStamp interrupt
Return values:
None

Definition at line 621 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTimeStamp_IT().

#define __HAL_RTC_TIMESTAMP_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)

Get the selected RTC TimeStamp's flag status.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC TimeStamp Flag is pending or not. This parameter can be:
  • RTC_FLAG_TSF
  • RTC_FLAG_TSOVF
Return values:
None

Definition at line 662 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_PollForTimeStampEvent(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define __HAL_RTC_TIMESTAMP_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != 0U) ? 1U : 0U)

Check whether the specified RTC TimeStamp interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC TimeStamp interrupt to check. This parameter can be:
  • RTC_IT_TS: TimeStamp interrupt
Return values:
None

Definition at line 641 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)

Check whether the specified RTC Time Stamp interrupt has been enabled or not.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Time Stamp interrupt source to check. This parameter can be:
  • RTC_IT_TS: TimeStamp interrupt
Return values:
None

Definition at line 651 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC Tamper

Defines
RTC Tamper
RTCEx Exported Macros

Defines

#define | __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E))
Enable the RTC Tamper1 input detection.
#define | __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E))
Disable the RTC Tamper1 input detection.
#define | __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E))
Enable the RTC Tamper2 input detection.
#define | __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E))
Disable the RTC Tamper2 input detection.
#define | __HAL_RTC_TAMPER3_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E))
Enable the RTC Tamper3 input detection.
#define | __HAL_RTC_TAMPER3_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E))
Disable the RTC Tamper3 input detection.
#define | __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__))
Enable the RTC Tamper interrupt.
#define | __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__))
Disable the RTC Tamper interrupt.
#define | __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)
Check whether the specified RTC Tamper interrupt has occurred or not.
#define | __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
Check whether the specified RTC Tamper interrupt has been enabled or not.
#define | __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)
Get the selected RTC Tamper's flag status.
#define | __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Tamper's pending flags.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE))
Enable the RTC internal TimeStamp peripheral.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE))
Disable the RTC internal TimeStamp peripheral.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)
Get the selected RTC Internal Time Stamp's flag status.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Internal Time Stamp's pending flags.

Define Documentation

#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))

Clear the RTC Internal Time Stamp's pending flags.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC Internal Time Stamp Flag source to clear. This parameter can be:
  • RTC_FLAG_ITSF
Return values:
None

Definition at line 875 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_GetTimeStamp(), and HAL_RTCEx_SetInternalTimeStamp().

#define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE))

Disable the RTC internal TimeStamp peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 855 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateInternalTimeStamp().

#define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE))

Enable the RTC internal TimeStamp peripheral.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 848 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetInternalTimeStamp().

#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)

Get the selected RTC Internal Time Stamp's flag status.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC Internal Time Stamp Flag is pending or not. This parameter can be:
  • RTC_FLAG_ITSF
Return values:
None

Definition at line 865 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER1_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E))

Disable the RTC Tamper1 input detection.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 698 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER1_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E))

Enable the RTC Tamper1 input detection.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 691 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER2_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E))

Disable the RTC Tamper2 input detection.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 713 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER2_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E))

Enable the RTC Tamper2 input detection.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 706 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER3_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E))

Disable the RTC Tamper3 input detection.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 728 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER3_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E))

Enable the RTC Tamper3 input detection.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 721 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))

Clear the RTC Tamper's pending flags.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC Tamper Flag to clear. This parameter can be:
  • RTC_FLAG_TAMP1F: Tamper1 flag (*)
  • RTC_FLAG_TAMP2F: Tamper2 flag
  • RTC_FLAG_TAMP3F: Tamper3 flag (*)
(*) Value not defined in all devices.
Return values:
None

Definition at line 836 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_PollForTamper1Event(), HAL_RTCEx_PollForTamper2Event(), HAL_RTCEx_PollForTamper3Event(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define __HAL_RTC_TAMPER_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__))

Disable the RTC Tamper interrupt.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled. This parameter can be any combination of the following values:
  • RTC_IT_TAMP: All tampers interrupts
  • RTC_IT_TAMP1: Tamper1 interrupt (*)
  • RTC_IT_TAMP2: Tamper2 interrupt
  • RTC_IT_TAMP3: Tamper3 interrupt (*)
(*) Value not defined in all devices.
Return values:
None

Definition at line 764 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__))

Enable the RTC Tamper interrupt.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled. This parameter can be any combination of the following values:
  • RTC_IT_TAMP: All tampers interrupts
  • RTC_IT_TAMP1: Tamper1 interrupt (*)
  • RTC_IT_TAMP2: Tamper2 interrupt
  • RTC_IT_TAMP3: Tamper3 interrupt (*)
(*) Value not defined in all devices.
Return values:
None

Definition at line 748 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)

Get the selected RTC Tamper's flag status.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC Tamper Flag is pending or not. This parameter can be:
  • RTC_FLAG_TAMP1F: Tamper1 flag (*)
  • RTC_FLAG_TAMP2F: Tamper2 flag
  • RTC_FLAG_TAMP3F: Tamper3 flag (*)
(*) Value not defined in all devices.
Return values:
None

Definition at line 821 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_PollForTamper1Event(), HAL_RTCEx_PollForTamper2Event(), HAL_RTCEx_PollForTamper3Event(), and HAL_RTCEx_TamperTimeStampIRQHandler().

#define __HAL_RTC_TAMPER_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3U)) != 0U) ? 1U : 0U) : \
                                                               ((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5U)) != 0U) ? 1U : 0U) : \
                                                               ((__INTERRUPT__) == RTC_IT_TAMP3) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7U)) != 0U) ? 1U : 0U))

Check whether the specified RTC Tamper interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Tamper interrupt to check. This parameter can be:
  • RTC_IT_TAMP1: Tamper1 interrupt (*)
  • RTC_IT_TAMP2: Tamper2 interrupt
  • RTC_IT_TAMP3: Tamper3 interrupt (*)
(*) Value not defined in all devices.
Return values:
None

Definition at line 782 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)

Check whether the specified RTC Tamper interrupt has been enabled or not.

Parameters:
__HANDLE__ specifies the RTC handle.
__INTERRUPT__ specifies the RTC Tamper interrupt source to check. This parameter can be:
  • RTC_IT_TAMP: All tampers interrupts
  • RTC_IT_TAMP1: Tamper1 interrupt (*)
  • RTC_IT_TAMP2: Tamper2 interrupt
  • RTC_IT_TAMP3: Tamper3 interrupt (*)
(*) Value not defined in all devices.
Return values:
None

Definition at line 805 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: EXTI RTC Tamper Timestamp EXTI

Defines
EXTI RTC Tamper Timestamp EXTI
RTCEx Exported Macros

Defines

#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable interrupt on the RTC Tamper and Timestamp associated Exti line of core 1.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_ENABLE_IT() (EXTI->C2IMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable interrupt on the RTC Tamper and Timestamp associated Exti line of core 2.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable interrupt on the RTC Tamper and Timestamp associated Exti line of core 1.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_DISABLE_IT() (EXTI->C2IMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable interrupt on the RTC Tamper and Timestamp associated Exti line of core 2.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable event on the RTC Tamper and Timestamp associated Exti line of core 1.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_ENABLE_EVENT() (EXTI->C2EMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable event on the RTC Tamper and Timestamp associated Exti line of core 2.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable event on the RTC Tamper and Timestamp associated Exti line of core 1.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_DISABLE_EVENT() (EXTI->C2EMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable event on the RTC Tamper and Timestamp associated Exti line of core 2.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR1 & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not of core 1.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_GET_FLAG() (EXTI->PR2 & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not of core 2.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI->PR1 = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Clear the RTC Tamper and Timestamp associated Exti line flag of core 1.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_CLEAR_FLAG() (EXTI->PR1 = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Clear the RTC Tamper and Timestamp associated Exti line flag of core 2.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line.

Define Documentation

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG ( ) (EXTI->PR1 = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Clear the RTC Tamper and Timestamp associated Exti line flag of core 1.

Return values:
None.

Definition at line 1000 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperTimeStampIRQHandler().

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT ( ) (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))

Disable event on the RTC Tamper and Timestamp associated Exti line of core 1.

Return values:
None.

Definition at line 931 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE ( ) (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))

Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.

Return values:
None.

Definition at line 950 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT ( ) (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))

Disable interrupt on the RTC Tamper and Timestamp associated Exti line of core 1.

Return values:
None

Definition at line 907 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE ( ) (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))

Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.

Return values:
None.

Definition at line 962 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();  \
                                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE(); \
                                                                       } while(0U)

Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.

This parameter can be:

Return values:
None.

Definition at line 979 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT ( ) (EXTI->EMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Enable event on the RTC Tamper and Timestamp associated Exti line of core 1.

Return values:
None.

Definition at line 919 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE ( ) (EXTI->FTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.

Return values:
None.

Definition at line 944 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT ( ) (EXTI->IMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Enable interrupt on the RTC Tamper and Timestamp associated Exti line of core 1.

Return values:
None

Definition at line 895 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper_IT(), and HAL_RTCEx_SetTimeStamp_IT().

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE ( ) (EXTI->RTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.

Return values:
None.

Definition at line 956 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper_IT(), and HAL_RTCEx_SetTimeStamp_IT().

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do { \
                                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();  \
                                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); \
                                                                      } while(0U)

Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.

Return values:
None.

Definition at line 969 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT ( ) (EXTI->SWIER1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line.

Return values:
None.

Definition at line 1012 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG ( ) (EXTI->PR1 & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not of core 1.

Return values:
Line Status.

Definition at line 988 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_CLEAR_FLAG ( ) (EXTI->PR1 = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Clear the RTC Tamper and Timestamp associated Exti line flag of core 2.

Return values:
None.

Definition at line 1006 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_DISABLE_EVENT ( ) (EXTI->C2EMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))

Disable event on the RTC Tamper and Timestamp associated Exti line of core 2.

Return values:
None.

Definition at line 937 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_DISABLE_IT ( ) (EXTI->C2IMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))

Disable interrupt on the RTC Tamper and Timestamp associated Exti line of core 2.

Return values:
None

Definition at line 913 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_ENABLE_EVENT ( ) (EXTI->C2EMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Enable event on the RTC Tamper and Timestamp associated Exti line of core 2.

Return values:
None.

Definition at line 925 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_ENABLE_IT ( ) (EXTI->C2IMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Enable interrupt on the RTC Tamper and Timestamp associated Exti line of core 2.

Return values:
None

Definition at line 901 of file stm32wbxx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_GET_FLAG ( ) (EXTI->PR2 & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not of core 2.

Return values:
Line Status.

Definition at line 994 of file stm32wbxx_hal_rtc_ex.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC Calibration

Defines
RTC Calibration
RTCEx Exported Macros

Defines

#define | __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
Enable the RTC calibration output.
#define | __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
Disable the calibration output.
#define | __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
Enable the clock reference detection.
#define | __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
Disable the clock reference detection.
#define | __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U)
Get the selected RTC shift operation's flag status.

Define Documentation

#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))

Disable the calibration output.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 1037 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateCalibrationOutPut().

#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))

Enable the RTC calibration output.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 1030 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetCalibrationOutPut().

#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))

Disable the clock reference detection.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 1052 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateRefClock().

#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))

Enable the clock reference detection.

Parameters:
__HANDLE__ specifies the RTC handle.
Return values:
None

Definition at line 1045 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetRefClock().

#define __HAL_RTC_SHIFT_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U)

Get the selected RTC shift operation's flag status.

Parameters:
__HANDLE__ specifies the RTC handle.
__FLAG__ specifies the RTC shift operation Flag is pending or not. This parameter can be:
  • RTC_FLAG_SHPF
Return values:
None

Definition at line 1063 of file stm32wbxx_hal_rtc_ex.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Extended RTC TimeStamp and Tamper functions

Functions
Extended RTC TimeStamp and Tamper functions
RTCEx Exported Functions

RTC TimeStamp and Tamper functions. More...

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp_IT (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp with Interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivate TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Set Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivate Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_GetTimeStamp (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
Get the RTC TimeStamp value.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper_IT (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper with interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTamper (RTC_HandleTypeDef *hrtc, uint32_t Tamper)
Deactivate Tamper.
void | HAL_RTCEx_TamperTimeStampIRQHandler (RTC_HandleTypeDef *hrtc)
Handle TimeStamp interrupt request.
__weak void | HAL_RTCEx_TimeStampEventCallback (RTC_HandleTypeDef *hrtc)
TimeStamp callback.
__weak void | HAL_RTCEx_Tamper1EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 1 callback.
__weak void | HAL_RTCEx_Tamper2EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 2 callback.
__weak void | HAL_RTCEx_Tamper3EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 3 callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForTimeStampEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle TimeStamp polling request.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper1Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper 1 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper2Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper 2 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper3Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper 3 Polling.

Detailed Description

RTC TimeStamp and Tamper functions.

 ===============================================================================
                 ##### RTC TimeStamp and Tamper functions #####
 ===============================================================================

 [..] This section provides functions allowing to configure TimeStamp feature

Function Documentation

HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp ( RTC_HandleTypeDef * hrtc )

Deactivate Internal TimeStamp.

Parameters:
hrtc pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 386 of file stm32wbxx_hal_rtc_ex.c.

References __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Tamper
 | ) |  |

Deactivate Tamper.

Parameters:
hrtc | RTC handle
Tamper | Selected tamper pin. This parameter can be any combination of RTC_TAMPER_1, RTC_TAMPER_2 and RTC_TAMPER_3.
Return values:
HAL status

Definition at line 667 of file stm32wbxx_hal_rtc_ex.c.

References assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, __RTC_HandleTypeDef::Instance, IS_RTC_TAMPER, RTC_IT_TAMP, RTC_IT_TAMP1, RTC_IT_TAMP2, RTC_IT_TAMP3, RTC_TAMPER_1, RTC_TAMPER_2, RTC_TAMPER_3, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp ( RTC_HandleTypeDef * hrtc )

Deactivate TimeStamp.

Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 312 of file stm32wbxx_hal_rtc_ex.c.

References __HAL_RTC_TIMESTAMP_DISABLE_IT, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, __RTC_HandleTypeDef::Instance, RTC_IT_TS, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TimeTypeDef * | sTimeStamp,
 |  | RTC_DateTypeDef * | sTimeStampDate,
 |  | uint32_t | Format
 | ) |  |

Get the RTC TimeStamp value.

Parameters:
hrtc | RTC handle
sTimeStamp | Pointer to Time structure
sTimeStampDate | Pointer to Date structure
Format specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 422 of file stm32wbxx_hal_rtc_ex.c.

References __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG, __HAL_RTC_TIMESTAMP_CLEAR_FLAG, assert_param, RTC_DateTypeDef::Date, RTC_TimeTypeDef::Hours, __RTC_HandleTypeDef::Instance, IS_RTC_FORMAT, RTC_TimeTypeDef::Minutes, RTC_DateTypeDef::Month, RTC_Bcd2ToByte(), RTC_DR_RESERVED_MASK, RTC_FLAG_ITSF, RTC_FLAG_TSF, RTC_FORMAT_BIN, RTC_TR_RESERVED_MASK, RTC_TimeTypeDef::Seconds, RTC_TimeTypeDef::SubSeconds, RTC_TimeTypeDef::TimeFormat, RTC_DateTypeDef::WeekDay, and RTC_DateTypeDef::Year.

HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle Tamper 1 Polling.

Parameters:
hrtc | RTC handle
Timeout | Timeout duration
Return values:
HAL status

Definition at line 909 of file stm32wbxx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_CLEAR_FLAG, __HAL_RTC_TAMPER_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_TAMP1F, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle Tamper 2 Polling.

Parameters:
hrtc | RTC handle
Timeout | Timeout duration
Return values:
HAL status

Definition at line 942 of file stm32wbxx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_CLEAR_FLAG, __HAL_RTC_TAMPER_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_TAMP2F, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle Tamper 3 Polling.

Parameters:
hrtc | RTC handle
Timeout | Timeout duration
Return values:
HAL status

Definition at line 975 of file stm32wbxx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_CLEAR_FLAG, __HAL_RTC_TAMPER_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_TAMP3F, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle TimeStamp polling request.

Parameters:
hrtc | RTC handle
Timeout | Timeout duration
Return values:
HAL status

Definition at line 869 of file stm32wbxx_hal_rtc_ex.c.

References __HAL_RTC_TIMESTAMP_CLEAR_FLAG, __HAL_RTC_TIMESTAMP_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_TSF, RTC_FLAG_TSOVF, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp ( RTC_HandleTypeDef * hrtc )

Set Internal TimeStamp.

Note:
This API must be called before enabling the internal TimeStamp feature.
Parameters:
hrtc pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 352 of file stm32wbxx_hal_rtc_ex.c.

References __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG, __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_FLAG_ITSF, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetTamper | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TamperTypeDef * | sTamper
 | ) |  |

Set Tamper.

Note:
By calling this API we disable the tamper interrupt for all tampers.
Parameters:
hrtc | RTC handle
sTamper | Pointer to Tamper Structure.
Return values:
HAL status

Definition at line 477 of file stm32wbxx_hal_rtc_ex.c.

References assert_param, RTC_TamperTypeDef::Filter, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, __RTC_HandleTypeDef::Instance, IS_RTC_TAMPER, IS_RTC_TAMPER_ERASE_MODE, IS_RTC_TAMPER_FILTER, IS_RTC_TAMPER_MASKFLAG_STATE, IS_RTC_TAMPER_PRECHARGE_DURATION, IS_RTC_TAMPER_PULLUP_STATE, IS_RTC_TAMPER_SAMPLING_FREQ, IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION, IS_RTC_TAMPER_TRIGGER, RTC_TamperTypeDef::MaskFlag, RTC_TamperTypeDef::NoErase, RTC_TamperTypeDef::PrechargeDuration, RTC_TAMPCR_MASK, RTC_TAMPER_1, RTC_TAMPER_2, RTC_TAMPER_3, RTC_TAMPER_ERASE_BACKUP_ENABLE, RTC_TAMPERMASK_FLAG_DISABLE, RTC_TAMPERTRIGGER_RISINGEDGE, RTC_TamperTypeDef::SamplingFrequency, __RTC_HandleTypeDef::State, RTC_TamperTypeDef::Tamper, RTC_TamperTypeDef::TamperPullUp, RTC_TamperTypeDef::TimeStampOnTamperDetection, and RTC_TamperTypeDef::Trigger.

HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TamperTypeDef * | sTamper
 | ) |  |

Set Tamper with interrupt.

Note:
By calling this API we force the tamper interrupt for all tampers.
Parameters:
hrtc | RTC handle
sTamper | Pointer to RTC Tamper.
Return values:
HAL status

Definition at line 569 of file stm32wbxx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT, __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE, assert_param, RTC_TamperTypeDef::Filter, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, __RTC_HandleTypeDef::Instance, RTC_TamperTypeDef::Interrupt, IS_RTC_TAMPER, IS_RTC_TAMPER_ERASE_MODE, IS_RTC_TAMPER_FILTER, IS_RTC_TAMPER_INTERRUPT, IS_RTC_TAMPER_MASKFLAG_STATE, IS_RTC_TAMPER_PRECHARGE_DURATION, IS_RTC_TAMPER_PULLUP_STATE, IS_RTC_TAMPER_SAMPLING_FREQ, IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION, IS_RTC_TAMPER_TRIGGER, RTC_TamperTypeDef::MaskFlag, RTC_TamperTypeDef::NoErase, RTC_TamperTypeDef::PrechargeDuration, RTC_TAMPCR_MASK, RTC_TAMPER_1, RTC_TAMPER_2, RTC_TAMPER_3, RTC_TAMPER_ERASE_BACKUP_ENABLE, RTC_TAMPERMASK_FLAG_DISABLE, RTC_TAMPERTRIGGER_RISINGEDGE, RTC_TamperTypeDef::SamplingFrequency, __RTC_HandleTypeDef::State, RTC_TamperTypeDef::Tamper, RTC_TamperTypeDef::TamperPullUp, RTC_TamperTypeDef::TimeStampOnTamperDetection, and RTC_TamperTypeDef::Trigger.

HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | TimeStampEdge,
 |  | uint32_t | RTC_TimeStampPin
 | ) |  |

Set TimeStamp.

Note:
This API must be called before enabling the TimeStamp feature.
Parameters:
hrtc RTC handle
TimeStampEdge Specifies the pin edge on which the TimeStamp is activated. This parameter can be one of the following values:
  • RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the rising edge of the related pin.
  • RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the falling edge of the related pin.
RTC_TimeStampPin specifies the RTC TimeStamp Pin. This parameter can be one of the following values:
  • RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. The RTC TimeStamp Pin is per default PC13, but for reasons of compatibility, this parameter is required.
Return values:
HAL status

Definition at line 194 of file stm32wbxx_hal_rtc_ex.c.

References __HAL_RTC_TIMESTAMP_CLEAR_FLAG, __HAL_RTC_TIMESTAMP_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, __RTC_HandleTypeDef::Instance, IS_RTC_TIMESTAMP_PIN, IS_TIMESTAMP_EDGE, RTC_FLAG_TSF, RTC_FLAG_TSOVF, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | TimeStampEdge,
 |  | uint32_t | RTC_TimeStampPin
 | ) |  |

Set TimeStamp with Interrupt.

Parameters:
hrtc RTC handle
Note:
This API must be called before enabling the TimeStamp feature.
Parameters:
TimeStampEdge Specifies the pin edge on which the TimeStamp is activated. This parameter can be one of the following values:
  • RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the rising edge of the related pin.
  • RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the falling edge of the related pin.
RTC_TimeStampPin Specifies the RTC TimeStamp Pin. This parameter can be one of the following values:
  • RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. The RTC TimeStamp Pin is per default PC13, but for reasons of compatibility, this parameter is required.
Return values:
HAL status

Definition at line 256 of file stm32wbxx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT, __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE, __HAL_RTC_TIMESTAMP_CLEAR_FLAG, __HAL_RTC_TIMESTAMP_ENABLE, __HAL_RTC_TIMESTAMP_ENABLE_IT, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, __RTC_HandleTypeDef::Instance, IS_RTC_TIMESTAMP_PIN, IS_TIMESTAMP_EDGE, RTC_FLAG_TSF, RTC_FLAG_TSOVF, RTC_IT_TS, and __RTC_HandleTypeDef::State.

void HAL_RTCEx_Tamper1EventCallback ( RTC_HandleTypeDef * hrtc )

Tamper 1 callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 820 of file stm32wbxx_hal_rtc_ex.c.

Referenced by HAL_RTC_Init(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperTimeStampIRQHandler().

void HAL_RTCEx_Tamper2EventCallback ( RTC_HandleTypeDef * hrtc )

Tamper 2 callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 836 of file stm32wbxx_hal_rtc_ex.c.

Referenced by HAL_RTC_Init(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperTimeStampIRQHandler().

void HAL_RTCEx_Tamper3EventCallback ( RTC_HandleTypeDef * hrtc )

Tamper 3 callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 852 of file stm32wbxx_hal_rtc_ex.c.

Referenced by HAL_RTC_Init(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperTimeStampIRQHandler().

void HAL_RTCEx_TamperTimeStampIRQHandler ( RTC_HandleTypeDef * hrtc )

Handle TimeStamp interrupt request.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 713 of file stm32wbxx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_CLEAR_FLAG, __HAL_RTC_TAMPER_GET_FLAG, __HAL_RTC_TAMPER_GET_IT_SOURCE, __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG, __HAL_RTC_TIMESTAMP_CLEAR_FLAG, __HAL_RTC_TIMESTAMP_GET_FLAG, __HAL_RTC_TIMESTAMP_GET_IT_SOURCE, HAL_RTC_STATE_READY, HAL_RTCEx_Tamper1EventCallback(), HAL_RTCEx_Tamper2EventCallback(), HAL_RTCEx_Tamper3EventCallback(), HAL_RTCEx_TimeStampEventCallback(), RTC_FLAG_TAMP1F, RTC_FLAG_TAMP2F, RTC_FLAG_TAMP3F, RTC_FLAG_TSF, RTC_IT_TAMP, RTC_IT_TAMP1, RTC_IT_TAMP2, RTC_IT_TAMP3, RTC_IT_TS, __RTC_HandleTypeDef::State, __RTC_HandleTypeDef::Tamper1EventCallback, __RTC_HandleTypeDef::Tamper2EventCallback, __RTC_HandleTypeDef::Tamper3EventCallback, and __RTC_HandleTypeDef::TimeStampEventCallback.

void HAL_RTCEx_TimeStampEventCallback ( RTC_HandleTypeDef * hrtc )

TimeStamp callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 804 of file stm32wbxx_hal_rtc_ex.c.

Referenced by HAL_RTC_Init(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_TamperTimeStampIRQHandler().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Extended RTC Wake-up functions

Functions
Extended RTC Wake-up functions
RTCEx Exported Functions

RTC Wake-up functions. More...

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer_IT (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer with interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateWakeUpTimer (RTC_HandleTypeDef *hrtc)
Deactivate wake up timer counter.
uint32_t | HAL_RTCEx_GetWakeUpTimer (RTC_HandleTypeDef *hrtc)
Get wake up timer counter.
void | HAL_RTCEx_WakeUpTimerIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Wake Up Timer interrupt request.
__weak void | HAL_RTCEx_WakeUpTimerEventCallback (RTC_HandleTypeDef *hrtc)
Wake Up Timer callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForWakeUpTimerEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Wake Up Timer Polling.

Detailed Description

RTC Wake-up functions.

 ===============================================================================
                        ##### RTC Wake-up functions #####
 ===============================================================================

 [..] This section provides functions allowing to configure Wake-up feature

Function Documentation

HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer ( RTC_HandleTypeDef * hrtc )

Deactivate wake up timer counter.

Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 1214 of file stm32wbxx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_DISABLE, __HAL_RTC_WAKEUPTIMER_DISABLE_IT, __HAL_RTC_WAKEUPTIMER_GET_FLAG, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_WUTWF, RTC_IT_WUT, RTC_TIMEOUT_VALUE, and __RTC_HandleTypeDef::State.

uint32_t HAL_RTCEx_GetWakeUpTimer ( RTC_HandleTypeDef * hrtc )

Get wake up timer counter.

Parameters:
hrtc RTC handle
Return values:
Counter value

Definition at line 1266 of file stm32wbxx_hal_rtc_ex.c.

References __RTC_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle Wake Up Timer Polling.

Parameters:
hrtc | RTC handle
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1322 of file stm32wbxx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG, __HAL_RTC_WAKEUPTIMER_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_WUTF, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | WakeUpCounter,
 |  | uint32_t | WakeUpClock
 | ) |  |

Set wake up timer.

Parameters:
hrtc | RTC handle
WakeUpCounter | Wake up counter
WakeUpClock | Wake up clock
Return values:
HAL status

Definition at line 1027 of file stm32wbxx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_DISABLE, __HAL_RTC_WAKEUPTIMER_ENABLE, __HAL_RTC_WAKEUPTIMER_GET_FLAG, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, __RTC_HandleTypeDef::Instance, IS_RTC_WAKEUP_CLOCK, IS_RTC_WAKEUP_COUNTER, RTC_FLAG_WUTWF, RTC_TIMEOUT_VALUE, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | WakeUpCounter,
 |  | uint32_t | WakeUpClock
 | ) |  |

Set wake up timer with interrupt.

Parameters:
hrtc | RTC handle
WakeUpCounter | Wake up counter
WakeUpClock | Wake up clock
Return values:
HAL status

Definition at line 1116 of file stm32wbxx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG, __HAL_RTC_WAKEUPTIMER_DISABLE, __HAL_RTC_WAKEUPTIMER_ENABLE, __HAL_RTC_WAKEUPTIMER_ENABLE_IT, __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT, __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE, __HAL_RTC_WAKEUPTIMER_GET_FLAG, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, __RTC_HandleTypeDef::Instance, IS_RTC_WAKEUP_CLOCK, IS_RTC_WAKEUP_COUNTER, RTC_FLAG_WUTF, RTC_FLAG_WUTWF, RTC_IT_WUT, RTC_TIMEOUT_VALUE, and __RTC_HandleTypeDef::State.

void HAL_RTCEx_WakeUpTimerEventCallback ( RTC_HandleTypeDef * hrtc )

Wake Up Timer callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1305 of file stm32wbxx_hal_rtc_ex.c.

Referenced by HAL_RTC_Init(), HAL_RTC_UnRegisterCallback(), and HAL_RTCEx_WakeUpTimerIRQHandler().

void HAL_RTCEx_WakeUpTimerIRQHandler ( RTC_HandleTypeDef * hrtc )

Handle Wake Up Timer interrupt request.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1277 of file stm32wbxx_hal_rtc_ex.c.

References __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG, __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG, __HAL_RTC_WAKEUPTIMER_GET_FLAG, HAL_RTC_STATE_READY, HAL_RTCEx_WakeUpTimerEventCallback(), RTC_FLAG_WUTF, __RTC_HandleTypeDef::State, and __RTC_HandleTypeDef::WakeUpTimerEventCallback.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Extended Peripheral Control functions

Functions
Extended Peripheral Control functions
RTCEx Exported Functions

Extended Peripheral Control functions. More...

Functions

void | HAL_RTCEx_BKUPWrite (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
Write a data in a specified RTC Backup data register.
uint32_t | HAL_RTCEx_BKUPRead (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
Reads data from the specified RTC Backup data Register.
HAL_StatusTypeDef | HAL_RTCEx_SetSmoothCalib (RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
Set the Smooth calibration parameters.
HAL_StatusTypeDef | HAL_RTCEx_SetSynchroShift (RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
Configure the Synchronization Shift Control Settings.
HAL_StatusTypeDef | HAL_RTCEx_SetCalibrationOutPut (RTC_HandleTypeDef *hrtc, uint32_t CalibOutput)
Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_DeactivateCalibrationOutPut (RTC_HandleTypeDef *hrtc)
Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_SetRefClock (RTC_HandleTypeDef *hrtc)
Enable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateRefClock (RTC_HandleTypeDef *hrtc)
Disable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_EnableBypassShadow (RTC_HandleTypeDef *hrtc)
Enable the Bypass Shadow feature.
HAL_StatusTypeDef | HAL_RTCEx_DisableBypassShadow (RTC_HandleTypeDef *hrtc)
Disable the Bypass Shadow feature.

Detailed Description

Extended Peripheral Control functions.

 ===============================================================================
              ##### Extended Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Write a data in a specified RTC Backup data register
      (+) Read a data in a specified RTC Backup data register
      (+) Set the Coarse calibration parameters.
      (+) Deactivate the Coarse calibration parameters
      (+) Set the Smooth calibration parameters.
      (+) Configure the Synchronization Shift Control Settings.
      (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
      (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
      (+) Enable the RTC reference clock detection.
      (+) Disable the RTC reference clock detection.
      (+) Enable the Bypass Shadow feature.
      (+) Disable the Bypass Shadow feature.

Function Documentation

uint32_t HAL_RTCEx_BKUPRead | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | BackupRegister
 | ) |  |

Reads data from the specified RTC Backup data Register.

Parameters:
hrtc | RTC handle
BackupRegister | RTC Backup data Register number. This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to specify the register.
Return values:
Read value

Definition at line 1410 of file stm32wbxx_hal_rtc_ex.c.

References assert_param, __RTC_HandleTypeDef::Instance, and IS_RTC_BKP.

void HAL_RTCEx_BKUPWrite | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | BackupRegister,
 |  | uint32_t | Data
 | ) |  |

Write a data in a specified RTC Backup data register.

Parameters:
hrtc | RTC handle
BackupRegister | RTC Backup data Register number. This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to specify the register.
Data | Data to be written in the specified RTC Backup data register.
Return values:
None

Definition at line 1388 of file stm32wbxx_hal_rtc_ex.c.

References assert_param, __RTC_HandleTypeDef::Instance, and IS_RTC_BKP.

HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut ( RTC_HandleTypeDef * hrtc )

Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).

Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 1642 of file stm32wbxx_hal_rtc_ex.c.

References __HAL_RTC_CALIBRATION_OUTPUT_DISABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock ( RTC_HandleTypeDef * hrtc )

Disable the RTC reference clock detection.

Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 1720 of file stm32wbxx_hal_rtc_ex.c.

References __HAL_RTC_CLOCKREF_DETECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, __RTC_HandleTypeDef::Instance, RTC_EnterInitMode(), and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow ( RTC_HandleTypeDef * hrtc )

Disable the Bypass Shadow feature.

Parameters:
hrtc RTC handle
Note:
When the Bypass Shadow is enabled the calendar value are taken directly from the Calendar counter.
Return values:
HAL status

Definition at line 1803 of file stm32wbxx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, __RTC_HandleTypeDef::Instance, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow ( RTC_HandleTypeDef * hrtc )

Enable the Bypass Shadow feature.

Parameters:
hrtc RTC handle
Note:
When the Bypass Shadow is enabled the calendar value are taken directly from the Calendar counter.
Return values:
HAL status

Definition at line 1771 of file stm32wbxx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, __RTC_HandleTypeDef::Instance, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | CalibOutput
 | ) |  |

Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).

Parameters:
hrtc RTC handle
CalibOutput : Select the Calibration output Selection . This parameter can be one of the following values:
  • RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
  • RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
Return values:
HAL status

Definition at line 1604 of file stm32wbxx_hal_rtc_ex.c.

References __HAL_RTC_CALIBRATION_OUTPUT_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, __RTC_HandleTypeDef::Instance, IS_RTC_CALIB_OUTPUT, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetRefClock ( RTC_HandleTypeDef * hrtc )

Enable the RTC reference clock detection.

Parameters:
hrtc RTC handle
Return values:
HAL status

Definition at line 1671 of file stm32wbxx_hal_rtc_ex.c.

References __HAL_RTC_CLOCKREF_DETECTION_ENABLE, __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, __RTC_HandleTypeDef::Instance, RTC_EnterInitMode(), and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | SmoothCalibPeriod,
 |  | uint32_t | SmoothCalibPlusPulses,
 |  | uint32_t | SmoothCalibMinusPulsesValue
 | ) |  |

Set the Smooth calibration parameters.

Parameters:
hrtc | RTC handle
SmoothCalibPeriod Select the Smooth Calibration Period. This parameter can be can be one of the following values :
  • RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
  • RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
  • RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
SmoothCalibPlusPulses Select to Set or reset the CALP bit. This parameter can be one of the following values:
  • RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses.
  • RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
SmoothCalibMinusPulsesValue | Select the value of CALM[8:0] bits. This parameter can be one any value from 0 to 0x000001FF.
Note:
To deactivate the smooth calibration, the field SmoothCalibPlusPulses must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field SmoothCalibMinusPulsesValue mut be equal to 0.
Return values:
HAL status

Definition at line 1443 of file stm32wbxx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, __RTC_HandleTypeDef::Instance, IS_RTC_SMOOTH_CALIB_MINUS, IS_RTC_SMOOTH_CALIB_PERIOD, IS_RTC_SMOOTH_CALIB_PLUS, RTC_TIMEOUT_VALUE, and __RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | ShiftAdd1S,
 |  | uint32_t | ShiftSubFS
 | ) |  |

Configure the Synchronization Shift Control Settings.

Note:
When REFCKON is set, firmware must not write to Shift control register.
Parameters:
hrtc | RTC handle
ShiftAdd1S Select to add or not 1 second to the time calendar. This parameter can be one of the following values :
  • RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
  • RTC_SHIFTADD1S_RESET: No effect.
ShiftSubFS | Select the number of Second Fractions to substitute. This parameter can be one any value from 0 to 0x7FFF.
Return values:
HAL status

Definition at line 1511 of file stm32wbxx_hal_rtc_ex.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, __HAL_RTC_WRITEPROTECTION_ENABLE, assert_param, HAL_GetTick(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, HAL_RTC_WaitForSynchro(), __RTC_HandleTypeDef::Instance, IS_RTC_SHIFT_ADD1S, IS_RTC_SHIFT_SUBFS, RTC_TIMEOUT_VALUE, and __RTC_HandleTypeDef::State.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Extended features functions

Functions
Extended features functions
RTCEx Exported Functions

Extended features functions. More...

Functions

__weak void | HAL_RTCEx_AlarmBEventCallback (RTC_HandleTypeDef *hrtc)
Alarm B callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForAlarmBEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Alarm B Polling request.

Detailed Description

Extended features functions.

 ===============================================================================
                 ##### Extended features functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) RTC Alram B callback
      (+) RTC Poll for Alarm B request

Function Documentation

void HAL_RTCEx_AlarmBEventCallback ( RTC_HandleTypeDef * hrtc )

Alarm B callback.

Parameters:
hrtc RTC handle
Return values:
None

Definition at line 1852 of file stm32wbxx_hal_rtc_ex.c.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_Init(), and HAL_RTC_UnRegisterCallback().

HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

Handle Alarm B Polling request.

Parameters:
hrtc | RTC handle
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1868 of file stm32wbxx_hal_rtc_ex.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_ALRBF, and __RTC_HandleTypeDef::State.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTCEx Smooth calib Minus pulses Definitions

Defines
RTCEx Smooth calib Minus pulses Definitions
Private macros to check input parameters

Defines

#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= RTC_CALR_CALM)

Define Documentation

#define IS_RTC_SMOOTH_CALIB_MINUS ( VALUE ) ((VALUE) <= RTC_CALR_CALM)

Definition at line 1290 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSmoothCalib().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTCEx Substract Fraction Of Second Value

Defines
RTCEx Substract Fraction Of Second Value
Private macros to check input parameters

Defines

#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= RTC_SHIFTR_SUBFS)

Define Documentation

#define IS_RTC_SHIFT_SUBFS ( FS ) ((FS) <= RTC_SHIFTR_SUBFS)

Definition at line 1304 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSynchroShift().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Private macros to check input parameters

Modules | Defines
Private macros to check input parameters
RTCEx Private Macros

Modules

RTCEx Smooth calib Minus pulses Definitions
RTCEx Substract Fraction Of Second Value

Defines

#define | IS_RTC_OUTPUT(OUTPUT)
#define | IS_RTC_BKP(BKP) ((BKP) < (uint32_t) RTC_BKP_NUMBER)
#define | IS_TIMESTAMP_EDGE(EDGE)
#define | IS_RTC_TAMPER(TAMPER) ((((TAMPER) & ((uint32_t)(0xFFFFFFFFU ^ RTC_TAMPCR_TAMPXE))) == 0x00U) && ((TAMPER) != 0U))
#define | IS_RTC_TAMPER_INTERRUPT(INTERRUPT) ((((INTERRUPT) & (uint32_t)(0xFFFFFFFFU ^ RTC_TAMPCR_TAMPXIE)) == 0x00U) && ((INTERRUPT) != 0U))
#define | IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
#define | IS_RTC_TAMPER_TRIGGER(TRIGGER)
#define | IS_RTC_TAMPER_ERASE_MODE(MODE)
#define | IS_RTC_TAMPER_MASKFLAG_STATE(STATE)
#define | IS_RTC_TAMPER_FILTER(FILTER)
#define | IS_RTC_TAMPER_SAMPLING_FREQ(FREQ)
#define | IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION)
#define | IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION)
#define | IS_RTC_TAMPER_PULLUP_STATE(STATE)
#define | IS_RTC_WAKEUP_CLOCK(CLOCK)
#define | IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= RTC_WUTR_WUT)
#define | IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD)
#define | IS_RTC_SMOOTH_CALIB_PLUS(PLUS)
#define | IS_RTC_SHIFT_ADD1S(SEL)
#define | IS_RTC_CALIB_OUTPUT(OUTPUT)

Define Documentation

#define IS_RTC_BKP ( BKP ) ((BKP) < (uint32_t) RTC_BKP_NUMBER)

Definition at line 1223 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_BKUPRead(), and HAL_RTCEx_BKUPWrite().

#define IS_RTC_CALIB_OUTPUT ( OUTPUT )
Value:
(((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
                                      ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))

Definition at line 1308 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetCalibrationOutPut().

#define IS_RTC_OUTPUT ( OUTPUT )
Value:
(((OUTPUT) == RTC_OUTPUT_DISABLE) || \
                               ((OUTPUT) == RTC_OUTPUT_ALARMA)  || \
                               ((OUTPUT) == RTC_OUTPUT_ALARMB)  || \
                               ((OUTPUT) == RTC_OUTPUT_WAKEUP))

Definition at line 1218 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_SHIFT_ADD1S ( SEL )
Value:
(((SEL) == RTC_SHIFTADD1S_RESET) || \
                                 ((SEL) == RTC_SHIFTADD1S_SET))

Definition at line 1296 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSynchroShift().

#define IS_RTC_SMOOTH_CALIB_PERIOD ( PERIOD )
Value:
(((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
                                            ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
                                            ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))

Definition at line 1279 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSmoothCalib().

#define IS_RTC_SMOOTH_CALIB_PLUS ( PLUS )
Value:
(((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
                                        ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))

Definition at line 1283 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSmoothCalib().

#define IS_RTC_TAMPER ( TAMPER ) ((((TAMPER) & ((uint32_t)(0xFFFFFFFFU ^ RTC_TAMPCR_TAMPXE))) == 0x00U) && ((TAMPER) != 0U))

Definition at line 1228 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_ERASE_MODE ( MODE )
Value:
(((MODE) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \
                                                    ((MODE) == RTC_TAMPER_ERASE_BACKUP_DISABLE))

Definition at line 1239 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_FILTER ( FILTER )
Value:
(((FILTER) == RTC_TAMPERFILTER_DISABLE) || \
                                       ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \
                                       ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \
                                       ((FILTER) == RTC_TAMPERFILTER_8SAMPLE))

Definition at line 1245 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_INTERRUPT ( INTERRUPT ) ((((INTERRUPT) & (uint32_t)(0xFFFFFFFFU ^ RTC_TAMPCR_TAMPXIE)) == 0x00U) && ((INTERRUPT) != 0U))

Definition at line 1230 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_MASKFLAG_STATE ( STATE )
Value:
(((STATE) == RTC_TAMPERMASK_FLAG_ENABLE) || \
                                                    ((STATE) == RTC_TAMPERMASK_FLAG_DISABLE))

Definition at line 1242 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_PRECHARGE_DURATION ( DURATION )
Value:
(((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
                                                    ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
                                                    ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
                                                   ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))

Definition at line 1259 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_PULLUP_STATE ( STATE )
Value:
(((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \
                                           ((STATE) == RTC_TAMPER_PULLUP_DISABLE))

Definition at line 1267 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_SAMPLING_FREQ ( FREQ )
Value:
(((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512)  || \
                                          ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))

Definition at line 1250 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION ( DETECTION )
Value:
(((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
                                                              ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))

Definition at line 1264 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_TRIGGER ( TRIGGER )
Value:
(((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
                                        ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
                                        ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
                                        ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))

Definition at line 1234 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TIMESTAMP_PIN ( PIN ) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))

Definition at line 1232 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTimeStamp(), and HAL_RTCEx_SetTimeStamp_IT().

#define IS_RTC_WAKEUP_CLOCK ( CLOCK )
Value:
(((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16)   || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8)    || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4)    || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2)    || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
                                    ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))

Definition at line 1270 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define IS_RTC_WAKEUP_COUNTER ( COUNTER ) ((COUNTER) <= RTC_WUTR_WUT)

Definition at line 1277 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetWakeUpTimer(), and HAL_RTCEx_SetWakeUpTimer_IT().

#define IS_TIMESTAMP_EDGE ( EDGE )
Value:
(((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
                                 ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))

Definition at line 1225 of file stm32wbxx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTimeStamp(), and HAL_RTCEx_SetTimeStamp_IT().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAI Private Typedefs

Enumerations
SAI Private Typedefs
SAI

Enumerations

enum SAI_ModeTypedef { SAI_MODE_DMA, SAI_MODE_IT }

Enumeration Type Documentation

enum SAI_ModeTypedef
Enumerator:
SAI_MODE_DMA
SAI_MODE_IT

Definition at line 234 of file stm32wbxx_hal_sai.c.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAI Private Constants

Defines
SAI Private Constants
SAI

Defines

#define | SAI_DEFAULT_TIMEOUT 4U
#define | SAI_LONG_TIMEOUT 1000U

Define Documentation

#define SAI_DEFAULT_TIMEOUT 4U

Definition at line 247 of file stm32wbxx_hal_sai.c.

Referenced by SAI_Disable().

#define SAI_LONG_TIMEOUT 1000U

Definition at line 248 of file stm32wbxx_hal_sai.c.

Referenced by HAL_SAI_Transmit_DMA().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAI Private Functions

Functions
SAI Private Functions
SAI

Private functions. More...

Functions

static void | SAI_FillFifo (SAI_HandleTypeDef *hsai)
Fill the fifo.
static uint32_t | SAI_InterruptFlag (const SAI_HandleTypeDef *hsai, SAI_ModeTypedef mode)
Return the interrupt flag to set according the SAI setup.
static HAL_StatusTypeDef | SAI_InitI2S (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initialize the SAI I2S protocol according to the specified parameters in the SAI_InitTypeDef and create the associated handle.
static HAL_StatusTypeDef | SAI_InitPCM (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initialize the SAI PCM protocol according to the specified parameters in the SAI_InitTypeDef and create the associated handle.
static HAL_StatusTypeDef | SAI_Disable (SAI_HandleTypeDef *hsai)
Disable the SAI and wait for the disabling.
static void | SAI_Transmit_IT8Bit (SAI_HandleTypeDef *hsai)
Tx Handler for Transmit in Interrupt mode 8-Bit transfer.
static void | SAI_Transmit_IT16Bit (SAI_HandleTypeDef *hsai)
Tx Handler for Transmit in Interrupt mode for 16-Bit transfer.
static void | SAI_Transmit_IT32Bit (SAI_HandleTypeDef *hsai)
Tx Handler for Transmit in Interrupt mode for 32-Bit transfer.
static void | SAI_Receive_IT8Bit (SAI_HandleTypeDef *hsai)
Rx Handler for Receive in Interrupt mode 8-Bit transfer.
static void | SAI_Receive_IT16Bit (SAI_HandleTypeDef *hsai)
Rx Handler for Receive in Interrupt mode for 16-Bit transfer.
static void | SAI_Receive_IT32Bit (SAI_HandleTypeDef *hsai)
Rx Handler for Receive in Interrupt mode for 32-Bit transfer.
static void | SAI_DMATxCplt (DMA_HandleTypeDef *hdma)
DMA SAI transmit process complete callback.
static void | SAI_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SAI transmit process half complete callback.
static void | SAI_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA SAI receive process complete callback.
static void | SAI_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SAI receive process half complete callback.
static void | SAI_DMAError (DMA_HandleTypeDef *hdma)
DMA SAI communication error callback.
static void | SAI_DMAAbort (DMA_HandleTypeDef *hdma)
DMA SAI Abort callback.

Detailed Description

Private functions.

Function Documentation

static HAL_StatusTypeDef SAI_Disable ( SAI_HandleTypeDef * hsai ) [static]

Disable the SAI and wait for the disabling.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2335 of file stm32wbxx_hal_sai.c.

References __HAL_SAI_DISABLE, __SAI_HandleTypeDef::ErrorCode, HAL_SAI_ERROR_TIMEOUT, __SAI_HandleTypeDef::Instance, and SAI_DEFAULT_TIMEOUT.

Referenced by HAL_SAI_Abort(), HAL_SAI_DeInit(), HAL_SAI_DMAStop(), HAL_SAI_Init(), HAL_SAI_Receive(), HAL_SAI_Transmit(), SAI_DMAAbort(), and SAI_DMAError().

static void SAI_DMAAbort ( DMA_HandleTypeDef * hdma ) [static]

DMA SAI Abort callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2697 of file stm32wbxx_hal_sai.c.

References __SAI_HandleTypeDef::ErrorCallback, __SAI_HandleTypeDef::ErrorCode, HAL_SAI_ERROR_WCKCFG, HAL_SAI_ErrorCallback(), HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Instance, SAI_Disable(), __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_IRQHandler().

static void SAI_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA SAI communication error callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2663 of file stm32wbxx_hal_sai.c.

References __SAI_HandleTypeDef::ErrorCallback, __SAI_HandleTypeDef::ErrorCode, HAL_SAI_ERROR_DMA, HAL_SAI_ErrorCallback(), HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Instance, SAI_Disable(), __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Receive_DMA(), and HAL_SAI_Transmit_DMA().

static void SAI_DMARxCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SAI receive process complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2618 of file stm32wbxx_hal_sai.c.

References __HAL_SAI_DISABLE_IT, DMA_CIRCULAR, HAL_SAI_RxCpltCallback(), HAL_SAI_STATE_READY, __DMA_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, __SAI_HandleTypeDef::RxCpltCallback, SAI_InterruptFlag(), SAI_MODE_DMA, __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Receive_DMA().

static void SAI_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SAI receive process half complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2646 of file stm32wbxx_hal_sai.c.

References HAL_SAI_RxHalfCpltCallback(), and __SAI_HandleTypeDef::RxHalfCpltCallback.

Referenced by HAL_SAI_Receive_DMA().

static void SAI_DMATxCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SAI transmit process complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2572 of file stm32wbxx_hal_sai.c.

References __HAL_SAI_DISABLE_IT, DMA_CIRCULAR, HAL_SAI_STATE_READY, HAL_SAI_TxCpltCallback(), __DMA_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, DMA_InitTypeDef::Mode, SAI_InterruptFlag(), SAI_MODE_DMA, __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::TxCpltCallback, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Transmit_DMA().

static void SAI_DMATxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SAI transmit process half complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2601 of file stm32wbxx_hal_sai.c.

References HAL_SAI_TxHalfCpltCallback(), and __SAI_HandleTypeDef::TxHalfCpltCallback.

Referenced by HAL_SAI_Transmit_DMA().

static void SAI_FillFifo ( SAI_HandleTypeDef * hsai ) [static]

Fill the fifo.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2259 of file stm32wbxx_hal_sai.c.

References SAI_InitTypeDef::CompandingMode, SAI_InitTypeDef::DataSize, __SAI_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_DATASIZE_16, SAI_DATASIZE_8, SAI_FIFOSTATUS_FULL, SAI_NOCOMPANDING, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Transmit(), and HAL_SAI_Transmit_IT().

static HAL_StatusTypeDef SAI_InitI2S | ( | SAI_HandleTypeDef * | hsai,
 |  | uint32_t | protocol,
 |  | uint32_t | datasize,
 |  | uint32_t | nbslot
 | ) |  | [static]

Initialize the SAI I2S protocol according to the specified parameters in the SAI_InitTypeDef and create the associated handle.

Parameters:
hsai | pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
protocol | one of the supported protocol.
datasize | one of the supported datasize SAI protocol data size.
nbslot | number of slot minimum value is 2 and max is 16. the value must be a multiple of 2.
Return values:
HAL status

Definition at line 2094 of file stm32wbxx_hal_sai.c.

References SAI_FrameInitTypeDef::ActiveFrameLength, SAI_InitTypeDef::AudioMode, SAI_InitTypeDef::ClockStrobing, SAI_InitTypeDef::DataSize, SAI_InitTypeDef::FirstBit, SAI_SlotInitTypeDef::FirstBitOffset, __SAI_HandleTypeDef::FrameInit, SAI_FrameInitTypeDef::FrameLength, SAI_FrameInitTypeDef::FSDefinition, SAI_FrameInitTypeDef::FSOffset, SAI_FrameInitTypeDef::FSPolarity, __SAI_HandleTypeDef::Init, SAI_InitTypeDef::Protocol, SAI_CLOCKSTROBING_FALLINGEDGE, SAI_CLOCKSTROBING_RISINGEDGE, SAI_DATASIZE_16, SAI_DATASIZE_24, SAI_DATASIZE_32, SAI_FIRSTBIT_MSB, SAI_FREE_PROTOCOL, SAI_FS_ACTIVE_HIGH, SAI_FS_ACTIVE_LOW, SAI_FS_BEFOREFIRSTBIT, SAI_FS_CHANNEL_IDENTIFICATION, SAI_FS_FIRSTBIT, SAI_I2S_LSBJUSTIFIED, SAI_I2S_STANDARD, SAI_MODEMASTER_TX, SAI_MODESLAVE_TX, SAI_PROTOCOL_DATASIZE_16BIT, SAI_PROTOCOL_DATASIZE_16BITEXTENDED, SAI_PROTOCOL_DATASIZE_24BIT, SAI_PROTOCOL_DATASIZE_32BIT, SAI_SLOTACTIVE_ALL, SAI_SLOTSIZE_16B, SAI_SLOTSIZE_32B, SAI_SlotInitTypeDef::SlotActive, __SAI_HandleTypeDef::SlotInit, SAI_SlotInitTypeDef::SlotNumber, and SAI_SlotInitTypeDef::SlotSize.

Referenced by HAL_SAI_InitProtocol().

static HAL_StatusTypeDef SAI_InitPCM | ( | SAI_HandleTypeDef * | hsai,
 |  | uint32_t | protocol,
 |  | uint32_t | datasize,
 |  | uint32_t | nbslot
 | ) |  | [static]

Initialize the SAI PCM protocol according to the specified parameters in the SAI_InitTypeDef and create the associated handle.

Parameters:
hsai | pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
protocol | one of the supported protocol
datasize | one of the supported datasize SAI protocol data size
nbslot | number of slot minimum value is 1 and the max is 16.
Return values:
HAL status

Definition at line 2189 of file stm32wbxx_hal_sai.c.

References SAI_FrameInitTypeDef::ActiveFrameLength, SAI_InitTypeDef::AudioMode, SAI_InitTypeDef::ClockStrobing, SAI_InitTypeDef::DataSize, SAI_InitTypeDef::FirstBit, SAI_SlotInitTypeDef::FirstBitOffset, __SAI_HandleTypeDef::FrameInit, SAI_FrameInitTypeDef::FrameLength, SAI_FrameInitTypeDef::FSDefinition, SAI_FrameInitTypeDef::FSOffset, SAI_FrameInitTypeDef::FSPolarity, __SAI_HandleTypeDef::Init, SAI_InitTypeDef::Protocol, SAI_CLOCKSTROBING_FALLINGEDGE, SAI_CLOCKSTROBING_RISINGEDGE, SAI_DATASIZE_16, SAI_DATASIZE_24, SAI_DATASIZE_32, SAI_FIRSTBIT_MSB, SAI_FREE_PROTOCOL, SAI_FS_ACTIVE_HIGH, SAI_FS_BEFOREFIRSTBIT, SAI_FS_STARTFRAME, SAI_MODEMASTER_TX, SAI_MODESLAVE_TX, SAI_PCM_SHORT, SAI_PROTOCOL_DATASIZE_16BIT, SAI_PROTOCOL_DATASIZE_16BITEXTENDED, SAI_PROTOCOL_DATASIZE_24BIT, SAI_PROTOCOL_DATASIZE_32BIT, SAI_SLOTACTIVE_ALL, SAI_SLOTSIZE_16B, SAI_SLOTSIZE_32B, SAI_SlotInitTypeDef::SlotActive, __SAI_HandleTypeDef::SlotInit, SAI_SlotInitTypeDef::SlotNumber, and SAI_SlotInitTypeDef::SlotSize.

Referenced by HAL_SAI_InitProtocol().

static uint32_t SAI_InterruptFlag | ( | const SAI_HandleTypeDef * | hsai,
 |  | SAI_ModeTypedef | mode
 | ) |  | [static]

Return the interrupt flag to set according the SAI setup.

Parameters:
hsai | pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
mode | SAI_MODE_DMA or SAI_MODE_IT
Return values:
the list of the IT flag to enable

Definition at line 2302 of file stm32wbxx_hal_sai.c.

References SAI_InitTypeDef::AudioMode, __SAI_HandleTypeDef::Init, SAI_InitTypeDef::Protocol, SAI_AC97_PROTOCOL, SAI_IT_AFSDET, SAI_IT_CNRDY, SAI_IT_FREQ, SAI_IT_LFSDET, SAI_IT_OVRUDR, SAI_IT_WCKCFG, SAI_MODE_IT, SAI_MODEMASTER_RX, SAI_MODESLAVE_RX, and SAI_MODESLAVE_TX.

Referenced by HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit_DMA(), HAL_SAI_Transmit_IT(), SAI_DMARxCplt(), SAI_DMATxCplt(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

static void SAI_Receive_IT16Bit ( SAI_HandleTypeDef * hsai ) [static]

Rx Handler for Receive in Interrupt mode for 16-Bit transfer.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2496 of file stm32wbxx_hal_sai.c.

References __HAL_SAI_CLEAR_FLAG, __HAL_SAI_DISABLE_IT, HAL_SAI_RxCpltCallback(), HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, __SAI_HandleTypeDef::RxCpltCallback, SAI_FLAG_OVRUDR, SAI_InterruptFlag(), SAI_MODE_IT, __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Receive_IT().

static void SAI_Receive_IT32Bit ( SAI_HandleTypeDef * hsai ) [static]

Rx Handler for Receive in Interrupt mode for 32-Bit transfer.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2532 of file stm32wbxx_hal_sai.c.

References __HAL_SAI_CLEAR_FLAG, __HAL_SAI_DISABLE_IT, HAL_SAI_RxCpltCallback(), HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, __SAI_HandleTypeDef::RxCpltCallback, SAI_FLAG_OVRUDR, SAI_InterruptFlag(), SAI_MODE_IT, __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Receive_IT().

static void SAI_Receive_IT8Bit ( SAI_HandleTypeDef * hsai ) [static]

Rx Handler for Receive in Interrupt mode 8-Bit transfer.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2465 of file stm32wbxx_hal_sai.c.

References __HAL_SAI_CLEAR_FLAG, __HAL_SAI_DISABLE_IT, HAL_SAI_RxCpltCallback(), HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, __SAI_HandleTypeDef::RxCpltCallback, SAI_FLAG_OVRUDR, SAI_InterruptFlag(), SAI_MODE_IT, __SAI_HandleTypeDef::State, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Receive_IT().

static void SAI_Transmit_IT16Bit ( SAI_HandleTypeDef * hsai ) [static]

Tx Handler for Transmit in Interrupt mode for 16-Bit transfer.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2395 of file stm32wbxx_hal_sai.c.

References __HAL_SAI_DISABLE_IT, HAL_SAI_STATE_READY, HAL_SAI_TxCpltCallback(), __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_InterruptFlag(), SAI_MODE_IT, __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::TxCpltCallback, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Transmit_IT().

static void SAI_Transmit_IT32Bit ( SAI_HandleTypeDef * hsai ) [static]

Tx Handler for Transmit in Interrupt mode for 32-Bit transfer.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2428 of file stm32wbxx_hal_sai.c.

References __HAL_SAI_DISABLE_IT, HAL_SAI_STATE_READY, HAL_SAI_TxCpltCallback(), __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_InterruptFlag(), SAI_MODE_IT, __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::TxCpltCallback, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Transmit_IT().

static void SAI_Transmit_IT8Bit ( SAI_HandleTypeDef * hsai ) [static]

Tx Handler for Transmit in Interrupt mode 8-Bit transfer.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2366 of file stm32wbxx_hal_sai.c.

References __HAL_SAI_DISABLE_IT, HAL_SAI_STATE_READY, HAL_SAI_TxCpltCallback(), __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_InterruptFlag(), SAI_MODE_IT, __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::TxCpltCallback, and __SAI_HandleTypeDef::XferCount.

Referenced by HAL_SAI_Transmit_IT().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SAI Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SAI_InitProtocol (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initialize the structure FrameInit, SlotInit and the low part of Init according to the specified parameters and call the function HAL_SAI_Init to initialize the SAI block.
HAL_StatusTypeDef | HAL_SAI_Init (SAI_HandleTypeDef *hsai)
Initialize the SAI according to the specified parameters.
HAL_StatusTypeDef | HAL_SAI_DeInit (SAI_HandleTypeDef *hsai)
DeInitialize the SAI peripheral.
__weak void | HAL_SAI_MspInit (SAI_HandleTypeDef *hsai)
Initialize the SAI MSP.
__weak void | HAL_SAI_MspDeInit (SAI_HandleTypeDef *hsai)
DeInitialize the SAI MSP.
HAL_StatusTypeDef | HAL_SAI_RegisterCallback (SAI_HandleTypeDef *hsai, HAL_SAI_CallbackIDTypeDef CallbackID, pSAI_CallbackTypeDef pCallback)
Register a user SAI callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SAI_UnRegisterCallback (SAI_HandleTypeDef *hsai, HAL_SAI_CallbackIDTypeDef CallbackID)
Unregister a user SAI callback.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
             ##### Initialization and de-initialization functions #####
 ===============================================================================
  [..]  This subsection provides a set of functions allowing to initialize and
        de-initialize the SAIx peripheral:

      (+) User must implement HAL_SAI_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).

      (+) Call the function HAL_SAI_Init() to configure the selected device with
          the selected configuration:
        (++) Mode (Master/slave TX/RX)
        (++) Protocol
        (++) Data Size
        (++) MCLK Output
        (++) Audio frequency
        (++) FIFO Threshold
        (++) Frame Config
        (++) Slot Config
        (++) PDM Config

      (+) Call the function HAL_SAI_DeInit() to restore the default configuration
          of the selected SAI peripheral.

Function Documentation

HAL_StatusTypeDef HAL_SAI_DeInit ( SAI_HandleTypeDef * hsai )

DeInitialize the SAI peripheral.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 622 of file stm32wbxx_hal_sai.c.

References __SAI_HandleTypeDef::ErrorCode, HAL_SAI_ERROR_NONE, HAL_SAI_MspDeInit(), HAL_SAI_STATE_BUSY, HAL_SAI_STATE_READY, HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::MspDeInitCallback, SAI_Disable(), and __SAI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SAI_Init ( SAI_HandleTypeDef * hsai )

Initialize the SAI according to the specified parameters.

in the SAI_InitTypeDef structure and initialize the associated handle.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 370 of file stm32wbxx_hal_sai.c.

References SAI_PdmInitTypeDef::Activation, SAI_FrameInitTypeDef::ActiveFrameLength, assert_param, SAI_InitTypeDef::AudioFrequency, SAI_InitTypeDef::AudioMode, SAI_PdmInitTypeDef::ClockEnable, SAI_InitTypeDef::ClockStrobing, SAI_InitTypeDef::CompandingMode, SAI_InitTypeDef::DataSize, __SAI_HandleTypeDef::ErrorCallback, __SAI_HandleTypeDef::ErrorCode, SAI_InitTypeDef::FIFOThreshold, SAI_InitTypeDef::FirstBit, SAI_SlotInitTypeDef::FirstBitOffset, __SAI_HandleTypeDef::FrameInit, SAI_FrameInitTypeDef::FrameLength, SAI_FrameInitTypeDef::FSDefinition, SAI_FrameInitTypeDef::FSOffset, SAI_FrameInitTypeDef::FSPolarity, HAL_RCCEx_GetPeriphCLKFreq(), HAL_SAI_ERROR_NONE, HAL_SAI_ErrorCallback(), HAL_SAI_MspInit(), HAL_SAI_RxCpltCallback(), HAL_SAI_RxHalfCpltCallback(), HAL_SAI_STATE_BUSY, HAL_SAI_STATE_READY, HAL_SAI_STATE_RESET, HAL_SAI_TxCpltCallback(), HAL_SAI_TxHalfCpltCallback(), __SAI_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, IS_SAI_AUDIO_FREQUENCY, IS_SAI_BLOCK_ACTIVE_FRAME, IS_SAI_BLOCK_CLOCK_STROBING, IS_SAI_BLOCK_COMPANDING_MODE, IS_SAI_BLOCK_DATASIZE, IS_SAI_BLOCK_FIFO_THRESHOLD, IS_SAI_BLOCK_FIRST_BIT, IS_SAI_BLOCK_FIRSTBIT_OFFSET, IS_SAI_BLOCK_FRAME_LENGTH, IS_SAI_BLOCK_FS_DEFINITION, IS_SAI_BLOCK_FS_OFFSET, IS_SAI_BLOCK_FS_POLARITY, IS_SAI_BLOCK_MASTER_DIVIDER, IS_SAI_BLOCK_MCK_OUTPUT, IS_SAI_BLOCK_MCK_OVERSAMPLING, IS_SAI_BLOCK_MODE, IS_SAI_BLOCK_NODIVIDER, IS_SAI_BLOCK_OUTPUT_DRIVE, IS_SAI_BLOCK_PROTOCOL, IS_SAI_BLOCK_SLOT_NUMBER, IS_SAI_BLOCK_SLOT_SIZE, IS_SAI_BLOCK_SYNCEXT, IS_SAI_BLOCK_SYNCHRO, IS_SAI_BLOCK_TRISTATE_MANAGEMENT, IS_SAI_MONO_STEREO_MODE, IS_SAI_PDM_CLOCK_ENABLE, IS_SAI_PDM_MIC_PAIRS_NUMBER, IS_SAI_SLOT_ACTIVE, __SAI_HandleTypeDef::Lock, SAI_InitTypeDef::Mckdiv, SAI_InitTypeDef::MckOutput, SAI_InitTypeDef::MckOverSampling, SAI_PdmInitTypeDef::MicPairsNbr, SAI_InitTypeDef::MonoStereoMode, __SAI_HandleTypeDef::MspInitCallback, SAI_InitTypeDef::NoDivider, SAI_InitTypeDef::OutputDrive, SAI_InitTypeDef::PdmInit, SAI_InitTypeDef::Protocol, RCC_PERIPHCLK_SAI1, __SAI_HandleTypeDef::RxCpltCallback, __SAI_HandleTypeDef::RxHalfCpltCallback, SAI_AC97_PROTOCOL, SAI_ASYNCHRONOUS, SAI_AUDIO_FREQUENCY_MCKDIV, SAI_CLOCKSTROBING_RISINGEDGE, SAI_Disable(), SAI_FREE_PROTOCOL, SAI_MASTERDIVIDER_DISABLE, SAI_MCK_OVERSAMPLING_ENABLE, SAI_MODEMASTER_RX, SAI_MODEMASTER_TX, SAI_MODESLAVE_TX, SAI_SPDIF_PROTOCOL, SAI_SYNCHRONOUS, SAI_SlotInitTypeDef::SlotActive, __SAI_HandleTypeDef::SlotInit, SAI_SlotInitTypeDef::SlotNumber, SAI_SlotInitTypeDef::SlotSize, __SAI_HandleTypeDef::State, SAI_InitTypeDef::Synchro, SAI_InitTypeDef::SynchroExt, SAI_InitTypeDef::TriState, __SAI_HandleTypeDef::TxCpltCallback, and __SAI_HandleTypeDef::TxHalfCpltCallback.

Referenced by HAL_SAI_InitProtocol().

HAL_StatusTypeDef HAL_SAI_InitProtocol | ( | SAI_HandleTypeDef * | hsai,
 |  | uint32_t | protocol,
 |  | uint32_t | datasize,
 |  | uint32_t | nbslot
 | ) |  |

Initialize the structure FrameInit, SlotInit and the low part of Init according to the specified parameters and call the function HAL_SAI_Init to initialize the SAI block.

Parameters:
hsai | pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
protocol | one of the supported protocol SAI Supported protocol
datasize | one of the supported datasize SAI protocol data size the configuration information for SAI module.
nbslot | Number of slot.
Return values:
HAL status

Definition at line 331 of file stm32wbxx_hal_sai.c.

References assert_param, HAL_SAI_Init(), IS_SAI_PROTOCOL_DATASIZE, IS_SAI_SUPPORTED_PROTOCOL, SAI_I2S_LSBJUSTIFIED, SAI_I2S_MSBJUSTIFIED, SAI_I2S_STANDARD, SAI_InitI2S(), SAI_InitPCM(), SAI_PCM_LONG, and SAI_PCM_SHORT.

void HAL_SAI_MspDeInit ( SAI_HandleTypeDef * hsai )

DeInitialize the SAI MSP.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 706 of file stm32wbxx_hal_sai.c.

Referenced by HAL_SAI_DeInit(), and HAL_SAI_UnRegisterCallback().

void HAL_SAI_MspInit ( SAI_HandleTypeDef * hsai )

Initialize the SAI MSP.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 690 of file stm32wbxx_hal_sai.c.

Referenced by HAL_SAI_Init(), and HAL_SAI_UnRegisterCallback().

HAL_StatusTypeDef HAL_SAI_RegisterCallback | ( | SAI_HandleTypeDef * | hsai,
 |  | HAL_SAI_CallbackIDTypeDef | CallbackID,
 |  | pSAI_CallbackTypeDef | pCallback
 | ) |  |

Register a user SAI callback to be used instead of the weak predefined callback.

Parameters:
hsai | SAI handle.
CallbackID ID of the callback to be registered. This parameter can be one of the following values:
  • HAL_SAI_RX_COMPLETE_CB_ID receive complete callback ID.
  • HAL_SAI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID.
  • HAL_SAI_TX_COMPLETE_CB_ID transmit complete callback ID.
  • HAL_SAI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID.
  • HAL_SAI_ERROR_CB_ID error callback ID.
  • HAL_SAI_MSPINIT_CB_ID MSP init callback ID.
  • HAL_SAI_MSPDEINIT_CB_ID MSP de-init callback ID.
pCallback | pointer to the callback function.
Return values:
HAL status.

Definition at line 733 of file stm32wbxx_hal_sai.c.

References __SAI_HandleTypeDef::ErrorCallback, __SAI_HandleTypeDef::ErrorCode, HAL_SAI_ERROR_CB_ID, HAL_SAI_ERROR_INVALID_CALLBACK, HAL_SAI_MSPDEINIT_CB_ID, HAL_SAI_MSPINIT_CB_ID, HAL_SAI_RX_COMPLETE_CB_ID, HAL_SAI_RX_HALFCOMPLETE_CB_ID, HAL_SAI_STATE_READY, HAL_SAI_STATE_RESET, HAL_SAI_TX_COMPLETE_CB_ID, HAL_SAI_TX_HALFCOMPLETE_CB_ID, __SAI_HandleTypeDef::MspDeInitCallback, __SAI_HandleTypeDef::MspInitCallback, __SAI_HandleTypeDef::RxCpltCallback, __SAI_HandleTypeDef::RxHalfCpltCallback, __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::TxCpltCallback, and __SAI_HandleTypeDef::TxHalfCpltCallback.

HAL_StatusTypeDef HAL_SAI_UnRegisterCallback | ( | SAI_HandleTypeDef * | hsai,
 |  | HAL_SAI_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a user SAI callback.

SAI callback is redirected to the weak predefined callback.

Parameters:
hsai SAI handle.
CallbackID ID of the callback to be unregistered. This parameter can be one of the following values:
  • HAL_SAI_RX_COMPLETE_CB_ID receive complete callback ID.
  • HAL_SAI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID.
  • HAL_SAI_TX_COMPLETE_CB_ID transmit complete callback ID.
  • HAL_SAI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID.
  • HAL_SAI_ERROR_CB_ID error callback ID.
  • HAL_SAI_MSPINIT_CB_ID MSP init callback ID.
  • HAL_SAI_MSPDEINIT_CB_ID MSP de-init callback ID.
Return values:
HAL status.

Definition at line 825 of file stm32wbxx_hal_sai.c.

References __SAI_HandleTypeDef::ErrorCallback, __SAI_HandleTypeDef::ErrorCode, HAL_SAI_ERROR_CB_ID, HAL_SAI_ERROR_INVALID_CALLBACK, HAL_SAI_ErrorCallback(), HAL_SAI_MspDeInit(), HAL_SAI_MSPDEINIT_CB_ID, HAL_SAI_MspInit(), HAL_SAI_MSPINIT_CB_ID, HAL_SAI_RX_COMPLETE_CB_ID, HAL_SAI_RX_HALFCOMPLETE_CB_ID, HAL_SAI_RxCpltCallback(), HAL_SAI_RxHalfCpltCallback(), HAL_SAI_STATE_READY, HAL_SAI_STATE_RESET, HAL_SAI_TX_COMPLETE_CB_ID, HAL_SAI_TX_HALFCOMPLETE_CB_ID, HAL_SAI_TxCpltCallback(), HAL_SAI_TxHalfCpltCallback(), __SAI_HandleTypeDef::MspDeInitCallback, __SAI_HandleTypeDef::MspInitCallback, __SAI_HandleTypeDef::RxCpltCallback, __SAI_HandleTypeDef::RxHalfCpltCallback, __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::TxCpltCallback, and __SAI_HandleTypeDef::TxHalfCpltCallback.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IO operation functions

Functions
IO operation functions
SAI Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_SAI_Transmit (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SAI_Receive (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SAI_Transmit_IT (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SAI_Receive_IT (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SAI_DMAPause (SAI_HandleTypeDef *hsai)
Pause the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_DMAResume (SAI_HandleTypeDef *hsai)
Resume the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_DMAStop (SAI_HandleTypeDef *hsai)
Stop the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_Abort (SAI_HandleTypeDef *hsai)
Abort the current transfer and disable the SAI.
HAL_StatusTypeDef | HAL_SAI_Transmit_DMA (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SAI_Receive_DMA (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SAI_EnableTxMuteMode (SAI_HandleTypeDef *hsai, uint16_t val)
Enable the Tx mute mode.
HAL_StatusTypeDef | HAL_SAI_DisableTxMuteMode (SAI_HandleTypeDef *hsai)
Disable the Tx mute mode.
HAL_StatusTypeDef | HAL_SAI_EnableRxMuteMode (SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter)
Enable the Rx mute detection.
HAL_StatusTypeDef | HAL_SAI_DisableRxMuteMode (SAI_HandleTypeDef *hsai)
Disable the Rx mute detection.
void | HAL_SAI_IRQHandler (SAI_HandleTypeDef *hsai)
Handle SAI interrupt request.
__weak void | HAL_SAI_TxCpltCallback (SAI_HandleTypeDef *hsai)
Tx Transfer completed callback.
__weak void | HAL_SAI_TxHalfCpltCallback (SAI_HandleTypeDef *hsai)
Tx Transfer Half completed callback.
__weak void | HAL_SAI_RxCpltCallback (SAI_HandleTypeDef *hsai)
Rx Transfer completed callback.
__weak void | HAL_SAI_RxHalfCpltCallback (SAI_HandleTypeDef *hsai)
Rx Transfer half completed callback.
__weak void | HAL_SAI_ErrorCallback (SAI_HandleTypeDef *hsai)
SAI error callback.

Detailed Description

Data transfers functions.

  ==============================================================================
                      ##### IO operation functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to manage the SAI data
    transfers.

    (+) There are two modes of transfer:
      (++) Blocking mode : The communication is performed in the polling mode.
           The status of all data processing is returned by the same function
           after finishing transfer.
      (++) No-Blocking mode : The communication is performed using Interrupts
           or DMA. These functions return the status of the transfer startup.
           The end of the data processing will be indicated through the
           dedicated SAI IRQ when using Interrupt mode or the DMA IRQ when
           using DMA mode.

    (+) Blocking mode functions are :
      (++) HAL_SAI_Transmit()
      (++) HAL_SAI_Receive()

    (+) Non Blocking mode functions with Interrupt are :
      (++) HAL_SAI_Transmit_IT()
      (++) HAL_SAI_Receive_IT()

    (+) Non Blocking mode functions with DMA are :
      (++) HAL_SAI_Transmit_DMA()
      (++) HAL_SAI_Receive_DMA()

    (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
      (++) HAL_SAI_TxCpltCallback()
      (++) HAL_SAI_RxCpltCallback()
      (++) HAL_SAI_ErrorCallback()

Function Documentation

HAL_StatusTypeDef HAL_SAI_Abort ( SAI_HandleTypeDef * hsai )

Abort the current transfer and disable the SAI.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 1387 of file stm32wbxx_hal_sai.c.

References HAL_DMA_Abort(), HAL_SAI_STATE_BUSY_RX, HAL_SAI_STATE_BUSY_TX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::hdmarx, __SAI_HandleTypeDef::hdmatx, __SAI_HandleTypeDef::Instance, SAI_Disable(), and __SAI_HandleTypeDef::State.

Referenced by HAL_SAI_IRQHandler().

HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode ( SAI_HandleTypeDef * hsai )

Disable the Rx mute detection.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 1663 of file stm32wbxx_hal_sai.c.

References __HAL_SAI_DISABLE_IT, HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::mutecallback, SAI_IT_MUTEDET, and __SAI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode ( SAI_HandleTypeDef * hsai )

Disable the Tx mute mode.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 1622 of file stm32wbxx_hal_sai.c.

References HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::Instance, and __SAI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SAI_DMAPause ( SAI_HandleTypeDef * hsai )

Pause the audio stream playing from the Media.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 1290 of file stm32wbxx_hal_sai.c.

References __SAI_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SAI_DMAResume ( SAI_HandleTypeDef * hsai )

Resume the audio stream playing from the Media.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 1310 of file stm32wbxx_hal_sai.c.

References __HAL_SAI_ENABLE, and __SAI_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SAI_DMAStop ( SAI_HandleTypeDef * hsai )

Stop the audio stream playing from the Media.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL status

Definition at line 1337 of file stm32wbxx_hal_sai.c.

References HAL_DMA_Abort(), HAL_SAI_STATE_BUSY_RX, HAL_SAI_STATE_BUSY_TX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::hdmarx, __SAI_HandleTypeDef::hdmatx, __SAI_HandleTypeDef::Instance, SAI_Disable(), and __SAI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode | ( | SAI_HandleTypeDef * | hsai,
 |  | SAIcallback | callback,
 |  | uint16_t | counter
 | ) |  |

Enable the Rx mute detection.

Parameters:
hsai | pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
callback | function called when the mute is detected.
counter | number a data before mute detection max 63.
Return values:
HAL status

Definition at line 1640 of file stm32wbxx_hal_sai.c.

References __HAL_SAI_ENABLE_IT, assert_param, HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::Instance, IS_SAI_BLOCK_MUTE_COUNTER, __SAI_HandleTypeDef::mutecallback, SAI_IT_MUTEDET, and __SAI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode | ( | SAI_HandleTypeDef * | hsai,
 |  | uint16_t | val
 | ) |  |

Enable the Tx mute mode.

Parameters:
hsai | pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
val | value sent during the mute SAI Block Mute Value
Return values:
HAL status

Definition at line 1603 of file stm32wbxx_hal_sai.c.

References assert_param, HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::Instance, IS_SAI_BLOCK_MUTE_VALUE, and __SAI_HandleTypeDef::State.

void HAL_SAI_ErrorCallback ( SAI_HandleTypeDef * hsai )

SAI error callback.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2019 of file stm32wbxx_hal_sai.c.

Referenced by HAL_SAI_Init(), HAL_SAI_IRQHandler(), HAL_SAI_UnRegisterCallback(), SAI_DMAAbort(), and SAI_DMAError().

void HAL_SAI_IRQHandler ( SAI_HandleTypeDef * hsai )

Handle SAI interrupt request.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 1682 of file stm32wbxx_hal_sai.c.

References __HAL_SAI_CLEAR_FLAG, __SAI_HandleTypeDef::ErrorCallback, __SAI_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_SAI_Abort(), HAL_SAI_ERROR_AFSDET, HAL_SAI_ERROR_CNREADY, HAL_SAI_ERROR_DMA, HAL_SAI_ERROR_LFSDET, HAL_SAI_ERROR_OVR, HAL_SAI_ERROR_UDR, HAL_SAI_ERROR_WCKCFG, HAL_SAI_ErrorCallback(), HAL_SAI_STATE_BUSY_RX, HAL_SAI_STATE_READY, HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::hdmarx, __SAI_HandleTypeDef::hdmatx, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::InterruptServiceRoutine, __SAI_HandleTypeDef::mutecallback, SAI_DMAAbort(), SAI_FLAG_AFSDET, SAI_FLAG_CNRDY, SAI_FLAG_LFSDET, SAI_FLAG_MUTEDET, SAI_FLAG_OVRUDR, SAI_FLAG_WCKCFG, SAI_IT_AFSDET, SAI_IT_CNRDY, SAI_IT_FREQ, SAI_IT_LFSDET, SAI_IT_MUTEDET, SAI_IT_OVRUDR, SAI_IT_WCKCFG, __SAI_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, and __SAI_HandleTypeDef::XferCount.

HAL_StatusTypeDef HAL_SAI_Receive | ( | SAI_HandleTypeDef * | hsai,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hsai | pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
pData | Pointer to data buffer
Size | Amount of data to be received
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1060 of file stm32wbxx_hal_sai.c.

References __HAL_SAI_ENABLE, SAI_InitTypeDef::CompandingMode, SAI_InitTypeDef::DataSize, __SAI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SAI_ERROR_NONE, HAL_SAI_ERROR_TIMEOUT, HAL_SAI_STATE_BUSY_RX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_DATASIZE_16, SAI_DATASIZE_8, SAI_Disable(), SAI_FIFOSTATUS_EMPTY, SAI_NOCOMPANDING, __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::XferCount, and __SAI_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SAI_Receive_DMA | ( | SAI_HandleTypeDef * | hsai,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with DMA.

Parameters:
hsai | pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
pData | Pointer to data buffer
Size | Amount of data to be received
Return values:
HAL status

Definition at line 1534 of file stm32wbxx_hal_sai.c.

References __HAL_SAI_ENABLE, __HAL_SAI_ENABLE_IT, __SAI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SAI_ERROR_NONE, HAL_SAI_STATE_BUSY_RX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::hdmarx, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_DMAError(), SAI_DMARxCplt(), SAI_DMARxHalfCplt(), SAI_InterruptFlag(), SAI_MODE_DMA, __SAI_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __SAI_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, and __SAI_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SAI_Receive_IT | ( | SAI_HandleTypeDef * | hsai,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with Interrupt.

Parameters:
hsai | pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
pData | Pointer to data buffer
Size | Amount of data to be received
Return values:
HAL status

Definition at line 1232 of file stm32wbxx_hal_sai.c.

References __HAL_SAI_ENABLE, __HAL_SAI_ENABLE_IT, SAI_InitTypeDef::CompandingMode, SAI_InitTypeDef::DataSize, __SAI_HandleTypeDef::ErrorCode, HAL_SAI_ERROR_NONE, HAL_SAI_STATE_BUSY_RX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::InterruptServiceRoutine, __SAI_HandleTypeDef::pBuffPtr, SAI_DATASIZE_16, SAI_DATASIZE_8, SAI_InterruptFlag(), SAI_MODE_IT, SAI_NOCOMPANDING, SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::XferCount, and __SAI_HandleTypeDef::XferSize.

void HAL_SAI_RxCpltCallback ( SAI_HandleTypeDef * hsai )

Rx Transfer completed callback.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 1987 of file stm32wbxx_hal_sai.c.

Referenced by HAL_SAI_Init(), HAL_SAI_UnRegisterCallback(), SAI_DMARxCplt(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), and SAI_Receive_IT8Bit().

void HAL_SAI_RxHalfCpltCallback ( SAI_HandleTypeDef * hsai )

Rx Transfer half completed callback.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 2003 of file stm32wbxx_hal_sai.c.

Referenced by HAL_SAI_Init(), HAL_SAI_UnRegisterCallback(), and SAI_DMARxHalfCplt().

HAL_StatusTypeDef HAL_SAI_Transmit | ( | SAI_HandleTypeDef * | hsai,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmit an amount of data in blocking mode.

Parameters:
hsai | pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 947 of file stm32wbxx_hal_sai.c.

References __HAL_SAI_ENABLE, SAI_InitTypeDef::CompandingMode, SAI_InitTypeDef::DataSize, __SAI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SAI_ERROR_NONE, HAL_SAI_ERROR_TIMEOUT, HAL_SAI_STATE_BUSY_TX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_DATASIZE_16, SAI_DATASIZE_8, SAI_Disable(), SAI_FIFOSTATUS_FULL, SAI_FillFifo(), SAI_NOCOMPANDING, __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::XferCount, and __SAI_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SAI_Transmit_DMA | ( | SAI_HandleTypeDef * | hsai,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with DMA.

Parameters:
hsai | pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1447 of file stm32wbxx_hal_sai.c.

References __HAL_SAI_ENABLE, __HAL_SAI_ENABLE_IT, __SAI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_GetTick(), HAL_SAI_ERROR_NONE, HAL_SAI_ERROR_TIMEOUT, HAL_SAI_STATE_BUSY_TX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::hdmatx, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::pBuffPtr, SAI_DMAError(), SAI_DMATxCplt(), SAI_DMATxHalfCplt(), SAI_FIFOSTATUS_EMPTY, SAI_InterruptFlag(), SAI_LONG_TIMEOUT, SAI_MODE_DMA, __SAI_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __SAI_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, and __SAI_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SAI_Transmit_IT | ( | SAI_HandleTypeDef * | hsai,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with Interrupt.

Parameters:
hsai | pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1170 of file stm32wbxx_hal_sai.c.

References __HAL_SAI_ENABLE, __HAL_SAI_ENABLE_IT, SAI_InitTypeDef::CompandingMode, SAI_InitTypeDef::DataSize, __SAI_HandleTypeDef::ErrorCode, HAL_SAI_ERROR_NONE, HAL_SAI_STATE_BUSY_TX, HAL_SAI_STATE_READY, __SAI_HandleTypeDef::Init, __SAI_HandleTypeDef::Instance, __SAI_HandleTypeDef::InterruptServiceRoutine, __SAI_HandleTypeDef::pBuffPtr, SAI_DATASIZE_16, SAI_DATASIZE_8, SAI_FillFifo(), SAI_InterruptFlag(), SAI_MODE_IT, SAI_NOCOMPANDING, SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), SAI_Transmit_IT8Bit(), __SAI_HandleTypeDef::State, __SAI_HandleTypeDef::XferCount, and __SAI_HandleTypeDef::XferSize.

void HAL_SAI_TxCpltCallback ( SAI_HandleTypeDef * hsai )

Tx Transfer completed callback.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 1955 of file stm32wbxx_hal_sai.c.

Referenced by HAL_SAI_Init(), HAL_SAI_UnRegisterCallback(), SAI_DMATxCplt(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

void HAL_SAI_TxHalfCpltCallback ( SAI_HandleTypeDef * hsai )

Tx Transfer Half completed callback.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
None

Definition at line 1971 of file stm32wbxx_hal_sai.c.

Referenced by HAL_SAI_Init(), HAL_SAI_UnRegisterCallback(), and SAI_DMATxHalfCplt().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
SAI Exported Functions

Peripheral State functions. More...

Functions

HAL_SAI_StateTypeDef | HAL_SAI_GetState (SAI_HandleTypeDef *hsai)
Return the SAI handle state.
uint32_t | HAL_SAI_GetError (SAI_HandleTypeDef *hsai)
Return the SAI error code.

Detailed Description

Peripheral State functions.

  ===============================================================================
                ##### Peripheral State and Errors functions #####
  ===============================================================================
  [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

uint32_t HAL_SAI_GetError ( SAI_HandleTypeDef * hsai )

Return the SAI error code.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for the specified SAI Block.
Return values:
SAI Error Code

Definition at line 2065 of file stm32wbxx_hal_sai.c.

References __SAI_HandleTypeDef::ErrorCode.

HAL_SAI_StateTypeDef HAL_SAI_GetState ( SAI_HandleTypeDef * hsai )

Return the SAI handle state.

Parameters:
hsai pointer to a SAI_HandleTypeDef structure that contains the configuration information for SAI module.
Return values:
HAL state

Definition at line 2054 of file stm32wbxx_hal_sai.c.

References __SAI_HandleTypeDef::State.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAI_PdmInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SAI_PdmInitTypeDef Struct Reference
SAI PDM Structure definition

#include <stm32wbxx_hal_sai.h>

Data Fields

FunctionalState | Activation
uint32_t | MicPairsNbr
uint32_t | ClockEnable

Detailed Description

Definition at line 67 of file stm32wbxx_hal_sai.h.

Field Documentation

FunctionalState SAI_PdmInitTypeDef::Activation

Enable/disable PDM interface

Definition at line 69 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_PdmInitTypeDef::ClockEnable

Specifies which clock must be enabled. This parameter can be a values combination of SAI PDM Clock Enable

Definition at line 72 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_PdmInitTypeDef::MicPairsNbr

Specifies the number of microphone pairs used. This parameter must be a number between Min_Data = 1 and Max_Data = 3.

Definition at line 70 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_sai.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SAI_InitTypeDef Struct Reference
SAI Init Structure definition

#include <stm32wbxx_hal_sai.h>

Data Fields

uint32_t | AudioMode
uint32_t | Synchro
uint32_t | SynchroExt
uint32_t | MckOutput
uint32_t | OutputDrive
uint32_t | NoDivider
uint32_t | FIFOThreshold
uint32_t | AudioFrequency
uint32_t | Mckdiv
uint32_t | MckOverSampling
uint32_t | MonoStereoMode
uint32_t | CompandingMode
uint32_t | TriState
SAI_PdmInitTypeDef PdmInit
uint32_t | Protocol
uint32_t | DataSize
uint32_t | FirstBit
uint32_t | ClockStrobing

Detailed Description

Definition at line 83 of file stm32wbxx_hal_sai.h.

Field Documentation

uint32_t SAI_InitTypeDef::AudioFrequency

Specifies the audio frequency sampling. This parameter can be a value of SAI Audio Frequency

Definition at line 115 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::AudioMode

Specifies the SAI Block audio Mode. This parameter can be a value of SAI Block Mode

Definition at line 85 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), SAI_InitPCM(), and SAI_InterruptFlag().

uint32_t SAI_InitTypeDef::ClockStrobing

Specifies the SAI Block clock strobing edge sensitivity. This parameter can be a value of SAI Block Clock Strobing

Definition at line 149 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_InitTypeDef::CompandingMode

Specifies the companding mode type. This parameter can be a value of SAI Block Companding Mode

Definition at line 129 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init(), HAL_SAI_Receive(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_IT(), and SAI_FillFifo().

uint32_t SAI_InitTypeDef::DataSize

Specifies the SAI Block data size. This parameter can be a value of SAI Block Data Size

Definition at line 143 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init(), HAL_SAI_Receive(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_IT(), SAI_FillFifo(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_InitTypeDef::FIFOThreshold

Specifies SAI Block FIFO threshold. This parameter can be a value of SAI Block Fifo Threshold

Definition at line 112 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::FirstBit

Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of SAI Block MSB LSB transmission

Definition at line 146 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_InitTypeDef::Mckdiv

Specifies the master clock divider. This parameter must be a number between Min_Data = 0 and Max_Data = 63.

Note:
This parameter is used only if AudioFrequency is set to SAI_AUDIO_FREQUENCY_MCKDIV otherwise it is internally computed.

Definition at line 118 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::MckOutput

Specifies whether master clock output will be generated or not. This parameter can be a value of SAI Block Master Clock Output

Definition at line 97 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::MckOverSampling

Specifies the master clock oversampling. This parameter can be a value of SAI Block Master Clock OverSampling

Definition at line 123 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::MonoStereoMode

Specifies if the mono or stereo mode is selected. This parameter can be a value of SAI Mono Stereo Mode

Definition at line 126 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::NoDivider

Specifies whether master clock will be divided or not. This parameter can be a value of SAI Block NoDivider

Note:
If bit NODIV in the SAI_xCR1 register is cleared, the frame length should be aligned to a number equal to a power of 2, from 8 to 256. If bit NODIV in the SAI_xCR1 register is set, the frame length can take any of the values from 8 to 256.

Definition at line 105 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::OutputDrive

Specifies when SAI Block outputs are driven. This parameter can be a value of SAI Block Output Drive

Note:
This value has to be set before enabling the audio block but after the audio block configuration.

Definition at line 100 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

SAI_PdmInitTypeDef SAI_InitTypeDef::PdmInit

Specifies the PDM configuration.

Definition at line 135 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::Protocol

Specifies the SAI Block protocol. This parameter can be a value of SAI Block Protocol

Definition at line 140 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), SAI_InitPCM(), and SAI_InterruptFlag().

uint32_t SAI_InitTypeDef::Synchro

Specifies SAI Block synchronization This parameter can be a value of SAI Block Synchronization

Definition at line 88 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::SynchroExt

Specifies SAI external output synchronization, this setup is common for BlockA and BlockB This parameter can be a value of SAI External synchronisation

Note:
If both audio blocks of same SAI are used, this parameter has to be set to the same value for each audio block

Definition at line 91 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

uint32_t SAI_InitTypeDef::TriState

Specifies the companding mode type. This parameter can be a value of SAI TRIState Management

Definition at line 132 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_sai.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAI_FrameInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SAI_FrameInitTypeDef Struct Reference
SAI Frame Structure definition

#include <stm32wbxx_hal_sai.h>

Data Fields

uint32_t | FrameLength
uint32_t | ActiveFrameLength
uint32_t | FSDefinition
uint32_t | FSPolarity
uint32_t | FSOffset

Detailed Description

Definition at line 161 of file stm32wbxx_hal_sai.h.

Field Documentation

uint32_t SAI_FrameInitTypeDef::ActiveFrameLength

Specifies the Frame synchronization active level length. This Parameter specifies the length in number of bit clock (SCK + 1) of the active level of FS signal in audio frame. This parameter must be a number between Min_Data = 1 and Max_Data = 128

Definition at line 170 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_FrameInitTypeDef::FrameLength

Specifies the Frame length, the number of SCK clocks for each audio frame. This parameter must be a number between Min_Data = 8 and Max_Data = 256.

Note:
If master clock MCLK_x pin is declared as an output, the frame length should be aligned to a number equal to power of 2 in order to keep in an audio frame, an integer number of MCLK pulses by bit Clock.

Definition at line 164 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_FrameInitTypeDef::FSDefinition

Specifies the Frame synchronization definition. This parameter can be a value of SAI Block FS Definition

Definition at line 175 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_FrameInitTypeDef::FSOffset

Specifies the Frame synchronization Offset. This parameter can be a value of SAI Block FS Offset

Definition at line 181 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_FrameInitTypeDef::FSPolarity

Specifies the Frame synchronization Polarity. This parameter can be a value of SAI Block FS Polarity

Definition at line 178 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_sai.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAI_SlotInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SAI_SlotInitTypeDef Struct Reference
SAI Slot Structure definition

#include <stm32wbxx_hal_sai.h>

Data Fields

uint32_t | FirstBitOffset
uint32_t | SlotSize
uint32_t | SlotNumber
uint32_t | SlotActive

Detailed Description

Definition at line 195 of file stm32wbxx_hal_sai.h.

Field Documentation

uint32_t SAI_SlotInitTypeDef::FirstBitOffset

Specifies the position of first data transfer bit in the slot. This parameter must be a number between Min_Data = 0 and Max_Data = 24

Definition at line 197 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_SlotInitTypeDef::SlotActive

Specifies the slots in audio frame that will be activated. This parameter can be a value of SAI Block Slot Active

Definition at line 206 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_SlotInitTypeDef::SlotNumber

Specifies the number of slot in the audio frame. This parameter must be a number between Min_Data = 1 and Max_Data = 16

Definition at line 203 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

uint32_t SAI_SlotInitTypeDef::SlotSize

Specifies the Slot Size. This parameter can be a value of SAI Block Slot Size

Definition at line 200 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_sai.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAI Handle Structure definition

Data Structures | Typedefs
SAI Handle Structure definition
SAI Exported Types

SAI handle Structure definition. More...

Data Structures

struct | __SAI_HandleTypeDef

Typedefs

typedef struct __SAI_HandleTypeDef | SAI_HandleTypeDef

Detailed Description

SAI handle Structure definition.

Typedef Documentation

typedef struct __SAI_HandleTypeDef SAI_HandleTypeDef
Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: __SAI_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__SAI_HandleTypeDef Struct Reference
SAI Handle Structure definition

#include <stm32wbxx_hal_sai.h>

Data Fields

SAI_Block_TypeDef * | Instance
SAI_InitTypeDef Init
SAI_FrameInitTypeDef FrameInit
SAI_SlotInitTypeDef SlotInit
uint8_t * | pBuffPtr
uint16_t | XferSize
uint16_t | XferCount
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
SAIcallback mutecallback
void(* | InterruptServiceRoutine )(struct __SAI_HandleTypeDef *hsai)
HAL_LockTypeDef | Lock
__IO HAL_SAI_StateTypeDef | State
__IO uint32_t | ErrorCode
void(* | RxCpltCallback )(struct __SAI_HandleTypeDef *hsai)
void(* | RxHalfCpltCallback )(struct __SAI_HandleTypeDef *hsai)
void(* | TxCpltCallback )(struct __SAI_HandleTypeDef *hsai)
void(* | TxHalfCpltCallback )(struct __SAI_HandleTypeDef *hsai)
void(* | ErrorCallback )(struct __SAI_HandleTypeDef *hsai)
void(* | MspInitCallback )(struct __SAI_HandleTypeDef *hsai)
void(* | MspDeInitCallback )(struct __SAI_HandleTypeDef *hsai)

Detailed Description

Definition at line 217 of file stm32wbxx_hal_sai.h.

Field Documentation

void(* __SAI_HandleTypeDef::ErrorCallback)(struct __SAI_HandleTypeDef *hsai)

SAI error callback

Definition at line 252 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init(), HAL_SAI_IRQHandler(), HAL_SAI_RegisterCallback(), HAL_SAI_UnRegisterCallback(), SAI_DMAAbort(), and SAI_DMAError().

__IO uint32_t __SAI_HandleTypeDef::ErrorCode

SAI Error code

Definition at line 245 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_DeInit(), HAL_SAI_GetError(), HAL_SAI_Init(), HAL_SAI_IRQHandler(), HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_RegisterCallback(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), HAL_SAI_Transmit_IT(), HAL_SAI_UnRegisterCallback(), SAI_Disable(), SAI_DMAAbort(), and SAI_DMAError().

SAI_FrameInitTypeDef __SAI_HandleTypeDef::FrameInit

SAI Frame configuration parameters

Definition at line 223 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

DMA_HandleTypeDef* __SAI_HandleTypeDef::hdmarx

SAI Rx DMA handle parameters

Definition at line 235 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Abort(), HAL_SAI_DMAStop(), HAL_SAI_IRQHandler(), and HAL_SAI_Receive_DMA().

DMA_HandleTypeDef* __SAI_HandleTypeDef::hdmatx

SAI Tx DMA handle parameters

Definition at line 233 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Abort(), HAL_SAI_DMAStop(), HAL_SAI_IRQHandler(), and HAL_SAI_Transmit_DMA().

SAI_InitTypeDef __SAI_HandleTypeDef::Init

SAI communication parameters

Definition at line 221 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init(), HAL_SAI_Receive(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_IT(), SAI_FillFifo(), SAI_InitI2S(), SAI_InitPCM(), and SAI_InterruptFlag().

SAI_Block_TypeDef* __SAI_HandleTypeDef::Instance

SAI Blockx registers base address

Definition at line 219 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Abort(), HAL_SAI_DeInit(), HAL_SAI_DisableTxMuteMode(), HAL_SAI_DMAPause(), HAL_SAI_DMAResume(), HAL_SAI_DMAStop(), HAL_SAI_EnableRxMuteMode(), HAL_SAI_EnableTxMuteMode(), HAL_SAI_Init(), HAL_SAI_IRQHandler(), HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), HAL_SAI_Transmit_IT(), HAL_SAIEx_ConfigPdmMicDelay(), SAI_Disable(), SAI_DMAAbort(), SAI_DMAError(), SAI_DMARxCplt(), SAI_DMATxCplt(), SAI_FillFifo(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

void(* __SAI_HandleTypeDef::InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai)

Definition at line 239 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), HAL_SAI_Receive_IT(), and HAL_SAI_Transmit_IT().

HAL_LockTypeDef __SAI_HandleTypeDef::Lock

SAI locking object

Definition at line 241 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

void(* __SAI_HandleTypeDef::MspDeInitCallback)(struct __SAI_HandleTypeDef *hsai)

SAI MSP de-init callback

Definition at line 254 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_DeInit(), HAL_SAI_RegisterCallback(), and HAL_SAI_UnRegisterCallback().

void(* __SAI_HandleTypeDef::MspInitCallback)(struct __SAI_HandleTypeDef *hsai)

SAI MSP init callback

Definition at line 253 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init(), HAL_SAI_RegisterCallback(), and HAL_SAI_UnRegisterCallback().

SAIcallback __SAI_HandleTypeDef::mutecallback

SAI mute callback

Definition at line 237 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_DisableRxMuteMode(), HAL_SAI_EnableRxMuteMode(), and HAL_SAI_IRQHandler().

uint8_t* __SAI_HandleTypeDef::pBuffPtr

Pointer to SAI transfer Buffer

Definition at line 227 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), HAL_SAI_Transmit_IT(), SAI_FillFifo(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

void(* __SAI_HandleTypeDef::RxCpltCallback)(struct __SAI_HandleTypeDef *hsai)

SAI receive complete callback

Definition at line 248 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init(), HAL_SAI_RegisterCallback(), HAL_SAI_UnRegisterCallback(), SAI_DMARxCplt(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), and SAI_Receive_IT8Bit().

void(* __SAI_HandleTypeDef::RxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai)

SAI receive half complete callback

Definition at line 249 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init(), HAL_SAI_RegisterCallback(), HAL_SAI_UnRegisterCallback(), and SAI_DMARxHalfCplt().

SAI_SlotInitTypeDef __SAI_HandleTypeDef::SlotInit

SAI Slot configuration parameters

Definition at line 225 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

__IO HAL_SAI_StateTypeDef __SAI_HandleTypeDef::State

SAI communication state

Definition at line 243 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Abort(), HAL_SAI_DeInit(), HAL_SAI_DisableRxMuteMode(), HAL_SAI_DisableTxMuteMode(), HAL_SAI_DMAStop(), HAL_SAI_EnableRxMuteMode(), HAL_SAI_EnableTxMuteMode(), HAL_SAI_GetState(), HAL_SAI_Init(), HAL_SAI_IRQHandler(), HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_RegisterCallback(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), HAL_SAI_Transmit_IT(), HAL_SAI_UnRegisterCallback(), HAL_SAIEx_ConfigPdmMicDelay(), SAI_DMAAbort(), SAI_DMAError(), SAI_DMARxCplt(), SAI_DMATxCplt(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

void(* __SAI_HandleTypeDef::TxCpltCallback)(struct __SAI_HandleTypeDef *hsai)

SAI transmit complete callback

Definition at line 250 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init(), HAL_SAI_RegisterCallback(), HAL_SAI_UnRegisterCallback(), SAI_DMATxCplt(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

void(* __SAI_HandleTypeDef::TxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai)

SAI transmit half complete callback

Definition at line 251 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init(), HAL_SAI_RegisterCallback(), HAL_SAI_UnRegisterCallback(), and SAI_DMATxHalfCplt().

uint16_t __SAI_HandleTypeDef::XferCount

SAI transfer counter

Definition at line 231 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), HAL_SAI_Transmit_IT(), SAI_DMAAbort(), SAI_DMAError(), SAI_DMARxCplt(), SAI_DMATxCplt(), SAI_FillFifo(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

uint16_t __SAI_HandleTypeDef::XferSize

SAI transfer size

Definition at line 229 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), and HAL_SAI_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_sai.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAI Exported Types

Modules | Typedefs | Enumerations
SAI Exported Types
SAI

Modules

SAI PDM Structure definition

SAI PDM Init structure definition.

SAI Init Structure definition

SAI Init Structure definition.

SAI Frame Structure definition

SAI Frame Init structure definition.

SAI Slot Structure definition

SAI Block Slot Init Structure definition.

SAI Handle Structure definition

SAI handle Structure definition.

Typedefs

typedef void(* | SAIcallback )(void)
SAI Callback prototype.
typedef void(* | pSAI_CallbackTypeDef )(SAI_HandleTypeDef *hsai)
SAI callback pointer definition.

Enumerations

enum HAL_SAI_StateTypeDef {
HAL_SAI_STATE_RESET = 0x00U, HAL_SAI_STATE_READY = 0x01U, HAL_SAI_STATE_BUSY = 0x02U, HAL_SAI_STATE_BUSY_TX = 0x12U,
HAL_SAI_STATE_BUSY_RX = 0x22U
}
HAL State structures definition. More...
enum HAL_SAI_CallbackIDTypeDef {
HAL_SAI_RX_COMPLETE_CB_ID = 0x00U, HAL_SAI_RX_HALFCOMPLETE_CB_ID = 0x01U, HAL_SAI_TX_COMPLETE_CB_ID = 0x02U, HAL_SAI_TX_HALFCOMPLETE_CB_ID = 0x03U,
HAL_SAI_ERROR_CB_ID = 0x04U, HAL_SAI_MSPINIT_CB_ID = 0x05U, HAL_SAI_MSPDEINIT_CB_ID = 0x06U
}
SAI callback ID enumeration definition. More...

Typedef Documentation

typedef void(* pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai)

SAI callback pointer definition.

Definition at line 279 of file stm32wbxx_hal_sai.h.

typedef void(* SAIcallback)(void)

SAI Callback prototype.

Definition at line 61 of file stm32wbxx_hal_sai.h.

Enumeration Type Documentation

enum HAL_SAI_CallbackIDTypeDef

SAI callback ID enumeration definition.

Enumerator:
HAL_SAI_RX_COMPLETE_CB_ID

SAI receive complete callback ID

HAL_SAI_RX_HALFCOMPLETE_CB_ID

SAI receive half complete callback ID

HAL_SAI_TX_COMPLETE_CB_ID

SAI transmit complete callback ID

HAL_SAI_TX_HALFCOMPLETE_CB_ID

SAI transmit half complete callback ID

HAL_SAI_ERROR_CB_ID

SAI error callback ID

HAL_SAI_MSPINIT_CB_ID

SAI MSP init callback ID

HAL_SAI_MSPDEINIT_CB_ID

SAI MSP de-init callback ID

Definition at line 265 of file stm32wbxx_hal_sai.h.

enum HAL_SAI_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_SAI_STATE_RESET

SAI not yet initialized or disabled

HAL_SAI_STATE_READY

SAI initialized and ready for use

HAL_SAI_STATE_BUSY

SAI internal process is ongoing

HAL_SAI_STATE_BUSY_TX

Data transmission process is ongoing

HAL_SAI_STATE_BUSY_RX

Data reception process is ongoing

Definition at line 49 of file stm32wbxx_hal_sai.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAI Error Code

Defines
SAI Error Code
SAI Exported Constants

Defines

#define | HAL_SAI_ERROR_NONE 0x00000000U
#define | HAL_SAI_ERROR_OVR 0x00000001U
#define | HAL_SAI_ERROR_UDR 0x00000002U
#define | HAL_SAI_ERROR_AFSDET 0x00000004U
#define | HAL_SAI_ERROR_LFSDET 0x00000008U
#define | HAL_SAI_ERROR_CNREADY 0x00000010U
#define | HAL_SAI_ERROR_WCKCFG 0x00000020U
#define | HAL_SAI_ERROR_TIMEOUT 0x00000040U
#define | HAL_SAI_ERROR_DMA 0x00000080U
#define | HAL_SAI_ERROR_INVALID_CALLBACK 0x00000100U

Define Documentation

#define HAL_SAI_ERROR_AFSDET 0x00000004U

Anticipated Frame synchronisation detection

Definition at line 297 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define HAL_SAI_ERROR_CNREADY 0x00000010U

codec not ready

Definition at line 299 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define HAL_SAI_ERROR_DMA 0x00000080U

DMA error

Definition at line 302 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_DMAError().

#define HAL_SAI_ERROR_INVALID_CALLBACK 0x00000100U

Invalid callback error

Definition at line 304 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_RegisterCallback(), and HAL_SAI_UnRegisterCallback().

#define HAL_SAI_ERROR_LFSDET 0x00000008U

Late Frame synchronisation detection

Definition at line 298 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define HAL_SAI_ERROR_NONE 0x00000000U

No error

Definition at line 294 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_DeInit(), HAL_SAI_Init(), HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), and HAL_SAI_Transmit_IT().

#define HAL_SAI_ERROR_OVR 0x00000001U

Overrun Error

Definition at line 295 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define HAL_SAI_ERROR_TIMEOUT 0x00000040U

Timeout error

Definition at line 301 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Receive(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), and SAI_Disable().

#define HAL_SAI_ERROR_UDR 0x00000002U

Underrun error

Definition at line 296 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define HAL_SAI_ERROR_WCKCFG 0x00000020U

Wrong clock configuration

Definition at line 300 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_DMAAbort().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAI External synchronisation

Defines
SAI External synchronisation
SAI Exported Constants

Defines

#define | SAI_SYNCEXT_DISABLE 0U
#define | SAI_SYNCEXT_OUTBLOCKA_ENABLE 1U
#define | SAI_SYNCEXT_OUTBLOCKB_ENABLE 2U

Define Documentation

#define SAI_SYNCEXT_DISABLE 0U

Definition at line 313 of file stm32wbxx_hal_sai.h.

#define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1U

Definition at line 314 of file stm32wbxx_hal_sai.h.

#define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2U

Definition at line 315 of file stm32wbxx_hal_sai.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAI Block Master Clock Output

Defines
SAI Block Master Clock Output
SAI Exported Constants

Defines

#define | SAI_MCK_OUTPUT_DISABLE 0x00000000U
#define | SAI_MCK_OUTPUT_ENABLE SAI_xCR1_MCKEN

Define Documentation

#define SAI_MCK_OUTPUT_DISABLE 0x00000000U

Definition at line 323 of file stm32wbxx_hal_sai.h.

#define SAI_MCK_OUTPUT_ENABLE SAI_xCR1_MCKEN

Definition at line 324 of file stm32wbxx_hal_sai.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAI Supported protocol

Defines
SAI Supported protocol
SAI Exported Constants

Defines

#define | SAI_I2S_STANDARD 0U
#define | SAI_I2S_MSBJUSTIFIED 1U
#define | SAI_I2S_LSBJUSTIFIED 2U
#define | SAI_PCM_LONG 3U
#define | SAI_PCM_SHORT 4U

Define Documentation

#define SAI_I2S_LSBJUSTIFIED 2U

Definition at line 334 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol(), and SAI_InitI2S().

#define SAI_I2S_MSBJUSTIFIED 1U

Definition at line 333 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol().

#define SAI_I2S_STANDARD 0U

Definition at line 332 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol(), and SAI_InitI2S().

#define SAI_PCM_LONG 3U

Definition at line 335 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol().

#define SAI_PCM_SHORT 4U

Definition at line 336 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol(), and SAI_InitPCM().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAI protocol data size

Defines
SAI protocol data size
SAI Exported Constants

Defines

#define | SAI_PROTOCOL_DATASIZE_16BIT 0U
#define | SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1U
#define | SAI_PROTOCOL_DATASIZE_24BIT 2U
#define | SAI_PROTOCOL_DATASIZE_32BIT 3U

Define Documentation

#define SAI_PROTOCOL_DATASIZE_16BIT 0U

Definition at line 344 of file stm32wbxx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1U

Definition at line 345 of file stm32wbxx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_PROTOCOL_DATASIZE_24BIT 2U

Definition at line 346 of file stm32wbxx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_PROTOCOL_DATASIZE_32BIT 3U

Definition at line 347 of file stm32wbxx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAI Audio Frequency

Defines
SAI Audio Frequency
SAI Exported Constants

Defines

#define | SAI_AUDIO_FREQUENCY_192K 192000U
#define | SAI_AUDIO_FREQUENCY_96K 96000U
#define | SAI_AUDIO_FREQUENCY_48K 48000U
#define | SAI_AUDIO_FREQUENCY_44K 44100U
#define | SAI_AUDIO_FREQUENCY_32K 32000U
#define | SAI_AUDIO_FREQUENCY_22K 22050U
#define | SAI_AUDIO_FREQUENCY_16K 16000U
#define | SAI_AUDIO_FREQUENCY_11K 11025U
#define | SAI_AUDIO_FREQUENCY_8K 8000U
#define | SAI_AUDIO_FREQUENCY_MCKDIV 0U

Define Documentation

#define SAI_AUDIO_FREQUENCY_11K 11025U

Definition at line 362 of file stm32wbxx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_16K 16000U

Definition at line 361 of file stm32wbxx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_192K 192000U

Definition at line 355 of file stm32wbxx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_22K 22050U

Definition at line 360 of file stm32wbxx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_32K 32000U

Definition at line 359 of file stm32wbxx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_44K 44100U

Definition at line 358 of file stm32wbxx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_48K 48000U

Definition at line 357 of file stm32wbxx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_8K 8000U

Definition at line 363 of file stm32wbxx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_96K 96000U

Definition at line 356 of file stm32wbxx_hal_sai.h.

#define SAI_AUDIO_FREQUENCY_MCKDIV 0U

Definition at line 364 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAI Block Master Clock OverSampling

Defines
SAI Block Master Clock OverSampling
SAI Exported Constants

Defines

#define | SAI_MCK_OVERSAMPLING_DISABLE 0x00000000U
#define | SAI_MCK_OVERSAMPLING_ENABLE SAI_xCR1_OSR

Define Documentation

#define SAI_MCK_OVERSAMPLING_DISABLE 0x00000000U

Definition at line 372 of file stm32wbxx_hal_sai.h.

#define SAI_MCK_OVERSAMPLING_ENABLE SAI_xCR1_OSR

Definition at line 373 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAI PDM Clock Enable

Defines
SAI PDM Clock Enable
SAI Exported Constants

Defines

#define | SAI_PDM_CLOCK1_ENABLE SAI_PDMCR_CKEN1
#define | SAI_PDM_CLOCK2_ENABLE SAI_PDMCR_CKEN2

Define Documentation

#define SAI_PDM_CLOCK1_ENABLE SAI_PDMCR_CKEN1

Definition at line 381 of file stm32wbxx_hal_sai.h.

#define SAI_PDM_CLOCK2_ENABLE SAI_PDMCR_CKEN2

Definition at line 382 of file stm32wbxx_hal_sai.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAI Block Mode

Defines
SAI Block Mode
SAI Exported Constants

Defines

#define | SAI_MODEMASTER_TX 0x00000000U
#define | SAI_MODEMASTER_RX SAI_xCR1_MODE_0
#define | SAI_MODESLAVE_TX SAI_xCR1_MODE_1
#define | SAI_MODESLAVE_RX (SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0)

Define Documentation

#define SAI_MODEMASTER_RX SAI_xCR1_MODE_0

Definition at line 391 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init(), and SAI_InterruptFlag().

#define SAI_MODEMASTER_TX 0x00000000U

Definition at line 390 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

#define SAI_MODESLAVE_RX (SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0)

Definition at line 393 of file stm32wbxx_hal_sai.h.

Referenced by SAI_InterruptFlag().

#define SAI_MODESLAVE_TX SAI_xCR1_MODE_1

Definition at line 392 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), SAI_InitPCM(), and SAI_InterruptFlag().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAI Block Protocol

Defines
SAI Block Protocol
SAI Exported Constants

Defines

#define | SAI_FREE_PROTOCOL 0x00000000U
#define | SAI_SPDIF_PROTOCOL SAI_xCR1_PRTCFG_0
#define | SAI_AC97_PROTOCOL SAI_xCR1_PRTCFG_1

Define Documentation

#define SAI_AC97_PROTOCOL SAI_xCR1_PRTCFG_1

Definition at line 404 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init(), and SAI_InterruptFlag().

#define SAI_FREE_PROTOCOL 0x00000000U

Definition at line 402 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

#define SAI_SPDIF_PROTOCOL SAI_xCR1_PRTCFG_0

Definition at line 403 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAI Block Data Size

Defines
SAI Block Data Size
SAI Exported Constants

Defines

#define | SAI_DATASIZE_8 SAI_xCR1_DS_1
#define | SAI_DATASIZE_10 (SAI_xCR1_DS_1 | SAI_xCR1_DS_0)
#define | SAI_DATASIZE_16 SAI_xCR1_DS_2
#define | SAI_DATASIZE_20 (SAI_xCR1_DS_2 | SAI_xCR1_DS_0)
#define | SAI_DATASIZE_24 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1)
#define | SAI_DATASIZE_32 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0)

Define Documentation

#define SAI_DATASIZE_10 (SAI_xCR1_DS_1 | SAI_xCR1_DS_0)

Definition at line 413 of file stm32wbxx_hal_sai.h.

#define SAI_DATASIZE_16 SAI_xCR1_DS_2

Definition at line 414 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Receive(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_IT(), SAI_FillFifo(), SAI_InitI2S(), and SAI_InitPCM().

#define SAI_DATASIZE_20 (SAI_xCR1_DS_2 | SAI_xCR1_DS_0)

Definition at line 415 of file stm32wbxx_hal_sai.h.

#define SAI_DATASIZE_24 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1)

Definition at line 416 of file stm32wbxx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_DATASIZE_32 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0)

Definition at line 417 of file stm32wbxx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_DATASIZE_8 SAI_xCR1_DS_1

Definition at line 412 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Receive(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_IT(), and SAI_FillFifo().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAI Block MSB LSB transmission

Defines
SAI Block MSB LSB transmission
SAI Exported Constants

Defines

#define | SAI_FIRSTBIT_MSB 0x00000000U
#define | SAI_FIRSTBIT_LSB SAI_xCR1_LSBFIRST

Define Documentation

#define SAI_FIRSTBIT_LSB SAI_xCR1_LSBFIRST

Definition at line 426 of file stm32wbxx_hal_sai.h.

#define SAI_FIRSTBIT_MSB 0x00000000U

Definition at line 425 of file stm32wbxx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAI Block Clock Strobing

Defines
SAI Block Clock Strobing
SAI Exported Constants

Defines

#define | SAI_CLOCKSTROBING_FALLINGEDGE 0U
#define | SAI_CLOCKSTROBING_RISINGEDGE 1U

Define Documentation

#define SAI_CLOCKSTROBING_FALLINGEDGE 0U

Definition at line 434 of file stm32wbxx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_CLOCKSTROBING_RISINGEDGE 1U

Definition at line 435 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init(), SAI_InitI2S(), and SAI_InitPCM().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAI Block Synchronization

Defines
SAI Block Synchronization
SAI Exported Constants

Defines

#define | SAI_ASYNCHRONOUS 0U
#define | SAI_SYNCHRONOUS 1U
#define | SAI_SYNCHRONOUS_EXT_SAI1 2U
#define | SAI_SYNCHRONOUS_EXT_SAI2 3U

Define Documentation

#define SAI_ASYNCHRONOUS 0U

Asynchronous

Definition at line 443 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define SAI_SYNCHRONOUS 1U

Synchronous with other block of same SAI

Definition at line 444 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define SAI_SYNCHRONOUS_EXT_SAI1 2U

Synchronous with other SAI, SAI1

Definition at line 445 of file stm32wbxx_hal_sai.h.

#define SAI_SYNCHRONOUS_EXT_SAI2 3U

Synchronous with other SAI, SAI2

Definition at line 446 of file stm32wbxx_hal_sai.h.

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STM32WB55xx HAL User Manual: SAI Block Output Drive

Defines
SAI Block Output Drive
SAI Exported Constants

Defines

#define | SAI_OUTPUTDRIVE_DISABLE 0x00000000U
#define | SAI_OUTPUTDRIVE_ENABLE SAI_xCR1_OUTDRIV

Define Documentation

#define SAI_OUTPUTDRIVE_DISABLE 0x00000000U

Definition at line 454 of file stm32wbxx_hal_sai.h.

#define SAI_OUTPUTDRIVE_ENABLE SAI_xCR1_OUTDRIV

Definition at line 455 of file stm32wbxx_hal_sai.h.

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STM32WB55xx HAL User Manual: SAI Block NoDivider

Defines
SAI Block NoDivider
SAI Exported Constants

Defines

#define | SAI_MASTERDIVIDER_ENABLE 0x00000000U
#define | SAI_MASTERDIVIDER_DISABLE SAI_xCR1_NODIV

Define Documentation

#define SAI_MASTERDIVIDER_DISABLE SAI_xCR1_NODIV

Definition at line 464 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define SAI_MASTERDIVIDER_ENABLE 0x00000000U

Definition at line 463 of file stm32wbxx_hal_sai.h.

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STM32WB55xx HAL User Manual: SAI Block FS Definition

Defines
SAI Block FS Definition
SAI Exported Constants

Defines

#define | SAI_FS_STARTFRAME 0x00000000U
#define | SAI_FS_CHANNEL_IDENTIFICATION SAI_xFRCR_FSDEF

Define Documentation

#define SAI_FS_CHANNEL_IDENTIFICATION SAI_xFRCR_FSDEF

Definition at line 473 of file stm32wbxx_hal_sai.h.

Referenced by SAI_InitI2S().

#define SAI_FS_STARTFRAME 0x00000000U

Definition at line 472 of file stm32wbxx_hal_sai.h.

Referenced by SAI_InitPCM().

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STM32WB55xx HAL User Manual: SAI Block FS Polarity

Defines
SAI Block FS Polarity
SAI Exported Constants

Defines

#define | SAI_FS_ACTIVE_LOW 0x00000000U
#define | SAI_FS_ACTIVE_HIGH SAI_xFRCR_FSPOL

Define Documentation

#define SAI_FS_ACTIVE_HIGH SAI_xFRCR_FSPOL

Definition at line 482 of file stm32wbxx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_FS_ACTIVE_LOW 0x00000000U

Definition at line 481 of file stm32wbxx_hal_sai.h.

Referenced by SAI_InitI2S().

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STM32WB55xx HAL User Manual: SAI Block FS Offset

Defines
SAI Block FS Offset
SAI Exported Constants

Defines

#define | SAI_FS_FIRSTBIT 0x00000000U
#define | SAI_FS_BEFOREFIRSTBIT SAI_xFRCR_FSOFF

Define Documentation

#define SAI_FS_BEFOREFIRSTBIT SAI_xFRCR_FSOFF

Definition at line 491 of file stm32wbxx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_FS_FIRSTBIT 0x00000000U

Definition at line 490 of file stm32wbxx_hal_sai.h.

Referenced by SAI_InitI2S().

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STM32WB55xx HAL User Manual: SAI Block Slot Size

Defines
SAI Block Slot Size
SAI Exported Constants

Defines

#define | SAI_SLOTSIZE_DATASIZE 0x00000000U
#define | SAI_SLOTSIZE_16B SAI_xSLOTR_SLOTSZ_0
#define | SAI_SLOTSIZE_32B SAI_xSLOTR_SLOTSZ_1

Define Documentation

#define SAI_SLOTSIZE_16B SAI_xSLOTR_SLOTSZ_0

Definition at line 500 of file stm32wbxx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_SLOTSIZE_32B SAI_xSLOTR_SLOTSZ_1

Definition at line 501 of file stm32wbxx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

#define SAI_SLOTSIZE_DATASIZE 0x00000000U

Definition at line 499 of file stm32wbxx_hal_sai.h.

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STM32WB55xx HAL User Manual: SAI Block Slot Active

Defines
SAI Block Slot Active
SAI Exported Constants

Defines

#define | SAI_SLOT_NOTACTIVE 0x00000000U
#define | SAI_SLOTACTIVE_0 0x00000001U
#define | SAI_SLOTACTIVE_1 0x00000002U
#define | SAI_SLOTACTIVE_2 0x00000004U
#define | SAI_SLOTACTIVE_3 0x00000008U
#define | SAI_SLOTACTIVE_4 0x00000010U
#define | SAI_SLOTACTIVE_5 0x00000020U
#define | SAI_SLOTACTIVE_6 0x00000040U
#define | SAI_SLOTACTIVE_7 0x00000080U
#define | SAI_SLOTACTIVE_8 0x00000100U
#define | SAI_SLOTACTIVE_9 0x00000200U
#define | SAI_SLOTACTIVE_10 0x00000400U
#define | SAI_SLOTACTIVE_11 0x00000800U
#define | SAI_SLOTACTIVE_12 0x00001000U
#define | SAI_SLOTACTIVE_13 0x00002000U
#define | SAI_SLOTACTIVE_14 0x00004000U
#define | SAI_SLOTACTIVE_15 0x00008000U
#define | SAI_SLOTACTIVE_ALL 0x0000FFFFU

Define Documentation

#define SAI_SLOT_NOTACTIVE 0x00000000U

Definition at line 509 of file stm32wbxx_hal_sai.h.

#define SAI_SLOTACTIVE_0 0x00000001U

Definition at line 510 of file stm32wbxx_hal_sai.h.

#define SAI_SLOTACTIVE_1 0x00000002U

Definition at line 511 of file stm32wbxx_hal_sai.h.

#define SAI_SLOTACTIVE_10 0x00000400U

Definition at line 520 of file stm32wbxx_hal_sai.h.

#define SAI_SLOTACTIVE_11 0x00000800U

Definition at line 521 of file stm32wbxx_hal_sai.h.

#define SAI_SLOTACTIVE_12 0x00001000U

Definition at line 522 of file stm32wbxx_hal_sai.h.

#define SAI_SLOTACTIVE_13 0x00002000U

Definition at line 523 of file stm32wbxx_hal_sai.h.

#define SAI_SLOTACTIVE_14 0x00004000U

Definition at line 524 of file stm32wbxx_hal_sai.h.

#define SAI_SLOTACTIVE_15 0x00008000U

Definition at line 525 of file stm32wbxx_hal_sai.h.

#define SAI_SLOTACTIVE_2 0x00000004U

Definition at line 512 of file stm32wbxx_hal_sai.h.

#define SAI_SLOTACTIVE_3 0x00000008U

Definition at line 513 of file stm32wbxx_hal_sai.h.

#define SAI_SLOTACTIVE_4 0x00000010U

Definition at line 514 of file stm32wbxx_hal_sai.h.

#define SAI_SLOTACTIVE_5 0x00000020U

Definition at line 515 of file stm32wbxx_hal_sai.h.

#define SAI_SLOTACTIVE_6 0x00000040U

Definition at line 516 of file stm32wbxx_hal_sai.h.

#define SAI_SLOTACTIVE_7 0x00000080U

Definition at line 517 of file stm32wbxx_hal_sai.h.

#define SAI_SLOTACTIVE_8 0x00000100U

Definition at line 518 of file stm32wbxx_hal_sai.h.

#define SAI_SLOTACTIVE_9 0x00000200U

Definition at line 519 of file stm32wbxx_hal_sai.h.

#define SAI_SLOTACTIVE_ALL 0x0000FFFFU

Definition at line 526 of file stm32wbxx_hal_sai.h.

Referenced by SAI_InitI2S(), and SAI_InitPCM().

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STM32WB55xx HAL User Manual: SAI Mono Stereo Mode

Defines
SAI Mono Stereo Mode
SAI Exported Constants

Defines

#define | SAI_STEREOMODE 0x00000000U
#define | SAI_MONOMODE SAI_xCR1_MONO

Define Documentation

#define SAI_MONOMODE SAI_xCR1_MONO

Definition at line 535 of file stm32wbxx_hal_sai.h.

#define SAI_STEREOMODE 0x00000000U

Definition at line 534 of file stm32wbxx_hal_sai.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAI TRIState Management

Defines
SAI TRIState Management
SAI Exported Constants

Defines

#define | SAI_OUTPUT_NOTRELEASED 0x00000000U
#define | SAI_OUTPUT_RELEASED SAI_xCR2_TRIS

Define Documentation

#define SAI_OUTPUT_NOTRELEASED 0x00000000U

Definition at line 543 of file stm32wbxx_hal_sai.h.

#define SAI_OUTPUT_RELEASED SAI_xCR2_TRIS

Definition at line 544 of file stm32wbxx_hal_sai.h.

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STM32WB55xx HAL User Manual: SAI Block Fifo Threshold

Defines
SAI Block Fifo Threshold
SAI Exported Constants

Defines

#define | SAI_FIFOTHRESHOLD_EMPTY 0x00000000U
#define | SAI_FIFOTHRESHOLD_1QF SAI_xCR2_FTH_0
#define | SAI_FIFOTHRESHOLD_HF SAI_xCR2_FTH_1
#define | SAI_FIFOTHRESHOLD_3QF (SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0)
#define | SAI_FIFOTHRESHOLD_FULL SAI_xCR2_FTH_2

Define Documentation

#define SAI_FIFOTHRESHOLD_1QF SAI_xCR2_FTH_0

Definition at line 553 of file stm32wbxx_hal_sai.h.

#define SAI_FIFOTHRESHOLD_3QF (SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0)

Definition at line 555 of file stm32wbxx_hal_sai.h.

#define SAI_FIFOTHRESHOLD_EMPTY 0x00000000U

Definition at line 552 of file stm32wbxx_hal_sai.h.

#define SAI_FIFOTHRESHOLD_FULL SAI_xCR2_FTH_2

Definition at line 556 of file stm32wbxx_hal_sai.h.

#define SAI_FIFOTHRESHOLD_HF SAI_xCR2_FTH_1

Definition at line 554 of file stm32wbxx_hal_sai.h.

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STM32WB55xx HAL User Manual: SAI Block Companding Mode

Defines
SAI Block Companding Mode
SAI Exported Constants

Defines

#define | SAI_NOCOMPANDING 0x00000000U
#define | SAI_ULAW_1CPL_COMPANDING SAI_xCR2_COMP_1
#define | SAI_ALAW_1CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0)
#define | SAI_ULAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_CPL)
#define | SAI_ALAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL)

Define Documentation

#define SAI_ALAW_1CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0)

Definition at line 566 of file stm32wbxx_hal_sai.h.

#define SAI_ALAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL)

Definition at line 568 of file stm32wbxx_hal_sai.h.

#define SAI_NOCOMPANDING 0x00000000U

Definition at line 564 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Receive(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_IT(), and SAI_FillFifo().

#define SAI_ULAW_1CPL_COMPANDING SAI_xCR2_COMP_1

Definition at line 565 of file stm32wbxx_hal_sai.h.

#define SAI_ULAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_CPL)

Definition at line 567 of file stm32wbxx_hal_sai.h.

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STM32WB55xx HAL User Manual: SAI Block Mute Value

Defines
SAI Block Mute Value
SAI Exported Constants

Defines

#define | SAI_ZERO_VALUE 0x00000000U
#define | SAI_LAST_SENT_VALUE SAI_xCR2_MUTEVAL

Define Documentation

#define SAI_LAST_SENT_VALUE SAI_xCR2_MUTEVAL

Definition at line 577 of file stm32wbxx_hal_sai.h.

#define SAI_ZERO_VALUE 0x00000000U

Definition at line 576 of file stm32wbxx_hal_sai.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAI Block Interrupts Definition

Defines
SAI Block Interrupts Definition
SAI Exported Constants

Defines

#define | SAI_IT_OVRUDR SAI_xIMR_OVRUDRIE
#define | SAI_IT_MUTEDET SAI_xIMR_MUTEDETIE
#define | SAI_IT_WCKCFG SAI_xIMR_WCKCFGIE
#define | SAI_IT_FREQ SAI_xIMR_FREQIE
#define | SAI_IT_CNRDY SAI_xIMR_CNRDYIE
#define | SAI_IT_AFSDET SAI_xIMR_AFSDETIE
#define | SAI_IT_LFSDET SAI_xIMR_LFSDETIE

Define Documentation

#define SAI_IT_AFSDET SAI_xIMR_AFSDETIE

Definition at line 590 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_InterruptFlag().

#define SAI_IT_CNRDY SAI_xIMR_CNRDYIE

Definition at line 589 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_InterruptFlag().

#define SAI_IT_FREQ SAI_xIMR_FREQIE

Definition at line 588 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_InterruptFlag().

#define SAI_IT_LFSDET SAI_xIMR_LFSDETIE

Definition at line 591 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_InterruptFlag().

#define SAI_IT_MUTEDET SAI_xIMR_MUTEDETIE

Definition at line 586 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_DisableRxMuteMode(), HAL_SAI_EnableRxMuteMode(), and HAL_SAI_IRQHandler().

#define SAI_IT_OVRUDR SAI_xIMR_OVRUDRIE

Definition at line 585 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_InterruptFlag().

#define SAI_IT_WCKCFG SAI_xIMR_WCKCFGIE

Definition at line 587 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), and SAI_InterruptFlag().

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STM32WB55xx HAL User Manual: SAI Block Flags Definition

Defines
SAI Block Flags Definition
SAI Exported Constants

Defines

#define | SAI_FLAG_OVRUDR SAI_xSR_OVRUDR
#define | SAI_FLAG_MUTEDET SAI_xSR_MUTEDET
#define | SAI_FLAG_WCKCFG SAI_xSR_WCKCFG
#define | SAI_FLAG_FREQ SAI_xSR_FREQ
#define | SAI_FLAG_CNRDY SAI_xSR_CNRDY
#define | SAI_FLAG_AFSDET SAI_xSR_AFSDET
#define | SAI_FLAG_LFSDET SAI_xSR_LFSDET

Define Documentation

#define SAI_FLAG_AFSDET SAI_xSR_AFSDET

Definition at line 604 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define SAI_FLAG_CNRDY SAI_xSR_CNRDY

Definition at line 603 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define SAI_FLAG_FREQ SAI_xSR_FREQ

Definition at line 602 of file stm32wbxx_hal_sai.h.

#define SAI_FLAG_LFSDET SAI_xSR_LFSDET

Definition at line 605 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define SAI_FLAG_MUTEDET SAI_xSR_MUTEDET

Definition at line 600 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

#define SAI_FLAG_OVRUDR SAI_xSR_OVRUDR

Definition at line 599 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), and SAI_Receive_IT8Bit().

#define SAI_FLAG_WCKCFG SAI_xSR_WCKCFG

Definition at line 601 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler().

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STM32WB55xx HAL User Manual: SAI Block Fifo Status Level

Defines
SAI Block Fifo Status Level
SAI Exported Constants

Defines

#define | SAI_FIFOSTATUS_EMPTY 0x00000000U
#define | SAI_FIFOSTATUS_LESS1QUARTERFULL 0x00010000U
#define | SAI_FIFOSTATUS_1QUARTERFULL 0x00020000U
#define | SAI_FIFOSTATUS_HALFFULL 0x00030000U
#define | SAI_FIFOSTATUS_3QUARTERFULL 0x00040000U
#define | SAI_FIFOSTATUS_FULL 0x00050000U

Define Documentation

#define SAI_FIFOSTATUS_1QUARTERFULL 0x00020000U

Definition at line 615 of file stm32wbxx_hal_sai.h.

#define SAI_FIFOSTATUS_3QUARTERFULL 0x00040000U

Definition at line 617 of file stm32wbxx_hal_sai.h.

#define SAI_FIFOSTATUS_EMPTY 0x00000000U

Definition at line 613 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Receive(), and HAL_SAI_Transmit_DMA().

#define SAI_FIFOSTATUS_FULL 0x00050000U

Definition at line 618 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Transmit(), and SAI_FillFifo().

#define SAI_FIFOSTATUS_HALFFULL 0x00030000U

Definition at line 616 of file stm32wbxx_hal_sai.h.

#define SAI_FIFOSTATUS_LESS1QUARTERFULL 0x00010000U

Definition at line 614 of file stm32wbxx_hal_sai.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAI Exported Macros

Defines
SAI Exported Macros
SAI

macros to handle interrupts and specific configurations More...

Defines

#define | __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__)
Reset SAI handle state.
#define | __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
Enable the specified SAI interrupts.
#define | __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))
Disable the specified SAI interrupts.
#define | __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified SAI interrupt source is enabled or not.
#define | __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Check whether the specified SAI flag is set or not.
#define | __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
Clear the specified SAI pending flag.
#define | __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN)
Enable SAI.
#define | __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN)
Disable SAI.

Detailed Description

macros to handle interrupts and specific configurations

Define Documentation

#define __HAL_SAI_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->CLRFR = (__FLAG__))

Clear the specified SAI pending flag.

Parameters:
__HANDLE__ specifies the SAI Handle.
__FLAG__ specifies the flag to check. This parameter can be any combination of the following values:
  • SAI_FLAG_OVRUDR: Clear Overrun underrun
  • SAI_FLAG_MUTEDET: Clear Mute detection
  • SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration
  • SAI_FLAG_FREQ: Clear FIFO request
  • SAI_FLAG_CNRDY: Clear Codec not ready
  • SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection
  • SAI_FLAG_LFSDET: Clear Late frame synchronization detection
Return values:
None

Definition at line 721 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_IRQHandler(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), and SAI_Receive_IT8Bit().

#define __HAL_SAI_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN)

Disable SAI.

Parameters:
__HANDLE__ specifies the SAI Handle.
Return values:
None

Definition at line 733 of file stm32wbxx_hal_sai.h.

Referenced by SAI_Disable().

#define __HAL_SAI_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))

Disable the specified SAI interrupts.

Parameters:
__HANDLE__ specifies the SAI Handle.
__INTERRUPT__ specifies the interrupt source to enable or disable. This parameter can be one of the following values:
  • SAI_IT_OVRUDR: Overrun underrun interrupt enable
  • SAI_IT_MUTEDET: Mute detection interrupt enable
  • SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
  • SAI_IT_FREQ: FIFO request interrupt enable
  • SAI_IT_CNRDY: Codec not ready interrupt enable
  • SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
  • SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
Return values:
None

Definition at line 675 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_DisableRxMuteMode(), SAI_DMARxCplt(), SAI_DMATxCplt(), SAI_Receive_IT16Bit(), SAI_Receive_IT32Bit(), SAI_Receive_IT8Bit(), SAI_Transmit_IT16Bit(), SAI_Transmit_IT32Bit(), and SAI_Transmit_IT8Bit().

#define __HAL_SAI_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN)

Enable SAI.

Parameters:
__HANDLE__ specifies the SAI Handle.
Return values:
None

Definition at line 727 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_DMAResume(), HAL_SAI_Receive(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit(), HAL_SAI_Transmit_DMA(), and HAL_SAI_Transmit_IT().

#define __HAL_SAI_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))

Enable the specified SAI interrupts.

Parameters:
__HANDLE__ specifies the SAI Handle.
__INTERRUPT__ specifies the interrupt source to enable or disable. This parameter can be one of the following values:
  • SAI_IT_OVRUDR: Overrun underrun interrupt enable
  • SAI_IT_MUTEDET: Mute detection interrupt enable
  • SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
  • SAI_IT_FREQ: FIFO request interrupt enable
  • SAI_IT_CNRDY: Codec not ready interrupt enable
  • SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
  • SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
Return values:
None

Definition at line 660 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_EnableRxMuteMode(), HAL_SAI_Receive_DMA(), HAL_SAI_Receive_IT(), HAL_SAI_Transmit_DMA(), and HAL_SAI_Transmit_IT().

#define __HAL_SAI_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

Check whether the specified SAI flag is set or not.

Parameters:
__HANDLE__ specifies the SAI Handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • SAI_FLAG_OVRUDR: Overrun underrun flag.
  • SAI_FLAG_MUTEDET: Mute detection flag.
  • SAI_FLAG_WCKCFG: Wrong Clock Configuration flag.
  • SAI_FLAG_FREQ: FIFO request flag.
  • SAI_FLAG_CNRDY: Codec not ready flag.
  • SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag.
  • SAI_FLAG_LFSDET: Late frame synchronization detection flag.
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 705 of file stm32wbxx_hal_sai.h.

#define __HAL_SAI_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified SAI interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the SAI Handle.
__INTERRUPT__ specifies the SAI interrupt source to check. This parameter can be one of the following values:
  • SAI_IT_OVRUDR: Overrun underrun interrupt enable
  • SAI_IT_MUTEDET: Mute detection interrupt enable
  • SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
  • SAI_IT_FREQ: FIFO request interrupt enable
  • SAI_IT_CNRDY: Codec not ready interrupt enable
  • SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
  • SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
Return values:
The new state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 690 of file stm32wbxx_hal_sai.h.

#define __HAL_SAI_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                            \
                                                     (__HANDLE__)->State = HAL_SAI_STATE_RESET; \
                                                     (__HANDLE__)->MspInitCallback = NULL;      \
                                                     (__HANDLE__)->MspDeInitCallback = NULL;    \
                                                   } while(0)

Reset SAI handle state.

Parameters:
__HANDLE__ specifies the SAI Handle.
Return values:
None

Definition at line 638 of file stm32wbxx_hal_sai.h.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAI Private Macros

Defines
SAI Private Macros
SAI

Defines

#define | IS_SAI_BLOCK_SYNCEXT(STATE)
#define | IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL)
#define | IS_SAI_PROTOCOL_DATASIZE(DATASIZE)
#define | IS_SAI_AUDIO_FREQUENCY(AUDIO)
#define | IS_SAI_BLOCK_MCK_OVERSAMPLING(VALUE)
#define | IS_SAI_PDM_MIC_PAIRS_NUMBER(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 3U))
#define | IS_SAI_PDM_CLOCK_ENABLE(CLOCK)
#define | IS_SAI_BLOCK_MODE(MODE)
#define | IS_SAI_BLOCK_PROTOCOL(PROTOCOL)
#define | IS_SAI_BLOCK_DATASIZE(DATASIZE)
#define | IS_SAI_BLOCK_FIRST_BIT(BIT)
#define | IS_SAI_BLOCK_CLOCK_STROBING(CLOCK)
#define | IS_SAI_BLOCK_SYNCHRO(SYNCHRO)
#define | IS_SAI_BLOCK_MCK_OUTPUT(VALUE)
#define | IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE)
#define | IS_SAI_BLOCK_NODIVIDER(NODIVIDER)
#define | IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63U)
#define | IS_SAI_BLOCK_MUTE_VALUE(VALUE)
#define | IS_SAI_BLOCK_COMPANDING_MODE(MODE)
#define | IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD)
#define | IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE)
#define | IS_SAI_MONO_STEREO_MODE(MODE)
#define | IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) <= SAI_SLOTACTIVE_ALL)
#define | IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1U <= (NUMBER)) && ((NUMBER) <= 16U))
#define | IS_SAI_BLOCK_SLOT_SIZE(SIZE)
#define | IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24U)
#define | IS_SAI_BLOCK_FS_OFFSET(OFFSET)
#define | IS_SAI_BLOCK_FS_POLARITY(POLARITY)
#define | IS_SAI_BLOCK_FS_DEFINITION(DEFINITION)
#define | IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 63U)
#define | IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8U <= (LENGTH)) && ((LENGTH) <= 256U))
#define | IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1U <= (LENGTH)) && ((LENGTH) <= 128U))

Define Documentation

#define IS_SAI_AUDIO_FREQUENCY ( AUDIO )
Value:
(((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \
                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_48K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \
                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_32K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \
                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_16K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \
                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_8K)   || ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV))

Definition at line 841 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_ACTIVE_FRAME ( LENGTH ) ((1U <= (LENGTH)) && ((LENGTH) <= 128U))

Definition at line 937 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_CLOCK_STROBING ( CLOCK )
Value:
(((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \
                                            ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))

Definition at line 874 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_COMPANDING_MODE ( MODE )
Value:
(((MODE) == SAI_NOCOMPANDING)         || \
                                               ((MODE) == SAI_ULAW_1CPL_COMPANDING) || \
                                               ((MODE) == SAI_ALAW_1CPL_COMPANDING) || \
                                               ((MODE) == SAI_ULAW_2CPL_COMPANDING) || \
                                               ((MODE) == SAI_ALAW_2CPL_COMPANDING))

Definition at line 896 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_DATASIZE ( DATASIZE )
Value:
(((DATASIZE) == SAI_DATASIZE_8)  || \
                                         ((DATASIZE) == SAI_DATASIZE_10) || \
                                         ((DATASIZE) == SAI_DATASIZE_16) || \
                                         ((DATASIZE) == SAI_DATASIZE_20) || \
                                         ((DATASIZE) == SAI_DATASIZE_24) || \
                                         ((DATASIZE) == SAI_DATASIZE_32))

Definition at line 864 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FIFO_THRESHOLD ( THRESHOLD )
Value:
(((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY)   || \
                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF)     || \
                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_HF)      || \
                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF)     || \
                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL))

Definition at line 902 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FIRST_BIT ( BIT )
Value:
(((BIT) == SAI_FIRSTBIT_MSB) || \
                                     ((BIT) == SAI_FIRSTBIT_LSB))

Definition at line 871 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FIRSTBIT_OFFSET ( OFFSET ) ((OFFSET) <= 24U)

Definition at line 922 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FRAME_LENGTH ( LENGTH ) ((8U <= (LENGTH)) && ((LENGTH) <= 256U))

Definition at line 935 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FS_DEFINITION ( DEFINITION )
Value:
(((DEFINITION) == SAI_FS_STARTFRAME) || \
                                                ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION))

Definition at line 930 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FS_OFFSET ( OFFSET )
Value:
(((OFFSET) == SAI_FS_FIRSTBIT) || \
                                        ((OFFSET) == SAI_FS_BEFOREFIRSTBIT))

Definition at line 924 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_FS_POLARITY ( POLARITY )
Value:
(((POLARITY) == SAI_FS_ACTIVE_LOW) || \
                                            ((POLARITY) == SAI_FS_ACTIVE_HIGH))

Definition at line 927 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_MASTER_DIVIDER ( DIVIDER ) ((DIVIDER) <= 63U)

Definition at line 933 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_MCK_OUTPUT ( VALUE )
Value:
(((VALUE) == SAI_MCK_OUTPUT_ENABLE) || \
                                        ((VALUE) == SAI_MCK_OUTPUT_DISABLE))

Definition at line 882 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_MCK_OVERSAMPLING ( VALUE )
Value:
(((VALUE) == SAI_MCK_OVERSAMPLING_DISABLE) || \
                                              ((VALUE) == SAI_MCK_OVERSAMPLING_ENABLE))

Definition at line 847 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_MODE ( MODE )
Value:
(((MODE) == SAI_MODEMASTER_TX) || \
                                  ((MODE) == SAI_MODEMASTER_RX) || \
                                  ((MODE) == SAI_MODESLAVE_TX)  || \
                                  ((MODE) == SAI_MODESLAVE_RX))

Definition at line 855 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_MUTE_COUNTER ( COUNTER ) ((COUNTER) <= 63U)

Definition at line 891 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_EnableRxMuteMode().

#define IS_SAI_BLOCK_MUTE_VALUE ( VALUE )
Value:
(((VALUE) == SAI_ZERO_VALUE)     || \
                                           ((VALUE) == SAI_LAST_SENT_VALUE))

Definition at line 893 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_EnableTxMuteMode().

#define IS_SAI_BLOCK_NODIVIDER ( NODIVIDER )
Value:
(((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \
                                           ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE))

Definition at line 888 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_OUTPUT_DRIVE ( DRIVE )
Value:
(((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \
                                          ((DRIVE) == SAI_OUTPUTDRIVE_ENABLE))

Definition at line 885 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_PROTOCOL ( PROTOCOL )
Value:
(((PROTOCOL) == SAI_FREE_PROTOCOL)  || \
                                         ((PROTOCOL) == SAI_AC97_PROTOCOL)  || \
                                         ((PROTOCOL) == SAI_SPDIF_PROTOCOL))

Definition at line 860 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_SLOT_NUMBER ( NUMBER ) ((1U <= (NUMBER)) && ((NUMBER) <= 16U))

Definition at line 916 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_SLOT_SIZE ( SIZE )
Value:
(((SIZE) == SAI_SLOTSIZE_DATASIZE) || \
                                      ((SIZE) == SAI_SLOTSIZE_16B)      || \
                                      ((SIZE) == SAI_SLOTSIZE_32B))

Definition at line 918 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_SYNCEXT ( STATE )
Value:
(((STATE) == SAI_SYNCEXT_DISABLE) ||\
                                     ((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE) ||\
                                     ((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE))

Definition at line 826 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_SYNCHRO ( SYNCHRO )
Value:
(((SYNCHRO) == SAI_ASYNCHRONOUS)         || \
                                       ((SYNCHRO) == SAI_SYNCHRONOUS)          || \
                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) || \
                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2))

Definition at line 877 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT ( STATE )
Value:
(((STATE) == SAI_OUTPUT_NOTRELEASED) ||\
                                                 ((STATE) == SAI_OUTPUT_RELEASED))

Definition at line 908 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_MONO_STEREO_MODE ( MODE )
Value:
(((MODE) == SAI_MONOMODE) ||\
                                       ((MODE) == SAI_STEREOMODE))

Definition at line 911 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_PDM_CLOCK_ENABLE ( CLOCK )
Value:
(((CLOCK) != 0U) && \
                                       (((CLOCK) & ~(SAI_PDM_CLOCK1_ENABLE | SAI_PDM_CLOCK2_ENABLE)) == 0U))

Definition at line 852 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_PDM_MIC_PAIRS_NUMBER ( VALUE ) ((1U <= (VALUE)) && ((VALUE) <= 3U))

Definition at line 850 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init(), and HAL_SAIEx_ConfigPdmMicDelay().

#define IS_SAI_PROTOCOL_DATASIZE ( DATASIZE )
Value:
(((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BIT)         ||\
                                              ((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) ||\
                                              ((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT)         ||\
                                              ((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT))

Definition at line 836 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol().

#define IS_SAI_SLOT_ACTIVE ( ACTIVE ) ((ACTIVE) <= SAI_SLOTACTIVE_ALL)

Definition at line 914 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_Init().

#define IS_SAI_SUPPORTED_PROTOCOL ( PROTOCOL )
Value:
(((PROTOCOL) == SAI_I2S_STANDARD)     ||\
                                               ((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\
                                               ((PROTOCOL) == SAI_I2S_LSBJUSTIFIED) ||\
                                               ((PROTOCOL) == SAI_PCM_LONG)         ||\
                                               ((PROTOCOL) == SAI_PCM_SHORT))

Definition at line 830 of file stm32wbxx_hal_sai.h.

Referenced by HAL_SAI_InitProtocol().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAIEx Extended Private Defines

Defines
SAIEx Extended Private Defines
SAIEx

Defines

#define | SAI_PDM_DELAY_MASK 0x77U
#define | SAI_PDM_DELAY_OFFSET 8U
#define | SAI_PDM_RIGHT_DELAY_OFFSET 4U

Define Documentation

#define SAI_PDM_DELAY_MASK 0x77U

Definition at line 45 of file stm32wbxx_hal_sai_ex.c.

Referenced by HAL_SAIEx_ConfigPdmMicDelay().

#define SAI_PDM_DELAY_OFFSET 8U

Definition at line 46 of file stm32wbxx_hal_sai_ex.c.

Referenced by HAL_SAIEx_ConfigPdmMicDelay().

#define SAI_PDM_RIGHT_DELAY_OFFSET 4U

Definition at line 47 of file stm32wbxx_hal_sai_ex.c.

Referenced by HAL_SAIEx_ConfigPdmMicDelay().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
SAIEx Extended Exported Functions

SAIEx control functions. More...

Functions

HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay (SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay)
Configure PDM microphone delays.

Detailed Description

SAIEx control functions.

 ===============================================================================
                 ##### Extended features functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Modify PDM microphone delays

Function Documentation

HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay | ( | SAI_HandleTypeDef * | hsai,
 |  | SAIEx_PdmMicDelayParamTypeDef * | pdmMicDelay
 | ) |  |

Configure PDM microphone delays.

Parameters:
hsai | SAI handle.
pdmMicDelay | Microphone delays configuration.
Return values:
HAL status

Definition at line 79 of file stm32wbxx_hal_sai_ex.c.

References assert_param, HAL_SAI_STATE_RESET, __SAI_HandleTypeDef::Instance, IS_SAI_PDM_MIC_DELAY, IS_SAI_PDM_MIC_PAIRS_NUMBER, SAIEx_PdmMicDelayParamTypeDef::LeftDelay, SAIEx_PdmMicDelayParamTypeDef::MicPair, SAIEx_PdmMicDelayParamTypeDef::RightDelay, SAI_PDM_DELAY_MASK, SAI_PDM_DELAY_OFFSET, SAI_PDM_RIGHT_DELAY_OFFSET, and __SAI_HandleTypeDef::State.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAIEx_PdmMicDelayParamTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SAIEx_PdmMicDelayParamTypeDef Struct Reference
SAIEx Exported Types

PDM microphone delay structure definition. More...

#include <stm32wbxx_hal_sai_ex.h>

Data Fields

uint32_t | MicPair
uint32_t | LeftDelay
uint32_t | RightDelay

Detailed Description

PDM microphone delay structure definition.

Definition at line 49 of file stm32wbxx_hal_sai_ex.h.

Field Documentation

uint32_t SAIEx_PdmMicDelayParamTypeDef::LeftDelay

Specifies the delay in PDM clock unit to apply on left microphone. This parameter must be a number between Min_Data = 0 and Max_Data = 7.

Definition at line 54 of file stm32wbxx_hal_sai_ex.h.

Referenced by HAL_SAIEx_ConfigPdmMicDelay().

uint32_t SAIEx_PdmMicDelayParamTypeDef::MicPair

Specifies which pair of microphones is selected. This parameter must be a number between Min_Data = 1 and Max_Data = 3.

Definition at line 51 of file stm32wbxx_hal_sai_ex.h.

Referenced by HAL_SAIEx_ConfigPdmMicDelay().

uint32_t SAIEx_PdmMicDelayParamTypeDef::RightDelay

Specifies the delay in PDM clock unit to apply on right microphone. This parameter must be a number between Min_Data = 0 and Max_Data = 7.

Definition at line 57 of file stm32wbxx_hal_sai_ex.h.

Referenced by HAL_SAIEx_ConfigPdmMicDelay().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_sai_ex.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAIEx Extended Private Macros

Defines
SAIEx Extended Private Macros
SAIEx

Defines

#define IS_SAI_PDM_MIC_DELAY(VALUE) ((VALUE) <= 7U)

Define Documentation

#define IS_SAI_PDM_MIC_DELAY ( VALUE ) ((VALUE) <= 7U)

Definition at line 88 of file stm32wbxx_hal_sai_ex.h.

Referenced by HAL_SAIEx_ConfigPdmMicDelay().

Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMARTCARD Private Constants

Defines
SMARTCARD Private Constants
SMARTCARD

Defines

#define | SMARTCARD_TEACK_REACK_TIMEOUT 1000U
#define | USART_CR1_FIELDS
#define | USART_CR2_CLK_FIELDS
#define | USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | USART_CR2_STOP))
#define | USART_CR3_FIELDS
#define | USART_BRR_MIN 0x10U
#define | USART_BRR_MAX 0x0000FFFFU

Define Documentation

#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U

SMARTCARD TX or RX enable acknowledge time-out value

Definition at line 201 of file stm32wbxx_hal_smartcard.c.

Referenced by SMARTCARD_CheckIdleState().

#define USART_BRR_MAX 0x0000FFFFU

USART BRR maximum authorized value

Definition at line 217 of file stm32wbxx_hal_smartcard.c.

Referenced by SMARTCARD_SetConfig().

#define USART_BRR_MIN 0x10U

USART BRR minimum authorized value

Definition at line 215 of file stm32wbxx_hal_smartcard.c.

Referenced by SMARTCARD_SetConfig().

#define USART_CR1_FIELDS
Value:
((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS   | \
                                          USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \
                                          USART_CR1_FIFOEN ))

USART CR1 fields of parameters set by SMARTCARD_SetConfig API

Definition at line 203 of file stm32wbxx_hal_smartcard.c.

Referenced by SMARTCARD_SetConfig().

#define USART_CR2_CLK_FIELDS
Value:
((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | \
                                          USART_CR2_LBCL))

SMARTCARD clock-related USART CR2 fields of parameters

Definition at line 207 of file stm32wbxx_hal_smartcard.c.

#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | USART_CR2_STOP))

USART CR2 fields of parameters set by SMARTCARD_SetConfig API

Definition at line 210 of file stm32wbxx_hal_smartcard.c.

Referenced by SMARTCARD_SetConfig().

#define USART_CR3_FIELDS
Value:
((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT | \
                                          USART_CR3_TXFTCFG | USART_CR3_RXFTCFG ))

USART CR3 fields of parameters set by SMARTCARD_SetConfig API

Definition at line 212 of file stm32wbxx_hal_smartcard.c.

Referenced by SMARTCARD_SetConfig().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SMARTCARD Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SMARTCARD_Init (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD mode according to the specified parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMARTCARD_DeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD peripheral.
__weak void | HAL_SMARTCARD_MspInit (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD MSP.
__weak void | HAL_SMARTCARD_MspDeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD MSP.
HAL_StatusTypeDef | HAL_SMARTCARD_RegisterCallback (SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback)
Register a User SMARTCARD Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SMARTCARD_UnRegisterCallback (SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID)
Unregister an SMARTCARD callback SMARTCARD callback is redirected to the weak predefined callback.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and Configuration functions #####
  ==============================================================================
  [..]
  This subsection provides a set of functions allowing to initialize the USARTx
  associated to the SmartCard.
  (+) These parameters can be configured:
      (++) Baud Rate
      (++) Parity: parity should be enabled, frame Length is fixed to 8 bits plus parity
      (++) Receiver/transmitter modes
      (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)
      (++) Prescaler value
      (++) Guard bit time
      (++) NACK enabling or disabling on transmission error

  (+) The following advanced features can be configured as well:
      (++) TX and/or RX pin level inversion
      (++) data logical level inversion
      (++) RX and TX pins swap
      (++) RX overrun detection disabling
      (++) DMA disabling on RX error
      (++) MSB first on communication line
      (++) Time out enabling (and if activated, timeout value)
      (++) Block length
      (++) Auto-retry counter
  [..]
  The HAL_SMARTCARD_Init() API follows the USART synchronous configuration procedures
  (details for the procedures are available in reference manual).

The USART frame format is given in the following table:

Table 1. USART frame format. +---------------------------------------------------------------+ | M1M0 bits | PCE bit | USART frame | |-----------------------|---------------------------------------| | 01 | 1 | | SB | 8 bit data | PB | STB | | +---------------------------------------------------------------+

Function Documentation

HAL_StatusTypeDef HAL_SMARTCARD_DeInit ( SMARTCARD_HandleTypeDef * hsmartcard )

DeInitialize the SMARTCARD peripheral.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 388 of file stm32wbxx_hal_smartcard.c.

References assert_param, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_MspDeInit(), HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_RESET, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::MspDeInitCallback, and __SMARTCARD_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_SMARTCARD_Init ( SMARTCARD_HandleTypeDef * hsmartcard )

Initialize the SMARTCARD mode according to the specified parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 315 of file stm32wbxx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::AdvancedInit, SMARTCARD_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_MspInit(), HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_RESET, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::Lock, __SMARTCARD_HandleTypeDef::MspInitCallback, SMARTCARD_ADVFEATURE_NO_INIT, SMARTCARD_AdvFeatureConfig(), SMARTCARD_CheckIdleState(), SMARTCARD_InitCallbacksToDefault(), SMARTCARD_SetConfig(), and SMARTCARD_TRANSMISSION_COMPLETION_SETTING.

void HAL_SMARTCARD_MspDeInit ( SMARTCARD_HandleTypeDef * hsmartcard )

DeInitialize the SMARTCARD MSP.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 454 of file stm32wbxx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_DeInit(), and HAL_SMARTCARD_UnRegisterCallback().

void HAL_SMARTCARD_MspInit ( SMARTCARD_HandleTypeDef * hsmartcard )

Initialize the SMARTCARD MSP.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 438 of file stm32wbxx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_Init(), and HAL_SMARTCARD_UnRegisterCallback().

HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | HAL_SMARTCARD_CallbackIDTypeDef | CallbackID,
 |  | pSMARTCARD_CallbackTypeDef | pCallback
 | ) |  |

Register a User SMARTCARD Callback To be used instead of the weak predefined callback.

Parameters:
hsmartcard | smartcard handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID
  • HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_SMARTCARD_ERROR_CB_ID Error Callback ID
  • HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
  • HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
  • HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
  • HAL_SMARTCARD_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
  • HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
  • HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID
  • HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 484 of file stm32wbxx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::AbortCpltCallback, __SMARTCARD_HandleTypeDef::AbortReceiveCpltCallback, __SMARTCARD_HandleTypeDef::AbortTransmitCpltCallback, __SMARTCARD_HandleTypeDef::ErrorCallback, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_ABORT_COMPLETE_CB_ID, HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID, HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID, HAL_SMARTCARD_ERROR_CB_ID, HAL_SMARTCARD_ERROR_INVALID_CALLBACK, HAL_SMARTCARD_MSPDEINIT_CB_ID, HAL_SMARTCARD_MSPINIT_CB_ID, HAL_SMARTCARD_RX_COMPLETE_CB_ID, HAL_SMARTCARD_RX_FIFO_FULL_CB_ID, HAL_SMARTCARD_STATE_READY, HAL_SMARTCARD_STATE_RESET, HAL_SMARTCARD_TX_COMPLETE_CB_ID, HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID, __SMARTCARD_HandleTypeDef::MspDeInitCallback, __SMARTCARD_HandleTypeDef::MspInitCallback, __SMARTCARD_HandleTypeDef::RxCpltCallback, __SMARTCARD_HandleTypeDef::RxFifoFullCallback, __SMARTCARD_HandleTypeDef::TxCpltCallback, and __SMARTCARD_HandleTypeDef::TxFifoEmptyCallback.

HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | HAL_SMARTCARD_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an SMARTCARD callback SMARTCARD callback is redirected to the weak predefined callback.

Parameters:
hsmartcard smartcard handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID
  • HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_SMARTCARD_ERROR_CB_ID Error Callback ID
  • HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
  • HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
  • HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
  • HAL_SMARTCARD_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
  • HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
  • HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID
  • HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
Return values:
HAL status

Definition at line 606 of file stm32wbxx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::AbortCpltCallback, __SMARTCARD_HandleTypeDef::AbortReceiveCpltCallback, __SMARTCARD_HandleTypeDef::AbortTransmitCpltCallback, __SMARTCARD_HandleTypeDef::ErrorCallback, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_ABORT_COMPLETE_CB_ID, HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID, HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID, HAL_SMARTCARD_AbortCpltCallback(), HAL_SMARTCARD_AbortReceiveCpltCallback(), HAL_SMARTCARD_AbortTransmitCpltCallback(), HAL_SMARTCARD_ERROR_CB_ID, HAL_SMARTCARD_ERROR_INVALID_CALLBACK, HAL_SMARTCARD_ErrorCallback(), HAL_SMARTCARD_MspDeInit(), HAL_SMARTCARD_MSPDEINIT_CB_ID, HAL_SMARTCARD_MspInit(), HAL_SMARTCARD_MSPINIT_CB_ID, HAL_SMARTCARD_RX_COMPLETE_CB_ID, HAL_SMARTCARD_RX_FIFO_FULL_CB_ID, HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_STATE_READY, HAL_SMARTCARD_STATE_RESET, HAL_SMARTCARD_TX_COMPLETE_CB_ID, HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID, HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARDEx_RxFifoFullCallback(), HAL_SMARTCARDEx_TxFifoEmptyCallback(), __SMARTCARD_HandleTypeDef::MspDeInitCallback, __SMARTCARD_HandleTypeDef::MspInitCallback, __SMARTCARD_HandleTypeDef::RxCpltCallback, __SMARTCARD_HandleTypeDef::RxFifoFullCallback, __SMARTCARD_HandleTypeDef::TxCpltCallback, and __SMARTCARD_HandleTypeDef::TxFifoEmptyCallback.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IO operation functions

Functions
IO operation functions
SMARTCARD Exported Functions

SMARTCARD Transmit and Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_SMARTCARD_Transmit (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_DMA (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_DMA (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Abort (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_Abort_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_SMARTCARD_IRQHandler (SMARTCARD_HandleTypeDef *hsmartcard)
Handle SMARTCARD interrupt requests.
__weak void | HAL_SMARTCARD_TxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Tx Transfer completed callback.
__weak void | HAL_SMARTCARD_RxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Rx Transfer completed callback.
__weak void | HAL_SMARTCARD_ErrorCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD error callback.
__weak void | HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Complete callback.
__weak void | HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Complete callback.
__weak void | HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Receive Complete callback.

Detailed Description

SMARTCARD Transmit and Receive functions.

  ==============================================================================
                         ##### IO operation functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.

  [..]
    Smartcard is a single wire half duplex communication protocol.
    The Smartcard interface is designed to support asynchronous protocol Smartcards as
    defined in the ISO 7816-3 standard. The USART should be configured as:
    (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
    (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.

  [..]
    (+) There are two modes of transfer:
        (++) Blocking mode: The communication is performed in polling mode.
             The HAL status of all data processing is returned by the same function
             after finishing transfer.
        (++) Non-Blocking mode: The communication is performed using Interrupts
             or DMA, the relevant API's return the HAL status.
             The end of the data processing will be indicated through the
             dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
             using DMA mode.
        (++) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
             will be executed respectively at the end of the Transmit or Receive process
             The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
             error is detected.

    (+) Blocking mode APIs are :
        (++) HAL_SMARTCARD_Transmit()
        (++) HAL_SMARTCARD_Receive()

    (+) Non Blocking mode APIs with Interrupt are :
        (++) HAL_SMARTCARD_Transmit_IT()
        (++) HAL_SMARTCARD_Receive_IT()
        (++) HAL_SMARTCARD_IRQHandler()

    (+) Non Blocking mode functions with DMA are :
        (++) HAL_SMARTCARD_Transmit_DMA()
        (++) HAL_SMARTCARD_Receive_DMA()

    (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
        (++) HAL_SMARTCARD_TxCpltCallback()
        (++) HAL_SMARTCARD_RxCpltCallback()
        (++) HAL_SMARTCARD_ErrorCallback()

    (#) Non-Blocking mode transfers could be aborted using Abort API's :
        (+) HAL_SMARTCARD_Abort()
        (+) HAL_SMARTCARD_AbortTransmit()
        (+) HAL_SMARTCARD_AbortReceive()
        (+) HAL_SMARTCARD_Abort_IT()
        (+) HAL_SMARTCARD_AbortTransmit_IT()
        (+) HAL_SMARTCARD_AbortReceive_IT()

    (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
        (+) HAL_SMARTCARD_AbortCpltCallback()
        (+) HAL_SMARTCARD_AbortTransmitCpltCallback()
        (+) HAL_SMARTCARD_AbortReceiveCpltCallback()

    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
        Errors are handled as follows :
       (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
           to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
           Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
           and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
           If user wants to abort it, Abort services should be called by user.
       (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
           This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
           Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.

Function Documentation

HAL_StatusTypeDef HAL_SMARTCARD_Abort ( SMARTCARD_HandleTypeDef * hsmartcard )

Abort ongoing transfers (blocking mode).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SMARTCARD Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1276 of file stm32wbxx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_SMARTCARD_ERROR_DMA, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmarx, __SMARTCARD_HandleTypeDef::hdmatx, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, __SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT ( SMARTCARD_HandleTypeDef * hsmartcard )

Abort ongoing transfers (Interrupt mode).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SMARTCARD Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1502 of file stm32wbxx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::AbortCpltCallback, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_SMARTCARD_AbortCpltCallback(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmarx, __SMARTCARD_HandleTypeDef::hdmatx, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::RxISR, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMATxAbortCallback(), __SMARTCARD_HandleTypeDef::TxISR, __SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_SMARTCARD_AbortCpltCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

SMARTCARD Abort Complete callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2153 of file stm32wbxx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMATxAbortCallback(), and SMARTCARD_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive ( SMARTCARD_HandleTypeDef * hsmartcard )

Abort ongoing Receive transfer (blocking mode).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Note:
This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SMARTCARD Interrupts (Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1434 of file stm32wbxx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_SMARTCARD_ERROR_DMA, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmarx, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT ( SMARTCARD_HandleTypeDef * hsmartcard )

Abort ongoing Receive transfer (Interrupt mode).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Note:
This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SMARTCARD Interrupts (Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1733 of file stm32wbxx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::AbortReceiveCpltCallback, __SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_SMARTCARD_AbortReceiveCpltCallback(), HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmarx, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::RxISR, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, SMARTCARD_DMARxOnlyAbortCallback(), and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_SMARTCARD_AbortReceiveCpltCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

SMARTCARD Abort Receive Complete callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2185 of file stm32wbxx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMARxOnlyAbortCallback(), and SMARTCARD_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit ( SMARTCARD_HandleTypeDef * hsmartcard )

Abort ongoing Transmit transfer (blocking mode).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Note:
This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SMARTCARD Interrupts (Tx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1368 of file stm32wbxx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_SMARTCARD_ERROR_DMA, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmatx, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::RxState, SMARTCARD_CLEAR_FEF, __SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT ( SMARTCARD_HandleTypeDef * hsmartcard )

Abort ongoing Transmit transfer (Interrupt mode).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Note:
This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SMARTCARD Interrupts (Tx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1638 of file stm32wbxx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::AbortTransmitCpltCallback, __SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_SMARTCARD_AbortTransmitCpltCallback(), HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmatx, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::RxState, SMARTCARD_CLEAR_FEF, SMARTCARD_DMATxOnlyAbortCallback(), __SMARTCARD_HandleTypeDef::TxISR, __SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_SMARTCARD_AbortTransmitCpltCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

SMARTCARD Abort Complete callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2169 of file stm32wbxx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMATxOnlyAbortCallback(), and SMARTCARD_InitCallbacksToDefault().

void HAL_SMARTCARD_ErrorCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

SMARTCARD error callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2137 of file stm32wbxx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMAAbortOnError(), SMARTCARD_DMAError(), and SMARTCARD_InitCallbacksToDefault().

void HAL_SMARTCARD_IRQHandler ( SMARTCARD_HandleTypeDef * hsmartcard )

Handle SMARTCARD interrupt requests.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 1822 of file stm32wbxx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_IT, __HAL_SMARTCARD_GET_IT, __HAL_SMARTCARD_GET_IT_SOURCE, __SMARTCARD_HandleTypeDef::AdvancedInit, __SMARTCARD_HandleTypeDef::ErrorCallback, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_SMARTCARD_ERROR_FE, HAL_SMARTCARD_ERROR_NE, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_ERROR_ORE, HAL_SMARTCARD_ERROR_PE, HAL_SMARTCARD_ERROR_RTO, HAL_SMARTCARD_ErrorCallback(), HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_READY, HAL_SMARTCARDEx_RxFifoFullCallback(), HAL_SMARTCARDEx_TxFifoEmptyCallback(), __SMARTCARD_HandleTypeDef::hdmarx, __SMARTCARD_HandleTypeDef::hdmatx, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::RxCpltCallback, __SMARTCARD_HandleTypeDef::RxFifoFullCallback, __SMARTCARD_HandleTypeDef::RxISR, __SMARTCARD_HandleTypeDef::RxState, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, SMARTCARD_DMAAbortOnError(), SMARTCARD_EndRxTransfer(), SMARTCARD_EndTransmit_IT(), SMARTCARD_EndTxTransfer(), SMARTCARD_AdvFeatureInitTypeDef::TxCompletionIndication, __SMARTCARD_HandleTypeDef::TxFifoEmptyCallback, __SMARTCARD_HandleTypeDef::TxISR, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SMARTCARD_Receive | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Note:
When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO is not empty. Read operations from the RDR register are performed when RXFNE flag is set. From hardware perspective, RXFNE flag and RXNE are mapped on the same bit-field.
Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData | pointer to data buffer.
Size | amount of data to be received.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 885 of file stm32wbxx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, __SMARTCARD_HandleTypeDef::RxXferSize, SMARTCARD_FLAG_RXNE, and SMARTCARD_WaitOnFlagUntilTimeout().

HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in DMA mode.

Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData | pointer to data buffer.
Size | amount of data to be received.
Note:
The SMARTCARD-associated USART parity is enabled (PCE = 1), the received data contain the parity bit (MSB position).
Return values:
HAL status

Definition at line 1193 of file stm32wbxx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SMARTCARD_ERROR_DMA, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmarx, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::pRxBuffPtr, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferSize, SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in interrupt mode.

Note:
When FIFO mode is disabled, USART interrupt is generated whenever USART_RDR register can be read, i.e one interrupt per data to receive.
When FIFO mode is enabled, USART interrupt is generated whenever RXFIFO threshold reached. In that case the interrupt rate depends on RXFIFO threshold configuration.
This function sets the hsmartcard->RxIsr function pointer according to the FIFO mode (data reception processing depends on FIFO mode).
Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData | pointer to data buffer.
Size | amount of data to be received.
Return values:
HAL status

Definition at line 1037 of file stm32wbxx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::FifoMode, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::NbRxDataToProcess, __SMARTCARD_HandleTypeDef::pRxBuffPtr, __SMARTCARD_HandleTypeDef::RxISR, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, __SMARTCARD_HandleTypeDef::RxXferSize, SMARTCARD_FIFOMODE_ENABLE, SMARTCARD_RxISR(), and SMARTCARD_RxISR_FIFOEN().

void HAL_SMARTCARD_RxCpltCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

Rx Transfer completed callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2121 of file stm32wbxx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_InitCallbacksToDefault(), SMARTCARD_RxISR(), and SMARTCARD_RxISR_FIFOEN().

HAL_StatusTypeDef HAL_SMARTCARD_Transmit | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Send an amount of data in blocking mode.

Note:
When FIFO mode is enabled, writing a data in the TDR register adds one data to the TXFIFO. Write operations to the TDR register are performed when TXFNF flag is set. From hardware perspective, TXFNF flag and TXE are mapped on the same bit-field.
Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData | pointer to data buffer.
Size | amount of data to be sent.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 798 of file stm32wbxx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_GetTick(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Init, __SMARTCARD_HandleTypeDef::Instance, SMARTCARD_InitTypeDef::Mode, SMARTCARD_FLAG_TXE, SMARTCARD_MODE_TX_RX, SMARTCARD_RXDATA_FLUSH_REQUEST, SMARTCARD_TRANSMISSION_COMPLETION_FLAG, SMARTCARD_WaitOnFlagUntilTimeout(), __SMARTCARD_HandleTypeDef::TxXferCount, and __SMARTCARD_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in DMA mode.

Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData | pointer to data buffer.
Size | amount of data to be sent.
Return values:
HAL status

Definition at line 1101 of file stm32wbxx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_DMA_Start_IT(), HAL_SMARTCARD_ERROR_DMA, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmatx, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::pTxBuffPtr, SMARTCARD_DMAError(), SMARTCARD_DMATransmitCplt(), SMARTCARD_RXDATA_FLUSH_REQUEST, __SMARTCARD_HandleTypeDef::TxXferCount, __SMARTCARD_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in interrupt mode.

Note:
When FIFO mode is disabled, USART interrupt is generated whenever USART_TDR register is empty, i.e one interrupt per data to transmit.
When FIFO mode is enabled, USART interrupt is generated whenever TXFIFO threshold reached. In that case the interrupt rate depends on TXFIFO threshold configuration.
This function sets the hsmartcard->TxIsr function pointer according to the FIFO mode (data transmission processing depends on FIFO mode).
Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
pData | pointer to data buffer.
Size | amount of data to be sent.
Return values:
HAL status

Definition at line 952 of file stm32wbxx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::FifoMode, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::pTxBuffPtr, SMARTCARD_FIFOMODE_ENABLE, SMARTCARD_RXDATA_FLUSH_REQUEST, SMARTCARD_TxISR(), SMARTCARD_TxISR_FIFOEN(), __SMARTCARD_HandleTypeDef::TxISR, __SMARTCARD_HandleTypeDef::TxXferCount, and __SMARTCARD_HandleTypeDef::TxXferSize.

void HAL_SMARTCARD_TxCpltCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

Tx Transfer completed callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2105 of file stm32wbxx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_EndTransmit_IT(), and SMARTCARD_InitCallbacksToDefault().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
SMARTCARD Exported Functions

SMARTCARD State and Errors functions. More...

Functions

HAL_SMARTCARD_StateTypeDef | HAL_SMARTCARD_GetState (SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle state.
uint32_t | HAL_SMARTCARD_GetError (SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle error code.

Detailed Description

SMARTCARD State and Errors functions.

  ==============================================================================
                  ##### Peripheral State and Errors functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to return the State of SmartCard
    handle and also return Peripheral Errors occurred during communication process
     (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state
         of the SMARTCARD peripheral.
     (+) HAL_SMARTCARD_GetError() checks in run-time errors that could occur during
         communication.

Function Documentation

uint32_t HAL_SMARTCARD_GetError ( SMARTCARD_HandleTypeDef * hsmartcard )

Return the SMARTCARD handle error code.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
SMARTCARD handle Error Code

Definition at line 2240 of file stm32wbxx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::ErrorCode.

HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState ( SMARTCARD_HandleTypeDef * hsmartcard )

Return the SMARTCARD handle state.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
SMARTCARD handle state

Definition at line 2224 of file stm32wbxx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::gState, and __SMARTCARD_HandleTypeDef::RxState.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMARTCARD Private Functions

Functions
SMARTCARD Private Functions
SMARTCARD

Functions

void | SMARTCARD_InitCallbacksToDefault (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the callbacks to their default values.
static HAL_StatusTypeDef | SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsmartcard)
Configure the SMARTCARD associated USART peripheral.
static void | SMARTCARD_AdvFeatureConfig (SMARTCARD_HandleTypeDef *hsmartcard)
Configure the SMARTCARD associated USART peripheral advanced features.
static HAL_StatusTypeDef | SMARTCARD_CheckIdleState (SMARTCARD_HandleTypeDef *hsmartcard)
Check the SMARTCARD Idle State.
static HAL_StatusTypeDef | SMARTCARD_WaitOnFlagUntilTimeout (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle SMARTCARD Communication Timeout.
static void | SMARTCARD_EndTxTransfer (SMARTCARD_HandleTypeDef *hsmartcard)
End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
static void | SMARTCARD_EndRxTransfer (SMARTCARD_HandleTypeDef *hsmartcard)
End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
static void | SMARTCARD_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD transmit process complete callback.
static void | SMARTCARD_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD receive process complete callback.
static void | SMARTCARD_DMAError (DMA_HandleTypeDef *hdma)
DMA SMARTCARD communication error callback.
static void | SMARTCARD_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA SMARTCARD communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | SMARTCARD_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | SMARTCARD_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | SMARTCARD_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | SMARTCARD_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static void | SMARTCARD_TxISR (SMARTCARD_HandleTypeDef *hsmartcard)
Send an amount of data in non-blocking mode.
static void | SMARTCARD_TxISR_FIFOEN (SMARTCARD_HandleTypeDef *hsmartcard)
Send an amount of data in non-blocking mode.
static void | SMARTCARD_EndTransmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Wrap up transmission in non-blocking mode.
static void | SMARTCARD_RxISR (SMARTCARD_HandleTypeDef *hsmartcard)
Receive an amount of data in non-blocking mode.
static void | SMARTCARD_RxISR_FIFOEN (SMARTCARD_HandleTypeDef *hsmartcard)
Receive an amount of data in non-blocking mode.

Function Documentation

static void SMARTCARD_AdvFeatureConfig ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Configure the SMARTCARD associated USART peripheral advanced features.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2408 of file stm32wbxx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::AdvancedInit, SMARTCARD_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, SMARTCARD_AdvFeatureInitTypeDef::DataInvert, SMARTCARD_AdvFeatureInitTypeDef::DMADisableonRxError, __SMARTCARD_HandleTypeDef::Instance, IS_SMARTCARD_ADVFEATURE_DATAINV, IS_SMARTCARD_ADVFEATURE_DMAONRXERROR, IS_SMARTCARD_ADVFEATURE_INIT, IS_SMARTCARD_ADVFEATURE_MSBFIRST, IS_SMARTCARD_ADVFEATURE_RXINV, IS_SMARTCARD_ADVFEATURE_SWAP, IS_SMARTCARD_ADVFEATURE_TXINV, IS_SMARTCARD_OVERRUN, SMARTCARD_AdvFeatureInitTypeDef::MSBFirst, SMARTCARD_AdvFeatureInitTypeDef::OverrunDisable, SMARTCARD_AdvFeatureInitTypeDef::RxPinLevelInvert, SMARTCARD_ADVFEATURE_DATAINVERT_INIT, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT, SMARTCARD_ADVFEATURE_MSBFIRST_INIT, SMARTCARD_ADVFEATURE_RXINVERT_INIT, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT, SMARTCARD_ADVFEATURE_SWAP_INIT, SMARTCARD_ADVFEATURE_TXINVERT_INIT, SMARTCARD_AdvFeatureInitTypeDef::Swap, and SMARTCARD_AdvFeatureInitTypeDef::TxPinLevelInvert.

Referenced by HAL_SMARTCARD_Init().

static HAL_StatusTypeDef SMARTCARD_CheckIdleState ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Check the SMARTCARD Idle State.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 2470 of file stm32wbxx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_GetTick(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::RxState, SMARTCARD_TEACK_REACK_TIMEOUT, and SMARTCARD_WaitOnFlagUntilTimeout().

Referenced by HAL_SMARTCARD_Init().

static void SMARTCARD_DMAAbortOnError ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2678 of file stm32wbxx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::ErrorCallback, HAL_SMARTCARD_ErrorCallback(), __DMA_HandleTypeDef::Parent, __SMARTCARD_HandleTypeDef::RxXferCount, and __SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_IRQHandler().

static void SMARTCARD_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD communication error callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2638 of file stm32wbxx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::ErrorCallback, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_ERROR_DMA, HAL_SMARTCARD_ErrorCallback(), HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_BUSY_TX, __SMARTCARD_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_EndRxTransfer(), SMARTCARD_EndTxTransfer(), and __SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_Receive_DMA(), and HAL_SMARTCARD_Transmit_DMA().

static void SMARTCARD_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD receive process complete callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2607 of file stm32wbxx_hal_smartcard.c.

References HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, __SMARTCARD_HandleTypeDef::RxCpltCallback, __SMARTCARD_HandleTypeDef::RxState, and __SMARTCARD_HandleTypeDef::RxXferCount.

Referenced by HAL_SMARTCARD_Receive_DMA().

static void SMARTCARD_DMARxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Tx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2748 of file stm32wbxx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::AbortCpltCallback, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_AbortCpltCallback(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmarx, __SMARTCARD_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Parent, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, __SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_SMARTCARD_Abort_IT().

static void SMARTCARD_DMARxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2824 of file stm32wbxx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::AbortReceiveCpltCallback, HAL_SMARTCARD_AbortReceiveCpltCallback(), HAL_SMARTCARD_STATE_READY, __DMA_HandleTypeDef::Parent, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, and SMARTCARD_CLEAR_RTOF.

Referenced by HAL_SMARTCARD_AbortReceive_IT().

static void SMARTCARD_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD transmit process complete callback.

Parameters:
hdma Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2588 of file stm32wbxx_hal_smartcard.c.

References __HAL_SMARTCARD_ENABLE_IT, __SMARTCARD_HandleTypeDef::AdvancedInit, __SMARTCARD_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, SMARTCARD_AdvFeatureInitTypeDef::TxCompletionIndication, and __SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_Transmit_DMA().

static void SMARTCARD_DMATxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Rx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2701 of file stm32wbxx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::AbortCpltCallback, __SMARTCARD_HandleTypeDef::ErrorCode, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_AbortCpltCallback(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::hdmarx, __SMARTCARD_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Parent, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_CLEAR_EOBF, SMARTCARD_CLEAR_FEF, SMARTCARD_CLEAR_NEF, SMARTCARD_CLEAR_OREF, SMARTCARD_CLEAR_PEF, SMARTCARD_CLEAR_RTOF, __SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_SMARTCARD_Abort_IT().

static void SMARTCARD_DMATxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2795 of file stm32wbxx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, __SMARTCARD_HandleTypeDef::AbortTransmitCpltCallback, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_AbortTransmitCpltCallback(), HAL_SMARTCARD_STATE_READY, __DMA_HandleTypeDef::Parent, SMARTCARD_CLEAR_FEF, and __SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_AbortTransmit_IT().

static void SMARTCARD_EndRxTransfer ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2571 of file stm32wbxx_hal_smartcard.c.

References HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, and __SMARTCARD_HandleTypeDef::RxState.

Referenced by HAL_SMARTCARD_IRQHandler(), and SMARTCARD_DMAError().

static void SMARTCARD_EndTransmit_IT ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Wrap up transmission in non-blocking mode.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2922 of file stm32wbxx_hal_smartcard.c.

References __HAL_SMARTCARD_DISABLE_IT, __SMARTCARD_HandleTypeDef::AdvancedInit, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_READY, HAL_SMARTCARD_TxCpltCallback(), __SMARTCARD_HandleTypeDef::Init, __SMARTCARD_HandleTypeDef::Instance, SMARTCARD_InitTypeDef::Mode, __SMARTCARD_HandleTypeDef::RxState, SMARTCARD_MODE_TX_RX, SMARTCARD_AdvFeatureInitTypeDef::TxCompletionIndication, __SMARTCARD_HandleTypeDef::TxCpltCallback, and __SMARTCARD_HandleTypeDef::TxISR.

Referenced by HAL_SMARTCARD_IRQHandler().

static void SMARTCARD_EndTxTransfer ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2554 of file stm32wbxx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_READY, and __SMARTCARD_HandleTypeDef::Instance.

Referenced by HAL_SMARTCARD_IRQHandler(), and SMARTCARD_DMAError().

void SMARTCARD_InitCallbacksToDefault ( SMARTCARD_HandleTypeDef * hsmartcard )

Initialize the callbacks to their default values.

Parameters:
hsmartcard SMARTCARD handle.
Return values:
none

Definition at line 2263 of file stm32wbxx_hal_smartcard.c.

References __SMARTCARD_HandleTypeDef::AbortCpltCallback, __SMARTCARD_HandleTypeDef::AbortReceiveCpltCallback, __SMARTCARD_HandleTypeDef::AbortTransmitCpltCallback, __SMARTCARD_HandleTypeDef::ErrorCallback, HAL_SMARTCARD_AbortCpltCallback(), HAL_SMARTCARD_AbortReceiveCpltCallback(), HAL_SMARTCARD_AbortTransmitCpltCallback(), HAL_SMARTCARD_ErrorCallback(), HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARDEx_RxFifoFullCallback(), HAL_SMARTCARDEx_TxFifoEmptyCallback(), __SMARTCARD_HandleTypeDef::RxCpltCallback, __SMARTCARD_HandleTypeDef::RxFifoFullCallback, __SMARTCARD_HandleTypeDef::TxCpltCallback, and __SMARTCARD_HandleTypeDef::TxFifoEmptyCallback.

Referenced by HAL_SMARTCARD_Init().

static void SMARTCARD_RxISR ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Receive an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_SMARTCARD_Receive_IT() and when the FIFO mode is disabled.
Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2968 of file stm32wbxx_hal_smartcard.c.

References __HAL_SMARTCARD_SEND_REQ, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::pRxBuffPtr, __SMARTCARD_HandleTypeDef::RxCpltCallback, __SMARTCARD_HandleTypeDef::RxISR, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, and SMARTCARD_RXDATA_FLUSH_REQUEST.

Referenced by HAL_SMARTCARD_Receive_IT(), and SMARTCARD_RxISR_FIFOEN().

static void SMARTCARD_RxISR_FIFOEN ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Receive an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_SMARTCARD_Receive_IT() and when the FIFO mode is enabled.
Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 3021 of file stm32wbxx_hal_smartcard.c.

References __HAL_SMARTCARD_SEND_REQ, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::NbRxDataToProcess, __SMARTCARD_HandleTypeDef::pRxBuffPtr, __SMARTCARD_HandleTypeDef::RxCpltCallback, __SMARTCARD_HandleTypeDef::RxISR, __SMARTCARD_HandleTypeDef::RxState, __SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_RXDATA_FLUSH_REQUEST, and SMARTCARD_RxISR().

Referenced by HAL_SMARTCARD_Receive_IT().

static HAL_StatusTypeDef SMARTCARD_SetConfig ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Configure the SMARTCARD associated USART peripheral.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 2284 of file stm32wbxx_hal_smartcard.c.

References assert_param, SMARTCARD_InitTypeDef::AutoRetryCount, SMARTCARD_InitTypeDef::BaudRate, SMARTCARD_InitTypeDef::BlockLength, SMARTCARD_InitTypeDef::CLKLastBit, SMARTCARD_InitTypeDef::CLKPhase, SMARTCARD_InitTypeDef::CLKPolarity, SMARTCARD_InitTypeDef::ClockPrescaler, __SMARTCARD_HandleTypeDef::FifoMode, SMARTCARD_InitTypeDef::GuardTime, HAL_RCC_GetPCLK2Freq(), HAL_RCC_GetSysClockFreq(), HSI_VALUE, __SMARTCARD_HandleTypeDef::Init, __SMARTCARD_HandleTypeDef::Instance, IS_SMARTCARD_AUTORETRY_COUNT, IS_SMARTCARD_BAUDRATE, IS_SMARTCARD_CLOCKPRESCALER, IS_SMARTCARD_LASTBIT, IS_SMARTCARD_MODE, IS_SMARTCARD_NACK, IS_SMARTCARD_ONE_BIT_SAMPLE, IS_SMARTCARD_PARITY, IS_SMARTCARD_PHASE, IS_SMARTCARD_POLARITY, IS_SMARTCARD_STOPBITS, IS_SMARTCARD_TIMEOUT, IS_SMARTCARD_TIMEOUT_VALUE, IS_SMARTCARD_WORD_LENGTH, LSE_VALUE, SMARTCARD_InitTypeDef::Mode, SMARTCARD_InitTypeDef::NACKEnable, __SMARTCARD_HandleTypeDef::NbRxDataToProcess, __SMARTCARD_HandleTypeDef::NbTxDataToProcess, SMARTCARD_InitTypeDef::OneBitSampling, SMARTCARD_InitTypeDef::Parity, SMARTCARD_InitTypeDef::Prescaler, __SMARTCARD_HandleTypeDef::RxISR, SMARTCARD_CLOCKSOURCE_HSI, SMARTCARD_CLOCKSOURCE_LSE, SMARTCARD_CLOCKSOURCE_PCLK2, SMARTCARD_CLOCKSOURCE_SYSCLK, SMARTCARD_GETCLOCKSOURCE, SMARTCARD_TIMEOUT_ENABLE, SMARTCARD_InitTypeDef::StopBits, SMARTCARD_InitTypeDef::TimeOutEnable, SMARTCARD_InitTypeDef::TimeOutValue, __SMARTCARD_HandleTypeDef::TxISR, USART_BRR_MAX, USART_BRR_MIN, USART_CR1_FIELDS, USART_CR2_FIELDS, USART_CR3_FIELDS, and SMARTCARD_InitTypeDef::WordLength.

Referenced by HAL_SMARTCARD_Init().

static void SMARTCARD_TxISR ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Send an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_SMARTCARD_Transmit_IT() and when the FIFO mode is disabled.
Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2854 of file stm32wbxx_hal_smartcard.c.

References __HAL_SMARTCARD_ENABLE_IT, __SMARTCARD_HandleTypeDef::AdvancedInit, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY_TX, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::pTxBuffPtr, SMARTCARD_AdvFeatureInitTypeDef::TxCompletionIndication, and __SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_Transmit_IT().

static void SMARTCARD_TxISR_FIFOEN ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Send an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_SMARTCARD_Transmit_IT() and when the FIFO mode is enabled.
Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 2885 of file stm32wbxx_hal_smartcard.c.

References __HAL_SMARTCARD_ENABLE_IT, __SMARTCARD_HandleTypeDef::AdvancedInit, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY_TX, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::NbTxDataToProcess, __SMARTCARD_HandleTypeDef::pTxBuffPtr, SMARTCARD_AdvFeatureInitTypeDef::TxCompletionIndication, and __SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_Transmit_IT().

static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Tickstart,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle SMARTCARD Communication Timeout.

Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Flag | Specifies the SMARTCARD flag to check.
Status | The new Flag status (SET or RESET).
Tickstart | Tick start value
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 2521 of file stm32wbxx_hal_smartcard.c.

References __HAL_SMARTCARD_GET_FLAG, __SMARTCARD_HandleTypeDef::gState, HAL_GetTick(), HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, and __SMARTCARD_HandleTypeDef::RxState.

Referenced by HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Transmit(), and SMARTCARD_CheckIdleState().

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMARTCARD Exported Types

Data Structures | Typedefs | Enumerations
SMARTCARD Exported Types
SMARTCARD

Data Structures

struct | SMARTCARD_InitTypeDef
SMARTCARD Init Structure definition. More...
struct | SMARTCARD_AdvFeatureInitTypeDef
SMARTCARD advanced features initalization structure definition. More...
struct | __SMARTCARD_HandleTypeDef
SMARTCARD handle Structure definition. More...

Typedefs

typedef uint32_t | HAL_SMARTCARD_StateTypeDef
HAL SMARTCARD State definition.
typedef struct
__SMARTCARD_HandleTypeDef 		SMARTCARD_HandleTypeDef
SMARTCARD handle Structure definition.
typedef void(* | pSMARTCARD_CallbackTypeDef )(SMARTCARD_HandleTypeDef *hsmartcard)
HAL SMARTCARD Callback pointer definition.

Enumerations

enum HAL_SMARTCARD_CallbackIDTypeDef {
HAL_SMARTCARD_TX_COMPLETE_CB_ID = 0x00U, HAL_SMARTCARD_RX_COMPLETE_CB_ID = 0x01U, HAL_SMARTCARD_ERROR_CB_ID = 0x02U, HAL_SMARTCARD_ABORT_COMPLETE_CB_ID = 0x03U,
HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x04U, HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID = 0x05U, HAL_SMARTCARD_RX_FIFO_FULL_CB_ID = 0x06U, HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID = 0x07U,
HAL_SMARTCARD_MSPINIT_CB_ID = 0x08U, HAL_SMARTCARD_MSPDEINIT_CB_ID = 0x09U
}
HAL SMARTCARD Callback ID enumeration definition. More...
enum SMARTCARD_ClockSourceTypeDef {
SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01, SMARTCARD_CLOCKSOURCE_HSI = 0x02, SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04, SMARTCARD_CLOCKSOURCE_LSE = 0x08,
SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10
}
SMARTCARD clock sources. More...

Typedef Documentation

typedef uint32_t HAL_SMARTCARD_StateTypeDef

HAL SMARTCARD State definition.

Note:
HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState (see SMARTCARD State Code Definition).
  • gState contains SMARTCARD state information related to global Handle management and also information related to Tx operations. gState value coding follow below described bitmap : b7-b6 Error information 00 : No Error 01 : (Not Used) 10 : Timeout 11 : Error b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP not initialized. HAL SMARTCARD Init function already called) b4-b3 (not used) xx : Should be set to 00 b2 Intrinsic process state 0 : Ready 1 : Busy (IP busy with some configuration or internal operations) b1 (not used) x : Should be set to 0 b0 Tx state 0 : Ready (no Tx operation ongoing) 1 : Busy (Tx operation ongoing)
  • RxState contains information related to Rx operations. RxState value coding follow below described bitmap : b7-b6 (not used) xx : Should be set to 00 b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP not initialized) b4-b2 (not used) xxx : Should be set to 000 b1 Rx state 0 : Ready (no Rx operation ongoing) 1 : Busy (Rx operation ongoing) b0 (not used) x : Should be set to 0.

Definition at line 188 of file stm32wbxx_hal_smartcard.h.

typedef void(* pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsmartcard)

HAL SMARTCARD Callback pointer definition.

pointer to an SMARTCARD callback function

Definition at line 287 of file stm32wbxx_hal_smartcard.h.

typedef struct __SMARTCARD_HandleTypeDef SMARTCARD_HandleTypeDef

SMARTCARD handle Structure definition.

Enumeration Type Documentation

enum HAL_SMARTCARD_CallbackIDTypeDef

HAL SMARTCARD Callback ID enumeration definition.

Enumerator:
HAL_SMARTCARD_TX_COMPLETE_CB_ID

SMARTCARD Tx Complete Callback ID

HAL_SMARTCARD_RX_COMPLETE_CB_ID

SMARTCARD Rx Complete Callback ID

HAL_SMARTCARD_ERROR_CB_ID

SMARTCARD Error Callback ID

HAL_SMARTCARD_ABORT_COMPLETE_CB_ID

SMARTCARD Abort Complete Callback ID

HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID

SMARTCARD Abort Transmit Complete Callback ID

HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID

SMARTCARD Abort Receive Complete Callback ID

HAL_SMARTCARD_RX_FIFO_FULL_CB_ID

SMARTCARD Rx Fifo Full Callback ID

HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID

SMARTCARD Tx Fifo Empty Callback ID

HAL_SMARTCARD_MSPINIT_CB_ID

SMARTCARD MspInit callback ID

HAL_SMARTCARD_MSPDEINIT_CB_ID

SMARTCARD MspDeInit callback ID

Definition at line 268 of file stm32wbxx_hal_smartcard.h.

enum SMARTCARD_ClockSourceTypeDef

SMARTCARD clock sources.

Enumerator:
SMARTCARD_CLOCKSOURCE_PCLK2

PCLK2 clock source

SMARTCARD_CLOCKSOURCE_HSI

HSI clock source

SMARTCARD_CLOCKSOURCE_SYSCLK

SYSCLK clock source

SMARTCARD_CLOCKSOURCE_LSE

LSE clock source

SMARTCARD_CLOCKSOURCE_UNDEFINED

undefined clock source

Definition at line 294 of file stm32wbxx_hal_smartcard.h.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMARTCARD_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SMARTCARD_InitTypeDef Struct Reference
SMARTCARD Exported Types

SMARTCARD Init Structure definition. More...

#include <stm32wbxx_hal_smartcard.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | StopBits
uint16_t | Parity
uint16_t | Mode
uint16_t | CLKPolarity
uint16_t | CLKPhase
uint16_t | CLKLastBit
uint16_t | OneBitSampling
uint8_t | Prescaler
uint8_t | GuardTime
uint16_t | NACKEnable
uint32_t | TimeOutEnable
uint32_t | TimeOutValue
uint8_t | BlockLength
uint8_t | AutoRetryCount
uint32_t | ClockPrescaler

Detailed Description

SMARTCARD Init Structure definition.

Definition at line 47 of file stm32wbxx_hal_smartcard.h.

Field Documentation

uint8_t SMARTCARD_InitTypeDef::AutoRetryCount

Specifies the SmartCard auto-retry count (number of retries in receive and transmit mode). When set to 0, retransmission is disabled. Otherwise, its maximum value is 7 (before signalling an error)

Definition at line 103 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::BaudRate

Configures the SmartCard communication baud rate. The baud rate register is computed using the following formula: Baud Rate Register = ((usart_ker_ckpres) / ((hsmartcard->Init.BaudRate))) where usart_ker_ckpres is the USART input clock divided by a prescaler

Definition at line 49 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint8_t SMARTCARD_InitTypeDef::BlockLength

Specifies the SmartCard Block Length in T=1 Reception mode. This parameter can be any value from 0x0 to 0xFF

Definition at line 100 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::CLKLastBit

Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of SMARTCARD Last Bit

Definition at line 75 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::CLKPhase

Specifies the clock transition on which the bit capture is made. This parameter can be a value of SMARTCARD Clock Phase

Definition at line 72 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::CLKPolarity

Specifies the steady state of the serial clock. This parameter can be a value of SMARTCARD Clock Polarity

Definition at line 69 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::ClockPrescaler

Specifies the prescaler value used to divide the USART clock source. This parameter can be a value of Clock Prescaler.

Definition at line 108 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint8_t SMARTCARD_InitTypeDef::GuardTime

Specifies the SmartCard Guard Time applied after stop bits.

Definition at line 87 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::Mode

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of SMARTCARD Transfer Mode

Definition at line 66 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), SMARTCARD_EndTransmit_IT(), and SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::NACKEnable

Specifies whether the SmartCard NACK transmission is enabled in case of parity error. This parameter can be a value of SMARTCARD NACK Enable

Definition at line 89 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::OneBitSampling

Specifies whether a single sample or three samples' majority vote is selected. Selecting the single sample method increases the receiver tolerance to clock deviations. This parameter can be a value of SMARTCARD One Bit Sampling Method.

Definition at line 79 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint16_t SMARTCARD_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of SMARTCARD Parity

Note:
The parity is enabled by default (PCE is forced to 1). Since the WordLength is forced to 8 bits + parity, M is forced to 1 and the parity bit is the 9th bit.

Definition at line 60 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint8_t SMARTCARD_InitTypeDef::Prescaler

Specifies the SmartCard Prescaler. This parameter can be any value from 0x01 to 0x1F. Prescaler value is multiplied by 2 to give the division factor of the source clock frequency

Definition at line 83 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::StopBits

Specifies the number of stop bits. This parameter can be a value of SMARTCARD Number of Stop Bits.

Definition at line 57 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::TimeOutEnable

Specifies whether the receiver timeout is enabled. This parameter can be a value of SMARTCARD Timeout Enable

Definition at line 93 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::TimeOutValue

Specifies the receiver time out value in number of baud blocks: it is used to implement the Character Wait Time (CWT) and Block Wait Time (BWT). It is coded over 24 bits.

Definition at line 96 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARDEx_TimeOut_Config(), and SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter SMARTCARD Word Length can only be set to 9 (8 data + 1 parity bits).

Definition at line 54 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_smartcard.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMARTCARD_AdvFeatureInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SMARTCARD_AdvFeatureInitTypeDef Struct Reference
SMARTCARD Exported Types

SMARTCARD advanced features initalization structure definition. More...

#include <stm32wbxx_hal_smartcard.h>

Data Fields

uint32_t | AdvFeatureInit
uint32_t | TxPinLevelInvert
uint32_t | RxPinLevelInvert
uint32_t | DataInvert
uint32_t | Swap
uint32_t | OverrunDisable
uint32_t | DMADisableonRxError
uint32_t | MSBFirst
uint16_t | TxCompletionIndication

Detailed Description

SMARTCARD advanced features initalization structure definition.

Definition at line 116 of file stm32wbxx_hal_smartcard.h.

Field Documentation

uint32_t SMARTCARD_AdvFeatureInitTypeDef::AdvFeatureInit

Specifies which advanced SMARTCARD features is initialized. Several advanced features may be initialized at the same time. This parameter can be a value of SMARTCARD advanced feature initialization type

Definition at line 118 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init(), and SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::DataInvert

Specifies whether data are inverted (positive/direct logic vs negative/inverted logic). This parameter can be a value of SMARTCARD advanced feature Binary Data inversion

Definition at line 128 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::DMADisableonRxError

Specifies whether the DMA is disabled in case of reception error. This parameter can be a value of SMARTCARD advanced feature DMA Disable on Rx Error

Definition at line 138 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::MSBFirst

Specifies whether MSB is sent first on UART line. This parameter can be a value of SMARTCARD advanced feature MSB first

Definition at line 141 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::OverrunDisable

Specifies whether the reception overrun detection is disabled. This parameter can be a value of SMARTCARD advanced feature Overrun Disable

Definition at line 135 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::RxPinLevelInvert

Specifies whether the RX pin active level is inverted. This parameter can be a value of SMARTCARD advanced feature RX pin active level inversion

Definition at line 125 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::Swap

Specifies whether TX and RX pins are swapped. This parameter can be a value of SMARTCARD advanced feature RX TX pins swap

Definition at line 132 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

uint16_t SMARTCARD_AdvFeatureInitTypeDef::TxCompletionIndication

Specifies which transmission completion indication is used: before (when relevant flag is available) or once guard time period has elapsed. This parameter can be a value of SMARTCARD Transmission Completion Indication.

Definition at line 144 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMATransmitCplt(), SMARTCARD_EndTransmit_IT(), SMARTCARD_TxISR(), and SMARTCARD_TxISR_FIFOEN().

uint32_t SMARTCARD_AdvFeatureInitTypeDef::TxPinLevelInvert

Specifies whether the TX pin active level is inverted. This parameter can be a value of SMARTCARD advanced feature TX pin active level inversion

Definition at line 122 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_smartcard.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: __SMARTCARD_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__SMARTCARD_HandleTypeDef Struct Reference
SMARTCARD Exported Types

SMARTCARD handle Structure definition. More...

#include <stm32wbxx_hal_smartcard.h>

Data Fields

USART_TypeDef * | Instance
SMARTCARD_InitTypeDef Init
SMARTCARD_AdvFeatureInitTypeDef AdvancedInit
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
__IO uint16_t | RxXferCount
uint16_t | NbRxDataToProcess
uint16_t | NbTxDataToProcess
uint32_t | FifoMode
void(* | RxISR )(struct __SMARTCARD_HandleTypeDef *huart)
void(* | TxISR )(struct __SMARTCARD_HandleTypeDef *huart)
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_SMARTCARD_StateTypeDef | gState
__IO HAL_SMARTCARD_StateTypeDef | RxState
uint32_t | ErrorCode
void(* | TxCpltCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)
void(* | RxCpltCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)
void(* | ErrorCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)
void(* | AbortCpltCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)
void(* | AbortTransmitCpltCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)
void(* | AbortReceiveCpltCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)
void(* | RxFifoFullCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)
void(* | TxFifoEmptyCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)
void(* | MspInitCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)
void(* | MspDeInitCallback )(struct __SMARTCARD_HandleTypeDef *hsmartcard)

Detailed Description

SMARTCARD handle Structure definition.

Definition at line 193 of file stm32wbxx_hal_smartcard.h.

Field Documentation

void(* __SMARTCARD_HandleTypeDef::AbortCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Abort Complete Callback

Definition at line 246 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMATxAbortCallback(), and SMARTCARD_InitCallbacksToDefault().

void(* __SMARTCARD_HandleTypeDef::AbortReceiveCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Abort Receive Complete Callback

Definition at line 250 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMARxOnlyAbortCallback(), and SMARTCARD_InitCallbacksToDefault().

void(* __SMARTCARD_HandleTypeDef::AbortTransmitCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Abort Transmit Complete Callback

Definition at line 248 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMATxOnlyAbortCallback(), and SMARTCARD_InitCallbacksToDefault().

SMARTCARD_AdvFeatureInitTypeDef __SMARTCARD_HandleTypeDef::AdvancedInit

SmartCard advanced features initialization parameters

Definition at line 199 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_AdvFeatureConfig(), SMARTCARD_DMATransmitCplt(), SMARTCARD_EndTransmit_IT(), SMARTCARD_TxISR(), and SMARTCARD_TxISR_FIFOEN().

void(* __SMARTCARD_HandleTypeDef::ErrorCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Error Callback

Definition at line 244 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMAAbortOnError(), SMARTCARD_DMAError(), and SMARTCARD_InitCallbacksToDefault().

uint32_t __SMARTCARD_HandleTypeDef::ErrorCode

SmartCard Error code

Definition at line 237 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_GetError(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_CheckIdleState(), SMARTCARD_DMAError(), SMARTCARD_DMARxAbortCallback(), and SMARTCARD_DMATxAbortCallback().

uint32_t __SMARTCARD_HandleTypeDef::FifoMode

Specifies if the FIFO mode will be used. This parameter can be a value of SMARTCARDEx FIFO mode.

Definition at line 217 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_Transmit_IT(), HAL_SMARTCARDEx_DisableFifoMode(), HAL_SMARTCARDEx_EnableFifoMode(), SMARTCARD_SetConfig(), and SMARTCARDEx_SetNbDataToProcess().

__IO HAL_SMARTCARD_StateTypeDef __SMARTCARD_HandleTypeDef::gState

SmartCard state information related to global Handle management and also related to Tx operations. This parameter can be a value of HAL_SMARTCARD_StateTypeDef

Definition at line 230 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_GetState(), HAL_SMARTCARD_Init(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), HAL_SMARTCARD_UnRegisterCallback(), HAL_SMARTCARDEx_DisableFifoMode(), HAL_SMARTCARDEx_DisableReceiverTimeOut(), HAL_SMARTCARDEx_EnableFifoMode(), HAL_SMARTCARDEx_EnableReceiverTimeOut(), HAL_SMARTCARDEx_SetRxFifoThreshold(), HAL_SMARTCARDEx_SetTxFifoThreshold(), SMARTCARD_CheckIdleState(), SMARTCARD_DMAError(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMATxAbortCallback(), SMARTCARD_DMATxOnlyAbortCallback(), SMARTCARD_EndTransmit_IT(), SMARTCARD_EndTxTransfer(), SMARTCARD_RxISR(), SMARTCARD_RxISR_FIFOEN(), SMARTCARD_TxISR(), SMARTCARD_TxISR_FIFOEN(), and SMARTCARD_WaitOnFlagUntilTimeout().

DMA_HandleTypeDef* __SMARTCARD_HandleTypeDef::hdmarx

SmartCard Rx DMA Handle parameters

Definition at line 226 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive_DMA(), SMARTCARD_DMARxAbortCallback(), and SMARTCARD_DMATxAbortCallback().

DMA_HandleTypeDef* __SMARTCARD_HandleTypeDef::hdmatx

SmartCard Tx DMA Handle parameters

Definition at line 224 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Transmit_DMA(), SMARTCARD_DMARxAbortCallback(), and SMARTCARD_DMATxAbortCallback().

SMARTCARD_InitTypeDef __SMARTCARD_HandleTypeDef::Init

SmartCard communication parameters

Definition at line 197 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), HAL_SMARTCARDEx_TimeOut_Config(), SMARTCARD_EndTransmit_IT(), and SMARTCARD_SetConfig().

USART_TypeDef* __SMARTCARD_HandleTypeDef::Instance

USART registers base address

Definition at line 195 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_Init(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), HAL_SMARTCARDEx_BlockLength_Config(), HAL_SMARTCARDEx_DisableFifoMode(), HAL_SMARTCARDEx_DisableReceiverTimeOut(), HAL_SMARTCARDEx_EnableFifoMode(), HAL_SMARTCARDEx_EnableReceiverTimeOut(), HAL_SMARTCARDEx_SetRxFifoThreshold(), HAL_SMARTCARDEx_SetTxFifoThreshold(), HAL_SMARTCARDEx_TimeOut_Config(), SMARTCARD_AdvFeatureConfig(), SMARTCARD_CheckIdleState(), SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_DMATransmitCplt(), SMARTCARD_EndRxTransfer(), SMARTCARD_EndTransmit_IT(), SMARTCARD_EndTxTransfer(), SMARTCARD_RxISR(), SMARTCARD_RxISR_FIFOEN(), SMARTCARD_SetConfig(), SMARTCARD_TxISR(), SMARTCARD_TxISR_FIFOEN(), SMARTCARD_WaitOnFlagUntilTimeout(), and SMARTCARDEx_SetNbDataToProcess().

HAL_LockTypeDef __SMARTCARD_HandleTypeDef::Lock

Locking object

Definition at line 228 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init().

void(* __SMARTCARD_HandleTypeDef::MspDeInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Msp DeInit callback

Definition at line 259 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_RegisterCallback(), and HAL_SMARTCARD_UnRegisterCallback().

void(* __SMARTCARD_HandleTypeDef::MspInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Msp Init callback

Definition at line 257 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init(), HAL_SMARTCARD_RegisterCallback(), and HAL_SMARTCARD_UnRegisterCallback().

uint16_t __SMARTCARD_HandleTypeDef::NbRxDataToProcess

Number of data to process during RX ISR execution

Definition at line 213 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive_IT(), SMARTCARD_RxISR_FIFOEN(), SMARTCARD_SetConfig(), and SMARTCARDEx_SetNbDataToProcess().

uint16_t __SMARTCARD_HandleTypeDef::NbTxDataToProcess

Number of data to process during TX ISR execution

Definition at line 215 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig(), SMARTCARD_TxISR_FIFOEN(), and SMARTCARDEx_SetNbDataToProcess().

uint8_t* __SMARTCARD_HandleTypeDef::pRxBuffPtr

Pointer to SmartCard Rx transfer Buffer

Definition at line 207 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), SMARTCARD_RxISR(), and SMARTCARD_RxISR_FIFOEN().

uint8_t* __SMARTCARD_HandleTypeDef::pTxBuffPtr

Pointer to SmartCard Tx transfer Buffer

Definition at line 201 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_TxISR(), and SMARTCARD_TxISR_FIFOEN().

void(* __SMARTCARD_HandleTypeDef::RxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Rx Complete Callback

Definition at line 242 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_InitCallbacksToDefault(), SMARTCARD_RxISR(), and SMARTCARD_RxISR_FIFOEN().

void(* __SMARTCARD_HandleTypeDef::RxFifoFullCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Rx Fifo Full Callback

Definition at line 252 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_UnRegisterCallback(), and SMARTCARD_InitCallbacksToDefault().

void(* __SMARTCARD_HandleTypeDef::RxISR)(struct __SMARTCARD_HandleTypeDef *huart)

Function pointer on Rx IRQ handler

Definition at line 220 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive_IT(), SMARTCARD_RxISR(), SMARTCARD_RxISR_FIFOEN(), and SMARTCARD_SetConfig().

__IO HAL_SMARTCARD_StateTypeDef __SMARTCARD_HandleTypeDef::RxState

SmartCard state information related to Rx operations. This parameter can be a value of HAL_SMARTCARD_StateTypeDef

Definition at line 234 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_GetState(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), SMARTCARD_CheckIdleState(), SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), SMARTCARD_DMATxAbortCallback(), SMARTCARD_EndRxTransfer(), SMARTCARD_EndTransmit_IT(), SMARTCARD_RxISR(), SMARTCARD_RxISR_FIFOEN(), and SMARTCARD_WaitOnFlagUntilTimeout().

__IO uint16_t __SMARTCARD_HandleTypeDef::RxXferCount

SmartCard Rx Transfer Counter

Definition at line 211 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_IT(), SMARTCARD_DMAAbortOnError(), SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), SMARTCARD_DMATxAbortCallback(), SMARTCARD_RxISR(), and SMARTCARD_RxISR_FIFOEN().

uint16_t __SMARTCARD_HandleTypeDef::RxXferSize

SmartCard Rx Transfer size

Definition at line 209 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), and HAL_SMARTCARD_Receive_IT().

void(* __SMARTCARD_HandleTypeDef::TxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Tx Complete Callback

Definition at line 240 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_UnRegisterCallback(), SMARTCARD_EndTransmit_IT(), and SMARTCARD_InitCallbacksToDefault().

void(* __SMARTCARD_HandleTypeDef::TxFifoEmptyCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard)

SMARTCARD Tx Fifo Empty Callback

Definition at line 254 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_UnRegisterCallback(), and SMARTCARD_InitCallbacksToDefault().

void(* __SMARTCARD_HandleTypeDef::TxISR)(struct __SMARTCARD_HandleTypeDef *huart)

Function pointer on Tx IRQ handler

Definition at line 222 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_EndTransmit_IT(), and SMARTCARD_SetConfig().

__IO uint16_t __SMARTCARD_HandleTypeDef::TxXferCount

SmartCard Tx Transfer Counter

Definition at line 205 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_DMAAbortOnError(), SMARTCARD_DMAError(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMATransmitCplt(), SMARTCARD_DMATxAbortCallback(), SMARTCARD_DMATxOnlyAbortCallback(), SMARTCARD_TxISR(), and SMARTCARD_TxISR_FIFOEN().

uint16_t __SMARTCARD_HandleTypeDef::TxXferSize

SmartCard Tx Transfer size

Definition at line 203 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), and HAL_SMARTCARD_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_smartcard.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMARTCARD State Code Definition

Defines
SMARTCARD State Code Definition
SMARTCARD Exported Constants

Defines

#define | HAL_SMARTCARD_STATE_RESET 0x00000000U
#define | HAL_SMARTCARD_STATE_READY 0x00000020U
#define | HAL_SMARTCARD_STATE_BUSY 0x00000024U
#define | HAL_SMARTCARD_STATE_BUSY_TX 0x00000021U
#define | HAL_SMARTCARD_STATE_BUSY_RX 0x00000022U
#define | HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U
#define | HAL_SMARTCARD_STATE_TIMEOUT 0x000000A0U
#define | HAL_SMARTCARD_STATE_ERROR 0x000000E0U

Define Documentation

#define HAL_SMARTCARD_STATE_BUSY 0x00000024U

an internal process is ongoing Value is allowed for gState only

Definition at line 319 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_Init(), HAL_SMARTCARDEx_DisableFifoMode(), HAL_SMARTCARDEx_DisableReceiverTimeOut(), HAL_SMARTCARDEx_EnableFifoMode(), HAL_SMARTCARDEx_EnableReceiverTimeOut(), HAL_SMARTCARDEx_SetRxFifoThreshold(), and HAL_SMARTCARDEx_SetTxFifoThreshold().

#define HAL_SMARTCARD_STATE_BUSY_RX 0x00000022U

Data Reception process is ongoing Value is allowed for RxState only

Definition at line 323 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), SMARTCARD_DMAError(), SMARTCARD_RxISR(), and SMARTCARD_RxISR_FIFOEN().

#define HAL_SMARTCARD_STATE_BUSY_TX 0x00000021U

Data Transmission process is ongoing Value is allowed for gState only

Definition at line 321 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_DMAError(), SMARTCARD_TxISR(), and SMARTCARD_TxISR_FIFOEN().

#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U

Data Transmission and Reception process is ongoing Not to be used for neither gState nor RxState. Value is result of combination (Or) between gState and RxState values

Definition at line 325 of file stm32wbxx_hal_smartcard.h.

#define HAL_SMARTCARD_STATE_ERROR 0x000000E0U

Error Value is allowed for gState only

Definition at line 330 of file stm32wbxx_hal_smartcard.h.

#define HAL_SMARTCARD_STATE_READY 0x00000020U

Peripheral Initialized and ready for use Value is allowed for gState and RxState

Definition at line 317 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_RegisterCallback(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), HAL_SMARTCARD_UnRegisterCallback(), HAL_SMARTCARDEx_DisableFifoMode(), HAL_SMARTCARDEx_DisableReceiverTimeOut(), HAL_SMARTCARDEx_EnableFifoMode(), HAL_SMARTCARDEx_EnableReceiverTimeOut(), HAL_SMARTCARDEx_SetRxFifoThreshold(), HAL_SMARTCARDEx_SetTxFifoThreshold(), SMARTCARD_CheckIdleState(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), SMARTCARD_DMATxAbortCallback(), SMARTCARD_DMATxOnlyAbortCallback(), SMARTCARD_EndRxTransfer(), SMARTCARD_EndTransmit_IT(), SMARTCARD_EndTxTransfer(), SMARTCARD_RxISR(), SMARTCARD_RxISR_FIFOEN(), and SMARTCARD_WaitOnFlagUntilTimeout().

#define HAL_SMARTCARD_STATE_RESET 0x00000000U

Peripheral is not initialized Value is allowed for gState and RxState

Definition at line 315 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_Init(), HAL_SMARTCARD_RegisterCallback(), and HAL_SMARTCARD_UnRegisterCallback().

#define HAL_SMARTCARD_STATE_TIMEOUT 0x000000A0U

Timeout state Value is allowed for gState only

Definition at line 328 of file stm32wbxx_hal_smartcard.h.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMARTCARD Error Code Definition

Defines
SMARTCARD Error Code Definition
SMARTCARD Exported Constants

Defines

#define | HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_SMARTCARD_ERROR_PE ((uint32_t)0x00000001U)
#define | HAL_SMARTCARD_ERROR_NE ((uint32_t)0x00000002U)
#define | HAL_SMARTCARD_ERROR_FE ((uint32_t)0x00000004U)
#define | HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x00000008U)
#define | HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x00000010U)
#define | HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x00000020U)
#define | HAL_SMARTCARD_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U)

Define Documentation

#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x00000010U)

DMA transfer error

Definition at line 344 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), and SMARTCARD_DMAError().

#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x00000004U)

frame error

Definition at line 342 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U)

Invalid Callback error

Definition at line 347 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_RegisterCallback(), and HAL_SMARTCARD_UnRegisterCallback().

#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x00000002U)

Noise error

Definition at line 341 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00000000U)

No error

Definition at line 339 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_CheckIdleState(), SMARTCARD_DMARxAbortCallback(), and SMARTCARD_DMATxAbortCallback().

#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x00000008U)

Overrun error

Definition at line 343 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x00000001U)

Parity error

Definition at line 340 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x00000020U)

Receiver TimeOut error

Definition at line 345 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMARTCARD Word Length

Defines
SMARTCARD Word Length
SMARTCARD Exported Constants

Defines

#define SMARTCARD_WORDLENGTH_9B USART_CR1_M0

Define Documentation

#define SMARTCARD_WORDLENGTH_9B USART_CR1_M0

SMARTCARD frame length

Definition at line 356 of file stm32wbxx_hal_smartcard.h.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMARTCARD Number of Stop Bits

Defines
SMARTCARD Number of Stop Bits
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_STOPBITS_0_5 USART_CR2_STOP_0
#define | SMARTCARD_STOPBITS_1_5 USART_CR2_STOP

Define Documentation

#define SMARTCARD_STOPBITS_0_5 USART_CR2_STOP_0

SMARTCARD frame with 0.5 stop bit

Definition at line 364 of file stm32wbxx_hal_smartcard.h.

#define SMARTCARD_STOPBITS_1_5 USART_CR2_STOP

SMARTCARD frame with 1.5 stop bits

Definition at line 365 of file stm32wbxx_hal_smartcard.h.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMARTCARD Parity

Defines
SMARTCARD Parity
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_PARITY_EVEN USART_CR1_PCE
#define | SMARTCARD_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Define Documentation

#define SMARTCARD_PARITY_EVEN USART_CR1_PCE

SMARTCARD frame even parity

Definition at line 373 of file stm32wbxx_hal_smartcard.h.

#define SMARTCARD_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

SMARTCARD frame odd parity

Definition at line 374 of file stm32wbxx_hal_smartcard.h.

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STM32WB55xx HAL User Manual: SMARTCARD Transfer Mode

Defines
SMARTCARD Transfer Mode
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_MODE_RX USART_CR1_RE
#define | SMARTCARD_MODE_TX USART_CR1_TE
#define | SMARTCARD_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)

Define Documentation

#define SMARTCARD_MODE_RX USART_CR1_RE

SMARTCARD RX mode

Definition at line 382 of file stm32wbxx_hal_smartcard.h.

#define SMARTCARD_MODE_TX USART_CR1_TE

SMARTCARD TX mode

Definition at line 383 of file stm32wbxx_hal_smartcard.h.

#define SMARTCARD_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)

SMARTCARD RX and TX mode

Definition at line 384 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), and SMARTCARD_EndTransmit_IT().

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STM32WB55xx HAL User Manual: SMARTCARD Clock Polarity

Defines
SMARTCARD Clock Polarity
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_POLARITY_LOW 0x00000000U
#define | SMARTCARD_POLARITY_HIGH USART_CR2_CPOL

Define Documentation

#define SMARTCARD_POLARITY_HIGH USART_CR2_CPOL

SMARTCARD frame high polarity

Definition at line 393 of file stm32wbxx_hal_smartcard.h.

#define SMARTCARD_POLARITY_LOW 0x00000000U

SMARTCARD frame low polarity

Definition at line 392 of file stm32wbxx_hal_smartcard.h.

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STM32WB55xx HAL User Manual: SMARTCARD Clock Phase

Defines
SMARTCARD Clock Phase
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_PHASE_1EDGE 0x00000000U
#define | SMARTCARD_PHASE_2EDGE USART_CR2_CPHA

Define Documentation

#define SMARTCARD_PHASE_1EDGE 0x00000000U

SMARTCARD frame phase on first clock transition

Definition at line 401 of file stm32wbxx_hal_smartcard.h.

#define SMARTCARD_PHASE_2EDGE USART_CR2_CPHA

SMARTCARD frame phase on second clock transition

Definition at line 402 of file stm32wbxx_hal_smartcard.h.

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STM32WB55xx HAL User Manual: SMARTCARD Last Bit

Defines
SMARTCARD Last Bit
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_LASTBIT_DISABLE 0x00000000U
#define | SMARTCARD_LASTBIT_ENABLE USART_CR2_LBCL

Define Documentation

#define SMARTCARD_LASTBIT_DISABLE 0x00000000U

SMARTCARD frame last data bit clock pulse not output to SCLK pin

Definition at line 410 of file stm32wbxx_hal_smartcard.h.

#define SMARTCARD_LASTBIT_ENABLE USART_CR2_LBCL

SMARTCARD frame last data bit clock pulse output to SCLK pin

Definition at line 411 of file stm32wbxx_hal_smartcard.h.

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STM32WB55xx HAL User Manual: SMARTCARD One Bit Sampling Method

Defines
SMARTCARD One Bit Sampling Method
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ONE_BIT_SAMPLE_DISABLE 0x00000000U
#define | SMARTCARD_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT

Define Documentation

#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE 0x00000000U

SMARTCARD frame one-bit sample disabled

Definition at line 419 of file stm32wbxx_hal_smartcard.h.

#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT

SMARTCARD frame one-bit sample enabled

Definition at line 420 of file stm32wbxx_hal_smartcard.h.

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STM32WB55xx HAL User Manual: SMARTCARD NACK Enable

Defines
SMARTCARD NACK Enable
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_NACK_DISABLE 0x00000000U
#define | SMARTCARD_NACK_ENABLE USART_CR3_NACK

Define Documentation

#define SMARTCARD_NACK_DISABLE 0x00000000U

SMARTCARD NACK transmission disabled

Definition at line 429 of file stm32wbxx_hal_smartcard.h.

#define SMARTCARD_NACK_ENABLE USART_CR3_NACK

SMARTCARD NACK transmission enabled

Definition at line 430 of file stm32wbxx_hal_smartcard.h.

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STM32WB55xx HAL User Manual: SMARTCARD Timeout Enable

Defines
SMARTCARD Timeout Enable
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_TIMEOUT_DISABLE 0x00000000U
#define | SMARTCARD_TIMEOUT_ENABLE USART_CR2_RTOEN

Define Documentation

#define SMARTCARD_TIMEOUT_DISABLE 0x00000000U

SMARTCARD receiver timeout disabled

Definition at line 438 of file stm32wbxx_hal_smartcard.h.

#define SMARTCARD_TIMEOUT_ENABLE USART_CR2_RTOEN

SMARTCARD receiver timeout enabled

Definition at line 439 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

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STM32WB55xx HAL User Manual: Clock Prescaler

Defines
Clock Prescaler
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_PRESCALER_DIV1 0x00000000U
#define | SMARTCARD_PRESCALER_DIV2 0x00000001U
#define | SMARTCARD_PRESCALER_DIV4 0x00000002U
#define | SMARTCARD_PRESCALER_DIV6 0x00000003U
#define | SMARTCARD_PRESCALER_DIV8 0x00000004U
#define | SMARTCARD_PRESCALER_DIV10 0x00000005U
#define | SMARTCARD_PRESCALER_DIV12 0x00000006U
#define | SMARTCARD_PRESCALER_DIV16 0x00000007U
#define | SMARTCARD_PRESCALER_DIV32 0x00000008U
#define | SMARTCARD_PRESCALER_DIV64 0x00000009U
#define | SMARTCARD_PRESCALER_DIV128 0x0000000AU
#define | SMARTCARD_PRESCALER_DIV256 0x0000000BU

Define Documentation

#define SMARTCARD_PRESCALER_DIV1 0x00000000U

fclk_pres = fclk

Definition at line 447 of file stm32wbxx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV10 0x00000005U

fclk_pres = fclk/10

Definition at line 452 of file stm32wbxx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV12 0x00000006U

fclk_pres = fclk/12

Definition at line 453 of file stm32wbxx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV128 0x0000000AU

fclk_pres = fclk/128

Definition at line 457 of file stm32wbxx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV16 0x00000007U

fclk_pres = fclk/16

Definition at line 454 of file stm32wbxx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV2 0x00000001U

fclk_pres = fclk/2

Definition at line 448 of file stm32wbxx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV256 0x0000000BU

fclk_pres = fclk/256

Definition at line 458 of file stm32wbxx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV32 0x00000008U

fclk_pres = fclk/32

Definition at line 455 of file stm32wbxx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV4 0x00000002U

fclk_pres = fclk/4

Definition at line 449 of file stm32wbxx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV6 0x00000003U

fclk_pres = fclk/6

Definition at line 450 of file stm32wbxx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV64 0x00000009U

fclk_pres = fclk/64

Definition at line 456 of file stm32wbxx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_DIV8 0x00000004U

fclk_pres = fclk/8

Definition at line 451 of file stm32wbxx_hal_smartcard.h.

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STM32WB55xx HAL User Manual: SMARTCARD advanced feature TX pin active level inversion

Defines
SMARTCARD advanced feature TX pin active level inversion
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_TXINV_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV

Define Documentation

#define SMARTCARD_ADVFEATURE_TXINV_DISABLE 0x00000000U

TX pin active level inversion disable

Definition at line 467 of file stm32wbxx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV

TX pin active level inversion enable

Definition at line 468 of file stm32wbxx_hal_smartcard.h.

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STM32WB55xx HAL User Manual: SMARTCARD advanced feature RX pin active level inversion

Defines
SMARTCARD advanced feature RX pin active level inversion
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_RXINV_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV

Define Documentation

#define SMARTCARD_ADVFEATURE_RXINV_DISABLE 0x00000000U

RX pin active level inversion disable

Definition at line 476 of file stm32wbxx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV

RX pin active level inversion enable

Definition at line 477 of file stm32wbxx_hal_smartcard.h.

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STM32WB55xx HAL User Manual: SMARTCARD advanced feature Binary Data inversion

Defines
SMARTCARD advanced feature Binary Data inversion
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_DATAINV_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV

Define Documentation

#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE 0x00000000U

Binary data inversion disable

Definition at line 485 of file stm32wbxx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV

Binary data inversion enable

Definition at line 486 of file stm32wbxx_hal_smartcard.h.

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STM32WB55xx HAL User Manual: SMARTCARD advanced feature RX TX pins swap

Defines
SMARTCARD advanced feature RX TX pins swap
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_SWAP_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP

Define Documentation

#define SMARTCARD_ADVFEATURE_SWAP_DISABLE 0x00000000U

TX/RX pins swap disable

Definition at line 494 of file stm32wbxx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP

TX/RX pins swap enable

Definition at line 495 of file stm32wbxx_hal_smartcard.h.

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STM32WB55xx HAL User Manual: SMARTCARD advanced feature Overrun Disable

Defines
SMARTCARD advanced feature Overrun Disable
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_OVERRUN_ENABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS

Define Documentation

#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS

RX overrun disable

Definition at line 504 of file stm32wbxx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE 0x00000000U

RX overrun enable

Definition at line 503 of file stm32wbxx_hal_smartcard.h.

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STM32WB55xx HAL User Manual: SMARTCARD advanced feature DMA Disable on Rx Error

Defines
SMARTCARD advanced feature DMA Disable on Rx Error
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U
#define | SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE

Define Documentation

#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE

DMA disable on Reception Error

Definition at line 513 of file stm32wbxx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U

DMA enable on Reception Error

Definition at line 512 of file stm32wbxx_hal_smartcard.h.

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STM32WB55xx HAL User Manual: SMARTCARD advanced feature MSB first

Defines
SMARTCARD advanced feature MSB first
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST

Define Documentation

#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U

Most significant bit sent/received first disable

Definition at line 521 of file stm32wbxx_hal_smartcard.h.

#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST

Most significant bit sent/received first enable

Definition at line 522 of file stm32wbxx_hal_smartcard.h.

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STM32WB55xx HAL User Manual: SMARTCARD Request Parameters

Defines
SMARTCARD Request Parameters
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ
#define | SMARTCARD_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ

Define Documentation

#define SMARTCARD_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ

Receive data flush request

Definition at line 530 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_RxISR(), and SMARTCARD_RxISR_FIFOEN().

#define SMARTCARD_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ

Transmit data flush request

Definition at line 531 of file stm32wbxx_hal_smartcard.h.

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STM32WB55xx HAL User Manual: SMARTCARD interruptions flags mask

Defines
SMARTCARD interruptions flags mask
SMARTCARD Exported Constants

Defines

#define | SMARTCARD_IT_MASK 0x001FU
#define | SMARTCARD_CR_MASK 0x00E0U
#define | SMARTCARD_CR_POS 5U
#define | SMARTCARD_ISR_MASK 0x1F00U
#define | SMARTCARD_ISR_POS 8U

Define Documentation

#define SMARTCARD_CR_MASK 0x00E0U

SMARTCARD control register mask

Definition at line 540 of file stm32wbxx_hal_smartcard.h.

#define SMARTCARD_CR_POS 5U

SMARTCARD control register position

Definition at line 541 of file stm32wbxx_hal_smartcard.h.

#define SMARTCARD_ISR_MASK 0x1F00U

SMARTCARD ISR register mask

Definition at line 542 of file stm32wbxx_hal_smartcard.h.

#define SMARTCARD_ISR_POS 8U

SMARTCARD ISR register position

Definition at line 543 of file stm32wbxx_hal_smartcard.h.

#define SMARTCARD_IT_MASK 0x001FU

SMARTCARD interruptions flags mask

Definition at line 539 of file stm32wbxx_hal_smartcard.h.

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STM32WB55xx HAL User Manual: SMARTCARD Exported Macros

Defines
SMARTCARD Exported Macros
SMARTCARD

Defines

#define | __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)
Reset SMARTCARD handle states.
#define | __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__)
Flush the Smartcard Data registers.
#define | __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified SMARTCARD pending flag.
#define | __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
Clear the SMARTCARD PE pending flag.
#define | __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)
Clear the SMARTCARD FE pending flag.
#define | __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)
Clear the SMARTCARD NE pending flag.
#define | __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)
Clear the SMARTCARD ORE pending flag.
#define | __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
Clear the SMARTCARD IDLE pending flag.
#define | __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified Smartcard flag is set or not.
#define | __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified SmartCard interrupt.
#define | __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified SmartCard interrupt.
#define | __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET)
Check whether the specified SmartCard interrupt has occurred or not.
#define | __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified SmartCard interrupt source is enabled or not.
#define | __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))
Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
#define | __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific SMARTCARD request flag.
#define | __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the SMARTCARD one bit sample method.
#define | __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
Disable the SMARTCARD one bit sample method.
#define | __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable the USART associated to the SMARTCARD Handle.
#define | __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable the USART associated to the SMARTCARD Handle.

Define Documentation

#define __HAL_SMARTCARD_CLEAR_FEFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)

Clear the SMARTCARD FE pending flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 614 of file stm32wbxx_hal_smartcard.h.

#define __HAL_SMARTCARD_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the specified SMARTCARD pending flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__FLAG__ specifies the flag to check. This parameter can be any combination of the following values:
  • SMARTCARD_CLEAR_PEF Parity error clear flag
  • SMARTCARD_CLEAR_FEF Framing error clear flag
  • SMARTCARD_CLEAR_NEF Noise detected clear flag
  • SMARTCARD_CLEAR_OREF OverRun error clear flag
  • SMARTCARD_CLEAR_IDLEF Idle line detected clear flag
  • SMARTCARD_CLEAR_TCF Transmission complete clear flag
  • SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag
  • SMARTCARD_CLEAR_RTOF Receiver timeout clear flag
  • SMARTCARD_CLEAR_EOBF End of block clear flag
  • SMARTCARD_CLEAR_TXFECF TXFIFO empty Clear flag
Return values:
None

Definition at line 601 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), SMARTCARD_DMATxAbortCallback(), and SMARTCARD_DMATxOnlyAbortCallback().

#define __HAL_SMARTCARD_CLEAR_IDLEFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)

Clear the SMARTCARD IDLE pending flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 632 of file stm32wbxx_hal_smartcard.h.

#define __HAL_SMARTCARD_CLEAR_IT | ( | __HANDLE__,
 |  | __IT_CLEAR__
 | ) | ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))

Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__IT_CLEAR__ specifies the interrupt clear register flag that needs to be set to clear the corresponding interrupt. This parameter can be one of the following values:
  • SMARTCARD_CLEAR_PEF Parity error clear flag
  • SMARTCARD_CLEAR_FEF Framing error clear flag
  • SMARTCARD_CLEAR_NEF Noise detected clear flag
  • SMARTCARD_CLEAR_OREF OverRun error clear flag
  • SMARTCARD_CLEAR_IDLEF Idle line detection clear flag
  • SMARTCARD_CLEAR_TXFECF TXFIFO empty Clear Flag
  • SMARTCARD_CLEAR_TCF Transmission complete clear flag
  • SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available)
  • SMARTCARD_CLEAR_RTOF Receiver timeout clear flag
  • SMARTCARD_CLEAR_EOBF End of block clear flag
Return values:
None

Definition at line 779 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define __HAL_SMARTCARD_CLEAR_NEFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)

Clear the SMARTCARD NE pending flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 620 of file stm32wbxx_hal_smartcard.h.

#define __HAL_SMARTCARD_CLEAR_OREFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)

Clear the SMARTCARD ORE pending flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 626 of file stm32wbxx_hal_smartcard.h.

#define __HAL_SMARTCARD_CLEAR_PEFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)

Clear the SMARTCARD PE pending flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 607 of file stm32wbxx_hal_smartcard.h.

#define __HAL_SMARTCARD_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

Disable the USART associated to the SMARTCARD Handle.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 814 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARDEx_DisableFifoMode(), HAL_SMARTCARDEx_EnableFifoMode(), HAL_SMARTCARDEx_SetRxFifoThreshold(), and HAL_SMARTCARDEx_SetTxFifoThreshold().

#define __HAL_SMARTCARD_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
                                                                ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
                                                                ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))

Disable the specified SmartCard interrupt.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__INTERRUPT__ specifies the SMARTCARD interrupt to disable. This parameter can be one of the following values:
  • SMARTCARD_IT_EOB End of block interrupt
  • SMARTCARD_IT_RTO Receive timeout interrupt
  • SMARTCARD_IT_TXE Transmit data register empty interrupt
  • SMARTCARD_IT_TXFNF TX FIFO not full interruption
  • SMARTCARD_IT_TC Transmission complete interrupt
  • SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
  • SMARTCARD_IT_RXNE Receive data register not empty interrupt
  • SMARTCARD_IT_RXFNE RXFIFO not empty interruption
  • SMARTCARD_IT_IDLE Idle line detection interrupt
  • SMARTCARD_IT_PE Parity error interrupt
  • SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
  • SMARTCARD_IT_RXFF RXFIFO full interruption
  • SMARTCARD_IT_TXFE TXFIFO empty interruption
  • SMARTCARD_IT_RXFT RXFIFO threshold reached interruption
  • SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
Return values:
None

Definition at line 708 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_EndTransmit_IT().

#define __HAL_SMARTCARD_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

Enable the USART associated to the SMARTCARD Handle.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 808 of file stm32wbxx_hal_smartcard.h.

#define __HAL_SMARTCARD_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
                                                                ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
                                                                ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))

Enable the specified SmartCard interrupt.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__INTERRUPT__ specifies the SMARTCARD interrupt to enable. This parameter can be one of the following values:
  • SMARTCARD_IT_EOB End of block interrupt
  • SMARTCARD_IT_RTO Receive timeout interrupt
  • SMARTCARD_IT_TXE Transmit data register empty interrupt
  • SMARTCARD_IT_TXFNF TX FIFO not full interruption
  • SMARTCARD_IT_TC Transmission complete interrupt
  • SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
  • SMARTCARD_IT_RXNE Receive data register not empty interrupt
  • SMARTCARD_IT_RXFNE RXFIFO not empty interruption
  • SMARTCARD_IT_IDLE Idle line detection interrupt
  • SMARTCARD_IT_PE Parity error interrupt
  • SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
  • SMARTCARD_IT_RXFF RXFIFO full interruption
  • SMARTCARD_IT_TXFE TXFIFO empty interruption
  • SMARTCARD_IT_RXFT RXFIFO threshold reached interruption
  • SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
Return values:
None

Definition at line 683 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_DMATransmitCplt(), SMARTCARD_TxISR(), and SMARTCARD_TxISR_FIFOEN().

#define __HAL_SMARTCARD_FLUSH_DRREGISTER ( __HANDLE__ )
Value:
do{                                                                              \
      SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
      SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
      } while(0U)

Flush the Smartcard Data registers.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 579 of file stm32wbxx_hal_smartcard.h.

#define __HAL_SMARTCARD_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))

Check whether the specified Smartcard flag is set or not.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • SMARTCARD_FLAG_TCBGT Transmission complete before guard time flag (when flag available)
  • SMARTCARD_FLAG_REACK Receive enable acknowledge flag
  • SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag
  • SMARTCARD_FLAG_BUSY Busy flag
  • SMARTCARD_FLAG_EOBF End of block flag
  • SMARTCARD_FLAG_RTOF Receiver timeout flag
  • SMARTCARD_FLAG_TXE Transmit data register empty flag
  • SMARTCARD_FLAG_TXFNF TXFIFO not full flag
  • SMARTCARD_FLAG_TC Transmission complete flag
  • SMARTCARD_FLAG_RXNE Receive data register not empty flag
  • SMARTCARD_FLAG_RXFNE RXFIFO not empty flag
  • SMARTCARD_FLAG_IDLE Idle line detection flag
  • SMARTCARD_FLAG_ORE Overrun error flag
  • SMARTCARD_FLAG_NE Noise error flag
  • SMARTCARD_FLAG_FE Framing error flag
  • SMARTCARD_FLAG_PE Parity error flag
  • SMARTCARD_FLAG_TXFE TXFIFO Empty flag
  • SMARTCARD_FLAG_RXFF RXFIFO Full flag
  • SMARTCARD_FLAG_RXFT SMARTCARD RXFIFO threshold flag
  • SMARTCARD_FLAG_TXFT SMARTCARD TXFIFO threshold flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 660 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_WaitOnFlagUntilTimeout().

#define __HAL_SMARTCARD_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->ISR & ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET)

Check whether the specified SmartCard interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__INTERRUPT__ specifies the SMARTCARD interrupt to check. This parameter can be one of the following values:
  • SMARTCARD_IT_EOB End of block interrupt
  • SMARTCARD_IT_RTO Receive timeout interrupt
  • SMARTCARD_IT_TXE Transmit data register empty interrupt
  • SMARTCARD_IT_TXFNF TX FIFO not full interruption
  • SMARTCARD_IT_TC Transmission complete interrupt
  • SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
  • SMARTCARD_IT_RXNE Receive data register not empty interrupt
  • SMARTCARD_IT_RXFNE RXFIFO not empty interruption
  • SMARTCARD_IT_IDLE Idle line detection interrupt
  • SMARTCARD_IT_PE Parity error interrupt
  • SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
  • SMARTCARD_IT_RXFF RXFIFO full interruption
  • SMARTCARD_IT_TXFE TXFIFO empty interruption
  • SMARTCARD_IT_RXFT RXFIFO threshold reached interruption
  • SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 734 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define __HAL_SMARTCARD_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \
                                                                    (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
                                                                    (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK)))  != 0U) ? SET : RESET)

Check whether the specified SmartCard interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__INTERRUPT__ specifies the SMARTCARD interrupt source to check. This parameter can be one of the following values:
  • SMARTCARD_IT_EOB End of block interrupt
  • SMARTCARD_IT_RTO Receive timeout interrupt
  • SMARTCARD_IT_TXE Transmit data register empty interrupt
  • SMARTCARD_IT_TXFNF TX FIFO not full interruption
  • SMARTCARD_IT_TC Transmission complete interrupt
  • SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
  • SMARTCARD_IT_RXNE Receive data register not empty interrupt
  • SMARTCARD_IT_RXFNE RXFIFO not empty interruption
  • SMARTCARD_IT_IDLE Idle line detection interrupt
  • SMARTCARD_IT_PE Parity error interrupt
  • SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
  • SMARTCARD_IT_RXFF RXFIFO full interruption
  • SMARTCARD_IT_TXFE TXFIFO empty interruption
  • SMARTCARD_IT_RXFT RXFIFO threshold reached interruption
  • SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 757 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))

Disable the SMARTCARD one bit sample method.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 802 of file stm32wbxx_hal_smartcard.h.

#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)

Enable the SMARTCARD one bit sample method.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Return values:
None

Definition at line 796 of file stm32wbxx_hal_smartcard.h.

#define __HAL_SMARTCARD_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                       \
                                                           (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;      \
                                                           (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;     \
                                                           (__HANDLE__)->MspInitCallback = NULL;                  \
                                                           (__HANDLE__)->MspDeInitCallback = NULL;                \
                                                          } while(0U)

Reset SMARTCARD handle states.

Parameters:
__HANDLE__ SMARTCARD handle.
Return values:
None

Definition at line 562 of file stm32wbxx_hal_smartcard.h.

#define __HAL_SMARTCARD_SEND_REQ | ( | __HANDLE__,
 |  | __REQ__
 | ) | ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))

Set a specific SMARTCARD request flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
__REQ__ specifies the request flag to set This parameter can be one of the following values:
  • SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request
  • SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request
Return values:
None

Definition at line 790 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_RxISR(), and SMARTCARD_RxISR_FIFOEN().

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMARTCARD Private Macros

Defines
SMARTCARD Private Macros
SMARTCARD

Defines

#define | SMARTCARD_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the SMARTCARD clock source.
#define | IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4000001U)
Check the Baud rate range.
#define | IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU)
Check the block length range.
#define | IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
Check the receiver timeout value.
#define | IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7U)
Check the SMARTCARD autoretry counter value.
#define | IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
Ensure that SMARTCARD frame length is valid.
#define | IS_SMARTCARD_STOPBITS(__STOPBITS__)
Ensure that SMARTCARD frame number of stop bits is valid.
#define | IS_SMARTCARD_PARITY(__PARITY__)
Ensure that SMARTCARD frame parity is valid.
#define | IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & 0xFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
Ensure that SMARTCARD communication mode is valid.
#define | IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
Ensure that SMARTCARD frame polarity is valid.
#define | IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
Ensure that SMARTCARD frame phase is valid.
#define | IS_SMARTCARD_LASTBIT(__LASTBIT__)
Ensure that SMARTCARD frame last bit clock pulse setting is valid.
#define | IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that SMARTCARD frame sampling is valid.
#define | IS_SMARTCARD_NACK(__NACK__)
Ensure that SMARTCARD NACK transmission setting is valid.
#define | IS_SMARTCARD_TIMEOUT(__TIMEOUT__)
Ensure that SMARTCARD receiver timeout setting is valid.
#define | IS_SMARTCARD_CLOCKPRESCALER(__CLOCKPRESCALER__)
Ensure that SMARTCARD clock Prescaler is valid.
#define | IS_SMARTCARD_ADVFEATURE_INIT(__INIT__)
Ensure that SMARTCARD advanced features initialization is valid.
#define | IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__)
Ensure that SMARTCARD frame TX inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__)
Ensure that SMARTCARD frame RX inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__)
Ensure that SMARTCARD frame data inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__)
Ensure that SMARTCARD frame RX/TX pins swap setting is valid.
#define | IS_SMARTCARD_OVERRUN(__OVERRUN__)
Ensure that SMARTCARD frame overrun setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__)
Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__)
Ensure that SMARTCARD frame MSB first setting is valid.
#define | IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__)
Ensure that SMARTCARD request parameter is valid.

Define Documentation

#define IS_SMARTCARD_ADVFEATURE_DATAINV ( __DATAINV__ )
Value:
(((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \
                                                      ((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))

Ensure that SMARTCARD frame data inversion setting is valid.

Parameters:
__DATAINV__ SMARTCARD frame data inversion setting.
Return values:
SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)

Definition at line 1017 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR ( __DMA__ )
Value:
(((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \
                                                       ((__DMA__) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))

Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.

Parameters:
__DMA__ SMARTCARD DMA enabling or disabling on error setting.
Return values:
SET (__DMA__ is valid) or RESET (__DMA__ is invalid)

Definition at line 1041 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_INIT ( __INIT__ )
Value:
((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT                | \
                                                               SMARTCARD_ADVFEATURE_TXINVERT_INIT          | \
                                                               SMARTCARD_ADVFEATURE_RXINVERT_INIT          | \
                                                               SMARTCARD_ADVFEATURE_DATAINVERT_INIT        | \
                                                               SMARTCARD_ADVFEATURE_SWAP_INIT              | \
                                                               SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
                                                               SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \
                                                               SMARTCARD_ADVFEATURE_MSBFIRST_INIT))

Ensure that SMARTCARD advanced features initialization is valid.

Parameters:
__INIT__ SMARTCARD advanced features initialization.
Return values:
SET (__INIT__ is valid) or RESET (__INIT__ is invalid)

Definition at line 987 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_MSBFIRST ( __MSBFIRST__ )
Value:
(((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \
                                                        ((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))

Ensure that SMARTCARD frame MSB first setting is valid.

Parameters:
__MSBFIRST__ SMARTCARD frame MSB first setting.
Return values:
SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)

Definition at line 1049 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_RXINV ( __RXINV__ )
Value:
(((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \
                                                  ((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))

Ensure that SMARTCARD frame RX inversion setting is valid.

Parameters:
__RXINV__ SMARTCARD frame RX inversion setting.
Return values:
SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)

Definition at line 1009 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_SWAP ( __SWAP__ )
Value:
(((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \
                                                ((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))

Ensure that SMARTCARD frame RX/TX pins swap setting is valid.

Parameters:
__SWAP__ SMARTCARD frame RX/TX pins swap setting.
Return values:
SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)

Definition at line 1025 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_ADVFEATURE_TXINV ( __TXINV__ )
Value:
(((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \
                                                  ((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))

Ensure that SMARTCARD frame TX inversion setting is valid.

Parameters:
__TXINV__ SMARTCARD frame TX inversion setting.
Return values:
SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)

Definition at line 1001 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_AUTORETRY_COUNT ( __COUNT__ ) ((__COUNT__) <= 0x7U)

Check the SMARTCARD autoretry counter value.

Note:
The maximum number of retransmissions is 0x7.
Parameters:
__COUNT__ number of retransmissions.
Return values:
Test result (TRUE or FALSE)

Definition at line 886 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_BAUDRATE ( __BAUDRATE__ ) ((__BAUDRATE__) < 4000001U)

Check the Baud rate range.

Note:
The maximum Baud Rate is derived from the maximum clock on WB (64 MHz) divided by the oversampling used on the SMARTCARD (i.e. 16).
Parameters:
__BAUDRATE__ Baud rate set by the configuration function.
Return values:
Test result (TRUE or FALSE)

Definition at line 865 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_BLOCKLENGTH ( __LENGTH__ ) ((__LENGTH__) <= 0xFFU)

Check the block length range.

Note:
The maximum SMARTCARD block length is 0xFF.
Parameters:
__LENGTH__ block length.
Return values:
Test result (TRUE or FALSE)

Definition at line 872 of file stm32wbxx_hal_smartcard.h.

#define IS_SMARTCARD_CLOCKPRESCALER ( __CLOCKPRESCALER__ )
Value:
(((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV1) || \
              ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV2)   || \
              ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV4)   || \
              ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV6)   || \
              ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV8)   || \
              ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV10)  || \
              ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV12)  || \
              ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV16)  || \
              ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV32)  || \
              ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV64)  || \
              ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV128) || \
              ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV256))

Ensure that SMARTCARD clock Prescaler is valid.

Parameters:
__CLOCKPRESCALER__ SMARTCARD clock Prescaler value.
Return values:
SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)

Definition at line 969 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_LASTBIT ( __LASTBIT__ )
Value:
(((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \
                                           ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE))

Ensure that SMARTCARD frame last bit clock pulse setting is valid.

Parameters:
__LASTBIT__ SMARTCARD frame last bit clock pulse setting.
Return values:
SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)

Definition at line 937 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_MODE ( __MODE__ ) ((((__MODE__) & 0xFFF3U) == 0x00U) && ((__MODE__) != 0x00U))

Ensure that SMARTCARD communication mode is valid.

Parameters:
__MODE__ SMARTCARD communication mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 916 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_NACK ( __NACK__ )
Value:
(((__NACK__) == SMARTCARD_NACK_ENABLE) || \
                                     ((__NACK__) == SMARTCARD_NACK_DISABLE))

Ensure that SMARTCARD NACK transmission setting is valid.

Parameters:
__NACK__ SMARTCARD NACK transmission setting.
Return values:
SET (__NACK__ is valid) or RESET (__NACK__ is invalid)

Definition at line 953 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_ONE_BIT_SAMPLE ( __ONEBIT__ )
Value:
(((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \
                                                 ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE))

Ensure that SMARTCARD frame sampling is valid.

Parameters:
__ONEBIT__ SMARTCARD frame sampling.
Return values:
SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)

Definition at line 945 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_OVERRUN ( __OVERRUN__ )
Value:
(((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \
                                           ((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))

Ensure that SMARTCARD frame overrun setting is valid.

Parameters:
__OVERRUN__ SMARTCARD frame overrun setting.
Return values:
SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)

Definition at line 1033 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define IS_SMARTCARD_PARITY ( __PARITY__ )
Value:
(((__PARITY__) == SMARTCARD_PARITY_EVEN) || \
                                         ((__PARITY__) == SMARTCARD_PARITY_ODD))

Ensure that SMARTCARD frame parity is valid.

Parameters:
__PARITY__ SMARTCARD frame parity.
Return values:
SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)

Definition at line 908 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_PHASE ( __CPHA__ ) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))

Ensure that SMARTCARD frame phase is valid.

Parameters:
__CPHA__ SMARTCARD frame phase.
Return values:
SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)

Definition at line 930 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_POLARITY ( __CPOL__ ) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))

Ensure that SMARTCARD frame polarity is valid.

Parameters:
__CPOL__ SMARTCARD frame polarity.
Return values:
SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)

Definition at line 923 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_REQUEST_PARAMETER ( __PARAM__ )
Value:
(((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \
                                                   ((__PARAM__) == SMARTCARD_TXDATA_FLUSH_REQUEST))

Ensure that SMARTCARD request parameter is valid.

Parameters:
__PARAM__ SMARTCARD request parameter.
Return values:
SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)

Definition at line 1057 of file stm32wbxx_hal_smartcard.h.

#define IS_SMARTCARD_STOPBITS ( __STOPBITS__ )
Value:
(((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\
                                             ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5))

Ensure that SMARTCARD frame number of stop bits is valid.

Parameters:
__STOPBITS__ SMARTCARD frame number of stop bits.
Return values:
SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)

Definition at line 900 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_TIMEOUT ( __TIMEOUT__ )
Value:
(((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \
                                           ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE))

Ensure that SMARTCARD receiver timeout setting is valid.

Parameters:
__TIMEOUT__ SMARTCARD receiver timeout setting.
Return values:
SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)

Definition at line 961 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_TIMEOUT_VALUE ( __TIMEOUTVALUE__ ) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)

Check the receiver timeout value.

Note:
The maximum SMARTCARD receiver timeout value is 0xFFFFFF.
Parameters:
__TIMEOUTVALUE__ receiver timeout value.
Return values:
Test result (TRUE or FALSE)

Definition at line 879 of file stm32wbxx_hal_smartcard.h.

Referenced by HAL_SMARTCARDEx_TimeOut_Config(), and SMARTCARD_SetConfig().

#define IS_SMARTCARD_WORD_LENGTH ( __LENGTH__ ) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)

Ensure that SMARTCARD frame length is valid.

Parameters:
__LENGTH__ SMARTCARD frame length.
Return values:
SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

Definition at line 893 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define SMARTCARD_GETCLOCKSOURCE | ( | __HANDLE__,
 |  | __CLOCKSOURCE__
 | ) |
Value:
do {                                                         \
    if((__HANDLE__)->Instance == USART1)                       \
    {                                                          \
       switch(__HAL_RCC_GET_USART1_SOURCE())                   \
       {                                                       \
        case RCC_USART1CLKSOURCE_PCLK2:                        \
          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2;     \
          break;                                               \
        case RCC_USART1CLKSOURCE_HSI:                          \
          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
          break;                                               \
        case RCC_USART1CLKSOURCE_SYSCLK:                       \
          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;    \
          break;                                               \
        case RCC_USART1CLKSOURCE_LSE:                          \
          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
          break;                                               \
        default:                                               \
          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
          break;                                               \
       }                                                       \
    }                                                          \
    else                                                       \
    {                                                          \
      (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED;     \
    }                                                          \
  } while(0U)

Report the SMARTCARD clock source.

Parameters:
__HANDLE__ | specifies the SMARTCARD Handle.
__CLOCKSOURCE__ | output variable.
Return values:
the SMARTCARD clocking source, written in __CLOCKSOURCE__.

Definition at line 830 of file stm32wbxx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Extended Peripheral Control functions

Functions
Extended Peripheral Control functions
SMARTCARD Extended Exported Functions

Extended control functions. More...

Functions

void | HAL_SMARTCARDEx_BlockLength_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
Update on the fly the SMARTCARD block length in RTOR register.
void | HAL_SMARTCARDEx_TimeOut_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
Update on the fly the receiver timeout value in RTOR register.
HAL_StatusTypeDef | HAL_SMARTCARDEx_EnableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Enable the SMARTCARD receiver timeout feature.
HAL_StatusTypeDef | HAL_SMARTCARDEx_DisableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Disable the SMARTCARD receiver timeout feature.

Detailed Description

Extended control functions.

  ===============================================================================
                      ##### Peripheral Control functions #####
  ===============================================================================
  [..]
  This subsection provides a set of functions allowing to initialize the SMARTCARD.
     (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly
     (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly
     (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature
     (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature

Function Documentation

void HAL_SMARTCARDEx_BlockLength_Config | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint8_t | BlockLength
 | ) |  |

Update on the fly the SMARTCARD block length in RTOR register.

Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
BlockLength | SMARTCARD block length (8-bit long at most)
Return values:
None

Definition at line 100 of file stm32wbxx_hal_smartcard_ex.c.

References __SMARTCARD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut ( SMARTCARD_HandleTypeDef * hsmartcard )

Disable the SMARTCARD receiver timeout feature.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 157 of file stm32wbxx_hal_smartcard_ex.c.

References __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, and __SMARTCARD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut ( SMARTCARD_HandleTypeDef * hsmartcard )

Enable the SMARTCARD receiver timeout feature.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 125 of file stm32wbxx_hal_smartcard_ex.c.

References __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, and __SMARTCARD_HandleTypeDef::Instance.

void HAL_SMARTCARDEx_TimeOut_Config | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint32_t | TimeOutValue
 | ) |  |

Update on the fly the receiver timeout value in RTOR register.

Parameters:
hsmartcard | Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
TimeOutValue | receiver timeout value in number of baud blocks. The timeout value must be less or equal to 0x0FFFFFFFF.
Return values:
None

Definition at line 113 of file stm32wbxx_hal_smartcard_ex.c.

References assert_param, __SMARTCARD_HandleTypeDef::Init, __SMARTCARD_HandleTypeDef::Instance, IS_SMARTCARD_TIMEOUT_VALUE, and SMARTCARD_InitTypeDef::TimeOutValue.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Extended Peripheral IO operation functions

Functions
Extended Peripheral IO operation functions
SMARTCARD Extended Exported Functions

SMARTCARD Transmit and Receive functions. More...

Functions

__weak void | HAL_SMARTCARDEx_RxFifoFullCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD RX Fifo full callback.
__weak void | HAL_SMARTCARDEx_TxFifoEmptyCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD TX Fifo empty callback.

Detailed Description

SMARTCARD Transmit and Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    This subsection provides a set of FIFO mode related callback functions.

    (#) TX/RX Fifos Callbacks:
        (+) HAL_SMARTCARDEx_RxFifoFullCallback()
        (+) HAL_SMARTCARDEx_TxFifoEmptyCallback()

Function Documentation

void HAL_SMARTCARDEx_RxFifoFullCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

SMARTCARD RX Fifo full callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 211 of file stm32wbxx_hal_smartcard_ex.c.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_UnRegisterCallback(), and SMARTCARD_InitCallbacksToDefault().

void HAL_SMARTCARDEx_TxFifoEmptyCallback ( SMARTCARD_HandleTypeDef * hsmartcard )

SMARTCARD TX Fifo empty callback.

Parameters:
hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
None

Definition at line 227 of file stm32wbxx_hal_smartcard_ex.c.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_UnRegisterCallback(), and SMARTCARD_InitCallbacksToDefault().

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Extended Peripheral Peripheral Control functions

Functions
Extended Peripheral Peripheral Control functions
SMARTCARD Extended Exported Functions

SMARTCARD control functions. More...

Functions

HAL_StatusTypeDef | HAL_SMARTCARDEx_EnableFifoMode (SMARTCARD_HandleTypeDef *hsmartcard)
Enable the FIFO mode.
HAL_StatusTypeDef | HAL_SMARTCARDEx_DisableFifoMode (SMARTCARD_HandleTypeDef *hsmartcard)
Disable the FIFO mode.
HAL_StatusTypeDef | HAL_SMARTCARDEx_SetTxFifoThreshold (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
Set the TXFIFO threshold.
HAL_StatusTypeDef | HAL_SMARTCARDEx_SetRxFifoThreshold (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
Set the RXFIFO threshold.

Detailed Description

SMARTCARD control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the SMARTCARD.
     (+) HAL_SMARTCARDEx_EnableFifoMode() API enables the FIFO mode
     (+) HAL_SMARTCARDEx_DisableFifoMode() API disables the FIFO mode
     (+) HAL_SMARTCARDEx_SetTxFifoThreshold() API sets the TX FIFO threshold
     (+) HAL_SMARTCARDEx_SetRxFifoThreshold() API sets the RX FIFO threshold

Function Documentation

HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode ( SMARTCARD_HandleTypeDef * hsmartcard )

Disable the FIFO mode.

Parameters:
hsmartcard SMARTCARD handle.
Return values:
HAL status

Definition at line 304 of file stm32wbxx_hal_smartcard_ex.c.

References __HAL_SMARTCARD_DISABLE, assert_param, __SMARTCARD_HandleTypeDef::FifoMode, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, and SMARTCARD_FIFOMODE_DISABLE.

HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode ( SMARTCARD_HandleTypeDef * hsmartcard )

Enable the FIFO mode.

Parameters:
hsmartcard SMARTCARD handle.
Return values:
HAL status

Definition at line 263 of file stm32wbxx_hal_smartcard_ex.c.

References __HAL_SMARTCARD_DISABLE, assert_param, __SMARTCARD_HandleTypeDef::FifoMode, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, SMARTCARD_FIFOMODE_ENABLE, and SMARTCARDEx_SetNbDataToProcess().

HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint32_t | Threshold
 | ) |  |

Set the RXFIFO threshold.

Parameters:
hsmartcard SMARTCARD handle.
Threshold RX FIFO threshold value This parameter can be one of the following values:
  • SMARTCARD_RXFIFO_THRESHOLD_1_8
  • SMARTCARD_RXFIFO_THRESHOLD_1_4
  • SMARTCARD_RXFIFO_THRESHOLD_1_2
  • SMARTCARD_RXFIFO_THRESHOLD_3_4
  • SMARTCARD_RXFIFO_THRESHOLD_7_8
  • SMARTCARD_RXFIFO_THRESHOLD_8_8
Return values:
HAL status

Definition at line 399 of file stm32wbxx_hal_smartcard_ex.c.

References __HAL_SMARTCARD_DISABLE, assert_param, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, IS_SMARTCARD_RXFIFO_THRESHOLD, and SMARTCARDEx_SetNbDataToProcess().

HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint32_t | Threshold
 | ) |  |

Set the TXFIFO threshold.

Parameters:
hsmartcard SMARTCARD handle.
Threshold TX FIFO threshold value This parameter can be one of the following values:
  • SMARTCARD_TXFIFO_THRESHOLD_1_8
  • SMARTCARD_TXFIFO_THRESHOLD_1_4
  • SMARTCARD_TXFIFO_THRESHOLD_1_2
  • SMARTCARD_TXFIFO_THRESHOLD_3_4
  • SMARTCARD_TXFIFO_THRESHOLD_7_8
  • SMARTCARD_TXFIFO_THRESHOLD_8_8
Return values:
HAL status

Definition at line 350 of file stm32wbxx_hal_smartcard_ex.c.

References __HAL_SMARTCARD_DISABLE, assert_param, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, IS_SMARTCARD_TXFIFO_THRESHOLD, and SMARTCARDEx_SetNbDataToProcess().

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMARTCARDEx_Exported_Functions_Group3

Functions
SMARTCARDEx_Exported_Functions_Group3
SMARTCARD Extended Exported Functions

Functions

HAL_StatusTypeDef | HAL_SMARTCARDEx_EnableFifoMode (SMARTCARD_HandleTypeDef *hsmartcard)
Enable the FIFO mode.
HAL_StatusTypeDef | HAL_SMARTCARDEx_DisableFifoMode (SMARTCARD_HandleTypeDef *hsmartcard)
Disable the FIFO mode.
HAL_StatusTypeDef | HAL_SMARTCARDEx_SetTxFifoThreshold (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
Set the TXFIFO threshold.
HAL_StatusTypeDef | HAL_SMARTCARDEx_SetRxFifoThreshold (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
Set the RXFIFO threshold.

Function Documentation

HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode ( SMARTCARD_HandleTypeDef * hsmartcard )

Disable the FIFO mode.

Parameters:
hsmartcard SMARTCARD handle.
Return values:
HAL status

Definition at line 304 of file stm32wbxx_hal_smartcard_ex.c.

References __HAL_SMARTCARD_DISABLE, assert_param, __SMARTCARD_HandleTypeDef::FifoMode, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, and SMARTCARD_FIFOMODE_DISABLE.

HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode ( SMARTCARD_HandleTypeDef * hsmartcard )

Enable the FIFO mode.

Parameters:
hsmartcard SMARTCARD handle.
Return values:
HAL status

Definition at line 263 of file stm32wbxx_hal_smartcard_ex.c.

References __HAL_SMARTCARD_DISABLE, assert_param, __SMARTCARD_HandleTypeDef::FifoMode, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, SMARTCARD_FIFOMODE_ENABLE, and SMARTCARDEx_SetNbDataToProcess().

HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint32_t | Threshold
 | ) |  |

Set the RXFIFO threshold.

Parameters:
hsmartcard SMARTCARD handle.
Threshold RX FIFO threshold value This parameter can be one of the following values:
  • SMARTCARD_RXFIFO_THRESHOLD_1_8
  • SMARTCARD_RXFIFO_THRESHOLD_1_4
  • SMARTCARD_RXFIFO_THRESHOLD_1_2
  • SMARTCARD_RXFIFO_THRESHOLD_3_4
  • SMARTCARD_RXFIFO_THRESHOLD_7_8
  • SMARTCARD_RXFIFO_THRESHOLD_8_8
Return values:
HAL status

Definition at line 399 of file stm32wbxx_hal_smartcard_ex.c.

References __HAL_SMARTCARD_DISABLE, assert_param, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, IS_SMARTCARD_RXFIFO_THRESHOLD, and SMARTCARDEx_SetNbDataToProcess().

HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold | ( | SMARTCARD_HandleTypeDef * | hsmartcard,
 |  | uint32_t | Threshold
 | ) |  |

Set the TXFIFO threshold.

Parameters:
hsmartcard SMARTCARD handle.
Threshold TX FIFO threshold value This parameter can be one of the following values:
  • SMARTCARD_TXFIFO_THRESHOLD_1_8
  • SMARTCARD_TXFIFO_THRESHOLD_1_4
  • SMARTCARD_TXFIFO_THRESHOLD_1_2
  • SMARTCARD_TXFIFO_THRESHOLD_3_4
  • SMARTCARD_TXFIFO_THRESHOLD_7_8
  • SMARTCARD_TXFIFO_THRESHOLD_8_8
Return values:
HAL status

Definition at line 350 of file stm32wbxx_hal_smartcard_ex.c.

References __HAL_SMARTCARD_DISABLE, assert_param, __SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, __SMARTCARD_HandleTypeDef::Instance, IS_SMARTCARD_TXFIFO_THRESHOLD, and SMARTCARDEx_SetNbDataToProcess().

Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMARTCARD Extended private Functions

Functions
SMARTCARD Extended private Functions
SMARTCARDEx

Functions

static void SMARTCARDEx_SetNbDataToProcess (SMARTCARD_HandleTypeDef *hsmartcard)
Calculate the number of data to process in RX/TX ISR.

Function Documentation

static void SMARTCARDEx_SetNbDataToProcess ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Calculate the number of data to process in RX/TX ISR.

Note:
The RX FIFO depth and the TX FIFO depth is extracted from the USART configuration registers.
Parameters:
hsmartcard SMARTCARD handle.
Return values:
None

Definition at line 454 of file stm32wbxx_hal_smartcard_ex.c.

References __SMARTCARD_HandleTypeDef::FifoMode, __SMARTCARD_HandleTypeDef::Instance, __SMARTCARD_HandleTypeDef::NbRxDataToProcess, __SMARTCARD_HandleTypeDef::NbTxDataToProcess, RX_FIFO_DEPTH, SMARTCARD_FIFOMODE_DISABLE, and TX_FIFO_DEPTH.

Referenced by HAL_SMARTCARDEx_EnableFifoMode(), HAL_SMARTCARDEx_SetRxFifoThreshold(), and HAL_SMARTCARDEx_SetTxFifoThreshold().

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMARTCARD Extended Private Macros

Defines
SMARTCARD Extended Private Macros
SMARTCARDEx

Defines

#define | SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__)
Set the Transmission Completion flag.
#define | SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) : (SMARTCARD_FLAG_TCBGT))
Return the transmission completion flag.
#define | IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__)
Ensure that SMARTCARD frame transmission completion used flag is valid.
#define | IS_SMARTCARD_FIFOMODE_STATE(__STATE__)
Ensure that SMARTCARD FIFO mode is valid.
#define | IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that SMARTCARD TXFIFO threshold level is valid.
#define | IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that SMARTCARD RXFIFO threshold level is valid.

Define Documentation

#define IS_SMARTCARD_FIFOMODE_STATE ( __STATE__ )
Value:
(((__STATE__) == SMARTCARD_FIFOMODE_DISABLE ) || \
                                         ((__STATE__) == SMARTCARD_FIFOMODE_ENABLE))

Ensure that SMARTCARD FIFO mode is valid.

Parameters:
__STATE__ SMARTCARD FIFO mode.
Return values:
SET (__STATE__ is valid) or RESET (__STATE__ is invalid)

Definition at line 242 of file stm32wbxx_hal_smartcard_ex.h.

#define IS_SMARTCARD_RXFIFO_THRESHOLD ( __THRESHOLD__ )
Value:
(((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_8) || \
                                          ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4)             || \
                                          ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2)             || \
                                          ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4)             || \
                                          ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8)             || \
                                          ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8))

Ensure that SMARTCARD RXFIFO threshold level is valid.

Parameters:
__THRESHOLD__ SMARTCARD RXFIFO threshold level.
Return values:
SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)

Definition at line 262 of file stm32wbxx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARDEx_SetRxFifoThreshold().

#define IS_SMARTCARD_TRANSMISSION_COMPLETION ( __TXCOMPLETE__ )
Value:
(((__TXCOMPLETE__) == SMARTCARD_TCBGT) ||\
                                                              ((__TXCOMPLETE__) == SMARTCARD_TC))

Ensure that SMARTCARD frame transmission completion used flag is valid.

Parameters:
__TXCOMPLETE__ SMARTCARD frame transmission completion used flag.
Return values:
SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid)

Definition at line 234 of file stm32wbxx_hal_smartcard_ex.h.

#define IS_SMARTCARD_TXFIFO_THRESHOLD ( __THRESHOLD__ )
Value:
(((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_8) || \
                                          ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4)             || \
                                          ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2)             || \
                                          ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4)             || \
                                          ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8)             || \
                                          ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8))

Ensure that SMARTCARD TXFIFO threshold level is valid.

Parameters:
__THRESHOLD__ SMARTCARD TXFIFO threshold level.
Return values:
SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)

Definition at line 250 of file stm32wbxx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARDEx_SetTxFifoThreshold().

#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG ( __HANDLE__ ) (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) : (SMARTCARD_FLAG_TCBGT))

Return the transmission completion flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Note:
Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag. When TCBGT flag (Transmission Complete Before Guard Time) is not available, TC flag is reported.
Return values:
Transmission completion flag

Definition at line 225 of file stm32wbxx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Transmit().

#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING ( __HANDLE__ )
Value:
do {                                                                                                       \
    if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION))        \
    {                                                                                                        \
     (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC;                                       \
    }                                                                                                        \
    else                                                                                                     \
    {                                                                                                        \
      assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \
    }                                                                                                        \
  } while(0U)

Set the Transmission Completion flag.

Parameters:
__HANDLE__ specifies the SMARTCARD Handle.
Note:
If TCBGT (Transmission Complete Before Guard Time) flag is not available or if AdvancedInit.TxCompletionIndication is not already filled, the latter is forced to SMARTCARD_TC (transmission completion indication when guard time has elapsed).
Return values:
None

Definition at line 206 of file stm32wbxx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Init().

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMARTCARD Transmission Completion Indication

Defines
SMARTCARD Transmission Completion Indication
SMARTCARD Extended Exported Constants

Defines

#define | SMARTCARD_TCBGT SMARTCARD_IT_TCBGT
#define | SMARTCARD_TC SMARTCARD_IT_TC

Define Documentation

#define SMARTCARD_TC SMARTCARD_IT_TC

SMARTCARD transmission complete (flag raised when guard time has elapsed)

Definition at line 50 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_TCBGT SMARTCARD_IT_TCBGT

SMARTCARD transmission complete before guard time

Definition at line 49 of file stm32wbxx_hal_smartcard_ex.h.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMARTCARD advanced feature initialization type

Defines
SMARTCARD advanced feature initialization type
SMARTCARD Extended Exported Constants

Defines

#define | SMARTCARD_ADVFEATURE_NO_INIT 0x00000000U
#define | SMARTCARD_ADVFEATURE_TXINVERT_INIT 0x00000001U
#define | SMARTCARD_ADVFEATURE_RXINVERT_INIT 0x00000002U
#define | SMARTCARD_ADVFEATURE_DATAINVERT_INIT 0x00000004U
#define | SMARTCARD_ADVFEATURE_SWAP_INIT 0x00000008U
#define | SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U
#define | SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U
#define | SMARTCARD_ADVFEATURE_MSBFIRST_INIT 0x00000080U
#define | SMARTCARD_ADVFEATURE_TXCOMPLETION 0x00000100U

Define Documentation

#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT 0x00000004U

Binary data inversion

Definition at line 61 of file stm32wbxx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U

DMA disable on Reception Error

Definition at line 64 of file stm32wbxx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT 0x00000080U

Most significant bit sent/received first

Definition at line 65 of file stm32wbxx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_NO_INIT 0x00000000U

No advanced feature initialization

Definition at line 58 of file stm32wbxx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Init().

#define SMARTCARD_ADVFEATURE_RXINVERT_INIT 0x00000002U

RX pin active level inversion

Definition at line 60 of file stm32wbxx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U

RX overrun disable

Definition at line 63 of file stm32wbxx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_SWAP_INIT 0x00000008U

TX/RX pins swap

Definition at line 62 of file stm32wbxx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

#define SMARTCARD_ADVFEATURE_TXCOMPLETION 0x00000100U

TX completion indication before of after guard time

Definition at line 66 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_ADVFEATURE_TXINVERT_INIT 0x00000001U

TX pin active level inversion

Definition at line 59 of file stm32wbxx_hal_smartcard_ex.h.

Referenced by SMARTCARD_AdvFeatureConfig().

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMARTCARDEx FIFO mode

Defines
SMARTCARDEx FIFO mode
SMARTCARD Extended Exported Constants

SMARTCARD FIFO mode. More...

Defines

#define | SMARTCARD_FIFOMODE_DISABLE 0x00000000U
#define | SMARTCARD_FIFOMODE_ENABLE USART_CR1_FIFOEN

Detailed Description

SMARTCARD FIFO mode.

Define Documentation

#define SMARTCARD_FIFOMODE_DISABLE 0x00000000U

FIFO mode disable

Definition at line 75 of file stm32wbxx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARDEx_DisableFifoMode(), and SMARTCARDEx_SetNbDataToProcess().

#define SMARTCARD_FIFOMODE_ENABLE USART_CR1_FIFOEN

FIFO mode enable

Definition at line 76 of file stm32wbxx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_Transmit_IT(), and HAL_SMARTCARDEx_EnableFifoMode().

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMARTCARDEx TXFIFO threshold level

Defines
SMARTCARDEx TXFIFO threshold level
SMARTCARD Extended Exported Constants

SMARTCARD TXFIFO level. More...

Defines

#define | SMARTCARD_TXFIFO_THRESHOLD_1_8 0x00000000U
#define | SMARTCARD_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0
#define | SMARTCARD_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1
#define | SMARTCARD_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)
#define | SMARTCARD_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2
#define | SMARTCARD_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)

Detailed Description

SMARTCARD TXFIFO level.

Define Documentation

#define SMARTCARD_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1

TXFIFO reaches 1/2 of its depth

Definition at line 87 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0

TXFIFO reaches 1/4 of its depth

Definition at line 86 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_TXFIFO_THRESHOLD_1_8 0x00000000U

TXFIFO reaches 1/8 of its depth

Definition at line 85 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)

TXFIFO reaches 3/4 of its depth

Definition at line 88 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2

TXFIFO reaches 7/8 of its depth

Definition at line 89 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)

TXFIFO becomes empty

Definition at line 90 of file stm32wbxx_hal_smartcard_ex.h.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMARTCARDEx RXFIFO threshold level

Defines
SMARTCARDEx RXFIFO threshold level
SMARTCARD Extended Exported Constants

SMARTCARD RXFIFO level. More...

Defines

#define | SMARTCARD_RXFIFO_THRESHOLD_1_8 0x00000000U
#define | SMARTCARD_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0
#define | SMARTCARD_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1
#define | SMARTCARD_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)
#define | SMARTCARD_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2
#define | SMARTCARD_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)

Detailed Description

SMARTCARD RXFIFO level.

Define Documentation

#define SMARTCARD_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1

RXFIFO FIFO reaches 1/2 of its depth

Definition at line 101 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0

RXFIFO FIFO reaches 1/4 of its depth

Definition at line 100 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_RXFIFO_THRESHOLD_1_8 0x00000000U

RXFIFO FIFO reaches 1/8 of its depth

Definition at line 99 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)

RXFIFO FIFO reaches 3/4 of its depth

Definition at line 102 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2

RXFIFO FIFO reaches 7/8 of its depth

Definition at line 103 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)

RXFIFO FIFO becomes full

Definition at line 104 of file stm32wbxx_hal_smartcard_ex.h.

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STM32WB55xx HAL User Manual: SMARTCARD Flags

Defines
SMARTCARD Flags
SMARTCARD Extended Exported Constants

Elements values convention: 0xXXXX. More...

Defines

#define | SMARTCARD_FLAG_TCBGT USART_ISR_TCBGT
#define | SMARTCARD_FLAG_REACK USART_ISR_REACK
#define | SMARTCARD_FLAG_TEACK USART_ISR_TEACK
#define | SMARTCARD_FLAG_BUSY USART_ISR_BUSY
#define | SMARTCARD_FLAG_EOBF USART_ISR_EOBF
#define | SMARTCARD_FLAG_RTOF USART_ISR_RTOF
#define | SMARTCARD_FLAG_TXE USART_ISR_TXE_TXFNF
#define | SMARTCARD_FLAG_TXFNF USART_ISR_TXE_TXFNF
#define | SMARTCARD_FLAG_TC USART_ISR_TC
#define | SMARTCARD_FLAG_RXNE USART_ISR_RXNE_RXFNE
#define | SMARTCARD_FLAG_RXFNE USART_ISR_RXNE_RXFNE
#define | SMARTCARD_FLAG_IDLE USART_ISR_IDLE
#define | SMARTCARD_FLAG_ORE USART_ISR_ORE
#define | SMARTCARD_FLAG_NE USART_ISR_NE
#define | SMARTCARD_FLAG_FE USART_ISR_FE
#define | SMARTCARD_FLAG_PE USART_ISR_PE
#define | SMARTCARD_FLAG_TXFE USART_ISR_TXFE
#define | SMARTCARD_FLAG_RXFF USART_ISR_RXFF
#define | SMARTCARD_FLAG_RXFT USART_ISR_RXFT
#define | SMARTCARD_FLAG_TXFT USART_ISR_TXFT

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the ISR register

Define Documentation

#define SMARTCARD_FLAG_BUSY USART_ISR_BUSY

SMARTCARD busy flag

Definition at line 117 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_EOBF USART_ISR_EOBF

SMARTCARD end of block flag

Definition at line 118 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_FE USART_ISR_FE

SMARTCARD frame error

Definition at line 128 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_IDLE USART_ISR_IDLE

SMARTCARD idle line detection

Definition at line 125 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_NE USART_ISR_NE

SMARTCARD noise error

Definition at line 127 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_ORE USART_ISR_ORE

SMARTCARD overrun error

Definition at line 126 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_PE USART_ISR_PE

SMARTCARD parity error

Definition at line 129 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_REACK USART_ISR_REACK

SMARTCARD receive enable acknowledge flag

Definition at line 115 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_RTOF USART_ISR_RTOF

SMARTCARD receiver timeout flag

Definition at line 119 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_RXFF USART_ISR_RXFF

SMARTCARD RXFIFO Full flag

Definition at line 131 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_RXFNE USART_ISR_RXNE_RXFNE

SMARTCARD RXFIFO not empty

Definition at line 124 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_RXFT USART_ISR_RXFT

SMARTCARD RXFIFO threshold flag

Definition at line 132 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_RXNE USART_ISR_RXNE_RXFNE

SMARTCARD read data register not empty

Definition at line 123 of file stm32wbxx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Receive().

#define SMARTCARD_FLAG_TC USART_ISR_TC

SMARTCARD transmission complete

Definition at line 122 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_TCBGT USART_ISR_TCBGT

SMARTCARD transmission complete before guard time completion

Definition at line 114 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_TEACK USART_ISR_TEACK

SMARTCARD transmit enable acknowledge flag

Definition at line 116 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_TXE USART_ISR_TXE_TXFNF

SMARTCARD transmit data register empty

Definition at line 120 of file stm32wbxx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Transmit().

#define SMARTCARD_FLAG_TXFE USART_ISR_TXFE

SMARTCARD TXFIFO Empty flag

Definition at line 130 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_TXFNF USART_ISR_TXE_TXFNF

SMARTCARD TXFIFO not full

Definition at line 121 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_FLAG_TXFT USART_ISR_TXFT

SMARTCARD TXFIFO threshold flag

Definition at line 133 of file stm32wbxx_hal_smartcard_ex.h.

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STM32WB55xx HAL User Manual: SMARTCARD Interrupts Definition

Defines
SMARTCARD Interrupts Definition
SMARTCARD Extended Exported Constants

Elements values convention: 000ZZZZZ0XXYYYYYb. More...

Defines

#define | SMARTCARD_IT_PE 0x0028U
#define | SMARTCARD_IT_TXE 0x0727U
#define | SMARTCARD_IT_TXFNF 0x0727U
#define | SMARTCARD_IT_TC 0x0626U
#define | SMARTCARD_IT_RXNE 0x0525U
#define | SMARTCARD_IT_RXFNE 0x0525U
#define | SMARTCARD_IT_IDLE 0x0424U
#define | SMARTCARD_IT_ERR 0x0060U
#define | SMARTCARD_IT_ORE 0x0300U
#define | SMARTCARD_IT_NE 0x0200U
#define | SMARTCARD_IT_FE 0x0100U
#define | SMARTCARD_IT_EOB 0x0C3BU
#define | SMARTCARD_IT_RTO 0x0B3AU
#define | SMARTCARD_IT_TCBGT 0x1978U
#define | SMARTCARD_IT_RXFF 0x183FU
#define | SMARTCARD_IT_TXFE 0x173EU
#define | SMARTCARD_IT_RXFT 0x1A7CU
#define | SMARTCARD_IT_TXFT 0x1B77U

Detailed Description

Elements values convention: 000ZZZZZ0XXYYYYYb.

  • YYYYY : Interrupt source position in the XX register (5 bits)
  • XX : Interrupt source register (2 bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register
  • ZZZZZ : Flag position in the ISR register(5 bits)

Define Documentation

#define SMARTCARD_IT_EOB 0x0C3BU

SMARTCARD end of block interruption

Definition at line 161 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_IT_ERR 0x0060U

SMARTCARD error interruption

Definition at line 156 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_IT_FE 0x0100U

SMARTCARD frame error interruption

Definition at line 159 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_IT_IDLE 0x0424U

SMARTCARD idle line detection interruption

Definition at line 154 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_IT_NE 0x0200U

SMARTCARD noise error interruption

Definition at line 158 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_IT_ORE 0x0300U

SMARTCARD overrun error interruption

Definition at line 157 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_IT_PE 0x0028U

SMARTCARD parity error interruption

Definition at line 148 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_IT_RTO 0x0B3AU

SMARTCARD receiver timeout interruption

Definition at line 162 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_IT_RXFF 0x183FU

SMARTCARD RXFIFO full interruption

Definition at line 165 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_IT_RXFNE 0x0525U

SMARTCARD RXFIFO not empty interruption

Definition at line 153 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_IT_RXFT 0x1A7CU

SMARTCARD RXFIFO threshold reached interruption

Definition at line 167 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_IT_RXNE 0x0525U

SMARTCARD read data register not empty interruption

Definition at line 152 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_IT_TC 0x0626U

SMARTCARD transmission complete interruption

Definition at line 151 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_IT_TCBGT 0x1978U

SMARTCARD transmission complete before guard time completion interruption

Definition at line 163 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_IT_TXE 0x0727U

SMARTCARD transmit data register empty interruption

Definition at line 149 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_IT_TXFE 0x173EU

SMARTCARD TXFIFO empty interruption

Definition at line 166 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_IT_TXFNF 0x0727U

SMARTCARD TX FIFO not full interruption

Definition at line 150 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_IT_TXFT 0x1B77U

SMARTCARD TXFIFO threshold reached interruption

Definition at line 168 of file stm32wbxx_hal_smartcard_ex.h.

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STM32WB55xx HAL User Manual: SMARTCARD Interruption Clear Flags

Defines
SMARTCARD Interruption Clear Flags
SMARTCARD Extended Exported Constants

Defines

#define | SMARTCARD_CLEAR_PEF USART_ICR_PECF
#define | SMARTCARD_CLEAR_FEF USART_ICR_FECF
#define | SMARTCARD_CLEAR_NEF USART_ICR_NECF
#define | SMARTCARD_CLEAR_OREF USART_ICR_ORECF
#define | SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF
#define | SMARTCARD_CLEAR_TXFECF USART_ICR_TXFECF
#define | SMARTCARD_CLEAR_TCF USART_ICR_TCCF
#define | SMARTCARD_CLEAR_TCBGTF USART_ICR_TCBGTCF
#define | SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF
#define | SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF

Define Documentation

#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF

SMARTCARD end of block clear flag

Definition at line 185 of file stm32wbxx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), and SMARTCARD_DMATxAbortCallback().

#define SMARTCARD_CLEAR_FEF USART_ICR_FECF

SMARTCARD framing error clear flag

Definition at line 177 of file stm32wbxx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), SMARTCARD_DMATxAbortCallback(), and SMARTCARD_DMATxOnlyAbortCallback().

#define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF

SMARTCARD idle line detected clear flag

Definition at line 180 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_CLEAR_NEF USART_ICR_NECF

SMARTCARD noise error detected clear flag

Definition at line 178 of file stm32wbxx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), and SMARTCARD_DMATxAbortCallback().

#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF

SMARTCARD overrun error clear flag

Definition at line 179 of file stm32wbxx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), and SMARTCARD_DMATxAbortCallback().

#define SMARTCARD_CLEAR_PEF USART_ICR_PECF

SMARTCARD parity error clear flag

Definition at line 176 of file stm32wbxx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), and SMARTCARD_DMATxAbortCallback().

#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF

SMARTCARD receiver time out clear flag

Definition at line 184 of file stm32wbxx_hal_smartcard_ex.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), and SMARTCARD_DMATxAbortCallback().

#define SMARTCARD_CLEAR_TCBGTF USART_ICR_TCBGTCF

SMARTCARD transmission complete before guard time completion clear flag

Definition at line 183 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF

SMARTCARD transmission complete clear flag

Definition at line 182 of file stm32wbxx_hal_smartcard_ex.h.

#define SMARTCARD_CLEAR_TXFECF USART_ICR_TXFECF

TXFIFO empty Clear Flag

Definition at line 181 of file stm32wbxx_hal_smartcard_ex.h.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMARTCARDEx

Modules | Defines
SMARTCARDEx
STM32WBxx_HAL_Driver

SMARTCARD Extended HAL module driver. More...

Modules

SMARTCARD Extended Exported Functions
SMARTCARD Extended private Functions
SMARTCARD Extended Private Macros
SMARTCARD Extended Exported Constants

Defines

#define | RX_FIFO_DEPTH 8U
#define | TX_FIFO_DEPTH 8U

Detailed Description

SMARTCARD Extended HAL module driver.

Define Documentation

#define RX_FIFO_DEPTH 8U

Definition at line 60 of file stm32wbxx_hal_smartcard_ex.c.

Referenced by SMARTCARDEx_SetNbDataToProcess().

#define TX_FIFO_DEPTH 8U

Definition at line 63 of file stm32wbxx_hal_smartcard_ex.c.

Referenced by SMARTCARDEx_SetNbDataToProcess().

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMBUS Private Constants

Defines
SMBUS Private Constants
SMBUS

Defines

#define | TIMING_CLEAR_MASK (0xF0FFFFFFUL)
#define | HAL_TIMEOUT_ADDR (10000U)
#define | HAL_TIMEOUT_BUSY (25U)
#define | HAL_TIMEOUT_DIR (25U)
#define | HAL_TIMEOUT_RXNE (25U)
#define | HAL_TIMEOUT_STOPF (25U)
#define | HAL_TIMEOUT_TC (25U)
#define | HAL_TIMEOUT_TCR (25U)
#define | HAL_TIMEOUT_TXIS (25U)
#define | MAX_NBYTE_SIZE 255U

Define Documentation

#define HAL_TIMEOUT_ADDR (10000U)

10 s

Definition at line 187 of file stm32wbxx_hal_smbus.c.

#define HAL_TIMEOUT_BUSY (25U)

25 ms

Definition at line 188 of file stm32wbxx_hal_smbus.c.

#define HAL_TIMEOUT_DIR (25U)

25 ms

Definition at line 189 of file stm32wbxx_hal_smbus.c.

#define HAL_TIMEOUT_RXNE (25U)

25 ms

Definition at line 190 of file stm32wbxx_hal_smbus.c.

#define HAL_TIMEOUT_STOPF (25U)

25 ms

Definition at line 191 of file stm32wbxx_hal_smbus.c.

#define HAL_TIMEOUT_TC (25U)

25 ms

Definition at line 192 of file stm32wbxx_hal_smbus.c.

#define HAL_TIMEOUT_TCR (25U)

25 ms

Definition at line 193 of file stm32wbxx_hal_smbus.c.

#define HAL_TIMEOUT_TXIS (25U)

25 ms

Definition at line 194 of file stm32wbxx_hal_smbus.c.

#define MAX_NBYTE_SIZE 255U

Definition at line 195 of file stm32wbxx_hal_smbus.c.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define TIMING_CLEAR_MASK (0xF0FFFFFFUL)

SMBUS TIMING clear register Mask

Definition at line 186 of file stm32wbxx_hal_smbus.c.

Referenced by HAL_SMBUS_Init().

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SMBUS Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SMBUS_Init (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS according to the specified parameters in the SMBUS_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS peripheral.
__weak void | HAL_SMBUS_MspInit (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS MSP.
__weak void | HAL_SMBUS_MspDeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS MSP.
HAL_StatusTypeDef | HAL_SMBUS_ConfigAnalogFilter (SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter)
Configure Analog noise filter.
HAL_StatusTypeDef | HAL_SMBUS_ConfigDigitalFilter (SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter)
Configure Digital noise filter.
HAL_StatusTypeDef | HAL_SMBUS_RegisterCallback (SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback)
Register a User SMBUS Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_UnRegisterCallback (SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID)
Unregister an SMBUS Callback SMBUS callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_RegisterAddrCallback (SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback)
Register the Slave Address Match SMBUS Callback To be used instead of the weak HAL_SMBUS_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_UnRegisterAddrCallback (SMBUS_HandleTypeDef *hsmbus)
UnRegister the Slave Address Match SMBUS Callback Info Ready SMBUS Callback is redirected to the weak HAL_SMBUS_AddrCallback() predefined callback.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          deinitialize the SMBUSx peripheral:

      (+) User must Implement HAL_SMBUS_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, IT and NVIC ).

      (+) Call the function HAL_SMBUS_Init() to configure the selected device with
          the selected configuration:
        (++) Clock Timing
        (++) Bus Timeout
        (++) Analog Filer mode
        (++) Own Address 1
        (++) Addressing mode (Master, Slave)
        (++) Dual Addressing mode
        (++) Own Address 2
        (++) Own Address 2 Mask
        (++) General call mode
        (++) Nostretch mode
        (++) Packet Error Check mode
        (++) Peripheral mode

      (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration
          of the selected SMBUSx peripheral.

      (+) Enable/Disable Analog/Digital filters with HAL_SMBUS_ConfigAnalogFilter() and
          HAL_SMBUS_ConfigDigitalFilter().

Function Documentation

HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint32_t | AnalogFilter
 | ) |  |

Configure Analog noise filter.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
AnalogFilter This parameter can be one of the following values:
  • SMBUS_ANALOGFILTER_ENABLE
  • SMBUS_ANALOGFILTER_DISABLE
Return values:
HAL status

Definition at line 474 of file stm32wbxx_hal_smbus.c.

References __HAL_SMBUS_DISABLE, __HAL_SMBUS_ENABLE, assert_param, HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_READY, __SMBUS_HandleTypeDef::Instance, IS_SMBUS_ANALOG_FILTER, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint32_t | DigitalFilter
 | ) |  |

Configure Digital noise filter.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DigitalFilter | Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
Return values:
HAL status

Definition at line 518 of file stm32wbxx_hal_smbus.c.

References __HAL_SMBUS_DISABLE, __HAL_SMBUS_ENABLE, assert_param, HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_READY, __SMBUS_HandleTypeDef::Instance, IS_SMBUS_DIGITAL_FILTER, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_DeInit ( SMBUS_HandleTypeDef * hsmbus )

DeInitialize the SMBUS peripheral.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 394 of file stm32wbxx_hal_smbus.c.

References __HAL_SMBUS_DISABLE, assert_param, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_MspDeInit(), HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_RESET, __SMBUS_HandleTypeDef::Instance, __SMBUS_HandleTypeDef::MspDeInitCallback, __SMBUS_HandleTypeDef::PreviousState, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_Init ( SMBUS_HandleTypeDef * hsmbus )

Initialize the SMBUS according to the specified parameters in the SMBUS_InitTypeDef and initialize the associated handle.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 274 of file stm32wbxx_hal_smbus.c.

References __HAL_SMBUS_DISABLE, __HAL_SMBUS_ENABLE, __SMBUS_HandleTypeDef::AddrCallback, SMBUS_InitTypeDef::AddressingMode, SMBUS_InitTypeDef::AnalogFilter, assert_param, SMBUS_InitTypeDef::DualAddressMode, __SMBUS_HandleTypeDef::ErrorCallback, __SMBUS_HandleTypeDef::ErrorCode, SMBUS_InitTypeDef::GeneralCallMode, HAL_SMBUS_AddrCallback(), HAL_SMBUS_ERROR_NONE, HAL_SMBUS_ErrorCallback(), HAL_SMBUS_ListenCpltCallback(), HAL_SMBUS_MasterRxCpltCallback(), HAL_SMBUS_MasterTxCpltCallback(), HAL_SMBUS_MspInit(), HAL_SMBUS_SlaveRxCpltCallback(), HAL_SMBUS_SlaveTxCpltCallback(), HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_READY, HAL_SMBUS_STATE_RESET, __SMBUS_HandleTypeDef::Init, __SMBUS_HandleTypeDef::Instance, IS_SMBUS_ADDRESSING_MODE, IS_SMBUS_ANALOG_FILTER, IS_SMBUS_DUAL_ADDRESS, IS_SMBUS_GENERAL_CALL, IS_SMBUS_NO_STRETCH, IS_SMBUS_OWN_ADDRESS1, IS_SMBUS_OWN_ADDRESS2, IS_SMBUS_OWN_ADDRESS2_MASK, IS_SMBUS_PEC, IS_SMBUS_PERIPHERAL_MODE, __SMBUS_HandleTypeDef::ListenCpltCallback, __SMBUS_HandleTypeDef::Lock, __SMBUS_HandleTypeDef::MasterRxCpltCallback, __SMBUS_HandleTypeDef::MasterTxCpltCallback, __SMBUS_HandleTypeDef::MspInitCallback, SMBUS_InitTypeDef::NoStretchMode, SMBUS_InitTypeDef::OwnAddress1, SMBUS_InitTypeDef::OwnAddress2, SMBUS_InitTypeDef::OwnAddress2Masks, SMBUS_InitTypeDef::PacketErrorCheckMode, SMBUS_InitTypeDef::PeripheralMode, __SMBUS_HandleTypeDef::PreviousState, __SMBUS_HandleTypeDef::SlaveRxCpltCallback, __SMBUS_HandleTypeDef::SlaveTxCpltCallback, SMBUS_ADDRESSINGMODE_10BIT, SMBUS_ADDRESSINGMODE_7BIT, SMBUS_PEC_ENABLE, SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE, SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP, SMBUS_InitTypeDef::SMBusTimeout, __SMBUS_HandleTypeDef::State, SMBUS_InitTypeDef::Timing, and TIMING_CLEAR_MASK.

void HAL_SMBUS_MspDeInit ( SMBUS_HandleTypeDef * hsmbus )

DeInitialize the SMBUS MSP.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 455 of file stm32wbxx_hal_smbus.c.

Referenced by HAL_SMBUS_DeInit(), and HAL_SMBUS_UnRegisterCallback().

void HAL_SMBUS_MspInit ( SMBUS_HandleTypeDef * hsmbus )

Initialize the SMBUS MSP.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 439 of file stm32wbxx_hal_smbus.c.

Referenced by HAL_SMBUS_Init(), and HAL_SMBUS_UnRegisterCallback().

HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | pSMBUS_AddrCallbackTypeDef | pCallback
 | ) |  |

Register the Slave Address Match SMBUS Callback To be used instead of the weak HAL_SMBUS_AddrCallback() predefined callback.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
pCallback | pointer to the Address Match Callback function
Return values:
HAL status

Definition at line 790 of file stm32wbxx_hal_smbus.c.

References __SMBUS_HandleTypeDef::AddrCallback, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_INVALID_CALLBACK, HAL_SMBUS_STATE_READY, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_RegisterCallback | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | HAL_SMBUS_CallbackIDTypeDef | CallbackID,
 |  | pSMBUS_CallbackTypeDef | pCallback
 | ) |  |

Register a User SMBUS Callback To be used instead of the weak predefined callback.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
  • HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
  • HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
  • HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
  • HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
  • HAL_SMBUS_ERROR_CB_ID Error callback ID
  • HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID
  • HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 582 of file stm32wbxx_hal_smbus.c.

References __SMBUS_HandleTypeDef::ErrorCallback, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_CB_ID, HAL_SMBUS_ERROR_INVALID_CALLBACK, HAL_SMBUS_LISTEN_COMPLETE_CB_ID, HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID, HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID, HAL_SMBUS_MSPDEINIT_CB_ID, HAL_SMBUS_MSPINIT_CB_ID, HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID, HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID, HAL_SMBUS_STATE_READY, HAL_SMBUS_STATE_RESET, __SMBUS_HandleTypeDef::ListenCpltCallback, __SMBUS_HandleTypeDef::MasterRxCpltCallback, __SMBUS_HandleTypeDef::MasterTxCpltCallback, __SMBUS_HandleTypeDef::MspDeInitCallback, __SMBUS_HandleTypeDef::MspInitCallback, __SMBUS_HandleTypeDef::SlaveRxCpltCallback, __SMBUS_HandleTypeDef::SlaveTxCpltCallback, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback ( SMBUS_HandleTypeDef * hsmbus )

UnRegister the Slave Address Match SMBUS Callback Info Ready SMBUS Callback is redirected to the weak HAL_SMBUS_AddrCallback() predefined callback.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 829 of file stm32wbxx_hal_smbus.c.

References __SMBUS_HandleTypeDef::AddrCallback, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_AddrCallback(), HAL_SMBUS_ERROR_INVALID_CALLBACK, HAL_SMBUS_STATE_READY, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | HAL_SMBUS_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an SMBUS Callback SMBUS callback is redirected to the weak predefined callback.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
CallbackID ID of the callback to be unregistered This parameter can be one of the following values: This parameter can be one of the following values:
  • HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
  • HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
  • HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
  • HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
  • HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
  • HAL_SMBUS_ERROR_CB_ID Error callback ID
  • HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID
  • HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
HAL status

Definition at line 695 of file stm32wbxx_hal_smbus.c.

References __SMBUS_HandleTypeDef::ErrorCallback, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_CB_ID, HAL_SMBUS_ERROR_INVALID_CALLBACK, HAL_SMBUS_ErrorCallback(), HAL_SMBUS_LISTEN_COMPLETE_CB_ID, HAL_SMBUS_ListenCpltCallback(), HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID, HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID, HAL_SMBUS_MasterRxCpltCallback(), HAL_SMBUS_MasterTxCpltCallback(), HAL_SMBUS_MspDeInit(), HAL_SMBUS_MSPDEINIT_CB_ID, HAL_SMBUS_MspInit(), HAL_SMBUS_MSPINIT_CB_ID, HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID, HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID, HAL_SMBUS_SlaveRxCpltCallback(), HAL_SMBUS_SlaveTxCpltCallback(), HAL_SMBUS_STATE_READY, HAL_SMBUS_STATE_RESET, __SMBUS_HandleTypeDef::ListenCpltCallback, __SMBUS_HandleTypeDef::MasterRxCpltCallback, __SMBUS_HandleTypeDef::MasterTxCpltCallback, __SMBUS_HandleTypeDef::MspDeInitCallback, __SMBUS_HandleTypeDef::MspInitCallback, __SMBUS_HandleTypeDef::SlaveRxCpltCallback, __SMBUS_HandleTypeDef::SlaveTxCpltCallback, and __SMBUS_HandleTypeDef::State.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Blocking mode Polling

Functions
Blocking mode Polling
Input and Output operation functions

Functions

HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Check if target device is ready for communication.

Function Documentation

HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint32_t | Trials,
 |  | uint32_t | Timeout
 | ) |  |

Check if target device is ready for communication.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
Trials | Number of trials
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1420 of file stm32wbxx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __HAL_SMBUS_GET_FLAG, SMBUS_InitTypeDef::AddressingMode, __SMBUS_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SMBUS_ERROR_HALTIMEOUT, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_READY, __SMBUS_HandleTypeDef::Init, __SMBUS_HandleTypeDef::Instance, SMBUS_FLAG_AF, SMBUS_FLAG_BUSY, SMBUS_FLAG_STOPF, SMBUS_GENERATE_START, SMBUS_WaitOnFlagUntilTimeout(), and __SMBUS_HandleTypeDef::State.

Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Non-Blocking mode Interrupt

Functions
Non-Blocking mode Interrupt
Input and Output operation functions

Functions

HAL_StatusTypeDef | HAL_SMBUS_Master_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Abort_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
Abort a master/host SMBUS process communication with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the Address listen mode with Interrupt.

Function Documentation

HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT ( SMBUS_HandleTypeDef * hsmbus )

Disable the SMBUS alert mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUSx peripheral.
Return values:
HAL status

Definition at line 1399 of file stm32wbxx_hal_smbus.c.

References __SMBUS_HandleTypeDef::Instance, SMBUS_Disable_IRQ(), and SMBUS_IT_ALERT.

HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT ( SMBUS_HandleTypeDef * hsmbus )

Disable the Address listen mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 1356 of file stm32wbxx_hal_smbus.c.

References HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_READY, SMBUS_Disable_IRQ(), SMBUS_IT_ADDR, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT ( SMBUS_HandleTypeDef * hsmbus )

Enable the SMBUS alert mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUSx peripheral.
Return values:
HAL status

Definition at line 1380 of file stm32wbxx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __SMBUS_HandleTypeDef::Instance, SMBUS_Enable_IRQ(), SMBUS_FLAG_ALERT, and SMBUS_IT_ALERT.

HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT ( SMBUS_HandleTypeDef * hsmbus )

Enable the Address listen mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 1340 of file stm32wbxx_hal_smbus.c.

References HAL_SMBUS_STATE_LISTEN, SMBUS_Enable_IRQ(), SMBUS_IT_ADDR, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress
 | ) |  |

Abort a master/host SMBUS process communication with Interrupt.

Note:
This abort can be called only if state is ready
Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
Return values:
HAL status

Definition at line 1103 of file stm32wbxx_hal_smbus.c.

References __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_READY, __SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_Enable_IRQ(), SMBUS_IT_RX, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_TransferConfig(), and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 1013 of file stm32wbxx_hal_smbus.c.

References assert_param, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_READY, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __SMBUS_HandleTypeDef::pBuffPtr, __SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_ConvertOtherXferOptions(), SMBUS_Enable_IRQ(), SMBUS_GENERATE_START_READ, SMBUS_IT_RX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 914 of file stm32wbxx_hal_smbus.c.

References assert_param, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_READY, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __SMBUS_HandleTypeDef::pBuffPtr, __SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_ConvertOtherXferOptions(), SMBUS_Enable_IRQ(), SMBUS_GENERATE_START_WRITE, SMBUS_GET_PEC_MODE, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 1262 of file stm32wbxx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, assert_param, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_INVALID_PARAM, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_SLAVE_BUSY_RX, __SMBUS_HandleTypeDef::Instance, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, __SMBUS_HandleTypeDef::pBuffPtr, SMBUS_ConvertOtherXferOptions(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_FLAG_ADDR, SMBUS_GET_PEC_MODE, SMBUS_IT_ADDR, SMBUS_IT_RX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 1168 of file stm32wbxx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, assert_param, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_INVALID_PARAM, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_SLAVE_BUSY_TX, __SMBUS_HandleTypeDef::Instance, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __SMBUS_HandleTypeDef::pBuffPtr, SMBUS_ConvertOtherXferOptions(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_FLAG_ADDR, SMBUS_GET_PEC_MODE, SMBUS_IT_ADDR, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IRQ Handler and Callbacks

Functions
IRQ Handler and Callbacks
SMBUS Exported Functions | Input and Output operation functions

Functions

void | HAL_SMBUS_EV_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS event interrupt request.
void | HAL_SMBUS_ER_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS error interrupt request.
__weak void | HAL_SMBUS_MasterTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Tx Transfer completed callback.
__weak void | HAL_SMBUS_MasterRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Rx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Tx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Rx Transfer completed callback.
__weak void | HAL_SMBUS_AddrCallback (SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_SMBUS_ListenCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Listen Complete callback.
__weak void | HAL_SMBUS_ErrorCallback (SMBUS_HandleTypeDef *hsmbus)
SMBUS error callback.

Function Documentation

void HAL_SMBUS_AddrCallback | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint8_t | TransferDirection,
 |  | uint16_t | AddrMatchCode
 | ) |  |

Slave Address Match callback.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
TransferDirection | Master request Transfer Direction (Write/Read)
AddrMatchCode | Address Match Code
Return values:
None

Definition at line 1698 of file stm32wbxx_hal_smbus.c.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_UnRegisterAddrCallback(), and SMBUS_Slave_ISR().

void HAL_SMBUS_ER_IRQHandler ( SMBUS_HandleTypeDef * hsmbus )

Handle SMBUS error interrupt request.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1622 of file stm32wbxx_hal_smbus.c.

References SMBUS_ITErrorHandler().

void HAL_SMBUS_ErrorCallback ( SMBUS_HandleTypeDef * hsmbus )

SMBUS error callback.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1732 of file stm32wbxx_hal_smbus.c.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_UnRegisterCallback(), SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

void HAL_SMBUS_EV_IRQHandler ( SMBUS_HandleTypeDef * hsmbus )

Handle SMBUS event interrupt request.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1561 of file stm32wbxx_hal_smbus.c.

References HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_SLAVE_BUSY_RX, HAL_SMBUS_STATE_SLAVE_BUSY_TX, __SMBUS_HandleTypeDef::Instance, SMBUS_CHECK_FLAG, SMBUS_CHECK_IT_SOURCE, SMBUS_FLAG_ADDR, SMBUS_FLAG_AF, SMBUS_FLAG_RXNE, SMBUS_FLAG_STOPF, SMBUS_FLAG_TC, SMBUS_FLAG_TCR, SMBUS_FLAG_TXIS, SMBUS_IT_ADDRI, SMBUS_IT_NACKI, SMBUS_IT_RXI, SMBUS_IT_STOPI, SMBUS_IT_TCI, SMBUS_IT_TXI, SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and __SMBUS_HandleTypeDef::State.

void HAL_SMBUS_ListenCpltCallback ( SMBUS_HandleTypeDef * hsmbus )

Listen Complete callback.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1716 of file stm32wbxx_hal_smbus.c.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Slave_ISR().

void HAL_SMBUS_MasterRxCpltCallback ( SMBUS_HandleTypeDef * hsmbus )

Master Rx Transfer completed callback.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1649 of file stm32wbxx_hal_smbus.c.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Master_ISR().

void HAL_SMBUS_MasterTxCpltCallback ( SMBUS_HandleTypeDef * hsmbus )

Master Tx Transfer completed callback.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1633 of file stm32wbxx_hal_smbus.c.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Master_ISR().

void HAL_SMBUS_SlaveRxCpltCallback ( SMBUS_HandleTypeDef * hsmbus )

Slave Rx Transfer completed callback.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1680 of file stm32wbxx_hal_smbus.c.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Slave_ISR().

void HAL_SMBUS_SlaveTxCpltCallback ( SMBUS_HandleTypeDef * hsmbus )

Slave Tx Transfer completed callback.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
None

Definition at line 1664 of file stm32wbxx_hal_smbus.c.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Slave_ISR().

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
SMBUS Exported Functions | Input and Output operation functions

Peripheral State and Errors functions. More...

Functions

uint32_t | HAL_SMBUS_GetState (SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS handle state.
uint32_t | HAL_SMBUS_GetError (SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS error code.

Detailed Description

Peripheral State and Errors functions.

 ===============================================================================
            ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

uint32_t HAL_SMBUS_GetError ( SMBUS_HandleTypeDef * hsmbus )

Return the SMBUS error code.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
SMBUS Error Code

Definition at line 1779 of file stm32wbxx_hal_smbus.c.

References __SMBUS_HandleTypeDef::ErrorCode.

uint32_t HAL_SMBUS_GetState ( SMBUS_HandleTypeDef * hsmbus )

Return the SMBUS handle state.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL state

Definition at line 1767 of file stm32wbxx_hal_smbus.c.

References __SMBUS_HandleTypeDef::State.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Input and Output operation functions

Modules | Functions
Input and Output operation functions
SMBUS Exported Functions

Data transfers functions. More...

Modules

Blocking mode Polling
Non-Blocking mode Interrupt
IRQ Handler and Callbacks
Peripheral State and Errors functions

Peripheral State and Errors functions.

Functions

HAL_StatusTypeDef | HAL_SMBUS_Master_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Abort_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
Abort a master/host SMBUS process communication with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_IsDeviceReady (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Check if target device is ready for communication.

Detailed Description

Data transfers functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the SMBUS data
    transfers.

    (#) Blocking mode function to check if device is ready for usage is :
        (++) HAL_SMBUS_IsDeviceReady()

    (#) There is only one mode of transfer:
       (++) Non-Blocking mode : The communication is performed using Interrupts.
            These functions return the status of the transfer startup.
            The end of the data processing will be indicated through the
            dedicated SMBUS IRQ when using Interrupt mode.

    (#) Non-Blocking mode functions with Interrupt are :
        (++) HAL_SMBUS_Master_Transmit_IT()
        (++) HAL_SMBUS_Master_Receive_IT()
        (++) HAL_SMBUS_Slave_Transmit_IT()
        (++) HAL_SMBUS_Slave_Receive_IT()
        (++) HAL_SMBUS_EnableListen_IT() or alias HAL_SMBUS_EnableListen_IT()
        (++) HAL_SMBUS_DisableListen_IT()
        (++) HAL_SMBUS_EnableAlert_IT()
        (++) HAL_SMBUS_DisableAlert_IT()

    (#) A set of Transfer Complete Callbacks are provided in non-Blocking mode:
        (++) HAL_SMBUS_MasterTxCpltCallback()
        (++) HAL_SMBUS_MasterRxCpltCallback()
        (++) HAL_SMBUS_SlaveTxCpltCallback()
        (++) HAL_SMBUS_SlaveRxCpltCallback()
        (++) HAL_SMBUS_AddrCallback()
        (++) HAL_SMBUS_ListenCpltCallback()
        (++) HAL_SMBUS_ErrorCallback()

Function Documentation

HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT ( SMBUS_HandleTypeDef * hsmbus )

Disable the SMBUS alert mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUSx peripheral.
Return values:
HAL status

Definition at line 1399 of file stm32wbxx_hal_smbus.c.

References __SMBUS_HandleTypeDef::Instance, SMBUS_Disable_IRQ(), and SMBUS_IT_ALERT.

HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT ( SMBUS_HandleTypeDef * hsmbus )

Disable the Address listen mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 1356 of file stm32wbxx_hal_smbus.c.

References HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_READY, SMBUS_Disable_IRQ(), SMBUS_IT_ADDR, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT ( SMBUS_HandleTypeDef * hsmbus )

Enable the SMBUS alert mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUSx peripheral.
Return values:
HAL status

Definition at line 1380 of file stm32wbxx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __SMBUS_HandleTypeDef::Instance, SMBUS_Enable_IRQ(), SMBUS_FLAG_ALERT, and SMBUS_IT_ALERT.

HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT ( SMBUS_HandleTypeDef * hsmbus )

Enable the Address listen mode with Interrupt.

Parameters:
hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Return values:
HAL status

Definition at line 1340 of file stm32wbxx_hal_smbus.c.

References HAL_SMBUS_STATE_LISTEN, SMBUS_Enable_IRQ(), SMBUS_IT_ADDR, and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint32_t | Trials,
 |  | uint32_t | Timeout
 | ) |  |

Check if target device is ready for communication.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
Trials | Number of trials
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1420 of file stm32wbxx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __HAL_SMBUS_GET_FLAG, SMBUS_InitTypeDef::AddressingMode, __SMBUS_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SMBUS_ERROR_HALTIMEOUT, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_BUSY, HAL_SMBUS_STATE_READY, __SMBUS_HandleTypeDef::Init, __SMBUS_HandleTypeDef::Instance, SMBUS_FLAG_AF, SMBUS_FLAG_BUSY, SMBUS_FLAG_STOPF, SMBUS_GENERATE_START, SMBUS_WaitOnFlagUntilTimeout(), and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress
 | ) |  |

Abort a master/host SMBUS process communication with Interrupt.

Note:
This abort can be called only if state is ready
Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
Return values:
HAL status

Definition at line 1103 of file stm32wbxx_hal_smbus.c.

References __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_READY, __SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_Enable_IRQ(), SMBUS_IT_RX, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_TransferConfig(), and __SMBUS_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 1013 of file stm32wbxx_hal_smbus.c.

References assert_param, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_READY, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __SMBUS_HandleTypeDef::pBuffPtr, __SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_ConvertOtherXferOptions(), SMBUS_Enable_IRQ(), SMBUS_GENERATE_START_READ, SMBUS_IT_RX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shifted to the left before calling the interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 914 of file stm32wbxx_hal_smbus.c.

References assert_param, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_READY, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __SMBUS_HandleTypeDef::pBuffPtr, __SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_ConvertOtherXferOptions(), SMBUS_Enable_IRQ(), SMBUS_GENERATE_START_WRITE, SMBUS_GET_PEC_MODE, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 1262 of file stm32wbxx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, assert_param, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_INVALID_PARAM, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_SLAVE_BUSY_RX, __SMBUS_HandleTypeDef::Instance, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, __SMBUS_HandleTypeDef::pBuffPtr, SMBUS_ConvertOtherXferOptions(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_FLAG_ADDR, SMBUS_GET_PEC_MODE, SMBUS_IT_ADDR, SMBUS_IT_RX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT | ( | SMBUS_HandleTypeDef * | hsmbus,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of SMBUS XferOptions definition
Return values:
HAL status

Definition at line 1168 of file stm32wbxx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, assert_param, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_INVALID_PARAM, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_SLAVE_BUSY_TX, __SMBUS_HandleTypeDef::Instance, IS_SMBUS_TRANSFER_OPTIONS_REQUEST, MAX_NBYTE_SIZE, __SMBUS_HandleTypeDef::pBuffPtr, SMBUS_ConvertOtherXferOptions(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_FLAG_ADDR, SMBUS_GET_PEC_MODE, SMBUS_IT_ADDR, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMBUS Private Functions

Functions
SMBUS Private Functions
SMBUS Exported Functions | SMBUS

Data transfers Private functions. More...

Functions

static HAL_StatusTypeDef | SMBUS_WaitOnFlagUntilTimeout (struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
Handle SMBUS Communication Timeout.
static void | SMBUS_Enable_IRQ (struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
Manage the enabling of Interrupts.
static void | SMBUS_Disable_IRQ (struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
Manage the disabling of Interrupts.
static HAL_StatusTypeDef | SMBUS_Master_ISR (struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
static HAL_StatusTypeDef | SMBUS_Slave_ISR (struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
static void | SMBUS_ConvertOtherXferOptions (struct __SMBUS_HandleTypeDef *hsmbus)
Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions.
static void | SMBUS_ITErrorHandler (struct __SMBUS_HandleTypeDef *hsmbus)
SMBUS interrupts error handler.
static void | SMBUS_TransferConfig (struct __SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).

Detailed Description

Data transfers Private functions.

Function Documentation

static void SMBUS_ConvertOtherXferOptions ( struct __SMBUS_HandleTypeDef * hsmbus ) [static]

Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions.

Parameters:
hsmbus SMBUS handle.
Return values:
None

Definition at line 2623 of file stm32wbxx_hal_smbus.c.

References SMBUS_FIRST_AND_LAST_FRAME_NO_PEC, SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC, SMBUS_FIRST_FRAME, SMBUS_OTHER_AND_LAST_FRAME_NO_PEC, SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC, SMBUS_OTHER_FRAME_NO_PEC, SMBUS_OTHER_FRAME_WITH_PEC, SMBUS_SENDPEC_MODE, and __SMBUS_HandleTypeDef::XferOptions.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), and HAL_SMBUS_Slave_Transmit_IT().

static void SMBUS_Disable_IRQ | ( | struct __SMBUS_HandleTypeDef * | hsmbus,
 |  | uint32_t | InterruptRequest
 | ) |  | [static]

Manage the disabling of Interrupts.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
InterruptRequest | Value of SMBUS Interrupt configuration definition.
Return values:
HAL status

Definition at line 2384 of file stm32wbxx_hal_smbus.c.

References __HAL_SMBUS_DISABLE_IT, HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_READY, SMBUS_GET_ALERT_ENABLED, SMBUS_IT_ADDR, SMBUS_IT_ADDRI, SMBUS_IT_ALERT, SMBUS_IT_ERRI, SMBUS_IT_NACKI, SMBUS_IT_RX, SMBUS_IT_RXI, SMBUS_IT_STOPI, SMBUS_IT_TCI, SMBUS_IT_TX, SMBUS_IT_TXI, and __SMBUS_HandleTypeDef::State.

Referenced by HAL_SMBUS_DisableAlert_IT(), HAL_SMBUS_DisableListen_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

static void SMBUS_Enable_IRQ | ( | struct __SMBUS_HandleTypeDef * | hsmbus,
 |  | uint32_t | InterruptRequest
 | ) |  | [static]

Manage the enabling of Interrupts.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
InterruptRequest | Value of SMBUS Interrupt configuration definition.
Return values:
HAL status

Definition at line 2344 of file stm32wbxx_hal_smbus.c.

References __HAL_SMBUS_ENABLE_IT, SMBUS_IT_ADDR, SMBUS_IT_ADDRI, SMBUS_IT_ALERT, SMBUS_IT_ERRI, SMBUS_IT_NACKI, SMBUS_IT_RX, SMBUS_IT_RXI, SMBUS_IT_STOPI, SMBUS_IT_TCI, SMBUS_IT_TX, and SMBUS_IT_TXI.

Referenced by HAL_SMBUS_EnableAlert_IT(), HAL_SMBUS_EnableListen_IT(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), and HAL_SMBUS_Slave_Transmit_IT().

static void SMBUS_ITErrorHandler ( struct __SMBUS_HandleTypeDef * hsmbus ) [static]

SMBUS interrupts error handler.

Parameters:
hsmbus SMBUS handle.
Return values:
None

Definition at line 2456 of file stm32wbxx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __SMBUS_HandleTypeDef::ErrorCallback, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_ACKF, HAL_SMBUS_ERROR_ALERT, HAL_SMBUS_ERROR_ARLO, HAL_SMBUS_ERROR_BERR, HAL_SMBUS_ERROR_BUSTIMEOUT, HAL_SMBUS_ERROR_NONE, HAL_SMBUS_ERROR_OVR, HAL_SMBUS_ERROR_PECERR, HAL_SMBUS_ErrorCallback(), HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_READY, HAL_SMBUS_STATE_SLAVE_BUSY_RX, HAL_SMBUS_STATE_SLAVE_BUSY_TX, __SMBUS_HandleTypeDef::Instance, __SMBUS_HandleTypeDef::PreviousState, SMBUS_FLAG_ALERT, SMBUS_FLAG_ARLO, SMBUS_FLAG_BERR, SMBUS_FLAG_OVR, SMBUS_FLAG_PECERR, SMBUS_FLAG_TIMEOUT, SMBUS_IT_ERRI, and __SMBUS_HandleTypeDef::State.

Referenced by HAL_SMBUS_ER_IRQHandler(), and SMBUS_Master_ISR().

static HAL_StatusTypeDef SMBUS_Master_ISR | ( | struct __SMBUS_HandleTypeDef * | hsmbus,
 |  | uint32_t | StatusFlags
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
StatusFlags | Value of Interrupt Flags.
Return values:
HAL status

Definition at line 1804 of file stm32wbxx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __HAL_SMBUS_DISABLE, __HAL_SMBUS_ENABLE, __SMBUS_HandleTypeDef::ErrorCallback, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_ERROR_ACKF, HAL_SMBUS_ErrorCallback(), HAL_SMBUS_MasterRxCpltCallback(), HAL_SMBUS_MasterTxCpltCallback(), HAL_SMBUS_STATE_MASTER_BUSY_RX, HAL_SMBUS_STATE_MASTER_BUSY_TX, HAL_SMBUS_STATE_READY, __SMBUS_HandleTypeDef::Instance, __SMBUS_HandleTypeDef::MasterRxCpltCallback, __SMBUS_HandleTypeDef::MasterTxCpltCallback, MAX_NBYTE_SIZE, __SMBUS_HandleTypeDef::pBuffPtr, __SMBUS_HandleTypeDef::PreviousState, SMBUS_AUTOEND_MODE, SMBUS_CHECK_FLAG, SMBUS_Disable_IRQ(), SMBUS_FLAG_AF, SMBUS_FLAG_RXNE, SMBUS_FLAG_STOPF, SMBUS_FLAG_TC, SMBUS_FLAG_TCR, SMBUS_FLAG_TXIS, SMBUS_GET_PEC_MODE, SMBUS_GET_STOP_MODE, SMBUS_IT_RX, SMBUS_IT_TX, SMBUS_ITErrorHandler(), SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_RESET_CR2, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

Referenced by HAL_SMBUS_EV_IRQHandler().

static HAL_StatusTypeDef SMBUS_Slave_ISR | ( | struct __SMBUS_HandleTypeDef * | hsmbus,
 |  | uint32_t | StatusFlags
 | ) |  | [static]

Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
StatusFlags | Value of Interrupt Flags.
Return values:
HAL status

Definition at line 2088 of file stm32wbxx_hal_smbus.c.

References __HAL_SMBUS_CLEAR_FLAG, __HAL_SMBUS_DISABLE_IT, __HAL_SMBUS_GET_FLAG, __SMBUS_HandleTypeDef::AddrCallback, __SMBUS_HandleTypeDef::ErrorCallback, __SMBUS_HandleTypeDef::ErrorCode, HAL_SMBUS_AddrCallback(), HAL_SMBUS_ERROR_ACKF, HAL_SMBUS_ErrorCallback(), HAL_SMBUS_ListenCpltCallback(), HAL_SMBUS_SlaveRxCpltCallback(), HAL_SMBUS_SlaveTxCpltCallback(), HAL_SMBUS_STATE_LISTEN, HAL_SMBUS_STATE_READY, HAL_SMBUS_STATE_SLAVE_BUSY_RX, HAL_SMBUS_STATE_SLAVE_BUSY_TX, __SMBUS_HandleTypeDef::Instance, __SMBUS_HandleTypeDef::ListenCpltCallback, MAX_NBYTE_SIZE, __SMBUS_HandleTypeDef::pBuffPtr, __SMBUS_HandleTypeDef::PreviousState, __SMBUS_HandleTypeDef::SlaveRxCpltCallback, __SMBUS_HandleTypeDef::SlaveTxCpltCallback, SMBUS_CHECK_FLAG, SMBUS_Disable_IRQ(), SMBUS_FLAG_ADDR, SMBUS_FLAG_AF, SMBUS_FLAG_RXNE, SMBUS_FLAG_STOPF, SMBUS_FLAG_TCR, SMBUS_FLAG_TXIS, SMBUS_GET_ADDR_MATCH, SMBUS_GET_DIR, SMBUS_GET_PEC_MODE, SMBUS_IT_ADDR, SMBUS_IT_ADDRI, SMBUS_IT_RX, SMBUS_IT_TX, SMBUS_NO_STARTSTOP, SMBUS_RELOAD_MODE, SMBUS_RESET_CR2, SMBUS_SENDPEC_MODE, SMBUS_TransferConfig(), __SMBUS_HandleTypeDef::State, __SMBUS_HandleTypeDef::XferCount, __SMBUS_HandleTypeDef::XferOptions, and __SMBUS_HandleTypeDef::XferSize.

Referenced by HAL_SMBUS_EV_IRQHandler().

static void SMBUS_TransferConfig | ( | struct __SMBUS_HandleTypeDef * | hsmbus,
 |  | uint16_t | DevAddress,
 |  | uint8_t | Size,
 |  | uint32_t | Mode,
 |  | uint32_t | Request
 | ) |  | [static]

Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).

Parameters:
hsmbus | SMBUS handle.
DevAddress | specifies the slave address to be programmed.
Size | specifies the number of bytes to be programmed. This parameter must be a value between 0 and 255.
Mode New state of the SMBUS START condition generation. This parameter can be one or a combination of the following values:
  • SMBUS_RELOAD_MODE Enable Reload mode.
  • SMBUS_AUTOEND_MODE Enable Automatic end mode.
  • SMBUS_SOFTEND_MODE Enable Software end mode and Reload mode.
  • SMBUS_SENDPEC_MODE Enable Packet Error Calculation mode.
Request New state of the SMBUS START condition generation. This parameter can be one of the following values:
  • SMBUS_NO_STARTSTOP Don't Generate stop and start condition.
  • SMBUS_GENERATE_STOP Generate stop condition (Size should be set to 0).
  • SMBUS_GENERATE_START_READ Generate Restart for read request.
  • SMBUS_GENERATE_START_WRITE Generate Restart for write request.
Return values:
None

Definition at line 2606 of file stm32wbxx_hal_smbus.c.

References assert_param, __SMBUS_HandleTypeDef::Instance, IS_SMBUS_TRANSFER_MODE, and IS_SMBUS_TRANSFER_REQUEST.

Referenced by HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout | ( | struct __SMBUS_HandleTypeDef * | hsmbus,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle SMBUS Communication Timeout.

Parameters:
hsmbus | Pointer to a SMBUS_HandleTypeDef structure that contains the configuration information for the specified SMBUS.
Flag | Specifies the SMBUS flag to check.
Status | The new Flag status (SET or RESET).
Timeout | Timeout duration
Return values:
HAL status

Definition at line 2557 of file stm32wbxx_hal_smbus.c.

References __HAL_SMBUS_GET_FLAG, __SMBUS_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SMBUS_ERROR_HALTIMEOUT, HAL_SMBUS_STATE_READY, __SMBUS_HandleTypeDef::PreviousState, and __SMBUS_HandleTypeDef::State.

Referenced by HAL_SMBUS_IsDeviceReady().

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMBUS_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SMBUS_InitTypeDef Struct Reference
SMBUS Configuration Structure definition

#include <stm32wbxx_hal_smbus.h>

Data Fields

uint32_t | Timing
uint32_t | AnalogFilter
uint32_t | OwnAddress1
uint32_t | AddressingMode
uint32_t | DualAddressMode
uint32_t | OwnAddress2
uint32_t | OwnAddress2Masks
uint32_t | GeneralCallMode
uint32_t | NoStretchMode
uint32_t | PacketErrorCheckMode
uint32_t | PeripheralMode
uint32_t | SMBusTimeout

Detailed Description

Definition at line 48 of file stm32wbxx_hal_smbus.h.

Field Documentation

uint32_t SMBUS_InitTypeDef::AddressingMode

Specifies if 7-bit or 10-bit addressing mode for master is selected. This parameter can be a value of SMBUS addressing mode

Definition at line 59 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), and HAL_SMBUS_IsDeviceReady().

uint32_t SMBUS_InitTypeDef::AnalogFilter

Specifies if Analog Filter is enable or not. This parameter can be a value of SMBUS Analog Filter

Definition at line 53 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::DualAddressMode

Specifies if dual addressing mode is selected. This parameter can be a value of SMBUS dual addressing mode

Definition at line 62 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::GeneralCallMode

Specifies if general call mode is selected. This parameter can be a value of SMBUS general call addressing mode.

Definition at line 71 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::NoStretchMode

Specifies if nostretch mode is selected. This parameter can be a value of SMBUS nostretch mode

Definition at line 74 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::OwnAddress1

Specifies the first device own address. This parameter can be a 7-bit or 10-bit address.

Definition at line 56 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::OwnAddress2

Specifies the second device own address if dual addressing mode is selected This parameter can be a 7-bit address.

Definition at line 65 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::OwnAddress2Masks

Specifies the acknoledge mask address second device own address if dual addressing mode is selected This parameter can be a value of SMBUS ownaddress2 masks.

Definition at line 68 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::PacketErrorCheckMode

Specifies if Packet Error Check mode is selected. This parameter can be a value of SMBUS packet error check mode

Definition at line 77 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::PeripheralMode

Specifies which mode of Periphal is selected. This parameter can be a value of SMBUS peripheral mode

Definition at line 80 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::SMBusTimeout

Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value. (Enable bits and different timeout values) This parameter calculated by referring to SMBUS initialization section in Reference manual

Definition at line 83 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

uint32_t SMBUS_InitTypeDef::Timing

Specifies the SMBUS_TIMINGR_register value. This parameter calculated by referring to SMBUS initialization section in Reference manual

Definition at line 50 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_smbus.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: HAL state definition

Defines
HAL state definition
SMBUS Exported Types

HAL State definition. More...

Defines

#define | HAL_SMBUS_STATE_RESET (0x00000000U)
#define | HAL_SMBUS_STATE_READY (0x00000001U)
#define | HAL_SMBUS_STATE_BUSY (0x00000002U)
#define | HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U)
#define | HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U)
#define | HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U)
#define | HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U)
#define | HAL_SMBUS_STATE_TIMEOUT (0x00000003U)
#define | HAL_SMBUS_STATE_ERROR (0x00000004U)
#define | HAL_SMBUS_STATE_LISTEN (0x00000008U)

Detailed Description

HAL State definition.

Define Documentation

#define HAL_SMBUS_STATE_BUSY (0x00000002U)

SMBUS internal process is ongoing

Definition at line 98 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigAnalogFilter(), HAL_SMBUS_ConfigDigitalFilter(), HAL_SMBUS_DeInit(), HAL_SMBUS_Init(), and HAL_SMBUS_IsDeviceReady().

#define HAL_SMBUS_STATE_ERROR (0x00000004U)

Reception process is ongoing

Definition at line 104 of file stm32wbxx_hal_smbus.h.

#define HAL_SMBUS_STATE_LISTEN (0x00000008U)

Address Listen Mode is ongoing

Definition at line 105 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_DisableListen_IT(), HAL_SMBUS_EnableListen_IT(), HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Disable_IRQ(), SMBUS_ITErrorHandler(), and SMBUS_Slave_ISR().

#define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U)

Master Data Reception process is ongoing

Definition at line 100 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), and SMBUS_Master_ISR().

#define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U)

Master Data Transmission process is ongoing

Definition at line 99 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Transmit_IT(), and SMBUS_Master_ISR().

#define HAL_SMBUS_STATE_READY (0x00000001U)

SMBUS initialized and ready for use

Definition at line 97 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigAnalogFilter(), HAL_SMBUS_ConfigDigitalFilter(), HAL_SMBUS_DisableListen_IT(), HAL_SMBUS_Init(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_RegisterAddrCallback(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_UnRegisterAddrCallback(), HAL_SMBUS_UnRegisterCallback(), SMBUS_Disable_IRQ(), SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and SMBUS_WaitOnFlagUntilTimeout().

#define HAL_SMBUS_STATE_RESET (0x00000000U)

SMBUS not yet initialized or disabled

Definition at line 96 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), HAL_SMBUS_Init(), HAL_SMBUS_RegisterCallback(), and HAL_SMBUS_UnRegisterCallback().

#define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U)

Slave Data Reception process is ongoing

Definition at line 102 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Slave_Receive_IT(), SMBUS_ITErrorHandler(), and SMBUS_Slave_ISR().

#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U)

Slave Data Transmission process is ongoing

Definition at line 101 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_ITErrorHandler(), and SMBUS_Slave_ISR().

#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U)

Timeout state

Definition at line 103 of file stm32wbxx_hal_smbus.h.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMBUS Error Code definition

Defines
SMBUS Error Code definition
SMBUS Exported Types

SMBUS Error Code definition. More...

Defines

#define | HAL_SMBUS_ERROR_NONE (0x00000000U)
#define | HAL_SMBUS_ERROR_BERR (0x00000001U)
#define | HAL_SMBUS_ERROR_ARLO (0x00000002U)
#define | HAL_SMBUS_ERROR_ACKF (0x00000004U)
#define | HAL_SMBUS_ERROR_OVR (0x00000008U)
#define | HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U)
#define | HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U)
#define | HAL_SMBUS_ERROR_ALERT (0x00000040U)
#define | HAL_SMBUS_ERROR_PECERR (0x00000080U)
#define | HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U)
#define | HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U)

Detailed Description

SMBUS Error Code definition.

Define Documentation

#define HAL_SMBUS_ERROR_ACKF (0x00000004U)

ACKF error

Definition at line 117 of file stm32wbxx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define HAL_SMBUS_ERROR_ALERT (0x00000040U)

Alert error

Definition at line 121 of file stm32wbxx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define HAL_SMBUS_ERROR_ARLO (0x00000002U)

ARLO error

Definition at line 116 of file stm32wbxx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define HAL_SMBUS_ERROR_BERR (0x00000001U)

BERR error

Definition at line 115 of file stm32wbxx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U)

Bus Timeout error

Definition at line 120 of file stm32wbxx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U)

Timeout error

Definition at line 119 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_IsDeviceReady(), and SMBUS_WaitOnFlagUntilTimeout().

#define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U)

Invalid Callback error

Definition at line 124 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_RegisterAddrCallback(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_UnRegisterAddrCallback(), and HAL_SMBUS_UnRegisterCallback().

#define HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U)

Invalid Parameters error

Definition at line 126 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Slave_Receive_IT(), and HAL_SMBUS_Slave_Transmit_IT().

#define HAL_SMBUS_ERROR_NONE (0x00000000U)

No error

Definition at line 114 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), HAL_SMBUS_Init(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), and SMBUS_ITErrorHandler().

#define HAL_SMBUS_ERROR_OVR (0x00000008U)

OVR error

Definition at line 118 of file stm32wbxx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define HAL_SMBUS_ERROR_PECERR (0x00000080U)

PEC error

Definition at line 122 of file stm32wbxx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMBUS handle Structure definition

Data Structures | Typedefs | Enumerations
SMBUS handle Structure definition
SMBUS Exported Types

SMBUS handle Structure definition. More...

Data Structures

struct | __SMBUS_HandleTypeDef

Typedefs

typedef struct
__SMBUS_HandleTypeDef 		SMBUS_HandleTypeDef
typedef void(* | pSMBUS_CallbackTypeDef )(SMBUS_HandleTypeDef *hsmbus)
HAL SMBUS Callback pointer definition.
typedef void(* | pSMBUS_AddrCallbackTypeDef )(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)

Enumerations

enum HAL_SMBUS_CallbackIDTypeDef {
HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U,
HAL_SMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, HAL_SMBUS_ERROR_CB_ID = 0x05U, HAL_SMBUS_MSPINIT_CB_ID = 0x06U, HAL_SMBUS_MSPDEINIT_CB_ID = 0x07U
}
HAL SMBUS Callback ID enumeration definition. More...

Detailed Description

SMBUS handle Structure definition.

Typedef Documentation

typedef void(* pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)

pointer to an SMBUS Address Match callback function

Definition at line 195 of file stm32wbxx_hal_smbus.h.

typedef void(* pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus)

HAL SMBUS Callback pointer definition.

pointer to an SMBUS callback function

Definition at line 194 of file stm32wbxx_hal_smbus.h.

typedef struct __SMBUS_HandleTypeDef SMBUS_HandleTypeDef

Enumeration Type Documentation

enum HAL_SMBUS_CallbackIDTypeDef

HAL SMBUS Callback ID enumeration definition.

Enumerator:
HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID

SMBUS Master Tx Transfer completed callback ID

HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID

SMBUS Master Rx Transfer completed callback ID

HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID

SMBUS Slave Tx Transfer completed callback ID

HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID

SMBUS Slave Rx Transfer completed callback ID

HAL_SMBUS_LISTEN_COMPLETE_CB_ID

SMBUS Listen Complete callback ID

HAL_SMBUS_ERROR_CB_ID

SMBUS Error callback ID

HAL_SMBUS_MSPINIT_CB_ID

SMBUS Msp Init callback ID

HAL_SMBUS_MSPDEINIT_CB_ID

SMBUS Msp DeInit callback ID

Definition at line 177 of file stm32wbxx_hal_smbus.h.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: __SMBUS_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__SMBUS_HandleTypeDef Struct Reference
SMBUS handle Structure definition

#include <stm32wbxx_hal_smbus.h>

Data Fields

I2C_TypeDef * | Instance
SMBUS_InitTypeDef Init
uint8_t * | pBuffPtr
uint16_t | XferSize
__IO uint16_t | XferCount
__IO uint32_t | XferOptions
__IO uint32_t | PreviousState
HAL_LockTypeDef | Lock
__IO uint32_t | State
__IO uint32_t | ErrorCode
void(* | MasterTxCpltCallback )(struct __SMBUS_HandleTypeDef *hsmbus)
void(* | MasterRxCpltCallback )(struct __SMBUS_HandleTypeDef *hsmbus)
void(* | SlaveTxCpltCallback )(struct __SMBUS_HandleTypeDef *hsmbus)
void(* | SlaveRxCpltCallback )(struct __SMBUS_HandleTypeDef *hsmbus)
void(* | ListenCpltCallback )(struct __SMBUS_HandleTypeDef *hsmbus)
void(* | ErrorCallback )(struct __SMBUS_HandleTypeDef *hsmbus)
void(* | AddrCallback )(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
void(* | MspInitCallback )(struct __SMBUS_HandleTypeDef *hsmbus)
void(* | MspDeInitCallback )(struct __SMBUS_HandleTypeDef *hsmbus)

Detailed Description

Definition at line 135 of file stm32wbxx_hal_smbus.h.

Field Documentation

void(* __SMBUS_HandleTypeDef::AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)

SMBUS Slave Address Match callback

Definition at line 165 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_RegisterAddrCallback(), HAL_SMBUS_UnRegisterAddrCallback(), and SMBUS_Slave_ISR().

void(* __SMBUS_HandleTypeDef::ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus)

SMBUS Error callback

Definition at line 163 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_UnRegisterCallback(), SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

__IO uint32_t __SMBUS_HandleTypeDef::ErrorCode

SMBUS Error code

Definition at line 155 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), HAL_SMBUS_GetError(), HAL_SMBUS_Init(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_RegisterAddrCallback(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), HAL_SMBUS_UnRegisterAddrCallback(), HAL_SMBUS_UnRegisterCallback(), SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and SMBUS_WaitOnFlagUntilTimeout().

SMBUS_InitTypeDef __SMBUS_HandleTypeDef::Init

SMBUS communication parameters

Definition at line 139 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), and HAL_SMBUS_IsDeviceReady().

I2C_TypeDef* __SMBUS_HandleTypeDef::Instance

SMBUS registers base address

Definition at line 137 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigAnalogFilter(), HAL_SMBUS_ConfigDigitalFilter(), HAL_SMBUS_DeInit(), HAL_SMBUS_DisableAlert_IT(), HAL_SMBUS_EnableAlert_IT(), HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Init(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and SMBUS_TransferConfig().

void(* __SMBUS_HandleTypeDef::ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus)

SMBUS Listen Complete callback

Definition at line 162 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Slave_ISR().

HAL_LockTypeDef __SMBUS_HandleTypeDef::Lock

SMBUS locking object

Definition at line 151 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

void(* __SMBUS_HandleTypeDef::MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus)

SMBUS Master Rx Transfer completed callback

Definition at line 159 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Master_ISR().

void(* __SMBUS_HandleTypeDef::MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus)

SMBUS Master Tx Transfer completed callback

Definition at line 158 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Master_ISR().

void(* __SMBUS_HandleTypeDef::MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus)

SMBUS Msp DeInit callback

Definition at line 168 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), HAL_SMBUS_RegisterCallback(), and HAL_SMBUS_UnRegisterCallback().

void(* __SMBUS_HandleTypeDef::MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus)

SMBUS Msp Init callback

Definition at line 167 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_RegisterCallback(), and HAL_SMBUS_UnRegisterCallback().

uint8_t* __SMBUS_HandleTypeDef::pBuffPtr

Pointer to SMBUS transfer buffer

Definition at line 141 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

__IO uint32_t __SMBUS_HandleTypeDef::PreviousState

SMBUS communication Previous state

Definition at line 149 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_DeInit(), HAL_SMBUS_Init(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and SMBUS_WaitOnFlagUntilTimeout().

void(* __SMBUS_HandleTypeDef::SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus)

SMBUS Slave Rx Transfer completed callback

Definition at line 161 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Slave_ISR().

void(* __SMBUS_HandleTypeDef::SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus)

SMBUS Slave Tx Transfer completed callback

Definition at line 160 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Init(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_UnRegisterCallback(), and SMBUS_Slave_ISR().

__IO uint32_t __SMBUS_HandleTypeDef::State

SMBUS communication state

Definition at line 153 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigAnalogFilter(), HAL_SMBUS_ConfigDigitalFilter(), HAL_SMBUS_DeInit(), HAL_SMBUS_DisableListen_IT(), HAL_SMBUS_EnableListen_IT(), HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_GetState(), HAL_SMBUS_Init(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_RegisterAddrCallback(), HAL_SMBUS_RegisterCallback(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), HAL_SMBUS_UnRegisterAddrCallback(), HAL_SMBUS_UnRegisterCallback(), SMBUS_Disable_IRQ(), SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), SMBUS_Slave_ISR(), and SMBUS_WaitOnFlagUntilTimeout().

__IO uint16_t __SMBUS_HandleTypeDef::XferCount

SMBUS transfer counter

Definition at line 145 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

__IO uint32_t __SMBUS_HandleTypeDef::XferOptions

SMBUS transfer options

Definition at line 147 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_ConvertOtherXferOptions(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

uint16_t __SMBUS_HandleTypeDef::XferSize

SMBUS transfer size

Definition at line 143 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_smbus.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMBUS Analog Filter

Defines
SMBUS Analog Filter
SMBUS Exported Constants

Defines

#define | SMBUS_ANALOGFILTER_ENABLE (0x00000000U)
#define | SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Define Documentation

#define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF

Definition at line 215 of file stm32wbxx_hal_smbus.h.

#define SMBUS_ANALOGFILTER_ENABLE (0x00000000U)

Definition at line 214 of file stm32wbxx_hal_smbus.h.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMBUS addressing mode

Defines
SMBUS addressing mode
SMBUS Exported Constants

Defines

#define | SMBUS_ADDRESSINGMODE_7BIT (0x00000001U)
#define | SMBUS_ADDRESSINGMODE_10BIT (0x00000002U)

Define Documentation

#define SMBUS_ADDRESSINGMODE_10BIT (0x00000002U)

Definition at line 224 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U)

Definition at line 223 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMBUS dual addressing mode

Defines
SMBUS dual addressing mode
SMBUS Exported Constants

Defines

#define | SMBUS_DUALADDRESS_DISABLE (0x00000000U)
#define | SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN

Define Documentation

#define SMBUS_DUALADDRESS_DISABLE (0x00000000U)

Definition at line 233 of file stm32wbxx_hal_smbus.h.

#define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN

Definition at line 234 of file stm32wbxx_hal_smbus.h.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMBUS ownaddress2 masks

Defines
SMBUS ownaddress2 masks
SMBUS Exported Constants

Defines

#define | SMBUS_OA2_NOMASK ((uint8_t)0x00U)
#define | SMBUS_OA2_MASK01 ((uint8_t)0x01U)
#define | SMBUS_OA2_MASK02 ((uint8_t)0x02U)
#define | SMBUS_OA2_MASK03 ((uint8_t)0x03U)
#define | SMBUS_OA2_MASK04 ((uint8_t)0x04U)
#define | SMBUS_OA2_MASK05 ((uint8_t)0x05U)
#define | SMBUS_OA2_MASK06 ((uint8_t)0x06U)
#define | SMBUS_OA2_MASK07 ((uint8_t)0x07U)

Define Documentation

#define SMBUS_OA2_MASK01 ((uint8_t)0x01U)

Definition at line 244 of file stm32wbxx_hal_smbus.h.

#define SMBUS_OA2_MASK02 ((uint8_t)0x02U)

Definition at line 245 of file stm32wbxx_hal_smbus.h.

#define SMBUS_OA2_MASK03 ((uint8_t)0x03U)

Definition at line 246 of file stm32wbxx_hal_smbus.h.

#define SMBUS_OA2_MASK04 ((uint8_t)0x04U)

Definition at line 247 of file stm32wbxx_hal_smbus.h.

#define SMBUS_OA2_MASK05 ((uint8_t)0x05U)

Definition at line 248 of file stm32wbxx_hal_smbus.h.

#define SMBUS_OA2_MASK06 ((uint8_t)0x06U)

Definition at line 249 of file stm32wbxx_hal_smbus.h.

#define SMBUS_OA2_MASK07 ((uint8_t)0x07U)

Definition at line 250 of file stm32wbxx_hal_smbus.h.

#define SMBUS_OA2_NOMASK ((uint8_t)0x00U)

Definition at line 243 of file stm32wbxx_hal_smbus.h.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMBUS general call addressing mode

Defines
SMBUS general call addressing mode
SMBUS Exported Constants

Defines

#define | SMBUS_GENERALCALL_DISABLE (0x00000000U)
#define | SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN

Define Documentation

#define SMBUS_GENERALCALL_DISABLE (0x00000000U)

Definition at line 259 of file stm32wbxx_hal_smbus.h.

#define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN

Definition at line 260 of file stm32wbxx_hal_smbus.h.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMBUS nostretch mode

Defines
SMBUS nostretch mode
SMBUS Exported Constants

Defines

#define | SMBUS_NOSTRETCH_DISABLE (0x00000000U)
#define | SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH

Define Documentation

#define SMBUS_NOSTRETCH_DISABLE (0x00000000U)

Definition at line 268 of file stm32wbxx_hal_smbus.h.

#define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH

Definition at line 269 of file stm32wbxx_hal_smbus.h.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMBUS packet error check mode

Defines
SMBUS packet error check mode
SMBUS Exported Constants

Defines

#define | SMBUS_PEC_DISABLE (0x00000000U)
#define | SMBUS_PEC_ENABLE I2C_CR1_PECEN

Define Documentation

#define SMBUS_PEC_DISABLE (0x00000000U)

Definition at line 277 of file stm32wbxx_hal_smbus.h.

#define SMBUS_PEC_ENABLE I2C_CR1_PECEN

Definition at line 278 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMBUS peripheral mode

Defines
SMBUS peripheral mode
SMBUS Exported Constants

Defines

#define | SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN
#define | SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U)
#define | SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN

Define Documentation

#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN

Definition at line 286 of file stm32wbxx_hal_smbus.h.

#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U)

Definition at line 287 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN

Definition at line 288 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMBUS ReloadEndMode definition

Defines
SMBUS ReloadEndMode definition
SMBUS Exported Constants

Defines

#define | SMBUS_SOFTEND_MODE (0x00000000U)
#define | SMBUS_RELOAD_MODE I2C_CR2_RELOAD
#define | SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
#define | SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE

Define Documentation

#define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND

Definition at line 299 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), and SMBUS_Master_ISR().

#define SMBUS_RELOAD_MODE I2C_CR2_RELOAD

Definition at line 298 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE

Definition at line 300 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_ConvertOtherXferOptions(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_SOFTEND_MODE (0x00000000U)

Definition at line 297 of file stm32wbxx_hal_smbus.h.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMBUS StartStopMode definition

Defines
SMBUS StartStopMode definition
SMBUS Exported Constants

Defines

#define | SMBUS_NO_STARTSTOP (0x00000000U)
#define | SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define | SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define | SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)

Define Documentation

#define SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)

Definition at line 311 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT().

#define SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)

Definition at line 312 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Transmit_IT().

#define SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)

Definition at line 310 of file stm32wbxx_hal_smbus.h.

#define SMBUS_NO_STARTSTOP (0x00000000U)

Definition at line 309 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMBUS XferOptions definition

Defines
SMBUS XferOptions definition
SMBUS Exported Constants

Defines

#define | SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE
#define | SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
#define | SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define | SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define | SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
#define | SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
#define | SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)
#define | SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)
#define | SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)
#define | SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)

Define Documentation

#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE

Definition at line 327 of file stm32wbxx_hal_smbus.h.

Referenced by SMBUS_ConvertOtherXferOptions().

#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))

Definition at line 329 of file stm32wbxx_hal_smbus.h.

Referenced by SMBUS_ConvertOtherXferOptions().

#define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE

Definition at line 325 of file stm32wbxx_hal_smbus.h.

Referenced by SMBUS_ConvertOtherXferOptions().

#define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE

Definition at line 328 of file stm32wbxx_hal_smbus.h.

#define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))

Definition at line 330 of file stm32wbxx_hal_smbus.h.

#define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))

Definition at line 326 of file stm32wbxx_hal_smbus.h.

#define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)

Definition at line 337 of file stm32wbxx_hal_smbus.h.

Referenced by SMBUS_ConvertOtherXferOptions().

#define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)

Definition at line 338 of file stm32wbxx_hal_smbus.h.

Referenced by SMBUS_ConvertOtherXferOptions().

#define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)

Definition at line 335 of file stm32wbxx_hal_smbus.h.

Referenced by SMBUS_ConvertOtherXferOptions().

#define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)

Definition at line 336 of file stm32wbxx_hal_smbus.h.

Referenced by SMBUS_ConvertOtherXferOptions().

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMBUS Interrupt configuration definition

Defines
SMBUS Interrupt configuration definition
SMBUS Exported Constants

SMBUS Interrupt definition Elements values convention: 0xXXXXXXXX. More...

Defines

#define | SMBUS_IT_ERRI I2C_CR1_ERRIE
#define | SMBUS_IT_TCI I2C_CR1_TCIE
#define | SMBUS_IT_STOPI I2C_CR1_STOPIE
#define | SMBUS_IT_NACKI I2C_CR1_NACKIE
#define | SMBUS_IT_ADDRI I2C_CR1_ADDRIE
#define | SMBUS_IT_RXI I2C_CR1_RXIE
#define | SMBUS_IT_TXI I2C_CR1_TXIE
#define | SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
#define | SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
#define | SMBUS_IT_ALERT (SMBUS_IT_ERRI)
#define | SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)

Detailed Description

SMBUS Interrupt definition Elements values convention: 0xXXXXXXXX.

  • XXXXXXXX : Interrupt control mask

Define Documentation

#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)

Definition at line 359 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_DisableListen_IT(), HAL_SMBUS_EnableListen_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), and SMBUS_Slave_ISR().

#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE

Definition at line 353 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), and SMBUS_Slave_ISR().

#define SMBUS_IT_ALERT (SMBUS_IT_ERRI)

Definition at line 358 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_DisableAlert_IT(), HAL_SMBUS_EnableAlert_IT(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

#define SMBUS_IT_ERRI I2C_CR1_ERRIE

Definition at line 349 of file stm32wbxx_hal_smbus.h.

Referenced by SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), and SMBUS_ITErrorHandler().

#define SMBUS_IT_NACKI I2C_CR1_NACKIE

Definition at line 352 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)

Definition at line 357 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Slave_Receive_IT(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_IT_RXI I2C_CR1_RXIE

Definition at line 354 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

#define SMBUS_IT_STOPI I2C_CR1_STOPIE

Definition at line 351 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

#define SMBUS_IT_TCI I2C_CR1_TCIE

Definition at line 350 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)

Definition at line 356 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Abort_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Disable_IRQ(), SMBUS_Enable_IRQ(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_IT_TXI I2C_CR1_TXIE

Definition at line 355 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Disable_IRQ(), and SMBUS_Enable_IRQ().

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMBUS Flag definition

Defines
SMBUS Flag definition
SMBUS Exported Constants

Flag definition Elements values convention: 0xXXXXYYYY. More...

Defines

#define | SMBUS_FLAG_TXE I2C_ISR_TXE
#define | SMBUS_FLAG_TXIS I2C_ISR_TXIS
#define | SMBUS_FLAG_RXNE I2C_ISR_RXNE
#define | SMBUS_FLAG_ADDR I2C_ISR_ADDR
#define | SMBUS_FLAG_AF I2C_ISR_NACKF
#define | SMBUS_FLAG_STOPF I2C_ISR_STOPF
#define | SMBUS_FLAG_TC I2C_ISR_TC
#define | SMBUS_FLAG_TCR I2C_ISR_TCR
#define | SMBUS_FLAG_BERR I2C_ISR_BERR
#define | SMBUS_FLAG_ARLO I2C_ISR_ARLO
#define | SMBUS_FLAG_OVR I2C_ISR_OVR
#define | SMBUS_FLAG_PECERR I2C_ISR_PECERR
#define | SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define | SMBUS_FLAG_ALERT I2C_ISR_ALERT
#define | SMBUS_FLAG_BUSY I2C_ISR_BUSY
#define | SMBUS_FLAG_DIR I2C_ISR_DIR

Detailed Description

Flag definition Elements values convention: 0xXXXXYYYY.

  • XXXXXXXX : Flag mask

Define Documentation

#define SMBUS_FLAG_ADDR I2C_ISR_ADDR

Definition at line 374 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), and SMBUS_Slave_ISR().

#define SMBUS_FLAG_AF I2C_ISR_NACKF

Definition at line 375 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_IsDeviceReady(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_FLAG_ALERT I2C_ISR_ALERT

Definition at line 384 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_EnableAlert_IT(), and SMBUS_ITErrorHandler().

#define SMBUS_FLAG_ARLO I2C_ISR_ARLO

Definition at line 380 of file stm32wbxx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define SMBUS_FLAG_BERR I2C_ISR_BERR

Definition at line 379 of file stm32wbxx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define SMBUS_FLAG_BUSY I2C_ISR_BUSY

Definition at line 385 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_IsDeviceReady().

#define SMBUS_FLAG_DIR I2C_ISR_DIR

Definition at line 386 of file stm32wbxx_hal_smbus.h.

#define SMBUS_FLAG_OVR I2C_ISR_OVR

Definition at line 381 of file stm32wbxx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define SMBUS_FLAG_PECERR I2C_ISR_PECERR

Definition at line 382 of file stm32wbxx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define SMBUS_FLAG_RXNE I2C_ISR_RXNE

Definition at line 373 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_FLAG_STOPF I2C_ISR_STOPF

Definition at line 376 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), HAL_SMBUS_IsDeviceReady(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_FLAG_TC I2C_ISR_TC

Definition at line 377 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), and SMBUS_Master_ISR().

#define SMBUS_FLAG_TCR I2C_ISR_TCR

Definition at line 378 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT

Definition at line 383 of file stm32wbxx_hal_smbus.h.

Referenced by SMBUS_ITErrorHandler().

#define SMBUS_FLAG_TXE I2C_ISR_TXE

Definition at line 371 of file stm32wbxx_hal_smbus.h.

#define SMBUS_FLAG_TXIS I2C_ISR_TXIS

Definition at line 372 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMBUS Exported Macros

Defines
SMBUS Exported Macros
SMBUS

Defines

#define | __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__)
Reset SMBUS handle state.
#define | __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
Enable the specified SMBUS interrupts.
#define | __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
Disable the specified SMBUS interrupts.
#define | __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified SMBUS interrupt source is enabled or not.
#define | SMBUS_FLAG_MASK (0x0001FFFFU)
Check whether the specified SMBUS flag is set or not.
#define | __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
#define | __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
#define | __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Enable the specified SMBUS peripheral.
#define | __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Disable the specified SMBUS peripheral.
#define | __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
Generate a Non-Acknowledge SMBUS peripheral in Slave mode.

Define Documentation

#define __HAL_SMBUS_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
__FLAG__ specifies the flag to clear. This parameter can be any combination of the following values:
  • SMBUS_FLAG_ADDR Address matched (slave mode)
  • SMBUS_FLAG_AF NACK received flag
  • SMBUS_FLAG_STOPF STOP detection flag
  • SMBUS_FLAG_BERR Bus error
  • SMBUS_FLAG_ARLO Arbitration lost
  • SMBUS_FLAG_OVR Overrun/Underrun
  • SMBUS_FLAG_PECERR PEC error in reception
  • SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
  • SMBUS_FLAG_ALERT SMBus alert
Return values:
None

Definition at line 504 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_EnableAlert_IT(), HAL_SMBUS_IsDeviceReady(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_ITErrorHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define __HAL_SMBUS_DISABLE ( __HANDLE__ ) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))

Disable the specified SMBUS peripheral.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
Return values:
None

Definition at line 516 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigAnalogFilter(), HAL_SMBUS_ConfigDigitalFilter(), HAL_SMBUS_DeInit(), HAL_SMBUS_Init(), and SMBUS_Master_ISR().

#define __HAL_SMBUS_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))

Disable the specified SMBUS interrupts.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
__INTERRUPT__ specifies the interrupt source to disable. This parameter can be one of the following values:
  • SMBUS_IT_ERRI Errors interrupt enable
  • SMBUS_IT_TCI Transfer complete interrupt enable
  • SMBUS_IT_STOPI STOP detection interrupt enable
  • SMBUS_IT_NACKI NACK received interrupt enable
  • SMBUS_IT_ADDRI Address match interrupt enable
  • SMBUS_IT_RXI RX interrupt enable
  • SMBUS_IT_TXI TX interrupt enable
Return values:
None

Definition at line 444 of file stm32wbxx_hal_smbus.h.

Referenced by SMBUS_Disable_IRQ(), and SMBUS_Slave_ISR().

#define __HAL_SMBUS_ENABLE ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))

Enable the specified SMBUS peripheral.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
Return values:
None

Definition at line 510 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigAnalogFilter(), HAL_SMBUS_ConfigDigitalFilter(), HAL_SMBUS_Init(), and SMBUS_Master_ISR().

#define __HAL_SMBUS_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))

Enable the specified SMBUS interrupts.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
__INTERRUPT__ specifies the interrupt source to enable. This parameter can be one of the following values:
  • SMBUS_IT_ERRI Errors interrupt enable
  • SMBUS_IT_TCI Transfer complete interrupt enable
  • SMBUS_IT_STOPI STOP detection interrupt enable
  • SMBUS_IT_NACKI NACK received interrupt enable
  • SMBUS_IT_ADDRI Address match interrupt enable
  • SMBUS_IT_RXI RX interrupt enable
  • SMBUS_IT_TXI TX interrupt enable
Return values:
None

Definition at line 428 of file stm32wbxx_hal_smbus.h.

Referenced by SMBUS_Enable_IRQ().

#define __HAL_SMBUS_GENERATE_NACK ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))

Generate a Non-Acknowledge SMBUS peripheral in Slave mode.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
Return values:
None

Definition at line 522 of file stm32wbxx_hal_smbus.h.

#define __HAL_SMBUS_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)

Definition at line 486 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_IsDeviceReady(), SMBUS_Slave_ISR(), and SMBUS_WaitOnFlagUntilTimeout().

#define __HAL_SMBUS_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified SMBUS interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
__INTERRUPT__ specifies the SMBUS interrupt source to check. This parameter can be one of the following values:
  • SMBUS_IT_ERRI Errors interrupt enable
  • SMBUS_IT_TCI Transfer complete interrupt enable
  • SMBUS_IT_STOPI STOP detection interrupt enable
  • SMBUS_IT_NACKI NACK received interrupt enable
  • SMBUS_IT_ADDRI Address match interrupt enable
  • SMBUS_IT_RXI RX interrupt enable
  • SMBUS_IT_TXI TX interrupt enable
Return values:
The new state of __IT__ (SET or RESET).

Definition at line 460 of file stm32wbxx_hal_smbus.h.

#define __HAL_SMBUS_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                   \
                                                                (__HANDLE__)->State = HAL_SMBUS_STATE_RESET;       \
                                                                (__HANDLE__)->MspInitCallback = NULL;            \
                                                                (__HANDLE__)->MspDeInitCallback = NULL;          \
                                                             } while(0)

Reset SMBUS handle state.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
Return values:
None

Definition at line 405 of file stm32wbxx_hal_smbus.h.

#define SMBUS_FLAG_MASK (0x0001FFFFU)

Check whether the specified SMBUS flag is set or not.

Parameters:
__HANDLE__ specifies the SMBUS Handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • SMBUS_FLAG_TXE Transmit data register empty
  • SMBUS_FLAG_TXIS Transmit interrupt status
  • SMBUS_FLAG_RXNE Receive data register not empty
  • SMBUS_FLAG_ADDR Address matched (slave mode)
  • SMBUS_FLAG_AF NACK received flag
  • SMBUS_FLAG_STOPF STOP detection flag
  • SMBUS_FLAG_TC Transfer complete (master mode)
  • SMBUS_FLAG_TCR Transfer complete reload
  • SMBUS_FLAG_BERR Bus error
  • SMBUS_FLAG_ARLO Arbitration lost
  • SMBUS_FLAG_OVR Overrun/Underrun
  • SMBUS_FLAG_PECERR PEC error in reception
  • SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
  • SMBUS_FLAG_ALERT SMBus alert
  • SMBUS_FLAG_BUSY Bus busy
  • SMBUS_FLAG_DIR Transfer direction (slave mode)
Return values:
The new state of __FLAG__ (SET or RESET).

Definition at line 485 of file stm32wbxx_hal_smbus.h.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMBUS Private Macros

Defines
SMBUS Private Macros
SMBUS

Defines

#define | IS_SMBUS_ANALOG_FILTER(FILTER)
#define | IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define | IS_SMBUS_ADDRESSING_MODE(MODE)
#define | IS_SMBUS_DUAL_ADDRESS(ADDRESS)
#define | IS_SMBUS_OWN_ADDRESS2_MASK(MASK)
#define | IS_SMBUS_GENERAL_CALL(CALL)
#define | IS_SMBUS_NO_STRETCH(STRETCH)
#define | IS_SMBUS_PEC(PEC)
#define | IS_SMBUS_PERIPHERAL_MODE(MODE)
#define | IS_SMBUS_TRANSFER_MODE(MODE)
#define | IS_SMBUS_TRANSFER_REQUEST(REQUEST)
#define | IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST)
#define | IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)
#define | SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
#define | SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
#define | SMBUS_GENERATE_START(__ADDMODE__, __ADDRESS__)
#define | SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
#define | SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
#define | SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define | SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
#define | SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
#define | SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
#define | SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
#define | IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define | IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)

Define Documentation

#define IS_SMBUS_ADDRESSING_MODE ( MODE )
Value:
(((MODE) == SMBUS_ADDRESSINGMODE_7BIT)  || \
                                                          ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))

Definition at line 541 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_ANALOG_FILTER ( FILTER )
Value:
(((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
                                                          ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))

Definition at line 536 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigAnalogFilter(), and HAL_SMBUS_Init().

#define IS_SMBUS_DIGITAL_FILTER ( FILTER ) ((FILTER) <= 0x0000000FU)

Definition at line 539 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_ConfigDigitalFilter().

#define IS_SMBUS_DUAL_ADDRESS ( ADDRESS )
Value:
(((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
                                                          ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))

Definition at line 544 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_GENERAL_CALL ( CALL )
Value:
(((CALL) == SMBUS_GENERALCALL_DISABLE) || \
                                                         ((CALL) == SMBUS_GENERALCALL_ENABLE))

Definition at line 556 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_NO_STRETCH ( STRETCH )
Value:
(((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
                                                         ((STRETCH) == SMBUS_NOSTRETCH_ENABLE))

Definition at line 559 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_OWN_ADDRESS1 ( ADDRESS1 ) ((ADDRESS1) <= 0x000003FFU)

Definition at line 613 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_OWN_ADDRESS2 ( ADDRESS2 ) ((ADDRESS2) <= (uint16_t)0x00FFU)

Definition at line 614 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_OWN_ADDRESS2_MASK ( MASK )
Value:
(((MASK) == SMBUS_OA2_NOMASK)    || \
                                                         ((MASK) == SMBUS_OA2_MASK01)    || \
                                                         ((MASK) == SMBUS_OA2_MASK02)    || \
                                                         ((MASK) == SMBUS_OA2_MASK03)    || \
                                                         ((MASK) == SMBUS_OA2_MASK04)    || \
                                                         ((MASK) == SMBUS_OA2_MASK05)    || \
                                                         ((MASK) == SMBUS_OA2_MASK06)    || \
                                                         ((MASK) == SMBUS_OA2_MASK07))

Definition at line 547 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_PEC ( PEC )
Value:
(((PEC) == SMBUS_PEC_DISABLE) || \
                                                          ((PEC) == SMBUS_PEC_ENABLE))

Definition at line 562 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_PERIPHERAL_MODE ( MODE )
Value:
(((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST)    || \
                                                          ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE)  || \
                                                          ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))

Definition at line 565 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Init().

#define IS_SMBUS_TRANSFER_MODE ( MODE )
Value:
(((MODE) == SMBUS_RELOAD_MODE)                           || \
                                                          ((MODE) == SMBUS_AUTOEND_MODE)                         || \
                                                          ((MODE) == SMBUS_SOFTEND_MODE)                         || \
                                                          ((MODE) == SMBUS_SENDPEC_MODE)                         || \
                                                          ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE))   || \
                                                          ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))  || \
                                                          ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE))   || \
                                                          ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))

Definition at line 569 of file stm32wbxx_hal_smbus.h.

Referenced by SMBUS_TransferConfig().

#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST ( REQUEST )
Value:
(IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)       || \
                                                          ((REQUEST) == SMBUS_FIRST_FRAME)                       || \
                                                          ((REQUEST) == SMBUS_NEXT_FRAME)                        || \
                                                          ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC)       || \
                                                          ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC)                 || \
                                                          ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)     || \
                                                          ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))

Definition at line 585 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), and HAL_SMBUS_Slave_Transmit_IT().

#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST ( REQUEST )
Value:
(((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC)                || \
                                                          ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)       || \
                                                          ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC)              || \
                                                          ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))

Definition at line 593 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Receive_IT(), and HAL_SMBUS_Master_Transmit_IT().

#define IS_SMBUS_TRANSFER_REQUEST ( REQUEST )
Value:
(((REQUEST) == SMBUS_GENERATE_STOP)              || \
                                                          ((REQUEST) == SMBUS_GENERATE_START_READ)       || \
                                                          ((REQUEST) == SMBUS_GENERATE_START_WRITE)      || \
                                                          ((REQUEST) == SMBUS_NO_STARTSTOP))

Definition at line 579 of file stm32wbxx_hal_smbus.h.

Referenced by SMBUS_TransferConfig().

#define SMBUS_CHECK_FLAG | ( | __ISR__,
 |  | __FLAG__
 | ) | ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)

Definition at line 610 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_CHECK_IT_SOURCE | ( | __CR1__,
 |  | __IT__
 | ) | ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)

Definition at line 611 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_EV_IRQHandler().

#define SMBUS_GENERATE_START | ( | __ADDMODE__,
 |  | __ADDRESS__
 | ) |
Value:
(((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
                                                                  (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))

Definition at line 601 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_IsDeviceReady().

#define SMBUS_GET_ADDR_MATCH ( __HANDLE__ ) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)

Definition at line 604 of file stm32wbxx_hal_smbus.h.

Referenced by SMBUS_Slave_ISR().

#define SMBUS_GET_ALERT_ENABLED ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)

Definition at line 608 of file stm32wbxx_hal_smbus.h.

Referenced by SMBUS_Disable_IRQ().

#define SMBUS_GET_DIR ( __HANDLE__ ) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)

Definition at line 605 of file stm32wbxx_hal_smbus.h.

Referenced by SMBUS_Slave_ISR().

#define SMBUS_GET_PEC_MODE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)

Definition at line 607 of file stm32wbxx_hal_smbus.h.

Referenced by HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

#define SMBUS_GET_STOP_MODE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)

Definition at line 606 of file stm32wbxx_hal_smbus.h.

Referenced by SMBUS_Master_ISR().

#define SMBUS_RESET_CR1 ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))

Definition at line 598 of file stm32wbxx_hal_smbus.h.

#define SMBUS_RESET_CR2 ( __HANDLE__ ) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))

Definition at line 599 of file stm32wbxx_hal_smbus.h.

Referenced by SMBUS_Master_ISR(), and SMBUS_Slave_ISR().

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SPI Private Constants

Defines
SPI Private Constants
SPI

Defines

#define SPI_DEFAULT_TIMEOUT 100U

Define Documentation

#define SPI_DEFAULT_TIMEOUT 100U

Definition at line 219 of file stm32wbxx_hal_spi.c.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), and SPI_DMATxAbortCallback().

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SPI Private Functions

Functions
SPI Private Functions
SPI

Private functions. More...

Functions

static void | SPI_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit process complete callback.
static void | SPI_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI receive process complete callback.
static void | SPI_DMATransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit receive process complete callback.
static void | SPI_DMAHalfTransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI half transmit process complete callback.
static void | SPI_DMAHalfReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI half receive process complete callback.
static void | SPI_DMAHalfTransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI half transmit receive process complete callback.
static void | SPI_DMAError (DMA_HandleTypeDef *hdma)
DMA SPI communication error callback.
static void | SPI_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA SPI communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | SPI_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SPI Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | SPI_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SPI Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static HAL_StatusTypeDef | SPI_WaitFlagStateUntilTimeout (SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, uint32_t Timeout, uint32_t Tickstart)
Handle SPI Communication Timeout.
static HAL_StatusTypeDef | SPI_WaitFifoStateUntilTimeout (SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
Handle SPI FIFO Communication Timeout.
static void | SPI_TxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Handle the data 8-bit transmit in Interrupt mode.
static void | SPI_TxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Handle the data 16-bit transmit in Interrupt mode.
static void | SPI_RxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Manage the receive 8-bit in Interrupt context.
static void | SPI_RxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Manage the 16-bit receive in Interrupt context.
static void | SPI_2linesRxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Rx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesTxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Tx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesTxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Tx 16-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesRxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Rx 16-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_RxISR_8BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 8-bit receive in Interrupt context.
static void | SPI_RxISR_16BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 16-bit receive in Interrupt context.
static void | SPI_2linesRxISR_8BITCRC (struct __SPI_HandleTypeDef *hspi)
Rx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesRxISR_16BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
static void | SPI_AbortRx_ISR (SPI_HandleTypeDef *hspi)
Handle abort a Rx transaction.
static void | SPI_AbortTx_ISR (SPI_HandleTypeDef *hspi)
Handle abort a Tx or Rx/Tx transaction.
static void | SPI_CloseRxTx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the RXTX transaction.
static void | SPI_CloseRx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the RX transaction.
static void | SPI_CloseTx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the TX transaction.
static HAL_StatusTypeDef | SPI_EndRxTransaction (SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
Handle the check of the RX transaction complete.
static HAL_StatusTypeDef | SPI_EndRxTxTransaction (SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
Handle the check of the RXTX or TX transaction complete.

Detailed Description

Private functions.

Function Documentation

static void SPI_2linesRxISR_16BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Rx 16-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3544 of file stm32wbxx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_2linesRxISR_16BITCRC(), SPI_CloseRxTx_ISR(), SPI_CRCCALCULATION_ENABLE, SPI_IT_RXNE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_IT().

static void SPI_2linesRxISR_16BITCRC ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3578 of file stm32wbxx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::Instance, SPI_CloseRxTx_ISR(), and SPI_IT_RXNE.

Referenced by SPI_2linesRxISR_16BIT().

static void SPI_2linesRxISR_8BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Rx 8-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3419 of file stm32wbxx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_2linesRxISR_8BITCRC(), SPI_CloseRxTx_ISR(), SPI_CRCCALCULATION_ENABLE, SPI_IT_ERR, SPI_IT_RXNE, SPI_RXFIFO_THRESHOLD, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_IT().

static void SPI_2linesRxISR_8BITCRC ( struct __SPI_HandleTypeDef * hspi ) [static]

Rx 8-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3470 of file stm32wbxx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::CRCSize, __SPI_HandleTypeDef::Instance, SPI_CloseRxTx_ISR(), SPI_IT_ERR, SPI_IT_RXNE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by SPI_2linesRxISR_8BIT().

static void SPI_2linesTxISR_16BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Tx 16-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3596 of file stm32wbxx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRxTx_ISR(), SPI_CRCCALCULATION_ENABLE, SPI_IT_TXE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_IT().

static void SPI_2linesTxISR_8BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Tx 8-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3497 of file stm32wbxx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRxTx_ISR(), SPI_CRCCALCULATION_ENABLE, SPI_IT_TXE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_IT().

static void SPI_AbortRx_ISR ( SPI_HandleTypeDef * hspi ) [static]

Handle abort a Rx transaction.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 4153 of file stm32wbxx_hal_spi.c.

References __HAL_SPI_DISABLE, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_ABORT, HAL_SPI_STATE_ABORT, __SPI_HandleTypeDef::Instance, SPI_DEFAULT_TIMEOUT, SPI_FLAG_BSY, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_WaitFifoStateUntilTimeout(), SPI_WaitFlagStateUntilTimeout(), and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Abort(), and HAL_SPI_Abort_IT().

static void SPI_AbortTx_ISR ( SPI_HandleTypeDef * hspi ) [static]

Handle abort a Tx or Rx/Tx transaction.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 4197 of file stm32wbxx_hal_spi.c.

References __HAL_SPI_DISABLE, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_ABORT, HAL_SPI_STATE_ABORT, __SPI_HandleTypeDef::Instance, SPI_DEFAULT_TIMEOUT, SPI_EndRxTxTransaction(), SPI_FLAG_BSY, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_WaitFifoStateUntilTimeout(), SPI_WaitFlagStateUntilTimeout(), and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Abort(), and HAL_SPI_Abort_IT().

static void SPI_CloseRx_ISR ( SPI_HandleTypeDef * hspi ) [static]

Handle the end of the RX transaction.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 4047 of file stm32wbxx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_DISABLE_IT, __HAL_SPI_GET_FLAG, __SPI_HandleTypeDef::ErrorCallback, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_RxCpltCallback(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::RxCpltCallback, SPI_DEFAULT_TIMEOUT, SPI_EndRxTransaction(), SPI_FLAG_CRCERR, SPI_IT_ERR, SPI_IT_RXNE, and __SPI_HandleTypeDef::State.

Referenced by SPI_RxISR_16BIT(), SPI_RxISR_16BITCRC(), SPI_RxISR_8BIT(), and SPI_RxISR_8BITCRC().

static void SPI_CloseRxTx_ISR ( SPI_HandleTypeDef * hspi ) [static]

Handle the end of the RXTX transaction.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3970 of file stm32wbxx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_DISABLE_IT, __HAL_SPI_GET_FLAG, __SPI_HandleTypeDef::ErrorCallback, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_RxCpltCallback(), HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_READY, HAL_SPI_TxRxCpltCallback(), __SPI_HandleTypeDef::RxCpltCallback, SPI_DEFAULT_TIMEOUT, SPI_EndRxTxTransaction(), SPI_FLAG_CRCERR, SPI_IT_ERR, __SPI_HandleTypeDef::State, and __SPI_HandleTypeDef::TxRxCpltCallback.

Referenced by SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_16BITCRC(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_2linesTxISR_16BIT(), and SPI_2linesTxISR_8BIT().

static void SPI_CloseTx_ISR ( SPI_HandleTypeDef * hspi ) [static]

Handle the end of the TX transaction.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 4104 of file stm32wbxx_hal_spi.c.

References __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCallback, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_READY, HAL_SPI_TxCpltCallback(), __SPI_HandleTypeDef::Init, SPI_DEFAULT_TIMEOUT, SPI_DIRECTION_2LINES, SPI_EndRxTxTransaction(), SPI_IT_ERR, SPI_IT_TXE, __SPI_HandleTypeDef::State, and __SPI_HandleTypeDef::TxCpltCallback.

Referenced by SPI_TxISR_16BIT(), and SPI_TxISR_8BIT().

static void SPI_DMAAbortOnError ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3266 of file stm32wbxx_hal_spi.c.

References __SPI_HandleTypeDef::ErrorCallback, HAL_SPI_ErrorCallback(), __SPI_HandleTypeDef::RxXferCount, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_IRQHandler().

static void SPI_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI communication error callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 3243 of file stm32wbxx_hal_spi.c.

References __SPI_HandleTypeDef::ErrorCallback, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_DMA, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Instance, and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

static void SPI_DMAHalfReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI half receive process complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 3207 of file stm32wbxx_hal_spi.c.

References HAL_SPI_RxHalfCpltCallback(), and __SPI_HandleTypeDef::RxHalfCpltCallback.

Referenced by HAL_SPI_Receive_DMA(), and HAL_SPI_TransmitReceive_DMA().

static void SPI_DMAHalfTransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI half transmit process complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 3189 of file stm32wbxx_hal_spi.c.

References HAL_SPI_TxHalfCpltCallback(), and __SPI_HandleTypeDef::TxHalfCpltCallback.

Referenced by HAL_SPI_Transmit_DMA().

static void SPI_DMAHalfTransmitReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI half transmit receive process complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 3225 of file stm32wbxx_hal_spi.c.

References HAL_SPI_TxRxHalfCpltCallback(), and __SPI_HandleTypeDef::TxRxHalfCpltCallback.

Referenced by HAL_SPI_TransmitReceive_DMA().

static void SPI_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI receive process complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 3005 of file stm32wbxx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_DISABLE_IT, __HAL_SPI_GET_FLAG, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, SPI_InitTypeDef::DataSize, __SPI_HandleTypeDef::ErrorCallback, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_RxCpltCallback(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __DMA_HandleTypeDef::Instance, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxCpltCallback, __SPI_HandleTypeDef::RxXferCount, SPI_CRC_LENGTH_16BIT, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DEFAULT_TIMEOUT, SPI_EndRxTransaction(), SPI_FLAG_CRCERR, SPI_FLAG_RXNE, SPI_IT_ERR, SPI_WaitFlagStateUntilTimeout(), and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Receive_DMA(), and HAL_SPI_TransmitReceive_DMA().

static void SPI_DMARxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Tx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3354 of file stm32wbxx_hal_spi.c.

References __HAL_SPI_CLEAR_FREFLAG, __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_DISABLE, __SPI_HandleTypeDef::AbortCpltCallback, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_AbortCpltCallback(), HAL_SPI_ERROR_ABORT, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxXferCount, SPI_DEFAULT_TIMEOUT, SPI_FLAG_BSY, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_WaitFifoStateUntilTimeout(), SPI_WaitFlagStateUntilTimeout(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_SPI_Abort_IT().

static void SPI_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI transmit process complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2948 of file stm32wbxx_hal_spi.c.

References __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCallback, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_READY, HAL_SPI_TxCpltCallback(), __SPI_HandleTypeDef::Init, __DMA_HandleTypeDef::Instance, __SPI_HandleTypeDef::Instance, SPI_DEFAULT_TIMEOUT, SPI_DIRECTION_2LINES, SPI_EndRxTxTransaction(), SPI_IT_ERR, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxCpltCallback, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_Transmit_DMA().

static void SPI_DMATransmitReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI transmit receive process complete callback.

Parameters:
hdma pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 3100 of file stm32wbxx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_DISABLE_IT, __HAL_SPI_GET_FLAG, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, SPI_InitTypeDef::DataSize, __SPI_HandleTypeDef::ErrorCallback, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_READY, HAL_SPI_TxRxCpltCallback(), __SPI_HandleTypeDef::Init, __DMA_HandleTypeDef::Instance, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxXferCount, SPI_CRC_LENGTH_8BIT, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DEFAULT_TIMEOUT, SPI_EndRxTxTransaction(), SPI_FLAG_CRCERR, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_FRLVL_QUARTER_FULL, SPI_IT_ERR, SPI_WaitFifoStateUntilTimeout(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxRxCpltCallback, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_DMA().

static void SPI_DMATxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Rx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3288 of file stm32wbxx_hal_spi.c.

References __HAL_SPI_CLEAR_FREFLAG, __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_DISABLE, __SPI_HandleTypeDef::AbortCpltCallback, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_AbortCpltCallback(), HAL_SPI_ERROR_ABORT, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxXferCount, SPI_DEFAULT_TIMEOUT, SPI_EndRxTxTransaction(), SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_WaitFifoStateUntilTimeout(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_SPI_Abort_IT().

static HAL_StatusTypeDef SPI_EndRxTransaction | ( | SPI_HandleTypeDef * | hspi,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Handle the check of the RX transaction complete.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Timeout | Timeout duration
Tickstart | tick start value
Return values:
HAL status

Definition at line 3902 of file stm32wbxx_hal_spi.c.

References __HAL_SPI_DISABLE, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_FLAG, __SPI_HandleTypeDef::Init, SPI_InitTypeDef::Mode, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES_RXONLY, SPI_FLAG_BSY, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_MODE_MASTER, SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

Referenced by HAL_SPI_Receive(), SPI_CloseRx_ISR(), and SPI_DMAReceiveCplt().

static HAL_StatusTypeDef SPI_EndRxTxTransaction | ( | SPI_HandleTypeDef * | hspi,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Handle the check of the RXTX or TX transaction complete.

Parameters:
hspi | SPI handle
Timeout | Timeout duration
Tickstart | tick start value
Return values:
HAL status

Definition at line 3938 of file stm32wbxx_hal_spi.c.

References __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_FLAG, SPI_FLAG_BSY, SPI_FLAG_FRLVL, SPI_FLAG_FTLVL, SPI_FRLVL_EMPTY, SPI_FTLVL_EMPTY, SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

Referenced by HAL_SPI_Abort(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), SPI_AbortTx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), and SPI_DMATxAbortCallback().

static void SPI_RxISR_16BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the 16-bit receive in Interrupt context.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3706 of file stm32wbxx_hal_spi.c.

References SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRx_ISR(), SPI_CRCCALCULATION_ENABLE, and SPI_RxISR_16BITCRC().

Referenced by HAL_SPI_Receive_IT().

static void SPI_RxISR_16BITCRC ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the CRC 16-bit receive in Interrupt context.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3688 of file stm32wbxx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::Instance, SPI_CloseRx_ISR(), SPI_IT_ERR, and SPI_IT_RXNE.

Referenced by SPI_RxISR_16BIT().

static void SPI_RxISR_8BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the receive 8-bit in Interrupt context.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3654 of file stm32wbxx_hal_spi.c.

References SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRx_ISR(), SPI_CRCCALCULATION_ENABLE, and SPI_RxISR_8BITCRC().

Referenced by HAL_SPI_Receive_IT().

static void SPI_RxISR_8BITCRC ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the CRC 8-bit receive in Interrupt context.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3634 of file stm32wbxx_hal_spi.c.

References __SPI_HandleTypeDef::CRCSize, __SPI_HandleTypeDef::Instance, and SPI_CloseRx_ISR().

Referenced by SPI_RxISR_8BIT().

static void SPI_TxISR_16BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Handle the data 16-bit transmit in Interrupt mode.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3764 of file stm32wbxx_hal_spi.c.

References SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, SPI_CloseTx_ISR(), SPI_CRCCALCULATION_ENABLE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_Transmit_IT().

static void SPI_TxISR_8BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Handle the data 8-bit transmit in Interrupt mode.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3739 of file stm32wbxx_hal_spi.c.

References SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, SPI_CloseTx_ISR(), SPI_CRCCALCULATION_ENABLE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_Transmit_IT().

static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout | ( | SPI_HandleTypeDef * | hspi,
 |  | uint32_t | Fifo,
 |  | uint32_t | State,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Handle SPI FIFO Communication Timeout.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Fifo | Fifo to check
State | Fifo state to check
Timeout | Timeout duration
Tickstart | tick start value
Return values:
HAL status

Definition at line 3846 of file stm32wbxx_hal_spi.c.

References __HAL_SPI_DISABLE, __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::Direction, HAL_GetTick(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, SPI_InitTypeDef::Mode, SPI_CRCCALCULATION_ENABLE, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES_RXONLY, SPI_FRLVL_EMPTY, SPI_IT_ERR, SPI_IT_RXNE, SPI_IT_TXE, SPI_MODE_MASTER, SPI_RESET_CRC, and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Abort(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DMARxAbortCallback(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout | ( | SPI_HandleTypeDef * | hspi,
 |  | uint32_t | Flag,
 |  | FlagStatus | State,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Handle SPI Communication Timeout.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Flag | SPI flag to check
State | flag state to check
Timeout | Timeout duration
Tickstart | tick start value
Return values:
HAL status

Definition at line 3794 of file stm32wbxx_hal_spi.c.

References __HAL_SPI_DISABLE, __HAL_SPI_DISABLE_IT, __HAL_SPI_GET_FLAG, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::Direction, HAL_GetTick(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, SPI_InitTypeDef::Mode, SPI_CRCCALCULATION_ENABLE, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES_RXONLY, SPI_IT_ERR, SPI_IT_RXNE, SPI_IT_TXE, SPI_MODE_MASTER, SPI_RESET_CRC, and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Abort(), HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SPI Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SPI_Init (SPI_HandleTypeDef *hspi)
Initialize the SPI according to the specified parameters in the SPI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SPI_DeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI peripheral.
__weak void | HAL_SPI_MspInit (SPI_HandleTypeDef *hspi)
Initialize the SPI MSP.
__weak void | HAL_SPI_MspDeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI MSP.
HAL_StatusTypeDef | HAL_SPI_RegisterCallback (SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback)
Register a User SPI Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SPI_UnRegisterCallback (SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
Unregister an SPI Callback SPI callback is redirected to the weak predefined callback.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          de-initialize the SPIx peripheral:

      (+) User must implement HAL_SPI_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).

      (+) Call the function HAL_SPI_Init() to configure the selected device with
          the selected configuration:
        (++) Mode
        (++) Direction
        (++) Data Size
        (++) Clock Polarity and Phase
        (++) NSS Management
        (++) BaudRate Prescaler
        (++) FirstBit
        (++) TIMode
        (++) CRC Calculation
        (++) CRC Polynomial if CRC enabled
        (++) CRC Length, used only with Data8 and Data16
        (++) FIFO reception threshold

      (+) Call the function HAL_SPI_DeInit() to restore the default configuration
          of the selected SPIx peripheral.

Function Documentation

HAL_StatusTypeDef HAL_SPI_DeInit ( SPI_HandleTypeDef * hspi )

De-Initialize the SPI peripheral.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
HAL status

Definition at line 461 of file stm32wbxx_hal_spi.c.

References __HAL_SPI_DISABLE, assert_param, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_MspDeInit(), HAL_SPI_STATE_BUSY, HAL_SPI_STATE_RESET, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::MspDeInitCallback, and __SPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SPI_Init ( SPI_HandleTypeDef * hspi )

Initialize the SPI according to the specified parameters in the SPI_InitTypeDef and initialize the associated handle.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
HAL status

Definition at line 316 of file stm32wbxx_hal_spi.c.

References __HAL_SPI_DISABLE, __SPI_HandleTypeDef::AbortCpltCallback, assert_param, SPI_InitTypeDef::BaudRatePrescaler, SPI_InitTypeDef::CLKPhase, SPI_InitTypeDef::CLKPolarity, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, SPI_InitTypeDef::CRCPolynomial, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCallback, __SPI_HandleTypeDef::ErrorCode, SPI_InitTypeDef::FirstBit, HAL_SPI_AbortCpltCallback(), HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_MspInit(), HAL_SPI_RxCpltCallback(), HAL_SPI_RxHalfCpltCallback(), HAL_SPI_STATE_BUSY, HAL_SPI_STATE_READY, HAL_SPI_STATE_RESET, HAL_SPI_TxCpltCallback(), HAL_SPI_TxHalfCpltCallback(), HAL_SPI_TxRxCpltCallback(), HAL_SPI_TxRxHalfCpltCallback(), __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_BAUDRATE_PRESCALER, IS_SPI_CPHA, IS_SPI_CPOL, IS_SPI_CRC_CALCULATION, IS_SPI_CRC_LENGTH, IS_SPI_CRC_POLYNOMIAL, IS_SPI_DATASIZE, IS_SPI_DIRECTION, IS_SPI_FIRST_BIT, IS_SPI_MODE, IS_SPI_NSS, IS_SPI_NSSP, IS_SPI_TIMODE, __SPI_HandleTypeDef::Lock, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::MspInitCallback, SPI_InitTypeDef::NSS, SPI_InitTypeDef::NSSPMode, __SPI_HandleTypeDef::RxCpltCallback, __SPI_HandleTypeDef::RxHalfCpltCallback, SPI_CRC_LENGTH_16BIT, SPI_CRC_LENGTH_8BIT, SPI_CRC_LENGTH_DATASIZE, SPI_CRCCALCULATION_DISABLE, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_RXFIFO_THRESHOLD_HF, SPI_RXFIFO_THRESHOLD_QF, SPI_TIMODE_DISABLE, __SPI_HandleTypeDef::State, SPI_InitTypeDef::TIMode, __SPI_HandleTypeDef::TxCpltCallback, __SPI_HandleTypeDef::TxHalfCpltCallback, __SPI_HandleTypeDef::TxRxCpltCallback, and __SPI_HandleTypeDef::TxRxHalfCpltCallback.

void HAL_SPI_MspDeInit ( SPI_HandleTypeDef * hspi )

De-Initialize the SPI MSP.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 521 of file stm32wbxx_hal_spi.c.

Referenced by HAL_SPI_DeInit(), and HAL_SPI_UnRegisterCallback().

void HAL_SPI_MspInit ( SPI_HandleTypeDef * hspi )

Initialize the SPI MSP.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 505 of file stm32wbxx_hal_spi.c.

Referenced by HAL_SPI_Init(), and HAL_SPI_UnRegisterCallback().

HAL_StatusTypeDef HAL_SPI_RegisterCallback | ( | SPI_HandleTypeDef * | hspi,
 |  | HAL_SPI_CallbackIDTypeDef | CallbackID,
 |  | pSPI_CallbackTypeDef | pCallback
 | ) |  |

Register a User SPI Callback To be used instead of the weak predefined callback.

Parameters:
hspi | Pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI.
CallbackID | ID of the callback to be registered
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 541 of file stm32wbxx_hal_spi.c.

References __SPI_HandleTypeDef::AbortCpltCallback, __SPI_HandleTypeDef::ErrorCallback, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ABORT_CB_ID, HAL_SPI_ERROR_CB_ID, HAL_SPI_ERROR_INVALID_CALLBACK, HAL_SPI_MSPDEINIT_CB_ID, HAL_SPI_MSPINIT_CB_ID, HAL_SPI_RX_COMPLETE_CB_ID, HAL_SPI_RX_HALF_COMPLETE_CB_ID, HAL_SPI_STATE_READY, HAL_SPI_STATE_RESET, HAL_SPI_TX_COMPLETE_CB_ID, HAL_SPI_TX_HALF_COMPLETE_CB_ID, HAL_SPI_TX_RX_COMPLETE_CB_ID, HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID, __SPI_HandleTypeDef::MspDeInitCallback, __SPI_HandleTypeDef::MspInitCallback, __SPI_HandleTypeDef::RxCpltCallback, __SPI_HandleTypeDef::RxHalfCpltCallback, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxCpltCallback, __SPI_HandleTypeDef::TxHalfCpltCallback, __SPI_HandleTypeDef::TxRxCpltCallback, and __SPI_HandleTypeDef::TxRxHalfCpltCallback.

HAL_StatusTypeDef HAL_SPI_UnRegisterCallback | ( | SPI_HandleTypeDef * | hspi,
 |  | HAL_SPI_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an SPI Callback SPI callback is redirected to the weak predefined callback.

Parameters:
hspi | Pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI.
CallbackID | ID of the callback to be unregistered
Return values:
HAL status

Definition at line 652 of file stm32wbxx_hal_spi.c.

References __SPI_HandleTypeDef::AbortCpltCallback, __SPI_HandleTypeDef::ErrorCallback, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ABORT_CB_ID, HAL_SPI_AbortCpltCallback(), HAL_SPI_ERROR_CB_ID, HAL_SPI_ERROR_INVALID_CALLBACK, HAL_SPI_ErrorCallback(), HAL_SPI_MspDeInit(), HAL_SPI_MSPDEINIT_CB_ID, HAL_SPI_MspInit(), HAL_SPI_MSPINIT_CB_ID, HAL_SPI_RX_COMPLETE_CB_ID, HAL_SPI_RX_HALF_COMPLETE_CB_ID, HAL_SPI_RxCpltCallback(), HAL_SPI_RxHalfCpltCallback(), HAL_SPI_STATE_READY, HAL_SPI_STATE_RESET, HAL_SPI_TX_COMPLETE_CB_ID, HAL_SPI_TX_HALF_COMPLETE_CB_ID, HAL_SPI_TX_RX_COMPLETE_CB_ID, HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID, HAL_SPI_TxCpltCallback(), HAL_SPI_TxHalfCpltCallback(), HAL_SPI_TxRxCpltCallback(), HAL_SPI_TxRxHalfCpltCallback(), __SPI_HandleTypeDef::MspDeInitCallback, __SPI_HandleTypeDef::MspInitCallback, __SPI_HandleTypeDef::RxCpltCallback, __SPI_HandleTypeDef::RxHalfCpltCallback, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxCpltCallback, __SPI_HandleTypeDef::TxHalfCpltCallback, __SPI_HandleTypeDef::TxRxCpltCallback, and __SPI_HandleTypeDef::TxRxHalfCpltCallback.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IO operation functions

Functions
IO operation functions
SPI Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_SPI_Transmit (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Receive (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Transmit and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Transmit_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Receive_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_IT (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Transmit_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Receive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Abort (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (blocking mode).
HAL_StatusTypeDef | HAL_SPI_Abort_IT (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_SPI_DMAPause (SPI_HandleTypeDef *hspi)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAResume (SPI_HandleTypeDef *hspi)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAStop (SPI_HandleTypeDef *hspi)
Stop the DMA Transfer.
void | HAL_SPI_IRQHandler (SPI_HandleTypeDef *hspi)
Handle SPI interrupt request.
__weak void | HAL_SPI_TxCpltCallback (SPI_HandleTypeDef *hspi)
Tx Transfer completed callback.
__weak void | HAL_SPI_RxCpltCallback (SPI_HandleTypeDef *hspi)
Rx Transfer completed callback.
__weak void | HAL_SPI_TxRxCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Transfer completed callback.
__weak void | HAL_SPI_TxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx Half Transfer completed callback.
__weak void | HAL_SPI_RxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Rx Half Transfer completed callback.
__weak void | HAL_SPI_TxRxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Half Transfer callback.
__weak void | HAL_SPI_ErrorCallback (SPI_HandleTypeDef *hspi)
SPI error callback.
__weak void | HAL_SPI_AbortCpltCallback (SPI_HandleTypeDef *hspi)
SPI Abort Complete callback.

Detailed Description

Data transfers functions.

  ==============================================================================
                      ##### IO operation functions #####
 ===============================================================================
 [..]
    This subsection provides a set of functions allowing to manage the SPI
    data transfers.

    [..] The SPI supports master and slave mode :

    (#) There are two modes of transfer:
       (++) Blocking mode: The communication is performed in polling mode.
            The HAL status of all data processing is returned by the same function
            after finishing transfer.
       (++) No-Blocking mode: The communication is performed using Interrupts
            or DMA, These APIs return the HAL status.
            The end of the data processing will be indicated through the
            dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
            using DMA mode.
            The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
            will be executed respectively at the end of the transmit or Receive process
            The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected

    (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
        exist for 1Line (simplex) and 2Lines (full duplex) modes.

Function Documentation

HAL_StatusTypeDef HAL_SPI_Abort ( SPI_HandleTypeDef * hspi )

Abort ongoing transfer (blocking mode).

Parameters:
hspi SPI handle.
Note:
This procedure could be used for aborting any ongoing transfer (Tx and Rx), started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SPI Interrupts (depending of transfer direction)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 2254 of file stm32wbxx_hal_spi.c.

References __HAL_SPI_CLEAR_FREFLAG, __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_DISABLE, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_GetTick(), HAL_SPI_ERROR_ABORT, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_ABORT, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DEFAULT_TIMEOUT, SPI_EndRxTxTransaction(), SPI_FLAG_BSY, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_WaitFifoStateUntilTimeout(), SPI_WaitFlagStateUntilTimeout(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SPI_Abort_IT ( SPI_HandleTypeDef * hspi )

Abort ongoing transfer (Interrupt mode).

Parameters:
hspi SPI handle.
Note:
This procedure could be used for aborting any ongoing transfer (Tx and Rx), started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SPI Interrupts (depending of transfer direction)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 2414 of file stm32wbxx_hal_spi.c.

References __HAL_SPI_CLEAR_FREFLAG, __HAL_SPI_CLEAR_OVRFLAG, __SPI_HandleTypeDef::AbortCpltCallback, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_SPI_AbortCpltCallback(), HAL_SPI_ERROR_ABORT, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_ABORT, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DEFAULT_TIMEOUT, SPI_DMARxAbortCallback(), SPI_DMATxAbortCallback(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_SPI_AbortCpltCallback ( SPI_HandleTypeDef * hspi )

SPI Abort Complete callback.

Parameters:
hspi SPI handle.
Return values:
None

Definition at line 2876 of file stm32wbxx_hal_spi.c.

Referenced by HAL_SPI_Abort_IT(), HAL_SPI_Init(), HAL_SPI_UnRegisterCallback(), SPI_DMARxAbortCallback(), and SPI_DMATxAbortCallback().

HAL_StatusTypeDef HAL_SPI_DMAPause ( SPI_HandleTypeDef * hspi )

Pause the DMA Transfer.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
HAL status

Definition at line 2575 of file stm32wbxx_hal_spi.c.

References __SPI_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SPI_DMAResume ( SPI_HandleTypeDef * hspi )

Resume the DMA Transfer.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
HAL status

Definition at line 2595 of file stm32wbxx_hal_spi.c.

References __SPI_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SPI_DMAStop ( SPI_HandleTypeDef * hspi )

Stop the DMA Transfer.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
HAL status

Definition at line 2615 of file stm32wbxx_hal_spi.c.

References __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_SPI_ERROR_DMA, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, and __SPI_HandleTypeDef::State.

void HAL_SPI_ErrorCallback ( SPI_HandleTypeDef * hspi )

SPI error callback.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2858 of file stm32wbxx_hal_spi.c.

Referenced by HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_UnRegisterCallback(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAAbortOnError(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), and SPI_DMATransmitReceiveCplt().

void HAL_SPI_IRQHandler ( SPI_HandleTypeDef * hspi )

Handle SPI interrupt request.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
None

Definition at line 2655 of file stm32wbxx_hal_spi.c.

References __HAL_SPI_CLEAR_FREFLAG, __HAL_SPI_CLEAR_MODFFLAG, __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::ErrorCallback, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_SPI_ERROR_ABORT, HAL_SPI_ERROR_FRE, HAL_SPI_ERROR_MODF, HAL_SPI_ERROR_NONE, HAL_SPI_ERROR_OVR, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxISR, SPI_CHECK_FLAG, SPI_CHECK_IT_SOURCE, SPI_DMAAbortOnError(), SPI_FLAG_FRE, SPI_FLAG_MODF, SPI_FLAG_OVR, SPI_FLAG_RXNE, SPI_FLAG_TXE, SPI_IT_ERR, SPI_IT_RXNE, SPI_IT_TXE, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SPI_Receive | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData | pointer to data buffer
Size | amount of data to be received
Timeout | Timeout duration
Return values:
HAL status

Definition at line 976 of file stm32wbxx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_ENABLE, __HAL_SPI_GET_FLAG, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_READY, HAL_SPI_TransmitReceive(), __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_RX, SPI_CRC_LENGTH_16BIT, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_EndRxTransaction(), SPI_FLAG_CRCERR, SPI_FLAG_RXNE, SPI_MODE_MASTER, SPI_RESET_CRC, SPI_RXFIFO_THRESHOLD, SPI_WaitFlagStateUntilTimeout(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SPI_Receive_DMA | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with DMA.

Note:
In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData | pointer to data buffer
Note:
When the CRC feature is enabled the pData Length must be Size + 1.
Parameters:
Size amount of data to be sent
Return values:
HAL status

Definition at line 1919 of file stm32wbxx_hal_spi.c.

References __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, DMA_MDATAALIGN_HALFWORD, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SPI_ERROR_DMA, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_READY, HAL_SPI_TransmitReceive_DMA(), __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Init, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DMA_HANDLE, DMA_InitTypeDef::MemDataAlignment, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_RX, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_DMAError(), SPI_DMAHalfReceiveCplt(), SPI_DMAReceiveCplt(), SPI_IT_ERR, SPI_MODE_MASTER, SPI_RESET_CRC, SPI_RXFIFO_THRESHOLD, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, __SPI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SPI_Receive_IT | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with Interrupt.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData | pointer to data buffer
Size | amount of data to be sent
Return values:
HAL status

Definition at line 1582 of file stm32wbxx_hal_spi.c.

References __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, __SPI_HandleTypeDef::CRCSize, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_READY, HAL_SPI_TransmitReceive_IT(), __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_RX, SPI_CRC_LENGTH_16BIT, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_IT_ERR, SPI_IT_RXNE, SPI_MODE_MASTER, SPI_RESET_CRC, SPI_RXFIFO_THRESHOLD, SPI_RxISR_16BIT(), SPI_RxISR_8BIT(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

void HAL_SPI_RxCpltCallback ( SPI_HandleTypeDef * hspi )

Rx Transfer completed callback.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2778 of file stm32wbxx_hal_spi.c.

Referenced by HAL_SPI_Init(), HAL_SPI_UnRegisterCallback(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), and SPI_DMAReceiveCplt().

void HAL_SPI_RxHalfCpltCallback ( SPI_HandleTypeDef * hspi )

Rx Half Transfer completed callback.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2826 of file stm32wbxx_hal_spi.c.

Referenced by HAL_SPI_Init(), HAL_SPI_UnRegisterCallback(), and SPI_DMAHalfReceiveCplt().

HAL_StatusTypeDef HAL_SPI_Transmit | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmit an amount of data in blocking mode.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData | pointer to data buffer
Size | amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 793 of file stm32wbxx_hal_spi.c.

References __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_ENABLE, __HAL_SPI_GET_FLAG, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES_OR_1LINE, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_TX, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_EndRxTxTransaction(), SPI_FLAG_TXE, SPI_MODE_SLAVE, SPI_RESET_CRC, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SPI_Transmit_DMA | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with DMA.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData | pointer to data buffer
Size | amount of data to be sent
Return values:
HAL status

Definition at line 1796 of file stm32wbxx_hal_spi.c.

References __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, DMA_MDATAALIGN_HALFWORD, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SPI_ERROR_DMA, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Init, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES_OR_1LINE, IS_SPI_DMA_HANDLE, DMA_InitTypeDef::MemDataAlignment, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_TX, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DMAError(), SPI_DMAHalfTransmitCplt(), SPI_DMATransmitCplt(), SPI_IT_ERR, SPI_RESET_CRC, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, __SPI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SPI_Transmit_IT | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with Interrupt.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData | pointer to data buffer
Size | amount of data to be sent
Return values:
HAL status

Definition at line 1499 of file stm32wbxx_hal_spi.c.

References __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES_OR_1LINE, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_TX, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_IT_ERR, SPI_IT_TXE, SPI_RESET_CRC, SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SPI_TransmitReceive | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmit and Receive an amount of data in blocking mode.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pTxData | pointer to transmission data buffer
pRxData | pointer to reception data buffer
Size | amount of data to be sent and received
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1201 of file stm32wbxx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_ENABLE, __HAL_SPI_GET_FLAG, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_BUSY_TX_RX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_CRC_LENGTH_16BIT, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_DIRECTION_2LINES, SPI_EndRxTxTransaction(), SPI_FLAG_CRCERR, SPI_FLAG_RXNE, SPI_FLAG_TXE, SPI_MODE_MASTER, SPI_MODE_SLAVE, SPI_RESET_CRC, SPI_RXFIFO_THRESHOLD, SPI_WaitFlagStateUntilTimeout(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

Referenced by HAL_SPI_Receive().

HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Transmit and Receive an amount of data in non-blocking mode with DMA.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pTxData | pointer to transmission data buffer
pRxData | pointer to reception data buffer
Note:
When the CRC feature is enabled the pRxData Length must be Size + 1
Parameters:
Size amount of data to be sent
Return values:
HAL status

Definition at line 2062 of file stm32wbxx_hal_spi.c.

References __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, DMA_MDATAALIGN_HALFWORD, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SPI_ERROR_DMA, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_BUSY_TX_RX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Init, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES, IS_SPI_DMA_HANDLE, DMA_InitTypeDef::MemDataAlignment, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_2LINES, SPI_DMAError(), SPI_DMAHalfReceiveCplt(), SPI_DMAHalfTransmitReceiveCplt(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt(), SPI_IT_ERR, SPI_MODE_MASTER, SPI_RESET_CRC, SPI_RXFIFO_THRESHOLD, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, __SPI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Referenced by HAL_SPI_Receive_DMA().

HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Transmit and Receive an amount of data in non-blocking mode with Interrupt.

Parameters:
hspi | pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pTxData | pointer to transmission data buffer
pRxData | pointer to reception data buffer
Size | amount of data to be sent and received
Return values:
HAL status

Definition at line 1687 of file stm32wbxx_hal_spi.c.

References __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCLength, __SPI_HandleTypeDef::CRCSize, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_BUSY_TX_RX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_CRC_LENGTH_16BIT, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_2LINES, SPI_IT_ERR, SPI_IT_RXNE, SPI_IT_TXE, SPI_MODE_MASTER, SPI_RESET_CRC, SPI_RXFIFO_THRESHOLD, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

Referenced by HAL_SPI_Receive_IT().

void HAL_SPI_TxCpltCallback ( SPI_HandleTypeDef * hspi )

Tx Transfer completed callback.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2762 of file stm32wbxx_hal_spi.c.

Referenced by HAL_SPI_Init(), HAL_SPI_UnRegisterCallback(), SPI_CloseTx_ISR(), and SPI_DMATransmitCplt().

void HAL_SPI_TxHalfCpltCallback ( SPI_HandleTypeDef * hspi )

Tx Half Transfer completed callback.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2810 of file stm32wbxx_hal_spi.c.

Referenced by HAL_SPI_Init(), HAL_SPI_UnRegisterCallback(), and SPI_DMAHalfTransmitCplt().

void HAL_SPI_TxRxCpltCallback ( SPI_HandleTypeDef * hspi )

Tx and Rx Transfer completed callback.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2794 of file stm32wbxx_hal_spi.c.

Referenced by HAL_SPI_Init(), HAL_SPI_UnRegisterCallback(), SPI_CloseRxTx_ISR(), and SPI_DMATransmitReceiveCplt().

void HAL_SPI_TxRxHalfCpltCallback ( SPI_HandleTypeDef * hspi )

Tx and Rx Half Transfer callback.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2842 of file stm32wbxx_hal_spi.c.

Referenced by HAL_SPI_Init(), HAL_SPI_UnRegisterCallback(), and SPI_DMAHalfTransmitReceiveCplt().

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
SPI Exported Functions

SPI control functions. More...

Functions

HAL_SPI_StateTypeDef | HAL_SPI_GetState (SPI_HandleTypeDef *hspi)
Return the SPI handle state.
uint32_t | HAL_SPI_GetError (SPI_HandleTypeDef *hspi)
Return the SPI error code.

Detailed Description

SPI control functions.

 ===============================================================================
                      ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the SPI.
     (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
     (+) HAL_SPI_GetError() check in run-time Errors occurring during communication

Function Documentation

uint32_t HAL_SPI_GetError ( SPI_HandleTypeDef * hspi )

Return the SPI error code.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
SPI error code in bitmap format

Definition at line 2923 of file stm32wbxx_hal_spi.c.

References __SPI_HandleTypeDef::ErrorCode.

HAL_SPI_StateTypeDef HAL_SPI_GetState ( SPI_HandleTypeDef * hspi )

Return the SPI handle state.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
SPI state

Definition at line 2911 of file stm32wbxx_hal_spi.c.

References __SPI_HandleTypeDef::State.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SPI Exported Types

Data Structures | Typedefs | Enumerations
SPI Exported Types
SPI

Data Structures

struct | SPI_InitTypeDef
SPI Configuration Structure definition. More...
struct | __SPI_HandleTypeDef
SPI handle Structure definition. More...

Typedefs

typedef struct __SPI_HandleTypeDef | SPI_HandleTypeDef
SPI handle Structure definition.
typedef void(* | pSPI_CallbackTypeDef )(SPI_HandleTypeDef *hspi)
HAL SPI Callback pointer definition.

Enumerations

enum HAL_SPI_StateTypeDef {
HAL_SPI_STATE_RESET = 0x00U, HAL_SPI_STATE_READY = 0x01U, HAL_SPI_STATE_BUSY = 0x02U, HAL_SPI_STATE_BUSY_TX = 0x03U,
HAL_SPI_STATE_BUSY_RX = 0x04U, HAL_SPI_STATE_BUSY_TX_RX = 0x05U, HAL_SPI_STATE_ERROR = 0x06U, HAL_SPI_STATE_ABORT = 0x07U
}
HAL SPI State structure definition. More...
enum HAL_SPI_CallbackIDTypeDef {
HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U,
HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U, HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, HAL_SPI_ERROR_CB_ID = 0x06U, HAL_SPI_ABORT_CB_ID = 0x07U,
HAL_SPI_MSPINIT_CB_ID = 0x08U, HAL_SPI_MSPDEINIT_CB_ID = 0x09U
}
HAL SPI Callback ID enumeration definition. More...

Typedef Documentation

typedef void(* pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi)

HAL SPI Callback pointer definition.

pointer to an SPI callback function

Definition at line 187 of file stm32wbxx_hal_spi.h.

typedef struct __SPI_HandleTypeDef SPI_HandleTypeDef

SPI handle Structure definition.

Enumeration Type Documentation

enum HAL_SPI_CallbackIDTypeDef

HAL SPI Callback ID enumeration definition.

Enumerator:
HAL_SPI_TX_COMPLETE_CB_ID

SPI Tx Completed callback ID

HAL_SPI_RX_COMPLETE_CB_ID

SPI Rx Completed callback ID

HAL_SPI_TX_RX_COMPLETE_CB_ID

SPI TxRx Completed callback ID

HAL_SPI_TX_HALF_COMPLETE_CB_ID

SPI Tx Half Completed callback ID

HAL_SPI_RX_HALF_COMPLETE_CB_ID

SPI Rx Half Completed callback ID

HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID

SPI TxRx Half Completed callback ID

HAL_SPI_ERROR_CB_ID

SPI Error callback ID

HAL_SPI_ABORT_CB_ID

SPI Abort callback ID

HAL_SPI_MSPINIT_CB_ID

SPI Msp Init callback ID

HAL_SPI_MSPDEINIT_CB_ID

SPI Msp DeInit callback ID

Definition at line 169 of file stm32wbxx_hal_spi.h.

enum HAL_SPI_StateTypeDef

HAL SPI State structure definition.

Enumerator:
HAL_SPI_STATE_RESET

Peripheral not Initialized

HAL_SPI_STATE_READY

Peripheral Initialized and ready for use

HAL_SPI_STATE_BUSY

an internal process is ongoing

HAL_SPI_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_SPI_STATE_BUSY_RX

Data Reception process is ongoing

HAL_SPI_STATE_BUSY_TX_RX

Data Transmission and Reception process is ongoing

HAL_SPI_STATE_ERROR

SPI error state

HAL_SPI_STATE_ABORT

SPI abort is ongoing

Definition at line 101 of file stm32wbxx_hal_spi.h.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SPI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SPI_InitTypeDef Struct Reference
SPI Exported Types

SPI Configuration Structure definition. More...

#include <stm32wbxx_hal_spi.h>

Data Fields

uint32_t | Mode
uint32_t | Direction
uint32_t | DataSize
uint32_t | CLKPolarity
uint32_t | CLKPhase
uint32_t | NSS
uint32_t | BaudRatePrescaler
uint32_t | FirstBit
uint32_t | TIMode
uint32_t | CRCCalculation
uint32_t | CRCPolynomial
uint32_t | CRCLength
uint32_t | NSSPMode

Detailed Description

SPI Configuration Structure definition.

Definition at line 47 of file stm32wbxx_hal_spi.h.

Field Documentation

uint32_t SPI_InitTypeDef::BaudRatePrescaler

Specifies the Baud Rate prescaler value which will be used to configure the transmit and receive SCK clock. This parameter can be a value of SPI BaudRate Prescaler

Note:
The communication clock is derived from the master clock. The slave clock does not need to be set.

Definition at line 68 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::CLKPhase

Specifies the clock active edge for the bit capture. This parameter can be a value of SPI Clock Phase

Definition at line 61 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::CLKPolarity

Specifies the serial clock steady state. This parameter can be a value of SPI Clock Polarity

Definition at line 58 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::CRCCalculation

Specifies if the CRC calculation is enabled or not. This parameter can be a value of SPI CRC Calculation

Definition at line 80 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt(), SPI_RxISR_16BIT(), SPI_RxISR_8BIT(), SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

uint32_t SPI_InitTypeDef::CRCLength

Specifies the CRC Length used for the CRC calculation. CRC Length is only used with Data8 and Data16, not other data size This parameter can be a value of SPI CRC Length

Definition at line 86 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

uint32_t SPI_InitTypeDef::CRCPolynomial

Specifies the polynomial used for the CRC calculation. This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535

Definition at line 83 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::DataSize

Specifies the SPI data size. This parameter can be a value of SPI Data Size

Definition at line 55 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

uint32_t SPI_InitTypeDef::Direction

Specifies the SPI bidirectional mode state. This parameter can be a value of SPI Direction Mode

Definition at line 52 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_CloseTx_ISR(), SPI_DMATransmitCplt(), SPI_EndRxTransaction(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

uint32_t SPI_InitTypeDef::FirstBit

Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of SPI MSB LSB Transmission

Definition at line 74 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::Mode

Specifies the SPI operating mode. This parameter can be a value of SPI Mode

Definition at line 49 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_EndRxTransaction(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

uint32_t SPI_InitTypeDef::NSS

Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. This parameter can be a value of SPI Slave Select Management

Definition at line 64 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::NSSPMode

Specifies whether the NSSP signal is enabled or not . This parameter can be a value of SPI NSS Pulse Mode This mode is activated by the NSSP bit in the SPIx_CR2 register and it takes effect only if the SPI interface is configured as Motorola SPI master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0, CPOL setting is ignored)..

Definition at line 90 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::TIMode

Specifies if the TI mode is enabled or not. This parameter can be a value of SPI TI Mode

Definition at line 77 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_spi.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: __SPI_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__SPI_HandleTypeDef Struct Reference
SPI Exported Types

SPI handle Structure definition. More...

#include <stm32wbxx_hal_spi.h>

Data Fields

SPI_TypeDef * | Instance
SPI_InitTypeDef Init
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
__IO uint16_t | RxXferCount
uint32_t | CRCSize
void(* | RxISR )(struct __SPI_HandleTypeDef *hspi)
void(* | TxISR )(struct __SPI_HandleTypeDef *hspi)
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_SPI_StateTypeDef | State
__IO uint32_t | ErrorCode
void(* | TxCpltCallback )(struct __SPI_HandleTypeDef *hspi)
void(* | RxCpltCallback )(struct __SPI_HandleTypeDef *hspi)
void(* | TxRxCpltCallback )(struct __SPI_HandleTypeDef *hspi)
void(* | TxHalfCpltCallback )(struct __SPI_HandleTypeDef *hspi)
void(* | RxHalfCpltCallback )(struct __SPI_HandleTypeDef *hspi)
void(* | TxRxHalfCpltCallback )(struct __SPI_HandleTypeDef *hspi)
void(* | ErrorCallback )(struct __SPI_HandleTypeDef *hspi)
void(* | AbortCpltCallback )(struct __SPI_HandleTypeDef *hspi)
void(* | MspInitCallback )(struct __SPI_HandleTypeDef *hspi)
void(* | MspDeInitCallback )(struct __SPI_HandleTypeDef *hspi)

Detailed Description

SPI handle Structure definition.

Definition at line 116 of file stm32wbxx_hal_spi.h.

Field Documentation

void(* __SPI_HandleTypeDef::AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi)

SPI Abort callback

Definition at line 158 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Abort_IT(), HAL_SPI_Init(), HAL_SPI_RegisterCallback(), HAL_SPI_UnRegisterCallback(), SPI_DMARxAbortCallback(), and SPI_DMATxAbortCallback().

uint32_t __SPI_HandleTypeDef::CRCSize

SPI CRC size used for the transfer

Definition at line 134 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_8BITCRC(), and SPI_RxISR_8BITCRC().

void(* __SPI_HandleTypeDef::ErrorCallback)(struct __SPI_HandleTypeDef *hspi)

SPI Error callback

Definition at line 157 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_RegisterCallback(), HAL_SPI_UnRegisterCallback(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAAbortOnError(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), and SPI_DMATransmitReceiveCplt().

__IO uint32_t __SPI_HandleTypeDef::ErrorCode

SPI Error code

Definition at line 148 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DeInit(), HAL_SPI_DMAStop(), HAL_SPI_GetError(), HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_RegisterCallback(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), HAL_SPI_UnRegisterCallback(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

DMA_HandleTypeDef* __SPI_HandleTypeDef::hdmarx

SPI Rx DMA Handle parameters

Definition at line 142 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DMAStop(), HAL_SPI_IRQHandler(), HAL_SPI_Receive_DMA(), HAL_SPI_TransmitReceive_DMA(), SPI_DMARxAbortCallback(), and SPI_DMATxAbortCallback().

DMA_HandleTypeDef* __SPI_HandleTypeDef::hdmatx

SPI Tx DMA Handle parameters

Definition at line 140 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DMAStop(), HAL_SPI_IRQHandler(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), SPI_DMARxAbortCallback(), and SPI_DMATxAbortCallback().

SPI_InitTypeDef __SPI_HandleTypeDef::Init

SPI communication parameters

Definition at line 120 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_EndRxTransaction(), SPI_RxISR_16BIT(), SPI_RxISR_8BIT(), SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

SPI_TypeDef* __SPI_HandleTypeDef::Instance

SPI registers base address

Definition at line 118 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DeInit(), HAL_SPI_DMAPause(), HAL_SPI_DMAResume(), HAL_SPI_DMAStop(), HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), HAL_SPIEx_FlushRxFifo(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_16BITCRC(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_RxISR_16BIT(), SPI_RxISR_16BITCRC(), SPI_RxISR_8BIT(), SPI_RxISR_8BITCRC(), SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), and SPI_WaitFifoStateUntilTimeout().

HAL_LockTypeDef __SPI_HandleTypeDef::Lock

Locking object

Definition at line 144 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init().

void(* __SPI_HandleTypeDef::MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi)

SPI Msp DeInit callback

Definition at line 160 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_DeInit(), HAL_SPI_RegisterCallback(), and HAL_SPI_UnRegisterCallback().

void(* __SPI_HandleTypeDef::MspInitCallback)(struct __SPI_HandleTypeDef *hspi)

SPI Msp Init callback

Definition at line 159 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_RegisterCallback(), and HAL_SPI_UnRegisterCallback().

uint8_t* __SPI_HandleTypeDef::pRxBuffPtr

Pointer to SPI Rx transfer Buffer

Definition at line 128 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_RxISR_16BIT(), and SPI_RxISR_8BIT().

uint8_t* __SPI_HandleTypeDef::pTxBuffPtr

Pointer to SPI Tx transfer Buffer

Definition at line 122 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_TxISR_16BIT(), and SPI_TxISR_8BIT().

void(* __SPI_HandleTypeDef::RxCpltCallback)(struct __SPI_HandleTypeDef *hspi)

SPI Rx Completed callback

Definition at line 152 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_RegisterCallback(), HAL_SPI_UnRegisterCallback(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), and SPI_DMAReceiveCplt().

void(* __SPI_HandleTypeDef::RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi)

SPI Rx Half Completed callback

Definition at line 155 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_RegisterCallback(), HAL_SPI_UnRegisterCallback(), and SPI_DMAHalfReceiveCplt().

void(* __SPI_HandleTypeDef::RxISR)(struct __SPI_HandleTypeDef *hspi)

function pointer on Rx ISR

Definition at line 136 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_RxISR_16BIT(), and SPI_RxISR_8BIT().

__IO uint16_t __SPI_HandleTypeDef::RxXferCount

SPI Rx Transfer Counter

Definition at line 132 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_DMAAbortOnError(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_RxISR_16BIT(), and SPI_RxISR_8BIT().

uint16_t __SPI_HandleTypeDef::RxXferSize

SPI Rx Transfer size

Definition at line 130 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

__IO HAL_SPI_StateTypeDef __SPI_HandleTypeDef::State

SPI communication state

Definition at line 146 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DeInit(), HAL_SPI_DMAStop(), HAL_SPI_GetState(), HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_RegisterCallback(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), HAL_SPI_UnRegisterCallback(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

void(* __SPI_HandleTypeDef::TxCpltCallback)(struct __SPI_HandleTypeDef *hspi)

SPI Tx Completed callback

Definition at line 151 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_RegisterCallback(), HAL_SPI_UnRegisterCallback(), SPI_CloseTx_ISR(), and SPI_DMATransmitCplt().

void(* __SPI_HandleTypeDef::TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi)

SPI Tx Half Completed callback

Definition at line 154 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_RegisterCallback(), HAL_SPI_UnRegisterCallback(), and SPI_DMAHalfTransmitCplt().

void(* __SPI_HandleTypeDef::TxISR)(struct __SPI_HandleTypeDef *hspi)

function pointer on Tx ISR

Definition at line 138 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

void(* __SPI_HandleTypeDef::TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi)

SPI TxRx Completed callback

Definition at line 153 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_RegisterCallback(), HAL_SPI_UnRegisterCallback(), SPI_CloseRxTx_ISR(), and SPI_DMATransmitReceiveCplt().

void(* __SPI_HandleTypeDef::TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi)

SPI TxRx Half Completed callback

Definition at line 156 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_RegisterCallback(), HAL_SPI_UnRegisterCallback(), and SPI_DMAHalfTransmitReceiveCplt().

__IO uint16_t __SPI_HandleTypeDef::TxXferCount

SPI Tx Transfer Counter

Definition at line 126 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_DMAAbortOnError(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_TxISR_16BIT(), and SPI_TxISR_8BIT().

uint16_t __SPI_HandleTypeDef::TxXferSize

SPI Tx Transfer size

Definition at line 124 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_spi.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SPI Error Code

Defines
SPI Error Code
SPI Exported Constants

Defines

#define | HAL_SPI_ERROR_NONE (0x00000000U)
#define | HAL_SPI_ERROR_MODF (0x00000001U)
#define | HAL_SPI_ERROR_CRC (0x00000002U)
#define | HAL_SPI_ERROR_OVR (0x00000004U)
#define | HAL_SPI_ERROR_FRE (0x00000008U)
#define | HAL_SPI_ERROR_DMA (0x00000010U)
#define | HAL_SPI_ERROR_FLAG (0x00000020U)
#define | HAL_SPI_ERROR_ABORT (0x00000040U)
#define | HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U)

Define Documentation

#define HAL_SPI_ERROR_ABORT (0x00000040U)

Error during SPI Abort procedure

Definition at line 209 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DMARxAbortCallback(), and SPI_DMATxAbortCallback().

#define HAL_SPI_ERROR_CRC (0x00000002U)

CRC error

Definition at line 204 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define HAL_SPI_ERROR_DMA (0x00000010U)

DMA transfer error

Definition at line 207 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_DMAStop(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), and SPI_DMAError().

#define HAL_SPI_ERROR_FLAG (0x00000020U)

Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag

Definition at line 208 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

#define HAL_SPI_ERROR_FRE (0x00000008U)

FRE error

Definition at line 206 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U)

Invalid Callback error

Definition at line 211 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_RegisterCallback(), and HAL_SPI_UnRegisterCallback().

#define HAL_SPI_ERROR_MODF (0x00000001U)

MODF error

Definition at line 203 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define HAL_SPI_ERROR_NONE (0x00000000U)

No error

Definition at line 202 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DeInit(), HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), and SPI_DMATxAbortCallback().

#define HAL_SPI_ERROR_OVR (0x00000004U)

OVR error

Definition at line 205 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SPI Mode

Defines
SPI Mode
SPI Exported Constants

Defines

#define | SPI_MODE_SLAVE (0x00000000U)
#define | SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)

Define Documentation

#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)

Definition at line 221 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_EndRxTransaction(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define SPI_MODE_SLAVE (0x00000000U)

Definition at line 220 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Transmit(), and HAL_SPI_TransmitReceive().

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SPI Direction Mode

Defines
SPI Direction Mode
SPI Exported Constants

Defines

#define | SPI_DIRECTION_2LINES (0x00000000U)
#define | SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
#define | SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE

Define Documentation

#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE

Definition at line 231 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), SPI_EndRxTransaction(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define SPI_DIRECTION_2LINES (0x00000000U)

Definition at line 229 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_CloseTx_ISR(), and SPI_DMATransmitCplt().

#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY

Definition at line 230 of file stm32wbxx_hal_spi.h.

Referenced by SPI_EndRxTransaction(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SPI Data Size

Defines
SPI Data Size
SPI Exported Constants

Defines

#define | SPI_DATASIZE_4BIT (0x00000300U)
#define | SPI_DATASIZE_5BIT (0x00000400U)
#define | SPI_DATASIZE_6BIT (0x00000500U)
#define | SPI_DATASIZE_7BIT (0x00000600U)
#define | SPI_DATASIZE_8BIT (0x00000700U)
#define | SPI_DATASIZE_9BIT (0x00000800U)
#define | SPI_DATASIZE_10BIT (0x00000900U)
#define | SPI_DATASIZE_11BIT (0x00000A00U)
#define | SPI_DATASIZE_12BIT (0x00000B00U)
#define | SPI_DATASIZE_13BIT (0x00000C00U)
#define | SPI_DATASIZE_14BIT (0x00000D00U)
#define | SPI_DATASIZE_15BIT (0x00000E00U)
#define | SPI_DATASIZE_16BIT (0x00000F00U)

Define Documentation

#define SPI_DATASIZE_10BIT (0x00000900U)

Definition at line 245 of file stm32wbxx_hal_spi.h.

#define SPI_DATASIZE_11BIT (0x00000A00U)

Definition at line 246 of file stm32wbxx_hal_spi.h.

#define SPI_DATASIZE_12BIT (0x00000B00U)

Definition at line 247 of file stm32wbxx_hal_spi.h.

#define SPI_DATASIZE_13BIT (0x00000C00U)

Definition at line 248 of file stm32wbxx_hal_spi.h.

#define SPI_DATASIZE_14BIT (0x00000D00U)

Definition at line 249 of file stm32wbxx_hal_spi.h.

#define SPI_DATASIZE_15BIT (0x00000E00U)

Definition at line 250 of file stm32wbxx_hal_spi.h.

#define SPI_DATASIZE_16BIT (0x00000F00U)

Definition at line 251 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), and HAL_SPI_TransmitReceive().

#define SPI_DATASIZE_4BIT (0x00000300U)

Definition at line 239 of file stm32wbxx_hal_spi.h.

#define SPI_DATASIZE_5BIT (0x00000400U)

Definition at line 240 of file stm32wbxx_hal_spi.h.

#define SPI_DATASIZE_6BIT (0x00000500U)

Definition at line 241 of file stm32wbxx_hal_spi.h.

#define SPI_DATASIZE_7BIT (0x00000600U)

Definition at line 242 of file stm32wbxx_hal_spi.h.

#define SPI_DATASIZE_8BIT (0x00000700U)

Definition at line 243 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define SPI_DATASIZE_9BIT (0x00000800U)

Definition at line 244 of file stm32wbxx_hal_spi.h.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SPI Clock Polarity

Defines
SPI Clock Polarity
SPI Exported Constants

Defines

#define | SPI_POLARITY_LOW (0x00000000U)
#define | SPI_POLARITY_HIGH SPI_CR1_CPOL

Define Documentation

#define SPI_POLARITY_HIGH SPI_CR1_CPOL

Definition at line 260 of file stm32wbxx_hal_spi.h.

#define SPI_POLARITY_LOW (0x00000000U)

Definition at line 259 of file stm32wbxx_hal_spi.h.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SPI Clock Phase

Defines
SPI Clock Phase
SPI Exported Constants

Defines

#define | SPI_PHASE_1EDGE (0x00000000U)
#define | SPI_PHASE_2EDGE SPI_CR1_CPHA

Define Documentation

#define SPI_PHASE_1EDGE (0x00000000U)

Definition at line 268 of file stm32wbxx_hal_spi.h.

#define SPI_PHASE_2EDGE SPI_CR1_CPHA

Definition at line 269 of file stm32wbxx_hal_spi.h.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SPI Slave Select Management

Defines
SPI Slave Select Management
SPI Exported Constants

Defines

#define | SPI_NSS_SOFT SPI_CR1_SSM
#define | SPI_NSS_HARD_INPUT (0x00000000U)
#define | SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U)

Define Documentation

#define SPI_NSS_HARD_INPUT (0x00000000U)

Definition at line 278 of file stm32wbxx_hal_spi.h.

#define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U)

Definition at line 279 of file stm32wbxx_hal_spi.h.

#define SPI_NSS_SOFT SPI_CR1_SSM

Definition at line 277 of file stm32wbxx_hal_spi.h.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SPI NSS Pulse Mode

Defines
SPI NSS Pulse Mode
SPI Exported Constants

Defines

#define | SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP
#define | SPI_NSS_PULSE_DISABLE (0x00000000U)

Define Documentation

#define SPI_NSS_PULSE_DISABLE (0x00000000U)

Definition at line 288 of file stm32wbxx_hal_spi.h.

#define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP

Definition at line 287 of file stm32wbxx_hal_spi.h.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SPI BaudRate Prescaler

Defines
SPI BaudRate Prescaler
SPI Exported Constants

Defines

#define | SPI_BAUDRATEPRESCALER_2 (0x00000000U)
#define | SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0)
#define | SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1)
#define | SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
#define | SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2)
#define | SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
#define | SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
#define | SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)

Define Documentation

#define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)

Definition at line 302 of file stm32wbxx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)

Definition at line 299 of file stm32wbxx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_2 (0x00000000U)

Definition at line 296 of file stm32wbxx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)

Definition at line 303 of file stm32wbxx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2)

Definition at line 300 of file stm32wbxx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0)

Definition at line 297 of file stm32wbxx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)

Definition at line 301 of file stm32wbxx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1)

Definition at line 298 of file stm32wbxx_hal_spi.h.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SPI MSB LSB Transmission

Defines
SPI MSB LSB Transmission
SPI Exported Constants

Defines

#define | SPI_FIRSTBIT_MSB (0x00000000U)
#define | SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST

Define Documentation

#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST

Definition at line 312 of file stm32wbxx_hal_spi.h.

#define SPI_FIRSTBIT_MSB (0x00000000U)

Definition at line 311 of file stm32wbxx_hal_spi.h.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SPI TI Mode

Defines
SPI TI Mode
SPI Exported Constants

Defines

#define | SPI_TIMODE_DISABLE (0x00000000U)
#define | SPI_TIMODE_ENABLE SPI_CR2_FRF

Define Documentation

#define SPI_TIMODE_DISABLE (0x00000000U)

Definition at line 320 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_TIMODE_ENABLE SPI_CR2_FRF

Definition at line 321 of file stm32wbxx_hal_spi.h.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SPI CRC Calculation

Defines
SPI CRC Calculation
SPI Exported Constants

Defines

#define | SPI_CRCCALCULATION_DISABLE (0x00000000U)
#define | SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN

Define Documentation

#define SPI_CRCCALCULATION_DISABLE (0x00000000U)

Definition at line 329 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN

Definition at line 330 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt(), SPI_RxISR_16BIT(), SPI_RxISR_8BIT(), SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SPI CRC Length

Defines
SPI CRC Length
SPI Exported Constants

This parameter can be one of the following values: SPI_CRC_LENGTH_DATASIZE: aligned with the data size SPI_CRC_LENGTH_8BIT : CRC 8bit SPI_CRC_LENGTH_16BIT : CRC 16bit. More...

Defines

#define | SPI_CRC_LENGTH_DATASIZE (0x00000000U)
#define | SPI_CRC_LENGTH_8BIT (0x00000001U)
#define | SPI_CRC_LENGTH_16BIT (0x00000002U)

Detailed Description

This parameter can be one of the following values: SPI_CRC_LENGTH_DATASIZE: aligned with the data size SPI_CRC_LENGTH_8BIT : CRC 8bit SPI_CRC_LENGTH_16BIT : CRC 16bit.

Define Documentation

#define SPI_CRC_LENGTH_16BIT (0x00000002U)

Definition at line 344 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT(), and SPI_DMAReceiveCplt().

#define SPI_CRC_LENGTH_8BIT (0x00000001U)

Definition at line 343 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init(), and SPI_DMATransmitReceiveCplt().

#define SPI_CRC_LENGTH_DATASIZE (0x00000000U)

Definition at line 342 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init().

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SPI FIFO Reception Threshold

Defines
SPI FIFO Reception Threshold
SPI Exported Constants

This parameter can be one of the following values: SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF : RXNE event is generated if the FIFO level is greater or equal to 1/4(8-bits). More...

Defines

#define | SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
#define | SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
#define | SPI_RXFIFO_THRESHOLD_HF (0x00000000U)

Detailed Description

This parameter can be one of the following values: SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF : RXNE event is generated if the FIFO level is greater or equal to 1/4(8-bits).

SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO level is greater or equal to 1/2(16 bits).

Define Documentation

#define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH

Definition at line 357 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), and SPI_2linesRxISR_8BIT().

#define SPI_RXFIFO_THRESHOLD_HF (0x00000000U)

Definition at line 359 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH

Definition at line 358 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init().

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SPI Interrupt Definition

Defines
SPI Interrupt Definition
SPI Exported Constants

Defines

#define | SPI_IT_TXE SPI_CR2_TXEIE
#define | SPI_IT_RXNE SPI_CR2_RXNEIE
#define | SPI_IT_ERR SPI_CR2_ERRIE

Define Documentation

#define SPI_IT_ERR SPI_CR2_ERRIE

Definition at line 369 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_RxISR_16BITCRC(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define SPI_IT_RXNE SPI_CR2_RXNEIE

Definition at line 368 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_16BITCRC(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_CloseRx_ISR(), SPI_RxISR_16BITCRC(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define SPI_IT_TXE SPI_CR2_TXEIE

Definition at line 367 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive_IT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_CloseTx_ISR(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SPI Flags Definition

Defines
SPI Flags Definition
SPI Exported Constants

Defines

#define | SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
#define | SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
#define | SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
#define | SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
#define | SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
#define | SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
#define | SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
#define | SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
#define | SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */
#define | SPI_FLAG_MASK

Define Documentation

#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */

Definition at line 379 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Abort(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DMARxAbortCallback(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */

Definition at line 380 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */

Definition at line 383 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */

Definition at line 385 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPIEx_FlushRxFifo(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DMARxAbortCallback(), SPI_DMATransmitReceiveCplt(), SPI_DMATxAbortCallback(), SPI_EndRxTransaction(), and SPI_EndRxTxTransaction().

#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */

Definition at line 384 of file stm32wbxx_hal_spi.h.

Referenced by SPI_EndRxTxTransaction().

#define SPI_FLAG_MASK
Value:
(SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR\
                                         | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_FTLVL | SPI_SR_FRLVL)

Definition at line 386 of file stm32wbxx_hal_spi.h.

#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */

Definition at line 381 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */

Definition at line 382 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */

Definition at line 377 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), and SPI_DMAReceiveCplt().

#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */

Definition at line 378 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Transmit(), and HAL_SPI_TransmitReceive().

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SPI Transmission FIFO Status Level

Defines
SPI Transmission FIFO Status Level
SPI Exported Constants

Defines

#define | SPI_FTLVL_EMPTY (0x00000000U)
#define | SPI_FTLVL_QUARTER_FULL (0x00000800U)
#define | SPI_FTLVL_HALF_FULL (0x00001000U)
#define | SPI_FTLVL_FULL (0x00001800U)

Define Documentation

#define SPI_FTLVL_EMPTY (0x00000000U)

Definition at line 395 of file stm32wbxx_hal_spi.h.

Referenced by SPI_EndRxTxTransaction().

#define SPI_FTLVL_FULL (0x00001800U)

Definition at line 398 of file stm32wbxx_hal_spi.h.

#define SPI_FTLVL_HALF_FULL (0x00001000U)

Definition at line 397 of file stm32wbxx_hal_spi.h.

#define SPI_FTLVL_QUARTER_FULL (0x00000800U)

Definition at line 396 of file stm32wbxx_hal_spi.h.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SPI Reception FIFO Status Level

Defines
SPI Reception FIFO Status Level
SPI Exported Constants

Defines

#define | SPI_FRLVL_EMPTY (0x00000000U)
#define | SPI_FRLVL_QUARTER_FULL (0x00000200U)
#define | SPI_FRLVL_HALF_FULL (0x00000400U)
#define | SPI_FRLVL_FULL (0x00000600U)

Define Documentation

#define SPI_FRLVL_EMPTY (0x00000000U)

Definition at line 407 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPIEx_FlushRxFifo(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DMARxAbortCallback(), SPI_DMATxAbortCallback(), SPI_EndRxTransaction(), SPI_EndRxTxTransaction(), and SPI_WaitFifoStateUntilTimeout().

#define SPI_FRLVL_FULL (0x00000600U)

Definition at line 410 of file stm32wbxx_hal_spi.h.

#define SPI_FRLVL_HALF_FULL (0x00000400U)

Definition at line 409 of file stm32wbxx_hal_spi.h.

Referenced by SPI_DMATransmitReceiveCplt().

#define SPI_FRLVL_QUARTER_FULL (0x00000200U)

Definition at line 408 of file stm32wbxx_hal_spi.h.

Referenced by SPI_DMATransmitReceiveCplt().

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SPI Exported Macros

Defines
SPI Exported Macros
SPI

Defines

#define | __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__)
Reset SPI handle state.
#define | __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
Enable the specified SPI interrupts.
#define | __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
Disable the specified SPI interrupts.
#define | __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified SPI interrupt source is enabled or not.
#define | __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Check whether the specified SPI flag is set or not.
#define | __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
Clear the SPI CRCERR pending flag.
#define | __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)
Clear the SPI MODF pending flag.
#define | __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)
Clear the SPI OVR pending flag.
#define | __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)
Clear the SPI FRE pending flag.
#define | __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
Enable the SPI peripheral.
#define | __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
Disable the SPI peripheral.

Define Documentation

#define __HAL_SPI_CLEAR_CRCERRFLAG ( __HANDLE__ ) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))

Clear the SPI CRCERR pending flag.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 499 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define __HAL_SPI_CLEAR_FREFLAG ( __HANDLE__ )
Value:
do{                                              \
    __IO uint32_t tmpreg_fre = 0x00U;              \
    tmpreg_fre = (__HANDLE__)->Instance->SR;       \
    UNUSED(tmpreg_fre);                            \
  }while(0U)

Clear the SPI FRE pending flag.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 532 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), SPI_DMARxAbortCallback(), and SPI_DMATxAbortCallback().

#define __HAL_SPI_CLEAR_MODFFLAG ( __HANDLE__ )
Value:
do{                                                    \
    __IO uint32_t tmpreg_modf = 0x00U;                   \
    tmpreg_modf = (__HANDLE__)->Instance->SR;            \
    CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
    UNUSED(tmpreg_modf);                                 \
  } while(0U)

Clear the SPI MODF pending flag.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 506 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define __HAL_SPI_CLEAR_OVRFLAG ( __HANDLE__ )
Value:
do{                                              \
    __IO uint32_t tmpreg_ovr = 0x00U;              \
    tmpreg_ovr = (__HANDLE__)->Instance->DR;       \
    tmpreg_ovr = (__HANDLE__)->Instance->SR;       \
    UNUSED(tmpreg_ovr);                            \
  } while(0U)

Clear the SPI OVR pending flag.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 519 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), HAL_SPI_Transmit(), SPI_CloseTx_ISR(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), and SPI_DMATxAbortCallback().

#define __HAL_SPI_DISABLE ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)

Disable the SPI peripheral.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 551 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_DeInit(), HAL_SPI_Init(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DMARxAbortCallback(), SPI_DMATxAbortCallback(), SPI_EndRxTransaction(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define __HAL_SPI_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))

Disable the specified SPI interrupts.

Parameters:
__HANDLE__ specifies the SPI handle. This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
__INTERRUPT__ specifies the interrupt source to disable. This parameter can be one of the following values:
  • SPI_IT_TXE: Tx buffer empty interrupt enable
  • SPI_IT_RXNE: RX buffer not empty interrupt enable
  • SPI_IT_ERR: Error interrupt enable
Return values:
None

Definition at line 461 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_16BITCRC(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_RxISR_16BITCRC(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

#define __HAL_SPI_ENABLE ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)

Enable the SPI peripheral.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 544 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

#define __HAL_SPI_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))

Enable the specified SPI interrupts.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
__INTERRUPT__ specifies the interrupt source to enable. This parameter can be one of the following values:
  • SPI_IT_TXE: Tx buffer empty interrupt enable
  • SPI_IT_RXNE: RX buffer not empty interrupt enable
  • SPI_IT_ERR: Error interrupt enable
Return values:
None

Definition at line 449 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

#define __HAL_SPI_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

Check whether the specified SPI flag is set or not.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • SPI_FLAG_RXNE: Receive buffer not empty flag
  • SPI_FLAG_TXE: Transmit buffer empty flag
  • SPI_FLAG_CRCERR: CRC error flag
  • SPI_FLAG_MODF: Mode fault flag
  • SPI_FLAG_OVR: Overrun flag
  • SPI_FLAG_BSY: Busy flag
  • SPI_FLAG_FRE: Frame format error flag
  • SPI_FLAG_FTLVL: SPI fifo transmission level
  • SPI_FLAG_FRLVL: SPI fifo reception level
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 492 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt(), and SPI_WaitFlagStateUntilTimeout().

#define __HAL_SPI_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__HANDLE__)->Instance->CR2\
                                                              & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified SPI interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
__INTERRUPT__ specifies the SPI interrupt source to check. This parameter can be one of the following values:
  • SPI_IT_TXE: Tx buffer empty interrupt enable
  • SPI_IT_RXNE: RX buffer not empty interrupt enable
  • SPI_IT_ERR: Error interrupt enable
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 473 of file stm32wbxx_hal_spi.h.

#define __HAL_SPI_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                  \
                                                                    (__HANDLE__)->State = HAL_SPI_STATE_RESET;       \
                                                                    (__HANDLE__)->MspInitCallback = NULL;            \
                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \
                                                                  } while(0)

Reset SPI handle state.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 430 of file stm32wbxx_hal_spi.h.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SPI Private Macros

Defines
SPI Private Macros
SPI

Defines

#define | SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
Set the SPI transmit-only mode.
#define | SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
Set the SPI receive-only mode.
#define | SPI_RESET_CRC(__HANDLE__)
Reset the CRC calculation of the SPI.
#define | SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
Check whether the specified SPI flag is set or not.
#define | SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified SPI Interrupt is set or not.
#define | IS_SPI_MODE(__MODE__)
Checks if SPI Mode parameter is in allowed range.
#define | IS_SPI_DIRECTION(__MODE__)
Checks if SPI Direction Mode parameter is in allowed range.
#define | IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)
Checks if SPI Direction Mode parameter is 2 lines.
#define | IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__)
Checks if SPI Direction Mode parameter is 1 or 2 lines.
#define | IS_SPI_DATASIZE(__DATASIZE__)
Checks if SPI Data Size parameter is in allowed range.
#define | IS_SPI_CPOL(__CPOL__)
Checks if SPI Serial clock steady state parameter is in allowed range.
#define | IS_SPI_CPHA(__CPHA__)
Checks if SPI Clock Phase parameter is in allowed range.
#define | IS_SPI_NSS(__NSS__)
Checks if SPI Slave Select parameter is in allowed range.
#define | IS_SPI_NSSP(__NSSP__)
Checks if SPI NSS Pulse parameter is in allowed range.
#define | IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__)
Checks if SPI Baudrate prescaler parameter is in allowed range.
#define | IS_SPI_FIRST_BIT(__BIT__)
Checks if SPI MSB LSB transmission parameter is in allowed range.
#define | IS_SPI_TIMODE(__MODE__)
Checks if SPI TI mode parameter is in allowed range.
#define | IS_SPI_CRC_CALCULATION(__CALCULATION__)
Checks if SPI CRC calculation enabled state is in allowed range.
#define | IS_SPI_CRC_LENGTH(__LENGTH__)
Checks if SPI CRC length is in allowed range.
#define | IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU) && (((__POLYNOMIAL__)&0x1U) != 0U))
Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
#define | IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL)
Checks if DMA handle is valid.

Define Documentation

#define IS_SPI_BAUDRATE_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2)   || \
                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4)   || \
                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8)   || \
                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16)  || \
                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32)  || \
                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64)  || \
                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \
                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))

Checks if SPI Baudrate prescaler parameter is in allowed range.

Parameters:
__PRESCALER__ specifies the SPI Baudrate prescaler. This parameter can be a value of SPI BaudRate Prescaler
Return values:
None

Definition at line 699 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CPHA ( __CPHA__ )
Value:
(((__CPHA__) == SPI_PHASE_1EDGE) || \
                               ((__CPHA__) == SPI_PHASE_2EDGE))

Checks if SPI Clock Phase parameter is in allowed range.

Parameters:
__CPHA__ specifies the SPI Clock Phase. This parameter can be a value of SPI Clock Phase
Return values:
None

Definition at line 674 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CPOL ( __CPOL__ )
Value:
(((__CPOL__) == SPI_POLARITY_LOW) || \
                               ((__CPOL__) == SPI_POLARITY_HIGH))

Checks if SPI Serial clock steady state parameter is in allowed range.

Parameters:
__CPOL__ specifies the SPI serial clock steady state. This parameter can be a value of SPI Clock Polarity
Return values:
None

Definition at line 666 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CRC_CALCULATION ( __CALCULATION__ )
Value:
(((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \
                                                 ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))

Checks if SPI CRC calculation enabled state is in allowed range.

Parameters:
__CALCULATION__ specifies the SPI CRC calculation enable state. This parameter can be a value of SPI CRC Calculation
Return values:
None

Definition at line 729 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CRC_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) ||\
                                       ((__LENGTH__) == SPI_CRC_LENGTH_8BIT)  ||   \
                                       ((__LENGTH__) == SPI_CRC_LENGTH_16BIT))

Checks if SPI CRC length is in allowed range.

Parameters:
__LENGTH__ specifies the SPI CRC length. This parameter can be a value of SPI CRC Length
Return values:
None

Definition at line 737 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CRC_POLYNOMIAL ( __POLYNOMIAL__ ) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU) && (((__POLYNOMIAL__)&0x1U) != 0U))

Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.

Parameters:
__POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation. This parameter must be a number between Min_Data = 0 and Max_Data = 65535
Return values:
None

Definition at line 746 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_DATASIZE ( __DATASIZE__ )
Value:
(((__DATASIZE__) == SPI_DATASIZE_16BIT) || \
                                       ((__DATASIZE__) == SPI_DATASIZE_15BIT) || \
                                       ((__DATASIZE__) == SPI_DATASIZE_14BIT) || \
                                       ((__DATASIZE__) == SPI_DATASIZE_13BIT) || \
                                       ((__DATASIZE__) == SPI_DATASIZE_12BIT) || \
                                       ((__DATASIZE__) == SPI_DATASIZE_11BIT) || \
                                       ((__DATASIZE__) == SPI_DATASIZE_10BIT) || \
                                       ((__DATASIZE__) == SPI_DATASIZE_9BIT)  || \
                                       ((__DATASIZE__) == SPI_DATASIZE_8BIT)  || \
                                       ((__DATASIZE__) == SPI_DATASIZE_7BIT)  || \
                                       ((__DATASIZE__) == SPI_DATASIZE_6BIT)  || \
                                       ((__DATASIZE__) == SPI_DATASIZE_5BIT)  || \
                                       ((__DATASIZE__) == SPI_DATASIZE_4BIT))

Checks if SPI Data Size parameter is in allowed range.

Parameters:
__DATASIZE__ specifies the SPI Data Size. This parameter can be a value of SPI Data Size
Return values:
None

Definition at line 647 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_DIRECTION ( __MODE__ )
Value:
(((__MODE__) == SPI_DIRECTION_2LINES)        || \
                                    ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \
                                    ((__MODE__) == SPI_DIRECTION_1LINE))

Checks if SPI Direction Mode parameter is in allowed range.

Parameters:
__MODE__ specifies the SPI Direction Mode. This parameter can be a value of SPI Direction Mode
Return values:
None

Definition at line 625 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_DIRECTION_2LINES ( __MODE__ ) ((__MODE__) == SPI_DIRECTION_2LINES)

Checks if SPI Direction Mode parameter is 2 lines.

Parameters:
__MODE__ specifies the SPI Direction Mode.
Return values:
None

Definition at line 633 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

#define IS_SPI_DIRECTION_2LINES_OR_1LINE ( __MODE__ )
Value:
(((__MODE__) == SPI_DIRECTION_2LINES) || \
                                                    ((__MODE__) == SPI_DIRECTION_1LINE))

Checks if SPI Direction Mode parameter is 1 or 2 lines.

Parameters:
__MODE__ specifies the SPI Direction Mode.
Return values:
None

Definition at line 639 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), and HAL_SPI_Transmit_IT().

#define IS_SPI_DMA_HANDLE ( __HANDLE__ ) ((__HANDLE__) != NULL)

Checks if DMA handle is valid.

Parameters:
__HANDLE__ specifies a DMA Handle.
Return values:
None

Definition at line 752 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

#define IS_SPI_FIRST_BIT ( __BIT__ )
Value:
(((__BIT__) == SPI_FIRSTBIT_MSB) || \
                                   ((__BIT__) == SPI_FIRSTBIT_LSB))

Checks if SPI MSB LSB transmission parameter is in allowed range.

Parameters:
__BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit). This parameter can be a value of SPI MSB LSB Transmission
Return values:
None

Definition at line 713 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_MODE ( __MODE__ )
Value:
(((__MODE__) == SPI_MODE_SLAVE) || \
                               ((__MODE__) == SPI_MODE_MASTER))

Checks if SPI Mode parameter is in allowed range.

Parameters:
__MODE__ specifies the SPI Mode. This parameter can be a value of SPI Mode
Return values:
None

Definition at line 617 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_NSS ( __NSS__ )
Value:
(((__NSS__) == SPI_NSS_SOFT)       || \
                             ((__NSS__) == SPI_NSS_HARD_INPUT) || \
                             ((__NSS__) == SPI_NSS_HARD_OUTPUT))

Checks if SPI Slave Select parameter is in allowed range.

Parameters:
__NSS__ specifies the SPI Slave Select management parameter. This parameter can be a value of SPI Slave Select Management
Return values:
None

Definition at line 682 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_NSSP ( __NSSP__ )
Value:
(((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \
                               ((__NSSP__) == SPI_NSS_PULSE_DISABLE))

Checks if SPI NSS Pulse parameter is in allowed range.

Parameters:
__NSSP__ specifies the SPI NSS Pulse Mode parameter. This parameter can be a value of SPI NSS Pulse Mode
Return values:
None

Definition at line 691 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_TIMODE ( __MODE__ )
Value:
(((__MODE__) == SPI_TIMODE_DISABLE) || \
                                 ((__MODE__) == SPI_TIMODE_ENABLE))

Checks if SPI TI mode parameter is in allowed range.

Parameters:
__MODE__ specifies the SPI TI mode. This parameter can be a value of SPI TI Mode
Return values:
None

Definition at line 721 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_1LINE_RX ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)

Set the SPI receive-only mode.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 574 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), and HAL_SPI_Receive_IT().

#define SPI_1LINE_TX ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)

Set the SPI transmit-only mode.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 567 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), and HAL_SPI_Transmit_IT().

#define SPI_CHECK_FLAG | ( | __SR__,
 |  | __FLAG__
 | ) | ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)

Check whether the specified SPI flag is set or not.

Parameters:
__SR__ copy of SPI SR regsiter.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • SPI_FLAG_RXNE: Receive buffer not empty flag
  • SPI_FLAG_TXE: Transmit buffer empty flag
  • SPI_FLAG_CRCERR: CRC error flag
  • SPI_FLAG_MODF: Mode fault flag
  • SPI_FLAG_OVR: Overrun flag
  • SPI_FLAG_BSY: Busy flag
  • SPI_FLAG_FRE: Frame format error flag
  • SPI_FLAG_FTLVL: SPI fifo transmission level
  • SPI_FLAG_FRLVL: SPI fifo reception level
Return values:
SET or RESET.

Definition at line 599 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define SPI_CHECK_IT_SOURCE | ( | __CR2__,
 |  | __INTERRUPT__
 | ) | ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified SPI Interrupt is set or not.

Parameters:
__CR2__ copy of SPI CR2 regsiter.
__INTERRUPT__ specifies the SPI interrupt source to check. This parameter can be one of the following values:
  • SPI_IT_TXE: Tx buffer empty interrupt enable
  • SPI_IT_RXNE: RX buffer not empty interrupt enable
  • SPI_IT_ERR: Error interrupt enable
Return values:
SET or RESET.

Definition at line 610 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define SPI_RESET_CRC ( __HANDLE__ )
Value:
do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
                                       SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)

Reset the CRC calculation of the SPI.

Parameters:
__HANDLE__ specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 581 of file stm32wbxx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_WaitFifoStateUntilTimeout(), and SPI_WaitFlagStateUntilTimeout().

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SPIEx Private Constants

Defines
SPIEx Private Constants
SPIEx

Defines

#define SPI_FIFO_SIZE 4UL

Define Documentation

#define SPI_FIFO_SIZE 4UL

Definition at line 42 of file stm32wbxx_hal_spi_ex.c.

Referenced by HAL_SPIEx_FlushRxFifo().

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IO operation functions

Functions
IO operation functions
SPIEx Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo (SPI_HandleTypeDef *hspi)
Flush the RX fifo.

Detailed Description

Data transfers functions.

  ==============================================================================
                      ##### IO operation functions #####
 ===============================================================================
 [..]
    This subsection provides a set of extended functions to manage the SPI
    data transfers.

    (#) Rx data flush function:
        (++) HAL_SPIEx_FlushRxFifo()

Function Documentation

HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo ( SPI_HandleTypeDef * hspi )

Flush the RX fifo.

Parameters:
hspi pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
HAL status

Definition at line 80 of file stm32wbxx_hal_spi_ex.c.

References __SPI_HandleTypeDef::Instance, SPI_FIFO_SIZE, SPI_FLAG_FRLVL, and SPI_FRLVL_EMPTY.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM Time Base functions

Functions
TIM Time Base functions
TIM Exported Functions

Time Base functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_Base_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_Base_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Base peripheral.
__weak void | HAL_TIM_Base_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Base MSP.
__weak void | HAL_TIM_Base_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Base MSP.
HAL_StatusTypeDef | HAL_TIM_Base_Start (TIM_HandleTypeDef *htim)
Starts the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in DMA mode.

Detailed Description

Time Base functions.

  ==============================================================================
              ##### Time Base functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM base.
    (+) De-initialize the TIM base.
    (+) Start the Time Base.
    (+) Stop the Time Base.
    (+) Start the Time Base and enable interrupt.
    (+) Stop the Time Base and disable interrupt.
    (+) Start the Time Base and enable DMA transfer.
    (+) Stop the Time Base and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_Base_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM Base peripheral.

Parameters:
htim TIM Base handle
Return values:
HAL status

Definition at line 328 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, __TIM_HandleTypeDef::Base_MspDeInitCallback, HAL_TIM_Base_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::Instance, and __TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_Base_Init ( TIM_HandleTypeDef * htim )

Initializes the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.

Note:
Switching from Center Aligned counter mode to Edge counter mode (or reverse) requires a timer reset to avoid unexpected direction due to DIR bit readonly in center aligned mode. Ex: call HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
Parameters:
htim TIM Base handle
Return values:
HAL status

Definition at line 276 of file stm32wbxx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, __TIM_HandleTypeDef::Base_MspInitCallback, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_Base_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::Init, __TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, __TIM_HandleTypeDef::Lock, __TIM_HandleTypeDef::State, TIM_Base_SetConfig(), and TIM_ResetCallback().

void HAL_TIM_Base_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Base MSP.

Parameters:
htim TIM Base handle
Return values:
None

Definition at line 379 of file stm32wbxx_hal_tim.c.

Referenced by HAL_TIM_Base_DeInit(), and HAL_TIM_UnRegisterCallback().

void HAL_TIM_Base_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Base MSP.

Parameters:
htim TIM Base handle
Return values:
None

Definition at line 364 of file stm32wbxx_hal_tim.c.

Referenced by HAL_TIM_Base_Init(), and HAL_TIM_UnRegisterCallback().

HAL_StatusTypeDef HAL_TIM_Base_Start ( TIM_HandleTypeDef * htim )

Starts the TIM Base generation.

Parameters:
htim TIM Base handle
Return values:
HAL status

Definition at line 395 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_ENABLE, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, and __TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_Base_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Base generation in DMA mode.

Parameters:
htim | TIM Base handle
pData | The source Buffer address.
Length | The length of data to be transferred from memory to peripheral.
Return values:
HAL status

Definition at line 494 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, __TIM_HandleTypeDef::State, TIM_DMA_ID_UPDATE, TIM_DMA_UPDATE, TIM_DMAError(), TIM_DMAPeriodElapsedCplt(), TIM_DMAPeriodElapsedHalfCplt(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_TIM_Base_Start_IT ( TIM_HandleTypeDef * htim )

Starts the TIM Base generation in interrupt mode.

Parameters:
htim TIM Base handle
Return values:
HAL status

Definition at line 447 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, and TIM_IT_UPDATE.

HAL_StatusTypeDef HAL_TIM_Base_Stop ( TIM_HandleTypeDef * htim )

Stops the TIM Base generation.

Parameters:
htim TIM Base handle
Return values:
HAL status

Definition at line 424 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, and __TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA ( TIM_HandleTypeDef * htim )

Stops the TIM Base generation in DMA mode.

Parameters:
htim TIM Base handle
Return values:
HAL status

Definition at line 553 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, HAL_DMA_Abort_IT(), HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::State, TIM_DMA_ID_UPDATE, and TIM_DMA_UPDATE.

HAL_StatusTypeDef HAL_TIM_Base_Stop_IT ( TIM_HandleTypeDef * htim )

Stops the TIM Base generation in interrupt mode.

Parameters:
htim TIM Base handle
Return values:
HAL status

Definition at line 473 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, __TIM_HandleTypeDef::Instance, and TIM_IT_UPDATE.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM Output Compare functions

Functions
TIM Output Compare functions
TIM Exported Functions

TIM Output Compare functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_OC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_OC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_OC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare MSP.
__weak void | HAL_TIM_OC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Output Compare MSP.
HAL_StatusTypeDef | HAL_TIM_OC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode.

Detailed Description

TIM Output Compare functions.

  ==============================================================================
                  ##### TIM Output Compare functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM Output Compare.
    (+) De-initialize the TIM Output Compare.
    (+) Start the TIM Output Compare.
    (+) Stop the TIM Output Compare.
    (+) Start the TIM Output Compare and enable interrupt.
    (+) Stop the TIM Output Compare and disable interrupt.
    (+) Start the TIM Output Compare and enable DMA transfer.
    (+) Stop the TIM Output Compare and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_OC_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM peripheral.

Parameters:
htim TIM Output Compare handle
Return values:
HAL status

Definition at line 660 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_OC_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::OC_MspDeInitCallback, and __TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_OC_Init ( TIM_HandleTypeDef * htim )

Initializes the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.

Note:
Switching from Center Aligned counter mode to Edge counter mode (or reverse) requires a timer reset to avoid unexpected direction due to DIR bit readonly in center aligned mode. Ex: call HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
Parameters:
htim TIM Output Compare handle
Return values:
HAL status

Definition at line 608 of file stm32wbxx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_OC_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::Init, __TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, __TIM_HandleTypeDef::Lock, __TIM_HandleTypeDef::OC_MspInitCallback, __TIM_HandleTypeDef::State, TIM_Base_SetConfig(), and TIM_ResetCallback().

void HAL_TIM_OC_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Output Compare MSP.

Parameters:
htim TIM Output Compare handle
Return values:
None

Definition at line 711 of file stm32wbxx_hal_tim.c.

Referenced by HAL_TIM_OC_DeInit(), and HAL_TIM_UnRegisterCallback().

void HAL_TIM_OC_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Output Compare MSP.

Parameters:
htim TIM Output Compare handle
Return values:
None

Definition at line 696 of file stm32wbxx_hal_tim.c.

Referenced by HAL_TIM_OC_Init(), and HAL_TIM_UnRegisterCallback().

HAL_StatusTypeDef HAL_TIM_OC_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation.

Parameters:
htim TIM Output Compare handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
HAL status

Definition at line 734 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_OC_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Output Compare signal generation in DMA mode.

Parameters:
htim | TIM Output Compare handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData | The source Buffer address.
Length | The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 946 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, __TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMADelayPulseCplt(), TIM_DMADelayPulseHalfCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_TIM_OC_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation in interrupt mode.

Parameters:
htim TIM Output Compare handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 806 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIM_OC_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation.

Parameters:
htim TIM Output Compare handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
HAL status

Definition at line 774 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in DMA mode.

Parameters:
htim TIM Output Compare handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1088 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_DMA_Abort_IT(), HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

HAL_StatusTypeDef HAL_TIM_OC_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in interrupt mode.

Parameters:
htim TIM Output Compare handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 878 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM PWM functions

Functions
TIM PWM functions
TIM Exported Functions

TIM PWM functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_PWM_Init (TIM_HandleTypeDef *htim)
Initializes the TIM PWM Time Base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_PWM_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_PWM_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM PWM MSP.
__weak void | HAL_TIM_PWM_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM PWM MSP.
HAL_StatusTypeDef | HAL_TIM_PWM_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode.

Detailed Description

TIM PWM functions.

  ==============================================================================
                          ##### TIM PWM functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM PWM.
    (+) De-initialize the TIM PWM.
    (+) Start the TIM PWM.
    (+) Stop the TIM PWM.
    (+) Start the TIM PWM and enable interrupt.
    (+) Stop the TIM PWM and disable interrupt.
    (+) Start the TIM PWM and enable DMA transfer.
    (+) Stop the TIM PWM and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_PWM_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM peripheral.

Parameters:
htim TIM PWM handle
Return values:
HAL status

Definition at line 1237 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_PWM_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::PWM_MspDeInitCallback, and __TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_PWM_Init ( TIM_HandleTypeDef * htim )

Initializes the TIM PWM Time Base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.

Note:
Switching from Center Aligned counter mode to Edge counter mode (or reverse) requires a timer reset to avoid unexpected direction due to DIR bit readonly in center aligned mode. Ex: call HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
Parameters:
htim TIM PWM handle
Return values:
HAL status

Definition at line 1185 of file stm32wbxx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_PWM_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::Init, __TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, __TIM_HandleTypeDef::Lock, __TIM_HandleTypeDef::PWM_MspInitCallback, __TIM_HandleTypeDef::State, TIM_Base_SetConfig(), and TIM_ResetCallback().

void HAL_TIM_PWM_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM PWM MSP.

Parameters:
htim TIM PWM handle
Return values:
None

Definition at line 1288 of file stm32wbxx_hal_tim.c.

Referenced by HAL_TIM_PWM_DeInit(), and HAL_TIM_UnRegisterCallback().

void HAL_TIM_PWM_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM PWM MSP.

Parameters:
htim TIM PWM handle
Return values:
None

Definition at line 1273 of file stm32wbxx_hal_tim.c.

Referenced by HAL_TIM_PWM_Init(), and HAL_TIM_UnRegisterCallback().

HAL_StatusTypeDef HAL_TIM_PWM_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation.

Parameters:
htim TIM handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
HAL status

Definition at line 1311 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM PWM signal generation in DMA mode.

Parameters:
htim | TIM PWM handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData | The source Buffer address.
Length | The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 1525 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, __TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMADelayPulseCplt(), TIM_DMADelayPulseHalfCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_TIM_PWM_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation in interrupt mode.

Parameters:
htim TIM PWM handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1386 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIM_PWM_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation.

Parameters:
htim TIM PWM handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
HAL status

Definition at line 1351 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::State, TIM_CCx_DISABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM PWM signal generation in DMA mode.

Parameters:
htim TIM PWM handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1666 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_DMA_Abort_IT(), HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation in interrupt mode.

Parameters:
htim TIM PWM handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1457 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM Input Capture functions

Functions
TIM Input Capture functions
TIM Exported Functions

TIM Input Capture functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_IC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_IC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_IC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture MSP.
__weak void | HAL_TIM_IC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Input Capture MSP.
HAL_StatusTypeDef | HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Input Capture measurement in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in DMA mode.

Detailed Description

TIM Input Capture functions.

  ==============================================================================
              ##### TIM Input Capture functions #####
  ==============================================================================
 [..]
   This section provides functions allowing to:
   (+) Initialize and configure the TIM Input Capture.
   (+) De-initialize the TIM Input Capture.
   (+) Start the TIM Input Capture.
   (+) Stop the TIM Input Capture.
   (+) Start the TIM Input Capture and enable interrupt.
   (+) Stop the TIM Input Capture and disable interrupt.
   (+) Start the TIM Input Capture and enable DMA transfer.
   (+) Stop the TIM Input Capture and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_IC_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM peripheral.

Parameters:
htim TIM Input Capture handle
Return values:
HAL status

Definition at line 1815 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_IC_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::IC_MspDeInitCallback, __TIM_HandleTypeDef::Instance, and __TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_IC_Init ( TIM_HandleTypeDef * htim )

Initializes the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.

Note:
Switching from Center Aligned counter mode to Edge counter mode (or reverse) requires a timer reset to avoid unexpected direction due to DIR bit readonly in center aligned mode. Ex: call HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
Parameters:
htim TIM Input Capture handle
Return values:
HAL status

Definition at line 1763 of file stm32wbxx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_IC_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::IC_MspInitCallback, __TIM_HandleTypeDef::Init, __TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, __TIM_HandleTypeDef::Lock, __TIM_HandleTypeDef::State, TIM_Base_SetConfig(), and TIM_ResetCallback().

void HAL_TIM_IC_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Input Capture MSP.

Parameters:
htim TIM handle
Return values:
None

Definition at line 1866 of file stm32wbxx_hal_tim.c.

Referenced by HAL_TIM_IC_DeInit(), and HAL_TIM_UnRegisterCallback().

void HAL_TIM_IC_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Input Capture MSP.

Parameters:
htim TIM Input Capture handle
Return values:
None

Definition at line 1851 of file stm32wbxx_hal_tim.c.

Referenced by HAL_TIM_IC_Init(), and HAL_TIM_UnRegisterCallback().

HAL_StatusTypeDef HAL_TIM_IC_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Input Capture measurement.

Parameters:
htim TIM Input Capture handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1887 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_ENABLE, assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_IC_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Input Capture measurement in DMA mode.

Parameters:
htim | TIM Input Capture handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData | The destination Buffer address.
Length | The length of data to be transferred from TIM peripheral to memory.
Return values:
HAL status

Definition at line 2072 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, __TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_TIM_IC_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Input Capture measurement in interrupt mode.

Parameters:
htim TIM Input Capture handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1945 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIM_IC_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Input Capture measurement.

Parameters:
htim TIM Input Capture handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1919 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Input Capture measurement in DMA mode.

Parameters:
htim TIM Input Capture handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 2207 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, HAL_DMA_Abort_IT(), HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

HAL_StatusTypeDef HAL_TIM_IC_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Input Capture measurement in interrupt mode.

Parameters:
htim TIM Input Capture handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 2010 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM One Pulse functions

Functions
TIM One Pulse functions
TIM Exported Functions

TIM One Pulse functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_OnePulse_Init (TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
Initializes the TIM One Pulse Time Base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_OnePulse_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM One Pulse.
__weak void | HAL_TIM_OnePulse_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM One Pulse MSP.
__weak void | HAL_TIM_OnePulse_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM One Pulse MSP.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode.

Detailed Description

TIM One Pulse functions.

  ==============================================================================
                        ##### TIM One Pulse functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM One Pulse.
    (+) De-initialize the TIM One Pulse.
    (+) Start the TIM One Pulse.
    (+) Stop the TIM One Pulse.
    (+) Start the TIM One Pulse and enable interrupt.
    (+) Stop the TIM One Pulse and disable interrupt.
    (+) Start the TIM One Pulse and enable DMA transfer.
    (+) Stop the TIM One Pulse and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM One Pulse.

Parameters:
htim TIM One Pulse handle
Return values:
HAL status

Definition at line 2361 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_OnePulse_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::OnePulse_MspDeInitCallback, and __TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_OnePulse_Init | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OnePulseMode
 | ) |  |

Initializes the TIM One Pulse Time Base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.

Note:
Switching from Center Aligned counter mode to Edge counter mode (or reverse) requires a timer reset to avoid unexpected direction due to DIR bit readonly in center aligned mode. Ex: call HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
Parameters:
htim TIM One Pulse handle
OnePulseMode Select the One pulse mode. This parameter can be one of the following values:
  • TIM_OPMODE_SINGLE: Only one pulse will be generated.
  • TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
Return values:
HAL status

Definition at line 2302 of file stm32wbxx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_OnePulse_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::Init, __TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, IS_TIM_OPM_MODE, __TIM_HandleTypeDef::Lock, __TIM_HandleTypeDef::OnePulse_MspInitCallback, __TIM_HandleTypeDef::State, TIM_Base_SetConfig(), and TIM_ResetCallback().

void HAL_TIM_OnePulse_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM One Pulse MSP.

Parameters:
htim TIM One Pulse handle
Return values:
None

Definition at line 2412 of file stm32wbxx_hal_tim.c.

Referenced by HAL_TIM_OnePulse_DeInit(), and HAL_TIM_UnRegisterCallback().

void HAL_TIM_OnePulse_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM One Pulse MSP.

Parameters:
htim TIM One Pulse handle
Return values:
None

Definition at line 2397 of file stm32wbxx_hal_tim.c.

Referenced by HAL_TIM_OnePulse_Init(), and HAL_TIM_UnRegisterCallback().

HAL_StatusTypeDef HAL_TIM_OnePulse_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation.

Parameters:
htim TIM One Pulse handle
OutputChannel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 2431 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_MOE_ENABLE, __TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_CHANNEL_2.

HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation in interrupt mode.

Parameters:
htim TIM One Pulse handle
OutputChannel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 2503 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, __TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_IT_CC1, and TIM_IT_CC2.

HAL_StatusTypeDef HAL_TIM_OnePulse_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation.

Parameters:
htim TIM One Pulse handle
OutputChannel TIM Channels to be disable This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 2467 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_CHANNEL_2.

HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation in interrupt mode.

Parameters:
htim TIM One Pulse handle
OutputChannel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 2545 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_IT_CC1, and TIM_IT_CC2.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM Encoder functions

Functions
TIM Encoder functions
TIM Exported Functions

TIM Encoder functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_Encoder_Init (TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
Initializes the TIM Encoder Interface and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_Encoder_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Encoder interface.
__weak void | HAL_TIM_Encoder_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Encoder Interface MSP.
__weak void | HAL_TIM_Encoder_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Encoder Interface MSP.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
Starts the TIM Encoder Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in DMA mode.

Detailed Description

TIM Encoder functions.

  ==============================================================================
                          ##### TIM Encoder functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM Encoder.
    (+) De-initialize the TIM Encoder.
    (+) Start the TIM Encoder.
    (+) Stop the TIM Encoder.
    (+) Start the TIM Encoder and enable interrupt.
    (+) Stop the TIM Encoder and disable interrupt.
    (+) Start the TIM Encoder and enable DMA transfer.
    (+) Stop the TIM Encoder and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_Encoder_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM Encoder interface.

Parameters:
htim TIM Encoder Interface handle
Return values:
HAL status

Definition at line 2720 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, __TIM_HandleTypeDef::Encoder_MspDeInitCallback, HAL_TIM_Encoder_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, __TIM_HandleTypeDef::Instance, and __TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_Encoder_Init | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_Encoder_InitTypeDef * | sConfig
 | ) |  |

Initializes the TIM Encoder Interface and initialize the associated handle.

Note:
Switching from Center Aligned counter mode to Edge counter mode (or reverse) requires a timer reset to avoid unexpected direction due to DIR bit readonly in center aligned mode. Ex: call HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
Encoder mode and External clock mode 2 are not compatible and must not be selected together Ex: A call for HAL_TIM_Encoder_Init will erase the settings of HAL_TIM_ConfigClockSource using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
Parameters:
htim | TIM Encoder Interface handle
sConfig | TIM Encoder Interface configuration structure
Return values:
HAL status

Definition at line 2615 of file stm32wbxx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, __TIM_HandleTypeDef::Encoder_MspInitCallback, TIM_Encoder_InitTypeDef::EncoderMode, HAL_TIM_Encoder_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_Encoder_InitTypeDef::IC1Filter, TIM_Encoder_InitTypeDef::IC1Polarity, TIM_Encoder_InitTypeDef::IC1Prescaler, TIM_Encoder_InitTypeDef::IC1Selection, TIM_Encoder_InitTypeDef::IC2Filter, TIM_Encoder_InitTypeDef::IC2Polarity, TIM_Encoder_InitTypeDef::IC2Prescaler, TIM_Encoder_InitTypeDef::IC2Selection, __TIM_HandleTypeDef::Init, __TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, IS_TIM_ENCODER_MODE, IS_TIM_ENCODERINPUT_POLARITY, IS_TIM_IC_FILTER, IS_TIM_IC_PRESCALER, IS_TIM_IC_SELECTION, __TIM_HandleTypeDef::Lock, __TIM_HandleTypeDef::State, TIM_Base_SetConfig(), and TIM_ResetCallback().

void HAL_TIM_Encoder_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Encoder Interface MSP.

Parameters:
htim TIM Encoder Interface handle
Return values:
None

Definition at line 2771 of file stm32wbxx_hal_tim.c.

Referenced by HAL_TIM_Encoder_DeInit(), and HAL_TIM_UnRegisterCallback().

void HAL_TIM_Encoder_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Encoder Interface MSP.

Parameters:
htim TIM Encoder Interface handle
Return values:
None

Definition at line 2756 of file stm32wbxx_hal_tim.c.

Referenced by HAL_TIM_Encoder_Init(), and HAL_TIM_UnRegisterCallback().

HAL_StatusTypeDef HAL_TIM_Encoder_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Encoder Interface.

Parameters:
htim TIM Encoder Interface handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 2791 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_ENABLE, assert_param, __TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_CHANNEL_2.

HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData1,
 |  | uint32_t * | pData2,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Encoder Interface in DMA mode.

Parameters:
htim | TIM Encoder Interface handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
pData1 | The destination Buffer address for IC1.
pData2 | The destination Buffer address for IC2.
Length | The length of data to be transferred from TIM peripheral to memory.
Return values:
HAL status

Definition at line 2985 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_ALL, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Encoder Interface in interrupt mode.

Parameters:
htim TIM Encoder Interface handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 2881 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, __TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_IT_CC1, and TIM_IT_CC2.

HAL_StatusTypeDef HAL_TIM_Encoder_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Encoder Interface.

Parameters:
htim TIM Encoder Interface handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 2835 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_CHANNEL_2.

HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Encoder Interface in DMA mode.

Parameters:
htim TIM Encoder Interface handle
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 3120 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, HAL_DMA_Abort_IT(), HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_ID_CC1, and TIM_DMA_ID_CC2.

HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Encoder Interface in interrupt mode.

Parameters:
htim TIM Encoder Interface handle
Channel TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 2931 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_IT_CC1, and TIM_IT_CC2.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM IRQ handler management

Functions
TIM IRQ handler management
TIM Exported Functions

TIM IRQ handler management. More...

Functions

void HAL_TIM_IRQHandler (TIM_HandleTypeDef *htim)
This function handles TIM interrupts requests.

Detailed Description

TIM IRQ handler management.

IRQ handler management.

  ==============================================================================
                        ##### IRQ handler management #####
  ==============================================================================
  [..]
    This section provides Timer IRQ handler function.

Function Documentation

void HAL_TIM_IRQHandler ( TIM_HandleTypeDef * htim )

This function handles TIM interrupts requests.

Parameters:
htim TIM handle
Return values:
None

Definition at line 3186 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_CLEAR_FLAG, __HAL_TIM_CLEAR_IT, __HAL_TIM_GET_FLAG, __HAL_TIM_GET_IT_SOURCE, __TIM_HandleTypeDef::Break2Callback, __TIM_HandleTypeDef::BreakCallback, __TIM_HandleTypeDef::Channel, __TIM_HandleTypeDef::CommutationCallback, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_IC_CaptureCallback(), HAL_TIM_OC_DelayElapsedCallback(), HAL_TIM_PeriodElapsedCallback(), HAL_TIM_PWM_PulseFinishedCallback(), HAL_TIM_TriggerCallback(), HAL_TIMEx_Break2Callback(), HAL_TIMEx_BreakCallback(), HAL_TIMEx_CommutCallback(), __TIM_HandleTypeDef::IC_CaptureCallback, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::OC_DelayElapsedCallback, __TIM_HandleTypeDef::PeriodElapsedCallback, __TIM_HandleTypeDef::PWM_PulseFinishedCallback, TIM_FLAG_BREAK, TIM_FLAG_BREAK2, TIM_FLAG_CC1, TIM_FLAG_CC2, TIM_FLAG_CC3, TIM_FLAG_CC4, TIM_FLAG_COM, TIM_FLAG_TRIGGER, TIM_FLAG_UPDATE, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, TIM_IT_CC4, TIM_IT_COM, TIM_IT_TRIGGER, TIM_IT_UPDATE, and __TIM_HandleTypeDef::TriggerCallback.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM Peripheral Control functions

Functions
TIM Peripheral Control functions
TIM Exported Functions

TIM Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_OC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_IC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_PWM_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_OnePulse_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
Initializes the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stops the TIM DMA Burst mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stop the DMA burst reading.
HAL_StatusTypeDef | HAL_TIM_GenerateEvent (TIM_HandleTypeDef *htim, uint32_t EventSource)
Generate a software event.
HAL_StatusTypeDef | HAL_TIM_ConfigOCrefClear (TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel)
Configures the OCRef clear feature.
HAL_StatusTypeDef | HAL_TIM_ConfigClockSource (TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
Configures the clock source to be used.
HAL_StatusTypeDef | HAL_TIM_ConfigTI1Input (TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchro (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchro_IT (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode in interrupt mode.
uint32_t | HAL_TIM_ReadCapturedValue (TIM_HandleTypeDef *htim, uint32_t Channel)
Read the captured value from Capture Compare unit.

Detailed Description

TIM Peripheral Control functions.

Peripheral Control functions.

  ==============================================================================
                   ##### Peripheral Control functions #####
  ==============================================================================
 [..]
   This section provides functions allowing to:
      (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
      (+) Configure External Clock source.
      (+) Configure Complementary channels, break features and dead time.
      (+) Configure Master and the Slave synchronization.
      (+) Configure the DMA Burst Mode.

Function Documentation

HAL_StatusTypeDef HAL_TIM_ConfigClockSource | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_ClockConfigTypeDef * | sClockSourceConfig
 | ) |  |

Configures the clock source to be used.

Parameters:
htim | TIM handle
sClockSourceConfig | pointer to a TIM_ClockConfigTypeDef structure that contains the clock source information for the TIM peripheral.
Return values:
HAL status

Definition at line 4633 of file stm32wbxx_hal_tim.c.

References assert_param, TIM_ClockConfigTypeDef::ClockFilter, TIM_ClockConfigTypeDef::ClockPolarity, TIM_ClockConfigTypeDef::ClockPrescaler, TIM_ClockConfigTypeDef::ClockSource, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_CLOCKFILTER, IS_TIM_CLOCKPOLARITY, IS_TIM_CLOCKPRESCALER, IS_TIM_CLOCKSOURCE, __TIM_HandleTypeDef::State, TIM_CLOCKSOURCE_ETRMODE1, TIM_CLOCKSOURCE_ETRMODE2, TIM_CLOCKSOURCE_INTERNAL, TIM_CLOCKSOURCE_ITR0, TIM_CLOCKSOURCE_ITR1, TIM_CLOCKSOURCE_ITR2, TIM_CLOCKSOURCE_ITR3, TIM_CLOCKSOURCE_TI1, TIM_CLOCKSOURCE_TI1ED, TIM_CLOCKSOURCE_TI2, TIM_ETR_SetConfig(), TIM_ITRx_SetConfig(), TIM_SLAVEMODE_EXTERNAL1, TIM_TI1_ConfigInputStage(), and TIM_TI2_ConfigInputStage().

HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_ClearInputConfigTypeDef * | sClearInputConfig,
 |  | uint32_t | Channel
 | ) |  |

Configures the OCRef clear feature.

Parameters:
htim | TIM handle
sClearInputConfig | pointer to a TIM_ClearInputConfigTypeDef structure that contains the OCREF clear feature and parameters for the TIM peripheral.
Channel specifies the TIM Channel This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1
  • TIM_CHANNEL_2: TIM Channel 2
  • TIM_CHANNEL_3: TIM Channel 3
  • TIM_CHANNEL_4: TIM Channel 4
  • TIM_CHANNEL_5: TIM Channel 5
  • TIM_CHANNEL_6: TIM Channel 6
Return values:
HAL status

Definition at line 4462 of file stm32wbxx_hal_tim.c.

References assert_param, TIM_ClearInputConfigTypeDef::ClearInputFilter, TIM_ClearInputConfigTypeDef::ClearInputPolarity, TIM_ClearInputConfigTypeDef::ClearInputPrescaler, TIM_ClearInputConfigTypeDef::ClearInputSource, TIM_ClearInputConfigTypeDef::ClearInputState, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_CLEARINPUT_FILTER, IS_TIM_CLEARINPUT_POLARITY, IS_TIM_CLEARINPUT_PRESCALER, IS_TIM_CLEARINPUT_SOURCE, __TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_5, TIM_CHANNEL_6, TIM_CLEARINPUTPRESCALER_DIV1, TIM_CLEARINPUTSOURCE_COMP1, TIM_CLEARINPUTSOURCE_COMP2, TIM_CLEARINPUTSOURCE_ETR, TIM_CLEARINPUTSOURCE_NONE, and TIM_ETR_SetConfig().

HAL_StatusTypeDef HAL_TIM_ConfigTI1Input | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | TI1_Selection
 | ) |  |

Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.

Parameters:
htim TIM handle.
TI1_Selection Indicate whether or not channel 1 is connected to the output of a XOR gate. This parameter can be one of the following values:
  • TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
  • TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)
Return values:
HAL status

Definition at line 4785 of file stm32wbxx_hal_tim.c.

References assert_param, __TIM_HandleTypeDef::Instance, and IS_TIM_TI1SELECTION.

HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstBaseAddress,
 |  | uint32_t | BurstRequestSrc,
 |  | uint32_t * | BurstBuffer,
 |  | uint32_t | BurstLength
 | ) |  |

Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.

Parameters:
htim | TIM handle
BurstBaseAddress TIM Base address from where the DMA will start the Data read This parameter can be one of the following values:
  • TIM_DMABASE_CR1
  • TIM_DMABASE_CR2
  • TIM_DMABASE_SMCR
  • TIM_DMABASE_DIER
  • TIM_DMABASE_SR
  • TIM_DMABASE_EGR
  • TIM_DMABASE_CCMR1
  • TIM_DMABASE_CCMR2
  • TIM_DMABASE_CCER
  • TIM_DMABASE_CNT
  • TIM_DMABASE_PSC
  • TIM_DMABASE_ARR
  • TIM_DMABASE_RCR
  • TIM_DMABASE_CCR1
  • TIM_DMABASE_CCR2
  • TIM_DMABASE_CCR3
  • TIM_DMABASE_CCR4
  • TIM_DMABASE_BDTR
  • TIM_DMABASE_OR
  • TIM_DMABASE_CCMR3
  • TIM_DMABASE_CCR5
  • TIM_DMABASE_CCR6
  • TIM_DMABASE_AF1
  • TIM_DMABASE_AF2
BurstRequestSrc TIM DMA Request sources This parameter can be one of the following values:
  • TIM_DMA_UPDATE: TIM update Interrupt source
  • TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  • TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  • TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  • TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  • TIM_DMA_COM: TIM Commutation DMA source
  • TIM_DMA_TRIGGER: TIM Trigger DMA source
BurstBuffer | The Buffer address.
BurstLength | DMA Burst length. This parameter can be one value between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
Note:
This function should be used only when BurstLength is equal to DMA data transfer length.
Return values:
HAL status

Definition at line 4180 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_DMA_BASE, IS_TIM_DMA_LENGTH, IS_TIM_DMA_SOURCE, __TIM_HandleTypeDef::State, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, TIM_DMA_UPDATE, TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMAError(), TIM_DMAPeriodElapsedCplt(), TIM_DMAPeriodElapsedHalfCplt(), TIM_DMATriggerCplt(), TIM_DMATriggerHalfCplt(), TIMEx_DMACommutationCplt(), TIMEx_DMACommutationHalfCplt(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstRequestSrc
 | ) |  |

Stop the DMA burst reading.

Parameters:
htim | TIM handle
BurstRequestSrc | TIM DMA Request sources to disable.
Return values:
HAL status

Definition at line 4344 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_DISABLE_DMA, assert_param, HAL_DMA_Abort_IT(), __TIM_HandleTypeDef::hdma, IS_TIM_DMA_SOURCE, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, and TIM_DMA_UPDATE.

HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstBaseAddress,
 |  | uint32_t | BurstRequestSrc,
 |  | uint32_t * | BurstBuffer,
 |  | uint32_t | BurstLength
 | ) |  |

Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.

Parameters:
htim | TIM handle
BurstBaseAddress TIM Base address from where the DMA will start the Data write This parameter can be one of the following values:
  • TIM_DMABASE_CR1
  • TIM_DMABASE_CR2
  • TIM_DMABASE_SMCR
  • TIM_DMABASE_DIER
  • TIM_DMABASE_SR
  • TIM_DMABASE_EGR
  • TIM_DMABASE_CCMR1
  • TIM_DMABASE_CCMR2
  • TIM_DMABASE_CCER
  • TIM_DMABASE_CNT
  • TIM_DMABASE_PSC
  • TIM_DMABASE_ARR
  • TIM_DMABASE_RCR
  • TIM_DMABASE_CCR1
  • TIM_DMABASE_CCR2
  • TIM_DMABASE_CCR3
  • TIM_DMABASE_CCR4
  • TIM_DMABASE_BDTR
  • TIM_DMABASE_OR
  • TIM_DMABASE_CCMR3
  • TIM_DMABASE_CCR5
  • TIM_DMABASE_CCR6
  • TIM_DMABASE_AF1
  • TIM_DMABASE_AF2
BurstRequestSrc TIM DMA Request sources This parameter can be one of the following values:
  • TIM_DMA_UPDATE: TIM update Interrupt source
  • TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  • TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  • TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  • TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  • TIM_DMA_COM: TIM Commutation DMA source
  • TIM_DMA_TRIGGER: TIM Trigger DMA source
BurstBuffer | The Buffer address.
BurstLength | DMA Burst length. This parameter can be one value between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
Note:
This function should be used only when BurstLength is equal to DMA data transfer length.
Return values:
HAL status

Definition at line 3909 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_DMA_BASE, IS_TIM_DMA_LENGTH, IS_TIM_DMA_SOURCE, __TIM_HandleTypeDef::State, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, TIM_DMA_UPDATE, TIM_DMADelayPulseCplt(), TIM_DMADelayPulseHalfCplt(), TIM_DMAError(), TIM_DMAPeriodElapsedCplt(), TIM_DMAPeriodElapsedHalfCplt(), TIM_DMATriggerCplt(), TIM_DMATriggerHalfCplt(), TIMEx_DMACommutationCplt(), TIMEx_DMACommutationHalfCplt(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstRequestSrc
 | ) |  |

Stops the TIM DMA Burst mode.

Parameters:
htim | TIM handle
BurstRequestSrc | TIM DMA Request sources to disable
Return values:
HAL status

Definition at line 4078 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_DISABLE_DMA, assert_param, HAL_DMA_Abort_IT(), __TIM_HandleTypeDef::hdma, IS_TIM_DMA_SOURCE, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, and TIM_DMA_UPDATE.

HAL_StatusTypeDef HAL_TIM_GenerateEvent | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | EventSource
 | ) |  |

Generate a software event.

Parameters:
htim TIM handle
EventSource specifies the event source. This parameter can be one of the following values:
  • TIM_EVENTSOURCE_UPDATE: Timer update Event source
  • TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
  • TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
  • TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
  • TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
  • TIM_EVENTSOURCE_COM: Timer COM event source
  • TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
  • TIM_EVENTSOURCE_BREAK: Timer Break event source
  • TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
Note:
Basic timers can only generate an update event.
TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant only for timer instances supporting break input(s).
Return values:
HAL status

Definition at line 4423 of file stm32wbxx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_EVENT_SOURCE, and __TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_IC_InitTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Initializes the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.

Parameters:
htim | TIM IC handle
sConfig | TIM Input Capture configuration structure
Channel TIM Channel to configure This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 3516 of file stm32wbxx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_IC_InitTypeDef::ICFilter, TIM_IC_InitTypeDef::ICPolarity, TIM_IC_InitTypeDef::ICPrescaler, TIM_IC_InitTypeDef::ICSelection, __TIM_HandleTypeDef::Instance, IS_TIM_IC_FILTER, IS_TIM_IC_POLARITY, IS_TIM_IC_PRESCALER, IS_TIM_IC_SELECTION, __TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_TI1_SetConfig(), TIM_TI2_SetConfig(), TIM_TI3_SetConfig(), and TIM_TI4_SetConfig().

HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_OC_InitTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.

Parameters:
htim | TIM Output Compare handle
sConfig | TIM Output Compare configuration structure
Channel TIM Channels to configure This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
HAL status

Definition at line 3416 of file stm32wbxx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_CHANNELS, IS_TIM_OC_MODE, IS_TIM_OC_POLARITY, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, __TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_5, TIM_CHANNEL_6, TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_OnePulse_InitTypeDef * | sConfig,
 |  | uint32_t | OutputChannel,
 |  | uint32_t | InputChannel
 | ) |  |

Initializes the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.

Parameters:
htim | TIM One Pulse handle
sConfig | TIM One Pulse configuration structure
OutputChannel TIM output channel to configure This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
InputChannel TIM input Channel to configure This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Note:
To output a waveform with a minimum delay user can enable the fast mode by calling the __HAL_TIM_ENABLE_OCxFAST macro. Then CCx output is forced in response to the edge detection on TIx input, without taking in account the comparison.
Return values:
HAL status

Definition at line 3764 of file stm32wbxx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_OnePulse_InitTypeDef::ICFilter, TIM_OnePulse_InitTypeDef::ICPolarity, TIM_OnePulse_InitTypeDef::ICSelection, __TIM_HandleTypeDef::Instance, IS_TIM_OPM_CHANNELS, TIM_OC_InitTypeDef::OCIdleState, TIM_OnePulse_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OnePulse_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OnePulse_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OnePulse_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OnePulse_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, TIM_OnePulse_InitTypeDef::Pulse, __TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_SLAVEMODE_TRIGGER, TIM_TI1_SetConfig(), TIM_TI2_SetConfig(), TIM_TS_TI1FP1, and TIM_TS_TI2FP2.

HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_OC_InitTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.

Parameters:
htim | TIM PWM handle
sConfig | TIM PWM configuration structure
Channel TIM Channels to be configured This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
HAL status

Definition at line 3615 of file stm32wbxx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_CHANNELS, IS_TIM_FAST_STATE, IS_TIM_OC_POLARITY, IS_TIM_PWM_MODE, TIM_OC_InitTypeDef::OCFastMode, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, __TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CHANNEL_5, TIM_CHANNEL_6, TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

uint32_t HAL_TIM_ReadCapturedValue | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Read the captured value from Capture Compare unit.

Parameters:
htim TIM handle.
Channel TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
Captured value

Definition at line 4900 of file stm32wbxx_hal_tim.c.

References assert_param, __TIM_HandleTypeDef::Instance, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, and TIM_CHANNEL_4.

HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_SlaveConfigTypeDef * | sSlaveConfig
 | ) |  |

Configures the TIM in Slave mode.

Parameters:
htim | TIM handle.
sSlaveConfig | pointer to a TIM_SlaveConfigTypeDef structure that contains the selected trigger (internal trigger input, filtered timer input or external trigger input) and the Slave mode (Disable, Reset, Gated, Trigger, External clock mode 1).
Return values:
HAL status

Definition at line 4817 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_DISABLE_DMA, __HAL_TIM_DISABLE_IT, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_SlaveConfigTypeDef::InputTrigger, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVE_MODE, IS_TIM_TRIGGER_SELECTION, TIM_SlaveConfigTypeDef::SlaveMode, __TIM_HandleTypeDef::State, TIM_DMA_TRIGGER, TIM_IT_TRIGGER, and TIM_SlaveTimer_SetConfig().

HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_SlaveConfigTypeDef * | sSlaveConfig
 | ) |  |

Configures the TIM in Slave mode in interrupt mode.

Parameters:
htim | TIM handle.
sSlaveConfig | pointer to a TIM_SlaveConfigTypeDef structure that contains the selected trigger (internal trigger input, filtered timer input or external trigger input) and the Slave mode (Disable, Reset, Gated, Trigger, External clock mode 1).
Return values:
HAL status

Definition at line 4857 of file stm32wbxx_hal_tim.c.

References __HAL_TIM_DISABLE_DMA, __HAL_TIM_ENABLE_IT, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_SlaveConfigTypeDef::InputTrigger, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVE_MODE, IS_TIM_TRIGGER_SELECTION, TIM_SlaveConfigTypeDef::SlaveMode, __TIM_HandleTypeDef::State, TIM_DMA_TRIGGER, TIM_IT_TRIGGER, and TIM_SlaveTimer_SetConfig().

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM Callbacks functions

Functions
TIM Callbacks functions
TIM Exported Functions

TIM Callbacks functions. More...

Functions

__weak void | HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef *htim)
Period elapsed callback in non-blocking mode.
__weak void | HAL_TIM_PeriodElapsedHalfCpltCallback (TIM_HandleTypeDef *htim)
Period elapsed half complete callback in non-blocking mode.
__weak void | HAL_TIM_OC_DelayElapsedCallback (TIM_HandleTypeDef *htim)
Output Compare callback in non-blocking mode.
__weak void | HAL_TIM_IC_CaptureCallback (TIM_HandleTypeDef *htim)
Input Capture callback in non-blocking mode.
__weak void | HAL_TIM_IC_CaptureHalfCpltCallback (TIM_HandleTypeDef *htim)
Input Capture half complete callback in non-blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished callback in non-blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedHalfCpltCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished half complete callback in non-blocking mode.
__weak void | HAL_TIM_TriggerCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection callback in non-blocking mode.
__weak void | HAL_TIM_TriggerHalfCpltCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection half complete callback in non-blocking mode.
__weak void | HAL_TIM_ErrorCallback (TIM_HandleTypeDef *htim)
Timer error callback in non-blocking mode.
HAL_StatusTypeDef | HAL_TIM_RegisterCallback (TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback)
Register a User TIM callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_TIM_UnRegisterCallback (TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
Unregister a TIM callback TIM callback is redirected to the weak predefined callback.

Detailed Description

TIM Callbacks functions.

  ==============================================================================
                        ##### TIM Callbacks functions #####
  ==============================================================================
 [..]
   This section provides TIM callback functions:
   (+) TIM Period elapsed callback
   (+) TIM Output Compare callback
   (+) TIM Input capture callback
   (+) TIM Trigger callback
   (+) TIM Error callback

Function Documentation

void HAL_TIM_ErrorCallback ( TIM_HandleTypeDef * htim )

Timer error callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 5119 of file stm32wbxx_hal_tim.c.

Referenced by HAL_TIM_UnRegisterCallback(), TIM_DMAError(), and TIM_ResetCallback().

void HAL_TIM_IC_CaptureCallback ( TIM_HandleTypeDef * htim )

Input Capture callback in non-blocking mode.

Parameters:
htim TIM IC handle
Return values:
None

Definition at line 5029 of file stm32wbxx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_UnRegisterCallback(), TIM_DMACaptureCplt(), and TIM_ResetCallback().

void HAL_TIM_IC_CaptureHalfCpltCallback ( TIM_HandleTypeDef * htim )

Input Capture half complete callback in non-blocking mode.

Parameters:
htim TIM IC handle
Return values:
None

Definition at line 5044 of file stm32wbxx_hal_tim.c.

Referenced by HAL_TIM_UnRegisterCallback(), TIM_DMACaptureHalfCplt(), and TIM_ResetCallback().

void HAL_TIM_OC_DelayElapsedCallback ( TIM_HandleTypeDef * htim )

Output Compare callback in non-blocking mode.

Parameters:
htim TIM OC handle
Return values:
None

Definition at line 5014 of file stm32wbxx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_UnRegisterCallback(), and TIM_ResetCallback().

void HAL_TIM_PeriodElapsedCallback ( TIM_HandleTypeDef * htim )

Period elapsed callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 4984 of file stm32wbxx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_UnRegisterCallback(), TIM_DMAPeriodElapsedCplt(), and TIM_ResetCallback().

void HAL_TIM_PeriodElapsedHalfCpltCallback ( TIM_HandleTypeDef * htim )

Period elapsed half complete callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 4999 of file stm32wbxx_hal_tim.c.

Referenced by HAL_TIM_UnRegisterCallback(), TIM_DMAPeriodElapsedHalfCplt(), and TIM_ResetCallback().

void HAL_TIM_PWM_PulseFinishedCallback ( TIM_HandleTypeDef * htim )

PWM Pulse finished callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 5059 of file stm32wbxx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_UnRegisterCallback(), TIM_DMADelayPulseCplt(), and TIM_ResetCallback().

void HAL_TIM_PWM_PulseFinishedHalfCpltCallback ( TIM_HandleTypeDef * htim )

PWM Pulse finished half complete callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 5074 of file stm32wbxx_hal_tim.c.

Referenced by HAL_TIM_UnRegisterCallback(), TIM_DMADelayPulseHalfCplt(), and TIM_ResetCallback().

HAL_StatusTypeDef HAL_TIM_RegisterCallback | ( | TIM_HandleTypeDef * | htim,
 |  | HAL_TIM_CallbackIDTypeDef | CallbackID,
 |  | pTIM_CallbackTypeDef | pCallback
 | ) |  |

Register a User TIM callback to be used instead of the weak predefined callback.

Parameters:
htim | tim handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
  • HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
  • HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
  • HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
  • HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
  • HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
  • HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
  • HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
  • HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
  • HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
  • HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
  • HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
  • HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
  • HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
  • HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
  • HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
  • HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
  • HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
  • HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
  • HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
  • HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
  • HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
  • HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
  • HAL_TIM_ERROR_CB_ID Error Callback ID
  • HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
  • HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
  • HAL_TIM_BREAK_CB_ID Break Callback ID
  • HAL_TIM_BREAK2_CB_ID Break2 Callback ID
pCallback | pointer to the callback function
Return values:
status

Definition at line 5166 of file stm32wbxx_hal_tim.c.

References __TIM_HandleTypeDef::Base_MspDeInitCallback, __TIM_HandleTypeDef::Base_MspInitCallback, __TIM_HandleTypeDef::Break2Callback, __TIM_HandleTypeDef::BreakCallback, __TIM_HandleTypeDef::CommutationCallback, __TIM_HandleTypeDef::CommutationHalfCpltCallback, __TIM_HandleTypeDef::Encoder_MspDeInitCallback, __TIM_HandleTypeDef::Encoder_MspInitCallback, __TIM_HandleTypeDef::ErrorCallback, HAL_TIM_BASE_MSPDEINIT_CB_ID, HAL_TIM_BASE_MSPINIT_CB_ID, HAL_TIM_BREAK2_CB_ID, HAL_TIM_BREAK_CB_ID, HAL_TIM_COMMUTATION_CB_ID, HAL_TIM_COMMUTATION_HALF_CB_ID, HAL_TIM_ENCODER_MSPDEINIT_CB_ID, HAL_TIM_ENCODER_MSPINIT_CB_ID, HAL_TIM_ERROR_CB_ID, HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID, HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID, HAL_TIM_IC_CAPTURE_CB_ID, HAL_TIM_IC_CAPTURE_HALF_CB_ID, HAL_TIM_IC_MSPDEINIT_CB_ID, HAL_TIM_IC_MSPINIT_CB_ID, HAL_TIM_OC_DELAY_ELAPSED_CB_ID, HAL_TIM_OC_MSPDEINIT_CB_ID, HAL_TIM_OC_MSPINIT_CB_ID, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID, HAL_TIM_ONE_PULSE_MSPINIT_CB_ID, HAL_TIM_PERIOD_ELAPSED_CB_ID, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID, HAL_TIM_PWM_MSPDEINIT_CB_ID, HAL_TIM_PWM_MSPINIT_CB_ID, HAL_TIM_PWM_PULSE_FINISHED_CB_ID, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, HAL_TIM_TRIGGER_CB_ID, HAL_TIM_TRIGGER_HALF_CB_ID, __TIM_HandleTypeDef::HallSensor_MspDeInitCallback, __TIM_HandleTypeDef::HallSensor_MspInitCallback, __TIM_HandleTypeDef::IC_CaptureCallback, __TIM_HandleTypeDef::IC_CaptureHalfCpltCallback, __TIM_HandleTypeDef::IC_MspDeInitCallback, __TIM_HandleTypeDef::IC_MspInitCallback, __TIM_HandleTypeDef::OC_DelayElapsedCallback, __TIM_HandleTypeDef::OC_MspDeInitCallback, __TIM_HandleTypeDef::OC_MspInitCallback, __TIM_HandleTypeDef::OnePulse_MspDeInitCallback, __TIM_HandleTypeDef::OnePulse_MspInitCallback, __TIM_HandleTypeDef::PeriodElapsedCallback, __TIM_HandleTypeDef::PeriodElapsedHalfCpltCallback, __TIM_HandleTypeDef::PWM_MspDeInitCallback, __TIM_HandleTypeDef::PWM_MspInitCallback, __TIM_HandleTypeDef::PWM_PulseFinishedCallback, __TIM_HandleTypeDef::PWM_PulseFinishedHalfCpltCallback, __TIM_HandleTypeDef::State, __TIM_HandleTypeDef::TriggerCallback, and __TIM_HandleTypeDef::TriggerHalfCpltCallback.

void HAL_TIM_TriggerCallback ( TIM_HandleTypeDef * htim )

Hall Trigger detection callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 5089 of file stm32wbxx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_UnRegisterCallback(), TIM_DMATriggerCplt(), and TIM_ResetCallback().

void HAL_TIM_TriggerHalfCpltCallback ( TIM_HandleTypeDef * htim )

Hall Trigger detection half complete callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 5104 of file stm32wbxx_hal_tim.c.

Referenced by HAL_TIM_UnRegisterCallback(), TIM_DMATriggerHalfCplt(), and TIM_ResetCallback().

HAL_StatusTypeDef HAL_TIM_UnRegisterCallback | ( | TIM_HandleTypeDef * | htim,
 |  | HAL_TIM_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a TIM callback TIM callback is redirected to the weak predefined callback.

Parameters:
htim tim handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
  • HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
  • HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
  • HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
  • HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
  • HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
  • HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
  • HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
  • HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
  • HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
  • HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
  • HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
  • HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
  • HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
  • HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
  • HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
  • HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
  • HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
  • HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
  • HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
  • HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
  • HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
  • HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
  • HAL_TIM_ERROR_CB_ID Error Callback ID
  • HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
  • HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
  • HAL_TIM_BREAK_CB_ID Break Callback ID
  • HAL_TIM_BREAK2_CB_ID Break2 Callback ID
Return values:
status

Definition at line 5414 of file stm32wbxx_hal_tim.c.

References __TIM_HandleTypeDef::Base_MspDeInitCallback, __TIM_HandleTypeDef::Base_MspInitCallback, __TIM_HandleTypeDef::Break2Callback, __TIM_HandleTypeDef::BreakCallback, __TIM_HandleTypeDef::CommutationCallback, __TIM_HandleTypeDef::CommutationHalfCpltCallback, __TIM_HandleTypeDef::Encoder_MspDeInitCallback, __TIM_HandleTypeDef::Encoder_MspInitCallback, __TIM_HandleTypeDef::ErrorCallback, HAL_TIM_Base_MspDeInit(), HAL_TIM_BASE_MSPDEINIT_CB_ID, HAL_TIM_Base_MspInit(), HAL_TIM_BASE_MSPINIT_CB_ID, HAL_TIM_BREAK2_CB_ID, HAL_TIM_BREAK_CB_ID, HAL_TIM_COMMUTATION_CB_ID, HAL_TIM_COMMUTATION_HALF_CB_ID, HAL_TIM_Encoder_MspDeInit(), HAL_TIM_ENCODER_MSPDEINIT_CB_ID, HAL_TIM_Encoder_MspInit(), HAL_TIM_ENCODER_MSPINIT_CB_ID, HAL_TIM_ERROR_CB_ID, HAL_TIM_ErrorCallback(), HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID, HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID, HAL_TIM_IC_CAPTURE_CB_ID, HAL_TIM_IC_CAPTURE_HALF_CB_ID, HAL_TIM_IC_CaptureCallback(), HAL_TIM_IC_CaptureHalfCpltCallback(), HAL_TIM_IC_MspDeInit(), HAL_TIM_IC_MSPDEINIT_CB_ID, HAL_TIM_IC_MspInit(), HAL_TIM_IC_MSPINIT_CB_ID, HAL_TIM_OC_DELAY_ELAPSED_CB_ID, HAL_TIM_OC_DelayElapsedCallback(), HAL_TIM_OC_MspDeInit(), HAL_TIM_OC_MSPDEINIT_CB_ID, HAL_TIM_OC_MspInit(), HAL_TIM_OC_MSPINIT_CB_ID, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID, HAL_TIM_ONE_PULSE_MSPINIT_CB_ID, HAL_TIM_OnePulse_MspDeInit(), HAL_TIM_OnePulse_MspInit(), HAL_TIM_PERIOD_ELAPSED_CB_ID, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID, HAL_TIM_PeriodElapsedCallback(), HAL_TIM_PeriodElapsedHalfCpltCallback(), HAL_TIM_PWM_MspDeInit(), HAL_TIM_PWM_MSPDEINIT_CB_ID, HAL_TIM_PWM_MspInit(), HAL_TIM_PWM_MSPINIT_CB_ID, HAL_TIM_PWM_PULSE_FINISHED_CB_ID, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID, HAL_TIM_PWM_PulseFinishedCallback(), HAL_TIM_PWM_PulseFinishedHalfCpltCallback(), HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, HAL_TIM_TRIGGER_CB_ID, HAL_TIM_TRIGGER_HALF_CB_ID, HAL_TIM_TriggerCallback(), HAL_TIM_TriggerHalfCpltCallback(), HAL_TIMEx_Break2Callback(), HAL_TIMEx_BreakCallback(), HAL_TIMEx_CommutCallback(), HAL_TIMEx_CommutHalfCpltCallback(), HAL_TIMEx_HallSensor_MspDeInit(), HAL_TIMEx_HallSensor_MspInit(), __TIM_HandleTypeDef::HallSensor_MspDeInitCallback, __TIM_HandleTypeDef::HallSensor_MspInitCallback, __TIM_HandleTypeDef::IC_CaptureCallback, __TIM_HandleTypeDef::IC_CaptureHalfCpltCallback, __TIM_HandleTypeDef::IC_MspDeInitCallback, __TIM_HandleTypeDef::IC_MspInitCallback, __TIM_HandleTypeDef::OC_DelayElapsedCallback, __TIM_HandleTypeDef::OC_MspDeInitCallback, __TIM_HandleTypeDef::OC_MspInitCallback, __TIM_HandleTypeDef::OnePulse_MspDeInitCallback, __TIM_HandleTypeDef::OnePulse_MspInitCallback, __TIM_HandleTypeDef::PeriodElapsedCallback, __TIM_HandleTypeDef::PeriodElapsedHalfCpltCallback, __TIM_HandleTypeDef::PWM_MspDeInitCallback, __TIM_HandleTypeDef::PWM_MspInitCallback, __TIM_HandleTypeDef::PWM_PulseFinishedCallback, __TIM_HandleTypeDef::PWM_PulseFinishedHalfCpltCallback, __TIM_HandleTypeDef::State, __TIM_HandleTypeDef::TriggerCallback, and __TIM_HandleTypeDef::TriggerHalfCpltCallback.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM Peripheral State functions

Functions
TIM Peripheral State functions
TIM Exported Functions

TIM Peripheral State functions. More...

Functions

HAL_TIM_StateTypeDef | HAL_TIM_Base_GetState (TIM_HandleTypeDef *htim)
Return the TIM Base handle state.
HAL_TIM_StateTypeDef | HAL_TIM_OC_GetState (TIM_HandleTypeDef *htim)
Return the TIM OC handle state.
HAL_TIM_StateTypeDef | HAL_TIM_PWM_GetState (TIM_HandleTypeDef *htim)
Return the TIM PWM handle state.
HAL_TIM_StateTypeDef | HAL_TIM_IC_GetState (TIM_HandleTypeDef *htim)
Return the TIM Input Capture handle state.
HAL_TIM_StateTypeDef | HAL_TIM_OnePulse_GetState (TIM_HandleTypeDef *htim)
Return the TIM One Pulse Mode handle state.
HAL_TIM_StateTypeDef | HAL_TIM_Encoder_GetState (TIM_HandleTypeDef *htim)
Return the TIM Encoder Mode handle state.

Detailed Description

TIM Peripheral State functions.

Peripheral State functions.

  ==============================================================================
                        ##### Peripheral State functions #####
  ==============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

HAL_TIM_StateTypeDef HAL_TIM_Base_GetState ( TIM_HandleTypeDef * htim )

Return the TIM Base handle state.

Parameters:
htim TIM Base handle
Return values:
HAL state

Definition at line 5646 of file stm32wbxx_hal_tim.c.

References __TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState ( TIM_HandleTypeDef * htim )

Return the TIM Encoder Mode handle state.

Parameters:
htim TIM Encoder Interface handle
Return values:
HAL state

Definition at line 5696 of file stm32wbxx_hal_tim.c.

References __TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_IC_GetState ( TIM_HandleTypeDef * htim )

Return the TIM Input Capture handle state.

Parameters:
htim TIM IC handle
Return values:
HAL state

Definition at line 5676 of file stm32wbxx_hal_tim.c.

References __TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_OC_GetState ( TIM_HandleTypeDef * htim )

Return the TIM OC handle state.

Parameters:
htim TIM Output Compare handle
Return values:
HAL state

Definition at line 5656 of file stm32wbxx_hal_tim.c.

References __TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState ( TIM_HandleTypeDef * htim )

Return the TIM One Pulse Mode handle state.

Parameters:
htim TIM OPM handle
Return values:
HAL state

Definition at line 5686 of file stm32wbxx_hal_tim.c.

References __TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState ( TIM_HandleTypeDef * htim )

Return the TIM PWM handle state.

Parameters:
htim TIM handle
Return values:
HAL state

Definition at line 5666 of file stm32wbxx_hal_tim.c.

References __TIM_HandleTypeDef::State.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM Private Functions

Functions
TIM Private Functions
TIM

Functions

static void | TIM_OC1_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 1 configuration.
static void | TIM_OC3_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 3 configuration.
static void | TIM_OC4_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 4 configuration.
static void | TIM_OC5_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 5 configuration.
static void | TIM_OC6_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 6 configuration.
static void | TIM_TI1_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI1.
static void | TIM_TI2_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI2 as Input.
static void | TIM_TI2_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI2.
static void | TIM_TI3_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI3 as Input.
static void | TIM_TI4_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI4 as Input.
static void | TIM_ITRx_SetConfig (TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
Selects the Input Trigger source.
static void | TIM_DMAPeriodElapsedCplt (DMA_HandleTypeDef *hdma)
TIM DMA Period Elapse complete callback.
static void | TIM_DMAPeriodElapsedHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Period Elapse half complete callback.
static void | TIM_DMATriggerCplt (DMA_HandleTypeDef *hdma)
TIM DMA Trigger callback.
static void | TIM_DMATriggerHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Trigger half complete callback.
static HAL_StatusTypeDef | TIM_SlaveTimer_SetConfig (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Slave Timer configuration function.
void | TIM_DMAError (DMA_HandleTypeDef *hdma)
TIM DMA error callback.
void | TIM_DMADelayPulseCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse complete callback.
void | TIM_DMADelayPulseHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse half complete callback.
void | TIM_DMACaptureCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture complete callback.
void | TIM_DMACaptureHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture half complete callback.
void | TIM_Base_SetConfig (TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
Time Base configuration.
void | TIM_OC2_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 2 configuration.
void | TIM_TI1_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI1 as Input.
void | TIM_ETR_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
void | TIM_CCxChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
Enables or disables the TIM Capture Compare Channel x.
void | TIM_ResetCallback (TIM_HandleTypeDef *htim)
Reset interrupt callbacks to the legacy weak callbacks.

Function Documentation

void TIM_Base_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_Base_InitTypeDef * | Structure
 | ) |  |

Time Base configuration.

Parameters:
TIMx | TIM peripheral
Structure | TIM Base configuration structure
Return values:
None

Definition at line 5973 of file stm32wbxx_hal_tim.c.

References TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, TIM_Base_InitTypeDef::Period, TIM_Base_InitTypeDef::Prescaler, and TIM_Base_InitTypeDef::RepetitionCounter.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

void TIM_CCxChannelCmd | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ChannelState
 | ) |  |

Enables or disables the TIM Capture Compare Channel x.

Parameters:
TIMx | to select the TIM peripheral
Channel specifies the TIM Channel This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1
  • TIM_CHANNEL_2: TIM Channel 2
  • TIM_CHANNEL_3: TIM Channel 3
  • TIM_CHANNEL_4: TIM Channel 4
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
ChannelState | specifies the TIM Channel CCxE bit new state. This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
Return values:
None

Definition at line 6870 of file stm32wbxx_hal_tim.c.

References assert_param, and IS_TIM_CHANNELS.

Referenced by HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), and HAL_TIMEx_HallSensor_Stop_IT().

void TIM_DMACaptureCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Capture complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 5818 of file stm32wbxx_hal_tim.c.

References __TIM_HandleTypeDef::Channel, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_IC_CaptureCallback(), HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::IC_CaptureCallback, __TIM_HandleTypeDef::State, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), and HAL_TIMEx_HallSensor_Start_DMA().

void TIM_DMACaptureHalfCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Capture half complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 5859 of file stm32wbxx_hal_tim.c.

References __TIM_HandleTypeDef::Channel, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_IC_CaptureHalfCpltCallback(), HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::IC_CaptureHalfCpltCallback, __TIM_HandleTypeDef::State, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), and HAL_TIMEx_HallSensor_Start_DMA().

void TIM_DMADelayPulseCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Delay Pulse complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 5736 of file stm32wbxx_hal_tim.c.

References __TIM_HandleTypeDef::Channel, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_PWM_PulseFinishedCallback(), HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::PWM_PulseFinishedCallback, __TIM_HandleTypeDef::State, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIM_DMABurst_WriteStart(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

void TIM_DMADelayPulseHalfCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Delay Pulse half complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 5777 of file stm32wbxx_hal_tim.c.

References __TIM_HandleTypeDef::Channel, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_PWM_PulseFinishedHalfCpltCallback(), HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::PWM_PulseFinishedHalfCpltCallback, __TIM_HandleTypeDef::State, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIM_DMABurst_WriteStart(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

void TIM_DMAError ( DMA_HandleTypeDef * hdma )

TIM DMA error callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 5718 of file stm32wbxx_hal_tim.c.

References __TIM_HandleTypeDef::ErrorCallback, HAL_TIM_ErrorCallback(), HAL_TIM_STATE_READY, and __TIM_HandleTypeDef::State.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

static void TIM_DMAPeriodElapsedCplt ( DMA_HandleTypeDef * hdma ) [static]

TIM DMA Period Elapse complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 5900 of file stm32wbxx_hal_tim.c.

References HAL_TIM_PeriodElapsedCallback(), HAL_TIM_STATE_READY, __TIM_HandleTypeDef::PeriodElapsedCallback, and __TIM_HandleTypeDef::State.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), and HAL_TIM_DMABurst_WriteStart().

static void TIM_DMAPeriodElapsedHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

TIM DMA Period Elapse half complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 5918 of file stm32wbxx_hal_tim.c.

References HAL_TIM_PeriodElapsedHalfCpltCallback(), HAL_TIM_STATE_READY, __TIM_HandleTypeDef::PeriodElapsedHalfCpltCallback, and __TIM_HandleTypeDef::State.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), and HAL_TIM_DMABurst_WriteStart().

static void TIM_DMATriggerCplt ( DMA_HandleTypeDef * hdma ) [static]

TIM DMA Trigger callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 5936 of file stm32wbxx_hal_tim.c.

References HAL_TIM_STATE_READY, HAL_TIM_TriggerCallback(), __TIM_HandleTypeDef::State, and __TIM_HandleTypeDef::TriggerCallback.

Referenced by HAL_TIM_DMABurst_ReadStart(), and HAL_TIM_DMABurst_WriteStart().

static void TIM_DMATriggerHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

TIM DMA Trigger half complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 5954 of file stm32wbxx_hal_tim.c.

References HAL_TIM_STATE_READY, HAL_TIM_TriggerHalfCpltCallback(), __TIM_HandleTypeDef::State, and __TIM_HandleTypeDef::TriggerHalfCpltCallback.

Referenced by HAL_TIM_DMABurst_ReadStart(), and HAL_TIM_DMABurst_WriteStart().

void TIM_ETR_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ExtTRGPrescaler,
 |  | uint32_t | TIM_ExtTRGPolarity,
 |  | uint32_t | ExtTRGFilter
 | ) |  |

Configures the TIMx External Trigger (ETR).

Parameters:
TIMx | to select the TIM peripheral
TIM_ExtTRGPrescaler The external Trigger Prescaler. This parameter can be one of the following values:
  • TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
  • TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
  • TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
  • TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
TIM_ExtTRGPolarity The external Trigger Polarity. This parameter can be one of the following values:
  • TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
  • TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
ExtTRGFilter | External Trigger Filter. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 6838 of file stm32wbxx_hal_tim.c.

Referenced by HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), and TIM_SlaveTimer_SetConfig().

static void TIM_ITRx_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | InputTriggerSource
 | ) |  | [static]

Selects the Input Trigger source.

Parameters:
TIMx to select the TIM peripheral
InputTriggerSource The Input Trigger source. This parameter can be one of the following values:
  • TIM_TS_ITR0: Internal Trigger 0
  • TIM_TS_ITR1: Internal Trigger 1
  • TIM_TS_ITR2: Internal Trigger 2
  • TIM_TS_ITR3: Internal Trigger 3
  • TIM_TS_TI1F_ED: TI1 Edge Detector
  • TIM_TS_TI1FP1: Filtered Timer Input 1
  • TIM_TS_TI2FP2: Filtered Timer Input 2
  • TIM_TS_ETRF: External Trigger input
Return values:
None

Definition at line 6808 of file stm32wbxx_hal_tim.c.

References TIM_SLAVEMODE_EXTERNAL1.

Referenced by HAL_TIM_ConfigClockSource().

static void TIM_OC1_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  | [static]

Timer Output Compare 1 configuration.

Parameters:
TIMx | to select the TIM peripheral
OC_Config | The ouput configuration structure
Return values:
None

Definition at line 6021 of file stm32wbxx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, IS_TIM_OCN_POLARITY, IS_TIM_OCNIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, and TIM_CHANNEL_1.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

void TIM_OC2_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  |

Timer Output Compare 2 configuration.

Parameters:
TIMx | to select the TIM peripheral
OC_Config | The ouput configuration structure
Return values:
None

Definition at line 6096 of file stm32wbxx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, IS_TIM_OCN_POLARITY, IS_TIM_OCNIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, and TIM_CHANNEL_2.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

static void TIM_OC3_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  | [static]

Timer Output Compare 3 configuration.

Parameters:
TIMx | to select the TIM peripheral
OC_Config | The ouput configuration structure
Return values:
None

Definition at line 6172 of file stm32wbxx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, IS_TIM_OCN_POLARITY, IS_TIM_OCNIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, and TIM_CHANNEL_3.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

static void TIM_OC4_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  | [static]

Timer Output Compare 4 configuration.

Parameters:
TIMx | to select the TIM peripheral
OC_Config | The ouput configuration structure
Return values:
None

Definition at line 6246 of file stm32wbxx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, and TIM_OC_InitTypeDef::Pulse.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

static void TIM_OC5_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  | [static]

Timer Output Compare 5 configuration.

Parameters:
TIMx | to select the TIM peripheral
OC_Config | The ouput configuration structure
Return values:
None

Definition at line 6306 of file stm32wbxx_hal_tim.c.

References TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, and TIM_OC_InitTypeDef::Pulse.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

static void TIM_OC6_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  | [static]

Timer Output Compare 6 configuration.

Parameters:
TIMx | to select the TIM peripheral
OC_Config | The ouput configuration structure
Return values:
None

Definition at line 6359 of file stm32wbxx_hal_tim.c.

References TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, and TIM_OC_InitTypeDef::Pulse.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

void TIM_ResetCallback ( TIM_HandleTypeDef * htim )

Reset interrupt callbacks to the legacy weak callbacks.

Parameters:
htim pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
Return values:
None

Definition at line 6894 of file stm32wbxx_hal_tim.c.

References __TIM_HandleTypeDef::Break2Callback, __TIM_HandleTypeDef::BreakCallback, __TIM_HandleTypeDef::CommutationCallback, __TIM_HandleTypeDef::CommutationHalfCpltCallback, __TIM_HandleTypeDef::ErrorCallback, HAL_TIM_ErrorCallback(), HAL_TIM_IC_CaptureCallback(), HAL_TIM_IC_CaptureHalfCpltCallback(), HAL_TIM_OC_DelayElapsedCallback(), HAL_TIM_PeriodElapsedCallback(), HAL_TIM_PeriodElapsedHalfCpltCallback(), HAL_TIM_PWM_PulseFinishedCallback(), HAL_TIM_PWM_PulseFinishedHalfCpltCallback(), HAL_TIM_TriggerCallback(), HAL_TIM_TriggerHalfCpltCallback(), HAL_TIMEx_Break2Callback(), HAL_TIMEx_BreakCallback(), HAL_TIMEx_CommutCallback(), HAL_TIMEx_CommutHalfCpltCallback(), __TIM_HandleTypeDef::IC_CaptureCallback, __TIM_HandleTypeDef::IC_CaptureHalfCpltCallback, __TIM_HandleTypeDef::OC_DelayElapsedCallback, __TIM_HandleTypeDef::PeriodElapsedCallback, __TIM_HandleTypeDef::PeriodElapsedHalfCpltCallback, __TIM_HandleTypeDef::PWM_PulseFinishedCallback, __TIM_HandleTypeDef::PWM_PulseFinishedHalfCpltCallback, __TIM_HandleTypeDef::TriggerCallback, and __TIM_HandleTypeDef::TriggerHalfCpltCallback.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_SlaveConfigTypeDef * | sSlaveConfig
 | ) |  | [static]

Slave Timer configuration function.

Parameters:
htim | TIM handle
sSlaveConfig | Slave timer configuration
Return values:
None

Definition at line 6413 of file stm32wbxx_hal_tim.c.

References assert_param, TIM_SlaveConfigTypeDef::InputTrigger, __TIM_HandleTypeDef::Instance, IS_TIM_TRIGGERFILTER, IS_TIM_TRIGGERPOLARITY, IS_TIM_TRIGGERPRESCALER, TIM_SlaveConfigTypeDef::SlaveMode, TIM_ETR_SetConfig(), TIM_SLAVEMODE_GATED, TIM_TI1_ConfigInputStage(), TIM_TI2_ConfigInputStage(), TIM_TS_ETRF, TIM_TS_ITR0, TIM_TS_ITR1, TIM_TS_ITR2, TIM_TS_ITR3, TIM_TS_TI1F_ED, TIM_TS_TI1FP1, TIM_TS_TI2FP2, TIM_SlaveConfigTypeDef::TriggerFilter, TIM_SlaveConfigTypeDef::TriggerPolarity, and TIM_SlaveConfigTypeDef::TriggerPrescaler.

Referenced by HAL_TIM_SlaveConfigSynchro(), and HAL_TIM_SlaveConfigSynchro_IT().

static void TIM_TI1_ConfigInputStage | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the Polarity and Filter for TI1.

Parameters:
TIMx | to select the TIM peripheral.
TIM_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPOLARITY_RISING
  • TIM_ICPOLARITY_FALLING
  • TIM_ICPOLARITY_BOTHEDGE
TIM_ICFilter | Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 6591 of file stm32wbxx_hal_tim.c.

Referenced by HAL_TIM_ConfigClockSource(), and TIM_SlaveTimer_SetConfig().

void TIM_TI1_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  |

Configure the TI1 as Input.

Parameters:
TIMx | to select the TIM peripheral.
TIM_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPOLARITY_RISING
  • TIM_ICPOLARITY_FALLING
  • TIM_ICPOLARITY_BOTHEDGE
TIM_ICSelection specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
  • TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
  • TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
TIM_ICFilter | Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 (on channel2 path) is used as the input signal. Therefore CCMR1 must be protected against un-initialized filter and polarity values.

Definition at line 6544 of file stm32wbxx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

static void TIM_TI2_ConfigInputStage | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the Polarity and Filter for TI2.

Parameters:
TIMx | to select the TIM peripheral.
TIM_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPOLARITY_RISING
  • TIM_ICPOLARITY_FALLING
  • TIM_ICPOLARITY_BOTHEDGE
TIM_ICFilter | Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 6674 of file stm32wbxx_hal_tim.c.

Referenced by HAL_TIM_ConfigClockSource(), and TIM_SlaveTimer_SetConfig().

static void TIM_TI2_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the TI2 as Input.

Parameters:
TIMx | to select the TIM peripheral
TIM_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPOLARITY_RISING
  • TIM_ICPOLARITY_FALLING
  • TIM_ICPOLARITY_BOTHEDGE
TIM_ICSelection specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
  • TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
  • TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
TIM_ICFilter | Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 (on channel1 path) is used as the input signal. Therefore CCMR1 must be protected against un-initialized filter and polarity values.

Definition at line 6634 of file stm32wbxx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel(), and HAL_TIM_OnePulse_ConfigChannel().

static void TIM_TI3_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the TI3 as Input.

Parameters:
TIMx | to select the TIM peripheral
TIM_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPOLARITY_RISING
  • TIM_ICPOLARITY_FALLING
  • TIM_ICPOLARITY_BOTHEDGE
TIM_ICSelection specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
  • TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
  • TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
TIM_ICFilter | Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 (on channel1 path) is used as the input signal. Therefore CCMR2 must be protected against un-initialized filter and polarity values.

Definition at line 6717 of file stm32wbxx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel().

static void TIM_TI4_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the TI4 as Input.

Parameters:
TIMx | to select the TIM peripheral
TIM_ICPolarity The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPOLARITY_RISING
  • TIM_ICPOLARITY_FALLING
  • TIM_ICPOLARITY_BOTHEDGE
TIM_ICSelection specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
  • TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
  • TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
TIM_ICFilter | Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 (on channel1 path) is used as the input signal. Therefore CCMR2 must be protected against un-initialized filter and polarity values.
Return values:
None

Definition at line 6765 of file stm32wbxx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel().

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM Exported Types

Data Structures | Typedefs | Enumerations
TIM Exported Types
TIM

Data Structures

struct | TIM_Base_InitTypeDef
TIM Time base Configuration Structure definition. More...
struct | TIM_OC_InitTypeDef
TIM Output Compare Configuration Structure definition. More...
struct | TIM_OnePulse_InitTypeDef
TIM One Pulse Mode Configuration Structure definition. More...
struct | TIM_IC_InitTypeDef
TIM Input Capture Configuration Structure definition. More...
struct | TIM_Encoder_InitTypeDef
TIM Encoder Configuration Structure definition. More...
struct | TIM_ClockConfigTypeDef
Clock Configuration Handle Structure definition. More...
struct | TIM_ClearInputConfigTypeDef
TIM Clear Input Configuration Handle Structure definition. More...
struct | TIM_MasterConfigTypeDef
TIM Master configuration Structure definition. More...
struct | TIM_SlaveConfigTypeDef
TIM Slave configuration Structure definition. More...
struct | TIM_BreakDeadTimeConfigTypeDef
TIM Break input(s) and Dead time configuration Structure definition. More...
struct | __TIM_HandleTypeDef
TIM Time Base Handle Structure definition. More...

Typedefs

typedef struct __TIM_HandleTypeDef | TIM_HandleTypeDef
TIM Time Base Handle Structure definition.
typedef void(* | pTIM_CallbackTypeDef )(TIM_HandleTypeDef *htim)
HAL TIM Callback pointer definition.

Enumerations

enum HAL_TIM_StateTypeDef {
HAL_TIM_STATE_RESET = 0x00U, HAL_TIM_STATE_READY = 0x01U, HAL_TIM_STATE_BUSY = 0x02U, HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04U
}
HAL State structures definition. More...
enum HAL_TIM_ActiveChannel {
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U
}
HAL Active channel structures definition. More...
enum HAL_TIM_CallbackIDTypeDef {
HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U, HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U, HAL_TIM_IC_MSPINIT_CB_ID = 0x02U, HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U,
HAL_TIM_OC_MSPINIT_CB_ID = 0x04U, HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U, HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U, HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U,
HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U, HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU, HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU,
HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU, HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU, HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU,
HAL_TIM_TRIGGER_CB_ID = 0x10U, HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U, HAL_TIM_IC_CAPTURE_CB_ID = 0x12U, HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U,
HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U, HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U, HAL_TIM_ERROR_CB_ID = 0x17U,
HAL_TIM_COMMUTATION_CB_ID = 0x18U, HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U, HAL_TIM_BREAK_CB_ID = 0x1AU, HAL_TIM_BREAK2_CB_ID = 0x1BU
}
HAL TIM Callback ID enumeration definition. More...

Typedef Documentation

typedef void(* pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim)

HAL TIM Callback pointer definition.

pointer to the TIM callback function

Definition at line 410 of file stm32wbxx_hal_tim.h.

typedef struct __TIM_HandleTypeDef TIM_HandleTypeDef

TIM Time Base Handle Structure definition.

Enumeration Type Documentation

enum HAL_TIM_ActiveChannel

HAL Active channel structures definition.

Enumerator:
HAL_TIM_ACTIVE_CHANNEL_1

The active channel is 1

HAL_TIM_ACTIVE_CHANNEL_2

The active channel is 2

HAL_TIM_ACTIVE_CHANNEL_3

The active channel is 3

HAL_TIM_ACTIVE_CHANNEL_4

The active channel is 4

HAL_TIM_ACTIVE_CHANNEL_5

The active channel is 5

HAL_TIM_ACTIVE_CHANNEL_6

The active channel is 6

HAL_TIM_ACTIVE_CHANNEL_CLEARED

All active channels cleared

Definition at line 310 of file stm32wbxx_hal_tim.h.

enum HAL_TIM_CallbackIDTypeDef

HAL TIM Callback ID enumeration definition.

Enumerator:
HAL_TIM_BASE_MSPINIT_CB_ID

TIM Base MspInit Callback ID

HAL_TIM_BASE_MSPDEINIT_CB_ID

TIM Base MspDeInit Callback ID

HAL_TIM_IC_MSPINIT_CB_ID

TIM IC MspInit Callback ID

HAL_TIM_IC_MSPDEINIT_CB_ID

TIM IC MspDeInit Callback ID

HAL_TIM_OC_MSPINIT_CB_ID

TIM OC MspInit Callback ID

HAL_TIM_OC_MSPDEINIT_CB_ID

TIM OC MspDeInit Callback ID

HAL_TIM_PWM_MSPINIT_CB_ID

TIM PWM MspInit Callback ID

HAL_TIM_PWM_MSPDEINIT_CB_ID

TIM PWM MspDeInit Callback ID

HAL_TIM_ONE_PULSE_MSPINIT_CB_ID

TIM One Pulse MspInit Callback ID

HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID

TIM One Pulse MspDeInit Callback ID

HAL_TIM_ENCODER_MSPINIT_CB_ID

TIM Encoder MspInit Callback ID

HAL_TIM_ENCODER_MSPDEINIT_CB_ID

TIM Encoder MspDeInit Callback ID

HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID

TIM Hall Sensor MspDeInit Callback ID

HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID

TIM Hall Sensor MspDeInit Callback ID

HAL_TIM_PERIOD_ELAPSED_CB_ID

TIM Period Elapsed Callback ID

HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID

TIM Period Elapsed half complete Callback ID

HAL_TIM_TRIGGER_CB_ID

TIM Trigger Callback ID

HAL_TIM_TRIGGER_HALF_CB_ID

TIM Trigger half complete Callback ID

HAL_TIM_IC_CAPTURE_CB_ID

TIM Input Capture Callback ID

HAL_TIM_IC_CAPTURE_HALF_CB_ID

TIM Input Capture half complete Callback ID

HAL_TIM_OC_DELAY_ELAPSED_CB_ID

TIM Output Compare Delay Elapsed Callback ID

HAL_TIM_PWM_PULSE_FINISHED_CB_ID

TIM PWM Pulse Finished Callback ID

HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID

TIM PWM Pulse Finished half complete Callback ID

HAL_TIM_ERROR_CB_ID

TIM Error Callback ID

HAL_TIM_COMMUTATION_CB_ID

TIM Commutation Callback ID

HAL_TIM_COMMUTATION_HALF_CB_ID

TIM Commutation half complete Callback ID

HAL_TIM_BREAK_CB_ID

TIM Break Callback ID

HAL_TIM_BREAK2_CB_ID

TIM Break2 Callback ID

Definition at line 374 of file stm32wbxx_hal_tim.h.

enum HAL_TIM_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_TIM_STATE_RESET

Peripheral not yet initialized or disabled

HAL_TIM_STATE_READY

Peripheral Initialized and ready for use

HAL_TIM_STATE_BUSY

An internal process is ongoing

HAL_TIM_STATE_TIMEOUT

Timeout state

HAL_TIM_STATE_ERROR

Reception process is ongoing

Definition at line 298 of file stm32wbxx_hal_tim.h.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM_Base_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_Base_InitTypeDef Struct Reference
TIM Exported Types

TIM Time base Configuration Structure definition. More...

#include <stm32wbxx_hal_tim.h>

Data Fields

uint32_t | Prescaler
uint32_t | CounterMode
uint32_t | Period
uint32_t | ClockDivision
uint32_t | RepetitionCounter
uint32_t | AutoReloadPreload

Detailed Description

TIM Time base Configuration Structure definition.

Definition at line 47 of file stm32wbxx_hal_tim.h.

Field Documentation

uint32_t TIM_Base_InitTypeDef::AutoReloadPreload

Specifies the auto-reload preload. This parameter can be a value of TIM Auto-Reload Preload

Definition at line 71 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), HAL_TIMEx_HallSensor_Init(), and TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::ClockDivision

Specifies the clock division. This parameter can be a value of TIM Clock Division

Definition at line 59 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), HAL_TIMEx_HallSensor_Init(), and TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::CounterMode

Specifies the counter mode. This parameter can be a value of TIM Counter Mode

Definition at line 52 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), HAL_TIMEx_HallSensor_Init(), and TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::Period

Specifies the period value to be loaded into the active Auto-Reload Register at the next update event. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.

Definition at line 55 of file stm32wbxx_hal_tim.h.

Referenced by TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::Prescaler

Specifies the prescaler value used to divide the TIM clock. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 49 of file stm32wbxx_hal_tim.h.

Referenced by TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::RepetitionCounter

Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts from the RCR value (N). This means in PWM mode that (N+1) corresponds to:

  • the number of PWM periods in edge-aligned mode
  • the number of half PWM period in center-aligned mode GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.

Definition at line 62 of file stm32wbxx_hal_tim.h.

Referenced by TIM_Base_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_tim.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM_OC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_OC_InitTypeDef Struct Reference
TIM Exported Types

TIM Output Compare Configuration Structure definition. More...

#include <stm32wbxx_hal_tim.h>

Data Fields

uint32_t | OCMode
uint32_t | Pulse
uint32_t | OCPolarity
uint32_t | OCNPolarity
uint32_t | OCFastMode
uint32_t | OCIdleState
uint32_t | OCNIdleState

Detailed Description

TIM Output Compare Configuration Structure definition.

Definition at line 78 of file stm32wbxx_hal_tim.h.

Field Documentation

uint32_t TIM_OC_InitTypeDef::OCFastMode

Specifies the Fast mode state. This parameter can be a value of TIM Output Fast State

Note:
This parameter is valid only in PWM1 and PWM2 mode.

Definition at line 93 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_PWM_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

uint32_t TIM_OC_InitTypeDef::OCIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Output Compare Idle State

Note:
This parameter is valid only for timer instances supporting break feature.

Definition at line 98 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCMode

Specifies the TIM mode. This parameter can be a value of TIM Output Compare and PWM Modes

Definition at line 80 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCNIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Complementary Output Compare Idle State

Note:
This parameter is valid only for timer instances supporting break feature.

Definition at line 102 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), and TIM_OC3_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCNPolarity

Specifies the complementary output polarity. This parameter can be a value of TIM Complementary Output Compare Polarity

Note:
This parameter is valid only for timer instances supporting break feature.

Definition at line 89 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), and TIM_OC3_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCPolarity

Specifies the output polarity. This parameter can be a value of TIM Output Compare Polarity

Definition at line 86 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

uint32_t TIM_OC_InitTypeDef::Pulse

Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 83 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_OC5_SetConfig(), and TIM_OC6_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_tim.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM_OnePulse_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_OnePulse_InitTypeDef Struct Reference
TIM Exported Types

TIM One Pulse Mode Configuration Structure definition. More...

#include <stm32wbxx_hal_tim.h>

Data Fields

uint32_t | OCMode
uint32_t | Pulse
uint32_t | OCPolarity
uint32_t | OCNPolarity
uint32_t | OCIdleState
uint32_t | OCNIdleState
uint32_t | ICPolarity
uint32_t | ICSelection
uint32_t | ICFilter

Detailed Description

TIM One Pulse Mode Configuration Structure definition.

Definition at line 110 of file stm32wbxx_hal_tim.h.

Field Documentation

uint32_t TIM_OnePulse_InitTypeDef::ICFilter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 139 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::ICPolarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 133 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::ICSelection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 136 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Output Compare Idle State

Note:
This parameter is valid only for timer instances supporting break feature.

Definition at line 125 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCMode

Specifies the TIM mode. This parameter can be a value of TIM Output Compare and PWM Modes

Definition at line 112 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCNIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Complementary Output Compare Idle State

Note:
This parameter is valid only for timer instances supporting break feature.

Definition at line 129 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCNPolarity

Specifies the complementary output polarity. This parameter can be a value of TIM Complementary Output Compare Polarity

Note:
This parameter is valid only for timer instances supporting break feature.

Definition at line 121 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCPolarity

Specifies the output polarity. This parameter can be a value of TIM Output Compare Polarity

Definition at line 118 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::Pulse

Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 115 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_tim.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM_IC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_IC_InitTypeDef Struct Reference
TIM Exported Types

TIM Input Capture Configuration Structure definition. More...

#include <stm32wbxx_hal_tim.h>

Data Fields

uint32_t | ICPolarity
uint32_t | ICSelection
uint32_t | ICPrescaler
uint32_t | ICFilter

Detailed Description

TIM Input Capture Configuration Structure definition.

Definition at line 146 of file stm32wbxx_hal_tim.h.

Field Documentation

uint32_t TIM_IC_InitTypeDef::ICFilter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 157 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

uint32_t TIM_IC_InitTypeDef::ICPolarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 148 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

uint32_t TIM_IC_InitTypeDef::ICPrescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 154 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

uint32_t TIM_IC_InitTypeDef::ICSelection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 151 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_tim.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM_Encoder_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_Encoder_InitTypeDef Struct Reference
TIM Exported Types

TIM Encoder Configuration Structure definition. More...

#include <stm32wbxx_hal_tim.h>

Data Fields

uint32_t | EncoderMode
uint32_t | IC1Polarity
uint32_t | IC1Selection
uint32_t | IC1Prescaler
uint32_t | IC1Filter
uint32_t | IC2Polarity
uint32_t | IC2Selection
uint32_t | IC2Prescaler
uint32_t | IC2Filter

Detailed Description

TIM Encoder Configuration Structure definition.

Definition at line 164 of file stm32wbxx_hal_tim.h.

Field Documentation

uint32_t TIM_Encoder_InitTypeDef::EncoderMode

Specifies the active edge of the input signal. This parameter can be a value of TIM Encoder Mode

Definition at line 166 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Filter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 178 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Polarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Encoder Input Polarity

Definition at line 169 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Prescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 175 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Selection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 172 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Filter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 190 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Polarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Encoder Input Polarity

Definition at line 181 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Prescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 187 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Selection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 184 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_tim.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM_ClockConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_ClockConfigTypeDef Struct Reference
TIM Exported Types

Clock Configuration Handle Structure definition. More...

#include <stm32wbxx_hal_tim.h>

Data Fields

uint32_t | ClockSource
uint32_t | ClockPolarity
uint32_t | ClockPrescaler
uint32_t | ClockFilter

Detailed Description

Clock Configuration Handle Structure definition.

Definition at line 197 of file stm32wbxx_hal_tim.h.

Field Documentation

uint32_t TIM_ClockConfigTypeDef::ClockFilter

TIM clock filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 205 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

uint32_t TIM_ClockConfigTypeDef::ClockPolarity

TIM clock polarity This parameter can be a value of TIM Clock Polarity

Definition at line 201 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

uint32_t TIM_ClockConfigTypeDef::ClockPrescaler

TIM clock prescaler This parameter can be a value of TIM Clock Prescaler

Definition at line 203 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

uint32_t TIM_ClockConfigTypeDef::ClockSource

TIM clock sources This parameter can be a value of TIM Clock Source

Definition at line 199 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_tim.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM_ClearInputConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_ClearInputConfigTypeDef Struct Reference
TIM Exported Types

TIM Clear Input Configuration Handle Structure definition. More...

#include <stm32wbxx_hal_tim.h>

Data Fields

uint32_t | ClearInputState
uint32_t | ClearInputSource
uint32_t | ClearInputPolarity
uint32_t | ClearInputPrescaler
uint32_t | ClearInputFilter

Detailed Description

TIM Clear Input Configuration Handle Structure definition.

Definition at line 212 of file stm32wbxx_hal_tim.h.

Field Documentation

uint32_t TIM_ClearInputConfigTypeDef::ClearInputFilter

TIM Clear Input filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 222 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputPolarity

TIM Clear Input polarity This parameter can be a value of TIM Clear Input Polarity

Definition at line 218 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputPrescaler

TIM Clear Input prescaler This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off

Definition at line 220 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputSource

TIM clear Input sources This parameter can be a value of TIM Clear Input Source

Definition at line 216 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputState

TIM clear Input state This parameter can be ENABLE or DISABLE

Definition at line 214 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_tim.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM_MasterConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_MasterConfigTypeDef Struct Reference
TIM Exported Types

TIM Master configuration Structure definition. More...

#include <stm32wbxx_hal_tim.h>

Data Fields

uint32_t | MasterOutputTrigger
uint32_t | MasterOutputTrigger2
uint32_t | MasterSlaveMode

Detailed Description

TIM Master configuration Structure definition.

Note:
Advanced timers provide TRGO2 internal line which is redirected to the ADC

Definition at line 231 of file stm32wbxx_hal_tim.h.

Field Documentation

uint32_t TIM_MasterConfigTypeDef::MasterOutputTrigger

Trigger output (TRGO) selection This parameter can be a value of TIM Master Mode Selection

Definition at line 233 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

uint32_t TIM_MasterConfigTypeDef::MasterOutputTrigger2

Trigger output2 (TRGO2) selection This parameter can be a value of TIM Master Mode Selection 2 (TRGO2)

Definition at line 235 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

uint32_t TIM_MasterConfigTypeDef::MasterSlaveMode

Master/slave mode selection This parameter can be a value of TIM Master/Slave Mode

Note:
When the Master/slave mode is enabled, the effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is not mandatory in case of timer synchronization mode.

Definition at line 237 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_tim.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM_SlaveConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_SlaveConfigTypeDef Struct Reference
TIM Exported Types

TIM Slave configuration Structure definition. More...

#include <stm32wbxx_hal_tim.h>

Data Fields

uint32_t | SlaveMode
uint32_t | InputTrigger
uint32_t | TriggerPolarity
uint32_t | TriggerPrescaler
uint32_t | TriggerFilter

Detailed Description

TIM Slave configuration Structure definition.

Definition at line 249 of file stm32wbxx_hal_tim.h.

Field Documentation

uint32_t TIM_SlaveConfigTypeDef::InputTrigger

Input Trigger source This parameter can be a value of TIM Trigger Selection

Definition at line 253 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchro(), HAL_TIM_SlaveConfigSynchro_IT(), and TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::SlaveMode

Slave mode selection This parameter can be a value of TIM Slave mode

Definition at line 251 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchro(), HAL_TIM_SlaveConfigSynchro_IT(), and TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::TriggerFilter

Input trigger filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 259 of file stm32wbxx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::TriggerPolarity

Input Trigger polarity This parameter can be a value of TIM Trigger Polarity

Definition at line 255 of file stm32wbxx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::TriggerPrescaler

Input trigger prescaler This parameter can be a value of TIM Trigger Prescaler

Definition at line 257 of file stm32wbxx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_tim.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM_BreakDeadTimeConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_BreakDeadTimeConfigTypeDef Struct Reference
TIM Exported Types

TIM Break input(s) and Dead time configuration Structure definition. More...

#include <stm32wbxx_hal_tim.h>

Data Fields

uint32_t | OffStateRunMode
uint32_t | OffStateIDLEMode
uint32_t | LockLevel
uint32_t | DeadTime
uint32_t | BreakState
uint32_t | BreakPolarity
uint32_t | BreakFilter
uint32_t | Break2State
uint32_t | Break2Polarity
uint32_t | Break2Filter
uint32_t | AutomaticOutput

Detailed Description

TIM Break input(s) and Dead time configuration Structure definition.

Note:
2 break inputs can be configured (BKIN and BKIN2) with configurable filter and polarity.

Definition at line 269 of file stm32wbxx_hal_tim.h.

Field Documentation

uint32_t TIM_BreakDeadTimeConfigTypeDef::AutomaticOutput

TIM Automatic Output Enable state This parameter can be a value of TIM Automatic Output Enable

Definition at line 291 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::Break2Filter

TIM break2 input filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 289 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::Break2Polarity

TIM Break2 input polarity This parameter can be a value of TIM Break Input 2 Polarity

Definition at line 287 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::Break2State

TIM Break2 State This parameter can be a value of TIM Break input 2 Enable

Definition at line 285 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::BreakFilter

Specifies the break input filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 283 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::BreakPolarity

TIM Break input polarity This parameter can be a value of TIM Break Input Polarity

Definition at line 281 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::BreakState

TIM Break State This parameter can be a value of TIM Break Input Enable

Definition at line 279 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::DeadTime

TIM dead Time This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF

Definition at line 277 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::LockLevel

TIM Lock level This parameter can be a value of TIM Lock level

Definition at line 275 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::OffStateIDLEMode

TIM off state in IDLE mode This parameter can be a value of TIM OSSI OffState Selection for Idle mode state

Definition at line 273 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::OffStateRunMode

TIM off state in run mode This parameter can be a value of TIM OSSR OffState Selection for Run mode state

Definition at line 271 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_tim.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: __TIM_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__TIM_HandleTypeDef Struct Reference
TIM Exported Types

TIM Time Base Handle Structure definition. More...

#include <stm32wbxx_hal_tim.h>

Data Fields

TIM_TypeDef * | Instance
TIM_Base_InitTypeDef Init
HAL_TIM_ActiveChannel Channel
DMA_HandleTypeDef * | hdma [7]
HAL_LockTypeDef | Lock
__IO HAL_TIM_StateTypeDef | State
void(* | Base_MspInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | Base_MspDeInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | IC_MspInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | IC_MspDeInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | OC_MspInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | OC_MspDeInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | PWM_MspInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | PWM_MspDeInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | OnePulse_MspInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | OnePulse_MspDeInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | Encoder_MspInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | Encoder_MspDeInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | HallSensor_MspInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | HallSensor_MspDeInitCallback )(struct __TIM_HandleTypeDef *htim)
void(* | PeriodElapsedCallback )(struct __TIM_HandleTypeDef *htim)
void(* | PeriodElapsedHalfCpltCallback )(struct __TIM_HandleTypeDef *htim)
void(* | TriggerCallback )(struct __TIM_HandleTypeDef *htim)
void(* | TriggerHalfCpltCallback )(struct __TIM_HandleTypeDef *htim)
void(* | IC_CaptureCallback )(struct __TIM_HandleTypeDef *htim)
void(* | IC_CaptureHalfCpltCallback )(struct __TIM_HandleTypeDef *htim)
void(* | OC_DelayElapsedCallback )(struct __TIM_HandleTypeDef *htim)
void(* | PWM_PulseFinishedCallback )(struct __TIM_HandleTypeDef *htim)
void(* | PWM_PulseFinishedHalfCpltCallback )(struct __TIM_HandleTypeDef *htim)
void(* | ErrorCallback )(struct __TIM_HandleTypeDef *htim)
void(* | CommutationCallback )(struct __TIM_HandleTypeDef *htim)
void(* | CommutationHalfCpltCallback )(struct __TIM_HandleTypeDef *htim)
void(* | BreakCallback )(struct __TIM_HandleTypeDef *htim)
void(* | Break2Callback )(struct __TIM_HandleTypeDef *htim)

Detailed Description

TIM Time Base Handle Structure definition.

Definition at line 325 of file stm32wbxx_hal_tim.h.

Field Documentation

void(* __TIM_HandleTypeDef::Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM Base Msp DeInit Callback

Definition at line 340 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM Base Msp Init Callback

Definition at line 339 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::Break2Callback)(struct __TIM_HandleTypeDef *htim)

TIM Break2 Callback

Definition at line 366 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), and TIM_ResetCallback().

void(* __TIM_HandleTypeDef::BreakCallback)(struct __TIM_HandleTypeDef *htim)

TIM Break Callback

Definition at line 365 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), and TIM_ResetCallback().

HAL_TIM_ActiveChannel __TIM_HandleTypeDef::Channel

Active channel

Definition at line 332 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMADelayPulseCplt(), and TIM_DMADelayPulseHalfCplt().

void(* __TIM_HandleTypeDef::CommutationCallback)(struct __TIM_HandleTypeDef *htim)

TIM Commutation Callback

Definition at line 363 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_ResetCallback(), and TIMEx_DMACommutationCplt().

void(* __TIM_HandleTypeDef::CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim)

TIM Commutation half complete Callback

Definition at line 364 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_ResetCallback(), and TIMEx_DMACommutationHalfCplt().

void(* __TIM_HandleTypeDef::Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM Encoder Msp DeInit Callback

Definition at line 350 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Encoder_DeInit(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM Encoder Msp Init Callback

Definition at line 349 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::ErrorCallback)(struct __TIM_HandleTypeDef *htim)

TIM Error Callback

Definition at line 362 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_DMAError(), and TIM_ResetCallback().

void(* __TIM_HandleTypeDef::HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM Hall Sensor Msp DeInit Callback

Definition at line 352 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), and HAL_TIMEx_HallSensor_DeInit().

void(* __TIM_HandleTypeDef::HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM Hall Sensor Msp Init Callback

Definition at line 351 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), and HAL_TIMEx_HallSensor_Init().

DMA_HandleTypeDef* __TIM_HandleTypeDef::hdma[7]

DMA Handlers array This array is accessed by a TIM DMA Handle Index

Definition at line 333 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Stop_DMA(), TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMADelayPulseCplt(), TIM_DMADelayPulseHalfCplt(), TIMEx_DMACommutationCplt(), and TIMEx_DMACommutationHalfCplt().

void(* __TIM_HandleTypeDef::IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim)

TIM Input Capture Callback

Definition at line 357 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_DMACaptureCplt(), and TIM_ResetCallback().

void(* __TIM_HandleTypeDef::IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim)

TIM Input Capture half complete Callback

Definition at line 358 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_DMACaptureHalfCplt(), and TIM_ResetCallback().

void(* __TIM_HandleTypeDef::IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM IC Msp DeInit Callback

Definition at line 342 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_IC_DeInit(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM IC Msp Init Callback

Definition at line 341 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_IC_Init(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

TIM_Base_InitTypeDef __TIM_HandleTypeDef::Init

TIM Time Base required parameters

Definition at line 331 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

TIM_TypeDef* __TIM_HandleTypeDef::Instance

Register base address

Definition at line 330 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_Base_Init(), HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_Base_Stop_IT(), HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), HAL_TIM_ConfigTI1Input(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Init(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_GenerateEvent(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_Init(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_Init(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Init(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_Init(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIM_SlaveConfigSynchro(), HAL_TIM_SlaveConfigSynchro_IT(), HAL_TIMEx_ConfigBreakDeadTime(), HAL_TIMEx_ConfigBreakInput(), HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_ConfigCommutEvent_IT(), HAL_TIMEx_GroupChannel5(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_Init(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_MasterConfigSynchronization(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), HAL_TIMEx_RemapConfig(), and TIM_SlaveTimer_SetConfig().

HAL_LockTypeDef __TIM_HandleTypeDef::Lock

Locking object

Definition at line 335 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

void(* __TIM_HandleTypeDef::OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim)

TIM Output Compare Delay Elapsed Callback

Definition at line 359 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), and TIM_ResetCallback().

void(* __TIM_HandleTypeDef::OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM OC Msp DeInit Callback

Definition at line 344 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_OC_DeInit(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM OC Msp Init Callback

Definition at line 343 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_OC_Init(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM One Pulse Msp DeInit Callback

Definition at line 348 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_DeInit(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM One Pulse Msp Init Callback

Definition at line 347 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_Init(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim)

TIM Period Elapsed Callback

Definition at line 353 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_DMAPeriodElapsedCplt(), and TIM_ResetCallback().

void(* __TIM_HandleTypeDef::PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim)

TIM Period Elapsed half complete Callback

Definition at line 354 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_DMAPeriodElapsedHalfCplt(), and TIM_ResetCallback().

void(* __TIM_HandleTypeDef::PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM PWM Msp DeInit Callback

Definition at line 346 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_PWM_DeInit(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim)

TIM PWM Msp Init Callback

Definition at line 345 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_PWM_Init(), HAL_TIM_RegisterCallback(), and HAL_TIM_UnRegisterCallback().

void(* __TIM_HandleTypeDef::PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim)

TIM PWM Pulse Finished Callback

Definition at line 360 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_DMADelayPulseCplt(), and TIM_ResetCallback().

void(* __TIM_HandleTypeDef::PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim)

TIM PWM Pulse Finished half complete Callback

Definition at line 361 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_DMADelayPulseHalfCplt(), and TIM_ResetCallback().

__IO HAL_TIM_StateTypeDef __TIM_HandleTypeDef::State

TIM operation state

Definition at line 336 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_Base_GetState(), HAL_TIM_Base_Init(), HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_GetState(), HAL_TIM_Encoder_Init(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_GenerateEvent(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_GetState(), HAL_TIM_IC_Init(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_GetState(), HAL_TIM_OC_Init(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_GetState(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_GetState(), HAL_TIM_PWM_Init(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_RegisterCallback(), HAL_TIM_SlaveConfigSynchro(), HAL_TIM_SlaveConfigSynchro_IT(), HAL_TIM_UnRegisterCallback(), HAL_TIMEx_GroupChannel5(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_GetState(), HAL_TIMEx_HallSensor_Init(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_MasterConfigSynchronization(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Stop_DMA(), TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMADelayPulseCplt(), TIM_DMADelayPulseHalfCplt(), TIM_DMAError(), TIM_DMAPeriodElapsedCplt(), TIM_DMAPeriodElapsedHalfCplt(), TIM_DMATriggerCplt(), TIM_DMATriggerHalfCplt(), TIMEx_DMACommutationCplt(), and TIMEx_DMACommutationHalfCplt().

void(* __TIM_HandleTypeDef::TriggerCallback)(struct __TIM_HandleTypeDef *htim)

TIM Trigger Callback

Definition at line 355 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_DMATriggerCplt(), and TIM_ResetCallback().

void(* __TIM_HandleTypeDef::TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim)

TIM Trigger half complete Callback

Definition at line 356 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_RegisterCallback(), HAL_TIM_UnRegisterCallback(), TIM_DMATriggerHalfCplt(), and TIM_ResetCallback().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_tim.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM Clear Input Source

Defines
TIM Clear Input Source
TIM Exported Constants

Defines

#define | TIM_CLEARINPUTSOURCE_NONE 0x00000000U
#define | TIM_CLEARINPUTSOURCE_ETR 0x00000001U
#define | TIM_CLEARINPUTSOURCE_COMP1 TIM1_AF1_ETRSEL_0
#define | TIM_CLEARINPUTSOURCE_COMP2 TIM1_AF1_ETRSEL_1

Define Documentation

#define TIM_CLEARINPUTSOURCE_COMP1 TIM1_AF1_ETRSEL_0

OCREF_CLR_INT is connected to COMP1 output

Definition at line 429 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define TIM_CLEARINPUTSOURCE_COMP2 TIM1_AF1_ETRSEL_1

OCREF_CLR_INT is connected to COMP2 output

Definition at line 430 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U

OCREF_CLR is connected to ETRF input

Definition at line 428 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U

OCREF_CLR is disabled

Definition at line 427 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM DMA Base Address

Defines
TIM DMA Base Address
TIM Exported Constants

Defines

#define | TIM_DMABASE_CR1 0x00000000U
#define | TIM_DMABASE_CR2 0x00000001U
#define | TIM_DMABASE_SMCR 0x00000002U
#define | TIM_DMABASE_DIER 0x00000003U
#define | TIM_DMABASE_SR 0x00000004U
#define | TIM_DMABASE_EGR 0x00000005U
#define | TIM_DMABASE_CCMR1 0x00000006U
#define | TIM_DMABASE_CCMR2 0x00000007U
#define | TIM_DMABASE_CCER 0x00000008U
#define | TIM_DMABASE_CNT 0x00000009U
#define | TIM_DMABASE_PSC 0x0000000AU
#define | TIM_DMABASE_ARR 0x0000000BU
#define | TIM_DMABASE_RCR 0x0000000CU
#define | TIM_DMABASE_CCR1 0x0000000DU
#define | TIM_DMABASE_CCR2 0x0000000EU
#define | TIM_DMABASE_CCR3 0x0000000FU
#define | TIM_DMABASE_CCR4 0x00000010U
#define | TIM_DMABASE_BDTR 0x00000011U
#define | TIM_DMABASE_DCR 0x00000012U
#define | TIM_DMABASE_DMAR 0x00000013U
#define | TIM_DMABASE_OR 0x00000014U
#define | TIM_DMABASE_CCMR3 0x00000015U
#define | TIM_DMABASE_CCR5 0x00000016U
#define | TIM_DMABASE_CCR6 0x00000017U
#define | TIM_DMABASE_AF1 0x00000018U
#define | TIM_DMABASE_AF2 0x00000019U

Define Documentation

#define TIM_DMABASE_AF1 0x00000018U

Definition at line 462 of file stm32wbxx_hal_tim.h.

#define TIM_DMABASE_AF2 0x00000019U

Definition at line 463 of file stm32wbxx_hal_tim.h.

#define TIM_DMABASE_ARR 0x0000000BU

Definition at line 449 of file stm32wbxx_hal_tim.h.

#define TIM_DMABASE_BDTR 0x00000011U

Definition at line 455 of file stm32wbxx_hal_tim.h.

#define TIM_DMABASE_CCER 0x00000008U

Definition at line 446 of file stm32wbxx_hal_tim.h.

#define TIM_DMABASE_CCMR1 0x00000006U

Definition at line 444 of file stm32wbxx_hal_tim.h.

#define TIM_DMABASE_CCMR2 0x00000007U

Definition at line 445 of file stm32wbxx_hal_tim.h.

#define TIM_DMABASE_CCMR3 0x00000015U

Definition at line 459 of file stm32wbxx_hal_tim.h.

#define TIM_DMABASE_CCR1 0x0000000DU

Definition at line 451 of file stm32wbxx_hal_tim.h.

#define TIM_DMABASE_CCR2 0x0000000EU

Definition at line 452 of file stm32wbxx_hal_tim.h.

#define TIM_DMABASE_CCR3 0x0000000FU

Definition at line 453 of file stm32wbxx_hal_tim.h.

#define TIM_DMABASE_CCR4 0x00000010U

Definition at line 454 of file stm32wbxx_hal_tim.h.

#define TIM_DMABASE_CCR5 0x00000016U

Definition at line 460 of file stm32wbxx_hal_tim.h.

#define TIM_DMABASE_CCR6 0x00000017U

Definition at line 461 of file stm32wbxx_hal_tim.h.

#define TIM_DMABASE_CNT 0x00000009U

Definition at line 447 of file stm32wbxx_hal_tim.h.

#define TIM_DMABASE_CR1 0x00000000U

Definition at line 438 of file stm32wbxx_hal_tim.h.

#define TIM_DMABASE_CR2 0x00000001U

Definition at line 439 of file stm32wbxx_hal_tim.h.

#define TIM_DMABASE_DCR 0x00000012U

Definition at line 456 of file stm32wbxx_hal_tim.h.

#define TIM_DMABASE_DIER 0x00000003U

Definition at line 441 of file stm32wbxx_hal_tim.h.

#define TIM_DMABASE_DMAR 0x00000013U

Definition at line 457 of file stm32wbxx_hal_tim.h.

#define TIM_DMABASE_EGR 0x00000005U

Definition at line 443 of file stm32wbxx_hal_tim.h.

#define TIM_DMABASE_OR 0x00000014U

Definition at line 458 of file stm32wbxx_hal_tim.h.

#define TIM_DMABASE_PSC 0x0000000AU

Definition at line 448 of file stm32wbxx_hal_tim.h.

#define TIM_DMABASE_RCR 0x0000000CU

Definition at line 450 of file stm32wbxx_hal_tim.h.

#define TIM_DMABASE_SMCR 0x00000002U

Definition at line 440 of file stm32wbxx_hal_tim.h.

#define TIM_DMABASE_SR 0x00000004U

Definition at line 442 of file stm32wbxx_hal_tim.h.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM Event Source

Defines
TIM Event Source
TIM Exported Constants

Defines

#define | TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
#define | TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
#define | TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
#define | TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
#define | TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
#define | TIM_EVENTSOURCE_COM TIM_EGR_COMG
#define | TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
#define | TIM_EVENTSOURCE_BREAK TIM_EGR_BG
#define | TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G

Define Documentation

#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG

A break event is generated

Definition at line 478 of file stm32wbxx_hal_tim.h.

#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G

A break 2 event is generated

Definition at line 479 of file stm32wbxx_hal_tim.h.

#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G

A capture/compare event is generated on channel 1

Definition at line 472 of file stm32wbxx_hal_tim.h.

#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G

A capture/compare event is generated on channel 2

Definition at line 473 of file stm32wbxx_hal_tim.h.

#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G

A capture/compare event is generated on channel 3

Definition at line 474 of file stm32wbxx_hal_tim.h.

#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G

A capture/compare event is generated on channel 4

Definition at line 475 of file stm32wbxx_hal_tim.h.

#define TIM_EVENTSOURCE_COM TIM_EGR_COMG

A commutation event is generated

Definition at line 476 of file stm32wbxx_hal_tim.h.

#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG

A trigger event is generated

Definition at line 477 of file stm32wbxx_hal_tim.h.

#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG

Reinitialize the counter and generates an update of the registers

Definition at line 471 of file stm32wbxx_hal_tim.h.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM Input Channel polarity

Defines
TIM Input Channel polarity
TIM Exported Constants

Defines

#define | TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U
#define | TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P
#define | TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)

Define Documentation

#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)

Polarity for TIx source

Definition at line 489 of file stm32wbxx_hal_tim.h.

#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P

Polarity for TIx source

Definition at line 488 of file stm32wbxx_hal_tim.h.

#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U

Polarity for TIx source

Definition at line 487 of file stm32wbxx_hal_tim.h.

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STM32WB55xx HAL User Manual: TIM ETR Polarity

Defines
TIM ETR Polarity
TIM Exported Constants

Defines

#define | TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP
#define | TIM_ETRPOLARITY_NONINVERTED 0x00000000U

Define Documentation

#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP

Polarity for ETR source

Definition at line 497 of file stm32wbxx_hal_tim.h.

#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U

Polarity for ETR source

Definition at line 498 of file stm32wbxx_hal_tim.h.

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STM32WB55xx HAL User Manual: TIM ETR Prescaler

Defines
TIM ETR Prescaler
TIM Exported Constants

Defines

#define | TIM_ETRPRESCALER_DIV1 0x00000000U
#define | TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0
#define | TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1
#define | TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS

Define Documentation

#define TIM_ETRPRESCALER_DIV1 0x00000000U

No prescaler is used

Definition at line 506 of file stm32wbxx_hal_tim.h.

#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0

ETR input source is divided by 2

Definition at line 507 of file stm32wbxx_hal_tim.h.

#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1

ETR input source is divided by 4

Definition at line 508 of file stm32wbxx_hal_tim.h.

#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS

ETR input source is divided by 8

Definition at line 509 of file stm32wbxx_hal_tim.h.

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STM32WB55xx HAL User Manual: TIM Counter Mode

Defines
TIM Counter Mode
TIM Exported Constants

Defines

#define | TIM_COUNTERMODE_UP 0x00000000U
#define | TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define | TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
#define | TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
#define | TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS

Define Documentation

#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0

Center-aligned mode 1

Definition at line 519 of file stm32wbxx_hal_tim.h.

#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1

Center-aligned mode 2

Definition at line 520 of file stm32wbxx_hal_tim.h.

#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS

Center-aligned mode 3

Definition at line 521 of file stm32wbxx_hal_tim.h.

#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR

Counter used as down-counter

Definition at line 518 of file stm32wbxx_hal_tim.h.

#define TIM_COUNTERMODE_UP 0x00000000U

Counter used as up-counter

Definition at line 517 of file stm32wbxx_hal_tim.h.

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STM32WB55xx HAL User Manual: TIM Clock Division

Defines
TIM Clock Division
TIM Exported Constants

Defines

#define | TIM_CLOCKDIVISION_DIV1 0x00000000U
#define | TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0
#define | TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1

Define Documentation

#define TIM_CLOCKDIVISION_DIV1 0x00000000U

Clock division: tDTS=tCK_INT

Definition at line 529 of file stm32wbxx_hal_tim.h.

#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0

Clock division: tDTS=2*tCK_INT

Definition at line 530 of file stm32wbxx_hal_tim.h.

#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1

Clock division: tDTS=4*tCK_INT

Definition at line 531 of file stm32wbxx_hal_tim.h.

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STM32WB55xx HAL User Manual: TIM Output Compare State

Defines
TIM Output Compare State
TIM Exported Constants

Defines

#define | TIM_OUTPUTSTATE_DISABLE 0x00000000U
#define | TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E

Define Documentation

#define TIM_OUTPUTSTATE_DISABLE 0x00000000U

Capture/Compare 1 output disabled

Definition at line 539 of file stm32wbxx_hal_tim.h.

#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E

Capture/Compare 1 output enabled

Definition at line 540 of file stm32wbxx_hal_tim.h.

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STM32WB55xx HAL User Manual: TIM Auto-Reload Preload

Defines
TIM Auto-Reload Preload
TIM Exported Constants

Defines

#define | TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U
#define | TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE

Define Documentation

#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U

TIMx_ARR register is not buffered

Definition at line 548 of file stm32wbxx_hal_tim.h.

#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE

TIMx_ARR register is buffered

Definition at line 549 of file stm32wbxx_hal_tim.h.

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STM32WB55xx HAL User Manual: TIM Output Fast State

Defines
TIM Output Fast State
TIM Exported Constants

Defines

#define | TIM_OCFAST_DISABLE 0x00000000U
#define | TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE

Define Documentation

#define TIM_OCFAST_DISABLE 0x00000000U

Output Compare fast disable

Definition at line 558 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE

Output Compare fast enable

Definition at line 559 of file stm32wbxx_hal_tim.h.

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STM32WB55xx HAL User Manual: TIM Complementary Output Compare State

Defines
TIM Complementary Output Compare State
TIM Exported Constants

Defines

#define | TIM_OUTPUTNSTATE_DISABLE 0x00000000U
#define | TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE

Define Documentation

#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U

OCxN is disabled

Definition at line 567 of file stm32wbxx_hal_tim.h.

#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE

OCxN is enabled

Definition at line 568 of file stm32wbxx_hal_tim.h.

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STM32WB55xx HAL User Manual: TIM Output Compare Polarity

Defines
TIM Output Compare Polarity
TIM Exported Constants

Defines

#define | TIM_OCPOLARITY_HIGH 0x00000000U
#define | TIM_OCPOLARITY_LOW TIM_CCER_CC1P

Define Documentation

#define TIM_OCPOLARITY_HIGH 0x00000000U

Capture/Compare output polarity

Definition at line 576 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P

Capture/Compare output polarity

Definition at line 577 of file stm32wbxx_hal_tim.h.

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STM32WB55xx HAL User Manual: TIM Complementary Output Compare Polarity

Defines
TIM Complementary Output Compare Polarity
TIM Exported Constants

Defines

#define | TIM_OCNPOLARITY_HIGH 0x00000000U
#define | TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP

Define Documentation

#define TIM_OCNPOLARITY_HIGH 0x00000000U

Capture/Compare complementary output polarity

Definition at line 585 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP

Capture/Compare complementary output polarity

Definition at line 586 of file stm32wbxx_hal_tim.h.

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STM32WB55xx HAL User Manual: TIM Output Compare Idle State

Defines
TIM Output Compare Idle State
TIM Exported Constants

Defines

#define | TIM_OCIDLESTATE_SET TIM_CR2_OIS1
#define | TIM_OCIDLESTATE_RESET 0x00000000U

Define Documentation

#define TIM_OCIDLESTATE_RESET 0x00000000U

Output Idle state: OCx=0 when MOE=0

Definition at line 595 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1

Output Idle state: OCx=1 when MOE=0

Definition at line 594 of file stm32wbxx_hal_tim.h.

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STM32WB55xx HAL User Manual: TIM Complementary Output Compare Idle State

Defines
TIM Complementary Output Compare Idle State
TIM Exported Constants

Defines

#define | TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N
#define | TIM_OCNIDLESTATE_RESET 0x00000000U

Define Documentation

#define TIM_OCNIDLESTATE_RESET 0x00000000U

Complementary output Idle state: OCxN=0 when MOE=0

Definition at line 604 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N

Complementary output Idle state: OCxN=1 when MOE=0

Definition at line 603 of file stm32wbxx_hal_tim.h.

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STM32WB55xx HAL User Manual: TIM Input Capture Polarity

Defines
TIM Input Capture Polarity
TIM Exported Constants

Defines

#define | TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Define Documentation

#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Capture triggered by both rising and falling edges on timer input

Definition at line 614 of file stm32wbxx_hal_tim.h.

#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING

Capture triggered by falling edge on timer input

Definition at line 613 of file stm32wbxx_hal_tim.h.

#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING

Capture triggered by rising edge on timer input

Definition at line 612 of file stm32wbxx_hal_tim.h.

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STM32WB55xx HAL User Manual: TIM Encoder Input Polarity

Defines
TIM Encoder Input Polarity
TIM Exported Constants

Defines

#define | TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING

Define Documentation

#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING

Encoder input with falling edge polarity

Definition at line 623 of file stm32wbxx_hal_tim.h.

#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING

Encoder input with rising edge polarity

Definition at line 622 of file stm32wbxx_hal_tim.h.

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STM32WB55xx HAL User Manual: TIM Input Capture Selection

Defines
TIM Input Capture Selection
TIM Exported Constants

Defines

#define | TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0
#define | TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1
#define | TIM_ICSELECTION_TRC TIM_CCMR1_CC1S

Define Documentation

#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0

TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively

Definition at line 631 of file stm32wbxx_hal_tim.h.

#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1

TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively

Definition at line 633 of file stm32wbxx_hal_tim.h.

#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S

TIM Input 1, 2, 3 or 4 is selected to be connected to TRC

Definition at line 635 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

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STM32WB55xx HAL User Manual: TIM Input Capture Prescaler

Defines
TIM Input Capture Prescaler
TIM Exported Constants

Defines

#define | TIM_ICPSC_DIV1 0x00000000U
#define | TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0
#define | TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1
#define | TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC

Define Documentation

#define TIM_ICPSC_DIV1 0x00000000U

Capture performed each time an edge is detected on the capture input

Definition at line 643 of file stm32wbxx_hal_tim.h.

#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0

Capture performed once every 2 events

Definition at line 644 of file stm32wbxx_hal_tim.h.

#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1

Capture performed once every 4 events

Definition at line 645 of file stm32wbxx_hal_tim.h.

#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC

Capture performed once every 8 events

Definition at line 646 of file stm32wbxx_hal_tim.h.

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STM32WB55xx HAL User Manual: TIM One Pulse Mode

Defines
TIM One Pulse Mode
TIM Exported Constants

Defines

#define | TIM_OPMODE_SINGLE TIM_CR1_OPM
#define | TIM_OPMODE_REPETITIVE 0x00000000U

Define Documentation

#define TIM_OPMODE_REPETITIVE 0x00000000U

Counter is not stopped at update event

Definition at line 655 of file stm32wbxx_hal_tim.h.

#define TIM_OPMODE_SINGLE TIM_CR1_OPM

Counter stops counting at the next update event

Definition at line 654 of file stm32wbxx_hal_tim.h.

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STM32WB55xx HAL User Manual: TIM Encoder Mode

Defines
TIM Encoder Mode
TIM Exported Constants

Defines

#define | TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0
#define | TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1
#define | TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Define Documentation

#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0

Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level

Definition at line 663 of file stm32wbxx_hal_tim.h.

#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.

Definition at line 665 of file stm32wbxx_hal_tim.h.

#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1

Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level.

Definition at line 664 of file stm32wbxx_hal_tim.h.

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STM32WB55xx HAL User Manual: TIM interrupt Definition

Defines
TIM interrupt Definition
TIM Exported Constants

Defines

#define | TIM_IT_UPDATE TIM_DIER_UIE
#define | TIM_IT_CC1 TIM_DIER_CC1IE
#define | TIM_IT_CC2 TIM_DIER_CC2IE
#define | TIM_IT_CC3 TIM_DIER_CC3IE
#define | TIM_IT_CC4 TIM_DIER_CC4IE
#define | TIM_IT_COM TIM_DIER_COMIE
#define | TIM_IT_TRIGGER TIM_DIER_TIE
#define | TIM_IT_BREAK TIM_DIER_BIE

Define Documentation

#define TIM_IT_BREAK TIM_DIER_BIE

Break interrupt

Definition at line 680 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC1 TIM_DIER_CC1IE

Capture/Compare 1 interrupt

Definition at line 674 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC2 TIM_DIER_CC2IE

Capture/Compare 2 interrupt

Definition at line 675 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC3 TIM_DIER_CC3IE

Capture/Compare 3 interrupt

Definition at line 676 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC4 TIM_DIER_CC4IE

Capture/Compare 4 interrupt

Definition at line 677 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_Start_IT(), and HAL_TIM_PWM_Stop_IT().

#define TIM_IT_COM TIM_DIER_COMIE

Commutation interrupt

Definition at line 678 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), and HAL_TIMEx_ConfigCommutEvent_IT().

#define TIM_IT_TRIGGER TIM_DIER_TIE

Trigger interrupt

Definition at line 679 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_SlaveConfigSynchro(), and HAL_TIM_SlaveConfigSynchro_IT().

#define TIM_IT_UPDATE TIM_DIER_UIE

Update interrupt

Definition at line 673 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_IT(), HAL_TIM_Base_Stop_IT(), and HAL_TIM_IRQHandler().

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STM32WB55xx HAL User Manual: TIM Commutation Source

Defines
TIM Commutation Source
TIM Exported Constants

Defines

#define | TIM_COMMUTATION_TRGI TIM_CR2_CCUS
#define | TIM_COMMUTATION_SOFTWARE 0x00000000U

Define Documentation

#define TIM_COMMUTATION_SOFTWARE 0x00000000U

When Capture/compare control bits are preloaded, they are updated by setting the COMG bit

Definition at line 689 of file stm32wbxx_hal_tim.h.

#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS

When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input

Definition at line 688 of file stm32wbxx_hal_tim.h.

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STM32WB55xx HAL User Manual: TIM DMA Sources

Defines
TIM DMA Sources
TIM Exported Constants

Defines

#define | TIM_DMA_UPDATE TIM_DIER_UDE
#define | TIM_DMA_CC1 TIM_DIER_CC1DE
#define | TIM_DMA_CC2 TIM_DIER_CC2DE
#define | TIM_DMA_CC3 TIM_DIER_CC3DE
#define | TIM_DMA_CC4 TIM_DIER_CC4DE
#define | TIM_DMA_COM TIM_DIER_COMDE
#define | TIM_DMA_TRIGGER TIM_DIER_TDE

Define Documentation

#define TIM_DMA_CC1 TIM_DIER_CC1DE

DMA request is triggered by the capture/compare macth 1 event

Definition at line 698 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define TIM_DMA_CC2 TIM_DIER_CC2DE

DMA request is triggered by the capture/compare macth 2 event event

Definition at line 699 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define TIM_DMA_CC3 TIM_DIER_CC3DE

DMA request is triggered by the capture/compare macth 3 event event

Definition at line 700 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define TIM_DMA_CC4 TIM_DIER_CC4DE

DMA request is triggered by the capture/compare macth 4 event event

Definition at line 701 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), and HAL_TIM_PWM_Stop_DMA().

#define TIM_DMA_COM TIM_DIER_COMDE

DMA request is triggered by the commutation event

Definition at line 702 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), and HAL_TIMEx_ConfigCommutEvent_IT().

#define TIM_DMA_TRIGGER TIM_DIER_TDE

DMA request is triggered by the trigger event

Definition at line 703 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_SlaveConfigSynchro(), and HAL_TIM_SlaveConfigSynchro_IT().

#define TIM_DMA_UPDATE TIM_DIER_UDE

DMA request is triggered by the update event

Definition at line 697 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), and HAL_TIM_DMABurst_WriteStop().

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM Flag Definition

Defines
TIM Flag Definition
TIM Exported Constants

Defines

#define | TIM_FLAG_UPDATE TIM_SR_UIF
#define | TIM_FLAG_CC1 TIM_SR_CC1IF
#define | TIM_FLAG_CC2 TIM_SR_CC2IF
#define | TIM_FLAG_CC3 TIM_SR_CC3IF
#define | TIM_FLAG_CC4 TIM_SR_CC4IF
#define | TIM_FLAG_CC5 TIM_SR_CC5IF
#define | TIM_FLAG_CC6 TIM_SR_CC6IF
#define | TIM_FLAG_COM TIM_SR_COMIF
#define | TIM_FLAG_TRIGGER TIM_SR_TIF
#define | TIM_FLAG_BREAK TIM_SR_BIF
#define | TIM_FLAG_BREAK2 TIM_SR_B2IF
#define | TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF
#define | TIM_FLAG_CC1OF TIM_SR_CC1OF
#define | TIM_FLAG_CC2OF TIM_SR_CC2OF
#define | TIM_FLAG_CC3OF TIM_SR_CC3OF
#define | TIM_FLAG_CC4OF TIM_SR_CC4OF

Define Documentation

#define TIM_FLAG_BREAK TIM_SR_BIF

Break interrupt flag

Definition at line 720 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_BREAK2 TIM_SR_B2IF

Break 2 interrupt flag

Definition at line 721 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC1 TIM_SR_CC1IF

Capture/Compare 1 interrupt flag

Definition at line 712 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC1OF TIM_SR_CC1OF

Capture 1 overcapture flag

Definition at line 723 of file stm32wbxx_hal_tim.h.

#define TIM_FLAG_CC2 TIM_SR_CC2IF

Capture/Compare 2 interrupt flag

Definition at line 713 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC2OF TIM_SR_CC2OF

Capture 2 overcapture flag

Definition at line 724 of file stm32wbxx_hal_tim.h.

#define TIM_FLAG_CC3 TIM_SR_CC3IF

Capture/Compare 3 interrupt flag

Definition at line 714 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC3OF TIM_SR_CC3OF

Capture 3 overcapture flag

Definition at line 725 of file stm32wbxx_hal_tim.h.

#define TIM_FLAG_CC4 TIM_SR_CC4IF

Capture/Compare 4 interrupt flag

Definition at line 715 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC4OF TIM_SR_CC4OF

Capture 4 overcapture flag

Definition at line 726 of file stm32wbxx_hal_tim.h.

#define TIM_FLAG_CC5 TIM_SR_CC5IF

Capture/Compare 5 interrupt flag

Definition at line 716 of file stm32wbxx_hal_tim.h.

#define TIM_FLAG_CC6 TIM_SR_CC6IF

Capture/Compare 6 interrupt flag

Definition at line 717 of file stm32wbxx_hal_tim.h.

#define TIM_FLAG_COM TIM_SR_COMIF

Commutation interrupt flag

Definition at line 718 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF

System Break interrupt flag

Definition at line 722 of file stm32wbxx_hal_tim.h.

#define TIM_FLAG_TRIGGER TIM_SR_TIF

Trigger interrupt flag

Definition at line 719 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_UPDATE TIM_SR_UIF

Update interrupt flag

Definition at line 711 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM Channel

Defines
TIM Channel
TIM Exported Constants

Defines

#define | TIM_CHANNEL_1 0x00000000U
#define | TIM_CHANNEL_2 0x00000004U
#define | TIM_CHANNEL_3 0x00000008U
#define | TIM_CHANNEL_4 0x0000000CU
#define | TIM_CHANNEL_5 0x00000010U
#define | TIM_CHANNEL_6 0x00000014U
#define | TIM_CHANNEL_ALL 0x0000003CU

Define Documentation

#define TIM_CHANNEL_1 0x00000000U

Capture/compare channel 1 identifier

Definition at line 734 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), and TIM_OC1_SetConfig().

#define TIM_CHANNEL_2 0x00000004U

Capture/compare channel 2 identifier

Definition at line 735 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), and TIM_OC2_SetConfig().

#define TIM_CHANNEL_3 0x00000008U

Capture/compare channel 3 identifier

Definition at line 736 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), and TIM_OC3_SetConfig().

#define TIM_CHANNEL_4 0x0000000CU

Capture/compare channel 4 identifier

Definition at line 737 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), and HAL_TIM_ReadCapturedValue().

#define TIM_CHANNEL_5 0x00000010U

Compare channel 5 identifier

Definition at line 738 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

#define TIM_CHANNEL_6 0x00000014U

Compare channel 6 identifier

Definition at line 739 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

#define TIM_CHANNEL_ALL 0x0000003CU

Global Capture/compare channel identifier

Definition at line 740 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Start_DMA().

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STM32WB55xx HAL User Manual: TIM Clock Source

Defines
TIM Clock Source
TIM Exported Constants

Defines

#define | TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1
#define | TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0
#define | TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0
#define | TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1
#define | TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2
#define | TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3
#define | TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED
#define | TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1
#define | TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2
#define | TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF

Define Documentation

#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF

External clock source mode 1 (ETRF)

Definition at line 757 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1

External clock source mode 2

Definition at line 748 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0

Internal clock source

Definition at line 749 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0

External clock source mode 1 (ITR0)

Definition at line 750 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1

External clock source mode 1 (ITR1)

Definition at line 751 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2

External clock source mode 1 (ITR2)

Definition at line 752 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3

External clock source mode 1 (ITR3)

Definition at line 753 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1

External clock source mode 1 (TTI1FP1)

Definition at line 755 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED

External clock source mode 1 (TTI1FP1 + edge detect.)

Definition at line 754 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2

External clock source mode 1 (TTI2FP2)

Definition at line 756 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

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STM32WB55xx HAL User Manual: TIM Clock Polarity

Defines
TIM Clock Polarity
TIM Exported Constants

Defines

#define | TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Define Documentation

#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Polarity for TIx clock sources

Definition at line 769 of file stm32wbxx_hal_tim.h.

#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING

Polarity for TIx clock sources

Definition at line 768 of file stm32wbxx_hal_tim.h.

#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED

Polarity for ETRx clock sources

Definition at line 765 of file stm32wbxx_hal_tim.h.

#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Polarity for ETRx clock sources

Definition at line 766 of file stm32wbxx_hal_tim.h.

#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING

Polarity for TIx clock sources

Definition at line 767 of file stm32wbxx_hal_tim.h.

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STM32WB55xx HAL User Manual: TIM Clock Prescaler

Defines
TIM Clock Prescaler
TIM Exported Constants

Defines

#define | TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Define Documentation

#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1

No prescaler is used

Definition at line 777 of file stm32wbxx_hal_tim.h.

#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2

Prescaler for External ETR Clock: Capture performed once every 2 events.

Definition at line 778 of file stm32wbxx_hal_tim.h.

#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4

Prescaler for External ETR Clock: Capture performed once every 4 events.

Definition at line 779 of file stm32wbxx_hal_tim.h.

#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Prescaler for External ETR Clock: Capture performed once every 8 events.

Definition at line 780 of file stm32wbxx_hal_tim.h.

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STM32WB55xx HAL User Manual: TIM Clear Input Polarity

Defines
TIM Clear Input Polarity
TIM Exported Constants

Defines

#define | TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Define Documentation

#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED

Polarity for ETRx pin

Definition at line 788 of file stm32wbxx_hal_tim.h.

#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Polarity for ETRx pin

Definition at line 789 of file stm32wbxx_hal_tim.h.

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STM32WB55xx HAL User Manual: TIM Clear Input Prescaler

Defines
TIM Clear Input Prescaler
TIM Exported Constants

Defines

#define | TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Define Documentation

#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1

No prescaler is used

Definition at line 797 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2

Prescaler for External ETR pin: Capture performed once every 2 events.

Definition at line 798 of file stm32wbxx_hal_tim.h.

#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4

Prescaler for External ETR pin: Capture performed once every 4 events.

Definition at line 799 of file stm32wbxx_hal_tim.h.

#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Prescaler for External ETR pin: Capture performed once every 8 events.

Definition at line 800 of file stm32wbxx_hal_tim.h.

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STM32WB55xx HAL User Manual: TIM OSSR OffState Selection for Run mode state

Defines
TIM OSSR OffState Selection for Run mode state
TIM Exported Constants

Defines

#define | TIM_OSSR_ENABLE TIM_BDTR_OSSR
#define | TIM_OSSR_DISABLE 0x00000000U

Define Documentation

#define TIM_OSSR_DISABLE 0x00000000U

When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer)

Definition at line 809 of file stm32wbxx_hal_tim.h.

#define TIM_OSSR_ENABLE TIM_BDTR_OSSR

When inactive, OC/OCN outputs are enabled (still controlled by the timer)

Definition at line 808 of file stm32wbxx_hal_tim.h.

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM OSSI OffState Selection for Idle mode state

Defines
TIM OSSI OffState Selection for Idle mode state
TIM Exported Constants

Defines

#define | TIM_OSSI_ENABLE TIM_BDTR_OSSI
#define | TIM_OSSI_DISABLE 0x00000000U

Define Documentation

#define TIM_OSSI_DISABLE 0x00000000U

When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer)

Definition at line 818 of file stm32wbxx_hal_tim.h.

#define TIM_OSSI_ENABLE TIM_BDTR_OSSI

When inactive, OC/OCN outputs are enabled (still controlled by the timer)

Definition at line 817 of file stm32wbxx_hal_tim.h.

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STM32WB55xx HAL User Manual: TIM Lock level

Defines
TIM Lock level
TIM Exported Constants

Defines

#define | TIM_LOCKLEVEL_OFF 0x00000000U
#define | TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0
#define | TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1
#define | TIM_LOCKLEVEL_3 TIM_BDTR_LOCK

Define Documentation

#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0

LOCK Level 1

Definition at line 826 of file stm32wbxx_hal_tim.h.

#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1

LOCK Level 2

Definition at line 827 of file stm32wbxx_hal_tim.h.

#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK

LOCK Level 3

Definition at line 828 of file stm32wbxx_hal_tim.h.

#define TIM_LOCKLEVEL_OFF 0x00000000U

LOCK OFF

Definition at line 825 of file stm32wbxx_hal_tim.h.

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STM32WB55xx HAL User Manual: TIM Break Input Enable

Defines
TIM Break Input Enable
TIM Exported Constants

Defines

#define | TIM_BREAK_ENABLE TIM_BDTR_BKE
#define | TIM_BREAK_DISABLE 0x00000000U

Define Documentation

#define TIM_BREAK_DISABLE 0x00000000U

Break input BRK is disabled

Definition at line 837 of file stm32wbxx_hal_tim.h.

#define TIM_BREAK_ENABLE TIM_BDTR_BKE

Break input BRK is enabled

Definition at line 836 of file stm32wbxx_hal_tim.h.

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STM32WB55xx HAL User Manual: TIM Break Input Polarity

Defines
TIM Break Input Polarity
TIM Exported Constants

Defines

#define | TIM_BREAKPOLARITY_LOW 0x00000000U
#define | TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP

Define Documentation

#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP

Break input BRK is active high

Definition at line 846 of file stm32wbxx_hal_tim.h.

#define TIM_BREAKPOLARITY_LOW 0x00000000U

Break input BRK is active low

Definition at line 845 of file stm32wbxx_hal_tim.h.

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STM32WB55xx HAL User Manual: TIM Break input 2 Enable

Defines
TIM Break input 2 Enable
TIM Exported Constants

Defines

#define | TIM_BREAK2_DISABLE 0x00000000U
#define | TIM_BREAK2_ENABLE TIM_BDTR_BK2E

Define Documentation

#define TIM_BREAK2_DISABLE 0x00000000U

Break input BRK2 is disabled

Definition at line 854 of file stm32wbxx_hal_tim.h.

#define TIM_BREAK2_ENABLE TIM_BDTR_BK2E

Break input BRK2 is enabled

Definition at line 855 of file stm32wbxx_hal_tim.h.

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STM32WB55xx HAL User Manual: TIM Break Input 2 Polarity

Defines
TIM Break Input 2 Polarity
TIM Exported Constants

Defines

#define | TIM_BREAK2POLARITY_LOW 0x00000000U
#define | TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P

Define Documentation

#define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P

Break input BRK2 is active high

Definition at line 864 of file stm32wbxx_hal_tim.h.

#define TIM_BREAK2POLARITY_LOW 0x00000000U

Break input BRK2 is active low

Definition at line 863 of file stm32wbxx_hal_tim.h.

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STM32WB55xx HAL User Manual: TIM Automatic Output Enable

Defines
TIM Automatic Output Enable
TIM Exported Constants

Defines

#define | TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U
#define | TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE

Define Documentation

#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U

MOE can be set only by software

Definition at line 872 of file stm32wbxx_hal_tim.h.

#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE

MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)

Definition at line 873 of file stm32wbxx_hal_tim.h.

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Group Channel 5 and Channel 1, 2 or 3

Defines
Group Channel 5 and Channel 1, 2 or 3
TIM Exported Constants

Defines

#define | TIM_GROUPCH5_NONE 0x00000000U /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
#define | TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
#define | TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
#define | TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */

Define Documentation

#define TIM_GROUPCH5_NONE 0x00000000U /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */

Definition at line 882 of file stm32wbxx_hal_tim.h.

#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */

Definition at line 883 of file stm32wbxx_hal_tim.h.

#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */

Definition at line 884 of file stm32wbxx_hal_tim.h.

#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */

Definition at line 885 of file stm32wbxx_hal_tim.h.

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STM32WB55xx HAL User Manual: TIM Master Mode Selection

Defines
TIM Master Mode Selection
TIM Exported Constants

Defines

#define | TIM_TRGO_RESET 0x00000000U
#define | TIM_TRGO_ENABLE TIM_CR2_MMS_0
#define | TIM_TRGO_UPDATE TIM_CR2_MMS_1
#define | TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
#define | TIM_TRGO_OC1REF TIM_CR2_MMS_2
#define | TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)
#define | TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)
#define | TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)

Define Documentation

#define TIM_TRGO_ENABLE TIM_CR2_MMS_0

TIMx_CR1.CEN bit is used as trigger output (TRGO)

Definition at line 894 of file stm32wbxx_hal_tim.h.

#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)

Capture or a compare match 1 is used as trigger output (TRGO)

Definition at line 896 of file stm32wbxx_hal_tim.h.

#define TIM_TRGO_OC1REF TIM_CR2_MMS_2

OC1REF signal is used as trigger output (TRGO)

Definition at line 897 of file stm32wbxx_hal_tim.h.

#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)

OC2REF signal is used as trigger output(TRGO)

Definition at line 898 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)

OC3REF signal is used as trigger output(TRGO)

Definition at line 899 of file stm32wbxx_hal_tim.h.

#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)

OC4REF signal is used as trigger output(TRGO)

Definition at line 900 of file stm32wbxx_hal_tim.h.

#define TIM_TRGO_RESET 0x00000000U

TIMx_EGR.UG bit is used as trigger output (TRGO)

Definition at line 893 of file stm32wbxx_hal_tim.h.

#define TIM_TRGO_UPDATE TIM_CR2_MMS_1

Update event is used as trigger output (TRGO)

Definition at line 895 of file stm32wbxx_hal_tim.h.

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STM32WB55xx HAL User Manual: TIM Master Mode Selection 2 (TRGO2)

Defines
TIM Master Mode Selection 2 (TRGO2)
TIM Exported Constants

Defines

#define | TIM_TRGO2_RESET 0x00000000U
#define | TIM_TRGO2_ENABLE TIM_CR2_MMS2_0
#define | TIM_TRGO2_UPDATE TIM_CR2_MMS2_1
#define | TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC1REF TIM_CR2_MMS2_2
#define | TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)
#define | TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC5REF TIM_CR2_MMS2_3
#define | TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)
#define | TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)
#define | TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)
#define | TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

Define Documentation

#define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0

TIMx_CR1.CEN bit is used as trigger output (TRGO2)

Definition at line 909 of file stm32wbxx_hal_tim.h.

#define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

Capture or a compare match 1 is used as trigger output (TRGO2)

Definition at line 911 of file stm32wbxx_hal_tim.h.

#define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2

OC1REF signal is used as trigger output (TRGO2)

Definition at line 912 of file stm32wbxx_hal_tim.h.

#define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)

OC2REF signal is used as trigger output (TRGO2)

Definition at line 913 of file stm32wbxx_hal_tim.h.

#define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)

OC3REF signal is used as trigger output (TRGO2)

Definition at line 914 of file stm32wbxx_hal_tim.h.

#define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

OC4REF signal is used as trigger output (TRGO2)

Definition at line 915 of file stm32wbxx_hal_tim.h.

#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)

OC4REF rising or OC6REF falling edges generate pulses on TRGO2

Definition at line 921 of file stm32wbxx_hal_tim.h.

#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)

OC4REF or OC6REF rising edges generate pulses on TRGO2

Definition at line 920 of file stm32wbxx_hal_tim.h.

#define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)

OC4REF rising or falling edges generate pulses on TRGO2

Definition at line 918 of file stm32wbxx_hal_tim.h.

#define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3

OC5REF signal is used as trigger output (TRGO2)

Definition at line 916 of file stm32wbxx_hal_tim.h.

#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

OC5REF or OC6REF rising edges generate pulses on TRGO2

Definition at line 923 of file stm32wbxx_hal_tim.h.

#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)

OC5REF or OC6REF rising edges generate pulses on TRGO2

Definition at line 922 of file stm32wbxx_hal_tim.h.

#define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)

OC6REF signal is used as trigger output (TRGO2)

Definition at line 917 of file stm32wbxx_hal_tim.h.

#define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)

OC6REF rising or falling edges generate pulses on TRGO2

Definition at line 919 of file stm32wbxx_hal_tim.h.

#define TIM_TRGO2_RESET 0x00000000U

TIMx_EGR.UG bit is used as trigger output (TRGO2)

Definition at line 908 of file stm32wbxx_hal_tim.h.

#define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1

Update event is used as trigger output (TRGO2)

Definition at line 910 of file stm32wbxx_hal_tim.h.

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STM32WB55xx HAL User Manual: TIM Master/Slave Mode

Defines
TIM Master/Slave Mode
TIM Exported Constants

Defines

#define | TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM
#define | TIM_MASTERSLAVEMODE_DISABLE 0x00000000U

Define Documentation

#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U

Master/slave mode is selected

Definition at line 932 of file stm32wbxx_hal_tim.h.

#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM

No action

Definition at line 931 of file stm32wbxx_hal_tim.h.

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STM32WB55xx HAL User Manual: TIM Slave mode

Defines
TIM Slave mode
TIM Exported Constants

Defines

#define | TIM_SLAVEMODE_DISABLE 0x00000000U
#define | TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2
#define | TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)
#define | TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)
#define | TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3

Define Documentation

#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3

Combined reset + trigger mode

Definition at line 945 of file stm32wbxx_hal_tim.h.

#define TIM_SLAVEMODE_DISABLE 0x00000000U

Slave mode disabled

Definition at line 940 of file stm32wbxx_hal_tim.h.

#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

External Clock Mode 1

Definition at line 944 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource(), and TIM_ITRx_SetConfig().

#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)

Gated Mode

Definition at line 942 of file stm32wbxx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2

Reset Mode

Definition at line 941 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)

Trigger Mode

Definition at line 943 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

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STM32WB55xx HAL User Manual: TIM Output Compare and PWM Modes

Defines
TIM Output Compare and PWM Modes
TIM Exported Constants

Defines

#define | TIM_OCMODE_TIMING 0x00000000U
#define | TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0
#define | TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1
#define | TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
#define | TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2
#define | TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3
#define | TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M

Define Documentation

#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0

Set channel to active level on match

Definition at line 954 of file stm32wbxx_hal_tim.h.

#define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)

Asymmetric PWM mode 1

Definition at line 965 of file stm32wbxx_hal_tim.h.

#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M

Asymmetric PWM mode 2

Definition at line 966 of file stm32wbxx_hal_tim.h.

#define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)

Combined PWM mode 1

Definition at line 963 of file stm32wbxx_hal_tim.h.

#define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)

Combined PWM mode 2

Definition at line 964 of file stm32wbxx_hal_tim.h.

#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)

Force active level

Definition at line 959 of file stm32wbxx_hal_tim.h.

#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2

Force inactive level

Definition at line 960 of file stm32wbxx_hal_tim.h.

#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1

Set channel to inactive level on match

Definition at line 955 of file stm32wbxx_hal_tim.h.

#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)

PWM mode 1

Definition at line 957 of file stm32wbxx_hal_tim.h.

#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)

PWM mode 2

Definition at line 958 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3

Retrigerrable OPM mode 1

Definition at line 961 of file stm32wbxx_hal_tim.h.

#define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)

Retrigerrable OPM mode 2

Definition at line 962 of file stm32wbxx_hal_tim.h.

#define TIM_OCMODE_TIMING 0x00000000U

Frozen

Definition at line 953 of file stm32wbxx_hal_tim.h.

#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)

Toggle

Definition at line 956 of file stm32wbxx_hal_tim.h.

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STM32WB55xx HAL User Manual: TIM Trigger Selection

Defines
TIM Trigger Selection
TIM Exported Constants

Defines

#define | TIM_TS_ITR0 0x00000000U
#define | TIM_TS_ITR1 TIM_SMCR_TS_0
#define | TIM_TS_ITR2 TIM_SMCR_TS_1
#define | TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
#define | TIM_TS_TI1F_ED TIM_SMCR_TS_2
#define | TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
#define | TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
#define | TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
#define | TIM_TS_NONE 0x0000FFFFU

Define Documentation

#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)

Filtered External Trigger input (ETRF)

Definition at line 981 of file stm32wbxx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR0 0x00000000U

Internal Trigger 0 (ITR0)

Definition at line 974 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_ConfigCommutEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR1 TIM_SMCR_TS_0

Internal Trigger 1 (ITR1)

Definition at line 975 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_ConfigCommutEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR2 TIM_SMCR_TS_1

Internal Trigger 2 (ITR2)

Definition at line 976 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_ConfigCommutEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)

Internal Trigger 3 (ITR3)

Definition at line 977 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_ConfigCommutEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_NONE 0x0000FFFFU

No trigger selected

Definition at line 982 of file stm32wbxx_hal_tim.h.

#define TIM_TS_TI1F_ED TIM_SMCR_TS_2

TI1 Edge Detector (TI1F_ED)

Definition at line 978 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)

Filtered Timer Input 1 (TI1FP1)

Definition at line 979 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)

Filtered Timer Input 2 (TI2FP2)

Definition at line 980 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), and TIM_SlaveTimer_SetConfig().

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STM32WB55xx HAL User Manual: TIM Trigger Polarity

Defines
TIM Trigger Polarity
TIM Exported Constants

Defines

#define | TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Define Documentation

#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Polarity for TIxFPx or TI1_ED trigger sources

Definition at line 994 of file stm32wbxx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING

Polarity for TIxFPx or TI1_ED trigger sources

Definition at line 993 of file stm32wbxx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED

Polarity for ETRx trigger sources

Definition at line 990 of file stm32wbxx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Polarity for ETRx trigger sources

Definition at line 991 of file stm32wbxx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING

Polarity for TIxFPx or TI1_ED trigger sources

Definition at line 992 of file stm32wbxx_hal_tim.h.

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STM32WB55xx HAL User Manual: TIM Trigger Prescaler

Defines
TIM Trigger Prescaler
TIM Exported Constants

Defines

#define | TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Define Documentation

#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1

No prescaler is used

Definition at line 1002 of file stm32wbxx_hal_tim.h.

#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2

Prescaler for External ETR Trigger: Capture performed once every 2 events.

Definition at line 1003 of file stm32wbxx_hal_tim.h.

#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4

Prescaler for External ETR Trigger: Capture performed once every 4 events.

Definition at line 1004 of file stm32wbxx_hal_tim.h.

#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Prescaler for External ETR Trigger: Capture performed once every 8 events.

Definition at line 1005 of file stm32wbxx_hal_tim.h.

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STM32WB55xx HAL User Manual: TIM TI1 Input Selection

Defines
TIM TI1 Input Selection
TIM Exported Constants

Defines

#define | TIM_TI1SELECTION_CH1 0x00000000U
#define | TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S

Define Documentation

#define TIM_TI1SELECTION_CH1 0x00000000U

The TIMx_CH1 pin is connected to TI1 input

Definition at line 1013 of file stm32wbxx_hal_tim.h.

#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S

The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)

Definition at line 1014 of file stm32wbxx_hal_tim.h.

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STM32WB55xx HAL User Manual: TIM DMA Burst Length

Defines
TIM DMA Burst Length
TIM Exported Constants

Defines

#define | TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U
#define | TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U
#define | TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U
#define | TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U
#define | TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U
#define | TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U
#define | TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U
#define | TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U
#define | TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U
#define | TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U
#define | TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U
#define | TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U
#define | TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U
#define | TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U
#define | TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U
#define | TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U
#define | TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U
#define | TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U

Define Documentation

#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U

The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1031 of file stm32wbxx_hal_tim.h.

#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U

The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1032 of file stm32wbxx_hal_tim.h.

#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U

The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1033 of file stm32wbxx_hal_tim.h.

#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U

The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1034 of file stm32wbxx_hal_tim.h.

#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U

The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1035 of file stm32wbxx_hal_tim.h.

#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U

The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1036 of file stm32wbxx_hal_tim.h.

#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U

The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1037 of file stm32wbxx_hal_tim.h.

#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U

The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1038 of file stm32wbxx_hal_tim.h.

#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U

The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1039 of file stm32wbxx_hal_tim.h.

#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U

The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1022 of file stm32wbxx_hal_tim.h.

#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U

The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1023 of file stm32wbxx_hal_tim.h.

#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U

The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1024 of file stm32wbxx_hal_tim.h.

#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U

The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1025 of file stm32wbxx_hal_tim.h.

#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U

The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1026 of file stm32wbxx_hal_tim.h.

#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U

The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1027 of file stm32wbxx_hal_tim.h.

#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U

The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1028 of file stm32wbxx_hal_tim.h.

#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U

The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1029 of file stm32wbxx_hal_tim.h.

#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U

The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA

Definition at line 1030 of file stm32wbxx_hal_tim.h.

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM DMA Handle Index

Defines
TIM DMA Handle Index
TIM Exported Constants

Defines

#define | TIM_DMA_ID_UPDATE ((uint16_t) 0x0000)
#define | TIM_DMA_ID_CC1 ((uint16_t) 0x0001)
#define | TIM_DMA_ID_CC2 ((uint16_t) 0x0002)
#define | TIM_DMA_ID_CC3 ((uint16_t) 0x0003)
#define | TIM_DMA_ID_CC4 ((uint16_t) 0x0004)
#define | TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005)
#define | TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006)

Define Documentation

#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001)

Index of the DMA handle used for Capture/Compare 1 DMA requests

Definition at line 1048 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Stop_DMA(), TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMADelayPulseCplt(), and TIM_DMADelayPulseHalfCplt().

#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002)

Index of the DMA handle used for Capture/Compare 2 DMA requests

Definition at line 1049 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Stop_DMA(), TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMADelayPulseCplt(), and TIM_DMADelayPulseHalfCplt().

#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003)

Index of the DMA handle used for Capture/Compare 3 DMA requests

Definition at line 1050 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Stop_DMA(), TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMADelayPulseCplt(), and TIM_DMADelayPulseHalfCplt().

#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004)

Index of the DMA handle used for Capture/Compare 4 DMA requests

Definition at line 1051 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMADelayPulseCplt(), and TIM_DMADelayPulseHalfCplt().

#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005)

Index of the DMA handle used for Commutation DMA requests

Definition at line 1052 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), and HAL_TIMEx_ConfigCommutEvent_DMA().

#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006)

Index of the DMA handle used for Trigger DMA requests

Definition at line 1053 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), and HAL_TIM_DMABurst_WriteStop().

#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000)

Index of the DMA handle used for Update DMA requests

Definition at line 1047 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), and HAL_TIM_DMABurst_WriteStop().

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM Capture/Compare Channel State

Defines
TIM Capture/Compare Channel State
TIM Exported Constants

Defines

#define | TIM_CCx_ENABLE 0x00000001U
#define | TIM_CCx_DISABLE 0x00000000U
#define | TIM_CCxN_ENABLE 0x00000004U
#define | TIM_CCxN_DISABLE 0x00000000U

Define Documentation

#define TIM_CCx_DISABLE 0x00000000U

Input or output channel is disabled

Definition at line 1062 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), and HAL_TIMEx_HallSensor_Stop_IT().

#define TIM_CCx_ENABLE 0x00000001U

Input or output channel is enabled

Definition at line 1061 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), and HAL_TIMEx_HallSensor_Start_IT().

#define TIM_CCxN_DISABLE 0x00000000U

Complementary output channel is enabled

Definition at line 1064 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_CCxN_ENABLE 0x00000004U

Complementary output channel is enabled

Definition at line 1063 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Start_IT().

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM Break System

Defines
TIM Break System
TIM Exported Constants

Defines

#define | TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL
#define | TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL
#define | TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR SYSCFG_CFGR2_SPL
#define | TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL

Define Documentation

#define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL

Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17

Definition at line 1072 of file stm32wbxx_hal_tim.h.

#define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL

Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17

Definition at line 1075 of file stm32wbxx_hal_tim.h.

#define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL

Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface

Definition at line 1073 of file stm32wbxx_hal_tim.h.

#define TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR SYSCFG_CFGR2_SPL

Enables and locks the SRAM2_PARITY error signal with Break Input of TIM1/8/15/16/17

Definition at line 1074 of file stm32wbxx_hal_tim.h.

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM Exported Macros

Defines
TIM Exported Macros
TIM

Defines

#define | __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__)
Reset TIM handle state.
#define | __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
Enable the TIM peripheral.
#define | __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
Enable the TIM main Output.
#define | __HAL_TIM_DISABLE(__HANDLE__)
Disable the TIM peripheral.
#define | __HAL_TIM_MOE_DISABLE(__HANDLE__)
Disable the TIM main Output.
#define | __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
Disable the TIM main Output.
#define | __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
Enable the specified TIM interrupt.
#define | __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
Disable the specified TIM interrupt.
#define | __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
Enable the specified DMA request.
#define | __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
Disable the specified DMA request.
#define | __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
Check whether the specified TIM interrupt flag is set or not.
#define | __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clear the specified TIM interrupt flag.
#define | __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified TIM interrupt source is enabled or not.
#define | __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
Clear the TIM interrupt pending bits.
#define | __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
Indicates whether or not the TIM Counter is used as downcounter.
#define | __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
Set the TIM Prescaler on runtime.
#define | __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
Set the TIM Counter Register value on runtime.
#define | __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
Get the TIM Counter Register value on runtime.
#define | __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__)
Set the TIM Autoreload Register value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
Get the TIM Autoreload Register value on runtime.
#define | __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__)
Set the TIM Clock Division value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
Get the TIM Clock Division value on runtime.
#define | __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__)
Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
#define | __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)
Get the TIM Input Capture prescaler on runtime.
#define | __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__)
Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
#define | __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__)
Get the TIM Capture Compare Register value on runtime.
#define | __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)
Set the TIM Output compare preload.
#define | __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)
Reset the TIM Output compare preload.
#define | __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__)
Enable fast mode for a given channel.
#define | __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__)
Disable fast mode for a given channel.
#define | __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
Set the Update Request Source (URS) bit of the TIMx_CR1 register.
#define | __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
#define | __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
Set the TIM Capture x input polarity on runtime.

Define Documentation

#define __HAL_TIM_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->SR = ~(__FLAG__))

Clear the specified TIM interrupt flag.

Parameters:
__HANDLE__ specifies the TIM Handle.
__FLAG__ specifies the TIM interrupt flag to clear. This parameter can be one of the following values:
  • TIM_FLAG_UPDATE: Update interrupt flag
  • TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
  • TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
  • TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
  • TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
  • TIM_FLAG_CC5: Compare 5 interrupt flag
  • TIM_FLAG_CC6: Compare 6 interrupt flag
  • TIM_FLAG_COM: Commutation interrupt flag
  • TIM_FLAG_TRIGGER: Trigger interrupt flag
  • TIM_FLAG_BREAK: Break interrupt flag
  • TIM_FLAG_BREAK2: Break 2 interrupt flag
  • TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
  • TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
  • TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
  • TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
  • TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 1279 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define __HAL_TIM_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))

Clear the TIM interrupt pending bits.

Parameters:
__HANDLE__ TIM handle
__INTERRUPT__ specifies the interrupt pending bit to clear. This parameter can be one of the following values:
  • TIM_IT_UPDATE: Update interrupt
  • TIM_IT_CC1: Capture/Compare 1 interrupt
  • TIM_IT_CC2: Capture/Compare 2 interrupt
  • TIM_IT_CC3: Capture/Compare 3 interrupt
  • TIM_IT_CC4: Capture/Compare 4 interrupt
  • TIM_IT_COM: Commutation interrupt
  • TIM_IT_TRIGGER: Trigger interrupt
  • TIM_IT_BREAK: Break interrupt
Return values:
None

Definition at line 1313 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define __HAL_TIM_DISABLE ( __HANDLE__ )
Value:
do { \
    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
    { \
      if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
      { \
        (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
      } \
    } \
  } while(0)

Disable the TIM peripheral.

Parameters:
__HANDLE__ TIM handle
Return values:
None

Definition at line 1135 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_Base_Stop_IT(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define __HAL_TIM_DISABLE_DMA | ( | __HANDLE__,
 |  | __DMA__
 | ) | ((__HANDLE__)->Instance->DIER &= ~(__DMA__))

Disable the specified DMA request.

Parameters:
__HANDLE__ specifies the TIM Handle.
__DMA__ specifies the TIM DMA request to disable. This parameter can be one of the following values:
  • TIM_DMA_UPDATE: Update DMA request
  • TIM_DMA_CC1: Capture/Compare 1 DMA request
  • TIM_DMA_CC2: Capture/Compare 2 DMA request
  • TIM_DMA_CC3: Capture/Compare 3 DMA request
  • TIM_DMA_CC4: Capture/Compare 4 DMA request
  • TIM_DMA_COM: Commutation DMA request
  • TIM_DMA_TRIGGER: Trigger DMA request
Return values:
None

Definition at line 1231 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Base_Stop_DMA(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_SlaveConfigSynchro(), HAL_TIM_SlaveConfigSynchro_IT(), HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_IT(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_OCN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define __HAL_TIM_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))

Disable the specified TIM interrupt.

Parameters:
__HANDLE__ specifies the TIM Handle.
__INTERRUPT__ specifies the TIM interrupt source to disable. This parameter can be one of the following values:
  • TIM_IT_UPDATE: Update interrupt
  • TIM_IT_CC1: Capture/Compare 1 interrupt
  • TIM_IT_CC2: Capture/Compare 2 interrupt
  • TIM_IT_CC3: Capture/Compare 3 interrupt
  • TIM_IT_CC4: Capture/Compare 4 interrupt
  • TIM_IT_COM: Commutation interrupt
  • TIM_IT_TRIGGER: Trigger interrupt
  • TIM_IT_BREAK: Break interrupt
Return values:
None

Definition at line 1201 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Base_Stop_IT(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_SlaveConfigSynchro(), HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define __HAL_TIM_DISABLE_OCxFAST | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\
   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\
   ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE))

Disable fast mode for a given channel.

Parameters:
__HANDLE__ TIM handle.
__CHANNEL__ TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Note:
When fast mode is disabled CCx output behaves normally depending on counter and CCRx values even when the trigger is ON. The minimum delay to activate CCx output when an active edge occurs on the trigger input is 5 clock cycles.
Return values:
None

Definition at line 1564 of file stm32wbxx_hal_tim.h.

#define __HAL_TIM_DISABLE_OCxPRELOAD | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\
   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\
   ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE))

Reset the TIM Output compare preload.

Parameters:
__HANDLE__ TIM handle.
__CHANNEL__ TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
None

Definition at line 1514 of file stm32wbxx_hal_tim.h.

#define __HAL_TIM_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))

Enable the TIM peripheral.

Parameters:
__HANDLE__ TIM handle
Return values:
None

Definition at line 1121 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Start_IT().

#define __HAL_TIM_ENABLE_DMA | ( | __HANDLE__,
 |  | __DMA__
 | ) | ((__HANDLE__)->Instance->DIER |= (__DMA__))

Enable the specified DMA request.

Parameters:
__HANDLE__ specifies the TIM Handle.
__DMA__ specifies the TIM DMA request to enable. This parameter can be one of the following values:
  • TIM_DMA_UPDATE: Update DMA request
  • TIM_DMA_CC1: Capture/Compare 1 DMA request
  • TIM_DMA_CC2: Capture/Compare 2 DMA request
  • TIM_DMA_CC3: Capture/Compare 3 DMA request
  • TIM_DMA_CC4: Capture/Compare 4 DMA request
  • TIM_DMA_COM: Commutation DMA request
  • TIM_DMA_TRIGGER: Trigger DMA request
Return values:
None

Definition at line 1216 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

#define __HAL_TIM_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))

Enable the specified TIM interrupt.

Parameters:
__HANDLE__ specifies the TIM Handle.
__INTERRUPT__ specifies the TIM interrupt source to enable. This parameter can be one of the following values:
  • TIM_IT_UPDATE: Update interrupt
  • TIM_IT_CC1: Capture/Compare 1 interrupt
  • TIM_IT_CC2: Capture/Compare 2 interrupt
  • TIM_IT_CC3: Capture/Compare 3 interrupt
  • TIM_IT_CC4: Capture/Compare 4 interrupt
  • TIM_IT_COM: Commutation interrupt
  • TIM_IT_TRIGGER: Trigger interrupt
  • TIM_IT_BREAK: Break interrupt
Return values:
None

Definition at line 1185 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_IT(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_IC_Start_IT(), HAL_TIM_OC_Start_IT(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_SlaveConfigSynchro_IT(), HAL_TIMEx_ConfigCommutEvent_IT(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OnePulseN_Start_IT(), and HAL_TIMEx_PWMN_Start_IT().

#define __HAL_TIM_ENABLE_OCxFAST | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\
   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\
   ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE))

Enable fast mode for a given channel.

Parameters:
__HANDLE__ TIM handle.
__CHANNEL__ TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Note:
When fast mode is enabled an active edge on the trigger input acts like a compare match on CCx output. Delay to sample the trigger input and to activate CCx output is reduced to 3 clock cycles.
Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
Return values:
None

Definition at line 1539 of file stm32wbxx_hal_tim.h.

#define __HAL_TIM_ENABLE_OCxPRELOAD | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
   ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))

Set the TIM Output compare preload.

Parameters:
__HANDLE__ TIM handle.
__CHANNEL__ TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
Return values:
None

Definition at line 1493 of file stm32wbxx_hal_tim.h.

#define __HAL_TIM_GET_AUTORELOAD ( __HANDLE__ ) ((__HANDLE__)->Instance->ARR)

Get the TIM Autoreload Register value on runtime.

Parameters:
__HANDLE__ TIM handle.
Return values:
16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)

Definition at line 1364 of file stm32wbxx_hal_tim.h.

#define __HAL_TIM_GET_CLOCKDIVISION ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)

Get the TIM Clock Division value on runtime.

Parameters:
__HANDLE__ TIM handle.
Return values:
The clock division can be one of the following values:
  • TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
  • TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
  • TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT

Definition at line 1391 of file stm32wbxx_hal_tim.h.

#define __HAL_TIM_GET_COMPARE | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
   ((__HANDLE__)->Instance->CCR6))

Get the TIM Capture Compare Register value on runtime.

Parameters:
__HANDLE__ TIM handle.
__CHANNEL__ TIM Channel associated with the capture compare register This parameter can be one of the following values:
  • TIM_CHANNEL_1: get capture/compare 1 register value
  • TIM_CHANNEL_2: get capture/compare 2 register value
  • TIM_CHANNEL_3: get capture/compare 3 register value
  • TIM_CHANNEL_4: get capture/compare 4 register value
  • TIM_CHANNEL_5: get capture/compare 5 register value
  • TIM_CHANNEL_6: get capture/compare 6 register value
Return values:
16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)

Definition at line 1472 of file stm32wbxx_hal_tim.h.

#define __HAL_TIM_GET_COUNTER ( __HANDLE__ ) ((__HANDLE__)->Instance->CNT)

Get the TIM Counter Register value on runtime.

Parameters:
__HANDLE__ TIM handle.
Return values:
16-bit or 32-bit value of the timer counter register (TIMx_CNT)

Definition at line 1345 of file stm32wbxx_hal_tim.h.

#define __HAL_TIM_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))

Check whether the specified TIM interrupt flag is set or not.

Parameters:
__HANDLE__ specifies the TIM Handle.
__FLAG__ specifies the TIM interrupt flag to check. This parameter can be one of the following values:
  • TIM_FLAG_UPDATE: Update interrupt flag
  • TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
  • TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
  • TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
  • TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
  • TIM_FLAG_CC5: Compare 5 interrupt flag
  • TIM_FLAG_CC6: Compare 6 interrupt flag
  • TIM_FLAG_COM: Commutation interrupt flag
  • TIM_FLAG_TRIGGER: Trigger interrupt flag
  • TIM_FLAG_BREAK: Break interrupt flag
  • TIM_FLAG_BREAK2: Break 2 interrupt flag
  • TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
  • TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
  • TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
  • TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
  • TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 1255 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define __HAL_TIM_GET_ICPRESCALER | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
   (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)

Get the TIM Input Capture prescaler on runtime.

Parameters:
__HANDLE__ TIM handle.
__CHANNEL__ TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: get input capture 1 prescaler value
  • TIM_CHANNEL_2: get input capture 2 prescaler value
  • TIM_CHANNEL_3: get input capture 3 prescaler value
  • TIM_CHANNEL_4: get input capture 4 prescaler value
Return values:
The input capture prescaler can be one of the following values:
  • TIM_ICPSC_DIV1: no prescaler
  • TIM_ICPSC_DIV2: capture is done once every 2 events
  • TIM_ICPSC_DIV4: capture is done once every 4 events
  • TIM_ICPSC_DIV8: capture is done once every 8 events

Definition at line 1431 of file stm32wbxx_hal_tim.h.

#define __HAL_TIM_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
                                                             == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified TIM interrupt source is enabled or not.

Parameters:
__HANDLE__ TIM handle
__INTERRUPT__ specifies the TIM interrupt source to check. This parameter can be one of the following values:
  • TIM_IT_UPDATE: Update interrupt
  • TIM_IT_CC1: Capture/Compare 1 interrupt
  • TIM_IT_CC2: Capture/Compare 2 interrupt
  • TIM_IT_CC3: Capture/Compare 3 interrupt
  • TIM_IT_CC4: Capture/Compare 4 interrupt
  • TIM_IT_COM: Commutation interrupt
  • TIM_IT_TRIGGER: Trigger interrupt
  • TIM_IT_BREAK: Break interrupt
Return values:
The state of TIM_IT (SET or RESET).

Definition at line 1296 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define __HAL_TIM_IS_TIM_COUNTING_DOWN ( __HANDLE__ ) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))

Indicates whether or not the TIM Counter is used as downcounter.

Parameters:
__HANDLE__ TIM handle.
Return values:
False (Counter used as upcounter) or True (Counter used as downcounter)
Note:
This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder mode.

Definition at line 1322 of file stm32wbxx_hal_tim.h.

#define __HAL_TIM_MOE_DISABLE ( __HANDLE__ )
Value:
do { \
    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
    { \
      if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
      { \
        (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
      } \
    } \
  } while(0)

Disable the TIM main Output.

Parameters:
__HANDLE__ TIM handle
Return values:
None
Note:
The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled

Definition at line 1152 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY ( __HANDLE__ ) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)

Disable the TIM main Output.

Parameters:
__HANDLE__ TIM handle
Return values:
None
Note:
The Main Output Enable of a timer instance is disabled unconditionally

Definition at line 1169 of file stm32wbxx_hal_tim.h.

#define __HAL_TIM_MOE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))

Enable the TIM main Output.

Parameters:
__HANDLE__ TIM handle
Return values:
None

Definition at line 1128 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Start_IT().

#define __HAL_TIM_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do {                                                        \
                                                      (__HANDLE__)->State             = HAL_TIM_STATE_RESET; \
                                                      (__HANDLE__)->Base_MspInitCallback         = NULL;     \
                                                      (__HANDLE__)->Base_MspDeInitCallback       = NULL;     \
                                                      (__HANDLE__)->IC_MspInitCallback           = NULL;     \
                                                      (__HANDLE__)->IC_MspDeInitCallback         = NULL;     \
                                                      (__HANDLE__)->OC_MspInitCallback           = NULL;     \
                                                      (__HANDLE__)->OC_MspDeInitCallback         = NULL;     \
                                                      (__HANDLE__)->PWM_MspInitCallback          = NULL;     \
                                                      (__HANDLE__)->PWM_MspDeInitCallback        = NULL;     \
                                                      (__HANDLE__)->OnePulse_MspInitCallback     = NULL;     \
                                                      (__HANDLE__)->OnePulse_MspDeInitCallback   = NULL;     \
                                                      (__HANDLE__)->Encoder_MspInitCallback      = NULL;     \
                                                      (__HANDLE__)->Encoder_MspDeInitCallback    = NULL;     \
                                                      (__HANDLE__)->HallSensor_MspInitCallback   = NULL;     \
                                                      (__HANDLE__)->HallSensor_MspDeInitCallback = NULL;     \
                                                     } while(0)

Reset TIM handle state.

Parameters:
__HANDLE__ TIM handle.
Return values:
None

Definition at line 1095 of file stm32wbxx_hal_tim.h.

#define __HAL_TIM_SET_AUTORELOAD | ( | __HANDLE__,
 |  | __AUTORELOAD__
 | ) |
Value:
do{                                                    \
    (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
    (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
  } while(0)

Set the TIM Autoreload Register value on runtime without calling another time any Init function.

Parameters:
__HANDLE__ | TIM handle.
__AUTORELOAD__ | specifies the Counter register new value.
Return values:
None

Definition at line 1353 of file stm32wbxx_hal_tim.h.

#define __HAL_TIM_SET_CAPTUREPOLARITY | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __POLARITY__
 | ) |
Value:
do{                                                                     \
    TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
    TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
  }while(0)

Set the TIM Capture x input polarity on runtime.

Parameters:
__HANDLE__ TIM handle.
__CHANNEL__ TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
__POLARITY__ Polarity for TIx source
  • TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
  • TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
  • TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
Return values:
None

Definition at line 1610 of file stm32wbxx_hal_tim.h.

#define __HAL_TIM_SET_CLOCKDIVISION | ( | __HANDLE__,
 |  | __CKD__
 | ) |
Value:
do{                                                   \
    (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD);  \
    (__HANDLE__)->Instance->CR1 |= (__CKD__);       \
    (__HANDLE__)->Init.ClockDivision = (__CKD__);   \
  } while(0)

Set the TIM Clock Division value on runtime without calling another time any Init function.

Parameters:
__HANDLE__ TIM handle.
__CKD__ specifies the clock division value. This parameter can be one of the following value:
  • TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
  • TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
  • TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
Return values:
None

Definition at line 1376 of file stm32wbxx_hal_tim.h.

#define __HAL_TIM_SET_COMPARE | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __COMPARE__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
   ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))

Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.

Parameters:
__HANDLE__ | TIM handle.
__CHANNEL__ TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
  • TIM_CHANNEL_5: TIM Channel 5 selected
  • TIM_CHANNEL_6: TIM Channel 6 selected
__COMPARE__ | specifies the Capture Compare register new value.
Return values:
None

Definition at line 1451 of file stm32wbxx_hal_tim.h.

#define __HAL_TIM_SET_COUNTER | ( | __HANDLE__,
 |  | __COUNTER__
 | ) | ((__HANDLE__)->Instance->CNT = (__COUNTER__))

Set the TIM Counter Register value on runtime.

Parameters:
__HANDLE__ | TIM handle.
__COUNTER__ | specifies the Counter register new value.
Return values:
None

Definition at line 1338 of file stm32wbxx_hal_tim.h.

#define __HAL_TIM_SET_ICPRESCALER | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __ICPSC__
 | ) |
Value:
do{                                                    \
    TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
    TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
  } while(0)

Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.

Parameters:
__HANDLE__ TIM handle.
__CHANNEL__ TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
__ICPSC__ specifies the Input Capture4 prescaler new value. This parameter can be one of the following values:
  • TIM_ICPSC_DIV1: no prescaler
  • TIM_ICPSC_DIV2: capture is done once every 2 events
  • TIM_ICPSC_DIV4: capture is done once every 4 events
  • TIM_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 1410 of file stm32wbxx_hal_tim.h.

#define __HAL_TIM_SET_PRESCALER | ( | __HANDLE__,
 |  | __PRESC__
 | ) | ((__HANDLE__)->Instance->PSC = (__PRESC__))

Set the TIM Prescaler on runtime.

Parameters:
__HANDLE__ | TIM handle.
__PRESC__ | specifies the Prescaler new value.
Return values:
None

Definition at line 1330 of file stm32wbxx_hal_tim.h.

#define __HAL_TIM_URS_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)

Reset the Update Request Source (URS) bit of the TIMx_CR1 register.

Parameters:
__HANDLE__ TIM handle.
Note:
When the URS bit of the TIMx_CR1 register is reset, any of the following events generate an update interrupt or DMA request (if enabled): _ Counter overflow underflow _ Setting the UG bit _ Update generation through the slave mode controller
Return values:
None

Definition at line 1593 of file stm32wbxx_hal_tim.h.

#define __HAL_TIM_URS_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)

Set the Update Request Source (URS) bit of the TIMx_CR1 register.

Parameters:
__HANDLE__ TIM handle.
Note:
When the URS bit of the TIMx_CR1 register is set, only counter overflow/underflow generates an update interrupt or DMA request (if enabled)
Return values:
None

Definition at line 1580 of file stm32wbxx_hal_tim.h.

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM Private Constants

Defines
TIM Private Constants
TIM

Defines

#define | TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL
#define | TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
#define | TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))

Define Documentation

#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))

Definition at line 1627 of file stm32wbxx_hal_tim.h.

#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))

Definition at line 1628 of file stm32wbxx_hal_tim.h.

#define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL

Definition at line 205 of file stm32wbxx_hal_tim.c.

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM Private Macros

Defines
TIM Private Macros
TIM

Defines

#define | IS_TIM_CLEARINPUT_SOURCE(__MODE__)
#define | IS_TIM_DMA_BASE(__BASE__)
#define | IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
#define | IS_TIM_COUNTER_MODE(__MODE__)
#define | IS_TIM_CLOCKDIVISION_DIV(__DIV__)
#define | IS_TIM_AUTORELOAD_PRELOAD(PRELOAD)
#define | IS_TIM_FAST_STATE(__STATE__)
#define | IS_TIM_OC_POLARITY(__POLARITY__)
#define | IS_TIM_OCN_POLARITY(__POLARITY__)
#define | IS_TIM_OCIDLE_STATE(__STATE__)
#define | IS_TIM_OCNIDLE_STATE(__STATE__)
#define | IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__)
#define | IS_TIM_IC_POLARITY(__POLARITY__)
#define | IS_TIM_IC_SELECTION(__SELECTION__)
#define | IS_TIM_IC_PRESCALER(__PRESCALER__)
#define | IS_TIM_OPM_MODE(__MODE__)
#define | IS_TIM_ENCODER_MODE(__MODE__)
#define | IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
#define | IS_TIM_CHANNELS(__CHANNEL__)
#define | IS_TIM_OPM_CHANNELS(__CHANNEL__)
#define | IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__)
#define | IS_TIM_CLOCKSOURCE(__CLOCK__)
#define | IS_TIM_CLOCKPOLARITY(__POLARITY__)
#define | IS_TIM_CLOCKPRESCALER(__PRESCALER__)
#define | IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define | IS_TIM_CLEARINPUT_POLARITY(__POLARITY__)
#define | IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__)
#define | IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define | IS_TIM_OSSR_STATE(__STATE__)
#define | IS_TIM_OSSI_STATE(__STATE__)
#define | IS_TIM_LOCK_LEVEL(__LEVEL__)
#define | IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
#define | IS_TIM_BREAK_STATE(__STATE__)
#define | IS_TIM_BREAK_POLARITY(__POLARITY__)
#define | IS_TIM_BREAK2_STATE(__STATE__)
#define | IS_TIM_BREAK2_POLARITY(__POLARITY__)
#define | IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__)
#define | IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
#define | IS_TIM_TRGO_SOURCE(__SOURCE__)
#define | IS_TIM_TRGO2_SOURCE(__SOURCE__)
#define | IS_TIM_MSM_STATE(__STATE__)
#define | IS_TIM_SLAVE_MODE(__MODE__)
#define | IS_TIM_PWM_MODE(__MODE__)
#define | IS_TIM_OC_MODE(__MODE__)
#define | IS_TIM_TRIGGER_SELECTION(__SELECTION__)
#define | IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__)
#define | IS_TIM_TRIGGERPOLARITY(__POLARITY__)
#define | IS_TIM_TRIGGERPRESCALER(__PRESCALER__)
#define | IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define | IS_TIM_TI1SELECTION(__TI1SELECTION__)
#define | IS_TIM_DMA_LENGTH(__LENGTH__)
#define | IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define | IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
#define | IS_TIM_BREAK_SYSTEM(__CONFIG__)
#define | IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__)
#define | TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__)
#define | TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__)
#define | TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
#define | TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__)

Define Documentation

#define IS_TIM_AUTOMATIC_OUTPUT_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
                                                  ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))

Definition at line 1798 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_AUTORELOAD_PRELOAD ( PRELOAD )
Value:
(((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
                                            ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))

Definition at line 1680 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_BREAK2_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
                                              ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))

Definition at line 1795 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK2_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_BREAK2_ENABLE) || \
                                            ((__STATE__) == TIM_BREAK2_DISABLE))

Definition at line 1792 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK_FILTER ( __BRKFILTER__ ) ((__BRKFILTER__) <= 0xFUL)

Definition at line 1783 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
                                             ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))

Definition at line 1789 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_BREAK_ENABLE) || \
                                            ((__STATE__) == TIM_BREAK_DISABLE))

Definition at line 1786 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK_SYSTEM ( __CONFIG__ )
Value:
(((__CONFIG__) == TIM_BREAK_SYSTEM_ECC)                  || \
                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD)                  || \
                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR)   || \
                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))

Definition at line 1910 of file stm32wbxx_hal_tim.h.

#define IS_TIM_CHANNELS ( __CHANNEL__ )
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_2) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_3) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_4) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_5) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_6) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_ALL))

Definition at line 1723 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), and TIM_CCxChannelCmd().

#define IS_TIM_CLEARINPUT_FILTER ( __ICFILTER__ ) ((__ICFILTER__) <= 0xFU)

Definition at line 1770 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_CLEARINPUT_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
                                                  ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))

Definition at line 1762 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_CLEARINPUT_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))

Definition at line 1765 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_CLEARINPUT_SOURCE ( __MODE__ )
Value:
(((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)      || \
                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1)    || \
                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2)    || \
                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))

Definition at line 1638 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_CLOCKDIVISION_DIV ( __DIV__ )
Value:
(((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV4))

Definition at line 1676 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_CLOCKFILTER ( __ICFILTER__ ) ((__ICFILTER__) <= 0xFU)

Definition at line 1760 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_CLOCKPOLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \
                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \
                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \
                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))

Definition at line 1749 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_CLOCKPRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))

Definition at line 1755 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_CLOCKSOURCE ( __CLOCK__ )
Value:
(((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))

Definition at line 1738 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_COMPLEMENTARY_CHANNELS ( __CHANNEL__ )
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) || \
                                                    ((__CHANNEL__) == TIM_CHANNEL_2) || \
                                                    ((__CHANNEL__) == TIM_CHANNEL_3))

Definition at line 1734 of file stm32wbxx_hal_tim.h.

#define IS_TIM_COUNTER_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_COUNTERMODE_UP)              || \
                                            ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \
                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))

Definition at line 1670 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_DEADTIME ( __DEADTIME__ ) ((__DEADTIME__) <= 0xFFU)

Definition at line 1908 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_DMA_BASE ( __BASE__ )
Value:
(((__BASE__) == TIM_DMABASE_CR1)   || \
                                   ((__BASE__) == TIM_DMABASE_CR2)   || \
                                   ((__BASE__) == TIM_DMABASE_SMCR)  || \
                                   ((__BASE__) == TIM_DMABASE_DIER)  || \
                                   ((__BASE__) == TIM_DMABASE_SR)    || \
                                   ((__BASE__) == TIM_DMABASE_EGR)   || \
                                   ((__BASE__) == TIM_DMABASE_CCMR1) || \
                                   ((__BASE__) == TIM_DMABASE_CCMR2) || \
                                   ((__BASE__) == TIM_DMABASE_CCER)  || \
                                   ((__BASE__) == TIM_DMABASE_CNT)   || \
                                   ((__BASE__) == TIM_DMABASE_PSC)   || \
                                   ((__BASE__) == TIM_DMABASE_ARR)   || \
                                   ((__BASE__) == TIM_DMABASE_RCR)   || \
                                   ((__BASE__) == TIM_DMABASE_CCR1)  || \
                                   ((__BASE__) == TIM_DMABASE_CCR2)  || \
                                   ((__BASE__) == TIM_DMABASE_CCR3)  || \
                                   ((__BASE__) == TIM_DMABASE_CCR4)  || \
                                   ((__BASE__) == TIM_DMABASE_BDTR)  || \
                                   ((__BASE__) == TIM_DMABASE_OR)    || \
                                   ((__BASE__) == TIM_DMABASE_CCMR3) || \
                                   ((__BASE__) == TIM_DMABASE_CCR5)  || \
                                   ((__BASE__) == TIM_DMABASE_CCR6)  || \
                                   ((__BASE__) == TIM_DMABASE_AF1)   || \
                                   ((__BASE__) == TIM_DMABASE_AF2))

Definition at line 1643 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), and HAL_TIM_DMABurst_WriteStart().

#define IS_TIM_DMA_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))

Definition at line 1887 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), and HAL_TIM_DMABurst_WriteStart().

#define IS_TIM_DMA_SOURCE ( __SOURCE__ ) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))

Definition at line 1721 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), and HAL_TIM_DMABurst_WriteStop().

#define IS_TIM_ENCODER_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_ENCODERMODE_TI1) || \
                                            ((__MODE__) == TIM_ENCODERMODE_TI2) || \
                                            ((__MODE__) == TIM_ENCODERMODE_TI12))

Definition at line 1717 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

#define IS_TIM_ENCODERINPUT_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING)   || \
                                                      ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))

Definition at line 1698 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

#define IS_TIM_EVENT_SOURCE ( __SOURCE__ ) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))

Definition at line 1668 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_GenerateEvent().

#define IS_TIM_FAST_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_OCFAST_DISABLE) || \
                                            ((__STATE__) == TIM_OCFAST_ENABLE))

Definition at line 1683 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_PWM_ConfigChannel().

#define IS_TIM_GROUPCH5 ( __OCREF__ ) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))

Definition at line 1801 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_GroupChannel5().

#define IS_TIM_IC_FILTER ( __ICFILTER__ ) ((__ICFILTER__) <= 0xFU)

Definition at line 1906 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), HAL_TIM_IC_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_IC_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \
                                            ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \
                                            ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))

Definition at line 1701 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_IC_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == TIM_ICPSC_DIV1) || \
                                            ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
                                            ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
                                            ((__PRESCALER__) == TIM_ICPSC_DIV8))

Definition at line 1709 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), HAL_TIM_IC_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_IC_SELECTION ( __SELECTION__ )
Value:
(((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
                                            ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
                                            ((__SELECTION__) == TIM_ICSELECTION_TRC))

Definition at line 1705 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), and HAL_TIM_IC_ConfigChannel().

#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION ( __SELECTION__ )
Value:
(((__SELECTION__) == TIM_TS_ITR0) || \
                                                               ((__SELECTION__) == TIM_TS_ITR1) || \
                                                               ((__SELECTION__) == TIM_TS_ITR2) || \
                                                               ((__SELECTION__) == TIM_TS_ITR3) || \
                                                               ((__SELECTION__) == TIM_TS_NONE))

Definition at line 1865 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), and HAL_TIMEx_ConfigCommutEvent_IT().

#define IS_TIM_LOCK_LEVEL ( __LEVEL__ )
Value:
(((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
                                            ((__LEVEL__) == TIM_LOCKLEVEL_1)   || \
                                            ((__LEVEL__) == TIM_LOCKLEVEL_2)   || \
                                            ((__LEVEL__) == TIM_LOCKLEVEL_3))

Definition at line 1778 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_MSM_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
                                          ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))

Definition at line 1830 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

#define IS_TIM_OC_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_OCMODE_TIMING)             || \
                                   ((__MODE__) == TIM_OCMODE_ACTIVE)             || \
                                   ((__MODE__) == TIM_OCMODE_INACTIVE)           || \
                                   ((__MODE__) == TIM_OCMODE_TOGGLE)             || \
                                   ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE)      || \
                                   ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)    || \
                                   ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
                                   ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))

Definition at line 1847 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel().

#define IS_TIM_OC_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
                                            ((__POLARITY__) == TIM_OCPOLARITY_LOW))

Definition at line 1686 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

#define IS_TIM_OCIDLE_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_OCIDLESTATE_SET) || \
                                            ((__STATE__) == TIM_OCIDLESTATE_RESET))

Definition at line 1692 of file stm32wbxx_hal_tim.h.

Referenced by TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), and TIM_OC4_SetConfig().

#define IS_TIM_OCN_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
                                            ((__POLARITY__) == TIM_OCNPOLARITY_LOW))

Definition at line 1689 of file stm32wbxx_hal_tim.h.

Referenced by TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), and TIM_OC3_SetConfig().

#define IS_TIM_OCNIDLE_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_OCNIDLESTATE_SET) || \
                                            ((__STATE__) == TIM_OCNIDLESTATE_RESET))

Definition at line 1695 of file stm32wbxx_hal_tim.h.

Referenced by TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), and TIM_OC3_SetConfig().

#define IS_TIM_OPM_CHANNELS ( __CHANNEL__ )
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) || \
                                            ((__CHANNEL__) == TIM_CHANNEL_2))

Definition at line 1731 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

#define IS_TIM_OPM_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_OPMODE_SINGLE) || \
                                            ((__MODE__) == TIM_OPMODE_REPETITIVE))

Definition at line 1714 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_Init().

#define IS_TIM_OSSI_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_OSSI_ENABLE) || \
                                            ((__STATE__) == TIM_OSSI_DISABLE))

Definition at line 1775 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_OSSR_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_OSSR_ENABLE) || \
                                            ((__STATE__) == TIM_OSSR_DISABLE))

Definition at line 1772 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_PWM_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_OCMODE_PWM1)               || \
                                   ((__MODE__) == TIM_OCMODE_PWM2)               || \
                                   ((__MODE__) == TIM_OCMODE_COMBINED_PWM1)      || \
                                   ((__MODE__) == TIM_OCMODE_COMBINED_PWM2)      || \
                                   ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1)    || \
                                   ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))

Definition at line 1840 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_PWM_ConfigChannel().

#define IS_TIM_SLAVE_MODE ( __MODE__ )
Value:
(((__MODE__) == TIM_SLAVEMODE_DISABLE)   || \
                                     ((__MODE__) == TIM_SLAVEMODE_RESET)     || \
                                     ((__MODE__) == TIM_SLAVEMODE_GATED)     || \
                                     ((__MODE__) == TIM_SLAVEMODE_TRIGGER)   || \
                                     ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
                                     ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))

Definition at line 1833 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchro(), and HAL_TIM_SlaveConfigSynchro_IT().

#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED ( __TRIGGER__ )
Value:
(((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \
                                                       ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))

Definition at line 1915 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Start_IT().

#define IS_TIM_TI1SELECTION ( __TI1SELECTION__ )
Value:
(((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
                                                ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))

Definition at line 1884 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_ConfigTI1Input().

#define IS_TIM_TRGO2_SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == TIM_TRGO2_RESET)                        || \
                                         ((__SOURCE__) == TIM_TRGO2_ENABLE)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_UPDATE)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC1)                          || \
                                         ((__SOURCE__) == TIM_TRGO2_OC1REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC2REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC4REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC5REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC6REF)                       || \
                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING)         || \
                                         ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING)         || \
                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING)  || \
                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
                                         ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING)  || \
                                         ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))

Definition at line 1812 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

#define IS_TIM_TRGO_SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == TIM_TRGO_RESET)  || \
                                        ((__SOURCE__) == TIM_TRGO_ENABLE) || \
                                        ((__SOURCE__) == TIM_TRGO_UPDATE) || \
                                        ((__SOURCE__) == TIM_TRGO_OC1)    || \
                                        ((__SOURCE__) == TIM_TRGO_OC1REF) || \
                                        ((__SOURCE__) == TIM_TRGO_OC2REF) || \
                                        ((__SOURCE__) == TIM_TRGO_OC3REF) || \
                                        ((__SOURCE__) == TIM_TRGO_OC4REF))

Definition at line 1803 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

#define IS_TIM_TRIGGER_SELECTION ( __SELECTION__ )
Value:
(((__SELECTION__) == TIM_TS_ITR0) || \
                                                 ((__SELECTION__) == TIM_TS_ITR1) || \
                                                 ((__SELECTION__) == TIM_TS_ITR2) || \
                                                 ((__SELECTION__) == TIM_TS_ITR3) || \
                                                 ((__SELECTION__) == TIM_TS_TI1F_ED) || \
                                                 ((__SELECTION__) == TIM_TS_TI1FP1) || \
                                                 ((__SELECTION__) == TIM_TS_TI2FP2) || \
                                                 ((__SELECTION__) == TIM_TS_ETRF))

Definition at line 1856 of file stm32wbxx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchro(), and HAL_TIM_SlaveConfigSynchro_IT().

#define IS_TIM_TRIGGERFILTER ( __ICFILTER__ ) ((__ICFILTER__) <= 0xFU)

Definition at line 1882 of file stm32wbxx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define IS_TIM_TRIGGERPOLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \
                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \
                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))

Definition at line 1871 of file stm32wbxx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define IS_TIM_TRIGGERPRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))

Definition at line 1877 of file stm32wbxx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define TIM_RESET_CAPTUREPOLARITY | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
   ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))

Definition at line 1936 of file stm32wbxx_hal_tim.h.

#define TIM_RESET_ICPRESCALERVALUE | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
   ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))

Definition at line 1924 of file stm32wbxx_hal_tim.h.

#define TIM_SET_CAPTUREPOLARITY | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __POLARITY__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
   ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))

Definition at line 1930 of file stm32wbxx_hal_tim.h.

#define TIM_SET_ICPRESCALERVALUE | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __ICPSC__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
   ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))

Definition at line 1918 of file stm32wbxx_hal_tim.h.

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Extended Timer Hall Sensor functions

Functions
Extended Timer Hall Sensor functions
TIM Extended Exported Functions

Timer Hall Sensor functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Init (TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
Initializes the TIM Hall Sensor Interface and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Hall Sensor interface.
__weak void | HAL_TIMEx_HallSensor_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Hall Sensor MSP.
__weak void | HAL_TIMEx_HallSensor_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Hall Sensor MSP.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Hall sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in DMA mode.

Detailed Description

Timer Hall Sensor functions.

  ==============================================================================
                      ##### Timer Hall Sensor functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure TIM HAL Sensor.
    (+) De-initialize TIM HAL Sensor.
    (+) Start the Hall Sensor Interface.
    (+) Stop the Hall Sensor Interface.
    (+) Start the Hall Sensor Interface and enable interrupts.
    (+) Stop the Hall Sensor Interface and disable interrupts.
    (+) Start the Hall Sensor Interface and enable DMA transfers.
    (+) Stop the Hall Sensor Interface and disable DMA transfers.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM Hall Sensor interface.

Parameters:
htim TIM Hall Sensor Interface handle
Return values:
HAL status

Definition at line 235 of file stm32wbxx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, HAL_TIMEx_HallSensor_MspDeInit(), __TIM_HandleTypeDef::HallSensor_MspDeInitCallback, __TIM_HandleTypeDef::Instance, and __TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_HallSensor_InitTypeDef * | sConfig
 | ) |  |

Initializes the TIM Hall Sensor Interface and initialize the associated handle.

Parameters:
htim | TIM Hall Sensor Interface handle
sConfig | TIM Hall Sensor configuration structure
Return values:
HAL status

Definition at line 143 of file stm32wbxx_hal_tim_ex.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_HallSensor_InitTypeDef::Commutation_Delay, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, HAL_TIMEx_HallSensor_MspInit(), __TIM_HandleTypeDef::HallSensor_MspInitCallback, TIM_HallSensor_InitTypeDef::IC1Filter, TIM_HallSensor_InitTypeDef::IC1Polarity, TIM_HallSensor_InitTypeDef::IC1Prescaler, __TIM_HandleTypeDef::Init, __TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, IS_TIM_IC_FILTER, IS_TIM_IC_POLARITY, IS_TIM_IC_PRESCALER, __TIM_HandleTypeDef::Lock, TIM_OC_InitTypeDef::OCFastMode, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, __TIM_HandleTypeDef::State, TIM_Base_SetConfig(), TIM_ICSELECTION_TRC, TIM_OC2_SetConfig(), TIM_OCFAST_DISABLE, TIM_OCIDLESTATE_RESET, TIM_OCMODE_PWM2, TIM_OCNIDLESTATE_RESET, TIM_OCNPOLARITY_HIGH, TIM_OCPOLARITY_HIGH, TIM_ResetCallback(), TIM_SLAVEMODE_RESET, TIM_TI1_SetConfig(), TIM_TRGO_OC2REF, and TIM_TS_TI1F_ED.

void HAL_TIMEx_HallSensor_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Hall Sensor MSP.

Parameters:
htim TIM Hall Sensor Interface handle
Return values:
None

Definition at line 286 of file stm32wbxx_hal_tim_ex.c.

Referenced by HAL_TIM_UnRegisterCallback(), and HAL_TIMEx_HallSensor_DeInit().

void HAL_TIMEx_HallSensor_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Hall Sensor MSP.

Parameters:
htim TIM Hall Sensor Interface handle
Return values:
None

Definition at line 271 of file stm32wbxx_hal_tim_ex.c.

Referenced by HAL_TIM_UnRegisterCallback(), and HAL_TIMEx_HallSensor_Init().

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start ( TIM_HandleTypeDef * htim )

Starts the TIM Hall Sensor Interface.

Parameters:
htim TIM Hall Sensor Interface handle
Return values:
HAL status

Definition at line 301 of file stm32wbxx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), and TIM_CHANNEL_1.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Hall Sensor Interface in DMA mode.

Parameters:
htim | TIM Hall Sensor Interface handle
pData | The destination Buffer address.
Length | The length of data to be transferred from TIM peripheral to memory.
Return values:
HAL status

Definition at line 405 of file stm32wbxx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, __TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_DMA_CC1, TIM_DMA_ID_CC1, TIM_DMACaptureCplt(), TIM_DMACaptureHalfCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT ( TIM_HandleTypeDef * htim )

Starts the TIM Hall Sensor Interface in interrupt mode.

Parameters:
htim TIM Hall Sensor Interface handle
Return values:
HAL status

Definition at line 349 of file stm32wbxx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_IT_CC1.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop ( TIM_HandleTypeDef * htim )

Stops the TIM Hall sensor Interface.

Parameters:
htim TIM Hall Sensor Interface handle
Return values:
HAL status

Definition at line 328 of file stm32wbxx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, assert_param, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), and TIM_CHANNEL_1.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA ( TIM_HandleTypeDef * htim )

Stops the TIM Hall Sensor Interface in DMA mode.

Parameters:
htim TIM Hall Sensor Interface handle
Return values:
HAL status

Definition at line 465 of file stm32wbxx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, HAL_DMA_Abort_IT(), __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_DMA_CC1, and TIM_DMA_ID_CC1.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT ( TIM_HandleTypeDef * htim )

Stops the TIM Hall Sensor Interface in interrupt mode.

Parameters:
htim TIM Hall Sensor Interface handle
Return values:
HAL status

Definition at line 379 of file stm32wbxx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, __TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_IT_CC1.

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Extended Timer Complementary Output Compare functions

Functions
Extended Timer Complementary Output Compare functions
TIM Extended Exported Functions

Timer Complementary Output Compare functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_OCN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode on the complementary output.

Detailed Description

Timer Complementary Output Compare functions.

  ==============================================================================
              ##### Timer Complementary Output Compare functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Start the Complementary Output Compare/PWM.
    (+) Stop the Complementary Output Compare/PWM.
    (+) Start the Complementary Output Compare/PWM and enable interrupts.
    (+) Stop the Complementary Output Compare/PWM and disable interrupts.
    (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
    (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_OCN_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation on the complementary output.

Parameters:
htim TIM Output Compare handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
Return values:
HAL status

Definition at line 521 of file stm32wbxx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCxN_ENABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Output Compare signal generation in DMA mode on the complementary output.

Parameters:
htim | TIM Output Compare handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
pData | The source Buffer address.
Length | The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 717 of file stm32wbxx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, __TIM_HandleTypeDef::State, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMADelayPulseCplt(), TIM_DMADelayPulseHalfCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.

Parameters:
htim TIM OC handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
Return values:
HAL status

Definition at line 585 of file stm32wbxx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, and TIM_IT_CC3.

HAL_StatusTypeDef HAL_TIMEx_OCN_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation on the complementary output.

Parameters:
htim TIM handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
Return values:
HAL status

Definition at line 556 of file stm32wbxx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, __TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in DMA mode on the complementary output.

Parameters:
htim TIM Output Compare handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
Return values:
HAL status

Definition at line 835 of file stm32wbxx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_DMA_Abort_IT(), HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::State, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, and TIM_DMA_ID_CC3.

HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.

Parameters:
htim TIM Output Compare handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
Return values:
HAL status

Definition at line 651 of file stm32wbxx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, __TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, and TIM_IT_CC3.

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Extended Timer Complementary PWM functions

Functions
Extended Timer Complementary PWM functions
TIM Extended Exported Functions

Timer Complementary PWM functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode on the complementary output.

Detailed Description

Timer Complementary PWM functions.

  ==============================================================================
                 ##### Timer Complementary PWM functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Start the Complementary PWM.
    (+) Stop the Complementary PWM.
    (+) Start the Complementary PWM and enable interrupts.
    (+) Stop the Complementary PWM and disable interrupts.
    (+) Start the Complementary PWM and enable DMA transfers.
    (+) Stop the Complementary PWM and disable DMA transfers.
    (+) Start the Complementary Input Capture measurement.
    (+) Stop the Complementary Input Capture.
    (+) Start the Complementary Input Capture and enable interrupts.
    (+) Stop the Complementary Input Capture and disable interrupts.
    (+) Start the Complementary Input Capture and enable DMA transfers.
    (+) Stop the Complementary Input Capture and disable DMA transfers.
    (+) Start the Complementary One Pulse generation.
    (+) Stop the Complementary One Pulse.
    (+) Start the Complementary One Pulse and enable interrupts.
    (+) Stop the Complementary One Pulse and disable interrupts.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_PWMN_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation on the complementary output.

Parameters:
htim TIM handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
Return values:
HAL status

Definition at line 930 of file stm32wbxx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCxN_ENABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM PWM signal generation in DMA mode on the complementary output.

Parameters:
htim | TIM handle
Channel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
pData | The source Buffer address.
Length | The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 1125 of file stm32wbxx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, __TIM_HandleTypeDef::State, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMADelayPulseCplt(), TIM_DMADelayPulseHalfCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation in interrupt mode on the complementary output.

Parameters:
htim TIM handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
Return values:
HAL status

Definition at line 993 of file stm32wbxx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_SLAVEMODE_TRIGGER_ENABLED, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, and TIM_IT_CC3.

HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation on the complementary output.

Parameters:
htim TIM handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
Return values:
HAL status

Definition at line 964 of file stm32wbxx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, __TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM PWM signal generation in DMA mode on the complementary output.

Parameters:
htim TIM handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
Return values:
HAL status

Definition at line 1242 of file stm32wbxx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_DMA_Abort_IT(), HAL_TIM_STATE_READY, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, __TIM_HandleTypeDef::State, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, and TIM_DMA_ID_CC3.

HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation in interrupt mode on the complementary output.

Parameters:
htim TIM handle
Channel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
Return values:
HAL status

Definition at line 1058 of file stm32wbxx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, __TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, and TIM_IT_CC3.

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Extended Timer Complementary One Pulse functions

Functions
Extended Timer Complementary One Pulse functions
TIM Extended Exported Functions

Timer Complementary One Pulse functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.

Detailed Description

Timer Complementary One Pulse functions.

  ==============================================================================
                ##### Timer Complementary One Pulse functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Start the Complementary One Pulse generation.
    (+) Stop the Complementary One Pulse.
    (+) Start the Complementary One Pulse and enable interrupts.
    (+) Stop the Complementary One Pulse and disable interrupts.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation on the complementary output.

Parameters:
htim TIM One Pulse handle
OutputChannel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1325 of file stm32wbxx_hal_tim_ex.c.

References __HAL_TIM_MOE_ENABLE, assert_param, __TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.

Parameters:
htim TIM One Pulse handle
OutputChannel TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1379 of file stm32wbxx_hal_tim_ex.c.

References __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, __TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_IT_CC1, and TIM_IT_CC2.

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation on the complementary output.

Parameters:
htim TIM One Pulse handle
OutputChannel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1350 of file stm32wbxx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, __TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.

Parameters:
htim TIM One Pulse handle
OutputChannel TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1410 of file stm32wbxx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, __TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_IT_CC1, and TIM_IT_CC2.

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Extended Peripheral Control functions

Functions
Extended Peripheral Control functions
TIM Extended Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutEvent (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutEvent_IT (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with interrupt.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutEvent_DMA (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with DMA.
HAL_StatusTypeDef | HAL_TIMEx_MasterConfigSynchronization (TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig)
Configures the TIM in master mode.
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakDeadTime (TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakInput (TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
Configures the break input source.
HAL_StatusTypeDef | HAL_TIMEx_RemapConfig (TIM_HandleTypeDef *htim, uint32_t Remap)
Configures the TIMx Remapping input capabilities.
HAL_StatusTypeDef | HAL_TIMEx_GroupChannel5 (TIM_HandleTypeDef *htim, uint32_t Channels)
Group channel 5 and channel 1, 2 or 3.

Detailed Description

Peripheral Control functions.

  ==============================================================================
                    ##### Peripheral Control functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
      (+) Configure the commutation event in case of use of the Hall sensor interface.
      (+) Configure Output channels for OC and PWM mode.

      (+) Configure Complementary channels, break features and dead time.
      (+) Configure Master synchronization.
      (+) Configure timer remapping capabilities.
      (+) Enable or disable channel grouping.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_BreakDeadTimeConfigTypeDef * | sBreakDeadTimeConfig
 | ) |  |

Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).

Parameters:
htim | TIM handle
sBreakDeadTimeConfig | pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that contains the BDTR Register configuration information for the TIM peripheral.
Note:
Interrupts can be generated when an active level is detected on the break input, the break 2 input or the system break input. Break interrupt can be enabled by calling the __HAL_TIM_ENABLE_IT macro.
Return values:
HAL status

Definition at line 1716 of file stm32wbxx_hal_tim_ex.c.

References assert_param, TIM_BreakDeadTimeConfigTypeDef::AutomaticOutput, TIM_BreakDeadTimeConfigTypeDef::Break2Filter, TIM_BreakDeadTimeConfigTypeDef::Break2Polarity, TIM_BreakDeadTimeConfigTypeDef::Break2State, TIM_BreakDeadTimeConfigTypeDef::BreakFilter, TIM_BreakDeadTimeConfigTypeDef::BreakPolarity, TIM_BreakDeadTimeConfigTypeDef::BreakState, TIM_BreakDeadTimeConfigTypeDef::DeadTime, __TIM_HandleTypeDef::Instance, IS_TIM_AUTOMATIC_OUTPUT_STATE, IS_TIM_BREAK2_POLARITY, IS_TIM_BREAK2_STATE, IS_TIM_BREAK_FILTER, IS_TIM_BREAK_POLARITY, IS_TIM_BREAK_STATE, IS_TIM_DEADTIME, IS_TIM_LOCK_LEVEL, IS_TIM_OSSI_STATE, IS_TIM_OSSR_STATE, TIM_BreakDeadTimeConfigTypeDef::LockLevel, TIM_BreakDeadTimeConfigTypeDef::OffStateIDLEMode, and TIM_BreakDeadTimeConfigTypeDef::OffStateRunMode.

HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BreakInput,
 |  | TIMEx_BreakInputConfigTypeDef * | sBreakInputConfig
 | ) |  |

Configures the break input source.

Parameters:
htim | TIM handle.
BreakInput Break input to configure This parameter can be one of the following values:
  • TIM_BREAKINPUT_BRK: Timer break input
  • TIM_BREAKINPUT_BRK2: Timer break 2 input
sBreakInputConfig | Break input source configuration
Return values:
HAL status

Definition at line 1780 of file stm32wbxx_hal_tim_ex.c.

References assert_param, TIMEx_BreakInputConfigTypeDef::Enable, __TIM_HandleTypeDef::Instance, IS_TIM_BREAKINPUT, IS_TIM_BREAKINPUTSOURCE, IS_TIM_BREAKINPUTSOURCE_POLARITY, IS_TIM_BREAKINPUTSOURCE_STATE, TIMEx_BreakInputConfigTypeDef::Polarity, TIMEx_BreakInputConfigTypeDef::Source, TIM_BREAKINPUT_BRK, TIM_BREAKINPUT_BRK2, TIM_BREAKINPUTSOURCE_BKIN, TIM_BREAKINPUTSOURCE_COMP1, and TIM_BREAKINPUTSOURCE_COMP2.

HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | InputTrigger,
 |  | uint32_t | CommutationSource
 | ) |  |

Configure the TIM commutation event sequence.

Note:
This function is mandatory to use the commutation event in order to update the configuration at each commutation detection on the TRGI input of the Timer, the typical use of this feature is with the use of another Timer(interface Timer) configured in Hall sensor interface, this interface Timer will generate the commutation at its TRGO output (connected to Timer used in this function) each time the TI1 of the Interface Timer detect a commutation at its input TI1.
Parameters:
htim TIM handle
InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor This parameter can be one of the following values:
  • TIM_TS_ITR0: Internal trigger 0 selected
  • TIM_TS_ITR1: Internal trigger 1 selected
  • TIM_TS_ITR2: Internal trigger 2 selected
  • TIM_TS_ITR3: Internal trigger 3 selected
  • TIM_TS_NONE: No trigger is needed
CommutationSource the Commutation Event source This parameter can be one of the following values:
  • TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
  • TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
Return values:
HAL status

Definition at line 1481 of file stm32wbxx_hal_tim_ex.c.

References __HAL_TIM_DISABLE_DMA, __HAL_TIM_DISABLE_IT, assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION, TIM_DMA_COM, TIM_IT_COM, TIM_TS_ITR0, TIM_TS_ITR1, TIM_TS_ITR2, and TIM_TS_ITR3.

HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | InputTrigger,
 |  | uint32_t | CommutationSource
 | ) |  |

Configure the TIM commutation event sequence with DMA.

Note:
This function is mandatory to use the commutation event in order to update the configuration at each commutation detection on the TRGI input of the Timer, the typical use of this feature is with the use of another Timer(interface Timer) configured in Hall sensor interface, this interface Timer will generate the commutation at its TRGO output (connected to Timer used in this function) each time the TI1 of the Interface Timer detect a commutation at its input TI1.
The user should configure the DMA in his own software, in This function only the COMDE bit is set
Parameters:
htim TIM handle
InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor This parameter can be one of the following values:
  • TIM_TS_ITR0: Internal trigger 0 selected
  • TIM_TS_ITR1: Internal trigger 1 selected
  • TIM_TS_ITR2: Internal trigger 2 selected
  • TIM_TS_ITR3: Internal trigger 3 selected
  • TIM_TS_NONE: No trigger is needed
CommutationSource the Commutation Event source This parameter can be one of the following values:
  • TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
  • TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
Return values:
HAL status

Definition at line 1594 of file stm32wbxx_hal_tim_ex.c.

References __HAL_TIM_DISABLE_IT, __HAL_TIM_ENABLE_DMA, assert_param, __TIM_HandleTypeDef::hdma, __TIM_HandleTypeDef::Instance, IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION, TIM_DMA_COM, TIM_DMA_ID_COMMUTATION, TIM_DMAError(), TIM_IT_COM, TIM_TS_ITR0, TIM_TS_ITR1, TIM_TS_ITR2, TIM_TS_ITR3, TIMEx_DMACommutationCplt(), TIMEx_DMACommutationHalfCplt(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | InputTrigger,
 |  | uint32_t | CommutationSource
 | ) |  |

Configure the TIM commutation event sequence with interrupt.

Note:
This function is mandatory to use the commutation event in order to update the configuration at each commutation detection on the TRGI input of the Timer, the typical use of this feature is with the use of another Timer(interface Timer) configured in Hall sensor interface, this interface Timer will generate the commutation at its TRGO output (connected to Timer used in this function) each time the TI1 of the Interface Timer detect a commutation at its input TI1.
Parameters:
htim TIM handle
InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor This parameter can be one of the following values:
  • TIM_TS_ITR0: Internal trigger 0 selected
  • TIM_TS_ITR1: Internal trigger 1 selected
  • TIM_TS_ITR2: Internal trigger 2 selected
  • TIM_TS_ITR3: Internal trigger 3 selected
  • TIM_TS_NONE: No trigger is needed
CommutationSource the Commutation Event source This parameter can be one of the following values:
  • TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
  • TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
Return values:
HAL status

Definition at line 1537 of file stm32wbxx_hal_tim_ex.c.

References __HAL_TIM_DISABLE_DMA, __HAL_TIM_ENABLE_IT, assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION, TIM_DMA_COM, TIM_IT_COM, TIM_TS_ITR0, TIM_TS_ITR1, TIM_TS_ITR2, and TIM_TS_ITR3.

HAL_StatusTypeDef HAL_TIMEx_GroupChannel5 | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channels
 | ) |  |

Group channel 5 and channel 1, 2 or 3.

Parameters:
htim | TIM handle.
Channels | specifies the reference signal(s) the OC5REF is combined with. This parameter can be any combination of the following values: TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
Return values:
HAL status

Definition at line 1992 of file stm32wbxx_hal_tim_ex.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_GROUPCH5, and __TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_MasterConfigTypeDef * | sMasterConfig
 | ) |  |

Configures the TIM in master mode.

Parameters:
htim | TIM handle.
sMasterConfig | pointer to a TIM_MasterConfigTypeDef structure that contains the selected trigger output (TRGO) and the Master/Slave mode.
Return values:
HAL status

Definition at line 1643 of file stm32wbxx_hal_tim_ex.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, __TIM_HandleTypeDef::Instance, IS_TIM_MSM_STATE, IS_TIM_TRGO2_SOURCE, IS_TIM_TRGO_SOURCE, TIM_MasterConfigTypeDef::MasterOutputTrigger, TIM_MasterConfigTypeDef::MasterOutputTrigger2, TIM_MasterConfigTypeDef::MasterSlaveMode, and __TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIMEx_RemapConfig | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Remap
 | ) |  |

Configures the TIMx Remapping input capabilities.

Parameters:
htim | TIM handle.
Remap | specifies the TIM remapping source. For TIM1, the parameter is a combination of 2 fields (field1 | field2):

field1 can have the following values:

  • TIM_TIM1_ETR_ADC1_GPIO: TIM1_ETR is connected to I/O
  • TIM_TIM1_ETR_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
  • TIM_TIM1_ETR_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
  • TIM_TIM1_ETR_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
  • TIM_TIM1_ETR_COMP1: TIM1_ETR is connected to COMP1 output (*)
  • TIM_TIM1_ETR_COMP2: TIM1_ETR is connected to COMP2 output (*) field2 can have the following values:
  • TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to I/O
  • TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output (*)

For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3):

field1 can have the following values:

  • TIM_TIM2_ITR1_NONE: No internal trigger on TIM2_ITR1
  • TIM_TIM2_ITR1_USB: TIM2_ITR1 is connected to USB SOF (*)

field2 can have the following values:

  • TIM_TIM2_ETR_GPIO: TIM2_ETR is connected to I/O
  • TIM_TIM2_ETR_LSE: TIM2_ETR is connected to LSE
  • TIM_TIM2_ETR_COMP1: TIM2_ETR is connected to COMP1 output (*)
  • TIM_TIM2_ETR_COMP2: TIM2_ETR is connected to COMP2 output (*)

field3 can have the following values:

  • TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to I/O
  • TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output (*)
  • TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output (*)
  • TIM_TIM2_TI4_COMP1_COMP2: TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output (*)

For TIM16, the parameter can have the following values:

  • TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to I/O
  • TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI
  • TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE
  • TIM_TIM16_TI1_RTC: TIM16 TI1 is connected to RTC wakeup interrupt

For TIM17, the parameter can have the following values:

  • TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to I/O
  • TIM_TIM17_TI1_MSI: TIM17 TI1 is connected to MSI (constraint: MSI clock < 1/4 TIM APB clock)
  • TIM_TIM17_TI1_HSE: TIM17 TI1 is connected to HSE div 32
  • TIM_TIM17_TI1_MCO: TIM17 TI1 is connected to MCO

(*) Value not defined in all devices.

Return values:
HAL status

Definition at line 1936 of file stm32wbxx_hal_tim_ex.c.

References assert_param, __TIM_HandleTypeDef::Instance, IS_TIM_REMAP, and TIM_GET_OR_MASK.

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Extended Callbacks functions

Functions
Extended Callbacks functions
TIM Extended Exported Functions

Extended Callbacks functions. More...

Functions

__weak void | HAL_TIMEx_CommutCallback (TIM_HandleTypeDef *htim)
Hall commutation changed callback in non-blocking mode.
__weak void | HAL_TIMEx_CommutHalfCpltCallback (TIM_HandleTypeDef *htim)
Hall commutation changed half complete callback in non-blocking mode.
__weak void | HAL_TIMEx_BreakCallback (TIM_HandleTypeDef *htim)
Hall Break detection callback in non-blocking mode.
__weak void | HAL_TIMEx_Break2Callback (TIM_HandleTypeDef *htim)
Hall Break2 detection callback in non blocking mode.

Detailed Description

Extended Callbacks functions.

  ==============================================================================
                    ##### Extended Callbacks functions #####
  ==============================================================================
  [..]
    This section provides Extended TIM callback functions:
    (+) Timer Commutation callback
    (+) Timer Break callback

Function Documentation

void HAL_TIMEx_Break2Callback ( TIM_HandleTypeDef * htim )

Hall Break2 detection callback in non blocking mode.

Parameters:
htim,: TIM handle
Return values:
None

Definition at line 2086 of file stm32wbxx_hal_tim_ex.c.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_UnRegisterCallback(), and TIM_ResetCallback().

void HAL_TIMEx_BreakCallback ( TIM_HandleTypeDef * htim )

Hall Break detection callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 2071 of file stm32wbxx_hal_tim_ex.c.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_UnRegisterCallback(), and TIM_ResetCallback().

void HAL_TIMEx_CommutCallback ( TIM_HandleTypeDef * htim )

Hall commutation changed callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 2042 of file stm32wbxx_hal_tim_ex.c.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_UnRegisterCallback(), TIM_ResetCallback(), and TIMEx_DMACommutationCplt().

void HAL_TIMEx_CommutHalfCpltCallback ( TIM_HandleTypeDef * htim )

Hall commutation changed half complete callback in non-blocking mode.

Parameters:
htim TIM handle
Return values:
None

Definition at line 2056 of file stm32wbxx_hal_tim_ex.c.

Referenced by HAL_TIM_UnRegisterCallback(), TIM_ResetCallback(), and TIMEx_DMACommutationHalfCplt().

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Extended Peripheral State functions

Functions
Extended Peripheral State functions
TIM Extended Exported Functions

Extended Peripheral State functions. More...

Functions

HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState (TIM_HandleTypeDef *htim)
Return the TIM Hall Sensor interface handle state.

Detailed Description

Extended Peripheral State functions.

  ==============================================================================
                ##### Extended Peripheral State functions #####
  ==============================================================================
  [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState ( TIM_HandleTypeDef * htim )

Return the TIM Hall Sensor interface handle state.

Parameters:
htim TIM Hall Sensor handle
Return values:
HAL state

Definition at line 2119 of file stm32wbxx_hal_tim_ex.c.

References __TIM_HandleTypeDef::State.

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIMEx Private Functions

Functions
TIMEx Private Functions
TIMEx

Functions

void | TIMEx_DMACommutationCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation callback.
void | TIMEx_DMACommutationHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation half complete callback.
static void | TIM_CCxNChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
Enables or disables the TIM Capture Compare Channel xN.

Function Documentation

static void TIM_CCxNChannelCmd | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ChannelNState
 | ) |  | [static]

Enables or disables the TIM Capture Compare Channel xN.

Parameters:
TIMx | to select the TIM peripheral
Channel specifies the TIM Channel This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1
  • TIM_CHANNEL_2: TIM Channel 2
  • TIM_CHANNEL_3: TIM Channel 3
ChannelNState | specifies the TIM Channel CCxNE bit new state. This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
Return values:
None

Definition at line 2188 of file stm32wbxx_hal_tim_ex.c.

Referenced by HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

void TIMEx_DMACommutationCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Commutation callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 2142 of file stm32wbxx_hal_tim_ex.c.

References __TIM_HandleTypeDef::CommutationCallback, HAL_TIM_STATE_READY, HAL_TIMEx_CommutCallback(), __TIM_HandleTypeDef::hdma, and __TIM_HandleTypeDef::State.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), and HAL_TIMEx_ConfigCommutEvent_DMA().

void TIMEx_DMACommutationHalfCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Commutation half complete callback.

Parameters:
hdma pointer to DMA handle.
Return values:
None

Definition at line 2161 of file stm32wbxx_hal_tim_ex.c.

References __TIM_HandleTypeDef::CommutationHalfCpltCallback, HAL_TIM_STATE_READY, HAL_TIMEx_CommutHalfCpltCallback(), __TIM_HandleTypeDef::hdma, and __TIM_HandleTypeDef::State.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), and HAL_TIMEx_ConfigCommutEvent_DMA().

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM_HallSensor_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_HallSensor_InitTypeDef Struct Reference
TIM Extended Exported Types

TIM Hall sensor Configuration Structure definition. More...

#include <stm32wbxx_hal_tim_ex.h>

Data Fields

uint32_t | IC1Polarity
uint32_t | IC1Prescaler
uint32_t | IC1Filter
uint32_t | Commutation_Delay

Detailed Description

TIM Hall sensor Configuration Structure definition.

Definition at line 48 of file stm32wbxx_hal_tim_ex.h.

Field Documentation

uint32_t TIM_HallSensor_InitTypeDef::Commutation_Delay

Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 59 of file stm32wbxx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

uint32_t TIM_HallSensor_InitTypeDef::IC1Filter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 56 of file stm32wbxx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

uint32_t TIM_HallSensor_InitTypeDef::IC1Polarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 50 of file stm32wbxx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

uint32_t TIM_HallSensor_InitTypeDef::IC1Prescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 53 of file stm32wbxx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_tim_ex.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIMEx_BreakInputConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIMEx_BreakInputConfigTypeDef Struct Reference
TIM Extended Exported Types

TIM Break/Break2 input configuration. More...

#include <stm32wbxx_hal_tim_ex.h>

Data Fields

uint32_t | Source
uint32_t | Enable
uint32_t | Polarity

Detailed Description

TIM Break/Break2 input configuration.

Definition at line 66 of file stm32wbxx_hal_tim_ex.h.

Field Documentation

uint32_t TIMEx_BreakInputConfigTypeDef::Enable

Specifies whether or not the break input source is enabled. This parameter can be a value of TIM Extended Break input source enabling

Definition at line 70 of file stm32wbxx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

uint32_t TIMEx_BreakInputConfigTypeDef::Polarity

Specifies the break input source polarity. This parameter can be a value of TIM Extended Break input polarity

Definition at line 72 of file stm32wbxx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

uint32_t TIMEx_BreakInputConfigTypeDef::Source

Specifies the source of the timer break input. This parameter can be a value of TIM Extended Break input source

Definition at line 68 of file stm32wbxx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_tim_ex.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM Extended Remapping

Defines
TIM Extended Remapping
TIM Extended Exported Constants

Defines

#define | TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is not connected to I/O */
#define | TIM_TIM1_ETR_ADC1_AWD1 TIM1_OR_ETR_ADC1_RMP_0 /* !< TIM1_ETR is connected to ADC1 AWD1 */
#define | TIM_TIM1_ETR_ADC1_AWD2 TIM1_OR_ETR_ADC1_RMP_1 /* !< TIM1_ETR is connected to ADC1 AWD2 */
#define | TIM_TIM1_ETR_ADC1_AWD3 (TIM1_OR_ETR_ADC1_RMP_0 | TIM1_OR_ETR_ADC1_RMP_1) /* !< TIM1_ETR is connected to ADC1 AWD3 */
#define | TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 output */
#define | TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 output */
#define | TIM_TIM1_TI1_GPIO 0x00000000U /* !< TIM1 Input capture 1 is connected to I/0 */
#define | TIM_TIM1_TI1_COMP1 TIM1_OR_TI1_RMP /* !< TIM1 Input capture 1is connected to COMP1 OUT */
#define | TIM_TIM2_ITR_NC 0x00000000U /* !< TIM2 Internal trigger ITR is not connected */
#define | TIM_TIM2_ITR_USB TIM2_OR_ITR1_RMP /* !< TIM2 Internal trigger ITR is connected to USBFS SOF */
#define | TIM_TIM2_ETR_GPIO 0x00000000U /* !< TIM2 External trigger ETR is connected to I/O */
#define | TIM_TIM2_ETR_LSE TIM2_OR_ETR_RMP /* !< TIM2 External trigger ETR is connected to LSE */
#define | TIM_TIM2_ETR_COMP1 TIM2_AF1_ETRSEL_0 /* !< TIM2_ETR is connected to COMP1 output */
#define | TIM_TIM2_ETR_COMP2 TIM2_AF1_ETRSEL_1 /* !< TIM2_ETR is connected to COMP2 output */
#define | TIM_TIM2_TI4_GPIO 0x00000000U /* !< TIM2_TI4 is connected to I/O */
#define | TIM_TIM2_TI4_COMP1 TIM2_OR_TI4_RMP_0 /* !< TIM2_TI4 is connected to COMP1 OUT */
#define | TIM_TIM2_TI4_COMP2 TIM2_OR_TI4_RMP_1 /* !< TIM2_TI4 is connected to COMP1 OUT */
#define | TIM_TIM2_TI4_COMP1_COMP2 (TIM2_OR_TI4_RMP_0 | TIM2_OR_TI4_RMP_1) /* !< TIM2_TI4 is connected to COMP1 and COMP2 OUT */
#define | TIM_TIM16_TI1_GPIO 0x00000000U /* !< TIM16_TI1 is connected to I/O */
#define | TIM_TIM16_TI1_LSI TIM16_OR_TI1_RMP_0 /* !< TIM16_TI1 is connected to LSI Clock */
#define | TIM_TIM16_TI1_LSE TIM16_OR_TI1_RMP_1 /* !< TIM16_TI1 is connected to LSE Clock */
#define | TIM_TIM16_TI1_RTC (TIM16_OR_TI1_RMP_0 | TIM16_OR_TI1_RMP_1) /* !< TIM16_TI1 is connected to RTC */
#define | TIM_TIM17_TI1_GPIO 0x00000000U /* !< TIM17_TI1 is connected to I/O */
#define | TIM_TIM17_TI1_MSI TIM17_OR_TI1_RMP_0 /* !< TIM17_TI1 is connected to MSI */
#define | TIM_TIM17_TI1_HSE TIM17_OR_TI1_RMP_1 /* !< TIM17_TI1 is connected to HSE/32 */
#define | TIM_TIM17_TI1_MCO (TIM17_OR_TI1_RMP_0 | TIM17_OR_TI1_RMP_1) /* !< TIM17_TI1 is connected to MCO */

Define Documentation

#define TIM_TIM16_TI1_GPIO 0x00000000U /* !< TIM16_TI1 is connected to I/O */

Definition at line 129 of file stm32wbxx_hal_tim_ex.h.

#define TIM_TIM16_TI1_LSE TIM16_OR_TI1_RMP_1 /* !< TIM16_TI1 is connected to LSE Clock */

Definition at line 131 of file stm32wbxx_hal_tim_ex.h.

#define TIM_TIM16_TI1_LSI TIM16_OR_TI1_RMP_0 /* !< TIM16_TI1 is connected to LSI Clock */

Definition at line 130 of file stm32wbxx_hal_tim_ex.h.

#define TIM_TIM16_TI1_RTC (TIM16_OR_TI1_RMP_0 | TIM16_OR_TI1_RMP_1) /* !< TIM16_TI1 is connected to RTC */

Definition at line 132 of file stm32wbxx_hal_tim_ex.h.

#define TIM_TIM17_TI1_GPIO 0x00000000U /* !< TIM17_TI1 is connected to I/O */

Definition at line 134 of file stm32wbxx_hal_tim_ex.h.

#define TIM_TIM17_TI1_HSE TIM17_OR_TI1_RMP_1 /* !< TIM17_TI1 is connected to HSE/32 */

Definition at line 136 of file stm32wbxx_hal_tim_ex.h.

#define TIM_TIM17_TI1_MCO (TIM17_OR_TI1_RMP_0 | TIM17_OR_TI1_RMP_1) /* !< TIM17_TI1 is connected to MCO */

Definition at line 137 of file stm32wbxx_hal_tim_ex.h.

#define TIM_TIM17_TI1_MSI TIM17_OR_TI1_RMP_0 /* !< TIM17_TI1 is connected to MSI */

Definition at line 135 of file stm32wbxx_hal_tim_ex.h.

#define TIM_TIM1_ETR_ADC1_AWD1 TIM1_OR_ETR_ADC1_RMP_0 /* !< TIM1_ETR is connected to ADC1 AWD1 */

Definition at line 91 of file stm32wbxx_hal_tim_ex.h.

#define TIM_TIM1_ETR_ADC1_AWD2 TIM1_OR_ETR_ADC1_RMP_1 /* !< TIM1_ETR is connected to ADC1 AWD2 */

Definition at line 92 of file stm32wbxx_hal_tim_ex.h.

#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_OR_ETR_ADC1_RMP_0 | TIM1_OR_ETR_ADC1_RMP_1) /* !< TIM1_ETR is connected to ADC1 AWD3 */

Definition at line 93 of file stm32wbxx_hal_tim_ex.h.

#define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 output */

Definition at line 95 of file stm32wbxx_hal_tim_ex.h.

#define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 output */

Definition at line 98 of file stm32wbxx_hal_tim_ex.h.

#define TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is not connected to I/O */

Definition at line 90 of file stm32wbxx_hal_tim_ex.h.

#define TIM_TIM1_TI1_COMP1 TIM1_OR_TI1_RMP /* !< TIM1 Input capture 1is connected to COMP1 OUT */

Definition at line 102 of file stm32wbxx_hal_tim_ex.h.

#define TIM_TIM1_TI1_GPIO 0x00000000U /* !< TIM1 Input capture 1 is connected to I/0 */

Definition at line 101 of file stm32wbxx_hal_tim_ex.h.

#define TIM_TIM2_ETR_COMP1 TIM2_AF1_ETRSEL_0 /* !< TIM2_ETR is connected to COMP1 output */

Definition at line 112 of file stm32wbxx_hal_tim_ex.h.

#define TIM_TIM2_ETR_COMP2 TIM2_AF1_ETRSEL_1 /* !< TIM2_ETR is connected to COMP2 output */

Definition at line 115 of file stm32wbxx_hal_tim_ex.h.

#define TIM_TIM2_ETR_GPIO 0x00000000U /* !< TIM2 External trigger ETR is connected to I/O */

Definition at line 109 of file stm32wbxx_hal_tim_ex.h.

#define TIM_TIM2_ETR_LSE TIM2_OR_ETR_RMP /* !< TIM2 External trigger ETR is connected to LSE */

Definition at line 110 of file stm32wbxx_hal_tim_ex.h.

#define TIM_TIM2_ITR_NC 0x00000000U /* !< TIM2 Internal trigger ITR is not connected */

Definition at line 104 of file stm32wbxx_hal_tim_ex.h.

#define TIM_TIM2_ITR_USB TIM2_OR_ITR1_RMP /* !< TIM2 Internal trigger ITR is connected to USBFS SOF */

Definition at line 106 of file stm32wbxx_hal_tim_ex.h.

#define TIM_TIM2_TI4_COMP1 TIM2_OR_TI4_RMP_0 /* !< TIM2_TI4 is connected to COMP1 OUT */

Definition at line 120 of file stm32wbxx_hal_tim_ex.h.

#define TIM_TIM2_TI4_COMP1_COMP2 (TIM2_OR_TI4_RMP_0 | TIM2_OR_TI4_RMP_1) /* !< TIM2_TI4 is connected to COMP1 and COMP2 OUT */

Definition at line 126 of file stm32wbxx_hal_tim_ex.h.

#define TIM_TIM2_TI4_COMP2 TIM2_OR_TI4_RMP_1 /* !< TIM2_TI4 is connected to COMP1 OUT */

Definition at line 123 of file stm32wbxx_hal_tim_ex.h.

#define TIM_TIM2_TI4_GPIO 0x00000000U /* !< TIM2_TI4 is connected to I/O */

Definition at line 118 of file stm32wbxx_hal_tim_ex.h.

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STM32WB55xx HAL User Manual: TIM Extended Break input

Defines
TIM Extended Break input
TIM Extended Exported Constants

Defines

#define | TIM_BREAKINPUT_BRK 0x00000001U /* !< Timer break input */
#define | TIM_BREAKINPUT_BRK2 0x00000002U /* !< Timer break2 input */

Define Documentation

#define TIM_BREAKINPUT_BRK 0x00000001U /* !< Timer break input */

Definition at line 145 of file stm32wbxx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define TIM_BREAKINPUT_BRK2 0x00000002U /* !< Timer break2 input */

Definition at line 146 of file stm32wbxx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM Extended Break input source

Defines
TIM Extended Break input source
TIM Extended Exported Constants

Defines

#define | TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */
#define | TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /* !< The COMP1 output is connected to the break input */
#define | TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /* !< The COMP2 output is connected to the break input */

Define Documentation

#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */

Definition at line 154 of file stm32wbxx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /* !< The COMP1 output is connected to the break input */

Definition at line 156 of file stm32wbxx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /* !< The COMP2 output is connected to the break input */

Definition at line 159 of file stm32wbxx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM Extended Break input source enabling

Defines
TIM Extended Break input source enabling
TIM Extended Exported Constants

Defines

#define | TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /* !< Break input source is disabled */
#define | TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /* !< Break input source is enabled */

Define Documentation

#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /* !< Break input source is disabled */

Definition at line 168 of file stm32wbxx_hal_tim_ex.h.

#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /* !< Break input source is enabled */

Definition at line 169 of file stm32wbxx_hal_tim_ex.h.

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STM32WB55xx HAL User Manual: TIM Extended Break input polarity

Defines
TIM Extended Break input polarity
TIM Extended Exported Constants

Defines

#define | TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /* !< Break input source is active low */
#define | TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /* !< Break input source is active_high */

Define Documentation

#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /* !< Break input source is active_high */

Definition at line 178 of file stm32wbxx_hal_tim_ex.h.

#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /* !< Break input source is active low */

Definition at line 177 of file stm32wbxx_hal_tim_ex.h.

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STM32WB55xx HAL User Manual: TIM Extended Exported Macros

TIM Extended Exported Macros
TIMEx
Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM Extended Private Macros

Defines
TIM Extended Private Macros
TIMEx

Defines

#define | TIM_GET_OR_MASK(__INSTANCE__)
#define | IS_TIM_REMAP(__INSTANCE__, __REMAP__)
#define | IS_TIM_BREAKINPUT(__BREAKINPUT__)
#define | IS_TIM_BREAKINPUTSOURCE(__SOURCE__)
#define | IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__)
#define | IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__)

Define Documentation

#define IS_TIM_BREAKINPUT ( __BREAKINPUT__ )
Value:
(((__BREAKINPUT__) == TIM_BREAKINPUT_BRK)  || \
           ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))

Definition at line 208 of file stm32wbxx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define IS_TIM_BREAKINPUTSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \
           ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
           ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2))

Definition at line 213 of file stm32wbxx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define IS_TIM_BREAKINPUTSOURCE_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW)  || \
             ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))

Definition at line 226 of file stm32wbxx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define IS_TIM_BREAKINPUTSOURCE_STATE ( __STATE__ )
Value:
(((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE)  || \
           ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))

Definition at line 222 of file stm32wbxx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakInput().

#define IS_TIM_REMAP | ( | __INSTANCE__,
 |  | __REMAP__
 | ) |
Value:
((((__INSTANCE__) == TIM1)  && ((((__REMAP__) & 0xFFFE3FECU) == 0x00000000U)))  \
        || (((__INSTANCE__) == TIM2)  && ((((__REMAP__) & 0xFFFE3FF0U) == 0x00000000U)))  \
        || (((__INSTANCE__) == TIM16) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U)))  \
        || (((__INSTANCE__) == TIM17) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))))

Definition at line 202 of file stm32wbxx_hal_tim_ex.h.

Referenced by HAL_TIMEx_RemapConfig().

#define TIM_GET_OR_MASK ( __INSTANCE__ )
Value:
(((__INSTANCE__) == TIM1) ? (TIM1_OR_ETR_ADC1_RMP | TIM1_OR_TI1_RMP) :               \
   ((__INSTANCE__) == TIM2) ? (TIM2_OR_TI4_RMP | TIM2_OR_ETR_RMP | TIM2_OR_ITR1_RMP) : \
   ((__INSTANCE__) == TIM16) ? TIM16_OR_TI1_RMP : TIM17_OR_TI1_RMP)

Definition at line 99 of file stm32wbxx_hal_tim_ex.c.

Referenced by HAL_TIMEx_RemapConfig().

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
TSC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_TSC_Init (TSC_HandleTypeDef *htsc)
Initialize the TSC peripheral according to the specified parameters in the TSC_InitTypeDef structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_TSC_DeInit (TSC_HandleTypeDef *htsc)
Deinitialize the TSC peripheral registers to their default reset values.
__weak void | HAL_TSC_MspInit (TSC_HandleTypeDef *htsc)
Initialize the TSC MSP.
__weak void | HAL_TSC_MspDeInit (TSC_HandleTypeDef *htsc)
DeInitialize the TSC MSP.
HAL_StatusTypeDef | HAL_TSC_RegisterCallback (TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID, pTSC_CallbackTypeDef pCallback)
Register a User TSC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_TSC_UnRegisterCallback (TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID)
Unregister an TSC Callback TSC callback is redirected to the weak predefined callback.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the TSC.
      (+) De-initialize the TSC.

Function Documentation

HAL_StatusTypeDef HAL_TSC_DeInit ( TSC_HandleTypeDef * htsc )

Deinitialize the TSC peripheral registers to their default reset values.

Parameters:
htsc TSC handle
Return values:
HAL status

Definition at line 346 of file stm32wbxx_hal_tsc.c.

References assert_param, HAL_TSC_MspDeInit(), HAL_TSC_STATE_BUSY, HAL_TSC_STATE_RESET, __TSC_HandleTypeDef::Instance, __TSC_HandleTypeDef::MspDeInitCallback, and __TSC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TSC_Init ( TSC_HandleTypeDef * htsc )

Initialize the TSC peripheral according to the specified parameters in the TSC_InitTypeDef structure and initialize the associated handle.

Parameters:
htsc TSC handle
Return values:
HAL status

Definition at line 241 of file stm32wbxx_hal_tsc.c.

References TSC_InitTypeDef::AcquisitionMode, assert_param, TSC_InitTypeDef::ChannelIOs, __TSC_HandleTypeDef::ConvCpltCallback, TSC_InitTypeDef::CTPulseHighLength, TSC_InitTypeDef::CTPulseLowLength, __TSC_HandleTypeDef::ErrorCallback, HAL_TSC_ConvCpltCallback(), HAL_TSC_ErrorCallback(), HAL_TSC_MspInit(), HAL_TSC_STATE_BUSY, HAL_TSC_STATE_READY, HAL_TSC_STATE_RESET, __TSC_HandleTypeDef::Init, __TSC_HandleTypeDef::Instance, TSC_InitTypeDef::IODefaultMode, IS_TSC_ACQ_MODE, IS_TSC_CTPH, IS_TSC_CTPL, IS_TSC_GROUP, IS_TSC_IODEF, IS_TSC_MCE_IT, IS_TSC_MCV, IS_TSC_PG_PRESC, IS_TSC_SS, IS_TSC_SS_PRESC, IS_TSC_SSD, IS_TSC_SYNC_POL, __TSC_HandleTypeDef::Lock, TSC_InitTypeDef::MaxCountInterrupt, TSC_InitTypeDef::MaxCountValue, __TSC_HandleTypeDef::MspInitCallback, TSC_InitTypeDef::PulseGeneratorPrescaler, TSC_InitTypeDef::SamplingIOs, TSC_InitTypeDef::ShieldIOs, TSC_InitTypeDef::SpreadSpectrum, TSC_InitTypeDef::SpreadSpectrumDeviation, TSC_InitTypeDef::SpreadSpectrumPrescaler, __TSC_HandleTypeDef::State, TSC_InitTypeDef::SynchroPinPolarity, TSC_extract_groups(), TSC_FLAG_EOA, TSC_FLAG_MCE, TSC_IT_EOA, and TSC_IT_MCE.

void HAL_TSC_MspDeInit ( TSC_HandleTypeDef * htsc )

DeInitialize the TSC MSP.

Parameters:
htsc Pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
Return values:
None

Definition at line 405 of file stm32wbxx_hal_tsc.c.

Referenced by HAL_TSC_DeInit(), and HAL_TSC_UnRegisterCallback().

void HAL_TSC_MspInit ( TSC_HandleTypeDef * htsc )

Initialize the TSC MSP.

Parameters:
htsc Pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
Return values:
None

Definition at line 389 of file stm32wbxx_hal_tsc.c.

Referenced by HAL_TSC_Init(), and HAL_TSC_UnRegisterCallback().

HAL_StatusTypeDef HAL_TSC_RegisterCallback | ( | TSC_HandleTypeDef * | htsc,
 |  | HAL_TSC_CallbackIDTypeDef | CallbackID,
 |  | pTSC_CallbackTypeDef | pCallback
 | ) |  |

Register a User TSC Callback To be used instead of the weak predefined callback.

Parameters:
htsc | Pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_TSC_CONV_COMPLETE_CB_ID Conversion completed callback ID
  • HAL_TSC_ERROR_CB_ID Error callback ID
  • HAL_TSC_MSPINIT_CB_ID MspInit callback ID
  • HAL_TSC_MSPDEINIT_CB_ID MspDeInit callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 430 of file stm32wbxx_hal_tsc.c.

References __TSC_HandleTypeDef::ConvCpltCallback, __TSC_HandleTypeDef::ErrorCallback, __TSC_HandleTypeDef::ErrorCode, HAL_TSC_CONV_COMPLETE_CB_ID, HAL_TSC_ERROR_CB_ID, HAL_TSC_ERROR_INVALID_CALLBACK, HAL_TSC_MSPDEINIT_CB_ID, HAL_TSC_MSPINIT_CB_ID, HAL_TSC_STATE_READY, HAL_TSC_STATE_RESET, __TSC_HandleTypeDef::MspDeInitCallback, __TSC_HandleTypeDef::MspInitCallback, and __TSC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TSC_UnRegisterCallback | ( | TSC_HandleTypeDef * | htsc,
 |  | HAL_TSC_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an TSC Callback TSC callback is redirected to the weak predefined callback.

Parameters:
htsc Pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
CallbackID ID of the callback to be unregistered This parameter can be one of the following values: This parameter can be one of the following values:
  • HAL_TSC_CONV_COMPLETE_CB_ID Conversion completed callback ID
  • HAL_TSC_ERROR_CB_ID Error callback ID
  • HAL_TSC_MSPINIT_CB_ID MspInit callback ID
  • HAL_TSC_MSPDEINIT_CB_ID MspDeInit callback ID
Return values:
HAL status

Definition at line 522 of file stm32wbxx_hal_tsc.c.

References __TSC_HandleTypeDef::ConvCpltCallback, __TSC_HandleTypeDef::ErrorCallback, __TSC_HandleTypeDef::ErrorCode, HAL_TSC_CONV_COMPLETE_CB_ID, HAL_TSC_ConvCpltCallback(), HAL_TSC_ERROR_CB_ID, HAL_TSC_ERROR_INVALID_CALLBACK, HAL_TSC_ErrorCallback(), HAL_TSC_MspDeInit(), HAL_TSC_MSPDEINIT_CB_ID, HAL_TSC_MspInit(), HAL_TSC_MSPINIT_CB_ID, HAL_TSC_STATE_READY, HAL_TSC_STATE_RESET, __TSC_HandleTypeDef::MspDeInitCallback, __TSC_HandleTypeDef::MspInitCallback, and __TSC_HandleTypeDef::State.

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
TSC Exported Functions

Input and Output operation functions. More...

Functions

HAL_StatusTypeDef | HAL_TSC_Start (TSC_HandleTypeDef *htsc)
Start the acquisition.
HAL_StatusTypeDef | HAL_TSC_Start_IT (TSC_HandleTypeDef *htsc)
Start the acquisition in interrupt mode.
HAL_StatusTypeDef | HAL_TSC_Stop (TSC_HandleTypeDef *htsc)
Stop the acquisition previously launched in polling mode.
HAL_StatusTypeDef | HAL_TSC_Stop_IT (TSC_HandleTypeDef *htsc)
Stop the acquisition previously launched in interrupt mode.
HAL_StatusTypeDef | HAL_TSC_PollForAcquisition (TSC_HandleTypeDef *htsc)
Start acquisition and wait until completion.
TSC_GroupStatusTypeDef | HAL_TSC_GroupGetStatus (TSC_HandleTypeDef *htsc, uint32_t gx_index)
Get the acquisition status for a group.
uint32_t | HAL_TSC_GroupGetValue (TSC_HandleTypeDef *htsc, uint32_t gx_index)
Get the acquisition measure for a group.

Detailed Description

Input and Output operation functions.

 ===============================================================================
             ##### IO Operation functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Start acquisition in polling mode.
      (+) Start acquisition in interrupt mode.
      (+) Stop conversion in polling mode.
      (+) Stop conversion in interrupt mode.
      (+) Poll for acquisition completed.
      (+) Get group acquisition status.
      (+) Get group acquisition value.

Function Documentation

TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus | ( | TSC_HandleTypeDef * | htsc,
 |  | uint32_t | gx_index
 | ) |  |

Get the acquisition status for a group.

Parameters:
htsc | Pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
gx_index | Index of the group
Return values:
Group status

Definition at line 819 of file stm32wbxx_hal_tsc.c.

References __HAL_TSC_GET_GROUP_STATUS, assert_param, __TSC_HandleTypeDef::Instance, and IS_TSC_GROUP_INDEX.

uint32_t HAL_TSC_GroupGetValue | ( | TSC_HandleTypeDef * | htsc,
 |  | uint32_t | gx_index
 | ) |  |

Get the acquisition measure for a group.

Parameters:
htsc | Pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
gx_index | Index of the group
Return values:
Acquisition measure

Definition at line 836 of file stm32wbxx_hal_tsc.c.

References assert_param, __TSC_HandleTypeDef::Instance, and IS_TSC_GROUP_INDEX.

HAL_StatusTypeDef HAL_TSC_PollForAcquisition ( TSC_HandleTypeDef * htsc )

Start acquisition and wait until completion.

Note:
There is no need of a timeout parameter as the max count error is already managed by the TSC peripheral.
Parameters:
htsc Pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
Return values:
HAL state

Definition at line 792 of file stm32wbxx_hal_tsc.c.

References assert_param, HAL_TSC_GetState(), HAL_TSC_STATE_BUSY, and __TSC_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_TSC_Start ( TSC_HandleTypeDef * htsc )

Start the acquisition.

Parameters:
htsc Pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
Return values:
HAL status

Definition at line 624 of file stm32wbxx_hal_tsc.c.

References __HAL_TSC_CLEAR_FLAG, __HAL_TSC_DISABLE_IT, __HAL_TSC_SET_IODEF_INFLOAT, __HAL_TSC_SET_IODEF_OUTPPLOW, __HAL_TSC_START_ACQ, assert_param, HAL_TSC_STATE_BUSY, __TSC_HandleTypeDef::Init, __TSC_HandleTypeDef::Instance, TSC_InitTypeDef::IODefaultMode, __TSC_HandleTypeDef::State, TSC_FLAG_EOA, TSC_FLAG_MCE, TSC_IODEF_OUT_PP_LOW, TSC_IT_EOA, and TSC_IT_MCE.

HAL_StatusTypeDef HAL_TSC_Start_IT ( TSC_HandleTypeDef * htsc )

Start the acquisition in interrupt mode.

Parameters:
htsc Pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
Return values:
HAL status.

Definition at line 667 of file stm32wbxx_hal_tsc.c.

References __HAL_TSC_CLEAR_FLAG, __HAL_TSC_DISABLE_IT, __HAL_TSC_ENABLE_IT, __HAL_TSC_SET_IODEF_INFLOAT, __HAL_TSC_SET_IODEF_OUTPPLOW, __HAL_TSC_START_ACQ, assert_param, HAL_TSC_STATE_BUSY, __TSC_HandleTypeDef::Init, __TSC_HandleTypeDef::Instance, TSC_InitTypeDef::IODefaultMode, IS_TSC_MCE_IT, TSC_InitTypeDef::MaxCountInterrupt, __TSC_HandleTypeDef::State, TSC_FLAG_EOA, TSC_FLAG_MCE, TSC_IODEF_OUT_PP_LOW, TSC_IT_EOA, and TSC_IT_MCE.

HAL_StatusTypeDef HAL_TSC_Stop ( TSC_HandleTypeDef * htsc )

Stop the acquisition previously launched in polling mode.

Parameters:
htsc Pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
Return values:
HAL status

Definition at line 721 of file stm32wbxx_hal_tsc.c.

References __HAL_TSC_CLEAR_FLAG, __HAL_TSC_SET_IODEF_OUTPPLOW, __HAL_TSC_STOP_ACQ, assert_param, HAL_TSC_STATE_READY, __TSC_HandleTypeDef::Instance, __TSC_HandleTypeDef::State, TSC_FLAG_EOA, and TSC_FLAG_MCE.

HAL_StatusTypeDef HAL_TSC_Stop_IT ( TSC_HandleTypeDef * htsc )

Stop the acquisition previously launched in interrupt mode.

Parameters:
htsc Pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
Return values:
HAL status

Definition at line 754 of file stm32wbxx_hal_tsc.c.

References __HAL_TSC_CLEAR_FLAG, __HAL_TSC_DISABLE_IT, __HAL_TSC_SET_IODEF_OUTPPLOW, __HAL_TSC_STOP_ACQ, assert_param, HAL_TSC_STATE_READY, __TSC_HandleTypeDef::Instance, __TSC_HandleTypeDef::State, TSC_FLAG_EOA, TSC_FLAG_MCE, TSC_IT_EOA, and TSC_IT_MCE.

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
TSC Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_TSC_IOConfig (TSC_HandleTypeDef *htsc, TSC_IOConfigTypeDef *config)
Configure TSC IOs.
HAL_StatusTypeDef | HAL_TSC_IODischarge (TSC_HandleTypeDef *htsc, FunctionalState choice)
Discharge TSC IOs.

Detailed Description

Peripheral Control functions.

 ===============================================================================
             ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure TSC IOs
      (+) Discharge TSC IOs

Function Documentation

HAL_StatusTypeDef HAL_TSC_IOConfig | ( | TSC_HandleTypeDef * | htsc,
 |  | TSC_IOConfigTypeDef * | config
 | ) |  |

Configure TSC IOs.

Parameters:
htsc | Pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
config | Pointer to the configuration structure.
Return values:
HAL status

Definition at line 871 of file stm32wbxx_hal_tsc.c.

References __HAL_TSC_STOP_ACQ, assert_param, TSC_IOConfigTypeDef::ChannelIOs, __TSC_HandleTypeDef::Instance, IS_TSC_GROUP, TSC_IOConfigTypeDef::SamplingIOs, TSC_IOConfigTypeDef::ShieldIOs, and TSC_extract_groups().

HAL_StatusTypeDef HAL_TSC_IODischarge | ( | TSC_HandleTypeDef * | htsc,
 |  | FunctionalState | choice
 | ) |  |

Discharge TSC IOs.

Parameters:
htsc | Pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
choice | This parameter can be set to ENABLE or DISABLE.
Return values:
HAL status

Definition at line 911 of file stm32wbxx_hal_tsc.c.

References __HAL_TSC_SET_IODEF_INFLOAT, __HAL_TSC_SET_IODEF_OUTPPLOW, assert_param, and __TSC_HandleTypeDef::Instance.

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
TSC Exported Functions

Peripheral State and Errors functions. More...

Functions

HAL_TSC_StateTypeDef HAL_TSC_GetState (TSC_HandleTypeDef *htsc)
Return the TSC handle state.

Detailed Description

Peripheral State and Errors functions.

 ===============================================================================
            ##### State and Errors functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Get TSC state.

Function Documentation

HAL_TSC_StateTypeDef HAL_TSC_GetState ( TSC_HandleTypeDef * htsc )

Return the TSC handle state.

Parameters:
htsc Pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
Return values:
HAL state

Definition at line 960 of file stm32wbxx_hal_tsc.c.

References __HAL_TSC_GET_FLAG, assert_param, HAL_TSC_STATE_BUSY, HAL_TSC_STATE_ERROR, HAL_TSC_STATE_READY, __TSC_HandleTypeDef::Instance, __TSC_HandleTypeDef::State, TSC_FLAG_EOA, and TSC_FLAG_MCE.

Referenced by HAL_TSC_PollForAcquisition().

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IRQ Handler and Callbacks

Functions
IRQ Handler and Callbacks
TSC Exported Functions

Functions

void | HAL_TSC_IRQHandler (TSC_HandleTypeDef *htsc)
Handle TSC interrupt request.
__weak void | HAL_TSC_ConvCpltCallback (TSC_HandleTypeDef *htsc)
Acquisition completed callback in non-blocking mode.
__weak void | HAL_TSC_ErrorCallback (TSC_HandleTypeDef *htsc)
Error callback in non-blocking mode.

Function Documentation

void HAL_TSC_ConvCpltCallback ( TSC_HandleTypeDef * htsc )

Acquisition completed callback in non-blocking mode.

Parameters:
htsc Pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
Return values:
None

Definition at line 1047 of file stm32wbxx_hal_tsc.c.

Referenced by HAL_TSC_Init(), HAL_TSC_IRQHandler(), and HAL_TSC_UnRegisterCallback().

void HAL_TSC_ErrorCallback ( TSC_HandleTypeDef * htsc )

Error callback in non-blocking mode.

Parameters:
htsc Pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
Return values:
None

Definition at line 1063 of file stm32wbxx_hal_tsc.c.

Referenced by HAL_TSC_Init(), HAL_TSC_IRQHandler(), and HAL_TSC_UnRegisterCallback().

void HAL_TSC_IRQHandler ( TSC_HandleTypeDef * htsc )

Handle TSC interrupt request.

Parameters:
htsc Pointer to a TSC_HandleTypeDef structure that contains the configuration information for the specified TSC.
Return values:
None

Definition at line 1002 of file stm32wbxx_hal_tsc.c.

References __HAL_TSC_CLEAR_FLAG, __HAL_TSC_GET_FLAG, assert_param, __TSC_HandleTypeDef::ConvCpltCallback, __TSC_HandleTypeDef::ErrorCallback, HAL_TSC_ConvCpltCallback(), HAL_TSC_ErrorCallback(), HAL_TSC_STATE_ERROR, HAL_TSC_STATE_READY, __TSC_HandleTypeDef::Instance, __TSC_HandleTypeDef::State, TSC_FLAG_EOA, and TSC_FLAG_MCE.

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TSC Private Functions

Functions
TSC Private Functions
TSC

Functions

static uint32_t TSC_extract_groups (uint32_t iomask)
Utility function used to set the acquired groups mask.

Function Documentation

static uint32_t TSC_extract_groups ( uint32_t iomask ) [static]

Utility function used to set the acquired groups mask.

Parameters:
iomask Channels IOs mask
Return values:
Acquired groups mask

Definition at line 1091 of file stm32wbxx_hal_tsc.c.

References TSC_NB_OF_GROUPS.

Referenced by HAL_TSC_Init(), and HAL_TSC_IOConfig().

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TSC Exported Types

Data Structures | Typedefs | Enumerations
TSC Exported Types
TSC

Data Structures

struct | TSC_InitTypeDef
TSC init structure definition. More...
struct | TSC_IOConfigTypeDef
TSC IOs configuration structure definition. More...
struct | __TSC_HandleTypeDef
TSC handle Structure definition. More...

Typedefs

typedef struct __TSC_HandleTypeDef | TSC_HandleTypeDef
TSC handle Structure definition.
typedef void(* | pTSC_CallbackTypeDef )(TSC_HandleTypeDef *htsc)
HAL TSC Callback pointer definition.

Enumerations

enum | HAL_TSC_StateTypeDef { HAL_TSC_STATE_RESET = 0x00UL, HAL_TSC_STATE_READY = 0x01UL, HAL_TSC_STATE_BUSY = 0x02UL, HAL_TSC_STATE_ERROR = 0x03UL }
TSC state structure definition. More...
enum | TSC_GroupStatusTypeDef { TSC_GROUP_ONGOING = 0x00UL, TSC_GROUP_COMPLETED = 0x01UL }
TSC group status structure definition. More...
enum {
TSC_GROUP1_IDX = 0x00UL, TSC_GROUP2_IDX, TSC_GROUP3_IDX, TSC_GROUP4_IDX,
TSC_GROUP5_IDX, TSC_GROUP6_IDX, TSC_GROUP7_IDX, TSC_NB_OF_GROUPS
}
enum | HAL_TSC_CallbackIDTypeDef { HAL_TSC_CONV_COMPLETE_CB_ID = 0x00UL, HAL_TSC_ERROR_CB_ID = 0x01UL, HAL_TSC_MSPINIT_CB_ID = 0x02UL, HAL_TSC_MSPDEINIT_CB_ID = 0x03UL }
HAL TSC Callback ID enumeration definition. More...

Typedef Documentation

typedef void(* pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc)

HAL TSC Callback pointer definition.

pointer to an TSC callback function

Definition at line 158 of file stm32wbxx_hal_tsc.h.

typedef struct __TSC_HandleTypeDef TSC_HandleTypeDef

TSC handle Structure definition.

Enumeration Type Documentation

anonymous enum
Enumerator:
TSC_GROUP1_IDX
TSC_GROUP2_IDX
TSC_GROUP3_IDX
TSC_GROUP4_IDX
TSC_GROUP5_IDX
TSC_GROUP6_IDX
TSC_GROUP7_IDX
TSC_NB_OF_GROUPS

Definition at line 129 of file stm32wbxx_hal_tsc.h.

enum HAL_TSC_CallbackIDTypeDef

HAL TSC Callback ID enumeration definition.

Enumerator:
HAL_TSC_CONV_COMPLETE_CB_ID

TSC Conversion completed callback ID

HAL_TSC_ERROR_CB_ID

TSC Error callback ID

HAL_TSC_MSPINIT_CB_ID

TSC Msp Init callback ID

HAL_TSC_MSPDEINIT_CB_ID

TSC Msp DeInit callback ID

Definition at line 145 of file stm32wbxx_hal_tsc.h.

enum HAL_TSC_StateTypeDef

TSC state structure definition.

Enumerator:
HAL_TSC_STATE_RESET

TSC registers have their reset value

HAL_TSC_STATE_READY

TSC registers are initialized or acquisition is completed with success

HAL_TSC_STATE_BUSY

TSC initialization or acquisition is on-going

HAL_TSC_STATE_ERROR

Acquisition is completed with max count error

Definition at line 49 of file stm32wbxx_hal_tsc.h.

enum TSC_GroupStatusTypeDef

TSC group status structure definition.

Enumerator:
TSC_GROUP_ONGOING

Acquisition on group is on-going or not started

TSC_GROUP_COMPLETED

Acquisition on group is completed with success (no max count error)

Definition at line 60 of file stm32wbxx_hal_tsc.h.

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TSC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TSC_InitTypeDef Struct Reference
TSC Exported Types

TSC init structure definition. More...

#include <stm32wbxx_hal_tsc.h>

Data Fields

uint32_t | CTPulseHighLength
uint32_t | CTPulseLowLength
FunctionalState | SpreadSpectrum
uint32_t | SpreadSpectrumDeviation
uint32_t | SpreadSpectrumPrescaler
uint32_t | PulseGeneratorPrescaler
uint32_t | MaxCountValue
uint32_t | IODefaultMode
uint32_t | SynchroPinPolarity
uint32_t | AcquisitionMode
FunctionalState | MaxCountInterrupt
uint32_t | ChannelIOs
uint32_t | ShieldIOs
uint32_t | SamplingIOs

Detailed Description

TSC init structure definition.

Definition at line 69 of file stm32wbxx_hal_tsc.h.

Field Documentation

uint32_t TSC_InitTypeDef::AcquisitionMode

Acquisition mode This parameter can be a value of Acquisition Mode

Definition at line 89 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_Init().

uint32_t TSC_InitTypeDef::ChannelIOs

Channel IOs mask

Definition at line 93 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_Init().

uint32_t TSC_InitTypeDef::CTPulseHighLength

Charge-transfer high pulse length This parameter can be a value of CTPulse High Length

Definition at line 71 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_Init().

uint32_t TSC_InitTypeDef::CTPulseLowLength

Charge-transfer low pulse length This parameter can be a value of CTPulse Low Length

Definition at line 73 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_Init().

uint32_t TSC_InitTypeDef::IODefaultMode

IO default mode This parameter can be a value of IO Default Mode

Definition at line 85 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_Init(), HAL_TSC_Start(), and HAL_TSC_Start_IT().

FunctionalState TSC_InitTypeDef::MaxCountInterrupt

Max count interrupt activation This parameter can be set to ENABLE or DISABLE.

Definition at line 91 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_Init(), and HAL_TSC_Start_IT().

uint32_t TSC_InitTypeDef::MaxCountValue

Max count value This parameter can be a value of Max Count Value

Definition at line 83 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_Init().

uint32_t TSC_InitTypeDef::PulseGeneratorPrescaler

Pulse generator prescaler This parameter can be a value of Pulse Generator Prescaler

Definition at line 81 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_Init().

uint32_t TSC_InitTypeDef::SamplingIOs

Sampling IOs mask

Definition at line 95 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_Init().

uint32_t TSC_InitTypeDef::ShieldIOs

Shield IOs mask

Definition at line 94 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_Init().

FunctionalState TSC_InitTypeDef::SpreadSpectrum

Spread spectrum activation This parameter can be set to ENABLE or DISABLE.

Definition at line 75 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_Init().

uint32_t TSC_InitTypeDef::SpreadSpectrumDeviation

Spread spectrum deviation This parameter must be a number between Min_Data = 0 and Max_Data = 127

Definition at line 77 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_Init().

uint32_t TSC_InitTypeDef::SpreadSpectrumPrescaler

Spread spectrum prescaler This parameter can be a value of Spread Spectrum Prescaler

Definition at line 79 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_Init().

uint32_t TSC_InitTypeDef::SynchroPinPolarity

Synchro pin polarity This parameter can be a value of Synchro Pin Polarity

Definition at line 87 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_Init().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_tsc.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TSC_IOConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TSC_IOConfigTypeDef Struct Reference
TSC Exported Types

TSC IOs configuration structure definition. More...

#include <stm32wbxx_hal_tsc.h>

Data Fields

uint32_t | ChannelIOs
uint32_t | ShieldIOs
uint32_t | SamplingIOs

Detailed Description

TSC IOs configuration structure definition.

Definition at line 101 of file stm32wbxx_hal_tsc.h.

Field Documentation

uint32_t TSC_IOConfigTypeDef::ChannelIOs

Channel IOs mask

Definition at line 103 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_IOConfig().

uint32_t TSC_IOConfigTypeDef::SamplingIOs

Sampling IOs mask

Definition at line 105 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_IOConfig().

uint32_t TSC_IOConfigTypeDef::ShieldIOs

Shield IOs mask

Definition at line 104 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_IOConfig().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_tsc.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: __TSC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__TSC_HandleTypeDef Struct Reference
TSC Exported Types

TSC handle Structure definition. More...

#include <stm32wbxx_hal_tsc.h>

Data Fields

TSC_TypeDef * | Instance
TSC_InitTypeDef Init
__IO HAL_TSC_StateTypeDef | State
HAL_LockTypeDef | Lock
__IO uint32_t | ErrorCode
void(* | ConvCpltCallback )(struct __TSC_HandleTypeDef *htsc)
void(* | ErrorCallback )(struct __TSC_HandleTypeDef *htsc)
void(* | MspInitCallback )(struct __TSC_HandleTypeDef *htsc)
void(* | MspDeInitCallback )(struct __TSC_HandleTypeDef *htsc)

Detailed Description

TSC handle Structure definition.

Definition at line 111 of file stm32wbxx_hal_tsc.h.

Field Documentation

void(* __TSC_HandleTypeDef::ConvCpltCallback)(struct __TSC_HandleTypeDef *htsc)

TSC Conversion complete callback

Definition at line 120 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_Init(), HAL_TSC_IRQHandler(), HAL_TSC_RegisterCallback(), and HAL_TSC_UnRegisterCallback().

void(* __TSC_HandleTypeDef::ErrorCallback)(struct __TSC_HandleTypeDef *htsc)

TSC Error callback

Definition at line 121 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_Init(), HAL_TSC_IRQHandler(), HAL_TSC_RegisterCallback(), and HAL_TSC_UnRegisterCallback().

__IO uint32_t __TSC_HandleTypeDef::ErrorCode

I2C Error code

Definition at line 117 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_RegisterCallback(), and HAL_TSC_UnRegisterCallback().

TSC_InitTypeDef __TSC_HandleTypeDef::Init

Initialization parameters

Definition at line 114 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_Init(), HAL_TSC_Start(), and HAL_TSC_Start_IT().

TSC_TypeDef* __TSC_HandleTypeDef::Instance

Register base address

Definition at line 113 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_DeInit(), HAL_TSC_GetState(), HAL_TSC_GroupGetStatus(), HAL_TSC_GroupGetValue(), HAL_TSC_Init(), HAL_TSC_IOConfig(), HAL_TSC_IODischarge(), HAL_TSC_IRQHandler(), HAL_TSC_PollForAcquisition(), HAL_TSC_Start(), HAL_TSC_Start_IT(), HAL_TSC_Stop(), and HAL_TSC_Stop_IT().

HAL_LockTypeDef __TSC_HandleTypeDef::Lock

Lock feature

Definition at line 116 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_Init().

void(* __TSC_HandleTypeDef::MspDeInitCallback)(struct __TSC_HandleTypeDef *htsc)

TSC Msp DeInit callback

Definition at line 124 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_DeInit(), HAL_TSC_RegisterCallback(), and HAL_TSC_UnRegisterCallback().

void(* __TSC_HandleTypeDef::MspInitCallback)(struct __TSC_HandleTypeDef *htsc)

TSC Msp Init callback

Definition at line 123 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_Init(), HAL_TSC_RegisterCallback(), and HAL_TSC_UnRegisterCallback().

__IO HAL_TSC_StateTypeDef __TSC_HandleTypeDef::State

Peripheral state

Definition at line 115 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_DeInit(), HAL_TSC_GetState(), HAL_TSC_Init(), HAL_TSC_IRQHandler(), HAL_TSC_RegisterCallback(), HAL_TSC_Start(), HAL_TSC_Start_IT(), HAL_TSC_Stop(), HAL_TSC_Stop_IT(), and HAL_TSC_UnRegisterCallback().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_tsc.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TSC Error Code definition

Defines
TSC Error Code definition
TSC Exported Constants

TSC Error Code definition. More...

Defines

#define | HAL_TSC_ERROR_NONE 0x00000000UL
#define | HAL_TSC_ERROR_INVALID_CALLBACK 0x00000001UL

Detailed Description

TSC Error Code definition.

Define Documentation

#define HAL_TSC_ERROR_INVALID_CALLBACK 0x00000001UL

Invalid Callback error

Definition at line 177 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_RegisterCallback(), and HAL_TSC_UnRegisterCallback().

#define HAL_TSC_ERROR_NONE 0x00000000UL

No error

Definition at line 175 of file stm32wbxx_hal_tsc.h.

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CTPulse High Length

Defines
CTPulse High Length
TSC Exported Constants

Defines

#define | TSC_CTPH_1CYCLE 0x00000000UL
#define | TSC_CTPH_2CYCLES TSC_CR_CTPH_0
#define | TSC_CTPH_3CYCLES TSC_CR_CTPH_1
#define | TSC_CTPH_4CYCLES (TSC_CR_CTPH_1 | TSC_CR_CTPH_0)
#define | TSC_CTPH_5CYCLES TSC_CR_CTPH_2
#define | TSC_CTPH_6CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_0)
#define | TSC_CTPH_7CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1)
#define | TSC_CTPH_8CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0)
#define | TSC_CTPH_9CYCLES TSC_CR_CTPH_3
#define | TSC_CTPH_10CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_0)
#define | TSC_CTPH_11CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1)
#define | TSC_CTPH_12CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0)
#define | TSC_CTPH_13CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2)
#define | TSC_CTPH_14CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_0)
#define | TSC_CTPH_15CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1)
#define | TSC_CTPH_16CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0)

Define Documentation

#define TSC_CTPH_10CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_0)

Charge transfer pulse high during 10 cycles (PGCLK)

Definition at line 195 of file stm32wbxx_hal_tsc.h.

#define TSC_CTPH_11CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1)

Charge transfer pulse high during 11 cycles (PGCLK)

Definition at line 196 of file stm32wbxx_hal_tsc.h.

#define TSC_CTPH_12CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0)

Charge transfer pulse high during 12 cycles (PGCLK)

Definition at line 197 of file stm32wbxx_hal_tsc.h.

#define TSC_CTPH_13CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2)

Charge transfer pulse high during 13 cycles (PGCLK)

Definition at line 198 of file stm32wbxx_hal_tsc.h.

#define TSC_CTPH_14CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_0)

Charge transfer pulse high during 14 cycles (PGCLK)

Definition at line 199 of file stm32wbxx_hal_tsc.h.

#define TSC_CTPH_15CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1)

Charge transfer pulse high during 15 cycles (PGCLK)

Definition at line 200 of file stm32wbxx_hal_tsc.h.

#define TSC_CTPH_16CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0)

Charge transfer pulse high during 16 cycles (PGCLK)

Definition at line 201 of file stm32wbxx_hal_tsc.h.

#define TSC_CTPH_1CYCLE 0x00000000UL

Charge transfer pulse high during 1 cycle (PGCLK)

Definition at line 186 of file stm32wbxx_hal_tsc.h.

#define TSC_CTPH_2CYCLES TSC_CR_CTPH_0

Charge transfer pulse high during 2 cycles (PGCLK)

Definition at line 187 of file stm32wbxx_hal_tsc.h.

#define TSC_CTPH_3CYCLES TSC_CR_CTPH_1

Charge transfer pulse high during 3 cycles (PGCLK)

Definition at line 188 of file stm32wbxx_hal_tsc.h.

#define TSC_CTPH_4CYCLES (TSC_CR_CTPH_1 | TSC_CR_CTPH_0)

Charge transfer pulse high during 4 cycles (PGCLK)

Definition at line 189 of file stm32wbxx_hal_tsc.h.

#define TSC_CTPH_5CYCLES TSC_CR_CTPH_2

Charge transfer pulse high during 5 cycles (PGCLK)

Definition at line 190 of file stm32wbxx_hal_tsc.h.

#define TSC_CTPH_6CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_0)

Charge transfer pulse high during 6 cycles (PGCLK)

Definition at line 191 of file stm32wbxx_hal_tsc.h.

#define TSC_CTPH_7CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1)

Charge transfer pulse high during 7 cycles (PGCLK)

Definition at line 192 of file stm32wbxx_hal_tsc.h.

#define TSC_CTPH_8CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0)

Charge transfer pulse high during 8 cycles (PGCLK)

Definition at line 193 of file stm32wbxx_hal_tsc.h.

#define TSC_CTPH_9CYCLES TSC_CR_CTPH_3

Charge transfer pulse high during 9 cycles (PGCLK)

Definition at line 194 of file stm32wbxx_hal_tsc.h.

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STM32WB55xx HAL User Manual: CTPulse Low Length

Defines
CTPulse Low Length
TSC Exported Constants

Defines

#define | TSC_CTPL_1CYCLE 0x00000000UL
#define | TSC_CTPL_2CYCLES TSC_CR_CTPL_0
#define | TSC_CTPL_3CYCLES TSC_CR_CTPL_1
#define | TSC_CTPL_4CYCLES (TSC_CR_CTPL_1 | TSC_CR_CTPL_0)
#define | TSC_CTPL_5CYCLES TSC_CR_CTPL_2
#define | TSC_CTPL_6CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_0)
#define | TSC_CTPL_7CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1)
#define | TSC_CTPL_8CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0)
#define | TSC_CTPL_9CYCLES TSC_CR_CTPL_3
#define | TSC_CTPL_10CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_0)
#define | TSC_CTPL_11CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1)
#define | TSC_CTPL_12CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0)
#define | TSC_CTPL_13CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2)
#define | TSC_CTPL_14CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0)
#define | TSC_CTPL_15CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1)
#define | TSC_CTPL_16CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0)

Define Documentation

#define TSC_CTPL_10CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_0)

Charge transfer pulse low during 10 cycles (PGCLK)

Definition at line 218 of file stm32wbxx_hal_tsc.h.

#define TSC_CTPL_11CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1)

Charge transfer pulse low during 11 cycles (PGCLK)

Definition at line 219 of file stm32wbxx_hal_tsc.h.

#define TSC_CTPL_12CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0)

Charge transfer pulse low during 12 cycles (PGCLK)

Definition at line 220 of file stm32wbxx_hal_tsc.h.

#define TSC_CTPL_13CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2)

Charge transfer pulse low during 13 cycles (PGCLK)

Definition at line 221 of file stm32wbxx_hal_tsc.h.

#define TSC_CTPL_14CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0)

Charge transfer pulse low during 14 cycles (PGCLK)

Definition at line 222 of file stm32wbxx_hal_tsc.h.

#define TSC_CTPL_15CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1)

Charge transfer pulse low during 15 cycles (PGCLK)

Definition at line 223 of file stm32wbxx_hal_tsc.h.

#define TSC_CTPL_16CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0)

Charge transfer pulse low during 16 cycles (PGCLK)

Definition at line 224 of file stm32wbxx_hal_tsc.h.

#define TSC_CTPL_1CYCLE 0x00000000UL

Charge transfer pulse low during 1 cycle (PGCLK)

Definition at line 209 of file stm32wbxx_hal_tsc.h.

#define TSC_CTPL_2CYCLES TSC_CR_CTPL_0

Charge transfer pulse low during 2 cycles (PGCLK)

Definition at line 210 of file stm32wbxx_hal_tsc.h.

#define TSC_CTPL_3CYCLES TSC_CR_CTPL_1

Charge transfer pulse low during 3 cycles (PGCLK)

Definition at line 211 of file stm32wbxx_hal_tsc.h.

#define TSC_CTPL_4CYCLES (TSC_CR_CTPL_1 | TSC_CR_CTPL_0)

Charge transfer pulse low during 4 cycles (PGCLK)

Definition at line 212 of file stm32wbxx_hal_tsc.h.

#define TSC_CTPL_5CYCLES TSC_CR_CTPL_2

Charge transfer pulse low during 5 cycles (PGCLK)

Definition at line 213 of file stm32wbxx_hal_tsc.h.

#define TSC_CTPL_6CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_0)

Charge transfer pulse low during 6 cycles (PGCLK)

Definition at line 214 of file stm32wbxx_hal_tsc.h.

#define TSC_CTPL_7CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1)

Charge transfer pulse low during 7 cycles (PGCLK)

Definition at line 215 of file stm32wbxx_hal_tsc.h.

#define TSC_CTPL_8CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0)

Charge transfer pulse low during 8 cycles (PGCLK)

Definition at line 216 of file stm32wbxx_hal_tsc.h.

#define TSC_CTPL_9CYCLES TSC_CR_CTPL_3

Charge transfer pulse low during 9 cycles (PGCLK)

Definition at line 217 of file stm32wbxx_hal_tsc.h.

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STM32WB55xx HAL User Manual: Spread Spectrum Prescaler

Defines
Spread Spectrum Prescaler
TSC Exported Constants

Defines

#define | TSC_SS_PRESC_DIV1 0x00000000UL
#define | TSC_SS_PRESC_DIV2 TSC_CR_SSPSC

Define Documentation

#define TSC_SS_PRESC_DIV1 0x00000000UL

Spread Spectrum Prescaler Div1

Definition at line 232 of file stm32wbxx_hal_tsc.h.

#define TSC_SS_PRESC_DIV2 TSC_CR_SSPSC

Spread Spectrum Prescaler Div2

Definition at line 233 of file stm32wbxx_hal_tsc.h.

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STM32WB55xx HAL User Manual: Pulse Generator Prescaler

Defines
Pulse Generator Prescaler
TSC Exported Constants

Defines

#define | TSC_PG_PRESC_DIV1 0x00000000UL
#define | TSC_PG_PRESC_DIV2 TSC_CR_PGPSC_0
#define | TSC_PG_PRESC_DIV4 TSC_CR_PGPSC_1
#define | TSC_PG_PRESC_DIV8 (TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0)
#define | TSC_PG_PRESC_DIV16 TSC_CR_PGPSC_2
#define | TSC_PG_PRESC_DIV32 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_0)
#define | TSC_PG_PRESC_DIV64 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1)
#define | TSC_PG_PRESC_DIV128 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0)

Define Documentation

#define TSC_PG_PRESC_DIV1 0x00000000UL

Pulse Generator HCLK Div1

Definition at line 241 of file stm32wbxx_hal_tsc.h.

#define TSC_PG_PRESC_DIV128 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0)

Pulse Generator HCLK Div128

Definition at line 248 of file stm32wbxx_hal_tsc.h.

#define TSC_PG_PRESC_DIV16 TSC_CR_PGPSC_2

Pulse Generator HCLK Div16

Definition at line 245 of file stm32wbxx_hal_tsc.h.

#define TSC_PG_PRESC_DIV2 TSC_CR_PGPSC_0

Pulse Generator HCLK Div2

Definition at line 242 of file stm32wbxx_hal_tsc.h.

#define TSC_PG_PRESC_DIV32 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_0)

Pulse Generator HCLK Div32

Definition at line 246 of file stm32wbxx_hal_tsc.h.

#define TSC_PG_PRESC_DIV4 TSC_CR_PGPSC_1

Pulse Generator HCLK Div4

Definition at line 243 of file stm32wbxx_hal_tsc.h.

#define TSC_PG_PRESC_DIV64 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1)

Pulse Generator HCLK Div64

Definition at line 247 of file stm32wbxx_hal_tsc.h.

#define TSC_PG_PRESC_DIV8 (TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0)

Pulse Generator HCLK Div8

Definition at line 244 of file stm32wbxx_hal_tsc.h.

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STM32WB55xx HAL User Manual: Max Count Value

Defines
Max Count Value
TSC Exported Constants

Defines

#define | TSC_MCV_255 0x00000000UL
#define | TSC_MCV_511 TSC_CR_MCV_0
#define | TSC_MCV_1023 TSC_CR_MCV_1
#define | TSC_MCV_2047 (TSC_CR_MCV_1 | TSC_CR_MCV_0)
#define | TSC_MCV_4095 TSC_CR_MCV_2
#define | TSC_MCV_8191 (TSC_CR_MCV_2 | TSC_CR_MCV_0)
#define | TSC_MCV_16383 (TSC_CR_MCV_2 | TSC_CR_MCV_1)

Define Documentation

#define TSC_MCV_1023 TSC_CR_MCV_1

1023 maximum number of charge transfer pulses

Definition at line 258 of file stm32wbxx_hal_tsc.h.

#define TSC_MCV_16383 (TSC_CR_MCV_2 | TSC_CR_MCV_1)

16383 maximum number of charge transfer pulses

Definition at line 262 of file stm32wbxx_hal_tsc.h.

#define TSC_MCV_2047 (TSC_CR_MCV_1 | TSC_CR_MCV_0)

2047 maximum number of charge transfer pulses

Definition at line 259 of file stm32wbxx_hal_tsc.h.

#define TSC_MCV_255 0x00000000UL

255 maximum number of charge transfer pulses

Definition at line 256 of file stm32wbxx_hal_tsc.h.

#define TSC_MCV_4095 TSC_CR_MCV_2

4095 maximum number of charge transfer pulses

Definition at line 260 of file stm32wbxx_hal_tsc.h.

#define TSC_MCV_511 TSC_CR_MCV_0

511 maximum number of charge transfer pulses

Definition at line 257 of file stm32wbxx_hal_tsc.h.

#define TSC_MCV_8191 (TSC_CR_MCV_2 | TSC_CR_MCV_0)

8191 maximum number of charge transfer pulses

Definition at line 261 of file stm32wbxx_hal_tsc.h.

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STM32WB55xx HAL User Manual: IO Default Mode

Defines
IO Default Mode
TSC Exported Constants

Defines

#define | TSC_IODEF_OUT_PP_LOW 0x00000000UL
#define | TSC_IODEF_IN_FLOAT TSC_CR_IODEF

Define Documentation

#define TSC_IODEF_IN_FLOAT TSC_CR_IODEF

I/Os are in input floating

Definition at line 271 of file stm32wbxx_hal_tsc.h.

#define TSC_IODEF_OUT_PP_LOW 0x00000000UL

I/Os are forced to output push-pull low

Definition at line 270 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_Start(), and HAL_TSC_Start_IT().

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Synchro Pin Polarity

Defines
Synchro Pin Polarity
TSC Exported Constants

Defines

#define | TSC_SYNC_POLARITY_FALLING 0x00000000UL
#define | TSC_SYNC_POLARITY_RISING TSC_CR_SYNCPOL

Define Documentation

#define TSC_SYNC_POLARITY_FALLING 0x00000000UL

Falling edge only

Definition at line 279 of file stm32wbxx_hal_tsc.h.

#define TSC_SYNC_POLARITY_RISING TSC_CR_SYNCPOL

Rising edge and high level

Definition at line 280 of file stm32wbxx_hal_tsc.h.

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STM32WB55xx HAL User Manual: Acquisition Mode

Defines
Acquisition Mode
TSC Exported Constants

Defines

#define | TSC_ACQ_MODE_NORMAL 0x00000000UL
#define | TSC_ACQ_MODE_SYNCHRO TSC_CR_AM

Define Documentation

#define TSC_ACQ_MODE_NORMAL 0x00000000UL

Normal acquisition mode (acquisition starts as soon as START bit is set)

Definition at line 288 of file stm32wbxx_hal_tsc.h.

#define TSC_ACQ_MODE_SYNCHRO TSC_CR_AM

Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin)

Definition at line 289 of file stm32wbxx_hal_tsc.h.

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STM32WB55xx HAL User Manual: Interrupts definition

Defines
Interrupts definition
TSC Exported Constants

Defines

#define | TSC_IT_EOA TSC_IER_EOAIE
#define | TSC_IT_MCE TSC_IER_MCEIE

Define Documentation

#define TSC_IT_EOA TSC_IER_EOAIE

End of acquisition interrupt enable

Definition at line 297 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_Init(), HAL_TSC_Start(), HAL_TSC_Start_IT(), and HAL_TSC_Stop_IT().

#define TSC_IT_MCE TSC_IER_MCEIE

Max count error interrupt enable

Definition at line 298 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_Init(), HAL_TSC_Start(), HAL_TSC_Start_IT(), and HAL_TSC_Stop_IT().

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Flags definition

Defines
Flags definition
TSC Exported Constants

Defines

#define | TSC_FLAG_EOA TSC_ISR_EOAF
#define | TSC_FLAG_MCE TSC_ISR_MCEF

Define Documentation

#define TSC_FLAG_EOA TSC_ISR_EOAF

End of acquisition flag

Definition at line 306 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_GetState(), HAL_TSC_Init(), HAL_TSC_IRQHandler(), HAL_TSC_Start(), HAL_TSC_Start_IT(), HAL_TSC_Stop(), and HAL_TSC_Stop_IT().

#define TSC_FLAG_MCE TSC_ISR_MCEF

Max count error flag

Definition at line 307 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_GetState(), HAL_TSC_Init(), HAL_TSC_IRQHandler(), HAL_TSC_Start(), HAL_TSC_Start_IT(), HAL_TSC_Stop(), and HAL_TSC_Stop_IT().

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STM32WB55xx HAL User Manual: Group definition

Defines
Group definition
TSC Exported Constants

Defines

#define | TSC_GROUP1 (0x1UL << TSC_GROUP1_IDX)
#define | TSC_GROUP2 (0x1UL << TSC_GROUP2_IDX)
#define | TSC_GROUP3 (0x1UL << TSC_GROUP3_IDX)
#define | TSC_GROUP4 (0x1UL << TSC_GROUP4_IDX)
#define | TSC_GROUP5 (0x1UL << TSC_GROUP5_IDX)
#define | TSC_GROUP6 (0x1UL << TSC_GROUP6_IDX)
#define | TSC_GROUP7 (0x1UL << TSC_GROUP7_IDX)
#define | TSC_GROUP1_IO1 TSC_IOCCR_G1_IO1
#define | TSC_GROUP1_IO2 TSC_IOCCR_G1_IO2
#define | TSC_GROUP1_IO3 TSC_IOCCR_G1_IO3
#define | TSC_GROUP1_IO4 TSC_IOCCR_G1_IO4
#define | TSC_GROUP2_IO1 TSC_IOCCR_G2_IO1
#define | TSC_GROUP2_IO2 TSC_IOCCR_G2_IO2
#define | TSC_GROUP2_IO3 TSC_IOCCR_G2_IO3
#define | TSC_GROUP2_IO4 TSC_IOCCR_G2_IO4
#define | TSC_GROUP3_IO1 TSC_IOCCR_G3_IO1
#define | TSC_GROUP3_IO2 TSC_IOCCR_G3_IO2
#define | TSC_GROUP3_IO3 TSC_IOCCR_G3_IO3
#define | TSC_GROUP3_IO4 TSC_IOCCR_G3_IO4
#define | TSC_GROUP4_IO1 TSC_IOCCR_G4_IO1
#define | TSC_GROUP4_IO2 TSC_IOCCR_G4_IO2
#define | TSC_GROUP4_IO3 TSC_IOCCR_G4_IO3
#define | TSC_GROUP4_IO4 TSC_IOCCR_G4_IO4
#define | TSC_GROUP5_IO1 TSC_IOCCR_G5_IO1
#define | TSC_GROUP5_IO2 TSC_IOCCR_G5_IO2
#define | TSC_GROUP5_IO3 TSC_IOCCR_G5_IO3
#define | TSC_GROUP5_IO4 TSC_IOCCR_G5_IO4
#define | TSC_GROUP6_IO1 TSC_IOCCR_G6_IO1
#define | TSC_GROUP6_IO2 TSC_IOCCR_G6_IO2
#define | TSC_GROUP6_IO3 TSC_IOCCR_G6_IO3
#define | TSC_GROUP6_IO4 TSC_IOCCR_G6_IO4
#define | TSC_GROUP7_IO1 TSC_IOCCR_G7_IO1
#define | TSC_GROUP7_IO2 TSC_IOCCR_G7_IO2
#define | TSC_GROUP7_IO3 TSC_IOCCR_G7_IO3
#define | TSC_GROUP7_IO4 TSC_IOCCR_G7_IO4

Define Documentation

#define TSC_GROUP1 (0x1UL << TSC_GROUP1_IDX)

Definition at line 315 of file stm32wbxx_hal_tsc.h.

#define TSC_GROUP1_IO1 TSC_IOCCR_G1_IO1

TSC Group1 IO1

Definition at line 323 of file stm32wbxx_hal_tsc.h.

#define TSC_GROUP1_IO2 TSC_IOCCR_G1_IO2

TSC Group1 IO2

Definition at line 324 of file stm32wbxx_hal_tsc.h.

#define TSC_GROUP1_IO3 TSC_IOCCR_G1_IO3

TSC Group1 IO3

Definition at line 325 of file stm32wbxx_hal_tsc.h.

#define TSC_GROUP1_IO4 TSC_IOCCR_G1_IO4

TSC Group1 IO4

Definition at line 326 of file stm32wbxx_hal_tsc.h.

#define TSC_GROUP2 (0x1UL << TSC_GROUP2_IDX)

Definition at line 316 of file stm32wbxx_hal_tsc.h.

#define TSC_GROUP2_IO1 TSC_IOCCR_G2_IO1

TSC Group2 IO1

Definition at line 328 of file stm32wbxx_hal_tsc.h.

#define TSC_GROUP2_IO2 TSC_IOCCR_G2_IO2

TSC Group2 IO2

Definition at line 329 of file stm32wbxx_hal_tsc.h.

#define TSC_GROUP2_IO3 TSC_IOCCR_G2_IO3

TSC Group2 IO3

Definition at line 330 of file stm32wbxx_hal_tsc.h.

#define TSC_GROUP2_IO4 TSC_IOCCR_G2_IO4

TSC Group2 IO4

Definition at line 331 of file stm32wbxx_hal_tsc.h.

#define TSC_GROUP3 (0x1UL << TSC_GROUP3_IDX)

Definition at line 317 of file stm32wbxx_hal_tsc.h.

#define TSC_GROUP3_IO1 TSC_IOCCR_G3_IO1

TSC Group3 IO1

Definition at line 333 of file stm32wbxx_hal_tsc.h.

#define TSC_GROUP3_IO2 TSC_IOCCR_G3_IO2

TSC Group3 IO2

Definition at line 334 of file stm32wbxx_hal_tsc.h.

#define TSC_GROUP3_IO3 TSC_IOCCR_G3_IO3

TSC Group3 IO3

Definition at line 335 of file stm32wbxx_hal_tsc.h.

#define TSC_GROUP3_IO4 TSC_IOCCR_G3_IO4

TSC Group3 IO4

Definition at line 336 of file stm32wbxx_hal_tsc.h.

#define TSC_GROUP4 (0x1UL << TSC_GROUP4_IDX)

Definition at line 318 of file stm32wbxx_hal_tsc.h.

#define TSC_GROUP4_IO1 TSC_IOCCR_G4_IO1

TSC Group4 IO1

Definition at line 338 of file stm32wbxx_hal_tsc.h.

#define TSC_GROUP4_IO2 TSC_IOCCR_G4_IO2

TSC Group4 IO2

Definition at line 339 of file stm32wbxx_hal_tsc.h.

#define TSC_GROUP4_IO3 TSC_IOCCR_G4_IO3

TSC Group4 IO3

Definition at line 340 of file stm32wbxx_hal_tsc.h.

#define TSC_GROUP4_IO4 TSC_IOCCR_G4_IO4

TSC Group4 IO4

Definition at line 341 of file stm32wbxx_hal_tsc.h.

#define TSC_GROUP5 (0x1UL << TSC_GROUP5_IDX)

Definition at line 319 of file stm32wbxx_hal_tsc.h.

#define TSC_GROUP5_IO1 TSC_IOCCR_G5_IO1

TSC Group5 IO1

Definition at line 343 of file stm32wbxx_hal_tsc.h.

#define TSC_GROUP5_IO2 TSC_IOCCR_G5_IO2

TSC Group5 IO2

Definition at line 344 of file stm32wbxx_hal_tsc.h.

#define TSC_GROUP5_IO3 TSC_IOCCR_G5_IO3

TSC Group5 IO3

Definition at line 345 of file stm32wbxx_hal_tsc.h.

#define TSC_GROUP5_IO4 TSC_IOCCR_G5_IO4

TSC Group5 IO4

Definition at line 346 of file stm32wbxx_hal_tsc.h.

#define TSC_GROUP6 (0x1UL << TSC_GROUP6_IDX)

Definition at line 320 of file stm32wbxx_hal_tsc.h.

#define TSC_GROUP6_IO1 TSC_IOCCR_G6_IO1

TSC Group6 IO1

Definition at line 348 of file stm32wbxx_hal_tsc.h.

#define TSC_GROUP6_IO2 TSC_IOCCR_G6_IO2

TSC Group6 IO2

Definition at line 349 of file stm32wbxx_hal_tsc.h.

#define TSC_GROUP6_IO3 TSC_IOCCR_G6_IO3

TSC Group6 IO3

Definition at line 350 of file stm32wbxx_hal_tsc.h.

#define TSC_GROUP6_IO4 TSC_IOCCR_G6_IO4

TSC Group6 IO4

Definition at line 351 of file stm32wbxx_hal_tsc.h.

#define TSC_GROUP7 (0x1UL << TSC_GROUP7_IDX)

Definition at line 321 of file stm32wbxx_hal_tsc.h.

#define TSC_GROUP7_IO1 TSC_IOCCR_G7_IO1

TSC Group7 IO1

Definition at line 353 of file stm32wbxx_hal_tsc.h.

#define TSC_GROUP7_IO2 TSC_IOCCR_G7_IO2

TSC Group7 IO2

Definition at line 354 of file stm32wbxx_hal_tsc.h.

#define TSC_GROUP7_IO3 TSC_IOCCR_G7_IO3

TSC Group7 IO3

Definition at line 355 of file stm32wbxx_hal_tsc.h.

#define TSC_GROUP7_IO4 TSC_IOCCR_G7_IO4

TSC Group7 IO4

Definition at line 356 of file stm32wbxx_hal_tsc.h.

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TSC Exported Macros

Defines
TSC Exported Macros
TSC

Defines

#define | __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__)
Reset TSC handle state.
#define | __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE)
Enable the TSC peripheral.
#define | __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_TSCE))
Disable the TSC peripheral.
#define | __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START)
Start acquisition.
#define | __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_START))
Stop acquisition.
#define | __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_IODEF))
Set IO default mode to output push-pull low.
#define | __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF)
Set IO default mode to input floating.
#define | __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_SYNCPOL))
Set synchronization polarity to falling edge.
#define | __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL)
Set synchronization polarity to rising edge and high level.
#define | __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enable TSC interrupt.
#define | __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
Disable TSC interrupt.
#define | __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified TSC interrupt source is enabled or not.
#define | __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
Check whether the specified TSC flag is set or not.
#define | __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the TSC's pending flag.
#define | __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__))
Enable schmitt trigger hysteresis on a group of IOs.
#define | __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (~(__GX_IOY_MASK__)))
Disable schmitt trigger hysteresis on a group of IOs.
#define | __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (~(__GX_IOY_MASK__)))
Open analog switch on a group of IOs.
#define | __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__))
Close analog switch on a group of IOs.
#define | __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__))
Enable a group of IOs in channel mode.
#define | __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (~(__GX_IOY_MASK__)))
Disable a group of channel IOs.
#define | __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__))
Enable a group of IOs in sampling mode.
#define | __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (~(__GX_IOY_MASK__)))
Disable a group of sampling IOs.
#define | __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__))
Enable acquisition groups.
#define | __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (~(__GX_MASK__)))
Disable acquisition groups.
#define | __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) ((((__HANDLE__)->Instance->IOGCSR & (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) == (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING)
Gets acquisition group status.

Define Documentation

#define __HAL_TSC_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the TSC's pending flag.

Parameters:
__HANDLE__ | TSC handle
__FLAG__ | TSC flag
Return values:
None

Definition at line 478 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_IRQHandler(), HAL_TSC_Start(), HAL_TSC_Start_IT(), HAL_TSC_Stop(), and HAL_TSC_Stop_IT().

#define __HAL_TSC_CLOSE_ANALOG_SWITCH | ( | __HANDLE__,
 |  | __GX_IOY_MASK__
 | ) | ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__))

Close analog switch on a group of IOs.

Parameters:
__HANDLE__ | TSC handle
__GX_IOY_MASK__ | IOs mask
Return values:
None

Definition at line 510 of file stm32wbxx_hal_tsc.h.

#define __HAL_TSC_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= (~TSC_CR_TSCE))

Disable the TSC peripheral.

Parameters:
__HANDLE__ TSC handle
Return values:
None

Definition at line 397 of file stm32wbxx_hal_tsc.h.

#define __HAL_TSC_DISABLE_CHANNEL | ( | __HANDLE__,
 |  | __GX_IOY_MASK__
 | ) | ((__HANDLE__)->Instance->IOCCR &= (~(__GX_IOY_MASK__)))

Disable a group of channel IOs.

Parameters:
__HANDLE__ | TSC handle
__GX_IOY_MASK__ | IOs mask
Return values:
None

Definition at line 526 of file stm32wbxx_hal_tsc.h.

#define __HAL_TSC_DISABLE_GROUP | ( | __HANDLE__,
 |  | __GX_MASK__
 | ) | ((__HANDLE__)->Instance->IOGCSR &= (~(__GX_MASK__)))

Disable acquisition groups.

Parameters:
__HANDLE__ | TSC handle
__GX_MASK__ | Groups mask
Return values:
None

Definition at line 558 of file stm32wbxx_hal_tsc.h.

#define __HAL_TSC_DISABLE_HYSTERESIS | ( | __HANDLE__,
 |  | __GX_IOY_MASK__
 | ) | ((__HANDLE__)->Instance->IOHCR &= (~(__GX_IOY_MASK__)))

Disable schmitt trigger hysteresis on a group of IOs.

Parameters:
__HANDLE__ | TSC handle
__GX_IOY_MASK__ | IOs mask
Return values:
None

Definition at line 494 of file stm32wbxx_hal_tsc.h.

#define __HAL_TSC_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))

Disable TSC interrupt.

Parameters:
__HANDLE__ | TSC handle
__INTERRUPT__ | TSC interrupt
Return values:
None

Definition at line 455 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_Start(), HAL_TSC_Start_IT(), and HAL_TSC_Stop_IT().

#define __HAL_TSC_DISABLE_SAMPLING | ( | __HANDLE__,
 |  | __GX_IOY_MASK__
 | ) | ((__HANDLE__)->Instance->IOSCR &= (~(__GX_IOY_MASK__)))

Disable a group of sampling IOs.

Parameters:
__HANDLE__ | TSC handle
__GX_IOY_MASK__ | IOs mask
Return values:
None

Definition at line 542 of file stm32wbxx_hal_tsc.h.

#define __HAL_TSC_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE)

Enable the TSC peripheral.

Parameters:
__HANDLE__ TSC handle
Return values:
None

Definition at line 390 of file stm32wbxx_hal_tsc.h.

#define __HAL_TSC_ENABLE_CHANNEL | ( | __HANDLE__,
 |  | __GX_IOY_MASK__
 | ) | ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__))

Enable a group of IOs in channel mode.

Parameters:
__HANDLE__ | TSC handle
__GX_IOY_MASK__ | IOs mask
Return values:
None

Definition at line 518 of file stm32wbxx_hal_tsc.h.

#define __HAL_TSC_ENABLE_GROUP | ( | __HANDLE__,
 |  | __GX_MASK__
 | ) | ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__))

Enable acquisition groups.

Parameters:
__HANDLE__ | TSC handle
__GX_MASK__ | Groups mask
Return values:
None

Definition at line 550 of file stm32wbxx_hal_tsc.h.

#define __HAL_TSC_ENABLE_HYSTERESIS | ( | __HANDLE__,
 |  | __GX_IOY_MASK__
 | ) | ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__))

Enable schmitt trigger hysteresis on a group of IOs.

Parameters:
__HANDLE__ | TSC handle
__GX_IOY_MASK__ | IOs mask
Return values:
None

Definition at line 486 of file stm32wbxx_hal_tsc.h.

#define __HAL_TSC_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))

Enable TSC interrupt.

Parameters:
__HANDLE__ | TSC handle
__INTERRUPT__ | TSC interrupt
Return values:
None

Definition at line 447 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_Start_IT().

#define __HAL_TSC_ENABLE_SAMPLING | ( | __HANDLE__,
 |  | __GX_IOY_MASK__
 | ) | ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__))

Enable a group of IOs in sampling mode.

Parameters:
__HANDLE__ | TSC handle
__GX_IOY_MASK__ | IOs mask
Return values:
None

Definition at line 534 of file stm32wbxx_hal_tsc.h.

#define __HAL_TSC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET)

Check whether the specified TSC flag is set or not.

Parameters:
__HANDLE__ | TSC handle
__FLAG__ | TSC flag
Return values:
SET or RESET

Definition at line 470 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_GetState(), and HAL_TSC_IRQHandler().

#define __HAL_TSC_GET_GROUP_STATUS | ( | __HANDLE__,
 |  | __GX_INDEX__
 | ) | ((((__HANDLE__)->Instance->IOGCSR & (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) == (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING)

Gets acquisition group status.

Parameters:
__HANDLE__ | TSC Handle
__GX_INDEX__ | Group index
Return values:
SET or RESET

Definition at line 565 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_GroupGetStatus().

#define __HAL_TSC_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified TSC interrupt source is enabled or not.

Parameters:
__HANDLE__ | TSC Handle
__INTERRUPT__ | TSC interrupt
Return values:
SET or RESET

Definition at line 462 of file stm32wbxx_hal_tsc.h.

#define __HAL_TSC_OPEN_ANALOG_SWITCH | ( | __HANDLE__,
 |  | __GX_IOY_MASK__
 | ) | ((__HANDLE__)->Instance->IOASCR &= (~(__GX_IOY_MASK__)))

Open analog switch on a group of IOs.

Parameters:
__HANDLE__ | TSC handle
__GX_IOY_MASK__ | IOs mask
Return values:
None

Definition at line 502 of file stm32wbxx_hal_tsc.h.

#define __HAL_TSC_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                   \
                                                                       (__HANDLE__)->State = HAL_TSC_STATE_RESET;       \
                                                                       (__HANDLE__)->MspInitCallback = NULL;            \
                                                                       (__HANDLE__)->MspDeInitCallback = NULL;          \
                                                                     } while(0)

Reset TSC handle state.

Parameters:
__HANDLE__ TSC handle
Return values:
None

Definition at line 376 of file stm32wbxx_hal_tsc.h.

#define __HAL_TSC_SET_IODEF_INFLOAT ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF)

Set IO default mode to input floating.

Parameters:
__HANDLE__ TSC handle
Return values:
None

Definition at line 425 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_IODischarge(), HAL_TSC_Start(), and HAL_TSC_Start_IT().

#define __HAL_TSC_SET_IODEF_OUTPPLOW ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= (~TSC_CR_IODEF))

Set IO default mode to output push-pull low.

Parameters:
__HANDLE__ TSC handle
Return values:
None

Definition at line 418 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_IODischarge(), HAL_TSC_Start(), HAL_TSC_Start_IT(), HAL_TSC_Stop(), and HAL_TSC_Stop_IT().

#define __HAL_TSC_SET_SYNC_POL_FALL ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= (~TSC_CR_SYNCPOL))

Set synchronization polarity to falling edge.

Parameters:
__HANDLE__ TSC handle
Return values:
None

Definition at line 432 of file stm32wbxx_hal_tsc.h.

#define __HAL_TSC_SET_SYNC_POL_RISE_HIGH ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL)

Set synchronization polarity to rising edge and high level.

Parameters:
__HANDLE__ TSC handle
Return values:
None

Definition at line 439 of file stm32wbxx_hal_tsc.h.

#define __HAL_TSC_START_ACQ ( __HANDLE__ ) ((__HANDLE__)->Instance->CR |= TSC_CR_START)

Start acquisition.

Parameters:
__HANDLE__ TSC handle
Return values:
None

Definition at line 404 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_Start(), and HAL_TSC_Start_IT().

#define __HAL_TSC_STOP_ACQ ( __HANDLE__ ) ((__HANDLE__)->Instance->CR &= (~TSC_CR_START))

Stop acquisition.

Parameters:
__HANDLE__ TSC handle
Return values:
None

Definition at line 411 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_IOConfig(), HAL_TSC_Stop(), and HAL_TSC_Stop_IT().

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TSC Private Macros

Defines
TSC Private Macros
TSC

Defines

#define | IS_TSC_CTPH(__VALUE__)
#define | IS_TSC_CTPL(__VALUE__)
#define | IS_TSC_SS(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE) || ((FunctionalState)(__VALUE__) == ENABLE))
#define | IS_TSC_SSD(__VALUE__) (((__VALUE__) == 0UL) || (((__VALUE__) > 0UL) && ((__VALUE__) < 128UL)))
#define | IS_TSC_SS_PRESC(__VALUE__) (((__VALUE__) == TSC_SS_PRESC_DIV1) || ((__VALUE__) == TSC_SS_PRESC_DIV2))
#define | IS_TSC_PG_PRESC(__VALUE__)
#define | IS_TSC_MCV(__VALUE__)
#define | IS_TSC_IODEF(__VALUE__) (((__VALUE__) == TSC_IODEF_OUT_PP_LOW) || ((__VALUE__) == TSC_IODEF_IN_FLOAT))
#define | IS_TSC_SYNC_POL(__VALUE__) (((__VALUE__) == TSC_SYNC_POLARITY_FALLING) || ((__VALUE__) == TSC_SYNC_POLARITY_RISING))
#define | IS_TSC_ACQ_MODE(__VALUE__) (((__VALUE__) == TSC_ACQ_MODE_NORMAL) || ((__VALUE__) == TSC_ACQ_MODE_SYNCHRO))
#define | IS_TSC_MCE_IT(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE) || ((FunctionalState)(__VALUE__) == ENABLE))
#define | IS_TSC_GROUP_INDEX(__VALUE__) (((__VALUE__) == 0UL) || (((__VALUE__) > 0UL) && ((__VALUE__) < (uint32_t)TSC_NB_OF_GROUPS)))
#define | IS_TSC_GROUP(__VALUE__)

Define Documentation

#define IS_TSC_ACQ_MODE ( __VALUE__ ) (((__VALUE__) == TSC_ACQ_MODE_NORMAL) || ((__VALUE__) == TSC_ACQ_MODE_SYNCHRO))

Definition at line 639 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_Init().

#define IS_TSC_CTPH ( __VALUE__ )
Value:
(((__VALUE__) == TSC_CTPH_1CYCLE)   || \
                                         ((__VALUE__) == TSC_CTPH_2CYCLES)  || \
                                         ((__VALUE__) == TSC_CTPH_3CYCLES)  || \
                                         ((__VALUE__) == TSC_CTPH_4CYCLES)  || \
                                         ((__VALUE__) == TSC_CTPH_5CYCLES)  || \
                                         ((__VALUE__) == TSC_CTPH_6CYCLES)  || \
                                         ((__VALUE__) == TSC_CTPH_7CYCLES)  || \
                                         ((__VALUE__) == TSC_CTPH_8CYCLES)  || \
                                         ((__VALUE__) == TSC_CTPH_9CYCLES)  || \
                                         ((__VALUE__) == TSC_CTPH_10CYCLES) || \
                                         ((__VALUE__) == TSC_CTPH_11CYCLES) || \
                                         ((__VALUE__) == TSC_CTPH_12CYCLES) || \
                                         ((__VALUE__) == TSC_CTPH_13CYCLES) || \
                                         ((__VALUE__) == TSC_CTPH_14CYCLES) || \
                                         ((__VALUE__) == TSC_CTPH_15CYCLES) || \
                                         ((__VALUE__) == TSC_CTPH_16CYCLES))

Definition at line 578 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_Init().

#define IS_TSC_CTPL ( __VALUE__ )
Value:
(((__VALUE__) == TSC_CTPL_1CYCLE)   || \
                                         ((__VALUE__) == TSC_CTPL_2CYCLES)  || \
                                         ((__VALUE__) == TSC_CTPL_3CYCLES)  || \
                                         ((__VALUE__) == TSC_CTPL_4CYCLES)  || \
                                         ((__VALUE__) == TSC_CTPL_5CYCLES)  || \
                                         ((__VALUE__) == TSC_CTPL_6CYCLES)  || \
                                         ((__VALUE__) == TSC_CTPL_7CYCLES)  || \
                                         ((__VALUE__) == TSC_CTPL_8CYCLES)  || \
                                         ((__VALUE__) == TSC_CTPL_9CYCLES)  || \
                                         ((__VALUE__) == TSC_CTPL_10CYCLES) || \
                                         ((__VALUE__) == TSC_CTPL_11CYCLES) || \
                                         ((__VALUE__) == TSC_CTPL_12CYCLES) || \
                                         ((__VALUE__) == TSC_CTPL_13CYCLES) || \
                                         ((__VALUE__) == TSC_CTPL_14CYCLES) || \
                                         ((__VALUE__) == TSC_CTPL_15CYCLES) || \
                                         ((__VALUE__) == TSC_CTPL_16CYCLES))

Definition at line 595 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_Init().

#define IS_TSC_GROUP ( __VALUE__ )
Value:
(((__VALUE__) == 0UL)                               ||\
                                         (((__VALUE__) & TSC_GROUP1_IO1) == TSC_GROUP1_IO1) ||\
                                         (((__VALUE__) & TSC_GROUP1_IO2) == TSC_GROUP1_IO2) ||\
                                         (((__VALUE__) & TSC_GROUP1_IO3) == TSC_GROUP1_IO3) ||\
                                         (((__VALUE__) & TSC_GROUP1_IO4) == TSC_GROUP1_IO4) ||\
                                         (((__VALUE__) & TSC_GROUP2_IO1) == TSC_GROUP2_IO1) ||\
                                         (((__VALUE__) & TSC_GROUP2_IO2) == TSC_GROUP2_IO2) ||\
                                         (((__VALUE__) & TSC_GROUP2_IO3) == TSC_GROUP2_IO3) ||\
                                         (((__VALUE__) & TSC_GROUP2_IO4) == TSC_GROUP2_IO4) ||\
                                         (((__VALUE__) & TSC_GROUP3_IO1) == TSC_GROUP3_IO1) ||\
                                         (((__VALUE__) & TSC_GROUP3_IO2) == TSC_GROUP3_IO2) ||\
                                         (((__VALUE__) & TSC_GROUP3_IO3) == TSC_GROUP3_IO3) ||\
                                         (((__VALUE__) & TSC_GROUP3_IO4) == TSC_GROUP3_IO4) ||\
                                         (((__VALUE__) & TSC_GROUP4_IO1) == TSC_GROUP4_IO1) ||\
                                         (((__VALUE__) & TSC_GROUP4_IO2) == TSC_GROUP4_IO2) ||\
                                         (((__VALUE__) & TSC_GROUP4_IO3) == TSC_GROUP4_IO3) ||\
                                         (((__VALUE__) & TSC_GROUP4_IO4) == TSC_GROUP4_IO4) ||\
                                         (((__VALUE__) & TSC_GROUP5_IO1) == TSC_GROUP5_IO1) ||\
                                         (((__VALUE__) & TSC_GROUP5_IO2) == TSC_GROUP5_IO2) ||\
                                         (((__VALUE__) & TSC_GROUP5_IO3) == TSC_GROUP5_IO3) ||\
                                         (((__VALUE__) & TSC_GROUP5_IO4) == TSC_GROUP5_IO4) ||\
                                         (((__VALUE__) & TSC_GROUP6_IO1) == TSC_GROUP6_IO1) ||\
                                         (((__VALUE__) & TSC_GROUP6_IO2) == TSC_GROUP6_IO2) ||\
                                         (((__VALUE__) & TSC_GROUP6_IO3) == TSC_GROUP6_IO3) ||\
                                         (((__VALUE__) & TSC_GROUP6_IO4) == TSC_GROUP6_IO4) ||\
                                         (((__VALUE__) & TSC_GROUP7_IO1) == TSC_GROUP7_IO1) ||\
                                         (((__VALUE__) & TSC_GROUP7_IO2) == TSC_GROUP7_IO2) ||\
                                         (((__VALUE__) & TSC_GROUP7_IO3) == TSC_GROUP7_IO3) ||\
                                         (((__VALUE__) & TSC_GROUP7_IO4) == TSC_GROUP7_IO4))

Definition at line 645 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_Init(), and HAL_TSC_IOConfig().

#define IS_TSC_GROUP_INDEX ( __VALUE__ ) (((__VALUE__) == 0UL) || (((__VALUE__) > 0UL) && ((__VALUE__) < (uint32_t)TSC_NB_OF_GROUPS)))

Definition at line 643 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_GroupGetStatus(), and HAL_TSC_GroupGetValue().

#define IS_TSC_IODEF ( __VALUE__ ) (((__VALUE__) == TSC_IODEF_OUT_PP_LOW) || ((__VALUE__) == TSC_IODEF_IN_FLOAT))

Definition at line 635 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_Init().

#define IS_TSC_MCE_IT ( __VALUE__ ) (((FunctionalState)(__VALUE__) == DISABLE) || ((FunctionalState)(__VALUE__) == ENABLE))

Definition at line 641 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_Init(), and HAL_TSC_Start_IT().

#define IS_TSC_MCV ( __VALUE__ )
Value:
(((__VALUE__) == TSC_MCV_255)  || \
                                         ((__VALUE__) == TSC_MCV_511)  || \
                                         ((__VALUE__) == TSC_MCV_1023) || \
                                         ((__VALUE__) == TSC_MCV_2047) || \
                                         ((__VALUE__) == TSC_MCV_4095) || \
                                         ((__VALUE__) == TSC_MCV_8191) || \
                                          ((__VALUE__) == TSC_MCV_16383))

Definition at line 627 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_Init().

#define IS_TSC_PG_PRESC ( __VALUE__ )
Value:
(((__VALUE__) == TSC_PG_PRESC_DIV1)  || \
                                         ((__VALUE__) == TSC_PG_PRESC_DIV2)  || \
                                         ((__VALUE__) == TSC_PG_PRESC_DIV4)  || \
                                         ((__VALUE__) == TSC_PG_PRESC_DIV8)  || \
                                         ((__VALUE__) == TSC_PG_PRESC_DIV16) || \
                                         ((__VALUE__) == TSC_PG_PRESC_DIV32) || \
                                         ((__VALUE__) == TSC_PG_PRESC_DIV64) || \
                                         ((__VALUE__) == TSC_PG_PRESC_DIV128))

Definition at line 618 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_Init().

#define IS_TSC_SS ( __VALUE__ ) (((FunctionalState)(__VALUE__) == DISABLE) || ((FunctionalState)(__VALUE__) == ENABLE))

Definition at line 612 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_Init().

#define IS_TSC_SS_PRESC ( __VALUE__ ) (((__VALUE__) == TSC_SS_PRESC_DIV1) || ((__VALUE__) == TSC_SS_PRESC_DIV2))

Definition at line 616 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_Init().

#define IS_TSC_SSD ( __VALUE__ ) (((__VALUE__) == 0UL) || (((__VALUE__) > 0UL) && ((__VALUE__) < 128UL)))

Definition at line 614 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_Init().

#define IS_TSC_SYNC_POL ( __VALUE__ ) (((__VALUE__) == TSC_SYNC_POLARITY_FALLING) || ((__VALUE__) == TSC_SYNC_POLARITY_RISING))

Definition at line 637 of file stm32wbxx_hal_tsc.h.

Referenced by HAL_TSC_Init().

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: UART Private Constants

Defines
UART Private Constants
UART

Defines

#define | USART_CR1_FIELDS
#define | USART_CR3_FIELDS
#define | LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */
#define | LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */
#define | UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */
#define | UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */

Define Documentation

#define LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */

Definition at line 184 of file stm32wbxx_hal_uart.c.

Referenced by UART_SetConfig().

#define LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */

Definition at line 183 of file stm32wbxx_hal_uart.c.

Referenced by UART_SetConfig().

#define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */

Definition at line 188 of file stm32wbxx_hal_uart.c.

Referenced by UART_SetConfig().

#define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */

Definition at line 187 of file stm32wbxx_hal_uart.c.

Referenced by UART_SetConfig().

#define USART_CR1_FIELDS
Value:
((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
                                      USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \
                                      USART_CR1_FIFOEN ))

UART or USART CR1 fields of parameters set by UART_SetConfig API

Definition at line 175 of file stm32wbxx_hal_uart.c.

Referenced by UART_SetConfig().

#define USART_CR3_FIELDS
Value:
((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT| \
                                      USART_CR3_TXFTCFG | USART_CR3_RXFTCFG ))

UART or USART CR3 fields of parameters set by UART_SetConfig API

Definition at line 179 of file stm32wbxx_hal_uart.c.

Referenced by UART_SetConfig().

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
UART Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_UART_Init (UART_HandleTypeDef *huart)
Initialize the UART mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_HalfDuplex_Init (UART_HandleTypeDef *huart)
Initialize the half-duplex mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_LIN_Init (UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
Initialize the LIN mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_MultiProcessor_Init (UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
Initialize the multiprocessor mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_UART_DeInit (UART_HandleTypeDef *huart)
DeInitialize the UART peripheral.
__weak void | HAL_UART_MspInit (UART_HandleTypeDef *huart)
Initialize the UART MSP.
__weak void | HAL_UART_MspDeInit (UART_HandleTypeDef *huart)
DeInitialize the UART MSP.
HAL_StatusTypeDef | HAL_UART_RegisterCallback (UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback)
Register a User UART Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_UART_UnRegisterCallback (UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID)
Unregister an UART Callback UART callaback is redirected to the weak predefined callback.

Detailed Description

Initialization and Configuration functions.

===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
    in asynchronous mode.
      (+) For the asynchronous mode the parameters below can be configured:
        (++) Baud Rate
        (++) Word Length
        (++) Stop Bit
        (++) Parity: If the parity is enabled, then the MSB bit of the data written
             in the data register is transmitted but is changed by the parity bit.
        (++) Hardware flow control
        (++) Receiver/transmitter modes
        (++) Over Sampling Method
        (++) One-Bit Sampling Method
      (+) For the asynchronous mode, the following advanced features can be configured as well:
        (++) TX and/or RX pin level inversion
        (++) data logical level inversion
        (++) RX and TX pins swap
        (++) RX overrun detection disabling
        (++) DMA disabling on RX error
        (++) MSB first on communication line
        (++) auto Baud rate detection
    [..]
    The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API
    follow respectively the UART asynchronous, UART Half duplex, UART LIN mode
    and UART multiprocessor mode configuration procedures (details for the procedures
    are available in reference manual).

Depending on the frame length defined by the M1 and M0 bits (7-bit, 8-bit or 9-bit), the possible UART formats are listed in the following table.

Table 1. UART frame format. +-----------------------------------------------------------------------+ | M1 bit | M0 bit | PCE bit | UART frame | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 0 | | SB | 8 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 0 | | SB | 9 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 0 | | SB | 7 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | +-----------------------------------------------------------------------+

Function Documentation

HAL_StatusTypeDef HAL_HalfDuplex_Init ( UART_HandleTypeDef * huart )

Initialize the half-duplex mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 374 of file stm32wbxx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, __UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, __UART_HandleTypeDef::gState, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::Lock, __UART_HandleTypeDef::MspInitCallback, UART_ADVFEATURE_NO_INIT, UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_InitCallbacksToDefault(), and UART_SetConfig().

HAL_StatusTypeDef HAL_LIN_Init | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | BreakDetectLength
 | ) |  |

Initialize the LIN mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.

Parameters:
huart UART handle.
BreakDetectLength Specifies the LIN break detection length. This parameter can be one of the following values:
  • UART_LINBREAKDETECTLENGTH_10B 10-bit break detection
  • UART_LINBREAKDETECTLENGTH_11B 11-bit break detection
Return values:
HAL status

Definition at line 447 of file stm32wbxx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, __UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, __UART_HandleTypeDef::gState, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, __UART_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, IS_UART_LIN_BREAK_DETECT_LENGTH, __UART_HandleTypeDef::Lock, __UART_HandleTypeDef::MspInitCallback, UART_InitTypeDef::OverSampling, UART_ADVFEATURE_NO_INIT, UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_InitCallbacksToDefault(), UART_OVERSAMPLING_8, UART_SetConfig(), UART_WORDLENGTH_8B, and UART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_MultiProcessor_Init | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t | Address,
 |  | uint32_t | WakeUpMethod
 | ) |  |

Initialize the multiprocessor mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.

Parameters:
huart | UART handle.
Address | UART node address (4-, 6-, 7- or 8-bit long).
WakeUpMethod Specifies the UART wakeup method. This parameter can be one of the following values:
  • UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection
  • UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark
Note:
If the user resorts to idle line detection wake up, the Address parameter is useless and ignored by the initialization function.
If the user resorts to address mark wake up, the address length detection is configured by default to 4 bits only. For the UART to be able to manage 6-, 7- or 8-bit long addresses detection, the API HAL_MultiProcessorEx_AddressLength_Set() must be called after HAL_MultiProcessor_Init().
Return values:
HAL status

Definition at line 544 of file stm32wbxx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, __UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, __UART_HandleTypeDef::gState, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, __UART_HandleTypeDef::Instance, IS_UART_WAKEUPMETHOD, __UART_HandleTypeDef::Lock, __UART_HandleTypeDef::MspInitCallback, UART_ADVFEATURE_NO_INIT, UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_CR2_ADDRESS_LSB_POS, UART_InitCallbacksToDefault(), UART_SetConfig(), and UART_WAKEUPMETHOD_ADDRESSMARK.

HAL_StatusTypeDef HAL_UART_DeInit ( UART_HandleTypeDef * huart )

DeInitialize the UART peripheral.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 618 of file stm32wbxx_hal_uart.c.

References __HAL_UART_DISABLE, assert_param, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_UART_ERROR_NONE, HAL_UART_MspDeInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::MspDeInitCallback, and __UART_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_UART_Init ( UART_HandleTypeDef * huart )

Initialize the UART mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 297 of file stm32wbxx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, __UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, __UART_HandleTypeDef::gState, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, UART_InitTypeDef::HwFlowCtl, __UART_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::Lock, __UART_HandleTypeDef::MspInitCallback, UART_ADVFEATURE_NO_INIT, UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_HWCONTROL_NONE, UART_InitCallbacksToDefault(), and UART_SetConfig().

void HAL_UART_MspDeInit ( UART_HandleTypeDef * huart )

DeInitialize the UART MSP.

Parameters:
huart UART handle.
Return values:
None

Definition at line 682 of file stm32wbxx_hal_uart.c.

Referenced by HAL_UART_DeInit(), and HAL_UART_UnRegisterCallback().

void HAL_UART_MspInit ( UART_HandleTypeDef * huart )

Initialize the UART MSP.

Parameters:
huart UART handle.
Return values:
None

Definition at line 667 of file stm32wbxx_hal_uart.c.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), HAL_UART_Init(), and HAL_UART_UnRegisterCallback().

HAL_StatusTypeDef HAL_UART_RegisterCallback | ( | UART_HandleTypeDef * | huart,
 |  | HAL_UART_CallbackIDTypeDef | CallbackID,
 |  | pUART_CallbackTypeDef | pCallback
 | ) |  |

Register a User UART Callback To be used instead of the weak predefined callback.

Parameters:
huart | uart handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
  • HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
  • HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
  • HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_UART_ERROR_CB_ID Error Callback ID
  • HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
  • HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
  • HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
  • HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
  • HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
  • HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
  • HAL_UART_MSPINIT_CB_ID MspInit Callback ID
  • HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
pCallback | pointer to the Callback function
Return values:
HAL status

Definition at line 715 of file stm32wbxx_hal_uart.c.

References __UART_HandleTypeDef::AbortCpltCallback, __UART_HandleTypeDef::AbortReceiveCpltCallback, __UART_HandleTypeDef::AbortTransmitCpltCallback, __UART_HandleTypeDef::ErrorCallback, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_UART_ABORT_COMPLETE_CB_ID, HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID, HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID, HAL_UART_ERROR_CB_ID, HAL_UART_ERROR_INVALID_CALLBACK, HAL_UART_MSPDEINIT_CB_ID, HAL_UART_MSPINIT_CB_ID, HAL_UART_RX_COMPLETE_CB_ID, HAL_UART_RX_FIFO_FULL_CB_ID, HAL_UART_RX_HALFCOMPLETE_CB_ID, HAL_UART_STATE_READY, HAL_UART_STATE_RESET, HAL_UART_TX_COMPLETE_CB_ID, HAL_UART_TX_FIFO_EMPTY_CB_ID, HAL_UART_TX_HALFCOMPLETE_CB_ID, HAL_UART_WAKEUP_CB_ID, __UART_HandleTypeDef::MspDeInitCallback, __UART_HandleTypeDef::MspInitCallback, __UART_HandleTypeDef::RxCpltCallback, __UART_HandleTypeDef::RxFifoFullCallback, __UART_HandleTypeDef::RxHalfCpltCallback, __UART_HandleTypeDef::TxCpltCallback, __UART_HandleTypeDef::TxFifoEmptyCallback, __UART_HandleTypeDef::TxHalfCpltCallback, and __UART_HandleTypeDef::WakeupCallback.

HAL_StatusTypeDef HAL_UART_UnRegisterCallback | ( | UART_HandleTypeDef * | huart,
 |  | HAL_UART_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an UART Callback UART callaback is redirected to the weak predefined callback.

Parameters:
huart uart handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
  • HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
  • HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
  • HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_UART_ERROR_CB_ID Error Callback ID
  • HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
  • HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
  • HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
  • HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
  • HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
  • HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
  • HAL_UART_MSPINIT_CB_ID MspInit Callback ID
  • HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
Return values:
HAL status

Definition at line 844 of file stm32wbxx_hal_uart.c.

References __UART_HandleTypeDef::AbortCpltCallback, __UART_HandleTypeDef::AbortReceiveCpltCallback, __UART_HandleTypeDef::AbortTransmitCpltCallback, __UART_HandleTypeDef::ErrorCallback, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_UART_ABORT_COMPLETE_CB_ID, HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID, HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID, HAL_UART_AbortCpltCallback(), HAL_UART_AbortReceiveCpltCallback(), HAL_UART_AbortTransmitCpltCallback(), HAL_UART_ERROR_CB_ID, HAL_UART_ERROR_INVALID_CALLBACK, HAL_UART_ErrorCallback(), HAL_UART_MspDeInit(), HAL_UART_MSPDEINIT_CB_ID, HAL_UART_MspInit(), HAL_UART_MSPINIT_CB_ID, HAL_UART_RX_COMPLETE_CB_ID, HAL_UART_RX_FIFO_FULL_CB_ID, HAL_UART_RX_HALFCOMPLETE_CB_ID, HAL_UART_RxCpltCallback(), HAL_UART_RxHalfCpltCallback(), HAL_UART_STATE_READY, HAL_UART_STATE_RESET, HAL_UART_TX_COMPLETE_CB_ID, HAL_UART_TX_FIFO_EMPTY_CB_ID, HAL_UART_TX_HALFCOMPLETE_CB_ID, HAL_UART_TxCpltCallback(), HAL_UART_TxHalfCpltCallback(), HAL_UART_WAKEUP_CB_ID, HAL_UARTEx_RxFifoFullCallback(), HAL_UARTEx_TxFifoEmptyCallback(), HAL_UARTEx_WakeupCallback(), __UART_HandleTypeDef::MspDeInitCallback, __UART_HandleTypeDef::MspInitCallback, __UART_HandleTypeDef::RxCpltCallback, __UART_HandleTypeDef::RxFifoFullCallback, __UART_HandleTypeDef::RxHalfCpltCallback, __UART_HandleTypeDef::TxCpltCallback, __UART_HandleTypeDef::TxFifoEmptyCallback, __UART_HandleTypeDef::TxHalfCpltCallback, and __UART_HandleTypeDef::WakeupCallback.

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IO operation functions

Functions
IO operation functions
UART Exported Functions

UART Transmit/Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_UART_Transmit (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Transmit_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Receive_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Transmit_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_Receive_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_DMAPause (UART_HandleTypeDef *huart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAResume (UART_HandleTypeDef *huart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAStop (UART_HandleTypeDef *huart)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_Abort (UART_HandleTypeDef *huart)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_Abort_IT (UART_HandleTypeDef *huart)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit_IT (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive_IT (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_UART_IRQHandler (UART_HandleTypeDef *huart)
Handle UART interrupt request.
__weak void | HAL_UART_TxCpltCallback (UART_HandleTypeDef *huart)
Tx Transfer completed callback.
__weak void | HAL_UART_TxHalfCpltCallback (UART_HandleTypeDef *huart)
Tx Half Transfer completed callback.
__weak void | HAL_UART_RxCpltCallback (UART_HandleTypeDef *huart)
Rx Transfer completed callback.
__weak void | HAL_UART_RxHalfCpltCallback (UART_HandleTypeDef *huart)
Rx Half Transfer completed callback.
__weak void | HAL_UART_ErrorCallback (UART_HandleTypeDef *huart)
UART error callback.
__weak void | HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
UART Abort Receive Complete callback.

Detailed Description

UART Transmit/Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    This subsection provides a set of functions allowing to manage the UART asynchronous
    and Half duplex data transfers.

    (#) There are two mode of transfer:
       (+) Blocking mode: The communication is performed in polling mode.
           The HAL status of all data processing is returned by the same function
           after finishing transfer.
       (+) Non-Blocking mode: The communication is performed using Interrupts
           or DMA, These API's return the HAL status.
           The end of the data processing will be indicated through the
           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
           using DMA mode.
           The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
           will be executed respectively at the end of the transmit or Receive process
           The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected

    (#) Blocking mode API's are :
        (+) HAL_UART_Transmit()
        (+) HAL_UART_Receive()

    (#) Non-Blocking mode API's with Interrupt are :
        (+) HAL_UART_Transmit_IT()
        (+) HAL_UART_Receive_IT()
        (+) HAL_UART_IRQHandler()

    (#) Non-Blocking mode API's with DMA are :
        (+) HAL_UART_Transmit_DMA()
        (+) HAL_UART_Receive_DMA()
        (+) HAL_UART_DMAPause()
        (+) HAL_UART_DMAResume()
        (+) HAL_UART_DMAStop()

    (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
        (+) HAL_UART_TxHalfCpltCallback()
        (+) HAL_UART_TxCpltCallback()
        (+) HAL_UART_RxHalfCpltCallback()
        (+) HAL_UART_RxCpltCallback()
        (+) HAL_UART_ErrorCallback()

    (#) Non-Blocking mode transfers could be aborted using Abort API's :
        (+) HAL_UART_Abort()
        (+) HAL_UART_AbortTransmit()
        (+) HAL_UART_AbortReceive()
        (+) HAL_UART_Abort_IT()
        (+) HAL_UART_AbortTransmit_IT()
        (+) HAL_UART_AbortReceive_IT()

    (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
        (+) HAL_UART_AbortCpltCallback()
        (+) HAL_UART_AbortTransmitCpltCallback()
        (+) HAL_UART_AbortReceiveCpltCallback()

    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
        Errors are handled as follows :
       (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
           to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
           Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
           and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side.
           If user wants to abort it, Abort services should be called by user.
       (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
           This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
           Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed.

    -@- In the Half duplex communication, it is forbidden to run the transmit
        and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.

Function Documentation

HAL_StatusTypeDef HAL_UART_Abort ( UART_HandleTypeDef * huart )

Abort ongoing transfers (blocking mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable UART Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1658 of file stm32wbxx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_SEND_REQ, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_UART_ERROR_DMA, HAL_UART_ERROR_NONE, HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmarx, __UART_HandleTypeDef::hdmatx, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::TxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, UART_FIFOMODE_ENABLE, UART_RXDATA_FLUSH_REQUEST, UART_TXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_UART_Abort_IT ( UART_HandleTypeDef * huart )

Abort ongoing transfers (Interrupt mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable UART Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1869 of file stm32wbxx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_SEND_REQ, __UART_HandleTypeDef::AbortCpltCallback, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_UART_AbortCpltCallback(), HAL_UART_ERROR_NONE, HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmarx, __UART_HandleTypeDef::hdmatx, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::RxISR, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::TxISR, __UART_HandleTypeDef::TxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, UART_DMARxAbortCallback(), UART_DMATxAbortCallback(), UART_FIFOMODE_ENABLE, UART_RXDATA_FLUSH_REQUEST, UART_TXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_UART_AbortCpltCallback ( UART_HandleTypeDef * huart )

UART Abort Complete callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 2494 of file stm32wbxx_hal_uart.c.

Referenced by HAL_UART_Abort_IT(), HAL_UART_UnRegisterCallback(), UART_DMARxAbortCallback(), UART_DMATxAbortCallback(), and UART_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_UART_AbortReceive ( UART_HandleTypeDef * huart )

Abort ongoing Receive transfer (blocking mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable UART Interrupts (Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1809 of file stm32wbxx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_SEND_REQ, __UART_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_UART_ERROR_DMA, HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmarx, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, UART_RXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_UART_AbortReceive_IT ( UART_HandleTypeDef * huart )

Abort ongoing Receive transfer (Interrupt mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable UART Interrupts (Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 2103 of file stm32wbxx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_SEND_REQ, __UART_HandleTypeDef::AbortReceiveCpltCallback, HAL_DMA_Abort_IT(), HAL_UART_AbortReceiveCpltCallback(), HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmarx, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::pRxBuffPtr, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, UART_DMARxOnlyAbortCallback(), UART_RXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_UART_AbortReceiveCpltCallback ( UART_HandleTypeDef * huart )

UART Abort Receive Complete callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 2524 of file stm32wbxx_hal_uart.c.

Referenced by HAL_UART_AbortReceive_IT(), HAL_UART_UnRegisterCallback(), UART_DMARxOnlyAbortCallback(), and UART_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_UART_AbortTransmit ( UART_HandleTypeDef * huart )

Abort ongoing Transmit transfer (blocking mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable UART Interrupts (Tx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1751 of file stm32wbxx_hal_uart.c.

References __HAL_UART_SEND_REQ, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_UART_ERROR_DMA, HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmatx, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::TxXferCount, UART_FIFOMODE_ENABLE, UART_TXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_UART_AbortTransmit_IT ( UART_HandleTypeDef * huart )

Abort ongoing Transmit transfer (Interrupt mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable UART Interrupts (Tx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 2013 of file stm32wbxx_hal_uart.c.

References __HAL_UART_SEND_REQ, __UART_HandleTypeDef::AbortTransmitCpltCallback, __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_UART_AbortTransmitCpltCallback(), HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmatx, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::TxISR, __UART_HandleTypeDef::TxXferCount, UART_DMATxOnlyAbortCallback(), UART_FIFOMODE_ENABLE, UART_TXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_UART_AbortTransmitCpltCallback ( UART_HandleTypeDef * huart )

UART Abort Complete callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 2509 of file stm32wbxx_hal_uart.c.

Referenced by HAL_UART_AbortTransmit_IT(), HAL_UART_UnRegisterCallback(), UART_DMATxOnlyAbortCallback(), and UART_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_UART_DMAPause ( UART_HandleTypeDef * huart )

Pause the DMA Transfer.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 1517 of file stm32wbxx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, __UART_HandleTypeDef::Instance, and __UART_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_UART_DMAResume ( UART_HandleTypeDef * huart )

Resume the DMA Transfer.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 1551 of file stm32wbxx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::RxState, and UART_CLEAR_OREF.

HAL_StatusTypeDef HAL_UART_DMAStop ( UART_HandleTypeDef * huart )

Stop the DMA Transfer.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 1583 of file stm32wbxx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_UART_ERROR_DMA, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, __UART_HandleTypeDef::hdmarx, __UART_HandleTypeDef::hdmatx, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::RxState, UART_EndRxTransfer(), and UART_EndTxTransfer().

void HAL_UART_ErrorCallback ( UART_HandleTypeDef * huart )

UART error callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 2479 of file stm32wbxx_hal_uart.c.

Referenced by HAL_UART_IRQHandler(), HAL_UART_UnRegisterCallback(), UART_DMAAbortOnError(), UART_DMAError(), and UART_InitCallbacksToDefault().

void HAL_UART_IRQHandler ( UART_HandleTypeDef * huart )

Handle UART interrupt request.

Parameters:
huart UART handle.
Return values:
None

Definition at line 2187 of file stm32wbxx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __UART_HandleTypeDef::ErrorCallback, __UART_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_UART_ERROR_FE, HAL_UART_ERROR_NE, HAL_UART_ERROR_NONE, HAL_UART_ERROR_ORE, HAL_UART_ERROR_PE, HAL_UART_ERROR_RTO, HAL_UART_ErrorCallback(), HAL_UARTEx_RxFifoFullCallback(), HAL_UARTEx_TxFifoEmptyCallback(), HAL_UARTEx_WakeupCallback(), __UART_HandleTypeDef::hdmarx, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::RxFifoFullCallback, __UART_HandleTypeDef::RxISR, __UART_HandleTypeDef::TxFifoEmptyCallback, __UART_HandleTypeDef::TxISR, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, UART_CLEAR_RTOF, UART_CLEAR_WUF, UART_DMAAbortOnError(), UART_EndRxTransfer(), UART_EndTransmit_IT(), __UART_HandleTypeDef::WakeupCallback, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_UART_Receive | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. In this case, Size must indicate the number of u16 available through pData.
When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO is not empty. Read operations from the RDR register are performed when RXFNE flag is set. From hardware perspective, RXFNE flag and RXNE are mapped on the same bit-field.
Parameters:
huart | UART handle.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be received.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 1130 of file stm32wbxx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, __UART_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::Mask, UART_InitTypeDef::Parity, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::RxXferSize, UART_FLAG_RXNE, UART_MASK_COMPUTATION, UART_PARITY_NONE, UART_WaitOnFlagUntilTimeout(), UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_UART_Receive_DMA | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in DMA mode.

Note:
When the UART parity is enabled (PCE = 1), the received data contain the parity bit (MSB position).
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. In this case, Size must indicate the number of u16 available through pData.
Parameters:
huart | UART handle.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be received.
Return values:
HAL status

Definition at line 1446 of file stm32wbxx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_DMA_Start_IT(), HAL_UART_ERROR_DMA, HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmarx, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::pRxBuffPtr, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferSize, UART_DMAError(), UART_DMAReceiveCplt(), UART_DMARxHalfCplt(), __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_UART_Receive_IT | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in interrupt mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. In this case, Size must indicate the number of u16 available through pData.
Parameters:
huart | UART handle.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be received.
Return values:
HAL status

Definition at line 1289 of file stm32wbxx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::FifoMode, HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, __UART_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::NbRxDataToProcess, UART_InitTypeDef::Parity, __UART_HandleTypeDef::pRxBuffPtr, __UART_HandleTypeDef::RxISR, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::RxXferSize, UART_FIFOMODE_ENABLE, UART_MASK_COMPUTATION, UART_PARITY_NONE, UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), UART_RxISR_8BIT_FIFOEN(), UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

void HAL_UART_RxCpltCallback ( UART_HandleTypeDef * huart )

Rx Transfer completed callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 2449 of file stm32wbxx_hal_uart.c.

Referenced by HAL_UART_UnRegisterCallback(), UART_DMAReceiveCplt(), UART_InitCallbacksToDefault(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

void HAL_UART_RxHalfCpltCallback ( UART_HandleTypeDef * huart )

Rx Half Transfer completed callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 2464 of file stm32wbxx_hal_uart.c.

Referenced by HAL_UART_UnRegisterCallback(), UART_DMARxHalfCplt(), and UART_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_UART_Transmit | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Send an amount of data in blocking mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. In this case, Size must indicate the number of u16 provided through pData.
When FIFO mode is enabled, writing a data in the TDR register adds one data to the TXFIFO. Write operations to the TDR register are performed when TXFNF flag is set. From hardware perspective, TXFNF flag and TXE are mapped on the same bit-field.
Parameters:
huart | UART handle.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be sent.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 1041 of file stm32wbxx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_GetTick(), HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_TX, HAL_UART_STATE_READY, __UART_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, UART_InitTypeDef::Parity, __UART_HandleTypeDef::TxXferCount, __UART_HandleTypeDef::TxXferSize, UART_FLAG_TC, UART_FLAG_TXE, UART_PARITY_NONE, UART_WaitOnFlagUntilTimeout(), UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_UART_Transmit_DMA | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in DMA mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. In this case, Size must indicate the number of u16 provided through pData.
Parameters:
huart | UART handle.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be sent.
Return values:
HAL status

Definition at line 1370 of file stm32wbxx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_DMA_Start_IT(), HAL_UART_ERROR_DMA, HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_TX, HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmatx, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::pTxBuffPtr, __UART_HandleTypeDef::TxXferCount, __UART_HandleTypeDef::TxXferSize, UART_CLEAR_TCF, UART_DMAError(), UART_DMATransmitCplt(), UART_DMATxHalfCplt(), __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_UART_Transmit_IT | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in interrupt mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. In this case, Size must indicate the number of u16 provided through pData.
Parameters:
huart | UART handle.
pData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be sent.
Return values:
HAL status

Definition at line 1215 of file stm32wbxx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::gState, HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_TX, HAL_UART_STATE_READY, __UART_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, UART_InitTypeDef::Parity, __UART_HandleTypeDef::pTxBuffPtr, __UART_HandleTypeDef::TxISR, __UART_HandleTypeDef::TxXferCount, __UART_HandleTypeDef::TxXferSize, UART_FIFOMODE_ENABLE, UART_PARITY_NONE, UART_TxISR_16BIT(), UART_TxISR_16BIT_FIFOEN(), UART_TxISR_8BIT(), UART_TxISR_8BIT_FIFOEN(), UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

void HAL_UART_TxCpltCallback ( UART_HandleTypeDef * huart )

Tx Transfer completed callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 2419 of file stm32wbxx_hal_uart.c.

Referenced by HAL_UART_UnRegisterCallback(), UART_DMATransmitCplt(), UART_EndTransmit_IT(), and UART_InitCallbacksToDefault().

void HAL_UART_TxHalfCpltCallback ( UART_HandleTypeDef * huart )

Tx Half Transfer completed callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 2434 of file stm32wbxx_hal_uart.c.

Referenced by HAL_UART_UnRegisterCallback(), UART_DMATxHalfCplt(), and UART_InitCallbacksToDefault().

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
UART Exported Functions

UART control functions. More...

Functions

void | HAL_UART_ReceiverTimeout_Config (UART_HandleTypeDef *huart, uint32_t TimeoutValue)
Update on the fly the receiver timeout value in RTOR register.
HAL_StatusTypeDef | HAL_UART_EnableReceiverTimeout (UART_HandleTypeDef *huart)
Enable the UART receiver timeout feature.
HAL_StatusTypeDef | HAL_UART_DisableReceiverTimeout (UART_HandleTypeDef *huart)
Disable the UART receiver timeout feature.
HAL_StatusTypeDef | HAL_MultiProcessor_EnableMuteMode (UART_HandleTypeDef *huart)
Enable UART in mute mode (does not mean UART enters mute mode; to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
HAL_StatusTypeDef | HAL_MultiProcessor_DisableMuteMode (UART_HandleTypeDef *huart)
Disable UART mute mode (does not mean the UART actually exits mute mode as it may not have been in mute mode at this very moment).
void | HAL_MultiProcessor_EnterMuteMode (UART_HandleTypeDef *huart)
Enter UART mute mode (means UART actually enters mute mode).
HAL_StatusTypeDef | HAL_HalfDuplex_EnableTransmitter (UART_HandleTypeDef *huart)
Enable the UART transmitter and disable the UART receiver.
HAL_StatusTypeDef | HAL_HalfDuplex_EnableReceiver (UART_HandleTypeDef *huart)
Enable the UART receiver and disable the UART transmitter.
HAL_StatusTypeDef | HAL_LIN_SendBreak (UART_HandleTypeDef *huart)
Transmit break characters.

Detailed Description

UART control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the UART.
     (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly
     (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature
     (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature
     (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
     (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
     (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
     (+) UART_SetConfig() API configures the UART peripheral
     (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features
     (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization
     (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
     (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
     (+) HAL_LIN_SendBreak() API transmits the break characters

Function Documentation

HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver ( UART_HandleTypeDef * huart )

Enable the UART receiver and disable the UART transmitter.

Parameters:
huart UART handle.
Return values:
HAL status.

Definition at line 2735 of file stm32wbxx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, and __UART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter ( UART_HandleTypeDef * huart )

Enable the UART transmitter and disable the UART receiver.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 2712 of file stm32wbxx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, and __UART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_LIN_SendBreak ( UART_HandleTypeDef * huart )

Transmit break characters.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 2759 of file stm32wbxx_hal_uart.c.

References __HAL_UART_SEND_REQ, assert_param, __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, and UART_SENDBREAK_REQUEST.

HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode ( UART_HandleTypeDef * huart )

Disable UART mute mode (does not mean the UART actually exits mute mode as it may not have been in mute mode at this very moment).

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 2682 of file stm32wbxx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, and UART_CheckIdleState().

HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode ( UART_HandleTypeDef * huart )

Enable UART in mute mode (does not mean UART enters mute mode; to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 2662 of file stm32wbxx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, and UART_CheckIdleState().

void HAL_MultiProcessor_EnterMuteMode ( UART_HandleTypeDef * huart )

Enter UART mute mode (means UART actually enters mute mode).

Note:
To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
Parameters:
huart UART handle.
Return values:
None

Definition at line 2702 of file stm32wbxx_hal_uart.c.

References __HAL_UART_SEND_REQ, and UART_MUTE_MODE_REQUEST.

HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout ( UART_HandleTypeDef * huart )

Disable the UART receiver timeout feature.

Parameters:
huart Pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 2624 of file stm32wbxx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, and __UART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout ( UART_HandleTypeDef * huart )

Enable the UART receiver timeout feature.

Parameters:
huart Pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 2586 of file stm32wbxx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, and __UART_HandleTypeDef::Instance.

void HAL_UART_ReceiverTimeout_Config | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | TimeoutValue
 | ) |  |

Update on the fly the receiver timeout value in RTOR register.

Parameters:
huart | Pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
TimeoutValue | receiver timeout value in number of baud blocks. The timeout value must be less or equal to 0x0FFFFFFFF.
Return values:
None

Definition at line 2571 of file stm32wbxx_hal_uart.c.

References assert_param, __UART_HandleTypeDef::Instance, and IS_UART_RECEIVER_TIMEOUT_VALUE.

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Peripheral State and Error functions

Functions
Peripheral State and Error functions
UART Exported Functions

UART Peripheral State functions. More...

Functions

HAL_UART_StateTypeDef | HAL_UART_GetState (UART_HandleTypeDef *huart)
Return the UART handle state.
uint32_t | HAL_UART_GetError (UART_HandleTypeDef *huart)
Return the UART handle error code.

Detailed Description

UART Peripheral State functions.

  ==============================================================================
            ##### Peripheral State and Error functions #####
  ==============================================================================
    [..]
    This subsection provides functions allowing to :
      (+) Return the UART handle state.
      (+) Return the UART handle error code

Function Documentation

uint32_t HAL_UART_GetError ( UART_HandleTypeDef * huart )

Return the UART handle error code.

Parameters:
huart Pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART.
Return values:
UART Error Code

Definition at line 2820 of file stm32wbxx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCode.

HAL_UART_StateTypeDef HAL_UART_GetState ( UART_HandleTypeDef * huart )

Return the UART handle state.

Parameters:
huart Pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART.
Return values:
HAL state

Definition at line 2804 of file stm32wbxx_hal_uart.c.

References __UART_HandleTypeDef::gState, and __UART_HandleTypeDef::RxState.

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: UART Private Functions

Functions
UART Private Functions
UART

Functions

static void | UART_EndTxTransfer (UART_HandleTypeDef *huart)
End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
static void | UART_EndRxTransfer (UART_HandleTypeDef *huart)
End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
static void | UART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process complete callback.
static void | UART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process complete callback.
static void | UART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process half complete callback.
static void | UART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process half complete callback.
static void | UART_DMAError (DMA_HandleTypeDef *hdma)
DMA UART communication error callback.
static void | UART_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA UART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | UART_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | UART_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | UART_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Tx communication abort callback, when initiated by user by a call to HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | UART_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Rx communication abort callback, when initiated by user by a call to HAL_UART_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static void | UART_TxISR_8BIT (UART_HandleTypeDef *huart)
TX interrrupt handler for 7 or 8 bits data word length .
static void | UART_TxISR_16BIT (UART_HandleTypeDef *huart)
TX interrrupt handler for 9 bits data word length.
static void | UART_TxISR_8BIT_FIFOEN (UART_HandleTypeDef *huart)
TX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
static void | UART_TxISR_16BIT_FIFOEN (UART_HandleTypeDef *huart)
TX interrrupt handler for 9 bits data word length and FIFO mode is enabled.
static void | UART_EndTransmit_IT (UART_HandleTypeDef *huart)
Wrap up transmission in non-blocking mode.
static void | UART_RxISR_8BIT (UART_HandleTypeDef *huart)
RX interrrupt handler for 7 or 8 bits data word length .
static void | UART_RxISR_16BIT (UART_HandleTypeDef *huart)
RX interrrupt handler for 9 bits data word length .
static void | UART_RxISR_8BIT_FIFOEN (UART_HandleTypeDef *huart)
RX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
static void | UART_RxISR_16BIT_FIFOEN (UART_HandleTypeDef *huart)
RX interrrupt handler for 9 bits data word length and FIFO mode is enabled.
void | UART_InitCallbacksToDefault (UART_HandleTypeDef *huart)
Initialize the callbacks to their default values.
HAL_StatusTypeDef | UART_SetConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral.
void | UART_AdvFeatureConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral advanced features.
HAL_StatusTypeDef | UART_CheckIdleState (UART_HandleTypeDef *huart)
Check the UART Idle State.
HAL_StatusTypeDef | UART_WaitOnFlagUntilTimeout (UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle UART Communication Timeout.

Function Documentation

void UART_AdvFeatureConfig ( UART_HandleTypeDef * huart )

Configure the UART peripheral advanced features.

Parameters:
huart UART handle.
Return values:
None

Definition at line 3100 of file stm32wbxx_hal_uart.c.

References __UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, UART_AdvFeatureInitTypeDef::AutoBaudRateEnable, UART_AdvFeatureInitTypeDef::AutoBaudRateMode, UART_AdvFeatureInitTypeDef::DataInvert, UART_AdvFeatureInitTypeDef::DMADisableonRxError, __UART_HandleTypeDef::Instance, IS_UART_ADVFEATURE_AUTOBAUDRATE, IS_UART_ADVFEATURE_AUTOBAUDRATEMODE, IS_UART_ADVFEATURE_DATAINV, IS_UART_ADVFEATURE_DMAONRXERROR, IS_UART_ADVFEATURE_INIT, IS_UART_ADVFEATURE_MSBFIRST, IS_UART_ADVFEATURE_RXINV, IS_UART_ADVFEATURE_SWAP, IS_UART_ADVFEATURE_TXINV, IS_UART_OVERRUN, UART_AdvFeatureInitTypeDef::MSBFirst, UART_AdvFeatureInitTypeDef::OverrunDisable, UART_AdvFeatureInitTypeDef::RxPinLevelInvert, UART_AdvFeatureInitTypeDef::Swap, UART_AdvFeatureInitTypeDef::TxPinLevelInvert, UART_ADVFEATURE_AUTOBAUDRATE_ENABLE, UART_ADVFEATURE_AUTOBAUDRATE_INIT, UART_ADVFEATURE_DATAINVERT_INIT, UART_ADVFEATURE_DMADISABLEONERROR_INIT, UART_ADVFEATURE_MSBFIRST_INIT, UART_ADVFEATURE_RXINVERT_INIT, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT, UART_ADVFEATURE_SWAP_INIT, and UART_ADVFEATURE_TXINVERT_INIT.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), and HAL_UART_Init().

HAL_StatusTypeDef UART_CheckIdleState ( UART_HandleTypeDef * huart )

Check the UART Idle State.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 3174 of file stm32wbxx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_GetTick(), HAL_UART_ERROR_NONE, HAL_UART_STATE_READY, HAL_UART_TIMEOUT_VALUE, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::RxState, and UART_WaitOnFlagUntilTimeout().

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_DisableMuteMode(), HAL_MultiProcessor_EnableMuteMode(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_RS485Ex_Init(), and HAL_UART_Init().

static void UART_DMAAbortOnError ( DMA_HandleTypeDef * hdma ) [static]

DMA UART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3459 of file stm32wbxx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCallback, HAL_UART_ErrorCallback(), __DMA_HandleTypeDef::Parent, __UART_HandleTypeDef::RxXferCount, and __UART_HandleTypeDef::TxXferCount.

Referenced by HAL_UART_IRQHandler().

static void UART_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA UART communication error callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3419 of file stm32wbxx_hal_uart.c.

References __UART_HandleTypeDef::ErrorCallback, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_UART_ERROR_DMA, HAL_UART_ErrorCallback(), HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, __UART_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::TxXferCount, UART_EndRxTransfer(), and UART_EndTxTransfer().

Referenced by HAL_UART_Receive_DMA(), and HAL_UART_Transmit_DMA().

static void UART_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART receive process complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3366 of file stm32wbxx_hal_uart.c.

References HAL_UART_RxCpltCallback(), HAL_UART_STATE_READY, __DMA_HandleTypeDef::Instance, __UART_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, __UART_HandleTypeDef::RxCpltCallback, __UART_HandleTypeDef::RxState, and __UART_HandleTypeDef::RxXferCount.

Referenced by HAL_UART_Receive_DMA().

static void UART_DMARxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA UART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Tx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3536 of file stm32wbxx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_SEND_REQ, __UART_HandleTypeDef::AbortCpltCallback, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_UART_AbortCpltCallback(), HAL_UART_ERROR_NONE, HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmarx, __UART_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Parent, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::TxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, UART_RXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_UART_Abort_IT().

static void UART_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART receive process half complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3401 of file stm32wbxx_hal_uart.c.

References HAL_UART_RxHalfCpltCallback(), __DMA_HandleTypeDef::Parent, and __UART_HandleTypeDef::RxHalfCpltCallback.

Referenced by HAL_UART_Receive_DMA().

static void UART_DMARxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA UART Rx communication abort callback, when initiated by user by a call to HAL_UART_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3620 of file stm32wbxx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_SEND_REQ, __UART_HandleTypeDef::AbortReceiveCpltCallback, HAL_UART_AbortReceiveCpltCallback(), HAL_UART_STATE_READY, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, and UART_RXDATA_FLUSH_REQUEST.

Referenced by HAL_UART_AbortReceive_IT().

static void UART_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART transmit process complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3314 of file stm32wbxx_hal_uart.c.

References HAL_UART_TxCpltCallback(), __DMA_HandleTypeDef::Instance, __UART_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, __UART_HandleTypeDef::TxCpltCallback, and __UART_HandleTypeDef::TxXferCount.

Referenced by HAL_UART_Transmit_DMA().

static void UART_DMATxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA UART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Rx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3482 of file stm32wbxx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_SEND_REQ, __UART_HandleTypeDef::AbortCpltCallback, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::gState, HAL_UART_AbortCpltCallback(), HAL_UART_ERROR_NONE, HAL_UART_STATE_READY, __UART_HandleTypeDef::hdmarx, __UART_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Parent, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, __UART_HandleTypeDef::TxXferCount, UART_CLEAR_FEF, UART_CLEAR_NEF, UART_CLEAR_OREF, UART_CLEAR_PEF, UART_FIFOMODE_ENABLE, UART_TXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_UART_Abort_IT().

static void UART_DMATxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART transmit process half complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3348 of file stm32wbxx_hal_uart.c.

References HAL_UART_TxHalfCpltCallback(), __DMA_HandleTypeDef::Parent, and __UART_HandleTypeDef::TxHalfCpltCallback.

Referenced by HAL_UART_Transmit_DMA().

static void UART_DMATxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA UART Tx communication abort callback, when initiated by user by a call to HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 3587 of file stm32wbxx_hal_uart.c.

References __HAL_UART_SEND_REQ, __UART_HandleTypeDef::AbortTransmitCpltCallback, __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::gState, HAL_UART_AbortTransmitCpltCallback(), HAL_UART_STATE_READY, __DMA_HandleTypeDef::Parent, __UART_HandleTypeDef::TxXferCount, UART_FIFOMODE_ENABLE, and UART_TXDATA_FLUSH_REQUEST.

Referenced by HAL_UART_AbortTransmit_IT().

static void UART_EndRxTransfer ( UART_HandleTypeDef * huart ) [static]

End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).

Parameters:
huart UART handle.
Return values:
None

Definition at line 3295 of file stm32wbxx_hal_uart.c.

References HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::RxISR, and __UART_HandleTypeDef::RxState.

Referenced by HAL_UART_DMAStop(), HAL_UART_IRQHandler(), and UART_DMAError().

static void UART_EndTransmit_IT ( UART_HandleTypeDef * huart ) [static]

Wrap up transmission in non-blocking mode.

Parameters:
huart pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
None

Definition at line 3794 of file stm32wbxx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_READY, HAL_UART_TxCpltCallback(), __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::TxCpltCallback, and __UART_HandleTypeDef::TxISR.

Referenced by HAL_UART_IRQHandler().

static void UART_EndTxTransfer ( UART_HandleTypeDef * huart ) [static]

End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).

Parameters:
huart UART handle.
Return values:
None

Definition at line 3279 of file stm32wbxx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_READY, and __UART_HandleTypeDef::Instance.

Referenced by HAL_UART_DMAStop(), and UART_DMAError().

void UART_InitCallbacksToDefault ( UART_HandleTypeDef * huart )

Initialize the callbacks to their default values.

Parameters:
huart UART handle.
Return values:
none

Definition at line 2842 of file stm32wbxx_hal_uart.c.

References __UART_HandleTypeDef::AbortCpltCallback, __UART_HandleTypeDef::AbortReceiveCpltCallback, __UART_HandleTypeDef::AbortTransmitCpltCallback, __UART_HandleTypeDef::ErrorCallback, HAL_UART_AbortCpltCallback(), HAL_UART_AbortReceiveCpltCallback(), HAL_UART_AbortTransmitCpltCallback(), HAL_UART_ErrorCallback(), HAL_UART_RxCpltCallback(), HAL_UART_RxHalfCpltCallback(), HAL_UART_TxCpltCallback(), HAL_UART_TxHalfCpltCallback(), HAL_UARTEx_RxFifoFullCallback(), HAL_UARTEx_TxFifoEmptyCallback(), HAL_UARTEx_WakeupCallback(), __UART_HandleTypeDef::RxCpltCallback, __UART_HandleTypeDef::RxFifoFullCallback, __UART_HandleTypeDef::RxHalfCpltCallback, __UART_HandleTypeDef::TxCpltCallback, __UART_HandleTypeDef::TxFifoEmptyCallback, __UART_HandleTypeDef::TxHalfCpltCallback, and __UART_HandleTypeDef::WakeupCallback.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), and HAL_UART_Init().

static void UART_RxISR_16BIT ( UART_HandleTypeDef * huart ) [static]

RX interrrupt handler for 9 bits data word length .

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_UART_Receive_IT()
Parameters:
huart UART handle.
Return values:
None

Definition at line 3869 of file stm32wbxx_hal_uart.c.

References __HAL_UART_SEND_REQ, HAL_UART_RxCpltCallback(), HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::Mask, __UART_HandleTypeDef::pRxBuffPtr, __UART_HandleTypeDef::RxCpltCallback, __UART_HandleTypeDef::RxISR, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, and UART_RXDATA_FLUSH_REQUEST.

Referenced by HAL_UART_Receive_IT(), and UART_RxISR_16BIT_FIFOEN().

static void UART_RxISR_16BIT_FIFOEN ( UART_HandleTypeDef * huart ) [static]

RX interrrupt handler for 9 bits data word length and FIFO mode is enabled.

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_UART_Receive_IT()
Parameters:
huart UART handle.
Return values:
None

Definition at line 3993 of file stm32wbxx_hal_uart.c.

References __HAL_UART_SEND_REQ, HAL_UART_RxCpltCallback(), HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::Mask, __UART_HandleTypeDef::NbRxDataToProcess, __UART_HandleTypeDef::pRxBuffPtr, __UART_HandleTypeDef::RxCpltCallback, __UART_HandleTypeDef::RxISR, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, UART_RXDATA_FLUSH_REQUEST, and UART_RxISR_16BIT().

Referenced by HAL_UART_Receive_IT().

static void UART_RxISR_8BIT ( UART_HandleTypeDef * huart ) [static]

RX interrrupt handler for 7 or 8 bits data word length .

Parameters:
huart UART handle.
Return values:
None

Definition at line 3819 of file stm32wbxx_hal_uart.c.

References __HAL_UART_SEND_REQ, HAL_UART_RxCpltCallback(), HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::Mask, __UART_HandleTypeDef::pRxBuffPtr, __UART_HandleTypeDef::RxCpltCallback, __UART_HandleTypeDef::RxISR, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, and UART_RXDATA_FLUSH_REQUEST.

Referenced by HAL_UART_Receive_IT(), and UART_RxISR_8BIT_FIFOEN().

static void UART_RxISR_8BIT_FIFOEN ( UART_HandleTypeDef * huart ) [static]

RX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_UART_Receive_IT()
Parameters:
huart UART handle.
Return values:
None

Definition at line 3921 of file stm32wbxx_hal_uart.c.

References __HAL_UART_SEND_REQ, HAL_UART_RxCpltCallback(), HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::Mask, __UART_HandleTypeDef::NbRxDataToProcess, __UART_HandleTypeDef::pRxBuffPtr, __UART_HandleTypeDef::RxCpltCallback, __UART_HandleTypeDef::RxISR, __UART_HandleTypeDef::RxState, __UART_HandleTypeDef::RxXferCount, UART_RXDATA_FLUSH_REQUEST, and UART_RxISR_8BIT().

Referenced by HAL_UART_Receive_IT().

HAL_StatusTypeDef UART_SetConfig ( UART_HandleTypeDef * huart )

Configure the UART peripheral.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 2865 of file stm32wbxx_hal_uart.c.

References assert_param, UART_InitTypeDef::BaudRate, UART_InitTypeDef::ClockPrescaler, __UART_HandleTypeDef::FifoMode, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), HAL_RCC_GetSysClockFreq(), HSI_VALUE, UART_InitTypeDef::HwFlowCtl, __UART_HandleTypeDef::Init, __UART_HandleTypeDef::Instance, IS_LPUART_STOPBITS, IS_UART_BAUDRATE, IS_UART_HARDWARE_FLOW_CONTROL, IS_UART_MODE, IS_UART_ONE_BIT_SAMPLE, IS_UART_OVERSAMPLING, IS_UART_PARITY, IS_UART_PRESCALER, IS_UART_STOPBITS, IS_UART_WORD_LENGTH, LPUART_BRR_MAX, LPUART_BRR_MIN, LSE_VALUE, UART_InitTypeDef::Mode, __UART_HandleTypeDef::NbRxDataToProcess, __UART_HandleTypeDef::NbTxDataToProcess, UART_InitTypeDef::OneBitSampling, UART_InitTypeDef::OverSampling, UART_InitTypeDef::Parity, __UART_HandleTypeDef::RxISR, UART_InitTypeDef::StopBits, __UART_HandleTypeDef::TxISR, UART_BRR_MAX, UART_BRR_MIN, UART_CLOCKSOURCE_HSI, UART_CLOCKSOURCE_LSE, UART_CLOCKSOURCE_PCLK1, UART_CLOCKSOURCE_PCLK2, UART_CLOCKSOURCE_SYSCLK, UART_DIV_LPUART, UART_DIV_SAMPLING16, UART_DIV_SAMPLING8, UART_GET_DIV_FACTOR, UART_GETCLOCKSOURCE, UART_INSTANCE_LOWPOWER, UART_OVERSAMPLING_8, USART_CR1_FIELDS, USART_CR3_FIELDS, and UART_InitTypeDef::WordLength.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), and HAL_UART_Init().

static void UART_TxISR_16BIT ( UART_HandleTypeDef * huart ) [static]

TX interrrupt handler for 9 bits data word length.

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_UART_Transmit_IT().
Parameters:
huart UART handle.
Return values:
None

Definition at line 3681 of file stm32wbxx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY_TX, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::pTxBuffPtr, and __UART_HandleTypeDef::TxXferCount.

Referenced by HAL_UART_Transmit_IT().

static void UART_TxISR_16BIT_FIFOEN ( UART_HandleTypeDef * huart ) [static]

TX interrrupt handler for 9 bits data word length and FIFO mode is enabled.

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_UART_Transmit_IT().
Parameters:
huart UART handle.
Return values:
None

Definition at line 3753 of file stm32wbxx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY_TX, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::NbTxDataToProcess, __UART_HandleTypeDef::pTxBuffPtr, and __UART_HandleTypeDef::TxXferCount.

Referenced by HAL_UART_Transmit_IT().

static void UART_TxISR_8BIT ( UART_HandleTypeDef * huart ) [static]

TX interrrupt handler for 7 or 8 bits data word length .

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_UART_Transmit_IT().
Parameters:
huart UART handle.
Return values:
None

Definition at line 3652 of file stm32wbxx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY_TX, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::pTxBuffPtr, and __UART_HandleTypeDef::TxXferCount.

Referenced by HAL_UART_Transmit_IT().

static void UART_TxISR_8BIT_FIFOEN ( UART_HandleTypeDef * huart ) [static]

TX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.

Note:
Function is called under interruption only, once interruptions have been enabled by HAL_UART_Transmit_IT().
Parameters:
huart UART handle.
Return values:
None

Definition at line 3713 of file stm32wbxx_hal_uart.c.

References __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY_TX, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::NbTxDataToProcess, __UART_HandleTypeDef::pTxBuffPtr, and __UART_HandleTypeDef::TxXferCount.

Referenced by HAL_UART_Transmit_IT().

HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Tickstart,
 |  | uint32_t | Timeout
 | ) |  |

Handle UART Communication Timeout.

Parameters:
huart | UART handle.
Flag | Specifies the UART flag to check
Status | Flag status (SET or RESET)
Tickstart | Tick start value
Timeout | Timeout duration
Return values:
HAL status

Definition at line 3224 of file stm32wbxx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, __HAL_UART_GET_FLAG, __UART_HandleTypeDef::ErrorCode, __UART_HandleTypeDef::gState, HAL_GetTick(), HAL_UART_ERROR_RTO, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::RxState, UART_CLEAR_RTOF, and UART_FLAG_RTOF.

Referenced by HAL_UART_Receive(), HAL_UART_Transmit(), HAL_UARTEx_StopModeWakeUpSourceConfig(), and UART_CheckIdleState().

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: UART Exported Types

Data Structures | Typedefs | Enumerations
UART Exported Types
UART

Data Structures

struct | UART_InitTypeDef
UART Init Structure definition. More...
struct | UART_AdvFeatureInitTypeDef
UART Advanced Features initialization structure definition. More...
struct | __UART_HandleTypeDef
UART handle Structure definition. More...

Typedefs

typedef uint32_t | HAL_UART_StateTypeDef
HAL UART State definition.
typedef struct __UART_HandleTypeDef | UART_HandleTypeDef
UART handle Structure definition.
typedef void(* | pUART_CallbackTypeDef )(UART_HandleTypeDef *huart)
HAL UART Callback pointer definition.

Enumerations

enum UART_ClockSourceTypeDef {
UART_CLOCKSOURCE_PCLK1 = 0x00U, UART_CLOCKSOURCE_PCLK2 = 0x01U, UART_CLOCKSOURCE_HSI = 0x02U, UART_CLOCKSOURCE_SYSCLK = 0x04U,
UART_CLOCKSOURCE_LSE = 0x08U, UART_CLOCKSOURCE_UNDEFINED = 0x10U
}
UART clock sources definition. More...
enum HAL_UART_CallbackIDTypeDef {
HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, HAL_UART_TX_COMPLETE_CB_ID = 0x01U, HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, HAL_UART_RX_COMPLETE_CB_ID = 0x03U,
HAL_UART_ERROR_CB_ID = 0x04U, HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U,
HAL_UART_WAKEUP_CB_ID = 0x08U, HAL_UART_RX_FIFO_FULL_CB_ID = 0x09U, HAL_UART_TX_FIFO_EMPTY_CB_ID = 0x0AU, HAL_UART_MSPINIT_CB_ID = 0x0BU,
HAL_UART_MSPDEINIT_CB_ID = 0x0CU
}
HAL UART Callback ID enumeration definition. More...

Typedef Documentation

typedef uint32_t HAL_UART_StateTypeDef

HAL UART State definition.

Note:
HAL UART State value is a combination of 2 different substates: gState and RxState (see UART State Code Definition).
  • gState contains UART state information related to global Handle management and also information related to Tx operations. gState value coding follow below described bitmap : b7-b6 Error information 00 : No Error 01 : (Not Used) 10 : Timeout 11 : Error b5 Peripheral initialization status 0 : Reset (Peripheral not initialized) 1 : Init done (Peripheral not initialized. HAL UART Init function already called) b4-b3 (not used) xx : Should be set to 00 b2 Intrinsic process state 0 : Ready 1 : Busy (Peripheral busy with some configuration or internal operations) b1 (not used) x : Should be set to 0 b0 Tx state 0 : Ready (no Tx operation ongoing) 1 : Busy (Tx operation ongoing)
  • RxState contains information related to Rx operations. RxState value coding follow below described bitmap : b7-b6 (not used) xx : Should be set to 00 b5 Peripheral initialization status 0 : Reset (Peripheral not initialized) 1 : Init done (Peripheral not initialized) b4-b2 (not used) xxx : Should be set to 000 b1 Rx state 0 : Ready (no Rx operation ongoing) 1 : Busy (Rx operation ongoing) b0 (not used) x : Should be set to 0.

Definition at line 177 of file stm32wbxx_hal_uart.h.

typedef void(* pUART_CallbackTypeDef)(UART_HandleTypeDef *huart)

HAL UART Callback pointer definition.

pointer to an UART callback function

Definition at line 288 of file stm32wbxx_hal_uart.h.

typedef struct __UART_HandleTypeDef UART_HandleTypeDef

UART handle Structure definition.

Enumeration Type Documentation

enum HAL_UART_CallbackIDTypeDef

HAL UART Callback ID enumeration definition.

Enumerator:
HAL_UART_TX_HALFCOMPLETE_CB_ID

UART Tx Half Complete Callback ID

HAL_UART_TX_COMPLETE_CB_ID

UART Tx Complete Callback ID

HAL_UART_RX_HALFCOMPLETE_CB_ID

UART Rx Half Complete Callback ID

HAL_UART_RX_COMPLETE_CB_ID

UART Rx Complete Callback ID

HAL_UART_ERROR_CB_ID

UART Error Callback ID

HAL_UART_ABORT_COMPLETE_CB_ID

UART Abort Complete Callback ID

HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID

UART Abort Transmit Complete Callback ID

HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID

UART Abort Receive Complete Callback ID

HAL_UART_WAKEUP_CB_ID

UART Wakeup Callback ID

HAL_UART_RX_FIFO_FULL_CB_ID

UART Rx Fifo Full Callback ID

HAL_UART_TX_FIFO_EMPTY_CB_ID

UART Tx Fifo Empty Callback ID

HAL_UART_MSPINIT_CB_ID

UART MspInit callback ID

HAL_UART_MSPDEINIT_CB_ID

UART MspDeInit callback ID

Definition at line 266 of file stm32wbxx_hal_uart.h.

enum UART_ClockSourceTypeDef

UART clock sources definition.

Enumerator:
UART_CLOCKSOURCE_PCLK1

PCLK1 clock source

UART_CLOCKSOURCE_PCLK2

PCLK2 clock source

UART_CLOCKSOURCE_HSI

HSI clock source

UART_CLOCKSOURCE_SYSCLK

SYSCLK clock source

UART_CLOCKSOURCE_LSE

LSE clock source

UART_CLOCKSOURCE_UNDEFINED

Undefined clock source

Definition at line 182 of file stm32wbxx_hal_uart.h.

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: UART_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
UART_InitTypeDef Struct Reference
UART Exported Types

UART Init Structure definition. More...

#include <stm32wbxx_hal_uart.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | StopBits
uint32_t | Parity
uint32_t | Mode
uint32_t | HwFlowCtl
uint32_t | OverSampling
uint32_t | OneBitSampling
uint32_t | ClockPrescaler

Detailed Description

UART Init Structure definition.

Definition at line 47 of file stm32wbxx_hal_uart.h.

Field Documentation

uint32_t UART_InitTypeDef::BaudRate

This member configures the UART communication baud rate. The baud rate register is computed using the following formula: #if defined(LPUART1) LPUART: ======= Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) where lpuart_ker_ck_pres is the UART input clock divided by a prescaler UART: ===== #endif

  • If oversampling is 16 or in LIN mode, Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate)))
  • If oversampling is 8, Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[15:4] Baud Rate Register[3] = 0 Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[3:0]) >> 1 where uart_ker_ck_pres is the UART input clock divided by a prescaler

Definition at line 49 of file stm32wbxx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::ClockPrescaler

Specifies the prescaler value used to divide the UART clock source. This parameter can be a value of UART Clock Prescaler.

Definition at line 94 of file stm32wbxx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::HwFlowCtl

Specifies whether the hardware flow control mode is enabled or disabled. This parameter can be a value of UART Hardware Flow Control.

Definition at line 83 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_Init(), and UART_SetConfig().

uint32_t UART_InitTypeDef::Mode

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of UART Transfer Mode.

Definition at line 80 of file stm32wbxx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::OneBitSampling

Specifies whether a single sample or three samples' majority vote is selected. Selecting the single sample method increases the receiver tolerance to clock deviations. This parameter can be a value of UART One Bit Sampling Method.

Definition at line 90 of file stm32wbxx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::OverSampling

Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8). This parameter can be a value of UART Over Sampling.

Definition at line 87 of file stm32wbxx_hal_uart.h.

Referenced by HAL_LIN_Init(), and UART_SetConfig().

uint32_t UART_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of UART Parity

Note:
When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits).

Definition at line 73 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_Receive(), HAL_UART_Receive_IT(), HAL_UART_Transmit(), HAL_UART_Transmit_IT(), and UART_SetConfig().

uint32_t UART_InitTypeDef::StopBits

Specifies the number of stop bits transmitted. This parameter can be a value of UART Number of Stop Bits.

Definition at line 70 of file stm32wbxx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of UARTEx Word Length.

Definition at line 67 of file stm32wbxx_hal_uart.h.

Referenced by HAL_LIN_Init(), HAL_UART_Receive(), HAL_UART_Receive_IT(), HAL_UART_Transmit(), HAL_UART_Transmit_IT(), and UART_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_uart.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: UART_AdvFeatureInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
UART_AdvFeatureInitTypeDef Struct Reference
UART Exported Types

UART Advanced Features initialization structure definition. More...

#include <stm32wbxx_hal_uart.h>

Data Fields

uint32_t | AdvFeatureInit
uint32_t | TxPinLevelInvert
uint32_t | RxPinLevelInvert
uint32_t | DataInvert
uint32_t | Swap
uint32_t | OverrunDisable
uint32_t | DMADisableonRxError
uint32_t | AutoBaudRateEnable
uint32_t | AutoBaudRateMode
uint32_t | MSBFirst

Detailed Description

UART Advanced Features initialization structure definition.

Definition at line 102 of file stm32wbxx_hal_uart.h.

Field Documentation

uint32_t UART_AdvFeatureInitTypeDef::AdvFeatureInit

Specifies which advanced UART features is initialized. Several Advanced Features may be initialized at the same time . This parameter can be a value of UART Advanced Feature Initialization Type.

Definition at line 104 of file stm32wbxx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), HAL_UART_Init(), and UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::AutoBaudRateEnable

Specifies whether auto Baud rate detection is enabled. This parameter can be a value of UART Advanced Feature Auto BaudRate Enable.

Definition at line 127 of file stm32wbxx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::AutoBaudRateMode

If auto Baud rate detection is enabled, specifies how the rate detection is carried out. This parameter can be a value of UART Advanced Feature AutoBaud Rate Mode.

Definition at line 130 of file stm32wbxx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::DataInvert

Specifies whether data are inverted (positive/direct logic vs negative/inverted logic). This parameter can be a value of UART Advanced Feature Binary Data Inversion.

Definition at line 114 of file stm32wbxx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::DMADisableonRxError

Specifies whether the DMA is disabled in case of reception error. This parameter can be a value of UART Advanced Feature DMA Disable On Rx Error.

Definition at line 124 of file stm32wbxx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::MSBFirst

Specifies whether MSB is sent first on UART line. This parameter can be a value of UART Advanced Feature MSB First.

Definition at line 134 of file stm32wbxx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::OverrunDisable

Specifies whether the reception overrun detection is disabled. This parameter can be a value of UART Advanced Feature Overrun Disable.

Definition at line 121 of file stm32wbxx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::RxPinLevelInvert

Specifies whether the RX pin active level is inverted. This parameter can be a value of UART Advanced Feature RX Pin Active Level Inversion.

Definition at line 111 of file stm32wbxx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::Swap

Specifies whether TX and RX pins are swapped. This parameter can be a value of UART Advanced Feature RX TX Pins Swap.

Definition at line 118 of file stm32wbxx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

uint32_t UART_AdvFeatureInitTypeDef::TxPinLevelInvert

Specifies whether the TX pin active level is inverted. This parameter can be a value of UART Advanced Feature TX Pin Active Level Inversion.

Definition at line 108 of file stm32wbxx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_uart.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: __UART_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__UART_HandleTypeDef Struct Reference
UART Exported Types

UART handle Structure definition. More...

#include <stm32wbxx_hal_uart.h>

Data Fields

USART_TypeDef * | Instance
UART_InitTypeDef Init
UART_AdvFeatureInitTypeDef AdvancedInit
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
__IO uint16_t | RxXferCount
uint16_t | Mask
uint32_t | FifoMode
uint16_t | NbRxDataToProcess
uint16_t | NbTxDataToProcess
void(* | RxISR )(struct __UART_HandleTypeDef *huart)
void(* | TxISR )(struct __UART_HandleTypeDef *huart)
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_UART_StateTypeDef | gState
__IO HAL_UART_StateTypeDef | RxState
__IO uint32_t | ErrorCode
void(* | TxHalfCpltCallback )(struct __UART_HandleTypeDef *huart)
void(* | TxCpltCallback )(struct __UART_HandleTypeDef *huart)
void(* | RxHalfCpltCallback )(struct __UART_HandleTypeDef *huart)
void(* | RxCpltCallback )(struct __UART_HandleTypeDef *huart)
void(* | ErrorCallback )(struct __UART_HandleTypeDef *huart)
void(* | AbortCpltCallback )(struct __UART_HandleTypeDef *huart)
void(* | AbortTransmitCpltCallback )(struct __UART_HandleTypeDef *huart)
void(* | AbortReceiveCpltCallback )(struct __UART_HandleTypeDef *huart)
void(* | WakeupCallback )(struct __UART_HandleTypeDef *huart)
void(* | RxFifoFullCallback )(struct __UART_HandleTypeDef *huart)
void(* | TxFifoEmptyCallback )(struct __UART_HandleTypeDef *huart)
void(* | MspInitCallback )(struct __UART_HandleTypeDef *huart)
void(* | MspDeInitCallback )(struct __UART_HandleTypeDef *huart)

Detailed Description

UART handle Structure definition.

Definition at line 195 of file stm32wbxx_hal_uart.h.

Field Documentation

void(* __UART_HandleTypeDef::AbortCpltCallback)(struct __UART_HandleTypeDef *huart)

UART Abort Complete Callback

Definition at line 249 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_Abort_IT(), HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), UART_DMARxAbortCallback(), UART_DMATxAbortCallback(), and UART_InitCallbacksToDefault().

void(* __UART_HandleTypeDef::AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart)

UART Abort Receive Complete Callback

Definition at line 251 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_AbortReceive_IT(), HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), UART_DMARxOnlyAbortCallback(), and UART_InitCallbacksToDefault().

void(* __UART_HandleTypeDef::AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart)

UART Abort Transmit Complete Callback

Definition at line 250 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_AbortTransmit_IT(), HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), UART_DMATxOnlyAbortCallback(), and UART_InitCallbacksToDefault().

UART_AdvFeatureInitTypeDef __UART_HandleTypeDef::AdvancedInit

UART Advanced Features initialization parameters

Definition at line 201 of file stm32wbxx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), HAL_UART_Init(), and UART_AdvFeatureConfig().

void(* __UART_HandleTypeDef::ErrorCallback)(struct __UART_HandleTypeDef *huart)

UART Error Callback

Definition at line 248 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), UART_DMAAbortOnError(), UART_DMAError(), and UART_InitCallbacksToDefault().

__IO uint32_t __UART_HandleTypeDef::ErrorCode

UART Error code

Definition at line 241 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortTransmit(), HAL_UART_DeInit(), HAL_UART_DMAStop(), HAL_UART_GetError(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), HAL_UART_RegisterCallback(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), HAL_UART_UnRegisterCallback(), UART_CheckIdleState(), UART_DMAError(), UART_DMARxAbortCallback(), UART_DMATxAbortCallback(), and UART_WaitOnFlagUntilTimeout().

uint32_t __UART_HandleTypeDef::FifoMode

Specifies if the FIFO mode is being used. This parameter can be a value of UARTEx FIFO mode.

Definition at line 217 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_Receive_IT(), HAL_UART_Transmit_IT(), HAL_UARTEx_DisableFifoMode(), HAL_UARTEx_EnableFifoMode(), UART_DMATxAbortCallback(), UART_DMATxOnlyAbortCallback(), UART_SetConfig(), and UARTEx_SetNbDataToProcess().

__IO HAL_UART_StateTypeDef __UART_HandleTypeDef::gState

UART state information related to global Handle management and also related to Tx operations. This parameter can be a value of HAL_UART_StateTypeDef

Definition at line 234 of file stm32wbxx_hal_uart.h.

Referenced by HAL_HalfDuplex_EnableReceiver(), HAL_HalfDuplex_EnableTransmitter(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_LIN_SendBreak(), HAL_MultiProcessor_DisableMuteMode(), HAL_MultiProcessor_EnableMuteMode(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_RS485Ex_Init(), HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_DeInit(), HAL_UART_DisableReceiverTimeout(), HAL_UART_DMAPause(), HAL_UART_DMAResume(), HAL_UART_DMAStop(), HAL_UART_EnableReceiverTimeout(), HAL_UART_GetState(), HAL_UART_Init(), HAL_UART_Receive_DMA(), HAL_UART_RegisterCallback(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), HAL_UART_UnRegisterCallback(), HAL_UARTEx_DisableFifoMode(), HAL_UARTEx_EnableFifoMode(), HAL_UARTEx_SetRxFifoThreshold(), HAL_UARTEx_SetTxFifoThreshold(), HAL_UARTEx_StopModeWakeUpSourceConfig(), UART_CheckIdleState(), UART_DMAError(), UART_DMARxAbortCallback(), UART_DMATxAbortCallback(), UART_DMATxOnlyAbortCallback(), UART_EndTransmit_IT(), UART_EndTxTransfer(), UART_TxISR_16BIT(), UART_TxISR_16BIT_FIFOEN(), UART_TxISR_8BIT(), UART_TxISR_8BIT_FIFOEN(), and UART_WaitOnFlagUntilTimeout().

DMA_HandleTypeDef* __UART_HandleTypeDef::hdmarx

UART Rx DMA Handle parameters

Definition at line 230 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_DMAStop(), HAL_UART_IRQHandler(), HAL_UART_Receive_DMA(), UART_DMARxAbortCallback(), and UART_DMATxAbortCallback().

DMA_HandleTypeDef* __UART_HandleTypeDef::hdmatx

UART Tx DMA Handle parameters

Definition at line 228 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_DMAStop(), HAL_UART_Transmit_DMA(), UART_DMARxAbortCallback(), and UART_DMATxAbortCallback().

UART_InitTypeDef __UART_HandleTypeDef::Init

UART communication parameters

Definition at line 199 of file stm32wbxx_hal_uart.h.

Referenced by HAL_LIN_Init(), HAL_UART_Init(), HAL_UART_Receive(), HAL_UART_Receive_IT(), HAL_UART_Transmit(), HAL_UART_Transmit_IT(), and UART_SetConfig().

USART_TypeDef* __UART_HandleTypeDef::Instance

UART registers base address

Definition at line 197 of file stm32wbxx_hal_uart.h.

Referenced by HAL_HalfDuplex_EnableReceiver(), HAL_HalfDuplex_EnableTransmitter(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_LIN_SendBreak(), HAL_MultiProcessor_DisableMuteMode(), HAL_MultiProcessor_EnableMuteMode(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_RS485Ex_Init(), HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_DeInit(), HAL_UART_DisableReceiverTimeout(), HAL_UART_DMAPause(), HAL_UART_DMAResume(), HAL_UART_DMAStop(), HAL_UART_EnableReceiverTimeout(), HAL_UART_Init(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), HAL_UART_ReceiverTimeout_Config(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), HAL_UARTEx_DisableFifoMode(), HAL_UARTEx_DisableStopMode(), HAL_UARTEx_EnableFifoMode(), HAL_UARTEx_EnableStopMode(), HAL_UARTEx_SetRxFifoThreshold(), HAL_UARTEx_SetTxFifoThreshold(), HAL_UARTEx_StopModeWakeUpSourceConfig(), UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_DMAError(), UART_DMAReceiveCplt(), UART_DMATransmitCplt(), UART_EndRxTransfer(), UART_EndTransmit_IT(), UART_EndTxTransfer(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), UART_RxISR_8BIT_FIFOEN(), UART_SetConfig(), UART_TxISR_16BIT(), UART_TxISR_16BIT_FIFOEN(), UART_TxISR_8BIT(), UART_TxISR_8BIT_FIFOEN(), UART_WaitOnFlagUntilTimeout(), UARTEx_SetNbDataToProcess(), and UARTEx_Wakeup_AddressConfig().

HAL_LockTypeDef __UART_HandleTypeDef::Lock

Locking object

Definition at line 232 of file stm32wbxx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), and HAL_UART_Init().

uint16_t __UART_HandleTypeDef::Mask

UART Rx RDR register mask

Definition at line 215 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_Receive(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

void(* __UART_HandleTypeDef::MspDeInitCallback)(struct __UART_HandleTypeDef *huart)

UART Msp DeInit callback

Definition at line 257 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_DeInit(), HAL_UART_RegisterCallback(), and HAL_UART_UnRegisterCallback().

void(* __UART_HandleTypeDef::MspInitCallback)(struct __UART_HandleTypeDef *huart)

UART Msp Init callback

Definition at line 256 of file stm32wbxx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), HAL_UART_Init(), HAL_UART_RegisterCallback(), and HAL_UART_UnRegisterCallback().

uint16_t __UART_HandleTypeDef::NbRxDataToProcess

Number of data to process during RX ISR execution

Definition at line 220 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_Receive_IT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT_FIFOEN(), UART_SetConfig(), UARTEx_SetNbDataToProcess(), USART_RxISR_16BIT_FIFOEN(), and USART_RxISR_8BIT_FIFOEN().

uint16_t __UART_HandleTypeDef::NbTxDataToProcess

Number of data to process during TX ISR execution

Definition at line 222 of file stm32wbxx_hal_uart.h.

Referenced by UART_SetConfig(), UART_TxISR_16BIT_FIFOEN(), UART_TxISR_8BIT_FIFOEN(), and UARTEx_SetNbDataToProcess().

uint8_t* __UART_HandleTypeDef::pRxBuffPtr

Pointer to UART Rx transfer Buffer

Definition at line 209 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_AbortReceive_IT(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

uint8_t* __UART_HandleTypeDef::pTxBuffPtr

Pointer to UART Tx transfer Buffer

Definition at line 203 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), UART_TxISR_16BIT(), UART_TxISR_16BIT_FIFOEN(), UART_TxISR_8BIT(), and UART_TxISR_8BIT_FIFOEN().

void(* __UART_HandleTypeDef::RxCpltCallback)(struct __UART_HandleTypeDef *huart)

UART Rx Complete Callback

Definition at line 247 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), UART_DMAReceiveCplt(), UART_InitCallbacksToDefault(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

void(* __UART_HandleTypeDef::RxFifoFullCallback)(struct __UART_HandleTypeDef *huart)

UART Rx Fifo Full Callback

Definition at line 253 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), and UART_InitCallbacksToDefault().

void(* __UART_HandleTypeDef::RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart)

UART Rx Half Complete Callback

Definition at line 246 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), UART_DMARxHalfCplt(), and UART_InitCallbacksToDefault().

void(* __UART_HandleTypeDef::RxISR)(struct __UART_HandleTypeDef *huart)

Function pointer on Rx IRQ handler

Definition at line 224 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_Abort_IT(), HAL_UART_IRQHandler(), HAL_UART_Receive_IT(), UART_EndRxTransfer(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), UART_RxISR_8BIT_FIFOEN(), and UART_SetConfig().

__IO HAL_UART_StateTypeDef __UART_HandleTypeDef::RxState

UART state information related to Rx operations. This parameter can be a value of HAL_UART_StateTypeDef

Definition at line 238 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_DeInit(), HAL_UART_DMAPause(), HAL_UART_DMAResume(), HAL_UART_DMAStop(), HAL_UART_GetState(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), UART_CheckIdleState(), UART_DMAError(), UART_DMAReceiveCplt(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), UART_DMATxAbortCallback(), UART_EndRxTransfer(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), UART_RxISR_8BIT_FIFOEN(), and UART_WaitOnFlagUntilTimeout().

__IO uint16_t __UART_HandleTypeDef::RxXferCount

UART Rx Transfer Counter

Definition at line 213 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_Receive(), HAL_UART_Receive_IT(), UART_DMAAbortOnError(), UART_DMAError(), UART_DMAReceiveCplt(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), UART_DMATxAbortCallback(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

uint16_t __UART_HandleTypeDef::RxXferSize

UART Rx Transfer size

Definition at line 211 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_Receive(), HAL_UART_Receive_DMA(), and HAL_UART_Receive_IT().

void(* __UART_HandleTypeDef::TxCpltCallback)(struct __UART_HandleTypeDef *huart)

UART Tx Complete Callback

Definition at line 245 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), UART_DMATransmitCplt(), UART_EndTransmit_IT(), and UART_InitCallbacksToDefault().

void(* __UART_HandleTypeDef::TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart)

UART Tx Fifo Empty Callback

Definition at line 254 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), and UART_InitCallbacksToDefault().

void(* __UART_HandleTypeDef::TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart)

UART Tx Half Complete Callback

Definition at line 244 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), UART_DMATxHalfCplt(), and UART_InitCallbacksToDefault().

void(* __UART_HandleTypeDef::TxISR)(struct __UART_HandleTypeDef *huart)

Function pointer on Tx IRQ handler

Definition at line 226 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_Abort_IT(), HAL_UART_AbortTransmit_IT(), HAL_UART_IRQHandler(), HAL_UART_Transmit_IT(), UART_EndTransmit_IT(), and UART_SetConfig().

__IO uint16_t __UART_HandleTypeDef::TxXferCount

UART Tx Transfer Counter

Definition at line 207 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), UART_DMAAbortOnError(), UART_DMAError(), UART_DMARxAbortCallback(), UART_DMATransmitCplt(), UART_DMATxAbortCallback(), UART_DMATxOnlyAbortCallback(), UART_TxISR_16BIT(), UART_TxISR_16BIT_FIFOEN(), UART_TxISR_8BIT(), and UART_TxISR_8BIT_FIFOEN().

uint16_t __UART_HandleTypeDef::TxXferSize

UART Tx Transfer size

Definition at line 205 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), and HAL_UART_Transmit_IT().

void(* __UART_HandleTypeDef::WakeupCallback)(struct __UART_HandleTypeDef *huart)

UART Wakeup Callback

Definition at line 252 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), HAL_UART_RegisterCallback(), HAL_UART_UnRegisterCallback(), and UART_InitCallbacksToDefault().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_uart.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: UART State Code Definition

Defines
UART State Code Definition
UART Exported Constants

Defines

#define | HAL_UART_STATE_RESET 0x00000000U
#define | HAL_UART_STATE_READY 0x00000020U
#define | HAL_UART_STATE_BUSY 0x00000024U
#define | HAL_UART_STATE_BUSY_TX 0x00000021U
#define | HAL_UART_STATE_BUSY_RX 0x00000022U
#define | HAL_UART_STATE_BUSY_TX_RX 0x00000023U
#define | HAL_UART_STATE_TIMEOUT 0x000000A0U
#define | HAL_UART_STATE_ERROR 0x000000E0U

Define Documentation

#define HAL_UART_STATE_BUSY 0x00000024U

an internal process is ongoing Value is allowed for gState only

Definition at line 308 of file stm32wbxx_hal_uart.h.

Referenced by HAL_HalfDuplex_EnableReceiver(), HAL_HalfDuplex_EnableTransmitter(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_LIN_SendBreak(), HAL_MultiProcessor_DisableMuteMode(), HAL_MultiProcessor_EnableMuteMode(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_RS485Ex_Init(), HAL_UART_DeInit(), HAL_UART_DisableReceiverTimeout(), HAL_UART_EnableReceiverTimeout(), HAL_UART_Init(), HAL_UARTEx_DisableFifoMode(), HAL_UARTEx_EnableFifoMode(), HAL_UARTEx_SetRxFifoThreshold(), HAL_UARTEx_SetTxFifoThreshold(), and HAL_UARTEx_StopModeWakeUpSourceConfig().

#define HAL_UART_STATE_BUSY_RX 0x00000022U

Data Reception process is ongoing Value is allowed for RxState only

Definition at line 312 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_DMAPause(), HAL_UART_DMAResume(), HAL_UART_DMAStop(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), UART_DMAError(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

#define HAL_UART_STATE_BUSY_TX 0x00000021U

Data Transmission process is ongoing Value is allowed for gState only

Definition at line 310 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_DMAPause(), HAL_UART_DMAResume(), HAL_UART_DMAStop(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), UART_DMAError(), UART_TxISR_16BIT(), UART_TxISR_16BIT_FIFOEN(), UART_TxISR_8BIT(), and UART_TxISR_8BIT_FIFOEN().

#define HAL_UART_STATE_BUSY_TX_RX 0x00000023U

Data Transmission and Reception process is ongoing Not to be used for neither gState nor RxState. Value is result of combination (Or) between gState and RxState values

Definition at line 314 of file stm32wbxx_hal_uart.h.

#define HAL_UART_STATE_ERROR 0x000000E0U

Error Value is allowed for gState only

Definition at line 319 of file stm32wbxx_hal_uart.h.

#define HAL_UART_STATE_READY 0x00000020U

Peripheral Initialized and ready for use Value is allowed for gState and RxState

Definition at line 306 of file stm32wbxx_hal_uart.h.

Referenced by HAL_HalfDuplex_EnableReceiver(), HAL_HalfDuplex_EnableTransmitter(), HAL_LIN_SendBreak(), HAL_MultiProcessor_DisableMuteMode(), HAL_MultiProcessor_EnableMuteMode(), HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_DisableReceiverTimeout(), HAL_UART_EnableReceiverTimeout(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), HAL_UART_RegisterCallback(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), HAL_UART_UnRegisterCallback(), HAL_UARTEx_DisableFifoMode(), HAL_UARTEx_EnableFifoMode(), HAL_UARTEx_SetRxFifoThreshold(), HAL_UARTEx_SetTxFifoThreshold(), HAL_UARTEx_StopModeWakeUpSourceConfig(), UART_CheckIdleState(), UART_DMAReceiveCplt(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), UART_DMATxAbortCallback(), UART_DMATxOnlyAbortCallback(), UART_EndRxTransfer(), UART_EndTransmit_IT(), UART_EndTxTransfer(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), UART_RxISR_8BIT_FIFOEN(), and UART_WaitOnFlagUntilTimeout().

#define HAL_UART_STATE_RESET 0x00000000U

Peripheral is not initialized Value is allowed for gState and RxState

Definition at line 304 of file stm32wbxx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), HAL_UART_DeInit(), HAL_UART_Init(), HAL_UART_RegisterCallback(), and HAL_UART_UnRegisterCallback().

#define HAL_UART_STATE_TIMEOUT 0x000000A0U

Timeout state Value is allowed for gState only

Definition at line 317 of file stm32wbxx_hal_uart.h.

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: UART Error Definition

Defines
UART Error Definition
UART Exported Constants

Defines

#define | HAL_UART_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_UART_ERROR_PE ((uint32_t)0x00000001U)
#define | HAL_UART_ERROR_NE ((uint32_t)0x00000002U)
#define | HAL_UART_ERROR_FE ((uint32_t)0x00000004U)
#define | HAL_UART_ERROR_ORE ((uint32_t)0x00000008U)
#define | HAL_UART_ERROR_DMA ((uint32_t)0x00000010U)
#define | HAL_UART_ERROR_RTO ((uint32_t)0x00000020U)
#define | HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U)

Define Documentation

#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U)

DMA transfer error

Definition at line 333 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_AbortReceive(), HAL_UART_AbortTransmit(), HAL_UART_DMAStop(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), and UART_DMAError().

#define HAL_UART_ERROR_FE ((uint32_t)0x00000004U)

Frame error

Definition at line 331 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U)

Invalid Callback error

Definition at line 337 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_RegisterCallback(), and HAL_UART_UnRegisterCallback().

#define HAL_UART_ERROR_NE ((uint32_t)0x00000002U)

Noise error

Definition at line 330 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000U)

No error

Definition at line 328 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_DeInit(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), UART_CheckIdleState(), UART_DMARxAbortCallback(), and UART_DMATxAbortCallback().

#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U)

Overrun error

Definition at line 332 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define HAL_UART_ERROR_PE ((uint32_t)0x00000001U)

Parity error

Definition at line 329 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define HAL_UART_ERROR_RTO ((uint32_t)0x00000020U)

Receiver Timeout error

Definition at line 334 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), and UART_WaitOnFlagUntilTimeout().

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: UART Number of Stop Bits

Defines
UART Number of Stop Bits
UART Exported Constants

Defines

#define | UART_STOPBITS_0_5 USART_CR2_STOP_0
#define | UART_STOPBITS_1 0x00000000U
#define | UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define | UART_STOPBITS_2 USART_CR2_STOP_1

Define Documentation

#define UART_STOPBITS_0_5 USART_CR2_STOP_0

UART frame with 0.5 stop bit

Definition at line 346 of file stm32wbxx_hal_uart.h.

#define UART_STOPBITS_1 0x00000000U

UART frame with 1 stop bit

Definition at line 347 of file stm32wbxx_hal_uart.h.

#define UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)

UART frame with 1.5 stop bits

Definition at line 348 of file stm32wbxx_hal_uart.h.

#define UART_STOPBITS_2 USART_CR2_STOP_1

UART frame with 2 stop bits

Definition at line 349 of file stm32wbxx_hal_uart.h.

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: UART Parity

Defines
UART Parity
UART Exported Constants

Defines

#define | UART_PARITY_NONE 0x00000000U
#define | UART_PARITY_EVEN USART_CR1_PCE
#define | UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Define Documentation

#define UART_PARITY_EVEN USART_CR1_PCE

Even parity

Definition at line 358 of file stm32wbxx_hal_uart.h.

#define UART_PARITY_NONE 0x00000000U

No parity

Definition at line 357 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_Receive(), HAL_UART_Receive_IT(), HAL_UART_Transmit(), and HAL_UART_Transmit_IT().

#define UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Odd parity

Definition at line 359 of file stm32wbxx_hal_uart.h.

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: UART Hardware Flow Control

Defines
UART Hardware Flow Control
UART Exported Constants

Defines

#define | UART_HWCONTROL_NONE 0x00000000U
#define | UART_HWCONTROL_RTS USART_CR3_RTSE
#define | UART_HWCONTROL_CTS USART_CR3_CTSE
#define | UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)

Define Documentation

#define UART_HWCONTROL_CTS USART_CR3_CTSE

Clear To Send

Definition at line 369 of file stm32wbxx_hal_uart.h.

#define UART_HWCONTROL_NONE 0x00000000U

No hardware control

Definition at line 367 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_Init().

#define UART_HWCONTROL_RTS USART_CR3_RTSE

Request To Send

Definition at line 368 of file stm32wbxx_hal_uart.h.

#define UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)

Request and Clear To Send

Definition at line 370 of file stm32wbxx_hal_uart.h.

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: UART Transfer Mode

Defines
UART Transfer Mode
UART Exported Constants

Defines

#define | UART_MODE_RX USART_CR1_RE
#define | UART_MODE_TX USART_CR1_TE
#define | UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)

Define Documentation

#define UART_MODE_RX USART_CR1_RE

RX mode

Definition at line 378 of file stm32wbxx_hal_uart.h.

#define UART_MODE_TX USART_CR1_TE

TX mode

Definition at line 379 of file stm32wbxx_hal_uart.h.

#define UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)

RX and TX mode

Definition at line 380 of file stm32wbxx_hal_uart.h.

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: UART State

Defines
UART State
UART Exported Constants

Defines

#define | UART_STATE_DISABLE 0x00000000U
#define | UART_STATE_ENABLE USART_CR1_UE

Define Documentation

#define UART_STATE_DISABLE 0x00000000U

UART disabled

Definition at line 388 of file stm32wbxx_hal_uart.h.

#define UART_STATE_ENABLE USART_CR1_UE

UART enabled

Definition at line 389 of file stm32wbxx_hal_uart.h.

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: UART Over Sampling

Defines
UART Over Sampling
UART Exported Constants

Defines

#define | UART_OVERSAMPLING_16 0x00000000U
#define | UART_OVERSAMPLING_8 USART_CR1_OVER8

Define Documentation

#define UART_OVERSAMPLING_16 0x00000000U

Oversampling by 16

Definition at line 397 of file stm32wbxx_hal_uart.h.

#define UART_OVERSAMPLING_8 USART_CR1_OVER8

Oversampling by 8

Definition at line 398 of file stm32wbxx_hal_uart.h.

Referenced by HAL_LIN_Init(), and UART_SetConfig().

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STM32WB55xx HAL User Manual: UART One Bit Sampling Method

Defines
UART One Bit Sampling Method
UART Exported Constants

Defines

#define | UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U
#define | UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT

Define Documentation

#define UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U

One-bit sampling disable

Definition at line 406 of file stm32wbxx_hal_uart.h.

#define UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT

One-bit sampling enable

Definition at line 407 of file stm32wbxx_hal_uart.h.

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: UART Clock Prescaler

Defines
UART Clock Prescaler
UART Exported Constants

Defines

#define | UART_PRESCALER_DIV1 0x00000000U
#define | UART_PRESCALER_DIV2 0x00000001U
#define | UART_PRESCALER_DIV4 0x00000002U
#define | UART_PRESCALER_DIV6 0x00000003U
#define | UART_PRESCALER_DIV8 0x00000004U
#define | UART_PRESCALER_DIV10 0x00000005U
#define | UART_PRESCALER_DIV12 0x00000006U
#define | UART_PRESCALER_DIV16 0x00000007U
#define | UART_PRESCALER_DIV32 0x00000008U
#define | UART_PRESCALER_DIV64 0x00000009U
#define | UART_PRESCALER_DIV128 0x0000000AU
#define | UART_PRESCALER_DIV256 0x0000000BU

Define Documentation

#define UART_PRESCALER_DIV1 0x00000000U

fclk_pres = fclk

Definition at line 415 of file stm32wbxx_hal_uart.h.

#define UART_PRESCALER_DIV10 0x00000005U

fclk_pres = fclk/10

Definition at line 420 of file stm32wbxx_hal_uart.h.

#define UART_PRESCALER_DIV12 0x00000006U

fclk_pres = fclk/12

Definition at line 421 of file stm32wbxx_hal_uart.h.

#define UART_PRESCALER_DIV128 0x0000000AU

fclk_pres = fclk/128

Definition at line 425 of file stm32wbxx_hal_uart.h.

#define UART_PRESCALER_DIV16 0x00000007U

fclk_pres = fclk/16

Definition at line 422 of file stm32wbxx_hal_uart.h.

#define UART_PRESCALER_DIV2 0x00000001U

fclk_pres = fclk/2

Definition at line 416 of file stm32wbxx_hal_uart.h.

#define UART_PRESCALER_DIV256 0x0000000BU

fclk_pres = fclk/256

Definition at line 426 of file stm32wbxx_hal_uart.h.

#define UART_PRESCALER_DIV32 0x00000008U

fclk_pres = fclk/32

Definition at line 423 of file stm32wbxx_hal_uart.h.

#define UART_PRESCALER_DIV4 0x00000002U

fclk_pres = fclk/4

Definition at line 417 of file stm32wbxx_hal_uart.h.

#define UART_PRESCALER_DIV6 0x00000003U

fclk_pres = fclk/6

Definition at line 418 of file stm32wbxx_hal_uart.h.

#define UART_PRESCALER_DIV64 0x00000009U

fclk_pres = fclk/64

Definition at line 424 of file stm32wbxx_hal_uart.h.

#define UART_PRESCALER_DIV8 0x00000004U

fclk_pres = fclk/8

Definition at line 419 of file stm32wbxx_hal_uart.h.

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STM32WB55xx HAL User Manual: UART Advanced Feature AutoBaud Rate Mode

Defines
UART Advanced Feature AutoBaud Rate Mode
UART Exported Constants

Defines

#define | UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U
#define | UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0
#define | UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1
#define | UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE

Define Documentation

#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE

Auto Baud rate detection on 0x55 frame detection

Definition at line 437 of file stm32wbxx_hal_uart.h.

#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1

Auto Baud rate detection on 0x7F frame detection

Definition at line 436 of file stm32wbxx_hal_uart.h.

#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0

Auto Baud rate detection on falling edge

Definition at line 435 of file stm32wbxx_hal_uart.h.

#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U

Auto Baud rate detection on start bit

Definition at line 434 of file stm32wbxx_hal_uart.h.

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STM32WB55xx HAL User Manual: UART Receiver Timeout

Defines
UART Receiver Timeout
UART Exported Constants

Defines

#define | UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U
#define | UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN

Define Documentation

#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U

UART Receiver Timeout disable

Definition at line 445 of file stm32wbxx_hal_uart.h.

#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN

UART Receiver Timeout enable

Definition at line 446 of file stm32wbxx_hal_uart.h.

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STM32WB55xx HAL User Manual: UART Local Interconnection Network mode

Defines
UART Local Interconnection Network mode
UART Exported Constants

Defines

#define | UART_LIN_DISABLE 0x00000000U
#define | UART_LIN_ENABLE USART_CR2_LINEN

Define Documentation

#define UART_LIN_DISABLE 0x00000000U

Local Interconnect Network disable

Definition at line 454 of file stm32wbxx_hal_uart.h.

#define UART_LIN_ENABLE USART_CR2_LINEN

Local Interconnect Network enable

Definition at line 455 of file stm32wbxx_hal_uart.h.

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STM32WB55xx HAL User Manual: UART LIN Break Detection

Defines
UART LIN Break Detection
UART Exported Constants

Defines

#define | UART_LINBREAKDETECTLENGTH_10B 0x00000000U
#define | UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL

Define Documentation

#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U

LIN 10-bit break detection length

Definition at line 463 of file stm32wbxx_hal_uart.h.

#define UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL

LIN 11-bit break detection length

Definition at line 464 of file stm32wbxx_hal_uart.h.

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STM32WB55xx HAL User Manual: UART DMA Tx

Defines
UART DMA Tx
UART Exported Constants

Defines

#define | UART_DMA_TX_DISABLE 0x00000000U
#define | UART_DMA_TX_ENABLE USART_CR3_DMAT

Define Documentation

#define UART_DMA_TX_DISABLE 0x00000000U

UART DMA TX disabled

Definition at line 472 of file stm32wbxx_hal_uart.h.

#define UART_DMA_TX_ENABLE USART_CR3_DMAT

UART DMA TX enabled

Definition at line 473 of file stm32wbxx_hal_uart.h.

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STM32WB55xx HAL User Manual: UART DMA Rx

Defines
UART DMA Rx
UART Exported Constants

Defines

#define | UART_DMA_RX_DISABLE 0x00000000U
#define | UART_DMA_RX_ENABLE USART_CR3_DMAR

Define Documentation

#define UART_DMA_RX_DISABLE 0x00000000U

UART DMA RX disabled

Definition at line 481 of file stm32wbxx_hal_uart.h.

#define UART_DMA_RX_ENABLE USART_CR3_DMAR

UART DMA RX enabled

Definition at line 482 of file stm32wbxx_hal_uart.h.

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STM32WB55xx HAL User Manual: UART Half Duplex Selection

Defines
UART Half Duplex Selection
UART Exported Constants

Defines

#define | UART_HALF_DUPLEX_DISABLE 0x00000000U
#define | UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL

Define Documentation

#define UART_HALF_DUPLEX_DISABLE 0x00000000U

UART half-duplex disabled

Definition at line 490 of file stm32wbxx_hal_uart.h.

#define UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL

UART half-duplex enabled

Definition at line 491 of file stm32wbxx_hal_uart.h.

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STM32WB55xx HAL User Manual: UART WakeUp Methods

Defines
UART WakeUp Methods
UART Exported Constants

Defines

#define | UART_WAKEUPMETHOD_IDLELINE 0x00000000U
#define | UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE

Define Documentation

#define UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE

UART wake-up on address mark

Definition at line 500 of file stm32wbxx_hal_uart.h.

Referenced by HAL_MultiProcessor_Init().

#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U

UART wake-up on idle line

Definition at line 499 of file stm32wbxx_hal_uart.h.

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STM32WB55xx HAL User Manual: UART Request Parameters

Defines
UART Request Parameters
UART Exported Constants

Defines

#define | UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ
#define | UART_SENDBREAK_REQUEST USART_RQR_SBKRQ
#define | UART_MUTE_MODE_REQUEST USART_RQR_MMRQ
#define | UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ
#define | UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ

Define Documentation

#define UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ

Auto-Baud Rate Request

Definition at line 508 of file stm32wbxx_hal_uart.h.

#define UART_MUTE_MODE_REQUEST USART_RQR_MMRQ

Mute Mode Request

Definition at line 510 of file stm32wbxx_hal_uart.h.

Referenced by HAL_MultiProcessor_EnterMuteMode().

#define UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ

Receive Data flush Request

Definition at line 511 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

#define UART_SENDBREAK_REQUEST USART_RQR_SBKRQ

Send Break Request

Definition at line 509 of file stm32wbxx_hal_uart.h.

Referenced by HAL_LIN_SendBreak().

#define UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ

Transmit data flush Request

Definition at line 512 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), UART_DMATxAbortCallback(), and UART_DMATxOnlyAbortCallback().

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STM32WB55xx HAL User Manual: UART Advanced Feature Initialization Type

Defines
UART Advanced Feature Initialization Type
UART Exported Constants

Defines

#define | UART_ADVFEATURE_NO_INIT 0x00000000U
#define | UART_ADVFEATURE_TXINVERT_INIT 0x00000001U
#define | UART_ADVFEATURE_RXINVERT_INIT 0x00000002U
#define | UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U
#define | UART_ADVFEATURE_SWAP_INIT 0x00000008U
#define | UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U
#define | UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U
#define | UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U
#define | UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U

Define Documentation

#define UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U

Auto Baud rate detection initialization

Definition at line 527 of file stm32wbxx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U

Binary data inversion

Definition at line 523 of file stm32wbxx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U

DMA disable on Reception Error

Definition at line 526 of file stm32wbxx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U

Most significant bit sent/received first

Definition at line 528 of file stm32wbxx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_NO_INIT 0x00000000U

No advanced feature initialization

Definition at line 520 of file stm32wbxx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_RS485Ex_Init(), and HAL_UART_Init().

#define UART_ADVFEATURE_RXINVERT_INIT 0x00000002U

RX pin active level inversion

Definition at line 522 of file stm32wbxx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U

RX overrun disable

Definition at line 525 of file stm32wbxx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_SWAP_INIT 0x00000008U

TX/RX pins swap

Definition at line 524 of file stm32wbxx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define UART_ADVFEATURE_TXINVERT_INIT 0x00000001U

TX pin active level inversion

Definition at line 521 of file stm32wbxx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

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STM32WB55xx HAL User Manual: UART Advanced Feature TX Pin Active Level Inversion

Defines
UART Advanced Feature TX Pin Active Level Inversion
UART Exported Constants

Defines

#define | UART_ADVFEATURE_TXINV_DISABLE 0x00000000U
#define | UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV

Define Documentation

#define UART_ADVFEATURE_TXINV_DISABLE 0x00000000U

TX pin active level inversion disable

Definition at line 536 of file stm32wbxx_hal_uart.h.

#define UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV

TX pin active level inversion enable

Definition at line 537 of file stm32wbxx_hal_uart.h.

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STM32WB55xx HAL User Manual: UART Advanced Feature RX Pin Active Level Inversion

Defines
UART Advanced Feature RX Pin Active Level Inversion
UART Exported Constants

Defines

#define | UART_ADVFEATURE_RXINV_DISABLE 0x00000000U
#define | UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV

Define Documentation

#define UART_ADVFEATURE_RXINV_DISABLE 0x00000000U

RX pin active level inversion disable

Definition at line 545 of file stm32wbxx_hal_uart.h.

#define UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV

RX pin active level inversion enable

Definition at line 546 of file stm32wbxx_hal_uart.h.

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STM32WB55xx HAL User Manual: UART Advanced Feature Binary Data Inversion

Defines
UART Advanced Feature Binary Data Inversion
UART Exported Constants

Defines

#define | UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U
#define | UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV

Define Documentation

#define UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U

Binary data inversion disable

Definition at line 554 of file stm32wbxx_hal_uart.h.

#define UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV

Binary data inversion enable

Definition at line 555 of file stm32wbxx_hal_uart.h.

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STM32WB55xx HAL User Manual: UART Advanced Feature RX TX Pins Swap

Defines
UART Advanced Feature RX TX Pins Swap
UART Exported Constants

Defines

#define | UART_ADVFEATURE_SWAP_DISABLE 0x00000000U
#define | UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP

Define Documentation

#define UART_ADVFEATURE_SWAP_DISABLE 0x00000000U

TX/RX pins swap disable

Definition at line 563 of file stm32wbxx_hal_uart.h.

#define UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP

TX/RX pins swap enable

Definition at line 564 of file stm32wbxx_hal_uart.h.

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STM32WB55xx HAL User Manual: UART Advanced Feature Overrun Disable

Defines
UART Advanced Feature Overrun Disable
UART Exported Constants

Defines

#define | UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U
#define | UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS

Define Documentation

#define UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS

RX overrun disable

Definition at line 573 of file stm32wbxx_hal_uart.h.

#define UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U

RX overrun enable

Definition at line 572 of file stm32wbxx_hal_uart.h.

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STM32WB55xx HAL User Manual: UART Advanced Feature Auto BaudRate Enable

Defines
UART Advanced Feature Auto BaudRate Enable
UART Exported Constants

Defines

#define | UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U
#define | UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN

Define Documentation

#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U

RX Auto Baud rate detection enable

Definition at line 581 of file stm32wbxx_hal_uart.h.

#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN

RX Auto Baud rate detection disable

Definition at line 582 of file stm32wbxx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

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STM32WB55xx HAL User Manual: UART Advanced Feature DMA Disable On Rx Error

Defines
UART Advanced Feature DMA Disable On Rx Error
UART Exported Constants

Defines

#define | UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U
#define | UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE

Define Documentation

#define UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE

DMA disable on Reception Error

Definition at line 591 of file stm32wbxx_hal_uart.h.

#define UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U

DMA enable on Reception Error

Definition at line 590 of file stm32wbxx_hal_uart.h.

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STM32WB55xx HAL User Manual: UART Advanced Feature MSB First

Defines
UART Advanced Feature MSB First
UART Exported Constants

Defines

#define | UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U
#define | UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST

Define Documentation

#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U

Most significant bit sent/received first disable

Definition at line 599 of file stm32wbxx_hal_uart.h.

#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST

Most significant bit sent/received first enable

Definition at line 600 of file stm32wbxx_hal_uart.h.

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STM32WB55xx HAL User Manual: UART Advanced Feature Stop Mode Enable

Defines
UART Advanced Feature Stop Mode Enable
UART Exported Constants

Defines

#define | UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U
#define | UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM

Define Documentation

#define UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U

UART stop mode disable

Definition at line 608 of file stm32wbxx_hal_uart.h.

#define UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM

UART stop mode enable

Definition at line 609 of file stm32wbxx_hal_uart.h.

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STM32WB55xx HAL User Manual: UART Advanced Feature Mute Mode Enable

Defines
UART Advanced Feature Mute Mode Enable
UART Exported Constants

Defines

#define | UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U
#define | UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME

Define Documentation

#define UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U

UART mute mode disable

Definition at line 617 of file stm32wbxx_hal_uart.h.

#define UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME

UART mute mode enable

Definition at line 618 of file stm32wbxx_hal_uart.h.

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STM32WB55xx HAL User Manual: UART Address-matching LSB Position In CR2 Register

Defines
UART Address-matching LSB Position In CR2 Register
UART Exported Constants

Defines

#define UART_CR2_ADDRESS_LSB_POS 24U

Define Documentation

#define UART_CR2_ADDRESS_LSB_POS 24U

UART address-matching LSB position in CR2 register

Definition at line 626 of file stm32wbxx_hal_uart.h.

Referenced by HAL_MultiProcessor_Init(), and UARTEx_Wakeup_AddressConfig().

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: UART WakeUp From Stop Selection

Defines
UART WakeUp From Stop Selection
UART Exported Constants

Defines

#define | UART_WAKEUP_ON_ADDRESS 0x00000000U
#define | UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1
#define | UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS

Define Documentation

#define UART_WAKEUP_ON_ADDRESS 0x00000000U

UART wake-up on address

Definition at line 634 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig().

#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS

UART wake-up on receive data register not empty or RXFIFO is not empty

Definition at line 636 of file stm32wbxx_hal_uart.h.

#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1

UART wake-up on start bit

Definition at line 635 of file stm32wbxx_hal_uart.h.

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STM32WB55xx HAL User Manual: UART DriverEnable Polarity

Defines
UART DriverEnable Polarity
UART Exported Constants

Defines

#define | UART_DE_POLARITY_HIGH 0x00000000U
#define | UART_DE_POLARITY_LOW USART_CR3_DEP

Define Documentation

#define UART_DE_POLARITY_HIGH 0x00000000U

Driver enable signal is active high

Definition at line 644 of file stm32wbxx_hal_uart.h.

#define UART_DE_POLARITY_LOW USART_CR3_DEP

Driver enable signal is active low

Definition at line 645 of file stm32wbxx_hal_uart.h.

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STM32WB55xx HAL User Manual: UART Driver Enable Assertion Time LSB Position In CR1 Register

Defines
UART Driver Enable Assertion Time LSB Position In CR1 Register
UART Exported Constants

Defines

#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U

Define Documentation

#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U

UART Driver Enable assertion time LSB position in CR1 register

Definition at line 653 of file stm32wbxx_hal_uart.h.

Referenced by HAL_RS485Ex_Init().

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STM32WB55xx HAL User Manual: UART Driver Enable DeAssertion Time LSB Position In CR1 Register

Defines
UART Driver Enable DeAssertion Time LSB Position In CR1 Register
UART Exported Constants

Defines

#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U

Define Documentation

#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U

UART Driver Enable de-assertion time LSB position in CR1 register

Definition at line 661 of file stm32wbxx_hal_uart.h.

Referenced by HAL_RS485Ex_Init().

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STM32WB55xx HAL User Manual: UART Interruptions Flag Mask

Defines
UART Interruptions Flag Mask
UART Exported Constants

Defines

#define UART_IT_MASK 0x001FU

Define Documentation

#define UART_IT_MASK 0x001FU

UART interruptions flags mask

Definition at line 669 of file stm32wbxx_hal_uart.h.

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: UART polling-based communications time-out value

Defines
UART polling-based communications time-out value
UART Exported Constants

Defines

#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU

Define Documentation

#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU

UART polling-based communications time-out value

Definition at line 677 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig(), and UART_CheckIdleState().

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: UART Status Flags

Defines
UART Status Flags
UART Exported Constants

Elements values convention: 0xXXXX. More...

Defines

#define | UART_FLAG_TXFT USART_ISR_TXFT
#define | UART_FLAG_RXFT USART_ISR_RXFT
#define | UART_FLAG_RXFF USART_ISR_RXFF
#define | UART_FLAG_TXFE USART_ISR_TXFE
#define | UART_FLAG_REACK USART_ISR_REACK
#define | UART_FLAG_TEACK USART_ISR_TEACK
#define | UART_FLAG_WUF USART_ISR_WUF
#define | UART_FLAG_RWU USART_ISR_RWU
#define | UART_FLAG_SBKF USART_ISR_SBKF
#define | UART_FLAG_CMF USART_ISR_CMF
#define | UART_FLAG_BUSY USART_ISR_BUSY
#define | UART_FLAG_ABRF USART_ISR_ABRF
#define | UART_FLAG_ABRE USART_ISR_ABRE
#define | UART_FLAG_RTOF USART_ISR_RTOF
#define | UART_FLAG_CTS USART_ISR_CTS
#define | UART_FLAG_CTSIF USART_ISR_CTSIF
#define | UART_FLAG_LBDF USART_ISR_LBDF
#define | UART_FLAG_TXE USART_ISR_TXE_TXFNF
#define | UART_FLAG_TXFNF USART_ISR_TXE_TXFNF
#define | UART_FLAG_TC USART_ISR_TC
#define | UART_FLAG_RXNE USART_ISR_RXNE_RXFNE
#define | UART_FLAG_RXFNE USART_ISR_RXNE_RXFNE
#define | UART_FLAG_IDLE USART_ISR_IDLE
#define | UART_FLAG_ORE USART_ISR_ORE
#define | UART_FLAG_NE USART_ISR_NE
#define | UART_FLAG_FE USART_ISR_FE
#define | UART_FLAG_PE USART_ISR_PE

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the ISR register

Define Documentation

#define UART_FLAG_ABRE USART_ISR_ABRE

UART auto Baud rate error

Definition at line 699 of file stm32wbxx_hal_uart.h.

#define UART_FLAG_ABRF USART_ISR_ABRF

UART auto Baud rate flag

Definition at line 698 of file stm32wbxx_hal_uart.h.

#define UART_FLAG_BUSY USART_ISR_BUSY

UART busy flag

Definition at line 697 of file stm32wbxx_hal_uart.h.

#define UART_FLAG_CMF USART_ISR_CMF

UART character match flag

Definition at line 696 of file stm32wbxx_hal_uart.h.

#define UART_FLAG_CTS USART_ISR_CTS

UART clear to send flag

Definition at line 701 of file stm32wbxx_hal_uart.h.

#define UART_FLAG_CTSIF USART_ISR_CTSIF

UART clear to send interrupt flag

Definition at line 702 of file stm32wbxx_hal_uart.h.

#define UART_FLAG_FE USART_ISR_FE

UART frame error

Definition at line 712 of file stm32wbxx_hal_uart.h.

#define UART_FLAG_IDLE USART_ISR_IDLE

UART idle flag

Definition at line 709 of file stm32wbxx_hal_uart.h.

#define UART_FLAG_LBDF USART_ISR_LBDF

UART LIN break detection flag

Definition at line 703 of file stm32wbxx_hal_uart.h.

#define UART_FLAG_NE USART_ISR_NE

UART noise error

Definition at line 711 of file stm32wbxx_hal_uart.h.

#define UART_FLAG_ORE USART_ISR_ORE

UART overrun error

Definition at line 710 of file stm32wbxx_hal_uart.h.

#define UART_FLAG_PE USART_ISR_PE

UART parity error

Definition at line 713 of file stm32wbxx_hal_uart.h.

#define UART_FLAG_REACK USART_ISR_REACK

UART receive enable acknowledge flag

Definition at line 691 of file stm32wbxx_hal_uart.h.

#define UART_FLAG_RTOF USART_ISR_RTOF

UART receiver timeout flag

Definition at line 700 of file stm32wbxx_hal_uart.h.

Referenced by UART_WaitOnFlagUntilTimeout().

#define UART_FLAG_RWU USART_ISR_RWU

UART receiver wake-up from mute mode flag

Definition at line 694 of file stm32wbxx_hal_uart.h.

#define UART_FLAG_RXFF USART_ISR_RXFF

UART RXFIFO Full flag

Definition at line 689 of file stm32wbxx_hal_uart.h.

#define UART_FLAG_RXFNE USART_ISR_RXNE_RXFNE

UART RXFIFO not empty

Definition at line 708 of file stm32wbxx_hal_uart.h.

#define UART_FLAG_RXFT USART_ISR_RXFT

UART RXFIFO threshold flag

Definition at line 688 of file stm32wbxx_hal_uart.h.

#define UART_FLAG_RXNE USART_ISR_RXNE_RXFNE

UART read data register not empty

Definition at line 707 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_Receive().

#define UART_FLAG_SBKF USART_ISR_SBKF

UART send break flag

Definition at line 695 of file stm32wbxx_hal_uart.h.

#define UART_FLAG_TC USART_ISR_TC

UART transmission complete

Definition at line 706 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_Transmit().

#define UART_FLAG_TEACK USART_ISR_TEACK

UART transmit enable acknowledge flag

Definition at line 692 of file stm32wbxx_hal_uart.h.

#define UART_FLAG_TXE USART_ISR_TXE_TXFNF

UART transmit data register empty

Definition at line 704 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_Transmit().

#define UART_FLAG_TXFE USART_ISR_TXFE

UART TXFIFO Empty flag

Definition at line 690 of file stm32wbxx_hal_uart.h.

#define UART_FLAG_TXFNF USART_ISR_TXE_TXFNF

UART TXFIFO not full

Definition at line 705 of file stm32wbxx_hal_uart.h.

#define UART_FLAG_TXFT USART_ISR_TXFT

UART TXFIFO threshold flag

Definition at line 687 of file stm32wbxx_hal_uart.h.

#define UART_FLAG_WUF USART_ISR_WUF

UART wake-up from stop mode flag

Definition at line 693 of file stm32wbxx_hal_uart.h.

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: UART Interrupts Definition

Defines
UART Interrupts Definition
UART Exported Constants

Elements values convention: 000ZZZZZ0XXYYYYYb. More...

Defines

#define | UART_IT_PE 0x0028U
#define | UART_IT_TXE 0x0727U
#define | UART_IT_TXFNF 0x0727U
#define | UART_IT_TC 0x0626U
#define | UART_IT_RXNE 0x0525U
#define | UART_IT_RXFNE 0x0525U
#define | UART_IT_IDLE 0x0424U
#define | UART_IT_LBD 0x0846U
#define | UART_IT_CTS 0x096AU
#define | UART_IT_CM 0x112EU
#define | UART_IT_WUF 0x1476U
#define | UART_IT_RXFF 0x183FU
#define | UART_IT_TXFE 0x173EU
#define | UART_IT_RXFT 0x1A7CU
#define | UART_IT_TXFT 0x1B77U
#define | UART_IT_RTO 0x0B3AU
#define | UART_IT_ERR 0x0060U
#define | UART_IT_ORE 0x0300U
#define | UART_IT_NE 0x0200U
#define | UART_IT_FE 0x0100U

Detailed Description

Elements values convention: 000ZZZZZ0XXYYYYYb.

  • YYYYY : Interrupt source position in the XX register (5bits)
  • XX : Interrupt source register (2bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register
  • ZZZZZ : Flag position in the ISR register(5bits) Elements values convention: 000000000XXYYYYYb
  • YYYYY : Interrupt source position in the XX register (5bits)
  • XX : Interrupt source register (2bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register Elements values convention: 0000ZZZZ00000000b
  • ZZZZ : Flag position in the ISR register(4bits)

Define Documentation

#define UART_IT_CM 0x112EU

UART character match interruption

Definition at line 745 of file stm32wbxx_hal_uart.h.

#define UART_IT_CTS 0x096AU

UART CTS interruption

Definition at line 744 of file stm32wbxx_hal_uart.h.

#define UART_IT_ERR 0x0060U

UART error interruption

Definition at line 753 of file stm32wbxx_hal_uart.h.

#define UART_IT_FE 0x0100U

UART frame error interruption

Definition at line 757 of file stm32wbxx_hal_uart.h.

#define UART_IT_IDLE 0x0424U

UART idle interruption

Definition at line 742 of file stm32wbxx_hal_uart.h.

#define UART_IT_LBD 0x0846U

UART LIN break detection interruption

Definition at line 743 of file stm32wbxx_hal_uart.h.

#define UART_IT_NE 0x0200U

UART noise error interruption

Definition at line 756 of file stm32wbxx_hal_uart.h.

#define UART_IT_ORE 0x0300U

UART overrun error interruption

Definition at line 755 of file stm32wbxx_hal_uart.h.

#define UART_IT_PE 0x0028U

UART parity error interruption

Definition at line 736 of file stm32wbxx_hal_uart.h.

#define UART_IT_RTO 0x0B3AU

UART receiver timeout interruption

Definition at line 751 of file stm32wbxx_hal_uart.h.

#define UART_IT_RXFF 0x183FU

UART RXFIFO full interruption

Definition at line 747 of file stm32wbxx_hal_uart.h.

#define UART_IT_RXFNE 0x0525U

UART RXFIFO not empty interruption

Definition at line 741 of file stm32wbxx_hal_uart.h.

#define UART_IT_RXFT 0x1A7CU

UART RXFIFO threshold reached interruption

Definition at line 749 of file stm32wbxx_hal_uart.h.

#define UART_IT_RXNE 0x0525U

UART read data register not empty interruption

Definition at line 740 of file stm32wbxx_hal_uart.h.

#define UART_IT_TC 0x0626U

UART transmission complete interruption

Definition at line 739 of file stm32wbxx_hal_uart.h.

#define UART_IT_TXE 0x0727U

UART transmit data register empty interruption

Definition at line 737 of file stm32wbxx_hal_uart.h.

#define UART_IT_TXFE 0x173EU

UART TXFIFO empty interruption

Definition at line 748 of file stm32wbxx_hal_uart.h.

#define UART_IT_TXFNF 0x0727U

UART TX FIFO not full interruption

Definition at line 738 of file stm32wbxx_hal_uart.h.

#define UART_IT_TXFT 0x1B77U

UART TXFIFO threshold reached interruption

Definition at line 750 of file stm32wbxx_hal_uart.h.

#define UART_IT_WUF 0x1476U

UART wake-up from stop mode interruption

Definition at line 746 of file stm32wbxx_hal_uart.h.

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: UART Interruption Clear Flags

Defines
UART Interruption Clear Flags
UART Exported Constants

Defines

#define | UART_CLEAR_PEF USART_ICR_PECF
#define | UART_CLEAR_FEF USART_ICR_FECF
#define | UART_CLEAR_NEF USART_ICR_NECF
#define | UART_CLEAR_OREF USART_ICR_ORECF
#define | UART_CLEAR_IDLEF USART_ICR_IDLECF
#define | UART_CLEAR_TXFECF USART_ICR_TXFECF
#define | UART_CLEAR_TCF USART_ICR_TCCF
#define | UART_CLEAR_LBDF USART_ICR_LBDCF
#define | UART_CLEAR_CTSF USART_ICR_CTSCF
#define | UART_CLEAR_CMF USART_ICR_CMCF
#define | UART_CLEAR_WUF USART_ICR_WUCF
#define | UART_CLEAR_RTOF USART_ICR_RTOCF

Define Documentation

#define UART_CLEAR_CMF USART_ICR_CMCF

Character Match Clear Flag

Definition at line 774 of file stm32wbxx_hal_uart.h.

#define UART_CLEAR_CTSF USART_ICR_CTSCF

CTS Interrupt Clear Flag

Definition at line 773 of file stm32wbxx_hal_uart.h.

#define UART_CLEAR_FEF USART_ICR_FECF

Framing Error Clear Flag

Definition at line 766 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_IRQHandler(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), and UART_DMATxAbortCallback().

#define UART_CLEAR_IDLEF USART_ICR_IDLECF

IDLE line detected Clear Flag

Definition at line 769 of file stm32wbxx_hal_uart.h.

#define UART_CLEAR_LBDF USART_ICR_LBDCF

LIN Break Detection Clear Flag

Definition at line 772 of file stm32wbxx_hal_uart.h.

#define UART_CLEAR_NEF USART_ICR_NECF

Noise Error detected Clear Flag

Definition at line 767 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_IRQHandler(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), and UART_DMATxAbortCallback().

#define UART_CLEAR_OREF USART_ICR_ORECF

Overrun Error Clear Flag

Definition at line 768 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_DMAResume(), HAL_UART_IRQHandler(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), and UART_DMATxAbortCallback().

#define UART_CLEAR_PEF USART_ICR_PECF

Parity Error Clear Flag

Definition at line 765 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_IRQHandler(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), and UART_DMATxAbortCallback().

#define UART_CLEAR_RTOF USART_ICR_RTOCF

UART receiver timeout clear flag

Definition at line 776 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_IRQHandler(), and UART_WaitOnFlagUntilTimeout().

#define UART_CLEAR_TCF USART_ICR_TCCF

Transmission Complete Clear Flag

Definition at line 771 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_Transmit_DMA().

#define UART_CLEAR_TXFECF USART_ICR_TXFECF

TXFIFO empty clear flag

Definition at line 770 of file stm32wbxx_hal_uart.h.

#define UART_CLEAR_WUF USART_ICR_WUCF

Wake Up from stop mode Clear Flag

Definition at line 775 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: UART Exported Macros

Defines
UART Exported Macros
UART

Defines

#define | __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)
Reset UART handle states.
#define | __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)
Flush the UART Data registers.
#define | __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified UART pending flag.
#define | __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
Clear the UART PE pending flag.
#define | __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
Clear the UART FE pending flag.
#define | __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
Clear the UART NE pending flag.
#define | __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
Clear the UART ORE pending flag.
#define | __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
Clear the UART IDLE pending flag.
#define | __HAL_UART_CLEAR_TXFECF(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF)
Clear the UART TX FIFO empty clear flag.
#define | __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified UART flag is set or not.
#define | __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified UART interrupt.
#define | __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified UART interrupt.
#define | __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__)
Check whether the specified UART interrupt has occurred or not.
#define | __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified UART interrupt source is enabled or not.
#define | __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified UART ISR flag, in setting the proper ICR register flag.
#define | __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific UART request flag.
#define | __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the UART one bit sample method.
#define | __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
Disable the UART one bit sample method.
#define | __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable UART.
#define | __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable UART.
#define | __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)
Enable CTS flow control.
#define | __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)
Disable CTS flow control.
#define | __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)
Enable RTS flow control.
#define | __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)
Disable RTS flow control.

Define Documentation

#define __HAL_UART_CLEAR_FEFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)

Clear the UART FE pending flag.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 849 of file stm32wbxx_hal_uart.h.

#define __HAL_UART_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the specified UART pending flag.

Parameters:
__HANDLE__ specifies the UART Handle.
__FLAG__ specifies the flag to check. This parameter can be any combination of the following values:
  • UART_CLEAR_PEF Parity Error Clear Flag
  • UART_CLEAR_FEF Framing Error Clear Flag
  • UART_CLEAR_NEF Noise detected Clear Flag
  • UART_CLEAR_OREF Overrun Error Clear Flag
  • UART_CLEAR_IDLEF IDLE line detected Clear Flag
  • UART_CLEAR_TXFECF TXFIFO empty clear Flag
  • UART_CLEAR_TCF Transmission Complete Clear Flag
  • UART_CLEAR_RTOF Receiver Timeout clear flag
  • UART_CLEAR_LBDF LIN Break Detection Clear Flag
  • UART_CLEAR_CTSF CTS Interrupt Clear Flag
  • UART_CLEAR_CMF Character Match Clear Flag
  • UART_CLEAR_WUF Wake Up from stop mode Clear Flag
Return values:
None

Definition at line 837 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_DMAResume(), HAL_UART_IRQHandler(), HAL_UART_Transmit_DMA(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), UART_DMATxAbortCallback(), and UART_WaitOnFlagUntilTimeout().

#define __HAL_UART_CLEAR_IDLEFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)

Clear the UART IDLE pending flag.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 867 of file stm32wbxx_hal_uart.h.

#define __HAL_UART_CLEAR_IT | ( | __HANDLE__,
 |  | __IT_CLEAR__
 | ) | ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))

Clear the specified UART ISR flag, in setting the proper ICR register flag.

Parameters:
__HANDLE__ specifies the UART Handle.
__IT_CLEAR__ specifies the interrupt clear register flag that needs to be set to clear the corresponding interrupt This parameter can be one of the following values:
  • UART_CLEAR_PEF Parity Error Clear Flag
  • UART_CLEAR_FEF Framing Error Clear Flag
  • UART_CLEAR_NEF Noise detected Clear Flag
  • UART_CLEAR_OREF Overrun Error Clear Flag
  • UART_CLEAR_IDLEF IDLE line detected Clear Flag
  • UART_CLEAR_RTOF Receiver timeout clear flag
  • UART_CLEAR_TXFECF TXFIFO empty Clear Flag
  • UART_CLEAR_TCF Transmission Complete Clear Flag
  • UART_CLEAR_LBDF LIN Break Detection Clear Flag
  • UART_CLEAR_CTSF CTS Interrupt Clear Flag
  • UART_CLEAR_CMF Character Match Clear Flag
  • UART_CLEAR_WUF Wake Up from stop mode Clear Flag
Return values:
None

Definition at line 1036 of file stm32wbxx_hal_uart.h.

#define __HAL_UART_CLEAR_NEFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)

Clear the UART NE pending flag.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 855 of file stm32wbxx_hal_uart.h.

#define __HAL_UART_CLEAR_OREFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)

Clear the UART ORE pending flag.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 861 of file stm32wbxx_hal_uart.h.

#define __HAL_UART_CLEAR_PEFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)

Clear the UART PE pending flag.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 843 of file stm32wbxx_hal_uart.h.

#define __HAL_UART_CLEAR_TXFECF ( __HANDLE__ ) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF)

Clear the UART TX FIFO empty clear flag.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 873 of file stm32wbxx_hal_uart.h.

#define __HAL_UART_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

Disable UART.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 1073 of file stm32wbxx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_RS485Ex_Init(), HAL_UART_DeInit(), HAL_UART_Init(), HAL_UARTEx_DisableFifoMode(), HAL_UARTEx_EnableFifoMode(), HAL_UARTEx_SetRxFifoThreshold(), HAL_UARTEx_SetTxFifoThreshold(), and HAL_UARTEx_StopModeWakeUpSourceConfig().

#define __HAL_UART_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
                                                           ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))

Disable the specified UART interrupt.

Parameters:
__HANDLE__ specifies the UART Handle.
__INTERRUPT__ specifies the UART interrupt source to disable. This parameter can be one of the following values:
  • UART_IT_RXFF RXFIFO Full interrupt
  • UART_IT_TXFE TXFIFO Empty interrupt
  • UART_IT_RXFT RXFIFO threshold interrupt
  • UART_IT_TXFT TXFIFO threshold interrupt
  • UART_IT_WUF Wakeup from stop mode interrupt
  • UART_IT_CM Character match interrupt
  • UART_IT_CTS CTS change interrupt
  • UART_IT_LBD LIN Break detection interrupt
  • UART_IT_TXE Transmit Data Register empty interrupt
  • UART_IT_TXFNF TX FIFO not full interrupt
  • UART_IT_TC Transmission complete interrupt
  • UART_IT_RXNE Receive Data register not empty interrupt
  • UART_IT_RXFNE RXFIFO not empty interrupt
  • UART_IT_RTO Receive Timeout interrupt
  • UART_IT_IDLE Idle line detection interrupt
  • UART_IT_PE Parity Error interrupt
  • UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
Return values:
None

Definition at line 960 of file stm32wbxx_hal_uart.h.

#define __HAL_UART_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

Enable UART.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 1067 of file stm32wbxx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_RS485Ex_Init(), HAL_UART_Init(), and HAL_UARTEx_StopModeWakeUpSourceConfig().

#define __HAL_UART_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
                                                           ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))

Enable the specified UART interrupt.

Parameters:
__HANDLE__ specifies the UART Handle.
__INTERRUPT__ specifies the UART interrupt source to enable. This parameter can be one of the following values:
  • UART_IT_RXFF RXFIFO Full interrupt
  • UART_IT_TXFE TXFIFO Empty interrupt
  • UART_IT_RXFT RXFIFO threshold interrupt
  • UART_IT_TXFT TXFIFO threshold interrupt
  • UART_IT_WUF Wakeup from stop mode interrupt
  • UART_IT_CM Character match interrupt
  • UART_IT_CTS CTS change interrupt
  • UART_IT_LBD LIN Break detection interrupt
  • UART_IT_TXE Transmit Data Register empty interrupt
  • UART_IT_TXFNF TX FIFO not full interrupt
  • UART_IT_TC Transmission complete interrupt
  • UART_IT_RXNE Receive Data register not empty interrupt
  • UART_IT_RXFNE RXFIFO not empty interrupt
  • UART_IT_RTO Receive Timeout interrupt
  • UART_IT_IDLE Idle line detection interrupt
  • UART_IT_PE Parity Error interrupt
  • UART_IT_ERR Error interrupt (frame error, noise error, overrun error)
Return values:
None

Definition at line 932 of file stm32wbxx_hal_uart.h.

#define __HAL_UART_FLUSH_DRREGISTER ( __HANDLE__ )
Value:
do{                \
    SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
    SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
  }  while(0U)

Flush the UART Data registers.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 813 of file stm32wbxx_hal_uart.h.

#define __HAL_UART_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))

Check whether the specified UART flag is set or not.

Parameters:
__HANDLE__ specifies the UART Handle.
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • UART_FLAG_TXFT TXFIFO threshold flag
  • UART_FLAG_RXFT RXFIFO threshold flag
  • UART_FLAG_RXFF RXFIFO Full flag
  • UART_FLAG_TXFE TXFIFO Empty flag
  • UART_FLAG_REACK Receive enable acknowledge flag
  • UART_FLAG_TEACK Transmit enable acknowledge flag
  • UART_FLAG_WUF Wake up from stop mode flag
  • UART_FLAG_RWU Receiver wake up flag (if the UART in mute mode)
  • UART_FLAG_SBKF Send Break flag
  • UART_FLAG_CMF Character match flag
  • UART_FLAG_BUSY Busy flag
  • UART_FLAG_ABRF Auto Baud rate detection flag
  • UART_FLAG_ABRE Auto Baud rate detection error flag
  • UART_FLAG_CTS CTS Change flag
  • UART_FLAG_LBDF LIN Break detection flag
  • UART_FLAG_TXE Transmit data register empty flag
  • UART_FLAG_TXFNF UART TXFIFO not full flag
  • UART_FLAG_TC Transmission Complete flag
  • UART_FLAG_RXNE Receive data register not empty flag
  • UART_FLAG_RXFNE UART RXFIFO not empty flag
  • UART_FLAG_RTOF Receiver Timeout flag
  • UART_FLAG_IDLE Idle Line detection flag
  • UART_FLAG_ORE Overrun Error flag
  • UART_FLAG_NE Noise Error flag
  • UART_FLAG_FE Framing Error flag
  • UART_FLAG_PE Parity Error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 907 of file stm32wbxx_hal_uart.h.

Referenced by UART_WaitOnFlagUntilTimeout().

#define __HAL_UART_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__HANDLE__)->Instance->ISR\
                                                        & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET)

Check whether the specified UART interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the UART Handle.
__INTERRUPT__ specifies the UART interrupt to check. This parameter can be one of the following values:
  • UART_IT_RXFF RXFIFO Full interrupt
  • UART_IT_TXFE TXFIFO Empty interrupt
  • UART_IT_RXFT RXFIFO threshold interrupt
  • UART_IT_TXFT TXFIFO threshold interrupt
  • UART_IT_WUF Wakeup from stop mode interrupt
  • UART_IT_CM Character match interrupt
  • UART_IT_CTS CTS change interrupt
  • UART_IT_LBD LIN Break detection interrupt
  • UART_IT_TXE Transmit Data Register empty interrupt
  • UART_IT_TXFNF TX FIFO not full interrupt
  • UART_IT_TC Transmission complete interrupt
  • UART_IT_RXNE Receive Data register not empty interrupt
  • UART_IT_RXFNE RXFIFO not empty interrupt
  • UART_IT_RTO Receive Timeout interrupt
  • UART_IT_IDLE Idle line detection interrupt
  • UART_IT_PE Parity Error interrupt
  • UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 987 of file stm32wbxx_hal_uart.h.

#define __HAL_UART_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : \
                                                                (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \
                                                                 (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK)))  != RESET) ? SET : RESET)

Check whether the specified UART interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the UART Handle.
__INTERRUPT__ specifies the UART interrupt source to check. This parameter can be one of the following values:
  • UART_IT_RXFF RXFIFO Full interrupt
  • UART_IT_TXFE TXFIFO Empty interrupt
  • UART_IT_RXFT RXFIFO threshold interrupt
  • UART_IT_TXFT TXFIFO threshold interrupt
  • UART_IT_WUF Wakeup from stop mode interrupt
  • UART_IT_CM Character match interrupt
  • UART_IT_CTS CTS change interrupt
  • UART_IT_LBD LIN Break detection interrupt
  • UART_IT_TXE Transmit Data Register empty interrupt
  • UART_IT_TXFNF TX FIFO not full interrupt
  • UART_IT_TC Transmission complete interrupt
  • UART_IT_RXNE Receive Data register not empty interrupt
  • UART_IT_RXFNE RXFIFO not empty interrupt
  • UART_IT_RTO Receive Timeout interrupt
  • UART_IT_IDLE Idle line detection interrupt
  • UART_IT_PE Parity Error interrupt
  • UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 1013 of file stm32wbxx_hal_uart.h.

#define __HAL_UART_HWCONTROL_CTS_DISABLE ( __HANDLE__ )
Value:
do{                                                       \
    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);      \
  } while(0U)

Disable CTS flow control.

Note:
This macro allows to disable CTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function. As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
As macro is expected to be used for modifying CTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 1105 of file stm32wbxx_hal_uart.h.

#define __HAL_UART_HWCONTROL_CTS_ENABLE ( __HANDLE__ )
Value:
do{                                                      \
    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;        \
  } while(0U)

Enable CTS flow control.

Note:
This macro allows to enable CTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function. As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
As macro is expected to be used for modifying CTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 1087 of file stm32wbxx_hal_uart.h.

#define __HAL_UART_HWCONTROL_RTS_DISABLE ( __HANDLE__ )
Value:
do{                                                      \
    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);     \
  } while(0U)

Disable RTS flow control.

Note:
This macro allows to disable RTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function. As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
As macro is expected to be used for modifying RTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 1141 of file stm32wbxx_hal_uart.h.

#define __HAL_UART_HWCONTROL_RTS_ENABLE ( __HANDLE__ )
Value:
do{                                                     \
    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;       \
  } while(0U)

Enable RTS flow control.

Note:
This macro allows to enable RTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function. As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
As macro is expected to be used for modifying RTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 1123 of file stm32wbxx_hal_uart.h.

#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)

Disable the UART one bit sample method.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 1061 of file stm32wbxx_hal_uart.h.

#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)

Enable the UART one bit sample method.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None

Definition at line 1055 of file stm32wbxx_hal_uart.h.

#define __HAL_UART_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                   \
                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
                                                       (__HANDLE__)->MspInitCallback = NULL;             \
                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \
                                                     } while(0U)

Reset UART handle states.

Parameters:
__HANDLE__ UART handle.
Return values:
None

Definition at line 796 of file stm32wbxx_hal_uart.h.

#define __HAL_UART_SEND_REQ | ( | __HANDLE__,
 |  | __REQ__
 | ) | ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))

Set a specific UART request flag.

Parameters:
__HANDLE__ specifies the UART Handle.
__REQ__ specifies the request flag to set This parameter can be one of the following values:
  • UART_AUTOBAUD_REQUEST Auto-Baud Rate Request
  • UART_SENDBREAK_REQUEST Send Break Request
  • UART_MUTE_MODE_REQUEST Mute Mode Request
  • UART_RXDATA_FLUSH_REQUEST Receive Data flush Request
  • UART_TXDATA_FLUSH_REQUEST Transmit data flush Request
Return values:
None

Definition at line 1049 of file stm32wbxx_hal_uart.h.

Referenced by HAL_LIN_SendBreak(), HAL_MultiProcessor_EnterMuteMode(), HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), UART_DMATxAbortCallback(), UART_DMATxOnlyAbortCallback(), UART_RxISR_16BIT(), UART_RxISR_16BIT_FIFOEN(), UART_RxISR_8BIT(), and UART_RxISR_8BIT_FIFOEN().

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: UART Private Macros

Defines
UART Private Macros
UART

Defines

#define | UART_GET_DIV_FACTOR(__CLOCKPRESCALER__)
Get UART clok division factor from clock prescaler value.
#define | UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__)
BRR division operation to set BRR register with LPUART.
#define | UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)
BRR division operation to set BRR register in 8-bit oversampling mode.
#define | UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__)
BRR division operation to set BRR register in 16-bit oversampling mode.
#define | UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance))
Check whether or not UART instance is Low Power UART.
#define | IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 8000001U)
Check UART Baud rate.
#define | IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
Check UART assertion time.
#define | IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
Check UART deassertion time.
#define | IS_UART_STOPBITS(__STOPBITS__)
Ensure that UART frame number of stop bits is valid.
#define | IS_LPUART_STOPBITS(__STOPBITS__)
Ensure that LPUART frame number of stop bits is valid.
#define | IS_UART_PARITY(__PARITY__)
Ensure that UART frame parity is valid.
#define | IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)
Ensure that UART hardware flow control is valid.
#define | IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
Ensure that UART communication mode is valid.
#define | IS_UART_STATE(__STATE__)
Ensure that UART state is valid.
#define | IS_UART_OVERSAMPLING(__SAMPLING__)
Ensure that UART oversampling is valid.
#define | IS_UART_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that UART frame sampling is valid.
#define | IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__)
Ensure that UART auto Baud rate detection mode is valid.
#define | IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__)
Ensure that UART receiver timeout setting is valid.
#define | IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
Check the receiver timeout value.
#define | IS_UART_LIN(__LIN__)
Ensure that UART LIN state is valid.
#define | IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__)
Ensure that UART LIN break detection length is valid.
#define | IS_UART_DMA_TX(__DMATX__)
Ensure that UART DMA TX state is valid.
#define | IS_UART_DMA_RX(__DMARX__)
Ensure that UART DMA RX state is valid.
#define | IS_UART_HALF_DUPLEX(__HDSEL__)
Ensure that UART half-duplex state is valid.
#define | IS_UART_WAKEUPMETHOD(__WAKEUP__)
Ensure that UART wake-up method is valid.
#define | IS_UART_REQUEST_PARAMETER(__PARAM__)
Ensure that UART request parameter is valid.
#define | IS_UART_ADVFEATURE_INIT(__INIT__)
Ensure that UART advanced features initialization is valid.
#define | IS_UART_ADVFEATURE_TXINV(__TXINV__)
Ensure that UART frame TX inversion setting is valid.
#define | IS_UART_ADVFEATURE_RXINV(__RXINV__)
Ensure that UART frame RX inversion setting is valid.
#define | IS_UART_ADVFEATURE_DATAINV(__DATAINV__)
Ensure that UART frame data inversion setting is valid.
#define | IS_UART_ADVFEATURE_SWAP(__SWAP__)
Ensure that UART frame RX/TX pins swap setting is valid.
#define | IS_UART_OVERRUN(__OVERRUN__)
Ensure that UART frame overrun setting is valid.
#define | IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__)
Ensure that UART auto Baud rate state is valid.
#define | IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__)
Ensure that UART DMA enabling or disabling on error setting is valid.
#define | IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__)
Ensure that UART frame MSB first setting is valid.
#define | IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__)
Ensure that UART stop mode state is valid.
#define | IS_UART_MUTE_MODE(__MUTE__)
Ensure that UART mute mode state is valid.
#define | IS_UART_WAKEUP_SELECTION(__WAKE__)
Ensure that UART wake-up selection is valid.
#define | IS_UART_DE_POLARITY(__POLARITY__)
Ensure that UART driver enable polarity is valid.
#define | IS_UART_PRESCALER(__CLOCKPRESCALER__)
Ensure that UART Prescaler is valid.

Define Documentation

#define IS_LPUART_STOPBITS ( __STOPBITS__ )
Value:
(((__STOPBITS__) == UART_STOPBITS_1) || \
                                          ((__STOPBITS__) == UART_STOPBITS_2))

Ensure that LPUART frame number of stop bits is valid.

Parameters:
__STOPBITS__ LPUART frame number of stop bits.
Return values:
SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)

Definition at line 1245 of file stm32wbxx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_ADVFEATURE_AUTOBAUDRATE ( __AUTOBAUDRATE__ )
Value:
(((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
                                                            ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))

Ensure that UART auto Baud rate state is valid.

Parameters:
__AUTOBAUDRATE__ UART auto Baud rate state.
Return values:
SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)

Definition at line 1444 of file stm32wbxx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE ( __MODE__ )
Value:
(((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT)    || \
                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME)   || \
                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))

Ensure that UART auto Baud rate detection mode is valid.

Parameters:
__MODE__ UART auto Baud rate detection mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 1305 of file stm32wbxx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_DATAINV ( __DATAINV__ )
Value:
(((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \
                                                 ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))

Ensure that UART frame data inversion setting is valid.

Parameters:
__DATAINV__ UART frame data inversion setting.
Return values:
SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)

Definition at line 1420 of file stm32wbxx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_DMAONRXERROR ( __DMA__ )
Value:
(((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
                                                   ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))

Ensure that UART DMA enabling or disabling on error setting is valid.

Parameters:
__DMA__ UART DMA enabling or disabling on error setting.
Return values:
SET (__DMA__ is valid) or RESET (__DMA__ is invalid)

Definition at line 1452 of file stm32wbxx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_INIT ( __INIT__ )
Value:
((__INIT__) <= (UART_ADVFEATURE_NO_INIT                | \
                                                            UART_ADVFEATURE_TXINVERT_INIT          | \
                                                            UART_ADVFEATURE_RXINVERT_INIT          | \
                                                            UART_ADVFEATURE_DATAINVERT_INIT        | \
                                                            UART_ADVFEATURE_SWAP_INIT              | \
                                                            UART_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
                                                            UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
                                                            UART_ADVFEATURE_AUTOBAUDRATE_INIT      | \
                                                            UART_ADVFEATURE_MSBFIRST_INIT))

Ensure that UART advanced features initialization is valid.

Parameters:
__INIT__ UART advanced features initialization.
Return values:
SET (__INIT__ is valid) or RESET (__INIT__ is invalid)

Definition at line 1389 of file stm32wbxx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_MSBFIRST ( __MSBFIRST__ )
Value:
(((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
                                                   ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))

Ensure that UART frame MSB first setting is valid.

Parameters:
__MSBFIRST__ UART frame MSB first setting.
Return values:
SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)

Definition at line 1460 of file stm32wbxx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_RXINV ( __RXINV__ )
Value:
(((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \
                                             ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))

Ensure that UART frame RX inversion setting is valid.

Parameters:
__RXINV__ UART frame RX inversion setting.
Return values:
SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)

Definition at line 1412 of file stm32wbxx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_STOPMODE ( __STOPMODE__ )
Value:
(((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
                                                   ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))

Ensure that UART stop mode state is valid.

Parameters:
__STOPMODE__ UART stop mode state.
Return values:
SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)

Definition at line 1468 of file stm32wbxx_hal_uart.h.

#define IS_UART_ADVFEATURE_SWAP ( __SWAP__ )
Value:
(((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \
                                           ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))

Ensure that UART frame RX/TX pins swap setting is valid.

Parameters:
__SWAP__ UART frame RX/TX pins swap setting.
Return values:
SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)

Definition at line 1428 of file stm32wbxx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ADVFEATURE_TXINV ( __TXINV__ )
Value:
(((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \
                                             ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))

Ensure that UART frame TX inversion setting is valid.

Parameters:
__TXINV__ UART frame TX inversion setting.
Return values:
SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)

Definition at line 1404 of file stm32wbxx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_ASSERTIONTIME ( __TIME__ ) ((__TIME__) <= 0x1FU)

Check UART assertion time.

Parameters:
__TIME__ 5-bit value assertion time.
Return values:
Test result (TRUE or FALSE).

Definition at line 1221 of file stm32wbxx_hal_uart.h.

Referenced by HAL_RS485Ex_Init().

#define IS_UART_BAUDRATE ( __BAUDRATE__ ) ((__BAUDRATE__) < 8000001U)

Check UART Baud rate.

Parameters:
__BAUDRATE__ Baudrate specified by the user. The maximum Baud Rate is derived from the maximum clock on WB (i.e. 64 MHz) divided by the smallest oversampling used on the USART (i.e. 8)
Return values:
SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)

Definition at line 1215 of file stm32wbxx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_DE_POLARITY ( __POLARITY__ )
Value:
(((__POLARITY__) == UART_DE_POLARITY_HIGH) || \
                                              ((__POLARITY__) == UART_DE_POLARITY_LOW))

Ensure that UART driver enable polarity is valid.

Parameters:
__POLARITY__ UART driver enable polarity.
Return values:
SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)

Definition at line 1493 of file stm32wbxx_hal_uart.h.

Referenced by HAL_RS485Ex_Init().

#define IS_UART_DEASSERTIONTIME ( __TIME__ ) ((__TIME__) <= 0x1FU)

Check UART deassertion time.

Parameters:
__TIME__ 5-bit value deassertion time.
Return values:
Test result (TRUE or FALSE).

Definition at line 1227 of file stm32wbxx_hal_uart.h.

Referenced by HAL_RS485Ex_Init().

#define IS_UART_DMA_RX ( __DMARX__ )
Value:
(((__DMARX__) == UART_DMA_RX_DISABLE) || \
                                       ((__DMARX__) == UART_DMA_RX_ENABLE))

Ensure that UART DMA RX state is valid.

Parameters:
__DMARX__ UART DMA RX state.
Return values:
SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)

Definition at line 1354 of file stm32wbxx_hal_uart.h.

#define IS_UART_DMA_TX ( __DMATX__ )
Value:
(((__DMATX__) == UART_DMA_TX_DISABLE) || \
                                       ((__DMATX__) == UART_DMA_TX_ENABLE))

Ensure that UART DMA TX state is valid.

Parameters:
__DMATX__ UART DMA TX state.
Return values:
SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)

Definition at line 1346 of file stm32wbxx_hal_uart.h.

#define IS_UART_HALF_DUPLEX ( __HDSEL__ )
Value:
(((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \
                                            ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))

Ensure that UART half-duplex state is valid.

Parameters:
__HDSEL__ UART half-duplex state.
Return values:
SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)

Definition at line 1362 of file stm32wbxx_hal_uart.h.

#define IS_UART_HARDWARE_FLOW_CONTROL ( __CONTROL__ )
Value:
(((__CONTROL__) == UART_HWCONTROL_NONE) || \
   ((__CONTROL__) == UART_HWCONTROL_RTS)  || \
   ((__CONTROL__) == UART_HWCONTROL_CTS)  || \
   ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))

Ensure that UART hardware flow control is valid.

Parameters:
__CONTROL__ UART hardware flow control.
Return values:
SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)

Definition at line 1263 of file stm32wbxx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_LIN ( __LIN__ )
Value:
(((__LIN__) == UART_LIN_DISABLE) || \
                                     ((__LIN__) == UART_LIN_ENABLE))

Ensure that UART LIN state is valid.

Parameters:
__LIN__ UART LIN state.
Return values:
SET (__LIN__ is valid) or RESET (__LIN__ is invalid)

Definition at line 1330 of file stm32wbxx_hal_uart.h.

#define IS_UART_LIN_BREAK_DETECT_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
                                                     ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))

Ensure that UART LIN break detection length is valid.

Parameters:
__LENGTH__ UART LIN break detection length.
Return values:
SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

Definition at line 1338 of file stm32wbxx_hal_uart.h.

Referenced by HAL_LIN_Init().

#define IS_UART_MODE ( __MODE__ ) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))

Ensure that UART communication mode is valid.

Parameters:
__MODE__ UART communication mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 1274 of file stm32wbxx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_MUTE_MODE ( __MUTE__ )
Value:
(((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
                                           ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))

Ensure that UART mute mode state is valid.

Parameters:
__MUTE__ UART mute mode state.
Return values:
SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)

Definition at line 1476 of file stm32wbxx_hal_uart.h.

#define IS_UART_ONE_BIT_SAMPLE ( __ONEBIT__ )
Value:
(((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \
                                            ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))

Ensure that UART frame sampling is valid.

Parameters:
__ONEBIT__ UART frame sampling.
Return values:
SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)

Definition at line 1297 of file stm32wbxx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_OVERRUN ( __OVERRUN__ )
Value:
(((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
                                          ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))

Ensure that UART frame overrun setting is valid.

Parameters:
__OVERRUN__ UART frame overrun setting.
Return values:
SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)

Definition at line 1436 of file stm32wbxx_hal_uart.h.

Referenced by UART_AdvFeatureConfig().

#define IS_UART_OVERSAMPLING ( __SAMPLING__ )
Value:
(((__SAMPLING__) == UART_OVERSAMPLING_16) || \
                                            ((__SAMPLING__) == UART_OVERSAMPLING_8))

Ensure that UART oversampling is valid.

Parameters:
__SAMPLING__ UART oversampling.
Return values:
SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)

Definition at line 1289 of file stm32wbxx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_PARITY ( __PARITY__ )
Value:
(((__PARITY__) == UART_PARITY_NONE) || \
                                    ((__PARITY__) == UART_PARITY_EVEN) || \
                                    ((__PARITY__) == UART_PARITY_ODD))

Ensure that UART frame parity is valid.

Parameters:
__PARITY__ UART frame parity.
Return values:
SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)

Definition at line 1254 of file stm32wbxx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_PRESCALER ( __CLOCKPRESCALER__ )
Value:
(((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1)   || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2)   || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4)   || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6)   || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8)   || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10)  || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12)  || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16)  || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32)  || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64)  || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) || \
                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256))

Ensure that UART Prescaler is valid.

Parameters:
__CLOCKPRESCALER__ UART Prescaler value.
Return values:
SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)

Definition at line 1501 of file stm32wbxx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_RECEIVER_TIMEOUT ( __TIMEOUT__ )
Value:
(((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
                                                ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))

Ensure that UART receiver timeout setting is valid.

Parameters:
__TIMEOUT__ UART receiver timeout setting.
Return values:
SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)

Definition at line 1315 of file stm32wbxx_hal_uart.h.

#define IS_UART_RECEIVER_TIMEOUT_VALUE ( __TIMEOUTVALUE__ ) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)

Check the receiver timeout value.

Note:
The maximum UART receiver timeout value is 0xFFFFFF.
Parameters:
__TIMEOUTVALUE__ receiver timeout value.
Return values:
Test result (TRUE or FALSE)

Definition at line 1323 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UART_ReceiverTimeout_Config().

#define IS_UART_REQUEST_PARAMETER ( __PARAM__ )
Value:
(((__PARAM__) == UART_AUTOBAUD_REQUEST)     || \
                                              ((__PARAM__) == UART_SENDBREAK_REQUEST)    || \
                                              ((__PARAM__) == UART_MUTE_MODE_REQUEST)    || \
                                              ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \
                                              ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))

Ensure that UART request parameter is valid.

Parameters:
__PARAM__ UART request parameter.
Return values:
SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)

Definition at line 1378 of file stm32wbxx_hal_uart.h.

#define IS_UART_STATE ( __STATE__ )
Value:
(((__STATE__) == UART_STATE_DISABLE) || \
                                  ((__STATE__) == UART_STATE_ENABLE))

Ensure that UART state is valid.

Parameters:
__STATE__ UART state.
Return values:
SET (__STATE__ is valid) or RESET (__STATE__ is invalid)

Definition at line 1281 of file stm32wbxx_hal_uart.h.

#define IS_UART_STOPBITS ( __STOPBITS__ )
Value:
(((__STOPBITS__) == UART_STOPBITS_0_5) || \
                                        ((__STOPBITS__) == UART_STOPBITS_1)   || \
                                        ((__STOPBITS__) == UART_STOPBITS_1_5) || \
                                        ((__STOPBITS__) == UART_STOPBITS_2))

Ensure that UART frame number of stop bits is valid.

Parameters:
__STOPBITS__ UART frame number of stop bits.
Return values:
SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)

Definition at line 1234 of file stm32wbxx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_WAKEUP_SELECTION ( __WAKE__ )
Value:
(((__WAKE__) == UART_WAKEUP_ON_ADDRESS)           || \
                                            ((__WAKE__) == UART_WAKEUP_ON_STARTBIT)          || \
                                            ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))

Ensure that UART wake-up selection is valid.

Parameters:
__WAKE__ UART wake-up selection.
Return values:
SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)

Definition at line 1484 of file stm32wbxx_hal_uart.h.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig().

#define IS_UART_WAKEUPMETHOD ( __WAKEUP__ )
Value:
(((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \
                                          ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))

Ensure that UART wake-up method is valid.

Parameters:
__WAKEUP__ UART wake-up method .
Return values:
SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)

Definition at line 1370 of file stm32wbxx_hal_uart.h.

Referenced by HAL_MultiProcessor_Init().

#define UART_DIV_LPUART | ( | __PCLK__,
 |  | __BAUD__,
 |  | __CLOCKPRESCALER__
 | ) |
Value:
((uint32_t)(((((uint64_t)(__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*256U)\
                                                                      + (uint32_t)((__BAUD__)/2U)) / (__BAUD__)))

BRR division operation to set BRR register with LPUART.

Parameters:
__PCLK__ | LPUART clock.
__BAUD__ | Baud rate set by the user.
__CLOCKPRESCALER__ | UART prescaler value.
Return values:
Division result

Definition at line 1179 of file stm32wbxx_hal_uart.h.

Referenced by UART_SetConfig().

#define UART_DIV_SAMPLING16 | ( | __PCLK__,
 |  | __BAUD__,
 |  | __CLOCKPRESCALER__
 | ) |
Value:
((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))\
                                                                       + ((__BAUD__)/2U)) / (__BAUD__))

BRR division operation to set BRR register in 16-bit oversampling mode.

Parameters:
__PCLK__ | UART clock.
__BAUD__ | Baud rate set by the user.
__CLOCKPRESCALER__ | UART prescaler value.
Return values:
Division result

Definition at line 1198 of file stm32wbxx_hal_uart.h.

Referenced by UART_SetConfig().

#define UART_DIV_SAMPLING8 | ( | __PCLK__,
 |  | __BAUD__,
 |  | __CLOCKPRESCALER__
 | ) |
Value:
(((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*2U)\
                                                                       + ((__BAUD__)/2U)) / (__BAUD__))

BRR division operation to set BRR register in 8-bit oversampling mode.

Parameters:
__PCLK__ | UART clock.
__BAUD__ | Baud rate set by the user.
__CLOCKPRESCALER__ | UART prescaler value.
Return values:
Division result

Definition at line 1189 of file stm32wbxx_hal_uart.h.

Referenced by UART_SetConfig().

#define UART_GET_DIV_FACTOR ( __CLOCKPRESCALER__ )
Value:
(((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1)   ? 1U :       \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2)   ? 2U :       \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4)   ? 4U :       \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6)   ? 6U :       \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8)   ? 8U :       \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10)  ? 10U :      \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12)  ? 12U :      \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16)  ? 16U :      \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32)  ? 32U :      \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64)  ? 64U :      \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U :     \
   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U)

Get UART clok division factor from clock prescaler value.

Parameters:
__CLOCKPRESCALER__ UART prescaler value.
Return values:
UART clock division factor

Definition at line 1158 of file stm32wbxx_hal_uart.h.

Referenced by UART_SetConfig().

#define UART_INSTANCE_LOWPOWER ( __HANDLE__ ) (IS_LPUART_INSTANCE((__HANDLE__)->Instance))

Check whether or not UART instance is Low Power UART.

Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
SET (instance is LPUART) or RESET (instance isn't LPUART)

Definition at line 1206 of file stm32wbxx_hal_uart.h.

Referenced by UART_SetConfig().

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: UARTEx Private Constants

Defines
UARTEx Private Constants
UARTEx

Defines

#define | RX_FIFO_DEPTH 8U
#define | TX_FIFO_DEPTH 8U

Define Documentation

#define RX_FIFO_DEPTH 8U

Definition at line 63 of file stm32wbxx_hal_uart_ex.c.

Referenced by UARTEx_SetNbDataToProcess().

#define TX_FIFO_DEPTH 8U

Definition at line 66 of file stm32wbxx_hal_uart_ex.c.

Referenced by UARTEx_SetNbDataToProcess().

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: UARTEx Private Functions

Functions
UARTEx Private Functions
UARTEx

Functions

static void | UARTEx_Wakeup_AddressConfig (UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
Initialize the UART wake-up from stop mode parameters when triggered by address detection.
static void | UARTEx_SetNbDataToProcess (UART_HandleTypeDef *huart)
Calculate the number of data to process in RX/TX ISR.

Function Documentation

static void UARTEx_SetNbDataToProcess ( UART_HandleTypeDef * huart ) [static]

Calculate the number of data to process in RX/TX ISR.

Note:
The RX FIFO depth and the TX FIFO depth is extracted from the UART configuration registers.
Parameters:
huart UART handle.
Return values:
None

Definition at line 691 of file stm32wbxx_hal_uart_ex.c.

References __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::Instance, __UART_HandleTypeDef::NbRxDataToProcess, __UART_HandleTypeDef::NbTxDataToProcess, RX_FIFO_DEPTH, TX_FIFO_DEPTH, and UART_FIFOMODE_DISABLE.

Referenced by HAL_UARTEx_EnableFifoMode(), HAL_UARTEx_SetRxFifoThreshold(), and HAL_UARTEx_SetTxFifoThreshold().

static void UARTEx_Wakeup_AddressConfig | ( | UART_HandleTypeDef * | huart,
 |  | UART_WakeUpTypeDef | WakeUpSelection
 | ) |  | [static]

Initialize the UART wake-up from stop mode parameters when triggered by address detection.

Parameters:
huart | UART handle.
WakeUpSelection | UART wake up from stop mode parameters.
Return values:
None

Definition at line 673 of file stm32wbxx_hal_uart_ex.c.

References UART_WakeUpTypeDef::Address, UART_WakeUpTypeDef::AddressLength, assert_param, __UART_HandleTypeDef::Instance, IS_UART_ADDRESSLENGTH_DETECT, and UART_CR2_ADDRESS_LSB_POS.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig().

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
UARTEx Exported Functions

Extended Initialization and Configuration Functions. More...

Functions

HAL_StatusTypeDef HAL_RS485Ex_Init (UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
Initialize the RS485 Driver enable feature according to the specified parameters in the UART_InitTypeDef and creates the associated handle.

Detailed Description

Extended Initialization and Configuration Functions.

===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
    in asynchronous mode.
      (+) For the asynchronous mode the parameters below can be configured:
        (++) Baud Rate
        (++) Word Length
        (++) Stop Bit
        (++) Parity: If the parity is enabled, then the MSB bit of the data written
             in the data register is transmitted but is changed by the parity bit.
        (++) Hardware flow control
        (++) Receiver/transmitter modes
        (++) Over Sampling Method
        (++) One-Bit Sampling Method
      (+) For the asynchronous mode, the following advanced features can be configured as well:
        (++) TX and/or RX pin level inversion
        (++) data logical level inversion
        (++) RX and TX pins swap
        (++) RX overrun detection disabling
        (++) DMA disabling on RX error
        (++) MSB first on communication line
        (++) auto Baud rate detection
    [..]
    The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration
     procedures (details for the procedures are available in reference manual).

Depending on the frame length defined by the M1 and M0 bits (7-bit, 8-bit or 9-bit), the possible UART formats are listed in the following table.

Table 1. UART frame format. +-----------------------------------------------------------------------+ | M1 bit | M0 bit | PCE bit | UART frame | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 0 | | SB | 8 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 0 | | SB | 9 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 0 | | SB | 7 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | +-----------------------------------------------------------------------+

Function Documentation

HAL_StatusTypeDef HAL_RS485Ex_Init | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | Polarity,
 |  | uint32_t | AssertionTime,
 |  | uint32_t | DeassertionTime
 | ) |  |

Initialize the RS485 Driver enable feature according to the specified parameters in the UART_InitTypeDef and creates the associated handle.

Parameters:
huart | UART handle.
Polarity Select the driver enable polarity. This parameter can be one of the following values:
  • UART_DE_POLARITY_HIGH DE signal is active high
  • UART_DE_POLARITY_LOW DE signal is active low
AssertionTime | Driver Enable assertion time: 5-bit value defining the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate)
DeassertionTime | Driver Enable deassertion time: 5-bit value defining the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate).
Return values:
HAL status

Definition at line 166 of file stm32wbxx_hal_uart_ex.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, __UART_HandleTypeDef::AdvancedInit, UART_AdvFeatureInitTypeDef::AdvFeatureInit, assert_param, __UART_HandleTypeDef::gState, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, __UART_HandleTypeDef::Instance, IS_UART_ASSERTIONTIME, IS_UART_DE_POLARITY, IS_UART_DEASSERTIONTIME, __UART_HandleTypeDef::Lock, __UART_HandleTypeDef::MspInitCallback, UART_ADVFEATURE_NO_INIT, UART_AdvFeatureConfig(), UART_CheckIdleState(), UART_CR1_DEAT_ADDRESS_LSB_POS, UART_CR1_DEDT_ADDRESS_LSB_POS, UART_InitCallbacksToDefault(), and UART_SetConfig().

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IO operation functions

Functions
IO operation functions
UARTEx Exported Functions

Extended functions. More...

Functions

__weak void | HAL_UARTEx_WakeupCallback (UART_HandleTypeDef *huart)
UART wakeup from Stop mode callback.
__weak void | HAL_UARTEx_RxFifoFullCallback (UART_HandleTypeDef *huart)
UART RX Fifo full callback.
__weak void | HAL_UARTEx_TxFifoEmptyCallback (UART_HandleTypeDef *huart)
UART TX Fifo empty callback.

Detailed Description

Extended functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    This subsection provides a set of Wakeup and FIFO mode related callback functions.

    (#) Wakeup from Stop mode Callback:
        (+) HAL_UARTEx_WakeupCallback()

    (#) TX/RX Fifos Callbacks:
        (+) HAL_UARTEx_RxFifoFullCallback()
        (+) HAL_UARTEx_TxFifoEmptyCallback()

Function Documentation

void HAL_UARTEx_RxFifoFullCallback ( UART_HandleTypeDef * huart )

UART RX Fifo full callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 287 of file stm32wbxx_hal_uart_ex.c.

Referenced by HAL_UART_IRQHandler(), HAL_UART_UnRegisterCallback(), and UART_InitCallbacksToDefault().

void HAL_UARTEx_TxFifoEmptyCallback ( UART_HandleTypeDef * huart )

UART TX Fifo empty callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 302 of file stm32wbxx_hal_uart_ex.c.

Referenced by HAL_UART_IRQHandler(), HAL_UART_UnRegisterCallback(), and UART_InitCallbacksToDefault().

void HAL_UARTEx_WakeupCallback ( UART_HandleTypeDef * huart )

UART wakeup from Stop mode callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 272 of file stm32wbxx_hal_uart_ex.c.

Referenced by HAL_UART_IRQHandler(), HAL_UART_UnRegisterCallback(), and UART_InitCallbacksToDefault().

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
UARTEx Exported Functions

Extended Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_MultiProcessorEx_AddressLength_Set (UART_HandleTypeDef *huart, uint32_t AddressLength)
By default in multiprocessor mode, when the wake up method is set to address mark, the UART handles only 4-bit long addresses detection; this API allows to enable longer addresses detection (6-, 7- or 8-bit long).
HAL_StatusTypeDef | HAL_UARTEx_StopModeWakeUpSourceConfig (UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
Set Wakeup from Stop mode interrupt flag selection.
HAL_StatusTypeDef | HAL_UARTEx_EnableStopMode (UART_HandleTypeDef *huart)
Enable UART Stop Mode.
HAL_StatusTypeDef | HAL_UARTEx_DisableStopMode (UART_HandleTypeDef *huart)
Disable UART Stop Mode.
HAL_StatusTypeDef | HAL_UARTEx_EnableFifoMode (UART_HandleTypeDef *huart)
Enable the FIFO mode.
HAL_StatusTypeDef | HAL_UARTEx_DisableFifoMode (UART_HandleTypeDef *huart)
Disable the FIFO mode.
HAL_StatusTypeDef | HAL_UARTEx_SetTxFifoThreshold (UART_HandleTypeDef *huart, uint32_t Threshold)
Set the TXFIFO threshold.
HAL_StatusTypeDef | HAL_UARTEx_SetRxFifoThreshold (UART_HandleTypeDef *huart, uint32_t Threshold)
Set the RXFIFO threshold.

Detailed Description

Extended Peripheral Control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..] This section provides the following functions:
     (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
         detection length to more than 4 bits for multiprocessor address mark wake up.
     (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode
         trigger: address match, Start Bit detection or RXNE bit status.
     (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode
     (+) HAL_UARTEx_DisableStopMode() API disables the above functionality
     (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode
     (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode
     (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
     (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold

Function Documentation

HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | AddressLength
 | ) |  |

By default in multiprocessor mode, when the wake up method is set to address mark, the UART handles only 4-bit long addresses detection; this API allows to enable longer addresses detection (6-, 7- or 8-bit long).

Note:
Addresses detection lengths are: 6-bit address detection in 7-bit data mode, 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
Parameters:
huart UART handle.
AddressLength This parameter can be one of the following values:
  • UART_ADDRESS_DETECT_4B 4-bit long address
  • UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
Return values:
HAL status

Definition at line 352 of file stm32wbxx_hal_uart_ex.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, assert_param, __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, __UART_HandleTypeDef::Instance, IS_UART_ADDRESSLENGTH_DETECT, and UART_CheckIdleState().

HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode ( UART_HandleTypeDef * huart )

Disable the FIFO mode.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 524 of file stm32wbxx_hal_uart_ex.c.

References __HAL_UART_DISABLE, assert_param, __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, and UART_FIFOMODE_DISABLE.

HAL_StatusTypeDef HAL_UARTEx_DisableStopMode ( UART_HandleTypeDef * huart )

Disable UART Stop Mode.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 464 of file stm32wbxx_hal_uart_ex.c.

References __UART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode ( UART_HandleTypeDef * huart )

Enable the FIFO mode.

Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 483 of file stm32wbxx_hal_uart_ex.c.

References __HAL_UART_DISABLE, assert_param, __UART_HandleTypeDef::FifoMode, __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, UART_FIFOMODE_ENABLE, and UARTEx_SetNbDataToProcess().

HAL_StatusTypeDef HAL_UARTEx_EnableStopMode ( UART_HandleTypeDef * huart )

Enable UART Stop Mode.

Note:
The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.
Parameters:
huart UART handle.
Return values:
HAL status

Definition at line 445 of file stm32wbxx_hal_uart_ex.c.

References __UART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | Threshold
 | ) |  |

Set the RXFIFO threshold.

Parameters:
huart UART handle.
Threshold RX FIFO threshold value This parameter can be one of the following values:
  • UART_RXFIFO_THRESHOLD_1_8
  • UART_RXFIFO_THRESHOLD_1_4
  • UART_RXFIFO_THRESHOLD_1_2
  • UART_RXFIFO_THRESHOLD_3_4
  • UART_RXFIFO_THRESHOLD_7_8
  • UART_RXFIFO_THRESHOLD_8_8
Return values:
HAL status

Definition at line 619 of file stm32wbxx_hal_uart_ex.c.

References __HAL_UART_DISABLE, assert_param, __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, IS_UART_RXFIFO_THRESHOLD, and UARTEx_SetNbDataToProcess().

HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | Threshold
 | ) |  |

Set the TXFIFO threshold.

Parameters:
huart UART handle.
Threshold TX FIFO threshold value This parameter can be one of the following values:
  • UART_TXFIFO_THRESHOLD_1_8
  • UART_TXFIFO_THRESHOLD_1_4
  • UART_TXFIFO_THRESHOLD_1_2
  • UART_TXFIFO_THRESHOLD_3_4
  • UART_TXFIFO_THRESHOLD_7_8
  • UART_TXFIFO_THRESHOLD_8_8
Return values:
HAL status

Definition at line 570 of file stm32wbxx_hal_uart_ex.c.

References __HAL_UART_DISABLE, assert_param, __UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, __UART_HandleTypeDef::Instance, IS_UART_TXFIFO_THRESHOLD, and UARTEx_SetNbDataToProcess().

HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig | ( | UART_HandleTypeDef * | huart,
 |  | UART_WakeUpTypeDef | WakeUpSelection
 | ) |  |

Set Wakeup from Stop mode interrupt flag selection.

Note:
It is the application responsibility to enable the interrupt used as usart_wkup interrupt source before entering low-power mode.
Parameters:
huart UART handle.
WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status. This parameter can be one of the following values:
  • UART_WAKEUP_ON_ADDRESS
  • UART_WAKEUP_ON_STARTBIT
  • UART_WAKEUP_ON_READDATA_NONEMPTY
Return values:
HAL status

Definition at line 390 of file stm32wbxx_hal_uart_ex.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, assert_param, __UART_HandleTypeDef::gState, HAL_GetTick(), HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, HAL_UART_TIMEOUT_VALUE, __UART_HandleTypeDef::Instance, IS_UART_WAKEUP_SELECTION, UART_WaitOnFlagUntilTimeout(), UART_WAKEUP_ON_ADDRESS, UARTEx_Wakeup_AddressConfig(), and UART_WakeUpTypeDef::WakeUpEvent.

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: UART_WakeUpTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
UART_WakeUpTypeDef Struct Reference
UARTEx Exported Types

UART wake up from stop mode parameters. More...

#include <stm32wbxx_hal_uart_ex.h>

Data Fields

uint32_t | WakeUpEvent
uint16_t | AddressLength
uint8_t | Address

Detailed Description

UART wake up from stop mode parameters.

Definition at line 47 of file stm32wbxx_hal_uart_ex.h.

Field Documentation

uint8_t UART_WakeUpTypeDef::Address

UART/USART node address (7-bit long max).

Definition at line 57 of file stm32wbxx_hal_uart_ex.h.

Referenced by UARTEx_Wakeup_AddressConfig().

uint16_t UART_WakeUpTypeDef::AddressLength

Specifies whether the address is 4 or 7-bit long. This parameter can be a value of UARTEx WakeUp Address Length.

Definition at line 54 of file stm32wbxx_hal_uart_ex.h.

Referenced by UARTEx_Wakeup_AddressConfig().

uint32_t UART_WakeUpTypeDef::WakeUpEvent

Specifies which event will activate the Wakeup from Stop mode flag (WUF). This parameter can be a value of UART WakeUp From Stop Selection. If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must be filled up.

Definition at line 49 of file stm32wbxx_hal_uart_ex.h.

Referenced by HAL_UARTEx_StopModeWakeUpSourceConfig().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_uart_ex.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: UARTEx Word Length

Defines
UARTEx Word Length
UARTEx Exported Constants

Defines

#define | UART_WORDLENGTH_7B USART_CR1_M1
#define | UART_WORDLENGTH_8B 0x00000000U
#define | UART_WORDLENGTH_9B USART_CR1_M0

Define Documentation

#define UART_WORDLENGTH_7B USART_CR1_M1

7-bit long UART frame

Definition at line 72 of file stm32wbxx_hal_uart_ex.h.

#define UART_WORDLENGTH_8B 0x00000000U

8-bit long UART frame

Definition at line 73 of file stm32wbxx_hal_uart_ex.h.

Referenced by HAL_LIN_Init().

#define UART_WORDLENGTH_9B USART_CR1_M0

9-bit long UART frame

Definition at line 74 of file stm32wbxx_hal_uart_ex.h.

Referenced by HAL_UART_Receive(), HAL_UART_Receive_IT(), HAL_UART_Transmit(), and HAL_UART_Transmit_IT().

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: UARTEx WakeUp Address Length

Defines
UARTEx WakeUp Address Length
UARTEx Exported Constants

Defines

#define | UART_ADDRESS_DETECT_4B 0x00000000U
#define | UART_ADDRESS_DETECT_7B USART_CR2_ADDM7

Define Documentation

#define UART_ADDRESS_DETECT_4B 0x00000000U

4-bit long wake-up address

Definition at line 82 of file stm32wbxx_hal_uart_ex.h.

#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7

7-bit long wake-up address

Definition at line 83 of file stm32wbxx_hal_uart_ex.h.

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: UARTEx FIFO mode

Defines
UARTEx FIFO mode
UARTEx Exported Constants

UART FIFO mode. More...

Defines

#define | UART_FIFOMODE_DISABLE 0x00000000U
#define | UART_FIFOMODE_ENABLE USART_CR1_FIFOEN

Detailed Description

UART FIFO mode.

Define Documentation

#define UART_FIFOMODE_DISABLE 0x00000000U

FIFO mode disable

Definition at line 92 of file stm32wbxx_hal_uart_ex.h.

Referenced by HAL_UARTEx_DisableFifoMode(), and UARTEx_SetNbDataToProcess().

#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN

FIFO mode enable

Definition at line 93 of file stm32wbxx_hal_uart_ex.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_Receive_IT(), HAL_UART_Transmit_IT(), HAL_UARTEx_EnableFifoMode(), UART_DMATxAbortCallback(), and UART_DMATxOnlyAbortCallback().

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: UARTEx TXFIFO threshold level

Defines
UARTEx TXFIFO threshold level
UARTEx Exported Constants

UART TXFIFO threshold level. More...

Defines

#define | UART_TXFIFO_THRESHOLD_1_8 0x00000000U
#define | UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0
#define | UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1
#define | UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)
#define | UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2
#define | UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)

Detailed Description

UART TXFIFO threshold level.

Define Documentation

#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1

TXFIFO reaches 1/2 of its depth

Definition at line 104 of file stm32wbxx_hal_uart_ex.h.

#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0

TXFIFO reaches 1/4 of its depth

Definition at line 103 of file stm32wbxx_hal_uart_ex.h.

#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U

TXFIFO reaches 1/8 of its depth

Definition at line 102 of file stm32wbxx_hal_uart_ex.h.

#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)

TXFIFO reaches 3/4 of its depth

Definition at line 105 of file stm32wbxx_hal_uart_ex.h.

#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2

TXFIFO reaches 7/8 of its depth

Definition at line 106 of file stm32wbxx_hal_uart_ex.h.

#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)

TXFIFO becomes empty

Definition at line 107 of file stm32wbxx_hal_uart_ex.h.

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: UARTEx RXFIFO threshold level

Defines
UARTEx RXFIFO threshold level
UARTEx Exported Constants

UART RXFIFO threshold level. More...

Defines

#define | UART_RXFIFO_THRESHOLD_1_8 0x00000000U
#define | UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0
#define | UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1
#define | UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)
#define | UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2
#define | UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)

Detailed Description

UART RXFIFO threshold level.

Define Documentation

#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1

RXFIFO FIFO reaches 1/2 of its depth

Definition at line 118 of file stm32wbxx_hal_uart_ex.h.

#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0

RXFIFO FIFO reaches 1/4 of its depth

Definition at line 117 of file stm32wbxx_hal_uart_ex.h.

#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U

RXFIFO FIFO reaches 1/8 of its depth

Definition at line 116 of file stm32wbxx_hal_uart_ex.h.

#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)

RXFIFO FIFO reaches 3/4 of its depth

Definition at line 119 of file stm32wbxx_hal_uart_ex.h.

#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2

RXFIFO FIFO reaches 7/8 of its depth

Definition at line 120 of file stm32wbxx_hal_uart_ex.h.

#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)

RXFIFO FIFO becomes full

Definition at line 121 of file stm32wbxx_hal_uart_ex.h.

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STM32WB55xx HAL User Manual: UARTEx Private Macros

Defines
UARTEx Private Macros
UARTEx

Defines

#define | UART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the UART clock source.
#define | UART_MASK_COMPUTATION(__HANDLE__)
Report the UART mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_UART_WORD_LENGTH(__LENGTH__)
Ensure that UART frame length is valid.
#define | IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__)
Ensure that UART wake-up address length is valid.
#define | IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that UART TXFIFO threshold level is valid.
#define | IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that UART RXFIFO threshold level is valid.

Define Documentation

#define IS_UART_ADDRESSLENGTH_DETECT ( __ADDRESS__ )
Value:
(((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
                                                   ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))

Ensure that UART wake-up address length is valid.

Parameters:
__ADDRESS__ UART wake-up address length.
Return values:
SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)

Definition at line 340 of file stm32wbxx_hal_uart_ex.h.

Referenced by HAL_MultiProcessorEx_AddressLength_Set(), and UARTEx_Wakeup_AddressConfig().

#define IS_UART_RXFIFO_THRESHOLD ( __THRESHOLD__ )
Value:
(((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \
                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \
                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \
                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \
                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \
                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8))

Ensure that UART RXFIFO threshold level is valid.

Parameters:
__THRESHOLD__ UART RXFIFO threshold level.
Return values:
SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)

Definition at line 360 of file stm32wbxx_hal_uart_ex.h.

Referenced by HAL_UARTEx_SetRxFifoThreshold().

#define IS_UART_TXFIFO_THRESHOLD ( __THRESHOLD__ )
Value:
(((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \
                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \
                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \
                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \
                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \
                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8))

Ensure that UART TXFIFO threshold level is valid.

Parameters:
__THRESHOLD__ UART TXFIFO threshold level.
Return values:
SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)

Definition at line 348 of file stm32wbxx_hal_uart_ex.h.

Referenced by HAL_UARTEx_SetTxFifoThreshold().

#define IS_UART_WORD_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == UART_WORDLENGTH_7B) || \
                                         ((__LENGTH__) == UART_WORDLENGTH_8B) || \
                                         ((__LENGTH__) == UART_WORDLENGTH_9B))

Ensure that UART frame length is valid.

Parameters:
__LENGTH__ UART frame length.
Return values:
SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

Definition at line 331 of file stm32wbxx_hal_uart_ex.h.

Referenced by UART_SetConfig().

#define UART_GETCLOCKSOURCE | ( | __HANDLE__,
 |  | __CLOCKSOURCE__
 | ) |

Report the UART clock source.

Parameters:
__HANDLE__ | specifies the UART Handle.
__CLOCKSOURCE__ | output variable.
Return values:
UART clocking source, written in __CLOCKSOURCE__.

Definition at line 196 of file stm32wbxx_hal_uart_ex.h.

Referenced by UART_SetConfig().

#define UART_MASK_COMPUTATION ( __HANDLE__ )

Report the UART mask to apply to retrieve the received data according to the word length and to the parity bits activation.

Note:
If PCE = 1, the parity bit is not included in the data extracted by the reception API(). This masking operation is not carried out in the case of DMA transfers.
Parameters:
__HANDLE__ specifies the UART Handle.
Return values:
None,the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.

Definition at line 285 of file stm32wbxx_hal_uart_ex.h.

Referenced by HAL_UART_Receive(), and HAL_UART_Receive_IT().

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: USART Private Constants

Defines
USART Private Constants
USART

Defines

#define | USART_DUMMY_DATA ((uint16_t) 0xFFFF)
#define | USART_TEACK_REACK_TIMEOUT 1000U
#define | USART_CR1_FIELDS
#define | USART_CR2_FIELDS
#define | USART_CR3_FIELDS ((uint32_t)(USART_CR3_TXFTCFG | USART_CR3_RXFTCFG ))
#define | USART_BRR_MIN 0x10U /* USART BRR minimum authorized value */
#define | USART_BRR_MAX 0xFFFFU /* USART BRR maximum authorized value */

Define Documentation

#define USART_BRR_MAX 0xFFFFU /* USART BRR maximum authorized value */

Definition at line 170 of file stm32wbxx_hal_usart.c.

Referenced by USART_SetConfig().

#define USART_BRR_MIN 0x10U /* USART BRR minimum authorized value */

Definition at line 169 of file stm32wbxx_hal_usart.c.

Referenced by USART_SetConfig().

#define USART_CR1_FIELDS
Value:
((uint32_t)(USART_CR1_M |  USART_CR1_PCE | USART_CR1_PS    | \
                                              USART_CR1_TE | USART_CR1_RE  | USART_CR1_OVER8 | \
                                              USART_CR1_FIFOEN ))

USART CR1 fields of parameters set by USART_SetConfig API

Definition at line 159 of file stm32wbxx_hal_usart.c.

Referenced by USART_SetConfig().

#define USART_CR2_FIELDS
Value:
((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | \
                                              USART_CR2_LBCL | USART_CR2_STOP | USART_CR2_SLVEN | \
                                              USART_CR2_DIS_NSS))

USART CR2 fields of parameters set by USART_SetConfig API

Definition at line 163 of file stm32wbxx_hal_usart.c.

Referenced by USART_SetConfig().

#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_TXFTCFG | USART_CR3_RXFTCFG ))

USART or USART CR3 fields of parameters set by USART_SetConfig API

Definition at line 167 of file stm32wbxx_hal_usart.c.

#define USART_DUMMY_DATA ((uint16_t) 0xFFFF)

USART transmitted dummy data

Definition at line 157 of file stm32wbxx_hal_usart.c.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

#define USART_TEACK_REACK_TIMEOUT 1000U

USART TX or RX enable acknowledge time-out value

Definition at line 158 of file stm32wbxx_hal_usart.c.

Referenced by USART_CheckIdleState().

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
USART Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_USART_Init (USART_HandleTypeDef *husart)
Initialize the USART mode according to the specified parameters in the USART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_USART_DeInit (USART_HandleTypeDef *husart)
DeInitialize the USART peripheral.
__weak void | HAL_USART_MspInit (USART_HandleTypeDef *husart)
Initialize the USART MSP.
__weak void | HAL_USART_MspDeInit (USART_HandleTypeDef *husart)
DeInitialize the USART MSP.
HAL_StatusTypeDef | HAL_USART_RegisterCallback (USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback)
Register a User USART Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_USART_UnRegisterCallback (USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID)
Unregister an UART Callback UART callaback is redirected to the weak predefined callback.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to initialize the USART
    in asynchronous and in synchronous modes.
      (+) For the asynchronous mode only these parameters can be configured:
        (++) Baud Rate
        (++) Word Length
        (++) Stop Bit
        (++) Parity: If the parity is enabled, then the MSB bit of the data written
             in the data register is transmitted but is changed by the parity bit.
        (++) USART polarity
        (++) USART phase
        (++) USART LastBit
        (++) Receiver/transmitter modes

    [..]
    The HAL_USART_Init() function follows the USART  synchronous configuration
    procedure (details for the procedure are available in reference manual).

Depending on the frame length defined by the M1 and M0 bits (7-bit, 8-bit or 9-bit), the possible USART formats are listed in the following table.

Table 1. USART frame format. +-----------------------------------------------------------------------+ | M1 bit | M0 bit | PCE bit | USART frame | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 0 | | SB | 8 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 0 | | SB | 9 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 0 | | SB | 7 bit data | STB | | |---------|---------|-----------|---------------------------------------| | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | +-----------------------------------------------------------------------+

Function Documentation

HAL_StatusTypeDef HAL_USART_DeInit ( USART_HandleTypeDef * husart )

DeInitialize the USART peripheral.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 335 of file stm32wbxx_hal_usart.c.

References assert_param, __USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_NONE, HAL_USART_MspDeInit(), HAL_USART_STATE_BUSY, HAL_USART_STATE_RESET, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::MspDeInitCallback, and __USART_HandleTypeDef::State.

HAL_StatusTypeDef HAL_USART_Init ( USART_HandleTypeDef * husart )

Initialize the USART mode according to the specified parameters in the USART_InitTypeDef and initialize the associated handle.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 274 of file stm32wbxx_hal_usart.c.

References __HAL_USART_DISABLE, __HAL_USART_ENABLE, assert_param, HAL_USART_MspInit(), HAL_USART_STATE_BUSY, HAL_USART_STATE_RESET, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::Lock, __USART_HandleTypeDef::MspInitCallback, __USART_HandleTypeDef::State, USART_CheckIdleState(), USART_InitCallbacksToDefault(), and USART_SetConfig().

void HAL_USART_MspDeInit ( USART_HandleTypeDef * husart )

DeInitialize the USART MSP.

Parameters:
husart USART handle.
Return values:
None

Definition at line 393 of file stm32wbxx_hal_usart.c.

Referenced by HAL_USART_DeInit(), and HAL_USART_UnRegisterCallback().

void HAL_USART_MspInit ( USART_HandleTypeDef * husart )

Initialize the USART MSP.

Parameters:
husart USART handle.
Return values:
None

Definition at line 378 of file stm32wbxx_hal_usart.c.

Referenced by HAL_USART_Init(), and HAL_USART_UnRegisterCallback().

HAL_StatusTypeDef HAL_USART_RegisterCallback | ( | USART_HandleTypeDef * | husart,
 |  | HAL_USART_CallbackIDTypeDef | CallbackID,
 |  | pUSART_CallbackTypeDef | pCallback
 | ) |  |

Register a User USART Callback To be used instead of the weak predefined callback.

Parameters:
husart | usart handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
  • HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID
  • HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
  • HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_USART_ERROR_CB_ID Error Callback ID
  • HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
  • HAL_USART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
  • HAL_USART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
  • HAL_USART_MSPINIT_CB_ID MspInit Callback ID
  • HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID
pCallback | pointer to the Callback function
Return values:
HAL status +

Definition at line 424 of file stm32wbxx_hal_usart.c.

References __USART_HandleTypeDef::AbortCpltCallback, __USART_HandleTypeDef::ErrorCallback, __USART_HandleTypeDef::ErrorCode, HAL_USART_ABORT_COMPLETE_CB_ID, HAL_USART_ERROR_CB_ID, HAL_USART_ERROR_INVALID_CALLBACK, HAL_USART_MSPDEINIT_CB_ID, HAL_USART_MSPINIT_CB_ID, HAL_USART_RX_COMPLETE_CB_ID, HAL_USART_RX_FIFO_FULL_CB_ID, HAL_USART_RX_HALFCOMPLETE_CB_ID, HAL_USART_STATE_READY, HAL_USART_STATE_RESET, HAL_USART_TX_COMPLETE_CB_ID, HAL_USART_TX_FIFO_EMPTY_CB_ID, HAL_USART_TX_HALFCOMPLETE_CB_ID, HAL_USART_TX_RX_COMPLETE_CB_ID, __USART_HandleTypeDef::MspDeInitCallback, __USART_HandleTypeDef::MspInitCallback, __USART_HandleTypeDef::RxCpltCallback, __USART_HandleTypeDef::RxFifoFullCallback, __USART_HandleTypeDef::RxHalfCpltCallback, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxCpltCallback, __USART_HandleTypeDef::TxFifoEmptyCallback, __USART_HandleTypeDef::TxHalfCpltCallback, and __USART_HandleTypeDef::TxRxCpltCallback.

HAL_StatusTypeDef HAL_USART_UnRegisterCallback | ( | USART_HandleTypeDef * | husart,
 |  | HAL_USART_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister an UART Callback UART callaback is redirected to the weak predefined callback.

Parameters:
husart uart handle
CallbackID ID of the callback to be unregistered This parameter can be one of the following values:
  • HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
  • HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID
  • HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
  • HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID
  • HAL_USART_ERROR_CB_ID Error Callback ID
  • HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
  • HAL_USART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
  • HAL_USART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
  • HAL_USART_MSPINIT_CB_ID MspInit Callback ID
  • HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID
Return values:
HAL status

Definition at line 550 of file stm32wbxx_hal_usart.c.

References __USART_HandleTypeDef::AbortCpltCallback, __USART_HandleTypeDef::ErrorCallback, __USART_HandleTypeDef::ErrorCode, HAL_USART_ABORT_COMPLETE_CB_ID, HAL_USART_AbortCpltCallback(), HAL_USART_ERROR_CB_ID, HAL_USART_ERROR_INVALID_CALLBACK, HAL_USART_ErrorCallback(), HAL_USART_MspDeInit(), HAL_USART_MSPDEINIT_CB_ID, HAL_USART_MspInit(), HAL_USART_MSPINIT_CB_ID, HAL_USART_RX_COMPLETE_CB_ID, HAL_USART_RX_FIFO_FULL_CB_ID, HAL_USART_RX_HALFCOMPLETE_CB_ID, HAL_USART_RxCpltCallback(), HAL_USART_RxHalfCpltCallback(), HAL_USART_STATE_READY, HAL_USART_STATE_RESET, HAL_USART_TX_COMPLETE_CB_ID, HAL_USART_TX_FIFO_EMPTY_CB_ID, HAL_USART_TX_HALFCOMPLETE_CB_ID, HAL_USART_TX_RX_COMPLETE_CB_ID, HAL_USART_TxCpltCallback(), HAL_USART_TxHalfCpltCallback(), HAL_USART_TxRxCpltCallback(), HAL_USARTEx_RxFifoFullCallback(), HAL_USARTEx_TxFifoEmptyCallback(), __USART_HandleTypeDef::MspDeInitCallback, __USART_HandleTypeDef::MspInitCallback, __USART_HandleTypeDef::RxCpltCallback, __USART_HandleTypeDef::RxFifoFullCallback, __USART_HandleTypeDef::RxHalfCpltCallback, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxCpltCallback, __USART_HandleTypeDef::TxFifoEmptyCallback, __USART_HandleTypeDef::TxHalfCpltCallback, and __USART_HandleTypeDef::TxRxCpltCallback.

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IO operation functions

Functions
IO operation functions
USART Exported Functions

USART Transmit and Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_USART_Transmit (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
Simplex send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Full-Duplex Send and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Transmit_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Receive_IT (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Send and Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Transmit_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_Receive_DMA (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Transmit Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_DMAPause (USART_HandleTypeDef *husart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAResume (USART_HandleTypeDef *husart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAStop (USART_HandleTypeDef *husart)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_Abort (USART_HandleTypeDef *husart)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_USART_Abort_IT (USART_HandleTypeDef *husart)
Abort ongoing transfers (Interrupt mode).
void | HAL_USART_IRQHandler (USART_HandleTypeDef *husart)
Handle USART interrupt request.
__weak void | HAL_USART_TxCpltCallback (USART_HandleTypeDef *husart)
Tx Transfer completed callback.
__weak void | HAL_USART_TxHalfCpltCallback (USART_HandleTypeDef *husart)
Tx Half Transfer completed callback.
__weak void | HAL_USART_RxCpltCallback (USART_HandleTypeDef *husart)
Rx Transfer completed callback.
__weak void | HAL_USART_RxHalfCpltCallback (USART_HandleTypeDef *husart)
Rx Half Transfer completed callback.
__weak void | HAL_USART_TxRxCpltCallback (USART_HandleTypeDef *husart)
Tx/Rx Transfers completed callback for the non-blocking process.
__weak void | HAL_USART_ErrorCallback (USART_HandleTypeDef *husart)
USART error callback.
__weak void | HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
USART Abort Complete callback.

Detailed Description

USART Transmit and Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..] This subsection provides a set of functions allowing to manage the USART synchronous
    data transfers.

    [..] The USART supports master mode only: it cannot receive or send data related to an input
         clock (SCLK is always an output).

    [..]

    (#) There are two modes of transfer:
        (++) Blocking mode: The communication is performed in polling mode.
             The HAL status of all data processing is returned by the same function
             after finishing transfer.
        (++) No-Blocking mode: The communication is performed using Interrupts
             or DMA, These API's return the HAL status.
             The end of the data processing will be indicated through the
             dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
             using DMA mode.
             The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks
             will be executed respectively at the end of the transmit or Receive process
             The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected

    (#) Blocking mode API's are :
        (++) HAL_USART_Transmit() in simplex mode
        (++) HAL_USART_Receive() in full duplex receive only
        (++) HAL_USART_TransmitReceive() in full duplex mode

    (#) Non-Blocking mode API's with Interrupt are :
        (++) HAL_USART_Transmit_IT() in simplex mode
        (++) HAL_USART_Receive_IT() in full duplex receive only
        (++) HAL_USART_TransmitReceive_IT() in full duplex mode
        (++) HAL_USART_IRQHandler()

    (#) No-Blocking mode API's  with DMA are :
        (++) HAL_USART_Transmit_DMA() in simplex mode
        (++) HAL_USART_Receive_DMA() in full duplex receive only
        (++) HAL_USART_TransmitReceive_DMA() in full duplex mode
        (++) HAL_USART_DMAPause()
        (++) HAL_USART_DMAResume()
        (++) HAL_USART_DMAStop()

    (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
        (++) HAL_USART_TxCpltCallback()
        (++) HAL_USART_RxCpltCallback()
        (++) HAL_USART_TxHalfCpltCallback()
        (++) HAL_USART_RxHalfCpltCallback()
        (++) HAL_USART_ErrorCallback()
        (++) HAL_USART_TxRxCpltCallback()

    (#) Non-Blocking mode transfers could be aborted using Abort API's :
        (++) HAL_USART_Abort()
        (++) HAL_USART_Abort_IT()

    (#) For Abort services based on interrupts (HAL_USART_Abort_IT), a Abort Complete Callbacks is provided:
        (++) HAL_USART_AbortCpltCallback()

    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
        Errors are handled as follows :
        (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
             to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
             Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
             and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side.
             If user wants to abort it, Abort services should be called by user.
        (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
             This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
             Error code is set to allow user to identify error type, and HAL_USART_ErrorCallback() user callback is executed.

Function Documentation

HAL_StatusTypeDef HAL_USART_Abort ( USART_HandleTypeDef * husart )

Abort ongoing transfers (blocking mode).

Parameters:
husart USART handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable USART Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1866 of file stm32wbxx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, __HAL_USART_SEND_REQ, __USART_HandleTypeDef::ErrorCode, __USART_HandleTypeDef::FifoMode, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_USART_ERROR_DMA, HAL_USART_ERROR_NONE, HAL_USART_STATE_READY, __USART_HandleTypeDef::hdmarx, __USART_HandleTypeDef::hdmatx, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, USART_CLEAR_FEF, USART_CLEAR_NEF, USART_CLEAR_OREF, USART_CLEAR_PEF, USART_FIFOMODE_ENABLE, USART_RXDATA_FLUSH_REQUEST, USART_TXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_USART_Abort_IT ( USART_HandleTypeDef * husart )

Abort ongoing transfers (Interrupt mode).

Parameters:
husart USART handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable USART Interrupts (Tx and Rx)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1967 of file stm32wbxx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, __HAL_USART_SEND_REQ, __USART_HandleTypeDef::AbortCpltCallback, __USART_HandleTypeDef::ErrorCode, __USART_HandleTypeDef::FifoMode, HAL_DMA_Abort_IT(), HAL_USART_AbortCpltCallback(), HAL_USART_ERROR_NONE, HAL_USART_STATE_READY, __USART_HandleTypeDef::hdmarx, __USART_HandleTypeDef::hdmatx, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, USART_CLEAR_FEF, USART_CLEAR_NEF, USART_CLEAR_OREF, USART_CLEAR_PEF, USART_DMARxAbortCallback(), USART_DMATxAbortCallback(), USART_FIFOMODE_ENABLE, USART_RXDATA_FLUSH_REQUEST, USART_TXDATA_FLUSH_REQUEST, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_USART_AbortCpltCallback ( USART_HandleTypeDef * husart )

USART Abort Complete callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 2417 of file stm32wbxx_hal_usart.c.

Referenced by HAL_USART_Abort_IT(), HAL_USART_UnRegisterCallback(), USART_DMARxAbortCallback(), USART_DMATxAbortCallback(), and USART_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_USART_DMAPause ( USART_HandleTypeDef * husart )

Pause the DMA Transfer.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 1709 of file stm32wbxx_hal_usart.c.

References HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_BUSY_TX_RX, __USART_HandleTypeDef::Instance, and __USART_HandleTypeDef::State.

HAL_StatusTypeDef HAL_USART_DMAResume ( USART_HandleTypeDef * husart )

Resume the DMA Transfer.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 1756 of file stm32wbxx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_BUSY_TX_RX, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::State, and USART_CLEAR_OREF.

HAL_StatusTypeDef HAL_USART_DMAStop ( USART_HandleTypeDef * husart )

Stop the DMA Transfer.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 1800 of file stm32wbxx_hal_usart.c.

References __USART_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_DMA_ERROR_TIMEOUT, HAL_DMA_GetError(), HAL_USART_ERROR_DMA, HAL_USART_STATE_READY, __USART_HandleTypeDef::hdmarx, __USART_HandleTypeDef::hdmatx, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::State, and USART_EndTransfer().

void HAL_USART_ErrorCallback ( USART_HandleTypeDef * husart )

USART error callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 2402 of file stm32wbxx_hal_usart.c.

Referenced by HAL_USART_IRQHandler(), HAL_USART_UnRegisterCallback(), USART_DMAAbortOnError(), USART_DMAError(), and USART_InitCallbacksToDefault().

void HAL_USART_IRQHandler ( USART_HandleTypeDef * husart )

Handle USART interrupt request.

Parameters:
husart USART handle.
Return values:
None

Definition at line 2097 of file stm32wbxx_hal_usart.c.

References __HAL_USART_CLEAR_IT, __HAL_USART_CLEAR_UDRFLAG, __USART_HandleTypeDef::ErrorCallback, __USART_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_USART_ERROR_FE, HAL_USART_ERROR_NE, HAL_USART_ERROR_NONE, HAL_USART_ERROR_ORE, HAL_USART_ERROR_PE, HAL_USART_ERROR_UDR, HAL_USART_ErrorCallback(), HAL_USART_STATE_BUSY_RX, HAL_USARTEx_RxFifoFullCallback(), HAL_USARTEx_TxFifoEmptyCallback(), __USART_HandleTypeDef::hdmarx, __USART_HandleTypeDef::hdmatx, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::RxFifoFullCallback, __USART_HandleTypeDef::RxISR, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxFifoEmptyCallback, __USART_HandleTypeDef::TxISR, USART_CLEAR_FEF, USART_CLEAR_NEF, USART_CLEAR_OREF, USART_CLEAR_PEF, USART_DMAAbortOnError(), USART_EndTransfer(), USART_EndTransmit_IT(), and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_USART_Receive | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Note:
To receive synchronous data, dummy data are simultaneously transmitted.
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. In this case, Size must indicate the number of u16 available through pRxData.
Parameters:
husart | USART handle.
pRxData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be received.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 842 of file stm32wbxx_hal_usart.c.

References __HAL_USART_CLEAR_UDRFLAG, __HAL_USART_SEND_REQ, __USART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, __USART_HandleTypeDef::Init, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::Mask, USART_InitTypeDef::Parity, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::RxXferSize, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, USART_DUMMY_DATA, USART_FLAG_RXNE, USART_FLAG_TXE, USART_MASK_COMPUTATION, USART_PARITY_NONE, USART_SLAVEMODE_DISABLE, USART_SLAVEMODE_ENABLE, USART_TXDATA_FLUSH_REQUEST, USART_WaitOnFlagUntilTimeout(), USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_USART_Receive_DMA | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in DMA mode.

Note:
When the USART parity is enabled (PCE = 1), the received data contain the parity bit (MSB position).
The USART DMA transmit channel must be configured in order to generate the clock for the slave.
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. In this case, Size must indicate the number of u16 available through pRxData.
Parameters:
husart | USART handle.
pRxData | pointer to data buffer (u8 or u16 data elements).
Size | amount of data elements (u8 or u16) to be received.
Return values:
HAL status

Definition at line 1474 of file stm32wbxx_hal_usart.c.

References __USART_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_DMA_Start_IT(), HAL_USART_ERROR_DMA, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, __USART_HandleTypeDef::hdmarx, __USART_HandleTypeDef::hdmatx, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::pRxBuffPtr, __USART_HandleTypeDef::pTxBuffPtr, __USART_HandleTypeDef::RxXferSize, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferSize, USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxHalfCplt(), USART_SLAVEMODE_DISABLE, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_USART_Receive_IT | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in interrupt mode.

Note:
To receive synchronous data, dummy data are simultaneously transmitted.
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the received data is handled as a set of u16. In this case, Size must indicate the number of u16 available through pRxData.
Parameters:
husart | USART handle.
pRxData | pointer to data buffer (u8 or u16 data elements).
Size | amount of data elements (u8 or u16) to be received.
Return values:
HAL status

Definition at line 1186 of file stm32wbxx_hal_usart.c.

References __USART_HandleTypeDef::ErrorCode, __USART_HandleTypeDef::FifoMode, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, __USART_HandleTypeDef::Init, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::NbRxDataToProcess, USART_InitTypeDef::Parity, __USART_HandleTypeDef::pRxBuffPtr, __USART_HandleTypeDef::RxISR, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::RxXferSize, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, USART_DUMMY_DATA, USART_FIFOMODE_ENABLE, USART_MASK_COMPUTATION, USART_PARITY_NONE, USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), USART_RxISR_8BIT_FIFOEN(), USART_SLAVEMODE_DISABLE, USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

void HAL_USART_RxCpltCallback ( USART_HandleTypeDef * husart )

Rx Transfer completed callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 2357 of file stm32wbxx_hal_usart.c.

Referenced by HAL_USART_UnRegisterCallback(), USART_DMAReceiveCplt(), USART_InitCallbacksToDefault(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

void HAL_USART_RxHalfCpltCallback ( USART_HandleTypeDef * husart )

Rx Half Transfer completed callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 2372 of file stm32wbxx_hal_usart.c.

Referenced by HAL_USART_UnRegisterCallback(), USART_DMARxHalfCplt(), and USART_InitCallbacksToDefault().

HAL_StatusTypeDef HAL_USART_Transmit | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Simplex send an amount of data in blocking mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. In this case, Size must indicate the number of u16 provided through pTxData.
Parameters:
husart | USART handle.
pTxData | Pointer to data buffer (u8 or u16 data elements).
Size | Amount of data elements (u8 or u16) to be sent.
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 744 of file stm32wbxx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, __HAL_USART_CLEAR_OREFLAG, __HAL_USART_SEND_REQ, __USART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_READY, __USART_HandleTypeDef::Init, __USART_HandleTypeDef::Instance, USART_InitTypeDef::Parity, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, __USART_HandleTypeDef::TxXferSize, USART_CLEAR_TCF, USART_FLAG_TC, USART_FLAG_TXE, USART_PARITY_NONE, USART_RXDATA_FLUSH_REQUEST, USART_TXDATA_FLUSH_REQUEST, USART_WaitOnFlagUntilTimeout(), USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_USART_Transmit_DMA | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in DMA mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. In this case, Size must indicate the number of u16 provided through pTxData.
Parameters:
husart | USART handle.
pTxData | pointer to data buffer (u8 or u16 data elements).
Size | amount of data elements (u8 or u16) to be sent.
Return values:
HAL status

Definition at line 1388 of file stm32wbxx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, __USART_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_USART_ERROR_DMA, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_READY, __USART_HandleTypeDef::hdmatx, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::pTxBuffPtr, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, __USART_HandleTypeDef::TxXferSize, USART_CLEAR_TCF, USART_DMAError(), USART_DMATransmitCplt(), USART_DMATxHalfCplt(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_USART_Transmit_IT | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in interrupt mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data is handled as a set of u16. In this case, Size must indicate the number of u16 provided through pTxData.
Parameters:
husart | USART handle.
pTxData | pointer to data buffer (u8 or u16 data elements).
Size | amount of data elements (u8 or u16) to be sent.
Return values:
HAL status

Definition at line 1102 of file stm32wbxx_hal_usart.c.

References __HAL_USART_ENABLE_IT, __USART_HandleTypeDef::ErrorCode, __USART_HandleTypeDef::FifoMode, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_READY, __USART_HandleTypeDef::Init, USART_InitTypeDef::Parity, __USART_HandleTypeDef::pTxBuffPtr, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxISR, __USART_HandleTypeDef::TxXferCount, __USART_HandleTypeDef::TxXferSize, USART_FIFOMODE_ENABLE, USART_IT_TXE, USART_IT_TXFT, USART_PARITY_NONE, USART_TxISR_16BIT(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT(), USART_TxISR_8BIT_FIFOEN(), USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_USART_TransmitReceive | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Full-Duplex Send and Receive an amount of data in blocking mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number of u16 available through pTxData and through pRxData.
Parameters:
husart | USART handle.
pTxData | pointer to TX data buffer (u8 or u16 data elements).
pRxData | pointer to RX data buffer (u8 or u16 data elements).
Size | amount of data elements (u8 or u16) to be sent (same amount to be received).
Timeout | Timeout duration.
Return values:
HAL status

Definition at line 955 of file stm32wbxx_hal_usart.c.

References __USART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, __USART_HandleTypeDef::Init, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::Mask, USART_InitTypeDef::Parity, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::RxXferSize, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, __USART_HandleTypeDef::TxXferSize, USART_FLAG_RXNE, USART_FLAG_TXE, USART_MASK_COMPUTATION, USART_PARITY_NONE, USART_SLAVEMODE_ENABLE, USART_WaitOnFlagUntilTimeout(), USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Full-Duplex Transmit Receive an amount of data in non-blocking mode.

Note:
When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number of u16 available through pTxData and through pRxData.
Parameters:
husart | USART handle.
pTxData | pointer to TX data buffer (u8 or u16 data elements).
pRxData | pointer to RX data buffer (u8 or u16 data elements).
Size | amount of data elements (u8 or u16) to be received/sent.
Return values:
HAL status

Definition at line 1592 of file stm32wbxx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, __USART_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_DMA_Start_IT(), HAL_USART_ERROR_DMA, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, __USART_HandleTypeDef::hdmarx, __USART_HandleTypeDef::hdmatx, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::pRxBuffPtr, __USART_HandleTypeDef::pTxBuffPtr, __USART_HandleTypeDef::RxXferSize, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferSize, USART_CLEAR_TCF, USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxHalfCplt(), USART_DMATransmitCplt(), USART_DMATxHalfCplt(), __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_USART_TransmitReceive_IT | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Full-Duplex Send and Receive an amount of data in interrupt mode.

Note:
When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number of u16 available through pTxData and through pRxData.
Parameters:
husart | USART handle.
pTxData | pointer to TX data buffer (u8 or u16 data elements).
pRxData | pointer to RX data buffer (u8 or u16 data elements).
Size | amount of data elements (u8 or u16) to be sent (same amount to be received).
Return values:
HAL status

Definition at line 1291 of file stm32wbxx_hal_usart.c.

References __USART_HandleTypeDef::ErrorCode, __USART_HandleTypeDef::FifoMode, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, __USART_HandleTypeDef::Init, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::NbRxDataToProcess, USART_InitTypeDef::Parity, __USART_HandleTypeDef::pRxBuffPtr, __USART_HandleTypeDef::pTxBuffPtr, __USART_HandleTypeDef::RxISR, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::RxXferSize, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxISR, __USART_HandleTypeDef::TxXferCount, __USART_HandleTypeDef::TxXferSize, USART_FIFOMODE_ENABLE, USART_MASK_COMPUTATION, USART_PARITY_NONE, USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), USART_RxISR_8BIT_FIFOEN(), USART_TxISR_16BIT(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT(), USART_TxISR_8BIT_FIFOEN(), USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

void HAL_USART_TxCpltCallback ( USART_HandleTypeDef * husart )

Tx Transfer completed callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 2327 of file stm32wbxx_hal_usart.c.

Referenced by HAL_USART_UnRegisterCallback(), USART_DMATransmitCplt(), USART_EndTransmit_IT(), and USART_InitCallbacksToDefault().

void HAL_USART_TxHalfCpltCallback ( USART_HandleTypeDef * husart )

Tx Half Transfer completed callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 2342 of file stm32wbxx_hal_usart.c.

Referenced by HAL_USART_UnRegisterCallback(), USART_DMATxHalfCplt(), and USART_InitCallbacksToDefault().

void HAL_USART_TxRxCpltCallback ( USART_HandleTypeDef * husart )

Tx/Rx Transfers completed callback for the non-blocking process.

Parameters:
husart USART handle.
Return values:
None

Definition at line 2387 of file stm32wbxx_hal_usart.c.

Referenced by HAL_USART_UnRegisterCallback(), USART_DMAReceiveCplt(), USART_EndTransmit_IT(), USART_InitCallbacksToDefault(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Peripheral State and Error functions

Functions
Peripheral State and Error functions
USART Exported Functions

USART Peripheral State and Error functions. More...

Functions

HAL_USART_StateTypeDef | HAL_USART_GetState (USART_HandleTypeDef *husart)
Return the USART handle state.
uint32_t | HAL_USART_GetError (USART_HandleTypeDef *husart)
Return the USART error code.

Detailed Description

USART Peripheral State and Error functions.

  ==============================================================================
            ##### Peripheral State and Error functions #####
  ==============================================================================
    [..]
    This subsection provides functions allowing to :
      (+) Return the USART handle state
      (+) Return the USART handle error code

Function Documentation

uint32_t HAL_USART_GetError ( USART_HandleTypeDef * husart )

Return the USART error code.

Parameters:
husart pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART.
Return values:
USART handle Error Code

Definition at line 2465 of file stm32wbxx_hal_usart.c.

References __USART_HandleTypeDef::ErrorCode.

HAL_USART_StateTypeDef HAL_USART_GetState ( USART_HandleTypeDef * husart )

Return the USART handle state.

Parameters:
husart pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART.
Return values:
USART handle state

Definition at line 2454 of file stm32wbxx_hal_usart.c.

References __USART_HandleTypeDef::State.

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: USART Private Functions

Functions
USART Private Functions
USART

Functions

void | USART_InitCallbacksToDefault (USART_HandleTypeDef *husart)
Initialize the callbacks to their default values.
static void | USART_EndTransfer (USART_HandleTypeDef *husart)
End ongoing transfer on USART peripheral (following error detection or Transfer completion).
static void | USART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process complete callback.
static void | USART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process complete callback.
static void | USART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process half complete callback.
static void | USART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process half complete callback.
static void | USART_DMAError (DMA_HandleTypeDef *hdma)
DMA USART communication error callback.
static void | USART_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA USART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | USART_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA USART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | USART_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA USART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static HAL_StatusTypeDef | USART_WaitOnFlagUntilTimeout (USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle USART Communication Timeout.
static HAL_StatusTypeDef | USART_SetConfig (USART_HandleTypeDef *husart)
Configure the USART peripheral.
static HAL_StatusTypeDef | USART_CheckIdleState (USART_HandleTypeDef *husart)
Check the USART Idle State.
static void | USART_TxISR_8BIT (USART_HandleTypeDef *husart)
Simplex send an amount of data in non-blocking mode.
static void | USART_TxISR_16BIT (USART_HandleTypeDef *husart)
Simplex send an amount of data in non-blocking mode.
static void | USART_TxISR_8BIT_FIFOEN (USART_HandleTypeDef *husart)
Simplex send an amount of data in non-blocking mode.
static void | USART_TxISR_16BIT_FIFOEN (USART_HandleTypeDef *husart)
Simplex send an amount of data in non-blocking mode.
static void | USART_EndTransmit_IT (USART_HandleTypeDef *husart)
Wraps up transmission in non-blocking mode.
static void | USART_RxISR_8BIT (USART_HandleTypeDef *husart)
Simplex receive an amount of data in non-blocking mode.
static void | USART_RxISR_16BIT (USART_HandleTypeDef *husart)
Simplex receive an amount of data in non-blocking mode.
static void | USART_RxISR_8BIT_FIFOEN (USART_HandleTypeDef *husart)
Simplex receive an amount of data in non-blocking mode.
static void | USART_RxISR_16BIT_FIFOEN (USART_HandleTypeDef *husart)
Simplex receive an amount of data in non-blocking mode.

Function Documentation

static HAL_StatusTypeDef USART_CheckIdleState ( USART_HandleTypeDef * husart ) [static]

Check the USART Idle State.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 2946 of file stm32wbxx_hal_usart.c.

References __USART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_USART_ERROR_NONE, HAL_USART_STATE_READY, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::State, USART_TEACK_REACK_TIMEOUT, and USART_WaitOnFlagUntilTimeout().

Referenced by HAL_USART_Init().

static void USART_DMAAbortOnError ( DMA_HandleTypeDef * hdma ) [static]

DMA USART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2700 of file stm32wbxx_hal_usart.c.

References __USART_HandleTypeDef::ErrorCallback, HAL_USART_ErrorCallback(), __DMA_HandleTypeDef::Parent, __USART_HandleTypeDef::RxXferCount, and __USART_HandleTypeDef::TxXferCount.

Referenced by HAL_USART_IRQHandler().

static void USART_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA USART communication error callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2674 of file stm32wbxx_hal_usart.c.

References __USART_HandleTypeDef::ErrorCallback, __USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_DMA, HAL_USART_ErrorCallback(), HAL_USART_STATE_READY, __DMA_HandleTypeDef::Parent, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, and USART_EndTransfer().

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART receive process complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2581 of file stm32wbxx_hal_usart.c.

References HAL_USART_RxCpltCallback(), HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, HAL_USART_TxRxCpltCallback(), __DMA_HandleTypeDef::Instance, __USART_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, __USART_HandleTypeDef::RxCpltCallback, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::State, and __USART_HandleTypeDef::TxRxCpltCallback.

Referenced by HAL_USART_Receive_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMARxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA USART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Tx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2771 of file stm32wbxx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, __USART_HandleTypeDef::AbortCpltCallback, __USART_HandleTypeDef::ErrorCode, HAL_USART_AbortCpltCallback(), HAL_USART_ERROR_NONE, HAL_USART_STATE_READY, __USART_HandleTypeDef::hdmarx, __USART_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Parent, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, USART_CLEAR_FEF, USART_CLEAR_NEF, USART_CLEAR_OREF, USART_CLEAR_PEF, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_USART_Abort_IT().

static void USART_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART receive process half complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2656 of file stm32wbxx_hal_usart.c.

References HAL_USART_RxHalfCpltCallback(), __DMA_HandleTypeDef::Parent, and __USART_HandleTypeDef::RxHalfCpltCallback.

Referenced by HAL_USART_Receive_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART transmit process complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2523 of file stm32wbxx_hal_usart.c.

References __HAL_USART_ENABLE_IT, HAL_USART_STATE_BUSY_TX, HAL_USART_TxCpltCallback(), __DMA_HandleTypeDef::Instance, __USART_HandleTypeDef::Instance, __DMA_HandleTypeDef::Parent, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxCpltCallback, __USART_HandleTypeDef::TxXferCount, and USART_IT_TC.

Referenced by HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMATxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA USART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Rx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2723 of file stm32wbxx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, __USART_HandleTypeDef::AbortCpltCallback, __USART_HandleTypeDef::ErrorCode, HAL_USART_AbortCpltCallback(), HAL_USART_ERROR_NONE, HAL_USART_STATE_READY, __USART_HandleTypeDef::hdmarx, __USART_HandleTypeDef::hdmatx, __DMA_HandleTypeDef::Parent, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, USART_CLEAR_FEF, USART_CLEAR_NEF, USART_CLEAR_OREF, USART_CLEAR_PEF, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_USART_Abort_IT().

static void USART_DMATxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART transmit process half complete callback.

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2563 of file stm32wbxx_hal_usart.c.

References HAL_USART_TxHalfCpltCallback(), __DMA_HandleTypeDef::Parent, and __USART_HandleTypeDef::TxHalfCpltCallback.

Referenced by HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_EndTransfer ( USART_HandleTypeDef * husart ) [static]

End ongoing transfer on USART peripheral (following error detection or Transfer completion).

Parameters:
husart USART handle.
Return values:
None

Definition at line 2508 of file stm32wbxx_hal_usart.c.

References HAL_USART_STATE_READY, __USART_HandleTypeDef::Instance, and __USART_HandleTypeDef::State.

Referenced by HAL_USART_DMAStop(), HAL_USART_IRQHandler(), and USART_DMAError().

static void USART_EndTransmit_IT ( USART_HandleTypeDef * husart ) [static]

Wraps up transmission in non-blocking mode.

Parameters:
husart Pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
None

Definition at line 3155 of file stm32wbxx_hal_usart.c.

References __HAL_USART_CLEAR_OREFLAG, __HAL_USART_DISABLE_IT, __HAL_USART_SEND_REQ, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_READY, HAL_USART_TxCpltCallback(), HAL_USART_TxRxCpltCallback(), __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxCpltCallback, __USART_HandleTypeDef::TxISR, __USART_HandleTypeDef::TxRxCpltCallback, USART_IT_ERR, USART_IT_TC, and USART_RXDATA_FLUSH_REQUEST.

Referenced by HAL_USART_IRQHandler().

void USART_InitCallbacksToDefault ( USART_HandleTypeDef * husart )

Initialize the callbacks to their default values.

Parameters:
husart USART handle.
Return values:
none

Definition at line 2488 of file stm32wbxx_hal_usart.c.

References __USART_HandleTypeDef::AbortCpltCallback, __USART_HandleTypeDef::ErrorCallback, HAL_USART_AbortCpltCallback(), HAL_USART_ErrorCallback(), HAL_USART_RxCpltCallback(), HAL_USART_RxHalfCpltCallback(), HAL_USART_TxCpltCallback(), HAL_USART_TxHalfCpltCallback(), HAL_USART_TxRxCpltCallback(), HAL_USARTEx_RxFifoFullCallback(), HAL_USARTEx_TxFifoEmptyCallback(), __USART_HandleTypeDef::RxCpltCallback, __USART_HandleTypeDef::RxFifoFullCallback, __USART_HandleTypeDef::RxHalfCpltCallback, __USART_HandleTypeDef::TxCpltCallback, __USART_HandleTypeDef::TxFifoEmptyCallback, __USART_HandleTypeDef::TxHalfCpltCallback, and __USART_HandleTypeDef::TxRxCpltCallback.

Referenced by HAL_USART_Init().

static void USART_RxISR_16BIT ( USART_HandleTypeDef * husart ) [static]

Simplex receive an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_Receive_IT().
ISR function executed when FIFO mode is disabled and when the data word length is 9 bits long.
Parameters:
husart USART handle
Return values:
None

Definition at line 3300 of file stm32wbxx_hal_usart.c.

References __HAL_USART_CLEAR_UDRFLAG, __HAL_USART_SEND_REQ, HAL_USART_RxCpltCallback(), HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, HAL_USART_TxRxCpltCallback(), __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::Mask, __USART_HandleTypeDef::pRxBuffPtr, __USART_HandleTypeDef::RxCpltCallback, __USART_HandleTypeDef::RxISR, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxRxCpltCallback, __USART_HandleTypeDef::TxXferCount, USART_DUMMY_DATA, USART_SLAVEMODE_DISABLE, USART_SLAVEMODE_ENABLE, and USART_TXDATA_FLUSH_REQUEST.

Referenced by HAL_USART_Receive_IT(), HAL_USART_TransmitReceive_IT(), and USART_RxISR_16BIT_FIFOEN().

static void USART_RxISR_16BIT_FIFOEN ( USART_HandleTypeDef * husart ) [static]

Simplex receive an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_Receive_IT().
ISR function executed when FIFO mode is enabled and when the data word length is 9 bits long.
Parameters:
husart USART handle
Return values:
None

Definition at line 3519 of file stm32wbxx_hal_usart.c.

References __HAL_USART_CLEAR_UDRFLAG, __HAL_USART_GET_FLAG, __HAL_USART_SEND_REQ, HAL_USART_RxCpltCallback(), HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, HAL_USART_TxRxCpltCallback(), __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::Mask, __USART_HandleTypeDef::NbRxDataToProcess, __UART_HandleTypeDef::NbRxDataToProcess, __USART_HandleTypeDef::pRxBuffPtr, __USART_HandleTypeDef::RxCpltCallback, __USART_HandleTypeDef::RxISR, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxRxCpltCallback, __USART_HandleTypeDef::TxXferCount, USART_DUMMY_DATA, USART_FLAG_RXFNE, USART_RXDATA_FLUSH_REQUEST, USART_RxISR_16BIT(), USART_SLAVEMODE_DISABLE, USART_SLAVEMODE_ENABLE, and USART_TXDATA_FLUSH_REQUEST.

Referenced by HAL_USART_Receive_IT(), and HAL_USART_TransmitReceive_IT().

static void USART_RxISR_8BIT ( USART_HandleTypeDef * husart ) [static]

Simplex receive an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_Receive_IT().
ISR function executed when FIFO mode is disabled and when the data word length is less than 9 bits long.
Parameters:
husart USART handle
Return values:
None

Definition at line 3212 of file stm32wbxx_hal_usart.c.

References __HAL_USART_CLEAR_UDRFLAG, __HAL_USART_SEND_REQ, HAL_USART_RxCpltCallback(), HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, HAL_USART_TxRxCpltCallback(), __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::Mask, __USART_HandleTypeDef::pRxBuffPtr, __USART_HandleTypeDef::RxCpltCallback, __USART_HandleTypeDef::RxISR, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxRxCpltCallback, __USART_HandleTypeDef::TxXferCount, USART_DUMMY_DATA, USART_SLAVEMODE_DISABLE, USART_SLAVEMODE_ENABLE, and USART_TXDATA_FLUSH_REQUEST.

Referenced by HAL_USART_Receive_IT(), HAL_USART_TransmitReceive_IT(), and USART_RxISR_8BIT_FIFOEN().

static void USART_RxISR_8BIT_FIFOEN ( USART_HandleTypeDef * husart ) [static]

Simplex receive an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_Receive_IT().
ISR function executed when FIFO mode is enabled and when the data word length is less than 9 bits long.
Parameters:
husart USART handle
Return values:
None

Definition at line 3390 of file stm32wbxx_hal_usart.c.

References __HAL_USART_CLEAR_UDRFLAG, __HAL_USART_GET_FLAG, __HAL_USART_SEND_REQ, HAL_USART_RxCpltCallback(), HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, HAL_USART_TxRxCpltCallback(), __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::Mask, __USART_HandleTypeDef::NbRxDataToProcess, __UART_HandleTypeDef::NbRxDataToProcess, __USART_HandleTypeDef::pRxBuffPtr, __USART_HandleTypeDef::RxCpltCallback, __USART_HandleTypeDef::RxISR, __USART_HandleTypeDef::RxXferCount, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxRxCpltCallback, __USART_HandleTypeDef::TxXferCount, USART_DUMMY_DATA, USART_FLAG_RXFNE, USART_RXDATA_FLUSH_REQUEST, USART_RxISR_8BIT(), USART_SLAVEMODE_DISABLE, USART_SLAVEMODE_ENABLE, and USART_TXDATA_FLUSH_REQUEST.

Referenced by HAL_USART_Receive_IT(), and HAL_USART_TransmitReceive_IT().

static HAL_StatusTypeDef USART_SetConfig ( USART_HandleTypeDef * husart ) [static]

Configure the USART peripheral.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 2846 of file stm32wbxx_hal_usart.c.

References assert_param, USART_InitTypeDef::BaudRate, USART_InitTypeDef::CLKLastBit, USART_InitTypeDef::CLKPhase, USART_InitTypeDef::CLKPolarity, USART_InitTypeDef::ClockPrescaler, HAL_RCC_GetPCLK2Freq(), HAL_RCC_GetSysClockFreq(), HSI_VALUE, __USART_HandleTypeDef::Init, __USART_HandleTypeDef::Instance, IS_USART_BAUDRATE, IS_USART_LASTBIT, IS_USART_MODE, IS_USART_PARITY, IS_USART_PHASE, IS_USART_POLARITY, IS_USART_PRESCALER, IS_USART_STOPBITS, IS_USART_WORD_LENGTH, LSE_VALUE, USART_InitTypeDef::Mode, __USART_HandleTypeDef::NbRxDataToProcess, __USART_HandleTypeDef::NbTxDataToProcess, USART_InitTypeDef::Parity, __USART_HandleTypeDef::RxISR, USART_InitTypeDef::StopBits, __USART_HandleTypeDef::TxISR, USART_BRR_MAX, USART_BRR_MIN, USART_CLOCK_ENABLE, USART_CLOCKSOURCE_HSI, USART_CLOCKSOURCE_LSE, USART_CLOCKSOURCE_PCLK2, USART_CLOCKSOURCE_SYSCLK, USART_CR1_FIELDS, USART_CR2_FIELDS, USART_DIV_SAMPLING8, USART_GETCLOCKSOURCE, and USART_InitTypeDef::WordLength.

Referenced by HAL_USART_Init().

static void USART_TxISR_16BIT ( USART_HandleTypeDef * husart ) [static]

Simplex send an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_Transmit_IT().
The USART errors are not managed to avoid the overrun error.
ISR function executed when FIFO mode is disabled and when the data word length is 9 bits long.
Parameters:
husart USART handle.
Return values:
None

Definition at line 3031 of file stm32wbxx_hal_usart.c.

References __HAL_USART_DISABLE_IT, __HAL_USART_ENABLE_IT, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_BUSY_TX_RX, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::pTxBuffPtr, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, USART_IT_TC, and USART_IT_TXE.

Referenced by HAL_USART_Transmit_IT(), and HAL_USART_TransmitReceive_IT().

static void USART_TxISR_16BIT_FIFOEN ( USART_HandleTypeDef * husart ) [static]

Simplex send an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_Transmit_IT().
The USART errors are not managed to avoid the overrun error.
ISR function executed when FIFO mode is enabled and when the data word length is 9 bits long.
Parameters:
husart USART handle.
Return values:
None

Definition at line 3112 of file stm32wbxx_hal_usart.c.

References __HAL_USART_DISABLE_IT, __HAL_USART_ENABLE_IT, __HAL_USART_GET_FLAG, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_BUSY_TX_RX, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::NbTxDataToProcess, __USART_HandleTypeDef::pTxBuffPtr, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, USART_FLAG_TXFNF, USART_IT_TC, and USART_IT_TXFT.

Referenced by HAL_USART_Transmit_IT(), and HAL_USART_TransmitReceive_IT().

static void USART_TxISR_8BIT ( USART_HandleTypeDef * husart ) [static]

Simplex send an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_Transmit_IT().
The USART errors are not managed to avoid the overrun error.
ISR function executed when FIFO mode is disabled and when the data word length is less than 9 bits long.
Parameters:
husart USART handle.
Return values:
None

Definition at line 2996 of file stm32wbxx_hal_usart.c.

References __HAL_USART_DISABLE_IT, __HAL_USART_ENABLE_IT, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_BUSY_TX_RX, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::pTxBuffPtr, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, USART_IT_TC, and USART_IT_TXE.

Referenced by HAL_USART_Transmit_IT(), and HAL_USART_TransmitReceive_IT().

static void USART_TxISR_8BIT_FIFOEN ( USART_HandleTypeDef * husart ) [static]

Simplex send an amount of data in non-blocking mode.

Note:
Function called under interruption only, once interruptions have been enabled by HAL_USART_Transmit_IT().
The USART errors are not managed to avoid the overrun error.
ISR function executed when FIFO mode is enabled and when the data word length is less than 9 bits long.
Parameters:
husart USART handle.
Return values:
None

Definition at line 3067 of file stm32wbxx_hal_usart.c.

References __HAL_USART_DISABLE_IT, __HAL_USART_ENABLE_IT, __HAL_USART_GET_FLAG, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_BUSY_TX_RX, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::NbTxDataToProcess, __USART_HandleTypeDef::pTxBuffPtr, __USART_HandleTypeDef::State, __USART_HandleTypeDef::TxXferCount, USART_FLAG_TXFNF, USART_IT_TC, and USART_IT_TXFT.

Referenced by HAL_USART_Transmit_IT(), and HAL_USART_TransmitReceive_IT().

static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout | ( | USART_HandleTypeDef * | husart,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Tickstart,
 |  | uint32_t | Timeout
 | ) |  | [static]

Handle USART Communication Timeout.

Parameters:
husart | USART handle.
Flag | Specifies the USART flag to check.
Status | the Flag status (SET or RESET).
Tickstart | Tick start value
Timeout | timeout duration.
Return values:
HAL status

Definition at line 2819 of file stm32wbxx_hal_usart.c.

References __HAL_USART_GET_FLAG, HAL_GetTick(), HAL_USART_STATE_READY, and __USART_HandleTypeDef::State.

Referenced by HAL_USART_Receive(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), and USART_CheckIdleState().

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: USART Exported Types

Data Structures | Typedefs | Enumerations
USART Exported Types
USART

Data Structures

struct | USART_InitTypeDef
USART Init Structure definition. More...
struct | __USART_HandleTypeDef
USART handle Structure definition. More...

Typedefs

typedef struct
__USART_HandleTypeDef 		USART_HandleTypeDef
USART handle Structure definition.
typedef void(* | pUSART_CallbackTypeDef )(USART_HandleTypeDef *husart)
HAL USART Callback pointer definition.

Enumerations

enum HAL_USART_StateTypeDef {
HAL_USART_STATE_RESET = 0x00U, HAL_USART_STATE_READY = 0x01U, HAL_USART_STATE_BUSY = 0x02U, HAL_USART_STATE_BUSY_TX = 0x12U,
HAL_USART_STATE_BUSY_RX = 0x22U, HAL_USART_STATE_BUSY_TX_RX = 0x32U, HAL_USART_STATE_TIMEOUT = 0x03U, HAL_USART_STATE_ERROR = 0x04U
}
HAL USART State structures definition. More...
enum USART_ClockSourceTypeDef {
USART_CLOCKSOURCE_PCLK2 = 0x01U, USART_CLOCKSOURCE_HSI = 0x02U, USART_CLOCKSOURCE_SYSCLK = 0x04U, USART_CLOCKSOURCE_LSE = 0x08U,
USART_CLOCKSOURCE_UNDEFINED = 0x10U
}
USART clock sources definitions. More...
enum HAL_USART_CallbackIDTypeDef {
HAL_USART_TX_HALFCOMPLETE_CB_ID = 0x00U, HAL_USART_TX_COMPLETE_CB_ID = 0x01U, HAL_USART_RX_HALFCOMPLETE_CB_ID = 0x02U, HAL_USART_RX_COMPLETE_CB_ID = 0x03U,
HAL_USART_TX_RX_COMPLETE_CB_ID = 0x04U, HAL_USART_ERROR_CB_ID = 0x05U, HAL_USART_ABORT_COMPLETE_CB_ID = 0x06U, HAL_USART_RX_FIFO_FULL_CB_ID = 0x07U,
HAL_USART_TX_FIFO_EMPTY_CB_ID = 0x08U, HAL_USART_MSPINIT_CB_ID = 0x09U, HAL_USART_MSPDEINIT_CB_ID = 0x0AU
}
HAL USART Callback ID enumeration definition. More...

Typedef Documentation

typedef void(* pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart)

HAL USART Callback pointer definition.

pointer to an USART callback function

Definition at line 202 of file stm32wbxx_hal_usart.h.

typedef struct __USART_HandleTypeDef USART_HandleTypeDef

USART handle Structure definition.

Enumeration Type Documentation

enum HAL_USART_CallbackIDTypeDef

HAL USART Callback ID enumeration definition.

Enumerator:
HAL_USART_TX_HALFCOMPLETE_CB_ID

USART Tx Half Complete Callback ID

HAL_USART_TX_COMPLETE_CB_ID

USART Tx Complete Callback ID

HAL_USART_RX_HALFCOMPLETE_CB_ID

USART Rx Half Complete Callback ID

HAL_USART_RX_COMPLETE_CB_ID

USART Rx Complete Callback ID

HAL_USART_TX_RX_COMPLETE_CB_ID

USART Tx Rx Complete Callback ID

HAL_USART_ERROR_CB_ID

USART Error Callback ID

HAL_USART_ABORT_COMPLETE_CB_ID

USART Abort Complete Callback ID

HAL_USART_RX_FIFO_FULL_CB_ID

USART Rx Fifo Full Callback ID

HAL_USART_TX_FIFO_EMPTY_CB_ID

USART Tx Fifo Empty Callback ID

HAL_USART_MSPINIT_CB_ID

USART MspInit callback ID

HAL_USART_MSPDEINIT_CB_ID

USART MspDeInit callback ID

Definition at line 182 of file stm32wbxx_hal_usart.h.

enum HAL_USART_StateTypeDef

HAL USART State structures definition.

Enumerator:
HAL_USART_STATE_RESET

Peripheral is not initialized

HAL_USART_STATE_READY

Peripheral Initialized and ready for use

HAL_USART_STATE_BUSY

an internal process is ongoing

HAL_USART_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_USART_STATE_BUSY_RX

Data Reception process is ongoing

HAL_USART_STATE_BUSY_TX_RX

Data Transmission Reception process is ongoing

HAL_USART_STATE_TIMEOUT

Timeout state

HAL_USART_STATE_ERROR

Error

Definition at line 90 of file stm32wbxx_hal_usart.h.

enum USART_ClockSourceTypeDef

USART clock sources definitions.

Enumerator:
USART_CLOCKSOURCE_PCLK2

PCLK2 clock source

USART_CLOCKSOURCE_HSI

HSI clock source

USART_CLOCKSOURCE_SYSCLK

SYSCLK clock source

USART_CLOCKSOURCE_LSE

LSE clock source

USART_CLOCKSOURCE_UNDEFINED

Undefined clock source

Definition at line 105 of file stm32wbxx_hal_usart.h.

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: USART_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
USART_InitTypeDef Struct Reference
USART Exported Types

USART Init Structure definition. More...

#include <stm32wbxx_hal_usart.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | StopBits
uint32_t | Parity
uint32_t | Mode
uint32_t | CLKPolarity
uint32_t | CLKPhase
uint32_t | CLKLastBit
uint32_t | ClockPrescaler

Detailed Description

USART Init Structure definition.

Definition at line 47 of file stm32wbxx_hal_usart.h.

Field Documentation

uint32_t USART_InitTypeDef::BaudRate

This member configures the Usart communication baud rate. The baud rate is computed using the following formula: Baud Rate Register[15:4] = ((2 * fclk_pres) / ((huart->Init.BaudRate)))[15:4] Baud Rate Register[3] = 0 Baud Rate Register[2:0] = (((2 * fclk_pres) / ((huart->Init.BaudRate)))[3:0]) >> 1 where fclk_pres is the USART input clock frequency (fclk) divided by a prescaler.

Note:
Oversampling by 8 is systematically applied to achieve high baud rates.

Definition at line 49 of file stm32wbxx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::CLKLastBit

Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of USART Last Bit.

Definition at line 79 of file stm32wbxx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::CLKPhase

Specifies the clock transition on which the bit capture is made. This parameter can be a value of USART Clock Phase.

Definition at line 76 of file stm32wbxx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::CLKPolarity

Specifies the steady state of the serial clock. This parameter can be a value of USART Clock Polarity.

Definition at line 73 of file stm32wbxx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::ClockPrescaler

Specifies the prescaler value used to divide the USART clock source. This parameter can be a value of USART Clock Prescaler.

Definition at line 83 of file stm32wbxx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::Mode

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of USART Mode.

Definition at line 70 of file stm32wbxx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of USART Parity

Note:
When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits).

Definition at line 63 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_IT(), and USART_SetConfig().

uint32_t USART_InitTypeDef::StopBits

Specifies the number of stop bits transmitted. This parameter can be a value of USART Number of Stop Bits.

Definition at line 60 of file stm32wbxx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of USARTEx Word Length.

Definition at line 57 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_IT(), and USART_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_usart.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: __USART_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__USART_HandleTypeDef Struct Reference
USART Exported Types

USART handle Structure definition. More...

#include <stm32wbxx_hal_usart.h>

Data Fields

USART_TypeDef * | Instance
USART_InitTypeDef Init
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
__IO uint16_t | RxXferCount
uint16_t | Mask
uint16_t | NbRxDataToProcess
uint16_t | NbTxDataToProcess
uint32_t | SlaveMode
uint32_t | FifoMode
void(* | RxISR )(struct __USART_HandleTypeDef *husart)
void(* | TxISR )(struct __USART_HandleTypeDef *husart)
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_USART_StateTypeDef | State
__IO uint32_t | ErrorCode
void(* | TxHalfCpltCallback )(struct __USART_HandleTypeDef *husart)
void(* | TxCpltCallback )(struct __USART_HandleTypeDef *husart)
void(* | RxHalfCpltCallback )(struct __USART_HandleTypeDef *husart)
void(* | RxCpltCallback )(struct __USART_HandleTypeDef *husart)
void(* | TxRxCpltCallback )(struct __USART_HandleTypeDef *husart)
void(* | ErrorCallback )(struct __USART_HandleTypeDef *husart)
void(* | AbortCpltCallback )(struct __USART_HandleTypeDef *husart)
void(* | RxFifoFullCallback )(struct __USART_HandleTypeDef *husart)
void(* | TxFifoEmptyCallback )(struct __USART_HandleTypeDef *husart)
void(* | MspInitCallback )(struct __USART_HandleTypeDef *husart)
void(* | MspDeInitCallback )(struct __USART_HandleTypeDef *husart)

Detailed Description

USART handle Structure definition.

Definition at line 117 of file stm32wbxx_hal_usart.h.

Field Documentation

void(* __USART_HandleTypeDef::AbortCpltCallback)(struct __USART_HandleTypeDef *husart)

USART Abort Complete Callback

Definition at line 168 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Abort_IT(), HAL_USART_RegisterCallback(), HAL_USART_UnRegisterCallback(), USART_DMARxAbortCallback(), USART_DMATxAbortCallback(), and USART_InitCallbacksToDefault().

void(* __USART_HandleTypeDef::ErrorCallback)(struct __USART_HandleTypeDef *husart)

USART Error Callback

Definition at line 167 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_IRQHandler(), HAL_USART_RegisterCallback(), HAL_USART_UnRegisterCallback(), USART_DMAAbortOnError(), USART_DMAError(), and USART_InitCallbacksToDefault().

__IO uint32_t __USART_HandleTypeDef::ErrorCode

USART Error code

Definition at line 159 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DeInit(), HAL_USART_DMAStop(), HAL_USART_GetError(), HAL_USART_IRQHandler(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_RegisterCallback(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), HAL_USART_UnRegisterCallback(), USART_CheckIdleState(), USART_DMAError(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

uint32_t __USART_HandleTypeDef::FifoMode

Specifies if the FIFO mode will be used. This parameter can be a value of USARTEx FIFO mode.

Definition at line 144 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_Receive_IT(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive_IT(), HAL_USARTEx_DisableFifoMode(), HAL_USARTEx_EnableFifoMode(), and USARTEx_SetNbDataToProcess().

DMA_HandleTypeDef* __USART_HandleTypeDef::hdmarx

USART Rx DMA Handle parameters

Definition at line 153 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DMAStop(), HAL_USART_IRQHandler(), HAL_USART_Receive_DMA(), HAL_USART_TransmitReceive_DMA(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

DMA_HandleTypeDef* __USART_HandleTypeDef::hdmatx

USART Tx DMA Handle parameters

Definition at line 151 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DMAStop(), HAL_USART_IRQHandler(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive_DMA(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

USART_InitTypeDef __USART_HandleTypeDef::Init

USART communication parameters

Definition at line 121 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_IT(), and USART_SetConfig().

USART_TypeDef* __USART_HandleTypeDef::Instance

USART registers base address

Definition at line 119 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DeInit(), HAL_USART_DMAPause(), HAL_USART_DMAResume(), HAL_USART_DMAStop(), HAL_USART_Init(), HAL_USART_IRQHandler(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), HAL_USARTEx_ConfigNSS(), HAL_USARTEx_DisableFifoMode(), HAL_USARTEx_DisableSlaveMode(), HAL_USARTEx_EnableFifoMode(), HAL_USARTEx_EnableSlaveMode(), HAL_USARTEx_SetRxFifoThreshold(), HAL_USARTEx_SetTxFifoThreshold(), USART_CheckIdleState(), USART_DMAReceiveCplt(), USART_DMATransmitCplt(), USART_EndTransfer(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), USART_RxISR_8BIT_FIFOEN(), USART_SetConfig(), USART_TxISR_16BIT(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT(), USART_TxISR_8BIT_FIFOEN(), and USARTEx_SetNbDataToProcess().

HAL_LockTypeDef __USART_HandleTypeDef::Lock

Locking object

Definition at line 155 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Init().

uint16_t __USART_HandleTypeDef::Mask

USART Rx RDR register mask

Definition at line 135 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_TransmitReceive(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

void(* __USART_HandleTypeDef::MspDeInitCallback)(struct __USART_HandleTypeDef *husart)

USART Msp DeInit callback

Definition at line 173 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_DeInit(), HAL_USART_RegisterCallback(), and HAL_USART_UnRegisterCallback().

void(* __USART_HandleTypeDef::MspInitCallback)(struct __USART_HandleTypeDef *husart)

USART Msp Init callback

Definition at line 172 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Init(), HAL_USART_RegisterCallback(), and HAL_USART_UnRegisterCallback().

uint16_t __USART_HandleTypeDef::NbRxDataToProcess

Number of data to process during RX ISR execution

Definition at line 137 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Receive_IT(), HAL_USART_TransmitReceive_IT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT_FIFOEN(), USART_SetConfig(), and USARTEx_SetNbDataToProcess().

uint16_t __USART_HandleTypeDef::NbTxDataToProcess

Number of data to process during TX ISR execution

Definition at line 139 of file stm32wbxx_hal_usart.h.

Referenced by USART_SetConfig(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT_FIFOEN(), and USARTEx_SetNbDataToProcess().

uint8_t* __USART_HandleTypeDef::pRxBuffPtr

Pointer to USART Rx transfer Buffer

Definition at line 129 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

uint8_t* __USART_HandleTypeDef::pTxBuffPtr

Pointer to USART Tx transfer Buffer

Definition at line 123 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_TxISR_16BIT(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT(), and USART_TxISR_8BIT_FIFOEN().

void(* __USART_HandleTypeDef::RxCpltCallback)(struct __USART_HandleTypeDef *husart)

USART Rx Complete Callback

Definition at line 165 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_RegisterCallback(), HAL_USART_UnRegisterCallback(), USART_DMAReceiveCplt(), USART_InitCallbacksToDefault(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

void(* __USART_HandleTypeDef::RxFifoFullCallback)(struct __USART_HandleTypeDef *husart)

USART Rx Fifo Full Callback

Definition at line 169 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_IRQHandler(), HAL_USART_RegisterCallback(), HAL_USART_UnRegisterCallback(), and USART_InitCallbacksToDefault().

void(* __USART_HandleTypeDef::RxHalfCpltCallback)(struct __USART_HandleTypeDef *husart)

USART Rx Half Complete Callback

Definition at line 164 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_RegisterCallback(), HAL_USART_UnRegisterCallback(), USART_DMARxHalfCplt(), and USART_InitCallbacksToDefault().

void(* __USART_HandleTypeDef::RxISR)(struct __USART_HandleTypeDef *husart)

Function pointer on Rx IRQ handler

Definition at line 147 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_IRQHandler(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive_IT(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), USART_RxISR_8BIT_FIFOEN(), and USART_SetConfig().

__IO uint16_t __USART_HandleTypeDef::RxXferCount

USART Rx Transfer Counter

Definition at line 133 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_IT(), USART_DMAAbortOnError(), USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxAbortCallback(), USART_DMATxAbortCallback(), USART_EndTransmit_IT(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

uint16_t __USART_HandleTypeDef::RxXferSize

USART Rx Transfer size

Definition at line 131 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), and HAL_USART_TransmitReceive_IT().

uint32_t __USART_HandleTypeDef::SlaveMode

Enable/Disable UART SPI Slave Mode. This parameter can be a value of USARTEx Synchronous Slave mode enable

Definition at line 141 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive(), HAL_USARTEx_DisableSlaveMode(), HAL_USARTEx_EnableSlaveMode(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

__IO HAL_USART_StateTypeDef __USART_HandleTypeDef::State

USART communication state

Definition at line 157 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DeInit(), HAL_USART_DMAPause(), HAL_USART_DMAResume(), HAL_USART_DMAStop(), HAL_USART_GetState(), HAL_USART_Init(), HAL_USART_IRQHandler(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_RegisterCallback(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), HAL_USART_UnRegisterCallback(), HAL_USARTEx_ConfigNSS(), HAL_USARTEx_DisableFifoMode(), HAL_USARTEx_DisableSlaveMode(), HAL_USARTEx_EnableFifoMode(), HAL_USARTEx_EnableSlaveMode(), HAL_USARTEx_SetRxFifoThreshold(), HAL_USARTEx_SetTxFifoThreshold(), USART_CheckIdleState(), USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxAbortCallback(), USART_DMATransmitCplt(), USART_DMATxAbortCallback(), USART_EndTransfer(), USART_EndTransmit_IT(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), USART_RxISR_8BIT_FIFOEN(), USART_TxISR_16BIT(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT(), USART_TxISR_8BIT_FIFOEN(), and USART_WaitOnFlagUntilTimeout().

void(* __USART_HandleTypeDef::TxCpltCallback)(struct __USART_HandleTypeDef *husart)

USART Tx Complete Callback

Definition at line 163 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_RegisterCallback(), HAL_USART_UnRegisterCallback(), USART_DMATransmitCplt(), USART_EndTransmit_IT(), and USART_InitCallbacksToDefault().

void(* __USART_HandleTypeDef::TxFifoEmptyCallback)(struct __USART_HandleTypeDef *husart)

USART Tx Fifo Empty Callback

Definition at line 170 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_IRQHandler(), HAL_USART_RegisterCallback(), HAL_USART_UnRegisterCallback(), and USART_InitCallbacksToDefault().

void(* __USART_HandleTypeDef::TxHalfCpltCallback)(struct __USART_HandleTypeDef *husart)

USART Tx Half Complete Callback

Definition at line 162 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_RegisterCallback(), HAL_USART_UnRegisterCallback(), USART_DMATxHalfCplt(), and USART_InitCallbacksToDefault().

void(* __USART_HandleTypeDef::TxISR)(struct __USART_HandleTypeDef *husart)

Function pointer on Tx IRQ handler

Definition at line 149 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_IRQHandler(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive_IT(), USART_EndTransmit_IT(), and USART_SetConfig().

void(* __USART_HandleTypeDef::TxRxCpltCallback)(struct __USART_HandleTypeDef *husart)

USART Tx Rx Complete Callback

Definition at line 166 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_RegisterCallback(), HAL_USART_UnRegisterCallback(), USART_DMAReceiveCplt(), USART_EndTransmit_IT(), USART_InitCallbacksToDefault(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

__IO uint16_t __USART_HandleTypeDef::TxXferCount

USART Tx Transfer Counter

Definition at line 127 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_IT(), USART_DMAAbortOnError(), USART_DMAError(), USART_DMARxAbortCallback(), USART_DMATransmitCplt(), USART_DMATxAbortCallback(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), USART_RxISR_8BIT_FIFOEN(), USART_TxISR_16BIT(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT(), and USART_TxISR_8BIT_FIFOEN().

uint16_t __USART_HandleTypeDef::TxXferSize

USART Tx Transfer size

Definition at line 125 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), and HAL_USART_TransmitReceive_IT().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_usart.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: USART Error Definition

Defines
USART Error Definition
USART Exported Constants

Defines

#define | HAL_USART_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_USART_ERROR_PE ((uint32_t)0x00000001U)
#define | HAL_USART_ERROR_NE ((uint32_t)0x00000002U)
#define | HAL_USART_ERROR_FE ((uint32_t)0x00000004U)
#define | HAL_USART_ERROR_ORE ((uint32_t)0x00000008U)
#define | HAL_USART_ERROR_DMA ((uint32_t)0x00000010U)
#define | HAL_USART_ERROR_UDR ((uint32_t)0x00000020U)
#define | HAL_USART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U)

Define Documentation

#define HAL_USART_ERROR_DMA ((uint32_t)0x00000010U)

DMA transfer error

Definition at line 223 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_DMAStop(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive_DMA(), and USART_DMAError().

#define HAL_USART_ERROR_FE ((uint32_t)0x00000004U)

frame error

Definition at line 221 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define HAL_USART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U)

Invalid Callback error

Definition at line 226 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_RegisterCallback(), and HAL_USART_UnRegisterCallback().

#define HAL_USART_ERROR_NE ((uint32_t)0x00000002U)

Noise error

Definition at line 220 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define HAL_USART_ERROR_NONE ((uint32_t)0x00000000U)

No error

Definition at line 218 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DeInit(), HAL_USART_IRQHandler(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_CheckIdleState(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

#define HAL_USART_ERROR_ORE ((uint32_t)0x00000008U)

Overrun error

Definition at line 222 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define HAL_USART_ERROR_PE ((uint32_t)0x00000001U)

Parity error

Definition at line 219 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define HAL_USART_ERROR_UDR ((uint32_t)0x00000020U)

SPI slave underrun error

Definition at line 224 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: USART Number of Stop Bits

Defines
USART Number of Stop Bits
USART Exported Constants

Defines

#define | USART_STOPBITS_0_5 USART_CR2_STOP_0
#define | USART_STOPBITS_1 0x00000000U
#define | USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define | USART_STOPBITS_2 USART_CR2_STOP_1

Define Documentation

#define USART_STOPBITS_0_5 USART_CR2_STOP_0

USART frame with 0.5 stop bit

Definition at line 235 of file stm32wbxx_hal_usart.h.

#define USART_STOPBITS_1 0x00000000U

USART frame with 1 stop bit

Definition at line 236 of file stm32wbxx_hal_usart.h.

#define USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)

USART frame with 1.5 stop bits

Definition at line 237 of file stm32wbxx_hal_usart.h.

#define USART_STOPBITS_2 USART_CR2_STOP_1

USART frame with 2 stop bits

Definition at line 238 of file stm32wbxx_hal_usart.h.

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: USART Parity

Defines
USART Parity
USART Exported Constants

Defines

#define | USART_PARITY_NONE 0x00000000U
#define | USART_PARITY_EVEN USART_CR1_PCE
#define | USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Define Documentation

#define USART_PARITY_EVEN USART_CR1_PCE

Even parity

Definition at line 247 of file stm32wbxx_hal_usart.h.

#define USART_PARITY_NONE 0x00000000U

No parity

Definition at line 246 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), and HAL_USART_TransmitReceive_IT().

#define USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Odd parity

Definition at line 248 of file stm32wbxx_hal_usart.h.

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: USART Mode

Defines
USART Mode
USART Exported Constants

Defines

#define | USART_MODE_RX USART_CR1_RE
#define | USART_MODE_TX USART_CR1_TE
#define | USART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)

Define Documentation

#define USART_MODE_RX USART_CR1_RE

RX mode

Definition at line 256 of file stm32wbxx_hal_usart.h.

#define USART_MODE_TX USART_CR1_TE

TX mode

Definition at line 257 of file stm32wbxx_hal_usart.h.

#define USART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)

RX and TX mode

Definition at line 258 of file stm32wbxx_hal_usart.h.

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: USART Over Sampling

Defines
USART Over Sampling
USART Exported Constants

Defines

#define | USART_OVERSAMPLING_16 0x00000000U
#define | USART_OVERSAMPLING_8 USART_CR1_OVER8

Define Documentation

#define USART_OVERSAMPLING_16 0x00000000U

Oversampling by 16

Definition at line 266 of file stm32wbxx_hal_usart.h.

#define USART_OVERSAMPLING_8 USART_CR1_OVER8

Oversampling by 8

Definition at line 267 of file stm32wbxx_hal_usart.h.

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: USART Clock

Defines
USART Clock
USART Exported Constants

Defines

#define | USART_CLOCK_DISABLE 0x00000000U
#define | USART_CLOCK_ENABLE USART_CR2_CLKEN

Define Documentation

#define USART_CLOCK_DISABLE 0x00000000U

USART clock disable

Definition at line 275 of file stm32wbxx_hal_usart.h.

#define USART_CLOCK_ENABLE USART_CR2_CLKEN

USART clock enable

Definition at line 276 of file stm32wbxx_hal_usart.h.

Referenced by USART_SetConfig().

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: USART Clock Polarity

Defines
USART Clock Polarity
USART Exported Constants

Defines

#define | USART_POLARITY_LOW 0x00000000U
#define | USART_POLARITY_HIGH USART_CR2_CPOL

Define Documentation

#define USART_POLARITY_HIGH USART_CR2_CPOL

Driver enable signal is active low

Definition at line 285 of file stm32wbxx_hal_usart.h.

#define USART_POLARITY_LOW 0x00000000U

Driver enable signal is active high

Definition at line 284 of file stm32wbxx_hal_usart.h.

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: USART Clock Phase

Defines
USART Clock Phase
USART Exported Constants

Defines

#define | USART_PHASE_1EDGE 0x00000000U
#define | USART_PHASE_2EDGE USART_CR2_CPHA

Define Documentation

#define USART_PHASE_1EDGE 0x00000000U

USART frame phase on first clock transition

Definition at line 293 of file stm32wbxx_hal_usart.h.

#define USART_PHASE_2EDGE USART_CR2_CPHA

USART frame phase on second clock transition

Definition at line 294 of file stm32wbxx_hal_usart.h.

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: USART Last Bit

Defines
USART Last Bit
USART Exported Constants

Defines

#define | USART_LASTBIT_DISABLE 0x00000000U
#define | USART_LASTBIT_ENABLE USART_CR2_LBCL

Define Documentation

#define USART_LASTBIT_DISABLE 0x00000000U

USART frame last data bit clock pulse not output to SCLK pin

Definition at line 302 of file stm32wbxx_hal_usart.h.

#define USART_LASTBIT_ENABLE USART_CR2_LBCL

USART frame last data bit clock pulse output to SCLK pin

Definition at line 303 of file stm32wbxx_hal_usart.h.

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: USART Clock Prescaler

Defines
USART Clock Prescaler
USART Exported Constants

Defines

#define | USART_PRESCALER_DIV1 0x00000000U
#define | USART_PRESCALER_DIV2 0x00000001U
#define | USART_PRESCALER_DIV4 0x00000002U
#define | USART_PRESCALER_DIV6 0x00000003U
#define | USART_PRESCALER_DIV8 0x00000004U
#define | USART_PRESCALER_DIV10 0x00000005U
#define | USART_PRESCALER_DIV12 0x00000006U
#define | USART_PRESCALER_DIV16 0x00000007U
#define | USART_PRESCALER_DIV32 0x00000008U
#define | USART_PRESCALER_DIV64 0x00000009U
#define | USART_PRESCALER_DIV128 0x0000000AU
#define | USART_PRESCALER_DIV256 0x0000000BU

Define Documentation

#define USART_PRESCALER_DIV1 0x00000000U

fclk_pres = fclk

Definition at line 311 of file stm32wbxx_hal_usart.h.

#define USART_PRESCALER_DIV10 0x00000005U

fclk_pres = fclk/10

Definition at line 316 of file stm32wbxx_hal_usart.h.

#define USART_PRESCALER_DIV12 0x00000006U

fclk_pres = fclk/12

Definition at line 317 of file stm32wbxx_hal_usart.h.

#define USART_PRESCALER_DIV128 0x0000000AU

fclk_pres = fclk/128

Definition at line 321 of file stm32wbxx_hal_usart.h.

#define USART_PRESCALER_DIV16 0x00000007U

fclk_pres = fclk/16

Definition at line 318 of file stm32wbxx_hal_usart.h.

#define USART_PRESCALER_DIV2 0x00000001U

fclk_pres = fclk/2

Definition at line 312 of file stm32wbxx_hal_usart.h.

#define USART_PRESCALER_DIV256 0x0000000BU

fclk_pres = fclk/256

Definition at line 322 of file stm32wbxx_hal_usart.h.

#define USART_PRESCALER_DIV32 0x00000008U

fclk_pres = fclk/32

Definition at line 319 of file stm32wbxx_hal_usart.h.

#define USART_PRESCALER_DIV4 0x00000002U

fclk_pres = fclk/4

Definition at line 313 of file stm32wbxx_hal_usart.h.

#define USART_PRESCALER_DIV6 0x00000003U

fclk_pres = fclk/6

Definition at line 314 of file stm32wbxx_hal_usart.h.

#define USART_PRESCALER_DIV64 0x00000009U

fclk_pres = fclk/64

Definition at line 320 of file stm32wbxx_hal_usart.h.

#define USART_PRESCALER_DIV8 0x00000004U

fclk_pres = fclk/8

Definition at line 315 of file stm32wbxx_hal_usart.h.

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: USART Request Parameters

Defines
USART Request Parameters
USART Exported Constants

Defines

#define | USART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ
#define | USART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ

Define Documentation

#define USART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ

Receive Data flush Request

Definition at line 331 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_Transmit(), USART_EndTransmit_IT(), USART_RxISR_16BIT_FIFOEN(), and USART_RxISR_8BIT_FIFOEN().

#define USART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ

Transmit data flush Request

Definition at line 332 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_Receive(), HAL_USART_Transmit(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: USART Flags

Defines
USART Flags
USART Exported Constants

Elements values convention: 0xXXXX. More...

Defines

#define | USART_FLAG_TXFT USART_ISR_TXFT
#define | USART_FLAG_RXFT USART_ISR_RXFT
#define | USART_FLAG_RXFF USART_ISR_RXFF
#define | USART_FLAG_TXFE USART_ISR_TXFE
#define | USART_FLAG_REACK USART_ISR_REACK
#define | USART_FLAG_TEACK USART_ISR_TEACK
#define | USART_FLAG_BUSY USART_ISR_BUSY
#define | USART_FLAG_UDR USART_ISR_UDR
#define | USART_FLAG_TXE USART_ISR_TXE_TXFNF
#define | USART_FLAG_TXFNF USART_ISR_TXE_TXFNF
#define | USART_FLAG_TC USART_ISR_TC
#define | USART_FLAG_RXNE USART_ISR_RXNE_RXFNE
#define | USART_FLAG_RXFNE USART_ISR_RXNE_RXFNE
#define | USART_FLAG_IDLE USART_ISR_IDLE
#define | USART_FLAG_ORE USART_ISR_ORE
#define | USART_FLAG_NE USART_ISR_NE
#define | USART_FLAG_FE USART_ISR_FE
#define | USART_FLAG_PE USART_ISR_PE

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the ISR register

Define Documentation

#define USART_FLAG_BUSY USART_ISR_BUSY

USART busy flag

Definition at line 348 of file stm32wbxx_hal_usart.h.

#define USART_FLAG_FE USART_ISR_FE

USART frame error

Definition at line 358 of file stm32wbxx_hal_usart.h.

#define USART_FLAG_IDLE USART_ISR_IDLE

USART idle flag

Definition at line 355 of file stm32wbxx_hal_usart.h.

#define USART_FLAG_NE USART_ISR_NE

USART noise error

Definition at line 357 of file stm32wbxx_hal_usart.h.

#define USART_FLAG_ORE USART_ISR_ORE

USART overrun error

Definition at line 356 of file stm32wbxx_hal_usart.h.

#define USART_FLAG_PE USART_ISR_PE

USART parity error

Definition at line 359 of file stm32wbxx_hal_usart.h.

#define USART_FLAG_REACK USART_ISR_REACK

USART receive enable acknowledge flag

Definition at line 346 of file stm32wbxx_hal_usart.h.

#define USART_FLAG_RXFF USART_ISR_RXFF

USART RXFIFO Full flag

Definition at line 344 of file stm32wbxx_hal_usart.h.

#define USART_FLAG_RXFNE USART_ISR_RXNE_RXFNE

USART RXFIFO not empty

Definition at line 354 of file stm32wbxx_hal_usart.h.

Referenced by USART_RxISR_16BIT_FIFOEN(), and USART_RxISR_8BIT_FIFOEN().

#define USART_FLAG_RXFT USART_ISR_RXFT

USART RXFIFO threshold flag

Definition at line 343 of file stm32wbxx_hal_usart.h.

#define USART_FLAG_RXNE USART_ISR_RXNE_RXFNE

USART read data register not empty

Definition at line 353 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Receive(), and HAL_USART_TransmitReceive().

#define USART_FLAG_TC USART_ISR_TC

USART transmission complete

Definition at line 352 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Transmit().

#define USART_FLAG_TEACK USART_ISR_TEACK

USART transmit enable acknowledge flag

Definition at line 347 of file stm32wbxx_hal_usart.h.

#define USART_FLAG_TXE USART_ISR_TXE_TXFNF

USART transmit data register empty

Definition at line 350 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Transmit(), and HAL_USART_TransmitReceive().

#define USART_FLAG_TXFE USART_ISR_TXFE

USART TXFIFO Empty flag

Definition at line 345 of file stm32wbxx_hal_usart.h.

#define USART_FLAG_TXFNF USART_ISR_TXE_TXFNF

USART TXFIFO not full

Definition at line 351 of file stm32wbxx_hal_usart.h.

Referenced by USART_TxISR_16BIT_FIFOEN(), and USART_TxISR_8BIT_FIFOEN().

#define USART_FLAG_TXFT USART_ISR_TXFT

USART TXFIFO threshold flag

Definition at line 342 of file stm32wbxx_hal_usart.h.

#define USART_FLAG_UDR USART_ISR_UDR

SPI slave underrun error flag

Definition at line 349 of file stm32wbxx_hal_usart.h.

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: USART Interrupts Definition

Defines
USART Interrupts Definition
USART Exported Constants

Elements values convention: 0000ZZZZ0XXYYYYYb. More...

Defines

#define | USART_IT_PE 0x0028U
#define | USART_IT_TXE 0x0727U
#define | USART_IT_TXFNF 0x0727U
#define | USART_IT_TC 0x0626U
#define | USART_IT_RXNE 0x0525U
#define | USART_IT_RXFNE 0x0525U
#define | USART_IT_IDLE 0x0424U
#define | USART_IT_ERR 0x0060U
#define | USART_IT_ORE 0x0300U
#define | USART_IT_NE 0x0200U
#define | USART_IT_FE 0x0100U
#define | USART_IT_RXFF 0x183FU
#define | USART_IT_TXFE 0x173EU
#define | USART_IT_RXFT 0x1A7CU
#define | USART_IT_TXFT 0x1B77U

Detailed Description

Elements values convention: 0000ZZZZ0XXYYYYYb.

  • YYYYY : Interrupt source position in the XX register (5bits)
  • XX : Interrupt source register (2bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register
  • ZZZZ : Flag position in the ISR register(4bits)

Define Documentation

#define USART_IT_ERR 0x0060U

USART error interruption

Definition at line 382 of file stm32wbxx_hal_usart.h.

Referenced by USART_EndTransmit_IT().

#define USART_IT_FE 0x0100U

USART frame error interruption

Definition at line 385 of file stm32wbxx_hal_usart.h.

#define USART_IT_IDLE 0x0424U

USART idle interruption

Definition at line 381 of file stm32wbxx_hal_usart.h.

#define USART_IT_NE 0x0200U

USART noise error interruption

Definition at line 384 of file stm32wbxx_hal_usart.h.

#define USART_IT_ORE 0x0300U

USART overrun error interruption

Definition at line 383 of file stm32wbxx_hal_usart.h.

#define USART_IT_PE 0x0028U

USART parity error interruption

Definition at line 375 of file stm32wbxx_hal_usart.h.

#define USART_IT_RXFF 0x183FU

USART RXFIFO full interruption

Definition at line 386 of file stm32wbxx_hal_usart.h.

#define USART_IT_RXFNE 0x0525U

USART RXFIFO not empty interruption

Definition at line 380 of file stm32wbxx_hal_usart.h.

#define USART_IT_RXFT 0x1A7CU

USART RXFIFO threshold reached interruption

Definition at line 388 of file stm32wbxx_hal_usart.h.

#define USART_IT_RXNE 0x0525U

USART read data register not empty interruption

Definition at line 379 of file stm32wbxx_hal_usart.h.

#define USART_IT_TC 0x0626U

USART transmission complete interruption

Definition at line 378 of file stm32wbxx_hal_usart.h.

Referenced by USART_DMATransmitCplt(), USART_EndTransmit_IT(), USART_TxISR_16BIT(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT(), and USART_TxISR_8BIT_FIFOEN().

#define USART_IT_TXE 0x0727U

USART transmit data register empty interruption

Definition at line 376 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Transmit_IT(), USART_TxISR_16BIT(), and USART_TxISR_8BIT().

#define USART_IT_TXFE 0x173EU

USART TXFIFO empty interruption

Definition at line 387 of file stm32wbxx_hal_usart.h.

#define USART_IT_TXFNF 0x0727U

USART TX FIFO not full interruption

Definition at line 377 of file stm32wbxx_hal_usart.h.

#define USART_IT_TXFT 0x1B77U

USART TXFIFO threshold reached interruption

Definition at line 389 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Transmit_IT(), USART_TxISR_16BIT_FIFOEN(), and USART_TxISR_8BIT_FIFOEN().

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: USART Interruption Clear Flags

Defines
USART Interruption Clear Flags
USART Exported Constants

Defines

#define | USART_CLEAR_PEF USART_ICR_PECF
#define | USART_CLEAR_FEF USART_ICR_FECF
#define | USART_CLEAR_NEF USART_ICR_NECF
#define | USART_CLEAR_OREF USART_ICR_ORECF
#define | USART_CLEAR_IDLEF USART_ICR_IDLECF
#define | USART_CLEAR_TCF USART_ICR_TCCF
#define | USART_CLEAR_UDRF USART_ICR_UDRCF
#define | USART_CLEAR_TXFECF USART_ICR_TXFECF

Define Documentation

#define USART_CLEAR_FEF USART_ICR_FECF

Framing Error Clear Flag

Definition at line 399 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_IRQHandler(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

#define USART_CLEAR_IDLEF USART_ICR_IDLECF

IDLE line detected Clear Flag

Definition at line 402 of file stm32wbxx_hal_usart.h.

#define USART_CLEAR_NEF USART_ICR_NECF

Noise Error detected Clear Flag

Definition at line 400 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_IRQHandler(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

#define USART_CLEAR_OREF USART_ICR_ORECF

OverRun Error Clear Flag

Definition at line 401 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DMAResume(), HAL_USART_IRQHandler(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

#define USART_CLEAR_PEF USART_ICR_PECF

Parity Error Clear Flag

Definition at line 398 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_IRQHandler(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

#define USART_CLEAR_TCF USART_ICR_TCCF

Transmission Complete Clear Flag

Definition at line 403 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

#define USART_CLEAR_TXFECF USART_ICR_TXFECF

TXFIFO Empty Clear Flag

Definition at line 405 of file stm32wbxx_hal_usart.h.

#define USART_CLEAR_UDRF USART_ICR_UDRCF

SPI slave underrun error Clear Flag

Definition at line 404 of file stm32wbxx_hal_usart.h.

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: USART Interruption Flags Mask

Defines
USART Interruption Flags Mask
USART Exported Constants

Defines

#define | USART_IT_MASK 0x001FU
#define | USART_CR_MASK 0x00E0U
#define | USART_CR_POS 5U

Define Documentation

#define USART_CR_MASK 0x00E0U

USART control register mask

Definition at line 414 of file stm32wbxx_hal_usart.h.

#define USART_CR_POS 5U

USART control register position

Definition at line 415 of file stm32wbxx_hal_usart.h.

#define USART_IT_MASK 0x001FU

USART interruptions flags mask

Definition at line 413 of file stm32wbxx_hal_usart.h.

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: USART Exported Macros

Defines
USART Exported Macros
USART

Defines

#define | __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)
Reset USART handle state.
#define | __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified USART flag is set or not.
#define | __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified USART pending flag.
#define | __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)
Clear the USART PE pending flag.
#define | __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)
Clear the USART FE pending flag.
#define | __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)
Clear the USART NE pending flag.
#define | __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)
Clear the USART ORE pending flag.
#define | __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)
Clear the USART IDLE pending flag.
#define | __HAL_USART_CLEAR_TXFECF(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_TXFECF)
Clear the USART TX FIFO empty clear flag.
#define | __HAL_USART_CLEAR_UDRFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_UDRF)
Clear SPI slave underrun error flag.
#define | __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified USART interrupt.
#define | __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified USART interrupt.
#define | __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__INTERRUPT__)>> 0x08))) != RESET) ? SET : RESET)
Check whether the specified USART interrupt has occurred or not.
#define | __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified USART interrupt source is enabled or not.
#define | __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified USART ISR flag, in setting the proper ICR register flag.
#define | __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (__REQ__))
Set a specific USART request flag.
#define | __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the USART one bit sample method.
#define | __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
Disable the USART one bit sample method.
#define | __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable USART.
#define | __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable USART.

Define Documentation

#define __HAL_USART_CLEAR_FEFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)

Clear the USART FE pending flag.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 495 of file stm32wbxx_hal_usart.h.

#define __HAL_USART_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->ICR = (__FLAG__))

Clear the specified USART pending flag.

Parameters:
__HANDLE__ specifies the USART Handle.
__FLAG__ specifies the flag to check. This parameter can be any combination of the following values:
  • USART_CLEAR_PEF Parity Error Clear Flag
  • USART_CLEAR_FEF Framing Error Clear Flag
  • USART_CLEAR_NEF Noise detected Clear Flag
  • USART_CLEAR_OREF Overrun Error Clear Flag
  • USART_CLEAR_IDLEF IDLE line detected Clear Flag
  • USART_CLEAR_TXFECF TXFIFO empty clear Flag
  • USART_CLEAR_TCF Transmission Complete Clear Flag
  • USART_CLEAR_UDRF SPI slave underrun error Clear Flag
Return values:
None

Definition at line 483 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DMAResume(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive_DMA(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

#define __HAL_USART_CLEAR_IDLEFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)

Clear the USART IDLE pending flag.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 513 of file stm32wbxx_hal_usart.h.

#define __HAL_USART_CLEAR_IT | ( | __HANDLE__,
 |  | __IT_CLEAR__
 | ) | ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))

Clear the specified USART ISR flag, in setting the proper ICR register flag.

Parameters:
__HANDLE__ specifies the USART Handle.
__IT_CLEAR__ specifies the interrupt clear register flag that needs to be set to clear the corresponding interrupt. This parameter can be one of the following values:
  • USART_CLEAR_PEF Parity Error Clear Flag
  • USART_CLEAR_FEF Framing Error Clear Flag
  • USART_CLEAR_NEF Noise detected Clear Flag
  • USART_CLEAR_OREF Overrun Error Clear Flag
  • USART_CLEAR_IDLEF IDLE line detected Clear Flag
  • USART_CLEAR_TXFECF TXFIFO empty clear Flag
  • USART_CLEAR_TCF Transmission Complete Clear Flag
Return values:
None

Definition at line 633 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define __HAL_USART_CLEAR_NEFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)

Clear the USART NE pending flag.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 501 of file stm32wbxx_hal_usart.h.

#define __HAL_USART_CLEAR_OREFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)

Clear the USART ORE pending flag.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 507 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Transmit(), and USART_EndTransmit_IT().

#define __HAL_USART_CLEAR_PEFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)

Clear the USART PE pending flag.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 489 of file stm32wbxx_hal_usart.h.

#define __HAL_USART_CLEAR_TXFECF ( __HANDLE__ ) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_TXFECF)

Clear the USART TX FIFO empty clear flag.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 519 of file stm32wbxx_hal_usart.h.

#define __HAL_USART_CLEAR_UDRFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_UDRF)

Clear SPI slave underrun error flag.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 525 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_IRQHandler(), HAL_USART_Receive(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

#define __HAL_USART_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

Disable USART.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 668 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Init(), HAL_USARTEx_ConfigNSS(), HAL_USARTEx_DisableFifoMode(), HAL_USARTEx_DisableSlaveMode(), HAL_USARTEx_EnableFifoMode(), HAL_USARTEx_EnableSlaveMode(), HAL_USARTEx_SetRxFifoThreshold(), and HAL_USARTEx_SetTxFifoThreshold().

#define __HAL_USART_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
                                                            ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
                                                            ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))

Disable the specified USART interrupt.

Parameters:
__HANDLE__ specifies the USART Handle.
__INTERRUPT__ specifies the USART interrupt source to disable. This parameter can be one of the following values:
  • USART_IT_RXFF RXFIFO Full interrupt
  • USART_IT_TXFE TXFIFO Empty interrupt
  • USART_IT_RXFT RXFIFO threshold interrupt
  • USART_IT_TXFT TXFIFO threshold interrupt
  • USART_IT_TXE Transmit Data Register empty interrupt
  • USART_IT_TXFNF TX FIFO not full interrupt
  • USART_IT_TC Transmission complete interrupt
  • USART_IT_RXNE Receive Data register not empty interrupt
  • USART_IT_RXFNE RXFIFO not empty interrupt
  • USART_IT_IDLE Idle line detection interrupt
  • USART_IT_PE Parity Error interrupt
  • USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
Return values:
None

Definition at line 567 of file stm32wbxx_hal_usart.h.

Referenced by USART_EndTransmit_IT(), USART_TxISR_16BIT(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT(), and USART_TxISR_8BIT_FIFOEN().

#define __HAL_USART_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

Enable USART.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 662 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Init(), and HAL_USARTEx_EnableSlaveMode().

#define __HAL_USART_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
                                                            ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
                                                            ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))

Enable the specified USART interrupt.

Parameters:
__HANDLE__ specifies the USART Handle.
__INTERRUPT__ specifies the USART interrupt source to enable. This parameter can be one of the following values:
  • USART_IT_RXFF RXFIFO Full interrupt
  • USART_IT_TXFE TXFIFO Empty interrupt
  • USART_IT_RXFT RXFIFO threshold interrupt
  • USART_IT_TXFT TXFIFO threshold interrupt
  • USART_IT_TXE Transmit Data Register empty interrupt
  • USART_IT_TXFNF TX FIFO not full interrupt
  • USART_IT_TC Transmission complete interrupt
  • USART_IT_RXNE Receive Data register not empty interrupt
  • USART_IT_RXFNE RXFIFO not empty interrupt
  • USART_IT_IDLE Idle line detection interrupt
  • USART_IT_PE Parity Error interrupt
  • USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
Return values:
None

Definition at line 545 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Transmit_IT(), USART_DMATransmitCplt(), USART_TxISR_16BIT(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT(), and USART_TxISR_8BIT_FIFOEN().

#define __HAL_USART_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))

Check whether the specified USART flag is set or not.

Parameters:
__HANDLE__ specifies the USART Handle
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • USART_FLAG_TXFT TXFIFO threshold flag
  • USART_FLAG_RXFT RXFIFO threshold flag
  • USART_FLAG_RXFF RXFIFO Full flag
  • USART_FLAG_TXFE TXFIFO Empty flag
  • USART_FLAG_REACK Receive enable acknowledge flag
  • USART_FLAG_TEACK Transmit enable acknowledge flag
  • USART_FLAG_BUSY Busy flag
  • USART_FLAG_UDR SPI slave underrun error flag
  • USART_FLAG_TXE Transmit data register empty flag
  • USART_FLAG_TXFNF TXFIFO not full flag
  • USART_FLAG_TC Transmission Complete flag
  • USART_FLAG_RXNE Receive data register not empty flag
  • USART_FLAG_RXFNE RXFIFO not empty flag
  • USART_FLAG_IDLE Idle Line detection flag
  • USART_FLAG_ORE OverRun Error flag
  • USART_FLAG_NE Noise Error flag
  • USART_FLAG_FE Framing Error flag
  • USART_FLAG_PE Parity Error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 467 of file stm32wbxx_hal_usart.h.

Referenced by USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT_FIFOEN(), USART_TxISR_16BIT_FIFOEN(), USART_TxISR_8BIT_FIFOEN(), and USART_WaitOnFlagUntilTimeout().

#define __HAL_USART_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__INTERRUPT__)>> 0x08))) != RESET) ? SET : RESET)

Check whether the specified USART interrupt has occurred or not.

Parameters:
__HANDLE__ specifies the USART Handle.
__INTERRUPT__ specifies the USART interrupt source to check. This parameter can be one of the following values:
  • USART_IT_RXFF RXFIFO Full interrupt
  • USART_IT_TXFE TXFIFO Empty interrupt
  • USART_IT_RXFT RXFIFO threshold interrupt
  • USART_IT_TXFT TXFIFO threshold interrupt
  • USART_IT_TXE Transmit Data Register empty interrupt
  • USART_IT_TXFNF TX FIFO not full interrupt
  • USART_IT_TC Transmission complete interrupt
  • USART_IT_RXNE Receive Data register not empty interrupt
  • USART_IT_RXFNE RXFIFO not empty interrupt
  • USART_IT_IDLE Idle line detection interrupt
  • USART_IT_ORE OverRun Error interrupt
  • USART_IT_NE Noise Error interrupt
  • USART_IT_FE Framing Error interrupt
  • USART_IT_PE Parity Error interrupt
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 592 of file stm32wbxx_hal_usart.h.

#define __HAL_USART_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ? (__HANDLE__)->Instance->CR1 : \
                                                                (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \
                                                                (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK)))  != RESET) ? SET : RESET)

Check whether the specified USART interrupt source is enabled or not.

Parameters:
__HANDLE__ specifies the USART Handle.
__INTERRUPT__ specifies the USART interrupt source to check. This parameter can be one of the following values:
  • USART_IT_RXFF RXFIFO Full interrupt
  • USART_IT_TXFE TXFIFO Empty interrupt
  • USART_IT_RXFT RXFIFO threshold interrupt
  • USART_IT_TXFT TXFIFO threshold interrupt
  • USART_IT_TXE Transmit Data Register empty interrupt
  • USART_IT_TXFNF TX FIFO not full interrupt
  • USART_IT_TC Transmission complete interrupt
  • USART_IT_RXNE Receive Data register not empty interrupt
  • USART_IT_RXFNE RXFIFO not empty interrupt
  • USART_IT_IDLE Idle line detection interrupt
  • USART_IT_ORE OverRun Error interrupt
  • USART_IT_NE Noise Error interrupt
  • USART_IT_FE Framing Error interrupt
  • USART_IT_PE Parity Error interrupt
Return values:
The new state of __INTERRUPT__ (SET or RESET).

Definition at line 614 of file stm32wbxx_hal_usart.h.

#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)

Disable the USART one bit sample method.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 656 of file stm32wbxx_hal_usart.h.

#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)

Enable the USART one bit sample method.

Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None

Definition at line 650 of file stm32wbxx_hal_usart.h.

#define __HAL_USART_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                            \
                                                      (__HANDLE__)->State = HAL_USART_STATE_RESET; \
                                                      (__HANDLE__)->MspInitCallback = NULL;        \
                                                      (__HANDLE__)->MspDeInitCallback = NULL;      \
                                                    } while(0U)

Reset USART handle state.

Parameters:
__HANDLE__ USART handle.
Return values:
None

Definition at line 434 of file stm32wbxx_hal_usart.h.

#define __HAL_USART_SEND_REQ | ( | __HANDLE__,
 |  | __REQ__
 | ) | ((__HANDLE__)->Instance->RQR |= (__REQ__))

Set a specific USART request flag.

Parameters:
__HANDLE__ specifies the USART Handle.
__REQ__ specifies the request flag to set. This parameter can be one of the following values:
  • USART_RXDATA_FLUSH_REQUEST Receive Data flush Request
  • USART_TXDATA_FLUSH_REQUEST Transmit data flush Request
Return values:
None

Definition at line 644 of file stm32wbxx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_Receive(), HAL_USART_Transmit(), USART_EndTransmit_IT(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: USART Private Macros

Defines
USART Private Macros
USART

Defines

#define | USART_GET_DIV_FACTOR(__CLOCKPRESCALER__)
Get USART clock division factor from clock prescaler value.
#define | USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U) + ((__BAUD__)/2U)) / (__BAUD__))
BRR division operation to set BRR register in 8-bit oversampling mode.
#define | USART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the USART clock source.
#define | IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 8000000U)
Check USART Baud rate.
#define | IS_USART_STOPBITS(__STOPBITS__)
Ensure that USART frame number of stop bits is valid.
#define | IS_USART_PARITY(__PARITY__)
Ensure that USART frame parity is valid.
#define | IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
Ensure that USART communication mode is valid.
#define | IS_USART_OVERSAMPLING(__SAMPLING__)
Ensure that USART oversampling is valid.
#define | IS_USART_CLOCK(__CLOCK__)
Ensure that USART clock state is valid.
#define | IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
Ensure that USART frame polarity is valid.
#define | IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
Ensure that USART frame phase is valid.
#define | IS_USART_LASTBIT(__LASTBIT__)
Ensure that USART frame last bit clock pulse setting is valid.
#define | IS_USART_REQUEST_PARAMETER(__PARAM__)
Ensure that USART request parameter is valid.
#define | IS_USART_PRESCALER(__CLOCKPRESCALER__)
Ensure that USART Prescaler is valid.

Define Documentation

#define IS_USART_BAUDRATE ( __BAUDRATE__ ) ((__BAUDRATE__) <= 8000000U)

Check USART Baud rate.

Parameters:
__BAUDRATE__ Baudrate specified by the user. The maximum Baud Rate is derived from the maximum clock on WB (i.e. 64 MHz) divided by the smallest oversampling used on the USART (i.e. 8)
Return values:
SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)

Definition at line 744 of file stm32wbxx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_CLOCK ( __CLOCK__ )
Value:
(((__CLOCK__) == USART_CLOCK_DISABLE) || \
                                   ((__CLOCK__) == USART_CLOCK_ENABLE))

Ensure that USART clock state is valid.

Parameters:
__CLOCK__ USART clock state.
Return values:
SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)

Definition at line 785 of file stm32wbxx_hal_usart.h.

#define IS_USART_LASTBIT ( __LASTBIT__ )
Value:
(((__LASTBIT__) == USART_LASTBIT_DISABLE) || \
                                       ((__LASTBIT__) == USART_LASTBIT_ENABLE))

Ensure that USART frame last bit clock pulse setting is valid.

Parameters:
__LASTBIT__ USART frame last bit clock pulse setting.
Return values:
SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)

Definition at line 807 of file stm32wbxx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_MODE ( __MODE__ ) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))

Ensure that USART communication mode is valid.

Parameters:
__MODE__ USART communication mode.
Return values:
SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

Definition at line 770 of file stm32wbxx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_OVERSAMPLING ( __SAMPLING__ )
Value:
(((__SAMPLING__) == USART_OVERSAMPLING_16) || \
                                             ((__SAMPLING__) == USART_OVERSAMPLING_8))

Ensure that USART oversampling is valid.

Parameters:
__SAMPLING__ USART oversampling.
Return values:
SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)

Definition at line 777 of file stm32wbxx_hal_usart.h.

#define IS_USART_PARITY ( __PARITY__ )
Value:
(((__PARITY__) == USART_PARITY_NONE) || \
                                     ((__PARITY__) == USART_PARITY_EVEN) || \
                                     ((__PARITY__) == USART_PARITY_ODD))

Ensure that USART frame parity is valid.

Parameters:
__PARITY__ USART frame parity.
Return values:
SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)

Definition at line 761 of file stm32wbxx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_PHASE ( __CPHA__ ) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))

Ensure that USART frame phase is valid.

Parameters:
__CPHA__ USART frame phase.
Return values:
SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)

Definition at line 800 of file stm32wbxx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_POLARITY ( __CPOL__ ) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))

Ensure that USART frame polarity is valid.

Parameters:
__CPOL__ USART frame polarity.
Return values:
SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)

Definition at line 793 of file stm32wbxx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_PRESCALER ( __CLOCKPRESCALER__ )
Value:
(((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) || \
                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256))

Ensure that USART Prescaler is valid.

Parameters:
__CLOCKPRESCALER__ USART Prescaler value.
Return values:
SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)

Definition at line 823 of file stm32wbxx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_REQUEST_PARAMETER ( __PARAM__ )
Value:
(((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \
                                               ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))

Ensure that USART request parameter is valid.

Parameters:
__PARAM__ USART request parameter.
Return values:
SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)

Definition at line 815 of file stm32wbxx_hal_usart.h.

#define IS_USART_STOPBITS ( __STOPBITS__ )
Value:
(((__STOPBITS__) == USART_STOPBITS_0_5) || \
                                         ((__STOPBITS__) == USART_STOPBITS_1)   || \
                                         ((__STOPBITS__) == USART_STOPBITS_1_5) || \
                                         ((__STOPBITS__) == USART_STOPBITS_2))

Ensure that USART frame number of stop bits is valid.

Parameters:
__STOPBITS__ USART frame number of stop bits.
Return values:
SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)

Definition at line 751 of file stm32wbxx_hal_usart.h.

Referenced by USART_SetConfig().

#define USART_DIV_SAMPLING8 | ( | __PCLK__,
 |  | __BAUD__,
 |  | __CLOCKPRESCALER__
 | ) | (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U) + ((__BAUD__)/2U)) / (__BAUD__))

BRR division operation to set BRR register in 8-bit oversampling mode.

Parameters:
__PCLK__ | USART clock.
__BAUD__ | Baud rate set by the user.
__CLOCKPRESCALER__ | UART prescaler value.
Return values:
Division result

Definition at line 703 of file stm32wbxx_hal_usart.h.

Referenced by USART_SetConfig().

#define USART_GET_DIV_FACTOR ( __CLOCKPRESCALER__ )
Value:
(((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1)   ? 1U :       \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2)   ? 2U :       \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4)   ? 4U :       \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6)   ? 6U :       \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8)   ? 8U :       \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10)  ? 10U :      \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12)  ? 12U :      \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16)  ? 16U :      \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32)  ? 32U :      \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64)  ? 64U :      \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U :     \
   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256) ? 256U : 1U)

Get USART clock division factor from clock prescaler value.

Parameters:
__CLOCKPRESCALER__ USART prescaler value.
Return values:
USART clock division factor

Definition at line 683 of file stm32wbxx_hal_usart.h.

#define USART_GETCLOCKSOURCE | ( | __HANDLE__,
 |  | __CLOCKSOURCE__
 | ) |
Value:
do {                                                         \
    if((__HANDLE__)->Instance == USART1)                       \
    {                                                          \
       switch(__HAL_RCC_GET_USART1_SOURCE())                   \
       {                                                       \
        case RCC_USART1CLKSOURCE_PCLK2:                        \
          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2;         \
          break;                                               \
        case RCC_USART1CLKSOURCE_HSI:                          \
          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
          break;                                               \
        case RCC_USART1CLKSOURCE_SYSCLK:                       \
          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
          break;                                               \
        case RCC_USART1CLKSOURCE_LSE:                          \
          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
          break;                                               \
        default:                                               \
          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
          break;                                               \
       }                                                       \
    }                                                       \
    else                                                       \
    {                                                          \
      (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;         \
    }                                                          \
  } while(0U)

Report the USART clock source.

Parameters:
__HANDLE__ | specifies the USART Handle.
__CLOCKSOURCE__ | output variable.
Return values:
the USART clocking source, written in __CLOCKSOURCE__.

Definition at line 710 of file stm32wbxx_hal_usart.h.

Referenced by USART_SetConfig().

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: USARTEx Private Functions

Functions
USARTEx Private Functions
USARTEx

Functions

static void USARTEx_SetNbDataToProcess (USART_HandleTypeDef *husart)
Calculate the number of data to process in RX/TX ISR.

Function Documentation

static void USARTEx_SetNbDataToProcess ( USART_HandleTypeDef * husart ) [static]

Calculate the number of data to process in RX/TX ISR.

Note:
The RX FIFO depth and the TX FIFO depth is extracted from the USART configuration registers.
Parameters:
husart USART handle.
Return values:
None

Definition at line 493 of file stm32wbxx_hal_usart_ex.c.

References __USART_HandleTypeDef::FifoMode, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::NbRxDataToProcess, __USART_HandleTypeDef::NbTxDataToProcess, RX_FIFO_DEPTH, TX_FIFO_DEPTH, and USART_FIFOMODE_DISABLE.

Referenced by HAL_USARTEx_EnableFifoMode(), HAL_USARTEx_SetRxFifoThreshold(), and HAL_USARTEx_SetTxFifoThreshold().

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IO operation functions

Functions
IO operation functions
USARTEx Exported Functions

Extended USART Transmit/Receive functions. More...

Functions

__weak void | HAL_USARTEx_RxFifoFullCallback (USART_HandleTypeDef *husart)
USART RX Fifo full callback.
__weak void | HAL_USARTEx_TxFifoEmptyCallback (USART_HandleTypeDef *husart)
USART TX Fifo empty callback.

Detailed Description

Extended USART Transmit/Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    This subsection provides a set of FIFO mode related callback functions.

    (#) TX/RX Fifos Callbacks:
        (+) HAL_USARTEx_RxFifoFullCallback()
        (+) HAL_USARTEx_TxFifoEmptyCallback()

Function Documentation

void HAL_USARTEx_RxFifoFullCallback ( USART_HandleTypeDef * husart )

USART RX Fifo full callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 103 of file stm32wbxx_hal_usart_ex.c.

Referenced by HAL_USART_IRQHandler(), HAL_USART_UnRegisterCallback(), and USART_InitCallbacksToDefault().

void HAL_USARTEx_TxFifoEmptyCallback ( USART_HandleTypeDef * husart )

USART TX Fifo empty callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 118 of file stm32wbxx_hal_usart_ex.c.

Referenced by HAL_USART_IRQHandler(), HAL_USART_UnRegisterCallback(), and USART_InitCallbacksToDefault().

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
USARTEx Exported Functions

Extended Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_USARTEx_EnableSlaveMode (USART_HandleTypeDef *husart)
Enable the SPI slave mode.
HAL_StatusTypeDef | HAL_USARTEx_DisableSlaveMode (USART_HandleTypeDef *husart)
Disable the SPI slave mode.
HAL_StatusTypeDef | HAL_USARTEx_ConfigNSS (USART_HandleTypeDef *husart, uint32_t NSSConfig)
Configure the Slave Select input pin (NSS).
HAL_StatusTypeDef | HAL_USARTEx_EnableFifoMode (USART_HandleTypeDef *husart)
Enable the FIFO mode.
HAL_StatusTypeDef | HAL_USARTEx_DisableFifoMode (USART_HandleTypeDef *husart)
Disable the FIFO mode.
HAL_StatusTypeDef | HAL_USARTEx_SetTxFifoThreshold (USART_HandleTypeDef *husart, uint32_t Threshold)
Set the TXFIFO threshold.
HAL_StatusTypeDef | HAL_USARTEx_SetRxFifoThreshold (USART_HandleTypeDef *husart, uint32_t Threshold)
Set the RXFIFO threshold.

Detailed Description

Extended Peripheral Control functions.

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..] This section provides the following functions:
     (+) HAL_USARTEx_EnableSPISlaveMode() API enables the SPI slave mode
     (+) HAL_USARTEx_DisableSPISlaveMode() API disables the SPI slave mode
     (+) HAL_USARTEx_ConfigNSS API configures the Slave Select input pin (NSS)
     (+) HAL_USARTEx_EnableFifoMode() API enables the FIFO mode
     (+) HAL_USARTEx_DisableFifoMode() API disables the FIFO mode
     (+) HAL_USARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
     (+) HAL_USARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold

Function Documentation

HAL_StatusTypeDef HAL_USARTEx_ConfigNSS | ( | USART_HandleTypeDef * | husart,
 |  | uint32_t | NSSConfig
 | ) |  |

Configure the Slave Select input pin (NSS).

Note:
Software NSS management: SPI slave will always be selected and NSS input pin will be ignored.
Hardware NSS management: the SPI slave selection depends on NSS input pin. The slave is selected when NSS is low and deselected when NSS is high.
Parameters:
husart USART handle.
NSSConfig NSS configuration. This parameter can be one of the following values:
  • USART_NSS_HARD
  • USART_NSS_SOFT
Return values:
HAL status

Definition at line 264 of file stm32wbxx_hal_usart_ex.c.

References __HAL_USART_DISABLE, assert_param, HAL_USART_STATE_BUSY, HAL_USART_STATE_READY, __USART_HandleTypeDef::Instance, IS_USART_NSS, and __USART_HandleTypeDef::State.

HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode ( USART_HandleTypeDef * husart )

Disable the FIFO mode.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 343 of file stm32wbxx_hal_usart_ex.c.

References __HAL_USART_DISABLE, assert_param, __USART_HandleTypeDef::FifoMode, HAL_USART_STATE_BUSY, HAL_USART_STATE_READY, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::State, and USART_FIFOMODE_DISABLE.

HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode ( USART_HandleTypeDef * husart )

Disable the SPI slave mode.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 216 of file stm32wbxx_hal_usart_ex.c.

References __HAL_USART_DISABLE, assert_param, HAL_USART_STATE_BUSY, HAL_USART_STATE_READY, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, and USART_SLAVEMODE_ENABLE.

HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode ( USART_HandleTypeDef * husart )

Enable the FIFO mode.

Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 302 of file stm32wbxx_hal_usart_ex.c.

References __HAL_USART_DISABLE, assert_param, __USART_HandleTypeDef::FifoMode, HAL_USART_STATE_BUSY, HAL_USART_STATE_READY, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::State, USART_FIFOMODE_ENABLE, and USARTEx_SetNbDataToProcess().

HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode ( USART_HandleTypeDef * husart )

Enable the SPI slave mode.

Note:
When the USART operates in SPI slave mode, it handles data flow using the serial interface clock derived from the external SCLK signal provided by the external master SPI device.
In SPI slave mode, the USART must be enabled before starting the master communications (or between frames while the clock is stable). Otherwise, if the USART slave is enabled while the master is in the middle of a frame, it will become desynchronized with the master.
The data register of the slave needs to be ready before the first edge of the communication clock or before the end of the ongoing communication, otherwise the SPI slave will transmit zeros.
Parameters:
husart USART handle.
Return values:
HAL status

Definition at line 168 of file stm32wbxx_hal_usart_ex.c.

References __HAL_USART_DISABLE, __HAL_USART_ENABLE, assert_param, HAL_USART_STATE_BUSY, HAL_USART_STATE_READY, __USART_HandleTypeDef::Instance, __USART_HandleTypeDef::SlaveMode, __USART_HandleTypeDef::State, and USART_SLAVEMODE_ENABLE.

HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold | ( | USART_HandleTypeDef * | husart,
 |  | uint32_t | Threshold
 | ) |  |

Set the RXFIFO threshold.

Parameters:
husart USART handle.
Threshold RX FIFO threshold value This parameter can be one of the following values:
  • USART_RXFIFO_THRESHOLD_1_8
  • USART_RXFIFO_THRESHOLD_1_4
  • USART_RXFIFO_THRESHOLD_1_2
  • USART_RXFIFO_THRESHOLD_3_4
  • USART_RXFIFO_THRESHOLD_7_8
  • USART_RXFIFO_THRESHOLD_8_8
Return values:
HAL status

Definition at line 438 of file stm32wbxx_hal_usart_ex.c.

References __HAL_USART_DISABLE, assert_param, HAL_USART_STATE_BUSY, HAL_USART_STATE_READY, __USART_HandleTypeDef::Instance, IS_USART_RXFIFO_THRESHOLD, __USART_HandleTypeDef::State, and USARTEx_SetNbDataToProcess().

HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold | ( | USART_HandleTypeDef * | husart,
 |  | uint32_t | Threshold
 | ) |  |

Set the TXFIFO threshold.

Parameters:
husart USART handle.
Threshold TX FIFO threshold value This parameter can be one of the following values:
  • USART_TXFIFO_THRESHOLD_1_8
  • USART_TXFIFO_THRESHOLD_1_4
  • USART_TXFIFO_THRESHOLD_1_2
  • USART_TXFIFO_THRESHOLD_3_4
  • USART_TXFIFO_THRESHOLD_7_8
  • USART_TXFIFO_THRESHOLD_8_8
Return values:
HAL status

Definition at line 389 of file stm32wbxx_hal_usart_ex.c.

References __HAL_USART_DISABLE, assert_param, HAL_USART_STATE_BUSY, HAL_USART_STATE_READY, __USART_HandleTypeDef::Instance, IS_USART_TXFIFO_THRESHOLD, __USART_HandleTypeDef::State, and USARTEx_SetNbDataToProcess().

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: USARTEx Word Length

Defines
USARTEx Word Length
USARTEx Exported Constants

Defines

#define | USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)
#define | USART_WORDLENGTH_8B 0x00000000U
#define | USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)

Define Documentation

#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)

7-bit long USART frame

Definition at line 48 of file stm32wbxx_hal_usart_ex.h.

#define USART_WORDLENGTH_8B 0x00000000U

8-bit long USART frame

Definition at line 49 of file stm32wbxx_hal_usart_ex.h.

#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)

9-bit long USART frame

Definition at line 50 of file stm32wbxx_hal_usart_ex.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), and HAL_USART_TransmitReceive_IT().

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: USARTEx Slave Select Management

Defines
USARTEx Slave Select Management
USARTEx Exported Constants

Defines

#define | USART_NSS_HARD 0x00000000U
#define | USART_NSS_SOFT USART_CR2_DIS_NSS

Define Documentation

#define USART_NSS_HARD 0x00000000U

SPI slave selection depends on NSS input pin

Definition at line 58 of file stm32wbxx_hal_usart_ex.h.

#define USART_NSS_SOFT USART_CR2_DIS_NSS

SPI slave is always selected and NSS input pin is ignored

Definition at line 59 of file stm32wbxx_hal_usart_ex.h.

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STM32WB55xx HAL User Manual: USARTEx Synchronous Slave mode enable

Defines
USARTEx Synchronous Slave mode enable
USARTEx Exported Constants

USART SLAVE mode. More...

Defines

#define | USART_SLAVEMODE_DISABLE 0x00000000U
#define | USART_SLAVEMODE_ENABLE USART_CR2_SLVEN

Detailed Description

USART SLAVE mode.

Define Documentation

#define USART_SLAVEMODE_DISABLE 0x00000000U

USART SPI Slave Mode Enable

Definition at line 69 of file stm32wbxx_hal_usart_ex.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

#define USART_SLAVEMODE_ENABLE USART_CR2_SLVEN

USART SPI Slave Mode Disable

Definition at line 70 of file stm32wbxx_hal_usart_ex.h.

Referenced by HAL_USART_Receive(), HAL_USART_TransmitReceive(), HAL_USARTEx_DisableSlaveMode(), HAL_USARTEx_EnableSlaveMode(), USART_RxISR_16BIT(), USART_RxISR_16BIT_FIFOEN(), USART_RxISR_8BIT(), and USART_RxISR_8BIT_FIFOEN().

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: USARTEx FIFO mode

Defines
USARTEx FIFO mode
USARTEx Exported Constants

USART FIFO mode. More...

Defines

#define | USART_FIFOMODE_DISABLE 0x00000000U
#define | USART_FIFOMODE_ENABLE USART_CR1_FIFOEN

Detailed Description

USART FIFO mode.

Define Documentation

#define USART_FIFOMODE_DISABLE 0x00000000U

FIFO mode disable

Definition at line 79 of file stm32wbxx_hal_usart_ex.h.

Referenced by HAL_USARTEx_DisableFifoMode(), and USARTEx_SetNbDataToProcess().

#define USART_FIFOMODE_ENABLE USART_CR1_FIFOEN

FIFO mode enable

Definition at line 80 of file stm32wbxx_hal_usart_ex.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_Receive_IT(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive_IT(), and HAL_USARTEx_EnableFifoMode().

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: USARTEx TXFIFO threshold level

Defines
USARTEx TXFIFO threshold level
USARTEx Exported Constants

USART TXFIFO level. More...

Defines

#define | USART_TXFIFO_THRESHOLD_1_8 0x00000000U
#define | USART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0
#define | USART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1
#define | USART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)
#define | USART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2
#define | USART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)

Detailed Description

USART TXFIFO level.

Define Documentation

#define USART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1

TXFIFO reaches 1/2 of its depth

Definition at line 91 of file stm32wbxx_hal_usart_ex.h.

#define USART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0

TXFIFO reaches 1/4 of its depth

Definition at line 90 of file stm32wbxx_hal_usart_ex.h.

#define USART_TXFIFO_THRESHOLD_1_8 0x00000000U

TXFIFO reaches 1/8 of its depth

Definition at line 89 of file stm32wbxx_hal_usart_ex.h.

#define USART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)

TXFIFO reaches 3/4 of its depth

Definition at line 92 of file stm32wbxx_hal_usart_ex.h.

#define USART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2

TXFIFO reaches 7/8 of its depth

Definition at line 93 of file stm32wbxx_hal_usart_ex.h.

#define USART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)

TXFIFO becomes empty

Definition at line 94 of file stm32wbxx_hal_usart_ex.h.

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: USARTEx RXFIFO threshold level

Defines
USARTEx RXFIFO threshold level
USARTEx Exported Constants

USART RXFIFO level. More...

Defines

#define | USART_RXFIFO_THRESHOLD_1_8 0x00000000U
#define | USART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0
#define | USART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1
#define | USART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)
#define | USART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2
#define | USART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)

Detailed Description

USART RXFIFO level.

Define Documentation

#define USART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1

RXFIFO FIFO reaches 1/2 of its depth

Definition at line 105 of file stm32wbxx_hal_usart_ex.h.

#define USART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0

RXFIFO FIFO reaches 1/4 of its depth

Definition at line 104 of file stm32wbxx_hal_usart_ex.h.

#define USART_RXFIFO_THRESHOLD_1_8 0x00000000U

RXFIFO FIFO reaches 1/8 of its depth

Definition at line 103 of file stm32wbxx_hal_usart_ex.h.

#define USART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)

RXFIFO FIFO reaches 3/4 of its depth

Definition at line 106 of file stm32wbxx_hal_usart_ex.h.

#define USART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2

RXFIFO FIFO reaches 7/8 of its depth

Definition at line 107 of file stm32wbxx_hal_usart_ex.h.

#define USART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)

RXFIFO FIFO becomes full

Definition at line 108 of file stm32wbxx_hal_usart_ex.h.

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STM32WB55xx HAL User Manual: USARTEx Private Macros

Defines
USARTEx Private Macros
USARTEx

Defines

#define | USART_MASK_COMPUTATION(__HANDLE__)
Compute the USART mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_USART_WORD_LENGTH(__LENGTH__)
Ensure that USART frame length is valid.
#define | IS_USART_NSS(__NSS__)
Ensure that USART Negative Slave Select (NSS) pin management is valid.
#define | IS_USART_SLAVEMODE(__STATE__)
Ensure that USART Slave Mode is valid.
#define | IS_USART_FIFO_MODE_STATE(__STATE__)
Ensure that USART FIFO mode is valid.
#define | IS_USART_TXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that USART TXFIFO threshold level is valid.
#define | IS_USART_RXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that USART RXFIFO threshold level is valid.

Define Documentation

#define IS_USART_FIFO_MODE_STATE ( __STATE__ )
Value:
(((__STATE__) == USART_FIFOMODE_DISABLE ) || \
                                             ((__STATE__) == USART_FIFOMODE_ENABLE))

Ensure that USART FIFO mode is valid.

Parameters:
__STATE__ USART FIFO mode.
Return values:
SET (__STATE__ is valid) or RESET (__STATE__ is invalid)

Definition at line 203 of file stm32wbxx_hal_usart_ex.h.

#define IS_USART_NSS ( __NSS__ )
Value:
(((__NSS__) == USART_NSS_HARD) || \
                               ((__NSS__) == USART_NSS_SOFT))

Ensure that USART Negative Slave Select (NSS) pin management is valid.

Parameters:
__NSS__ USART Negative Slave Select pin management.
Return values:
SET (__NSS__ is valid) or RESET (__NSS__ is invalid)

Definition at line 187 of file stm32wbxx_hal_usart_ex.h.

Referenced by HAL_USARTEx_ConfigNSS().

#define IS_USART_RXFIFO_THRESHOLD ( __THRESHOLD__ )
Value:
(((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_8)  || \
                                                   ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_4)  || \
                                                   ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_2)  || \
                                                   ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_3_4)  || \
                                                   ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_7_8)  || \
                                                   ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_8_8))

Ensure that USART RXFIFO threshold level is valid.

Parameters:
__THRESHOLD__ USART RXFIFO threshold level.
Return values:
SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)

Definition at line 223 of file stm32wbxx_hal_usart_ex.h.

Referenced by HAL_USARTEx_SetRxFifoThreshold().

#define IS_USART_SLAVEMODE ( __STATE__ )
Value:
(((__STATE__) == USART_SLAVEMODE_DISABLE ) || \
                                         ((__STATE__) == USART_SLAVEMODE_ENABLE))

Ensure that USART Slave Mode is valid.

Parameters:
__STATE__ USART Slave Mode.
Return values:
SET (__STATE__ is valid) or RESET (__STATE__ is invalid)

Definition at line 195 of file stm32wbxx_hal_usart_ex.h.

#define IS_USART_TXFIFO_THRESHOLD ( __THRESHOLD__ )
Value:
(((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_8)  || \
                                                   ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_4)  || \
                                                   ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_2)  || \
                                                   ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_3_4)  || \
                                                   ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_7_8)  || \
                                                   ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_8_8))

Ensure that USART TXFIFO threshold level is valid.

Parameters:
__THRESHOLD__ USART TXFIFO threshold level.
Return values:
SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)

Definition at line 211 of file stm32wbxx_hal_usart_ex.h.

Referenced by HAL_USARTEx_SetTxFifoThreshold().

#define IS_USART_WORD_LENGTH ( __LENGTH__ )
Value:
(((__LENGTH__) == USART_WORDLENGTH_7B) || \
                                          ((__LENGTH__) == USART_WORDLENGTH_8B) || \
                                          ((__LENGTH__) == USART_WORDLENGTH_9B))

Ensure that USART frame length is valid.

Parameters:
__LENGTH__ USART frame length.
Return values:
SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

Definition at line 178 of file stm32wbxx_hal_usart_ex.h.

Referenced by USART_SetConfig().

#define USART_MASK_COMPUTATION ( __HANDLE__ )

Compute the USART mask to apply to retrieve the received data according to the word length and to the parity bits activation.

Note:
If PCE = 1, the parity bit is not included in the data extracted by the reception API(). This masking operation is not carried out in the case of DMA transfers.
Parameters:
__HANDLE__ specifies the USART Handle.
Return values:
None,the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field.

Definition at line 131 of file stm32wbxx_hal_usart_ex.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive(), and HAL_USART_TransmitReceive_IT().

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STM32WB55xx HAL User Manual: USARTEx

Modules | Defines
USARTEx
STM32WBxx_HAL_Driver

USART Extended HAL module driver. More...

Modules

USARTEx Private Functions
USARTEx Exported Functions
USARTEx Exported Constants
USARTEx Private Macros

Defines

#define | RX_FIFO_DEPTH 8U
#define | TX_FIFO_DEPTH 8U

Detailed Description

USART Extended HAL module driver.

Define Documentation

#define RX_FIFO_DEPTH 8U

Definition at line 58 of file stm32wbxx_hal_usart_ex.c.

Referenced by USARTEx_SetNbDataToProcess().

#define TX_FIFO_DEPTH 8U

Definition at line 61 of file stm32wbxx_hal_usart_ex.c.

Referenced by USARTEx_SetNbDataToProcess().

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STM32WB55xx HAL User Manual: Initialization and Configuration functions

Functions
Initialization and Configuration functions
WWDG Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_WWDG_Init (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG according to the specified.
__weak void | HAL_WWDG_MspInit (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG MSP.
HAL_StatusTypeDef | HAL_WWDG_RegisterCallback (WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback)
Register a User WWDG Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_WWDG_UnRegisterCallback (WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID)
Unregister a WWDG Callback WWDG Callback is redirected to the weak (surcharged) predefined callback.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
          ##### Initialization and Configuration functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
      (+) Initialize and start the WWDG according to the specified parameters
          in the WWDG_InitTypeDef of associated handle.
      (+) Initialize the WWDG MSP.

Function Documentation

HAL_StatusTypeDef HAL_WWDG_Init ( WWDG_HandleTypeDef * hwwdg )

Initialize the WWDG according to the specified.

parameters in the WWDG_InitTypeDef of associated handle.

Parameters:
hwwdg pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
HAL status

Definition at line 169 of file stm32wbxx_hal_wwdg.c.

References assert_param, WWDG_InitTypeDef::Counter, __WWDG_HandleTypeDef::EwiCallback, WWDG_InitTypeDef::EWIMode, HAL_WWDG_EarlyWakeupCallback(), HAL_WWDG_MspInit(), __WWDG_HandleTypeDef::Init, __WWDG_HandleTypeDef::Instance, IS_WWDG_COUNTER, IS_WWDG_EWI_MODE, IS_WWDG_PRESCALER, IS_WWDG_WINDOW, __WWDG_HandleTypeDef::MspInitCallback, WWDG_InitTypeDef::Prescaler, and WWDG_InitTypeDef::Window.

void HAL_WWDG_MspInit ( WWDG_HandleTypeDef * hwwdg )

Initialize the WWDG MSP.

Parameters:
hwwdg pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Note:
When rewriting this function in user file, mechanism may be added to avoid multiple initialize when HAL_WWDG_Init function is called again to change parameters.
Return values:
None

Definition at line 223 of file stm32wbxx_hal_wwdg.c.

Referenced by HAL_WWDG_Init(), and HAL_WWDG_UnRegisterCallback().

HAL_StatusTypeDef HAL_WWDG_RegisterCallback | ( | WWDG_HandleTypeDef * | hwwdg,
 |  | HAL_WWDG_CallbackIDTypeDef | CallbackID,
 |  | pWWDG_CallbackTypeDef | pCallback
 | ) |  |

Register a User WWDG Callback To be used instead of the weak (surcharged) predefined callback.

Parameters:
hwwdg | WWDG handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
  • HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
pCallback | pointer to the Callback function
Return values:
status

Definition at line 246 of file stm32wbxx_hal_wwdg.c.

References __WWDG_HandleTypeDef::EwiCallback, HAL_WWDG_EWI_CB_ID, HAL_WWDG_MSPINIT_CB_ID, and __WWDG_HandleTypeDef::MspInitCallback.

HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback | ( | WWDG_HandleTypeDef * | hwwdg,
 |  | HAL_WWDG_CallbackIDTypeDef | CallbackID
 | ) |  |

Unregister a WWDG Callback WWDG Callback is redirected to the weak (surcharged) predefined callback.

Parameters:
hwwdg WWDG handle
CallbackID ID of the callback to be registered This parameter can be one of the following values:
  • HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
  • HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
Return values:
status

Definition at line 286 of file stm32wbxx_hal_wwdg.c.

References __WWDG_HandleTypeDef::EwiCallback, HAL_WWDG_EarlyWakeupCallback(), HAL_WWDG_EWI_CB_ID, HAL_WWDG_MspInit(), HAL_WWDG_MSPINIT_CB_ID, and __WWDG_HandleTypeDef::MspInitCallback.

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: IO operation functions

Functions
IO operation functions
WWDG Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_WWDG_Refresh (WWDG_HandleTypeDef *hwwdg)
Refresh the WWDG.
void | HAL_WWDG_IRQHandler (WWDG_HandleTypeDef *hwwdg)
Handle WWDG interrupt request.
__weak void | HAL_WWDG_EarlyWakeupCallback (WWDG_HandleTypeDef *hwwdg)
WWDG Early Wakeup callback.

Detailed Description

IO operation functions.

  ==============================================================================
                      ##### IO operation functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Refresh the WWDG.
    (+) Handle WWDG interrupt request and associated function callback.

Function Documentation

void HAL_WWDG_EarlyWakeupCallback ( WWDG_HandleTypeDef * hwwdg )

WWDG Early Wakeup callback.

Parameters:
hwwdg pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
None

Definition at line 387 of file stm32wbxx_hal_wwdg.c.

Referenced by HAL_WWDG_Init(), HAL_WWDG_IRQHandler(), and HAL_WWDG_UnRegisterCallback().

void HAL_WWDG_IRQHandler ( WWDG_HandleTypeDef * hwwdg )

Handle WWDG interrupt request.

Note:
The Early Wakeup Interrupt (EWI) can be used if specific safety operations or data logging must be performed before the actual reset is generated. The EWI interrupt is enabled by calling HAL_WWDG_Init function with EWIMode set to WWDG_EWI_ENABLE. When the downcounter reaches the value 0x40, and EWI interrupt is generated and the corresponding Interrupt Service Routine (ISR) can be used to trigger specific actions (such as communications or data logging), before resetting the device.
Parameters:
hwwdg pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
None

Definition at line 358 of file stm32wbxx_hal_wwdg.c.

References __HAL_WWDG_CLEAR_FLAG, __HAL_WWDG_GET_FLAG, __HAL_WWDG_GET_IT_SOURCE, __WWDG_HandleTypeDef::EwiCallback, HAL_WWDG_EarlyWakeupCallback(), WWDG_FLAG_EWIF, and WWDG_IT_EWI.

HAL_StatusTypeDef HAL_WWDG_Refresh ( WWDG_HandleTypeDef * hwwdg )

Refresh the WWDG.

Parameters:
hwwdg pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
HAL status

Definition at line 335 of file stm32wbxx_hal_wwdg.c.

References WWDG_InitTypeDef::Counter, __WWDG_HandleTypeDef::Init, and __WWDG_HandleTypeDef::Instance.

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STM32WB55xx HAL User Manual: WWDG Exported Types

Data Structures | Typedefs | Enumerations
WWDG Exported Types
WWDG

Data Structures

struct | WWDG_InitTypeDef
WWDG Init structure definition. More...
struct | __WWDG_HandleTypeDef
WWDG handle Structure definition. More...

Typedefs

typedef struct __WWDG_HandleTypeDef | WWDG_HandleTypeDef
WWDG handle Structure definition.
typedef void(* | pWWDG_CallbackTypeDef )(WWDG_HandleTypeDef *hppp)
HAL WWDG Callback pointer definition.

Enumerations

enum | HAL_WWDG_CallbackIDTypeDef { HAL_WWDG_EWI_CB_ID = 0x00u, HAL_WWDG_MSPINIT_CB_ID = 0x01u }
HAL WWDG common Callback ID enumeration definition. More...

Typedef Documentation

typedef void(* pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp)

HAL WWDG Callback pointer definition.

pointer to a WWDG common callback functions

Definition at line 97 of file stm32wbxx_hal_wwdg.h.

typedef struct __WWDG_HandleTypeDef WWDG_HandleTypeDef

WWDG handle Structure definition.

Enumeration Type Documentation

enum HAL_WWDG_CallbackIDTypeDef

HAL WWDG common Callback ID enumeration definition.

Enumerator:
HAL_WWDG_EWI_CB_ID

WWDG EWI callback ID

HAL_WWDG_MSPINIT_CB_ID

WWDG MspInit callback ID

Definition at line 88 of file stm32wbxx_hal_wwdg.h.

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STM32WB55xx HAL User Manual: WWDG_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
WWDG_InitTypeDef Struct Reference
WWDG Exported Types

WWDG Init structure definition. More...

#include <stm32wbxx_hal_wwdg.h>

Data Fields

uint32_t | Prescaler
uint32_t | Window
uint32_t | Counter
uint32_t | EWIMode

Detailed Description

WWDG Init structure definition.

Definition at line 48 of file stm32wbxx_hal_wwdg.h.

Field Documentation

uint32_t WWDG_InitTypeDef::Counter

Specifies the WWDG free-running downcounter value. This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F

Definition at line 56 of file stm32wbxx_hal_wwdg.h.

Referenced by HAL_WWDG_Init(), and HAL_WWDG_Refresh().

uint32_t WWDG_InitTypeDef::EWIMode

Specifies if WWDG Early Wakeup Interupt is enable or not. This parameter can be a value of WWDG Early Wakeup Interrupt Mode

Definition at line 59 of file stm32wbxx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

uint32_t WWDG_InitTypeDef::Prescaler

Specifies the prescaler value of the WWDG. This parameter can be a value of WWDG Prescaler

Definition at line 50 of file stm32wbxx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

uint32_t WWDG_InitTypeDef::Window

Specifies the WWDG window value to be compared to the downcounter. This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F

Definition at line 53 of file stm32wbxx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_wwdg.h
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: __WWDG_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__WWDG_HandleTypeDef Struct Reference
WWDG Exported Types

WWDG handle Structure definition. More...

#include <stm32wbxx_hal_wwdg.h>

Data Fields

WWDG_TypeDef * | Instance
WWDG_InitTypeDef Init
void(* | EwiCallback )(struct __WWDG_HandleTypeDef *hwwdg)
void(* | MspInitCallback )(struct __WWDG_HandleTypeDef *hwwdg)

Detailed Description

WWDG handle Structure definition.

Definition at line 68 of file stm32wbxx_hal_wwdg.h.

Field Documentation

void(* __WWDG_HandleTypeDef::EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg)

WWDG Early WakeUp Interrupt callback

Definition at line 78 of file stm32wbxx_hal_wwdg.h.

Referenced by HAL_WWDG_Init(), HAL_WWDG_IRQHandler(), HAL_WWDG_RegisterCallback(), and HAL_WWDG_UnRegisterCallback().

WWDG_InitTypeDef __WWDG_HandleTypeDef::Init

WWDG required parameters

Definition at line 75 of file stm32wbxx_hal_wwdg.h.

Referenced by HAL_WWDG_Init(), and HAL_WWDG_Refresh().

WWDG_TypeDef* __WWDG_HandleTypeDef::Instance

Register base address

Definition at line 73 of file stm32wbxx_hal_wwdg.h.

Referenced by HAL_WWDG_Init(), and HAL_WWDG_Refresh().

void(* __WWDG_HandleTypeDef::MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg)

WWDG Msp Init callback

Definition at line 80 of file stm32wbxx_hal_wwdg.h.

Referenced by HAL_WWDG_Init(), HAL_WWDG_RegisterCallback(), and HAL_WWDG_UnRegisterCallback().

The documentation for this struct was generated from the following file:
  • stm32wbxx_hal_wwdg.h
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: WWDG Interrupt definition

Defines
WWDG Interrupt definition
WWDG Exported Constants

Defines

#define WWDG_IT_EWI WWDG_CFR_EWI

Define Documentation

#define WWDG_IT_EWI WWDG_CFR_EWI

Early wakeup interrupt

Definition at line 113 of file stm32wbxx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: WWDG Flag definition

Defines
WWDG Flag definition
WWDG Exported Constants

WWDG Flag definition. More...

Defines

#define WWDG_FLAG_EWIF WWDG_SR_EWIF

Detailed Description

WWDG Flag definition.

Define Documentation

#define WWDG_FLAG_EWIF WWDG_SR_EWIF

Early wakeup interrupt flag

Definition at line 122 of file stm32wbxx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: WWDG Prescaler

Defines
WWDG Prescaler
WWDG Exported Constants

Defines

#define | WWDG_PRESCALER_1 0x00000000u
#define | WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0
#define | WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1
#define | WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)
#define | WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2
#define | WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0)
#define | WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1)
#define | WWDG_PRESCALER_128 WWDG_CFR_WDGTB

Define Documentation

#define WWDG_PRESCALER_1 0x00000000u

WWDG counter clock = (PCLK1/4096)/1

Definition at line 130 of file stm32wbxx_hal_wwdg.h.

#define WWDG_PRESCALER_128 WWDG_CFR_WDGTB

WWDG counter clock = (PCLK1/4096)/128

Definition at line 137 of file stm32wbxx_hal_wwdg.h.

#define WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2

WWDG counter clock = (PCLK1/4096)/16

Definition at line 134 of file stm32wbxx_hal_wwdg.h.

#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0

WWDG counter clock = (PCLK1/4096)/2

Definition at line 131 of file stm32wbxx_hal_wwdg.h.

#define WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0)

WWDG counter clock = (PCLK1/4096)/32

Definition at line 135 of file stm32wbxx_hal_wwdg.h.

#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1

WWDG counter clock = (PCLK1/4096)/4

Definition at line 132 of file stm32wbxx_hal_wwdg.h.

#define WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1)

WWDG counter clock = (PCLK1/4096)/64

Definition at line 136 of file stm32wbxx_hal_wwdg.h.

#define WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)

WWDG counter clock = (PCLK1/4096)/8

Definition at line 133 of file stm32wbxx_hal_wwdg.h.

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: WWDG Early Wakeup Interrupt Mode

Defines
WWDG Early Wakeup Interrupt Mode
WWDG Exported Constants

Defines

#define | WWDG_EWI_DISABLE 0x00000000u
#define | WWDG_EWI_ENABLE WWDG_CFR_EWI

Define Documentation

#define WWDG_EWI_DISABLE 0x00000000u

EWI Disable

Definition at line 145 of file stm32wbxx_hal_wwdg.h.

#define WWDG_EWI_ENABLE WWDG_CFR_EWI

EWI Enable

Definition at line 146 of file stm32wbxx_hal_wwdg.h.

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: WWDG Private Macros

Defines
WWDG Private Macros
WWDG

Defines

#define | IS_WWDG_PRESCALER(__PRESCALER__)
#define | IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
#define | IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
#define | IS_WWDG_EWI_MODE(__MODE__)

Define Documentation

#define IS_WWDG_COUNTER ( __COUNTER__ ) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))

Definition at line 171 of file stm32wbxx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

#define IS_WWDG_EWI_MODE ( __MODE__ )
Value:
(((__MODE__) == WWDG_EWI_ENABLE) || \
                                             ((__MODE__) == WWDG_EWI_DISABLE))

Definition at line 173 of file stm32wbxx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

#define IS_WWDG_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == WWDG_PRESCALER_1)  || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_2)  || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_4)  || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_8)  || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_16) || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_32) || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_64) || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_128))

Definition at line 160 of file stm32wbxx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

#define IS_WWDG_WINDOW ( __WINDOW__ ) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))

Definition at line 169 of file stm32wbxx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: WWDG Exported Macros

Defines
WWDG Exported Macros
WWDG

Defines

#define | __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
Enable the WWDG peripheral.
#define | __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
Enable the WWDG early wakeup interrupt.
#define | __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
Check whether the selected WWDG interrupt has occurred or not.
#define | __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
Clear the WWDG interrupt pending bits.
#define | __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check whether the specified WWDG flag is set or not.
#define | __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clear the WWDG's pending flags.
#define | __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified WWDG interrupt source is enabled or not.

Define Documentation

#define __HAL_WWDG_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->SR = ~(__FLAG__))

Clear the WWDG's pending flags.

Parameters:
__HANDLE__ WWDG handle
__FLAG__ specifies the flag to clear. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt flag
Return values:
None

Definition at line 241 of file stm32wbxx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

#define __HAL_WWDG_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))

Clear the WWDG interrupt pending bits.

bits to clear the selected interrupt pending bits.

Parameters:
__HANDLE__ WWDG handle
__INTERRUPT__ specifies the interrupt pending bit to clear. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt flag

Definition at line 221 of file stm32wbxx_hal_wwdg.h.

#define __HAL_WWDG_ENABLE ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)

Enable the WWDG peripheral.

Parameters:
__HANDLE__ WWDG handle
Return values:
None

Definition at line 191 of file stm32wbxx_hal_wwdg.h.

#define __HAL_WWDG_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))

Enable the WWDG early wakeup interrupt.

Parameters:
__HANDLE__,: WWDG handle
__INTERRUPT__ specifies the interrupt to enable. This parameter can be one of the following values:
  • WWDG_IT_EWI: Early wakeup interrupt
Note:
Once enabled this interrupt cannot be disabled except by a system reset.
Return values:
None

Definition at line 202 of file stm32wbxx_hal_wwdg.h.

#define __HAL_WWDG_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))

Check whether the specified WWDG flag is set or not.

Parameters:
__HANDLE__ WWDG handle
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt flag
Return values:
The new state of WWDG_FLAG (SET or RESET).

Definition at line 231 of file stm32wbxx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

#define __HAL_WWDG_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))

Check whether the selected WWDG interrupt has occurred or not.

Parameters:
__HANDLE__ WWDG handle
__INTERRUPT__ specifies the it to check. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt IT
Return values:
The new state of WWDG_FLAG (SET or RESET).

Definition at line 212 of file stm32wbxx_hal_wwdg.h.

#define __HAL_WWDG_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
(((__HANDLE__)->Instance->CFR\
                                                              & (__INTERRUPT__)) == (__INTERRUPT__))

Check whether the specified WWDG interrupt source is enabled or not.

Parameters:
__HANDLE__ WWDG Handle.
__INTERRUPT__ specifies the WWDG interrupt source to check. This parameter can be one of the following values:
  • WWDG_IT_EWI: Early Wakeup Interrupt
Return values:
state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 250 of file stm32wbxx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields

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  • AbortCpltCallback : __I2C_HandleTypeDef , __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __QSPI_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • AbortReceiveCpltCallback : __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef
  • AbortTransmitCpltCallback : __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef
  • AccessPermission : MPU_Region_InitTypeDef
  • AcquisitionMode : TSC_InitTypeDef
  • Activation : SAI_PdmInitTypeDef
  • ActiveEdge : LPTIM_TriggerConfigTypeDef
  • ActiveFrameLength : SAI_FrameInitTypeDef
  • AdcClockSelection : RCC_PeriphCLKInitTypeDef
  • AddrCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • Address : FLASH_ProcessTypeDef , QSPI_CommandTypeDef , UART_WakeUpTypeDef
  • AddressingMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • AddressLength : UART_WakeUpTypeDef
  • AddressMode : QSPI_CommandTypeDef
  • AddressSize : QSPI_CommandTypeDef
  • AddrEventCount : __I2C_HandleTypeDef
  • AdvancedInit : __UART_HandleTypeDef , __SMARTCARD_HandleTypeDef
  • AdvFeatureInit : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • AHB4CLKDivider : LL_UTILS_ClkInitTypeDef
  • AHBCLK2Divider : RCC_ClkInitTypeDef
  • AHBCLK4Divider : RCC_ClkInitTypeDef
  • AHBCLKDivider : RCC_ClkInitTypeDef
  • Alarm : RTC_AlarmTypeDef
  • AlarmAEventCallback : __RTC_HandleTypeDef
  • AlarmBEventCallback : __RTC_HandleTypeDef
  • AlarmDateWeekDay : LL_RTC_AlarmTypeDef , RTC_AlarmTypeDef
  • AlarmDateWeekDaySel : RTC_AlarmTypeDef , LL_RTC_AlarmTypeDef
  • AlarmMask : LL_RTC_AlarmTypeDef , RTC_AlarmTypeDef
  • AlarmSubSecondMask : RTC_AlarmTypeDef
  • AlarmTime : RTC_AlarmTypeDef , LL_RTC_AlarmTypeDef
  • Algorithm : CRYP_ConfigTypeDef
  • Alternate : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • AlternateByteMode : QSPI_CommandTypeDef
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  • AlternateBytesSize : QSPI_CommandTypeDef
  • AnalogFilter : SMBUS_InitTypeDef , LL_I2C_InitTypeDef
  • APB1CLKDivider : RCC_ClkInitTypeDef , LL_UTILS_ClkInitTypeDef
  • APB2CLKDivider : LL_UTILS_ClkInitTypeDef , RCC_ClkInitTypeDef
  • AsynchPrediv : RTC_InitTypeDef
  • AsynchPrescaler : LL_RTC_InitTypeDef
  • AudioFrequency : SAI_InitTypeDef
  • AudioMode : SAI_InitTypeDef
  • AutoBaudRateEnable : UART_AdvFeatureInitTypeDef
  • AutoBaudRateMode : UART_AdvFeatureInitTypeDef
  • AutoInjectedConv : ADC_InjectionConfTypeDef
  • AutoKeyDerivation : __CRYP_HandleTypeDef
  • AutomaticOutput : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • AutomaticStop : QSPI_AutoPollingTypeDef
  • Autoreload : LL_TIM_InitTypeDef
  • AutoReloadMatchCallback : __LPTIM_HandleTypeDef
  • AutoReloadPreload : TIM_Base_InitTypeDef
  • AutoReloadWriteCallback : __LPTIM_HandleTypeDef
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Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

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  • B0 : CRYP_ConfigTypeDef
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  • BaseAddress : MPU_Region_InitTypeDef
  • basePointX : PKA_ECDSAVerifInTypeDef , PKA_ECDSASignInTypeDef
  • basePointY : PKA_ECDSASignInTypeDef , PKA_ECDSAVerifInTypeDef
  • battery_charging_active : __PCD_HandleTypeDef
  • BaudRate : LL_USART_InitTypeDef , IRDA_InitTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef , LL_LPUART_InitTypeDef , LL_SPI_InitTypeDef
  • BaudRatePrescaler : SPI_InitTypeDef
  • BCDCallback : __PCD_HandleTypeDef
  • BESL : __PCD_HandleTypeDef
  • Bias : LCD_InitTypeDef
  • BitOrder : LL_SPI_InitTypeDef
  • BlankingSrce : COMP_InitTypeDef
  • BlinkFrequency : LCD_InitTypeDef
  • BlinkMode : LCD_InitTypeDef
  • BlockLength : SMARTCARD_InitTypeDef
  • Break2Callback : __TIM_HandleTypeDef
  • Break2Filter : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • Break2Polarity : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • Break2State : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • BreakCallback : __TIM_HandleTypeDef
  • BreakFilter : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • BreakPolarity : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • BreakState : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields

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  • C2BootRegion : FLASH_OBProgramInitTypeDef
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  • Channel : ADC_ChannelConfTypeDef , ADC_AnalogWDGConfTypeDef , __TIM_HandleTypeDef
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  • ChipSelectHighTime : QSPI_InitTypeDef
  • ClearInputFilter : TIM_ClearInputConfigTypeDef
  • ClearInputPolarity : TIM_ClearInputConfigTypeDef
  • ClearInputPrescaler : TIM_ClearInputConfigTypeDef
  • ClearInputSource : TIM_ClearInputConfigTypeDef
  • ClearInputState : TIM_ClearInputConfigTypeDef
  • CLKLastBit : SMARTCARD_InitTypeDef , USART_InitTypeDef
  • CLKPhase : SMARTCARD_InitTypeDef , SPI_InitTypeDef , USART_InitTypeDef
  • CLKPolarity : SMARTCARD_InitTypeDef , SPI_InitTypeDef , USART_InitTypeDef
  • Clock : LPTIM_InitTypeDef
  • ClockDivision : TIM_Base_InitTypeDef , LL_TIM_InitTypeDef
  • ClockEnable : SAI_PdmInitTypeDef
  • ClockErrorDetection : LL_RNG_InitTypeDef , RNG_InitTypeDef
  • ClockFilter : TIM_ClockConfigTypeDef
  • ClockMode : QSPI_InitTypeDef
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  • ConnectCallback : __PCD_HandleTypeDef
  • ContextQueue : ADC_InjectionConfigTypeDef
  • ContinuousConvMode : ADC_InitTypeDef
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  • Contrast : LCD_InitTypeDef
  • ConvCpltCallback : __ADC_HandleTypeDef , __TSC_HandleTypeDef
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  • Counter : WWDG_InitTypeDef
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  • CPU1CLKDivider : LL_UTILS_ClkInitTypeDef
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  • CRCCalculation : SPI_InitTypeDef , LL_SPI_InitTypeDef
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STM32WB55xx HAL User Manual: Data Fields

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  • DataAlign : ADC_InitTypeDef
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  • DataMode : QSPI_CommandTypeDef
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  • DualAddressMode : SMBUS_InitTypeDef , I2C_InitTypeDef
  • DummyCycles : QSPI_CommandTypeDef
  • Duty : LCD_InitTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

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  • Enable : MPU_Region_InitTypeDef , TIMEx_BreakInputConfigTypeDef
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  • EOCSelection : ADC_InitTypeDef
  • ErrorCallback : __SAI_HandleTypeDef , __SMARTCARD_HandleTypeDef , __ADC_HandleTypeDef , __SMBUS_HandleTypeDef , __SPI_HandleTypeDef , __CRYP_HandleTypeDef , __TIM_HandleTypeDef , __TSC_HandleTypeDef , __I2C_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef , __IRDA_HandleTypeDef , __PKA_HandleTypeDef , __QSPI_HandleTypeDef , __RNG_HandleTypeDef
  • ErrorCode : __RNG_HandleTypeDef , __USART_HandleTypeDef , __PCD_HandleTypeDef , __DMA_HandleTypeDef , __PKA_HandleTypeDef , __QSPI_HandleTypeDef , __SAI_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SMBUS_HandleTypeDef , __TSC_HandleTypeDef , __UART_HandleTypeDef , __SPI_HandleTypeDef , LCD_HandleTypeDef , __ADC_HandleTypeDef , __COMP_HandleTypeDef , __IRDA_HandleTypeDef , __I2C_HandleTypeDef , __CRYP_HandleTypeDef , FLASH_ProcessTypeDef
  • ErrorLimitValue : RCC_CRSInitTypeDef
  • EventEnable : HAL_DMA_MuxSyncConfigTypeDef
  • EwiCallback : __WWDG_HandleTypeDef
  • EWIMode : WWDG_InitTypeDef
  • expSize : PKA_ModExpFastModeInTypeDef , PKA_ModExpInTypeDef
  • ExternalTrigConv : ADC_InitTypeDef
  • ExternalTrigConvEdge : ADC_InitTypeDef
  • ExternalTrigInjecConv : ADC_InjectionConfTypeDef
  • ExternalTrigInjecConvEdge : ADC_InjectionConfTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- f -

  • FifoMode : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • FifoThreshold : QSPI_InitTypeDef
  • FIFOThreshold : SAI_InitTypeDef
  • FifoThresholdCallback : __QSPI_HandleTypeDef
  • Filter : RTC_TamperTypeDef
  • FirstBit : SAI_InitTypeDef , SPI_InitTypeDef
  • FirstBitOffset : SAI_SlotInitTypeDef
  • FlashSize : QSPI_InitTypeDef
  • FrameInit : __SAI_HandleTypeDef
  • FrameLength : SAI_FrameInitTypeDef
  • FreqErrorCapture : RCC_CRSSynchroInfoTypeDef
  • FreqErrorDirection : RCC_CRSSynchroInfoTypeDef
  • FSDefinition : SAI_FrameInitTypeDef
  • FSOffset : SAI_FrameInitTypeDef
  • FSPolarity : SAI_FrameInitTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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  • Variables
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  • b
  • c
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- g -

  • GeneralCallMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • GeneratingPolynomial : CRC_InitTypeDef
  • GPIOSel : EXTI_ConfigTypeDef
  • gState : __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef
  • GuardTime : SMARTCARD_InitTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields

  • Data Structure Index
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  • b
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- h -

  • HallSensor_MspDeInitCallback : __TIM_HandleTypeDef
  • HallSensor_MspInitCallback : __TIM_HandleTypeDef
  • HardwareFlowControl : LL_USART_InitTypeDef , LL_LPUART_InitTypeDef
  • hash : PKA_ECDSAVerifInTypeDef , PKA_ECDSASignInTypeDef
  • HCLK1_Frequency : LL_RCC_ClocksTypeDef
  • HCLK2_Frequency : LL_RCC_ClocksTypeDef
  • HCLK4_Frequency : LL_RCC_ClocksTypeDef
  • HCLK5_Frequency : LL_RCC_ClocksTypeDef
  • hdma : __QSPI_HandleTypeDef , __TIM_HandleTypeDef
  • hdmain : __CRYP_HandleTypeDef
  • hdmaout : __CRYP_HandleTypeDef
  • hdmarx : __IRDA_HandleTypeDef , __SAI_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef , __I2C_HandleTypeDef
  • hdmatx : __UART_HandleTypeDef , __I2C_HandleTypeDef , __IRDA_HandleTypeDef , __SAI_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __USART_HandleTypeDef
  • Header : CRYP_ConfigTypeDef
  • HeaderSize : CRYP_ConfigTypeDef
  • HighDrive : LCD_InitTypeDef
  • HighThreshold : ADC_AnalogWDGConfTypeDef
  • HourFormat : RTC_InitTypeDef , LL_RTC_InitTypeDef
  • Hours : LL_RTC_TimeTypeDef , RTC_TimeTypeDef
  • HSEState : RCC_OscInitTypeDef
  • HSI48CalibrationValue : RCC_CRSSynchroInfoTypeDef , RCC_CRSInitTypeDef
  • HSI48State : RCC_OscInitTypeDef
  • HSICalibrationValue : RCC_OscInitTypeDef
  • HSIState : RCC_OscInitTypeDef
  • HwFlowCtl : UART_InitTypeDef
  • Hysteresis : COMP_InitTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- i -

  • I2c1ClockSelection : RCC_PeriphCLKInitTypeDef
  • I2c3ClockSelection : RCC_PeriphCLKInitTypeDef
  • IC1ActiveInput : LL_TIM_ENCODER_InitTypeDef
  • IC1Filter : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef , LL_TIM_ENCODER_InitTypeDef , LL_TIM_HALLSENSOR_InitTypeDef
  • IC1Polarity : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef , LL_TIM_ENCODER_InitTypeDef , LL_TIM_HALLSENSOR_InitTypeDef
  • IC1Prescaler : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef , LL_TIM_ENCODER_InitTypeDef , LL_TIM_HALLSENSOR_InitTypeDef
  • IC1Selection : TIM_Encoder_InitTypeDef
  • IC2ActiveInput : LL_TIM_ENCODER_InitTypeDef
  • IC2Filter : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Polarity : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Prescaler : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Selection : TIM_Encoder_InitTypeDef
  • IC_CaptureCallback : __TIM_HandleTypeDef
  • IC_CaptureHalfCpltCallback : __TIM_HandleTypeDef
  • IC_MspDeInitCallback : __TIM_HandleTypeDef
  • IC_MspInitCallback : __TIM_HandleTypeDef
  • ICActiveInput : LL_TIM_IC_InitTypeDef
  • ICFilter : LL_TIM_IC_InitTypeDef , TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef
  • ICPolarity : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef , LL_TIM_IC_InitTypeDef
  • ICPrescaler : TIM_IC_InitTypeDef , LL_TIM_IC_InitTypeDef
  • ICSelection : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef
  • IN_ep : __PCD_HandleTypeDef
  • InCpltCallback : __CRYP_HandleTypeDef
  • Init : __WWDG_HandleTypeDef , __ADC_HandleTypeDef , __COMP_HandleTypeDef , CRC_HandleTypeDef , __CRYP_HandleTypeDef , __DMA_HandleTypeDef , __I2C_HandleTypeDef , __IRDA_HandleTypeDef , IWDG_HandleTypeDef , LCD_HandleTypeDef , __LPTIM_HandleTypeDef , __PCD_HandleTypeDef , __QSPI_HandleTypeDef , __RNG_HandleTypeDef , __RTC_HandleTypeDef , __SAI_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SMBUS_HandleTypeDef , __SPI_HandleTypeDef , __TIM_HandleTypeDef , __TSC_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • InitValue : CRC_InitTypeDef
  • InjecOversampling : ADC_InjectionConfTypeDef
  • InjecOversamplingMode : ADC_InjectionConfTypeDef
  • InjectedChannel : ADC_InjectionConfTypeDef
  • InjectedConvCpltCallback : __ADC_HandleTypeDef
  • InjectedDiscontinuousConvMode : ADC_InjectionConfTypeDef
  • InjectedNbrOfConversion : ADC_InjectionConfTypeDef
  • InjectedOffset : ADC_InjectionConfTypeDef
  • InjectedOffsetNumber : ADC_InjectionConfTypeDef
  • InjectedQueueOverflowCallback : __ADC_HandleTypeDef
  • InjectedRank : ADC_InjectionConfTypeDef
  • InjectedSamplingTime : ADC_InjectionConfTypeDef
  • InjectedSingleDiff : ADC_InjectionConfTypeDef
  • InjectionConfig : __ADC_HandleTypeDef
  • Input1Source : LPTIM_InitTypeDef
  • Input2Source : LPTIM_InitTypeDef
  • InputDataFormat : CRC_HandleTypeDef
  • InputDataInversionMode : CRC_InitTypeDef
  • InputHysteresis : LL_COMP_InitTypeDef
  • InputMinus : COMP_InitTypeDef , LL_COMP_InitTypeDef
  • InputPlus : LL_COMP_InitTypeDef , COMP_InitTypeDef
  • InputTrigger : TIM_SlaveConfigTypeDef
  • Instance : __SMBUS_HandleTypeDef , __UART_HandleTypeDef , CRC_HandleTypeDef , __LPTIM_HandleTypeDef , __CRYP_HandleTypeDef , __DMA_HandleTypeDef , IWDG_HandleTypeDef , __TSC_HandleTypeDef , __SPI_HandleTypeDef , __PKA_HandleTypeDef , __ADC_HandleTypeDef , __IPCC_HandleTypeDef , __COMP_HandleTypeDef , __WWDG_HandleTypeDef , __RTC_HandleTypeDef , __PCD_HandleTypeDef , LCD_HandleTypeDef , __TIM_HandleTypeDef , __SAI_HandleTypeDef , __RNG_HandleTypeDef , __IRDA_HandleTypeDef , __I2C_HandleTypeDef , __USART_HandleTypeDef , __QSPI_HandleTypeDef , __SMARTCARD_HandleTypeDef
  • Instruction : QSPI_CommandTypeDef
  • InstructionMode : QSPI_CommandTypeDef
  • integer : PKA_ECDSASignInTypeDef
  • Interrupt : RTC_TamperTypeDef
  • InterruptServiceRoutine : __SAI_HandleTypeDef
  • Interval : QSPI_AutoPollingTypeDef
  • IODefaultMode : TSC_InitTypeDef
  • IPCCdataBufAddr : FLASH_OBProgramInitTypeDef
  • IsBufferable : MPU_Region_InitTypeDef
  • IsCacheable : MPU_Region_InitTypeDef
  • ISOINIncompleteCallback : __PCD_HandleTypeDef
  • ISOOUTIncompleteCallback : __PCD_HandleTypeDef
  • IsShareable : MPU_Region_InitTypeDef
  • ITMode : ADC_AnalogWDGConfTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- k -

  • KeyIVConfig : __CRYP_HandleTypeDef
  • KeyIVConfigSkip : CRYP_ConfigTypeDef
  • KeySize : CRYP_ConfigTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- l -

  • LastBitClockPulse : LL_USART_ClockInitTypeDef
  • LeftDelay : SAIEx_PdmMicDelayParamTypeDef
  • LevelOutOfWindow2Callback : __ADC_HandleTypeDef
  • LevelOutOfWindow3Callback : __ADC_HandleTypeDef
  • LevelOutOfWindowCallback : __ADC_HandleTypeDef
  • Line : EXTI_HandleTypeDef , EXTI_ConfigTypeDef
  • Line_0_31 : LL_EXTI_InitTypeDef
  • Line_32_63 : LL_EXTI_InitTypeDef
  • LineCommand : LL_EXTI_InitTypeDef
  • ListenCpltCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • Lock : __CRYP_HandleTypeDef , __TSC_HandleTypeDef , __UART_HandleTypeDef , __DMA_HandleTypeDef , __USART_HandleTypeDef , FLASH_ProcessTypeDef , __TIM_HandleTypeDef , __SPI_HandleTypeDef , __SMBUS_HandleTypeDef , __I2C_HandleTypeDef , __SAI_HandleTypeDef , __RTC_HandleTypeDef , __IRDA_HandleTypeDef , LCD_HandleTypeDef , __LPTIM_HandleTypeDef , __PCD_HandleTypeDef , __QSPI_HandleTypeDef , __RNG_HandleTypeDef , __ADC_HandleTypeDef , __COMP_HandleTypeDef , __SMARTCARD_HandleTypeDef , CRC_HandleTypeDef
  • LockLevel : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • LowPowerAutoWait : ADC_InitTypeDef
  • LowPowerMode : LL_ADC_InitTypeDef
  • LowThreshold : ADC_AnalogWDGConfTypeDef
  • lpm_active : __PCD_HandleTypeDef
  • LPM_State : __PCD_HandleTypeDef
  • LPMCallback : __PCD_HandleTypeDef
  • Lptim1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Lptim2ClockSelection : RCC_PeriphCLKInitTypeDef
  • Lpuart1ClockSelection : RCC_PeriphCLKInitTypeDef
  • LSEState : RCC_OscInitTypeDef
  • LSI2CalibrationValue : RCC_OscInitTypeDef
  • LSIState : RCC_OscInitTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- m -

  • Mask : __IRDA_HandleTypeDef , QSPI_AutoPollingTypeDef , __USART_HandleTypeDef , __UART_HandleTypeDef
  • MaskFlag : RTC_TamperTypeDef
  • MasterOutputTrigger : TIM_MasterConfigTypeDef
  • MasterOutputTrigger2 : TIM_MasterConfigTypeDef
  • MasterRxCpltCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • MasterSlaveMode : TIM_MasterConfigTypeDef
  • MasterTxCpltCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • Match : QSPI_AutoPollingTypeDef
  • MatchMode : QSPI_AutoPollingTypeDef
  • MaxCountInterrupt : TSC_InitTypeDef
  • MaxCountValue : TSC_InitTypeDef
  • Mckdiv : SAI_InitTypeDef
  • MckOutput : SAI_InitTypeDef
  • MckOverSampling : SAI_InitTypeDef
  • MemDataAlignment : DMA_InitTypeDef
  • MemInc : DMA_InitTypeDef
  • MemoryOrM2MDstAddress : LL_DMA_InitTypeDef
  • MemoryOrM2MDstDataSize : LL_DMA_InitTypeDef
  • MemoryOrM2MDstIncMode : LL_DMA_InitTypeDef
  • MemRxCpltCallback : __I2C_HandleTypeDef
  • MemTxCpltCallback : __I2C_HandleTypeDef
  • MicPair : SAIEx_PdmMicDelayParamTypeDef
  • MicPairsNbr : SAI_PdmInitTypeDef
  • Minutes : RTC_TimeTypeDef , LL_RTC_TimeTypeDef
  • Mode : DMA_InitTypeDef , EXTI_ConfigTypeDef , GPIO_InitTypeDef , __I2C_HandleTypeDef , IRDA_InitTypeDef , PWR_PVDTypeDef , PWR_PVMTypeDef , SMARTCARD_InitTypeDef , SPI_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef , LL_DMA_InitTypeDef , LL_EXTI_InitTypeDef , LL_GPIO_InitTypeDef , LL_PKA_InitTypeDef , LL_SPI_InitTypeDef , COMP_InitTypeDef
  • modSize : PKA_ModRedInTypeDef
  • modulus : PKA_ECCMulFastModeInTypeDef , PKA_ECCMulInTypeDef , PKA_PointCheckInTypeDef , PKA_ECDSAVerifInTypeDef , PKA_ECDSASignInTypeDef
  • modulusSize : PKA_ECCMulFastModeInTypeDef , PKA_ECCMulInTypeDef , PKA_PointCheckInTypeDef , PKA_ECDSAVerifInTypeDef , PKA_ECDSASignInTypeDef
  • MonoStereoMode : SAI_InitTypeDef
  • Month : RTC_DateTypeDef , LL_RTC_DateTypeDef
  • MSBFirst : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • MSICalibrationValue : RCC_OscInitTypeDef
  • MSIClockRange : RCC_OscInitTypeDef
  • MSIState : RCC_OscInitTypeDef
  • MspDeInitCallback : __TSC_HandleTypeDef , __QSPI_HandleTypeDef , __ADC_HandleTypeDef , __PKA_HandleTypeDef , __PCD_HandleTypeDef , __COMP_HandleTypeDef , __CRYP_HandleTypeDef , __I2C_HandleTypeDef , __IRDA_HandleTypeDef , __LPTIM_HandleTypeDef , __RNG_HandleTypeDef , __SAI_HandleTypeDef , __SMBUS_HandleTypeDef , __SPI_HandleTypeDef , __USART_HandleTypeDef , __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __RTC_HandleTypeDef
  • MspInitCallback : __SAI_HandleTypeDef , __QSPI_HandleTypeDef , __WWDG_HandleTypeDef , __PCD_HandleTypeDef , __SMARTCARD_HandleTypeDef , __LPTIM_HandleTypeDef , __SPI_HandleTypeDef , __IRDA_HandleTypeDef , __RNG_HandleTypeDef , __PKA_HandleTypeDef , __I2C_HandleTypeDef , __UART_HandleTypeDef , __RTC_HandleTypeDef , __USART_HandleTypeDef , __COMP_HandleTypeDef , __ADC_HandleTypeDef , __SMBUS_HandleTypeDef , __TSC_HandleTypeDef , __CRYP_HandleTypeDef
  • mutecallback : __SAI_HandleTypeDef
  • MuxSegment : LCD_InitTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- n -

  • NACKEnable : SMARTCARD_InitTypeDef
  • NbData : QSPI_CommandTypeDef , LL_DMA_InitTypeDef
  • NbPages : FLASH_EraseInitTypeDef
  • NbPagesToErase : FLASH_ProcessTypeDef
  • NbrOfConversion : ADC_InitTypeDef
  • NbrOfDiscConversion : ADC_InitTypeDef
  • NbRxDataToProcess : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • NbTxDataToProcess : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • NoDivider : SAI_InitTypeDef
  • NoErase : RTC_TamperTypeDef
  • NoStretchMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • NSS : LL_SPI_InitTypeDef , SPI_InitTypeDef
  • NSSPMode : SPI_InitTypeDef
  • Number : MPU_Region_InitTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields

  • Data Structure Index
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  • c
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- o -

  • OC_DelayElapsedCallback : __TIM_HandleTypeDef
  • OC_MspDeInitCallback : __TIM_HandleTypeDef
  • OC_MspInitCallback : __TIM_HandleTypeDef
  • OCFastMode : TIM_OC_InitTypeDef
  • OCIdleState : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCMode : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCNIdleState : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCNPolarity : LL_TIM_OC_InitTypeDef , TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OCNState : LL_TIM_OC_InitTypeDef
  • OCPolarity : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCState : LL_TIM_OC_InitTypeDef
  • Offset : ADC_ChannelConfTypeDef
  • OffsetNumber : ADC_ChannelConfTypeDef
  • OffStateIDLEMode : TIM_BreakDeadTimeConfigTypeDef
  • OffStateRunMode : TIM_BreakDeadTimeConfigTypeDef
  • OneBitSampling : SMARTCARD_InitTypeDef , UART_InitTypeDef
  • OnePulse_MspDeInitCallback : __TIM_HandleTypeDef
  • OnePulse_MspInitCallback : __TIM_HandleTypeDef
  • OperationCpltCallback : __PKA_HandleTypeDef
  • OpSize : PKA_ModExpFastModeInTypeDef , PKA_ModRedInTypeDef , PKA_ModExpInTypeDef
  • OptionType : FLASH_OBProgramInitTypeDef
  • OscillatorType : RCC_OscInitTypeDef
  • OSSIState : LL_TIM_BDTR_InitTypeDef
  • OSSRState : LL_TIM_BDTR_InitTypeDef
  • OUT_ep : __PCD_HandleTypeDef
  • OutCpltCallback : __CRYP_HandleTypeDef
  • OutPut : RTC_InitTypeDef
  • OutputBlankingSource : LL_COMP_InitTypeDef
  • OutputDataInversionMode : CRC_InitTypeDef
  • OutputDrive : SAI_InitTypeDef
  • OutputPol : COMP_InitTypeDef
  • OutputPolarity : LL_COMP_InitTypeDef
  • OutPutPolarity : RTC_InitTypeDef
  • OutputPolarity : LPTIM_InitTypeDef
  • OutPutRemap : RTC_InitTypeDef
  • OutputType : LL_GPIO_InitTypeDef
  • OutPutType : RTC_InitTypeDef
  • OutputVoltage : PWR_SMPSTypeDef
  • Overrun : ADC_InitTypeDef , LL_ADC_REG_InitTypeDef
  • OverrunDisable : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • OverSampling : UART_InitTypeDef
  • Oversampling : ADC_InitTypeDef
  • OverSampling : LL_USART_InitTypeDef
  • OversamplingMode : ADC_InitTypeDef
  • OversamplingStopReset : ADC_OversamplingTypeDef
  • OwnAddress1 : LL_I2C_InitTypeDef , SMBUS_InitTypeDef , I2C_InitTypeDef
  • OwnAddress2 : I2C_InitTypeDef , SMBUS_InitTypeDef
  • OwnAddress2Masks : SMBUS_InitTypeDef , I2C_InitTypeDef
  • OwnAddrSize : LL_I2C_InitTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
  • c
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  • p
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  • u
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  • x
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- p -

  • PacketErrorCheckMode : SMBUS_InitTypeDef
  • Page : FLASH_EraseInitTypeDef , FLASH_ProcessTypeDef
  • Parent : __DMA_HandleTypeDef
  • Parity : USART_InitTypeDef , LL_LPUART_InitTypeDef , IRDA_InitTypeDef , LL_USART_InitTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef
  • pBuffPtr : __I2C_HandleTypeDef , __SAI_HandleTypeDef , __SMBUS_HandleTypeDef
  • PCLK1_Frequency : LL_RCC_ClocksTypeDef
  • PCLK2_Frequency : LL_RCC_ClocksTypeDef
  • PCROP1AEndAddr : FLASH_OBProgramInitTypeDef
  • PCROP1AStartAddr : FLASH_OBProgramInitTypeDef
  • PCROP1BEndAddr : FLASH_OBProgramInitTypeDef
  • PCROP1BStartAddr : FLASH_OBProgramInitTypeDef
  • PCROPConfig : FLASH_OBProgramInitTypeDef
  • pCrypInBuffPtr : __CRYP_HandleTypeDef
  • pCrypOutBuffPtr : __CRYP_HandleTypeDef
  • pData : __PCD_HandleTypeDef
  • PdmInit : SAI_InitTypeDef
  • PendingCallback : EXTI_HandleTypeDef
  • Period : TIM_Base_InitTypeDef
  • PeriodElapsedCallback : __TIM_HandleTypeDef
  • PeriodElapsedHalfCpltCallback : __TIM_HandleTypeDef
  • PeriphClockSelection : RCC_PeriphCLKInitTypeDef
  • PeriphDataAlignment : DMA_InitTypeDef
  • PeripheralMode : LL_I2C_InitTypeDef , SMBUS_InitTypeDef
  • PeriphInc : DMA_InitTypeDef
  • PeriphOrM2MSrcAddress : LL_DMA_InitTypeDef
  • PeriphOrM2MSrcDataSize : LL_DMA_InitTypeDef
  • PeriphOrM2MSrcIncMode : LL_DMA_InitTypeDef
  • PeriphRequest : LL_DMA_InitTypeDef
  • pExp : PKA_ModExpInTypeDef , PKA_ModExpFastModeInTypeDef
  • Phase : __CRYP_HandleTypeDef
  • Pin : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • pInitVect : CRYP_ConfigTypeDef
  • pKey : CRYP_ConfigTypeDef
  • PLL : RCC_OscInitTypeDef
  • PLLM : RCC_PLLInitTypeDef , LL_UTILS_PLLInitTypeDef
  • PLLN : RCC_PLLInitTypeDef , RCC_PLLSAI1InitTypeDef , LL_UTILS_PLLInitTypeDef
  • PLLP : RCC_PLLInitTypeDef , RCC_PLLSAI1InitTypeDef
  • PLLQ : RCC_PLLInitTypeDef , RCC_PLLSAI1InitTypeDef
  • PLLR : RCC_PLLInitTypeDef , RCC_PLLSAI1InitTypeDef , LL_UTILS_PLLInitTypeDef
  • PLLSAI1 : RCC_PeriphCLKInitTypeDef
  • PLLSAI1ClockOut : RCC_PLLSAI1InitTypeDef
  • PLLSource : RCC_PLLInitTypeDef
  • PLLState : RCC_PLLInitTypeDef
  • pMod : PKA_ModInvInTypeDef , PKA_ModRedInTypeDef , PKA_ModExpInTypeDef , PKA_ModExpFastModeInTypeDef
  • pMontgomeryParam : PKA_ECCMulFastModeInTypeDef , PKA_ModExpFastModeInTypeDef
  • pointX : PKA_ECCMulFastModeInTypeDef , PKA_ECCMulInTypeDef , PKA_PointCheckInTypeDef
  • pointY : PKA_ECCMulFastModeInTypeDef , PKA_ECCMulInTypeDef , PKA_PointCheckInTypeDef
  • Polarity : HAL_DMA_MuxRequestGeneratorConfigTypeDef , LPTIM_ULPClockConfigTypeDef , RCC_CRSInitTypeDef , TIMEx_BreakInputConfigTypeDef , LL_LPTIM_InitTypeDef
  • pOp1 : PKA_ModExpInTypeDef , PKA_ModExpFastModeInTypeDef , PKA_MontgomeryParamInTypeDef , PKA_AddInTypeDef , PKA_ModInvInTypeDef , PKA_ModRedInTypeDef , PKA_ModAddInTypeDef
  • pOp2 : PKA_ModAddInTypeDef , PKA_AddInTypeDef
  • pOp3 : PKA_ModAddInTypeDef
  • popA : PKA_RSACRTExpInTypeDef
  • pOpDp : PKA_RSACRTExpInTypeDef
  • pOpDq : PKA_RSACRTExpInTypeDef
  • pOpQinv : PKA_RSACRTExpInTypeDef
  • PowerMode : IRDA_InitTypeDef , LL_COMP_InitTypeDef
  • pPrimeP : PKA_RSACRTExpInTypeDef
  • pPrimeQ : PKA_RSACRTExpInTypeDef
  • pPubKeyCurvePtX : PKA_ECDSAVerifInTypeDef
  • pPubKeyCurvePtY : PKA_ECDSAVerifInTypeDef
  • PrechargeDuration : RTC_TamperTypeDef
  • Prescaler : LPTIM_ClockConfigTypeDef , LL_TIM_InitTypeDef , SMARTCARD_InitTypeDef , IRDA_InitTypeDef , IWDG_InitTypeDef , LCD_InitTypeDef , TIM_Base_InitTypeDef , RCC_CRSInitTypeDef , LL_LPTIM_InitTypeDef , WWDG_InitTypeDef
  • PrescalerValue : LL_LPUART_InitTypeDef , LL_USART_InitTypeDef
  • PreviousState : __SMBUS_HandleTypeDef , __I2C_HandleTypeDef
  • primeOrder : PKA_ECDSASignInTypeDef , PKA_ECDSAVerifInTypeDef
  • primeOrderSize : PKA_ECDSASignInTypeDef , PKA_ECDSAVerifInTypeDef
  • Priority : LL_DMA_InitTypeDef , DMA_InitTypeDef
  • privateKey : PKA_ECDSASignInTypeDef
  • ProcedureOnGoing : FLASH_ProcessTypeDef
  • Protocol : SAI_InitTypeDef
  • pRxBuffPtr : __USART_HandleTypeDef , __UART_HandleTypeDef , __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __QSPI_HandleTypeDef
  • ptX : PKA_ECDSASignOutExtParamTypeDef
  • pTxBuffPtr : __IRDA_HandleTypeDef , __QSPI_HandleTypeDef , __SPI_HandleTypeDef , __USART_HandleTypeDef , __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef
  • ptY : PKA_ECDSASignOutExtParamTypeDef
  • Pull : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • Pulse : TIM_OnePulse_InitTypeDef , TIM_OC_InitTypeDef
  • PulseGeneratorPrescaler : TSC_InitTypeDef
  • PulseOnDuration : LCD_InitTypeDef
  • PVDLevel : PWR_PVDTypeDef
  • PVMType : PWR_PVMTypeDef
  • PWM_MspDeInitCallback : __TIM_HandleTypeDef
  • PWM_MspInitCallback : __TIM_HandleTypeDef
  • PWM_PulseFinishedCallback : __TIM_HandleTypeDef
  • PWM_PulseFinishedHalfCpltCallback : __TIM_HandleTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- q -

  • QueueInjectedContext : ADC_InjectionConfTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- r -

  • RandomNumber : __RNG_HandleTypeDef
  • Rank : ADC_ChannelConfTypeDef
  • Ratio : ADC_InjOversamplingTypeDef , ADC_OversamplingTypeDef
  • RDPLevel : FLASH_OBProgramInitTypeDef
  • ReadyDataCallback : __RNG_HandleTypeDef
  • Reload : IWDG_InitTypeDef
  • ReloadValue : RCC_CRSInitTypeDef , RCC_CRSSynchroInfoTypeDef
  • RepetitionCounter : TIM_Base_InitTypeDef , LL_TIM_InitTypeDef
  • Request : DMA_InitTypeDef
  • RequestNumber : HAL_DMA_MuxSyncConfigTypeDef , HAL_DMA_MuxRequestGeneratorConfigTypeDef
  • ResetCallback : __PCD_HandleTypeDef
  • Resolution : ADC_InitTypeDef , LL_ADC_InitTypeDef
  • ResumeCallback : __PCD_HandleTypeDef
  • RFWakeUpClockSelection : RCC_PeriphCLKInitTypeDef
  • RightBitShift : ADC_OversamplingTypeDef , ADC_InjOversamplingTypeDef
  • RightDelay : SAIEx_PdmMicDelayParamTypeDef
  • RngClockSelection : RCC_PeriphCLKInitTypeDef
  • RSign : PKA_ECDSAVerifInTypeDef , PKA_ECDSASignOutTypeDef
  • RTCClockSelection : RCC_PeriphCLKInitTypeDef
  • RxCpltCallback : __UART_HandleTypeDef , __USART_HandleTypeDef , __IRDA_HandleTypeDef , __QSPI_HandleTypeDef , __SAI_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef
  • RxFifoFullCallback : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • RxHalfCpltCallback : __IRDA_HandleTypeDef , __QSPI_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef , __SAI_HandleTypeDef
  • RxISR : __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • RxPinLevelInvert : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • RxState : __SMARTCARD_HandleTypeDef , __IRDA_HandleTypeDef , __UART_HandleTypeDef
  • RxXferCount : __SMARTCARD_HandleTypeDef , __QSPI_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __IRDA_HandleTypeDef , __USART_HandleTypeDef
  • RxXferSize : __USART_HandleTypeDef , __UART_HandleTypeDef , __SMARTCARD_HandleTypeDef , __IRDA_HandleTypeDef , __SPI_HandleTypeDef , __QSPI_HandleTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields

  • Data Structure Index
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- s -

  • Sai1ClockSelection : RCC_PeriphCLKInitTypeDef
  • SampleShifting : QSPI_InitTypeDef
  • SampleTime : LPTIM_TriggerConfigTypeDef , LPTIM_ULPClockConfigTypeDef
  • SamplingFrequency : RTC_TamperTypeDef
  • SamplingIOs : TSC_InitTypeDef , TSC_IOConfigTypeDef
  • SamplingTime : ADC_ChannelConfTypeDef
  • scalarMul : PKA_ECCMulFastModeInTypeDef , PKA_ECCMulInTypeDef
  • scalarMulSize : PKA_ECCMulFastModeInTypeDef , PKA_ECCMulInTypeDef
  • ScanConvMode : ADC_InitTypeDef
  • SecondFraction : RTC_TimeTypeDef
  • Seconds : LL_RTC_TimeTypeDef , RTC_TimeTypeDef
  • SecureFlashStartAddr : FLASH_OBProgramInitTypeDef
  • SecureMode : FLASH_OBProgramInitTypeDef
  • SecureRAM2aStartAddr : FLASH_OBProgramInitTypeDef
  • SecureRAM2bStartAddr : FLASH_OBProgramInitTypeDef
  • SequencerDiscont : LL_ADC_REG_InitTypeDef , LL_ADC_INJ_InitTypeDef
  • SequencerLength : LL_ADC_REG_InitTypeDef , LL_ADC_INJ_InitTypeDef
  • Setup : __PCD_HandleTypeDef
  • SetupStageCallback : __PCD_HandleTypeDef
  • ShieldIOs : TSC_InitTypeDef , TSC_IOConfigTypeDef
  • SignalID : HAL_DMA_MuxRequestGeneratorConfigTypeDef
  • SingleDiff : ADC_ChannelConfTypeDef
  • SIOOMode : QSPI_CommandTypeDef
  • size : PKA_RSACRTExpInTypeDef , PKA_MontgomeryParamInTypeDef , PKA_AddInTypeDef , PKA_ModInvInTypeDef , PKA_ModAddInTypeDef
  • Size : MPU_Region_InitTypeDef , __CRYP_HandleTypeDef
  • SizesSum : __CRYP_HandleTypeDef
  • SlaveMode : TIM_SlaveConfigTypeDef , __USART_HandleTypeDef
  • SlaveRxCpltCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • SlaveTxCpltCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • SlotActive : SAI_SlotInitTypeDef
  • SlotInit : __SAI_HandleTypeDef
  • SlotNumber : SAI_SlotInitTypeDef
  • SlotSize : SAI_SlotInitTypeDef
  • SMBusTimeout : SMBUS_InitTypeDef
  • SmpsClockSelection : RCC_PeriphCLKInitTypeDef
  • SmpsDivSelection : RCC_PeriphCLKInitTypeDef
  • SOFCallback : __PCD_HandleTypeDef
  • Source : LPTIM_ClockConfigTypeDef , LPTIM_TriggerConfigTypeDef , RCC_CRSInitTypeDef , TIMEx_BreakInputConfigTypeDef
  • Speed : LL_GPIO_InitTypeDef , GPIO_InitTypeDef
  • SpreadSpectrum : TSC_InitTypeDef
  • SpreadSpectrumDeviation : TSC_InitTypeDef
  • SpreadSpectrumPrescaler : TSC_InitTypeDef
  • SSign : PKA_ECDSASignOutTypeDef , PKA_ECDSAVerifInTypeDef
  • StartupCurrent : PWR_SMPSTypeDef
  • State : __RNG_HandleTypeDef , __ADC_HandleTypeDef , __RTC_HandleTypeDef , __TSC_HandleTypeDef , CRC_HandleTypeDef , __DMA_HandleTypeDef , __QSPI_HandleTypeDef , __PKA_HandleTypeDef , __IPCC_HandleTypeDef , LCD_HandleTypeDef , __LPTIM_HandleTypeDef , __PCD_HandleTypeDef , __SAI_HandleTypeDef , __SMBUS_HandleTypeDef , __SPI_HandleTypeDef , __I2C_HandleTypeDef , __CRYP_HandleTypeDef , __COMP_HandleTypeDef , __USART_HandleTypeDef , __TIM_HandleTypeDef
  • Status : __LPTIM_HandleTypeDef
  • StatusBytesSize : QSPI_AutoPollingTypeDef
  • StatusMatchCallback : __QSPI_HandleTypeDef
  • StopBits : UART_InitTypeDef , LL_USART_InitTypeDef , USART_InitTypeDef , LL_LPUART_InitTypeDef , SMARTCARD_InitTypeDef
  • StoreOperation : RTC_TimeTypeDef
  • SubRegionDisable : MPU_Region_InitTypeDef
  • SubSeconds : RTC_TimeTypeDef
  • SuspendCallback : __PCD_HandleTypeDef
  • Swap : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • SyncEnable : HAL_DMA_MuxSyncConfigTypeDef
  • SynchPrediv : RTC_InitTypeDef
  • SynchPrescaler : LL_RTC_InitTypeDef
  • Synchro : SAI_InitTypeDef
  • SynchroExt : SAI_InitTypeDef
  • SynchroPinPolarity : TSC_InitTypeDef
  • SyncPolarity : HAL_DMA_MuxSyncConfigTypeDef
  • SyncSignalID : HAL_DMA_MuxSyncConfigTypeDef
  • SYSCLK_Frequency : LL_RCC_ClocksTypeDef
  • SYSCLKSource : RCC_ClkInitTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- t -

  • Tamper : RTC_TamperTypeDef
  • Tamper1EventCallback : __RTC_HandleTypeDef
  • Tamper2EventCallback : __RTC_HandleTypeDef
  • Tamper3EventCallback : __RTC_HandleTypeDef
  • TamperPullUp : RTC_TamperTypeDef
  • TimeFormat : RTC_TimeTypeDef , LL_RTC_TimeTypeDef
  • Timeout : __QSPI_HandleTypeDef
  • TimeOutActivation : QSPI_MemoryMappedTypeDef
  • TimeOutCallback : __QSPI_HandleTypeDef
  • TimeOutEnable : SMARTCARD_InitTypeDef
  • TimeOutPeriod : QSPI_MemoryMappedTypeDef
  • TimeOutValue : SMARTCARD_InitTypeDef
  • TimeStampEventCallback : __RTC_HandleTypeDef
  • TimeStampOnTamperDetection : RTC_TamperTypeDef
  • Timing : I2C_InitTypeDef , SMBUS_InitTypeDef , LL_I2C_InitTypeDef
  • TIMode : SPI_InitTypeDef
  • TransferDirection : LL_LPUART_InitTypeDef , LL_SPI_InitTypeDef , LL_USART_InitTypeDef
  • TrigAuto : LL_ADC_INJ_InitTypeDef
  • Trigger : EXTI_ConfigTypeDef , LPTIM_InitTypeDef , RTC_TamperTypeDef , LL_EXTI_InitTypeDef
  • TriggerCallback : __COMP_HandleTypeDef , __LPTIM_HandleTypeDef , __TIM_HandleTypeDef
  • TriggeredMode : ADC_OversamplingTypeDef
  • TriggerFilter : TIM_SlaveConfigTypeDef
  • TriggerHalfCpltCallback : __TIM_HandleTypeDef
  • TriggerMode : COMP_InitTypeDef
  • TriggerPolarity : TIM_SlaveConfigTypeDef
  • TriggerPrescaler : TIM_SlaveConfigTypeDef
  • TriggerSource : LL_ADC_REG_InitTypeDef , LL_ADC_INJ_InitTypeDef
  • TriState : SAI_InitTypeDef
  • TxCompletionIndication : SMARTCARD_AdvFeatureInitTypeDef
  • TxCpltCallback : __USART_HandleTypeDef , __SAI_HandleTypeDef , __IRDA_HandleTypeDef , __QSPI_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef
  • TxFifoEmptyCallback : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • TxHalfCpltCallback : __IRDA_HandleTypeDef , __QSPI_HandleTypeDef , __SAI_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • TxISR : __UART_HandleTypeDef , __SPI_HandleTypeDef , __USART_HandleTypeDef , __SMARTCARD_HandleTypeDef
  • TxPinLevelInvert : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • TxRxCpltCallback : __USART_HandleTypeDef , __SPI_HandleTypeDef
  • TxRxHalfCpltCallback : __SPI_HandleTypeDef
  • TxXferCount : __USART_HandleTypeDef , __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __SPI_HandleTypeDef , __IRDA_HandleTypeDef , __QSPI_HandleTypeDef
  • TxXferSize : __IRDA_HandleTypeDef , __USART_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __QSPI_HandleTypeDef
  • TypeAcknowledge : LL_I2C_InitTypeDef
  • TypeErase : FLASH_EraseInitTypeDef
  • TypeExtField : MPU_Region_InitTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- u -

  • UltraLowPowerClock : LPTIM_InitTypeDef
  • UpdateMode : LPTIM_InitTypeDef
  • Usart1ClockSelection : RCC_PeriphCLKInitTypeDef
  • USB_Address : __PCD_HandleTypeDef
  • UsbClockSelection : RCC_PeriphCLKInitTypeDef
  • UserConfig : FLASH_OBProgramInitTypeDef
  • UserType : FLASH_OBProgramInitTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- v -

  • VoltageSource : LCD_InitTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- w -

  • WakeupCallback : __UART_HandleTypeDef
  • WakeUpEvent : UART_WakeUpTypeDef
  • WakeupTarget : PWR_PVMTypeDef
  • WakeUpTimerEventCallback : __RTC_HandleTypeDef
  • WatchdogMode : ADC_AnalogWDGConfTypeDef
  • WatchdogNumber : ADC_AnalogWDGConfTypeDef
  • Waveform : LL_LPTIM_InitTypeDef
  • WeekDay : RTC_DateTypeDef , LL_RTC_DateTypeDef
  • Window : IWDG_InitTypeDef , WWDG_InitTypeDef
  • WindowMode : COMP_InitTypeDef
  • WordLength : IRDA_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef , SMARTCARD_InitTypeDef
  • WRPArea : FLASH_OBProgramInitTypeDef
  • WRPEndOffset : FLASH_OBProgramInitTypeDef
  • WRPStartOffset : FLASH_OBProgramInitTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- x -

  • XferAbortCallback : __DMA_HandleTypeDef
  • XferCount : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef , __SAI_HandleTypeDef
  • XferCpltCallback : __DMA_HandleTypeDef
  • XferErrorCallback : __DMA_HandleTypeDef
  • XferHalfCpltCallback : __DMA_HandleTypeDef
  • XferISR : __I2C_HandleTypeDef
  • XferOptions : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • XferSize : __SAI_HandleTypeDef , __SMBUS_HandleTypeDef , __I2C_HandleTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields

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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- y -

  • Year : RTC_DateTypeDef , LL_RTC_DateTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields - Variables

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- a -

  • AbortCpltCallback : __I2C_HandleTypeDef , __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __QSPI_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • AbortReceiveCpltCallback : __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef
  • AbortTransmitCpltCallback : __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef
  • AccessPermission : MPU_Region_InitTypeDef
  • AcquisitionMode : TSC_InitTypeDef
  • Activation : SAI_PdmInitTypeDef
  • ActiveEdge : LPTIM_TriggerConfigTypeDef
  • ActiveFrameLength : SAI_FrameInitTypeDef
  • AdcClockSelection : RCC_PeriphCLKInitTypeDef
  • AddrCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • Address : FLASH_ProcessTypeDef , QSPI_CommandTypeDef , UART_WakeUpTypeDef
  • AddressingMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • AddressLength : UART_WakeUpTypeDef
  • AddressMode : QSPI_CommandTypeDef
  • AddressSize : QSPI_CommandTypeDef
  • AddrEventCount : __I2C_HandleTypeDef
  • AdvancedInit : __UART_HandleTypeDef , __SMARTCARD_HandleTypeDef
  • AdvFeatureInit : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • AHB4CLKDivider : LL_UTILS_ClkInitTypeDef
  • AHBCLK2Divider : RCC_ClkInitTypeDef
  • AHBCLK4Divider : RCC_ClkInitTypeDef
  • AHBCLKDivider : RCC_ClkInitTypeDef
  • Alarm : RTC_AlarmTypeDef
  • AlarmAEventCallback : __RTC_HandleTypeDef
  • AlarmBEventCallback : __RTC_HandleTypeDef
  • AlarmDateWeekDay : LL_RTC_AlarmTypeDef , RTC_AlarmTypeDef
  • AlarmDateWeekDaySel : RTC_AlarmTypeDef , LL_RTC_AlarmTypeDef
  • AlarmMask : LL_RTC_AlarmTypeDef , RTC_AlarmTypeDef
  • AlarmSubSecondMask : RTC_AlarmTypeDef
  • AlarmTime : RTC_AlarmTypeDef , LL_RTC_AlarmTypeDef
  • Algorithm : CRYP_ConfigTypeDef
  • Alternate : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • AlternateByteMode : QSPI_CommandTypeDef
  • AlternateBytes : QSPI_CommandTypeDef
  • AlternateBytesSize : QSPI_CommandTypeDef
  • AnalogFilter : SMBUS_InitTypeDef , LL_I2C_InitTypeDef
  • APB1CLKDivider : RCC_ClkInitTypeDef , LL_UTILS_ClkInitTypeDef
  • APB2CLKDivider : LL_UTILS_ClkInitTypeDef , RCC_ClkInitTypeDef
  • AsynchPrediv : RTC_InitTypeDef
  • AsynchPrescaler : LL_RTC_InitTypeDef
  • AudioFrequency : SAI_InitTypeDef
  • AudioMode : SAI_InitTypeDef
  • AutoBaudRateEnable : UART_AdvFeatureInitTypeDef
  • AutoBaudRateMode : UART_AdvFeatureInitTypeDef
  • AutoInjectedConv : ADC_InjectionConfTypeDef
  • AutoKeyDerivation : __CRYP_HandleTypeDef
  • AutomaticOutput : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • AutomaticStop : QSPI_AutoPollingTypeDef
  • Autoreload : LL_TIM_InitTypeDef
  • AutoReloadMatchCallback : __LPTIM_HandleTypeDef
  • AutoReloadPreload : TIM_Base_InitTypeDef
  • AutoReloadWriteCallback : __LPTIM_HandleTypeDef
  • AutoRetryCount : SMARTCARD_InitTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields - Variables

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- b -

  • B0 : CRYP_ConfigTypeDef
  • Base_MspDeInitCallback : __TIM_HandleTypeDef
  • Base_MspInitCallback : __TIM_HandleTypeDef
  • BaseAddress : MPU_Region_InitTypeDef
  • basePointX : PKA_ECDSAVerifInTypeDef , PKA_ECDSASignInTypeDef
  • basePointY : PKA_ECDSASignInTypeDef , PKA_ECDSAVerifInTypeDef
  • battery_charging_active : __PCD_HandleTypeDef
  • BaudRate : LL_USART_InitTypeDef , IRDA_InitTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef , LL_LPUART_InitTypeDef , LL_SPI_InitTypeDef
  • BaudRatePrescaler : SPI_InitTypeDef
  • BCDCallback : __PCD_HandleTypeDef
  • BESL : __PCD_HandleTypeDef
  • Bias : LCD_InitTypeDef
  • BitOrder : LL_SPI_InitTypeDef
  • BlankingSrce : COMP_InitTypeDef
  • BlinkFrequency : LCD_InitTypeDef
  • BlinkMode : LCD_InitTypeDef
  • BlockLength : SMARTCARD_InitTypeDef
  • Break2Callback : __TIM_HandleTypeDef
  • Break2Filter : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • Break2Polarity : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • Break2State : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • BreakCallback : __TIM_HandleTypeDef
  • BreakFilter : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • BreakPolarity : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • BreakState : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
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- c -

  • C2BootRegion : FLASH_OBProgramInitTypeDef
  • C2SecureBootVectAddr : FLASH_OBProgramInitTypeDef
  • callbackRequest : __IPCC_HandleTypeDef
  • Channel : ADC_ChannelConfTypeDef , ADC_AnalogWDGConfTypeDef , __TIM_HandleTypeDef
  • ChannelCallbackRx : __IPCC_HandleTypeDef
  • ChannelCallbackTx : __IPCC_HandleTypeDef
  • ChannelCount : ADC_InjectionConfigTypeDef
  • ChannelIndex : __DMA_HandleTypeDef
  • ChannelIOs : TSC_InitTypeDef , TSC_IOConfigTypeDef
  • ChipSelectHighTime : QSPI_InitTypeDef
  • ClearInputFilter : TIM_ClearInputConfigTypeDef
  • ClearInputPolarity : TIM_ClearInputConfigTypeDef
  • ClearInputPrescaler : TIM_ClearInputConfigTypeDef
  • ClearInputSource : TIM_ClearInputConfigTypeDef
  • ClearInputState : TIM_ClearInputConfigTypeDef
  • CLKLastBit : SMARTCARD_InitTypeDef , USART_InitTypeDef
  • CLKPhase : SMARTCARD_InitTypeDef , SPI_InitTypeDef , USART_InitTypeDef
  • CLKPolarity : SMARTCARD_InitTypeDef , SPI_InitTypeDef , USART_InitTypeDef
  • Clock : LPTIM_InitTypeDef
  • ClockDivision : TIM_Base_InitTypeDef , LL_TIM_InitTypeDef
  • ClockEnable : SAI_PdmInitTypeDef
  • ClockErrorDetection : LL_RNG_InitTypeDef , RNG_InitTypeDef
  • ClockFilter : TIM_ClockConfigTypeDef
  • ClockMode : QSPI_InitTypeDef
  • ClockOutput : LL_USART_ClockInitTypeDef
  • ClockPhase : LL_SPI_InitTypeDef , LL_USART_ClockInitTypeDef
  • ClockPolarity : TIM_ClockConfigTypeDef , LL_SPI_InitTypeDef , LL_USART_ClockInitTypeDef
  • ClockPrescaler : ADC_InitTypeDef , IRDA_InitTypeDef , QSPI_InitTypeDef , SMARTCARD_InitTypeDef , TIM_ClockConfigTypeDef , UART_InitTypeDef , USART_InitTypeDef
  • ClockSource : TIM_ClockConfigTypeDef , LL_LPTIM_InitTypeDef
  • ClockStrobing : SAI_InitTypeDef
  • ClockType : RCC_ClkInitTypeDef
  • CmdCpltCallback : __QSPI_HandleTypeDef
  • coef : PKA_ECDSAVerifInTypeDef , PKA_ECDSASignInTypeDef
  • coefA : PKA_ECCMulFastModeInTypeDef , PKA_ECCMulInTypeDef , PKA_PointCheckInTypeDef
  • coefB : PKA_PointCheckInTypeDef
  • coefSign : PKA_ECDSASignInTypeDef , PKA_ECCMulFastModeInTypeDef , PKA_ECCMulInTypeDef , PKA_PointCheckInTypeDef , PKA_ECDSAVerifInTypeDef
  • CommonClock : LL_ADC_CommonInitTypeDef
  • Commutation_Delay : TIM_HallSensor_InitTypeDef
  • CommutationCallback : __TIM_HandleTypeDef
  • CommutationDelay : LL_TIM_HALLSENSOR_InitTypeDef
  • CommutationHalfCpltCallback : __TIM_HandleTypeDef
  • CompandingMode : SAI_InitTypeDef
  • CompareMatchCallback : __LPTIM_HandleTypeDef
  • CompareValue : LL_TIM_OC_InitTypeDef
  • CompareWriteCallback : __LPTIM_HandleTypeDef
  • ConnectCallback : __PCD_HandleTypeDef
  • ContextQueue : ADC_InjectionConfigTypeDef
  • ContinuousConvMode : ADC_InitTypeDef
  • ContinuousMode : LL_ADC_REG_InitTypeDef
  • Contrast : LCD_InitTypeDef
  • ConvCpltCallback : __ADC_HandleTypeDef , __TSC_HandleTypeDef
  • ConvHalfCpltCallback : __ADC_HandleTypeDef
  • Counter : WWDG_InitTypeDef
  • CounterMode : LL_TIM_InitTypeDef , TIM_Base_InitTypeDef
  • CounterSource : LPTIM_InitTypeDef
  • CPU1CLKDivider : LL_UTILS_ClkInitTypeDef
  • CPU2CLKDivider : LL_UTILS_ClkInitTypeDef
  • CRCCalculation : SPI_InitTypeDef , LL_SPI_InitTypeDef
  • CRCLength : CRC_InitTypeDef , SPI_InitTypeDef
  • CRCPoly : LL_SPI_InitTypeDef
  • CRCPolynomial : SPI_InitTypeDef
  • CRCSize : __SPI_HandleTypeDef
  • CrypHeaderCount : __CRYP_HandleTypeDef
  • CrypInCount : __CRYP_HandleTypeDef
  • CrypOutCount : __CRYP_HandleTypeDef
  • CTPulseHighLength : TSC_InitTypeDef
  • CTPulseLowLength : TSC_InitTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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- d -

  • DataAlign : ADC_InitTypeDef
  • DataAlignment : LL_ADC_InitTypeDef
  • DataInStageCallback : __PCD_HandleTypeDef
  • DataInvert : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • DataMode : QSPI_CommandTypeDef
  • DataOutStageCallback : __PCD_HandleTypeDef
  • DataSize : SAI_InitTypeDef , SPI_InitTypeDef
  • DataType : CRYP_ConfigTypeDef
  • DataWidth : LL_LPUART_InitTypeDef , LL_SPI_InitTypeDef , LL_USART_InitTypeDef
  • DataWidthUnit : CRYP_ConfigTypeDef
  • Date : RTC_DateTypeDef
  • Day : LL_RTC_DateTypeDef
  • DayLightSaving : RTC_TimeTypeDef
  • DdrMode : QSPI_CommandTypeDef
  • DeadTime : LCD_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • DefaultInitValueUse : CRC_InitTypeDef
  • DefaultPolynomialUse : CRC_InitTypeDef
  • DigitalFilter : LL_I2C_InitTypeDef
  • Direction : LL_DMA_InitTypeDef , DMA_InitTypeDef , SPI_InitTypeDef
  • DirectionDownCallback : __LPTIM_HandleTypeDef
  • DirectionUpCallback : __LPTIM_HandleTypeDef
  • DisableExec : MPU_Region_InitTypeDef
  • DisconnectCallback : __PCD_HandleTypeDef
  • DiscontinuousConvMode : ADC_InitTypeDef
  • Divider : LCD_InitTypeDef
  • DMA_Handle : __ADC_HandleTypeDef
  • DmaBaseAddress : __DMA_HandleTypeDef
  • DMAContinuousRequests : ADC_InitTypeDef
  • DMADisableonRxError : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • DMAmuxChannel : __DMA_HandleTypeDef
  • DMAmuxChannelStatus : __DMA_HandleTypeDef
  • DMAmuxChannelStatusMask : __DMA_HandleTypeDef
  • DMAmuxRequestGen : __DMA_HandleTypeDef
  • DMAmuxRequestGenStatus : __DMA_HandleTypeDef
  • DMAmuxRequestGenStatusMask : __DMA_HandleTypeDef
  • DMATransfer : LL_ADC_REG_InitTypeDef
  • DualAddressMode : SMBUS_InitTypeDef , I2C_InitTypeDef
  • DummyCycles : QSPI_CommandTypeDef
  • Duty : LCD_InitTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
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  • Enable : MPU_Region_InitTypeDef , TIMEx_BreakInputConfigTypeDef
  • Encoder_MspDeInitCallback : __TIM_HandleTypeDef
  • Encoder_MspInitCallback : __TIM_HandleTypeDef
  • EncoderMode : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • EndOfSamplingCallback : __ADC_HandleTypeDef
  • EOCSelection : ADC_InitTypeDef
  • ErrorCallback : __SAI_HandleTypeDef , __SMARTCARD_HandleTypeDef , __ADC_HandleTypeDef , __SMBUS_HandleTypeDef , __SPI_HandleTypeDef , __CRYP_HandleTypeDef , __TIM_HandleTypeDef , __TSC_HandleTypeDef , __I2C_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef , __IRDA_HandleTypeDef , __PKA_HandleTypeDef , __QSPI_HandleTypeDef , __RNG_HandleTypeDef
  • ErrorCode : __RNG_HandleTypeDef , __USART_HandleTypeDef , __PCD_HandleTypeDef , __DMA_HandleTypeDef , __PKA_HandleTypeDef , __QSPI_HandleTypeDef , __SAI_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SMBUS_HandleTypeDef , __TSC_HandleTypeDef , __UART_HandleTypeDef , __SPI_HandleTypeDef , LCD_HandleTypeDef , __ADC_HandleTypeDef , __COMP_HandleTypeDef , __IRDA_HandleTypeDef , __I2C_HandleTypeDef , __CRYP_HandleTypeDef , FLASH_ProcessTypeDef
  • ErrorLimitValue : RCC_CRSInitTypeDef
  • EventEnable : HAL_DMA_MuxSyncConfigTypeDef
  • EwiCallback : __WWDG_HandleTypeDef
  • EWIMode : WWDG_InitTypeDef
  • expSize : PKA_ModExpFastModeInTypeDef , PKA_ModExpInTypeDef
  • ExternalTrigConv : ADC_InitTypeDef
  • ExternalTrigConvEdge : ADC_InitTypeDef
  • ExternalTrigInjecConv : ADC_InjectionConfTypeDef
  • ExternalTrigInjecConvEdge : ADC_InjectionConfTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
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- f -

  • FifoMode : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • FifoThreshold : QSPI_InitTypeDef
  • FIFOThreshold : SAI_InitTypeDef
  • FifoThresholdCallback : __QSPI_HandleTypeDef
  • Filter : RTC_TamperTypeDef
  • FirstBit : SAI_InitTypeDef , SPI_InitTypeDef
  • FirstBitOffset : SAI_SlotInitTypeDef
  • FlashSize : QSPI_InitTypeDef
  • FrameInit : __SAI_HandleTypeDef
  • FrameLength : SAI_FrameInitTypeDef
  • FreqErrorCapture : RCC_CRSSynchroInfoTypeDef
  • FreqErrorDirection : RCC_CRSSynchroInfoTypeDef
  • FSDefinition : SAI_FrameInitTypeDef
  • FSOffset : SAI_FrameInitTypeDef
  • FSPolarity : SAI_FrameInitTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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  • GeneralCallMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • GeneratingPolynomial : CRC_InitTypeDef
  • GPIOSel : EXTI_ConfigTypeDef
  • gState : __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef
  • GuardTime : SMARTCARD_InitTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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- h -

  • HallSensor_MspDeInitCallback : __TIM_HandleTypeDef
  • HallSensor_MspInitCallback : __TIM_HandleTypeDef
  • HardwareFlowControl : LL_USART_InitTypeDef , LL_LPUART_InitTypeDef
  • hash : PKA_ECDSAVerifInTypeDef , PKA_ECDSASignInTypeDef
  • HCLK1_Frequency : LL_RCC_ClocksTypeDef
  • HCLK2_Frequency : LL_RCC_ClocksTypeDef
  • HCLK4_Frequency : LL_RCC_ClocksTypeDef
  • HCLK5_Frequency : LL_RCC_ClocksTypeDef
  • hdma : __QSPI_HandleTypeDef , __TIM_HandleTypeDef
  • hdmain : __CRYP_HandleTypeDef
  • hdmaout : __CRYP_HandleTypeDef
  • hdmarx : __IRDA_HandleTypeDef , __SAI_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef , __I2C_HandleTypeDef
  • hdmatx : __UART_HandleTypeDef , __I2C_HandleTypeDef , __IRDA_HandleTypeDef , __SAI_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __USART_HandleTypeDef
  • Header : CRYP_ConfigTypeDef
  • HeaderSize : CRYP_ConfigTypeDef
  • HighDrive : LCD_InitTypeDef
  • HighThreshold : ADC_AnalogWDGConfTypeDef
  • HourFormat : RTC_InitTypeDef , LL_RTC_InitTypeDef
  • Hours : LL_RTC_TimeTypeDef , RTC_TimeTypeDef
  • HSEState : RCC_OscInitTypeDef
  • HSI48CalibrationValue : RCC_CRSSynchroInfoTypeDef , RCC_CRSInitTypeDef
  • HSI48State : RCC_OscInitTypeDef
  • HSICalibrationValue : RCC_OscInitTypeDef
  • HSIState : RCC_OscInitTypeDef
  • HwFlowCtl : UART_InitTypeDef
  • Hysteresis : COMP_InitTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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- i -

  • I2c1ClockSelection : RCC_PeriphCLKInitTypeDef
  • I2c3ClockSelection : RCC_PeriphCLKInitTypeDef
  • IC1ActiveInput : LL_TIM_ENCODER_InitTypeDef
  • IC1Filter : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef , LL_TIM_ENCODER_InitTypeDef , LL_TIM_HALLSENSOR_InitTypeDef
  • IC1Polarity : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef , LL_TIM_ENCODER_InitTypeDef , LL_TIM_HALLSENSOR_InitTypeDef
  • IC1Prescaler : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef , LL_TIM_ENCODER_InitTypeDef , LL_TIM_HALLSENSOR_InitTypeDef
  • IC1Selection : TIM_Encoder_InitTypeDef
  • IC2ActiveInput : LL_TIM_ENCODER_InitTypeDef
  • IC2Filter : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Polarity : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Prescaler : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Selection : TIM_Encoder_InitTypeDef
  • IC_CaptureCallback : __TIM_HandleTypeDef
  • IC_CaptureHalfCpltCallback : __TIM_HandleTypeDef
  • IC_MspDeInitCallback : __TIM_HandleTypeDef
  • IC_MspInitCallback : __TIM_HandleTypeDef
  • ICActiveInput : LL_TIM_IC_InitTypeDef
  • ICFilter : LL_TIM_IC_InitTypeDef , TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef
  • ICPolarity : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef , LL_TIM_IC_InitTypeDef
  • ICPrescaler : TIM_IC_InitTypeDef , LL_TIM_IC_InitTypeDef
  • ICSelection : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef
  • IN_ep : __PCD_HandleTypeDef
  • InCpltCallback : __CRYP_HandleTypeDef
  • Init : __WWDG_HandleTypeDef , __ADC_HandleTypeDef , __COMP_HandleTypeDef , CRC_HandleTypeDef , __CRYP_HandleTypeDef , __DMA_HandleTypeDef , __I2C_HandleTypeDef , __IRDA_HandleTypeDef , IWDG_HandleTypeDef , LCD_HandleTypeDef , __LPTIM_HandleTypeDef , __PCD_HandleTypeDef , __QSPI_HandleTypeDef , __RNG_HandleTypeDef , __RTC_HandleTypeDef , __SAI_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SMBUS_HandleTypeDef , __SPI_HandleTypeDef , __TIM_HandleTypeDef , __TSC_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • InitValue : CRC_InitTypeDef
  • InjecOversampling : ADC_InjectionConfTypeDef
  • InjecOversamplingMode : ADC_InjectionConfTypeDef
  • InjectedChannel : ADC_InjectionConfTypeDef
  • InjectedConvCpltCallback : __ADC_HandleTypeDef
  • InjectedDiscontinuousConvMode : ADC_InjectionConfTypeDef
  • InjectedNbrOfConversion : ADC_InjectionConfTypeDef
  • InjectedOffset : ADC_InjectionConfTypeDef
  • InjectedOffsetNumber : ADC_InjectionConfTypeDef
  • InjectedQueueOverflowCallback : __ADC_HandleTypeDef
  • InjectedRank : ADC_InjectionConfTypeDef
  • InjectedSamplingTime : ADC_InjectionConfTypeDef
  • InjectedSingleDiff : ADC_InjectionConfTypeDef
  • InjectionConfig : __ADC_HandleTypeDef
  • Input1Source : LPTIM_InitTypeDef
  • Input2Source : LPTIM_InitTypeDef
  • InputDataFormat : CRC_HandleTypeDef
  • InputDataInversionMode : CRC_InitTypeDef
  • InputHysteresis : LL_COMP_InitTypeDef
  • InputMinus : COMP_InitTypeDef , LL_COMP_InitTypeDef
  • InputPlus : LL_COMP_InitTypeDef , COMP_InitTypeDef
  • InputTrigger : TIM_SlaveConfigTypeDef
  • Instance : __SMBUS_HandleTypeDef , __UART_HandleTypeDef , CRC_HandleTypeDef , __LPTIM_HandleTypeDef , __CRYP_HandleTypeDef , __DMA_HandleTypeDef , IWDG_HandleTypeDef , __TSC_HandleTypeDef , __SPI_HandleTypeDef , __PKA_HandleTypeDef , __ADC_HandleTypeDef , __IPCC_HandleTypeDef , __COMP_HandleTypeDef , __WWDG_HandleTypeDef , __RTC_HandleTypeDef , __PCD_HandleTypeDef , LCD_HandleTypeDef , __TIM_HandleTypeDef , __SAI_HandleTypeDef , __RNG_HandleTypeDef , __IRDA_HandleTypeDef , __I2C_HandleTypeDef , __USART_HandleTypeDef , __QSPI_HandleTypeDef , __SMARTCARD_HandleTypeDef
  • Instruction : QSPI_CommandTypeDef
  • InstructionMode : QSPI_CommandTypeDef
  • integer : PKA_ECDSASignInTypeDef
  • Interrupt : RTC_TamperTypeDef
  • InterruptServiceRoutine : __SAI_HandleTypeDef
  • Interval : QSPI_AutoPollingTypeDef
  • IODefaultMode : TSC_InitTypeDef
  • IPCCdataBufAddr : FLASH_OBProgramInitTypeDef
  • IsBufferable : MPU_Region_InitTypeDef
  • IsCacheable : MPU_Region_InitTypeDef
  • ISOINIncompleteCallback : __PCD_HandleTypeDef
  • ISOOUTIncompleteCallback : __PCD_HandleTypeDef
  • IsShareable : MPU_Region_InitTypeDef
  • ITMode : ADC_AnalogWDGConfTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
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- k -

  • KeyIVConfig : __CRYP_HandleTypeDef
  • KeyIVConfigSkip : CRYP_ConfigTypeDef
  • KeySize : CRYP_ConfigTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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  • Variables
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- l -

  • LastBitClockPulse : LL_USART_ClockInitTypeDef
  • LeftDelay : SAIEx_PdmMicDelayParamTypeDef
  • LevelOutOfWindow2Callback : __ADC_HandleTypeDef
  • LevelOutOfWindow3Callback : __ADC_HandleTypeDef
  • LevelOutOfWindowCallback : __ADC_HandleTypeDef
  • Line : EXTI_HandleTypeDef , EXTI_ConfigTypeDef
  • Line_0_31 : LL_EXTI_InitTypeDef
  • Line_32_63 : LL_EXTI_InitTypeDef
  • LineCommand : LL_EXTI_InitTypeDef
  • ListenCpltCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • Lock : __CRYP_HandleTypeDef , __TSC_HandleTypeDef , __UART_HandleTypeDef , __DMA_HandleTypeDef , __USART_HandleTypeDef , FLASH_ProcessTypeDef , __TIM_HandleTypeDef , __SPI_HandleTypeDef , __SMBUS_HandleTypeDef , __I2C_HandleTypeDef , __SAI_HandleTypeDef , __RTC_HandleTypeDef , __IRDA_HandleTypeDef , LCD_HandleTypeDef , __LPTIM_HandleTypeDef , __PCD_HandleTypeDef , __QSPI_HandleTypeDef , __RNG_HandleTypeDef , __ADC_HandleTypeDef , __COMP_HandleTypeDef , __SMARTCARD_HandleTypeDef , CRC_HandleTypeDef
  • LockLevel : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • LowPowerAutoWait : ADC_InitTypeDef
  • LowPowerMode : LL_ADC_InitTypeDef
  • LowThreshold : ADC_AnalogWDGConfTypeDef
  • lpm_active : __PCD_HandleTypeDef
  • LPM_State : __PCD_HandleTypeDef
  • LPMCallback : __PCD_HandleTypeDef
  • Lptim1ClockSelection : RCC_PeriphCLKInitTypeDef
  • Lptim2ClockSelection : RCC_PeriphCLKInitTypeDef
  • Lpuart1ClockSelection : RCC_PeriphCLKInitTypeDef
  • LSEState : RCC_OscInitTypeDef
  • LSI2CalibrationValue : RCC_OscInitTypeDef
  • LSIState : RCC_OscInitTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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- m -

  • Mask : __IRDA_HandleTypeDef , QSPI_AutoPollingTypeDef , __USART_HandleTypeDef , __UART_HandleTypeDef
  • MaskFlag : RTC_TamperTypeDef
  • MasterOutputTrigger : TIM_MasterConfigTypeDef
  • MasterOutputTrigger2 : TIM_MasterConfigTypeDef
  • MasterRxCpltCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • MasterSlaveMode : TIM_MasterConfigTypeDef
  • MasterTxCpltCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • Match : QSPI_AutoPollingTypeDef
  • MatchMode : QSPI_AutoPollingTypeDef
  • MaxCountInterrupt : TSC_InitTypeDef
  • MaxCountValue : TSC_InitTypeDef
  • Mckdiv : SAI_InitTypeDef
  • MckOutput : SAI_InitTypeDef
  • MckOverSampling : SAI_InitTypeDef
  • MemDataAlignment : DMA_InitTypeDef
  • MemInc : DMA_InitTypeDef
  • MemoryOrM2MDstAddress : LL_DMA_InitTypeDef
  • MemoryOrM2MDstDataSize : LL_DMA_InitTypeDef
  • MemoryOrM2MDstIncMode : LL_DMA_InitTypeDef
  • MemRxCpltCallback : __I2C_HandleTypeDef
  • MemTxCpltCallback : __I2C_HandleTypeDef
  • MicPair : SAIEx_PdmMicDelayParamTypeDef
  • MicPairsNbr : SAI_PdmInitTypeDef
  • Minutes : RTC_TimeTypeDef , LL_RTC_TimeTypeDef
  • Mode : DMA_InitTypeDef , EXTI_ConfigTypeDef , GPIO_InitTypeDef , __I2C_HandleTypeDef , IRDA_InitTypeDef , PWR_PVDTypeDef , PWR_PVMTypeDef , SMARTCARD_InitTypeDef , SPI_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef , LL_DMA_InitTypeDef , LL_EXTI_InitTypeDef , LL_GPIO_InitTypeDef , LL_PKA_InitTypeDef , LL_SPI_InitTypeDef , COMP_InitTypeDef
  • modSize : PKA_ModRedInTypeDef
  • modulus : PKA_ECCMulFastModeInTypeDef , PKA_ECCMulInTypeDef , PKA_PointCheckInTypeDef , PKA_ECDSAVerifInTypeDef , PKA_ECDSASignInTypeDef
  • modulusSize : PKA_ECCMulFastModeInTypeDef , PKA_ECCMulInTypeDef , PKA_PointCheckInTypeDef , PKA_ECDSAVerifInTypeDef , PKA_ECDSASignInTypeDef
  • MonoStereoMode : SAI_InitTypeDef
  • Month : RTC_DateTypeDef , LL_RTC_DateTypeDef
  • MSBFirst : UART_AdvFeatureInitTypeDef , SMARTCARD_AdvFeatureInitTypeDef
  • MSICalibrationValue : RCC_OscInitTypeDef
  • MSIClockRange : RCC_OscInitTypeDef
  • MSIState : RCC_OscInitTypeDef
  • MspDeInitCallback : __TSC_HandleTypeDef , __QSPI_HandleTypeDef , __ADC_HandleTypeDef , __PKA_HandleTypeDef , __PCD_HandleTypeDef , __COMP_HandleTypeDef , __CRYP_HandleTypeDef , __I2C_HandleTypeDef , __IRDA_HandleTypeDef , __LPTIM_HandleTypeDef , __RNG_HandleTypeDef , __SAI_HandleTypeDef , __SMBUS_HandleTypeDef , __SPI_HandleTypeDef , __USART_HandleTypeDef , __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __RTC_HandleTypeDef
  • MspInitCallback : __SAI_HandleTypeDef , __QSPI_HandleTypeDef , __WWDG_HandleTypeDef , __PCD_HandleTypeDef , __SMARTCARD_HandleTypeDef , __LPTIM_HandleTypeDef , __SPI_HandleTypeDef , __IRDA_HandleTypeDef , __RNG_HandleTypeDef , __PKA_HandleTypeDef , __I2C_HandleTypeDef , __UART_HandleTypeDef , __RTC_HandleTypeDef , __USART_HandleTypeDef , __COMP_HandleTypeDef , __ADC_HandleTypeDef , __SMBUS_HandleTypeDef , __TSC_HandleTypeDef , __CRYP_HandleTypeDef
  • mutecallback : __SAI_HandleTypeDef
  • MuxSegment : LCD_InitTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields - Variables

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  • NACKEnable : SMARTCARD_InitTypeDef
  • NbData : QSPI_CommandTypeDef , LL_DMA_InitTypeDef
  • NbPages : FLASH_EraseInitTypeDef
  • NbPagesToErase : FLASH_ProcessTypeDef
  • NbrOfConversion : ADC_InitTypeDef
  • NbrOfDiscConversion : ADC_InitTypeDef
  • NbRxDataToProcess : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • NbTxDataToProcess : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • NoDivider : SAI_InitTypeDef
  • NoErase : RTC_TamperTypeDef
  • NoStretchMode : I2C_InitTypeDef , SMBUS_InitTypeDef
  • NSS : LL_SPI_InitTypeDef , SPI_InitTypeDef
  • NSSPMode : SPI_InitTypeDef
  • Number : MPU_Region_InitTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields - Variables

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  • OC_DelayElapsedCallback : __TIM_HandleTypeDef
  • OC_MspDeInitCallback : __TIM_HandleTypeDef
  • OC_MspInitCallback : __TIM_HandleTypeDef
  • OCFastMode : TIM_OC_InitTypeDef
  • OCIdleState : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCMode : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCNIdleState : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCNPolarity : LL_TIM_OC_InitTypeDef , TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OCNState : LL_TIM_OC_InitTypeDef
  • OCPolarity : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCState : LL_TIM_OC_InitTypeDef
  • Offset : ADC_ChannelConfTypeDef
  • OffsetNumber : ADC_ChannelConfTypeDef
  • OffStateIDLEMode : TIM_BreakDeadTimeConfigTypeDef
  • OffStateRunMode : TIM_BreakDeadTimeConfigTypeDef
  • OneBitSampling : SMARTCARD_InitTypeDef , UART_InitTypeDef
  • OnePulse_MspDeInitCallback : __TIM_HandleTypeDef
  • OnePulse_MspInitCallback : __TIM_HandleTypeDef
  • OperationCpltCallback : __PKA_HandleTypeDef
  • OpSize : PKA_ModExpFastModeInTypeDef , PKA_ModRedInTypeDef , PKA_ModExpInTypeDef
  • OptionType : FLASH_OBProgramInitTypeDef
  • OscillatorType : RCC_OscInitTypeDef
  • OSSIState : LL_TIM_BDTR_InitTypeDef
  • OSSRState : LL_TIM_BDTR_InitTypeDef
  • OUT_ep : __PCD_HandleTypeDef
  • OutCpltCallback : __CRYP_HandleTypeDef
  • OutPut : RTC_InitTypeDef
  • OutputBlankingSource : LL_COMP_InitTypeDef
  • OutputDataInversionMode : CRC_InitTypeDef
  • OutputDrive : SAI_InitTypeDef
  • OutputPol : COMP_InitTypeDef
  • OutputPolarity : LL_COMP_InitTypeDef
  • OutPutPolarity : RTC_InitTypeDef
  • OutputPolarity : LPTIM_InitTypeDef
  • OutPutRemap : RTC_InitTypeDef
  • OutputType : LL_GPIO_InitTypeDef
  • OutPutType : RTC_InitTypeDef
  • OutputVoltage : PWR_SMPSTypeDef
  • Overrun : ADC_InitTypeDef , LL_ADC_REG_InitTypeDef
  • OverrunDisable : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • OverSampling : UART_InitTypeDef
  • Oversampling : ADC_InitTypeDef
  • OverSampling : LL_USART_InitTypeDef
  • OversamplingMode : ADC_InitTypeDef
  • OversamplingStopReset : ADC_OversamplingTypeDef
  • OwnAddress1 : LL_I2C_InitTypeDef , SMBUS_InitTypeDef , I2C_InitTypeDef
  • OwnAddress2 : I2C_InitTypeDef , SMBUS_InitTypeDef
  • OwnAddress2Masks : SMBUS_InitTypeDef , I2C_InitTypeDef
  • OwnAddrSize : LL_I2C_InitTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields - Variables

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  • PacketErrorCheckMode : SMBUS_InitTypeDef
  • Page : FLASH_EraseInitTypeDef , FLASH_ProcessTypeDef
  • Parent : __DMA_HandleTypeDef
  • Parity : USART_InitTypeDef , LL_LPUART_InitTypeDef , IRDA_InitTypeDef , LL_USART_InitTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef
  • pBuffPtr : __I2C_HandleTypeDef , __SAI_HandleTypeDef , __SMBUS_HandleTypeDef
  • PCLK1_Frequency : LL_RCC_ClocksTypeDef
  • PCLK2_Frequency : LL_RCC_ClocksTypeDef
  • PCROP1AEndAddr : FLASH_OBProgramInitTypeDef
  • PCROP1AStartAddr : FLASH_OBProgramInitTypeDef
  • PCROP1BEndAddr : FLASH_OBProgramInitTypeDef
  • PCROP1BStartAddr : FLASH_OBProgramInitTypeDef
  • PCROPConfig : FLASH_OBProgramInitTypeDef
  • pCrypInBuffPtr : __CRYP_HandleTypeDef
  • pCrypOutBuffPtr : __CRYP_HandleTypeDef
  • pData : __PCD_HandleTypeDef
  • PdmInit : SAI_InitTypeDef
  • PendingCallback : EXTI_HandleTypeDef
  • Period : TIM_Base_InitTypeDef
  • PeriodElapsedCallback : __TIM_HandleTypeDef
  • PeriodElapsedHalfCpltCallback : __TIM_HandleTypeDef
  • PeriphClockSelection : RCC_PeriphCLKInitTypeDef
  • PeriphDataAlignment : DMA_InitTypeDef
  • PeripheralMode : LL_I2C_InitTypeDef , SMBUS_InitTypeDef
  • PeriphInc : DMA_InitTypeDef
  • PeriphOrM2MSrcAddress : LL_DMA_InitTypeDef
  • PeriphOrM2MSrcDataSize : LL_DMA_InitTypeDef
  • PeriphOrM2MSrcIncMode : LL_DMA_InitTypeDef
  • PeriphRequest : LL_DMA_InitTypeDef
  • pExp : PKA_ModExpInTypeDef , PKA_ModExpFastModeInTypeDef
  • Phase : __CRYP_HandleTypeDef
  • Pin : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • pInitVect : CRYP_ConfigTypeDef
  • pKey : CRYP_ConfigTypeDef
  • PLL : RCC_OscInitTypeDef
  • PLLM : RCC_PLLInitTypeDef , LL_UTILS_PLLInitTypeDef
  • PLLN : RCC_PLLInitTypeDef , RCC_PLLSAI1InitTypeDef , LL_UTILS_PLLInitTypeDef
  • PLLP : RCC_PLLInitTypeDef , RCC_PLLSAI1InitTypeDef
  • PLLQ : RCC_PLLInitTypeDef , RCC_PLLSAI1InitTypeDef
  • PLLR : RCC_PLLInitTypeDef , RCC_PLLSAI1InitTypeDef , LL_UTILS_PLLInitTypeDef
  • PLLSAI1 : RCC_PeriphCLKInitTypeDef
  • PLLSAI1ClockOut : RCC_PLLSAI1InitTypeDef
  • PLLSource : RCC_PLLInitTypeDef
  • PLLState : RCC_PLLInitTypeDef
  • pMod : PKA_ModInvInTypeDef , PKA_ModRedInTypeDef , PKA_ModExpInTypeDef , PKA_ModExpFastModeInTypeDef
  • pMontgomeryParam : PKA_ECCMulFastModeInTypeDef , PKA_ModExpFastModeInTypeDef
  • pointX : PKA_ECCMulFastModeInTypeDef , PKA_ECCMulInTypeDef , PKA_PointCheckInTypeDef
  • pointY : PKA_ECCMulFastModeInTypeDef , PKA_ECCMulInTypeDef , PKA_PointCheckInTypeDef
  • Polarity : HAL_DMA_MuxRequestGeneratorConfigTypeDef , LPTIM_ULPClockConfigTypeDef , RCC_CRSInitTypeDef , TIMEx_BreakInputConfigTypeDef , LL_LPTIM_InitTypeDef
  • pOp1 : PKA_ModExpInTypeDef , PKA_ModExpFastModeInTypeDef , PKA_MontgomeryParamInTypeDef , PKA_AddInTypeDef , PKA_ModInvInTypeDef , PKA_ModRedInTypeDef , PKA_ModAddInTypeDef
  • pOp2 : PKA_ModAddInTypeDef , PKA_AddInTypeDef
  • pOp3 : PKA_ModAddInTypeDef
  • popA : PKA_RSACRTExpInTypeDef
  • pOpDp : PKA_RSACRTExpInTypeDef
  • pOpDq : PKA_RSACRTExpInTypeDef
  • pOpQinv : PKA_RSACRTExpInTypeDef
  • PowerMode : IRDA_InitTypeDef , LL_COMP_InitTypeDef
  • pPrimeP : PKA_RSACRTExpInTypeDef
  • pPrimeQ : PKA_RSACRTExpInTypeDef
  • pPubKeyCurvePtX : PKA_ECDSAVerifInTypeDef
  • pPubKeyCurvePtY : PKA_ECDSAVerifInTypeDef
  • PrechargeDuration : RTC_TamperTypeDef
  • Prescaler : LPTIM_ClockConfigTypeDef , LL_TIM_InitTypeDef , SMARTCARD_InitTypeDef , IRDA_InitTypeDef , IWDG_InitTypeDef , LCD_InitTypeDef , TIM_Base_InitTypeDef , RCC_CRSInitTypeDef , LL_LPTIM_InitTypeDef , WWDG_InitTypeDef
  • PrescalerValue : LL_LPUART_InitTypeDef , LL_USART_InitTypeDef
  • PreviousState : __SMBUS_HandleTypeDef , __I2C_HandleTypeDef
  • primeOrder : PKA_ECDSASignInTypeDef , PKA_ECDSAVerifInTypeDef
  • primeOrderSize : PKA_ECDSASignInTypeDef , PKA_ECDSAVerifInTypeDef
  • Priority : LL_DMA_InitTypeDef , DMA_InitTypeDef
  • privateKey : PKA_ECDSASignInTypeDef
  • ProcedureOnGoing : FLASH_ProcessTypeDef
  • Protocol : SAI_InitTypeDef
  • pRxBuffPtr : __USART_HandleTypeDef , __UART_HandleTypeDef , __IRDA_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __QSPI_HandleTypeDef
  • ptX : PKA_ECDSASignOutExtParamTypeDef
  • pTxBuffPtr : __IRDA_HandleTypeDef , __QSPI_HandleTypeDef , __SPI_HandleTypeDef , __USART_HandleTypeDef , __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef
  • ptY : PKA_ECDSASignOutExtParamTypeDef
  • Pull : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • Pulse : TIM_OnePulse_InitTypeDef , TIM_OC_InitTypeDef
  • PulseGeneratorPrescaler : TSC_InitTypeDef
  • PulseOnDuration : LCD_InitTypeDef
  • PVDLevel : PWR_PVDTypeDef
  • PVMType : PWR_PVMTypeDef
  • PWM_MspDeInitCallback : __TIM_HandleTypeDef
  • PWM_MspInitCallback : __TIM_HandleTypeDef
  • PWM_PulseFinishedCallback : __TIM_HandleTypeDef
  • PWM_PulseFinishedHalfCpltCallback : __TIM_HandleTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields - Variables

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  • QueueInjectedContext : ADC_InjectionConfTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
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  • RandomNumber : __RNG_HandleTypeDef
  • Rank : ADC_ChannelConfTypeDef
  • Ratio : ADC_InjOversamplingTypeDef , ADC_OversamplingTypeDef
  • RDPLevel : FLASH_OBProgramInitTypeDef
  • ReadyDataCallback : __RNG_HandleTypeDef
  • Reload : IWDG_InitTypeDef
  • ReloadValue : RCC_CRSInitTypeDef , RCC_CRSSynchroInfoTypeDef
  • RepetitionCounter : TIM_Base_InitTypeDef , LL_TIM_InitTypeDef
  • Request : DMA_InitTypeDef
  • RequestNumber : HAL_DMA_MuxSyncConfigTypeDef , HAL_DMA_MuxRequestGeneratorConfigTypeDef
  • ResetCallback : __PCD_HandleTypeDef
  • Resolution : ADC_InitTypeDef , LL_ADC_InitTypeDef
  • ResumeCallback : __PCD_HandleTypeDef
  • RFWakeUpClockSelection : RCC_PeriphCLKInitTypeDef
  • RightBitShift : ADC_OversamplingTypeDef , ADC_InjOversamplingTypeDef
  • RightDelay : SAIEx_PdmMicDelayParamTypeDef
  • RngClockSelection : RCC_PeriphCLKInitTypeDef
  • RSign : PKA_ECDSAVerifInTypeDef , PKA_ECDSASignOutTypeDef
  • RTCClockSelection : RCC_PeriphCLKInitTypeDef
  • RxCpltCallback : __UART_HandleTypeDef , __USART_HandleTypeDef , __IRDA_HandleTypeDef , __QSPI_HandleTypeDef , __SAI_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef
  • RxFifoFullCallback : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • RxHalfCpltCallback : __IRDA_HandleTypeDef , __QSPI_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef , __SAI_HandleTypeDef
  • RxISR : __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • RxPinLevelInvert : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • RxState : __SMARTCARD_HandleTypeDef , __IRDA_HandleTypeDef , __UART_HandleTypeDef
  • RxXferCount : __SMARTCARD_HandleTypeDef , __QSPI_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __IRDA_HandleTypeDef , __USART_HandleTypeDef
  • RxXferSize : __USART_HandleTypeDef , __UART_HandleTypeDef , __SMARTCARD_HandleTypeDef , __IRDA_HandleTypeDef , __SPI_HandleTypeDef , __QSPI_HandleTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields - Variables

  • Data Structure Index
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  • Sai1ClockSelection : RCC_PeriphCLKInitTypeDef
  • SampleShifting : QSPI_InitTypeDef
  • SampleTime : LPTIM_TriggerConfigTypeDef , LPTIM_ULPClockConfigTypeDef
  • SamplingFrequency : RTC_TamperTypeDef
  • SamplingIOs : TSC_InitTypeDef , TSC_IOConfigTypeDef
  • SamplingTime : ADC_ChannelConfTypeDef
  • scalarMul : PKA_ECCMulFastModeInTypeDef , PKA_ECCMulInTypeDef
  • scalarMulSize : PKA_ECCMulFastModeInTypeDef , PKA_ECCMulInTypeDef
  • ScanConvMode : ADC_InitTypeDef
  • SecondFraction : RTC_TimeTypeDef
  • Seconds : LL_RTC_TimeTypeDef , RTC_TimeTypeDef
  • SecureFlashStartAddr : FLASH_OBProgramInitTypeDef
  • SecureMode : FLASH_OBProgramInitTypeDef
  • SecureRAM2aStartAddr : FLASH_OBProgramInitTypeDef
  • SecureRAM2bStartAddr : FLASH_OBProgramInitTypeDef
  • SequencerDiscont : LL_ADC_REG_InitTypeDef , LL_ADC_INJ_InitTypeDef
  • SequencerLength : LL_ADC_REG_InitTypeDef , LL_ADC_INJ_InitTypeDef
  • Setup : __PCD_HandleTypeDef
  • SetupStageCallback : __PCD_HandleTypeDef
  • ShieldIOs : TSC_InitTypeDef , TSC_IOConfigTypeDef
  • SignalID : HAL_DMA_MuxRequestGeneratorConfigTypeDef
  • SingleDiff : ADC_ChannelConfTypeDef
  • SIOOMode : QSPI_CommandTypeDef
  • size : PKA_RSACRTExpInTypeDef , PKA_MontgomeryParamInTypeDef , PKA_AddInTypeDef , PKA_ModInvInTypeDef , PKA_ModAddInTypeDef
  • Size : MPU_Region_InitTypeDef , __CRYP_HandleTypeDef
  • SizesSum : __CRYP_HandleTypeDef
  • SlaveMode : TIM_SlaveConfigTypeDef , __USART_HandleTypeDef
  • SlaveRxCpltCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • SlaveTxCpltCallback : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • SlotActive : SAI_SlotInitTypeDef
  • SlotInit : __SAI_HandleTypeDef
  • SlotNumber : SAI_SlotInitTypeDef
  • SlotSize : SAI_SlotInitTypeDef
  • SMBusTimeout : SMBUS_InitTypeDef
  • SmpsClockSelection : RCC_PeriphCLKInitTypeDef
  • SmpsDivSelection : RCC_PeriphCLKInitTypeDef
  • SOFCallback : __PCD_HandleTypeDef
  • Source : LPTIM_ClockConfigTypeDef , LPTIM_TriggerConfigTypeDef , RCC_CRSInitTypeDef , TIMEx_BreakInputConfigTypeDef
  • Speed : LL_GPIO_InitTypeDef , GPIO_InitTypeDef
  • SpreadSpectrum : TSC_InitTypeDef
  • SpreadSpectrumDeviation : TSC_InitTypeDef
  • SpreadSpectrumPrescaler : TSC_InitTypeDef
  • SSign : PKA_ECDSASignOutTypeDef , PKA_ECDSAVerifInTypeDef
  • StartupCurrent : PWR_SMPSTypeDef
  • State : __RNG_HandleTypeDef , __ADC_HandleTypeDef , __RTC_HandleTypeDef , __TSC_HandleTypeDef , CRC_HandleTypeDef , __DMA_HandleTypeDef , __QSPI_HandleTypeDef , __PKA_HandleTypeDef , __IPCC_HandleTypeDef , LCD_HandleTypeDef , __LPTIM_HandleTypeDef , __PCD_HandleTypeDef , __SAI_HandleTypeDef , __SMBUS_HandleTypeDef , __SPI_HandleTypeDef , __I2C_HandleTypeDef , __CRYP_HandleTypeDef , __COMP_HandleTypeDef , __USART_HandleTypeDef , __TIM_HandleTypeDef
  • Status : __LPTIM_HandleTypeDef
  • StatusBytesSize : QSPI_AutoPollingTypeDef
  • StatusMatchCallback : __QSPI_HandleTypeDef
  • StopBits : UART_InitTypeDef , LL_USART_InitTypeDef , USART_InitTypeDef , LL_LPUART_InitTypeDef , SMARTCARD_InitTypeDef
  • StoreOperation : RTC_TimeTypeDef
  • SubRegionDisable : MPU_Region_InitTypeDef
  • SubSeconds : RTC_TimeTypeDef
  • SuspendCallback : __PCD_HandleTypeDef
  • Swap : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • SyncEnable : HAL_DMA_MuxSyncConfigTypeDef
  • SynchPrediv : RTC_InitTypeDef
  • SynchPrescaler : LL_RTC_InitTypeDef
  • Synchro : SAI_InitTypeDef
  • SynchroExt : SAI_InitTypeDef
  • SynchroPinPolarity : TSC_InitTypeDef
  • SyncPolarity : HAL_DMA_MuxSyncConfigTypeDef
  • SyncSignalID : HAL_DMA_MuxSyncConfigTypeDef
  • SYSCLK_Frequency : LL_RCC_ClocksTypeDef
  • SYSCLKSource : RCC_ClkInitTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields - Variables

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  • Tamper : RTC_TamperTypeDef
  • Tamper1EventCallback : __RTC_HandleTypeDef
  • Tamper2EventCallback : __RTC_HandleTypeDef
  • Tamper3EventCallback : __RTC_HandleTypeDef
  • TamperPullUp : RTC_TamperTypeDef
  • TimeFormat : RTC_TimeTypeDef , LL_RTC_TimeTypeDef
  • Timeout : __QSPI_HandleTypeDef
  • TimeOutActivation : QSPI_MemoryMappedTypeDef
  • TimeOutCallback : __QSPI_HandleTypeDef
  • TimeOutEnable : SMARTCARD_InitTypeDef
  • TimeOutPeriod : QSPI_MemoryMappedTypeDef
  • TimeOutValue : SMARTCARD_InitTypeDef
  • TimeStampEventCallback : __RTC_HandleTypeDef
  • TimeStampOnTamperDetection : RTC_TamperTypeDef
  • Timing : I2C_InitTypeDef , SMBUS_InitTypeDef , LL_I2C_InitTypeDef
  • TIMode : SPI_InitTypeDef
  • TransferDirection : LL_LPUART_InitTypeDef , LL_SPI_InitTypeDef , LL_USART_InitTypeDef
  • TrigAuto : LL_ADC_INJ_InitTypeDef
  • Trigger : EXTI_ConfigTypeDef , LPTIM_InitTypeDef , RTC_TamperTypeDef , LL_EXTI_InitTypeDef
  • TriggerCallback : __COMP_HandleTypeDef , __LPTIM_HandleTypeDef , __TIM_HandleTypeDef
  • TriggeredMode : ADC_OversamplingTypeDef
  • TriggerFilter : TIM_SlaveConfigTypeDef
  • TriggerHalfCpltCallback : __TIM_HandleTypeDef
  • TriggerMode : COMP_InitTypeDef
  • TriggerPolarity : TIM_SlaveConfigTypeDef
  • TriggerPrescaler : TIM_SlaveConfigTypeDef
  • TriggerSource : LL_ADC_REG_InitTypeDef , LL_ADC_INJ_InitTypeDef
  • TriState : SAI_InitTypeDef
  • TxCompletionIndication : SMARTCARD_AdvFeatureInitTypeDef
  • TxCpltCallback : __USART_HandleTypeDef , __SAI_HandleTypeDef , __IRDA_HandleTypeDef , __QSPI_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef
  • TxFifoEmptyCallback : __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • TxHalfCpltCallback : __IRDA_HandleTypeDef , __QSPI_HandleTypeDef , __SAI_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __USART_HandleTypeDef
  • TxISR : __UART_HandleTypeDef , __SPI_HandleTypeDef , __USART_HandleTypeDef , __SMARTCARD_HandleTypeDef
  • TxPinLevelInvert : SMARTCARD_AdvFeatureInitTypeDef , UART_AdvFeatureInitTypeDef
  • TxRxCpltCallback : __USART_HandleTypeDef , __SPI_HandleTypeDef
  • TxRxHalfCpltCallback : __SPI_HandleTypeDef
  • TxXferCount : __USART_HandleTypeDef , __SMARTCARD_HandleTypeDef , __UART_HandleTypeDef , __SPI_HandleTypeDef , __IRDA_HandleTypeDef , __QSPI_HandleTypeDef
  • TxXferSize : __IRDA_HandleTypeDef , __USART_HandleTypeDef , __SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , __UART_HandleTypeDef , __QSPI_HandleTypeDef
  • TypeAcknowledge : LL_I2C_InitTypeDef
  • TypeErase : FLASH_EraseInitTypeDef
  • TypeExtField : MPU_Region_InitTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields - Variables

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  • UltraLowPowerClock : LPTIM_InitTypeDef
  • UpdateMode : LPTIM_InitTypeDef
  • Usart1ClockSelection : RCC_PeriphCLKInitTypeDef
  • USB_Address : __PCD_HandleTypeDef
  • UsbClockSelection : RCC_PeriphCLKInitTypeDef
  • UserConfig : FLASH_OBProgramInitTypeDef
  • UserType : FLASH_OBProgramInitTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields - Variables

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  • VoltageSource : LCD_InitTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields - Variables

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  • WakeupCallback : __UART_HandleTypeDef
  • WakeUpEvent : UART_WakeUpTypeDef
  • WakeupTarget : PWR_PVMTypeDef
  • WakeUpTimerEventCallback : __RTC_HandleTypeDef
  • WatchdogMode : ADC_AnalogWDGConfTypeDef
  • WatchdogNumber : ADC_AnalogWDGConfTypeDef
  • Waveform : LL_LPTIM_InitTypeDef
  • WeekDay : RTC_DateTypeDef , LL_RTC_DateTypeDef
  • Window : IWDG_InitTypeDef , WWDG_InitTypeDef
  • WindowMode : COMP_InitTypeDef
  • WordLength : IRDA_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef , SMARTCARD_InitTypeDef
  • WRPArea : FLASH_OBProgramInitTypeDef
  • WRPEndOffset : FLASH_OBProgramInitTypeDef
  • WRPStartOffset : FLASH_OBProgramInitTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields - Variables

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- x -

  • XferAbortCallback : __DMA_HandleTypeDef
  • XferCount : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef , __SAI_HandleTypeDef
  • XferCpltCallback : __DMA_HandleTypeDef
  • XferErrorCallback : __DMA_HandleTypeDef
  • XferHalfCpltCallback : __DMA_HandleTypeDef
  • XferISR : __I2C_HandleTypeDef
  • XferOptions : __I2C_HandleTypeDef , __SMBUS_HandleTypeDef
  • XferSize : __SAI_HandleTypeDef , __SMBUS_HandleTypeDef , __I2C_HandleTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Fields - Variables

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  • Year : RTC_DateTypeDef , LL_RTC_DateTypeDef
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_conf.h File Reference

  • File List
  • Globals
Defines
stm32wbxx_hal_conf.h File Reference

HAL configuration file. More...

#include "stm32wbxx_hal_dma.h"
#include "stm32wbxx_hal_adc.h"
#include "stm32wbxx_hal_comp.h"
#include "stm32wbxx_hal_cortex.h"
#include "stm32wbxx_hal_crc.h"
#include "stm32wbxx_hal_cryp.h"
#include "stm32wbxx_hal_exti.h"
#include "stm32wbxx_hal_flash.h"
#include "stm32wbxx_hal_gpio.h"
#include "stm32wbxx_hal_hsem.h"
#include "stm32wbxx_hal_i2c.h"
#include "stm32wbxx_hal_ipcc.h"
#include "stm32wbxx_hal_irda.h"
#include "stm32wbxx_hal_iwdg.h"
#include "stm32wbxx_hal_lcd.h"
#include "stm32wbxx_hal_lptim.h"
#include "stm32wbxx_hal_pcd.h"
#include "stm32wbxx_hal_pka.h"
#include "stm32wbxx_hal_pwr.h"
#include "stm32wbxx_hal_qspi.h"
#include "stm32wbxx_hal_rcc.h"
#include "stm32wbxx_hal_rng.h"
#include "stm32wbxx_hal_rtc.h"
#include "stm32wbxx_hal_sai.h"
#include "stm32wbxx_hal_smartcard.h"
#include "stm32wbxx_hal_smbus.h"
#include "stm32wbxx_hal_spi.h"
#include "stm32wbxx_hal_tim.h"
#include "stm32wbxx_hal_tsc.h"
#include "stm32wbxx_hal_uart.h"
#include "stm32wbxx_hal_usart.h"
#include "stm32wbxx_hal_wwdg.h"

Go to the source code of this file.

Defines

#define | HAL_MODULE_ENABLED
This is the list of modules to be used in the HAL driver.
#define | HAL_ADC_MODULE_ENABLED
#define | HAL_COMP_MODULE_ENABLED
#define | HAL_CORTEX_MODULE_ENABLED
#define | HAL_CRC_MODULE_ENABLED
#define | HAL_CRYP_MODULE_ENABLED
#define | HAL_DMA_MODULE_ENABLED
#define | HAL_EXTI_MODULE_ENABLED
#define | HAL_FLASH_MODULE_ENABLED
#define | HAL_GPIO_MODULE_ENABLED
#define | HAL_HSEM_MODULE_ENABLED
#define | HAL_I2C_MODULE_ENABLED
#define | HAL_IPCC_MODULE_ENABLED
#define | HAL_IRDA_MODULE_ENABLED
#define | HAL_IWDG_MODULE_ENABLED
#define | HAL_LCD_MODULE_ENABLED
#define | HAL_LPTIM_MODULE_ENABLED
#define | HAL_PCD_MODULE_ENABLED
#define | HAL_PKA_MODULE_ENABLED
#define | HAL_PWR_MODULE_ENABLED
#define | HAL_QSPI_MODULE_ENABLED
#define | HAL_RCC_MODULE_ENABLED
#define | HAL_RNG_MODULE_ENABLED
#define | HAL_RTC_MODULE_ENABLED
#define | HAL_SAI_MODULE_ENABLED
#define | HAL_SMARTCARD_MODULE_ENABLED
#define | HAL_SMBUS_MODULE_ENABLED
#define | HAL_SPI_MODULE_ENABLED
#define | HAL_TIM_MODULE_ENABLED
#define | HAL_TSC_MODULE_ENABLED
#define | HAL_UART_MODULE_ENABLED
#define | HAL_USART_MODULE_ENABLED
#define | HAL_WWDG_MODULE_ENABLED
#define | USE_HAL_ADC_REGISTER_CALLBACKS 1u
#define | USE_HAL_COMP_REGISTER_CALLBACKS 1u
#define | USE_HAL_CRYP_REGISTER_CALLBACKS 1u
#define | USE_HAL_I2C_REGISTER_CALLBACKS 1u
#define | USE_HAL_IRDA_REGISTER_CALLBACKS 1u
#define | USE_HAL_LPTIM_REGISTER_CALLBACKS 1u
#define | USE_HAL_PCD_REGISTER_CALLBACKS 1u
#define | USE_HAL_PKA_REGISTER_CALLBACKS 1u
#define | USE_HAL_QSPI_REGISTER_CALLBACKS 1u
#define | USE_HAL_RNG_REGISTER_CALLBACKS 1u
#define | USE_HAL_RTC_REGISTER_CALLBACKS 1u
#define | USE_HAL_SAI_REGISTER_CALLBACKS 1u
#define | USE_HAL_SMARTCARD_REGISTER_CALLBACKS 1u
#define | USE_HAL_SMBUS_REGISTER_CALLBACKS 1u
#define | USE_HAL_SPI_REGISTER_CALLBACKS 1u
#define | USE_HAL_TIM_REGISTER_CALLBACKS 1u
#define | USE_HAL_TSC_REGISTER_CALLBACKS 1u
#define | USE_HAL_UART_REGISTER_CALLBACKS 1u
#define | USE_HAL_USART_REGISTER_CALLBACKS 1u
#define | USE_HAL_WWDG_REGISTER_CALLBACKS 1u
#define | HSE_VALUE (32000000UL)
Adjust the value of External High Speed oscillator (HSE) used in your application.
#define | HSE_STARTUP_TIMEOUT (100UL)
#define | MSI_VALUE (4000000UL)
Internal Multiple Speed oscillator (MSI) default value.
#define | HSI_VALUE (16000000UL)
Internal High Speed oscillator (HSI) value.
#define | LSI1_VALUE (32000UL)
Internal Low Speed oscillator (LSI1) value.
#define | LSI2_VALUE (32000UL)
Internal Low Speed oscillator (LSI2) value.
#define | LSE_VALUE (32768UL)
External Low Speed oscillator (LSE) value.
#define | HSI48_VALUE (48000000UL)
Internal Multiple Speed oscillator (HSI48) default value.
#define | LSE_STARTUP_TIMEOUT (5000UL)
#define | EXTERNAL_SAI1_CLOCK_VALUE (48000UL)
External clock source for SAI1 peripheral This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source frequency.
#define | VDD_VALUE (3300UL)
This is the HAL system configuration section.
#define | TICK_INT_PRIORITY ((1UL<<__NVIC_PRIO_BITS) - 1UL)
#define | USE_RTOS 0
#define | PREFETCH_ENABLE 0
#define | INSTRUCTION_CACHE_ENABLE 1
#define | DATA_CACHE_ENABLE 1
#define | USE_SPI_CRC 1U
Uncomment the line below to expanse the "assert_param" macro in the HAL drivers code.
#define | assert_param(expr) ((void)0U)
Include module's header file.

Detailed Description

HAL configuration file.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Include module's header file.

Definition at line 344 of file stm32wbxx_hal_conf.h.

Referenced by ADC_ConversionStop(), FLASH_OB_GetWRP(), FLASH_OB_IPCCBufferAddrConfig(), FLASH_OB_OptrConfig(), FLASH_OB_PCROP1AConfig(), FLASH_OB_PCROP1BConfig(), FLASH_OB_SecureConfig(), FLASH_OB_WRPConfig(), FLASH_PageErase(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_DeInit(), HAL_ADC_GetError(), HAL_ADC_GetState(), HAL_ADC_GetValue(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_GetValue(), HAL_ADCEx_Calibration_SetValue(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_DisableInjectedQueue(), HAL_ADCEx_DisableVoltageRegulator(), HAL_ADCEx_EnableInjectedQueue(), HAL_ADCEx_EnterADCDeepPowerDownMode(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedGetValue(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_RegularStop(), HAL_ADCEx_RegularStop_DMA(), HAL_ADCEx_RegularStop_IT(), HAL_COMP_DeInit(), HAL_COMP_GetError(), HAL_COMP_GetOutputLevel(), HAL_COMP_GetState(), HAL_COMP_Init(), HAL_COMP_Lock(), HAL_COMP_Start(), HAL_COMP_Stop(), HAL_CRC_DeInit(), HAL_CRC_Init(), HAL_CRCEx_Input_Data_Reverse(), HAL_CRCEx_Output_Data_Reverse(), HAL_CRCEx_Polynomial_Set(), HAL_CRYP_Decrypt(), HAL_CRYP_Decrypt_DMA(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt(), HAL_CRYP_Encrypt_DMA(), HAL_CRYP_Encrypt_IT(), HAL_CRYP_Init(), HAL_CRYP_SetConfig(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_Start(), HAL_DMA_Start_IT(), HAL_DMAEx_ConfigMuxRequestGenerator(), HAL_DMAEx_ConfigMuxSync(), HAL_DMAEx_DisableMuxRequestGenerator(), HAL_DMAEx_EnableMuxRequestGenerator(), HAL_EXTI_ClearConfigLine(), HAL_EXTI_ClearPending(), HAL_EXTI_GenerateSWI(), HAL_EXTI_GetConfigLine(), HAL_EXTI_GetHandle(), HAL_EXTI_GetPending(), HAL_EXTI_SetConfigLine(), HAL_FLASH_Program(), HAL_FLASH_Program_IT(), HAL_FLASHEx_Erase(), HAL_FLASHEx_Erase_IT(), HAL_FLASHEx_ForceFlashEmpty(), HAL_FLASHEx_OBProgram(), HAL_GPIO_DeInit(), HAL_GPIO_Init(), HAL_GPIO_LockPin(), HAL_GPIO_ReadPin(), HAL_GPIO_TogglePin(), HAL_GPIO_WritePin(), HAL_HalfDuplex_Init(), HAL_HSEM_FastTake(), HAL_HSEM_Release(), HAL_HSEM_ReleaseAll(), HAL_HSEM_SetClearKey(), HAL_HSEM_Take(), HAL_I2C_DeInit(), HAL_I2C_Init(), HAL_I2C_Master_Seq_Receive_DMA(), HAL_I2C_Master_Seq_Receive_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Seq_Receive_DMA(), HAL_I2C_Slave_Seq_Receive_IT(), HAL_I2C_Slave_Seq_Transmit_DMA(), HAL_I2C_Slave_Seq_Transmit_IT(), HAL_I2CEx_ConfigAnalogFilter(), HAL_I2CEx_ConfigDigitalFilter(), HAL_I2CEx_DisableFastModePlus(), HAL_I2CEx_DisableWakeUp(), HAL_I2CEx_EnableFastModePlus(), HAL_I2CEx_EnableWakeUp(), HAL_IPCC_ActivateNotification(), HAL_IPCC_DeActivateNotification(), HAL_IPCC_DeInit(), HAL_IPCC_GetChannelStatus(), HAL_IPCC_Init(), HAL_IPCC_NotifyCPU(), HAL_IRDA_DeInit(), HAL_IRDA_Init(), HAL_IWDG_Init(), HAL_LCD_DeInit(), HAL_LCD_Init(), HAL_LCD_Write(), HAL_LIN_Init(), HAL_LIN_SendBreak(), HAL_LPTIM_Counter_Start(), HAL_LPTIM_Counter_Start_IT(), HAL_LPTIM_Counter_Stop(), HAL_LPTIM_Counter_Stop_IT(), HAL_LPTIM_Encoder_Start(), HAL_LPTIM_Encoder_Start_IT(), HAL_LPTIM_Encoder_Stop(), HAL_LPTIM_Encoder_Stop_IT(), HAL_LPTIM_Init(), HAL_LPTIM_OnePulse_Start(), HAL_LPTIM_OnePulse_Start_IT(), HAL_LPTIM_OnePulse_Stop(), HAL_LPTIM_OnePulse_Stop_IT(), HAL_LPTIM_PWM_Start(), HAL_LPTIM_PWM_Start_IT(), HAL_LPTIM_PWM_Stop(), HAL_LPTIM_PWM_Stop_IT(), HAL_LPTIM_ReadAutoReload(), HAL_LPTIM_ReadCompare(), HAL_LPTIM_ReadCounter(), HAL_LPTIM_SetOnce_Start(), HAL_LPTIM_SetOnce_Start_IT(), HAL_LPTIM_SetOnce_Stop(), HAL_LPTIM_SetOnce_Stop_IT(), HAL_LPTIM_TimeOut_Start(), HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop(), HAL_LPTIM_TimeOut_Stop_IT(), HAL_MPU_ConfigRegion(), HAL_MultiProcessor_Init(), HAL_MultiProcessorEx_AddressLength_Set(), HAL_NVIC_ClearPendingIRQ(), HAL_NVIC_DisableIRQ(), HAL_NVIC_EnableIRQ(), HAL_NVIC_GetPendingIRQ(), HAL_NVIC_GetPriority(), HAL_NVIC_SetPendingIRQ(), HAL_NVIC_SetPriority(), HAL_NVIC_SetPriorityGrouping(), HAL_PCD_Init(), HAL_PKA_DeInit(), HAL_PKA_Init(), HAL_PWR_ConfigPVD(), HAL_PWR_DisableWakeUpPin(), HAL_PWR_EnableWakeUpPin(), HAL_PWR_EnterSLEEPMode(), HAL_PWR_EnterSTOPMode(), HAL_PWREx_ConfigPVM(), HAL_PWREx_ConfigSMPS(), HAL_PWREx_ControlVoltageScaling(), HAL_PWREx_DisableFlashPowerDown(), HAL_PWREx_DisableGPIOPullDown(), HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableBatteryCharging(), HAL_PWREx_EnableFlashPowerDown(), HAL_PWREx_EnableGPIOPullDown(), HAL_PWREx_EnableGPIOPullUp(), HAL_PWREx_EnableWakeUpPin(), HAL_PWREx_EnterSTOP0Mode(), HAL_PWREx_EnterSTOP1Mode(), HAL_PWREx_EnterSTOP2Mode(), HAL_PWREx_HoldCore(), HAL_PWREx_ReleaseCore(), HAL_QSPI_AutoPolling(), HAL_QSPI_AutoPolling_IT(), HAL_QSPI_Command(), HAL_QSPI_Command_IT(), HAL_QSPI_Init(), HAL_QSPI_MemoryMapped(), HAL_RCC_ClockConfig(), HAL_RCC_GetClockConfig(), HAL_RCC_GetOscConfig(), HAL_RCC_MCOConfig(), HAL_RCC_OscConfig(), HAL_RCCEx_CRSConfig(), HAL_RCCEx_CRSGetSynchronizationInfo(), HAL_RCCEx_EnableLSCO(), HAL_RCCEx_EnablePLLSAI1(), HAL_RCCEx_GetPeriphCLKFreq(), HAL_RCCEx_LSCOConfig(), HAL_RCCEx_PeriphCLKConfig(), HAL_RCCEx_TrimOsc(), HAL_RCCEx_WakeUpStopCLKConfig(), HAL_RNG_Init(), HAL_RS485Ex_Init(), HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_Init(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_BKUPRead(), HAL_RTCEx_BKUPWrite(), HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_GetTimeStamp(), HAL_RTCEx_SetCalibrationOutPut(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetSynchroShift(), HAL_RTCEx_SetTamper(), HAL_RTCEx_SetTamper_IT(), HAL_RTCEx_SetTimeStamp(), HAL_RTCEx_SetTimeStamp_IT(), HAL_RTCEx_SetWakeUpTimer(), HAL_RTCEx_SetWakeUpTimer_IT(), HAL_SAI_EnableRxMuteMode(), HAL_SAI_EnableTxMuteMode(), HAL_SAI_Init(), HAL_SAI_InitProtocol(), HAL_SAIEx_ConfigPdmMicDelay(), HAL_SetTickFreq(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_Init(), HAL_SMARTCARDEx_DisableFifoMode(), HAL_SMARTCARDEx_EnableFifoMode(), HAL_SMARTCARDEx_SetRxFifoThreshold(), HAL_SMARTCARDEx_SetTxFifoThreshold(), HAL_SMARTCARDEx_TimeOut_Config(), HAL_SMBUS_ConfigAnalogFilter(), HAL_SMBUS_ConfigDigitalFilter(), HAL_SMBUS_DeInit(), HAL_SMBUS_Init(), HAL_SMBUS_Master_Receive_IT(), HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Slave_Receive_IT(), HAL_SMBUS_Slave_Transmit_IT(), HAL_SPI_DeInit(), HAL_SPI_Init(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), HAL_SYSCFG_DisableSecurityAccess(), HAL_SYSCFG_EnableSecurityAccess(), HAL_SYSCFG_VREFBUF_HighImpedanceConfig(), HAL_SYSCFG_VREFBUF_TrimmingConfig(), HAL_SYSCFG_VREFBUF_VoltageScalingConfig(), HAL_SYSTICK_CLKSourceConfig(), HAL_TIM_Base_DeInit(), HAL_TIM_Base_Init(), HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_Base_Stop_IT(), HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), HAL_TIM_ConfigTI1Input(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Init(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_GenerateEvent(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_Init(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_Init(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_Init(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIM_SlaveConfigSynchro(), HAL_TIM_SlaveConfigSynchro_IT(), HAL_TIMEx_ConfigBreakDeadTime(), HAL_TIMEx_ConfigBreakInput(), HAL_TIMEx_ConfigCommutEvent(), HAL_TIMEx_ConfigCommutEvent_DMA(), HAL_TIMEx_ConfigCommutEvent_IT(), HAL_TIMEx_GroupChannel5(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_Init(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_MasterConfigSynchronization(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), HAL_TIMEx_RemapConfig(), HAL_TSC_DeInit(), HAL_TSC_GetState(), HAL_TSC_GroupGetStatus(), HAL_TSC_GroupGetValue(), HAL_TSC_Init(), HAL_TSC_IOConfig(), HAL_TSC_IODischarge(), HAL_TSC_IRQHandler(), HAL_TSC_PollForAcquisition(), HAL_TSC_Start(), HAL_TSC_Start_IT(), HAL_TSC_Stop(), HAL_TSC_Stop_IT(), HAL_UART_DeInit(), HAL_UART_Init(), HAL_UART_ReceiverTimeout_Config(), HAL_UARTEx_DisableFifoMode(), HAL_UARTEx_EnableFifoMode(), HAL_UARTEx_SetRxFifoThreshold(), HAL_UARTEx_SetTxFifoThreshold(), HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_USART_DeInit(), HAL_USART_Init(), HAL_USARTEx_ConfigNSS(), HAL_USARTEx_DisableFifoMode(), HAL_USARTEx_DisableSlaveMode(), HAL_USARTEx_EnableFifoMode(), HAL_USARTEx_EnableSlaveMode(), HAL_USARTEx_SetRxFifoThreshold(), HAL_USARTEx_SetTxFifoThreshold(), HAL_WWDG_Init(), I2C_TransferConfig(), IRDA_SetConfig(), QSPI_Config(), RCC_SetFlashLatencyFromMSIRange(), RCCEx_PLLSAI1_ConfigNP(), RCCEx_PLLSAI1_ConfigNQ(), RCCEx_PLLSAI1_ConfigNR(), SMARTCARD_AdvFeatureConfig(), SMARTCARD_SetConfig(), SMBUS_TransferConfig(), TIM_CCxChannelCmd(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_SlaveTimer_SetConfig(), UART_AdvFeatureConfig(), UART_SetConfig(), UARTEx_Wakeup_AddressConfig(), and USART_SetConfig().

#define DATA_CACHE_ENABLE 1

Definition at line 180 of file stm32wbxx_hal_conf.h.

#define EXTERNAL_SAI1_CLOCK_VALUE (48000UL)

External clock source for SAI1 peripheral This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source frequency.

Value of the SAI1 External clock source in Hz

Definition at line 165 of file stm32wbxx_hal_conf.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define HAL_ADC_MODULE_ENABLED

Definition at line 36 of file stm32wbxx_hal_conf.h.

#define HAL_COMP_MODULE_ENABLED

Definition at line 37 of file stm32wbxx_hal_conf.h.

#define HAL_CORTEX_MODULE_ENABLED

Definition at line 38 of file stm32wbxx_hal_conf.h.

#define HAL_CRC_MODULE_ENABLED

Definition at line 39 of file stm32wbxx_hal_conf.h.

#define HAL_CRYP_MODULE_ENABLED

Definition at line 40 of file stm32wbxx_hal_conf.h.

#define HAL_DMA_MODULE_ENABLED

Definition at line 41 of file stm32wbxx_hal_conf.h.

#define HAL_EXTI_MODULE_ENABLED

Definition at line 42 of file stm32wbxx_hal_conf.h.

#define HAL_FLASH_MODULE_ENABLED

Definition at line 43 of file stm32wbxx_hal_conf.h.

#define HAL_GPIO_MODULE_ENABLED

Definition at line 44 of file stm32wbxx_hal_conf.h.

#define HAL_HSEM_MODULE_ENABLED

Definition at line 45 of file stm32wbxx_hal_conf.h.

#define HAL_I2C_MODULE_ENABLED

Definition at line 46 of file stm32wbxx_hal_conf.h.

#define HAL_IPCC_MODULE_ENABLED

Definition at line 47 of file stm32wbxx_hal_conf.h.

#define HAL_IRDA_MODULE_ENABLED

Definition at line 48 of file stm32wbxx_hal_conf.h.

#define HAL_IWDG_MODULE_ENABLED

Definition at line 49 of file stm32wbxx_hal_conf.h.

#define HAL_LCD_MODULE_ENABLED

Definition at line 50 of file stm32wbxx_hal_conf.h.

#define HAL_LPTIM_MODULE_ENABLED

Definition at line 51 of file stm32wbxx_hal_conf.h.

#define HAL_MODULE_ENABLED

This is the list of modules to be used in the HAL driver.

Definition at line 35 of file stm32wbxx_hal_conf.h.

#define HAL_PCD_MODULE_ENABLED

Definition at line 52 of file stm32wbxx_hal_conf.h.

#define HAL_PKA_MODULE_ENABLED

Definition at line 53 of file stm32wbxx_hal_conf.h.

#define HAL_PWR_MODULE_ENABLED

Definition at line 54 of file stm32wbxx_hal_conf.h.

#define HAL_QSPI_MODULE_ENABLED

Definition at line 55 of file stm32wbxx_hal_conf.h.

#define HAL_RCC_MODULE_ENABLED

Definition at line 56 of file stm32wbxx_hal_conf.h.

#define HAL_RNG_MODULE_ENABLED

Definition at line 57 of file stm32wbxx_hal_conf.h.

#define HAL_RTC_MODULE_ENABLED

Definition at line 58 of file stm32wbxx_hal_conf.h.

#define HAL_SAI_MODULE_ENABLED

Definition at line 59 of file stm32wbxx_hal_conf.h.

#define HAL_SMARTCARD_MODULE_ENABLED

Definition at line 60 of file stm32wbxx_hal_conf.h.

#define HAL_SMBUS_MODULE_ENABLED

Definition at line 61 of file stm32wbxx_hal_conf.h.

#define HAL_SPI_MODULE_ENABLED

Definition at line 62 of file stm32wbxx_hal_conf.h.

#define HAL_TIM_MODULE_ENABLED

Definition at line 63 of file stm32wbxx_hal_conf.h.

#define HAL_TSC_MODULE_ENABLED

Definition at line 64 of file stm32wbxx_hal_conf.h.

#define HAL_UART_MODULE_ENABLED

Definition at line 65 of file stm32wbxx_hal_conf.h.

#define HAL_USART_MODULE_ENABLED

Definition at line 66 of file stm32wbxx_hal_conf.h.

#define HAL_WWDG_MODULE_ENABLED

Definition at line 67 of file stm32wbxx_hal_conf.h.

#define HSE_STARTUP_TIMEOUT (100UL)

Time out for HSE start up, in ms

Definition at line 102 of file stm32wbxx_hal_conf.h.

#define HSE_VALUE (32000000UL)

Adjust the value of External High Speed oscillator (HSE) used in your application.

This value is used by the RCC HAL module to compute the system frequency (when HSE is used as system clock source, directly or through the PLL). Value of the External oscillator in Hz

Definition at line 98 of file stm32wbxx_hal_conf.h.

Referenced by HAL_RCC_GetSysClockFreq(), HAL_RCCEx_GetPeriphCLKFreq(), LL_PLL_ConfigSystemClock_HSE(), LL_RCC_GetRFWKPClockFreq(), LL_RCC_GetRTCClockFreq(), LL_RCC_GetSMPSClockFreq(), RCC_GetHCLK5ClockFreq(), RCC_GetSystemClockFreq(), RCC_PLL_GetFreqDomain_48M(), RCC_PLL_GetFreqDomain_ADC(), RCC_PLL_GetFreqDomain_P(), RCC_PLL_GetFreqDomain_Q(), RCC_PLL_GetFreqDomain_SAI(), RCC_PLL_GetFreqDomain_SYS(), RCC_PLLSAI1_GetFreqDomain_48M(), RCC_PLLSAI1_GetFreqDomain_ADC(), RCC_PLLSAI1_GetFreqDomain_P(), RCC_PLLSAI1_GetFreqDomain_Q(), RCC_PLLSAI1_GetFreqDomain_R(), and RCC_PLLSAI1_GetFreqDomain_SAI().

#define HSI48_VALUE (48000000UL)

Internal Multiple Speed oscillator (HSI48) default value.

This value is the default HSI48 range value after Reset. Value of the Internal oscillator in Hz

Definition at line 152 of file stm32wbxx_hal_conf.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and LL_RCC_GetCLK48ClockFreq().

#define HSI_VALUE (16000000UL)

Internal High Speed oscillator (HSI) value.

This value is used by the RCC HAL module to compute the system frequency (when HSI is used as system clock source, directly or through the PLL). Value of the Internal oscillator in Hz

Definition at line 119 of file stm32wbxx_hal_conf.h.

Referenced by HAL_RCC_GetSysClockFreq(), HAL_RCCEx_GetPeriphCLKFreq(), IRDA_SetConfig(), LL_PLL_ConfigSystemClock_HSI(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetSAIClockFreq(), LL_RCC_GetSMPSClockFreq(), LL_RCC_GetUSARTClockFreq(), RCC_GetHCLK5ClockFreq(), RCC_GetSystemClockFreq(), RCC_PLL_GetFreqDomain_48M(), RCC_PLL_GetFreqDomain_ADC(), RCC_PLL_GetFreqDomain_P(), RCC_PLL_GetFreqDomain_Q(), RCC_PLL_GetFreqDomain_SAI(), RCC_PLL_GetFreqDomain_SYS(), RCC_PLLSAI1_GetFreqDomain_48M(), RCC_PLLSAI1_GetFreqDomain_ADC(), RCC_PLLSAI1_GetFreqDomain_P(), RCC_PLLSAI1_GetFreqDomain_Q(), RCC_PLLSAI1_GetFreqDomain_R(), RCC_PLLSAI1_GetFreqDomain_SAI(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

#define INSTRUCTION_CACHE_ENABLE 1

Definition at line 179 of file stm32wbxx_hal_conf.h.

#define LSE_STARTUP_TIMEOUT (5000UL)

Time out for LSE start up, in ms

Definition at line 156 of file stm32wbxx_hal_conf.h.

#define LSE_VALUE (32768UL)

External Low Speed oscillator (LSE) value.

< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature. This value is used by the UART, RTC HAL module to compute the system frequency Value of the External oscillator in Hz

Definition at line 144 of file stm32wbxx_hal_conf.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), IRDA_SetConfig(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetRFWKPClockFreq(), LL_RCC_GetRNGClockFreq(), LL_RCC_GetRTCClockFreq(), LL_RCC_GetUSARTClockFreq(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

#define LSI1_VALUE (32000UL)

Internal Low Speed oscillator (LSI1) value.

LSI1 Typical Value in Hz

Definition at line 126 of file stm32wbxx_hal_conf.h.

#define LSI2_VALUE (32000UL)

Internal Low Speed oscillator (LSI2) value.

< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature. LSI2 Typical Value in Hz

Definition at line 134 of file stm32wbxx_hal_conf.h.

#define MSI_VALUE (4000000UL)

Internal Multiple Speed oscillator (MSI) default value.

This value is the default MSI range value after Reset. Value of the Internal oscillator in Hz

Definition at line 110 of file stm32wbxx_hal_conf.h.

Referenced by HAL_RCC_DeInit().

#define PREFETCH_ENABLE 0

Definition at line 178 of file stm32wbxx_hal_conf.h.

#define TICK_INT_PRIORITY ((1UL<<__NVIC_PRIO_BITS) - 1UL)

tick interrupt priority (lowest by default)

Definition at line 176 of file stm32wbxx_hal_conf.h.

Referenced by HAL_Init().

#define USE_HAL_ADC_REGISTER_CALLBACKS 1u

Definition at line 69 of file stm32wbxx_hal_conf.h.

#define USE_HAL_COMP_REGISTER_CALLBACKS 1u

Definition at line 70 of file stm32wbxx_hal_conf.h.

#define USE_HAL_CRYP_REGISTER_CALLBACKS 1u

Definition at line 71 of file stm32wbxx_hal_conf.h.

#define USE_HAL_I2C_REGISTER_CALLBACKS 1u

Definition at line 72 of file stm32wbxx_hal_conf.h.

#define USE_HAL_IRDA_REGISTER_CALLBACKS 1u

Definition at line 73 of file stm32wbxx_hal_conf.h.

#define USE_HAL_LPTIM_REGISTER_CALLBACKS 1u

Definition at line 74 of file stm32wbxx_hal_conf.h.

#define USE_HAL_PCD_REGISTER_CALLBACKS 1u

Definition at line 75 of file stm32wbxx_hal_conf.h.

#define USE_HAL_PKA_REGISTER_CALLBACKS 1u

Definition at line 76 of file stm32wbxx_hal_conf.h.

#define USE_HAL_QSPI_REGISTER_CALLBACKS 1u

Definition at line 77 of file stm32wbxx_hal_conf.h.

#define USE_HAL_RNG_REGISTER_CALLBACKS 1u

Definition at line 78 of file stm32wbxx_hal_conf.h.

#define USE_HAL_RTC_REGISTER_CALLBACKS 1u

Definition at line 79 of file stm32wbxx_hal_conf.h.

#define USE_HAL_SAI_REGISTER_CALLBACKS 1u

Definition at line 80 of file stm32wbxx_hal_conf.h.

#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 1u

Definition at line 81 of file stm32wbxx_hal_conf.h.

#define USE_HAL_SMBUS_REGISTER_CALLBACKS 1u

Definition at line 82 of file stm32wbxx_hal_conf.h.

#define USE_HAL_SPI_REGISTER_CALLBACKS 1u

Definition at line 83 of file stm32wbxx_hal_conf.h.

#define USE_HAL_TIM_REGISTER_CALLBACKS 1u

Definition at line 84 of file stm32wbxx_hal_conf.h.

#define USE_HAL_TSC_REGISTER_CALLBACKS 1u

Definition at line 85 of file stm32wbxx_hal_conf.h.

#define USE_HAL_UART_REGISTER_CALLBACKS 1u

Definition at line 86 of file stm32wbxx_hal_conf.h.

#define USE_HAL_USART_REGISTER_CALLBACKS 1u

Definition at line 87 of file stm32wbxx_hal_conf.h.

#define USE_HAL_WWDG_REGISTER_CALLBACKS 1u

Definition at line 88 of file stm32wbxx_hal_conf.h.

#define USE_RTOS 0

Definition at line 177 of file stm32wbxx_hal_conf.h.

#define USE_SPI_CRC 1U

Uncomment the line below to expanse the "assert_param" macro in the HAL drivers code.

Definition at line 196 of file stm32wbxx_hal_conf.h.

#define VDD_VALUE (3300UL)

This is the HAL system configuration section.

Value of VDD in mv

Definition at line 175 of file stm32wbxx_hal_conf.h.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_rcc_ex.c File Reference

  • File List
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  • STM32WBxx_HAL_Driver
  • Src
Defines | Functions
stm32wbxx_hal_rcc_ex.c File Reference

Extended RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extended peripheral: + Extended Peripheral Control functions + Extended Clock management functions + Extended Clock Recovery System Control functions. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Defines

#define | PLLSAI1_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
#define | PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
#define | CLOCKSMPS_TIMEOUT_VALUE (5000U) /* 5 s */
#define | __LSCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define | LSCO1_GPIO_PORT GPIOA
#define | LSCO1_PIN GPIO_PIN_2
#define | __LSCO2_CLK_ENABLE() __HAL_RCC_GPIOH_CLK_ENABLE()
#define | LSCO2_GPIO_PORT GPIOH
#define | LSCO2_PIN GPIO_PIN_3
#define | __LSCO3_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
#define | LSCO3_GPIO_PORT GPIOC
#define | LSCO3_PIN GPIO_PIN_12
#define | LSI2_TIMEOUT_VALUE (3U) /* to be adjusted with DS */
#define | FTLSI2TRIM (0xFUL)

Functions

static HAL_StatusTypeDef | RCCEx_PLLSAI1_ConfigNP (RCC_PLLSAI1InitTypeDef *PLLSAI1)
Configure the parameters N & P of PLLSAI1 and enable PLLSAI1 output clock(s).
static HAL_StatusTypeDef | RCCEx_PLLSAI1_ConfigNQ (RCC_PLLSAI1InitTypeDef *PLLSAI1)
Configure the parameters N & Q of PLLSAI1 and enable PLLSAI1 output clock(s).
static HAL_StatusTypeDef | RCCEx_PLLSAI1_ConfigNR (RCC_PLLSAI1InitTypeDef *PLLSAI1)
Configure the parameters N & R of PLLSAI1 and enable PLLSAI1 output clock(s).
static uint32_t | RCC_PLL_GetFreqDomain_P (void)
Return PLL clock (PLLPCLK) frequency used for SAI domain.
static uint32_t | RCC_PLL_GetFreqDomain_Q (void)
Return PLL clock (PLLQCLK) frequency used for 48 MHz domain.
static uint32_t | RCC_PLLSAI1_GetFreqDomain_R (void)
Return PLLSAI1 clock (PLLSAI1RCLK) frequency used for ADC domain.
static uint32_t | RCC_PLLSAI1_GetFreqDomain_P (void)
Return PLLSAI1 clock (PLLSAI1PCLK) frequency used for SAI domain.
static uint32_t | RCC_PLLSAI1_GetFreqDomain_Q (void)
Return PLLSAI1 clock (PLLSAI1QCLK) frequency used for 48Mhz domain.
HAL_StatusTypeDef | HAL_RCCEx_PeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Initialize the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.
void | HAL_RCCEx_GetPeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
uint32_t | HAL_RCCEx_GetPeriphCLKFreq (uint32_t PeriphClk)
Return the peripheral clock frequency for peripherals with clock source.
uint32_t | HAL_RCCEx_GetRngCLKSource (void)
Return the RNG clock source.
HAL_StatusTypeDef | HAL_RCCEx_EnablePLLSAI1 (RCC_PLLSAI1InitTypeDef *PLLSAI1Init)
Enable PLLSAI1.
HAL_StatusTypeDef | HAL_RCCEx_DisablePLLSAI1 (void)
Disable PLLSAI1.
void | HAL_RCCEx_WakeUpStopCLKConfig (uint32_t WakeUpClk)
Configure the oscillator clock source for wakeup from Stop and CSS backup clock.
void | HAL_RCCEx_EnableLSECSS (void)
Enable the LSE Clock Security System.
void | HAL_RCCEx_DisableLSECSS (void)
Disable the LSE Clock Security System.
void | HAL_RCCEx_EnableLSECSS_IT (void)
Enable the LSE Clock Security System Interrupt & corresponding EXTI line.
void | HAL_RCCEx_LSECSS_IRQHandler (void)
Handle the RCC LSE Clock Security System interrupt request.
__weak void | HAL_RCCEx_LSECSS_Callback (void)
RCCEx LSE Clock Security System interrupt callback.
void | HAL_RCCEx_LSCOConfig (uint32_t RCC_LSCOx, uint32_t RCC_LSCOSource)
Select the clock source to output on LSCO1 pin(PA2) or LSC02 pin (PH3) or LSCO3 pin (PC12).
void | HAL_RCCEx_EnableLSCO (uint32_t LSCOSource)
Select the Low Speed clock source to output on LSCO pin (PA2).
void | HAL_RCCEx_DisableLSCO (void)
Disable the Low Speed clock output.
void | HAL_RCCEx_EnableMSIPLLMode (void)
Enable the PLL-mode of the MSI.
void | HAL_RCCEx_DisableMSIPLLMode (void)
Disable the PLL-mode of the MSI.
HAL_StatusTypeDef | HAL_RCCEx_TrimOsc (uint32_t OscillatorType)
Set trimming value.
void | HAL_RCCEx_CRSConfig (RCC_CRSInitTypeDef *pInit)
Start automatic synchronization for polling mode.
void | HAL_RCCEx_CRSSoftwareSynchronizationGenerate (void)
Generate the software synchronization event.
void | HAL_RCCEx_CRSGetSynchronizationInfo (RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
Return synchronization info.
uint32_t | HAL_RCCEx_CRSWaitSynchronization (uint32_t Timeout)
Wait for CRS Synchronization status.
void | HAL_RCCEx_CRS_IRQHandler (void)
Handle the Clock Recovery System interrupt request.
__weak void | HAL_RCCEx_CRS_SyncOkCallback (void)
RCCEx Clock Recovery System SYNCOK interrupt callback.
__weak void | HAL_RCCEx_CRS_SyncWarnCallback (void)
RCCEx Clock Recovery System SYNCWARN interrupt callback.
__weak void | HAL_RCCEx_CRS_ExpectedSyncCallback (void)
RCCEx Clock Recovery System Expected SYNC interrupt callback.
__weak void | HAL_RCCEx_CRS_ErrorCallback (uint32_t Error)
RCCEx Clock Recovery System Error interrupt callback.

Detailed Description

Extended RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extended peripheral: + Extended Peripheral Control functions + Extended Clock management functions + Extended Clock Recovery System Control functions.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_rcc_ex.c.

Define Documentation

#define FTLSI2TRIM (0xFUL)

Referenced by HAL_RCCEx_TrimOsc().

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_adc.c File Reference

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Defines | Functions
stm32wbxx_ll_adc.c File Reference

ADC LL module driver. More...

#include "stm32wbxx_ll_adc.h"
#include "stm32wbxx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 16UL * 4UL)
#define | ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
#define | ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
#define | IS_LL_ADC_COMMON_CLOCK(__CLOCK__)
#define | IS_LL_ADC_RESOLUTION(__RESOLUTION__)
#define | IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__)
#define | IS_LL_ADC_LOW_POWER(__LOW_POWER__)
#define | IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__)
#define | IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__)
#define | IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__)
#define | IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__)
#define | IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__)
#define | IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__)
#define | IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__)
#define | IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__)
#define | IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__)
#define | IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__)
#define | IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__)

Functions

ErrorStatus | LL_ADC_CommonDeInit (ADC_Common_TypeDef *ADCxy_COMMON)
De-initialize registers of all ADC instances belonging to the same ADC common instance to their default reset values.
ErrorStatus | LL_ADC_CommonInit (ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Initialize some features of ADC common parameters (all ADC instances belonging to the same ADC common instance) and multimode (for devices with several ADC instances available).
void | LL_ADC_CommonStructInit (LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Set each LL_ADC_CommonInitTypeDef field to default value.
ErrorStatus | LL_ADC_DeInit (ADC_TypeDef *ADCx)
De-initialize registers of the selected ADC instance to their default reset values.
ErrorStatus | LL_ADC_Init (ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
Initialize some features of ADC instance.
void | LL_ADC_StructInit (LL_ADC_InitTypeDef *ADC_InitStruct)
Set each LL_ADC_InitTypeDef field to default value.
ErrorStatus | LL_ADC_REG_Init (ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
Initialize some features of ADC group regular.
void | LL_ADC_REG_StructInit (LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
Set each LL_ADC_REG_InitTypeDef field to default value.
ErrorStatus | LL_ADC_INJ_Init (ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
Initialize some features of ADC group injected.
void | LL_ADC_INJ_StructInit (LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
Set each LL_ADC_INJ_InitTypeDef field to default value.

Detailed Description

ADC LL module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_adc.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 28 of file stm32wbxx_ll_adc.c.

Referenced by LL_ADC_CommonDeInit(), LL_ADC_CommonInit(), LL_ADC_DeInit(), LL_ADC_Init(), LL_ADC_INJ_Init(), and LL_ADC_REG_Init().

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_comp.c File Reference

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  • STM32WBxx_HAL_Driver
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Defines | Functions
stm32wbxx_ll_comp.c File Reference

COMP LL module driver. More...

#include "stm32wbxx_ll_comp.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_COMP_POWER_MODE(__POWER_MODE__)
#define | IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)
#define | IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)
#define | IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__)
#define | IS_LL_COMP_OUTPUT_POLARITY(__POLARITY__)
#define | IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__OUTPUT_BLANKING_SOURCE__)

Functions

ErrorStatus | LL_COMP_DeInit (COMP_TypeDef *COMPx)
De-initialize registers of the selected COMP instance to their default reset values.
ErrorStatus | LL_COMP_Init (COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct)
Initialize some features of COMP instance.
void | LL_COMP_StructInit (LL_COMP_InitTypeDef *COMP_InitStruct)
Set each LL_COMP_InitTypeDef field to default value.

Detailed Description

COMP LL module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_comp.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 27 of file stm32wbxx_ll_comp.c.

Referenced by LL_COMP_DeInit(), and LL_COMP_Init().

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_crc.c File Reference

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  • STM32WBxx_HAL_Driver
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Defines | Functions
stm32wbxx_ll_crc.c File Reference

CRC LL module driver. More...

#include "stm32wbxx_ll_crc.h"
#include "stm32wbxx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)

Functions

ErrorStatus | LL_CRC_DeInit (CRC_TypeDef *CRCx)
De-initialize CRC registers (Registers restored to their default values).

Detailed Description

CRC LL module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_crc.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 28 of file stm32wbxx_ll_crc.c.

Referenced by LL_CRC_DeInit().

Generated on Fri Sep 6 2019 11:34:39 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_dma.c File Reference

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  • STM32WBxx_HAL_Driver
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Defines | Functions
stm32wbxx_ll_dma.c File Reference

DMA LL module driver. More...

#include "stm32wbxx_ll_dma.h"
#include "stm32wbxx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_DMA_DIRECTION(__VALUE__)
#define | IS_LL_DMA_MODE(__VALUE__)
#define | IS_LL_DMA_PERIPHINCMODE(__VALUE__)
#define | IS_LL_DMA_MEMORYINCMODE(__VALUE__)
#define | IS_LL_DMA_PERIPHDATASIZE(__VALUE__)
#define | IS_LL_DMA_MEMORYDATASIZE(__VALUE__)
#define | IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
#define | IS_LL_DMA_PERIPHREQUEST(__VALUE__) ((__VALUE__) <= 40U)
#define | IS_LL_DMA_PRIORITY(__VALUE__)
#define | IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)

Functions

ErrorStatus | LL_DMA_DeInit (DMA_TypeDef *DMAx, uint32_t Channel)
De-initialize the DMA registers to their default reset values.
ErrorStatus | LL_DMA_Init (DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
void | LL_DMA_StructInit (LL_DMA_InitTypeDef *DMA_InitStruct)
Set each LL_DMA_InitTypeDef field to default value.

Detailed Description

DMA LL module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_dma.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 27 of file stm32wbxx_ll_dma.c.

Referenced by LL_DMA_DeInit(), and LL_DMA_Init().

Generated on Fri Sep 6 2019 11:34:39 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_exti.c File Reference

  • File List
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  • Firmware
  • Drivers
  • STM32WBxx_HAL_Driver
  • Src
Defines | Functions
stm32wbxx_ll_exti.c File Reference

EXTI LL module driver. More...

#include "stm32wbxx_ll_exti.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
#define | IS_LL_EXTI_LINE_32_63(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U)
#define | IS_LL_EXTI_MODE(__VALUE__)
#define | IS_LL_EXTI_TRIGGER(__VALUE__)

Functions

ErrorStatus | LL_EXTI_DeInit (void)
De-initialize the EXTI registers to their default reset values.
ErrorStatus | LL_EXTI_Init (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
void | LL_EXTI_StructInit (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Set each LL_EXTI_InitTypeDef field to default value.

Detailed Description

EXTI LL module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_exti.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 26 of file stm32wbxx_ll_exti.c.

Referenced by LL_EXTI_Init().

Generated on Fri Sep 6 2019 11:34:39 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_gpio.c File Reference

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  • STM32WBxx_HAL_Driver
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Defines | Functions
stm32wbxx_ll_gpio.c File Reference

GPIO LL module driver. More...

#include "stm32wbxx_ll_gpio.h"
#include "stm32wbxx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_GPIO_PIN(__VALUE__) (((0x00u) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
#define | IS_LL_GPIO_MODE(__VALUE__)
#define | IS_LL_GPIO_OUTPUT_TYPE(__VALUE__)
#define | IS_LL_GPIO_SPEED(__VALUE__)
#define | IS_LL_GPIO_PULL(__VALUE__)
#define | IS_LL_GPIO_ALTERNATE(__VALUE__)

Functions

ErrorStatus | LL_GPIO_DeInit (GPIO_TypeDef *GPIOx)
De-initialize GPIO registers (Registers restored to their default values).
ErrorStatus | LL_GPIO_Init (GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
void | LL_GPIO_StructInit (LL_GPIO_InitTypeDef *GPIO_InitStruct)
Set each LL_GPIO_InitTypeDef field to default value.

Detailed Description

GPIO LL module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_gpio.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 27 of file stm32wbxx_ll_gpio.c.

Referenced by LL_GPIO_DeInit(), and LL_GPIO_Init().

Generated on Fri Sep 6 2019 11:34:39 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_i2c.c File Reference

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Defines | Functions
stm32wbxx_ll_i2c.c File Reference

I2C LL module driver. More...

#include "stm32wbxx_ll_i2c.h"
#include "stm32wbxx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_I2C_PERIPHERAL_MODE(__VALUE__)
#define | IS_LL_I2C_ANALOG_FILTER(__VALUE__)
#define | IS_LL_I2C_DIGITAL_FILTER(__VALUE__) ((__VALUE__) <= 0x0000000FU)
#define | IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU)
#define | IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__)
#define | IS_LL_I2C_OWN_ADDRSIZE(__VALUE__)

Functions

ErrorStatus | LL_I2C_DeInit (I2C_TypeDef *I2Cx)
De-initialize the I2C registers to their default reset values.
ErrorStatus | LL_I2C_Init (I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
void | LL_I2C_StructInit (LL_I2C_InitTypeDef *I2C_InitStruct)
Set each LL_I2C_InitTypeDef field to default value.

Detailed Description

I2C LL module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_i2c.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 27 of file stm32wbxx_ll_i2c.c.

Referenced by LL_I2C_DeInit(), and LL_I2C_Init().

Generated on Fri Sep 6 2019 11:34:39 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_lptim.c File Reference

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Defines | Functions
stm32wbxx_ll_lptim.c File Reference

LPTIM LL module driver. More...

#include "stm32wbxx_ll_lptim.h"
#include "stm32wbxx_ll_bus.h"
#include "stm32wbxx_ll_rcc.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_LPTIM_CLOCK_SOURCE(__VALUE__)
#define | IS_LL_LPTIM_CLOCK_PRESCALER(__VALUE__)
#define | IS_LL_LPTIM_WAVEFORM(__VALUE__)
#define | IS_LL_LPTIM_OUTPUT_POLARITY(__VALUE__)

Functions

ErrorStatus | LL_LPTIM_DeInit (LPTIM_TypeDef *LPTIMx)
Set LPTIMx registers to their reset values.
void | LL_LPTIM_StructInit (LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
Set each fields of the LPTIM_InitStruct structure to its default value.
ErrorStatus | LL_LPTIM_Init (LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
Configure the LPTIMx peripheral according to the specified parameters.
void | LL_LPTIM_Disable (LPTIM_TypeDef *LPTIMx)
Disable the LPTIM instance.

Detailed Description

LPTIM LL module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_lptim.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 30 of file stm32wbxx_ll_lptim.c.

Referenced by LL_LPTIM_DeInit(), LL_LPTIM_Disable(), and LL_LPTIM_Init().

Generated on Fri Sep 6 2019 11:34:39 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_lpuart.c File Reference

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Defines | Functions
stm32wbxx_ll_lpuart.c File Reference

LPUART LL module driver. More...

#include "stm32wbxx_ll_lpuart.h"
#include "stm32wbxx_ll_rcc.h"
#include "stm32wbxx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_LPUART_PRESCALER(__VALUE__)
#define | IS_LL_LPUART_BAUDRATE(__BAUDRATE__) (((__BAUDRATE__) <= 21300000U) && ((__BAUDRATE__) >= 8U))
#define | IS_LL_LPUART_BRR_MIN(__VALUE__) ((__VALUE__) >= 0x300U)
#define | IS_LL_LPUART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x000FFFFFU)
#define | IS_LL_LPUART_DIRECTION(__VALUE__)
#define | IS_LL_LPUART_PARITY(__VALUE__)
#define | IS_LL_LPUART_DATAWIDTH(__VALUE__)
#define | IS_LL_LPUART_STOPBITS(__VALUE__)
#define | IS_LL_LPUART_HWCONTROL(__VALUE__)

Functions

ErrorStatus | LL_LPUART_DeInit (USART_TypeDef *LPUARTx)
De-initialize LPUART registers (Registers restored to their default values).
ErrorStatus | LL_LPUART_Init (USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct)
Initialize LPUART registers according to the specified parameters in LPUART_InitStruct.
void | LL_LPUART_StructInit (LL_LPUART_InitTypeDef *LPUART_InitStruct)
Set each LL_LPUART_InitTypeDef field to default value.

Detailed Description

LPUART LL module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_lpuart.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 28 of file stm32wbxx_ll_lpuart.c.

Referenced by LL_LPUART_DeInit(), and LL_LPUART_Init().

Generated on Fri Sep 6 2019 11:34:39 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_pka.c File Reference

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Defines | Functions
stm32wbxx_ll_pka.c File Reference

PKA LL module driver. More...

#include "stm32wbxx_ll_pka.h"
#include "stm32wbxx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_PKA_MODE(__VALUE__)

Functions

ErrorStatus | LL_PKA_DeInit (PKA_TypeDef *PKAx)
De-initialize PKA registers (Registers restored to their default values).
ErrorStatus | LL_PKA_Init (PKA_TypeDef *PKAx, LL_PKA_InitTypeDef *PKA_InitStruct)
Initialize PKA registers according to the specified parameters in PKA_InitStruct.
void | LL_PKA_StructInit (LL_PKA_InitTypeDef *PKA_InitStruct)
Set each LL_PKA_InitTypeDef field to default value.

Detailed Description

PKA LL module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_pka.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 28 of file stm32wbxx_ll_pka.c.

Referenced by LL_PKA_DeInit(), and LL_PKA_Init().

Generated on Fri Sep 6 2019 11:34:39 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_rcc.c File Reference

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Defines | Functions
stm32wbxx_ll_rcc.c File Reference

RCC LL module driver. More...

#include "stm32wbxx_ll_rcc.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_RCC_USART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_USART1_CLKSOURCE)
#define | IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE)
#define | IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__)
#define | IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_SAI1_CLKSOURCE)
#define | IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
#define | IS_LL_RCC_CLK48_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CLK48_CLKSOURCE))
#define | IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
#define | IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))

Functions

uint32_t | RCC_PLL_GetFreqDomain_SYS (void)
Return PLL clock (PLLRCLK) frequency used for system domain.
uint32_t | RCC_PLL_GetFreqDomain_SAI (void)
Return PLL clock (PLLPCLK) frequency used for SAI domain.
uint32_t | RCC_PLL_GetFreqDomain_ADC (void)
Return PLL clock (PLLPCLK) frequency used for ADC domain.
uint32_t | RCC_PLL_GetFreqDomain_48M (void)
Return PLL clock (PLLQCLK) frequency used for 48 MHz domain.
uint32_t | RCC_PLLSAI1_GetFreqDomain_SAI (void)
Return PLLSAI1 clock (PLLSAI1PCLK) frequency used for SAI domain.
uint32_t | RCC_PLLSAI1_GetFreqDomain_48M (void)
Return PLLSAI1 clock (PLLSAI1QCLK) frequency used for 48Mhz domain.
uint32_t | RCC_PLLSAI1_GetFreqDomain_ADC (void)
Return PLLSAI1 clock (PLLSAI1RCLK) frequency used for ADC domain.
uint32_t | RCC_GetSystemClockFreq (void)
Return SYSTEM clock (SYSCLK) frequency.
uint32_t | RCC_GetHCLK1ClockFreq (uint32_t SYSCLK_Frequency)
Return HCLK1 clock frequency.
uint32_t | RCC_GetHCLK2ClockFreq (uint32_t SYSCLK_Frequency)
Return HCLK2 clock frequency.
uint32_t | RCC_GetHCLK4ClockFreq (uint32_t SYSCLK_Frequency)
Return HCLK clock frequency.
uint32_t | RCC_GetHCLK5ClockFreq (void)
Return HCLK5 clock frequency.
uint32_t | RCC_GetPCLK1ClockFreq (uint32_t HCLK_Frequency)
Return PCLK1 clock frequency.
uint32_t | RCC_GetPCLK2ClockFreq (uint32_t HCLK_Frequency)
Return PCLK2 clock frequency.
ErrorStatus | LL_RCC_DeInit (void)
Reset the RCC clock to the default reset state.
void | LL_RCC_GetSystemClocksFreq (LL_RCC_ClocksTypeDef *RCC_Clocks)
Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks.
uint32_t | LL_RCC_GetSMPSClockFreq (void)
Return SMPS clock frequency.
uint32_t | LL_RCC_GetUSARTClockFreq (uint32_t USARTxSource)
Return USARTx clock frequency.
uint32_t | LL_RCC_GetI2CClockFreq (uint32_t I2CxSource)
Return I2Cx clock frequency.
uint32_t | LL_RCC_GetLPUARTClockFreq (uint32_t LPUARTxSource)
Return LPUARTx clock frequency.
uint32_t | LL_RCC_GetLPTIMClockFreq (uint32_t LPTIMxSource)
Return LPTIMx clock frequency.
uint32_t | LL_RCC_GetSAIClockFreq (uint32_t SAIxSource)
Return SAIx clock frequency.
uint32_t | LL_RCC_GetCLK48ClockFreq (uint32_t CLK48xSource)
Return CLK48x clock frequency.
uint32_t | LL_RCC_GetUSBClockFreq (uint32_t USBxSource)
Return USBx clock frequency.
uint32_t | LL_RCC_GetRNGClockFreq (uint32_t RNGxSource)
Return RNGx clock frequency.
uint32_t | LL_RCC_GetADCClockFreq (uint32_t ADCxSource)
Return ADCx clock frequency.
uint32_t | LL_RCC_GetRTCClockFreq (void)
Return RTC & LCD clock frequency.
uint32_t | LL_RCC_GetRFWKPClockFreq (void)
Return RF Wakeup clock frequency.

Detailed Description

RCC LL module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_rcc.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 26 of file stm32wbxx_ll_rcc.c.

Referenced by LL_RCC_GetADCClockFreq(), LL_RCC_GetCLK48ClockFreq(), LL_RCC_GetI2CClockFreq(), LL_RCC_GetLPTIMClockFreq(), LL_RCC_GetLPUARTClockFreq(), LL_RCC_GetRNGClockFreq(), LL_RCC_GetSAIClockFreq(), and LL_RCC_GetUSARTClockFreq().

Generated on Fri Sep 6 2019 11:34:39 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_rng.c File Reference

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Defines | Functions
stm32wbxx_ll_rng.c File Reference

RNG LL module driver. More...

#include "stm32wbxx_ll_rng.h"
#include "stm32wbxx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_RNG_CED(__MODE__)

Functions

ErrorStatus | LL_RNG_DeInit (RNG_TypeDef *RNGx)
De-initialize RNG registers (Registers restored to their default values).
ErrorStatus | LL_RNG_Init (RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct)
Initialize RNG registers according to the specified parameters in RNG_InitStruct.
void | LL_RNG_StructInit (LL_RNG_InitTypeDef *RNG_InitStruct)
Set each LL_RNG_InitTypeDef field to default value.

Detailed Description

RNG LL module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_rng.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 28 of file stm32wbxx_ll_rng.c.

Referenced by LL_RNG_DeInit(), and LL_RNG_Init().

Generated on Fri Sep 6 2019 11:34:39 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_rtc.c File Reference

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Defines | Functions
stm32wbxx_ll_rtc.c File Reference

RTC LL module driver. More...

#include "stm32wbxx_ll_rtc.h"
#include "stm32wbxx_ll_cortex.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | RTC_ASYNCH_PRESC_DEFAULT 0x0000007FU
#define | RTC_SYNCH_PRESC_DEFAULT 0x000000FFU
#define | RTC_INITMODE_TIMEOUT 1000U /* 1s when tick set to 1ms */
#define | RTC_SYNCHRO_TIMEOUT 1000U /* 1s when tick set to 1ms */
#define | IS_LL_RTC_HOURFORMAT(__VALUE__)
#define | IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FU)
#define | IS_LL_RTC_SYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FFFU)
#define | IS_LL_RTC_FORMAT(__VALUE__)
#define | IS_LL_RTC_TIME_FORMAT(__VALUE__)
#define | IS_LL_RTC_HOUR12(__HOUR__) (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))
#define | IS_LL_RTC_HOUR24(__HOUR__) ((__HOUR__) <= 23U)
#define | IS_LL_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= 59U)
#define | IS_LL_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= 59U)
#define | IS_LL_RTC_WEEKDAY(__VALUE__)
#define | IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= 1U) && ((__DAY__) <= 31U))
#define | IS_LL_RTC_MONTH(__VALUE__)
#define | IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
#define | IS_LL_RTC_ALMA_MASK(__VALUE__)
#define | IS_LL_RTC_ALMB_MASK(__VALUE__)
#define | IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__)
#define | IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__)

Functions

ErrorStatus | LL_RTC_DeInit (RTC_TypeDef *RTCx)
De-Initializes the RTC registers to their default reset values.
ErrorStatus | LL_RTC_Init (RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
Initializes the RTC registers according to the specified parameters in RTC_InitStruct.
void | LL_RTC_StructInit (LL_RTC_InitTypeDef *RTC_InitStruct)
Set each LL_RTC_InitTypeDef field to default value.
ErrorStatus | LL_RTC_TIME_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
Set the RTC current time.
void | LL_RTC_TIME_StructInit (LL_RTC_TimeTypeDef *RTC_TimeStruct)
Set each LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
ErrorStatus | LL_RTC_DATE_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct)
Set the RTC current date.
void | LL_RTC_DATE_StructInit (LL_RTC_DateTypeDef *RTC_DateStruct)
Set each LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)
ErrorStatus | LL_RTC_ALMA_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the RTC Alarm A.
ErrorStatus | LL_RTC_ALMB_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the RTC Alarm B.
void | LL_RTC_ALMA_StructInit (LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).
void | LL_RTC_ALMB_StructInit (LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).
ErrorStatus | LL_RTC_EnterInitMode (RTC_TypeDef *RTCx)
Enters the RTC Initialization mode.
ErrorStatus | LL_RTC_ExitInitMode (RTC_TypeDef *RTCx)
Exit the RTC Initialization mode.
ErrorStatus | LL_RTC_WaitForSynchro (RTC_TypeDef *RTCx)
Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Detailed Description

RTC LL module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_rtc.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 27 of file stm32wbxx_ll_rtc.c.

Referenced by LL_RTC_ALMA_Init(), LL_RTC_ALMB_Init(), LL_RTC_DATE_Init(), LL_RTC_DeInit(), LL_RTC_EnterInitMode(), LL_RTC_ExitInitMode(), LL_RTC_Init(), LL_RTC_TIME_Init(), and LL_RTC_WaitForSynchro().

Generated on Fri Sep 6 2019 11:34:39 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_spi.c File Reference

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Defines | Functions
stm32wbxx_ll_spi.c File Reference

SPI LL module driver. More...

#include "stm32wbxx_ll_spi.h"
#include "stm32wbxx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | SPI_CR1_CLEAR_MASK
#define | IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__)
#define | IS_LL_SPI_MODE(__VALUE__)
#define | IS_LL_SPI_DATAWIDTH(__VALUE__)
#define | IS_LL_SPI_POLARITY(__VALUE__)
#define | IS_LL_SPI_PHASE(__VALUE__)
#define | IS_LL_SPI_NSS(__VALUE__)
#define | IS_LL_SPI_BAUDRATE(__VALUE__)
#define | IS_LL_SPI_BITORDER(__VALUE__)
#define | IS_LL_SPI_CRCCALCULATION(__VALUE__)
#define | IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)

Functions

ErrorStatus | LL_SPI_DeInit (SPI_TypeDef *SPIx)
De-initialize the SPI registers to their default reset values.
ErrorStatus | LL_SPI_Init (SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
void | LL_SPI_StructInit (LL_SPI_InitTypeDef *SPI_InitStruct)
Set each LL_SPI_InitTypeDef field to default value.

Detailed Description

SPI LL module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_spi.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 28 of file stm32wbxx_ll_spi.c.

Referenced by LL_SPI_DeInit(), and LL_SPI_Init().

Generated on Fri Sep 6 2019 11:34:39 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_tim.c File Reference

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Defines | Functions
stm32wbxx_ll_tim.c File Reference

TIM LL module driver. More...

#include "stm32wbxx_ll_tim.h"
#include "stm32wbxx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_TIM_COUNTERMODE(__VALUE__)
#define | IS_LL_TIM_CLOCKDIVISION(__VALUE__)
#define | IS_LL_TIM_OCMODE(__VALUE__)
#define | IS_LL_TIM_OCSTATE(__VALUE__)
#define | IS_LL_TIM_OCPOLARITY(__VALUE__)
#define | IS_LL_TIM_OCIDLESTATE(__VALUE__)
#define | IS_LL_TIM_ACTIVEINPUT(__VALUE__)
#define | IS_LL_TIM_ICPSC(__VALUE__)
#define | IS_LL_TIM_IC_FILTER(__VALUE__)
#define | IS_LL_TIM_IC_POLARITY(__VALUE__)
#define | IS_LL_TIM_ENCODERMODE(__VALUE__)
#define | IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__)
#define | IS_LL_TIM_OSSR_STATE(__VALUE__)
#define | IS_LL_TIM_OSSI_STATE(__VALUE__)
#define | IS_LL_TIM_LOCK_LEVEL(__VALUE__)
#define | IS_LL_TIM_BREAK_STATE(__VALUE__)
#define | IS_LL_TIM_BREAK_POLARITY(__VALUE__)
#define | IS_LL_TIM_BREAK_FILTER(__VALUE__)
#define | IS_LL_TIM_BREAK2_STATE(__VALUE__)
#define | IS_LL_TIM_BREAK2_POLARITY(__VALUE__)
#define | IS_LL_TIM_BREAK2_FILTER(__VALUE__)
#define | IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__)

Functions

static ErrorStatus | OC1Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 1.
static ErrorStatus | OC2Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 2.
static ErrorStatus | OC3Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 3.
static ErrorStatus | OC4Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 4.
static ErrorStatus | OC5Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 5.
static ErrorStatus | OC6Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 6.
static ErrorStatus | IC1Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 1.
static ErrorStatus | IC2Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 2.
static ErrorStatus | IC3Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 3.
static ErrorStatus | IC4Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 4.
ErrorStatus | LL_TIM_DeInit (TIM_TypeDef *TIMx)
Set TIMx registers to their reset values.
void | LL_TIM_StructInit (LL_TIM_InitTypeDef *TIM_InitStruct)
Set the fields of the time base unit configuration data structure to their default values.
ErrorStatus | LL_TIM_Init (TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
Configure the TIMx time base unit.
void | LL_TIM_OC_StructInit (LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Set the fields of the TIMx output channel configuration data structure to their default values.
ErrorStatus | LL_TIM_OC_Init (TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Configure the TIMx output channel.
void | LL_TIM_IC_StructInit (LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Set the fields of the TIMx input channel configuration data structure to their default values.
ErrorStatus | LL_TIM_IC_Init (TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
Configure the TIMx input channel.
void | LL_TIM_ENCODER_StructInit (LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Fills each TIM_EncoderInitStruct field with its default value.
ErrorStatus | LL_TIM_ENCODER_Init (TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Configure the encoder interface of the timer instance.
void | LL_TIM_HALLSENSOR_StructInit (LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
Set the fields of the TIMx Hall sensor interface configuration data structure to their default values.
ErrorStatus | LL_TIM_HALLSENSOR_Init (TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
Configure the Hall sensor interface of the timer instance.
void | LL_TIM_BDTR_StructInit (LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
Set the fields of the Break and Dead Time configuration data structure to their default values.
ErrorStatus | LL_TIM_BDTR_Init (TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
Configure the Break and Dead Time feature of the timer instance.

Detailed Description

TIM LL module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_tim.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 28 of file stm32wbxx_ll_tim.c.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), LL_TIM_BDTR_Init(), LL_TIM_DeInit(), LL_TIM_ENCODER_Init(), LL_TIM_HALLSENSOR_Init(), LL_TIM_Init(), OC1Config(), OC2Config(), OC3Config(), OC4Config(), OC5Config(), and OC6Config().

Generated on Fri Sep 6 2019 11:34:39 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_usart.c File Reference

  • File List
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  • Firmware
  • Drivers
  • STM32WBxx_HAL_Driver
  • Src
Defines | Functions
stm32wbxx_ll_usart.c File Reference

USART LL module driver. More...

#include "stm32wbxx_ll_usart.h"
#include "stm32wbxx_ll_rcc.h"
#include "stm32wbxx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_USART_PRESCALER(__VALUE__)
#define | IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 8000000U)
#define | IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
#define | IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
#define | IS_LL_USART_DIRECTION(__VALUE__)
#define | IS_LL_USART_PARITY(__VALUE__)
#define | IS_LL_USART_DATAWIDTH(__VALUE__)
#define | IS_LL_USART_OVERSAMPLING(__VALUE__)
#define | IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__)
#define | IS_LL_USART_CLOCKPHASE(__VALUE__)
#define | IS_LL_USART_CLOCKPOLARITY(__VALUE__)
#define | IS_LL_USART_CLOCKOUTPUT(__VALUE__)
#define | IS_LL_USART_STOPBITS(__VALUE__)
#define | IS_LL_USART_HWCONTROL(__VALUE__)

Functions

ErrorStatus | LL_USART_DeInit (USART_TypeDef *USARTx)
De-initialize USART registers (Registers restored to their default values).
ErrorStatus | LL_USART_Init (USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
Initialize USART registers according to the specified parameters in USART_InitStruct.
void | LL_USART_StructInit (LL_USART_InitTypeDef *USART_InitStruct)
Set each LL_USART_InitTypeDef field to default value.
ErrorStatus | LL_USART_ClockInit (USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Initialize USART Clock related settings according to the specified parameters in the USART_ClockInitStruct.
void | LL_USART_ClockStructInit (LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Set each field of a LL_USART_ClockInitTypeDef type structure to default value.

Detailed Description

USART LL module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_usart.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 28 of file stm32wbxx_ll_usart.c.

Referenced by LL_USART_ClockInit(), LL_USART_DeInit(), and LL_USART_Init().

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_utils.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32WBxx_HAL_Driver
  • Src
Defines | Functions
stm32wbxx_ll_utils.c File Reference

UTILS LL module driver. More...

#include "stm32wbxx_ll_utils.h"
#include "stm32wbxx_ll_rcc.h"
#include "stm32wbxx_ll_system.h"
#include "stm32wbxx_ll_pwr.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | UTILS_MAX_FREQUENCY_SCALE1 64000000U
#define | UTILS_MAX_FREQUENCY_SCALE2 16000000U
#define | UTILS_PLLVCO_INPUT_MIN 2660000U
#define | UTILS_PLLVCO_INPUT_MAX 16000000U
#define | UTILS_PLLVCO_OUTPUT_MIN 96000000U
#define | UTILS_PLLVCO_OUTPUT_MAX 344000000U
#define | UTILS_HCLK2_MAX 32000000U
#define | IS_LL_UTILS_SYSCLK_DIV(__VALUE__)
#define | IS_LL_UTILS_APB1_DIV(__VALUE__)
#define | IS_LL_UTILS_APB2_DIV(__VALUE__)
#define | IS_LL_UTILS_PLLM_VALUE(__VALUE__)
#define | IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((6U <= (__VALUE__)) && ((__VALUE__) <= 127U))
#define | IS_LL_UTILS_PLLR_VALUE(__VALUE__)
#define | IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))
#define | IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))
#define | IS_LL_UTILS_PLL_FREQUENCY(__VALUE__)
#define | IS_LL_UTILS_HSE_BYPASS(__STATE__)
#define | countof(a) (sizeof(a) / sizeof(*(a)))

Functions

static uint32_t | UTILS_GetPLLOutputFrequency (uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
Function to check that PLL can be modified.
static ErrorStatus | UTILS_SetFlashLatency (uint32_t HCLK4_Frequency)
Update number of Flash wait states in line with new frequency and current voltage range.
static ErrorStatus | UTILS_EnablePLLAndSwitchSystem (uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
Function to enable PLL and switch system clock to PLL.
static ErrorStatus | UTILS_PLL_IsBusy (void)
Function to check that PLL can be modified.
void | LL_Init1msTick (uint32_t HCLKFrequency)
This function configures the Cortex-M SysTick source to have 1ms time base.
void | LL_mDelay (uint32_t Delay)
This function provides accurate delay (in milliseconds) based on SysTick counter flag.
void | LL_SetSystemCoreClock (uint32_t HCLKFrequency)
This function sets directly SystemCoreClock CMSIS variable.
ErrorStatus | LL_PLL_ConfigSystemClock_MSI (LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock with MSI as clock source of the PLL.
ErrorStatus | LL_PLL_ConfigSystemClock_HSI (LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock at maximum frequency with HSI as clock source of the PLL.
ErrorStatus | LL_PLL_ConfigSystemClock_HSE (uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock with HSE as clock source of the PLL.

Detailed Description

UTILS LL module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_utils.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 27 of file stm32wbxx_ll_utils.c.

Referenced by LL_PLL_ConfigSystemClock_HSE(), UTILS_EnablePLLAndSwitchSystem(), and UTILS_GetPLLOutputFrequency().

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- _ -

  • __ADC_PTR_REG_OFFSET : stm32wbxx_ll_adc.h
  • __COUNTOF : stm32wbxx_hal_rcc.c
  • __HAL_ADC_CALC_DATA_TO_VOLTAGE : stm32wbxx_hal_adc.h
  • __HAL_ADC_CALC_TEMPERATURE : stm32wbxx_hal_adc.h
  • __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS : stm32wbxx_hal_adc.h
  • __HAL_ADC_CALC_VREFANALOG_VOLTAGE : stm32wbxx_hal_adc.h
  • __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL : stm32wbxx_hal_adc.h
  • __HAL_ADC_CHANNEL_TO_DECIMAL_NB : stm32wbxx_hal_adc.h
  • __HAL_ADC_CLEAR_FLAG : stm32wbxx_hal_adc.h
  • __HAL_ADC_COMMON_INSTANCE : stm32wbxx_hal_adc.h
  • __HAL_ADC_CONVERT_DATA_RESOLUTION : stm32wbxx_hal_adc.h
  • __HAL_ADC_DECIMAL_NB_TO_CHANNEL : stm32wbxx_hal_adc.h
  • __HAL_ADC_DIGITAL_SCALE : stm32wbxx_hal_adc.h
  • __HAL_ADC_DISABLE_IT : stm32wbxx_hal_adc.h
  • __HAL_ADC_ENABLE_IT : stm32wbxx_hal_adc.h
  • __HAL_ADC_GET_FLAG : stm32wbxx_hal_adc.h
  • __HAL_ADC_GET_IT_SOURCE : stm32wbxx_hal_adc.h
  • __HAL_ADC_IS_CHANNEL_INTERNAL : stm32wbxx_hal_adc.h
  • __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE : stm32wbxx_hal_adc.h
  • __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE : stm32wbxx_hal_adc.h
  • __HAL_ADC_RESET_HANDLE_STATE : stm32wbxx_hal_adc.h
  • __HAL_C2_DBGMCU_FREEZE_I2C1_TIMEOUT : stm32wbxx_hal.h
  • __HAL_C2_DBGMCU_FREEZE_I2C3_TIMEOUT : stm32wbxx_hal.h
  • __HAL_C2_DBGMCU_FREEZE_IWDG : stm32wbxx_hal.h
  • __HAL_C2_DBGMCU_FREEZE_LPTIM1 : stm32wbxx_hal.h
  • __HAL_C2_DBGMCU_FREEZE_LPTIM2 : stm32wbxx_hal.h
  • __HAL_C2_DBGMCU_FREEZE_RTC : stm32wbxx_hal.h
  • __HAL_C2_DBGMCU_FREEZE_TIM1 : stm32wbxx_hal.h
  • __HAL_C2_DBGMCU_FREEZE_TIM16 : stm32wbxx_hal.h
  • __HAL_C2_DBGMCU_FREEZE_TIM17 : stm32wbxx_hal.h
  • __HAL_C2_DBGMCU_FREEZE_TIM2 : stm32wbxx_hal.h
  • __HAL_C2_DBGMCU_UNFREEZE_I2C1_TIMEOUT : stm32wbxx_hal.h
  • __HAL_C2_DBGMCU_UNFREEZE_I2C3_TIMEOUT : stm32wbxx_hal.h
  • __HAL_C2_DBGMCU_UNFREEZE_IWDG : stm32wbxx_hal.h
  • __HAL_C2_DBGMCU_UNFREEZE_LPTIM1 : stm32wbxx_hal.h
  • __HAL_C2_DBGMCU_UNFREEZE_LPTIM2 : stm32wbxx_hal.h
  • __HAL_C2_DBGMCU_UNFREEZE_RTC : stm32wbxx_hal.h
  • __HAL_C2_DBGMCU_UNFREEZE_TIM1 : stm32wbxx_hal.h
  • __HAL_C2_DBGMCU_UNFREEZE_TIM16 : stm32wbxx_hal.h
  • __HAL_C2_DBGMCU_UNFREEZE_TIM17 : stm32wbxx_hal.h
  • __HAL_C2_DBGMCU_UNFREEZE_TIM2 : stm32wbxx_hal.h
  • __HAL_C2_PWR_WAKEUP_802_15_4 : stm32wbxx_hal_pwr_ex.h
  • __HAL_C2_PWR_WAKEUP_BLE : stm32wbxx_hal_pwr_ex.h
  • __HAL_C2_RCC_LSECSS_EXTI_DISABLE_EVENT : stm32wbxx_hal_rcc_ex.h
  • __HAL_C2_RCC_LSECSS_EXTI_DISABLE_IT : stm32wbxx_hal_rcc_ex.h
  • __HAL_C2_RCC_LSECSS_EXTI_ENABLE_EVENT : stm32wbxx_hal_rcc_ex.h
  • __HAL_C2_RCC_LSECSS_EXTI_ENABLE_IT : stm32wbxx_hal_rcc_ex.h
  • __HAL_COMP_COMP1_EXTI_CLEAR_FLAG : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_EVENT : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_IT : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_EVENT : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_IT : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_GENERATE_SWIT : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_GET_FLAG : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_CLEAR_FLAG : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_EVENT : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_IT : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_EVENT : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_IT : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_GENERATE_SWIT : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_GET_FLAG : stm32wbxx_hal_comp.h
  • __HAL_COMP_DISABLE : stm32wbxx_hal_comp.h
  • __HAL_COMP_ENABLE : stm32wbxx_hal_comp.h
  • __HAL_COMP_IS_LOCKED : stm32wbxx_hal_comp.h
  • __HAL_COMP_LOCK : stm32wbxx_hal_comp.h
  • __HAL_COMP_RESET_HANDLE_STATE : stm32wbxx_hal_comp.h
  • __HAL_CRC_DR_RESET : stm32wbxx_hal_crc.h
  • __HAL_CRC_GET_IDR : stm32wbxx_hal_crc.h
  • __HAL_CRC_INITIALCRCVALUE_CONFIG : stm32wbxx_hal_crc.h
  • __HAL_CRC_OUTPUTREVERSAL_DISABLE : stm32wbxx_hal_crc_ex.h
  • __HAL_CRC_OUTPUTREVERSAL_ENABLE : stm32wbxx_hal_crc_ex.h
  • __HAL_CRC_POLYNOMIAL_CONFIG : stm32wbxx_hal_crc_ex.h
  • __HAL_CRC_RESET_HANDLE_STATE : stm32wbxx_hal_crc.h
  • __HAL_CRC_SET_IDR : stm32wbxx_hal_crc.h
  • __HAL_CRYP_CLEAR_FLAG : stm32wbxx_hal_cryp.h
  • __HAL_CRYP_DISABLE : stm32wbxx_hal_cryp.h
  • __HAL_CRYP_DISABLE_IT : stm32wbxx_hal_cryp.h
  • __HAL_CRYP_ENABLE : stm32wbxx_hal_cryp.h
  • __HAL_CRYP_ENABLE_IT : stm32wbxx_hal_cryp.h
  • __HAL_CRYP_GET_FLAG : stm32wbxx_hal_cryp.h
  • __HAL_CRYP_GET_IT : stm32wbxx_hal_cryp.h
  • __HAL_CRYP_GET_IT_SOURCE : stm32wbxx_hal_cryp.h
  • __HAL_CRYP_RESET_HANDLE_STATE : stm32wbxx_hal_cryp.h
  • __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT : stm32wbxx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT : stm32wbxx_hal.h
  • __HAL_DBGMCU_FREEZE_IWDG : stm32wbxx_hal.h
  • __HAL_DBGMCU_FREEZE_LPTIM1 : stm32wbxx_hal.h
  • __HAL_DBGMCU_FREEZE_LPTIM2 : stm32wbxx_hal.h
  • __HAL_DBGMCU_FREEZE_RTC : stm32wbxx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM1 : stm32wbxx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM16 : stm32wbxx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM17 : stm32wbxx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM2 : stm32wbxx_hal.h
  • __HAL_DBGMCU_FREEZE_WWDG : stm32wbxx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT : stm32wbxx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT : stm32wbxx_hal.h
  • __HAL_DBGMCU_UNFREEZE_IWDG : stm32wbxx_hal.h
  • __HAL_DBGMCU_UNFREEZE_LPTIM1 : stm32wbxx_hal.h
  • __HAL_DBGMCU_UNFREEZE_LPTIM2 : stm32wbxx_hal.h
  • __HAL_DBGMCU_UNFREEZE_RTC : stm32wbxx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM1 : stm32wbxx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM16 : stm32wbxx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM17 : stm32wbxx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM2 : stm32wbxx_hal.h
  • __HAL_DBGMCU_UNFREEZE_WWDG : stm32wbxx_hal.h
  • __HAL_DMA_CLEAR_FLAG : stm32wbxx_hal_dma.h
  • __HAL_DMA_DISABLE : stm32wbxx_hal_dma.h
  • __HAL_DMA_DISABLE_IT : stm32wbxx_hal_dma.h
  • __HAL_DMA_ENABLE : stm32wbxx_hal_dma.h
  • __HAL_DMA_ENABLE_IT : stm32wbxx_hal_dma.h
  • __HAL_DMA_GET_COUNTER : stm32wbxx_hal_dma.h
  • __HAL_DMA_GET_FLAG : stm32wbxx_hal_dma.h
  • __HAL_DMA_GET_GI_FLAG_INDEX : stm32wbxx_hal_dma.h
  • __HAL_DMA_GET_HT_FLAG_INDEX : stm32wbxx_hal_dma.h
  • __HAL_DMA_GET_IT_SOURCE : stm32wbxx_hal_dma.h
  • __HAL_DMA_GET_TC_FLAG_INDEX : stm32wbxx_hal_dma.h
  • __HAL_DMA_GET_TE_FLAG_INDEX : stm32wbxx_hal_dma.h
  • __HAL_DMA_RESET_HANDLE_STATE : stm32wbxx_hal_dma.h
  • __HAL_FLASH_CLEAR_FLAG : stm32wbxx_hal_flash.h
  • __HAL_FLASH_DATA_CACHE_DISABLE : stm32wbxx_hal_flash.h
  • __HAL_FLASH_DATA_CACHE_ENABLE : stm32wbxx_hal_flash.h
  • __HAL_FLASH_DATA_CACHE_RESET : stm32wbxx_hal_flash.h
  • __HAL_FLASH_DISABLE_IT : stm32wbxx_hal_flash.h
  • __HAL_FLASH_ENABLE_IT : stm32wbxx_hal_flash.h
  • __HAL_FLASH_GET_FLAG : stm32wbxx_hal_flash.h
  • __HAL_FLASH_GET_LATENCY : stm32wbxx_hal_flash.h
  • __HAL_FLASH_INSTRUCTION_CACHE_DISABLE : stm32wbxx_hal_flash.h
  • __HAL_FLASH_INSTRUCTION_CACHE_ENABLE : stm32wbxx_hal_flash.h
  • __HAL_FLASH_INSTRUCTION_CACHE_RESET : stm32wbxx_hal_flash.h
  • __HAL_FLASH_PREFETCH_BUFFER_DISABLE : stm32wbxx_hal_flash.h
  • __HAL_FLASH_PREFETCH_BUFFER_ENABLE : stm32wbxx_hal_flash.h
  • __HAL_FLASH_SET_LATENCY : stm32wbxx_hal_flash.h
  • __HAL_GPIO_EXTI_CLEAR_FLAG : stm32wbxx_hal_gpio.h
  • __HAL_GPIO_EXTI_CLEAR_IT : stm32wbxx_hal_gpio.h
  • __HAL_GPIO_EXTI_GENERATE_SWIT : stm32wbxx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_FLAG : stm32wbxx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_IT : stm32wbxx_hal_gpio.h
  • __HAL_HSEM_CLEAR_FLAG : stm32wbxx_hal_hsem.h
  • __HAL_HSEM_DISABLE_IT : stm32wbxx_hal_hsem.h
  • __HAL_HSEM_ENABLE_IT : stm32wbxx_hal_hsem.h
  • __HAL_HSEM_GET_FLAG : stm32wbxx_hal_hsem.h
  • __HAL_HSEM_GET_IT : stm32wbxx_hal_hsem.h
  • __HAL_HSEM_SEMID_TO_MASK : stm32wbxx_hal_hsem.h
  • __HAL_I2C_CLEAR_FLAG : stm32wbxx_hal_i2c.h
  • __HAL_I2C_DISABLE : stm32wbxx_hal_i2c.h
  • __HAL_I2C_DISABLE_IT : stm32wbxx_hal_i2c.h
  • __HAL_I2C_ENABLE : stm32wbxx_hal_i2c.h
  • __HAL_I2C_ENABLE_IT : stm32wbxx_hal_i2c.h
  • __HAL_I2C_GENERATE_NACK : stm32wbxx_hal_i2c.h
  • __HAL_I2C_GET_FLAG : stm32wbxx_hal_i2c.h
  • __HAL_I2C_GET_IT_SOURCE : stm32wbxx_hal_i2c.h
  • __HAL_I2C_RESET_HANDLE_STATE : stm32wbxx_hal_i2c.h
  • __HAL_IPCC_DISABLE_IT : stm32wbxx_hal_ipcc.h
  • __HAL_IPCC_ENABLE_IT : stm32wbxx_hal_ipcc.h
  • __HAL_IPCC_MASK_CHANNEL_IT : stm32wbxx_hal_ipcc.h
  • __HAL_IPCC_UNMASK_CHANNEL_IT : stm32wbxx_hal_ipcc.h
  • __HAL_IRDA_CLEAR_FEFLAG : stm32wbxx_hal_irda.h
  • __HAL_IRDA_CLEAR_FLAG : stm32wbxx_hal_irda.h
  • __HAL_IRDA_CLEAR_IDLEFLAG : stm32wbxx_hal_irda.h
  • __HAL_IRDA_CLEAR_IT : stm32wbxx_hal_irda.h
  • __HAL_IRDA_CLEAR_NEFLAG : stm32wbxx_hal_irda.h
  • __HAL_IRDA_CLEAR_OREFLAG : stm32wbxx_hal_irda.h
  • __HAL_IRDA_CLEAR_PEFLAG : stm32wbxx_hal_irda.h
  • __HAL_IRDA_DISABLE : stm32wbxx_hal_irda.h
  • __HAL_IRDA_DISABLE_IT : stm32wbxx_hal_irda.h
  • __HAL_IRDA_ENABLE : stm32wbxx_hal_irda.h
  • __HAL_IRDA_ENABLE_IT : stm32wbxx_hal_irda.h
  • __HAL_IRDA_FLUSH_DRREGISTER : stm32wbxx_hal_irda.h
  • __HAL_IRDA_GET_FLAG : stm32wbxx_hal_irda.h
  • __HAL_IRDA_GET_IT : stm32wbxx_hal_irda.h
  • __HAL_IRDA_GET_IT_SOURCE : stm32wbxx_hal_irda.h
  • __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE : stm32wbxx_hal_irda.h
  • __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE : stm32wbxx_hal_irda.h
  • __HAL_IRDA_RESET_HANDLE_STATE : stm32wbxx_hal_irda.h
  • __HAL_IRDA_SEND_REQ : stm32wbxx_hal_irda.h
  • __HAL_IWDG_RELOAD_COUNTER : stm32wbxx_hal_iwdg.h
  • __HAL_IWDG_START : stm32wbxx_hal_iwdg.h
  • __HAL_LCD_BLINK_CONFIG : stm32wbxx_hal_lcd.h
  • __HAL_LCD_CLEAR_FLAG : stm32wbxx_hal_lcd.h
  • __HAL_LCD_CONTRAST_CONFIG : stm32wbxx_hal_lcd.h
  • __HAL_LCD_DEADTIME_CONFIG : stm32wbxx_hal_lcd.h
  • __HAL_LCD_DISABLE : stm32wbxx_hal_lcd.h
  • __HAL_LCD_DISABLE_IT : stm32wbxx_hal_lcd.h
  • __HAL_LCD_ENABLE : stm32wbxx_hal_lcd.h
  • __HAL_LCD_ENABLE_IT : stm32wbxx_hal_lcd.h
  • __HAL_LCD_GET_FLAG : stm32wbxx_hal_lcd.h
  • __HAL_LCD_GET_IT_SOURCE : stm32wbxx_hal_lcd.h
  • __HAL_LCD_HIGHDRIVER_DISABLE : stm32wbxx_hal_lcd.h
  • __HAL_LCD_HIGHDRIVER_ENABLE : stm32wbxx_hal_lcd.h
  • __HAL_LCD_PULSEONDURATION_CONFIG : stm32wbxx_hal_lcd.h
  • __HAL_LCD_RESET_HANDLE_STATE : stm32wbxx_hal_lcd.h
  • __HAL_LCD_VOLTAGE_BUFFER_DISABLE : stm32wbxx_hal_lcd.h
  • __HAL_LCD_VOLTAGE_BUFFER_ENABLE : stm32wbxx_hal_lcd.h
  • __HAL_LPTIM_AUTORELOAD_SET : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_CLEAR_FLAG : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_COMPARE_SET : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_DISABLE : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_DISABLE_IT : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_ENABLE : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_ENABLE_IT : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_GET_FLAG : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_GET_IT_SOURCE : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_LPTIM1_EXTI_DISABLE_EVENT : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_LPTIM1_EXTI_ENABLE_EVENT : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_LPTIM2_EXTI_DISABLE_EVENT : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_LPTIM2_EXTI_ENABLE_EVENT : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_RESET_COUNTER : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_RESET_COUNTER_AFTERREAD : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_RESET_HANDLE_STATE : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_START_CONTINUOUS : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_START_SINGLE : stm32wbxx_hal_lptim.h
  • __HAL_PCD_CLEAR_FLAG : stm32wbxx_hal_pcd.h
  • __HAL_PCD_DISABLE : stm32wbxx_hal_pcd.h
  • __HAL_PCD_ENABLE : stm32wbxx_hal_pcd.h
  • __HAL_PCD_GET_FLAG : stm32wbxx_hal_pcd.h
  • __HAL_PKA_CLEAR_FLAG : stm32wbxx_hal_pka.h
  • __HAL_PKA_DISABLE : stm32wbxx_hal_pka.h
  • __HAL_PKA_DISABLE_IT : stm32wbxx_hal_pka.h
  • __HAL_PKA_ENABLE : stm32wbxx_hal_pka.h
  • __HAL_PKA_ENABLE_IT : stm32wbxx_hal_pka.h
  • __HAL_PKA_GET_FLAG : stm32wbxx_hal_pka.h
  • __HAL_PKA_GET_IT_SOURCE : stm32wbxx_hal_pka.h
  • __HAL_PKA_RESET_HANDLE_STATE : stm32wbxx_hal_pka.h
  • __HAL_PKA_START : stm32wbxx_hal_pka.h
  • __HAL_PWR_CLEAR_FLAG : stm32wbxx_hal_pwr.h
  • __HAL_PWR_GET_FLAG : stm32wbxx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_CLEAR_FLAG : stm32wbxx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE : stm32wbxx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_IT : stm32wbxx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE : stm32wbxx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE : stm32wbxx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE : stm32wbxx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_IT : stm32wbxx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE : stm32wbxx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE : stm32wbxx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_GENERATE_SWIT : stm32wbxx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_GET_FLAG : stm32wbxx_hal_pwr.h
  • __HAL_PWR_PVD_EXTIC2_DISABLE_IT : stm32wbxx_hal_pwr.h
  • __HAL_PWR_PVD_EXTIC2_ENABLE_IT : stm32wbxx_hal_pwr.h
  • __HAL_PWR_PVM1_EXTI_CLEAR_FLAG : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_DISABLE_EVENT : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_DISABLE_IT : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_ENABLE_EVENT : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_ENABLE_IT : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_GENERATE_SWIT : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_GET_FLAG : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTIC2_DISABLE_EVENT : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTIC2_DISABLE_IT : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTIC2_ENABLE_EVENT : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTIC2_ENABLE_IT : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_CLEAR_FLAG : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_DISABLE_EVENT : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_DISABLE_IT : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_ENABLE_EVENT : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_ENABLE_IT : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_GENERATE_SWIT : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_GET_FLAG : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTIC2_DISABLE_EVENT : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTIC2_DISABLE_IT : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTIC2_ENABLE_EVENT : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTIC2_ENABLE_IT : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_VOLTAGESCALING_CONFIG : stm32wbxx_hal_pwr_ex.h
  • __HAL_QSPI_CLEAR_FLAG : stm32wbxx_hal_qspi.h
  • __HAL_QSPI_DISABLE : stm32wbxx_hal_qspi.h
  • __HAL_QSPI_DISABLE_IT : stm32wbxx_hal_qspi.h
  • __HAL_QSPI_ENABLE : stm32wbxx_hal_qspi.h
  • __HAL_QSPI_ENABLE_IT : stm32wbxx_hal_qspi.h
  • __HAL_QSPI_GET_FLAG : stm32wbxx_hal_qspi.h
  • __HAL_QSPI_GET_IT_SOURCE : stm32wbxx_hal_qspi.h
  • __HAL_QSPI_RESET_HANDLE_STATE : stm32wbxx_hal_qspi.h
  • __HAL_RCC_ADC_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_ADC_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_ADC_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_ADC_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_ADC_CONFIG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_ADC_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_ADC_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_ADC_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_ADC_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES1_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES1_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES2_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES2_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES2_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES2_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES2_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES2_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES2_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES2_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES2_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES2_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AHB1_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AHB1_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AHB2_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AHB2_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AHB3_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AHB3_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_APB1_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_APB1_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_APB1H_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_APB1H_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_APB1L_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_APB1L_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_APB2_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_APB2_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_APB3_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_APB3_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_BACKUPRESET_FORCE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_BACKUPRESET_RELEASE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2802_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2802_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2802_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2802_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2802_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2802_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2802_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2802_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2ADC_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2ADC_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2ADC_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2ADC_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2ADC_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2ADC_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2ADC_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2ADC_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2AES1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2AES1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2AES1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2AES1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2AES1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2AES1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2AES1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2AES1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2AES2_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2AES2_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2AES2_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2AES2_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2AES2_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2AES2_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2AES2_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2AES2_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2BLE_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2BLE_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2BLE_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2BLE_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2BLE_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2BLE_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2BLE_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2BLE_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2CRC_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2CRC_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2CRC_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2CRC_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2CRC_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2CRC_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2CRC_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2CRC_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2CRS_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2CRS_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2CRS_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2CRS_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2CRS_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2CRS_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2CRS_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2CRS_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMA1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMA1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMA1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMA1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMA1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMA1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMA1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMA1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMA2_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMA2_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMA2_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMA2_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMA2_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMA2_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMA2_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMA2_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMAMUX1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMAMUX1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMAMUX1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMAMUX1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMAMUX1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMAMUX1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMAMUX1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMAMUX1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2FLASH_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2FLASH_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2FLASH_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2FLASH_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2FLASH_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2FLASH_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2FLASH_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2FLASH_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOA_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOA_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOA_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOA_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOA_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOA_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOA_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOA_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOB_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOB_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOB_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOB_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOB_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOB_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOB_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOB_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOC_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOC_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOC_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOC_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOC_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOC_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOC_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOC_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOD_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOD_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOD_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOD_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOD_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOD_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOD_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOD_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOE_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOE_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOE_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOE_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOE_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOE_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOE_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOE_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOH_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOH_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOH_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOH_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOH_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOH_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOH_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOH_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2HSEM_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2HSEM_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2HSEM_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2HSEM_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2I2C1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2I2C1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2I2C1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2I2C1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2I2C1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2I2C1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2I2C1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2I2C1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2I2C3_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2I2C3_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2I2C3_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2I2C3_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2I2C3_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2I2C3_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2I2C3_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2I2C3_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2IPCC_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2IPCC_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2IPCC_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2IPCC_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LCD_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LCD_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LCD_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LCD_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LCD_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LCD_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LCD_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LCD_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPTIM1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPTIM1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPTIM1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPTIM1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPTIM1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPTIM1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPTIM1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPTIM1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPTIM2_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPTIM2_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPTIM2_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPTIM2_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPTIM2_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPTIM2_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPTIM2_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPTIM2_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPUART1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPUART1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPUART1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPUART1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPUART1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPUART1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPUART1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPUART1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2PKA_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2PKA_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2PKA_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2PKA_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2PKA_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2PKA_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2PKA_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2PKA_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2RNG_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2RNG_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2RNG_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2RNG_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2RNG_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2RNG_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2RNG_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2RNG_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2RTCAPB_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2RTCAPB_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2RTCAPB_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2RTCAPB_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2RTCAPB_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2RTCAPB_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2RTCAPB_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2RTCAPB_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SAI1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SAI1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SAI1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SAI1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SAI1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SAI1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SAI1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SAI1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SPI1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SPI1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SPI1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SPI1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SPI1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SPI1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SPI1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SPI1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SPI2_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SPI2_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SPI2_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SPI2_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SPI2_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SPI2_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SPI2_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SPI2_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SRAM1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SRAM1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SRAM1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SRAM1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SRAM1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SRAM1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SRAM1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SRAM1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SRAM2_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SRAM2_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SRAM2_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SRAM2_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM16_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM16_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM16_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM16_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM16_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM16_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM16_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM16_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM17_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM17_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM17_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM17_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM17_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM17_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM17_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM17_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM2_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM2_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM2_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM2_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM2_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM2_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM2_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM2_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TSC_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TSC_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TSC_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TSC_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TSC_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TSC_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TSC_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TSC_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2USART1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2USART1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2USART1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2USART1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2USART1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2USART1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2USART1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2USART1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2USB_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2USB_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2USB_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2USB_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2USB_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2USB_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2USB_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2USB_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CLEAR_IT : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CLEAR_RESET_FLAGS : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRC_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRC_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_CRS_CLEAR_FLAG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_CRS_CLEAR_IT : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_CRS_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRS_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRS_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRS_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRS_DISABLE_IT : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_CRS_ENABLE_IT : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_CRS_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_CRS_GET_FLAG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_CRS_GET_IT_SOURCE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_CRS_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRS_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRS_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRS_RELOADVALUE_CALCULATE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_DISABLE_IT : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA1_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA1_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA2_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA2_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_ENABLE_IT : stm32wbxx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_FLASH_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_FLASH_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_FLASH_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_FLASH_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GET_ADC_SOURCE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_GET_FLAG : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GET_I2C1_SOURCE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2C3_SOURCE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_GET_IT : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GET_LPTIM1_SOURCE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_GET_LPTIM2_SOURCE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_GET_LPUART1_SOURCE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_GET_MSI_RANGE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GET_PLL_OSCSOURCE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GET_PLLCLKOUT_CONFIG : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_GET_RFWAKEUP_SOURCE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_GET_RNG_SOURCE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_GET_RTC_SOURCE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GET_SAI1_SOURCE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_GET_SMPS_DIV : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_GET_SMPS_SOURCE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_GET_SMPS_SOURCE_STATUS : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_GET_SYSCLK_SOURCE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GET_USART1_SOURCE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_GET_USB_SOURCE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_GPIOA_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOA_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOA_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOB_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOB_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOC_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOC_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOD_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOD_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOE_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOE_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOH_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOH_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOH_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOH_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSE_AMPCONFIG : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSE_CAPACITORTUNING : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSE_CONFIG : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSE_CURRENTCONFIG : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSE_DIV2_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSE_DIV2_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSEM_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSEM_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSEM_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSEM_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSEM_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSEM_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSI48_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSI48_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSI_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSI_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSIAUTOMATIC_START_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSIAUTOMATIC_START_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSISTOP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSISTOP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C1_CONFIG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_I2C1_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C1_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C3_CONFIG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_I2C3_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C3_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_IPCC_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_IPCC_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_IPCC_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_IPCC_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_IPCC_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_IPCC_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LCD_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LCD_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LCD_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LCD_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LCD_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LCD_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LCD_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LCD_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CONFIG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM1_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CONFIG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM2_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM2_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM2_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM2_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPUART1_CONFIG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_LPUART1_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPUART1_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LSE_CONFIG : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_DISABLE_IT : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_ENABLE_IT : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_GET_FLAG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_LSEDRIVE_CONFIG : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LSI1_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LSI1_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LSI2_CALIBRATIONVALUE_ADJUST : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LSI2_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LSI2_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_MCO1_CONFIG : stm32wbxx_hal_rcc.h
  • __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST : stm32wbxx_hal_rcc.h
  • __HAL_RCC_MSI_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_MSI_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_MSI_RANGE_CONFIG : stm32wbxx_hal_rcc.h
  • __HAL_RCC_PKA_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_PKA_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_PKA_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_PKA_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_PKA_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_PKA_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_PKA_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_PKA_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_PKA_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_PKA_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_PLL_CONFIG : stm32wbxx_hal_rcc.h
  • __HAL_RCC_PLL_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_PLL_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_PLL_PLLM_CONFIG : stm32wbxx_hal_rcc.h
  • __HAL_RCC_PLL_PLLSOURCE_CONFIG : stm32wbxx_hal_rcc.h
  • __HAL_RCC_PLLCLKOUT_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_PLLCLKOUT_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_PLLSAI1_CLEAR_IT : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_CONFIG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_DISABLE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_DISABLE_IT : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_DIVP_CONFIG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_DIVQ_CONFIG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_DIVR_CONFIG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_ENABLE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_ENABLE_IT : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_GET_FLAG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_GET_IT_SOURCE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_MULN_CONFIG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1CLKOUT_DISABLE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1CLKOUT_ENABLE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_QUADSPI_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_QUADSPI_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_QUADSPI_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_QUADSPI_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_QUADSPI_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_QUADSPI_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RF_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RF_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RFWAKEUP_CONFIG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_RNG_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RNG_CONFIG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_RNG_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RNG_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RTC_CONFIG : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RTC_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RTC_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RTCAPB_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RTCAPB_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RTCAPB_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RTCAPB_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SAI1_CONFIG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_SAI1_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SAI1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SAI1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SAI1_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SMPS_CONFIG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_SMPS_DIV_CONFIG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SPI1_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SPI1_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SPI2_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SPI2_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SYSCLK_CONFIG : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM16_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM16_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM17_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM17_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM1_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM1_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM2_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM2_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TSC_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TSC_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TSC_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TSC_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TSC_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TSC_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TSC_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TSC_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USART1_CONFIG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_USART1_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USART1_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USB_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USB_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USB_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USB_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USB_CONFIG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_USB_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USB_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USB_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USB_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_WAKEUPSTOP_CLK_CONFIG : stm32wbxx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RNG_CLEAR_FLAG : stm32wbxx_hal_rng.h
  • __HAL_RNG_CLEAR_IT : stm32wbxx_hal_rng.h
  • __HAL_RNG_DISABLE : stm32wbxx_hal_rng.h
  • __HAL_RNG_DISABLE_IT : stm32wbxx_hal_rng.h
  • __HAL_RNG_ENABLE : stm32wbxx_hal_rng.h
  • __HAL_RNG_ENABLE_IT : stm32wbxx_hal_rng.h
  • __HAL_RNG_GET_FLAG : stm32wbxx_hal_rng.h
  • __HAL_RNG_GET_IT : stm32wbxx_hal_rng.h
  • __HAL_RNG_RESET_HANDLE_STATE : stm32wbxx_hal_rng.h
  • __HAL_RTC_ALARM_CLEAR_FLAG : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_DISABLE_IT : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_ENABLE_IT : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_CLEAR_FLAG : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_EVENT : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_IT : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_EVENT : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_IT : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_GENERATE_SWIT : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_GET_FLAG : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTIC2_CLEAR_FLAG : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTIC2_DISABLE_EVENT : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTIC2_DISABLE_IT : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTIC2_ENABLE_EVENT : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTIC2_ENABLE_IT : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTIC2_GET_FLAG : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_FLAG : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT_SOURCE : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARMA_DISABLE : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARMA_ENABLE : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARMB_DISABLE : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARMB_ENABLE : stm32wbxx_hal_rtc.h
  • __HAL_RTC_CALIBRATION_OUTPUT_DISABLE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_CALIBRATION_OUTPUT_ENABLE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_CLOCKREF_DETECTION_DISABLE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_CLOCKREF_DETECTION_ENABLE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_RESET_HANDLE_STATE : stm32wbxx_hal_rtc.h
  • __HAL_RTC_SHIFT_GET_FLAG : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER1_DISABLE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER1_ENABLE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER2_DISABLE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER2_ENABLE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER3_DISABLE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER3_ENABLE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_CLEAR_FLAG : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_DISABLE_IT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_ENABLE_IT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_FLAG : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT_SOURCE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_CLEAR_FLAG : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_DISABLE_EVENT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_DISABLE_IT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_ENABLE_EVENT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_ENABLE_IT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_GET_FLAG : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_CLEAR_FLAG : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_DISABLE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_DISABLE_IT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_ENABLE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_ENABLE_IT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_FLAG : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_IT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_IT_SOURCE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_DISABLE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_DISABLE_IT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_ENABLE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_ENABLE_IT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTIC2_CLEAR_FLAG : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTIC2_DISABLE_EVENT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTIC2_DISABLE_IT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTIC2_ENABLE_EVENT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTIC2_ENABLE_IT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTIC2_GET_FLAG : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_FLAG : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_IT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WRITEPROTECTION_DISABLE : stm32wbxx_hal_rtc.h
  • __HAL_RTC_WRITEPROTECTION_ENABLE : stm32wbxx_hal_rtc.h
  • __HAL_SAI_CLEAR_FLAG : stm32wbxx_hal_sai.h
  • __HAL_SAI_DISABLE : stm32wbxx_hal_sai.h
  • __HAL_SAI_DISABLE_IT : stm32wbxx_hal_sai.h
  • __HAL_SAI_ENABLE : stm32wbxx_hal_sai.h
  • __HAL_SAI_ENABLE_IT : stm32wbxx_hal_sai.h
  • __HAL_SAI_GET_FLAG : stm32wbxx_hal_sai.h
  • __HAL_SAI_GET_IT_SOURCE : stm32wbxx_hal_sai.h
  • __HAL_SAI_RESET_HANDLE_STATE : stm32wbxx_hal_sai.h
  • __HAL_SMARTCARD_CLEAR_FEFLAG : stm32wbxx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_FLAG : stm32wbxx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_IDLEFLAG : stm32wbxx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_IT : stm32wbxx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_NEFLAG : stm32wbxx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_OREFLAG : stm32wbxx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_PEFLAG : stm32wbxx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE : stm32wbxx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE_IT : stm32wbxx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE : stm32wbxx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE_IT : stm32wbxx_hal_smartcard.h
  • __HAL_SMARTCARD_FLUSH_DRREGISTER : stm32wbxx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_FLAG : stm32wbxx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_IT : stm32wbxx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_IT_SOURCE : stm32wbxx_hal_smartcard.h
  • __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE : stm32wbxx_hal_smartcard.h
  • __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE : stm32wbxx_hal_smartcard.h
  • __HAL_SMARTCARD_RESET_HANDLE_STATE : stm32wbxx_hal_smartcard.h
  • __HAL_SMARTCARD_SEND_REQ : stm32wbxx_hal_smartcard.h
  • __HAL_SMBUS_CLEAR_FLAG : stm32wbxx_hal_smbus.h
  • __HAL_SMBUS_DISABLE : stm32wbxx_hal_smbus.h
  • __HAL_SMBUS_DISABLE_IT : stm32wbxx_hal_smbus.h
  • __HAL_SMBUS_ENABLE : stm32wbxx_hal_smbus.h
  • __HAL_SMBUS_ENABLE_IT : stm32wbxx_hal_smbus.h
  • __HAL_SMBUS_GENERATE_NACK : stm32wbxx_hal_smbus.h
  • __HAL_SMBUS_GET_FLAG : stm32wbxx_hal_smbus.h
  • __HAL_SMBUS_GET_IT_SOURCE : stm32wbxx_hal_smbus.h
  • __HAL_SMBUS_RESET_HANDLE_STATE : stm32wbxx_hal_smbus.h
  • __HAL_SPI_CLEAR_CRCERRFLAG : stm32wbxx_hal_spi.h
  • __HAL_SPI_CLEAR_FREFLAG : stm32wbxx_hal_spi.h
  • __HAL_SPI_CLEAR_MODFFLAG : stm32wbxx_hal_spi.h
  • __HAL_SPI_CLEAR_OVRFLAG : stm32wbxx_hal_spi.h
  • __HAL_SPI_DISABLE : stm32wbxx_hal_spi.h
  • __HAL_SPI_DISABLE_IT : stm32wbxx_hal_spi.h
  • __HAL_SPI_ENABLE : stm32wbxx_hal_spi.h
  • __HAL_SPI_ENABLE_IT : stm32wbxx_hal_spi.h
  • __HAL_SPI_GET_FLAG : stm32wbxx_hal_spi.h
  • __HAL_SPI_GET_IT_SOURCE : stm32wbxx_hal_spi.h
  • __HAL_SPI_RESET_HANDLE_STATE : stm32wbxx_hal_spi.h
  • __HAL_SYSCFG_BREAK_ECC_LOCK : stm32wbxx_hal.h
  • __HAL_SYSCFG_BREAK_LOCKUP_LOCK : stm32wbxx_hal.h
  • __HAL_SYSCFG_BREAK_PVD_LOCK : stm32wbxx_hal.h
  • __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK : stm32wbxx_hal.h
  • __HAL_SYSCFG_CLEAR_FLAG : stm32wbxx_hal.h
  • __HAL_SYSCFG_FASTMODEPLUS_DISABLE : stm32wbxx_hal.h
  • __HAL_SYSCFG_FASTMODEPLUS_ENABLE : stm32wbxx_hal.h
  • __HAL_SYSCFG_FPU_INTERRUPT_DISABLE : stm32wbxx_hal.h
  • __HAL_SYSCFG_FPU_INTERRUPT_ENABLE : stm32wbxx_hal.h
  • __HAL_SYSCFG_GET_BOOT_MODE : stm32wbxx_hal.h
  • __HAL_SYSCFG_GET_FLAG : stm32wbxx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_FLASH : stm32wbxx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_QUADSPI : stm32wbxx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_SRAM : stm32wbxx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH : stm32wbxx_hal.h
  • __HAL_SYSCFG_SRAM2_ERASE : stm32wbxx_hal.h
  • __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE : stm32wbxx_hal.h
  • __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE : stm32wbxx_hal.h
  • __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE : stm32wbxx_hal.h
  • __HAL_SYSCFG_SRAM2_WRP_UNLOCK : stm32wbxx_hal.h
  • __HAL_TIM_CLEAR_FLAG : stm32wbxx_hal_tim.h
  • __HAL_TIM_CLEAR_IT : stm32wbxx_hal_tim.h
  • __HAL_TIM_DISABLE : stm32wbxx_hal_tim.h
  • __HAL_TIM_DISABLE_DMA : stm32wbxx_hal_tim.h
  • __HAL_TIM_DISABLE_IT : stm32wbxx_hal_tim.h
  • __HAL_TIM_DISABLE_OCxFAST : stm32wbxx_hal_tim.h
  • __HAL_TIM_DISABLE_OCxPRELOAD : stm32wbxx_hal_tim.h
  • __HAL_TIM_ENABLE : stm32wbxx_hal_tim.h
  • __HAL_TIM_ENABLE_DMA : stm32wbxx_hal_tim.h
  • __HAL_TIM_ENABLE_IT : stm32wbxx_hal_tim.h
  • __HAL_TIM_ENABLE_OCxFAST : stm32wbxx_hal_tim.h
  • __HAL_TIM_ENABLE_OCxPRELOAD : stm32wbxx_hal_tim.h
  • __HAL_TIM_GET_AUTORELOAD : stm32wbxx_hal_tim.h
  • __HAL_TIM_GET_CLOCKDIVISION : stm32wbxx_hal_tim.h
  • __HAL_TIM_GET_COMPARE : stm32wbxx_hal_tim.h
  • __HAL_TIM_GET_COUNTER : stm32wbxx_hal_tim.h
  • __HAL_TIM_GET_FLAG : stm32wbxx_hal_tim.h
  • __HAL_TIM_GET_ICPRESCALER : stm32wbxx_hal_tim.h
  • __HAL_TIM_GET_IT_SOURCE : stm32wbxx_hal_tim.h
  • __HAL_TIM_IS_TIM_COUNTING_DOWN : stm32wbxx_hal_tim.h
  • __HAL_TIM_MOE_DISABLE : stm32wbxx_hal_tim.h
  • __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY : stm32wbxx_hal_tim.h
  • __HAL_TIM_MOE_ENABLE : stm32wbxx_hal_tim.h
  • __HAL_TIM_RESET_HANDLE_STATE : stm32wbxx_hal_tim.h
  • __HAL_TIM_SET_AUTORELOAD : stm32wbxx_hal_tim.h
  • __HAL_TIM_SET_CAPTUREPOLARITY : stm32wbxx_hal_tim.h
  • __HAL_TIM_SET_CLOCKDIVISION : stm32wbxx_hal_tim.h
  • __HAL_TIM_SET_COMPARE : stm32wbxx_hal_tim.h
  • __HAL_TIM_SET_COUNTER : stm32wbxx_hal_tim.h
  • __HAL_TIM_SET_ICPRESCALER : stm32wbxx_hal_tim.h
  • __HAL_TIM_SET_PRESCALER : stm32wbxx_hal_tim.h
  • __HAL_TIM_URS_DISABLE : stm32wbxx_hal_tim.h
  • __HAL_TIM_URS_ENABLE : stm32wbxx_hal_tim.h
  • __HAL_TSC_CLEAR_FLAG : stm32wbxx_hal_tsc.h
  • __HAL_TSC_CLOSE_ANALOG_SWITCH : stm32wbxx_hal_tsc.h
  • __HAL_TSC_DISABLE : stm32wbxx_hal_tsc.h
  • __HAL_TSC_DISABLE_CHANNEL : stm32wbxx_hal_tsc.h
  • __HAL_TSC_DISABLE_GROUP : stm32wbxx_hal_tsc.h
  • __HAL_TSC_DISABLE_HYSTERESIS : stm32wbxx_hal_tsc.h
  • __HAL_TSC_DISABLE_IT : stm32wbxx_hal_tsc.h
  • __HAL_TSC_DISABLE_SAMPLING : stm32wbxx_hal_tsc.h
  • __HAL_TSC_ENABLE : stm32wbxx_hal_tsc.h
  • __HAL_TSC_ENABLE_CHANNEL : stm32wbxx_hal_tsc.h
  • __HAL_TSC_ENABLE_GROUP : stm32wbxx_hal_tsc.h
  • __HAL_TSC_ENABLE_HYSTERESIS : stm32wbxx_hal_tsc.h
  • __HAL_TSC_ENABLE_IT : stm32wbxx_hal_tsc.h
  • __HAL_TSC_ENABLE_SAMPLING : stm32wbxx_hal_tsc.h
  • __HAL_TSC_GET_FLAG : stm32wbxx_hal_tsc.h
  • __HAL_TSC_GET_GROUP_STATUS : stm32wbxx_hal_tsc.h
  • __HAL_TSC_GET_IT_SOURCE : stm32wbxx_hal_tsc.h
  • __HAL_TSC_OPEN_ANALOG_SWITCH : stm32wbxx_hal_tsc.h
  • __HAL_TSC_RESET_HANDLE_STATE : stm32wbxx_hal_tsc.h
  • __HAL_TSC_SET_IODEF_INFLOAT : stm32wbxx_hal_tsc.h
  • __HAL_TSC_SET_IODEF_OUTPPLOW : stm32wbxx_hal_tsc.h
  • __HAL_TSC_SET_SYNC_POL_FALL : stm32wbxx_hal_tsc.h
  • __HAL_TSC_SET_SYNC_POL_RISE_HIGH : stm32wbxx_hal_tsc.h
  • __HAL_TSC_START_ACQ : stm32wbxx_hal_tsc.h
  • __HAL_TSC_STOP_ACQ : stm32wbxx_hal_tsc.h
  • __HAL_UART_CLEAR_FEFLAG : stm32wbxx_hal_uart.h
  • __HAL_UART_CLEAR_FLAG : stm32wbxx_hal_uart.h
  • __HAL_UART_CLEAR_IDLEFLAG : stm32wbxx_hal_uart.h
  • __HAL_UART_CLEAR_IT : stm32wbxx_hal_uart.h
  • __HAL_UART_CLEAR_NEFLAG : stm32wbxx_hal_uart.h
  • __HAL_UART_CLEAR_OREFLAG : stm32wbxx_hal_uart.h
  • __HAL_UART_CLEAR_PEFLAG : stm32wbxx_hal_uart.h
  • __HAL_UART_CLEAR_TXFECF : stm32wbxx_hal_uart.h
  • __HAL_UART_DISABLE : stm32wbxx_hal_uart.h
  • __HAL_UART_DISABLE_IT : stm32wbxx_hal_uart.h
  • __HAL_UART_ENABLE : stm32wbxx_hal_uart.h
  • __HAL_UART_ENABLE_IT : stm32wbxx_hal_uart.h
  • __HAL_UART_FLUSH_DRREGISTER : stm32wbxx_hal_uart.h
  • __HAL_UART_GET_FLAG : stm32wbxx_hal_uart.h
  • __HAL_UART_GET_IT : stm32wbxx_hal_uart.h
  • __HAL_UART_GET_IT_SOURCE : stm32wbxx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_DISABLE : stm32wbxx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_ENABLE : stm32wbxx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_DISABLE : stm32wbxx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_ENABLE : stm32wbxx_hal_uart.h
  • __HAL_UART_ONE_BIT_SAMPLE_DISABLE : stm32wbxx_hal_uart.h
  • __HAL_UART_ONE_BIT_SAMPLE_ENABLE : stm32wbxx_hal_uart.h
  • __HAL_UART_RESET_HANDLE_STATE : stm32wbxx_hal_uart.h
  • __HAL_UART_SEND_REQ : stm32wbxx_hal_uart.h
  • __HAL_USART_CLEAR_FEFLAG : stm32wbxx_hal_usart.h
  • __HAL_USART_CLEAR_FLAG : stm32wbxx_hal_usart.h
  • __HAL_USART_CLEAR_IDLEFLAG : stm32wbxx_hal_usart.h
  • __HAL_USART_CLEAR_IT : stm32wbxx_hal_usart.h
  • __HAL_USART_CLEAR_NEFLAG : stm32wbxx_hal_usart.h
  • __HAL_USART_CLEAR_OREFLAG : stm32wbxx_hal_usart.h
  • __HAL_USART_CLEAR_PEFLAG : stm32wbxx_hal_usart.h
  • __HAL_USART_CLEAR_TXFECF : stm32wbxx_hal_usart.h
  • __HAL_USART_CLEAR_UDRFLAG : stm32wbxx_hal_usart.h
  • __HAL_USART_DISABLE : stm32wbxx_hal_usart.h
  • __HAL_USART_DISABLE_IT : stm32wbxx_hal_usart.h
  • __HAL_USART_ENABLE : stm32wbxx_hal_usart.h
  • __HAL_USART_ENABLE_IT : stm32wbxx_hal_usart.h
  • __HAL_USART_GET_FLAG : stm32wbxx_hal_usart.h
  • __HAL_USART_GET_IT : stm32wbxx_hal_usart.h
  • __HAL_USART_GET_IT_SOURCE : stm32wbxx_hal_usart.h
  • __HAL_USART_ONE_BIT_SAMPLE_DISABLE : stm32wbxx_hal_usart.h
  • __HAL_USART_ONE_BIT_SAMPLE_ENABLE : stm32wbxx_hal_usart.h
  • __HAL_USART_RESET_HANDLE_STATE : stm32wbxx_hal_usart.h
  • __HAL_USART_SEND_REQ : stm32wbxx_hal_usart.h
  • __HAL_USB_WAKEUP_EXTI_DISABLE_IT : stm32wbxx_hal_pcd.h
  • __HAL_USB_WAKEUP_EXTI_ENABLE_IT : stm32wbxx_hal_pcd.h
  • __HAL_WWDG_CLEAR_FLAG : stm32wbxx_hal_wwdg.h
  • __HAL_WWDG_CLEAR_IT : stm32wbxx_hal_wwdg.h
  • __HAL_WWDG_ENABLE : stm32wbxx_hal_wwdg.h
  • __HAL_WWDG_ENABLE_IT : stm32wbxx_hal_wwdg.h
  • __HAL_WWDG_GET_FLAG : stm32wbxx_hal_wwdg.h
  • __HAL_WWDG_GET_IT : stm32wbxx_hal_wwdg.h
  • __HAL_WWDG_GET_IT_SOURCE : stm32wbxx_hal_wwdg.h
  • __LL_ADC_ANALOGWD_CHANNEL_GROUP : stm32wbxx_ll_adc.h
  • __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION : stm32wbxx_ll_adc.h
  • __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION : stm32wbxx_ll_adc.h
  • __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW : stm32wbxx_ll_adc.h
  • __LL_ADC_CALC_DATA_TO_VOLTAGE : stm32wbxx_ll_adc.h
  • __LL_ADC_CALC_TEMPERATURE : stm32wbxx_ll_adc.h
  • __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS : stm32wbxx_ll_adc.h
  • __LL_ADC_CALC_VREFANALOG_VOLTAGE : stm32wbxx_ll_adc.h
  • __LL_ADC_CALIB_FACTOR_SINGLE_DIFF : stm32wbxx_ll_adc.h
  • __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL : stm32wbxx_ll_adc.h
  • __LL_ADC_CHANNEL_TO_DECIMAL_NB : stm32wbxx_ll_adc.h
  • __LL_ADC_COMMON_INSTANCE : stm32wbxx_ll_adc.h
  • __LL_ADC_CONVERT_DATA_RESOLUTION : stm32wbxx_ll_adc.h
  • __LL_ADC_DECIMAL_NB_TO_CHANNEL : stm32wbxx_ll_adc.h
  • __LL_ADC_DIGITAL_SCALE : stm32wbxx_ll_adc.h
  • __LL_ADC_IS_CHANNEL_INTERNAL : stm32wbxx_ll_adc.h
  • __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE : stm32wbxx_ll_adc.h
  • __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE : stm32wbxx_ll_adc.h
  • __LL_COMP_COMMON_INSTANCE : stm32wbxx_ll_comp.h
  • __LL_CRS_CALC_CALCULATE_RELOADVALUE : stm32wbxx_ll_crs.h
  • __LL_DMA_GET_CHANNEL : stm32wbxx_ll_dma.h
  • __LL_DMA_GET_CHANNEL_INSTANCE : stm32wbxx_ll_dma.h
  • __LL_DMA_GET_INSTANCE : stm32wbxx_ll_dma.h
  • __LL_DMA_INSTANCE_TO_CHANNEL : stm32wbxx_ll_dma.h
  • __LL_DMA_INSTANCE_TO_DMAMUX_CCR : stm32wbxx_ll_dma.h
  • __LL_I2C_CONVERT_TIMINGS : stm32wbxx_ll_i2c.h
  • __LL_LPUART_DIV : stm32wbxx_ll_lpuart.h
  • __LL_RCC_CALC_HCLK1_FREQ : stm32wbxx_ll_rcc.h
  • __LL_RCC_CALC_HCLK2_FREQ : stm32wbxx_ll_rcc.h
  • __LL_RCC_CALC_HCLK4_FREQ : stm32wbxx_ll_rcc.h
  • __LL_RCC_CALC_MSI_FREQ : stm32wbxx_ll_rcc.h
  • __LL_RCC_CALC_PCLK1_FREQ : stm32wbxx_ll_rcc.h
  • __LL_RCC_CALC_PCLK2_FREQ : stm32wbxx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_48M_FREQ : stm32wbxx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_ADC_FREQ : stm32wbxx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_FREQ : stm32wbxx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_SAI_FREQ : stm32wbxx_ll_rcc.h
  • __LL_RCC_CALC_PLLSAI1_48M_FREQ : stm32wbxx_ll_rcc.h
  • __LL_RCC_CALC_PLLSAI1_ADC_FREQ : stm32wbxx_ll_rcc.h
  • __LL_RCC_CALC_PLLSAI1_SAI_FREQ : stm32wbxx_ll_rcc.h
  • __LL_RTC_CONVERT_BCD2BIN : stm32wbxx_ll_rtc.h
  • __LL_RTC_CONVERT_BIN2BCD : stm32wbxx_ll_rtc.h
  • __LL_RTC_GET_DAY : stm32wbxx_ll_rtc.h
  • __LL_RTC_GET_HOUR : stm32wbxx_ll_rtc.h
  • __LL_RTC_GET_MINUTE : stm32wbxx_ll_rtc.h
  • __LL_RTC_GET_MONTH : stm32wbxx_ll_rtc.h
  • __LL_RTC_GET_SECOND : stm32wbxx_ll_rtc.h
  • __LL_RTC_GET_WEEKDAY : stm32wbxx_ll_rtc.h
  • __LL_RTC_GET_YEAR : stm32wbxx_ll_rtc.h
  • __LL_TIM_CALC_ARR : stm32wbxx_ll_tim.h
  • __LL_TIM_CALC_DEADTIME : stm32wbxx_ll_tim.h
  • __LL_TIM_CALC_DELAY : stm32wbxx_ll_tim.h
  • __LL_TIM_CALC_PSC : stm32wbxx_ll_tim.h
  • __LL_TIM_CALC_PULSE : stm32wbxx_ll_tim.h
  • __LL_TIM_GET_ICPSC_RATIO : stm32wbxx_ll_tim.h
  • __LL_TIM_GETFLAG_UIFCPY : stm32wbxx_ll_tim.h
  • __LL_USART_DIV_SAMPLING16 : stm32wbxx_ll_usart.h
  • __LL_USART_DIV_SAMPLING8 : stm32wbxx_ll_usart.h
  • __LSCO1_CLK_ENABLE : stm32wbxx_hal_rcc_ex.c
  • __LSCO2_CLK_ENABLE : stm32wbxx_hal_rcc_ex.c
  • __LSCO3_CLK_ENABLE : stm32wbxx_hal_rcc_ex.c
  • __MCO1_CLK_ENABLE : stm32wbxx_hal_rcc.c
  • __MCO2_CLK_ENABLE : stm32wbxx_hal_rcc.c
  • __MCO3_CLK_ENABLE : stm32wbxx_hal_rcc.c
  • __STM32WBxx_HAL_VERSION : stm32wbxx_hal.c
  • __STM32WBxx_HAL_VERSION_MAIN : stm32wbxx_hal.c
  • __STM32WBxx_HAL_VERSION_RC : stm32wbxx_hal.c
  • __STM32WBxx_HAL_VERSION_SUB1 : stm32wbxx_hal.c
  • __STM32WBxx_HAL_VERSION_SUB2 : stm32wbxx_hal.c
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- a -

  • ADC_ANALOGWATCHDOG_1 : stm32wbxx_hal_adc.h
  • ADC_ANALOGWATCHDOG_2 : stm32wbxx_hal_adc.h
  • ADC_ANALOGWATCHDOG_3 : stm32wbxx_hal_adc.h
  • ADC_ANALOGWATCHDOG_ALL_INJEC : stm32wbxx_hal_adc.h
  • ADC_ANALOGWATCHDOG_ALL_REG : stm32wbxx_hal_adc.h
  • ADC_ANALOGWATCHDOG_ALL_REGINJEC : stm32wbxx_hal_adc.h
  • ADC_ANALOGWATCHDOG_NONE : stm32wbxx_hal_adc.h
  • ADC_ANALOGWATCHDOG_SINGLE_INJEC : stm32wbxx_hal_adc.h
  • ADC_ANALOGWATCHDOG_SINGLE_REG : stm32wbxx_hal_adc.h
  • ADC_ANALOGWATCHDOG_SINGLE_REGINJEC : stm32wbxx_hal_adc.h
  • ADC_AWD1_EVENT : stm32wbxx_hal_adc.h
  • ADC_AWD1THRESHOLD_SHIFT_RESOLUTION : stm32wbxx_hal_adc_ex.h
  • ADC_AWD23THRESHOLD_SHIFT_RESOLUTION : stm32wbxx_hal_adc_ex.h
  • ADC_AWD2_EVENT : stm32wbxx_hal_adc.h
  • ADC_AWD3_EVENT : stm32wbxx_hal_adc.h
  • ADC_AWD_CR12_REGOFFSETGAP_MASK : stm32wbxx_ll_adc.h
  • ADC_AWD_CR12_REGOFFSETGAP_VAL : stm32wbxx_ll_adc.h
  • ADC_AWD_CR1_CHANNEL_MASK : stm32wbxx_ll_adc.h
  • ADC_AWD_CR1_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_AWD_CR23_CHANNEL_MASK : stm32wbxx_ll_adc.h
  • ADC_AWD_CR2_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_AWD_CR3_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_AWD_CR_ALL_CHANNEL_MASK : stm32wbxx_ll_adc.h
  • ADC_AWD_CRX_REGOFFSET_MASK : stm32wbxx_ll_adc.h
  • ADC_AWD_CRX_REGOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_AWD_EVENT : stm32wbxx_hal_adc.h
  • ADC_AWD_TR1_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_AWD_TR2_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_AWD_TR3_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_AWD_TRX_BIT_HIGH_MASK : stm32wbxx_ll_adc.h
  • ADC_AWD_TRX_BIT_HIGH_POS : stm32wbxx_ll_adc.h
  • ADC_AWD_TRX_BIT_HIGH_SHIFT4 : stm32wbxx_ll_adc.h
  • ADC_AWD_TRX_REGOFFSET_MASK : stm32wbxx_ll_adc.h
  • ADC_AWD_TRX_REGOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_BATTERY_VOLTAGE_INSTANCE : stm32wbxx_hal_adc_ex.h
  • ADC_CALIBRATION_TIMEOUT : stm32wbxx_hal_adc_ex.c
  • ADC_CFGR_AUTOWAIT : stm32wbxx_hal_adc_ex.h
  • ADC_CFGR_AWD1EN_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_CFGR_AWD1SGL_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_CFGR_CONTINUOUS : stm32wbxx_hal_adc_ex.h
  • ADC_CFGR_DFSDM : stm32wbxx_hal_adc_ex.h
  • ADC_CFGR_DISCONTINUOUS_NUM : stm32wbxx_hal_adc_ex.h
  • ADC_CFGR_DMACONTREQ : stm32wbxx_hal_adc_ex.h
  • ADC_CFGR_FIELDS : stm32wbxx_hal_adc_ex.h
  • ADC_CFGR_FIELDS_1 : stm32wbxx_hal_adc.c
  • ADC_CFGR_FIELDS_2 : stm32wbxx_hal_adc_ex.h
  • ADC_CFGR_INJECT_CONTEXT_QUEUE : stm32wbxx_hal_adc_ex.h
  • ADC_CFGR_INJECT_DISCCONTINUOUS : stm32wbxx_hal_adc_ex.h
  • ADC_CFGR_JAWD1EN_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_CFGR_REG_DISCONTINUOUS : stm32wbxx_hal_adc_ex.h
  • ADC_CFGR_RES_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_0 : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_0_BITFIELD : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_0_NUMBER : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_0_SMP : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_1 : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_10 : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_10_BITFIELD : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_10_NUMBER : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_10_SMP : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_11 : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_11_BITFIELD : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_11_NUMBER : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_11_SMP : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_12 : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_12_BITFIELD : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_12_NUMBER : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_12_SMP : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_13 : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_13_BITFIELD : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_13_NUMBER : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_13_SMP : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_14 : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_14_BITFIELD : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_14_NUMBER : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_14_SMP : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_15 : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_15_BITFIELD : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_15_NUMBER : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_15_SMP : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_16 : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_16_BITFIELD : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_16_NUMBER : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_16_SMP : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_17 : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_17_BITFIELD : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_17_NUMBER : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_17_SMP : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_18 : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_18_BITFIELD : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_18_NUMBER : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_18_SMP : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_1_BITFIELD : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_1_NUMBER : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_1_SMP : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_2 : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_2_BITFIELD : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_2_NUMBER : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_2_SMP : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_3 : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_3_BITFIELD : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_3_NUMBER : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_3_SMP : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_4 : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_4_BITFIELD : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_4_NUMBER : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_4_SMP : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_5 : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_5_BITFIELD : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_5_NUMBER : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_5_SMP : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_6 : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_6_BITFIELD : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_6_NUMBER : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_6_SMP : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_7 : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_7_BITFIELD : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_7_NUMBER : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_7_SMP : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_8 : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_8_BITFIELD : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_8_NUMBER : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_8_SMP : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_9 : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_9_BITFIELD : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_9_NUMBER : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_9_SMP : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_ID_BITFIELD_MASK : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_ID_INTERNAL_CH : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_ID_INTERNAL_CH_2 : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_ID_INTERNAL_CH_MASK : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_ID_MASK : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_MASK : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_SMPRX_REGOFFSET_MASK : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_SMPx_BITOFFSET_MASK : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_SMPx_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_TEMPSENSOR : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_VBAT : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_VREFINT : stm32wbxx_hal_adc.h
  • ADC_CLEAR_COMMON_CONTROL_REGISTER : stm32wbxx_hal_adc_ex.h
  • ADC_CLEAR_ERRORCODE : stm32wbxx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV1 : stm32wbxx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV10 : stm32wbxx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV12 : stm32wbxx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV128 : stm32wbxx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV16 : stm32wbxx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV2 : stm32wbxx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV256 : stm32wbxx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV32 : stm32wbxx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV4 : stm32wbxx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV6 : stm32wbxx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV64 : stm32wbxx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV8 : stm32wbxx_hal_adc.h
  • ADC_CLOCK_RATIO_VS_CPU_HIGHEST : stm32wbxx_ll_adc.c
  • ADC_CLOCK_SYNC_PCLK_DIV1 : stm32wbxx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV2 : stm32wbxx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV4 : stm32wbxx_hal_adc.h
  • ADC_CONVERSION_TIME_MAX_CPU_CYCLES : stm32wbxx_hal_adc.c
  • ADC_ConversionStop() : stm32wbxx_hal_adc.c
  • ADC_CR_BITS_PROPERTY_RS : stm32wbxx_ll_adc.h
  • ADC_DATAALIGN_LEFT : stm32wbxx_hal_adc.h
  • ADC_DATAALIGN_RIGHT : stm32wbxx_hal_adc.h
  • ADC_DIFFERENTIAL_ENDED : stm32wbxx_hal_adc_ex.h
  • ADC_Disable() : stm32wbxx_hal_adc.c
  • ADC_DISABLE_TIMEOUT : stm32wbxx_hal_adc.c
  • ADC_DMAConvCplt() : stm32wbxx_hal_adc.c
  • ADC_DMAError() : stm32wbxx_hal_adc.c
  • ADC_DMAHalfConvCplt() : stm32wbxx_hal_adc.c
  • ADC_Enable() : stm32wbxx_hal_adc.c
  • ADC_ENABLE_TIMEOUT : stm32wbxx_hal_adc.c
  • ADC_EOC_SEQ_CONV : stm32wbxx_hal_adc.h
  • ADC_EOC_SINGLE_CONV : stm32wbxx_hal_adc.h
  • ADC_EOSMP_EVENT : stm32wbxx_hal_adc.h
  • ADC_EXTERNALTRIG_EXT_IT11 : stm32wbxx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_CC1 : stm32wbxx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_CC2 : stm32wbxx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_CC3 : stm32wbxx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_TRGO : stm32wbxx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_TRGO2 : stm32wbxx_hal_adc.h
  • ADC_EXTERNALTRIG_T2_CC2 : stm32wbxx_hal_adc.h
  • ADC_EXTERNALTRIG_T2_TRGO : stm32wbxx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_FALLING : stm32wbxx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_NONE : stm32wbxx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_RISING : stm32wbxx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING : stm32wbxx_hal_adc.h
  • ADC_EXTERNALTRIGINJEC_EXT_IT15 : stm32wbxx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T1_CC4 : stm32wbxx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T1_TRGO : stm32wbxx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T1_TRGO2 : stm32wbxx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T2_CC1 : stm32wbxx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T2_TRGO : stm32wbxx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING : stm32wbxx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_NONE : stm32wbxx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_RISING : stm32wbxx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING : stm32wbxx_hal_adc_ex.h
  • ADC_FLAG_AWD1 : stm32wbxx_hal_adc.h
  • ADC_FLAG_AWD2 : stm32wbxx_hal_adc.h
  • ADC_FLAG_AWD3 : stm32wbxx_hal_adc.h
  • ADC_FLAG_EOC : stm32wbxx_hal_adc.h
  • ADC_FLAG_EOS : stm32wbxx_hal_adc.h
  • ADC_FLAG_EOSMP : stm32wbxx_hal_adc.h
  • ADC_FLAG_JEOC : stm32wbxx_hal_adc.h
  • ADC_FLAG_JEOS : stm32wbxx_hal_adc.h
  • ADC_FLAG_JQOVF : stm32wbxx_hal_adc.h
  • ADC_FLAG_OVR : stm32wbxx_hal_adc.h
  • ADC_FLAG_RDY : stm32wbxx_hal_adc.h
  • ADC_GET_RESOLUTION : stm32wbxx_hal_adc.h
  • ADC_HandleTypeDef : stm32wbxx_hal_adc.h
  • ADC_INJ_JDRX_REGOFFSET_MASK : stm32wbxx_ll_adc.h
  • ADC_INJ_RANK_1_JSQR_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_INJ_RANK_2_JSQR_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_INJ_RANK_3_JSQR_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_INJ_RANK_4_JSQR_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_INJ_RANK_ID_JSQR_MASK : stm32wbxx_ll_adc.h
  • ADC_INJ_TRIG_EDGE_MASK : stm32wbxx_ll_adc.h
  • ADC_INJ_TRIG_EXT_EDGE_DEFAULT : stm32wbxx_ll_adc.h
  • ADC_INJ_TRIG_EXTEN_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_INJ_TRIG_SOURCE_MASK : stm32wbxx_ll_adc.h
  • ADC_INJECTED_GROUP : stm32wbxx_hal_adc_ex.h
  • ADC_INJECTED_RANK_1 : stm32wbxx_hal_adc_ex.h
  • ADC_INJECTED_RANK_2 : stm32wbxx_hal_adc_ex.h
  • ADC_INJECTED_RANK_3 : stm32wbxx_hal_adc_ex.h
  • ADC_INJECTED_RANK_4 : stm32wbxx_hal_adc_ex.h
  • ADC_INJECTED_SOFTWARE_START : stm32wbxx_hal_adc_ex.h
  • ADC_IS_INDEPENDENT : stm32wbxx_hal_adc_ex.h
  • ADC_IS_SOFTWARE_START_INJECTED : stm32wbxx_hal_adc_ex.h
  • ADC_IT_AWD : stm32wbxx_hal_adc.h
  • ADC_IT_AWD1 : stm32wbxx_hal_adc.h
  • ADC_IT_AWD2 : stm32wbxx_hal_adc.h
  • ADC_IT_AWD3 : stm32wbxx_hal_adc.h
  • ADC_IT_EOC : stm32wbxx_hal_adc.h
  • ADC_IT_EOS : stm32wbxx_hal_adc.h
  • ADC_IT_EOSMP : stm32wbxx_hal_adc.h
  • ADC_IT_JEOC : stm32wbxx_hal_adc.h
  • ADC_IT_JEOS : stm32wbxx_hal_adc.h
  • ADC_IT_JQOVF : stm32wbxx_hal_adc.h
  • ADC_IT_OVR : stm32wbxx_hal_adc.h
  • ADC_IT_RDY : stm32wbxx_hal_adc.h
  • ADC_JDR1_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_JDR2_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_JDR3_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_JDR4_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_JDRX_REGOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_JQOVF_EVENT : stm32wbxx_hal_adc.h
  • ADC_JSQR_FIELDS : stm32wbxx_hal_adc_ex.c
  • ADC_JSQR_RK : stm32wbxx_hal_adc_ex.h
  • ADC_OFFSET_1 : stm32wbxx_hal_adc_ex.h
  • ADC_OFFSET_2 : stm32wbxx_hal_adc_ex.h
  • ADC_OFFSET_3 : stm32wbxx_hal_adc_ex.h
  • ADC_OFFSET_4 : stm32wbxx_hal_adc_ex.h
  • ADC_OFFSET_NONE : stm32wbxx_hal_adc_ex.h
  • ADC_OFFSET_SHIFT_RESOLUTION : stm32wbxx_hal_adc_ex.h
  • ADC_OFR1_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_OFR2_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_OFR3_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_OFR4_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_OFRx_REGOFFSET_MASK : stm32wbxx_ll_adc.h
  • ADC_OVERSAMPLING_RATIO_128 : stm32wbxx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_16 : stm32wbxx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_2 : stm32wbxx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_256 : stm32wbxx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_32 : stm32wbxx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_4 : stm32wbxx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_64 : stm32wbxx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_8 : stm32wbxx_hal_adc.h
  • ADC_OVR_DATA_OVERWRITTEN : stm32wbxx_hal_adc.h
  • ADC_OVR_DATA_PRESERVED : stm32wbxx_hal_adc.h
  • ADC_OVR_EVENT : stm32wbxx_hal_adc.h
  • ADC_REG_RANK_10_SQRX_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_REG_RANK_11_SQRX_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_REG_RANK_12_SQRX_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_REG_RANK_13_SQRX_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_REG_RANK_14_SQRX_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_REG_RANK_15_SQRX_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_REG_RANK_16_SQRX_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_REG_RANK_1_SQRX_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_REG_RANK_2_SQRX_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_REG_RANK_3_SQRX_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_REG_RANK_4_SQRX_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_REG_RANK_5_SQRX_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_REG_RANK_6_SQRX_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_REG_RANK_7_SQRX_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_REG_RANK_8_SQRX_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_REG_RANK_9_SQRX_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_REG_RANK_ID_SQRX_MASK : stm32wbxx_ll_adc.h
  • ADC_REG_SQRX_REGOFFSET_MASK : stm32wbxx_ll_adc.h
  • ADC_REG_TRIG_EDGE_MASK : stm32wbxx_ll_adc.h
  • ADC_REG_TRIG_EXT_EDGE_DEFAULT : stm32wbxx_ll_adc.h
  • ADC_REG_TRIG_EXTEN_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_REG_TRIG_EXTSEL_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_REG_TRIG_SOURCE_MASK : stm32wbxx_ll_adc.h
  • ADC_REGOVERSAMPLING_CONTINUED_MODE : stm32wbxx_hal_adc.h
  • ADC_REGOVERSAMPLING_RESUMED_MODE : stm32wbxx_hal_adc.h
  • ADC_REGULAR_GROUP : stm32wbxx_hal_adc_ex.h
  • ADC_REGULAR_INJECTED_GROUP : stm32wbxx_hal_adc_ex.h
  • ADC_REGULAR_RANK_1 : stm32wbxx_hal_adc.h
  • ADC_REGULAR_RANK_10 : stm32wbxx_hal_adc.h
  • ADC_REGULAR_RANK_11 : stm32wbxx_hal_adc.h
  • ADC_REGULAR_RANK_12 : stm32wbxx_hal_adc.h
  • ADC_REGULAR_RANK_13 : stm32wbxx_hal_adc.h
  • ADC_REGULAR_RANK_14 : stm32wbxx_hal_adc.h
  • ADC_REGULAR_RANK_15 : stm32wbxx_hal_adc.h
  • ADC_REGULAR_RANK_16 : stm32wbxx_hal_adc.h
  • ADC_REGULAR_RANK_2 : stm32wbxx_hal_adc.h
  • ADC_REGULAR_RANK_3 : stm32wbxx_hal_adc.h
  • ADC_REGULAR_RANK_4 : stm32wbxx_hal_adc.h
  • ADC_REGULAR_RANK_5 : stm32wbxx_hal_adc.h
  • ADC_REGULAR_RANK_6 : stm32wbxx_hal_adc.h
  • ADC_REGULAR_RANK_7 : stm32wbxx_hal_adc.h
  • ADC_REGULAR_RANK_8 : stm32wbxx_hal_adc.h
  • ADC_REGULAR_RANK_9 : stm32wbxx_hal_adc.h
  • ADC_RESOLUTION_10B : stm32wbxx_hal_adc.h
  • ADC_RESOLUTION_12B : stm32wbxx_hal_adc.h
  • ADC_RESOLUTION_6B : stm32wbxx_hal_adc.h
  • ADC_RESOLUTION_8B : stm32wbxx_hal_adc.h
  • ADC_RIGHTBITSHIFT_1 : stm32wbxx_hal_adc.h
  • ADC_RIGHTBITSHIFT_2 : stm32wbxx_hal_adc.h
  • ADC_RIGHTBITSHIFT_3 : stm32wbxx_hal_adc.h
  • ADC_RIGHTBITSHIFT_4 : stm32wbxx_hal_adc.h
  • ADC_RIGHTBITSHIFT_5 : stm32wbxx_hal_adc.h
  • ADC_RIGHTBITSHIFT_6 : stm32wbxx_hal_adc.h
  • ADC_RIGHTBITSHIFT_7 : stm32wbxx_hal_adc.h
  • ADC_RIGHTBITSHIFT_8 : stm32wbxx_hal_adc.h
  • ADC_RIGHTBITSHIFT_NONE : stm32wbxx_hal_adc.h
  • ADC_SAMPLETIME_12CYCLES_5 : stm32wbxx_hal_adc.h
  • ADC_SAMPLETIME_247CYCLES_5 : stm32wbxx_hal_adc.h
  • ADC_SAMPLETIME_24CYCLES_5 : stm32wbxx_hal_adc.h
  • ADC_SAMPLETIME_2CYCLES_5 : stm32wbxx_hal_adc.h
  • ADC_SAMPLETIME_47CYCLES_5 : stm32wbxx_hal_adc.h
  • ADC_SAMPLETIME_640CYCLES_5 : stm32wbxx_hal_adc.h
  • ADC_SAMPLETIME_6CYCLES_5 : stm32wbxx_hal_adc.h
  • ADC_SAMPLETIME_92CYCLES_5 : stm32wbxx_hal_adc.h
  • ADC_SCAN_DISABLE : stm32wbxx_hal_adc.h
  • ADC_SCAN_ENABLE : stm32wbxx_hal_adc.h
  • ADC_SINGLE_ENDED : stm32wbxx_hal_adc_ex.h
  • ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK : stm32wbxx_ll_adc.h
  • ADC_SINGLEDIFF_CALIB_F_BIT_D_POS : stm32wbxx_ll_adc.h
  • ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 : stm32wbxx_ll_adc.h
  • ADC_SINGLEDIFF_CALIB_FACTOR_MASK : stm32wbxx_ll_adc.h
  • ADC_SINGLEDIFF_CALIB_START_MASK : stm32wbxx_ll_adc.h
  • ADC_SINGLEDIFF_CHANNEL_MASK : stm32wbxx_ll_adc.h
  • ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK : stm32wbxx_ll_adc.h
  • ADC_SMPR1_FIELDS : stm32wbxx_hal_adc_ex.h
  • ADC_SMPR1_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_SMPR2_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_SMPRX_REGOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_SOFTWARE_START : stm32wbxx_hal_adc.h
  • ADC_SQR1_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_SQR2_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_SQR3_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_SQR4_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_SQRX_REGOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_STATE_CLR_SET : stm32wbxx_hal_adc.h
  • ADC_STOP_CONVERSION_TIMEOUT : stm32wbxx_hal_adc.h
  • ADC_TEMPERATURE_SENSOR_INSTANCE : stm32wbxx_hal_adc_ex.h
  • ADC_TEMPSENSOR_DELAY_US : stm32wbxx_hal_adc.h
  • ADC_TIMEOUT_DISABLE_CPU_CYCLES : stm32wbxx_ll_adc.c
  • ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES : stm32wbxx_ll_adc.c
  • ADC_TR1_HT1_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_TRIGGEREDMODE_MULTI_TRIGGER : stm32wbxx_hal_adc.h
  • ADC_TRIGGEREDMODE_SINGLE_TRIGGER : stm32wbxx_hal_adc.h
  • ADC_VREFINT_INSTANCE : stm32wbxx_hal_adc_ex.h
  • assert_param : stm32wbxx_ll_gpio.c , stm32wbxx_ll_i2c.c , stm32wbxx_ll_utils.c , stm32wbxx_ll_adc.c , stm32wbxx_ll_pka.c , stm32wbxx_ll_lptim.c , stm32wbxx_ll_dma.c , stm32wbxx_ll_exti.c , stm32wbxx_ll_lpuart.c , stm32wbxx_ll_rtc.c , stm32wbxx_ll_spi.c , stm32wbxx_ll_comp.c , stm32wbxx_ll_rng.c , stm32wbxx_ll_tim.c , stm32wbxx_hal_conf.h , stm32wbxx_ll_rcc.c , stm32wbxx_ll_crc.c , stm32wbxx_ll_usart.c
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

  • File List
  • Globals
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  • Functions
  • Variables
  • Typedefs
  • Enumerations
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- b -

  • BDCR_REG_INDEX : stm32wbxx_hal_rcc.h
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
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  • r
  • s
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  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- c -

  • CHANNEL_INDEX_Msk : stm32wbxx_hal_ipcc.c
  • ChannelCb : stm32wbxx_hal_ipcc.h
  • CLK48_MASK : stm32wbxx_hal_rcc_ex.h
  • CLOCKSMPS_TIMEOUT_VALUE : stm32wbxx_hal_rcc_ex.c
  • CLOCKSWITCH_TIMEOUT_VALUE : stm32wbxx_hal_rcc.c
  • COMP_BLANKINGSRC_NONE : stm32wbxx_hal_comp.h
  • COMP_BLANKINGSRC_TIM1_OC5 : stm32wbxx_hal_comp.h
  • COMP_BLANKINGSRC_TIM2_OC3 : stm32wbxx_hal_comp.h
  • COMP_CLEAR_ERRORCODE : stm32wbxx_hal_comp.h
  • COMP_DELAY_STARTUP_US : stm32wbxx_hal_comp.c
  • COMP_DELAY_VOLTAGE_SCALER_STAB_US : stm32wbxx_hal_comp.c
  • COMP_EXTI_EVENT : stm32wbxx_hal_comp.h
  • COMP_EXTI_FALLING : stm32wbxx_hal_comp.h
  • COMP_EXTI_IT : stm32wbxx_hal_comp.h
  • COMP_EXTI_LINE_COMP1 : stm32wbxx_hal_comp.h
  • COMP_EXTI_LINE_COMP2 : stm32wbxx_hal_comp.h
  • COMP_EXTI_RISING : stm32wbxx_hal_comp.h
  • COMP_GET_EXTI_LINE : stm32wbxx_hal_comp.h
  • COMP_HandleTypeDef : stm32wbxx_hal_comp.h
  • COMP_HYSTERESIS_HIGH : stm32wbxx_hal_comp.h
  • COMP_HYSTERESIS_LOW : stm32wbxx_hal_comp.h
  • COMP_HYSTERESIS_MEDIUM : stm32wbxx_hal_comp.h
  • COMP_HYSTERESIS_NONE : stm32wbxx_hal_comp.h
  • COMP_INPUT_MINUS_1_2VREFINT : stm32wbxx_hal_comp.h
  • COMP_INPUT_MINUS_1_4VREFINT : stm32wbxx_hal_comp.h
  • COMP_INPUT_MINUS_3_4VREFINT : stm32wbxx_hal_comp.h
  • COMP_INPUT_MINUS_IO1 : stm32wbxx_hal_comp.h
  • COMP_INPUT_MINUS_IO2 : stm32wbxx_hal_comp.h
  • COMP_INPUT_MINUS_IO3 : stm32wbxx_hal_comp.h
  • COMP_INPUT_MINUS_IO4 : stm32wbxx_hal_comp.h
  • COMP_INPUT_MINUS_IO5 : stm32wbxx_hal_comp.h
  • COMP_INPUT_MINUS_VREFINT : stm32wbxx_hal_comp.h
  • COMP_INPUT_PLUS_IO1 : stm32wbxx_hal_comp.h
  • COMP_INPUT_PLUS_IO2 : stm32wbxx_hal_comp.h
  • COMP_INPUT_PLUS_IO3 : stm32wbxx_hal_comp.h
  • COMP_OUTPUT_LEVEL_BITOFFSET_POS : stm32wbxx_hal_comp.c
  • COMP_OUTPUT_LEVEL_HIGH : stm32wbxx_hal_comp.h
  • COMP_OUTPUT_LEVEL_LOW : stm32wbxx_hal_comp.h
  • COMP_OUTPUTPOL_INVERTED : stm32wbxx_hal_comp.h
  • COMP_OUTPUTPOL_NONINVERTED : stm32wbxx_hal_comp.h
  • COMP_POWERMODE_HIGHSPEED : stm32wbxx_hal_comp.h
  • COMP_POWERMODE_MEDIUMSPEED : stm32wbxx_hal_comp.h
  • COMP_POWERMODE_ULTRALOWPOWER : stm32wbxx_hal_comp.h
  • COMP_STATE_BITFIELD_LOCK : stm32wbxx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_FALLING : stm32wbxx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_RISING : stm32wbxx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_RISING_FALLING : stm32wbxx_hal_comp.h
  • COMP_TRIGGERMODE_IT_FALLING : stm32wbxx_hal_comp.h
  • COMP_TRIGGERMODE_IT_RISING : stm32wbxx_hal_comp.h
  • COMP_TRIGGERMODE_IT_RISING_FALLING : stm32wbxx_hal_comp.h
  • COMP_TRIGGERMODE_NONE : stm32wbxx_hal_comp.h
  • COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON : stm32wbxx_hal_comp.h
  • COMP_WINDOWMODE_DISABLE : stm32wbxx_hal_comp.h
  • countof : stm32wbxx_ll_utils.c
  • CR_REG_INDEX : stm32wbxx_hal_rcc.h
  • CRC_Handle_16() : stm32wbxx_hal_crc.c
  • CRC_Handle_8() : stm32wbxx_hal_crc.c
  • CRC_INPUTDATA_FORMAT_BYTES : stm32wbxx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_HALFWORDS : stm32wbxx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_UNDEFINED : stm32wbxx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_WORDS : stm32wbxx_hal_crc.h
  • CRC_INPUTDATA_INVERSION_BYTE : stm32wbxx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_HALFWORD : stm32wbxx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_NONE : stm32wbxx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_WORD : stm32wbxx_hal_crc_ex.h
  • CRC_OUTPUTDATA_INVERSION_DISABLE : stm32wbxx_hal_crc_ex.h
  • CRC_OUTPUTDATA_INVERSION_ENABLE : stm32wbxx_hal_crc_ex.h
  • CRC_POLYLENGTH_16B : stm32wbxx_hal_crc.h
  • CRC_POLYLENGTH_32B : stm32wbxx_hal_crc.h
  • CRC_POLYLENGTH_7B : stm32wbxx_hal_crc.h
  • CRC_POLYLENGTH_8B : stm32wbxx_hal_crc.h
  • CRRCR_REG_INDEX : stm32wbxx_hal_rcc.h
  • CRS_POSITION_FECAP : stm32wbxx_ll_crs.h
  • CRS_POSITION_FELIM : stm32wbxx_ll_crs.h
  • CRS_POSITION_TRIM : stm32wbxx_ll_crs.h
  • CRYP_AES_CBC : stm32wbxx_hal_cryp.h
  • CRYP_AES_CCM : stm32wbxx_hal_cryp.h
  • CRYP_AES_CTR : stm32wbxx_hal_cryp.h
  • CRYP_AES_Decrypt() : stm32wbxx_hal_cryp.c
  • CRYP_AES_Decrypt_DMA() : stm32wbxx_hal_cryp.c
  • CRYP_AES_Decrypt_IT() : stm32wbxx_hal_cryp.c
  • CRYP_AES_ECB : stm32wbxx_hal_cryp.h
  • CRYP_AES_Encrypt() : stm32wbxx_hal_cryp.c
  • CRYP_AES_Encrypt_IT() : stm32wbxx_hal_cryp.c
  • CRYP_AES_GCM_GMAC : stm32wbxx_hal_cryp.h
  • CRYP_AES_IT() : stm32wbxx_hal_cryp.c
  • CRYP_AES_ProcessData() : stm32wbxx_hal_cryp.c
  • CRYP_AESCCM_Process() : stm32wbxx_hal_cryp.c
  • CRYP_AESCCM_Process_DMA() : stm32wbxx_hal_cryp.c
  • CRYP_AESCCM_Process_IT() : stm32wbxx_hal_cryp.c
  • CRYP_AESGCM_Process() : stm32wbxx_hal_cryp.c
  • CRYP_AESGCM_Process_DMA() : stm32wbxx_hal_cryp.c
  • CRYP_AESGCM_Process_IT() : stm32wbxx_hal_cryp.c
  • CRYP_CCF_CLEAR : stm32wbxx_hal_cryp.h
  • CRYP_CCM_CTR0_0 : stm32wbxx_hal_cryp_ex.c
  • CRYP_CCM_CTR0_3 : stm32wbxx_hal_cryp_ex.c
  • CRYP_CCM_CTR1_0 : stm32wbxx_hal_cryp.c
  • CRYP_CCM_CTR1_1 : stm32wbxx_hal_cryp.c
  • CRYP_CCM_CTR1_2 : stm32wbxx_hal_cryp.c
  • CRYP_DATATYPE_16B : stm32wbxx_hal_cryp.h
  • CRYP_DATATYPE_1B : stm32wbxx_hal_cryp.h
  • CRYP_DATATYPE_32B : stm32wbxx_hal_cryp.h
  • CRYP_DATATYPE_8B : stm32wbxx_hal_cryp.h
  • CRYP_DATAWIDTHUNIT_BYTE : stm32wbxx_hal_cryp.h
  • CRYP_DATAWIDTHUNIT_WORD : stm32wbxx_hal_cryp.h
  • CRYP_DMAError() : stm32wbxx_hal_cryp.c
  • CRYP_DMAInCplt() : stm32wbxx_hal_cryp.c
  • CRYP_DMAOutCplt() : stm32wbxx_hal_cryp.c
  • CRYP_ERR_CLEAR : stm32wbxx_hal_cryp.h
  • CRYP_FLAG_BUSY : stm32wbxx_hal_cryp.h
  • CRYP_FLAG_CCF : stm32wbxx_hal_cryp.h
  • CRYP_FLAG_MASK : stm32wbxx_hal_cryp.h
  • CRYP_FLAG_RDERR : stm32wbxx_hal_cryp.h
  • CRYP_FLAG_WRERR : stm32wbxx_hal_cryp.h
  • CRYP_GCMCCM_SetHeaderPhase() : stm32wbxx_hal_cryp.c
  • CRYP_GCMCCM_SetHeaderPhase_DMA() : stm32wbxx_hal_cryp.c
  • CRYP_GCMCCM_SetHeaderPhase_IT() : stm32wbxx_hal_cryp.c
  • CRYP_GCMCCM_SetPayloadPhase_IT() : stm32wbxx_hal_cryp.c
  • CRYP_HandleTypeDef : stm32wbxx_hal_cryp.h
  • CRYP_IT_CCF : stm32wbxx_hal_cryp.h
  • CRYP_IT_CCFIE : stm32wbxx_hal_cryp.h
  • CRYP_IT_ERRIE : stm32wbxx_hal_cryp.h
  • CRYP_IT_RDERR : stm32wbxx_hal_cryp.h
  • CRYP_IT_WRERR : stm32wbxx_hal_cryp.h
  • CRYP_KEYIVCONFIG_ALWAYS : stm32wbxx_hal_cryp.h
  • CRYP_KEYIVCONFIG_ONCE : stm32wbxx_hal_cryp.h
  • CRYP_KEYSIZE_128B : stm32wbxx_hal_cryp.h
  • CRYP_KEYSIZE_256B : stm32wbxx_hal_cryp.h
  • CRYP_OPERATINGMODE_DECRYPT : stm32wbxx_hal_cryp.c , stm32wbxx_hal_cryp_ex.c
  • CRYP_OPERATINGMODE_ENCRYPT : stm32wbxx_hal_cryp_ex.c , stm32wbxx_hal_cryp.c
  • CRYP_OPERATINGMODE_KEYDERIVATION : stm32wbxx_hal_cryp_ex.c , stm32wbxx_hal_cryp.c
  • CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT : stm32wbxx_hal_cryp.c , stm32wbxx_hal_cryp_ex.c
  • CRYP_PHASE_FINAL : stm32wbxx_hal_cryp_ex.c , stm32wbxx_hal_cryp.c
  • CRYP_PHASE_HEADER : stm32wbxx_hal_cryp.c , stm32wbxx_hal_cryp_ex.c
  • CRYP_PHASE_INIT : stm32wbxx_hal_cryp.c , stm32wbxx_hal_cryp_ex.c
  • CRYP_PHASE_PAYLOAD : stm32wbxx_hal_cryp_ex.c , stm32wbxx_hal_cryp.c
  • CRYP_PHASE_PROCESS : stm32wbxx_hal_cryp.c
  • CRYP_PHASE_READY : stm32wbxx_hal_cryp.c
  • CRYP_SET_PHASE : stm32wbxx_hal_cryp.c
  • CRYP_SetDMAConfig() : stm32wbxx_hal_cryp.c
  • CRYP_SetKey() : stm32wbxx_hal_cryp.c
  • CRYP_TIMEOUT_GCMCCMHEADERPHASE : stm32wbxx_hal_cryp.c
  • CRYP_TIMEOUT_GCMCCMINITPHASE : stm32wbxx_hal_cryp.c
  • CRYP_TIMEOUT_KEYPREPARATION : stm32wbxx_hal_cryp.c
  • CRYP_WaitOnCCFlag() : stm32wbxx_hal_cryp.c
  • CRYPEx_PHASE_FINAL : stm32wbxx_hal_cryp_ex.c
  • CRYPEx_PHASE_PROCESS : stm32wbxx_hal_cryp_ex.c
  • CSR_REG_INDEX : stm32wbxx_hal_rcc.h
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- d -

  • DATA_CACHE_ENABLE : stm32wbxx_hal_conf.h
  • DEFAULT_CRC32_POLY : stm32wbxx_hal_crc.h
  • DEFAULT_CRC_INITVALUE : stm32wbxx_hal_crc.h
  • DEFAULT_INIT_VALUE_DISABLE : stm32wbxx_hal_crc.h
  • DEFAULT_INIT_VALUE_ENABLE : stm32wbxx_hal_crc.h
  • DEFAULT_POLYNOMIAL_DISABLE : stm32wbxx_hal_crc.h
  • DEFAULT_POLYNOMIAL_ENABLE : stm32wbxx_hal_crc.h
  • DMA_CalcDMAMUXChannelBaseAndMask() : stm32wbxx_hal_dma.c
  • DMA_CalcDMAMUXRequestGenBaseAndMask() : stm32wbxx_hal_dma.c
  • DMA_CIRCULAR : stm32wbxx_hal_dma.h
  • DMA_FLAG_GL1 : stm32wbxx_hal_dma.h
  • DMA_FLAG_GL2 : stm32wbxx_hal_dma.h
  • DMA_FLAG_GL3 : stm32wbxx_hal_dma.h
  • DMA_FLAG_GL4 : stm32wbxx_hal_dma.h
  • DMA_FLAG_GL5 : stm32wbxx_hal_dma.h
  • DMA_FLAG_GL6 : stm32wbxx_hal_dma.h
  • DMA_FLAG_GL7 : stm32wbxx_hal_dma.h
  • DMA_FLAG_HT1 : stm32wbxx_hal_dma.h
  • DMA_FLAG_HT2 : stm32wbxx_hal_dma.h
  • DMA_FLAG_HT3 : stm32wbxx_hal_dma.h
  • DMA_FLAG_HT4 : stm32wbxx_hal_dma.h
  • DMA_FLAG_HT5 : stm32wbxx_hal_dma.h
  • DMA_FLAG_HT6 : stm32wbxx_hal_dma.h
  • DMA_FLAG_HT7 : stm32wbxx_hal_dma.h
  • DMA_FLAG_TC1 : stm32wbxx_hal_dma.h
  • DMA_FLAG_TC2 : stm32wbxx_hal_dma.h
  • DMA_FLAG_TC3 : stm32wbxx_hal_dma.h
  • DMA_FLAG_TC4 : stm32wbxx_hal_dma.h
  • DMA_FLAG_TC5 : stm32wbxx_hal_dma.h
  • DMA_FLAG_TC6 : stm32wbxx_hal_dma.h
  • DMA_FLAG_TC7 : stm32wbxx_hal_dma.h
  • DMA_FLAG_TE1 : stm32wbxx_hal_dma.h
  • DMA_FLAG_TE2 : stm32wbxx_hal_dma.h
  • DMA_FLAG_TE3 : stm32wbxx_hal_dma.h
  • DMA_FLAG_TE4 : stm32wbxx_hal_dma.h
  • DMA_FLAG_TE5 : stm32wbxx_hal_dma.h
  • DMA_FLAG_TE6 : stm32wbxx_hal_dma.h
  • DMA_FLAG_TE7 : stm32wbxx_hal_dma.h
  • DMA_HandleTypeDef : stm32wbxx_hal_dma.h
  • DMA_IT_HT : stm32wbxx_hal_dma.h
  • DMA_IT_TC : stm32wbxx_hal_dma.h
  • DMA_IT_TE : stm32wbxx_hal_dma.h
  • DMA_MDATAALIGN_BYTE : stm32wbxx_hal_dma.h
  • DMA_MDATAALIGN_HALFWORD : stm32wbxx_hal_dma.h
  • DMA_MDATAALIGN_WORD : stm32wbxx_hal_dma.h
  • DMA_MEMORY_TO_MEMORY : stm32wbxx_hal_dma.h
  • DMA_MEMORY_TO_PERIPH : stm32wbxx_hal_dma.h
  • DMA_MINC_DISABLE : stm32wbxx_hal_dma.h
  • DMA_MINC_ENABLE : stm32wbxx_hal_dma.h
  • DMA_NORMAL : stm32wbxx_hal_dma.h
  • DMA_PDATAALIGN_BYTE : stm32wbxx_hal_dma.h
  • DMA_PDATAALIGN_HALFWORD : stm32wbxx_hal_dma.h
  • DMA_PDATAALIGN_WORD : stm32wbxx_hal_dma.h
  • DMA_PERIPH_TO_MEMORY : stm32wbxx_hal_dma.h
  • DMA_PINC_DISABLE : stm32wbxx_hal_dma.h
  • DMA_PINC_ENABLE : stm32wbxx_hal_dma.h
  • DMA_PRIORITY_HIGH : stm32wbxx_hal_dma.h
  • DMA_PRIORITY_LOW : stm32wbxx_hal_dma.h
  • DMA_PRIORITY_MEDIUM : stm32wbxx_hal_dma.h
  • DMA_PRIORITY_VERY_HIGH : stm32wbxx_hal_dma.h
  • DMA_REQUEST_ADC1 : stm32wbxx_hal_dma.h
  • DMA_REQUEST_AES1_IN : stm32wbxx_hal_dma.h
  • DMA_REQUEST_AES1_OUT : stm32wbxx_hal_dma.h
  • DMA_REQUEST_AES2_IN : stm32wbxx_hal_dma.h
  • DMA_REQUEST_AES2_OUT : stm32wbxx_hal_dma.h
  • DMA_REQUEST_GENERATOR0 : stm32wbxx_hal_dma.h
  • DMA_REQUEST_GENERATOR1 : stm32wbxx_hal_dma.h
  • DMA_REQUEST_GENERATOR2 : stm32wbxx_hal_dma.h
  • DMA_REQUEST_GENERATOR3 : stm32wbxx_hal_dma.h
  • DMA_REQUEST_I2C1_RX : stm32wbxx_hal_dma.h
  • DMA_REQUEST_I2C1_TX : stm32wbxx_hal_dma.h
  • DMA_REQUEST_I2C3_RX : stm32wbxx_hal_dma.h
  • DMA_REQUEST_I2C3_TX : stm32wbxx_hal_dma.h
  • DMA_REQUEST_LPUART1_RX : stm32wbxx_hal_dma.h
  • DMA_REQUEST_LPUART1_TX : stm32wbxx_hal_dma.h
  • DMA_REQUEST_MEM2MEM : stm32wbxx_hal_dma.h
  • DMA_REQUEST_QUADSPI : stm32wbxx_hal_dma.h
  • DMA_REQUEST_SAI1_A : stm32wbxx_hal_dma.h
  • DMA_REQUEST_SAI1_B : stm32wbxx_hal_dma.h
  • DMA_REQUEST_SPI1_RX : stm32wbxx_hal_dma.h
  • DMA_REQUEST_SPI1_TX : stm32wbxx_hal_dma.h
  • DMA_REQUEST_SPI2_RX : stm32wbxx_hal_dma.h
  • DMA_REQUEST_SPI2_TX : stm32wbxx_hal_dma.h
  • DMA_REQUEST_TIM16_CH1 : stm32wbxx_hal_dma.h
  • DMA_REQUEST_TIM16_UP : stm32wbxx_hal_dma.h
  • DMA_REQUEST_TIM17_CH1 : stm32wbxx_hal_dma.h
  • DMA_REQUEST_TIM17_UP : stm32wbxx_hal_dma.h
  • DMA_REQUEST_TIM1_CH1 : stm32wbxx_hal_dma.h
  • DMA_REQUEST_TIM1_CH2 : stm32wbxx_hal_dma.h
  • DMA_REQUEST_TIM1_CH3 : stm32wbxx_hal_dma.h
  • DMA_REQUEST_TIM1_CH4 : stm32wbxx_hal_dma.h
  • DMA_REQUEST_TIM1_COM : stm32wbxx_hal_dma.h
  • DMA_REQUEST_TIM1_TRIG : stm32wbxx_hal_dma.h
  • DMA_REQUEST_TIM1_UP : stm32wbxx_hal_dma.h
  • DMA_REQUEST_TIM2_CH1 : stm32wbxx_hal_dma.h
  • DMA_REQUEST_TIM2_CH2 : stm32wbxx_hal_dma.h
  • DMA_REQUEST_TIM2_CH3 : stm32wbxx_hal_dma.h
  • DMA_REQUEST_TIM2_CH4 : stm32wbxx_hal_dma.h
  • DMA_REQUEST_TIM2_UP : stm32wbxx_hal_dma.h
  • DMA_REQUEST_USART1_RX : stm32wbxx_hal_dma.h
  • DMA_REQUEST_USART1_TX : stm32wbxx_hal_dma.h
  • DMA_SetConfig() : stm32wbxx_hal_dma.c
  • DMAMUX_CCR_SIZE : stm32wbxx_ll_dmamux.h
  • DMAMUX_RGCR_SIZE : stm32wbxx_ll_dmamux.h
  • DT_DELAY_1 : stm32wbxx_ll_tim.h
  • DT_DELAY_2 : stm32wbxx_ll_tim.h
  • DT_DELAY_3 : stm32wbxx_ll_tim.h
  • DT_DELAY_4 : stm32wbxx_ll_tim.h
  • DT_RANGE_1 : stm32wbxx_ll_tim.h
  • DT_RANGE_2 : stm32wbxx_ll_tim.h
  • DT_RANGE_3 : stm32wbxx_ll_tim.h
  • DT_RANGE_4 : stm32wbxx_ll_tim.h
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- e -

  • EXTERNAL_SAI1_CLOCK_VALUE : stm32wbxx_hal_conf.h
  • EXTI_CallbackIDTypeDef : stm32wbxx_hal_exti.h
  • EXTI_CONFIG : stm32wbxx_hal_exti.h
  • EXTI_CONFIG_OFFSET : stm32wbxx_hal_exti.c
  • EXTI_DIRECT : stm32wbxx_hal_exti.h
  • EXTI_EVENT : stm32wbxx_hal_exti.h
  • EXTI_EVENT_PRESENCE_MASK : stm32wbxx_hal_exti.h
  • EXTI_EVENT_PRESENCE_SHIFT : stm32wbxx_hal_exti.h
  • EXTI_GPIO : stm32wbxx_hal_exti.h
  • EXTI_GPIOA : stm32wbxx_hal_exti.h
  • EXTI_GPIOB : stm32wbxx_hal_exti.h
  • EXTI_GPIOC : stm32wbxx_hal_exti.h
  • EXTI_GPIOD : stm32wbxx_hal_exti.h
  • EXTI_GPIOE : stm32wbxx_hal_exti.h
  • EXTI_GPIOH : stm32wbxx_hal_exti.h
  • EXTI_LINE_0 : stm32wbxx_hal_exti.h
  • EXTI_LINE_1 : stm32wbxx_hal_exti.h
  • EXTI_LINE_10 : stm32wbxx_hal_exti.h
  • EXTI_LINE_11 : stm32wbxx_hal_exti.h
  • EXTI_LINE_12 : stm32wbxx_hal_exti.h
  • EXTI_LINE_13 : stm32wbxx_hal_exti.h
  • EXTI_LINE_14 : stm32wbxx_hal_exti.h
  • EXTI_LINE_15 : stm32wbxx_hal_exti.h
  • EXTI_LINE_16 : stm32wbxx_hal_exti.h
  • EXTI_LINE_17 : stm32wbxx_hal_exti.h
  • EXTI_LINE_18 : stm32wbxx_hal_exti.h
  • EXTI_LINE_19 : stm32wbxx_hal_exti.h
  • EXTI_LINE_2 : stm32wbxx_hal_exti.h
  • EXTI_LINE_20 : stm32wbxx_hal_exti.h
  • EXTI_LINE_21 : stm32wbxx_hal_exti.h
  • EXTI_LINE_22 : stm32wbxx_hal_exti.h
  • EXTI_LINE_23 : stm32wbxx_hal_exti.h
  • EXTI_LINE_24 : stm32wbxx_hal_exti.h
  • EXTI_LINE_25 : stm32wbxx_hal_exti.h
  • EXTI_LINE_26 : stm32wbxx_hal_exti.h
  • EXTI_LINE_27 : stm32wbxx_hal_exti.h
  • EXTI_LINE_28 : stm32wbxx_hal_exti.h
  • EXTI_LINE_29 : stm32wbxx_hal_exti.h
  • EXTI_LINE_3 : stm32wbxx_hal_exti.h
  • EXTI_LINE_30 : stm32wbxx_hal_exti.h
  • EXTI_LINE_31 : stm32wbxx_hal_exti.h
  • EXTI_LINE_32 : stm32wbxx_hal_exti.h
  • EXTI_LINE_33 : stm32wbxx_hal_exti.h
  • EXTI_LINE_34 : stm32wbxx_hal_exti.h
  • EXTI_LINE_35 : stm32wbxx_hal_exti.h
  • EXTI_LINE_36 : stm32wbxx_hal_exti.h
  • EXTI_LINE_37 : stm32wbxx_hal_exti.h
  • EXTI_LINE_38 : stm32wbxx_hal_exti.h
  • EXTI_LINE_39 : stm32wbxx_hal_exti.h
  • EXTI_LINE_4 : stm32wbxx_hal_exti.h
  • EXTI_LINE_40 : stm32wbxx_hal_exti.h
  • EXTI_LINE_41 : stm32wbxx_hal_exti.h
  • EXTI_LINE_42 : stm32wbxx_hal_exti.h
  • EXTI_LINE_43 : stm32wbxx_hal_exti.h
  • EXTI_LINE_44 : stm32wbxx_hal_exti.h
  • EXTI_LINE_45 : stm32wbxx_hal_exti.h
  • EXTI_LINE_46 : stm32wbxx_hal_exti.h
  • EXTI_LINE_47 : stm32wbxx_hal_exti.h
  • EXTI_LINE_48 : stm32wbxx_hal_exti.h
  • EXTI_LINE_5 : stm32wbxx_hal_exti.h
  • EXTI_LINE_6 : stm32wbxx_hal_exti.h
  • EXTI_LINE_7 : stm32wbxx_hal_exti.h
  • EXTI_LINE_8 : stm32wbxx_hal_exti.h
  • EXTI_LINE_9 : stm32wbxx_hal_exti.h
  • EXTI_LINE_NB : stm32wbxx_hal_exti.h
  • EXTI_MODE : stm32wbxx_hal_gpio.c
  • EXTI_MODE_EVENT : stm32wbxx_hal_exti.h
  • EXTI_MODE_INTERRUPT : stm32wbxx_hal_exti.h
  • EXTI_MODE_MASK : stm32wbxx_hal_exti.h
  • EXTI_MODE_NONE : stm32wbxx_hal_exti.h
  • EXTI_MODE_OFFSET : stm32wbxx_hal_exti.c
  • EXTI_PIN_MASK : stm32wbxx_hal_exti.h
  • EXTI_PROPERTY_MASK : stm32wbxx_hal_exti.h
  • EXTI_PROPERTY_SHIFT : stm32wbxx_hal_exti.h
  • EXTI_REG1 : stm32wbxx_hal_exti.h
  • EXTI_REG2 : stm32wbxx_hal_exti.h
  • EXTI_REG_MASK : stm32wbxx_hal_exti.h
  • EXTI_REG_SHIFT : stm32wbxx_hal_exti.h
  • EXTI_RESERVED : stm32wbxx_hal_exti.h
  • EXTI_TRIGGER_FALLING : stm32wbxx_hal_exti.h
  • EXTI_TRIGGER_MASK : stm32wbxx_hal_exti.h
  • EXTI_TRIGGER_NONE : stm32wbxx_hal_exti.h
  • EXTI_TRIGGER_RISING : stm32wbxx_hal_exti.h
  • EXTI_TRIGGER_RISING_FALLING : stm32wbxx_hal_exti.h
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
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  • q
  • r
  • s
  • t
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  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- f -

  • FALLING_EDGE : stm32wbxx_hal_gpio.c
  • FLASH_AcknowledgePageErase() : stm32wbxx_hal_flash_ex.c
  • FLASH_BANK_SIZE : stm32wbxx_hal_flash.h
  • FLASH_END_ADDR : stm32wbxx_hal_flash.h
  • FLASH_FLAG_ALL_ERRORS : stm32wbxx_hal_flash.h
  • FLASH_FLAG_BSY : stm32wbxx_hal_flash.h
  • FLASH_FLAG_CFGBSY : stm32wbxx_hal_flash.h
  • FLASH_FLAG_ECCC : stm32wbxx_hal_flash.h
  • FLASH_FLAG_ECCD : stm32wbxx_hal_flash.h
  • FLASH_FLAG_ECCR_ERRORS : stm32wbxx_hal_flash.h
  • FLASH_FLAG_EOP : stm32wbxx_hal_flash.h
  • FLASH_FLAG_FASTERR : stm32wbxx_hal_flash.h
  • FLASH_FLAG_MISERR : stm32wbxx_hal_flash.h
  • FLASH_FLAG_OPERR : stm32wbxx_hal_flash.h
  • FLASH_FLAG_OPTNV : stm32wbxx_hal_flash.h
  • FLASH_FLAG_OPTVERR : stm32wbxx_hal_flash.h
  • FLASH_FLAG_PESD : stm32wbxx_hal_flash.h
  • FLASH_FLAG_PGAERR : stm32wbxx_hal_flash.h
  • FLASH_FLAG_PGSERR : stm32wbxx_hal_flash.h
  • FLASH_FLAG_PROGERR : stm32wbxx_hal_flash.h
  • FLASH_FLAG_RDERR : stm32wbxx_hal_flash.h
  • FLASH_FLAG_SIZERR : stm32wbxx_hal_flash.h
  • FLASH_FLAG_SR_ERRORS : stm32wbxx_hal_flash.h
  • FLASH_FLAG_WRPERR : stm32wbxx_hal_flash.h
  • FLASH_FlushCaches() : stm32wbxx_hal_flash_ex.c
  • FLASH_IT_ECCC : stm32wbxx_hal_flash.h
  • FLASH_IT_EOP : stm32wbxx_hal_flash.h
  • FLASH_IT_OPERR : stm32wbxx_hal_flash.h
  • FLASH_IT_RDERR : stm32wbxx_hal_flash.h
  • FLASH_KEY1 : stm32wbxx_hal_flash.h
  • FLASH_KEY2 : stm32wbxx_hal_flash.h
  • FLASH_LATENCY_0 : stm32wbxx_hal_flash.h
  • FLASH_LATENCY_1 : stm32wbxx_hal_flash.h
  • FLASH_LATENCY_2 : stm32wbxx_hal_flash.h
  • FLASH_LATENCY_3 : stm32wbxx_hal_flash.h
  • FLASH_MassErase() : stm32wbxx_hal_flash_ex.c
  • FLASH_NB_DOUBLE_WORDS_IN_ROW : stm32wbxx_hal_flash.c
  • FLASH_OB_GetC2BootResetConfig() : stm32wbxx_hal_flash_ex.c
  • FLASH_OB_GetIPCCBufferAddr() : stm32wbxx_hal_flash_ex.c
  • FLASH_OB_GetPCROP() : stm32wbxx_hal_flash_ex.c
  • FLASH_OB_GetRDP() : stm32wbxx_hal_flash_ex.c
  • FLASH_OB_GetSecureMemoryConfig() : stm32wbxx_hal_flash_ex.c
  • FLASH_OB_GetUser() : stm32wbxx_hal_flash_ex.c
  • FLASH_OB_GetWRP() : stm32wbxx_hal_flash_ex.c
  • FLASH_OB_IPCCBufferAddrConfig() : stm32wbxx_hal_flash_ex.c
  • FLASH_OB_OptrConfig() : stm32wbxx_hal_flash_ex.c
  • FLASH_OB_PCROP1AConfig() : stm32wbxx_hal_flash_ex.c
  • FLASH_OB_PCROP1BConfig() : stm32wbxx_hal_flash_ex.c
  • FLASH_OB_ProceedWriteOperation() : stm32wbxx_hal_flash_ex.c
  • FLASH_OB_SecureConfig() : stm32wbxx_hal_flash_ex.c
  • FLASH_OB_WRPConfig() : stm32wbxx_hal_flash_ex.c
  • FLASH_OPTKEY1 : stm32wbxx_hal_flash.h
  • FLASH_OPTKEY2 : stm32wbxx_hal_flash.h
  • FLASH_PAGE_NB : stm32wbxx_hal_flash.h
  • FLASH_PAGE_SIZE : stm32wbxx_hal_flash.h
  • FLASH_PageErase() : stm32wbxx_hal_flash_ex.c
  • FLASH_PCROP_GRANULARITY : stm32wbxx_hal_flash.h
  • FLASH_PCROP_GRANULARITY_OFFSET : stm32wbxx_hal_flash.h
  • FLASH_PROG_EMPTY : stm32wbxx_hal_flash_ex.h
  • FLASH_PROG_NOT_EMPTY : stm32wbxx_hal_flash_ex.h
  • FLASH_Program_DoubleWord() : stm32wbxx_hal_flash.c
  • FLASH_Program_Fast() : stm32wbxx_hal_flash.c
  • FLASH_TIMEOUT_VALUE : stm32wbxx_hal_flash.h
  • FLASH_TYPEERASE_MASSERASE : stm32wbxx_hal_flash.h
  • FLASH_TYPEERASE_PAGES : stm32wbxx_hal_flash.h
  • FLASH_TYPENONE : stm32wbxx_hal_flash.h
  • FLASH_TYPEPROGRAM_DOUBLEWORD : stm32wbxx_hal_flash.h
  • FLASH_TYPEPROGRAM_FAST : stm32wbxx_hal_flash.h
  • FLASH_WaitForLastOperation() : stm32wbxx_hal_flash.h , stm32wbxx_hal_flash.c
  • FLASHSIZE_BASE_ADDRESS : stm32wbxx_ll_utils.h
  • FTLSI2TRIM : stm32wbxx_hal_rcc_ex.c
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- g -

  • GPIO_AF0_JTCK_SWCLK : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF0_JTD_TRACE : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF0_JTDI : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF0_JTMS_SWDIO : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF0_LSCO : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF0_MCO : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF0_NJTRST : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF0_RTC_OUT : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF0_RTC_REFIN : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF0_SYS : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF0_TRACECK : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF0_TRACED0 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF0_TRACED1 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF0_TRACED2 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF0_TRACED3 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF0_TRIG_INOUT : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF10_QUADSPI : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF10_USB : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF11_LCD : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF12_COMP1 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF12_COMP2 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF12_TIM1 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF13_SAI1 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF14_LPTIM2 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF14_TIM16 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF14_TIM17 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF14_TIM2 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF15_EVENTOUT : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF1_LPTIM1 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF1_TIM1 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF1_TIM2 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF2_TIM1 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF2_TIM2 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF3_SAI1 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF3_SPI2 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF3_TIM1 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF4_I2C1 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF4_I2C3 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF5_SPI1 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF5_SPI2 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_LSCO : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_MCO : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_DTB0 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_DTB1 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_DTB10 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_DTB11 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_DTB12 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_DTB13 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_DTB14 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_DTB15 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_DTB16 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_DTB17 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_DTB18 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_DTB2 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_DTB3 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_DTB4 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_DTB5 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_DTB6 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_DTB7 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_DTB8 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_DTB9 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_MISO : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_MOSI : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_NSS : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_SCK : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF7_USART1 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF8_IR : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF8_LPUART1 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF9_TSC : stm32wbxx_hal_gpio_ex.h
  • GPIO_GET_INDEX : stm32wbxx_hal_gpio_ex.h
  • GPIO_MODE : stm32wbxx_hal_gpio.c
  • GPIO_MODE_AF_OD : stm32wbxx_hal_gpio.h
  • GPIO_MODE_AF_PP : stm32wbxx_hal_gpio.h
  • GPIO_MODE_ANALOG : stm32wbxx_hal_gpio.h
  • GPIO_MODE_EVT : stm32wbxx_hal_gpio.c
  • GPIO_MODE_EVT_FALLING : stm32wbxx_hal_gpio.h
  • GPIO_MODE_EVT_RISING : stm32wbxx_hal_gpio.h
  • GPIO_MODE_EVT_RISING_FALLING : stm32wbxx_hal_gpio.h
  • GPIO_MODE_INPUT : stm32wbxx_hal_gpio.h
  • GPIO_MODE_IT : stm32wbxx_hal_gpio.c
  • GPIO_MODE_IT_FALLING : stm32wbxx_hal_gpio.h
  • GPIO_MODE_IT_RISING : stm32wbxx_hal_gpio.h
  • GPIO_MODE_IT_RISING_FALLING : stm32wbxx_hal_gpio.h
  • GPIO_MODE_OUTPUT_OD : stm32wbxx_hal_gpio.h
  • GPIO_MODE_OUTPUT_PP : stm32wbxx_hal_gpio.h
  • GPIO_NOPULL : stm32wbxx_hal_gpio.h
  • GPIO_NUMBER : stm32wbxx_hal_gpio.c
  • GPIO_OUTPUT_TYPE : stm32wbxx_hal_gpio.c
  • GPIO_PIN_0 : stm32wbxx_hal_gpio.h
  • GPIO_PIN_1 : stm32wbxx_hal_gpio.h
  • GPIO_PIN_10 : stm32wbxx_hal_gpio.h
  • GPIO_PIN_11 : stm32wbxx_hal_gpio.h
  • GPIO_PIN_12 : stm32wbxx_hal_gpio.h
  • GPIO_PIN_13 : stm32wbxx_hal_gpio.h
  • GPIO_PIN_14 : stm32wbxx_hal_gpio.h
  • GPIO_PIN_15 : stm32wbxx_hal_gpio.h
  • GPIO_PIN_2 : stm32wbxx_hal_gpio.h
  • GPIO_PIN_3 : stm32wbxx_hal_gpio.h
  • GPIO_PIN_4 : stm32wbxx_hal_gpio.h
  • GPIO_PIN_5 : stm32wbxx_hal_gpio.h
  • GPIO_PIN_6 : stm32wbxx_hal_gpio.h
  • GPIO_PIN_7 : stm32wbxx_hal_gpio.h
  • GPIO_PIN_8 : stm32wbxx_hal_gpio.h
  • GPIO_PIN_9 : stm32wbxx_hal_gpio.h
  • GPIO_PIN_All : stm32wbxx_hal_gpio.h
  • GPIO_PIN_MASK : stm32wbxx_hal_gpio.h
  • GPIO_PIN_RESET : stm32wbxx_hal_gpio.h
  • GPIO_PIN_SET : stm32wbxx_hal_gpio.h
  • GPIO_PinState : stm32wbxx_hal_gpio.h
  • GPIO_PULLDOWN : stm32wbxx_hal_gpio.h
  • GPIO_PULLUP : stm32wbxx_hal_gpio.h
  • GPIO_SPEED_FREQ_HIGH : stm32wbxx_hal_gpio.h
  • GPIO_SPEED_FREQ_LOW : stm32wbxx_hal_gpio.h
  • GPIO_SPEED_FREQ_MEDIUM : stm32wbxx_hal_gpio.h
  • GPIO_SPEED_FREQ_VERY_HIGH : stm32wbxx_hal_gpio.h
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

  • File List
  • Globals
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  • Variables
  • Typedefs
  • Enumerations
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  • _
  • a
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  • c
  • d
  • e
  • f
  • g
  • h
  • i
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  • m
  • n
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  • r
  • s
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  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- h -

  • HAL_ADC_AnalogWDGConfig() : stm32wbxx_hal_adc.c
  • HAL_ADC_CallbackIDTypeDef : stm32wbxx_hal_adc.h
  • HAL_ADC_ConfigChannel() : stm32wbxx_hal_adc.c
  • HAL_ADC_ConvCpltCallback() : stm32wbxx_hal_adc.c
  • HAL_ADC_CONVERSION_COMPLETE_CB_ID : stm32wbxx_hal_adc.h
  • HAL_ADC_CONVERSION_HALF_CB_ID : stm32wbxx_hal_adc.h
  • HAL_ADC_ConvHalfCpltCallback() : stm32wbxx_hal_adc.c
  • HAL_ADC_DeInit() : stm32wbxx_hal_adc.c
  • HAL_ADC_END_OF_SAMPLING_CB_ID : stm32wbxx_hal_adc.h
  • HAL_ADC_ERROR_CB_ID : stm32wbxx_hal_adc.h
  • HAL_ADC_ERROR_DMA : stm32wbxx_hal_adc.h
  • HAL_ADC_ERROR_INTERNAL : stm32wbxx_hal_adc.h
  • HAL_ADC_ERROR_INVALID_CALLBACK : stm32wbxx_hal_adc.h
  • HAL_ADC_ERROR_JQOVF : stm32wbxx_hal_adc.h
  • HAL_ADC_ERROR_NONE : stm32wbxx_hal_adc.h
  • HAL_ADC_ERROR_OVR : stm32wbxx_hal_adc.h
  • HAL_ADC_ErrorCallback() : stm32wbxx_hal_adc.c
  • HAL_ADC_GetError() : stm32wbxx_hal_adc.c
  • HAL_ADC_GetState() : stm32wbxx_hal_adc.c
  • HAL_ADC_GetValue() : stm32wbxx_hal_adc.c
  • HAL_ADC_Init() : stm32wbxx_hal_adc.c
  • HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : stm32wbxx_hal_adc.h
  • HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID : stm32wbxx_hal_adc.h
  • HAL_ADC_IRQHandler() : stm32wbxx_hal_adc.c
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : stm32wbxx_hal_adc.h
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID : stm32wbxx_hal_adc.h
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID : stm32wbxx_hal_adc.h
  • HAL_ADC_LevelOutOfWindowCallback() : stm32wbxx_hal_adc.c
  • HAL_ADC_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_ADC_MspDeInit() : stm32wbxx_hal_adc.c
  • HAL_ADC_MSPDEINIT_CB_ID : stm32wbxx_hal_adc.h
  • HAL_ADC_MspInit() : stm32wbxx_hal_adc.c
  • HAL_ADC_MSPINIT_CB_ID : stm32wbxx_hal_adc.h
  • HAL_ADC_PollForConversion() : stm32wbxx_hal_adc.c
  • HAL_ADC_PollForEvent() : stm32wbxx_hal_adc.c
  • HAL_ADC_RegisterCallback() : stm32wbxx_hal_adc.c
  • HAL_ADC_Start() : stm32wbxx_hal_adc.c
  • HAL_ADC_Start_DMA() : stm32wbxx_hal_adc.c
  • HAL_ADC_Start_IT() : stm32wbxx_hal_adc.c
  • HAL_ADC_STATE_AWD1 : stm32wbxx_hal_adc.h
  • HAL_ADC_STATE_AWD2 : stm32wbxx_hal_adc.h
  • HAL_ADC_STATE_AWD3 : stm32wbxx_hal_adc.h
  • HAL_ADC_STATE_BUSY_INTERNAL : stm32wbxx_hal_adc.h
  • HAL_ADC_STATE_ERROR_CONFIG : stm32wbxx_hal_adc.h
  • HAL_ADC_STATE_ERROR_DMA : stm32wbxx_hal_adc.h
  • HAL_ADC_STATE_ERROR_INTERNAL : stm32wbxx_hal_adc.h
  • HAL_ADC_STATE_INJ_BUSY : stm32wbxx_hal_adc.h
  • HAL_ADC_STATE_INJ_EOC : stm32wbxx_hal_adc.h
  • HAL_ADC_STATE_INJ_JQOVF : stm32wbxx_hal_adc.h
  • HAL_ADC_STATE_MULTIMODE_SLAVE : stm32wbxx_hal_adc.h
  • HAL_ADC_STATE_READY : stm32wbxx_hal_adc.h
  • HAL_ADC_STATE_REG_BUSY : stm32wbxx_hal_adc.h
  • HAL_ADC_STATE_REG_EOC : stm32wbxx_hal_adc.h
  • HAL_ADC_STATE_REG_EOSMP : stm32wbxx_hal_adc.h
  • HAL_ADC_STATE_REG_OVR : stm32wbxx_hal_adc.h
  • HAL_ADC_STATE_RESET : stm32wbxx_hal_adc.h
  • HAL_ADC_STATE_TIMEOUT : stm32wbxx_hal_adc.h
  • HAL_ADC_Stop() : stm32wbxx_hal_adc.c
  • HAL_ADC_Stop_DMA() : stm32wbxx_hal_adc.c
  • HAL_ADC_Stop_IT() : stm32wbxx_hal_adc.c
  • HAL_ADC_UnRegisterCallback() : stm32wbxx_hal_adc.c
  • HAL_ADCEx_Calibration_GetValue() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_Calibration_SetValue() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_Calibration_Start() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_DisableInjectedQueue() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_DisableVoltageRegulator() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_EnableInjectedQueue() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_EndOfSamplingCallback() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_EnterADCDeepPowerDownMode() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_InjectedConfigChannel() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_InjectedConvCpltCallback() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_InjectedGetValue() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_InjectedPollForConversion() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_InjectedQueueOverflowCallback() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStart() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStart_IT() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStop() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStop_IT() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_LevelOutOfWindow2Callback() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_LevelOutOfWindow3Callback() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_RegularStop() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_RegularStop_DMA() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_RegularStop_IT() : stm32wbxx_hal_adc_ex.c
  • HAL_COMP_CallbackIDTypeDef : stm32wbxx_hal_comp.h
  • HAL_COMP_DeInit() : stm32wbxx_hal_comp.c
  • HAL_COMP_ERROR_INVALID_CALLBACK : stm32wbxx_hal_comp.h
  • HAL_COMP_ERROR_NONE : stm32wbxx_hal_comp.h
  • HAL_COMP_GetError() : stm32wbxx_hal_comp.c
  • HAL_COMP_GetOutputLevel() : stm32wbxx_hal_comp.c
  • HAL_COMP_GetState() : stm32wbxx_hal_comp.c
  • HAL_COMP_Init() : stm32wbxx_hal_comp.c
  • HAL_COMP_IRQHandler() : stm32wbxx_hal_comp.c
  • HAL_COMP_Lock() : stm32wbxx_hal_comp.c
  • HAL_COMP_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_COMP_MspDeInit() : stm32wbxx_hal_comp.c
  • HAL_COMP_MSPDEINIT_CB_ID : stm32wbxx_hal_comp.h
  • HAL_COMP_MspInit() : stm32wbxx_hal_comp.c
  • HAL_COMP_MSPINIT_CB_ID : stm32wbxx_hal_comp.h
  • HAL_COMP_RegisterCallback() : stm32wbxx_hal_comp.c
  • HAL_COMP_Start() : stm32wbxx_hal_comp.c
  • HAL_COMP_STATE_BUSY : stm32wbxx_hal_comp.h
  • HAL_COMP_STATE_BUSY_LOCKED : stm32wbxx_hal_comp.h
  • HAL_COMP_STATE_READY : stm32wbxx_hal_comp.h
  • HAL_COMP_STATE_READY_LOCKED : stm32wbxx_hal_comp.h
  • HAL_COMP_STATE_RESET : stm32wbxx_hal_comp.h
  • HAL_COMP_STATE_RESET_LOCKED : stm32wbxx_hal_comp.h
  • HAL_COMP_StateTypeDef : stm32wbxx_hal_comp.h
  • HAL_COMP_Stop() : stm32wbxx_hal_comp.c
  • HAL_COMP_TRIGGER_CB_ID : stm32wbxx_hal_comp.h
  • HAL_COMP_TriggerCallback() : stm32wbxx_hal_comp.c
  • HAL_COMP_UnRegisterCallback() : stm32wbxx_hal_comp.c
  • HAL_CORTEX_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_CRC_Accumulate() : stm32wbxx_hal_crc.c
  • HAL_CRC_Calculate() : stm32wbxx_hal_crc.c
  • HAL_CRC_DeInit() : stm32wbxx_hal_crc.c
  • HAL_CRC_GetState() : stm32wbxx_hal_crc.c
  • HAL_CRC_Init() : stm32wbxx_hal_crc.c
  • HAL_CRC_Input_Data_Reverse : stm32wbxx_hal_crc.h
  • HAL_CRC_LENGTH_16B : stm32wbxx_hal_crc.h
  • HAL_CRC_LENGTH_32B : stm32wbxx_hal_crc.h
  • HAL_CRC_LENGTH_7B : stm32wbxx_hal_crc.h
  • HAL_CRC_LENGTH_8B : stm32wbxx_hal_crc.h
  • HAL_CRC_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_CRC_MspDeInit() : stm32wbxx_hal_crc.c
  • HAL_CRC_MspInit() : stm32wbxx_hal_crc.c
  • HAL_CRC_Output_Data_Reverse : stm32wbxx_hal_crc.h
  • HAL_CRC_STATE_BUSY : stm32wbxx_hal_crc.h
  • HAL_CRC_STATE_ERROR : stm32wbxx_hal_crc.h
  • HAL_CRC_STATE_READY : stm32wbxx_hal_crc.h
  • HAL_CRC_STATE_RESET : stm32wbxx_hal_crc.h
  • HAL_CRC_STATE_TIMEOUT : stm32wbxx_hal_crc.h
  • HAL_CRC_StateTypeDef : stm32wbxx_hal_crc.h
  • HAL_CRCEx_Input_Data_Reverse() : stm32wbxx_hal_crc_ex.c
  • HAL_CRCEx_Output_Data_Reverse() : stm32wbxx_hal_crc_ex.c
  • HAL_CRCEx_Polynomial_Set() : stm32wbxx_hal_crc_ex.c
  • HAL_CRYP_CallbackIDTypeDef : stm32wbxx_hal_cryp.h
  • HAL_CRYP_Decrypt() : stm32wbxx_hal_cryp.c
  • HAL_CRYP_Decrypt_DMA() : stm32wbxx_hal_cryp.c
  • HAL_CRYP_Decrypt_IT() : stm32wbxx_hal_cryp.c
  • HAL_CRYP_DeInit() : stm32wbxx_hal_cryp.c
  • HAL_CRYP_Encrypt() : stm32wbxx_hal_cryp.c
  • HAL_CRYP_Encrypt_DMA() : stm32wbxx_hal_cryp.c
  • HAL_CRYP_Encrypt_IT() : stm32wbxx_hal_cryp.c
  • HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE : stm32wbxx_hal_cryp.h
  • HAL_CRYP_ERROR_BUSY : stm32wbxx_hal_cryp.h
  • HAL_CRYP_ERROR_CB_ID : stm32wbxx_hal_cryp.h
  • HAL_CRYP_ERROR_DMA : stm32wbxx_hal_cryp.h
  • HAL_CRYP_ERROR_INVALID_CALLBACK : stm32wbxx_hal_cryp.h
  • HAL_CRYP_ERROR_NONE : stm32wbxx_hal_cryp.h
  • HAL_CRYP_ERROR_NOT_SUPPORTED : stm32wbxx_hal_cryp.h
  • HAL_CRYP_ERROR_READ : stm32wbxx_hal_cryp.h
  • HAL_CRYP_ERROR_TIMEOUT : stm32wbxx_hal_cryp.h
  • HAL_CRYP_ERROR_WRITE : stm32wbxx_hal_cryp.h
  • HAL_CRYP_ErrorCallback() : stm32wbxx_hal_cryp.c
  • HAL_CRYP_GetConfig() : stm32wbxx_hal_cryp.c
  • HAL_CRYP_GetError() : stm32wbxx_hal_cryp.c
  • HAL_CRYP_GetState() : stm32wbxx_hal_cryp.c
  • HAL_CRYP_InCpltCallback() : stm32wbxx_hal_cryp.c
  • HAL_CRYP_Init() : stm32wbxx_hal_cryp.c
  • HAL_CRYP_INPUT_COMPLETE_CB_ID : stm32wbxx_hal_cryp.h
  • HAL_CRYP_IRQHandler() : stm32wbxx_hal_cryp.c
  • HAL_CRYP_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_CRYP_MspDeInit() : stm32wbxx_hal_cryp.c
  • HAL_CRYP_MSPDEINIT_CB_ID : stm32wbxx_hal_cryp.h
  • HAL_CRYP_MspInit() : stm32wbxx_hal_cryp.c
  • HAL_CRYP_MSPINIT_CB_ID : stm32wbxx_hal_cryp.h
  • HAL_CRYP_OutCpltCallback() : stm32wbxx_hal_cryp.c
  • HAL_CRYP_OUTPUT_COMPLETE_CB_ID : stm32wbxx_hal_cryp.h
  • HAL_CRYP_RegisterCallback() : stm32wbxx_hal_cryp.c
  • HAL_CRYP_SetConfig() : stm32wbxx_hal_cryp.c
  • HAL_CRYP_STATE_BUSY : stm32wbxx_hal_cryp.h
  • HAL_CRYP_STATE_READY : stm32wbxx_hal_cryp.h
  • HAL_CRYP_STATE_RESET : stm32wbxx_hal_cryp.h
  • HAL_CRYP_STATETypeDef : stm32wbxx_hal_cryp.h
  • HAL_CRYP_UnRegisterCallback() : stm32wbxx_hal_cryp.c
  • HAL_CRYPEx_AESCCM_GenerateAuthTAG() : stm32wbxx_hal_cryp_ex.c
  • HAL_CRYPEx_AESGCM_GenerateAuthTAG() : stm32wbxx_hal_cryp_ex.c
  • HAL_CRYPEx_DisableAutoKeyDerivation() : stm32wbxx_hal_cryp_ex.c
  • HAL_CRYPEx_EnableAutoKeyDerivation() : stm32wbxx_hal_cryp_ex.c
  • HAL_DBGMCU_DisableDBGSleepMode() : stm32wbxx_hal.c
  • HAL_DBGMCU_DisableDBGStandbyMode() : stm32wbxx_hal.c
  • HAL_DBGMCU_DisableDBGStopMode() : stm32wbxx_hal.c
  • HAL_DBGMCU_EnableDBGSleepMode() : stm32wbxx_hal.c
  • HAL_DBGMCU_EnableDBGStandbyMode() : stm32wbxx_hal.c
  • HAL_DBGMCU_EnableDBGStopMode() : stm32wbxx_hal.c
  • HAL_DeInit() : stm32wbxx_hal.c
  • HAL_Delay() : stm32wbxx_hal.c
  • HAL_DMA_Abort() : stm32wbxx_hal_dma.c
  • HAL_DMA_Abort_IT() : stm32wbxx_hal_dma.c
  • HAL_DMA_CallbackIDTypeDef : stm32wbxx_hal_dma.h
  • HAL_DMA_DeInit() : stm32wbxx_hal_dma.c
  • HAL_DMA_ERROR_NO_XFER : stm32wbxx_hal_dma.h
  • HAL_DMA_ERROR_NONE : stm32wbxx_hal_dma.h
  • HAL_DMA_ERROR_NOT_SUPPORTED : stm32wbxx_hal_dma.h
  • HAL_DMA_ERROR_REQGEN : stm32wbxx_hal_dma.h
  • HAL_DMA_ERROR_SYNC : stm32wbxx_hal_dma.h
  • HAL_DMA_ERROR_TE : stm32wbxx_hal_dma.h
  • HAL_DMA_ERROR_TIMEOUT : stm32wbxx_hal_dma.h
  • HAL_DMA_FULL_TRANSFER : stm32wbxx_hal_dma.h
  • HAL_DMA_GetError() : stm32wbxx_hal_dma.c
  • HAL_DMA_GetState() : stm32wbxx_hal_dma.c
  • HAL_DMA_HALF_TRANSFER : stm32wbxx_hal_dma.h
  • HAL_DMA_Init() : stm32wbxx_hal_dma.c
  • HAL_DMA_IRQHandler() : stm32wbxx_hal_dma.c
  • HAL_DMA_LevelCompleteTypeDef : stm32wbxx_hal_dma.h
  • HAL_DMA_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_DMA_PollForTransfer() : stm32wbxx_hal_dma.c
  • HAL_DMA_RegisterCallback() : stm32wbxx_hal_dma.c
  • HAL_DMA_Start() : stm32wbxx_hal_dma.c
  • HAL_DMA_Start_IT() : stm32wbxx_hal_dma.c
  • HAL_DMA_STATE_BUSY : stm32wbxx_hal_dma.h
  • HAL_DMA_STATE_READY : stm32wbxx_hal_dma.h
  • HAL_DMA_STATE_RESET : stm32wbxx_hal_dma.h
  • HAL_DMA_STATE_TIMEOUT : stm32wbxx_hal_dma.h
  • HAL_DMA_StateTypeDef : stm32wbxx_hal_dma.h
  • HAL_DMA_UnRegisterCallback() : stm32wbxx_hal_dma.c
  • HAL_DMA_XFER_ABORT_CB_ID : stm32wbxx_hal_dma.h
  • HAL_DMA_XFER_ALL_CB_ID : stm32wbxx_hal_dma.h
  • HAL_DMA_XFER_CPLT_CB_ID : stm32wbxx_hal_dma.h
  • HAL_DMA_XFER_ERROR_CB_ID : stm32wbxx_hal_dma.h
  • HAL_DMA_XFER_HALFCPLT_CB_ID : stm32wbxx_hal_dma.h
  • HAL_DMAEx_ConfigMuxRequestGenerator() : stm32wbxx_hal_dma_ex.c
  • HAL_DMAEx_ConfigMuxSync() : stm32wbxx_hal_dma_ex.c
  • HAL_DMAEx_DisableMuxRequestGenerator() : stm32wbxx_hal_dma_ex.c
  • HAL_DMAEx_EnableMuxRequestGenerator() : stm32wbxx_hal_dma_ex.c
  • HAL_DMAEx_MUX_IRQHandler() : stm32wbxx_hal_dma_ex.c
  • HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI0 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI1 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI10 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI11 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI12 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI13 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI14 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI15 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI2 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI3 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI4 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI5 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI6 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI7 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI8 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI9 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI0 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI1 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI10 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI11 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI12 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI13 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI14 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI15 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI2 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI3 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI4 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI5 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI6 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI7 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI8 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI9 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_LPTIM1_OUT : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_LPTIM2_OUT : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX_REQ_GEN_FALLING : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX_REQ_GEN_NO_EVENT : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX_REQ_GEN_RISING : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX_REQ_GEN_RISING_FALLING : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_FALLING : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_NO_EVENT : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_RISING : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_RISING_FALLING : stm32wbxx_hal_dma_ex.h
  • HAL_EXTI_ClearConfigLine() : stm32wbxx_hal_exti.c
  • HAL_EXTI_ClearPending() : stm32wbxx_hal_exti.c
  • HAL_EXTI_COMMON_CB_ID : stm32wbxx_hal_exti.h
  • HAL_EXTI_GenerateSWI() : stm32wbxx_hal_exti.c
  • HAL_EXTI_GetConfigLine() : stm32wbxx_hal_exti.c
  • HAL_EXTI_GetHandle() : stm32wbxx_hal_exti.c
  • HAL_EXTI_GetPending() : stm32wbxx_hal_exti.c
  • HAL_EXTI_IRQHandler() : stm32wbxx_hal_exti.c
  • HAL_EXTI_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_EXTI_RegisterCallback() : stm32wbxx_hal_exti.c
  • HAL_EXTI_SetConfigLine() : stm32wbxx_hal_exti.c
  • HAL_FLASH_EndOfOperationCallback() : stm32wbxx_hal_flash.c
  • HAL_FLASH_ERROR_FAST : stm32wbxx_hal_flash.h
  • HAL_FLASH_ERROR_MIS : stm32wbxx_hal_flash.h
  • HAL_FLASH_ERROR_NONE : stm32wbxx_hal_flash.h
  • HAL_FLASH_ERROR_OP : stm32wbxx_hal_flash.h
  • HAL_FLASH_ERROR_OPTV : stm32wbxx_hal_flash.h
  • HAL_FLASH_ERROR_PGA : stm32wbxx_hal_flash.h
  • HAL_FLASH_ERROR_PGS : stm32wbxx_hal_flash.h
  • HAL_FLASH_ERROR_PROG : stm32wbxx_hal_flash.h
  • HAL_FLASH_ERROR_RD : stm32wbxx_hal_flash.h
  • HAL_FLASH_ERROR_SIZ : stm32wbxx_hal_flash.h
  • HAL_FLASH_ERROR_WRP : stm32wbxx_hal_flash.h
  • HAL_FLASH_GetError() : stm32wbxx_hal_flash.c
  • HAL_FLASH_IRQHandler() : stm32wbxx_hal_flash.c
  • HAL_FLASH_Lock() : stm32wbxx_hal_flash.c
  • HAL_FLASH_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_FLASH_OB_Launch() : stm32wbxx_hal_flash.c
  • HAL_FLASH_OB_Lock() : stm32wbxx_hal_flash.c
  • HAL_FLASH_OB_Unlock() : stm32wbxx_hal_flash.c
  • HAL_FLASH_OperationErrorCallback() : stm32wbxx_hal_flash.c
  • HAL_FLASH_Program() : stm32wbxx_hal_flash.c
  • HAL_FLASH_Program_IT() : stm32wbxx_hal_flash.c
  • HAL_FLASH_Unlock() : stm32wbxx_hal_flash.c
  • HAL_FLASHEx_AllowOperation() : stm32wbxx_hal_flash_ex.c
  • HAL_FLASHEx_Erase() : stm32wbxx_hal_flash_ex.c
  • HAL_FLASHEx_Erase_IT() : stm32wbxx_hal_flash_ex.c
  • HAL_FLASHEx_FlashEmptyCheck() : stm32wbxx_hal_flash_ex.c
  • HAL_FLASHEx_ForceFlashEmpty() : stm32wbxx_hal_flash_ex.c
  • HAL_FLASHEx_IsOperationSuspended() : stm32wbxx_hal_flash_ex.c
  • HAL_FLASHEx_OBGetConfig() : stm32wbxx_hal_flash_ex.c
  • HAL_FLASHEx_OBProgram() : stm32wbxx_hal_flash_ex.c
  • HAL_FLASHEx_SuspendOperation() : stm32wbxx_hal_flash_ex.c
  • HAL_GetDEVID() : stm32wbxx_hal.c
  • HAL_GetHalVersion() : stm32wbxx_hal.c
  • HAL_GetREVID() : stm32wbxx_hal.c
  • HAL_GetTick() : stm32wbxx_hal.c
  • HAL_GetTickFreq() : stm32wbxx_hal.c
  • HAL_GetTickPrio() : stm32wbxx_hal.c
  • HAL_GetUIDw0() : stm32wbxx_hal.c
  • HAL_GetUIDw1() : stm32wbxx_hal.c
  • HAL_GetUIDw2() : stm32wbxx_hal.c
  • HAL_GPIO_DeInit() : stm32wbxx_hal_gpio.c
  • HAL_GPIO_EXTI_Callback() : stm32wbxx_hal_gpio.c
  • HAL_GPIO_EXTI_IRQHandler() : stm32wbxx_hal_gpio.c
  • HAL_GPIO_Init() : stm32wbxx_hal_gpio.c
  • HAL_GPIO_LockPin() : stm32wbxx_hal_gpio.c
  • HAL_GPIO_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_GPIO_ReadPin() : stm32wbxx_hal_gpio.c
  • HAL_GPIO_TogglePin() : stm32wbxx_hal_gpio.c
  • HAL_GPIO_WritePin() : stm32wbxx_hal_gpio.c
  • HAL_HalfDuplex_EnableReceiver() : stm32wbxx_hal_uart.c
  • HAL_HalfDuplex_EnableTransmitter() : stm32wbxx_hal_uart.c
  • HAL_HalfDuplex_Init() : stm32wbxx_hal_uart.c
  • HAL_HSEM_ActivateNotification() : stm32wbxx_hal_hsem.c
  • HAL_HSEM_DeactivateNotification() : stm32wbxx_hal_hsem.c
  • HAL_HSEM_FastTake() : stm32wbxx_hal_hsem.c
  • HAL_HSEM_FreeCallback() : stm32wbxx_hal_hsem.c
  • HAL_HSEM_GetClearKey() : stm32wbxx_hal_hsem.c
  • HAL_HSEM_IRQHandler() : stm32wbxx_hal_hsem.c
  • HAL_HSEM_IsSemTaken() : stm32wbxx_hal_hsem.c
  • HAL_HSEM_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_HSEM_Release() : stm32wbxx_hal_hsem.c
  • HAL_HSEM_ReleaseAll() : stm32wbxx_hal_hsem.c
  • HAL_HSEM_SetClearKey() : stm32wbxx_hal_hsem.c
  • HAL_HSEM_Take() : stm32wbxx_hal_hsem.c
  • HAL_I2C_ABORT_CB_ID : stm32wbxx_hal_i2c.h
  • HAL_I2C_AbortCpltCallback() : stm32wbxx_hal_i2c.c
  • HAL_I2C_AddrCallback() : stm32wbxx_hal_i2c.c
  • HAL_I2C_CallbackIDTypeDef : stm32wbxx_hal_i2c.h
  • HAL_I2C_DeInit() : stm32wbxx_hal_i2c.c
  • HAL_I2C_DisableListen_IT() : stm32wbxx_hal_i2c.c
  • HAL_I2C_EnableListen_IT() : stm32wbxx_hal_i2c.c
  • HAL_I2C_ER_IRQHandler() : stm32wbxx_hal_i2c.c
  • HAL_I2C_ERROR_AF : stm32wbxx_hal_i2c.h
  • HAL_I2C_ERROR_ARLO : stm32wbxx_hal_i2c.h
  • HAL_I2C_ERROR_BERR : stm32wbxx_hal_i2c.h
  • HAL_I2C_ERROR_CB_ID : stm32wbxx_hal_i2c.h
  • HAL_I2C_ERROR_DMA : stm32wbxx_hal_i2c.h
  • HAL_I2C_ERROR_DMA_PARAM : stm32wbxx_hal_i2c.h
  • HAL_I2C_ERROR_INVALID_CALLBACK : stm32wbxx_hal_i2c.h
  • HAL_I2C_ERROR_INVALID_PARAM : stm32wbxx_hal_i2c.h
  • HAL_I2C_ERROR_NONE : stm32wbxx_hal_i2c.h
  • HAL_I2C_ERROR_OVR : stm32wbxx_hal_i2c.h
  • HAL_I2C_ERROR_SIZE : stm32wbxx_hal_i2c.h
  • HAL_I2C_ERROR_TIMEOUT : stm32wbxx_hal_i2c.h
  • HAL_I2C_ErrorCallback() : stm32wbxx_hal_i2c.c
  • HAL_I2C_EV_IRQHandler() : stm32wbxx_hal_i2c.c
  • HAL_I2C_GetError() : stm32wbxx_hal_i2c.c
  • HAL_I2C_GetMode() : stm32wbxx_hal_i2c.c
  • HAL_I2C_GetState() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Init() : stm32wbxx_hal_i2c.c
  • HAL_I2C_IsDeviceReady() : stm32wbxx_hal_i2c.c
  • HAL_I2C_LISTEN_COMPLETE_CB_ID : stm32wbxx_hal_i2c.h
  • HAL_I2C_ListenCpltCallback() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Master_Abort_IT() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Master_Receive() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Master_Receive_DMA() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Master_Receive_IT() : stm32wbxx_hal_i2c.c
  • HAL_I2C_MASTER_RX_COMPLETE_CB_ID : stm32wbxx_hal_i2c.h
  • HAL_I2C_Master_Seq_Receive_DMA() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Master_Seq_Receive_IT() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Master_Seq_Transmit_DMA() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Master_Seq_Transmit_IT() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Master_Transmit() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Master_Transmit_DMA() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Master_Transmit_IT() : stm32wbxx_hal_i2c.c
  • HAL_I2C_MASTER_TX_COMPLETE_CB_ID : stm32wbxx_hal_i2c.h
  • HAL_I2C_MasterRxCpltCallback() : stm32wbxx_hal_i2c.c
  • HAL_I2C_MasterTxCpltCallback() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Mem_Read() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Mem_Read_DMA() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Mem_Read_IT() : stm32wbxx_hal_i2c.c
  • HAL_I2C_MEM_RX_COMPLETE_CB_ID : stm32wbxx_hal_i2c.h
  • HAL_I2C_MEM_TX_COMPLETE_CB_ID : stm32wbxx_hal_i2c.h
  • HAL_I2C_Mem_Write() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Mem_Write_DMA() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Mem_Write_IT() : stm32wbxx_hal_i2c.c
  • HAL_I2C_MemRxCpltCallback() : stm32wbxx_hal_i2c.c
  • HAL_I2C_MemTxCpltCallback() : stm32wbxx_hal_i2c.c
  • HAL_I2C_MODE_MASTER : stm32wbxx_hal_i2c.h
  • HAL_I2C_MODE_MEM : stm32wbxx_hal_i2c.h
  • HAL_I2C_MODE_NONE : stm32wbxx_hal_i2c.h
  • HAL_I2C_MODE_SLAVE : stm32wbxx_hal_i2c.h
  • HAL_I2C_ModeTypeDef : stm32wbxx_hal_i2c.h
  • HAL_I2C_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_I2C_MspDeInit() : stm32wbxx_hal_i2c.c
  • HAL_I2C_MSPDEINIT_CB_ID : stm32wbxx_hal_i2c.h
  • HAL_I2C_MspInit() : stm32wbxx_hal_i2c.c
  • HAL_I2C_MSPINIT_CB_ID : stm32wbxx_hal_i2c.h
  • HAL_I2C_RegisterAddrCallback() : stm32wbxx_hal_i2c.c
  • HAL_I2C_RegisterCallback() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Slave_Receive() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Slave_Receive_DMA() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Slave_Receive_IT() : stm32wbxx_hal_i2c.c
  • HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : stm32wbxx_hal_i2c.h
  • HAL_I2C_Slave_Seq_Receive_DMA() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Slave_Seq_Receive_IT() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Slave_Seq_Transmit_DMA() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Slave_Seq_Transmit_IT() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Slave_Transmit() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_DMA() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_IT() : stm32wbxx_hal_i2c.c
  • HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : stm32wbxx_hal_i2c.h
  • HAL_I2C_SlaveRxCpltCallback() : stm32wbxx_hal_i2c.c
  • HAL_I2C_SlaveTxCpltCallback() : stm32wbxx_hal_i2c.c
  • HAL_I2C_STATE_ABORT : stm32wbxx_hal_i2c.h
  • HAL_I2C_STATE_BUSY : stm32wbxx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_RX : stm32wbxx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_RX_LISTEN : stm32wbxx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_TX : stm32wbxx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_TX_LISTEN : stm32wbxx_hal_i2c.h
  • HAL_I2C_STATE_ERROR : stm32wbxx_hal_i2c.h
  • HAL_I2C_STATE_LISTEN : stm32wbxx_hal_i2c.h
  • HAL_I2C_STATE_READY : stm32wbxx_hal_i2c.h
  • HAL_I2C_STATE_RESET : stm32wbxx_hal_i2c.h
  • HAL_I2C_STATE_TIMEOUT : stm32wbxx_hal_i2c.h
  • HAL_I2C_StateTypeDef : stm32wbxx_hal_i2c.h
  • HAL_I2C_UnRegisterAddrCallback() : stm32wbxx_hal_i2c.c
  • HAL_I2C_UnRegisterCallback() : stm32wbxx_hal_i2c.c
  • HAL_I2CEx_ConfigAnalogFilter() : stm32wbxx_hal_i2c_ex.c
  • HAL_I2CEx_ConfigDigitalFilter() : stm32wbxx_hal_i2c_ex.c
  • HAL_I2CEx_DisableFastModePlus() : stm32wbxx_hal_i2c_ex.c
  • HAL_I2CEx_DisableWakeUp() : stm32wbxx_hal_i2c_ex.c
  • HAL_I2CEx_EnableFastModePlus() : stm32wbxx_hal_i2c_ex.c
  • HAL_I2CEx_EnableWakeUp() : stm32wbxx_hal_i2c_ex.c
  • HAL_IncTick() : stm32wbxx_hal.c
  • HAL_Init() : stm32wbxx_hal.c
  • HAL_InitTick() : stm32wbxx_hal.c
  • HAL_IPCC_ActivateNotification() : stm32wbxx_hal_ipcc.c
  • HAL_IPCC_DeActivateNotification() : stm32wbxx_hal_ipcc.c
  • HAL_IPCC_DeInit() : stm32wbxx_hal_ipcc.c
  • HAL_IPCC_GetChannelStatus() : stm32wbxx_hal_ipcc.c
  • HAL_IPCC_GetState() : stm32wbxx_hal_ipcc.c
  • HAL_IPCC_Init() : stm32wbxx_hal_ipcc.c
  • HAL_IPCC_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_IPCC_MspDeInit() : stm32wbxx_hal_ipcc.c
  • HAL_IPCC_MspInit() : stm32wbxx_hal_ipcc.c
  • HAL_IPCC_NotifyCPU() : stm32wbxx_hal_ipcc.c
  • HAL_IPCC_RX_IRQHandler() : stm32wbxx_hal_ipcc.c
  • HAL_IPCC_RxCallback() : stm32wbxx_hal_ipcc.c
  • HAL_IPCC_STATE_BUSY : stm32wbxx_hal_ipcc.h
  • HAL_IPCC_STATE_READY : stm32wbxx_hal_ipcc.h
  • HAL_IPCC_STATE_RESET : stm32wbxx_hal_ipcc.h
  • HAL_IPCC_StateTypeDef : stm32wbxx_hal_ipcc.h
  • HAL_IPCC_TX_IRQHandler() : stm32wbxx_hal_ipcc.c
  • HAL_IPCC_TxCallback() : stm32wbxx_hal_ipcc.c
  • HAL_IRDA_Abort() : stm32wbxx_hal_irda.c
  • HAL_IRDA_ABORT_COMPLETE_CB_ID : stm32wbxx_hal_irda.h
  • HAL_IRDA_Abort_IT() : stm32wbxx_hal_irda.c
  • HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID : stm32wbxx_hal_irda.h
  • HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID : stm32wbxx_hal_irda.h
  • HAL_IRDA_AbortCpltCallback() : stm32wbxx_hal_irda.c
  • HAL_IRDA_AbortReceive() : stm32wbxx_hal_irda.c
  • HAL_IRDA_AbortReceive_IT() : stm32wbxx_hal_irda.c
  • HAL_IRDA_AbortReceiveCpltCallback() : stm32wbxx_hal_irda.c
  • HAL_IRDA_AbortTransmit() : stm32wbxx_hal_irda.c
  • HAL_IRDA_AbortTransmit_IT() : stm32wbxx_hal_irda.c
  • HAL_IRDA_AbortTransmitCpltCallback() : stm32wbxx_hal_irda.c
  • HAL_IRDA_CallbackIDTypeDef : stm32wbxx_hal_irda.h
  • HAL_IRDA_DeInit() : stm32wbxx_hal_irda.c
  • HAL_IRDA_DMAPause() : stm32wbxx_hal_irda.c
  • HAL_IRDA_DMAResume() : stm32wbxx_hal_irda.c
  • HAL_IRDA_DMAStop() : stm32wbxx_hal_irda.c
  • HAL_IRDA_ERROR_BUSY : stm32wbxx_hal_irda.h
  • HAL_IRDA_ERROR_CB_ID : stm32wbxx_hal_irda.h
  • HAL_IRDA_ERROR_DMA : stm32wbxx_hal_irda.h
  • HAL_IRDA_ERROR_FE : stm32wbxx_hal_irda.h
  • HAL_IRDA_ERROR_INVALID_CALLBACK : stm32wbxx_hal_irda.h
  • HAL_IRDA_ERROR_NE : stm32wbxx_hal_irda.h
  • HAL_IRDA_ERROR_NONE : stm32wbxx_hal_irda.h
  • HAL_IRDA_ERROR_ORE : stm32wbxx_hal_irda.h
  • HAL_IRDA_ERROR_PE : stm32wbxx_hal_irda.h
  • HAL_IRDA_ErrorCallback() : stm32wbxx_hal_irda.c
  • HAL_IRDA_GetError() : stm32wbxx_hal_irda.c
  • HAL_IRDA_GetState() : stm32wbxx_hal_irda.c
  • HAL_IRDA_Init() : stm32wbxx_hal_irda.c
  • HAL_IRDA_IRQHandler() : stm32wbxx_hal_irda.c
  • HAL_IRDA_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_IRDA_MspDeInit() : stm32wbxx_hal_irda.c
  • HAL_IRDA_MSPDEINIT_CB_ID : stm32wbxx_hal_irda.h
  • HAL_IRDA_MspInit() : stm32wbxx_hal_irda.c
  • HAL_IRDA_MSPINIT_CB_ID : stm32wbxx_hal_irda.h
  • HAL_IRDA_Receive() : stm32wbxx_hal_irda.c
  • HAL_IRDA_Receive_DMA() : stm32wbxx_hal_irda.c
  • HAL_IRDA_Receive_IT() : stm32wbxx_hal_irda.c
  • HAL_IRDA_RegisterCallback() : stm32wbxx_hal_irda.c
  • HAL_IRDA_RX_COMPLETE_CB_ID : stm32wbxx_hal_irda.h
  • HAL_IRDA_RX_HALFCOMPLETE_CB_ID : stm32wbxx_hal_irda.h
  • HAL_IRDA_RxCpltCallback() : stm32wbxx_hal_irda.c
  • HAL_IRDA_RxHalfCpltCallback() : stm32wbxx_hal_irda.c
  • HAL_IRDA_STATE_BUSY : stm32wbxx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_RX : stm32wbxx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX : stm32wbxx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX_RX : stm32wbxx_hal_irda.h
  • HAL_IRDA_STATE_ERROR : stm32wbxx_hal_irda.h
  • HAL_IRDA_STATE_READY : stm32wbxx_hal_irda.h
  • HAL_IRDA_STATE_RESET : stm32wbxx_hal_irda.h
  • HAL_IRDA_STATE_TIMEOUT : stm32wbxx_hal_irda.h
  • HAL_IRDA_StateTypeDef : stm32wbxx_hal_irda.h
  • HAL_IRDA_Transmit() : stm32wbxx_hal_irda.c
  • HAL_IRDA_Transmit_DMA() : stm32wbxx_hal_irda.c
  • HAL_IRDA_Transmit_IT() : stm32wbxx_hal_irda.c
  • HAL_IRDA_TX_COMPLETE_CB_ID : stm32wbxx_hal_irda.h
  • HAL_IRDA_TX_HALFCOMPLETE_CB_ID : stm32wbxx_hal_irda.h
  • HAL_IRDA_TxCpltCallback() : stm32wbxx_hal_irda.c
  • HAL_IRDA_TxHalfCpltCallback() : stm32wbxx_hal_irda.c
  • HAL_IRDA_UnRegisterCallback() : stm32wbxx_hal_irda.c
  • HAL_IWDG_DEFAULT_TIMEOUT : stm32wbxx_hal_iwdg.c
  • HAL_IWDG_Init() : stm32wbxx_hal_iwdg.c
  • HAL_IWDG_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_IWDG_Refresh() : stm32wbxx_hal_iwdg.c
  • HAL_LCD_Clear() : stm32wbxx_hal_lcd.c
  • HAL_LCD_DeInit() : stm32wbxx_hal_lcd.c
  • HAL_LCD_ERROR_ENS : stm32wbxx_hal_lcd.h
  • HAL_LCD_ERROR_FCRSF : stm32wbxx_hal_lcd.h
  • HAL_LCD_ERROR_NONE : stm32wbxx_hal_lcd.h
  • HAL_LCD_ERROR_RDY : stm32wbxx_hal_lcd.h
  • HAL_LCD_ERROR_UDD : stm32wbxx_hal_lcd.h
  • HAL_LCD_ERROR_UDR : stm32wbxx_hal_lcd.h
  • HAL_LCD_GetError() : stm32wbxx_hal_lcd.c
  • HAL_LCD_GetState() : stm32wbxx_hal_lcd.c
  • HAL_LCD_Init() : stm32wbxx_hal_lcd.c
  • HAL_LCD_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_LCD_MspDeInit() : stm32wbxx_hal_lcd.c
  • HAL_LCD_MspInit() : stm32wbxx_hal_lcd.c
  • HAL_LCD_STATE_BUSY : stm32wbxx_hal_lcd.h
  • HAL_LCD_STATE_ERROR : stm32wbxx_hal_lcd.h
  • HAL_LCD_STATE_READY : stm32wbxx_hal_lcd.h
  • HAL_LCD_STATE_RESET : stm32wbxx_hal_lcd.h
  • HAL_LCD_STATE_TIMEOUT : stm32wbxx_hal_lcd.h
  • HAL_LCD_StateTypeDef : stm32wbxx_hal_lcd.h
  • HAL_LCD_UpdateDisplayRequest() : stm32wbxx_hal_lcd.c
  • HAL_LCD_Write() : stm32wbxx_hal_lcd.c
  • HAL_LIN_Init() : stm32wbxx_hal_uart.c
  • HAL_LIN_SendBreak() : stm32wbxx_hal_uart.c
  • HAL_LPTIM_AUTORELOAD_MATCH_CB_ID : stm32wbxx_hal_lptim.h
  • HAL_LPTIM_AUTORELOAD_WRITE_CB_ID : stm32wbxx_hal_lptim.h
  • HAL_LPTIM_AutoReloadMatchCallback() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_AutoReloadWriteCallback() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_CallbackIDTypeDef : stm32wbxx_hal_lptim.h
  • HAL_LPTIM_COMPARE_MATCH_CB_ID : stm32wbxx_hal_lptim.h
  • HAL_LPTIM_COMPARE_WRITE_CB_ID : stm32wbxx_hal_lptim.h
  • HAL_LPTIM_CompareMatchCallback() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_CompareWriteCallback() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_Counter_Start() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_Counter_Start_IT() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_Counter_Stop() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_Counter_Stop_IT() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_DeInit() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_DIRECTION_DOWN_CB_ID : stm32wbxx_hal_lptim.h
  • HAL_LPTIM_DIRECTION_UP_CB_ID : stm32wbxx_hal_lptim.h
  • HAL_LPTIM_DirectionDownCallback() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_DirectionUpCallback() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_Encoder_Start() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_Encoder_Start_IT() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_Encoder_Stop() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_Encoder_Stop_IT() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_GetState() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_Init() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_IRQHandler() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_LPTIM_MspDeInit() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_MSPDEINIT_CB_ID : stm32wbxx_hal_lptim.h
  • HAL_LPTIM_MspInit() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_MSPINIT_CB_ID : stm32wbxx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Start() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Start_IT() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Stop() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Stop_IT() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_PWM_Start() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_PWM_Start_IT() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_PWM_Stop() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_PWM_Stop_IT() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_ReadAutoReload() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_ReadCompare() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_ReadCounter() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_RegisterCallback() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Start() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Start_IT() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Stop() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Stop_IT() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_STATE_BUSY : stm32wbxx_hal_lptim.h
  • HAL_LPTIM_STATE_ERROR : stm32wbxx_hal_lptim.h
  • HAL_LPTIM_STATE_READY : stm32wbxx_hal_lptim.h
  • HAL_LPTIM_STATE_RESET : stm32wbxx_hal_lptim.h
  • HAL_LPTIM_STATE_TIMEOUT : stm32wbxx_hal_lptim.h
  • HAL_LPTIM_StateTypeDef : stm32wbxx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Start() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Start_IT() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Stop() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Stop_IT() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_TRIGGER_CB_ID : stm32wbxx_hal_lptim.h
  • HAL_LPTIM_TriggerCallback() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_UnRegisterCallback() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_MPU_ConfigRegion() : stm32wbxx_hal_cortex.c
  • HAL_MPU_Disable() : stm32wbxx_hal_cortex.c
  • HAL_MPU_Enable() : stm32wbxx_hal_cortex.c
  • HAL_MspDeInit() : stm32wbxx_hal.c
  • HAL_MspInit() : stm32wbxx_hal.c
  • HAL_MultiProcessor_DisableMuteMode() : stm32wbxx_hal_uart.c
  • HAL_MultiProcessor_EnableMuteMode() : stm32wbxx_hal_uart.c
  • HAL_MultiProcessor_EnterMuteMode() : stm32wbxx_hal_uart.c
  • HAL_MultiProcessor_Init() : stm32wbxx_hal_uart.c
  • HAL_MultiProcessorEx_AddressLength_Set() : stm32wbxx_hal_uart_ex.c
  • HAL_NVIC_ClearPendingIRQ() : stm32wbxx_hal_cortex.c
  • HAL_NVIC_DisableIRQ() : stm32wbxx_hal_cortex.c
  • HAL_NVIC_EnableIRQ() : stm32wbxx_hal_cortex.c
  • HAL_NVIC_GetPendingIRQ() : stm32wbxx_hal_cortex.c
  • HAL_NVIC_GetPriority() : stm32wbxx_hal_cortex.c
  • HAL_NVIC_GetPriorityGrouping() : stm32wbxx_hal_cortex.c
  • HAL_NVIC_SetPendingIRQ() : stm32wbxx_hal_cortex.c
  • HAL_NVIC_SetPriority() : stm32wbxx_hal_cortex.c
  • HAL_NVIC_SetPriorityGrouping() : stm32wbxx_hal_cortex.c
  • HAL_NVIC_SystemReset() : stm32wbxx_hal_cortex.c
  • HAL_PCD_ActivateRemoteWakeup() : stm32wbxx_hal_pcd.c
  • HAL_PCD_CallbackIDTypeDef : stm32wbxx_hal_pcd.h
  • HAL_PCD_CONNECT_CB_ID : stm32wbxx_hal_pcd.h
  • HAL_PCD_ConnectCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_DataInStageCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_DataOutStageCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_DeActivateRemoteWakeup() : stm32wbxx_hal_pcd.c
  • HAL_PCD_DeInit() : stm32wbxx_hal_pcd.c
  • HAL_PCD_DevConnect() : stm32wbxx_hal_pcd.c
  • HAL_PCD_DevDisconnect() : stm32wbxx_hal_pcd.c
  • HAL_PCD_DISCONNECT_CB_ID : stm32wbxx_hal_pcd.h
  • HAL_PCD_DisconnectCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_EP_Close() : stm32wbxx_hal_pcd.c
  • HAL_PCD_EP_ClrStall() : stm32wbxx_hal_pcd.c
  • HAL_PCD_EP_Flush() : stm32wbxx_hal_pcd.c
  • HAL_PCD_EP_GetRxCount() : stm32wbxx_hal_pcd.c
  • HAL_PCD_EP_Open() : stm32wbxx_hal_pcd.c
  • HAL_PCD_EP_Receive() : stm32wbxx_hal_pcd.c
  • HAL_PCD_EP_SetStall() : stm32wbxx_hal_pcd.c
  • HAL_PCD_EP_Transmit() : stm32wbxx_hal_pcd.c
  • HAL_PCD_ERROR_INVALID_CALLBACK : stm32wbxx_hal_pcd.h
  • HAL_PCD_GetState() : stm32wbxx_hal_pcd.c
  • HAL_PCD_Init() : stm32wbxx_hal_pcd.c
  • HAL_PCD_IRQHandler() : stm32wbxx_hal_pcd.c
  • HAL_PCD_ISOINIncompleteCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_ISOOUTIncompleteCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_PCD_MspDeInit() : stm32wbxx_hal_pcd.c
  • HAL_PCD_MSPDEINIT_CB_ID : stm32wbxx_hal_pcd.h
  • HAL_PCD_MspInit() : stm32wbxx_hal_pcd.c
  • HAL_PCD_MSPINIT_CB_ID : stm32wbxx_hal_pcd.h
  • HAL_PCD_RegisterBcdCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_RegisterCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_RegisterDataInStageCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_RegisterDataOutStageCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_RegisterIsoInIncpltCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_RegisterIsoOutIncpltCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_RegisterLpmCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_RESET_CB_ID : stm32wbxx_hal_pcd.h
  • HAL_PCD_ResetCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_RESUME_CB_ID : stm32wbxx_hal_pcd.h
  • HAL_PCD_ResumeCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_SetAddress() : stm32wbxx_hal_pcd.c
  • HAL_PCD_SETUPSTAGE_CB_ID : stm32wbxx_hal_pcd.h
  • HAL_PCD_SetupStageCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_SOF_CB_ID : stm32wbxx_hal_pcd.h
  • HAL_PCD_SOFCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_Start() : stm32wbxx_hal_pcd.c
  • HAL_PCD_STATE_BUSY : stm32wbxx_hal_pcd.h
  • HAL_PCD_STATE_ERROR : stm32wbxx_hal_pcd.h
  • HAL_PCD_STATE_READY : stm32wbxx_hal_pcd.h
  • HAL_PCD_STATE_RESET : stm32wbxx_hal_pcd.h
  • HAL_PCD_STATE_TIMEOUT : stm32wbxx_hal_pcd.h
  • HAL_PCD_Stop() : stm32wbxx_hal_pcd.c
  • HAL_PCD_SUSPEND_CB_ID : stm32wbxx_hal_pcd.h
  • HAL_PCD_SuspendCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_UnRegisterBcdCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_UnRegisterCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_UnRegisterDataInStageCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_UnRegisterDataOutStageCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_UnRegisterIsoInIncpltCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_UnRegisterIsoOutIncpltCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_UnRegisterLpmCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCDEx_ActivateBCD() : stm32wbxx_hal_pcd_ex.c
  • HAL_PCDEx_ActivateLPM() : stm32wbxx_hal_pcd_ex.c
  • HAL_PCDEx_BCD_Callback() : stm32wbxx_hal_pcd_ex.c
  • HAL_PCDEx_BCD_VBUSDetect() : stm32wbxx_hal_pcd_ex.c
  • HAL_PCDEx_DeActivateBCD() : stm32wbxx_hal_pcd_ex.c
  • HAL_PCDEx_DeActivateLPM() : stm32wbxx_hal_pcd_ex.c
  • HAL_PCDEx_LPM_Callback() : stm32wbxx_hal_pcd_ex.c
  • HAL_PCDEx_PMAConfig() : stm32wbxx_hal_pcd_ex.c
  • HAL_PKA_Abort() : stm32wbxx_hal_pka.c
  • HAL_PKA_Add() : stm32wbxx_hal_pka.c
  • HAL_PKA_Add_IT() : stm32wbxx_hal_pka.c
  • HAL_PKA_Arithmetic_GetResult() : stm32wbxx_hal_pka.c
  • HAL_PKA_CallbackIDTypeDef : stm32wbxx_hal_pka.h
  • HAL_PKA_Cmp() : stm32wbxx_hal_pka.c
  • HAL_PKA_Cmp_IT() : stm32wbxx_hal_pka.c
  • HAL_PKA_DeInit() : stm32wbxx_hal_pka.c
  • HAL_PKA_ECCMul() : stm32wbxx_hal_pka.c
  • HAL_PKA_ECCMul_GetResult() : stm32wbxx_hal_pka.c
  • HAL_PKA_ECCMul_IT() : stm32wbxx_hal_pka.c
  • HAL_PKA_ECCMulFastMode() : stm32wbxx_hal_pka.c
  • HAL_PKA_ECCMulFastMode_IT() : stm32wbxx_hal_pka.c
  • HAL_PKA_ECDSASign() : stm32wbxx_hal_pka.c
  • HAL_PKA_ECDSASign_GetResult() : stm32wbxx_hal_pka.c
  • HAL_PKA_ECDSASign_IT() : stm32wbxx_hal_pka.c
  • HAL_PKA_ECDSAVerif() : stm32wbxx_hal_pka.c
  • HAL_PKA_ECDSAVerif_IsValidSignature() : stm32wbxx_hal_pka.c
  • HAL_PKA_ECDSAVerif_IT() : stm32wbxx_hal_pka.c
  • HAL_PKA_ERROR_ADDRERR : stm32wbxx_hal_pka.h
  • HAL_PKA_ERROR_CB_ID : stm32wbxx_hal_pka.h
  • HAL_PKA_ERROR_INVALID_CALLBACK : stm32wbxx_hal_pka.h
  • HAL_PKA_ERROR_NONE : stm32wbxx_hal_pka.h
  • HAL_PKA_ERROR_OPERATION : stm32wbxx_hal_pka.h
  • HAL_PKA_ERROR_RAMERR : stm32wbxx_hal_pka.h
  • HAL_PKA_ERROR_TIMEOUT : stm32wbxx_hal_pka.h
  • HAL_PKA_ErrorCallback() : stm32wbxx_hal_pka.c
  • HAL_PKA_GetError() : stm32wbxx_hal_pka.c
  • HAL_PKA_GetState() : stm32wbxx_hal_pka.c
  • HAL_PKA_Init() : stm32wbxx_hal_pka.c
  • HAL_PKA_IRQHandler() : stm32wbxx_hal_pka.c
  • HAL_PKA_ModAdd() : stm32wbxx_hal_pka.c
  • HAL_PKA_ModAdd_IT() : stm32wbxx_hal_pka.c
  • HAL_PKA_ModExp() : stm32wbxx_hal_pka.c
  • HAL_PKA_ModExp_GetResult() : stm32wbxx_hal_pka.c
  • HAL_PKA_ModExp_IT() : stm32wbxx_hal_pka.c
  • HAL_PKA_ModExpFastMode() : stm32wbxx_hal_pka.c
  • HAL_PKA_ModExpFastMode_IT() : stm32wbxx_hal_pka.c
  • HAL_PKA_ModInv() : stm32wbxx_hal_pka.c
  • HAL_PKA_ModInv_IT() : stm32wbxx_hal_pka.c
  • HAL_PKA_ModRed() : stm32wbxx_hal_pka.c
  • HAL_PKA_ModRed_IT() : stm32wbxx_hal_pka.c
  • HAL_PKA_ModSub() : stm32wbxx_hal_pka.c
  • HAL_PKA_ModSub_IT() : stm32wbxx_hal_pka.c
  • HAL_PKA_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_PKA_MontgomeryMul() : stm32wbxx_hal_pka.c
  • HAL_PKA_MontgomeryMul_IT() : stm32wbxx_hal_pka.c
  • HAL_PKA_MontgomeryParam() : stm32wbxx_hal_pka.c
  • HAL_PKA_MontgomeryParam_GetResult() : stm32wbxx_hal_pka.c
  • HAL_PKA_MontgomeryParam_IT() : stm32wbxx_hal_pka.c
  • HAL_PKA_MspDeInit() : stm32wbxx_hal_pka.c
  • HAL_PKA_MSPDEINIT_CB_ID : stm32wbxx_hal_pka.h
  • HAL_PKA_MspInit() : stm32wbxx_hal_pka.c
  • HAL_PKA_MSPINIT_CB_ID : stm32wbxx_hal_pka.h
  • HAL_PKA_Mul() : stm32wbxx_hal_pka.c
  • HAL_PKA_Mul_IT() : stm32wbxx_hal_pka.c
  • HAL_PKA_OPERATION_COMPLETE_CB_ID : stm32wbxx_hal_pka.h
  • HAL_PKA_OperationCpltCallback() : stm32wbxx_hal_pka.c
  • HAL_PKA_PointCheck() : stm32wbxx_hal_pka.c
  • HAL_PKA_PointCheck_IsOnCurve() : stm32wbxx_hal_pka.c
  • HAL_PKA_PointCheck_IT() : stm32wbxx_hal_pka.c
  • HAL_PKA_RAMReset() : stm32wbxx_hal_pka.c
  • HAL_PKA_RegisterCallback() : stm32wbxx_hal_pka.c
  • HAL_PKA_RSACRTExp() : stm32wbxx_hal_pka.c
  • HAL_PKA_RSACRTExp_GetResult() : stm32wbxx_hal_pka.c
  • HAL_PKA_RSACRTExp_IT() : stm32wbxx_hal_pka.c
  • HAL_PKA_STATE_BUSY : stm32wbxx_hal_pka.h
  • HAL_PKA_STATE_ERROR : stm32wbxx_hal_pka.h
  • HAL_PKA_STATE_READY : stm32wbxx_hal_pka.h
  • HAL_PKA_STATE_RESET : stm32wbxx_hal_pka.h
  • HAL_PKA_StateTypeDef : stm32wbxx_hal_pka.h
  • HAL_PKA_Sub() : stm32wbxx_hal_pka.c
  • HAL_PKA_Sub_IT() : stm32wbxx_hal_pka.c
  • HAL_PKA_UnRegisterCallback() : stm32wbxx_hal_pka.c
  • HAL_PWR_ConfigPVD() : stm32wbxx_hal_pwr.c
  • HAL_PWR_DeInit() : stm32wbxx_hal_pwr.c
  • HAL_PWR_DisableBkUpAccess() : stm32wbxx_hal_pwr.c
  • HAL_PWR_DisablePVD() : stm32wbxx_hal_pwr.c
  • HAL_PWR_DisableSEVOnPend() : stm32wbxx_hal_pwr.c
  • HAL_PWR_DisableSleepOnExit() : stm32wbxx_hal_pwr.c
  • HAL_PWR_DisableWakeUpPin() : stm32wbxx_hal_pwr.c
  • HAL_PWR_EnableBkUpAccess() : stm32wbxx_hal_pwr.c
  • HAL_PWR_EnablePVD() : stm32wbxx_hal_pwr.c
  • HAL_PWR_EnableSEVOnPend() : stm32wbxx_hal_pwr.c
  • HAL_PWR_EnableSleepOnExit() : stm32wbxx_hal_pwr.c
  • HAL_PWR_EnableWakeUpPin() : stm32wbxx_hal_pwr.c
  • HAL_PWR_EnterSLEEPMode() : stm32wbxx_hal_pwr.c
  • HAL_PWR_EnterSTANDBYMode() : stm32wbxx_hal_pwr.c
  • HAL_PWR_EnterSTOPMode() : stm32wbxx_hal_pwr.c
  • HAL_PWR_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_PWR_PVDCallback() : stm32wbxx_hal_pwr.c
  • HAL_PWREx_ClearWakeupFlag() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_ConfigPVM() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_ConfigSMPS() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_ControlVoltageScaling() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_Disable802ActivityIT() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_DisableBatteryCharging() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_DisableBLEActivityIT() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_DisableBORH_SMPSBypassIT() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_DisableFlashPowerDown() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_DisableGPIOPullDown() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_DisableGPIOPullUp() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_DisableHOLDC2IT() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_DisableInternalWakeUpLine() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_DisableLowPowerRunMode() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_DisablePullUpPullDownConfig() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_DisablePVM1() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_DisablePVM3() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_DisableRFPhaseIT() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_DisableSRAMRetention() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_DisableVddUSB() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_Enable802ActivityIT() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnableBatteryCharging() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnableBLEActivityIT() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnableBORH_SMPSBypassIT() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnableFlashPowerDown() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnableGPIOPullDown() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnableGPIOPullUp() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnableHOLDC2IT() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnableInternalWakeUpLine() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnableLowPowerRunMode() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnablePullUpPullDownConfig() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnablePVM1() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnablePVM3() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnableRFPhaseIT() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnableSRAMRetention() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnableVddUSB() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnableWakeUpPin() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnterSHUTDOWNMode() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnterSTOP0Mode() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnterSTOP1Mode() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnterSTOP2Mode() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_GetBORConfig() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_GetVoltageRange() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_GetWakeupFlag() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_HoldCore() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_PVD_PVM_IRQHandler() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_PVM1Callback() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_PVM3Callback() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_ReleaseCore() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_SetBORConfig() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_SMPS_GetEffectiveMode() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_SMPS_SetMode() : stm32wbxx_hal_pwr_ex.c
  • HAL_QSPI_Abort() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_ABORT_CB_ID : stm32wbxx_hal_qspi.h
  • HAL_QSPI_Abort_IT() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_AbortCpltCallback() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_AutoPolling() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_AutoPolling_IT() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_CallbackIDTypeDef : stm32wbxx_hal_qspi.h
  • HAL_QSPI_CMD_CPLT_CB_ID : stm32wbxx_hal_qspi.h
  • HAL_QSPI_CmdCpltCallback() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_Command() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_Command_IT() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_DeInit() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_ERROR_CB_ID : stm32wbxx_hal_qspi.h
  • HAL_QSPI_ERROR_DMA : stm32wbxx_hal_qspi.h
  • HAL_QSPI_ERROR_INVALID_CALLBACK : stm32wbxx_hal_qspi.h
  • HAL_QSPI_ERROR_INVALID_PARAM : stm32wbxx_hal_qspi.h
  • HAL_QSPI_ERROR_NONE : stm32wbxx_hal_qspi.h
  • HAL_QSPI_ERROR_TIMEOUT : stm32wbxx_hal_qspi.h
  • HAL_QSPI_ERROR_TRANSFER : stm32wbxx_hal_qspi.h
  • HAL_QSPI_ErrorCallback() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_FIFO_THRESHOLD_CB_ID : stm32wbxx_hal_qspi.h
  • HAL_QSPI_FifoThresholdCallback() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_GetError() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_GetFifoThreshold() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_GetState() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_Init() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_IRQHandler() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_MemoryMapped() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_QSPI_MSP_DEINIT_CB_ID : stm32wbxx_hal_qspi.h
  • HAL_QSPI_MSP_INIT_CB_ID : stm32wbxx_hal_qspi.h
  • HAL_QSPI_MspDeInit() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_MspInit() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_Receive() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_Receive_DMA() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_Receive_IT() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_RegisterCallback() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_RX_CPLT_CB_ID : stm32wbxx_hal_qspi.h
  • HAL_QSPI_RX_HALF_CPLT_CB_ID : stm32wbxx_hal_qspi.h
  • HAL_QSPI_RxCpltCallback() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_RxHalfCpltCallback() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_SetFifoThreshold() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_SetTimeout() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_STATE_ABORT : stm32wbxx_hal_qspi.h
  • HAL_QSPI_STATE_BUSY : stm32wbxx_hal_qspi.h
  • HAL_QSPI_STATE_BUSY_AUTO_POLLING : stm32wbxx_hal_qspi.h
  • HAL_QSPI_STATE_BUSY_INDIRECT_RX : stm32wbxx_hal_qspi.h
  • HAL_QSPI_STATE_BUSY_INDIRECT_TX : stm32wbxx_hal_qspi.h
  • HAL_QSPI_STATE_BUSY_MEM_MAPPED : stm32wbxx_hal_qspi.h
  • HAL_QSPI_STATE_ERROR : stm32wbxx_hal_qspi.h
  • HAL_QSPI_STATE_READY : stm32wbxx_hal_qspi.h
  • HAL_QSPI_STATE_RESET : stm32wbxx_hal_qspi.h
  • HAL_QSPI_StateTypeDef : stm32wbxx_hal_qspi.h
  • HAL_QSPI_STATUS_MATCH_CB_ID : stm32wbxx_hal_qspi.h
  • HAL_QSPI_StatusMatchCallback() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_TIMEOUT_CB_ID : stm32wbxx_hal_qspi.h
  • HAL_QSPI_TIMEOUT_DEFAULT_VALUE : stm32wbxx_hal_qspi.h
  • HAL_QSPI_TimeOutCallback() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_Transmit() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_Transmit_DMA() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_Transmit_IT() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_TX_CPLT_CB_ID : stm32wbxx_hal_qspi.h
  • HAL_QSPI_TX_HALF_CPLT_CB_ID : stm32wbxx_hal_qspi.h
  • HAL_QSPI_TxCpltCallback() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_TxHalfCpltCallback() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_UnRegisterCallback() : stm32wbxx_hal_qspi.c
  • HAL_RCC_ClockConfig() : stm32wbxx_hal_rcc.c
  • HAL_RCC_CSSCallback() : stm32wbxx_hal_rcc.c
  • HAL_RCC_DeInit() : stm32wbxx_hal_rcc.c
  • HAL_RCC_EnableCSS() : stm32wbxx_hal_rcc.c
  • HAL_RCC_GetClockConfig() : stm32wbxx_hal_rcc.c
  • HAL_RCC_GetHCLK2Freq() : stm32wbxx_hal_rcc.c
  • HAL_RCC_GetHCLK4Freq() : stm32wbxx_hal_rcc.c
  • HAL_RCC_GetHCLKFreq() : stm32wbxx_hal_rcc.c
  • HAL_RCC_GetOscConfig() : stm32wbxx_hal_rcc.c
  • HAL_RCC_GetPCLK1Freq() : stm32wbxx_hal_rcc.c
  • HAL_RCC_GetPCLK2Freq() : stm32wbxx_hal_rcc.c
  • HAL_RCC_GetSysClockFreq() : stm32wbxx_hal_rcc.c
  • HAL_RCC_MCOConfig() : stm32wbxx_hal_rcc.c
  • HAL_RCC_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_RCC_NMI_IRQHandler() : stm32wbxx_hal_rcc.c
  • HAL_RCC_OscConfig() : stm32wbxx_hal_rcc.c
  • HAL_RCCEx_CRS_ErrorCallback() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_ExpectedSyncCallback() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_IRQHandler() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_SyncOkCallback() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_SyncWarnCallback() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_CRSConfig() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_CRSGetSynchronizationInfo() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_CRSSoftwareSynchronizationGenerate() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_CRSWaitSynchronization() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_DisableLSCO() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_DisableLSECSS() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_DisableMSIPLLMode() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_DisablePLLSAI1() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_EnableLSCO() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_EnableLSECSS() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_EnableLSECSS_IT() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_EnableMSIPLLMode() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_EnablePLLSAI1() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_GetPeriphCLKConfig() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_GetPeriphCLKFreq() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_GetRngCLKSource() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_LSCOConfig() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_LSECSS_Callback() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_LSECSS_IRQHandler() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_PeriphCLKConfig() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_TrimOsc() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_WakeUpStopCLKConfig() : stm32wbxx_hal_rcc_ex.c
  • HAL_ResumeTick() : stm32wbxx_hal.c
  • HAL_RNG_CallbackIDTypeDef : stm32wbxx_hal_rng.h
  • HAL_RNG_DeInit() : stm32wbxx_hal_rng.c
  • HAL_RNG_ERROR_BUSY : stm32wbxx_hal_rng.h
  • HAL_RNG_ERROR_CB_ID : stm32wbxx_hal_rng.h
  • HAL_RNG_ERROR_CLOCK : stm32wbxx_hal_rng.h
  • HAL_RNG_ERROR_INVALID_CALLBACK : stm32wbxx_hal_rng.h
  • HAL_RNG_ERROR_NONE : stm32wbxx_hal_rng.h
  • HAL_RNG_ERROR_SEED : stm32wbxx_hal_rng.h
  • HAL_RNG_ERROR_TIMEOUT : stm32wbxx_hal_rng.h
  • HAL_RNG_ErrorCallback() : stm32wbxx_hal_rng.c
  • HAL_RNG_GenerateRandomNumber() : stm32wbxx_hal_rng.c
  • HAL_RNG_GenerateRandomNumber_IT() : stm32wbxx_hal_rng.c
  • HAL_RNG_GetError() : stm32wbxx_hal_rng.c
  • HAL_RNG_GetState() : stm32wbxx_hal_rng.c
  • HAL_RNG_Init() : stm32wbxx_hal_rng.c
  • HAL_RNG_IRQHandler() : stm32wbxx_hal_rng.c
  • HAL_RNG_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_RNG_MspDeInit() : stm32wbxx_hal_rng.c
  • HAL_RNG_MSPDEINIT_CB_ID : stm32wbxx_hal_rng.h
  • HAL_RNG_MspInit() : stm32wbxx_hal_rng.c
  • HAL_RNG_MSPINIT_CB_ID : stm32wbxx_hal_rng.h
  • HAL_RNG_ReadLastRandomNumber() : stm32wbxx_hal_rng.c
  • HAL_RNG_ReadyDataCallback() : stm32wbxx_hal_rng.c
  • HAL_RNG_RegisterCallback() : stm32wbxx_hal_rng.c
  • HAL_RNG_RegisterReadyDataCallback() : stm32wbxx_hal_rng.c
  • HAL_RNG_STATE_BUSY : stm32wbxx_hal_rng.h
  • HAL_RNG_STATE_ERROR : stm32wbxx_hal_rng.h
  • HAL_RNG_STATE_READY : stm32wbxx_hal_rng.h
  • HAL_RNG_STATE_RESET : stm32wbxx_hal_rng.h
  • HAL_RNG_STATE_TIMEOUT : stm32wbxx_hal_rng.h
  • HAL_RNG_StateTypeDef : stm32wbxx_hal_rng.h
  • HAL_RNG_UnRegisterCallback() : stm32wbxx_hal_rng.c
  • HAL_RNG_UnRegisterReadyDataCallback() : stm32wbxx_hal_rng.c
  • HAL_RS485Ex_Init() : stm32wbxx_hal_uart_ex.c
  • HAL_RTC_ALARM_A_EVENT_CB_ID : stm32wbxx_hal_rtc.h
  • HAL_RTC_ALARM_B_EVENT_CB_ID : stm32wbxx_hal_rtc.h
  • HAL_RTC_AlarmAEventCallback() : stm32wbxx_hal_rtc.c
  • HAL_RTC_AlarmIRQHandler() : stm32wbxx_hal_rtc.c
  • HAL_RTC_CallbackIDTypeDef : stm32wbxx_hal_rtc.h
  • HAL_RTC_DeactivateAlarm() : stm32wbxx_hal_rtc.c
  • HAL_RTC_DeInit() : stm32wbxx_hal_rtc.c
  • HAL_RTC_GetAlarm() : stm32wbxx_hal_rtc.c
  • HAL_RTC_GetDate() : stm32wbxx_hal_rtc.c
  • HAL_RTC_GetState() : stm32wbxx_hal_rtc.c
  • HAL_RTC_GetTime() : stm32wbxx_hal_rtc.c
  • HAL_RTC_Init() : stm32wbxx_hal_rtc.c
  • HAL_RTC_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_RTC_MspDeInit() : stm32wbxx_hal_rtc.c
  • HAL_RTC_MSPDEINIT_CB_ID : stm32wbxx_hal_rtc.h
  • HAL_RTC_MspInit() : stm32wbxx_hal_rtc.c
  • HAL_RTC_MSPINIT_CB_ID : stm32wbxx_hal_rtc.h
  • HAL_RTC_PollForAlarmAEvent() : stm32wbxx_hal_rtc.c
  • HAL_RTC_RegisterCallback() : stm32wbxx_hal_rtc.c
  • HAL_RTC_SetAlarm() : stm32wbxx_hal_rtc.c
  • HAL_RTC_SetAlarm_IT() : stm32wbxx_hal_rtc.c
  • HAL_RTC_SetDate() : stm32wbxx_hal_rtc.c
  • HAL_RTC_SetTime() : stm32wbxx_hal_rtc.c
  • HAL_RTC_STATE_BUSY : stm32wbxx_hal_rtc.h
  • HAL_RTC_STATE_ERROR : stm32wbxx_hal_rtc.h
  • HAL_RTC_STATE_READY : stm32wbxx_hal_rtc.h
  • HAL_RTC_STATE_RESET : stm32wbxx_hal_rtc.h
  • HAL_RTC_STATE_TIMEOUT : stm32wbxx_hal_rtc.h
  • HAL_RTC_TAMPER1_EVENT_CB_ID : stm32wbxx_hal_rtc.h
  • HAL_RTC_TAMPER2_EVENT_CB_ID : stm32wbxx_hal_rtc.h
  • HAL_RTC_TAMPER3_EVENT_CB_ID : stm32wbxx_hal_rtc.h
  • HAL_RTC_TIMESTAMP_EVENT_CB_ID : stm32wbxx_hal_rtc.h
  • HAL_RTC_UnRegisterCallback() : stm32wbxx_hal_rtc.c
  • HAL_RTC_WaitForSynchro() : stm32wbxx_hal_rtc.c
  • HAL_RTC_WAKEUPTIMER_EVENT_CB_ID : stm32wbxx_hal_rtc.h
  • HAL_RTCEx_AlarmBEventCallback() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_BKUPRead() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_BKUPWrite() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateCalibrationOutPut() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateInternalTimeStamp() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateRefClock() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateTamper() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateTimeStamp() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateWakeUpTimer() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_DisableBypassShadow() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_EnableBypassShadow() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_GetTimeStamp() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_GetWakeUpTimer() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_PollForAlarmBEvent() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamper1Event() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamper2Event() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamper3Event() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTimeStampEvent() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_PollForWakeUpTimerEvent() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_SetCalibrationOutPut() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_SetInternalTimeStamp() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_SetRefClock() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_SetSmoothCalib() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_SetSynchroShift() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_SetTamper() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_SetTamper_IT() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_SetTimeStamp() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_SetTimeStamp_IT() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_SetWakeUpTimer() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_SetWakeUpTimer_IT() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper1EventCallback() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper2EventCallback() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper3EventCallback() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_TamperTimeStampIRQHandler() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_TimeStampEventCallback() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_WakeUpTimerEventCallback() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_WakeUpTimerIRQHandler() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCStateTypeDef : stm32wbxx_hal_rtc.h
  • HAL_SAI_Abort() : stm32wbxx_hal_sai.c
  • HAL_SAI_CallbackIDTypeDef : stm32wbxx_hal_sai.h
  • HAL_SAI_DeInit() : stm32wbxx_hal_sai.c
  • HAL_SAI_DisableRxMuteMode() : stm32wbxx_hal_sai.c
  • HAL_SAI_DisableTxMuteMode() : stm32wbxx_hal_sai.c
  • HAL_SAI_DMAPause() : stm32wbxx_hal_sai.c
  • HAL_SAI_DMAResume() : stm32wbxx_hal_sai.c
  • HAL_SAI_DMAStop() : stm32wbxx_hal_sai.c
  • HAL_SAI_EnableRxMuteMode() : stm32wbxx_hal_sai.c
  • HAL_SAI_EnableTxMuteMode() : stm32wbxx_hal_sai.c
  • HAL_SAI_ERROR_AFSDET : stm32wbxx_hal_sai.h
  • HAL_SAI_ERROR_CB_ID : stm32wbxx_hal_sai.h
  • HAL_SAI_ERROR_CNREADY : stm32wbxx_hal_sai.h
  • HAL_SAI_ERROR_DMA : stm32wbxx_hal_sai.h
  • HAL_SAI_ERROR_INVALID_CALLBACK : stm32wbxx_hal_sai.h
  • HAL_SAI_ERROR_LFSDET : stm32wbxx_hal_sai.h
  • HAL_SAI_ERROR_NONE : stm32wbxx_hal_sai.h
  • HAL_SAI_ERROR_OVR : stm32wbxx_hal_sai.h
  • HAL_SAI_ERROR_TIMEOUT : stm32wbxx_hal_sai.h
  • HAL_SAI_ERROR_UDR : stm32wbxx_hal_sai.h
  • HAL_SAI_ERROR_WCKCFG : stm32wbxx_hal_sai.h
  • HAL_SAI_ErrorCallback() : stm32wbxx_hal_sai.c
  • HAL_SAI_GetError() : stm32wbxx_hal_sai.c
  • HAL_SAI_GetState() : stm32wbxx_hal_sai.c
  • HAL_SAI_Init() : stm32wbxx_hal_sai.c
  • HAL_SAI_InitProtocol() : stm32wbxx_hal_sai.c
  • HAL_SAI_IRQHandler() : stm32wbxx_hal_sai.c
  • HAL_SAI_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_SAI_MspDeInit() : stm32wbxx_hal_sai.c
  • HAL_SAI_MSPDEINIT_CB_ID : stm32wbxx_hal_sai.h
  • HAL_SAI_MspInit() : stm32wbxx_hal_sai.c
  • HAL_SAI_MSPINIT_CB_ID : stm32wbxx_hal_sai.h
  • HAL_SAI_Receive() : stm32wbxx_hal_sai.c
  • HAL_SAI_Receive_DMA() : stm32wbxx_hal_sai.c
  • HAL_SAI_Receive_IT() : stm32wbxx_hal_sai.c
  • HAL_SAI_RegisterCallback() : stm32wbxx_hal_sai.c
  • HAL_SAI_RX_COMPLETE_CB_ID : stm32wbxx_hal_sai.h
  • HAL_SAI_RX_HALFCOMPLETE_CB_ID : stm32wbxx_hal_sai.h
  • HAL_SAI_RxCpltCallback() : stm32wbxx_hal_sai.c
  • HAL_SAI_RxHalfCpltCallback() : stm32wbxx_hal_sai.c
  • HAL_SAI_STATE_BUSY : stm32wbxx_hal_sai.h
  • HAL_SAI_STATE_BUSY_RX : stm32wbxx_hal_sai.h
  • HAL_SAI_STATE_BUSY_TX : stm32wbxx_hal_sai.h
  • HAL_SAI_STATE_READY : stm32wbxx_hal_sai.h
  • HAL_SAI_STATE_RESET : stm32wbxx_hal_sai.h
  • HAL_SAI_StateTypeDef : stm32wbxx_hal_sai.h
  • HAL_SAI_Transmit() : stm32wbxx_hal_sai.c
  • HAL_SAI_Transmit_DMA() : stm32wbxx_hal_sai.c
  • HAL_SAI_Transmit_IT() : stm32wbxx_hal_sai.c
  • HAL_SAI_TX_COMPLETE_CB_ID : stm32wbxx_hal_sai.h
  • HAL_SAI_TX_HALFCOMPLETE_CB_ID : stm32wbxx_hal_sai.h
  • HAL_SAI_TxCpltCallback() : stm32wbxx_hal_sai.c
  • HAL_SAI_TxHalfCpltCallback() : stm32wbxx_hal_sai.c
  • HAL_SAI_UnRegisterCallback() : stm32wbxx_hal_sai.c
  • HAL_SAIEx_ConfigPdmMicDelay() : stm32wbxx_hal_sai_ex.c
  • HAL_SetTickFreq() : stm32wbxx_hal.c
  • HAL_SMARTCARD_Abort() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_ABORT_COMPLETE_CB_ID : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_Abort_IT() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_AbortCpltCallback() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceive() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceive_IT() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceiveCpltCallback() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmit() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmit_IT() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmitCpltCallback() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_CallbackIDTypeDef : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_DeInit() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_ERROR_CB_ID : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_DMA : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_FE : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_INVALID_CALLBACK : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NE : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NONE : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_ORE : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_PE : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_RTO : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_ErrorCallback() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_GetError() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_GetState() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_Init() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_IRQHandler() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_SMARTCARD_MspDeInit() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_MSPDEINIT_CB_ID : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_MspInit() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_MSPINIT_CB_ID : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_Receive() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_DMA() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_IT() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_RegisterCallback() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_RX_COMPLETE_CB_ID : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_RX_FIFO_FULL_CB_ID : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_RxCpltCallback() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_STATE_BUSY : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_RX : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX_RX : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_ERROR : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_READY : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_RESET : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_TIMEOUT : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_StateTypeDef : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_Transmit() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_DMA() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_IT() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_TX_COMPLETE_CB_ID : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_TxCpltCallback() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_UnRegisterCallback() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARDEx_BlockLength_Config() : stm32wbxx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_DisableFifoMode() : stm32wbxx_hal_smartcard_ex.c , stm32wbxx_hal_smartcard_ex.h
  • HAL_SMARTCARDEx_DisableReceiverTimeOut() : stm32wbxx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_EnableFifoMode() : stm32wbxx_hal_smartcard_ex.h , stm32wbxx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_EnableReceiverTimeOut() : stm32wbxx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_RxFifoFullCallback() : stm32wbxx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_SetRxFifoThreshold() : stm32wbxx_hal_smartcard_ex.h , stm32wbxx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_SetTxFifoThreshold() : stm32wbxx_hal_smartcard_ex.c , stm32wbxx_hal_smartcard_ex.h
  • HAL_SMARTCARDEx_TimeOut_Config() : stm32wbxx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_TxFifoEmptyCallback() : stm32wbxx_hal_smartcard_ex.c
  • HAL_SMBUS_AddrCallback() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_CallbackIDTypeDef : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_ConfigAnalogFilter() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_ConfigDigitalFilter() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_DeInit() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_DisableAlert_IT() : stm32wbxx_hal_smbus.c , stm32wbxx_hal_smbus.h
  • HAL_SMBUS_DisableListen_IT() : stm32wbxx_hal_smbus.c , stm32wbxx_hal_smbus.h
  • HAL_SMBUS_EnableAlert_IT() : stm32wbxx_hal_smbus.c , stm32wbxx_hal_smbus.h
  • HAL_SMBUS_EnableListen_IT() : stm32wbxx_hal_smbus.c , stm32wbxx_hal_smbus.h
  • HAL_SMBUS_ER_IRQHandler() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_ERROR_ACKF : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_ERROR_ALERT : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_ERROR_ARLO : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_ERROR_BERR : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_ERROR_BUSTIMEOUT : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_ERROR_CB_ID : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_ERROR_HALTIMEOUT : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_ERROR_INVALID_CALLBACK : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_ERROR_INVALID_PARAM : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_ERROR_NONE : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_ERROR_OVR : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_ERROR_PECERR : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_ErrorCallback() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_EV_IRQHandler() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_GetError() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_GetState() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_Init() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_IsDeviceReady() : stm32wbxx_hal_smbus.c , stm32wbxx_hal_smbus.h
  • HAL_SMBUS_LISTEN_COMPLETE_CB_ID : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_ListenCpltCallback() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_Master_Abort_IT() : stm32wbxx_hal_smbus.h , stm32wbxx_hal_smbus.c
  • HAL_SMBUS_Master_Receive_IT() : stm32wbxx_hal_smbus.c , stm32wbxx_hal_smbus.h
  • HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_Master_Transmit_IT() : stm32wbxx_hal_smbus.c , stm32wbxx_hal_smbus.h
  • HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_MasterRxCpltCallback() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_MasterTxCpltCallback() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_SMBUS_MspDeInit() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_MSPDEINIT_CB_ID : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_MspInit() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_MSPINIT_CB_ID : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_RegisterAddrCallback() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_RegisterCallback() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_Slave_Receive_IT() : stm32wbxx_hal_smbus.c , stm32wbxx_hal_smbus.h
  • HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_Slave_Transmit_IT() : stm32wbxx_hal_smbus.h , stm32wbxx_hal_smbus.c
  • HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_SlaveRxCpltCallback() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_SlaveTxCpltCallback() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_STATE_BUSY : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_STATE_ERROR : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_STATE_LISTEN : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_STATE_MASTER_BUSY_RX : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_STATE_MASTER_BUSY_TX : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_STATE_READY : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_STATE_RESET : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_STATE_SLAVE_BUSY_RX : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_STATE_SLAVE_BUSY_TX : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_STATE_TIMEOUT : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_UnRegisterAddrCallback() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_UnRegisterCallback() : stm32wbxx_hal_smbus.c
  • HAL_SPI_Abort() : stm32wbxx_hal_spi.c
  • HAL_SPI_ABORT_CB_ID : stm32wbxx_hal_spi.h
  • HAL_SPI_Abort_IT() : stm32wbxx_hal_spi.c
  • HAL_SPI_AbortCpltCallback() : stm32wbxx_hal_spi.c
  • HAL_SPI_CallbackIDTypeDef : stm32wbxx_hal_spi.h
  • HAL_SPI_DeInit() : stm32wbxx_hal_spi.c
  • HAL_SPI_DMAPause() : stm32wbxx_hal_spi.c
  • HAL_SPI_DMAResume() : stm32wbxx_hal_spi.c
  • HAL_SPI_DMAStop() : stm32wbxx_hal_spi.c
  • HAL_SPI_ERROR_ABORT : stm32wbxx_hal_spi.h
  • HAL_SPI_ERROR_CB_ID : stm32wbxx_hal_spi.h
  • HAL_SPI_ERROR_CRC : stm32wbxx_hal_spi.h
  • HAL_SPI_ERROR_DMA : stm32wbxx_hal_spi.h
  • HAL_SPI_ERROR_FLAG : stm32wbxx_hal_spi.h
  • HAL_SPI_ERROR_FRE : stm32wbxx_hal_spi.h
  • HAL_SPI_ERROR_INVALID_CALLBACK : stm32wbxx_hal_spi.h
  • HAL_SPI_ERROR_MODF : stm32wbxx_hal_spi.h
  • HAL_SPI_ERROR_NONE : stm32wbxx_hal_spi.h
  • HAL_SPI_ERROR_OVR : stm32wbxx_hal_spi.h
  • HAL_SPI_ErrorCallback() : stm32wbxx_hal_spi.c
  • HAL_SPI_GetError() : stm32wbxx_hal_spi.c
  • HAL_SPI_GetState() : stm32wbxx_hal_spi.c
  • HAL_SPI_Init() : stm32wbxx_hal_spi.c
  • HAL_SPI_IRQHandler() : stm32wbxx_hal_spi.c
  • HAL_SPI_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_SPI_MspDeInit() : stm32wbxx_hal_spi.c
  • HAL_SPI_MSPDEINIT_CB_ID : stm32wbxx_hal_spi.h
  • HAL_SPI_MspInit() : stm32wbxx_hal_spi.c
  • HAL_SPI_MSPINIT_CB_ID : stm32wbxx_hal_spi.h
  • HAL_SPI_Receive() : stm32wbxx_hal_spi.c
  • HAL_SPI_Receive_DMA() : stm32wbxx_hal_spi.c
  • HAL_SPI_Receive_IT() : stm32wbxx_hal_spi.c
  • HAL_SPI_RegisterCallback() : stm32wbxx_hal_spi.c
  • HAL_SPI_RX_COMPLETE_CB_ID : stm32wbxx_hal_spi.h
  • HAL_SPI_RX_HALF_COMPLETE_CB_ID : stm32wbxx_hal_spi.h
  • HAL_SPI_RxCpltCallback() : stm32wbxx_hal_spi.c
  • HAL_SPI_RxHalfCpltCallback() : stm32wbxx_hal_spi.c
  • HAL_SPI_STATE_ABORT : stm32wbxx_hal_spi.h
  • HAL_SPI_STATE_BUSY : stm32wbxx_hal_spi.h
  • HAL_SPI_STATE_BUSY_RX : stm32wbxx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX : stm32wbxx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX_RX : stm32wbxx_hal_spi.h
  • HAL_SPI_STATE_ERROR : stm32wbxx_hal_spi.h
  • HAL_SPI_STATE_READY : stm32wbxx_hal_spi.h
  • HAL_SPI_STATE_RESET : stm32wbxx_hal_spi.h
  • HAL_SPI_StateTypeDef : stm32wbxx_hal_spi.h
  • HAL_SPI_Transmit() : stm32wbxx_hal_spi.c
  • HAL_SPI_Transmit_DMA() : stm32wbxx_hal_spi.c
  • HAL_SPI_Transmit_IT() : stm32wbxx_hal_spi.c
  • HAL_SPI_TransmitReceive() : stm32wbxx_hal_spi.c
  • HAL_SPI_TransmitReceive_DMA() : stm32wbxx_hal_spi.c
  • HAL_SPI_TransmitReceive_IT() : stm32wbxx_hal_spi.c
  • HAL_SPI_TX_COMPLETE_CB_ID : stm32wbxx_hal_spi.h
  • HAL_SPI_TX_HALF_COMPLETE_CB_ID : stm32wbxx_hal_spi.h
  • HAL_SPI_TX_RX_COMPLETE_CB_ID : stm32wbxx_hal_spi.h
  • HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : stm32wbxx_hal_spi.h
  • HAL_SPI_TxCpltCallback() : stm32wbxx_hal_spi.c
  • HAL_SPI_TxHalfCpltCallback() : stm32wbxx_hal_spi.c
  • HAL_SPI_TxRxCpltCallback() : stm32wbxx_hal_spi.c
  • HAL_SPI_TxRxHalfCpltCallback() : stm32wbxx_hal_spi.c
  • HAL_SPI_UnRegisterCallback() : stm32wbxx_hal_spi.c
  • HAL_SPIEx_FlushRxFifo() : stm32wbxx_hal_spi_ex.c
  • HAL_SuspendTick() : stm32wbxx_hal.c
  • HAL_SYSCFG_DisableIOBooster() : stm32wbxx_hal.c
  • HAL_SYSCFG_DisableIOVdd() : stm32wbxx_hal.c
  • HAL_SYSCFG_DisableSecurityAccess() : stm32wbxx_hal.c
  • HAL_SYSCFG_DisableSRAMFetch() : stm32wbxx_hal.c
  • HAL_SYSCFG_DisableVREFBUF() : stm32wbxx_hal.c
  • HAL_SYSCFG_EnableIOBooster() : stm32wbxx_hal.c
  • HAL_SYSCFG_EnableIOVdd() : stm32wbxx_hal.c
  • HAL_SYSCFG_EnableSecurityAccess() : stm32wbxx_hal.c
  • HAL_SYSCFG_EnableVREFBUF() : stm32wbxx_hal.c
  • HAL_SYSCFG_IsEnabledSecurityAccess() : stm32wbxx_hal.c
  • HAL_SYSCFG_IsEnabledSRAMFetch() : stm32wbxx_hal.c
  • HAL_SYSCFG_SECURE_ACCESS_AES1 : stm32wbxx_hal.h
  • HAL_SYSCFG_SECURE_ACCESS_AES2 : stm32wbxx_hal.h
  • HAL_SYSCFG_SECURE_ACCESS_PKA : stm32wbxx_hal.h
  • HAL_SYSCFG_SECURE_ACCESS_RNG : stm32wbxx_hal.h
  • HAL_SYSCFG_SRAM2Erase() : stm32wbxx_hal.c
  • HAL_SYSCFG_VREFBUF_HighImpedanceConfig() : stm32wbxx_hal.c
  • HAL_SYSCFG_VREFBUF_TrimmingConfig() : stm32wbxx_hal.c
  • HAL_SYSCFG_VREFBUF_VoltageScalingConfig() : stm32wbxx_hal.c
  • HAL_SYSTICK_Callback() : stm32wbxx_hal_cortex.c
  • HAL_SYSTICK_CLKSourceConfig() : stm32wbxx_hal_cortex.c
  • HAL_SYSTICK_Config() : stm32wbxx_hal_cortex.c
  • HAL_SYSTICK_IRQHandler() : stm32wbxx_hal_cortex.c
  • HAL_TICK_FREQ_100HZ : stm32wbxx_hal.h
  • HAL_TICK_FREQ_10HZ : stm32wbxx_hal.h
  • HAL_TICK_FREQ_1KHZ : stm32wbxx_hal.h
  • HAL_TICK_FREQ_DEFAULT : stm32wbxx_hal.h
  • HAL_TIM_ACTIVE_CHANNEL_1 : stm32wbxx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_2 : stm32wbxx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_3 : stm32wbxx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_4 : stm32wbxx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_5 : stm32wbxx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_6 : stm32wbxx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_CLEARED : stm32wbxx_hal_tim.h
  • HAL_TIM_ActiveChannel : stm32wbxx_hal_tim.h
  • HAL_TIM_Base_DeInit() : stm32wbxx_hal_tim.c
  • HAL_TIM_Base_GetState() : stm32wbxx_hal_tim.c
  • HAL_TIM_Base_Init() : stm32wbxx_hal_tim.c
  • HAL_TIM_Base_MspDeInit() : stm32wbxx_hal_tim.c
  • HAL_TIM_BASE_MSPDEINIT_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_Base_MspInit() : stm32wbxx_hal_tim.c
  • HAL_TIM_BASE_MSPINIT_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_Base_Start() : stm32wbxx_hal_tim.c
  • HAL_TIM_Base_Start_DMA() : stm32wbxx_hal_tim.c
  • HAL_TIM_Base_Start_IT() : stm32wbxx_hal_tim.c
  • HAL_TIM_Base_Stop() : stm32wbxx_hal_tim.c
  • HAL_TIM_Base_Stop_DMA() : stm32wbxx_hal_tim.c
  • HAL_TIM_Base_Stop_IT() : stm32wbxx_hal_tim.c
  • HAL_TIM_BREAK2_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_BREAK_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_CallbackIDTypeDef : stm32wbxx_hal_tim.h
  • HAL_TIM_COMMUTATION_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_COMMUTATION_HALF_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_ConfigClockSource() : stm32wbxx_hal_tim.c
  • HAL_TIM_ConfigOCrefClear() : stm32wbxx_hal_tim.c
  • HAL_TIM_ConfigTI1Input() : stm32wbxx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStart() : stm32wbxx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStop() : stm32wbxx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStart() : stm32wbxx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStop() : stm32wbxx_hal_tim.c
  • HAL_TIM_Encoder_DeInit() : stm32wbxx_hal_tim.c
  • HAL_TIM_Encoder_GetState() : stm32wbxx_hal_tim.c
  • HAL_TIM_Encoder_Init() : stm32wbxx_hal_tim.c
  • HAL_TIM_Encoder_MspDeInit() : stm32wbxx_hal_tim.c
  • HAL_TIM_ENCODER_MSPDEINIT_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_Encoder_MspInit() : stm32wbxx_hal_tim.c
  • HAL_TIM_ENCODER_MSPINIT_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_Encoder_Start() : stm32wbxx_hal_tim.c
  • HAL_TIM_Encoder_Start_DMA() : stm32wbxx_hal_tim.c
  • HAL_TIM_Encoder_Start_IT() : stm32wbxx_hal_tim.c
  • HAL_TIM_Encoder_Stop() : stm32wbxx_hal_tim.c
  • HAL_TIM_Encoder_Stop_DMA() : stm32wbxx_hal_tim.c
  • HAL_TIM_Encoder_Stop_IT() : stm32wbxx_hal_tim.c
  • HAL_TIM_ERROR_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_ErrorCallback() : stm32wbxx_hal_tim.c
  • HAL_TIM_GenerateEvent() : stm32wbxx_hal_tim.c
  • HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_IC_CAPTURE_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_IC_CAPTURE_HALF_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_IC_CaptureCallback() : stm32wbxx_hal_tim.c
  • HAL_TIM_IC_CaptureHalfCpltCallback() : stm32wbxx_hal_tim.c
  • HAL_TIM_IC_ConfigChannel() : stm32wbxx_hal_tim.c
  • HAL_TIM_IC_DeInit() : stm32wbxx_hal_tim.c
  • HAL_TIM_IC_GetState() : stm32wbxx_hal_tim.c
  • HAL_TIM_IC_Init() : stm32wbxx_hal_tim.c
  • HAL_TIM_IC_MspDeInit() : stm32wbxx_hal_tim.c
  • HAL_TIM_IC_MSPDEINIT_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_IC_MspInit() : stm32wbxx_hal_tim.c
  • HAL_TIM_IC_MSPINIT_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_IC_Start() : stm32wbxx_hal_tim.c
  • HAL_TIM_IC_Start_DMA() : stm32wbxx_hal_tim.c
  • HAL_TIM_IC_Start_IT() : stm32wbxx_hal_tim.c
  • HAL_TIM_IC_Stop() : stm32wbxx_hal_tim.c
  • HAL_TIM_IC_Stop_DMA() : stm32wbxx_hal_tim.c
  • HAL_TIM_IC_Stop_IT() : stm32wbxx_hal_tim.c
  • HAL_TIM_IRQHandler() : stm32wbxx_hal_tim.c
  • HAL_TIM_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_TIM_OC_ConfigChannel() : stm32wbxx_hal_tim.c
  • HAL_TIM_OC_DeInit() : stm32wbxx_hal_tim.c
  • HAL_TIM_OC_DELAY_ELAPSED_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_OC_DelayElapsedCallback() : stm32wbxx_hal_tim.c
  • HAL_TIM_OC_GetState() : stm32wbxx_hal_tim.c
  • HAL_TIM_OC_Init() : stm32wbxx_hal_tim.c
  • HAL_TIM_OC_MspDeInit() : stm32wbxx_hal_tim.c
  • HAL_TIM_OC_MSPDEINIT_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_OC_MspInit() : stm32wbxx_hal_tim.c
  • HAL_TIM_OC_MSPINIT_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_OC_Start() : stm32wbxx_hal_tim.c
  • HAL_TIM_OC_Start_DMA() : stm32wbxx_hal_tim.c
  • HAL_TIM_OC_Start_IT() : stm32wbxx_hal_tim.c
  • HAL_TIM_OC_Stop() : stm32wbxx_hal_tim.c
  • HAL_TIM_OC_Stop_DMA() : stm32wbxx_hal_tim.c
  • HAL_TIM_OC_Stop_IT() : stm32wbxx_hal_tim.c
  • HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_OnePulse_ConfigChannel() : stm32wbxx_hal_tim.c
  • HAL_TIM_OnePulse_DeInit() : stm32wbxx_hal_tim.c
  • HAL_TIM_OnePulse_GetState() : stm32wbxx_hal_tim.c
  • HAL_TIM_OnePulse_Init() : stm32wbxx_hal_tim.c
  • HAL_TIM_OnePulse_MspDeInit() : stm32wbxx_hal_tim.c
  • HAL_TIM_OnePulse_MspInit() : stm32wbxx_hal_tim.c
  • HAL_TIM_OnePulse_Start() : stm32wbxx_hal_tim.c
  • HAL_TIM_OnePulse_Start_IT() : stm32wbxx_hal_tim.c
  • HAL_TIM_OnePulse_Stop() : stm32wbxx_hal_tim.c
  • HAL_TIM_OnePulse_Stop_IT() : stm32wbxx_hal_tim.c
  • HAL_TIM_PERIOD_ELAPSED_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_PeriodElapsedCallback() : stm32wbxx_hal_tim.c
  • HAL_TIM_PeriodElapsedHalfCpltCallback() : stm32wbxx_hal_tim.c
  • HAL_TIM_PWM_ConfigChannel() : stm32wbxx_hal_tim.c
  • HAL_TIM_PWM_DeInit() : stm32wbxx_hal_tim.c
  • HAL_TIM_PWM_GetState() : stm32wbxx_hal_tim.c
  • HAL_TIM_PWM_Init() : stm32wbxx_hal_tim.c
  • HAL_TIM_PWM_MspDeInit() : stm32wbxx_hal_tim.c
  • HAL_TIM_PWM_MSPDEINIT_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_PWM_MspInit() : stm32wbxx_hal_tim.c
  • HAL_TIM_PWM_MSPINIT_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_PWM_PULSE_FINISHED_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_PWM_PulseFinishedCallback() : stm32wbxx_hal_tim.c
  • HAL_TIM_PWM_PulseFinishedHalfCpltCallback() : stm32wbxx_hal_tim.c
  • HAL_TIM_PWM_Start() : stm32wbxx_hal_tim.c
  • HAL_TIM_PWM_Start_DMA() : stm32wbxx_hal_tim.c
  • HAL_TIM_PWM_Start_IT() : stm32wbxx_hal_tim.c
  • HAL_TIM_PWM_Stop() : stm32wbxx_hal_tim.c
  • HAL_TIM_PWM_Stop_DMA() : stm32wbxx_hal_tim.c
  • HAL_TIM_PWM_Stop_IT() : stm32wbxx_hal_tim.c
  • HAL_TIM_ReadCapturedValue() : stm32wbxx_hal_tim.c
  • HAL_TIM_RegisterCallback() : stm32wbxx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchro() : stm32wbxx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchro_IT() : stm32wbxx_hal_tim.c
  • HAL_TIM_STATE_BUSY : stm32wbxx_hal_tim.h
  • HAL_TIM_STATE_ERROR : stm32wbxx_hal_tim.h
  • HAL_TIM_STATE_READY : stm32wbxx_hal_tim.h
  • HAL_TIM_STATE_RESET : stm32wbxx_hal_tim.h
  • HAL_TIM_STATE_TIMEOUT : stm32wbxx_hal_tim.h
  • HAL_TIM_StateTypeDef : stm32wbxx_hal_tim.h
  • HAL_TIM_TRIGGER_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_TRIGGER_HALF_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_TriggerCallback() : stm32wbxx_hal_tim.c
  • HAL_TIM_TriggerHalfCpltCallback() : stm32wbxx_hal_tim.c
  • HAL_TIM_UnRegisterCallback() : stm32wbxx_hal_tim.c
  • HAL_TIMEOUT_ADDR : stm32wbxx_hal_smbus.c
  • HAL_TIMEOUT_BUSY : stm32wbxx_hal_smbus.c
  • HAL_TIMEOUT_DIR : stm32wbxx_hal_smbus.c
  • HAL_TIMEOUT_RXNE : stm32wbxx_hal_smbus.c
  • HAL_TIMEOUT_STOPF : stm32wbxx_hal_smbus.c
  • HAL_TIMEOUT_TC : stm32wbxx_hal_smbus.c
  • HAL_TIMEOUT_TCR : stm32wbxx_hal_smbus.c
  • HAL_TIMEOUT_TXIS : stm32wbxx_hal_smbus.c
  • HAL_TIMEx_Break2Callback() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_BreakCallback() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_CommutCallback() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_CommutHalfCpltCallback() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_ConfigBreakDeadTime() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_ConfigBreakInput() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutEvent() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutEvent_DMA() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutEvent_IT() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_GroupChannel5() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_DeInit() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_GetState() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Init() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspDeInit() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspInit() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_DMA() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_IT() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_DMA() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_IT() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_MasterConfigSynchronization() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_DMA() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_IT() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_DMA() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_IT() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start_IT() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop_IT() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_DMA() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_IT() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_DMA() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_IT() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_RemapConfig() : stm32wbxx_hal_tim_ex.c
  • HAL_TSC_CallbackIDTypeDef : stm32wbxx_hal_tsc.h
  • HAL_TSC_CONV_COMPLETE_CB_ID : stm32wbxx_hal_tsc.h
  • HAL_TSC_ConvCpltCallback() : stm32wbxx_hal_tsc.c
  • HAL_TSC_DeInit() : stm32wbxx_hal_tsc.c
  • HAL_TSC_ERROR_CB_ID : stm32wbxx_hal_tsc.h
  • HAL_TSC_ERROR_INVALID_CALLBACK : stm32wbxx_hal_tsc.h
  • HAL_TSC_ERROR_NONE : stm32wbxx_hal_tsc.h
  • HAL_TSC_ErrorCallback() : stm32wbxx_hal_tsc.c
  • HAL_TSC_GetState() : stm32wbxx_hal_tsc.c
  • HAL_TSC_GroupGetStatus() : stm32wbxx_hal_tsc.c
  • HAL_TSC_GroupGetValue() : stm32wbxx_hal_tsc.c
  • HAL_TSC_Init() : stm32wbxx_hal_tsc.c
  • HAL_TSC_IOConfig() : stm32wbxx_hal_tsc.c
  • HAL_TSC_IODischarge() : stm32wbxx_hal_tsc.c
  • HAL_TSC_IRQHandler() : stm32wbxx_hal_tsc.c
  • HAL_TSC_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_TSC_MspDeInit() : stm32wbxx_hal_tsc.c
  • HAL_TSC_MSPDEINIT_CB_ID : stm32wbxx_hal_tsc.h
  • HAL_TSC_MspInit() : stm32wbxx_hal_tsc.c
  • HAL_TSC_MSPINIT_CB_ID : stm32wbxx_hal_tsc.h
  • HAL_TSC_PollForAcquisition() : stm32wbxx_hal_tsc.c
  • HAL_TSC_RegisterCallback() : stm32wbxx_hal_tsc.c
  • HAL_TSC_Start() : stm32wbxx_hal_tsc.c
  • HAL_TSC_Start_IT() : stm32wbxx_hal_tsc.c
  • HAL_TSC_STATE_BUSY : stm32wbxx_hal_tsc.h
  • HAL_TSC_STATE_ERROR : stm32wbxx_hal_tsc.h
  • HAL_TSC_STATE_READY : stm32wbxx_hal_tsc.h
  • HAL_TSC_STATE_RESET : stm32wbxx_hal_tsc.h
  • HAL_TSC_StateTypeDef : stm32wbxx_hal_tsc.h
  • HAL_TSC_Stop() : stm32wbxx_hal_tsc.c
  • HAL_TSC_Stop_IT() : stm32wbxx_hal_tsc.c
  • HAL_TSC_UnRegisterCallback() : stm32wbxx_hal_tsc.c
  • HAL_UART_Abort() : stm32wbxx_hal_uart.c
  • HAL_UART_ABORT_COMPLETE_CB_ID : stm32wbxx_hal_uart.h
  • HAL_UART_Abort_IT() : stm32wbxx_hal_uart.c
  • HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : stm32wbxx_hal_uart.h
  • HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : stm32wbxx_hal_uart.h
  • HAL_UART_AbortCpltCallback() : stm32wbxx_hal_uart.c
  • HAL_UART_AbortReceive() : stm32wbxx_hal_uart.c
  • HAL_UART_AbortReceive_IT() : stm32wbxx_hal_uart.c
  • HAL_UART_AbortReceiveCpltCallback() : stm32wbxx_hal_uart.c
  • HAL_UART_AbortTransmit() : stm32wbxx_hal_uart.c
  • HAL_UART_AbortTransmit_IT() : stm32wbxx_hal_uart.c
  • HAL_UART_AbortTransmitCpltCallback() : stm32wbxx_hal_uart.c
  • HAL_UART_CallbackIDTypeDef : stm32wbxx_hal_uart.h
  • HAL_UART_DeInit() : stm32wbxx_hal_uart.c
  • HAL_UART_DisableReceiverTimeout() : stm32wbxx_hal_uart.c
  • HAL_UART_DMAPause() : stm32wbxx_hal_uart.c
  • HAL_UART_DMAResume() : stm32wbxx_hal_uart.c
  • HAL_UART_DMAStop() : stm32wbxx_hal_uart.c
  • HAL_UART_EnableReceiverTimeout() : stm32wbxx_hal_uart.c
  • HAL_UART_ERROR_CB_ID : stm32wbxx_hal_uart.h
  • HAL_UART_ERROR_DMA : stm32wbxx_hal_uart.h
  • HAL_UART_ERROR_FE : stm32wbxx_hal_uart.h
  • HAL_UART_ERROR_INVALID_CALLBACK : stm32wbxx_hal_uart.h
  • HAL_UART_ERROR_NE : stm32wbxx_hal_uart.h
  • HAL_UART_ERROR_NONE : stm32wbxx_hal_uart.h
  • HAL_UART_ERROR_ORE : stm32wbxx_hal_uart.h
  • HAL_UART_ERROR_PE : stm32wbxx_hal_uart.h
  • HAL_UART_ERROR_RTO : stm32wbxx_hal_uart.h
  • HAL_UART_ErrorCallback() : stm32wbxx_hal_uart.c
  • HAL_UART_GetError() : stm32wbxx_hal_uart.c
  • HAL_UART_GetState() : stm32wbxx_hal_uart.c
  • HAL_UART_Init() : stm32wbxx_hal_uart.c
  • HAL_UART_IRQHandler() : stm32wbxx_hal_uart.c
  • HAL_UART_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_UART_MspDeInit() : stm32wbxx_hal_uart.c
  • HAL_UART_MSPDEINIT_CB_ID : stm32wbxx_hal_uart.h
  • HAL_UART_MspInit() : stm32wbxx_hal_uart.c
  • HAL_UART_MSPINIT_CB_ID : stm32wbxx_hal_uart.h
  • HAL_UART_Receive() : stm32wbxx_hal_uart.c
  • HAL_UART_Receive_DMA() : stm32wbxx_hal_uart.c
  • HAL_UART_Receive_IT() : stm32wbxx_hal_uart.c
  • HAL_UART_ReceiverTimeout_Config() : stm32wbxx_hal_uart.c
  • HAL_UART_RegisterCallback() : stm32wbxx_hal_uart.c
  • HAL_UART_RX_COMPLETE_CB_ID : stm32wbxx_hal_uart.h
  • HAL_UART_RX_FIFO_FULL_CB_ID : stm32wbxx_hal_uart.h
  • HAL_UART_RX_HALFCOMPLETE_CB_ID : stm32wbxx_hal_uart.h
  • HAL_UART_RxCpltCallback() : stm32wbxx_hal_uart.c
  • HAL_UART_RxHalfCpltCallback() : stm32wbxx_hal_uart.c
  • HAL_UART_STATE_BUSY : stm32wbxx_hal_uart.h
  • HAL_UART_STATE_BUSY_RX : stm32wbxx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX : stm32wbxx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX_RX : stm32wbxx_hal_uart.h
  • HAL_UART_STATE_ERROR : stm32wbxx_hal_uart.h
  • HAL_UART_STATE_READY : stm32wbxx_hal_uart.h
  • HAL_UART_STATE_RESET : stm32wbxx_hal_uart.h
  • HAL_UART_STATE_TIMEOUT : stm32wbxx_hal_uart.h
  • HAL_UART_StateTypeDef : stm32wbxx_hal_uart.h
  • HAL_UART_TIMEOUT_VALUE : stm32wbxx_hal_uart.h
  • HAL_UART_Transmit() : stm32wbxx_hal_uart.c
  • HAL_UART_Transmit_DMA() : stm32wbxx_hal_uart.c
  • HAL_UART_Transmit_IT() : stm32wbxx_hal_uart.c
  • HAL_UART_TX_COMPLETE_CB_ID : stm32wbxx_hal_uart.h
  • HAL_UART_TX_FIFO_EMPTY_CB_ID : stm32wbxx_hal_uart.h
  • HAL_UART_TX_HALFCOMPLETE_CB_ID : stm32wbxx_hal_uart.h
  • HAL_UART_TxCpltCallback() : stm32wbxx_hal_uart.c
  • HAL_UART_TxHalfCpltCallback() : stm32wbxx_hal_uart.c
  • HAL_UART_UnRegisterCallback() : stm32wbxx_hal_uart.c
  • HAL_UART_WAKEUP_CB_ID : stm32wbxx_hal_uart.h
  • HAL_UARTEx_DisableFifoMode() : stm32wbxx_hal_uart_ex.c
  • HAL_UARTEx_DisableStopMode() : stm32wbxx_hal_uart_ex.c
  • HAL_UARTEx_EnableFifoMode() : stm32wbxx_hal_uart_ex.c
  • HAL_UARTEx_EnableStopMode() : stm32wbxx_hal_uart_ex.c
  • HAL_UARTEx_RxFifoFullCallback() : stm32wbxx_hal_uart_ex.c
  • HAL_UARTEx_SetRxFifoThreshold() : stm32wbxx_hal_uart_ex.c
  • HAL_UARTEx_SetTxFifoThreshold() : stm32wbxx_hal_uart_ex.c
  • HAL_UARTEx_StopModeWakeUpSourceConfig() : stm32wbxx_hal_uart_ex.c
  • HAL_UARTEx_TxFifoEmptyCallback() : stm32wbxx_hal_uart_ex.c
  • HAL_UARTEx_WakeupCallback() : stm32wbxx_hal_uart_ex.c
  • HAL_USART_Abort() : stm32wbxx_hal_usart.c
  • HAL_USART_ABORT_COMPLETE_CB_ID : stm32wbxx_hal_usart.h
  • HAL_USART_Abort_IT() : stm32wbxx_hal_usart.c
  • HAL_USART_AbortCpltCallback() : stm32wbxx_hal_usart.c
  • HAL_USART_CallbackIDTypeDef : stm32wbxx_hal_usart.h
  • HAL_USART_DeInit() : stm32wbxx_hal_usart.c
  • HAL_USART_DMAPause() : stm32wbxx_hal_usart.c
  • HAL_USART_DMAResume() : stm32wbxx_hal_usart.c
  • HAL_USART_DMAStop() : stm32wbxx_hal_usart.c
  • HAL_USART_ERROR_CB_ID : stm32wbxx_hal_usart.h
  • HAL_USART_ERROR_DMA : stm32wbxx_hal_usart.h
  • HAL_USART_ERROR_FE : stm32wbxx_hal_usart.h
  • HAL_USART_ERROR_INVALID_CALLBACK : stm32wbxx_hal_usart.h
  • HAL_USART_ERROR_NE : stm32wbxx_hal_usart.h
  • HAL_USART_ERROR_NONE : stm32wbxx_hal_usart.h
  • HAL_USART_ERROR_ORE : stm32wbxx_hal_usart.h
  • HAL_USART_ERROR_PE : stm32wbxx_hal_usart.h
  • HAL_USART_ERROR_UDR : stm32wbxx_hal_usart.h
  • HAL_USART_ErrorCallback() : stm32wbxx_hal_usart.c
  • HAL_USART_GetError() : stm32wbxx_hal_usart.c
  • HAL_USART_GetState() : stm32wbxx_hal_usart.c
  • HAL_USART_Init() : stm32wbxx_hal_usart.c
  • HAL_USART_IRQHandler() : stm32wbxx_hal_usart.c
  • HAL_USART_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_USART_MspDeInit() : stm32wbxx_hal_usart.c
  • HAL_USART_MSPDEINIT_CB_ID : stm32wbxx_hal_usart.h
  • HAL_USART_MspInit() : stm32wbxx_hal_usart.c
  • HAL_USART_MSPINIT_CB_ID : stm32wbxx_hal_usart.h
  • HAL_USART_Receive() : stm32wbxx_hal_usart.c
  • HAL_USART_Receive_DMA() : stm32wbxx_hal_usart.c
  • HAL_USART_Receive_IT() : stm32wbxx_hal_usart.c
  • HAL_USART_RegisterCallback() : stm32wbxx_hal_usart.c
  • HAL_USART_RX_COMPLETE_CB_ID : stm32wbxx_hal_usart.h
  • HAL_USART_RX_FIFO_FULL_CB_ID : stm32wbxx_hal_usart.h
  • HAL_USART_RX_HALFCOMPLETE_CB_ID : stm32wbxx_hal_usart.h
  • HAL_USART_RxCpltCallback() : stm32wbxx_hal_usart.c
  • HAL_USART_RxHalfCpltCallback() : stm32wbxx_hal_usart.c
  • HAL_USART_STATE_BUSY : stm32wbxx_hal_usart.h
  • HAL_USART_STATE_BUSY_RX : stm32wbxx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX : stm32wbxx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX_RX : stm32wbxx_hal_usart.h
  • HAL_USART_STATE_ERROR : stm32wbxx_hal_usart.h
  • HAL_USART_STATE_READY : stm32wbxx_hal_usart.h
  • HAL_USART_STATE_RESET : stm32wbxx_hal_usart.h
  • HAL_USART_STATE_TIMEOUT : stm32wbxx_hal_usart.h
  • HAL_USART_StateTypeDef : stm32wbxx_hal_usart.h
  • HAL_USART_Transmit() : stm32wbxx_hal_usart.c
  • HAL_USART_Transmit_DMA() : stm32wbxx_hal_usart.c
  • HAL_USART_Transmit_IT() : stm32wbxx_hal_usart.c
  • HAL_USART_TransmitReceive() : stm32wbxx_hal_usart.c
  • HAL_USART_TransmitReceive_DMA() : stm32wbxx_hal_usart.c
  • HAL_USART_TransmitReceive_IT() : stm32wbxx_hal_usart.c
  • HAL_USART_TX_COMPLETE_CB_ID : stm32wbxx_hal_usart.h
  • HAL_USART_TX_FIFO_EMPTY_CB_ID : stm32wbxx_hal_usart.h
  • HAL_USART_TX_HALFCOMPLETE_CB_ID : stm32wbxx_hal_usart.h
  • HAL_USART_TX_RX_COMPLETE_CB_ID : stm32wbxx_hal_usart.h
  • HAL_USART_TxCpltCallback() : stm32wbxx_hal_usart.c
  • HAL_USART_TxHalfCpltCallback() : stm32wbxx_hal_usart.c
  • HAL_USART_TxRxCpltCallback() : stm32wbxx_hal_usart.c
  • HAL_USART_UnRegisterCallback() : stm32wbxx_hal_usart.c
  • HAL_USARTEx_ConfigNSS() : stm32wbxx_hal_usart_ex.c
  • HAL_USARTEx_DisableFifoMode() : stm32wbxx_hal_usart_ex.c
  • HAL_USARTEx_DisableSlaveMode() : stm32wbxx_hal_usart_ex.c
  • HAL_USARTEx_EnableFifoMode() : stm32wbxx_hal_usart_ex.c
  • HAL_USARTEx_EnableSlaveMode() : stm32wbxx_hal_usart_ex.c
  • HAL_USARTEx_RxFifoFullCallback() : stm32wbxx_hal_usart_ex.c
  • HAL_USARTEx_SetRxFifoThreshold() : stm32wbxx_hal_usart_ex.c
  • HAL_USARTEx_SetTxFifoThreshold() : stm32wbxx_hal_usart_ex.c
  • HAL_USARTEx_TxFifoEmptyCallback() : stm32wbxx_hal_usart_ex.c
  • HAL_WWDG_CallbackIDTypeDef : stm32wbxx_hal_wwdg.h
  • HAL_WWDG_EarlyWakeupCallback() : stm32wbxx_hal_wwdg.c
  • HAL_WWDG_EWI_CB_ID : stm32wbxx_hal_wwdg.h
  • HAL_WWDG_Init() : stm32wbxx_hal_wwdg.c
  • HAL_WWDG_IRQHandler() : stm32wbxx_hal_wwdg.c
  • HAL_WWDG_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_WWDG_MspInit() : stm32wbxx_hal_wwdg.c
  • HAL_WWDG_MSPINIT_CB_ID : stm32wbxx_hal_wwdg.h
  • HAL_WWDG_Refresh() : stm32wbxx_hal_wwdg.c
  • HAL_WWDG_RegisterCallback() : stm32wbxx_hal_wwdg.c
  • HAL_WWDG_UnRegisterCallback() : stm32wbxx_hal_wwdg.c
  • HSE_CONTROL_UNLOCK_KEY : stm32wbxx_ll_rcc.h
  • HSE_STARTUP_TIMEOUT : stm32wbxx_hal_conf.h
  • HSE_TIMEOUT_VALUE : stm32wbxx_hal_rcc.c
  • HSE_VALUE : stm32wbxx_hal_conf.h
  • HSI48_TIMEOUT_VALUE : stm32wbxx_hal_rcc.c
  • HSI48_VALUE : stm32wbxx_hal_conf.h
  • HSI_TIMEOUT_VALUE : stm32wbxx_hal_rcc.c
  • HSI_VALUE : stm32wbxx_hal_conf.h
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- i -

  • I2C_ADDRESSINGMODE_10BIT : stm32wbxx_hal_i2c.h
  • I2C_ADDRESSINGMODE_7BIT : stm32wbxx_hal_i2c.h
  • I2C_ANALOGFILTER_DISABLE : stm32wbxx_hal_i2c_ex.h
  • I2C_ANALOGFILTER_ENABLE : stm32wbxx_hal_i2c_ex.h
  • I2C_AUTOEND_MODE : stm32wbxx_hal_i2c.h
  • I2C_CHECK_FLAG : stm32wbxx_hal_i2c.h
  • I2C_CHECK_IT_SOURCE : stm32wbxx_hal_i2c.h
  • I2C_ConvertOtherXferOptions() : stm32wbxx_hal_i2c.c
  • I2C_DIRECTION_RECEIVE : stm32wbxx_hal_i2c.h
  • I2C_DIRECTION_TRANSMIT : stm32wbxx_hal_i2c.h
  • I2C_Disable_IRQ() : stm32wbxx_hal_i2c.c
  • I2C_DMAAbort() : stm32wbxx_hal_i2c.c
  • I2C_DMAError() : stm32wbxx_hal_i2c.c
  • I2C_DMAMasterReceiveCplt() : stm32wbxx_hal_i2c.c
  • I2C_DMAMasterTransmitCplt() : stm32wbxx_hal_i2c.c
  • I2C_DMASlaveReceiveCplt() : stm32wbxx_hal_i2c.c
  • I2C_DMASlaveTransmitCplt() : stm32wbxx_hal_i2c.c
  • I2C_DUALADDRESS_DISABLE : stm32wbxx_hal_i2c.h
  • I2C_DUALADDRESS_ENABLE : stm32wbxx_hal_i2c.h
  • I2C_Enable_IRQ() : stm32wbxx_hal_i2c.c
  • I2C_FASTMODEPLUS_I2C1 : stm32wbxx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_I2C3 : stm32wbxx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB6 : stm32wbxx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB7 : stm32wbxx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB8 : stm32wbxx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB9 : stm32wbxx_hal_i2c_ex.h
  • I2C_FIRST_AND_LAST_FRAME : stm32wbxx_hal_i2c.h
  • I2C_FIRST_AND_NEXT_FRAME : stm32wbxx_hal_i2c.h
  • I2C_FIRST_FRAME : stm32wbxx_hal_i2c.h
  • I2C_FLAG_ADDR : stm32wbxx_hal_i2c.h
  • I2C_FLAG_AF : stm32wbxx_hal_i2c.h
  • I2C_FLAG_ALERT : stm32wbxx_hal_i2c.h
  • I2C_FLAG_ARLO : stm32wbxx_hal_i2c.h
  • I2C_FLAG_BERR : stm32wbxx_hal_i2c.h
  • I2C_FLAG_BUSY : stm32wbxx_hal_i2c.h
  • I2C_FLAG_DIR : stm32wbxx_hal_i2c.h
  • I2C_FLAG_MASK : stm32wbxx_hal_i2c.h
  • I2C_FLAG_OVR : stm32wbxx_hal_i2c.h
  • I2C_FLAG_PECERR : stm32wbxx_hal_i2c.h
  • I2C_FLAG_RXNE : stm32wbxx_hal_i2c.h
  • I2C_FLAG_STOPF : stm32wbxx_hal_i2c.h
  • I2C_FLAG_TC : stm32wbxx_hal_i2c.h
  • I2C_FLAG_TCR : stm32wbxx_hal_i2c.h
  • I2C_FLAG_TIMEOUT : stm32wbxx_hal_i2c.h
  • I2C_FLAG_TXE : stm32wbxx_hal_i2c.h
  • I2C_FLAG_TXIS : stm32wbxx_hal_i2c.h
  • I2C_Flush_TXDR() : stm32wbxx_hal_i2c.c
  • I2C_FMP_NOT_SUPPORTED : stm32wbxx_hal_i2c_ex.h
  • I2C_GENERALCALL_DISABLE : stm32wbxx_hal_i2c.h
  • I2C_GENERALCALL_ENABLE : stm32wbxx_hal_i2c.h
  • I2C_GENERATE_START : stm32wbxx_hal_i2c.h
  • I2C_GENERATE_START_READ : stm32wbxx_hal_i2c.h
  • I2C_GENERATE_START_WRITE : stm32wbxx_hal_i2c.h
  • I2C_GENERATE_STOP : stm32wbxx_hal_i2c.h
  • I2C_GET_ADDR_MATCH : stm32wbxx_hal_i2c.h
  • I2C_GET_DIR : stm32wbxx_hal_i2c.h
  • I2C_GET_OWN_ADDRESS1 : stm32wbxx_hal_i2c.h
  • I2C_GET_OWN_ADDRESS2 : stm32wbxx_hal_i2c.h
  • I2C_GET_STOP_MODE : stm32wbxx_hal_i2c.h
  • I2C_HandleTypeDef : stm32wbxx_hal_i2c.h
  • I2C_IsAcknowledgeFailed() : stm32wbxx_hal_i2c.c
  • I2C_IT_ADDRI : stm32wbxx_hal_i2c.h
  • I2C_IT_ERRI : stm32wbxx_hal_i2c.h
  • I2C_IT_NACKI : stm32wbxx_hal_i2c.h
  • I2C_IT_RXI : stm32wbxx_hal_i2c.h
  • I2C_IT_STOPI : stm32wbxx_hal_i2c.h
  • I2C_IT_TCI : stm32wbxx_hal_i2c.h
  • I2C_IT_TXI : stm32wbxx_hal_i2c.h
  • I2C_ITAddrCplt() : stm32wbxx_hal_i2c.c
  • I2C_ITError() : stm32wbxx_hal_i2c.c
  • I2C_ITListenCplt() : stm32wbxx_hal_i2c.c
  • I2C_ITMasterCplt() : stm32wbxx_hal_i2c.c
  • I2C_ITMasterSeqCplt() : stm32wbxx_hal_i2c.c
  • I2C_ITSlaveCplt() : stm32wbxx_hal_i2c.c
  • I2C_ITSlaveSeqCplt() : stm32wbxx_hal_i2c.c
  • I2C_LAST_FRAME : stm32wbxx_hal_i2c.h
  • I2C_LAST_FRAME_NO_STOP : stm32wbxx_hal_i2c.h
  • I2C_Master_ISR_DMA() : stm32wbxx_hal_i2c.c
  • I2C_Master_ISR_IT() : stm32wbxx_hal_i2c.c
  • I2C_MEM_ADD_LSB : stm32wbxx_hal_i2c.h
  • I2C_MEM_ADD_MSB : stm32wbxx_hal_i2c.h
  • I2C_MEMADD_SIZE_16BIT : stm32wbxx_hal_i2c.h
  • I2C_MEMADD_SIZE_8BIT : stm32wbxx_hal_i2c.h
  • I2C_NEXT_FRAME : stm32wbxx_hal_i2c.h
  • I2C_NO_OPTION_FRAME : stm32wbxx_hal_i2c.c
  • I2C_NO_STARTSTOP : stm32wbxx_hal_i2c.h
  • I2C_NOSTRETCH_DISABLE : stm32wbxx_hal_i2c.h
  • I2C_NOSTRETCH_ENABLE : stm32wbxx_hal_i2c.h
  • I2C_OA2_MASK01 : stm32wbxx_hal_i2c.h
  • I2C_OA2_MASK02 : stm32wbxx_hal_i2c.h
  • I2C_OA2_MASK03 : stm32wbxx_hal_i2c.h
  • I2C_OA2_MASK04 : stm32wbxx_hal_i2c.h
  • I2C_OA2_MASK05 : stm32wbxx_hal_i2c.h
  • I2C_OA2_MASK06 : stm32wbxx_hal_i2c.h
  • I2C_OA2_MASK07 : stm32wbxx_hal_i2c.h
  • I2C_OA2_NOMASK : stm32wbxx_hal_i2c.h
  • I2C_OTHER_AND_LAST_FRAME : stm32wbxx_hal_i2c.h
  • I2C_OTHER_FRAME : stm32wbxx_hal_i2c.h
  • I2C_RELOAD_MODE : stm32wbxx_hal_i2c.h
  • I2C_RequestMemoryRead() : stm32wbxx_hal_i2c.c
  • I2C_RequestMemoryWrite() : stm32wbxx_hal_i2c.c
  • I2C_RESET_CR2 : stm32wbxx_hal_i2c.h
  • I2C_Slave_ISR_DMA() : stm32wbxx_hal_i2c.c
  • I2C_Slave_ISR_IT() : stm32wbxx_hal_i2c.c
  • I2C_SOFTEND_MODE : stm32wbxx_hal_i2c.h
  • I2C_STATE_MASTER_BUSY_RX : stm32wbxx_hal_i2c.c
  • I2C_STATE_MASTER_BUSY_TX : stm32wbxx_hal_i2c.c
  • I2C_STATE_MEM_BUSY_RX : stm32wbxx_hal_i2c.c
  • I2C_STATE_MEM_BUSY_TX : stm32wbxx_hal_i2c.c
  • I2C_STATE_MSK : stm32wbxx_hal_i2c.c
  • I2C_STATE_NONE : stm32wbxx_hal_i2c.c
  • I2C_STATE_SLAVE_BUSY_RX : stm32wbxx_hal_i2c.c
  • I2C_STATE_SLAVE_BUSY_TX : stm32wbxx_hal_i2c.c
  • I2C_TIMEOUT_ADDR : stm32wbxx_hal_i2c.c
  • I2C_TIMEOUT_BUSY : stm32wbxx_hal_i2c.c
  • I2C_TIMEOUT_DIR : stm32wbxx_hal_i2c.c
  • I2C_TIMEOUT_FLAG : stm32wbxx_hal_i2c.c
  • I2C_TIMEOUT_RXNE : stm32wbxx_hal_i2c.c
  • I2C_TIMEOUT_STOPF : stm32wbxx_hal_i2c.c
  • I2C_TIMEOUT_TC : stm32wbxx_hal_i2c.c
  • I2C_TIMEOUT_TCR : stm32wbxx_hal_i2c.c
  • I2C_TIMEOUT_TXIS : stm32wbxx_hal_i2c.c
  • I2C_TransferConfig() : stm32wbxx_hal_i2c.c
  • I2C_WaitOnFlagUntilTimeout() : stm32wbxx_hal_i2c.c
  • I2C_WaitOnRXNEFlagUntilTimeout() : stm32wbxx_hal_i2c.c
  • I2C_WaitOnSTOPFlagUntilTimeout() : stm32wbxx_hal_i2c.c
  • I2C_WaitOnTXISFlagUntilTimeout() : stm32wbxx_hal_i2c.c
  • I2C_XFER_CPLT_IT : stm32wbxx_hal_i2c.c
  • I2C_XFER_ERROR_IT : stm32wbxx_hal_i2c.c
  • I2C_XFER_LISTEN_IT : stm32wbxx_hal_i2c.c
  • I2C_XFER_RELOAD_IT : stm32wbxx_hal_i2c.c
  • I2C_XFER_RX_IT : stm32wbxx_hal_i2c.c
  • I2C_XFER_TX_IT : stm32wbxx_hal_i2c.c
  • IC1Config() : stm32wbxx_ll_tim.c
  • IC2Config() : stm32wbxx_ll_tim.c
  • IC3Config() : stm32wbxx_ll_tim.c
  • IC4Config() : stm32wbxx_ll_tim.c
  • INSTRUCTION_CACHE_ENABLE : stm32wbxx_hal_conf.h
  • IPCC_ALL_RX_BUF : stm32wbxx_hal_ipcc.c
  • IPCC_ALL_TX_BUF : stm32wbxx_hal_ipcc.c
  • IPCC_CHANNEL_1 : stm32wbxx_hal_ipcc.h
  • IPCC_CHANNEL_2 : stm32wbxx_hal_ipcc.h
  • IPCC_CHANNEL_3 : stm32wbxx_hal_ipcc.h
  • IPCC_CHANNEL_4 : stm32wbxx_hal_ipcc.h
  • IPCC_CHANNEL_5 : stm32wbxx_hal_ipcc.h
  • IPCC_CHANNEL_6 : stm32wbxx_hal_ipcc.h
  • IPCC_CHANNEL_DIR_RX : stm32wbxx_hal_ipcc.h
  • IPCC_CHANNEL_DIR_TX : stm32wbxx_hal_ipcc.h
  • IPCC_CHANNEL_STATUS_FREE : stm32wbxx_hal_ipcc.h
  • IPCC_CHANNEL_STATUS_OCCUPIED : stm32wbxx_hal_ipcc.h
  • IPCC_CHANNELDirTypeDef : stm32wbxx_hal_ipcc.h
  • IPCC_CHANNELStatusTypeDef : stm32wbxx_hal_ipcc.h
  • IPCC_HandleTypeDef : stm32wbxx_hal_ipcc.h
  • IPCC_MaskInterrupt() : stm32wbxx_hal_ipcc.c
  • IPCC_Reset_Register() : stm32wbxx_hal_ipcc.c
  • IPCC_SetDefaultCallbacks() : stm32wbxx_hal_ipcc.c
  • IPCC_UnmaskInterrupt() : stm32wbxx_hal_ipcc.c
  • IRDA_AUTOBAUD_REQUEST : stm32wbxx_hal_irda.h
  • IRDA_CheckIdleState() : stm32wbxx_hal_irda.c
  • IRDA_CLEAR_FEF : stm32wbxx_hal_irda.h
  • IRDA_CLEAR_IDLEF : stm32wbxx_hal_irda.h
  • IRDA_CLEAR_NEF : stm32wbxx_hal_irda.h
  • IRDA_CLEAR_OREF : stm32wbxx_hal_irda.h
  • IRDA_CLEAR_PEF : stm32wbxx_hal_irda.h
  • IRDA_CLEAR_TCF : stm32wbxx_hal_irda.h
  • IRDA_CLOCKSOURCE_HSI : stm32wbxx_hal_irda.h
  • IRDA_CLOCKSOURCE_LSE : stm32wbxx_hal_irda.h
  • IRDA_CLOCKSOURCE_PCLK2 : stm32wbxx_hal_irda.h
  • IRDA_CLOCKSOURCE_SYSCLK : stm32wbxx_hal_irda.h
  • IRDA_CLOCKSOURCE_UNDEFINED : stm32wbxx_hal_irda.h
  • IRDA_ClockSourceTypeDef : stm32wbxx_hal_irda.h
  • IRDA_CR1_FIELDS : stm32wbxx_hal_irda.c
  • IRDA_CR_MASK : stm32wbxx_hal_irda.h
  • IRDA_CR_POS : stm32wbxx_hal_irda.h
  • IRDA_DIV_SAMPLING16 : stm32wbxx_hal_irda.c
  • IRDA_DMA_RX_DISABLE : stm32wbxx_hal_irda.h
  • IRDA_DMA_RX_ENABLE : stm32wbxx_hal_irda.h
  • IRDA_DMA_TX_DISABLE : stm32wbxx_hal_irda.h
  • IRDA_DMA_TX_ENABLE : stm32wbxx_hal_irda.h
  • IRDA_DMAAbortOnError() : stm32wbxx_hal_irda.c
  • IRDA_DMAError() : stm32wbxx_hal_irda.c
  • IRDA_DMAReceiveCplt() : stm32wbxx_hal_irda.c
  • IRDA_DMAReceiveHalfCplt() : stm32wbxx_hal_irda.c
  • IRDA_DMARxAbortCallback() : stm32wbxx_hal_irda.c
  • IRDA_DMARxOnlyAbortCallback() : stm32wbxx_hal_irda.c
  • IRDA_DMATransmitCplt() : stm32wbxx_hal_irda.c
  • IRDA_DMATransmitHalfCplt() : stm32wbxx_hal_irda.c
  • IRDA_DMATxAbortCallback() : stm32wbxx_hal_irda.c
  • IRDA_DMATxOnlyAbortCallback() : stm32wbxx_hal_irda.c
  • IRDA_EndRxTransfer() : stm32wbxx_hal_irda.c
  • IRDA_EndTransmit_IT() : stm32wbxx_hal_irda.c
  • IRDA_EndTxTransfer() : stm32wbxx_hal_irda.c
  • IRDA_FLAG_ABRE : stm32wbxx_hal_irda.h
  • IRDA_FLAG_ABRF : stm32wbxx_hal_irda.h
  • IRDA_FLAG_BUSY : stm32wbxx_hal_irda.h
  • IRDA_FLAG_FE : stm32wbxx_hal_irda.h
  • IRDA_FLAG_NE : stm32wbxx_hal_irda.h
  • IRDA_FLAG_ORE : stm32wbxx_hal_irda.h
  • IRDA_FLAG_PE : stm32wbxx_hal_irda.h
  • IRDA_FLAG_REACK : stm32wbxx_hal_irda.h
  • IRDA_FLAG_RXNE : stm32wbxx_hal_irda.h
  • IRDA_FLAG_TC : stm32wbxx_hal_irda.h
  • IRDA_FLAG_TEACK : stm32wbxx_hal_irda.h
  • IRDA_FLAG_TXE : stm32wbxx_hal_irda.h
  • IRDA_GETCLOCKSOURCE : stm32wbxx_hal_irda_ex.h
  • IRDA_HandleTypeDef : stm32wbxx_hal_irda.h
  • IRDA_InitCallbacksToDefault() : stm32wbxx_hal_irda.c
  • IRDA_ISR_MASK : stm32wbxx_hal_irda.h
  • IRDA_ISR_POS : stm32wbxx_hal_irda.h
  • IRDA_IT_ERR : stm32wbxx_hal_irda.h
  • IRDA_IT_FE : stm32wbxx_hal_irda.h
  • IRDA_IT_IDLE : stm32wbxx_hal_irda.h
  • IRDA_IT_MASK : stm32wbxx_hal_irda.h
  • IRDA_IT_NE : stm32wbxx_hal_irda.h
  • IRDA_IT_ORE : stm32wbxx_hal_irda.h
  • IRDA_IT_PE : stm32wbxx_hal_irda.h
  • IRDA_IT_RXNE : stm32wbxx_hal_irda.h
  • IRDA_IT_TC : stm32wbxx_hal_irda.h
  • IRDA_IT_TXE : stm32wbxx_hal_irda.h
  • IRDA_MASK_COMPUTATION : stm32wbxx_hal_irda.h
  • IRDA_MODE_DISABLE : stm32wbxx_hal_irda.h
  • IRDA_MODE_ENABLE : stm32wbxx_hal_irda.h
  • IRDA_MODE_RX : stm32wbxx_hal_irda.h
  • IRDA_MODE_TX : stm32wbxx_hal_irda.h
  • IRDA_MODE_TX_RX : stm32wbxx_hal_irda.h
  • IRDA_ONE_BIT_SAMPLE_DISABLE : stm32wbxx_hal_irda.h
  • IRDA_ONE_BIT_SAMPLE_ENABLE : stm32wbxx_hal_irda.h
  • IRDA_PARITY_EVEN : stm32wbxx_hal_irda.h
  • IRDA_PARITY_NONE : stm32wbxx_hal_irda.h
  • IRDA_PARITY_ODD : stm32wbxx_hal_irda.h
  • IRDA_POWERMODE_LOWPOWER : stm32wbxx_hal_irda.h
  • IRDA_POWERMODE_NORMAL : stm32wbxx_hal_irda.h
  • IRDA_PRESCALER_DIV1 : stm32wbxx_hal_irda.h
  • IRDA_PRESCALER_DIV10 : stm32wbxx_hal_irda.h
  • IRDA_PRESCALER_DIV12 : stm32wbxx_hal_irda.h
  • IRDA_PRESCALER_DIV128 : stm32wbxx_hal_irda.h
  • IRDA_PRESCALER_DIV16 : stm32wbxx_hal_irda.h
  • IRDA_PRESCALER_DIV2 : stm32wbxx_hal_irda.h
  • IRDA_PRESCALER_DIV256 : stm32wbxx_hal_irda.h
  • IRDA_PRESCALER_DIV32 : stm32wbxx_hal_irda.h
  • IRDA_PRESCALER_DIV4 : stm32wbxx_hal_irda.h
  • IRDA_PRESCALER_DIV6 : stm32wbxx_hal_irda.h
  • IRDA_PRESCALER_DIV64 : stm32wbxx_hal_irda.h
  • IRDA_PRESCALER_DIV8 : stm32wbxx_hal_irda.h
  • IRDA_Receive_IT() : stm32wbxx_hal_irda.c
  • IRDA_RXDATA_FLUSH_REQUEST : stm32wbxx_hal_irda.h
  • IRDA_SetConfig() : stm32wbxx_hal_irda.c
  • IRDA_STATE_DISABLE : stm32wbxx_hal_irda.h
  • IRDA_STATE_ENABLE : stm32wbxx_hal_irda.h
  • IRDA_TEACK_REACK_TIMEOUT : stm32wbxx_hal_irda.c
  • IRDA_Transmit_IT() : stm32wbxx_hal_irda.c
  • IRDA_TXDATA_FLUSH_REQUEST : stm32wbxx_hal_irda.h
  • IRDA_WaitOnFlagUntilTimeout() : stm32wbxx_hal_irda.c
  • IRDA_WORDLENGTH_7B : stm32wbxx_hal_irda.h
  • IRDA_WORDLENGTH_8B : stm32wbxx_hal_irda.h
  • IRDA_WORDLENGTH_9B : stm32wbxx_hal_irda.h
  • IS_ADC_ANALOG_WATCHDOG_MODE : stm32wbxx_hal_adc_ex.h
  • IS_ADC_ANALOG_WATCHDOG_NUMBER : stm32wbxx_hal_adc_ex.h
  • IS_ADC_CALFACT : stm32wbxx_hal_adc_ex.h
  • IS_ADC_CHANNEL : stm32wbxx_hal_adc_ex.h
  • IS_ADC_CLOCKPRESCALER : stm32wbxx_hal_adc.h
  • IS_ADC_CONVERSION_GROUP : stm32wbxx_hal_adc_ex.h
  • IS_ADC_DATA_ALIGN : stm32wbxx_hal_adc.h
  • IS_ADC_DFSDMCFG_MODE : stm32wbxx_hal_adc_ex.h
  • IS_ADC_DIFF_CHANNEL : stm32wbxx_hal_adc_ex.h
  • IS_ADC_EOC_SELECTION : stm32wbxx_hal_adc.h
  • IS_ADC_EVENT_TYPE : stm32wbxx_hal_adc_ex.h
  • IS_ADC_EXTTRIG : stm32wbxx_hal_adc.h
  • IS_ADC_EXTTRIG_EDGE : stm32wbxx_hal_adc.h
  • IS_ADC_EXTTRIGINJEC : stm32wbxx_hal_adc_ex.h
  • IS_ADC_EXTTRIGINJEC_EDGE : stm32wbxx_hal_adc_ex.h
  • IS_ADC_INJECTED_NB_CONV : stm32wbxx_hal_adc_ex.h
  • IS_ADC_INJECTED_RANK : stm32wbxx_hal_adc_ex.h
  • IS_ADC_OFFSET_NUMBER : stm32wbxx_hal_adc_ex.h
  • IS_ADC_OVERRUN : stm32wbxx_hal_adc.h
  • IS_ADC_OVERSAMPLING_RATIO : stm32wbxx_hal_adc_ex.h
  • IS_ADC_RANGE : stm32wbxx_hal_adc.h
  • IS_ADC_REGOVERSAMPLING_MODE : stm32wbxx_hal_adc_ex.h
  • IS_ADC_REGULAR_DISCONT_NUMBER : stm32wbxx_hal_adc.h
  • IS_ADC_REGULAR_NB_CONV : stm32wbxx_hal_adc.h
  • IS_ADC_REGULAR_RANK : stm32wbxx_hal_adc.h
  • IS_ADC_RESOLUTION : stm32wbxx_hal_adc.h
  • IS_ADC_RESOLUTION_8_6_BITS : stm32wbxx_hal_adc.h
  • IS_ADC_RIGHT_BIT_SHIFT : stm32wbxx_hal_adc_ex.h
  • IS_ADC_SAMPLE_TIME : stm32wbxx_hal_adc.h
  • IS_ADC_SCAN_MODE : stm32wbxx_hal_adc.h
  • IS_ADC_SINGLE_DIFFERENTIAL : stm32wbxx_hal_adc_ex.h
  • IS_ADC_TRIGGERED_OVERSAMPLING_MODE : stm32wbxx_hal_adc_ex.h
  • IS_ADDR_ALIGNED_64BITS : stm32wbxx_hal_flash.h
  • IS_COMP_BLANKINGSRC_INSTANCE : stm32wbxx_hal_comp.h
  • IS_COMP_BLANKINGSRCE : stm32wbxx_hal_comp.h
  • IS_COMP_HYSTERESIS : stm32wbxx_hal_comp.h
  • IS_COMP_INPUT_MINUS : stm32wbxx_hal_comp.h
  • IS_COMP_INPUT_PLUS : stm32wbxx_hal_comp.h
  • IS_COMP_OUTPUT_LEVEL : stm32wbxx_hal_comp.h
  • IS_COMP_OUTPUTPOL : stm32wbxx_hal_comp.h
  • IS_COMP_POWERMODE : stm32wbxx_hal_comp.h
  • IS_COMP_TRIGGERMODE : stm32wbxx_hal_comp.h
  • IS_COMP_WINDOWMODE : stm32wbxx_hal_comp.h
  • IS_CRC_INPUTDATA_FORMAT : stm32wbxx_hal_crc.h
  • IS_CRC_INPUTDATA_INVERSION_MODE : stm32wbxx_hal_crc_ex.h
  • IS_CRC_OUTPUTDATA_INVERSION_MODE : stm32wbxx_hal_crc_ex.h
  • IS_CRC_POL_LENGTH : stm32wbxx_hal_crc.h
  • IS_CRYP_ALGORITHM : stm32wbxx_hal_cryp.h
  • IS_CRYP_BUFFERSIZE : stm32wbxx_hal_cryp.h
  • IS_CRYP_DATATYPE : stm32wbxx_hal_cryp.h
  • IS_CRYP_INIT : stm32wbxx_hal_cryp.h
  • IS_CRYP_KEYSIZE : stm32wbxx_hal_cryp.h
  • IS_DEFAULT_INIT_VALUE : stm32wbxx_hal_crc.h
  • IS_DEFAULT_POLYNOMIAL : stm32wbxx_hal_crc.h
  • IS_DMA_ALL_REQUEST : stm32wbxx_hal_dma.h
  • IS_DMA_BUFFER_SIZE : stm32wbxx_hal_dma.h
  • IS_DMA_DIRECTION : stm32wbxx_hal_dma.h
  • IS_DMA_MEMORY_DATA_SIZE : stm32wbxx_hal_dma.h
  • IS_DMA_MEMORY_INC_STATE : stm32wbxx_hal_dma.h
  • IS_DMA_MODE : stm32wbxx_hal_dma.h
  • IS_DMA_PERIPHERAL_DATA_SIZE : stm32wbxx_hal_dma.h
  • IS_DMA_PERIPHERAL_INC_STATE : stm32wbxx_hal_dma.h
  • IS_DMA_PRIORITY : stm32wbxx_hal_dma.h
  • IS_DMAMUX_REQUEST_GEN_POLARITY : stm32wbxx_hal_dma_ex.h
  • IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER : stm32wbxx_hal_dma_ex.h
  • IS_DMAMUX_REQUEST_GEN_SIGNAL_ID : stm32wbxx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_EVENT : stm32wbxx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_POLARITY : stm32wbxx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_REQUEST_NUMBER : stm32wbxx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_SIGNAL_ID : stm32wbxx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_STATE : stm32wbxx_hal_dma_ex.h
  • IS_EXTI_CONFIG_LINE : stm32wbxx_hal_exti.h
  • IS_EXTI_GPIO_PIN : stm32wbxx_hal_exti.h
  • IS_EXTI_GPIO_PORT : stm32wbxx_hal_exti.h
  • IS_EXTI_LINE : stm32wbxx_hal_exti.h
  • IS_EXTI_MODE : stm32wbxx_hal_exti.h
  • IS_EXTI_PENDING_EDGE : stm32wbxx_hal_exti.h
  • IS_EXTI_TRIGGER : stm32wbxx_hal_exti.h
  • IS_FLASH_EMPTY_CHECK : stm32wbxx_hal_flash_ex.h
  • IS_FLASH_FAST_PROGRAM_ADDRESS : stm32wbxx_hal_flash.h
  • IS_FLASH_LATENCY : stm32wbxx_hal_flash.h
  • IS_FLASH_MAIN_MEM_ADDRESS : stm32wbxx_hal_flash.h
  • IS_FLASH_PAGE : stm32wbxx_hal_flash.h
  • IS_FLASH_PROGRAM_ADDRESS : stm32wbxx_hal_flash.h
  • IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS : stm32wbxx_hal_flash.h
  • IS_FLASH_PROGRAM_OTP_ADDRESS : stm32wbxx_hal_flash.h
  • IS_FLASH_TYPEERASE : stm32wbxx_hal_flash.h
  • IS_FLASH_TYPEPROGRAM : stm32wbxx_hal_flash.h
  • IS_GPIO_AF : stm32wbxx_hal_gpio_ex.h
  • IS_GPIO_MODE : stm32wbxx_hal_gpio.h
  • IS_GPIO_PIN : stm32wbxx_hal_gpio.h
  • IS_GPIO_PIN_ACTION : stm32wbxx_hal_gpio.h
  • IS_GPIO_PULL : stm32wbxx_hal_gpio.h
  • IS_GPIO_SPEED : stm32wbxx_hal_gpio.h
  • IS_HSEM_COREID : stm32wbxx_hal_hsem.h
  • IS_HSEM_KEY : stm32wbxx_hal_hsem.h
  • IS_HSEM_PROCESSID : stm32wbxx_hal_hsem.h
  • IS_HSEM_SEMID : stm32wbxx_hal_hsem.h
  • IS_I2C_ADDRESSING_MODE : stm32wbxx_hal_i2c.h
  • IS_I2C_ANALOG_FILTER : stm32wbxx_hal_i2c_ex.h
  • IS_I2C_DIGITAL_FILTER : stm32wbxx_hal_i2c_ex.h
  • IS_I2C_DUAL_ADDRESS : stm32wbxx_hal_i2c.h
  • IS_I2C_FASTMODEPLUS : stm32wbxx_hal_i2c_ex.h
  • IS_I2C_GENERAL_CALL : stm32wbxx_hal_i2c.h
  • IS_I2C_MEMADD_SIZE : stm32wbxx_hal_i2c.h
  • IS_I2C_NO_STRETCH : stm32wbxx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS1 : stm32wbxx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS2 : stm32wbxx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS2_MASK : stm32wbxx_hal_i2c.h
  • IS_I2C_TRANSFER_OPTIONS_REQUEST : stm32wbxx_hal_i2c.h
  • IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST : stm32wbxx_hal_i2c.h
  • IS_IRDA_BAUDRATE : stm32wbxx_hal_irda.h
  • IS_IRDA_CLOCKPRESCALER : stm32wbxx_hal_irda.h
  • IS_IRDA_DMA_RX : stm32wbxx_hal_irda.h
  • IS_IRDA_DMA_TX : stm32wbxx_hal_irda.h
  • IS_IRDA_MODE : stm32wbxx_hal_irda.h
  • IS_IRDA_ONE_BIT_SAMPLE : stm32wbxx_hal_irda.h
  • IS_IRDA_PARITY : stm32wbxx_hal_irda.h
  • IS_IRDA_POWERMODE : stm32wbxx_hal_irda.h
  • IS_IRDA_PRESCALER : stm32wbxx_hal_irda.h
  • IS_IRDA_REQUEST_PARAMETER : stm32wbxx_hal_irda.h
  • IS_IRDA_STATE : stm32wbxx_hal_irda.h
  • IS_IRDA_TX_RX_MODE : stm32wbxx_hal_irda.h
  • IS_IRDA_WORD_LENGTH : stm32wbxx_hal_irda.h
  • IS_IWDG_PRESCALER : stm32wbxx_hal_iwdg.h
  • IS_IWDG_RELOAD : stm32wbxx_hal_iwdg.h
  • IS_IWDG_WINDOW : stm32wbxx_hal_iwdg.h
  • IS_LCD_BIAS : stm32wbxx_hal_lcd.h
  • IS_LCD_BLINK_FREQUENCY : stm32wbxx_hal_lcd.h
  • IS_LCD_BLINK_MODE : stm32wbxx_hal_lcd.h
  • IS_LCD_CONTRAST : stm32wbxx_hal_lcd.h
  • IS_LCD_DEAD_TIME : stm32wbxx_hal_lcd.h
  • IS_LCD_DIVIDER : stm32wbxx_hal_lcd.h
  • IS_LCD_DUTY : stm32wbxx_hal_lcd.h
  • IS_LCD_HIGH_DRIVE : stm32wbxx_hal_lcd.h
  • IS_LCD_MUX_SEGMENT : stm32wbxx_hal_lcd.h
  • IS_LCD_PRESCALER : stm32wbxx_hal_lcd.h
  • IS_LCD_PULSE_ON_DURATION : stm32wbxx_hal_lcd.h
  • IS_LCD_RAM_REGISTER : stm32wbxx_hal_lcd.h
  • IS_LCD_VOLTAGE_SOURCE : stm32wbxx_hal_lcd.h
  • IS_LL_ADC_COMMON_CLOCK : stm32wbxx_ll_adc.c
  • IS_LL_ADC_DATA_ALIGN : stm32wbxx_ll_adc.c
  • IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE : stm32wbxx_ll_adc.c
  • IS_LL_ADC_INJ_SEQ_SCAN_LENGTH : stm32wbxx_ll_adc.c
  • IS_LL_ADC_INJ_TRIG_AUTO : stm32wbxx_ll_adc.c
  • IS_LL_ADC_INJ_TRIG_EXT_EDGE : stm32wbxx_ll_adc.c
  • IS_LL_ADC_INJ_TRIG_SOURCE : stm32wbxx_ll_adc.c
  • IS_LL_ADC_LOW_POWER : stm32wbxx_ll_adc.c
  • IS_LL_ADC_REG_CONTINUOUS_MODE : stm32wbxx_ll_adc.c
  • IS_LL_ADC_REG_DMA_TRANSFER : stm32wbxx_ll_adc.c
  • IS_LL_ADC_REG_OVR_DATA_BEHAVIOR : stm32wbxx_ll_adc.c
  • IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE : stm32wbxx_ll_adc.c
  • IS_LL_ADC_REG_SEQ_SCAN_LENGTH : stm32wbxx_ll_adc.c
  • IS_LL_ADC_REG_TRIG_SOURCE : stm32wbxx_ll_adc.c
  • IS_LL_ADC_RESOLUTION : stm32wbxx_ll_adc.c
  • IS_LL_COMP_INPUT_HYSTERESIS : stm32wbxx_ll_comp.c
  • IS_LL_COMP_INPUT_MINUS : stm32wbxx_ll_comp.c
  • IS_LL_COMP_INPUT_PLUS : stm32wbxx_ll_comp.c
  • IS_LL_COMP_OUTPUT_BLANKING_SOURCE : stm32wbxx_ll_comp.c
  • IS_LL_COMP_OUTPUT_POLARITY : stm32wbxx_ll_comp.c
  • IS_LL_COMP_POWER_MODE : stm32wbxx_ll_comp.c
  • IS_LL_DMA_ALL_CHANNEL_INSTANCE : stm32wbxx_ll_dma.c
  • IS_LL_DMA_DIRECTION : stm32wbxx_ll_dma.c
  • IS_LL_DMA_MEMORYDATASIZE : stm32wbxx_ll_dma.c
  • IS_LL_DMA_MEMORYINCMODE : stm32wbxx_ll_dma.c
  • IS_LL_DMA_MODE : stm32wbxx_ll_dma.c
  • IS_LL_DMA_NBDATA : stm32wbxx_ll_dma.c
  • IS_LL_DMA_PERIPHDATASIZE : stm32wbxx_ll_dma.c
  • IS_LL_DMA_PERIPHINCMODE : stm32wbxx_ll_dma.c
  • IS_LL_DMA_PERIPHREQUEST : stm32wbxx_ll_dma.c
  • IS_LL_DMA_PRIORITY : stm32wbxx_ll_dma.c
  • IS_LL_EXTI_LINE_0_31 : stm32wbxx_ll_exti.c
  • IS_LL_EXTI_LINE_32_63 : stm32wbxx_ll_exti.c
  • IS_LL_EXTI_MODE : stm32wbxx_ll_exti.c
  • IS_LL_EXTI_TRIGGER : stm32wbxx_ll_exti.c
  • IS_LL_GPIO_ALTERNATE : stm32wbxx_ll_gpio.c
  • IS_LL_GPIO_MODE : stm32wbxx_ll_gpio.c
  • IS_LL_GPIO_OUTPUT_TYPE : stm32wbxx_ll_gpio.c
  • IS_LL_GPIO_PIN : stm32wbxx_ll_gpio.c
  • IS_LL_GPIO_PULL : stm32wbxx_ll_gpio.c
  • IS_LL_GPIO_SPEED : stm32wbxx_ll_gpio.c
  • IS_LL_I2C_ANALOG_FILTER : stm32wbxx_ll_i2c.c
  • IS_LL_I2C_DIGITAL_FILTER : stm32wbxx_ll_i2c.c
  • IS_LL_I2C_OWN_ADDRESS1 : stm32wbxx_ll_i2c.c
  • IS_LL_I2C_OWN_ADDRSIZE : stm32wbxx_ll_i2c.c
  • IS_LL_I2C_PERIPHERAL_MODE : stm32wbxx_ll_i2c.c
  • IS_LL_I2C_TYPE_ACKNOWLEDGE : stm32wbxx_ll_i2c.c
  • IS_LL_LPTIM_CLOCK_PRESCALER : stm32wbxx_ll_lptim.c
  • IS_LL_LPTIM_CLOCK_SOURCE : stm32wbxx_ll_lptim.c
  • IS_LL_LPTIM_OUTPUT_POLARITY : stm32wbxx_ll_lptim.c
  • IS_LL_LPTIM_WAVEFORM : stm32wbxx_ll_lptim.c
  • IS_LL_LPUART_BAUDRATE : stm32wbxx_ll_lpuart.c
  • IS_LL_LPUART_BRR_MAX : stm32wbxx_ll_lpuart.c
  • IS_LL_LPUART_BRR_MIN : stm32wbxx_ll_lpuart.c
  • IS_LL_LPUART_DATAWIDTH : stm32wbxx_ll_lpuart.c
  • IS_LL_LPUART_DIRECTION : stm32wbxx_ll_lpuart.c
  • IS_LL_LPUART_HWCONTROL : stm32wbxx_ll_lpuart.c
  • IS_LL_LPUART_PARITY : stm32wbxx_ll_lpuart.c
  • IS_LL_LPUART_PRESCALER : stm32wbxx_ll_lpuart.c
  • IS_LL_LPUART_STOPBITS : stm32wbxx_ll_lpuart.c
  • IS_LL_PKA_MODE : stm32wbxx_ll_pka.c
  • IS_LL_RCC_ADC_CLKSOURCE : stm32wbxx_ll_rcc.c
  • IS_LL_RCC_CLK48_CLKSOURCE : stm32wbxx_ll_rcc.c
  • IS_LL_RCC_I2C_CLKSOURCE : stm32wbxx_ll_rcc.c
  • IS_LL_RCC_LPTIM_CLKSOURCE : stm32wbxx_ll_rcc.c
  • IS_LL_RCC_LPUART_CLKSOURCE : stm32wbxx_ll_rcc.c
  • IS_LL_RCC_RNG_CLKSOURCE : stm32wbxx_ll_rcc.c
  • IS_LL_RCC_SAI_CLKSOURCE : stm32wbxx_ll_rcc.c
  • IS_LL_RCC_USART_CLKSOURCE : stm32wbxx_ll_rcc.c
  • IS_LL_RCC_USB_CLKSOURCE : stm32wbxx_ll_rcc.c
  • IS_LL_RNG_CED : stm32wbxx_ll_rng.c
  • IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL : stm32wbxx_ll_rtc.c
  • IS_LL_RTC_ALMA_MASK : stm32wbxx_ll_rtc.c
  • IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL : stm32wbxx_ll_rtc.c
  • IS_LL_RTC_ALMB_MASK : stm32wbxx_ll_rtc.c
  • IS_LL_RTC_ASYNCH_PREDIV : stm32wbxx_ll_rtc.c
  • IS_LL_RTC_DAY : stm32wbxx_ll_rtc.c
  • IS_LL_RTC_FORMAT : stm32wbxx_ll_rtc.c
  • IS_LL_RTC_HOUR12 : stm32wbxx_ll_rtc.c
  • IS_LL_RTC_HOUR24 : stm32wbxx_ll_rtc.c
  • IS_LL_RTC_HOURFORMAT : stm32wbxx_ll_rtc.c
  • IS_LL_RTC_MINUTES : stm32wbxx_ll_rtc.c
  • IS_LL_RTC_MONTH : stm32wbxx_ll_rtc.c
  • IS_LL_RTC_SECONDS : stm32wbxx_ll_rtc.c
  • IS_LL_RTC_SYNCH_PREDIV : stm32wbxx_ll_rtc.c
  • IS_LL_RTC_TIME_FORMAT : stm32wbxx_ll_rtc.c
  • IS_LL_RTC_WEEKDAY : stm32wbxx_ll_rtc.c
  • IS_LL_RTC_YEAR : stm32wbxx_ll_rtc.c
  • IS_LL_SPI_BAUDRATE : stm32wbxx_ll_spi.c
  • IS_LL_SPI_BITORDER : stm32wbxx_ll_spi.c
  • IS_LL_SPI_CRC_POLYNOMIAL : stm32wbxx_ll_spi.c
  • IS_LL_SPI_CRCCALCULATION : stm32wbxx_ll_spi.c
  • IS_LL_SPI_DATAWIDTH : stm32wbxx_ll_spi.c
  • IS_LL_SPI_MODE : stm32wbxx_ll_spi.c
  • IS_LL_SPI_NSS : stm32wbxx_ll_spi.c
  • IS_LL_SPI_PHASE : stm32wbxx_ll_spi.c
  • IS_LL_SPI_POLARITY : stm32wbxx_ll_spi.c
  • IS_LL_SPI_TRANSFER_DIRECTION : stm32wbxx_ll_spi.c
  • IS_LL_TIM_ACTIVEINPUT : stm32wbxx_ll_tim.c
  • IS_LL_TIM_AUTOMATIC_OUTPUT_STATE : stm32wbxx_ll_tim.c
  • IS_LL_TIM_BREAK2_FILTER : stm32wbxx_ll_tim.c
  • IS_LL_TIM_BREAK2_POLARITY : stm32wbxx_ll_tim.c
  • IS_LL_TIM_BREAK2_STATE : stm32wbxx_ll_tim.c
  • IS_LL_TIM_BREAK_FILTER : stm32wbxx_ll_tim.c
  • IS_LL_TIM_BREAK_POLARITY : stm32wbxx_ll_tim.c
  • IS_LL_TIM_BREAK_STATE : stm32wbxx_ll_tim.c
  • IS_LL_TIM_CLOCKDIVISION : stm32wbxx_ll_tim.c
  • IS_LL_TIM_COUNTERMODE : stm32wbxx_ll_tim.c
  • IS_LL_TIM_ENCODERMODE : stm32wbxx_ll_tim.c
  • IS_LL_TIM_IC_FILTER : stm32wbxx_ll_tim.c
  • IS_LL_TIM_IC_POLARITY : stm32wbxx_ll_tim.c
  • IS_LL_TIM_IC_POLARITY_ENCODER : stm32wbxx_ll_tim.c
  • IS_LL_TIM_ICPSC : stm32wbxx_ll_tim.c
  • IS_LL_TIM_LOCK_LEVEL : stm32wbxx_ll_tim.c
  • IS_LL_TIM_OCIDLESTATE : stm32wbxx_ll_tim.c
  • IS_LL_TIM_OCMODE : stm32wbxx_ll_tim.c
  • IS_LL_TIM_OCPOLARITY : stm32wbxx_ll_tim.c
  • IS_LL_TIM_OCSTATE : stm32wbxx_ll_tim.c
  • IS_LL_TIM_OSSI_STATE : stm32wbxx_ll_tim.c
  • IS_LL_TIM_OSSR_STATE : stm32wbxx_ll_tim.c
  • IS_LL_USART_BAUDRATE : stm32wbxx_ll_usart.c
  • IS_LL_USART_BRR_MAX : stm32wbxx_ll_usart.c
  • IS_LL_USART_BRR_MIN : stm32wbxx_ll_usart.c
  • IS_LL_USART_CLOCKOUTPUT : stm32wbxx_ll_usart.c
  • IS_LL_USART_CLOCKPHASE : stm32wbxx_ll_usart.c
  • IS_LL_USART_CLOCKPOLARITY : stm32wbxx_ll_usart.c
  • IS_LL_USART_DATAWIDTH : stm32wbxx_ll_usart.c
  • IS_LL_USART_DIRECTION : stm32wbxx_ll_usart.c
  • IS_LL_USART_HWCONTROL : stm32wbxx_ll_usart.c
  • IS_LL_USART_LASTBITCLKOUTPUT : stm32wbxx_ll_usart.c
  • IS_LL_USART_OVERSAMPLING : stm32wbxx_ll_usart.c
  • IS_LL_USART_PARITY : stm32wbxx_ll_usart.c
  • IS_LL_USART_PRESCALER : stm32wbxx_ll_usart.c
  • IS_LL_USART_STOPBITS : stm32wbxx_ll_usart.c
  • IS_LL_UTILS_APB1_DIV : stm32wbxx_ll_utils.c
  • IS_LL_UTILS_APB2_DIV : stm32wbxx_ll_utils.c
  • IS_LL_UTILS_HSE_BYPASS : stm32wbxx_ll_utils.c
  • IS_LL_UTILS_PLL_FREQUENCY : stm32wbxx_ll_utils.c
  • IS_LL_UTILS_PLLM_VALUE : stm32wbxx_ll_utils.c
  • IS_LL_UTILS_PLLN_VALUE : stm32wbxx_ll_utils.c
  • IS_LL_UTILS_PLLR_VALUE : stm32wbxx_ll_utils.c
  • IS_LL_UTILS_PLLVCO_INPUT : stm32wbxx_ll_utils.c
  • IS_LL_UTILS_PLLVCO_OUTPUT : stm32wbxx_ll_utils.c
  • IS_LL_UTILS_SYSCLK_DIV : stm32wbxx_ll_utils.c
  • IS_LPTIM_AUTORELOAD : stm32wbxx_hal_lptim.h
  • IS_LPTIM_CLOCK_POLARITY : stm32wbxx_hal_lptim.h
  • IS_LPTIM_CLOCK_PRESCALER : stm32wbxx_hal_lptim.h
  • IS_LPTIM_CLOCK_PRESCALERDIV1 : stm32wbxx_hal_lptim.h
  • IS_LPTIM_CLOCK_SAMPLE_TIME : stm32wbxx_hal_lptim.h
  • IS_LPTIM_CLOCK_SOURCE : stm32wbxx_hal_lptim.h
  • IS_LPTIM_COMPARE : stm32wbxx_hal_lptim.h
  • IS_LPTIM_COUNTER_SOURCE : stm32wbxx_hal_lptim.h
  • IS_LPTIM_EXT_TRG_POLARITY : stm32wbxx_hal_lptim.h
  • IS_LPTIM_INPUT1_SOURCE : stm32wbxx_hal_lptim.h
  • IS_LPTIM_INPUT2_SOURCE : stm32wbxx_hal_lptim.h
  • IS_LPTIM_OUTPUT_POLARITY : stm32wbxx_hal_lptim.h
  • IS_LPTIM_PERIOD : stm32wbxx_hal_lptim.h
  • IS_LPTIM_PULSE : stm32wbxx_hal_lptim.h
  • IS_LPTIM_TRG_SOURCE : stm32wbxx_hal_lptim.h
  • IS_LPTIM_TRIG_SAMPLE_TIME : stm32wbxx_hal_lptim.h
  • IS_LPTIM_UPDATE_MODE : stm32wbxx_hal_lptim.h
  • IS_LPUART_STOPBITS : stm32wbxx_hal_uart.h
  • IS_MPU_ACCESS_BUFFERABLE : stm32wbxx_hal_cortex.h
  • IS_MPU_ACCESS_CACHEABLE : stm32wbxx_hal_cortex.h
  • IS_MPU_ACCESS_SHAREABLE : stm32wbxx_hal_cortex.h
  • IS_MPU_INSTRUCTION_ACCESS : stm32wbxx_hal_cortex.h
  • IS_MPU_REGION_ENABLE : stm32wbxx_hal_cortex.h
  • IS_MPU_REGION_NUMBER : stm32wbxx_hal_cortex.h
  • IS_MPU_REGION_PERMISSION_ATTRIBUTE : stm32wbxx_hal_cortex.h
  • IS_MPU_REGION_SIZE : stm32wbxx_hal_cortex.h
  • IS_MPU_SUB_REGION_DISABLE : stm32wbxx_hal_cortex.h
  • IS_MPU_TEX_LEVEL : stm32wbxx_hal_cortex.h
  • IS_NVIC_DEVICE_IRQ : stm32wbxx_hal_cortex.h
  • IS_NVIC_PREEMPTION_PRIORITY : stm32wbxx_hal_cortex.h
  • IS_NVIC_PRIORITY_GROUP : stm32wbxx_hal_cortex.h
  • IS_NVIC_SUB_PRIORITY : stm32wbxx_hal_cortex.h
  • IS_OB_BOOT_REGION : stm32wbxx_hal_flash.h
  • IS_OB_BOOT_VECTOR_ADDR : stm32wbxx_hal_flash.h
  • IS_OB_IPCC_BUF_ADDR : stm32wbxx_hal_flash.h
  • IS_OB_PCROP_CONFIG : stm32wbxx_hal_flash.h
  • IS_OB_RDP_LEVEL : stm32wbxx_hal_flash.h
  • IS_OB_SBRSA_START_ADDR : stm32wbxx_hal_flash.h
  • IS_OB_SECURE_CONFIG : stm32wbxx_hal_flash.h
  • IS_OB_SECURE_MODE : stm32wbxx_hal_flash.h
  • IS_OB_SFSA_START_ADDR : stm32wbxx_hal_flash.h
  • IS_OB_SNBRSA_START_ADDR : stm32wbxx_hal_flash.h
  • IS_OB_USER_AGC_TRIMMING : stm32wbxx_hal_flash.h
  • IS_OB_USER_BOR_LEVEL : stm32wbxx_hal_flash.h
  • IS_OB_USER_CONFIG : stm32wbxx_hal_flash.h
  • IS_OB_USER_TYPE : stm32wbxx_hal_flash.h
  • IS_OB_WRPAREA : stm32wbxx_hal_flash.h
  • IS_OPTIONBYTE : stm32wbxx_hal_flash.h
  • IS_PWR_BATTERY_CHARGING : stm32wbxx_hal_pwr_ex.h
  • IS_PWR_BATTERY_RESISTOR_SELECT : stm32wbxx_hal_pwr_ex.h
  • IS_PWR_CORE : stm32wbxx_hal_pwr_ex.h
  • IS_PWR_CORE_HOLD_RELEASE : stm32wbxx_hal_pwr_ex.h
  • IS_PWR_FLASH_POWERDOWN : stm32wbxx_hal_pwr_ex.h
  • IS_PWR_GPIO : stm32wbxx_hal_pwr_ex.h
  • IS_PWR_GPIO_BIT_NUMBER : stm32wbxx_hal_pwr_ex.h
  • IS_PWR_PVD_LEVEL : stm32wbxx_hal_pwr.h
  • IS_PWR_PVD_MODE : stm32wbxx_hal_pwr.h
  • IS_PWR_PVM_MODE : stm32wbxx_hal_pwr_ex.h
  • IS_PWR_PVM_TYPE : stm32wbxx_hal_pwr_ex.h
  • IS_PWR_REGULATOR : stm32wbxx_hal_pwr.h
  • IS_PWR_SLEEP_ENTRY : stm32wbxx_hal_pwr.h
  • IS_PWR_SMPS_MODE : stm32wbxx_hal_pwr_ex.h
  • IS_PWR_SMPS_OUTPUT_VOLTAGE : stm32wbxx_hal_pwr_ex.h
  • IS_PWR_SMPS_STARTUP_CURRENT : stm32wbxx_hal_pwr_ex.h
  • IS_PWR_STOP_ENTRY : stm32wbxx_hal_pwr.h
  • IS_PWR_VOLTAGE_SCALING_RANGE : stm32wbxx_hal_pwr_ex.h
  • IS_PWR_WAKEUP_PIN : stm32wbxx_hal_pwr_ex.h
  • IS_PWR_WAKEUP_PIN_POLARITY : stm32wbxx_hal_pwr_ex.h
  • IS_QSPI_ADDRESS_MODE : stm32wbxx_hal_qspi.h
  • IS_QSPI_ADDRESS_SIZE : stm32wbxx_hal_qspi.h
  • IS_QSPI_ALTERNATE_BYTES_MODE : stm32wbxx_hal_qspi.h
  • IS_QSPI_ALTERNATE_BYTES_SIZE : stm32wbxx_hal_qspi.h
  • IS_QSPI_AUTOMATIC_STOP : stm32wbxx_hal_qspi.h
  • IS_QSPI_CLOCK_MODE : stm32wbxx_hal_qspi.h
  • IS_QSPI_CLOCK_PRESCALER : stm32wbxx_hal_qspi.h
  • IS_QSPI_CS_HIGH_TIME : stm32wbxx_hal_qspi.h
  • IS_QSPI_DATA_MODE : stm32wbxx_hal_qspi.h
  • IS_QSPI_DDR_MODE : stm32wbxx_hal_qspi.h
  • IS_QSPI_DUMMY_CYCLES : stm32wbxx_hal_qspi.h
  • IS_QSPI_FIFO_THRESHOLD : stm32wbxx_hal_qspi.h
  • IS_QSPI_FLASH_SIZE : stm32wbxx_hal_qspi.h
  • IS_QSPI_FUNCTIONAL_MODE : stm32wbxx_hal_qspi.c
  • IS_QSPI_INSTRUCTION : stm32wbxx_hal_qspi.h
  • IS_QSPI_INSTRUCTION_MODE : stm32wbxx_hal_qspi.h
  • IS_QSPI_INTERVAL : stm32wbxx_hal_qspi.h
  • IS_QSPI_MATCH_MODE : stm32wbxx_hal_qspi.h
  • IS_QSPI_SIOO_MODE : stm32wbxx_hal_qspi.h
  • IS_QSPI_SSHIFT : stm32wbxx_hal_qspi.h
  • IS_QSPI_STATUS_BYTES_SIZE : stm32wbxx_hal_qspi.h
  • IS_QSPI_TIMEOUT_ACTIVATION : stm32wbxx_hal_qspi.h
  • IS_QSPI_TIMEOUT_PERIOD : stm32wbxx_hal_qspi.h
  • IS_RCC_ADCCLKSOURCE : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_CLOCKTYPE : stm32wbxx_hal_rcc.h
  • IS_RCC_CRS_ERRORLIMIT : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_CRS_FREQERRORDIR : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_CRS_HSI48CALIBRATION : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_CRS_RELOADVALUE : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_CRS_SYNC_DIV : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_CRS_SYNC_POLARITY : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_CRS_SYNC_SOURCE : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_HCLKx : stm32wbxx_hal_rcc.h
  • IS_RCC_HSE : stm32wbxx_hal_rcc.h
  • IS_RCC_HSI : stm32wbxx_hal_rcc.h
  • IS_RCC_HSI48 : stm32wbxx_hal_rcc.h
  • IS_RCC_HSI_CALIBRATION_VALUE : stm32wbxx_hal_rcc.h
  • IS_RCC_I2C1CLKSOURCE : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_I2C3CLKSOURCE : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_LPTIM1CLK : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_LPTIM2CLK : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_LPUART1CLKSOURCE : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_LSCO : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_LSCOSOURCE : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_LSE : stm32wbxx_hal_rcc.h
  • IS_RCC_LSE_DRIVE : stm32wbxx_hal_rcc.h
  • IS_RCC_LSI : stm32wbxx_hal_rcc.h
  • IS_RCC_LSI2_CALIBRATION_VALUE : stm32wbxx_hal_rcc.h
  • IS_RCC_MCO : stm32wbxx_hal_rcc.h
  • IS_RCC_MCO1SOURCE : stm32wbxx_hal_rcc.h
  • IS_RCC_MCO2SOURCE : stm32wbxx_hal_rcc.h
  • IS_RCC_MCO3SOURCE : stm32wbxx_hal_rcc.h
  • IS_RCC_MCODIV : stm32wbxx_hal_rcc.h
  • IS_RCC_MSI : stm32wbxx_hal_rcc.h
  • IS_RCC_MSI_CLOCK_RANGE : stm32wbxx_hal_rcc.h
  • IS_RCC_MSICALIBRATION_VALUE : stm32wbxx_hal_rcc.h
  • IS_RCC_OSCILLATORTYPE : stm32wbxx_hal_rcc.h
  • IS_RCC_PCLKx : stm32wbxx_hal_rcc.h
  • IS_RCC_PERIPHCLOCK : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_PLL : stm32wbxx_hal_rcc.h
  • IS_RCC_PLLM_VALUE : stm32wbxx_hal_rcc.h
  • IS_RCC_PLLN_VALUE : stm32wbxx_hal_rcc.h
  • IS_RCC_PLLP_VALUE : stm32wbxx_hal_rcc.h
  • IS_RCC_PLLQ_VALUE : stm32wbxx_hal_rcc.h
  • IS_RCC_PLLR_VALUE : stm32wbxx_hal_rcc.h
  • IS_RCC_PLLSAI1CLOCKOUT_VALUE : stm32wbxx_hal_rcc.h
  • IS_RCC_PLLSAI1N_VALUE : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_PLLSAI1P_VALUE : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_PLLSAI1Q_VALUE : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_PLLSAI1R_VALUE : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_PLLSOURCE : stm32wbxx_hal_rcc.h
  • IS_RCC_RFWKPCLKSOURCE : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_RNGCLKSOURCE : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_RTCCLKSOURCE : stm32wbxx_hal_rcc.h
  • IS_RCC_SAI1CLK : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_SMPSCLKDIV : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_SMPSCLKSOURCE : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_STOP_WAKEUPCLOCK : stm32wbxx_hal_rcc.h
  • IS_RCC_SYSCLKSOURCE : stm32wbxx_hal_rcc.h
  • IS_RCC_TRIMOSC : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_USART1CLKSOURCE : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_USBCLKSOURCE : stm32wbxx_hal_rcc_ex.h
  • IS_RNG_CED : stm32wbxx_hal_rng.h
  • IS_RNG_FLAG : stm32wbxx_hal_rng.h
  • IS_RNG_IT : stm32wbxx_hal_rng.h
  • IS_RTC_ALARM : stm32wbxx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_DATE : stm32wbxx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_SEL : stm32wbxx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY : stm32wbxx_hal_rtc.h
  • IS_RTC_ALARM_MASK : stm32wbxx_hal_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_MASK : stm32wbxx_hal_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_VALUE : stm32wbxx_hal_rtc.h
  • IS_RTC_ASYNCH_PREDIV : stm32wbxx_hal_rtc.h
  • IS_RTC_BKP : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_CALIB_OUTPUT : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_DATE : stm32wbxx_hal_rtc.h
  • IS_RTC_DAYLIGHT_SAVING : stm32wbxx_hal_rtc.h
  • IS_RTC_FORMAT : stm32wbxx_hal_rtc.h
  • IS_RTC_HOUR12 : stm32wbxx_hal_rtc.h
  • IS_RTC_HOUR24 : stm32wbxx_hal_rtc.h
  • IS_RTC_HOUR_FORMAT : stm32wbxx_hal_rtc.h
  • IS_RTC_HOURFORMAT12 : stm32wbxx_hal_rtc.h
  • IS_RTC_MINUTES : stm32wbxx_hal_rtc.h
  • IS_RTC_MONTH : stm32wbxx_hal_rtc.h
  • IS_RTC_OUTPUT : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_OUTPUT_POL : stm32wbxx_hal_rtc.h
  • IS_RTC_OUTPUT_REMAP : stm32wbxx_hal_rtc.h
  • IS_RTC_OUTPUT_TYPE : stm32wbxx_hal_rtc.h
  • IS_RTC_SECONDS : stm32wbxx_hal_rtc.h
  • IS_RTC_SHIFT_ADD1S : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_SHIFT_SUBFS : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_MINUS : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_PERIOD : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_PLUS : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_STORE_OPERATION : stm32wbxx_hal_rtc.h
  • IS_RTC_SYNCH_PREDIV : stm32wbxx_hal_rtc.h
  • IS_RTC_TAMPER : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_TAMPER_ERASE_MODE : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_TAMPER_FILTER : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_TAMPER_INTERRUPT : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_TAMPER_MASKFLAG_STATE : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_TAMPER_PRECHARGE_DURATION : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_TAMPER_PULLUP_STATE : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_TAMPER_SAMPLING_FREQ : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TRIGGER : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_TIMESTAMP_PIN : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_WAKEUP_CLOCK : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_WAKEUP_COUNTER : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_WEEKDAY : stm32wbxx_hal_rtc.h
  • IS_RTC_YEAR : stm32wbxx_hal_rtc.h
  • IS_SAI_AUDIO_FREQUENCY : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_ACTIVE_FRAME : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_CLOCK_STROBING : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_COMPANDING_MODE : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_DATASIZE : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_FIFO_THRESHOLD : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_FIRST_BIT : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_FIRSTBIT_OFFSET : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_FRAME_LENGTH : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_FS_DEFINITION : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_FS_OFFSET : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_FS_POLARITY : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_MASTER_DIVIDER : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_MCK_OUTPUT : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_MCK_OVERSAMPLING : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_MODE : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_MUTE_COUNTER : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_MUTE_VALUE : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_NODIVIDER : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_OUTPUT_DRIVE : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_PROTOCOL : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_SLOT_NUMBER : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_SLOT_SIZE : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_SYNCEXT : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_SYNCHRO : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_TRISTATE_MANAGEMENT : stm32wbxx_hal_sai.h
  • IS_SAI_MONO_STEREO_MODE : stm32wbxx_hal_sai.h
  • IS_SAI_PDM_CLOCK_ENABLE : stm32wbxx_hal_sai.h
  • IS_SAI_PDM_MIC_DELAY : stm32wbxx_hal_sai_ex.h
  • IS_SAI_PDM_MIC_PAIRS_NUMBER : stm32wbxx_hal_sai.h
  • IS_SAI_PROTOCOL_DATASIZE : stm32wbxx_hal_sai.h
  • IS_SAI_SLOT_ACTIVE : stm32wbxx_hal_sai.h
  • IS_SAI_SUPPORTED_PROTOCOL : stm32wbxx_hal_sai.h
  • IS_SMARTCARD_ADVFEATURE_DATAINV : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_DMAONRXERROR : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_INIT : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_MSBFIRST : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_RXINV : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_SWAP : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_TXINV : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_AUTORETRY_COUNT : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_BAUDRATE : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_BLOCKLENGTH : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_CLOCKPRESCALER : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_FIFOMODE_STATE : stm32wbxx_hal_smartcard_ex.h
  • IS_SMARTCARD_LASTBIT : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_MODE : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_NACK : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_ONE_BIT_SAMPLE : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_OVERRUN : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_PARITY : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_PHASE : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_POLARITY : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_REQUEST_PARAMETER : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_RXFIFO_THRESHOLD : stm32wbxx_hal_smartcard_ex.h
  • IS_SMARTCARD_STOPBITS : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_TIMEOUT : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_TIMEOUT_VALUE : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_TRANSMISSION_COMPLETION : stm32wbxx_hal_smartcard_ex.h
  • IS_SMARTCARD_TXFIFO_THRESHOLD : stm32wbxx_hal_smartcard_ex.h
  • IS_SMARTCARD_WORD_LENGTH : stm32wbxx_hal_smartcard.h
  • IS_SMBUS_ADDRESSING_MODE : stm32wbxx_hal_smbus.h
  • IS_SMBUS_ANALOG_FILTER : stm32wbxx_hal_smbus.h
  • IS_SMBUS_DIGITAL_FILTER : stm32wbxx_hal_smbus.h
  • IS_SMBUS_DUAL_ADDRESS : stm32wbxx_hal_smbus.h
  • IS_SMBUS_GENERAL_CALL : stm32wbxx_hal_smbus.h
  • IS_SMBUS_NO_STRETCH : stm32wbxx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS1 : stm32wbxx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS2 : stm32wbxx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS2_MASK : stm32wbxx_hal_smbus.h
  • IS_SMBUS_PEC : stm32wbxx_hal_smbus.h
  • IS_SMBUS_PERIPHERAL_MODE : stm32wbxx_hal_smbus.h
  • IS_SMBUS_TRANSFER_MODE : stm32wbxx_hal_smbus.h
  • IS_SMBUS_TRANSFER_OPTIONS_REQUEST : stm32wbxx_hal_smbus.h
  • IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST : stm32wbxx_hal_smbus.h
  • IS_SMBUS_TRANSFER_REQUEST : stm32wbxx_hal_smbus.h
  • IS_SPI_BAUDRATE_PRESCALER : stm32wbxx_hal_spi.h
  • IS_SPI_CPHA : stm32wbxx_hal_spi.h
  • IS_SPI_CPOL : stm32wbxx_hal_spi.h
  • IS_SPI_CRC_CALCULATION : stm32wbxx_hal_spi.h
  • IS_SPI_CRC_LENGTH : stm32wbxx_hal_spi.h
  • IS_SPI_CRC_POLYNOMIAL : stm32wbxx_hal_spi.h
  • IS_SPI_DATASIZE : stm32wbxx_hal_spi.h
  • IS_SPI_DIRECTION : stm32wbxx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES : stm32wbxx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES_OR_1LINE : stm32wbxx_hal_spi.h
  • IS_SPI_DMA_HANDLE : stm32wbxx_hal_spi.h
  • IS_SPI_FIRST_BIT : stm32wbxx_hal_spi.h
  • IS_SPI_MODE : stm32wbxx_hal_spi.h
  • IS_SPI_NSS : stm32wbxx_hal_spi.h
  • IS_SPI_NSSP : stm32wbxx_hal_spi.h
  • IS_SPI_TIMODE : stm32wbxx_hal_spi.h
  • IS_SYSCFG_FASTMODEPLUS : stm32wbxx_hal.h
  • IS_SYSCFG_FPU_INTERRUPT : stm32wbxx_hal.h
  • IS_SYSCFG_SECURITY_ACCESS : stm32wbxx_hal.h
  • IS_SYSCFG_SRAM2WRP_PAGE : stm32wbxx_hal.h
  • IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE : stm32wbxx_hal.h
  • IS_SYSCFG_VREFBUF_TRIMMING : stm32wbxx_hal.h
  • IS_SYSCFG_VREFBUF_VOLTAGE_SCALE : stm32wbxx_hal.h
  • IS_SYSTICK_CLK_SOURCE : stm32wbxx_hal_cortex.h
  • IS_TICKFREQ : stm32wbxx_hal.h
  • IS_TIM_AUTOMATIC_OUTPUT_STATE : stm32wbxx_hal_tim.h
  • IS_TIM_AUTORELOAD_PRELOAD : stm32wbxx_hal_tim.h
  • IS_TIM_BREAK2_POLARITY : stm32wbxx_hal_tim.h
  • IS_TIM_BREAK2_STATE : stm32wbxx_hal_tim.h
  • IS_TIM_BREAK_FILTER : stm32wbxx_hal_tim.h
  • IS_TIM_BREAK_POLARITY : stm32wbxx_hal_tim.h
  • IS_TIM_BREAK_STATE : stm32wbxx_hal_tim.h
  • IS_TIM_BREAK_SYSTEM : stm32wbxx_hal_tim.h
  • IS_TIM_BREAKINPUT : stm32wbxx_hal_tim_ex.h
  • IS_TIM_BREAKINPUTSOURCE : stm32wbxx_hal_tim_ex.h
  • IS_TIM_BREAKINPUTSOURCE_POLARITY : stm32wbxx_hal_tim_ex.h
  • IS_TIM_BREAKINPUTSOURCE_STATE : stm32wbxx_hal_tim_ex.h
  • IS_TIM_CHANNELS : stm32wbxx_hal_tim.h
  • IS_TIM_CLEARINPUT_FILTER : stm32wbxx_hal_tim.h
  • IS_TIM_CLEARINPUT_POLARITY : stm32wbxx_hal_tim.h
  • IS_TIM_CLEARINPUT_PRESCALER : stm32wbxx_hal_tim.h
  • IS_TIM_CLEARINPUT_SOURCE : stm32wbxx_hal_tim.h
  • IS_TIM_CLOCKDIVISION_DIV : stm32wbxx_hal_tim.h
  • IS_TIM_CLOCKFILTER : stm32wbxx_hal_tim.h
  • IS_TIM_CLOCKPOLARITY : stm32wbxx_hal_tim.h
  • IS_TIM_CLOCKPRESCALER : stm32wbxx_hal_tim.h
  • IS_TIM_CLOCKSOURCE : stm32wbxx_hal_tim.h
  • IS_TIM_COMPLEMENTARY_CHANNELS : stm32wbxx_hal_tim.h
  • IS_TIM_COUNTER_MODE : stm32wbxx_hal_tim.h
  • IS_TIM_DEADTIME : stm32wbxx_hal_tim.h
  • IS_TIM_DMA_BASE : stm32wbxx_hal_tim.h
  • IS_TIM_DMA_LENGTH : stm32wbxx_hal_tim.h
  • IS_TIM_DMA_SOURCE : stm32wbxx_hal_tim.h
  • IS_TIM_ENCODER_MODE : stm32wbxx_hal_tim.h
  • IS_TIM_ENCODERINPUT_POLARITY : stm32wbxx_hal_tim.h
  • IS_TIM_EVENT_SOURCE : stm32wbxx_hal_tim.h
  • IS_TIM_FAST_STATE : stm32wbxx_hal_tim.h
  • IS_TIM_GROUPCH5 : stm32wbxx_hal_tim.h
  • IS_TIM_IC_FILTER : stm32wbxx_hal_tim.h
  • IS_TIM_IC_POLARITY : stm32wbxx_hal_tim.h
  • IS_TIM_IC_PRESCALER : stm32wbxx_hal_tim.h
  • IS_TIM_IC_SELECTION : stm32wbxx_hal_tim.h
  • IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION : stm32wbxx_hal_tim.h
  • IS_TIM_LOCK_LEVEL : stm32wbxx_hal_tim.h
  • IS_TIM_MSM_STATE : stm32wbxx_hal_tim.h
  • IS_TIM_OC_MODE : stm32wbxx_hal_tim.h
  • IS_TIM_OC_POLARITY : stm32wbxx_hal_tim.h
  • IS_TIM_OCIDLE_STATE : stm32wbxx_hal_tim.h
  • IS_TIM_OCN_POLARITY : stm32wbxx_hal_tim.h
  • IS_TIM_OCNIDLE_STATE : stm32wbxx_hal_tim.h
  • IS_TIM_OPM_CHANNELS : stm32wbxx_hal_tim.h
  • IS_TIM_OPM_MODE : stm32wbxx_hal_tim.h
  • IS_TIM_OSSI_STATE : stm32wbxx_hal_tim.h
  • IS_TIM_OSSR_STATE : stm32wbxx_hal_tim.h
  • IS_TIM_PWM_MODE : stm32wbxx_hal_tim.h
  • IS_TIM_REMAP : stm32wbxx_hal_tim_ex.h
  • IS_TIM_SLAVE_MODE : stm32wbxx_hal_tim.h
  • IS_TIM_SLAVEMODE_TRIGGER_ENABLED : stm32wbxx_hal_tim.h
  • IS_TIM_TI1SELECTION : stm32wbxx_hal_tim.h
  • IS_TIM_TRGO2_SOURCE : stm32wbxx_hal_tim.h
  • IS_TIM_TRGO_SOURCE : stm32wbxx_hal_tim.h
  • IS_TIM_TRIGGER_SELECTION : stm32wbxx_hal_tim.h
  • IS_TIM_TRIGGERFILTER : stm32wbxx_hal_tim.h
  • IS_TIM_TRIGGERPOLARITY : stm32wbxx_hal_tim.h
  • IS_TIM_TRIGGERPRESCALER : stm32wbxx_hal_tim.h
  • IS_TIMESTAMP_EDGE : stm32wbxx_hal_rtc_ex.h
  • IS_TRANSFER_MODE : stm32wbxx_hal_i2c.h
  • IS_TRANSFER_REQUEST : stm32wbxx_hal_i2c.h
  • IS_TSC_ACQ_MODE : stm32wbxx_hal_tsc.h
  • IS_TSC_CTPH : stm32wbxx_hal_tsc.h
  • IS_TSC_CTPL : stm32wbxx_hal_tsc.h
  • IS_TSC_GROUP : stm32wbxx_hal_tsc.h
  • IS_TSC_GROUP_INDEX : stm32wbxx_hal_tsc.h
  • IS_TSC_IODEF : stm32wbxx_hal_tsc.h
  • IS_TSC_MCE_IT : stm32wbxx_hal_tsc.h
  • IS_TSC_MCV : stm32wbxx_hal_tsc.h
  • IS_TSC_PG_PRESC : stm32wbxx_hal_tsc.h
  • IS_TSC_SS : stm32wbxx_hal_tsc.h
  • IS_TSC_SS_PRESC : stm32wbxx_hal_tsc.h
  • IS_TSC_SSD : stm32wbxx_hal_tsc.h
  • IS_TSC_SYNC_POL : stm32wbxx_hal_tsc.h
  • IS_UART_ADDRESSLENGTH_DETECT : stm32wbxx_hal_uart_ex.h
  • IS_UART_ADVFEATURE_AUTOBAUDRATE : stm32wbxx_hal_uart.h
  • IS_UART_ADVFEATURE_AUTOBAUDRATEMODE : stm32wbxx_hal_uart.h
  • IS_UART_ADVFEATURE_DATAINV : stm32wbxx_hal_uart.h
  • IS_UART_ADVFEATURE_DMAONRXERROR : stm32wbxx_hal_uart.h
  • IS_UART_ADVFEATURE_INIT : stm32wbxx_hal_uart.h
  • IS_UART_ADVFEATURE_MSBFIRST : stm32wbxx_hal_uart.h
  • IS_UART_ADVFEATURE_RXINV : stm32wbxx_hal_uart.h
  • IS_UART_ADVFEATURE_STOPMODE : stm32wbxx_hal_uart.h
  • IS_UART_ADVFEATURE_SWAP : stm32wbxx_hal_uart.h
  • IS_UART_ADVFEATURE_TXINV : stm32wbxx_hal_uart.h
  • IS_UART_ASSERTIONTIME : stm32wbxx_hal_uart.h
  • IS_UART_BAUDRATE : stm32wbxx_hal_uart.h
  • IS_UART_DE_POLARITY : stm32wbxx_hal_uart.h
  • IS_UART_DEASSERTIONTIME : stm32wbxx_hal_uart.h
  • IS_UART_DMA_RX : stm32wbxx_hal_uart.h
  • IS_UART_DMA_TX : stm32wbxx_hal_uart.h
  • IS_UART_HALF_DUPLEX : stm32wbxx_hal_uart.h
  • IS_UART_HARDWARE_FLOW_CONTROL : stm32wbxx_hal_uart.h
  • IS_UART_LIN : stm32wbxx_hal_uart.h
  • IS_UART_LIN_BREAK_DETECT_LENGTH : stm32wbxx_hal_uart.h
  • IS_UART_MODE : stm32wbxx_hal_uart.h
  • IS_UART_MUTE_MODE : stm32wbxx_hal_uart.h
  • IS_UART_ONE_BIT_SAMPLE : stm32wbxx_hal_uart.h
  • IS_UART_OVERRUN : stm32wbxx_hal_uart.h
  • IS_UART_OVERSAMPLING : stm32wbxx_hal_uart.h
  • IS_UART_PARITY : stm32wbxx_hal_uart.h
  • IS_UART_PRESCALER : stm32wbxx_hal_uart.h
  • IS_UART_RECEIVER_TIMEOUT : stm32wbxx_hal_uart.h
  • IS_UART_RECEIVER_TIMEOUT_VALUE : stm32wbxx_hal_uart.h
  • IS_UART_REQUEST_PARAMETER : stm32wbxx_hal_uart.h
  • IS_UART_RXFIFO_THRESHOLD : stm32wbxx_hal_uart_ex.h
  • IS_UART_STATE : stm32wbxx_hal_uart.h
  • IS_UART_STOPBITS : stm32wbxx_hal_uart.h
  • IS_UART_TXFIFO_THRESHOLD : stm32wbxx_hal_uart_ex.h
  • IS_UART_WAKEUP_SELECTION : stm32wbxx_hal_uart.h
  • IS_UART_WAKEUPMETHOD : stm32wbxx_hal_uart.h
  • IS_UART_WORD_LENGTH : stm32wbxx_hal_uart_ex.h
  • IS_USART_BAUDRATE : stm32wbxx_hal_usart.h
  • IS_USART_CLOCK : stm32wbxx_hal_usart.h
  • IS_USART_FIFO_MODE_STATE : stm32wbxx_hal_usart_ex.h
  • IS_USART_LASTBIT : stm32wbxx_hal_usart.h
  • IS_USART_MODE : stm32wbxx_hal_usart.h
  • IS_USART_NSS : stm32wbxx_hal_usart_ex.h
  • IS_USART_OVERSAMPLING : stm32wbxx_hal_usart.h
  • IS_USART_PARITY : stm32wbxx_hal_usart.h
  • IS_USART_PHASE : stm32wbxx_hal_usart.h
  • IS_USART_POLARITY : stm32wbxx_hal_usart.h
  • IS_USART_PRESCALER : stm32wbxx_hal_usart.h
  • IS_USART_REQUEST_PARAMETER : stm32wbxx_hal_usart.h
  • IS_USART_RXFIFO_THRESHOLD : stm32wbxx_hal_usart_ex.h
  • IS_USART_SLAVEMODE : stm32wbxx_hal_usart_ex.h
  • IS_USART_STOPBITS : stm32wbxx_hal_usart.h
  • IS_USART_TXFIFO_THRESHOLD : stm32wbxx_hal_usart_ex.h
  • IS_USART_WORD_LENGTH : stm32wbxx_hal_usart_ex.h
  • IS_WWDG_COUNTER : stm32wbxx_hal_wwdg.h
  • IS_WWDG_EWI_MODE : stm32wbxx_hal_wwdg.h
  • IS_WWDG_PRESCALER : stm32wbxx_hal_wwdg.h
  • IS_WWDG_WINDOW : stm32wbxx_hal_wwdg.h
  • IWDG_DISABLE_WRITE_ACCESS : stm32wbxx_hal_iwdg.h
  • IWDG_ENABLE_WRITE_ACCESS : stm32wbxx_hal_iwdg.h
  • IWDG_KEY_ENABLE : stm32wbxx_hal_iwdg.h
  • IWDG_KEY_RELOAD : stm32wbxx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_DISABLE : stm32wbxx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_ENABLE : stm32wbxx_hal_iwdg.h
  • IWDG_PRESCALER_128 : stm32wbxx_hal_iwdg.h
  • IWDG_PRESCALER_16 : stm32wbxx_hal_iwdg.h
  • IWDG_PRESCALER_256 : stm32wbxx_hal_iwdg.h
  • IWDG_PRESCALER_32 : stm32wbxx_hal_iwdg.h
  • IWDG_PRESCALER_4 : stm32wbxx_hal_iwdg.h
  • IWDG_PRESCALER_64 : stm32wbxx_hal_iwdg.h
  • IWDG_PRESCALER_8 : stm32wbxx_hal_iwdg.h
  • IWDG_WINDOW_DISABLE : stm32wbxx_hal_iwdg.h
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
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  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- l -

  • LATENCY_TIMEOUT_VALUE : stm32wbxx_hal_rcc.c
  • LCD_BIAS_1_2 : stm32wbxx_hal_lcd.h
  • LCD_BIAS_1_3 : stm32wbxx_hal_lcd.h
  • LCD_BIAS_1_4 : stm32wbxx_hal_lcd.h
  • LCD_BLINKFREQUENCY_DIV1024 : stm32wbxx_hal_lcd.h
  • LCD_BLINKFREQUENCY_DIV128 : stm32wbxx_hal_lcd.h
  • LCD_BLINKFREQUENCY_DIV16 : stm32wbxx_hal_lcd.h
  • LCD_BLINKFREQUENCY_DIV256 : stm32wbxx_hal_lcd.h
  • LCD_BLINKFREQUENCY_DIV32 : stm32wbxx_hal_lcd.h
  • LCD_BLINKFREQUENCY_DIV512 : stm32wbxx_hal_lcd.h
  • LCD_BLINKFREQUENCY_DIV64 : stm32wbxx_hal_lcd.h
  • LCD_BLINKFREQUENCY_DIV8 : stm32wbxx_hal_lcd.h
  • LCD_BLINKMODE_ALLSEG_ALLCOM : stm32wbxx_hal_lcd.h
  • LCD_BLINKMODE_OFF : stm32wbxx_hal_lcd.h
  • LCD_BLINKMODE_SEG0_ALLCOM : stm32wbxx_hal_lcd.h
  • LCD_BLINKMODE_SEG0_COM0 : stm32wbxx_hal_lcd.h
  • LCD_CONTRASTLEVEL_0 : stm32wbxx_hal_lcd.h
  • LCD_CONTRASTLEVEL_1 : stm32wbxx_hal_lcd.h
  • LCD_CONTRASTLEVEL_2 : stm32wbxx_hal_lcd.h
  • LCD_CONTRASTLEVEL_3 : stm32wbxx_hal_lcd.h
  • LCD_CONTRASTLEVEL_4 : stm32wbxx_hal_lcd.h
  • LCD_CONTRASTLEVEL_5 : stm32wbxx_hal_lcd.h
  • LCD_CONTRASTLEVEL_6 : stm32wbxx_hal_lcd.h
  • LCD_CONTRASTLEVEL_7 : stm32wbxx_hal_lcd.h
  • LCD_DEADTIME_0 : stm32wbxx_hal_lcd.h
  • LCD_DEADTIME_1 : stm32wbxx_hal_lcd.h
  • LCD_DEADTIME_2 : stm32wbxx_hal_lcd.h
  • LCD_DEADTIME_3 : stm32wbxx_hal_lcd.h
  • LCD_DEADTIME_4 : stm32wbxx_hal_lcd.h
  • LCD_DEADTIME_5 : stm32wbxx_hal_lcd.h
  • LCD_DEADTIME_6 : stm32wbxx_hal_lcd.h
  • LCD_DEADTIME_7 : stm32wbxx_hal_lcd.h
  • LCD_DIVIDER_16 : stm32wbxx_hal_lcd.h
  • LCD_DIVIDER_17 : stm32wbxx_hal_lcd.h
  • LCD_DIVIDER_18 : stm32wbxx_hal_lcd.h
  • LCD_DIVIDER_19 : stm32wbxx_hal_lcd.h
  • LCD_DIVIDER_20 : stm32wbxx_hal_lcd.h
  • LCD_DIVIDER_21 : stm32wbxx_hal_lcd.h
  • LCD_DIVIDER_22 : stm32wbxx_hal_lcd.h
  • LCD_DIVIDER_23 : stm32wbxx_hal_lcd.h
  • LCD_DIVIDER_24 : stm32wbxx_hal_lcd.h
  • LCD_DIVIDER_25 : stm32wbxx_hal_lcd.h
  • LCD_DIVIDER_26 : stm32wbxx_hal_lcd.h
  • LCD_DIVIDER_27 : stm32wbxx_hal_lcd.h
  • LCD_DIVIDER_28 : stm32wbxx_hal_lcd.h
  • LCD_DIVIDER_29 : stm32wbxx_hal_lcd.h
  • LCD_DIVIDER_30 : stm32wbxx_hal_lcd.h
  • LCD_DIVIDER_31 : stm32wbxx_hal_lcd.h
  • LCD_DUTY_1_2 : stm32wbxx_hal_lcd.h
  • LCD_DUTY_1_3 : stm32wbxx_hal_lcd.h
  • LCD_DUTY_1_4 : stm32wbxx_hal_lcd.h
  • LCD_DUTY_1_8 : stm32wbxx_hal_lcd.h
  • LCD_DUTY_STATIC : stm32wbxx_hal_lcd.h
  • LCD_FLAG_ENS : stm32wbxx_hal_lcd.h
  • LCD_FLAG_FCRSF : stm32wbxx_hal_lcd.h
  • LCD_FLAG_RDY : stm32wbxx_hal_lcd.h
  • LCD_FLAG_SOF : stm32wbxx_hal_lcd.h
  • LCD_FLAG_UDD : stm32wbxx_hal_lcd.h
  • LCD_FLAG_UDR : stm32wbxx_hal_lcd.h
  • LCD_HIGHDRIVE_DISABLE : stm32wbxx_hal_lcd.h
  • LCD_HIGHDRIVE_ENABLE : stm32wbxx_hal_lcd.h
  • LCD_IT_SOF : stm32wbxx_hal_lcd.h
  • LCD_IT_UDD : stm32wbxx_hal_lcd.h
  • LCD_MUXSEGMENT_DISABLE : stm32wbxx_hal_lcd.h
  • LCD_MUXSEGMENT_ENABLE : stm32wbxx_hal_lcd.h
  • LCD_PRESCALER_1 : stm32wbxx_hal_lcd.h
  • LCD_PRESCALER_1024 : stm32wbxx_hal_lcd.h
  • LCD_PRESCALER_128 : stm32wbxx_hal_lcd.h
  • LCD_PRESCALER_16 : stm32wbxx_hal_lcd.h
  • LCD_PRESCALER_16384 : stm32wbxx_hal_lcd.h
  • LCD_PRESCALER_2 : stm32wbxx_hal_lcd.h
  • LCD_PRESCALER_2048 : stm32wbxx_hal_lcd.h
  • LCD_PRESCALER_256 : stm32wbxx_hal_lcd.h
  • LCD_PRESCALER_32 : stm32wbxx_hal_lcd.h
  • LCD_PRESCALER_32768 : stm32wbxx_hal_lcd.h
  • LCD_PRESCALER_4 : stm32wbxx_hal_lcd.h
  • LCD_PRESCALER_4096 : stm32wbxx_hal_lcd.h
  • LCD_PRESCALER_512 : stm32wbxx_hal_lcd.h
  • LCD_PRESCALER_64 : stm32wbxx_hal_lcd.h
  • LCD_PRESCALER_8 : stm32wbxx_hal_lcd.h
  • LCD_PRESCALER_8192 : stm32wbxx_hal_lcd.h
  • LCD_PULSEONDURATION_0 : stm32wbxx_hal_lcd.h
  • LCD_PULSEONDURATION_1 : stm32wbxx_hal_lcd.h
  • LCD_PULSEONDURATION_2 : stm32wbxx_hal_lcd.h
  • LCD_PULSEONDURATION_3 : stm32wbxx_hal_lcd.h
  • LCD_PULSEONDURATION_4 : stm32wbxx_hal_lcd.h
  • LCD_PULSEONDURATION_5 : stm32wbxx_hal_lcd.h
  • LCD_PULSEONDURATION_6 : stm32wbxx_hal_lcd.h
  • LCD_PULSEONDURATION_7 : stm32wbxx_hal_lcd.h
  • LCD_RAM_REGISTER0 : stm32wbxx_hal_lcd.h
  • LCD_RAM_REGISTER1 : stm32wbxx_hal_lcd.h
  • LCD_RAM_REGISTER10 : stm32wbxx_hal_lcd.h
  • LCD_RAM_REGISTER11 : stm32wbxx_hal_lcd.h
  • LCD_RAM_REGISTER12 : stm32wbxx_hal_lcd.h
  • LCD_RAM_REGISTER13 : stm32wbxx_hal_lcd.h
  • LCD_RAM_REGISTER14 : stm32wbxx_hal_lcd.h
  • LCD_RAM_REGISTER15 : stm32wbxx_hal_lcd.h
  • LCD_RAM_REGISTER2 : stm32wbxx_hal_lcd.h
  • LCD_RAM_REGISTER3 : stm32wbxx_hal_lcd.h
  • LCD_RAM_REGISTER4 : stm32wbxx_hal_lcd.h
  • LCD_RAM_REGISTER5 : stm32wbxx_hal_lcd.h
  • LCD_RAM_REGISTER6 : stm32wbxx_hal_lcd.h
  • LCD_RAM_REGISTER7 : stm32wbxx_hal_lcd.h
  • LCD_RAM_REGISTER8 : stm32wbxx_hal_lcd.h
  • LCD_RAM_REGISTER9 : stm32wbxx_hal_lcd.h
  • LCD_TIMEOUT_VALUE : stm32wbxx_hal_lcd.c
  • LCD_VOLTAGESOURCE_EXTERNAL : stm32wbxx_hal_lcd.h
  • LCD_VOLTAGESOURCE_INTERNAL : stm32wbxx_hal_lcd.h
  • LCD_WaitForSynchro() : stm32wbxx_hal_lcd.c
  • LL_ADC_AWD1 : stm32wbxx_ll_adc.h
  • LL_ADC_AWD2 : stm32wbxx_ll_adc.h
  • LL_ADC_AWD3 : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_ALL_CHANNELS_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_ALL_CHANNELS_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_ALL_CHANNELS_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CH_VBAT_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CH_VBAT_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CH_VBAT_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CH_VREFINT_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CH_VREFINT_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CH_VREFINT_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_0_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_0_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_0_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_10_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_10_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_10_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_11_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_11_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_11_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_12_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_12_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_12_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_13_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_13_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_13_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_14_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_14_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_14_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_15_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_15_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_15_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_16_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_16_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_16_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_17_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_17_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_17_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_18_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_18_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_18_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_1_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_1_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_1_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_2_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_2_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_2_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_3_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_3_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_3_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_4_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_4_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_4_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_5_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_5_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_5_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_6_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_6_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_6_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_7_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_7_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_7_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_8_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_8_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_8_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_9_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_9_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_9_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_DISABLE : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_THRESHOLD_HIGH : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_THRESHOLD_LOW : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_THRESHOLDS_HIGH_LOW : stm32wbxx_ll_adc.h
  • LL_ADC_BOTH_SINGLE_DIFF_ENDED : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_0 : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_1 : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_10 : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_11 : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_12 : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_13 : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_14 : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_15 : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_16 : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_17 : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_18 : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_2 : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_3 : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_4 : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_5 : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_6 : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_7 : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_8 : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_9 : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_TEMPSENSOR : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_VBAT : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_VREFINT : stm32wbxx_ll_adc.h
  • LL_ADC_ClearFlag_ADRDY() : stm32wbxx_ll_adc.h
  • LL_ADC_ClearFlag_AWD1() : stm32wbxx_ll_adc.h
  • LL_ADC_ClearFlag_AWD2() : stm32wbxx_ll_adc.h
  • LL_ADC_ClearFlag_AWD3() : stm32wbxx_ll_adc.h
  • LL_ADC_ClearFlag_EOC() : stm32wbxx_ll_adc.h
  • LL_ADC_ClearFlag_EOS() : stm32wbxx_ll_adc.h
  • LL_ADC_ClearFlag_EOSMP() : stm32wbxx_ll_adc.h
  • LL_ADC_ClearFlag_JEOC() : stm32wbxx_ll_adc.h
  • LL_ADC_ClearFlag_JEOS() : stm32wbxx_ll_adc.h
  • LL_ADC_ClearFlag_JQOVF() : stm32wbxx_ll_adc.h
  • LL_ADC_ClearFlag_OVR() : stm32wbxx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV1 : stm32wbxx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV10 : stm32wbxx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV12 : stm32wbxx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV128 : stm32wbxx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV16 : stm32wbxx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV2 : stm32wbxx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV256 : stm32wbxx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV32 : stm32wbxx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV4 : stm32wbxx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV6 : stm32wbxx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV64 : stm32wbxx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV8 : stm32wbxx_ll_adc.h
  • LL_ADC_CLOCK_SYNC_PCLK_DIV1 : stm32wbxx_ll_adc.h
  • LL_ADC_CLOCK_SYNC_PCLK_DIV2 : stm32wbxx_ll_adc.h
  • LL_ADC_CLOCK_SYNC_PCLK_DIV4 : stm32wbxx_ll_adc.h
  • LL_ADC_CommonDeInit() : stm32wbxx_ll_adc.c
  • LL_ADC_CommonInit() : stm32wbxx_ll_adc.c
  • LL_ADC_CommonStructInit() : stm32wbxx_ll_adc.c
  • LL_ADC_ConfigAnalogWDThresholds() : stm32wbxx_ll_adc.h
  • LL_ADC_ConfigOverSamplingRatioShift() : stm32wbxx_ll_adc.h
  • LL_ADC_DATA_ALIGN_LEFT : stm32wbxx_ll_adc.h
  • LL_ADC_DATA_ALIGN_RIGHT : stm32wbxx_ll_adc.h
  • LL_ADC_DeInit() : stm32wbxx_ll_adc.c
  • LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES : stm32wbxx_ll_adc.h
  • LL_ADC_DELAY_INTERNAL_REGUL_STAB_US : stm32wbxx_ll_adc.h
  • LL_ADC_DELAY_TEMPSENSOR_STAB_US : stm32wbxx_ll_adc.h
  • LL_ADC_DELAY_VREFINT_STAB_US : stm32wbxx_ll_adc.h
  • LL_ADC_DIFFERENTIAL_ENDED : stm32wbxx_ll_adc.h
  • LL_ADC_Disable() : stm32wbxx_ll_adc.h
  • LL_ADC_DisableDeepPowerDown() : stm32wbxx_ll_adc.h
  • LL_ADC_DisableInternalRegulator() : stm32wbxx_ll_adc.h
  • LL_ADC_DisableIT_ADRDY() : stm32wbxx_ll_adc.h
  • LL_ADC_DisableIT_AWD1() : stm32wbxx_ll_adc.h
  • LL_ADC_DisableIT_AWD2() : stm32wbxx_ll_adc.h
  • LL_ADC_DisableIT_AWD3() : stm32wbxx_ll_adc.h
  • LL_ADC_DisableIT_EOC() : stm32wbxx_ll_adc.h
  • LL_ADC_DisableIT_EOS() : stm32wbxx_ll_adc.h
  • LL_ADC_DisableIT_EOSMP() : stm32wbxx_ll_adc.h
  • LL_ADC_DisableIT_JEOC() : stm32wbxx_ll_adc.h
  • LL_ADC_DisableIT_JEOS() : stm32wbxx_ll_adc.h
  • LL_ADC_DisableIT_JQOVF() : stm32wbxx_ll_adc.h
  • LL_ADC_DisableIT_OVR() : stm32wbxx_ll_adc.h
  • LL_ADC_DMA_GetRegAddr() : stm32wbxx_ll_adc.h
  • LL_ADC_DMA_REG_REGULAR_DATA : stm32wbxx_ll_adc.h
  • LL_ADC_Enable() : stm32wbxx_ll_adc.h
  • LL_ADC_EnableDeepPowerDown() : stm32wbxx_ll_adc.h
  • LL_ADC_EnableInternalRegulator() : stm32wbxx_ll_adc.h
  • LL_ADC_EnableIT_ADRDY() : stm32wbxx_ll_adc.h
  • LL_ADC_EnableIT_AWD1() : stm32wbxx_ll_adc.h
  • LL_ADC_EnableIT_AWD2() : stm32wbxx_ll_adc.h
  • LL_ADC_EnableIT_AWD3() : stm32wbxx_ll_adc.h
  • LL_ADC_EnableIT_EOC() : stm32wbxx_ll_adc.h
  • LL_ADC_EnableIT_EOS() : stm32wbxx_ll_adc.h
  • LL_ADC_EnableIT_EOSMP() : stm32wbxx_ll_adc.h
  • LL_ADC_EnableIT_JEOC() : stm32wbxx_ll_adc.h
  • LL_ADC_EnableIT_JEOS() : stm32wbxx_ll_adc.h
  • LL_ADC_EnableIT_JQOVF() : stm32wbxx_ll_adc.h
  • LL_ADC_EnableIT_OVR() : stm32wbxx_ll_adc.h
  • LL_ADC_FLAG_ADRDY : stm32wbxx_ll_adc.h
  • LL_ADC_FLAG_AWD1 : stm32wbxx_ll_adc.h
  • LL_ADC_FLAG_AWD2 : stm32wbxx_ll_adc.h
  • LL_ADC_FLAG_AWD3 : stm32wbxx_ll_adc.h
  • LL_ADC_FLAG_EOC : stm32wbxx_ll_adc.h
  • LL_ADC_FLAG_EOS : stm32wbxx_ll_adc.h
  • LL_ADC_FLAG_EOSMP : stm32wbxx_ll_adc.h
  • LL_ADC_FLAG_JEOC : stm32wbxx_ll_adc.h
  • LL_ADC_FLAG_JEOS : stm32wbxx_ll_adc.h
  • LL_ADC_FLAG_JQOVF : stm32wbxx_ll_adc.h
  • LL_ADC_FLAG_OVR : stm32wbxx_ll_adc.h
  • LL_ADC_GetAnalogWDMonitChannels() : stm32wbxx_ll_adc.h
  • LL_ADC_GetAnalogWDThresholds() : stm32wbxx_ll_adc.h
  • LL_ADC_GetCalibrationFactor() : stm32wbxx_ll_adc.h
  • LL_ADC_GetChannelSamplingTime() : stm32wbxx_ll_adc.h
  • LL_ADC_GetChannelSingleDiff() : stm32wbxx_ll_adc.h
  • LL_ADC_GetCommonClock() : stm32wbxx_ll_adc.h
  • LL_ADC_GetCommonPathInternalCh() : stm32wbxx_ll_adc.h
  • LL_ADC_GetDataAlignment() : stm32wbxx_ll_adc.h
  • LL_ADC_GetLowPowerMode() : stm32wbxx_ll_adc.h
  • LL_ADC_GetOffsetChannel() : stm32wbxx_ll_adc.h
  • LL_ADC_GetOffsetLevel() : stm32wbxx_ll_adc.h
  • LL_ADC_GetOffsetState() : stm32wbxx_ll_adc.h
  • LL_ADC_GetOverSamplingDiscont() : stm32wbxx_ll_adc.h
  • LL_ADC_GetOverSamplingRatio() : stm32wbxx_ll_adc.h
  • LL_ADC_GetOverSamplingScope() : stm32wbxx_ll_adc.h
  • LL_ADC_GetOverSamplingShift() : stm32wbxx_ll_adc.h
  • LL_ADC_GetResolution() : stm32wbxx_ll_adc.h
  • LL_ADC_GROUP_INJECTED : stm32wbxx_ll_adc.h
  • LL_ADC_GROUP_REGULAR : stm32wbxx_ll_adc.h
  • LL_ADC_GROUP_REGULAR_INJECTED : stm32wbxx_ll_adc.h
  • LL_ADC_Init() : stm32wbxx_ll_adc.c
  • LL_ADC_INJ_ConfigQueueContext() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_GetQueueMode() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_GetSequencerDiscont() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_GetSequencerLength() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_GetSequencerRanks() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_GetTrigAuto() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_GetTriggerEdge() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_GetTriggerSource() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_Init() : stm32wbxx_ll_adc.c
  • LL_ADC_INJ_IsConversionOngoing() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_IsStopConversionOngoing() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_IsTriggerSourceSWStart() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_QUEUE_DISABLE : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_RANK_1 : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_RANK_2 : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_RANK_3 : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_RANK_4 : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData10() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData12() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData32() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData6() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData8() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_SEQ_DISCONT_1RANK : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_SEQ_DISCONT_DISABLE : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_DISABLE : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_SetQueueMode() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_SetSequencerDiscont() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_SetSequencerLength() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_SetSequencerRanks() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_SetTrigAuto() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_SetTriggerEdge() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_SetTriggerSource() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_StartConversion() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_StopConversion() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_StructInit() : stm32wbxx_ll_adc.c
  • LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_FALLING : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_RISING : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_RISINGFALLING : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM1_CH4 : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM2_CH1 : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM2_TRGO : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_TRIG_FROM_GRP_REGULAR : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_TRIG_INDEPENDENT : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_TRIG_SOFTWARE : stm32wbxx_ll_adc.h
  • LL_ADC_IsActiveFlag_ADRDY() : stm32wbxx_ll_adc.h
  • LL_ADC_IsActiveFlag_AWD1() : stm32wbxx_ll_adc.h
  • LL_ADC_IsActiveFlag_AWD2() : stm32wbxx_ll_adc.h
  • LL_ADC_IsActiveFlag_AWD3() : stm32wbxx_ll_adc.h
  • LL_ADC_IsActiveFlag_EOC() : stm32wbxx_ll_adc.h
  • LL_ADC_IsActiveFlag_EOS() : stm32wbxx_ll_adc.h
  • LL_ADC_IsActiveFlag_EOSMP() : stm32wbxx_ll_adc.h
  • LL_ADC_IsActiveFlag_JEOC() : stm32wbxx_ll_adc.h
  • LL_ADC_IsActiveFlag_JEOS() : stm32wbxx_ll_adc.h
  • LL_ADC_IsActiveFlag_JQOVF() : stm32wbxx_ll_adc.h
  • LL_ADC_IsActiveFlag_OVR() : stm32wbxx_ll_adc.h
  • LL_ADC_IsCalibrationOnGoing() : stm32wbxx_ll_adc.h
  • LL_ADC_IsDeepPowerDownEnabled() : stm32wbxx_ll_adc.h
  • LL_ADC_IsDisableOngoing() : stm32wbxx_ll_adc.h
  • LL_ADC_IsEnabled() : stm32wbxx_ll_adc.h
  • LL_ADC_IsEnabledIT_ADRDY() : stm32wbxx_ll_adc.h
  • LL_ADC_IsEnabledIT_AWD1() : stm32wbxx_ll_adc.h
  • LL_ADC_IsEnabledIT_AWD2() : stm32wbxx_ll_adc.h
  • LL_ADC_IsEnabledIT_AWD3() : stm32wbxx_ll_adc.h
  • LL_ADC_IsEnabledIT_EOC() : stm32wbxx_ll_adc.h
  • LL_ADC_IsEnabledIT_EOS() : stm32wbxx_ll_adc.h
  • LL_ADC_IsEnabledIT_EOSMP() : stm32wbxx_ll_adc.h
  • LL_ADC_IsEnabledIT_JEOC() : stm32wbxx_ll_adc.h
  • LL_ADC_IsEnabledIT_JEOS() : stm32wbxx_ll_adc.h
  • LL_ADC_IsEnabledIT_JQOVF() : stm32wbxx_ll_adc.h
  • LL_ADC_IsEnabledIT_OVR() : stm32wbxx_ll_adc.h
  • LL_ADC_IsInternalRegulatorEnabled() : stm32wbxx_ll_adc.h
  • LL_ADC_IT_ADRDY : stm32wbxx_ll_adc.h
  • LL_ADC_IT_AWD1 : stm32wbxx_ll_adc.h
  • LL_ADC_IT_AWD2 : stm32wbxx_ll_adc.h
  • LL_ADC_IT_AWD3 : stm32wbxx_ll_adc.h
  • LL_ADC_IT_EOC : stm32wbxx_ll_adc.h
  • LL_ADC_IT_EOS : stm32wbxx_ll_adc.h
  • LL_ADC_IT_EOSMP : stm32wbxx_ll_adc.h
  • LL_ADC_IT_JEOC : stm32wbxx_ll_adc.h
  • LL_ADC_IT_JEOS : stm32wbxx_ll_adc.h
  • LL_ADC_IT_JQOVF : stm32wbxx_ll_adc.h
  • LL_ADC_IT_OVR : stm32wbxx_ll_adc.h
  • LL_ADC_LP_AUTOWAIT : stm32wbxx_ll_adc.h
  • LL_ADC_LP_MODE_NONE : stm32wbxx_ll_adc.h
  • LL_ADC_OFFSET_1 : stm32wbxx_ll_adc.h
  • LL_ADC_OFFSET_2 : stm32wbxx_ll_adc.h
  • LL_ADC_OFFSET_3 : stm32wbxx_ll_adc.h
  • LL_ADC_OFFSET_4 : stm32wbxx_ll_adc.h
  • LL_ADC_OFFSET_DISABLE : stm32wbxx_ll_adc.h
  • LL_ADC_OFFSET_ENABLE : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_DISABLE : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_GRP_INJ_REG_RESUMED : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_GRP_INJECTED : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_GRP_REGULAR_CONTINUED : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_GRP_REGULAR_RESUMED : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_RATIO_128 : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_RATIO_16 : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_RATIO_2 : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_RATIO_256 : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_RATIO_32 : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_RATIO_4 : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_RATIO_64 : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_RATIO_8 : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_REG_CONT : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_REG_DISCONT : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_SHIFT_NONE : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_1 : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_2 : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_3 : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_4 : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_5 : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_6 : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_7 : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_8 : stm32wbxx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_NONE : stm32wbxx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_TEMPSENSOR : stm32wbxx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_VBAT : stm32wbxx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_VREFINT : stm32wbxx_ll_adc.h
  • LL_ADC_ReadReg : stm32wbxx_ll_adc.h
  • LL_ADC_REG_CONV_CONTINUOUS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_CONV_SINGLE : stm32wbxx_ll_adc.h
  • LL_ADC_REG_DMA_TRANSFER_LIMITED : stm32wbxx_ll_adc.h
  • LL_ADC_REG_DMA_TRANSFER_NONE : stm32wbxx_ll_adc.h
  • LL_ADC_REG_DMA_TRANSFER_UNLIMITED : stm32wbxx_ll_adc.h
  • LL_ADC_REG_GetContinuousMode() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_GetDMATransfer() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_GetOverrun() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_GetSequencerDiscont() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_GetSequencerLength() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_GetSequencerRanks() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_GetTriggerEdge() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_GetTriggerSource() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_Init() : stm32wbxx_ll_adc.c
  • LL_ADC_REG_IsConversionOngoing() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_IsStopConversionOngoing() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_IsTriggerSourceSWStart() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_OVR_DATA_OVERWRITTEN : stm32wbxx_ll_adc.h
  • LL_ADC_REG_OVR_DATA_PRESERVED : stm32wbxx_ll_adc.h
  • LL_ADC_REG_RANK_1 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_RANK_10 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_RANK_11 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_RANK_12 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_RANK_13 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_RANK_14 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_RANK_15 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_RANK_16 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_RANK_2 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_RANK_3 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_RANK_4 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_RANK_5 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_RANK_6 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_RANK_7 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_RANK_8 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_RANK_9 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_ReadConversionData10() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_ReadConversionData12() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_ReadConversionData32() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_ReadConversionData6() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_ReadConversionData8() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_1RANK : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_2RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_3RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_4RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_5RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_6RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_7RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_8RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_DISABLE : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_DISABLE : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SetContinuousMode() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SetDMATransfer() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SetOverrun() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SetSequencerDiscont() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SetSequencerLength() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SetSequencerRanks() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SetTriggerEdge() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SetTriggerSource() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_StartConversion() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_StopConversion() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_StructInit() : stm32wbxx_ll_adc.c
  • LL_ADC_REG_TRIG_EXT_EXTI_LINE11 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_FALLING : stm32wbxx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_RISING : stm32wbxx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_RISINGFALLING : stm32wbxx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_CH1 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_CH2 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_CH3 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_TRGO : stm32wbxx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM2_CH2 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM2_TRGO : stm32wbxx_ll_adc.h
  • LL_ADC_REG_TRIG_SOFTWARE : stm32wbxx_ll_adc.h
  • LL_ADC_RESOLUTION_10B : stm32wbxx_ll_adc.h
  • LL_ADC_RESOLUTION_12B : stm32wbxx_ll_adc.h
  • LL_ADC_RESOLUTION_6B : stm32wbxx_ll_adc.h
  • LL_ADC_RESOLUTION_8B : stm32wbxx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_12CYCLES_5 : stm32wbxx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_247CYCLES_5 : stm32wbxx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_24CYCLES_5 : stm32wbxx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_2CYCLES_5 : stm32wbxx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_47CYCLES_5 : stm32wbxx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_640CYCLES_5 : stm32wbxx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_6CYCLES_5 : stm32wbxx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_92CYCLES_5 : stm32wbxx_ll_adc.h
  • LL_ADC_SetAnalogWDMonitChannels() : stm32wbxx_ll_adc.h
  • LL_ADC_SetAnalogWDThresholds() : stm32wbxx_ll_adc.h
  • LL_ADC_SetCalibrationFactor() : stm32wbxx_ll_adc.h
  • LL_ADC_SetChannelSamplingTime() : stm32wbxx_ll_adc.h
  • LL_ADC_SetChannelSingleDiff() : stm32wbxx_ll_adc.h
  • LL_ADC_SetCommonClock() : stm32wbxx_ll_adc.h
  • LL_ADC_SetCommonPathInternalCh() : stm32wbxx_ll_adc.h
  • LL_ADC_SetDataAlignment() : stm32wbxx_ll_adc.h
  • LL_ADC_SetLowPowerMode() : stm32wbxx_ll_adc.h
  • LL_ADC_SetOffset() : stm32wbxx_ll_adc.h
  • LL_ADC_SetOffsetState() : stm32wbxx_ll_adc.h
  • LL_ADC_SetOverSamplingDiscont() : stm32wbxx_ll_adc.h
  • LL_ADC_SetOverSamplingScope() : stm32wbxx_ll_adc.h
  • LL_ADC_SetResolution() : stm32wbxx_ll_adc.h
  • LL_ADC_SINGLE_ENDED : stm32wbxx_ll_adc.h
  • LL_ADC_StartCalibration() : stm32wbxx_ll_adc.h
  • LL_ADC_StructInit() : stm32wbxx_ll_adc.c
  • LL_ADC_WriteReg : stm32wbxx_ll_adc.h
  • LL_AHB1_GRP1_DisableClock() : stm32wbxx_ll_bus.h
  • LL_AHB1_GRP1_DisableClockSleep() : stm32wbxx_ll_bus.h
  • LL_AHB1_GRP1_EnableClock() : stm32wbxx_ll_bus.h
  • LL_AHB1_GRP1_EnableClockSleep() : stm32wbxx_ll_bus.h
  • LL_AHB1_GRP1_ForceReset() : stm32wbxx_ll_bus.h
  • LL_AHB1_GRP1_IsEnabledClock() : stm32wbxx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_ALL : stm32wbxx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_CRC : stm32wbxx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_DMA1 : stm32wbxx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_DMA2 : stm32wbxx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_DMAMUX1 : stm32wbxx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_SRAM1 : stm32wbxx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_TSC : stm32wbxx_ll_bus.h
  • LL_AHB1_GRP1_ReleaseReset() : stm32wbxx_ll_bus.h
  • LL_AHB2_GRP1_DisableClock() : stm32wbxx_ll_bus.h
  • LL_AHB2_GRP1_DisableClockSleep() : stm32wbxx_ll_bus.h
  • LL_AHB2_GRP1_EnableClock() : stm32wbxx_ll_bus.h
  • LL_AHB2_GRP1_EnableClockSleep() : stm32wbxx_ll_bus.h
  • LL_AHB2_GRP1_ForceReset() : stm32wbxx_ll_bus.h
  • LL_AHB2_GRP1_IsEnabledClock() : stm32wbxx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_ADC : stm32wbxx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_AES1 : stm32wbxx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_ALL : stm32wbxx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOA : stm32wbxx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOB : stm32wbxx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOC : stm32wbxx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOD : stm32wbxx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOE : stm32wbxx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOH : stm32wbxx_ll_bus.h
  • LL_AHB2_GRP1_ReleaseReset() : stm32wbxx_ll_bus.h
  • LL_AHB3_GRP1_DisableClock() : stm32wbxx_ll_bus.h
  • LL_AHB3_GRP1_DisableClockSleep() : stm32wbxx_ll_bus.h
  • LL_AHB3_GRP1_EnableClock() : stm32wbxx_ll_bus.h
  • LL_AHB3_GRP1_EnableClockSleep() : stm32wbxx_ll_bus.h
  • LL_AHB3_GRP1_ForceReset() : stm32wbxx_ll_bus.h
  • LL_AHB3_GRP1_IsEnabledClock() : stm32wbxx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_AES2 : stm32wbxx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_ALL : stm32wbxx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_FLASH : stm32wbxx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_HSEM : stm32wbxx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_IPCC : stm32wbxx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_PKA : stm32wbxx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_QUADSPI : stm32wbxx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_RNG : stm32wbxx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_SRAM2 : stm32wbxx_ll_bus.h
  • LL_AHB3_GRP1_ReleaseReset() : stm32wbxx_ll_bus.h
  • LL_APB1_GRP1_DisableClock() : stm32wbxx_ll_bus.h
  • LL_APB1_GRP1_DisableClockSleep() : stm32wbxx_ll_bus.h
  • LL_APB1_GRP1_EnableClock() : stm32wbxx_ll_bus.h
  • LL_APB1_GRP1_EnableClockSleep() : stm32wbxx_ll_bus.h
  • LL_APB1_GRP1_ForceReset() : stm32wbxx_ll_bus.h
  • LL_APB1_GRP1_IsEnabledClock() : stm32wbxx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_ALL : stm32wbxx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_CRS : stm32wbxx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_I2C1 : stm32wbxx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_I2C3 : stm32wbxx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_LCD : stm32wbxx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_LPTIM1 : stm32wbxx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_RTCAPB : stm32wbxx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_SPI2 : stm32wbxx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM2 : stm32wbxx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USB : stm32wbxx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_WWDG : stm32wbxx_ll_bus.h
  • LL_APB1_GRP1_ReleaseReset() : stm32wbxx_ll_bus.h
  • LL_APB1_GRP2_DisableClock() : stm32wbxx_ll_bus.h
  • LL_APB1_GRP2_DisableClockSleep() : stm32wbxx_ll_bus.h
  • LL_APB1_GRP2_EnableClock() : stm32wbxx_ll_bus.h
  • LL_APB1_GRP2_EnableClockSleep() : stm32wbxx_ll_bus.h
  • LL_APB1_GRP2_ForceReset() : stm32wbxx_ll_bus.h
  • LL_APB1_GRP2_IsEnabledClock() : stm32wbxx_ll_bus.h
  • LL_APB1_GRP2_PERIPH_ALL : stm32wbxx_ll_bus.h
  • LL_APB1_GRP2_PERIPH_LPTIM2 : stm32wbxx_ll_bus.h
  • LL_APB1_GRP2_PERIPH_LPUART1 : stm32wbxx_ll_bus.h
  • LL_APB1_GRP2_ReleaseReset() : stm32wbxx_ll_bus.h
  • LL_APB2_GRP1_DisableClock() : stm32wbxx_ll_bus.h
  • LL_APB2_GRP1_DisableClockSleep() : stm32wbxx_ll_bus.h
  • LL_APB2_GRP1_EnableClock() : stm32wbxx_ll_bus.h
  • LL_APB2_GRP1_EnableClockSleep() : stm32wbxx_ll_bus.h
  • LL_APB2_GRP1_ForceReset() : stm32wbxx_ll_bus.h
  • LL_APB2_GRP1_IsEnabledClock() : stm32wbxx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_ALL : stm32wbxx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SAI1 : stm32wbxx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SPI1 : stm32wbxx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM1 : stm32wbxx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM16 : stm32wbxx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM17 : stm32wbxx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_USART1 : stm32wbxx_ll_bus.h
  • LL_APB2_GRP1_ReleaseReset() : stm32wbxx_ll_bus.h
  • LL_APB3_GRP1_ForceReset() : stm32wbxx_ll_bus.h
  • LL_APB3_GRP1_PERIPH_ALL : stm32wbxx_ll_bus.h
  • LL_APB3_GRP1_PERIPH_RF : stm32wbxx_ll_bus.h
  • LL_APB3_GRP1_ReleaseReset() : stm32wbxx_ll_bus.h
  • LL_C1_IPCC_ClearFlag_CHx() : stm32wbxx_ll_ipcc.h
  • LL_C1_IPCC_DisableIT_RXO() : stm32wbxx_ll_ipcc.h
  • LL_C1_IPCC_DisableIT_TXF() : stm32wbxx_ll_ipcc.h
  • LL_C1_IPCC_DisableReceiveChannel() : stm32wbxx_ll_ipcc.h
  • LL_C1_IPCC_DisableTransmitChannel() : stm32wbxx_ll_ipcc.h
  • LL_C1_IPCC_EnableIT_RXO() : stm32wbxx_ll_ipcc.h
  • LL_C1_IPCC_EnableIT_TXF() : stm32wbxx_ll_ipcc.h
  • LL_C1_IPCC_EnableReceiveChannel() : stm32wbxx_ll_ipcc.h
  • LL_C1_IPCC_EnableTransmitChannel() : stm32wbxx_ll_ipcc.h
  • LL_C1_IPCC_IsActiveFlag_CHx() : stm32wbxx_ll_ipcc.h
  • LL_C1_IPCC_IsEnabledIT_RXO() : stm32wbxx_ll_ipcc.h
  • LL_C1_IPCC_IsEnabledIT_TXF() : stm32wbxx_ll_ipcc.h
  • LL_C1_IPCC_IsEnabledReceiveChannel() : stm32wbxx_ll_ipcc.h
  • LL_C1_IPCC_IsEnabledTransmitChannel() : stm32wbxx_ll_ipcc.h
  • LL_C1_IPCC_SetFlag_CHx() : stm32wbxx_ll_ipcc.h
  • LL_C2_AHB1_GRP1_DisableClock() : stm32wbxx_ll_bus.h
  • LL_C2_AHB1_GRP1_DisableClockSleep() : stm32wbxx_ll_bus.h
  • LL_C2_AHB1_GRP1_EnableClock() : stm32wbxx_ll_bus.h
  • LL_C2_AHB1_GRP1_EnableClockSleep() : stm32wbxx_ll_bus.h
  • LL_C2_AHB1_GRP1_IsEnabledClock() : stm32wbxx_ll_bus.h
  • LL_C2_AHB1_GRP1_PERIPH_CRC : stm32wbxx_ll_bus.h
  • LL_C2_AHB1_GRP1_PERIPH_DMA1 : stm32wbxx_ll_bus.h
  • LL_C2_AHB1_GRP1_PERIPH_DMA2 : stm32wbxx_ll_bus.h
  • LL_C2_AHB1_GRP1_PERIPH_DMAMUX1 : stm32wbxx_ll_bus.h
  • LL_C2_AHB1_GRP1_PERIPH_SRAM1 : stm32wbxx_ll_bus.h
  • LL_C2_AHB1_GRP1_PERIPH_TSC : stm32wbxx_ll_bus.h
  • LL_C2_AHB2_GRP1_DisableClock() : stm32wbxx_ll_bus.h
  • LL_C2_AHB2_GRP1_DisableClockSleep() : stm32wbxx_ll_bus.h
  • LL_C2_AHB2_GRP1_EnableClock() : stm32wbxx_ll_bus.h
  • LL_C2_AHB2_GRP1_EnableClockSleep() : stm32wbxx_ll_bus.h
  • LL_C2_AHB2_GRP1_IsEnabledClock() : stm32wbxx_ll_bus.h
  • LL_C2_AHB2_GRP1_PERIPH_ADC : stm32wbxx_ll_bus.h
  • LL_C2_AHB2_GRP1_PERIPH_AES1 : stm32wbxx_ll_bus.h
  • LL_C2_AHB2_GRP1_PERIPH_GPIOA : stm32wbxx_ll_bus.h
  • LL_C2_AHB2_GRP1_PERIPH_GPIOB : stm32wbxx_ll_bus.h
  • LL_C2_AHB2_GRP1_PERIPH_GPIOC : stm32wbxx_ll_bus.h
  • LL_C2_AHB2_GRP1_PERIPH_GPIOD : stm32wbxx_ll_bus.h
  • LL_C2_AHB2_GRP1_PERIPH_GPIOE : stm32wbxx_ll_bus.h
  • LL_C2_AHB2_GRP1_PERIPH_GPIOH : stm32wbxx_ll_bus.h
  • LL_C2_AHB3_GRP1_DisableClock() : stm32wbxx_ll_bus.h
  • LL_C2_AHB3_GRP1_DisableClockSleep() : stm32wbxx_ll_bus.h
  • LL_C2_AHB3_GRP1_EnableClock() : stm32wbxx_ll_bus.h
  • LL_C2_AHB3_GRP1_EnableClockSleep() : stm32wbxx_ll_bus.h
  • LL_C2_AHB3_GRP1_IsEnabledClock() : stm32wbxx_ll_bus.h
  • LL_C2_AHB3_GRP1_PERIPH_AES2 : stm32wbxx_ll_bus.h
  • LL_C2_AHB3_GRP1_PERIPH_FLASH : stm32wbxx_ll_bus.h
  • LL_C2_AHB3_GRP1_PERIPH_HSEM : stm32wbxx_ll_bus.h
  • LL_C2_AHB3_GRP1_PERIPH_IPCC : stm32wbxx_ll_bus.h
  • LL_C2_AHB3_GRP1_PERIPH_PKA : stm32wbxx_ll_bus.h
  • LL_C2_AHB3_GRP1_PERIPH_RNG : stm32wbxx_ll_bus.h
  • LL_C2_AHB3_GRP1_PERIPH_SRAM2 : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP1_DisableClock() : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP1_DisableClockSleep() : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP1_EnableClock() : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP1_EnableClockSleep() : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP1_IsEnabledClock() : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP1_PERIPH_CRS : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP1_PERIPH_I2C1 : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP1_PERIPH_I2C3 : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP1_PERIPH_LCD : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP1_PERIPH_LPTIM1 : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP1_PERIPH_RTCAPB : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP1_PERIPH_SPI2 : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP1_PERIPH_TIM2 : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP1_PERIPH_USB : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP2_DisableClock() : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP2_DisableClockSleep() : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP2_EnableClock() : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP2_EnableClockSleep() : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP2_IsEnabledClock() : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP2_PERIPH_LPTIM2 : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP2_PERIPH_LPUART1 : stm32wbxx_ll_bus.h
  • LL_C2_APB2_GRP1_DisableClock() : stm32wbxx_ll_bus.h
  • LL_C2_APB2_GRP1_DisableClockSleep() : stm32wbxx_ll_bus.h
  • LL_C2_APB2_GRP1_EnableClock() : stm32wbxx_ll_bus.h
  • LL_C2_APB2_GRP1_EnableClockSleep() : stm32wbxx_ll_bus.h
  • LL_C2_APB2_GRP1_IsEnabledClock() : stm32wbxx_ll_bus.h
  • LL_C2_APB2_GRP1_PERIPH_SAI1 : stm32wbxx_ll_bus.h
  • LL_C2_APB2_GRP1_PERIPH_SPI1 : stm32wbxx_ll_bus.h
  • LL_C2_APB2_GRP1_PERIPH_TIM1 : stm32wbxx_ll_bus.h
  • LL_C2_APB2_GRP1_PERIPH_TIM16 : stm32wbxx_ll_bus.h
  • LL_C2_APB2_GRP1_PERIPH_TIM17 : stm32wbxx_ll_bus.h
  • LL_C2_APB2_GRP1_PERIPH_USART1 : stm32wbxx_ll_bus.h
  • LL_C2_APB3_GRP1_DisableClock() : stm32wbxx_ll_bus.h
  • LL_C2_APB3_GRP1_DisableClockSleep() : stm32wbxx_ll_bus.h
  • LL_C2_APB3_GRP1_EnableClock() : stm32wbxx_ll_bus.h
  • LL_C2_APB3_GRP1_EnableClockSleep() : stm32wbxx_ll_bus.h
  • LL_C2_APB3_GRP1_IsEnabledClock() : stm32wbxx_ll_bus.h
  • LL_C2_APB3_GRP1_PERIPH_802 : stm32wbxx_ll_bus.h
  • LL_C2_APB3_GRP1_PERIPH_BLE : stm32wbxx_ll_bus.h
  • LL_C2_DBGMCU_APB1_GRP1_FreezePeriph() : stm32wbxx_ll_system.h
  • LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP : stm32wbxx_ll_system.h
  • LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP : stm32wbxx_ll_system.h
  • LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP : stm32wbxx_ll_system.h
  • LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP : stm32wbxx_ll_system.h
  • LL_C2_DBGMCU_APB1_GRP1_RTC_STOP : stm32wbxx_ll_system.h
  • LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP : stm32wbxx_ll_system.h
  • LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph() : stm32wbxx_ll_system.h
  • LL_C2_DBGMCU_APB1_GRP2_FreezePeriph() : stm32wbxx_ll_system.h
  • LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP : stm32wbxx_ll_system.h
  • LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph() : stm32wbxx_ll_system.h
  • LL_C2_DBGMCU_APB2_GRP1_FreezePeriph() : stm32wbxx_ll_system.h
  • LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP : stm32wbxx_ll_system.h
  • LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP : stm32wbxx_ll_system.h
  • LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP : stm32wbxx_ll_system.h
  • LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph() : stm32wbxx_ll_system.h
  • LL_C2_EXTI_DisableEvent_0_31() : stm32wbxx_ll_exti.h
  • LL_C2_EXTI_DisableEvent_32_63() : stm32wbxx_ll_exti.h
  • LL_C2_EXTI_DisableIT_0_31() : stm32wbxx_ll_exti.h
  • LL_C2_EXTI_DisableIT_32_63() : stm32wbxx_ll_exti.h
  • LL_C2_EXTI_EnableEvent_0_31() : stm32wbxx_ll_exti.h
  • LL_C2_EXTI_EnableEvent_32_63() : stm32wbxx_ll_exti.h
  • LL_C2_EXTI_EnableIT_0_31() : stm32wbxx_ll_exti.h
  • LL_C2_EXTI_EnableIT_32_63() : stm32wbxx_ll_exti.h
  • LL_C2_EXTI_IsEnabledEvent_0_31() : stm32wbxx_ll_exti.h
  • LL_C2_EXTI_IsEnabledEvent_32_63() : stm32wbxx_ll_exti.h
  • LL_C2_EXTI_IsEnabledIT_0_31() : stm32wbxx_ll_exti.h
  • LL_C2_EXTI_IsEnabledIT_32_63() : stm32wbxx_ll_exti.h
  • LL_C2_IPCC_ClearFlag_CHx() : stm32wbxx_ll_ipcc.h
  • LL_C2_IPCC_DisableIT_RXO() : stm32wbxx_ll_ipcc.h
  • LL_C2_IPCC_DisableIT_TXF() : stm32wbxx_ll_ipcc.h
  • LL_C2_IPCC_DisableReceiveChannel() : stm32wbxx_ll_ipcc.h
  • LL_C2_IPCC_DisableTransmitChannel() : stm32wbxx_ll_ipcc.h
  • LL_C2_IPCC_EnableIT_RXO() : stm32wbxx_ll_ipcc.h
  • LL_C2_IPCC_EnableIT_TXF() : stm32wbxx_ll_ipcc.h
  • LL_C2_IPCC_EnableReceiveChannel() : stm32wbxx_ll_ipcc.h
  • LL_C2_IPCC_EnableTransmitChannel() : stm32wbxx_ll_ipcc.h
  • LL_C2_IPCC_IsActiveFlag_CHx() : stm32wbxx_ll_ipcc.h
  • LL_C2_IPCC_IsEnabledIT_RXO() : stm32wbxx_ll_ipcc.h
  • LL_C2_IPCC_IsEnabledIT_TXF() : stm32wbxx_ll_ipcc.h
  • LL_C2_IPCC_IsEnabledReceiveChannel() : stm32wbxx_ll_ipcc.h
  • LL_C2_IPCC_IsEnabledTransmitChannel() : stm32wbxx_ll_ipcc.h
  • LL_C2_IPCC_SetFlag_CHx() : stm32wbxx_ll_ipcc.h
  • LL_C2_PWR_DisableInternWU() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_DisableIT_802WU() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_DisableIT_BLEWU() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_DisablePUPDCfg() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_DisableWakeUpPin() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_EnableInternWU() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_EnableIT_802WU() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_EnableIT_BLEWU() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_EnablePUPDCfg() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_EnableWakeUpPin() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_GetFlashPowerModeLPRun() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_GetFlashPowerModeSleep() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_GetPowerMode() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_IsEnabledInternWU() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_IsEnabledIT_802WU() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_IsEnabledIT_BLEWU() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_IsEnabledPUPDCfg() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_IsEnabledWakeUpPin() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_IsWokenUp_802_15_4() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_IsWokenUp_BLE() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_SetFlashPowerModeLPRun() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_SetFlashPowerModeSleep() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_SetPowerMode() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_WakeUp_802_15_4() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_WakeUp_BLE() : stm32wbxx_ll_pwr.h
  • LL_C2_RCC_GetAHBPrescaler() : stm32wbxx_ll_rcc.h
  • LL_C2_RCC_SetAHBPrescaler() : stm32wbxx_ll_rcc.h
  • LL_C2_SYSCFG_GRP1_ADC : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_AES1 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_COMP : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_DisableIT() : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_EnableIT() : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_EXTI0 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_EXTI1 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_EXTI10 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_EXTI11 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_EXTI12 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_EXTI13 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_EXTI14 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_EXTI15 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_EXTI2 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_EXTI3 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_EXTI4 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_EXTI5 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_EXTI6 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_EXTI7 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_EXTI8 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_EXTI9 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_FLASH : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_IsEnabledIT() : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_PKA : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_RCC : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_RNG : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_RTCALARM : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_RTCWKUP : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_DisableIT() : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_DMA1CH1 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_DMA1CH2 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_DMA1CH3 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_DMA1CH4 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_DMA1CH5 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_DMA1CH6 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_DMA1CH7 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_DMA2CH1 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_DMA2CH2 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_DMA2CH3 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_DMA2CH4 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_DMA2CH5 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_DMA2CH6 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_DMA2CH7 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_DMAMUX1 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_EnableIT() : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_IsEnabledIT() : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_LCD : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_PVD : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_PVM1 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_PVM3 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_TSC : stm32wbxx_ll_system.h
  • LL_COMP_BLANKINGSRC_NONE : stm32wbxx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM1_OC5 : stm32wbxx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM2_OC3 : stm32wbxx_ll_comp.h
  • LL_COMP_ConfigInputs() : stm32wbxx_ll_comp.h
  • LL_COMP_DeInit() : stm32wbxx_ll_comp.c
  • LL_COMP_DELAY_STARTUP_US : stm32wbxx_ll_comp.h
  • LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US : stm32wbxx_ll_comp.h
  • LL_COMP_Disable() : stm32wbxx_ll_comp.h
  • LL_COMP_Enable() : stm32wbxx_ll_comp.h
  • LL_COMP_GetCommonWindowMode() : stm32wbxx_ll_comp.h
  • LL_COMP_GetInputHysteresis() : stm32wbxx_ll_comp.h
  • LL_COMP_GetInputMinus() : stm32wbxx_ll_comp.h
  • LL_COMP_GetInputPlus() : stm32wbxx_ll_comp.h
  • LL_COMP_GetOutputBlankingSource() : stm32wbxx_ll_comp.h
  • LL_COMP_GetOutputPolarity() : stm32wbxx_ll_comp.h
  • LL_COMP_GetPowerMode() : stm32wbxx_ll_comp.h
  • LL_COMP_HYSTERESIS_HIGH : stm32wbxx_ll_comp.h
  • LL_COMP_HYSTERESIS_LOW : stm32wbxx_ll_comp.h
  • LL_COMP_HYSTERESIS_MEDIUM : stm32wbxx_ll_comp.h
  • LL_COMP_HYSTERESIS_NONE : stm32wbxx_ll_comp.h
  • LL_COMP_Init() : stm32wbxx_ll_comp.c
  • LL_COMP_INPUT_MINUS_1_2VREFINT : stm32wbxx_ll_comp.h
  • LL_COMP_INPUT_MINUS_1_4VREFINT : stm32wbxx_ll_comp.h
  • LL_COMP_INPUT_MINUS_3_4VREFINT : stm32wbxx_ll_comp.h
  • LL_COMP_INPUT_MINUS_IO1 : stm32wbxx_ll_comp.h
  • LL_COMP_INPUT_MINUS_IO2 : stm32wbxx_ll_comp.h
  • LL_COMP_INPUT_MINUS_IO3 : stm32wbxx_ll_comp.h
  • LL_COMP_INPUT_MINUS_IO4 : stm32wbxx_ll_comp.h
  • LL_COMP_INPUT_MINUS_IO5 : stm32wbxx_ll_comp.h
  • LL_COMP_INPUT_MINUS_VREFINT : stm32wbxx_ll_comp.h
  • LL_COMP_INPUT_PLUS_IO1 : stm32wbxx_ll_comp.h
  • LL_COMP_INPUT_PLUS_IO2 : stm32wbxx_ll_comp.h
  • LL_COMP_INPUT_PLUS_IO3 : stm32wbxx_ll_comp.h
  • LL_COMP_IsEnabled() : stm32wbxx_ll_comp.h
  • LL_COMP_IsLocked() : stm32wbxx_ll_comp.h
  • LL_COMP_Lock() : stm32wbxx_ll_comp.h
  • LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS : stm32wbxx_ll_comp.h
  • LL_COMP_OUTPUT_LEVEL_HIGH : stm32wbxx_ll_comp.h
  • LL_COMP_OUTPUT_LEVEL_LOW : stm32wbxx_ll_comp.h
  • LL_COMP_OUTPUTPOL_INVERTED : stm32wbxx_ll_comp.h
  • LL_COMP_OUTPUTPOL_NONINVERTED : stm32wbxx_ll_comp.h
  • LL_COMP_POWERMODE_HIGHSPEED : stm32wbxx_ll_comp.h
  • LL_COMP_POWERMODE_MEDIUMSPEED : stm32wbxx_ll_comp.h
  • LL_COMP_POWERMODE_ULTRALOWPOWER : stm32wbxx_ll_comp.h
  • LL_COMP_ReadOutputLevel() : stm32wbxx_ll_comp.h
  • LL_COMP_ReadReg : stm32wbxx_ll_comp.h
  • LL_COMP_SetCommonWindowMode() : stm32wbxx_ll_comp.h
  • LL_COMP_SetInputHysteresis() : stm32wbxx_ll_comp.h
  • LL_COMP_SetInputMinus() : stm32wbxx_ll_comp.h
  • LL_COMP_SetInputPlus() : stm32wbxx_ll_comp.h
  • LL_COMP_SetOutputBlankingSource() : stm32wbxx_ll_comp.h
  • LL_COMP_SetOutputPolarity() : stm32wbxx_ll_comp.h
  • LL_COMP_SetPowerMode() : stm32wbxx_ll_comp.h
  • LL_COMP_StructInit() : stm32wbxx_ll_comp.c
  • LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON : stm32wbxx_ll_comp.h
  • LL_COMP_WINDOWMODE_DISABLE : stm32wbxx_ll_comp.h
  • LL_COMP_WriteReg : stm32wbxx_ll_comp.h
  • LL_CPUID_GetConstant() : stm32wbxx_ll_cortex.h
  • LL_CPUID_GetImplementer() : stm32wbxx_ll_cortex.h
  • LL_CPUID_GetParNo() : stm32wbxx_ll_cortex.h
  • LL_CPUID_GetRevision() : stm32wbxx_ll_cortex.h
  • LL_CPUID_GetVariant() : stm32wbxx_ll_cortex.h
  • LL_CRC_DEFAULT_CRC32_POLY : stm32wbxx_ll_crc.h
  • LL_CRC_DEFAULT_CRC_INITVALUE : stm32wbxx_ll_crc.h
  • LL_CRC_DeInit() : stm32wbxx_ll_crc.c
  • LL_CRC_FeedData16() : stm32wbxx_ll_crc.h
  • LL_CRC_FeedData32() : stm32wbxx_ll_crc.h
  • LL_CRC_FeedData8() : stm32wbxx_ll_crc.h
  • LL_CRC_GetInitialData() : stm32wbxx_ll_crc.h
  • LL_CRC_GetInputDataReverseMode() : stm32wbxx_ll_crc.h
  • LL_CRC_GetOutputDataReverseMode() : stm32wbxx_ll_crc.h
  • LL_CRC_GetPolynomialCoef() : stm32wbxx_ll_crc.h
  • LL_CRC_GetPolynomialSize() : stm32wbxx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_BYTE : stm32wbxx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_HALFWORD : stm32wbxx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_NONE : stm32wbxx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_WORD : stm32wbxx_ll_crc.h
  • LL_CRC_OUTDATA_REVERSE_BIT : stm32wbxx_ll_crc.h
  • LL_CRC_OUTDATA_REVERSE_NONE : stm32wbxx_ll_crc.h
  • LL_CRC_POLYLENGTH_16B : stm32wbxx_ll_crc.h
  • LL_CRC_POLYLENGTH_32B : stm32wbxx_ll_crc.h
  • LL_CRC_POLYLENGTH_7B : stm32wbxx_ll_crc.h
  • LL_CRC_POLYLENGTH_8B : stm32wbxx_ll_crc.h
  • LL_CRC_Read_IDR() : stm32wbxx_ll_crc.h
  • LL_CRC_ReadData16() : stm32wbxx_ll_crc.h
  • LL_CRC_ReadData32() : stm32wbxx_ll_crc.h
  • LL_CRC_ReadData7() : stm32wbxx_ll_crc.h
  • LL_CRC_ReadData8() : stm32wbxx_ll_crc.h
  • LL_CRC_ReadReg : stm32wbxx_ll_crc.h
  • LL_CRC_ResetCRCCalculationUnit() : stm32wbxx_ll_crc.h
  • LL_CRC_SetInitialData() : stm32wbxx_ll_crc.h
  • LL_CRC_SetInputDataReverseMode() : stm32wbxx_ll_crc.h
  • LL_CRC_SetOutputDataReverseMode() : stm32wbxx_ll_crc.h
  • LL_CRC_SetPolynomialCoef() : stm32wbxx_ll_crc.h
  • LL_CRC_SetPolynomialSize() : stm32wbxx_ll_crc.h
  • LL_CRC_Write_IDR() : stm32wbxx_ll_crc.h
  • LL_CRC_WriteReg : stm32wbxx_ll_crc.h
  • LL_CRS_ClearFlag_ERR() : stm32wbxx_ll_crs.h
  • LL_CRS_ClearFlag_ESYNC() : stm32wbxx_ll_crs.h
  • LL_CRS_ClearFlag_SYNCOK() : stm32wbxx_ll_crs.h
  • LL_CRS_ClearFlag_SYNCWARN() : stm32wbxx_ll_crs.h
  • LL_CRS_ConfigSynchronization() : stm32wbxx_ll_crs.h
  • LL_CRS_CR_ERRIE : stm32wbxx_ll_crs.h
  • LL_CRS_CR_ESYNCIE : stm32wbxx_ll_crs.h
  • LL_CRS_CR_SYNCOKIE : stm32wbxx_ll_crs.h
  • LL_CRS_CR_SYNCWARNIE : stm32wbxx_ll_crs.h
  • LL_CRS_DeInit() : stm32wbxx_ll_crs.c
  • LL_CRS_DisableAutoTrimming() : stm32wbxx_ll_crs.h
  • LL_CRS_DisableFreqErrorCounter() : stm32wbxx_ll_crs.h
  • LL_CRS_DisableIT_ERR() : stm32wbxx_ll_crs.h
  • LL_CRS_DisableIT_ESYNC() : stm32wbxx_ll_crs.h
  • LL_CRS_DisableIT_SYNCOK() : stm32wbxx_ll_crs.h
  • LL_CRS_DisableIT_SYNCWARN() : stm32wbxx_ll_crs.h
  • LL_CRS_EnableAutoTrimming() : stm32wbxx_ll_crs.h
  • LL_CRS_EnableFreqErrorCounter() : stm32wbxx_ll_crs.h
  • LL_CRS_EnableIT_ERR() : stm32wbxx_ll_crs.h
  • LL_CRS_EnableIT_ESYNC() : stm32wbxx_ll_crs.h
  • LL_CRS_EnableIT_SYNCOK() : stm32wbxx_ll_crs.h
  • LL_CRS_EnableIT_SYNCWARN() : stm32wbxx_ll_crs.h
  • LL_CRS_ERRORLIMIT_DEFAULT : stm32wbxx_ll_crs.h
  • LL_CRS_FREQ_ERROR_DIR_DOWN : stm32wbxx_ll_crs.h
  • LL_CRS_FREQ_ERROR_DIR_UP : stm32wbxx_ll_crs.h
  • LL_CRS_GenerateEvent_SWSYNC() : stm32wbxx_ll_crs.h
  • LL_CRS_GetFreqErrorCapture() : stm32wbxx_ll_crs.h
  • LL_CRS_GetFreqErrorDirection() : stm32wbxx_ll_crs.h
  • LL_CRS_GetFreqErrorLimit() : stm32wbxx_ll_crs.h
  • LL_CRS_GetHSI48SmoothTrimming() : stm32wbxx_ll_crs.h
  • LL_CRS_GetReloadCounter() : stm32wbxx_ll_crs.h
  • LL_CRS_GetSyncDivider() : stm32wbxx_ll_crs.h
  • LL_CRS_GetSyncPolarity() : stm32wbxx_ll_crs.h
  • LL_CRS_GetSyncSignalSource() : stm32wbxx_ll_crs.h
  • LL_CRS_HSI48CALIBRATION_DEFAULT : stm32wbxx_ll_crs.h
  • LL_CRS_IsActiveFlag_ERR() : stm32wbxx_ll_crs.h
  • LL_CRS_IsActiveFlag_ESYNC() : stm32wbxx_ll_crs.h
  • LL_CRS_IsActiveFlag_SYNCERR() : stm32wbxx_ll_crs.h
  • LL_CRS_IsActiveFlag_SYNCMISS() : stm32wbxx_ll_crs.h
  • LL_CRS_IsActiveFlag_SYNCOK() : stm32wbxx_ll_crs.h
  • LL_CRS_IsActiveFlag_SYNCWARN() : stm32wbxx_ll_crs.h
  • LL_CRS_IsActiveFlag_TRIMOVF() : stm32wbxx_ll_crs.h
  • LL_CRS_IsEnabledAutoTrimming() : stm32wbxx_ll_crs.h
  • LL_CRS_IsEnabledFreqErrorCounter() : stm32wbxx_ll_crs.h
  • LL_CRS_IsEnabledIT_ERR() : stm32wbxx_ll_crs.h
  • LL_CRS_IsEnabledIT_ESYNC() : stm32wbxx_ll_crs.h
  • LL_CRS_IsEnabledIT_SYNCOK() : stm32wbxx_ll_crs.h
  • LL_CRS_IsEnabledIT_SYNCWARN() : stm32wbxx_ll_crs.h
  • LL_CRS_ISR_ERRF : stm32wbxx_ll_crs.h
  • LL_CRS_ISR_ESYNCF : stm32wbxx_ll_crs.h
  • LL_CRS_ISR_SYNCERR : stm32wbxx_ll_crs.h
  • LL_CRS_ISR_SYNCMISS : stm32wbxx_ll_crs.h
  • LL_CRS_ISR_SYNCOKF : stm32wbxx_ll_crs.h
  • LL_CRS_ISR_SYNCWARNF : stm32wbxx_ll_crs.h
  • LL_CRS_ISR_TRIMOVF : stm32wbxx_ll_crs.h
  • LL_CRS_ReadReg : stm32wbxx_ll_crs.h
  • LL_CRS_RELOADVALUE_DEFAULT : stm32wbxx_ll_crs.h
  • LL_CRS_SetFreqErrorLimit() : stm32wbxx_ll_crs.h
  • LL_CRS_SetHSI48SmoothTrimming() : stm32wbxx_ll_crs.h
  • LL_CRS_SetReloadCounter() : stm32wbxx_ll_crs.h
  • LL_CRS_SetSyncDivider() : stm32wbxx_ll_crs.h
  • LL_CRS_SetSyncPolarity() : stm32wbxx_ll_crs.h
  • LL_CRS_SetSyncSignalSource() : stm32wbxx_ll_crs.h
  • LL_CRS_SYNC_DIV_1 : stm32wbxx_ll_crs.h
  • LL_CRS_SYNC_DIV_128 : stm32wbxx_ll_crs.h
  • LL_CRS_SYNC_DIV_16 : stm32wbxx_ll_crs.h
  • LL_CRS_SYNC_DIV_2 : stm32wbxx_ll_crs.h
  • LL_CRS_SYNC_DIV_32 : stm32wbxx_ll_crs.h
  • LL_CRS_SYNC_DIV_4 : stm32wbxx_ll_crs.h
  • LL_CRS_SYNC_DIV_64 : stm32wbxx_ll_crs.h
  • LL_CRS_SYNC_DIV_8 : stm32wbxx_ll_crs.h
  • LL_CRS_SYNC_POLARITY_FALLING : stm32wbxx_ll_crs.h
  • LL_CRS_SYNC_POLARITY_RISING : stm32wbxx_ll_crs.h
  • LL_CRS_SYNC_SOURCE_GPIO : stm32wbxx_ll_crs.h
  • LL_CRS_SYNC_SOURCE_LSE : stm32wbxx_ll_crs.h
  • LL_CRS_SYNC_SOURCE_USB : stm32wbxx_ll_crs.h
  • LL_CRS_WriteReg : stm32wbxx_ll_crs.h
  • LL_DBGMCU_APB1_GRP1_FreezePeriph() : stm32wbxx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_I2C1_STOP : stm32wbxx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_I2C3_STOP : stm32wbxx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_IWDG_STOP : stm32wbxx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_LPTIM1_STOP : stm32wbxx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_RTC_STOP : stm32wbxx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM2_STOP : stm32wbxx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_UnFreezePeriph() : stm32wbxx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_WWDG_STOP : stm32wbxx_ll_system.h
  • LL_DBGMCU_APB1_GRP2_FreezePeriph() : stm32wbxx_ll_system.h
  • LL_DBGMCU_APB1_GRP2_LPTIM2_STOP : stm32wbxx_ll_system.h
  • LL_DBGMCU_APB1_GRP2_UnFreezePeriph() : stm32wbxx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_FreezePeriph() : stm32wbxx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM16_STOP : stm32wbxx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM17_STOP : stm32wbxx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM1_STOP : stm32wbxx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_UnFreezePeriph() : stm32wbxx_ll_system.h
  • LL_DBGMCU_DisableDBGSleepMode() : stm32wbxx_ll_system.h
  • LL_DBGMCU_DisableDBGStandbyMode() : stm32wbxx_ll_system.h
  • LL_DBGMCU_DisableDBGStopMode() : stm32wbxx_ll_system.h
  • LL_DBGMCU_DisableTraceClock() : stm32wbxx_ll_system.h
  • LL_DBGMCU_DisableTriggerOutput() : stm32wbxx_ll_system.h
  • LL_DBGMCU_EnableDBGSleepMode() : stm32wbxx_ll_system.h
  • LL_DBGMCU_EnableDBGStandbyMode() : stm32wbxx_ll_system.h
  • LL_DBGMCU_EnableDBGStopMode() : stm32wbxx_ll_system.h
  • LL_DBGMCU_EnableTraceClock() : stm32wbxx_ll_system.h
  • LL_DBGMCU_EnableTriggerOutput() : stm32wbxx_ll_system.h
  • LL_DBGMCU_GetDeviceID() : stm32wbxx_ll_system.h
  • LL_DBGMCU_GetRevisionID() : stm32wbxx_ll_system.h
  • LL_DBGMCU_IsEnabledTraceClock() : stm32wbxx_ll_system.h
  • LL_DBGMCU_IsEnabledTriggerOutput() : stm32wbxx_ll_system.h
  • LL_DMA_CCR_HTIE : stm32wbxx_ll_dma.h
  • LL_DMA_CCR_TCIE : stm32wbxx_ll_dma.h
  • LL_DMA_CCR_TEIE : stm32wbxx_ll_dma.h
  • LL_DMA_CHANNEL_1 : stm32wbxx_ll_dma.h
  • LL_DMA_CHANNEL_2 : stm32wbxx_ll_dma.h
  • LL_DMA_CHANNEL_3 : stm32wbxx_ll_dma.h
  • LL_DMA_CHANNEL_4 : stm32wbxx_ll_dma.h
  • LL_DMA_CHANNEL_5 : stm32wbxx_ll_dma.h
  • LL_DMA_CHANNEL_6 : stm32wbxx_ll_dma.h
  • LL_DMA_CHANNEL_7 : stm32wbxx_ll_dma.h
  • LL_DMA_CHANNEL_ALL : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_GI1() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_GI2() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_GI3() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_GI4() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_GI5() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_GI6() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_GI7() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_HT1() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_HT2() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_HT3() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_HT4() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_HT5() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_HT6() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_HT7() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_TC1() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_TC2() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_TC3() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_TC4() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_TC5() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_TC6() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_TC7() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_TE1() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_TE2() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_TE3() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_TE4() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_TE5() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_TE6() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_TE7() : stm32wbxx_ll_dma.h
  • LL_DMA_ConfigAddresses() : stm32wbxx_ll_dma.h
  • LL_DMA_ConfigTransfer() : stm32wbxx_ll_dma.h
  • LL_DMA_DeInit() : stm32wbxx_ll_dma.c
  • LL_DMA_DIRECTION_MEMORY_TO_MEMORY : stm32wbxx_ll_dma.h
  • LL_DMA_DIRECTION_MEMORY_TO_PERIPH : stm32wbxx_ll_dma.h
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY : stm32wbxx_ll_dma.h
  • LL_DMA_DisableChannel() : stm32wbxx_ll_dma.h
  • LL_DMA_DisableIT_HT() : stm32wbxx_ll_dma.h
  • LL_DMA_DisableIT_TC() : stm32wbxx_ll_dma.h
  • LL_DMA_DisableIT_TE() : stm32wbxx_ll_dma.h
  • LL_DMA_EnableChannel() : stm32wbxx_ll_dma.h
  • LL_DMA_EnableIT_HT() : stm32wbxx_ll_dma.h
  • LL_DMA_EnableIT_TC() : stm32wbxx_ll_dma.h
  • LL_DMA_EnableIT_TE() : stm32wbxx_ll_dma.h
  • LL_DMA_GetChannelPriorityLevel() : stm32wbxx_ll_dma.h
  • LL_DMA_GetDataLength() : stm32wbxx_ll_dma.h
  • LL_DMA_GetDataTransferDirection() : stm32wbxx_ll_dma.h
  • LL_DMA_GetM2MDstAddress() : stm32wbxx_ll_dma.h
  • LL_DMA_GetM2MSrcAddress() : stm32wbxx_ll_dma.h
  • LL_DMA_GetMemoryAddress() : stm32wbxx_ll_dma.h
  • LL_DMA_GetMemoryIncMode() : stm32wbxx_ll_dma.h
  • LL_DMA_GetMemorySize() : stm32wbxx_ll_dma.h
  • LL_DMA_GetMode() : stm32wbxx_ll_dma.h
  • LL_DMA_GetPeriphAddress() : stm32wbxx_ll_dma.h
  • LL_DMA_GetPeriphIncMode() : stm32wbxx_ll_dma.h
  • LL_DMA_GetPeriphRequest() : stm32wbxx_ll_dma.h
  • LL_DMA_GetPeriphSize() : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CGIF1 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CGIF2 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CGIF3 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CGIF4 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CGIF5 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CGIF6 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CGIF7 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CHTIF1 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CHTIF2 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CHTIF3 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CHTIF4 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CHTIF5 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CHTIF6 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CHTIF7 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CTCIF1 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CTCIF2 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CTCIF3 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CTCIF4 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CTCIF5 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CTCIF6 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CTCIF7 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CTEIF1 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CTEIF2 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CTEIF3 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CTEIF4 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CTEIF5 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CTEIF6 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CTEIF7 : stm32wbxx_ll_dma.h
  • LL_DMA_Init() : stm32wbxx_ll_dma.c
  • LL_DMA_IsActiveFlag_GI1() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI2() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI3() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI4() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI5() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI6() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI7() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT1() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT2() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT3() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT4() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT5() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT6() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT7() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC1() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC2() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC3() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC4() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC5() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC6() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC7() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE1() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE2() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE3() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE4() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE5() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE6() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE7() : stm32wbxx_ll_dma.h
  • LL_DMA_IsEnabledChannel() : stm32wbxx_ll_dma.h
  • LL_DMA_IsEnabledIT_HT() : stm32wbxx_ll_dma.h
  • LL_DMA_IsEnabledIT_TC() : stm32wbxx_ll_dma.h
  • LL_DMA_IsEnabledIT_TE() : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_GIF1 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_GIF2 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_GIF3 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_GIF4 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_GIF5 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_GIF6 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_GIF7 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_HTIF1 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_HTIF2 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_HTIF3 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_HTIF4 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_HTIF5 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_HTIF6 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_HTIF7 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_TCIF1 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_TCIF2 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_TCIF3 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_TCIF4 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_TCIF5 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_TCIF6 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_TCIF7 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_TEIF1 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_TEIF2 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_TEIF3 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_TEIF4 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_TEIF5 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_TEIF6 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_TEIF7 : stm32wbxx_ll_dma.h
  • LL_DMA_MDATAALIGN_BYTE : stm32wbxx_ll_dma.h
  • LL_DMA_MDATAALIGN_HALFWORD : stm32wbxx_ll_dma.h
  • LL_DMA_MDATAALIGN_WORD : stm32wbxx_ll_dma.h
  • LL_DMA_MEMORY_INCREMENT : stm32wbxx_ll_dma.h
  • LL_DMA_MEMORY_NOINCREMENT : stm32wbxx_ll_dma.h
  • LL_DMA_MODE_CIRCULAR : stm32wbxx_ll_dma.h
  • LL_DMA_MODE_NORMAL : stm32wbxx_ll_dma.h
  • LL_DMA_PDATAALIGN_BYTE : stm32wbxx_ll_dma.h
  • LL_DMA_PDATAALIGN_HALFWORD : stm32wbxx_ll_dma.h
  • LL_DMA_PDATAALIGN_WORD : stm32wbxx_ll_dma.h
  • LL_DMA_PERIPH_INCREMENT : stm32wbxx_ll_dma.h
  • LL_DMA_PERIPH_NOINCREMENT : stm32wbxx_ll_dma.h
  • LL_DMA_PRIORITY_HIGH : stm32wbxx_ll_dma.h
  • LL_DMA_PRIORITY_LOW : stm32wbxx_ll_dma.h
  • LL_DMA_PRIORITY_MEDIUM : stm32wbxx_ll_dma.h
  • LL_DMA_PRIORITY_VERYHIGH : stm32wbxx_ll_dma.h
  • LL_DMA_ReadReg : stm32wbxx_ll_dma.h
  • LL_DMA_SetChannelPriorityLevel() : stm32wbxx_ll_dma.h
  • LL_DMA_SetDataLength() : stm32wbxx_ll_dma.h
  • LL_DMA_SetDataTransferDirection() : stm32wbxx_ll_dma.h
  • LL_DMA_SetM2MDstAddress() : stm32wbxx_ll_dma.h
  • LL_DMA_SetM2MSrcAddress() : stm32wbxx_ll_dma.h
  • LL_DMA_SetMemoryAddress() : stm32wbxx_ll_dma.h
  • LL_DMA_SetMemoryIncMode() : stm32wbxx_ll_dma.h
  • LL_DMA_SetMemorySize() : stm32wbxx_ll_dma.h
  • LL_DMA_SetMode() : stm32wbxx_ll_dma.h
  • LL_DMA_SetPeriphAddress() : stm32wbxx_ll_dma.h
  • LL_DMA_SetPeriphIncMode() : stm32wbxx_ll_dma.h
  • LL_DMA_SetPeriphRequest() : stm32wbxx_ll_dma.h
  • LL_DMA_SetPeriphSize() : stm32wbxx_ll_dma.h
  • LL_DMA_StructInit() : stm32wbxx_ll_dma.c
  • LL_DMA_WriteReg : stm32wbxx_ll_dma.h
  • LL_DMAMUX_CCR_SOIE : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF0 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF1 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF10 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF11 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF12 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF13 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF2 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF3 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF4 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF5 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF6 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF7 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF8 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF9 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_0 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_1 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_10 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_11 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_12 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_13 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_2 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_3 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_4 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_5 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_6 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_7 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_8 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_9 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_RGO0() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_RGO1() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_RGO2() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_RGO3() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO0() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO1() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO10() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO11() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO12() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO13() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO2() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO3() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO4() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO5() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO6() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO7() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO8() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO9() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF0 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF1 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF10 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF11 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF12 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF13 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF2 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF3 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF4 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF5 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF6 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF7 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF8 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF9 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_DisableEventGeneration() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_DisableIT_RGO() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_DisableIT_SO() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_DisableRequestGen() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_DisableSync() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_EnableEventGeneration() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_EnableIT_RGO() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_EnableIT_SO() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_EnableRequestGen() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_EnableSync() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_GetGenRequestNb() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_GetRequestGenPolarity() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_GetRequestID() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_GetRequestSignalID() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_GetSyncID() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_GetSyncPolarity() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_GetSyncRequestNb() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO0() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO1() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO2() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO3() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO0() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO1() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO10() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO11() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO12() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO13() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO2() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO3() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO4() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO5() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO6() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO7() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO8() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO9() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledEventGeneration() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledIT_RGO() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledIT_SO() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledRequestGen() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledSync() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_ReadReg : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_ADC1 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_AES1_IN : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_AES1_OUT : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_AES2_IN : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_AES2_OUT : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_0 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_1 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_2 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_3 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH0 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH1 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE0 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE1 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE10 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE11 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE12 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE13 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE14 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE15 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE2 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE3 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE4 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE5 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE6 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE7 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE8 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE9 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_LPTIM1_OUT : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_LPTIM2_OUT : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_NO_EVENT : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_POL_FALLING : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_POL_RISING : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_POL_RISING_FALLING : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GENERATOR0 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GENERATOR1 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GENERATOR2 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GENERATOR3 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_I2C1_RX : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_I2C1_TX : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_I2C3_RX : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_I2C3_TX : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_LPUART1_RX : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_LPUART1_TX : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_MEM2MEM : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_QUADSPI : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_SAI1_A : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_SAI1_B : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_SPI1_RX : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_SPI1_TX : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_SPI2_RX : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_SPI2_TX : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM16_CH1 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM16_UP : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM17_CH1 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM17_UP : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_CH1 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_CH2 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_CH3 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_CH4 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_COM : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_TRIG : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_UP : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM2_CH1 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM2_CH2 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM2_CH3 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM2_CH4 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM2_UP : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART1_RX : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART1_TX : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF0 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF1 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF2 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF3 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_RGCR_RGOIE : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF0 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF1 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF2 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF3 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SetGenRequestNb() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SetRequestGenPolarity() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SetRequestID() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SetRequestSignalID() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SetSyncID() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SetSyncPolarity() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SetSyncRequestNb() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_DMAMUX_CH0 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_DMAMUX_CH1 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE0 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE1 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE10 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE11 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE12 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE13 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE14 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE15 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE2 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE3 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE4 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE5 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE6 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE7 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE8 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE9 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_LPTIM1_OUT : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_LPTIM2_OUT : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_NO_EVENT : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_POL_FALLING : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_POL_RISING : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_POL_RISING_FALLING : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_WriteReg : stm32wbxx_ll_dmamux.h
  • LL_EXTI_ClearFlag_0_31() : stm32wbxx_ll_exti.h
  • LL_EXTI_ClearFlag_32_63() : stm32wbxx_ll_exti.h
  • LL_EXTI_DeInit() : stm32wbxx_ll_exti.c
  • LL_EXTI_DisableEvent_0_31() : stm32wbxx_ll_exti.h
  • LL_EXTI_DisableEvent_32_63() : stm32wbxx_ll_exti.h
  • LL_EXTI_DisableFallingTrig_0_31() : stm32wbxx_ll_exti.h
  • LL_EXTI_DisableFallingTrig_32_63() : stm32wbxx_ll_exti.h
  • LL_EXTI_DisableIT_0_31() : stm32wbxx_ll_exti.h
  • LL_EXTI_DisableIT_32_63() : stm32wbxx_ll_exti.h
  • LL_EXTI_DisableRisingTrig_0_31() : stm32wbxx_ll_exti.h
  • LL_EXTI_DisableRisingTrig_32_63() : stm32wbxx_ll_exti.h
  • LL_EXTI_EnableEvent_0_31() : stm32wbxx_ll_exti.h
  • LL_EXTI_EnableEvent_32_63() : stm32wbxx_ll_exti.h
  • LL_EXTI_EnableFallingTrig_0_31() : stm32wbxx_ll_exti.h
  • LL_EXTI_EnableFallingTrig_32_63() : stm32wbxx_ll_exti.h
  • LL_EXTI_EnableIT_0_31() : stm32wbxx_ll_exti.h
  • LL_EXTI_EnableIT_32_63() : stm32wbxx_ll_exti.h
  • LL_EXTI_EnableRisingTrig_0_31() : stm32wbxx_ll_exti.h
  • LL_EXTI_EnableRisingTrig_32_63() : stm32wbxx_ll_exti.h
  • LL_EXTI_GenerateSWI_0_31() : stm32wbxx_ll_exti.h
  • LL_EXTI_GenerateSWI_32_63() : stm32wbxx_ll_exti.h
  • LL_EXTI_Init() : stm32wbxx_ll_exti.c
  • LL_EXTI_IsActiveFlag_0_31() : stm32wbxx_ll_exti.h
  • LL_EXTI_IsActiveFlag_32_63() : stm32wbxx_ll_exti.h
  • LL_EXTI_IsEnabledEvent_0_31() : stm32wbxx_ll_exti.h
  • LL_EXTI_IsEnabledEvent_32_63() : stm32wbxx_ll_exti.h
  • LL_EXTI_IsEnabledFallingTrig_0_31() : stm32wbxx_ll_exti.h
  • LL_EXTI_IsEnabledFallingTrig_32_63() : stm32wbxx_ll_exti.h
  • LL_EXTI_IsEnabledIT_0_31() : stm32wbxx_ll_exti.h
  • LL_EXTI_IsEnabledIT_32_63() : stm32wbxx_ll_exti.h
  • LL_EXTI_IsEnabledRisingTrig_0_31() : stm32wbxx_ll_exti.h
  • LL_EXTI_IsEnabledRisingTrig_32_63() : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_0 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_1 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_10 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_11 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_12 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_13 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_14 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_15 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_16 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_17 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_18 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_19 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_2 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_20 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_21 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_22 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_23 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_24 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_25 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_28 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_29 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_3 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_30 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_31 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_33 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_36 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_37 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_38 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_39 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_4 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_40 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_41 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_42 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_43 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_44 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_45 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_46 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_48 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_5 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_6 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_7 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_8 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_9 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_ALL : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_ALL_0_31 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_ALL_32_63 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_NONE : stm32wbxx_ll_exti.h
  • LL_EXTI_MODE_EVENT : stm32wbxx_ll_exti.h
  • LL_EXTI_MODE_IT : stm32wbxx_ll_exti.h
  • LL_EXTI_MODE_IT_EVENT : stm32wbxx_ll_exti.h
  • LL_EXTI_ReadFlag_0_31() : stm32wbxx_ll_exti.h
  • LL_EXTI_ReadFlag_32_63() : stm32wbxx_ll_exti.h
  • LL_EXTI_ReadReg : stm32wbxx_ll_exti.h
  • LL_EXTI_StructInit() : stm32wbxx_ll_exti.c
  • LL_EXTI_TRIGGER_FALLING : stm32wbxx_ll_exti.h
  • LL_EXTI_TRIGGER_NONE : stm32wbxx_ll_exti.h
  • LL_EXTI_TRIGGER_RISING : stm32wbxx_ll_exti.h
  • LL_EXTI_TRIGGER_RISING_FALLING : stm32wbxx_ll_exti.h
  • LL_EXTI_WriteReg : stm32wbxx_ll_exti.h
  • LL_FLASH_AllowOperation() : stm32wbxx_ll_system.h
  • LL_FLASH_ClearEmptyFlag() : stm32wbxx_ll_system.h
  • LL_FLASH_DisableDataCache() : stm32wbxx_ll_system.h
  • LL_FLASH_DisableDataCacheReset() : stm32wbxx_ll_system.h
  • LL_FLASH_DisableInstCache() : stm32wbxx_ll_system.h
  • LL_FLASH_DisableInstCacheReset() : stm32wbxx_ll_system.h
  • LL_FLASH_DisablePrefetch() : stm32wbxx_ll_system.h
  • LL_FLASH_EnableDataCache() : stm32wbxx_ll_system.h
  • LL_FLASH_EnableDataCacheReset() : stm32wbxx_ll_system.h
  • LL_FLASH_EnableInstCache() : stm32wbxx_ll_system.h
  • LL_FLASH_EnableInstCacheReset() : stm32wbxx_ll_system.h
  • LL_FLASH_EnablePrefetch() : stm32wbxx_ll_system.h
  • LL_FLASH_GetC2BootResetVect() : stm32wbxx_ll_system.h
  • LL_FLASH_GetDeviceID() : stm32wbxx_ll_system.h
  • LL_FLASH_GetIPCCBufferAddr() : stm32wbxx_ll_system.h
  • LL_FLASH_GetLatency() : stm32wbxx_ll_system.h
  • LL_FLASH_GetSTCompanyID() : stm32wbxx_ll_system.h
  • LL_FLASH_GetUDN() : stm32wbxx_ll_system.h
  • LL_FLASH_IsActiveFlag_OperationSuspended() : stm32wbxx_ll_system.h
  • LL_FLASH_IsEmptyFlag() : stm32wbxx_ll_system.h
  • LL_FLASH_IsOperationSuspended() : stm32wbxx_ll_system.h
  • LL_FLASH_IsPrefetchEnabled() : stm32wbxx_ll_system.h
  • LL_FLASH_LATENCY_0 : stm32wbxx_ll_system.h
  • LL_FLASH_LATENCY_1 : stm32wbxx_ll_system.h
  • LL_FLASH_LATENCY_2 : stm32wbxx_ll_system.h
  • LL_FLASH_LATENCY_3 : stm32wbxx_ll_system.h
  • LL_FLASH_SetEmptyFlag() : stm32wbxx_ll_system.h
  • LL_FLASH_SetLatency() : stm32wbxx_ll_system.h
  • LL_FLASH_SuspendOperation() : stm32wbxx_ll_system.h
  • LL_GetFlashSize() : stm32wbxx_ll_utils.h
  • LL_GetPackageType() : stm32wbxx_ll_utils.h
  • LL_GetUID_Word0() : stm32wbxx_ll_utils.h
  • LL_GetUID_Word1() : stm32wbxx_ll_utils.h
  • LL_GetUID_Word2() : stm32wbxx_ll_utils.h
  • LL_GPIO_AF_0 : stm32wbxx_ll_gpio.h
  • LL_GPIO_AF_1 : stm32wbxx_ll_gpio.h
  • LL_GPIO_AF_10 : stm32wbxx_ll_gpio.h
  • LL_GPIO_AF_11 : stm32wbxx_ll_gpio.h
  • LL_GPIO_AF_12 : stm32wbxx_ll_gpio.h
  • LL_GPIO_AF_13 : stm32wbxx_ll_gpio.h
  • LL_GPIO_AF_14 : stm32wbxx_ll_gpio.h
  • LL_GPIO_AF_15 : stm32wbxx_ll_gpio.h
  • LL_GPIO_AF_2 : stm32wbxx_ll_gpio.h
  • LL_GPIO_AF_3 : stm32wbxx_ll_gpio.h
  • LL_GPIO_AF_4 : stm32wbxx_ll_gpio.h
  • LL_GPIO_AF_5 : stm32wbxx_ll_gpio.h
  • LL_GPIO_AF_6 : stm32wbxx_ll_gpio.h
  • LL_GPIO_AF_7 : stm32wbxx_ll_gpio.h
  • LL_GPIO_AF_8 : stm32wbxx_ll_gpio.h
  • LL_GPIO_AF_9 : stm32wbxx_ll_gpio.h
  • LL_GPIO_DeInit() : stm32wbxx_ll_gpio.c
  • LL_GPIO_GetAFPin_0_7() : stm32wbxx_ll_gpio.h
  • LL_GPIO_GetAFPin_8_15() : stm32wbxx_ll_gpio.h
  • LL_GPIO_GetPinMode() : stm32wbxx_ll_gpio.h
  • LL_GPIO_GetPinOutputType() : stm32wbxx_ll_gpio.h
  • LL_GPIO_GetPinPull() : stm32wbxx_ll_gpio.h
  • LL_GPIO_GetPinSpeed() : stm32wbxx_ll_gpio.h
  • LL_GPIO_Init() : stm32wbxx_ll_gpio.c
  • LL_GPIO_IsAnyPinLocked() : stm32wbxx_ll_gpio.h
  • LL_GPIO_IsInputPinSet() : stm32wbxx_ll_gpio.h
  • LL_GPIO_IsOutputPinSet() : stm32wbxx_ll_gpio.h
  • LL_GPIO_IsPinLocked() : stm32wbxx_ll_gpio.h
  • LL_GPIO_LockPin() : stm32wbxx_ll_gpio.h
  • LL_GPIO_MODE_ALTERNATE : stm32wbxx_ll_gpio.h
  • LL_GPIO_MODE_ANALOG : stm32wbxx_ll_gpio.h
  • LL_GPIO_MODE_INPUT : stm32wbxx_ll_gpio.h
  • LL_GPIO_MODE_OUTPUT : stm32wbxx_ll_gpio.h
  • LL_GPIO_OUTPUT_OPENDRAIN : stm32wbxx_ll_gpio.h
  • LL_GPIO_OUTPUT_PUSHPULL : stm32wbxx_ll_gpio.h
  • LL_GPIO_PIN_0 : stm32wbxx_ll_gpio.h
  • LL_GPIO_PIN_1 : stm32wbxx_ll_gpio.h
  • LL_GPIO_PIN_10 : stm32wbxx_ll_gpio.h
  • LL_GPIO_PIN_11 : stm32wbxx_ll_gpio.h
  • LL_GPIO_PIN_12 : stm32wbxx_ll_gpio.h
  • LL_GPIO_PIN_13 : stm32wbxx_ll_gpio.h
  • LL_GPIO_PIN_14 : stm32wbxx_ll_gpio.h
  • LL_GPIO_PIN_15 : stm32wbxx_ll_gpio.h
  • LL_GPIO_PIN_2 : stm32wbxx_ll_gpio.h
  • LL_GPIO_PIN_3 : stm32wbxx_ll_gpio.h
  • LL_GPIO_PIN_4 : stm32wbxx_ll_gpio.h
  • LL_GPIO_PIN_5 : stm32wbxx_ll_gpio.h
  • LL_GPIO_PIN_6 : stm32wbxx_ll_gpio.h
  • LL_GPIO_PIN_7 : stm32wbxx_ll_gpio.h
  • LL_GPIO_PIN_8 : stm32wbxx_ll_gpio.h
  • LL_GPIO_PIN_9 : stm32wbxx_ll_gpio.h
  • LL_GPIO_PIN_ALL : stm32wbxx_ll_gpio.h
  • LL_GPIO_PULL_DOWN : stm32wbxx_ll_gpio.h
  • LL_GPIO_PULL_NO : stm32wbxx_ll_gpio.h
  • LL_GPIO_PULL_UP : stm32wbxx_ll_gpio.h
  • LL_GPIO_ReadInputPort() : stm32wbxx_ll_gpio.h
  • LL_GPIO_ReadOutputPort() : stm32wbxx_ll_gpio.h
  • LL_GPIO_ReadReg : stm32wbxx_ll_gpio.h
  • LL_GPIO_ResetOutputPin() : stm32wbxx_ll_gpio.h
  • LL_GPIO_SetAFPin_0_7() : stm32wbxx_ll_gpio.h
  • LL_GPIO_SetAFPin_8_15() : stm32wbxx_ll_gpio.h
  • LL_GPIO_SetOutputPin() : stm32wbxx_ll_gpio.h
  • LL_GPIO_SetPinMode() : stm32wbxx_ll_gpio.h
  • LL_GPIO_SetPinOutputType() : stm32wbxx_ll_gpio.h
  • LL_GPIO_SetPinPull() : stm32wbxx_ll_gpio.h
  • LL_GPIO_SetPinSpeed() : stm32wbxx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_HIGH : stm32wbxx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_LOW : stm32wbxx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_MEDIUM : stm32wbxx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_VERY_HIGH : stm32wbxx_ll_gpio.h
  • LL_GPIO_StructInit() : stm32wbxx_ll_gpio.c
  • LL_GPIO_TogglePin() : stm32wbxx_ll_gpio.h
  • LL_GPIO_WriteOutputPort() : stm32wbxx_ll_gpio.h
  • LL_GPIO_WriteReg : stm32wbxx_ll_gpio.h
  • LL_HANDLER_DisableFault() : stm32wbxx_ll_cortex.h
  • LL_HANDLER_EnableFault() : stm32wbxx_ll_cortex.h
  • LL_HANDLER_FAULT_BUS : stm32wbxx_ll_cortex.h
  • LL_HANDLER_FAULT_MEM : stm32wbxx_ll_cortex.h
  • LL_HANDLER_FAULT_USG : stm32wbxx_ll_cortex.h
  • LL_HSEM_1StepLock() : stm32wbxx_ll_hsem.h
  • LL_HSEM_2StepLock() : stm32wbxx_ll_hsem.h
  • LL_HSEM_ClearFlag_C1ICR() : stm32wbxx_ll_hsem.h
  • LL_HSEM_ClearFlag_C2ICR() : stm32wbxx_ll_hsem.h
  • LL_HSEM_COREID : stm32wbxx_ll_hsem.h
  • LL_HSEM_COREID_CPU1 : stm32wbxx_ll_hsem.h
  • LL_HSEM_COREID_CPU2 : stm32wbxx_ll_hsem.h
  • LL_HSEM_COREID_NONE : stm32wbxx_ll_hsem.h
  • LL_HSEM_DisableIT_C1IER() : stm32wbxx_ll_hsem.h
  • LL_HSEM_DisableIT_C2IER() : stm32wbxx_ll_hsem.h
  • LL_HSEM_EnableIT_C1IER() : stm32wbxx_ll_hsem.h
  • LL_HSEM_EnableIT_C2IER() : stm32wbxx_ll_hsem.h
  • LL_HSEM_GetCoreId() : stm32wbxx_ll_hsem.h
  • LL_HSEM_GetKey() : stm32wbxx_ll_hsem.h
  • LL_HSEM_GetProcessId() : stm32wbxx_ll_hsem.h
  • LL_HSEM_GetStatus() : stm32wbxx_ll_hsem.h
  • LL_HSEM_IsActiveFlag_C1ISR() : stm32wbxx_ll_hsem.h
  • LL_HSEM_IsActiveFlag_C1MISR() : stm32wbxx_ll_hsem.h
  • LL_HSEM_IsActiveFlag_C2ISR() : stm32wbxx_ll_hsem.h
  • LL_HSEM_IsActiveFlag_C2MISR() : stm32wbxx_ll_hsem.h
  • LL_HSEM_IsEnabledIT_C1IER() : stm32wbxx_ll_hsem.h
  • LL_HSEM_IsEnabledIT_C2IER() : stm32wbxx_ll_hsem.h
  • LL_HSEM_IsSemaphoreLocked() : stm32wbxx_ll_hsem.h
  • LL_HSEM_ReadReg : stm32wbxx_ll_hsem.h
  • LL_HSEM_ReleaseLock() : stm32wbxx_ll_hsem.h
  • LL_HSEM_ResetAllLock() : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_0 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_1 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_10 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_11 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_12 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_13 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_14 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_15 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_16 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_17 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_18 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_19 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_2 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_20 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_21 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_22 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_23 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_24 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_25 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_26 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_27 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_28 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_29 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_3 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_30 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_31 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_4 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_5 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_6 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_7 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_8 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_9 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_ALL : stm32wbxx_ll_hsem.h
  • LL_HSEM_SetKey() : stm32wbxx_ll_hsem.h
  • LL_HSEM_SetLock() : stm32wbxx_ll_hsem.h
  • LL_HSEM_WriteReg : stm32wbxx_ll_hsem.h
  • LL_I2C_ACK : stm32wbxx_ll_i2c.h
  • LL_I2C_AcknowledgeNextData() : stm32wbxx_ll_i2c.h
  • LL_I2C_ADDRESSING_MODE_10BIT : stm32wbxx_ll_i2c.h
  • LL_I2C_ADDRESSING_MODE_7BIT : stm32wbxx_ll_i2c.h
  • LL_I2C_ADDRSLAVE_10BIT : stm32wbxx_ll_i2c.h
  • LL_I2C_ADDRSLAVE_7BIT : stm32wbxx_ll_i2c.h
  • LL_I2C_ANALOGFILTER_DISABLE : stm32wbxx_ll_i2c.h
  • LL_I2C_ANALOGFILTER_ENABLE : stm32wbxx_ll_i2c.h
  • LL_I2C_ClearFlag_ADDR() : stm32wbxx_ll_i2c.h
  • LL_I2C_ClearFlag_ARLO() : stm32wbxx_ll_i2c.h
  • LL_I2C_ClearFlag_BERR() : stm32wbxx_ll_i2c.h
  • LL_I2C_ClearFlag_NACK() : stm32wbxx_ll_i2c.h
  • LL_I2C_ClearFlag_OVR() : stm32wbxx_ll_i2c.h
  • LL_I2C_ClearFlag_STOP() : stm32wbxx_ll_i2c.h
  • LL_I2C_ClearFlag_TXE() : stm32wbxx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_ALERT() : stm32wbxx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_PECERR() : stm32wbxx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_TIMEOUT() : stm32wbxx_ll_i2c.h
  • LL_I2C_ConfigFilters() : stm32wbxx_ll_i2c.h
  • LL_I2C_ConfigSMBusTimeout() : stm32wbxx_ll_i2c.h
  • LL_I2C_CR1_ADDRIE : stm32wbxx_ll_i2c.h
  • LL_I2C_CR1_ERRIE : stm32wbxx_ll_i2c.h
  • LL_I2C_CR1_NACKIE : stm32wbxx_ll_i2c.h
  • LL_I2C_CR1_RXIE : stm32wbxx_ll_i2c.h
  • LL_I2C_CR1_STOPIE : stm32wbxx_ll_i2c.h
  • LL_I2C_CR1_TCIE : stm32wbxx_ll_i2c.h
  • LL_I2C_CR1_TXIE : stm32wbxx_ll_i2c.h
  • LL_I2C_DeInit() : stm32wbxx_ll_i2c.c
  • LL_I2C_DIRECTION_READ : stm32wbxx_ll_i2c.h
  • LL_I2C_DIRECTION_WRITE : stm32wbxx_ll_i2c.h
  • LL_I2C_Disable() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableAnalogFilter() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableAuto10BitRead() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableAutoEndMode() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableClockStretching() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableDMAReq_RX() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableDMAReq_TX() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableGeneralCall() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableIT_ADDR() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableIT_ERR() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableIT_NACK() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableIT_RX() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableIT_STOP() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableIT_TC() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableIT_TX() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableOwnAddress1() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableOwnAddress2() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableReloadMode() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableSlaveByteControl() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableSMBusAlert() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableSMBusPEC() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableSMBusTimeout() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableWakeUpFromStop() : stm32wbxx_ll_i2c.h
  • LL_I2C_DMA_GetRegAddr() : stm32wbxx_ll_i2c.h
  • LL_I2C_DMA_REG_DATA_RECEIVE : stm32wbxx_ll_i2c.h
  • LL_I2C_DMA_REG_DATA_TRANSMIT : stm32wbxx_ll_i2c.h
  • LL_I2C_Enable() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableAnalogFilter() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableAuto10BitRead() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableAutoEndMode() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableClockStretching() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableDMAReq_RX() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableDMAReq_TX() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableGeneralCall() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableIT_ADDR() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableIT_ERR() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableIT_NACK() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableIT_RX() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableIT_STOP() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableIT_TC() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableIT_TX() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableOwnAddress1() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableOwnAddress2() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableReloadMode() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableSlaveByteControl() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableSMBusAlert() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableSMBusPEC() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableSMBusPECCompare() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableSMBusTimeout() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableWakeUpFromStop() : stm32wbxx_ll_i2c.h
  • LL_I2C_GENERATE_NOSTARTSTOP : stm32wbxx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_10BIT_READ : stm32wbxx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_10BIT_WRITE : stm32wbxx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_7BIT_READ : stm32wbxx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_7BIT_WRITE : stm32wbxx_ll_i2c.h
  • LL_I2C_GENERATE_START_READ : stm32wbxx_ll_i2c.h
  • LL_I2C_GENERATE_START_WRITE : stm32wbxx_ll_i2c.h
  • LL_I2C_GENERATE_STOP : stm32wbxx_ll_i2c.h
  • LL_I2C_GenerateStartCondition() : stm32wbxx_ll_i2c.h
  • LL_I2C_GenerateStopCondition() : stm32wbxx_ll_i2c.h
  • LL_I2C_GetAddressMatchCode() : stm32wbxx_ll_i2c.h
  • LL_I2C_GetClockHighPeriod() : stm32wbxx_ll_i2c.h
  • LL_I2C_GetClockLowPeriod() : stm32wbxx_ll_i2c.h
  • LL_I2C_GetDataHoldTime() : stm32wbxx_ll_i2c.h
  • LL_I2C_GetDataSetupTime() : stm32wbxx_ll_i2c.h
  • LL_I2C_GetDigitalFilter() : stm32wbxx_ll_i2c.h
  • LL_I2C_GetMasterAddressingMode() : stm32wbxx_ll_i2c.h
  • LL_I2C_GetMode() : stm32wbxx_ll_i2c.h
  • LL_I2C_GetSlaveAddr() : stm32wbxx_ll_i2c.h
  • LL_I2C_GetSMBusPEC() : stm32wbxx_ll_i2c.h
  • LL_I2C_GetSMBusTimeoutA() : stm32wbxx_ll_i2c.h
  • LL_I2C_GetSMBusTimeoutAMode() : stm32wbxx_ll_i2c.h
  • LL_I2C_GetSMBusTimeoutB() : stm32wbxx_ll_i2c.h
  • LL_I2C_GetTimingPrescaler() : stm32wbxx_ll_i2c.h
  • LL_I2C_GetTransferDirection() : stm32wbxx_ll_i2c.h
  • LL_I2C_GetTransferRequest() : stm32wbxx_ll_i2c.h
  • LL_I2C_GetTransferSize() : stm32wbxx_ll_i2c.h
  • LL_I2C_HandleTransfer() : stm32wbxx_ll_i2c.h
  • LL_I2C_ICR_ADDRCF : stm32wbxx_ll_i2c.h
  • LL_I2C_ICR_ALERTCF : stm32wbxx_ll_i2c.h
  • LL_I2C_ICR_ARLOCF : stm32wbxx_ll_i2c.h
  • LL_I2C_ICR_BERRCF : stm32wbxx_ll_i2c.h
  • LL_I2C_ICR_NACKCF : stm32wbxx_ll_i2c.h
  • LL_I2C_ICR_OVRCF : stm32wbxx_ll_i2c.h
  • LL_I2C_ICR_PECCF : stm32wbxx_ll_i2c.h
  • LL_I2C_ICR_STOPCF : stm32wbxx_ll_i2c.h
  • LL_I2C_ICR_TIMOUTCF : stm32wbxx_ll_i2c.h
  • LL_I2C_Init() : stm32wbxx_ll_i2c.c
  • LL_I2C_IsActiveFlag_ADDR() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsActiveFlag_ARLO() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsActiveFlag_BERR() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsActiveFlag_BUSY() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsActiveFlag_NACK() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsActiveFlag_OVR() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsActiveFlag_RXNE() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsActiveFlag_STOP() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TC() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TCR() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TXE() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TXIS() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_ALERT() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_PECERR() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_TIMEOUT() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabled() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledAnalogFilter() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledAuto10BitRead() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledAutoEndMode() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledClockStretching() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledDMAReq_RX() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledDMAReq_TX() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledGeneralCall() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledIT_ADDR() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledIT_ERR() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledIT_NACK() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledIT_RX() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledIT_STOP() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledIT_TC() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledIT_TX() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledOwnAddress1() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledOwnAddress2() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledReloadMode() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledSlaveByteControl() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusAlert() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusPEC() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusPECCompare() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusTimeout() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledWakeUpFromStop() : stm32wbxx_ll_i2c.h
  • LL_I2C_ISR_ADDR : stm32wbxx_ll_i2c.h
  • LL_I2C_ISR_ALERT : stm32wbxx_ll_i2c.h
  • LL_I2C_ISR_ARLO : stm32wbxx_ll_i2c.h
  • LL_I2C_ISR_BERR : stm32wbxx_ll_i2c.h
  • LL_I2C_ISR_BUSY : stm32wbxx_ll_i2c.h
  • LL_I2C_ISR_NACKF : stm32wbxx_ll_i2c.h
  • LL_I2C_ISR_OVR : stm32wbxx_ll_i2c.h
  • LL_I2C_ISR_PECERR : stm32wbxx_ll_i2c.h
  • LL_I2C_ISR_RXNE : stm32wbxx_ll_i2c.h
  • LL_I2C_ISR_STOPF : stm32wbxx_ll_i2c.h
  • LL_I2C_ISR_TC : stm32wbxx_ll_i2c.h
  • LL_I2C_ISR_TCR : stm32wbxx_ll_i2c.h
  • LL_I2C_ISR_TIMEOUT : stm32wbxx_ll_i2c.h
  • LL_I2C_ISR_TXE : stm32wbxx_ll_i2c.h
  • LL_I2C_ISR_TXIS : stm32wbxx_ll_i2c.h
  • LL_I2C_MODE_AUTOEND : stm32wbxx_ll_i2c.h
  • LL_I2C_MODE_I2C : stm32wbxx_ll_i2c.h
  • LL_I2C_MODE_RELOAD : stm32wbxx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC : stm32wbxx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC : stm32wbxx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_DEVICE : stm32wbxx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_DEVICE_ARP : stm32wbxx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_HOST : stm32wbxx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_RELOAD : stm32wbxx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC : stm32wbxx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC : stm32wbxx_ll_i2c.h
  • LL_I2C_MODE_SOFTEND : stm32wbxx_ll_i2c.h
  • LL_I2C_NACK : stm32wbxx_ll_i2c.h
  • LL_I2C_OWNADDRESS1_10BIT : stm32wbxx_ll_i2c.h
  • LL_I2C_OWNADDRESS1_7BIT : stm32wbxx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK01 : stm32wbxx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK02 : stm32wbxx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK03 : stm32wbxx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK04 : stm32wbxx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK05 : stm32wbxx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK06 : stm32wbxx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK07 : stm32wbxx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_NOMASK : stm32wbxx_ll_i2c.h
  • LL_I2C_ReadReg : stm32wbxx_ll_i2c.h
  • LL_I2C_ReceiveData8() : stm32wbxx_ll_i2c.h
  • LL_I2C_REQUEST_READ : stm32wbxx_ll_i2c.h
  • LL_I2C_REQUEST_WRITE : stm32wbxx_ll_i2c.h
  • LL_I2C_SetDigitalFilter() : stm32wbxx_ll_i2c.h
  • LL_I2C_SetMasterAddressingMode() : stm32wbxx_ll_i2c.h
  • LL_I2C_SetMode() : stm32wbxx_ll_i2c.h
  • LL_I2C_SetOwnAddress1() : stm32wbxx_ll_i2c.h
  • LL_I2C_SetOwnAddress2() : stm32wbxx_ll_i2c.h
  • LL_I2C_SetSlaveAddr() : stm32wbxx_ll_i2c.h
  • LL_I2C_SetSMBusTimeoutA() : stm32wbxx_ll_i2c.h
  • LL_I2C_SetSMBusTimeoutAMode() : stm32wbxx_ll_i2c.h
  • LL_I2C_SetSMBusTimeoutB() : stm32wbxx_ll_i2c.h
  • LL_I2C_SetTiming() : stm32wbxx_ll_i2c.h
  • LL_I2C_SetTransferRequest() : stm32wbxx_ll_i2c.h
  • LL_I2C_SetTransferSize() : stm32wbxx_ll_i2c.h
  • LL_I2C_SMBUS_ALL_TIMEOUT : stm32wbxx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTA : stm32wbxx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW : stm32wbxx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH : stm32wbxx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTB : stm32wbxx_ll_i2c.h
  • LL_I2C_StructInit() : stm32wbxx_ll_i2c.c
  • LL_I2C_TransmitData8() : stm32wbxx_ll_i2c.h
  • LL_I2C_WriteReg : stm32wbxx_ll_i2c.h
  • LL_Init1msTick() : stm32wbxx_ll_utils.c
  • LL_InitTick() : stm32wbxx_ll_utils.h
  • LL_IPCC_C1TOC2SR_CH1F : stm32wbxx_ll_ipcc.h
  • LL_IPCC_C1TOC2SR_CH2F : stm32wbxx_ll_ipcc.h
  • LL_IPCC_C1TOC2SR_CH3F : stm32wbxx_ll_ipcc.h
  • LL_IPCC_C1TOC2SR_CH4F : stm32wbxx_ll_ipcc.h
  • LL_IPCC_C1TOC2SR_CH5F : stm32wbxx_ll_ipcc.h
  • LL_IPCC_C1TOC2SR_CH6F : stm32wbxx_ll_ipcc.h
  • LL_IPCC_C2TOC1SR_CH1F : stm32wbxx_ll_ipcc.h
  • LL_IPCC_C2TOC1SR_CH2F : stm32wbxx_ll_ipcc.h
  • LL_IPCC_C2TOC1SR_CH3F : stm32wbxx_ll_ipcc.h
  • LL_IPCC_C2TOC1SR_CH4F : stm32wbxx_ll_ipcc.h
  • LL_IPCC_C2TOC1SR_CH5F : stm32wbxx_ll_ipcc.h
  • LL_IPCC_C2TOC1SR_CH6F : stm32wbxx_ll_ipcc.h
  • LL_IPCC_CHANNEL_1 : stm32wbxx_ll_ipcc.h
  • LL_IPCC_CHANNEL_2 : stm32wbxx_ll_ipcc.h
  • LL_IPCC_CHANNEL_3 : stm32wbxx_ll_ipcc.h
  • LL_IPCC_CHANNEL_4 : stm32wbxx_ll_ipcc.h
  • LL_IPCC_CHANNEL_5 : stm32wbxx_ll_ipcc.h
  • LL_IPCC_CHANNEL_6 : stm32wbxx_ll_ipcc.h
  • LL_IPCC_ReadReg : stm32wbxx_ll_ipcc.h
  • LL_IPCC_WriteReg : stm32wbxx_ll_ipcc.h
  • LL_IWDG_DisableWriteAccess() : stm32wbxx_ll_iwdg.h
  • LL_IWDG_Enable() : stm32wbxx_ll_iwdg.h
  • LL_IWDG_EnableWriteAccess() : stm32wbxx_ll_iwdg.h
  • LL_IWDG_GetPrescaler() : stm32wbxx_ll_iwdg.h
  • LL_IWDG_GetReloadCounter() : stm32wbxx_ll_iwdg.h
  • LL_IWDG_GetWindow() : stm32wbxx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_PVU() : stm32wbxx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_RVU() : stm32wbxx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_WVU() : stm32wbxx_ll_iwdg.h
  • LL_IWDG_IsReady() : stm32wbxx_ll_iwdg.h
  • LL_IWDG_KEY_ENABLE : stm32wbxx_ll_iwdg.h
  • LL_IWDG_KEY_RELOAD : stm32wbxx_ll_iwdg.h
  • LL_IWDG_KEY_WR_ACCESS_DISABLE : stm32wbxx_ll_iwdg.h
  • LL_IWDG_KEY_WR_ACCESS_ENABLE : stm32wbxx_ll_iwdg.h
  • LL_IWDG_PRESCALER_128 : stm32wbxx_ll_iwdg.h
  • LL_IWDG_PRESCALER_16 : stm32wbxx_ll_iwdg.h
  • LL_IWDG_PRESCALER_256 : stm32wbxx_ll_iwdg.h
  • LL_IWDG_PRESCALER_32 : stm32wbxx_ll_iwdg.h
  • LL_IWDG_PRESCALER_4 : stm32wbxx_ll_iwdg.h
  • LL_IWDG_PRESCALER_64 : stm32wbxx_ll_iwdg.h
  • LL_IWDG_PRESCALER_8 : stm32wbxx_ll_iwdg.h
  • LL_IWDG_ReadReg : stm32wbxx_ll_iwdg.h
  • LL_IWDG_ReloadCounter() : stm32wbxx_ll_iwdg.h
  • LL_IWDG_SetPrescaler() : stm32wbxx_ll_iwdg.h
  • LL_IWDG_SetReloadCounter() : stm32wbxx_ll_iwdg.h
  • LL_IWDG_SetWindow() : stm32wbxx_ll_iwdg.h
  • LL_IWDG_SR_PVU : stm32wbxx_ll_iwdg.h
  • LL_IWDG_SR_RVU : stm32wbxx_ll_iwdg.h
  • LL_IWDG_SR_WVU : stm32wbxx_ll_iwdg.h
  • LL_IWDG_WriteReg : stm32wbxx_ll_iwdg.h
  • LL_LPM_DisableEventOnPend() : stm32wbxx_ll_cortex.h
  • LL_LPM_DisableSleepOnExit() : stm32wbxx_ll_cortex.h
  • LL_LPM_EnableDeepSleep() : stm32wbxx_ll_cortex.h
  • LL_LPM_EnableEventOnPend() : stm32wbxx_ll_cortex.h
  • LL_LPM_EnableSleep() : stm32wbxx_ll_cortex.h
  • LL_LPM_EnableSleepOnExit() : stm32wbxx_ll_cortex.h
  • LL_LPTIM_ClearFLAG_ARRM() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ClearFlag_ARROK() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ClearFLAG_CMPM() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ClearFlag_CMPOK() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ClearFlag_DOWN() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ClearFlag_EXTTRIG() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ClearFlag_UP() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_CLK_FILTER_2 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_CLK_FILTER_4 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_CLK_FILTER_8 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_CLK_FILTER_NONE : stm32wbxx_ll_lptim.h
  • LL_LPTIM_CLK_POLARITY_FALLING : stm32wbxx_ll_lptim.h
  • LL_LPTIM_CLK_POLARITY_RISING : stm32wbxx_ll_lptim.h
  • LL_LPTIM_CLK_POLARITY_RISING_FALLING : stm32wbxx_ll_lptim.h
  • LL_LPTIM_CLK_SOURCE_EXTERNAL : stm32wbxx_ll_lptim.h
  • LL_LPTIM_CLK_SOURCE_INTERNAL : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ConfigClock() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ConfigOutput() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ConfigTrigger() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_COUNTER_MODE_EXTERNAL : stm32wbxx_ll_lptim.h
  • LL_LPTIM_COUNTER_MODE_INTERNAL : stm32wbxx_ll_lptim.h
  • LL_LPTIM_DeInit() : stm32wbxx_ll_lptim.c
  • LL_LPTIM_Disable() : stm32wbxx_ll_lptim.c , stm32wbxx_ll_lptim.h
  • LL_LPTIM_DisableEncoderMode() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_DisableIT_ARRM() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_DisableIT_ARROK() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_DisableIT_CMPM() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_DisableIT_CMPOK() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_DisableIT_DOWN() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_DisableIT_EXTTRIG() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_DisableIT_UP() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_DisableResetAfterRead() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_DisableTimeout() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_Enable() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_EnableEncoderMode() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_EnableIT_ARRM() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_EnableIT_ARROK() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_EnableIT_CMPM() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_EnableIT_CMPOK() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_EnableIT_DOWN() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_EnableIT_EXTTRIG() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_EnableIT_UP() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_EnableResetAfterRead() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_EnableTimeout() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ENCODER_MODE_FALLING : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ENCODER_MODE_RISING : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ENCODER_MODE_RISING_FALLING : stm32wbxx_ll_lptim.h
  • LL_LPTIM_GetAutoReload() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_GetClockFilter() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_GetClockPolarity() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_GetClockSource() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_GetCompare() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_GetCounter() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_GetCounterMode() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_GetEncoderMode() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_GetPolarity() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_GetPrescaler() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_GetTriggerFilter() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_GetTriggerPolarity() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_GetTriggerSource() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_GetUpdateMode() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_GetWaveform() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IER_ARRMIE : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IER_ARROKIE : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IER_CMPMIE : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IER_CMPOKIE : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IER_DOWNIE : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IER_EXTTRIGIE : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IER_UPIE : stm32wbxx_ll_lptim.h
  • LL_LPTIM_Init() : stm32wbxx_ll_lptim.c
  • LL_LPTIM_INPUT1_SRC_COMP1 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_INPUT1_SRC_COMP1_COMP2 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_INPUT1_SRC_COMP2 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_INPUT1_SRC_GPIO : stm32wbxx_ll_lptim.h
  • LL_LPTIM_INPUT2_SRC_COMP2 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_INPUT2_SRC_GPIO : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_ARRM() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_ARROK() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_CMPM() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_CMPOK() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_DOWN() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_EXTTRIG() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_UP() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IsEnabled() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IsEnabledEncoderMode() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_ARRM() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_ARROK() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_CMPM() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_CMPOK() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_DOWN() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_EXTTRIG() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_UP() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IsEnabledResetAfterRead() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IsEnabledTimeout() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ISR_ARRM : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ISR_ARROK : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ISR_CMPM : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ISR_CMPOK : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ISR_DOWN : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ISR_EXTTRIG : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ISR_UP : stm32wbxx_ll_lptim.h
  • LL_LPTIM_OPERATING_MODE_CONTINUOUS : stm32wbxx_ll_lptim.h
  • LL_LPTIM_OPERATING_MODE_ONESHOT : stm32wbxx_ll_lptim.h
  • LL_LPTIM_OUTPUT_POLARITY_INVERSE : stm32wbxx_ll_lptim.h
  • LL_LPTIM_OUTPUT_POLARITY_REGULAR : stm32wbxx_ll_lptim.h
  • LL_LPTIM_OUTPUT_WAVEFORM_PWM : stm32wbxx_ll_lptim.h
  • LL_LPTIM_OUTPUT_WAVEFORM_SETONCE : stm32wbxx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV1 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV128 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV16 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV2 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV32 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV4 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV64 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV8 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ReadReg : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ResetCounter() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_SetAutoReload() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_SetClockSource() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_SetCompare() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_SetCounterMode() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_SetEncoderMode() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_SetInput1Src() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_SetInput2Src() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_SetPolarity() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_SetPrescaler() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_SetUpdateMode() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_SetWaveform() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_StartCounter() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_StructInit() : stm32wbxx_ll_lptim.c
  • LL_LPTIM_TRIG_FILTER_2 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_TRIG_FILTER_4 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_TRIG_FILTER_8 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_TRIG_FILTER_NONE : stm32wbxx_ll_lptim.h
  • LL_LPTIM_TRIG_POLARITY_FALLING : stm32wbxx_ll_lptim.h
  • LL_LPTIM_TRIG_POLARITY_RISING : stm32wbxx_ll_lptim.h
  • LL_LPTIM_TRIG_POLARITY_RISING_FALLING : stm32wbxx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_COMP1 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_COMP2 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_GPIO : stm32wbxx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCALARMA : stm32wbxx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCALARMB : stm32wbxx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP1 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP2 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP3 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_TrigSw() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_UPDATE_MODE_ENDOFPERIOD : stm32wbxx_ll_lptim.h
  • LL_LPTIM_UPDATE_MODE_IMMEDIATE : stm32wbxx_ll_lptim.h
  • LL_LPTIM_WriteReg : stm32wbxx_ll_lptim.h
  • LL_LPUART_ADDRESS_DETECT_4B : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ADDRESS_DETECT_7B : stm32wbxx_ll_lpuart.h
  • LL_LPUART_BINARY_LOGIC_NEGATIVE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_BINARY_LOGIC_POSITIVE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_BITORDER_LSBFIRST : stm32wbxx_ll_lpuart.h
  • LL_LPUART_BITORDER_MSBFIRST : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ClearFlag_CM() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ClearFlag_FE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ClearFlag_IDLE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ClearFlag_nCTS() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ClearFlag_NE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ClearFlag_ORE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ClearFlag_PE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ClearFlag_TC() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ClearFlag_TXFE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ClearFlag_WKUP() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ConfigCharacter() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ConfigFIFOsThreshold() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ConfigNodeAddress() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_CR1_CMIE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_CR1_IDLEIE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_CR1_PEIE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_CR1_RXFFIE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_CR1_RXNEIE_RXFNEIE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_CR1_TCIE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_CR1_TXEIE_TXFNFIE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_CR1_TXFEIE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_CR3_CTSIE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_CR3_EIE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_CR3_RXFTIE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_CR3_TXFTIE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_CR3_WUFIE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DATAWIDTH_7B : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DATAWIDTH_8B : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DATAWIDTH_9B : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DE_POLARITY_HIGH : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DE_POLARITY_LOW : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DeInit() : stm32wbxx_ll_lpuart.c
  • LL_LPUART_DIRECTION_NONE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DIRECTION_RX : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DIRECTION_TX : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DIRECTION_TX_RX : stm32wbxx_ll_lpuart.h
  • LL_LPUART_Disable() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableCTSHWFlowCtrl() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableDEMode() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableDirectionRx() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableDirectionTx() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableDMADeactOnRxErr() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableDMAReq_RX() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableDMAReq_TX() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableFIFO() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableHalfDuplex() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableInStopMode() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableIT_CM() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableIT_CTS() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableIT_ERROR() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableIT_IDLE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableIT_PE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableIT_RXFF() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableIT_RXFT() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableIT_RXNE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableIT_RXNE_RXFNE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableIT_TC() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableIT_TXE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableIT_TXE_TXFNF() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableIT_TXFE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableIT_TXFT() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableIT_WKUP() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableMuteMode() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableOverrunDetect() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableRTSHWFlowCtrl() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DMA_GetRegAddr() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DMA_REG_DATA_RECEIVE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DMA_REG_DATA_TRANSMIT : stm32wbxx_ll_lpuart.h
  • LL_LPUART_Enable() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableCTSHWFlowCtrl() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableDEMode() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableDirectionRx() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableDirectionTx() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableDMADeactOnRxErr() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableDMAReq_RX() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableDMAReq_TX() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableFIFO() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableHalfDuplex() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableInStopMode() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableIT_CM() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableIT_CTS() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableIT_ERROR() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableIT_IDLE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableIT_PE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableIT_RXFF() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableIT_RXFT() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableIT_RXNE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableIT_RXNE_RXFNE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableIT_TC() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableIT_TXE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableIT_TXE_TXFNF() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableIT_TXFE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableIT_TXFT() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableIT_WKUP() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableMuteMode() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableOverrunDetect() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableRTSHWFlowCtrl() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_1_2 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_1_4 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_1_8 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_3_4 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_7_8 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_8_8 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetBaudRate() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetBinaryDataLogic() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetDataWidth() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetDEAssertionTime() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetDEDeassertionTime() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetDESignalPolarity() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetHWFlowCtrl() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetNodeAddress() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetNodeAddressLen() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetParity() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetPrescaler() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetRXFIFOThreshold() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetRXPinLevel() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetStopBitsLength() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetTransferBitOrder() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetTransferDirection() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetTXFIFOThreshold() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetTXPinLevel() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetTXRXSwap() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetWakeUpMethod() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetWKUPType() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_CTS : stm32wbxx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_NONE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_RTS : stm32wbxx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_RTS_CTS : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ICR_CMCF : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ICR_CTSCF : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ICR_FECF : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ICR_IDLECF : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ICR_NCF : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ICR_ORECF : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ICR_PECF : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ICR_TCCF : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ICR_TXFECF : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ICR_WUCF : stm32wbxx_ll_lpuart.h
  • LL_LPUART_Init() : stm32wbxx_ll_lpuart.c
  • LL_LPUART_IsActiveFlag_BUSY() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_CM() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_CTS() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_FE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_IDLE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_nCTS() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_NE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_ORE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_PE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_REACK() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RWU() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RXFF() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RXFT() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RXNE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RXNE_RXFNE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_SBK() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TC() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TEACK() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TXE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TXE_TXFNF() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TXFE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TXFT() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_WKUP() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabled() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledDEMode() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledDMADeactOnRxErr() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledDMAReq_RX() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledDMAReq_TX() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledFIFO() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledHalfDuplex() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledInStopMode() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_CM() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_CTS() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_ERROR() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_IDLE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_PE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_RXFF() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_RXFT() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_RXNE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_RXNE_RXFNE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TC() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TXE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TXE_TXFNF() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TXFE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TXFT() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_WKUP() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledMuteMode() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledOverrunDetect() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_BUSY : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_CMF : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_CTS : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_CTSIF : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_FE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_IDLE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_NE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_ORE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_PE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_REACK : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_RWU : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_RXFF : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_RXFT : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_RXNE_RXFNE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_SBKF : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_TC : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_TEACK : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_TXE_TXFNF : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_TXFE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_TXFT : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_WUF : stm32wbxx_ll_lpuart.h
  • LL_LPUART_PARITY_EVEN : stm32wbxx_ll_lpuart.h
  • LL_LPUART_PARITY_NONE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_PARITY_ODD : stm32wbxx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV1 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV10 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV12 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV128 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV16 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV2 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV256 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV32 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV4 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV6 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV64 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV8 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ReadReg : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ReceiveData8() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ReceiveData9() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_RequestBreakSending() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_RequestEnterMuteMode() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_RequestRxDataFlush() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_RXPIN_LEVEL_INVERTED : stm32wbxx_ll_lpuart.h
  • LL_LPUART_RXPIN_LEVEL_STANDARD : stm32wbxx_ll_lpuart.h
  • LL_LPUART_SetBaudRate() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_SetBinaryDataLogic() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_SetDataWidth() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_SetDEAssertionTime() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_SetDEDeassertionTime() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_SetDESignalPolarity() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_SetHWFlowCtrl() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_SetParity() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_SetPrescaler() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_SetRXFIFOThreshold() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_SetRXPinLevel() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_SetStopBitsLength() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_SetTransferBitOrder() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_SetTransferDirection() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_SetTXFIFOThreshold() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_SetTXPinLevel() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_SetTXRXSwap() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_SetWakeUpMethod() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_SetWKUPType() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_STOPBITS_1 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_STOPBITS_2 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_StructInit() : stm32wbxx_ll_lpuart.c
  • LL_LPUART_TransmitData8() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_TransmitData9() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_TXPIN_LEVEL_INVERTED : stm32wbxx_ll_lpuart.h
  • LL_LPUART_TXPIN_LEVEL_STANDARD : stm32wbxx_ll_lpuart.h
  • LL_LPUART_TXRX_STANDARD : stm32wbxx_ll_lpuart.h
  • LL_LPUART_TXRX_SWAPPED : stm32wbxx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ADDRESSMARK : stm32wbxx_ll_lpuart.h
  • LL_LPUART_WAKEUP_IDLELINE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ON_ADDRESS : stm32wbxx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ON_RXNE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ON_STARTBIT : stm32wbxx_ll_lpuart.h
  • LL_LPUART_WriteReg : stm32wbxx_ll_lpuart.h
  • LL_MAX_DELAY : stm32wbxx_ll_utils.h
  • LL_mDelay() : stm32wbxx_ll_utils.c
  • LL_MPU_ACCESS_BUFFERABLE : stm32wbxx_ll_cortex.h
  • LL_MPU_ACCESS_CACHEABLE : stm32wbxx_ll_cortex.h
  • LL_MPU_ACCESS_NOT_BUFFERABLE : stm32wbxx_ll_cortex.h
  • LL_MPU_ACCESS_NOT_CACHEABLE : stm32wbxx_ll_cortex.h
  • LL_MPU_ACCESS_NOT_SHAREABLE : stm32wbxx_ll_cortex.h
  • LL_MPU_ACCESS_SHAREABLE : stm32wbxx_ll_cortex.h
  • LL_MPU_ConfigRegion() : stm32wbxx_ll_cortex.h
  • LL_MPU_CTRL_HARDFAULT_NMI : stm32wbxx_ll_cortex.h
  • LL_MPU_CTRL_HFNMI_PRIVDEF : stm32wbxx_ll_cortex.h
  • LL_MPU_CTRL_HFNMI_PRIVDEF_NONE : stm32wbxx_ll_cortex.h
  • LL_MPU_CTRL_PRIVILEGED_DEFAULT : stm32wbxx_ll_cortex.h
  • LL_MPU_Disable() : stm32wbxx_ll_cortex.h
  • LL_MPU_DisableRegion() : stm32wbxx_ll_cortex.h
  • LL_MPU_Enable() : stm32wbxx_ll_cortex.h
  • LL_MPU_EnableRegion() : stm32wbxx_ll_cortex.h
  • LL_MPU_INSTRUCTION_ACCESS_DISABLE : stm32wbxx_ll_cortex.h
  • LL_MPU_INSTRUCTION_ACCESS_ENABLE : stm32wbxx_ll_cortex.h
  • LL_MPU_IsEnabled() : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_FULL_ACCESS : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_NO_ACCESS : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_NUMBER0 : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_NUMBER1 : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_NUMBER2 : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_NUMBER3 : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_NUMBER4 : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_NUMBER5 : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_NUMBER6 : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_NUMBER7 : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RO : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RO_URO : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RW : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RW_URO : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_128B : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_128KB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_128MB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_16KB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_16MB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_1GB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_1KB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_1MB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_256B : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_256KB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_256MB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_2GB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_2KB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_2MB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_32B : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_32KB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_32MB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_4GB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_4KB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_4MB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_512B : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_512KB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_512MB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_64B : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_64KB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_64MB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_8KB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_8MB : stm32wbxx_ll_cortex.h
  • LL_MPU_TEX_LEVEL0 : stm32wbxx_ll_cortex.h
  • LL_MPU_TEX_LEVEL1 : stm32wbxx_ll_cortex.h
  • LL_MPU_TEX_LEVEL2 : stm32wbxx_ll_cortex.h
  • LL_MPU_TEX_LEVEL4 : stm32wbxx_ll_cortex.h
  • LL_PKA_ClearFlag_ADDERR() : stm32wbxx_ll_pka.h
  • LL_PKA_ClearFlag_PROCEND() : stm32wbxx_ll_pka.h
  • LL_PKA_ClearFlag_RAMERR() : stm32wbxx_ll_pka.h
  • LL_PKA_CLRFR_ADDRERRFC : stm32wbxx_ll_pka.h
  • LL_PKA_CLRFR_PROCENDFC : stm32wbxx_ll_pka.h
  • LL_PKA_CLRFR_RAMERRFC : stm32wbxx_ll_pka.h
  • LL_PKA_Config() : stm32wbxx_ll_pka.h
  • LL_PKA_CR_ADDRERRIE : stm32wbxx_ll_pka.h
  • LL_PKA_CR_PROCENDIE : stm32wbxx_ll_pka.h
  • LL_PKA_CR_RAMERRIE : stm32wbxx_ll_pka.h
  • LL_PKA_DeInit() : stm32wbxx_ll_pka.c
  • LL_PKA_Disable() : stm32wbxx_ll_pka.h
  • LL_PKA_DisableIT_ADDERR() : stm32wbxx_ll_pka.h
  • LL_PKA_DisableIT_PROCEND() : stm32wbxx_ll_pka.h
  • LL_PKA_DisableIT_RAMERR() : stm32wbxx_ll_pka.h
  • LL_PKA_Enable() : stm32wbxx_ll_pka.h
  • LL_PKA_EnableIT_ADDRERR() : stm32wbxx_ll_pka.h
  • LL_PKA_EnableIT_PROCEND() : stm32wbxx_ll_pka.h
  • LL_PKA_EnableIT_RAMERR() : stm32wbxx_ll_pka.h
  • LL_PKA_GetMode() : stm32wbxx_ll_pka.h
  • LL_PKA_Init() : stm32wbxx_ll_pka.c
  • LL_PKA_IsActiveFlag_ADDRERR() : stm32wbxx_ll_pka.h
  • LL_PKA_IsActiveFlag_BUSY() : stm32wbxx_ll_pka.h
  • LL_PKA_IsActiveFlag_PROCEND() : stm32wbxx_ll_pka.h
  • LL_PKA_IsActiveFlag_RAMERR() : stm32wbxx_ll_pka.h
  • LL_PKA_IsEnabled() : stm32wbxx_ll_pka.h
  • LL_PKA_IsEnabledIT_ADDRERR() : stm32wbxx_ll_pka.h
  • LL_PKA_IsEnabledIT_PROCEND() : stm32wbxx_ll_pka.h
  • LL_PKA_IsEnabledIT_RAMERR() : stm32wbxx_ll_pka.h
  • LL_PKA_MODE_ARITHMETIC_ADD : stm32wbxx_ll_pka.h
  • LL_PKA_MODE_ARITHMETIC_MUL : stm32wbxx_ll_pka.h
  • LL_PKA_MODE_ARITHMETIC_SUB : stm32wbxx_ll_pka.h
  • LL_PKA_MODE_COMPARISON : stm32wbxx_ll_pka.h
  • LL_PKA_MODE_ECC_KP_PRIMITIVE : stm32wbxx_ll_pka.h
  • LL_PKA_MODE_ECDSA_SIGNATURE : stm32wbxx_ll_pka.h
  • LL_PKA_MODE_ECDSA_VERIFICATION : stm32wbxx_ll_pka.h
  • LL_PKA_MODE_MODULAR_ADD : stm32wbxx_ll_pka.h
  • LL_PKA_MODE_MODULAR_EXP : stm32wbxx_ll_pka.h
  • LL_PKA_MODE_MODULAR_INV : stm32wbxx_ll_pka.h
  • LL_PKA_MODE_MODULAR_REDUC : stm32wbxx_ll_pka.h
  • LL_PKA_MODE_MODULAR_SUB : stm32wbxx_ll_pka.h
  • LL_PKA_MODE_MONTGOMERY_MUL : stm32wbxx_ll_pka.h
  • LL_PKA_MODE_MONTGOMERY_PARAM : stm32wbxx_ll_pka.h
  • LL_PKA_MODE_MONTGOMERY_PARAM_ECC : stm32wbxx_ll_pka.h
  • LL_PKA_MODE_MONTGOMERY_PARAM_MOD_EXP : stm32wbxx_ll_pka.h
  • LL_PKA_MODE_POINT_CHECK : stm32wbxx_ll_pka.h
  • LL_PKA_MODE_RSA_CRT_EXP : stm32wbxx_ll_pka.h
  • LL_PKA_ReadReg : stm32wbxx_ll_pka.h
  • LL_PKA_SetMode() : stm32wbxx_ll_pka.h
  • LL_PKA_SR_ADDRERRF : stm32wbxx_ll_pka.h
  • LL_PKA_SR_BUSY : stm32wbxx_ll_pka.h
  • LL_PKA_SR_PROCENDF : stm32wbxx_ll_pka.h
  • LL_PKA_SR_RAMERRF : stm32wbxx_ll_pka.h
  • LL_PKA_Start() : stm32wbxx_ll_pka.h
  • LL_PKA_StructInit() : stm32wbxx_ll_pka.c
  • LL_PKA_WriteReg : stm32wbxx_ll_pka.h
  • LL_PLL_ConfigSystemClock_HSE() : stm32wbxx_ll_utils.c
  • LL_PLL_ConfigSystemClock_HSI() : stm32wbxx_ll_utils.c
  • LL_PLL_ConfigSystemClock_MSI() : stm32wbxx_ll_utils.c
  • LL_PWR_BATT_CHARG_RESISTOR_5K : stm32wbxx_ll_pwr.h
  • LL_PWR_BATT_CHARGRESISTOR_1_5K : stm32wbxx_ll_pwr.h
  • LL_PWR_BOR_SMPS_FORCE_BYPASS : stm32wbxx_ll_pwr.h
  • LL_PWR_BOR_SYSTEM_RESET : stm32wbxx_ll_pwr.h
  • LL_PWR_ClearFlag_802A() : stm32wbxx_ll_pwr.h
  • LL_PWR_ClearFlag_802WU() : stm32wbxx_ll_pwr.h
  • LL_PWR_ClearFlag_BLEA() : stm32wbxx_ll_pwr.h
  • LL_PWR_ClearFlag_BLEWU() : stm32wbxx_ll_pwr.h
  • LL_PWR_ClearFlag_BORH() : stm32wbxx_ll_pwr.h
  • LL_PWR_ClearFlag_C1STOP_C1STB() : stm32wbxx_ll_pwr.h
  • LL_PWR_ClearFlag_C2H() : stm32wbxx_ll_pwr.h
  • LL_PWR_ClearFlag_C2STOP_C2STB() : stm32wbxx_ll_pwr.h
  • LL_PWR_ClearFlag_CRP() : stm32wbxx_ll_pwr.h
  • LL_PWR_ClearFlag_CRPE() : stm32wbxx_ll_pwr.h
  • LL_PWR_ClearFlag_SMPSFB() : stm32wbxx_ll_pwr.h
  • LL_PWR_ClearFlag_WU() : stm32wbxx_ll_pwr.h
  • LL_PWR_ClearFlag_WU1() : stm32wbxx_ll_pwr.h
  • LL_PWR_ClearFlag_WU2() : stm32wbxx_ll_pwr.h
  • LL_PWR_ClearFlag_WU3() : stm32wbxx_ll_pwr.h
  • LL_PWR_ClearFlag_WU4() : stm32wbxx_ll_pwr.h
  • LL_PWR_ClearFlag_WU5() : stm32wbxx_ll_pwr.h
  • LL_PWR_DeInit() : stm32wbxx_ll_pwr.c
  • LL_PWR_DisableBatteryCharging() : stm32wbxx_ll_pwr.h
  • LL_PWR_DisableBkUpAccess() : stm32wbxx_ll_pwr.h
  • LL_PWR_DisableBootC2() : stm32wbxx_ll_pwr.h
  • LL_PWR_DisableGPIOPullDown() : stm32wbxx_ll_pwr.h
  • LL_PWR_DisableGPIOPullUp() : stm32wbxx_ll_pwr.h
  • LL_PWR_DisableInternWU() : stm32wbxx_ll_pwr.h
  • LL_PWR_DisableIT_802A() : stm32wbxx_ll_pwr.h
  • LL_PWR_DisableIT_BLEA() : stm32wbxx_ll_pwr.h
  • LL_PWR_DisableIT_BORH_SMPSFB() : stm32wbxx_ll_pwr.h
  • LL_PWR_DisableIT_CRPE() : stm32wbxx_ll_pwr.h
  • LL_PWR_DisableIT_HoldCPU2() : stm32wbxx_ll_pwr.h
  • LL_PWR_DisablePUPDCfg() : stm32wbxx_ll_pwr.h
  • LL_PWR_DisablePVD() : stm32wbxx_ll_pwr.h
  • LL_PWR_DisablePVM() : stm32wbxx_ll_pwr.h
  • LL_PWR_DisableSRAM2Retention() : stm32wbxx_ll_pwr.h
  • LL_PWR_DisableVddUSB() : stm32wbxx_ll_pwr.h
  • LL_PWR_DisableWakeUpPin() : stm32wbxx_ll_pwr.h
  • LL_PWR_EnableBatteryCharging() : stm32wbxx_ll_pwr.h
  • LL_PWR_EnableBkUpAccess() : stm32wbxx_ll_pwr.h
  • LL_PWR_EnableBootC2() : stm32wbxx_ll_pwr.h
  • LL_PWR_EnableGPIOPullDown() : stm32wbxx_ll_pwr.h
  • LL_PWR_EnableGPIOPullUp() : stm32wbxx_ll_pwr.h
  • LL_PWR_EnableInternWU() : stm32wbxx_ll_pwr.h
  • LL_PWR_EnableIT_802A() : stm32wbxx_ll_pwr.h
  • LL_PWR_EnableIT_BLEA() : stm32wbxx_ll_pwr.h
  • LL_PWR_EnableIT_BORH_SMPSFB() : stm32wbxx_ll_pwr.h
  • LL_PWR_EnableIT_CRPE() : stm32wbxx_ll_pwr.h
  • LL_PWR_EnableIT_HoldCPU2() : stm32wbxx_ll_pwr.h
  • LL_PWR_EnablePUPDCfg() : stm32wbxx_ll_pwr.h
  • LL_PWR_EnablePVD() : stm32wbxx_ll_pwr.h
  • LL_PWR_EnablePVM() : stm32wbxx_ll_pwr.h
  • LL_PWR_EnableSRAM2Retention() : stm32wbxx_ll_pwr.h
  • LL_PWR_EnableVddUSB() : stm32wbxx_ll_pwr.h
  • LL_PWR_EnableWakeUpPin() : stm32wbxx_ll_pwr.h
  • LL_PWR_EnterLowPowerRunMode() : stm32wbxx_ll_pwr.h
  • LL_PWR_ExitLowPowerRunMode() : stm32wbxx_ll_pwr.h
  • LL_PWR_EXTSCR_C1CSSF : stm32wbxx_ll_pwr.h
  • LL_PWR_EXTSCR_C1DS : stm32wbxx_ll_pwr.h
  • LL_PWR_EXTSCR_C1SBF : stm32wbxx_ll_pwr.h
  • LL_PWR_EXTSCR_C1STOPF : stm32wbxx_ll_pwr.h
  • LL_PWR_EXTSCR_C2CSSF : stm32wbxx_ll_pwr.h
  • LL_PWR_EXTSCR_C2DS : stm32wbxx_ll_pwr.h
  • LL_PWR_EXTSCR_C2SBF : stm32wbxx_ll_pwr.h
  • LL_PWR_EXTSCR_C2STOPF : stm32wbxx_ll_pwr.h
  • LL_PWR_EXTSCR_CCRPF : stm32wbxx_ll_pwr.h
  • LL_PWR_FLAG_802A : stm32wbxx_ll_pwr.h
  • LL_PWR_FLAG_802WU : stm32wbxx_ll_pwr.h
  • LL_PWR_FLAG_BLEA : stm32wbxx_ll_pwr.h
  • LL_PWR_FLAG_BLEWU : stm32wbxx_ll_pwr.h
  • LL_PWR_FLAG_BORH : stm32wbxx_ll_pwr.h
  • LL_PWR_FLAG_CRP : stm32wbxx_ll_pwr.h
  • LL_PWR_FLAG_CRPE : stm32wbxx_ll_pwr.h
  • LL_PWR_FLAG_SMPS : stm32wbxx_ll_pwr.h
  • LL_PWR_FLAG_SMPSB : stm32wbxx_ll_pwr.h
  • LL_PWR_FLAG_SMPSFB : stm32wbxx_ll_pwr.h
  • LL_PWR_FLASH_LPRUN_MODE_IDLE : stm32wbxx_ll_pwr.h
  • LL_PWR_FLASH_LPRUN_MODE_POWER_DOWN : stm32wbxx_ll_pwr.h
  • LL_PWR_FLASH_SLEEP_MODE_IDLE : stm32wbxx_ll_pwr.h
  • LL_PWR_FLASH_SLEEP_MODE_POWER_DOWN : stm32wbxx_ll_pwr.h
  • LL_PWR_GetBattChargResistor() : stm32wbxx_ll_pwr.h
  • LL_PWR_GetBORConfig() : stm32wbxx_ll_pwr.h
  • LL_PWR_GetFlashPowerModeLPRun() : stm32wbxx_ll_pwr.h
  • LL_PWR_GetFlashPowerModeSleep() : stm32wbxx_ll_pwr.h
  • LL_PWR_GetPowerMode() : stm32wbxx_ll_pwr.h
  • LL_PWR_GetPVDLevel() : stm32wbxx_ll_pwr.h
  • LL_PWR_GetRegulVoltageScaling() : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_A : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_B : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_BIT_0 : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_BIT_1 : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_BIT_10 : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_BIT_11 : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_BIT_12 : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_BIT_13 : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_BIT_14 : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_BIT_15 : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_BIT_2 : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_BIT_3 : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_BIT_4 : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_BIT_5 : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_BIT_6 : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_BIT_7 : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_BIT_8 : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_BIT_9 : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_C : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_D : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_E : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_H : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_802A() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_802WU() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_BLEA() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_BLEWU() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_BORH() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_C1DS() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_C1SB() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_C1STOP() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_C2DS() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_C2H() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_C2SB() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_C2STOP() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_CRP() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_CRPE() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_InternWU() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_PVDO() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_PVMO1() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_PVMO3() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_REGLPF() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_REGLPS() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_SMPSFB() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_VOS() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU1() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU2() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU3() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU4() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU5() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsEnabledBatteryCharging() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsEnabledBkUpAccess() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsEnabledBootC2() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsEnabledGPIOPullDown() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsEnabledGPIOPullUp() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsEnabledInternWU() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsEnabledIT_802A() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsEnabledIT_BLEA() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsEnabledIT_BORH_SMPSFB() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsEnabledIT_CRPE() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsEnabledIT_HoldCPU2() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsEnabledLowPowerRunMode() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsEnabledPUPDCfg() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsEnabledPVD() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsEnabledPVM() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsEnabledSRAM2Retention() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsEnabledVddUSB() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsEnabledWakeUpPin() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsWakeUpPinPolarityLow() : stm32wbxx_ll_pwr.h
  • LL_PWR_MODE_SHUTDOWN : stm32wbxx_ll_pwr.h
  • LL_PWR_MODE_STANDBY : stm32wbxx_ll_pwr.h
  • LL_PWR_MODE_STOP0 : stm32wbxx_ll_pwr.h
  • LL_PWR_MODE_STOP1 : stm32wbxx_ll_pwr.h
  • LL_PWR_MODE_STOP2 : stm32wbxx_ll_pwr.h
  • LL_PWR_PVDLEVEL_0 : stm32wbxx_ll_pwr.h
  • LL_PWR_PVDLEVEL_1 : stm32wbxx_ll_pwr.h
  • LL_PWR_PVDLEVEL_2 : stm32wbxx_ll_pwr.h
  • LL_PWR_PVDLEVEL_3 : stm32wbxx_ll_pwr.h
  • LL_PWR_PVDLEVEL_4 : stm32wbxx_ll_pwr.h
  • LL_PWR_PVDLEVEL_5 : stm32wbxx_ll_pwr.h
  • LL_PWR_PVDLEVEL_6 : stm32wbxx_ll_pwr.h
  • LL_PWR_PVDLEVEL_7 : stm32wbxx_ll_pwr.h
  • LL_PWR_PVM_VDDA_1_62V : stm32wbxx_ll_pwr.h
  • LL_PWR_PVM_VDDUSB_1_2V : stm32wbxx_ll_pwr.h
  • LL_PWR_ReadReg : stm32wbxx_ll_pwr.h
  • LL_PWR_REGU_VOLTAGE_SCALE1 : stm32wbxx_ll_pwr.h
  • LL_PWR_REGU_VOLTAGE_SCALE2 : stm32wbxx_ll_pwr.h
  • LL_PWR_SCR_C802AF : stm32wbxx_ll_pwr.h
  • LL_PWR_SCR_C802WUF : stm32wbxx_ll_pwr.h
  • LL_PWR_SCR_CBLEAF : stm32wbxx_ll_pwr.h
  • LL_PWR_SCR_CBLEWUF : stm32wbxx_ll_pwr.h
  • LL_PWR_SCR_CBORHF : stm32wbxx_ll_pwr.h
  • LL_PWR_SCR_CC2HF : stm32wbxx_ll_pwr.h
  • LL_PWR_SCR_CCRPEF : stm32wbxx_ll_pwr.h
  • LL_PWR_SCR_CSMPSFBF : stm32wbxx_ll_pwr.h
  • LL_PWR_SCR_CWUF : stm32wbxx_ll_pwr.h
  • LL_PWR_SCR_CWUF1 : stm32wbxx_ll_pwr.h
  • LL_PWR_SCR_CWUF2 : stm32wbxx_ll_pwr.h
  • LL_PWR_SCR_CWUF3 : stm32wbxx_ll_pwr.h
  • LL_PWR_SCR_CWUF4 : stm32wbxx_ll_pwr.h
  • LL_PWR_SCR_CWUF5 : stm32wbxx_ll_pwr.h
  • LL_PWR_SetBattChargResistor() : stm32wbxx_ll_pwr.h
  • LL_PWR_SetBORConfig() : stm32wbxx_ll_pwr.h
  • LL_PWR_SetFlashPowerModeLPRun() : stm32wbxx_ll_pwr.h
  • LL_PWR_SetFlashPowerModeSleep() : stm32wbxx_ll_pwr.h
  • LL_PWR_SetPowerMode() : stm32wbxx_ll_pwr.h
  • LL_PWR_SetPVDLevel() : stm32wbxx_ll_pwr.h
  • LL_PWR_SetRegulVoltageScaling() : stm32wbxx_ll_pwr.h
  • LL_PWR_SetWakeUpPinPolarityHigh() : stm32wbxx_ll_pwr.h
  • LL_PWR_SetWakeUpPinPolarityLow() : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_BYPASS : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_Disable() : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_Enable() : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_GetEffectiveMode() : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_GetMode() : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_GetOutputVoltageLevel() : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_GetStartupCurrent() : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_IsEnabled() : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V20 : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V25 : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V30 : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V35 : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40 : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V45 : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V50 : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V55 : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V60 : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V65 : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V70 : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V75 : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V80 : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V85 : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V90 : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_SetMode() : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_SetOutputVoltageLevel() : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_SetStartupCurrent() : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_STARTUP_CURRENT_100MA : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_STARTUP_CURRENT_120MA : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_STARTUP_CURRENT_140MA : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_STARTUP_CURRENT_160MA : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_STARTUP_CURRENT_180MA : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_STARTUP_CURRENT_200MA : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_STARTUP_CURRENT_220MA : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_STARTUP_CURRENT_80MA : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_STEP_DOWN : stm32wbxx_ll_pwr.h
  • LL_PWR_SR1_C2HF : stm32wbxx_ll_pwr.h
  • LL_PWR_SR1_WUF1 : stm32wbxx_ll_pwr.h
  • LL_PWR_SR1_WUF2 : stm32wbxx_ll_pwr.h
  • LL_PWR_SR1_WUF3 : stm32wbxx_ll_pwr.h
  • LL_PWR_SR1_WUF4 : stm32wbxx_ll_pwr.h
  • LL_PWR_SR1_WUF5 : stm32wbxx_ll_pwr.h
  • LL_PWR_SR1_WUFI : stm32wbxx_ll_pwr.h
  • LL_PWR_SR2_PVDO : stm32wbxx_ll_pwr.h
  • LL_PWR_SR2_PVMO1 : stm32wbxx_ll_pwr.h
  • LL_PWR_SR2_PVMO3 : stm32wbxx_ll_pwr.h
  • LL_PWR_SR2_REGLPF : stm32wbxx_ll_pwr.h
  • LL_PWR_SR2_REGLPS : stm32wbxx_ll_pwr.h
  • LL_PWR_SR2_VOSF : stm32wbxx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN1 : stm32wbxx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN2 : stm32wbxx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN3 : stm32wbxx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN4 : stm32wbxx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN5 : stm32wbxx_ll_pwr.h
  • LL_PWR_WriteReg : stm32wbxx_ll_pwr.h
  • LL_RCC_ADC_CLKSOURCE : stm32wbxx_ll_rcc.h
  • LL_RCC_ADC_CLKSOURCE_NONE : stm32wbxx_ll_rcc.h
  • LL_RCC_ADC_CLKSOURCE_PLL : stm32wbxx_ll_rcc.h
  • LL_RCC_ADC_CLKSOURCE_PLLSAI1 : stm32wbxx_ll_rcc.h
  • LL_RCC_ADC_CLKSOURCE_SYSCLK : stm32wbxx_ll_rcc.h
  • LL_RCC_APB1_DIV_1 : stm32wbxx_ll_rcc.h
  • LL_RCC_APB1_DIV_16 : stm32wbxx_ll_rcc.h
  • LL_RCC_APB1_DIV_2 : stm32wbxx_ll_rcc.h
  • LL_RCC_APB1_DIV_4 : stm32wbxx_ll_rcc.h
  • LL_RCC_APB1_DIV_8 : stm32wbxx_ll_rcc.h
  • LL_RCC_APB2_DIV_1 : stm32wbxx_ll_rcc.h
  • LL_RCC_APB2_DIV_16 : stm32wbxx_ll_rcc.h
  • LL_RCC_APB2_DIV_2 : stm32wbxx_ll_rcc.h
  • LL_RCC_APB2_DIV_4 : stm32wbxx_ll_rcc.h
  • LL_RCC_APB2_DIV_8 : stm32wbxx_ll_rcc.h
  • LL_RCC_CICR_CSSC : stm32wbxx_ll_rcc.h
  • LL_RCC_CICR_HSERDYC : stm32wbxx_ll_rcc.h
  • LL_RCC_CICR_HSI48RDYC : stm32wbxx_ll_rcc.h
  • LL_RCC_CICR_HSIRDYC : stm32wbxx_ll_rcc.h
  • LL_RCC_CICR_LSECSSC : stm32wbxx_ll_rcc.h
  • LL_RCC_CICR_LSERDYC : stm32wbxx_ll_rcc.h
  • LL_RCC_CICR_LSI1RDYC : stm32wbxx_ll_rcc.h
  • LL_RCC_CICR_LSI2RDYC : stm32wbxx_ll_rcc.h
  • LL_RCC_CICR_MSIRDYC : stm32wbxx_ll_rcc.h
  • LL_RCC_CICR_PLLRDYC : stm32wbxx_ll_rcc.h
  • LL_RCC_CICR_PLLSAI1RDYC : stm32wbxx_ll_rcc.h
  • LL_RCC_CIER_HSERDYIE : stm32wbxx_ll_rcc.h
  • LL_RCC_CIER_HSI48RDYIE : stm32wbxx_ll_rcc.h
  • LL_RCC_CIER_HSIRDYIE : stm32wbxx_ll_rcc.h
  • LL_RCC_CIER_LSECSSIE : stm32wbxx_ll_rcc.h
  • LL_RCC_CIER_LSERDYIE : stm32wbxx_ll_rcc.h
  • LL_RCC_CIER_LSI1RDYIE : stm32wbxx_ll_rcc.h
  • LL_RCC_CIER_LSI2RDYIE : stm32wbxx_ll_rcc.h
  • LL_RCC_CIER_MSIRDYIE : stm32wbxx_ll_rcc.h
  • LL_RCC_CIER_PLLRDYIE : stm32wbxx_ll_rcc.h
  • LL_RCC_CIER_PLLSAI1RDYIE : stm32wbxx_ll_rcc.h
  • LL_RCC_CIFR_CSSF : stm32wbxx_ll_rcc.h
  • LL_RCC_CIFR_HSERDYF : stm32wbxx_ll_rcc.h
  • LL_RCC_CIFR_HSI48RDYF : stm32wbxx_ll_rcc.h
  • LL_RCC_CIFR_HSIRDYF : stm32wbxx_ll_rcc.h
  • LL_RCC_CIFR_LSECSSF : stm32wbxx_ll_rcc.h
  • LL_RCC_CIFR_LSERDYF : stm32wbxx_ll_rcc.h
  • LL_RCC_CIFR_LSI1RDYF : stm32wbxx_ll_rcc.h
  • LL_RCC_CIFR_LSI2RDYF : stm32wbxx_ll_rcc.h
  • LL_RCC_CIFR_MSIRDYF : stm32wbxx_ll_rcc.h
  • LL_RCC_CIFR_PLLRDYF : stm32wbxx_ll_rcc.h
  • LL_RCC_CIFR_PLLSAI1RDYF : stm32wbxx_ll_rcc.h
  • LL_RCC_ClearFlag_HSECSS() : stm32wbxx_ll_rcc.h
  • LL_RCC_ClearFlag_HSERDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_ClearFlag_HSI48RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_ClearFlag_HSIRDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_ClearFlag_LSECSS() : stm32wbxx_ll_rcc.h
  • LL_RCC_ClearFlag_LSERDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_ClearFlag_LSI1RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_ClearFlag_LSI2RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_ClearFlag_MSIRDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_ClearFlag_PLLRDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_ClearFlag_PLLSAI1RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_ClearResetFlags() : stm32wbxx_ll_rcc.h
  • LL_RCC_CLK48_CLKSOURCE : stm32wbxx_ll_rcc.h
  • LL_RCC_CLK48_CLKSOURCE_HSI48 : stm32wbxx_ll_rcc.h
  • LL_RCC_CLK48_CLKSOURCE_MSI : stm32wbxx_ll_rcc.h
  • LL_RCC_CLK48_CLKSOURCE_PLL : stm32wbxx_ll_rcc.h
  • LL_RCC_CLK48_CLKSOURCE_PLLSAI1 : stm32wbxx_ll_rcc.h
  • LL_RCC_ConfigMCO() : stm32wbxx_ll_rcc.h
  • LL_RCC_ConfigRNGClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_CSR_BORRSTF : stm32wbxx_ll_rcc.h
  • LL_RCC_CSR_IWDGRSTF : stm32wbxx_ll_rcc.h
  • LL_RCC_CSR_LPWRRSTF : stm32wbxx_ll_rcc.h
  • LL_RCC_CSR_OBLRSTF : stm32wbxx_ll_rcc.h
  • LL_RCC_CSR_PINRSTF : stm32wbxx_ll_rcc.h
  • LL_RCC_CSR_SFTRSTF : stm32wbxx_ll_rcc.h
  • LL_RCC_CSR_WWDGRSTF : stm32wbxx_ll_rcc.h
  • LL_RCC_DeInit() : stm32wbxx_ll_rcc.c
  • LL_RCC_DisableIT_HSERDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_DisableIT_HSI48RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_DisableIT_HSIRDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_DisableIT_LSECSS() : stm32wbxx_ll_rcc.h
  • LL_RCC_DisableIT_LSERDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_DisableIT_LSI1RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_DisableIT_LSI2RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_DisableIT_MSIRDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_DisableIT_PLLRDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_DisableIT_PLLSAI1RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_DisableRTC() : stm32wbxx_ll_rcc.h
  • LL_RCC_EnableIT_HSERDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_EnableIT_HSI48RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_EnableIT_HSIRDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_EnableIT_LSECSS() : stm32wbxx_ll_rcc.h
  • LL_RCC_EnableIT_LSERDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_EnableIT_LSI1RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_EnableIT_LSI2RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_EnableIT_MSIRDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_EnableIT_PLLRDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_EnableIT_PLLSAI1RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_EnableRTC() : stm32wbxx_ll_rcc.h
  • LL_RCC_ForceBackupDomainReset() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetADCClockFreq() : stm32wbxx_ll_rcc.c
  • LL_RCC_GetADCClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetAHB4Prescaler() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetAHBPrescaler() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetAPB1Prescaler() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetAPB2Prescaler() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetCLK48ClockFreq() : stm32wbxx_ll_rcc.c
  • LL_RCC_GetCLK48ClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetClkAfterWakeFromStop() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetI2CClockFreq() : stm32wbxx_ll_rcc.c
  • LL_RCC_GetI2CClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetLPTIMClockFreq() : stm32wbxx_ll_rcc.c
  • LL_RCC_GetLPTIMClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetLPUARTClockFreq() : stm32wbxx_ll_rcc.c
  • LL_RCC_GetLPUARTClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetRFClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetRFWKPClockFreq() : stm32wbxx_ll_rcc.c
  • LL_RCC_GetRFWKPClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetRNGClockFreq() : stm32wbxx_ll_rcc.c
  • LL_RCC_GetRNGClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetRTCClockFreq() : stm32wbxx_ll_rcc.c
  • LL_RCC_GetRTCClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetSAIClockFreq() : stm32wbxx_ll_rcc.c
  • LL_RCC_GetSAIClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetSMPSClockFreq() : stm32wbxx_ll_rcc.c
  • LL_RCC_GetSMPSClockSelection() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetSMPSClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetSMPSPrescaler() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetSysClkSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetSystemClocksFreq() : stm32wbxx_ll_rcc.c
  • LL_RCC_GetUSARTClockFreq() : stm32wbxx_ll_rcc.c
  • LL_RCC_GetUSARTClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetUSBClockFreq() : stm32wbxx_ll_rcc.c
  • LL_RCC_GetUSBClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_CURRENTMAX_0 : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_CURRENTMAX_1 : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_CURRENTMAX_2 : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_CURRENTMAX_3 : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_CURRENTMAX_4 : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_CURRENTMAX_5 : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_CURRENTMAX_6 : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_CURRENTMAX_7 : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_Disable() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_DisableBypass() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_DisableDiv2() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_Enable() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_EnableBypass() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_EnableCSS() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_EnableDiv2() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_GetCapacitorTuning() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_GetCurrentControl() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_GetSenseAmplifier() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_IsClockControlLocked() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_IsEnabledDiv2() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_IsReady() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_SetCapacitorTuning() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_SetCurrentControl() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_SetSenseAmplifier() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSEAMPTHRESHOLD_1_2 : stm32wbxx_ll_rcc.h
  • LL_RCC_HSEAMPTHRESHOLD_3_4 : stm32wbxx_ll_rcc.h
  • LL_RCC_HSI48_Disable() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSI48_Enable() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSI48_GetCalibration() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSI48_IsReady() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSI_Disable() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSI_DisableAutoFromStop() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSI_DisableInStopMode() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSI_Enable() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSI_EnableAutoFromStop() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSI_EnableInStopMode() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSI_GetCalibration() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSI_GetCalibTrimming() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSI_IsEnabledInStopMode() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSI_IsReady() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSI_SetCalibTrimming() : stm32wbxx_ll_rcc.h
  • LL_RCC_I2C1_CLKSOURCE : stm32wbxx_ll_rcc.h
  • LL_RCC_I2C1_CLKSOURCE_HSI : stm32wbxx_ll_rcc.h
  • LL_RCC_I2C1_CLKSOURCE_PCLK1 : stm32wbxx_ll_rcc.h
  • LL_RCC_I2C1_CLKSOURCE_SYSCLK : stm32wbxx_ll_rcc.h
  • LL_RCC_I2C3_CLKSOURCE : stm32wbxx_ll_rcc.h
  • LL_RCC_I2C3_CLKSOURCE_HSI : stm32wbxx_ll_rcc.h
  • LL_RCC_I2C3_CLKSOURCE_PCLK1 : stm32wbxx_ll_rcc.h
  • LL_RCC_I2C3_CLKSOURCE_SYSCLK : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_BORRST() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_C2HPRE() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HPRE() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSECSS() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSERDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSI48RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSIRDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_IWDGRST() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LPWRRST() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSECSS() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSERDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSI1RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSI2RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_MSIRDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_OBLRST() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PINRST() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PLLRDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PLLSAI1RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PPRE1() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PPRE2() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_SFTRST() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_SHDHPRE() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_WWDGRST() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsEnabledIT_HSERDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsEnabledIT_HSI48RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsEnabledIT_HSIRDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsEnabledIT_LSECSS() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsEnabledIT_LSERDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsEnabledIT_LSI1RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsEnabledIT_LSI2RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsEnabledIT_MSIRDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsEnabledIT_PLLRDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsEnabledIT_PLLSAI1RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsEnabledRTC() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsRFUnderReset() : stm32wbxx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE : stm32wbxx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_HSI : stm32wbxx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_LSE : stm32wbxx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_LSI : stm32wbxx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_PCLK1 : stm32wbxx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE : stm32wbxx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE_HSI : stm32wbxx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE_LSE : stm32wbxx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE_LSI : stm32wbxx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE_PCLK1 : stm32wbxx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE : stm32wbxx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_HSI : stm32wbxx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_LSE : stm32wbxx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_PCLK1 : stm32wbxx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_SYSCLK : stm32wbxx_ll_rcc.h
  • LL_RCC_LSCO_CLKSOURCE_LSE : stm32wbxx_ll_rcc.h
  • LL_RCC_LSCO_CLKSOURCE_LSI : stm32wbxx_ll_rcc.h
  • LL_RCC_LSCO_Disable() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSCO_Enable() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSCO_GetSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSCO_SetSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSE_Disable() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSE_DisableBypass() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSE_DisableCSS() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSE_Enable() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSE_EnableBypass() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSE_EnableCSS() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSE_GetDriveCapability() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSE_IsCSSDetected() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSE_IsEnabled() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSE_IsReady() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSE_SetDriveCapability() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSEDRIVE_HIGH : stm32wbxx_ll_rcc.h
  • LL_RCC_LSEDRIVE_LOW : stm32wbxx_ll_rcc.h
  • LL_RCC_LSEDRIVE_MEDIUMHIGH : stm32wbxx_ll_rcc.h
  • LL_RCC_LSEDRIVE_MEDIUMLOW : stm32wbxx_ll_rcc.h
  • LL_RCC_LSI1_Disable() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSI1_Enable() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSI1_IsReady() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSI2_Disable() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSI2_Enable() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSI2_GetTrimming() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSI2_IsReady() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSI2_SetTrimming() : stm32wbxx_ll_rcc.h
  • LL_RCC_MCO1_DIV_1 : stm32wbxx_ll_rcc.h
  • LL_RCC_MCO1_DIV_16 : stm32wbxx_ll_rcc.h
  • LL_RCC_MCO1_DIV_2 : stm32wbxx_ll_rcc.h
  • LL_RCC_MCO1_DIV_4 : stm32wbxx_ll_rcc.h
  • LL_RCC_MCO1_DIV_8 : stm32wbxx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_HSE : stm32wbxx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_HSE_BEFORE_STAB : stm32wbxx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_HSI : stm32wbxx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_HSI48 : stm32wbxx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_LSE : stm32wbxx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_LSI1 : stm32wbxx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_LSI2 : stm32wbxx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_MSI : stm32wbxx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_NOCLOCK : stm32wbxx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_PLLCLK : stm32wbxx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_SYSCLK : stm32wbxx_ll_rcc.h
  • LL_RCC_MSI_Disable() : stm32wbxx_ll_rcc.h
  • LL_RCC_MSI_DisablePLLMode() : stm32wbxx_ll_rcc.h
  • LL_RCC_MSI_Enable() : stm32wbxx_ll_rcc.h
  • LL_RCC_MSI_EnablePLLMode() : stm32wbxx_ll_rcc.h
  • LL_RCC_MSI_GetCalibration() : stm32wbxx_ll_rcc.h
  • LL_RCC_MSI_GetCalibTrimming() : stm32wbxx_ll_rcc.h
  • LL_RCC_MSI_GetRange() : stm32wbxx_ll_rcc.h
  • LL_RCC_MSI_IsReady() : stm32wbxx_ll_rcc.h
  • LL_RCC_MSI_SetCalibTrimming() : stm32wbxx_ll_rcc.h
  • LL_RCC_MSI_SetRange() : stm32wbxx_ll_rcc.h
  • LL_RCC_MSIRANGE_0 : stm32wbxx_ll_rcc.h
  • LL_RCC_MSIRANGE_1 : stm32wbxx_ll_rcc.h
  • LL_RCC_MSIRANGE_10 : stm32wbxx_ll_rcc.h
  • LL_RCC_MSIRANGE_11 : stm32wbxx_ll_rcc.h
  • LL_RCC_MSIRANGE_2 : stm32wbxx_ll_rcc.h
  • LL_RCC_MSIRANGE_3 : stm32wbxx_ll_rcc.h
  • LL_RCC_MSIRANGE_4 : stm32wbxx_ll_rcc.h
  • LL_RCC_MSIRANGE_5 : stm32wbxx_ll_rcc.h
  • LL_RCC_MSIRANGE_6 : stm32wbxx_ll_rcc.h
  • LL_RCC_MSIRANGE_7 : stm32wbxx_ll_rcc.h
  • LL_RCC_MSIRANGE_8 : stm32wbxx_ll_rcc.h
  • LL_RCC_MSIRANGE_9 : stm32wbxx_ll_rcc.h
  • LL_RCC_PERIPH_FREQUENCY_NA : stm32wbxx_ll_rcc.h
  • LL_RCC_PERIPH_FREQUENCY_NO : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_48M() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_ADC() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_SAI() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_SYS() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_Disable() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_DisableDomain_48M() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_DisableDomain_ADC() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_DisableDomain_SAI() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_DisableDomain_SYS() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_Enable() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_EnableDomain_48M() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_EnableDomain_ADC() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_EnableDomain_SAI() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_EnableDomain_SYS() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_GetDivider() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_GetMainSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_GetN() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_GetP() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_GetQ() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_GetR() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_IsReady() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_SetMainSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLM_DIV_1 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLM_DIV_2 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLM_DIV_3 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLM_DIV_4 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLM_DIV_5 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLM_DIV_6 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLM_DIV_7 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLM_DIV_8 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_10 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_11 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_12 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_13 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_14 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_15 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_16 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_17 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_18 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_19 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_2 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_20 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_21 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_22 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_23 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_24 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_25 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_26 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_27 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_28 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_29 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_3 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_30 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_31 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_32 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_4 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_5 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_6 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_7 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_8 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_9 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_2 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_3 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_4 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_5 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_6 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_7 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_8 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLR_DIV_2 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLR_DIV_3 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLR_DIV_4 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLR_DIV_5 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLR_DIV_6 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLR_DIV_7 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLR_DIV_8 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1_ConfigDomain_48M() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1_ConfigDomain_ADC() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1_ConfigDomain_SAI() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1_Disable() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1_DisableDomain_48M() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1_DisableDomain_ADC() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1_DisableDomain_SAI() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1_Enable() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1_EnableDomain_48M() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1_EnableDomain_ADC() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1_EnableDomain_SAI() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1_GetN() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1_GetP() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1_GetQ() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1_GetR() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1_IsReady() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_10 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_11 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_12 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_13 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_14 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_15 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_16 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_17 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_18 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_19 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_2 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_20 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_21 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_22 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_23 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_24 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_25 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_26 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_27 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_28 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_29 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_3 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_30 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_31 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_32 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_4 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_5 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_6 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_7 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_8 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_9 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1Q_DIV_2 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1Q_DIV_3 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1Q_DIV_4 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1Q_DIV_5 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1Q_DIV_6 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1Q_DIV_7 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1Q_DIV_8 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1R_DIV_2 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1R_DIV_3 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1R_DIV_4 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1R_DIV_5 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1R_DIV_6 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1R_DIV_7 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1R_DIV_8 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSI : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSOURCE_MSI : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSOURCE_NONE : stm32wbxx_ll_rcc.h
  • LL_RCC_ReadReg : stm32wbxx_ll_rcc.h
  • LL_RCC_ReleaseBackupDomainReset() : stm32wbxx_ll_rcc.h
  • LL_RCC_RF_CLKSOURCE_HSE_DIV2 : stm32wbxx_ll_rcc.h
  • LL_RCC_RF_CLKSOURCE_HSI : stm32wbxx_ll_rcc.h
  • LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024 : stm32wbxx_ll_rcc.h
  • LL_RCC_RFWKP_CLKSOURCE_LSE : stm32wbxx_ll_rcc.h
  • LL_RCC_RFWKP_CLKSOURCE_LSI : stm32wbxx_ll_rcc.h
  • LL_RCC_RFWKP_CLKSOURCE_NONE : stm32wbxx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE : stm32wbxx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE_CLK48 : stm32wbxx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE_LSE : stm32wbxx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE_LSI : stm32wbxx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_HSE_DIV32 : stm32wbxx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_LSE : stm32wbxx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_LSI : stm32wbxx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_NONE : stm32wbxx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE : stm32wbxx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE_HSI : stm32wbxx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE_PIN : stm32wbxx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE_PLL : stm32wbxx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE_PLLSAI1 : stm32wbxx_ll_rcc.h
  • LL_RCC_SetADCClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_SetAHB4Prescaler() : stm32wbxx_ll_rcc.h
  • LL_RCC_SetAHBPrescaler() : stm32wbxx_ll_rcc.h
  • LL_RCC_SetAPB1Prescaler() : stm32wbxx_ll_rcc.h
  • LL_RCC_SetAPB2Prescaler() : stm32wbxx_ll_rcc.h
  • LL_RCC_SetCLK48ClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_SetClkAfterWakeFromStop() : stm32wbxx_ll_rcc.h
  • LL_RCC_SetI2CClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_SetLPTIMClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_SetLPUARTClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_SetRFWKPClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_SetRNGClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_SetRTCClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_SetSAIClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_SetSMPSClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_SetSMPSPrescaler() : stm32wbxx_ll_rcc.h
  • LL_RCC_SetSysClkSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_SetUSARTClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_SetUSBClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_SMPS_CLKSOURCE_HSE : stm32wbxx_ll_rcc.h
  • LL_RCC_SMPS_CLKSOURCE_HSI : stm32wbxx_ll_rcc.h
  • LL_RCC_SMPS_CLKSOURCE_MSI : stm32wbxx_ll_rcc.h
  • LL_RCC_SMPS_CLKSOURCE_STATUS_HSE : stm32wbxx_ll_rcc.h
  • LL_RCC_SMPS_CLKSOURCE_STATUS_HSI : stm32wbxx_ll_rcc.h
  • LL_RCC_SMPS_CLKSOURCE_STATUS_MSI : stm32wbxx_ll_rcc.h
  • LL_RCC_SMPS_CLKSOURCE_STATUS_NO_CLOCK : stm32wbxx_ll_rcc.h
  • LL_RCC_SMPS_DIV_0 : stm32wbxx_ll_rcc.h
  • LL_RCC_SMPS_DIV_1 : stm32wbxx_ll_rcc.h
  • LL_RCC_SMPS_DIV_2 : stm32wbxx_ll_rcc.h
  • LL_RCC_SMPS_DIV_3 : stm32wbxx_ll_rcc.h
  • LL_RCC_STOP_WAKEUPCLOCK_HSI : stm32wbxx_ll_rcc.h
  • LL_RCC_STOP_WAKEUPCLOCK_MSI : stm32wbxx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_HSE : stm32wbxx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_HSI : stm32wbxx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_MSI : stm32wbxx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_PLL : stm32wbxx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSE : stm32wbxx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSI : stm32wbxx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_MSI : stm32wbxx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_PLL : stm32wbxx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_1 : stm32wbxx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_10 : stm32wbxx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_128 : stm32wbxx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_16 : stm32wbxx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_2 : stm32wbxx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_256 : stm32wbxx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_3 : stm32wbxx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_32 : stm32wbxx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_4 : stm32wbxx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_5 : stm32wbxx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_512 : stm32wbxx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_6 : stm32wbxx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_64 : stm32wbxx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_8 : stm32wbxx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE : stm32wbxx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_HSI : stm32wbxx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_LSE : stm32wbxx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_PCLK2 : stm32wbxx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_SYSCLK : stm32wbxx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE : stm32wbxx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_HSI48 : stm32wbxx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_MSI : stm32wbxx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_PLL : stm32wbxx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_PLLSAI1 : stm32wbxx_ll_rcc.h
  • LL_RCC_WriteReg : stm32wbxx_ll_rcc.h
  • LL_RNG_CED_DISABLE : stm32wbxx_ll_rng.h
  • LL_RNG_CED_ENABLE : stm32wbxx_ll_rng.h
  • LL_RNG_ClearFlag_CEIS() : stm32wbxx_ll_rng.h
  • LL_RNG_ClearFlag_SEIS() : stm32wbxx_ll_rng.h
  • LL_RNG_CR_IE : stm32wbxx_ll_rng.h
  • LL_RNG_DeInit() : stm32wbxx_ll_rng.c
  • LL_RNG_Disable() : stm32wbxx_ll_rng.h
  • LL_RNG_DisableClkErrorDetect() : stm32wbxx_ll_rng.h
  • LL_RNG_DisableIT() : stm32wbxx_ll_rng.h
  • LL_RNG_Enable() : stm32wbxx_ll_rng.h
  • LL_RNG_EnableClkErrorDetect() : stm32wbxx_ll_rng.h
  • LL_RNG_EnableIT() : stm32wbxx_ll_rng.h
  • LL_RNG_Init() : stm32wbxx_ll_rng.c
  • LL_RNG_IsActiveFlag_CECS() : stm32wbxx_ll_rng.h
  • LL_RNG_IsActiveFlag_CEIS() : stm32wbxx_ll_rng.h
  • LL_RNG_IsActiveFlag_DRDY() : stm32wbxx_ll_rng.h
  • LL_RNG_IsActiveFlag_SECS() : stm32wbxx_ll_rng.h
  • LL_RNG_IsActiveFlag_SEIS() : stm32wbxx_ll_rng.h
  • LL_RNG_IsEnabled() : stm32wbxx_ll_rng.h
  • LL_RNG_IsEnabledClkErrorDetect() : stm32wbxx_ll_rng.h
  • LL_RNG_IsEnabledIT() : stm32wbxx_ll_rng.h
  • LL_RNG_ReadRandData32() : stm32wbxx_ll_rng.h
  • LL_RNG_ReadReg : stm32wbxx_ll_rng.h
  • LL_RNG_SR_CECS : stm32wbxx_ll_rng.h
  • LL_RNG_SR_CEIS : stm32wbxx_ll_rng.h
  • LL_RNG_SR_DRDY : stm32wbxx_ll_rng.h
  • LL_RNG_SR_SECS : stm32wbxx_ll_rng.h
  • LL_RNG_SR_SEIS : stm32wbxx_ll_rng.h
  • LL_RNG_StructInit() : stm32wbxx_ll_rng.c
  • LL_RNG_WriteReg : stm32wbxx_ll_rng.h
  • LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN : stm32wbxx_ll_rtc.h
  • LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL : stm32wbxx_ll_rtc.h
  • LL_RTC_ALARMOUT_ALMA : stm32wbxx_ll_rtc.h
  • LL_RTC_ALARMOUT_ALMB : stm32wbxx_ll_rtc.h
  • LL_RTC_ALARMOUT_DISABLE : stm32wbxx_ll_rtc.h
  • LL_RTC_ALARMOUT_WAKEUP : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_ConfigTime() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_DATEWEEKDAYSEL_DATE : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_Disable() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_DisableWeekday() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_Enable() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_EnableWeekday() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_GetDay() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_GetHour() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_GetMask() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_GetMinute() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_GetSecond() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_GetSubSecond() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_GetSubSecondMask() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_GetTime() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_GetTimeFormat() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_GetWeekDay() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_Init() : stm32wbxx_ll_rtc.c
  • LL_RTC_ALMA_MASK_ALL : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_MASK_DATEWEEKDAY : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_MASK_HOURS : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_MASK_MINUTES : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_MASK_NONE : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_MASK_SECONDS : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_SetDay() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_SetHour() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_SetMask() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_SetMinute() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_SetSecond() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_SetSubSecond() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_SetSubSecondMask() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_SetTimeFormat() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_SetWeekDay() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_StructInit() : stm32wbxx_ll_rtc.c
  • LL_RTC_ALMA_TIME_FORMAT_AM : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_TIME_FORMAT_PM : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_ConfigTime() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_DATEWEEKDAYSEL_DATE : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_Disable() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_DisableWeekday() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_Enable() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_EnableWeekday() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_GetDay() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_GetHour() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_GetMask() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_GetMinute() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_GetSecond() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_GetSubSecond() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_GetSubSecondMask() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_GetTime() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_GetTimeFormat() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_GetWeekDay() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_Init() : stm32wbxx_ll_rtc.c
  • LL_RTC_ALMB_MASK_ALL : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_MASK_DATEWEEKDAY : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_MASK_HOURS : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_MASK_MINUTES : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_MASK_NONE : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_MASK_SECONDS : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_SetDay() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_SetHour() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_SetMask() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_SetMinute() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_SetSecond() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_SetSubSecond() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_SetSubSecondMask() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_SetTimeFormat() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_SetWeekDay() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_StructInit() : stm32wbxx_ll_rtc.c
  • LL_RTC_ALMB_TIME_FORMAT_AM : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_TIME_FORMAT_PM : stm32wbxx_ll_rtc.h
  • LL_RTC_BAK_GetRegister() : stm32wbxx_ll_rtc.h
  • LL_RTC_BAK_SetRegister() : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR0 : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR1 : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR10 : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR11 : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR12 : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR13 : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR14 : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR15 : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR16 : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR17 : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR18 : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR19 : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR2 : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR3 : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR4 : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR5 : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR6 : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR7 : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR8 : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR9 : stm32wbxx_ll_rtc.h
  • LL_RTC_CAL_GetMinus() : stm32wbxx_ll_rtc.h
  • LL_RTC_CAL_GetOutputFreq() : stm32wbxx_ll_rtc.h
  • LL_RTC_CAL_GetPeriod() : stm32wbxx_ll_rtc.h
  • LL_RTC_CAL_IsPulseInserted() : stm32wbxx_ll_rtc.h
  • LL_RTC_CAL_SetMinus() : stm32wbxx_ll_rtc.h
  • LL_RTC_CAL_SetOutputFreq() : stm32wbxx_ll_rtc.h
  • LL_RTC_CAL_SetPeriod() : stm32wbxx_ll_rtc.h
  • LL_RTC_CAL_SetPulse() : stm32wbxx_ll_rtc.h
  • LL_RTC_CALIB_INSERTPULSE_NONE : stm32wbxx_ll_rtc.h
  • LL_RTC_CALIB_INSERTPULSE_SET : stm32wbxx_ll_rtc.h
  • LL_RTC_CALIB_OUTPUT_1HZ : stm32wbxx_ll_rtc.h
  • LL_RTC_CALIB_OUTPUT_512HZ : stm32wbxx_ll_rtc.h
  • LL_RTC_CALIB_OUTPUT_NONE : stm32wbxx_ll_rtc.h
  • LL_RTC_CALIB_PERIOD_16SEC : stm32wbxx_ll_rtc.h
  • LL_RTC_CALIB_PERIOD_32SEC : stm32wbxx_ll_rtc.h
  • LL_RTC_CALIB_PERIOD_8SEC : stm32wbxx_ll_rtc.h
  • LL_RTC_ClearFlag_ALRA() : stm32wbxx_ll_rtc.h
  • LL_RTC_ClearFlag_ALRB() : stm32wbxx_ll_rtc.h
  • LL_RTC_ClearFlag_ITS() : stm32wbxx_ll_rtc.h
  • LL_RTC_ClearFlag_RS() : stm32wbxx_ll_rtc.h
  • LL_RTC_ClearFlag_TAMP1() : stm32wbxx_ll_rtc.h
  • LL_RTC_ClearFlag_TAMP2() : stm32wbxx_ll_rtc.h
  • LL_RTC_ClearFlag_TAMP3() : stm32wbxx_ll_rtc.h
  • LL_RTC_ClearFlag_TS() : stm32wbxx_ll_rtc.h
  • LL_RTC_ClearFlag_TSOV() : stm32wbxx_ll_rtc.h
  • LL_RTC_ClearFlag_WUT() : stm32wbxx_ll_rtc.h
  • LL_RTC_CR_ALRAIE : stm32wbxx_ll_rtc.h
  • LL_RTC_CR_ALRBIE : stm32wbxx_ll_rtc.h
  • LL_RTC_CR_TSIE : stm32wbxx_ll_rtc.h
  • LL_RTC_CR_WUTIE : stm32wbxx_ll_rtc.h
  • LL_RTC_DATE_Config() : stm32wbxx_ll_rtc.h
  • LL_RTC_DATE_Get() : stm32wbxx_ll_rtc.h
  • LL_RTC_DATE_GetDay() : stm32wbxx_ll_rtc.h
  • LL_RTC_DATE_GetMonth() : stm32wbxx_ll_rtc.h
  • LL_RTC_DATE_GetWeekDay() : stm32wbxx_ll_rtc.h
  • LL_RTC_DATE_GetYear() : stm32wbxx_ll_rtc.h
  • LL_RTC_DATE_Init() : stm32wbxx_ll_rtc.c
  • LL_RTC_DATE_SetDay() : stm32wbxx_ll_rtc.h
  • LL_RTC_DATE_SetMonth() : stm32wbxx_ll_rtc.h
  • LL_RTC_DATE_SetWeekDay() : stm32wbxx_ll_rtc.h
  • LL_RTC_DATE_SetYear() : stm32wbxx_ll_rtc.h
  • LL_RTC_DATE_StructInit() : stm32wbxx_ll_rtc.c
  • LL_RTC_DeInit() : stm32wbxx_ll_rtc.c
  • LL_RTC_DisableInitMode() : stm32wbxx_ll_rtc.h
  • LL_RTC_DisableIT_ALRA() : stm32wbxx_ll_rtc.h
  • LL_RTC_DisableIT_ALRB() : stm32wbxx_ll_rtc.h
  • LL_RTC_DisableIT_TAMP() : stm32wbxx_ll_rtc.h
  • LL_RTC_DisableIT_TAMP1() : stm32wbxx_ll_rtc.h
  • LL_RTC_DisableIT_TAMP2() : stm32wbxx_ll_rtc.h
  • LL_RTC_DisableIT_TAMP3() : stm32wbxx_ll_rtc.h
  • LL_RTC_DisableIT_TS() : stm32wbxx_ll_rtc.h
  • LL_RTC_DisableIT_WUT() : stm32wbxx_ll_rtc.h
  • LL_RTC_DisableOutRemap() : stm32wbxx_ll_rtc.h
  • LL_RTC_DisableRefClock() : stm32wbxx_ll_rtc.h
  • LL_RTC_DisableShadowRegBypass() : stm32wbxx_ll_rtc.h
  • LL_RTC_DisableWriteProtection() : stm32wbxx_ll_rtc.h
  • LL_RTC_EnableInitMode() : stm32wbxx_ll_rtc.h
  • LL_RTC_EnableIT_ALRA() : stm32wbxx_ll_rtc.h
  • LL_RTC_EnableIT_ALRB() : stm32wbxx_ll_rtc.h
  • LL_RTC_EnableIT_TAMP() : stm32wbxx_ll_rtc.h
  • LL_RTC_EnableIT_TAMP1() : stm32wbxx_ll_rtc.h
  • LL_RTC_EnableIT_TAMP2() : stm32wbxx_ll_rtc.h
  • LL_RTC_EnableIT_TAMP3() : stm32wbxx_ll_rtc.h
  • LL_RTC_EnableIT_TS() : stm32wbxx_ll_rtc.h
  • LL_RTC_EnableIT_WUT() : stm32wbxx_ll_rtc.h
  • LL_RTC_EnableOutRemap() : stm32wbxx_ll_rtc.h
  • LL_RTC_EnableRefClock() : stm32wbxx_ll_rtc.h
  • LL_RTC_EnableShadowRegBypass() : stm32wbxx_ll_rtc.h
  • LL_RTC_EnableWriteProtection() : stm32wbxx_ll_rtc.h
  • LL_RTC_EnterInitMode() : stm32wbxx_ll_rtc.c
  • LL_RTC_ExitInitMode() : stm32wbxx_ll_rtc.c
  • LL_RTC_FORMAT_BCD : stm32wbxx_ll_rtc.h
  • LL_RTC_FORMAT_BIN : stm32wbxx_ll_rtc.h
  • LL_RTC_GetAlarmOutEvent() : stm32wbxx_ll_rtc.h
  • LL_RTC_GetAlarmOutputType() : stm32wbxx_ll_rtc.h
  • LL_RTC_GetAsynchPrescaler() : stm32wbxx_ll_rtc.h
  • LL_RTC_GetHourFormat() : stm32wbxx_ll_rtc.h
  • LL_RTC_GetOutputPolarity() : stm32wbxx_ll_rtc.h
  • LL_RTC_GetSynchPrescaler() : stm32wbxx_ll_rtc.h
  • LL_RTC_HOURFORMAT_24HOUR : stm32wbxx_ll_rtc.h
  • LL_RTC_HOURFORMAT_AMPM : stm32wbxx_ll_rtc.h
  • LL_RTC_Init() : stm32wbxx_ll_rtc.c
  • LL_RTC_IsActiveFlag_ALRA() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRAW() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRB() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRBW() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsActiveFlag_INIT() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsActiveFlag_INITS() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITS() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsActiveFlag_RECALP() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsActiveFlag_RS() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsActiveFlag_SHP() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP1() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP2() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP3() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TS() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TSOV() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsActiveFlag_WUT() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsActiveFlag_WUTW() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ALRA() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ALRB() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TAMP() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TAMP1() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TAMP2() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TAMP3() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TS() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsEnabledIT_WUT() : stm32wbxx_ll_rtc.h
  • LL_RTC_ISR_ALRAF : stm32wbxx_ll_rtc.h
  • LL_RTC_ISR_ALRAWF : stm32wbxx_ll_rtc.h
  • LL_RTC_ISR_ALRBF : stm32wbxx_ll_rtc.h
  • LL_RTC_ISR_ALRBWF : stm32wbxx_ll_rtc.h
  • LL_RTC_ISR_INITF : stm32wbxx_ll_rtc.h
  • LL_RTC_ISR_INITS : stm32wbxx_ll_rtc.h
  • LL_RTC_ISR_ITSF : stm32wbxx_ll_rtc.h
  • LL_RTC_ISR_RECALPF : stm32wbxx_ll_rtc.h
  • LL_RTC_ISR_RSF : stm32wbxx_ll_rtc.h
  • LL_RTC_ISR_SHPF : stm32wbxx_ll_rtc.h
  • LL_RTC_ISR_TAMP1F : stm32wbxx_ll_rtc.h
  • LL_RTC_ISR_TAMP2F : stm32wbxx_ll_rtc.h
  • LL_RTC_ISR_TAMP3F : stm32wbxx_ll_rtc.h
  • LL_RTC_ISR_TSF : stm32wbxx_ll_rtc.h
  • LL_RTC_ISR_TSOVF : stm32wbxx_ll_rtc.h
  • LL_RTC_ISR_WUTF : stm32wbxx_ll_rtc.h
  • LL_RTC_ISR_WUTWF : stm32wbxx_ll_rtc.h
  • LL_RTC_IsShadowRegBypassEnabled() : stm32wbxx_ll_rtc.h
  • LL_RTC_MONTH_APRIL : stm32wbxx_ll_rtc.h
  • LL_RTC_MONTH_AUGUST : stm32wbxx_ll_rtc.h
  • LL_RTC_MONTH_DECEMBER : stm32wbxx_ll_rtc.h
  • LL_RTC_MONTH_FEBRUARY : stm32wbxx_ll_rtc.h
  • LL_RTC_MONTH_JANUARY : stm32wbxx_ll_rtc.h
  • LL_RTC_MONTH_JULY : stm32wbxx_ll_rtc.h
  • LL_RTC_MONTH_JUNE : stm32wbxx_ll_rtc.h
  • LL_RTC_MONTH_MARCH : stm32wbxx_ll_rtc.h
  • LL_RTC_MONTH_MAY : stm32wbxx_ll_rtc.h
  • LL_RTC_MONTH_NOVEMBER : stm32wbxx_ll_rtc.h
  • LL_RTC_MONTH_OCTOBER : stm32wbxx_ll_rtc.h
  • LL_RTC_MONTH_SEPTEMBER : stm32wbxx_ll_rtc.h
  • LL_RTC_OUTPUTPOLARITY_PIN_HIGH : stm32wbxx_ll_rtc.h
  • LL_RTC_OUTPUTPOLARITY_PIN_LOW : stm32wbxx_ll_rtc.h
  • LL_RTC_ReadReg : stm32wbxx_ll_rtc.h
  • LL_RTC_SetAlarmOutEvent() : stm32wbxx_ll_rtc.h
  • LL_RTC_SetAlarmOutputType() : stm32wbxx_ll_rtc.h
  • LL_RTC_SetAsynchPrescaler() : stm32wbxx_ll_rtc.h
  • LL_RTC_SetHourFormat() : stm32wbxx_ll_rtc.h
  • LL_RTC_SetOutputPolarity() : stm32wbxx_ll_rtc.h
  • LL_RTC_SetSynchPrescaler() : stm32wbxx_ll_rtc.h
  • LL_RTC_SHIFT_SECOND_ADVANCE : stm32wbxx_ll_rtc.h
  • LL_RTC_SHIFT_SECOND_DELAY : stm32wbxx_ll_rtc.h
  • LL_RTC_StructInit() : stm32wbxx_ll_rtc.c
  • LL_RTC_TAMPCR_TAMP1IE : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPCR_TAMP2IE : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPCR_TAMP3IE : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPCR_TAMPIE : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_1 : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_2 : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_3 : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_Disable() : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_DisableActiveLevel() : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_DisableEraseBKP() : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_DisableMask() : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_DisablePullUp() : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_1RTCCLK : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_2RTCCLK : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_4RTCCLK : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_8RTCCLK : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_Enable() : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_EnableActiveLevel() : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_EnableEraseBKP() : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_EnableMask() : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_EnablePullUp() : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_2SAMPLE : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_4SAMPLE : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_8SAMPLE : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_DISABLE : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_GetFilterCount() : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_GetPrecharge() : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_GetSamplingFreq() : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_MASK_TAMPER1 : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_MASK_TAMPER2 : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_MASK_TAMPER3 : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_NOERASE_TAMPER1 : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_NOERASE_TAMPER2 : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_NOERASE_TAMPER3 : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_1024 : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_16384 : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_2048 : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_256 : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_32768 : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_4096 : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_512 : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_8192 : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_SetFilterCount() : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_SetPrecharge() : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_SetSamplingFreq() : stm32wbxx_ll_rtc.h
  • LL_RTC_TIME_Config() : stm32wbxx_ll_rtc.h
  • LL_RTC_TIME_DecHour() : stm32wbxx_ll_rtc.h
  • LL_RTC_TIME_DisableDayLightStore() : stm32wbxx_ll_rtc.h
  • LL_RTC_TIME_EnableDayLightStore() : stm32wbxx_ll_rtc.h
  • LL_RTC_TIME_FORMAT_AM_OR_24 : stm32wbxx_ll_rtc.h
  • LL_RTC_TIME_FORMAT_PM : stm32wbxx_ll_rtc.h
  • LL_RTC_TIME_Get() : stm32wbxx_ll_rtc.h
  • LL_RTC_TIME_GetFormat() : stm32wbxx_ll_rtc.h
  • LL_RTC_TIME_GetHour() : stm32wbxx_ll_rtc.h
  • LL_RTC_TIME_GetMinute() : stm32wbxx_ll_rtc.h
  • LL_RTC_TIME_GetSecond() : stm32wbxx_ll_rtc.h
  • LL_RTC_TIME_GetSubSecond() : stm32wbxx_ll_rtc.h
  • LL_RTC_TIME_IncHour() : stm32wbxx_ll_rtc.h
  • LL_RTC_TIME_Init() : stm32wbxx_ll_rtc.c
  • LL_RTC_TIME_IsDayLightStoreEnabled() : stm32wbxx_ll_rtc.h
  • LL_RTC_TIME_SetFormat() : stm32wbxx_ll_rtc.h
  • LL_RTC_TIME_SetHour() : stm32wbxx_ll_rtc.h
  • LL_RTC_TIME_SetMinute() : stm32wbxx_ll_rtc.h
  • LL_RTC_TIME_SetSecond() : stm32wbxx_ll_rtc.h
  • LL_RTC_TIME_StructInit() : stm32wbxx_ll_rtc.c
  • LL_RTC_TIME_Synchronize() : stm32wbxx_ll_rtc.h
  • LL_RTC_TIMESTAMP_EDGE_FALLING : stm32wbxx_ll_rtc.h
  • LL_RTC_TIMESTAMP_EDGE_RISING : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_Disable() : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_DisableInternalEvent() : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_DisableOnTamper() : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_Enable() : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_EnableInternalEvent() : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_EnableOnTamper() : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_GetActiveEdge() : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_GetDate() : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_GetDay() : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_GetHour() : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_GetMinute() : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_GetMonth() : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_GetSecond() : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_GetSubSecond() : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_GetTime() : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_GetTimeFormat() : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_GetWeekDay() : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_SetActiveEdge() : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_TIME_FORMAT_AM : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_TIME_FORMAT_PM : stm32wbxx_ll_rtc.h
  • LL_RTC_WaitForSynchro() : stm32wbxx_ll_rtc.c
  • LL_RTC_WAKEUP_Disable() : stm32wbxx_ll_rtc.h
  • LL_RTC_WAKEUP_Enable() : stm32wbxx_ll_rtc.h
  • LL_RTC_WAKEUP_GetAutoReload() : stm32wbxx_ll_rtc.h
  • LL_RTC_WAKEUP_GetClock() : stm32wbxx_ll_rtc.h
  • LL_RTC_WAKEUP_IsEnabled() : stm32wbxx_ll_rtc.h
  • LL_RTC_WAKEUP_SetAutoReload() : stm32wbxx_ll_rtc.h
  • LL_RTC_WAKEUP_SetClock() : stm32wbxx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_CKSPRE : stm32wbxx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_CKSPRE_WUT : stm32wbxx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_16 : stm32wbxx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_2 : stm32wbxx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_4 : stm32wbxx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_8 : stm32wbxx_ll_rtc.h
  • LL_RTC_WEEKDAY_FRIDAY : stm32wbxx_ll_rtc.h
  • LL_RTC_WEEKDAY_MONDAY : stm32wbxx_ll_rtc.h
  • LL_RTC_WEEKDAY_SATURDAY : stm32wbxx_ll_rtc.h
  • LL_RTC_WEEKDAY_SUNDAY : stm32wbxx_ll_rtc.h
  • LL_RTC_WEEKDAY_THURSDAY : stm32wbxx_ll_rtc.h
  • LL_RTC_WEEKDAY_TUESDAY : stm32wbxx_ll_rtc.h
  • LL_RTC_WEEKDAY_WEDNESDAY : stm32wbxx_ll_rtc.h
  • LL_RTC_WriteReg : stm32wbxx_ll_rtc.h
  • LL_SetSystemCoreClock() : stm32wbxx_ll_utils.c
  • LL_SPI_BAUDRATEPRESCALER_DIV128 : stm32wbxx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV16 : stm32wbxx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV2 : stm32wbxx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV256 : stm32wbxx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV32 : stm32wbxx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV4 : stm32wbxx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV64 : stm32wbxx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV8 : stm32wbxx_ll_spi.h
  • LL_SPI_ClearFlag_CRCERR() : stm32wbxx_ll_spi.h
  • LL_SPI_ClearFlag_FRE() : stm32wbxx_ll_spi.h
  • LL_SPI_ClearFlag_MODF() : stm32wbxx_ll_spi.h
  • LL_SPI_ClearFlag_OVR() : stm32wbxx_ll_spi.h
  • LL_SPI_CR2_ERRIE : stm32wbxx_ll_spi.h
  • LL_SPI_CR2_RXNEIE : stm32wbxx_ll_spi.h
  • LL_SPI_CR2_TXEIE : stm32wbxx_ll_spi.h
  • LL_SPI_CRC_16BIT : stm32wbxx_ll_spi.h
  • LL_SPI_CRC_8BIT : stm32wbxx_ll_spi.h
  • LL_SPI_CRCCALCULATION_DISABLE : stm32wbxx_ll_spi.h
  • LL_SPI_CRCCALCULATION_ENABLE : stm32wbxx_ll_spi.h
  • LL_SPI_DATAWIDTH_10BIT : stm32wbxx_ll_spi.h
  • LL_SPI_DATAWIDTH_11BIT : stm32wbxx_ll_spi.h
  • LL_SPI_DATAWIDTH_12BIT : stm32wbxx_ll_spi.h
  • LL_SPI_DATAWIDTH_13BIT : stm32wbxx_ll_spi.h
  • LL_SPI_DATAWIDTH_14BIT : stm32wbxx_ll_spi.h
  • LL_SPI_DATAWIDTH_15BIT : stm32wbxx_ll_spi.h
  • LL_SPI_DATAWIDTH_16BIT : stm32wbxx_ll_spi.h
  • LL_SPI_DATAWIDTH_4BIT : stm32wbxx_ll_spi.h
  • LL_SPI_DATAWIDTH_5BIT : stm32wbxx_ll_spi.h
  • LL_SPI_DATAWIDTH_6BIT : stm32wbxx_ll_spi.h
  • LL_SPI_DATAWIDTH_7BIT : stm32wbxx_ll_spi.h
  • LL_SPI_DATAWIDTH_8BIT : stm32wbxx_ll_spi.h
  • LL_SPI_DATAWIDTH_9BIT : stm32wbxx_ll_spi.h
  • LL_SPI_DeInit() : stm32wbxx_ll_spi.c
  • LL_SPI_Disable() : stm32wbxx_ll_spi.h
  • LL_SPI_DisableCRC() : stm32wbxx_ll_spi.h
  • LL_SPI_DisableDMAReq_RX() : stm32wbxx_ll_spi.h
  • LL_SPI_DisableDMAReq_TX() : stm32wbxx_ll_spi.h
  • LL_SPI_DisableIT_ERR() : stm32wbxx_ll_spi.h
  • LL_SPI_DisableIT_RXNE() : stm32wbxx_ll_spi.h
  • LL_SPI_DisableIT_TXE() : stm32wbxx_ll_spi.h
  • LL_SPI_DisableNSSPulseMgt() : stm32wbxx_ll_spi.h
  • LL_SPI_DMA_GetRegAddr() : stm32wbxx_ll_spi.h
  • LL_SPI_DMA_PARITY_EVEN : stm32wbxx_ll_spi.h
  • LL_SPI_DMA_PARITY_ODD : stm32wbxx_ll_spi.h
  • LL_SPI_Enable() : stm32wbxx_ll_spi.h
  • LL_SPI_EnableCRC() : stm32wbxx_ll_spi.h
  • LL_SPI_EnableDMAReq_RX() : stm32wbxx_ll_spi.h
  • LL_SPI_EnableDMAReq_TX() : stm32wbxx_ll_spi.h
  • LL_SPI_EnableIT_ERR() : stm32wbxx_ll_spi.h
  • LL_SPI_EnableIT_RXNE() : stm32wbxx_ll_spi.h
  • LL_SPI_EnableIT_TXE() : stm32wbxx_ll_spi.h
  • LL_SPI_EnableNSSPulseMgt() : stm32wbxx_ll_spi.h
  • LL_SPI_FULL_DUPLEX : stm32wbxx_ll_spi.h
  • LL_SPI_GetBaudRatePrescaler() : stm32wbxx_ll_spi.h
  • LL_SPI_GetClockPhase() : stm32wbxx_ll_spi.h
  • LL_SPI_GetClockPolarity() : stm32wbxx_ll_spi.h
  • LL_SPI_GetCRCPolynomial() : stm32wbxx_ll_spi.h
  • LL_SPI_GetCRCWidth() : stm32wbxx_ll_spi.h
  • LL_SPI_GetDataWidth() : stm32wbxx_ll_spi.h
  • LL_SPI_GetDMAParity_RX() : stm32wbxx_ll_spi.h
  • LL_SPI_GetDMAParity_TX() : stm32wbxx_ll_spi.h
  • LL_SPI_GetMode() : stm32wbxx_ll_spi.h
  • LL_SPI_GetNSSMode() : stm32wbxx_ll_spi.h
  • LL_SPI_GetRxCRC() : stm32wbxx_ll_spi.h
  • LL_SPI_GetRxFIFOLevel() : stm32wbxx_ll_spi.h
  • LL_SPI_GetRxFIFOThreshold() : stm32wbxx_ll_spi.h
  • LL_SPI_GetStandard() : stm32wbxx_ll_spi.h
  • LL_SPI_GetTransferBitOrder() : stm32wbxx_ll_spi.h
  • LL_SPI_GetTransferDirection() : stm32wbxx_ll_spi.h
  • LL_SPI_GetTxCRC() : stm32wbxx_ll_spi.h
  • LL_SPI_GetTxFIFOLevel() : stm32wbxx_ll_spi.h
  • LL_SPI_HALF_DUPLEX_RX : stm32wbxx_ll_spi.h
  • LL_SPI_HALF_DUPLEX_TX : stm32wbxx_ll_spi.h
  • LL_SPI_Init() : stm32wbxx_ll_spi.c
  • LL_SPI_IsActiveFlag_BSY() : stm32wbxx_ll_spi.h
  • LL_SPI_IsActiveFlag_CRCERR() : stm32wbxx_ll_spi.h
  • LL_SPI_IsActiveFlag_FRE() : stm32wbxx_ll_spi.h
  • LL_SPI_IsActiveFlag_MODF() : stm32wbxx_ll_spi.h
  • LL_SPI_IsActiveFlag_OVR() : stm32wbxx_ll_spi.h
  • LL_SPI_IsActiveFlag_RXNE() : stm32wbxx_ll_spi.h
  • LL_SPI_IsActiveFlag_TXE() : stm32wbxx_ll_spi.h
  • LL_SPI_IsEnabled() : stm32wbxx_ll_spi.h
  • LL_SPI_IsEnabledCRC() : stm32wbxx_ll_spi.h
  • LL_SPI_IsEnabledDMAReq_RX() : stm32wbxx_ll_spi.h
  • LL_SPI_IsEnabledDMAReq_TX() : stm32wbxx_ll_spi.h
  • LL_SPI_IsEnabledIT_ERR() : stm32wbxx_ll_spi.h
  • LL_SPI_IsEnabledIT_RXNE() : stm32wbxx_ll_spi.h
  • LL_SPI_IsEnabledIT_TXE() : stm32wbxx_ll_spi.h
  • LL_SPI_IsEnabledNSSPulse() : stm32wbxx_ll_spi.h
  • LL_SPI_LSB_FIRST : stm32wbxx_ll_spi.h
  • LL_SPI_MODE_MASTER : stm32wbxx_ll_spi.h
  • LL_SPI_MODE_SLAVE : stm32wbxx_ll_spi.h
  • LL_SPI_MSB_FIRST : stm32wbxx_ll_spi.h
  • LL_SPI_NSS_HARD_INPUT : stm32wbxx_ll_spi.h
  • LL_SPI_NSS_HARD_OUTPUT : stm32wbxx_ll_spi.h
  • LL_SPI_NSS_SOFT : stm32wbxx_ll_spi.h
  • LL_SPI_PHASE_1EDGE : stm32wbxx_ll_spi.h
  • LL_SPI_PHASE_2EDGE : stm32wbxx_ll_spi.h
  • LL_SPI_POLARITY_HIGH : stm32wbxx_ll_spi.h
  • LL_SPI_POLARITY_LOW : stm32wbxx_ll_spi.h
  • LL_SPI_PROTOCOL_MOTOROLA : stm32wbxx_ll_spi.h
  • LL_SPI_PROTOCOL_TI : stm32wbxx_ll_spi.h
  • LL_SPI_ReadReg : stm32wbxx_ll_spi.h
  • LL_SPI_ReceiveData16() : stm32wbxx_ll_spi.h
  • LL_SPI_ReceiveData8() : stm32wbxx_ll_spi.h
  • LL_SPI_RX_FIFO_EMPTY : stm32wbxx_ll_spi.h
  • LL_SPI_RX_FIFO_FULL : stm32wbxx_ll_spi.h
  • LL_SPI_RX_FIFO_HALF_FULL : stm32wbxx_ll_spi.h
  • LL_SPI_RX_FIFO_QUARTER_FULL : stm32wbxx_ll_spi.h
  • LL_SPI_RX_FIFO_TH_HALF : stm32wbxx_ll_spi.h
  • LL_SPI_RX_FIFO_TH_QUARTER : stm32wbxx_ll_spi.h
  • LL_SPI_SetBaudRatePrescaler() : stm32wbxx_ll_spi.h
  • LL_SPI_SetClockPhase() : stm32wbxx_ll_spi.h
  • LL_SPI_SetClockPolarity() : stm32wbxx_ll_spi.h
  • LL_SPI_SetCRCNext() : stm32wbxx_ll_spi.h
  • LL_SPI_SetCRCPolynomial() : stm32wbxx_ll_spi.h
  • LL_SPI_SetCRCWidth() : stm32wbxx_ll_spi.h
  • LL_SPI_SetDataWidth() : stm32wbxx_ll_spi.h
  • LL_SPI_SetDMAParity_RX() : stm32wbxx_ll_spi.h
  • LL_SPI_SetDMAParity_TX() : stm32wbxx_ll_spi.h
  • LL_SPI_SetMode() : stm32wbxx_ll_spi.h
  • LL_SPI_SetNSSMode() : stm32wbxx_ll_spi.h
  • LL_SPI_SetRxFIFOThreshold() : stm32wbxx_ll_spi.h
  • LL_SPI_SetStandard() : stm32wbxx_ll_spi.h
  • LL_SPI_SetTransferBitOrder() : stm32wbxx_ll_spi.h
  • LL_SPI_SetTransferDirection() : stm32wbxx_ll_spi.h
  • LL_SPI_SIMPLEX_RX : stm32wbxx_ll_spi.h
  • LL_SPI_SR_BSY : stm32wbxx_ll_spi.h
  • LL_SPI_SR_CRCERR : stm32wbxx_ll_spi.h
  • LL_SPI_SR_FRE : stm32wbxx_ll_spi.h
  • LL_SPI_SR_MODF : stm32wbxx_ll_spi.h
  • LL_SPI_SR_OVR : stm32wbxx_ll_spi.h
  • LL_SPI_SR_RXNE : stm32wbxx_ll_spi.h
  • LL_SPI_SR_TXE : stm32wbxx_ll_spi.h
  • LL_SPI_StructInit() : stm32wbxx_ll_spi.c
  • LL_SPI_TransmitData16() : stm32wbxx_ll_spi.h
  • LL_SPI_TransmitData8() : stm32wbxx_ll_spi.h
  • LL_SPI_TX_FIFO_EMPTY : stm32wbxx_ll_spi.h
  • LL_SPI_TX_FIFO_FULL : stm32wbxx_ll_spi.h
  • LL_SPI_TX_FIFO_HALF_FULL : stm32wbxx_ll_spi.h
  • LL_SPI_TX_FIFO_QUARTER_FULL : stm32wbxx_ll_spi.h
  • LL_SPI_WriteReg : stm32wbxx_ll_spi.h
  • LL_SYSCFG_ClearFlag_SP() : stm32wbxx_ll_system.h
  • LL_SYSCFG_DisableAnalogBooster() : stm32wbxx_ll_system.h
  • LL_SYSCFG_DisableAnalogGpioSwitch() : stm32wbxx_ll_system.h
  • LL_SYSCFG_DisableFastModePlus() : stm32wbxx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_DZC() : stm32wbxx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_IDC() : stm32wbxx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_IOC() : stm32wbxx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_IXC() : stm32wbxx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_OFC() : stm32wbxx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_UFC() : stm32wbxx_ll_system.h
  • LL_SYSCFG_DisableSecurityAccess() : stm32wbxx_ll_system.h
  • LL_SYSCFG_DisableSRAMFetch() : stm32wbxx_ll_system.h
  • LL_SYSCFG_EnableAnalogBooster() : stm32wbxx_ll_system.h
  • LL_SYSCFG_EnableAnalogGpioSwitch() : stm32wbxx_ll_system.h
  • LL_SYSCFG_EnableFastModePlus() : stm32wbxx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_DZC() : stm32wbxx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_IDC() : stm32wbxx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_IOC() : stm32wbxx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_IXC() : stm32wbxx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_OFC() : stm32wbxx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_UFC() : stm32wbxx_ll_system.h
  • LL_SYSCFG_EnableSecurityAccess() : stm32wbxx_ll_system.h
  • LL_SYSCFG_EnableSRAM2Erase() : stm32wbxx_ll_system.h
  • LL_SYSCFG_EnableSRAM2PageWRP : stm32wbxx_ll_system.h
  • LL_SYSCFG_EnableSRAM2PageWRP_0_31() : stm32wbxx_ll_system.h
  • LL_SYSCFG_EnableSRAM2PageWRP_32_63() : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_LINE0 : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_LINE1 : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_LINE10 : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_LINE11 : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_LINE12 : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_LINE13 : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_LINE14 : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_LINE15 : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_LINE2 : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_LINE3 : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_LINE4 : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_LINE5 : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_LINE6 : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_LINE7 : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_LINE8 : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_LINE9 : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_PORTA : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_PORTB : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_PORTC : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_PORTD : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_PORTE : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_PORTH : stm32wbxx_ll_system.h
  • LL_SYSCFG_GetEXTISource() : stm32wbxx_ll_system.h
  • LL_SYSCFG_GetRemapMemory() : stm32wbxx_ll_system.h
  • LL_SYSCFG_GetTIMBreakInputs() : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP1_DisableIT() : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP1_EnableIT() : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP1_EXTI10 : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP1_EXTI11 : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP1_EXTI12 : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP1_EXTI13 : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP1_EXTI14 : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP1_EXTI15 : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP1_EXTI5 : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP1_EXTI6 : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP1_EXTI7 : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP1_EXTI8 : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP1_EXTI9 : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP1_IsEnabledIT() : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP1_TIM1 : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP1_TIM16 : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP1_TIM17 : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP2_DisableIT() : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP2_EnableIT() : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP2_IsEnabledIT() : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP2_PVD : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP2_PVM1 : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP2_PVM3 : stm32wbxx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 : stm32wbxx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 : stm32wbxx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB6 : stm32wbxx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB7 : stm32wbxx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB8 : stm32wbxx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB9 : stm32wbxx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_SP() : stm32wbxx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_DZC() : stm32wbxx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_IDC() : stm32wbxx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_IOC() : stm32wbxx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_IXC() : stm32wbxx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_OFC() : stm32wbxx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_UFC() : stm32wbxx_ll_system.h
  • LL_SYSCFG_IsEnabledSecurityAccess() : stm32wbxx_ll_system.h
  • LL_SYSCFG_IsEnabledSRAMFetch() : stm32wbxx_ll_system.h
  • LL_SYSCFG_IsSRAM2EraseOngoing() : stm32wbxx_ll_system.h
  • LL_SYSCFG_LockSRAM2WRP() : stm32wbxx_ll_system.h
  • LL_SYSCFG_REMAP_FLASH : stm32wbxx_ll_system.h
  • LL_SYSCFG_REMAP_QUADSPI : stm32wbxx_ll_system.h
  • LL_SYSCFG_REMAP_SRAM : stm32wbxx_ll_system.h
  • LL_SYSCFG_REMAP_SYSTEMFLASH : stm32wbxx_ll_system.h
  • LL_SYSCFG_SECURE_ACCESS_AES1 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SECURE_ACCESS_AES2 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SECURE_ACCESS_PKA : stm32wbxx_ll_system.h
  • LL_SYSCFG_SECURE_ACCESS_RNG : stm32wbxx_ll_system.h
  • LL_SYSCFG_SetEXTISource() : stm32wbxx_ll_system.h
  • LL_SYSCFG_SetRemapMemory() : stm32wbxx_ll_system.h
  • LL_SYSCFG_SetTIMBreakInputs() : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE0 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE1 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE10 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE11 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE12 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE13 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE14 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE15 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE16 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE17 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE18 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE19 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE2 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE20 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE21 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE22 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE23 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE24 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE25 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE26 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE27 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE28 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE29 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE3 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE30 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE31 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE32 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE33 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE34 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE35 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE36 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE37 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE38 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE39 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE4 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE40 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE41 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE42 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE43 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE44 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE45 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE46 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE47 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE48 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE49 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE5 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE50 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE51 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE52 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE53 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE54 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE55 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE56 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE57 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE58 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE59 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE6 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE60 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE61 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE62 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE63 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE7 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE8 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE9 : stm32wbxx_ll_system.h
  • LL_SYSCFG_TIMBREAK_ECC : stm32wbxx_ll_system.h
  • LL_SYSCFG_TIMBREAK_LOCKUP : stm32wbxx_ll_system.h
  • LL_SYSCFG_TIMBREAK_PVD : stm32wbxx_ll_system.h
  • LL_SYSCFG_TIMBREAK_SRAM2_PARITY : stm32wbxx_ll_system.h
  • LL_SYSCFG_UnlockSRAM2WRP() : stm32wbxx_ll_system.h
  • LL_SYSTICK_CLKSOURCE_HCLK : stm32wbxx_ll_cortex.h
  • LL_SYSTICK_CLKSOURCE_HCLK_DIV8 : stm32wbxx_ll_cortex.h
  • LL_SYSTICK_DisableIT() : stm32wbxx_ll_cortex.h
  • LL_SYSTICK_EnableIT() : stm32wbxx_ll_cortex.h
  • LL_SYSTICK_GetClkSource() : stm32wbxx_ll_cortex.h
  • LL_SYSTICK_IsActiveCounterFlag() : stm32wbxx_ll_cortex.h
  • LL_SYSTICK_IsEnabledIT() : stm32wbxx_ll_cortex.h
  • LL_SYSTICK_SetClkSource() : stm32wbxx_ll_cortex.h
  • LL_TIM_ACTIVEINPUT_DIRECTTI : stm32wbxx_ll_tim.h
  • LL_TIM_ACTIVEINPUT_INDIRECTTI : stm32wbxx_ll_tim.h
  • LL_TIM_ACTIVEINPUT_TRC : stm32wbxx_ll_tim.h
  • LL_TIM_AUTOMATICOUTPUT_DISABLE : stm32wbxx_ll_tim.h
  • LL_TIM_AUTOMATICOUTPUT_ENABLE : stm32wbxx_ll_tim.h
  • LL_TIM_BDTR_Init() : stm32wbxx_ll_tim.c
  • LL_TIM_BDTR_StructInit() : stm32wbxx_ll_tim.c
  • LL_TIM_BKIN_POLARITY_HIGH : stm32wbxx_ll_tim.h
  • LL_TIM_BKIN_POLARITY_LOW : stm32wbxx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_BKCOMP1 : stm32wbxx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_BKCOMP2 : stm32wbxx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_BKIN : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_DISABLE : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_ENABLE : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV16_N5 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV16_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV16_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1_N2 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1_N4 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV2_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV2_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV32_N5 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV32_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV32_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV4_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV4_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV8_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV8_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_POLARITY_HIGH : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_POLARITY_LOW : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_DISABLE : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_ENABLE : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV16_N5 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV16_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV16_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1_N2 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1_N4 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV2_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV2_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV32_N5 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV32_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV32_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV4_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV4_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV8_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV8_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_INPUT_BKIN : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_INPUT_BKIN2 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_POLARITY_HIGH : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_POLARITY_LOW : stm32wbxx_ll_tim.h
  • LL_TIM_CC_DisableChannel() : stm32wbxx_ll_tim.h
  • LL_TIM_CC_DisablePreload() : stm32wbxx_ll_tim.h
  • LL_TIM_CC_EnableChannel() : stm32wbxx_ll_tim.h
  • LL_TIM_CC_EnablePreload() : stm32wbxx_ll_tim.h
  • LL_TIM_CC_GetDMAReqTrigger() : stm32wbxx_ll_tim.h
  • LL_TIM_CC_IsEnabledChannel() : stm32wbxx_ll_tim.h
  • LL_TIM_CC_SetDMAReqTrigger() : stm32wbxx_ll_tim.h
  • LL_TIM_CC_SetLockLevel() : stm32wbxx_ll_tim.h
  • LL_TIM_CC_SetUpdate() : stm32wbxx_ll_tim.h
  • LL_TIM_CCDMAREQUEST_CC : stm32wbxx_ll_tim.h
  • LL_TIM_CCDMAREQUEST_UPDATE : stm32wbxx_ll_tim.h
  • LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI : stm32wbxx_ll_tim.h
  • LL_TIM_CCUPDATESOURCE_COMG_ONLY : stm32wbxx_ll_tim.h
  • LL_TIM_CHANNEL_CH1 : stm32wbxx_ll_tim.h
  • LL_TIM_CHANNEL_CH1N : stm32wbxx_ll_tim.h
  • LL_TIM_CHANNEL_CH2 : stm32wbxx_ll_tim.h
  • LL_TIM_CHANNEL_CH2N : stm32wbxx_ll_tim.h
  • LL_TIM_CHANNEL_CH3 : stm32wbxx_ll_tim.h
  • LL_TIM_CHANNEL_CH3N : stm32wbxx_ll_tim.h
  • LL_TIM_CHANNEL_CH4 : stm32wbxx_ll_tim.h
  • LL_TIM_CHANNEL_CH5 : stm32wbxx_ll_tim.h
  • LL_TIM_CHANNEL_CH6 : stm32wbxx_ll_tim.h
  • LL_TIM_ClearFlag_BRK() : stm32wbxx_ll_tim.h
  • LL_TIM_ClearFlag_BRK2() : stm32wbxx_ll_tim.h
  • LL_TIM_ClearFlag_CC1() : stm32wbxx_ll_tim.h
  • LL_TIM_ClearFlag_CC1OVR() : stm32wbxx_ll_tim.h
  • LL_TIM_ClearFlag_CC2() : stm32wbxx_ll_tim.h
  • LL_TIM_ClearFlag_CC2OVR() : stm32wbxx_ll_tim.h
  • LL_TIM_ClearFlag_CC3() : stm32wbxx_ll_tim.h
  • LL_TIM_ClearFlag_CC3OVR() : stm32wbxx_ll_tim.h
  • LL_TIM_ClearFlag_CC4() : stm32wbxx_ll_tim.h
  • LL_TIM_ClearFlag_CC4OVR() : stm32wbxx_ll_tim.h
  • LL_TIM_ClearFlag_CC5() : stm32wbxx_ll_tim.h
  • LL_TIM_ClearFlag_CC6() : stm32wbxx_ll_tim.h
  • LL_TIM_ClearFlag_COM() : stm32wbxx_ll_tim.h
  • LL_TIM_ClearFlag_SYSBRK() : stm32wbxx_ll_tim.h
  • LL_TIM_ClearFlag_TRIG() : stm32wbxx_ll_tim.h
  • LL_TIM_ClearFlag_UPDATE() : stm32wbxx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV1 : stm32wbxx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV2 : stm32wbxx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV4 : stm32wbxx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_EXT_MODE1 : stm32wbxx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_EXT_MODE2 : stm32wbxx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_INTERNAL : stm32wbxx_ll_tim.h
  • LL_TIM_ConfigBRK() : stm32wbxx_ll_tim.h
  • LL_TIM_ConfigBRK2() : stm32wbxx_ll_tim.h
  • LL_TIM_ConfigDMABurst() : stm32wbxx_ll_tim.h
  • LL_TIM_ConfigETR() : stm32wbxx_ll_tim.h
  • LL_TIM_COUNTERDIRECTION_DOWN : stm32wbxx_ll_tim.h
  • LL_TIM_COUNTERDIRECTION_UP : stm32wbxx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_DOWN : stm32wbxx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_UP : stm32wbxx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_UP_DOWN : stm32wbxx_ll_tim.h
  • LL_TIM_COUNTERMODE_DOWN : stm32wbxx_ll_tim.h
  • LL_TIM_COUNTERMODE_UP : stm32wbxx_ll_tim.h
  • LL_TIM_DeInit() : stm32wbxx_ll_tim.c
  • LL_TIM_DIER_BIE : stm32wbxx_ll_tim.h
  • LL_TIM_DIER_CC1IE : stm32wbxx_ll_tim.h
  • LL_TIM_DIER_CC2IE : stm32wbxx_ll_tim.h
  • LL_TIM_DIER_CC3IE : stm32wbxx_ll_tim.h
  • LL_TIM_DIER_CC4IE : stm32wbxx_ll_tim.h
  • LL_TIM_DIER_COMIE : stm32wbxx_ll_tim.h
  • LL_TIM_DIER_TIE : stm32wbxx_ll_tim.h
  • LL_TIM_DIER_UIE : stm32wbxx_ll_tim.h
  • LL_TIM_DisableAllOutputs() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableARRPreload() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableAutomaticOutput() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableBreakInputSource() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableBRK() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableBRK2() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableCounter() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC1() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC2() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC3() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC4() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableDMAReq_COM() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableDMAReq_TRIG() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableDMAReq_UPDATE() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableExternalClock() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableIT_BRK() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableIT_CC1() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableIT_CC2() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableIT_CC3() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableIT_CC4() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableIT_COM() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableIT_TRIG() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableIT_UPDATE() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableMasterSlaveMode() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableUIFRemap() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableUpdateEvent() : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_AF1 : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_AF2 : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_ARR : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_BDTR : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCER : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR1 : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR2 : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR3 : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR1 : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR2 : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR3 : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR4 : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR5 : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR6 : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CNT : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CR1 : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CR2 : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_DIER : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_EGR : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_OR : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_PSC : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_RCR : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_SMCR : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_SR : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_10TRANSFERS : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_11TRANSFERS : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_12TRANSFERS : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_13TRANSFERS : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_14TRANSFERS : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_15TRANSFERS : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_16TRANSFERS : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_17TRANSFERS : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_18TRANSFERS : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_1TRANSFER : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_2TRANSFERS : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_3TRANSFERS : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_4TRANSFERS : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_5TRANSFERS : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_6TRANSFERS : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_7TRANSFERS : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_8TRANSFERS : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_9TRANSFERS : stm32wbxx_ll_tim.h
  • LL_TIM_EnableAllOutputs() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableARRPreload() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableAutomaticOutput() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableBreakInputSource() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableBRK() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableBRK2() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableCounter() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC1() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC2() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC3() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC4() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableDMAReq_COM() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableDMAReq_TRIG() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableDMAReq_UPDATE() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableExternalClock() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableIT_BRK() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableIT_CC1() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableIT_CC2() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableIT_CC3() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableIT_CC4() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableIT_COM() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableIT_TRIG() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableIT_UPDATE() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableMasterSlaveMode() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableUIFRemap() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableUpdateEvent() : stm32wbxx_ll_tim.h
  • LL_TIM_ENCODER_Init() : stm32wbxx_ll_tim.c
  • LL_TIM_ENCODER_StructInit() : stm32wbxx_ll_tim.c
  • LL_TIM_ENCODERMODE_X2_TI1 : stm32wbxx_ll_tim.h
  • LL_TIM_ENCODERMODE_X2_TI2 : stm32wbxx_ll_tim.h
  • LL_TIM_ENCODERMODE_X4_TI12 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N5 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N2 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N4 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV2_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV2_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N5 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV4_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV4_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV8_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV8_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_POLARITY_INVERTED : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_POLARITY_NONINVERTED : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV1 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV2 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV4 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV8 : stm32wbxx_ll_tim.h
  • LL_TIM_ETRSOURCE_ADC1_AWD1 : stm32wbxx_ll_tim.h
  • LL_TIM_ETRSOURCE_ADC1_AWD2 : stm32wbxx_ll_tim.h
  • LL_TIM_ETRSOURCE_ADC1_AWD3 : stm32wbxx_ll_tim.h
  • LL_TIM_ETRSOURCE_COMP1 : stm32wbxx_ll_tim.h
  • LL_TIM_ETRSOURCE_COMP2 : stm32wbxx_ll_tim.h
  • LL_TIM_ETRSOURCE_GPIO : stm32wbxx_ll_tim.h
  • LL_TIM_ETRSOURCE_LEGACY : stm32wbxx_ll_tim.h
  • LL_TIM_GenerateEvent_BRK() : stm32wbxx_ll_tim.h
  • LL_TIM_GenerateEvent_BRK2() : stm32wbxx_ll_tim.h
  • LL_TIM_GenerateEvent_CC1() : stm32wbxx_ll_tim.h
  • LL_TIM_GenerateEvent_CC2() : stm32wbxx_ll_tim.h
  • LL_TIM_GenerateEvent_CC3() : stm32wbxx_ll_tim.h
  • LL_TIM_GenerateEvent_CC4() : stm32wbxx_ll_tim.h
  • LL_TIM_GenerateEvent_COM() : stm32wbxx_ll_tim.h
  • LL_TIM_GenerateEvent_TRIG() : stm32wbxx_ll_tim.h
  • LL_TIM_GenerateEvent_UPDATE() : stm32wbxx_ll_tim.h
  • LL_TIM_GetAutoReload() : stm32wbxx_ll_tim.h
  • LL_TIM_GetClockDivision() : stm32wbxx_ll_tim.h
  • LL_TIM_GetCounter() : stm32wbxx_ll_tim.h
  • LL_TIM_GetCounterMode() : stm32wbxx_ll_tim.h
  • LL_TIM_GetDirection() : stm32wbxx_ll_tim.h
  • LL_TIM_GetOnePulseMode() : stm32wbxx_ll_tim.h
  • LL_TIM_GetPrescaler() : stm32wbxx_ll_tim.h
  • LL_TIM_GetRepetitionCounter() : stm32wbxx_ll_tim.h
  • LL_TIM_GetUpdateSource() : stm32wbxx_ll_tim.h
  • LL_TIM_GROUPCH5_NONE : stm32wbxx_ll_tim.h
  • LL_TIM_GROUPCH5_OC1REFC : stm32wbxx_ll_tim.h
  • LL_TIM_GROUPCH5_OC2REFC : stm32wbxx_ll_tim.h
  • LL_TIM_GROUPCH5_OC3REFC : stm32wbxx_ll_tim.h
  • LL_TIM_HALLSENSOR_Init() : stm32wbxx_ll_tim.c
  • LL_TIM_HALLSENSOR_StructInit() : stm32wbxx_ll_tim.c
  • LL_TIM_IC_Config() : stm32wbxx_ll_tim.h
  • LL_TIM_IC_DisableXORCombination() : stm32wbxx_ll_tim.h
  • LL_TIM_IC_EnableXORCombination() : stm32wbxx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1 : stm32wbxx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N5 : stm32wbxx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N2 : stm32wbxx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N4 : stm32wbxx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV2_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV2_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N5 : stm32wbxx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV4_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV4_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV8_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV8_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_IC_GetActiveInput() : stm32wbxx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH1() : stm32wbxx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH2() : stm32wbxx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH3() : stm32wbxx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH4() : stm32wbxx_ll_tim.h
  • LL_TIM_IC_GetFilter() : stm32wbxx_ll_tim.h
  • LL_TIM_IC_GetPolarity() : stm32wbxx_ll_tim.h
  • LL_TIM_IC_GetPrescaler() : stm32wbxx_ll_tim.h
  • LL_TIM_IC_Init() : stm32wbxx_ll_tim.c
  • LL_TIM_IC_IsEnabledXORCombination() : stm32wbxx_ll_tim.h
  • LL_TIM_IC_POLARITY_BOTHEDGE : stm32wbxx_ll_tim.h
  • LL_TIM_IC_POLARITY_FALLING : stm32wbxx_ll_tim.h
  • LL_TIM_IC_POLARITY_RISING : stm32wbxx_ll_tim.h
  • LL_TIM_IC_SetActiveInput() : stm32wbxx_ll_tim.h
  • LL_TIM_IC_SetFilter() : stm32wbxx_ll_tim.h
  • LL_TIM_IC_SetPolarity() : stm32wbxx_ll_tim.h
  • LL_TIM_IC_SetPrescaler() : stm32wbxx_ll_tim.h
  • LL_TIM_IC_StructInit() : stm32wbxx_ll_tim.c
  • LL_TIM_ICPSC_DIV1 : stm32wbxx_ll_tim.h
  • LL_TIM_ICPSC_DIV2 : stm32wbxx_ll_tim.h
  • LL_TIM_ICPSC_DIV4 : stm32wbxx_ll_tim.h
  • LL_TIM_ICPSC_DIV8 : stm32wbxx_ll_tim.h
  • LL_TIM_Init() : stm32wbxx_ll_tim.c
  • LL_TIM_IsActiveFlag_BRK() : stm32wbxx_ll_tim.h
  • LL_TIM_IsActiveFlag_BRK2() : stm32wbxx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC1() : stm32wbxx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC1OVR() : stm32wbxx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC2() : stm32wbxx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC2OVR() : stm32wbxx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC3() : stm32wbxx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC3OVR() : stm32wbxx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC4() : stm32wbxx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC4OVR() : stm32wbxx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC5() : stm32wbxx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC6() : stm32wbxx_ll_tim.h
  • LL_TIM_IsActiveFlag_COM() : stm32wbxx_ll_tim.h
  • LL_TIM_IsActiveFlag_SYSBRK() : stm32wbxx_ll_tim.h
  • LL_TIM_IsActiveFlag_TRIG() : stm32wbxx_ll_tim.h
  • LL_TIM_IsActiveFlag_UPDATE() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledAllOutputs() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledARRPreload() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledAutomaticOutput() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledCounter() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC1() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC2() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC3() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC4() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_COM() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_TRIG() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_UPDATE() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledExternalClock() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledIT_BRK() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC1() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC2() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC3() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC4() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledIT_COM() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledIT_TRIG() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledIT_UPDATE() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledMasterSlaveMode() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledUpdateEvent() : stm32wbxx_ll_tim.h
  • LL_TIM_LOCKLEVEL_1 : stm32wbxx_ll_tim.h
  • LL_TIM_LOCKLEVEL_2 : stm32wbxx_ll_tim.h
  • LL_TIM_LOCKLEVEL_3 : stm32wbxx_ll_tim.h
  • LL_TIM_LOCKLEVEL_OFF : stm32wbxx_ll_tim.h
  • LL_TIM_OC_ConfigOutput() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_DisableClear() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_DisableFast() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_DisablePreload() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_EnableClear() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_EnableFast() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_EnablePreload() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_GetCompareCH1() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_GetCompareCH2() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_GetCompareCH3() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_GetCompareCH4() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_GetCompareCH5() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_GetCompareCH6() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_GetIdleState() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_GetMode() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_GetPolarity() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_Init() : stm32wbxx_ll_tim.c
  • LL_TIM_OC_IsEnabledClear() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_IsEnabledFast() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_IsEnabledPreload() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_SetCompareCH1() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_SetCompareCH2() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_SetCompareCH3() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_SetCompareCH4() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_SetCompareCH5() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_SetCompareCH6() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_SetDeadTime() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_SetIdleState() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_SetMode() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_SetPolarity() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_StructInit() : stm32wbxx_ll_tim.c
  • LL_TIM_OCIDLESTATE_HIGH : stm32wbxx_ll_tim.h
  • LL_TIM_OCIDLESTATE_LOW : stm32wbxx_ll_tim.h
  • LL_TIM_OCMODE_ACTIVE : stm32wbxx_ll_tim.h
  • LL_TIM_OCMODE_ASSYMETRIC_PWM1 : stm32wbxx_ll_tim.h
  • LL_TIM_OCMODE_ASSYMETRIC_PWM2 : stm32wbxx_ll_tim.h
  • LL_TIM_OCMODE_COMBINED_PWM1 : stm32wbxx_ll_tim.h
  • LL_TIM_OCMODE_COMBINED_PWM2 : stm32wbxx_ll_tim.h
  • LL_TIM_OCMODE_FORCED_ACTIVE : stm32wbxx_ll_tim.h
  • LL_TIM_OCMODE_FORCED_INACTIVE : stm32wbxx_ll_tim.h
  • LL_TIM_OCMODE_FROZEN : stm32wbxx_ll_tim.h
  • LL_TIM_OCMODE_INACTIVE : stm32wbxx_ll_tim.h
  • LL_TIM_OCMODE_PWM1 : stm32wbxx_ll_tim.h
  • LL_TIM_OCMODE_PWM2 : stm32wbxx_ll_tim.h
  • LL_TIM_OCMODE_RETRIG_OPM1 : stm32wbxx_ll_tim.h
  • LL_TIM_OCMODE_RETRIG_OPM2 : stm32wbxx_ll_tim.h
  • LL_TIM_OCMODE_TOGGLE : stm32wbxx_ll_tim.h
  • LL_TIM_OCPOLARITY_HIGH : stm32wbxx_ll_tim.h
  • LL_TIM_OCPOLARITY_LOW : stm32wbxx_ll_tim.h
  • LL_TIM_OCREF_CLR_INT_ETR : stm32wbxx_ll_tim.h
  • LL_TIM_OCREF_CLR_INT_OCREF_CLR : stm32wbxx_ll_tim.h
  • LL_TIM_OCSTATE_DISABLE : stm32wbxx_ll_tim.h
  • LL_TIM_OCSTATE_ENABLE : stm32wbxx_ll_tim.h
  • LL_TIM_ONEPULSEMODE_REPETITIVE : stm32wbxx_ll_tim.h
  • LL_TIM_ONEPULSEMODE_SINGLE : stm32wbxx_ll_tim.h
  • LL_TIM_OSSI_DISABLE : stm32wbxx_ll_tim.h
  • LL_TIM_OSSI_ENABLE : stm32wbxx_ll_tim.h
  • LL_TIM_OSSR_DISABLE : stm32wbxx_ll_tim.h
  • LL_TIM_OSSR_ENABLE : stm32wbxx_ll_tim.h
  • LL_TIM_ReadReg : stm32wbxx_ll_tim.h
  • LL_TIM_SetAutoReload() : stm32wbxx_ll_tim.h
  • LL_TIM_SetBreakInputSourcePolarity() : stm32wbxx_ll_tim.h
  • LL_TIM_SetCH5CombinedChannels() : stm32wbxx_ll_tim.h
  • LL_TIM_SetClockDivision() : stm32wbxx_ll_tim.h
  • LL_TIM_SetClockSource() : stm32wbxx_ll_tim.h
  • LL_TIM_SetCounter() : stm32wbxx_ll_tim.h
  • LL_TIM_SetCounterMode() : stm32wbxx_ll_tim.h
  • LL_TIM_SetEncoderMode() : stm32wbxx_ll_tim.h
  • LL_TIM_SetETRSource() : stm32wbxx_ll_tim.h
  • LL_TIM_SetOCRefClearInputSource() : stm32wbxx_ll_tim.h
  • LL_TIM_SetOffStates() : stm32wbxx_ll_tim.h
  • LL_TIM_SetOnePulseMode() : stm32wbxx_ll_tim.h
  • LL_TIM_SetPrescaler() : stm32wbxx_ll_tim.h
  • LL_TIM_SetRemap() : stm32wbxx_ll_tim.h
  • LL_TIM_SetRepetitionCounter() : stm32wbxx_ll_tim.h
  • LL_TIM_SetSlaveMode() : stm32wbxx_ll_tim.h
  • LL_TIM_SetTriggerInput() : stm32wbxx_ll_tim.h
  • LL_TIM_SetTriggerOutput() : stm32wbxx_ll_tim.h
  • LL_TIM_SetTriggerOutput2() : stm32wbxx_ll_tim.h
  • LL_TIM_SetUpdateSource() : stm32wbxx_ll_tim.h
  • LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER : stm32wbxx_ll_tim.h
  • LL_TIM_SLAVEMODE_DISABLED : stm32wbxx_ll_tim.h
  • LL_TIM_SLAVEMODE_GATED : stm32wbxx_ll_tim.h
  • LL_TIM_SLAVEMODE_RESET : stm32wbxx_ll_tim.h
  • LL_TIM_SLAVEMODE_TRIGGER : stm32wbxx_ll_tim.h
  • LL_TIM_SR_B2IF : stm32wbxx_ll_tim.h
  • LL_TIM_SR_BIF : stm32wbxx_ll_tim.h
  • LL_TIM_SR_CC1IF : stm32wbxx_ll_tim.h
  • LL_TIM_SR_CC1OF : stm32wbxx_ll_tim.h
  • LL_TIM_SR_CC2IF : stm32wbxx_ll_tim.h
  • LL_TIM_SR_CC2OF : stm32wbxx_ll_tim.h
  • LL_TIM_SR_CC3IF : stm32wbxx_ll_tim.h
  • LL_TIM_SR_CC3OF : stm32wbxx_ll_tim.h
  • LL_TIM_SR_CC4IF : stm32wbxx_ll_tim.h
  • LL_TIM_SR_CC4OF : stm32wbxx_ll_tim.h
  • LL_TIM_SR_CC5IF : stm32wbxx_ll_tim.h
  • LL_TIM_SR_CC6IF : stm32wbxx_ll_tim.h
  • LL_TIM_SR_COMIF : stm32wbxx_ll_tim.h
  • LL_TIM_SR_SBIF : stm32wbxx_ll_tim.h
  • LL_TIM_SR_TIF : stm32wbxx_ll_tim.h
  • LL_TIM_SR_UIF : stm32wbxx_ll_tim.h
  • LL_TIM_StructInit() : stm32wbxx_ll_tim.c
  • LL_TIM_TIM16_TI1_RMP_GPIO : stm32wbxx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_LSE : stm32wbxx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_LSI : stm32wbxx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_RTC : stm32wbxx_ll_tim.h
  • LL_TIM_TIM17_TI1_RMP_GPIO : stm32wbxx_ll_tim.h
  • LL_TIM_TIM17_TI1_RMP_HSE_32 : stm32wbxx_ll_tim.h
  • LL_TIM_TIM17_TI1_RMP_MCO : stm32wbxx_ll_tim.h
  • LL_TIM_TIM17_TI1_RMP_MSI : stm32wbxx_ll_tim.h
  • LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 : stm32wbxx_ll_tim.h
  • LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 : stm32wbxx_ll_tim.h
  • LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 : stm32wbxx_ll_tim.h
  • LL_TIM_TIM1_ETR_ADC1_RMP_NC : stm32wbxx_ll_tim.h
  • LL_TIM_TIM1_TI1_RMP_COMP1 : stm32wbxx_ll_tim.h
  • LL_TIM_TIM1_TI1_RMP_GPIO : stm32wbxx_ll_tim.h
  • LL_TIM_TIM2_ETR_RMP_GPIO : stm32wbxx_ll_tim.h
  • LL_TIM_TIM2_ETR_RMP_LSE : stm32wbxx_ll_tim.h
  • LL_TIM_TIM2_ITR1_RMP_NONE : stm32wbxx_ll_tim.h
  • LL_TIM_TIM2_ITR1_RMP_USB_SOF : stm32wbxx_ll_tim.h
  • LL_TIM_TIM2_TI4_RMP_COMP1 : stm32wbxx_ll_tim.h
  • LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 : stm32wbxx_ll_tim.h
  • LL_TIM_TIM2_TI4_RMP_COMP2 : stm32wbxx_ll_tim.h
  • LL_TIM_TIM2_TI4_RMP_GPIO : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO2_CC1F : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO2_ENABLE : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO2_OC1 : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO2_OC2 : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO2_OC3 : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO2_OC4 : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO2_OC4_RISING_OC6_FALLING : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO2_OC4_RISING_OC6_RISING : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO2_OC4_RISINGFALLING : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO2_OC5 : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO2_OC5_RISING_OC6_FALLING : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO2_OC5_RISING_OC6_RISING : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO2_OC6 : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO2_OC6_RISINGFALLING : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO2_RESET : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO2_UPDATE : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO_CC1IF : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO_ENABLE : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO_OC1REF : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO_OC2REF : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO_OC3REF : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO_OC4REF : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO_RESET : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO_UPDATE : stm32wbxx_ll_tim.h
  • LL_TIM_TS_ETRF : stm32wbxx_ll_tim.h
  • LL_TIM_TS_ITR0 : stm32wbxx_ll_tim.h
  • LL_TIM_TS_ITR1 : stm32wbxx_ll_tim.h
  • LL_TIM_TS_ITR2 : stm32wbxx_ll_tim.h
  • LL_TIM_TS_ITR3 : stm32wbxx_ll_tim.h
  • LL_TIM_TS_TI1F_ED : stm32wbxx_ll_tim.h
  • LL_TIM_TS_TI1FP1 : stm32wbxx_ll_tim.h
  • LL_TIM_TS_TI2FP2 : stm32wbxx_ll_tim.h
  • LL_TIM_UPDATESOURCE_COUNTER : stm32wbxx_ll_tim.h
  • LL_TIM_UPDATESOURCE_REGULAR : stm32wbxx_ll_tim.h
  • LL_TIM_WriteReg : stm32wbxx_ll_tim.h
  • LL_USART_ADDRESS_DETECT_4B : stm32wbxx_ll_usart.h
  • LL_USART_ADDRESS_DETECT_7B : stm32wbxx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_55_FRAME : stm32wbxx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME : stm32wbxx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE : stm32wbxx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_STARTBIT : stm32wbxx_ll_usart.h
  • LL_USART_BINARY_LOGIC_NEGATIVE : stm32wbxx_ll_usart.h
  • LL_USART_BINARY_LOGIC_POSITIVE : stm32wbxx_ll_usart.h
  • LL_USART_BITORDER_LSBFIRST : stm32wbxx_ll_usart.h
  • LL_USART_BITORDER_MSBFIRST : stm32wbxx_ll_usart.h
  • LL_USART_ClearFlag_CM() : stm32wbxx_ll_usart.h
  • LL_USART_ClearFlag_EOB() : stm32wbxx_ll_usart.h
  • LL_USART_ClearFlag_FE() : stm32wbxx_ll_usart.h
  • LL_USART_ClearFlag_IDLE() : stm32wbxx_ll_usart.h
  • LL_USART_ClearFlag_LBD() : stm32wbxx_ll_usart.h
  • LL_USART_ClearFlag_nCTS() : stm32wbxx_ll_usart.h
  • LL_USART_ClearFlag_NE() : stm32wbxx_ll_usart.h
  • LL_USART_ClearFlag_ORE() : stm32wbxx_ll_usart.h
  • LL_USART_ClearFlag_PE() : stm32wbxx_ll_usart.h
  • LL_USART_ClearFlag_RTO() : stm32wbxx_ll_usart.h
  • LL_USART_ClearFlag_TC() : stm32wbxx_ll_usart.h
  • LL_USART_ClearFlag_TCBGT() : stm32wbxx_ll_usart.h
  • LL_USART_ClearFlag_TXFE() : stm32wbxx_ll_usart.h
  • LL_USART_ClearFlag_UDR() : stm32wbxx_ll_usart.h
  • LL_USART_ClearFlag_WKUP() : stm32wbxx_ll_usart.h
  • LL_USART_CLOCK_DISABLE : stm32wbxx_ll_usart.h
  • LL_USART_CLOCK_ENABLE : stm32wbxx_ll_usart.h
  • LL_USART_ClockInit() : stm32wbxx_ll_usart.c
  • LL_USART_ClockStructInit() : stm32wbxx_ll_usart.c
  • LL_USART_ConfigAsyncMode() : stm32wbxx_ll_usart.h
  • LL_USART_ConfigCharacter() : stm32wbxx_ll_usart.h
  • LL_USART_ConfigClock() : stm32wbxx_ll_usart.h
  • LL_USART_ConfigFIFOsThreshold() : stm32wbxx_ll_usart.h
  • LL_USART_ConfigHalfDuplexMode() : stm32wbxx_ll_usart.h
  • LL_USART_ConfigIrdaMode() : stm32wbxx_ll_usart.h
  • LL_USART_ConfigLINMode() : stm32wbxx_ll_usart.h
  • LL_USART_ConfigMultiProcessMode() : stm32wbxx_ll_usart.h
  • LL_USART_ConfigNodeAddress() : stm32wbxx_ll_usart.h
  • LL_USART_ConfigSmartcardMode() : stm32wbxx_ll_usart.h
  • LL_USART_ConfigSyncMode() : stm32wbxx_ll_usart.h
  • LL_USART_CR1_CMIE : stm32wbxx_ll_usart.h
  • LL_USART_CR1_EOBIE : stm32wbxx_ll_usart.h
  • LL_USART_CR1_IDLEIE : stm32wbxx_ll_usart.h
  • LL_USART_CR1_PEIE : stm32wbxx_ll_usart.h
  • LL_USART_CR1_RTOIE : stm32wbxx_ll_usart.h
  • LL_USART_CR1_RXFFIE : stm32wbxx_ll_usart.h
  • LL_USART_CR1_RXNEIE_RXFNEIE : stm32wbxx_ll_usart.h
  • LL_USART_CR1_TCIE : stm32wbxx_ll_usart.h
  • LL_USART_CR1_TXEIE_TXFNFIE : stm32wbxx_ll_usart.h
  • LL_USART_CR1_TXFEIE : stm32wbxx_ll_usart.h
  • LL_USART_CR2_LBDIE : stm32wbxx_ll_usart.h
  • LL_USART_CR3_CTSIE : stm32wbxx_ll_usart.h
  • LL_USART_CR3_EIE : stm32wbxx_ll_usart.h
  • LL_USART_CR3_RXFTIE : stm32wbxx_ll_usart.h
  • LL_USART_CR3_TCBGTIE : stm32wbxx_ll_usart.h
  • LL_USART_CR3_TXFTIE : stm32wbxx_ll_usart.h
  • LL_USART_CR3_WUFIE : stm32wbxx_ll_usart.h
  • LL_USART_DATAWIDTH_7B : stm32wbxx_ll_usart.h
  • LL_USART_DATAWIDTH_8B : stm32wbxx_ll_usart.h
  • LL_USART_DATAWIDTH_9B : stm32wbxx_ll_usart.h
  • LL_USART_DE_POLARITY_HIGH : stm32wbxx_ll_usart.h
  • LL_USART_DE_POLARITY_LOW : stm32wbxx_ll_usart.h
  • LL_USART_DeInit() : stm32wbxx_ll_usart.c
  • LL_USART_DIRECTION_NONE : stm32wbxx_ll_usart.h
  • LL_USART_DIRECTION_RX : stm32wbxx_ll_usart.h
  • LL_USART_DIRECTION_TX : stm32wbxx_ll_usart.h
  • LL_USART_DIRECTION_TX_RX : stm32wbxx_ll_usart.h
  • LL_USART_Disable() : stm32wbxx_ll_usart.h
  • LL_USART_DisableAutoBaudRate() : stm32wbxx_ll_usart.h
  • LL_USART_DisableCTSHWFlowCtrl() : stm32wbxx_ll_usart.h
  • LL_USART_DisableDEMode() : stm32wbxx_ll_usart.h
  • LL_USART_DisableDirectionRx() : stm32wbxx_ll_usart.h
  • LL_USART_DisableDirectionTx() : stm32wbxx_ll_usart.h
  • LL_USART_DisableDMADeactOnRxErr() : stm32wbxx_ll_usart.h
  • LL_USART_DisableDMAReq_RX() : stm32wbxx_ll_usart.h
  • LL_USART_DisableDMAReq_TX() : stm32wbxx_ll_usart.h
  • LL_USART_DisableFIFO() : stm32wbxx_ll_usart.h
  • LL_USART_DisableHalfDuplex() : stm32wbxx_ll_usart.h
  • LL_USART_DisableInStopMode() : stm32wbxx_ll_usart.h
  • LL_USART_DisableIrda() : stm32wbxx_ll_usart.h
  • LL_USART_DisableIT_CM() : stm32wbxx_ll_usart.h
  • LL_USART_DisableIT_CTS() : stm32wbxx_ll_usart.h
  • LL_USART_DisableIT_EOB() : stm32wbxx_ll_usart.h
  • LL_USART_DisableIT_ERROR() : stm32wbxx_ll_usart.h
  • LL_USART_DisableIT_IDLE() : stm32wbxx_ll_usart.h
  • LL_USART_DisableIT_LBD() : stm32wbxx_ll_usart.h
  • LL_USART_DisableIT_PE() : stm32wbxx_ll_usart.h
  • LL_USART_DisableIT_RTO() : stm32wbxx_ll_usart.h
  • LL_USART_DisableIT_RXFF() : stm32wbxx_ll_usart.h
  • LL_USART_DisableIT_RXFT() : stm32wbxx_ll_usart.h
  • LL_USART_DisableIT_RXNE : stm32wbxx_ll_usart.h
  • LL_USART_DisableIT_RXNE_RXFNE() : stm32wbxx_ll_usart.h
  • LL_USART_DisableIT_TC() : stm32wbxx_ll_usart.h
  • LL_USART_DisableIT_TCBGT() : stm32wbxx_ll_usart.h
  • LL_USART_DisableIT_TXE : stm32wbxx_ll_usart.h
  • LL_USART_DisableIT_TXE_TXFNF() : stm32wbxx_ll_usart.h
  • LL_USART_DisableIT_TXFE() : stm32wbxx_ll_usart.h
  • LL_USART_DisableIT_TXFT() : stm32wbxx_ll_usart.h
  • LL_USART_DisableIT_WKUP() : stm32wbxx_ll_usart.h
  • LL_USART_DisableLIN() : stm32wbxx_ll_usart.h
  • LL_USART_DisableMuteMode() : stm32wbxx_ll_usart.h
  • LL_USART_DisableOneBitSamp() : stm32wbxx_ll_usart.h
  • LL_USART_DisableOverrunDetect() : stm32wbxx_ll_usart.h
  • LL_USART_DisableRTSHWFlowCtrl() : stm32wbxx_ll_usart.h
  • LL_USART_DisableRxTimeout() : stm32wbxx_ll_usart.h
  • LL_USART_DisableSCLKOutput() : stm32wbxx_ll_usart.h
  • LL_USART_DisableSmartcard() : stm32wbxx_ll_usart.h
  • LL_USART_DisableSmartcardNACK() : stm32wbxx_ll_usart.h
  • LL_USART_DisableSPISlave() : stm32wbxx_ll_usart.h
  • LL_USART_DisableSPISlaveSelect() : stm32wbxx_ll_usart.h
  • LL_USART_DMA_GetRegAddr() : stm32wbxx_ll_usart.h
  • LL_USART_DMA_REG_DATA_RECEIVE : stm32wbxx_ll_usart.h
  • LL_USART_DMA_REG_DATA_TRANSMIT : stm32wbxx_ll_usart.h
  • LL_USART_Enable() : stm32wbxx_ll_usart.h
  • LL_USART_EnableAutoBaudRate() : stm32wbxx_ll_usart.h
  • LL_USART_EnableCTSHWFlowCtrl() : stm32wbxx_ll_usart.h
  • LL_USART_EnableDEMode() : stm32wbxx_ll_usart.h
  • LL_USART_EnableDirectionRx() : stm32wbxx_ll_usart.h
  • LL_USART_EnableDirectionTx() : stm32wbxx_ll_usart.h
  • LL_USART_EnableDMADeactOnRxErr() : stm32wbxx_ll_usart.h
  • LL_USART_EnableDMAReq_RX() : stm32wbxx_ll_usart.h
  • LL_USART_EnableDMAReq_TX() : stm32wbxx_ll_usart.h
  • LL_USART_EnableFIFO() : stm32wbxx_ll_usart.h
  • LL_USART_EnableHalfDuplex() : stm32wbxx_ll_usart.h
  • LL_USART_EnableInStopMode() : stm32wbxx_ll_usart.h
  • LL_USART_EnableIrda() : stm32wbxx_ll_usart.h
  • LL_USART_EnableIT_CM() : stm32wbxx_ll_usart.h
  • LL_USART_EnableIT_CTS() : stm32wbxx_ll_usart.h
  • LL_USART_EnableIT_EOB() : stm32wbxx_ll_usart.h
  • LL_USART_EnableIT_ERROR() : stm32wbxx_ll_usart.h
  • LL_USART_EnableIT_IDLE() : stm32wbxx_ll_usart.h
  • LL_USART_EnableIT_LBD() : stm32wbxx_ll_usart.h
  • LL_USART_EnableIT_PE() : stm32wbxx_ll_usart.h
  • LL_USART_EnableIT_RTO() : stm32wbxx_ll_usart.h
  • LL_USART_EnableIT_RXFF() : stm32wbxx_ll_usart.h
  • LL_USART_EnableIT_RXFT() : stm32wbxx_ll_usart.h
  • LL_USART_EnableIT_RXNE : stm32wbxx_ll_usart.h
  • LL_USART_EnableIT_RXNE_RXFNE() : stm32wbxx_ll_usart.h
  • LL_USART_EnableIT_TC() : stm32wbxx_ll_usart.h
  • LL_USART_EnableIT_TCBGT() : stm32wbxx_ll_usart.h
  • LL_USART_EnableIT_TXE : stm32wbxx_ll_usart.h
  • LL_USART_EnableIT_TXE_TXFNF() : stm32wbxx_ll_usart.h
  • LL_USART_EnableIT_TXFE() : stm32wbxx_ll_usart.h
  • LL_USART_EnableIT_TXFT() : stm32wbxx_ll_usart.h
  • LL_USART_EnableIT_WKUP() : stm32wbxx_ll_usart.h
  • LL_USART_EnableLIN() : stm32wbxx_ll_usart.h
  • LL_USART_EnableMuteMode() : stm32wbxx_ll_usart.h
  • LL_USART_EnableOneBitSamp() : stm32wbxx_ll_usart.h
  • LL_USART_EnableOverrunDetect() : stm32wbxx_ll_usart.h
  • LL_USART_EnableRTSHWFlowCtrl() : stm32wbxx_ll_usart.h
  • LL_USART_EnableRxTimeout() : stm32wbxx_ll_usart.h
  • LL_USART_EnableSCLKOutput() : stm32wbxx_ll_usart.h
  • LL_USART_EnableSmartcard() : stm32wbxx_ll_usart.h
  • LL_USART_EnableSmartcardNACK() : stm32wbxx_ll_usart.h
  • LL_USART_EnableSPISlave() : stm32wbxx_ll_usart.h
  • LL_USART_EnableSPISlaveSelect() : stm32wbxx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_1_2 : stm32wbxx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_1_4 : stm32wbxx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_1_8 : stm32wbxx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_3_4 : stm32wbxx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_7_8 : stm32wbxx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_8_8 : stm32wbxx_ll_usart.h
  • LL_USART_GetAutoBaudRateMode() : stm32wbxx_ll_usart.h
  • LL_USART_GetBaudRate() : stm32wbxx_ll_usart.h
  • LL_USART_GetBinaryDataLogic() : stm32wbxx_ll_usart.h
  • LL_USART_GetBlockLength() : stm32wbxx_ll_usart.h
  • LL_USART_GetClockPhase() : stm32wbxx_ll_usart.h
  • LL_USART_GetClockPolarity() : stm32wbxx_ll_usart.h
  • LL_USART_GetDataWidth() : stm32wbxx_ll_usart.h
  • LL_USART_GetDEAssertionTime() : stm32wbxx_ll_usart.h
  • LL_USART_GetDEDeassertionTime() : stm32wbxx_ll_usart.h
  • LL_USART_GetDESignalPolarity() : stm32wbxx_ll_usart.h
  • LL_USART_GetHWFlowCtrl() : stm32wbxx_ll_usart.h
  • LL_USART_GetIrdaPowerMode() : stm32wbxx_ll_usart.h
  • LL_USART_GetIrdaPrescaler() : stm32wbxx_ll_usart.h
  • LL_USART_GetLastClkPulseOutput() : stm32wbxx_ll_usart.h
  • LL_USART_GetLINBrkDetectionLen() : stm32wbxx_ll_usart.h
  • LL_USART_GetNodeAddress() : stm32wbxx_ll_usart.h
  • LL_USART_GetNodeAddressLen() : stm32wbxx_ll_usart.h
  • LL_USART_GetOverSampling() : stm32wbxx_ll_usart.h
  • LL_USART_GetParity() : stm32wbxx_ll_usart.h
  • LL_USART_GetPrescaler() : stm32wbxx_ll_usart.h
  • LL_USART_GetRXFIFOThreshold() : stm32wbxx_ll_usart.h
  • LL_USART_GetRXPinLevel() : stm32wbxx_ll_usart.h
  • LL_USART_GetRxTimeout() : stm32wbxx_ll_usart.h
  • LL_USART_GetSmartcardAutoRetryCount() : stm32wbxx_ll_usart.h
  • LL_USART_GetSmartcardGuardTime() : stm32wbxx_ll_usart.h
  • LL_USART_GetSmartcardPrescaler() : stm32wbxx_ll_usart.h
  • LL_USART_GetStopBitsLength() : stm32wbxx_ll_usart.h
  • LL_USART_GetTransferBitOrder() : stm32wbxx_ll_usart.h
  • LL_USART_GetTransferDirection() : stm32wbxx_ll_usart.h
  • LL_USART_GetTXFIFOThreshold() : stm32wbxx_ll_usart.h
  • LL_USART_GetTXPinLevel() : stm32wbxx_ll_usart.h
  • LL_USART_GetTXRXSwap() : stm32wbxx_ll_usart.h
  • LL_USART_GetWakeUpMethod() : stm32wbxx_ll_usart.h
  • LL_USART_GetWKUPType() : stm32wbxx_ll_usart.h
  • LL_USART_HWCONTROL_CTS : stm32wbxx_ll_usart.h
  • LL_USART_HWCONTROL_NONE : stm32wbxx_ll_usart.h
  • LL_USART_HWCONTROL_RTS : stm32wbxx_ll_usart.h
  • LL_USART_HWCONTROL_RTS_CTS : stm32wbxx_ll_usart.h
  • LL_USART_ICR_CMCF : stm32wbxx_ll_usart.h
  • LL_USART_ICR_CTSCF : stm32wbxx_ll_usart.h
  • LL_USART_ICR_EOBCF : stm32wbxx_ll_usart.h
  • LL_USART_ICR_FECF : stm32wbxx_ll_usart.h
  • LL_USART_ICR_IDLECF : stm32wbxx_ll_usart.h
  • LL_USART_ICR_LBDCF : stm32wbxx_ll_usart.h
  • LL_USART_ICR_NECF : stm32wbxx_ll_usart.h
  • LL_USART_ICR_ORECF : stm32wbxx_ll_usart.h
  • LL_USART_ICR_PECF : stm32wbxx_ll_usart.h
  • LL_USART_ICR_RTOCF : stm32wbxx_ll_usart.h
  • LL_USART_ICR_TCBGTCF : stm32wbxx_ll_usart.h
  • LL_USART_ICR_TCCF : stm32wbxx_ll_usart.h
  • LL_USART_ICR_TXFECF : stm32wbxx_ll_usart.h
  • LL_USART_ICR_UDRCF : stm32wbxx_ll_usart.h
  • LL_USART_ICR_WUCF : stm32wbxx_ll_usart.h
  • LL_USART_Init() : stm32wbxx_ll_usart.c
  • LL_USART_IRDA_POWER_LOW : stm32wbxx_ll_usart.h
  • LL_USART_IRDA_POWER_NORMAL : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_ABR() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_ABRE() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_BUSY() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_CM() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_CTS() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_EOB() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_FE() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_IDLE() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_LBD() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_nCTS() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_NE() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_ORE() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_PE() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_REACK() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_RTO() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_RWU() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_RXFF() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_RXFT() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_RXNE : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_RXNE_RXFNE() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_SBK() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_TC() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_TCBGT() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_TEACK() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_TXE : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_TXE_TXFNF() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_TXFE() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_TXFT() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_UDR() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_WKUP() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabled() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledAutoBaud() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledDEMode() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledDMADeactOnRxErr() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledDMAReq_RX() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledDMAReq_TX() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledFIFO() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledHalfDuplex() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledInStopMode() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIrda() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIT_CM() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIT_CTS() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIT_EOB() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIT_ERROR() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIT_IDLE() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIT_LBD() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIT_PE() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIT_RTO() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIT_RXFF() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIT_RXFT() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIT_RXNE : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIT_RXNE_RXFNE() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIT_TC() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIT_TCBGT() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIT_TXE : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIT_TXE_TXFNF() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIT_TXFE() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIT_TXFT() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIT_WKUP() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledLIN() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledMuteMode() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledOneBitSamp() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledOverrunDetect() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledRxTimeout() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledSCLKOutput() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledSmartcard() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledSmartcardNACK() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledSPISlave() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledSPISlaveSelect() : stm32wbxx_ll_usart.h
  • LL_USART_ISR_ABRE : stm32wbxx_ll_usart.h
  • LL_USART_ISR_ABRF : stm32wbxx_ll_usart.h
  • LL_USART_ISR_BUSY : stm32wbxx_ll_usart.h
  • LL_USART_ISR_CMF : stm32wbxx_ll_usart.h
  • LL_USART_ISR_CTS : stm32wbxx_ll_usart.h
  • LL_USART_ISR_CTSIF : stm32wbxx_ll_usart.h
  • LL_USART_ISR_EOBF : stm32wbxx_ll_usart.h
  • LL_USART_ISR_FE : stm32wbxx_ll_usart.h
  • LL_USART_ISR_IDLE : stm32wbxx_ll_usart.h
  • LL_USART_ISR_LBDF : stm32wbxx_ll_usart.h
  • LL_USART_ISR_NE : stm32wbxx_ll_usart.h
  • LL_USART_ISR_ORE : stm32wbxx_ll_usart.h
  • LL_USART_ISR_PE : stm32wbxx_ll_usart.h
  • LL_USART_ISR_REACK : stm32wbxx_ll_usart.h
  • LL_USART_ISR_RTOF : stm32wbxx_ll_usart.h
  • LL_USART_ISR_RWU : stm32wbxx_ll_usart.h
  • LL_USART_ISR_RXFF : stm32wbxx_ll_usart.h
  • LL_USART_ISR_RXFT : stm32wbxx_ll_usart.h
  • LL_USART_ISR_RXNE_RXFNE : stm32wbxx_ll_usart.h
  • LL_USART_ISR_SBKF : stm32wbxx_ll_usart.h
  • LL_USART_ISR_TC : stm32wbxx_ll_usart.h
  • LL_USART_ISR_TCBGT : stm32wbxx_ll_usart.h
  • LL_USART_ISR_TEACK : stm32wbxx_ll_usart.h
  • LL_USART_ISR_TXE_TXFNF : stm32wbxx_ll_usart.h
  • LL_USART_ISR_TXFE : stm32wbxx_ll_usart.h
  • LL_USART_ISR_TXFT : stm32wbxx_ll_usart.h
  • LL_USART_ISR_UDR : stm32wbxx_ll_usart.h
  • LL_USART_ISR_WUF : stm32wbxx_ll_usart.h
  • LL_USART_LASTCLKPULSE_NO_OUTPUT : stm32wbxx_ll_usart.h
  • LL_USART_LASTCLKPULSE_OUTPUT : stm32wbxx_ll_usart.h
  • LL_USART_LINBREAK_DETECT_10B : stm32wbxx_ll_usart.h
  • LL_USART_LINBREAK_DETECT_11B : stm32wbxx_ll_usart.h
  • LL_USART_OVERSAMPLING_16 : stm32wbxx_ll_usart.h
  • LL_USART_OVERSAMPLING_8 : stm32wbxx_ll_usart.h
  • LL_USART_PARITY_EVEN : stm32wbxx_ll_usart.h
  • LL_USART_PARITY_NONE : stm32wbxx_ll_usart.h
  • LL_USART_PARITY_ODD : stm32wbxx_ll_usart.h
  • LL_USART_PHASE_1EDGE : stm32wbxx_ll_usart.h
  • LL_USART_PHASE_2EDGE : stm32wbxx_ll_usart.h
  • LL_USART_POLARITY_HIGH : stm32wbxx_ll_usart.h
  • LL_USART_POLARITY_LOW : stm32wbxx_ll_usart.h
  • LL_USART_PRESCALER_DIV1 : stm32wbxx_ll_usart.h
  • LL_USART_PRESCALER_DIV10 : stm32wbxx_ll_usart.h
  • LL_USART_PRESCALER_DIV12 : stm32wbxx_ll_usart.h
  • LL_USART_PRESCALER_DIV128 : stm32wbxx_ll_usart.h
  • LL_USART_PRESCALER_DIV16 : stm32wbxx_ll_usart.h
  • LL_USART_PRESCALER_DIV2 : stm32wbxx_ll_usart.h
  • LL_USART_PRESCALER_DIV256 : stm32wbxx_ll_usart.h
  • LL_USART_PRESCALER_DIV32 : stm32wbxx_ll_usart.h
  • LL_USART_PRESCALER_DIV4 : stm32wbxx_ll_usart.h
  • LL_USART_PRESCALER_DIV6 : stm32wbxx_ll_usart.h
  • LL_USART_PRESCALER_DIV64 : stm32wbxx_ll_usart.h
  • LL_USART_PRESCALER_DIV8 : stm32wbxx_ll_usart.h
  • LL_USART_ReadReg : stm32wbxx_ll_usart.h
  • LL_USART_ReceiveData8() : stm32wbxx_ll_usart.h
  • LL_USART_ReceiveData9() : stm32wbxx_ll_usart.h
  • LL_USART_RequestAutoBaudRate() : stm32wbxx_ll_usart.h
  • LL_USART_RequestBreakSending() : stm32wbxx_ll_usart.h
  • LL_USART_RequestEnterMuteMode() : stm32wbxx_ll_usart.h
  • LL_USART_RequestRxDataFlush() : stm32wbxx_ll_usart.h
  • LL_USART_RequestTxDataFlush() : stm32wbxx_ll_usart.h
  • LL_USART_RXPIN_LEVEL_INVERTED : stm32wbxx_ll_usart.h
  • LL_USART_RXPIN_LEVEL_STANDARD : stm32wbxx_ll_usart.h
  • LL_USART_SetAutoBaudRateMode() : stm32wbxx_ll_usart.h
  • LL_USART_SetBaudRate() : stm32wbxx_ll_usart.h
  • LL_USART_SetBinaryDataLogic() : stm32wbxx_ll_usart.h
  • LL_USART_SetBlockLength() : stm32wbxx_ll_usart.h
  • LL_USART_SetClockPhase() : stm32wbxx_ll_usart.h
  • LL_USART_SetClockPolarity() : stm32wbxx_ll_usart.h
  • LL_USART_SetDataWidth() : stm32wbxx_ll_usart.h
  • LL_USART_SetDEAssertionTime() : stm32wbxx_ll_usart.h
  • LL_USART_SetDEDeassertionTime() : stm32wbxx_ll_usart.h
  • LL_USART_SetDESignalPolarity() : stm32wbxx_ll_usart.h
  • LL_USART_SetHWFlowCtrl() : stm32wbxx_ll_usart.h
  • LL_USART_SetIrdaPowerMode() : stm32wbxx_ll_usart.h
  • LL_USART_SetIrdaPrescaler() : stm32wbxx_ll_usart.h
  • LL_USART_SetLastClkPulseOutput() : stm32wbxx_ll_usart.h
  • LL_USART_SetLINBrkDetectionLen() : stm32wbxx_ll_usart.h
  • LL_USART_SetOverSampling() : stm32wbxx_ll_usart.h
  • LL_USART_SetParity() : stm32wbxx_ll_usart.h
  • LL_USART_SetPrescaler() : stm32wbxx_ll_usart.h
  • LL_USART_SetRXFIFOThreshold() : stm32wbxx_ll_usart.h
  • LL_USART_SetRXPinLevel() : stm32wbxx_ll_usart.h
  • LL_USART_SetRxTimeout() : stm32wbxx_ll_usart.h
  • LL_USART_SetSmartcardAutoRetryCount() : stm32wbxx_ll_usart.h
  • LL_USART_SetSmartcardGuardTime() : stm32wbxx_ll_usart.h
  • LL_USART_SetSmartcardPrescaler() : stm32wbxx_ll_usart.h
  • LL_USART_SetStopBitsLength() : stm32wbxx_ll_usart.h
  • LL_USART_SetTransferBitOrder() : stm32wbxx_ll_usart.h
  • LL_USART_SetTransferDirection() : stm32wbxx_ll_usart.h
  • LL_USART_SetTXFIFOThreshold() : stm32wbxx_ll_usart.h
  • LL_USART_SetTXPinLevel() : stm32wbxx_ll_usart.h
  • LL_USART_SetTXRXSwap() : stm32wbxx_ll_usart.h
  • LL_USART_SetWakeUpMethod() : stm32wbxx_ll_usart.h
  • LL_USART_SetWKUPType() : stm32wbxx_ll_usart.h
  • LL_USART_STOPBITS_0_5 : stm32wbxx_ll_usart.h
  • LL_USART_STOPBITS_1 : stm32wbxx_ll_usart.h
  • LL_USART_STOPBITS_1_5 : stm32wbxx_ll_usart.h
  • LL_USART_STOPBITS_2 : stm32wbxx_ll_usart.h
  • LL_USART_StructInit() : stm32wbxx_ll_usart.c
  • LL_USART_TransmitData8() : stm32wbxx_ll_usart.h
  • LL_USART_TransmitData9() : stm32wbxx_ll_usart.h
  • LL_USART_TXPIN_LEVEL_INVERTED : stm32wbxx_ll_usart.h
  • LL_USART_TXPIN_LEVEL_STANDARD : stm32wbxx_ll_usart.h
  • LL_USART_TXRX_STANDARD : stm32wbxx_ll_usart.h
  • LL_USART_TXRX_SWAPPED : stm32wbxx_ll_usart.h
  • LL_USART_WAKEUP_ADDRESSMARK : stm32wbxx_ll_usart.h
  • LL_USART_WAKEUP_IDLELINE : stm32wbxx_ll_usart.h
  • LL_USART_WAKEUP_ON_ADDRESS : stm32wbxx_ll_usart.h
  • LL_USART_WAKEUP_ON_RXNE : stm32wbxx_ll_usart.h
  • LL_USART_WAKEUP_ON_STARTBIT : stm32wbxx_ll_usart.h
  • LL_USART_WriteReg : stm32wbxx_ll_usart.h
  • LL_UTILS_HSEBYPASS_OFF : stm32wbxx_ll_utils.h
  • LL_UTILS_HSEBYPASS_ON : stm32wbxx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_CSP100 : stm32wbxx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_CSP100_C : stm32wbxx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_QFN48 : stm32wbxx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_QFN48_C : stm32wbxx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_QFN68 : stm32wbxx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_QFN68_C : stm32wbxx_ll_utils.h
  • LL_VREFBUF_Disable() : stm32wbxx_ll_system.h
  • LL_VREFBUF_DisableHIZ() : stm32wbxx_ll_system.h
  • LL_VREFBUF_Enable() : stm32wbxx_ll_system.h
  • LL_VREFBUF_EnableHIZ() : stm32wbxx_ll_system.h
  • LL_VREFBUF_GetTrimming() : stm32wbxx_ll_system.h
  • LL_VREFBUF_GetVoltageScaling() : stm32wbxx_ll_system.h
  • LL_VREFBUF_IsVREFReady() : stm32wbxx_ll_system.h
  • LL_VREFBUF_SetTrimming() : stm32wbxx_ll_system.h
  • LL_VREFBUF_SetVoltageScaling() : stm32wbxx_ll_system.h
  • LL_VREFBUF_VOLTAGE_SCALE0 : stm32wbxx_ll_system.h
  • LL_VREFBUF_VOLTAGE_SCALE1 : stm32wbxx_ll_system.h
  • LL_WWDG_CFR_EWI : stm32wbxx_ll_wwdg.h
  • LL_WWDG_ClearFlag_EWKUP() : stm32wbxx_ll_wwdg.h
  • LL_WWDG_Enable() : stm32wbxx_ll_wwdg.h
  • LL_WWDG_EnableIT_EWKUP() : stm32wbxx_ll_wwdg.h
  • LL_WWDG_GetCounter() : stm32wbxx_ll_wwdg.h
  • LL_WWDG_GetPrescaler() : stm32wbxx_ll_wwdg.h
  • LL_WWDG_GetWindow() : stm32wbxx_ll_wwdg.h
  • LL_WWDG_IsActiveFlag_EWKUP() : stm32wbxx_ll_wwdg.h
  • LL_WWDG_IsEnabled() : stm32wbxx_ll_wwdg.h
  • LL_WWDG_IsEnabledIT_EWKUP() : stm32wbxx_ll_wwdg.h
  • LL_WWDG_PRESCALER_1 : stm32wbxx_ll_wwdg.h
  • LL_WWDG_PRESCALER_128 : stm32wbxx_ll_wwdg.h
  • LL_WWDG_PRESCALER_16 : stm32wbxx_ll_wwdg.h
  • LL_WWDG_PRESCALER_2 : stm32wbxx_ll_wwdg.h
  • LL_WWDG_PRESCALER_32 : stm32wbxx_ll_wwdg.h
  • LL_WWDG_PRESCALER_4 : stm32wbxx_ll_wwdg.h
  • LL_WWDG_PRESCALER_64 : stm32wbxx_ll_wwdg.h
  • LL_WWDG_PRESCALER_8 : stm32wbxx_ll_wwdg.h
  • LL_WWDG_ReadReg : stm32wbxx_ll_wwdg.h
  • LL_WWDG_SetCounter() : stm32wbxx_ll_wwdg.h
  • LL_WWDG_SetPrescaler() : stm32wbxx_ll_wwdg.h
  • LL_WWDG_SetWindow() : stm32wbxx_ll_wwdg.h
  • LL_WWDG_WriteReg : stm32wbxx_ll_wwdg.h
  • LPM_L0 : stm32wbxx_hal_pcd.h
  • LPM_L1 : stm32wbxx_hal_pcd.h
  • LPM_L2 : stm32wbxx_hal_pcd.h
  • LPM_L3 : stm32wbxx_hal_pcd.h
  • LPTIM_ACTIVEEDGE_FALLING : stm32wbxx_hal_lptim.h
  • LPTIM_ACTIVEEDGE_RISING : stm32wbxx_hal_lptim.h
  • LPTIM_ACTIVEEDGE_RISING_FALLING : stm32wbxx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_FALLING : stm32wbxx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_RISING : stm32wbxx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_RISING_FALLING : stm32wbxx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_2TRANSITIONS : stm32wbxx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_4TRANSITIONS : stm32wbxx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_8TRANSITIONS : stm32wbxx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION : stm32wbxx_hal_lptim.h
  • LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC : stm32wbxx_hal_lptim.h
  • LPTIM_CLOCKSOURCE_ULPTIM : stm32wbxx_hal_lptim.h
  • LPTIM_COUNTERSOURCE_EXTERNAL : stm32wbxx_hal_lptim.h
  • LPTIM_COUNTERSOURCE_INTERNAL : stm32wbxx_hal_lptim.h
  • LPTIM_Disable() : stm32wbxx_hal_lptim.c
  • LPTIM_EXTI_LINE_LPTIM1 : stm32wbxx_hal_lptim.h
  • LPTIM_EXTI_LINE_LPTIM2 : stm32wbxx_hal_lptim.h
  • LPTIM_FLAG_ARRM : stm32wbxx_hal_lptim.h
  • LPTIM_FLAG_ARROK : stm32wbxx_hal_lptim.h
  • LPTIM_FLAG_CMPM : stm32wbxx_hal_lptim.h
  • LPTIM_FLAG_CMPOK : stm32wbxx_hal_lptim.h
  • LPTIM_FLAG_DOWN : stm32wbxx_hal_lptim.h
  • LPTIM_FLAG_EXTTRIG : stm32wbxx_hal_lptim.h
  • LPTIM_FLAG_UP : stm32wbxx_hal_lptim.h
  • LPTIM_HandleTypeDef : stm32wbxx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_COMP1 : stm32wbxx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_COMP1_COMP2 : stm32wbxx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_COMP2 : stm32wbxx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_GPIO : stm32wbxx_hal_lptim.h
  • LPTIM_INPUT2SOURCE_COMP2 : stm32wbxx_hal_lptim.h
  • LPTIM_INPUT2SOURCE_GPIO : stm32wbxx_hal_lptim.h
  • LPTIM_IT_ARRM : stm32wbxx_hal_lptim.h
  • LPTIM_IT_ARROK : stm32wbxx_hal_lptim.h
  • LPTIM_IT_CMPM : stm32wbxx_hal_lptim.h
  • LPTIM_IT_CMPOK : stm32wbxx_hal_lptim.h
  • LPTIM_IT_DOWN : stm32wbxx_hal_lptim.h
  • LPTIM_IT_EXTTRIG : stm32wbxx_hal_lptim.h
  • LPTIM_IT_UP : stm32wbxx_hal_lptim.h
  • LPTIM_OUTPUTPOLARITY_HIGH : stm32wbxx_hal_lptim.h
  • LPTIM_OUTPUTPOLARITY_LOW : stm32wbxx_hal_lptim.h
  • LPTIM_PRESCALER_DIV1 : stm32wbxx_hal_lptim.h
  • LPTIM_PRESCALER_DIV128 : stm32wbxx_hal_lptim.h
  • LPTIM_PRESCALER_DIV16 : stm32wbxx_hal_lptim.h
  • LPTIM_PRESCALER_DIV2 : stm32wbxx_hal_lptim.h
  • LPTIM_PRESCALER_DIV32 : stm32wbxx_hal_lptim.h
  • LPTIM_PRESCALER_DIV4 : stm32wbxx_hal_lptim.h
  • LPTIM_PRESCALER_DIV64 : stm32wbxx_hal_lptim.h
  • LPTIM_PRESCALER_DIV8 : stm32wbxx_hal_lptim.h
  • LPTIM_ResetCallback() : stm32wbxx_hal_lptim.c
  • LPTIM_TRIGSAMPLETIME_2TRANSITIONS : stm32wbxx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_4TRANSITIONS : stm32wbxx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_8TRANSITIONS : stm32wbxx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION : stm32wbxx_hal_lptim.h
  • LPTIM_TRIGSOURCE_0 : stm32wbxx_hal_lptim.h
  • LPTIM_TRIGSOURCE_1 : stm32wbxx_hal_lptim.h
  • LPTIM_TRIGSOURCE_2 : stm32wbxx_hal_lptim.h
  • LPTIM_TRIGSOURCE_3 : stm32wbxx_hal_lptim.h
  • LPTIM_TRIGSOURCE_4 : stm32wbxx_hal_lptim.h
  • LPTIM_TRIGSOURCE_5 : stm32wbxx_hal_lptim.h
  • LPTIM_TRIGSOURCE_6 : stm32wbxx_hal_lptim.h
  • LPTIM_TRIGSOURCE_7 : stm32wbxx_hal_lptim.h
  • LPTIM_TRIGSOURCE_SOFTWARE : stm32wbxx_hal_lptim.h
  • LPTIM_UPDATE_ENDOFPERIOD : stm32wbxx_hal_lptim.h
  • LPTIM_UPDATE_IMMEDIATE : stm32wbxx_hal_lptim.h
  • LPTIM_WaitForFlag() : stm32wbxx_hal_lptim.c
  • LPUART_BRR_MASK : stm32wbxx_ll_lpuart.h
  • LPUART_BRR_MAX : stm32wbxx_hal_uart.c
  • LPUART_BRR_MIN : stm32wbxx_hal_uart.c
  • LPUART_BRR_MIN_VALUE : stm32wbxx_ll_lpuart.h
  • LPUART_LPUARTDIV_FREQ_MUL : stm32wbxx_ll_lpuart.h
  • LPUART_PRESCALER_TAB : stm32wbxx_ll_lpuart.h
  • LSCO1_GPIO_PORT : stm32wbxx_hal_rcc_ex.c
  • LSCO1_PIN : stm32wbxx_hal_rcc_ex.c
  • LSCO2_GPIO_PORT : stm32wbxx_hal_rcc_ex.c
  • LSCO2_PIN : stm32wbxx_hal_rcc_ex.c
  • LSCO3_GPIO_PORT : stm32wbxx_hal_rcc_ex.c
  • LSCO3_PIN : stm32wbxx_hal_rcc_ex.c
  • LSE_STARTUP_TIMEOUT : stm32wbxx_hal_conf.h
  • LSE_VALUE : stm32wbxx_hal_conf.h
  • LSI1_TIMEOUT_VALUE : stm32wbxx_hal_rcc.c
  • LSI1_VALUE : stm32wbxx_hal_conf.h
  • LSI2_TIMEOUT_VALUE : stm32wbxx_hal_rcc.c , stm32wbxx_hal_rcc_ex.c
  • LSI2_VALUE : stm32wbxx_hal_conf.h
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
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  • r
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- m -

  • MAX_NBYTE_SIZE : stm32wbxx_hal_i2c.c , stm32wbxx_hal_smbus.c
  • MCO1_GPIO_PORT : stm32wbxx_hal_rcc.c
  • MCO1_PIN : stm32wbxx_hal_rcc.c
  • MCO2_GPIO_PORT : stm32wbxx_hal_rcc.c
  • MCO2_PIN : stm32wbxx_hal_rcc.c
  • MCO3_GPIO_PORT : stm32wbxx_hal_rcc.c
  • MCO3_PIN : stm32wbxx_hal_rcc.c
  • MEGA_HZ : stm32wbxx_hal_rcc.c
  • MPU_ACCESS_BUFFERABLE : stm32wbxx_hal_cortex.h
  • MPU_ACCESS_CACHEABLE : stm32wbxx_hal_cortex.h
  • MPU_ACCESS_NOT_BUFFERABLE : stm32wbxx_hal_cortex.h
  • MPU_ACCESS_NOT_CACHEABLE : stm32wbxx_hal_cortex.h
  • MPU_ACCESS_NOT_SHAREABLE : stm32wbxx_hal_cortex.h
  • MPU_ACCESS_SHAREABLE : stm32wbxx_hal_cortex.h
  • MPU_HARDFAULT_NMI : stm32wbxx_hal_cortex.h
  • MPU_HFNMI_PRIVDEF : stm32wbxx_hal_cortex.h
  • MPU_HFNMI_PRIVDEF_NONE : stm32wbxx_hal_cortex.h
  • MPU_INSTRUCTION_ACCESS_DISABLE : stm32wbxx_hal_cortex.h
  • MPU_INSTRUCTION_ACCESS_ENABLE : stm32wbxx_hal_cortex.h
  • MPU_PRIVILEGED_DEFAULT : stm32wbxx_hal_cortex.h
  • MPU_REGION_DISABLE : stm32wbxx_hal_cortex.h
  • MPU_REGION_ENABLE : stm32wbxx_hal_cortex.h
  • MPU_REGION_FULL_ACCESS : stm32wbxx_hal_cortex.h
  • MPU_REGION_NO_ACCESS : stm32wbxx_hal_cortex.h
  • MPU_REGION_NUMBER0 : stm32wbxx_hal_cortex.h
  • MPU_REGION_NUMBER1 : stm32wbxx_hal_cortex.h
  • MPU_REGION_NUMBER2 : stm32wbxx_hal_cortex.h
  • MPU_REGION_NUMBER3 : stm32wbxx_hal_cortex.h
  • MPU_REGION_NUMBER4 : stm32wbxx_hal_cortex.h
  • MPU_REGION_NUMBER5 : stm32wbxx_hal_cortex.h
  • MPU_REGION_NUMBER6 : stm32wbxx_hal_cortex.h
  • MPU_REGION_NUMBER7 : stm32wbxx_hal_cortex.h
  • MPU_REGION_PRIV_RO : stm32wbxx_hal_cortex.h
  • MPU_REGION_PRIV_RO_URO : stm32wbxx_hal_cortex.h
  • MPU_REGION_PRIV_RW : stm32wbxx_hal_cortex.h
  • MPU_REGION_PRIV_RW_URO : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_128B : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_128KB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_128MB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_16KB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_16MB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_1GB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_1KB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_1MB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_256B : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_256KB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_256MB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_2GB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_2KB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_2MB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_32B : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_32KB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_32MB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_4GB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_4KB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_4MB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_512B : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_512KB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_512MB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_64B : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_64KB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_64MB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_8KB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_8MB : stm32wbxx_hal_cortex.h
  • MPU_TEX_LEVEL0 : stm32wbxx_hal_cortex.h
  • MPU_TEX_LEVEL1 : stm32wbxx_hal_cortex.h
  • MPU_TEX_LEVEL2 : stm32wbxx_hal_cortex.h
  • MSI_TIMEOUT_VALUE : stm32wbxx_hal_rcc.c
  • MSI_VALUE : stm32wbxx_hal_conf.h
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
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  • Defines
  • _
  • a
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- n -

  • NVIC_PRIORITYGROUP_0 : stm32wbxx_hal_cortex.h
  • NVIC_PRIORITYGROUP_1 : stm32wbxx_hal_cortex.h
  • NVIC_PRIORITYGROUP_2 : stm32wbxx_hal_cortex.h
  • NVIC_PRIORITYGROUP_3 : stm32wbxx_hal_cortex.h
  • NVIC_PRIORITYGROUP_4 : stm32wbxx_hal_cortex.h
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
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  • e
  • f
  • g
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- o -

  • OB_AGC_TRIM_0 : stm32wbxx_hal_flash.h
  • OB_AGC_TRIM_1 : stm32wbxx_hal_flash.h
  • OB_AGC_TRIM_2 : stm32wbxx_hal_flash.h
  • OB_AGC_TRIM_3 : stm32wbxx_hal_flash.h
  • OB_AGC_TRIM_4 : stm32wbxx_hal_flash.h
  • OB_AGC_TRIM_5 : stm32wbxx_hal_flash.h
  • OB_AGC_TRIM_6 : stm32wbxx_hal_flash.h
  • OB_AGC_TRIM_7 : stm32wbxx_hal_flash.h
  • OB_BOOT0_FROM_OB : stm32wbxx_hal_flash.h
  • OB_BOOT0_FROM_PIN : stm32wbxx_hal_flash.h
  • OB_BOOT0_RESET : stm32wbxx_hal_flash.h
  • OB_BOOT0_SET : stm32wbxx_hal_flash.h
  • OB_BOOT1_SRAM : stm32wbxx_hal_flash.h
  • OB_BOOT1_SYSTEM : stm32wbxx_hal_flash.h
  • OB_BOR_LEVEL_0 : stm32wbxx_hal_flash.h
  • OB_BOR_LEVEL_1 : stm32wbxx_hal_flash.h
  • OB_BOR_LEVEL_2 : stm32wbxx_hal_flash.h
  • OB_BOR_LEVEL_3 : stm32wbxx_hal_flash.h
  • OB_BOR_LEVEL_4 : stm32wbxx_hal_flash.h
  • OB_C2_BOOT_FROM_FLASH : stm32wbxx_hal_flash.h
  • OB_C2_BOOT_FROM_SRAM : stm32wbxx_hal_flash.h
  • OB_IWDG_HW : stm32wbxx_hal_flash.h
  • OB_IWDG_STDBY_FREEZE : stm32wbxx_hal_flash.h
  • OB_IWDG_STDBY_RUN : stm32wbxx_hal_flash.h
  • OB_IWDG_STOP_FREEZE : stm32wbxx_hal_flash.h
  • OB_IWDG_STOP_RUN : stm32wbxx_hal_flash.h
  • OB_IWDG_SW : stm32wbxx_hal_flash.h
  • OB_PCROP_RDP_ERASE : stm32wbxx_hal_flash.h
  • OB_PCROP_RDP_NOT_ERASE : stm32wbxx_hal_flash.h
  • OB_PCROP_ZONE_A : stm32wbxx_hal_flash.h
  • OB_PCROP_ZONE_B : stm32wbxx_hal_flash.h
  • OB_RDP_LEVEL_0 : stm32wbxx_hal_flash.h
  • OB_RDP_LEVEL_1 : stm32wbxx_hal_flash.h
  • OB_RDP_LEVEL_2 : stm32wbxx_hal_flash.h
  • OB_SHUTDOWN_NORST : stm32wbxx_hal_flash.h
  • OB_SHUTDOWN_RST : stm32wbxx_hal_flash.h
  • OB_SRAM2_PARITY_DISABLE : stm32wbxx_hal_flash.h
  • OB_SRAM2_PARITY_ENABLE : stm32wbxx_hal_flash.h
  • OB_SRAM2_RST_ERASE : stm32wbxx_hal_flash.h
  • OB_SRAM2_RST_NOT_ERASE : stm32wbxx_hal_flash.h
  • OB_STANDBY_NORST : stm32wbxx_hal_flash.h
  • OB_STANDBY_RST : stm32wbxx_hal_flash.h
  • OB_STOP_NORST : stm32wbxx_hal_flash.h
  • OB_STOP_RST : stm32wbxx_hal_flash.h
  • OB_USER_AGC_TRIM : stm32wbxx_hal_flash.h
  • OB_USER_ALL : stm32wbxx_hal_flash.h
  • OB_USER_BOR_LEV : stm32wbxx_hal_flash.h
  • OB_USER_IWDG_STDBY : stm32wbxx_hal_flash.h
  • OB_USER_IWDG_STOP : stm32wbxx_hal_flash.h
  • OB_USER_IWDG_SW : stm32wbxx_hal_flash.h
  • OB_USER_nBOOT0 : stm32wbxx_hal_flash.h
  • OB_USER_nBOOT1 : stm32wbxx_hal_flash.h
  • OB_USER_nRST_SHDW : stm32wbxx_hal_flash.h
  • OB_USER_nRST_STDBY : stm32wbxx_hal_flash.h
  • OB_USER_nRST_STOP : stm32wbxx_hal_flash.h
  • OB_USER_nSWBOOT0 : stm32wbxx_hal_flash.h
  • OB_USER_SRAM2PE : stm32wbxx_hal_flash.h
  • OB_USER_SRAM2RST : stm32wbxx_hal_flash.h
  • OB_USER_WWDG_SW : stm32wbxx_hal_flash.h
  • OB_WRPAREA_BANK1_AREAA : stm32wbxx_hal_flash.h
  • OB_WRPAREA_BANK1_AREAB : stm32wbxx_hal_flash.h
  • OB_WWDG_HW : stm32wbxx_hal_flash.h
  • OB_WWDG_SW : stm32wbxx_hal_flash.h
  • OC1Config() : stm32wbxx_ll_tim.c
  • OC2Config() : stm32wbxx_ll_tim.c
  • OC3Config() : stm32wbxx_ll_tim.c
  • OC4Config() : stm32wbxx_ll_tim.c
  • OC5Config() : stm32wbxx_ll_tim.c
  • OC6Config() : stm32wbxx_ll_tim.c
  • OFFSET_TAB_CCMRx : stm32wbxx_ll_tim.h
  • OPTIONBYTE_ALL : stm32wbxx_hal_flash.h
  • OPTIONBYTE_C2_BOOT_VECT : stm32wbxx_hal_flash.h
  • OPTIONBYTE_IPCC_BUF_ADDR : stm32wbxx_hal_flash.h
  • OPTIONBYTE_PCROP : stm32wbxx_hal_flash.h
  • OPTIONBYTE_RDP : stm32wbxx_hal_flash.h
  • OPTIONBYTE_SECURE_MODE : stm32wbxx_hal_flash.h
  • OPTIONBYTE_USER : stm32wbxx_hal_flash.h
  • OPTIONBYTE_WRP : stm32wbxx_hal_flash.h
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
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  • Defines
  • _
  • a
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  • m
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  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- p -

  • PACKAGE_BASE_ADDRESS : stm32wbxx_ll_utils.h
  • pADC_CallbackTypeDef : stm32wbxx_hal_adc.h
  • PCD_BCD_CHARGING_DOWNSTREAM_PORT : stm32wbxx_hal_pcd.h
  • PCD_BCD_CONTACT_DETECTION : stm32wbxx_hal_pcd.h
  • PCD_BCD_DEDICATED_CHARGING_PORT : stm32wbxx_hal_pcd.h
  • PCD_BCD_DISCOVERY_COMPLETED : stm32wbxx_hal_pcd.h
  • PCD_BCD_ERROR : stm32wbxx_hal_pcd.h
  • PCD_BCD_MsgTypeDef : stm32wbxx_hal_pcd.h
  • PCD_BCD_STD_DOWNSTREAM_PORT : stm32wbxx_hal_pcd.h
  • PCD_CALC_BLK2 : stm32wbxx_hal_pcd.h
  • PCD_CALC_BLK32 : stm32wbxx_hal_pcd.h
  • PCD_CLEAR_EP_DBUF : stm32wbxx_hal_pcd.h
  • PCD_CLEAR_EP_KIND : stm32wbxx_hal_pcd.h
  • PCD_CLEAR_OUT_STATUS : stm32wbxx_hal_pcd.h
  • PCD_CLEAR_RX_DTOG : stm32wbxx_hal_pcd.h
  • PCD_CLEAR_RX_EP_CTR : stm32wbxx_hal_pcd.h
  • PCD_CLEAR_TX_DTOG : stm32wbxx_hal_pcd.h
  • PCD_CLEAR_TX_EP_CTR : stm32wbxx_hal_pcd.h
  • PCD_DBL_BUF : stm32wbxx_hal_pcd.h
  • PCD_ENDP0 : stm32wbxx_hal_pcd.h
  • PCD_ENDP1 : stm32wbxx_hal_pcd.h
  • PCD_ENDP2 : stm32wbxx_hal_pcd.h
  • PCD_ENDP3 : stm32wbxx_hal_pcd.h
  • PCD_ENDP4 : stm32wbxx_hal_pcd.h
  • PCD_ENDP5 : stm32wbxx_hal_pcd.h
  • PCD_ENDP6 : stm32wbxx_hal_pcd.h
  • PCD_ENDP7 : stm32wbxx_hal_pcd.h
  • PCD_EP0MPS_08 : stm32wbxx_hal_pcd.h
  • PCD_EP0MPS_16 : stm32wbxx_hal_pcd.h
  • PCD_EP0MPS_32 : stm32wbxx_hal_pcd.h
  • PCD_EP0MPS_64 : stm32wbxx_hal_pcd.h
  • PCD_EP_ISR_Handler() : stm32wbxx_hal_pcd.c
  • PCD_EP_RX_CNT : stm32wbxx_hal_pcd.h
  • PCD_EP_TX_CNT : stm32wbxx_hal_pcd.h
  • PCD_EPTypeDef : stm32wbxx_hal_pcd.h
  • PCD_FreeUserBuffer : stm32wbxx_hal_pcd.h
  • PCD_GET_ENDPOINT : stm32wbxx_hal_pcd.h
  • PCD_GET_EP_ADDRESS : stm32wbxx_hal_pcd.h
  • PCD_GET_EP_DBUF0_ADDR : stm32wbxx_hal_pcd.h
  • PCD_GET_EP_DBUF0_CNT : stm32wbxx_hal_pcd.h
  • PCD_GET_EP_DBUF1_ADDR : stm32wbxx_hal_pcd.h
  • PCD_GET_EP_DBUF1_CNT : stm32wbxx_hal_pcd.h
  • PCD_GET_EP_RX_ADDRESS : stm32wbxx_hal_pcd.h
  • PCD_GET_EP_RX_CNT : stm32wbxx_hal_pcd.h
  • PCD_GET_EP_RX_STALL_STATUS : stm32wbxx_hal_pcd.h
  • PCD_GET_EP_RX_STATUS : stm32wbxx_hal_pcd.h
  • PCD_GET_EP_TX_ADDRESS : stm32wbxx_hal_pcd.h
  • PCD_GET_EP_TX_CNT : stm32wbxx_hal_pcd.h
  • PCD_GET_EP_TX_STALL_STATUS : stm32wbxx_hal_pcd.h
  • PCD_GET_EP_TX_STATUS : stm32wbxx_hal_pcd.h
  • PCD_GET_EPTYPE : stm32wbxx_hal_pcd.h
  • PCD_HandleTypeDef : stm32wbxx_hal_pcd.h
  • PCD_InitTypeDef : stm32wbxx_hal_pcd.h
  • PCD_LPM_L0_ACTIVE : stm32wbxx_hal_pcd.h
  • PCD_LPM_L1_ACTIVE : stm32wbxx_hal_pcd.h
  • PCD_LPM_MsgTypeDef : stm32wbxx_hal_pcd.h
  • PCD_LPM_StateTypeDef : stm32wbxx_hal_pcd.h
  • PCD_MAX : stm32wbxx_hal_pcd.c
  • PCD_MIN : stm32wbxx_hal_pcd.c
  • PCD_PHY_EMBEDDED : stm32wbxx_hal_pcd.h
  • PCD_PHY_ULPI : stm32wbxx_hal_pcd.h
  • PCD_PHY_UTMI : stm32wbxx_hal_pcd.h
  • PCD_RX_DTOG : stm32wbxx_hal_pcd.h
  • PCD_SET_ENDPOINT : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_ADDRESS : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_CNT_RX_REG : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_DBUF : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_DBUF0_ADDR : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_DBUF0_CNT : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_DBUF1_ADDR : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_DBUF1_CNT : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_DBUF_ADDR : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_DBUF_CNT : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_KIND : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_RX_ADDRESS : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_RX_CNT : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_RX_DBUF0_CNT : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_RX_STATUS : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_RX_VALID : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_TX_ADDRESS : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_TX_CNT : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_TX_STATUS : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_TX_VALID : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_TXRX_STATUS : stm32wbxx_hal_pcd.h
  • PCD_SET_EPTYPE : stm32wbxx_hal_pcd.h
  • PCD_SET_OUT_STATUS : stm32wbxx_hal_pcd.h
  • PCD_SNG_BUF : stm32wbxx_hal_pcd.h
  • PCD_SPEED_FULL : stm32wbxx_hal_pcd.h
  • PCD_StateTypeDef : stm32wbxx_hal_pcd.h
  • PCD_TX_DTOG : stm32wbxx_hal_pcd.h
  • PCD_TypeDef : stm32wbxx_hal_pcd.h
  • pCOMP_CallbackTypeDef : stm32wbxx_hal_comp.h
  • pCRYP_CallbackTypeDef : stm32wbxx_hal_cryp.h
  • pFlash : stm32wbxx_hal_flash.c , stm32wbxx_hal_flash.h
  • pI2C_AddrCallbackTypeDef : stm32wbxx_hal_i2c.h
  • pI2C_CallbackTypeDef : stm32wbxx_hal_i2c.h
  • pIRDA_CallbackTypeDef : stm32wbxx_hal_irda.h
  • PKA_ARI_Set() : stm32wbxx_hal_pka.c
  • PKA_CheckError() : stm32wbxx_hal_pka.c
  • PKA_CmpInTypeDef : stm32wbxx_hal_pka.h
  • PKA_ECCMul_Set() : stm32wbxx_hal_pka.c
  • PKA_ECCMulFastMode_Set() : stm32wbxx_hal_pka.c
  • PKA_ECCMulOutTypeDef : stm32wbxx_hal_pka.h
  • PKA_ECDSASign_Set() : stm32wbxx_hal_pka.c
  • PKA_ECDSAVerif_Set() : stm32wbxx_hal_pka.c
  • PKA_FLAG_ADDRERR : stm32wbxx_hal_pka.h
  • PKA_FLAG_PROCEND : stm32wbxx_hal_pka.h
  • PKA_FLAG_RAMERR : stm32wbxx_hal_pka.h
  • PKA_GetArraySize_u8() : stm32wbxx_hal_pka.c
  • PKA_GetBitSize_u32() : stm32wbxx_hal_pka.c
  • PKA_GetBitSize_u8() : stm32wbxx_hal_pka.c
  • PKA_GetMode() : stm32wbxx_hal_pka.c
  • PKA_GetOptBitSize_u8() : stm32wbxx_hal_pka.c
  • PKA_HandleTypeDef : stm32wbxx_hal_pka.h
  • PKA_IT_ADDRERR : stm32wbxx_hal_pka.h
  • PKA_IT_PROCEND : stm32wbxx_hal_pka.h
  • PKA_IT_RAMERR : stm32wbxx_hal_pka.h
  • PKA_Memcpy_u32_to_u32() : stm32wbxx_hal_pka.c
  • PKA_Memcpy_u32_to_u8() : stm32wbxx_hal_pka.c
  • PKA_Memcpy_u8_to_u32() : stm32wbxx_hal_pka.c
  • PKA_MODE_ARITHMETIC_ADD : stm32wbxx_hal_pka.h
  • PKA_MODE_ARITHMETIC_MUL : stm32wbxx_hal_pka.h
  • PKA_MODE_ARITHMETIC_SUB : stm32wbxx_hal_pka.h
  • PKA_MODE_COMPARISON : stm32wbxx_hal_pka.h
  • PKA_MODE_ECC_MUL : stm32wbxx_hal_pka.h
  • PKA_MODE_ECC_MUL_FAST_MODE : stm32wbxx_hal_pka.h
  • PKA_MODE_ECDSA_SIGNATURE : stm32wbxx_hal_pka.h
  • PKA_MODE_ECDSA_VERIFICATION : stm32wbxx_hal_pka.h
  • PKA_MODE_MODULAR_ADD : stm32wbxx_hal_pka.h
  • PKA_MODE_MODULAR_EXP : stm32wbxx_hal_pka.h
  • PKA_MODE_MODULAR_EXP_FAST_MODE : stm32wbxx_hal_pka.h
  • PKA_MODE_MODULAR_INV : stm32wbxx_hal_pka.h
  • PKA_MODE_MODULAR_RED : stm32wbxx_hal_pka.h
  • PKA_MODE_MODULAR_SUB : stm32wbxx_hal_pka.h
  • PKA_MODE_MONTGOMERY_MUL : stm32wbxx_hal_pka.h
  • PKA_MODE_MONTGOMERY_PARAM : stm32wbxx_hal_pka.h
  • PKA_MODE_POINT_CHECK : stm32wbxx_hal_pka.h
  • PKA_MODE_RSA_CRT_EXP : stm32wbxx_hal_pka.h
  • PKA_ModExp_Set() : stm32wbxx_hal_pka.c
  • PKA_ModExpFastMode_Set() : stm32wbxx_hal_pka.c
  • PKA_ModInv_Set() : stm32wbxx_hal_pka.c
  • PKA_ModRed_Set() : stm32wbxx_hal_pka.c
  • PKA_ModSubInTypeDef : stm32wbxx_hal_pka.h
  • PKA_MontgomeryMulInTypeDef : stm32wbxx_hal_pka.h
  • PKA_MontgomeryParam_Set() : stm32wbxx_hal_pka.c
  • PKA_MulInTypeDef : stm32wbxx_hal_pka.h
  • PKA_PointCheck_Set() : stm32wbxx_hal_pka.c
  • PKA_PollEndOfOperation() : stm32wbxx_hal_pka.c
  • PKA_Process() : stm32wbxx_hal_pka.c
  • PKA_Process_IT() : stm32wbxx_hal_pka.c
  • PKA_RAM_SIZE : stm32wbxx_hal_pka.c
  • PKA_RSACRTExp_Set() : stm32wbxx_hal_pka.c
  • PKA_SubInTypeDef : stm32wbxx_hal_pka.h
  • PLL_TIMEOUT_VALUE : stm32wbxx_hal_rcc.c , stm32wbxx_hal_rcc_ex.c
  • PLLSAI1_TIMEOUT_VALUE : stm32wbxx_hal_rcc.c , stm32wbxx_hal_rcc_ex.c
  • PLLSOURCE_NONE : stm32wbxx_hal_rcc.c
  • pLPTIM_CallbackTypeDef : stm32wbxx_hal_lptim.h
  • pPCD_BcdCallbackTypeDef : stm32wbxx_hal_pcd.h
  • pPCD_CallbackTypeDef : stm32wbxx_hal_pcd.h
  • pPCD_DataInStageCallbackTypeDef : stm32wbxx_hal_pcd.h
  • pPCD_DataOutStageCallbackTypeDef : stm32wbxx_hal_pcd.h
  • pPCD_IsoInIncpltCallbackTypeDef : stm32wbxx_hal_pcd.h
  • pPCD_IsoOutIncpltCallbackTypeDef : stm32wbxx_hal_pcd.h
  • pPCD_LpmCallbackTypeDef : stm32wbxx_hal_pcd.h
  • pPKA_CallbackTypeDef : stm32wbxx_hal_pka.h
  • pQSPI_CallbackTypeDef : stm32wbxx_hal_qspi.h
  • PREFETCH_ENABLE : stm32wbxx_hal_conf.h
  • PRESCALER_TIMEOUT_VALUE : stm32wbxx_hal_rcc.c
  • pRNG_CallbackTypeDef : stm32wbxx_hal_rng.h
  • pRNG_ReadyDataCallbackTypeDef : stm32wbxx_hal_rng.h
  • pRTC_CallbackTypeDef : stm32wbxx_hal_rtc.h
  • pSAI_CallbackTypeDef : stm32wbxx_hal_sai.h
  • pSMARTCARD_CallbackTypeDef : stm32wbxx_hal_smartcard.h
  • pSMBUS_AddrCallbackTypeDef : stm32wbxx_hal_smbus.h
  • pSMBUS_CallbackTypeDef : stm32wbxx_hal_smbus.h
  • pSPI_CallbackTypeDef : stm32wbxx_hal_spi.h
  • pTIM_CallbackTypeDef : stm32wbxx_hal_tim.h
  • pTSC_CallbackTypeDef : stm32wbxx_hal_tsc.h
  • pUART_CallbackTypeDef : stm32wbxx_hal_uart.h
  • pUSART_CallbackTypeDef : stm32wbxx_hal_usart.h
  • PVD_FALLING_EDGE : stm32wbxx_hal_pwr.h
  • PVD_MODE_IT : stm32wbxx_hal_pwr.h
  • PVD_RISING_EDGE : stm32wbxx_hal_pwr.h
  • PVD_RISING_FALLING_EDGE : stm32wbxx_hal_pwr.h
  • PVM_FALLING_EDGE : stm32wbxx_hal_pwr_ex.h
  • PVM_MODE_EVT : stm32wbxx_hal_pwr_ex.h
  • PVM_MODE_IT : stm32wbxx_hal_pwr_ex.h
  • PVM_RISING_EDGE : stm32wbxx_hal_pwr_ex.h
  • PVM_RISING_FALLING_EDGE : stm32wbxx_hal_pwr_ex.h
  • PWR_BATTERY_CHARGING_DISABLE : stm32wbxx_hal_pwr_ex.h
  • PWR_BATTERY_CHARGING_ENABLE : stm32wbxx_hal_pwr_ex.h
  • PWR_BATTERY_CHARGING_RESISTOR_1_5 : stm32wbxx_hal_pwr_ex.h
  • PWR_BATTERY_CHARGING_RESISTOR_5 : stm32wbxx_hal_pwr_ex.h
  • PWR_BOR_SMPS_FORCE_BYPASS : stm32wbxx_hal_pwr_ex.h
  • PWR_BOR_SYSTEM_RESET : stm32wbxx_hal_pwr_ex.h
  • PWR_C2CR1_RESET_VALUE : stm32wbxx_hal_pwr.c , stm32wbxx_ll_pwr.c
  • PWR_C2CR3_RESET_VALUE : stm32wbxx_hal_pwr.c , stm32wbxx_ll_pwr.c
  • PWR_CORE_CPU1 : stm32wbxx_hal_pwr_ex.h
  • PWR_CORE_CPU2 : stm32wbxx_hal_pwr_ex.h
  • PWR_CR1_RESET_VALUE : stm32wbxx_hal_pwr.c , stm32wbxx_ll_pwr.c
  • PWR_CR2_RESET_VALUE : stm32wbxx_hal_pwr.c , stm32wbxx_ll_pwr.c
  • PWR_CR3_RESET_VALUE : stm32wbxx_hal_pwr.c , stm32wbxx_ll_pwr.c
  • PWR_CR4_RESET_VALUE : stm32wbxx_hal_pwr.c , stm32wbxx_ll_pwr.c
  • PWR_CR5_RESET_VALUE : stm32wbxx_hal_pwr.c , stm32wbxx_ll_pwr.c
  • PWR_EXTI_LINE_PVD : stm32wbxx_hal_pwr.h
  • PWR_EXTI_LINE_PVM1 : stm32wbxx_hal_pwr_ex.h
  • PWR_EXTI_LINE_PVM3 : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_802ACTI : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_BHWF : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_BLEACTI : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_C1DEEPSLEEP : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_C2DEEPSLEEP : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_C2SB : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_C2STOP : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_CRITICAL_RF_PHASE : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_FRCBYPI : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_HOLDC2I : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_PVDO : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_PVMO1 : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_PVMO3 : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_REGLPF : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_REGLPS : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_RFPHASEI : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_SB : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_SETTING_DELAY_US : stm32wbxx_hal_pwr_ex.c
  • PWR_FLAG_SMPSBYPF : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_SMPSRDYF : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_STOP : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_VOSF : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_WU : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_WUF1 : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_WUF2 : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_WUF3 : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_WUF4 : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_WUF5 : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_WUFI : stm32wbxx_hal_pwr_ex.h
  • PWR_FLASHPD_LPRUN : stm32wbxx_hal_pwr_ex.h
  • PWR_FLASHPD_LPSLEEP : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_A : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_B : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_BIT_0 : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_BIT_1 : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_BIT_10 : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_BIT_11 : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_BIT_12 : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_BIT_13 : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_BIT_14 : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_BIT_15 : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_BIT_2 : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_BIT_3 : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_BIT_4 : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_BIT_5 : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_BIT_6 : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_BIT_7 : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_BIT_8 : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_BIT_9 : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_C : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_D : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_E : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_H : stm32wbxx_hal_pwr_ex.h
  • PWR_LOWPOWERMODE_SHUTDOWN : stm32wbxx_hal_pwr.h
  • PWR_LOWPOWERMODE_STANDBY : stm32wbxx_hal_pwr.h
  • PWR_LOWPOWERMODE_STOP0 : stm32wbxx_hal_pwr.h
  • PWR_LOWPOWERMODE_STOP1 : stm32wbxx_hal_pwr.h
  • PWR_LOWPOWERMODE_STOP2 : stm32wbxx_hal_pwr.h
  • PWR_LOWPOWERREGULATOR_ON : stm32wbxx_hal_pwr.h
  • PWR_MAINREGULATOR_ON : stm32wbxx_hal_pwr.h
  • PWR_PDCRA_RESET_VALUE : stm32wbxx_hal_pwr.c , stm32wbxx_ll_pwr.c
  • PWR_PDCRB_RESET_VALUE : stm32wbxx_hal_pwr.c , stm32wbxx_ll_pwr.c
  • PWR_PDCRC_RESET_VALUE : stm32wbxx_hal_pwr.c , stm32wbxx_ll_pwr.c
  • PWR_PDCRD_RESET_VALUE : stm32wbxx_ll_pwr.c , stm32wbxx_hal_pwr.c
  • PWR_PDCRE_RESET_VALUE : stm32wbxx_hal_pwr.c , stm32wbxx_ll_pwr.c
  • PWR_PDCRH_RESET_VALUE : stm32wbxx_hal_pwr.c , stm32wbxx_ll_pwr.c
  • PWR_PIN_POLARITY_HIGH : stm32wbxx_hal_pwr_ex.h
  • PWR_PIN_POLARITY_LOW : stm32wbxx_hal_pwr_ex.h
  • PWR_PORTE_AVAILABLE_PINS : stm32wbxx_hal_pwr_ex.c
  • PWR_PORTH_AVAILABLE_PINS : stm32wbxx_hal_pwr_ex.c
  • PWR_PUCRA_RESET_VALUE : stm32wbxx_ll_pwr.c , stm32wbxx_hal_pwr.c
  • PWR_PUCRB_RESET_VALUE : stm32wbxx_hal_pwr.c , stm32wbxx_ll_pwr.c
  • PWR_PUCRC_RESET_VALUE : stm32wbxx_hal_pwr.c , stm32wbxx_ll_pwr.c
  • PWR_PUCRD_RESET_VALUE : stm32wbxx_hal_pwr.c , stm32wbxx_ll_pwr.c
  • PWR_PUCRE_RESET_VALUE : stm32wbxx_ll_pwr.c , stm32wbxx_hal_pwr.c
  • PWR_PUCRH_RESET_VALUE : stm32wbxx_hal_pwr.c , stm32wbxx_ll_pwr.c
  • PWR_PVD_MODE_IT_FALLING : stm32wbxx_hal_pwr.h
  • PWR_PVD_MODE_IT_RISING : stm32wbxx_hal_pwr.h
  • PWR_PVD_MODE_IT_RISING_FALLING : stm32wbxx_hal_pwr.h
  • PWR_PVD_MODE_NORMAL : stm32wbxx_hal_pwr.h
  • PWR_PVDLEVEL_0 : stm32wbxx_hal_pwr.h
  • PWR_PVDLEVEL_1 : stm32wbxx_hal_pwr.h
  • PWR_PVDLEVEL_2 : stm32wbxx_hal_pwr.h
  • PWR_PVDLEVEL_3 : stm32wbxx_hal_pwr.h
  • PWR_PVDLEVEL_4 : stm32wbxx_hal_pwr.h
  • PWR_PVDLEVEL_5 : stm32wbxx_hal_pwr.h
  • PWR_PVDLEVEL_6 : stm32wbxx_hal_pwr.h
  • PWR_PVDLEVEL_7 : stm32wbxx_hal_pwr.h
  • PWR_PVM_1 : stm32wbxx_hal_pwr_ex.h
  • PWR_PVM_3 : stm32wbxx_hal_pwr_ex.h
  • PWR_PVM_MODE_EVENT_FALLING : stm32wbxx_hal_pwr_ex.h
  • PWR_PVM_MODE_EVENT_RISING : stm32wbxx_hal_pwr_ex.h
  • PWR_PVM_MODE_EVENT_RISING_FALLING : stm32wbxx_hal_pwr_ex.h
  • PWR_PVM_MODE_IT_FALLING : stm32wbxx_hal_pwr_ex.h
  • PWR_PVM_MODE_IT_RISING : stm32wbxx_hal_pwr_ex.h
  • PWR_PVM_MODE_IT_RISING_FALLING : stm32wbxx_hal_pwr_ex.h
  • PWR_PVM_MODE_NORMAL : stm32wbxx_hal_pwr_ex.h
  • PWR_REGULATOR_VOLTAGE_SCALE1 : stm32wbxx_hal_pwr_ex.h
  • PWR_REGULATOR_VOLTAGE_SCALE2 : stm32wbxx_hal_pwr_ex.h
  • PWR_SLEEPENTRY_WFE : stm32wbxx_hal_pwr.h
  • PWR_SLEEPENTRY_WFI : stm32wbxx_hal_pwr.h
  • PWR_SMPS_BYPASS : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_OUTPUT_VOLTAGE_1V20 : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_OUTPUT_VOLTAGE_1V25 : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_OUTPUT_VOLTAGE_1V30 : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_OUTPUT_VOLTAGE_1V35 : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_OUTPUT_VOLTAGE_1V40 : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_OUTPUT_VOLTAGE_1V45 : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_OUTPUT_VOLTAGE_1V50 : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_OUTPUT_VOLTAGE_1V55 : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_OUTPUT_VOLTAGE_1V60 : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_OUTPUT_VOLTAGE_1V65 : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_OUTPUT_VOLTAGE_1V70 : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_OUTPUT_VOLTAGE_1V75 : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_OUTPUT_VOLTAGE_1V80 : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_OUTPUT_VOLTAGE_1V85 : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_OUTPUT_VOLTAGE_1V90 : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_STARTUP_CURRENT_100MA : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_STARTUP_CURRENT_120MA : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_STARTUP_CURRENT_140MA : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_STARTUP_CURRENT_160MA : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_STARTUP_CURRENT_180MA : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_STARTUP_CURRENT_200MA : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_STARTUP_CURRENT_220MA : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_STARTUP_CURRENT_80MA : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_STEP_DOWN : stm32wbxx_hal_pwr_ex.h
  • PWR_STOPENTRY_WFE : stm32wbxx_hal_pwr.h
  • PWR_STOPENTRY_WFI : stm32wbxx_hal_pwr.h
  • PWR_WAKEUP_PIN1 : stm32wbxx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN1_HIGH : stm32wbxx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN1_LOW : stm32wbxx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN2 : stm32wbxx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN2_HIGH : stm32wbxx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN2_LOW : stm32wbxx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN3 : stm32wbxx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN3_HIGH : stm32wbxx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN3_LOW : stm32wbxx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN4 : stm32wbxx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN4_HIGH : stm32wbxx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN4_LOW : stm32wbxx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN5 : stm32wbxx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN5_HIGH : stm32wbxx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN5_LOW : stm32wbxx_hal_pwr_ex.h
  • PWR_WAKEUPTARGET_ALL_CPU : stm32wbxx_hal_pwr_ex.h
  • PWR_WAKEUPTARGET_CPU1 : stm32wbxx_hal_pwr_ex.h
  • PWR_WAKEUPTARGET_CPU2 : stm32wbxx_hal_pwr_ex.h
  • PWR_WAKEUPTARGET_RF : stm32wbxx_hal_pwr_ex.h
  • PWR_WUP_POLARITY_SHIFT : stm32wbxx_hal_pwr_ex.h
  • pWWDG_CallbackTypeDef : stm32wbxx_hal_wwdg.h
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
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  • a
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- q -

  • QSPI_ADDRESS_16_BITS : stm32wbxx_hal_qspi.h
  • QSPI_ADDRESS_1_LINE : stm32wbxx_hal_qspi.h
  • QSPI_ADDRESS_24_BITS : stm32wbxx_hal_qspi.h
  • QSPI_ADDRESS_2_LINES : stm32wbxx_hal_qspi.h
  • QSPI_ADDRESS_32_BITS : stm32wbxx_hal_qspi.h
  • QSPI_ADDRESS_4_LINES : stm32wbxx_hal_qspi.h
  • QSPI_ADDRESS_8_BITS : stm32wbxx_hal_qspi.h
  • QSPI_ADDRESS_NONE : stm32wbxx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_16_BITS : stm32wbxx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_1_LINE : stm32wbxx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_24_BITS : stm32wbxx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_2_LINES : stm32wbxx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_32_BITS : stm32wbxx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_4_LINES : stm32wbxx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_8_BITS : stm32wbxx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_NONE : stm32wbxx_hal_qspi.h
  • QSPI_AUTOMATIC_STOP_DISABLE : stm32wbxx_hal_qspi.h
  • QSPI_AUTOMATIC_STOP_ENABLE : stm32wbxx_hal_qspi.h
  • QSPI_CLOCK_MODE_0 : stm32wbxx_hal_qspi.h
  • QSPI_CLOCK_MODE_3 : stm32wbxx_hal_qspi.h
  • QSPI_Config() : stm32wbxx_hal_qspi.c
  • QSPI_CS_HIGH_TIME_1_CYCLE : stm32wbxx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_2_CYCLE : stm32wbxx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_3_CYCLE : stm32wbxx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_4_CYCLE : stm32wbxx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_5_CYCLE : stm32wbxx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_6_CYCLE : stm32wbxx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_7_CYCLE : stm32wbxx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_8_CYCLE : stm32wbxx_hal_qspi.h
  • QSPI_DATA_1_LINE : stm32wbxx_hal_qspi.h
  • QSPI_DATA_2_LINES : stm32wbxx_hal_qspi.h
  • QSPI_DATA_4_LINES : stm32wbxx_hal_qspi.h
  • QSPI_DATA_NONE : stm32wbxx_hal_qspi.h
  • QSPI_DDR_MODE_DISABLE : stm32wbxx_hal_qspi.h
  • QSPI_DDR_MODE_ENABLE : stm32wbxx_hal_qspi.h
  • QSPI_DMAAbortCplt() : stm32wbxx_hal_qspi.c
  • QSPI_DMAError() : stm32wbxx_hal_qspi.c
  • QSPI_DMARxCplt() : stm32wbxx_hal_qspi.c
  • QSPI_DMARxHalfCplt() : stm32wbxx_hal_qspi.c
  • QSPI_DMATxCplt() : stm32wbxx_hal_qspi.c
  • QSPI_DMATxHalfCplt() : stm32wbxx_hal_qspi.c
  • QSPI_FLAG_BUSY : stm32wbxx_hal_qspi.h
  • QSPI_FLAG_FT : stm32wbxx_hal_qspi.h
  • QSPI_FLAG_SM : stm32wbxx_hal_qspi.h
  • QSPI_FLAG_TC : stm32wbxx_hal_qspi.h
  • QSPI_FLAG_TE : stm32wbxx_hal_qspi.h
  • QSPI_FLAG_TO : stm32wbxx_hal_qspi.h
  • QSPI_FUNCTIONAL_MODE_AUTO_POLLING : stm32wbxx_hal_qspi.c
  • QSPI_FUNCTIONAL_MODE_INDIRECT_READ : stm32wbxx_hal_qspi.c
  • QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE : stm32wbxx_hal_qspi.c
  • QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED : stm32wbxx_hal_qspi.c
  • QSPI_HandleTypeDef : stm32wbxx_hal_qspi.h
  • QSPI_INSTRUCTION_1_LINE : stm32wbxx_hal_qspi.h
  • QSPI_INSTRUCTION_2_LINES : stm32wbxx_hal_qspi.h
  • QSPI_INSTRUCTION_4_LINES : stm32wbxx_hal_qspi.h
  • QSPI_INSTRUCTION_NONE : stm32wbxx_hal_qspi.h
  • QSPI_IT_FT : stm32wbxx_hal_qspi.h
  • QSPI_IT_SM : stm32wbxx_hal_qspi.h
  • QSPI_IT_TC : stm32wbxx_hal_qspi.h
  • QSPI_IT_TE : stm32wbxx_hal_qspi.h
  • QSPI_IT_TO : stm32wbxx_hal_qspi.h
  • QSPI_MATCH_MODE_AND : stm32wbxx_hal_qspi.h
  • QSPI_MATCH_MODE_OR : stm32wbxx_hal_qspi.h
  • QSPI_SAMPLE_SHIFTING_HALFCYCLE : stm32wbxx_hal_qspi.h
  • QSPI_SAMPLE_SHIFTING_NONE : stm32wbxx_hal_qspi.h
  • QSPI_SIOO_INST_EVERY_CMD : stm32wbxx_hal_qspi.h
  • QSPI_SIOO_INST_ONLY_FIRST_CMD : stm32wbxx_hal_qspi.h
  • QSPI_TIMEOUT_COUNTER_DISABLE : stm32wbxx_hal_qspi.h
  • QSPI_TIMEOUT_COUNTER_ENABLE : stm32wbxx_hal_qspi.h
  • QSPI_WaitFlagStateUntilTimeout() : stm32wbxx_hal_qspi.c
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- r -

  • RCC_ADCCLKSOURCE_NONE : stm32wbxx_hal_rcc_ex.h
  • RCC_ADCCLKSOURCE_PLL : stm32wbxx_hal_rcc_ex.h
  • RCC_ADCCLKSOURCE_PLLSAI1 : stm32wbxx_hal_rcc_ex.h
  • RCC_ADCCLKSOURCE_SYSCLK : stm32wbxx_hal_rcc_ex.h
  • RCC_CLOCKTYPE_HCLK : stm32wbxx_hal_rcc.h
  • RCC_CLOCKTYPE_HCLK2 : stm32wbxx_hal_rcc.h
  • RCC_CLOCKTYPE_HCLK4 : stm32wbxx_hal_rcc.h
  • RCC_CLOCKTYPE_PCLK1 : stm32wbxx_hal_rcc.h
  • RCC_CLOCKTYPE_PCLK2 : stm32wbxx_hal_rcc.h
  • RCC_CLOCKTYPE_SYSCLK : stm32wbxx_hal_rcc.h
  • RCC_CRS_ERRORLIMIT_DEFAULT : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_FLAG_ERR : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_FLAG_ERROR_MASK : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_FLAG_ESYNC : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCERR : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCMISS : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCOK : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCWARN : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_FLAG_TRIMOVF : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_FREQERRORDIR_DOWN : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_FREQERRORDIR_UP : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_HSI48CALIBRATION_DEFAULT : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_IT_ERR : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_IT_ERROR_MASK : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_IT_ESYNC : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCERR : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCMISS : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCOK : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCWARN : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_IT_TRIMOVF : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_NONE : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_RELOADVALUE_DEFAULT : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV1 : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV128 : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV16 : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV2 : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV32 : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV4 : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV64 : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV8 : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_SYNC_POLARITY_FALLING : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_SYNC_POLARITY_RISING : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_SYNC_SOURCE_GPIO : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_SYNC_SOURCE_LSE : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_SYNC_SOURCE_USB : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_SYNCERR : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_SYNCMISS : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_SYNCOK : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_SYNCWARN : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_TIMEOUT : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_TRIMOVF : stm32wbxx_hal_rcc_ex.h
  • RCC_DBP_TIMEOUT_VALUE : stm32wbxx_hal_rcc.h
  • RCC_EXTI_LINE_LSECSS : stm32wbxx_hal_rcc_ex.h
  • RCC_FLAG_BORRST : stm32wbxx_hal_rcc.h
  • RCC_FLAG_HSERDY : stm32wbxx_hal_rcc.h
  • RCC_FLAG_HSI48RDY : stm32wbxx_hal_rcc.h
  • RCC_FLAG_HSIRDY : stm32wbxx_hal_rcc.h
  • RCC_FLAG_IWDGRST : stm32wbxx_hal_rcc.h
  • RCC_FLAG_LPWRRST : stm32wbxx_hal_rcc.h
  • RCC_FLAG_LSECSSD : stm32wbxx_hal_rcc.h
  • RCC_FLAG_LSERDY : stm32wbxx_hal_rcc.h
  • RCC_FLAG_LSI1RDY : stm32wbxx_hal_rcc.h
  • RCC_FLAG_LSI2RDY : stm32wbxx_hal_rcc.h
  • RCC_FLAG_MASK : stm32wbxx_hal_rcc.h
  • RCC_FLAG_MSIRDY : stm32wbxx_hal_rcc.h
  • RCC_FLAG_OBLRST : stm32wbxx_hal_rcc.h
  • RCC_FLAG_PINRST : stm32wbxx_hal_rcc.h
  • RCC_FLAG_PLLRDY : stm32wbxx_hal_rcc.h
  • RCC_FLAG_PLLSAI1RDY : stm32wbxx_hal_rcc.h
  • RCC_FLAG_SFTRST : stm32wbxx_hal_rcc.h
  • RCC_FLAG_WWDGRST : stm32wbxx_hal_rcc.h
  • RCC_GetHCLK1ClockFreq() : stm32wbxx_ll_rcc.c
  • RCC_GetHCLK2ClockFreq() : stm32wbxx_ll_rcc.c
  • RCC_GetHCLK4ClockFreq() : stm32wbxx_ll_rcc.c
  • RCC_GetHCLK5ClockFreq() : stm32wbxx_ll_rcc.c
  • RCC_GetPCLK1ClockFreq() : stm32wbxx_ll_rcc.c
  • RCC_GetPCLK2ClockFreq() : stm32wbxx_ll_rcc.c
  • RCC_GetSystemClockFreq() : stm32wbxx_ll_rcc.c
  • RCC_HCLK5SOURCE_HSE : stm32wbxx_hal_rcc_ex.h
  • RCC_HCLK5SOURCE_HSI : stm32wbxx_hal_rcc_ex.h
  • RCC_HCLK_DIV1 : stm32wbxx_hal_rcc.h
  • RCC_HCLK_DIV16 : stm32wbxx_hal_rcc.h
  • RCC_HCLK_DIV2 : stm32wbxx_hal_rcc.h
  • RCC_HCLK_DIV4 : stm32wbxx_hal_rcc.h
  • RCC_HCLK_DIV8 : stm32wbxx_hal_rcc.h
  • RCC_HSE_BYPASS : stm32wbxx_hal_rcc.h
  • RCC_HSE_CURRENTMAX_0 : stm32wbxx_hal_rcc.h
  • RCC_HSE_CURRENTMAX_1 : stm32wbxx_hal_rcc.h
  • RCC_HSE_CURRENTMAX_2 : stm32wbxx_hal_rcc.h
  • RCC_HSE_CURRENTMAX_3 : stm32wbxx_hal_rcc.h
  • RCC_HSE_CURRENTMAX_4 : stm32wbxx_hal_rcc.h
  • RCC_HSE_CURRENTMAX_5 : stm32wbxx_hal_rcc.h
  • RCC_HSE_CURRENTMAX_6 : stm32wbxx_hal_rcc.h
  • RCC_HSE_CURRENTMAX_7 : stm32wbxx_hal_rcc.h
  • RCC_HSE_OFF : stm32wbxx_hal_rcc.h
  • RCC_HSE_ON : stm32wbxx_hal_rcc.h
  • RCC_HSEAMPTHRESHOLD_1_2 : stm32wbxx_hal_rcc.h
  • RCC_HSEAMPTHRESHOLD_3_4 : stm32wbxx_hal_rcc.h
  • RCC_HSI48_OFF : stm32wbxx_hal_rcc.h
  • RCC_HSI48_ON : stm32wbxx_hal_rcc.h
  • RCC_HSI_OFF : stm32wbxx_hal_rcc.h
  • RCC_HSI_ON : stm32wbxx_hal_rcc.h
  • RCC_HSICALIBRATION_DEFAULT : stm32wbxx_hal_rcc.h
  • RCC_I2C1CLKSOURCE_HSI : stm32wbxx_hal_rcc_ex.h
  • RCC_I2C1CLKSOURCE_PCLK1 : stm32wbxx_hal_rcc_ex.h
  • RCC_I2C1CLKSOURCE_SYSCLK : stm32wbxx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_HSI : stm32wbxx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_PCLK1 : stm32wbxx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_SYSCLK : stm32wbxx_hal_rcc_ex.h
  • RCC_IT_HSECSS : stm32wbxx_hal_rcc.h
  • RCC_IT_HSERDY : stm32wbxx_hal_rcc.h
  • RCC_IT_HSI48RDY : stm32wbxx_hal_rcc.h
  • RCC_IT_HSIRDY : stm32wbxx_hal_rcc.h
  • RCC_IT_LSECSS : stm32wbxx_hal_rcc.h
  • RCC_IT_LSERDY : stm32wbxx_hal_rcc.h
  • RCC_IT_LSI1RDY : stm32wbxx_hal_rcc.h
  • RCC_IT_LSI2RDY : stm32wbxx_hal_rcc.h
  • RCC_IT_MSIRDY : stm32wbxx_hal_rcc.h
  • RCC_IT_PLLRDY : stm32wbxx_hal_rcc.h
  • RCC_IT_PLLSAI1RDY : stm32wbxx_hal_rcc.h
  • RCC_LPTIM1CLKSOURCE_HSI : stm32wbxx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_LSE : stm32wbxx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_LSI : stm32wbxx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_PCLK1 : stm32wbxx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_HSI : stm32wbxx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_LSE : stm32wbxx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_LSI : stm32wbxx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_PCLK1 : stm32wbxx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_HSI : stm32wbxx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_LSE : stm32wbxx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_PCLK1 : stm32wbxx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_SYSCLK : stm32wbxx_hal_rcc_ex.h
  • RCC_LSCO1 : stm32wbxx_hal_rcc_ex.h
  • RCC_LSCO2 : stm32wbxx_hal_rcc_ex.h
  • RCC_LSCO3 : stm32wbxx_hal_rcc_ex.h
  • RCC_LSCOSOURCE_LSE : stm32wbxx_hal_rcc_ex.h
  • RCC_LSCOSOURCE_LSI : stm32wbxx_hal_rcc_ex.h
  • RCC_LSE_BYPASS : stm32wbxx_hal_rcc.h
  • RCC_LSE_OFF : stm32wbxx_hal_rcc.h
  • RCC_LSE_ON : stm32wbxx_hal_rcc.h
  • RCC_LSE_TIMEOUT_VALUE : stm32wbxx_hal_rcc.h
  • RCC_LSEDRIVE_HIGH : stm32wbxx_hal_rcc.h
  • RCC_LSEDRIVE_LOW : stm32wbxx_hal_rcc.h
  • RCC_LSEDRIVE_MEDIUMHIGH : stm32wbxx_hal_rcc.h
  • RCC_LSEDRIVE_MEDIUMLOW : stm32wbxx_hal_rcc.h
  • RCC_LSI_OFF : stm32wbxx_hal_rcc.h
  • RCC_LSI_ON : stm32wbxx_hal_rcc.h
  • RCC_MCO : stm32wbxx_hal_rcc.h
  • RCC_MCO1 : stm32wbxx_hal_rcc.h
  • RCC_MCO1SOURCE_HSE : stm32wbxx_hal_rcc.h
  • RCC_MCO1SOURCE_HSE_BEFORE_STAB : stm32wbxx_hal_rcc.h
  • RCC_MCO1SOURCE_HSI : stm32wbxx_hal_rcc.h
  • RCC_MCO1SOURCE_HSI48 : stm32wbxx_hal_rcc.h
  • RCC_MCO1SOURCE_LSE : stm32wbxx_hal_rcc.h
  • RCC_MCO1SOURCE_LSI1 : stm32wbxx_hal_rcc.h
  • RCC_MCO1SOURCE_LSI2 : stm32wbxx_hal_rcc.h
  • RCC_MCO1SOURCE_MSI : stm32wbxx_hal_rcc.h
  • RCC_MCO1SOURCE_NOCLOCK : stm32wbxx_hal_rcc.h
  • RCC_MCO1SOURCE_PLLCLK : stm32wbxx_hal_rcc.h
  • RCC_MCO1SOURCE_SYSCLK : stm32wbxx_hal_rcc.h
  • RCC_MCO2 : stm32wbxx_hal_rcc.h
  • RCC_MCO3 : stm32wbxx_hal_rcc.h
  • RCC_MCODIV_1 : stm32wbxx_hal_rcc.h
  • RCC_MCODIV_16 : stm32wbxx_hal_rcc.h
  • RCC_MCODIV_2 : stm32wbxx_hal_rcc.h
  • RCC_MCODIV_4 : stm32wbxx_hal_rcc.h
  • RCC_MCODIV_8 : stm32wbxx_hal_rcc.h
  • RCC_MSI_OFF : stm32wbxx_hal_rcc.h
  • RCC_MSI_ON : stm32wbxx_hal_rcc.h
  • RCC_MSICALIBRATION_DEFAULT : stm32wbxx_hal_rcc.h
  • RCC_MSIRANGE_0 : stm32wbxx_hal_rcc.h
  • RCC_MSIRANGE_1 : stm32wbxx_hal_rcc.h
  • RCC_MSIRANGE_10 : stm32wbxx_hal_rcc.h
  • RCC_MSIRANGE_11 : stm32wbxx_hal_rcc.h
  • RCC_MSIRANGE_2 : stm32wbxx_hal_rcc.h
  • RCC_MSIRANGE_3 : stm32wbxx_hal_rcc.h
  • RCC_MSIRANGE_4 : stm32wbxx_hal_rcc.h
  • RCC_MSIRANGE_5 : stm32wbxx_hal_rcc.h
  • RCC_MSIRANGE_6 : stm32wbxx_hal_rcc.h
  • RCC_MSIRANGE_7 : stm32wbxx_hal_rcc.h
  • RCC_MSIRANGE_8 : stm32wbxx_hal_rcc.h
  • RCC_MSIRANGE_9 : stm32wbxx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSE : stm32wbxx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSI : stm32wbxx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSI48 : stm32wbxx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSE : stm32wbxx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSI1 : stm32wbxx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSI2 : stm32wbxx_hal_rcc.h
  • RCC_OSCILLATORTYPE_MSI : stm32wbxx_hal_rcc.h
  • RCC_OSCILLATORTYPE_NONE : stm32wbxx_hal_rcc.h
  • RCC_PERIPHCLK_ADC : stm32wbxx_hal_rcc_ex.h
  • RCC_PERIPHCLK_CLK48SEL : stm32wbxx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C1 : stm32wbxx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C3 : stm32wbxx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPTIM1 : stm32wbxx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPTIM2 : stm32wbxx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPUART1 : stm32wbxx_hal_rcc_ex.h
  • RCC_PERIPHCLK_RFWAKEUP : stm32wbxx_hal_rcc_ex.h
  • RCC_PERIPHCLK_RNG : stm32wbxx_hal_rcc_ex.h
  • RCC_PERIPHCLK_RTC : stm32wbxx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SAI1 : stm32wbxx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SMPS : stm32wbxx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART1 : stm32wbxx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USB : stm32wbxx_hal_rcc_ex.h
  • RCC_PLL_ADCCLK : stm32wbxx_hal_rcc.h
  • RCC_PLL_GetFreqDomain_48M() : stm32wbxx_ll_rcc.c
  • RCC_PLL_GetFreqDomain_ADC() : stm32wbxx_ll_rcc.c
  • RCC_PLL_GetFreqDomain_P() : stm32wbxx_hal_rcc_ex.c
  • RCC_PLL_GetFreqDomain_Q() : stm32wbxx_hal_rcc_ex.c
  • RCC_PLL_GetFreqDomain_SAI() : stm32wbxx_ll_rcc.c
  • RCC_PLL_GetFreqDomain_SYS() : stm32wbxx_ll_rcc.c
  • RCC_PLL_NONE : stm32wbxx_hal_rcc.h
  • RCC_PLL_OFF : stm32wbxx_hal_rcc.h
  • RCC_PLL_ON : stm32wbxx_hal_rcc.h
  • RCC_PLL_OSCSOURCE_CONFIG : stm32wbxx_hal_rcc.c
  • RCC_PLL_RNGCLK : stm32wbxx_hal_rcc.h
  • RCC_PLL_SAI1CLK : stm32wbxx_hal_rcc.h
  • RCC_PLL_SYSCLK : stm32wbxx_hal_rcc.h
  • RCC_PLL_USBCLK : stm32wbxx_hal_rcc.h
  • RCC_PLLM_DIV1 : stm32wbxx_hal_rcc.h
  • RCC_PLLM_DIV2 : stm32wbxx_hal_rcc.h
  • RCC_PLLM_DIV3 : stm32wbxx_hal_rcc.h
  • RCC_PLLM_DIV4 : stm32wbxx_hal_rcc.h
  • RCC_PLLM_DIV5 : stm32wbxx_hal_rcc.h
  • RCC_PLLM_DIV6 : stm32wbxx_hal_rcc.h
  • RCC_PLLM_DIV7 : stm32wbxx_hal_rcc.h
  • RCC_PLLM_DIV8 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV10 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV11 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV12 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV13 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV14 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV15 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV16 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV17 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV18 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV19 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV2 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV20 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV21 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV22 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV23 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV24 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV25 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV26 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV27 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV28 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV29 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV3 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV30 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV31 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV32 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV4 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV5 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV6 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV7 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV8 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV9 : stm32wbxx_hal_rcc.h
  • RCC_PLLQ_DIV2 : stm32wbxx_hal_rcc.h
  • RCC_PLLQ_DIV3 : stm32wbxx_hal_rcc.h
  • RCC_PLLQ_DIV4 : stm32wbxx_hal_rcc.h
  • RCC_PLLQ_DIV5 : stm32wbxx_hal_rcc.h
  • RCC_PLLQ_DIV6 : stm32wbxx_hal_rcc.h
  • RCC_PLLQ_DIV7 : stm32wbxx_hal_rcc.h
  • RCC_PLLQ_DIV8 : stm32wbxx_hal_rcc.h
  • RCC_PLLR_DIV2 : stm32wbxx_hal_rcc.h
  • RCC_PLLR_DIV3 : stm32wbxx_hal_rcc.h
  • RCC_PLLR_DIV4 : stm32wbxx_hal_rcc.h
  • RCC_PLLR_DIV5 : stm32wbxx_hal_rcc.h
  • RCC_PLLR_DIV6 : stm32wbxx_hal_rcc.h
  • RCC_PLLR_DIV7 : stm32wbxx_hal_rcc.h
  • RCC_PLLR_DIV8 : stm32wbxx_hal_rcc.h
  • RCC_PLLSAI1_ADCCLK : stm32wbxx_hal_rcc.h
  • RCC_PLLSAI1_GetFreqDomain_48M() : stm32wbxx_ll_rcc.c
  • RCC_PLLSAI1_GetFreqDomain_ADC() : stm32wbxx_ll_rcc.c
  • RCC_PLLSAI1_GetFreqDomain_P() : stm32wbxx_hal_rcc_ex.c
  • RCC_PLLSAI1_GetFreqDomain_Q() : stm32wbxx_hal_rcc_ex.c
  • RCC_PLLSAI1_GetFreqDomain_R() : stm32wbxx_hal_rcc_ex.c
  • RCC_PLLSAI1_GetFreqDomain_SAI() : stm32wbxx_ll_rcc.c
  • RCC_PLLSAI1_SAI1CLK : stm32wbxx_hal_rcc.h
  • RCC_PLLSAI1_USBCLK : stm32wbxx_hal_rcc.h
  • RCC_PLLSOURCE_HSE : stm32wbxx_hal_rcc.h
  • RCC_PLLSOURCE_HSI : stm32wbxx_hal_rcc.h
  • RCC_PLLSOURCE_MSI : stm32wbxx_hal_rcc.h
  • RCC_PLLSOURCE_NONE : stm32wbxx_hal_rcc.h
  • RCC_RFWKPCLKSOURCE_HSE_DIV1024 : stm32wbxx_hal_rcc_ex.h
  • RCC_RFWKPCLKSOURCE_LSE : stm32wbxx_hal_rcc_ex.h
  • RCC_RFWKPCLKSOURCE_LSI : stm32wbxx_hal_rcc_ex.h
  • RCC_RFWKPCLKSOURCE_NONE : stm32wbxx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_CLK48 : stm32wbxx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_HSI48 : stm32wbxx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_LSE : stm32wbxx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_LSI : stm32wbxx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_MSI : stm32wbxx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_PLL : stm32wbxx_hal_rcc_ex.h
  • RCC_RTCCLKSOURCE_HSE_DIV32 : stm32wbxx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSE : stm32wbxx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSI : stm32wbxx_hal_rcc.h
  • RCC_RTCCLKSOURCE_NONE : stm32wbxx_hal_rcc.h
  • RCC_SAI1CLKSOURCE_HSI : stm32wbxx_hal_rcc_ex.h
  • RCC_SAI1CLKSOURCE_PIN : stm32wbxx_hal_rcc_ex.h
  • RCC_SAI1CLKSOURCE_PLL : stm32wbxx_hal_rcc_ex.h
  • RCC_SAI1CLKSOURCE_PLLSAI1 : stm32wbxx_hal_rcc_ex.h
  • RCC_SetFlashLatency() : stm32wbxx_hal_rcc.c
  • RCC_SetFlashLatencyFromMSIRange() : stm32wbxx_hal_rcc.c
  • RCC_SMPSCLKDIV_RANGE0 : stm32wbxx_hal_rcc_ex.h
  • RCC_SMPSCLKDIV_RANGE1 : stm32wbxx_hal_rcc_ex.h
  • RCC_SMPSCLKDIV_RANGE2 : stm32wbxx_hal_rcc_ex.h
  • RCC_SMPSCLKDIV_RANGE3 : stm32wbxx_hal_rcc_ex.h
  • RCC_SMPSCLKSOURCE_HSE : stm32wbxx_hal_rcc_ex.h
  • RCC_SMPSCLKSOURCE_HSI : stm32wbxx_hal_rcc_ex.h
  • RCC_SMPSCLKSOURCE_MSI : stm32wbxx_hal_rcc_ex.h
  • RCC_SMPSCLKSOURCE_STATUS_HSE : stm32wbxx_hal_rcc_ex.h
  • RCC_SMPSCLKSOURCE_STATUS_HSI : stm32wbxx_hal_rcc_ex.h
  • RCC_SMPSCLKSOURCE_STATUS_MSI : stm32wbxx_hal_rcc_ex.h
  • RCC_STOP_WAKEUPCLOCK_HSI : stm32wbxx_hal_rcc.h
  • RCC_STOP_WAKEUPCLOCK_MSI : stm32wbxx_hal_rcc.h
  • RCC_SYSCLK_DIV1 : stm32wbxx_hal_rcc.h
  • RCC_SYSCLK_DIV10 : stm32wbxx_hal_rcc.h
  • RCC_SYSCLK_DIV128 : stm32wbxx_hal_rcc.h
  • RCC_SYSCLK_DIV16 : stm32wbxx_hal_rcc.h
  • RCC_SYSCLK_DIV2 : stm32wbxx_hal_rcc.h
  • RCC_SYSCLK_DIV256 : stm32wbxx_hal_rcc.h
  • RCC_SYSCLK_DIV3 : stm32wbxx_hal_rcc.h
  • RCC_SYSCLK_DIV32 : stm32wbxx_hal_rcc.h
  • RCC_SYSCLK_DIV4 : stm32wbxx_hal_rcc.h
  • RCC_SYSCLK_DIV5 : stm32wbxx_hal_rcc.h
  • RCC_SYSCLK_DIV512 : stm32wbxx_hal_rcc.h
  • RCC_SYSCLK_DIV6 : stm32wbxx_hal_rcc.h
  • RCC_SYSCLK_DIV64 : stm32wbxx_hal_rcc.h
  • RCC_SYSCLK_DIV8 : stm32wbxx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSE : stm32wbxx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSI : stm32wbxx_hal_rcc.h
  • RCC_SYSCLKSOURCE_MSI : stm32wbxx_hal_rcc.h
  • RCC_SYSCLKSOURCE_PLLCLK : stm32wbxx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_HSE : stm32wbxx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_HSI : stm32wbxx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_MSI : stm32wbxx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_PLLCLK : stm32wbxx_hal_rcc.h
  • RCC_USART1CLKSOURCE_HSI : stm32wbxx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_LSE : stm32wbxx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_PCLK2 : stm32wbxx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_SYSCLK : stm32wbxx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_HSI48 : stm32wbxx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_MSI : stm32wbxx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_PLL : stm32wbxx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_PLLSAI1 : stm32wbxx_hal_rcc_ex.h
  • RCCEx_PLLSAI1_ConfigNP() : stm32wbxx_hal_rcc_ex.c
  • RCCEx_PLLSAI1_ConfigNQ() : stm32wbxx_hal_rcc_ex.c
  • RCCEx_PLLSAI1_ConfigNR() : stm32wbxx_hal_rcc_ex.c
  • RISING_EDGE : stm32wbxx_hal_gpio.c
  • RNG_CED_DISABLE : stm32wbxx_hal_rng.h
  • RNG_CED_ENABLE : stm32wbxx_hal_rng.h
  • RNG_FLAG_CECS : stm32wbxx_hal_rng.h
  • RNG_FLAG_DRDY : stm32wbxx_hal_rng.h
  • RNG_FLAG_SECS : stm32wbxx_hal_rng.h
  • RNG_HandleTypeDef : stm32wbxx_hal_rng.h
  • RNG_IT_CEI : stm32wbxx_hal_rng.h
  • RNG_IT_DRDY : stm32wbxx_hal_rng.h
  • RNG_IT_SEI : stm32wbxx_hal_rng.h
  • RNG_TIMEOUT_VALUE : stm32wbxx_hal_rng.c
  • RTC_ALARM_A : stm32wbxx_hal_rtc.h
  • RTC_ALARM_B : stm32wbxx_hal_rtc.h
  • RTC_ALARMDATEWEEKDAYSEL_DATE : stm32wbxx_hal_rtc.h
  • RTC_ALARMDATEWEEKDAYSEL_WEEKDAY : stm32wbxx_hal_rtc.h
  • RTC_ALARMMASK_ALL : stm32wbxx_hal_rtc.h
  • RTC_ALARMMASK_DATEWEEKDAY : stm32wbxx_hal_rtc.h
  • RTC_ALARMMASK_HOURS : stm32wbxx_hal_rtc.h
  • RTC_ALARMMASK_MINUTES : stm32wbxx_hal_rtc.h
  • RTC_ALARMMASK_NONE : stm32wbxx_hal_rtc.h
  • RTC_ALARMMASK_SECONDS : stm32wbxx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_ALL : stm32wbxx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_NONE : stm32wbxx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14 : stm32wbxx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_1 : stm32wbxx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_10 : stm32wbxx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_11 : stm32wbxx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_12 : stm32wbxx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_13 : stm32wbxx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_2 : stm32wbxx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_3 : stm32wbxx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_4 : stm32wbxx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_5 : stm32wbxx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_6 : stm32wbxx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_7 : stm32wbxx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_8 : stm32wbxx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_9 : stm32wbxx_hal_rtc.h
  • RTC_ALL_TAMPER_INTERRUPT : stm32wbxx_hal_rtc_ex.h
  • RTC_ASYNCH_PRESC_DEFAULT : stm32wbxx_ll_rtc.c
  • RTC_Bcd2ToByte() : stm32wbxx_hal_rtc.c
  • RTC_BKP_DR0 : stm32wbxx_hal_rtc_ex.h
  • RTC_BKP_DR1 : stm32wbxx_hal_rtc_ex.h
  • RTC_BKP_DR10 : stm32wbxx_hal_rtc_ex.h
  • RTC_BKP_DR11 : stm32wbxx_hal_rtc_ex.h
  • RTC_BKP_DR12 : stm32wbxx_hal_rtc_ex.h
  • RTC_BKP_DR13 : stm32wbxx_hal_rtc_ex.h
  • RTC_BKP_DR14 : stm32wbxx_hal_rtc_ex.h
  • RTC_BKP_DR15 : stm32wbxx_hal_rtc_ex.h
  • RTC_BKP_DR16 : stm32wbxx_hal_rtc_ex.h
  • RTC_BKP_DR17 : stm32wbxx_hal_rtc_ex.h
  • RTC_BKP_DR18 : stm32wbxx_hal_rtc_ex.h
  • RTC_BKP_DR19 : stm32wbxx_hal_rtc_ex.h
  • RTC_BKP_DR2 : stm32wbxx_hal_rtc_ex.h
  • RTC_BKP_DR3 : stm32wbxx_hal_rtc_ex.h
  • RTC_BKP_DR4 : stm32wbxx_hal_rtc_ex.h
  • RTC_BKP_DR5 : stm32wbxx_hal_rtc_ex.h
  • RTC_BKP_DR6 : stm32wbxx_hal_rtc_ex.h
  • RTC_BKP_DR7 : stm32wbxx_hal_rtc_ex.h
  • RTC_BKP_DR8 : stm32wbxx_hal_rtc_ex.h
  • RTC_BKP_DR9 : stm32wbxx_hal_rtc_ex.h
  • RTC_ByteToBcd2() : stm32wbxx_hal_rtc.c
  • RTC_CALIBOUTPUT_1HZ : stm32wbxx_hal_rtc_ex.h
  • RTC_CALIBOUTPUT_512HZ : stm32wbxx_hal_rtc_ex.h
  • RTC_DAYLIGHTSAVING_ADD1H : stm32wbxx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_NONE : stm32wbxx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_SUB1H : stm32wbxx_hal_rtc.h
  • RTC_DR_RESERVED_MASK : stm32wbxx_hal_rtc.h
  • RTC_EnterInitMode() : stm32wbxx_hal_rtc.c
  • RTC_EXTI_LINE_ALARM_EVENT : stm32wbxx_hal_rtc.h
  • RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT : stm32wbxx_hal_rtc_ex.h
  • RTC_EXTI_LINE_WAKEUPTIMER_EVENT : stm32wbxx_hal_rtc_ex.h
  • RTC_FLAG_ALRAF : stm32wbxx_hal_rtc.h
  • RTC_FLAG_ALRAWF : stm32wbxx_hal_rtc.h
  • RTC_FLAG_ALRBF : stm32wbxx_hal_rtc.h
  • RTC_FLAG_ALRBWF : stm32wbxx_hal_rtc.h
  • RTC_FLAG_INITF : stm32wbxx_hal_rtc.h
  • RTC_FLAG_INITS : stm32wbxx_hal_rtc.h
  • RTC_FLAG_ITSF : stm32wbxx_hal_rtc.h
  • RTC_FLAG_RECALPF : stm32wbxx_hal_rtc.h
  • RTC_FLAG_RSF : stm32wbxx_hal_rtc.h
  • RTC_FLAG_SHPF : stm32wbxx_hal_rtc.h
  • RTC_FLAG_TAMP1F : stm32wbxx_hal_rtc.h
  • RTC_FLAG_TAMP2F : stm32wbxx_hal_rtc.h
  • RTC_FLAG_TAMP3F : stm32wbxx_hal_rtc_ex.h
  • RTC_FLAG_TSF : stm32wbxx_hal_rtc.h
  • RTC_FLAG_TSOVF : stm32wbxx_hal_rtc.h
  • RTC_FLAG_WUTF : stm32wbxx_hal_rtc.h
  • RTC_FLAG_WUTWF : stm32wbxx_hal_rtc.h
  • RTC_FLAGS_MASK : stm32wbxx_hal_rtc_ex.h
  • RTC_FORMAT_BCD : stm32wbxx_hal_rtc.h
  • RTC_FORMAT_BIN : stm32wbxx_hal_rtc.h
  • RTC_HandleTypeDef : stm32wbxx_hal_rtc.h
  • RTC_HOURFORMAT12_AM : stm32wbxx_hal_rtc.h
  • RTC_HOURFORMAT12_PM : stm32wbxx_hal_rtc.h
  • RTC_HOURFORMAT_12 : stm32wbxx_hal_rtc.h
  • RTC_HOURFORMAT_24 : stm32wbxx_hal_rtc.h
  • RTC_INIT_MASK : stm32wbxx_hal_rtc.h
  • RTC_INITMODE_TIMEOUT : stm32wbxx_ll_rtc.c
  • RTC_IT_ALRA : stm32wbxx_hal_rtc.h
  • RTC_IT_ALRB : stm32wbxx_hal_rtc.h
  • RTC_IT_TAMP : stm32wbxx_hal_rtc.h
  • RTC_IT_TAMP1 : stm32wbxx_hal_rtc.h
  • RTC_IT_TAMP2 : stm32wbxx_hal_rtc.h
  • RTC_IT_TAMP3 : stm32wbxx_hal_rtc_ex.h
  • RTC_IT_TS : stm32wbxx_hal_rtc.h
  • RTC_IT_WUT : stm32wbxx_hal_rtc.h
  • RTC_MONTH_APRIL : stm32wbxx_hal_rtc.h
  • RTC_MONTH_AUGUST : stm32wbxx_hal_rtc.h
  • RTC_MONTH_DECEMBER : stm32wbxx_hal_rtc.h
  • RTC_MONTH_FEBRUARY : stm32wbxx_hal_rtc.h
  • RTC_MONTH_JANUARY : stm32wbxx_hal_rtc.h
  • RTC_MONTH_JULY : stm32wbxx_hal_rtc.h
  • RTC_MONTH_JUNE : stm32wbxx_hal_rtc.h
  • RTC_MONTH_MARCH : stm32wbxx_hal_rtc.h
  • RTC_MONTH_MAY : stm32wbxx_hal_rtc.h
  • RTC_MONTH_NOVEMBER : stm32wbxx_hal_rtc.h
  • RTC_MONTH_OCTOBER : stm32wbxx_hal_rtc.h
  • RTC_MONTH_SEPTEMBER : stm32wbxx_hal_rtc.h
  • RTC_OFFSET_DAY : stm32wbxx_ll_rtc.h
  • RTC_OFFSET_HOUR : stm32wbxx_ll_rtc.h
  • RTC_OFFSET_MINUTE : stm32wbxx_ll_rtc.h
  • RTC_OFFSET_MONTH : stm32wbxx_ll_rtc.h
  • RTC_OFFSET_WEEKDAY : stm32wbxx_ll_rtc.h
  • RTC_OUTPUT_ALARMA : stm32wbxx_hal_rtc_ex.h
  • RTC_OUTPUT_ALARMB : stm32wbxx_hal_rtc_ex.h
  • RTC_OUTPUT_DISABLE : stm32wbxx_hal_rtc_ex.h
  • RTC_OUTPUT_POLARITY_HIGH : stm32wbxx_hal_rtc.h
  • RTC_OUTPUT_POLARITY_LOW : stm32wbxx_hal_rtc.h
  • RTC_OUTPUT_REMAP_NONE : stm32wbxx_hal_rtc.h
  • RTC_OUTPUT_REMAP_POS1 : stm32wbxx_hal_rtc.h
  • RTC_OUTPUT_TYPE_OPENDRAIN : stm32wbxx_hal_rtc.h
  • RTC_OUTPUT_TYPE_PUSHPULL : stm32wbxx_hal_rtc.h
  • RTC_OUTPUT_WAKEUP : stm32wbxx_hal_rtc_ex.h
  • RTC_RSF_MASK : stm32wbxx_hal_rtc.h
  • RTC_SHIFTADD1S_RESET : stm32wbxx_hal_rtc_ex.h
  • RTC_SHIFTADD1S_SET : stm32wbxx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_16SEC : stm32wbxx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_32SEC : stm32wbxx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_8SEC : stm32wbxx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PLUSPULSES_RESET : stm32wbxx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PLUSPULSES_SET : stm32wbxx_hal_rtc_ex.h
  • RTC_STOREOPERATION_RESET : stm32wbxx_hal_rtc.h
  • RTC_STOREOPERATION_SET : stm32wbxx_hal_rtc.h
  • RTC_SYNCH_PRESC_DEFAULT : stm32wbxx_ll_rtc.c
  • RTC_SYNCHRO_TIMEOUT : stm32wbxx_ll_rtc.c
  • RTC_TAMPCR_MASK : stm32wbxx_hal_rtc_ex.c
  • RTC_TAMPCR_TAMPXE : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPCR_TAMPXIE : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPER1_INTERRUPT : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPER2_INTERRUPT : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPER3_INTERRUPT : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPER_1 : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPER_2 : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPER_3 : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPER_ERASE_BACKUP_DISABLE : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPER_ERASE_BACKUP_ENABLE : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPER_PULLUP_DISABLE : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPER_PULLUP_ENABLE : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_2SAMPLE : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_4SAMPLE : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_8SAMPLE : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_DISABLE : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERMASK_FLAG_DISABLE : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERMASK_FLAG_ENABLE : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_1RTCCLK : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_2RTCCLK : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_4RTCCLK : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_8RTCCLK : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_FALLINGEDGE : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_HIGHLEVEL : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_LOWLEVEL : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_RISINGEDGE : stm32wbxx_hal_rtc_ex.h
  • RTC_TIMEOUT_VALUE : stm32wbxx_hal_rtc.h
  • RTC_TIMESTAMPEDGE_FALLING : stm32wbxx_hal_rtc_ex.h
  • RTC_TIMESTAMPEDGE_RISING : stm32wbxx_hal_rtc_ex.h
  • RTC_TIMESTAMPONTAMPERDETECTION_DISABLE : stm32wbxx_hal_rtc_ex.h
  • RTC_TIMESTAMPONTAMPERDETECTION_ENABLE : stm32wbxx_hal_rtc_ex.h
  • RTC_TIMESTAMPPIN_DEFAULT : stm32wbxx_hal_rtc_ex.h
  • RTC_TR_RESERVED_MASK : stm32wbxx_hal_rtc.h
  • RTC_WAKEUPCLOCK_CK_SPRE_16BITS : stm32wbxx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_CK_SPRE_17BITS : stm32wbxx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV16 : stm32wbxx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV2 : stm32wbxx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV4 : stm32wbxx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV8 : stm32wbxx_hal_rtc_ex.h
  • RTC_WEEKDAY_FRIDAY : stm32wbxx_hal_rtc.h
  • RTC_WEEKDAY_MONDAY : stm32wbxx_hal_rtc.h
  • RTC_WEEKDAY_SATURDAY : stm32wbxx_hal_rtc.h
  • RTC_WEEKDAY_SUNDAY : stm32wbxx_hal_rtc.h
  • RTC_WEEKDAY_THURSDAY : stm32wbxx_hal_rtc.h
  • RTC_WEEKDAY_TUESDAY : stm32wbxx_hal_rtc.h
  • RTC_WEEKDAY_WEDNESDAY : stm32wbxx_hal_rtc.h
  • RTC_WRITE_PROTECTION_DISABLE : stm32wbxx_ll_rtc.h
  • RTC_WRITE_PROTECTION_ENABLE_1 : stm32wbxx_ll_rtc.h
  • RTC_WRITE_PROTECTION_ENABLE_2 : stm32wbxx_ll_rtc.h
  • RX_FIFO_DEPTH : stm32wbxx_hal_uart_ex.c , stm32wbxx_hal_smartcard_ex.c , stm32wbxx_hal_usart_ex.c
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

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  • Variables
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- s -

  • SAI_AC97_PROTOCOL : stm32wbxx_hal_sai.h
  • SAI_ALAW_1CPL_COMPANDING : stm32wbxx_hal_sai.h
  • SAI_ALAW_2CPL_COMPANDING : stm32wbxx_hal_sai.h
  • SAI_ASYNCHRONOUS : stm32wbxx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_11K : stm32wbxx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_16K : stm32wbxx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_192K : stm32wbxx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_22K : stm32wbxx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_32K : stm32wbxx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_44K : stm32wbxx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_48K : stm32wbxx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_8K : stm32wbxx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_96K : stm32wbxx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_MCKDIV : stm32wbxx_hal_sai.h
  • SAI_CLOCKSTROBING_FALLINGEDGE : stm32wbxx_hal_sai.h
  • SAI_CLOCKSTROBING_RISINGEDGE : stm32wbxx_hal_sai.h
  • SAI_DATASIZE_10 : stm32wbxx_hal_sai.h
  • SAI_DATASIZE_16 : stm32wbxx_hal_sai.h
  • SAI_DATASIZE_20 : stm32wbxx_hal_sai.h
  • SAI_DATASIZE_24 : stm32wbxx_hal_sai.h
  • SAI_DATASIZE_32 : stm32wbxx_hal_sai.h
  • SAI_DATASIZE_8 : stm32wbxx_hal_sai.h
  • SAI_DEFAULT_TIMEOUT : stm32wbxx_hal_sai.c
  • SAI_Disable() : stm32wbxx_hal_sai.c
  • SAI_DMAAbort() : stm32wbxx_hal_sai.c
  • SAI_DMAError() : stm32wbxx_hal_sai.c
  • SAI_DMARxCplt() : stm32wbxx_hal_sai.c
  • SAI_DMARxHalfCplt() : stm32wbxx_hal_sai.c
  • SAI_DMATxCplt() : stm32wbxx_hal_sai.c
  • SAI_DMATxHalfCplt() : stm32wbxx_hal_sai.c
  • SAI_FIFOSTATUS_1QUARTERFULL : stm32wbxx_hal_sai.h
  • SAI_FIFOSTATUS_3QUARTERFULL : stm32wbxx_hal_sai.h
  • SAI_FIFOSTATUS_EMPTY : stm32wbxx_hal_sai.h
  • SAI_FIFOSTATUS_FULL : stm32wbxx_hal_sai.h
  • SAI_FIFOSTATUS_HALFFULL : stm32wbxx_hal_sai.h
  • SAI_FIFOSTATUS_LESS1QUARTERFULL : stm32wbxx_hal_sai.h
  • SAI_FIFOTHRESHOLD_1QF : stm32wbxx_hal_sai.h
  • SAI_FIFOTHRESHOLD_3QF : stm32wbxx_hal_sai.h
  • SAI_FIFOTHRESHOLD_EMPTY : stm32wbxx_hal_sai.h
  • SAI_FIFOTHRESHOLD_FULL : stm32wbxx_hal_sai.h
  • SAI_FIFOTHRESHOLD_HF : stm32wbxx_hal_sai.h
  • SAI_FillFifo() : stm32wbxx_hal_sai.c
  • SAI_FIRSTBIT_LSB : stm32wbxx_hal_sai.h
  • SAI_FIRSTBIT_MSB : stm32wbxx_hal_sai.h
  • SAI_FLAG_AFSDET : stm32wbxx_hal_sai.h
  • SAI_FLAG_CNRDY : stm32wbxx_hal_sai.h
  • SAI_FLAG_FREQ : stm32wbxx_hal_sai.h
  • SAI_FLAG_LFSDET : stm32wbxx_hal_sai.h
  • SAI_FLAG_MUTEDET : stm32wbxx_hal_sai.h
  • SAI_FLAG_OVRUDR : stm32wbxx_hal_sai.h
  • SAI_FLAG_WCKCFG : stm32wbxx_hal_sai.h
  • SAI_FREE_PROTOCOL : stm32wbxx_hal_sai.h
  • SAI_FS_ACTIVE_HIGH : stm32wbxx_hal_sai.h
  • SAI_FS_ACTIVE_LOW : stm32wbxx_hal_sai.h
  • SAI_FS_BEFOREFIRSTBIT : stm32wbxx_hal_sai.h
  • SAI_FS_CHANNEL_IDENTIFICATION : stm32wbxx_hal_sai.h
  • SAI_FS_FIRSTBIT : stm32wbxx_hal_sai.h
  • SAI_FS_STARTFRAME : stm32wbxx_hal_sai.h
  • SAI_HandleTypeDef : stm32wbxx_hal_sai.h
  • SAI_I2S_LSBJUSTIFIED : stm32wbxx_hal_sai.h
  • SAI_I2S_MSBJUSTIFIED : stm32wbxx_hal_sai.h
  • SAI_I2S_STANDARD : stm32wbxx_hal_sai.h
  • SAI_InitI2S() : stm32wbxx_hal_sai.c
  • SAI_InitPCM() : stm32wbxx_hal_sai.c
  • SAI_InterruptFlag() : stm32wbxx_hal_sai.c
  • SAI_IT_AFSDET : stm32wbxx_hal_sai.h
  • SAI_IT_CNRDY : stm32wbxx_hal_sai.h
  • SAI_IT_FREQ : stm32wbxx_hal_sai.h
  • SAI_IT_LFSDET : stm32wbxx_hal_sai.h
  • SAI_IT_MUTEDET : stm32wbxx_hal_sai.h
  • SAI_IT_OVRUDR : stm32wbxx_hal_sai.h
  • SAI_IT_WCKCFG : stm32wbxx_hal_sai.h
  • SAI_LAST_SENT_VALUE : stm32wbxx_hal_sai.h
  • SAI_LONG_TIMEOUT : stm32wbxx_hal_sai.c
  • SAI_MASTERDIVIDER_DISABLE : stm32wbxx_hal_sai.h
  • SAI_MASTERDIVIDER_ENABLE : stm32wbxx_hal_sai.h
  • SAI_MCK_OUTPUT_DISABLE : stm32wbxx_hal_sai.h
  • SAI_MCK_OUTPUT_ENABLE : stm32wbxx_hal_sai.h
  • SAI_MCK_OVERSAMPLING_DISABLE : stm32wbxx_hal_sai.h
  • SAI_MCK_OVERSAMPLING_ENABLE : stm32wbxx_hal_sai.h
  • SAI_MODE_DMA : stm32wbxx_hal_sai.c
  • SAI_MODE_IT : stm32wbxx_hal_sai.c
  • SAI_MODEMASTER_RX : stm32wbxx_hal_sai.h
  • SAI_MODEMASTER_TX : stm32wbxx_hal_sai.h
  • SAI_MODESLAVE_RX : stm32wbxx_hal_sai.h
  • SAI_MODESLAVE_TX : stm32wbxx_hal_sai.h
  • SAI_ModeTypedef : stm32wbxx_hal_sai.c
  • SAI_MONOMODE : stm32wbxx_hal_sai.h
  • SAI_NOCOMPANDING : stm32wbxx_hal_sai.h
  • SAI_OUTPUT_NOTRELEASED : stm32wbxx_hal_sai.h
  • SAI_OUTPUT_RELEASED : stm32wbxx_hal_sai.h
  • SAI_OUTPUTDRIVE_DISABLE : stm32wbxx_hal_sai.h
  • SAI_OUTPUTDRIVE_ENABLE : stm32wbxx_hal_sai.h
  • SAI_PCM_LONG : stm32wbxx_hal_sai.h
  • SAI_PCM_SHORT : stm32wbxx_hal_sai.h
  • SAI_PDM_CLOCK1_ENABLE : stm32wbxx_hal_sai.h
  • SAI_PDM_CLOCK2_ENABLE : stm32wbxx_hal_sai.h
  • SAI_PDM_DELAY_MASK : stm32wbxx_hal_sai_ex.c
  • SAI_PDM_DELAY_OFFSET : stm32wbxx_hal_sai_ex.c
  • SAI_PDM_RIGHT_DELAY_OFFSET : stm32wbxx_hal_sai_ex.c
  • SAI_PROTOCOL_DATASIZE_16BIT : stm32wbxx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_16BITEXTENDED : stm32wbxx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_24BIT : stm32wbxx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_32BIT : stm32wbxx_hal_sai.h
  • SAI_Receive_IT16Bit() : stm32wbxx_hal_sai.c
  • SAI_Receive_IT32Bit() : stm32wbxx_hal_sai.c
  • SAI_Receive_IT8Bit() : stm32wbxx_hal_sai.c
  • SAI_SLOT_NOTACTIVE : stm32wbxx_hal_sai.h
  • SAI_SLOTACTIVE_0 : stm32wbxx_hal_sai.h
  • SAI_SLOTACTIVE_1 : stm32wbxx_hal_sai.h
  • SAI_SLOTACTIVE_10 : stm32wbxx_hal_sai.h
  • SAI_SLOTACTIVE_11 : stm32wbxx_hal_sai.h
  • SAI_SLOTACTIVE_12 : stm32wbxx_hal_sai.h
  • SAI_SLOTACTIVE_13 : stm32wbxx_hal_sai.h
  • SAI_SLOTACTIVE_14 : stm32wbxx_hal_sai.h
  • SAI_SLOTACTIVE_15 : stm32wbxx_hal_sai.h
  • SAI_SLOTACTIVE_2 : stm32wbxx_hal_sai.h
  • SAI_SLOTACTIVE_3 : stm32wbxx_hal_sai.h
  • SAI_SLOTACTIVE_4 : stm32wbxx_hal_sai.h
  • SAI_SLOTACTIVE_5 : stm32wbxx_hal_sai.h
  • SAI_SLOTACTIVE_6 : stm32wbxx_hal_sai.h
  • SAI_SLOTACTIVE_7 : stm32wbxx_hal_sai.h
  • SAI_SLOTACTIVE_8 : stm32wbxx_hal_sai.h
  • SAI_SLOTACTIVE_9 : stm32wbxx_hal_sai.h
  • SAI_SLOTACTIVE_ALL : stm32wbxx_hal_sai.h
  • SAI_SLOTSIZE_16B : stm32wbxx_hal_sai.h
  • SAI_SLOTSIZE_32B : stm32wbxx_hal_sai.h
  • SAI_SLOTSIZE_DATASIZE : stm32wbxx_hal_sai.h
  • SAI_SPDIF_PROTOCOL : stm32wbxx_hal_sai.h
  • SAI_STEREOMODE : stm32wbxx_hal_sai.h
  • SAI_SYNCEXT_DISABLE : stm32wbxx_hal_sai.h
  • SAI_SYNCEXT_OUTBLOCKA_ENABLE : stm32wbxx_hal_sai.h
  • SAI_SYNCEXT_OUTBLOCKB_ENABLE : stm32wbxx_hal_sai.h
  • SAI_SYNCHRONOUS : stm32wbxx_hal_sai.h
  • SAI_SYNCHRONOUS_EXT_SAI1 : stm32wbxx_hal_sai.h
  • SAI_SYNCHRONOUS_EXT_SAI2 : stm32wbxx_hal_sai.h
  • SAI_Transmit_IT16Bit() : stm32wbxx_hal_sai.c
  • SAI_Transmit_IT32Bit() : stm32wbxx_hal_sai.c
  • SAI_Transmit_IT8Bit() : stm32wbxx_hal_sai.c
  • SAI_ULAW_1CPL_COMPANDING : stm32wbxx_hal_sai.h
  • SAI_ULAW_2CPL_COMPANDING : stm32wbxx_hal_sai.h
  • SAI_ZERO_VALUE : stm32wbxx_hal_sai.h
  • SAIcallback : stm32wbxx_hal_sai.h
  • SHIFT_TAB_CCxP : stm32wbxx_ll_tim.h
  • SHIFT_TAB_ICxx : stm32wbxx_ll_tim.h
  • SHIFT_TAB_OCxx : stm32wbxx_ll_tim.h
  • SHIFT_TAB_OISx : stm32wbxx_ll_tim.h
  • SlaveAddr_MSK : stm32wbxx_hal_i2c.c
  • SlaveAddr_SHIFT : stm32wbxx_hal_i2c.c
  • SMARTCARD_ADVFEATURE_DATAINV_DISABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DATAINV_ENABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DATAINVERT_INIT : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR : stm32wbxx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR : stm32wbxx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_INIT : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_NO_INIT : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_OVERRUN_DISABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_OVERRUN_ENABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINV_DISABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINV_ENABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINVERT_INIT : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_SWAP_DISABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_SWAP_ENABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_SWAP_INIT : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_TXCOMPLETION : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_TXINV_DISABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_TXINV_ENABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_TXINVERT_INIT : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_AdvFeatureConfig() : stm32wbxx_hal_smartcard.c
  • SMARTCARD_CheckIdleState() : stm32wbxx_hal_smartcard.c
  • SMARTCARD_CLEAR_EOBF : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_FEF : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_IDLEF : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_NEF : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_OREF : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_PEF : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_RTOF : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_TCBGTF : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_TCF : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_TXFECF : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_CLOCKSOURCE_HSI : stm32wbxx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_LSE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_PCLK2 : stm32wbxx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_SYSCLK : stm32wbxx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_UNDEFINED : stm32wbxx_hal_smartcard.h
  • SMARTCARD_ClockSourceTypeDef : stm32wbxx_hal_smartcard.h
  • SMARTCARD_CR_MASK : stm32wbxx_hal_smartcard.h
  • SMARTCARD_CR_POS : stm32wbxx_hal_smartcard.h
  • SMARTCARD_DMAAbortOnError() : stm32wbxx_hal_smartcard.c
  • SMARTCARD_DMAError() : stm32wbxx_hal_smartcard.c
  • SMARTCARD_DMAReceiveCplt() : stm32wbxx_hal_smartcard.c
  • SMARTCARD_DMARxAbortCallback() : stm32wbxx_hal_smartcard.c
  • SMARTCARD_DMARxOnlyAbortCallback() : stm32wbxx_hal_smartcard.c
  • SMARTCARD_DMATransmitCplt() : stm32wbxx_hal_smartcard.c
  • SMARTCARD_DMATxAbortCallback() : stm32wbxx_hal_smartcard.c
  • SMARTCARD_DMATxOnlyAbortCallback() : stm32wbxx_hal_smartcard.c
  • SMARTCARD_EndRxTransfer() : stm32wbxx_hal_smartcard.c
  • SMARTCARD_EndTransmit_IT() : stm32wbxx_hal_smartcard.c
  • SMARTCARD_EndTxTransfer() : stm32wbxx_hal_smartcard.c
  • SMARTCARD_FIFOMODE_DISABLE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FIFOMODE_ENABLE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_BUSY : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_EOBF : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_FE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_IDLE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_NE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_ORE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_PE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_REACK : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RTOF : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXFF : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXFNE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXFT : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXNE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TC : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TCBGT : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TEACK : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXFE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXFNF : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXFT : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_GETCLOCKSOURCE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_HandleTypeDef : stm32wbxx_hal_smartcard.h
  • SMARTCARD_InitCallbacksToDefault() : stm32wbxx_hal_smartcard.c
  • SMARTCARD_ISR_MASK : stm32wbxx_hal_smartcard.h
  • SMARTCARD_ISR_POS : stm32wbxx_hal_smartcard.h
  • SMARTCARD_IT_EOB : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_IT_ERR : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_IT_FE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_IT_IDLE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_IT_MASK : stm32wbxx_hal_smartcard.h
  • SMARTCARD_IT_NE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_IT_ORE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_IT_PE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_IT_RTO : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXFF : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXFNE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXFT : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXNE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_IT_TC : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_IT_TCBGT : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXFE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXFNF : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXFT : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_LASTBIT_DISABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_LASTBIT_ENABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_MODE_RX : stm32wbxx_hal_smartcard.h
  • SMARTCARD_MODE_TX : stm32wbxx_hal_smartcard.h
  • SMARTCARD_MODE_TX_RX : stm32wbxx_hal_smartcard.h
  • SMARTCARD_NACK_DISABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_NACK_ENABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_ONE_BIT_SAMPLE_DISABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_ONE_BIT_SAMPLE_ENABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_PARITY_EVEN : stm32wbxx_hal_smartcard.h
  • SMARTCARD_PARITY_ODD : stm32wbxx_hal_smartcard.h
  • SMARTCARD_PHASE_1EDGE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_PHASE_2EDGE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_POLARITY_HIGH : stm32wbxx_hal_smartcard.h
  • SMARTCARD_POLARITY_LOW : stm32wbxx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV1 : stm32wbxx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV10 : stm32wbxx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV12 : stm32wbxx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV128 : stm32wbxx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV16 : stm32wbxx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV2 : stm32wbxx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV256 : stm32wbxx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV32 : stm32wbxx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV4 : stm32wbxx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV6 : stm32wbxx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV64 : stm32wbxx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV8 : stm32wbxx_hal_smartcard.h
  • SMARTCARD_RXDATA_FLUSH_REQUEST : stm32wbxx_hal_smartcard.h
  • SMARTCARD_RXFIFO_THRESHOLD_1_2 : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_1_4 : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_1_8 : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_3_4 : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_7_8 : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_8_8 : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_RxISR() : stm32wbxx_hal_smartcard.c
  • SMARTCARD_RxISR_FIFOEN() : stm32wbxx_hal_smartcard.c
  • SMARTCARD_SetConfig() : stm32wbxx_hal_smartcard.c
  • SMARTCARD_STOPBITS_0_5 : stm32wbxx_hal_smartcard.h
  • SMARTCARD_STOPBITS_1_5 : stm32wbxx_hal_smartcard.h
  • SMARTCARD_TC : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_TCBGT : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_TEACK_REACK_TIMEOUT : stm32wbxx_hal_smartcard.c
  • SMARTCARD_TIMEOUT_DISABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_TIMEOUT_ENABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_TRANSMISSION_COMPLETION_FLAG : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_TRANSMISSION_COMPLETION_SETTING : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_TXDATA_FLUSH_REQUEST : stm32wbxx_hal_smartcard.h
  • SMARTCARD_TXFIFO_THRESHOLD_1_2 : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_1_4 : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_1_8 : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_3_4 : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_7_8 : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_8_8 : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_TxISR() : stm32wbxx_hal_smartcard.c
  • SMARTCARD_TxISR_FIFOEN() : stm32wbxx_hal_smartcard.c
  • SMARTCARD_WaitOnFlagUntilTimeout() : stm32wbxx_hal_smartcard.c
  • SMARTCARD_WORDLENGTH_9B : stm32wbxx_hal_smartcard.h
  • SMARTCARDEx_SetNbDataToProcess() : stm32wbxx_hal_smartcard_ex.c
  • SMBUS_ADDRESSINGMODE_10BIT : stm32wbxx_hal_smbus.h
  • SMBUS_ADDRESSINGMODE_7BIT : stm32wbxx_hal_smbus.h
  • SMBUS_ANALOGFILTER_DISABLE : stm32wbxx_hal_smbus.h
  • SMBUS_ANALOGFILTER_ENABLE : stm32wbxx_hal_smbus.h
  • SMBUS_AUTOEND_MODE : stm32wbxx_hal_smbus.h
  • SMBUS_CHECK_FLAG : stm32wbxx_hal_smbus.h
  • SMBUS_CHECK_IT_SOURCE : stm32wbxx_hal_smbus.h
  • SMBUS_ConvertOtherXferOptions() : stm32wbxx_hal_smbus.c
  • SMBUS_Disable_IRQ() : stm32wbxx_hal_smbus.c
  • SMBUS_DUALADDRESS_DISABLE : stm32wbxx_hal_smbus.h
  • SMBUS_DUALADDRESS_ENABLE : stm32wbxx_hal_smbus.h
  • SMBUS_Enable_IRQ() : stm32wbxx_hal_smbus.c
  • SMBUS_FIRST_AND_LAST_FRAME_NO_PEC : stm32wbxx_hal_smbus.h
  • SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC : stm32wbxx_hal_smbus.h
  • SMBUS_FIRST_FRAME : stm32wbxx_hal_smbus.h
  • SMBUS_FLAG_ADDR : stm32wbxx_hal_smbus.h
  • SMBUS_FLAG_AF : stm32wbxx_hal_smbus.h
  • SMBUS_FLAG_ALERT : stm32wbxx_hal_smbus.h
  • SMBUS_FLAG_ARLO : stm32wbxx_hal_smbus.h
  • SMBUS_FLAG_BERR : stm32wbxx_hal_smbus.h
  • SMBUS_FLAG_BUSY : stm32wbxx_hal_smbus.h
  • SMBUS_FLAG_DIR : stm32wbxx_hal_smbus.h
  • SMBUS_FLAG_MASK : stm32wbxx_hal_smbus.h
  • SMBUS_FLAG_OVR : stm32wbxx_hal_smbus.h
  • SMBUS_FLAG_PECERR : stm32wbxx_hal_smbus.h
  • SMBUS_FLAG_RXNE : stm32wbxx_hal_smbus.h
  • SMBUS_FLAG_STOPF : stm32wbxx_hal_smbus.h
  • SMBUS_FLAG_TC : stm32wbxx_hal_smbus.h
  • SMBUS_FLAG_TCR : stm32wbxx_hal_smbus.h
  • SMBUS_FLAG_TIMEOUT : stm32wbxx_hal_smbus.h
  • SMBUS_FLAG_TXE : stm32wbxx_hal_smbus.h
  • SMBUS_FLAG_TXIS : stm32wbxx_hal_smbus.h
  • SMBUS_GENERALCALL_DISABLE : stm32wbxx_hal_smbus.h
  • SMBUS_GENERALCALL_ENABLE : stm32wbxx_hal_smbus.h
  • SMBUS_GENERATE_START : stm32wbxx_hal_smbus.h
  • SMBUS_GENERATE_START_READ : stm32wbxx_hal_smbus.h
  • SMBUS_GENERATE_START_WRITE : stm32wbxx_hal_smbus.h
  • SMBUS_GENERATE_STOP : stm32wbxx_hal_smbus.h
  • SMBUS_GET_ADDR_MATCH : stm32wbxx_hal_smbus.h
  • SMBUS_GET_ALERT_ENABLED : stm32wbxx_hal_smbus.h
  • SMBUS_GET_DIR : stm32wbxx_hal_smbus.h
  • SMBUS_GET_PEC_MODE : stm32wbxx_hal_smbus.h
  • SMBUS_GET_STOP_MODE : stm32wbxx_hal_smbus.h
  • SMBUS_HandleTypeDef : stm32wbxx_hal_smbus.h
  • SMBUS_IT_ADDR : stm32wbxx_hal_smbus.h
  • SMBUS_IT_ADDRI : stm32wbxx_hal_smbus.h
  • SMBUS_IT_ALERT : stm32wbxx_hal_smbus.h
  • SMBUS_IT_ERRI : stm32wbxx_hal_smbus.h
  • SMBUS_IT_NACKI : stm32wbxx_hal_smbus.h
  • SMBUS_IT_RX : stm32wbxx_hal_smbus.h
  • SMBUS_IT_RXI : stm32wbxx_hal_smbus.h
  • SMBUS_IT_STOPI : stm32wbxx_hal_smbus.h
  • SMBUS_IT_TCI : stm32wbxx_hal_smbus.h
  • SMBUS_IT_TX : stm32wbxx_hal_smbus.h
  • SMBUS_IT_TXI : stm32wbxx_hal_smbus.h
  • SMBUS_ITErrorHandler() : stm32wbxx_hal_smbus.c
  • SMBUS_LAST_FRAME_NO_PEC : stm32wbxx_hal_smbus.h
  • SMBUS_LAST_FRAME_WITH_PEC : stm32wbxx_hal_smbus.h
  • SMBUS_Master_ISR() : stm32wbxx_hal_smbus.c
  • SMBUS_NEXT_FRAME : stm32wbxx_hal_smbus.h
  • SMBUS_NO_STARTSTOP : stm32wbxx_hal_smbus.h
  • SMBUS_NOSTRETCH_DISABLE : stm32wbxx_hal_smbus.h
  • SMBUS_NOSTRETCH_ENABLE : stm32wbxx_hal_smbus.h
  • SMBUS_OA2_MASK01 : stm32wbxx_hal_smbus.h
  • SMBUS_OA2_MASK02 : stm32wbxx_hal_smbus.h
  • SMBUS_OA2_MASK03 : stm32wbxx_hal_smbus.h
  • SMBUS_OA2_MASK04 : stm32wbxx_hal_smbus.h
  • SMBUS_OA2_MASK05 : stm32wbxx_hal_smbus.h
  • SMBUS_OA2_MASK06 : stm32wbxx_hal_smbus.h
  • SMBUS_OA2_MASK07 : stm32wbxx_hal_smbus.h
  • SMBUS_OA2_NOMASK : stm32wbxx_hal_smbus.h
  • SMBUS_OTHER_AND_LAST_FRAME_NO_PEC : stm32wbxx_hal_smbus.h
  • SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC : stm32wbxx_hal_smbus.h
  • SMBUS_OTHER_FRAME_NO_PEC : stm32wbxx_hal_smbus.h
  • SMBUS_OTHER_FRAME_WITH_PEC : stm32wbxx_hal_smbus.h
  • SMBUS_PEC_DISABLE : stm32wbxx_hal_smbus.h
  • SMBUS_PEC_ENABLE : stm32wbxx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_HOST : stm32wbxx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE : stm32wbxx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP : stm32wbxx_hal_smbus.h
  • SMBUS_RELOAD_MODE : stm32wbxx_hal_smbus.h
  • SMBUS_RESET_CR1 : stm32wbxx_hal_smbus.h
  • SMBUS_RESET_CR2 : stm32wbxx_hal_smbus.h
  • SMBUS_SENDPEC_MODE : stm32wbxx_hal_smbus.h
  • SMBUS_Slave_ISR() : stm32wbxx_hal_smbus.c
  • SMBUS_SOFTEND_MODE : stm32wbxx_hal_smbus.h
  • SMBUS_TransferConfig() : stm32wbxx_hal_smbus.c
  • SMBUS_WaitOnFlagUntilTimeout() : stm32wbxx_hal_smbus.c
  • SMPS_VOLTAGE_BASE_MV : stm32wbxx_ll_pwr.h
  • SMPS_VOLTAGE_CAL : stm32wbxx_ll_pwr.h
  • SMPS_VOLTAGE_CAL_ADDR : stm32wbxx_ll_pwr.h
  • SMPS_VOLTAGE_CAL_POS : stm32wbxx_ll_pwr.h
  • SMPS_VOLTAGE_CAL_VOLTAGE_MV : stm32wbxx_ll_pwr.h
  • SMPS_VOLTAGE_STEP_MV : stm32wbxx_ll_pwr.h
  • SPI_1LINE_RX : stm32wbxx_hal_spi.h
  • SPI_1LINE_TX : stm32wbxx_hal_spi.h
  • SPI_2linesRxISR_16BIT() : stm32wbxx_hal_spi.c
  • SPI_2linesRxISR_16BITCRC() : stm32wbxx_hal_spi.c
  • SPI_2linesRxISR_8BIT() : stm32wbxx_hal_spi.c
  • SPI_2linesRxISR_8BITCRC() : stm32wbxx_hal_spi.c
  • SPI_2linesTxISR_16BIT() : stm32wbxx_hal_spi.c
  • SPI_2linesTxISR_8BIT() : stm32wbxx_hal_spi.c
  • SPI_AbortRx_ISR() : stm32wbxx_hal_spi.c
  • SPI_AbortTx_ISR() : stm32wbxx_hal_spi.c
  • SPI_BAUDRATEPRESCALER_128 : stm32wbxx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_16 : stm32wbxx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_2 : stm32wbxx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_256 : stm32wbxx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_32 : stm32wbxx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_4 : stm32wbxx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_64 : stm32wbxx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_8 : stm32wbxx_hal_spi.h
  • SPI_CHECK_FLAG : stm32wbxx_hal_spi.h
  • SPI_CHECK_IT_SOURCE : stm32wbxx_hal_spi.h
  • SPI_CloseRx_ISR() : stm32wbxx_hal_spi.c
  • SPI_CloseRxTx_ISR() : stm32wbxx_hal_spi.c
  • SPI_CloseTx_ISR() : stm32wbxx_hal_spi.c
  • SPI_CR1_CLEAR_MASK : stm32wbxx_ll_spi.c
  • SPI_CRC_LENGTH_16BIT : stm32wbxx_hal_spi.h
  • SPI_CRC_LENGTH_8BIT : stm32wbxx_hal_spi.h
  • SPI_CRC_LENGTH_DATASIZE : stm32wbxx_hal_spi.h
  • SPI_CRCCALCULATION_DISABLE : stm32wbxx_hal_spi.h
  • SPI_CRCCALCULATION_ENABLE : stm32wbxx_hal_spi.h
  • SPI_DATASIZE_10BIT : stm32wbxx_hal_spi.h
  • SPI_DATASIZE_11BIT : stm32wbxx_hal_spi.h
  • SPI_DATASIZE_12BIT : stm32wbxx_hal_spi.h
  • SPI_DATASIZE_13BIT : stm32wbxx_hal_spi.h
  • SPI_DATASIZE_14BIT : stm32wbxx_hal_spi.h
  • SPI_DATASIZE_15BIT : stm32wbxx_hal_spi.h
  • SPI_DATASIZE_16BIT : stm32wbxx_hal_spi.h
  • SPI_DATASIZE_4BIT : stm32wbxx_hal_spi.h
  • SPI_DATASIZE_5BIT : stm32wbxx_hal_spi.h
  • SPI_DATASIZE_6BIT : stm32wbxx_hal_spi.h
  • SPI_DATASIZE_7BIT : stm32wbxx_hal_spi.h
  • SPI_DATASIZE_8BIT : stm32wbxx_hal_spi.h
  • SPI_DATASIZE_9BIT : stm32wbxx_hal_spi.h
  • SPI_DEFAULT_TIMEOUT : stm32wbxx_hal_spi.c
  • SPI_DIRECTION_1LINE : stm32wbxx_hal_spi.h
  • SPI_DIRECTION_2LINES : stm32wbxx_hal_spi.h
  • SPI_DIRECTION_2LINES_RXONLY : stm32wbxx_hal_spi.h
  • SPI_DMAAbortOnError() : stm32wbxx_hal_spi.c
  • SPI_DMAError() : stm32wbxx_hal_spi.c
  • SPI_DMAHalfReceiveCplt() : stm32wbxx_hal_spi.c
  • SPI_DMAHalfTransmitCplt() : stm32wbxx_hal_spi.c
  • SPI_DMAHalfTransmitReceiveCplt() : stm32wbxx_hal_spi.c
  • SPI_DMAReceiveCplt() : stm32wbxx_hal_spi.c
  • SPI_DMARxAbortCallback() : stm32wbxx_hal_spi.c
  • SPI_DMATransmitCplt() : stm32wbxx_hal_spi.c
  • SPI_DMATransmitReceiveCplt() : stm32wbxx_hal_spi.c
  • SPI_DMATxAbortCallback() : stm32wbxx_hal_spi.c
  • SPI_EndRxTransaction() : stm32wbxx_hal_spi.c
  • SPI_EndRxTxTransaction() : stm32wbxx_hal_spi.c
  • SPI_FIFO_SIZE : stm32wbxx_hal_spi_ex.c
  • SPI_FIRSTBIT_LSB : stm32wbxx_hal_spi.h
  • SPI_FIRSTBIT_MSB : stm32wbxx_hal_spi.h
  • SPI_FLAG_BSY : stm32wbxx_hal_spi.h
  • SPI_FLAG_CRCERR : stm32wbxx_hal_spi.h
  • SPI_FLAG_FRE : stm32wbxx_hal_spi.h
  • SPI_FLAG_FRLVL : stm32wbxx_hal_spi.h
  • SPI_FLAG_FTLVL : stm32wbxx_hal_spi.h
  • SPI_FLAG_MASK : stm32wbxx_hal_spi.h
  • SPI_FLAG_MODF : stm32wbxx_hal_spi.h
  • SPI_FLAG_OVR : stm32wbxx_hal_spi.h
  • SPI_FLAG_RXNE : stm32wbxx_hal_spi.h
  • SPI_FLAG_TXE : stm32wbxx_hal_spi.h
  • SPI_FRLVL_EMPTY : stm32wbxx_hal_spi.h
  • SPI_FRLVL_FULL : stm32wbxx_hal_spi.h
  • SPI_FRLVL_HALF_FULL : stm32wbxx_hal_spi.h
  • SPI_FRLVL_QUARTER_FULL : stm32wbxx_hal_spi.h
  • SPI_FTLVL_EMPTY : stm32wbxx_hal_spi.h
  • SPI_FTLVL_FULL : stm32wbxx_hal_spi.h
  • SPI_FTLVL_HALF_FULL : stm32wbxx_hal_spi.h
  • SPI_FTLVL_QUARTER_FULL : stm32wbxx_hal_spi.h
  • SPI_HandleTypeDef : stm32wbxx_hal_spi.h
  • SPI_IT_ERR : stm32wbxx_hal_spi.h
  • SPI_IT_RXNE : stm32wbxx_hal_spi.h
  • SPI_IT_TXE : stm32wbxx_hal_spi.h
  • SPI_MODE_MASTER : stm32wbxx_hal_spi.h
  • SPI_MODE_SLAVE : stm32wbxx_hal_spi.h
  • SPI_NSS_HARD_INPUT : stm32wbxx_hal_spi.h
  • SPI_NSS_HARD_OUTPUT : stm32wbxx_hal_spi.h
  • SPI_NSS_PULSE_DISABLE : stm32wbxx_hal_spi.h
  • SPI_NSS_PULSE_ENABLE : stm32wbxx_hal_spi.h
  • SPI_NSS_SOFT : stm32wbxx_hal_spi.h
  • SPI_PHASE_1EDGE : stm32wbxx_hal_spi.h
  • SPI_PHASE_2EDGE : stm32wbxx_hal_spi.h
  • SPI_POLARITY_HIGH : stm32wbxx_hal_spi.h
  • SPI_POLARITY_LOW : stm32wbxx_hal_spi.h
  • SPI_RESET_CRC : stm32wbxx_hal_spi.h
  • SPI_RXFIFO_THRESHOLD : stm32wbxx_hal_spi.h
  • SPI_RXFIFO_THRESHOLD_HF : stm32wbxx_hal_spi.h
  • SPI_RXFIFO_THRESHOLD_QF : stm32wbxx_hal_spi.h
  • SPI_RxISR_16BIT() : stm32wbxx_hal_spi.c
  • SPI_RxISR_16BITCRC() : stm32wbxx_hal_spi.c
  • SPI_RxISR_8BIT() : stm32wbxx_hal_spi.c
  • SPI_RxISR_8BITCRC() : stm32wbxx_hal_spi.c
  • SPI_TIMODE_DISABLE : stm32wbxx_hal_spi.h
  • SPI_TIMODE_ENABLE : stm32wbxx_hal_spi.h
  • SPI_TxISR_16BIT() : stm32wbxx_hal_spi.c
  • SPI_TxISR_8BIT() : stm32wbxx_hal_spi.c
  • SPI_WaitFifoStateUntilTimeout() : stm32wbxx_hal_spi.c
  • SPI_WaitFlagStateUntilTimeout() : stm32wbxx_hal_spi.c
  • SRAM2A_FULL_UNSECURE : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_0 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_1 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_10 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_11 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_12 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_13 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_14 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_15 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_16 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_17 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_18 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_19 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_2 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_20 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_21 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_22 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_23 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_24 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_25 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_26 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_27 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_28 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_29 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_3 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_30 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_31 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_4 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_5 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_6 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_7 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_8 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_9 : stm32wbxx_hal_flash.h
  • SRAM2B_FULL_UNSECURE : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_0 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_1 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_10 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_11 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_12 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_13 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_14 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_15 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_16 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_17 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_18 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_19 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_2 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_20 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_21 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_22 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_23 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_24 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_25 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_26 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_27 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_28 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_29 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_3 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_30 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_31 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_4 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_5 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_6 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_7 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_8 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_9 : stm32wbxx_hal_flash.h
  • SRAM_SECURE_PAGE_GRANULARITY : stm32wbxx_hal_flash.h
  • SRAM_SECURE_PAGE_GRANULARITY_OFFSET : stm32wbxx_hal_flash.h
  • SYSCFG_BOOT_MAINFLASH : stm32wbxx_hal.h
  • SYSCFG_BOOT_QUADSPI : stm32wbxx_hal.h
  • SYSCFG_BOOT_SRAM : stm32wbxx_hal.h
  • SYSCFG_BOOT_SYSTEMFLASH : stm32wbxx_hal.h
  • SYSCFG_FASTMODEPLUS_PB6 : stm32wbxx_hal.h
  • SYSCFG_FASTMODEPLUS_PB7 : stm32wbxx_hal.h
  • SYSCFG_FASTMODEPLUS_PB8 : stm32wbxx_hal.h
  • SYSCFG_FASTMODEPLUS_PB9 : stm32wbxx_hal.h
  • SYSCFG_FLAG_SRAM2_BUSY : stm32wbxx_hal.h
  • SYSCFG_FLAG_SRAM2_PE : stm32wbxx_hal.h
  • SYSCFG_IT_FPU_DZC : stm32wbxx_hal.h
  • SYSCFG_IT_FPU_IDC : stm32wbxx_hal.h
  • SYSCFG_IT_FPU_IOC : stm32wbxx_hal.h
  • SYSCFG_IT_FPU_IXC : stm32wbxx_hal.h
  • SYSCFG_IT_FPU_OFC : stm32wbxx_hal.h
  • SYSCFG_IT_FPU_UFC : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE0 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE1 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE10 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE11 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE12 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE13 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE14 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE15 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE16 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE17 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE18 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE19 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE2 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE20 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE21 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE22 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE23 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE24 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE25 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE26 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE27 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE28 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE29 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE3 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE30 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE31 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE32 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE33 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE34 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE35 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE36 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE37 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE38 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE39 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE4 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE40 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE41 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE42 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE43 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE44 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE45 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE46 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE47 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE48 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE49 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE5 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE50 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE51 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE52 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE53 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE54 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE55 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE56 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE57 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE58 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE59 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE6 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE60 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE61 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE62 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE63 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE7 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE8 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE9 : stm32wbxx_hal.h
  • SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE : stm32wbxx_hal.h
  • SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE : stm32wbxx_hal.h
  • SYSCFG_VREFBUF_VOLTAGE_SCALE0 : stm32wbxx_hal.h
  • SYSCFG_VREFBUF_VOLTAGE_SCALE1 : stm32wbxx_hal.h
  • SYSTEM_IN_SECURE_MODE : stm32wbxx_hal_flash.h
  • SYSTEM_NOT_IN_SECURE_MODE : stm32wbxx_hal_flash.h
  • SYSTICK_CLKSOURCE_HCLK : stm32wbxx_hal_cortex.h
  • SYSTICK_CLKSOURCE_HCLK_DIV8 : stm32wbxx_hal_cortex.h
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- t -

  • TEMPSENSOR_CAL1_ADDR : stm32wbxx_ll_adc.h
  • TEMPSENSOR_CAL1_TEMP : stm32wbxx_ll_adc.h
  • TEMPSENSOR_CAL2_ADDR : stm32wbxx_ll_adc.h
  • TEMPSENSOR_CAL2_TEMP : stm32wbxx_ll_adc.h
  • TEMPSENSOR_CAL_VREFANALOG : stm32wbxx_ll_adc.h
  • TICK_INT_PRIORITY : stm32wbxx_hal_conf.h
  • TIM16_OR_RMP_MASK : stm32wbxx_ll_tim.h
  • TIM17_OR_RMP_MASK : stm32wbxx_ll_tim.h
  • TIM1_OR_RMP_MASK : stm32wbxx_ll_tim.h
  • TIM2_OR_RMP_MASK : stm32wbxx_ll_tim.h
  • TIM_AUTOMATICOUTPUT_DISABLE : stm32wbxx_hal_tim.h
  • TIM_AUTOMATICOUTPUT_ENABLE : stm32wbxx_hal_tim.h
  • TIM_AUTORELOAD_PRELOAD_DISABLE : stm32wbxx_hal_tim.h
  • TIM_AUTORELOAD_PRELOAD_ENABLE : stm32wbxx_hal_tim.h
  • TIM_Base_SetConfig() : stm32wbxx_hal_tim.c
  • TIM_BREAK2_DISABLE : stm32wbxx_hal_tim.h
  • TIM_BREAK2_ENABLE : stm32wbxx_hal_tim.h
  • TIM_BREAK2POLARITY_HIGH : stm32wbxx_hal_tim.h
  • TIM_BREAK2POLARITY_LOW : stm32wbxx_hal_tim.h
  • TIM_BREAK_DISABLE : stm32wbxx_hal_tim.h
  • TIM_BREAK_ENABLE : stm32wbxx_hal_tim.h
  • TIM_BREAK_SYSTEM_ECC : stm32wbxx_hal_tim.h
  • TIM_BREAK_SYSTEM_LOCKUP : stm32wbxx_hal_tim.h
  • TIM_BREAK_SYSTEM_PVD : stm32wbxx_hal_tim.h
  • TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR : stm32wbxx_hal_tim.h
  • TIM_BREAKINPUT_BRK : stm32wbxx_hal_tim_ex.h
  • TIM_BREAKINPUT_BRK2 : stm32wbxx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_BKIN : stm32wbxx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_COMP1 : stm32wbxx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_COMP2 : stm32wbxx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_DISABLE : stm32wbxx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_ENABLE : stm32wbxx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_POLARITY_HIGH : stm32wbxx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_POLARITY_LOW : stm32wbxx_hal_tim_ex.h
  • TIM_BREAKPOLARITY_HIGH : stm32wbxx_hal_tim.h
  • TIM_BREAKPOLARITY_LOW : stm32wbxx_hal_tim.h
  • TIM_CALC_DTS : stm32wbxx_ll_tim.h
  • TIM_CCER_CCxE_MASK : stm32wbxx_hal_tim.h
  • TIM_CCER_CCxNE_MASK : stm32wbxx_hal_tim.h
  • TIM_CCx_DISABLE : stm32wbxx_hal_tim.h
  • TIM_CCx_ENABLE : stm32wbxx_hal_tim.h
  • TIM_CCxChannelCmd() : stm32wbxx_hal_tim.c
  • TIM_CCxN_DISABLE : stm32wbxx_hal_tim.h
  • TIM_CCxN_ENABLE : stm32wbxx_hal_tim.h
  • TIM_CCxNChannelCmd() : stm32wbxx_hal_tim_ex.c
  • TIM_CHANNEL_1 : stm32wbxx_hal_tim.h
  • TIM_CHANNEL_2 : stm32wbxx_hal_tim.h
  • TIM_CHANNEL_3 : stm32wbxx_hal_tim.h
  • TIM_CHANNEL_4 : stm32wbxx_hal_tim.h
  • TIM_CHANNEL_5 : stm32wbxx_hal_tim.h
  • TIM_CHANNEL_6 : stm32wbxx_hal_tim.h
  • TIM_CHANNEL_ALL : stm32wbxx_hal_tim.h
  • TIM_CLEARINPUTPOLARITY_INVERTED : stm32wbxx_hal_tim.h
  • TIM_CLEARINPUTPOLARITY_NONINVERTED : stm32wbxx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV1 : stm32wbxx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV2 : stm32wbxx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV4 : stm32wbxx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV8 : stm32wbxx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_COMP1 : stm32wbxx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_COMP2 : stm32wbxx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_ETR : stm32wbxx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_NONE : stm32wbxx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV1 : stm32wbxx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV2 : stm32wbxx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV4 : stm32wbxx_hal_tim.h
  • TIM_CLOCKPOLARITY_BOTHEDGE : stm32wbxx_hal_tim.h
  • TIM_CLOCKPOLARITY_FALLING : stm32wbxx_hal_tim.h
  • TIM_CLOCKPOLARITY_INVERTED : stm32wbxx_hal_tim.h
  • TIM_CLOCKPOLARITY_NONINVERTED : stm32wbxx_hal_tim.h
  • TIM_CLOCKPOLARITY_RISING : stm32wbxx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV1 : stm32wbxx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV2 : stm32wbxx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV4 : stm32wbxx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV8 : stm32wbxx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE1 : stm32wbxx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE2 : stm32wbxx_hal_tim.h
  • TIM_CLOCKSOURCE_INTERNAL : stm32wbxx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR0 : stm32wbxx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR1 : stm32wbxx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR2 : stm32wbxx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR3 : stm32wbxx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1 : stm32wbxx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1ED : stm32wbxx_hal_tim.h
  • TIM_CLOCKSOURCE_TI2 : stm32wbxx_hal_tim.h
  • TIM_COMMUTATION_SOFTWARE : stm32wbxx_hal_tim.h
  • TIM_COMMUTATION_TRGI : stm32wbxx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED1 : stm32wbxx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED2 : stm32wbxx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED3 : stm32wbxx_hal_tim.h
  • TIM_COUNTERMODE_DOWN : stm32wbxx_hal_tim.h
  • TIM_COUNTERMODE_UP : stm32wbxx_hal_tim.h
  • TIM_DMA_CC1 : stm32wbxx_hal_tim.h
  • TIM_DMA_CC2 : stm32wbxx_hal_tim.h
  • TIM_DMA_CC3 : stm32wbxx_hal_tim.h
  • TIM_DMA_CC4 : stm32wbxx_hal_tim.h
  • TIM_DMA_COM : stm32wbxx_hal_tim.h
  • TIM_DMA_ID_CC1 : stm32wbxx_hal_tim.h
  • TIM_DMA_ID_CC2 : stm32wbxx_hal_tim.h
  • TIM_DMA_ID_CC3 : stm32wbxx_hal_tim.h
  • TIM_DMA_ID_CC4 : stm32wbxx_hal_tim.h
  • TIM_DMA_ID_COMMUTATION : stm32wbxx_hal_tim.h
  • TIM_DMA_ID_TRIGGER : stm32wbxx_hal_tim.h
  • TIM_DMA_ID_UPDATE : stm32wbxx_hal_tim.h
  • TIM_DMA_TRIGGER : stm32wbxx_hal_tim.h
  • TIM_DMA_UPDATE : stm32wbxx_hal_tim.h
  • TIM_DMABASE_AF1 : stm32wbxx_hal_tim.h
  • TIM_DMABASE_AF2 : stm32wbxx_hal_tim.h
  • TIM_DMABASE_ARR : stm32wbxx_hal_tim.h
  • TIM_DMABASE_BDTR : stm32wbxx_hal_tim.h
  • TIM_DMABASE_CCER : stm32wbxx_hal_tim.h
  • TIM_DMABASE_CCMR1 : stm32wbxx_hal_tim.h
  • TIM_DMABASE_CCMR2 : stm32wbxx_hal_tim.h
  • TIM_DMABASE_CCMR3 : stm32wbxx_hal_tim.h
  • TIM_DMABASE_CCR1 : stm32wbxx_hal_tim.h
  • TIM_DMABASE_CCR2 : stm32wbxx_hal_tim.h
  • TIM_DMABASE_CCR3 : stm32wbxx_hal_tim.h
  • TIM_DMABASE_CCR4 : stm32wbxx_hal_tim.h
  • TIM_DMABASE_CCR5 : stm32wbxx_hal_tim.h
  • TIM_DMABASE_CCR6 : stm32wbxx_hal_tim.h
  • TIM_DMABASE_CNT : stm32wbxx_hal_tim.h
  • TIM_DMABASE_CR1 : stm32wbxx_hal_tim.h
  • TIM_DMABASE_CR2 : stm32wbxx_hal_tim.h
  • TIM_DMABASE_DCR : stm32wbxx_hal_tim.h
  • TIM_DMABASE_DIER : stm32wbxx_hal_tim.h
  • TIM_DMABASE_DMAR : stm32wbxx_hal_tim.h
  • TIM_DMABASE_EGR : stm32wbxx_hal_tim.h
  • TIM_DMABASE_OR : stm32wbxx_hal_tim.h
  • TIM_DMABASE_PSC : stm32wbxx_hal_tim.h
  • TIM_DMABASE_RCR : stm32wbxx_hal_tim.h
  • TIM_DMABASE_SMCR : stm32wbxx_hal_tim.h
  • TIM_DMABASE_SR : stm32wbxx_hal_tim.h
  • TIM_DMABURSTLENGTH_10TRANSFERS : stm32wbxx_hal_tim.h
  • TIM_DMABURSTLENGTH_11TRANSFERS : stm32wbxx_hal_tim.h
  • TIM_DMABURSTLENGTH_12TRANSFERS : stm32wbxx_hal_tim.h
  • TIM_DMABURSTLENGTH_13TRANSFERS : stm32wbxx_hal_tim.h
  • TIM_DMABURSTLENGTH_14TRANSFERS : stm32wbxx_hal_tim.h
  • TIM_DMABURSTLENGTH_15TRANSFERS : stm32wbxx_hal_tim.h
  • TIM_DMABURSTLENGTH_16TRANSFERS : stm32wbxx_hal_tim.h
  • TIM_DMABURSTLENGTH_17TRANSFERS : stm32wbxx_hal_tim.h
  • TIM_DMABURSTLENGTH_18TRANSFERS : stm32wbxx_hal_tim.h
  • TIM_DMABURSTLENGTH_1TRANSFER : stm32wbxx_hal_tim.h
  • TIM_DMABURSTLENGTH_2TRANSFERS : stm32wbxx_hal_tim.h
  • TIM_DMABURSTLENGTH_3TRANSFERS : stm32wbxx_hal_tim.h
  • TIM_DMABURSTLENGTH_4TRANSFERS : stm32wbxx_hal_tim.h
  • TIM_DMABURSTLENGTH_5TRANSFERS : stm32wbxx_hal_tim.h
  • TIM_DMABURSTLENGTH_6TRANSFERS : stm32wbxx_hal_tim.h
  • TIM_DMABURSTLENGTH_7TRANSFERS : stm32wbxx_hal_tim.h
  • TIM_DMABURSTLENGTH_8TRANSFERS : stm32wbxx_hal_tim.h
  • TIM_DMABURSTLENGTH_9TRANSFERS : stm32wbxx_hal_tim.h
  • TIM_DMACaptureCplt() : stm32wbxx_hal_tim.c
  • TIM_DMACaptureHalfCplt() : stm32wbxx_hal_tim.c
  • TIM_DMADelayPulseCplt() : stm32wbxx_hal_tim.c
  • TIM_DMADelayPulseHalfCplt() : stm32wbxx_hal_tim.c
  • TIM_DMAError() : stm32wbxx_hal_tim.c
  • TIM_DMAPeriodElapsedCplt() : stm32wbxx_hal_tim.c
  • TIM_DMAPeriodElapsedHalfCplt() : stm32wbxx_hal_tim.c
  • TIM_DMATriggerCplt() : stm32wbxx_hal_tim.c
  • TIM_DMATriggerHalfCplt() : stm32wbxx_hal_tim.c
  • TIM_ENCODERINPUTPOLARITY_FALLING : stm32wbxx_hal_tim.h
  • TIM_ENCODERINPUTPOLARITY_RISING : stm32wbxx_hal_tim.h
  • TIM_ENCODERMODE_TI1 : stm32wbxx_hal_tim.h
  • TIM_ENCODERMODE_TI12 : stm32wbxx_hal_tim.h
  • TIM_ENCODERMODE_TI2 : stm32wbxx_hal_tim.h
  • TIM_ETR_SetConfig() : stm32wbxx_hal_tim.c
  • TIM_ETRPOLARITY_INVERTED : stm32wbxx_hal_tim.h
  • TIM_ETRPOLARITY_NONINVERTED : stm32wbxx_hal_tim.h
  • TIM_ETRPRESCALER_DIV1 : stm32wbxx_hal_tim.h
  • TIM_ETRPRESCALER_DIV2 : stm32wbxx_hal_tim.h
  • TIM_ETRPRESCALER_DIV4 : stm32wbxx_hal_tim.h
  • TIM_ETRPRESCALER_DIV8 : stm32wbxx_hal_tim.h
  • TIM_EVENTSOURCE_BREAK : stm32wbxx_hal_tim.h
  • TIM_EVENTSOURCE_BREAK2 : stm32wbxx_hal_tim.h
  • TIM_EVENTSOURCE_CC1 : stm32wbxx_hal_tim.h
  • TIM_EVENTSOURCE_CC2 : stm32wbxx_hal_tim.h
  • TIM_EVENTSOURCE_CC3 : stm32wbxx_hal_tim.h
  • TIM_EVENTSOURCE_CC4 : stm32wbxx_hal_tim.h
  • TIM_EVENTSOURCE_COM : stm32wbxx_hal_tim.h
  • TIM_EVENTSOURCE_TRIGGER : stm32wbxx_hal_tim.h
  • TIM_EVENTSOURCE_UPDATE : stm32wbxx_hal_tim.h
  • TIM_FLAG_BREAK : stm32wbxx_hal_tim.h
  • TIM_FLAG_BREAK2 : stm32wbxx_hal_tim.h
  • TIM_FLAG_CC1 : stm32wbxx_hal_tim.h
  • TIM_FLAG_CC1OF : stm32wbxx_hal_tim.h
  • TIM_FLAG_CC2 : stm32wbxx_hal_tim.h
  • TIM_FLAG_CC2OF : stm32wbxx_hal_tim.h
  • TIM_FLAG_CC3 : stm32wbxx_hal_tim.h
  • TIM_FLAG_CC3OF : stm32wbxx_hal_tim.h
  • TIM_FLAG_CC4 : stm32wbxx_hal_tim.h
  • TIM_FLAG_CC4OF : stm32wbxx_hal_tim.h
  • TIM_FLAG_CC5 : stm32wbxx_hal_tim.h
  • TIM_FLAG_CC6 : stm32wbxx_hal_tim.h
  • TIM_FLAG_COM : stm32wbxx_hal_tim.h
  • TIM_FLAG_SYSTEM_BREAK : stm32wbxx_hal_tim.h
  • TIM_FLAG_TRIGGER : stm32wbxx_hal_tim.h
  • TIM_FLAG_UPDATE : stm32wbxx_hal_tim.h
  • TIM_GET_CHANNEL_INDEX : stm32wbxx_ll_tim.h
  • TIM_GET_OR_MASK : stm32wbxx_hal_tim_ex.c
  • TIM_GROUPCH5_NONE : stm32wbxx_hal_tim.h
  • TIM_GROUPCH5_OC1REFC : stm32wbxx_hal_tim.h
  • TIM_GROUPCH5_OC2REFC : stm32wbxx_hal_tim.h
  • TIM_GROUPCH5_OC3REFC : stm32wbxx_hal_tim.h
  • TIM_HandleTypeDef : stm32wbxx_hal_tim.h
  • TIM_ICPOLARITY_BOTHEDGE : stm32wbxx_hal_tim.h
  • TIM_ICPOLARITY_FALLING : stm32wbxx_hal_tim.h
  • TIM_ICPOLARITY_RISING : stm32wbxx_hal_tim.h
  • TIM_ICPSC_DIV1 : stm32wbxx_hal_tim.h
  • TIM_ICPSC_DIV2 : stm32wbxx_hal_tim.h
  • TIM_ICPSC_DIV4 : stm32wbxx_hal_tim.h
  • TIM_ICPSC_DIV8 : stm32wbxx_hal_tim.h
  • TIM_ICSELECTION_DIRECTTI : stm32wbxx_hal_tim.h
  • TIM_ICSELECTION_INDIRECTTI : stm32wbxx_hal_tim.h
  • TIM_ICSELECTION_TRC : stm32wbxx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_BOTHEDGE : stm32wbxx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_FALLING : stm32wbxx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_RISING : stm32wbxx_hal_tim.h
  • TIM_IT_BREAK : stm32wbxx_hal_tim.h
  • TIM_IT_CC1 : stm32wbxx_hal_tim.h
  • TIM_IT_CC2 : stm32wbxx_hal_tim.h
  • TIM_IT_CC3 : stm32wbxx_hal_tim.h
  • TIM_IT_CC4 : stm32wbxx_hal_tim.h
  • TIM_IT_COM : stm32wbxx_hal_tim.h
  • TIM_IT_TRIGGER : stm32wbxx_hal_tim.h
  • TIM_IT_UPDATE : stm32wbxx_hal_tim.h
  • TIM_ITRx_SetConfig() : stm32wbxx_hal_tim.c
  • TIM_LOCKLEVEL_1 : stm32wbxx_hal_tim.h
  • TIM_LOCKLEVEL_2 : stm32wbxx_hal_tim.h
  • TIM_LOCKLEVEL_3 : stm32wbxx_hal_tim.h
  • TIM_LOCKLEVEL_OFF : stm32wbxx_hal_tim.h
  • TIM_MASTERSLAVEMODE_DISABLE : stm32wbxx_hal_tim.h
  • TIM_MASTERSLAVEMODE_ENABLE : stm32wbxx_hal_tim.h
  • TIM_OC1_SetConfig() : stm32wbxx_hal_tim.c
  • TIM_OC2_SetConfig() : stm32wbxx_hal_tim.c
  • TIM_OC3_SetConfig() : stm32wbxx_hal_tim.c
  • TIM_OC4_SetConfig() : stm32wbxx_hal_tim.c
  • TIM_OC5_SetConfig() : stm32wbxx_hal_tim.c
  • TIM_OC6_SetConfig() : stm32wbxx_hal_tim.c
  • TIM_OCFAST_DISABLE : stm32wbxx_hal_tim.h
  • TIM_OCFAST_ENABLE : stm32wbxx_hal_tim.h
  • TIM_OCIDLESTATE_RESET : stm32wbxx_hal_tim.h
  • TIM_OCIDLESTATE_SET : stm32wbxx_hal_tim.h
  • TIM_OCMODE_ACTIVE : stm32wbxx_hal_tim.h
  • TIM_OCMODE_ASSYMETRIC_PWM1 : stm32wbxx_hal_tim.h
  • TIM_OCMODE_ASSYMETRIC_PWM2 : stm32wbxx_hal_tim.h
  • TIM_OCMODE_COMBINED_PWM1 : stm32wbxx_hal_tim.h
  • TIM_OCMODE_COMBINED_PWM2 : stm32wbxx_hal_tim.h
  • TIM_OCMODE_FORCED_ACTIVE : stm32wbxx_hal_tim.h
  • TIM_OCMODE_FORCED_INACTIVE : stm32wbxx_hal_tim.h
  • TIM_OCMODE_INACTIVE : stm32wbxx_hal_tim.h
  • TIM_OCMODE_PWM1 : stm32wbxx_hal_tim.h
  • TIM_OCMODE_PWM2 : stm32wbxx_hal_tim.h
  • TIM_OCMODE_RETRIGERRABLE_OPM1 : stm32wbxx_hal_tim.h
  • TIM_OCMODE_RETRIGERRABLE_OPM2 : stm32wbxx_hal_tim.h
  • TIM_OCMODE_TIMING : stm32wbxx_hal_tim.h
  • TIM_OCMODE_TOGGLE : stm32wbxx_hal_tim.h
  • TIM_OCNIDLESTATE_RESET : stm32wbxx_hal_tim.h
  • TIM_OCNIDLESTATE_SET : stm32wbxx_hal_tim.h
  • TIM_OCNPOLARITY_HIGH : stm32wbxx_hal_tim.h
  • TIM_OCNPOLARITY_LOW : stm32wbxx_hal_tim.h
  • TIM_OCPOLARITY_HIGH : stm32wbxx_hal_tim.h
  • TIM_OCPOLARITY_LOW : stm32wbxx_hal_tim.h
  • TIM_OPMODE_REPETITIVE : stm32wbxx_hal_tim.h
  • TIM_OPMODE_SINGLE : stm32wbxx_hal_tim.h
  • TIM_OSSI_DISABLE : stm32wbxx_hal_tim.h
  • TIM_OSSI_ENABLE : stm32wbxx_hal_tim.h
  • TIM_OSSR_DISABLE : stm32wbxx_hal_tim.h
  • TIM_OSSR_ENABLE : stm32wbxx_hal_tim.h
  • TIM_OUTPUTNSTATE_DISABLE : stm32wbxx_hal_tim.h
  • TIM_OUTPUTNSTATE_ENABLE : stm32wbxx_hal_tim.h
  • TIM_OUTPUTSTATE_DISABLE : stm32wbxx_hal_tim.h
  • TIM_OUTPUTSTATE_ENABLE : stm32wbxx_hal_tim.h
  • TIM_POSITION_BRK_SOURCE : stm32wbxx_ll_tim.h
  • TIM_RESET_CAPTUREPOLARITY : stm32wbxx_hal_tim.h
  • TIM_RESET_ICPRESCALERVALUE : stm32wbxx_hal_tim.h
  • TIM_ResetCallback() : stm32wbxx_hal_tim.c
  • TIM_SET_CAPTUREPOLARITY : stm32wbxx_hal_tim.h
  • TIM_SET_ICPRESCALERVALUE : stm32wbxx_hal_tim.h
  • TIM_SLAVEMODE_COMBINED_RESETTRIGGER : stm32wbxx_hal_tim.h
  • TIM_SLAVEMODE_DISABLE : stm32wbxx_hal_tim.h
  • TIM_SLAVEMODE_EXTERNAL1 : stm32wbxx_hal_tim.h
  • TIM_SLAVEMODE_GATED : stm32wbxx_hal_tim.h
  • TIM_SLAVEMODE_RESET : stm32wbxx_hal_tim.h
  • TIM_SLAVEMODE_TRIGGER : stm32wbxx_hal_tim.h
  • TIM_SlaveTimer_SetConfig() : stm32wbxx_hal_tim.c
  • TIM_TI1_ConfigInputStage() : stm32wbxx_hal_tim.c
  • TIM_TI1_SetConfig() : stm32wbxx_hal_tim.c
  • TIM_TI1SELECTION_CH1 : stm32wbxx_hal_tim.h
  • TIM_TI1SELECTION_XORCOMBINATION : stm32wbxx_hal_tim.h
  • TIM_TI2_ConfigInputStage() : stm32wbxx_hal_tim.c
  • TIM_TI2_SetConfig() : stm32wbxx_hal_tim.c
  • TIM_TI3_SetConfig() : stm32wbxx_hal_tim.c
  • TIM_TI4_SetConfig() : stm32wbxx_hal_tim.c
  • TIM_TIM16_TI1_GPIO : stm32wbxx_hal_tim_ex.h
  • TIM_TIM16_TI1_LSE : stm32wbxx_hal_tim_ex.h
  • TIM_TIM16_TI1_LSI : stm32wbxx_hal_tim_ex.h
  • TIM_TIM16_TI1_RTC : stm32wbxx_hal_tim_ex.h
  • TIM_TIM17_TI1_GPIO : stm32wbxx_hal_tim_ex.h
  • TIM_TIM17_TI1_HSE : stm32wbxx_hal_tim_ex.h
  • TIM_TIM17_TI1_MCO : stm32wbxx_hal_tim_ex.h
  • TIM_TIM17_TI1_MSI : stm32wbxx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC1_AWD1 : stm32wbxx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC1_AWD2 : stm32wbxx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC1_AWD3 : stm32wbxx_hal_tim_ex.h
  • TIM_TIM1_ETR_COMP1 : stm32wbxx_hal_tim_ex.h
  • TIM_TIM1_ETR_COMP2 : stm32wbxx_hal_tim_ex.h
  • TIM_TIM1_ETR_GPIO : stm32wbxx_hal_tim_ex.h
  • TIM_TIM1_TI1_COMP1 : stm32wbxx_hal_tim_ex.h
  • TIM_TIM1_TI1_GPIO : stm32wbxx_hal_tim_ex.h
  • TIM_TIM2_ETR_COMP1 : stm32wbxx_hal_tim_ex.h
  • TIM_TIM2_ETR_COMP2 : stm32wbxx_hal_tim_ex.h
  • TIM_TIM2_ETR_GPIO : stm32wbxx_hal_tim_ex.h
  • TIM_TIM2_ETR_LSE : stm32wbxx_hal_tim_ex.h
  • TIM_TIM2_ITR_NC : stm32wbxx_hal_tim_ex.h
  • TIM_TIM2_ITR_USB : stm32wbxx_hal_tim_ex.h
  • TIM_TIM2_TI4_COMP1 : stm32wbxx_hal_tim_ex.h
  • TIM_TIM2_TI4_COMP1_COMP2 : stm32wbxx_hal_tim_ex.h
  • TIM_TIM2_TI4_COMP2 : stm32wbxx_hal_tim_ex.h
  • TIM_TIM2_TI4_GPIO : stm32wbxx_hal_tim_ex.h
  • TIM_TRGO2_ENABLE : stm32wbxx_hal_tim.h
  • TIM_TRGO2_OC1 : stm32wbxx_hal_tim.h
  • TIM_TRGO2_OC1REF : stm32wbxx_hal_tim.h
  • TIM_TRGO2_OC2REF : stm32wbxx_hal_tim.h
  • TIM_TRGO2_OC3REF : stm32wbxx_hal_tim.h
  • TIM_TRGO2_OC4REF : stm32wbxx_hal_tim.h
  • TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING : stm32wbxx_hal_tim.h
  • TIM_TRGO2_OC4REF_RISING_OC6REF_RISING : stm32wbxx_hal_tim.h
  • TIM_TRGO2_OC4REF_RISINGFALLING : stm32wbxx_hal_tim.h
  • TIM_TRGO2_OC5REF : stm32wbxx_hal_tim.h
  • TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING : stm32wbxx_hal_tim.h
  • TIM_TRGO2_OC5REF_RISING_OC6REF_RISING : stm32wbxx_hal_tim.h
  • TIM_TRGO2_OC6REF : stm32wbxx_hal_tim.h
  • TIM_TRGO2_OC6REF_RISINGFALLING : stm32wbxx_hal_tim.h
  • TIM_TRGO2_RESET : stm32wbxx_hal_tim.h
  • TIM_TRGO2_UPDATE : stm32wbxx_hal_tim.h
  • TIM_TRGO_ENABLE : stm32wbxx_hal_tim.h
  • TIM_TRGO_OC1 : stm32wbxx_hal_tim.h
  • TIM_TRGO_OC1REF : stm32wbxx_hal_tim.h
  • TIM_TRGO_OC2REF : stm32wbxx_hal_tim.h
  • TIM_TRGO_OC3REF : stm32wbxx_hal_tim.h
  • TIM_TRGO_OC4REF : stm32wbxx_hal_tim.h
  • TIM_TRGO_RESET : stm32wbxx_hal_tim.h
  • TIM_TRGO_UPDATE : stm32wbxx_hal_tim.h
  • TIM_TRIGGERPOLARITY_BOTHEDGE : stm32wbxx_hal_tim.h
  • TIM_TRIGGERPOLARITY_FALLING : stm32wbxx_hal_tim.h
  • TIM_TRIGGERPOLARITY_INVERTED : stm32wbxx_hal_tim.h
  • TIM_TRIGGERPOLARITY_NONINVERTED : stm32wbxx_hal_tim.h
  • TIM_TRIGGERPOLARITY_RISING : stm32wbxx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV1 : stm32wbxx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV2 : stm32wbxx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV4 : stm32wbxx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV8 : stm32wbxx_hal_tim.h
  • TIM_TS_ETRF : stm32wbxx_hal_tim.h
  • TIM_TS_ITR0 : stm32wbxx_hal_tim.h
  • TIM_TS_ITR1 : stm32wbxx_hal_tim.h
  • TIM_TS_ITR2 : stm32wbxx_hal_tim.h
  • TIM_TS_ITR3 : stm32wbxx_hal_tim.h
  • TIM_TS_NONE : stm32wbxx_hal_tim.h
  • TIM_TS_TI1F_ED : stm32wbxx_hal_tim.h
  • TIM_TS_TI1FP1 : stm32wbxx_hal_tim.h
  • TIM_TS_TI2FP2 : stm32wbxx_hal_tim.h
  • TIMEOUT : stm32wbxx_hal_lptim.c
  • TIMEx_DMACommutationCplt() : stm32wbxx_hal_tim_ex.c
  • TIMEx_DMACommutationHalfCplt() : stm32wbxx_hal_tim_ex.c
  • TIMING_CLEAR_MASK : stm32wbxx_hal_smbus.c , stm32wbxx_hal_i2c.c
  • TIMx_AF1_BKCOMP1E : stm32wbxx_ll_tim.h
  • TIMx_AF1_BKCOMP1P : stm32wbxx_ll_tim.h
  • TIMx_AF1_BKCOMP2E : stm32wbxx_ll_tim.h
  • TIMx_AF1_BKCOMP2P : stm32wbxx_ll_tim.h
  • TIMx_AF1_BKINE : stm32wbxx_ll_tim.h
  • TIMx_AF1_BKINP : stm32wbxx_ll_tim.h
  • TIMx_AF1_ETRSEL : stm32wbxx_ll_tim.h , stm32wbxx_hal_tim.c
  • TIMx_AF2_BK2COMP1E : stm32wbxx_ll_tim.h
  • TIMx_AF2_BK2COMP1P : stm32wbxx_ll_tim.h
  • TIMx_AF2_BK2COMP2E : stm32wbxx_ll_tim.h
  • TIMx_AF2_BK2COMP2P : stm32wbxx_ll_tim.h
  • TIMx_AF2_BK2INE : stm32wbxx_ll_tim.h
  • TIMx_AF2_BK2INP : stm32wbxx_ll_tim.h
  • TIMx_OR_RMP_MASK : stm32wbxx_ll_tim.h
  • TIMx_OR_RMP_SHIFT : stm32wbxx_ll_tim.h
  • TSC_ACQ_MODE_NORMAL : stm32wbxx_hal_tsc.h
  • TSC_ACQ_MODE_SYNCHRO : stm32wbxx_hal_tsc.h
  • TSC_CTPH_10CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPH_11CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPH_12CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPH_13CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPH_14CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPH_15CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPH_16CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPH_1CYCLE : stm32wbxx_hal_tsc.h
  • TSC_CTPH_2CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPH_3CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPH_4CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPH_5CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPH_6CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPH_7CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPH_8CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPH_9CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPL_10CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPL_11CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPL_12CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPL_13CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPL_14CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPL_15CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPL_16CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPL_1CYCLE : stm32wbxx_hal_tsc.h
  • TSC_CTPL_2CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPL_3CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPL_4CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPL_5CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPL_6CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPL_7CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPL_8CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPL_9CYCLES : stm32wbxx_hal_tsc.h
  • TSC_extract_groups() : stm32wbxx_hal_tsc.c
  • TSC_FLAG_EOA : stm32wbxx_hal_tsc.h
  • TSC_FLAG_MCE : stm32wbxx_hal_tsc.h
  • TSC_GROUP1 : stm32wbxx_hal_tsc.h
  • TSC_GROUP1_IDX : stm32wbxx_hal_tsc.h
  • TSC_GROUP1_IO1 : stm32wbxx_hal_tsc.h
  • TSC_GROUP1_IO2 : stm32wbxx_hal_tsc.h
  • TSC_GROUP1_IO3 : stm32wbxx_hal_tsc.h
  • TSC_GROUP1_IO4 : stm32wbxx_hal_tsc.h
  • TSC_GROUP2 : stm32wbxx_hal_tsc.h
  • TSC_GROUP2_IDX : stm32wbxx_hal_tsc.h
  • TSC_GROUP2_IO1 : stm32wbxx_hal_tsc.h
  • TSC_GROUP2_IO2 : stm32wbxx_hal_tsc.h
  • TSC_GROUP2_IO3 : stm32wbxx_hal_tsc.h
  • TSC_GROUP2_IO4 : stm32wbxx_hal_tsc.h
  • TSC_GROUP3 : stm32wbxx_hal_tsc.h
  • TSC_GROUP3_IDX : stm32wbxx_hal_tsc.h
  • TSC_GROUP3_IO1 : stm32wbxx_hal_tsc.h
  • TSC_GROUP3_IO2 : stm32wbxx_hal_tsc.h
  • TSC_GROUP3_IO3 : stm32wbxx_hal_tsc.h
  • TSC_GROUP3_IO4 : stm32wbxx_hal_tsc.h
  • TSC_GROUP4 : stm32wbxx_hal_tsc.h
  • TSC_GROUP4_IDX : stm32wbxx_hal_tsc.h
  • TSC_GROUP4_IO1 : stm32wbxx_hal_tsc.h
  • TSC_GROUP4_IO2 : stm32wbxx_hal_tsc.h
  • TSC_GROUP4_IO3 : stm32wbxx_hal_tsc.h
  • TSC_GROUP4_IO4 : stm32wbxx_hal_tsc.h
  • TSC_GROUP5 : stm32wbxx_hal_tsc.h
  • TSC_GROUP5_IDX : stm32wbxx_hal_tsc.h
  • TSC_GROUP5_IO1 : stm32wbxx_hal_tsc.h
  • TSC_GROUP5_IO2 : stm32wbxx_hal_tsc.h
  • TSC_GROUP5_IO3 : stm32wbxx_hal_tsc.h
  • TSC_GROUP5_IO4 : stm32wbxx_hal_tsc.h
  • TSC_GROUP6 : stm32wbxx_hal_tsc.h
  • TSC_GROUP6_IDX : stm32wbxx_hal_tsc.h
  • TSC_GROUP6_IO1 : stm32wbxx_hal_tsc.h
  • TSC_GROUP6_IO2 : stm32wbxx_hal_tsc.h
  • TSC_GROUP6_IO3 : stm32wbxx_hal_tsc.h
  • TSC_GROUP6_IO4 : stm32wbxx_hal_tsc.h
  • TSC_GROUP7 : stm32wbxx_hal_tsc.h
  • TSC_GROUP7_IDX : stm32wbxx_hal_tsc.h
  • TSC_GROUP7_IO1 : stm32wbxx_hal_tsc.h
  • TSC_GROUP7_IO2 : stm32wbxx_hal_tsc.h
  • TSC_GROUP7_IO3 : stm32wbxx_hal_tsc.h
  • TSC_GROUP7_IO4 : stm32wbxx_hal_tsc.h
  • TSC_GROUP_COMPLETED : stm32wbxx_hal_tsc.h
  • TSC_GROUP_ONGOING : stm32wbxx_hal_tsc.h
  • TSC_GroupStatusTypeDef : stm32wbxx_hal_tsc.h
  • TSC_HandleTypeDef : stm32wbxx_hal_tsc.h
  • TSC_IODEF_IN_FLOAT : stm32wbxx_hal_tsc.h
  • TSC_IODEF_OUT_PP_LOW : stm32wbxx_hal_tsc.h
  • TSC_IT_EOA : stm32wbxx_hal_tsc.h
  • TSC_IT_MCE : stm32wbxx_hal_tsc.h
  • TSC_MCV_1023 : stm32wbxx_hal_tsc.h
  • TSC_MCV_16383 : stm32wbxx_hal_tsc.h
  • TSC_MCV_2047 : stm32wbxx_hal_tsc.h
  • TSC_MCV_255 : stm32wbxx_hal_tsc.h
  • TSC_MCV_4095 : stm32wbxx_hal_tsc.h
  • TSC_MCV_511 : stm32wbxx_hal_tsc.h
  • TSC_MCV_8191 : stm32wbxx_hal_tsc.h
  • TSC_NB_OF_GROUPS : stm32wbxx_hal_tsc.h
  • TSC_PG_PRESC_DIV1 : stm32wbxx_hal_tsc.h
  • TSC_PG_PRESC_DIV128 : stm32wbxx_hal_tsc.h
  • TSC_PG_PRESC_DIV16 : stm32wbxx_hal_tsc.h
  • TSC_PG_PRESC_DIV2 : stm32wbxx_hal_tsc.h
  • TSC_PG_PRESC_DIV32 : stm32wbxx_hal_tsc.h
  • TSC_PG_PRESC_DIV4 : stm32wbxx_hal_tsc.h
  • TSC_PG_PRESC_DIV64 : stm32wbxx_hal_tsc.h
  • TSC_PG_PRESC_DIV8 : stm32wbxx_hal_tsc.h
  • TSC_SS_PRESC_DIV1 : stm32wbxx_hal_tsc.h
  • TSC_SS_PRESC_DIV2 : stm32wbxx_hal_tsc.h
  • TSC_SYNC_POLARITY_FALLING : stm32wbxx_hal_tsc.h
  • TSC_SYNC_POLARITY_RISING : stm32wbxx_hal_tsc.h
  • TX_FIFO_DEPTH : stm32wbxx_hal_usart_ex.c , stm32wbxx_hal_smartcard_ex.c , stm32wbxx_hal_uart_ex.c
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- u -

  • UART_ADDRESS_DETECT_4B : stm32wbxx_hal_uart_ex.h
  • UART_ADDRESS_DETECT_7B : stm32wbxx_hal_uart_ex.h
  • UART_ADVFEATURE_AUTOBAUDRATE_DISABLE : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ENABLE : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_INIT : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_DATAINV_DISABLE : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_DATAINV_ENABLE : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_DATAINVERT_INIT : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_DMA_DISABLEONRXERROR : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_DMA_ENABLEONRXERROR : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_DMADISABLEONERROR_INIT : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_DISABLE : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_ENABLE : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_INIT : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_MUTEMODE_DISABLE : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_MUTEMODE_ENABLE : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_NO_INIT : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_OVERRUN_DISABLE : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_OVERRUN_ENABLE : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_RXINV_DISABLE : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_RXINV_ENABLE : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_RXINVERT_INIT : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_RXOVERRUNDISABLE_INIT : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_STOPMODE_DISABLE : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_STOPMODE_ENABLE : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_SWAP_DISABLE : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_SWAP_ENABLE : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_SWAP_INIT : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_TXINV_DISABLE : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_TXINV_ENABLE : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_TXINVERT_INIT : stm32wbxx_hal_uart.h
  • UART_AdvFeatureConfig() : stm32wbxx_hal_uart.c
  • UART_AUTOBAUD_REQUEST : stm32wbxx_hal_uart.h
  • UART_BRR_MAX : stm32wbxx_hal_uart.c
  • UART_BRR_MIN : stm32wbxx_hal_uart.c
  • UART_CheckIdleState() : stm32wbxx_hal_uart.c
  • UART_CLEAR_CMF : stm32wbxx_hal_uart.h
  • UART_CLEAR_CTSF : stm32wbxx_hal_uart.h
  • UART_CLEAR_FEF : stm32wbxx_hal_uart.h
  • UART_CLEAR_IDLEF : stm32wbxx_hal_uart.h
  • UART_CLEAR_LBDF : stm32wbxx_hal_uart.h
  • UART_CLEAR_NEF : stm32wbxx_hal_uart.h
  • UART_CLEAR_OREF : stm32wbxx_hal_uart.h
  • UART_CLEAR_PEF : stm32wbxx_hal_uart.h
  • UART_CLEAR_RTOF : stm32wbxx_hal_uart.h
  • UART_CLEAR_TCF : stm32wbxx_hal_uart.h
  • UART_CLEAR_TXFECF : stm32wbxx_hal_uart.h
  • UART_CLEAR_WUF : stm32wbxx_hal_uart.h
  • UART_CLOCKSOURCE_HSI : stm32wbxx_hal_uart.h
  • UART_CLOCKSOURCE_LSE : stm32wbxx_hal_uart.h
  • UART_CLOCKSOURCE_PCLK1 : stm32wbxx_hal_uart.h
  • UART_CLOCKSOURCE_PCLK2 : stm32wbxx_hal_uart.h
  • UART_CLOCKSOURCE_SYSCLK : stm32wbxx_hal_uart.h
  • UART_CLOCKSOURCE_UNDEFINED : stm32wbxx_hal_uart.h
  • UART_ClockSourceTypeDef : stm32wbxx_hal_uart.h
  • UART_CR1_DEAT_ADDRESS_LSB_POS : stm32wbxx_hal_uart.h
  • UART_CR1_DEDT_ADDRESS_LSB_POS : stm32wbxx_hal_uart.h
  • UART_CR2_ADDRESS_LSB_POS : stm32wbxx_hal_uart.h
  • UART_DE_POLARITY_HIGH : stm32wbxx_hal_uart.h
  • UART_DE_POLARITY_LOW : stm32wbxx_hal_uart.h
  • UART_DIV_LPUART : stm32wbxx_hal_uart.h
  • UART_DIV_SAMPLING16 : stm32wbxx_hal_uart.h
  • UART_DIV_SAMPLING8 : stm32wbxx_hal_uart.h
  • UART_DMA_RX_DISABLE : stm32wbxx_hal_uart.h
  • UART_DMA_RX_ENABLE : stm32wbxx_hal_uart.h
  • UART_DMA_TX_DISABLE : stm32wbxx_hal_uart.h
  • UART_DMA_TX_ENABLE : stm32wbxx_hal_uart.h
  • UART_DMAAbortOnError() : stm32wbxx_hal_uart.c
  • UART_DMAError() : stm32wbxx_hal_uart.c
  • UART_DMAReceiveCplt() : stm32wbxx_hal_uart.c
  • UART_DMARxAbortCallback() : stm32wbxx_hal_uart.c
  • UART_DMARxHalfCplt() : stm32wbxx_hal_uart.c
  • UART_DMARxOnlyAbortCallback() : stm32wbxx_hal_uart.c
  • UART_DMATransmitCplt() : stm32wbxx_hal_uart.c
  • UART_DMATxAbortCallback() : stm32wbxx_hal_uart.c
  • UART_DMATxHalfCplt() : stm32wbxx_hal_uart.c
  • UART_DMATxOnlyAbortCallback() : stm32wbxx_hal_uart.c
  • UART_EndRxTransfer() : stm32wbxx_hal_uart.c
  • UART_EndTransmit_IT() : stm32wbxx_hal_uart.c
  • UART_EndTxTransfer() : stm32wbxx_hal_uart.c
  • UART_FIFOMODE_DISABLE : stm32wbxx_hal_uart_ex.h
  • UART_FIFOMODE_ENABLE : stm32wbxx_hal_uart_ex.h
  • UART_FLAG_ABRE : stm32wbxx_hal_uart.h
  • UART_FLAG_ABRF : stm32wbxx_hal_uart.h
  • UART_FLAG_BUSY : stm32wbxx_hal_uart.h
  • UART_FLAG_CMF : stm32wbxx_hal_uart.h
  • UART_FLAG_CTS : stm32wbxx_hal_uart.h
  • UART_FLAG_CTSIF : stm32wbxx_hal_uart.h
  • UART_FLAG_FE : stm32wbxx_hal_uart.h
  • UART_FLAG_IDLE : stm32wbxx_hal_uart.h
  • UART_FLAG_LBDF : stm32wbxx_hal_uart.h
  • UART_FLAG_NE : stm32wbxx_hal_uart.h
  • UART_FLAG_ORE : stm32wbxx_hal_uart.h
  • UART_FLAG_PE : stm32wbxx_hal_uart.h
  • UART_FLAG_REACK : stm32wbxx_hal_uart.h
  • UART_FLAG_RTOF : stm32wbxx_hal_uart.h
  • UART_FLAG_RWU : stm32wbxx_hal_uart.h
  • UART_FLAG_RXFF : stm32wbxx_hal_uart.h
  • UART_FLAG_RXFNE : stm32wbxx_hal_uart.h
  • UART_FLAG_RXFT : stm32wbxx_hal_uart.h
  • UART_FLAG_RXNE : stm32wbxx_hal_uart.h
  • UART_FLAG_SBKF : stm32wbxx_hal_uart.h
  • UART_FLAG_TC : stm32wbxx_hal_uart.h
  • UART_FLAG_TEACK : stm32wbxx_hal_uart.h
  • UART_FLAG_TXE : stm32wbxx_hal_uart.h
  • UART_FLAG_TXFE : stm32wbxx_hal_uart.h
  • UART_FLAG_TXFNF : stm32wbxx_hal_uart.h
  • UART_FLAG_TXFT : stm32wbxx_hal_uart.h
  • UART_FLAG_WUF : stm32wbxx_hal_uart.h
  • UART_GET_DIV_FACTOR : stm32wbxx_hal_uart.h
  • UART_GETCLOCKSOURCE : stm32wbxx_hal_uart_ex.h
  • UART_HALF_DUPLEX_DISABLE : stm32wbxx_hal_uart.h
  • UART_HALF_DUPLEX_ENABLE : stm32wbxx_hal_uart.h
  • UART_HandleTypeDef : stm32wbxx_hal_uart.h
  • UART_HWCONTROL_CTS : stm32wbxx_hal_uart.h
  • UART_HWCONTROL_NONE : stm32wbxx_hal_uart.h
  • UART_HWCONTROL_RTS : stm32wbxx_hal_uart.h
  • UART_HWCONTROL_RTS_CTS : stm32wbxx_hal_uart.h
  • UART_InitCallbacksToDefault() : stm32wbxx_hal_uart.c
  • UART_INSTANCE_LOWPOWER : stm32wbxx_hal_uart.h
  • UART_IT_CM : stm32wbxx_hal_uart.h
  • UART_IT_CTS : stm32wbxx_hal_uart.h
  • UART_IT_ERR : stm32wbxx_hal_uart.h
  • UART_IT_FE : stm32wbxx_hal_uart.h
  • UART_IT_IDLE : stm32wbxx_hal_uart.h
  • UART_IT_LBD : stm32wbxx_hal_uart.h
  • UART_IT_MASK : stm32wbxx_hal_uart.h
  • UART_IT_NE : stm32wbxx_hal_uart.h
  • UART_IT_ORE : stm32wbxx_hal_uart.h
  • UART_IT_PE : stm32wbxx_hal_uart.h
  • UART_IT_RTO : stm32wbxx_hal_uart.h
  • UART_IT_RXFF : stm32wbxx_hal_uart.h
  • UART_IT_RXFNE : stm32wbxx_hal_uart.h
  • UART_IT_RXFT : stm32wbxx_hal_uart.h
  • UART_IT_RXNE : stm32wbxx_hal_uart.h
  • UART_IT_TC : stm32wbxx_hal_uart.h
  • UART_IT_TXE : stm32wbxx_hal_uart.h
  • UART_IT_TXFE : stm32wbxx_hal_uart.h
  • UART_IT_TXFNF : stm32wbxx_hal_uart.h
  • UART_IT_TXFT : stm32wbxx_hal_uart.h
  • UART_IT_WUF : stm32wbxx_hal_uart.h
  • UART_LIN_DISABLE : stm32wbxx_hal_uart.h
  • UART_LIN_ENABLE : stm32wbxx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_10B : stm32wbxx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_11B : stm32wbxx_hal_uart.h
  • UART_MASK_COMPUTATION : stm32wbxx_hal_uart_ex.h
  • UART_MODE_RX : stm32wbxx_hal_uart.h
  • UART_MODE_TX : stm32wbxx_hal_uart.h
  • UART_MODE_TX_RX : stm32wbxx_hal_uart.h
  • UART_MUTE_MODE_REQUEST : stm32wbxx_hal_uart.h
  • UART_ONE_BIT_SAMPLE_DISABLE : stm32wbxx_hal_uart.h
  • UART_ONE_BIT_SAMPLE_ENABLE : stm32wbxx_hal_uart.h
  • UART_OVERSAMPLING_16 : stm32wbxx_hal_uart.h
  • UART_OVERSAMPLING_8 : stm32wbxx_hal_uart.h
  • UART_PARITY_EVEN : stm32wbxx_hal_uart.h
  • UART_PARITY_NONE : stm32wbxx_hal_uart.h
  • UART_PARITY_ODD : stm32wbxx_hal_uart.h
  • UART_PRESCALER_DIV1 : stm32wbxx_hal_uart.h
  • UART_PRESCALER_DIV10 : stm32wbxx_hal_uart.h
  • UART_PRESCALER_DIV12 : stm32wbxx_hal_uart.h
  • UART_PRESCALER_DIV128 : stm32wbxx_hal_uart.h
  • UART_PRESCALER_DIV16 : stm32wbxx_hal_uart.h
  • UART_PRESCALER_DIV2 : stm32wbxx_hal_uart.h
  • UART_PRESCALER_DIV256 : stm32wbxx_hal_uart.h
  • UART_PRESCALER_DIV32 : stm32wbxx_hal_uart.h
  • UART_PRESCALER_DIV4 : stm32wbxx_hal_uart.h
  • UART_PRESCALER_DIV6 : stm32wbxx_hal_uart.h
  • UART_PRESCALER_DIV64 : stm32wbxx_hal_uart.h
  • UART_PRESCALER_DIV8 : stm32wbxx_hal_uart.h
  • UART_RECEIVER_TIMEOUT_DISABLE : stm32wbxx_hal_uart.h
  • UART_RECEIVER_TIMEOUT_ENABLE : stm32wbxx_hal_uart.h
  • UART_RXDATA_FLUSH_REQUEST : stm32wbxx_hal_uart.h
  • UART_RXFIFO_THRESHOLD_1_2 : stm32wbxx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_1_4 : stm32wbxx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_1_8 : stm32wbxx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_3_4 : stm32wbxx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_7_8 : stm32wbxx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_8_8 : stm32wbxx_hal_uart_ex.h
  • UART_RxISR_16BIT() : stm32wbxx_hal_uart.c
  • UART_RxISR_16BIT_FIFOEN() : stm32wbxx_hal_uart.c
  • UART_RxISR_8BIT() : stm32wbxx_hal_uart.c
  • UART_RxISR_8BIT_FIFOEN() : stm32wbxx_hal_uart.c
  • UART_SENDBREAK_REQUEST : stm32wbxx_hal_uart.h
  • UART_SetConfig() : stm32wbxx_hal_uart.c
  • UART_STATE_DISABLE : stm32wbxx_hal_uart.h
  • UART_STATE_ENABLE : stm32wbxx_hal_uart.h
  • UART_STOPBITS_0_5 : stm32wbxx_hal_uart.h
  • UART_STOPBITS_1 : stm32wbxx_hal_uart.h
  • UART_STOPBITS_1_5 : stm32wbxx_hal_uart.h
  • UART_STOPBITS_2 : stm32wbxx_hal_uart.h
  • UART_TXDATA_FLUSH_REQUEST : stm32wbxx_hal_uart.h
  • UART_TXFIFO_THRESHOLD_1_2 : stm32wbxx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_1_4 : stm32wbxx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_1_8 : stm32wbxx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_3_4 : stm32wbxx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_7_8 : stm32wbxx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_8_8 : stm32wbxx_hal_uart_ex.h
  • UART_TxISR_16BIT() : stm32wbxx_hal_uart.c
  • UART_TxISR_16BIT_FIFOEN() : stm32wbxx_hal_uart.c
  • UART_TxISR_8BIT() : stm32wbxx_hal_uart.c
  • UART_TxISR_8BIT_FIFOEN() : stm32wbxx_hal_uart.c
  • UART_WaitOnFlagUntilTimeout() : stm32wbxx_hal_uart.c
  • UART_WAKEUP_ON_ADDRESS : stm32wbxx_hal_uart.h
  • UART_WAKEUP_ON_READDATA_NONEMPTY : stm32wbxx_hal_uart.h
  • UART_WAKEUP_ON_STARTBIT : stm32wbxx_hal_uart.h
  • UART_WAKEUPMETHOD_ADDRESSMARK : stm32wbxx_hal_uart.h
  • UART_WAKEUPMETHOD_IDLELINE : stm32wbxx_hal_uart.h
  • UART_WORDLENGTH_7B : stm32wbxx_hal_uart_ex.h
  • UART_WORDLENGTH_8B : stm32wbxx_hal_uart_ex.h
  • UART_WORDLENGTH_9B : stm32wbxx_hal_uart_ex.h
  • UARTEx_SetNbDataToProcess() : stm32wbxx_hal_uart_ex.c
  • UARTEx_Wakeup_AddressConfig() : stm32wbxx_hal_uart_ex.c
  • UID_BASE_ADDRESS : stm32wbxx_ll_utils.h
  • USART_BRR_MAX : stm32wbxx_hal_smartcard.c , stm32wbxx_hal_irda.c , stm32wbxx_hal_usart.c
  • USART_BRR_MIN : stm32wbxx_hal_usart.c , stm32wbxx_hal_irda.c , stm32wbxx_hal_smartcard.c
  • USART_CheckIdleState() : stm32wbxx_hal_usart.c
  • USART_CLEAR_FEF : stm32wbxx_hal_usart.h
  • USART_CLEAR_IDLEF : stm32wbxx_hal_usart.h
  • USART_CLEAR_NEF : stm32wbxx_hal_usart.h
  • USART_CLEAR_OREF : stm32wbxx_hal_usart.h
  • USART_CLEAR_PEF : stm32wbxx_hal_usart.h
  • USART_CLEAR_TCF : stm32wbxx_hal_usart.h
  • USART_CLEAR_TXFECF : stm32wbxx_hal_usart.h
  • USART_CLEAR_UDRF : stm32wbxx_hal_usart.h
  • USART_CLOCK_DISABLE : stm32wbxx_hal_usart.h
  • USART_CLOCK_ENABLE : stm32wbxx_hal_usart.h
  • USART_CLOCKSOURCE_HSI : stm32wbxx_hal_usart.h
  • USART_CLOCKSOURCE_LSE : stm32wbxx_hal_usart.h
  • USART_CLOCKSOURCE_PCLK2 : stm32wbxx_hal_usart.h
  • USART_CLOCKSOURCE_SYSCLK : stm32wbxx_hal_usart.h
  • USART_CLOCKSOURCE_UNDEFINED : stm32wbxx_hal_usart.h
  • USART_ClockSourceTypeDef : stm32wbxx_hal_usart.h
  • USART_CR1_FIELDS : stm32wbxx_hal_smartcard.c , stm32wbxx_hal_uart.c , stm32wbxx_hal_usart.c
  • USART_CR2_CLK_FIELDS : stm32wbxx_hal_smartcard.c
  • USART_CR2_FIELDS : stm32wbxx_hal_smartcard.c , stm32wbxx_hal_usart.c
  • USART_CR3_FIELDS : stm32wbxx_hal_smartcard.c , stm32wbxx_hal_uart.c , stm32wbxx_hal_usart.c
  • USART_CR_MASK : stm32wbxx_hal_usart.h
  • USART_CR_POS : stm32wbxx_hal_usart.h
  • USART_DIV_SAMPLING8 : stm32wbxx_hal_usart.h
  • USART_DMAAbortOnError() : stm32wbxx_hal_usart.c
  • USART_DMAError() : stm32wbxx_hal_usart.c
  • USART_DMAReceiveCplt() : stm32wbxx_hal_usart.c
  • USART_DMARxAbortCallback() : stm32wbxx_hal_usart.c
  • USART_DMARxHalfCplt() : stm32wbxx_hal_usart.c
  • USART_DMATransmitCplt() : stm32wbxx_hal_usart.c
  • USART_DMATxAbortCallback() : stm32wbxx_hal_usart.c
  • USART_DMATxHalfCplt() : stm32wbxx_hal_usart.c
  • USART_DUMMY_DATA : stm32wbxx_hal_usart.c
  • USART_EndTransfer() : stm32wbxx_hal_usart.c
  • USART_EndTransmit_IT() : stm32wbxx_hal_usart.c
  • USART_FIFOMODE_DISABLE : stm32wbxx_hal_usart_ex.h
  • USART_FIFOMODE_ENABLE : stm32wbxx_hal_usart_ex.h
  • USART_FLAG_BUSY : stm32wbxx_hal_usart.h
  • USART_FLAG_FE : stm32wbxx_hal_usart.h
  • USART_FLAG_IDLE : stm32wbxx_hal_usart.h
  • USART_FLAG_NE : stm32wbxx_hal_usart.h
  • USART_FLAG_ORE : stm32wbxx_hal_usart.h
  • USART_FLAG_PE : stm32wbxx_hal_usart.h
  • USART_FLAG_REACK : stm32wbxx_hal_usart.h
  • USART_FLAG_RXFF : stm32wbxx_hal_usart.h
  • USART_FLAG_RXFNE : stm32wbxx_hal_usart.h
  • USART_FLAG_RXFT : stm32wbxx_hal_usart.h
  • USART_FLAG_RXNE : stm32wbxx_hal_usart.h
  • USART_FLAG_TC : stm32wbxx_hal_usart.h
  • USART_FLAG_TEACK : stm32wbxx_hal_usart.h
  • USART_FLAG_TXE : stm32wbxx_hal_usart.h
  • USART_FLAG_TXFE : stm32wbxx_hal_usart.h
  • USART_FLAG_TXFNF : stm32wbxx_hal_usart.h
  • USART_FLAG_TXFT : stm32wbxx_hal_usart.h
  • USART_FLAG_UDR : stm32wbxx_hal_usart.h
  • USART_GET_DIV_FACTOR : stm32wbxx_hal_usart.h
  • USART_GETCLOCKSOURCE : stm32wbxx_hal_usart.h
  • USART_HandleTypeDef : stm32wbxx_hal_usart.h
  • USART_InitCallbacksToDefault() : stm32wbxx_hal_usart.c
  • USART_IT_ERR : stm32wbxx_hal_usart.h
  • USART_IT_FE : stm32wbxx_hal_usart.h
  • USART_IT_IDLE : stm32wbxx_hal_usart.h
  • USART_IT_MASK : stm32wbxx_hal_usart.h
  • USART_IT_NE : stm32wbxx_hal_usart.h
  • USART_IT_ORE : stm32wbxx_hal_usart.h
  • USART_IT_PE : stm32wbxx_hal_usart.h
  • USART_IT_RXFF : stm32wbxx_hal_usart.h
  • USART_IT_RXFNE : stm32wbxx_hal_usart.h
  • USART_IT_RXFT : stm32wbxx_hal_usart.h
  • USART_IT_RXNE : stm32wbxx_hal_usart.h
  • USART_IT_TC : stm32wbxx_hal_usart.h
  • USART_IT_TXE : stm32wbxx_hal_usart.h
  • USART_IT_TXFE : stm32wbxx_hal_usart.h
  • USART_IT_TXFNF : stm32wbxx_hal_usart.h
  • USART_IT_TXFT : stm32wbxx_hal_usart.h
  • USART_LASTBIT_DISABLE : stm32wbxx_hal_usart.h
  • USART_LASTBIT_ENABLE : stm32wbxx_hal_usart.h
  • USART_MASK_COMPUTATION : stm32wbxx_hal_usart_ex.h
  • USART_MODE_RX : stm32wbxx_hal_usart.h
  • USART_MODE_TX : stm32wbxx_hal_usart.h
  • USART_MODE_TX_RX : stm32wbxx_hal_usart.h
  • USART_NSS_HARD : stm32wbxx_hal_usart_ex.h
  • USART_NSS_SOFT : stm32wbxx_hal_usart_ex.h
  • USART_OVERSAMPLING_16 : stm32wbxx_hal_usart.h
  • USART_OVERSAMPLING_8 : stm32wbxx_hal_usart.h
  • USART_PARITY_EVEN : stm32wbxx_hal_usart.h
  • USART_PARITY_NONE : stm32wbxx_hal_usart.h
  • USART_PARITY_ODD : stm32wbxx_hal_usart.h
  • USART_PHASE_1EDGE : stm32wbxx_hal_usart.h
  • USART_PHASE_2EDGE : stm32wbxx_hal_usart.h
  • USART_POLARITY_HIGH : stm32wbxx_hal_usart.h
  • USART_POLARITY_LOW : stm32wbxx_hal_usart.h
  • USART_PRESCALER_DIV1 : stm32wbxx_hal_usart.h
  • USART_PRESCALER_DIV10 : stm32wbxx_hal_usart.h
  • USART_PRESCALER_DIV12 : stm32wbxx_hal_usart.h
  • USART_PRESCALER_DIV128 : stm32wbxx_hal_usart.h
  • USART_PRESCALER_DIV16 : stm32wbxx_hal_usart.h
  • USART_PRESCALER_DIV2 : stm32wbxx_hal_usart.h
  • USART_PRESCALER_DIV256 : stm32wbxx_hal_usart.h
  • USART_PRESCALER_DIV32 : stm32wbxx_hal_usart.h
  • USART_PRESCALER_DIV4 : stm32wbxx_hal_usart.h
  • USART_PRESCALER_DIV6 : stm32wbxx_hal_usart.h
  • USART_PRESCALER_DIV64 : stm32wbxx_hal_usart.h
  • USART_PRESCALER_DIV8 : stm32wbxx_hal_usart.h
  • USART_PRESCALER_TAB : stm32wbxx_ll_usart.h
  • USART_RXDATA_FLUSH_REQUEST : stm32wbxx_hal_usart.h
  • USART_RXFIFO_THRESHOLD_1_2 : stm32wbxx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_1_4 : stm32wbxx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_1_8 : stm32wbxx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_3_4 : stm32wbxx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_7_8 : stm32wbxx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_8_8 : stm32wbxx_hal_usart_ex.h
  • USART_RxISR_16BIT() : stm32wbxx_hal_usart.c
  • USART_RxISR_16BIT_FIFOEN() : stm32wbxx_hal_usart.c
  • USART_RxISR_8BIT() : stm32wbxx_hal_usart.c
  • USART_RxISR_8BIT_FIFOEN() : stm32wbxx_hal_usart.c
  • USART_SetConfig() : stm32wbxx_hal_usart.c
  • USART_SLAVEMODE_DISABLE : stm32wbxx_hal_usart_ex.h
  • USART_SLAVEMODE_ENABLE : stm32wbxx_hal_usart_ex.h
  • USART_STOPBITS_0_5 : stm32wbxx_hal_usart.h
  • USART_STOPBITS_1 : stm32wbxx_hal_usart.h
  • USART_STOPBITS_1_5 : stm32wbxx_hal_usart.h
  • USART_STOPBITS_2 : stm32wbxx_hal_usart.h
  • USART_TEACK_REACK_TIMEOUT : stm32wbxx_hal_usart.c
  • USART_TXDATA_FLUSH_REQUEST : stm32wbxx_hal_usart.h
  • USART_TXFIFO_THRESHOLD_1_2 : stm32wbxx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_1_4 : stm32wbxx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_1_8 : stm32wbxx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_3_4 : stm32wbxx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_7_8 : stm32wbxx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_8_8 : stm32wbxx_hal_usart_ex.h
  • USART_TxISR_16BIT() : stm32wbxx_hal_usart.c
  • USART_TxISR_16BIT_FIFOEN() : stm32wbxx_hal_usart.c
  • USART_TxISR_8BIT() : stm32wbxx_hal_usart.c
  • USART_TxISR_8BIT_FIFOEN() : stm32wbxx_hal_usart.c
  • USART_WaitOnFlagUntilTimeout() : stm32wbxx_hal_usart.c
  • USART_WORDLENGTH_7B : stm32wbxx_hal_usart_ex.h
  • USART_WORDLENGTH_8B : stm32wbxx_hal_usart_ex.h
  • USART_WORDLENGTH_9B : stm32wbxx_hal_usart_ex.h
  • USARTEx_SetNbDataToProcess() : stm32wbxx_hal_usart_ex.c
  • USB_CNTRX_BLSIZE : stm32wbxx_hal_pcd.h
  • USB_CNTRX_NBLK_MSK : stm32wbxx_hal_pcd.h
  • USB_EP0StartXfer : stm32wbxx_hal_pcd.h
  • USB_WAKEUP_EXTI_LINE : stm32wbxx_hal_pcd.h
  • USE_HAL_ADC_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_HAL_COMP_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_HAL_CRYP_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_HAL_I2C_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_HAL_IRDA_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_HAL_LPTIM_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_HAL_PCD_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_HAL_PKA_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_HAL_QSPI_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_HAL_RNG_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_HAL_RTC_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_HAL_SAI_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_HAL_SMARTCARD_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_HAL_SMBUS_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_HAL_SPI_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_HAL_TIM_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_HAL_TSC_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_HAL_UART_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_HAL_USART_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_HAL_WWDG_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_RTOS : stm32wbxx_hal_conf.h
  • USE_SPI_CRC : stm32wbxx_hal_conf.h
  • UTILS_EnablePLLAndSwitchSystem() : stm32wbxx_ll_utils.c
  • UTILS_GetPLLOutputFrequency() : stm32wbxx_ll_utils.c
  • UTILS_HCLK2_MAX : stm32wbxx_ll_utils.c
  • UTILS_MAX_FREQUENCY_SCALE1 : stm32wbxx_ll_utils.c
  • UTILS_MAX_FREQUENCY_SCALE2 : stm32wbxx_ll_utils.c
  • UTILS_PLL_IsBusy() : stm32wbxx_ll_utils.c
  • UTILS_PLLVCO_INPUT_MAX : stm32wbxx_ll_utils.c
  • UTILS_PLLVCO_INPUT_MIN : stm32wbxx_ll_utils.c
  • UTILS_PLLVCO_OUTPUT_MAX : stm32wbxx_ll_utils.c
  • UTILS_PLLVCO_OUTPUT_MIN : stm32wbxx_ll_utils.c
  • UTILS_SetFlashLatency() : stm32wbxx_ll_utils.c
  • uwTick : stm32wbxx_hal.c , stm32wbxx_hal.h
  • uwTickFreq : stm32wbxx_hal.c , stm32wbxx_hal.h
  • uwTickPrio : stm32wbxx_hal.c , stm32wbxx_hal.h
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- v -

  • VDD_VALUE : stm32wbxx_hal_conf.h
  • VREFBUF_TIMEOUT_VALUE : stm32wbxx_hal.c
  • VREFINT_CAL_ADDR : stm32wbxx_ll_adc.h
  • VREFINT_CAL_VREF : stm32wbxx_ll_adc.h
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

  • File List
  • Globals
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  • Functions
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  • Typedefs
  • Enumerations
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  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- w -

  • WWDG_EWI_DISABLE : stm32wbxx_hal_wwdg.h
  • WWDG_EWI_ENABLE : stm32wbxx_hal_wwdg.h
  • WWDG_FLAG_EWIF : stm32wbxx_hal_wwdg.h
  • WWDG_HandleTypeDef : stm32wbxx_hal_wwdg.h
  • WWDG_IT_EWI : stm32wbxx_hal_wwdg.h
  • WWDG_PRESCALER_1 : stm32wbxx_hal_wwdg.h
  • WWDG_PRESCALER_128 : stm32wbxx_hal_wwdg.h
  • WWDG_PRESCALER_16 : stm32wbxx_hal_wwdg.h
  • WWDG_PRESCALER_2 : stm32wbxx_hal_wwdg.h
  • WWDG_PRESCALER_32 : stm32wbxx_hal_wwdg.h
  • WWDG_PRESCALER_4 : stm32wbxx_hal_wwdg.h
  • WWDG_PRESCALER_64 : stm32wbxx_hal_wwdg.h
  • WWDG_PRESCALER_8 : stm32wbxx_hal_wwdg.h
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

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  • Typedefs
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  • q
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  • s
  • t
  • u

- a -

  • ADC_ConversionStop() : stm32wbxx_hal_adc.c
  • ADC_Disable() : stm32wbxx_hal_adc.c
  • ADC_DMAConvCplt() : stm32wbxx_hal_adc.c
  • ADC_DMAError() : stm32wbxx_hal_adc.c
  • ADC_DMAHalfConvCplt() : stm32wbxx_hal_adc.c
  • ADC_Enable() : stm32wbxx_hal_adc.c
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

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  • Functions
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- c -

  • CRC_Handle_16() : stm32wbxx_hal_crc.c
  • CRC_Handle_8() : stm32wbxx_hal_crc.c
  • CRYP_AES_Decrypt() : stm32wbxx_hal_cryp.c
  • CRYP_AES_Decrypt_DMA() : stm32wbxx_hal_cryp.c
  • CRYP_AES_Decrypt_IT() : stm32wbxx_hal_cryp.c
  • CRYP_AES_Encrypt() : stm32wbxx_hal_cryp.c
  • CRYP_AES_Encrypt_IT() : stm32wbxx_hal_cryp.c
  • CRYP_AES_IT() : stm32wbxx_hal_cryp.c
  • CRYP_AES_ProcessData() : stm32wbxx_hal_cryp.c
  • CRYP_AESCCM_Process() : stm32wbxx_hal_cryp.c
  • CRYP_AESCCM_Process_DMA() : stm32wbxx_hal_cryp.c
  • CRYP_AESCCM_Process_IT() : stm32wbxx_hal_cryp.c
  • CRYP_AESGCM_Process() : stm32wbxx_hal_cryp.c
  • CRYP_AESGCM_Process_DMA() : stm32wbxx_hal_cryp.c
  • CRYP_AESGCM_Process_IT() : stm32wbxx_hal_cryp.c
  • CRYP_DMAError() : stm32wbxx_hal_cryp.c
  • CRYP_DMAInCplt() : stm32wbxx_hal_cryp.c
  • CRYP_DMAOutCplt() : stm32wbxx_hal_cryp.c
  • CRYP_GCMCCM_SetHeaderPhase() : stm32wbxx_hal_cryp.c
  • CRYP_GCMCCM_SetHeaderPhase_DMA() : stm32wbxx_hal_cryp.c
  • CRYP_GCMCCM_SetHeaderPhase_IT() : stm32wbxx_hal_cryp.c
  • CRYP_GCMCCM_SetPayloadPhase_IT() : stm32wbxx_hal_cryp.c
  • CRYP_SetDMAConfig() : stm32wbxx_hal_cryp.c
  • CRYP_SetKey() : stm32wbxx_hal_cryp.c
  • CRYP_WaitOnCCFlag() : stm32wbxx_hal_cryp.c
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

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- d -

  • DMA_CalcDMAMUXChannelBaseAndMask() : stm32wbxx_hal_dma.c
  • DMA_CalcDMAMUXRequestGenBaseAndMask() : stm32wbxx_hal_dma.c
  • DMA_SetConfig() : stm32wbxx_hal_dma.c
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

  • File List
  • Globals
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  • Functions
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  • Typedefs
  • Enumerations
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- f -

  • FLASH_AcknowledgePageErase() : stm32wbxx_hal_flash_ex.c
  • FLASH_FlushCaches() : stm32wbxx_hal_flash_ex.c
  • FLASH_MassErase() : stm32wbxx_hal_flash_ex.c
  • FLASH_OB_GetC2BootResetConfig() : stm32wbxx_hal_flash_ex.c
  • FLASH_OB_GetIPCCBufferAddr() : stm32wbxx_hal_flash_ex.c
  • FLASH_OB_GetPCROP() : stm32wbxx_hal_flash_ex.c
  • FLASH_OB_GetRDP() : stm32wbxx_hal_flash_ex.c
  • FLASH_OB_GetSecureMemoryConfig() : stm32wbxx_hal_flash_ex.c
  • FLASH_OB_GetUser() : stm32wbxx_hal_flash_ex.c
  • FLASH_OB_GetWRP() : stm32wbxx_hal_flash_ex.c
  • FLASH_OB_IPCCBufferAddrConfig() : stm32wbxx_hal_flash_ex.c
  • FLASH_OB_OptrConfig() : stm32wbxx_hal_flash_ex.c
  • FLASH_OB_PCROP1AConfig() : stm32wbxx_hal_flash_ex.c
  • FLASH_OB_PCROP1BConfig() : stm32wbxx_hal_flash_ex.c
  • FLASH_OB_ProceedWriteOperation() : stm32wbxx_hal_flash_ex.c
  • FLASH_OB_SecureConfig() : stm32wbxx_hal_flash_ex.c
  • FLASH_OB_WRPConfig() : stm32wbxx_hal_flash_ex.c
  • FLASH_PageErase() : stm32wbxx_hal_flash_ex.c
  • FLASH_Program_DoubleWord() : stm32wbxx_hal_flash.c
  • FLASH_Program_Fast() : stm32wbxx_hal_flash.c
  • FLASH_WaitForLastOperation() : stm32wbxx_hal_flash.h , stm32wbxx_hal_flash.c
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

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  • Typedefs
  • Enumerations
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  • u

- h -

  • HAL_ADC_AnalogWDGConfig() : stm32wbxx_hal_adc.c
  • HAL_ADC_ConfigChannel() : stm32wbxx_hal_adc.c
  • HAL_ADC_ConvCpltCallback() : stm32wbxx_hal_adc.c
  • HAL_ADC_ConvHalfCpltCallback() : stm32wbxx_hal_adc.c
  • HAL_ADC_DeInit() : stm32wbxx_hal_adc.c
  • HAL_ADC_ErrorCallback() : stm32wbxx_hal_adc.c
  • HAL_ADC_GetError() : stm32wbxx_hal_adc.c
  • HAL_ADC_GetState() : stm32wbxx_hal_adc.c
  • HAL_ADC_GetValue() : stm32wbxx_hal_adc.c
  • HAL_ADC_Init() : stm32wbxx_hal_adc.c
  • HAL_ADC_IRQHandler() : stm32wbxx_hal_adc.c
  • HAL_ADC_LevelOutOfWindowCallback() : stm32wbxx_hal_adc.c
  • HAL_ADC_MspDeInit() : stm32wbxx_hal_adc.c
  • HAL_ADC_MspInit() : stm32wbxx_hal_adc.c
  • HAL_ADC_PollForConversion() : stm32wbxx_hal_adc.c
  • HAL_ADC_PollForEvent() : stm32wbxx_hal_adc.c
  • HAL_ADC_RegisterCallback() : stm32wbxx_hal_adc.c
  • HAL_ADC_Start() : stm32wbxx_hal_adc.c
  • HAL_ADC_Start_DMA() : stm32wbxx_hal_adc.c
  • HAL_ADC_Start_IT() : stm32wbxx_hal_adc.c
  • HAL_ADC_Stop() : stm32wbxx_hal_adc.c
  • HAL_ADC_Stop_DMA() : stm32wbxx_hal_adc.c
  • HAL_ADC_Stop_IT() : stm32wbxx_hal_adc.c
  • HAL_ADC_UnRegisterCallback() : stm32wbxx_hal_adc.c
  • HAL_ADCEx_Calibration_GetValue() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_Calibration_SetValue() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_Calibration_Start() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_DisableInjectedQueue() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_DisableVoltageRegulator() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_EnableInjectedQueue() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_EndOfSamplingCallback() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_EnterADCDeepPowerDownMode() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_InjectedConfigChannel() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_InjectedConvCpltCallback() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_InjectedGetValue() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_InjectedPollForConversion() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_InjectedQueueOverflowCallback() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStart() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStart_IT() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStop() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStop_IT() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_LevelOutOfWindow2Callback() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_LevelOutOfWindow3Callback() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_RegularStop() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_RegularStop_DMA() : stm32wbxx_hal_adc_ex.c
  • HAL_ADCEx_RegularStop_IT() : stm32wbxx_hal_adc_ex.c
  • HAL_COMP_DeInit() : stm32wbxx_hal_comp.c
  • HAL_COMP_GetError() : stm32wbxx_hal_comp.c
  • HAL_COMP_GetOutputLevel() : stm32wbxx_hal_comp.c
  • HAL_COMP_GetState() : stm32wbxx_hal_comp.c
  • HAL_COMP_Init() : stm32wbxx_hal_comp.c
  • HAL_COMP_IRQHandler() : stm32wbxx_hal_comp.c
  • HAL_COMP_Lock() : stm32wbxx_hal_comp.c
  • HAL_COMP_MspDeInit() : stm32wbxx_hal_comp.c
  • HAL_COMP_MspInit() : stm32wbxx_hal_comp.c
  • HAL_COMP_RegisterCallback() : stm32wbxx_hal_comp.c
  • HAL_COMP_Start() : stm32wbxx_hal_comp.c
  • HAL_COMP_Stop() : stm32wbxx_hal_comp.c
  • HAL_COMP_TriggerCallback() : stm32wbxx_hal_comp.c
  • HAL_COMP_UnRegisterCallback() : stm32wbxx_hal_comp.c
  • HAL_CRC_Accumulate() : stm32wbxx_hal_crc.c
  • HAL_CRC_Calculate() : stm32wbxx_hal_crc.c
  • HAL_CRC_DeInit() : stm32wbxx_hal_crc.c
  • HAL_CRC_GetState() : stm32wbxx_hal_crc.c
  • HAL_CRC_Init() : stm32wbxx_hal_crc.c
  • HAL_CRC_MspDeInit() : stm32wbxx_hal_crc.c
  • HAL_CRC_MspInit() : stm32wbxx_hal_crc.c
  • HAL_CRCEx_Input_Data_Reverse() : stm32wbxx_hal_crc_ex.c
  • HAL_CRCEx_Output_Data_Reverse() : stm32wbxx_hal_crc_ex.c
  • HAL_CRCEx_Polynomial_Set() : stm32wbxx_hal_crc_ex.c
  • HAL_CRYP_Decrypt() : stm32wbxx_hal_cryp.c
  • HAL_CRYP_Decrypt_DMA() : stm32wbxx_hal_cryp.c
  • HAL_CRYP_Decrypt_IT() : stm32wbxx_hal_cryp.c
  • HAL_CRYP_DeInit() : stm32wbxx_hal_cryp.c
  • HAL_CRYP_Encrypt() : stm32wbxx_hal_cryp.c
  • HAL_CRYP_Encrypt_DMA() : stm32wbxx_hal_cryp.c
  • HAL_CRYP_Encrypt_IT() : stm32wbxx_hal_cryp.c
  • HAL_CRYP_ErrorCallback() : stm32wbxx_hal_cryp.c
  • HAL_CRYP_GetConfig() : stm32wbxx_hal_cryp.c
  • HAL_CRYP_GetError() : stm32wbxx_hal_cryp.c
  • HAL_CRYP_GetState() : stm32wbxx_hal_cryp.c
  • HAL_CRYP_InCpltCallback() : stm32wbxx_hal_cryp.c
  • HAL_CRYP_Init() : stm32wbxx_hal_cryp.c
  • HAL_CRYP_IRQHandler() : stm32wbxx_hal_cryp.c
  • HAL_CRYP_MspDeInit() : stm32wbxx_hal_cryp.c
  • HAL_CRYP_MspInit() : stm32wbxx_hal_cryp.c
  • HAL_CRYP_OutCpltCallback() : stm32wbxx_hal_cryp.c
  • HAL_CRYP_RegisterCallback() : stm32wbxx_hal_cryp.c
  • HAL_CRYP_SetConfig() : stm32wbxx_hal_cryp.c
  • HAL_CRYP_UnRegisterCallback() : stm32wbxx_hal_cryp.c
  • HAL_CRYPEx_AESCCM_GenerateAuthTAG() : stm32wbxx_hal_cryp_ex.c
  • HAL_CRYPEx_AESGCM_GenerateAuthTAG() : stm32wbxx_hal_cryp_ex.c
  • HAL_CRYPEx_DisableAutoKeyDerivation() : stm32wbxx_hal_cryp_ex.c
  • HAL_CRYPEx_EnableAutoKeyDerivation() : stm32wbxx_hal_cryp_ex.c
  • HAL_DBGMCU_DisableDBGSleepMode() : stm32wbxx_hal.c
  • HAL_DBGMCU_DisableDBGStandbyMode() : stm32wbxx_hal.c
  • HAL_DBGMCU_DisableDBGStopMode() : stm32wbxx_hal.c
  • HAL_DBGMCU_EnableDBGSleepMode() : stm32wbxx_hal.c
  • HAL_DBGMCU_EnableDBGStandbyMode() : stm32wbxx_hal.c
  • HAL_DBGMCU_EnableDBGStopMode() : stm32wbxx_hal.c
  • HAL_DeInit() : stm32wbxx_hal.c
  • HAL_Delay() : stm32wbxx_hal.c
  • HAL_DMA_Abort() : stm32wbxx_hal_dma.c
  • HAL_DMA_Abort_IT() : stm32wbxx_hal_dma.c
  • HAL_DMA_DeInit() : stm32wbxx_hal_dma.c
  • HAL_DMA_GetError() : stm32wbxx_hal_dma.c
  • HAL_DMA_GetState() : stm32wbxx_hal_dma.c
  • HAL_DMA_Init() : stm32wbxx_hal_dma.c
  • HAL_DMA_IRQHandler() : stm32wbxx_hal_dma.c
  • HAL_DMA_PollForTransfer() : stm32wbxx_hal_dma.c
  • HAL_DMA_RegisterCallback() : stm32wbxx_hal_dma.c
  • HAL_DMA_Start() : stm32wbxx_hal_dma.c
  • HAL_DMA_Start_IT() : stm32wbxx_hal_dma.c
  • HAL_DMA_UnRegisterCallback() : stm32wbxx_hal_dma.c
  • HAL_DMAEx_ConfigMuxRequestGenerator() : stm32wbxx_hal_dma_ex.c
  • HAL_DMAEx_ConfigMuxSync() : stm32wbxx_hal_dma_ex.c
  • HAL_DMAEx_DisableMuxRequestGenerator() : stm32wbxx_hal_dma_ex.c
  • HAL_DMAEx_EnableMuxRequestGenerator() : stm32wbxx_hal_dma_ex.c
  • HAL_DMAEx_MUX_IRQHandler() : stm32wbxx_hal_dma_ex.c
  • HAL_EXTI_ClearConfigLine() : stm32wbxx_hal_exti.c
  • HAL_EXTI_ClearPending() : stm32wbxx_hal_exti.c
  • HAL_EXTI_GenerateSWI() : stm32wbxx_hal_exti.c
  • HAL_EXTI_GetConfigLine() : stm32wbxx_hal_exti.c
  • HAL_EXTI_GetHandle() : stm32wbxx_hal_exti.c
  • HAL_EXTI_GetPending() : stm32wbxx_hal_exti.c
  • HAL_EXTI_IRQHandler() : stm32wbxx_hal_exti.c
  • HAL_EXTI_RegisterCallback() : stm32wbxx_hal_exti.c
  • HAL_EXTI_SetConfigLine() : stm32wbxx_hal_exti.c
  • HAL_FLASH_EndOfOperationCallback() : stm32wbxx_hal_flash.c
  • HAL_FLASH_GetError() : stm32wbxx_hal_flash.c
  • HAL_FLASH_IRQHandler() : stm32wbxx_hal_flash.c
  • HAL_FLASH_Lock() : stm32wbxx_hal_flash.c
  • HAL_FLASH_OB_Launch() : stm32wbxx_hal_flash.c
  • HAL_FLASH_OB_Lock() : stm32wbxx_hal_flash.c
  • HAL_FLASH_OB_Unlock() : stm32wbxx_hal_flash.c
  • HAL_FLASH_OperationErrorCallback() : stm32wbxx_hal_flash.c
  • HAL_FLASH_Program() : stm32wbxx_hal_flash.c
  • HAL_FLASH_Program_IT() : stm32wbxx_hal_flash.c
  • HAL_FLASH_Unlock() : stm32wbxx_hal_flash.c
  • HAL_FLASHEx_AllowOperation() : stm32wbxx_hal_flash_ex.c
  • HAL_FLASHEx_Erase() : stm32wbxx_hal_flash_ex.c
  • HAL_FLASHEx_Erase_IT() : stm32wbxx_hal_flash_ex.c
  • HAL_FLASHEx_FlashEmptyCheck() : stm32wbxx_hal_flash_ex.c
  • HAL_FLASHEx_ForceFlashEmpty() : stm32wbxx_hal_flash_ex.c
  • HAL_FLASHEx_IsOperationSuspended() : stm32wbxx_hal_flash_ex.c
  • HAL_FLASHEx_OBGetConfig() : stm32wbxx_hal_flash_ex.c
  • HAL_FLASHEx_OBProgram() : stm32wbxx_hal_flash_ex.c
  • HAL_FLASHEx_SuspendOperation() : stm32wbxx_hal_flash_ex.c
  • HAL_GetDEVID() : stm32wbxx_hal.c
  • HAL_GetHalVersion() : stm32wbxx_hal.c
  • HAL_GetREVID() : stm32wbxx_hal.c
  • HAL_GetTick() : stm32wbxx_hal.c
  • HAL_GetTickFreq() : stm32wbxx_hal.c
  • HAL_GetTickPrio() : stm32wbxx_hal.c
  • HAL_GetUIDw0() : stm32wbxx_hal.c
  • HAL_GetUIDw1() : stm32wbxx_hal.c
  • HAL_GetUIDw2() : stm32wbxx_hal.c
  • HAL_GPIO_DeInit() : stm32wbxx_hal_gpio.c
  • HAL_GPIO_EXTI_Callback() : stm32wbxx_hal_gpio.c
  • HAL_GPIO_EXTI_IRQHandler() : stm32wbxx_hal_gpio.c
  • HAL_GPIO_Init() : stm32wbxx_hal_gpio.c
  • HAL_GPIO_LockPin() : stm32wbxx_hal_gpio.c
  • HAL_GPIO_ReadPin() : stm32wbxx_hal_gpio.c
  • HAL_GPIO_TogglePin() : stm32wbxx_hal_gpio.c
  • HAL_GPIO_WritePin() : stm32wbxx_hal_gpio.c
  • HAL_HalfDuplex_EnableReceiver() : stm32wbxx_hal_uart.c
  • HAL_HalfDuplex_EnableTransmitter() : stm32wbxx_hal_uart.c
  • HAL_HalfDuplex_Init() : stm32wbxx_hal_uart.c
  • HAL_HSEM_ActivateNotification() : stm32wbxx_hal_hsem.c
  • HAL_HSEM_DeactivateNotification() : stm32wbxx_hal_hsem.c
  • HAL_HSEM_FastTake() : stm32wbxx_hal_hsem.c
  • HAL_HSEM_FreeCallback() : stm32wbxx_hal_hsem.c
  • HAL_HSEM_GetClearKey() : stm32wbxx_hal_hsem.c
  • HAL_HSEM_IRQHandler() : stm32wbxx_hal_hsem.c
  • HAL_HSEM_IsSemTaken() : stm32wbxx_hal_hsem.c
  • HAL_HSEM_Release() : stm32wbxx_hal_hsem.c
  • HAL_HSEM_ReleaseAll() : stm32wbxx_hal_hsem.c
  • HAL_HSEM_SetClearKey() : stm32wbxx_hal_hsem.c
  • HAL_HSEM_Take() : stm32wbxx_hal_hsem.c
  • HAL_I2C_AbortCpltCallback() : stm32wbxx_hal_i2c.c
  • HAL_I2C_AddrCallback() : stm32wbxx_hal_i2c.c
  • HAL_I2C_DeInit() : stm32wbxx_hal_i2c.c
  • HAL_I2C_DisableListen_IT() : stm32wbxx_hal_i2c.c
  • HAL_I2C_EnableListen_IT() : stm32wbxx_hal_i2c.c
  • HAL_I2C_ER_IRQHandler() : stm32wbxx_hal_i2c.c
  • HAL_I2C_ErrorCallback() : stm32wbxx_hal_i2c.c
  • HAL_I2C_EV_IRQHandler() : stm32wbxx_hal_i2c.c
  • HAL_I2C_GetError() : stm32wbxx_hal_i2c.c
  • HAL_I2C_GetMode() : stm32wbxx_hal_i2c.c
  • HAL_I2C_GetState() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Init() : stm32wbxx_hal_i2c.c
  • HAL_I2C_IsDeviceReady() : stm32wbxx_hal_i2c.c
  • HAL_I2C_ListenCpltCallback() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Master_Abort_IT() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Master_Receive() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Master_Receive_DMA() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Master_Receive_IT() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Master_Seq_Receive_DMA() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Master_Seq_Receive_IT() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Master_Seq_Transmit_DMA() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Master_Seq_Transmit_IT() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Master_Transmit() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Master_Transmit_DMA() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Master_Transmit_IT() : stm32wbxx_hal_i2c.c
  • HAL_I2C_MasterRxCpltCallback() : stm32wbxx_hal_i2c.c
  • HAL_I2C_MasterTxCpltCallback() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Mem_Read() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Mem_Read_DMA() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Mem_Read_IT() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Mem_Write() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Mem_Write_DMA() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Mem_Write_IT() : stm32wbxx_hal_i2c.c
  • HAL_I2C_MemRxCpltCallback() : stm32wbxx_hal_i2c.c
  • HAL_I2C_MemTxCpltCallback() : stm32wbxx_hal_i2c.c
  • HAL_I2C_MspDeInit() : stm32wbxx_hal_i2c.c
  • HAL_I2C_MspInit() : stm32wbxx_hal_i2c.c
  • HAL_I2C_RegisterAddrCallback() : stm32wbxx_hal_i2c.c
  • HAL_I2C_RegisterCallback() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Slave_Receive() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Slave_Receive_DMA() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Slave_Receive_IT() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Slave_Seq_Receive_DMA() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Slave_Seq_Receive_IT() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Slave_Seq_Transmit_DMA() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Slave_Seq_Transmit_IT() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Slave_Transmit() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_DMA() : stm32wbxx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_IT() : stm32wbxx_hal_i2c.c
  • HAL_I2C_SlaveRxCpltCallback() : stm32wbxx_hal_i2c.c
  • HAL_I2C_SlaveTxCpltCallback() : stm32wbxx_hal_i2c.c
  • HAL_I2C_UnRegisterAddrCallback() : stm32wbxx_hal_i2c.c
  • HAL_I2C_UnRegisterCallback() : stm32wbxx_hal_i2c.c
  • HAL_I2CEx_ConfigAnalogFilter() : stm32wbxx_hal_i2c_ex.c
  • HAL_I2CEx_ConfigDigitalFilter() : stm32wbxx_hal_i2c_ex.c
  • HAL_I2CEx_DisableFastModePlus() : stm32wbxx_hal_i2c_ex.c
  • HAL_I2CEx_DisableWakeUp() : stm32wbxx_hal_i2c_ex.c
  • HAL_I2CEx_EnableFastModePlus() : stm32wbxx_hal_i2c_ex.c
  • HAL_I2CEx_EnableWakeUp() : stm32wbxx_hal_i2c_ex.c
  • HAL_IncTick() : stm32wbxx_hal.c
  • HAL_Init() : stm32wbxx_hal.c
  • HAL_InitTick() : stm32wbxx_hal.c
  • HAL_IPCC_ActivateNotification() : stm32wbxx_hal_ipcc.c
  • HAL_IPCC_DeActivateNotification() : stm32wbxx_hal_ipcc.c
  • HAL_IPCC_DeInit() : stm32wbxx_hal_ipcc.c
  • HAL_IPCC_GetChannelStatus() : stm32wbxx_hal_ipcc.c
  • HAL_IPCC_GetState() : stm32wbxx_hal_ipcc.c
  • HAL_IPCC_Init() : stm32wbxx_hal_ipcc.c
  • HAL_IPCC_MspDeInit() : stm32wbxx_hal_ipcc.c
  • HAL_IPCC_MspInit() : stm32wbxx_hal_ipcc.c
  • HAL_IPCC_NotifyCPU() : stm32wbxx_hal_ipcc.c
  • HAL_IPCC_RX_IRQHandler() : stm32wbxx_hal_ipcc.c
  • HAL_IPCC_RxCallback() : stm32wbxx_hal_ipcc.c
  • HAL_IPCC_TX_IRQHandler() : stm32wbxx_hal_ipcc.c
  • HAL_IPCC_TxCallback() : stm32wbxx_hal_ipcc.c
  • HAL_IRDA_Abort() : stm32wbxx_hal_irda.c
  • HAL_IRDA_Abort_IT() : stm32wbxx_hal_irda.c
  • HAL_IRDA_AbortCpltCallback() : stm32wbxx_hal_irda.c
  • HAL_IRDA_AbortReceive() : stm32wbxx_hal_irda.c
  • HAL_IRDA_AbortReceive_IT() : stm32wbxx_hal_irda.c
  • HAL_IRDA_AbortReceiveCpltCallback() : stm32wbxx_hal_irda.c
  • HAL_IRDA_AbortTransmit() : stm32wbxx_hal_irda.c
  • HAL_IRDA_AbortTransmit_IT() : stm32wbxx_hal_irda.c
  • HAL_IRDA_AbortTransmitCpltCallback() : stm32wbxx_hal_irda.c
  • HAL_IRDA_DeInit() : stm32wbxx_hal_irda.c
  • HAL_IRDA_DMAPause() : stm32wbxx_hal_irda.c
  • HAL_IRDA_DMAResume() : stm32wbxx_hal_irda.c
  • HAL_IRDA_DMAStop() : stm32wbxx_hal_irda.c
  • HAL_IRDA_ErrorCallback() : stm32wbxx_hal_irda.c
  • HAL_IRDA_GetError() : stm32wbxx_hal_irda.c
  • HAL_IRDA_GetState() : stm32wbxx_hal_irda.c
  • HAL_IRDA_Init() : stm32wbxx_hal_irda.c
  • HAL_IRDA_IRQHandler() : stm32wbxx_hal_irda.c
  • HAL_IRDA_MspDeInit() : stm32wbxx_hal_irda.c
  • HAL_IRDA_MspInit() : stm32wbxx_hal_irda.c
  • HAL_IRDA_Receive() : stm32wbxx_hal_irda.c
  • HAL_IRDA_Receive_DMA() : stm32wbxx_hal_irda.c
  • HAL_IRDA_Receive_IT() : stm32wbxx_hal_irda.c
  • HAL_IRDA_RegisterCallback() : stm32wbxx_hal_irda.c
  • HAL_IRDA_RxCpltCallback() : stm32wbxx_hal_irda.c
  • HAL_IRDA_RxHalfCpltCallback() : stm32wbxx_hal_irda.c
  • HAL_IRDA_Transmit() : stm32wbxx_hal_irda.c
  • HAL_IRDA_Transmit_DMA() : stm32wbxx_hal_irda.c
  • HAL_IRDA_Transmit_IT() : stm32wbxx_hal_irda.c
  • HAL_IRDA_TxCpltCallback() : stm32wbxx_hal_irda.c
  • HAL_IRDA_TxHalfCpltCallback() : stm32wbxx_hal_irda.c
  • HAL_IRDA_UnRegisterCallback() : stm32wbxx_hal_irda.c
  • HAL_IWDG_Init() : stm32wbxx_hal_iwdg.c
  • HAL_IWDG_Refresh() : stm32wbxx_hal_iwdg.c
  • HAL_LCD_Clear() : stm32wbxx_hal_lcd.c
  • HAL_LCD_DeInit() : stm32wbxx_hal_lcd.c
  • HAL_LCD_GetError() : stm32wbxx_hal_lcd.c
  • HAL_LCD_GetState() : stm32wbxx_hal_lcd.c
  • HAL_LCD_Init() : stm32wbxx_hal_lcd.c
  • HAL_LCD_MspDeInit() : stm32wbxx_hal_lcd.c
  • HAL_LCD_MspInit() : stm32wbxx_hal_lcd.c
  • HAL_LCD_UpdateDisplayRequest() : stm32wbxx_hal_lcd.c
  • HAL_LCD_Write() : stm32wbxx_hal_lcd.c
  • HAL_LIN_Init() : stm32wbxx_hal_uart.c
  • HAL_LIN_SendBreak() : stm32wbxx_hal_uart.c
  • HAL_LPTIM_AutoReloadMatchCallback() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_AutoReloadWriteCallback() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_CompareMatchCallback() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_CompareWriteCallback() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_Counter_Start() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_Counter_Start_IT() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_Counter_Stop() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_Counter_Stop_IT() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_DeInit() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_DirectionDownCallback() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_DirectionUpCallback() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_Encoder_Start() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_Encoder_Start_IT() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_Encoder_Stop() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_Encoder_Stop_IT() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_GetState() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_Init() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_IRQHandler() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_MspDeInit() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_MspInit() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Start() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Start_IT() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Stop() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_OnePulse_Stop_IT() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_PWM_Start() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_PWM_Start_IT() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_PWM_Stop() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_PWM_Stop_IT() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_ReadAutoReload() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_ReadCompare() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_ReadCounter() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_RegisterCallback() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Start() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Start_IT() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Stop() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_SetOnce_Stop_IT() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Start() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Start_IT() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Stop() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_TimeOut_Stop_IT() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_TriggerCallback() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_LPTIM_UnRegisterCallback() : stm32wbxx_hal_lptim.c , stm32wbxx_hal_lptim.h
  • HAL_MPU_ConfigRegion() : stm32wbxx_hal_cortex.c
  • HAL_MPU_Disable() : stm32wbxx_hal_cortex.c
  • HAL_MPU_Enable() : stm32wbxx_hal_cortex.c
  • HAL_MspDeInit() : stm32wbxx_hal.c
  • HAL_MspInit() : stm32wbxx_hal.c
  • HAL_MultiProcessor_DisableMuteMode() : stm32wbxx_hal_uart.c
  • HAL_MultiProcessor_EnableMuteMode() : stm32wbxx_hal_uart.c
  • HAL_MultiProcessor_EnterMuteMode() : stm32wbxx_hal_uart.c
  • HAL_MultiProcessor_Init() : stm32wbxx_hal_uart.c
  • HAL_MultiProcessorEx_AddressLength_Set() : stm32wbxx_hal_uart_ex.c
  • HAL_NVIC_ClearPendingIRQ() : stm32wbxx_hal_cortex.c
  • HAL_NVIC_DisableIRQ() : stm32wbxx_hal_cortex.c
  • HAL_NVIC_EnableIRQ() : stm32wbxx_hal_cortex.c
  • HAL_NVIC_GetPendingIRQ() : stm32wbxx_hal_cortex.c
  • HAL_NVIC_GetPriority() : stm32wbxx_hal_cortex.c
  • HAL_NVIC_GetPriorityGrouping() : stm32wbxx_hal_cortex.c
  • HAL_NVIC_SetPendingIRQ() : stm32wbxx_hal_cortex.c
  • HAL_NVIC_SetPriority() : stm32wbxx_hal_cortex.c
  • HAL_NVIC_SetPriorityGrouping() : stm32wbxx_hal_cortex.c
  • HAL_NVIC_SystemReset() : stm32wbxx_hal_cortex.c
  • HAL_PCD_ActivateRemoteWakeup() : stm32wbxx_hal_pcd.c
  • HAL_PCD_ConnectCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_DataInStageCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_DataOutStageCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_DeActivateRemoteWakeup() : stm32wbxx_hal_pcd.c
  • HAL_PCD_DeInit() : stm32wbxx_hal_pcd.c
  • HAL_PCD_DevConnect() : stm32wbxx_hal_pcd.c
  • HAL_PCD_DevDisconnect() : stm32wbxx_hal_pcd.c
  • HAL_PCD_DisconnectCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_EP_Close() : stm32wbxx_hal_pcd.c
  • HAL_PCD_EP_ClrStall() : stm32wbxx_hal_pcd.c
  • HAL_PCD_EP_Flush() : stm32wbxx_hal_pcd.c
  • HAL_PCD_EP_GetRxCount() : stm32wbxx_hal_pcd.c
  • HAL_PCD_EP_Open() : stm32wbxx_hal_pcd.c
  • HAL_PCD_EP_Receive() : stm32wbxx_hal_pcd.c
  • HAL_PCD_EP_SetStall() : stm32wbxx_hal_pcd.c
  • HAL_PCD_EP_Transmit() : stm32wbxx_hal_pcd.c
  • HAL_PCD_GetState() : stm32wbxx_hal_pcd.c
  • HAL_PCD_Init() : stm32wbxx_hal_pcd.c
  • HAL_PCD_IRQHandler() : stm32wbxx_hal_pcd.c
  • HAL_PCD_ISOINIncompleteCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_ISOOUTIncompleteCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_MspDeInit() : stm32wbxx_hal_pcd.c
  • HAL_PCD_MspInit() : stm32wbxx_hal_pcd.c
  • HAL_PCD_RegisterBcdCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_RegisterCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_RegisterDataInStageCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_RegisterDataOutStageCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_RegisterIsoInIncpltCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_RegisterIsoOutIncpltCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_RegisterLpmCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_ResetCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_ResumeCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_SetAddress() : stm32wbxx_hal_pcd.c
  • HAL_PCD_SetupStageCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_SOFCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_Start() : stm32wbxx_hal_pcd.c
  • HAL_PCD_Stop() : stm32wbxx_hal_pcd.c
  • HAL_PCD_SuspendCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_UnRegisterBcdCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_UnRegisterCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_UnRegisterDataInStageCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_UnRegisterDataOutStageCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_UnRegisterIsoInIncpltCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_UnRegisterIsoOutIncpltCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCD_UnRegisterLpmCallback() : stm32wbxx_hal_pcd.c
  • HAL_PCDEx_ActivateBCD() : stm32wbxx_hal_pcd_ex.c
  • HAL_PCDEx_ActivateLPM() : stm32wbxx_hal_pcd_ex.c
  • HAL_PCDEx_BCD_Callback() : stm32wbxx_hal_pcd_ex.c
  • HAL_PCDEx_BCD_VBUSDetect() : stm32wbxx_hal_pcd_ex.c
  • HAL_PCDEx_DeActivateBCD() : stm32wbxx_hal_pcd_ex.c
  • HAL_PCDEx_DeActivateLPM() : stm32wbxx_hal_pcd_ex.c
  • HAL_PCDEx_LPM_Callback() : stm32wbxx_hal_pcd_ex.c
  • HAL_PCDEx_PMAConfig() : stm32wbxx_hal_pcd_ex.c
  • HAL_PKA_Abort() : stm32wbxx_hal_pka.c
  • HAL_PKA_Add() : stm32wbxx_hal_pka.c
  • HAL_PKA_Add_IT() : stm32wbxx_hal_pka.c
  • HAL_PKA_Arithmetic_GetResult() : stm32wbxx_hal_pka.c
  • HAL_PKA_Cmp() : stm32wbxx_hal_pka.c
  • HAL_PKA_Cmp_IT() : stm32wbxx_hal_pka.c
  • HAL_PKA_DeInit() : stm32wbxx_hal_pka.c
  • HAL_PKA_ECCMul() : stm32wbxx_hal_pka.c
  • HAL_PKA_ECCMul_GetResult() : stm32wbxx_hal_pka.c
  • HAL_PKA_ECCMul_IT() : stm32wbxx_hal_pka.c
  • HAL_PKA_ECCMulFastMode() : stm32wbxx_hal_pka.c
  • HAL_PKA_ECCMulFastMode_IT() : stm32wbxx_hal_pka.c
  • HAL_PKA_ECDSASign() : stm32wbxx_hal_pka.c
  • HAL_PKA_ECDSASign_GetResult() : stm32wbxx_hal_pka.c
  • HAL_PKA_ECDSASign_IT() : stm32wbxx_hal_pka.c
  • HAL_PKA_ECDSAVerif() : stm32wbxx_hal_pka.c
  • HAL_PKA_ECDSAVerif_IsValidSignature() : stm32wbxx_hal_pka.c
  • HAL_PKA_ECDSAVerif_IT() : stm32wbxx_hal_pka.c
  • HAL_PKA_ErrorCallback() : stm32wbxx_hal_pka.c
  • HAL_PKA_GetError() : stm32wbxx_hal_pka.c
  • HAL_PKA_GetState() : stm32wbxx_hal_pka.c
  • HAL_PKA_Init() : stm32wbxx_hal_pka.c
  • HAL_PKA_IRQHandler() : stm32wbxx_hal_pka.c
  • HAL_PKA_ModAdd() : stm32wbxx_hal_pka.c
  • HAL_PKA_ModAdd_IT() : stm32wbxx_hal_pka.c
  • HAL_PKA_ModExp() : stm32wbxx_hal_pka.c
  • HAL_PKA_ModExp_GetResult() : stm32wbxx_hal_pka.c
  • HAL_PKA_ModExp_IT() : stm32wbxx_hal_pka.c
  • HAL_PKA_ModExpFastMode() : stm32wbxx_hal_pka.c
  • HAL_PKA_ModExpFastMode_IT() : stm32wbxx_hal_pka.c
  • HAL_PKA_ModInv() : stm32wbxx_hal_pka.c
  • HAL_PKA_ModInv_IT() : stm32wbxx_hal_pka.c
  • HAL_PKA_ModRed() : stm32wbxx_hal_pka.c
  • HAL_PKA_ModRed_IT() : stm32wbxx_hal_pka.c
  • HAL_PKA_ModSub() : stm32wbxx_hal_pka.c
  • HAL_PKA_ModSub_IT() : stm32wbxx_hal_pka.c
  • HAL_PKA_MontgomeryMul() : stm32wbxx_hal_pka.c
  • HAL_PKA_MontgomeryMul_IT() : stm32wbxx_hal_pka.c
  • HAL_PKA_MontgomeryParam() : stm32wbxx_hal_pka.c
  • HAL_PKA_MontgomeryParam_GetResult() : stm32wbxx_hal_pka.c
  • HAL_PKA_MontgomeryParam_IT() : stm32wbxx_hal_pka.c
  • HAL_PKA_MspDeInit() : stm32wbxx_hal_pka.c
  • HAL_PKA_MspInit() : stm32wbxx_hal_pka.c
  • HAL_PKA_Mul() : stm32wbxx_hal_pka.c
  • HAL_PKA_Mul_IT() : stm32wbxx_hal_pka.c
  • HAL_PKA_OperationCpltCallback() : stm32wbxx_hal_pka.c
  • HAL_PKA_PointCheck() : stm32wbxx_hal_pka.c
  • HAL_PKA_PointCheck_IsOnCurve() : stm32wbxx_hal_pka.c
  • HAL_PKA_PointCheck_IT() : stm32wbxx_hal_pka.c
  • HAL_PKA_RAMReset() : stm32wbxx_hal_pka.c
  • HAL_PKA_RegisterCallback() : stm32wbxx_hal_pka.c
  • HAL_PKA_RSACRTExp() : stm32wbxx_hal_pka.c
  • HAL_PKA_RSACRTExp_GetResult() : stm32wbxx_hal_pka.c
  • HAL_PKA_RSACRTExp_IT() : stm32wbxx_hal_pka.c
  • HAL_PKA_Sub() : stm32wbxx_hal_pka.c
  • HAL_PKA_Sub_IT() : stm32wbxx_hal_pka.c
  • HAL_PKA_UnRegisterCallback() : stm32wbxx_hal_pka.c
  • HAL_PWR_ConfigPVD() : stm32wbxx_hal_pwr.c
  • HAL_PWR_DeInit() : stm32wbxx_hal_pwr.c
  • HAL_PWR_DisableBkUpAccess() : stm32wbxx_hal_pwr.c
  • HAL_PWR_DisablePVD() : stm32wbxx_hal_pwr.c
  • HAL_PWR_DisableSEVOnPend() : stm32wbxx_hal_pwr.c
  • HAL_PWR_DisableSleepOnExit() : stm32wbxx_hal_pwr.c
  • HAL_PWR_DisableWakeUpPin() : stm32wbxx_hal_pwr.c
  • HAL_PWR_EnableBkUpAccess() : stm32wbxx_hal_pwr.c
  • HAL_PWR_EnablePVD() : stm32wbxx_hal_pwr.c
  • HAL_PWR_EnableSEVOnPend() : stm32wbxx_hal_pwr.c
  • HAL_PWR_EnableSleepOnExit() : stm32wbxx_hal_pwr.c
  • HAL_PWR_EnableWakeUpPin() : stm32wbxx_hal_pwr.c
  • HAL_PWR_EnterSLEEPMode() : stm32wbxx_hal_pwr.c
  • HAL_PWR_EnterSTANDBYMode() : stm32wbxx_hal_pwr.c
  • HAL_PWR_EnterSTOPMode() : stm32wbxx_hal_pwr.c
  • HAL_PWR_PVDCallback() : stm32wbxx_hal_pwr.c
  • HAL_PWREx_ClearWakeupFlag() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_ConfigPVM() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_ConfigSMPS() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_ControlVoltageScaling() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_Disable802ActivityIT() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_DisableBatteryCharging() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_DisableBLEActivityIT() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_DisableBORH_SMPSBypassIT() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_DisableFlashPowerDown() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_DisableGPIOPullDown() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_DisableGPIOPullUp() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_DisableHOLDC2IT() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_DisableInternalWakeUpLine() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_DisableLowPowerRunMode() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_DisablePullUpPullDownConfig() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_DisablePVM1() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_DisablePVM3() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_DisableRFPhaseIT() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_DisableSRAMRetention() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_DisableVddUSB() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_Enable802ActivityIT() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnableBatteryCharging() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnableBLEActivityIT() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnableBORH_SMPSBypassIT() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnableFlashPowerDown() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnableGPIOPullDown() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnableGPIOPullUp() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnableHOLDC2IT() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnableInternalWakeUpLine() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnableLowPowerRunMode() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnablePullUpPullDownConfig() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnablePVM1() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnablePVM3() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnableRFPhaseIT() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnableSRAMRetention() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnableVddUSB() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnableWakeUpPin() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnterSHUTDOWNMode() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnterSTOP0Mode() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnterSTOP1Mode() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_EnterSTOP2Mode() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_GetBORConfig() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_GetVoltageRange() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_GetWakeupFlag() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_HoldCore() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_PVD_PVM_IRQHandler() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_PVM1Callback() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_PVM3Callback() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_ReleaseCore() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_SetBORConfig() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_SMPS_GetEffectiveMode() : stm32wbxx_hal_pwr_ex.c
  • HAL_PWREx_SMPS_SetMode() : stm32wbxx_hal_pwr_ex.c
  • HAL_QSPI_Abort() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_Abort_IT() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_AbortCpltCallback() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_AutoPolling() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_AutoPolling_IT() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_CmdCpltCallback() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_Command() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_Command_IT() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_DeInit() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_ErrorCallback() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_FifoThresholdCallback() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_GetError() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_GetFifoThreshold() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_GetState() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_Init() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_IRQHandler() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_MemoryMapped() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_MspDeInit() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_MspInit() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_Receive() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_Receive_DMA() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_Receive_IT() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_RegisterCallback() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_RxCpltCallback() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_RxHalfCpltCallback() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_SetFifoThreshold() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_SetTimeout() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_StatusMatchCallback() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_TimeOutCallback() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_Transmit() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_Transmit_DMA() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_Transmit_IT() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_TxCpltCallback() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_TxHalfCpltCallback() : stm32wbxx_hal_qspi.c
  • HAL_QSPI_UnRegisterCallback() : stm32wbxx_hal_qspi.c
  • HAL_RCC_ClockConfig() : stm32wbxx_hal_rcc.c
  • HAL_RCC_CSSCallback() : stm32wbxx_hal_rcc.c
  • HAL_RCC_DeInit() : stm32wbxx_hal_rcc.c
  • HAL_RCC_EnableCSS() : stm32wbxx_hal_rcc.c
  • HAL_RCC_GetClockConfig() : stm32wbxx_hal_rcc.c
  • HAL_RCC_GetHCLK2Freq() : stm32wbxx_hal_rcc.c
  • HAL_RCC_GetHCLK4Freq() : stm32wbxx_hal_rcc.c
  • HAL_RCC_GetHCLKFreq() : stm32wbxx_hal_rcc.c
  • HAL_RCC_GetOscConfig() : stm32wbxx_hal_rcc.c
  • HAL_RCC_GetPCLK1Freq() : stm32wbxx_hal_rcc.c
  • HAL_RCC_GetPCLK2Freq() : stm32wbxx_hal_rcc.c
  • HAL_RCC_GetSysClockFreq() : stm32wbxx_hal_rcc.c
  • HAL_RCC_MCOConfig() : stm32wbxx_hal_rcc.c
  • HAL_RCC_NMI_IRQHandler() : stm32wbxx_hal_rcc.c
  • HAL_RCC_OscConfig() : stm32wbxx_hal_rcc.c
  • HAL_RCCEx_CRS_ErrorCallback() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_ExpectedSyncCallback() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_IRQHandler() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_SyncOkCallback() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_CRS_SyncWarnCallback() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_CRSConfig() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_CRSGetSynchronizationInfo() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_CRSSoftwareSynchronizationGenerate() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_CRSWaitSynchronization() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_DisableLSCO() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_DisableLSECSS() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_DisableMSIPLLMode() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_DisablePLLSAI1() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_EnableLSCO() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_EnableLSECSS() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_EnableLSECSS_IT() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_EnableMSIPLLMode() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_EnablePLLSAI1() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_GetPeriphCLKConfig() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_GetPeriphCLKFreq() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_GetRngCLKSource() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_LSCOConfig() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_LSECSS_Callback() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_LSECSS_IRQHandler() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_PeriphCLKConfig() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_TrimOsc() : stm32wbxx_hal_rcc_ex.c
  • HAL_RCCEx_WakeUpStopCLKConfig() : stm32wbxx_hal_rcc_ex.c
  • HAL_ResumeTick() : stm32wbxx_hal.c
  • HAL_RNG_DeInit() : stm32wbxx_hal_rng.c
  • HAL_RNG_ErrorCallback() : stm32wbxx_hal_rng.c
  • HAL_RNG_GenerateRandomNumber() : stm32wbxx_hal_rng.c
  • HAL_RNG_GenerateRandomNumber_IT() : stm32wbxx_hal_rng.c
  • HAL_RNG_GetError() : stm32wbxx_hal_rng.c
  • HAL_RNG_GetState() : stm32wbxx_hal_rng.c
  • HAL_RNG_Init() : stm32wbxx_hal_rng.c
  • HAL_RNG_IRQHandler() : stm32wbxx_hal_rng.c
  • HAL_RNG_MspDeInit() : stm32wbxx_hal_rng.c
  • HAL_RNG_MspInit() : stm32wbxx_hal_rng.c
  • HAL_RNG_ReadLastRandomNumber() : stm32wbxx_hal_rng.c
  • HAL_RNG_ReadyDataCallback() : stm32wbxx_hal_rng.c
  • HAL_RNG_RegisterCallback() : stm32wbxx_hal_rng.c
  • HAL_RNG_RegisterReadyDataCallback() : stm32wbxx_hal_rng.c
  • HAL_RNG_UnRegisterCallback() : stm32wbxx_hal_rng.c
  • HAL_RNG_UnRegisterReadyDataCallback() : stm32wbxx_hal_rng.c
  • HAL_RS485Ex_Init() : stm32wbxx_hal_uart_ex.c
  • HAL_RTC_AlarmAEventCallback() : stm32wbxx_hal_rtc.c
  • HAL_RTC_AlarmIRQHandler() : stm32wbxx_hal_rtc.c
  • HAL_RTC_DeactivateAlarm() : stm32wbxx_hal_rtc.c
  • HAL_RTC_DeInit() : stm32wbxx_hal_rtc.c
  • HAL_RTC_GetAlarm() : stm32wbxx_hal_rtc.c
  • HAL_RTC_GetDate() : stm32wbxx_hal_rtc.c
  • HAL_RTC_GetState() : stm32wbxx_hal_rtc.c
  • HAL_RTC_GetTime() : stm32wbxx_hal_rtc.c
  • HAL_RTC_Init() : stm32wbxx_hal_rtc.c
  • HAL_RTC_MspDeInit() : stm32wbxx_hal_rtc.c
  • HAL_RTC_MspInit() : stm32wbxx_hal_rtc.c
  • HAL_RTC_PollForAlarmAEvent() : stm32wbxx_hal_rtc.c
  • HAL_RTC_RegisterCallback() : stm32wbxx_hal_rtc.c
  • HAL_RTC_SetAlarm() : stm32wbxx_hal_rtc.c
  • HAL_RTC_SetAlarm_IT() : stm32wbxx_hal_rtc.c
  • HAL_RTC_SetDate() : stm32wbxx_hal_rtc.c
  • HAL_RTC_SetTime() : stm32wbxx_hal_rtc.c
  • HAL_RTC_UnRegisterCallback() : stm32wbxx_hal_rtc.c
  • HAL_RTC_WaitForSynchro() : stm32wbxx_hal_rtc.c
  • HAL_RTCEx_AlarmBEventCallback() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_BKUPRead() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_BKUPWrite() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateCalibrationOutPut() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateInternalTimeStamp() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateRefClock() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateTamper() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateTimeStamp() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateWakeUpTimer() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_DisableBypassShadow() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_EnableBypassShadow() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_GetTimeStamp() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_GetWakeUpTimer() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_PollForAlarmBEvent() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamper1Event() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamper2Event() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamper3Event() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTimeStampEvent() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_PollForWakeUpTimerEvent() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_SetCalibrationOutPut() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_SetInternalTimeStamp() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_SetRefClock() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_SetSmoothCalib() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_SetSynchroShift() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_SetTamper() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_SetTamper_IT() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_SetTimeStamp() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_SetTimeStamp_IT() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_SetWakeUpTimer() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_SetWakeUpTimer_IT() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper1EventCallback() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper2EventCallback() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper3EventCallback() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_TamperTimeStampIRQHandler() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_TimeStampEventCallback() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_WakeUpTimerEventCallback() : stm32wbxx_hal_rtc_ex.c
  • HAL_RTCEx_WakeUpTimerIRQHandler() : stm32wbxx_hal_rtc_ex.c
  • HAL_SAI_Abort() : stm32wbxx_hal_sai.c
  • HAL_SAI_DeInit() : stm32wbxx_hal_sai.c
  • HAL_SAI_DisableRxMuteMode() : stm32wbxx_hal_sai.c
  • HAL_SAI_DisableTxMuteMode() : stm32wbxx_hal_sai.c
  • HAL_SAI_DMAPause() : stm32wbxx_hal_sai.c
  • HAL_SAI_DMAResume() : stm32wbxx_hal_sai.c
  • HAL_SAI_DMAStop() : stm32wbxx_hal_sai.c
  • HAL_SAI_EnableRxMuteMode() : stm32wbxx_hal_sai.c
  • HAL_SAI_EnableTxMuteMode() : stm32wbxx_hal_sai.c
  • HAL_SAI_ErrorCallback() : stm32wbxx_hal_sai.c
  • HAL_SAI_GetError() : stm32wbxx_hal_sai.c
  • HAL_SAI_GetState() : stm32wbxx_hal_sai.c
  • HAL_SAI_Init() : stm32wbxx_hal_sai.c
  • HAL_SAI_InitProtocol() : stm32wbxx_hal_sai.c
  • HAL_SAI_IRQHandler() : stm32wbxx_hal_sai.c
  • HAL_SAI_MspDeInit() : stm32wbxx_hal_sai.c
  • HAL_SAI_MspInit() : stm32wbxx_hal_sai.c
  • HAL_SAI_Receive() : stm32wbxx_hal_sai.c
  • HAL_SAI_Receive_DMA() : stm32wbxx_hal_sai.c
  • HAL_SAI_Receive_IT() : stm32wbxx_hal_sai.c
  • HAL_SAI_RegisterCallback() : stm32wbxx_hal_sai.c
  • HAL_SAI_RxCpltCallback() : stm32wbxx_hal_sai.c
  • HAL_SAI_RxHalfCpltCallback() : stm32wbxx_hal_sai.c
  • HAL_SAI_Transmit() : stm32wbxx_hal_sai.c
  • HAL_SAI_Transmit_DMA() : stm32wbxx_hal_sai.c
  • HAL_SAI_Transmit_IT() : stm32wbxx_hal_sai.c
  • HAL_SAI_TxCpltCallback() : stm32wbxx_hal_sai.c
  • HAL_SAI_TxHalfCpltCallback() : stm32wbxx_hal_sai.c
  • HAL_SAI_UnRegisterCallback() : stm32wbxx_hal_sai.c
  • HAL_SAIEx_ConfigPdmMicDelay() : stm32wbxx_hal_sai_ex.c
  • HAL_SetTickFreq() : stm32wbxx_hal.c
  • HAL_SMARTCARD_Abort() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_Abort_IT() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_AbortCpltCallback() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceive() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceive_IT() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceiveCpltCallback() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmit() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmit_IT() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmitCpltCallback() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_DeInit() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_ErrorCallback() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_GetError() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_GetState() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_Init() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_IRQHandler() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_MspDeInit() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_MspInit() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_Receive() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_DMA() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_IT() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_RegisterCallback() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_RxCpltCallback() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_DMA() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_IT() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_TxCpltCallback() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARD_UnRegisterCallback() : stm32wbxx_hal_smartcard.c
  • HAL_SMARTCARDEx_BlockLength_Config() : stm32wbxx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_DisableFifoMode() : stm32wbxx_hal_smartcard_ex.c , stm32wbxx_hal_smartcard_ex.h
  • HAL_SMARTCARDEx_DisableReceiverTimeOut() : stm32wbxx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_EnableFifoMode() : stm32wbxx_hal_smartcard_ex.c , stm32wbxx_hal_smartcard_ex.h
  • HAL_SMARTCARDEx_EnableReceiverTimeOut() : stm32wbxx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_RxFifoFullCallback() : stm32wbxx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_SetRxFifoThreshold() : stm32wbxx_hal_smartcard_ex.c , stm32wbxx_hal_smartcard_ex.h
  • HAL_SMARTCARDEx_SetTxFifoThreshold() : stm32wbxx_hal_smartcard_ex.h , stm32wbxx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_TimeOut_Config() : stm32wbxx_hal_smartcard_ex.c
  • HAL_SMARTCARDEx_TxFifoEmptyCallback() : stm32wbxx_hal_smartcard_ex.c
  • HAL_SMBUS_AddrCallback() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_ConfigAnalogFilter() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_ConfigDigitalFilter() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_DeInit() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_DisableAlert_IT() : stm32wbxx_hal_smbus.h , stm32wbxx_hal_smbus.c
  • HAL_SMBUS_DisableListen_IT() : stm32wbxx_hal_smbus.c , stm32wbxx_hal_smbus.h
  • HAL_SMBUS_EnableAlert_IT() : stm32wbxx_hal_smbus.h , stm32wbxx_hal_smbus.c
  • HAL_SMBUS_EnableListen_IT() : stm32wbxx_hal_smbus.c , stm32wbxx_hal_smbus.h
  • HAL_SMBUS_ER_IRQHandler() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_ErrorCallback() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_EV_IRQHandler() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_GetError() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_GetState() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_Init() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_IsDeviceReady() : stm32wbxx_hal_smbus.h , stm32wbxx_hal_smbus.c
  • HAL_SMBUS_ListenCpltCallback() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_Master_Abort_IT() : stm32wbxx_hal_smbus.c , stm32wbxx_hal_smbus.h
  • HAL_SMBUS_Master_Receive_IT() : stm32wbxx_hal_smbus.h , stm32wbxx_hal_smbus.c
  • HAL_SMBUS_Master_Transmit_IT() : stm32wbxx_hal_smbus.c , stm32wbxx_hal_smbus.h
  • HAL_SMBUS_MasterRxCpltCallback() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_MasterTxCpltCallback() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_MspDeInit() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_MspInit() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_RegisterAddrCallback() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_RegisterCallback() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_Slave_Receive_IT() : stm32wbxx_hal_smbus.c , stm32wbxx_hal_smbus.h
  • HAL_SMBUS_Slave_Transmit_IT() : stm32wbxx_hal_smbus.c , stm32wbxx_hal_smbus.h
  • HAL_SMBUS_SlaveRxCpltCallback() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_SlaveTxCpltCallback() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_UnRegisterAddrCallback() : stm32wbxx_hal_smbus.c
  • HAL_SMBUS_UnRegisterCallback() : stm32wbxx_hal_smbus.c
  • HAL_SPI_Abort() : stm32wbxx_hal_spi.c
  • HAL_SPI_Abort_IT() : stm32wbxx_hal_spi.c
  • HAL_SPI_AbortCpltCallback() : stm32wbxx_hal_spi.c
  • HAL_SPI_DeInit() : stm32wbxx_hal_spi.c
  • HAL_SPI_DMAPause() : stm32wbxx_hal_spi.c
  • HAL_SPI_DMAResume() : stm32wbxx_hal_spi.c
  • HAL_SPI_DMAStop() : stm32wbxx_hal_spi.c
  • HAL_SPI_ErrorCallback() : stm32wbxx_hal_spi.c
  • HAL_SPI_GetError() : stm32wbxx_hal_spi.c
  • HAL_SPI_GetState() : stm32wbxx_hal_spi.c
  • HAL_SPI_Init() : stm32wbxx_hal_spi.c
  • HAL_SPI_IRQHandler() : stm32wbxx_hal_spi.c
  • HAL_SPI_MspDeInit() : stm32wbxx_hal_spi.c
  • HAL_SPI_MspInit() : stm32wbxx_hal_spi.c
  • HAL_SPI_Receive() : stm32wbxx_hal_spi.c
  • HAL_SPI_Receive_DMA() : stm32wbxx_hal_spi.c
  • HAL_SPI_Receive_IT() : stm32wbxx_hal_spi.c
  • HAL_SPI_RegisterCallback() : stm32wbxx_hal_spi.c
  • HAL_SPI_RxCpltCallback() : stm32wbxx_hal_spi.c
  • HAL_SPI_RxHalfCpltCallback() : stm32wbxx_hal_spi.c
  • HAL_SPI_Transmit() : stm32wbxx_hal_spi.c
  • HAL_SPI_Transmit_DMA() : stm32wbxx_hal_spi.c
  • HAL_SPI_Transmit_IT() : stm32wbxx_hal_spi.c
  • HAL_SPI_TransmitReceive() : stm32wbxx_hal_spi.c
  • HAL_SPI_TransmitReceive_DMA() : stm32wbxx_hal_spi.c
  • HAL_SPI_TransmitReceive_IT() : stm32wbxx_hal_spi.c
  • HAL_SPI_TxCpltCallback() : stm32wbxx_hal_spi.c
  • HAL_SPI_TxHalfCpltCallback() : stm32wbxx_hal_spi.c
  • HAL_SPI_TxRxCpltCallback() : stm32wbxx_hal_spi.c
  • HAL_SPI_TxRxHalfCpltCallback() : stm32wbxx_hal_spi.c
  • HAL_SPI_UnRegisterCallback() : stm32wbxx_hal_spi.c
  • HAL_SPIEx_FlushRxFifo() : stm32wbxx_hal_spi_ex.c
  • HAL_SuspendTick() : stm32wbxx_hal.c
  • HAL_SYSCFG_DisableIOBooster() : stm32wbxx_hal.c
  • HAL_SYSCFG_DisableIOVdd() : stm32wbxx_hal.c
  • HAL_SYSCFG_DisableSecurityAccess() : stm32wbxx_hal.c
  • HAL_SYSCFG_DisableSRAMFetch() : stm32wbxx_hal.c
  • HAL_SYSCFG_DisableVREFBUF() : stm32wbxx_hal.c
  • HAL_SYSCFG_EnableIOBooster() : stm32wbxx_hal.c
  • HAL_SYSCFG_EnableIOVdd() : stm32wbxx_hal.c
  • HAL_SYSCFG_EnableSecurityAccess() : stm32wbxx_hal.c
  • HAL_SYSCFG_EnableVREFBUF() : stm32wbxx_hal.c
  • HAL_SYSCFG_IsEnabledSecurityAccess() : stm32wbxx_hal.c
  • HAL_SYSCFG_IsEnabledSRAMFetch() : stm32wbxx_hal.c
  • HAL_SYSCFG_SRAM2Erase() : stm32wbxx_hal.c
  • HAL_SYSCFG_VREFBUF_HighImpedanceConfig() : stm32wbxx_hal.c
  • HAL_SYSCFG_VREFBUF_TrimmingConfig() : stm32wbxx_hal.c
  • HAL_SYSCFG_VREFBUF_VoltageScalingConfig() : stm32wbxx_hal.c
  • HAL_SYSTICK_Callback() : stm32wbxx_hal_cortex.c
  • HAL_SYSTICK_CLKSourceConfig() : stm32wbxx_hal_cortex.c
  • HAL_SYSTICK_Config() : stm32wbxx_hal_cortex.c
  • HAL_SYSTICK_IRQHandler() : stm32wbxx_hal_cortex.c
  • HAL_TIM_Base_DeInit() : stm32wbxx_hal_tim.c
  • HAL_TIM_Base_GetState() : stm32wbxx_hal_tim.c
  • HAL_TIM_Base_Init() : stm32wbxx_hal_tim.c
  • HAL_TIM_Base_MspDeInit() : stm32wbxx_hal_tim.c
  • HAL_TIM_Base_MspInit() : stm32wbxx_hal_tim.c
  • HAL_TIM_Base_Start() : stm32wbxx_hal_tim.c
  • HAL_TIM_Base_Start_DMA() : stm32wbxx_hal_tim.c
  • HAL_TIM_Base_Start_IT() : stm32wbxx_hal_tim.c
  • HAL_TIM_Base_Stop() : stm32wbxx_hal_tim.c
  • HAL_TIM_Base_Stop_DMA() : stm32wbxx_hal_tim.c
  • HAL_TIM_Base_Stop_IT() : stm32wbxx_hal_tim.c
  • HAL_TIM_ConfigClockSource() : stm32wbxx_hal_tim.c
  • HAL_TIM_ConfigOCrefClear() : stm32wbxx_hal_tim.c
  • HAL_TIM_ConfigTI1Input() : stm32wbxx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStart() : stm32wbxx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStop() : stm32wbxx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStart() : stm32wbxx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStop() : stm32wbxx_hal_tim.c
  • HAL_TIM_Encoder_DeInit() : stm32wbxx_hal_tim.c
  • HAL_TIM_Encoder_GetState() : stm32wbxx_hal_tim.c
  • HAL_TIM_Encoder_Init() : stm32wbxx_hal_tim.c
  • HAL_TIM_Encoder_MspDeInit() : stm32wbxx_hal_tim.c
  • HAL_TIM_Encoder_MspInit() : stm32wbxx_hal_tim.c
  • HAL_TIM_Encoder_Start() : stm32wbxx_hal_tim.c
  • HAL_TIM_Encoder_Start_DMA() : stm32wbxx_hal_tim.c
  • HAL_TIM_Encoder_Start_IT() : stm32wbxx_hal_tim.c
  • HAL_TIM_Encoder_Stop() : stm32wbxx_hal_tim.c
  • HAL_TIM_Encoder_Stop_DMA() : stm32wbxx_hal_tim.c
  • HAL_TIM_Encoder_Stop_IT() : stm32wbxx_hal_tim.c
  • HAL_TIM_ErrorCallback() : stm32wbxx_hal_tim.c
  • HAL_TIM_GenerateEvent() : stm32wbxx_hal_tim.c
  • HAL_TIM_IC_CaptureCallback() : stm32wbxx_hal_tim.c
  • HAL_TIM_IC_CaptureHalfCpltCallback() : stm32wbxx_hal_tim.c
  • HAL_TIM_IC_ConfigChannel() : stm32wbxx_hal_tim.c
  • HAL_TIM_IC_DeInit() : stm32wbxx_hal_tim.c
  • HAL_TIM_IC_GetState() : stm32wbxx_hal_tim.c
  • HAL_TIM_IC_Init() : stm32wbxx_hal_tim.c
  • HAL_TIM_IC_MspDeInit() : stm32wbxx_hal_tim.c
  • HAL_TIM_IC_MspInit() : stm32wbxx_hal_tim.c
  • HAL_TIM_IC_Start() : stm32wbxx_hal_tim.c
  • HAL_TIM_IC_Start_DMA() : stm32wbxx_hal_tim.c
  • HAL_TIM_IC_Start_IT() : stm32wbxx_hal_tim.c
  • HAL_TIM_IC_Stop() : stm32wbxx_hal_tim.c
  • HAL_TIM_IC_Stop_DMA() : stm32wbxx_hal_tim.c
  • HAL_TIM_IC_Stop_IT() : stm32wbxx_hal_tim.c
  • HAL_TIM_IRQHandler() : stm32wbxx_hal_tim.c
  • HAL_TIM_OC_ConfigChannel() : stm32wbxx_hal_tim.c
  • HAL_TIM_OC_DeInit() : stm32wbxx_hal_tim.c
  • HAL_TIM_OC_DelayElapsedCallback() : stm32wbxx_hal_tim.c
  • HAL_TIM_OC_GetState() : stm32wbxx_hal_tim.c
  • HAL_TIM_OC_Init() : stm32wbxx_hal_tim.c
  • HAL_TIM_OC_MspDeInit() : stm32wbxx_hal_tim.c
  • HAL_TIM_OC_MspInit() : stm32wbxx_hal_tim.c
  • HAL_TIM_OC_Start() : stm32wbxx_hal_tim.c
  • HAL_TIM_OC_Start_DMA() : stm32wbxx_hal_tim.c
  • HAL_TIM_OC_Start_IT() : stm32wbxx_hal_tim.c
  • HAL_TIM_OC_Stop() : stm32wbxx_hal_tim.c
  • HAL_TIM_OC_Stop_DMA() : stm32wbxx_hal_tim.c
  • HAL_TIM_OC_Stop_IT() : stm32wbxx_hal_tim.c
  • HAL_TIM_OnePulse_ConfigChannel() : stm32wbxx_hal_tim.c
  • HAL_TIM_OnePulse_DeInit() : stm32wbxx_hal_tim.c
  • HAL_TIM_OnePulse_GetState() : stm32wbxx_hal_tim.c
  • HAL_TIM_OnePulse_Init() : stm32wbxx_hal_tim.c
  • HAL_TIM_OnePulse_MspDeInit() : stm32wbxx_hal_tim.c
  • HAL_TIM_OnePulse_MspInit() : stm32wbxx_hal_tim.c
  • HAL_TIM_OnePulse_Start() : stm32wbxx_hal_tim.c
  • HAL_TIM_OnePulse_Start_IT() : stm32wbxx_hal_tim.c
  • HAL_TIM_OnePulse_Stop() : stm32wbxx_hal_tim.c
  • HAL_TIM_OnePulse_Stop_IT() : stm32wbxx_hal_tim.c
  • HAL_TIM_PeriodElapsedCallback() : stm32wbxx_hal_tim.c
  • HAL_TIM_PeriodElapsedHalfCpltCallback() : stm32wbxx_hal_tim.c
  • HAL_TIM_PWM_ConfigChannel() : stm32wbxx_hal_tim.c
  • HAL_TIM_PWM_DeInit() : stm32wbxx_hal_tim.c
  • HAL_TIM_PWM_GetState() : stm32wbxx_hal_tim.c
  • HAL_TIM_PWM_Init() : stm32wbxx_hal_tim.c
  • HAL_TIM_PWM_MspDeInit() : stm32wbxx_hal_tim.c
  • HAL_TIM_PWM_MspInit() : stm32wbxx_hal_tim.c
  • HAL_TIM_PWM_PulseFinishedCallback() : stm32wbxx_hal_tim.c
  • HAL_TIM_PWM_PulseFinishedHalfCpltCallback() : stm32wbxx_hal_tim.c
  • HAL_TIM_PWM_Start() : stm32wbxx_hal_tim.c
  • HAL_TIM_PWM_Start_DMA() : stm32wbxx_hal_tim.c
  • HAL_TIM_PWM_Start_IT() : stm32wbxx_hal_tim.c
  • HAL_TIM_PWM_Stop() : stm32wbxx_hal_tim.c
  • HAL_TIM_PWM_Stop_DMA() : stm32wbxx_hal_tim.c
  • HAL_TIM_PWM_Stop_IT() : stm32wbxx_hal_tim.c
  • HAL_TIM_ReadCapturedValue() : stm32wbxx_hal_tim.c
  • HAL_TIM_RegisterCallback() : stm32wbxx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchro() : stm32wbxx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchro_IT() : stm32wbxx_hal_tim.c
  • HAL_TIM_TriggerCallback() : stm32wbxx_hal_tim.c
  • HAL_TIM_TriggerHalfCpltCallback() : stm32wbxx_hal_tim.c
  • HAL_TIM_UnRegisterCallback() : stm32wbxx_hal_tim.c
  • HAL_TIMEx_Break2Callback() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_BreakCallback() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_CommutCallback() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_CommutHalfCpltCallback() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_ConfigBreakDeadTime() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_ConfigBreakInput() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutEvent() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutEvent_DMA() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutEvent_IT() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_GroupChannel5() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_DeInit() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_GetState() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Init() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspDeInit() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspInit() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_DMA() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_IT() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_DMA() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_IT() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_MasterConfigSynchronization() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_DMA() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_IT() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_DMA() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_IT() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start_IT() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop_IT() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_DMA() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_IT() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_DMA() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_IT() : stm32wbxx_hal_tim_ex.c
  • HAL_TIMEx_RemapConfig() : stm32wbxx_hal_tim_ex.c
  • HAL_TSC_ConvCpltCallback() : stm32wbxx_hal_tsc.c
  • HAL_TSC_DeInit() : stm32wbxx_hal_tsc.c
  • HAL_TSC_ErrorCallback() : stm32wbxx_hal_tsc.c
  • HAL_TSC_GetState() : stm32wbxx_hal_tsc.c
  • HAL_TSC_GroupGetStatus() : stm32wbxx_hal_tsc.c
  • HAL_TSC_GroupGetValue() : stm32wbxx_hal_tsc.c
  • HAL_TSC_Init() : stm32wbxx_hal_tsc.c
  • HAL_TSC_IOConfig() : stm32wbxx_hal_tsc.c
  • HAL_TSC_IODischarge() : stm32wbxx_hal_tsc.c
  • HAL_TSC_IRQHandler() : stm32wbxx_hal_tsc.c
  • HAL_TSC_MspDeInit() : stm32wbxx_hal_tsc.c
  • HAL_TSC_MspInit() : stm32wbxx_hal_tsc.c
  • HAL_TSC_PollForAcquisition() : stm32wbxx_hal_tsc.c
  • HAL_TSC_RegisterCallback() : stm32wbxx_hal_tsc.c
  • HAL_TSC_Start() : stm32wbxx_hal_tsc.c
  • HAL_TSC_Start_IT() : stm32wbxx_hal_tsc.c
  • HAL_TSC_Stop() : stm32wbxx_hal_tsc.c
  • HAL_TSC_Stop_IT() : stm32wbxx_hal_tsc.c
  • HAL_TSC_UnRegisterCallback() : stm32wbxx_hal_tsc.c
  • HAL_UART_Abort() : stm32wbxx_hal_uart.c
  • HAL_UART_Abort_IT() : stm32wbxx_hal_uart.c
  • HAL_UART_AbortCpltCallback() : stm32wbxx_hal_uart.c
  • HAL_UART_AbortReceive() : stm32wbxx_hal_uart.c
  • HAL_UART_AbortReceive_IT() : stm32wbxx_hal_uart.c
  • HAL_UART_AbortReceiveCpltCallback() : stm32wbxx_hal_uart.c
  • HAL_UART_AbortTransmit() : stm32wbxx_hal_uart.c
  • HAL_UART_AbortTransmit_IT() : stm32wbxx_hal_uart.c
  • HAL_UART_AbortTransmitCpltCallback() : stm32wbxx_hal_uart.c
  • HAL_UART_DeInit() : stm32wbxx_hal_uart.c
  • HAL_UART_DisableReceiverTimeout() : stm32wbxx_hal_uart.c
  • HAL_UART_DMAPause() : stm32wbxx_hal_uart.c
  • HAL_UART_DMAResume() : stm32wbxx_hal_uart.c
  • HAL_UART_DMAStop() : stm32wbxx_hal_uart.c
  • HAL_UART_EnableReceiverTimeout() : stm32wbxx_hal_uart.c
  • HAL_UART_ErrorCallback() : stm32wbxx_hal_uart.c
  • HAL_UART_GetError() : stm32wbxx_hal_uart.c
  • HAL_UART_GetState() : stm32wbxx_hal_uart.c
  • HAL_UART_Init() : stm32wbxx_hal_uart.c
  • HAL_UART_IRQHandler() : stm32wbxx_hal_uart.c
  • HAL_UART_MspDeInit() : stm32wbxx_hal_uart.c
  • HAL_UART_MspInit() : stm32wbxx_hal_uart.c
  • HAL_UART_Receive() : stm32wbxx_hal_uart.c
  • HAL_UART_Receive_DMA() : stm32wbxx_hal_uart.c
  • HAL_UART_Receive_IT() : stm32wbxx_hal_uart.c
  • HAL_UART_ReceiverTimeout_Config() : stm32wbxx_hal_uart.c
  • HAL_UART_RegisterCallback() : stm32wbxx_hal_uart.c
  • HAL_UART_RxCpltCallback() : stm32wbxx_hal_uart.c
  • HAL_UART_RxHalfCpltCallback() : stm32wbxx_hal_uart.c
  • HAL_UART_Transmit() : stm32wbxx_hal_uart.c
  • HAL_UART_Transmit_DMA() : stm32wbxx_hal_uart.c
  • HAL_UART_Transmit_IT() : stm32wbxx_hal_uart.c
  • HAL_UART_TxCpltCallback() : stm32wbxx_hal_uart.c
  • HAL_UART_TxHalfCpltCallback() : stm32wbxx_hal_uart.c
  • HAL_UART_UnRegisterCallback() : stm32wbxx_hal_uart.c
  • HAL_UARTEx_DisableFifoMode() : stm32wbxx_hal_uart_ex.c
  • HAL_UARTEx_DisableStopMode() : stm32wbxx_hal_uart_ex.c
  • HAL_UARTEx_EnableFifoMode() : stm32wbxx_hal_uart_ex.c
  • HAL_UARTEx_EnableStopMode() : stm32wbxx_hal_uart_ex.c
  • HAL_UARTEx_RxFifoFullCallback() : stm32wbxx_hal_uart_ex.c
  • HAL_UARTEx_SetRxFifoThreshold() : stm32wbxx_hal_uart_ex.c
  • HAL_UARTEx_SetTxFifoThreshold() : stm32wbxx_hal_uart_ex.c
  • HAL_UARTEx_StopModeWakeUpSourceConfig() : stm32wbxx_hal_uart_ex.c
  • HAL_UARTEx_TxFifoEmptyCallback() : stm32wbxx_hal_uart_ex.c
  • HAL_UARTEx_WakeupCallback() : stm32wbxx_hal_uart_ex.c
  • HAL_USART_Abort() : stm32wbxx_hal_usart.c
  • HAL_USART_Abort_IT() : stm32wbxx_hal_usart.c
  • HAL_USART_AbortCpltCallback() : stm32wbxx_hal_usart.c
  • HAL_USART_DeInit() : stm32wbxx_hal_usart.c
  • HAL_USART_DMAPause() : stm32wbxx_hal_usart.c
  • HAL_USART_DMAResume() : stm32wbxx_hal_usart.c
  • HAL_USART_DMAStop() : stm32wbxx_hal_usart.c
  • HAL_USART_ErrorCallback() : stm32wbxx_hal_usart.c
  • HAL_USART_GetError() : stm32wbxx_hal_usart.c
  • HAL_USART_GetState() : stm32wbxx_hal_usart.c
  • HAL_USART_Init() : stm32wbxx_hal_usart.c
  • HAL_USART_IRQHandler() : stm32wbxx_hal_usart.c
  • HAL_USART_MspDeInit() : stm32wbxx_hal_usart.c
  • HAL_USART_MspInit() : stm32wbxx_hal_usart.c
  • HAL_USART_Receive() : stm32wbxx_hal_usart.c
  • HAL_USART_Receive_DMA() : stm32wbxx_hal_usart.c
  • HAL_USART_Receive_IT() : stm32wbxx_hal_usart.c
  • HAL_USART_RegisterCallback() : stm32wbxx_hal_usart.c
  • HAL_USART_RxCpltCallback() : stm32wbxx_hal_usart.c
  • HAL_USART_RxHalfCpltCallback() : stm32wbxx_hal_usart.c
  • HAL_USART_Transmit() : stm32wbxx_hal_usart.c
  • HAL_USART_Transmit_DMA() : stm32wbxx_hal_usart.c
  • HAL_USART_Transmit_IT() : stm32wbxx_hal_usart.c
  • HAL_USART_TransmitReceive() : stm32wbxx_hal_usart.c
  • HAL_USART_TransmitReceive_DMA() : stm32wbxx_hal_usart.c
  • HAL_USART_TransmitReceive_IT() : stm32wbxx_hal_usart.c
  • HAL_USART_TxCpltCallback() : stm32wbxx_hal_usart.c
  • HAL_USART_TxHalfCpltCallback() : stm32wbxx_hal_usart.c
  • HAL_USART_TxRxCpltCallback() : stm32wbxx_hal_usart.c
  • HAL_USART_UnRegisterCallback() : stm32wbxx_hal_usart.c
  • HAL_USARTEx_ConfigNSS() : stm32wbxx_hal_usart_ex.c
  • HAL_USARTEx_DisableFifoMode() : stm32wbxx_hal_usart_ex.c
  • HAL_USARTEx_DisableSlaveMode() : stm32wbxx_hal_usart_ex.c
  • HAL_USARTEx_EnableFifoMode() : stm32wbxx_hal_usart_ex.c
  • HAL_USARTEx_EnableSlaveMode() : stm32wbxx_hal_usart_ex.c
  • HAL_USARTEx_RxFifoFullCallback() : stm32wbxx_hal_usart_ex.c
  • HAL_USARTEx_SetRxFifoThreshold() : stm32wbxx_hal_usart_ex.c
  • HAL_USARTEx_SetTxFifoThreshold() : stm32wbxx_hal_usart_ex.c
  • HAL_USARTEx_TxFifoEmptyCallback() : stm32wbxx_hal_usart_ex.c
  • HAL_WWDG_EarlyWakeupCallback() : stm32wbxx_hal_wwdg.c
  • HAL_WWDG_Init() : stm32wbxx_hal_wwdg.c
  • HAL_WWDG_IRQHandler() : stm32wbxx_hal_wwdg.c
  • HAL_WWDG_MspInit() : stm32wbxx_hal_wwdg.c
  • HAL_WWDG_Refresh() : stm32wbxx_hal_wwdg.c
  • HAL_WWDG_RegisterCallback() : stm32wbxx_hal_wwdg.c
  • HAL_WWDG_UnRegisterCallback() : stm32wbxx_hal_wwdg.c
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • a
  • c
  • d
  • f
  • h
  • i
  • l
  • o
  • p
  • q
  • r
  • s
  • t
  • u

- i -

  • I2C_ConvertOtherXferOptions() : stm32wbxx_hal_i2c.c
  • I2C_Disable_IRQ() : stm32wbxx_hal_i2c.c
  • I2C_DMAAbort() : stm32wbxx_hal_i2c.c
  • I2C_DMAError() : stm32wbxx_hal_i2c.c
  • I2C_DMAMasterReceiveCplt() : stm32wbxx_hal_i2c.c
  • I2C_DMAMasterTransmitCplt() : stm32wbxx_hal_i2c.c
  • I2C_DMASlaveReceiveCplt() : stm32wbxx_hal_i2c.c
  • I2C_DMASlaveTransmitCplt() : stm32wbxx_hal_i2c.c
  • I2C_Enable_IRQ() : stm32wbxx_hal_i2c.c
  • I2C_Flush_TXDR() : stm32wbxx_hal_i2c.c
  • I2C_IsAcknowledgeFailed() : stm32wbxx_hal_i2c.c
  • I2C_ITAddrCplt() : stm32wbxx_hal_i2c.c
  • I2C_ITError() : stm32wbxx_hal_i2c.c
  • I2C_ITListenCplt() : stm32wbxx_hal_i2c.c
  • I2C_ITMasterCplt() : stm32wbxx_hal_i2c.c
  • I2C_ITMasterSeqCplt() : stm32wbxx_hal_i2c.c
  • I2C_ITSlaveCplt() : stm32wbxx_hal_i2c.c
  • I2C_ITSlaveSeqCplt() : stm32wbxx_hal_i2c.c
  • I2C_Master_ISR_DMA() : stm32wbxx_hal_i2c.c
  • I2C_Master_ISR_IT() : stm32wbxx_hal_i2c.c
  • I2C_RequestMemoryRead() : stm32wbxx_hal_i2c.c
  • I2C_RequestMemoryWrite() : stm32wbxx_hal_i2c.c
  • I2C_Slave_ISR_DMA() : stm32wbxx_hal_i2c.c
  • I2C_Slave_ISR_IT() : stm32wbxx_hal_i2c.c
  • I2C_TransferConfig() : stm32wbxx_hal_i2c.c
  • I2C_WaitOnFlagUntilTimeout() : stm32wbxx_hal_i2c.c
  • I2C_WaitOnRXNEFlagUntilTimeout() : stm32wbxx_hal_i2c.c
  • I2C_WaitOnSTOPFlagUntilTimeout() : stm32wbxx_hal_i2c.c
  • I2C_WaitOnTXISFlagUntilTimeout() : stm32wbxx_hal_i2c.c
  • IC1Config() : stm32wbxx_ll_tim.c
  • IC2Config() : stm32wbxx_ll_tim.c
  • IC3Config() : stm32wbxx_ll_tim.c
  • IC4Config() : stm32wbxx_ll_tim.c
  • IPCC_MaskInterrupt() : stm32wbxx_hal_ipcc.c
  • IPCC_Reset_Register() : stm32wbxx_hal_ipcc.c
  • IPCC_SetDefaultCallbacks() : stm32wbxx_hal_ipcc.c
  • IPCC_UnmaskInterrupt() : stm32wbxx_hal_ipcc.c
  • IRDA_CheckIdleState() : stm32wbxx_hal_irda.c
  • IRDA_DMAAbortOnError() : stm32wbxx_hal_irda.c
  • IRDA_DMAError() : stm32wbxx_hal_irda.c
  • IRDA_DMAReceiveCplt() : stm32wbxx_hal_irda.c
  • IRDA_DMAReceiveHalfCplt() : stm32wbxx_hal_irda.c
  • IRDA_DMARxAbortCallback() : stm32wbxx_hal_irda.c
  • IRDA_DMARxOnlyAbortCallback() : stm32wbxx_hal_irda.c
  • IRDA_DMATransmitCplt() : stm32wbxx_hal_irda.c
  • IRDA_DMATransmitHalfCplt() : stm32wbxx_hal_irda.c
  • IRDA_DMATxAbortCallback() : stm32wbxx_hal_irda.c
  • IRDA_DMATxOnlyAbortCallback() : stm32wbxx_hal_irda.c
  • IRDA_EndRxTransfer() : stm32wbxx_hal_irda.c
  • IRDA_EndTransmit_IT() : stm32wbxx_hal_irda.c
  • IRDA_EndTxTransfer() : stm32wbxx_hal_irda.c
  • IRDA_InitCallbacksToDefault() : stm32wbxx_hal_irda.c
  • IRDA_Receive_IT() : stm32wbxx_hal_irda.c
  • IRDA_SetConfig() : stm32wbxx_hal_irda.c
  • IRDA_Transmit_IT() : stm32wbxx_hal_irda.c
  • IRDA_WaitOnFlagUntilTimeout() : stm32wbxx_hal_irda.c
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • a
  • c
  • d
  • f
  • h
  • i
  • l
  • o
  • p
  • q
  • r
  • s
  • t
  • u

- l -

  • LCD_WaitForSynchro() : stm32wbxx_hal_lcd.c
  • LL_ADC_ClearFlag_ADRDY() : stm32wbxx_ll_adc.h
  • LL_ADC_ClearFlag_AWD1() : stm32wbxx_ll_adc.h
  • LL_ADC_ClearFlag_AWD2() : stm32wbxx_ll_adc.h
  • LL_ADC_ClearFlag_AWD3() : stm32wbxx_ll_adc.h
  • LL_ADC_ClearFlag_EOC() : stm32wbxx_ll_adc.h
  • LL_ADC_ClearFlag_EOS() : stm32wbxx_ll_adc.h
  • LL_ADC_ClearFlag_EOSMP() : stm32wbxx_ll_adc.h
  • LL_ADC_ClearFlag_JEOC() : stm32wbxx_ll_adc.h
  • LL_ADC_ClearFlag_JEOS() : stm32wbxx_ll_adc.h
  • LL_ADC_ClearFlag_JQOVF() : stm32wbxx_ll_adc.h
  • LL_ADC_ClearFlag_OVR() : stm32wbxx_ll_adc.h
  • LL_ADC_CommonDeInit() : stm32wbxx_ll_adc.c
  • LL_ADC_CommonInit() : stm32wbxx_ll_adc.c
  • LL_ADC_CommonStructInit() : stm32wbxx_ll_adc.c
  • LL_ADC_ConfigAnalogWDThresholds() : stm32wbxx_ll_adc.h
  • LL_ADC_ConfigOverSamplingRatioShift() : stm32wbxx_ll_adc.h
  • LL_ADC_DeInit() : stm32wbxx_ll_adc.c
  • LL_ADC_Disable() : stm32wbxx_ll_adc.h
  • LL_ADC_DisableDeepPowerDown() : stm32wbxx_ll_adc.h
  • LL_ADC_DisableInternalRegulator() : stm32wbxx_ll_adc.h
  • LL_ADC_DisableIT_ADRDY() : stm32wbxx_ll_adc.h
  • LL_ADC_DisableIT_AWD1() : stm32wbxx_ll_adc.h
  • LL_ADC_DisableIT_AWD2() : stm32wbxx_ll_adc.h
  • LL_ADC_DisableIT_AWD3() : stm32wbxx_ll_adc.h
  • LL_ADC_DisableIT_EOC() : stm32wbxx_ll_adc.h
  • LL_ADC_DisableIT_EOS() : stm32wbxx_ll_adc.h
  • LL_ADC_DisableIT_EOSMP() : stm32wbxx_ll_adc.h
  • LL_ADC_DisableIT_JEOC() : stm32wbxx_ll_adc.h
  • LL_ADC_DisableIT_JEOS() : stm32wbxx_ll_adc.h
  • LL_ADC_DisableIT_JQOVF() : stm32wbxx_ll_adc.h
  • LL_ADC_DisableIT_OVR() : stm32wbxx_ll_adc.h
  • LL_ADC_DMA_GetRegAddr() : stm32wbxx_ll_adc.h
  • LL_ADC_Enable() : stm32wbxx_ll_adc.h
  • LL_ADC_EnableDeepPowerDown() : stm32wbxx_ll_adc.h
  • LL_ADC_EnableInternalRegulator() : stm32wbxx_ll_adc.h
  • LL_ADC_EnableIT_ADRDY() : stm32wbxx_ll_adc.h
  • LL_ADC_EnableIT_AWD1() : stm32wbxx_ll_adc.h
  • LL_ADC_EnableIT_AWD2() : stm32wbxx_ll_adc.h
  • LL_ADC_EnableIT_AWD3() : stm32wbxx_ll_adc.h
  • LL_ADC_EnableIT_EOC() : stm32wbxx_ll_adc.h
  • LL_ADC_EnableIT_EOS() : stm32wbxx_ll_adc.h
  • LL_ADC_EnableIT_EOSMP() : stm32wbxx_ll_adc.h
  • LL_ADC_EnableIT_JEOC() : stm32wbxx_ll_adc.h
  • LL_ADC_EnableIT_JEOS() : stm32wbxx_ll_adc.h
  • LL_ADC_EnableIT_JQOVF() : stm32wbxx_ll_adc.h
  • LL_ADC_EnableIT_OVR() : stm32wbxx_ll_adc.h
  • LL_ADC_GetAnalogWDMonitChannels() : stm32wbxx_ll_adc.h
  • LL_ADC_GetAnalogWDThresholds() : stm32wbxx_ll_adc.h
  • LL_ADC_GetCalibrationFactor() : stm32wbxx_ll_adc.h
  • LL_ADC_GetChannelSamplingTime() : stm32wbxx_ll_adc.h
  • LL_ADC_GetChannelSingleDiff() : stm32wbxx_ll_adc.h
  • LL_ADC_GetCommonClock() : stm32wbxx_ll_adc.h
  • LL_ADC_GetCommonPathInternalCh() : stm32wbxx_ll_adc.h
  • LL_ADC_GetDataAlignment() : stm32wbxx_ll_adc.h
  • LL_ADC_GetLowPowerMode() : stm32wbxx_ll_adc.h
  • LL_ADC_GetOffsetChannel() : stm32wbxx_ll_adc.h
  • LL_ADC_GetOffsetLevel() : stm32wbxx_ll_adc.h
  • LL_ADC_GetOffsetState() : stm32wbxx_ll_adc.h
  • LL_ADC_GetOverSamplingDiscont() : stm32wbxx_ll_adc.h
  • LL_ADC_GetOverSamplingRatio() : stm32wbxx_ll_adc.h
  • LL_ADC_GetOverSamplingScope() : stm32wbxx_ll_adc.h
  • LL_ADC_GetOverSamplingShift() : stm32wbxx_ll_adc.h
  • LL_ADC_GetResolution() : stm32wbxx_ll_adc.h
  • LL_ADC_Init() : stm32wbxx_ll_adc.c
  • LL_ADC_INJ_ConfigQueueContext() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_GetQueueMode() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_GetSequencerDiscont() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_GetSequencerLength() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_GetSequencerRanks() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_GetTrigAuto() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_GetTriggerEdge() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_GetTriggerSource() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_Init() : stm32wbxx_ll_adc.c
  • LL_ADC_INJ_IsConversionOngoing() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_IsStopConversionOngoing() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_IsTriggerSourceSWStart() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData10() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData12() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData32() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData6() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData8() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_SetQueueMode() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_SetSequencerDiscont() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_SetSequencerLength() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_SetSequencerRanks() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_SetTrigAuto() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_SetTriggerEdge() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_SetTriggerSource() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_StartConversion() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_StopConversion() : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_StructInit() : stm32wbxx_ll_adc.c
  • LL_ADC_IsActiveFlag_ADRDY() : stm32wbxx_ll_adc.h
  • LL_ADC_IsActiveFlag_AWD1() : stm32wbxx_ll_adc.h
  • LL_ADC_IsActiveFlag_AWD2() : stm32wbxx_ll_adc.h
  • LL_ADC_IsActiveFlag_AWD3() : stm32wbxx_ll_adc.h
  • LL_ADC_IsActiveFlag_EOC() : stm32wbxx_ll_adc.h
  • LL_ADC_IsActiveFlag_EOS() : stm32wbxx_ll_adc.h
  • LL_ADC_IsActiveFlag_EOSMP() : stm32wbxx_ll_adc.h
  • LL_ADC_IsActiveFlag_JEOC() : stm32wbxx_ll_adc.h
  • LL_ADC_IsActiveFlag_JEOS() : stm32wbxx_ll_adc.h
  • LL_ADC_IsActiveFlag_JQOVF() : stm32wbxx_ll_adc.h
  • LL_ADC_IsActiveFlag_OVR() : stm32wbxx_ll_adc.h
  • LL_ADC_IsCalibrationOnGoing() : stm32wbxx_ll_adc.h
  • LL_ADC_IsDeepPowerDownEnabled() : stm32wbxx_ll_adc.h
  • LL_ADC_IsDisableOngoing() : stm32wbxx_ll_adc.h
  • LL_ADC_IsEnabled() : stm32wbxx_ll_adc.h
  • LL_ADC_IsEnabledIT_ADRDY() : stm32wbxx_ll_adc.h
  • LL_ADC_IsEnabledIT_AWD1() : stm32wbxx_ll_adc.h
  • LL_ADC_IsEnabledIT_AWD2() : stm32wbxx_ll_adc.h
  • LL_ADC_IsEnabledIT_AWD3() : stm32wbxx_ll_adc.h
  • LL_ADC_IsEnabledIT_EOC() : stm32wbxx_ll_adc.h
  • LL_ADC_IsEnabledIT_EOS() : stm32wbxx_ll_adc.h
  • LL_ADC_IsEnabledIT_EOSMP() : stm32wbxx_ll_adc.h
  • LL_ADC_IsEnabledIT_JEOC() : stm32wbxx_ll_adc.h
  • LL_ADC_IsEnabledIT_JEOS() : stm32wbxx_ll_adc.h
  • LL_ADC_IsEnabledIT_JQOVF() : stm32wbxx_ll_adc.h
  • LL_ADC_IsEnabledIT_OVR() : stm32wbxx_ll_adc.h
  • LL_ADC_IsInternalRegulatorEnabled() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_GetContinuousMode() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_GetDMATransfer() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_GetOverrun() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_GetSequencerDiscont() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_GetSequencerLength() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_GetSequencerRanks() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_GetTriggerEdge() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_GetTriggerSource() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_Init() : stm32wbxx_ll_adc.c
  • LL_ADC_REG_IsConversionOngoing() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_IsStopConversionOngoing() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_IsTriggerSourceSWStart() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_ReadConversionData10() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_ReadConversionData12() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_ReadConversionData32() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_ReadConversionData6() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_ReadConversionData8() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SetContinuousMode() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SetDMATransfer() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SetOverrun() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SetSequencerDiscont() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SetSequencerLength() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SetSequencerRanks() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SetTriggerEdge() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SetTriggerSource() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_StartConversion() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_StopConversion() : stm32wbxx_ll_adc.h
  • LL_ADC_REG_StructInit() : stm32wbxx_ll_adc.c
  • LL_ADC_SetAnalogWDMonitChannels() : stm32wbxx_ll_adc.h
  • LL_ADC_SetAnalogWDThresholds() : stm32wbxx_ll_adc.h
  • LL_ADC_SetCalibrationFactor() : stm32wbxx_ll_adc.h
  • LL_ADC_SetChannelSamplingTime() : stm32wbxx_ll_adc.h
  • LL_ADC_SetChannelSingleDiff() : stm32wbxx_ll_adc.h
  • LL_ADC_SetCommonClock() : stm32wbxx_ll_adc.h
  • LL_ADC_SetCommonPathInternalCh() : stm32wbxx_ll_adc.h
  • LL_ADC_SetDataAlignment() : stm32wbxx_ll_adc.h
  • LL_ADC_SetLowPowerMode() : stm32wbxx_ll_adc.h
  • LL_ADC_SetOffset() : stm32wbxx_ll_adc.h
  • LL_ADC_SetOffsetState() : stm32wbxx_ll_adc.h
  • LL_ADC_SetOverSamplingDiscont() : stm32wbxx_ll_adc.h
  • LL_ADC_SetOverSamplingScope() : stm32wbxx_ll_adc.h
  • LL_ADC_SetResolution() : stm32wbxx_ll_adc.h
  • LL_ADC_StartCalibration() : stm32wbxx_ll_adc.h
  • LL_ADC_StructInit() : stm32wbxx_ll_adc.c
  • LL_AHB1_GRP1_DisableClock() : stm32wbxx_ll_bus.h
  • LL_AHB1_GRP1_DisableClockSleep() : stm32wbxx_ll_bus.h
  • LL_AHB1_GRP1_EnableClock() : stm32wbxx_ll_bus.h
  • LL_AHB1_GRP1_EnableClockSleep() : stm32wbxx_ll_bus.h
  • LL_AHB1_GRP1_ForceReset() : stm32wbxx_ll_bus.h
  • LL_AHB1_GRP1_IsEnabledClock() : stm32wbxx_ll_bus.h
  • LL_AHB1_GRP1_ReleaseReset() : stm32wbxx_ll_bus.h
  • LL_AHB2_GRP1_DisableClock() : stm32wbxx_ll_bus.h
  • LL_AHB2_GRP1_DisableClockSleep() : stm32wbxx_ll_bus.h
  • LL_AHB2_GRP1_EnableClock() : stm32wbxx_ll_bus.h
  • LL_AHB2_GRP1_EnableClockSleep() : stm32wbxx_ll_bus.h
  • LL_AHB2_GRP1_ForceReset() : stm32wbxx_ll_bus.h
  • LL_AHB2_GRP1_IsEnabledClock() : stm32wbxx_ll_bus.h
  • LL_AHB2_GRP1_ReleaseReset() : stm32wbxx_ll_bus.h
  • LL_AHB3_GRP1_DisableClock() : stm32wbxx_ll_bus.h
  • LL_AHB3_GRP1_DisableClockSleep() : stm32wbxx_ll_bus.h
  • LL_AHB3_GRP1_EnableClock() : stm32wbxx_ll_bus.h
  • LL_AHB3_GRP1_EnableClockSleep() : stm32wbxx_ll_bus.h
  • LL_AHB3_GRP1_ForceReset() : stm32wbxx_ll_bus.h
  • LL_AHB3_GRP1_IsEnabledClock() : stm32wbxx_ll_bus.h
  • LL_AHB3_GRP1_ReleaseReset() : stm32wbxx_ll_bus.h
  • LL_APB1_GRP1_DisableClock() : stm32wbxx_ll_bus.h
  • LL_APB1_GRP1_DisableClockSleep() : stm32wbxx_ll_bus.h
  • LL_APB1_GRP1_EnableClock() : stm32wbxx_ll_bus.h
  • LL_APB1_GRP1_EnableClockSleep() : stm32wbxx_ll_bus.h
  • LL_APB1_GRP1_ForceReset() : stm32wbxx_ll_bus.h
  • LL_APB1_GRP1_IsEnabledClock() : stm32wbxx_ll_bus.h
  • LL_APB1_GRP1_ReleaseReset() : stm32wbxx_ll_bus.h
  • LL_APB1_GRP2_DisableClock() : stm32wbxx_ll_bus.h
  • LL_APB1_GRP2_DisableClockSleep() : stm32wbxx_ll_bus.h
  • LL_APB1_GRP2_EnableClock() : stm32wbxx_ll_bus.h
  • LL_APB1_GRP2_EnableClockSleep() : stm32wbxx_ll_bus.h
  • LL_APB1_GRP2_ForceReset() : stm32wbxx_ll_bus.h
  • LL_APB1_GRP2_IsEnabledClock() : stm32wbxx_ll_bus.h
  • LL_APB1_GRP2_ReleaseReset() : stm32wbxx_ll_bus.h
  • LL_APB2_GRP1_DisableClock() : stm32wbxx_ll_bus.h
  • LL_APB2_GRP1_DisableClockSleep() : stm32wbxx_ll_bus.h
  • LL_APB2_GRP1_EnableClock() : stm32wbxx_ll_bus.h
  • LL_APB2_GRP1_EnableClockSleep() : stm32wbxx_ll_bus.h
  • LL_APB2_GRP1_ForceReset() : stm32wbxx_ll_bus.h
  • LL_APB2_GRP1_IsEnabledClock() : stm32wbxx_ll_bus.h
  • LL_APB2_GRP1_ReleaseReset() : stm32wbxx_ll_bus.h
  • LL_APB3_GRP1_ForceReset() : stm32wbxx_ll_bus.h
  • LL_APB3_GRP1_ReleaseReset() : stm32wbxx_ll_bus.h
  • LL_C1_IPCC_ClearFlag_CHx() : stm32wbxx_ll_ipcc.h
  • LL_C1_IPCC_DisableIT_RXO() : stm32wbxx_ll_ipcc.h
  • LL_C1_IPCC_DisableIT_TXF() : stm32wbxx_ll_ipcc.h
  • LL_C1_IPCC_DisableReceiveChannel() : stm32wbxx_ll_ipcc.h
  • LL_C1_IPCC_DisableTransmitChannel() : stm32wbxx_ll_ipcc.h
  • LL_C1_IPCC_EnableIT_RXO() : stm32wbxx_ll_ipcc.h
  • LL_C1_IPCC_EnableIT_TXF() : stm32wbxx_ll_ipcc.h
  • LL_C1_IPCC_EnableReceiveChannel() : stm32wbxx_ll_ipcc.h
  • LL_C1_IPCC_EnableTransmitChannel() : stm32wbxx_ll_ipcc.h
  • LL_C1_IPCC_IsActiveFlag_CHx() : stm32wbxx_ll_ipcc.h
  • LL_C1_IPCC_IsEnabledIT_RXO() : stm32wbxx_ll_ipcc.h
  • LL_C1_IPCC_IsEnabledIT_TXF() : stm32wbxx_ll_ipcc.h
  • LL_C1_IPCC_IsEnabledReceiveChannel() : stm32wbxx_ll_ipcc.h
  • LL_C1_IPCC_IsEnabledTransmitChannel() : stm32wbxx_ll_ipcc.h
  • LL_C1_IPCC_SetFlag_CHx() : stm32wbxx_ll_ipcc.h
  • LL_C2_AHB1_GRP1_DisableClock() : stm32wbxx_ll_bus.h
  • LL_C2_AHB1_GRP1_DisableClockSleep() : stm32wbxx_ll_bus.h
  • LL_C2_AHB1_GRP1_EnableClock() : stm32wbxx_ll_bus.h
  • LL_C2_AHB1_GRP1_EnableClockSleep() : stm32wbxx_ll_bus.h
  • LL_C2_AHB1_GRP1_IsEnabledClock() : stm32wbxx_ll_bus.h
  • LL_C2_AHB2_GRP1_DisableClock() : stm32wbxx_ll_bus.h
  • LL_C2_AHB2_GRP1_DisableClockSleep() : stm32wbxx_ll_bus.h
  • LL_C2_AHB2_GRP1_EnableClock() : stm32wbxx_ll_bus.h
  • LL_C2_AHB2_GRP1_EnableClockSleep() : stm32wbxx_ll_bus.h
  • LL_C2_AHB2_GRP1_IsEnabledClock() : stm32wbxx_ll_bus.h
  • LL_C2_AHB3_GRP1_DisableClock() : stm32wbxx_ll_bus.h
  • LL_C2_AHB3_GRP1_DisableClockSleep() : stm32wbxx_ll_bus.h
  • LL_C2_AHB3_GRP1_EnableClock() : stm32wbxx_ll_bus.h
  • LL_C2_AHB3_GRP1_EnableClockSleep() : stm32wbxx_ll_bus.h
  • LL_C2_AHB3_GRP1_IsEnabledClock() : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP1_DisableClock() : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP1_DisableClockSleep() : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP1_EnableClock() : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP1_EnableClockSleep() : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP1_IsEnabledClock() : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP2_DisableClock() : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP2_DisableClockSleep() : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP2_EnableClock() : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP2_EnableClockSleep() : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP2_IsEnabledClock() : stm32wbxx_ll_bus.h
  • LL_C2_APB2_GRP1_DisableClock() : stm32wbxx_ll_bus.h
  • LL_C2_APB2_GRP1_DisableClockSleep() : stm32wbxx_ll_bus.h
  • LL_C2_APB2_GRP1_EnableClock() : stm32wbxx_ll_bus.h
  • LL_C2_APB2_GRP1_EnableClockSleep() : stm32wbxx_ll_bus.h
  • LL_C2_APB2_GRP1_IsEnabledClock() : stm32wbxx_ll_bus.h
  • LL_C2_APB3_GRP1_DisableClock() : stm32wbxx_ll_bus.h
  • LL_C2_APB3_GRP1_DisableClockSleep() : stm32wbxx_ll_bus.h
  • LL_C2_APB3_GRP1_EnableClock() : stm32wbxx_ll_bus.h
  • LL_C2_APB3_GRP1_EnableClockSleep() : stm32wbxx_ll_bus.h
  • LL_C2_APB3_GRP1_IsEnabledClock() : stm32wbxx_ll_bus.h
  • LL_C2_DBGMCU_APB1_GRP1_FreezePeriph() : stm32wbxx_ll_system.h
  • LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph() : stm32wbxx_ll_system.h
  • LL_C2_DBGMCU_APB1_GRP2_FreezePeriph() : stm32wbxx_ll_system.h
  • LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph() : stm32wbxx_ll_system.h
  • LL_C2_DBGMCU_APB2_GRP1_FreezePeriph() : stm32wbxx_ll_system.h
  • LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph() : stm32wbxx_ll_system.h
  • LL_C2_EXTI_DisableEvent_0_31() : stm32wbxx_ll_exti.h
  • LL_C2_EXTI_DisableEvent_32_63() : stm32wbxx_ll_exti.h
  • LL_C2_EXTI_DisableIT_0_31() : stm32wbxx_ll_exti.h
  • LL_C2_EXTI_DisableIT_32_63() : stm32wbxx_ll_exti.h
  • LL_C2_EXTI_EnableEvent_0_31() : stm32wbxx_ll_exti.h
  • LL_C2_EXTI_EnableEvent_32_63() : stm32wbxx_ll_exti.h
  • LL_C2_EXTI_EnableIT_0_31() : stm32wbxx_ll_exti.h
  • LL_C2_EXTI_EnableIT_32_63() : stm32wbxx_ll_exti.h
  • LL_C2_EXTI_IsEnabledEvent_0_31() : stm32wbxx_ll_exti.h
  • LL_C2_EXTI_IsEnabledEvent_32_63() : stm32wbxx_ll_exti.h
  • LL_C2_EXTI_IsEnabledIT_0_31() : stm32wbxx_ll_exti.h
  • LL_C2_EXTI_IsEnabledIT_32_63() : stm32wbxx_ll_exti.h
  • LL_C2_IPCC_ClearFlag_CHx() : stm32wbxx_ll_ipcc.h
  • LL_C2_IPCC_DisableIT_RXO() : stm32wbxx_ll_ipcc.h
  • LL_C2_IPCC_DisableIT_TXF() : stm32wbxx_ll_ipcc.h
  • LL_C2_IPCC_DisableReceiveChannel() : stm32wbxx_ll_ipcc.h
  • LL_C2_IPCC_DisableTransmitChannel() : stm32wbxx_ll_ipcc.h
  • LL_C2_IPCC_EnableIT_RXO() : stm32wbxx_ll_ipcc.h
  • LL_C2_IPCC_EnableIT_TXF() : stm32wbxx_ll_ipcc.h
  • LL_C2_IPCC_EnableReceiveChannel() : stm32wbxx_ll_ipcc.h
  • LL_C2_IPCC_EnableTransmitChannel() : stm32wbxx_ll_ipcc.h
  • LL_C2_IPCC_IsActiveFlag_CHx() : stm32wbxx_ll_ipcc.h
  • LL_C2_IPCC_IsEnabledIT_RXO() : stm32wbxx_ll_ipcc.h
  • LL_C2_IPCC_IsEnabledIT_TXF() : stm32wbxx_ll_ipcc.h
  • LL_C2_IPCC_IsEnabledReceiveChannel() : stm32wbxx_ll_ipcc.h
  • LL_C2_IPCC_IsEnabledTransmitChannel() : stm32wbxx_ll_ipcc.h
  • LL_C2_IPCC_SetFlag_CHx() : stm32wbxx_ll_ipcc.h
  • LL_C2_PWR_DisableInternWU() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_DisableIT_802WU() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_DisableIT_BLEWU() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_DisablePUPDCfg() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_DisableWakeUpPin() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_EnableInternWU() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_EnableIT_802WU() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_EnableIT_BLEWU() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_EnablePUPDCfg() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_EnableWakeUpPin() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_GetFlashPowerModeLPRun() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_GetFlashPowerModeSleep() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_GetPowerMode() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_IsEnabledInternWU() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_IsEnabledIT_802WU() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_IsEnabledIT_BLEWU() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_IsEnabledPUPDCfg() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_IsEnabledWakeUpPin() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_IsWokenUp_802_15_4() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_IsWokenUp_BLE() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_SetFlashPowerModeLPRun() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_SetFlashPowerModeSleep() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_SetPowerMode() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_WakeUp_802_15_4() : stm32wbxx_ll_pwr.h
  • LL_C2_PWR_WakeUp_BLE() : stm32wbxx_ll_pwr.h
  • LL_C2_RCC_GetAHBPrescaler() : stm32wbxx_ll_rcc.h
  • LL_C2_RCC_SetAHBPrescaler() : stm32wbxx_ll_rcc.h
  • LL_C2_SYSCFG_GRP1_DisableIT() : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_EnableIT() : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_IsEnabledIT() : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_DisableIT() : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_EnableIT() : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_IsEnabledIT() : stm32wbxx_ll_system.h
  • LL_COMP_ConfigInputs() : stm32wbxx_ll_comp.h
  • LL_COMP_DeInit() : stm32wbxx_ll_comp.c
  • LL_COMP_Disable() : stm32wbxx_ll_comp.h
  • LL_COMP_Enable() : stm32wbxx_ll_comp.h
  • LL_COMP_GetCommonWindowMode() : stm32wbxx_ll_comp.h
  • LL_COMP_GetInputHysteresis() : stm32wbxx_ll_comp.h
  • LL_COMP_GetInputMinus() : stm32wbxx_ll_comp.h
  • LL_COMP_GetInputPlus() : stm32wbxx_ll_comp.h
  • LL_COMP_GetOutputBlankingSource() : stm32wbxx_ll_comp.h
  • LL_COMP_GetOutputPolarity() : stm32wbxx_ll_comp.h
  • LL_COMP_GetPowerMode() : stm32wbxx_ll_comp.h
  • LL_COMP_Init() : stm32wbxx_ll_comp.c
  • LL_COMP_IsEnabled() : stm32wbxx_ll_comp.h
  • LL_COMP_IsLocked() : stm32wbxx_ll_comp.h
  • LL_COMP_Lock() : stm32wbxx_ll_comp.h
  • LL_COMP_ReadOutputLevel() : stm32wbxx_ll_comp.h
  • LL_COMP_SetCommonWindowMode() : stm32wbxx_ll_comp.h
  • LL_COMP_SetInputHysteresis() : stm32wbxx_ll_comp.h
  • LL_COMP_SetInputMinus() : stm32wbxx_ll_comp.h
  • LL_COMP_SetInputPlus() : stm32wbxx_ll_comp.h
  • LL_COMP_SetOutputBlankingSource() : stm32wbxx_ll_comp.h
  • LL_COMP_SetOutputPolarity() : stm32wbxx_ll_comp.h
  • LL_COMP_SetPowerMode() : stm32wbxx_ll_comp.h
  • LL_COMP_StructInit() : stm32wbxx_ll_comp.c
  • LL_CPUID_GetConstant() : stm32wbxx_ll_cortex.h
  • LL_CPUID_GetImplementer() : stm32wbxx_ll_cortex.h
  • LL_CPUID_GetParNo() : stm32wbxx_ll_cortex.h
  • LL_CPUID_GetRevision() : stm32wbxx_ll_cortex.h
  • LL_CPUID_GetVariant() : stm32wbxx_ll_cortex.h
  • LL_CRC_DeInit() : stm32wbxx_ll_crc.c
  • LL_CRC_FeedData16() : stm32wbxx_ll_crc.h
  • LL_CRC_FeedData32() : stm32wbxx_ll_crc.h
  • LL_CRC_FeedData8() : stm32wbxx_ll_crc.h
  • LL_CRC_GetInitialData() : stm32wbxx_ll_crc.h
  • LL_CRC_GetInputDataReverseMode() : stm32wbxx_ll_crc.h
  • LL_CRC_GetOutputDataReverseMode() : stm32wbxx_ll_crc.h
  • LL_CRC_GetPolynomialCoef() : stm32wbxx_ll_crc.h
  • LL_CRC_GetPolynomialSize() : stm32wbxx_ll_crc.h
  • LL_CRC_Read_IDR() : stm32wbxx_ll_crc.h
  • LL_CRC_ReadData16() : stm32wbxx_ll_crc.h
  • LL_CRC_ReadData32() : stm32wbxx_ll_crc.h
  • LL_CRC_ReadData7() : stm32wbxx_ll_crc.h
  • LL_CRC_ReadData8() : stm32wbxx_ll_crc.h
  • LL_CRC_ResetCRCCalculationUnit() : stm32wbxx_ll_crc.h
  • LL_CRC_SetInitialData() : stm32wbxx_ll_crc.h
  • LL_CRC_SetInputDataReverseMode() : stm32wbxx_ll_crc.h
  • LL_CRC_SetOutputDataReverseMode() : stm32wbxx_ll_crc.h
  • LL_CRC_SetPolynomialCoef() : stm32wbxx_ll_crc.h
  • LL_CRC_SetPolynomialSize() : stm32wbxx_ll_crc.h
  • LL_CRC_Write_IDR() : stm32wbxx_ll_crc.h
  • LL_CRS_ClearFlag_ERR() : stm32wbxx_ll_crs.h
  • LL_CRS_ClearFlag_ESYNC() : stm32wbxx_ll_crs.h
  • LL_CRS_ClearFlag_SYNCOK() : stm32wbxx_ll_crs.h
  • LL_CRS_ClearFlag_SYNCWARN() : stm32wbxx_ll_crs.h
  • LL_CRS_ConfigSynchronization() : stm32wbxx_ll_crs.h
  • LL_CRS_DeInit() : stm32wbxx_ll_crs.c
  • LL_CRS_DisableAutoTrimming() : stm32wbxx_ll_crs.h
  • LL_CRS_DisableFreqErrorCounter() : stm32wbxx_ll_crs.h
  • LL_CRS_DisableIT_ERR() : stm32wbxx_ll_crs.h
  • LL_CRS_DisableIT_ESYNC() : stm32wbxx_ll_crs.h
  • LL_CRS_DisableIT_SYNCOK() : stm32wbxx_ll_crs.h
  • LL_CRS_DisableIT_SYNCWARN() : stm32wbxx_ll_crs.h
  • LL_CRS_EnableAutoTrimming() : stm32wbxx_ll_crs.h
  • LL_CRS_EnableFreqErrorCounter() : stm32wbxx_ll_crs.h
  • LL_CRS_EnableIT_ERR() : stm32wbxx_ll_crs.h
  • LL_CRS_EnableIT_ESYNC() : stm32wbxx_ll_crs.h
  • LL_CRS_EnableIT_SYNCOK() : stm32wbxx_ll_crs.h
  • LL_CRS_EnableIT_SYNCWARN() : stm32wbxx_ll_crs.h
  • LL_CRS_GenerateEvent_SWSYNC() : stm32wbxx_ll_crs.h
  • LL_CRS_GetFreqErrorCapture() : stm32wbxx_ll_crs.h
  • LL_CRS_GetFreqErrorDirection() : stm32wbxx_ll_crs.h
  • LL_CRS_GetFreqErrorLimit() : stm32wbxx_ll_crs.h
  • LL_CRS_GetHSI48SmoothTrimming() : stm32wbxx_ll_crs.h
  • LL_CRS_GetReloadCounter() : stm32wbxx_ll_crs.h
  • LL_CRS_GetSyncDivider() : stm32wbxx_ll_crs.h
  • LL_CRS_GetSyncPolarity() : stm32wbxx_ll_crs.h
  • LL_CRS_GetSyncSignalSource() : stm32wbxx_ll_crs.h
  • LL_CRS_IsActiveFlag_ERR() : stm32wbxx_ll_crs.h
  • LL_CRS_IsActiveFlag_ESYNC() : stm32wbxx_ll_crs.h
  • LL_CRS_IsActiveFlag_SYNCERR() : stm32wbxx_ll_crs.h
  • LL_CRS_IsActiveFlag_SYNCMISS() : stm32wbxx_ll_crs.h
  • LL_CRS_IsActiveFlag_SYNCOK() : stm32wbxx_ll_crs.h
  • LL_CRS_IsActiveFlag_SYNCWARN() : stm32wbxx_ll_crs.h
  • LL_CRS_IsActiveFlag_TRIMOVF() : stm32wbxx_ll_crs.h
  • LL_CRS_IsEnabledAutoTrimming() : stm32wbxx_ll_crs.h
  • LL_CRS_IsEnabledFreqErrorCounter() : stm32wbxx_ll_crs.h
  • LL_CRS_IsEnabledIT_ERR() : stm32wbxx_ll_crs.h
  • LL_CRS_IsEnabledIT_ESYNC() : stm32wbxx_ll_crs.h
  • LL_CRS_IsEnabledIT_SYNCOK() : stm32wbxx_ll_crs.h
  • LL_CRS_IsEnabledIT_SYNCWARN() : stm32wbxx_ll_crs.h
  • LL_CRS_SetFreqErrorLimit() : stm32wbxx_ll_crs.h
  • LL_CRS_SetHSI48SmoothTrimming() : stm32wbxx_ll_crs.h
  • LL_CRS_SetReloadCounter() : stm32wbxx_ll_crs.h
  • LL_CRS_SetSyncDivider() : stm32wbxx_ll_crs.h
  • LL_CRS_SetSyncPolarity() : stm32wbxx_ll_crs.h
  • LL_CRS_SetSyncSignalSource() : stm32wbxx_ll_crs.h
  • LL_DBGMCU_APB1_GRP1_FreezePeriph() : stm32wbxx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_UnFreezePeriph() : stm32wbxx_ll_system.h
  • LL_DBGMCU_APB1_GRP2_FreezePeriph() : stm32wbxx_ll_system.h
  • LL_DBGMCU_APB1_GRP2_UnFreezePeriph() : stm32wbxx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_FreezePeriph() : stm32wbxx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_UnFreezePeriph() : stm32wbxx_ll_system.h
  • LL_DBGMCU_DisableDBGSleepMode() : stm32wbxx_ll_system.h
  • LL_DBGMCU_DisableDBGStandbyMode() : stm32wbxx_ll_system.h
  • LL_DBGMCU_DisableDBGStopMode() : stm32wbxx_ll_system.h
  • LL_DBGMCU_DisableTraceClock() : stm32wbxx_ll_system.h
  • LL_DBGMCU_DisableTriggerOutput() : stm32wbxx_ll_system.h
  • LL_DBGMCU_EnableDBGSleepMode() : stm32wbxx_ll_system.h
  • LL_DBGMCU_EnableDBGStandbyMode() : stm32wbxx_ll_system.h
  • LL_DBGMCU_EnableDBGStopMode() : stm32wbxx_ll_system.h
  • LL_DBGMCU_EnableTraceClock() : stm32wbxx_ll_system.h
  • LL_DBGMCU_EnableTriggerOutput() : stm32wbxx_ll_system.h
  • LL_DBGMCU_GetDeviceID() : stm32wbxx_ll_system.h
  • LL_DBGMCU_GetRevisionID() : stm32wbxx_ll_system.h
  • LL_DBGMCU_IsEnabledTraceClock() : stm32wbxx_ll_system.h
  • LL_DBGMCU_IsEnabledTriggerOutput() : stm32wbxx_ll_system.h
  • LL_DMA_ClearFlag_GI1() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_GI2() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_GI3() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_GI4() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_GI5() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_GI6() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_GI7() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_HT1() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_HT2() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_HT3() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_HT4() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_HT5() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_HT6() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_HT7() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_TC1() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_TC2() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_TC3() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_TC4() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_TC5() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_TC6() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_TC7() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_TE1() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_TE2() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_TE3() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_TE4() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_TE5() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_TE6() : stm32wbxx_ll_dma.h
  • LL_DMA_ClearFlag_TE7() : stm32wbxx_ll_dma.h
  • LL_DMA_ConfigAddresses() : stm32wbxx_ll_dma.h
  • LL_DMA_ConfigTransfer() : stm32wbxx_ll_dma.h
  • LL_DMA_DeInit() : stm32wbxx_ll_dma.c
  • LL_DMA_DisableChannel() : stm32wbxx_ll_dma.h
  • LL_DMA_DisableIT_HT() : stm32wbxx_ll_dma.h
  • LL_DMA_DisableIT_TC() : stm32wbxx_ll_dma.h
  • LL_DMA_DisableIT_TE() : stm32wbxx_ll_dma.h
  • LL_DMA_EnableChannel() : stm32wbxx_ll_dma.h
  • LL_DMA_EnableIT_HT() : stm32wbxx_ll_dma.h
  • LL_DMA_EnableIT_TC() : stm32wbxx_ll_dma.h
  • LL_DMA_EnableIT_TE() : stm32wbxx_ll_dma.h
  • LL_DMA_GetChannelPriorityLevel() : stm32wbxx_ll_dma.h
  • LL_DMA_GetDataLength() : stm32wbxx_ll_dma.h
  • LL_DMA_GetDataTransferDirection() : stm32wbxx_ll_dma.h
  • LL_DMA_GetM2MDstAddress() : stm32wbxx_ll_dma.h
  • LL_DMA_GetM2MSrcAddress() : stm32wbxx_ll_dma.h
  • LL_DMA_GetMemoryAddress() : stm32wbxx_ll_dma.h
  • LL_DMA_GetMemoryIncMode() : stm32wbxx_ll_dma.h
  • LL_DMA_GetMemorySize() : stm32wbxx_ll_dma.h
  • LL_DMA_GetMode() : stm32wbxx_ll_dma.h
  • LL_DMA_GetPeriphAddress() : stm32wbxx_ll_dma.h
  • LL_DMA_GetPeriphIncMode() : stm32wbxx_ll_dma.h
  • LL_DMA_GetPeriphRequest() : stm32wbxx_ll_dma.h
  • LL_DMA_GetPeriphSize() : stm32wbxx_ll_dma.h
  • LL_DMA_Init() : stm32wbxx_ll_dma.c
  • LL_DMA_IsActiveFlag_GI1() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI2() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI3() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI4() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI5() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI6() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI7() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT1() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT2() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT3() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT4() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT5() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT6() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT7() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC1() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC2() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC3() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC4() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC5() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC6() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC7() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE1() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE2() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE3() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE4() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE5() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE6() : stm32wbxx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE7() : stm32wbxx_ll_dma.h
  • LL_DMA_IsEnabledChannel() : stm32wbxx_ll_dma.h
  • LL_DMA_IsEnabledIT_HT() : stm32wbxx_ll_dma.h
  • LL_DMA_IsEnabledIT_TC() : stm32wbxx_ll_dma.h
  • LL_DMA_IsEnabledIT_TE() : stm32wbxx_ll_dma.h
  • LL_DMA_SetChannelPriorityLevel() : stm32wbxx_ll_dma.h
  • LL_DMA_SetDataLength() : stm32wbxx_ll_dma.h
  • LL_DMA_SetDataTransferDirection() : stm32wbxx_ll_dma.h
  • LL_DMA_SetM2MDstAddress() : stm32wbxx_ll_dma.h
  • LL_DMA_SetM2MSrcAddress() : stm32wbxx_ll_dma.h
  • LL_DMA_SetMemoryAddress() : stm32wbxx_ll_dma.h
  • LL_DMA_SetMemoryIncMode() : stm32wbxx_ll_dma.h
  • LL_DMA_SetMemorySize() : stm32wbxx_ll_dma.h
  • LL_DMA_SetMode() : stm32wbxx_ll_dma.h
  • LL_DMA_SetPeriphAddress() : stm32wbxx_ll_dma.h
  • LL_DMA_SetPeriphIncMode() : stm32wbxx_ll_dma.h
  • LL_DMA_SetPeriphRequest() : stm32wbxx_ll_dma.h
  • LL_DMA_SetPeriphSize() : stm32wbxx_ll_dma.h
  • LL_DMA_StructInit() : stm32wbxx_ll_dma.c
  • LL_DMAMUX_ClearFlag_RGO0() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_RGO1() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_RGO2() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_RGO3() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO0() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO1() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO10() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO11() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO12() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO13() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO2() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO3() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO4() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO5() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO6() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO7() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO8() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_ClearFlag_SO9() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_DisableEventGeneration() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_DisableIT_RGO() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_DisableIT_SO() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_DisableRequestGen() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_DisableSync() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_EnableEventGeneration() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_EnableIT_RGO() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_EnableIT_SO() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_EnableRequestGen() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_EnableSync() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_GetGenRequestNb() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_GetRequestGenPolarity() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_GetRequestID() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_GetRequestSignalID() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_GetSyncID() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_GetSyncPolarity() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_GetSyncRequestNb() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO0() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO1() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO2() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_RGO3() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO0() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO1() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO10() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO11() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO12() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO13() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO2() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO3() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO4() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO5() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO6() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO7() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO8() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsActiveFlag_SO9() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledEventGeneration() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledIT_RGO() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledIT_SO() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledRequestGen() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_IsEnabledSync() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SetGenRequestNb() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SetRequestGenPolarity() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SetRequestID() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SetRequestSignalID() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SetSyncID() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SetSyncPolarity() : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SetSyncRequestNb() : stm32wbxx_ll_dmamux.h
  • LL_EXTI_ClearFlag_0_31() : stm32wbxx_ll_exti.h
  • LL_EXTI_ClearFlag_32_63() : stm32wbxx_ll_exti.h
  • LL_EXTI_DeInit() : stm32wbxx_ll_exti.c
  • LL_EXTI_DisableEvent_0_31() : stm32wbxx_ll_exti.h
  • LL_EXTI_DisableEvent_32_63() : stm32wbxx_ll_exti.h
  • LL_EXTI_DisableFallingTrig_0_31() : stm32wbxx_ll_exti.h
  • LL_EXTI_DisableFallingTrig_32_63() : stm32wbxx_ll_exti.h
  • LL_EXTI_DisableIT_0_31() : stm32wbxx_ll_exti.h
  • LL_EXTI_DisableIT_32_63() : stm32wbxx_ll_exti.h
  • LL_EXTI_DisableRisingTrig_0_31() : stm32wbxx_ll_exti.h
  • LL_EXTI_DisableRisingTrig_32_63() : stm32wbxx_ll_exti.h
  • LL_EXTI_EnableEvent_0_31() : stm32wbxx_ll_exti.h
  • LL_EXTI_EnableEvent_32_63() : stm32wbxx_ll_exti.h
  • LL_EXTI_EnableFallingTrig_0_31() : stm32wbxx_ll_exti.h
  • LL_EXTI_EnableFallingTrig_32_63() : stm32wbxx_ll_exti.h
  • LL_EXTI_EnableIT_0_31() : stm32wbxx_ll_exti.h
  • LL_EXTI_EnableIT_32_63() : stm32wbxx_ll_exti.h
  • LL_EXTI_EnableRisingTrig_0_31() : stm32wbxx_ll_exti.h
  • LL_EXTI_EnableRisingTrig_32_63() : stm32wbxx_ll_exti.h
  • LL_EXTI_GenerateSWI_0_31() : stm32wbxx_ll_exti.h
  • LL_EXTI_GenerateSWI_32_63() : stm32wbxx_ll_exti.h
  • LL_EXTI_Init() : stm32wbxx_ll_exti.c
  • LL_EXTI_IsActiveFlag_0_31() : stm32wbxx_ll_exti.h
  • LL_EXTI_IsActiveFlag_32_63() : stm32wbxx_ll_exti.h
  • LL_EXTI_IsEnabledEvent_0_31() : stm32wbxx_ll_exti.h
  • LL_EXTI_IsEnabledEvent_32_63() : stm32wbxx_ll_exti.h
  • LL_EXTI_IsEnabledFallingTrig_0_31() : stm32wbxx_ll_exti.h
  • LL_EXTI_IsEnabledFallingTrig_32_63() : stm32wbxx_ll_exti.h
  • LL_EXTI_IsEnabledIT_0_31() : stm32wbxx_ll_exti.h
  • LL_EXTI_IsEnabledIT_32_63() : stm32wbxx_ll_exti.h
  • LL_EXTI_IsEnabledRisingTrig_0_31() : stm32wbxx_ll_exti.h
  • LL_EXTI_IsEnabledRisingTrig_32_63() : stm32wbxx_ll_exti.h
  • LL_EXTI_ReadFlag_0_31() : stm32wbxx_ll_exti.h
  • LL_EXTI_ReadFlag_32_63() : stm32wbxx_ll_exti.h
  • LL_EXTI_StructInit() : stm32wbxx_ll_exti.c
  • LL_FLASH_AllowOperation() : stm32wbxx_ll_system.h
  • LL_FLASH_ClearEmptyFlag() : stm32wbxx_ll_system.h
  • LL_FLASH_DisableDataCache() : stm32wbxx_ll_system.h
  • LL_FLASH_DisableDataCacheReset() : stm32wbxx_ll_system.h
  • LL_FLASH_DisableInstCache() : stm32wbxx_ll_system.h
  • LL_FLASH_DisableInstCacheReset() : stm32wbxx_ll_system.h
  • LL_FLASH_DisablePrefetch() : stm32wbxx_ll_system.h
  • LL_FLASH_EnableDataCache() : stm32wbxx_ll_system.h
  • LL_FLASH_EnableDataCacheReset() : stm32wbxx_ll_system.h
  • LL_FLASH_EnableInstCache() : stm32wbxx_ll_system.h
  • LL_FLASH_EnableInstCacheReset() : stm32wbxx_ll_system.h
  • LL_FLASH_EnablePrefetch() : stm32wbxx_ll_system.h
  • LL_FLASH_GetC2BootResetVect() : stm32wbxx_ll_system.h
  • LL_FLASH_GetDeviceID() : stm32wbxx_ll_system.h
  • LL_FLASH_GetIPCCBufferAddr() : stm32wbxx_ll_system.h
  • LL_FLASH_GetLatency() : stm32wbxx_ll_system.h
  • LL_FLASH_GetSTCompanyID() : stm32wbxx_ll_system.h
  • LL_FLASH_GetUDN() : stm32wbxx_ll_system.h
  • LL_FLASH_IsActiveFlag_OperationSuspended() : stm32wbxx_ll_system.h
  • LL_FLASH_IsEmptyFlag() : stm32wbxx_ll_system.h
  • LL_FLASH_IsOperationSuspended() : stm32wbxx_ll_system.h
  • LL_FLASH_IsPrefetchEnabled() : stm32wbxx_ll_system.h
  • LL_FLASH_SetEmptyFlag() : stm32wbxx_ll_system.h
  • LL_FLASH_SetLatency() : stm32wbxx_ll_system.h
  • LL_FLASH_SuspendOperation() : stm32wbxx_ll_system.h
  • LL_GetFlashSize() : stm32wbxx_ll_utils.h
  • LL_GetPackageType() : stm32wbxx_ll_utils.h
  • LL_GetUID_Word0() : stm32wbxx_ll_utils.h
  • LL_GetUID_Word1() : stm32wbxx_ll_utils.h
  • LL_GetUID_Word2() : stm32wbxx_ll_utils.h
  • LL_GPIO_DeInit() : stm32wbxx_ll_gpio.c
  • LL_GPIO_GetAFPin_0_7() : stm32wbxx_ll_gpio.h
  • LL_GPIO_GetAFPin_8_15() : stm32wbxx_ll_gpio.h
  • LL_GPIO_GetPinMode() : stm32wbxx_ll_gpio.h
  • LL_GPIO_GetPinOutputType() : stm32wbxx_ll_gpio.h
  • LL_GPIO_GetPinPull() : stm32wbxx_ll_gpio.h
  • LL_GPIO_GetPinSpeed() : stm32wbxx_ll_gpio.h
  • LL_GPIO_Init() : stm32wbxx_ll_gpio.c
  • LL_GPIO_IsAnyPinLocked() : stm32wbxx_ll_gpio.h
  • LL_GPIO_IsInputPinSet() : stm32wbxx_ll_gpio.h
  • LL_GPIO_IsOutputPinSet() : stm32wbxx_ll_gpio.h
  • LL_GPIO_IsPinLocked() : stm32wbxx_ll_gpio.h
  • LL_GPIO_LockPin() : stm32wbxx_ll_gpio.h
  • LL_GPIO_ReadInputPort() : stm32wbxx_ll_gpio.h
  • LL_GPIO_ReadOutputPort() : stm32wbxx_ll_gpio.h
  • LL_GPIO_ResetOutputPin() : stm32wbxx_ll_gpio.h
  • LL_GPIO_SetAFPin_0_7() : stm32wbxx_ll_gpio.h
  • LL_GPIO_SetAFPin_8_15() : stm32wbxx_ll_gpio.h
  • LL_GPIO_SetOutputPin() : stm32wbxx_ll_gpio.h
  • LL_GPIO_SetPinMode() : stm32wbxx_ll_gpio.h
  • LL_GPIO_SetPinOutputType() : stm32wbxx_ll_gpio.h
  • LL_GPIO_SetPinPull() : stm32wbxx_ll_gpio.h
  • LL_GPIO_SetPinSpeed() : stm32wbxx_ll_gpio.h
  • LL_GPIO_StructInit() : stm32wbxx_ll_gpio.c
  • LL_GPIO_TogglePin() : stm32wbxx_ll_gpio.h
  • LL_GPIO_WriteOutputPort() : stm32wbxx_ll_gpio.h
  • LL_HANDLER_DisableFault() : stm32wbxx_ll_cortex.h
  • LL_HANDLER_EnableFault() : stm32wbxx_ll_cortex.h
  • LL_HSEM_1StepLock() : stm32wbxx_ll_hsem.h
  • LL_HSEM_2StepLock() : stm32wbxx_ll_hsem.h
  • LL_HSEM_ClearFlag_C1ICR() : stm32wbxx_ll_hsem.h
  • LL_HSEM_ClearFlag_C2ICR() : stm32wbxx_ll_hsem.h
  • LL_HSEM_DisableIT_C1IER() : stm32wbxx_ll_hsem.h
  • LL_HSEM_DisableIT_C2IER() : stm32wbxx_ll_hsem.h
  • LL_HSEM_EnableIT_C1IER() : stm32wbxx_ll_hsem.h
  • LL_HSEM_EnableIT_C2IER() : stm32wbxx_ll_hsem.h
  • LL_HSEM_GetCoreId() : stm32wbxx_ll_hsem.h
  • LL_HSEM_GetKey() : stm32wbxx_ll_hsem.h
  • LL_HSEM_GetProcessId() : stm32wbxx_ll_hsem.h
  • LL_HSEM_GetStatus() : stm32wbxx_ll_hsem.h
  • LL_HSEM_IsActiveFlag_C1ISR() : stm32wbxx_ll_hsem.h
  • LL_HSEM_IsActiveFlag_C1MISR() : stm32wbxx_ll_hsem.h
  • LL_HSEM_IsActiveFlag_C2ISR() : stm32wbxx_ll_hsem.h
  • LL_HSEM_IsActiveFlag_C2MISR() : stm32wbxx_ll_hsem.h
  • LL_HSEM_IsEnabledIT_C1IER() : stm32wbxx_ll_hsem.h
  • LL_HSEM_IsEnabledIT_C2IER() : stm32wbxx_ll_hsem.h
  • LL_HSEM_IsSemaphoreLocked() : stm32wbxx_ll_hsem.h
  • LL_HSEM_ReleaseLock() : stm32wbxx_ll_hsem.h
  • LL_HSEM_ResetAllLock() : stm32wbxx_ll_hsem.h
  • LL_HSEM_SetKey() : stm32wbxx_ll_hsem.h
  • LL_HSEM_SetLock() : stm32wbxx_ll_hsem.h
  • LL_I2C_AcknowledgeNextData() : stm32wbxx_ll_i2c.h
  • LL_I2C_ClearFlag_ADDR() : stm32wbxx_ll_i2c.h
  • LL_I2C_ClearFlag_ARLO() : stm32wbxx_ll_i2c.h
  • LL_I2C_ClearFlag_BERR() : stm32wbxx_ll_i2c.h
  • LL_I2C_ClearFlag_NACK() : stm32wbxx_ll_i2c.h
  • LL_I2C_ClearFlag_OVR() : stm32wbxx_ll_i2c.h
  • LL_I2C_ClearFlag_STOP() : stm32wbxx_ll_i2c.h
  • LL_I2C_ClearFlag_TXE() : stm32wbxx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_ALERT() : stm32wbxx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_PECERR() : stm32wbxx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_TIMEOUT() : stm32wbxx_ll_i2c.h
  • LL_I2C_ConfigFilters() : stm32wbxx_ll_i2c.h
  • LL_I2C_ConfigSMBusTimeout() : stm32wbxx_ll_i2c.h
  • LL_I2C_DeInit() : stm32wbxx_ll_i2c.c
  • LL_I2C_Disable() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableAnalogFilter() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableAuto10BitRead() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableAutoEndMode() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableClockStretching() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableDMAReq_RX() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableDMAReq_TX() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableGeneralCall() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableIT_ADDR() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableIT_ERR() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableIT_NACK() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableIT_RX() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableIT_STOP() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableIT_TC() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableIT_TX() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableOwnAddress1() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableOwnAddress2() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableReloadMode() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableSlaveByteControl() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableSMBusAlert() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableSMBusPEC() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableSMBusTimeout() : stm32wbxx_ll_i2c.h
  • LL_I2C_DisableWakeUpFromStop() : stm32wbxx_ll_i2c.h
  • LL_I2C_DMA_GetRegAddr() : stm32wbxx_ll_i2c.h
  • LL_I2C_Enable() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableAnalogFilter() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableAuto10BitRead() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableAutoEndMode() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableClockStretching() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableDMAReq_RX() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableDMAReq_TX() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableGeneralCall() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableIT_ADDR() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableIT_ERR() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableIT_NACK() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableIT_RX() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableIT_STOP() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableIT_TC() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableIT_TX() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableOwnAddress1() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableOwnAddress2() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableReloadMode() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableSlaveByteControl() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableSMBusAlert() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableSMBusPEC() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableSMBusPECCompare() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableSMBusTimeout() : stm32wbxx_ll_i2c.h
  • LL_I2C_EnableWakeUpFromStop() : stm32wbxx_ll_i2c.h
  • LL_I2C_GenerateStartCondition() : stm32wbxx_ll_i2c.h
  • LL_I2C_GenerateStopCondition() : stm32wbxx_ll_i2c.h
  • LL_I2C_GetAddressMatchCode() : stm32wbxx_ll_i2c.h
  • LL_I2C_GetClockHighPeriod() : stm32wbxx_ll_i2c.h
  • LL_I2C_GetClockLowPeriod() : stm32wbxx_ll_i2c.h
  • LL_I2C_GetDataHoldTime() : stm32wbxx_ll_i2c.h
  • LL_I2C_GetDataSetupTime() : stm32wbxx_ll_i2c.h
  • LL_I2C_GetDigitalFilter() : stm32wbxx_ll_i2c.h
  • LL_I2C_GetMasterAddressingMode() : stm32wbxx_ll_i2c.h
  • LL_I2C_GetMode() : stm32wbxx_ll_i2c.h
  • LL_I2C_GetSlaveAddr() : stm32wbxx_ll_i2c.h
  • LL_I2C_GetSMBusPEC() : stm32wbxx_ll_i2c.h
  • LL_I2C_GetSMBusTimeoutA() : stm32wbxx_ll_i2c.h
  • LL_I2C_GetSMBusTimeoutAMode() : stm32wbxx_ll_i2c.h
  • LL_I2C_GetSMBusTimeoutB() : stm32wbxx_ll_i2c.h
  • LL_I2C_GetTimingPrescaler() : stm32wbxx_ll_i2c.h
  • LL_I2C_GetTransferDirection() : stm32wbxx_ll_i2c.h
  • LL_I2C_GetTransferRequest() : stm32wbxx_ll_i2c.h
  • LL_I2C_GetTransferSize() : stm32wbxx_ll_i2c.h
  • LL_I2C_HandleTransfer() : stm32wbxx_ll_i2c.h
  • LL_I2C_Init() : stm32wbxx_ll_i2c.c
  • LL_I2C_IsActiveFlag_ADDR() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsActiveFlag_ARLO() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsActiveFlag_BERR() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsActiveFlag_BUSY() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsActiveFlag_NACK() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsActiveFlag_OVR() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsActiveFlag_RXNE() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsActiveFlag_STOP() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TC() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TCR() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TXE() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TXIS() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_ALERT() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_PECERR() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_TIMEOUT() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabled() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledAnalogFilter() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledAuto10BitRead() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledAutoEndMode() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledClockStretching() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledDMAReq_RX() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledDMAReq_TX() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledGeneralCall() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledIT_ADDR() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledIT_ERR() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledIT_NACK() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledIT_RX() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledIT_STOP() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledIT_TC() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledIT_TX() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledOwnAddress1() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledOwnAddress2() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledReloadMode() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledSlaveByteControl() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusAlert() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusPEC() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusPECCompare() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusTimeout() : stm32wbxx_ll_i2c.h
  • LL_I2C_IsEnabledWakeUpFromStop() : stm32wbxx_ll_i2c.h
  • LL_I2C_ReceiveData8() : stm32wbxx_ll_i2c.h
  • LL_I2C_SetDigitalFilter() : stm32wbxx_ll_i2c.h
  • LL_I2C_SetMasterAddressingMode() : stm32wbxx_ll_i2c.h
  • LL_I2C_SetMode() : stm32wbxx_ll_i2c.h
  • LL_I2C_SetOwnAddress1() : stm32wbxx_ll_i2c.h
  • LL_I2C_SetOwnAddress2() : stm32wbxx_ll_i2c.h
  • LL_I2C_SetSlaveAddr() : stm32wbxx_ll_i2c.h
  • LL_I2C_SetSMBusTimeoutA() : stm32wbxx_ll_i2c.h
  • LL_I2C_SetSMBusTimeoutAMode() : stm32wbxx_ll_i2c.h
  • LL_I2C_SetSMBusTimeoutB() : stm32wbxx_ll_i2c.h
  • LL_I2C_SetTiming() : stm32wbxx_ll_i2c.h
  • LL_I2C_SetTransferRequest() : stm32wbxx_ll_i2c.h
  • LL_I2C_SetTransferSize() : stm32wbxx_ll_i2c.h
  • LL_I2C_StructInit() : stm32wbxx_ll_i2c.c
  • LL_I2C_TransmitData8() : stm32wbxx_ll_i2c.h
  • LL_Init1msTick() : stm32wbxx_ll_utils.c
  • LL_InitTick() : stm32wbxx_ll_utils.h
  • LL_IWDG_DisableWriteAccess() : stm32wbxx_ll_iwdg.h
  • LL_IWDG_Enable() : stm32wbxx_ll_iwdg.h
  • LL_IWDG_EnableWriteAccess() : stm32wbxx_ll_iwdg.h
  • LL_IWDG_GetPrescaler() : stm32wbxx_ll_iwdg.h
  • LL_IWDG_GetReloadCounter() : stm32wbxx_ll_iwdg.h
  • LL_IWDG_GetWindow() : stm32wbxx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_PVU() : stm32wbxx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_RVU() : stm32wbxx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_WVU() : stm32wbxx_ll_iwdg.h
  • LL_IWDG_IsReady() : stm32wbxx_ll_iwdg.h
  • LL_IWDG_ReloadCounter() : stm32wbxx_ll_iwdg.h
  • LL_IWDG_SetPrescaler() : stm32wbxx_ll_iwdg.h
  • LL_IWDG_SetReloadCounter() : stm32wbxx_ll_iwdg.h
  • LL_IWDG_SetWindow() : stm32wbxx_ll_iwdg.h
  • LL_LPM_DisableEventOnPend() : stm32wbxx_ll_cortex.h
  • LL_LPM_DisableSleepOnExit() : stm32wbxx_ll_cortex.h
  • LL_LPM_EnableDeepSleep() : stm32wbxx_ll_cortex.h
  • LL_LPM_EnableEventOnPend() : stm32wbxx_ll_cortex.h
  • LL_LPM_EnableSleep() : stm32wbxx_ll_cortex.h
  • LL_LPM_EnableSleepOnExit() : stm32wbxx_ll_cortex.h
  • LL_LPTIM_ClearFLAG_ARRM() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ClearFlag_ARROK() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ClearFLAG_CMPM() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ClearFlag_CMPOK() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ClearFlag_DOWN() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ClearFlag_EXTTRIG() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ClearFlag_UP() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ConfigClock() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ConfigOutput() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ConfigTrigger() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_DeInit() : stm32wbxx_ll_lptim.c
  • LL_LPTIM_Disable() : stm32wbxx_ll_lptim.c , stm32wbxx_ll_lptim.h
  • LL_LPTIM_DisableEncoderMode() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_DisableIT_ARRM() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_DisableIT_ARROK() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_DisableIT_CMPM() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_DisableIT_CMPOK() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_DisableIT_DOWN() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_DisableIT_EXTTRIG() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_DisableIT_UP() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_DisableResetAfterRead() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_DisableTimeout() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_Enable() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_EnableEncoderMode() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_EnableIT_ARRM() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_EnableIT_ARROK() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_EnableIT_CMPM() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_EnableIT_CMPOK() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_EnableIT_DOWN() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_EnableIT_EXTTRIG() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_EnableIT_UP() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_EnableResetAfterRead() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_EnableTimeout() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_GetAutoReload() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_GetClockFilter() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_GetClockPolarity() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_GetClockSource() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_GetCompare() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_GetCounter() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_GetCounterMode() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_GetEncoderMode() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_GetPolarity() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_GetPrescaler() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_GetTriggerFilter() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_GetTriggerPolarity() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_GetTriggerSource() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_GetUpdateMode() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_GetWaveform() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_Init() : stm32wbxx_ll_lptim.c
  • LL_LPTIM_IsActiveFlag_ARRM() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_ARROK() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_CMPM() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_CMPOK() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_DOWN() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_EXTTRIG() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IsActiveFlag_UP() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IsEnabled() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IsEnabledEncoderMode() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_ARRM() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_ARROK() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_CMPM() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_CMPOK() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_DOWN() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_EXTTRIG() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IsEnabledIT_UP() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IsEnabledResetAfterRead() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IsEnabledTimeout() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ResetCounter() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_SetAutoReload() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_SetClockSource() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_SetCompare() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_SetCounterMode() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_SetEncoderMode() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_SetInput1Src() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_SetInput2Src() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_SetPolarity() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_SetPrescaler() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_SetUpdateMode() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_SetWaveform() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_StartCounter() : stm32wbxx_ll_lptim.h
  • LL_LPTIM_StructInit() : stm32wbxx_ll_lptim.c
  • LL_LPTIM_TrigSw() : stm32wbxx_ll_lptim.h
  • LL_LPUART_ClearFlag_CM() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ClearFlag_FE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ClearFlag_IDLE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ClearFlag_nCTS() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ClearFlag_NE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ClearFlag_ORE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ClearFlag_PE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ClearFlag_TC() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ClearFlag_TXFE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ClearFlag_WKUP() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ConfigCharacter() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ConfigFIFOsThreshold() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ConfigNodeAddress() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DeInit() : stm32wbxx_ll_lpuart.c
  • LL_LPUART_Disable() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableCTSHWFlowCtrl() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableDEMode() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableDirectionRx() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableDirectionTx() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableDMADeactOnRxErr() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableDMAReq_RX() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableDMAReq_TX() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableFIFO() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableHalfDuplex() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableInStopMode() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableIT_CM() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableIT_CTS() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableIT_ERROR() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableIT_IDLE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableIT_PE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableIT_RXFF() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableIT_RXFT() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableIT_RXNE_RXFNE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableIT_TC() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableIT_TXE_TXFNF() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableIT_TXFE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableIT_TXFT() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableIT_WKUP() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableMuteMode() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableOverrunDetect() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableRTSHWFlowCtrl() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DMA_GetRegAddr() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_Enable() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableCTSHWFlowCtrl() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableDEMode() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableDirectionRx() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableDirectionTx() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableDMADeactOnRxErr() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableDMAReq_RX() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableDMAReq_TX() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableFIFO() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableHalfDuplex() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableInStopMode() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableIT_CM() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableIT_CTS() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableIT_ERROR() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableIT_IDLE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableIT_PE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableIT_RXFF() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableIT_RXFT() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableIT_RXNE_RXFNE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableIT_TC() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableIT_TXE_TXFNF() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableIT_TXFE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableIT_TXFT() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableIT_WKUP() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableMuteMode() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableOverrunDetect() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableRTSHWFlowCtrl() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetBaudRate() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetBinaryDataLogic() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetDataWidth() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetDEAssertionTime() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetDEDeassertionTime() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetDESignalPolarity() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetHWFlowCtrl() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetNodeAddress() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetNodeAddressLen() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetParity() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetPrescaler() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetRXFIFOThreshold() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetRXPinLevel() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetStopBitsLength() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetTransferBitOrder() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetTransferDirection() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetTXFIFOThreshold() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetTXPinLevel() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetTXRXSwap() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetWakeUpMethod() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_GetWKUPType() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_Init() : stm32wbxx_ll_lpuart.c
  • LL_LPUART_IsActiveFlag_BUSY() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_CM() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_CTS() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_FE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_IDLE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_nCTS() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_NE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_ORE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_PE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_REACK() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RWU() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RXFF() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RXFT() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RXNE_RXFNE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_SBK() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TC() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TEACK() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TXE_TXFNF() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TXFE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TXFT() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_WKUP() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabled() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledDEMode() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledDMADeactOnRxErr() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledDMAReq_RX() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledDMAReq_TX() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledFIFO() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledHalfDuplex() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledInStopMode() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_CM() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_CTS() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_ERROR() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_IDLE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_PE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_RXFF() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_RXFT() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_RXNE_RXFNE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TC() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TXE_TXFNF() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TXFE() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TXFT() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_WKUP() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledMuteMode() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledOverrunDetect() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ReceiveData8() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ReceiveData9() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_RequestBreakSending() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_RequestEnterMuteMode() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_RequestRxDataFlush() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_SetBaudRate() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_SetBinaryDataLogic() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_SetDataWidth() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_SetDEAssertionTime() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_SetDEDeassertionTime() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_SetDESignalPolarity() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_SetHWFlowCtrl() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_SetParity() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_SetPrescaler() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_SetRXFIFOThreshold() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_SetRXPinLevel() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_SetStopBitsLength() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_SetTransferBitOrder() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_SetTransferDirection() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_SetTXFIFOThreshold() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_SetTXPinLevel() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_SetTXRXSwap() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_SetWakeUpMethod() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_SetWKUPType() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_StructInit() : stm32wbxx_ll_lpuart.c
  • LL_LPUART_TransmitData8() : stm32wbxx_ll_lpuart.h
  • LL_LPUART_TransmitData9() : stm32wbxx_ll_lpuart.h
  • LL_mDelay() : stm32wbxx_ll_utils.c
  • LL_MPU_ConfigRegion() : stm32wbxx_ll_cortex.h
  • LL_MPU_Disable() : stm32wbxx_ll_cortex.h
  • LL_MPU_DisableRegion() : stm32wbxx_ll_cortex.h
  • LL_MPU_Enable() : stm32wbxx_ll_cortex.h
  • LL_MPU_EnableRegion() : stm32wbxx_ll_cortex.h
  • LL_MPU_IsEnabled() : stm32wbxx_ll_cortex.h
  • LL_PKA_ClearFlag_ADDERR() : stm32wbxx_ll_pka.h
  • LL_PKA_ClearFlag_PROCEND() : stm32wbxx_ll_pka.h
  • LL_PKA_ClearFlag_RAMERR() : stm32wbxx_ll_pka.h
  • LL_PKA_Config() : stm32wbxx_ll_pka.h
  • LL_PKA_DeInit() : stm32wbxx_ll_pka.c
  • LL_PKA_Disable() : stm32wbxx_ll_pka.h
  • LL_PKA_DisableIT_ADDERR() : stm32wbxx_ll_pka.h
  • LL_PKA_DisableIT_PROCEND() : stm32wbxx_ll_pka.h
  • LL_PKA_DisableIT_RAMERR() : stm32wbxx_ll_pka.h
  • LL_PKA_Enable() : stm32wbxx_ll_pka.h
  • LL_PKA_EnableIT_ADDRERR() : stm32wbxx_ll_pka.h
  • LL_PKA_EnableIT_PROCEND() : stm32wbxx_ll_pka.h
  • LL_PKA_EnableIT_RAMERR() : stm32wbxx_ll_pka.h
  • LL_PKA_GetMode() : stm32wbxx_ll_pka.h
  • LL_PKA_Init() : stm32wbxx_ll_pka.c
  • LL_PKA_IsActiveFlag_ADDRERR() : stm32wbxx_ll_pka.h
  • LL_PKA_IsActiveFlag_BUSY() : stm32wbxx_ll_pka.h
  • LL_PKA_IsActiveFlag_PROCEND() : stm32wbxx_ll_pka.h
  • LL_PKA_IsActiveFlag_RAMERR() : stm32wbxx_ll_pka.h
  • LL_PKA_IsEnabled() : stm32wbxx_ll_pka.h
  • LL_PKA_IsEnabledIT_ADDRERR() : stm32wbxx_ll_pka.h
  • LL_PKA_IsEnabledIT_PROCEND() : stm32wbxx_ll_pka.h
  • LL_PKA_IsEnabledIT_RAMERR() : stm32wbxx_ll_pka.h
  • LL_PKA_SetMode() : stm32wbxx_ll_pka.h
  • LL_PKA_Start() : stm32wbxx_ll_pka.h
  • LL_PKA_StructInit() : stm32wbxx_ll_pka.c
  • LL_PLL_ConfigSystemClock_HSE() : stm32wbxx_ll_utils.c
  • LL_PLL_ConfigSystemClock_HSI() : stm32wbxx_ll_utils.c
  • LL_PLL_ConfigSystemClock_MSI() : stm32wbxx_ll_utils.c
  • LL_PWR_ClearFlag_802A() : stm32wbxx_ll_pwr.h
  • LL_PWR_ClearFlag_802WU() : stm32wbxx_ll_pwr.h
  • LL_PWR_ClearFlag_BLEA() : stm32wbxx_ll_pwr.h
  • LL_PWR_ClearFlag_BLEWU() : stm32wbxx_ll_pwr.h
  • LL_PWR_ClearFlag_BORH() : stm32wbxx_ll_pwr.h
  • LL_PWR_ClearFlag_C1STOP_C1STB() : stm32wbxx_ll_pwr.h
  • LL_PWR_ClearFlag_C2H() : stm32wbxx_ll_pwr.h
  • LL_PWR_ClearFlag_C2STOP_C2STB() : stm32wbxx_ll_pwr.h
  • LL_PWR_ClearFlag_CRP() : stm32wbxx_ll_pwr.h
  • LL_PWR_ClearFlag_CRPE() : stm32wbxx_ll_pwr.h
  • LL_PWR_ClearFlag_SMPSFB() : stm32wbxx_ll_pwr.h
  • LL_PWR_ClearFlag_WU() : stm32wbxx_ll_pwr.h
  • LL_PWR_ClearFlag_WU1() : stm32wbxx_ll_pwr.h
  • LL_PWR_ClearFlag_WU2() : stm32wbxx_ll_pwr.h
  • LL_PWR_ClearFlag_WU3() : stm32wbxx_ll_pwr.h
  • LL_PWR_ClearFlag_WU4() : stm32wbxx_ll_pwr.h
  • LL_PWR_ClearFlag_WU5() : stm32wbxx_ll_pwr.h
  • LL_PWR_DeInit() : stm32wbxx_ll_pwr.c
  • LL_PWR_DisableBatteryCharging() : stm32wbxx_ll_pwr.h
  • LL_PWR_DisableBkUpAccess() : stm32wbxx_ll_pwr.h
  • LL_PWR_DisableBootC2() : stm32wbxx_ll_pwr.h
  • LL_PWR_DisableGPIOPullDown() : stm32wbxx_ll_pwr.h
  • LL_PWR_DisableGPIOPullUp() : stm32wbxx_ll_pwr.h
  • LL_PWR_DisableInternWU() : stm32wbxx_ll_pwr.h
  • LL_PWR_DisableIT_802A() : stm32wbxx_ll_pwr.h
  • LL_PWR_DisableIT_BLEA() : stm32wbxx_ll_pwr.h
  • LL_PWR_DisableIT_BORH_SMPSFB() : stm32wbxx_ll_pwr.h
  • LL_PWR_DisableIT_CRPE() : stm32wbxx_ll_pwr.h
  • LL_PWR_DisableIT_HoldCPU2() : stm32wbxx_ll_pwr.h
  • LL_PWR_DisablePUPDCfg() : stm32wbxx_ll_pwr.h
  • LL_PWR_DisablePVD() : stm32wbxx_ll_pwr.h
  • LL_PWR_DisablePVM() : stm32wbxx_ll_pwr.h
  • LL_PWR_DisableSRAM2Retention() : stm32wbxx_ll_pwr.h
  • LL_PWR_DisableVddUSB() : stm32wbxx_ll_pwr.h
  • LL_PWR_DisableWakeUpPin() : stm32wbxx_ll_pwr.h
  • LL_PWR_EnableBatteryCharging() : stm32wbxx_ll_pwr.h
  • LL_PWR_EnableBkUpAccess() : stm32wbxx_ll_pwr.h
  • LL_PWR_EnableBootC2() : stm32wbxx_ll_pwr.h
  • LL_PWR_EnableGPIOPullDown() : stm32wbxx_ll_pwr.h
  • LL_PWR_EnableGPIOPullUp() : stm32wbxx_ll_pwr.h
  • LL_PWR_EnableInternWU() : stm32wbxx_ll_pwr.h
  • LL_PWR_EnableIT_802A() : stm32wbxx_ll_pwr.h
  • LL_PWR_EnableIT_BLEA() : stm32wbxx_ll_pwr.h
  • LL_PWR_EnableIT_BORH_SMPSFB() : stm32wbxx_ll_pwr.h
  • LL_PWR_EnableIT_CRPE() : stm32wbxx_ll_pwr.h
  • LL_PWR_EnableIT_HoldCPU2() : stm32wbxx_ll_pwr.h
  • LL_PWR_EnablePUPDCfg() : stm32wbxx_ll_pwr.h
  • LL_PWR_EnablePVD() : stm32wbxx_ll_pwr.h
  • LL_PWR_EnablePVM() : stm32wbxx_ll_pwr.h
  • LL_PWR_EnableSRAM2Retention() : stm32wbxx_ll_pwr.h
  • LL_PWR_EnableVddUSB() : stm32wbxx_ll_pwr.h
  • LL_PWR_EnableWakeUpPin() : stm32wbxx_ll_pwr.h
  • LL_PWR_EnterLowPowerRunMode() : stm32wbxx_ll_pwr.h
  • LL_PWR_ExitLowPowerRunMode() : stm32wbxx_ll_pwr.h
  • LL_PWR_GetBattChargResistor() : stm32wbxx_ll_pwr.h
  • LL_PWR_GetBORConfig() : stm32wbxx_ll_pwr.h
  • LL_PWR_GetFlashPowerModeLPRun() : stm32wbxx_ll_pwr.h
  • LL_PWR_GetFlashPowerModeSleep() : stm32wbxx_ll_pwr.h
  • LL_PWR_GetPowerMode() : stm32wbxx_ll_pwr.h
  • LL_PWR_GetPVDLevel() : stm32wbxx_ll_pwr.h
  • LL_PWR_GetRegulVoltageScaling() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_802A() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_802WU() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_BLEA() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_BLEWU() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_BORH() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_C1DS() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_C1SB() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_C1STOP() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_C2DS() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_C2H() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_C2SB() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_C2STOP() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_CRP() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_CRPE() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_InternWU() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_PVDO() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_PVMO1() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_PVMO3() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_REGLPF() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_REGLPS() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_SMPSFB() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_VOS() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU1() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU2() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU3() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU4() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU5() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsEnabledBatteryCharging() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsEnabledBkUpAccess() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsEnabledBootC2() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsEnabledGPIOPullDown() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsEnabledGPIOPullUp() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsEnabledInternWU() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsEnabledIT_802A() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsEnabledIT_BLEA() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsEnabledIT_BORH_SMPSFB() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsEnabledIT_CRPE() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsEnabledIT_HoldCPU2() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsEnabledLowPowerRunMode() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsEnabledPUPDCfg() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsEnabledPVD() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsEnabledPVM() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsEnabledSRAM2Retention() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsEnabledVddUSB() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsEnabledWakeUpPin() : stm32wbxx_ll_pwr.h
  • LL_PWR_IsWakeUpPinPolarityLow() : stm32wbxx_ll_pwr.h
  • LL_PWR_SetBattChargResistor() : stm32wbxx_ll_pwr.h
  • LL_PWR_SetBORConfig() : stm32wbxx_ll_pwr.h
  • LL_PWR_SetFlashPowerModeLPRun() : stm32wbxx_ll_pwr.h
  • LL_PWR_SetFlashPowerModeSleep() : stm32wbxx_ll_pwr.h
  • LL_PWR_SetPowerMode() : stm32wbxx_ll_pwr.h
  • LL_PWR_SetPVDLevel() : stm32wbxx_ll_pwr.h
  • LL_PWR_SetRegulVoltageScaling() : stm32wbxx_ll_pwr.h
  • LL_PWR_SetWakeUpPinPolarityHigh() : stm32wbxx_ll_pwr.h
  • LL_PWR_SetWakeUpPinPolarityLow() : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_Disable() : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_Enable() : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_GetEffectiveMode() : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_GetMode() : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_GetOutputVoltageLevel() : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_GetStartupCurrent() : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_IsEnabled() : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_SetMode() : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_SetOutputVoltageLevel() : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_SetStartupCurrent() : stm32wbxx_ll_pwr.h
  • LL_RCC_ClearFlag_HSECSS() : stm32wbxx_ll_rcc.h
  • LL_RCC_ClearFlag_HSERDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_ClearFlag_HSI48RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_ClearFlag_HSIRDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_ClearFlag_LSECSS() : stm32wbxx_ll_rcc.h
  • LL_RCC_ClearFlag_LSERDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_ClearFlag_LSI1RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_ClearFlag_LSI2RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_ClearFlag_MSIRDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_ClearFlag_PLLRDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_ClearFlag_PLLSAI1RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_ClearResetFlags() : stm32wbxx_ll_rcc.h
  • LL_RCC_ConfigMCO() : stm32wbxx_ll_rcc.h
  • LL_RCC_ConfigRNGClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_DeInit() : stm32wbxx_ll_rcc.c
  • LL_RCC_DisableIT_HSERDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_DisableIT_HSI48RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_DisableIT_HSIRDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_DisableIT_LSECSS() : stm32wbxx_ll_rcc.h
  • LL_RCC_DisableIT_LSERDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_DisableIT_LSI1RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_DisableIT_LSI2RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_DisableIT_MSIRDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_DisableIT_PLLRDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_DisableIT_PLLSAI1RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_DisableRTC() : stm32wbxx_ll_rcc.h
  • LL_RCC_EnableIT_HSERDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_EnableIT_HSI48RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_EnableIT_HSIRDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_EnableIT_LSECSS() : stm32wbxx_ll_rcc.h
  • LL_RCC_EnableIT_LSERDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_EnableIT_LSI1RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_EnableIT_LSI2RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_EnableIT_MSIRDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_EnableIT_PLLRDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_EnableIT_PLLSAI1RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_EnableRTC() : stm32wbxx_ll_rcc.h
  • LL_RCC_ForceBackupDomainReset() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetADCClockFreq() : stm32wbxx_ll_rcc.c
  • LL_RCC_GetADCClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetAHB4Prescaler() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetAHBPrescaler() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetAPB1Prescaler() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetAPB2Prescaler() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetCLK48ClockFreq() : stm32wbxx_ll_rcc.c
  • LL_RCC_GetCLK48ClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetClkAfterWakeFromStop() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetI2CClockFreq() : stm32wbxx_ll_rcc.c
  • LL_RCC_GetI2CClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetLPTIMClockFreq() : stm32wbxx_ll_rcc.c
  • LL_RCC_GetLPTIMClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetLPUARTClockFreq() : stm32wbxx_ll_rcc.c
  • LL_RCC_GetLPUARTClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetRFClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetRFWKPClockFreq() : stm32wbxx_ll_rcc.c
  • LL_RCC_GetRFWKPClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetRNGClockFreq() : stm32wbxx_ll_rcc.c
  • LL_RCC_GetRNGClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetRTCClockFreq() : stm32wbxx_ll_rcc.c
  • LL_RCC_GetRTCClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetSAIClockFreq() : stm32wbxx_ll_rcc.c
  • LL_RCC_GetSAIClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetSMPSClockFreq() : stm32wbxx_ll_rcc.c
  • LL_RCC_GetSMPSClockSelection() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetSMPSClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetSMPSPrescaler() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetSysClkSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetSystemClocksFreq() : stm32wbxx_ll_rcc.c
  • LL_RCC_GetUSARTClockFreq() : stm32wbxx_ll_rcc.c
  • LL_RCC_GetUSARTClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_GetUSBClockFreq() : stm32wbxx_ll_rcc.c
  • LL_RCC_GetUSBClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_Disable() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_DisableBypass() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_DisableDiv2() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_Enable() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_EnableBypass() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_EnableCSS() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_EnableDiv2() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_GetCapacitorTuning() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_GetCurrentControl() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_GetSenseAmplifier() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_IsClockControlLocked() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_IsEnabledDiv2() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_IsReady() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_SetCapacitorTuning() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_SetCurrentControl() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_SetSenseAmplifier() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSI48_Disable() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSI48_Enable() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSI48_GetCalibration() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSI48_IsReady() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSI_Disable() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSI_DisableAutoFromStop() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSI_DisableInStopMode() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSI_Enable() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSI_EnableAutoFromStop() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSI_EnableInStopMode() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSI_GetCalibration() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSI_GetCalibTrimming() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSI_IsEnabledInStopMode() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSI_IsReady() : stm32wbxx_ll_rcc.h
  • LL_RCC_HSI_SetCalibTrimming() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_BORRST() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_C2HPRE() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HPRE() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSECSS() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSERDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSI48RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSIRDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_IWDGRST() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LPWRRST() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSECSS() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSERDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSI1RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSI2RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_MSIRDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_OBLRST() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PINRST() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PLLRDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PLLSAI1RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PPRE1() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PPRE2() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_SFTRST() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_SHDHPRE() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsActiveFlag_WWDGRST() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsEnabledIT_HSERDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsEnabledIT_HSI48RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsEnabledIT_HSIRDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsEnabledIT_LSECSS() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsEnabledIT_LSERDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsEnabledIT_LSI1RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsEnabledIT_LSI2RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsEnabledIT_MSIRDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsEnabledIT_PLLRDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsEnabledIT_PLLSAI1RDY() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsEnabledRTC() : stm32wbxx_ll_rcc.h
  • LL_RCC_IsRFUnderReset() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSCO_Disable() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSCO_Enable() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSCO_GetSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSCO_SetSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSE_Disable() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSE_DisableBypass() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSE_DisableCSS() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSE_Enable() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSE_EnableBypass() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSE_EnableCSS() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSE_GetDriveCapability() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSE_IsCSSDetected() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSE_IsEnabled() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSE_IsReady() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSE_SetDriveCapability() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSI1_Disable() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSI1_Enable() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSI1_IsReady() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSI2_Disable() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSI2_Enable() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSI2_GetTrimming() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSI2_IsReady() : stm32wbxx_ll_rcc.h
  • LL_RCC_LSI2_SetTrimming() : stm32wbxx_ll_rcc.h
  • LL_RCC_MSI_Disable() : stm32wbxx_ll_rcc.h
  • LL_RCC_MSI_DisablePLLMode() : stm32wbxx_ll_rcc.h
  • LL_RCC_MSI_Enable() : stm32wbxx_ll_rcc.h
  • LL_RCC_MSI_EnablePLLMode() : stm32wbxx_ll_rcc.h
  • LL_RCC_MSI_GetCalibration() : stm32wbxx_ll_rcc.h
  • LL_RCC_MSI_GetCalibTrimming() : stm32wbxx_ll_rcc.h
  • LL_RCC_MSI_GetRange() : stm32wbxx_ll_rcc.h
  • LL_RCC_MSI_IsReady() : stm32wbxx_ll_rcc.h
  • LL_RCC_MSI_SetCalibTrimming() : stm32wbxx_ll_rcc.h
  • LL_RCC_MSI_SetRange() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_48M() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_ADC() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_SAI() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_SYS() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_Disable() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_DisableDomain_48M() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_DisableDomain_ADC() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_DisableDomain_SAI() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_DisableDomain_SYS() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_Enable() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_EnableDomain_48M() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_EnableDomain_ADC() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_EnableDomain_SAI() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_EnableDomain_SYS() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_GetDivider() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_GetMainSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_GetN() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_GetP() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_GetQ() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_GetR() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_IsReady() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLL_SetMainSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1_ConfigDomain_48M() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1_ConfigDomain_ADC() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1_ConfigDomain_SAI() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1_Disable() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1_DisableDomain_48M() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1_DisableDomain_ADC() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1_DisableDomain_SAI() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1_Enable() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1_EnableDomain_48M() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1_EnableDomain_ADC() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1_EnableDomain_SAI() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1_GetN() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1_GetP() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1_GetQ() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1_GetR() : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1_IsReady() : stm32wbxx_ll_rcc.h
  • LL_RCC_ReleaseBackupDomainReset() : stm32wbxx_ll_rcc.h
  • LL_RCC_SetADCClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_SetAHB4Prescaler() : stm32wbxx_ll_rcc.h
  • LL_RCC_SetAHBPrescaler() : stm32wbxx_ll_rcc.h
  • LL_RCC_SetAPB1Prescaler() : stm32wbxx_ll_rcc.h
  • LL_RCC_SetAPB2Prescaler() : stm32wbxx_ll_rcc.h
  • LL_RCC_SetCLK48ClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_SetClkAfterWakeFromStop() : stm32wbxx_ll_rcc.h
  • LL_RCC_SetI2CClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_SetLPTIMClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_SetLPUARTClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_SetRFWKPClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_SetRNGClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_SetRTCClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_SetSAIClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_SetSMPSClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_SetSMPSPrescaler() : stm32wbxx_ll_rcc.h
  • LL_RCC_SetSysClkSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_SetUSARTClockSource() : stm32wbxx_ll_rcc.h
  • LL_RCC_SetUSBClockSource() : stm32wbxx_ll_rcc.h
  • LL_RNG_ClearFlag_CEIS() : stm32wbxx_ll_rng.h
  • LL_RNG_ClearFlag_SEIS() : stm32wbxx_ll_rng.h
  • LL_RNG_DeInit() : stm32wbxx_ll_rng.c
  • LL_RNG_Disable() : stm32wbxx_ll_rng.h
  • LL_RNG_DisableClkErrorDetect() : stm32wbxx_ll_rng.h
  • LL_RNG_DisableIT() : stm32wbxx_ll_rng.h
  • LL_RNG_Enable() : stm32wbxx_ll_rng.h
  • LL_RNG_EnableClkErrorDetect() : stm32wbxx_ll_rng.h
  • LL_RNG_EnableIT() : stm32wbxx_ll_rng.h
  • LL_RNG_Init() : stm32wbxx_ll_rng.c
  • LL_RNG_IsActiveFlag_CECS() : stm32wbxx_ll_rng.h
  • LL_RNG_IsActiveFlag_CEIS() : stm32wbxx_ll_rng.h
  • LL_RNG_IsActiveFlag_DRDY() : stm32wbxx_ll_rng.h
  • LL_RNG_IsActiveFlag_SECS() : stm32wbxx_ll_rng.h
  • LL_RNG_IsActiveFlag_SEIS() : stm32wbxx_ll_rng.h
  • LL_RNG_IsEnabled() : stm32wbxx_ll_rng.h
  • LL_RNG_IsEnabledClkErrorDetect() : stm32wbxx_ll_rng.h
  • LL_RNG_IsEnabledIT() : stm32wbxx_ll_rng.h
  • LL_RNG_ReadRandData32() : stm32wbxx_ll_rng.h
  • LL_RNG_StructInit() : stm32wbxx_ll_rng.c
  • LL_RTC_ALMA_ConfigTime() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_Disable() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_DisableWeekday() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_Enable() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_EnableWeekday() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_GetDay() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_GetHour() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_GetMask() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_GetMinute() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_GetSecond() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_GetSubSecond() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_GetSubSecondMask() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_GetTime() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_GetTimeFormat() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_GetWeekDay() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_Init() : stm32wbxx_ll_rtc.c
  • LL_RTC_ALMA_SetDay() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_SetHour() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_SetMask() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_SetMinute() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_SetSecond() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_SetSubSecond() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_SetSubSecondMask() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_SetTimeFormat() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_SetWeekDay() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_StructInit() : stm32wbxx_ll_rtc.c
  • LL_RTC_ALMB_ConfigTime() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_Disable() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_DisableWeekday() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_Enable() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_EnableWeekday() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_GetDay() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_GetHour() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_GetMask() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_GetMinute() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_GetSecond() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_GetSubSecond() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_GetSubSecondMask() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_GetTime() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_GetTimeFormat() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_GetWeekDay() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_Init() : stm32wbxx_ll_rtc.c
  • LL_RTC_ALMB_SetDay() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_SetHour() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_SetMask() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_SetMinute() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_SetSecond() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_SetSubSecond() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_SetSubSecondMask() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_SetTimeFormat() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_SetWeekDay() : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_StructInit() : stm32wbxx_ll_rtc.c
  • LL_RTC_BAK_GetRegister() : stm32wbxx_ll_rtc.h
  • LL_RTC_BAK_SetRegister() : stm32wbxx_ll_rtc.h
  • LL_RTC_CAL_GetMinus() : stm32wbxx_ll_rtc.h
  • LL_RTC_CAL_GetOutputFreq() : stm32wbxx_ll_rtc.h
  • LL_RTC_CAL_GetPeriod() : stm32wbxx_ll_rtc.h
  • LL_RTC_CAL_IsPulseInserted() : stm32wbxx_ll_rtc.h
  • LL_RTC_CAL_SetMinus() : stm32wbxx_ll_rtc.h
  • LL_RTC_CAL_SetOutputFreq() : stm32wbxx_ll_rtc.h
  • LL_RTC_CAL_SetPeriod() : stm32wbxx_ll_rtc.h
  • LL_RTC_CAL_SetPulse() : stm32wbxx_ll_rtc.h
  • LL_RTC_ClearFlag_ALRA() : stm32wbxx_ll_rtc.h
  • LL_RTC_ClearFlag_ALRB() : stm32wbxx_ll_rtc.h
  • LL_RTC_ClearFlag_ITS() : stm32wbxx_ll_rtc.h
  • LL_RTC_ClearFlag_RS() : stm32wbxx_ll_rtc.h
  • LL_RTC_ClearFlag_TAMP1() : stm32wbxx_ll_rtc.h
  • LL_RTC_ClearFlag_TAMP2() : stm32wbxx_ll_rtc.h
  • LL_RTC_ClearFlag_TAMP3() : stm32wbxx_ll_rtc.h
  • LL_RTC_ClearFlag_TS() : stm32wbxx_ll_rtc.h
  • LL_RTC_ClearFlag_TSOV() : stm32wbxx_ll_rtc.h
  • LL_RTC_ClearFlag_WUT() : stm32wbxx_ll_rtc.h
  • LL_RTC_DATE_Config() : stm32wbxx_ll_rtc.h
  • LL_RTC_DATE_Get() : stm32wbxx_ll_rtc.h
  • LL_RTC_DATE_GetDay() : stm32wbxx_ll_rtc.h
  • LL_RTC_DATE_GetMonth() : stm32wbxx_ll_rtc.h
  • LL_RTC_DATE_GetWeekDay() : stm32wbxx_ll_rtc.h
  • LL_RTC_DATE_GetYear() : stm32wbxx_ll_rtc.h
  • LL_RTC_DATE_Init() : stm32wbxx_ll_rtc.c
  • LL_RTC_DATE_SetDay() : stm32wbxx_ll_rtc.h
  • LL_RTC_DATE_SetMonth() : stm32wbxx_ll_rtc.h
  • LL_RTC_DATE_SetWeekDay() : stm32wbxx_ll_rtc.h
  • LL_RTC_DATE_SetYear() : stm32wbxx_ll_rtc.h
  • LL_RTC_DATE_StructInit() : stm32wbxx_ll_rtc.c
  • LL_RTC_DeInit() : stm32wbxx_ll_rtc.c
  • LL_RTC_DisableInitMode() : stm32wbxx_ll_rtc.h
  • LL_RTC_DisableIT_ALRA() : stm32wbxx_ll_rtc.h
  • LL_RTC_DisableIT_ALRB() : stm32wbxx_ll_rtc.h
  • LL_RTC_DisableIT_TAMP() : stm32wbxx_ll_rtc.h
  • LL_RTC_DisableIT_TAMP1() : stm32wbxx_ll_rtc.h
  • LL_RTC_DisableIT_TAMP2() : stm32wbxx_ll_rtc.h
  • LL_RTC_DisableIT_TAMP3() : stm32wbxx_ll_rtc.h
  • LL_RTC_DisableIT_TS() : stm32wbxx_ll_rtc.h
  • LL_RTC_DisableIT_WUT() : stm32wbxx_ll_rtc.h
  • LL_RTC_DisableOutRemap() : stm32wbxx_ll_rtc.h
  • LL_RTC_DisableRefClock() : stm32wbxx_ll_rtc.h
  • LL_RTC_DisableShadowRegBypass() : stm32wbxx_ll_rtc.h
  • LL_RTC_DisableWriteProtection() : stm32wbxx_ll_rtc.h
  • LL_RTC_EnableInitMode() : stm32wbxx_ll_rtc.h
  • LL_RTC_EnableIT_ALRA() : stm32wbxx_ll_rtc.h
  • LL_RTC_EnableIT_ALRB() : stm32wbxx_ll_rtc.h
  • LL_RTC_EnableIT_TAMP() : stm32wbxx_ll_rtc.h
  • LL_RTC_EnableIT_TAMP1() : stm32wbxx_ll_rtc.h
  • LL_RTC_EnableIT_TAMP2() : stm32wbxx_ll_rtc.h
  • LL_RTC_EnableIT_TAMP3() : stm32wbxx_ll_rtc.h
  • LL_RTC_EnableIT_TS() : stm32wbxx_ll_rtc.h
  • LL_RTC_EnableIT_WUT() : stm32wbxx_ll_rtc.h
  • LL_RTC_EnableOutRemap() : stm32wbxx_ll_rtc.h
  • LL_RTC_EnableRefClock() : stm32wbxx_ll_rtc.h
  • LL_RTC_EnableShadowRegBypass() : stm32wbxx_ll_rtc.h
  • LL_RTC_EnableWriteProtection() : stm32wbxx_ll_rtc.h
  • LL_RTC_EnterInitMode() : stm32wbxx_ll_rtc.c
  • LL_RTC_ExitInitMode() : stm32wbxx_ll_rtc.c
  • LL_RTC_GetAlarmOutEvent() : stm32wbxx_ll_rtc.h
  • LL_RTC_GetAlarmOutputType() : stm32wbxx_ll_rtc.h
  • LL_RTC_GetAsynchPrescaler() : stm32wbxx_ll_rtc.h
  • LL_RTC_GetHourFormat() : stm32wbxx_ll_rtc.h
  • LL_RTC_GetOutputPolarity() : stm32wbxx_ll_rtc.h
  • LL_RTC_GetSynchPrescaler() : stm32wbxx_ll_rtc.h
  • LL_RTC_Init() : stm32wbxx_ll_rtc.c
  • LL_RTC_IsActiveFlag_ALRA() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRAW() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRB() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ALRBW() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsActiveFlag_INIT() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsActiveFlag_INITS() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsActiveFlag_ITS() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsActiveFlag_RECALP() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsActiveFlag_RS() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsActiveFlag_SHP() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP1() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP2() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TAMP3() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TS() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsActiveFlag_TSOV() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsActiveFlag_WUT() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsActiveFlag_WUTW() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ALRA() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsEnabledIT_ALRB() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TAMP() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TAMP1() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TAMP2() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TAMP3() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsEnabledIT_TS() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsEnabledIT_WUT() : stm32wbxx_ll_rtc.h
  • LL_RTC_IsShadowRegBypassEnabled() : stm32wbxx_ll_rtc.h
  • LL_RTC_SetAlarmOutEvent() : stm32wbxx_ll_rtc.h
  • LL_RTC_SetAlarmOutputType() : stm32wbxx_ll_rtc.h
  • LL_RTC_SetAsynchPrescaler() : stm32wbxx_ll_rtc.h
  • LL_RTC_SetHourFormat() : stm32wbxx_ll_rtc.h
  • LL_RTC_SetOutputPolarity() : stm32wbxx_ll_rtc.h
  • LL_RTC_SetSynchPrescaler() : stm32wbxx_ll_rtc.h
  • LL_RTC_StructInit() : stm32wbxx_ll_rtc.c
  • LL_RTC_TAMPER_Disable() : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_DisableActiveLevel() : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_DisableEraseBKP() : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_DisableMask() : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_DisablePullUp() : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_Enable() : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_EnableActiveLevel() : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_EnableEraseBKP() : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_EnableMask() : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_EnablePullUp() : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_GetFilterCount() : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_GetPrecharge() : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_GetSamplingFreq() : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_SetFilterCount() : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_SetPrecharge() : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_SetSamplingFreq() : stm32wbxx_ll_rtc.h
  • LL_RTC_TIME_Config() : stm32wbxx_ll_rtc.h
  • LL_RTC_TIME_DecHour() : stm32wbxx_ll_rtc.h
  • LL_RTC_TIME_DisableDayLightStore() : stm32wbxx_ll_rtc.h
  • LL_RTC_TIME_EnableDayLightStore() : stm32wbxx_ll_rtc.h
  • LL_RTC_TIME_Get() : stm32wbxx_ll_rtc.h
  • LL_RTC_TIME_GetFormat() : stm32wbxx_ll_rtc.h
  • LL_RTC_TIME_GetHour() : stm32wbxx_ll_rtc.h
  • LL_RTC_TIME_GetMinute() : stm32wbxx_ll_rtc.h
  • LL_RTC_TIME_GetSecond() : stm32wbxx_ll_rtc.h
  • LL_RTC_TIME_GetSubSecond() : stm32wbxx_ll_rtc.h
  • LL_RTC_TIME_IncHour() : stm32wbxx_ll_rtc.h
  • LL_RTC_TIME_Init() : stm32wbxx_ll_rtc.c
  • LL_RTC_TIME_IsDayLightStoreEnabled() : stm32wbxx_ll_rtc.h
  • LL_RTC_TIME_SetFormat() : stm32wbxx_ll_rtc.h
  • LL_RTC_TIME_SetHour() : stm32wbxx_ll_rtc.h
  • LL_RTC_TIME_SetMinute() : stm32wbxx_ll_rtc.h
  • LL_RTC_TIME_SetSecond() : stm32wbxx_ll_rtc.h
  • LL_RTC_TIME_StructInit() : stm32wbxx_ll_rtc.c
  • LL_RTC_TIME_Synchronize() : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_Disable() : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_DisableInternalEvent() : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_DisableOnTamper() : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_Enable() : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_EnableInternalEvent() : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_EnableOnTamper() : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_GetActiveEdge() : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_GetDate() : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_GetDay() : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_GetHour() : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_GetMinute() : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_GetMonth() : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_GetSecond() : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_GetSubSecond() : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_GetTime() : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_GetTimeFormat() : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_GetWeekDay() : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_SetActiveEdge() : stm32wbxx_ll_rtc.h
  • LL_RTC_WaitForSynchro() : stm32wbxx_ll_rtc.c
  • LL_RTC_WAKEUP_Disable() : stm32wbxx_ll_rtc.h
  • LL_RTC_WAKEUP_Enable() : stm32wbxx_ll_rtc.h
  • LL_RTC_WAKEUP_GetAutoReload() : stm32wbxx_ll_rtc.h
  • LL_RTC_WAKEUP_GetClock() : stm32wbxx_ll_rtc.h
  • LL_RTC_WAKEUP_IsEnabled() : stm32wbxx_ll_rtc.h
  • LL_RTC_WAKEUP_SetAutoReload() : stm32wbxx_ll_rtc.h
  • LL_RTC_WAKEUP_SetClock() : stm32wbxx_ll_rtc.h
  • LL_SetSystemCoreClock() : stm32wbxx_ll_utils.c
  • LL_SPI_ClearFlag_CRCERR() : stm32wbxx_ll_spi.h
  • LL_SPI_ClearFlag_FRE() : stm32wbxx_ll_spi.h
  • LL_SPI_ClearFlag_MODF() : stm32wbxx_ll_spi.h
  • LL_SPI_ClearFlag_OVR() : stm32wbxx_ll_spi.h
  • LL_SPI_DeInit() : stm32wbxx_ll_spi.c
  • LL_SPI_Disable() : stm32wbxx_ll_spi.h
  • LL_SPI_DisableCRC() : stm32wbxx_ll_spi.h
  • LL_SPI_DisableDMAReq_RX() : stm32wbxx_ll_spi.h
  • LL_SPI_DisableDMAReq_TX() : stm32wbxx_ll_spi.h
  • LL_SPI_DisableIT_ERR() : stm32wbxx_ll_spi.h
  • LL_SPI_DisableIT_RXNE() : stm32wbxx_ll_spi.h
  • LL_SPI_DisableIT_TXE() : stm32wbxx_ll_spi.h
  • LL_SPI_DisableNSSPulseMgt() : stm32wbxx_ll_spi.h
  • LL_SPI_DMA_GetRegAddr() : stm32wbxx_ll_spi.h
  • LL_SPI_Enable() : stm32wbxx_ll_spi.h
  • LL_SPI_EnableCRC() : stm32wbxx_ll_spi.h
  • LL_SPI_EnableDMAReq_RX() : stm32wbxx_ll_spi.h
  • LL_SPI_EnableDMAReq_TX() : stm32wbxx_ll_spi.h
  • LL_SPI_EnableIT_ERR() : stm32wbxx_ll_spi.h
  • LL_SPI_EnableIT_RXNE() : stm32wbxx_ll_spi.h
  • LL_SPI_EnableIT_TXE() : stm32wbxx_ll_spi.h
  • LL_SPI_EnableNSSPulseMgt() : stm32wbxx_ll_spi.h
  • LL_SPI_GetBaudRatePrescaler() : stm32wbxx_ll_spi.h
  • LL_SPI_GetClockPhase() : stm32wbxx_ll_spi.h
  • LL_SPI_GetClockPolarity() : stm32wbxx_ll_spi.h
  • LL_SPI_GetCRCPolynomial() : stm32wbxx_ll_spi.h
  • LL_SPI_GetCRCWidth() : stm32wbxx_ll_spi.h
  • LL_SPI_GetDataWidth() : stm32wbxx_ll_spi.h
  • LL_SPI_GetDMAParity_RX() : stm32wbxx_ll_spi.h
  • LL_SPI_GetDMAParity_TX() : stm32wbxx_ll_spi.h
  • LL_SPI_GetMode() : stm32wbxx_ll_spi.h
  • LL_SPI_GetNSSMode() : stm32wbxx_ll_spi.h
  • LL_SPI_GetRxCRC() : stm32wbxx_ll_spi.h
  • LL_SPI_GetRxFIFOLevel() : stm32wbxx_ll_spi.h
  • LL_SPI_GetRxFIFOThreshold() : stm32wbxx_ll_spi.h
  • LL_SPI_GetStandard() : stm32wbxx_ll_spi.h
  • LL_SPI_GetTransferBitOrder() : stm32wbxx_ll_spi.h
  • LL_SPI_GetTransferDirection() : stm32wbxx_ll_spi.h
  • LL_SPI_GetTxCRC() : stm32wbxx_ll_spi.h
  • LL_SPI_GetTxFIFOLevel() : stm32wbxx_ll_spi.h
  • LL_SPI_Init() : stm32wbxx_ll_spi.c
  • LL_SPI_IsActiveFlag_BSY() : stm32wbxx_ll_spi.h
  • LL_SPI_IsActiveFlag_CRCERR() : stm32wbxx_ll_spi.h
  • LL_SPI_IsActiveFlag_FRE() : stm32wbxx_ll_spi.h
  • LL_SPI_IsActiveFlag_MODF() : stm32wbxx_ll_spi.h
  • LL_SPI_IsActiveFlag_OVR() : stm32wbxx_ll_spi.h
  • LL_SPI_IsActiveFlag_RXNE() : stm32wbxx_ll_spi.h
  • LL_SPI_IsActiveFlag_TXE() : stm32wbxx_ll_spi.h
  • LL_SPI_IsEnabled() : stm32wbxx_ll_spi.h
  • LL_SPI_IsEnabledCRC() : stm32wbxx_ll_spi.h
  • LL_SPI_IsEnabledDMAReq_RX() : stm32wbxx_ll_spi.h
  • LL_SPI_IsEnabledDMAReq_TX() : stm32wbxx_ll_spi.h
  • LL_SPI_IsEnabledIT_ERR() : stm32wbxx_ll_spi.h
  • LL_SPI_IsEnabledIT_RXNE() : stm32wbxx_ll_spi.h
  • LL_SPI_IsEnabledIT_TXE() : stm32wbxx_ll_spi.h
  • LL_SPI_IsEnabledNSSPulse() : stm32wbxx_ll_spi.h
  • LL_SPI_ReceiveData16() : stm32wbxx_ll_spi.h
  • LL_SPI_ReceiveData8() : stm32wbxx_ll_spi.h
  • LL_SPI_SetBaudRatePrescaler() : stm32wbxx_ll_spi.h
  • LL_SPI_SetClockPhase() : stm32wbxx_ll_spi.h
  • LL_SPI_SetClockPolarity() : stm32wbxx_ll_spi.h
  • LL_SPI_SetCRCNext() : stm32wbxx_ll_spi.h
  • LL_SPI_SetCRCPolynomial() : stm32wbxx_ll_spi.h
  • LL_SPI_SetCRCWidth() : stm32wbxx_ll_spi.h
  • LL_SPI_SetDataWidth() : stm32wbxx_ll_spi.h
  • LL_SPI_SetDMAParity_RX() : stm32wbxx_ll_spi.h
  • LL_SPI_SetDMAParity_TX() : stm32wbxx_ll_spi.h
  • LL_SPI_SetMode() : stm32wbxx_ll_spi.h
  • LL_SPI_SetNSSMode() : stm32wbxx_ll_spi.h
  • LL_SPI_SetRxFIFOThreshold() : stm32wbxx_ll_spi.h
  • LL_SPI_SetStandard() : stm32wbxx_ll_spi.h
  • LL_SPI_SetTransferBitOrder() : stm32wbxx_ll_spi.h
  • LL_SPI_SetTransferDirection() : stm32wbxx_ll_spi.h
  • LL_SPI_StructInit() : stm32wbxx_ll_spi.c
  • LL_SPI_TransmitData16() : stm32wbxx_ll_spi.h
  • LL_SPI_TransmitData8() : stm32wbxx_ll_spi.h
  • LL_SYSCFG_ClearFlag_SP() : stm32wbxx_ll_system.h
  • LL_SYSCFG_DisableAnalogBooster() : stm32wbxx_ll_system.h
  • LL_SYSCFG_DisableAnalogGpioSwitch() : stm32wbxx_ll_system.h
  • LL_SYSCFG_DisableFastModePlus() : stm32wbxx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_DZC() : stm32wbxx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_IDC() : stm32wbxx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_IOC() : stm32wbxx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_IXC() : stm32wbxx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_OFC() : stm32wbxx_ll_system.h
  • LL_SYSCFG_DisableIT_FPU_UFC() : stm32wbxx_ll_system.h
  • LL_SYSCFG_DisableSecurityAccess() : stm32wbxx_ll_system.h
  • LL_SYSCFG_DisableSRAMFetch() : stm32wbxx_ll_system.h
  • LL_SYSCFG_EnableAnalogBooster() : stm32wbxx_ll_system.h
  • LL_SYSCFG_EnableAnalogGpioSwitch() : stm32wbxx_ll_system.h
  • LL_SYSCFG_EnableFastModePlus() : stm32wbxx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_DZC() : stm32wbxx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_IDC() : stm32wbxx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_IOC() : stm32wbxx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_IXC() : stm32wbxx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_OFC() : stm32wbxx_ll_system.h
  • LL_SYSCFG_EnableIT_FPU_UFC() : stm32wbxx_ll_system.h
  • LL_SYSCFG_EnableSecurityAccess() : stm32wbxx_ll_system.h
  • LL_SYSCFG_EnableSRAM2Erase() : stm32wbxx_ll_system.h
  • LL_SYSCFG_EnableSRAM2PageWRP_0_31() : stm32wbxx_ll_system.h
  • LL_SYSCFG_EnableSRAM2PageWRP_32_63() : stm32wbxx_ll_system.h
  • LL_SYSCFG_GetEXTISource() : stm32wbxx_ll_system.h
  • LL_SYSCFG_GetRemapMemory() : stm32wbxx_ll_system.h
  • LL_SYSCFG_GetTIMBreakInputs() : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP1_DisableIT() : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP1_EnableIT() : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP1_IsEnabledIT() : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP2_DisableIT() : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP2_EnableIT() : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP2_IsEnabledIT() : stm32wbxx_ll_system.h
  • LL_SYSCFG_IsActiveFlag_SP() : stm32wbxx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_DZC() : stm32wbxx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_IDC() : stm32wbxx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_IOC() : stm32wbxx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_IXC() : stm32wbxx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_OFC() : stm32wbxx_ll_system.h
  • LL_SYSCFG_IsEnabledIT_FPU_UFC() : stm32wbxx_ll_system.h
  • LL_SYSCFG_IsEnabledSecurityAccess() : stm32wbxx_ll_system.h
  • LL_SYSCFG_IsEnabledSRAMFetch() : stm32wbxx_ll_system.h
  • LL_SYSCFG_IsSRAM2EraseOngoing() : stm32wbxx_ll_system.h
  • LL_SYSCFG_LockSRAM2WRP() : stm32wbxx_ll_system.h
  • LL_SYSCFG_SetEXTISource() : stm32wbxx_ll_system.h
  • LL_SYSCFG_SetRemapMemory() : stm32wbxx_ll_system.h
  • LL_SYSCFG_SetTIMBreakInputs() : stm32wbxx_ll_system.h
  • LL_SYSCFG_UnlockSRAM2WRP() : stm32wbxx_ll_system.h
  • LL_SYSTICK_DisableIT() : stm32wbxx_ll_cortex.h
  • LL_SYSTICK_EnableIT() : stm32wbxx_ll_cortex.h
  • LL_SYSTICK_GetClkSource() : stm32wbxx_ll_cortex.h
  • LL_SYSTICK_IsActiveCounterFlag() : stm32wbxx_ll_cortex.h
  • LL_SYSTICK_IsEnabledIT() : stm32wbxx_ll_cortex.h
  • LL_SYSTICK_SetClkSource() : stm32wbxx_ll_cortex.h
  • LL_TIM_BDTR_Init() : stm32wbxx_ll_tim.c
  • LL_TIM_BDTR_StructInit() : stm32wbxx_ll_tim.c
  • LL_TIM_CC_DisableChannel() : stm32wbxx_ll_tim.h
  • LL_TIM_CC_DisablePreload() : stm32wbxx_ll_tim.h
  • LL_TIM_CC_EnableChannel() : stm32wbxx_ll_tim.h
  • LL_TIM_CC_EnablePreload() : stm32wbxx_ll_tim.h
  • LL_TIM_CC_GetDMAReqTrigger() : stm32wbxx_ll_tim.h
  • LL_TIM_CC_IsEnabledChannel() : stm32wbxx_ll_tim.h
  • LL_TIM_CC_SetDMAReqTrigger() : stm32wbxx_ll_tim.h
  • LL_TIM_CC_SetLockLevel() : stm32wbxx_ll_tim.h
  • LL_TIM_CC_SetUpdate() : stm32wbxx_ll_tim.h
  • LL_TIM_ClearFlag_BRK() : stm32wbxx_ll_tim.h
  • LL_TIM_ClearFlag_BRK2() : stm32wbxx_ll_tim.h
  • LL_TIM_ClearFlag_CC1() : stm32wbxx_ll_tim.h
  • LL_TIM_ClearFlag_CC1OVR() : stm32wbxx_ll_tim.h
  • LL_TIM_ClearFlag_CC2() : stm32wbxx_ll_tim.h
  • LL_TIM_ClearFlag_CC2OVR() : stm32wbxx_ll_tim.h
  • LL_TIM_ClearFlag_CC3() : stm32wbxx_ll_tim.h
  • LL_TIM_ClearFlag_CC3OVR() : stm32wbxx_ll_tim.h
  • LL_TIM_ClearFlag_CC4() : stm32wbxx_ll_tim.h
  • LL_TIM_ClearFlag_CC4OVR() : stm32wbxx_ll_tim.h
  • LL_TIM_ClearFlag_CC5() : stm32wbxx_ll_tim.h
  • LL_TIM_ClearFlag_CC6() : stm32wbxx_ll_tim.h
  • LL_TIM_ClearFlag_COM() : stm32wbxx_ll_tim.h
  • LL_TIM_ClearFlag_SYSBRK() : stm32wbxx_ll_tim.h
  • LL_TIM_ClearFlag_TRIG() : stm32wbxx_ll_tim.h
  • LL_TIM_ClearFlag_UPDATE() : stm32wbxx_ll_tim.h
  • LL_TIM_ConfigBRK() : stm32wbxx_ll_tim.h
  • LL_TIM_ConfigBRK2() : stm32wbxx_ll_tim.h
  • LL_TIM_ConfigDMABurst() : stm32wbxx_ll_tim.h
  • LL_TIM_ConfigETR() : stm32wbxx_ll_tim.h
  • LL_TIM_DeInit() : stm32wbxx_ll_tim.c
  • LL_TIM_DisableAllOutputs() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableARRPreload() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableAutomaticOutput() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableBreakInputSource() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableBRK() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableBRK2() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableCounter() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC1() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC2() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC3() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC4() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableDMAReq_COM() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableDMAReq_TRIG() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableDMAReq_UPDATE() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableExternalClock() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableIT_BRK() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableIT_CC1() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableIT_CC2() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableIT_CC3() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableIT_CC4() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableIT_COM() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableIT_TRIG() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableIT_UPDATE() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableMasterSlaveMode() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableUIFRemap() : stm32wbxx_ll_tim.h
  • LL_TIM_DisableUpdateEvent() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableAllOutputs() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableARRPreload() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableAutomaticOutput() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableBreakInputSource() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableBRK() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableBRK2() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableCounter() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC1() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC2() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC3() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC4() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableDMAReq_COM() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableDMAReq_TRIG() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableDMAReq_UPDATE() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableExternalClock() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableIT_BRK() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableIT_CC1() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableIT_CC2() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableIT_CC3() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableIT_CC4() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableIT_COM() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableIT_TRIG() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableIT_UPDATE() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableMasterSlaveMode() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableUIFRemap() : stm32wbxx_ll_tim.h
  • LL_TIM_EnableUpdateEvent() : stm32wbxx_ll_tim.h
  • LL_TIM_ENCODER_Init() : stm32wbxx_ll_tim.c
  • LL_TIM_ENCODER_StructInit() : stm32wbxx_ll_tim.c
  • LL_TIM_GenerateEvent_BRK() : stm32wbxx_ll_tim.h
  • LL_TIM_GenerateEvent_BRK2() : stm32wbxx_ll_tim.h
  • LL_TIM_GenerateEvent_CC1() : stm32wbxx_ll_tim.h
  • LL_TIM_GenerateEvent_CC2() : stm32wbxx_ll_tim.h
  • LL_TIM_GenerateEvent_CC3() : stm32wbxx_ll_tim.h
  • LL_TIM_GenerateEvent_CC4() : stm32wbxx_ll_tim.h
  • LL_TIM_GenerateEvent_COM() : stm32wbxx_ll_tim.h
  • LL_TIM_GenerateEvent_TRIG() : stm32wbxx_ll_tim.h
  • LL_TIM_GenerateEvent_UPDATE() : stm32wbxx_ll_tim.h
  • LL_TIM_GetAutoReload() : stm32wbxx_ll_tim.h
  • LL_TIM_GetClockDivision() : stm32wbxx_ll_tim.h
  • LL_TIM_GetCounter() : stm32wbxx_ll_tim.h
  • LL_TIM_GetCounterMode() : stm32wbxx_ll_tim.h
  • LL_TIM_GetDirection() : stm32wbxx_ll_tim.h
  • LL_TIM_GetOnePulseMode() : stm32wbxx_ll_tim.h
  • LL_TIM_GetPrescaler() : stm32wbxx_ll_tim.h
  • LL_TIM_GetRepetitionCounter() : stm32wbxx_ll_tim.h
  • LL_TIM_GetUpdateSource() : stm32wbxx_ll_tim.h
  • LL_TIM_HALLSENSOR_Init() : stm32wbxx_ll_tim.c
  • LL_TIM_HALLSENSOR_StructInit() : stm32wbxx_ll_tim.c
  • LL_TIM_IC_Config() : stm32wbxx_ll_tim.h
  • LL_TIM_IC_DisableXORCombination() : stm32wbxx_ll_tim.h
  • LL_TIM_IC_EnableXORCombination() : stm32wbxx_ll_tim.h
  • LL_TIM_IC_GetActiveInput() : stm32wbxx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH1() : stm32wbxx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH2() : stm32wbxx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH3() : stm32wbxx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH4() : stm32wbxx_ll_tim.h
  • LL_TIM_IC_GetFilter() : stm32wbxx_ll_tim.h
  • LL_TIM_IC_GetPolarity() : stm32wbxx_ll_tim.h
  • LL_TIM_IC_GetPrescaler() : stm32wbxx_ll_tim.h
  • LL_TIM_IC_Init() : stm32wbxx_ll_tim.c
  • LL_TIM_IC_IsEnabledXORCombination() : stm32wbxx_ll_tim.h
  • LL_TIM_IC_SetActiveInput() : stm32wbxx_ll_tim.h
  • LL_TIM_IC_SetFilter() : stm32wbxx_ll_tim.h
  • LL_TIM_IC_SetPolarity() : stm32wbxx_ll_tim.h
  • LL_TIM_IC_SetPrescaler() : stm32wbxx_ll_tim.h
  • LL_TIM_IC_StructInit() : stm32wbxx_ll_tim.c
  • LL_TIM_Init() : stm32wbxx_ll_tim.c
  • LL_TIM_IsActiveFlag_BRK() : stm32wbxx_ll_tim.h
  • LL_TIM_IsActiveFlag_BRK2() : stm32wbxx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC1() : stm32wbxx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC1OVR() : stm32wbxx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC2() : stm32wbxx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC2OVR() : stm32wbxx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC3() : stm32wbxx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC3OVR() : stm32wbxx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC4() : stm32wbxx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC4OVR() : stm32wbxx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC5() : stm32wbxx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC6() : stm32wbxx_ll_tim.h
  • LL_TIM_IsActiveFlag_COM() : stm32wbxx_ll_tim.h
  • LL_TIM_IsActiveFlag_SYSBRK() : stm32wbxx_ll_tim.h
  • LL_TIM_IsActiveFlag_TRIG() : stm32wbxx_ll_tim.h
  • LL_TIM_IsActiveFlag_UPDATE() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledAllOutputs() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledARRPreload() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledAutomaticOutput() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledCounter() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC1() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC2() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC3() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC4() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_COM() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_TRIG() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_UPDATE() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledExternalClock() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledIT_BRK() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC1() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC2() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC3() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC4() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledIT_COM() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledIT_TRIG() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledIT_UPDATE() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledMasterSlaveMode() : stm32wbxx_ll_tim.h
  • LL_TIM_IsEnabledUpdateEvent() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_ConfigOutput() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_DisableClear() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_DisableFast() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_DisablePreload() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_EnableClear() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_EnableFast() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_EnablePreload() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_GetCompareCH1() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_GetCompareCH2() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_GetCompareCH3() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_GetCompareCH4() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_GetCompareCH5() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_GetCompareCH6() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_GetIdleState() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_GetMode() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_GetPolarity() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_Init() : stm32wbxx_ll_tim.c
  • LL_TIM_OC_IsEnabledClear() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_IsEnabledFast() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_IsEnabledPreload() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_SetCompareCH1() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_SetCompareCH2() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_SetCompareCH3() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_SetCompareCH4() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_SetCompareCH5() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_SetCompareCH6() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_SetDeadTime() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_SetIdleState() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_SetMode() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_SetPolarity() : stm32wbxx_ll_tim.h
  • LL_TIM_OC_StructInit() : stm32wbxx_ll_tim.c
  • LL_TIM_SetAutoReload() : stm32wbxx_ll_tim.h
  • LL_TIM_SetBreakInputSourcePolarity() : stm32wbxx_ll_tim.h
  • LL_TIM_SetCH5CombinedChannels() : stm32wbxx_ll_tim.h
  • LL_TIM_SetClockDivision() : stm32wbxx_ll_tim.h
  • LL_TIM_SetClockSource() : stm32wbxx_ll_tim.h
  • LL_TIM_SetCounter() : stm32wbxx_ll_tim.h
  • LL_TIM_SetCounterMode() : stm32wbxx_ll_tim.h
  • LL_TIM_SetEncoderMode() : stm32wbxx_ll_tim.h
  • LL_TIM_SetETRSource() : stm32wbxx_ll_tim.h
  • LL_TIM_SetOCRefClearInputSource() : stm32wbxx_ll_tim.h
  • LL_TIM_SetOffStates() : stm32wbxx_ll_tim.h
  • LL_TIM_SetOnePulseMode() : stm32wbxx_ll_tim.h
  • LL_TIM_SetPrescaler() : stm32wbxx_ll_tim.h
  • LL_TIM_SetRemap() : stm32wbxx_ll_tim.h
  • LL_TIM_SetRepetitionCounter() : stm32wbxx_ll_tim.h
  • LL_TIM_SetSlaveMode() : stm32wbxx_ll_tim.h
  • LL_TIM_SetTriggerInput() : stm32wbxx_ll_tim.h
  • LL_TIM_SetTriggerOutput() : stm32wbxx_ll_tim.h
  • LL_TIM_SetTriggerOutput2() : stm32wbxx_ll_tim.h
  • LL_TIM_SetUpdateSource() : stm32wbxx_ll_tim.h
  • LL_TIM_StructInit() : stm32wbxx_ll_tim.c
  • LL_USART_ClearFlag_CM() : stm32wbxx_ll_usart.h
  • LL_USART_ClearFlag_EOB() : stm32wbxx_ll_usart.h
  • LL_USART_ClearFlag_FE() : stm32wbxx_ll_usart.h
  • LL_USART_ClearFlag_IDLE() : stm32wbxx_ll_usart.h
  • LL_USART_ClearFlag_LBD() : stm32wbxx_ll_usart.h
  • LL_USART_ClearFlag_nCTS() : stm32wbxx_ll_usart.h
  • LL_USART_ClearFlag_NE() : stm32wbxx_ll_usart.h
  • LL_USART_ClearFlag_ORE() : stm32wbxx_ll_usart.h
  • LL_USART_ClearFlag_PE() : stm32wbxx_ll_usart.h
  • LL_USART_ClearFlag_RTO() : stm32wbxx_ll_usart.h
  • LL_USART_ClearFlag_TC() : stm32wbxx_ll_usart.h
  • LL_USART_ClearFlag_TCBGT() : stm32wbxx_ll_usart.h
  • LL_USART_ClearFlag_TXFE() : stm32wbxx_ll_usart.h
  • LL_USART_ClearFlag_UDR() : stm32wbxx_ll_usart.h
  • LL_USART_ClearFlag_WKUP() : stm32wbxx_ll_usart.h
  • LL_USART_ClockInit() : stm32wbxx_ll_usart.c
  • LL_USART_ClockStructInit() : stm32wbxx_ll_usart.c
  • LL_USART_ConfigAsyncMode() : stm32wbxx_ll_usart.h
  • LL_USART_ConfigCharacter() : stm32wbxx_ll_usart.h
  • LL_USART_ConfigClock() : stm32wbxx_ll_usart.h
  • LL_USART_ConfigFIFOsThreshold() : stm32wbxx_ll_usart.h
  • LL_USART_ConfigHalfDuplexMode() : stm32wbxx_ll_usart.h
  • LL_USART_ConfigIrdaMode() : stm32wbxx_ll_usart.h
  • LL_USART_ConfigLINMode() : stm32wbxx_ll_usart.h
  • LL_USART_ConfigMultiProcessMode() : stm32wbxx_ll_usart.h
  • LL_USART_ConfigNodeAddress() : stm32wbxx_ll_usart.h
  • LL_USART_ConfigSmartcardMode() : stm32wbxx_ll_usart.h
  • LL_USART_ConfigSyncMode() : stm32wbxx_ll_usart.h
  • LL_USART_DeInit() : stm32wbxx_ll_usart.c
  • LL_USART_Disable() : stm32wbxx_ll_usart.h
  • LL_USART_DisableAutoBaudRate() : stm32wbxx_ll_usart.h
  • LL_USART_DisableCTSHWFlowCtrl() : stm32wbxx_ll_usart.h
  • LL_USART_DisableDEMode() : stm32wbxx_ll_usart.h
  • LL_USART_DisableDirectionRx() : stm32wbxx_ll_usart.h
  • LL_USART_DisableDirectionTx() : stm32wbxx_ll_usart.h
  • LL_USART_DisableDMADeactOnRxErr() : stm32wbxx_ll_usart.h
  • LL_USART_DisableDMAReq_RX() : stm32wbxx_ll_usart.h
  • LL_USART_DisableDMAReq_TX() : stm32wbxx_ll_usart.h
  • LL_USART_DisableFIFO() : stm32wbxx_ll_usart.h
  • LL_USART_DisableHalfDuplex() : stm32wbxx_ll_usart.h
  • LL_USART_DisableInStopMode() : stm32wbxx_ll_usart.h
  • LL_USART_DisableIrda() : stm32wbxx_ll_usart.h
  • LL_USART_DisableIT_CM() : stm32wbxx_ll_usart.h
  • LL_USART_DisableIT_CTS() : stm32wbxx_ll_usart.h
  • LL_USART_DisableIT_EOB() : stm32wbxx_ll_usart.h
  • LL_USART_DisableIT_ERROR() : stm32wbxx_ll_usart.h
  • LL_USART_DisableIT_IDLE() : stm32wbxx_ll_usart.h
  • LL_USART_DisableIT_LBD() : stm32wbxx_ll_usart.h
  • LL_USART_DisableIT_PE() : stm32wbxx_ll_usart.h
  • LL_USART_DisableIT_RTO() : stm32wbxx_ll_usart.h
  • LL_USART_DisableIT_RXFF() : stm32wbxx_ll_usart.h
  • LL_USART_DisableIT_RXFT() : stm32wbxx_ll_usart.h
  • LL_USART_DisableIT_RXNE_RXFNE() : stm32wbxx_ll_usart.h
  • LL_USART_DisableIT_TC() : stm32wbxx_ll_usart.h
  • LL_USART_DisableIT_TCBGT() : stm32wbxx_ll_usart.h
  • LL_USART_DisableIT_TXE_TXFNF() : stm32wbxx_ll_usart.h
  • LL_USART_DisableIT_TXFE() : stm32wbxx_ll_usart.h
  • LL_USART_DisableIT_TXFT() : stm32wbxx_ll_usart.h
  • LL_USART_DisableIT_WKUP() : stm32wbxx_ll_usart.h
  • LL_USART_DisableLIN() : stm32wbxx_ll_usart.h
  • LL_USART_DisableMuteMode() : stm32wbxx_ll_usart.h
  • LL_USART_DisableOneBitSamp() : stm32wbxx_ll_usart.h
  • LL_USART_DisableOverrunDetect() : stm32wbxx_ll_usart.h
  • LL_USART_DisableRTSHWFlowCtrl() : stm32wbxx_ll_usart.h
  • LL_USART_DisableRxTimeout() : stm32wbxx_ll_usart.h
  • LL_USART_DisableSCLKOutput() : stm32wbxx_ll_usart.h
  • LL_USART_DisableSmartcard() : stm32wbxx_ll_usart.h
  • LL_USART_DisableSmartcardNACK() : stm32wbxx_ll_usart.h
  • LL_USART_DisableSPISlave() : stm32wbxx_ll_usart.h
  • LL_USART_DisableSPISlaveSelect() : stm32wbxx_ll_usart.h
  • LL_USART_DMA_GetRegAddr() : stm32wbxx_ll_usart.h
  • LL_USART_Enable() : stm32wbxx_ll_usart.h
  • LL_USART_EnableAutoBaudRate() : stm32wbxx_ll_usart.h
  • LL_USART_EnableCTSHWFlowCtrl() : stm32wbxx_ll_usart.h
  • LL_USART_EnableDEMode() : stm32wbxx_ll_usart.h
  • LL_USART_EnableDirectionRx() : stm32wbxx_ll_usart.h
  • LL_USART_EnableDirectionTx() : stm32wbxx_ll_usart.h
  • LL_USART_EnableDMADeactOnRxErr() : stm32wbxx_ll_usart.h
  • LL_USART_EnableDMAReq_RX() : stm32wbxx_ll_usart.h
  • LL_USART_EnableDMAReq_TX() : stm32wbxx_ll_usart.h
  • LL_USART_EnableFIFO() : stm32wbxx_ll_usart.h
  • LL_USART_EnableHalfDuplex() : stm32wbxx_ll_usart.h
  • LL_USART_EnableInStopMode() : stm32wbxx_ll_usart.h
  • LL_USART_EnableIrda() : stm32wbxx_ll_usart.h
  • LL_USART_EnableIT_CM() : stm32wbxx_ll_usart.h
  • LL_USART_EnableIT_CTS() : stm32wbxx_ll_usart.h
  • LL_USART_EnableIT_EOB() : stm32wbxx_ll_usart.h
  • LL_USART_EnableIT_ERROR() : stm32wbxx_ll_usart.h
  • LL_USART_EnableIT_IDLE() : stm32wbxx_ll_usart.h
  • LL_USART_EnableIT_LBD() : stm32wbxx_ll_usart.h
  • LL_USART_EnableIT_PE() : stm32wbxx_ll_usart.h
  • LL_USART_EnableIT_RTO() : stm32wbxx_ll_usart.h
  • LL_USART_EnableIT_RXFF() : stm32wbxx_ll_usart.h
  • LL_USART_EnableIT_RXFT() : stm32wbxx_ll_usart.h
  • LL_USART_EnableIT_RXNE_RXFNE() : stm32wbxx_ll_usart.h
  • LL_USART_EnableIT_TC() : stm32wbxx_ll_usart.h
  • LL_USART_EnableIT_TCBGT() : stm32wbxx_ll_usart.h
  • LL_USART_EnableIT_TXE_TXFNF() : stm32wbxx_ll_usart.h
  • LL_USART_EnableIT_TXFE() : stm32wbxx_ll_usart.h
  • LL_USART_EnableIT_TXFT() : stm32wbxx_ll_usart.h
  • LL_USART_EnableIT_WKUP() : stm32wbxx_ll_usart.h
  • LL_USART_EnableLIN() : stm32wbxx_ll_usart.h
  • LL_USART_EnableMuteMode() : stm32wbxx_ll_usart.h
  • LL_USART_EnableOneBitSamp() : stm32wbxx_ll_usart.h
  • LL_USART_EnableOverrunDetect() : stm32wbxx_ll_usart.h
  • LL_USART_EnableRTSHWFlowCtrl() : stm32wbxx_ll_usart.h
  • LL_USART_EnableRxTimeout() : stm32wbxx_ll_usart.h
  • LL_USART_EnableSCLKOutput() : stm32wbxx_ll_usart.h
  • LL_USART_EnableSmartcard() : stm32wbxx_ll_usart.h
  • LL_USART_EnableSmartcardNACK() : stm32wbxx_ll_usart.h
  • LL_USART_EnableSPISlave() : stm32wbxx_ll_usart.h
  • LL_USART_EnableSPISlaveSelect() : stm32wbxx_ll_usart.h
  • LL_USART_GetAutoBaudRateMode() : stm32wbxx_ll_usart.h
  • LL_USART_GetBaudRate() : stm32wbxx_ll_usart.h
  • LL_USART_GetBinaryDataLogic() : stm32wbxx_ll_usart.h
  • LL_USART_GetBlockLength() : stm32wbxx_ll_usart.h
  • LL_USART_GetClockPhase() : stm32wbxx_ll_usart.h
  • LL_USART_GetClockPolarity() : stm32wbxx_ll_usart.h
  • LL_USART_GetDataWidth() : stm32wbxx_ll_usart.h
  • LL_USART_GetDEAssertionTime() : stm32wbxx_ll_usart.h
  • LL_USART_GetDEDeassertionTime() : stm32wbxx_ll_usart.h
  • LL_USART_GetDESignalPolarity() : stm32wbxx_ll_usart.h
  • LL_USART_GetHWFlowCtrl() : stm32wbxx_ll_usart.h
  • LL_USART_GetIrdaPowerMode() : stm32wbxx_ll_usart.h
  • LL_USART_GetIrdaPrescaler() : stm32wbxx_ll_usart.h
  • LL_USART_GetLastClkPulseOutput() : stm32wbxx_ll_usart.h
  • LL_USART_GetLINBrkDetectionLen() : stm32wbxx_ll_usart.h
  • LL_USART_GetNodeAddress() : stm32wbxx_ll_usart.h
  • LL_USART_GetNodeAddressLen() : stm32wbxx_ll_usart.h
  • LL_USART_GetOverSampling() : stm32wbxx_ll_usart.h
  • LL_USART_GetParity() : stm32wbxx_ll_usart.h
  • LL_USART_GetPrescaler() : stm32wbxx_ll_usart.h
  • LL_USART_GetRXFIFOThreshold() : stm32wbxx_ll_usart.h
  • LL_USART_GetRXPinLevel() : stm32wbxx_ll_usart.h
  • LL_USART_GetRxTimeout() : stm32wbxx_ll_usart.h
  • LL_USART_GetSmartcardAutoRetryCount() : stm32wbxx_ll_usart.h
  • LL_USART_GetSmartcardGuardTime() : stm32wbxx_ll_usart.h
  • LL_USART_GetSmartcardPrescaler() : stm32wbxx_ll_usart.h
  • LL_USART_GetStopBitsLength() : stm32wbxx_ll_usart.h
  • LL_USART_GetTransferBitOrder() : stm32wbxx_ll_usart.h
  • LL_USART_GetTransferDirection() : stm32wbxx_ll_usart.h
  • LL_USART_GetTXFIFOThreshold() : stm32wbxx_ll_usart.h
  • LL_USART_GetTXPinLevel() : stm32wbxx_ll_usart.h
  • LL_USART_GetTXRXSwap() : stm32wbxx_ll_usart.h
  • LL_USART_GetWakeUpMethod() : stm32wbxx_ll_usart.h
  • LL_USART_GetWKUPType() : stm32wbxx_ll_usart.h
  • LL_USART_Init() : stm32wbxx_ll_usart.c
  • LL_USART_IsActiveFlag_ABR() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_ABRE() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_BUSY() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_CM() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_CTS() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_EOB() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_FE() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_IDLE() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_LBD() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_nCTS() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_NE() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_ORE() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_PE() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_REACK() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_RTO() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_RWU() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_RXFF() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_RXFT() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_RXNE_RXFNE() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_SBK() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_TC() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_TCBGT() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_TEACK() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_TXE_TXFNF() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_TXFE() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_TXFT() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_UDR() : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_WKUP() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabled() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledAutoBaud() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledDEMode() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledDMADeactOnRxErr() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledDMAReq_RX() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledDMAReq_TX() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledFIFO() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledHalfDuplex() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledInStopMode() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIrda() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIT_CM() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIT_CTS() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIT_EOB() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIT_ERROR() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIT_IDLE() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIT_LBD() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIT_PE() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIT_RTO() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIT_RXFF() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIT_RXFT() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIT_RXNE_RXFNE() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIT_TC() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIT_TCBGT() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIT_TXE_TXFNF() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIT_TXFE() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIT_TXFT() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIT_WKUP() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledLIN() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledMuteMode() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledOneBitSamp() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledOverrunDetect() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledRxTimeout() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledSCLKOutput() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledSmartcard() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledSmartcardNACK() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledSPISlave() : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledSPISlaveSelect() : stm32wbxx_ll_usart.h
  • LL_USART_ReceiveData8() : stm32wbxx_ll_usart.h
  • LL_USART_ReceiveData9() : stm32wbxx_ll_usart.h
  • LL_USART_RequestAutoBaudRate() : stm32wbxx_ll_usart.h
  • LL_USART_RequestBreakSending() : stm32wbxx_ll_usart.h
  • LL_USART_RequestEnterMuteMode() : stm32wbxx_ll_usart.h
  • LL_USART_RequestRxDataFlush() : stm32wbxx_ll_usart.h
  • LL_USART_RequestTxDataFlush() : stm32wbxx_ll_usart.h
  • LL_USART_SetAutoBaudRateMode() : stm32wbxx_ll_usart.h
  • LL_USART_SetBaudRate() : stm32wbxx_ll_usart.h
  • LL_USART_SetBinaryDataLogic() : stm32wbxx_ll_usart.h
  • LL_USART_SetBlockLength() : stm32wbxx_ll_usart.h
  • LL_USART_SetClockPhase() : stm32wbxx_ll_usart.h
  • LL_USART_SetClockPolarity() : stm32wbxx_ll_usart.h
  • LL_USART_SetDataWidth() : stm32wbxx_ll_usart.h
  • LL_USART_SetDEAssertionTime() : stm32wbxx_ll_usart.h
  • LL_USART_SetDEDeassertionTime() : stm32wbxx_ll_usart.h
  • LL_USART_SetDESignalPolarity() : stm32wbxx_ll_usart.h
  • LL_USART_SetHWFlowCtrl() : stm32wbxx_ll_usart.h
  • LL_USART_SetIrdaPowerMode() : stm32wbxx_ll_usart.h
  • LL_USART_SetIrdaPrescaler() : stm32wbxx_ll_usart.h
  • LL_USART_SetLastClkPulseOutput() : stm32wbxx_ll_usart.h
  • LL_USART_SetLINBrkDetectionLen() : stm32wbxx_ll_usart.h
  • LL_USART_SetOverSampling() : stm32wbxx_ll_usart.h
  • LL_USART_SetParity() : stm32wbxx_ll_usart.h
  • LL_USART_SetPrescaler() : stm32wbxx_ll_usart.h
  • LL_USART_SetRXFIFOThreshold() : stm32wbxx_ll_usart.h
  • LL_USART_SetRXPinLevel() : stm32wbxx_ll_usart.h
  • LL_USART_SetRxTimeout() : stm32wbxx_ll_usart.h
  • LL_USART_SetSmartcardAutoRetryCount() : stm32wbxx_ll_usart.h
  • LL_USART_SetSmartcardGuardTime() : stm32wbxx_ll_usart.h
  • LL_USART_SetSmartcardPrescaler() : stm32wbxx_ll_usart.h
  • LL_USART_SetStopBitsLength() : stm32wbxx_ll_usart.h
  • LL_USART_SetTransferBitOrder() : stm32wbxx_ll_usart.h
  • LL_USART_SetTransferDirection() : stm32wbxx_ll_usart.h
  • LL_USART_SetTXFIFOThreshold() : stm32wbxx_ll_usart.h
  • LL_USART_SetTXPinLevel() : stm32wbxx_ll_usart.h
  • LL_USART_SetTXRXSwap() : stm32wbxx_ll_usart.h
  • LL_USART_SetWakeUpMethod() : stm32wbxx_ll_usart.h
  • LL_USART_SetWKUPType() : stm32wbxx_ll_usart.h
  • LL_USART_StructInit() : stm32wbxx_ll_usart.c
  • LL_USART_TransmitData8() : stm32wbxx_ll_usart.h
  • LL_USART_TransmitData9() : stm32wbxx_ll_usart.h
  • LL_VREFBUF_Disable() : stm32wbxx_ll_system.h
  • LL_VREFBUF_DisableHIZ() : stm32wbxx_ll_system.h
  • LL_VREFBUF_Enable() : stm32wbxx_ll_system.h
  • LL_VREFBUF_EnableHIZ() : stm32wbxx_ll_system.h
  • LL_VREFBUF_GetTrimming() : stm32wbxx_ll_system.h
  • LL_VREFBUF_GetVoltageScaling() : stm32wbxx_ll_system.h
  • LL_VREFBUF_IsVREFReady() : stm32wbxx_ll_system.h
  • LL_VREFBUF_SetTrimming() : stm32wbxx_ll_system.h
  • LL_VREFBUF_SetVoltageScaling() : stm32wbxx_ll_system.h
  • LL_WWDG_ClearFlag_EWKUP() : stm32wbxx_ll_wwdg.h
  • LL_WWDG_Enable() : stm32wbxx_ll_wwdg.h
  • LL_WWDG_EnableIT_EWKUP() : stm32wbxx_ll_wwdg.h
  • LL_WWDG_GetCounter() : stm32wbxx_ll_wwdg.h
  • LL_WWDG_GetPrescaler() : stm32wbxx_ll_wwdg.h
  • LL_WWDG_GetWindow() : stm32wbxx_ll_wwdg.h
  • LL_WWDG_IsActiveFlag_EWKUP() : stm32wbxx_ll_wwdg.h
  • LL_WWDG_IsEnabled() : stm32wbxx_ll_wwdg.h
  • LL_WWDG_IsEnabledIT_EWKUP() : stm32wbxx_ll_wwdg.h
  • LL_WWDG_SetCounter() : stm32wbxx_ll_wwdg.h
  • LL_WWDG_SetPrescaler() : stm32wbxx_ll_wwdg.h
  • LL_WWDG_SetWindow() : stm32wbxx_ll_wwdg.h
  • LPTIM_Disable() : stm32wbxx_hal_lptim.c
  • LPTIM_ResetCallback() : stm32wbxx_hal_lptim.c
  • LPTIM_WaitForFlag() : stm32wbxx_hal_lptim.c
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

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- o -

  • OC1Config() : stm32wbxx_ll_tim.c
  • OC2Config() : stm32wbxx_ll_tim.c
  • OC3Config() : stm32wbxx_ll_tim.c
  • OC4Config() : stm32wbxx_ll_tim.c
  • OC5Config() : stm32wbxx_ll_tim.c
  • OC6Config() : stm32wbxx_ll_tim.c
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
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- p -

  • PCD_EP_ISR_Handler() : stm32wbxx_hal_pcd.c
  • PKA_ARI_Set() : stm32wbxx_hal_pka.c
  • PKA_CheckError() : stm32wbxx_hal_pka.c
  • PKA_ECCMul_Set() : stm32wbxx_hal_pka.c
  • PKA_ECCMulFastMode_Set() : stm32wbxx_hal_pka.c
  • PKA_ECDSASign_Set() : stm32wbxx_hal_pka.c
  • PKA_ECDSAVerif_Set() : stm32wbxx_hal_pka.c
  • PKA_GetArraySize_u8() : stm32wbxx_hal_pka.c
  • PKA_GetBitSize_u32() : stm32wbxx_hal_pka.c
  • PKA_GetBitSize_u8() : stm32wbxx_hal_pka.c
  • PKA_GetMode() : stm32wbxx_hal_pka.c
  • PKA_GetOptBitSize_u8() : stm32wbxx_hal_pka.c
  • PKA_Memcpy_u32_to_u32() : stm32wbxx_hal_pka.c
  • PKA_Memcpy_u32_to_u8() : stm32wbxx_hal_pka.c
  • PKA_Memcpy_u8_to_u32() : stm32wbxx_hal_pka.c
  • PKA_ModExp_Set() : stm32wbxx_hal_pka.c
  • PKA_ModExpFastMode_Set() : stm32wbxx_hal_pka.c
  • PKA_ModInv_Set() : stm32wbxx_hal_pka.c
  • PKA_ModRed_Set() : stm32wbxx_hal_pka.c
  • PKA_MontgomeryParam_Set() : stm32wbxx_hal_pka.c
  • PKA_PointCheck_Set() : stm32wbxx_hal_pka.c
  • PKA_PollEndOfOperation() : stm32wbxx_hal_pka.c
  • PKA_Process() : stm32wbxx_hal_pka.c
  • PKA_Process_IT() : stm32wbxx_hal_pka.c
  • PKA_RSACRTExp_Set() : stm32wbxx_hal_pka.c
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STM32WB55xx HAL User Manual: Globals

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- q -

  • QSPI_Config() : stm32wbxx_hal_qspi.c
  • QSPI_DMAAbortCplt() : stm32wbxx_hal_qspi.c
  • QSPI_DMAError() : stm32wbxx_hal_qspi.c
  • QSPI_DMARxCplt() : stm32wbxx_hal_qspi.c
  • QSPI_DMARxHalfCplt() : stm32wbxx_hal_qspi.c
  • QSPI_DMATxCplt() : stm32wbxx_hal_qspi.c
  • QSPI_DMATxHalfCplt() : stm32wbxx_hal_qspi.c
  • QSPI_WaitFlagStateUntilTimeout() : stm32wbxx_hal_qspi.c
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STM32WB55xx HAL User Manual: Globals

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- r -

  • RCC_GetHCLK1ClockFreq() : stm32wbxx_ll_rcc.c
  • RCC_GetHCLK2ClockFreq() : stm32wbxx_ll_rcc.c
  • RCC_GetHCLK4ClockFreq() : stm32wbxx_ll_rcc.c
  • RCC_GetHCLK5ClockFreq() : stm32wbxx_ll_rcc.c
  • RCC_GetPCLK1ClockFreq() : stm32wbxx_ll_rcc.c
  • RCC_GetPCLK2ClockFreq() : stm32wbxx_ll_rcc.c
  • RCC_GetSystemClockFreq() : stm32wbxx_ll_rcc.c
  • RCC_PLL_GetFreqDomain_48M() : stm32wbxx_ll_rcc.c
  • RCC_PLL_GetFreqDomain_ADC() : stm32wbxx_ll_rcc.c
  • RCC_PLL_GetFreqDomain_P() : stm32wbxx_hal_rcc_ex.c
  • RCC_PLL_GetFreqDomain_Q() : stm32wbxx_hal_rcc_ex.c
  • RCC_PLL_GetFreqDomain_SAI() : stm32wbxx_ll_rcc.c
  • RCC_PLL_GetFreqDomain_SYS() : stm32wbxx_ll_rcc.c
  • RCC_PLLSAI1_GetFreqDomain_48M() : stm32wbxx_ll_rcc.c
  • RCC_PLLSAI1_GetFreqDomain_ADC() : stm32wbxx_ll_rcc.c
  • RCC_PLLSAI1_GetFreqDomain_P() : stm32wbxx_hal_rcc_ex.c
  • RCC_PLLSAI1_GetFreqDomain_Q() : stm32wbxx_hal_rcc_ex.c
  • RCC_PLLSAI1_GetFreqDomain_R() : stm32wbxx_hal_rcc_ex.c
  • RCC_PLLSAI1_GetFreqDomain_SAI() : stm32wbxx_ll_rcc.c
  • RCC_SetFlashLatency() : stm32wbxx_hal_rcc.c
  • RCC_SetFlashLatencyFromMSIRange() : stm32wbxx_hal_rcc.c
  • RCCEx_PLLSAI1_ConfigNP() : stm32wbxx_hal_rcc_ex.c
  • RCCEx_PLLSAI1_ConfigNQ() : stm32wbxx_hal_rcc_ex.c
  • RCCEx_PLLSAI1_ConfigNR() : stm32wbxx_hal_rcc_ex.c
  • RTC_Bcd2ToByte() : stm32wbxx_hal_rtc.c
  • RTC_ByteToBcd2() : stm32wbxx_hal_rtc.c
  • RTC_EnterInitMode() : stm32wbxx_hal_rtc.c
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STM32WB55xx HAL User Manual: Globals

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- s -

  • SAI_Disable() : stm32wbxx_hal_sai.c
  • SAI_DMAAbort() : stm32wbxx_hal_sai.c
  • SAI_DMAError() : stm32wbxx_hal_sai.c
  • SAI_DMARxCplt() : stm32wbxx_hal_sai.c
  • SAI_DMARxHalfCplt() : stm32wbxx_hal_sai.c
  • SAI_DMATxCplt() : stm32wbxx_hal_sai.c
  • SAI_DMATxHalfCplt() : stm32wbxx_hal_sai.c
  • SAI_FillFifo() : stm32wbxx_hal_sai.c
  • SAI_InitI2S() : stm32wbxx_hal_sai.c
  • SAI_InitPCM() : stm32wbxx_hal_sai.c
  • SAI_InterruptFlag() : stm32wbxx_hal_sai.c
  • SAI_Receive_IT16Bit() : stm32wbxx_hal_sai.c
  • SAI_Receive_IT32Bit() : stm32wbxx_hal_sai.c
  • SAI_Receive_IT8Bit() : stm32wbxx_hal_sai.c
  • SAI_Transmit_IT16Bit() : stm32wbxx_hal_sai.c
  • SAI_Transmit_IT32Bit() : stm32wbxx_hal_sai.c
  • SAI_Transmit_IT8Bit() : stm32wbxx_hal_sai.c
  • SMARTCARD_AdvFeatureConfig() : stm32wbxx_hal_smartcard.c
  • SMARTCARD_CheckIdleState() : stm32wbxx_hal_smartcard.c
  • SMARTCARD_DMAAbortOnError() : stm32wbxx_hal_smartcard.c
  • SMARTCARD_DMAError() : stm32wbxx_hal_smartcard.c
  • SMARTCARD_DMAReceiveCplt() : stm32wbxx_hal_smartcard.c
  • SMARTCARD_DMARxAbortCallback() : stm32wbxx_hal_smartcard.c
  • SMARTCARD_DMARxOnlyAbortCallback() : stm32wbxx_hal_smartcard.c
  • SMARTCARD_DMATransmitCplt() : stm32wbxx_hal_smartcard.c
  • SMARTCARD_DMATxAbortCallback() : stm32wbxx_hal_smartcard.c
  • SMARTCARD_DMATxOnlyAbortCallback() : stm32wbxx_hal_smartcard.c
  • SMARTCARD_EndRxTransfer() : stm32wbxx_hal_smartcard.c
  • SMARTCARD_EndTransmit_IT() : stm32wbxx_hal_smartcard.c
  • SMARTCARD_EndTxTransfer() : stm32wbxx_hal_smartcard.c
  • SMARTCARD_InitCallbacksToDefault() : stm32wbxx_hal_smartcard.c
  • SMARTCARD_RxISR() : stm32wbxx_hal_smartcard.c
  • SMARTCARD_RxISR_FIFOEN() : stm32wbxx_hal_smartcard.c
  • SMARTCARD_SetConfig() : stm32wbxx_hal_smartcard.c
  • SMARTCARD_TxISR() : stm32wbxx_hal_smartcard.c
  • SMARTCARD_TxISR_FIFOEN() : stm32wbxx_hal_smartcard.c
  • SMARTCARD_WaitOnFlagUntilTimeout() : stm32wbxx_hal_smartcard.c
  • SMARTCARDEx_SetNbDataToProcess() : stm32wbxx_hal_smartcard_ex.c
  • SMBUS_ConvertOtherXferOptions() : stm32wbxx_hal_smbus.c
  • SMBUS_Disable_IRQ() : stm32wbxx_hal_smbus.c
  • SMBUS_Enable_IRQ() : stm32wbxx_hal_smbus.c
  • SMBUS_ITErrorHandler() : stm32wbxx_hal_smbus.c
  • SMBUS_Master_ISR() : stm32wbxx_hal_smbus.c
  • SMBUS_Slave_ISR() : stm32wbxx_hal_smbus.c
  • SMBUS_TransferConfig() : stm32wbxx_hal_smbus.c
  • SMBUS_WaitOnFlagUntilTimeout() : stm32wbxx_hal_smbus.c
  • SPI_2linesRxISR_16BIT() : stm32wbxx_hal_spi.c
  • SPI_2linesRxISR_16BITCRC() : stm32wbxx_hal_spi.c
  • SPI_2linesRxISR_8BIT() : stm32wbxx_hal_spi.c
  • SPI_2linesRxISR_8BITCRC() : stm32wbxx_hal_spi.c
  • SPI_2linesTxISR_16BIT() : stm32wbxx_hal_spi.c
  • SPI_2linesTxISR_8BIT() : stm32wbxx_hal_spi.c
  • SPI_AbortRx_ISR() : stm32wbxx_hal_spi.c
  • SPI_AbortTx_ISR() : stm32wbxx_hal_spi.c
  • SPI_CloseRx_ISR() : stm32wbxx_hal_spi.c
  • SPI_CloseRxTx_ISR() : stm32wbxx_hal_spi.c
  • SPI_CloseTx_ISR() : stm32wbxx_hal_spi.c
  • SPI_DMAAbortOnError() : stm32wbxx_hal_spi.c
  • SPI_DMAError() : stm32wbxx_hal_spi.c
  • SPI_DMAHalfReceiveCplt() : stm32wbxx_hal_spi.c
  • SPI_DMAHalfTransmitCplt() : stm32wbxx_hal_spi.c
  • SPI_DMAHalfTransmitReceiveCplt() : stm32wbxx_hal_spi.c
  • SPI_DMAReceiveCplt() : stm32wbxx_hal_spi.c
  • SPI_DMARxAbortCallback() : stm32wbxx_hal_spi.c
  • SPI_DMATransmitCplt() : stm32wbxx_hal_spi.c
  • SPI_DMATransmitReceiveCplt() : stm32wbxx_hal_spi.c
  • SPI_DMATxAbortCallback() : stm32wbxx_hal_spi.c
  • SPI_EndRxTransaction() : stm32wbxx_hal_spi.c
  • SPI_EndRxTxTransaction() : stm32wbxx_hal_spi.c
  • SPI_RxISR_16BIT() : stm32wbxx_hal_spi.c
  • SPI_RxISR_16BITCRC() : stm32wbxx_hal_spi.c
  • SPI_RxISR_8BIT() : stm32wbxx_hal_spi.c
  • SPI_RxISR_8BITCRC() : stm32wbxx_hal_spi.c
  • SPI_TxISR_16BIT() : stm32wbxx_hal_spi.c
  • SPI_TxISR_8BIT() : stm32wbxx_hal_spi.c
  • SPI_WaitFifoStateUntilTimeout() : stm32wbxx_hal_spi.c
  • SPI_WaitFlagStateUntilTimeout() : stm32wbxx_hal_spi.c
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STM32WB55xx HAL User Manual: Globals

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- t -

  • TIM_Base_SetConfig() : stm32wbxx_hal_tim.c
  • TIM_CCxChannelCmd() : stm32wbxx_hal_tim.c
  • TIM_CCxNChannelCmd() : stm32wbxx_hal_tim_ex.c
  • TIM_DMACaptureCplt() : stm32wbxx_hal_tim.c
  • TIM_DMACaptureHalfCplt() : stm32wbxx_hal_tim.c
  • TIM_DMADelayPulseCplt() : stm32wbxx_hal_tim.c
  • TIM_DMADelayPulseHalfCplt() : stm32wbxx_hal_tim.c
  • TIM_DMAError() : stm32wbxx_hal_tim.c
  • TIM_DMAPeriodElapsedCplt() : stm32wbxx_hal_tim.c
  • TIM_DMAPeriodElapsedHalfCplt() : stm32wbxx_hal_tim.c
  • TIM_DMATriggerCplt() : stm32wbxx_hal_tim.c
  • TIM_DMATriggerHalfCplt() : stm32wbxx_hal_tim.c
  • TIM_ETR_SetConfig() : stm32wbxx_hal_tim.c
  • TIM_ITRx_SetConfig() : stm32wbxx_hal_tim.c
  • TIM_OC1_SetConfig() : stm32wbxx_hal_tim.c
  • TIM_OC2_SetConfig() : stm32wbxx_hal_tim.c
  • TIM_OC3_SetConfig() : stm32wbxx_hal_tim.c
  • TIM_OC4_SetConfig() : stm32wbxx_hal_tim.c
  • TIM_OC5_SetConfig() : stm32wbxx_hal_tim.c
  • TIM_OC6_SetConfig() : stm32wbxx_hal_tim.c
  • TIM_ResetCallback() : stm32wbxx_hal_tim.c
  • TIM_SlaveTimer_SetConfig() : stm32wbxx_hal_tim.c
  • TIM_TI1_ConfigInputStage() : stm32wbxx_hal_tim.c
  • TIM_TI1_SetConfig() : stm32wbxx_hal_tim.c
  • TIM_TI2_ConfigInputStage() : stm32wbxx_hal_tim.c
  • TIM_TI2_SetConfig() : stm32wbxx_hal_tim.c
  • TIM_TI3_SetConfig() : stm32wbxx_hal_tim.c
  • TIM_TI4_SetConfig() : stm32wbxx_hal_tim.c
  • TIMEx_DMACommutationCplt() : stm32wbxx_hal_tim_ex.c
  • TIMEx_DMACommutationHalfCplt() : stm32wbxx_hal_tim_ex.c
  • TSC_extract_groups() : stm32wbxx_hal_tsc.c
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STM32WB55xx HAL User Manual: Globals

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- u -

  • UART_AdvFeatureConfig() : stm32wbxx_hal_uart.c
  • UART_CheckIdleState() : stm32wbxx_hal_uart.c
  • UART_DMAAbortOnError() : stm32wbxx_hal_uart.c
  • UART_DMAError() : stm32wbxx_hal_uart.c
  • UART_DMAReceiveCplt() : stm32wbxx_hal_uart.c
  • UART_DMARxAbortCallback() : stm32wbxx_hal_uart.c
  • UART_DMARxHalfCplt() : stm32wbxx_hal_uart.c
  • UART_DMARxOnlyAbortCallback() : stm32wbxx_hal_uart.c
  • UART_DMATransmitCplt() : stm32wbxx_hal_uart.c
  • UART_DMATxAbortCallback() : stm32wbxx_hal_uart.c
  • UART_DMATxHalfCplt() : stm32wbxx_hal_uart.c
  • UART_DMATxOnlyAbortCallback() : stm32wbxx_hal_uart.c
  • UART_EndRxTransfer() : stm32wbxx_hal_uart.c
  • UART_EndTransmit_IT() : stm32wbxx_hal_uart.c
  • UART_EndTxTransfer() : stm32wbxx_hal_uart.c
  • UART_InitCallbacksToDefault() : stm32wbxx_hal_uart.c
  • UART_RxISR_16BIT() : stm32wbxx_hal_uart.c
  • UART_RxISR_16BIT_FIFOEN() : stm32wbxx_hal_uart.c
  • UART_RxISR_8BIT() : stm32wbxx_hal_uart.c
  • UART_RxISR_8BIT_FIFOEN() : stm32wbxx_hal_uart.c
  • UART_SetConfig() : stm32wbxx_hal_uart.c
  • UART_TxISR_16BIT() : stm32wbxx_hal_uart.c
  • UART_TxISR_16BIT_FIFOEN() : stm32wbxx_hal_uart.c
  • UART_TxISR_8BIT() : stm32wbxx_hal_uart.c
  • UART_TxISR_8BIT_FIFOEN() : stm32wbxx_hal_uart.c
  • UART_WaitOnFlagUntilTimeout() : stm32wbxx_hal_uart.c
  • UARTEx_SetNbDataToProcess() : stm32wbxx_hal_uart_ex.c
  • UARTEx_Wakeup_AddressConfig() : stm32wbxx_hal_uart_ex.c
  • USART_CheckIdleState() : stm32wbxx_hal_usart.c
  • USART_DMAAbortOnError() : stm32wbxx_hal_usart.c
  • USART_DMAError() : stm32wbxx_hal_usart.c
  • USART_DMAReceiveCplt() : stm32wbxx_hal_usart.c
  • USART_DMARxAbortCallback() : stm32wbxx_hal_usart.c
  • USART_DMARxHalfCplt() : stm32wbxx_hal_usart.c
  • USART_DMATransmitCplt() : stm32wbxx_hal_usart.c
  • USART_DMATxAbortCallback() : stm32wbxx_hal_usart.c
  • USART_DMATxHalfCplt() : stm32wbxx_hal_usart.c
  • USART_EndTransfer() : stm32wbxx_hal_usart.c
  • USART_EndTransmit_IT() : stm32wbxx_hal_usart.c
  • USART_InitCallbacksToDefault() : stm32wbxx_hal_usart.c
  • USART_RxISR_16BIT() : stm32wbxx_hal_usart.c
  • USART_RxISR_16BIT_FIFOEN() : stm32wbxx_hal_usart.c
  • USART_RxISR_8BIT() : stm32wbxx_hal_usart.c
  • USART_RxISR_8BIT_FIFOEN() : stm32wbxx_hal_usart.c
  • USART_SetConfig() : stm32wbxx_hal_usart.c
  • USART_TxISR_16BIT() : stm32wbxx_hal_usart.c
  • USART_TxISR_16BIT_FIFOEN() : stm32wbxx_hal_usart.c
  • USART_TxISR_8BIT() : stm32wbxx_hal_usart.c
  • USART_TxISR_8BIT_FIFOEN() : stm32wbxx_hal_usart.c
  • USART_WaitOnFlagUntilTimeout() : stm32wbxx_hal_usart.c
  • USARTEx_SetNbDataToProcess() : stm32wbxx_hal_usart_ex.c
  • UTILS_EnablePLLAndSwitchSystem() : stm32wbxx_ll_utils.c
  • UTILS_GetPLLOutputFrequency() : stm32wbxx_ll_utils.c
  • UTILS_PLL_IsBusy() : stm32wbxx_ll_utils.c
  • UTILS_SetFlashLatency() : stm32wbxx_ll_utils.c
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STM32WB55xx HAL User Manual: Globals

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  • LPUART_PRESCALER_TAB : stm32wbxx_ll_lpuart.h
  • OFFSET_TAB_CCMRx : stm32wbxx_ll_tim.h
  • pFlash : stm32wbxx_hal_flash.c , stm32wbxx_hal_flash.h
  • SHIFT_TAB_CCxP : stm32wbxx_ll_tim.h
  • SHIFT_TAB_ICxx : stm32wbxx_ll_tim.h
  • SHIFT_TAB_OCxx : stm32wbxx_ll_tim.h
  • SHIFT_TAB_OISx : stm32wbxx_ll_tim.h
  • USART_PRESCALER_TAB : stm32wbxx_ll_usart.h
  • uwTick : stm32wbxx_hal.c , stm32wbxx_hal.h
  • uwTickFreq : stm32wbxx_hal.h , stm32wbxx_hal.c
  • uwTickPrio : stm32wbxx_hal.c , stm32wbxx_hal.h
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STM32WB55xx HAL User Manual: Globals

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  • w

- a -

  • ADC_HandleTypeDef : stm32wbxx_hal_adc.h

- c -

  • ChannelCb : stm32wbxx_hal_ipcc.h
  • COMP_HandleTypeDef : stm32wbxx_hal_comp.h
  • CRYP_HandleTypeDef : stm32wbxx_hal_cryp.h

- d -

  • DMA_HandleTypeDef : stm32wbxx_hal_dma.h

- h -

  • HAL_IRDA_StateTypeDef : stm32wbxx_hal_irda.h
  • HAL_SMARTCARD_StateTypeDef : stm32wbxx_hal_smartcard.h
  • HAL_UART_StateTypeDef : stm32wbxx_hal_uart.h

- i -

  • I2C_HandleTypeDef : stm32wbxx_hal_i2c.h
  • IPCC_HandleTypeDef : stm32wbxx_hal_ipcc.h
  • IRDA_HandleTypeDef : stm32wbxx_hal_irda.h

- l -

  • LPTIM_HandleTypeDef : stm32wbxx_hal_lptim.h

- p -

  • pADC_CallbackTypeDef : stm32wbxx_hal_adc.h
  • PCD_EPTypeDef : stm32wbxx_hal_pcd.h
  • PCD_HandleTypeDef : stm32wbxx_hal_pcd.h
  • PCD_InitTypeDef : stm32wbxx_hal_pcd.h
  • PCD_TypeDef : stm32wbxx_hal_pcd.h
  • pCOMP_CallbackTypeDef : stm32wbxx_hal_comp.h
  • pCRYP_CallbackTypeDef : stm32wbxx_hal_cryp.h
  • pI2C_AddrCallbackTypeDef : stm32wbxx_hal_i2c.h
  • pI2C_CallbackTypeDef : stm32wbxx_hal_i2c.h
  • pIRDA_CallbackTypeDef : stm32wbxx_hal_irda.h
  • PKA_CmpInTypeDef : stm32wbxx_hal_pka.h
  • PKA_ECCMulOutTypeDef : stm32wbxx_hal_pka.h
  • PKA_HandleTypeDef : stm32wbxx_hal_pka.h
  • PKA_ModSubInTypeDef : stm32wbxx_hal_pka.h
  • PKA_MontgomeryMulInTypeDef : stm32wbxx_hal_pka.h
  • PKA_MulInTypeDef : stm32wbxx_hal_pka.h
  • PKA_SubInTypeDef : stm32wbxx_hal_pka.h
  • pLPTIM_CallbackTypeDef : stm32wbxx_hal_lptim.h
  • pPCD_BcdCallbackTypeDef : stm32wbxx_hal_pcd.h
  • pPCD_CallbackTypeDef : stm32wbxx_hal_pcd.h
  • pPCD_DataInStageCallbackTypeDef : stm32wbxx_hal_pcd.h
  • pPCD_DataOutStageCallbackTypeDef : stm32wbxx_hal_pcd.h
  • pPCD_IsoInIncpltCallbackTypeDef : stm32wbxx_hal_pcd.h
  • pPCD_IsoOutIncpltCallbackTypeDef : stm32wbxx_hal_pcd.h
  • pPCD_LpmCallbackTypeDef : stm32wbxx_hal_pcd.h
  • pPKA_CallbackTypeDef : stm32wbxx_hal_pka.h
  • pQSPI_CallbackTypeDef : stm32wbxx_hal_qspi.h
  • pRNG_CallbackTypeDef : stm32wbxx_hal_rng.h
  • pRNG_ReadyDataCallbackTypeDef : stm32wbxx_hal_rng.h
  • pRTC_CallbackTypeDef : stm32wbxx_hal_rtc.h
  • pSAI_CallbackTypeDef : stm32wbxx_hal_sai.h
  • pSMARTCARD_CallbackTypeDef : stm32wbxx_hal_smartcard.h
  • pSMBUS_AddrCallbackTypeDef : stm32wbxx_hal_smbus.h
  • pSMBUS_CallbackTypeDef : stm32wbxx_hal_smbus.h
  • pSPI_CallbackTypeDef : stm32wbxx_hal_spi.h
  • pTIM_CallbackTypeDef : stm32wbxx_hal_tim.h
  • pTSC_CallbackTypeDef : stm32wbxx_hal_tsc.h
  • pUART_CallbackTypeDef : stm32wbxx_hal_uart.h
  • pUSART_CallbackTypeDef : stm32wbxx_hal_usart.h
  • pWWDG_CallbackTypeDef : stm32wbxx_hal_wwdg.h

- q -

  • QSPI_HandleTypeDef : stm32wbxx_hal_qspi.h

- r -

  • RNG_HandleTypeDef : stm32wbxx_hal_rng.h
  • RTC_HandleTypeDef : stm32wbxx_hal_rtc.h

- s -

  • SAI_HandleTypeDef : stm32wbxx_hal_sai.h
  • SAIcallback : stm32wbxx_hal_sai.h
  • SMARTCARD_HandleTypeDef : stm32wbxx_hal_smartcard.h
  • SMBUS_HandleTypeDef : stm32wbxx_hal_smbus.h
  • SPI_HandleTypeDef : stm32wbxx_hal_spi.h

- t -

  • TIM_HandleTypeDef : stm32wbxx_hal_tim.h
  • TSC_HandleTypeDef : stm32wbxx_hal_tsc.h

- u -

  • UART_HandleTypeDef : stm32wbxx_hal_uart.h
  • USART_HandleTypeDef : stm32wbxx_hal_usart.h

- w -

  • WWDG_HandleTypeDef : stm32wbxx_hal_wwdg.h
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • e
  • g
  • h
  • i
  • p
  • s
  • t
  • u

- e -

  • EXTI_CallbackIDTypeDef : stm32wbxx_hal_exti.h

- g -

  • GPIO_PinState : stm32wbxx_hal_gpio.h

- h -

  • HAL_ADC_CallbackIDTypeDef : stm32wbxx_hal_adc.h
  • HAL_COMP_CallbackIDTypeDef : stm32wbxx_hal_comp.h
  • HAL_COMP_StateTypeDef : stm32wbxx_hal_comp.h
  • HAL_CRC_StateTypeDef : stm32wbxx_hal_crc.h
  • HAL_CRYP_CallbackIDTypeDef : stm32wbxx_hal_cryp.h
  • HAL_CRYP_STATETypeDef : stm32wbxx_hal_cryp.h
  • HAL_DMA_CallbackIDTypeDef : stm32wbxx_hal_dma.h
  • HAL_DMA_LevelCompleteTypeDef : stm32wbxx_hal_dma.h
  • HAL_DMA_StateTypeDef : stm32wbxx_hal_dma.h
  • HAL_I2C_CallbackIDTypeDef : stm32wbxx_hal_i2c.h
  • HAL_I2C_ModeTypeDef : stm32wbxx_hal_i2c.h
  • HAL_I2C_StateTypeDef : stm32wbxx_hal_i2c.h
  • HAL_IPCC_StateTypeDef : stm32wbxx_hal_ipcc.h
  • HAL_IRDA_CallbackIDTypeDef : stm32wbxx_hal_irda.h
  • HAL_LCD_StateTypeDef : stm32wbxx_hal_lcd.h
  • HAL_LPTIM_CallbackIDTypeDef : stm32wbxx_hal_lptim.h
  • HAL_LPTIM_StateTypeDef : stm32wbxx_hal_lptim.h
  • HAL_PCD_CallbackIDTypeDef : stm32wbxx_hal_pcd.h
  • HAL_PKA_CallbackIDTypeDef : stm32wbxx_hal_pka.h
  • HAL_PKA_StateTypeDef : stm32wbxx_hal_pka.h
  • HAL_QSPI_CallbackIDTypeDef : stm32wbxx_hal_qspi.h
  • HAL_QSPI_StateTypeDef : stm32wbxx_hal_qspi.h
  • HAL_RNG_CallbackIDTypeDef : stm32wbxx_hal_rng.h
  • HAL_RNG_StateTypeDef : stm32wbxx_hal_rng.h
  • HAL_RTC_CallbackIDTypeDef : stm32wbxx_hal_rtc.h
  • HAL_RTCStateTypeDef : stm32wbxx_hal_rtc.h
  • HAL_SAI_CallbackIDTypeDef : stm32wbxx_hal_sai.h
  • HAL_SAI_StateTypeDef : stm32wbxx_hal_sai.h
  • HAL_SMARTCARD_CallbackIDTypeDef : stm32wbxx_hal_smartcard.h
  • HAL_SMBUS_CallbackIDTypeDef : stm32wbxx_hal_smbus.h
  • HAL_SPI_CallbackIDTypeDef : stm32wbxx_hal_spi.h
  • HAL_SPI_StateTypeDef : stm32wbxx_hal_spi.h
  • HAL_TIM_ActiveChannel : stm32wbxx_hal_tim.h
  • HAL_TIM_CallbackIDTypeDef : stm32wbxx_hal_tim.h
  • HAL_TIM_StateTypeDef : stm32wbxx_hal_tim.h
  • HAL_TSC_CallbackIDTypeDef : stm32wbxx_hal_tsc.h
  • HAL_TSC_StateTypeDef : stm32wbxx_hal_tsc.h
  • HAL_UART_CallbackIDTypeDef : stm32wbxx_hal_uart.h
  • HAL_USART_CallbackIDTypeDef : stm32wbxx_hal_usart.h
  • HAL_USART_StateTypeDef : stm32wbxx_hal_usart.h
  • HAL_WWDG_CallbackIDTypeDef : stm32wbxx_hal_wwdg.h

- i -

  • IPCC_CHANNELDirTypeDef : stm32wbxx_hal_ipcc.h
  • IPCC_CHANNELStatusTypeDef : stm32wbxx_hal_ipcc.h
  • IRDA_ClockSourceTypeDef : stm32wbxx_hal_irda.h

- p -

  • PCD_BCD_MsgTypeDef : stm32wbxx_hal_pcd.h
  • PCD_LPM_MsgTypeDef : stm32wbxx_hal_pcd.h
  • PCD_LPM_StateTypeDef : stm32wbxx_hal_pcd.h
  • PCD_StateTypeDef : stm32wbxx_hal_pcd.h

- s -

  • SAI_ModeTypedef : stm32wbxx_hal_sai.c
  • SMARTCARD_ClockSourceTypeDef : stm32wbxx_hal_smartcard.h

- t -

  • TSC_GroupStatusTypeDef : stm32wbxx_hal_tsc.h

- u -

  • UART_ClockSourceTypeDef : stm32wbxx_hal_uart.h
  • USART_ClockSourceTypeDef : stm32wbxx_hal_usart.h
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • g
  • h
  • i
  • l
  • p
  • s
  • t
  • u

- g -

  • GPIO_PIN_RESET : stm32wbxx_hal_gpio.h
  • GPIO_PIN_SET : stm32wbxx_hal_gpio.h
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • g
  • h
  • i
  • l
  • p
  • s
  • t
  • u

- h -

  • HAL_ADC_CONVERSION_COMPLETE_CB_ID : stm32wbxx_hal_adc.h
  • HAL_ADC_CONVERSION_HALF_CB_ID : stm32wbxx_hal_adc.h
  • HAL_ADC_END_OF_SAMPLING_CB_ID : stm32wbxx_hal_adc.h
  • HAL_ADC_ERROR_CB_ID : stm32wbxx_hal_adc.h
  • HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : stm32wbxx_hal_adc.h
  • HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID : stm32wbxx_hal_adc.h
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : stm32wbxx_hal_adc.h
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID : stm32wbxx_hal_adc.h
  • HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID : stm32wbxx_hal_adc.h
  • HAL_ADC_MSPDEINIT_CB_ID : stm32wbxx_hal_adc.h
  • HAL_ADC_MSPINIT_CB_ID : stm32wbxx_hal_adc.h
  • HAL_COMP_MSPDEINIT_CB_ID : stm32wbxx_hal_comp.h
  • HAL_COMP_MSPINIT_CB_ID : stm32wbxx_hal_comp.h
  • HAL_COMP_STATE_BUSY : stm32wbxx_hal_comp.h
  • HAL_COMP_STATE_BUSY_LOCKED : stm32wbxx_hal_comp.h
  • HAL_COMP_STATE_READY : stm32wbxx_hal_comp.h
  • HAL_COMP_STATE_READY_LOCKED : stm32wbxx_hal_comp.h
  • HAL_COMP_STATE_RESET : stm32wbxx_hal_comp.h
  • HAL_COMP_STATE_RESET_LOCKED : stm32wbxx_hal_comp.h
  • HAL_COMP_TRIGGER_CB_ID : stm32wbxx_hal_comp.h
  • HAL_CRC_STATE_BUSY : stm32wbxx_hal_crc.h
  • HAL_CRC_STATE_ERROR : stm32wbxx_hal_crc.h
  • HAL_CRC_STATE_READY : stm32wbxx_hal_crc.h
  • HAL_CRC_STATE_RESET : stm32wbxx_hal_crc.h
  • HAL_CRC_STATE_TIMEOUT : stm32wbxx_hal_crc.h
  • HAL_CRYP_ERROR_CB_ID : stm32wbxx_hal_cryp.h
  • HAL_CRYP_INPUT_COMPLETE_CB_ID : stm32wbxx_hal_cryp.h
  • HAL_CRYP_MSPDEINIT_CB_ID : stm32wbxx_hal_cryp.h
  • HAL_CRYP_MSPINIT_CB_ID : stm32wbxx_hal_cryp.h
  • HAL_CRYP_OUTPUT_COMPLETE_CB_ID : stm32wbxx_hal_cryp.h
  • HAL_CRYP_STATE_BUSY : stm32wbxx_hal_cryp.h
  • HAL_CRYP_STATE_READY : stm32wbxx_hal_cryp.h
  • HAL_CRYP_STATE_RESET : stm32wbxx_hal_cryp.h
  • HAL_DMA_FULL_TRANSFER : stm32wbxx_hal_dma.h
  • HAL_DMA_HALF_TRANSFER : stm32wbxx_hal_dma.h
  • HAL_DMA_STATE_BUSY : stm32wbxx_hal_dma.h
  • HAL_DMA_STATE_READY : stm32wbxx_hal_dma.h
  • HAL_DMA_STATE_RESET : stm32wbxx_hal_dma.h
  • HAL_DMA_STATE_TIMEOUT : stm32wbxx_hal_dma.h
  • HAL_DMA_XFER_ABORT_CB_ID : stm32wbxx_hal_dma.h
  • HAL_DMA_XFER_ALL_CB_ID : stm32wbxx_hal_dma.h
  • HAL_DMA_XFER_CPLT_CB_ID : stm32wbxx_hal_dma.h
  • HAL_DMA_XFER_ERROR_CB_ID : stm32wbxx_hal_dma.h
  • HAL_DMA_XFER_HALFCPLT_CB_ID : stm32wbxx_hal_dma.h
  • HAL_EXTI_COMMON_CB_ID : stm32wbxx_hal_exti.h
  • HAL_I2C_ABORT_CB_ID : stm32wbxx_hal_i2c.h
  • HAL_I2C_ERROR_CB_ID : stm32wbxx_hal_i2c.h
  • HAL_I2C_LISTEN_COMPLETE_CB_ID : stm32wbxx_hal_i2c.h
  • HAL_I2C_MASTER_RX_COMPLETE_CB_ID : stm32wbxx_hal_i2c.h
  • HAL_I2C_MASTER_TX_COMPLETE_CB_ID : stm32wbxx_hal_i2c.h
  • HAL_I2C_MEM_RX_COMPLETE_CB_ID : stm32wbxx_hal_i2c.h
  • HAL_I2C_MEM_TX_COMPLETE_CB_ID : stm32wbxx_hal_i2c.h
  • HAL_I2C_MODE_MASTER : stm32wbxx_hal_i2c.h
  • HAL_I2C_MODE_MEM : stm32wbxx_hal_i2c.h
  • HAL_I2C_MODE_NONE : stm32wbxx_hal_i2c.h
  • HAL_I2C_MODE_SLAVE : stm32wbxx_hal_i2c.h
  • HAL_I2C_MSPDEINIT_CB_ID : stm32wbxx_hal_i2c.h
  • HAL_I2C_MSPINIT_CB_ID : stm32wbxx_hal_i2c.h
  • HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : stm32wbxx_hal_i2c.h
  • HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : stm32wbxx_hal_i2c.h
  • HAL_I2C_STATE_ABORT : stm32wbxx_hal_i2c.h
  • HAL_I2C_STATE_BUSY : stm32wbxx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_RX : stm32wbxx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_RX_LISTEN : stm32wbxx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_TX : stm32wbxx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_TX_LISTEN : stm32wbxx_hal_i2c.h
  • HAL_I2C_STATE_ERROR : stm32wbxx_hal_i2c.h
  • HAL_I2C_STATE_LISTEN : stm32wbxx_hal_i2c.h
  • HAL_I2C_STATE_READY : stm32wbxx_hal_i2c.h
  • HAL_I2C_STATE_RESET : stm32wbxx_hal_i2c.h
  • HAL_I2C_STATE_TIMEOUT : stm32wbxx_hal_i2c.h
  • HAL_IPCC_STATE_BUSY : stm32wbxx_hal_ipcc.h
  • HAL_IPCC_STATE_READY : stm32wbxx_hal_ipcc.h
  • HAL_IPCC_STATE_RESET : stm32wbxx_hal_ipcc.h
  • HAL_IRDA_ABORT_COMPLETE_CB_ID : stm32wbxx_hal_irda.h
  • HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID : stm32wbxx_hal_irda.h
  • HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID : stm32wbxx_hal_irda.h
  • HAL_IRDA_ERROR_CB_ID : stm32wbxx_hal_irda.h
  • HAL_IRDA_MSPDEINIT_CB_ID : stm32wbxx_hal_irda.h
  • HAL_IRDA_MSPINIT_CB_ID : stm32wbxx_hal_irda.h
  • HAL_IRDA_RX_COMPLETE_CB_ID : stm32wbxx_hal_irda.h
  • HAL_IRDA_RX_HALFCOMPLETE_CB_ID : stm32wbxx_hal_irda.h
  • HAL_IRDA_TX_COMPLETE_CB_ID : stm32wbxx_hal_irda.h
  • HAL_IRDA_TX_HALFCOMPLETE_CB_ID : stm32wbxx_hal_irda.h
  • HAL_LCD_STATE_BUSY : stm32wbxx_hal_lcd.h
  • HAL_LCD_STATE_ERROR : stm32wbxx_hal_lcd.h
  • HAL_LCD_STATE_READY : stm32wbxx_hal_lcd.h
  • HAL_LCD_STATE_RESET : stm32wbxx_hal_lcd.h
  • HAL_LCD_STATE_TIMEOUT : stm32wbxx_hal_lcd.h
  • HAL_LPTIM_AUTORELOAD_MATCH_CB_ID : stm32wbxx_hal_lptim.h
  • HAL_LPTIM_AUTORELOAD_WRITE_CB_ID : stm32wbxx_hal_lptim.h
  • HAL_LPTIM_COMPARE_MATCH_CB_ID : stm32wbxx_hal_lptim.h
  • HAL_LPTIM_COMPARE_WRITE_CB_ID : stm32wbxx_hal_lptim.h
  • HAL_LPTIM_DIRECTION_DOWN_CB_ID : stm32wbxx_hal_lptim.h
  • HAL_LPTIM_DIRECTION_UP_CB_ID : stm32wbxx_hal_lptim.h
  • HAL_LPTIM_MSPDEINIT_CB_ID : stm32wbxx_hal_lptim.h
  • HAL_LPTIM_MSPINIT_CB_ID : stm32wbxx_hal_lptim.h
  • HAL_LPTIM_STATE_BUSY : stm32wbxx_hal_lptim.h
  • HAL_LPTIM_STATE_ERROR : stm32wbxx_hal_lptim.h
  • HAL_LPTIM_STATE_READY : stm32wbxx_hal_lptim.h
  • HAL_LPTIM_STATE_RESET : stm32wbxx_hal_lptim.h
  • HAL_LPTIM_STATE_TIMEOUT : stm32wbxx_hal_lptim.h
  • HAL_LPTIM_TRIGGER_CB_ID : stm32wbxx_hal_lptim.h
  • HAL_PCD_CONNECT_CB_ID : stm32wbxx_hal_pcd.h
  • HAL_PCD_DISCONNECT_CB_ID : stm32wbxx_hal_pcd.h
  • HAL_PCD_MSPDEINIT_CB_ID : stm32wbxx_hal_pcd.h
  • HAL_PCD_MSPINIT_CB_ID : stm32wbxx_hal_pcd.h
  • HAL_PCD_RESET_CB_ID : stm32wbxx_hal_pcd.h
  • HAL_PCD_RESUME_CB_ID : stm32wbxx_hal_pcd.h
  • HAL_PCD_SETUPSTAGE_CB_ID : stm32wbxx_hal_pcd.h
  • HAL_PCD_SOF_CB_ID : stm32wbxx_hal_pcd.h
  • HAL_PCD_STATE_BUSY : stm32wbxx_hal_pcd.h
  • HAL_PCD_STATE_ERROR : stm32wbxx_hal_pcd.h
  • HAL_PCD_STATE_READY : stm32wbxx_hal_pcd.h
  • HAL_PCD_STATE_RESET : stm32wbxx_hal_pcd.h
  • HAL_PCD_STATE_TIMEOUT : stm32wbxx_hal_pcd.h
  • HAL_PCD_SUSPEND_CB_ID : stm32wbxx_hal_pcd.h
  • HAL_PKA_ERROR_CB_ID : stm32wbxx_hal_pka.h
  • HAL_PKA_MSPDEINIT_CB_ID : stm32wbxx_hal_pka.h
  • HAL_PKA_MSPINIT_CB_ID : stm32wbxx_hal_pka.h
  • HAL_PKA_OPERATION_COMPLETE_CB_ID : stm32wbxx_hal_pka.h
  • HAL_PKA_STATE_BUSY : stm32wbxx_hal_pka.h
  • HAL_PKA_STATE_ERROR : stm32wbxx_hal_pka.h
  • HAL_PKA_STATE_READY : stm32wbxx_hal_pka.h
  • HAL_PKA_STATE_RESET : stm32wbxx_hal_pka.h
  • HAL_QSPI_ABORT_CB_ID : stm32wbxx_hal_qspi.h
  • HAL_QSPI_CMD_CPLT_CB_ID : stm32wbxx_hal_qspi.h
  • HAL_QSPI_ERROR_CB_ID : stm32wbxx_hal_qspi.h
  • HAL_QSPI_FIFO_THRESHOLD_CB_ID : stm32wbxx_hal_qspi.h
  • HAL_QSPI_MSP_DEINIT_CB_ID : stm32wbxx_hal_qspi.h
  • HAL_QSPI_MSP_INIT_CB_ID : stm32wbxx_hal_qspi.h
  • HAL_QSPI_RX_CPLT_CB_ID : stm32wbxx_hal_qspi.h
  • HAL_QSPI_RX_HALF_CPLT_CB_ID : stm32wbxx_hal_qspi.h
  • HAL_QSPI_STATE_ABORT : stm32wbxx_hal_qspi.h
  • HAL_QSPI_STATE_BUSY : stm32wbxx_hal_qspi.h
  • HAL_QSPI_STATE_BUSY_AUTO_POLLING : stm32wbxx_hal_qspi.h
  • HAL_QSPI_STATE_BUSY_INDIRECT_RX : stm32wbxx_hal_qspi.h
  • HAL_QSPI_STATE_BUSY_INDIRECT_TX : stm32wbxx_hal_qspi.h
  • HAL_QSPI_STATE_BUSY_MEM_MAPPED : stm32wbxx_hal_qspi.h
  • HAL_QSPI_STATE_ERROR : stm32wbxx_hal_qspi.h
  • HAL_QSPI_STATE_READY : stm32wbxx_hal_qspi.h
  • HAL_QSPI_STATE_RESET : stm32wbxx_hal_qspi.h
  • HAL_QSPI_STATUS_MATCH_CB_ID : stm32wbxx_hal_qspi.h
  • HAL_QSPI_TIMEOUT_CB_ID : stm32wbxx_hal_qspi.h
  • HAL_QSPI_TX_CPLT_CB_ID : stm32wbxx_hal_qspi.h
  • HAL_QSPI_TX_HALF_CPLT_CB_ID : stm32wbxx_hal_qspi.h
  • HAL_RNG_ERROR_CB_ID : stm32wbxx_hal_rng.h
  • HAL_RNG_MSPDEINIT_CB_ID : stm32wbxx_hal_rng.h
  • HAL_RNG_MSPINIT_CB_ID : stm32wbxx_hal_rng.h
  • HAL_RNG_STATE_BUSY : stm32wbxx_hal_rng.h
  • HAL_RNG_STATE_ERROR : stm32wbxx_hal_rng.h
  • HAL_RNG_STATE_READY : stm32wbxx_hal_rng.h
  • HAL_RNG_STATE_RESET : stm32wbxx_hal_rng.h
  • HAL_RNG_STATE_TIMEOUT : stm32wbxx_hal_rng.h
  • HAL_RTC_ALARM_A_EVENT_CB_ID : stm32wbxx_hal_rtc.h
  • HAL_RTC_ALARM_B_EVENT_CB_ID : stm32wbxx_hal_rtc.h
  • HAL_RTC_MSPDEINIT_CB_ID : stm32wbxx_hal_rtc.h
  • HAL_RTC_MSPINIT_CB_ID : stm32wbxx_hal_rtc.h
  • HAL_RTC_STATE_BUSY : stm32wbxx_hal_rtc.h
  • HAL_RTC_STATE_ERROR : stm32wbxx_hal_rtc.h
  • HAL_RTC_STATE_READY : stm32wbxx_hal_rtc.h
  • HAL_RTC_STATE_RESET : stm32wbxx_hal_rtc.h
  • HAL_RTC_STATE_TIMEOUT : stm32wbxx_hal_rtc.h
  • HAL_RTC_TAMPER1_EVENT_CB_ID : stm32wbxx_hal_rtc.h
  • HAL_RTC_TAMPER2_EVENT_CB_ID : stm32wbxx_hal_rtc.h
  • HAL_RTC_TAMPER3_EVENT_CB_ID : stm32wbxx_hal_rtc.h
  • HAL_RTC_TIMESTAMP_EVENT_CB_ID : stm32wbxx_hal_rtc.h
  • HAL_RTC_WAKEUPTIMER_EVENT_CB_ID : stm32wbxx_hal_rtc.h
  • HAL_SAI_ERROR_CB_ID : stm32wbxx_hal_sai.h
  • HAL_SAI_MSPDEINIT_CB_ID : stm32wbxx_hal_sai.h
  • HAL_SAI_MSPINIT_CB_ID : stm32wbxx_hal_sai.h
  • HAL_SAI_RX_COMPLETE_CB_ID : stm32wbxx_hal_sai.h
  • HAL_SAI_RX_HALFCOMPLETE_CB_ID : stm32wbxx_hal_sai.h
  • HAL_SAI_STATE_BUSY : stm32wbxx_hal_sai.h
  • HAL_SAI_STATE_BUSY_RX : stm32wbxx_hal_sai.h
  • HAL_SAI_STATE_BUSY_TX : stm32wbxx_hal_sai.h
  • HAL_SAI_STATE_READY : stm32wbxx_hal_sai.h
  • HAL_SAI_STATE_RESET : stm32wbxx_hal_sai.h
  • HAL_SAI_TX_COMPLETE_CB_ID : stm32wbxx_hal_sai.h
  • HAL_SAI_TX_HALFCOMPLETE_CB_ID : stm32wbxx_hal_sai.h
  • HAL_SMARTCARD_ABORT_COMPLETE_CB_ID : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_CB_ID : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_MSPDEINIT_CB_ID : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_MSPINIT_CB_ID : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_RX_COMPLETE_CB_ID : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_RX_FIFO_FULL_CB_ID : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_TX_COMPLETE_CB_ID : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID : stm32wbxx_hal_smartcard.h
  • HAL_SMBUS_ERROR_CB_ID : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_LISTEN_COMPLETE_CB_ID : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_MSPDEINIT_CB_ID : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_MSPINIT_CB_ID : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID : stm32wbxx_hal_smbus.h
  • HAL_SPI_ABORT_CB_ID : stm32wbxx_hal_spi.h
  • HAL_SPI_ERROR_CB_ID : stm32wbxx_hal_spi.h
  • HAL_SPI_MSPDEINIT_CB_ID : stm32wbxx_hal_spi.h
  • HAL_SPI_MSPINIT_CB_ID : stm32wbxx_hal_spi.h
  • HAL_SPI_RX_COMPLETE_CB_ID : stm32wbxx_hal_spi.h
  • HAL_SPI_RX_HALF_COMPLETE_CB_ID : stm32wbxx_hal_spi.h
  • HAL_SPI_STATE_ABORT : stm32wbxx_hal_spi.h
  • HAL_SPI_STATE_BUSY : stm32wbxx_hal_spi.h
  • HAL_SPI_STATE_BUSY_RX : stm32wbxx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX : stm32wbxx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX_RX : stm32wbxx_hal_spi.h
  • HAL_SPI_STATE_ERROR : stm32wbxx_hal_spi.h
  • HAL_SPI_STATE_READY : stm32wbxx_hal_spi.h
  • HAL_SPI_STATE_RESET : stm32wbxx_hal_spi.h
  • HAL_SPI_TX_COMPLETE_CB_ID : stm32wbxx_hal_spi.h
  • HAL_SPI_TX_HALF_COMPLETE_CB_ID : stm32wbxx_hal_spi.h
  • HAL_SPI_TX_RX_COMPLETE_CB_ID : stm32wbxx_hal_spi.h
  • HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : stm32wbxx_hal_spi.h
  • HAL_TIM_ACTIVE_CHANNEL_1 : stm32wbxx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_2 : stm32wbxx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_3 : stm32wbxx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_4 : stm32wbxx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_5 : stm32wbxx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_6 : stm32wbxx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_CLEARED : stm32wbxx_hal_tim.h
  • HAL_TIM_BASE_MSPDEINIT_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_BASE_MSPINIT_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_BREAK2_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_BREAK_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_COMMUTATION_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_COMMUTATION_HALF_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_ENCODER_MSPDEINIT_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_ENCODER_MSPINIT_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_ERROR_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_IC_CAPTURE_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_IC_CAPTURE_HALF_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_IC_MSPDEINIT_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_IC_MSPINIT_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_OC_DELAY_ELAPSED_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_OC_MSPDEINIT_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_OC_MSPINIT_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_PERIOD_ELAPSED_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_PWM_MSPDEINIT_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_PWM_MSPINIT_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_PWM_PULSE_FINISHED_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_STATE_BUSY : stm32wbxx_hal_tim.h
  • HAL_TIM_STATE_ERROR : stm32wbxx_hal_tim.h
  • HAL_TIM_STATE_READY : stm32wbxx_hal_tim.h
  • HAL_TIM_STATE_RESET : stm32wbxx_hal_tim.h
  • HAL_TIM_STATE_TIMEOUT : stm32wbxx_hal_tim.h
  • HAL_TIM_TRIGGER_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TIM_TRIGGER_HALF_CB_ID : stm32wbxx_hal_tim.h
  • HAL_TSC_CONV_COMPLETE_CB_ID : stm32wbxx_hal_tsc.h
  • HAL_TSC_ERROR_CB_ID : stm32wbxx_hal_tsc.h
  • HAL_TSC_MSPDEINIT_CB_ID : stm32wbxx_hal_tsc.h
  • HAL_TSC_MSPINIT_CB_ID : stm32wbxx_hal_tsc.h
  • HAL_TSC_STATE_BUSY : stm32wbxx_hal_tsc.h
  • HAL_TSC_STATE_ERROR : stm32wbxx_hal_tsc.h
  • HAL_TSC_STATE_READY : stm32wbxx_hal_tsc.h
  • HAL_TSC_STATE_RESET : stm32wbxx_hal_tsc.h
  • HAL_UART_ABORT_COMPLETE_CB_ID : stm32wbxx_hal_uart.h
  • HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : stm32wbxx_hal_uart.h
  • HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : stm32wbxx_hal_uart.h
  • HAL_UART_ERROR_CB_ID : stm32wbxx_hal_uart.h
  • HAL_UART_MSPDEINIT_CB_ID : stm32wbxx_hal_uart.h
  • HAL_UART_MSPINIT_CB_ID : stm32wbxx_hal_uart.h
  • HAL_UART_RX_COMPLETE_CB_ID : stm32wbxx_hal_uart.h
  • HAL_UART_RX_FIFO_FULL_CB_ID : stm32wbxx_hal_uart.h
  • HAL_UART_RX_HALFCOMPLETE_CB_ID : stm32wbxx_hal_uart.h
  • HAL_UART_TX_COMPLETE_CB_ID : stm32wbxx_hal_uart.h
  • HAL_UART_TX_FIFO_EMPTY_CB_ID : stm32wbxx_hal_uart.h
  • HAL_UART_TX_HALFCOMPLETE_CB_ID : stm32wbxx_hal_uart.h
  • HAL_UART_WAKEUP_CB_ID : stm32wbxx_hal_uart.h
  • HAL_USART_ABORT_COMPLETE_CB_ID : stm32wbxx_hal_usart.h
  • HAL_USART_ERROR_CB_ID : stm32wbxx_hal_usart.h
  • HAL_USART_MSPDEINIT_CB_ID : stm32wbxx_hal_usart.h
  • HAL_USART_MSPINIT_CB_ID : stm32wbxx_hal_usart.h
  • HAL_USART_RX_COMPLETE_CB_ID : stm32wbxx_hal_usart.h
  • HAL_USART_RX_FIFO_FULL_CB_ID : stm32wbxx_hal_usart.h
  • HAL_USART_RX_HALFCOMPLETE_CB_ID : stm32wbxx_hal_usart.h
  • HAL_USART_STATE_BUSY : stm32wbxx_hal_usart.h
  • HAL_USART_STATE_BUSY_RX : stm32wbxx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX : stm32wbxx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX_RX : stm32wbxx_hal_usart.h
  • HAL_USART_STATE_ERROR : stm32wbxx_hal_usart.h
  • HAL_USART_STATE_READY : stm32wbxx_hal_usart.h
  • HAL_USART_STATE_RESET : stm32wbxx_hal_usart.h
  • HAL_USART_STATE_TIMEOUT : stm32wbxx_hal_usart.h
  • HAL_USART_TX_COMPLETE_CB_ID : stm32wbxx_hal_usart.h
  • HAL_USART_TX_FIFO_EMPTY_CB_ID : stm32wbxx_hal_usart.h
  • HAL_USART_TX_HALFCOMPLETE_CB_ID : stm32wbxx_hal_usart.h
  • HAL_USART_TX_RX_COMPLETE_CB_ID : stm32wbxx_hal_usart.h
  • HAL_WWDG_EWI_CB_ID : stm32wbxx_hal_wwdg.h
  • HAL_WWDG_MSPINIT_CB_ID : stm32wbxx_hal_wwdg.h
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STM32WB55xx HAL User Manual: Globals

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- i -

  • IPCC_CHANNEL_DIR_RX : stm32wbxx_hal_ipcc.h
  • IPCC_CHANNEL_DIR_TX : stm32wbxx_hal_ipcc.h
  • IPCC_CHANNEL_STATUS_FREE : stm32wbxx_hal_ipcc.h
  • IPCC_CHANNEL_STATUS_OCCUPIED : stm32wbxx_hal_ipcc.h
  • IRDA_CLOCKSOURCE_HSI : stm32wbxx_hal_irda.h
  • IRDA_CLOCKSOURCE_LSE : stm32wbxx_hal_irda.h
  • IRDA_CLOCKSOURCE_PCLK2 : stm32wbxx_hal_irda.h
  • IRDA_CLOCKSOURCE_SYSCLK : stm32wbxx_hal_irda.h
  • IRDA_CLOCKSOURCE_UNDEFINED : stm32wbxx_hal_irda.h
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STM32WB55xx HAL User Manual: Globals

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- l -

  • LPM_L0 : stm32wbxx_hal_pcd.h
  • LPM_L1 : stm32wbxx_hal_pcd.h
  • LPM_L2 : stm32wbxx_hal_pcd.h
  • LPM_L3 : stm32wbxx_hal_pcd.h
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STM32WB55xx HAL User Manual: Globals

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- p -

  • PCD_BCD_CHARGING_DOWNSTREAM_PORT : stm32wbxx_hal_pcd.h
  • PCD_BCD_CONTACT_DETECTION : stm32wbxx_hal_pcd.h
  • PCD_BCD_DEDICATED_CHARGING_PORT : stm32wbxx_hal_pcd.h
  • PCD_BCD_DISCOVERY_COMPLETED : stm32wbxx_hal_pcd.h
  • PCD_BCD_ERROR : stm32wbxx_hal_pcd.h
  • PCD_BCD_STD_DOWNSTREAM_PORT : stm32wbxx_hal_pcd.h
  • PCD_LPM_L0_ACTIVE : stm32wbxx_hal_pcd.h
  • PCD_LPM_L1_ACTIVE : stm32wbxx_hal_pcd.h
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STM32WB55xx HAL User Manual: Globals

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- s -

  • SAI_MODE_DMA : stm32wbxx_hal_sai.c
  • SAI_MODE_IT : stm32wbxx_hal_sai.c
  • SMARTCARD_CLOCKSOURCE_HSI : stm32wbxx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_LSE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_PCLK2 : stm32wbxx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_SYSCLK : stm32wbxx_hal_smartcard.h
  • SMARTCARD_CLOCKSOURCE_UNDEFINED : stm32wbxx_hal_smartcard.h
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STM32WB55xx HAL User Manual: Globals

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- t -

  • TSC_GROUP1_IDX : stm32wbxx_hal_tsc.h
  • TSC_GROUP2_IDX : stm32wbxx_hal_tsc.h
  • TSC_GROUP3_IDX : stm32wbxx_hal_tsc.h
  • TSC_GROUP4_IDX : stm32wbxx_hal_tsc.h
  • TSC_GROUP5_IDX : stm32wbxx_hal_tsc.h
  • TSC_GROUP6_IDX : stm32wbxx_hal_tsc.h
  • TSC_GROUP7_IDX : stm32wbxx_hal_tsc.h
  • TSC_GROUP_COMPLETED : stm32wbxx_hal_tsc.h
  • TSC_GROUP_ONGOING : stm32wbxx_hal_tsc.h
  • TSC_NB_OF_GROUPS : stm32wbxx_hal_tsc.h
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STM32WB55xx HAL User Manual: Globals

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- u -

  • UART_CLOCKSOURCE_HSI : stm32wbxx_hal_uart.h
  • UART_CLOCKSOURCE_LSE : stm32wbxx_hal_uart.h
  • UART_CLOCKSOURCE_PCLK1 : stm32wbxx_hal_uart.h
  • UART_CLOCKSOURCE_PCLK2 : stm32wbxx_hal_uart.h
  • UART_CLOCKSOURCE_SYSCLK : stm32wbxx_hal_uart.h
  • UART_CLOCKSOURCE_UNDEFINED : stm32wbxx_hal_uart.h
  • USART_CLOCKSOURCE_HSI : stm32wbxx_hal_usart.h
  • USART_CLOCKSOURCE_LSE : stm32wbxx_hal_usart.h
  • USART_CLOCKSOURCE_PCLK2 : stm32wbxx_hal_usart.h
  • USART_CLOCKSOURCE_SYSCLK : stm32wbxx_hal_usart.h
  • USART_CLOCKSOURCE_UNDEFINED : stm32wbxx_hal_usart.h
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STM32WB55xx HAL User Manual: Globals

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- _ -

  • __ADC_PTR_REG_OFFSET : stm32wbxx_ll_adc.h
  • __COUNTOF : stm32wbxx_hal_rcc.c
  • __HAL_ADC_CALC_DATA_TO_VOLTAGE : stm32wbxx_hal_adc.h
  • __HAL_ADC_CALC_TEMPERATURE : stm32wbxx_hal_adc.h
  • __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS : stm32wbxx_hal_adc.h
  • __HAL_ADC_CALC_VREFANALOG_VOLTAGE : stm32wbxx_hal_adc.h
  • __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL : stm32wbxx_hal_adc.h
  • __HAL_ADC_CHANNEL_TO_DECIMAL_NB : stm32wbxx_hal_adc.h
  • __HAL_ADC_CLEAR_FLAG : stm32wbxx_hal_adc.h
  • __HAL_ADC_COMMON_INSTANCE : stm32wbxx_hal_adc.h
  • __HAL_ADC_CONVERT_DATA_RESOLUTION : stm32wbxx_hal_adc.h
  • __HAL_ADC_DECIMAL_NB_TO_CHANNEL : stm32wbxx_hal_adc.h
  • __HAL_ADC_DIGITAL_SCALE : stm32wbxx_hal_adc.h
  • __HAL_ADC_DISABLE_IT : stm32wbxx_hal_adc.h
  • __HAL_ADC_ENABLE_IT : stm32wbxx_hal_adc.h
  • __HAL_ADC_GET_FLAG : stm32wbxx_hal_adc.h
  • __HAL_ADC_GET_IT_SOURCE : stm32wbxx_hal_adc.h
  • __HAL_ADC_IS_CHANNEL_INTERNAL : stm32wbxx_hal_adc.h
  • __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE : stm32wbxx_hal_adc.h
  • __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE : stm32wbxx_hal_adc.h
  • __HAL_ADC_RESET_HANDLE_STATE : stm32wbxx_hal_adc.h
  • __HAL_C2_DBGMCU_FREEZE_I2C1_TIMEOUT : stm32wbxx_hal.h
  • __HAL_C2_DBGMCU_FREEZE_I2C3_TIMEOUT : stm32wbxx_hal.h
  • __HAL_C2_DBGMCU_FREEZE_IWDG : stm32wbxx_hal.h
  • __HAL_C2_DBGMCU_FREEZE_LPTIM1 : stm32wbxx_hal.h
  • __HAL_C2_DBGMCU_FREEZE_LPTIM2 : stm32wbxx_hal.h
  • __HAL_C2_DBGMCU_FREEZE_RTC : stm32wbxx_hal.h
  • __HAL_C2_DBGMCU_FREEZE_TIM1 : stm32wbxx_hal.h
  • __HAL_C2_DBGMCU_FREEZE_TIM16 : stm32wbxx_hal.h
  • __HAL_C2_DBGMCU_FREEZE_TIM17 : stm32wbxx_hal.h
  • __HAL_C2_DBGMCU_FREEZE_TIM2 : stm32wbxx_hal.h
  • __HAL_C2_DBGMCU_UNFREEZE_I2C1_TIMEOUT : stm32wbxx_hal.h
  • __HAL_C2_DBGMCU_UNFREEZE_I2C3_TIMEOUT : stm32wbxx_hal.h
  • __HAL_C2_DBGMCU_UNFREEZE_IWDG : stm32wbxx_hal.h
  • __HAL_C2_DBGMCU_UNFREEZE_LPTIM1 : stm32wbxx_hal.h
  • __HAL_C2_DBGMCU_UNFREEZE_LPTIM2 : stm32wbxx_hal.h
  • __HAL_C2_DBGMCU_UNFREEZE_RTC : stm32wbxx_hal.h
  • __HAL_C2_DBGMCU_UNFREEZE_TIM1 : stm32wbxx_hal.h
  • __HAL_C2_DBGMCU_UNFREEZE_TIM16 : stm32wbxx_hal.h
  • __HAL_C2_DBGMCU_UNFREEZE_TIM17 : stm32wbxx_hal.h
  • __HAL_C2_DBGMCU_UNFREEZE_TIM2 : stm32wbxx_hal.h
  • __HAL_C2_PWR_WAKEUP_802_15_4 : stm32wbxx_hal_pwr_ex.h
  • __HAL_C2_PWR_WAKEUP_BLE : stm32wbxx_hal_pwr_ex.h
  • __HAL_C2_RCC_LSECSS_EXTI_DISABLE_EVENT : stm32wbxx_hal_rcc_ex.h
  • __HAL_C2_RCC_LSECSS_EXTI_DISABLE_IT : stm32wbxx_hal_rcc_ex.h
  • __HAL_C2_RCC_LSECSS_EXTI_ENABLE_EVENT : stm32wbxx_hal_rcc_ex.h
  • __HAL_C2_RCC_LSECSS_EXTI_ENABLE_IT : stm32wbxx_hal_rcc_ex.h
  • __HAL_COMP_COMP1_EXTI_CLEAR_FLAG : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_EVENT : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_IT : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_EVENT : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_IT : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_GENERATE_SWIT : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP1_EXTI_GET_FLAG : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_CLEAR_FLAG : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_EVENT : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_IT : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_EVENT : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_IT : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_GENERATE_SWIT : stm32wbxx_hal_comp.h
  • __HAL_COMP_COMP2_EXTI_GET_FLAG : stm32wbxx_hal_comp.h
  • __HAL_COMP_DISABLE : stm32wbxx_hal_comp.h
  • __HAL_COMP_ENABLE : stm32wbxx_hal_comp.h
  • __HAL_COMP_IS_LOCKED : stm32wbxx_hal_comp.h
  • __HAL_COMP_LOCK : stm32wbxx_hal_comp.h
  • __HAL_COMP_RESET_HANDLE_STATE : stm32wbxx_hal_comp.h
  • __HAL_CRC_DR_RESET : stm32wbxx_hal_crc.h
  • __HAL_CRC_GET_IDR : stm32wbxx_hal_crc.h
  • __HAL_CRC_INITIALCRCVALUE_CONFIG : stm32wbxx_hal_crc.h
  • __HAL_CRC_OUTPUTREVERSAL_DISABLE : stm32wbxx_hal_crc_ex.h
  • __HAL_CRC_OUTPUTREVERSAL_ENABLE : stm32wbxx_hal_crc_ex.h
  • __HAL_CRC_POLYNOMIAL_CONFIG : stm32wbxx_hal_crc_ex.h
  • __HAL_CRC_RESET_HANDLE_STATE : stm32wbxx_hal_crc.h
  • __HAL_CRC_SET_IDR : stm32wbxx_hal_crc.h
  • __HAL_CRYP_CLEAR_FLAG : stm32wbxx_hal_cryp.h
  • __HAL_CRYP_DISABLE : stm32wbxx_hal_cryp.h
  • __HAL_CRYP_DISABLE_IT : stm32wbxx_hal_cryp.h
  • __HAL_CRYP_ENABLE : stm32wbxx_hal_cryp.h
  • __HAL_CRYP_ENABLE_IT : stm32wbxx_hal_cryp.h
  • __HAL_CRYP_GET_FLAG : stm32wbxx_hal_cryp.h
  • __HAL_CRYP_GET_IT : stm32wbxx_hal_cryp.h
  • __HAL_CRYP_GET_IT_SOURCE : stm32wbxx_hal_cryp.h
  • __HAL_CRYP_RESET_HANDLE_STATE : stm32wbxx_hal_cryp.h
  • __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT : stm32wbxx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT : stm32wbxx_hal.h
  • __HAL_DBGMCU_FREEZE_IWDG : stm32wbxx_hal.h
  • __HAL_DBGMCU_FREEZE_LPTIM1 : stm32wbxx_hal.h
  • __HAL_DBGMCU_FREEZE_LPTIM2 : stm32wbxx_hal.h
  • __HAL_DBGMCU_FREEZE_RTC : stm32wbxx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM1 : stm32wbxx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM16 : stm32wbxx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM17 : stm32wbxx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM2 : stm32wbxx_hal.h
  • __HAL_DBGMCU_FREEZE_WWDG : stm32wbxx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT : stm32wbxx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT : stm32wbxx_hal.h
  • __HAL_DBGMCU_UNFREEZE_IWDG : stm32wbxx_hal.h
  • __HAL_DBGMCU_UNFREEZE_LPTIM1 : stm32wbxx_hal.h
  • __HAL_DBGMCU_UNFREEZE_LPTIM2 : stm32wbxx_hal.h
  • __HAL_DBGMCU_UNFREEZE_RTC : stm32wbxx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM1 : stm32wbxx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM16 : stm32wbxx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM17 : stm32wbxx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM2 : stm32wbxx_hal.h
  • __HAL_DBGMCU_UNFREEZE_WWDG : stm32wbxx_hal.h
  • __HAL_DMA_CLEAR_FLAG : stm32wbxx_hal_dma.h
  • __HAL_DMA_DISABLE : stm32wbxx_hal_dma.h
  • __HAL_DMA_DISABLE_IT : stm32wbxx_hal_dma.h
  • __HAL_DMA_ENABLE : stm32wbxx_hal_dma.h
  • __HAL_DMA_ENABLE_IT : stm32wbxx_hal_dma.h
  • __HAL_DMA_GET_COUNTER : stm32wbxx_hal_dma.h
  • __HAL_DMA_GET_FLAG : stm32wbxx_hal_dma.h
  • __HAL_DMA_GET_GI_FLAG_INDEX : stm32wbxx_hal_dma.h
  • __HAL_DMA_GET_HT_FLAG_INDEX : stm32wbxx_hal_dma.h
  • __HAL_DMA_GET_IT_SOURCE : stm32wbxx_hal_dma.h
  • __HAL_DMA_GET_TC_FLAG_INDEX : stm32wbxx_hal_dma.h
  • __HAL_DMA_GET_TE_FLAG_INDEX : stm32wbxx_hal_dma.h
  • __HAL_DMA_RESET_HANDLE_STATE : stm32wbxx_hal_dma.h
  • __HAL_FLASH_CLEAR_FLAG : stm32wbxx_hal_flash.h
  • __HAL_FLASH_DATA_CACHE_DISABLE : stm32wbxx_hal_flash.h
  • __HAL_FLASH_DATA_CACHE_ENABLE : stm32wbxx_hal_flash.h
  • __HAL_FLASH_DATA_CACHE_RESET : stm32wbxx_hal_flash.h
  • __HAL_FLASH_DISABLE_IT : stm32wbxx_hal_flash.h
  • __HAL_FLASH_ENABLE_IT : stm32wbxx_hal_flash.h
  • __HAL_FLASH_GET_FLAG : stm32wbxx_hal_flash.h
  • __HAL_FLASH_GET_LATENCY : stm32wbxx_hal_flash.h
  • __HAL_FLASH_INSTRUCTION_CACHE_DISABLE : stm32wbxx_hal_flash.h
  • __HAL_FLASH_INSTRUCTION_CACHE_ENABLE : stm32wbxx_hal_flash.h
  • __HAL_FLASH_INSTRUCTION_CACHE_RESET : stm32wbxx_hal_flash.h
  • __HAL_FLASH_PREFETCH_BUFFER_DISABLE : stm32wbxx_hal_flash.h
  • __HAL_FLASH_PREFETCH_BUFFER_ENABLE : stm32wbxx_hal_flash.h
  • __HAL_FLASH_SET_LATENCY : stm32wbxx_hal_flash.h
  • __HAL_GPIO_EXTI_CLEAR_FLAG : stm32wbxx_hal_gpio.h
  • __HAL_GPIO_EXTI_CLEAR_IT : stm32wbxx_hal_gpio.h
  • __HAL_GPIO_EXTI_GENERATE_SWIT : stm32wbxx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_FLAG : stm32wbxx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_IT : stm32wbxx_hal_gpio.h
  • __HAL_HSEM_CLEAR_FLAG : stm32wbxx_hal_hsem.h
  • __HAL_HSEM_DISABLE_IT : stm32wbxx_hal_hsem.h
  • __HAL_HSEM_ENABLE_IT : stm32wbxx_hal_hsem.h
  • __HAL_HSEM_GET_FLAG : stm32wbxx_hal_hsem.h
  • __HAL_HSEM_GET_IT : stm32wbxx_hal_hsem.h
  • __HAL_HSEM_SEMID_TO_MASK : stm32wbxx_hal_hsem.h
  • __HAL_I2C_CLEAR_FLAG : stm32wbxx_hal_i2c.h
  • __HAL_I2C_DISABLE : stm32wbxx_hal_i2c.h
  • __HAL_I2C_DISABLE_IT : stm32wbxx_hal_i2c.h
  • __HAL_I2C_ENABLE : stm32wbxx_hal_i2c.h
  • __HAL_I2C_ENABLE_IT : stm32wbxx_hal_i2c.h
  • __HAL_I2C_GENERATE_NACK : stm32wbxx_hal_i2c.h
  • __HAL_I2C_GET_FLAG : stm32wbxx_hal_i2c.h
  • __HAL_I2C_GET_IT_SOURCE : stm32wbxx_hal_i2c.h
  • __HAL_I2C_RESET_HANDLE_STATE : stm32wbxx_hal_i2c.h
  • __HAL_IPCC_DISABLE_IT : stm32wbxx_hal_ipcc.h
  • __HAL_IPCC_ENABLE_IT : stm32wbxx_hal_ipcc.h
  • __HAL_IPCC_MASK_CHANNEL_IT : stm32wbxx_hal_ipcc.h
  • __HAL_IPCC_UNMASK_CHANNEL_IT : stm32wbxx_hal_ipcc.h
  • __HAL_IRDA_CLEAR_FEFLAG : stm32wbxx_hal_irda.h
  • __HAL_IRDA_CLEAR_FLAG : stm32wbxx_hal_irda.h
  • __HAL_IRDA_CLEAR_IDLEFLAG : stm32wbxx_hal_irda.h
  • __HAL_IRDA_CLEAR_IT : stm32wbxx_hal_irda.h
  • __HAL_IRDA_CLEAR_NEFLAG : stm32wbxx_hal_irda.h
  • __HAL_IRDA_CLEAR_OREFLAG : stm32wbxx_hal_irda.h
  • __HAL_IRDA_CLEAR_PEFLAG : stm32wbxx_hal_irda.h
  • __HAL_IRDA_DISABLE : stm32wbxx_hal_irda.h
  • __HAL_IRDA_DISABLE_IT : stm32wbxx_hal_irda.h
  • __HAL_IRDA_ENABLE : stm32wbxx_hal_irda.h
  • __HAL_IRDA_ENABLE_IT : stm32wbxx_hal_irda.h
  • __HAL_IRDA_FLUSH_DRREGISTER : stm32wbxx_hal_irda.h
  • __HAL_IRDA_GET_FLAG : stm32wbxx_hal_irda.h
  • __HAL_IRDA_GET_IT : stm32wbxx_hal_irda.h
  • __HAL_IRDA_GET_IT_SOURCE : stm32wbxx_hal_irda.h
  • __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE : stm32wbxx_hal_irda.h
  • __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE : stm32wbxx_hal_irda.h
  • __HAL_IRDA_RESET_HANDLE_STATE : stm32wbxx_hal_irda.h
  • __HAL_IRDA_SEND_REQ : stm32wbxx_hal_irda.h
  • __HAL_IWDG_RELOAD_COUNTER : stm32wbxx_hal_iwdg.h
  • __HAL_IWDG_START : stm32wbxx_hal_iwdg.h
  • __HAL_LCD_BLINK_CONFIG : stm32wbxx_hal_lcd.h
  • __HAL_LCD_CLEAR_FLAG : stm32wbxx_hal_lcd.h
  • __HAL_LCD_CONTRAST_CONFIG : stm32wbxx_hal_lcd.h
  • __HAL_LCD_DEADTIME_CONFIG : stm32wbxx_hal_lcd.h
  • __HAL_LCD_DISABLE : stm32wbxx_hal_lcd.h
  • __HAL_LCD_DISABLE_IT : stm32wbxx_hal_lcd.h
  • __HAL_LCD_ENABLE : stm32wbxx_hal_lcd.h
  • __HAL_LCD_ENABLE_IT : stm32wbxx_hal_lcd.h
  • __HAL_LCD_GET_FLAG : stm32wbxx_hal_lcd.h
  • __HAL_LCD_GET_IT_SOURCE : stm32wbxx_hal_lcd.h
  • __HAL_LCD_HIGHDRIVER_DISABLE : stm32wbxx_hal_lcd.h
  • __HAL_LCD_HIGHDRIVER_ENABLE : stm32wbxx_hal_lcd.h
  • __HAL_LCD_PULSEONDURATION_CONFIG : stm32wbxx_hal_lcd.h
  • __HAL_LCD_RESET_HANDLE_STATE : stm32wbxx_hal_lcd.h
  • __HAL_LCD_VOLTAGE_BUFFER_DISABLE : stm32wbxx_hal_lcd.h
  • __HAL_LCD_VOLTAGE_BUFFER_ENABLE : stm32wbxx_hal_lcd.h
  • __HAL_LPTIM_AUTORELOAD_SET : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_CLEAR_FLAG : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_COMPARE_SET : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_DISABLE : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_DISABLE_IT : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_ENABLE : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_ENABLE_IT : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_GET_FLAG : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_GET_IT_SOURCE : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_LPTIM1_EXTI_DISABLE_EVENT : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_LPTIM1_EXTI_ENABLE_EVENT : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_LPTIM2_EXTI_DISABLE_EVENT : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_LPTIM2_EXTI_ENABLE_EVENT : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_RESET_COUNTER : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_RESET_COUNTER_AFTERREAD : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_RESET_HANDLE_STATE : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_START_CONTINUOUS : stm32wbxx_hal_lptim.h
  • __HAL_LPTIM_START_SINGLE : stm32wbxx_hal_lptim.h
  • __HAL_PCD_CLEAR_FLAG : stm32wbxx_hal_pcd.h
  • __HAL_PCD_DISABLE : stm32wbxx_hal_pcd.h
  • __HAL_PCD_ENABLE : stm32wbxx_hal_pcd.h
  • __HAL_PCD_GET_FLAG : stm32wbxx_hal_pcd.h
  • __HAL_PKA_CLEAR_FLAG : stm32wbxx_hal_pka.h
  • __HAL_PKA_DISABLE : stm32wbxx_hal_pka.h
  • __HAL_PKA_DISABLE_IT : stm32wbxx_hal_pka.h
  • __HAL_PKA_ENABLE : stm32wbxx_hal_pka.h
  • __HAL_PKA_ENABLE_IT : stm32wbxx_hal_pka.h
  • __HAL_PKA_GET_FLAG : stm32wbxx_hal_pka.h
  • __HAL_PKA_GET_IT_SOURCE : stm32wbxx_hal_pka.h
  • __HAL_PKA_RESET_HANDLE_STATE : stm32wbxx_hal_pka.h
  • __HAL_PKA_START : stm32wbxx_hal_pka.h
  • __HAL_PWR_CLEAR_FLAG : stm32wbxx_hal_pwr.h
  • __HAL_PWR_GET_FLAG : stm32wbxx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_CLEAR_FLAG : stm32wbxx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE : stm32wbxx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_IT : stm32wbxx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE : stm32wbxx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE : stm32wbxx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE : stm32wbxx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_IT : stm32wbxx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE : stm32wbxx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE : stm32wbxx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_GENERATE_SWIT : stm32wbxx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_GET_FLAG : stm32wbxx_hal_pwr.h
  • __HAL_PWR_PVD_EXTIC2_DISABLE_IT : stm32wbxx_hal_pwr.h
  • __HAL_PWR_PVD_EXTIC2_ENABLE_IT : stm32wbxx_hal_pwr.h
  • __HAL_PWR_PVM1_EXTI_CLEAR_FLAG : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_DISABLE_EVENT : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_DISABLE_IT : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_ENABLE_EVENT : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_ENABLE_IT : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_GENERATE_SWIT : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTI_GET_FLAG : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTIC2_DISABLE_EVENT : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTIC2_DISABLE_IT : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTIC2_ENABLE_EVENT : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM1_EXTIC2_ENABLE_IT : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_CLEAR_FLAG : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_DISABLE_EVENT : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_DISABLE_IT : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_ENABLE_EVENT : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_ENABLE_IT : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_GENERATE_SWIT : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTI_GET_FLAG : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTIC2_DISABLE_EVENT : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTIC2_DISABLE_IT : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTIC2_ENABLE_EVENT : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_PVM3_EXTIC2_ENABLE_IT : stm32wbxx_hal_pwr_ex.h
  • __HAL_PWR_VOLTAGESCALING_CONFIG : stm32wbxx_hal_pwr_ex.h
  • __HAL_QSPI_CLEAR_FLAG : stm32wbxx_hal_qspi.h
  • __HAL_QSPI_DISABLE : stm32wbxx_hal_qspi.h
  • __HAL_QSPI_DISABLE_IT : stm32wbxx_hal_qspi.h
  • __HAL_QSPI_ENABLE : stm32wbxx_hal_qspi.h
  • __HAL_QSPI_ENABLE_IT : stm32wbxx_hal_qspi.h
  • __HAL_QSPI_GET_FLAG : stm32wbxx_hal_qspi.h
  • __HAL_QSPI_GET_IT_SOURCE : stm32wbxx_hal_qspi.h
  • __HAL_QSPI_RESET_HANDLE_STATE : stm32wbxx_hal_qspi.h
  • __HAL_RCC_ADC_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_ADC_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_ADC_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_ADC_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_ADC_CONFIG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_ADC_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_ADC_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_ADC_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_ADC_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES1_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES1_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES2_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES2_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES2_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES2_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES2_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES2_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES2_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES2_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES2_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AES2_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AHB1_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AHB1_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AHB2_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AHB2_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AHB3_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_AHB3_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_APB1_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_APB1_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_APB1H_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_APB1H_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_APB1L_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_APB1L_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_APB2_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_APB2_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_APB3_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_APB3_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_BACKUPRESET_FORCE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_BACKUPRESET_RELEASE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2802_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2802_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2802_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2802_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2802_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2802_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2802_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2802_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2ADC_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2ADC_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2ADC_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2ADC_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2ADC_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2ADC_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2ADC_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2ADC_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2AES1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2AES1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2AES1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2AES1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2AES1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2AES1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2AES1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2AES1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2AES2_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2AES2_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2AES2_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2AES2_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2AES2_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2AES2_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2AES2_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2AES2_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2BLE_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2BLE_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2BLE_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2BLE_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2BLE_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2BLE_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2BLE_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2BLE_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2CRC_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2CRC_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2CRC_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2CRC_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2CRC_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2CRC_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2CRC_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2CRC_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2CRS_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2CRS_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2CRS_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2CRS_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2CRS_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2CRS_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2CRS_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2CRS_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMA1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMA1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMA1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMA1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMA1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMA1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMA1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMA1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMA2_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMA2_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMA2_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMA2_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMA2_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMA2_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMA2_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMA2_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMAMUX1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMAMUX1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMAMUX1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMAMUX1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMAMUX1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMAMUX1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMAMUX1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2DMAMUX1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2FLASH_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2FLASH_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2FLASH_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2FLASH_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2FLASH_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2FLASH_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2FLASH_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2FLASH_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOA_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOA_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOA_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOA_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOA_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOA_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOA_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOA_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOB_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOB_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOB_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOB_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOB_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOB_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOB_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOB_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOC_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOC_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOC_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOC_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOC_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOC_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOC_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOC_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOD_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOD_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOD_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOD_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOD_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOD_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOD_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOD_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOE_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOE_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOE_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOE_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOE_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOE_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOE_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOE_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOH_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOH_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOH_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOH_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOH_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOH_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOH_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2GPIOH_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2HSEM_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2HSEM_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2HSEM_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2HSEM_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2I2C1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2I2C1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2I2C1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2I2C1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2I2C1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2I2C1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2I2C1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2I2C1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2I2C3_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2I2C3_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2I2C3_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2I2C3_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2I2C3_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2I2C3_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2I2C3_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2I2C3_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2IPCC_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2IPCC_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2IPCC_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2IPCC_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LCD_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LCD_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LCD_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LCD_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LCD_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LCD_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LCD_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LCD_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPTIM1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPTIM1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPTIM1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPTIM1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPTIM1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPTIM1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPTIM1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPTIM1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPTIM2_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPTIM2_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPTIM2_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPTIM2_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPTIM2_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPTIM2_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPTIM2_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPTIM2_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPUART1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPUART1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPUART1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPUART1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPUART1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPUART1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPUART1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2LPUART1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2PKA_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2PKA_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2PKA_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2PKA_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2PKA_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2PKA_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2PKA_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2PKA_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2RNG_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2RNG_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2RNG_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2RNG_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2RNG_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2RNG_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2RNG_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2RNG_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2RTCAPB_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2RTCAPB_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2RTCAPB_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2RTCAPB_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2RTCAPB_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2RTCAPB_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2RTCAPB_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2RTCAPB_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SAI1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SAI1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SAI1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SAI1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SAI1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SAI1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SAI1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SAI1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SPI1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SPI1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SPI1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SPI1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SPI1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SPI1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SPI1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SPI1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SPI2_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SPI2_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SPI2_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SPI2_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SPI2_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SPI2_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SPI2_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SPI2_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SRAM1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SRAM1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SRAM1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SRAM1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SRAM1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SRAM1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SRAM1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SRAM1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SRAM2_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SRAM2_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SRAM2_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2SRAM2_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM16_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM16_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM16_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM16_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM16_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM16_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM16_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM16_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM17_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM17_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM17_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM17_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM17_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM17_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM17_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM17_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM2_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM2_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM2_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM2_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM2_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM2_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM2_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TIM2_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TSC_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TSC_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TSC_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TSC_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TSC_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TSC_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TSC_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2TSC_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2USART1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2USART1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2USART1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2USART1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2USART1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2USART1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2USART1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2USART1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2USB_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2USB_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2USB_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2USB_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2USB_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2USB_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2USB_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_C2USB_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CLEAR_IT : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CLEAR_RESET_FLAGS : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRC_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRC_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_CRS_CLEAR_FLAG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_CRS_CLEAR_IT : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_CRS_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRS_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRS_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRS_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRS_DISABLE_IT : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_CRS_ENABLE_IT : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_CRS_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_CRS_GET_FLAG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_CRS_GET_IT_SOURCE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_CRS_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRS_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRS_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_CRS_RELOADVALUE_CALCULATE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_DISABLE_IT : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA1_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA1_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA2_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA2_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMA2_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_DMAMUX1_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_ENABLE_IT : stm32wbxx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_FLASH_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_FLASH_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_FLASH_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_FLASH_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_FLASH_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GET_ADC_SOURCE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_GET_FLAG : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GET_I2C1_SOURCE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_GET_I2C3_SOURCE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_GET_IT : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GET_LPTIM1_SOURCE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_GET_LPTIM2_SOURCE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_GET_LPUART1_SOURCE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_GET_MSI_RANGE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GET_PLL_OSCSOURCE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GET_PLLCLKOUT_CONFIG : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_GET_RFWAKEUP_SOURCE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_GET_RNG_SOURCE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_GET_RTC_SOURCE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GET_SAI1_SOURCE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_GET_SMPS_DIV : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_GET_SMPS_SOURCE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_GET_SMPS_SOURCE_STATUS : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_GET_SYSCLK_SOURCE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GET_USART1_SOURCE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_GET_USB_SOURCE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_GPIOA_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOA_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOA_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOB_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOB_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOC_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOC_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOD_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOD_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOE_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOE_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOH_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOH_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOH_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_GPIOH_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSE_AMPCONFIG : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSE_CAPACITORTUNING : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSE_CONFIG : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSE_CURRENTCONFIG : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSE_DIV2_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSE_DIV2_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSEM_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSEM_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSEM_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSEM_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSEM_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSEM_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSI48_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSI48_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSI_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSI_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSIAUTOMATIC_START_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSIAUTOMATIC_START_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSISTOP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_HSISTOP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C1_CONFIG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_I2C1_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C1_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C3_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C3_CONFIG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_I2C3_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_I2C3_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_IPCC_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_IPCC_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_IPCC_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_IPCC_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_IPCC_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_IPCC_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LCD_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LCD_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LCD_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LCD_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LCD_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LCD_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LCD_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LCD_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM1_CONFIG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM1_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM1_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM2_CONFIG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_LPTIM2_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM2_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM2_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPTIM2_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPUART1_CONFIG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_LPUART1_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LPUART1_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LSE_CONFIG : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_DISABLE_IT : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_ENABLE_IT : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_LSECSS_EXTI_GET_FLAG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_LSEDRIVE_CONFIG : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LSI1_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LSI1_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LSI2_CALIBRATIONVALUE_ADJUST : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LSI2_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_LSI2_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_MCO1_CONFIG : stm32wbxx_hal_rcc.h
  • __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST : stm32wbxx_hal_rcc.h
  • __HAL_RCC_MSI_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_MSI_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_MSI_RANGE_CONFIG : stm32wbxx_hal_rcc.h
  • __HAL_RCC_PKA_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_PKA_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_PKA_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_PKA_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_PKA_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_PKA_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_PKA_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_PKA_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_PKA_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_PKA_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_PLL_CONFIG : stm32wbxx_hal_rcc.h
  • __HAL_RCC_PLL_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_PLL_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_PLL_PLLM_CONFIG : stm32wbxx_hal_rcc.h
  • __HAL_RCC_PLL_PLLSOURCE_CONFIG : stm32wbxx_hal_rcc.h
  • __HAL_RCC_PLLCLKOUT_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_PLLCLKOUT_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_PLLSAI1_CLEAR_IT : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_CONFIG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_DISABLE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_DISABLE_IT : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_DIVP_CONFIG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_DIVQ_CONFIG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_DIVR_CONFIG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_ENABLE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_ENABLE_IT : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_GET_FLAG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_GET_IT_SOURCE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1_MULN_CONFIG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1CLKOUT_DISABLE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_PLLSAI1CLKOUT_ENABLE : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_QUADSPI_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_QUADSPI_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_QUADSPI_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_QUADSPI_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_QUADSPI_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_QUADSPI_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RF_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RF_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RFWAKEUP_CONFIG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_RNG_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RNG_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RNG_CONFIG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_RNG_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RNG_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RTC_CONFIG : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RTC_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RTC_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RTCAPB_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RTCAPB_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RTCAPB_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RTCAPB_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SAI1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SAI1_CONFIG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_SAI1_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SAI1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SAI1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SAI1_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SMPS_CONFIG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_SMPS_DIV_CONFIG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_SPI1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SPI1_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SPI1_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SPI2_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SPI2_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_SYSCLK_CONFIG : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM16_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM16_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM16_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM17_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM17_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM17_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM1_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM1_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM2_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TIM2_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TSC_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TSC_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TSC_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TSC_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TSC_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TSC_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TSC_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_TSC_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USART1_CONFIG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_USART1_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USART1_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USB_CLK_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USB_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USB_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USB_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USB_CONFIG : stm32wbxx_hal_rcc_ex.h
  • __HAL_RCC_USB_FORCE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USB_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USB_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_USB_RELEASE_RESET : stm32wbxx_hal_rcc.h
  • __HAL_RCC_WAKEUPSTOP_CLK_CONFIG : stm32wbxx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_SLEEP_DISABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_SLEEP_ENABLE : stm32wbxx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED : stm32wbxx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED : stm32wbxx_hal_rcc.h
  • __HAL_RNG_CLEAR_FLAG : stm32wbxx_hal_rng.h
  • __HAL_RNG_CLEAR_IT : stm32wbxx_hal_rng.h
  • __HAL_RNG_DISABLE : stm32wbxx_hal_rng.h
  • __HAL_RNG_DISABLE_IT : stm32wbxx_hal_rng.h
  • __HAL_RNG_ENABLE : stm32wbxx_hal_rng.h
  • __HAL_RNG_ENABLE_IT : stm32wbxx_hal_rng.h
  • __HAL_RNG_GET_FLAG : stm32wbxx_hal_rng.h
  • __HAL_RNG_GET_IT : stm32wbxx_hal_rng.h
  • __HAL_RNG_RESET_HANDLE_STATE : stm32wbxx_hal_rng.h
  • __HAL_RTC_ALARM_CLEAR_FLAG : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_DISABLE_IT : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_ENABLE_IT : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_CLEAR_FLAG : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_EVENT : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_IT : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_EVENT : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_IT : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_GENERATE_SWIT : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_GET_FLAG : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTIC2_CLEAR_FLAG : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTIC2_DISABLE_EVENT : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTIC2_DISABLE_IT : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTIC2_ENABLE_EVENT : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTIC2_ENABLE_IT : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTIC2_GET_FLAG : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_FLAG : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT_SOURCE : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARMA_DISABLE : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARMA_ENABLE : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARMB_DISABLE : stm32wbxx_hal_rtc.h
  • __HAL_RTC_ALARMB_ENABLE : stm32wbxx_hal_rtc.h
  • __HAL_RTC_CALIBRATION_OUTPUT_DISABLE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_CALIBRATION_OUTPUT_ENABLE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_CLOCKREF_DETECTION_DISABLE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_CLOCKREF_DETECTION_ENABLE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_RESET_HANDLE_STATE : stm32wbxx_hal_rtc.h
  • __HAL_RTC_SHIFT_GET_FLAG : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER1_DISABLE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER1_ENABLE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER2_DISABLE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER2_ENABLE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER3_DISABLE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER3_ENABLE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_CLEAR_FLAG : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_DISABLE_IT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_ENABLE_IT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_FLAG : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT_SOURCE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_CLEAR_FLAG : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_DISABLE_EVENT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_DISABLE_IT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_ENABLE_EVENT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_ENABLE_IT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_GET_FLAG : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_CLEAR_FLAG : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_DISABLE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_DISABLE_IT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_ENABLE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_ENABLE_IT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_FLAG : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_IT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_TIMESTAMP_GET_IT_SOURCE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_DISABLE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_DISABLE_IT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_ENABLE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_ENABLE_IT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTIC2_CLEAR_FLAG : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTIC2_DISABLE_EVENT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTIC2_DISABLE_IT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTIC2_ENABLE_EVENT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTIC2_ENABLE_IT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_EXTIC2_GET_FLAG : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_FLAG : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_IT : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE : stm32wbxx_hal_rtc_ex.h
  • __HAL_RTC_WRITEPROTECTION_DISABLE : stm32wbxx_hal_rtc.h
  • __HAL_RTC_WRITEPROTECTION_ENABLE : stm32wbxx_hal_rtc.h
  • __HAL_SAI_CLEAR_FLAG : stm32wbxx_hal_sai.h
  • __HAL_SAI_DISABLE : stm32wbxx_hal_sai.h
  • __HAL_SAI_DISABLE_IT : stm32wbxx_hal_sai.h
  • __HAL_SAI_ENABLE : stm32wbxx_hal_sai.h
  • __HAL_SAI_ENABLE_IT : stm32wbxx_hal_sai.h
  • __HAL_SAI_GET_FLAG : stm32wbxx_hal_sai.h
  • __HAL_SAI_GET_IT_SOURCE : stm32wbxx_hal_sai.h
  • __HAL_SAI_RESET_HANDLE_STATE : stm32wbxx_hal_sai.h
  • __HAL_SMARTCARD_CLEAR_FEFLAG : stm32wbxx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_FLAG : stm32wbxx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_IDLEFLAG : stm32wbxx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_IT : stm32wbxx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_NEFLAG : stm32wbxx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_OREFLAG : stm32wbxx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_PEFLAG : stm32wbxx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE : stm32wbxx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE_IT : stm32wbxx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE : stm32wbxx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE_IT : stm32wbxx_hal_smartcard.h
  • __HAL_SMARTCARD_FLUSH_DRREGISTER : stm32wbxx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_FLAG : stm32wbxx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_IT : stm32wbxx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_IT_SOURCE : stm32wbxx_hal_smartcard.h
  • __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE : stm32wbxx_hal_smartcard.h
  • __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE : stm32wbxx_hal_smartcard.h
  • __HAL_SMARTCARD_RESET_HANDLE_STATE : stm32wbxx_hal_smartcard.h
  • __HAL_SMARTCARD_SEND_REQ : stm32wbxx_hal_smartcard.h
  • __HAL_SMBUS_CLEAR_FLAG : stm32wbxx_hal_smbus.h
  • __HAL_SMBUS_DISABLE : stm32wbxx_hal_smbus.h
  • __HAL_SMBUS_DISABLE_IT : stm32wbxx_hal_smbus.h
  • __HAL_SMBUS_ENABLE : stm32wbxx_hal_smbus.h
  • __HAL_SMBUS_ENABLE_IT : stm32wbxx_hal_smbus.h
  • __HAL_SMBUS_GENERATE_NACK : stm32wbxx_hal_smbus.h
  • __HAL_SMBUS_GET_FLAG : stm32wbxx_hal_smbus.h
  • __HAL_SMBUS_GET_IT_SOURCE : stm32wbxx_hal_smbus.h
  • __HAL_SMBUS_RESET_HANDLE_STATE : stm32wbxx_hal_smbus.h
  • __HAL_SPI_CLEAR_CRCERRFLAG : stm32wbxx_hal_spi.h
  • __HAL_SPI_CLEAR_FREFLAG : stm32wbxx_hal_spi.h
  • __HAL_SPI_CLEAR_MODFFLAG : stm32wbxx_hal_spi.h
  • __HAL_SPI_CLEAR_OVRFLAG : stm32wbxx_hal_spi.h
  • __HAL_SPI_DISABLE : stm32wbxx_hal_spi.h
  • __HAL_SPI_DISABLE_IT : stm32wbxx_hal_spi.h
  • __HAL_SPI_ENABLE : stm32wbxx_hal_spi.h
  • __HAL_SPI_ENABLE_IT : stm32wbxx_hal_spi.h
  • __HAL_SPI_GET_FLAG : stm32wbxx_hal_spi.h
  • __HAL_SPI_GET_IT_SOURCE : stm32wbxx_hal_spi.h
  • __HAL_SPI_RESET_HANDLE_STATE : stm32wbxx_hal_spi.h
  • __HAL_SYSCFG_BREAK_ECC_LOCK : stm32wbxx_hal.h
  • __HAL_SYSCFG_BREAK_LOCKUP_LOCK : stm32wbxx_hal.h
  • __HAL_SYSCFG_BREAK_PVD_LOCK : stm32wbxx_hal.h
  • __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK : stm32wbxx_hal.h
  • __HAL_SYSCFG_CLEAR_FLAG : stm32wbxx_hal.h
  • __HAL_SYSCFG_FASTMODEPLUS_DISABLE : stm32wbxx_hal.h
  • __HAL_SYSCFG_FASTMODEPLUS_ENABLE : stm32wbxx_hal.h
  • __HAL_SYSCFG_FPU_INTERRUPT_DISABLE : stm32wbxx_hal.h
  • __HAL_SYSCFG_FPU_INTERRUPT_ENABLE : stm32wbxx_hal.h
  • __HAL_SYSCFG_GET_BOOT_MODE : stm32wbxx_hal.h
  • __HAL_SYSCFG_GET_FLAG : stm32wbxx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_FLASH : stm32wbxx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_QUADSPI : stm32wbxx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_SRAM : stm32wbxx_hal.h
  • __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH : stm32wbxx_hal.h
  • __HAL_SYSCFG_SRAM2_ERASE : stm32wbxx_hal.h
  • __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE : stm32wbxx_hal.h
  • __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE : stm32wbxx_hal.h
  • __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE : stm32wbxx_hal.h
  • __HAL_SYSCFG_SRAM2_WRP_UNLOCK : stm32wbxx_hal.h
  • __HAL_TIM_CLEAR_FLAG : stm32wbxx_hal_tim.h
  • __HAL_TIM_CLEAR_IT : stm32wbxx_hal_tim.h
  • __HAL_TIM_DISABLE : stm32wbxx_hal_tim.h
  • __HAL_TIM_DISABLE_DMA : stm32wbxx_hal_tim.h
  • __HAL_TIM_DISABLE_IT : stm32wbxx_hal_tim.h
  • __HAL_TIM_DISABLE_OCxFAST : stm32wbxx_hal_tim.h
  • __HAL_TIM_DISABLE_OCxPRELOAD : stm32wbxx_hal_tim.h
  • __HAL_TIM_ENABLE : stm32wbxx_hal_tim.h
  • __HAL_TIM_ENABLE_DMA : stm32wbxx_hal_tim.h
  • __HAL_TIM_ENABLE_IT : stm32wbxx_hal_tim.h
  • __HAL_TIM_ENABLE_OCxFAST : stm32wbxx_hal_tim.h
  • __HAL_TIM_ENABLE_OCxPRELOAD : stm32wbxx_hal_tim.h
  • __HAL_TIM_GET_AUTORELOAD : stm32wbxx_hal_tim.h
  • __HAL_TIM_GET_CLOCKDIVISION : stm32wbxx_hal_tim.h
  • __HAL_TIM_GET_COMPARE : stm32wbxx_hal_tim.h
  • __HAL_TIM_GET_COUNTER : stm32wbxx_hal_tim.h
  • __HAL_TIM_GET_FLAG : stm32wbxx_hal_tim.h
  • __HAL_TIM_GET_ICPRESCALER : stm32wbxx_hal_tim.h
  • __HAL_TIM_GET_IT_SOURCE : stm32wbxx_hal_tim.h
  • __HAL_TIM_IS_TIM_COUNTING_DOWN : stm32wbxx_hal_tim.h
  • __HAL_TIM_MOE_DISABLE : stm32wbxx_hal_tim.h
  • __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY : stm32wbxx_hal_tim.h
  • __HAL_TIM_MOE_ENABLE : stm32wbxx_hal_tim.h
  • __HAL_TIM_RESET_HANDLE_STATE : stm32wbxx_hal_tim.h
  • __HAL_TIM_SET_AUTORELOAD : stm32wbxx_hal_tim.h
  • __HAL_TIM_SET_CAPTUREPOLARITY : stm32wbxx_hal_tim.h
  • __HAL_TIM_SET_CLOCKDIVISION : stm32wbxx_hal_tim.h
  • __HAL_TIM_SET_COMPARE : stm32wbxx_hal_tim.h
  • __HAL_TIM_SET_COUNTER : stm32wbxx_hal_tim.h
  • __HAL_TIM_SET_ICPRESCALER : stm32wbxx_hal_tim.h
  • __HAL_TIM_SET_PRESCALER : stm32wbxx_hal_tim.h
  • __HAL_TIM_URS_DISABLE : stm32wbxx_hal_tim.h
  • __HAL_TIM_URS_ENABLE : stm32wbxx_hal_tim.h
  • __HAL_TSC_CLEAR_FLAG : stm32wbxx_hal_tsc.h
  • __HAL_TSC_CLOSE_ANALOG_SWITCH : stm32wbxx_hal_tsc.h
  • __HAL_TSC_DISABLE : stm32wbxx_hal_tsc.h
  • __HAL_TSC_DISABLE_CHANNEL : stm32wbxx_hal_tsc.h
  • __HAL_TSC_DISABLE_GROUP : stm32wbxx_hal_tsc.h
  • __HAL_TSC_DISABLE_HYSTERESIS : stm32wbxx_hal_tsc.h
  • __HAL_TSC_DISABLE_IT : stm32wbxx_hal_tsc.h
  • __HAL_TSC_DISABLE_SAMPLING : stm32wbxx_hal_tsc.h
  • __HAL_TSC_ENABLE : stm32wbxx_hal_tsc.h
  • __HAL_TSC_ENABLE_CHANNEL : stm32wbxx_hal_tsc.h
  • __HAL_TSC_ENABLE_GROUP : stm32wbxx_hal_tsc.h
  • __HAL_TSC_ENABLE_HYSTERESIS : stm32wbxx_hal_tsc.h
  • __HAL_TSC_ENABLE_IT : stm32wbxx_hal_tsc.h
  • __HAL_TSC_ENABLE_SAMPLING : stm32wbxx_hal_tsc.h
  • __HAL_TSC_GET_FLAG : stm32wbxx_hal_tsc.h
  • __HAL_TSC_GET_GROUP_STATUS : stm32wbxx_hal_tsc.h
  • __HAL_TSC_GET_IT_SOURCE : stm32wbxx_hal_tsc.h
  • __HAL_TSC_OPEN_ANALOG_SWITCH : stm32wbxx_hal_tsc.h
  • __HAL_TSC_RESET_HANDLE_STATE : stm32wbxx_hal_tsc.h
  • __HAL_TSC_SET_IODEF_INFLOAT : stm32wbxx_hal_tsc.h
  • __HAL_TSC_SET_IODEF_OUTPPLOW : stm32wbxx_hal_tsc.h
  • __HAL_TSC_SET_SYNC_POL_FALL : stm32wbxx_hal_tsc.h
  • __HAL_TSC_SET_SYNC_POL_RISE_HIGH : stm32wbxx_hal_tsc.h
  • __HAL_TSC_START_ACQ : stm32wbxx_hal_tsc.h
  • __HAL_TSC_STOP_ACQ : stm32wbxx_hal_tsc.h
  • __HAL_UART_CLEAR_FEFLAG : stm32wbxx_hal_uart.h
  • __HAL_UART_CLEAR_FLAG : stm32wbxx_hal_uart.h
  • __HAL_UART_CLEAR_IDLEFLAG : stm32wbxx_hal_uart.h
  • __HAL_UART_CLEAR_IT : stm32wbxx_hal_uart.h
  • __HAL_UART_CLEAR_NEFLAG : stm32wbxx_hal_uart.h
  • __HAL_UART_CLEAR_OREFLAG : stm32wbxx_hal_uart.h
  • __HAL_UART_CLEAR_PEFLAG : stm32wbxx_hal_uart.h
  • __HAL_UART_CLEAR_TXFECF : stm32wbxx_hal_uart.h
  • __HAL_UART_DISABLE : stm32wbxx_hal_uart.h
  • __HAL_UART_DISABLE_IT : stm32wbxx_hal_uart.h
  • __HAL_UART_ENABLE : stm32wbxx_hal_uart.h
  • __HAL_UART_ENABLE_IT : stm32wbxx_hal_uart.h
  • __HAL_UART_FLUSH_DRREGISTER : stm32wbxx_hal_uart.h
  • __HAL_UART_GET_FLAG : stm32wbxx_hal_uart.h
  • __HAL_UART_GET_IT : stm32wbxx_hal_uart.h
  • __HAL_UART_GET_IT_SOURCE : stm32wbxx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_DISABLE : stm32wbxx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_ENABLE : stm32wbxx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_DISABLE : stm32wbxx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_ENABLE : stm32wbxx_hal_uart.h
  • __HAL_UART_ONE_BIT_SAMPLE_DISABLE : stm32wbxx_hal_uart.h
  • __HAL_UART_ONE_BIT_SAMPLE_ENABLE : stm32wbxx_hal_uart.h
  • __HAL_UART_RESET_HANDLE_STATE : stm32wbxx_hal_uart.h
  • __HAL_UART_SEND_REQ : stm32wbxx_hal_uart.h
  • __HAL_USART_CLEAR_FEFLAG : stm32wbxx_hal_usart.h
  • __HAL_USART_CLEAR_FLAG : stm32wbxx_hal_usart.h
  • __HAL_USART_CLEAR_IDLEFLAG : stm32wbxx_hal_usart.h
  • __HAL_USART_CLEAR_IT : stm32wbxx_hal_usart.h
  • __HAL_USART_CLEAR_NEFLAG : stm32wbxx_hal_usart.h
  • __HAL_USART_CLEAR_OREFLAG : stm32wbxx_hal_usart.h
  • __HAL_USART_CLEAR_PEFLAG : stm32wbxx_hal_usart.h
  • __HAL_USART_CLEAR_TXFECF : stm32wbxx_hal_usart.h
  • __HAL_USART_CLEAR_UDRFLAG : stm32wbxx_hal_usart.h
  • __HAL_USART_DISABLE : stm32wbxx_hal_usart.h
  • __HAL_USART_DISABLE_IT : stm32wbxx_hal_usart.h
  • __HAL_USART_ENABLE : stm32wbxx_hal_usart.h
  • __HAL_USART_ENABLE_IT : stm32wbxx_hal_usart.h
  • __HAL_USART_GET_FLAG : stm32wbxx_hal_usart.h
  • __HAL_USART_GET_IT : stm32wbxx_hal_usart.h
  • __HAL_USART_GET_IT_SOURCE : stm32wbxx_hal_usart.h
  • __HAL_USART_ONE_BIT_SAMPLE_DISABLE : stm32wbxx_hal_usart.h
  • __HAL_USART_ONE_BIT_SAMPLE_ENABLE : stm32wbxx_hal_usart.h
  • __HAL_USART_RESET_HANDLE_STATE : stm32wbxx_hal_usart.h
  • __HAL_USART_SEND_REQ : stm32wbxx_hal_usart.h
  • __HAL_USB_WAKEUP_EXTI_DISABLE_IT : stm32wbxx_hal_pcd.h
  • __HAL_USB_WAKEUP_EXTI_ENABLE_IT : stm32wbxx_hal_pcd.h
  • __HAL_WWDG_CLEAR_FLAG : stm32wbxx_hal_wwdg.h
  • __HAL_WWDG_CLEAR_IT : stm32wbxx_hal_wwdg.h
  • __HAL_WWDG_ENABLE : stm32wbxx_hal_wwdg.h
  • __HAL_WWDG_ENABLE_IT : stm32wbxx_hal_wwdg.h
  • __HAL_WWDG_GET_FLAG : stm32wbxx_hal_wwdg.h
  • __HAL_WWDG_GET_IT : stm32wbxx_hal_wwdg.h
  • __HAL_WWDG_GET_IT_SOURCE : stm32wbxx_hal_wwdg.h
  • __LL_ADC_ANALOGWD_CHANNEL_GROUP : stm32wbxx_ll_adc.h
  • __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION : stm32wbxx_ll_adc.h
  • __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION : stm32wbxx_ll_adc.h
  • __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW : stm32wbxx_ll_adc.h
  • __LL_ADC_CALC_DATA_TO_VOLTAGE : stm32wbxx_ll_adc.h
  • __LL_ADC_CALC_TEMPERATURE : stm32wbxx_ll_adc.h
  • __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS : stm32wbxx_ll_adc.h
  • __LL_ADC_CALC_VREFANALOG_VOLTAGE : stm32wbxx_ll_adc.h
  • __LL_ADC_CALIB_FACTOR_SINGLE_DIFF : stm32wbxx_ll_adc.h
  • __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL : stm32wbxx_ll_adc.h
  • __LL_ADC_CHANNEL_TO_DECIMAL_NB : stm32wbxx_ll_adc.h
  • __LL_ADC_COMMON_INSTANCE : stm32wbxx_ll_adc.h
  • __LL_ADC_CONVERT_DATA_RESOLUTION : stm32wbxx_ll_adc.h
  • __LL_ADC_DECIMAL_NB_TO_CHANNEL : stm32wbxx_ll_adc.h
  • __LL_ADC_DIGITAL_SCALE : stm32wbxx_ll_adc.h
  • __LL_ADC_IS_CHANNEL_INTERNAL : stm32wbxx_ll_adc.h
  • __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE : stm32wbxx_ll_adc.h
  • __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE : stm32wbxx_ll_adc.h
  • __LL_COMP_COMMON_INSTANCE : stm32wbxx_ll_comp.h
  • __LL_CRS_CALC_CALCULATE_RELOADVALUE : stm32wbxx_ll_crs.h
  • __LL_DMA_GET_CHANNEL : stm32wbxx_ll_dma.h
  • __LL_DMA_GET_CHANNEL_INSTANCE : stm32wbxx_ll_dma.h
  • __LL_DMA_GET_INSTANCE : stm32wbxx_ll_dma.h
  • __LL_DMA_INSTANCE_TO_CHANNEL : stm32wbxx_ll_dma.h
  • __LL_DMA_INSTANCE_TO_DMAMUX_CCR : stm32wbxx_ll_dma.h
  • __LL_I2C_CONVERT_TIMINGS : stm32wbxx_ll_i2c.h
  • __LL_LPUART_DIV : stm32wbxx_ll_lpuart.h
  • __LL_RCC_CALC_HCLK1_FREQ : stm32wbxx_ll_rcc.h
  • __LL_RCC_CALC_HCLK2_FREQ : stm32wbxx_ll_rcc.h
  • __LL_RCC_CALC_HCLK4_FREQ : stm32wbxx_ll_rcc.h
  • __LL_RCC_CALC_MSI_FREQ : stm32wbxx_ll_rcc.h
  • __LL_RCC_CALC_PCLK1_FREQ : stm32wbxx_ll_rcc.h
  • __LL_RCC_CALC_PCLK2_FREQ : stm32wbxx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_48M_FREQ : stm32wbxx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_ADC_FREQ : stm32wbxx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_FREQ : stm32wbxx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_SAI_FREQ : stm32wbxx_ll_rcc.h
  • __LL_RCC_CALC_PLLSAI1_48M_FREQ : stm32wbxx_ll_rcc.h
  • __LL_RCC_CALC_PLLSAI1_ADC_FREQ : stm32wbxx_ll_rcc.h
  • __LL_RCC_CALC_PLLSAI1_SAI_FREQ : stm32wbxx_ll_rcc.h
  • __LL_RTC_CONVERT_BCD2BIN : stm32wbxx_ll_rtc.h
  • __LL_RTC_CONVERT_BIN2BCD : stm32wbxx_ll_rtc.h
  • __LL_RTC_GET_DAY : stm32wbxx_ll_rtc.h
  • __LL_RTC_GET_HOUR : stm32wbxx_ll_rtc.h
  • __LL_RTC_GET_MINUTE : stm32wbxx_ll_rtc.h
  • __LL_RTC_GET_MONTH : stm32wbxx_ll_rtc.h
  • __LL_RTC_GET_SECOND : stm32wbxx_ll_rtc.h
  • __LL_RTC_GET_WEEKDAY : stm32wbxx_ll_rtc.h
  • __LL_RTC_GET_YEAR : stm32wbxx_ll_rtc.h
  • __LL_TIM_CALC_ARR : stm32wbxx_ll_tim.h
  • __LL_TIM_CALC_DEADTIME : stm32wbxx_ll_tim.h
  • __LL_TIM_CALC_DELAY : stm32wbxx_ll_tim.h
  • __LL_TIM_CALC_PSC : stm32wbxx_ll_tim.h
  • __LL_TIM_CALC_PULSE : stm32wbxx_ll_tim.h
  • __LL_TIM_GET_ICPSC_RATIO : stm32wbxx_ll_tim.h
  • __LL_TIM_GETFLAG_UIFCPY : stm32wbxx_ll_tim.h
  • __LL_USART_DIV_SAMPLING16 : stm32wbxx_ll_usart.h
  • __LL_USART_DIV_SAMPLING8 : stm32wbxx_ll_usart.h
  • __LSCO1_CLK_ENABLE : stm32wbxx_hal_rcc_ex.c
  • __LSCO2_CLK_ENABLE : stm32wbxx_hal_rcc_ex.c
  • __LSCO3_CLK_ENABLE : stm32wbxx_hal_rcc_ex.c
  • __MCO1_CLK_ENABLE : stm32wbxx_hal_rcc.c
  • __MCO2_CLK_ENABLE : stm32wbxx_hal_rcc.c
  • __MCO3_CLK_ENABLE : stm32wbxx_hal_rcc.c
  • __STM32WBxx_HAL_VERSION : stm32wbxx_hal.c
  • __STM32WBxx_HAL_VERSION_MAIN : stm32wbxx_hal.c
  • __STM32WBxx_HAL_VERSION_RC : stm32wbxx_hal.c
  • __STM32WBxx_HAL_VERSION_SUB1 : stm32wbxx_hal.c
  • __STM32WBxx_HAL_VERSION_SUB2 : stm32wbxx_hal.c
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

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- a -

  • ADC_ANALOGWATCHDOG_1 : stm32wbxx_hal_adc.h
  • ADC_ANALOGWATCHDOG_2 : stm32wbxx_hal_adc.h
  • ADC_ANALOGWATCHDOG_3 : stm32wbxx_hal_adc.h
  • ADC_ANALOGWATCHDOG_ALL_INJEC : stm32wbxx_hal_adc.h
  • ADC_ANALOGWATCHDOG_ALL_REG : stm32wbxx_hal_adc.h
  • ADC_ANALOGWATCHDOG_ALL_REGINJEC : stm32wbxx_hal_adc.h
  • ADC_ANALOGWATCHDOG_NONE : stm32wbxx_hal_adc.h
  • ADC_ANALOGWATCHDOG_SINGLE_INJEC : stm32wbxx_hal_adc.h
  • ADC_ANALOGWATCHDOG_SINGLE_REG : stm32wbxx_hal_adc.h
  • ADC_ANALOGWATCHDOG_SINGLE_REGINJEC : stm32wbxx_hal_adc.h
  • ADC_AWD1_EVENT : stm32wbxx_hal_adc.h
  • ADC_AWD1THRESHOLD_SHIFT_RESOLUTION : stm32wbxx_hal_adc_ex.h
  • ADC_AWD23THRESHOLD_SHIFT_RESOLUTION : stm32wbxx_hal_adc_ex.h
  • ADC_AWD2_EVENT : stm32wbxx_hal_adc.h
  • ADC_AWD3_EVENT : stm32wbxx_hal_adc.h
  • ADC_AWD_CR12_REGOFFSETGAP_MASK : stm32wbxx_ll_adc.h
  • ADC_AWD_CR12_REGOFFSETGAP_VAL : stm32wbxx_ll_adc.h
  • ADC_AWD_CR1_CHANNEL_MASK : stm32wbxx_ll_adc.h
  • ADC_AWD_CR1_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_AWD_CR23_CHANNEL_MASK : stm32wbxx_ll_adc.h
  • ADC_AWD_CR2_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_AWD_CR3_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_AWD_CR_ALL_CHANNEL_MASK : stm32wbxx_ll_adc.h
  • ADC_AWD_CRX_REGOFFSET_MASK : stm32wbxx_ll_adc.h
  • ADC_AWD_CRX_REGOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_AWD_EVENT : stm32wbxx_hal_adc.h
  • ADC_AWD_TR1_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_AWD_TR2_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_AWD_TR3_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_AWD_TRX_BIT_HIGH_MASK : stm32wbxx_ll_adc.h
  • ADC_AWD_TRX_BIT_HIGH_POS : stm32wbxx_ll_adc.h
  • ADC_AWD_TRX_BIT_HIGH_SHIFT4 : stm32wbxx_ll_adc.h
  • ADC_AWD_TRX_REGOFFSET_MASK : stm32wbxx_ll_adc.h
  • ADC_AWD_TRX_REGOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_BATTERY_VOLTAGE_INSTANCE : stm32wbxx_hal_adc_ex.h
  • ADC_CALIBRATION_TIMEOUT : stm32wbxx_hal_adc_ex.c
  • ADC_CFGR_AUTOWAIT : stm32wbxx_hal_adc_ex.h
  • ADC_CFGR_AWD1EN_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_CFGR_AWD1SGL_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_CFGR_CONTINUOUS : stm32wbxx_hal_adc_ex.h
  • ADC_CFGR_DFSDM : stm32wbxx_hal_adc_ex.h
  • ADC_CFGR_DISCONTINUOUS_NUM : stm32wbxx_hal_adc_ex.h
  • ADC_CFGR_DMACONTREQ : stm32wbxx_hal_adc_ex.h
  • ADC_CFGR_FIELDS : stm32wbxx_hal_adc_ex.h
  • ADC_CFGR_FIELDS_1 : stm32wbxx_hal_adc.c
  • ADC_CFGR_FIELDS_2 : stm32wbxx_hal_adc_ex.h
  • ADC_CFGR_INJECT_CONTEXT_QUEUE : stm32wbxx_hal_adc_ex.h
  • ADC_CFGR_INJECT_DISCCONTINUOUS : stm32wbxx_hal_adc_ex.h
  • ADC_CFGR_JAWD1EN_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_CFGR_REG_DISCONTINUOUS : stm32wbxx_hal_adc_ex.h
  • ADC_CFGR_RES_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_0 : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_0_BITFIELD : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_0_NUMBER : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_0_SMP : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_1 : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_10 : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_10_BITFIELD : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_10_NUMBER : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_10_SMP : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_11 : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_11_BITFIELD : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_11_NUMBER : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_11_SMP : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_12 : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_12_BITFIELD : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_12_NUMBER : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_12_SMP : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_13 : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_13_BITFIELD : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_13_NUMBER : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_13_SMP : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_14 : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_14_BITFIELD : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_14_NUMBER : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_14_SMP : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_15 : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_15_BITFIELD : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_15_NUMBER : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_15_SMP : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_16 : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_16_BITFIELD : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_16_NUMBER : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_16_SMP : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_17 : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_17_BITFIELD : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_17_NUMBER : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_17_SMP : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_18 : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_18_BITFIELD : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_18_NUMBER : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_18_SMP : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_1_BITFIELD : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_1_NUMBER : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_1_SMP : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_2 : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_2_BITFIELD : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_2_NUMBER : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_2_SMP : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_3 : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_3_BITFIELD : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_3_NUMBER : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_3_SMP : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_4 : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_4_BITFIELD : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_4_NUMBER : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_4_SMP : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_5 : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_5_BITFIELD : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_5_NUMBER : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_5_SMP : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_6 : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_6_BITFIELD : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_6_NUMBER : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_6_SMP : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_7 : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_7_BITFIELD : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_7_NUMBER : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_7_SMP : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_8 : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_8_BITFIELD : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_8_NUMBER : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_8_SMP : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_9 : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_9_BITFIELD : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_9_NUMBER : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_9_SMP : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_ID_BITFIELD_MASK : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_ID_INTERNAL_CH : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_ID_INTERNAL_CH_2 : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_ID_INTERNAL_CH_MASK : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_ID_MASK : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_MASK : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_SMPRX_REGOFFSET_MASK : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_SMPx_BITOFFSET_MASK : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_SMPx_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_CHANNEL_TEMPSENSOR : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_VBAT : stm32wbxx_hal_adc.h
  • ADC_CHANNEL_VREFINT : stm32wbxx_hal_adc.h
  • ADC_CLEAR_COMMON_CONTROL_REGISTER : stm32wbxx_hal_adc_ex.h
  • ADC_CLEAR_ERRORCODE : stm32wbxx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV1 : stm32wbxx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV10 : stm32wbxx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV12 : stm32wbxx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV128 : stm32wbxx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV16 : stm32wbxx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV2 : stm32wbxx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV256 : stm32wbxx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV32 : stm32wbxx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV4 : stm32wbxx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV6 : stm32wbxx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV64 : stm32wbxx_hal_adc.h
  • ADC_CLOCK_ASYNC_DIV8 : stm32wbxx_hal_adc.h
  • ADC_CLOCK_RATIO_VS_CPU_HIGHEST : stm32wbxx_ll_adc.c
  • ADC_CLOCK_SYNC_PCLK_DIV1 : stm32wbxx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV2 : stm32wbxx_hal_adc.h
  • ADC_CLOCK_SYNC_PCLK_DIV4 : stm32wbxx_hal_adc.h
  • ADC_CONVERSION_TIME_MAX_CPU_CYCLES : stm32wbxx_hal_adc.c
  • ADC_CR_BITS_PROPERTY_RS : stm32wbxx_ll_adc.h
  • ADC_DATAALIGN_LEFT : stm32wbxx_hal_adc.h
  • ADC_DATAALIGN_RIGHT : stm32wbxx_hal_adc.h
  • ADC_DIFFERENTIAL_ENDED : stm32wbxx_hal_adc_ex.h
  • ADC_DISABLE_TIMEOUT : stm32wbxx_hal_adc.c
  • ADC_ENABLE_TIMEOUT : stm32wbxx_hal_adc.c
  • ADC_EOC_SEQ_CONV : stm32wbxx_hal_adc.h
  • ADC_EOC_SINGLE_CONV : stm32wbxx_hal_adc.h
  • ADC_EOSMP_EVENT : stm32wbxx_hal_adc.h
  • ADC_EXTERNALTRIG_EXT_IT11 : stm32wbxx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_CC1 : stm32wbxx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_CC2 : stm32wbxx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_CC3 : stm32wbxx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_TRGO : stm32wbxx_hal_adc.h
  • ADC_EXTERNALTRIG_T1_TRGO2 : stm32wbxx_hal_adc.h
  • ADC_EXTERNALTRIG_T2_CC2 : stm32wbxx_hal_adc.h
  • ADC_EXTERNALTRIG_T2_TRGO : stm32wbxx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_FALLING : stm32wbxx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_NONE : stm32wbxx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_RISING : stm32wbxx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING : stm32wbxx_hal_adc.h
  • ADC_EXTERNALTRIGINJEC_EXT_IT15 : stm32wbxx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T1_CC4 : stm32wbxx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T1_TRGO : stm32wbxx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T1_TRGO2 : stm32wbxx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T2_CC1 : stm32wbxx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJEC_T2_TRGO : stm32wbxx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING : stm32wbxx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_NONE : stm32wbxx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_RISING : stm32wbxx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING : stm32wbxx_hal_adc_ex.h
  • ADC_FLAG_AWD1 : stm32wbxx_hal_adc.h
  • ADC_FLAG_AWD2 : stm32wbxx_hal_adc.h
  • ADC_FLAG_AWD3 : stm32wbxx_hal_adc.h
  • ADC_FLAG_EOC : stm32wbxx_hal_adc.h
  • ADC_FLAG_EOS : stm32wbxx_hal_adc.h
  • ADC_FLAG_EOSMP : stm32wbxx_hal_adc.h
  • ADC_FLAG_JEOC : stm32wbxx_hal_adc.h
  • ADC_FLAG_JEOS : stm32wbxx_hal_adc.h
  • ADC_FLAG_JQOVF : stm32wbxx_hal_adc.h
  • ADC_FLAG_OVR : stm32wbxx_hal_adc.h
  • ADC_FLAG_RDY : stm32wbxx_hal_adc.h
  • ADC_GET_RESOLUTION : stm32wbxx_hal_adc.h
  • ADC_INJ_JDRX_REGOFFSET_MASK : stm32wbxx_ll_adc.h
  • ADC_INJ_RANK_1_JSQR_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_INJ_RANK_2_JSQR_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_INJ_RANK_3_JSQR_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_INJ_RANK_4_JSQR_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_INJ_RANK_ID_JSQR_MASK : stm32wbxx_ll_adc.h
  • ADC_INJ_TRIG_EDGE_MASK : stm32wbxx_ll_adc.h
  • ADC_INJ_TRIG_EXT_EDGE_DEFAULT : stm32wbxx_ll_adc.h
  • ADC_INJ_TRIG_EXTEN_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_INJ_TRIG_SOURCE_MASK : stm32wbxx_ll_adc.h
  • ADC_INJECTED_GROUP : stm32wbxx_hal_adc_ex.h
  • ADC_INJECTED_RANK_1 : stm32wbxx_hal_adc_ex.h
  • ADC_INJECTED_RANK_2 : stm32wbxx_hal_adc_ex.h
  • ADC_INJECTED_RANK_3 : stm32wbxx_hal_adc_ex.h
  • ADC_INJECTED_RANK_4 : stm32wbxx_hal_adc_ex.h
  • ADC_INJECTED_SOFTWARE_START : stm32wbxx_hal_adc_ex.h
  • ADC_IS_INDEPENDENT : stm32wbxx_hal_adc_ex.h
  • ADC_IS_SOFTWARE_START_INJECTED : stm32wbxx_hal_adc_ex.h
  • ADC_IT_AWD : stm32wbxx_hal_adc.h
  • ADC_IT_AWD1 : stm32wbxx_hal_adc.h
  • ADC_IT_AWD2 : stm32wbxx_hal_adc.h
  • ADC_IT_AWD3 : stm32wbxx_hal_adc.h
  • ADC_IT_EOC : stm32wbxx_hal_adc.h
  • ADC_IT_EOS : stm32wbxx_hal_adc.h
  • ADC_IT_EOSMP : stm32wbxx_hal_adc.h
  • ADC_IT_JEOC : stm32wbxx_hal_adc.h
  • ADC_IT_JEOS : stm32wbxx_hal_adc.h
  • ADC_IT_JQOVF : stm32wbxx_hal_adc.h
  • ADC_IT_OVR : stm32wbxx_hal_adc.h
  • ADC_IT_RDY : stm32wbxx_hal_adc.h
  • ADC_JDR1_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_JDR2_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_JDR3_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_JDR4_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_JDRX_REGOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_JQOVF_EVENT : stm32wbxx_hal_adc.h
  • ADC_JSQR_FIELDS : stm32wbxx_hal_adc_ex.c
  • ADC_JSQR_RK : stm32wbxx_hal_adc_ex.h
  • ADC_OFFSET_1 : stm32wbxx_hal_adc_ex.h
  • ADC_OFFSET_2 : stm32wbxx_hal_adc_ex.h
  • ADC_OFFSET_3 : stm32wbxx_hal_adc_ex.h
  • ADC_OFFSET_4 : stm32wbxx_hal_adc_ex.h
  • ADC_OFFSET_NONE : stm32wbxx_hal_adc_ex.h
  • ADC_OFFSET_SHIFT_RESOLUTION : stm32wbxx_hal_adc_ex.h
  • ADC_OFR1_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_OFR2_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_OFR3_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_OFR4_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_OFRx_REGOFFSET_MASK : stm32wbxx_ll_adc.h
  • ADC_OVERSAMPLING_RATIO_128 : stm32wbxx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_16 : stm32wbxx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_2 : stm32wbxx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_256 : stm32wbxx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_32 : stm32wbxx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_4 : stm32wbxx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_64 : stm32wbxx_hal_adc.h
  • ADC_OVERSAMPLING_RATIO_8 : stm32wbxx_hal_adc.h
  • ADC_OVR_DATA_OVERWRITTEN : stm32wbxx_hal_adc.h
  • ADC_OVR_DATA_PRESERVED : stm32wbxx_hal_adc.h
  • ADC_OVR_EVENT : stm32wbxx_hal_adc.h
  • ADC_REG_RANK_10_SQRX_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_REG_RANK_11_SQRX_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_REG_RANK_12_SQRX_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_REG_RANK_13_SQRX_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_REG_RANK_14_SQRX_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_REG_RANK_15_SQRX_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_REG_RANK_16_SQRX_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_REG_RANK_1_SQRX_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_REG_RANK_2_SQRX_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_REG_RANK_3_SQRX_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_REG_RANK_4_SQRX_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_REG_RANK_5_SQRX_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_REG_RANK_6_SQRX_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_REG_RANK_7_SQRX_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_REG_RANK_8_SQRX_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_REG_RANK_9_SQRX_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_REG_RANK_ID_SQRX_MASK : stm32wbxx_ll_adc.h
  • ADC_REG_SQRX_REGOFFSET_MASK : stm32wbxx_ll_adc.h
  • ADC_REG_TRIG_EDGE_MASK : stm32wbxx_ll_adc.h
  • ADC_REG_TRIG_EXT_EDGE_DEFAULT : stm32wbxx_ll_adc.h
  • ADC_REG_TRIG_EXTEN_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_REG_TRIG_EXTSEL_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_REG_TRIG_SOURCE_MASK : stm32wbxx_ll_adc.h
  • ADC_REGOVERSAMPLING_CONTINUED_MODE : stm32wbxx_hal_adc.h
  • ADC_REGOVERSAMPLING_RESUMED_MODE : stm32wbxx_hal_adc.h
  • ADC_REGULAR_GROUP : stm32wbxx_hal_adc_ex.h
  • ADC_REGULAR_INJECTED_GROUP : stm32wbxx_hal_adc_ex.h
  • ADC_REGULAR_RANK_1 : stm32wbxx_hal_adc.h
  • ADC_REGULAR_RANK_10 : stm32wbxx_hal_adc.h
  • ADC_REGULAR_RANK_11 : stm32wbxx_hal_adc.h
  • ADC_REGULAR_RANK_12 : stm32wbxx_hal_adc.h
  • ADC_REGULAR_RANK_13 : stm32wbxx_hal_adc.h
  • ADC_REGULAR_RANK_14 : stm32wbxx_hal_adc.h
  • ADC_REGULAR_RANK_15 : stm32wbxx_hal_adc.h
  • ADC_REGULAR_RANK_16 : stm32wbxx_hal_adc.h
  • ADC_REGULAR_RANK_2 : stm32wbxx_hal_adc.h
  • ADC_REGULAR_RANK_3 : stm32wbxx_hal_adc.h
  • ADC_REGULAR_RANK_4 : stm32wbxx_hal_adc.h
  • ADC_REGULAR_RANK_5 : stm32wbxx_hal_adc.h
  • ADC_REGULAR_RANK_6 : stm32wbxx_hal_adc.h
  • ADC_REGULAR_RANK_7 : stm32wbxx_hal_adc.h
  • ADC_REGULAR_RANK_8 : stm32wbxx_hal_adc.h
  • ADC_REGULAR_RANK_9 : stm32wbxx_hal_adc.h
  • ADC_RESOLUTION_10B : stm32wbxx_hal_adc.h
  • ADC_RESOLUTION_12B : stm32wbxx_hal_adc.h
  • ADC_RESOLUTION_6B : stm32wbxx_hal_adc.h
  • ADC_RESOLUTION_8B : stm32wbxx_hal_adc.h
  • ADC_RIGHTBITSHIFT_1 : stm32wbxx_hal_adc.h
  • ADC_RIGHTBITSHIFT_2 : stm32wbxx_hal_adc.h
  • ADC_RIGHTBITSHIFT_3 : stm32wbxx_hal_adc.h
  • ADC_RIGHTBITSHIFT_4 : stm32wbxx_hal_adc.h
  • ADC_RIGHTBITSHIFT_5 : stm32wbxx_hal_adc.h
  • ADC_RIGHTBITSHIFT_6 : stm32wbxx_hal_adc.h
  • ADC_RIGHTBITSHIFT_7 : stm32wbxx_hal_adc.h
  • ADC_RIGHTBITSHIFT_8 : stm32wbxx_hal_adc.h
  • ADC_RIGHTBITSHIFT_NONE : stm32wbxx_hal_adc.h
  • ADC_SAMPLETIME_12CYCLES_5 : stm32wbxx_hal_adc.h
  • ADC_SAMPLETIME_247CYCLES_5 : stm32wbxx_hal_adc.h
  • ADC_SAMPLETIME_24CYCLES_5 : stm32wbxx_hal_adc.h
  • ADC_SAMPLETIME_2CYCLES_5 : stm32wbxx_hal_adc.h
  • ADC_SAMPLETIME_47CYCLES_5 : stm32wbxx_hal_adc.h
  • ADC_SAMPLETIME_640CYCLES_5 : stm32wbxx_hal_adc.h
  • ADC_SAMPLETIME_6CYCLES_5 : stm32wbxx_hal_adc.h
  • ADC_SAMPLETIME_92CYCLES_5 : stm32wbxx_hal_adc.h
  • ADC_SCAN_DISABLE : stm32wbxx_hal_adc.h
  • ADC_SCAN_ENABLE : stm32wbxx_hal_adc.h
  • ADC_SINGLE_ENDED : stm32wbxx_hal_adc_ex.h
  • ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK : stm32wbxx_ll_adc.h
  • ADC_SINGLEDIFF_CALIB_F_BIT_D_POS : stm32wbxx_ll_adc.h
  • ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 : stm32wbxx_ll_adc.h
  • ADC_SINGLEDIFF_CALIB_FACTOR_MASK : stm32wbxx_ll_adc.h
  • ADC_SINGLEDIFF_CALIB_START_MASK : stm32wbxx_ll_adc.h
  • ADC_SINGLEDIFF_CHANNEL_MASK : stm32wbxx_ll_adc.h
  • ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK : stm32wbxx_ll_adc.h
  • ADC_SMPR1_FIELDS : stm32wbxx_hal_adc_ex.h
  • ADC_SMPR1_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_SMPR2_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_SMPRX_REGOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_SOFTWARE_START : stm32wbxx_hal_adc.h
  • ADC_SQR1_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_SQR2_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_SQR3_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_SQR4_REGOFFSET : stm32wbxx_ll_adc.h
  • ADC_SQRX_REGOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_STATE_CLR_SET : stm32wbxx_hal_adc.h
  • ADC_STOP_CONVERSION_TIMEOUT : stm32wbxx_hal_adc.h
  • ADC_TEMPERATURE_SENSOR_INSTANCE : stm32wbxx_hal_adc_ex.h
  • ADC_TEMPSENSOR_DELAY_US : stm32wbxx_hal_adc.h
  • ADC_TIMEOUT_DISABLE_CPU_CYCLES : stm32wbxx_ll_adc.c
  • ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES : stm32wbxx_ll_adc.c
  • ADC_TR1_HT1_BITOFFSET_POS : stm32wbxx_ll_adc.h
  • ADC_TRIGGEREDMODE_MULTI_TRIGGER : stm32wbxx_hal_adc.h
  • ADC_TRIGGEREDMODE_SINGLE_TRIGGER : stm32wbxx_hal_adc.h
  • ADC_VREFINT_INSTANCE : stm32wbxx_hal_adc_ex.h
  • assert_param : stm32wbxx_ll_lpuart.c , stm32wbxx_ll_lptim.c , stm32wbxx_ll_usart.c , stm32wbxx_ll_comp.c , stm32wbxx_ll_rng.c , stm32wbxx_ll_spi.c , stm32wbxx_ll_utils.c , stm32wbxx_ll_i2c.c , stm32wbxx_ll_crc.c , stm32wbxx_ll_tim.c , stm32wbxx_ll_rtc.c , stm32wbxx_ll_gpio.c , stm32wbxx_ll_pka.c , stm32wbxx_ll_adc.c , stm32wbxx_ll_rcc.c , stm32wbxx_ll_exti.c , stm32wbxx_hal_conf.h , stm32wbxx_ll_dma.c
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

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- b -

  • BDCR_REG_INDEX : stm32wbxx_hal_rcc.h
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
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  • q
  • r
  • s
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- c -

  • CHANNEL_INDEX_Msk : stm32wbxx_hal_ipcc.c
  • CLK48_MASK : stm32wbxx_hal_rcc_ex.h
  • CLOCKSMPS_TIMEOUT_VALUE : stm32wbxx_hal_rcc_ex.c
  • CLOCKSWITCH_TIMEOUT_VALUE : stm32wbxx_hal_rcc.c
  • COMP_BLANKINGSRC_NONE : stm32wbxx_hal_comp.h
  • COMP_BLANKINGSRC_TIM1_OC5 : stm32wbxx_hal_comp.h
  • COMP_BLANKINGSRC_TIM2_OC3 : stm32wbxx_hal_comp.h
  • COMP_CLEAR_ERRORCODE : stm32wbxx_hal_comp.h
  • COMP_DELAY_STARTUP_US : stm32wbxx_hal_comp.c
  • COMP_DELAY_VOLTAGE_SCALER_STAB_US : stm32wbxx_hal_comp.c
  • COMP_EXTI_EVENT : stm32wbxx_hal_comp.h
  • COMP_EXTI_FALLING : stm32wbxx_hal_comp.h
  • COMP_EXTI_IT : stm32wbxx_hal_comp.h
  • COMP_EXTI_LINE_COMP1 : stm32wbxx_hal_comp.h
  • COMP_EXTI_LINE_COMP2 : stm32wbxx_hal_comp.h
  • COMP_EXTI_RISING : stm32wbxx_hal_comp.h
  • COMP_GET_EXTI_LINE : stm32wbxx_hal_comp.h
  • COMP_HYSTERESIS_HIGH : stm32wbxx_hal_comp.h
  • COMP_HYSTERESIS_LOW : stm32wbxx_hal_comp.h
  • COMP_HYSTERESIS_MEDIUM : stm32wbxx_hal_comp.h
  • COMP_HYSTERESIS_NONE : stm32wbxx_hal_comp.h
  • COMP_INPUT_MINUS_1_2VREFINT : stm32wbxx_hal_comp.h
  • COMP_INPUT_MINUS_1_4VREFINT : stm32wbxx_hal_comp.h
  • COMP_INPUT_MINUS_3_4VREFINT : stm32wbxx_hal_comp.h
  • COMP_INPUT_MINUS_IO1 : stm32wbxx_hal_comp.h
  • COMP_INPUT_MINUS_IO2 : stm32wbxx_hal_comp.h
  • COMP_INPUT_MINUS_IO3 : stm32wbxx_hal_comp.h
  • COMP_INPUT_MINUS_IO4 : stm32wbxx_hal_comp.h
  • COMP_INPUT_MINUS_IO5 : stm32wbxx_hal_comp.h
  • COMP_INPUT_MINUS_VREFINT : stm32wbxx_hal_comp.h
  • COMP_INPUT_PLUS_IO1 : stm32wbxx_hal_comp.h
  • COMP_INPUT_PLUS_IO2 : stm32wbxx_hal_comp.h
  • COMP_INPUT_PLUS_IO3 : stm32wbxx_hal_comp.h
  • COMP_OUTPUT_LEVEL_BITOFFSET_POS : stm32wbxx_hal_comp.c
  • COMP_OUTPUT_LEVEL_HIGH : stm32wbxx_hal_comp.h
  • COMP_OUTPUT_LEVEL_LOW : stm32wbxx_hal_comp.h
  • COMP_OUTPUTPOL_INVERTED : stm32wbxx_hal_comp.h
  • COMP_OUTPUTPOL_NONINVERTED : stm32wbxx_hal_comp.h
  • COMP_POWERMODE_HIGHSPEED : stm32wbxx_hal_comp.h
  • COMP_POWERMODE_MEDIUMSPEED : stm32wbxx_hal_comp.h
  • COMP_POWERMODE_ULTRALOWPOWER : stm32wbxx_hal_comp.h
  • COMP_STATE_BITFIELD_LOCK : stm32wbxx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_FALLING : stm32wbxx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_RISING : stm32wbxx_hal_comp.h
  • COMP_TRIGGERMODE_EVENT_RISING_FALLING : stm32wbxx_hal_comp.h
  • COMP_TRIGGERMODE_IT_FALLING : stm32wbxx_hal_comp.h
  • COMP_TRIGGERMODE_IT_RISING : stm32wbxx_hal_comp.h
  • COMP_TRIGGERMODE_IT_RISING_FALLING : stm32wbxx_hal_comp.h
  • COMP_TRIGGERMODE_NONE : stm32wbxx_hal_comp.h
  • COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON : stm32wbxx_hal_comp.h
  • COMP_WINDOWMODE_DISABLE : stm32wbxx_hal_comp.h
  • countof : stm32wbxx_ll_utils.c
  • CR_REG_INDEX : stm32wbxx_hal_rcc.h
  • CRC_INPUTDATA_FORMAT_BYTES : stm32wbxx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_HALFWORDS : stm32wbxx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_UNDEFINED : stm32wbxx_hal_crc.h
  • CRC_INPUTDATA_FORMAT_WORDS : stm32wbxx_hal_crc.h
  • CRC_INPUTDATA_INVERSION_BYTE : stm32wbxx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_HALFWORD : stm32wbxx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_NONE : stm32wbxx_hal_crc_ex.h
  • CRC_INPUTDATA_INVERSION_WORD : stm32wbxx_hal_crc_ex.h
  • CRC_OUTPUTDATA_INVERSION_DISABLE : stm32wbxx_hal_crc_ex.h
  • CRC_OUTPUTDATA_INVERSION_ENABLE : stm32wbxx_hal_crc_ex.h
  • CRC_POLYLENGTH_16B : stm32wbxx_hal_crc.h
  • CRC_POLYLENGTH_32B : stm32wbxx_hal_crc.h
  • CRC_POLYLENGTH_7B : stm32wbxx_hal_crc.h
  • CRC_POLYLENGTH_8B : stm32wbxx_hal_crc.h
  • CRRCR_REG_INDEX : stm32wbxx_hal_rcc.h
  • CRS_POSITION_FECAP : stm32wbxx_ll_crs.h
  • CRS_POSITION_FELIM : stm32wbxx_ll_crs.h
  • CRS_POSITION_TRIM : stm32wbxx_ll_crs.h
  • CRYP_AES_CBC : stm32wbxx_hal_cryp.h
  • CRYP_AES_CCM : stm32wbxx_hal_cryp.h
  • CRYP_AES_CTR : stm32wbxx_hal_cryp.h
  • CRYP_AES_ECB : stm32wbxx_hal_cryp.h
  • CRYP_AES_GCM_GMAC : stm32wbxx_hal_cryp.h
  • CRYP_CCF_CLEAR : stm32wbxx_hal_cryp.h
  • CRYP_CCM_CTR0_0 : stm32wbxx_hal_cryp_ex.c
  • CRYP_CCM_CTR0_3 : stm32wbxx_hal_cryp_ex.c
  • CRYP_CCM_CTR1_0 : stm32wbxx_hal_cryp.c
  • CRYP_CCM_CTR1_1 : stm32wbxx_hal_cryp.c
  • CRYP_CCM_CTR1_2 : stm32wbxx_hal_cryp.c
  • CRYP_DATATYPE_16B : stm32wbxx_hal_cryp.h
  • CRYP_DATATYPE_1B : stm32wbxx_hal_cryp.h
  • CRYP_DATATYPE_32B : stm32wbxx_hal_cryp.h
  • CRYP_DATATYPE_8B : stm32wbxx_hal_cryp.h
  • CRYP_DATAWIDTHUNIT_BYTE : stm32wbxx_hal_cryp.h
  • CRYP_DATAWIDTHUNIT_WORD : stm32wbxx_hal_cryp.h
  • CRYP_ERR_CLEAR : stm32wbxx_hal_cryp.h
  • CRYP_FLAG_BUSY : stm32wbxx_hal_cryp.h
  • CRYP_FLAG_CCF : stm32wbxx_hal_cryp.h
  • CRYP_FLAG_MASK : stm32wbxx_hal_cryp.h
  • CRYP_FLAG_RDERR : stm32wbxx_hal_cryp.h
  • CRYP_FLAG_WRERR : stm32wbxx_hal_cryp.h
  • CRYP_IT_CCF : stm32wbxx_hal_cryp.h
  • CRYP_IT_CCFIE : stm32wbxx_hal_cryp.h
  • CRYP_IT_ERRIE : stm32wbxx_hal_cryp.h
  • CRYP_IT_RDERR : stm32wbxx_hal_cryp.h
  • CRYP_IT_WRERR : stm32wbxx_hal_cryp.h
  • CRYP_KEYIVCONFIG_ALWAYS : stm32wbxx_hal_cryp.h
  • CRYP_KEYIVCONFIG_ONCE : stm32wbxx_hal_cryp.h
  • CRYP_KEYSIZE_128B : stm32wbxx_hal_cryp.h
  • CRYP_KEYSIZE_256B : stm32wbxx_hal_cryp.h
  • CRYP_OPERATINGMODE_DECRYPT : stm32wbxx_hal_cryp_ex.c , stm32wbxx_hal_cryp.c
  • CRYP_OPERATINGMODE_ENCRYPT : stm32wbxx_hal_cryp_ex.c , stm32wbxx_hal_cryp.c
  • CRYP_OPERATINGMODE_KEYDERIVATION : stm32wbxx_hal_cryp.c , stm32wbxx_hal_cryp_ex.c
  • CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT : stm32wbxx_hal_cryp.c , stm32wbxx_hal_cryp_ex.c
  • CRYP_PHASE_FINAL : stm32wbxx_hal_cryp.c , stm32wbxx_hal_cryp_ex.c
  • CRYP_PHASE_HEADER : stm32wbxx_hal_cryp_ex.c , stm32wbxx_hal_cryp.c
  • CRYP_PHASE_INIT : stm32wbxx_hal_cryp.c , stm32wbxx_hal_cryp_ex.c
  • CRYP_PHASE_PAYLOAD : stm32wbxx_hal_cryp_ex.c , stm32wbxx_hal_cryp.c
  • CRYP_PHASE_PROCESS : stm32wbxx_hal_cryp.c
  • CRYP_PHASE_READY : stm32wbxx_hal_cryp.c
  • CRYP_SET_PHASE : stm32wbxx_hal_cryp.c
  • CRYP_TIMEOUT_GCMCCMHEADERPHASE : stm32wbxx_hal_cryp.c
  • CRYP_TIMEOUT_GCMCCMINITPHASE : stm32wbxx_hal_cryp.c
  • CRYP_TIMEOUT_KEYPREPARATION : stm32wbxx_hal_cryp.c
  • CRYPEx_PHASE_FINAL : stm32wbxx_hal_cryp_ex.c
  • CRYPEx_PHASE_PROCESS : stm32wbxx_hal_cryp_ex.c
  • CSR_REG_INDEX : stm32wbxx_hal_rcc.h
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

  • File List
  • Globals
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- d -

  • DATA_CACHE_ENABLE : stm32wbxx_hal_conf.h
  • DEFAULT_CRC32_POLY : stm32wbxx_hal_crc.h
  • DEFAULT_CRC_INITVALUE : stm32wbxx_hal_crc.h
  • DEFAULT_INIT_VALUE_DISABLE : stm32wbxx_hal_crc.h
  • DEFAULT_INIT_VALUE_ENABLE : stm32wbxx_hal_crc.h
  • DEFAULT_POLYNOMIAL_DISABLE : stm32wbxx_hal_crc.h
  • DEFAULT_POLYNOMIAL_ENABLE : stm32wbxx_hal_crc.h
  • DMA_CIRCULAR : stm32wbxx_hal_dma.h
  • DMA_FLAG_GL1 : stm32wbxx_hal_dma.h
  • DMA_FLAG_GL2 : stm32wbxx_hal_dma.h
  • DMA_FLAG_GL3 : stm32wbxx_hal_dma.h
  • DMA_FLAG_GL4 : stm32wbxx_hal_dma.h
  • DMA_FLAG_GL5 : stm32wbxx_hal_dma.h
  • DMA_FLAG_GL6 : stm32wbxx_hal_dma.h
  • DMA_FLAG_GL7 : stm32wbxx_hal_dma.h
  • DMA_FLAG_HT1 : stm32wbxx_hal_dma.h
  • DMA_FLAG_HT2 : stm32wbxx_hal_dma.h
  • DMA_FLAG_HT3 : stm32wbxx_hal_dma.h
  • DMA_FLAG_HT4 : stm32wbxx_hal_dma.h
  • DMA_FLAG_HT5 : stm32wbxx_hal_dma.h
  • DMA_FLAG_HT6 : stm32wbxx_hal_dma.h
  • DMA_FLAG_HT7 : stm32wbxx_hal_dma.h
  • DMA_FLAG_TC1 : stm32wbxx_hal_dma.h
  • DMA_FLAG_TC2 : stm32wbxx_hal_dma.h
  • DMA_FLAG_TC3 : stm32wbxx_hal_dma.h
  • DMA_FLAG_TC4 : stm32wbxx_hal_dma.h
  • DMA_FLAG_TC5 : stm32wbxx_hal_dma.h
  • DMA_FLAG_TC6 : stm32wbxx_hal_dma.h
  • DMA_FLAG_TC7 : stm32wbxx_hal_dma.h
  • DMA_FLAG_TE1 : stm32wbxx_hal_dma.h
  • DMA_FLAG_TE2 : stm32wbxx_hal_dma.h
  • DMA_FLAG_TE3 : stm32wbxx_hal_dma.h
  • DMA_FLAG_TE4 : stm32wbxx_hal_dma.h
  • DMA_FLAG_TE5 : stm32wbxx_hal_dma.h
  • DMA_FLAG_TE6 : stm32wbxx_hal_dma.h
  • DMA_FLAG_TE7 : stm32wbxx_hal_dma.h
  • DMA_IT_HT : stm32wbxx_hal_dma.h
  • DMA_IT_TC : stm32wbxx_hal_dma.h
  • DMA_IT_TE : stm32wbxx_hal_dma.h
  • DMA_MDATAALIGN_BYTE : stm32wbxx_hal_dma.h
  • DMA_MDATAALIGN_HALFWORD : stm32wbxx_hal_dma.h
  • DMA_MDATAALIGN_WORD : stm32wbxx_hal_dma.h
  • DMA_MEMORY_TO_MEMORY : stm32wbxx_hal_dma.h
  • DMA_MEMORY_TO_PERIPH : stm32wbxx_hal_dma.h
  • DMA_MINC_DISABLE : stm32wbxx_hal_dma.h
  • DMA_MINC_ENABLE : stm32wbxx_hal_dma.h
  • DMA_NORMAL : stm32wbxx_hal_dma.h
  • DMA_PDATAALIGN_BYTE : stm32wbxx_hal_dma.h
  • DMA_PDATAALIGN_HALFWORD : stm32wbxx_hal_dma.h
  • DMA_PDATAALIGN_WORD : stm32wbxx_hal_dma.h
  • DMA_PERIPH_TO_MEMORY : stm32wbxx_hal_dma.h
  • DMA_PINC_DISABLE : stm32wbxx_hal_dma.h
  • DMA_PINC_ENABLE : stm32wbxx_hal_dma.h
  • DMA_PRIORITY_HIGH : stm32wbxx_hal_dma.h
  • DMA_PRIORITY_LOW : stm32wbxx_hal_dma.h
  • DMA_PRIORITY_MEDIUM : stm32wbxx_hal_dma.h
  • DMA_PRIORITY_VERY_HIGH : stm32wbxx_hal_dma.h
  • DMA_REQUEST_ADC1 : stm32wbxx_hal_dma.h
  • DMA_REQUEST_AES1_IN : stm32wbxx_hal_dma.h
  • DMA_REQUEST_AES1_OUT : stm32wbxx_hal_dma.h
  • DMA_REQUEST_AES2_IN : stm32wbxx_hal_dma.h
  • DMA_REQUEST_AES2_OUT : stm32wbxx_hal_dma.h
  • DMA_REQUEST_GENERATOR0 : stm32wbxx_hal_dma.h
  • DMA_REQUEST_GENERATOR1 : stm32wbxx_hal_dma.h
  • DMA_REQUEST_GENERATOR2 : stm32wbxx_hal_dma.h
  • DMA_REQUEST_GENERATOR3 : stm32wbxx_hal_dma.h
  • DMA_REQUEST_I2C1_RX : stm32wbxx_hal_dma.h
  • DMA_REQUEST_I2C1_TX : stm32wbxx_hal_dma.h
  • DMA_REQUEST_I2C3_RX : stm32wbxx_hal_dma.h
  • DMA_REQUEST_I2C3_TX : stm32wbxx_hal_dma.h
  • DMA_REQUEST_LPUART1_RX : stm32wbxx_hal_dma.h
  • DMA_REQUEST_LPUART1_TX : stm32wbxx_hal_dma.h
  • DMA_REQUEST_MEM2MEM : stm32wbxx_hal_dma.h
  • DMA_REQUEST_QUADSPI : stm32wbxx_hal_dma.h
  • DMA_REQUEST_SAI1_A : stm32wbxx_hal_dma.h
  • DMA_REQUEST_SAI1_B : stm32wbxx_hal_dma.h
  • DMA_REQUEST_SPI1_RX : stm32wbxx_hal_dma.h
  • DMA_REQUEST_SPI1_TX : stm32wbxx_hal_dma.h
  • DMA_REQUEST_SPI2_RX : stm32wbxx_hal_dma.h
  • DMA_REQUEST_SPI2_TX : stm32wbxx_hal_dma.h
  • DMA_REQUEST_TIM16_CH1 : stm32wbxx_hal_dma.h
  • DMA_REQUEST_TIM16_UP : stm32wbxx_hal_dma.h
  • DMA_REQUEST_TIM17_CH1 : stm32wbxx_hal_dma.h
  • DMA_REQUEST_TIM17_UP : stm32wbxx_hal_dma.h
  • DMA_REQUEST_TIM1_CH1 : stm32wbxx_hal_dma.h
  • DMA_REQUEST_TIM1_CH2 : stm32wbxx_hal_dma.h
  • DMA_REQUEST_TIM1_CH3 : stm32wbxx_hal_dma.h
  • DMA_REQUEST_TIM1_CH4 : stm32wbxx_hal_dma.h
  • DMA_REQUEST_TIM1_COM : stm32wbxx_hal_dma.h
  • DMA_REQUEST_TIM1_TRIG : stm32wbxx_hal_dma.h
  • DMA_REQUEST_TIM1_UP : stm32wbxx_hal_dma.h
  • DMA_REQUEST_TIM2_CH1 : stm32wbxx_hal_dma.h
  • DMA_REQUEST_TIM2_CH2 : stm32wbxx_hal_dma.h
  • DMA_REQUEST_TIM2_CH3 : stm32wbxx_hal_dma.h
  • DMA_REQUEST_TIM2_CH4 : stm32wbxx_hal_dma.h
  • DMA_REQUEST_TIM2_UP : stm32wbxx_hal_dma.h
  • DMA_REQUEST_USART1_RX : stm32wbxx_hal_dma.h
  • DMA_REQUEST_USART1_TX : stm32wbxx_hal_dma.h
  • DMAMUX_CCR_SIZE : stm32wbxx_ll_dmamux.h
  • DMAMUX_RGCR_SIZE : stm32wbxx_ll_dmamux.h
  • DT_DELAY_1 : stm32wbxx_ll_tim.h
  • DT_DELAY_2 : stm32wbxx_ll_tim.h
  • DT_DELAY_3 : stm32wbxx_ll_tim.h
  • DT_DELAY_4 : stm32wbxx_ll_tim.h
  • DT_RANGE_1 : stm32wbxx_ll_tim.h
  • DT_RANGE_2 : stm32wbxx_ll_tim.h
  • DT_RANGE_3 : stm32wbxx_ll_tim.h
  • DT_RANGE_4 : stm32wbxx_ll_tim.h
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

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- e -

  • EXTERNAL_SAI1_CLOCK_VALUE : stm32wbxx_hal_conf.h
  • EXTI_CONFIG : stm32wbxx_hal_exti.h
  • EXTI_CONFIG_OFFSET : stm32wbxx_hal_exti.c
  • EXTI_DIRECT : stm32wbxx_hal_exti.h
  • EXTI_EVENT : stm32wbxx_hal_exti.h
  • EXTI_EVENT_PRESENCE_MASK : stm32wbxx_hal_exti.h
  • EXTI_EVENT_PRESENCE_SHIFT : stm32wbxx_hal_exti.h
  • EXTI_GPIO : stm32wbxx_hal_exti.h
  • EXTI_GPIOA : stm32wbxx_hal_exti.h
  • EXTI_GPIOB : stm32wbxx_hal_exti.h
  • EXTI_GPIOC : stm32wbxx_hal_exti.h
  • EXTI_GPIOD : stm32wbxx_hal_exti.h
  • EXTI_GPIOE : stm32wbxx_hal_exti.h
  • EXTI_GPIOH : stm32wbxx_hal_exti.h
  • EXTI_LINE_0 : stm32wbxx_hal_exti.h
  • EXTI_LINE_1 : stm32wbxx_hal_exti.h
  • EXTI_LINE_10 : stm32wbxx_hal_exti.h
  • EXTI_LINE_11 : stm32wbxx_hal_exti.h
  • EXTI_LINE_12 : stm32wbxx_hal_exti.h
  • EXTI_LINE_13 : stm32wbxx_hal_exti.h
  • EXTI_LINE_14 : stm32wbxx_hal_exti.h
  • EXTI_LINE_15 : stm32wbxx_hal_exti.h
  • EXTI_LINE_16 : stm32wbxx_hal_exti.h
  • EXTI_LINE_17 : stm32wbxx_hal_exti.h
  • EXTI_LINE_18 : stm32wbxx_hal_exti.h
  • EXTI_LINE_19 : stm32wbxx_hal_exti.h
  • EXTI_LINE_2 : stm32wbxx_hal_exti.h
  • EXTI_LINE_20 : stm32wbxx_hal_exti.h
  • EXTI_LINE_21 : stm32wbxx_hal_exti.h
  • EXTI_LINE_22 : stm32wbxx_hal_exti.h
  • EXTI_LINE_23 : stm32wbxx_hal_exti.h
  • EXTI_LINE_24 : stm32wbxx_hal_exti.h
  • EXTI_LINE_25 : stm32wbxx_hal_exti.h
  • EXTI_LINE_26 : stm32wbxx_hal_exti.h
  • EXTI_LINE_27 : stm32wbxx_hal_exti.h
  • EXTI_LINE_28 : stm32wbxx_hal_exti.h
  • EXTI_LINE_29 : stm32wbxx_hal_exti.h
  • EXTI_LINE_3 : stm32wbxx_hal_exti.h
  • EXTI_LINE_30 : stm32wbxx_hal_exti.h
  • EXTI_LINE_31 : stm32wbxx_hal_exti.h
  • EXTI_LINE_32 : stm32wbxx_hal_exti.h
  • EXTI_LINE_33 : stm32wbxx_hal_exti.h
  • EXTI_LINE_34 : stm32wbxx_hal_exti.h
  • EXTI_LINE_35 : stm32wbxx_hal_exti.h
  • EXTI_LINE_36 : stm32wbxx_hal_exti.h
  • EXTI_LINE_37 : stm32wbxx_hal_exti.h
  • EXTI_LINE_38 : stm32wbxx_hal_exti.h
  • EXTI_LINE_39 : stm32wbxx_hal_exti.h
  • EXTI_LINE_4 : stm32wbxx_hal_exti.h
  • EXTI_LINE_40 : stm32wbxx_hal_exti.h
  • EXTI_LINE_41 : stm32wbxx_hal_exti.h
  • EXTI_LINE_42 : stm32wbxx_hal_exti.h
  • EXTI_LINE_43 : stm32wbxx_hal_exti.h
  • EXTI_LINE_44 : stm32wbxx_hal_exti.h
  • EXTI_LINE_45 : stm32wbxx_hal_exti.h
  • EXTI_LINE_46 : stm32wbxx_hal_exti.h
  • EXTI_LINE_47 : stm32wbxx_hal_exti.h
  • EXTI_LINE_48 : stm32wbxx_hal_exti.h
  • EXTI_LINE_5 : stm32wbxx_hal_exti.h
  • EXTI_LINE_6 : stm32wbxx_hal_exti.h
  • EXTI_LINE_7 : stm32wbxx_hal_exti.h
  • EXTI_LINE_8 : stm32wbxx_hal_exti.h
  • EXTI_LINE_9 : stm32wbxx_hal_exti.h
  • EXTI_LINE_NB : stm32wbxx_hal_exti.h
  • EXTI_MODE : stm32wbxx_hal_gpio.c
  • EXTI_MODE_EVENT : stm32wbxx_hal_exti.h
  • EXTI_MODE_INTERRUPT : stm32wbxx_hal_exti.h
  • EXTI_MODE_MASK : stm32wbxx_hal_exti.h
  • EXTI_MODE_NONE : stm32wbxx_hal_exti.h
  • EXTI_MODE_OFFSET : stm32wbxx_hal_exti.c
  • EXTI_PIN_MASK : stm32wbxx_hal_exti.h
  • EXTI_PROPERTY_MASK : stm32wbxx_hal_exti.h
  • EXTI_PROPERTY_SHIFT : stm32wbxx_hal_exti.h
  • EXTI_REG1 : stm32wbxx_hal_exti.h
  • EXTI_REG2 : stm32wbxx_hal_exti.h
  • EXTI_REG_MASK : stm32wbxx_hal_exti.h
  • EXTI_REG_SHIFT : stm32wbxx_hal_exti.h
  • EXTI_RESERVED : stm32wbxx_hal_exti.h
  • EXTI_TRIGGER_FALLING : stm32wbxx_hal_exti.h
  • EXTI_TRIGGER_MASK : stm32wbxx_hal_exti.h
  • EXTI_TRIGGER_NONE : stm32wbxx_hal_exti.h
  • EXTI_TRIGGER_RISING : stm32wbxx_hal_exti.h
  • EXTI_TRIGGER_RISING_FALLING : stm32wbxx_hal_exti.h
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

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- f -

  • FALLING_EDGE : stm32wbxx_hal_gpio.c
  • FLASH_BANK_SIZE : stm32wbxx_hal_flash.h
  • FLASH_END_ADDR : stm32wbxx_hal_flash.h
  • FLASH_FLAG_ALL_ERRORS : stm32wbxx_hal_flash.h
  • FLASH_FLAG_BSY : stm32wbxx_hal_flash.h
  • FLASH_FLAG_CFGBSY : stm32wbxx_hal_flash.h
  • FLASH_FLAG_ECCC : stm32wbxx_hal_flash.h
  • FLASH_FLAG_ECCD : stm32wbxx_hal_flash.h
  • FLASH_FLAG_ECCR_ERRORS : stm32wbxx_hal_flash.h
  • FLASH_FLAG_EOP : stm32wbxx_hal_flash.h
  • FLASH_FLAG_FASTERR : stm32wbxx_hal_flash.h
  • FLASH_FLAG_MISERR : stm32wbxx_hal_flash.h
  • FLASH_FLAG_OPERR : stm32wbxx_hal_flash.h
  • FLASH_FLAG_OPTNV : stm32wbxx_hal_flash.h
  • FLASH_FLAG_OPTVERR : stm32wbxx_hal_flash.h
  • FLASH_FLAG_PESD : stm32wbxx_hal_flash.h
  • FLASH_FLAG_PGAERR : stm32wbxx_hal_flash.h
  • FLASH_FLAG_PGSERR : stm32wbxx_hal_flash.h
  • FLASH_FLAG_PROGERR : stm32wbxx_hal_flash.h
  • FLASH_FLAG_RDERR : stm32wbxx_hal_flash.h
  • FLASH_FLAG_SIZERR : stm32wbxx_hal_flash.h
  • FLASH_FLAG_SR_ERRORS : stm32wbxx_hal_flash.h
  • FLASH_FLAG_WRPERR : stm32wbxx_hal_flash.h
  • FLASH_IT_ECCC : stm32wbxx_hal_flash.h
  • FLASH_IT_EOP : stm32wbxx_hal_flash.h
  • FLASH_IT_OPERR : stm32wbxx_hal_flash.h
  • FLASH_IT_RDERR : stm32wbxx_hal_flash.h
  • FLASH_KEY1 : stm32wbxx_hal_flash.h
  • FLASH_KEY2 : stm32wbxx_hal_flash.h
  • FLASH_LATENCY_0 : stm32wbxx_hal_flash.h
  • FLASH_LATENCY_1 : stm32wbxx_hal_flash.h
  • FLASH_LATENCY_2 : stm32wbxx_hal_flash.h
  • FLASH_LATENCY_3 : stm32wbxx_hal_flash.h
  • FLASH_NB_DOUBLE_WORDS_IN_ROW : stm32wbxx_hal_flash.c
  • FLASH_OPTKEY1 : stm32wbxx_hal_flash.h
  • FLASH_OPTKEY2 : stm32wbxx_hal_flash.h
  • FLASH_PAGE_NB : stm32wbxx_hal_flash.h
  • FLASH_PAGE_SIZE : stm32wbxx_hal_flash.h
  • FLASH_PCROP_GRANULARITY : stm32wbxx_hal_flash.h
  • FLASH_PCROP_GRANULARITY_OFFSET : stm32wbxx_hal_flash.h
  • FLASH_PROG_EMPTY : stm32wbxx_hal_flash_ex.h
  • FLASH_PROG_NOT_EMPTY : stm32wbxx_hal_flash_ex.h
  • FLASH_TIMEOUT_VALUE : stm32wbxx_hal_flash.h
  • FLASH_TYPEERASE_MASSERASE : stm32wbxx_hal_flash.h
  • FLASH_TYPEERASE_PAGES : stm32wbxx_hal_flash.h
  • FLASH_TYPENONE : stm32wbxx_hal_flash.h
  • FLASH_TYPEPROGRAM_DOUBLEWORD : stm32wbxx_hal_flash.h
  • FLASH_TYPEPROGRAM_FAST : stm32wbxx_hal_flash.h
  • FLASHSIZE_BASE_ADDRESS : stm32wbxx_ll_utils.h
  • FTLSI2TRIM : stm32wbxx_hal_rcc_ex.c
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

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  • Globals
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- g -

  • GPIO_AF0_JTCK_SWCLK : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF0_JTD_TRACE : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF0_JTDI : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF0_JTMS_SWDIO : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF0_LSCO : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF0_MCO : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF0_NJTRST : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF0_RTC_OUT : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF0_RTC_REFIN : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF0_SYS : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF0_TRACECK : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF0_TRACED0 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF0_TRACED1 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF0_TRACED2 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF0_TRACED3 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF0_TRIG_INOUT : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF10_QUADSPI : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF10_USB : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF11_LCD : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF12_COMP1 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF12_COMP2 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF12_TIM1 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF13_SAI1 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF14_LPTIM2 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF14_TIM16 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF14_TIM17 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF14_TIM2 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF15_EVENTOUT : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF1_LPTIM1 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF1_TIM1 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF1_TIM2 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF2_TIM1 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF2_TIM2 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF3_SAI1 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF3_SPI2 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF3_TIM1 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF4_I2C1 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF4_I2C3 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF5_SPI1 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF5_SPI2 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_LSCO : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_MCO : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_DTB0 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_DTB1 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_DTB10 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_DTB11 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_DTB12 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_DTB13 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_DTB14 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_DTB15 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_DTB16 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_DTB17 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_DTB18 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_DTB2 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_DTB3 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_DTB4 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_DTB5 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_DTB6 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_DTB7 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_DTB8 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_DTB9 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_MISO : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_MOSI : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_NSS : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF6_RF_SCK : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF7_USART1 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF8_IR : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF8_LPUART1 : stm32wbxx_hal_gpio_ex.h
  • GPIO_AF9_TSC : stm32wbxx_hal_gpio_ex.h
  • GPIO_GET_INDEX : stm32wbxx_hal_gpio_ex.h
  • GPIO_MODE : stm32wbxx_hal_gpio.c
  • GPIO_MODE_AF_OD : stm32wbxx_hal_gpio.h
  • GPIO_MODE_AF_PP : stm32wbxx_hal_gpio.h
  • GPIO_MODE_ANALOG : stm32wbxx_hal_gpio.h
  • GPIO_MODE_EVT : stm32wbxx_hal_gpio.c
  • GPIO_MODE_EVT_FALLING : stm32wbxx_hal_gpio.h
  • GPIO_MODE_EVT_RISING : stm32wbxx_hal_gpio.h
  • GPIO_MODE_EVT_RISING_FALLING : stm32wbxx_hal_gpio.h
  • GPIO_MODE_INPUT : stm32wbxx_hal_gpio.h
  • GPIO_MODE_IT : stm32wbxx_hal_gpio.c
  • GPIO_MODE_IT_FALLING : stm32wbxx_hal_gpio.h
  • GPIO_MODE_IT_RISING : stm32wbxx_hal_gpio.h
  • GPIO_MODE_IT_RISING_FALLING : stm32wbxx_hal_gpio.h
  • GPIO_MODE_OUTPUT_OD : stm32wbxx_hal_gpio.h
  • GPIO_MODE_OUTPUT_PP : stm32wbxx_hal_gpio.h
  • GPIO_NOPULL : stm32wbxx_hal_gpio.h
  • GPIO_NUMBER : stm32wbxx_hal_gpio.c
  • GPIO_OUTPUT_TYPE : stm32wbxx_hal_gpio.c
  • GPIO_PIN_0 : stm32wbxx_hal_gpio.h
  • GPIO_PIN_1 : stm32wbxx_hal_gpio.h
  • GPIO_PIN_10 : stm32wbxx_hal_gpio.h
  • GPIO_PIN_11 : stm32wbxx_hal_gpio.h
  • GPIO_PIN_12 : stm32wbxx_hal_gpio.h
  • GPIO_PIN_13 : stm32wbxx_hal_gpio.h
  • GPIO_PIN_14 : stm32wbxx_hal_gpio.h
  • GPIO_PIN_15 : stm32wbxx_hal_gpio.h
  • GPIO_PIN_2 : stm32wbxx_hal_gpio.h
  • GPIO_PIN_3 : stm32wbxx_hal_gpio.h
  • GPIO_PIN_4 : stm32wbxx_hal_gpio.h
  • GPIO_PIN_5 : stm32wbxx_hal_gpio.h
  • GPIO_PIN_6 : stm32wbxx_hal_gpio.h
  • GPIO_PIN_7 : stm32wbxx_hal_gpio.h
  • GPIO_PIN_8 : stm32wbxx_hal_gpio.h
  • GPIO_PIN_9 : stm32wbxx_hal_gpio.h
  • GPIO_PIN_All : stm32wbxx_hal_gpio.h
  • GPIO_PIN_MASK : stm32wbxx_hal_gpio.h
  • GPIO_PULLDOWN : stm32wbxx_hal_gpio.h
  • GPIO_PULLUP : stm32wbxx_hal_gpio.h
  • GPIO_SPEED_FREQ_HIGH : stm32wbxx_hal_gpio.h
  • GPIO_SPEED_FREQ_LOW : stm32wbxx_hal_gpio.h
  • GPIO_SPEED_FREQ_MEDIUM : stm32wbxx_hal_gpio.h
  • GPIO_SPEED_FREQ_VERY_HIGH : stm32wbxx_hal_gpio.h
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

  • File List
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- h -

  • HAL_ADC_ERROR_DMA : stm32wbxx_hal_adc.h
  • HAL_ADC_ERROR_INTERNAL : stm32wbxx_hal_adc.h
  • HAL_ADC_ERROR_INVALID_CALLBACK : stm32wbxx_hal_adc.h
  • HAL_ADC_ERROR_JQOVF : stm32wbxx_hal_adc.h
  • HAL_ADC_ERROR_NONE : stm32wbxx_hal_adc.h
  • HAL_ADC_ERROR_OVR : stm32wbxx_hal_adc.h
  • HAL_ADC_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_ADC_STATE_AWD1 : stm32wbxx_hal_adc.h
  • HAL_ADC_STATE_AWD2 : stm32wbxx_hal_adc.h
  • HAL_ADC_STATE_AWD3 : stm32wbxx_hal_adc.h
  • HAL_ADC_STATE_BUSY_INTERNAL : stm32wbxx_hal_adc.h
  • HAL_ADC_STATE_ERROR_CONFIG : stm32wbxx_hal_adc.h
  • HAL_ADC_STATE_ERROR_DMA : stm32wbxx_hal_adc.h
  • HAL_ADC_STATE_ERROR_INTERNAL : stm32wbxx_hal_adc.h
  • HAL_ADC_STATE_INJ_BUSY : stm32wbxx_hal_adc.h
  • HAL_ADC_STATE_INJ_EOC : stm32wbxx_hal_adc.h
  • HAL_ADC_STATE_INJ_JQOVF : stm32wbxx_hal_adc.h
  • HAL_ADC_STATE_MULTIMODE_SLAVE : stm32wbxx_hal_adc.h
  • HAL_ADC_STATE_READY : stm32wbxx_hal_adc.h
  • HAL_ADC_STATE_REG_BUSY : stm32wbxx_hal_adc.h
  • HAL_ADC_STATE_REG_EOC : stm32wbxx_hal_adc.h
  • HAL_ADC_STATE_REG_EOSMP : stm32wbxx_hal_adc.h
  • HAL_ADC_STATE_REG_OVR : stm32wbxx_hal_adc.h
  • HAL_ADC_STATE_RESET : stm32wbxx_hal_adc.h
  • HAL_ADC_STATE_TIMEOUT : stm32wbxx_hal_adc.h
  • HAL_COMP_ERROR_INVALID_CALLBACK : stm32wbxx_hal_comp.h
  • HAL_COMP_ERROR_NONE : stm32wbxx_hal_comp.h
  • HAL_COMP_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_CORTEX_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_CRC_Input_Data_Reverse : stm32wbxx_hal_crc.h
  • HAL_CRC_LENGTH_16B : stm32wbxx_hal_crc.h
  • HAL_CRC_LENGTH_32B : stm32wbxx_hal_crc.h
  • HAL_CRC_LENGTH_7B : stm32wbxx_hal_crc.h
  • HAL_CRC_LENGTH_8B : stm32wbxx_hal_crc.h
  • HAL_CRC_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_CRC_Output_Data_Reverse : stm32wbxx_hal_crc.h
  • HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE : stm32wbxx_hal_cryp.h
  • HAL_CRYP_ERROR_BUSY : stm32wbxx_hal_cryp.h
  • HAL_CRYP_ERROR_DMA : stm32wbxx_hal_cryp.h
  • HAL_CRYP_ERROR_INVALID_CALLBACK : stm32wbxx_hal_cryp.h
  • HAL_CRYP_ERROR_NONE : stm32wbxx_hal_cryp.h
  • HAL_CRYP_ERROR_NOT_SUPPORTED : stm32wbxx_hal_cryp.h
  • HAL_CRYP_ERROR_READ : stm32wbxx_hal_cryp.h
  • HAL_CRYP_ERROR_TIMEOUT : stm32wbxx_hal_cryp.h
  • HAL_CRYP_ERROR_WRITE : stm32wbxx_hal_cryp.h
  • HAL_CRYP_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_DMA_ERROR_NO_XFER : stm32wbxx_hal_dma.h
  • HAL_DMA_ERROR_NONE : stm32wbxx_hal_dma.h
  • HAL_DMA_ERROR_NOT_SUPPORTED : stm32wbxx_hal_dma.h
  • HAL_DMA_ERROR_REQGEN : stm32wbxx_hal_dma.h
  • HAL_DMA_ERROR_SYNC : stm32wbxx_hal_dma.h
  • HAL_DMA_ERROR_TE : stm32wbxx_hal_dma.h
  • HAL_DMA_ERROR_TIMEOUT : stm32wbxx_hal_dma.h
  • HAL_DMA_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI0 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI1 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI10 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI11 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI12 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI13 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI14 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI15 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI2 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI3 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI4 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI5 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI6 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI7 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI8 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_EXTI9 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI0 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI1 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI10 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI11 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI12 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI13 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI14 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI15 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI2 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI3 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI4 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI5 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI6 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI7 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI8 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_EXTI9 : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_LPTIM1_OUT : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX1_SYNC_LPTIM2_OUT : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX_REQ_GEN_FALLING : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX_REQ_GEN_NO_EVENT : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX_REQ_GEN_RISING : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX_REQ_GEN_RISING_FALLING : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_FALLING : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_NO_EVENT : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_RISING : stm32wbxx_hal_dma_ex.h
  • HAL_DMAMUX_SYNC_RISING_FALLING : stm32wbxx_hal_dma_ex.h
  • HAL_EXTI_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_FLASH_ERROR_FAST : stm32wbxx_hal_flash.h
  • HAL_FLASH_ERROR_MIS : stm32wbxx_hal_flash.h
  • HAL_FLASH_ERROR_NONE : stm32wbxx_hal_flash.h
  • HAL_FLASH_ERROR_OP : stm32wbxx_hal_flash.h
  • HAL_FLASH_ERROR_OPTV : stm32wbxx_hal_flash.h
  • HAL_FLASH_ERROR_PGA : stm32wbxx_hal_flash.h
  • HAL_FLASH_ERROR_PGS : stm32wbxx_hal_flash.h
  • HAL_FLASH_ERROR_PROG : stm32wbxx_hal_flash.h
  • HAL_FLASH_ERROR_RD : stm32wbxx_hal_flash.h
  • HAL_FLASH_ERROR_SIZ : stm32wbxx_hal_flash.h
  • HAL_FLASH_ERROR_WRP : stm32wbxx_hal_flash.h
  • HAL_FLASH_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_GPIO_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_HSEM_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_I2C_ERROR_AF : stm32wbxx_hal_i2c.h
  • HAL_I2C_ERROR_ARLO : stm32wbxx_hal_i2c.h
  • HAL_I2C_ERROR_BERR : stm32wbxx_hal_i2c.h
  • HAL_I2C_ERROR_DMA : stm32wbxx_hal_i2c.h
  • HAL_I2C_ERROR_DMA_PARAM : stm32wbxx_hal_i2c.h
  • HAL_I2C_ERROR_INVALID_CALLBACK : stm32wbxx_hal_i2c.h
  • HAL_I2C_ERROR_INVALID_PARAM : stm32wbxx_hal_i2c.h
  • HAL_I2C_ERROR_NONE : stm32wbxx_hal_i2c.h
  • HAL_I2C_ERROR_OVR : stm32wbxx_hal_i2c.h
  • HAL_I2C_ERROR_SIZE : stm32wbxx_hal_i2c.h
  • HAL_I2C_ERROR_TIMEOUT : stm32wbxx_hal_i2c.h
  • HAL_I2C_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_IPCC_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_IRDA_ERROR_BUSY : stm32wbxx_hal_irda.h
  • HAL_IRDA_ERROR_DMA : stm32wbxx_hal_irda.h
  • HAL_IRDA_ERROR_FE : stm32wbxx_hal_irda.h
  • HAL_IRDA_ERROR_INVALID_CALLBACK : stm32wbxx_hal_irda.h
  • HAL_IRDA_ERROR_NE : stm32wbxx_hal_irda.h
  • HAL_IRDA_ERROR_NONE : stm32wbxx_hal_irda.h
  • HAL_IRDA_ERROR_ORE : stm32wbxx_hal_irda.h
  • HAL_IRDA_ERROR_PE : stm32wbxx_hal_irda.h
  • HAL_IRDA_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_IRDA_STATE_BUSY : stm32wbxx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_RX : stm32wbxx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX : stm32wbxx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX_RX : stm32wbxx_hal_irda.h
  • HAL_IRDA_STATE_ERROR : stm32wbxx_hal_irda.h
  • HAL_IRDA_STATE_READY : stm32wbxx_hal_irda.h
  • HAL_IRDA_STATE_RESET : stm32wbxx_hal_irda.h
  • HAL_IRDA_STATE_TIMEOUT : stm32wbxx_hal_irda.h
  • HAL_IWDG_DEFAULT_TIMEOUT : stm32wbxx_hal_iwdg.c
  • HAL_IWDG_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_LCD_ERROR_ENS : stm32wbxx_hal_lcd.h
  • HAL_LCD_ERROR_FCRSF : stm32wbxx_hal_lcd.h
  • HAL_LCD_ERROR_NONE : stm32wbxx_hal_lcd.h
  • HAL_LCD_ERROR_RDY : stm32wbxx_hal_lcd.h
  • HAL_LCD_ERROR_UDD : stm32wbxx_hal_lcd.h
  • HAL_LCD_ERROR_UDR : stm32wbxx_hal_lcd.h
  • HAL_LCD_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_LPTIM_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_PCD_ERROR_INVALID_CALLBACK : stm32wbxx_hal_pcd.h
  • HAL_PCD_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_PKA_ERROR_ADDRERR : stm32wbxx_hal_pka.h
  • HAL_PKA_ERROR_INVALID_CALLBACK : stm32wbxx_hal_pka.h
  • HAL_PKA_ERROR_NONE : stm32wbxx_hal_pka.h
  • HAL_PKA_ERROR_OPERATION : stm32wbxx_hal_pka.h
  • HAL_PKA_ERROR_RAMERR : stm32wbxx_hal_pka.h
  • HAL_PKA_ERROR_TIMEOUT : stm32wbxx_hal_pka.h
  • HAL_PKA_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_PWR_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_QSPI_ERROR_DMA : stm32wbxx_hal_qspi.h
  • HAL_QSPI_ERROR_INVALID_CALLBACK : stm32wbxx_hal_qspi.h
  • HAL_QSPI_ERROR_INVALID_PARAM : stm32wbxx_hal_qspi.h
  • HAL_QSPI_ERROR_NONE : stm32wbxx_hal_qspi.h
  • HAL_QSPI_ERROR_TIMEOUT : stm32wbxx_hal_qspi.h
  • HAL_QSPI_ERROR_TRANSFER : stm32wbxx_hal_qspi.h
  • HAL_QSPI_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_QSPI_TIMEOUT_DEFAULT_VALUE : stm32wbxx_hal_qspi.h
  • HAL_RCC_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_RNG_ERROR_BUSY : stm32wbxx_hal_rng.h
  • HAL_RNG_ERROR_CLOCK : stm32wbxx_hal_rng.h
  • HAL_RNG_ERROR_INVALID_CALLBACK : stm32wbxx_hal_rng.h
  • HAL_RNG_ERROR_NONE : stm32wbxx_hal_rng.h
  • HAL_RNG_ERROR_SEED : stm32wbxx_hal_rng.h
  • HAL_RNG_ERROR_TIMEOUT : stm32wbxx_hal_rng.h
  • HAL_RNG_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_RTC_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_SAI_ERROR_AFSDET : stm32wbxx_hal_sai.h
  • HAL_SAI_ERROR_CNREADY : stm32wbxx_hal_sai.h
  • HAL_SAI_ERROR_DMA : stm32wbxx_hal_sai.h
  • HAL_SAI_ERROR_INVALID_CALLBACK : stm32wbxx_hal_sai.h
  • HAL_SAI_ERROR_LFSDET : stm32wbxx_hal_sai.h
  • HAL_SAI_ERROR_NONE : stm32wbxx_hal_sai.h
  • HAL_SAI_ERROR_OVR : stm32wbxx_hal_sai.h
  • HAL_SAI_ERROR_TIMEOUT : stm32wbxx_hal_sai.h
  • HAL_SAI_ERROR_UDR : stm32wbxx_hal_sai.h
  • HAL_SAI_ERROR_WCKCFG : stm32wbxx_hal_sai.h
  • HAL_SAI_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_SMARTCARD_ERROR_DMA : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_FE : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_INVALID_CALLBACK : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NE : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NONE : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_ORE : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_PE : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_RTO : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_SMARTCARD_STATE_BUSY : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_RX : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX_RX : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_ERROR : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_READY : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_RESET : stm32wbxx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_TIMEOUT : stm32wbxx_hal_smartcard.h
  • HAL_SMBUS_ERROR_ACKF : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_ERROR_ALERT : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_ERROR_ARLO : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_ERROR_BERR : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_ERROR_BUSTIMEOUT : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_ERROR_HALTIMEOUT : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_ERROR_INVALID_CALLBACK : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_ERROR_INVALID_PARAM : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_ERROR_NONE : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_ERROR_OVR : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_ERROR_PECERR : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_SMBUS_STATE_BUSY : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_STATE_ERROR : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_STATE_LISTEN : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_STATE_MASTER_BUSY_RX : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_STATE_MASTER_BUSY_TX : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_STATE_READY : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_STATE_RESET : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_STATE_SLAVE_BUSY_RX : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_STATE_SLAVE_BUSY_TX : stm32wbxx_hal_smbus.h
  • HAL_SMBUS_STATE_TIMEOUT : stm32wbxx_hal_smbus.h
  • HAL_SPI_ERROR_ABORT : stm32wbxx_hal_spi.h
  • HAL_SPI_ERROR_CRC : stm32wbxx_hal_spi.h
  • HAL_SPI_ERROR_DMA : stm32wbxx_hal_spi.h
  • HAL_SPI_ERROR_FLAG : stm32wbxx_hal_spi.h
  • HAL_SPI_ERROR_FRE : stm32wbxx_hal_spi.h
  • HAL_SPI_ERROR_INVALID_CALLBACK : stm32wbxx_hal_spi.h
  • HAL_SPI_ERROR_MODF : stm32wbxx_hal_spi.h
  • HAL_SPI_ERROR_NONE : stm32wbxx_hal_spi.h
  • HAL_SPI_ERROR_OVR : stm32wbxx_hal_spi.h
  • HAL_SPI_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_SYSCFG_SECURE_ACCESS_AES1 : stm32wbxx_hal.h
  • HAL_SYSCFG_SECURE_ACCESS_AES2 : stm32wbxx_hal.h
  • HAL_SYSCFG_SECURE_ACCESS_PKA : stm32wbxx_hal.h
  • HAL_SYSCFG_SECURE_ACCESS_RNG : stm32wbxx_hal.h
  • HAL_TICK_FREQ_100HZ : stm32wbxx_hal.h
  • HAL_TICK_FREQ_10HZ : stm32wbxx_hal.h
  • HAL_TICK_FREQ_1KHZ : stm32wbxx_hal.h
  • HAL_TICK_FREQ_DEFAULT : stm32wbxx_hal.h
  • HAL_TIM_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_TIMEOUT_ADDR : stm32wbxx_hal_smbus.c
  • HAL_TIMEOUT_BUSY : stm32wbxx_hal_smbus.c
  • HAL_TIMEOUT_DIR : stm32wbxx_hal_smbus.c
  • HAL_TIMEOUT_RXNE : stm32wbxx_hal_smbus.c
  • HAL_TIMEOUT_STOPF : stm32wbxx_hal_smbus.c
  • HAL_TIMEOUT_TC : stm32wbxx_hal_smbus.c
  • HAL_TIMEOUT_TCR : stm32wbxx_hal_smbus.c
  • HAL_TIMEOUT_TXIS : stm32wbxx_hal_smbus.c
  • HAL_TSC_ERROR_INVALID_CALLBACK : stm32wbxx_hal_tsc.h
  • HAL_TSC_ERROR_NONE : stm32wbxx_hal_tsc.h
  • HAL_TSC_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_UART_ERROR_DMA : stm32wbxx_hal_uart.h
  • HAL_UART_ERROR_FE : stm32wbxx_hal_uart.h
  • HAL_UART_ERROR_INVALID_CALLBACK : stm32wbxx_hal_uart.h
  • HAL_UART_ERROR_NE : stm32wbxx_hal_uart.h
  • HAL_UART_ERROR_NONE : stm32wbxx_hal_uart.h
  • HAL_UART_ERROR_ORE : stm32wbxx_hal_uart.h
  • HAL_UART_ERROR_PE : stm32wbxx_hal_uart.h
  • HAL_UART_ERROR_RTO : stm32wbxx_hal_uart.h
  • HAL_UART_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_UART_STATE_BUSY : stm32wbxx_hal_uart.h
  • HAL_UART_STATE_BUSY_RX : stm32wbxx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX : stm32wbxx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX_RX : stm32wbxx_hal_uart.h
  • HAL_UART_STATE_ERROR : stm32wbxx_hal_uart.h
  • HAL_UART_STATE_READY : stm32wbxx_hal_uart.h
  • HAL_UART_STATE_RESET : stm32wbxx_hal_uart.h
  • HAL_UART_STATE_TIMEOUT : stm32wbxx_hal_uart.h
  • HAL_UART_TIMEOUT_VALUE : stm32wbxx_hal_uart.h
  • HAL_USART_ERROR_DMA : stm32wbxx_hal_usart.h
  • HAL_USART_ERROR_FE : stm32wbxx_hal_usart.h
  • HAL_USART_ERROR_INVALID_CALLBACK : stm32wbxx_hal_usart.h
  • HAL_USART_ERROR_NE : stm32wbxx_hal_usart.h
  • HAL_USART_ERROR_NONE : stm32wbxx_hal_usart.h
  • HAL_USART_ERROR_ORE : stm32wbxx_hal_usart.h
  • HAL_USART_ERROR_PE : stm32wbxx_hal_usart.h
  • HAL_USART_ERROR_UDR : stm32wbxx_hal_usart.h
  • HAL_USART_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HAL_WWDG_MODULE_ENABLED : stm32wbxx_hal_conf.h
  • HSE_CONTROL_UNLOCK_KEY : stm32wbxx_ll_rcc.h
  • HSE_STARTUP_TIMEOUT : stm32wbxx_hal_conf.h
  • HSE_TIMEOUT_VALUE : stm32wbxx_hal_rcc.c
  • HSE_VALUE : stm32wbxx_hal_conf.h
  • HSI48_TIMEOUT_VALUE : stm32wbxx_hal_rcc.c
  • HSI48_VALUE : stm32wbxx_hal_conf.h
  • HSI_TIMEOUT_VALUE : stm32wbxx_hal_rcc.c
  • HSI_VALUE : stm32wbxx_hal_conf.h
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

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- i -

  • I2C_ADDRESSINGMODE_10BIT : stm32wbxx_hal_i2c.h
  • I2C_ADDRESSINGMODE_7BIT : stm32wbxx_hal_i2c.h
  • I2C_ANALOGFILTER_DISABLE : stm32wbxx_hal_i2c_ex.h
  • I2C_ANALOGFILTER_ENABLE : stm32wbxx_hal_i2c_ex.h
  • I2C_AUTOEND_MODE : stm32wbxx_hal_i2c.h
  • I2C_CHECK_FLAG : stm32wbxx_hal_i2c.h
  • I2C_CHECK_IT_SOURCE : stm32wbxx_hal_i2c.h
  • I2C_DIRECTION_RECEIVE : stm32wbxx_hal_i2c.h
  • I2C_DIRECTION_TRANSMIT : stm32wbxx_hal_i2c.h
  • I2C_DUALADDRESS_DISABLE : stm32wbxx_hal_i2c.h
  • I2C_DUALADDRESS_ENABLE : stm32wbxx_hal_i2c.h
  • I2C_FASTMODEPLUS_I2C1 : stm32wbxx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_I2C3 : stm32wbxx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB6 : stm32wbxx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB7 : stm32wbxx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB8 : stm32wbxx_hal_i2c_ex.h
  • I2C_FASTMODEPLUS_PB9 : stm32wbxx_hal_i2c_ex.h
  • I2C_FIRST_AND_LAST_FRAME : stm32wbxx_hal_i2c.h
  • I2C_FIRST_AND_NEXT_FRAME : stm32wbxx_hal_i2c.h
  • I2C_FIRST_FRAME : stm32wbxx_hal_i2c.h
  • I2C_FLAG_ADDR : stm32wbxx_hal_i2c.h
  • I2C_FLAG_AF : stm32wbxx_hal_i2c.h
  • I2C_FLAG_ALERT : stm32wbxx_hal_i2c.h
  • I2C_FLAG_ARLO : stm32wbxx_hal_i2c.h
  • I2C_FLAG_BERR : stm32wbxx_hal_i2c.h
  • I2C_FLAG_BUSY : stm32wbxx_hal_i2c.h
  • I2C_FLAG_DIR : stm32wbxx_hal_i2c.h
  • I2C_FLAG_MASK : stm32wbxx_hal_i2c.h
  • I2C_FLAG_OVR : stm32wbxx_hal_i2c.h
  • I2C_FLAG_PECERR : stm32wbxx_hal_i2c.h
  • I2C_FLAG_RXNE : stm32wbxx_hal_i2c.h
  • I2C_FLAG_STOPF : stm32wbxx_hal_i2c.h
  • I2C_FLAG_TC : stm32wbxx_hal_i2c.h
  • I2C_FLAG_TCR : stm32wbxx_hal_i2c.h
  • I2C_FLAG_TIMEOUT : stm32wbxx_hal_i2c.h
  • I2C_FLAG_TXE : stm32wbxx_hal_i2c.h
  • I2C_FLAG_TXIS : stm32wbxx_hal_i2c.h
  • I2C_FMP_NOT_SUPPORTED : stm32wbxx_hal_i2c_ex.h
  • I2C_GENERALCALL_DISABLE : stm32wbxx_hal_i2c.h
  • I2C_GENERALCALL_ENABLE : stm32wbxx_hal_i2c.h
  • I2C_GENERATE_START : stm32wbxx_hal_i2c.h
  • I2C_GENERATE_START_READ : stm32wbxx_hal_i2c.h
  • I2C_GENERATE_START_WRITE : stm32wbxx_hal_i2c.h
  • I2C_GENERATE_STOP : stm32wbxx_hal_i2c.h
  • I2C_GET_ADDR_MATCH : stm32wbxx_hal_i2c.h
  • I2C_GET_DIR : stm32wbxx_hal_i2c.h
  • I2C_GET_OWN_ADDRESS1 : stm32wbxx_hal_i2c.h
  • I2C_GET_OWN_ADDRESS2 : stm32wbxx_hal_i2c.h
  • I2C_GET_STOP_MODE : stm32wbxx_hal_i2c.h
  • I2C_IT_ADDRI : stm32wbxx_hal_i2c.h
  • I2C_IT_ERRI : stm32wbxx_hal_i2c.h
  • I2C_IT_NACKI : stm32wbxx_hal_i2c.h
  • I2C_IT_RXI : stm32wbxx_hal_i2c.h
  • I2C_IT_STOPI : stm32wbxx_hal_i2c.h
  • I2C_IT_TCI : stm32wbxx_hal_i2c.h
  • I2C_IT_TXI : stm32wbxx_hal_i2c.h
  • I2C_LAST_FRAME : stm32wbxx_hal_i2c.h
  • I2C_LAST_FRAME_NO_STOP : stm32wbxx_hal_i2c.h
  • I2C_MEM_ADD_LSB : stm32wbxx_hal_i2c.h
  • I2C_MEM_ADD_MSB : stm32wbxx_hal_i2c.h
  • I2C_MEMADD_SIZE_16BIT : stm32wbxx_hal_i2c.h
  • I2C_MEMADD_SIZE_8BIT : stm32wbxx_hal_i2c.h
  • I2C_NEXT_FRAME : stm32wbxx_hal_i2c.h
  • I2C_NO_OPTION_FRAME : stm32wbxx_hal_i2c.c
  • I2C_NO_STARTSTOP : stm32wbxx_hal_i2c.h
  • I2C_NOSTRETCH_DISABLE : stm32wbxx_hal_i2c.h
  • I2C_NOSTRETCH_ENABLE : stm32wbxx_hal_i2c.h
  • I2C_OA2_MASK01 : stm32wbxx_hal_i2c.h
  • I2C_OA2_MASK02 : stm32wbxx_hal_i2c.h
  • I2C_OA2_MASK03 : stm32wbxx_hal_i2c.h
  • I2C_OA2_MASK04 : stm32wbxx_hal_i2c.h
  • I2C_OA2_MASK05 : stm32wbxx_hal_i2c.h
  • I2C_OA2_MASK06 : stm32wbxx_hal_i2c.h
  • I2C_OA2_MASK07 : stm32wbxx_hal_i2c.h
  • I2C_OA2_NOMASK : stm32wbxx_hal_i2c.h
  • I2C_OTHER_AND_LAST_FRAME : stm32wbxx_hal_i2c.h
  • I2C_OTHER_FRAME : stm32wbxx_hal_i2c.h
  • I2C_RELOAD_MODE : stm32wbxx_hal_i2c.h
  • I2C_RESET_CR2 : stm32wbxx_hal_i2c.h
  • I2C_SOFTEND_MODE : stm32wbxx_hal_i2c.h
  • I2C_STATE_MASTER_BUSY_RX : stm32wbxx_hal_i2c.c
  • I2C_STATE_MASTER_BUSY_TX : stm32wbxx_hal_i2c.c
  • I2C_STATE_MEM_BUSY_RX : stm32wbxx_hal_i2c.c
  • I2C_STATE_MEM_BUSY_TX : stm32wbxx_hal_i2c.c
  • I2C_STATE_MSK : stm32wbxx_hal_i2c.c
  • I2C_STATE_NONE : stm32wbxx_hal_i2c.c
  • I2C_STATE_SLAVE_BUSY_RX : stm32wbxx_hal_i2c.c
  • I2C_STATE_SLAVE_BUSY_TX : stm32wbxx_hal_i2c.c
  • I2C_TIMEOUT_ADDR : stm32wbxx_hal_i2c.c
  • I2C_TIMEOUT_BUSY : stm32wbxx_hal_i2c.c
  • I2C_TIMEOUT_DIR : stm32wbxx_hal_i2c.c
  • I2C_TIMEOUT_FLAG : stm32wbxx_hal_i2c.c
  • I2C_TIMEOUT_RXNE : stm32wbxx_hal_i2c.c
  • I2C_TIMEOUT_STOPF : stm32wbxx_hal_i2c.c
  • I2C_TIMEOUT_TC : stm32wbxx_hal_i2c.c
  • I2C_TIMEOUT_TCR : stm32wbxx_hal_i2c.c
  • I2C_TIMEOUT_TXIS : stm32wbxx_hal_i2c.c
  • I2C_XFER_CPLT_IT : stm32wbxx_hal_i2c.c
  • I2C_XFER_ERROR_IT : stm32wbxx_hal_i2c.c
  • I2C_XFER_LISTEN_IT : stm32wbxx_hal_i2c.c
  • I2C_XFER_RELOAD_IT : stm32wbxx_hal_i2c.c
  • I2C_XFER_RX_IT : stm32wbxx_hal_i2c.c
  • I2C_XFER_TX_IT : stm32wbxx_hal_i2c.c
  • INSTRUCTION_CACHE_ENABLE : stm32wbxx_hal_conf.h
  • IPCC_ALL_RX_BUF : stm32wbxx_hal_ipcc.c
  • IPCC_ALL_TX_BUF : stm32wbxx_hal_ipcc.c
  • IPCC_CHANNEL_1 : stm32wbxx_hal_ipcc.h
  • IPCC_CHANNEL_2 : stm32wbxx_hal_ipcc.h
  • IPCC_CHANNEL_3 : stm32wbxx_hal_ipcc.h
  • IPCC_CHANNEL_4 : stm32wbxx_hal_ipcc.h
  • IPCC_CHANNEL_5 : stm32wbxx_hal_ipcc.h
  • IPCC_CHANNEL_6 : stm32wbxx_hal_ipcc.h
  • IRDA_AUTOBAUD_REQUEST : stm32wbxx_hal_irda.h
  • IRDA_CLEAR_FEF : stm32wbxx_hal_irda.h
  • IRDA_CLEAR_IDLEF : stm32wbxx_hal_irda.h
  • IRDA_CLEAR_NEF : stm32wbxx_hal_irda.h
  • IRDA_CLEAR_OREF : stm32wbxx_hal_irda.h
  • IRDA_CLEAR_PEF : stm32wbxx_hal_irda.h
  • IRDA_CLEAR_TCF : stm32wbxx_hal_irda.h
  • IRDA_CR1_FIELDS : stm32wbxx_hal_irda.c
  • IRDA_CR_MASK : stm32wbxx_hal_irda.h
  • IRDA_CR_POS : stm32wbxx_hal_irda.h
  • IRDA_DIV_SAMPLING16 : stm32wbxx_hal_irda.c
  • IRDA_DMA_RX_DISABLE : stm32wbxx_hal_irda.h
  • IRDA_DMA_RX_ENABLE : stm32wbxx_hal_irda.h
  • IRDA_DMA_TX_DISABLE : stm32wbxx_hal_irda.h
  • IRDA_DMA_TX_ENABLE : stm32wbxx_hal_irda.h
  • IRDA_FLAG_ABRE : stm32wbxx_hal_irda.h
  • IRDA_FLAG_ABRF : stm32wbxx_hal_irda.h
  • IRDA_FLAG_BUSY : stm32wbxx_hal_irda.h
  • IRDA_FLAG_FE : stm32wbxx_hal_irda.h
  • IRDA_FLAG_NE : stm32wbxx_hal_irda.h
  • IRDA_FLAG_ORE : stm32wbxx_hal_irda.h
  • IRDA_FLAG_PE : stm32wbxx_hal_irda.h
  • IRDA_FLAG_REACK : stm32wbxx_hal_irda.h
  • IRDA_FLAG_RXNE : stm32wbxx_hal_irda.h
  • IRDA_FLAG_TC : stm32wbxx_hal_irda.h
  • IRDA_FLAG_TEACK : stm32wbxx_hal_irda.h
  • IRDA_FLAG_TXE : stm32wbxx_hal_irda.h
  • IRDA_GETCLOCKSOURCE : stm32wbxx_hal_irda_ex.h
  • IRDA_ISR_MASK : stm32wbxx_hal_irda.h
  • IRDA_ISR_POS : stm32wbxx_hal_irda.h
  • IRDA_IT_ERR : stm32wbxx_hal_irda.h
  • IRDA_IT_FE : stm32wbxx_hal_irda.h
  • IRDA_IT_IDLE : stm32wbxx_hal_irda.h
  • IRDA_IT_MASK : stm32wbxx_hal_irda.h
  • IRDA_IT_NE : stm32wbxx_hal_irda.h
  • IRDA_IT_ORE : stm32wbxx_hal_irda.h
  • IRDA_IT_PE : stm32wbxx_hal_irda.h
  • IRDA_IT_RXNE : stm32wbxx_hal_irda.h
  • IRDA_IT_TC : stm32wbxx_hal_irda.h
  • IRDA_IT_TXE : stm32wbxx_hal_irda.h
  • IRDA_MASK_COMPUTATION : stm32wbxx_hal_irda.h
  • IRDA_MODE_DISABLE : stm32wbxx_hal_irda.h
  • IRDA_MODE_ENABLE : stm32wbxx_hal_irda.h
  • IRDA_MODE_RX : stm32wbxx_hal_irda.h
  • IRDA_MODE_TX : stm32wbxx_hal_irda.h
  • IRDA_MODE_TX_RX : stm32wbxx_hal_irda.h
  • IRDA_ONE_BIT_SAMPLE_DISABLE : stm32wbxx_hal_irda.h
  • IRDA_ONE_BIT_SAMPLE_ENABLE : stm32wbxx_hal_irda.h
  • IRDA_PARITY_EVEN : stm32wbxx_hal_irda.h
  • IRDA_PARITY_NONE : stm32wbxx_hal_irda.h
  • IRDA_PARITY_ODD : stm32wbxx_hal_irda.h
  • IRDA_POWERMODE_LOWPOWER : stm32wbxx_hal_irda.h
  • IRDA_POWERMODE_NORMAL : stm32wbxx_hal_irda.h
  • IRDA_PRESCALER_DIV1 : stm32wbxx_hal_irda.h
  • IRDA_PRESCALER_DIV10 : stm32wbxx_hal_irda.h
  • IRDA_PRESCALER_DIV12 : stm32wbxx_hal_irda.h
  • IRDA_PRESCALER_DIV128 : stm32wbxx_hal_irda.h
  • IRDA_PRESCALER_DIV16 : stm32wbxx_hal_irda.h
  • IRDA_PRESCALER_DIV2 : stm32wbxx_hal_irda.h
  • IRDA_PRESCALER_DIV256 : stm32wbxx_hal_irda.h
  • IRDA_PRESCALER_DIV32 : stm32wbxx_hal_irda.h
  • IRDA_PRESCALER_DIV4 : stm32wbxx_hal_irda.h
  • IRDA_PRESCALER_DIV6 : stm32wbxx_hal_irda.h
  • IRDA_PRESCALER_DIV64 : stm32wbxx_hal_irda.h
  • IRDA_PRESCALER_DIV8 : stm32wbxx_hal_irda.h
  • IRDA_RXDATA_FLUSH_REQUEST : stm32wbxx_hal_irda.h
  • IRDA_STATE_DISABLE : stm32wbxx_hal_irda.h
  • IRDA_STATE_ENABLE : stm32wbxx_hal_irda.h
  • IRDA_TEACK_REACK_TIMEOUT : stm32wbxx_hal_irda.c
  • IRDA_TXDATA_FLUSH_REQUEST : stm32wbxx_hal_irda.h
  • IRDA_WORDLENGTH_7B : stm32wbxx_hal_irda.h
  • IRDA_WORDLENGTH_8B : stm32wbxx_hal_irda.h
  • IRDA_WORDLENGTH_9B : stm32wbxx_hal_irda.h
  • IS_ADC_ANALOG_WATCHDOG_MODE : stm32wbxx_hal_adc_ex.h
  • IS_ADC_ANALOG_WATCHDOG_NUMBER : stm32wbxx_hal_adc_ex.h
  • IS_ADC_CALFACT : stm32wbxx_hal_adc_ex.h
  • IS_ADC_CHANNEL : stm32wbxx_hal_adc_ex.h
  • IS_ADC_CLOCKPRESCALER : stm32wbxx_hal_adc.h
  • IS_ADC_CONVERSION_GROUP : stm32wbxx_hal_adc_ex.h
  • IS_ADC_DATA_ALIGN : stm32wbxx_hal_adc.h
  • IS_ADC_DFSDMCFG_MODE : stm32wbxx_hal_adc_ex.h
  • IS_ADC_DIFF_CHANNEL : stm32wbxx_hal_adc_ex.h
  • IS_ADC_EOC_SELECTION : stm32wbxx_hal_adc.h
  • IS_ADC_EVENT_TYPE : stm32wbxx_hal_adc_ex.h
  • IS_ADC_EXTTRIG : stm32wbxx_hal_adc.h
  • IS_ADC_EXTTRIG_EDGE : stm32wbxx_hal_adc.h
  • IS_ADC_EXTTRIGINJEC : stm32wbxx_hal_adc_ex.h
  • IS_ADC_EXTTRIGINJEC_EDGE : stm32wbxx_hal_adc_ex.h
  • IS_ADC_INJECTED_NB_CONV : stm32wbxx_hal_adc_ex.h
  • IS_ADC_INJECTED_RANK : stm32wbxx_hal_adc_ex.h
  • IS_ADC_OFFSET_NUMBER : stm32wbxx_hal_adc_ex.h
  • IS_ADC_OVERRUN : stm32wbxx_hal_adc.h
  • IS_ADC_OVERSAMPLING_RATIO : stm32wbxx_hal_adc_ex.h
  • IS_ADC_RANGE : stm32wbxx_hal_adc.h
  • IS_ADC_REGOVERSAMPLING_MODE : stm32wbxx_hal_adc_ex.h
  • IS_ADC_REGULAR_DISCONT_NUMBER : stm32wbxx_hal_adc.h
  • IS_ADC_REGULAR_NB_CONV : stm32wbxx_hal_adc.h
  • IS_ADC_REGULAR_RANK : stm32wbxx_hal_adc.h
  • IS_ADC_RESOLUTION : stm32wbxx_hal_adc.h
  • IS_ADC_RESOLUTION_8_6_BITS : stm32wbxx_hal_adc.h
  • IS_ADC_RIGHT_BIT_SHIFT : stm32wbxx_hal_adc_ex.h
  • IS_ADC_SAMPLE_TIME : stm32wbxx_hal_adc.h
  • IS_ADC_SCAN_MODE : stm32wbxx_hal_adc.h
  • IS_ADC_SINGLE_DIFFERENTIAL : stm32wbxx_hal_adc_ex.h
  • IS_ADC_TRIGGERED_OVERSAMPLING_MODE : stm32wbxx_hal_adc_ex.h
  • IS_ADDR_ALIGNED_64BITS : stm32wbxx_hal_flash.h
  • IS_COMP_BLANKINGSRC_INSTANCE : stm32wbxx_hal_comp.h
  • IS_COMP_BLANKINGSRCE : stm32wbxx_hal_comp.h
  • IS_COMP_HYSTERESIS : stm32wbxx_hal_comp.h
  • IS_COMP_INPUT_MINUS : stm32wbxx_hal_comp.h
  • IS_COMP_INPUT_PLUS : stm32wbxx_hal_comp.h
  • IS_COMP_OUTPUT_LEVEL : stm32wbxx_hal_comp.h
  • IS_COMP_OUTPUTPOL : stm32wbxx_hal_comp.h
  • IS_COMP_POWERMODE : stm32wbxx_hal_comp.h
  • IS_COMP_TRIGGERMODE : stm32wbxx_hal_comp.h
  • IS_COMP_WINDOWMODE : stm32wbxx_hal_comp.h
  • IS_CRC_INPUTDATA_FORMAT : stm32wbxx_hal_crc.h
  • IS_CRC_INPUTDATA_INVERSION_MODE : stm32wbxx_hal_crc_ex.h
  • IS_CRC_OUTPUTDATA_INVERSION_MODE : stm32wbxx_hal_crc_ex.h
  • IS_CRC_POL_LENGTH : stm32wbxx_hal_crc.h
  • IS_CRYP_ALGORITHM : stm32wbxx_hal_cryp.h
  • IS_CRYP_BUFFERSIZE : stm32wbxx_hal_cryp.h
  • IS_CRYP_DATATYPE : stm32wbxx_hal_cryp.h
  • IS_CRYP_INIT : stm32wbxx_hal_cryp.h
  • IS_CRYP_KEYSIZE : stm32wbxx_hal_cryp.h
  • IS_DEFAULT_INIT_VALUE : stm32wbxx_hal_crc.h
  • IS_DEFAULT_POLYNOMIAL : stm32wbxx_hal_crc.h
  • IS_DMA_ALL_REQUEST : stm32wbxx_hal_dma.h
  • IS_DMA_BUFFER_SIZE : stm32wbxx_hal_dma.h
  • IS_DMA_DIRECTION : stm32wbxx_hal_dma.h
  • IS_DMA_MEMORY_DATA_SIZE : stm32wbxx_hal_dma.h
  • IS_DMA_MEMORY_INC_STATE : stm32wbxx_hal_dma.h
  • IS_DMA_MODE : stm32wbxx_hal_dma.h
  • IS_DMA_PERIPHERAL_DATA_SIZE : stm32wbxx_hal_dma.h
  • IS_DMA_PERIPHERAL_INC_STATE : stm32wbxx_hal_dma.h
  • IS_DMA_PRIORITY : stm32wbxx_hal_dma.h
  • IS_DMAMUX_REQUEST_GEN_POLARITY : stm32wbxx_hal_dma_ex.h
  • IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER : stm32wbxx_hal_dma_ex.h
  • IS_DMAMUX_REQUEST_GEN_SIGNAL_ID : stm32wbxx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_EVENT : stm32wbxx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_POLARITY : stm32wbxx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_REQUEST_NUMBER : stm32wbxx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_SIGNAL_ID : stm32wbxx_hal_dma_ex.h
  • IS_DMAMUX_SYNC_STATE : stm32wbxx_hal_dma_ex.h
  • IS_EXTI_CONFIG_LINE : stm32wbxx_hal_exti.h
  • IS_EXTI_GPIO_PIN : stm32wbxx_hal_exti.h
  • IS_EXTI_GPIO_PORT : stm32wbxx_hal_exti.h
  • IS_EXTI_LINE : stm32wbxx_hal_exti.h
  • IS_EXTI_MODE : stm32wbxx_hal_exti.h
  • IS_EXTI_PENDING_EDGE : stm32wbxx_hal_exti.h
  • IS_EXTI_TRIGGER : stm32wbxx_hal_exti.h
  • IS_FLASH_EMPTY_CHECK : stm32wbxx_hal_flash_ex.h
  • IS_FLASH_FAST_PROGRAM_ADDRESS : stm32wbxx_hal_flash.h
  • IS_FLASH_LATENCY : stm32wbxx_hal_flash.h
  • IS_FLASH_MAIN_MEM_ADDRESS : stm32wbxx_hal_flash.h
  • IS_FLASH_PAGE : stm32wbxx_hal_flash.h
  • IS_FLASH_PROGRAM_ADDRESS : stm32wbxx_hal_flash.h
  • IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS : stm32wbxx_hal_flash.h
  • IS_FLASH_PROGRAM_OTP_ADDRESS : stm32wbxx_hal_flash.h
  • IS_FLASH_TYPEERASE : stm32wbxx_hal_flash.h
  • IS_FLASH_TYPEPROGRAM : stm32wbxx_hal_flash.h
  • IS_GPIO_AF : stm32wbxx_hal_gpio_ex.h
  • IS_GPIO_MODE : stm32wbxx_hal_gpio.h
  • IS_GPIO_PIN : stm32wbxx_hal_gpio.h
  • IS_GPIO_PIN_ACTION : stm32wbxx_hal_gpio.h
  • IS_GPIO_PULL : stm32wbxx_hal_gpio.h
  • IS_GPIO_SPEED : stm32wbxx_hal_gpio.h
  • IS_HSEM_COREID : stm32wbxx_hal_hsem.h
  • IS_HSEM_KEY : stm32wbxx_hal_hsem.h
  • IS_HSEM_PROCESSID : stm32wbxx_hal_hsem.h
  • IS_HSEM_SEMID : stm32wbxx_hal_hsem.h
  • IS_I2C_ADDRESSING_MODE : stm32wbxx_hal_i2c.h
  • IS_I2C_ANALOG_FILTER : stm32wbxx_hal_i2c_ex.h
  • IS_I2C_DIGITAL_FILTER : stm32wbxx_hal_i2c_ex.h
  • IS_I2C_DUAL_ADDRESS : stm32wbxx_hal_i2c.h
  • IS_I2C_FASTMODEPLUS : stm32wbxx_hal_i2c_ex.h
  • IS_I2C_GENERAL_CALL : stm32wbxx_hal_i2c.h
  • IS_I2C_MEMADD_SIZE : stm32wbxx_hal_i2c.h
  • IS_I2C_NO_STRETCH : stm32wbxx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS1 : stm32wbxx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS2 : stm32wbxx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS2_MASK : stm32wbxx_hal_i2c.h
  • IS_I2C_TRANSFER_OPTIONS_REQUEST : stm32wbxx_hal_i2c.h
  • IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST : stm32wbxx_hal_i2c.h
  • IS_IRDA_BAUDRATE : stm32wbxx_hal_irda.h
  • IS_IRDA_CLOCKPRESCALER : stm32wbxx_hal_irda.h
  • IS_IRDA_DMA_RX : stm32wbxx_hal_irda.h
  • IS_IRDA_DMA_TX : stm32wbxx_hal_irda.h
  • IS_IRDA_MODE : stm32wbxx_hal_irda.h
  • IS_IRDA_ONE_BIT_SAMPLE : stm32wbxx_hal_irda.h
  • IS_IRDA_PARITY : stm32wbxx_hal_irda.h
  • IS_IRDA_POWERMODE : stm32wbxx_hal_irda.h
  • IS_IRDA_PRESCALER : stm32wbxx_hal_irda.h
  • IS_IRDA_REQUEST_PARAMETER : stm32wbxx_hal_irda.h
  • IS_IRDA_STATE : stm32wbxx_hal_irda.h
  • IS_IRDA_TX_RX_MODE : stm32wbxx_hal_irda.h
  • IS_IRDA_WORD_LENGTH : stm32wbxx_hal_irda.h
  • IS_IWDG_PRESCALER : stm32wbxx_hal_iwdg.h
  • IS_IWDG_RELOAD : stm32wbxx_hal_iwdg.h
  • IS_IWDG_WINDOW : stm32wbxx_hal_iwdg.h
  • IS_LCD_BIAS : stm32wbxx_hal_lcd.h
  • IS_LCD_BLINK_FREQUENCY : stm32wbxx_hal_lcd.h
  • IS_LCD_BLINK_MODE : stm32wbxx_hal_lcd.h
  • IS_LCD_CONTRAST : stm32wbxx_hal_lcd.h
  • IS_LCD_DEAD_TIME : stm32wbxx_hal_lcd.h
  • IS_LCD_DIVIDER : stm32wbxx_hal_lcd.h
  • IS_LCD_DUTY : stm32wbxx_hal_lcd.h
  • IS_LCD_HIGH_DRIVE : stm32wbxx_hal_lcd.h
  • IS_LCD_MUX_SEGMENT : stm32wbxx_hal_lcd.h
  • IS_LCD_PRESCALER : stm32wbxx_hal_lcd.h
  • IS_LCD_PULSE_ON_DURATION : stm32wbxx_hal_lcd.h
  • IS_LCD_RAM_REGISTER : stm32wbxx_hal_lcd.h
  • IS_LCD_VOLTAGE_SOURCE : stm32wbxx_hal_lcd.h
  • IS_LL_ADC_COMMON_CLOCK : stm32wbxx_ll_adc.c
  • IS_LL_ADC_DATA_ALIGN : stm32wbxx_ll_adc.c
  • IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE : stm32wbxx_ll_adc.c
  • IS_LL_ADC_INJ_SEQ_SCAN_LENGTH : stm32wbxx_ll_adc.c
  • IS_LL_ADC_INJ_TRIG_AUTO : stm32wbxx_ll_adc.c
  • IS_LL_ADC_INJ_TRIG_EXT_EDGE : stm32wbxx_ll_adc.c
  • IS_LL_ADC_INJ_TRIG_SOURCE : stm32wbxx_ll_adc.c
  • IS_LL_ADC_LOW_POWER : stm32wbxx_ll_adc.c
  • IS_LL_ADC_REG_CONTINUOUS_MODE : stm32wbxx_ll_adc.c
  • IS_LL_ADC_REG_DMA_TRANSFER : stm32wbxx_ll_adc.c
  • IS_LL_ADC_REG_OVR_DATA_BEHAVIOR : stm32wbxx_ll_adc.c
  • IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE : stm32wbxx_ll_adc.c
  • IS_LL_ADC_REG_SEQ_SCAN_LENGTH : stm32wbxx_ll_adc.c
  • IS_LL_ADC_REG_TRIG_SOURCE : stm32wbxx_ll_adc.c
  • IS_LL_ADC_RESOLUTION : stm32wbxx_ll_adc.c
  • IS_LL_COMP_INPUT_HYSTERESIS : stm32wbxx_ll_comp.c
  • IS_LL_COMP_INPUT_MINUS : stm32wbxx_ll_comp.c
  • IS_LL_COMP_INPUT_PLUS : stm32wbxx_ll_comp.c
  • IS_LL_COMP_OUTPUT_BLANKING_SOURCE : stm32wbxx_ll_comp.c
  • IS_LL_COMP_OUTPUT_POLARITY : stm32wbxx_ll_comp.c
  • IS_LL_COMP_POWER_MODE : stm32wbxx_ll_comp.c
  • IS_LL_DMA_ALL_CHANNEL_INSTANCE : stm32wbxx_ll_dma.c
  • IS_LL_DMA_DIRECTION : stm32wbxx_ll_dma.c
  • IS_LL_DMA_MEMORYDATASIZE : stm32wbxx_ll_dma.c
  • IS_LL_DMA_MEMORYINCMODE : stm32wbxx_ll_dma.c
  • IS_LL_DMA_MODE : stm32wbxx_ll_dma.c
  • IS_LL_DMA_NBDATA : stm32wbxx_ll_dma.c
  • IS_LL_DMA_PERIPHDATASIZE : stm32wbxx_ll_dma.c
  • IS_LL_DMA_PERIPHINCMODE : stm32wbxx_ll_dma.c
  • IS_LL_DMA_PERIPHREQUEST : stm32wbxx_ll_dma.c
  • IS_LL_DMA_PRIORITY : stm32wbxx_ll_dma.c
  • IS_LL_EXTI_LINE_0_31 : stm32wbxx_ll_exti.c
  • IS_LL_EXTI_LINE_32_63 : stm32wbxx_ll_exti.c
  • IS_LL_EXTI_MODE : stm32wbxx_ll_exti.c
  • IS_LL_EXTI_TRIGGER : stm32wbxx_ll_exti.c
  • IS_LL_GPIO_ALTERNATE : stm32wbxx_ll_gpio.c
  • IS_LL_GPIO_MODE : stm32wbxx_ll_gpio.c
  • IS_LL_GPIO_OUTPUT_TYPE : stm32wbxx_ll_gpio.c
  • IS_LL_GPIO_PIN : stm32wbxx_ll_gpio.c
  • IS_LL_GPIO_PULL : stm32wbxx_ll_gpio.c
  • IS_LL_GPIO_SPEED : stm32wbxx_ll_gpio.c
  • IS_LL_I2C_ANALOG_FILTER : stm32wbxx_ll_i2c.c
  • IS_LL_I2C_DIGITAL_FILTER : stm32wbxx_ll_i2c.c
  • IS_LL_I2C_OWN_ADDRESS1 : stm32wbxx_ll_i2c.c
  • IS_LL_I2C_OWN_ADDRSIZE : stm32wbxx_ll_i2c.c
  • IS_LL_I2C_PERIPHERAL_MODE : stm32wbxx_ll_i2c.c
  • IS_LL_I2C_TYPE_ACKNOWLEDGE : stm32wbxx_ll_i2c.c
  • IS_LL_LPTIM_CLOCK_PRESCALER : stm32wbxx_ll_lptim.c
  • IS_LL_LPTIM_CLOCK_SOURCE : stm32wbxx_ll_lptim.c
  • IS_LL_LPTIM_OUTPUT_POLARITY : stm32wbxx_ll_lptim.c
  • IS_LL_LPTIM_WAVEFORM : stm32wbxx_ll_lptim.c
  • IS_LL_LPUART_BAUDRATE : stm32wbxx_ll_lpuart.c
  • IS_LL_LPUART_BRR_MAX : stm32wbxx_ll_lpuart.c
  • IS_LL_LPUART_BRR_MIN : stm32wbxx_ll_lpuart.c
  • IS_LL_LPUART_DATAWIDTH : stm32wbxx_ll_lpuart.c
  • IS_LL_LPUART_DIRECTION : stm32wbxx_ll_lpuart.c
  • IS_LL_LPUART_HWCONTROL : stm32wbxx_ll_lpuart.c
  • IS_LL_LPUART_PARITY : stm32wbxx_ll_lpuart.c
  • IS_LL_LPUART_PRESCALER : stm32wbxx_ll_lpuart.c
  • IS_LL_LPUART_STOPBITS : stm32wbxx_ll_lpuart.c
  • IS_LL_PKA_MODE : stm32wbxx_ll_pka.c
  • IS_LL_RCC_ADC_CLKSOURCE : stm32wbxx_ll_rcc.c
  • IS_LL_RCC_CLK48_CLKSOURCE : stm32wbxx_ll_rcc.c
  • IS_LL_RCC_I2C_CLKSOURCE : stm32wbxx_ll_rcc.c
  • IS_LL_RCC_LPTIM_CLKSOURCE : stm32wbxx_ll_rcc.c
  • IS_LL_RCC_LPUART_CLKSOURCE : stm32wbxx_ll_rcc.c
  • IS_LL_RCC_RNG_CLKSOURCE : stm32wbxx_ll_rcc.c
  • IS_LL_RCC_SAI_CLKSOURCE : stm32wbxx_ll_rcc.c
  • IS_LL_RCC_USART_CLKSOURCE : stm32wbxx_ll_rcc.c
  • IS_LL_RCC_USB_CLKSOURCE : stm32wbxx_ll_rcc.c
  • IS_LL_RNG_CED : stm32wbxx_ll_rng.c
  • IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL : stm32wbxx_ll_rtc.c
  • IS_LL_RTC_ALMA_MASK : stm32wbxx_ll_rtc.c
  • IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL : stm32wbxx_ll_rtc.c
  • IS_LL_RTC_ALMB_MASK : stm32wbxx_ll_rtc.c
  • IS_LL_RTC_ASYNCH_PREDIV : stm32wbxx_ll_rtc.c
  • IS_LL_RTC_DAY : stm32wbxx_ll_rtc.c
  • IS_LL_RTC_FORMAT : stm32wbxx_ll_rtc.c
  • IS_LL_RTC_HOUR12 : stm32wbxx_ll_rtc.c
  • IS_LL_RTC_HOUR24 : stm32wbxx_ll_rtc.c
  • IS_LL_RTC_HOURFORMAT : stm32wbxx_ll_rtc.c
  • IS_LL_RTC_MINUTES : stm32wbxx_ll_rtc.c
  • IS_LL_RTC_MONTH : stm32wbxx_ll_rtc.c
  • IS_LL_RTC_SECONDS : stm32wbxx_ll_rtc.c
  • IS_LL_RTC_SYNCH_PREDIV : stm32wbxx_ll_rtc.c
  • IS_LL_RTC_TIME_FORMAT : stm32wbxx_ll_rtc.c
  • IS_LL_RTC_WEEKDAY : stm32wbxx_ll_rtc.c
  • IS_LL_RTC_YEAR : stm32wbxx_ll_rtc.c
  • IS_LL_SPI_BAUDRATE : stm32wbxx_ll_spi.c
  • IS_LL_SPI_BITORDER : stm32wbxx_ll_spi.c
  • IS_LL_SPI_CRC_POLYNOMIAL : stm32wbxx_ll_spi.c
  • IS_LL_SPI_CRCCALCULATION : stm32wbxx_ll_spi.c
  • IS_LL_SPI_DATAWIDTH : stm32wbxx_ll_spi.c
  • IS_LL_SPI_MODE : stm32wbxx_ll_spi.c
  • IS_LL_SPI_NSS : stm32wbxx_ll_spi.c
  • IS_LL_SPI_PHASE : stm32wbxx_ll_spi.c
  • IS_LL_SPI_POLARITY : stm32wbxx_ll_spi.c
  • IS_LL_SPI_TRANSFER_DIRECTION : stm32wbxx_ll_spi.c
  • IS_LL_TIM_ACTIVEINPUT : stm32wbxx_ll_tim.c
  • IS_LL_TIM_AUTOMATIC_OUTPUT_STATE : stm32wbxx_ll_tim.c
  • IS_LL_TIM_BREAK2_FILTER : stm32wbxx_ll_tim.c
  • IS_LL_TIM_BREAK2_POLARITY : stm32wbxx_ll_tim.c
  • IS_LL_TIM_BREAK2_STATE : stm32wbxx_ll_tim.c
  • IS_LL_TIM_BREAK_FILTER : stm32wbxx_ll_tim.c
  • IS_LL_TIM_BREAK_POLARITY : stm32wbxx_ll_tim.c
  • IS_LL_TIM_BREAK_STATE : stm32wbxx_ll_tim.c
  • IS_LL_TIM_CLOCKDIVISION : stm32wbxx_ll_tim.c
  • IS_LL_TIM_COUNTERMODE : stm32wbxx_ll_tim.c
  • IS_LL_TIM_ENCODERMODE : stm32wbxx_ll_tim.c
  • IS_LL_TIM_IC_FILTER : stm32wbxx_ll_tim.c
  • IS_LL_TIM_IC_POLARITY : stm32wbxx_ll_tim.c
  • IS_LL_TIM_IC_POLARITY_ENCODER : stm32wbxx_ll_tim.c
  • IS_LL_TIM_ICPSC : stm32wbxx_ll_tim.c
  • IS_LL_TIM_LOCK_LEVEL : stm32wbxx_ll_tim.c
  • IS_LL_TIM_OCIDLESTATE : stm32wbxx_ll_tim.c
  • IS_LL_TIM_OCMODE : stm32wbxx_ll_tim.c
  • IS_LL_TIM_OCPOLARITY : stm32wbxx_ll_tim.c
  • IS_LL_TIM_OCSTATE : stm32wbxx_ll_tim.c
  • IS_LL_TIM_OSSI_STATE : stm32wbxx_ll_tim.c
  • IS_LL_TIM_OSSR_STATE : stm32wbxx_ll_tim.c
  • IS_LL_USART_BAUDRATE : stm32wbxx_ll_usart.c
  • IS_LL_USART_BRR_MAX : stm32wbxx_ll_usart.c
  • IS_LL_USART_BRR_MIN : stm32wbxx_ll_usart.c
  • IS_LL_USART_CLOCKOUTPUT : stm32wbxx_ll_usart.c
  • IS_LL_USART_CLOCKPHASE : stm32wbxx_ll_usart.c
  • IS_LL_USART_CLOCKPOLARITY : stm32wbxx_ll_usart.c
  • IS_LL_USART_DATAWIDTH : stm32wbxx_ll_usart.c
  • IS_LL_USART_DIRECTION : stm32wbxx_ll_usart.c
  • IS_LL_USART_HWCONTROL : stm32wbxx_ll_usart.c
  • IS_LL_USART_LASTBITCLKOUTPUT : stm32wbxx_ll_usart.c
  • IS_LL_USART_OVERSAMPLING : stm32wbxx_ll_usart.c
  • IS_LL_USART_PARITY : stm32wbxx_ll_usart.c
  • IS_LL_USART_PRESCALER : stm32wbxx_ll_usart.c
  • IS_LL_USART_STOPBITS : stm32wbxx_ll_usart.c
  • IS_LL_UTILS_APB1_DIV : stm32wbxx_ll_utils.c
  • IS_LL_UTILS_APB2_DIV : stm32wbxx_ll_utils.c
  • IS_LL_UTILS_HSE_BYPASS : stm32wbxx_ll_utils.c
  • IS_LL_UTILS_PLL_FREQUENCY : stm32wbxx_ll_utils.c
  • IS_LL_UTILS_PLLM_VALUE : stm32wbxx_ll_utils.c
  • IS_LL_UTILS_PLLN_VALUE : stm32wbxx_ll_utils.c
  • IS_LL_UTILS_PLLR_VALUE : stm32wbxx_ll_utils.c
  • IS_LL_UTILS_PLLVCO_INPUT : stm32wbxx_ll_utils.c
  • IS_LL_UTILS_PLLVCO_OUTPUT : stm32wbxx_ll_utils.c
  • IS_LL_UTILS_SYSCLK_DIV : stm32wbxx_ll_utils.c
  • IS_LPTIM_AUTORELOAD : stm32wbxx_hal_lptim.h
  • IS_LPTIM_CLOCK_POLARITY : stm32wbxx_hal_lptim.h
  • IS_LPTIM_CLOCK_PRESCALER : stm32wbxx_hal_lptim.h
  • IS_LPTIM_CLOCK_PRESCALERDIV1 : stm32wbxx_hal_lptim.h
  • IS_LPTIM_CLOCK_SAMPLE_TIME : stm32wbxx_hal_lptim.h
  • IS_LPTIM_CLOCK_SOURCE : stm32wbxx_hal_lptim.h
  • IS_LPTIM_COMPARE : stm32wbxx_hal_lptim.h
  • IS_LPTIM_COUNTER_SOURCE : stm32wbxx_hal_lptim.h
  • IS_LPTIM_EXT_TRG_POLARITY : stm32wbxx_hal_lptim.h
  • IS_LPTIM_INPUT1_SOURCE : stm32wbxx_hal_lptim.h
  • IS_LPTIM_INPUT2_SOURCE : stm32wbxx_hal_lptim.h
  • IS_LPTIM_OUTPUT_POLARITY : stm32wbxx_hal_lptim.h
  • IS_LPTIM_PERIOD : stm32wbxx_hal_lptim.h
  • IS_LPTIM_PULSE : stm32wbxx_hal_lptim.h
  • IS_LPTIM_TRG_SOURCE : stm32wbxx_hal_lptim.h
  • IS_LPTIM_TRIG_SAMPLE_TIME : stm32wbxx_hal_lptim.h
  • IS_LPTIM_UPDATE_MODE : stm32wbxx_hal_lptim.h
  • IS_LPUART_STOPBITS : stm32wbxx_hal_uart.h
  • IS_MPU_ACCESS_BUFFERABLE : stm32wbxx_hal_cortex.h
  • IS_MPU_ACCESS_CACHEABLE : stm32wbxx_hal_cortex.h
  • IS_MPU_ACCESS_SHAREABLE : stm32wbxx_hal_cortex.h
  • IS_MPU_INSTRUCTION_ACCESS : stm32wbxx_hal_cortex.h
  • IS_MPU_REGION_ENABLE : stm32wbxx_hal_cortex.h
  • IS_MPU_REGION_NUMBER : stm32wbxx_hal_cortex.h
  • IS_MPU_REGION_PERMISSION_ATTRIBUTE : stm32wbxx_hal_cortex.h
  • IS_MPU_REGION_SIZE : stm32wbxx_hal_cortex.h
  • IS_MPU_SUB_REGION_DISABLE : stm32wbxx_hal_cortex.h
  • IS_MPU_TEX_LEVEL : stm32wbxx_hal_cortex.h
  • IS_NVIC_DEVICE_IRQ : stm32wbxx_hal_cortex.h
  • IS_NVIC_PREEMPTION_PRIORITY : stm32wbxx_hal_cortex.h
  • IS_NVIC_PRIORITY_GROUP : stm32wbxx_hal_cortex.h
  • IS_NVIC_SUB_PRIORITY : stm32wbxx_hal_cortex.h
  • IS_OB_BOOT_REGION : stm32wbxx_hal_flash.h
  • IS_OB_BOOT_VECTOR_ADDR : stm32wbxx_hal_flash.h
  • IS_OB_IPCC_BUF_ADDR : stm32wbxx_hal_flash.h
  • IS_OB_PCROP_CONFIG : stm32wbxx_hal_flash.h
  • IS_OB_RDP_LEVEL : stm32wbxx_hal_flash.h
  • IS_OB_SBRSA_START_ADDR : stm32wbxx_hal_flash.h
  • IS_OB_SECURE_CONFIG : stm32wbxx_hal_flash.h
  • IS_OB_SECURE_MODE : stm32wbxx_hal_flash.h
  • IS_OB_SFSA_START_ADDR : stm32wbxx_hal_flash.h
  • IS_OB_SNBRSA_START_ADDR : stm32wbxx_hal_flash.h
  • IS_OB_USER_AGC_TRIMMING : stm32wbxx_hal_flash.h
  • IS_OB_USER_BOR_LEVEL : stm32wbxx_hal_flash.h
  • IS_OB_USER_CONFIG : stm32wbxx_hal_flash.h
  • IS_OB_USER_TYPE : stm32wbxx_hal_flash.h
  • IS_OB_WRPAREA : stm32wbxx_hal_flash.h
  • IS_OPTIONBYTE : stm32wbxx_hal_flash.h
  • IS_PWR_BATTERY_CHARGING : stm32wbxx_hal_pwr_ex.h
  • IS_PWR_BATTERY_RESISTOR_SELECT : stm32wbxx_hal_pwr_ex.h
  • IS_PWR_CORE : stm32wbxx_hal_pwr_ex.h
  • IS_PWR_CORE_HOLD_RELEASE : stm32wbxx_hal_pwr_ex.h
  • IS_PWR_FLASH_POWERDOWN : stm32wbxx_hal_pwr_ex.h
  • IS_PWR_GPIO : stm32wbxx_hal_pwr_ex.h
  • IS_PWR_GPIO_BIT_NUMBER : stm32wbxx_hal_pwr_ex.h
  • IS_PWR_PVD_LEVEL : stm32wbxx_hal_pwr.h
  • IS_PWR_PVD_MODE : stm32wbxx_hal_pwr.h
  • IS_PWR_PVM_MODE : stm32wbxx_hal_pwr_ex.h
  • IS_PWR_PVM_TYPE : stm32wbxx_hal_pwr_ex.h
  • IS_PWR_REGULATOR : stm32wbxx_hal_pwr.h
  • IS_PWR_SLEEP_ENTRY : stm32wbxx_hal_pwr.h
  • IS_PWR_SMPS_MODE : stm32wbxx_hal_pwr_ex.h
  • IS_PWR_SMPS_OUTPUT_VOLTAGE : stm32wbxx_hal_pwr_ex.h
  • IS_PWR_SMPS_STARTUP_CURRENT : stm32wbxx_hal_pwr_ex.h
  • IS_PWR_STOP_ENTRY : stm32wbxx_hal_pwr.h
  • IS_PWR_VOLTAGE_SCALING_RANGE : stm32wbxx_hal_pwr_ex.h
  • IS_PWR_WAKEUP_PIN : stm32wbxx_hal_pwr_ex.h
  • IS_PWR_WAKEUP_PIN_POLARITY : stm32wbxx_hal_pwr_ex.h
  • IS_QSPI_ADDRESS_MODE : stm32wbxx_hal_qspi.h
  • IS_QSPI_ADDRESS_SIZE : stm32wbxx_hal_qspi.h
  • IS_QSPI_ALTERNATE_BYTES_MODE : stm32wbxx_hal_qspi.h
  • IS_QSPI_ALTERNATE_BYTES_SIZE : stm32wbxx_hal_qspi.h
  • IS_QSPI_AUTOMATIC_STOP : stm32wbxx_hal_qspi.h
  • IS_QSPI_CLOCK_MODE : stm32wbxx_hal_qspi.h
  • IS_QSPI_CLOCK_PRESCALER : stm32wbxx_hal_qspi.h
  • IS_QSPI_CS_HIGH_TIME : stm32wbxx_hal_qspi.h
  • IS_QSPI_DATA_MODE : stm32wbxx_hal_qspi.h
  • IS_QSPI_DDR_MODE : stm32wbxx_hal_qspi.h
  • IS_QSPI_DUMMY_CYCLES : stm32wbxx_hal_qspi.h
  • IS_QSPI_FIFO_THRESHOLD : stm32wbxx_hal_qspi.h
  • IS_QSPI_FLASH_SIZE : stm32wbxx_hal_qspi.h
  • IS_QSPI_FUNCTIONAL_MODE : stm32wbxx_hal_qspi.c
  • IS_QSPI_INSTRUCTION : stm32wbxx_hal_qspi.h
  • IS_QSPI_INSTRUCTION_MODE : stm32wbxx_hal_qspi.h
  • IS_QSPI_INTERVAL : stm32wbxx_hal_qspi.h
  • IS_QSPI_MATCH_MODE : stm32wbxx_hal_qspi.h
  • IS_QSPI_SIOO_MODE : stm32wbxx_hal_qspi.h
  • IS_QSPI_SSHIFT : stm32wbxx_hal_qspi.h
  • IS_QSPI_STATUS_BYTES_SIZE : stm32wbxx_hal_qspi.h
  • IS_QSPI_TIMEOUT_ACTIVATION : stm32wbxx_hal_qspi.h
  • IS_QSPI_TIMEOUT_PERIOD : stm32wbxx_hal_qspi.h
  • IS_RCC_ADCCLKSOURCE : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_CLOCKTYPE : stm32wbxx_hal_rcc.h
  • IS_RCC_CRS_ERRORLIMIT : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_CRS_FREQERRORDIR : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_CRS_HSI48CALIBRATION : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_CRS_RELOADVALUE : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_CRS_SYNC_DIV : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_CRS_SYNC_POLARITY : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_CRS_SYNC_SOURCE : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_HCLKx : stm32wbxx_hal_rcc.h
  • IS_RCC_HSE : stm32wbxx_hal_rcc.h
  • IS_RCC_HSI : stm32wbxx_hal_rcc.h
  • IS_RCC_HSI48 : stm32wbxx_hal_rcc.h
  • IS_RCC_HSI_CALIBRATION_VALUE : stm32wbxx_hal_rcc.h
  • IS_RCC_I2C1CLKSOURCE : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_I2C3CLKSOURCE : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_LPTIM1CLK : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_LPTIM2CLK : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_LPUART1CLKSOURCE : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_LSCO : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_LSCOSOURCE : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_LSE : stm32wbxx_hal_rcc.h
  • IS_RCC_LSE_DRIVE : stm32wbxx_hal_rcc.h
  • IS_RCC_LSI : stm32wbxx_hal_rcc.h
  • IS_RCC_LSI2_CALIBRATION_VALUE : stm32wbxx_hal_rcc.h
  • IS_RCC_MCO : stm32wbxx_hal_rcc.h
  • IS_RCC_MCO1SOURCE : stm32wbxx_hal_rcc.h
  • IS_RCC_MCO2SOURCE : stm32wbxx_hal_rcc.h
  • IS_RCC_MCO3SOURCE : stm32wbxx_hal_rcc.h
  • IS_RCC_MCODIV : stm32wbxx_hal_rcc.h
  • IS_RCC_MSI : stm32wbxx_hal_rcc.h
  • IS_RCC_MSI_CLOCK_RANGE : stm32wbxx_hal_rcc.h
  • IS_RCC_MSICALIBRATION_VALUE : stm32wbxx_hal_rcc.h
  • IS_RCC_OSCILLATORTYPE : stm32wbxx_hal_rcc.h
  • IS_RCC_PCLKx : stm32wbxx_hal_rcc.h
  • IS_RCC_PERIPHCLOCK : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_PLL : stm32wbxx_hal_rcc.h
  • IS_RCC_PLLM_VALUE : stm32wbxx_hal_rcc.h
  • IS_RCC_PLLN_VALUE : stm32wbxx_hal_rcc.h
  • IS_RCC_PLLP_VALUE : stm32wbxx_hal_rcc.h
  • IS_RCC_PLLQ_VALUE : stm32wbxx_hal_rcc.h
  • IS_RCC_PLLR_VALUE : stm32wbxx_hal_rcc.h
  • IS_RCC_PLLSAI1CLOCKOUT_VALUE : stm32wbxx_hal_rcc.h
  • IS_RCC_PLLSAI1N_VALUE : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_PLLSAI1P_VALUE : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_PLLSAI1Q_VALUE : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_PLLSAI1R_VALUE : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_PLLSOURCE : stm32wbxx_hal_rcc.h
  • IS_RCC_RFWKPCLKSOURCE : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_RNGCLKSOURCE : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_RTCCLKSOURCE : stm32wbxx_hal_rcc.h
  • IS_RCC_SAI1CLK : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_SMPSCLKDIV : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_SMPSCLKSOURCE : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_STOP_WAKEUPCLOCK : stm32wbxx_hal_rcc.h
  • IS_RCC_SYSCLKSOURCE : stm32wbxx_hal_rcc.h
  • IS_RCC_TRIMOSC : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_USART1CLKSOURCE : stm32wbxx_hal_rcc_ex.h
  • IS_RCC_USBCLKSOURCE : stm32wbxx_hal_rcc_ex.h
  • IS_RNG_CED : stm32wbxx_hal_rng.h
  • IS_RNG_FLAG : stm32wbxx_hal_rng.h
  • IS_RNG_IT : stm32wbxx_hal_rng.h
  • IS_RTC_ALARM : stm32wbxx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_DATE : stm32wbxx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_SEL : stm32wbxx_hal_rtc.h
  • IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY : stm32wbxx_hal_rtc.h
  • IS_RTC_ALARM_MASK : stm32wbxx_hal_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_MASK : stm32wbxx_hal_rtc.h
  • IS_RTC_ALARM_SUB_SECOND_VALUE : stm32wbxx_hal_rtc.h
  • IS_RTC_ASYNCH_PREDIV : stm32wbxx_hal_rtc.h
  • IS_RTC_BKP : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_CALIB_OUTPUT : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_DATE : stm32wbxx_hal_rtc.h
  • IS_RTC_DAYLIGHT_SAVING : stm32wbxx_hal_rtc.h
  • IS_RTC_FORMAT : stm32wbxx_hal_rtc.h
  • IS_RTC_HOUR12 : stm32wbxx_hal_rtc.h
  • IS_RTC_HOUR24 : stm32wbxx_hal_rtc.h
  • IS_RTC_HOUR_FORMAT : stm32wbxx_hal_rtc.h
  • IS_RTC_HOURFORMAT12 : stm32wbxx_hal_rtc.h
  • IS_RTC_MINUTES : stm32wbxx_hal_rtc.h
  • IS_RTC_MONTH : stm32wbxx_hal_rtc.h
  • IS_RTC_OUTPUT : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_OUTPUT_POL : stm32wbxx_hal_rtc.h
  • IS_RTC_OUTPUT_REMAP : stm32wbxx_hal_rtc.h
  • IS_RTC_OUTPUT_TYPE : stm32wbxx_hal_rtc.h
  • IS_RTC_SECONDS : stm32wbxx_hal_rtc.h
  • IS_RTC_SHIFT_ADD1S : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_SHIFT_SUBFS : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_MINUS : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_PERIOD : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_SMOOTH_CALIB_PLUS : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_STORE_OPERATION : stm32wbxx_hal_rtc.h
  • IS_RTC_SYNCH_PREDIV : stm32wbxx_hal_rtc.h
  • IS_RTC_TAMPER : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_TAMPER_ERASE_MODE : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_TAMPER_FILTER : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_TAMPER_INTERRUPT : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_TAMPER_MASKFLAG_STATE : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_TAMPER_PRECHARGE_DURATION : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_TAMPER_PULLUP_STATE : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_TAMPER_SAMPLING_FREQ : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TRIGGER : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_TIMESTAMP_PIN : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_WAKEUP_CLOCK : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_WAKEUP_COUNTER : stm32wbxx_hal_rtc_ex.h
  • IS_RTC_WEEKDAY : stm32wbxx_hal_rtc.h
  • IS_RTC_YEAR : stm32wbxx_hal_rtc.h
  • IS_SAI_AUDIO_FREQUENCY : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_ACTIVE_FRAME : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_CLOCK_STROBING : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_COMPANDING_MODE : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_DATASIZE : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_FIFO_THRESHOLD : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_FIRST_BIT : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_FIRSTBIT_OFFSET : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_FRAME_LENGTH : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_FS_DEFINITION : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_FS_OFFSET : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_FS_POLARITY : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_MASTER_DIVIDER : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_MCK_OUTPUT : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_MCK_OVERSAMPLING : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_MODE : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_MUTE_COUNTER : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_MUTE_VALUE : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_NODIVIDER : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_OUTPUT_DRIVE : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_PROTOCOL : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_SLOT_NUMBER : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_SLOT_SIZE : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_SYNCEXT : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_SYNCHRO : stm32wbxx_hal_sai.h
  • IS_SAI_BLOCK_TRISTATE_MANAGEMENT : stm32wbxx_hal_sai.h
  • IS_SAI_MONO_STEREO_MODE : stm32wbxx_hal_sai.h
  • IS_SAI_PDM_CLOCK_ENABLE : stm32wbxx_hal_sai.h
  • IS_SAI_PDM_MIC_DELAY : stm32wbxx_hal_sai_ex.h
  • IS_SAI_PDM_MIC_PAIRS_NUMBER : stm32wbxx_hal_sai.h
  • IS_SAI_PROTOCOL_DATASIZE : stm32wbxx_hal_sai.h
  • IS_SAI_SLOT_ACTIVE : stm32wbxx_hal_sai.h
  • IS_SAI_SUPPORTED_PROTOCOL : stm32wbxx_hal_sai.h
  • IS_SMARTCARD_ADVFEATURE_DATAINV : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_DMAONRXERROR : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_INIT : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_MSBFIRST : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_RXINV : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_SWAP : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_ADVFEATURE_TXINV : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_AUTORETRY_COUNT : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_BAUDRATE : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_BLOCKLENGTH : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_CLOCKPRESCALER : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_FIFOMODE_STATE : stm32wbxx_hal_smartcard_ex.h
  • IS_SMARTCARD_LASTBIT : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_MODE : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_NACK : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_ONE_BIT_SAMPLE : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_OVERRUN : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_PARITY : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_PHASE : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_POLARITY : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_REQUEST_PARAMETER : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_RXFIFO_THRESHOLD : stm32wbxx_hal_smartcard_ex.h
  • IS_SMARTCARD_STOPBITS : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_TIMEOUT : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_TIMEOUT_VALUE : stm32wbxx_hal_smartcard.h
  • IS_SMARTCARD_TRANSMISSION_COMPLETION : stm32wbxx_hal_smartcard_ex.h
  • IS_SMARTCARD_TXFIFO_THRESHOLD : stm32wbxx_hal_smartcard_ex.h
  • IS_SMARTCARD_WORD_LENGTH : stm32wbxx_hal_smartcard.h
  • IS_SMBUS_ADDRESSING_MODE : stm32wbxx_hal_smbus.h
  • IS_SMBUS_ANALOG_FILTER : stm32wbxx_hal_smbus.h
  • IS_SMBUS_DIGITAL_FILTER : stm32wbxx_hal_smbus.h
  • IS_SMBUS_DUAL_ADDRESS : stm32wbxx_hal_smbus.h
  • IS_SMBUS_GENERAL_CALL : stm32wbxx_hal_smbus.h
  • IS_SMBUS_NO_STRETCH : stm32wbxx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS1 : stm32wbxx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS2 : stm32wbxx_hal_smbus.h
  • IS_SMBUS_OWN_ADDRESS2_MASK : stm32wbxx_hal_smbus.h
  • IS_SMBUS_PEC : stm32wbxx_hal_smbus.h
  • IS_SMBUS_PERIPHERAL_MODE : stm32wbxx_hal_smbus.h
  • IS_SMBUS_TRANSFER_MODE : stm32wbxx_hal_smbus.h
  • IS_SMBUS_TRANSFER_OPTIONS_REQUEST : stm32wbxx_hal_smbus.h
  • IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST : stm32wbxx_hal_smbus.h
  • IS_SMBUS_TRANSFER_REQUEST : stm32wbxx_hal_smbus.h
  • IS_SPI_BAUDRATE_PRESCALER : stm32wbxx_hal_spi.h
  • IS_SPI_CPHA : stm32wbxx_hal_spi.h
  • IS_SPI_CPOL : stm32wbxx_hal_spi.h
  • IS_SPI_CRC_CALCULATION : stm32wbxx_hal_spi.h
  • IS_SPI_CRC_LENGTH : stm32wbxx_hal_spi.h
  • IS_SPI_CRC_POLYNOMIAL : stm32wbxx_hal_spi.h
  • IS_SPI_DATASIZE : stm32wbxx_hal_spi.h
  • IS_SPI_DIRECTION : stm32wbxx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES : stm32wbxx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES_OR_1LINE : stm32wbxx_hal_spi.h
  • IS_SPI_DMA_HANDLE : stm32wbxx_hal_spi.h
  • IS_SPI_FIRST_BIT : stm32wbxx_hal_spi.h
  • IS_SPI_MODE : stm32wbxx_hal_spi.h
  • IS_SPI_NSS : stm32wbxx_hal_spi.h
  • IS_SPI_NSSP : stm32wbxx_hal_spi.h
  • IS_SPI_TIMODE : stm32wbxx_hal_spi.h
  • IS_SYSCFG_FASTMODEPLUS : stm32wbxx_hal.h
  • IS_SYSCFG_FPU_INTERRUPT : stm32wbxx_hal.h
  • IS_SYSCFG_SECURITY_ACCESS : stm32wbxx_hal.h
  • IS_SYSCFG_SRAM2WRP_PAGE : stm32wbxx_hal.h
  • IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE : stm32wbxx_hal.h
  • IS_SYSCFG_VREFBUF_TRIMMING : stm32wbxx_hal.h
  • IS_SYSCFG_VREFBUF_VOLTAGE_SCALE : stm32wbxx_hal.h
  • IS_SYSTICK_CLK_SOURCE : stm32wbxx_hal_cortex.h
  • IS_TICKFREQ : stm32wbxx_hal.h
  • IS_TIM_AUTOMATIC_OUTPUT_STATE : stm32wbxx_hal_tim.h
  • IS_TIM_AUTORELOAD_PRELOAD : stm32wbxx_hal_tim.h
  • IS_TIM_BREAK2_POLARITY : stm32wbxx_hal_tim.h
  • IS_TIM_BREAK2_STATE : stm32wbxx_hal_tim.h
  • IS_TIM_BREAK_FILTER : stm32wbxx_hal_tim.h
  • IS_TIM_BREAK_POLARITY : stm32wbxx_hal_tim.h
  • IS_TIM_BREAK_STATE : stm32wbxx_hal_tim.h
  • IS_TIM_BREAK_SYSTEM : stm32wbxx_hal_tim.h
  • IS_TIM_BREAKINPUT : stm32wbxx_hal_tim_ex.h
  • IS_TIM_BREAKINPUTSOURCE : stm32wbxx_hal_tim_ex.h
  • IS_TIM_BREAKINPUTSOURCE_POLARITY : stm32wbxx_hal_tim_ex.h
  • IS_TIM_BREAKINPUTSOURCE_STATE : stm32wbxx_hal_tim_ex.h
  • IS_TIM_CHANNELS : stm32wbxx_hal_tim.h
  • IS_TIM_CLEARINPUT_FILTER : stm32wbxx_hal_tim.h
  • IS_TIM_CLEARINPUT_POLARITY : stm32wbxx_hal_tim.h
  • IS_TIM_CLEARINPUT_PRESCALER : stm32wbxx_hal_tim.h
  • IS_TIM_CLEARINPUT_SOURCE : stm32wbxx_hal_tim.h
  • IS_TIM_CLOCKDIVISION_DIV : stm32wbxx_hal_tim.h
  • IS_TIM_CLOCKFILTER : stm32wbxx_hal_tim.h
  • IS_TIM_CLOCKPOLARITY : stm32wbxx_hal_tim.h
  • IS_TIM_CLOCKPRESCALER : stm32wbxx_hal_tim.h
  • IS_TIM_CLOCKSOURCE : stm32wbxx_hal_tim.h
  • IS_TIM_COMPLEMENTARY_CHANNELS : stm32wbxx_hal_tim.h
  • IS_TIM_COUNTER_MODE : stm32wbxx_hal_tim.h
  • IS_TIM_DEADTIME : stm32wbxx_hal_tim.h
  • IS_TIM_DMA_BASE : stm32wbxx_hal_tim.h
  • IS_TIM_DMA_LENGTH : stm32wbxx_hal_tim.h
  • IS_TIM_DMA_SOURCE : stm32wbxx_hal_tim.h
  • IS_TIM_ENCODER_MODE : stm32wbxx_hal_tim.h
  • IS_TIM_ENCODERINPUT_POLARITY : stm32wbxx_hal_tim.h
  • IS_TIM_EVENT_SOURCE : stm32wbxx_hal_tim.h
  • IS_TIM_FAST_STATE : stm32wbxx_hal_tim.h
  • IS_TIM_GROUPCH5 : stm32wbxx_hal_tim.h
  • IS_TIM_IC_FILTER : stm32wbxx_hal_tim.h
  • IS_TIM_IC_POLARITY : stm32wbxx_hal_tim.h
  • IS_TIM_IC_PRESCALER : stm32wbxx_hal_tim.h
  • IS_TIM_IC_SELECTION : stm32wbxx_hal_tim.h
  • IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION : stm32wbxx_hal_tim.h
  • IS_TIM_LOCK_LEVEL : stm32wbxx_hal_tim.h
  • IS_TIM_MSM_STATE : stm32wbxx_hal_tim.h
  • IS_TIM_OC_MODE : stm32wbxx_hal_tim.h
  • IS_TIM_OC_POLARITY : stm32wbxx_hal_tim.h
  • IS_TIM_OCIDLE_STATE : stm32wbxx_hal_tim.h
  • IS_TIM_OCN_POLARITY : stm32wbxx_hal_tim.h
  • IS_TIM_OCNIDLE_STATE : stm32wbxx_hal_tim.h
  • IS_TIM_OPM_CHANNELS : stm32wbxx_hal_tim.h
  • IS_TIM_OPM_MODE : stm32wbxx_hal_tim.h
  • IS_TIM_OSSI_STATE : stm32wbxx_hal_tim.h
  • IS_TIM_OSSR_STATE : stm32wbxx_hal_tim.h
  • IS_TIM_PWM_MODE : stm32wbxx_hal_tim.h
  • IS_TIM_REMAP : stm32wbxx_hal_tim_ex.h
  • IS_TIM_SLAVE_MODE : stm32wbxx_hal_tim.h
  • IS_TIM_SLAVEMODE_TRIGGER_ENABLED : stm32wbxx_hal_tim.h
  • IS_TIM_TI1SELECTION : stm32wbxx_hal_tim.h
  • IS_TIM_TRGO2_SOURCE : stm32wbxx_hal_tim.h
  • IS_TIM_TRGO_SOURCE : stm32wbxx_hal_tim.h
  • IS_TIM_TRIGGER_SELECTION : stm32wbxx_hal_tim.h
  • IS_TIM_TRIGGERFILTER : stm32wbxx_hal_tim.h
  • IS_TIM_TRIGGERPOLARITY : stm32wbxx_hal_tim.h
  • IS_TIM_TRIGGERPRESCALER : stm32wbxx_hal_tim.h
  • IS_TIMESTAMP_EDGE : stm32wbxx_hal_rtc_ex.h
  • IS_TRANSFER_MODE : stm32wbxx_hal_i2c.h
  • IS_TRANSFER_REQUEST : stm32wbxx_hal_i2c.h
  • IS_TSC_ACQ_MODE : stm32wbxx_hal_tsc.h
  • IS_TSC_CTPH : stm32wbxx_hal_tsc.h
  • IS_TSC_CTPL : stm32wbxx_hal_tsc.h
  • IS_TSC_GROUP : stm32wbxx_hal_tsc.h
  • IS_TSC_GROUP_INDEX : stm32wbxx_hal_tsc.h
  • IS_TSC_IODEF : stm32wbxx_hal_tsc.h
  • IS_TSC_MCE_IT : stm32wbxx_hal_tsc.h
  • IS_TSC_MCV : stm32wbxx_hal_tsc.h
  • IS_TSC_PG_PRESC : stm32wbxx_hal_tsc.h
  • IS_TSC_SS : stm32wbxx_hal_tsc.h
  • IS_TSC_SS_PRESC : stm32wbxx_hal_tsc.h
  • IS_TSC_SSD : stm32wbxx_hal_tsc.h
  • IS_TSC_SYNC_POL : stm32wbxx_hal_tsc.h
  • IS_UART_ADDRESSLENGTH_DETECT : stm32wbxx_hal_uart_ex.h
  • IS_UART_ADVFEATURE_AUTOBAUDRATE : stm32wbxx_hal_uart.h
  • IS_UART_ADVFEATURE_AUTOBAUDRATEMODE : stm32wbxx_hal_uart.h
  • IS_UART_ADVFEATURE_DATAINV : stm32wbxx_hal_uart.h
  • IS_UART_ADVFEATURE_DMAONRXERROR : stm32wbxx_hal_uart.h
  • IS_UART_ADVFEATURE_INIT : stm32wbxx_hal_uart.h
  • IS_UART_ADVFEATURE_MSBFIRST : stm32wbxx_hal_uart.h
  • IS_UART_ADVFEATURE_RXINV : stm32wbxx_hal_uart.h
  • IS_UART_ADVFEATURE_STOPMODE : stm32wbxx_hal_uart.h
  • IS_UART_ADVFEATURE_SWAP : stm32wbxx_hal_uart.h
  • IS_UART_ADVFEATURE_TXINV : stm32wbxx_hal_uart.h
  • IS_UART_ASSERTIONTIME : stm32wbxx_hal_uart.h
  • IS_UART_BAUDRATE : stm32wbxx_hal_uart.h
  • IS_UART_DE_POLARITY : stm32wbxx_hal_uart.h
  • IS_UART_DEASSERTIONTIME : stm32wbxx_hal_uart.h
  • IS_UART_DMA_RX : stm32wbxx_hal_uart.h
  • IS_UART_DMA_TX : stm32wbxx_hal_uart.h
  • IS_UART_HALF_DUPLEX : stm32wbxx_hal_uart.h
  • IS_UART_HARDWARE_FLOW_CONTROL : stm32wbxx_hal_uart.h
  • IS_UART_LIN : stm32wbxx_hal_uart.h
  • IS_UART_LIN_BREAK_DETECT_LENGTH : stm32wbxx_hal_uart.h
  • IS_UART_MODE : stm32wbxx_hal_uart.h
  • IS_UART_MUTE_MODE : stm32wbxx_hal_uart.h
  • IS_UART_ONE_BIT_SAMPLE : stm32wbxx_hal_uart.h
  • IS_UART_OVERRUN : stm32wbxx_hal_uart.h
  • IS_UART_OVERSAMPLING : stm32wbxx_hal_uart.h
  • IS_UART_PARITY : stm32wbxx_hal_uart.h
  • IS_UART_PRESCALER : stm32wbxx_hal_uart.h
  • IS_UART_RECEIVER_TIMEOUT : stm32wbxx_hal_uart.h
  • IS_UART_RECEIVER_TIMEOUT_VALUE : stm32wbxx_hal_uart.h
  • IS_UART_REQUEST_PARAMETER : stm32wbxx_hal_uart.h
  • IS_UART_RXFIFO_THRESHOLD : stm32wbxx_hal_uart_ex.h
  • IS_UART_STATE : stm32wbxx_hal_uart.h
  • IS_UART_STOPBITS : stm32wbxx_hal_uart.h
  • IS_UART_TXFIFO_THRESHOLD : stm32wbxx_hal_uart_ex.h
  • IS_UART_WAKEUP_SELECTION : stm32wbxx_hal_uart.h
  • IS_UART_WAKEUPMETHOD : stm32wbxx_hal_uart.h
  • IS_UART_WORD_LENGTH : stm32wbxx_hal_uart_ex.h
  • IS_USART_BAUDRATE : stm32wbxx_hal_usart.h
  • IS_USART_CLOCK : stm32wbxx_hal_usart.h
  • IS_USART_FIFO_MODE_STATE : stm32wbxx_hal_usart_ex.h
  • IS_USART_LASTBIT : stm32wbxx_hal_usart.h
  • IS_USART_MODE : stm32wbxx_hal_usart.h
  • IS_USART_NSS : stm32wbxx_hal_usart_ex.h
  • IS_USART_OVERSAMPLING : stm32wbxx_hal_usart.h
  • IS_USART_PARITY : stm32wbxx_hal_usart.h
  • IS_USART_PHASE : stm32wbxx_hal_usart.h
  • IS_USART_POLARITY : stm32wbxx_hal_usart.h
  • IS_USART_PRESCALER : stm32wbxx_hal_usart.h
  • IS_USART_REQUEST_PARAMETER : stm32wbxx_hal_usart.h
  • IS_USART_RXFIFO_THRESHOLD : stm32wbxx_hal_usart_ex.h
  • IS_USART_SLAVEMODE : stm32wbxx_hal_usart_ex.h
  • IS_USART_STOPBITS : stm32wbxx_hal_usart.h
  • IS_USART_TXFIFO_THRESHOLD : stm32wbxx_hal_usart_ex.h
  • IS_USART_WORD_LENGTH : stm32wbxx_hal_usart_ex.h
  • IS_WWDG_COUNTER : stm32wbxx_hal_wwdg.h
  • IS_WWDG_EWI_MODE : stm32wbxx_hal_wwdg.h
  • IS_WWDG_PRESCALER : stm32wbxx_hal_wwdg.h
  • IS_WWDG_WINDOW : stm32wbxx_hal_wwdg.h
  • IWDG_DISABLE_WRITE_ACCESS : stm32wbxx_hal_iwdg.h
  • IWDG_ENABLE_WRITE_ACCESS : stm32wbxx_hal_iwdg.h
  • IWDG_KEY_ENABLE : stm32wbxx_hal_iwdg.h
  • IWDG_KEY_RELOAD : stm32wbxx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_DISABLE : stm32wbxx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_ENABLE : stm32wbxx_hal_iwdg.h
  • IWDG_PRESCALER_128 : stm32wbxx_hal_iwdg.h
  • IWDG_PRESCALER_16 : stm32wbxx_hal_iwdg.h
  • IWDG_PRESCALER_256 : stm32wbxx_hal_iwdg.h
  • IWDG_PRESCALER_32 : stm32wbxx_hal_iwdg.h
  • IWDG_PRESCALER_4 : stm32wbxx_hal_iwdg.h
  • IWDG_PRESCALER_64 : stm32wbxx_hal_iwdg.h
  • IWDG_PRESCALER_8 : stm32wbxx_hal_iwdg.h
  • IWDG_WINDOW_DISABLE : stm32wbxx_hal_iwdg.h
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

  • File List
  • Globals
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- l -

  • LATENCY_TIMEOUT_VALUE : stm32wbxx_hal_rcc.c
  • LCD_BIAS_1_2 : stm32wbxx_hal_lcd.h
  • LCD_BIAS_1_3 : stm32wbxx_hal_lcd.h
  • LCD_BIAS_1_4 : stm32wbxx_hal_lcd.h
  • LCD_BLINKFREQUENCY_DIV1024 : stm32wbxx_hal_lcd.h
  • LCD_BLINKFREQUENCY_DIV128 : stm32wbxx_hal_lcd.h
  • LCD_BLINKFREQUENCY_DIV16 : stm32wbxx_hal_lcd.h
  • LCD_BLINKFREQUENCY_DIV256 : stm32wbxx_hal_lcd.h
  • LCD_BLINKFREQUENCY_DIV32 : stm32wbxx_hal_lcd.h
  • LCD_BLINKFREQUENCY_DIV512 : stm32wbxx_hal_lcd.h
  • LCD_BLINKFREQUENCY_DIV64 : stm32wbxx_hal_lcd.h
  • LCD_BLINKFREQUENCY_DIV8 : stm32wbxx_hal_lcd.h
  • LCD_BLINKMODE_ALLSEG_ALLCOM : stm32wbxx_hal_lcd.h
  • LCD_BLINKMODE_OFF : stm32wbxx_hal_lcd.h
  • LCD_BLINKMODE_SEG0_ALLCOM : stm32wbxx_hal_lcd.h
  • LCD_BLINKMODE_SEG0_COM0 : stm32wbxx_hal_lcd.h
  • LCD_CONTRASTLEVEL_0 : stm32wbxx_hal_lcd.h
  • LCD_CONTRASTLEVEL_1 : stm32wbxx_hal_lcd.h
  • LCD_CONTRASTLEVEL_2 : stm32wbxx_hal_lcd.h
  • LCD_CONTRASTLEVEL_3 : stm32wbxx_hal_lcd.h
  • LCD_CONTRASTLEVEL_4 : stm32wbxx_hal_lcd.h
  • LCD_CONTRASTLEVEL_5 : stm32wbxx_hal_lcd.h
  • LCD_CONTRASTLEVEL_6 : stm32wbxx_hal_lcd.h
  • LCD_CONTRASTLEVEL_7 : stm32wbxx_hal_lcd.h
  • LCD_DEADTIME_0 : stm32wbxx_hal_lcd.h
  • LCD_DEADTIME_1 : stm32wbxx_hal_lcd.h
  • LCD_DEADTIME_2 : stm32wbxx_hal_lcd.h
  • LCD_DEADTIME_3 : stm32wbxx_hal_lcd.h
  • LCD_DEADTIME_4 : stm32wbxx_hal_lcd.h
  • LCD_DEADTIME_5 : stm32wbxx_hal_lcd.h
  • LCD_DEADTIME_6 : stm32wbxx_hal_lcd.h
  • LCD_DEADTIME_7 : stm32wbxx_hal_lcd.h
  • LCD_DIVIDER_16 : stm32wbxx_hal_lcd.h
  • LCD_DIVIDER_17 : stm32wbxx_hal_lcd.h
  • LCD_DIVIDER_18 : stm32wbxx_hal_lcd.h
  • LCD_DIVIDER_19 : stm32wbxx_hal_lcd.h
  • LCD_DIVIDER_20 : stm32wbxx_hal_lcd.h
  • LCD_DIVIDER_21 : stm32wbxx_hal_lcd.h
  • LCD_DIVIDER_22 : stm32wbxx_hal_lcd.h
  • LCD_DIVIDER_23 : stm32wbxx_hal_lcd.h
  • LCD_DIVIDER_24 : stm32wbxx_hal_lcd.h
  • LCD_DIVIDER_25 : stm32wbxx_hal_lcd.h
  • LCD_DIVIDER_26 : stm32wbxx_hal_lcd.h
  • LCD_DIVIDER_27 : stm32wbxx_hal_lcd.h
  • LCD_DIVIDER_28 : stm32wbxx_hal_lcd.h
  • LCD_DIVIDER_29 : stm32wbxx_hal_lcd.h
  • LCD_DIVIDER_30 : stm32wbxx_hal_lcd.h
  • LCD_DIVIDER_31 : stm32wbxx_hal_lcd.h
  • LCD_DUTY_1_2 : stm32wbxx_hal_lcd.h
  • LCD_DUTY_1_3 : stm32wbxx_hal_lcd.h
  • LCD_DUTY_1_4 : stm32wbxx_hal_lcd.h
  • LCD_DUTY_1_8 : stm32wbxx_hal_lcd.h
  • LCD_DUTY_STATIC : stm32wbxx_hal_lcd.h
  • LCD_FLAG_ENS : stm32wbxx_hal_lcd.h
  • LCD_FLAG_FCRSF : stm32wbxx_hal_lcd.h
  • LCD_FLAG_RDY : stm32wbxx_hal_lcd.h
  • LCD_FLAG_SOF : stm32wbxx_hal_lcd.h
  • LCD_FLAG_UDD : stm32wbxx_hal_lcd.h
  • LCD_FLAG_UDR : stm32wbxx_hal_lcd.h
  • LCD_HIGHDRIVE_DISABLE : stm32wbxx_hal_lcd.h
  • LCD_HIGHDRIVE_ENABLE : stm32wbxx_hal_lcd.h
  • LCD_IT_SOF : stm32wbxx_hal_lcd.h
  • LCD_IT_UDD : stm32wbxx_hal_lcd.h
  • LCD_MUXSEGMENT_DISABLE : stm32wbxx_hal_lcd.h
  • LCD_MUXSEGMENT_ENABLE : stm32wbxx_hal_lcd.h
  • LCD_PRESCALER_1 : stm32wbxx_hal_lcd.h
  • LCD_PRESCALER_1024 : stm32wbxx_hal_lcd.h
  • LCD_PRESCALER_128 : stm32wbxx_hal_lcd.h
  • LCD_PRESCALER_16 : stm32wbxx_hal_lcd.h
  • LCD_PRESCALER_16384 : stm32wbxx_hal_lcd.h
  • LCD_PRESCALER_2 : stm32wbxx_hal_lcd.h
  • LCD_PRESCALER_2048 : stm32wbxx_hal_lcd.h
  • LCD_PRESCALER_256 : stm32wbxx_hal_lcd.h
  • LCD_PRESCALER_32 : stm32wbxx_hal_lcd.h
  • LCD_PRESCALER_32768 : stm32wbxx_hal_lcd.h
  • LCD_PRESCALER_4 : stm32wbxx_hal_lcd.h
  • LCD_PRESCALER_4096 : stm32wbxx_hal_lcd.h
  • LCD_PRESCALER_512 : stm32wbxx_hal_lcd.h
  • LCD_PRESCALER_64 : stm32wbxx_hal_lcd.h
  • LCD_PRESCALER_8 : stm32wbxx_hal_lcd.h
  • LCD_PRESCALER_8192 : stm32wbxx_hal_lcd.h
  • LCD_PULSEONDURATION_0 : stm32wbxx_hal_lcd.h
  • LCD_PULSEONDURATION_1 : stm32wbxx_hal_lcd.h
  • LCD_PULSEONDURATION_2 : stm32wbxx_hal_lcd.h
  • LCD_PULSEONDURATION_3 : stm32wbxx_hal_lcd.h
  • LCD_PULSEONDURATION_4 : stm32wbxx_hal_lcd.h
  • LCD_PULSEONDURATION_5 : stm32wbxx_hal_lcd.h
  • LCD_PULSEONDURATION_6 : stm32wbxx_hal_lcd.h
  • LCD_PULSEONDURATION_7 : stm32wbxx_hal_lcd.h
  • LCD_RAM_REGISTER0 : stm32wbxx_hal_lcd.h
  • LCD_RAM_REGISTER1 : stm32wbxx_hal_lcd.h
  • LCD_RAM_REGISTER10 : stm32wbxx_hal_lcd.h
  • LCD_RAM_REGISTER11 : stm32wbxx_hal_lcd.h
  • LCD_RAM_REGISTER12 : stm32wbxx_hal_lcd.h
  • LCD_RAM_REGISTER13 : stm32wbxx_hal_lcd.h
  • LCD_RAM_REGISTER14 : stm32wbxx_hal_lcd.h
  • LCD_RAM_REGISTER15 : stm32wbxx_hal_lcd.h
  • LCD_RAM_REGISTER2 : stm32wbxx_hal_lcd.h
  • LCD_RAM_REGISTER3 : stm32wbxx_hal_lcd.h
  • LCD_RAM_REGISTER4 : stm32wbxx_hal_lcd.h
  • LCD_RAM_REGISTER5 : stm32wbxx_hal_lcd.h
  • LCD_RAM_REGISTER6 : stm32wbxx_hal_lcd.h
  • LCD_RAM_REGISTER7 : stm32wbxx_hal_lcd.h
  • LCD_RAM_REGISTER8 : stm32wbxx_hal_lcd.h
  • LCD_RAM_REGISTER9 : stm32wbxx_hal_lcd.h
  • LCD_TIMEOUT_VALUE : stm32wbxx_hal_lcd.c
  • LCD_VOLTAGESOURCE_EXTERNAL : stm32wbxx_hal_lcd.h
  • LCD_VOLTAGESOURCE_INTERNAL : stm32wbxx_hal_lcd.h
  • LL_ADC_AWD1 : stm32wbxx_ll_adc.h
  • LL_ADC_AWD2 : stm32wbxx_ll_adc.h
  • LL_ADC_AWD3 : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_ALL_CHANNELS_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_ALL_CHANNELS_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_ALL_CHANNELS_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CH_VBAT_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CH_VBAT_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CH_VBAT_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CH_VREFINT_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CH_VREFINT_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CH_VREFINT_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_0_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_0_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_0_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_10_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_10_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_10_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_11_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_11_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_11_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_12_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_12_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_12_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_13_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_13_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_13_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_14_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_14_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_14_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_15_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_15_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_15_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_16_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_16_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_16_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_17_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_17_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_17_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_18_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_18_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_18_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_1_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_1_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_1_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_2_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_2_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_2_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_3_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_3_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_3_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_4_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_4_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_4_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_5_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_5_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_5_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_6_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_6_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_6_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_7_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_7_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_7_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_8_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_8_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_8_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_9_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_9_REG : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_9_REG_INJ : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_DISABLE : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_THRESHOLD_HIGH : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_THRESHOLD_LOW : stm32wbxx_ll_adc.h
  • LL_ADC_AWD_THRESHOLDS_HIGH_LOW : stm32wbxx_ll_adc.h
  • LL_ADC_BOTH_SINGLE_DIFF_ENDED : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_0 : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_1 : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_10 : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_11 : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_12 : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_13 : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_14 : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_15 : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_16 : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_17 : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_18 : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_2 : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_3 : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_4 : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_5 : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_6 : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_7 : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_8 : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_9 : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_TEMPSENSOR : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_VBAT : stm32wbxx_ll_adc.h
  • LL_ADC_CHANNEL_VREFINT : stm32wbxx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV1 : stm32wbxx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV10 : stm32wbxx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV12 : stm32wbxx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV128 : stm32wbxx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV16 : stm32wbxx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV2 : stm32wbxx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV256 : stm32wbxx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV32 : stm32wbxx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV4 : stm32wbxx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV6 : stm32wbxx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV64 : stm32wbxx_ll_adc.h
  • LL_ADC_CLOCK_ASYNC_DIV8 : stm32wbxx_ll_adc.h
  • LL_ADC_CLOCK_SYNC_PCLK_DIV1 : stm32wbxx_ll_adc.h
  • LL_ADC_CLOCK_SYNC_PCLK_DIV2 : stm32wbxx_ll_adc.h
  • LL_ADC_CLOCK_SYNC_PCLK_DIV4 : stm32wbxx_ll_adc.h
  • LL_ADC_DATA_ALIGN_LEFT : stm32wbxx_ll_adc.h
  • LL_ADC_DATA_ALIGN_RIGHT : stm32wbxx_ll_adc.h
  • LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES : stm32wbxx_ll_adc.h
  • LL_ADC_DELAY_INTERNAL_REGUL_STAB_US : stm32wbxx_ll_adc.h
  • LL_ADC_DELAY_TEMPSENSOR_STAB_US : stm32wbxx_ll_adc.h
  • LL_ADC_DELAY_VREFINT_STAB_US : stm32wbxx_ll_adc.h
  • LL_ADC_DIFFERENTIAL_ENDED : stm32wbxx_ll_adc.h
  • LL_ADC_DMA_REG_REGULAR_DATA : stm32wbxx_ll_adc.h
  • LL_ADC_FLAG_ADRDY : stm32wbxx_ll_adc.h
  • LL_ADC_FLAG_AWD1 : stm32wbxx_ll_adc.h
  • LL_ADC_FLAG_AWD2 : stm32wbxx_ll_adc.h
  • LL_ADC_FLAG_AWD3 : stm32wbxx_ll_adc.h
  • LL_ADC_FLAG_EOC : stm32wbxx_ll_adc.h
  • LL_ADC_FLAG_EOS : stm32wbxx_ll_adc.h
  • LL_ADC_FLAG_EOSMP : stm32wbxx_ll_adc.h
  • LL_ADC_FLAG_JEOC : stm32wbxx_ll_adc.h
  • LL_ADC_FLAG_JEOS : stm32wbxx_ll_adc.h
  • LL_ADC_FLAG_JQOVF : stm32wbxx_ll_adc.h
  • LL_ADC_FLAG_OVR : stm32wbxx_ll_adc.h
  • LL_ADC_GROUP_INJECTED : stm32wbxx_ll_adc.h
  • LL_ADC_GROUP_REGULAR : stm32wbxx_ll_adc.h
  • LL_ADC_GROUP_REGULAR_INJECTED : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_QUEUE_DISABLE : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_RANK_1 : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_RANK_2 : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_RANK_3 : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_RANK_4 : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_SEQ_DISCONT_1RANK : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_SEQ_DISCONT_DISABLE : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_DISABLE : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_FALLING : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_RISING : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_RISINGFALLING : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM1_CH4 : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM2_CH1 : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM2_TRGO : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_TRIG_FROM_GRP_REGULAR : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_TRIG_INDEPENDENT : stm32wbxx_ll_adc.h
  • LL_ADC_INJ_TRIG_SOFTWARE : stm32wbxx_ll_adc.h
  • LL_ADC_IT_ADRDY : stm32wbxx_ll_adc.h
  • LL_ADC_IT_AWD1 : stm32wbxx_ll_adc.h
  • LL_ADC_IT_AWD2 : stm32wbxx_ll_adc.h
  • LL_ADC_IT_AWD3 : stm32wbxx_ll_adc.h
  • LL_ADC_IT_EOC : stm32wbxx_ll_adc.h
  • LL_ADC_IT_EOS : stm32wbxx_ll_adc.h
  • LL_ADC_IT_EOSMP : stm32wbxx_ll_adc.h
  • LL_ADC_IT_JEOC : stm32wbxx_ll_adc.h
  • LL_ADC_IT_JEOS : stm32wbxx_ll_adc.h
  • LL_ADC_IT_JQOVF : stm32wbxx_ll_adc.h
  • LL_ADC_IT_OVR : stm32wbxx_ll_adc.h
  • LL_ADC_LP_AUTOWAIT : stm32wbxx_ll_adc.h
  • LL_ADC_LP_MODE_NONE : stm32wbxx_ll_adc.h
  • LL_ADC_OFFSET_1 : stm32wbxx_ll_adc.h
  • LL_ADC_OFFSET_2 : stm32wbxx_ll_adc.h
  • LL_ADC_OFFSET_3 : stm32wbxx_ll_adc.h
  • LL_ADC_OFFSET_4 : stm32wbxx_ll_adc.h
  • LL_ADC_OFFSET_DISABLE : stm32wbxx_ll_adc.h
  • LL_ADC_OFFSET_ENABLE : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_DISABLE : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_GRP_INJ_REG_RESUMED : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_GRP_INJECTED : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_GRP_REGULAR_CONTINUED : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_GRP_REGULAR_RESUMED : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_RATIO_128 : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_RATIO_16 : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_RATIO_2 : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_RATIO_256 : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_RATIO_32 : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_RATIO_4 : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_RATIO_64 : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_RATIO_8 : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_REG_CONT : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_REG_DISCONT : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_SHIFT_NONE : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_1 : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_2 : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_3 : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_4 : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_5 : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_6 : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_7 : stm32wbxx_ll_adc.h
  • LL_ADC_OVS_SHIFT_RIGHT_8 : stm32wbxx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_NONE : stm32wbxx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_TEMPSENSOR : stm32wbxx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_VBAT : stm32wbxx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_VREFINT : stm32wbxx_ll_adc.h
  • LL_ADC_ReadReg : stm32wbxx_ll_adc.h
  • LL_ADC_REG_CONV_CONTINUOUS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_CONV_SINGLE : stm32wbxx_ll_adc.h
  • LL_ADC_REG_DMA_TRANSFER_LIMITED : stm32wbxx_ll_adc.h
  • LL_ADC_REG_DMA_TRANSFER_NONE : stm32wbxx_ll_adc.h
  • LL_ADC_REG_DMA_TRANSFER_UNLIMITED : stm32wbxx_ll_adc.h
  • LL_ADC_REG_OVR_DATA_OVERWRITTEN : stm32wbxx_ll_adc.h
  • LL_ADC_REG_OVR_DATA_PRESERVED : stm32wbxx_ll_adc.h
  • LL_ADC_REG_RANK_1 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_RANK_10 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_RANK_11 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_RANK_12 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_RANK_13 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_RANK_14 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_RANK_15 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_RANK_16 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_RANK_2 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_RANK_3 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_RANK_4 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_RANK_5 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_RANK_6 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_RANK_7 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_RANK_8 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_RANK_9 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_1RANK : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_2RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_3RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_4RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_5RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_6RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_7RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_8RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_DISABLE : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_DISABLE : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS : stm32wbxx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_EXTI_LINE11 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_FALLING : stm32wbxx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_RISING : stm32wbxx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_RISINGFALLING : stm32wbxx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_CH1 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_CH2 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_CH3 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_TRGO : stm32wbxx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM2_CH2 : stm32wbxx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM2_TRGO : stm32wbxx_ll_adc.h
  • LL_ADC_REG_TRIG_SOFTWARE : stm32wbxx_ll_adc.h
  • LL_ADC_RESOLUTION_10B : stm32wbxx_ll_adc.h
  • LL_ADC_RESOLUTION_12B : stm32wbxx_ll_adc.h
  • LL_ADC_RESOLUTION_6B : stm32wbxx_ll_adc.h
  • LL_ADC_RESOLUTION_8B : stm32wbxx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_12CYCLES_5 : stm32wbxx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_247CYCLES_5 : stm32wbxx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_24CYCLES_5 : stm32wbxx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_2CYCLES_5 : stm32wbxx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_47CYCLES_5 : stm32wbxx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_640CYCLES_5 : stm32wbxx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_6CYCLES_5 : stm32wbxx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_92CYCLES_5 : stm32wbxx_ll_adc.h
  • LL_ADC_SINGLE_ENDED : stm32wbxx_ll_adc.h
  • LL_ADC_WriteReg : stm32wbxx_ll_adc.h
  • LL_AHB1_GRP1_PERIPH_ALL : stm32wbxx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_CRC : stm32wbxx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_DMA1 : stm32wbxx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_DMA2 : stm32wbxx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_DMAMUX1 : stm32wbxx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_SRAM1 : stm32wbxx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_TSC : stm32wbxx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_ADC : stm32wbxx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_AES1 : stm32wbxx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_ALL : stm32wbxx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOA : stm32wbxx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOB : stm32wbxx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOC : stm32wbxx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOD : stm32wbxx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOE : stm32wbxx_ll_bus.h
  • LL_AHB2_GRP1_PERIPH_GPIOH : stm32wbxx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_AES2 : stm32wbxx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_ALL : stm32wbxx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_FLASH : stm32wbxx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_HSEM : stm32wbxx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_IPCC : stm32wbxx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_PKA : stm32wbxx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_QUADSPI : stm32wbxx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_RNG : stm32wbxx_ll_bus.h
  • LL_AHB3_GRP1_PERIPH_SRAM2 : stm32wbxx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_ALL : stm32wbxx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_CRS : stm32wbxx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_I2C1 : stm32wbxx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_I2C3 : stm32wbxx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_LCD : stm32wbxx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_LPTIM1 : stm32wbxx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_RTCAPB : stm32wbxx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_SPI2 : stm32wbxx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM2 : stm32wbxx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USB : stm32wbxx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_WWDG : stm32wbxx_ll_bus.h
  • LL_APB1_GRP2_PERIPH_ALL : stm32wbxx_ll_bus.h
  • LL_APB1_GRP2_PERIPH_LPTIM2 : stm32wbxx_ll_bus.h
  • LL_APB1_GRP2_PERIPH_LPUART1 : stm32wbxx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_ALL : stm32wbxx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SAI1 : stm32wbxx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SPI1 : stm32wbxx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM1 : stm32wbxx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM16 : stm32wbxx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM17 : stm32wbxx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_USART1 : stm32wbxx_ll_bus.h
  • LL_APB3_GRP1_PERIPH_ALL : stm32wbxx_ll_bus.h
  • LL_APB3_GRP1_PERIPH_RF : stm32wbxx_ll_bus.h
  • LL_C2_AHB1_GRP1_PERIPH_CRC : stm32wbxx_ll_bus.h
  • LL_C2_AHB1_GRP1_PERIPH_DMA1 : stm32wbxx_ll_bus.h
  • LL_C2_AHB1_GRP1_PERIPH_DMA2 : stm32wbxx_ll_bus.h
  • LL_C2_AHB1_GRP1_PERIPH_DMAMUX1 : stm32wbxx_ll_bus.h
  • LL_C2_AHB1_GRP1_PERIPH_SRAM1 : stm32wbxx_ll_bus.h
  • LL_C2_AHB1_GRP1_PERIPH_TSC : stm32wbxx_ll_bus.h
  • LL_C2_AHB2_GRP1_PERIPH_ADC : stm32wbxx_ll_bus.h
  • LL_C2_AHB2_GRP1_PERIPH_AES1 : stm32wbxx_ll_bus.h
  • LL_C2_AHB2_GRP1_PERIPH_GPIOA : stm32wbxx_ll_bus.h
  • LL_C2_AHB2_GRP1_PERIPH_GPIOB : stm32wbxx_ll_bus.h
  • LL_C2_AHB2_GRP1_PERIPH_GPIOC : stm32wbxx_ll_bus.h
  • LL_C2_AHB2_GRP1_PERIPH_GPIOD : stm32wbxx_ll_bus.h
  • LL_C2_AHB2_GRP1_PERIPH_GPIOE : stm32wbxx_ll_bus.h
  • LL_C2_AHB2_GRP1_PERIPH_GPIOH : stm32wbxx_ll_bus.h
  • LL_C2_AHB3_GRP1_PERIPH_AES2 : stm32wbxx_ll_bus.h
  • LL_C2_AHB3_GRP1_PERIPH_FLASH : stm32wbxx_ll_bus.h
  • LL_C2_AHB3_GRP1_PERIPH_HSEM : stm32wbxx_ll_bus.h
  • LL_C2_AHB3_GRP1_PERIPH_IPCC : stm32wbxx_ll_bus.h
  • LL_C2_AHB3_GRP1_PERIPH_PKA : stm32wbxx_ll_bus.h
  • LL_C2_AHB3_GRP1_PERIPH_RNG : stm32wbxx_ll_bus.h
  • LL_C2_AHB3_GRP1_PERIPH_SRAM2 : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP1_PERIPH_CRS : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP1_PERIPH_I2C1 : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP1_PERIPH_I2C3 : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP1_PERIPH_LCD : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP1_PERIPH_LPTIM1 : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP1_PERIPH_RTCAPB : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP1_PERIPH_SPI2 : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP1_PERIPH_TIM2 : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP1_PERIPH_USB : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP2_PERIPH_LPTIM2 : stm32wbxx_ll_bus.h
  • LL_C2_APB1_GRP2_PERIPH_LPUART1 : stm32wbxx_ll_bus.h
  • LL_C2_APB2_GRP1_PERIPH_SAI1 : stm32wbxx_ll_bus.h
  • LL_C2_APB2_GRP1_PERIPH_SPI1 : stm32wbxx_ll_bus.h
  • LL_C2_APB2_GRP1_PERIPH_TIM1 : stm32wbxx_ll_bus.h
  • LL_C2_APB2_GRP1_PERIPH_TIM16 : stm32wbxx_ll_bus.h
  • LL_C2_APB2_GRP1_PERIPH_TIM17 : stm32wbxx_ll_bus.h
  • LL_C2_APB2_GRP1_PERIPH_USART1 : stm32wbxx_ll_bus.h
  • LL_C2_APB3_GRP1_PERIPH_802 : stm32wbxx_ll_bus.h
  • LL_C2_APB3_GRP1_PERIPH_BLE : stm32wbxx_ll_bus.h
  • LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP : stm32wbxx_ll_system.h
  • LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP : stm32wbxx_ll_system.h
  • LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP : stm32wbxx_ll_system.h
  • LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP : stm32wbxx_ll_system.h
  • LL_C2_DBGMCU_APB1_GRP1_RTC_STOP : stm32wbxx_ll_system.h
  • LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP : stm32wbxx_ll_system.h
  • LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP : stm32wbxx_ll_system.h
  • LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP : stm32wbxx_ll_system.h
  • LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP : stm32wbxx_ll_system.h
  • LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_ADC : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_AES1 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_COMP : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_EXTI0 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_EXTI1 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_EXTI10 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_EXTI11 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_EXTI12 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_EXTI13 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_EXTI14 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_EXTI15 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_EXTI2 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_EXTI3 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_EXTI4 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_EXTI5 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_EXTI6 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_EXTI7 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_EXTI8 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_EXTI9 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_FLASH : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_PKA : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_RCC : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_RNG : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_RTCALARM : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP1_RTCWKUP : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_DMA1CH1 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_DMA1CH2 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_DMA1CH3 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_DMA1CH4 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_DMA1CH5 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_DMA1CH6 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_DMA1CH7 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_DMA2CH1 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_DMA2CH2 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_DMA2CH3 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_DMA2CH4 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_DMA2CH5 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_DMA2CH6 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_DMA2CH7 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_DMAMUX1 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_LCD : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_PVD : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_PVM1 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_PVM3 : stm32wbxx_ll_system.h
  • LL_C2_SYSCFG_GRP2_TSC : stm32wbxx_ll_system.h
  • LL_COMP_BLANKINGSRC_NONE : stm32wbxx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM1_OC5 : stm32wbxx_ll_comp.h
  • LL_COMP_BLANKINGSRC_TIM2_OC3 : stm32wbxx_ll_comp.h
  • LL_COMP_DELAY_STARTUP_US : stm32wbxx_ll_comp.h
  • LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US : stm32wbxx_ll_comp.h
  • LL_COMP_HYSTERESIS_HIGH : stm32wbxx_ll_comp.h
  • LL_COMP_HYSTERESIS_LOW : stm32wbxx_ll_comp.h
  • LL_COMP_HYSTERESIS_MEDIUM : stm32wbxx_ll_comp.h
  • LL_COMP_HYSTERESIS_NONE : stm32wbxx_ll_comp.h
  • LL_COMP_INPUT_MINUS_1_2VREFINT : stm32wbxx_ll_comp.h
  • LL_COMP_INPUT_MINUS_1_4VREFINT : stm32wbxx_ll_comp.h
  • LL_COMP_INPUT_MINUS_3_4VREFINT : stm32wbxx_ll_comp.h
  • LL_COMP_INPUT_MINUS_IO1 : stm32wbxx_ll_comp.h
  • LL_COMP_INPUT_MINUS_IO2 : stm32wbxx_ll_comp.h
  • LL_COMP_INPUT_MINUS_IO3 : stm32wbxx_ll_comp.h
  • LL_COMP_INPUT_MINUS_IO4 : stm32wbxx_ll_comp.h
  • LL_COMP_INPUT_MINUS_IO5 : stm32wbxx_ll_comp.h
  • LL_COMP_INPUT_MINUS_VREFINT : stm32wbxx_ll_comp.h
  • LL_COMP_INPUT_PLUS_IO1 : stm32wbxx_ll_comp.h
  • LL_COMP_INPUT_PLUS_IO2 : stm32wbxx_ll_comp.h
  • LL_COMP_INPUT_PLUS_IO3 : stm32wbxx_ll_comp.h
  • LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS : stm32wbxx_ll_comp.h
  • LL_COMP_OUTPUT_LEVEL_HIGH : stm32wbxx_ll_comp.h
  • LL_COMP_OUTPUT_LEVEL_LOW : stm32wbxx_ll_comp.h
  • LL_COMP_OUTPUTPOL_INVERTED : stm32wbxx_ll_comp.h
  • LL_COMP_OUTPUTPOL_NONINVERTED : stm32wbxx_ll_comp.h
  • LL_COMP_POWERMODE_HIGHSPEED : stm32wbxx_ll_comp.h
  • LL_COMP_POWERMODE_MEDIUMSPEED : stm32wbxx_ll_comp.h
  • LL_COMP_POWERMODE_ULTRALOWPOWER : stm32wbxx_ll_comp.h
  • LL_COMP_ReadReg : stm32wbxx_ll_comp.h
  • LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON : stm32wbxx_ll_comp.h
  • LL_COMP_WINDOWMODE_DISABLE : stm32wbxx_ll_comp.h
  • LL_COMP_WriteReg : stm32wbxx_ll_comp.h
  • LL_CRC_DEFAULT_CRC32_POLY : stm32wbxx_ll_crc.h
  • LL_CRC_DEFAULT_CRC_INITVALUE : stm32wbxx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_BYTE : stm32wbxx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_HALFWORD : stm32wbxx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_NONE : stm32wbxx_ll_crc.h
  • LL_CRC_INDATA_REVERSE_WORD : stm32wbxx_ll_crc.h
  • LL_CRC_OUTDATA_REVERSE_BIT : stm32wbxx_ll_crc.h
  • LL_CRC_OUTDATA_REVERSE_NONE : stm32wbxx_ll_crc.h
  • LL_CRC_POLYLENGTH_16B : stm32wbxx_ll_crc.h
  • LL_CRC_POLYLENGTH_32B : stm32wbxx_ll_crc.h
  • LL_CRC_POLYLENGTH_7B : stm32wbxx_ll_crc.h
  • LL_CRC_POLYLENGTH_8B : stm32wbxx_ll_crc.h
  • LL_CRC_ReadReg : stm32wbxx_ll_crc.h
  • LL_CRC_WriteReg : stm32wbxx_ll_crc.h
  • LL_CRS_CR_ERRIE : stm32wbxx_ll_crs.h
  • LL_CRS_CR_ESYNCIE : stm32wbxx_ll_crs.h
  • LL_CRS_CR_SYNCOKIE : stm32wbxx_ll_crs.h
  • LL_CRS_CR_SYNCWARNIE : stm32wbxx_ll_crs.h
  • LL_CRS_ERRORLIMIT_DEFAULT : stm32wbxx_ll_crs.h
  • LL_CRS_FREQ_ERROR_DIR_DOWN : stm32wbxx_ll_crs.h
  • LL_CRS_FREQ_ERROR_DIR_UP : stm32wbxx_ll_crs.h
  • LL_CRS_HSI48CALIBRATION_DEFAULT : stm32wbxx_ll_crs.h
  • LL_CRS_ISR_ERRF : stm32wbxx_ll_crs.h
  • LL_CRS_ISR_ESYNCF : stm32wbxx_ll_crs.h
  • LL_CRS_ISR_SYNCERR : stm32wbxx_ll_crs.h
  • LL_CRS_ISR_SYNCMISS : stm32wbxx_ll_crs.h
  • LL_CRS_ISR_SYNCOKF : stm32wbxx_ll_crs.h
  • LL_CRS_ISR_SYNCWARNF : stm32wbxx_ll_crs.h
  • LL_CRS_ISR_TRIMOVF : stm32wbxx_ll_crs.h
  • LL_CRS_ReadReg : stm32wbxx_ll_crs.h
  • LL_CRS_RELOADVALUE_DEFAULT : stm32wbxx_ll_crs.h
  • LL_CRS_SYNC_DIV_1 : stm32wbxx_ll_crs.h
  • LL_CRS_SYNC_DIV_128 : stm32wbxx_ll_crs.h
  • LL_CRS_SYNC_DIV_16 : stm32wbxx_ll_crs.h
  • LL_CRS_SYNC_DIV_2 : stm32wbxx_ll_crs.h
  • LL_CRS_SYNC_DIV_32 : stm32wbxx_ll_crs.h
  • LL_CRS_SYNC_DIV_4 : stm32wbxx_ll_crs.h
  • LL_CRS_SYNC_DIV_64 : stm32wbxx_ll_crs.h
  • LL_CRS_SYNC_DIV_8 : stm32wbxx_ll_crs.h
  • LL_CRS_SYNC_POLARITY_FALLING : stm32wbxx_ll_crs.h
  • LL_CRS_SYNC_POLARITY_RISING : stm32wbxx_ll_crs.h
  • LL_CRS_SYNC_SOURCE_GPIO : stm32wbxx_ll_crs.h
  • LL_CRS_SYNC_SOURCE_LSE : stm32wbxx_ll_crs.h
  • LL_CRS_SYNC_SOURCE_USB : stm32wbxx_ll_crs.h
  • LL_CRS_WriteReg : stm32wbxx_ll_crs.h
  • LL_DBGMCU_APB1_GRP1_I2C1_STOP : stm32wbxx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_I2C3_STOP : stm32wbxx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_IWDG_STOP : stm32wbxx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_LPTIM1_STOP : stm32wbxx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_RTC_STOP : stm32wbxx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM2_STOP : stm32wbxx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_WWDG_STOP : stm32wbxx_ll_system.h
  • LL_DBGMCU_APB1_GRP2_LPTIM2_STOP : stm32wbxx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM16_STOP : stm32wbxx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM17_STOP : stm32wbxx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM1_STOP : stm32wbxx_ll_system.h
  • LL_DMA_CCR_HTIE : stm32wbxx_ll_dma.h
  • LL_DMA_CCR_TCIE : stm32wbxx_ll_dma.h
  • LL_DMA_CCR_TEIE : stm32wbxx_ll_dma.h
  • LL_DMA_CHANNEL_1 : stm32wbxx_ll_dma.h
  • LL_DMA_CHANNEL_2 : stm32wbxx_ll_dma.h
  • LL_DMA_CHANNEL_3 : stm32wbxx_ll_dma.h
  • LL_DMA_CHANNEL_4 : stm32wbxx_ll_dma.h
  • LL_DMA_CHANNEL_5 : stm32wbxx_ll_dma.h
  • LL_DMA_CHANNEL_6 : stm32wbxx_ll_dma.h
  • LL_DMA_CHANNEL_7 : stm32wbxx_ll_dma.h
  • LL_DMA_CHANNEL_ALL : stm32wbxx_ll_dma.h
  • LL_DMA_DIRECTION_MEMORY_TO_MEMORY : stm32wbxx_ll_dma.h
  • LL_DMA_DIRECTION_MEMORY_TO_PERIPH : stm32wbxx_ll_dma.h
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CGIF1 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CGIF2 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CGIF3 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CGIF4 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CGIF5 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CGIF6 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CGIF7 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CHTIF1 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CHTIF2 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CHTIF3 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CHTIF4 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CHTIF5 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CHTIF6 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CHTIF7 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CTCIF1 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CTCIF2 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CTCIF3 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CTCIF4 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CTCIF5 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CTCIF6 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CTCIF7 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CTEIF1 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CTEIF2 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CTEIF3 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CTEIF4 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CTEIF5 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CTEIF6 : stm32wbxx_ll_dma.h
  • LL_DMA_IFCR_CTEIF7 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_GIF1 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_GIF2 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_GIF3 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_GIF4 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_GIF5 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_GIF6 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_GIF7 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_HTIF1 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_HTIF2 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_HTIF3 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_HTIF4 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_HTIF5 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_HTIF6 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_HTIF7 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_TCIF1 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_TCIF2 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_TCIF3 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_TCIF4 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_TCIF5 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_TCIF6 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_TCIF7 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_TEIF1 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_TEIF2 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_TEIF3 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_TEIF4 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_TEIF5 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_TEIF6 : stm32wbxx_ll_dma.h
  • LL_DMA_ISR_TEIF7 : stm32wbxx_ll_dma.h
  • LL_DMA_MDATAALIGN_BYTE : stm32wbxx_ll_dma.h
  • LL_DMA_MDATAALIGN_HALFWORD : stm32wbxx_ll_dma.h
  • LL_DMA_MDATAALIGN_WORD : stm32wbxx_ll_dma.h
  • LL_DMA_MEMORY_INCREMENT : stm32wbxx_ll_dma.h
  • LL_DMA_MEMORY_NOINCREMENT : stm32wbxx_ll_dma.h
  • LL_DMA_MODE_CIRCULAR : stm32wbxx_ll_dma.h
  • LL_DMA_MODE_NORMAL : stm32wbxx_ll_dma.h
  • LL_DMA_PDATAALIGN_BYTE : stm32wbxx_ll_dma.h
  • LL_DMA_PDATAALIGN_HALFWORD : stm32wbxx_ll_dma.h
  • LL_DMA_PDATAALIGN_WORD : stm32wbxx_ll_dma.h
  • LL_DMA_PERIPH_INCREMENT : stm32wbxx_ll_dma.h
  • LL_DMA_PERIPH_NOINCREMENT : stm32wbxx_ll_dma.h
  • LL_DMA_PRIORITY_HIGH : stm32wbxx_ll_dma.h
  • LL_DMA_PRIORITY_LOW : stm32wbxx_ll_dma.h
  • LL_DMA_PRIORITY_MEDIUM : stm32wbxx_ll_dma.h
  • LL_DMA_PRIORITY_VERYHIGH : stm32wbxx_ll_dma.h
  • LL_DMA_ReadReg : stm32wbxx_ll_dma.h
  • LL_DMA_WriteReg : stm32wbxx_ll_dma.h
  • LL_DMAMUX_CCR_SOIE : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF0 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF1 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF10 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF11 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF12 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF13 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF2 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF3 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF4 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF5 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF6 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF7 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF8 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CFR_CSOF9 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_0 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_1 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_10 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_11 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_12 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_13 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_2 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_3 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_4 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_5 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_6 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_7 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_8 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CHANNEL_9 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF0 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF1 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF10 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF11 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF12 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF13 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF2 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF3 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF4 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF5 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF6 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF7 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF8 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_CSR_SOF9 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_ReadReg : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_ADC1 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_AES1_IN : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_AES1_OUT : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_AES2_IN : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_AES2_OUT : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_0 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_1 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_2 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_3 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH0 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_DMAMUX_CH1 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE0 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE1 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE10 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE11 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE12 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE13 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE14 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE15 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE2 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE3 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE4 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE5 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE6 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE7 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE8 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_EXTI_LINE9 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_LPTIM1_OUT : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_LPTIM2_OUT : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_NO_EVENT : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_POL_FALLING : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_POL_RISING : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GEN_POL_RISING_FALLING : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GENERATOR0 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GENERATOR1 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GENERATOR2 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_GENERATOR3 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_I2C1_RX : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_I2C1_TX : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_I2C3_RX : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_I2C3_TX : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_LPUART1_RX : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_LPUART1_TX : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_MEM2MEM : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_QUADSPI : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_SAI1_A : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_SAI1_B : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_SPI1_RX : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_SPI1_TX : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_SPI2_RX : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_SPI2_TX : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM16_CH1 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM16_UP : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM17_CH1 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM17_UP : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_CH1 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_CH2 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_CH3 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_CH4 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_COM : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_TRIG : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM1_UP : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM2_CH1 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM2_CH2 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM2_CH3 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM2_CH4 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_TIM2_UP : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART1_RX : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_REQ_USART1_TX : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF0 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF1 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF2 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_RGCFR_RGCOF3 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_RGCR_RGOIE : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF0 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF1 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF2 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_RGSR_RGOF3 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_DMAMUX_CH0 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_DMAMUX_CH1 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE0 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE1 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE10 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE11 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE12 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE13 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE14 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE15 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE2 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE3 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE4 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE5 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE6 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE7 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE8 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_EXTI_LINE9 : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_LPTIM1_OUT : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_LPTIM2_OUT : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_NO_EVENT : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_POL_FALLING : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_POL_RISING : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_SYNC_POL_RISING_FALLING : stm32wbxx_ll_dmamux.h
  • LL_DMAMUX_WriteReg : stm32wbxx_ll_dmamux.h
  • LL_EXTI_LINE_0 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_1 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_10 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_11 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_12 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_13 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_14 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_15 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_16 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_17 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_18 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_19 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_2 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_20 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_21 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_22 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_23 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_24 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_25 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_28 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_29 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_3 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_30 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_31 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_33 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_36 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_37 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_38 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_39 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_4 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_40 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_41 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_42 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_43 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_44 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_45 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_46 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_48 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_5 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_6 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_7 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_8 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_9 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_ALL : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_ALL_0_31 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_ALL_32_63 : stm32wbxx_ll_exti.h
  • LL_EXTI_LINE_NONE : stm32wbxx_ll_exti.h
  • LL_EXTI_MODE_EVENT : stm32wbxx_ll_exti.h
  • LL_EXTI_MODE_IT : stm32wbxx_ll_exti.h
  • LL_EXTI_MODE_IT_EVENT : stm32wbxx_ll_exti.h
  • LL_EXTI_ReadReg : stm32wbxx_ll_exti.h
  • LL_EXTI_TRIGGER_FALLING : stm32wbxx_ll_exti.h
  • LL_EXTI_TRIGGER_NONE : stm32wbxx_ll_exti.h
  • LL_EXTI_TRIGGER_RISING : stm32wbxx_ll_exti.h
  • LL_EXTI_TRIGGER_RISING_FALLING : stm32wbxx_ll_exti.h
  • LL_EXTI_WriteReg : stm32wbxx_ll_exti.h
  • LL_FLASH_LATENCY_0 : stm32wbxx_ll_system.h
  • LL_FLASH_LATENCY_1 : stm32wbxx_ll_system.h
  • LL_FLASH_LATENCY_2 : stm32wbxx_ll_system.h
  • LL_FLASH_LATENCY_3 : stm32wbxx_ll_system.h
  • LL_GPIO_AF_0 : stm32wbxx_ll_gpio.h
  • LL_GPIO_AF_1 : stm32wbxx_ll_gpio.h
  • LL_GPIO_AF_10 : stm32wbxx_ll_gpio.h
  • LL_GPIO_AF_11 : stm32wbxx_ll_gpio.h
  • LL_GPIO_AF_12 : stm32wbxx_ll_gpio.h
  • LL_GPIO_AF_13 : stm32wbxx_ll_gpio.h
  • LL_GPIO_AF_14 : stm32wbxx_ll_gpio.h
  • LL_GPIO_AF_15 : stm32wbxx_ll_gpio.h
  • LL_GPIO_AF_2 : stm32wbxx_ll_gpio.h
  • LL_GPIO_AF_3 : stm32wbxx_ll_gpio.h
  • LL_GPIO_AF_4 : stm32wbxx_ll_gpio.h
  • LL_GPIO_AF_5 : stm32wbxx_ll_gpio.h
  • LL_GPIO_AF_6 : stm32wbxx_ll_gpio.h
  • LL_GPIO_AF_7 : stm32wbxx_ll_gpio.h
  • LL_GPIO_AF_8 : stm32wbxx_ll_gpio.h
  • LL_GPIO_AF_9 : stm32wbxx_ll_gpio.h
  • LL_GPIO_MODE_ALTERNATE : stm32wbxx_ll_gpio.h
  • LL_GPIO_MODE_ANALOG : stm32wbxx_ll_gpio.h
  • LL_GPIO_MODE_INPUT : stm32wbxx_ll_gpio.h
  • LL_GPIO_MODE_OUTPUT : stm32wbxx_ll_gpio.h
  • LL_GPIO_OUTPUT_OPENDRAIN : stm32wbxx_ll_gpio.h
  • LL_GPIO_OUTPUT_PUSHPULL : stm32wbxx_ll_gpio.h
  • LL_GPIO_PIN_0 : stm32wbxx_ll_gpio.h
  • LL_GPIO_PIN_1 : stm32wbxx_ll_gpio.h
  • LL_GPIO_PIN_10 : stm32wbxx_ll_gpio.h
  • LL_GPIO_PIN_11 : stm32wbxx_ll_gpio.h
  • LL_GPIO_PIN_12 : stm32wbxx_ll_gpio.h
  • LL_GPIO_PIN_13 : stm32wbxx_ll_gpio.h
  • LL_GPIO_PIN_14 : stm32wbxx_ll_gpio.h
  • LL_GPIO_PIN_15 : stm32wbxx_ll_gpio.h
  • LL_GPIO_PIN_2 : stm32wbxx_ll_gpio.h
  • LL_GPIO_PIN_3 : stm32wbxx_ll_gpio.h
  • LL_GPIO_PIN_4 : stm32wbxx_ll_gpio.h
  • LL_GPIO_PIN_5 : stm32wbxx_ll_gpio.h
  • LL_GPIO_PIN_6 : stm32wbxx_ll_gpio.h
  • LL_GPIO_PIN_7 : stm32wbxx_ll_gpio.h
  • LL_GPIO_PIN_8 : stm32wbxx_ll_gpio.h
  • LL_GPIO_PIN_9 : stm32wbxx_ll_gpio.h
  • LL_GPIO_PIN_ALL : stm32wbxx_ll_gpio.h
  • LL_GPIO_PULL_DOWN : stm32wbxx_ll_gpio.h
  • LL_GPIO_PULL_NO : stm32wbxx_ll_gpio.h
  • LL_GPIO_PULL_UP : stm32wbxx_ll_gpio.h
  • LL_GPIO_ReadReg : stm32wbxx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_HIGH : stm32wbxx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_LOW : stm32wbxx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_MEDIUM : stm32wbxx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_VERY_HIGH : stm32wbxx_ll_gpio.h
  • LL_GPIO_WriteReg : stm32wbxx_ll_gpio.h
  • LL_HANDLER_FAULT_BUS : stm32wbxx_ll_cortex.h
  • LL_HANDLER_FAULT_MEM : stm32wbxx_ll_cortex.h
  • LL_HANDLER_FAULT_USG : stm32wbxx_ll_cortex.h
  • LL_HSEM_COREID : stm32wbxx_ll_hsem.h
  • LL_HSEM_COREID_CPU1 : stm32wbxx_ll_hsem.h
  • LL_HSEM_COREID_CPU2 : stm32wbxx_ll_hsem.h
  • LL_HSEM_COREID_NONE : stm32wbxx_ll_hsem.h
  • LL_HSEM_ReadReg : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_0 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_1 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_10 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_11 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_12 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_13 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_14 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_15 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_16 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_17 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_18 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_19 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_2 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_20 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_21 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_22 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_23 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_24 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_25 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_26 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_27 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_28 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_29 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_3 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_30 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_31 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_4 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_5 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_6 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_7 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_8 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_9 : stm32wbxx_ll_hsem.h
  • LL_HSEM_SEMAPHORE_ALL : stm32wbxx_ll_hsem.h
  • LL_HSEM_WriteReg : stm32wbxx_ll_hsem.h
  • LL_I2C_ACK : stm32wbxx_ll_i2c.h
  • LL_I2C_ADDRESSING_MODE_10BIT : stm32wbxx_ll_i2c.h
  • LL_I2C_ADDRESSING_MODE_7BIT : stm32wbxx_ll_i2c.h
  • LL_I2C_ADDRSLAVE_10BIT : stm32wbxx_ll_i2c.h
  • LL_I2C_ADDRSLAVE_7BIT : stm32wbxx_ll_i2c.h
  • LL_I2C_ANALOGFILTER_DISABLE : stm32wbxx_ll_i2c.h
  • LL_I2C_ANALOGFILTER_ENABLE : stm32wbxx_ll_i2c.h
  • LL_I2C_CR1_ADDRIE : stm32wbxx_ll_i2c.h
  • LL_I2C_CR1_ERRIE : stm32wbxx_ll_i2c.h
  • LL_I2C_CR1_NACKIE : stm32wbxx_ll_i2c.h
  • LL_I2C_CR1_RXIE : stm32wbxx_ll_i2c.h
  • LL_I2C_CR1_STOPIE : stm32wbxx_ll_i2c.h
  • LL_I2C_CR1_TCIE : stm32wbxx_ll_i2c.h
  • LL_I2C_CR1_TXIE : stm32wbxx_ll_i2c.h
  • LL_I2C_DIRECTION_READ : stm32wbxx_ll_i2c.h
  • LL_I2C_DIRECTION_WRITE : stm32wbxx_ll_i2c.h
  • LL_I2C_DMA_REG_DATA_RECEIVE : stm32wbxx_ll_i2c.h
  • LL_I2C_DMA_REG_DATA_TRANSMIT : stm32wbxx_ll_i2c.h
  • LL_I2C_GENERATE_NOSTARTSTOP : stm32wbxx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_10BIT_READ : stm32wbxx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_10BIT_WRITE : stm32wbxx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_7BIT_READ : stm32wbxx_ll_i2c.h
  • LL_I2C_GENERATE_RESTART_7BIT_WRITE : stm32wbxx_ll_i2c.h
  • LL_I2C_GENERATE_START_READ : stm32wbxx_ll_i2c.h
  • LL_I2C_GENERATE_START_WRITE : stm32wbxx_ll_i2c.h
  • LL_I2C_GENERATE_STOP : stm32wbxx_ll_i2c.h
  • LL_I2C_ICR_ADDRCF : stm32wbxx_ll_i2c.h
  • LL_I2C_ICR_ALERTCF : stm32wbxx_ll_i2c.h
  • LL_I2C_ICR_ARLOCF : stm32wbxx_ll_i2c.h
  • LL_I2C_ICR_BERRCF : stm32wbxx_ll_i2c.h
  • LL_I2C_ICR_NACKCF : stm32wbxx_ll_i2c.h
  • LL_I2C_ICR_OVRCF : stm32wbxx_ll_i2c.h
  • LL_I2C_ICR_PECCF : stm32wbxx_ll_i2c.h
  • LL_I2C_ICR_STOPCF : stm32wbxx_ll_i2c.h
  • LL_I2C_ICR_TIMOUTCF : stm32wbxx_ll_i2c.h
  • LL_I2C_ISR_ADDR : stm32wbxx_ll_i2c.h
  • LL_I2C_ISR_ALERT : stm32wbxx_ll_i2c.h
  • LL_I2C_ISR_ARLO : stm32wbxx_ll_i2c.h
  • LL_I2C_ISR_BERR : stm32wbxx_ll_i2c.h
  • LL_I2C_ISR_BUSY : stm32wbxx_ll_i2c.h
  • LL_I2C_ISR_NACKF : stm32wbxx_ll_i2c.h
  • LL_I2C_ISR_OVR : stm32wbxx_ll_i2c.h
  • LL_I2C_ISR_PECERR : stm32wbxx_ll_i2c.h
  • LL_I2C_ISR_RXNE : stm32wbxx_ll_i2c.h
  • LL_I2C_ISR_STOPF : stm32wbxx_ll_i2c.h
  • LL_I2C_ISR_TC : stm32wbxx_ll_i2c.h
  • LL_I2C_ISR_TCR : stm32wbxx_ll_i2c.h
  • LL_I2C_ISR_TIMEOUT : stm32wbxx_ll_i2c.h
  • LL_I2C_ISR_TXE : stm32wbxx_ll_i2c.h
  • LL_I2C_ISR_TXIS : stm32wbxx_ll_i2c.h
  • LL_I2C_MODE_AUTOEND : stm32wbxx_ll_i2c.h
  • LL_I2C_MODE_I2C : stm32wbxx_ll_i2c.h
  • LL_I2C_MODE_RELOAD : stm32wbxx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC : stm32wbxx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC : stm32wbxx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_DEVICE : stm32wbxx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_DEVICE_ARP : stm32wbxx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_HOST : stm32wbxx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_RELOAD : stm32wbxx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC : stm32wbxx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC : stm32wbxx_ll_i2c.h
  • LL_I2C_MODE_SOFTEND : stm32wbxx_ll_i2c.h
  • LL_I2C_NACK : stm32wbxx_ll_i2c.h
  • LL_I2C_OWNADDRESS1_10BIT : stm32wbxx_ll_i2c.h
  • LL_I2C_OWNADDRESS1_7BIT : stm32wbxx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK01 : stm32wbxx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK02 : stm32wbxx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK03 : stm32wbxx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK04 : stm32wbxx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK05 : stm32wbxx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK06 : stm32wbxx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_MASK07 : stm32wbxx_ll_i2c.h
  • LL_I2C_OWNADDRESS2_NOMASK : stm32wbxx_ll_i2c.h
  • LL_I2C_ReadReg : stm32wbxx_ll_i2c.h
  • LL_I2C_REQUEST_READ : stm32wbxx_ll_i2c.h
  • LL_I2C_REQUEST_WRITE : stm32wbxx_ll_i2c.h
  • LL_I2C_SMBUS_ALL_TIMEOUT : stm32wbxx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTA : stm32wbxx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW : stm32wbxx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH : stm32wbxx_ll_i2c.h
  • LL_I2C_SMBUS_TIMEOUTB : stm32wbxx_ll_i2c.h
  • LL_I2C_WriteReg : stm32wbxx_ll_i2c.h
  • LL_IPCC_C1TOC2SR_CH1F : stm32wbxx_ll_ipcc.h
  • LL_IPCC_C1TOC2SR_CH2F : stm32wbxx_ll_ipcc.h
  • LL_IPCC_C1TOC2SR_CH3F : stm32wbxx_ll_ipcc.h
  • LL_IPCC_C1TOC2SR_CH4F : stm32wbxx_ll_ipcc.h
  • LL_IPCC_C1TOC2SR_CH5F : stm32wbxx_ll_ipcc.h
  • LL_IPCC_C1TOC2SR_CH6F : stm32wbxx_ll_ipcc.h
  • LL_IPCC_C2TOC1SR_CH1F : stm32wbxx_ll_ipcc.h
  • LL_IPCC_C2TOC1SR_CH2F : stm32wbxx_ll_ipcc.h
  • LL_IPCC_C2TOC1SR_CH3F : stm32wbxx_ll_ipcc.h
  • LL_IPCC_C2TOC1SR_CH4F : stm32wbxx_ll_ipcc.h
  • LL_IPCC_C2TOC1SR_CH5F : stm32wbxx_ll_ipcc.h
  • LL_IPCC_C2TOC1SR_CH6F : stm32wbxx_ll_ipcc.h
  • LL_IPCC_CHANNEL_1 : stm32wbxx_ll_ipcc.h
  • LL_IPCC_CHANNEL_2 : stm32wbxx_ll_ipcc.h
  • LL_IPCC_CHANNEL_3 : stm32wbxx_ll_ipcc.h
  • LL_IPCC_CHANNEL_4 : stm32wbxx_ll_ipcc.h
  • LL_IPCC_CHANNEL_5 : stm32wbxx_ll_ipcc.h
  • LL_IPCC_CHANNEL_6 : stm32wbxx_ll_ipcc.h
  • LL_IPCC_ReadReg : stm32wbxx_ll_ipcc.h
  • LL_IPCC_WriteReg : stm32wbxx_ll_ipcc.h
  • LL_IWDG_KEY_ENABLE : stm32wbxx_ll_iwdg.h
  • LL_IWDG_KEY_RELOAD : stm32wbxx_ll_iwdg.h
  • LL_IWDG_KEY_WR_ACCESS_DISABLE : stm32wbxx_ll_iwdg.h
  • LL_IWDG_KEY_WR_ACCESS_ENABLE : stm32wbxx_ll_iwdg.h
  • LL_IWDG_PRESCALER_128 : stm32wbxx_ll_iwdg.h
  • LL_IWDG_PRESCALER_16 : stm32wbxx_ll_iwdg.h
  • LL_IWDG_PRESCALER_256 : stm32wbxx_ll_iwdg.h
  • LL_IWDG_PRESCALER_32 : stm32wbxx_ll_iwdg.h
  • LL_IWDG_PRESCALER_4 : stm32wbxx_ll_iwdg.h
  • LL_IWDG_PRESCALER_64 : stm32wbxx_ll_iwdg.h
  • LL_IWDG_PRESCALER_8 : stm32wbxx_ll_iwdg.h
  • LL_IWDG_ReadReg : stm32wbxx_ll_iwdg.h
  • LL_IWDG_SR_PVU : stm32wbxx_ll_iwdg.h
  • LL_IWDG_SR_RVU : stm32wbxx_ll_iwdg.h
  • LL_IWDG_SR_WVU : stm32wbxx_ll_iwdg.h
  • LL_IWDG_WriteReg : stm32wbxx_ll_iwdg.h
  • LL_LPTIM_CLK_FILTER_2 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_CLK_FILTER_4 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_CLK_FILTER_8 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_CLK_FILTER_NONE : stm32wbxx_ll_lptim.h
  • LL_LPTIM_CLK_POLARITY_FALLING : stm32wbxx_ll_lptim.h
  • LL_LPTIM_CLK_POLARITY_RISING : stm32wbxx_ll_lptim.h
  • LL_LPTIM_CLK_POLARITY_RISING_FALLING : stm32wbxx_ll_lptim.h
  • LL_LPTIM_CLK_SOURCE_EXTERNAL : stm32wbxx_ll_lptim.h
  • LL_LPTIM_CLK_SOURCE_INTERNAL : stm32wbxx_ll_lptim.h
  • LL_LPTIM_COUNTER_MODE_EXTERNAL : stm32wbxx_ll_lptim.h
  • LL_LPTIM_COUNTER_MODE_INTERNAL : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ENCODER_MODE_FALLING : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ENCODER_MODE_RISING : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ENCODER_MODE_RISING_FALLING : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IER_ARRMIE : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IER_ARROKIE : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IER_CMPMIE : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IER_CMPOKIE : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IER_DOWNIE : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IER_EXTTRIGIE : stm32wbxx_ll_lptim.h
  • LL_LPTIM_IER_UPIE : stm32wbxx_ll_lptim.h
  • LL_LPTIM_INPUT1_SRC_COMP1 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_INPUT1_SRC_COMP1_COMP2 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_INPUT1_SRC_COMP2 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_INPUT1_SRC_GPIO : stm32wbxx_ll_lptim.h
  • LL_LPTIM_INPUT2_SRC_COMP2 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_INPUT2_SRC_GPIO : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ISR_ARRM : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ISR_ARROK : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ISR_CMPM : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ISR_CMPOK : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ISR_DOWN : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ISR_EXTTRIG : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ISR_UP : stm32wbxx_ll_lptim.h
  • LL_LPTIM_OPERATING_MODE_CONTINUOUS : stm32wbxx_ll_lptim.h
  • LL_LPTIM_OPERATING_MODE_ONESHOT : stm32wbxx_ll_lptim.h
  • LL_LPTIM_OUTPUT_POLARITY_INVERSE : stm32wbxx_ll_lptim.h
  • LL_LPTIM_OUTPUT_POLARITY_REGULAR : stm32wbxx_ll_lptim.h
  • LL_LPTIM_OUTPUT_WAVEFORM_PWM : stm32wbxx_ll_lptim.h
  • LL_LPTIM_OUTPUT_WAVEFORM_SETONCE : stm32wbxx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV1 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV128 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV16 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV2 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV32 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV4 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV64 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_PRESCALER_DIV8 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_ReadReg : stm32wbxx_ll_lptim.h
  • LL_LPTIM_TRIG_FILTER_2 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_TRIG_FILTER_4 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_TRIG_FILTER_8 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_TRIG_FILTER_NONE : stm32wbxx_ll_lptim.h
  • LL_LPTIM_TRIG_POLARITY_FALLING : stm32wbxx_ll_lptim.h
  • LL_LPTIM_TRIG_POLARITY_RISING : stm32wbxx_ll_lptim.h
  • LL_LPTIM_TRIG_POLARITY_RISING_FALLING : stm32wbxx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_COMP1 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_COMP2 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_GPIO : stm32wbxx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCALARMA : stm32wbxx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCALARMB : stm32wbxx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP1 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP2 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_TRIG_SOURCE_RTCTAMP3 : stm32wbxx_ll_lptim.h
  • LL_LPTIM_UPDATE_MODE_ENDOFPERIOD : stm32wbxx_ll_lptim.h
  • LL_LPTIM_UPDATE_MODE_IMMEDIATE : stm32wbxx_ll_lptim.h
  • LL_LPTIM_WriteReg : stm32wbxx_ll_lptim.h
  • LL_LPUART_ADDRESS_DETECT_4B : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ADDRESS_DETECT_7B : stm32wbxx_ll_lpuart.h
  • LL_LPUART_BINARY_LOGIC_NEGATIVE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_BINARY_LOGIC_POSITIVE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_BITORDER_LSBFIRST : stm32wbxx_ll_lpuart.h
  • LL_LPUART_BITORDER_MSBFIRST : stm32wbxx_ll_lpuart.h
  • LL_LPUART_CR1_CMIE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_CR1_IDLEIE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_CR1_PEIE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_CR1_RXFFIE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_CR1_RXNEIE_RXFNEIE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_CR1_TCIE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_CR1_TXEIE_TXFNFIE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_CR1_TXFEIE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_CR3_CTSIE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_CR3_EIE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_CR3_RXFTIE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_CR3_TXFTIE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_CR3_WUFIE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DATAWIDTH_7B : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DATAWIDTH_8B : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DATAWIDTH_9B : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DE_POLARITY_HIGH : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DE_POLARITY_LOW : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DIRECTION_NONE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DIRECTION_RX : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DIRECTION_TX : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DIRECTION_TX_RX : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableIT_RXNE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DisableIT_TXE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DMA_REG_DATA_RECEIVE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_DMA_REG_DATA_TRANSMIT : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableIT_RXNE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_EnableIT_TXE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_1_2 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_1_4 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_1_8 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_3_4 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_7_8 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_FIFOTHRESHOLD_8_8 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_CTS : stm32wbxx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_NONE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_RTS : stm32wbxx_ll_lpuart.h
  • LL_LPUART_HWCONTROL_RTS_CTS : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ICR_CMCF : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ICR_CTSCF : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ICR_FECF : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ICR_IDLECF : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ICR_NCF : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ICR_ORECF : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ICR_PECF : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ICR_TCCF : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ICR_TXFECF : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ICR_WUCF : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_RXNE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsActiveFlag_TXE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_RXNE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_IsEnabledIT_TXE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_BUSY : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_CMF : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_CTS : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_CTSIF : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_FE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_IDLE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_NE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_ORE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_PE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_REACK : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_RWU : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_RXFF : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_RXFT : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_RXNE_RXFNE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_SBKF : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_TC : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_TEACK : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_TXE_TXFNF : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_TXFE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_TXFT : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ISR_WUF : stm32wbxx_ll_lpuart.h
  • LL_LPUART_PARITY_EVEN : stm32wbxx_ll_lpuart.h
  • LL_LPUART_PARITY_NONE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_PARITY_ODD : stm32wbxx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV1 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV10 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV12 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV128 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV16 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV2 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV256 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV32 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV4 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV6 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV64 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_PRESCALER_DIV8 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_ReadReg : stm32wbxx_ll_lpuart.h
  • LL_LPUART_RXPIN_LEVEL_INVERTED : stm32wbxx_ll_lpuart.h
  • LL_LPUART_RXPIN_LEVEL_STANDARD : stm32wbxx_ll_lpuart.h
  • LL_LPUART_STOPBITS_1 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_STOPBITS_2 : stm32wbxx_ll_lpuart.h
  • LL_LPUART_TXPIN_LEVEL_INVERTED : stm32wbxx_ll_lpuart.h
  • LL_LPUART_TXPIN_LEVEL_STANDARD : stm32wbxx_ll_lpuart.h
  • LL_LPUART_TXRX_STANDARD : stm32wbxx_ll_lpuart.h
  • LL_LPUART_TXRX_SWAPPED : stm32wbxx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ADDRESSMARK : stm32wbxx_ll_lpuart.h
  • LL_LPUART_WAKEUP_IDLELINE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ON_ADDRESS : stm32wbxx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ON_RXNE : stm32wbxx_ll_lpuart.h
  • LL_LPUART_WAKEUP_ON_STARTBIT : stm32wbxx_ll_lpuart.h
  • LL_LPUART_WriteReg : stm32wbxx_ll_lpuart.h
  • LL_MAX_DELAY : stm32wbxx_ll_utils.h
  • LL_MPU_ACCESS_BUFFERABLE : stm32wbxx_ll_cortex.h
  • LL_MPU_ACCESS_CACHEABLE : stm32wbxx_ll_cortex.h
  • LL_MPU_ACCESS_NOT_BUFFERABLE : stm32wbxx_ll_cortex.h
  • LL_MPU_ACCESS_NOT_CACHEABLE : stm32wbxx_ll_cortex.h
  • LL_MPU_ACCESS_NOT_SHAREABLE : stm32wbxx_ll_cortex.h
  • LL_MPU_ACCESS_SHAREABLE : stm32wbxx_ll_cortex.h
  • LL_MPU_CTRL_HARDFAULT_NMI : stm32wbxx_ll_cortex.h
  • LL_MPU_CTRL_HFNMI_PRIVDEF : stm32wbxx_ll_cortex.h
  • LL_MPU_CTRL_HFNMI_PRIVDEF_NONE : stm32wbxx_ll_cortex.h
  • LL_MPU_CTRL_PRIVILEGED_DEFAULT : stm32wbxx_ll_cortex.h
  • LL_MPU_INSTRUCTION_ACCESS_DISABLE : stm32wbxx_ll_cortex.h
  • LL_MPU_INSTRUCTION_ACCESS_ENABLE : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_FULL_ACCESS : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_NO_ACCESS : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_NUMBER0 : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_NUMBER1 : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_NUMBER2 : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_NUMBER3 : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_NUMBER4 : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_NUMBER5 : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_NUMBER6 : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_NUMBER7 : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RO : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RO_URO : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RW : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_PRIV_RW_URO : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_128B : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_128KB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_128MB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_16KB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_16MB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_1GB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_1KB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_1MB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_256B : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_256KB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_256MB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_2GB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_2KB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_2MB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_32B : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_32KB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_32MB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_4GB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_4KB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_4MB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_512B : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_512KB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_512MB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_64B : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_64KB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_64MB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_8KB : stm32wbxx_ll_cortex.h
  • LL_MPU_REGION_SIZE_8MB : stm32wbxx_ll_cortex.h
  • LL_MPU_TEX_LEVEL0 : stm32wbxx_ll_cortex.h
  • LL_MPU_TEX_LEVEL1 : stm32wbxx_ll_cortex.h
  • LL_MPU_TEX_LEVEL2 : stm32wbxx_ll_cortex.h
  • LL_MPU_TEX_LEVEL4 : stm32wbxx_ll_cortex.h
  • LL_PKA_CLRFR_ADDRERRFC : stm32wbxx_ll_pka.h
  • LL_PKA_CLRFR_PROCENDFC : stm32wbxx_ll_pka.h
  • LL_PKA_CLRFR_RAMERRFC : stm32wbxx_ll_pka.h
  • LL_PKA_CR_ADDRERRIE : stm32wbxx_ll_pka.h
  • LL_PKA_CR_PROCENDIE : stm32wbxx_ll_pka.h
  • LL_PKA_CR_RAMERRIE : stm32wbxx_ll_pka.h
  • LL_PKA_MODE_ARITHMETIC_ADD : stm32wbxx_ll_pka.h
  • LL_PKA_MODE_ARITHMETIC_MUL : stm32wbxx_ll_pka.h
  • LL_PKA_MODE_ARITHMETIC_SUB : stm32wbxx_ll_pka.h
  • LL_PKA_MODE_COMPARISON : stm32wbxx_ll_pka.h
  • LL_PKA_MODE_ECC_KP_PRIMITIVE : stm32wbxx_ll_pka.h
  • LL_PKA_MODE_ECDSA_SIGNATURE : stm32wbxx_ll_pka.h
  • LL_PKA_MODE_ECDSA_VERIFICATION : stm32wbxx_ll_pka.h
  • LL_PKA_MODE_MODULAR_ADD : stm32wbxx_ll_pka.h
  • LL_PKA_MODE_MODULAR_EXP : stm32wbxx_ll_pka.h
  • LL_PKA_MODE_MODULAR_INV : stm32wbxx_ll_pka.h
  • LL_PKA_MODE_MODULAR_REDUC : stm32wbxx_ll_pka.h
  • LL_PKA_MODE_MODULAR_SUB : stm32wbxx_ll_pka.h
  • LL_PKA_MODE_MONTGOMERY_MUL : stm32wbxx_ll_pka.h
  • LL_PKA_MODE_MONTGOMERY_PARAM : stm32wbxx_ll_pka.h
  • LL_PKA_MODE_MONTGOMERY_PARAM_ECC : stm32wbxx_ll_pka.h
  • LL_PKA_MODE_MONTGOMERY_PARAM_MOD_EXP : stm32wbxx_ll_pka.h
  • LL_PKA_MODE_POINT_CHECK : stm32wbxx_ll_pka.h
  • LL_PKA_MODE_RSA_CRT_EXP : stm32wbxx_ll_pka.h
  • LL_PKA_ReadReg : stm32wbxx_ll_pka.h
  • LL_PKA_SR_ADDRERRF : stm32wbxx_ll_pka.h
  • LL_PKA_SR_BUSY : stm32wbxx_ll_pka.h
  • LL_PKA_SR_PROCENDF : stm32wbxx_ll_pka.h
  • LL_PKA_SR_RAMERRF : stm32wbxx_ll_pka.h
  • LL_PKA_WriteReg : stm32wbxx_ll_pka.h
  • LL_PWR_BATT_CHARG_RESISTOR_5K : stm32wbxx_ll_pwr.h
  • LL_PWR_BATT_CHARGRESISTOR_1_5K : stm32wbxx_ll_pwr.h
  • LL_PWR_BOR_SMPS_FORCE_BYPASS : stm32wbxx_ll_pwr.h
  • LL_PWR_BOR_SYSTEM_RESET : stm32wbxx_ll_pwr.h
  • LL_PWR_EXTSCR_C1CSSF : stm32wbxx_ll_pwr.h
  • LL_PWR_EXTSCR_C1DS : stm32wbxx_ll_pwr.h
  • LL_PWR_EXTSCR_C1SBF : stm32wbxx_ll_pwr.h
  • LL_PWR_EXTSCR_C1STOPF : stm32wbxx_ll_pwr.h
  • LL_PWR_EXTSCR_C2CSSF : stm32wbxx_ll_pwr.h
  • LL_PWR_EXTSCR_C2DS : stm32wbxx_ll_pwr.h
  • LL_PWR_EXTSCR_C2SBF : stm32wbxx_ll_pwr.h
  • LL_PWR_EXTSCR_C2STOPF : stm32wbxx_ll_pwr.h
  • LL_PWR_EXTSCR_CCRPF : stm32wbxx_ll_pwr.h
  • LL_PWR_FLAG_802A : stm32wbxx_ll_pwr.h
  • LL_PWR_FLAG_802WU : stm32wbxx_ll_pwr.h
  • LL_PWR_FLAG_BLEA : stm32wbxx_ll_pwr.h
  • LL_PWR_FLAG_BLEWU : stm32wbxx_ll_pwr.h
  • LL_PWR_FLAG_BORH : stm32wbxx_ll_pwr.h
  • LL_PWR_FLAG_CRP : stm32wbxx_ll_pwr.h
  • LL_PWR_FLAG_CRPE : stm32wbxx_ll_pwr.h
  • LL_PWR_FLAG_SMPS : stm32wbxx_ll_pwr.h
  • LL_PWR_FLAG_SMPSB : stm32wbxx_ll_pwr.h
  • LL_PWR_FLAG_SMPSFB : stm32wbxx_ll_pwr.h
  • LL_PWR_FLASH_LPRUN_MODE_IDLE : stm32wbxx_ll_pwr.h
  • LL_PWR_FLASH_LPRUN_MODE_POWER_DOWN : stm32wbxx_ll_pwr.h
  • LL_PWR_FLASH_SLEEP_MODE_IDLE : stm32wbxx_ll_pwr.h
  • LL_PWR_FLASH_SLEEP_MODE_POWER_DOWN : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_A : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_B : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_BIT_0 : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_BIT_1 : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_BIT_10 : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_BIT_11 : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_BIT_12 : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_BIT_13 : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_BIT_14 : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_BIT_15 : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_BIT_2 : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_BIT_3 : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_BIT_4 : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_BIT_5 : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_BIT_6 : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_BIT_7 : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_BIT_8 : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_BIT_9 : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_C : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_D : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_E : stm32wbxx_ll_pwr.h
  • LL_PWR_GPIO_H : stm32wbxx_ll_pwr.h
  • LL_PWR_MODE_SHUTDOWN : stm32wbxx_ll_pwr.h
  • LL_PWR_MODE_STANDBY : stm32wbxx_ll_pwr.h
  • LL_PWR_MODE_STOP0 : stm32wbxx_ll_pwr.h
  • LL_PWR_MODE_STOP1 : stm32wbxx_ll_pwr.h
  • LL_PWR_MODE_STOP2 : stm32wbxx_ll_pwr.h
  • LL_PWR_PVDLEVEL_0 : stm32wbxx_ll_pwr.h
  • LL_PWR_PVDLEVEL_1 : stm32wbxx_ll_pwr.h
  • LL_PWR_PVDLEVEL_2 : stm32wbxx_ll_pwr.h
  • LL_PWR_PVDLEVEL_3 : stm32wbxx_ll_pwr.h
  • LL_PWR_PVDLEVEL_4 : stm32wbxx_ll_pwr.h
  • LL_PWR_PVDLEVEL_5 : stm32wbxx_ll_pwr.h
  • LL_PWR_PVDLEVEL_6 : stm32wbxx_ll_pwr.h
  • LL_PWR_PVDLEVEL_7 : stm32wbxx_ll_pwr.h
  • LL_PWR_PVM_VDDA_1_62V : stm32wbxx_ll_pwr.h
  • LL_PWR_PVM_VDDUSB_1_2V : stm32wbxx_ll_pwr.h
  • LL_PWR_ReadReg : stm32wbxx_ll_pwr.h
  • LL_PWR_REGU_VOLTAGE_SCALE1 : stm32wbxx_ll_pwr.h
  • LL_PWR_REGU_VOLTAGE_SCALE2 : stm32wbxx_ll_pwr.h
  • LL_PWR_SCR_C802AF : stm32wbxx_ll_pwr.h
  • LL_PWR_SCR_C802WUF : stm32wbxx_ll_pwr.h
  • LL_PWR_SCR_CBLEAF : stm32wbxx_ll_pwr.h
  • LL_PWR_SCR_CBLEWUF : stm32wbxx_ll_pwr.h
  • LL_PWR_SCR_CBORHF : stm32wbxx_ll_pwr.h
  • LL_PWR_SCR_CC2HF : stm32wbxx_ll_pwr.h
  • LL_PWR_SCR_CCRPEF : stm32wbxx_ll_pwr.h
  • LL_PWR_SCR_CSMPSFBF : stm32wbxx_ll_pwr.h
  • LL_PWR_SCR_CWUF : stm32wbxx_ll_pwr.h
  • LL_PWR_SCR_CWUF1 : stm32wbxx_ll_pwr.h
  • LL_PWR_SCR_CWUF2 : stm32wbxx_ll_pwr.h
  • LL_PWR_SCR_CWUF3 : stm32wbxx_ll_pwr.h
  • LL_PWR_SCR_CWUF4 : stm32wbxx_ll_pwr.h
  • LL_PWR_SCR_CWUF5 : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_BYPASS : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V20 : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V25 : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V30 : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V35 : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40 : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V45 : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V50 : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V55 : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V60 : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V65 : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V70 : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V75 : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V80 : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V85 : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_OUTPUT_VOLTAGE_1V90 : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_STARTUP_CURRENT_100MA : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_STARTUP_CURRENT_120MA : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_STARTUP_CURRENT_140MA : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_STARTUP_CURRENT_160MA : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_STARTUP_CURRENT_180MA : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_STARTUP_CURRENT_200MA : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_STARTUP_CURRENT_220MA : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_STARTUP_CURRENT_80MA : stm32wbxx_ll_pwr.h
  • LL_PWR_SMPS_STEP_DOWN : stm32wbxx_ll_pwr.h
  • LL_PWR_SR1_C2HF : stm32wbxx_ll_pwr.h
  • LL_PWR_SR1_WUF1 : stm32wbxx_ll_pwr.h
  • LL_PWR_SR1_WUF2 : stm32wbxx_ll_pwr.h
  • LL_PWR_SR1_WUF3 : stm32wbxx_ll_pwr.h
  • LL_PWR_SR1_WUF4 : stm32wbxx_ll_pwr.h
  • LL_PWR_SR1_WUF5 : stm32wbxx_ll_pwr.h
  • LL_PWR_SR1_WUFI : stm32wbxx_ll_pwr.h
  • LL_PWR_SR2_PVDO : stm32wbxx_ll_pwr.h
  • LL_PWR_SR2_PVMO1 : stm32wbxx_ll_pwr.h
  • LL_PWR_SR2_PVMO3 : stm32wbxx_ll_pwr.h
  • LL_PWR_SR2_REGLPF : stm32wbxx_ll_pwr.h
  • LL_PWR_SR2_REGLPS : stm32wbxx_ll_pwr.h
  • LL_PWR_SR2_VOSF : stm32wbxx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN1 : stm32wbxx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN2 : stm32wbxx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN3 : stm32wbxx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN4 : stm32wbxx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN5 : stm32wbxx_ll_pwr.h
  • LL_PWR_WriteReg : stm32wbxx_ll_pwr.h
  • LL_RCC_ADC_CLKSOURCE : stm32wbxx_ll_rcc.h
  • LL_RCC_ADC_CLKSOURCE_NONE : stm32wbxx_ll_rcc.h
  • LL_RCC_ADC_CLKSOURCE_PLL : stm32wbxx_ll_rcc.h
  • LL_RCC_ADC_CLKSOURCE_PLLSAI1 : stm32wbxx_ll_rcc.h
  • LL_RCC_ADC_CLKSOURCE_SYSCLK : stm32wbxx_ll_rcc.h
  • LL_RCC_APB1_DIV_1 : stm32wbxx_ll_rcc.h
  • LL_RCC_APB1_DIV_16 : stm32wbxx_ll_rcc.h
  • LL_RCC_APB1_DIV_2 : stm32wbxx_ll_rcc.h
  • LL_RCC_APB1_DIV_4 : stm32wbxx_ll_rcc.h
  • LL_RCC_APB1_DIV_8 : stm32wbxx_ll_rcc.h
  • LL_RCC_APB2_DIV_1 : stm32wbxx_ll_rcc.h
  • LL_RCC_APB2_DIV_16 : stm32wbxx_ll_rcc.h
  • LL_RCC_APB2_DIV_2 : stm32wbxx_ll_rcc.h
  • LL_RCC_APB2_DIV_4 : stm32wbxx_ll_rcc.h
  • LL_RCC_APB2_DIV_8 : stm32wbxx_ll_rcc.h
  • LL_RCC_CICR_CSSC : stm32wbxx_ll_rcc.h
  • LL_RCC_CICR_HSERDYC : stm32wbxx_ll_rcc.h
  • LL_RCC_CICR_HSI48RDYC : stm32wbxx_ll_rcc.h
  • LL_RCC_CICR_HSIRDYC : stm32wbxx_ll_rcc.h
  • LL_RCC_CICR_LSECSSC : stm32wbxx_ll_rcc.h
  • LL_RCC_CICR_LSERDYC : stm32wbxx_ll_rcc.h
  • LL_RCC_CICR_LSI1RDYC : stm32wbxx_ll_rcc.h
  • LL_RCC_CICR_LSI2RDYC : stm32wbxx_ll_rcc.h
  • LL_RCC_CICR_MSIRDYC : stm32wbxx_ll_rcc.h
  • LL_RCC_CICR_PLLRDYC : stm32wbxx_ll_rcc.h
  • LL_RCC_CICR_PLLSAI1RDYC : stm32wbxx_ll_rcc.h
  • LL_RCC_CIER_HSERDYIE : stm32wbxx_ll_rcc.h
  • LL_RCC_CIER_HSI48RDYIE : stm32wbxx_ll_rcc.h
  • LL_RCC_CIER_HSIRDYIE : stm32wbxx_ll_rcc.h
  • LL_RCC_CIER_LSECSSIE : stm32wbxx_ll_rcc.h
  • LL_RCC_CIER_LSERDYIE : stm32wbxx_ll_rcc.h
  • LL_RCC_CIER_LSI1RDYIE : stm32wbxx_ll_rcc.h
  • LL_RCC_CIER_LSI2RDYIE : stm32wbxx_ll_rcc.h
  • LL_RCC_CIER_MSIRDYIE : stm32wbxx_ll_rcc.h
  • LL_RCC_CIER_PLLRDYIE : stm32wbxx_ll_rcc.h
  • LL_RCC_CIER_PLLSAI1RDYIE : stm32wbxx_ll_rcc.h
  • LL_RCC_CIFR_CSSF : stm32wbxx_ll_rcc.h
  • LL_RCC_CIFR_HSERDYF : stm32wbxx_ll_rcc.h
  • LL_RCC_CIFR_HSI48RDYF : stm32wbxx_ll_rcc.h
  • LL_RCC_CIFR_HSIRDYF : stm32wbxx_ll_rcc.h
  • LL_RCC_CIFR_LSECSSF : stm32wbxx_ll_rcc.h
  • LL_RCC_CIFR_LSERDYF : stm32wbxx_ll_rcc.h
  • LL_RCC_CIFR_LSI1RDYF : stm32wbxx_ll_rcc.h
  • LL_RCC_CIFR_LSI2RDYF : stm32wbxx_ll_rcc.h
  • LL_RCC_CIFR_MSIRDYF : stm32wbxx_ll_rcc.h
  • LL_RCC_CIFR_PLLRDYF : stm32wbxx_ll_rcc.h
  • LL_RCC_CIFR_PLLSAI1RDYF : stm32wbxx_ll_rcc.h
  • LL_RCC_CLK48_CLKSOURCE : stm32wbxx_ll_rcc.h
  • LL_RCC_CLK48_CLKSOURCE_HSI48 : stm32wbxx_ll_rcc.h
  • LL_RCC_CLK48_CLKSOURCE_MSI : stm32wbxx_ll_rcc.h
  • LL_RCC_CLK48_CLKSOURCE_PLL : stm32wbxx_ll_rcc.h
  • LL_RCC_CLK48_CLKSOURCE_PLLSAI1 : stm32wbxx_ll_rcc.h
  • LL_RCC_CSR_BORRSTF : stm32wbxx_ll_rcc.h
  • LL_RCC_CSR_IWDGRSTF : stm32wbxx_ll_rcc.h
  • LL_RCC_CSR_LPWRRSTF : stm32wbxx_ll_rcc.h
  • LL_RCC_CSR_OBLRSTF : stm32wbxx_ll_rcc.h
  • LL_RCC_CSR_PINRSTF : stm32wbxx_ll_rcc.h
  • LL_RCC_CSR_SFTRSTF : stm32wbxx_ll_rcc.h
  • LL_RCC_CSR_WWDGRSTF : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_CURRENTMAX_0 : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_CURRENTMAX_1 : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_CURRENTMAX_2 : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_CURRENTMAX_3 : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_CURRENTMAX_4 : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_CURRENTMAX_5 : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_CURRENTMAX_6 : stm32wbxx_ll_rcc.h
  • LL_RCC_HSE_CURRENTMAX_7 : stm32wbxx_ll_rcc.h
  • LL_RCC_HSEAMPTHRESHOLD_1_2 : stm32wbxx_ll_rcc.h
  • LL_RCC_HSEAMPTHRESHOLD_3_4 : stm32wbxx_ll_rcc.h
  • LL_RCC_I2C1_CLKSOURCE : stm32wbxx_ll_rcc.h
  • LL_RCC_I2C1_CLKSOURCE_HSI : stm32wbxx_ll_rcc.h
  • LL_RCC_I2C1_CLKSOURCE_PCLK1 : stm32wbxx_ll_rcc.h
  • LL_RCC_I2C1_CLKSOURCE_SYSCLK : stm32wbxx_ll_rcc.h
  • LL_RCC_I2C3_CLKSOURCE : stm32wbxx_ll_rcc.h
  • LL_RCC_I2C3_CLKSOURCE_HSI : stm32wbxx_ll_rcc.h
  • LL_RCC_I2C3_CLKSOURCE_PCLK1 : stm32wbxx_ll_rcc.h
  • LL_RCC_I2C3_CLKSOURCE_SYSCLK : stm32wbxx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE : stm32wbxx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_HSI : stm32wbxx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_LSE : stm32wbxx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_LSI : stm32wbxx_ll_rcc.h
  • LL_RCC_LPTIM1_CLKSOURCE_PCLK1 : stm32wbxx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE : stm32wbxx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE_HSI : stm32wbxx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE_LSE : stm32wbxx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE_LSI : stm32wbxx_ll_rcc.h
  • LL_RCC_LPTIM2_CLKSOURCE_PCLK1 : stm32wbxx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE : stm32wbxx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_HSI : stm32wbxx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_LSE : stm32wbxx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_PCLK1 : stm32wbxx_ll_rcc.h
  • LL_RCC_LPUART1_CLKSOURCE_SYSCLK : stm32wbxx_ll_rcc.h
  • LL_RCC_LSCO_CLKSOURCE_LSE : stm32wbxx_ll_rcc.h
  • LL_RCC_LSCO_CLKSOURCE_LSI : stm32wbxx_ll_rcc.h
  • LL_RCC_LSEDRIVE_HIGH : stm32wbxx_ll_rcc.h
  • LL_RCC_LSEDRIVE_LOW : stm32wbxx_ll_rcc.h
  • LL_RCC_LSEDRIVE_MEDIUMHIGH : stm32wbxx_ll_rcc.h
  • LL_RCC_LSEDRIVE_MEDIUMLOW : stm32wbxx_ll_rcc.h
  • LL_RCC_MCO1_DIV_1 : stm32wbxx_ll_rcc.h
  • LL_RCC_MCO1_DIV_16 : stm32wbxx_ll_rcc.h
  • LL_RCC_MCO1_DIV_2 : stm32wbxx_ll_rcc.h
  • LL_RCC_MCO1_DIV_4 : stm32wbxx_ll_rcc.h
  • LL_RCC_MCO1_DIV_8 : stm32wbxx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_HSE : stm32wbxx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_HSE_BEFORE_STAB : stm32wbxx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_HSI : stm32wbxx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_HSI48 : stm32wbxx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_LSE : stm32wbxx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_LSI1 : stm32wbxx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_LSI2 : stm32wbxx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_MSI : stm32wbxx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_NOCLOCK : stm32wbxx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_PLLCLK : stm32wbxx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_SYSCLK : stm32wbxx_ll_rcc.h
  • LL_RCC_MSIRANGE_0 : stm32wbxx_ll_rcc.h
  • LL_RCC_MSIRANGE_1 : stm32wbxx_ll_rcc.h
  • LL_RCC_MSIRANGE_10 : stm32wbxx_ll_rcc.h
  • LL_RCC_MSIRANGE_11 : stm32wbxx_ll_rcc.h
  • LL_RCC_MSIRANGE_2 : stm32wbxx_ll_rcc.h
  • LL_RCC_MSIRANGE_3 : stm32wbxx_ll_rcc.h
  • LL_RCC_MSIRANGE_4 : stm32wbxx_ll_rcc.h
  • LL_RCC_MSIRANGE_5 : stm32wbxx_ll_rcc.h
  • LL_RCC_MSIRANGE_6 : stm32wbxx_ll_rcc.h
  • LL_RCC_MSIRANGE_7 : stm32wbxx_ll_rcc.h
  • LL_RCC_MSIRANGE_8 : stm32wbxx_ll_rcc.h
  • LL_RCC_MSIRANGE_9 : stm32wbxx_ll_rcc.h
  • LL_RCC_PERIPH_FREQUENCY_NA : stm32wbxx_ll_rcc.h
  • LL_RCC_PERIPH_FREQUENCY_NO : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLM_DIV_1 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLM_DIV_2 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLM_DIV_3 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLM_DIV_4 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLM_DIV_5 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLM_DIV_6 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLM_DIV_7 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLM_DIV_8 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_10 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_11 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_12 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_13 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_14 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_15 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_16 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_17 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_18 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_19 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_2 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_20 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_21 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_22 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_23 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_24 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_25 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_26 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_27 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_28 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_29 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_3 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_30 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_31 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_32 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_4 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_5 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_6 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_7 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_8 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLP_DIV_9 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_2 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_3 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_4 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_5 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_6 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_7 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLQ_DIV_8 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLR_DIV_2 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLR_DIV_3 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLR_DIV_4 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLR_DIV_5 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLR_DIV_6 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLR_DIV_7 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLR_DIV_8 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_10 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_11 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_12 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_13 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_14 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_15 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_16 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_17 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_18 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_19 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_2 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_20 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_21 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_22 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_23 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_24 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_25 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_26 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_27 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_28 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_29 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_3 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_30 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_31 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_32 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_4 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_5 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_6 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_7 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_8 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1P_DIV_9 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1Q_DIV_2 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1Q_DIV_3 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1Q_DIV_4 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1Q_DIV_5 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1Q_DIV_6 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1Q_DIV_7 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1Q_DIV_8 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1R_DIV_2 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1R_DIV_3 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1R_DIV_4 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1R_DIV_5 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1R_DIV_6 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1R_DIV_7 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSAI1R_DIV_8 : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSI : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSOURCE_MSI : stm32wbxx_ll_rcc.h
  • LL_RCC_PLLSOURCE_NONE : stm32wbxx_ll_rcc.h
  • LL_RCC_ReadReg : stm32wbxx_ll_rcc.h
  • LL_RCC_RF_CLKSOURCE_HSE_DIV2 : stm32wbxx_ll_rcc.h
  • LL_RCC_RF_CLKSOURCE_HSI : stm32wbxx_ll_rcc.h
  • LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024 : stm32wbxx_ll_rcc.h
  • LL_RCC_RFWKP_CLKSOURCE_LSE : stm32wbxx_ll_rcc.h
  • LL_RCC_RFWKP_CLKSOURCE_LSI : stm32wbxx_ll_rcc.h
  • LL_RCC_RFWKP_CLKSOURCE_NONE : stm32wbxx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE : stm32wbxx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE_CLK48 : stm32wbxx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE_LSE : stm32wbxx_ll_rcc.h
  • LL_RCC_RNG_CLKSOURCE_LSI : stm32wbxx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_HSE_DIV32 : stm32wbxx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_LSE : stm32wbxx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_LSI : stm32wbxx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_NONE : stm32wbxx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE : stm32wbxx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE_HSI : stm32wbxx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE_PIN : stm32wbxx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE_PLL : stm32wbxx_ll_rcc.h
  • LL_RCC_SAI1_CLKSOURCE_PLLSAI1 : stm32wbxx_ll_rcc.h
  • LL_RCC_SMPS_CLKSOURCE_HSE : stm32wbxx_ll_rcc.h
  • LL_RCC_SMPS_CLKSOURCE_HSI : stm32wbxx_ll_rcc.h
  • LL_RCC_SMPS_CLKSOURCE_MSI : stm32wbxx_ll_rcc.h
  • LL_RCC_SMPS_CLKSOURCE_STATUS_HSE : stm32wbxx_ll_rcc.h
  • LL_RCC_SMPS_CLKSOURCE_STATUS_HSI : stm32wbxx_ll_rcc.h
  • LL_RCC_SMPS_CLKSOURCE_STATUS_MSI : stm32wbxx_ll_rcc.h
  • LL_RCC_SMPS_CLKSOURCE_STATUS_NO_CLOCK : stm32wbxx_ll_rcc.h
  • LL_RCC_SMPS_DIV_0 : stm32wbxx_ll_rcc.h
  • LL_RCC_SMPS_DIV_1 : stm32wbxx_ll_rcc.h
  • LL_RCC_SMPS_DIV_2 : stm32wbxx_ll_rcc.h
  • LL_RCC_SMPS_DIV_3 : stm32wbxx_ll_rcc.h
  • LL_RCC_STOP_WAKEUPCLOCK_HSI : stm32wbxx_ll_rcc.h
  • LL_RCC_STOP_WAKEUPCLOCK_MSI : stm32wbxx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_HSE : stm32wbxx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_HSI : stm32wbxx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_MSI : stm32wbxx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_PLL : stm32wbxx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSE : stm32wbxx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSI : stm32wbxx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_MSI : stm32wbxx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_PLL : stm32wbxx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_1 : stm32wbxx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_10 : stm32wbxx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_128 : stm32wbxx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_16 : stm32wbxx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_2 : stm32wbxx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_256 : stm32wbxx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_3 : stm32wbxx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_32 : stm32wbxx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_4 : stm32wbxx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_5 : stm32wbxx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_512 : stm32wbxx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_6 : stm32wbxx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_64 : stm32wbxx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_8 : stm32wbxx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE : stm32wbxx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_HSI : stm32wbxx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_LSE : stm32wbxx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_PCLK2 : stm32wbxx_ll_rcc.h
  • LL_RCC_USART1_CLKSOURCE_SYSCLK : stm32wbxx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE : stm32wbxx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_HSI48 : stm32wbxx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_MSI : stm32wbxx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_PLL : stm32wbxx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_PLLSAI1 : stm32wbxx_ll_rcc.h
  • LL_RCC_WriteReg : stm32wbxx_ll_rcc.h
  • LL_RNG_CED_DISABLE : stm32wbxx_ll_rng.h
  • LL_RNG_CED_ENABLE : stm32wbxx_ll_rng.h
  • LL_RNG_CR_IE : stm32wbxx_ll_rng.h
  • LL_RNG_ReadReg : stm32wbxx_ll_rng.h
  • LL_RNG_SR_CECS : stm32wbxx_ll_rng.h
  • LL_RNG_SR_CEIS : stm32wbxx_ll_rng.h
  • LL_RNG_SR_DRDY : stm32wbxx_ll_rng.h
  • LL_RNG_SR_SECS : stm32wbxx_ll_rng.h
  • LL_RNG_SR_SEIS : stm32wbxx_ll_rng.h
  • LL_RNG_WriteReg : stm32wbxx_ll_rng.h
  • LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN : stm32wbxx_ll_rtc.h
  • LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL : stm32wbxx_ll_rtc.h
  • LL_RTC_ALARMOUT_ALMA : stm32wbxx_ll_rtc.h
  • LL_RTC_ALARMOUT_ALMB : stm32wbxx_ll_rtc.h
  • LL_RTC_ALARMOUT_DISABLE : stm32wbxx_ll_rtc.h
  • LL_RTC_ALARMOUT_WAKEUP : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_DATEWEEKDAYSEL_DATE : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_MASK_ALL : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_MASK_DATEWEEKDAY : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_MASK_HOURS : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_MASK_MINUTES : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_MASK_NONE : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_MASK_SECONDS : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_TIME_FORMAT_AM : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMA_TIME_FORMAT_PM : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_DATEWEEKDAYSEL_DATE : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_MASK_ALL : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_MASK_DATEWEEKDAY : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_MASK_HOURS : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_MASK_MINUTES : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_MASK_NONE : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_MASK_SECONDS : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_TIME_FORMAT_AM : stm32wbxx_ll_rtc.h
  • LL_RTC_ALMB_TIME_FORMAT_PM : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR0 : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR1 : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR10 : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR11 : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR12 : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR13 : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR14 : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR15 : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR16 : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR17 : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR18 : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR19 : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR2 : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR3 : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR4 : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR5 : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR6 : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR7 : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR8 : stm32wbxx_ll_rtc.h
  • LL_RTC_BKP_DR9 : stm32wbxx_ll_rtc.h
  • LL_RTC_CALIB_INSERTPULSE_NONE : stm32wbxx_ll_rtc.h
  • LL_RTC_CALIB_INSERTPULSE_SET : stm32wbxx_ll_rtc.h
  • LL_RTC_CALIB_OUTPUT_1HZ : stm32wbxx_ll_rtc.h
  • LL_RTC_CALIB_OUTPUT_512HZ : stm32wbxx_ll_rtc.h
  • LL_RTC_CALIB_OUTPUT_NONE : stm32wbxx_ll_rtc.h
  • LL_RTC_CALIB_PERIOD_16SEC : stm32wbxx_ll_rtc.h
  • LL_RTC_CALIB_PERIOD_32SEC : stm32wbxx_ll_rtc.h
  • LL_RTC_CALIB_PERIOD_8SEC : stm32wbxx_ll_rtc.h
  • LL_RTC_CR_ALRAIE : stm32wbxx_ll_rtc.h
  • LL_RTC_CR_ALRBIE : stm32wbxx_ll_rtc.h
  • LL_RTC_CR_TSIE : stm32wbxx_ll_rtc.h
  • LL_RTC_CR_WUTIE : stm32wbxx_ll_rtc.h
  • LL_RTC_FORMAT_BCD : stm32wbxx_ll_rtc.h
  • LL_RTC_FORMAT_BIN : stm32wbxx_ll_rtc.h
  • LL_RTC_HOURFORMAT_24HOUR : stm32wbxx_ll_rtc.h
  • LL_RTC_HOURFORMAT_AMPM : stm32wbxx_ll_rtc.h
  • LL_RTC_ISR_ALRAF : stm32wbxx_ll_rtc.h
  • LL_RTC_ISR_ALRAWF : stm32wbxx_ll_rtc.h
  • LL_RTC_ISR_ALRBF : stm32wbxx_ll_rtc.h
  • LL_RTC_ISR_ALRBWF : stm32wbxx_ll_rtc.h
  • LL_RTC_ISR_INITF : stm32wbxx_ll_rtc.h
  • LL_RTC_ISR_INITS : stm32wbxx_ll_rtc.h
  • LL_RTC_ISR_ITSF : stm32wbxx_ll_rtc.h
  • LL_RTC_ISR_RECALPF : stm32wbxx_ll_rtc.h
  • LL_RTC_ISR_RSF : stm32wbxx_ll_rtc.h
  • LL_RTC_ISR_SHPF : stm32wbxx_ll_rtc.h
  • LL_RTC_ISR_TAMP1F : stm32wbxx_ll_rtc.h
  • LL_RTC_ISR_TAMP2F : stm32wbxx_ll_rtc.h
  • LL_RTC_ISR_TAMP3F : stm32wbxx_ll_rtc.h
  • LL_RTC_ISR_TSF : stm32wbxx_ll_rtc.h
  • LL_RTC_ISR_TSOVF : stm32wbxx_ll_rtc.h
  • LL_RTC_ISR_WUTF : stm32wbxx_ll_rtc.h
  • LL_RTC_ISR_WUTWF : stm32wbxx_ll_rtc.h
  • LL_RTC_MONTH_APRIL : stm32wbxx_ll_rtc.h
  • LL_RTC_MONTH_AUGUST : stm32wbxx_ll_rtc.h
  • LL_RTC_MONTH_DECEMBER : stm32wbxx_ll_rtc.h
  • LL_RTC_MONTH_FEBRUARY : stm32wbxx_ll_rtc.h
  • LL_RTC_MONTH_JANUARY : stm32wbxx_ll_rtc.h
  • LL_RTC_MONTH_JULY : stm32wbxx_ll_rtc.h
  • LL_RTC_MONTH_JUNE : stm32wbxx_ll_rtc.h
  • LL_RTC_MONTH_MARCH : stm32wbxx_ll_rtc.h
  • LL_RTC_MONTH_MAY : stm32wbxx_ll_rtc.h
  • LL_RTC_MONTH_NOVEMBER : stm32wbxx_ll_rtc.h
  • LL_RTC_MONTH_OCTOBER : stm32wbxx_ll_rtc.h
  • LL_RTC_MONTH_SEPTEMBER : stm32wbxx_ll_rtc.h
  • LL_RTC_OUTPUTPOLARITY_PIN_HIGH : stm32wbxx_ll_rtc.h
  • LL_RTC_OUTPUTPOLARITY_PIN_LOW : stm32wbxx_ll_rtc.h
  • LL_RTC_ReadReg : stm32wbxx_ll_rtc.h
  • LL_RTC_SHIFT_SECOND_ADVANCE : stm32wbxx_ll_rtc.h
  • LL_RTC_SHIFT_SECOND_DELAY : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPCR_TAMP1IE : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPCR_TAMP2IE : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPCR_TAMP3IE : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPCR_TAMPIE : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_1 : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_2 : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_3 : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_1RTCCLK : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_2RTCCLK : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_4RTCCLK : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_DURATION_8RTCCLK : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_2SAMPLE : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_4SAMPLE : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_8SAMPLE : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_FILTER_DISABLE : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_MASK_TAMPER1 : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_MASK_TAMPER2 : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_MASK_TAMPER3 : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_NOERASE_TAMPER1 : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_NOERASE_TAMPER2 : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_NOERASE_TAMPER3 : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_1024 : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_16384 : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_2048 : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_256 : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_32768 : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_4096 : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_512 : stm32wbxx_ll_rtc.h
  • LL_RTC_TAMPER_SAMPLFREQDIV_8192 : stm32wbxx_ll_rtc.h
  • LL_RTC_TIME_FORMAT_AM_OR_24 : stm32wbxx_ll_rtc.h
  • LL_RTC_TIME_FORMAT_PM : stm32wbxx_ll_rtc.h
  • LL_RTC_TIMESTAMP_EDGE_FALLING : stm32wbxx_ll_rtc.h
  • LL_RTC_TIMESTAMP_EDGE_RISING : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_TIME_FORMAT_AM : stm32wbxx_ll_rtc.h
  • LL_RTC_TS_TIME_FORMAT_PM : stm32wbxx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_CKSPRE : stm32wbxx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_CKSPRE_WUT : stm32wbxx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_16 : stm32wbxx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_2 : stm32wbxx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_4 : stm32wbxx_ll_rtc.h
  • LL_RTC_WAKEUPCLOCK_DIV_8 : stm32wbxx_ll_rtc.h
  • LL_RTC_WEEKDAY_FRIDAY : stm32wbxx_ll_rtc.h
  • LL_RTC_WEEKDAY_MONDAY : stm32wbxx_ll_rtc.h
  • LL_RTC_WEEKDAY_SATURDAY : stm32wbxx_ll_rtc.h
  • LL_RTC_WEEKDAY_SUNDAY : stm32wbxx_ll_rtc.h
  • LL_RTC_WEEKDAY_THURSDAY : stm32wbxx_ll_rtc.h
  • LL_RTC_WEEKDAY_TUESDAY : stm32wbxx_ll_rtc.h
  • LL_RTC_WEEKDAY_WEDNESDAY : stm32wbxx_ll_rtc.h
  • LL_RTC_WriteReg : stm32wbxx_ll_rtc.h
  • LL_SPI_BAUDRATEPRESCALER_DIV128 : stm32wbxx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV16 : stm32wbxx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV2 : stm32wbxx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV256 : stm32wbxx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV32 : stm32wbxx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV4 : stm32wbxx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV64 : stm32wbxx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV8 : stm32wbxx_ll_spi.h
  • LL_SPI_CR2_ERRIE : stm32wbxx_ll_spi.h
  • LL_SPI_CR2_RXNEIE : stm32wbxx_ll_spi.h
  • LL_SPI_CR2_TXEIE : stm32wbxx_ll_spi.h
  • LL_SPI_CRC_16BIT : stm32wbxx_ll_spi.h
  • LL_SPI_CRC_8BIT : stm32wbxx_ll_spi.h
  • LL_SPI_CRCCALCULATION_DISABLE : stm32wbxx_ll_spi.h
  • LL_SPI_CRCCALCULATION_ENABLE : stm32wbxx_ll_spi.h
  • LL_SPI_DATAWIDTH_10BIT : stm32wbxx_ll_spi.h
  • LL_SPI_DATAWIDTH_11BIT : stm32wbxx_ll_spi.h
  • LL_SPI_DATAWIDTH_12BIT : stm32wbxx_ll_spi.h
  • LL_SPI_DATAWIDTH_13BIT : stm32wbxx_ll_spi.h
  • LL_SPI_DATAWIDTH_14BIT : stm32wbxx_ll_spi.h
  • LL_SPI_DATAWIDTH_15BIT : stm32wbxx_ll_spi.h
  • LL_SPI_DATAWIDTH_16BIT : stm32wbxx_ll_spi.h
  • LL_SPI_DATAWIDTH_4BIT : stm32wbxx_ll_spi.h
  • LL_SPI_DATAWIDTH_5BIT : stm32wbxx_ll_spi.h
  • LL_SPI_DATAWIDTH_6BIT : stm32wbxx_ll_spi.h
  • LL_SPI_DATAWIDTH_7BIT : stm32wbxx_ll_spi.h
  • LL_SPI_DATAWIDTH_8BIT : stm32wbxx_ll_spi.h
  • LL_SPI_DATAWIDTH_9BIT : stm32wbxx_ll_spi.h
  • LL_SPI_DMA_PARITY_EVEN : stm32wbxx_ll_spi.h
  • LL_SPI_DMA_PARITY_ODD : stm32wbxx_ll_spi.h
  • LL_SPI_FULL_DUPLEX : stm32wbxx_ll_spi.h
  • LL_SPI_HALF_DUPLEX_RX : stm32wbxx_ll_spi.h
  • LL_SPI_HALF_DUPLEX_TX : stm32wbxx_ll_spi.h
  • LL_SPI_LSB_FIRST : stm32wbxx_ll_spi.h
  • LL_SPI_MODE_MASTER : stm32wbxx_ll_spi.h
  • LL_SPI_MODE_SLAVE : stm32wbxx_ll_spi.h
  • LL_SPI_MSB_FIRST : stm32wbxx_ll_spi.h
  • LL_SPI_NSS_HARD_INPUT : stm32wbxx_ll_spi.h
  • LL_SPI_NSS_HARD_OUTPUT : stm32wbxx_ll_spi.h
  • LL_SPI_NSS_SOFT : stm32wbxx_ll_spi.h
  • LL_SPI_PHASE_1EDGE : stm32wbxx_ll_spi.h
  • LL_SPI_PHASE_2EDGE : stm32wbxx_ll_spi.h
  • LL_SPI_POLARITY_HIGH : stm32wbxx_ll_spi.h
  • LL_SPI_POLARITY_LOW : stm32wbxx_ll_spi.h
  • LL_SPI_PROTOCOL_MOTOROLA : stm32wbxx_ll_spi.h
  • LL_SPI_PROTOCOL_TI : stm32wbxx_ll_spi.h
  • LL_SPI_ReadReg : stm32wbxx_ll_spi.h
  • LL_SPI_RX_FIFO_EMPTY : stm32wbxx_ll_spi.h
  • LL_SPI_RX_FIFO_FULL : stm32wbxx_ll_spi.h
  • LL_SPI_RX_FIFO_HALF_FULL : stm32wbxx_ll_spi.h
  • LL_SPI_RX_FIFO_QUARTER_FULL : stm32wbxx_ll_spi.h
  • LL_SPI_RX_FIFO_TH_HALF : stm32wbxx_ll_spi.h
  • LL_SPI_RX_FIFO_TH_QUARTER : stm32wbxx_ll_spi.h
  • LL_SPI_SIMPLEX_RX : stm32wbxx_ll_spi.h
  • LL_SPI_SR_BSY : stm32wbxx_ll_spi.h
  • LL_SPI_SR_CRCERR : stm32wbxx_ll_spi.h
  • LL_SPI_SR_FRE : stm32wbxx_ll_spi.h
  • LL_SPI_SR_MODF : stm32wbxx_ll_spi.h
  • LL_SPI_SR_OVR : stm32wbxx_ll_spi.h
  • LL_SPI_SR_RXNE : stm32wbxx_ll_spi.h
  • LL_SPI_SR_TXE : stm32wbxx_ll_spi.h
  • LL_SPI_TX_FIFO_EMPTY : stm32wbxx_ll_spi.h
  • LL_SPI_TX_FIFO_FULL : stm32wbxx_ll_spi.h
  • LL_SPI_TX_FIFO_HALF_FULL : stm32wbxx_ll_spi.h
  • LL_SPI_TX_FIFO_QUARTER_FULL : stm32wbxx_ll_spi.h
  • LL_SPI_WriteReg : stm32wbxx_ll_spi.h
  • LL_SYSCFG_EnableSRAM2PageWRP : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_LINE0 : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_LINE1 : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_LINE10 : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_LINE11 : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_LINE12 : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_LINE13 : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_LINE14 : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_LINE15 : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_LINE2 : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_LINE3 : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_LINE4 : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_LINE5 : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_LINE6 : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_LINE7 : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_LINE8 : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_LINE9 : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_PORTA : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_PORTB : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_PORTC : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_PORTD : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_PORTE : stm32wbxx_ll_system.h
  • LL_SYSCFG_EXTI_PORTH : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP1_EXTI10 : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP1_EXTI11 : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP1_EXTI12 : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP1_EXTI13 : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP1_EXTI14 : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP1_EXTI15 : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP1_EXTI5 : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP1_EXTI6 : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP1_EXTI7 : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP1_EXTI8 : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP1_EXTI9 : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP1_TIM1 : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP1_TIM16 : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP1_TIM17 : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP2_PVD : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP2_PVM1 : stm32wbxx_ll_system.h
  • LL_SYSCFG_GRP2_PVM3 : stm32wbxx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 : stm32wbxx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 : stm32wbxx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB6 : stm32wbxx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB7 : stm32wbxx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB8 : stm32wbxx_ll_system.h
  • LL_SYSCFG_I2C_FASTMODEPLUS_PB9 : stm32wbxx_ll_system.h
  • LL_SYSCFG_REMAP_FLASH : stm32wbxx_ll_system.h
  • LL_SYSCFG_REMAP_QUADSPI : stm32wbxx_ll_system.h
  • LL_SYSCFG_REMAP_SRAM : stm32wbxx_ll_system.h
  • LL_SYSCFG_REMAP_SYSTEMFLASH : stm32wbxx_ll_system.h
  • LL_SYSCFG_SECURE_ACCESS_AES1 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SECURE_ACCESS_AES2 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SECURE_ACCESS_PKA : stm32wbxx_ll_system.h
  • LL_SYSCFG_SECURE_ACCESS_RNG : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE0 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE1 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE10 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE11 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE12 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE13 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE14 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE15 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE16 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE17 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE18 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE19 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE2 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE20 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE21 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE22 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE23 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE24 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE25 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE26 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE27 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE28 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE29 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE3 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE30 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE31 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE32 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE33 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE34 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE35 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE36 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE37 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE38 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE39 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE4 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE40 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE41 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE42 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE43 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE44 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE45 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE46 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE47 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE48 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE49 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE5 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE50 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE51 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE52 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE53 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE54 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE55 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE56 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE57 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE58 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE59 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE6 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE60 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE61 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE62 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE63 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE7 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE8 : stm32wbxx_ll_system.h
  • LL_SYSCFG_SRAM2WRP_PAGE9 : stm32wbxx_ll_system.h
  • LL_SYSCFG_TIMBREAK_ECC : stm32wbxx_ll_system.h
  • LL_SYSCFG_TIMBREAK_LOCKUP : stm32wbxx_ll_system.h
  • LL_SYSCFG_TIMBREAK_PVD : stm32wbxx_ll_system.h
  • LL_SYSCFG_TIMBREAK_SRAM2_PARITY : stm32wbxx_ll_system.h
  • LL_SYSTICK_CLKSOURCE_HCLK : stm32wbxx_ll_cortex.h
  • LL_SYSTICK_CLKSOURCE_HCLK_DIV8 : stm32wbxx_ll_cortex.h
  • LL_TIM_ACTIVEINPUT_DIRECTTI : stm32wbxx_ll_tim.h
  • LL_TIM_ACTIVEINPUT_INDIRECTTI : stm32wbxx_ll_tim.h
  • LL_TIM_ACTIVEINPUT_TRC : stm32wbxx_ll_tim.h
  • LL_TIM_AUTOMATICOUTPUT_DISABLE : stm32wbxx_ll_tim.h
  • LL_TIM_AUTOMATICOUTPUT_ENABLE : stm32wbxx_ll_tim.h
  • LL_TIM_BKIN_POLARITY_HIGH : stm32wbxx_ll_tim.h
  • LL_TIM_BKIN_POLARITY_LOW : stm32wbxx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_BKCOMP1 : stm32wbxx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_BKCOMP2 : stm32wbxx_ll_tim.h
  • LL_TIM_BKIN_SOURCE_BKIN : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_DISABLE : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_ENABLE : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV16_N5 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV16_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV16_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1_N2 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1_N4 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV1_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV2_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV2_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV32_N5 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV32_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV32_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV4_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV4_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV8_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_FILTER_FDIV8_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_POLARITY_HIGH : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK2_POLARITY_LOW : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_DISABLE : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_ENABLE : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV16_N5 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV16_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV16_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1_N2 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1_N4 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV1_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV2_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV2_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV32_N5 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV32_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV32_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV4_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV4_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV8_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_FILTER_FDIV8_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_INPUT_BKIN : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_INPUT_BKIN2 : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_POLARITY_HIGH : stm32wbxx_ll_tim.h
  • LL_TIM_BREAK_POLARITY_LOW : stm32wbxx_ll_tim.h
  • LL_TIM_CCDMAREQUEST_CC : stm32wbxx_ll_tim.h
  • LL_TIM_CCDMAREQUEST_UPDATE : stm32wbxx_ll_tim.h
  • LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI : stm32wbxx_ll_tim.h
  • LL_TIM_CCUPDATESOURCE_COMG_ONLY : stm32wbxx_ll_tim.h
  • LL_TIM_CHANNEL_CH1 : stm32wbxx_ll_tim.h
  • LL_TIM_CHANNEL_CH1N : stm32wbxx_ll_tim.h
  • LL_TIM_CHANNEL_CH2 : stm32wbxx_ll_tim.h
  • LL_TIM_CHANNEL_CH2N : stm32wbxx_ll_tim.h
  • LL_TIM_CHANNEL_CH3 : stm32wbxx_ll_tim.h
  • LL_TIM_CHANNEL_CH3N : stm32wbxx_ll_tim.h
  • LL_TIM_CHANNEL_CH4 : stm32wbxx_ll_tim.h
  • LL_TIM_CHANNEL_CH5 : stm32wbxx_ll_tim.h
  • LL_TIM_CHANNEL_CH6 : stm32wbxx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV1 : stm32wbxx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV2 : stm32wbxx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV4 : stm32wbxx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_EXT_MODE1 : stm32wbxx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_EXT_MODE2 : stm32wbxx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_INTERNAL : stm32wbxx_ll_tim.h
  • LL_TIM_COUNTERDIRECTION_DOWN : stm32wbxx_ll_tim.h
  • LL_TIM_COUNTERDIRECTION_UP : stm32wbxx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_DOWN : stm32wbxx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_UP : stm32wbxx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_UP_DOWN : stm32wbxx_ll_tim.h
  • LL_TIM_COUNTERMODE_DOWN : stm32wbxx_ll_tim.h
  • LL_TIM_COUNTERMODE_UP : stm32wbxx_ll_tim.h
  • LL_TIM_DIER_BIE : stm32wbxx_ll_tim.h
  • LL_TIM_DIER_CC1IE : stm32wbxx_ll_tim.h
  • LL_TIM_DIER_CC2IE : stm32wbxx_ll_tim.h
  • LL_TIM_DIER_CC3IE : stm32wbxx_ll_tim.h
  • LL_TIM_DIER_CC4IE : stm32wbxx_ll_tim.h
  • LL_TIM_DIER_COMIE : stm32wbxx_ll_tim.h
  • LL_TIM_DIER_TIE : stm32wbxx_ll_tim.h
  • LL_TIM_DIER_UIE : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_AF1 : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_AF2 : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_ARR : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_BDTR : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCER : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR1 : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR2 : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR3 : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR1 : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR2 : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR3 : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR4 : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR5 : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR6 : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CNT : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CR1 : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CR2 : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_DIER : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_EGR : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_OR : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_PSC : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_RCR : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_SMCR : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_SR : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_10TRANSFERS : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_11TRANSFERS : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_12TRANSFERS : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_13TRANSFERS : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_14TRANSFERS : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_15TRANSFERS : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_16TRANSFERS : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_17TRANSFERS : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_18TRANSFERS : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_1TRANSFER : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_2TRANSFERS : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_3TRANSFERS : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_4TRANSFERS : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_5TRANSFERS : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_6TRANSFERS : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_7TRANSFERS : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_8TRANSFERS : stm32wbxx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_9TRANSFERS : stm32wbxx_ll_tim.h
  • LL_TIM_ENCODERMODE_X2_TI1 : stm32wbxx_ll_tim.h
  • LL_TIM_ENCODERMODE_X2_TI2 : stm32wbxx_ll_tim.h
  • LL_TIM_ENCODERMODE_X4_TI12 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N5 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N2 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N4 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV2_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV2_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N5 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV4_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV4_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV8_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV8_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_POLARITY_INVERTED : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_POLARITY_NONINVERTED : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV1 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV2 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV4 : stm32wbxx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV8 : stm32wbxx_ll_tim.h
  • LL_TIM_ETRSOURCE_ADC1_AWD1 : stm32wbxx_ll_tim.h
  • LL_TIM_ETRSOURCE_ADC1_AWD2 : stm32wbxx_ll_tim.h
  • LL_TIM_ETRSOURCE_ADC1_AWD3 : stm32wbxx_ll_tim.h
  • LL_TIM_ETRSOURCE_COMP1 : stm32wbxx_ll_tim.h
  • LL_TIM_ETRSOURCE_COMP2 : stm32wbxx_ll_tim.h
  • LL_TIM_ETRSOURCE_GPIO : stm32wbxx_ll_tim.h
  • LL_TIM_ETRSOURCE_LEGACY : stm32wbxx_ll_tim.h
  • LL_TIM_GROUPCH5_NONE : stm32wbxx_ll_tim.h
  • LL_TIM_GROUPCH5_OC1REFC : stm32wbxx_ll_tim.h
  • LL_TIM_GROUPCH5_OC2REFC : stm32wbxx_ll_tim.h
  • LL_TIM_GROUPCH5_OC3REFC : stm32wbxx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1 : stm32wbxx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N5 : stm32wbxx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N2 : stm32wbxx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N4 : stm32wbxx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV2_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV2_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N5 : stm32wbxx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV4_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV4_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV8_N6 : stm32wbxx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV8_N8 : stm32wbxx_ll_tim.h
  • LL_TIM_IC_POLARITY_BOTHEDGE : stm32wbxx_ll_tim.h
  • LL_TIM_IC_POLARITY_FALLING : stm32wbxx_ll_tim.h
  • LL_TIM_IC_POLARITY_RISING : stm32wbxx_ll_tim.h
  • LL_TIM_ICPSC_DIV1 : stm32wbxx_ll_tim.h
  • LL_TIM_ICPSC_DIV2 : stm32wbxx_ll_tim.h
  • LL_TIM_ICPSC_DIV4 : stm32wbxx_ll_tim.h
  • LL_TIM_ICPSC_DIV8 : stm32wbxx_ll_tim.h
  • LL_TIM_LOCKLEVEL_1 : stm32wbxx_ll_tim.h
  • LL_TIM_LOCKLEVEL_2 : stm32wbxx_ll_tim.h
  • LL_TIM_LOCKLEVEL_3 : stm32wbxx_ll_tim.h
  • LL_TIM_LOCKLEVEL_OFF : stm32wbxx_ll_tim.h
  • LL_TIM_OCIDLESTATE_HIGH : stm32wbxx_ll_tim.h
  • LL_TIM_OCIDLESTATE_LOW : stm32wbxx_ll_tim.h
  • LL_TIM_OCMODE_ACTIVE : stm32wbxx_ll_tim.h
  • LL_TIM_OCMODE_ASSYMETRIC_PWM1 : stm32wbxx_ll_tim.h
  • LL_TIM_OCMODE_ASSYMETRIC_PWM2 : stm32wbxx_ll_tim.h
  • LL_TIM_OCMODE_COMBINED_PWM1 : stm32wbxx_ll_tim.h
  • LL_TIM_OCMODE_COMBINED_PWM2 : stm32wbxx_ll_tim.h
  • LL_TIM_OCMODE_FORCED_ACTIVE : stm32wbxx_ll_tim.h
  • LL_TIM_OCMODE_FORCED_INACTIVE : stm32wbxx_ll_tim.h
  • LL_TIM_OCMODE_FROZEN : stm32wbxx_ll_tim.h
  • LL_TIM_OCMODE_INACTIVE : stm32wbxx_ll_tim.h
  • LL_TIM_OCMODE_PWM1 : stm32wbxx_ll_tim.h
  • LL_TIM_OCMODE_PWM2 : stm32wbxx_ll_tim.h
  • LL_TIM_OCMODE_RETRIG_OPM1 : stm32wbxx_ll_tim.h
  • LL_TIM_OCMODE_RETRIG_OPM2 : stm32wbxx_ll_tim.h
  • LL_TIM_OCMODE_TOGGLE : stm32wbxx_ll_tim.h
  • LL_TIM_OCPOLARITY_HIGH : stm32wbxx_ll_tim.h
  • LL_TIM_OCPOLARITY_LOW : stm32wbxx_ll_tim.h
  • LL_TIM_OCREF_CLR_INT_ETR : stm32wbxx_ll_tim.h
  • LL_TIM_OCREF_CLR_INT_OCREF_CLR : stm32wbxx_ll_tim.h
  • LL_TIM_OCSTATE_DISABLE : stm32wbxx_ll_tim.h
  • LL_TIM_OCSTATE_ENABLE : stm32wbxx_ll_tim.h
  • LL_TIM_ONEPULSEMODE_REPETITIVE : stm32wbxx_ll_tim.h
  • LL_TIM_ONEPULSEMODE_SINGLE : stm32wbxx_ll_tim.h
  • LL_TIM_OSSI_DISABLE : stm32wbxx_ll_tim.h
  • LL_TIM_OSSI_ENABLE : stm32wbxx_ll_tim.h
  • LL_TIM_OSSR_DISABLE : stm32wbxx_ll_tim.h
  • LL_TIM_OSSR_ENABLE : stm32wbxx_ll_tim.h
  • LL_TIM_ReadReg : stm32wbxx_ll_tim.h
  • LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER : stm32wbxx_ll_tim.h
  • LL_TIM_SLAVEMODE_DISABLED : stm32wbxx_ll_tim.h
  • LL_TIM_SLAVEMODE_GATED : stm32wbxx_ll_tim.h
  • LL_TIM_SLAVEMODE_RESET : stm32wbxx_ll_tim.h
  • LL_TIM_SLAVEMODE_TRIGGER : stm32wbxx_ll_tim.h
  • LL_TIM_SR_B2IF : stm32wbxx_ll_tim.h
  • LL_TIM_SR_BIF : stm32wbxx_ll_tim.h
  • LL_TIM_SR_CC1IF : stm32wbxx_ll_tim.h
  • LL_TIM_SR_CC1OF : stm32wbxx_ll_tim.h
  • LL_TIM_SR_CC2IF : stm32wbxx_ll_tim.h
  • LL_TIM_SR_CC2OF : stm32wbxx_ll_tim.h
  • LL_TIM_SR_CC3IF : stm32wbxx_ll_tim.h
  • LL_TIM_SR_CC3OF : stm32wbxx_ll_tim.h
  • LL_TIM_SR_CC4IF : stm32wbxx_ll_tim.h
  • LL_TIM_SR_CC4OF : stm32wbxx_ll_tim.h
  • LL_TIM_SR_CC5IF : stm32wbxx_ll_tim.h
  • LL_TIM_SR_CC6IF : stm32wbxx_ll_tim.h
  • LL_TIM_SR_COMIF : stm32wbxx_ll_tim.h
  • LL_TIM_SR_SBIF : stm32wbxx_ll_tim.h
  • LL_TIM_SR_TIF : stm32wbxx_ll_tim.h
  • LL_TIM_SR_UIF : stm32wbxx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_GPIO : stm32wbxx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_LSE : stm32wbxx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_LSI : stm32wbxx_ll_tim.h
  • LL_TIM_TIM16_TI1_RMP_RTC : stm32wbxx_ll_tim.h
  • LL_TIM_TIM17_TI1_RMP_GPIO : stm32wbxx_ll_tim.h
  • LL_TIM_TIM17_TI1_RMP_HSE_32 : stm32wbxx_ll_tim.h
  • LL_TIM_TIM17_TI1_RMP_MCO : stm32wbxx_ll_tim.h
  • LL_TIM_TIM17_TI1_RMP_MSI : stm32wbxx_ll_tim.h
  • LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 : stm32wbxx_ll_tim.h
  • LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 : stm32wbxx_ll_tim.h
  • LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 : stm32wbxx_ll_tim.h
  • LL_TIM_TIM1_ETR_ADC1_RMP_NC : stm32wbxx_ll_tim.h
  • LL_TIM_TIM1_TI1_RMP_COMP1 : stm32wbxx_ll_tim.h
  • LL_TIM_TIM1_TI1_RMP_GPIO : stm32wbxx_ll_tim.h
  • LL_TIM_TIM2_ETR_RMP_GPIO : stm32wbxx_ll_tim.h
  • LL_TIM_TIM2_ETR_RMP_LSE : stm32wbxx_ll_tim.h
  • LL_TIM_TIM2_ITR1_RMP_NONE : stm32wbxx_ll_tim.h
  • LL_TIM_TIM2_ITR1_RMP_USB_SOF : stm32wbxx_ll_tim.h
  • LL_TIM_TIM2_TI4_RMP_COMP1 : stm32wbxx_ll_tim.h
  • LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 : stm32wbxx_ll_tim.h
  • LL_TIM_TIM2_TI4_RMP_COMP2 : stm32wbxx_ll_tim.h
  • LL_TIM_TIM2_TI4_RMP_GPIO : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO2_CC1F : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO2_ENABLE : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO2_OC1 : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO2_OC2 : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO2_OC3 : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO2_OC4 : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO2_OC4_RISING_OC6_FALLING : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO2_OC4_RISING_OC6_RISING : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO2_OC4_RISINGFALLING : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO2_OC5 : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO2_OC5_RISING_OC6_FALLING : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO2_OC5_RISING_OC6_RISING : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO2_OC6 : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO2_OC6_RISINGFALLING : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO2_RESET : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO2_UPDATE : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO_CC1IF : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO_ENABLE : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO_OC1REF : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO_OC2REF : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO_OC3REF : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO_OC4REF : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO_RESET : stm32wbxx_ll_tim.h
  • LL_TIM_TRGO_UPDATE : stm32wbxx_ll_tim.h
  • LL_TIM_TS_ETRF : stm32wbxx_ll_tim.h
  • LL_TIM_TS_ITR0 : stm32wbxx_ll_tim.h
  • LL_TIM_TS_ITR1 : stm32wbxx_ll_tim.h
  • LL_TIM_TS_ITR2 : stm32wbxx_ll_tim.h
  • LL_TIM_TS_ITR3 : stm32wbxx_ll_tim.h
  • LL_TIM_TS_TI1F_ED : stm32wbxx_ll_tim.h
  • LL_TIM_TS_TI1FP1 : stm32wbxx_ll_tim.h
  • LL_TIM_TS_TI2FP2 : stm32wbxx_ll_tim.h
  • LL_TIM_UPDATESOURCE_COUNTER : stm32wbxx_ll_tim.h
  • LL_TIM_UPDATESOURCE_REGULAR : stm32wbxx_ll_tim.h
  • LL_TIM_WriteReg : stm32wbxx_ll_tim.h
  • LL_USART_ADDRESS_DETECT_4B : stm32wbxx_ll_usart.h
  • LL_USART_ADDRESS_DETECT_7B : stm32wbxx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_55_FRAME : stm32wbxx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME : stm32wbxx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE : stm32wbxx_ll_usart.h
  • LL_USART_AUTOBAUD_DETECT_ON_STARTBIT : stm32wbxx_ll_usart.h
  • LL_USART_BINARY_LOGIC_NEGATIVE : stm32wbxx_ll_usart.h
  • LL_USART_BINARY_LOGIC_POSITIVE : stm32wbxx_ll_usart.h
  • LL_USART_BITORDER_LSBFIRST : stm32wbxx_ll_usart.h
  • LL_USART_BITORDER_MSBFIRST : stm32wbxx_ll_usart.h
  • LL_USART_CLOCK_DISABLE : stm32wbxx_ll_usart.h
  • LL_USART_CLOCK_ENABLE : stm32wbxx_ll_usart.h
  • LL_USART_CR1_CMIE : stm32wbxx_ll_usart.h
  • LL_USART_CR1_EOBIE : stm32wbxx_ll_usart.h
  • LL_USART_CR1_IDLEIE : stm32wbxx_ll_usart.h
  • LL_USART_CR1_PEIE : stm32wbxx_ll_usart.h
  • LL_USART_CR1_RTOIE : stm32wbxx_ll_usart.h
  • LL_USART_CR1_RXFFIE : stm32wbxx_ll_usart.h
  • LL_USART_CR1_RXNEIE_RXFNEIE : stm32wbxx_ll_usart.h
  • LL_USART_CR1_TCIE : stm32wbxx_ll_usart.h
  • LL_USART_CR1_TXEIE_TXFNFIE : stm32wbxx_ll_usart.h
  • LL_USART_CR1_TXFEIE : stm32wbxx_ll_usart.h
  • LL_USART_CR2_LBDIE : stm32wbxx_ll_usart.h
  • LL_USART_CR3_CTSIE : stm32wbxx_ll_usart.h
  • LL_USART_CR3_EIE : stm32wbxx_ll_usart.h
  • LL_USART_CR3_RXFTIE : stm32wbxx_ll_usart.h
  • LL_USART_CR3_TCBGTIE : stm32wbxx_ll_usart.h
  • LL_USART_CR3_TXFTIE : stm32wbxx_ll_usart.h
  • LL_USART_CR3_WUFIE : stm32wbxx_ll_usart.h
  • LL_USART_DATAWIDTH_7B : stm32wbxx_ll_usart.h
  • LL_USART_DATAWIDTH_8B : stm32wbxx_ll_usart.h
  • LL_USART_DATAWIDTH_9B : stm32wbxx_ll_usart.h
  • LL_USART_DE_POLARITY_HIGH : stm32wbxx_ll_usart.h
  • LL_USART_DE_POLARITY_LOW : stm32wbxx_ll_usart.h
  • LL_USART_DIRECTION_NONE : stm32wbxx_ll_usart.h
  • LL_USART_DIRECTION_RX : stm32wbxx_ll_usart.h
  • LL_USART_DIRECTION_TX : stm32wbxx_ll_usart.h
  • LL_USART_DIRECTION_TX_RX : stm32wbxx_ll_usart.h
  • LL_USART_DisableIT_RXNE : stm32wbxx_ll_usart.h
  • LL_USART_DisableIT_TXE : stm32wbxx_ll_usart.h
  • LL_USART_DMA_REG_DATA_RECEIVE : stm32wbxx_ll_usart.h
  • LL_USART_DMA_REG_DATA_TRANSMIT : stm32wbxx_ll_usart.h
  • LL_USART_EnableIT_RXNE : stm32wbxx_ll_usart.h
  • LL_USART_EnableIT_TXE : stm32wbxx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_1_2 : stm32wbxx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_1_4 : stm32wbxx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_1_8 : stm32wbxx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_3_4 : stm32wbxx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_7_8 : stm32wbxx_ll_usart.h
  • LL_USART_FIFOTHRESHOLD_8_8 : stm32wbxx_ll_usart.h
  • LL_USART_HWCONTROL_CTS : stm32wbxx_ll_usart.h
  • LL_USART_HWCONTROL_NONE : stm32wbxx_ll_usart.h
  • LL_USART_HWCONTROL_RTS : stm32wbxx_ll_usart.h
  • LL_USART_HWCONTROL_RTS_CTS : stm32wbxx_ll_usart.h
  • LL_USART_ICR_CMCF : stm32wbxx_ll_usart.h
  • LL_USART_ICR_CTSCF : stm32wbxx_ll_usart.h
  • LL_USART_ICR_EOBCF : stm32wbxx_ll_usart.h
  • LL_USART_ICR_FECF : stm32wbxx_ll_usart.h
  • LL_USART_ICR_IDLECF : stm32wbxx_ll_usart.h
  • LL_USART_ICR_LBDCF : stm32wbxx_ll_usart.h
  • LL_USART_ICR_NECF : stm32wbxx_ll_usart.h
  • LL_USART_ICR_ORECF : stm32wbxx_ll_usart.h
  • LL_USART_ICR_PECF : stm32wbxx_ll_usart.h
  • LL_USART_ICR_RTOCF : stm32wbxx_ll_usart.h
  • LL_USART_ICR_TCBGTCF : stm32wbxx_ll_usart.h
  • LL_USART_ICR_TCCF : stm32wbxx_ll_usart.h
  • LL_USART_ICR_TXFECF : stm32wbxx_ll_usart.h
  • LL_USART_ICR_UDRCF : stm32wbxx_ll_usart.h
  • LL_USART_ICR_WUCF : stm32wbxx_ll_usart.h
  • LL_USART_IRDA_POWER_LOW : stm32wbxx_ll_usart.h
  • LL_USART_IRDA_POWER_NORMAL : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_RXNE : stm32wbxx_ll_usart.h
  • LL_USART_IsActiveFlag_TXE : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIT_RXNE : stm32wbxx_ll_usart.h
  • LL_USART_IsEnabledIT_TXE : stm32wbxx_ll_usart.h
  • LL_USART_ISR_ABRE : stm32wbxx_ll_usart.h
  • LL_USART_ISR_ABRF : stm32wbxx_ll_usart.h
  • LL_USART_ISR_BUSY : stm32wbxx_ll_usart.h
  • LL_USART_ISR_CMF : stm32wbxx_ll_usart.h
  • LL_USART_ISR_CTS : stm32wbxx_ll_usart.h
  • LL_USART_ISR_CTSIF : stm32wbxx_ll_usart.h
  • LL_USART_ISR_EOBF : stm32wbxx_ll_usart.h
  • LL_USART_ISR_FE : stm32wbxx_ll_usart.h
  • LL_USART_ISR_IDLE : stm32wbxx_ll_usart.h
  • LL_USART_ISR_LBDF : stm32wbxx_ll_usart.h
  • LL_USART_ISR_NE : stm32wbxx_ll_usart.h
  • LL_USART_ISR_ORE : stm32wbxx_ll_usart.h
  • LL_USART_ISR_PE : stm32wbxx_ll_usart.h
  • LL_USART_ISR_REACK : stm32wbxx_ll_usart.h
  • LL_USART_ISR_RTOF : stm32wbxx_ll_usart.h
  • LL_USART_ISR_RWU : stm32wbxx_ll_usart.h
  • LL_USART_ISR_RXFF : stm32wbxx_ll_usart.h
  • LL_USART_ISR_RXFT : stm32wbxx_ll_usart.h
  • LL_USART_ISR_RXNE_RXFNE : stm32wbxx_ll_usart.h
  • LL_USART_ISR_SBKF : stm32wbxx_ll_usart.h
  • LL_USART_ISR_TC : stm32wbxx_ll_usart.h
  • LL_USART_ISR_TCBGT : stm32wbxx_ll_usart.h
  • LL_USART_ISR_TEACK : stm32wbxx_ll_usart.h
  • LL_USART_ISR_TXE_TXFNF : stm32wbxx_ll_usart.h
  • LL_USART_ISR_TXFE : stm32wbxx_ll_usart.h
  • LL_USART_ISR_TXFT : stm32wbxx_ll_usart.h
  • LL_USART_ISR_UDR : stm32wbxx_ll_usart.h
  • LL_USART_ISR_WUF : stm32wbxx_ll_usart.h
  • LL_USART_LASTCLKPULSE_NO_OUTPUT : stm32wbxx_ll_usart.h
  • LL_USART_LASTCLKPULSE_OUTPUT : stm32wbxx_ll_usart.h
  • LL_USART_LINBREAK_DETECT_10B : stm32wbxx_ll_usart.h
  • LL_USART_LINBREAK_DETECT_11B : stm32wbxx_ll_usart.h
  • LL_USART_OVERSAMPLING_16 : stm32wbxx_ll_usart.h
  • LL_USART_OVERSAMPLING_8 : stm32wbxx_ll_usart.h
  • LL_USART_PARITY_EVEN : stm32wbxx_ll_usart.h
  • LL_USART_PARITY_NONE : stm32wbxx_ll_usart.h
  • LL_USART_PARITY_ODD : stm32wbxx_ll_usart.h
  • LL_USART_PHASE_1EDGE : stm32wbxx_ll_usart.h
  • LL_USART_PHASE_2EDGE : stm32wbxx_ll_usart.h
  • LL_USART_POLARITY_HIGH : stm32wbxx_ll_usart.h
  • LL_USART_POLARITY_LOW : stm32wbxx_ll_usart.h
  • LL_USART_PRESCALER_DIV1 : stm32wbxx_ll_usart.h
  • LL_USART_PRESCALER_DIV10 : stm32wbxx_ll_usart.h
  • LL_USART_PRESCALER_DIV12 : stm32wbxx_ll_usart.h
  • LL_USART_PRESCALER_DIV128 : stm32wbxx_ll_usart.h
  • LL_USART_PRESCALER_DIV16 : stm32wbxx_ll_usart.h
  • LL_USART_PRESCALER_DIV2 : stm32wbxx_ll_usart.h
  • LL_USART_PRESCALER_DIV256 : stm32wbxx_ll_usart.h
  • LL_USART_PRESCALER_DIV32 : stm32wbxx_ll_usart.h
  • LL_USART_PRESCALER_DIV4 : stm32wbxx_ll_usart.h
  • LL_USART_PRESCALER_DIV6 : stm32wbxx_ll_usart.h
  • LL_USART_PRESCALER_DIV64 : stm32wbxx_ll_usart.h
  • LL_USART_PRESCALER_DIV8 : stm32wbxx_ll_usart.h
  • LL_USART_ReadReg : stm32wbxx_ll_usart.h
  • LL_USART_RXPIN_LEVEL_INVERTED : stm32wbxx_ll_usart.h
  • LL_USART_RXPIN_LEVEL_STANDARD : stm32wbxx_ll_usart.h
  • LL_USART_STOPBITS_0_5 : stm32wbxx_ll_usart.h
  • LL_USART_STOPBITS_1 : stm32wbxx_ll_usart.h
  • LL_USART_STOPBITS_1_5 : stm32wbxx_ll_usart.h
  • LL_USART_STOPBITS_2 : stm32wbxx_ll_usart.h
  • LL_USART_TXPIN_LEVEL_INVERTED : stm32wbxx_ll_usart.h
  • LL_USART_TXPIN_LEVEL_STANDARD : stm32wbxx_ll_usart.h
  • LL_USART_TXRX_STANDARD : stm32wbxx_ll_usart.h
  • LL_USART_TXRX_SWAPPED : stm32wbxx_ll_usart.h
  • LL_USART_WAKEUP_ADDRESSMARK : stm32wbxx_ll_usart.h
  • LL_USART_WAKEUP_IDLELINE : stm32wbxx_ll_usart.h
  • LL_USART_WAKEUP_ON_ADDRESS : stm32wbxx_ll_usart.h
  • LL_USART_WAKEUP_ON_RXNE : stm32wbxx_ll_usart.h
  • LL_USART_WAKEUP_ON_STARTBIT : stm32wbxx_ll_usart.h
  • LL_USART_WriteReg : stm32wbxx_ll_usart.h
  • LL_UTILS_HSEBYPASS_OFF : stm32wbxx_ll_utils.h
  • LL_UTILS_HSEBYPASS_ON : stm32wbxx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_CSP100 : stm32wbxx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_CSP100_C : stm32wbxx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_QFN48 : stm32wbxx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_QFN48_C : stm32wbxx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_QFN68 : stm32wbxx_ll_utils.h
  • LL_UTILS_PACKAGETYPE_QFN68_C : stm32wbxx_ll_utils.h
  • LL_VREFBUF_VOLTAGE_SCALE0 : stm32wbxx_ll_system.h
  • LL_VREFBUF_VOLTAGE_SCALE1 : stm32wbxx_ll_system.h
  • LL_WWDG_CFR_EWI : stm32wbxx_ll_wwdg.h
  • LL_WWDG_PRESCALER_1 : stm32wbxx_ll_wwdg.h
  • LL_WWDG_PRESCALER_128 : stm32wbxx_ll_wwdg.h
  • LL_WWDG_PRESCALER_16 : stm32wbxx_ll_wwdg.h
  • LL_WWDG_PRESCALER_2 : stm32wbxx_ll_wwdg.h
  • LL_WWDG_PRESCALER_32 : stm32wbxx_ll_wwdg.h
  • LL_WWDG_PRESCALER_4 : stm32wbxx_ll_wwdg.h
  • LL_WWDG_PRESCALER_64 : stm32wbxx_ll_wwdg.h
  • LL_WWDG_PRESCALER_8 : stm32wbxx_ll_wwdg.h
  • LL_WWDG_ReadReg : stm32wbxx_ll_wwdg.h
  • LL_WWDG_WriteReg : stm32wbxx_ll_wwdg.h
  • LPTIM_ACTIVEEDGE_FALLING : stm32wbxx_hal_lptim.h
  • LPTIM_ACTIVEEDGE_RISING : stm32wbxx_hal_lptim.h
  • LPTIM_ACTIVEEDGE_RISING_FALLING : stm32wbxx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_FALLING : stm32wbxx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_RISING : stm32wbxx_hal_lptim.h
  • LPTIM_CLOCKPOLARITY_RISING_FALLING : stm32wbxx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_2TRANSITIONS : stm32wbxx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_4TRANSITIONS : stm32wbxx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_8TRANSITIONS : stm32wbxx_hal_lptim.h
  • LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION : stm32wbxx_hal_lptim.h
  • LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC : stm32wbxx_hal_lptim.h
  • LPTIM_CLOCKSOURCE_ULPTIM : stm32wbxx_hal_lptim.h
  • LPTIM_COUNTERSOURCE_EXTERNAL : stm32wbxx_hal_lptim.h
  • LPTIM_COUNTERSOURCE_INTERNAL : stm32wbxx_hal_lptim.h
  • LPTIM_EXTI_LINE_LPTIM1 : stm32wbxx_hal_lptim.h
  • LPTIM_EXTI_LINE_LPTIM2 : stm32wbxx_hal_lptim.h
  • LPTIM_FLAG_ARRM : stm32wbxx_hal_lptim.h
  • LPTIM_FLAG_ARROK : stm32wbxx_hal_lptim.h
  • LPTIM_FLAG_CMPM : stm32wbxx_hal_lptim.h
  • LPTIM_FLAG_CMPOK : stm32wbxx_hal_lptim.h
  • LPTIM_FLAG_DOWN : stm32wbxx_hal_lptim.h
  • LPTIM_FLAG_EXTTRIG : stm32wbxx_hal_lptim.h
  • LPTIM_FLAG_UP : stm32wbxx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_COMP1 : stm32wbxx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_COMP1_COMP2 : stm32wbxx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_COMP2 : stm32wbxx_hal_lptim.h
  • LPTIM_INPUT1SOURCE_GPIO : stm32wbxx_hal_lptim.h
  • LPTIM_INPUT2SOURCE_COMP2 : stm32wbxx_hal_lptim.h
  • LPTIM_INPUT2SOURCE_GPIO : stm32wbxx_hal_lptim.h
  • LPTIM_IT_ARRM : stm32wbxx_hal_lptim.h
  • LPTIM_IT_ARROK : stm32wbxx_hal_lptim.h
  • LPTIM_IT_CMPM : stm32wbxx_hal_lptim.h
  • LPTIM_IT_CMPOK : stm32wbxx_hal_lptim.h
  • LPTIM_IT_DOWN : stm32wbxx_hal_lptim.h
  • LPTIM_IT_EXTTRIG : stm32wbxx_hal_lptim.h
  • LPTIM_IT_UP : stm32wbxx_hal_lptim.h
  • LPTIM_OUTPUTPOLARITY_HIGH : stm32wbxx_hal_lptim.h
  • LPTIM_OUTPUTPOLARITY_LOW : stm32wbxx_hal_lptim.h
  • LPTIM_PRESCALER_DIV1 : stm32wbxx_hal_lptim.h
  • LPTIM_PRESCALER_DIV128 : stm32wbxx_hal_lptim.h
  • LPTIM_PRESCALER_DIV16 : stm32wbxx_hal_lptim.h
  • LPTIM_PRESCALER_DIV2 : stm32wbxx_hal_lptim.h
  • LPTIM_PRESCALER_DIV32 : stm32wbxx_hal_lptim.h
  • LPTIM_PRESCALER_DIV4 : stm32wbxx_hal_lptim.h
  • LPTIM_PRESCALER_DIV64 : stm32wbxx_hal_lptim.h
  • LPTIM_PRESCALER_DIV8 : stm32wbxx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_2TRANSITIONS : stm32wbxx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_4TRANSITIONS : stm32wbxx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_8TRANSITIONS : stm32wbxx_hal_lptim.h
  • LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION : stm32wbxx_hal_lptim.h
  • LPTIM_TRIGSOURCE_0 : stm32wbxx_hal_lptim.h
  • LPTIM_TRIGSOURCE_1 : stm32wbxx_hal_lptim.h
  • LPTIM_TRIGSOURCE_2 : stm32wbxx_hal_lptim.h
  • LPTIM_TRIGSOURCE_3 : stm32wbxx_hal_lptim.h
  • LPTIM_TRIGSOURCE_4 : stm32wbxx_hal_lptim.h
  • LPTIM_TRIGSOURCE_5 : stm32wbxx_hal_lptim.h
  • LPTIM_TRIGSOURCE_6 : stm32wbxx_hal_lptim.h
  • LPTIM_TRIGSOURCE_7 : stm32wbxx_hal_lptim.h
  • LPTIM_TRIGSOURCE_SOFTWARE : stm32wbxx_hal_lptim.h
  • LPTIM_UPDATE_ENDOFPERIOD : stm32wbxx_hal_lptim.h
  • LPTIM_UPDATE_IMMEDIATE : stm32wbxx_hal_lptim.h
  • LPUART_BRR_MASK : stm32wbxx_ll_lpuart.h
  • LPUART_BRR_MAX : stm32wbxx_hal_uart.c
  • LPUART_BRR_MIN : stm32wbxx_hal_uart.c
  • LPUART_BRR_MIN_VALUE : stm32wbxx_ll_lpuart.h
  • LPUART_LPUARTDIV_FREQ_MUL : stm32wbxx_ll_lpuart.h
  • LSCO1_GPIO_PORT : stm32wbxx_hal_rcc_ex.c
  • LSCO1_PIN : stm32wbxx_hal_rcc_ex.c
  • LSCO2_GPIO_PORT : stm32wbxx_hal_rcc_ex.c
  • LSCO2_PIN : stm32wbxx_hal_rcc_ex.c
  • LSCO3_GPIO_PORT : stm32wbxx_hal_rcc_ex.c
  • LSCO3_PIN : stm32wbxx_hal_rcc_ex.c
  • LSE_STARTUP_TIMEOUT : stm32wbxx_hal_conf.h
  • LSE_VALUE : stm32wbxx_hal_conf.h
  • LSI1_TIMEOUT_VALUE : stm32wbxx_hal_rcc.c
  • LSI1_VALUE : stm32wbxx_hal_conf.h
  • LSI2_TIMEOUT_VALUE : stm32wbxx_hal_rcc.c , stm32wbxx_hal_rcc_ex.c
  • LSI2_VALUE : stm32wbxx_hal_conf.h
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

  • File List
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- m -

  • MAX_NBYTE_SIZE : stm32wbxx_hal_i2c.c , stm32wbxx_hal_smbus.c
  • MCO1_GPIO_PORT : stm32wbxx_hal_rcc.c
  • MCO1_PIN : stm32wbxx_hal_rcc.c
  • MCO2_GPIO_PORT : stm32wbxx_hal_rcc.c
  • MCO2_PIN : stm32wbxx_hal_rcc.c
  • MCO3_GPIO_PORT : stm32wbxx_hal_rcc.c
  • MCO3_PIN : stm32wbxx_hal_rcc.c
  • MEGA_HZ : stm32wbxx_hal_rcc.c
  • MPU_ACCESS_BUFFERABLE : stm32wbxx_hal_cortex.h
  • MPU_ACCESS_CACHEABLE : stm32wbxx_hal_cortex.h
  • MPU_ACCESS_NOT_BUFFERABLE : stm32wbxx_hal_cortex.h
  • MPU_ACCESS_NOT_CACHEABLE : stm32wbxx_hal_cortex.h
  • MPU_ACCESS_NOT_SHAREABLE : stm32wbxx_hal_cortex.h
  • MPU_ACCESS_SHAREABLE : stm32wbxx_hal_cortex.h
  • MPU_HARDFAULT_NMI : stm32wbxx_hal_cortex.h
  • MPU_HFNMI_PRIVDEF : stm32wbxx_hal_cortex.h
  • MPU_HFNMI_PRIVDEF_NONE : stm32wbxx_hal_cortex.h
  • MPU_INSTRUCTION_ACCESS_DISABLE : stm32wbxx_hal_cortex.h
  • MPU_INSTRUCTION_ACCESS_ENABLE : stm32wbxx_hal_cortex.h
  • MPU_PRIVILEGED_DEFAULT : stm32wbxx_hal_cortex.h
  • MPU_REGION_DISABLE : stm32wbxx_hal_cortex.h
  • MPU_REGION_ENABLE : stm32wbxx_hal_cortex.h
  • MPU_REGION_FULL_ACCESS : stm32wbxx_hal_cortex.h
  • MPU_REGION_NO_ACCESS : stm32wbxx_hal_cortex.h
  • MPU_REGION_NUMBER0 : stm32wbxx_hal_cortex.h
  • MPU_REGION_NUMBER1 : stm32wbxx_hal_cortex.h
  • MPU_REGION_NUMBER2 : stm32wbxx_hal_cortex.h
  • MPU_REGION_NUMBER3 : stm32wbxx_hal_cortex.h
  • MPU_REGION_NUMBER4 : stm32wbxx_hal_cortex.h
  • MPU_REGION_NUMBER5 : stm32wbxx_hal_cortex.h
  • MPU_REGION_NUMBER6 : stm32wbxx_hal_cortex.h
  • MPU_REGION_NUMBER7 : stm32wbxx_hal_cortex.h
  • MPU_REGION_PRIV_RO : stm32wbxx_hal_cortex.h
  • MPU_REGION_PRIV_RO_URO : stm32wbxx_hal_cortex.h
  • MPU_REGION_PRIV_RW : stm32wbxx_hal_cortex.h
  • MPU_REGION_PRIV_RW_URO : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_128B : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_128KB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_128MB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_16KB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_16MB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_1GB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_1KB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_1MB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_256B : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_256KB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_256MB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_2GB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_2KB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_2MB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_32B : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_32KB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_32MB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_4GB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_4KB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_4MB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_512B : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_512KB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_512MB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_64B : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_64KB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_64MB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_8KB : stm32wbxx_hal_cortex.h
  • MPU_REGION_SIZE_8MB : stm32wbxx_hal_cortex.h
  • MPU_TEX_LEVEL0 : stm32wbxx_hal_cortex.h
  • MPU_TEX_LEVEL1 : stm32wbxx_hal_cortex.h
  • MPU_TEX_LEVEL2 : stm32wbxx_hal_cortex.h
  • MSI_TIMEOUT_VALUE : stm32wbxx_hal_rcc.c
  • MSI_VALUE : stm32wbxx_hal_conf.h
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

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- n -

  • NVIC_PRIORITYGROUP_0 : stm32wbxx_hal_cortex.h
  • NVIC_PRIORITYGROUP_1 : stm32wbxx_hal_cortex.h
  • NVIC_PRIORITYGROUP_2 : stm32wbxx_hal_cortex.h
  • NVIC_PRIORITYGROUP_3 : stm32wbxx_hal_cortex.h
  • NVIC_PRIORITYGROUP_4 : stm32wbxx_hal_cortex.h
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

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- o -

  • OB_AGC_TRIM_0 : stm32wbxx_hal_flash.h
  • OB_AGC_TRIM_1 : stm32wbxx_hal_flash.h
  • OB_AGC_TRIM_2 : stm32wbxx_hal_flash.h
  • OB_AGC_TRIM_3 : stm32wbxx_hal_flash.h
  • OB_AGC_TRIM_4 : stm32wbxx_hal_flash.h
  • OB_AGC_TRIM_5 : stm32wbxx_hal_flash.h
  • OB_AGC_TRIM_6 : stm32wbxx_hal_flash.h
  • OB_AGC_TRIM_7 : stm32wbxx_hal_flash.h
  • OB_BOOT0_FROM_OB : stm32wbxx_hal_flash.h
  • OB_BOOT0_FROM_PIN : stm32wbxx_hal_flash.h
  • OB_BOOT0_RESET : stm32wbxx_hal_flash.h
  • OB_BOOT0_SET : stm32wbxx_hal_flash.h
  • OB_BOOT1_SRAM : stm32wbxx_hal_flash.h
  • OB_BOOT1_SYSTEM : stm32wbxx_hal_flash.h
  • OB_BOR_LEVEL_0 : stm32wbxx_hal_flash.h
  • OB_BOR_LEVEL_1 : stm32wbxx_hal_flash.h
  • OB_BOR_LEVEL_2 : stm32wbxx_hal_flash.h
  • OB_BOR_LEVEL_3 : stm32wbxx_hal_flash.h
  • OB_BOR_LEVEL_4 : stm32wbxx_hal_flash.h
  • OB_C2_BOOT_FROM_FLASH : stm32wbxx_hal_flash.h
  • OB_C2_BOOT_FROM_SRAM : stm32wbxx_hal_flash.h
  • OB_IWDG_HW : stm32wbxx_hal_flash.h
  • OB_IWDG_STDBY_FREEZE : stm32wbxx_hal_flash.h
  • OB_IWDG_STDBY_RUN : stm32wbxx_hal_flash.h
  • OB_IWDG_STOP_FREEZE : stm32wbxx_hal_flash.h
  • OB_IWDG_STOP_RUN : stm32wbxx_hal_flash.h
  • OB_IWDG_SW : stm32wbxx_hal_flash.h
  • OB_PCROP_RDP_ERASE : stm32wbxx_hal_flash.h
  • OB_PCROP_RDP_NOT_ERASE : stm32wbxx_hal_flash.h
  • OB_PCROP_ZONE_A : stm32wbxx_hal_flash.h
  • OB_PCROP_ZONE_B : stm32wbxx_hal_flash.h
  • OB_RDP_LEVEL_0 : stm32wbxx_hal_flash.h
  • OB_RDP_LEVEL_1 : stm32wbxx_hal_flash.h
  • OB_RDP_LEVEL_2 : stm32wbxx_hal_flash.h
  • OB_SHUTDOWN_NORST : stm32wbxx_hal_flash.h
  • OB_SHUTDOWN_RST : stm32wbxx_hal_flash.h
  • OB_SRAM2_PARITY_DISABLE : stm32wbxx_hal_flash.h
  • OB_SRAM2_PARITY_ENABLE : stm32wbxx_hal_flash.h
  • OB_SRAM2_RST_ERASE : stm32wbxx_hal_flash.h
  • OB_SRAM2_RST_NOT_ERASE : stm32wbxx_hal_flash.h
  • OB_STANDBY_NORST : stm32wbxx_hal_flash.h
  • OB_STANDBY_RST : stm32wbxx_hal_flash.h
  • OB_STOP_NORST : stm32wbxx_hal_flash.h
  • OB_STOP_RST : stm32wbxx_hal_flash.h
  • OB_USER_AGC_TRIM : stm32wbxx_hal_flash.h
  • OB_USER_ALL : stm32wbxx_hal_flash.h
  • OB_USER_BOR_LEV : stm32wbxx_hal_flash.h
  • OB_USER_IWDG_STDBY : stm32wbxx_hal_flash.h
  • OB_USER_IWDG_STOP : stm32wbxx_hal_flash.h
  • OB_USER_IWDG_SW : stm32wbxx_hal_flash.h
  • OB_USER_nBOOT0 : stm32wbxx_hal_flash.h
  • OB_USER_nBOOT1 : stm32wbxx_hal_flash.h
  • OB_USER_nRST_SHDW : stm32wbxx_hal_flash.h
  • OB_USER_nRST_STDBY : stm32wbxx_hal_flash.h
  • OB_USER_nRST_STOP : stm32wbxx_hal_flash.h
  • OB_USER_nSWBOOT0 : stm32wbxx_hal_flash.h
  • OB_USER_SRAM2PE : stm32wbxx_hal_flash.h
  • OB_USER_SRAM2RST : stm32wbxx_hal_flash.h
  • OB_USER_WWDG_SW : stm32wbxx_hal_flash.h
  • OB_WRPAREA_BANK1_AREAA : stm32wbxx_hal_flash.h
  • OB_WRPAREA_BANK1_AREAB : stm32wbxx_hal_flash.h
  • OB_WWDG_HW : stm32wbxx_hal_flash.h
  • OB_WWDG_SW : stm32wbxx_hal_flash.h
  • OPTIONBYTE_ALL : stm32wbxx_hal_flash.h
  • OPTIONBYTE_C2_BOOT_VECT : stm32wbxx_hal_flash.h
  • OPTIONBYTE_IPCC_BUF_ADDR : stm32wbxx_hal_flash.h
  • OPTIONBYTE_PCROP : stm32wbxx_hal_flash.h
  • OPTIONBYTE_RDP : stm32wbxx_hal_flash.h
  • OPTIONBYTE_SECURE_MODE : stm32wbxx_hal_flash.h
  • OPTIONBYTE_USER : stm32wbxx_hal_flash.h
  • OPTIONBYTE_WRP : stm32wbxx_hal_flash.h
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

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- p -

  • PACKAGE_BASE_ADDRESS : stm32wbxx_ll_utils.h
  • PCD_CALC_BLK2 : stm32wbxx_hal_pcd.h
  • PCD_CALC_BLK32 : stm32wbxx_hal_pcd.h
  • PCD_CLEAR_EP_DBUF : stm32wbxx_hal_pcd.h
  • PCD_CLEAR_EP_KIND : stm32wbxx_hal_pcd.h
  • PCD_CLEAR_OUT_STATUS : stm32wbxx_hal_pcd.h
  • PCD_CLEAR_RX_DTOG : stm32wbxx_hal_pcd.h
  • PCD_CLEAR_RX_EP_CTR : stm32wbxx_hal_pcd.h
  • PCD_CLEAR_TX_DTOG : stm32wbxx_hal_pcd.h
  • PCD_CLEAR_TX_EP_CTR : stm32wbxx_hal_pcd.h
  • PCD_DBL_BUF : stm32wbxx_hal_pcd.h
  • PCD_ENDP0 : stm32wbxx_hal_pcd.h
  • PCD_ENDP1 : stm32wbxx_hal_pcd.h
  • PCD_ENDP2 : stm32wbxx_hal_pcd.h
  • PCD_ENDP3 : stm32wbxx_hal_pcd.h
  • PCD_ENDP4 : stm32wbxx_hal_pcd.h
  • PCD_ENDP5 : stm32wbxx_hal_pcd.h
  • PCD_ENDP6 : stm32wbxx_hal_pcd.h
  • PCD_ENDP7 : stm32wbxx_hal_pcd.h
  • PCD_EP0MPS_08 : stm32wbxx_hal_pcd.h
  • PCD_EP0MPS_16 : stm32wbxx_hal_pcd.h
  • PCD_EP0MPS_32 : stm32wbxx_hal_pcd.h
  • PCD_EP0MPS_64 : stm32wbxx_hal_pcd.h
  • PCD_EP_RX_CNT : stm32wbxx_hal_pcd.h
  • PCD_EP_TX_CNT : stm32wbxx_hal_pcd.h
  • PCD_FreeUserBuffer : stm32wbxx_hal_pcd.h
  • PCD_GET_ENDPOINT : stm32wbxx_hal_pcd.h
  • PCD_GET_EP_ADDRESS : stm32wbxx_hal_pcd.h
  • PCD_GET_EP_DBUF0_ADDR : stm32wbxx_hal_pcd.h
  • PCD_GET_EP_DBUF0_CNT : stm32wbxx_hal_pcd.h
  • PCD_GET_EP_DBUF1_ADDR : stm32wbxx_hal_pcd.h
  • PCD_GET_EP_DBUF1_CNT : stm32wbxx_hal_pcd.h
  • PCD_GET_EP_RX_ADDRESS : stm32wbxx_hal_pcd.h
  • PCD_GET_EP_RX_CNT : stm32wbxx_hal_pcd.h
  • PCD_GET_EP_RX_STALL_STATUS : stm32wbxx_hal_pcd.h
  • PCD_GET_EP_RX_STATUS : stm32wbxx_hal_pcd.h
  • PCD_GET_EP_TX_ADDRESS : stm32wbxx_hal_pcd.h
  • PCD_GET_EP_TX_CNT : stm32wbxx_hal_pcd.h
  • PCD_GET_EP_TX_STALL_STATUS : stm32wbxx_hal_pcd.h
  • PCD_GET_EP_TX_STATUS : stm32wbxx_hal_pcd.h
  • PCD_GET_EPTYPE : stm32wbxx_hal_pcd.h
  • PCD_MAX : stm32wbxx_hal_pcd.c
  • PCD_MIN : stm32wbxx_hal_pcd.c
  • PCD_PHY_EMBEDDED : stm32wbxx_hal_pcd.h
  • PCD_PHY_ULPI : stm32wbxx_hal_pcd.h
  • PCD_PHY_UTMI : stm32wbxx_hal_pcd.h
  • PCD_RX_DTOG : stm32wbxx_hal_pcd.h
  • PCD_SET_ENDPOINT : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_ADDRESS : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_CNT_RX_REG : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_DBUF : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_DBUF0_ADDR : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_DBUF0_CNT : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_DBUF1_ADDR : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_DBUF1_CNT : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_DBUF_ADDR : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_DBUF_CNT : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_KIND : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_RX_ADDRESS : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_RX_CNT : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_RX_DBUF0_CNT : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_RX_STATUS : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_RX_VALID : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_TX_ADDRESS : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_TX_CNT : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_TX_STATUS : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_TX_VALID : stm32wbxx_hal_pcd.h
  • PCD_SET_EP_TXRX_STATUS : stm32wbxx_hal_pcd.h
  • PCD_SET_EPTYPE : stm32wbxx_hal_pcd.h
  • PCD_SET_OUT_STATUS : stm32wbxx_hal_pcd.h
  • PCD_SNG_BUF : stm32wbxx_hal_pcd.h
  • PCD_SPEED_FULL : stm32wbxx_hal_pcd.h
  • PCD_TX_DTOG : stm32wbxx_hal_pcd.h
  • PKA_FLAG_ADDRERR : stm32wbxx_hal_pka.h
  • PKA_FLAG_PROCEND : stm32wbxx_hal_pka.h
  • PKA_FLAG_RAMERR : stm32wbxx_hal_pka.h
  • PKA_IT_ADDRERR : stm32wbxx_hal_pka.h
  • PKA_IT_PROCEND : stm32wbxx_hal_pka.h
  • PKA_IT_RAMERR : stm32wbxx_hal_pka.h
  • PKA_MODE_ARITHMETIC_ADD : stm32wbxx_hal_pka.h
  • PKA_MODE_ARITHMETIC_MUL : stm32wbxx_hal_pka.h
  • PKA_MODE_ARITHMETIC_SUB : stm32wbxx_hal_pka.h
  • PKA_MODE_COMPARISON : stm32wbxx_hal_pka.h
  • PKA_MODE_ECC_MUL : stm32wbxx_hal_pka.h
  • PKA_MODE_ECC_MUL_FAST_MODE : stm32wbxx_hal_pka.h
  • PKA_MODE_ECDSA_SIGNATURE : stm32wbxx_hal_pka.h
  • PKA_MODE_ECDSA_VERIFICATION : stm32wbxx_hal_pka.h
  • PKA_MODE_MODULAR_ADD : stm32wbxx_hal_pka.h
  • PKA_MODE_MODULAR_EXP : stm32wbxx_hal_pka.h
  • PKA_MODE_MODULAR_EXP_FAST_MODE : stm32wbxx_hal_pka.h
  • PKA_MODE_MODULAR_INV : stm32wbxx_hal_pka.h
  • PKA_MODE_MODULAR_RED : stm32wbxx_hal_pka.h
  • PKA_MODE_MODULAR_SUB : stm32wbxx_hal_pka.h
  • PKA_MODE_MONTGOMERY_MUL : stm32wbxx_hal_pka.h
  • PKA_MODE_MONTGOMERY_PARAM : stm32wbxx_hal_pka.h
  • PKA_MODE_POINT_CHECK : stm32wbxx_hal_pka.h
  • PKA_MODE_RSA_CRT_EXP : stm32wbxx_hal_pka.h
  • PKA_RAM_SIZE : stm32wbxx_hal_pka.c
  • PLL_TIMEOUT_VALUE : stm32wbxx_hal_rcc.c , stm32wbxx_hal_rcc_ex.c
  • PLLSAI1_TIMEOUT_VALUE : stm32wbxx_hal_rcc.c , stm32wbxx_hal_rcc_ex.c
  • PLLSOURCE_NONE : stm32wbxx_hal_rcc.c
  • PREFETCH_ENABLE : stm32wbxx_hal_conf.h
  • PRESCALER_TIMEOUT_VALUE : stm32wbxx_hal_rcc.c
  • PVD_FALLING_EDGE : stm32wbxx_hal_pwr.h
  • PVD_MODE_IT : stm32wbxx_hal_pwr.h
  • PVD_RISING_EDGE : stm32wbxx_hal_pwr.h
  • PVD_RISING_FALLING_EDGE : stm32wbxx_hal_pwr.h
  • PVM_FALLING_EDGE : stm32wbxx_hal_pwr_ex.h
  • PVM_MODE_EVT : stm32wbxx_hal_pwr_ex.h
  • PVM_MODE_IT : stm32wbxx_hal_pwr_ex.h
  • PVM_RISING_EDGE : stm32wbxx_hal_pwr_ex.h
  • PVM_RISING_FALLING_EDGE : stm32wbxx_hal_pwr_ex.h
  • PWR_BATTERY_CHARGING_DISABLE : stm32wbxx_hal_pwr_ex.h
  • PWR_BATTERY_CHARGING_ENABLE : stm32wbxx_hal_pwr_ex.h
  • PWR_BATTERY_CHARGING_RESISTOR_1_5 : stm32wbxx_hal_pwr_ex.h
  • PWR_BATTERY_CHARGING_RESISTOR_5 : stm32wbxx_hal_pwr_ex.h
  • PWR_BOR_SMPS_FORCE_BYPASS : stm32wbxx_hal_pwr_ex.h
  • PWR_BOR_SYSTEM_RESET : stm32wbxx_hal_pwr_ex.h
  • PWR_C2CR1_RESET_VALUE : stm32wbxx_hal_pwr.c , stm32wbxx_ll_pwr.c
  • PWR_C2CR3_RESET_VALUE : stm32wbxx_hal_pwr.c , stm32wbxx_ll_pwr.c
  • PWR_CORE_CPU1 : stm32wbxx_hal_pwr_ex.h
  • PWR_CORE_CPU2 : stm32wbxx_hal_pwr_ex.h
  • PWR_CR1_RESET_VALUE : stm32wbxx_ll_pwr.c , stm32wbxx_hal_pwr.c
  • PWR_CR2_RESET_VALUE : stm32wbxx_hal_pwr.c , stm32wbxx_ll_pwr.c
  • PWR_CR3_RESET_VALUE : stm32wbxx_hal_pwr.c , stm32wbxx_ll_pwr.c
  • PWR_CR4_RESET_VALUE : stm32wbxx_hal_pwr.c , stm32wbxx_ll_pwr.c
  • PWR_CR5_RESET_VALUE : stm32wbxx_hal_pwr.c , stm32wbxx_ll_pwr.c
  • PWR_EXTI_LINE_PVD : stm32wbxx_hal_pwr.h
  • PWR_EXTI_LINE_PVM1 : stm32wbxx_hal_pwr_ex.h
  • PWR_EXTI_LINE_PVM3 : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_802ACTI : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_BHWF : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_BLEACTI : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_C1DEEPSLEEP : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_C2DEEPSLEEP : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_C2SB : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_C2STOP : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_CRITICAL_RF_PHASE : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_FRCBYPI : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_HOLDC2I : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_PVDO : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_PVMO1 : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_PVMO3 : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_REGLPF : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_REGLPS : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_RFPHASEI : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_SB : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_SETTING_DELAY_US : stm32wbxx_hal_pwr_ex.c
  • PWR_FLAG_SMPSBYPF : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_SMPSRDYF : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_STOP : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_VOSF : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_WU : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_WUF1 : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_WUF2 : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_WUF3 : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_WUF4 : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_WUF5 : stm32wbxx_hal_pwr_ex.h
  • PWR_FLAG_WUFI : stm32wbxx_hal_pwr_ex.h
  • PWR_FLASHPD_LPRUN : stm32wbxx_hal_pwr_ex.h
  • PWR_FLASHPD_LPSLEEP : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_A : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_B : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_BIT_0 : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_BIT_1 : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_BIT_10 : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_BIT_11 : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_BIT_12 : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_BIT_13 : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_BIT_14 : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_BIT_15 : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_BIT_2 : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_BIT_3 : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_BIT_4 : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_BIT_5 : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_BIT_6 : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_BIT_7 : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_BIT_8 : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_BIT_9 : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_C : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_D : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_E : stm32wbxx_hal_pwr_ex.h
  • PWR_GPIO_H : stm32wbxx_hal_pwr_ex.h
  • PWR_LOWPOWERMODE_SHUTDOWN : stm32wbxx_hal_pwr.h
  • PWR_LOWPOWERMODE_STANDBY : stm32wbxx_hal_pwr.h
  • PWR_LOWPOWERMODE_STOP0 : stm32wbxx_hal_pwr.h
  • PWR_LOWPOWERMODE_STOP1 : stm32wbxx_hal_pwr.h
  • PWR_LOWPOWERMODE_STOP2 : stm32wbxx_hal_pwr.h
  • PWR_LOWPOWERREGULATOR_ON : stm32wbxx_hal_pwr.h
  • PWR_MAINREGULATOR_ON : stm32wbxx_hal_pwr.h
  • PWR_PDCRA_RESET_VALUE : stm32wbxx_hal_pwr.c , stm32wbxx_ll_pwr.c
  • PWR_PDCRB_RESET_VALUE : stm32wbxx_hal_pwr.c , stm32wbxx_ll_pwr.c
  • PWR_PDCRC_RESET_VALUE : stm32wbxx_ll_pwr.c , stm32wbxx_hal_pwr.c
  • PWR_PDCRD_RESET_VALUE : stm32wbxx_hal_pwr.c , stm32wbxx_ll_pwr.c
  • PWR_PDCRE_RESET_VALUE : stm32wbxx_hal_pwr.c , stm32wbxx_ll_pwr.c
  • PWR_PDCRH_RESET_VALUE : stm32wbxx_hal_pwr.c , stm32wbxx_ll_pwr.c
  • PWR_PIN_POLARITY_HIGH : stm32wbxx_hal_pwr_ex.h
  • PWR_PIN_POLARITY_LOW : stm32wbxx_hal_pwr_ex.h
  • PWR_PORTE_AVAILABLE_PINS : stm32wbxx_hal_pwr_ex.c
  • PWR_PORTH_AVAILABLE_PINS : stm32wbxx_hal_pwr_ex.c
  • PWR_PUCRA_RESET_VALUE : stm32wbxx_ll_pwr.c , stm32wbxx_hal_pwr.c
  • PWR_PUCRB_RESET_VALUE : stm32wbxx_ll_pwr.c , stm32wbxx_hal_pwr.c
  • PWR_PUCRC_RESET_VALUE : stm32wbxx_ll_pwr.c , stm32wbxx_hal_pwr.c
  • PWR_PUCRD_RESET_VALUE : stm32wbxx_ll_pwr.c , stm32wbxx_hal_pwr.c
  • PWR_PUCRE_RESET_VALUE : stm32wbxx_hal_pwr.c , stm32wbxx_ll_pwr.c
  • PWR_PUCRH_RESET_VALUE : stm32wbxx_ll_pwr.c , stm32wbxx_hal_pwr.c
  • PWR_PVD_MODE_IT_FALLING : stm32wbxx_hal_pwr.h
  • PWR_PVD_MODE_IT_RISING : stm32wbxx_hal_pwr.h
  • PWR_PVD_MODE_IT_RISING_FALLING : stm32wbxx_hal_pwr.h
  • PWR_PVD_MODE_NORMAL : stm32wbxx_hal_pwr.h
  • PWR_PVDLEVEL_0 : stm32wbxx_hal_pwr.h
  • PWR_PVDLEVEL_1 : stm32wbxx_hal_pwr.h
  • PWR_PVDLEVEL_2 : stm32wbxx_hal_pwr.h
  • PWR_PVDLEVEL_3 : stm32wbxx_hal_pwr.h
  • PWR_PVDLEVEL_4 : stm32wbxx_hal_pwr.h
  • PWR_PVDLEVEL_5 : stm32wbxx_hal_pwr.h
  • PWR_PVDLEVEL_6 : stm32wbxx_hal_pwr.h
  • PWR_PVDLEVEL_7 : stm32wbxx_hal_pwr.h
  • PWR_PVM_1 : stm32wbxx_hal_pwr_ex.h
  • PWR_PVM_3 : stm32wbxx_hal_pwr_ex.h
  • PWR_PVM_MODE_EVENT_FALLING : stm32wbxx_hal_pwr_ex.h
  • PWR_PVM_MODE_EVENT_RISING : stm32wbxx_hal_pwr_ex.h
  • PWR_PVM_MODE_EVENT_RISING_FALLING : stm32wbxx_hal_pwr_ex.h
  • PWR_PVM_MODE_IT_FALLING : stm32wbxx_hal_pwr_ex.h
  • PWR_PVM_MODE_IT_RISING : stm32wbxx_hal_pwr_ex.h
  • PWR_PVM_MODE_IT_RISING_FALLING : stm32wbxx_hal_pwr_ex.h
  • PWR_PVM_MODE_NORMAL : stm32wbxx_hal_pwr_ex.h
  • PWR_REGULATOR_VOLTAGE_SCALE1 : stm32wbxx_hal_pwr_ex.h
  • PWR_REGULATOR_VOLTAGE_SCALE2 : stm32wbxx_hal_pwr_ex.h
  • PWR_SLEEPENTRY_WFE : stm32wbxx_hal_pwr.h
  • PWR_SLEEPENTRY_WFI : stm32wbxx_hal_pwr.h
  • PWR_SMPS_BYPASS : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_OUTPUT_VOLTAGE_1V20 : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_OUTPUT_VOLTAGE_1V25 : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_OUTPUT_VOLTAGE_1V30 : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_OUTPUT_VOLTAGE_1V35 : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_OUTPUT_VOLTAGE_1V40 : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_OUTPUT_VOLTAGE_1V45 : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_OUTPUT_VOLTAGE_1V50 : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_OUTPUT_VOLTAGE_1V55 : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_OUTPUT_VOLTAGE_1V60 : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_OUTPUT_VOLTAGE_1V65 : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_OUTPUT_VOLTAGE_1V70 : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_OUTPUT_VOLTAGE_1V75 : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_OUTPUT_VOLTAGE_1V80 : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_OUTPUT_VOLTAGE_1V85 : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_OUTPUT_VOLTAGE_1V90 : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_STARTUP_CURRENT_100MA : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_STARTUP_CURRENT_120MA : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_STARTUP_CURRENT_140MA : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_STARTUP_CURRENT_160MA : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_STARTUP_CURRENT_180MA : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_STARTUP_CURRENT_200MA : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_STARTUP_CURRENT_220MA : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_STARTUP_CURRENT_80MA : stm32wbxx_hal_pwr_ex.h
  • PWR_SMPS_STEP_DOWN : stm32wbxx_hal_pwr_ex.h
  • PWR_STOPENTRY_WFE : stm32wbxx_hal_pwr.h
  • PWR_STOPENTRY_WFI : stm32wbxx_hal_pwr.h
  • PWR_WAKEUP_PIN1 : stm32wbxx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN1_HIGH : stm32wbxx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN1_LOW : stm32wbxx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN2 : stm32wbxx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN2_HIGH : stm32wbxx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN2_LOW : stm32wbxx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN3 : stm32wbxx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN3_HIGH : stm32wbxx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN3_LOW : stm32wbxx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN4 : stm32wbxx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN4_HIGH : stm32wbxx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN4_LOW : stm32wbxx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN5 : stm32wbxx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN5_HIGH : stm32wbxx_hal_pwr_ex.h
  • PWR_WAKEUP_PIN5_LOW : stm32wbxx_hal_pwr_ex.h
  • PWR_WAKEUPTARGET_ALL_CPU : stm32wbxx_hal_pwr_ex.h
  • PWR_WAKEUPTARGET_CPU1 : stm32wbxx_hal_pwr_ex.h
  • PWR_WAKEUPTARGET_CPU2 : stm32wbxx_hal_pwr_ex.h
  • PWR_WAKEUPTARGET_RF : stm32wbxx_hal_pwr_ex.h
  • PWR_WUP_POLARITY_SHIFT : stm32wbxx_hal_pwr_ex.h
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

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- q -

  • QSPI_ADDRESS_16_BITS : stm32wbxx_hal_qspi.h
  • QSPI_ADDRESS_1_LINE : stm32wbxx_hal_qspi.h
  • QSPI_ADDRESS_24_BITS : stm32wbxx_hal_qspi.h
  • QSPI_ADDRESS_2_LINES : stm32wbxx_hal_qspi.h
  • QSPI_ADDRESS_32_BITS : stm32wbxx_hal_qspi.h
  • QSPI_ADDRESS_4_LINES : stm32wbxx_hal_qspi.h
  • QSPI_ADDRESS_8_BITS : stm32wbxx_hal_qspi.h
  • QSPI_ADDRESS_NONE : stm32wbxx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_16_BITS : stm32wbxx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_1_LINE : stm32wbxx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_24_BITS : stm32wbxx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_2_LINES : stm32wbxx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_32_BITS : stm32wbxx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_4_LINES : stm32wbxx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_8_BITS : stm32wbxx_hal_qspi.h
  • QSPI_ALTERNATE_BYTES_NONE : stm32wbxx_hal_qspi.h
  • QSPI_AUTOMATIC_STOP_DISABLE : stm32wbxx_hal_qspi.h
  • QSPI_AUTOMATIC_STOP_ENABLE : stm32wbxx_hal_qspi.h
  • QSPI_CLOCK_MODE_0 : stm32wbxx_hal_qspi.h
  • QSPI_CLOCK_MODE_3 : stm32wbxx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_1_CYCLE : stm32wbxx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_2_CYCLE : stm32wbxx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_3_CYCLE : stm32wbxx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_4_CYCLE : stm32wbxx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_5_CYCLE : stm32wbxx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_6_CYCLE : stm32wbxx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_7_CYCLE : stm32wbxx_hal_qspi.h
  • QSPI_CS_HIGH_TIME_8_CYCLE : stm32wbxx_hal_qspi.h
  • QSPI_DATA_1_LINE : stm32wbxx_hal_qspi.h
  • QSPI_DATA_2_LINES : stm32wbxx_hal_qspi.h
  • QSPI_DATA_4_LINES : stm32wbxx_hal_qspi.h
  • QSPI_DATA_NONE : stm32wbxx_hal_qspi.h
  • QSPI_DDR_MODE_DISABLE : stm32wbxx_hal_qspi.h
  • QSPI_DDR_MODE_ENABLE : stm32wbxx_hal_qspi.h
  • QSPI_FLAG_BUSY : stm32wbxx_hal_qspi.h
  • QSPI_FLAG_FT : stm32wbxx_hal_qspi.h
  • QSPI_FLAG_SM : stm32wbxx_hal_qspi.h
  • QSPI_FLAG_TC : stm32wbxx_hal_qspi.h
  • QSPI_FLAG_TE : stm32wbxx_hal_qspi.h
  • QSPI_FLAG_TO : stm32wbxx_hal_qspi.h
  • QSPI_FUNCTIONAL_MODE_AUTO_POLLING : stm32wbxx_hal_qspi.c
  • QSPI_FUNCTIONAL_MODE_INDIRECT_READ : stm32wbxx_hal_qspi.c
  • QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE : stm32wbxx_hal_qspi.c
  • QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED : stm32wbxx_hal_qspi.c
  • QSPI_INSTRUCTION_1_LINE : stm32wbxx_hal_qspi.h
  • QSPI_INSTRUCTION_2_LINES : stm32wbxx_hal_qspi.h
  • QSPI_INSTRUCTION_4_LINES : stm32wbxx_hal_qspi.h
  • QSPI_INSTRUCTION_NONE : stm32wbxx_hal_qspi.h
  • QSPI_IT_FT : stm32wbxx_hal_qspi.h
  • QSPI_IT_SM : stm32wbxx_hal_qspi.h
  • QSPI_IT_TC : stm32wbxx_hal_qspi.h
  • QSPI_IT_TE : stm32wbxx_hal_qspi.h
  • QSPI_IT_TO : stm32wbxx_hal_qspi.h
  • QSPI_MATCH_MODE_AND : stm32wbxx_hal_qspi.h
  • QSPI_MATCH_MODE_OR : stm32wbxx_hal_qspi.h
  • QSPI_SAMPLE_SHIFTING_HALFCYCLE : stm32wbxx_hal_qspi.h
  • QSPI_SAMPLE_SHIFTING_NONE : stm32wbxx_hal_qspi.h
  • QSPI_SIOO_INST_EVERY_CMD : stm32wbxx_hal_qspi.h
  • QSPI_SIOO_INST_ONLY_FIRST_CMD : stm32wbxx_hal_qspi.h
  • QSPI_TIMEOUT_COUNTER_DISABLE : stm32wbxx_hal_qspi.h
  • QSPI_TIMEOUT_COUNTER_ENABLE : stm32wbxx_hal_qspi.h
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

  • File List
  • Globals
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  • Functions
  • Variables
  • Typedefs
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- r -

  • RCC_ADCCLKSOURCE_NONE : stm32wbxx_hal_rcc_ex.h
  • RCC_ADCCLKSOURCE_PLL : stm32wbxx_hal_rcc_ex.h
  • RCC_ADCCLKSOURCE_PLLSAI1 : stm32wbxx_hal_rcc_ex.h
  • RCC_ADCCLKSOURCE_SYSCLK : stm32wbxx_hal_rcc_ex.h
  • RCC_CLOCKTYPE_HCLK : stm32wbxx_hal_rcc.h
  • RCC_CLOCKTYPE_HCLK2 : stm32wbxx_hal_rcc.h
  • RCC_CLOCKTYPE_HCLK4 : stm32wbxx_hal_rcc.h
  • RCC_CLOCKTYPE_PCLK1 : stm32wbxx_hal_rcc.h
  • RCC_CLOCKTYPE_PCLK2 : stm32wbxx_hal_rcc.h
  • RCC_CLOCKTYPE_SYSCLK : stm32wbxx_hal_rcc.h
  • RCC_CRS_ERRORLIMIT_DEFAULT : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_FLAG_ERR : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_FLAG_ERROR_MASK : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_FLAG_ESYNC : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCERR : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCMISS : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCOK : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_FLAG_SYNCWARN : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_FLAG_TRIMOVF : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_FREQERRORDIR_DOWN : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_FREQERRORDIR_UP : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_HSI48CALIBRATION_DEFAULT : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_IT_ERR : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_IT_ERROR_MASK : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_IT_ESYNC : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCERR : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCMISS : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCOK : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_IT_SYNCWARN : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_IT_TRIMOVF : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_NONE : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_RELOADVALUE_DEFAULT : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV1 : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV128 : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV16 : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV2 : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV32 : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV4 : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV64 : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_SYNC_DIV8 : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_SYNC_POLARITY_FALLING : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_SYNC_POLARITY_RISING : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_SYNC_SOURCE_GPIO : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_SYNC_SOURCE_LSE : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_SYNC_SOURCE_USB : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_SYNCERR : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_SYNCMISS : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_SYNCOK : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_SYNCWARN : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_TIMEOUT : stm32wbxx_hal_rcc_ex.h
  • RCC_CRS_TRIMOVF : stm32wbxx_hal_rcc_ex.h
  • RCC_DBP_TIMEOUT_VALUE : stm32wbxx_hal_rcc.h
  • RCC_EXTI_LINE_LSECSS : stm32wbxx_hal_rcc_ex.h
  • RCC_FLAG_BORRST : stm32wbxx_hal_rcc.h
  • RCC_FLAG_HSERDY : stm32wbxx_hal_rcc.h
  • RCC_FLAG_HSI48RDY : stm32wbxx_hal_rcc.h
  • RCC_FLAG_HSIRDY : stm32wbxx_hal_rcc.h
  • RCC_FLAG_IWDGRST : stm32wbxx_hal_rcc.h
  • RCC_FLAG_LPWRRST : stm32wbxx_hal_rcc.h
  • RCC_FLAG_LSECSSD : stm32wbxx_hal_rcc.h
  • RCC_FLAG_LSERDY : stm32wbxx_hal_rcc.h
  • RCC_FLAG_LSI1RDY : stm32wbxx_hal_rcc.h
  • RCC_FLAG_LSI2RDY : stm32wbxx_hal_rcc.h
  • RCC_FLAG_MASK : stm32wbxx_hal_rcc.h
  • RCC_FLAG_MSIRDY : stm32wbxx_hal_rcc.h
  • RCC_FLAG_OBLRST : stm32wbxx_hal_rcc.h
  • RCC_FLAG_PINRST : stm32wbxx_hal_rcc.h
  • RCC_FLAG_PLLRDY : stm32wbxx_hal_rcc.h
  • RCC_FLAG_PLLSAI1RDY : stm32wbxx_hal_rcc.h
  • RCC_FLAG_SFTRST : stm32wbxx_hal_rcc.h
  • RCC_FLAG_WWDGRST : stm32wbxx_hal_rcc.h
  • RCC_HCLK5SOURCE_HSE : stm32wbxx_hal_rcc_ex.h
  • RCC_HCLK5SOURCE_HSI : stm32wbxx_hal_rcc_ex.h
  • RCC_HCLK_DIV1 : stm32wbxx_hal_rcc.h
  • RCC_HCLK_DIV16 : stm32wbxx_hal_rcc.h
  • RCC_HCLK_DIV2 : stm32wbxx_hal_rcc.h
  • RCC_HCLK_DIV4 : stm32wbxx_hal_rcc.h
  • RCC_HCLK_DIV8 : stm32wbxx_hal_rcc.h
  • RCC_HSE_BYPASS : stm32wbxx_hal_rcc.h
  • RCC_HSE_CURRENTMAX_0 : stm32wbxx_hal_rcc.h
  • RCC_HSE_CURRENTMAX_1 : stm32wbxx_hal_rcc.h
  • RCC_HSE_CURRENTMAX_2 : stm32wbxx_hal_rcc.h
  • RCC_HSE_CURRENTMAX_3 : stm32wbxx_hal_rcc.h
  • RCC_HSE_CURRENTMAX_4 : stm32wbxx_hal_rcc.h
  • RCC_HSE_CURRENTMAX_5 : stm32wbxx_hal_rcc.h
  • RCC_HSE_CURRENTMAX_6 : stm32wbxx_hal_rcc.h
  • RCC_HSE_CURRENTMAX_7 : stm32wbxx_hal_rcc.h
  • RCC_HSE_OFF : stm32wbxx_hal_rcc.h
  • RCC_HSE_ON : stm32wbxx_hal_rcc.h
  • RCC_HSEAMPTHRESHOLD_1_2 : stm32wbxx_hal_rcc.h
  • RCC_HSEAMPTHRESHOLD_3_4 : stm32wbxx_hal_rcc.h
  • RCC_HSI48_OFF : stm32wbxx_hal_rcc.h
  • RCC_HSI48_ON : stm32wbxx_hal_rcc.h
  • RCC_HSI_OFF : stm32wbxx_hal_rcc.h
  • RCC_HSI_ON : stm32wbxx_hal_rcc.h
  • RCC_HSICALIBRATION_DEFAULT : stm32wbxx_hal_rcc.h
  • RCC_I2C1CLKSOURCE_HSI : stm32wbxx_hal_rcc_ex.h
  • RCC_I2C1CLKSOURCE_PCLK1 : stm32wbxx_hal_rcc_ex.h
  • RCC_I2C1CLKSOURCE_SYSCLK : stm32wbxx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_HSI : stm32wbxx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_PCLK1 : stm32wbxx_hal_rcc_ex.h
  • RCC_I2C3CLKSOURCE_SYSCLK : stm32wbxx_hal_rcc_ex.h
  • RCC_IT_HSECSS : stm32wbxx_hal_rcc.h
  • RCC_IT_HSERDY : stm32wbxx_hal_rcc.h
  • RCC_IT_HSI48RDY : stm32wbxx_hal_rcc.h
  • RCC_IT_HSIRDY : stm32wbxx_hal_rcc.h
  • RCC_IT_LSECSS : stm32wbxx_hal_rcc.h
  • RCC_IT_LSERDY : stm32wbxx_hal_rcc.h
  • RCC_IT_LSI1RDY : stm32wbxx_hal_rcc.h
  • RCC_IT_LSI2RDY : stm32wbxx_hal_rcc.h
  • RCC_IT_MSIRDY : stm32wbxx_hal_rcc.h
  • RCC_IT_PLLRDY : stm32wbxx_hal_rcc.h
  • RCC_IT_PLLSAI1RDY : stm32wbxx_hal_rcc.h
  • RCC_LPTIM1CLKSOURCE_HSI : stm32wbxx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_LSE : stm32wbxx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_LSI : stm32wbxx_hal_rcc_ex.h
  • RCC_LPTIM1CLKSOURCE_PCLK1 : stm32wbxx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_HSI : stm32wbxx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_LSE : stm32wbxx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_LSI : stm32wbxx_hal_rcc_ex.h
  • RCC_LPTIM2CLKSOURCE_PCLK1 : stm32wbxx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_HSI : stm32wbxx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_LSE : stm32wbxx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_PCLK1 : stm32wbxx_hal_rcc_ex.h
  • RCC_LPUART1CLKSOURCE_SYSCLK : stm32wbxx_hal_rcc_ex.h
  • RCC_LSCO1 : stm32wbxx_hal_rcc_ex.h
  • RCC_LSCO2 : stm32wbxx_hal_rcc_ex.h
  • RCC_LSCO3 : stm32wbxx_hal_rcc_ex.h
  • RCC_LSCOSOURCE_LSE : stm32wbxx_hal_rcc_ex.h
  • RCC_LSCOSOURCE_LSI : stm32wbxx_hal_rcc_ex.h
  • RCC_LSE_BYPASS : stm32wbxx_hal_rcc.h
  • RCC_LSE_OFF : stm32wbxx_hal_rcc.h
  • RCC_LSE_ON : stm32wbxx_hal_rcc.h
  • RCC_LSE_TIMEOUT_VALUE : stm32wbxx_hal_rcc.h
  • RCC_LSEDRIVE_HIGH : stm32wbxx_hal_rcc.h
  • RCC_LSEDRIVE_LOW : stm32wbxx_hal_rcc.h
  • RCC_LSEDRIVE_MEDIUMHIGH : stm32wbxx_hal_rcc.h
  • RCC_LSEDRIVE_MEDIUMLOW : stm32wbxx_hal_rcc.h
  • RCC_LSI_OFF : stm32wbxx_hal_rcc.h
  • RCC_LSI_ON : stm32wbxx_hal_rcc.h
  • RCC_MCO : stm32wbxx_hal_rcc.h
  • RCC_MCO1 : stm32wbxx_hal_rcc.h
  • RCC_MCO1SOURCE_HSE : stm32wbxx_hal_rcc.h
  • RCC_MCO1SOURCE_HSE_BEFORE_STAB : stm32wbxx_hal_rcc.h
  • RCC_MCO1SOURCE_HSI : stm32wbxx_hal_rcc.h
  • RCC_MCO1SOURCE_HSI48 : stm32wbxx_hal_rcc.h
  • RCC_MCO1SOURCE_LSE : stm32wbxx_hal_rcc.h
  • RCC_MCO1SOURCE_LSI1 : stm32wbxx_hal_rcc.h
  • RCC_MCO1SOURCE_LSI2 : stm32wbxx_hal_rcc.h
  • RCC_MCO1SOURCE_MSI : stm32wbxx_hal_rcc.h
  • RCC_MCO1SOURCE_NOCLOCK : stm32wbxx_hal_rcc.h
  • RCC_MCO1SOURCE_PLLCLK : stm32wbxx_hal_rcc.h
  • RCC_MCO1SOURCE_SYSCLK : stm32wbxx_hal_rcc.h
  • RCC_MCO2 : stm32wbxx_hal_rcc.h
  • RCC_MCO3 : stm32wbxx_hal_rcc.h
  • RCC_MCODIV_1 : stm32wbxx_hal_rcc.h
  • RCC_MCODIV_16 : stm32wbxx_hal_rcc.h
  • RCC_MCODIV_2 : stm32wbxx_hal_rcc.h
  • RCC_MCODIV_4 : stm32wbxx_hal_rcc.h
  • RCC_MCODIV_8 : stm32wbxx_hal_rcc.h
  • RCC_MSI_OFF : stm32wbxx_hal_rcc.h
  • RCC_MSI_ON : stm32wbxx_hal_rcc.h
  • RCC_MSICALIBRATION_DEFAULT : stm32wbxx_hal_rcc.h
  • RCC_MSIRANGE_0 : stm32wbxx_hal_rcc.h
  • RCC_MSIRANGE_1 : stm32wbxx_hal_rcc.h
  • RCC_MSIRANGE_10 : stm32wbxx_hal_rcc.h
  • RCC_MSIRANGE_11 : stm32wbxx_hal_rcc.h
  • RCC_MSIRANGE_2 : stm32wbxx_hal_rcc.h
  • RCC_MSIRANGE_3 : stm32wbxx_hal_rcc.h
  • RCC_MSIRANGE_4 : stm32wbxx_hal_rcc.h
  • RCC_MSIRANGE_5 : stm32wbxx_hal_rcc.h
  • RCC_MSIRANGE_6 : stm32wbxx_hal_rcc.h
  • RCC_MSIRANGE_7 : stm32wbxx_hal_rcc.h
  • RCC_MSIRANGE_8 : stm32wbxx_hal_rcc.h
  • RCC_MSIRANGE_9 : stm32wbxx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSE : stm32wbxx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSI : stm32wbxx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSI48 : stm32wbxx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSE : stm32wbxx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSI1 : stm32wbxx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSI2 : stm32wbxx_hal_rcc.h
  • RCC_OSCILLATORTYPE_MSI : stm32wbxx_hal_rcc.h
  • RCC_OSCILLATORTYPE_NONE : stm32wbxx_hal_rcc.h
  • RCC_PERIPHCLK_ADC : stm32wbxx_hal_rcc_ex.h
  • RCC_PERIPHCLK_CLK48SEL : stm32wbxx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C1 : stm32wbxx_hal_rcc_ex.h
  • RCC_PERIPHCLK_I2C3 : stm32wbxx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPTIM1 : stm32wbxx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPTIM2 : stm32wbxx_hal_rcc_ex.h
  • RCC_PERIPHCLK_LPUART1 : stm32wbxx_hal_rcc_ex.h
  • RCC_PERIPHCLK_RFWAKEUP : stm32wbxx_hal_rcc_ex.h
  • RCC_PERIPHCLK_RNG : stm32wbxx_hal_rcc_ex.h
  • RCC_PERIPHCLK_RTC : stm32wbxx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SAI1 : stm32wbxx_hal_rcc_ex.h
  • RCC_PERIPHCLK_SMPS : stm32wbxx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USART1 : stm32wbxx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USB : stm32wbxx_hal_rcc_ex.h
  • RCC_PLL_ADCCLK : stm32wbxx_hal_rcc.h
  • RCC_PLL_NONE : stm32wbxx_hal_rcc.h
  • RCC_PLL_OFF : stm32wbxx_hal_rcc.h
  • RCC_PLL_ON : stm32wbxx_hal_rcc.h
  • RCC_PLL_OSCSOURCE_CONFIG : stm32wbxx_hal_rcc.c
  • RCC_PLL_RNGCLK : stm32wbxx_hal_rcc.h
  • RCC_PLL_SAI1CLK : stm32wbxx_hal_rcc.h
  • RCC_PLL_SYSCLK : stm32wbxx_hal_rcc.h
  • RCC_PLL_USBCLK : stm32wbxx_hal_rcc.h
  • RCC_PLLM_DIV1 : stm32wbxx_hal_rcc.h
  • RCC_PLLM_DIV2 : stm32wbxx_hal_rcc.h
  • RCC_PLLM_DIV3 : stm32wbxx_hal_rcc.h
  • RCC_PLLM_DIV4 : stm32wbxx_hal_rcc.h
  • RCC_PLLM_DIV5 : stm32wbxx_hal_rcc.h
  • RCC_PLLM_DIV6 : stm32wbxx_hal_rcc.h
  • RCC_PLLM_DIV7 : stm32wbxx_hal_rcc.h
  • RCC_PLLM_DIV8 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV10 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV11 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV12 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV13 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV14 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV15 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV16 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV17 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV18 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV19 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV2 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV20 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV21 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV22 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV23 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV24 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV25 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV26 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV27 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV28 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV29 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV3 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV30 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV31 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV32 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV4 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV5 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV6 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV7 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV8 : stm32wbxx_hal_rcc.h
  • RCC_PLLP_DIV9 : stm32wbxx_hal_rcc.h
  • RCC_PLLQ_DIV2 : stm32wbxx_hal_rcc.h
  • RCC_PLLQ_DIV3 : stm32wbxx_hal_rcc.h
  • RCC_PLLQ_DIV4 : stm32wbxx_hal_rcc.h
  • RCC_PLLQ_DIV5 : stm32wbxx_hal_rcc.h
  • RCC_PLLQ_DIV6 : stm32wbxx_hal_rcc.h
  • RCC_PLLQ_DIV7 : stm32wbxx_hal_rcc.h
  • RCC_PLLQ_DIV8 : stm32wbxx_hal_rcc.h
  • RCC_PLLR_DIV2 : stm32wbxx_hal_rcc.h
  • RCC_PLLR_DIV3 : stm32wbxx_hal_rcc.h
  • RCC_PLLR_DIV4 : stm32wbxx_hal_rcc.h
  • RCC_PLLR_DIV5 : stm32wbxx_hal_rcc.h
  • RCC_PLLR_DIV6 : stm32wbxx_hal_rcc.h
  • RCC_PLLR_DIV7 : stm32wbxx_hal_rcc.h
  • RCC_PLLR_DIV8 : stm32wbxx_hal_rcc.h
  • RCC_PLLSAI1_ADCCLK : stm32wbxx_hal_rcc.h
  • RCC_PLLSAI1_SAI1CLK : stm32wbxx_hal_rcc.h
  • RCC_PLLSAI1_USBCLK : stm32wbxx_hal_rcc.h
  • RCC_PLLSOURCE_HSE : stm32wbxx_hal_rcc.h
  • RCC_PLLSOURCE_HSI : stm32wbxx_hal_rcc.h
  • RCC_PLLSOURCE_MSI : stm32wbxx_hal_rcc.h
  • RCC_PLLSOURCE_NONE : stm32wbxx_hal_rcc.h
  • RCC_RFWKPCLKSOURCE_HSE_DIV1024 : stm32wbxx_hal_rcc_ex.h
  • RCC_RFWKPCLKSOURCE_LSE : stm32wbxx_hal_rcc_ex.h
  • RCC_RFWKPCLKSOURCE_LSI : stm32wbxx_hal_rcc_ex.h
  • RCC_RFWKPCLKSOURCE_NONE : stm32wbxx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_CLK48 : stm32wbxx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_HSI48 : stm32wbxx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_LSE : stm32wbxx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_LSI : stm32wbxx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_MSI : stm32wbxx_hal_rcc_ex.h
  • RCC_RNGCLKSOURCE_PLL : stm32wbxx_hal_rcc_ex.h
  • RCC_RTCCLKSOURCE_HSE_DIV32 : stm32wbxx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSE : stm32wbxx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSI : stm32wbxx_hal_rcc.h
  • RCC_RTCCLKSOURCE_NONE : stm32wbxx_hal_rcc.h
  • RCC_SAI1CLKSOURCE_HSI : stm32wbxx_hal_rcc_ex.h
  • RCC_SAI1CLKSOURCE_PIN : stm32wbxx_hal_rcc_ex.h
  • RCC_SAI1CLKSOURCE_PLL : stm32wbxx_hal_rcc_ex.h
  • RCC_SAI1CLKSOURCE_PLLSAI1 : stm32wbxx_hal_rcc_ex.h
  • RCC_SMPSCLKDIV_RANGE0 : stm32wbxx_hal_rcc_ex.h
  • RCC_SMPSCLKDIV_RANGE1 : stm32wbxx_hal_rcc_ex.h
  • RCC_SMPSCLKDIV_RANGE2 : stm32wbxx_hal_rcc_ex.h
  • RCC_SMPSCLKDIV_RANGE3 : stm32wbxx_hal_rcc_ex.h
  • RCC_SMPSCLKSOURCE_HSE : stm32wbxx_hal_rcc_ex.h
  • RCC_SMPSCLKSOURCE_HSI : stm32wbxx_hal_rcc_ex.h
  • RCC_SMPSCLKSOURCE_MSI : stm32wbxx_hal_rcc_ex.h
  • RCC_SMPSCLKSOURCE_STATUS_HSE : stm32wbxx_hal_rcc_ex.h
  • RCC_SMPSCLKSOURCE_STATUS_HSI : stm32wbxx_hal_rcc_ex.h
  • RCC_SMPSCLKSOURCE_STATUS_MSI : stm32wbxx_hal_rcc_ex.h
  • RCC_STOP_WAKEUPCLOCK_HSI : stm32wbxx_hal_rcc.h
  • RCC_STOP_WAKEUPCLOCK_MSI : stm32wbxx_hal_rcc.h
  • RCC_SYSCLK_DIV1 : stm32wbxx_hal_rcc.h
  • RCC_SYSCLK_DIV10 : stm32wbxx_hal_rcc.h
  • RCC_SYSCLK_DIV128 : stm32wbxx_hal_rcc.h
  • RCC_SYSCLK_DIV16 : stm32wbxx_hal_rcc.h
  • RCC_SYSCLK_DIV2 : stm32wbxx_hal_rcc.h
  • RCC_SYSCLK_DIV256 : stm32wbxx_hal_rcc.h
  • RCC_SYSCLK_DIV3 : stm32wbxx_hal_rcc.h
  • RCC_SYSCLK_DIV32 : stm32wbxx_hal_rcc.h
  • RCC_SYSCLK_DIV4 : stm32wbxx_hal_rcc.h
  • RCC_SYSCLK_DIV5 : stm32wbxx_hal_rcc.h
  • RCC_SYSCLK_DIV512 : stm32wbxx_hal_rcc.h
  • RCC_SYSCLK_DIV6 : stm32wbxx_hal_rcc.h
  • RCC_SYSCLK_DIV64 : stm32wbxx_hal_rcc.h
  • RCC_SYSCLK_DIV8 : stm32wbxx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSE : stm32wbxx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSI : stm32wbxx_hal_rcc.h
  • RCC_SYSCLKSOURCE_MSI : stm32wbxx_hal_rcc.h
  • RCC_SYSCLKSOURCE_PLLCLK : stm32wbxx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_HSE : stm32wbxx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_HSI : stm32wbxx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_MSI : stm32wbxx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_PLLCLK : stm32wbxx_hal_rcc.h
  • RCC_USART1CLKSOURCE_HSI : stm32wbxx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_LSE : stm32wbxx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_PCLK2 : stm32wbxx_hal_rcc_ex.h
  • RCC_USART1CLKSOURCE_SYSCLK : stm32wbxx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_HSI48 : stm32wbxx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_MSI : stm32wbxx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_PLL : stm32wbxx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_PLLSAI1 : stm32wbxx_hal_rcc_ex.h
  • RISING_EDGE : stm32wbxx_hal_gpio.c
  • RNG_CED_DISABLE : stm32wbxx_hal_rng.h
  • RNG_CED_ENABLE : stm32wbxx_hal_rng.h
  • RNG_FLAG_CECS : stm32wbxx_hal_rng.h
  • RNG_FLAG_DRDY : stm32wbxx_hal_rng.h
  • RNG_FLAG_SECS : stm32wbxx_hal_rng.h
  • RNG_IT_CEI : stm32wbxx_hal_rng.h
  • RNG_IT_DRDY : stm32wbxx_hal_rng.h
  • RNG_IT_SEI : stm32wbxx_hal_rng.h
  • RNG_TIMEOUT_VALUE : stm32wbxx_hal_rng.c
  • RTC_ALARM_A : stm32wbxx_hal_rtc.h
  • RTC_ALARM_B : stm32wbxx_hal_rtc.h
  • RTC_ALARMDATEWEEKDAYSEL_DATE : stm32wbxx_hal_rtc.h
  • RTC_ALARMDATEWEEKDAYSEL_WEEKDAY : stm32wbxx_hal_rtc.h
  • RTC_ALARMMASK_ALL : stm32wbxx_hal_rtc.h
  • RTC_ALARMMASK_DATEWEEKDAY : stm32wbxx_hal_rtc.h
  • RTC_ALARMMASK_HOURS : stm32wbxx_hal_rtc.h
  • RTC_ALARMMASK_MINUTES : stm32wbxx_hal_rtc.h
  • RTC_ALARMMASK_NONE : stm32wbxx_hal_rtc.h
  • RTC_ALARMMASK_SECONDS : stm32wbxx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_ALL : stm32wbxx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_NONE : stm32wbxx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14 : stm32wbxx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_1 : stm32wbxx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_10 : stm32wbxx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_11 : stm32wbxx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_12 : stm32wbxx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_13 : stm32wbxx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_2 : stm32wbxx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_3 : stm32wbxx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_4 : stm32wbxx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_5 : stm32wbxx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_6 : stm32wbxx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_7 : stm32wbxx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_8 : stm32wbxx_hal_rtc.h
  • RTC_ALARMSUBSECONDMASK_SS14_9 : stm32wbxx_hal_rtc.h
  • RTC_ALL_TAMPER_INTERRUPT : stm32wbxx_hal_rtc_ex.h
  • RTC_ASYNCH_PRESC_DEFAULT : stm32wbxx_ll_rtc.c
  • RTC_BKP_DR0 : stm32wbxx_hal_rtc_ex.h
  • RTC_BKP_DR1 : stm32wbxx_hal_rtc_ex.h
  • RTC_BKP_DR10 : stm32wbxx_hal_rtc_ex.h
  • RTC_BKP_DR11 : stm32wbxx_hal_rtc_ex.h
  • RTC_BKP_DR12 : stm32wbxx_hal_rtc_ex.h
  • RTC_BKP_DR13 : stm32wbxx_hal_rtc_ex.h
  • RTC_BKP_DR14 : stm32wbxx_hal_rtc_ex.h
  • RTC_BKP_DR15 : stm32wbxx_hal_rtc_ex.h
  • RTC_BKP_DR16 : stm32wbxx_hal_rtc_ex.h
  • RTC_BKP_DR17 : stm32wbxx_hal_rtc_ex.h
  • RTC_BKP_DR18 : stm32wbxx_hal_rtc_ex.h
  • RTC_BKP_DR19 : stm32wbxx_hal_rtc_ex.h
  • RTC_BKP_DR2 : stm32wbxx_hal_rtc_ex.h
  • RTC_BKP_DR3 : stm32wbxx_hal_rtc_ex.h
  • RTC_BKP_DR4 : stm32wbxx_hal_rtc_ex.h
  • RTC_BKP_DR5 : stm32wbxx_hal_rtc_ex.h
  • RTC_BKP_DR6 : stm32wbxx_hal_rtc_ex.h
  • RTC_BKP_DR7 : stm32wbxx_hal_rtc_ex.h
  • RTC_BKP_DR8 : stm32wbxx_hal_rtc_ex.h
  • RTC_BKP_DR9 : stm32wbxx_hal_rtc_ex.h
  • RTC_CALIBOUTPUT_1HZ : stm32wbxx_hal_rtc_ex.h
  • RTC_CALIBOUTPUT_512HZ : stm32wbxx_hal_rtc_ex.h
  • RTC_DAYLIGHTSAVING_ADD1H : stm32wbxx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_NONE : stm32wbxx_hal_rtc.h
  • RTC_DAYLIGHTSAVING_SUB1H : stm32wbxx_hal_rtc.h
  • RTC_DR_RESERVED_MASK : stm32wbxx_hal_rtc.h
  • RTC_EXTI_LINE_ALARM_EVENT : stm32wbxx_hal_rtc.h
  • RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT : stm32wbxx_hal_rtc_ex.h
  • RTC_EXTI_LINE_WAKEUPTIMER_EVENT : stm32wbxx_hal_rtc_ex.h
  • RTC_FLAG_ALRAF : stm32wbxx_hal_rtc.h
  • RTC_FLAG_ALRAWF : stm32wbxx_hal_rtc.h
  • RTC_FLAG_ALRBF : stm32wbxx_hal_rtc.h
  • RTC_FLAG_ALRBWF : stm32wbxx_hal_rtc.h
  • RTC_FLAG_INITF : stm32wbxx_hal_rtc.h
  • RTC_FLAG_INITS : stm32wbxx_hal_rtc.h
  • RTC_FLAG_ITSF : stm32wbxx_hal_rtc.h
  • RTC_FLAG_RECALPF : stm32wbxx_hal_rtc.h
  • RTC_FLAG_RSF : stm32wbxx_hal_rtc.h
  • RTC_FLAG_SHPF : stm32wbxx_hal_rtc.h
  • RTC_FLAG_TAMP1F : stm32wbxx_hal_rtc.h
  • RTC_FLAG_TAMP2F : stm32wbxx_hal_rtc.h
  • RTC_FLAG_TAMP3F : stm32wbxx_hal_rtc_ex.h
  • RTC_FLAG_TSF : stm32wbxx_hal_rtc.h
  • RTC_FLAG_TSOVF : stm32wbxx_hal_rtc.h
  • RTC_FLAG_WUTF : stm32wbxx_hal_rtc.h
  • RTC_FLAG_WUTWF : stm32wbxx_hal_rtc.h
  • RTC_FLAGS_MASK : stm32wbxx_hal_rtc_ex.h
  • RTC_FORMAT_BCD : stm32wbxx_hal_rtc.h
  • RTC_FORMAT_BIN : stm32wbxx_hal_rtc.h
  • RTC_HOURFORMAT12_AM : stm32wbxx_hal_rtc.h
  • RTC_HOURFORMAT12_PM : stm32wbxx_hal_rtc.h
  • RTC_HOURFORMAT_12 : stm32wbxx_hal_rtc.h
  • RTC_HOURFORMAT_24 : stm32wbxx_hal_rtc.h
  • RTC_INIT_MASK : stm32wbxx_hal_rtc.h
  • RTC_INITMODE_TIMEOUT : stm32wbxx_ll_rtc.c
  • RTC_IT_ALRA : stm32wbxx_hal_rtc.h
  • RTC_IT_ALRB : stm32wbxx_hal_rtc.h
  • RTC_IT_TAMP : stm32wbxx_hal_rtc.h
  • RTC_IT_TAMP1 : stm32wbxx_hal_rtc.h
  • RTC_IT_TAMP2 : stm32wbxx_hal_rtc.h
  • RTC_IT_TAMP3 : stm32wbxx_hal_rtc_ex.h
  • RTC_IT_TS : stm32wbxx_hal_rtc.h
  • RTC_IT_WUT : stm32wbxx_hal_rtc.h
  • RTC_MONTH_APRIL : stm32wbxx_hal_rtc.h
  • RTC_MONTH_AUGUST : stm32wbxx_hal_rtc.h
  • RTC_MONTH_DECEMBER : stm32wbxx_hal_rtc.h
  • RTC_MONTH_FEBRUARY : stm32wbxx_hal_rtc.h
  • RTC_MONTH_JANUARY : stm32wbxx_hal_rtc.h
  • RTC_MONTH_JULY : stm32wbxx_hal_rtc.h
  • RTC_MONTH_JUNE : stm32wbxx_hal_rtc.h
  • RTC_MONTH_MARCH : stm32wbxx_hal_rtc.h
  • RTC_MONTH_MAY : stm32wbxx_hal_rtc.h
  • RTC_MONTH_NOVEMBER : stm32wbxx_hal_rtc.h
  • RTC_MONTH_OCTOBER : stm32wbxx_hal_rtc.h
  • RTC_MONTH_SEPTEMBER : stm32wbxx_hal_rtc.h
  • RTC_OFFSET_DAY : stm32wbxx_ll_rtc.h
  • RTC_OFFSET_HOUR : stm32wbxx_ll_rtc.h
  • RTC_OFFSET_MINUTE : stm32wbxx_ll_rtc.h
  • RTC_OFFSET_MONTH : stm32wbxx_ll_rtc.h
  • RTC_OFFSET_WEEKDAY : stm32wbxx_ll_rtc.h
  • RTC_OUTPUT_ALARMA : stm32wbxx_hal_rtc_ex.h
  • RTC_OUTPUT_ALARMB : stm32wbxx_hal_rtc_ex.h
  • RTC_OUTPUT_DISABLE : stm32wbxx_hal_rtc_ex.h
  • RTC_OUTPUT_POLARITY_HIGH : stm32wbxx_hal_rtc.h
  • RTC_OUTPUT_POLARITY_LOW : stm32wbxx_hal_rtc.h
  • RTC_OUTPUT_REMAP_NONE : stm32wbxx_hal_rtc.h
  • RTC_OUTPUT_REMAP_POS1 : stm32wbxx_hal_rtc.h
  • RTC_OUTPUT_TYPE_OPENDRAIN : stm32wbxx_hal_rtc.h
  • RTC_OUTPUT_TYPE_PUSHPULL : stm32wbxx_hal_rtc.h
  • RTC_OUTPUT_WAKEUP : stm32wbxx_hal_rtc_ex.h
  • RTC_RSF_MASK : stm32wbxx_hal_rtc.h
  • RTC_SHIFTADD1S_RESET : stm32wbxx_hal_rtc_ex.h
  • RTC_SHIFTADD1S_SET : stm32wbxx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_16SEC : stm32wbxx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_32SEC : stm32wbxx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PERIOD_8SEC : stm32wbxx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PLUSPULSES_RESET : stm32wbxx_hal_rtc_ex.h
  • RTC_SMOOTHCALIB_PLUSPULSES_SET : stm32wbxx_hal_rtc_ex.h
  • RTC_STOREOPERATION_RESET : stm32wbxx_hal_rtc.h
  • RTC_STOREOPERATION_SET : stm32wbxx_hal_rtc.h
  • RTC_SYNCH_PRESC_DEFAULT : stm32wbxx_ll_rtc.c
  • RTC_SYNCHRO_TIMEOUT : stm32wbxx_ll_rtc.c
  • RTC_TAMPCR_MASK : stm32wbxx_hal_rtc_ex.c
  • RTC_TAMPCR_TAMPXE : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPCR_TAMPXIE : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPER1_INTERRUPT : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPER2_INTERRUPT : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPER3_INTERRUPT : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPER_1 : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPER_2 : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPER_3 : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPER_ERASE_BACKUP_DISABLE : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPER_ERASE_BACKUP_ENABLE : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPER_PULLUP_DISABLE : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPER_PULLUP_ENABLE : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_2SAMPLE : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_4SAMPLE : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_8SAMPLE : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERFILTER_DISABLE : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERMASK_FLAG_DISABLE : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERMASK_FLAG_ENABLE : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_1RTCCLK : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_2RTCCLK : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_4RTCCLK : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERPRECHARGEDURATION_8RTCCLK : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_FALLINGEDGE : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_HIGHLEVEL : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_LOWLEVEL : stm32wbxx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_RISINGEDGE : stm32wbxx_hal_rtc_ex.h
  • RTC_TIMEOUT_VALUE : stm32wbxx_hal_rtc.h
  • RTC_TIMESTAMPEDGE_FALLING : stm32wbxx_hal_rtc_ex.h
  • RTC_TIMESTAMPEDGE_RISING : stm32wbxx_hal_rtc_ex.h
  • RTC_TIMESTAMPONTAMPERDETECTION_DISABLE : stm32wbxx_hal_rtc_ex.h
  • RTC_TIMESTAMPONTAMPERDETECTION_ENABLE : stm32wbxx_hal_rtc_ex.h
  • RTC_TIMESTAMPPIN_DEFAULT : stm32wbxx_hal_rtc_ex.h
  • RTC_TR_RESERVED_MASK : stm32wbxx_hal_rtc.h
  • RTC_WAKEUPCLOCK_CK_SPRE_16BITS : stm32wbxx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_CK_SPRE_17BITS : stm32wbxx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV16 : stm32wbxx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV2 : stm32wbxx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV4 : stm32wbxx_hal_rtc_ex.h
  • RTC_WAKEUPCLOCK_RTCCLK_DIV8 : stm32wbxx_hal_rtc_ex.h
  • RTC_WEEKDAY_FRIDAY : stm32wbxx_hal_rtc.h
  • RTC_WEEKDAY_MONDAY : stm32wbxx_hal_rtc.h
  • RTC_WEEKDAY_SATURDAY : stm32wbxx_hal_rtc.h
  • RTC_WEEKDAY_SUNDAY : stm32wbxx_hal_rtc.h
  • RTC_WEEKDAY_THURSDAY : stm32wbxx_hal_rtc.h
  • RTC_WEEKDAY_TUESDAY : stm32wbxx_hal_rtc.h
  • RTC_WEEKDAY_WEDNESDAY : stm32wbxx_hal_rtc.h
  • RTC_WRITE_PROTECTION_DISABLE : stm32wbxx_ll_rtc.h
  • RTC_WRITE_PROTECTION_ENABLE_1 : stm32wbxx_ll_rtc.h
  • RTC_WRITE_PROTECTION_ENABLE_2 : stm32wbxx_ll_rtc.h
  • RX_FIFO_DEPTH : stm32wbxx_hal_uart_ex.c , stm32wbxx_hal_usart_ex.c , stm32wbxx_hal_smartcard_ex.c
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

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- s -

  • SAI_AC97_PROTOCOL : stm32wbxx_hal_sai.h
  • SAI_ALAW_1CPL_COMPANDING : stm32wbxx_hal_sai.h
  • SAI_ALAW_2CPL_COMPANDING : stm32wbxx_hal_sai.h
  • SAI_ASYNCHRONOUS : stm32wbxx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_11K : stm32wbxx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_16K : stm32wbxx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_192K : stm32wbxx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_22K : stm32wbxx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_32K : stm32wbxx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_44K : stm32wbxx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_48K : stm32wbxx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_8K : stm32wbxx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_96K : stm32wbxx_hal_sai.h
  • SAI_AUDIO_FREQUENCY_MCKDIV : stm32wbxx_hal_sai.h
  • SAI_CLOCKSTROBING_FALLINGEDGE : stm32wbxx_hal_sai.h
  • SAI_CLOCKSTROBING_RISINGEDGE : stm32wbxx_hal_sai.h
  • SAI_DATASIZE_10 : stm32wbxx_hal_sai.h
  • SAI_DATASIZE_16 : stm32wbxx_hal_sai.h
  • SAI_DATASIZE_20 : stm32wbxx_hal_sai.h
  • SAI_DATASIZE_24 : stm32wbxx_hal_sai.h
  • SAI_DATASIZE_32 : stm32wbxx_hal_sai.h
  • SAI_DATASIZE_8 : stm32wbxx_hal_sai.h
  • SAI_DEFAULT_TIMEOUT : stm32wbxx_hal_sai.c
  • SAI_FIFOSTATUS_1QUARTERFULL : stm32wbxx_hal_sai.h
  • SAI_FIFOSTATUS_3QUARTERFULL : stm32wbxx_hal_sai.h
  • SAI_FIFOSTATUS_EMPTY : stm32wbxx_hal_sai.h
  • SAI_FIFOSTATUS_FULL : stm32wbxx_hal_sai.h
  • SAI_FIFOSTATUS_HALFFULL : stm32wbxx_hal_sai.h
  • SAI_FIFOSTATUS_LESS1QUARTERFULL : stm32wbxx_hal_sai.h
  • SAI_FIFOTHRESHOLD_1QF : stm32wbxx_hal_sai.h
  • SAI_FIFOTHRESHOLD_3QF : stm32wbxx_hal_sai.h
  • SAI_FIFOTHRESHOLD_EMPTY : stm32wbxx_hal_sai.h
  • SAI_FIFOTHRESHOLD_FULL : stm32wbxx_hal_sai.h
  • SAI_FIFOTHRESHOLD_HF : stm32wbxx_hal_sai.h
  • SAI_FIRSTBIT_LSB : stm32wbxx_hal_sai.h
  • SAI_FIRSTBIT_MSB : stm32wbxx_hal_sai.h
  • SAI_FLAG_AFSDET : stm32wbxx_hal_sai.h
  • SAI_FLAG_CNRDY : stm32wbxx_hal_sai.h
  • SAI_FLAG_FREQ : stm32wbxx_hal_sai.h
  • SAI_FLAG_LFSDET : stm32wbxx_hal_sai.h
  • SAI_FLAG_MUTEDET : stm32wbxx_hal_sai.h
  • SAI_FLAG_OVRUDR : stm32wbxx_hal_sai.h
  • SAI_FLAG_WCKCFG : stm32wbxx_hal_sai.h
  • SAI_FREE_PROTOCOL : stm32wbxx_hal_sai.h
  • SAI_FS_ACTIVE_HIGH : stm32wbxx_hal_sai.h
  • SAI_FS_ACTIVE_LOW : stm32wbxx_hal_sai.h
  • SAI_FS_BEFOREFIRSTBIT : stm32wbxx_hal_sai.h
  • SAI_FS_CHANNEL_IDENTIFICATION : stm32wbxx_hal_sai.h
  • SAI_FS_FIRSTBIT : stm32wbxx_hal_sai.h
  • SAI_FS_STARTFRAME : stm32wbxx_hal_sai.h
  • SAI_I2S_LSBJUSTIFIED : stm32wbxx_hal_sai.h
  • SAI_I2S_MSBJUSTIFIED : stm32wbxx_hal_sai.h
  • SAI_I2S_STANDARD : stm32wbxx_hal_sai.h
  • SAI_IT_AFSDET : stm32wbxx_hal_sai.h
  • SAI_IT_CNRDY : stm32wbxx_hal_sai.h
  • SAI_IT_FREQ : stm32wbxx_hal_sai.h
  • SAI_IT_LFSDET : stm32wbxx_hal_sai.h
  • SAI_IT_MUTEDET : stm32wbxx_hal_sai.h
  • SAI_IT_OVRUDR : stm32wbxx_hal_sai.h
  • SAI_IT_WCKCFG : stm32wbxx_hal_sai.h
  • SAI_LAST_SENT_VALUE : stm32wbxx_hal_sai.h
  • SAI_LONG_TIMEOUT : stm32wbxx_hal_sai.c
  • SAI_MASTERDIVIDER_DISABLE : stm32wbxx_hal_sai.h
  • SAI_MASTERDIVIDER_ENABLE : stm32wbxx_hal_sai.h
  • SAI_MCK_OUTPUT_DISABLE : stm32wbxx_hal_sai.h
  • SAI_MCK_OUTPUT_ENABLE : stm32wbxx_hal_sai.h
  • SAI_MCK_OVERSAMPLING_DISABLE : stm32wbxx_hal_sai.h
  • SAI_MCK_OVERSAMPLING_ENABLE : stm32wbxx_hal_sai.h
  • SAI_MODEMASTER_RX : stm32wbxx_hal_sai.h
  • SAI_MODEMASTER_TX : stm32wbxx_hal_sai.h
  • SAI_MODESLAVE_RX : stm32wbxx_hal_sai.h
  • SAI_MODESLAVE_TX : stm32wbxx_hal_sai.h
  • SAI_MONOMODE : stm32wbxx_hal_sai.h
  • SAI_NOCOMPANDING : stm32wbxx_hal_sai.h
  • SAI_OUTPUT_NOTRELEASED : stm32wbxx_hal_sai.h
  • SAI_OUTPUT_RELEASED : stm32wbxx_hal_sai.h
  • SAI_OUTPUTDRIVE_DISABLE : stm32wbxx_hal_sai.h
  • SAI_OUTPUTDRIVE_ENABLE : stm32wbxx_hal_sai.h
  • SAI_PCM_LONG : stm32wbxx_hal_sai.h
  • SAI_PCM_SHORT : stm32wbxx_hal_sai.h
  • SAI_PDM_CLOCK1_ENABLE : stm32wbxx_hal_sai.h
  • SAI_PDM_CLOCK2_ENABLE : stm32wbxx_hal_sai.h
  • SAI_PDM_DELAY_MASK : stm32wbxx_hal_sai_ex.c
  • SAI_PDM_DELAY_OFFSET : stm32wbxx_hal_sai_ex.c
  • SAI_PDM_RIGHT_DELAY_OFFSET : stm32wbxx_hal_sai_ex.c
  • SAI_PROTOCOL_DATASIZE_16BIT : stm32wbxx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_16BITEXTENDED : stm32wbxx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_24BIT : stm32wbxx_hal_sai.h
  • SAI_PROTOCOL_DATASIZE_32BIT : stm32wbxx_hal_sai.h
  • SAI_SLOT_NOTACTIVE : stm32wbxx_hal_sai.h
  • SAI_SLOTACTIVE_0 : stm32wbxx_hal_sai.h
  • SAI_SLOTACTIVE_1 : stm32wbxx_hal_sai.h
  • SAI_SLOTACTIVE_10 : stm32wbxx_hal_sai.h
  • SAI_SLOTACTIVE_11 : stm32wbxx_hal_sai.h
  • SAI_SLOTACTIVE_12 : stm32wbxx_hal_sai.h
  • SAI_SLOTACTIVE_13 : stm32wbxx_hal_sai.h
  • SAI_SLOTACTIVE_14 : stm32wbxx_hal_sai.h
  • SAI_SLOTACTIVE_15 : stm32wbxx_hal_sai.h
  • SAI_SLOTACTIVE_2 : stm32wbxx_hal_sai.h
  • SAI_SLOTACTIVE_3 : stm32wbxx_hal_sai.h
  • SAI_SLOTACTIVE_4 : stm32wbxx_hal_sai.h
  • SAI_SLOTACTIVE_5 : stm32wbxx_hal_sai.h
  • SAI_SLOTACTIVE_6 : stm32wbxx_hal_sai.h
  • SAI_SLOTACTIVE_7 : stm32wbxx_hal_sai.h
  • SAI_SLOTACTIVE_8 : stm32wbxx_hal_sai.h
  • SAI_SLOTACTIVE_9 : stm32wbxx_hal_sai.h
  • SAI_SLOTACTIVE_ALL : stm32wbxx_hal_sai.h
  • SAI_SLOTSIZE_16B : stm32wbxx_hal_sai.h
  • SAI_SLOTSIZE_32B : stm32wbxx_hal_sai.h
  • SAI_SLOTSIZE_DATASIZE : stm32wbxx_hal_sai.h
  • SAI_SPDIF_PROTOCOL : stm32wbxx_hal_sai.h
  • SAI_STEREOMODE : stm32wbxx_hal_sai.h
  • SAI_SYNCEXT_DISABLE : stm32wbxx_hal_sai.h
  • SAI_SYNCEXT_OUTBLOCKA_ENABLE : stm32wbxx_hal_sai.h
  • SAI_SYNCEXT_OUTBLOCKB_ENABLE : stm32wbxx_hal_sai.h
  • SAI_SYNCHRONOUS : stm32wbxx_hal_sai.h
  • SAI_SYNCHRONOUS_EXT_SAI1 : stm32wbxx_hal_sai.h
  • SAI_SYNCHRONOUS_EXT_SAI2 : stm32wbxx_hal_sai.h
  • SAI_ULAW_1CPL_COMPANDING : stm32wbxx_hal_sai.h
  • SAI_ULAW_2CPL_COMPANDING : stm32wbxx_hal_sai.h
  • SAI_ZERO_VALUE : stm32wbxx_hal_sai.h
  • SlaveAddr_MSK : stm32wbxx_hal_i2c.c
  • SlaveAddr_SHIFT : stm32wbxx_hal_i2c.c
  • SMARTCARD_ADVFEATURE_DATAINV_DISABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DATAINV_ENABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DATAINVERT_INIT : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR : stm32wbxx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR : stm32wbxx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_MSBFIRST_INIT : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_NO_INIT : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_OVERRUN_DISABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_OVERRUN_ENABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINV_DISABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINV_ENABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_RXINVERT_INIT : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_SWAP_DISABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_SWAP_ENABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_SWAP_INIT : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_TXCOMPLETION : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_ADVFEATURE_TXINV_DISABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_TXINV_ENABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_ADVFEATURE_TXINVERT_INIT : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_EOBF : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_FEF : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_IDLEF : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_NEF : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_OREF : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_PEF : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_RTOF : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_TCBGTF : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_TCF : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_CLEAR_TXFECF : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_CR_MASK : stm32wbxx_hal_smartcard.h
  • SMARTCARD_CR_POS : stm32wbxx_hal_smartcard.h
  • SMARTCARD_FIFOMODE_DISABLE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FIFOMODE_ENABLE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_BUSY : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_EOBF : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_FE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_IDLE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_NE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_ORE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_PE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_REACK : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RTOF : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXFF : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXFNE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXFT : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_RXNE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TC : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TCBGT : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TEACK : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXFE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXFNF : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_FLAG_TXFT : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_GETCLOCKSOURCE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_ISR_MASK : stm32wbxx_hal_smartcard.h
  • SMARTCARD_ISR_POS : stm32wbxx_hal_smartcard.h
  • SMARTCARD_IT_EOB : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_IT_ERR : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_IT_FE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_IT_IDLE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_IT_MASK : stm32wbxx_hal_smartcard.h
  • SMARTCARD_IT_NE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_IT_ORE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_IT_PE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_IT_RTO : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXFF : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXFNE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXFT : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_IT_RXNE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_IT_TC : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_IT_TCBGT : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXFE : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXFNF : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_IT_TXFT : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_LASTBIT_DISABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_LASTBIT_ENABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_MODE_RX : stm32wbxx_hal_smartcard.h
  • SMARTCARD_MODE_TX : stm32wbxx_hal_smartcard.h
  • SMARTCARD_MODE_TX_RX : stm32wbxx_hal_smartcard.h
  • SMARTCARD_NACK_DISABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_NACK_ENABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_ONE_BIT_SAMPLE_DISABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_ONE_BIT_SAMPLE_ENABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_PARITY_EVEN : stm32wbxx_hal_smartcard.h
  • SMARTCARD_PARITY_ODD : stm32wbxx_hal_smartcard.h
  • SMARTCARD_PHASE_1EDGE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_PHASE_2EDGE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_POLARITY_HIGH : stm32wbxx_hal_smartcard.h
  • SMARTCARD_POLARITY_LOW : stm32wbxx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV1 : stm32wbxx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV10 : stm32wbxx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV12 : stm32wbxx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV128 : stm32wbxx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV16 : stm32wbxx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV2 : stm32wbxx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV256 : stm32wbxx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV32 : stm32wbxx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV4 : stm32wbxx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV6 : stm32wbxx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV64 : stm32wbxx_hal_smartcard.h
  • SMARTCARD_PRESCALER_DIV8 : stm32wbxx_hal_smartcard.h
  • SMARTCARD_RXDATA_FLUSH_REQUEST : stm32wbxx_hal_smartcard.h
  • SMARTCARD_RXFIFO_THRESHOLD_1_2 : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_1_4 : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_1_8 : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_3_4 : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_7_8 : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_RXFIFO_THRESHOLD_8_8 : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_STOPBITS_0_5 : stm32wbxx_hal_smartcard.h
  • SMARTCARD_STOPBITS_1_5 : stm32wbxx_hal_smartcard.h
  • SMARTCARD_TC : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_TCBGT : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_TEACK_REACK_TIMEOUT : stm32wbxx_hal_smartcard.c
  • SMARTCARD_TIMEOUT_DISABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_TIMEOUT_ENABLE : stm32wbxx_hal_smartcard.h
  • SMARTCARD_TRANSMISSION_COMPLETION_FLAG : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_TRANSMISSION_COMPLETION_SETTING : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_TXDATA_FLUSH_REQUEST : stm32wbxx_hal_smartcard.h
  • SMARTCARD_TXFIFO_THRESHOLD_1_2 : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_1_4 : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_1_8 : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_3_4 : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_7_8 : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_TXFIFO_THRESHOLD_8_8 : stm32wbxx_hal_smartcard_ex.h
  • SMARTCARD_WORDLENGTH_9B : stm32wbxx_hal_smartcard.h
  • SMBUS_ADDRESSINGMODE_10BIT : stm32wbxx_hal_smbus.h
  • SMBUS_ADDRESSINGMODE_7BIT : stm32wbxx_hal_smbus.h
  • SMBUS_ANALOGFILTER_DISABLE : stm32wbxx_hal_smbus.h
  • SMBUS_ANALOGFILTER_ENABLE : stm32wbxx_hal_smbus.h
  • SMBUS_AUTOEND_MODE : stm32wbxx_hal_smbus.h
  • SMBUS_CHECK_FLAG : stm32wbxx_hal_smbus.h
  • SMBUS_CHECK_IT_SOURCE : stm32wbxx_hal_smbus.h
  • SMBUS_DUALADDRESS_DISABLE : stm32wbxx_hal_smbus.h
  • SMBUS_DUALADDRESS_ENABLE : stm32wbxx_hal_smbus.h
  • SMBUS_FIRST_AND_LAST_FRAME_NO_PEC : stm32wbxx_hal_smbus.h
  • SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC : stm32wbxx_hal_smbus.h
  • SMBUS_FIRST_FRAME : stm32wbxx_hal_smbus.h
  • SMBUS_FLAG_ADDR : stm32wbxx_hal_smbus.h
  • SMBUS_FLAG_AF : stm32wbxx_hal_smbus.h
  • SMBUS_FLAG_ALERT : stm32wbxx_hal_smbus.h
  • SMBUS_FLAG_ARLO : stm32wbxx_hal_smbus.h
  • SMBUS_FLAG_BERR : stm32wbxx_hal_smbus.h
  • SMBUS_FLAG_BUSY : stm32wbxx_hal_smbus.h
  • SMBUS_FLAG_DIR : stm32wbxx_hal_smbus.h
  • SMBUS_FLAG_MASK : stm32wbxx_hal_smbus.h
  • SMBUS_FLAG_OVR : stm32wbxx_hal_smbus.h
  • SMBUS_FLAG_PECERR : stm32wbxx_hal_smbus.h
  • SMBUS_FLAG_RXNE : stm32wbxx_hal_smbus.h
  • SMBUS_FLAG_STOPF : stm32wbxx_hal_smbus.h
  • SMBUS_FLAG_TC : stm32wbxx_hal_smbus.h
  • SMBUS_FLAG_TCR : stm32wbxx_hal_smbus.h
  • SMBUS_FLAG_TIMEOUT : stm32wbxx_hal_smbus.h
  • SMBUS_FLAG_TXE : stm32wbxx_hal_smbus.h
  • SMBUS_FLAG_TXIS : stm32wbxx_hal_smbus.h
  • SMBUS_GENERALCALL_DISABLE : stm32wbxx_hal_smbus.h
  • SMBUS_GENERALCALL_ENABLE : stm32wbxx_hal_smbus.h
  • SMBUS_GENERATE_START : stm32wbxx_hal_smbus.h
  • SMBUS_GENERATE_START_READ : stm32wbxx_hal_smbus.h
  • SMBUS_GENERATE_START_WRITE : stm32wbxx_hal_smbus.h
  • SMBUS_GENERATE_STOP : stm32wbxx_hal_smbus.h
  • SMBUS_GET_ADDR_MATCH : stm32wbxx_hal_smbus.h
  • SMBUS_GET_ALERT_ENABLED : stm32wbxx_hal_smbus.h
  • SMBUS_GET_DIR : stm32wbxx_hal_smbus.h
  • SMBUS_GET_PEC_MODE : stm32wbxx_hal_smbus.h
  • SMBUS_GET_STOP_MODE : stm32wbxx_hal_smbus.h
  • SMBUS_IT_ADDR : stm32wbxx_hal_smbus.h
  • SMBUS_IT_ADDRI : stm32wbxx_hal_smbus.h
  • SMBUS_IT_ALERT : stm32wbxx_hal_smbus.h
  • SMBUS_IT_ERRI : stm32wbxx_hal_smbus.h
  • SMBUS_IT_NACKI : stm32wbxx_hal_smbus.h
  • SMBUS_IT_RX : stm32wbxx_hal_smbus.h
  • SMBUS_IT_RXI : stm32wbxx_hal_smbus.h
  • SMBUS_IT_STOPI : stm32wbxx_hal_smbus.h
  • SMBUS_IT_TCI : stm32wbxx_hal_smbus.h
  • SMBUS_IT_TX : stm32wbxx_hal_smbus.h
  • SMBUS_IT_TXI : stm32wbxx_hal_smbus.h
  • SMBUS_LAST_FRAME_NO_PEC : stm32wbxx_hal_smbus.h
  • SMBUS_LAST_FRAME_WITH_PEC : stm32wbxx_hal_smbus.h
  • SMBUS_NEXT_FRAME : stm32wbxx_hal_smbus.h
  • SMBUS_NO_STARTSTOP : stm32wbxx_hal_smbus.h
  • SMBUS_NOSTRETCH_DISABLE : stm32wbxx_hal_smbus.h
  • SMBUS_NOSTRETCH_ENABLE : stm32wbxx_hal_smbus.h
  • SMBUS_OA2_MASK01 : stm32wbxx_hal_smbus.h
  • SMBUS_OA2_MASK02 : stm32wbxx_hal_smbus.h
  • SMBUS_OA2_MASK03 : stm32wbxx_hal_smbus.h
  • SMBUS_OA2_MASK04 : stm32wbxx_hal_smbus.h
  • SMBUS_OA2_MASK05 : stm32wbxx_hal_smbus.h
  • SMBUS_OA2_MASK06 : stm32wbxx_hal_smbus.h
  • SMBUS_OA2_MASK07 : stm32wbxx_hal_smbus.h
  • SMBUS_OA2_NOMASK : stm32wbxx_hal_smbus.h
  • SMBUS_OTHER_AND_LAST_FRAME_NO_PEC : stm32wbxx_hal_smbus.h
  • SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC : stm32wbxx_hal_smbus.h
  • SMBUS_OTHER_FRAME_NO_PEC : stm32wbxx_hal_smbus.h
  • SMBUS_OTHER_FRAME_WITH_PEC : stm32wbxx_hal_smbus.h
  • SMBUS_PEC_DISABLE : stm32wbxx_hal_smbus.h
  • SMBUS_PEC_ENABLE : stm32wbxx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_HOST : stm32wbxx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE : stm32wbxx_hal_smbus.h
  • SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP : stm32wbxx_hal_smbus.h
  • SMBUS_RELOAD_MODE : stm32wbxx_hal_smbus.h
  • SMBUS_RESET_CR1 : stm32wbxx_hal_smbus.h
  • SMBUS_RESET_CR2 : stm32wbxx_hal_smbus.h
  • SMBUS_SENDPEC_MODE : stm32wbxx_hal_smbus.h
  • SMBUS_SOFTEND_MODE : stm32wbxx_hal_smbus.h
  • SMPS_VOLTAGE_BASE_MV : stm32wbxx_ll_pwr.h
  • SMPS_VOLTAGE_CAL : stm32wbxx_ll_pwr.h
  • SMPS_VOLTAGE_CAL_ADDR : stm32wbxx_ll_pwr.h
  • SMPS_VOLTAGE_CAL_POS : stm32wbxx_ll_pwr.h
  • SMPS_VOLTAGE_CAL_VOLTAGE_MV : stm32wbxx_ll_pwr.h
  • SMPS_VOLTAGE_STEP_MV : stm32wbxx_ll_pwr.h
  • SPI_1LINE_RX : stm32wbxx_hal_spi.h
  • SPI_1LINE_TX : stm32wbxx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_128 : stm32wbxx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_16 : stm32wbxx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_2 : stm32wbxx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_256 : stm32wbxx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_32 : stm32wbxx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_4 : stm32wbxx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_64 : stm32wbxx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_8 : stm32wbxx_hal_spi.h
  • SPI_CHECK_FLAG : stm32wbxx_hal_spi.h
  • SPI_CHECK_IT_SOURCE : stm32wbxx_hal_spi.h
  • SPI_CR1_CLEAR_MASK : stm32wbxx_ll_spi.c
  • SPI_CRC_LENGTH_16BIT : stm32wbxx_hal_spi.h
  • SPI_CRC_LENGTH_8BIT : stm32wbxx_hal_spi.h
  • SPI_CRC_LENGTH_DATASIZE : stm32wbxx_hal_spi.h
  • SPI_CRCCALCULATION_DISABLE : stm32wbxx_hal_spi.h
  • SPI_CRCCALCULATION_ENABLE : stm32wbxx_hal_spi.h
  • SPI_DATASIZE_10BIT : stm32wbxx_hal_spi.h
  • SPI_DATASIZE_11BIT : stm32wbxx_hal_spi.h
  • SPI_DATASIZE_12BIT : stm32wbxx_hal_spi.h
  • SPI_DATASIZE_13BIT : stm32wbxx_hal_spi.h
  • SPI_DATASIZE_14BIT : stm32wbxx_hal_spi.h
  • SPI_DATASIZE_15BIT : stm32wbxx_hal_spi.h
  • SPI_DATASIZE_16BIT : stm32wbxx_hal_spi.h
  • SPI_DATASIZE_4BIT : stm32wbxx_hal_spi.h
  • SPI_DATASIZE_5BIT : stm32wbxx_hal_spi.h
  • SPI_DATASIZE_6BIT : stm32wbxx_hal_spi.h
  • SPI_DATASIZE_7BIT : stm32wbxx_hal_spi.h
  • SPI_DATASIZE_8BIT : stm32wbxx_hal_spi.h
  • SPI_DATASIZE_9BIT : stm32wbxx_hal_spi.h
  • SPI_DEFAULT_TIMEOUT : stm32wbxx_hal_spi.c
  • SPI_DIRECTION_1LINE : stm32wbxx_hal_spi.h
  • SPI_DIRECTION_2LINES : stm32wbxx_hal_spi.h
  • SPI_DIRECTION_2LINES_RXONLY : stm32wbxx_hal_spi.h
  • SPI_FIFO_SIZE : stm32wbxx_hal_spi_ex.c
  • SPI_FIRSTBIT_LSB : stm32wbxx_hal_spi.h
  • SPI_FIRSTBIT_MSB : stm32wbxx_hal_spi.h
  • SPI_FLAG_BSY : stm32wbxx_hal_spi.h
  • SPI_FLAG_CRCERR : stm32wbxx_hal_spi.h
  • SPI_FLAG_FRE : stm32wbxx_hal_spi.h
  • SPI_FLAG_FRLVL : stm32wbxx_hal_spi.h
  • SPI_FLAG_FTLVL : stm32wbxx_hal_spi.h
  • SPI_FLAG_MASK : stm32wbxx_hal_spi.h
  • SPI_FLAG_MODF : stm32wbxx_hal_spi.h
  • SPI_FLAG_OVR : stm32wbxx_hal_spi.h
  • SPI_FLAG_RXNE : stm32wbxx_hal_spi.h
  • SPI_FLAG_TXE : stm32wbxx_hal_spi.h
  • SPI_FRLVL_EMPTY : stm32wbxx_hal_spi.h
  • SPI_FRLVL_FULL : stm32wbxx_hal_spi.h
  • SPI_FRLVL_HALF_FULL : stm32wbxx_hal_spi.h
  • SPI_FRLVL_QUARTER_FULL : stm32wbxx_hal_spi.h
  • SPI_FTLVL_EMPTY : stm32wbxx_hal_spi.h
  • SPI_FTLVL_FULL : stm32wbxx_hal_spi.h
  • SPI_FTLVL_HALF_FULL : stm32wbxx_hal_spi.h
  • SPI_FTLVL_QUARTER_FULL : stm32wbxx_hal_spi.h
  • SPI_IT_ERR : stm32wbxx_hal_spi.h
  • SPI_IT_RXNE : stm32wbxx_hal_spi.h
  • SPI_IT_TXE : stm32wbxx_hal_spi.h
  • SPI_MODE_MASTER : stm32wbxx_hal_spi.h
  • SPI_MODE_SLAVE : stm32wbxx_hal_spi.h
  • SPI_NSS_HARD_INPUT : stm32wbxx_hal_spi.h
  • SPI_NSS_HARD_OUTPUT : stm32wbxx_hal_spi.h
  • SPI_NSS_PULSE_DISABLE : stm32wbxx_hal_spi.h
  • SPI_NSS_PULSE_ENABLE : stm32wbxx_hal_spi.h
  • SPI_NSS_SOFT : stm32wbxx_hal_spi.h
  • SPI_PHASE_1EDGE : stm32wbxx_hal_spi.h
  • SPI_PHASE_2EDGE : stm32wbxx_hal_spi.h
  • SPI_POLARITY_HIGH : stm32wbxx_hal_spi.h
  • SPI_POLARITY_LOW : stm32wbxx_hal_spi.h
  • SPI_RESET_CRC : stm32wbxx_hal_spi.h
  • SPI_RXFIFO_THRESHOLD : stm32wbxx_hal_spi.h
  • SPI_RXFIFO_THRESHOLD_HF : stm32wbxx_hal_spi.h
  • SPI_RXFIFO_THRESHOLD_QF : stm32wbxx_hal_spi.h
  • SPI_TIMODE_DISABLE : stm32wbxx_hal_spi.h
  • SPI_TIMODE_ENABLE : stm32wbxx_hal_spi.h
  • SRAM2A_FULL_UNSECURE : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_0 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_1 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_10 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_11 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_12 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_13 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_14 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_15 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_16 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_17 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_18 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_19 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_2 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_20 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_21 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_22 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_23 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_24 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_25 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_26 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_27 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_28 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_29 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_3 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_30 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_31 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_4 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_5 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_6 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_7 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_8 : stm32wbxx_hal_flash.h
  • SRAM2A_START_SECURE_ADDR_9 : stm32wbxx_hal_flash.h
  • SRAM2B_FULL_UNSECURE : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_0 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_1 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_10 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_11 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_12 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_13 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_14 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_15 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_16 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_17 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_18 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_19 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_2 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_20 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_21 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_22 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_23 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_24 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_25 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_26 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_27 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_28 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_29 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_3 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_30 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_31 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_4 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_5 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_6 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_7 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_8 : stm32wbxx_hal_flash.h
  • SRAM2B_START_SECURE_ADDR_9 : stm32wbxx_hal_flash.h
  • SRAM_SECURE_PAGE_GRANULARITY : stm32wbxx_hal_flash.h
  • SRAM_SECURE_PAGE_GRANULARITY_OFFSET : stm32wbxx_hal_flash.h
  • SYSCFG_BOOT_MAINFLASH : stm32wbxx_hal.h
  • SYSCFG_BOOT_QUADSPI : stm32wbxx_hal.h
  • SYSCFG_BOOT_SRAM : stm32wbxx_hal.h
  • SYSCFG_BOOT_SYSTEMFLASH : stm32wbxx_hal.h
  • SYSCFG_FASTMODEPLUS_PB6 : stm32wbxx_hal.h
  • SYSCFG_FASTMODEPLUS_PB7 : stm32wbxx_hal.h
  • SYSCFG_FASTMODEPLUS_PB8 : stm32wbxx_hal.h
  • SYSCFG_FASTMODEPLUS_PB9 : stm32wbxx_hal.h
  • SYSCFG_FLAG_SRAM2_BUSY : stm32wbxx_hal.h
  • SYSCFG_FLAG_SRAM2_PE : stm32wbxx_hal.h
  • SYSCFG_IT_FPU_DZC : stm32wbxx_hal.h
  • SYSCFG_IT_FPU_IDC : stm32wbxx_hal.h
  • SYSCFG_IT_FPU_IOC : stm32wbxx_hal.h
  • SYSCFG_IT_FPU_IXC : stm32wbxx_hal.h
  • SYSCFG_IT_FPU_OFC : stm32wbxx_hal.h
  • SYSCFG_IT_FPU_UFC : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE0 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE1 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE10 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE11 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE12 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE13 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE14 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE15 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE16 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE17 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE18 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE19 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE2 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE20 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE21 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE22 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE23 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE24 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE25 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE26 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE27 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE28 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE29 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE3 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE30 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE31 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE32 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE33 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE34 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE35 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE36 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE37 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE38 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE39 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE4 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE40 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE41 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE42 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE43 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE44 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE45 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE46 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE47 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE48 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE49 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE5 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE50 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE51 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE52 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE53 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE54 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE55 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE56 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE57 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE58 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE59 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE6 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE60 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE61 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE62 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE63 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE7 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE8 : stm32wbxx_hal.h
  • SYSCFG_SRAM2WRP_PAGE9 : stm32wbxx_hal.h
  • SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE : stm32wbxx_hal.h
  • SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE : stm32wbxx_hal.h
  • SYSCFG_VREFBUF_VOLTAGE_SCALE0 : stm32wbxx_hal.h
  • SYSCFG_VREFBUF_VOLTAGE_SCALE1 : stm32wbxx_hal.h
  • SYSTEM_IN_SECURE_MODE : stm32wbxx_hal_flash.h
  • SYSTEM_NOT_IN_SECURE_MODE : stm32wbxx_hal_flash.h
  • SYSTICK_CLKSOURCE_HCLK : stm32wbxx_hal_cortex.h
  • SYSTICK_CLKSOURCE_HCLK_DIV8 : stm32wbxx_hal_cortex.h
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

  • File List
  • Globals
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- t -

  • TEMPSENSOR_CAL1_ADDR : stm32wbxx_ll_adc.h
  • TEMPSENSOR_CAL1_TEMP : stm32wbxx_ll_adc.h
  • TEMPSENSOR_CAL2_ADDR : stm32wbxx_ll_adc.h
  • TEMPSENSOR_CAL2_TEMP : stm32wbxx_ll_adc.h
  • TEMPSENSOR_CAL_VREFANALOG : stm32wbxx_ll_adc.h
  • TICK_INT_PRIORITY : stm32wbxx_hal_conf.h
  • TIM16_OR_RMP_MASK : stm32wbxx_ll_tim.h
  • TIM17_OR_RMP_MASK : stm32wbxx_ll_tim.h
  • TIM1_OR_RMP_MASK : stm32wbxx_ll_tim.h
  • TIM2_OR_RMP_MASK : stm32wbxx_ll_tim.h
  • TIM_AUTOMATICOUTPUT_DISABLE : stm32wbxx_hal_tim.h
  • TIM_AUTOMATICOUTPUT_ENABLE : stm32wbxx_hal_tim.h
  • TIM_AUTORELOAD_PRELOAD_DISABLE : stm32wbxx_hal_tim.h
  • TIM_AUTORELOAD_PRELOAD_ENABLE : stm32wbxx_hal_tim.h
  • TIM_BREAK2_DISABLE : stm32wbxx_hal_tim.h
  • TIM_BREAK2_ENABLE : stm32wbxx_hal_tim.h
  • TIM_BREAK2POLARITY_HIGH : stm32wbxx_hal_tim.h
  • TIM_BREAK2POLARITY_LOW : stm32wbxx_hal_tim.h
  • TIM_BREAK_DISABLE : stm32wbxx_hal_tim.h
  • TIM_BREAK_ENABLE : stm32wbxx_hal_tim.h
  • TIM_BREAK_SYSTEM_ECC : stm32wbxx_hal_tim.h
  • TIM_BREAK_SYSTEM_LOCKUP : stm32wbxx_hal_tim.h
  • TIM_BREAK_SYSTEM_PVD : stm32wbxx_hal_tim.h
  • TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR : stm32wbxx_hal_tim.h
  • TIM_BREAKINPUT_BRK : stm32wbxx_hal_tim_ex.h
  • TIM_BREAKINPUT_BRK2 : stm32wbxx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_BKIN : stm32wbxx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_COMP1 : stm32wbxx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_COMP2 : stm32wbxx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_DISABLE : stm32wbxx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_ENABLE : stm32wbxx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_POLARITY_HIGH : stm32wbxx_hal_tim_ex.h
  • TIM_BREAKINPUTSOURCE_POLARITY_LOW : stm32wbxx_hal_tim_ex.h
  • TIM_BREAKPOLARITY_HIGH : stm32wbxx_hal_tim.h
  • TIM_BREAKPOLARITY_LOW : stm32wbxx_hal_tim.h
  • TIM_CALC_DTS : stm32wbxx_ll_tim.h
  • TIM_CCER_CCxE_MASK : stm32wbxx_hal_tim.h
  • TIM_CCER_CCxNE_MASK : stm32wbxx_hal_tim.h
  • TIM_CCx_DISABLE : stm32wbxx_hal_tim.h
  • TIM_CCx_ENABLE : stm32wbxx_hal_tim.h
  • TIM_CCxN_DISABLE : stm32wbxx_hal_tim.h
  • TIM_CCxN_ENABLE : stm32wbxx_hal_tim.h
  • TIM_CHANNEL_1 : stm32wbxx_hal_tim.h
  • TIM_CHANNEL_2 : stm32wbxx_hal_tim.h
  • TIM_CHANNEL_3 : stm32wbxx_hal_tim.h
  • TIM_CHANNEL_4 : stm32wbxx_hal_tim.h
  • TIM_CHANNEL_5 : stm32wbxx_hal_tim.h
  • TIM_CHANNEL_6 : stm32wbxx_hal_tim.h
  • TIM_CHANNEL_ALL : stm32wbxx_hal_tim.h
  • TIM_CLEARINPUTPOLARITY_INVERTED : stm32wbxx_hal_tim.h
  • TIM_CLEARINPUTPOLARITY_NONINVERTED : stm32wbxx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV1 : stm32wbxx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV2 : stm32wbxx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV4 : stm32wbxx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV8 : stm32wbxx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_COMP1 : stm32wbxx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_COMP2 : stm32wbxx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_ETR : stm32wbxx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_NONE : stm32wbxx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV1 : stm32wbxx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV2 : stm32wbxx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV4 : stm32wbxx_hal_tim.h
  • TIM_CLOCKPOLARITY_BOTHEDGE : stm32wbxx_hal_tim.h
  • TIM_CLOCKPOLARITY_FALLING : stm32wbxx_hal_tim.h
  • TIM_CLOCKPOLARITY_INVERTED : stm32wbxx_hal_tim.h
  • TIM_CLOCKPOLARITY_NONINVERTED : stm32wbxx_hal_tim.h
  • TIM_CLOCKPOLARITY_RISING : stm32wbxx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV1 : stm32wbxx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV2 : stm32wbxx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV4 : stm32wbxx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV8 : stm32wbxx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE1 : stm32wbxx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE2 : stm32wbxx_hal_tim.h
  • TIM_CLOCKSOURCE_INTERNAL : stm32wbxx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR0 : stm32wbxx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR1 : stm32wbxx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR2 : stm32wbxx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR3 : stm32wbxx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1 : stm32wbxx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1ED : stm32wbxx_hal_tim.h
  • TIM_CLOCKSOURCE_TI2 : stm32wbxx_hal_tim.h
  • TIM_COMMUTATION_SOFTWARE : stm32wbxx_hal_tim.h
  • TIM_COMMUTATION_TRGI : stm32wbxx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED1 : stm32wbxx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED2 : stm32wbxx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED3 : stm32wbxx_hal_tim.h
  • TIM_COUNTERMODE_DOWN : stm32wbxx_hal_tim.h
  • TIM_COUNTERMODE_UP : stm32wbxx_hal_tim.h
  • TIM_DMA_CC1 : stm32wbxx_hal_tim.h
  • TIM_DMA_CC2 : stm32wbxx_hal_tim.h
  • TIM_DMA_CC3 : stm32wbxx_hal_tim.h
  • TIM_DMA_CC4 : stm32wbxx_hal_tim.h
  • TIM_DMA_COM : stm32wbxx_hal_tim.h
  • TIM_DMA_ID_CC1 : stm32wbxx_hal_tim.h
  • TIM_DMA_ID_CC2 : stm32wbxx_hal_tim.h
  • TIM_DMA_ID_CC3 : stm32wbxx_hal_tim.h
  • TIM_DMA_ID_CC4 : stm32wbxx_hal_tim.h
  • TIM_DMA_ID_COMMUTATION : stm32wbxx_hal_tim.h
  • TIM_DMA_ID_TRIGGER : stm32wbxx_hal_tim.h
  • TIM_DMA_ID_UPDATE : stm32wbxx_hal_tim.h
  • TIM_DMA_TRIGGER : stm32wbxx_hal_tim.h
  • TIM_DMA_UPDATE : stm32wbxx_hal_tim.h
  • TIM_DMABASE_AF1 : stm32wbxx_hal_tim.h
  • TIM_DMABASE_AF2 : stm32wbxx_hal_tim.h
  • TIM_DMABASE_ARR : stm32wbxx_hal_tim.h
  • TIM_DMABASE_BDTR : stm32wbxx_hal_tim.h
  • TIM_DMABASE_CCER : stm32wbxx_hal_tim.h
  • TIM_DMABASE_CCMR1 : stm32wbxx_hal_tim.h
  • TIM_DMABASE_CCMR2 : stm32wbxx_hal_tim.h
  • TIM_DMABASE_CCMR3 : stm32wbxx_hal_tim.h
  • TIM_DMABASE_CCR1 : stm32wbxx_hal_tim.h
  • TIM_DMABASE_CCR2 : stm32wbxx_hal_tim.h
  • TIM_DMABASE_CCR3 : stm32wbxx_hal_tim.h
  • TIM_DMABASE_CCR4 : stm32wbxx_hal_tim.h
  • TIM_DMABASE_CCR5 : stm32wbxx_hal_tim.h
  • TIM_DMABASE_CCR6 : stm32wbxx_hal_tim.h
  • TIM_DMABASE_CNT : stm32wbxx_hal_tim.h
  • TIM_DMABASE_CR1 : stm32wbxx_hal_tim.h
  • TIM_DMABASE_CR2 : stm32wbxx_hal_tim.h
  • TIM_DMABASE_DCR : stm32wbxx_hal_tim.h
  • TIM_DMABASE_DIER : stm32wbxx_hal_tim.h
  • TIM_DMABASE_DMAR : stm32wbxx_hal_tim.h
  • TIM_DMABASE_EGR : stm32wbxx_hal_tim.h
  • TIM_DMABASE_OR : stm32wbxx_hal_tim.h
  • TIM_DMABASE_PSC : stm32wbxx_hal_tim.h
  • TIM_DMABASE_RCR : stm32wbxx_hal_tim.h
  • TIM_DMABASE_SMCR : stm32wbxx_hal_tim.h
  • TIM_DMABASE_SR : stm32wbxx_hal_tim.h
  • TIM_DMABURSTLENGTH_10TRANSFERS : stm32wbxx_hal_tim.h
  • TIM_DMABURSTLENGTH_11TRANSFERS : stm32wbxx_hal_tim.h
  • TIM_DMABURSTLENGTH_12TRANSFERS : stm32wbxx_hal_tim.h
  • TIM_DMABURSTLENGTH_13TRANSFERS : stm32wbxx_hal_tim.h
  • TIM_DMABURSTLENGTH_14TRANSFERS : stm32wbxx_hal_tim.h
  • TIM_DMABURSTLENGTH_15TRANSFERS : stm32wbxx_hal_tim.h
  • TIM_DMABURSTLENGTH_16TRANSFERS : stm32wbxx_hal_tim.h
  • TIM_DMABURSTLENGTH_17TRANSFERS : stm32wbxx_hal_tim.h
  • TIM_DMABURSTLENGTH_18TRANSFERS : stm32wbxx_hal_tim.h
  • TIM_DMABURSTLENGTH_1TRANSFER : stm32wbxx_hal_tim.h
  • TIM_DMABURSTLENGTH_2TRANSFERS : stm32wbxx_hal_tim.h
  • TIM_DMABURSTLENGTH_3TRANSFERS : stm32wbxx_hal_tim.h
  • TIM_DMABURSTLENGTH_4TRANSFERS : stm32wbxx_hal_tim.h
  • TIM_DMABURSTLENGTH_5TRANSFERS : stm32wbxx_hal_tim.h
  • TIM_DMABURSTLENGTH_6TRANSFERS : stm32wbxx_hal_tim.h
  • TIM_DMABURSTLENGTH_7TRANSFERS : stm32wbxx_hal_tim.h
  • TIM_DMABURSTLENGTH_8TRANSFERS : stm32wbxx_hal_tim.h
  • TIM_DMABURSTLENGTH_9TRANSFERS : stm32wbxx_hal_tim.h
  • TIM_ENCODERINPUTPOLARITY_FALLING : stm32wbxx_hal_tim.h
  • TIM_ENCODERINPUTPOLARITY_RISING : stm32wbxx_hal_tim.h
  • TIM_ENCODERMODE_TI1 : stm32wbxx_hal_tim.h
  • TIM_ENCODERMODE_TI12 : stm32wbxx_hal_tim.h
  • TIM_ENCODERMODE_TI2 : stm32wbxx_hal_tim.h
  • TIM_ETRPOLARITY_INVERTED : stm32wbxx_hal_tim.h
  • TIM_ETRPOLARITY_NONINVERTED : stm32wbxx_hal_tim.h
  • TIM_ETRPRESCALER_DIV1 : stm32wbxx_hal_tim.h
  • TIM_ETRPRESCALER_DIV2 : stm32wbxx_hal_tim.h
  • TIM_ETRPRESCALER_DIV4 : stm32wbxx_hal_tim.h
  • TIM_ETRPRESCALER_DIV8 : stm32wbxx_hal_tim.h
  • TIM_EVENTSOURCE_BREAK : stm32wbxx_hal_tim.h
  • TIM_EVENTSOURCE_BREAK2 : stm32wbxx_hal_tim.h
  • TIM_EVENTSOURCE_CC1 : stm32wbxx_hal_tim.h
  • TIM_EVENTSOURCE_CC2 : stm32wbxx_hal_tim.h
  • TIM_EVENTSOURCE_CC3 : stm32wbxx_hal_tim.h
  • TIM_EVENTSOURCE_CC4 : stm32wbxx_hal_tim.h
  • TIM_EVENTSOURCE_COM : stm32wbxx_hal_tim.h
  • TIM_EVENTSOURCE_TRIGGER : stm32wbxx_hal_tim.h
  • TIM_EVENTSOURCE_UPDATE : stm32wbxx_hal_tim.h
  • TIM_FLAG_BREAK : stm32wbxx_hal_tim.h
  • TIM_FLAG_BREAK2 : stm32wbxx_hal_tim.h
  • TIM_FLAG_CC1 : stm32wbxx_hal_tim.h
  • TIM_FLAG_CC1OF : stm32wbxx_hal_tim.h
  • TIM_FLAG_CC2 : stm32wbxx_hal_tim.h
  • TIM_FLAG_CC2OF : stm32wbxx_hal_tim.h
  • TIM_FLAG_CC3 : stm32wbxx_hal_tim.h
  • TIM_FLAG_CC3OF : stm32wbxx_hal_tim.h
  • TIM_FLAG_CC4 : stm32wbxx_hal_tim.h
  • TIM_FLAG_CC4OF : stm32wbxx_hal_tim.h
  • TIM_FLAG_CC5 : stm32wbxx_hal_tim.h
  • TIM_FLAG_CC6 : stm32wbxx_hal_tim.h
  • TIM_FLAG_COM : stm32wbxx_hal_tim.h
  • TIM_FLAG_SYSTEM_BREAK : stm32wbxx_hal_tim.h
  • TIM_FLAG_TRIGGER : stm32wbxx_hal_tim.h
  • TIM_FLAG_UPDATE : stm32wbxx_hal_tim.h
  • TIM_GET_CHANNEL_INDEX : stm32wbxx_ll_tim.h
  • TIM_GET_OR_MASK : stm32wbxx_hal_tim_ex.c
  • TIM_GROUPCH5_NONE : stm32wbxx_hal_tim.h
  • TIM_GROUPCH5_OC1REFC : stm32wbxx_hal_tim.h
  • TIM_GROUPCH5_OC2REFC : stm32wbxx_hal_tim.h
  • TIM_GROUPCH5_OC3REFC : stm32wbxx_hal_tim.h
  • TIM_ICPOLARITY_BOTHEDGE : stm32wbxx_hal_tim.h
  • TIM_ICPOLARITY_FALLING : stm32wbxx_hal_tim.h
  • TIM_ICPOLARITY_RISING : stm32wbxx_hal_tim.h
  • TIM_ICPSC_DIV1 : stm32wbxx_hal_tim.h
  • TIM_ICPSC_DIV2 : stm32wbxx_hal_tim.h
  • TIM_ICPSC_DIV4 : stm32wbxx_hal_tim.h
  • TIM_ICPSC_DIV8 : stm32wbxx_hal_tim.h
  • TIM_ICSELECTION_DIRECTTI : stm32wbxx_hal_tim.h
  • TIM_ICSELECTION_INDIRECTTI : stm32wbxx_hal_tim.h
  • TIM_ICSELECTION_TRC : stm32wbxx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_BOTHEDGE : stm32wbxx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_FALLING : stm32wbxx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_RISING : stm32wbxx_hal_tim.h
  • TIM_IT_BREAK : stm32wbxx_hal_tim.h
  • TIM_IT_CC1 : stm32wbxx_hal_tim.h
  • TIM_IT_CC2 : stm32wbxx_hal_tim.h
  • TIM_IT_CC3 : stm32wbxx_hal_tim.h
  • TIM_IT_CC4 : stm32wbxx_hal_tim.h
  • TIM_IT_COM : stm32wbxx_hal_tim.h
  • TIM_IT_TRIGGER : stm32wbxx_hal_tim.h
  • TIM_IT_UPDATE : stm32wbxx_hal_tim.h
  • TIM_LOCKLEVEL_1 : stm32wbxx_hal_tim.h
  • TIM_LOCKLEVEL_2 : stm32wbxx_hal_tim.h
  • TIM_LOCKLEVEL_3 : stm32wbxx_hal_tim.h
  • TIM_LOCKLEVEL_OFF : stm32wbxx_hal_tim.h
  • TIM_MASTERSLAVEMODE_DISABLE : stm32wbxx_hal_tim.h
  • TIM_MASTERSLAVEMODE_ENABLE : stm32wbxx_hal_tim.h
  • TIM_OCFAST_DISABLE : stm32wbxx_hal_tim.h
  • TIM_OCFAST_ENABLE : stm32wbxx_hal_tim.h
  • TIM_OCIDLESTATE_RESET : stm32wbxx_hal_tim.h
  • TIM_OCIDLESTATE_SET : stm32wbxx_hal_tim.h
  • TIM_OCMODE_ACTIVE : stm32wbxx_hal_tim.h
  • TIM_OCMODE_ASSYMETRIC_PWM1 : stm32wbxx_hal_tim.h
  • TIM_OCMODE_ASSYMETRIC_PWM2 : stm32wbxx_hal_tim.h
  • TIM_OCMODE_COMBINED_PWM1 : stm32wbxx_hal_tim.h
  • TIM_OCMODE_COMBINED_PWM2 : stm32wbxx_hal_tim.h
  • TIM_OCMODE_FORCED_ACTIVE : stm32wbxx_hal_tim.h
  • TIM_OCMODE_FORCED_INACTIVE : stm32wbxx_hal_tim.h
  • TIM_OCMODE_INACTIVE : stm32wbxx_hal_tim.h
  • TIM_OCMODE_PWM1 : stm32wbxx_hal_tim.h
  • TIM_OCMODE_PWM2 : stm32wbxx_hal_tim.h
  • TIM_OCMODE_RETRIGERRABLE_OPM1 : stm32wbxx_hal_tim.h
  • TIM_OCMODE_RETRIGERRABLE_OPM2 : stm32wbxx_hal_tim.h
  • TIM_OCMODE_TIMING : stm32wbxx_hal_tim.h
  • TIM_OCMODE_TOGGLE : stm32wbxx_hal_tim.h
  • TIM_OCNIDLESTATE_RESET : stm32wbxx_hal_tim.h
  • TIM_OCNIDLESTATE_SET : stm32wbxx_hal_tim.h
  • TIM_OCNPOLARITY_HIGH : stm32wbxx_hal_tim.h
  • TIM_OCNPOLARITY_LOW : stm32wbxx_hal_tim.h
  • TIM_OCPOLARITY_HIGH : stm32wbxx_hal_tim.h
  • TIM_OCPOLARITY_LOW : stm32wbxx_hal_tim.h
  • TIM_OPMODE_REPETITIVE : stm32wbxx_hal_tim.h
  • TIM_OPMODE_SINGLE : stm32wbxx_hal_tim.h
  • TIM_OSSI_DISABLE : stm32wbxx_hal_tim.h
  • TIM_OSSI_ENABLE : stm32wbxx_hal_tim.h
  • TIM_OSSR_DISABLE : stm32wbxx_hal_tim.h
  • TIM_OSSR_ENABLE : stm32wbxx_hal_tim.h
  • TIM_OUTPUTNSTATE_DISABLE : stm32wbxx_hal_tim.h
  • TIM_OUTPUTNSTATE_ENABLE : stm32wbxx_hal_tim.h
  • TIM_OUTPUTSTATE_DISABLE : stm32wbxx_hal_tim.h
  • TIM_OUTPUTSTATE_ENABLE : stm32wbxx_hal_tim.h
  • TIM_POSITION_BRK_SOURCE : stm32wbxx_ll_tim.h
  • TIM_RESET_CAPTUREPOLARITY : stm32wbxx_hal_tim.h
  • TIM_RESET_ICPRESCALERVALUE : stm32wbxx_hal_tim.h
  • TIM_SET_CAPTUREPOLARITY : stm32wbxx_hal_tim.h
  • TIM_SET_ICPRESCALERVALUE : stm32wbxx_hal_tim.h
  • TIM_SLAVEMODE_COMBINED_RESETTRIGGER : stm32wbxx_hal_tim.h
  • TIM_SLAVEMODE_DISABLE : stm32wbxx_hal_tim.h
  • TIM_SLAVEMODE_EXTERNAL1 : stm32wbxx_hal_tim.h
  • TIM_SLAVEMODE_GATED : stm32wbxx_hal_tim.h
  • TIM_SLAVEMODE_RESET : stm32wbxx_hal_tim.h
  • TIM_SLAVEMODE_TRIGGER : stm32wbxx_hal_tim.h
  • TIM_TI1SELECTION_CH1 : stm32wbxx_hal_tim.h
  • TIM_TI1SELECTION_XORCOMBINATION : stm32wbxx_hal_tim.h
  • TIM_TIM16_TI1_GPIO : stm32wbxx_hal_tim_ex.h
  • TIM_TIM16_TI1_LSE : stm32wbxx_hal_tim_ex.h
  • TIM_TIM16_TI1_LSI : stm32wbxx_hal_tim_ex.h
  • TIM_TIM16_TI1_RTC : stm32wbxx_hal_tim_ex.h
  • TIM_TIM17_TI1_GPIO : stm32wbxx_hal_tim_ex.h
  • TIM_TIM17_TI1_HSE : stm32wbxx_hal_tim_ex.h
  • TIM_TIM17_TI1_MCO : stm32wbxx_hal_tim_ex.h
  • TIM_TIM17_TI1_MSI : stm32wbxx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC1_AWD1 : stm32wbxx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC1_AWD2 : stm32wbxx_hal_tim_ex.h
  • TIM_TIM1_ETR_ADC1_AWD3 : stm32wbxx_hal_tim_ex.h
  • TIM_TIM1_ETR_COMP1 : stm32wbxx_hal_tim_ex.h
  • TIM_TIM1_ETR_COMP2 : stm32wbxx_hal_tim_ex.h
  • TIM_TIM1_ETR_GPIO : stm32wbxx_hal_tim_ex.h
  • TIM_TIM1_TI1_COMP1 : stm32wbxx_hal_tim_ex.h
  • TIM_TIM1_TI1_GPIO : stm32wbxx_hal_tim_ex.h
  • TIM_TIM2_ETR_COMP1 : stm32wbxx_hal_tim_ex.h
  • TIM_TIM2_ETR_COMP2 : stm32wbxx_hal_tim_ex.h
  • TIM_TIM2_ETR_GPIO : stm32wbxx_hal_tim_ex.h
  • TIM_TIM2_ETR_LSE : stm32wbxx_hal_tim_ex.h
  • TIM_TIM2_ITR_NC : stm32wbxx_hal_tim_ex.h
  • TIM_TIM2_ITR_USB : stm32wbxx_hal_tim_ex.h
  • TIM_TIM2_TI4_COMP1 : stm32wbxx_hal_tim_ex.h
  • TIM_TIM2_TI4_COMP1_COMP2 : stm32wbxx_hal_tim_ex.h
  • TIM_TIM2_TI4_COMP2 : stm32wbxx_hal_tim_ex.h
  • TIM_TIM2_TI4_GPIO : stm32wbxx_hal_tim_ex.h
  • TIM_TRGO2_ENABLE : stm32wbxx_hal_tim.h
  • TIM_TRGO2_OC1 : stm32wbxx_hal_tim.h
  • TIM_TRGO2_OC1REF : stm32wbxx_hal_tim.h
  • TIM_TRGO2_OC2REF : stm32wbxx_hal_tim.h
  • TIM_TRGO2_OC3REF : stm32wbxx_hal_tim.h
  • TIM_TRGO2_OC4REF : stm32wbxx_hal_tim.h
  • TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING : stm32wbxx_hal_tim.h
  • TIM_TRGO2_OC4REF_RISING_OC6REF_RISING : stm32wbxx_hal_tim.h
  • TIM_TRGO2_OC4REF_RISINGFALLING : stm32wbxx_hal_tim.h
  • TIM_TRGO2_OC5REF : stm32wbxx_hal_tim.h
  • TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING : stm32wbxx_hal_tim.h
  • TIM_TRGO2_OC5REF_RISING_OC6REF_RISING : stm32wbxx_hal_tim.h
  • TIM_TRGO2_OC6REF : stm32wbxx_hal_tim.h
  • TIM_TRGO2_OC6REF_RISINGFALLING : stm32wbxx_hal_tim.h
  • TIM_TRGO2_RESET : stm32wbxx_hal_tim.h
  • TIM_TRGO2_UPDATE : stm32wbxx_hal_tim.h
  • TIM_TRGO_ENABLE : stm32wbxx_hal_tim.h
  • TIM_TRGO_OC1 : stm32wbxx_hal_tim.h
  • TIM_TRGO_OC1REF : stm32wbxx_hal_tim.h
  • TIM_TRGO_OC2REF : stm32wbxx_hal_tim.h
  • TIM_TRGO_OC3REF : stm32wbxx_hal_tim.h
  • TIM_TRGO_OC4REF : stm32wbxx_hal_tim.h
  • TIM_TRGO_RESET : stm32wbxx_hal_tim.h
  • TIM_TRGO_UPDATE : stm32wbxx_hal_tim.h
  • TIM_TRIGGERPOLARITY_BOTHEDGE : stm32wbxx_hal_tim.h
  • TIM_TRIGGERPOLARITY_FALLING : stm32wbxx_hal_tim.h
  • TIM_TRIGGERPOLARITY_INVERTED : stm32wbxx_hal_tim.h
  • TIM_TRIGGERPOLARITY_NONINVERTED : stm32wbxx_hal_tim.h
  • TIM_TRIGGERPOLARITY_RISING : stm32wbxx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV1 : stm32wbxx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV2 : stm32wbxx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV4 : stm32wbxx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV8 : stm32wbxx_hal_tim.h
  • TIM_TS_ETRF : stm32wbxx_hal_tim.h
  • TIM_TS_ITR0 : stm32wbxx_hal_tim.h
  • TIM_TS_ITR1 : stm32wbxx_hal_tim.h
  • TIM_TS_ITR2 : stm32wbxx_hal_tim.h
  • TIM_TS_ITR3 : stm32wbxx_hal_tim.h
  • TIM_TS_NONE : stm32wbxx_hal_tim.h
  • TIM_TS_TI1F_ED : stm32wbxx_hal_tim.h
  • TIM_TS_TI1FP1 : stm32wbxx_hal_tim.h
  • TIM_TS_TI2FP2 : stm32wbxx_hal_tim.h
  • TIMEOUT : stm32wbxx_hal_lptim.c
  • TIMING_CLEAR_MASK : stm32wbxx_hal_i2c.c , stm32wbxx_hal_smbus.c
  • TIMx_AF1_BKCOMP1E : stm32wbxx_ll_tim.h
  • TIMx_AF1_BKCOMP1P : stm32wbxx_ll_tim.h
  • TIMx_AF1_BKCOMP2E : stm32wbxx_ll_tim.h
  • TIMx_AF1_BKCOMP2P : stm32wbxx_ll_tim.h
  • TIMx_AF1_BKINE : stm32wbxx_ll_tim.h
  • TIMx_AF1_BKINP : stm32wbxx_ll_tim.h
  • TIMx_AF1_ETRSEL : stm32wbxx_hal_tim.c , stm32wbxx_ll_tim.h
  • TIMx_AF2_BK2COMP1E : stm32wbxx_ll_tim.h
  • TIMx_AF2_BK2COMP1P : stm32wbxx_ll_tim.h
  • TIMx_AF2_BK2COMP2E : stm32wbxx_ll_tim.h
  • TIMx_AF2_BK2COMP2P : stm32wbxx_ll_tim.h
  • TIMx_AF2_BK2INE : stm32wbxx_ll_tim.h
  • TIMx_AF2_BK2INP : stm32wbxx_ll_tim.h
  • TIMx_OR_RMP_MASK : stm32wbxx_ll_tim.h
  • TIMx_OR_RMP_SHIFT : stm32wbxx_ll_tim.h
  • TSC_ACQ_MODE_NORMAL : stm32wbxx_hal_tsc.h
  • TSC_ACQ_MODE_SYNCHRO : stm32wbxx_hal_tsc.h
  • TSC_CTPH_10CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPH_11CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPH_12CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPH_13CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPH_14CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPH_15CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPH_16CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPH_1CYCLE : stm32wbxx_hal_tsc.h
  • TSC_CTPH_2CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPH_3CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPH_4CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPH_5CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPH_6CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPH_7CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPH_8CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPH_9CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPL_10CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPL_11CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPL_12CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPL_13CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPL_14CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPL_15CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPL_16CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPL_1CYCLE : stm32wbxx_hal_tsc.h
  • TSC_CTPL_2CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPL_3CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPL_4CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPL_5CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPL_6CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPL_7CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPL_8CYCLES : stm32wbxx_hal_tsc.h
  • TSC_CTPL_9CYCLES : stm32wbxx_hal_tsc.h
  • TSC_FLAG_EOA : stm32wbxx_hal_tsc.h
  • TSC_FLAG_MCE : stm32wbxx_hal_tsc.h
  • TSC_GROUP1 : stm32wbxx_hal_tsc.h
  • TSC_GROUP1_IO1 : stm32wbxx_hal_tsc.h
  • TSC_GROUP1_IO2 : stm32wbxx_hal_tsc.h
  • TSC_GROUP1_IO3 : stm32wbxx_hal_tsc.h
  • TSC_GROUP1_IO4 : stm32wbxx_hal_tsc.h
  • TSC_GROUP2 : stm32wbxx_hal_tsc.h
  • TSC_GROUP2_IO1 : stm32wbxx_hal_tsc.h
  • TSC_GROUP2_IO2 : stm32wbxx_hal_tsc.h
  • TSC_GROUP2_IO3 : stm32wbxx_hal_tsc.h
  • TSC_GROUP2_IO4 : stm32wbxx_hal_tsc.h
  • TSC_GROUP3 : stm32wbxx_hal_tsc.h
  • TSC_GROUP3_IO1 : stm32wbxx_hal_tsc.h
  • TSC_GROUP3_IO2 : stm32wbxx_hal_tsc.h
  • TSC_GROUP3_IO3 : stm32wbxx_hal_tsc.h
  • TSC_GROUP3_IO4 : stm32wbxx_hal_tsc.h
  • TSC_GROUP4 : stm32wbxx_hal_tsc.h
  • TSC_GROUP4_IO1 : stm32wbxx_hal_tsc.h
  • TSC_GROUP4_IO2 : stm32wbxx_hal_tsc.h
  • TSC_GROUP4_IO3 : stm32wbxx_hal_tsc.h
  • TSC_GROUP4_IO4 : stm32wbxx_hal_tsc.h
  • TSC_GROUP5 : stm32wbxx_hal_tsc.h
  • TSC_GROUP5_IO1 : stm32wbxx_hal_tsc.h
  • TSC_GROUP5_IO2 : stm32wbxx_hal_tsc.h
  • TSC_GROUP5_IO3 : stm32wbxx_hal_tsc.h
  • TSC_GROUP5_IO4 : stm32wbxx_hal_tsc.h
  • TSC_GROUP6 : stm32wbxx_hal_tsc.h
  • TSC_GROUP6_IO1 : stm32wbxx_hal_tsc.h
  • TSC_GROUP6_IO2 : stm32wbxx_hal_tsc.h
  • TSC_GROUP6_IO3 : stm32wbxx_hal_tsc.h
  • TSC_GROUP6_IO4 : stm32wbxx_hal_tsc.h
  • TSC_GROUP7 : stm32wbxx_hal_tsc.h
  • TSC_GROUP7_IO1 : stm32wbxx_hal_tsc.h
  • TSC_GROUP7_IO2 : stm32wbxx_hal_tsc.h
  • TSC_GROUP7_IO3 : stm32wbxx_hal_tsc.h
  • TSC_GROUP7_IO4 : stm32wbxx_hal_tsc.h
  • TSC_IODEF_IN_FLOAT : stm32wbxx_hal_tsc.h
  • TSC_IODEF_OUT_PP_LOW : stm32wbxx_hal_tsc.h
  • TSC_IT_EOA : stm32wbxx_hal_tsc.h
  • TSC_IT_MCE : stm32wbxx_hal_tsc.h
  • TSC_MCV_1023 : stm32wbxx_hal_tsc.h
  • TSC_MCV_16383 : stm32wbxx_hal_tsc.h
  • TSC_MCV_2047 : stm32wbxx_hal_tsc.h
  • TSC_MCV_255 : stm32wbxx_hal_tsc.h
  • TSC_MCV_4095 : stm32wbxx_hal_tsc.h
  • TSC_MCV_511 : stm32wbxx_hal_tsc.h
  • TSC_MCV_8191 : stm32wbxx_hal_tsc.h
  • TSC_PG_PRESC_DIV1 : stm32wbxx_hal_tsc.h
  • TSC_PG_PRESC_DIV128 : stm32wbxx_hal_tsc.h
  • TSC_PG_PRESC_DIV16 : stm32wbxx_hal_tsc.h
  • TSC_PG_PRESC_DIV2 : stm32wbxx_hal_tsc.h
  • TSC_PG_PRESC_DIV32 : stm32wbxx_hal_tsc.h
  • TSC_PG_PRESC_DIV4 : stm32wbxx_hal_tsc.h
  • TSC_PG_PRESC_DIV64 : stm32wbxx_hal_tsc.h
  • TSC_PG_PRESC_DIV8 : stm32wbxx_hal_tsc.h
  • TSC_SS_PRESC_DIV1 : stm32wbxx_hal_tsc.h
  • TSC_SS_PRESC_DIV2 : stm32wbxx_hal_tsc.h
  • TSC_SYNC_POLARITY_FALLING : stm32wbxx_hal_tsc.h
  • TSC_SYNC_POLARITY_RISING : stm32wbxx_hal_tsc.h
  • TX_FIFO_DEPTH : stm32wbxx_hal_uart_ex.c , stm32wbxx_hal_smartcard_ex.c , stm32wbxx_hal_usart_ex.c
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

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- u -

  • UART_ADDRESS_DETECT_4B : stm32wbxx_hal_uart_ex.h
  • UART_ADDRESS_DETECT_7B : stm32wbxx_hal_uart_ex.h
  • UART_ADVFEATURE_AUTOBAUDRATE_DISABLE : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ENABLE : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_INIT : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_DATAINV_DISABLE : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_DATAINV_ENABLE : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_DATAINVERT_INIT : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_DMA_DISABLEONRXERROR : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_DMA_ENABLEONRXERROR : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_DMADISABLEONERROR_INIT : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_DISABLE : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_ENABLE : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_MSBFIRST_INIT : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_MUTEMODE_DISABLE : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_MUTEMODE_ENABLE : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_NO_INIT : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_OVERRUN_DISABLE : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_OVERRUN_ENABLE : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_RXINV_DISABLE : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_RXINV_ENABLE : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_RXINVERT_INIT : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_RXOVERRUNDISABLE_INIT : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_STOPMODE_DISABLE : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_STOPMODE_ENABLE : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_SWAP_DISABLE : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_SWAP_ENABLE : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_SWAP_INIT : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_TXINV_DISABLE : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_TXINV_ENABLE : stm32wbxx_hal_uart.h
  • UART_ADVFEATURE_TXINVERT_INIT : stm32wbxx_hal_uart.h
  • UART_AUTOBAUD_REQUEST : stm32wbxx_hal_uart.h
  • UART_BRR_MAX : stm32wbxx_hal_uart.c
  • UART_BRR_MIN : stm32wbxx_hal_uart.c
  • UART_CLEAR_CMF : stm32wbxx_hal_uart.h
  • UART_CLEAR_CTSF : stm32wbxx_hal_uart.h
  • UART_CLEAR_FEF : stm32wbxx_hal_uart.h
  • UART_CLEAR_IDLEF : stm32wbxx_hal_uart.h
  • UART_CLEAR_LBDF : stm32wbxx_hal_uart.h
  • UART_CLEAR_NEF : stm32wbxx_hal_uart.h
  • UART_CLEAR_OREF : stm32wbxx_hal_uart.h
  • UART_CLEAR_PEF : stm32wbxx_hal_uart.h
  • UART_CLEAR_RTOF : stm32wbxx_hal_uart.h
  • UART_CLEAR_TCF : stm32wbxx_hal_uart.h
  • UART_CLEAR_TXFECF : stm32wbxx_hal_uart.h
  • UART_CLEAR_WUF : stm32wbxx_hal_uart.h
  • UART_CR1_DEAT_ADDRESS_LSB_POS : stm32wbxx_hal_uart.h
  • UART_CR1_DEDT_ADDRESS_LSB_POS : stm32wbxx_hal_uart.h
  • UART_CR2_ADDRESS_LSB_POS : stm32wbxx_hal_uart.h
  • UART_DE_POLARITY_HIGH : stm32wbxx_hal_uart.h
  • UART_DE_POLARITY_LOW : stm32wbxx_hal_uart.h
  • UART_DIV_LPUART : stm32wbxx_hal_uart.h
  • UART_DIV_SAMPLING16 : stm32wbxx_hal_uart.h
  • UART_DIV_SAMPLING8 : stm32wbxx_hal_uart.h
  • UART_DMA_RX_DISABLE : stm32wbxx_hal_uart.h
  • UART_DMA_RX_ENABLE : stm32wbxx_hal_uart.h
  • UART_DMA_TX_DISABLE : stm32wbxx_hal_uart.h
  • UART_DMA_TX_ENABLE : stm32wbxx_hal_uart.h
  • UART_FIFOMODE_DISABLE : stm32wbxx_hal_uart_ex.h
  • UART_FIFOMODE_ENABLE : stm32wbxx_hal_uart_ex.h
  • UART_FLAG_ABRE : stm32wbxx_hal_uart.h
  • UART_FLAG_ABRF : stm32wbxx_hal_uart.h
  • UART_FLAG_BUSY : stm32wbxx_hal_uart.h
  • UART_FLAG_CMF : stm32wbxx_hal_uart.h
  • UART_FLAG_CTS : stm32wbxx_hal_uart.h
  • UART_FLAG_CTSIF : stm32wbxx_hal_uart.h
  • UART_FLAG_FE : stm32wbxx_hal_uart.h
  • UART_FLAG_IDLE : stm32wbxx_hal_uart.h
  • UART_FLAG_LBDF : stm32wbxx_hal_uart.h
  • UART_FLAG_NE : stm32wbxx_hal_uart.h
  • UART_FLAG_ORE : stm32wbxx_hal_uart.h
  • UART_FLAG_PE : stm32wbxx_hal_uart.h
  • UART_FLAG_REACK : stm32wbxx_hal_uart.h
  • UART_FLAG_RTOF : stm32wbxx_hal_uart.h
  • UART_FLAG_RWU : stm32wbxx_hal_uart.h
  • UART_FLAG_RXFF : stm32wbxx_hal_uart.h
  • UART_FLAG_RXFNE : stm32wbxx_hal_uart.h
  • UART_FLAG_RXFT : stm32wbxx_hal_uart.h
  • UART_FLAG_RXNE : stm32wbxx_hal_uart.h
  • UART_FLAG_SBKF : stm32wbxx_hal_uart.h
  • UART_FLAG_TC : stm32wbxx_hal_uart.h
  • UART_FLAG_TEACK : stm32wbxx_hal_uart.h
  • UART_FLAG_TXE : stm32wbxx_hal_uart.h
  • UART_FLAG_TXFE : stm32wbxx_hal_uart.h
  • UART_FLAG_TXFNF : stm32wbxx_hal_uart.h
  • UART_FLAG_TXFT : stm32wbxx_hal_uart.h
  • UART_FLAG_WUF : stm32wbxx_hal_uart.h
  • UART_GET_DIV_FACTOR : stm32wbxx_hal_uart.h
  • UART_GETCLOCKSOURCE : stm32wbxx_hal_uart_ex.h
  • UART_HALF_DUPLEX_DISABLE : stm32wbxx_hal_uart.h
  • UART_HALF_DUPLEX_ENABLE : stm32wbxx_hal_uart.h
  • UART_HWCONTROL_CTS : stm32wbxx_hal_uart.h
  • UART_HWCONTROL_NONE : stm32wbxx_hal_uart.h
  • UART_HWCONTROL_RTS : stm32wbxx_hal_uart.h
  • UART_HWCONTROL_RTS_CTS : stm32wbxx_hal_uart.h
  • UART_INSTANCE_LOWPOWER : stm32wbxx_hal_uart.h
  • UART_IT_CM : stm32wbxx_hal_uart.h
  • UART_IT_CTS : stm32wbxx_hal_uart.h
  • UART_IT_ERR : stm32wbxx_hal_uart.h
  • UART_IT_FE : stm32wbxx_hal_uart.h
  • UART_IT_IDLE : stm32wbxx_hal_uart.h
  • UART_IT_LBD : stm32wbxx_hal_uart.h
  • UART_IT_MASK : stm32wbxx_hal_uart.h
  • UART_IT_NE : stm32wbxx_hal_uart.h
  • UART_IT_ORE : stm32wbxx_hal_uart.h
  • UART_IT_PE : stm32wbxx_hal_uart.h
  • UART_IT_RTO : stm32wbxx_hal_uart.h
  • UART_IT_RXFF : stm32wbxx_hal_uart.h
  • UART_IT_RXFNE : stm32wbxx_hal_uart.h
  • UART_IT_RXFT : stm32wbxx_hal_uart.h
  • UART_IT_RXNE : stm32wbxx_hal_uart.h
  • UART_IT_TC : stm32wbxx_hal_uart.h
  • UART_IT_TXE : stm32wbxx_hal_uart.h
  • UART_IT_TXFE : stm32wbxx_hal_uart.h
  • UART_IT_TXFNF : stm32wbxx_hal_uart.h
  • UART_IT_TXFT : stm32wbxx_hal_uart.h
  • UART_IT_WUF : stm32wbxx_hal_uart.h
  • UART_LIN_DISABLE : stm32wbxx_hal_uart.h
  • UART_LIN_ENABLE : stm32wbxx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_10B : stm32wbxx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_11B : stm32wbxx_hal_uart.h
  • UART_MASK_COMPUTATION : stm32wbxx_hal_uart_ex.h
  • UART_MODE_RX : stm32wbxx_hal_uart.h
  • UART_MODE_TX : stm32wbxx_hal_uart.h
  • UART_MODE_TX_RX : stm32wbxx_hal_uart.h
  • UART_MUTE_MODE_REQUEST : stm32wbxx_hal_uart.h
  • UART_ONE_BIT_SAMPLE_DISABLE : stm32wbxx_hal_uart.h
  • UART_ONE_BIT_SAMPLE_ENABLE : stm32wbxx_hal_uart.h
  • UART_OVERSAMPLING_16 : stm32wbxx_hal_uart.h
  • UART_OVERSAMPLING_8 : stm32wbxx_hal_uart.h
  • UART_PARITY_EVEN : stm32wbxx_hal_uart.h
  • UART_PARITY_NONE : stm32wbxx_hal_uart.h
  • UART_PARITY_ODD : stm32wbxx_hal_uart.h
  • UART_PRESCALER_DIV1 : stm32wbxx_hal_uart.h
  • UART_PRESCALER_DIV10 : stm32wbxx_hal_uart.h
  • UART_PRESCALER_DIV12 : stm32wbxx_hal_uart.h
  • UART_PRESCALER_DIV128 : stm32wbxx_hal_uart.h
  • UART_PRESCALER_DIV16 : stm32wbxx_hal_uart.h
  • UART_PRESCALER_DIV2 : stm32wbxx_hal_uart.h
  • UART_PRESCALER_DIV256 : stm32wbxx_hal_uart.h
  • UART_PRESCALER_DIV32 : stm32wbxx_hal_uart.h
  • UART_PRESCALER_DIV4 : stm32wbxx_hal_uart.h
  • UART_PRESCALER_DIV6 : stm32wbxx_hal_uart.h
  • UART_PRESCALER_DIV64 : stm32wbxx_hal_uart.h
  • UART_PRESCALER_DIV8 : stm32wbxx_hal_uart.h
  • UART_RECEIVER_TIMEOUT_DISABLE : stm32wbxx_hal_uart.h
  • UART_RECEIVER_TIMEOUT_ENABLE : stm32wbxx_hal_uart.h
  • UART_RXDATA_FLUSH_REQUEST : stm32wbxx_hal_uart.h
  • UART_RXFIFO_THRESHOLD_1_2 : stm32wbxx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_1_4 : stm32wbxx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_1_8 : stm32wbxx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_3_4 : stm32wbxx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_7_8 : stm32wbxx_hal_uart_ex.h
  • UART_RXFIFO_THRESHOLD_8_8 : stm32wbxx_hal_uart_ex.h
  • UART_SENDBREAK_REQUEST : stm32wbxx_hal_uart.h
  • UART_STATE_DISABLE : stm32wbxx_hal_uart.h
  • UART_STATE_ENABLE : stm32wbxx_hal_uart.h
  • UART_STOPBITS_0_5 : stm32wbxx_hal_uart.h
  • UART_STOPBITS_1 : stm32wbxx_hal_uart.h
  • UART_STOPBITS_1_5 : stm32wbxx_hal_uart.h
  • UART_STOPBITS_2 : stm32wbxx_hal_uart.h
  • UART_TXDATA_FLUSH_REQUEST : stm32wbxx_hal_uart.h
  • UART_TXFIFO_THRESHOLD_1_2 : stm32wbxx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_1_4 : stm32wbxx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_1_8 : stm32wbxx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_3_4 : stm32wbxx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_7_8 : stm32wbxx_hal_uart_ex.h
  • UART_TXFIFO_THRESHOLD_8_8 : stm32wbxx_hal_uart_ex.h
  • UART_WAKEUP_ON_ADDRESS : stm32wbxx_hal_uart.h
  • UART_WAKEUP_ON_READDATA_NONEMPTY : stm32wbxx_hal_uart.h
  • UART_WAKEUP_ON_STARTBIT : stm32wbxx_hal_uart.h
  • UART_WAKEUPMETHOD_ADDRESSMARK : stm32wbxx_hal_uart.h
  • UART_WAKEUPMETHOD_IDLELINE : stm32wbxx_hal_uart.h
  • UART_WORDLENGTH_7B : stm32wbxx_hal_uart_ex.h
  • UART_WORDLENGTH_8B : stm32wbxx_hal_uart_ex.h
  • UART_WORDLENGTH_9B : stm32wbxx_hal_uart_ex.h
  • UID_BASE_ADDRESS : stm32wbxx_ll_utils.h
  • USART_BRR_MAX : stm32wbxx_hal_smartcard.c , stm32wbxx_hal_irda.c , stm32wbxx_hal_usart.c
  • USART_BRR_MIN : stm32wbxx_hal_usart.c , stm32wbxx_hal_irda.c , stm32wbxx_hal_smartcard.c
  • USART_CLEAR_FEF : stm32wbxx_hal_usart.h
  • USART_CLEAR_IDLEF : stm32wbxx_hal_usart.h
  • USART_CLEAR_NEF : stm32wbxx_hal_usart.h
  • USART_CLEAR_OREF : stm32wbxx_hal_usart.h
  • USART_CLEAR_PEF : stm32wbxx_hal_usart.h
  • USART_CLEAR_TCF : stm32wbxx_hal_usart.h
  • USART_CLEAR_TXFECF : stm32wbxx_hal_usart.h
  • USART_CLEAR_UDRF : stm32wbxx_hal_usart.h
  • USART_CLOCK_DISABLE : stm32wbxx_hal_usart.h
  • USART_CLOCK_ENABLE : stm32wbxx_hal_usart.h
  • USART_CR1_FIELDS : stm32wbxx_hal_uart.c , stm32wbxx_hal_smartcard.c , stm32wbxx_hal_usart.c
  • USART_CR2_CLK_FIELDS : stm32wbxx_hal_smartcard.c
  • USART_CR2_FIELDS : stm32wbxx_hal_usart.c , stm32wbxx_hal_smartcard.c
  • USART_CR3_FIELDS : stm32wbxx_hal_smartcard.c , stm32wbxx_hal_uart.c , stm32wbxx_hal_usart.c
  • USART_CR_MASK : stm32wbxx_hal_usart.h
  • USART_CR_POS : stm32wbxx_hal_usart.h
  • USART_DIV_SAMPLING8 : stm32wbxx_hal_usart.h
  • USART_DUMMY_DATA : stm32wbxx_hal_usart.c
  • USART_FIFOMODE_DISABLE : stm32wbxx_hal_usart_ex.h
  • USART_FIFOMODE_ENABLE : stm32wbxx_hal_usart_ex.h
  • USART_FLAG_BUSY : stm32wbxx_hal_usart.h
  • USART_FLAG_FE : stm32wbxx_hal_usart.h
  • USART_FLAG_IDLE : stm32wbxx_hal_usart.h
  • USART_FLAG_NE : stm32wbxx_hal_usart.h
  • USART_FLAG_ORE : stm32wbxx_hal_usart.h
  • USART_FLAG_PE : stm32wbxx_hal_usart.h
  • USART_FLAG_REACK : stm32wbxx_hal_usart.h
  • USART_FLAG_RXFF : stm32wbxx_hal_usart.h
  • USART_FLAG_RXFNE : stm32wbxx_hal_usart.h
  • USART_FLAG_RXFT : stm32wbxx_hal_usart.h
  • USART_FLAG_RXNE : stm32wbxx_hal_usart.h
  • USART_FLAG_TC : stm32wbxx_hal_usart.h
  • USART_FLAG_TEACK : stm32wbxx_hal_usart.h
  • USART_FLAG_TXE : stm32wbxx_hal_usart.h
  • USART_FLAG_TXFE : stm32wbxx_hal_usart.h
  • USART_FLAG_TXFNF : stm32wbxx_hal_usart.h
  • USART_FLAG_TXFT : stm32wbxx_hal_usart.h
  • USART_FLAG_UDR : stm32wbxx_hal_usart.h
  • USART_GET_DIV_FACTOR : stm32wbxx_hal_usart.h
  • USART_GETCLOCKSOURCE : stm32wbxx_hal_usart.h
  • USART_IT_ERR : stm32wbxx_hal_usart.h
  • USART_IT_FE : stm32wbxx_hal_usart.h
  • USART_IT_IDLE : stm32wbxx_hal_usart.h
  • USART_IT_MASK : stm32wbxx_hal_usart.h
  • USART_IT_NE : stm32wbxx_hal_usart.h
  • USART_IT_ORE : stm32wbxx_hal_usart.h
  • USART_IT_PE : stm32wbxx_hal_usart.h
  • USART_IT_RXFF : stm32wbxx_hal_usart.h
  • USART_IT_RXFNE : stm32wbxx_hal_usart.h
  • USART_IT_RXFT : stm32wbxx_hal_usart.h
  • USART_IT_RXNE : stm32wbxx_hal_usart.h
  • USART_IT_TC : stm32wbxx_hal_usart.h
  • USART_IT_TXE : stm32wbxx_hal_usart.h
  • USART_IT_TXFE : stm32wbxx_hal_usart.h
  • USART_IT_TXFNF : stm32wbxx_hal_usart.h
  • USART_IT_TXFT : stm32wbxx_hal_usart.h
  • USART_LASTBIT_DISABLE : stm32wbxx_hal_usart.h
  • USART_LASTBIT_ENABLE : stm32wbxx_hal_usart.h
  • USART_MASK_COMPUTATION : stm32wbxx_hal_usart_ex.h
  • USART_MODE_RX : stm32wbxx_hal_usart.h
  • USART_MODE_TX : stm32wbxx_hal_usart.h
  • USART_MODE_TX_RX : stm32wbxx_hal_usart.h
  • USART_NSS_HARD : stm32wbxx_hal_usart_ex.h
  • USART_NSS_SOFT : stm32wbxx_hal_usart_ex.h
  • USART_OVERSAMPLING_16 : stm32wbxx_hal_usart.h
  • USART_OVERSAMPLING_8 : stm32wbxx_hal_usart.h
  • USART_PARITY_EVEN : stm32wbxx_hal_usart.h
  • USART_PARITY_NONE : stm32wbxx_hal_usart.h
  • USART_PARITY_ODD : stm32wbxx_hal_usart.h
  • USART_PHASE_1EDGE : stm32wbxx_hal_usart.h
  • USART_PHASE_2EDGE : stm32wbxx_hal_usart.h
  • USART_POLARITY_HIGH : stm32wbxx_hal_usart.h
  • USART_POLARITY_LOW : stm32wbxx_hal_usart.h
  • USART_PRESCALER_DIV1 : stm32wbxx_hal_usart.h
  • USART_PRESCALER_DIV10 : stm32wbxx_hal_usart.h
  • USART_PRESCALER_DIV12 : stm32wbxx_hal_usart.h
  • USART_PRESCALER_DIV128 : stm32wbxx_hal_usart.h
  • USART_PRESCALER_DIV16 : stm32wbxx_hal_usart.h
  • USART_PRESCALER_DIV2 : stm32wbxx_hal_usart.h
  • USART_PRESCALER_DIV256 : stm32wbxx_hal_usart.h
  • USART_PRESCALER_DIV32 : stm32wbxx_hal_usart.h
  • USART_PRESCALER_DIV4 : stm32wbxx_hal_usart.h
  • USART_PRESCALER_DIV6 : stm32wbxx_hal_usart.h
  • USART_PRESCALER_DIV64 : stm32wbxx_hal_usart.h
  • USART_PRESCALER_DIV8 : stm32wbxx_hal_usart.h
  • USART_RXDATA_FLUSH_REQUEST : stm32wbxx_hal_usart.h
  • USART_RXFIFO_THRESHOLD_1_2 : stm32wbxx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_1_4 : stm32wbxx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_1_8 : stm32wbxx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_3_4 : stm32wbxx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_7_8 : stm32wbxx_hal_usart_ex.h
  • USART_RXFIFO_THRESHOLD_8_8 : stm32wbxx_hal_usart_ex.h
  • USART_SLAVEMODE_DISABLE : stm32wbxx_hal_usart_ex.h
  • USART_SLAVEMODE_ENABLE : stm32wbxx_hal_usart_ex.h
  • USART_STOPBITS_0_5 : stm32wbxx_hal_usart.h
  • USART_STOPBITS_1 : stm32wbxx_hal_usart.h
  • USART_STOPBITS_1_5 : stm32wbxx_hal_usart.h
  • USART_STOPBITS_2 : stm32wbxx_hal_usart.h
  • USART_TEACK_REACK_TIMEOUT : stm32wbxx_hal_usart.c
  • USART_TXDATA_FLUSH_REQUEST : stm32wbxx_hal_usart.h
  • USART_TXFIFO_THRESHOLD_1_2 : stm32wbxx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_1_4 : stm32wbxx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_1_8 : stm32wbxx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_3_4 : stm32wbxx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_7_8 : stm32wbxx_hal_usart_ex.h
  • USART_TXFIFO_THRESHOLD_8_8 : stm32wbxx_hal_usart_ex.h
  • USART_WORDLENGTH_7B : stm32wbxx_hal_usart_ex.h
  • USART_WORDLENGTH_8B : stm32wbxx_hal_usart_ex.h
  • USART_WORDLENGTH_9B : stm32wbxx_hal_usart_ex.h
  • USB_CNTRX_BLSIZE : stm32wbxx_hal_pcd.h
  • USB_CNTRX_NBLK_MSK : stm32wbxx_hal_pcd.h
  • USB_EP0StartXfer : stm32wbxx_hal_pcd.h
  • USB_WAKEUP_EXTI_LINE : stm32wbxx_hal_pcd.h
  • USE_HAL_ADC_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_HAL_COMP_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_HAL_CRYP_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_HAL_I2C_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_HAL_IRDA_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_HAL_LPTIM_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_HAL_PCD_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_HAL_PKA_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_HAL_QSPI_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_HAL_RNG_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_HAL_RTC_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_HAL_SAI_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_HAL_SMARTCARD_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_HAL_SMBUS_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_HAL_SPI_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_HAL_TIM_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_HAL_TSC_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_HAL_UART_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_HAL_USART_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_HAL_WWDG_REGISTER_CALLBACKS : stm32wbxx_hal_conf.h
  • USE_RTOS : stm32wbxx_hal_conf.h
  • USE_SPI_CRC : stm32wbxx_hal_conf.h
  • UTILS_HCLK2_MAX : stm32wbxx_ll_utils.c
  • UTILS_MAX_FREQUENCY_SCALE1 : stm32wbxx_ll_utils.c
  • UTILS_MAX_FREQUENCY_SCALE2 : stm32wbxx_ll_utils.c
  • UTILS_PLLVCO_INPUT_MAX : stm32wbxx_ll_utils.c
  • UTILS_PLLVCO_INPUT_MIN : stm32wbxx_ll_utils.c
  • UTILS_PLLVCO_OUTPUT_MAX : stm32wbxx_ll_utils.c
  • UTILS_PLLVCO_OUTPUT_MIN : stm32wbxx_ll_utils.c
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

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- v -

  • VDD_VALUE : stm32wbxx_hal_conf.h
  • VREFBUF_TIMEOUT_VALUE : stm32wbxx_hal.c
  • VREFINT_CAL_ADDR : stm32wbxx_ll_adc.h
  • VREFINT_CAL_VREF : stm32wbxx_ll_adc.h
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Globals

  • File List
  • Globals
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  • Functions
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  • Typedefs
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- w -

  • WWDG_EWI_DISABLE : stm32wbxx_hal_wwdg.h
  • WWDG_EWI_ENABLE : stm32wbxx_hal_wwdg.h
  • WWDG_FLAG_EWIF : stm32wbxx_hal_wwdg.h
  • WWDG_IT_EWI : stm32wbxx_hal_wwdg.h
  • WWDG_PRESCALER_1 : stm32wbxx_hal_wwdg.h
  • WWDG_PRESCALER_128 : stm32wbxx_hal_wwdg.h
  • WWDG_PRESCALER_16 : stm32wbxx_hal_wwdg.h
  • WWDG_PRESCALER_2 : stm32wbxx_hal_wwdg.h
  • WWDG_PRESCALER_32 : stm32wbxx_hal_wwdg.h
  • WWDG_PRESCALER_4 : stm32wbxx_hal_wwdg.h
  • WWDG_PRESCALER_64 : stm32wbxx_hal_wwdg.h
  • WWDG_PRESCALER_8 : stm32wbxx_hal_wwdg.h
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal.h File Reference

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Defines | Functions | Variables
stm32wbxx_hal.h File Reference

This file contains all the functions prototypes for the HAL module driver. More...

#include "stm32wbxx_hal_conf.h"
#include "stm32wbxx_ll_system.h"

Go to the source code of this file.

Defines

#define | HAL_TICK_FREQ_10HZ 100U
#define | HAL_TICK_FREQ_100HZ 10U
#define | HAL_TICK_FREQ_1KHZ 1U
#define | HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ
#define | SYSCFG_BOOT_MAINFLASH LL_SYSCFG_REMAP_FLASH
#define | SYSCFG_BOOT_SYSTEMFLASH LL_SYSCFG_REMAP_SYSTEMFLASH
#define | SYSCFG_BOOT_SRAM LL_SYSCFG_REMAP_SRAM
#define | SYSCFG_BOOT_QUADSPI LL_SYSCFG_REMAP_QUADSPI
#define | SYSCFG_IT_FPU_IOC SYSCFG_CFGR1_FPU_IE_0
#define | SYSCFG_IT_FPU_DZC SYSCFG_CFGR1_FPU_IE_1
#define | SYSCFG_IT_FPU_UFC SYSCFG_CFGR1_FPU_IE_2
#define | SYSCFG_IT_FPU_OFC SYSCFG_CFGR1_FPU_IE_3
#define | SYSCFG_IT_FPU_IDC SYSCFG_CFGR1_FPU_IE_4
#define | SYSCFG_IT_FPU_IXC SYSCFG_CFGR1_FPU_IE_5
#define | SYSCFG_SRAM2WRP_PAGE0 LL_SYSCFG_SRAM2WRP_PAGE0
#define | SYSCFG_SRAM2WRP_PAGE1 LL_SYSCFG_SRAM2WRP_PAGE1
#define | SYSCFG_SRAM2WRP_PAGE2 LL_SYSCFG_SRAM2WRP_PAGE2
#define | SYSCFG_SRAM2WRP_PAGE3 LL_SYSCFG_SRAM2WRP_PAGE3
#define | SYSCFG_SRAM2WRP_PAGE4 LL_SYSCFG_SRAM2WRP_PAGE4
#define | SYSCFG_SRAM2WRP_PAGE5 LL_SYSCFG_SRAM2WRP_PAGE5
#define | SYSCFG_SRAM2WRP_PAGE6 LL_SYSCFG_SRAM2WRP_PAGE6
#define | SYSCFG_SRAM2WRP_PAGE7 LL_SYSCFG_SRAM2WRP_PAGE7
#define | SYSCFG_SRAM2WRP_PAGE8 LL_SYSCFG_SRAM2WRP_PAGE8
#define | SYSCFG_SRAM2WRP_PAGE9 LL_SYSCFG_SRAM2WRP_PAGE9
#define | SYSCFG_SRAM2WRP_PAGE10 LL_SYSCFG_SRAM2WRP_PAGE10
#define | SYSCFG_SRAM2WRP_PAGE11 LL_SYSCFG_SRAM2WRP_PAGE11
#define | SYSCFG_SRAM2WRP_PAGE12 LL_SYSCFG_SRAM2WRP_PAGE12
#define | SYSCFG_SRAM2WRP_PAGE13 LL_SYSCFG_SRAM2WRP_PAGE13
#define | SYSCFG_SRAM2WRP_PAGE14 LL_SYSCFG_SRAM2WRP_PAGE14
#define | SYSCFG_SRAM2WRP_PAGE15 LL_SYSCFG_SRAM2WRP_PAGE15
#define | SYSCFG_SRAM2WRP_PAGE16 LL_SYSCFG_SRAM2WRP_PAGE16
#define | SYSCFG_SRAM2WRP_PAGE17 LL_SYSCFG_SRAM2WRP_PAGE17
#define | SYSCFG_SRAM2WRP_PAGE18 LL_SYSCFG_SRAM2WRP_PAGE18
#define | SYSCFG_SRAM2WRP_PAGE19 LL_SYSCFG_SRAM2WRP_PAGE19
#define | SYSCFG_SRAM2WRP_PAGE20 LL_SYSCFG_SRAM2WRP_PAGE20
#define | SYSCFG_SRAM2WRP_PAGE21 LL_SYSCFG_SRAM2WRP_PAGE21
#define | SYSCFG_SRAM2WRP_PAGE22 LL_SYSCFG_SRAM2WRP_PAGE22
#define | SYSCFG_SRAM2WRP_PAGE23 LL_SYSCFG_SRAM2WRP_PAGE23
#define | SYSCFG_SRAM2WRP_PAGE24 LL_SYSCFG_SRAM2WRP_PAGE24
#define | SYSCFG_SRAM2WRP_PAGE25 LL_SYSCFG_SRAM2WRP_PAGE25
#define | SYSCFG_SRAM2WRP_PAGE26 LL_SYSCFG_SRAM2WRP_PAGE26
#define | SYSCFG_SRAM2WRP_PAGE27 LL_SYSCFG_SRAM2WRP_PAGE27
#define | SYSCFG_SRAM2WRP_PAGE28 LL_SYSCFG_SRAM2WRP_PAGE28
#define | SYSCFG_SRAM2WRP_PAGE29 LL_SYSCFG_SRAM2WRP_PAGE29
#define | SYSCFG_SRAM2WRP_PAGE30 LL_SYSCFG_SRAM2WRP_PAGE30
#define | SYSCFG_SRAM2WRP_PAGE31 LL_SYSCFG_SRAM2WRP_PAGE31
#define | SYSCFG_SRAM2WRP_PAGE32 LL_SYSCFG_SRAM2WRP_PAGE32
#define | SYSCFG_SRAM2WRP_PAGE33 LL_SYSCFG_SRAM2WRP_PAGE33
#define | SYSCFG_SRAM2WRP_PAGE34 LL_SYSCFG_SRAM2WRP_PAGE34
#define | SYSCFG_SRAM2WRP_PAGE35 LL_SYSCFG_SRAM2WRP_PAGE35
#define | SYSCFG_SRAM2WRP_PAGE36 LL_SYSCFG_SRAM2WRP_PAGE36
#define | SYSCFG_SRAM2WRP_PAGE37 LL_SYSCFG_SRAM2WRP_PAGE37
#define | SYSCFG_SRAM2WRP_PAGE38 LL_SYSCFG_SRAM2WRP_PAGE38
#define | SYSCFG_SRAM2WRP_PAGE39 LL_SYSCFG_SRAM2WRP_PAGE39
#define | SYSCFG_SRAM2WRP_PAGE40 LL_SYSCFG_SRAM2WRP_PAGE40
#define | SYSCFG_SRAM2WRP_PAGE41 LL_SYSCFG_SRAM2WRP_PAGE41
#define | SYSCFG_SRAM2WRP_PAGE42 LL_SYSCFG_SRAM2WRP_PAGE42
#define | SYSCFG_SRAM2WRP_PAGE43 LL_SYSCFG_SRAM2WRP_PAGE43
#define | SYSCFG_SRAM2WRP_PAGE44 LL_SYSCFG_SRAM2WRP_PAGE44
#define | SYSCFG_SRAM2WRP_PAGE45 LL_SYSCFG_SRAM2WRP_PAGE45
#define | SYSCFG_SRAM2WRP_PAGE46 LL_SYSCFG_SRAM2WRP_PAGE46
#define | SYSCFG_SRAM2WRP_PAGE47 LL_SYSCFG_SRAM2WRP_PAGE47
#define | SYSCFG_SRAM2WRP_PAGE48 LL_SYSCFG_SRAM2WRP_PAGE48
#define | SYSCFG_SRAM2WRP_PAGE49 LL_SYSCFG_SRAM2WRP_PAGE49
#define | SYSCFG_SRAM2WRP_PAGE50 LL_SYSCFG_SRAM2WRP_PAGE50
#define | SYSCFG_SRAM2WRP_PAGE51 LL_SYSCFG_SRAM2WRP_PAGE51
#define | SYSCFG_SRAM2WRP_PAGE52 LL_SYSCFG_SRAM2WRP_PAGE52
#define | SYSCFG_SRAM2WRP_PAGE53 LL_SYSCFG_SRAM2WRP_PAGE53
#define | SYSCFG_SRAM2WRP_PAGE54 LL_SYSCFG_SRAM2WRP_PAGE54
#define | SYSCFG_SRAM2WRP_PAGE55 LL_SYSCFG_SRAM2WRP_PAGE55
#define | SYSCFG_SRAM2WRP_PAGE56 LL_SYSCFG_SRAM2WRP_PAGE56
#define | SYSCFG_SRAM2WRP_PAGE57 LL_SYSCFG_SRAM2WRP_PAGE57
#define | SYSCFG_SRAM2WRP_PAGE58 LL_SYSCFG_SRAM2WRP_PAGE58
#define | SYSCFG_SRAM2WRP_PAGE59 LL_SYSCFG_SRAM2WRP_PAGE59
#define | SYSCFG_SRAM2WRP_PAGE60 LL_SYSCFG_SRAM2WRP_PAGE60
#define | SYSCFG_SRAM2WRP_PAGE61 LL_SYSCFG_SRAM2WRP_PAGE61
#define | SYSCFG_SRAM2WRP_PAGE62 LL_SYSCFG_SRAM2WRP_PAGE62
#define | SYSCFG_SRAM2WRP_PAGE63 LL_SYSCFG_SRAM2WRP_PAGE63
#define | SYSCFG_VREFBUF_VOLTAGE_SCALE0 LL_VREFBUF_VOLTAGE_SCALE0
#define | SYSCFG_VREFBUF_VOLTAGE_SCALE1 LL_VREFBUF_VOLTAGE_SCALE1
#define | SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0x00000000U
#define | SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ
#define | SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_SPF
#define | SYSCFG_FLAG_SRAM2_BUSY SYSCFG_SCSR_SRAM2BSY
#define | SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP
Fast-mode Plus driving capability on a specific GPIO.
#define | SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP
#define | SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP
#define | SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP
#define | HAL_SYSCFG_SECURE_ACCESS_AES1 LL_SYSCFG_SECURE_ACCESS_AES1
#define | HAL_SYSCFG_SECURE_ACCESS_AES2 LL_SYSCFG_SECURE_ACCESS_AES2
#define | HAL_SYSCFG_SECURE_ACCESS_PKA LL_SYSCFG_SECURE_ACCESS_PKA
#define | HAL_SYSCFG_SECURE_ACCESS_RNG LL_SYSCFG_SECURE_ACCESS_RNG
#define | __HAL_DBGMCU_FREEZE_TIM2() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_TIM2_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM2() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_TIM2_STOP)
#define | __HAL_DBGMCU_FREEZE_RTC() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_RTC_STOP)
#define | __HAL_DBGMCU_UNFREEZE_RTC() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_RTC_STOP)
#define | __HAL_DBGMCU_FREEZE_WWDG() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG_STOP)
#define | __HAL_DBGMCU_UNFREEZE_WWDG() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG_STOP)
#define | __HAL_DBGMCU_FREEZE_IWDG() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP)
#define | __HAL_DBGMCU_UNFREEZE_IWDG() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP)
#define | __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_I2C1_STOP)
#define | __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_I2C1_STOP)
#define | __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_I2C3_STOP)
#define | __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_I2C3_STOP)
#define | __HAL_DBGMCU_FREEZE_LPTIM1() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP)
#define | __HAL_DBGMCU_UNFREEZE_LPTIM1() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP)
#define | __HAL_DBGMCU_FREEZE_LPTIM2() LL_DBGMCU_APB1_GRP2_FreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP)
#define | __HAL_DBGMCU_UNFREEZE_LPTIM2() LL_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM1() LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM1_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM1() LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM1_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM16() LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM16_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM16() LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM16_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM17() LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM17_STOP)
#define | __HAL_DBGMCU_UNFREEZE_TIM17() LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM17_STOP)
#define | __HAL_C2_DBGMCU_FREEZE_TIM2() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP)
#define | __HAL_C2_DBGMCU_UNFREEZE_TIM2() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP)
#define | __HAL_C2_DBGMCU_FREEZE_RTC() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP)
#define | __HAL_C2_DBGMCU_UNFREEZE_RTC() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP)
#define | __HAL_C2_DBGMCU_FREEZE_IWDG() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP)
#define | __HAL_C2_DBGMCU_UNFREEZE_IWDG() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP)
#define | __HAL_C2_DBGMCU_FREEZE_I2C1_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP)
#define | __HAL_C2_DBGMCU_UNFREEZE_I2C1_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP)
#define | __HAL_C2_DBGMCU_FREEZE_I2C3_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP)
#define | __HAL_C2_DBGMCU_UNFREEZE_I2C3_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP)
#define | __HAL_C2_DBGMCU_FREEZE_LPTIM1() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP)
#define | __HAL_C2_DBGMCU_UNFREEZE_LPTIM1() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP)
#define | __HAL_C2_DBGMCU_FREEZE_LPTIM2() LL_C2_DBGMCU_APB1_GRP2_FreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP)
#define | __HAL_C2_DBGMCU_UNFREEZE_LPTIM2() LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP)
#define | __HAL_C2_DBGMCU_FREEZE_TIM1() LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP)
#define | __HAL_C2_DBGMCU_UNFREEZE_TIM1() LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP)
#define | __HAL_C2_DBGMCU_FREEZE_TIM16() LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP)
#define | __HAL_C2_DBGMCU_UNFREEZE_TIM16() LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP)
#define | __HAL_C2_DBGMCU_FREEZE_TIM17() LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP)
#define | __HAL_C2_DBGMCU_UNFREEZE_TIM17() LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP)
#define | __HAL_SYSCFG_REMAPMEMORY_FLASH() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_FLASH)
Main Flash memory mapped at 0x00000000.
#define | __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_SYSTEMFLASH)
System Flash memory mapped at 0x00000000.
#define | __HAL_SYSCFG_REMAPMEMORY_SRAM() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_SRAM)
Embedded SRAM mapped at 0x00000000.
#define | __HAL_SYSCFG_REMAPMEMORY_QUADSPI() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_QUADSPI)
QUADSPI mapped at 0x00000000.
#define | __HAL_SYSCFG_GET_BOOT_MODE() LL_SYSCFG_GetRemapMemory()
Return the boot mode as configured by user.
#define | __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
SRAM2 page 0 to 31 write protection enable macro.
#define | __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE(__SRAM2WRP__)
#define | __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE(__SRAM2WRP__)
SRAM2 page 32 to 63 write protection enable macro.
#define | __HAL_SYSCFG_SRAM2_WRP_UNLOCK() LL_SYSCFG_UnlockSRAM2WRP()
SRAM2 page write protection unlock prior to erase.
#define | __HAL_SYSCFG_SRAM2_ERASE() LL_SYSCFG_EnableSRAM2Erase()
SRAM2 erase.
#define | __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__)
Floating Point Unit interrupt enable/disable macros.
#define | __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__)
#define | __HAL_SYSCFG_BREAK_ECC_LOCK() LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_ECC)
SYSCFG Break ECC lock.
#define | __HAL_SYSCFG_BREAK_LOCKUP_LOCK() LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_LOCKUP)
SYSCFG Break Cortex-M4 Lockup lock.
#define | __HAL_SYSCFG_BREAK_PVD_LOCK() LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_PVD)
SYSCFG Break PVD lock.
#define | __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_SRAM2_PARITY)
SYSCFG Break SRAM2 parity lock.
#define | __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0U) ? 1U : 0U)
Check SYSCFG flag is set or not.
#define | __HAL_SYSCFG_CLEAR_FLAG() LL_SYSCFG_ClearFlag_SP()
Set the SPF bit to clear the SRAM Parity Error Flag.
#define | __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)
Fast mode Plus driving capability enable/disable macros.
#define | __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__)
#define | IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__)
#define | IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFU))
#define | IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)
#define | IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__)
#define | IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
#define | IS_SYSCFG_FASTMODEPLUS(__PIN__)
#define | IS_SYSCFG_SECURITY_ACCESS(__VALUE__)
#define | IS_TICKFREQ(FREQ)

Functions

HAL_StatusTypeDef | HAL_Init (void)
This function is used to initialize the HAL Library; it must be the first instruction to be executed in the main program (before to call any other HAL function), it performs the following: Configure the Flash prefetch, instruction and Data caches.
HAL_StatusTypeDef | HAL_DeInit (void)
This function de-Initializes common part of the HAL and stops the source of time base.
__weak void | HAL_MspInit (void)
Initialize the MSP.
__weak void | HAL_MspDeInit (void)
DeInitializes the MSP.
__weak HAL_StatusTypeDef | HAL_InitTick (uint32_t TickPriority)
This function configures the source of the time base: The time source is configured to have 1ms time base with a dedicated Tick interrupt priority.
__weak void | HAL_IncTick (void)
This function is called to increment a global variable "uwTick" used as application time base.
__weak void | HAL_Delay (uint32_t Delay)
This function provides minimum delay (in milliseconds) based on variable incremented.
__weak uint32_t | HAL_GetTick (void)
Provides a tick value in millisecond.
uint32_t | HAL_GetTickPrio (void)
This function returns a tick priority.
HAL_StatusTypeDef | HAL_SetTickFreq (uint32_t Freq)
Set new tick Freq.
uint32_t | HAL_GetTickFreq (void)
Return tick frequency.
__weak void | HAL_SuspendTick (void)
Suspend Tick increment.
__weak void | HAL_ResumeTick (void)
Resume Tick increment.
uint32_t | HAL_GetHalVersion (void)
Returns the HAL revision.
uint32_t | HAL_GetREVID (void)
Returns the device revision identifier.
uint32_t | HAL_GetDEVID (void)
Returns the device identifier.
uint32_t | HAL_GetUIDw0 (void)
Return the first word of the unique device identifier (UID based on 96 bits)
uint32_t | HAL_GetUIDw1 (void)
Return the second word of the unique device identifier (UID based on 96 bits)
uint32_t | HAL_GetUIDw2 (void)
Return the third word of the unique device identifier (UID based on 96 bits)
void | HAL_DBGMCU_EnableDBGSleepMode (void)
Enable the Debug Module during SLEEP mode.
void | HAL_DBGMCU_DisableDBGSleepMode (void)
Disable the Debug Module during SLEEP mode.
void | HAL_DBGMCU_EnableDBGStopMode (void)
Enable the Debug Module during STOP mode.
void | HAL_DBGMCU_DisableDBGStopMode (void)
Disable the Debug Module during STOP mode.
void | HAL_DBGMCU_EnableDBGStandbyMode (void)
Enable the Debug Module during STANDBY mode.
void | HAL_DBGMCU_DisableDBGStandbyMode (void)
Disable the Debug Module during STANDBY mode.
void | HAL_SYSCFG_SRAM2Erase (void)
Start a hardware SRAM2 erase operation.
void | HAL_SYSCFG_DisableSRAMFetch (void)
Disable CPU2 SRAM fetch (execution) (This bit can be set by Firmware and will only be reset by a Hardware reset, including a reset after Standby.)
uint32_t | HAL_SYSCFG_IsEnabledSRAMFetch (void)
Check if CPU2 SRAM fetch is enabled.
void | HAL_SYSCFG_VREFBUF_VoltageScalingConfig (uint32_t VoltageScaling)
Configure the internal voltage reference buffer voltage scale.
void | HAL_SYSCFG_VREFBUF_HighImpedanceConfig (uint32_t Mode)
Configure the internal voltage reference buffer high impedance mode.
void | HAL_SYSCFG_VREFBUF_TrimmingConfig (uint32_t TrimmingValue)
Tune the Internal Voltage Reference buffer (VREFBUF).
HAL_StatusTypeDef | HAL_SYSCFG_EnableVREFBUF (void)
Enable the Internal Voltage Reference buffer (VREFBUF).
void | HAL_SYSCFG_DisableVREFBUF (void)
Disable the Internal Voltage Reference buffer (VREFBUF).
void | HAL_SYSCFG_EnableIOBooster (void)
Enable the I/O analog switch voltage booster.
void | HAL_SYSCFG_DisableIOBooster (void)
Disable the I/O analog switch voltage booster.
void | HAL_SYSCFG_EnableIOVdd (void)
Enable the I/O analog switch supplied by VDD.
void | HAL_SYSCFG_DisableIOVdd (void)
Disable the I/O analog switch supplied by VDD.
void | HAL_SYSCFG_EnableSecurityAccess (uint32_t SecurityAccess)
Enable the access for security IP.
void | HAL_SYSCFG_DisableSecurityAccess (uint32_t SecurityAccess)
Disable the access for security IP.
uint32_t | HAL_SYSCFG_IsEnabledSecurityAccess (uint32_t SecurityAccess)
Indicate if access for security IP is enabled.

Variables

__IO uint32_t | uwTick
uint32_t | uwTickPrio
uint32_t | uwTickFreq

Detailed Description

This file contains all the functions prototypes for the HAL module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal.h.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_adc.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32wbxx_hal_adc.h File Reference

Header file of ADC HAL module. More...

#include "stm32wbxx_hal_def.h"
#include "stm32wbxx_ll_adc.h"
#include "stm32wbxx_hal_adc_ex.h"

Go to the source code of this file.

Data Structures

struct | ADC_OversamplingTypeDef
ADC group regular oversampling structure definition. More...
struct | ADC_InitTypeDef
Structure definition of ADC instance and ADC group regular. More...
struct | ADC_ChannelConfTypeDef
Structure definition of ADC channel for regular group. More...
struct | ADC_AnalogWDGConfTypeDef
Structure definition of ADC analog watchdog. More...
struct | ADC_InjectionConfigTypeDef
ADC group injected contexts queue configuration. More...
struct | __ADC_HandleTypeDef
ADC handle Structure definition. More...

Defines

#define | HAL_ADC_STATE_RESET (0x00000000UL)
HAL ADC state machine: ADC states definition (bitfields)
#define | HAL_ADC_STATE_READY (0x00000001UL)
#define | HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL)
#define | HAL_ADC_STATE_TIMEOUT (0x00000004UL)
#define | HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL)
#define | HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL)
#define | HAL_ADC_STATE_ERROR_DMA (0x00000040UL)
#define | HAL_ADC_STATE_REG_BUSY (0x00000100UL)
#define | HAL_ADC_STATE_REG_EOC (0x00000200UL)
#define | HAL_ADC_STATE_REG_OVR (0x00000400UL)
#define | HAL_ADC_STATE_REG_EOSMP (0x00000800UL)
#define | HAL_ADC_STATE_INJ_BUSY (0x00001000UL)
#define | HAL_ADC_STATE_INJ_EOC (0x00002000UL)
#define | HAL_ADC_STATE_INJ_JQOVF (0x00004000UL)
#define | HAL_ADC_STATE_AWD1 (0x00010000UL)
#define | HAL_ADC_STATE_AWD2 (0x00020000UL)
#define | HAL_ADC_STATE_AWD3 (0x00040000UL)
#define | HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL)
#define | HAL_ADC_ERROR_NONE (0x00U)
#define | HAL_ADC_ERROR_INTERNAL (0x01U)
#define | HAL_ADC_ERROR_OVR (0x02U)
#define | HAL_ADC_ERROR_DMA (0x04U)
#define | HAL_ADC_ERROR_JQOVF (0x08U)
#define | HAL_ADC_ERROR_INVALID_CALLBACK (0x10U)
#define | ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1)
#define | ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2)
#define | ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4)
#define | ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1)
#define | ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2)
#define | ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4)
#define | ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6)
#define | ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8)
#define | ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10)
#define | ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12)
#define | ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16)
#define | ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32)
#define | ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64)
#define | ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128)
#define | ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256)
#define | ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B)
#define | ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B)
#define | ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B)
#define | ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B)
#define | ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)
#define | ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT)
#define | ADC_SCAN_DISABLE (0x00000000UL)
#define | ADC_SCAN_ENABLE (0x00000001UL)
#define | ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE)
#define | ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO)
#define | ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)
#define | ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1)
#define | ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2)
#define | ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3)
#define | ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO)
#define | ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2)
#define | ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11)
#define | ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL)
#define | ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING)
#define | ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING)
#define | ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING)
#define | ADC_EOC_SINGLE_CONV (ADC_ISR_EOC)
#define | ADC_EOC_SEQ_CONV (ADC_ISR_EOS)
#define | ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED)
#define | ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN)
#define | ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1)
#define | ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2)
#define | ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3)
#define | ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4)
#define | ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5)
#define | ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6)
#define | ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7)
#define | ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8)
#define | ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9)
#define | ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10)
#define | ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11)
#define | ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12)
#define | ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13)
#define | ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14)
#define | ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15)
#define | ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16)
#define | ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5)
#define | ADC_SAMPLETIME_6CYCLES_5 (LL_ADC_SAMPLINGTIME_6CYCLES_5)
#define | ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5)
#define | ADC_SAMPLETIME_24CYCLES_5 (LL_ADC_SAMPLINGTIME_24CYCLES_5)
#define | ADC_SAMPLETIME_47CYCLES_5 (LL_ADC_SAMPLINGTIME_47CYCLES_5)
#define | ADC_SAMPLETIME_92CYCLES_5 (LL_ADC_SAMPLINGTIME_92CYCLES_5)
#define | ADC_SAMPLETIME_247CYCLES_5 (LL_ADC_SAMPLINGTIME_247CYCLES_5)
#define | ADC_SAMPLETIME_640CYCLES_5 (LL_ADC_SAMPLINGTIME_640CYCLES_5)
#define | ADC_CHANNEL_0 (LL_ADC_CHANNEL_0)
#define | ADC_CHANNEL_1 (LL_ADC_CHANNEL_1)
#define | ADC_CHANNEL_2 (LL_ADC_CHANNEL_2)
#define | ADC_CHANNEL_3 (LL_ADC_CHANNEL_3)
#define | ADC_CHANNEL_4 (LL_ADC_CHANNEL_4)
#define | ADC_CHANNEL_5 (LL_ADC_CHANNEL_5)
#define | ADC_CHANNEL_6 (LL_ADC_CHANNEL_6)
#define | ADC_CHANNEL_7 (LL_ADC_CHANNEL_7)
#define | ADC_CHANNEL_8 (LL_ADC_CHANNEL_8)
#define | ADC_CHANNEL_9 (LL_ADC_CHANNEL_9)
#define | ADC_CHANNEL_10 (LL_ADC_CHANNEL_10)
#define | ADC_CHANNEL_11 (LL_ADC_CHANNEL_11)
#define | ADC_CHANNEL_12 (LL_ADC_CHANNEL_12)
#define | ADC_CHANNEL_13 (LL_ADC_CHANNEL_13)
#define | ADC_CHANNEL_14 (LL_ADC_CHANNEL_14)
#define | ADC_CHANNEL_15 (LL_ADC_CHANNEL_15)
#define | ADC_CHANNEL_16 (LL_ADC_CHANNEL_16)
#define | ADC_CHANNEL_17 (LL_ADC_CHANNEL_17)
#define | ADC_CHANNEL_18 (LL_ADC_CHANNEL_18)
#define | ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT)
#define | ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR)
#define | ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT)
#define | ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1)
#define | ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2)
#define | ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3)
#define | ADC_ANALOGWATCHDOG_NONE (0x00000000UL)
#define | ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN)
#define | ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN)
#define | ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)
#define | ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN)
#define | ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN)
#define | ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)
#define | ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2)
#define | ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4)
#define | ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8)
#define | ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16)
#define | ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32)
#define | ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64)
#define | ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128)
#define | ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256)
#define | ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE)
#define | ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1)
#define | ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2)
#define | ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3)
#define | ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4)
#define | ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5)
#define | ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6)
#define | ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7)
#define | ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8)
#define | ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT)
#define | ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT)
#define | ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED)
#define | ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED)
#define | ADC_EOSMP_EVENT (ADC_FLAG_EOSMP)
#define | ADC_AWD1_EVENT (ADC_FLAG_AWD1)
#define | ADC_AWD2_EVENT (ADC_FLAG_AWD2)
#define | ADC_AWD3_EVENT (ADC_FLAG_AWD3)
#define | ADC_OVR_EVENT (ADC_FLAG_OVR)
#define | ADC_JQOVF_EVENT (ADC_FLAG_JQOVF)
#define | ADC_AWD_EVENT ADC_AWD1_EVENT
#define | ADC_IT_RDY ADC_IER_ADRDYIE
#define | ADC_IT_EOSMP ADC_IER_EOSMPIE
#define | ADC_IT_EOC ADC_IER_EOCIE
#define | ADC_IT_EOS ADC_IER_EOSIE
#define | ADC_IT_OVR ADC_IER_OVRIE
#define | ADC_IT_JEOC ADC_IER_JEOCIE
#define | ADC_IT_JEOS ADC_IER_JEOSIE
#define | ADC_IT_AWD1 ADC_IER_AWD1IE
#define | ADC_IT_AWD2 ADC_IER_AWD2IE
#define | ADC_IT_AWD3 ADC_IER_AWD3IE
#define | ADC_IT_JQOVF ADC_IER_JQOVFIE
#define | ADC_IT_AWD ADC_IT_AWD1
#define | ADC_FLAG_RDY ADC_ISR_ADRDY
#define | ADC_FLAG_EOSMP ADC_ISR_EOSMP
#define | ADC_FLAG_EOC ADC_ISR_EOC
#define | ADC_FLAG_EOS ADC_ISR_EOS
#define | ADC_FLAG_OVR ADC_ISR_OVR
#define | ADC_FLAG_JEOC ADC_ISR_JEOC
#define | ADC_FLAG_JEOS ADC_ISR_JEOS
#define | ADC_FLAG_AWD1 ADC_ISR_AWD1
#define | ADC_FLAG_AWD2 ADC_ISR_AWD2
#define | ADC_FLAG_AWD3 ADC_ISR_AWD3
#define | ADC_FLAG_JQOVF ADC_ISR_JQOVF
#define | ADC_GET_RESOLUTION(__HANDLE__) (LL_ADC_GetResolution((__HANDLE__)->Instance))
Return resolution bits in CFGR register RES[1:0] field.
#define | ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").
#define | ADC_STATE_CLR_SET MODIFY_REG
Simultaneously clear and set specific bits of the handle State.
#define | IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__))
Verify that a given value is aligned with the ADC resolution range.
#define | IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL)))
Verify the length of the scheduled regular conversions group.
#define | IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL)))
Verify the number of scheduled regular conversions in discontinuous mode.
#define | IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__)
Verify the ADC clock setting.
#define | IS_ADC_RESOLUTION(__RESOLUTION__)
Verify the ADC resolution setting.
#define | IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__)
Verify the ADC resolution setting when limited to 6 or 8 bits.
#define | IS_ADC_DATA_ALIGN(__ALIGN__)
Verify the ADC converted data alignment.
#define | IS_ADC_SCAN_MODE(__SCAN_MODE__)
Verify the ADC scan mode.
#define | IS_ADC_EXTTRIG_EDGE(__EDGE__)
Verify the ADC edge trigger setting for regular group.
#define | IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__)
Verify the ADC regular conversions external trigger.
#define | IS_ADC_EOC_SELECTION(__EOC_SELECTION__)
Verify the ADC regular conversions check for converted data availability.
#define | IS_ADC_OVERRUN(__OVR__)
Verify the ADC regular conversions overrun handling.
#define | IS_ADC_SAMPLE_TIME(__TIME__)
Verify the ADC conversions sampling time.
#define | IS_ADC_REGULAR_RANK(__CHANNEL__)
Verify the ADC regular channel setting.
#define | ADC_STOP_CONVERSION_TIMEOUT ( 5UL)
#define | ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US)
#define | __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)
Reset ADC handle state.
#define | __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
Enable ADC interrupt.
#define | __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
Disable ADC interrupt.
#define | __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
Checks if the specified ADC interrupt source is enabled or disabled.
#define | __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
Check whether the specified ADC flag is set or not.
#define | __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR) = (__FLAG__))
Clear the specified ADC flag.
#define | __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))
Helper macro to get ADC channel number in decimal format from literals ADC_CHANNEL_x.
#define | __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))
Helper macro to get ADC channel in literal format ADC_CHANNEL_x from number in decimal format.
#define | __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))
Helper macro to determine whether the selected channel corresponds to literal definitions of driver.
#define | __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))
Helper macro to convert a channel defined from parameter definition of a ADC internal channel (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), to its equivalent parameter definition of a ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...).
#define | __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))
Helper macro to determine whether the internal channel selected is available on the ADC instance selected.
#define | __HAL_ADC_COMMON_INSTANCE(__ADCx__) __LL_ADC_COMMON_INSTANCE((__ADCx__))
Helper macro to select the ADC common instance to which is belonging the selected ADC instance.
#define | __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))
Helper macro to check if all ADC instances sharing the same ADC common instance are disabled.
#define | __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))
Helper macro to define the ADC conversion data full-scale digital value corresponding to the selected ADC resolution.
#define | __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__)
Helper macro to convert the ADC conversion data from a resolution to another resolution.
#define | __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__, __ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value).
#define | __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate analog reference voltage (Vref+) (unit: mVolt) from ADC conversion data of internal voltage reference VrefInt.
#define | __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.
#define | __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__, __TEMPSENSOR_TYP_CALX_V__, __TEMPSENSOR_CALX_TEMP__, __VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Typedefs

typedef struct __ADC_HandleTypeDef | ADC_HandleTypeDef
ADC handle Structure definition.
typedef void(* | pADC_CallbackTypeDef )(ADC_HandleTypeDef *hadc)
HAL ADC Callback pointer definition.

Enumerations

enum HAL_ADC_CallbackIDTypeDef {
HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, HAL_ADC_ERROR_CB_ID = 0x03U,
HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID = 0x05U, HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U,
HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, HAL_ADC_MSPINIT_CB_ID = 0x09U, HAL_ADC_MSPDEINIT_CB_ID = 0x0AU
}
HAL ADC Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_ADC_Init (ADC_HandleTypeDef *hadc)
Initialize the ADC peripheral and regular group according to parameters specified in structure "ADC_InitTypeDef".
HAL_StatusTypeDef | HAL_ADC_DeInit (ADC_HandleTypeDef *hadc)
Deinitialize the ADC peripheral registers to their default reset values, with deinitialization of the ADC MSP.
__weak void | HAL_ADC_MspInit (ADC_HandleTypeDef *hadc)
Initialize the ADC MSP.
__weak void | HAL_ADC_MspDeInit (ADC_HandleTypeDef *hadc)
DeInitialize the ADC MSP.
HAL_StatusTypeDef | HAL_ADC_RegisterCallback (ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
Register a User ADC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_ADC_UnRegisterCallback (ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
Unregister a ADC Callback ADC callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_ADC_Start (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of regular group.
HAL_StatusTypeDef | HAL_ADC_Stop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_PollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for regular group conversion to be completed.
HAL_StatusTypeDef | HAL_ADC_PollForEvent (ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
Poll for ADC event.
HAL_StatusTypeDef | HAL_ADC_Start_IT (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of regular group with interruption.
HAL_StatusTypeDef | HAL_ADC_Stop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable interrution of end-of-conversion, disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_Start_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enable ADC, start conversion of regular group and transfer result through DMA.
HAL_StatusTypeDef | HAL_ADC_Stop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral.
uint32_t | HAL_ADC_GetValue (ADC_HandleTypeDef *hadc)
Get ADC regular group conversion result.
void | HAL_ADC_IRQHandler (ADC_HandleTypeDef *hadc)
Handle ADC interrupt request.
__weak void | HAL_ADC_ConvCpltCallback (ADC_HandleTypeDef *hadc)
Conversion complete callback in non-blocking mode.
__weak void | HAL_ADC_ConvHalfCpltCallback (ADC_HandleTypeDef *hadc)
Conversion DMA half-transfer callback in non-blocking mode.
__weak void | HAL_ADC_LevelOutOfWindowCallback (ADC_HandleTypeDef *hadc)
Analog watchdog 1 callback in non-blocking mode.
__weak void | HAL_ADC_ErrorCallback (ADC_HandleTypeDef *hadc)
ADC error callback in non-blocking mode (ADC conversion with interruption or transfer by DMA).
HAL_StatusTypeDef | HAL_ADC_ConfigChannel (ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
Configure a channel to be assigned to ADC group regular.
HAL_StatusTypeDef | HAL_ADC_AnalogWDGConfig (ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
Configure the analog watchdog.
uint32_t | HAL_ADC_GetState (ADC_HandleTypeDef *hadc)
Return the ADC handle state.
uint32_t | HAL_ADC_GetError (ADC_HandleTypeDef *hadc)
Return the ADC error code.
HAL_StatusTypeDef | ADC_ConversionStop (ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
Stop ADC conversion.
HAL_StatusTypeDef | ADC_Enable (ADC_HandleTypeDef *hadc)
Enable the selected ADC.
HAL_StatusTypeDef | ADC_Disable (ADC_HandleTypeDef *hadc)
Disable the selected ADC.
void | ADC_DMAConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
void | ADC_DMAHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
void | ADC_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.

Detailed Description

Header file of ADC HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_adc.h.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_adc_ex.h File Reference

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Data Structures | Defines | Functions
stm32wbxx_hal_adc_ex.h File Reference

Header file of ADC HAL extended module. More...

#include "stm32wbxx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | ADC_InjOversamplingTypeDef
ADC Injected Conversion Oversampling structure definition. More...
struct | ADC_InjectionConfTypeDef
Structure definition of ADC group injected and ADC channel affected to ADC group injected. More...

Defines

#define | ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE)
#define | ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)
#define | ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)
#define | ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4)
#define | ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)
#define | ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1)
#define | ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL)
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0)
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1)
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN)
#define | ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED)
#define | ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED)
#define | ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U)
#define | ADC_OFFSET_1 (LL_ADC_OFFSET_1)
#define | ADC_OFFSET_2 (LL_ADC_OFFSET_2)
#define | ADC_OFFSET_3 (LL_ADC_OFFSET_3)
#define | ADC_OFFSET_4 (LL_ADC_OFFSET_4)
#define | ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1)
#define | ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2)
#define | ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3)
#define | ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4)
#define | ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR)
#define | ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED)
#define | ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED)
#define | ADC_CFGR_FIELDS
#define | ADC_SMPR1_FIELDS
#define | ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY))
#define | ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL)
Test if conversion trigger of injected group is software start or external trigger.
#define | ADC_IS_INDEPENDENT(__HANDLE__) (SET)
Check whether or not ADC is independent.
#define | ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))
Set the selected injected Channel rank.
#define | ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos)
Configure ADC injected context queue.
#define | ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos)
Configure ADC discontinuous conversion mode for injected group.
#define | ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos)
Configure ADC discontinuous conversion mode for regular group.
#define | ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos)
Configure the number of discontinuous conversions for regular group.
#define | ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos)
Configure the ADC auto delay mode.
#define | ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos)
Configure ADC continuous conversion mode.
#define | ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CFGR_DMACFG_Pos)
Configure the ADC DMA continuous request.
#define | ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL))
Shift the offset with respect to the selected ADC resolution.
#define | ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL))
Shift the AWD1 threshold with respect to the selected ADC resolution.
#define | ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__)
Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution.
#define | ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__)
Clear Common Control Register.
#define | ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
Verify the ADC instance connected to the temperature sensor.
#define | ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
Verify the ADC instance connected to the battery voltage VBAT.
#define | ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
Verify the ADC instance connected to the internal voltage reference VREFINT.
#define | IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))
Verify the length of scheduled injected conversions group.
#define | IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
Calibration factor size verification (7 bits maximum).
#define | IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__)
Verify the ADC channel setting.
#define | IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__)
Verify the ADC channel setting in differential mode.
#define | IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__)
Verify the ADC single-ended input or differential mode setting.
#define | IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__)
Verify the ADC offset management setting.
#define | IS_ADC_INJECTED_RANK(__CHANNEL__)
Verify the ADC injected channel setting.
#define | IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__)
Verify the ADC injected conversions external trigger.
#define | IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__)
Verify the ADC edge trigger setting for injected group.
#define | IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__)
Verify the ADC analog watchdog setting.
#define | IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__)
Verify the ADC analog watchdog mode setting.
#define | IS_ADC_CONVERSION_GROUP(__CONVERSION__)
Verify the ADC conversion (regular or injected or both).
#define | IS_ADC_EVENT_TYPE(__EVENT__)
Verify the ADC event type.
#define | IS_ADC_OVERSAMPLING_RATIO(__RATIO__)
Verify the ADC oversampling ratio.
#define | IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__)
Verify the ADC oversampling shift.
#define | IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__)
Verify the ADC oversampling triggered mode.
#define | IS_ADC_REGOVERSAMPLING_MODE(__MODE__)
Verify the ADC oversampling regular conversion resumed or continued mode.
#define | IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET)
Verify the DFSDM mode configuration.
#define | ADC_CFGR_DFSDM(__HANDLE__) (0x0UL)
Return the DFSDM configuration mode.

Functions

HAL_StatusTypeDef | HAL_ADCEx_Calibration_Start (ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
Perform an ADC automatic self-calibration Calibration prerequisite: ADC must be disabled (execute this function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
uint32_t | HAL_ADCEx_Calibration_GetValue (ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
Get the calibration factor.
HAL_StatusTypeDef | HAL_ADCEx_Calibration_SetValue (ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
Set the calibration factor to overwrite automatic conversion result.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of injected group.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels.
HAL_StatusTypeDef | HAL_ADCEx_InjectedPollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for injected group conversion to be completed.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart_IT (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of injected group with interruption.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop_IT (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels, disable interruption of end-of-conversion.
uint32_t | HAL_ADCEx_InjectedGetValue (ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
Get ADC injected group conversion result.
__weak void | HAL_ADCEx_InjectedConvCpltCallback (ADC_HandleTypeDef *hadc)
Injected conversion complete callback in non-blocking mode.
__weak void | HAL_ADCEx_InjectedQueueOverflowCallback (ADC_HandleTypeDef *hadc)
Injected context queue overflow callback.
__weak void | HAL_ADCEx_LevelOutOfWindow2Callback (ADC_HandleTypeDef *hadc)
Analog watchdog 2 callback in non-blocking mode.
__weak void | HAL_ADCEx_LevelOutOfWindow3Callback (ADC_HandleTypeDef *hadc)
Analog watchdog 3 callback in non-blocking mode.
__weak void | HAL_ADCEx_EndOfSamplingCallback (ADC_HandleTypeDef *hadc)
End Of Sampling callback in non-blocking mode.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral if no conversion is on going on injected group.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of ADC groups regular and injected, disable interrution of end-of-conversion, disable ADC peripheral if no conversion is on going on injected group.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral if no conversion is on going on injected group.
HAL_StatusTypeDef | HAL_ADCEx_InjectedConfigChannel (ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected)
Configure a channel to be assigned to ADC group injected.
HAL_StatusTypeDef | HAL_ADCEx_EnableInjectedQueue (ADC_HandleTypeDef *hadc)
Enable Injected Queue.
HAL_StatusTypeDef | HAL_ADCEx_DisableInjectedQueue (ADC_HandleTypeDef *hadc)
Disable Injected Queue.
HAL_StatusTypeDef | HAL_ADCEx_DisableVoltageRegulator (ADC_HandleTypeDef *hadc)
Disable ADC voltage regulator.
HAL_StatusTypeDef | HAL_ADCEx_EnterADCDeepPowerDownMode (ADC_HandleTypeDef *hadc)
Enter ADC deep-power-down mode.

Detailed Description

Header file of ADC HAL extended module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_adc_ex.h.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_comp.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32wbxx_hal_comp.h File Reference

Header file of COMP HAL module. More...

#include "stm32wbxx_hal_def.h"
#include "stm32wbxx_ll_exti.h"

Go to the source code of this file.

Data Structures

struct | COMP_InitTypeDef
COMP Init structure definition. More...
struct | __COMP_HandleTypeDef
COMP Handle Structure definition. More...

Defines

#define | COMP_STATE_BITFIELD_LOCK (0x10U)
HAL COMP state machine: HAL COMP states definition.
#define | HAL_COMP_ERROR_NONE (0x00UL)
#define | HAL_COMP_ERROR_INVALID_CALLBACK (0x01UL)
#define | COMP_WINDOWMODE_DISABLE (0x00000000UL)
#define | COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE)
#define | COMP_POWERMODE_HIGHSPEED (0x00000000UL)
#define | COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0)
#define | COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_PWRMODE)
#define | COMP_INPUT_PLUS_IO1 (0x00000000UL)
#define | COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0)
#define | COMP_INPUT_PLUS_IO3 (COMP_CSR_INPSEL_1)
#define | COMP_INPUT_MINUS_1_4VREFINT ( COMP_CSR_SCALEN | COMP_CSR_BRGEN)
#define | COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)
#define | COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)
#define | COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN )
#define | COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 )
#define | COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)
#define | COMP_INPUT_MINUS_IO3 ( COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)
#define | COMP_INPUT_MINUS_IO4 (COMP_CSR_INMESEL_1 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)
#define | COMP_INPUT_MINUS_IO5 (COMP_CSR_INMESEL_1 | COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)
#define | COMP_HYSTERESIS_NONE (0x00000000UL)
#define | COMP_HYSTERESIS_LOW ( COMP_CSR_HYST_0)
#define | COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1 )
#define | COMP_HYSTERESIS_HIGH (COMP_CSR_HYST_1 | COMP_CSR_HYST_0)
#define | COMP_OUTPUTPOL_NONINVERTED (0x00000000UL)
#define | COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY)
#define | COMP_BLANKINGSRC_NONE (0x00000000UL)
#define | COMP_BLANKINGSRC_TIM1_OC5 (COMP_CSR_BLANKING_0)
#define | COMP_BLANKINGSRC_TIM2_OC3 (COMP_CSR_BLANKING_1)
#define | COMP_OUTPUT_LEVEL_LOW (0x00000000UL)
#define | COMP_OUTPUT_LEVEL_HIGH (0x00000001UL)
#define | COMP_TRIGGERMODE_NONE (0x00000000UL)
#define | COMP_TRIGGERMODE_IT_RISING (COMP_EXTI_IT | COMP_EXTI_RISING)
#define | COMP_TRIGGERMODE_IT_FALLING (COMP_EXTI_IT | COMP_EXTI_FALLING)
#define | COMP_TRIGGERMODE_IT_RISING_FALLING (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING)
#define | COMP_TRIGGERMODE_EVENT_RISING (COMP_EXTI_EVENT | COMP_EXTI_RISING)
#define | COMP_TRIGGERMODE_EVENT_FALLING (COMP_EXTI_EVENT | COMP_EXTI_FALLING)
#define | COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING)
#define | __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__)
Reset COMP handle state.
#define | COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE)
Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE").
#define | __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
Enable the specified comparator.
#define | __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
Disable the specified comparator.
#define | __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK)
Lock the specified comparator configuration.
#define | __HAL_COMP_IS_LOCKED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK)
Check whether the specified comparator is locked.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the COMP1 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the COMP1 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP1)
Generate a software interrupt on the COMP1 EXTI line.
#define | __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP1)
Enable the COMP1 EXTI line in event mode.
#define | __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP1)
Disable the COMP1 EXTI line in event mode.
#define | __HAL_COMP_COMP1_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP1)
Check whether the COMP1 EXTI line flag is set.
#define | __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP1)
Clear the COMP1 EXTI flag.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line rising edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the COMP2 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the COMP2 EXTI line rising & falling edge trigger.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line in interrupt mode.
#define | __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP2)
Generate a software interrupt on the COMP2 EXTI line.
#define | __HAL_COMP_COMP2_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP2)
Enable the COMP2 EXTI line in event mode.
#define | __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP2)
Disable the COMP2 EXTI line in event mode.
#define | __HAL_COMP_COMP2_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP2)
Check whether the COMP2 EXTI line flag is set.
#define | __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP2)
Clear the COMP2 EXTI flag.
#define | COMP_EXTI_LINE_COMP1 (LL_EXTI_LINE_20)
#define | COMP_EXTI_LINE_COMP2 (LL_EXTI_LINE_21)
#define | COMP_EXTI_IT (0x00000001UL)
#define | COMP_EXTI_EVENT (0x00000002UL)
#define | COMP_EXTI_RISING (0x00000010UL)
#define | COMP_EXTI_FALLING (0x00000020UL)
#define | COMP_GET_EXTI_LINE(__INSTANCE__)
Get the specified EXTI line for a comparator instance.
#define | IS_COMP_WINDOWMODE(__WINDOWMODE__)
#define | IS_COMP_POWERMODE(__POWERMODE__)
#define | IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)
#define | IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)
#define | IS_COMP_HYSTERESIS(__HYSTERESIS__)
#define | IS_COMP_OUTPUTPOL(__POL__)
#define | IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__)
#define | IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) (IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__))
#define | IS_COMP_TRIGGERMODE(__MODE__)
#define | IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__)

Typedefs

typedef struct __COMP_HandleTypeDef | COMP_HandleTypeDef
COMP Handle Structure definition.
typedef void(* | pCOMP_CallbackTypeDef )(COMP_HandleTypeDef *hcomp)
HAL COMP Callback pointer definition.

Enumerations

enum HAL_COMP_StateTypeDef {
HAL_COMP_STATE_RESET = 0x00U, HAL_COMP_STATE_RESET_LOCKED = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), HAL_COMP_STATE_READY = 0x01U, HAL_COMP_STATE_READY_LOCKED = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK),
HAL_COMP_STATE_BUSY = 0x02U, HAL_COMP_STATE_BUSY_LOCKED = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK)
}
enum | HAL_COMP_CallbackIDTypeDef { HAL_COMP_TRIGGER_CB_ID = 0x00U, HAL_COMP_MSPINIT_CB_ID = 0x01U, HAL_COMP_MSPDEINIT_CB_ID = 0x02U }
HAL COMP Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_COMP_Init (COMP_HandleTypeDef *hcomp)
Initialize the COMP according to the specified parameters in the COMP_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP peripheral.
__weak void | HAL_COMP_MspInit (COMP_HandleTypeDef *hcomp)
Initialize the COMP MSP.
__weak void | HAL_COMP_MspDeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP MSP.
HAL_StatusTypeDef | HAL_COMP_RegisterCallback (COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback)
Register a User COMP Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_COMP_UnRegisterCallback (COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID)
Unregister a COMP Callback COMP callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_COMP_Start (COMP_HandleTypeDef *hcomp)
Start the comparator.
HAL_StatusTypeDef | HAL_COMP_Stop (COMP_HandleTypeDef *hcomp)
Stop the comparator.
void | HAL_COMP_IRQHandler (COMP_HandleTypeDef *hcomp)
Comparator IRQ handler.
HAL_StatusTypeDef | HAL_COMP_Lock (COMP_HandleTypeDef *hcomp)
Lock the selected comparator configuration.
uint32_t | HAL_COMP_GetOutputLevel (COMP_HandleTypeDef *hcomp)
Return the output level (high or low) of the selected comparator.
__weak void | HAL_COMP_TriggerCallback (COMP_HandleTypeDef *hcomp)
Comparator trigger callback.
HAL_COMP_StateTypeDef | HAL_COMP_GetState (COMP_HandleTypeDef *hcomp)
Return the COMP handle state.
uint32_t | HAL_COMP_GetError (COMP_HandleTypeDef *hcomp)
Return the COMP error code.

Detailed Description

Header file of COMP HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_comp.h.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_cortex.h File Reference

  • File List
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  • Firmware
  • Drivers
  • STM32WBxx_HAL_Driver
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Data Structures | Defines | Functions
stm32wbxx_hal_cortex.h File Reference

Header file of CORTEX HAL module. More...

#include "stm32wbxx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | MPU_Region_InitTypeDef

Defines

#define | NVIC_PRIORITYGROUP_0 (0x00000007U)
#define | NVIC_PRIORITYGROUP_1 (0x00000006U)
#define | NVIC_PRIORITYGROUP_2 (0x00000005U)
#define | NVIC_PRIORITYGROUP_3 (0x00000004U)
#define | NVIC_PRIORITYGROUP_4 (0x00000003U)
#define | SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
#define | SYSTICK_CLKSOURCE_HCLK 0x00000004U
#define | MPU_HFNMI_PRIVDEF_NONE 0x00000000U
#define | MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk)
#define | MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk)
#define | MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
#define | MPU_REGION_ENABLE ((uint8_t)0x01)
#define | MPU_REGION_DISABLE ((uint8_t)0x00)
#define | MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
#define | MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
#define | MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
#define | MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
#define | MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
#define | MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
#define | MPU_TEX_LEVEL0 ((uint8_t)0x00)
#define | MPU_TEX_LEVEL1 ((uint8_t)0x01)
#define | MPU_TEX_LEVEL2 ((uint8_t)0x02)
#define | MPU_REGION_SIZE_32B ((uint8_t)0x04)
#define | MPU_REGION_SIZE_64B ((uint8_t)0x05)
#define | MPU_REGION_SIZE_128B ((uint8_t)0x06)
#define | MPU_REGION_SIZE_256B ((uint8_t)0x07)
#define | MPU_REGION_SIZE_512B ((uint8_t)0x08)
#define | MPU_REGION_SIZE_1KB ((uint8_t)0x09)
#define | MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
#define | MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
#define | MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
#define | MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
#define | MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
#define | MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
#define | MPU_REGION_SIZE_128KB ((uint8_t)0x10)
#define | MPU_REGION_SIZE_256KB ((uint8_t)0x11)
#define | MPU_REGION_SIZE_512KB ((uint8_t)0x12)
#define | MPU_REGION_SIZE_1MB ((uint8_t)0x13)
#define | MPU_REGION_SIZE_2MB ((uint8_t)0x14)
#define | MPU_REGION_SIZE_4MB ((uint8_t)0x15)
#define | MPU_REGION_SIZE_8MB ((uint8_t)0x16)
#define | MPU_REGION_SIZE_16MB ((uint8_t)0x17)
#define | MPU_REGION_SIZE_32MB ((uint8_t)0x18)
#define | MPU_REGION_SIZE_64MB ((uint8_t)0x19)
#define | MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
#define | MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
#define | MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
#define | MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
#define | MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
#define | MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
#define | MPU_REGION_NO_ACCESS ((uint8_t)0x00)
#define | MPU_REGION_PRIV_RW ((uint8_t)0x01)
#define | MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
#define | MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
#define | MPU_REGION_PRIV_RO ((uint8_t)0x05)
#define | MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
#define | MPU_REGION_NUMBER0 ((uint8_t)0x00)
#define | MPU_REGION_NUMBER1 ((uint8_t)0x01)
#define | MPU_REGION_NUMBER2 ((uint8_t)0x02)
#define | MPU_REGION_NUMBER3 ((uint8_t)0x03)
#define | MPU_REGION_NUMBER4 ((uint8_t)0x04)
#define | MPU_REGION_NUMBER5 ((uint8_t)0x05)
#define | MPU_REGION_NUMBER6 ((uint8_t)0x06)
#define | MPU_REGION_NUMBER7 ((uint8_t)0x07)
#define | IS_NVIC_PRIORITY_GROUP(GROUP)
#define | IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
#define | IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
#define | IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn)
#define | IS_SYSTICK_CLK_SOURCE(SOURCE)
#define | IS_MPU_REGION_ENABLE(STATE)
#define | IS_MPU_INSTRUCTION_ACCESS(STATE)
#define | IS_MPU_ACCESS_SHAREABLE(STATE)
#define | IS_MPU_ACCESS_CACHEABLE(STATE)
#define | IS_MPU_ACCESS_BUFFERABLE(STATE)
#define | IS_MPU_TEX_LEVEL(TYPE)
#define | IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE)
#define | IS_MPU_REGION_NUMBER(NUMBER)
#define | IS_MPU_REGION_SIZE(SIZE)
#define | IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)

Functions

void | HAL_NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
Set the priority grouping field (pre-emption priority and subpriority) using the required unlock sequence.
void | HAL_NVIC_SetPriority (IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
Set the priority of an interrupt.
void | HAL_NVIC_EnableIRQ (IRQn_Type IRQn)
Enable a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_DisableIRQ (IRQn_Type IRQn)
Disable a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_SystemReset (void)
Initiate a system reset request to reset the MCU.
uint32_t | HAL_SYSTICK_Config (uint32_t TicksNumb)
Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): Counter is in free running mode to generate periodic interrupts.
void | HAL_NVIC_GetPriority (IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
Get the priority of an interrupt.
uint32_t | HAL_NVIC_GetPriorityGrouping (void)
Get the priority grouping field from the NVIC Interrupt Controller.
uint32_t | HAL_NVIC_GetPendingIRQ (IRQn_Type IRQn)
Get Pending Interrupt (read the pending register in the NVIC and return the pending bit for the specified interrupt).
void | HAL_NVIC_SetPendingIRQ (IRQn_Type IRQn)
Set Pending bit of an external interrupt.
void | HAL_NVIC_ClearPendingIRQ (IRQn_Type IRQn)
Clear the pending bit of an external interrupt.
void | HAL_SYSTICK_CLKSourceConfig (uint32_t CLKSource)
Configure the SysTick clock source.
void | HAL_SYSTICK_IRQHandler (void)
Handle SYSTICK interrupt request.
__weak void | HAL_SYSTICK_Callback (void)
SYSTICK callback.
void | HAL_MPU_Enable (uint32_t MPU_Control)
Enable the MPU.
void | HAL_MPU_Disable (void)
Disables the MPU.
void | HAL_MPU_ConfigRegion (MPU_Region_InitTypeDef *MPU_Init)
Initialize and configure the Region and the memory to be protected.

Detailed Description

Header file of CORTEX HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_cortex.h.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_crc.h File Reference

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stm32wbxx_hal_crc.h File Reference

Header file of CRC HAL module. More...

#include "stm32wbxx_hal_def.h"
#include "stm32wbxx_hal_crc_ex.h"

Go to the source code of this file.

Data Structures

struct | CRC_InitTypeDef
CRC Init Structure definition. More...
struct | CRC_HandleTypeDef
CRC Handle Structure definition. More...

Defines

#define | DEFAULT_CRC32_POLY 0x04C11DB7U
#define | DEFAULT_CRC_INITVALUE 0xFFFFFFFFU
#define | DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U)
#define | DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U)
#define | DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U)
#define | DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U)
#define | CRC_POLYLENGTH_32B 0x00000000U
#define | CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0
#define | CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1
#define | CRC_POLYLENGTH_7B CRC_CR_POLYSIZE
#define | HAL_CRC_LENGTH_32B 32U
#define | HAL_CRC_LENGTH_16B 16U
#define | HAL_CRC_LENGTH_8B 8U
#define | HAL_CRC_LENGTH_7B 7U
#define | CRC_INPUTDATA_FORMAT_UNDEFINED 0x00000000U
#define | CRC_INPUTDATA_FORMAT_BYTES 0x00000001U
#define | CRC_INPUTDATA_FORMAT_HALFWORDS 0x00000002U
#define | CRC_INPUTDATA_FORMAT_WORDS 0x00000003U
#define | HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse
#define | HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse
#define | __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
Reset CRC handle state.
#define | __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
Reset CRC Data Register.
#define | __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
Set CRC INIT non-default value.
#define | __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
Store data in the Independent Data (ID) register.
#define | __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
Return the data stored in the Independent Data (ID) register.
#define | IS_DEFAULT_POLYNOMIAL(DEFAULT)
#define | IS_DEFAULT_INIT_VALUE(VALUE)
#define | IS_CRC_POL_LENGTH(LENGTH)
#define | IS_CRC_INPUTDATA_FORMAT(FORMAT)

Enumerations

enum HAL_CRC_StateTypeDef {
HAL_CRC_STATE_RESET = 0x00U, HAL_CRC_STATE_READY = 0x01U, HAL_CRC_STATE_BUSY = 0x02U, HAL_CRC_STATE_TIMEOUT = 0x03U,
HAL_CRC_STATE_ERROR = 0x04U
}
CRC HAL State Structure definition. More...

Functions

HAL_StatusTypeDef | HAL_CRC_Init (CRC_HandleTypeDef *hcrc)
Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC peripheral.
__weak void | HAL_CRC_MspInit (CRC_HandleTypeDef *hcrc)
Initializes the CRC MSP.
__weak void | HAL_CRC_MspDeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC MSP.
uint32_t | HAL_CRC_Accumulate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with the previously computed CRC as initialization value.
uint32_t | HAL_CRC_Calculate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with hcrc->Instance->INIT as initialization value.
HAL_CRC_StateTypeDef | HAL_CRC_GetState (CRC_HandleTypeDef *hcrc)
Return the CRC handle state.

Detailed Description

Header file of CRC HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_crc.h.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_crc_ex.h File Reference

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stm32wbxx_hal_crc_ex.h File Reference

Header file of CRC HAL extended module. More...

#include "stm32wbxx_hal_def.h"

Go to the source code of this file.

Defines

#define | CRC_INPUTDATA_INVERSION_NONE 0x00000000U
#define | CRC_INPUTDATA_INVERSION_BYTE CRC_CR_REV_IN_0
#define | CRC_INPUTDATA_INVERSION_HALFWORD CRC_CR_REV_IN_1
#define | CRC_INPUTDATA_INVERSION_WORD CRC_CR_REV_IN
#define | CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U
#define | CRC_OUTPUTDATA_INVERSION_ENABLE CRC_CR_REV_OUT
#define | __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
Set CRC output reversal.
#define | __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
Unset CRC output reversal.
#define | __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
Set CRC non-default polynomial.
#define | IS_CRC_INPUTDATA_INVERSION_MODE(MODE)
#define | IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE)

Functions

HAL_StatusTypeDef | HAL_CRCEx_Polynomial_Set (CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
Initialize the CRC polynomial if different from default one.
HAL_StatusTypeDef | HAL_CRCEx_Input_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
Set the Reverse Input data mode.
HAL_StatusTypeDef | HAL_CRCEx_Output_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
Set the Reverse Output data mode.

Detailed Description

Header file of CRC HAL extended module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_crc_ex.h.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_cryp.h File Reference

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stm32wbxx_hal_cryp.h File Reference

Header file of CRYP HAL module. More...

#include "stm32wbxx_hal_def.h"
#include "stm32wbxx_hal_cryp_ex.h"

Go to the source code of this file.

Data Structures

struct | CRYP_ConfigTypeDef
CRYP Init Structure definition. More...
struct | __CRYP_HandleTypeDef
CRYP handle Structure definition. More...

Defines

#define | HAL_CRYP_ERROR_NONE 0x00000000U
#define | HAL_CRYP_ERROR_WRITE 0x00000001U
#define | HAL_CRYP_ERROR_READ 0x00000002U
#define | HAL_CRYP_ERROR_DMA 0x00000004U
#define | HAL_CRYP_ERROR_BUSY 0x00000008U
#define | HAL_CRYP_ERROR_TIMEOUT 0x00000010U
#define | HAL_CRYP_ERROR_NOT_SUPPORTED 0x00000020U
#define | HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U
#define | HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U)
#define | CRYP_DATAWIDTHUNIT_WORD 0x00000000U
#define | CRYP_DATAWIDTHUNIT_BYTE 0x00000001U
#define | CRYP_AES_ECB 0x00000000U
#define | CRYP_AES_CBC AES_CR_CHMOD_0
#define | CRYP_AES_CTR AES_CR_CHMOD_1
#define | CRYP_AES_GCM_GMAC (AES_CR_CHMOD_0 | AES_CR_CHMOD_1)
#define | CRYP_AES_CCM AES_CR_CHMOD_2
#define | CRYP_KEYSIZE_128B 0x00000000U
#define | CRYP_KEYSIZE_256B AES_CR_KEYSIZE
#define | CRYP_DATATYPE_32B 0x00000000U
#define | CRYP_DATATYPE_16B AES_CR_DATATYPE_0
#define | CRYP_DATATYPE_8B AES_CR_DATATYPE_1
#define | CRYP_DATATYPE_1B AES_CR_DATATYPE
#define | CRYP_IT_CCFIE AES_CR_CCFIE
#define | CRYP_IT_ERRIE AES_CR_ERRIE
#define | CRYP_IT_WRERR AES_SR_WRERR
#define | CRYP_IT_RDERR AES_SR_RDERR
#define | CRYP_IT_CCF AES_SR_CCF
#define | CRYP_FLAG_BUSY AES_SR_BUSY
#define | CRYP_FLAG_WRERR AES_SR_WRERR
#define | CRYP_FLAG_RDERR AES_SR_RDERR
#define | CRYP_FLAG_CCF AES_SR_CCF
#define | CRYP_CCF_CLEAR AES_CR_CCFC
#define | CRYP_ERR_CLEAR AES_CR_ERRC
#define | CRYP_KEYIVCONFIG_ALWAYS 0x00000000U
#define | CRYP_KEYIVCONFIG_ONCE 0x00000001U
#define | __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__)
Reset CRYP handle state.
#define | __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= AES_CR_EN)
Enable/Disable the CRYP peripheral.
#define | __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~AES_CR_EN)
#define | CRYP_FLAG_MASK 0x0000001FU
Check whether the specified CRYP status flag is set or not.
#define | __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
#define | __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT((__HANDLE__)->Instance->CR, (__FLAG__))
Clear the CRYP pending status flag.
#define | __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified CRYP interrupt source is enabled or not.
#define | __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified CRYP interrupt is set or not.
#define | __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
Enable the CRYP interrupt.
#define | __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
Disable the CRYP interrupt.
#define | IS_CRYP_ALGORITHM(ALGORITHM)
#define | IS_CRYP_KEYSIZE(KEYSIZE)
#define | IS_CRYP_DATATYPE(DATATYPE)
#define | IS_CRYP_INIT(CONFIG)
#define | IS_CRYP_BUFFERSIZE(ALGO, DATAWIDTH, SIZE)

Typedefs

typedef struct __CRYP_HandleTypeDef | CRYP_HandleTypeDef
CRYP handle Structure definition.
typedef void(* | pCRYP_CallbackTypeDef )(CRYP_HandleTypeDef *hcryp)

Enumerations

enum | HAL_CRYP_STATETypeDef { HAL_CRYP_STATE_RESET = 0x00U, HAL_CRYP_STATE_READY = 0x01U, HAL_CRYP_STATE_BUSY = 0x02U }
CRYP State Structure definition. More...
enum HAL_CRYP_CallbackIDTypeDef {
HAL_CRYP_MSPINIT_CB_ID = 0x00U, HAL_CRYP_MSPDEINIT_CB_ID = 0x01U, HAL_CRYP_INPUT_COMPLETE_CB_ID = 0x02U, HAL_CRYP_OUTPUT_COMPLETE_CB_ID = 0x03U,
HAL_CRYP_ERROR_CB_ID = 0x04U
}

Functions

HAL_StatusTypeDef | HAL_CRYP_Init (CRYP_HandleTypeDef *hcryp)
Initializes the CRYP according to the specified parameters in the CRYP_ConfigTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_CRYP_DeInit (CRYP_HandleTypeDef *hcryp)
De-Initializes the CRYP peripheral.
__weak void | HAL_CRYP_MspInit (CRYP_HandleTypeDef *hcryp)
Initializes the CRYP MSP.
__weak void | HAL_CRYP_MspDeInit (CRYP_HandleTypeDef *hcryp)
DeInitializes CRYP MSP.
HAL_StatusTypeDef | HAL_CRYP_SetConfig (CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
Configure the CRYP according to the specified parameters in the CRYP_ConfigTypeDef.
HAL_StatusTypeDef | HAL_CRYP_GetConfig (CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
Get CRYP Configuration parameters in associated handle.
HAL_StatusTypeDef | HAL_CRYP_RegisterCallback (CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback)
Register a User CRYP Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_CRYP_UnRegisterCallback (CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID)
Unregister an CRYP Callback CRYP callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_CRYP_Encrypt (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
Encryption mode.
HAL_StatusTypeDef | HAL_CRYP_Decrypt (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
Decryption mode.
HAL_StatusTypeDef | HAL_CRYP_Encrypt_IT (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Encryption in interrupt mode.
HAL_StatusTypeDef | HAL_CRYP_Decrypt_IT (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Decryption in interrupt mode.
HAL_StatusTypeDef | HAL_CRYP_Encrypt_DMA (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Encryption in DMA mode.
HAL_StatusTypeDef | HAL_CRYP_Decrypt_DMA (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Decryption in DMA mode.
void | HAL_CRYP_IRQHandler (CRYP_HandleTypeDef *hcryp)
This function handles cryptographic interrupt request.
HAL_CRYP_STATETypeDef | HAL_CRYP_GetState (CRYP_HandleTypeDef *hcryp)
Returns the CRYP state.
__weak void | HAL_CRYP_InCpltCallback (CRYP_HandleTypeDef *hcryp)
Input FIFO transfer completed callback.
__weak void | HAL_CRYP_OutCpltCallback (CRYP_HandleTypeDef *hcryp)
Output FIFO transfer completed callback.
__weak void | HAL_CRYP_ErrorCallback (CRYP_HandleTypeDef *hcryp)
CRYP error callback.
uint32_t | HAL_CRYP_GetError (CRYP_HandleTypeDef *hcryp)
Return the CRYP error code.

Detailed Description

Header file of CRYP HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_cryp.h.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_cryp_ex.h File Reference

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Functions
stm32wbxx_hal_cryp_ex.h File Reference

Header file of CRYPEx HAL module. More...

#include "stm32wbxx_hal_def.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_CRYPEx_AESGCM_GenerateAuthTAG (CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
generate the GCM authentication TAG.
HAL_StatusTypeDef | HAL_CRYPEx_AESCCM_GenerateAuthTAG (CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
AES CCM Authentication TAG generation.
void | HAL_CRYPEx_EnableAutoKeyDerivation (CRYP_HandleTypeDef *hcryp)
AES enable key derivation functions.
void | HAL_CRYPEx_DisableAutoKeyDerivation (CRYP_HandleTypeDef *hcryp)
AES disable key derivation functions.

Detailed Description

Header file of CRYPEx HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_cryp_ex.h.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_dma.h File Reference

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stm32wbxx_hal_dma.h File Reference

Header file of DMA HAL module. More...

#include "stm32wbxx_hal_def.h"
#include "stm32wbxx_ll_dma.h"
#include "stm32wbxx_hal_dma_ex.h"

Go to the source code of this file.

Data Structures

struct | DMA_InitTypeDef
DMA Configuration Structure definition. More...
struct | __DMA_HandleTypeDef
DMA handle Structure definition. More...

Defines

#define | HAL_DMA_ERROR_NONE 0x00000000U
#define | HAL_DMA_ERROR_TE 0x00000001U
#define | HAL_DMA_ERROR_NO_XFER 0x00000004U
#define | HAL_DMA_ERROR_TIMEOUT 0x00000020U
#define | HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U
#define | HAL_DMA_ERROR_SYNC 0x00000200U
#define | HAL_DMA_ERROR_REQGEN 0x00000400U
#define | DMA_REQUEST_MEM2MEM LL_DMAMUX_REQ_MEM2MEM
#define | DMA_REQUEST_GENERATOR0 LL_DMAMUX_REQ_GENERATOR0
#define | DMA_REQUEST_GENERATOR1 LL_DMAMUX_REQ_GENERATOR1
#define | DMA_REQUEST_GENERATOR2 LL_DMAMUX_REQ_GENERATOR2
#define | DMA_REQUEST_GENERATOR3 LL_DMAMUX_REQ_GENERATOR3
#define | DMA_REQUEST_ADC1 LL_DMAMUX_REQ_ADC1
#define | DMA_REQUEST_SPI1_RX LL_DMAMUX_REQ_SPI1_RX
#define | DMA_REQUEST_SPI1_TX LL_DMAMUX_REQ_SPI1_TX
#define | DMA_REQUEST_SPI2_RX LL_DMAMUX_REQ_SPI2_RX
#define | DMA_REQUEST_SPI2_TX LL_DMAMUX_REQ_SPI2_TX
#define | DMA_REQUEST_I2C1_RX LL_DMAMUX_REQ_I2C1_RX
#define | DMA_REQUEST_I2C1_TX LL_DMAMUX_REQ_I2C1_TX
#define | DMA_REQUEST_I2C3_RX LL_DMAMUX_REQ_I2C3_RX
#define | DMA_REQUEST_I2C3_TX LL_DMAMUX_REQ_I2C3_TX
#define | DMA_REQUEST_USART1_RX LL_DMAMUX_REQ_USART1_RX
#define | DMA_REQUEST_USART1_TX LL_DMAMUX_REQ_USART1_TX
#define | DMA_REQUEST_LPUART1_RX LL_DMAMUX_REQ_LPUART1_RX
#define | DMA_REQUEST_LPUART1_TX LL_DMAMUX_REQ_LPUART1_TX
#define | DMA_REQUEST_SAI1_A LL_DMAMUX_REQ_SAI1_A
#define | DMA_REQUEST_SAI1_B LL_DMAMUX_REQ_SAI1_B
#define | DMA_REQUEST_QUADSPI LL_DMAMUX_REQ_QUADSPI
#define | DMA_REQUEST_TIM1_CH1 LL_DMAMUX_REQ_TIM1_CH1
#define | DMA_REQUEST_TIM1_CH2 LL_DMAMUX_REQ_TIM1_CH2
#define | DMA_REQUEST_TIM1_CH3 LL_DMAMUX_REQ_TIM1_CH3
#define | DMA_REQUEST_TIM1_CH4 LL_DMAMUX_REQ_TIM1_CH4
#define | DMA_REQUEST_TIM1_UP LL_DMAMUX_REQ_TIM1_UP
#define | DMA_REQUEST_TIM1_TRIG LL_DMAMUX_REQ_TIM1_TRIG
#define | DMA_REQUEST_TIM1_COM LL_DMAMUX_REQ_TIM1_COM
#define | DMA_REQUEST_TIM2_CH1 LL_DMAMUX_REQ_TIM2_CH1
#define | DMA_REQUEST_TIM2_CH2 LL_DMAMUX_REQ_TIM2_CH2
#define | DMA_REQUEST_TIM2_CH3 LL_DMAMUX_REQ_TIM2_CH3
#define | DMA_REQUEST_TIM2_CH4 LL_DMAMUX_REQ_TIM2_CH4
#define | DMA_REQUEST_TIM2_UP LL_DMAMUX_REQ_TIM2_UP
#define | DMA_REQUEST_TIM16_CH1 LL_DMAMUX_REQ_TIM16_CH1
#define | DMA_REQUEST_TIM16_UP LL_DMAMUX_REQ_TIM16_UP
#define | DMA_REQUEST_TIM17_CH1 LL_DMAMUX_REQ_TIM17_CH1
#define | DMA_REQUEST_TIM17_UP LL_DMAMUX_REQ_TIM17_UP
#define | DMA_REQUEST_AES1_IN LL_DMAMUX_REQ_AES1_IN
#define | DMA_REQUEST_AES1_OUT LL_DMAMUX_REQ_AES1_OUT
#define | DMA_REQUEST_AES2_IN LL_DMAMUX_REQ_AES2_IN
#define | DMA_REQUEST_AES2_OUT LL_DMAMUX_REQ_AES2_OUT
#define | DMA_PERIPH_TO_MEMORY LL_DMA_DIRECTION_PERIPH_TO_MEMORY
#define | DMA_MEMORY_TO_PERIPH LL_DMA_DIRECTION_MEMORY_TO_PERIPH
#define | DMA_MEMORY_TO_MEMORY LL_DMA_DIRECTION_MEMORY_TO_MEMORY
#define | DMA_PINC_ENABLE LL_DMA_PERIPH_INCREMENT
#define | DMA_PINC_DISABLE LL_DMA_PERIPH_NOINCREMENT
#define | DMA_MINC_ENABLE LL_DMA_MEMORY_INCREMENT
#define | DMA_MINC_DISABLE LL_DMA_MEMORY_NOINCREMENT
#define | DMA_PDATAALIGN_BYTE LL_DMA_PDATAALIGN_BYTE
#define | DMA_PDATAALIGN_HALFWORD LL_DMA_PDATAALIGN_HALFWORD
#define | DMA_PDATAALIGN_WORD LL_DMA_PDATAALIGN_WORD
#define | DMA_MDATAALIGN_BYTE LL_DMA_MDATAALIGN_BYTE
#define | DMA_MDATAALIGN_HALFWORD LL_DMA_MDATAALIGN_HALFWORD
#define | DMA_MDATAALIGN_WORD LL_DMA_MDATAALIGN_WORD
#define | DMA_NORMAL LL_DMA_MODE_NORMAL
#define | DMA_CIRCULAR LL_DMA_MODE_CIRCULAR
#define | DMA_PRIORITY_LOW LL_DMA_PRIORITY_LOW
#define | DMA_PRIORITY_MEDIUM LL_DMA_PRIORITY_MEDIUM
#define | DMA_PRIORITY_HIGH LL_DMA_PRIORITY_HIGH
#define | DMA_PRIORITY_VERY_HIGH LL_DMA_PRIORITY_VERYHIGH
#define | DMA_IT_TC LL_DMA_CCR_TCIE
#define | DMA_IT_HT LL_DMA_CCR_HTIE
#define | DMA_IT_TE LL_DMA_CCR_TEIE
#define | DMA_FLAG_GL1 LL_DMA_ISR_GIF1
#define | DMA_FLAG_TC1 LL_DMA_ISR_TCIF1
#define | DMA_FLAG_HT1 LL_DMA_ISR_HTIF1
#define | DMA_FLAG_TE1 LL_DMA_ISR_TEIF1
#define | DMA_FLAG_GL2 LL_DMA_ISR_GIF2
#define | DMA_FLAG_TC2 LL_DMA_ISR_TCIF2
#define | DMA_FLAG_HT2 LL_DMA_ISR_HTIF2
#define | DMA_FLAG_TE2 LL_DMA_ISR_TEIF2
#define | DMA_FLAG_GL3 LL_DMA_ISR_GIF3
#define | DMA_FLAG_TC3 LL_DMA_ISR_TCIF3
#define | DMA_FLAG_HT3 LL_DMA_ISR_HTIF3
#define | DMA_FLAG_TE3 LL_DMA_ISR_TEIF3
#define | DMA_FLAG_GL4 LL_DMA_ISR_GIF4
#define | DMA_FLAG_TC4 LL_DMA_ISR_TCIF4
#define | DMA_FLAG_HT4 LL_DMA_ISR_HTIF4
#define | DMA_FLAG_TE4 LL_DMA_ISR_TEIF4
#define | DMA_FLAG_GL5 LL_DMA_ISR_GIF5
#define | DMA_FLAG_TC5 LL_DMA_ISR_TCIF5
#define | DMA_FLAG_HT5 LL_DMA_ISR_HTIF5
#define | DMA_FLAG_TE5 LL_DMA_ISR_TEIF5
#define | DMA_FLAG_GL6 LL_DMA_ISR_GIF6
#define | DMA_FLAG_TC6 LL_DMA_ISR_TCIF6
#define | DMA_FLAG_HT6 LL_DMA_ISR_HTIF6
#define | DMA_FLAG_TE6 LL_DMA_ISR_TEIF6
#define | DMA_FLAG_GL7 LL_DMA_ISR_GIF7
#define | DMA_FLAG_TC7 LL_DMA_ISR_TCIF7
#define | DMA_FLAG_HT7 LL_DMA_ISR_HTIF7
#define | DMA_FLAG_TE7 LL_DMA_ISR_TEIF7
#define | __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
Reset DMA handle state.
#define | __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
Enable the specified DMA Channel.
#define | __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
Disable the specified DMA Channel.
#define | __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel transfer complete flag.
#define | __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel half transfer complete flag.
#define | __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel transfer error flag.
#define | __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel Global interrupt flag.
#define | __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)
Get the DMA Channel pending flags.
#define | __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the DMA Channel pending flags.
#define | __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
Enable the specified DMA Channel interrupts.
#define | __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
Disable the specified DMA Channel interrupts.
#define | __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
Check whether the specified DMA Channel interrupt is enabled or not.
#define | __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
Return the number of remaining data units in the current DMA Channel transfer.
#define | IS_DMA_DIRECTION(DIRECTION)
#define | IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
#define | IS_DMA_PERIPHERAL_INC_STATE(STATE)
#define | IS_DMA_MEMORY_INC_STATE(STATE)
#define | IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_REQUEST_AES2_OUT)
#define | IS_DMA_PERIPHERAL_DATA_SIZE(SIZE)
#define | IS_DMA_MEMORY_DATA_SIZE(SIZE)
#define | IS_DMA_MODE(MODE)
#define | IS_DMA_PRIORITY(PRIORITY)

Typedefs

typedef struct __DMA_HandleTypeDef | DMA_HandleTypeDef
DMA handle Structure definition.

Enumerations

enum | HAL_DMA_StateTypeDef { HAL_DMA_STATE_RESET = 0x00U, HAL_DMA_STATE_READY = 0x01U, HAL_DMA_STATE_BUSY = 0x02U, HAL_DMA_STATE_TIMEOUT = 0x03U }
HAL DMA State structures definition. More...
enum | HAL_DMA_LevelCompleteTypeDef { HAL_DMA_FULL_TRANSFER = 0x00U, HAL_DMA_HALF_TRANSFER = 0x01U }
HAL DMA Error Code structure definition. More...
enum HAL_DMA_CallbackIDTypeDef {
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, HAL_DMA_XFER_ERROR_CB_ID = 0x02U, HAL_DMA_XFER_ABORT_CB_ID = 0x03U,
HAL_DMA_XFER_ALL_CB_ID = 0x04U
}
HAL DMA Callback ID structure definition. More...

Functions

HAL_StatusTypeDef | HAL_DMA_Init (DMA_HandleTypeDef *hdma)
Initialize the DMA according to the specified parameters in the DMA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_DMA_DeInit (DMA_HandleTypeDef *hdma)
DeInitialize the DMA peripheral.
HAL_StatusTypeDef | HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Start_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA_Abort (DMA_HandleTypeDef *hdma)
Abort the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Abort_IT (DMA_HandleTypeDef *hdma)
Aborts the DMA Transfer in Interrupt mode.
HAL_StatusTypeDef | HAL_DMA_PollForTransfer (DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
Polling for transfer complete.
void | HAL_DMA_IRQHandler (DMA_HandleTypeDef *hdma)
Handle DMA interrupt request.
HAL_StatusTypeDef | HAL_DMA_RegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void(*pCallback)(DMA_HandleTypeDef *_hdma))
Register callbacks.
HAL_StatusTypeDef | HAL_DMA_UnRegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
UnRegister callbacks.
HAL_DMA_StateTypeDef | HAL_DMA_GetState (DMA_HandleTypeDef *hdma)
Return the DMA handle state.
uint32_t | HAL_DMA_GetError (DMA_HandleTypeDef *hdma)
Return the DMA error code.

Detailed Description

Header file of DMA HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_dma.h.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_dma_ex.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32WBxx_HAL_Driver
  • Inc
Data Structures | Defines | Functions
stm32wbxx_hal_dma_ex.h File Reference

Header file of DMA HAL extension module. More...

#include "stm32wbxx_hal_def.h"
#include "stm32wbxx_ll_dmamux.h"

Go to the source code of this file.

Data Structures

struct | HAL_DMA_MuxSyncConfigTypeDef
HAL DMA Synchro definition. More...
struct | HAL_DMA_MuxRequestGeneratorConfigTypeDef
HAL DMAMUX request generator parameters structure definition. More...

Defines

#define | HAL_DMAMUX1_SYNC_EXTI0 LL_DMAMUX_SYNC_EXTI_LINE0
#define | HAL_DMAMUX1_SYNC_EXTI1 LL_DMAMUX_SYNC_EXTI_LINE1
#define | HAL_DMAMUX1_SYNC_EXTI2 LL_DMAMUX_SYNC_EXTI_LINE2
#define | HAL_DMAMUX1_SYNC_EXTI3 LL_DMAMUX_SYNC_EXTI_LINE3
#define | HAL_DMAMUX1_SYNC_EXTI4 LL_DMAMUX_SYNC_EXTI_LINE4
#define | HAL_DMAMUX1_SYNC_EXTI5 LL_DMAMUX_SYNC_EXTI_LINE5
#define | HAL_DMAMUX1_SYNC_EXTI6 LL_DMAMUX_SYNC_EXTI_LINE6
#define | HAL_DMAMUX1_SYNC_EXTI7 LL_DMAMUX_SYNC_EXTI_LINE7
#define | HAL_DMAMUX1_SYNC_EXTI8 LL_DMAMUX_SYNC_EXTI_LINE8
#define | HAL_DMAMUX1_SYNC_EXTI9 LL_DMAMUX_SYNC_EXTI_LINE9
#define | HAL_DMAMUX1_SYNC_EXTI10 LL_DMAMUX_SYNC_EXTI_LINE10
#define | HAL_DMAMUX1_SYNC_EXTI11 LL_DMAMUX_SYNC_EXTI_LINE11
#define | HAL_DMAMUX1_SYNC_EXTI12 LL_DMAMUX_SYNC_EXTI_LINE12
#define | HAL_DMAMUX1_SYNC_EXTI13 LL_DMAMUX_SYNC_EXTI_LINE13
#define | HAL_DMAMUX1_SYNC_EXTI14 LL_DMAMUX_SYNC_EXTI_LINE14
#define | HAL_DMAMUX1_SYNC_EXTI15 LL_DMAMUX_SYNC_EXTI_LINE15
#define | HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT LL_DMAMUX_SYNC_DMAMUX_CH0
#define | HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT LL_DMAMUX_SYNC_DMAMUX_CH1
#define | HAL_DMAMUX1_SYNC_LPTIM1_OUT LL_DMAMUX_SYNC_LPTIM1_OUT
#define | HAL_DMAMUX1_SYNC_LPTIM2_OUT LL_DMAMUX_SYNC_LPTIM2_OUT
#define | HAL_DMAMUX_SYNC_NO_EVENT LL_DMAMUX_SYNC_NO_EVENT
#define | HAL_DMAMUX_SYNC_RISING LL_DMAMUX_SYNC_POL_RISING
#define | HAL_DMAMUX_SYNC_FALLING LL_DMAMUX_SYNC_POL_FALLING
#define | HAL_DMAMUX_SYNC_RISING_FALLING LL_DMAMUX_SYNC_POL_RISING_FALLING
#define | HAL_DMAMUX1_REQ_GEN_EXTI0 LL_DMAMUX_REQ_GEN_EXTI_LINE0
#define | HAL_DMAMUX1_REQ_GEN_EXTI1 LL_DMAMUX_REQ_GEN_EXTI_LINE1
#define | HAL_DMAMUX1_REQ_GEN_EXTI2 LL_DMAMUX_REQ_GEN_EXTI_LINE2
#define | HAL_DMAMUX1_REQ_GEN_EXTI3 LL_DMAMUX_REQ_GEN_EXTI_LINE3
#define | HAL_DMAMUX1_REQ_GEN_EXTI4 LL_DMAMUX_REQ_GEN_EXTI_LINE4
#define | HAL_DMAMUX1_REQ_GEN_EXTI5 LL_DMAMUX_REQ_GEN_EXTI_LINE5
#define | HAL_DMAMUX1_REQ_GEN_EXTI6 LL_DMAMUX_REQ_GEN_EXTI_LINE6
#define | HAL_DMAMUX1_REQ_GEN_EXTI7 LL_DMAMUX_REQ_GEN_EXTI_LINE7
#define | HAL_DMAMUX1_REQ_GEN_EXTI8 LL_DMAMUX_REQ_GEN_EXTI_LINE8
#define | HAL_DMAMUX1_REQ_GEN_EXTI9 LL_DMAMUX_REQ_GEN_EXTI_LINE9
#define | HAL_DMAMUX1_REQ_GEN_EXTI10 LL_DMAMUX_REQ_GEN_EXTI_LINE10
#define | HAL_DMAMUX1_REQ_GEN_EXTI11 LL_DMAMUX_REQ_GEN_EXTI_LINE11
#define | HAL_DMAMUX1_REQ_GEN_EXTI12 LL_DMAMUX_REQ_GEN_EXTI_LINE12
#define | HAL_DMAMUX1_REQ_GEN_EXTI13 LL_DMAMUX_REQ_GEN_EXTI_LINE13
#define | HAL_DMAMUX1_REQ_GEN_EXTI14 LL_DMAMUX_REQ_GEN_EXTI_LINE14
#define | HAL_DMAMUX1_REQ_GEN_EXTI15 LL_DMAMUX_REQ_GEN_EXTI_LINE15
#define | HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH0
#define | HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH1
#define | HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT LL_DMAMUX_REQ_GEN_LPTIM1_OUT
#define | HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT LL_DMAMUX_REQ_GEN_LPTIM2_OUT
#define | HAL_DMAMUX_REQ_GEN_NO_EVENT LL_DMAMUX_REQ_GEN_NO_EVENT
#define | HAL_DMAMUX_REQ_GEN_RISING LL_DMAMUX_REQ_GEN_POL_RISING
#define | HAL_DMAMUX_REQ_GEN_FALLING LL_DMAMUX_REQ_GEN_POL_FALLING
#define | HAL_DMAMUX_REQ_GEN_RISING_FALLING LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
#define | IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_LPTIM2_OUT)
#define | IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
#define | IS_DMAMUX_SYNC_POLARITY(POLARITY)
#define | IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE))
#define | IS_DMAMUX_SYNC_EVENT(EVENT)
#define | IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT)
#define | IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
#define | IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY)

Functions

HAL_StatusTypeDef | HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
Configure the DMAMUX request generator block used by the given DMA channel (instance).
HAL_StatusTypeDef | HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
Enable the DMAMUX request generator block used by the given DMA channel (instance).
HAL_StatusTypeDef | HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
Disable the DMAMUX request generator block used by the given DMA channel (instance).
HAL_StatusTypeDef | HAL_DMAEx_ConfigMuxSync (DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
Configure the DMAMUX synchronization parameters for a given DMA channel (instance).
void | HAL_DMAEx_MUX_IRQHandler (DMA_HandleTypeDef *hdma)
Handles DMAMUX interrupt request.

Detailed Description

Header file of DMA HAL extension module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_dma_ex.h.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_exti.h File Reference

  • File List
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Data Structures | Defines | Enumerations | Functions
stm32wbxx_hal_exti.h File Reference

Header file of EXTI HAL module. More...

#include "stm32wbxx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | EXTI_HandleTypeDef
EXTI Handle structure definition. More...
struct | EXTI_ConfigTypeDef
EXTI Configuration structure definition. More...

Defines

#define | EXTI_LINE_0 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x00u)
#define | EXTI_LINE_1 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x01u)
#define | EXTI_LINE_2 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x02u)
#define | EXTI_LINE_3 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x03u)
#define | EXTI_LINE_4 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x04u)
#define | EXTI_LINE_5 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x05u)
#define | EXTI_LINE_6 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x06u)
#define | EXTI_LINE_7 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x07u)
#define | EXTI_LINE_8 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x08u)
#define | EXTI_LINE_9 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x09u)
#define | EXTI_LINE_10 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Au)
#define | EXTI_LINE_11 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Bu)
#define | EXTI_LINE_12 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Cu)
#define | EXTI_LINE_13 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Du)
#define | EXTI_LINE_14 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Eu)
#define | EXTI_LINE_15 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Fu)
#define | EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10u)
#define | EXTI_LINE_17 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x11u)
#define | EXTI_LINE_18 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x12u)
#define | EXTI_LINE_19 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x13u)
#define | EXTI_LINE_20 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x14u)
#define | EXTI_LINE_21 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x15u)
#define | EXTI_LINE_22 (EXTI_DIRECT | EXTI_REG1 | 0x16u)
#define | EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17u)
#define | EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18u)
#define | EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19u)
#define | EXTI_LINE_26 (EXTI_RESERVED | EXTI_REG1 | 0x1Au)
#define | EXTI_LINE_27 (EXTI_RESERVED | EXTI_REG1 | 0x1Bu)
#define | EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1Cu)
#define | EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | 0x1Du)
#define | EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | 0x1Eu)
#define | EXTI_LINE_31 (EXTI_CONFIG | EXTI_REG1 | 0x1Fu)
#define | EXTI_LINE_32 (EXTI_RESERVED | EXTI_REG2 | 0x00u)
#define | EXTI_LINE_33 (EXTI_CONFIG | EXTI_REG2 | 0x01u)
#define | EXTI_LINE_34 (EXTI_RESERVED | EXTI_REG2 | 0x02u)
#define | EXTI_LINE_35 (EXTI_RESERVED | EXTI_REG2 | 0x03u)
#define | EXTI_LINE_36 (EXTI_DIRECT | EXTI_REG2 | 0x04u)
#define | EXTI_LINE_37 (EXTI_DIRECT | EXTI_REG2 | 0x05u)
#define | EXTI_LINE_38 (EXTI_DIRECT | EXTI_REG2 | 0x06u)
#define | EXTI_LINE_39 (EXTI_DIRECT | EXTI_REG2 | 0x07u)
#define | EXTI_LINE_40 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | 0x08u)
#define | EXTI_LINE_41 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | 0x09u)
#define | EXTI_LINE_42 (EXTI_DIRECT | EXTI_REG2 | 0x0Au)
#define | EXTI_LINE_43 (EXTI_DIRECT | EXTI_REG2 | 0x0Bu)
#define | EXTI_LINE_44 (EXTI_DIRECT | EXTI_REG2 | 0x0Cu)
#define | EXTI_LINE_45 (EXTI_DIRECT | EXTI_REG2 | 0x0Du)
#define | EXTI_LINE_46 (EXTI_DIRECT | EXTI_REG2 | 0x0Eu)
#define | EXTI_LINE_47 (EXTI_RESERVED | EXTI_REG2 | 0x0Fu)
#define | EXTI_LINE_48 (EXTI_DIRECT | EXTI_REG2 | 0x10u)
#define | EXTI_MODE_NONE 0x00000000u
#define | EXTI_MODE_INTERRUPT 0x00000001u
#define | EXTI_MODE_EVENT 0x00000002u
#define | EXTI_TRIGGER_NONE 0x00000000u
#define | EXTI_TRIGGER_RISING 0x00000001u
#define | EXTI_TRIGGER_FALLING 0x00000002u
#define | EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
#define | EXTI_GPIOA 0x00000000u
#define | EXTI_GPIOB 0x00000001u
#define | EXTI_GPIOC 0x00000002u
#define | EXTI_GPIOD 0x00000003u
#define | EXTI_GPIOE 0x00000004u
#define | EXTI_GPIOH 0x00000007u
#define | EXTI_PROPERTY_SHIFT 24u
EXTI Line property definition.
#define | EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT)
#define | EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
#define | EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
#define | EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)
#define | EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
#define | EXTI_EVENT_PRESENCE_SHIFT 28u
EXTI Event presence definition.
#define | EXTI_EVENT (0x01uL << EXTI_EVENT_PRESENCE_SHIFT)
#define | EXTI_EVENT_PRESENCE_MASK (EXTI_EVENT)
#define | EXTI_REG_SHIFT 16u
EXTI Register and bit usage.
#define | EXTI_REG1 (0x00uL << EXTI_REG_SHIFT)
#define | EXTI_REG2 (0x01uL << EXTI_REG_SHIFT)
#define | EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2)
#define | EXTI_PIN_MASK 0x0000001Fu
#define | EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
EXTI Mask for interrupt & event mode.
#define | EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
EXTI Mask for trigger possibilities.
#define | EXTI_LINE_NB 49uL
EXTI Line number.
#define | IS_EXTI_LINE(__LINE__)
#define | IS_EXTI_MODE(__LINE__)
#define | IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
#define | IS_EXTI_PENDING_EDGE(__LINE__) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING)
#define | IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u)
#define | IS_EXTI_GPIO_PORT(__PORT__)
#define | IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)

Enumerations

enum | EXTI_CallbackIDTypeDef { HAL_EXTI_COMMON_CB_ID = 0x00U }

Functions

HAL_StatusTypeDef | HAL_EXTI_SetConfigLine (EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
Set configuration of a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_GetConfigLine (EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
Get configuration of a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_ClearConfigLine (EXTI_HandleTypeDef *hexti)
Clear whole configuration of a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_RegisterCallback (EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void(*pPendingCbfn)(void))
Register callback for a dedicaated Exti line.
HAL_StatusTypeDef | HAL_EXTI_GetHandle (EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
Store line number as handle private field.
void | HAL_EXTI_IRQHandler (EXTI_HandleTypeDef *hexti)
Handle EXTI interrupt request.
uint32_t | HAL_EXTI_GetPending (EXTI_HandleTypeDef *hexti, uint32_t Edge)
Get interrupt pending bit of a dedicated line.
void | HAL_EXTI_ClearPending (EXTI_HandleTypeDef *hexti, uint32_t Edge)
Clear interrupt pending bit of a dedicated line.
void | HAL_EXTI_GenerateSWI (EXTI_HandleTypeDef *hexti)
Generate a software interrupt for a dedicated line.

Detailed Description

Header file of EXTI HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_exti.h.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_flash.h File Reference

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Data Structures | Defines | Functions | Variables
stm32wbxx_hal_flash.h File Reference

Header file of FLASH HAL module. More...

#include "stm32wbxx_hal_def.h"
#include "stm32wbxx_hal_flash_ex.h"

Go to the source code of this file.

Data Structures

struct | FLASH_EraseInitTypeDef
FLASH Erase structure definition. More...
struct | FLASH_OBProgramInitTypeDef
FLASH Option Bytes Program structure definition. More...
struct | FLASH_ProcessTypeDef
FLASH handle Structure definition. More...

Defines

#define | FLASH_KEY1 0x45670123U
#define | FLASH_KEY2 0xCDEF89ABU
#define | FLASH_OPTKEY1 0x08192A3BU
#define | FLASH_OPTKEY2 0x4C5D6E7FU
#define | FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS
#define | FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS
#define | FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS
#define | FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS
#define | FLASH_FLAG_EOP FLASH_SR_EOP
#define | FLASH_FLAG_OPERR FLASH_SR_OPERR
#define | FLASH_FLAG_PROGERR FLASH_SR_PROGERR
#define | FLASH_FLAG_WRPERR FLASH_SR_WRPERR
#define | FLASH_FLAG_PGAERR FLASH_SR_PGAERR
#define | FLASH_FLAG_SIZERR FLASH_SR_SIZERR
#define | FLASH_FLAG_PGSERR FLASH_SR_PGSERR
#define | FLASH_FLAG_MISERR FLASH_SR_MISERR
#define | FLASH_FLAG_FASTERR FLASH_SR_FASTERR
#define | FLASH_FLAG_OPTNV FLASH_SR_OPTNV
#define | FLASH_FLAG_RDERR FLASH_SR_RDERR
#define | FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR
#define | FLASH_FLAG_BSY FLASH_SR_BSY
#define | FLASH_FLAG_CFGBSY FLASH_SR_CFGBSY
#define | FLASH_FLAG_PESD FLASH_SR_PESD
#define | FLASH_FLAG_ECCC FLASH_ECCR_ECCC
#define | FLASH_FLAG_ECCD FLASH_ECCR_ECCD
#define | FLASH_FLAG_SR_ERRORS
#define | FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)
#define | FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_ECCR_ERRORS)
#define | FLASH_IT_EOP FLASH_CR_EOPIE
#define | FLASH_IT_OPERR FLASH_CR_ERRIE
#define | FLASH_IT_RDERR FLASH_CR_RDERRIE
#define | FLASH_IT_ECCC (FLASH_ECCR_ECCCIE >> FLASH_ECCR_ECCCIE_Pos)
#define | HAL_FLASH_ERROR_NONE 0x00000000U
#define | HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR
#define | HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR
#define | HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR
#define | HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR
#define | HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR
#define | HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR
#define | HAL_FLASH_ERROR_MIS FLASH_FLAG_MISERR
#define | HAL_FLASH_ERROR_FAST FLASH_FLAG_FASTERR
#define | HAL_FLASH_ERROR_RD FLASH_FLAG_RDERR
#define | HAL_FLASH_ERROR_OPTV FLASH_FLAG_OPTVERR
#define | FLASH_TYPEERASE_PAGES FLASH_CR_PER
#define | FLASH_TYPEERASE_MASSERASE FLASH_CR_MER
#define | FLASH_TYPEPROGRAM_DOUBLEWORD FLASH_CR_PG
#define | FLASH_TYPEPROGRAM_FAST FLASH_CR_FSTPG
#define | OPTIONBYTE_WRP 0x00000001U
#define | OPTIONBYTE_RDP 0x00000002U
#define | OPTIONBYTE_USER 0x00000004U
#define | OPTIONBYTE_PCROP 0x00000008U
#define | OPTIONBYTE_IPCC_BUF_ADDR 0x00000010U
#define | OPTIONBYTE_C2_BOOT_VECT 0x00000100U
#define | OPTIONBYTE_SECURE_MODE 0x00000200U
#define | OPTIONBYTE_ALL
#define | OB_WRPAREA_BANK1_AREAA 0x00000000U
#define | OB_WRPAREA_BANK1_AREAB 0x00000001U
#define | OB_RDP_LEVEL_0 0x000000AAU
#define | OB_RDP_LEVEL_1 0x000000BBU
#define | OB_RDP_LEVEL_2 0x000000CCU
#define | OB_USER_BOR_LEV FLASH_OPTR_BOR_LEV
#define | OB_USER_nRST_STOP FLASH_OPTR_nRST_STOP
#define | OB_USER_nRST_STDBY FLASH_OPTR_nRST_STDBY
#define | OB_USER_nRST_SHDW FLASH_OPTR_nRST_SHDW
#define | OB_USER_IWDG_SW FLASH_OPTR_IWDG_SW
#define | OB_USER_IWDG_STOP FLASH_OPTR_IWDG_STOP
#define | OB_USER_IWDG_STDBY FLASH_OPTR_IWDG_STDBY
#define | OB_USER_WWDG_SW FLASH_OPTR_WWDG_SW
#define | OB_USER_nBOOT1 FLASH_OPTR_nBOOT1
#define | OB_USER_SRAM2PE FLASH_OPTR_SRAM2PE
#define | OB_USER_SRAM2RST FLASH_OPTR_SRAM2RST
#define | OB_USER_nSWBOOT0 FLASH_OPTR_nSWBOOT0
#define | OB_USER_nBOOT0 FLASH_OPTR_nBOOT0
#define | OB_USER_AGC_TRIM FLASH_OPTR_AGC_TRIM
#define | OB_USER_ALL
#define | OB_AGC_TRIM_0 0x00000000U
#define | OB_AGC_TRIM_1 FLASH_OPTR_AGC_TRIM_0
#define | OB_AGC_TRIM_2 FLASH_OPTR_AGC_TRIM_1
#define | OB_AGC_TRIM_3 (FLASH_OPTR_AGC_TRIM_1 | FLASH_OPTR_AGC_TRIM_0)
#define | OB_AGC_TRIM_4 FLASH_OPTR_AGC_TRIM_2
#define | OB_AGC_TRIM_5 (FLASH_OPTR_AGC_TRIM_2 | FLASH_OPTR_AGC_TRIM_0)
#define | OB_AGC_TRIM_6 (FLASH_OPTR_AGC_TRIM_2 | FLASH_OPTR_AGC_TRIM_1)
#define | OB_AGC_TRIM_7 (FLASH_OPTR_AGC_TRIM_2 | FLASH_OPTR_AGC_TRIM_1 | FLASH_OPTR_AGC_TRIM_0)
#define | OB_BOR_LEVEL_0 0x00000000U
#define | OB_BOR_LEVEL_1 FLASH_OPTR_BOR_LEV_0
#define | OB_BOR_LEVEL_2 FLASH_OPTR_BOR_LEV_1
#define | OB_BOR_LEVEL_3 (FLASH_OPTR_BOR_LEV_0 | FLASH_OPTR_BOR_LEV_1)
#define | OB_BOR_LEVEL_4 FLASH_OPTR_BOR_LEV_2
#define | OB_STOP_RST 0x00000000U
#define | OB_STOP_NORST FLASH_OPTR_nRST_STOP
#define | OB_STANDBY_RST 0x00000000U
#define | OB_STANDBY_NORST FLASH_OPTR_nRST_STDBY
#define | OB_SHUTDOWN_RST 0x00000000U
#define | OB_SHUTDOWN_NORST FLASH_OPTR_nRST_SHDW
#define | OB_IWDG_HW 0x00000000U
#define | OB_IWDG_SW FLASH_OPTR_IWDG_SW
#define | OB_IWDG_STOP_FREEZE 0x00000000U
#define | OB_IWDG_STOP_RUN FLASH_OPTR_IWDG_STOP
#define | OB_IWDG_STDBY_FREEZE 0x00000000U
#define | OB_IWDG_STDBY_RUN FLASH_OPTR_IWDG_STDBY
#define | OB_WWDG_HW 0x00000000U
#define | OB_WWDG_SW FLASH_OPTR_WWDG_SW
#define | OB_SRAM2_PARITY_ENABLE 0x00000000U
#define | OB_SRAM2_PARITY_DISABLE FLASH_OPTR_SRAM2PE
#define | OB_SRAM2_RST_ERASE 0x00000000U
#define | OB_SRAM2_RST_NOT_ERASE FLASH_OPTR_SRAM2RST
#define | OB_BOOT1_SRAM 0x00000000U
#define | OB_BOOT1_SYSTEM FLASH_OPTR_nBOOT1
#define | OB_BOOT0_FROM_OB 0x00000000U
#define | OB_BOOT0_FROM_PIN FLASH_OPTR_nSWBOOT0
#define | OB_BOOT0_RESET 0x00000000U
#define | OB_BOOT0_SET FLASH_OPTR_nBOOT0
#define | OB_PCROP_ZONE_A 0x00000001U
#define | OB_PCROP_ZONE_B 0x00000002U
#define | OB_PCROP_RDP_NOT_ERASE 0x00000000U
#define | OB_PCROP_RDP_ERASE FLASH_PCROP1AER_PCROP_RDP
#define | SYSTEM_NOT_IN_SECURE_MODE 0x00000000U
#define | SYSTEM_IN_SECURE_MODE FLASH_OPTR_ESE
#define | OB_C2_BOOT_FROM_SRAM 0x00000000U
#define | OB_C2_BOOT_FROM_FLASH FLASH_SRRVR_C2OPT
#define | SRAM2A_START_SECURE_ADDR_0 (SRAM2A_BASE + 0x0000U) /* When in secure mode (SRAM2A_BASE + 0x0000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_1 (SRAM2A_BASE + 0x0400U) /* When in secure mode (SRAM2A_BASE + 0x0400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_2 (SRAM2A_BASE + 0x0800U) /* When in secure mode (SRAM2A_BASE + 0x0800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_3 (SRAM2A_BASE + 0x0C00U) /* When in secure mode (SRAM2A_BASE + 0x0C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_4 (SRAM2A_BASE + 0x1000U) /* When in secure mode (SRAM2A_BASE + 0x1000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_5 (SRAM2A_BASE + 0x1400U) /* When in secure mode (SRAM2A_BASE + 0x1400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_6 (SRAM2A_BASE + 0x1800U) /* When in secure mode (SRAM2A_BASE + 0x1800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_7 (SRAM2A_BASE + 0x1C00U) /* When in secure mode (SRAM2A_BASE + 0x1C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_8 (SRAM2A_BASE + 0x2000U) /* When in secure mode (SRAM2A_BASE + 0x2000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_9 (SRAM2A_BASE + 0x2400U) /* When in secure mode (SRAM2A_BASE + 0x2400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_10 (SRAM2A_BASE + 0x2800U) /* When in secure mode (SRAM2A_BASE + 0x2800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_11 (SRAM2A_BASE + 0x2C00U) /* When in secure mode (SRAM2A_BASE + 0x2C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_12 (SRAM2A_BASE + 0x3000U) /* When in secure mode (SRAM2A_BASE + 0x3000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_13 (SRAM2A_BASE + 0x3400U) /* When in secure mode (SRAM2A_BASE + 0x3400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_14 (SRAM2A_BASE + 0x3800U) /* When in secure mode (SRAM2A_BASE + 0x3800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_15 (SRAM2A_BASE + 0x3C00U) /* When in secure mode (SRAM2A_BASE + 0x3C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_16 (SRAM2A_BASE + 0x4000U) /* When in secure mode (SRAM2A_BASE + 0x4000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_17 (SRAM2A_BASE + 0x4400U) /* When in secure mode (SRAM2A_BASE + 0x4400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_18 (SRAM2A_BASE + 0x4800U) /* When in secure mode (SRAM2A_BASE + 0x4800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_19 (SRAM2A_BASE + 0x4C00U) /* When in secure mode (SRAM2A_BASE + 0x4C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_20 (SRAM2A_BASE + 0x5000U) /* When in secure mode (SRAM2A_BASE + 0x5000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_21 (SRAM2A_BASE + 0x5400U) /* When in secure mode (SRAM2A_BASE + 0x5400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_22 (SRAM2A_BASE + 0x5800U) /* When in secure mode (SRAM2A_BASE + 0x5800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_23 (SRAM2A_BASE + 0x5C00U) /* When in secure mode (SRAM2A_BASE + 0x5C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_24 (SRAM2A_BASE + 0x6000U) /* When in secure mode (SRAM2A_BASE + 0x6000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_25 (SRAM2A_BASE + 0x6400U) /* When in secure mode (SRAM2A_BASE + 0x6400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_26 (SRAM2A_BASE + 0x6800U) /* When in secure mode (SRAM2A_BASE + 0x6800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_27 (SRAM2A_BASE + 0x6C00U) /* When in secure mode (SRAM2A_BASE + 0x6C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_28 (SRAM2A_BASE + 0x7000U) /* When in secure mode (SRAM2A_BASE + 0x7000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_29 (SRAM2A_BASE + 0x7400U) /* When in secure mode (SRAM2A_BASE + 0x7400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_30 (SRAM2A_BASE + 0x7800U) /* When in secure mode (SRAM2A_BASE + 0x7800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_START_SECURE_ADDR_31 (SRAM2A_BASE + 0x7C00U) /* When in secure mode (SRAM2A_BASE + 0x7C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2A_FULL_UNSECURE (SRAM2A_BASE + 0x8000U) /* The RAM2A is accessible to M0 Plus and M4 */
#define | SRAM2B_START_SECURE_ADDR_0 (SRAM2B_BASE + 0x0000U) /* When in secure mode (SRAM2B_BASE + 0x0000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_1 (SRAM2B_BASE + 0x0400U) /* When in secure mode (SRAM2B_BASE + 0x0400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_2 (SRAM2B_BASE + 0x0800U) /* When in secure mode (SRAM2B_BASE + 0x0800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_3 (SRAM2B_BASE + 0x0C00U) /* When in secure mode (SRAM2B_BASE + 0x0C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_4 (SRAM2B_BASE + 0x1000U) /* When in secure mode (SRAM2B_BASE + 0x1000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_5 (SRAM2B_BASE + 0x1400U) /* When in secure mode (SRAM2B_BASE + 0x1400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_6 (SRAM2B_BASE + 0x1800U) /* When in secure mode (SRAM2B_BASE + 0x1800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_7 (SRAM2B_BASE + 0x1C00U) /* When in secure mode (SRAM2B_BASE + 0x1C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_8 (SRAM2B_BASE + 0x2000U) /* When in secure mode (SRAM2B_BASE + 0x2000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_9 (SRAM2B_BASE + 0x2400U) /* When in secure mode (SRAM2B_BASE + 0x2400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_10 (SRAM2B_BASE + 0x2800U) /* When in secure mode (SRAM2B_BASE + 0x2800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_11 (SRAM2B_BASE + 0x2C00U) /* When in secure mode (SRAM2B_BASE + 0x2C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_12 (SRAM2B_BASE + 0x3000U) /* When in secure mode (SRAM2B_BASE + 0x3000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_13 (SRAM2B_BASE + 0x3400U) /* When in secure mode (SRAM2B_BASE + 0x3400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_14 (SRAM2B_BASE + 0x3800U) /* When in secure mode (SRAM2B_BASE + 0x3800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_15 (SRAM2B_BASE + 0x3C00U) /* When in secure mode (SRAM2B_BASE + 0x3C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_16 (SRAM2B_BASE + 0x4000U) /* When in secure mode (SRAM2B_BASE + 0x4000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_17 (SRAM2B_BASE + 0x4400U) /* When in secure mode (SRAM2B_BASE + 0x4400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_18 (SRAM2B_BASE + 0x4800U) /* When in secure mode (SRAM2B_BASE + 0x4800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_19 (SRAM2B_BASE + 0x4C00U) /* When in secure mode (SRAM2B_BASE + 0x4C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_20 (SRAM2B_BASE + 0x5000U) /* When in secure mode (SRAM2B_BASE + 0x5000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_21 (SRAM2B_BASE + 0x5400U) /* When in secure mode (SRAM2B_BASE + 0x5400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_22 (SRAM2B_BASE + 0x5800U) /* When in secure mode (SRAM2B_BASE + 0x5800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_23 (SRAM2B_BASE + 0x5C00U) /* When in secure mode (SRAM2B_BASE + 0x5C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_24 (SRAM2B_BASE + 0x6000U) /* When in secure mode (SRAM2B_BASE + 0x6000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_25 (SRAM2B_BASE + 0x6400U) /* When in secure mode (SRAM2B_BASE + 0x6400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_26 (SRAM2B_BASE + 0x6800U) /* When in secure mode (SRAM2B_BASE + 0x6800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_27 (SRAM2B_BASE + 0x6C00U) /* When in secure mode (SRAM2B_BASE + 0x6C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_28 (SRAM2B_BASE + 0x7000U) /* When in secure mode (SRAM2B_BASE + 0x7000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_29 (SRAM2B_BASE + 0x7400U) /* When in secure mode (SRAM2B_BASE + 0x7400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_30 (SRAM2B_BASE + 0x7800U) /* When in secure mode (SRAM2B_BASE + 0x7800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_START_SECURE_ADDR_31 (SRAM2B_BASE + 0x7C00U) /* When in secure mode (SRAM2B_BASE + 0x7C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define | SRAM2B_FULL_UNSECURE (SRAM2B_BASE + 0x8000U) /* The RAM2B is accessible to M0 Plus and M4 */
#define | __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__))
Set the FLASH Latency.
#define | __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)
Get the FLASH Latency.
#define | __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
Enable the FLASH prefetch buffer.
#define | __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
Disable the FLASH prefetch buffer.
#define | __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN)
Enable the FLASH instruction cache.
#define | __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN)
Disable the FLASH instruction cache.
#define | __HAL_FLASH_DATA_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_DCEN)
Enable the FLASH data cache.
#define | __HAL_FLASH_DATA_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN)
Disable the FLASH data cache.
#define | __HAL_FLASH_INSTRUCTION_CACHE_RESET()
Reset the FLASH instruction Cache.
#define | __HAL_FLASH_DATA_CACHE_RESET()
Reset the FLASH data Cache.
#define | __HAL_FLASH_ENABLE_IT(__INTERRUPT__)
Enable the specified FLASH interrupt.
#define | __HAL_FLASH_DISABLE_IT(__INTERRUPT__)
Disable the specified FLASH interrupt.
#define | __HAL_FLASH_GET_FLAG(__FLAG__)
Check whether the specified FLASH flag is set or not.
#define | __HAL_FLASH_CLEAR_FLAG(__FLAG__)
Clear the FLASH's pending flags.
#define | FLASH_END_ADDR (FLASH_BASE + FLASH_SIZE - 1U)
#define | FLASH_BANK_SIZE FLASH_SIZE
#define | FLASH_PAGE_SIZE 0x00001000U
#define | FLASH_PAGE_NB (FLASH_SIZE / FLASH_PAGE_SIZE)
#define | FLASH_TIMEOUT_VALUE 1000U
#define | FLASH_PCROP_GRANULARITY_OFFSET 11U
#define | FLASH_PCROP_GRANULARITY (1UL << FLASH_PCROP_GRANULARITY_OFFSET)
#define | FLASH_TYPENONE 0x00000000U
#define | SRAM_SECURE_PAGE_GRANULARITY_OFFSET 10U
#define | SRAM_SECURE_PAGE_GRANULARITY (1UL << FLASH_PCROP_GRANULARITY_OFFSET)
#define | IS_FLASH_MAIN_MEM_ADDRESS(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 1UL)))
#define | IS_FLASH_FAST_PROGRAM_ADDRESS(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 256UL)) && (((__VALUE__) % 256UL) == 0UL))
#define | IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 8UL)) && (((__VALUE__) % 8UL) == 0UL))
#define | IS_FLASH_PROGRAM_OTP_ADDRESS(__VALUE__) (((__VALUE__) >= OTP_AREA_BASE) && ((__VALUE__) <= (OTP_AREA_END_ADDR + 1UL - 8UL)) && (((__VALUE__) % 8UL) == 0UL))
#define | IS_FLASH_PROGRAM_ADDRESS(__VALUE__) (IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__VALUE__) || IS_FLASH_PROGRAM_OTP_ADDRESS(__VALUE__))
#define | IS_FLASH_PAGE(__VALUE__) ((__VALUE__) < FLASH_PAGE_NB)
#define | IS_ADDR_ALIGNED_64BITS(__VALUE__) (((__VALUE__) & 0x7U) == (0x00UL))
#define | IS_FLASH_TYPEERASE(__VALUE__)
#define | IS_FLASH_TYPEPROGRAM(__VALUE__)
#define | IS_OB_SFSA_START_ADDR(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= FLASH_END_ADDR) && (((__VALUE__) & ~(uint32_t)0xFFFU) == (__VALUE__)))
#define | IS_OB_SBRSA_START_ADDR(__VALUE__) (((__VALUE__) >= SRAM2A_BASE) && ((__VALUE__) <= (SRAM2A_BASE + SRAM2A_SIZE - 1U)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__)))
#define | IS_OB_SNBRSA_START_ADDR(__VALUE__) (((__VALUE__) >= SRAM2B_BASE) && ((__VALUE__) <= (SRAM2B_BASE + SRAM2B_SIZE - 1U)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__)))
#define | IS_OB_SECURE_MODE(__VALUE__) (((__VALUE__) == SYSTEM_IN_SECURE_MODE) || ((__VALUE__) == SYSTEM_NOT_IN_SECURE_MODE))
#define | IS_OPTIONBYTE(__VALUE__)
#define | IS_OB_WRPAREA(__VALUE__) (((__VALUE__) == OB_WRPAREA_BANK1_AREAA) || ((__VALUE__) == OB_WRPAREA_BANK1_AREAB))
#define | IS_OB_RDP_LEVEL(__VALUE__)
#define | IS_OB_USER_TYPE(__VALUE__)
#define | IS_OB_USER_CONFIG(__TYPE__, __VALUE__)
#define | IS_OB_USER_AGC_TRIMMING(__VALUE__)
#define | IS_OB_USER_BOR_LEVEL(__VALUE__)
#define | IS_OB_PCROP_CONFIG(__VALUE__) (((__VALUE__) & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | OB_PCROP_RDP_ERASE)) == 0U)
#define | IS_OB_IPCC_BUF_ADDR(__VALUE__) (IS_OB_SBRSA_START_ADDR(__VALUE__) || IS_OB_SNBRSA_START_ADDR(__VALUE__))
#define | IS_OB_BOOT_VECTOR_ADDR(__VALUE__)
#define | IS_OB_BOOT_REGION(__VALUE__) (((__VALUE__) == OB_C2_BOOT_FROM_FLASH) || ((__VALUE__) == OB_C2_BOOT_FROM_SRAM))
#define | IS_OB_SECURE_CONFIG(__VALUE__) (((__VALUE__) & ~(OB_SECURE_CONFIG_MEMORY | OB_SECURE_CONFIG_BOOT_RESET)) == 0U)
#define | IS_FLASH_LATENCY(__VALUE__)

Functions

HAL_StatusTypeDef | HAL_FLASH_Program (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program double word or fast program of a row at a specified address.
HAL_StatusTypeDef | HAL_FLASH_Program_IT (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program double word or fast program of a row at a specified address with interrupt enabled.
void | HAL_FLASH_IRQHandler (void)
Handle FLASH interrupt request.
__weak void | HAL_FLASH_EndOfOperationCallback (uint32_t ReturnValue)
FLASH end of operation interrupt callback.
__weak void | HAL_FLASH_OperationErrorCallback (uint32_t ReturnValue)
FLASH operation error interrupt callback.
HAL_StatusTypeDef | HAL_FLASH_Unlock (void)
Unlock the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_Lock (void)
Lock the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_OB_Unlock (void)
Unlock the FLASH Option Bytes Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Lock (void)
Lock the FLASH Option Bytes Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Launch (void)
Launch the option byte loading.
uint32_t | HAL_FLASH_GetError (void)
Get the specific FLASH error flag.
HAL_StatusTypeDef | FLASH_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH operation to complete.

Variables

FLASH_ProcessTypeDef pFlash
Variable used for Program/Erase sectors under interruption.

Detailed Description

Header file of FLASH HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_flash.h.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_flash_ex.h File Reference

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stm32wbxx_hal_flash_ex.h File Reference

Header file of FLASH HAL Extended module. More...

#include "stm32wbxx_hal_def.h"

Go to the source code of this file.

Defines

#define | FLASH_PROG_NOT_EMPTY 0x00000000U
#define | FLASH_PROG_EMPTY FLASH_ACR_EMPTY
#define | IS_FLASH_EMPTY_CHECK(__VALUE__) (((__VALUE__) == FLASH_PROG_EMPTY) || ((__VALUE__) == FLASH_PROG_NOT_EMPTY))

Functions

HAL_StatusTypeDef | HAL_FLASHEx_Erase (FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
Perform a mass erase or erase the specified FLASH memory pages.
HAL_StatusTypeDef | HAL_FLASHEx_Erase_IT (FLASH_EraseInitTypeDef *pEraseInit)
Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.
uint32_t | HAL_FLASHEx_FlashEmptyCheck (void)
Flash Empty check.
void | HAL_FLASHEx_ForceFlashEmpty (uint32_t FlashEmpty)
Force Empty check value.
HAL_StatusTypeDef | HAL_FLASHEx_OBProgram (FLASH_OBProgramInitTypeDef *pOBInit)
Program Option bytes.
void | HAL_FLASHEx_OBGetConfig (FLASH_OBProgramInitTypeDef *pOBInit)
Get the Option bytes configuration.
void | HAL_FLASHEx_SuspendOperation (void)
Suspend new program or erase operation request.
void | HAL_FLASHEx_AllowOperation (void)
Allow new program or erase operation request.
uint32_t | HAL_FLASHEx_IsOperationSuspended (void)
Check if new program or erase operation request from CPU1 or CPU2 is suspended.
void | FLASH_PageErase (uint32_t Page)
Erase the specified FLASH memory page.

Detailed Description

Header file of FLASH HAL Extended module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_flash_ex.h.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_gpio.h File Reference

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Data Structures | Defines | Enumerations | Functions
stm32wbxx_hal_gpio.h File Reference

Header file of GPIO HAL module. More...

#include "stm32wbxx_hal_def.h"
#include "stm32wbxx_hal_gpio_ex.h"

Go to the source code of this file.

Data Structures

struct | GPIO_InitTypeDef
GPIO Init structure definition. More...

Defines

#define | GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
#define | GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
#define | GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
#define | GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
#define | GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
#define | GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
#define | GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
#define | GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
#define | GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
#define | GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
#define | GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
#define | GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
#define | GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
#define | GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
#define | GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
#define | GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
#define | GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
#define | GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
#define | GPIO_MODE_INPUT (0x00000000u)
#define | GPIO_MODE_OUTPUT_PP (0x00000001u)
#define | GPIO_MODE_OUTPUT_OD (0x00000011u)
#define | GPIO_MODE_AF_PP (0x00000002u)
#define | GPIO_MODE_AF_OD (0x00000012u)
#define | GPIO_MODE_ANALOG (0x00000003u)
#define | GPIO_MODE_IT_RISING (0x10110000u)
#define | GPIO_MODE_IT_FALLING (0x10210000u)
#define | GPIO_MODE_IT_RISING_FALLING (0x10310000u)
#define | GPIO_MODE_EVT_RISING (0x10120000u)
#define | GPIO_MODE_EVT_FALLING (0x10220000u)
#define | GPIO_MODE_EVT_RISING_FALLING (0x10320000u)
#define | GPIO_SPEED_FREQ_LOW (0x00000000u)
#define | GPIO_SPEED_FREQ_MEDIUM (0x00000001u)
#define | GPIO_SPEED_FREQ_HIGH (0x00000002u)
#define | GPIO_SPEED_FREQ_VERY_HIGH (0x00000003u)
#define | GPIO_NOPULL (0x00000000u)
#define | GPIO_PULLUP (0x00000001u)
#define | GPIO_PULLDOWN (0x00000002u)
#define | __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
Check whether the specified EXTI line flag is set or not.
#define | __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
Clear the EXTI's line pending flags.
#define | __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
Check whether the specified EXTI line is asserted or not.
#define | __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
Clear the EXTI's line pending bits.
#define | __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__))
Generate a Software interrupt on selected EXTI line.
#define | IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define | IS_GPIO_PIN(__PIN__)
#define | IS_GPIO_MODE(__MODE__)
#define | IS_GPIO_SPEED(__SPEED__)
#define | IS_GPIO_PULL(__PULL__)

Enumerations

enum | GPIO_PinState { GPIO_PIN_RESET = 0U, GPIO_PIN_SET }
GPIO Bit SET and Bit RESET enumeration. More...

Functions

void | HAL_GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
void | HAL_GPIO_DeInit (GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
De-initialize the GPIOx peripheral registers to their default reset values.
GPIO_PinState | HAL_GPIO_ReadPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Read the specified input port pin.
void | HAL_GPIO_WritePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
Set or clear the selected data port bit.
void | HAL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Toggle the specified GPIO pin.
HAL_StatusTypeDef | HAL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Lock GPIO Pins configuration registers.
void | HAL_GPIO_EXTI_IRQHandler (uint16_t GPIO_Pin)
Handle EXTI interrupt request.
__weak void | HAL_GPIO_EXTI_Callback (uint16_t GPIO_Pin)
EXTI line detection callback.

Detailed Description

Header file of GPIO HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_gpio.h.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_gpio_ex.h File Reference

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Defines
stm32wbxx_hal_gpio_ex.h File Reference

Header file of GPIO HAL Extended module. More...

#include "stm32wbxx_hal_def.h"

Go to the source code of this file.

Defines

#define | GPIO_AF0_MCO ((uint8_t)0x00)
AF 0 selection.
#define | GPIO_AF0_LSCO ((uint8_t)0x00)
#define | GPIO_AF0_JTMS_SWDIO ((uint8_t)0x00)
#define | GPIO_AF0_JTCK_SWCLK ((uint8_t)0x00)
#define | GPIO_AF0_JTDI ((uint8_t)0x00)
#define | GPIO_AF0_RTC_OUT ((uint8_t)0x00)
#define | GPIO_AF0_JTD_TRACE ((uint8_t)0x00)
#define | GPIO_AF0_NJTRST ((uint8_t)0x00)
#define | GPIO_AF0_RTC_REFIN ((uint8_t)0x00)
#define | GPIO_AF0_TRACED0 ((uint8_t)0x00)
#define | GPIO_AF0_TRACED1 ((uint8_t)0x00)
#define | GPIO_AF0_TRACED2 ((uint8_t)0x00)
#define | GPIO_AF0_TRACED3 ((uint8_t)0x00)
#define | GPIO_AF0_TRIG_INOUT ((uint8_t)0x00)
#define | GPIO_AF0_TRACECK ((uint8_t)0x00)
#define | GPIO_AF0_SYS ((uint8_t)0x00)
#define | GPIO_AF1_TIM1 ((uint8_t)0x01)
AF 1 selection.
#define | GPIO_AF1_TIM2 ((uint8_t)0x01)
#define | GPIO_AF1_LPTIM1 ((uint8_t)0x01)
#define | GPIO_AF2_TIM2 ((uint8_t)0x02)
AF 2 selection.
#define | GPIO_AF2_TIM1 ((uint8_t)0x02)
#define | GPIO_AF3_SAI1 ((uint8_t)0x03)
AF 3 selection.
#define | GPIO_AF3_SPI2 ((uint8_t)0x03)
#define | GPIO_AF3_TIM1 ((uint8_t)0x03)
#define | GPIO_AF4_I2C1 ((uint8_t)0x04)
AF 4 selection.
#define | GPIO_AF4_I2C3 ((uint8_t)0x04)
#define | GPIO_AF5_SPI1 ((uint8_t)0x05)
AF 5 selection.
#define | GPIO_AF5_SPI2 ((uint8_t)0x05)
#define | GPIO_AF6_MCO ((uint8_t)0x06)
AF 6 selection.
#define | GPIO_AF6_LSCO ((uint8_t)0x06)
#define | GPIO_AF6_RF_DTB0 ((uint8_t)0x06)
#define | GPIO_AF6_RF_DTB1 ((uint8_t)0x06)
#define | GPIO_AF6_RF_DTB2 ((uint8_t)0x06)
#define | GPIO_AF6_RF_DTB3 ((uint8_t)0x06)
#define | GPIO_AF6_RF_DTB4 ((uint8_t)0x06)
#define | GPIO_AF6_RF_DTB5 ((uint8_t)0x06)
#define | GPIO_AF6_RF_DTB6 ((uint8_t)0x06)
#define | GPIO_AF6_RF_DTB7 ((uint8_t)0x06)
#define | GPIO_AF6_RF_DTB8 ((uint8_t)0x06)
#define | GPIO_AF6_RF_DTB9 ((uint8_t)0x06)
#define | GPIO_AF6_RF_DTB10 ((uint8_t)0x06)
#define | GPIO_AF6_RF_DTB11 ((uint8_t)0x06)
#define | GPIO_AF6_RF_DTB12 ((uint8_t)0x06)
#define | GPIO_AF6_RF_DTB13 ((uint8_t)0x06)
#define | GPIO_AF6_RF_DTB14 ((uint8_t)0x06)
#define | GPIO_AF6_RF_DTB15 ((uint8_t)0x06)
#define | GPIO_AF6_RF_DTB16 ((uint8_t)0x06)
#define | GPIO_AF6_RF_DTB17 ((uint8_t)0x06)
#define | GPIO_AF6_RF_DTB18 ((uint8_t)0x06)
#define | GPIO_AF6_RF_MISO ((uint8_t)0x06)
#define | GPIO_AF6_RF_MOSI ((uint8_t)0x06)
#define | GPIO_AF6_RF_SCK ((uint8_t)0x06)
#define | GPIO_AF6_RF_NSS ((uint8_t)0x06)
#define | GPIO_AF7_USART1 ((uint8_t)0x07)
AF 7 selection.
#define | GPIO_AF8_LPUART1 ((uint8_t)0x08)
AF 8 selection.
#define | GPIO_AF8_IR ((uint8_t)0x08)
#define | GPIO_AF9_TSC ((uint8_t)0x09)
AF 9 selection.
#define | GPIO_AF10_QUADSPI ((uint8_t)0x0a)
AF 10 selection.
#define | GPIO_AF10_USB ((uint8_t)0x0a)
#define | GPIO_AF11_LCD ((uint8_t)0x0b)
AF 11 selection.
#define | GPIO_AF12_COMP1 ((uint8_t)0x0c)
AF 12 selection.
#define | GPIO_AF12_COMP2 ((uint8_t)0x0c)
#define | GPIO_AF12_TIM1 ((uint8_t)0x0c)
#define | GPIO_AF13_SAI1 ((uint8_t)0x0d)
AF 13 selection.
#define | GPIO_AF14_TIM2 ((uint8_t)0x0e)
AF 14 selection.
#define | GPIO_AF14_TIM16 ((uint8_t)0x0e)
#define | GPIO_AF14_TIM17 ((uint8_t)0x0e)
#define | GPIO_AF14_LPTIM2 ((uint8_t)0x0e)
#define | GPIO_AF15_EVENTOUT ((uint8_t)0x0f)
AF 15 selection.
#define | IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0f)
#define | GPIO_GET_INDEX(__GPIOx__)

Detailed Description

Header file of GPIO HAL Extended module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_gpio_ex.h.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_hsem.h File Reference

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stm32wbxx_hal_hsem.h File Reference

Header file of HSEM HAL module. More...

#include "stm32wbxx_hal_def.h"

Go to the source code of this file.

Defines

#define | __HAL_HSEM_SEMID_TO_MASK(__SEMID__) (1 << (__SEMID__))
SemID to mask helper Macro.
#define | __HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->IER |= (__SEM_MASK__))
Enables the specified HSEM interrupts.
#define | __HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->IER &= ~(__SEM_MASK__))
Disables the specified HSEM interrupts.
#define | __HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->MISR)
Checks whether interrupt has occurred or not for semaphores specified by a mask.
#define | __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->ISR)
Get the semaphores release status flags.
#define | __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->ICR |= (__SEM_MASK__))
Clears the HSEM Interrupt flags.
#define | IS_HSEM_SEMID(__SEMID__) ((__SEMID__) <= HSEM_SEMID_MAX )
#define | IS_HSEM_PROCESSID(__PROCESSID__) ((__PROCESSID__) <= HSEM_PROCESSID_MAX )
#define | IS_HSEM_KEY(__KEY__) ((__KEY__) <= HSEM_CLEAR_KEY_MAX )
#define | IS_HSEM_COREID(__COREID__)

Functions

HAL_StatusTypeDef | HAL_HSEM_Take (uint32_t SemID, uint32_t ProcessID)
Take a semaphore in 2 Step mode.
HAL_StatusTypeDef | HAL_HSEM_FastTake (uint32_t SemID)
Fast Take a semaphore with 1 Step mode.
uint32_t | HAL_HSEM_IsSemTaken (uint32_t SemID)
Check semaphore state Taken or not.
void | HAL_HSEM_Release (uint32_t SemID, uint32_t ProcessID)
Release a semaphore.
void | HAL_HSEM_ReleaseAll (uint32_t Key, uint32_t CoreID)
Release All semaphore used by a given Master .
void | HAL_HSEM_SetClearKey (uint32_t Key)
Set semaphore Key .
uint32_t | HAL_HSEM_GetClearKey (void)
Get semaphore Key .
void | HAL_HSEM_ActivateNotification (uint32_t SemMask)
Activate Semaphore release Notification for a given Semaphores Mask .
void | HAL_HSEM_DeactivateNotification (uint32_t SemMask)
Deactivate Semaphore release Notification for a given Semaphores Mask .
__weak void | HAL_HSEM_FreeCallback (uint32_t SemMask)
Semaphore Released Callback.
void | HAL_HSEM_IRQHandler (void)
This function handles HSEM interrupt request.

Detailed Description

Header file of HSEM HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_hsem.h.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_i2c.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32wbxx_hal_i2c.h File Reference

Header file of I2C HAL module. More...

#include "stm32wbxx_hal_def.h"
#include "stm32wbxx_hal_i2c_ex.h"

Go to the source code of this file.

Data Structures

struct | I2C_InitTypeDef
struct | __I2C_HandleTypeDef

Defines

#define | HAL_I2C_ERROR_NONE (0x00000000U)
#define | HAL_I2C_ERROR_BERR (0x00000001U)
#define | HAL_I2C_ERROR_ARLO (0x00000002U)
#define | HAL_I2C_ERROR_AF (0x00000004U)
#define | HAL_I2C_ERROR_OVR (0x00000008U)
#define | HAL_I2C_ERROR_DMA (0x00000010U)
#define | HAL_I2C_ERROR_TIMEOUT (0x00000020U)
#define | HAL_I2C_ERROR_SIZE (0x00000040U)
#define | HAL_I2C_ERROR_DMA_PARAM (0x00000080U)
#define | HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U)
#define | HAL_I2C_ERROR_INVALID_PARAM (0x00000200U)
#define | I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
#define | I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define | I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define | I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define | I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define | I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)
#define | I2C_OTHER_FRAME (0x000000AAU)
#define | I2C_OTHER_AND_LAST_FRAME (0x0000AA00U)
#define | I2C_ADDRESSINGMODE_7BIT (0x00000001U)
#define | I2C_ADDRESSINGMODE_10BIT (0x00000002U)
#define | I2C_DUALADDRESS_DISABLE (0x00000000U)
#define | I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
#define | I2C_OA2_NOMASK ((uint8_t)0x00U)
#define | I2C_OA2_MASK01 ((uint8_t)0x01U)
#define | I2C_OA2_MASK02 ((uint8_t)0x02U)
#define | I2C_OA2_MASK03 ((uint8_t)0x03U)
#define | I2C_OA2_MASK04 ((uint8_t)0x04U)
#define | I2C_OA2_MASK05 ((uint8_t)0x05U)
#define | I2C_OA2_MASK06 ((uint8_t)0x06U)
#define | I2C_OA2_MASK07 ((uint8_t)0x07U)
#define | I2C_GENERALCALL_DISABLE (0x00000000U)
#define | I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
#define | I2C_NOSTRETCH_DISABLE (0x00000000U)
#define | I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
#define | I2C_MEMADD_SIZE_8BIT (0x00000001U)
#define | I2C_MEMADD_SIZE_16BIT (0x00000002U)
#define | I2C_DIRECTION_TRANSMIT (0x00000000U)
#define | I2C_DIRECTION_RECEIVE (0x00000001U)
#define | I2C_RELOAD_MODE I2C_CR2_RELOAD
#define | I2C_AUTOEND_MODE I2C_CR2_AUTOEND
#define | I2C_SOFTEND_MODE (0x00000000U)
#define | I2C_NO_STARTSTOP (0x00000000U)
#define | I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define | I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define | I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
#define | I2C_IT_ERRI I2C_CR1_ERRIE
#define | I2C_IT_TCI I2C_CR1_TCIE
#define | I2C_IT_STOPI I2C_CR1_STOPIE
#define | I2C_IT_NACKI I2C_CR1_NACKIE
#define | I2C_IT_ADDRI I2C_CR1_ADDRIE
#define | I2C_IT_RXI I2C_CR1_RXIE
#define | I2C_IT_TXI I2C_CR1_TXIE
#define | I2C_FLAG_TXE I2C_ISR_TXE
#define | I2C_FLAG_TXIS I2C_ISR_TXIS
#define | I2C_FLAG_RXNE I2C_ISR_RXNE
#define | I2C_FLAG_ADDR I2C_ISR_ADDR
#define | I2C_FLAG_AF I2C_ISR_NACKF
#define | I2C_FLAG_STOPF I2C_ISR_STOPF
#define | I2C_FLAG_TC I2C_ISR_TC
#define | I2C_FLAG_TCR I2C_ISR_TCR
#define | I2C_FLAG_BERR I2C_ISR_BERR
#define | I2C_FLAG_ARLO I2C_ISR_ARLO
#define | I2C_FLAG_OVR I2C_ISR_OVR
#define | I2C_FLAG_PECERR I2C_ISR_PECERR
#define | I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define | I2C_FLAG_ALERT I2C_ISR_ALERT
#define | I2C_FLAG_BUSY I2C_ISR_BUSY
#define | I2C_FLAG_DIR I2C_ISR_DIR
#define | __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)
Reset I2C handle state.
#define | __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
Enable the specified I2C interrupt.
#define | __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
Disable the specified I2C interrupt.
#define | __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified I2C interrupt source is enabled or not.
#define | I2C_FLAG_MASK (0x0001FFFFU)
Check whether the specified I2C flag is set or not.
#define | __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
#define | __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
#define | __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Enable the specified I2C peripheral.
#define | __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Disable the specified I2C peripheral.
#define | __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
Generate a Non-Acknowledge I2C peripheral in Slave mode.
#define | IS_I2C_ADDRESSING_MODE(MODE)
#define | IS_I2C_DUAL_ADDRESS(ADDRESS)
#define | IS_I2C_OWN_ADDRESS2_MASK(MASK)
#define | IS_I2C_GENERAL_CALL(CALL)
#define | IS_I2C_NO_STRETCH(STRETCH)
#define | IS_I2C_MEMADD_SIZE(SIZE)
#define | IS_TRANSFER_MODE(MODE)
#define | IS_TRANSFER_REQUEST(REQUEST)
#define | IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)
#define | IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)
#define | I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
#define | I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U))
#define | I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U))
#define | I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define | I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
#define | I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
#define | IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define | IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
#define | I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
#define | I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define | I2C_GENERATE_START(__ADDMODE__, __ADDRESS__)
#define | I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
#define | I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)

Typedefs

typedef struct __I2C_HandleTypeDef | I2C_HandleTypeDef
typedef void(* | pI2C_CallbackTypeDef )(I2C_HandleTypeDef *hi2c)
HAL I2C Callback pointer definition.
typedef void(* | pI2C_AddrCallbackTypeDef )(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)

Enumerations

enum HAL_I2C_StateTypeDef {
HAL_I2C_STATE_RESET = 0x00U, HAL_I2C_STATE_READY = 0x20U, HAL_I2C_STATE_BUSY = 0x24U, HAL_I2C_STATE_BUSY_TX = 0x21U,
HAL_I2C_STATE_BUSY_RX = 0x22U, HAL_I2C_STATE_LISTEN = 0x28U, HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU,
HAL_I2C_STATE_ABORT = 0x60U, HAL_I2C_STATE_TIMEOUT = 0xA0U, HAL_I2C_STATE_ERROR = 0xE0U
}
enum | HAL_I2C_ModeTypeDef { HAL_I2C_MODE_NONE = 0x00U, HAL_I2C_MODE_MASTER = 0x10U, HAL_I2C_MODE_SLAVE = 0x20U, HAL_I2C_MODE_MEM = 0x40U }
enum HAL_I2C_CallbackIDTypeDef {
HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U,
HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, HAL_I2C_ERROR_CB_ID = 0x07U,
HAL_I2C_ABORT_CB_ID = 0x08U, HAL_I2C_MSPINIT_CB_ID = 0x09U, HAL_I2C_MSPDEINIT_CB_ID = 0x0AU
}
HAL I2C Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_I2C_Init (I2C_HandleTypeDef *hi2c)
Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C peripheral.
__weak void | HAL_I2C_MspInit (I2C_HandleTypeDef *hi2c)
Initialize the I2C MSP.
__weak void | HAL_I2C_MspDeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C MSP.
HAL_StatusTypeDef | HAL_I2C_RegisterCallback (I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)
Register a User I2C Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_I2C_UnRegisterCallback (I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
Unregister an I2C Callback I2C callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_I2C_RegisterAddrCallback (I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
Register the Slave Address Match I2C Callback To be used instead of the weak HAL_I2C_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_I2C_UnRegisterAddrCallback (I2C_HandleTypeDef *hi2c)
UnRegister the Slave Address Match I2C Callback Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Receive (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Mem_Write (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Write an amount of data in blocking mode to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Read an amount of data in blocking mode from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_IsDeviceReady (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Checks if target device is ready for communication.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with Interrupt to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Read an amount of data in non-blocking mode with Interrupt from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_EnableListen_IT (I2C_HandleTypeDef *hi2c)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_DisableListen_IT (I2C_HandleTypeDef *hi2c)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Abort_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
Abort a master I2C IT or DMA process communication with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with DMA to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Reads an amount of data in non-blocking mode with DMA from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA.
void | HAL_I2C_EV_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C event interrupt request.
void | HAL_I2C_ER_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C error interrupt request.
__weak void | HAL_I2C_MasterTxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Tx Transfer completed callback.
__weak void | HAL_I2C_MasterRxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Rx Transfer completed callback.
__weak void | HAL_I2C_SlaveTxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Tx Transfer completed callback.
__weak void | HAL_I2C_SlaveRxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Rx Transfer completed callback.
__weak void | HAL_I2C_AddrCallback (I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_I2C_ListenCpltCallback (I2C_HandleTypeDef *hi2c)
Listen Complete callback.
__weak void | HAL_I2C_MemTxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Tx Transfer completed callback.
__weak void | HAL_I2C_MemRxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Rx Transfer completed callback.
__weak void | HAL_I2C_ErrorCallback (I2C_HandleTypeDef *hi2c)
I2C error callback.
__weak void | HAL_I2C_AbortCpltCallback (I2C_HandleTypeDef *hi2c)
I2C abort callback.
HAL_I2C_StateTypeDef | HAL_I2C_GetState (I2C_HandleTypeDef *hi2c)
Return the I2C handle state.
HAL_I2C_ModeTypeDef | HAL_I2C_GetMode (I2C_HandleTypeDef *hi2c)
Returns the I2C Master, Slave, Memory or no mode.
uint32_t | HAL_I2C_GetError (I2C_HandleTypeDef *hi2c)
Return the I2C error code.

Detailed Description

Header file of I2C HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_i2c.h.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_i2c_ex.h File Reference

  • File List
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  • Firmware
  • Drivers
  • STM32WBxx_HAL_Driver
  • Inc
Defines | Functions
stm32wbxx_hal_i2c_ex.h File Reference

Header file of I2C HAL Extended module. More...

#include "stm32wbxx_hal_def.h"

Go to the source code of this file.

Defines

#define | I2C_ANALOGFILTER_ENABLE 0x00000000U
#define | I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
#define | I2C_FMP_NOT_SUPPORTED 0xAAAA0000U
#define | I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP
#define | I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP
#define | I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP
#define | I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP
#define | I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP
#define | I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP
#define | IS_I2C_ANALOG_FILTER(FILTER)
#define | IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define | IS_I2C_FASTMODEPLUS(__CONFIG__)

Functions

HAL_StatusTypeDef | HAL_I2CEx_ConfigAnalogFilter (I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
Configure I2C Analog noise filter.
HAL_StatusTypeDef | HAL_I2CEx_ConfigDigitalFilter (I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
Configure I2C Digital noise filter.
HAL_StatusTypeDef | HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
Enable I2C wakeup from Stop mode(s).
HAL_StatusTypeDef | HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
Disable I2C wakeup from Stop mode(s).
void | HAL_I2CEx_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the I2C fast mode plus driving capability.
void | HAL_I2CEx_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the I2C fast mode plus driving capability.

Detailed Description

Header file of I2C HAL Extended module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_i2c_ex.h.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_ipcc.h File Reference

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stm32wbxx_hal_ipcc.h File Reference

Header file of Mailbox HAL module. More...

#include "stm32wbxx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | __IPCC_HandleTypeDef
IPCC handle structure definition. More...

Defines

#define | IPCC_CHANNEL_1 0x00000000U
#define | IPCC_CHANNEL_2 0x00000001U
#define | IPCC_CHANNEL_3 0x00000002U
#define | IPCC_CHANNEL_4 0x00000003U
#define | IPCC_CHANNEL_5 0x00000004U
#define | IPCC_CHANNEL_6 0x00000005U
#define | __HAL_IPCC_ENABLE_IT(__HANDLE__, __CHDIRECTION__)
Enable the specified interrupt.
#define | __HAL_IPCC_DISABLE_IT(__HANDLE__, __CHDIRECTION__)
Disable the specified interrupt.
#define | __HAL_IPCC_MASK_CHANNEL_IT(__HANDLE__, __CHDIRECTION__, __CHINDEX__)
Mask the specified interrupt.
#define | __HAL_IPCC_UNMASK_CHANNEL_IT(__HANDLE__, __CHDIRECTION__, __CHINDEX__)
Unmask the specified interrupt.

Typedefs

typedef struct __IPCC_HandleTypeDef | IPCC_HandleTypeDef
IPCC handle structure definition.
typedef void | ChannelCb (IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
IPCC callback typedef.

Enumerations

enum | HAL_IPCC_StateTypeDef { HAL_IPCC_STATE_RESET = 0x00U, HAL_IPCC_STATE_READY = 0x01U, HAL_IPCC_STATE_BUSY = 0x02U }
HAL IPCC State structures definition. More...
enum | IPCC_CHANNELDirTypeDef { IPCC_CHANNEL_DIR_TX = 0x00U, IPCC_CHANNEL_DIR_RX = 0x01U }
IPCC channel direction structure definition. More...
enum | IPCC_CHANNELStatusTypeDef { IPCC_CHANNEL_STATUS_FREE = 0x00U, IPCC_CHANNEL_STATUS_OCCUPIED = 0x01U }
IPCC channel status structure definition. More...

Functions

HAL_StatusTypeDef | HAL_IPCC_Init (IPCC_HandleTypeDef *hipcc)
Initialize the IPCC peripheral.
HAL_StatusTypeDef | HAL_IPCC_DeInit (IPCC_HandleTypeDef *hipcc)
DeInitialize the IPCC peripheral.
__weak void | HAL_IPCC_MspInit (IPCC_HandleTypeDef *hipcc)
Initialize the IPCC MSP.
__weak void | HAL_IPCC_MspDeInit (IPCC_HandleTypeDef *hipcc)
IPCC MSP DeInit.
HAL_StatusTypeDef | HAL_IPCC_ActivateNotification (IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir, ChannelCb cb)
Activate the callback notification on receive/transmit interrupt.
HAL_StatusTypeDef | HAL_IPCC_DeActivateNotification (IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
Remove the callback notification on receive/transmit interrupt.
IPCC_CHANNELStatusTypeDef | HAL_IPCC_GetChannelStatus (IPCC_HandleTypeDef const *const hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
Get state of IPCC channel.
HAL_StatusTypeDef | HAL_IPCC_NotifyCPU (IPCC_HandleTypeDef const *const hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
Notify remote processor.
HAL_IPCC_StateTypeDef | HAL_IPCC_GetState (IPCC_HandleTypeDef const *const hipcc)
Return the IPCC handle state.
void | HAL_IPCC_TX_IRQHandler (IPCC_HandleTypeDef *const hipcc)
This function handles IPCC Tx Free interrupt request.
void | HAL_IPCC_RX_IRQHandler (IPCC_HandleTypeDef *const hipcc)
This function handles IPCC Rx Occupied interrupt request.
__weak void | HAL_IPCC_TxCallback (IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
Tx free callback.
__weak void | HAL_IPCC_RxCallback (IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
Rx occupied callback.

Detailed Description

Header file of Mailbox HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_ipcc.h.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_irda.h File Reference

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stm32wbxx_hal_irda.h File Reference

Header file of IRDA HAL module. More...

#include "stm32wbxx_hal_def.h"
#include "stm32wbxx_hal_irda_ex.h"

Go to the source code of this file.

Data Structures

struct | IRDA_InitTypeDef
IRDA Init Structure definition. More...
struct | __IRDA_HandleTypeDef
IRDA handle Structure definition. More...

Defines

#define | HAL_IRDA_STATE_RESET 0x00000000U
#define | HAL_IRDA_STATE_READY 0x00000020U
#define | HAL_IRDA_STATE_BUSY 0x00000024U
#define | HAL_IRDA_STATE_BUSY_TX 0x00000021U
#define | HAL_IRDA_STATE_BUSY_RX 0x00000022U
#define | HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U
#define | HAL_IRDA_STATE_TIMEOUT 0x000000A0U
#define | HAL_IRDA_STATE_ERROR 0x000000E0U
#define | HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_IRDA_ERROR_PE ((uint32_t)0x00000001U)
#define | HAL_IRDA_ERROR_NE ((uint32_t)0x00000002U)
#define | HAL_IRDA_ERROR_FE ((uint32_t)0x00000004U)
#define | HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008U)
#define | HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010U)
#define | HAL_IRDA_ERROR_BUSY ((uint32_t)0x00000020U)
#define | HAL_IRDA_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U)
#define | IRDA_WORDLENGTH_7B USART_CR1_M1
#define | IRDA_WORDLENGTH_8B 0x00000000U
#define | IRDA_WORDLENGTH_9B USART_CR1_M0
#define | IRDA_PARITY_NONE 0x00000000U
#define | IRDA_PARITY_EVEN USART_CR1_PCE
#define | IRDA_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)
#define | IRDA_MODE_RX USART_CR1_RE
#define | IRDA_MODE_TX USART_CR1_TE
#define | IRDA_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)
#define | IRDA_POWERMODE_NORMAL 0x00000000U
#define | IRDA_POWERMODE_LOWPOWER USART_CR3_IRLP
#define | IRDA_PRESCALER_DIV1 0x00000000U
#define | IRDA_PRESCALER_DIV2 0x00000001U
#define | IRDA_PRESCALER_DIV4 0x00000002U
#define | IRDA_PRESCALER_DIV6 0x00000003U
#define | IRDA_PRESCALER_DIV8 0x00000004U
#define | IRDA_PRESCALER_DIV10 0x00000005U
#define | IRDA_PRESCALER_DIV12 0x00000006U
#define | IRDA_PRESCALER_DIV16 0x00000007U
#define | IRDA_PRESCALER_DIV32 0x00000008U
#define | IRDA_PRESCALER_DIV64 0x00000009U
#define | IRDA_PRESCALER_DIV128 0x0000000AU
#define | IRDA_PRESCALER_DIV256 0x0000000BU
#define | IRDA_STATE_DISABLE 0x00000000U
#define | IRDA_STATE_ENABLE USART_CR1_UE
#define | IRDA_MODE_DISABLE 0x00000000U
#define | IRDA_MODE_ENABLE USART_CR3_IREN
#define | IRDA_ONE_BIT_SAMPLE_DISABLE 0x00000000U
#define | IRDA_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT
#define | IRDA_DMA_TX_DISABLE 0x00000000U
#define | IRDA_DMA_TX_ENABLE USART_CR3_DMAT
#define | IRDA_DMA_RX_DISABLE 0x00000000U
#define | IRDA_DMA_RX_ENABLE USART_CR3_DMAR
#define | IRDA_AUTOBAUD_REQUEST USART_RQR_ABRRQ
#define | IRDA_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ
#define | IRDA_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ
#define | IRDA_FLAG_REACK USART_ISR_REACK
#define | IRDA_FLAG_TEACK USART_ISR_TEACK
#define | IRDA_FLAG_BUSY USART_ISR_BUSY
#define | IRDA_FLAG_ABRF USART_ISR_ABRF
#define | IRDA_FLAG_ABRE USART_ISR_ABRE
#define | IRDA_FLAG_TXE USART_ISR_TXE_TXFNF
#define | IRDA_FLAG_TC USART_ISR_TC
#define | IRDA_FLAG_RXNE USART_ISR_RXNE_RXFNE
#define | IRDA_FLAG_ORE USART_ISR_ORE
#define | IRDA_FLAG_NE USART_ISR_NE
#define | IRDA_FLAG_FE USART_ISR_FE
#define | IRDA_FLAG_PE USART_ISR_PE
#define | IRDA_IT_PE 0x0028U
#define | IRDA_IT_TXE 0x0727U
#define | IRDA_IT_TC 0x0626U
#define | IRDA_IT_RXNE 0x0525U
#define | IRDA_IT_IDLE 0x0424U
#define | IRDA_IT_ERR 0x0060U
#define | IRDA_IT_ORE 0x0300U
#define | IRDA_IT_NE 0x0200U
#define | IRDA_IT_FE 0x0100U
#define | IRDA_CLEAR_PEF USART_ICR_PECF
#define | IRDA_CLEAR_FEF USART_ICR_FECF
#define | IRDA_CLEAR_NEF USART_ICR_NECF
#define | IRDA_CLEAR_OREF USART_ICR_ORECF
#define | IRDA_CLEAR_IDLEF USART_ICR_IDLECF
#define | IRDA_CLEAR_TCF USART_ICR_TCCF
#define | IRDA_IT_MASK 0x001FU
#define | IRDA_CR_MASK 0x00E0U
#define | IRDA_CR_POS 5U
#define | IRDA_ISR_MASK 0x1F00U
#define | IRDA_ISR_POS 8U
#define | __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)
Reset IRDA handle state.
#define | __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__)
Flush the IRDA DR register.
#define | __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified IRDA pending flag.
#define | __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
Clear the IRDA PE pending flag.
#define | __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
Clear the IRDA FE pending flag.
#define | __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
Clear the IRDA NE pending flag.
#define | __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
Clear the IRDA ORE pending flag.
#define | __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
Clear the IRDA IDLE pending flag.
#define | __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified IRDA flag is set or not.
#define | __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified IRDA interrupt.
#define | __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified IRDA interrupt.
#define | __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET)
Check whether the specified IRDA interrupt has occurred or not.
#define | __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified IRDA interrupt source is enabled or not.
#define | __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
#define | __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific IRDA request flag.
#define | __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the IRDA one bit sample method.
#define | __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
Disable the IRDA one bit sample method.
#define | __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable UART/USART associated to IRDA Handle.
#define | __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable UART/USART associated to IRDA Handle.
#define | IRDA_MASK_COMPUTATION(__HANDLE__)
Compute the mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U)
Ensure that IRDA Baud rate is less or equal to maximum value.
#define | IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U)
Ensure that IRDA prescaler value is strictly larger than 0.
#define | IS_IRDA_WORD_LENGTH(__LENGTH__)
Ensure that IRDA frame length is valid.
#define | IS_IRDA_PARITY(__PARITY__)
Ensure that IRDA frame parity is valid.
#define | IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
Ensure that IRDA communication mode is valid.
#define | IS_IRDA_POWERMODE(__MODE__)
Ensure that IRDA power mode is valid.
#define | IS_IRDA_CLOCKPRESCALER(__CLOCKPRESCALER__)
Ensure that IRDA clock Prescaler is valid.
#define | IS_IRDA_STATE(__STATE__)
Ensure that IRDA state is valid.
#define | IS_IRDA_MODE(__MODE__)
Ensure that IRDA associated UART/USART mode is valid.
#define | IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that IRDA sampling rate is valid.
#define | IS_IRDA_DMA_TX(__DMATX__)
Ensure that IRDA DMA TX mode is valid.
#define | IS_IRDA_DMA_RX(__DMARX__)
Ensure that IRDA DMA RX mode is valid.
#define | IS_IRDA_REQUEST_PARAMETER(__PARAM__)
Ensure that IRDA request is valid.

Typedefs

typedef uint32_t | HAL_IRDA_StateTypeDef
HAL IRDA State definition.
typedef struct __IRDA_HandleTypeDef | IRDA_HandleTypeDef
IRDA handle Structure definition.
typedef void(* | pIRDA_CallbackTypeDef )(IRDA_HandleTypeDef *hirda)
HAL IRDA Callback pointer definition.

Enumerations

enum IRDA_ClockSourceTypeDef {
IRDA_CLOCKSOURCE_PCLK2 = 0x01U, IRDA_CLOCKSOURCE_HSI = 0x02U, IRDA_CLOCKSOURCE_SYSCLK = 0x04U, IRDA_CLOCKSOURCE_LSE = 0x10U,
IRDA_CLOCKSOURCE_UNDEFINED = 0x20U
}
IRDA clock sources definition. More...
enum HAL_IRDA_CallbackIDTypeDef {
HAL_IRDA_TX_HALFCOMPLETE_CB_ID = 0x00U, HAL_IRDA_TX_COMPLETE_CB_ID = 0x01U, HAL_IRDA_RX_HALFCOMPLETE_CB_ID = 0x02U, HAL_IRDA_RX_COMPLETE_CB_ID = 0x03U,
HAL_IRDA_ERROR_CB_ID = 0x04U, HAL_IRDA_ABORT_COMPLETE_CB_ID = 0x05U, HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U,
HAL_IRDA_MSPINIT_CB_ID = 0x08U, HAL_IRDA_MSPDEINIT_CB_ID = 0x09U
}
HAL IRDA Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_IRDA_Init (IRDA_HandleTypeDef *hirda)
Initialize the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_IRDA_DeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA peripheral.
__weak void | HAL_IRDA_MspInit (IRDA_HandleTypeDef *hirda)
Initialize the IRDA MSP.
__weak void | HAL_IRDA_MspDeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA MSP.
HAL_StatusTypeDef | HAL_IRDA_RegisterCallback (IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback)
Register a User IRDA Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_IRDA_UnRegisterCallback (IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID)
Unregister an IRDA callback IRDA callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_IRDA_Transmit (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_DMAPause (IRDA_HandleTypeDef *hirda)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAResume (IRDA_HandleTypeDef *hirda)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAStop (IRDA_HandleTypeDef *hirda)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_Abort (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_Abort_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_IRDA_IRQHandler (IRDA_HandleTypeDef *hirda)
Handle IRDA interrupt request.
__weak void | HAL_IRDA_TxCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Transfer completed callback.
__weak void | HAL_IRDA_RxCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Transfer completed callback.
__weak void | HAL_IRDA_TxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Half Transfer completed callback.
__weak void | HAL_IRDA_RxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Half Transfer complete callback.
__weak void | HAL_IRDA_ErrorCallback (IRDA_HandleTypeDef *hirda)
IRDA error callback.
__weak void | HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Complete callback.
__weak void | HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Complete callback.
__weak void | HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Receive Complete callback.
HAL_IRDA_StateTypeDef | HAL_IRDA_GetState (IRDA_HandleTypeDef *hirda)
Return the IRDA handle state.
uint32_t | HAL_IRDA_GetError (IRDA_HandleTypeDef *hirda)
Return the IRDA handle error code.

Detailed Description

Header file of IRDA HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_irda.h.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_irda_ex.h File Reference

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Defines
stm32wbxx_hal_irda_ex.h File Reference

Header file of IRDA HAL Extended module. More...

#include "stm32wbxx_hal_def.h"

Go to the source code of this file.

Defines

#define IRDA_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the IRDA clock source.

Detailed Description

Header file of IRDA HAL Extended module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_irda_ex.h.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_iwdg.h File Reference

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Data Structures | Defines | Functions
stm32wbxx_hal_iwdg.h File Reference

Header file of IWDG HAL module. More...

#include "stm32wbxx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | IWDG_InitTypeDef
IWDG Init structure definition. More...
struct | IWDG_HandleTypeDef
IWDG Handle Structure definition. More...

Defines

#define | IWDG_PRESCALER_4 0x00000000u
#define | IWDG_PRESCALER_8 IWDG_PR_PR_0
#define | IWDG_PRESCALER_16 IWDG_PR_PR_1
#define | IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)
#define | IWDG_PRESCALER_64 IWDG_PR_PR_2
#define | IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)
#define | IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)
#define | IWDG_WINDOW_DISABLE IWDG_WINR_WIN
#define | __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
Enable the IWDG peripheral.
#define | __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
Reload IWDG counter with value defined in the reload register (write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers disabled).
#define | IWDG_KEY_RELOAD 0x0000AAAAu
IWDG Key Register BitMask.
#define | IWDG_KEY_ENABLE 0x0000CCCCu
#define | IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u
#define | IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u
#define | IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
#define | IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
#define | IS_IWDG_PRESCALER(__PRESCALER__)
Check IWDG prescaler value.
#define | IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
Check IWDG reload value.
#define | IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
Check IWDG window value.

Functions

HAL_StatusTypeDef | HAL_IWDG_Init (IWDG_HandleTypeDef *hiwdg)
Initialize the IWDG according to the specified parameters in the IWDG_InitTypeDef and start watchdog.
HAL_StatusTypeDef | HAL_IWDG_Refresh (IWDG_HandleTypeDef *hiwdg)
Refresh the IWDG.

Detailed Description

Header file of IWDG HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_iwdg.h.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_lcd.h File Reference

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stm32wbxx_hal_lcd.h File Reference

Header file of LCD Controller HAL module. More...

#include "stm32wbxx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | LCD_InitTypeDef
LCD Init structure definition. More...
struct | LCD_HandleTypeDef
UART handle Structure definition. More...

Defines

#define | HAL_LCD_ERROR_NONE (0x00000000U)
#define | HAL_LCD_ERROR_FCRSF (0x00000001U)
#define | HAL_LCD_ERROR_UDR (0x00000002U)
#define | HAL_LCD_ERROR_UDD (0x00000004U)
#define | HAL_LCD_ERROR_ENS (0x00000008U)
#define | HAL_LCD_ERROR_RDY (0x00000010U)
#define | LCD_PRESCALER_1 (0x00000000U)
#define | LCD_PRESCALER_2 (0x00400000U)
#define | LCD_PRESCALER_4 (0x00800000U)
#define | LCD_PRESCALER_8 (0x00C00000U)
#define | LCD_PRESCALER_16 (0x01000000U)
#define | LCD_PRESCALER_32 (0x01400000U)
#define | LCD_PRESCALER_64 (0x01800000U)
#define | LCD_PRESCALER_128 (0x01C00000U)
#define | LCD_PRESCALER_256 (0x02000000U)
#define | LCD_PRESCALER_512 (0x02400000U)
#define | LCD_PRESCALER_1024 (0x02800000U)
#define | LCD_PRESCALER_2048 (0x02C00000U)
#define | LCD_PRESCALER_4096 (0x03000000U)
#define | LCD_PRESCALER_8192 (0x03400000U)
#define | LCD_PRESCALER_16384 (0x03800000U)
#define | LCD_PRESCALER_32768 (0x03C00000U)
#define | LCD_DIVIDER_16 (0x00000000U)
#define | LCD_DIVIDER_17 (0x00040000U)
#define | LCD_DIVIDER_18 (0x00080000U)
#define | LCD_DIVIDER_19 (0x000C0000U)
#define | LCD_DIVIDER_20 (0x00100000U)
#define | LCD_DIVIDER_21 (0x00140000U)
#define | LCD_DIVIDER_22 (0x00180000U)
#define | LCD_DIVIDER_23 (0x001C0000U)
#define | LCD_DIVIDER_24 (0x00200000U)
#define | LCD_DIVIDER_25 (0x00240000U)
#define | LCD_DIVIDER_26 (0x00280000U)
#define | LCD_DIVIDER_27 (0x002C0000U)
#define | LCD_DIVIDER_28 (0x00300000U)
#define | LCD_DIVIDER_29 (0x00340000U)
#define | LCD_DIVIDER_30 (0x00380000U)
#define | LCD_DIVIDER_31 (0x003C0000U)
#define | LCD_DUTY_STATIC (0x00000000U)
#define | LCD_DUTY_1_2 (LCD_CR_DUTY_0)
#define | LCD_DUTY_1_3 (LCD_CR_DUTY_1)
#define | LCD_DUTY_1_4 ((LCD_CR_DUTY_1 | LCD_CR_DUTY_0))
#define | LCD_DUTY_1_8 (LCD_CR_DUTY_2)
#define | LCD_BIAS_1_4 (0x00000000U)
#define | LCD_BIAS_1_2 LCD_CR_BIAS_0
#define | LCD_BIAS_1_3 LCD_CR_BIAS_1
#define | LCD_VOLTAGESOURCE_INTERNAL (0x00000000U)
#define | LCD_VOLTAGESOURCE_EXTERNAL LCD_CR_VSEL
#define | LCD_IT_SOF LCD_FCR_SOFIE
#define | LCD_IT_UDD LCD_FCR_UDDIE
#define | LCD_PULSEONDURATION_0 (0x00000000U)
#define | LCD_PULSEONDURATION_1 (LCD_FCR_PON_0)
#define | LCD_PULSEONDURATION_2 (LCD_FCR_PON_1)
#define | LCD_PULSEONDURATION_3 (LCD_FCR_PON_1 | LCD_FCR_PON_0)
#define | LCD_PULSEONDURATION_4 (LCD_FCR_PON_2)
#define | LCD_PULSEONDURATION_5 (LCD_FCR_PON_2 | LCD_FCR_PON_0)
#define | LCD_PULSEONDURATION_6 (LCD_FCR_PON_2 | LCD_FCR_PON_1)
#define | LCD_PULSEONDURATION_7 (LCD_FCR_PON)
#define | LCD_DEADTIME_0 (0x00000000U)
#define | LCD_DEADTIME_1 (LCD_FCR_DEAD_0)
#define | LCD_DEADTIME_2 (LCD_FCR_DEAD_1)
#define | LCD_DEADTIME_3 (LCD_FCR_DEAD_1 | LCD_FCR_DEAD_0)
#define | LCD_DEADTIME_4 (LCD_FCR_DEAD_2)
#define | LCD_DEADTIME_5 (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_0)
#define | LCD_DEADTIME_6 (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_1)
#define | LCD_DEADTIME_7 (LCD_FCR_DEAD)
#define | LCD_BLINKMODE_OFF (0x00000000U)
#define | LCD_BLINKMODE_SEG0_COM0 (LCD_FCR_BLINK_0)
#define | LCD_BLINKMODE_SEG0_ALLCOM (LCD_FCR_BLINK_1)
#define | LCD_BLINKMODE_ALLSEG_ALLCOM (LCD_FCR_BLINK)
#define | LCD_BLINKFREQUENCY_DIV8 (0x00000000U)
#define | LCD_BLINKFREQUENCY_DIV16 (LCD_FCR_BLINKF_0)
#define | LCD_BLINKFREQUENCY_DIV32 (LCD_FCR_BLINKF_1)
#define | LCD_BLINKFREQUENCY_DIV64 (LCD_FCR_BLINKF_1 | LCD_FCR_BLINKF_0)
#define | LCD_BLINKFREQUENCY_DIV128 (LCD_FCR_BLINKF_2)
#define | LCD_BLINKFREQUENCY_DIV256 (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_0)
#define | LCD_BLINKFREQUENCY_DIV512 (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_1)
#define | LCD_BLINKFREQUENCY_DIV1024 (LCD_FCR_BLINKF)
#define | LCD_CONTRASTLEVEL_0 (0x00000000U)
#define | LCD_CONTRASTLEVEL_1 (LCD_FCR_CC_0)
#define | LCD_CONTRASTLEVEL_2 (LCD_FCR_CC_1)
#define | LCD_CONTRASTLEVEL_3 (LCD_FCR_CC_1 | LCD_FCR_CC_0)
#define | LCD_CONTRASTLEVEL_4 (LCD_FCR_CC_2)
#define | LCD_CONTRASTLEVEL_5 (LCD_FCR_CC_2 | LCD_FCR_CC_0)
#define | LCD_CONTRASTLEVEL_6 (LCD_FCR_CC_2 | LCD_FCR_CC_1)
#define | LCD_CONTRASTLEVEL_7 (LCD_FCR_CC)
#define | LCD_RAM_REGISTER0 (0x00000000U)
#define | LCD_RAM_REGISTER1 (0x00000001U)
#define | LCD_RAM_REGISTER2 (0x00000002U)
#define | LCD_RAM_REGISTER3 (0x00000003U)
#define | LCD_RAM_REGISTER4 (0x00000004U)
#define | LCD_RAM_REGISTER5 (0x00000005U)
#define | LCD_RAM_REGISTER6 (0x00000006U)
#define | LCD_RAM_REGISTER7 (0x00000007U)
#define | LCD_RAM_REGISTER8 (0x00000008U)
#define | LCD_RAM_REGISTER9 (0x00000009U)
#define | LCD_RAM_REGISTER10 (0x0000000AU)
#define | LCD_RAM_REGISTER11 (0x0000000BU)
#define | LCD_RAM_REGISTER12 (0x0000000CU)
#define | LCD_RAM_REGISTER13 (0x0000000DU)
#define | LCD_RAM_REGISTER14 (0x0000000EU)
#define | LCD_RAM_REGISTER15 (0x0000000FU)
#define | LCD_HIGHDRIVE_DISABLE ((uint32_t)0x00000000)
#define | LCD_HIGHDRIVE_ENABLE (LCD_FCR_HD)
#define | LCD_MUXSEGMENT_DISABLE (0x00000000U)
#define | LCD_MUXSEGMENT_ENABLE (LCD_CR_MUX_SEG)
#define | LCD_FLAG_ENS LCD_SR_ENS
#define | LCD_FLAG_SOF LCD_SR_SOF
#define | LCD_FLAG_UDR LCD_SR_UDR
#define | LCD_FLAG_UDD LCD_SR_UDD
#define | LCD_FLAG_RDY LCD_SR_RDY
#define | LCD_FLAG_FCRSF LCD_SR_FCRSR
#define | __HAL_LCD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LCD_STATE_RESET)
Reset LCD handle state.
#define | __HAL_LCD_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN)
Enable the LCD peripheral.
#define | __HAL_LCD_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN)
Disable the LCD peripheral.
#define | __HAL_LCD_HIGHDRIVER_ENABLE(__HANDLE__)
Enable the low resistance divider.
#define | __HAL_LCD_HIGHDRIVER_DISABLE(__HANDLE__)
Disable the low resistance divider.
#define | __HAL_LCD_VOLTAGE_BUFFER_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_BUFEN)
Enable the voltage output buffer for higher driving capability.
#define | __HAL_LCD_VOLTAGE_BUFFER_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_BUFEN)
Disable the voltage output buffer for higher driving capability.
#define | __HAL_LCD_PULSEONDURATION_CONFIG(__HANDLE__, __DURATION__)
Configure the LCD pulse on duration.
#define | __HAL_LCD_DEADTIME_CONFIG(__HANDLE__, __DEADTIME__)
Configure the LCD dead time.
#define | __HAL_LCD_CONTRAST_CONFIG(__HANDLE__, __CONTRAST__)
Configure the LCD contrast.
#define | __HAL_LCD_BLINK_CONFIG(__HANDLE__, __BLINKMODE__, __BLINKFREQUENCY__)
Configure the LCD Blink mode and Blink frequency.
#define | __HAL_LCD_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified LCD interrupt.
#define | __HAL_LCD_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified LCD interrupt.
#define | __HAL_LCD_GET_IT_SOURCE(__HANDLE__, __IT__) (((__HANDLE__)->Instance->FCR) & (__IT__))
Check whether the specified LCD interrupt source is enabled or not.
#define | __HAL_LCD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check whether the specified LCD flag is set or not.
#define | __HAL_LCD_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->CLR, (__FLAG__))
Clear the specified LCD pending flag.
#define | IS_LCD_PRESCALER(__PRESCALER__)
#define | IS_LCD_DIVIDER(__DIVIDER__)
#define | IS_LCD_DUTY(__DUTY__)
#define | IS_LCD_BIAS(__BIAS__)
#define | IS_LCD_VOLTAGE_SOURCE(SOURCE)
#define | IS_LCD_PULSE_ON_DURATION(__DURATION__)
#define | IS_LCD_DEAD_TIME(__TIME__)
#define | IS_LCD_BLINK_MODE(__MODE__)
#define | IS_LCD_BLINK_FREQUENCY(__FREQUENCY__)
#define | IS_LCD_CONTRAST(__CONTRAST__)
#define | IS_LCD_RAM_REGISTER(__REGISTER__)
#define | IS_LCD_HIGH_DRIVE(__VALUE__)
#define | IS_LCD_MUX_SEGMENT(__VALUE__)

Enumerations

enum HAL_LCD_StateTypeDef {
HAL_LCD_STATE_RESET = 0x00, HAL_LCD_STATE_READY = 0x01, HAL_LCD_STATE_BUSY = 0x02, HAL_LCD_STATE_TIMEOUT = 0x03,
HAL_LCD_STATE_ERROR = 0x04
}
HAL LCD State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_LCD_DeInit (LCD_HandleTypeDef *hlcd)
DeInitialize the LCD peripheral.
HAL_StatusTypeDef | HAL_LCD_Init (LCD_HandleTypeDef *hlcd)
Initialize the LCD peripheral according to the specified parameters in the LCD_InitStruct and initialize the associated handle.
__weak void | HAL_LCD_MspInit (LCD_HandleTypeDef *hlcd)
Initialize the LCD MSP.
__weak void | HAL_LCD_MspDeInit (LCD_HandleTypeDef *hlcd)
DeInitialize the LCD MSP.
HAL_StatusTypeDef | HAL_LCD_Write (LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterIndex, uint32_t RAMRegisterMask, uint32_t Data)
Write a word in the specific LCD RAM.
HAL_StatusTypeDef | HAL_LCD_Clear (LCD_HandleTypeDef *hlcd)
Clear the LCD RAM registers.
HAL_StatusTypeDef | HAL_LCD_UpdateDisplayRequest (LCD_HandleTypeDef *hlcd)
Enable the Update Display Request.
HAL_LCD_StateTypeDef | HAL_LCD_GetState (LCD_HandleTypeDef *hlcd)
Return the LCD handle state.
uint32_t | HAL_LCD_GetError (LCD_HandleTypeDef *hlcd)
Return the LCD error code.
HAL_StatusTypeDef | LCD_WaitForSynchro (LCD_HandleTypeDef *hlcd)
Wait until the LCD FCR register is synchronized in the LCDCLK domain.

Detailed Description

Header file of LCD Controller HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_lcd.h.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_lptim.h File Reference

  • File List
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stm32wbxx_hal_lptim.h File Reference

Header file of LPTIM HAL module. More...

#include "stm32wbxx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | LPTIM_ClockConfigTypeDef
LPTIM Clock configuration definition. More...
struct | LPTIM_ULPClockConfigTypeDef
LPTIM Clock configuration definition. More...
struct | LPTIM_TriggerConfigTypeDef
LPTIM Trigger configuration definition. More...
struct | LPTIM_InitTypeDef
LPTIM Initialization Structure definition. More...
struct | __LPTIM_HandleTypeDef
LPTIM handle Structure definition. More...

Defines

#define | LPTIM_EXTI_LINE_LPTIM1 EXTI_IMR1_IM29
#define | LPTIM_EXTI_LINE_LPTIM2 EXTI_IMR1_IM30
#define | LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC 0x00000000U
#define | LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL
#define | LPTIM_PRESCALER_DIV1 0x00000000U
#define | LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
#define | LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
#define | LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1)
#define | LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
#define | LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2)
#define | LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2)
#define | LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC
#define | LPTIM_OUTPUTPOLARITY_HIGH 0x00000000U
#define | LPTIM_OUTPUTPOLARITY_LOW LPTIM_CFGR_WAVPOL
#define | LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 0x00000000U
#define | LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0
#define | LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1
#define | LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT
#define | LPTIM_CLOCKPOLARITY_RISING 0x00000000U
#define | LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0
#define | LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1
#define | LPTIM_TRIGSOURCE_SOFTWARE 0x0000FFFFU
#define | LPTIM_TRIGSOURCE_0 0x00000000U
#define | LPTIM_TRIGSOURCE_1 LPTIM_CFGR_TRIGSEL_0
#define | LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1
#define | LPTIM_TRIGSOURCE_3 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
#define | LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2
#define | LPTIM_TRIGSOURCE_5 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
#define | LPTIM_TRIGSOURCE_6 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)
#define | LPTIM_TRIGSOURCE_7 LPTIM_CFGR_TRIGSEL
#define | LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0
#define | LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1
#define | LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN
#define | LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 0x00000000U
#define | LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0
#define | LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1
#define | LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT
#define | LPTIM_UPDATE_IMMEDIATE 0x00000000U
#define | LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD
#define | LPTIM_COUNTERSOURCE_INTERNAL 0x00000000U
#define | LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE
#define | LPTIM_INPUT1SOURCE_GPIO 0x00000000U
#define | LPTIM_INPUT1SOURCE_COMP1 LPTIM_OR_OR_0
#define | LPTIM_INPUT1SOURCE_COMP2 LPTIM_OR_OR_1
#define | LPTIM_INPUT1SOURCE_COMP1_COMP2 LPTIM_OR_OR
#define | LPTIM_INPUT2SOURCE_GPIO 0x00000000U
#define | LPTIM_INPUT2SOURCE_COMP2 LPTIM_OR_OR_1
#define | LPTIM_FLAG_DOWN LPTIM_ISR_DOWN
#define | LPTIM_FLAG_UP LPTIM_ISR_UP
#define | LPTIM_FLAG_ARROK LPTIM_ISR_ARROK
#define | LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK
#define | LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG
#define | LPTIM_FLAG_ARRM LPTIM_ISR_ARRM
#define | LPTIM_FLAG_CMPM LPTIM_ISR_CMPM
#define | LPTIM_IT_DOWN LPTIM_IER_DOWNIE
#define | LPTIM_IT_UP LPTIM_IER_UPIE
#define | LPTIM_IT_ARROK LPTIM_IER_ARROKIE
#define | LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE
#define | LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE
#define | LPTIM_IT_ARRM LPTIM_IER_ARRMIE
#define | LPTIM_IT_CMPM LPTIM_IER_CMPMIE
#define | __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__)
Reset LPTIM handle state.
#define | __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
Enable the LPTIM peripheral.
#define | __HAL_LPTIM_DISABLE(__HANDLE__) LPTIM_Disable(__HANDLE__)
Disable the LPTIM peripheral.
#define | __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)
Start the LPTIM peripheral in Continuous mode.
#define | __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)
Start the LPTIM peripheral in single mode.
#define | __HAL_LPTIM_RESET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_COUNTRST)
Reset the LPTIM Counter register in synchronous mode.
#define | __HAL_LPTIM_RESET_COUNTER_AFTERREAD(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_RSTARE)
Reset after read of the LPTIM Counter register in asynchronous mode.
#define | __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
Write the passed parameter in the Autoreload register.
#define | __HAL_LPTIM_COMPARE_SET(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
Write the passed parameter in the Compare register.
#define | __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
Check whether the specified LPTIM flag is set or not.
#define | __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified LPTIM flag.
#define | __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enable the specified LPTIM interrupt.
#define | __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
Disable the specified LPTIM interrupt.
#define | __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified LPTIM interrupt source is enabled or not.
#define | __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() (EXTI->IMR1 |= LPTIM_EXTI_LINE_LPTIM1)
Enable the LPTIM1 EXTI line in interrupt mode.
#define | __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(LPTIM_EXTI_LINE_LPTIM1))
Disable the LPTIM1 EXTI line in interrupt mode.
#define | __HAL_LPTIM_LPTIM1_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= LPTIM_EXTI_LINE_LPTIM1)
Enable the LPTIM1 EXTI line in event mode.
#define | __HAL_LPTIM_LPTIM1_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(LPTIM_EXTI_LINE_LPTIM1))
Disable the LPTIM1 EXTI line in event mode.
#define | __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT() (EXTI->IMR1 |= LPTIM_EXTI_LINE_LPTIM2)
Enable the LPTIM2 EXTI line in interrupt mode.
#define | __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(LPTIM_EXTI_LINE_LPTIM2))
Disable the LPTIM2 EXTI line in interrupt mode.
#define | __HAL_LPTIM_LPTIM2_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= LPTIM_EXTI_LINE_LPTIM2)
Enable the LPTIM2 EXTI line in event mode.
#define | __HAL_LPTIM_LPTIM2_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(LPTIM_EXTI_LINE_LPTIM2))
Disable the LPTIM2 EXTI line in event mode.
#define | IS_LPTIM_CLOCK_SOURCE(__SOURCE__)
#define | IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__)
#define | IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)
#define | IS_LPTIM_OUTPUT_POLARITY(__POLARITY__)
#define | IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__)
#define | IS_LPTIM_CLOCK_POLARITY(__POLARITY__)
#define | IS_LPTIM_TRG_SOURCE(__TRIG__)
#define | IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__)
#define | IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__)
#define | IS_LPTIM_UPDATE_MODE(__MODE__)
#define | IS_LPTIM_COUNTER_SOURCE(__SOURCE__)
#define | IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFUL)
#define | IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL)
#define | IS_LPTIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0x0000FFFFUL)
#define | IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL)
#define | IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__)
#define | IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__)

Typedefs

typedef struct
__LPTIM_HandleTypeDef 		LPTIM_HandleTypeDef
LPTIM handle Structure definition.
typedef void(* | pLPTIM_CallbackTypeDef )(LPTIM_HandleTypeDef *hlptim)
HAL TIM Callback pointer definition.

Enumerations

enum HAL_LPTIM_StateTypeDef {
HAL_LPTIM_STATE_RESET = 0x00U, HAL_LPTIM_STATE_READY = 0x01U, HAL_LPTIM_STATE_BUSY = 0x02U, HAL_LPTIM_STATE_TIMEOUT = 0x03U,
HAL_LPTIM_STATE_ERROR = 0x04U
}
HAL LPTIM State structure definition. More...
enum HAL_LPTIM_CallbackIDTypeDef {
HAL_LPTIM_MSPINIT_CB_ID = 0x00U, HAL_LPTIM_MSPDEINIT_CB_ID = 0x01U, HAL_LPTIM_COMPARE_MATCH_CB_ID = 0x02U, HAL_LPTIM_AUTORELOAD_MATCH_CB_ID = 0x03U,
HAL_LPTIM_TRIGGER_CB_ID = 0x04U, HAL_LPTIM_COMPARE_WRITE_CB_ID = 0x05U, HAL_LPTIM_AUTORELOAD_WRITE_CB_ID = 0x06U, HAL_LPTIM_DIRECTION_UP_CB_ID = 0x07U,
HAL_LPTIM_DIRECTION_DOWN_CB_ID = 0x08U
}
HAL LPTIM Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_LPTIM_Init (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_LPTIM_DeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize the LPTIM peripheral.
void | HAL_LPTIM_MspInit (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM MSP.
void | HAL_LPTIM_MspDeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize LPTIM MSP.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM in Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode in interrupt mode.
uint32_t | HAL_LPTIM_ReadCounter (LPTIM_HandleTypeDef *hlptim)
Return the current counter value.
uint32_t | HAL_LPTIM_ReadAutoReload (LPTIM_HandleTypeDef *hlptim)
Return the current Autoreload (Period) value.
uint32_t | HAL_LPTIM_ReadCompare (LPTIM_HandleTypeDef *hlptim)
Return the current Compare (Pulse) value.
void | HAL_LPTIM_IRQHandler (LPTIM_HandleTypeDef *hlptim)
Handle LPTIM interrupt request.
void | HAL_LPTIM_CompareMatchCallback (LPTIM_HandleTypeDef *hlptim)
Compare match callback in non-blocking mode.
void | HAL_LPTIM_AutoReloadMatchCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload match callback in non-blocking mode.
void | HAL_LPTIM_TriggerCallback (LPTIM_HandleTypeDef *hlptim)
Trigger detected callback in non-blocking mode.
void | HAL_LPTIM_CompareWriteCallback (LPTIM_HandleTypeDef *hlptim)
Compare write callback in non-blocking mode.
void | HAL_LPTIM_AutoReloadWriteCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload write callback in non-blocking mode.
void | HAL_LPTIM_DirectionUpCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Down to Up callback in non-blocking mode.
void | HAL_LPTIM_DirectionDownCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Up to Down callback in non-blocking mode.
HAL_StatusTypeDef | HAL_LPTIM_RegisterCallback (LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback)
Register a User LPTIM callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_LPTIM_UnRegisterCallback (LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID)
Unregister a LPTIM callback LLPTIM callback is redirected to the weak predefined callback.
HAL_LPTIM_StateTypeDef | HAL_LPTIM_GetState (LPTIM_HandleTypeDef *hlptim)
Return the LPTIM handle state.
void | LPTIM_Disable (LPTIM_HandleTypeDef *hlptim)
Disable LPTIM HW instance.

Detailed Description

Header file of LPTIM HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_lptim.h.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_pcd.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32wbxx_hal_pcd.h File Reference

Header file of PCD HAL module. More...

#include "stm32wbxx_ll_usb.h"
#include "stm32wbxx_hal_pcd_ex.h"

Go to the source code of this file.

Data Structures

struct | __PCD_HandleTypeDef
PCD Handle Structure definition. More...

Defines

#define | PCD_SPEED_FULL USBD_FS_SPEED
#define | PCD_PHY_ULPI 1U
#define | PCD_PHY_EMBEDDED 2U
#define | PCD_PHY_UTMI 3U
#define | HAL_PCD_ERROR_INVALID_CALLBACK (0x00000010U)
#define | __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#define | __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))
#define | __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR1 |= USB_WAKEUP_EXTI_LINE
#define | __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR1 &= ~(USB_WAKEUP_EXTI_LINE)
#define | USB_WAKEUP_EXTI_LINE (0x1U << 28)
#define | PCD_EP0MPS_64 DEP0CTL_MPS_64
#define | PCD_EP0MPS_32 DEP0CTL_MPS_32
#define | PCD_EP0MPS_16 DEP0CTL_MPS_16
#define | PCD_EP0MPS_08 DEP0CTL_MPS_8
#define | PCD_ENDP0 0U
#define | PCD_ENDP1 1U
#define | PCD_ENDP2 2U
#define | PCD_ENDP3 3U
#define | PCD_ENDP4 4U
#define | PCD_ENDP5 5U
#define | PCD_ENDP6 6U
#define | PCD_ENDP7 7U
#define | PCD_SNG_BUF 0U
#define | PCD_DBL_BUF 1U
#define | USB_CNTRX_NBLK_MSK (0x1FU << 10)
#define | USB_CNTRX_BLSIZE (0x1U << 15)
#define | PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue))
#define | PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))
#define | USB_EP0StartXfer USB_EPStartXfer
#define | PCD_SET_EPTYPE(USBx, bEpNum, wType)
sets the type in the endpoint register(bits EP_TYPE[1:0])
#define | PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)
gets the type in the endpoint register(bits EP_TYPE[1:0])
#define | PCD_FreeUserBuffer(USBx, bEpNum, bDir)
free buffer used from the application realizing it to the line toggles bit SW_BUF in the double buffered endpoint register
#define | PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState)
sets the status for tx transfer (bits STAT_TX[1:0]).
#define | PCD_SET_EP_RX_STATUS(USBx, bEpNum, wState)
sets the status for rx transfer (bits STAT_TX[1:0])
#define | PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx)
sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
#define | PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)
gets the status for tx/rx transfer (bits STAT_TX[1:0] /STAT_RX[1:0])
#define | PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)
#define | PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
sets directly the VALID tx/rx-status into the endpoint register
#define | PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
#define | PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum)
checks stall condition in an endpoint.
#define | PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum)
#define | PCD_SET_EP_KIND(USBx, bEpNum)
set & clear EP_KIND bit.
#define | PCD_CLEAR_EP_KIND(USBx, bEpNum)
#define | PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
Sets/clears directly STATUS_OUT bit in the endpoint register.
#define | PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
#define | PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
Sets/clears directly EP_KIND bit in the endpoint register.
#define | PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
#define | PCD_CLEAR_RX_EP_CTR(USBx, bEpNum)
Clears bit CTR_RX / CTR_TX in the endpoint register.
#define | PCD_CLEAR_TX_EP_CTR(USBx, bEpNum)
#define | PCD_RX_DTOG(USBx, bEpNum)
Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
#define | PCD_TX_DTOG(USBx, bEpNum)
#define | PCD_CLEAR_RX_DTOG(USBx, bEpNum)
Clears DTOG_RX / DTOG_TX bit in the endpoint register.
#define | PCD_CLEAR_TX_DTOG(USBx, bEpNum)
#define | PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr)
Sets address in an endpoint register.
#define | PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
Gets address in an endpoint register.
#define | PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
#define | PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
#define | PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr)
sets address of the tx/rx buffer.
#define | PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr)
#define | PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
Gets address of the tx/rx buffer.
#define | PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))
#define | PCD_CALC_BLK32(pdwReg, wCount, wNBlocks)
Sets counter of rx buffer with no.
#define | PCD_CALC_BLK2(pdwReg, wCount, wNBlocks)
#define | PCD_SET_EP_CNT_RX_REG(pdwReg, wCount)
#define | PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount)
#define | PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount)
sets counter for the tx/rx buffer.
#define | PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount)
#define | PCD_GET_EP_TX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU)
gets counter of the tx buffer.
#define | PCD_GET_EP_RX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU)
#define | PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr)
Sets buffer 0/1 address in a double buffer endpoint.
#define | PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr)
#define | PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr)
Sets addresses in a double buffer endpoint.
#define | PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
Gets buffer 0/1 address of a double buffer endpoint.
#define | PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
#define | PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount)
Gets buffer 0/1 address of a double buffer endpoint.
#define | PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount)
#define | PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount)
#define | PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
Gets buffer 0/1 rx/tx counter for double buffering.
#define | PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))

Typedefs

typedef USB_TypeDef | PCD_TypeDef
typedef USB_CfgTypeDef | PCD_InitTypeDef
typedef USB_EPTypeDef | PCD_EPTypeDef
typedef struct __PCD_HandleTypeDef | PCD_HandleTypeDef
PCD Handle Structure definition.
typedef void(* | pPCD_CallbackTypeDef )(PCD_HandleTypeDef *hpcd)
typedef void(* | pPCD_DataOutStageCallbackTypeDef )(PCD_HandleTypeDef *hpcd, uint8_t epnum)
typedef void(* | pPCD_DataInStageCallbackTypeDef )(PCD_HandleTypeDef *hpcd, uint8_t epnum)
typedef void(* | pPCD_IsoOutIncpltCallbackTypeDef )(PCD_HandleTypeDef *hpcd, uint8_t epnum)
typedef void(* | pPCD_IsoInIncpltCallbackTypeDef )(PCD_HandleTypeDef *hpcd, uint8_t epnum)
typedef void(* | pPCD_LpmCallbackTypeDef )(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
typedef void(* | pPCD_BcdCallbackTypeDef )(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)

Enumerations

enum PCD_StateTypeDef {
HAL_PCD_STATE_RESET = 0x00, HAL_PCD_STATE_READY = 0x01, HAL_PCD_STATE_ERROR = 0x02, HAL_PCD_STATE_BUSY = 0x03,
HAL_PCD_STATE_TIMEOUT = 0x04
}
PCD State structure definition. More...
enum | PCD_LPM_StateTypeDef { LPM_L0 = 0x00, LPM_L1 = 0x01, LPM_L2 = 0x02, LPM_L3 = 0x03 }
enum | PCD_LPM_MsgTypeDef { PCD_LPM_L0_ACTIVE = 0x00, PCD_LPM_L1_ACTIVE = 0x01 }
enum PCD_BCD_MsgTypeDef {
PCD_BCD_ERROR = 0xFF, PCD_BCD_CONTACT_DETECTION = 0xFE, PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD, PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC,
PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB, PCD_BCD_DISCOVERY_COMPLETED = 0x00
}
enum HAL_PCD_CallbackIDTypeDef {
HAL_PCD_SOF_CB_ID = 0x01, HAL_PCD_SETUPSTAGE_CB_ID = 0x02, HAL_PCD_RESET_CB_ID = 0x03, HAL_PCD_SUSPEND_CB_ID = 0x04,
HAL_PCD_RESUME_CB_ID = 0x05, HAL_PCD_CONNECT_CB_ID = 0x06, HAL_PCD_DISCONNECT_CB_ID = 0x07, HAL_PCD_MSPINIT_CB_ID = 0x08,
HAL_PCD_MSPDEINIT_CB_ID = 0x09
}

Functions

HAL_StatusTypeDef | HAL_PCD_Init (PCD_HandleTypeDef *hpcd)
Initializes the PCD according to the specified parameters in the PCD_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd)
DeInitializes the PCD peripheral.
__weak void | HAL_PCD_MspInit (PCD_HandleTypeDef *hpcd)
Initializes the PCD MSP.
__weak void | HAL_PCD_MspDeInit (PCD_HandleTypeDef *hpcd)
DeInitializes PCD MSP.
HAL_StatusTypeDef | HAL_PCD_RegisterCallback (PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback)
Register a User USB PCD Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterCallback (PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID)
Unregister an USB PCD Callback USB PCD callabck is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterDataOutStageCallback (PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback)
Register USB PCD Data OUT Stage Callback To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterDataOutStageCallback (PCD_HandleTypeDef *hpcd)
UnRegister the USB PCD Data OUT Stage Callback USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterDataInStageCallback (PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback)
Register USB PCD Data IN Stage Callback To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterDataInStageCallback (PCD_HandleTypeDef *hpcd)
UnRegister the USB PCD Data IN Stage Callback USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterIsoOutIncpltCallback (PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback)
Register USB PCD Iso OUT incomplete Callback To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterIsoOutIncpltCallback (PCD_HandleTypeDef *hpcd)
UnRegister the USB PCD Iso OUT incomplete Callback USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterIsoInIncpltCallback (PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback)
Register USB PCD Iso IN incomplete Callback To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterIsoInIncpltCallback (PCD_HandleTypeDef *hpcd)
UnRegister the USB PCD Iso IN incomplete Callback USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterBcdCallback (PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback)
Register USB PCD BCD Callback To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterBcdCallback (PCD_HandleTypeDef *hpcd)
UnRegister the USB PCD BCD Callback USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterLpmCallback (PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback)
Register USB PCD LPM Callback To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterLpmCallback (PCD_HandleTypeDef *hpcd)
UnRegister the USB PCD LPM Callback USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_Start (PCD_HandleTypeDef *hpcd)
Start the USB device.
HAL_StatusTypeDef | HAL_PCD_Stop (PCD_HandleTypeDef *hpcd)
Stop the USB device.
void | HAL_PCD_IRQHandler (PCD_HandleTypeDef *hpcd)
This function handles PCD interrupt request.
__weak void | HAL_PCD_SOFCallback (PCD_HandleTypeDef *hpcd)
USB Start Of Frame callback.
__weak void | HAL_PCD_SetupStageCallback (PCD_HandleTypeDef *hpcd)
Setup stage callback.
__weak void | HAL_PCD_ResetCallback (PCD_HandleTypeDef *hpcd)
USB Reset callback.
__weak void | HAL_PCD_SuspendCallback (PCD_HandleTypeDef *hpcd)
Suspend event callback.
__weak void | HAL_PCD_ResumeCallback (PCD_HandleTypeDef *hpcd)
Resume event callback.
__weak void | HAL_PCD_ConnectCallback (PCD_HandleTypeDef *hpcd)
Connection event callback.
__weak void | HAL_PCD_DisconnectCallback (PCD_HandleTypeDef *hpcd)
Disconnection event callback.
__weak void | HAL_PCD_DataOutStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data OUT stage callback.
__weak void | HAL_PCD_DataInStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data IN stage callback.
__weak void | HAL_PCD_ISOOUTIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO OUT callback.
__weak void | HAL_PCD_ISOINIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO IN callback.
HAL_StatusTypeDef | HAL_PCD_DevConnect (PCD_HandleTypeDef *hpcd)
Connect the USB device.
HAL_StatusTypeDef | HAL_PCD_DevDisconnect (PCD_HandleTypeDef *hpcd)
Disconnect the USB device.
HAL_StatusTypeDef | HAL_PCD_SetAddress (PCD_HandleTypeDef *hpcd, uint8_t address)
Set the USB Device address.
HAL_StatusTypeDef | HAL_PCD_EP_Open (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
Open and configure an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Close (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Deactivate an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Receive (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Receive an amount of data.
HAL_StatusTypeDef | HAL_PCD_EP_Transmit (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Send an amount of data.
uint32_t | HAL_PCD_EP_GetRxCount (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Get Received Data Size.
HAL_StatusTypeDef | HAL_PCD_EP_SetStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Set a STALL condition over an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_ClrStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Clear a STALL condition over in an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Flush (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Flush an endpoint.
HAL_StatusTypeDef | HAL_PCD_ActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
Activate remote wakeup signalling.
HAL_StatusTypeDef | HAL_PCD_DeActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
De-activate remote wakeup signalling.
PCD_StateTypeDef | HAL_PCD_GetState (PCD_HandleTypeDef *hpcd)
Return the PCD handle state.

Detailed Description

Header file of PCD HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_pcd.h.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_pcd_ex.h File Reference

  • File List
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Functions
stm32wbxx_hal_pcd_ex.h File Reference

Header file of PCD HAL Extension module. More...

#include "stm32wbxx_hal_def.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_PCDEx_PMAConfig (PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pmaadress)
Configure PMA for EP.
HAL_StatusTypeDef | HAL_PCDEx_ActivateLPM (PCD_HandleTypeDef *hpcd)
Activate LPM feature.
HAL_StatusTypeDef | HAL_PCDEx_DeActivateLPM (PCD_HandleTypeDef *hpcd)
Deactivate LPM feature.
HAL_StatusTypeDef | HAL_PCDEx_ActivateBCD (PCD_HandleTypeDef *hpcd)
Activate BatteryCharging feature.
HAL_StatusTypeDef | HAL_PCDEx_DeActivateBCD (PCD_HandleTypeDef *hpcd)
Deactivate BatteryCharging feature.
void | HAL_PCDEx_BCD_VBUSDetect (PCD_HandleTypeDef *hpcd)
Handle BatteryCharging Process.
__weak void | HAL_PCDEx_LPM_Callback (PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
Send LPM message to user layer callback.
__weak void | HAL_PCDEx_BCD_Callback (PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
Send BatteryCharging message to user layer callback.

Detailed Description

Header file of PCD HAL Extension module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_pcd_ex.h.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_pka.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32wbxx_hal_pka.h File Reference

Header file of PKA HAL module. More...

#include "stm32wbxx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | __PKA_HandleTypeDef
struct | PKA_ECCMulFastModeInTypeDef
struct | PKA_ECCMulInTypeDef
struct | PKA_PointCheckInTypeDef
struct | PKA_RSACRTExpInTypeDef
struct | PKA_ECDSAVerifInTypeDef
struct | PKA_ECDSASignInTypeDef
struct | PKA_ECDSASignOutTypeDef
struct | PKA_ECDSASignOutExtParamTypeDef
struct | PKA_ModExpInTypeDef
struct | PKA_ModExpFastModeInTypeDef
struct | PKA_MontgomeryParamInTypeDef
struct | PKA_AddInTypeDef
struct | PKA_ModInvInTypeDef
struct | PKA_ModRedInTypeDef
struct | PKA_ModAddInTypeDef

Defines

#define | HAL_PKA_ERROR_NONE (0x00000000U)
#define | HAL_PKA_ERROR_ADDRERR (0x00000001U)
#define | HAL_PKA_ERROR_RAMERR (0x00000002U)
#define | HAL_PKA_ERROR_TIMEOUT (0x00000004U)
#define | HAL_PKA_ERROR_OPERATION (0x00000008U)
#define | HAL_PKA_ERROR_INVALID_CALLBACK (0x00000010U)
#define | PKA_MODE_MONTGOMERY_PARAM (0x00000001U)
#define | PKA_MODE_MODULAR_EXP (0x00000000U)
#define | PKA_MODE_MODULAR_EXP_FAST_MODE (0x00000002U)
#define | PKA_MODE_ECC_MUL (0x00000020U)
#define | PKA_MODE_ECC_MUL_FAST_MODE (0x00000022U)
#define | PKA_MODE_ECDSA_SIGNATURE (0x00000024U)
#define | PKA_MODE_ECDSA_VERIFICATION (0x00000026U)
#define | PKA_MODE_POINT_CHECK (0x00000028U)
#define | PKA_MODE_RSA_CRT_EXP (0x00000007U)
#define | PKA_MODE_MODULAR_INV (0x00000008U)
#define | PKA_MODE_ARITHMETIC_ADD (0x00000009U)
#define | PKA_MODE_ARITHMETIC_SUB (0x0000000AU)
#define | PKA_MODE_ARITHMETIC_MUL (0x0000000BU)
#define | PKA_MODE_COMPARISON (0x0000000CU)
#define | PKA_MODE_MODULAR_RED (0x0000000DU)
#define | PKA_MODE_MODULAR_ADD (0x0000000EU)
#define | PKA_MODE_MODULAR_SUB (0x0000000FU)
#define | PKA_MODE_MONTGOMERY_MUL (0x00000010U)
#define | PKA_IT_PROCEND PKA_CR_PROCENDIE
#define | PKA_IT_ADDRERR PKA_CR_ADDRERRIE
#define | PKA_IT_RAMERR PKA_CR_RAMERRIE
#define | PKA_FLAG_PROCEND PKA_SR_PROCENDF
#define | PKA_FLAG_ADDRERR PKA_SR_ADDRERRF
#define | PKA_FLAG_RAMERR PKA_SR_RAMERRF
#define | __HAL_PKA_RESET_HANDLE_STATE(__HANDLE__)
Reset PKA handle state.
#define | __HAL_PKA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the specified PKA interrupt.
#define | __HAL_PKA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= (~(__INTERRUPT__)))
Disable the specified PKA interrupt.
#define | __HAL_PKA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified PKA interrupt source is enabled or not.
#define | __HAL_PKA_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
Check whether the specified PKA flag is set or not.
#define | __HAL_PKA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
Clear the PKA pending flags which are cleared by writing 1 in a specific bit.
#define | __HAL_PKA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR, PKA_CR_EN))
Enable the specified PKA peripheral.
#define | __HAL_PKA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR, PKA_CR_EN))
Disable the specified PKA peripheral.
#define | __HAL_PKA_START(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR, PKA_CR_START))
Start a PKA operation.

Typedefs

typedef struct __PKA_HandleTypeDef | PKA_HandleTypeDef
typedef void(* | pPKA_CallbackTypeDef )(PKA_HandleTypeDef *hpka)
typedef struct
PKA_ECDSASignOutExtParamTypeDef 		PKA_ECCMulOutTypeDef
typedef struct PKA_AddInTypeDef | PKA_SubInTypeDef
typedef struct PKA_AddInTypeDef | PKA_MulInTypeDef
typedef struct PKA_AddInTypeDef | PKA_CmpInTypeDef
typedef struct PKA_ModAddInTypeDef | PKA_ModSubInTypeDef
typedef struct PKA_ModAddInTypeDef | PKA_MontgomeryMulInTypeDef

Enumerations

enum | HAL_PKA_StateTypeDef { HAL_PKA_STATE_RESET = 0x00U, HAL_PKA_STATE_READY = 0x01U, HAL_PKA_STATE_BUSY = 0x02U, HAL_PKA_STATE_ERROR = 0x03U }
enum | HAL_PKA_CallbackIDTypeDef { HAL_PKA_OPERATION_COMPLETE_CB_ID = 0x00U, HAL_PKA_ERROR_CB_ID = 0x01U, HAL_PKA_MSPINIT_CB_ID = 0x02U, HAL_PKA_MSPDEINIT_CB_ID = 0x03U }

Functions

HAL_StatusTypeDef | HAL_PKA_Init (PKA_HandleTypeDef *hpka)
Initialize the PKA according to the specified parameters in the PKA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_PKA_DeInit (PKA_HandleTypeDef *hpka)
DeInitialize the PKA peripheral.
__weak void | HAL_PKA_MspInit (PKA_HandleTypeDef *hpka)
Initialize the PKA MSP.
__weak void | HAL_PKA_MspDeInit (PKA_HandleTypeDef *hpka)
DeInitialize the PKA MSP.
HAL_StatusTypeDef | HAL_PKA_RegisterCallback (PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID, pPKA_CallbackTypeDef pCallback)
Register a User PKA Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_PKA_UnRegisterCallback (PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID)
Unregister a PKA Callback PKA callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_PKA_ModExp (PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in, uint32_t Timeout)
Modular exponentiation in blocking mode.
HAL_StatusTypeDef | HAL_PKA_ModExp_IT (PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in)
Modular exponentiation in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_PKA_ModExpFastMode (PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in, uint32_t Timeout)
Modular exponentiation in blocking mode.
HAL_StatusTypeDef | HAL_PKA_ModExpFastMode_IT (PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in)
Modular exponentiation in non-blocking mode with Interrupt.
void | HAL_PKA_ModExp_GetResult (PKA_HandleTypeDef *hpka, uint8_t *pRes)
Retrieve operation result.
HAL_StatusTypeDef | HAL_PKA_ECDSASign (PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in, uint32_t Timeout)
Sign a message using elliptic curves over prime fields in blocking mode.
HAL_StatusTypeDef | HAL_PKA_ECDSASign_IT (PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in)
Sign a message using elliptic curves over prime fields in non-blocking mode with Interrupt.
void | HAL_PKA_ECDSASign_GetResult (PKA_HandleTypeDef *hpka, PKA_ECDSASignOutTypeDef *out, PKA_ECDSASignOutExtParamTypeDef *outExt)
Retrieve operation result.
HAL_StatusTypeDef | HAL_PKA_ECDSAVerif (PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in, uint32_t Timeout)
Verify the validity of a signature using elliptic curves over prime fields in blocking mode.
HAL_StatusTypeDef | HAL_PKA_ECDSAVerif_IT (PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in)
Verify the validity of a signature using elliptic curves over prime fields in non-blocking mode with Interrupt.
uint32_t | HAL_PKA_ECDSAVerif_IsValidSignature (PKA_HandleTypeDef const *const hpka)
Return the result of the ECDSA verification operation.
HAL_StatusTypeDef | HAL_PKA_RSACRTExp (PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in, uint32_t Timeout)
RSA CRT exponentiation in blocking mode.
HAL_StatusTypeDef | HAL_PKA_RSACRTExp_IT (PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in)
RSA CRT exponentiation in non-blocking mode with Interrupt.
void | HAL_PKA_RSACRTExp_GetResult (PKA_HandleTypeDef *hpka, uint8_t *pRes)
Retrieve operation result.
HAL_StatusTypeDef | HAL_PKA_PointCheck (PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in, uint32_t Timeout)
Point on elliptic curve check in blocking mode.
HAL_StatusTypeDef | HAL_PKA_PointCheck_IT (PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in)
Point on elliptic curve check in non-blocking mode with Interrupt.
uint32_t | HAL_PKA_PointCheck_IsOnCurve (PKA_HandleTypeDef const *const hpka)
Return the result of the point check operation.
HAL_StatusTypeDef | HAL_PKA_ECCMul (PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in, uint32_t Timeout)
ECC scalar multiplication in blocking mode.
HAL_StatusTypeDef | HAL_PKA_ECCMul_IT (PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in)
ECC scalar multiplication in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_PKA_ECCMulFastMode (PKA_HandleTypeDef *hpka, PKA_ECCMulFastModeInTypeDef *in, uint32_t Timeout)
ECC scalar multiplication in blocking mode.
HAL_StatusTypeDef | HAL_PKA_ECCMulFastMode_IT (PKA_HandleTypeDef *hpka, PKA_ECCMulFastModeInTypeDef *in)
ECC scalar multiplication in non-blocking mode with Interrupt.
void | HAL_PKA_ECCMul_GetResult (PKA_HandleTypeDef *hpka, PKA_ECCMulOutTypeDef *out)
Retrieve operation result.
HAL_StatusTypeDef | HAL_PKA_Add (PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in, uint32_t Timeout)
Arithmetic addition in blocking mode.
HAL_StatusTypeDef | HAL_PKA_Add_IT (PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in)
Arithmetic addition in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_PKA_Sub (PKA_HandleTypeDef *hpka, PKA_SubInTypeDef *in, uint32_t Timeout)
Arithmetic substraction in blocking mode.
HAL_StatusTypeDef | HAL_PKA_Sub_IT (PKA_HandleTypeDef *hpka, PKA_SubInTypeDef *in)
Arithmetic substraction in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_PKA_Cmp (PKA_HandleTypeDef *hpka, PKA_CmpInTypeDef *in, uint32_t Timeout)
Comparison in blocking mode.
HAL_StatusTypeDef | HAL_PKA_Cmp_IT (PKA_HandleTypeDef *hpka, PKA_CmpInTypeDef *in)
Comparison in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_PKA_Mul (PKA_HandleTypeDef *hpka, PKA_MulInTypeDef *in, uint32_t Timeout)
Arithmetic multiplication in blocking mode.
HAL_StatusTypeDef | HAL_PKA_Mul_IT (PKA_HandleTypeDef *hpka, PKA_MulInTypeDef *in)
Arithmetic multiplication in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_PKA_ModAdd (PKA_HandleTypeDef *hpka, PKA_ModAddInTypeDef *in, uint32_t Timeout)
Modular addition in blocking mode.
HAL_StatusTypeDef | HAL_PKA_ModAdd_IT (PKA_HandleTypeDef *hpka, PKA_ModAddInTypeDef *in)
Modular addition in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_PKA_ModSub (PKA_HandleTypeDef *hpka, PKA_ModSubInTypeDef *in, uint32_t Timeout)
Modular substraction in blocking mode.
HAL_StatusTypeDef | HAL_PKA_ModSub_IT (PKA_HandleTypeDef *hpka, PKA_ModSubInTypeDef *in)
Modular substraction in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_PKA_ModInv (PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in, uint32_t Timeout)
Modular inversion in blocking mode.
HAL_StatusTypeDef | HAL_PKA_ModInv_IT (PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in)
Modular inversion in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_PKA_ModRed (PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in, uint32_t Timeout)
Modular reduction in blocking mode.
HAL_StatusTypeDef | HAL_PKA_ModRed_IT (PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in)
Modular reduction in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_PKA_MontgomeryMul (PKA_HandleTypeDef *hpka, PKA_MontgomeryMulInTypeDef *in, uint32_t Timeout)
Montgomery multiplication in blocking mode.
HAL_StatusTypeDef | HAL_PKA_MontgomeryMul_IT (PKA_HandleTypeDef *hpka, PKA_MontgomeryMulInTypeDef *in)
Montgomery multiplication in non-blocking mode with Interrupt.
void | HAL_PKA_Arithmetic_GetResult (PKA_HandleTypeDef *hpka, uint32_t *pRes)
Retrieve operation result.
HAL_StatusTypeDef | HAL_PKA_MontgomeryParam (PKA_HandleTypeDef *hpka, PKA_MontgomeryParamInTypeDef *in, uint32_t Timeout)
Montgomery parameter computation in blocking mode.
HAL_StatusTypeDef | HAL_PKA_MontgomeryParam_IT (PKA_HandleTypeDef *hpka, PKA_MontgomeryParamInTypeDef *in)
Montgomery parameter computation in non-blocking mode with Interrupt.
void | HAL_PKA_MontgomeryParam_GetResult (PKA_HandleTypeDef *hpka, uint32_t *pRes)
Retrieve operation result.
HAL_StatusTypeDef | HAL_PKA_Abort (PKA_HandleTypeDef *hpka)
Abort any ongoing operation.
void | HAL_PKA_RAMReset (PKA_HandleTypeDef *hpka)
Reset the PKA RAM.
__weak void | HAL_PKA_OperationCpltCallback (PKA_HandleTypeDef *hpka)
Process completed callback.
__weak void | HAL_PKA_ErrorCallback (PKA_HandleTypeDef *hpka)
Error callback.
void | HAL_PKA_IRQHandler (PKA_HandleTypeDef *hpka)
This function handles PKA event interrupt request.
HAL_PKA_StateTypeDef | HAL_PKA_GetState (PKA_HandleTypeDef *hpka)
Return the PKA handle state.
uint32_t | HAL_PKA_GetError (PKA_HandleTypeDef *hpka)
Return the PKA error code.

Detailed Description

Header file of PKA HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_pka.h.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_pwr.h File Reference

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stm32wbxx_hal_pwr.h File Reference

Header file of PWR HAL module. More...

#include "stm32wbxx_hal_def.h"
#include "stm32wbxx_ll_pwr.h"
#include "stm32wbxx_ll_exti.h"
#include "stm32wbxx_hal_pwr_ex.h"

Go to the source code of this file.

Data Structures

struct | PWR_PVDTypeDef
PWR PVD configuration structure definition. More...

Defines

#define | PWR_PVDLEVEL_0 (0x00000000U)
#define | PWR_PVDLEVEL_1 ( PWR_CR2_PLS_0)
#define | PWR_PVDLEVEL_2 ( PWR_CR2_PLS_1 )
#define | PWR_PVDLEVEL_3 ( PWR_CR2_PLS_1 | PWR_CR2_PLS_0)
#define | PWR_PVDLEVEL_4 (PWR_CR2_PLS_2 )
#define | PWR_PVDLEVEL_5 (PWR_CR2_PLS_2 | PWR_CR2_PLS_0)
#define | PWR_PVDLEVEL_6 (PWR_CR2_PLS_2 | PWR_CR2_PLS_1 )
#define | PWR_PVDLEVEL_7 (PWR_CR2_PLS_2 | PWR_CR2_PLS_1 | PWR_CR2_PLS_0)
#define | PWR_PVD_MODE_NORMAL (0x00000000U)
#define | PWR_PVD_MODE_IT_RISING (PVD_MODE_IT | PVD_RISING_EDGE)
#define | PWR_PVD_MODE_IT_FALLING (PVD_MODE_IT | PVD_FALLING_EDGE)
#define | PWR_PVD_MODE_IT_RISING_FALLING (PVD_MODE_IT | PVD_RISING_FALLING_EDGE)
#define | PWR_LOWPOWERMODE_STOP0 (0x00000000u)
#define | PWR_LOWPOWERMODE_STOP1 (PWR_CR1_LPMS_0)
#define | PWR_LOWPOWERMODE_STOP2 (PWR_CR1_LPMS_1)
#define | PWR_LOWPOWERMODE_STANDBY (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1)
#define | PWR_LOWPOWERMODE_SHUTDOWN (PWR_CR1_LPMS_2)
#define | PWR_MAINREGULATOR_ON (0x00000000U)
#define | PWR_LOWPOWERREGULATOR_ON (PWR_CR1_LPR)
#define | PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
#define | PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
#define | PWR_STOPENTRY_WFI ((uint8_t)0x01)
#define | PWR_STOPENTRY_WFE ((uint8_t)0x02)
#define | PWR_EXTI_LINE_PVD (LL_EXTI_LINE_16)
#define | PVD_MODE_IT (0x00010000U)
#define | PVD_RISING_EDGE (0x00000001U)
#define | PVD_FALLING_EDGE (0x00000002U)
#define | PVD_RISING_FALLING_EDGE (0x00000003U)
#define | __HAL_PWR_GET_FLAG(__FLAG__)
Check whether or not a specific PWR flag is set.
#define | __HAL_PWR_CLEAR_FLAG(__FLAG__)
Clear a specific PWR flag.
#define | __HAL_PWR_PVD_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(PWR_EXTI_LINE_PVD)
Enable the PVD Extended Interrupt C1 Line.
#define | __HAL_PWR_PVD_EXTIC2_ENABLE_IT() LL_C2_EXTI_EnableIT_0_31(PWR_EXTI_LINE_PVD)
Enable the PVD Extended Interrupt C2 Line.
#define | __HAL_PWR_PVD_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt C1 Line.
#define | __HAL_PWR_PVD_EXTIC2_DISABLE_IT() LL_C2_EXTI_DisableIT_0_31(PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt C2 Line.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(PWR_EXTI_LINE_PVD)
Enable the PVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableFallingTrig_0_31(PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(PWR_EXTI_LINE_PVD)
Enable the PVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableRisingTrig_0_31(PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the PVD Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the PVD Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(PWR_EXTI_LINE_PVD)
Generate a Software interrupt on selected EXTI line.
#define | __HAL_PWR_PVD_EXTI_GET_FLAG() LL_EXTI_ReadFlag_0_31(PWR_EXTI_LINE_PVD)
Check whether or not the PVD EXTI interrupt flag is set.
#define | __HAL_PWR_PVD_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(PWR_EXTI_LINE_PVD)
Clear the PVD EXTI interrupt flag.
#define | IS_PWR_PVD_LEVEL(LEVEL)
#define | IS_PWR_PVD_MODE(MODE)
#define | IS_PWR_REGULATOR(REGULATOR)
#define | IS_PWR_SLEEP_ENTRY(ENTRY)
#define | IS_PWR_STOP_ENTRY(ENTRY)

Functions

void | HAL_PWR_DeInit (void)
Deinitialize the HAL PWR peripheral registers to their default reset values.
void | HAL_PWR_EnableBkUpAccess (void)
Enable access to the backup domain (RTC registers, RTC backup data registers).
void | HAL_PWR_DisableBkUpAccess (void)
Disable access to the backup domain (RTC registers, RTC backup data registers).
HAL_StatusTypeDef | HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
Configure the voltage threshold detected by the Power Voltage Detector (PVD).
void | HAL_PWR_EnablePVD (void)
Enables the Power Voltage Detector(PVD).
void | HAL_PWR_DisablePVD (void)
Disables the Power Voltage Detector(PVD).
void | HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity)
Enable the WakeUp PINx functionality.
void | HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
Disable the WakeUp PINx functionality.
void | HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
Enter Stop mode.
void | HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
Enter Sleep or Low-power Sleep mode.
void | HAL_PWR_EnterSTANDBYMode (void)
Enter Standby mode.
__weak void | HAL_PWR_PVDCallback (void)
PWR PVD interrupt callback.
void | HAL_PWR_EnableSleepOnExit (void)
Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.
void | HAL_PWR_DisableSleepOnExit (void)
Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
void | HAL_PWR_EnableSEVOnPend (void)
Enable CORTEX M4 SEVONPEND bit.
void | HAL_PWR_DisableSEVOnPend (void)
Disable CORTEX M4 SEVONPEND bit.

Detailed Description

Header file of PWR HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

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Definition in file stm32wbxx_hal_pwr.h.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_pwr_ex.h File Reference

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Data Structures | Defines | Functions
stm32wbxx_hal_pwr_ex.h File Reference

Header file of PWR HAL Extended module. More...

#include "stm32wbxx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | PWR_PVMTypeDef
PWR PVM configuration structure definition. More...
struct | PWR_SMPSTypeDef
PWR SMPS step down configuration structure definition. More...

Defines

#define | PWR_WUP_POLARITY_SHIFT 0x05U
#define | PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1
#define | PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2
#define | PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3
#define | PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4
#define | PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5
#define | PWR_WAKEUP_PIN1_LOW ((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1)
#define | PWR_WAKEUP_PIN2_LOW ((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2)
#define | PWR_WAKEUP_PIN3_LOW ((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3)
#define | PWR_WAKEUP_PIN4_LOW ((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4)
#define | PWR_WAKEUP_PIN5_LOW ((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5)
#define | PWR_WAKEUP_PIN1 PWR_CR3_EWUP1
#define | PWR_WAKEUP_PIN2 PWR_CR3_EWUP2
#define | PWR_WAKEUP_PIN3 PWR_CR3_EWUP3
#define | PWR_WAKEUP_PIN4 PWR_CR3_EWUP4
#define | PWR_WAKEUP_PIN5 PWR_CR3_EWUP5
#define | PWR_PIN_POLARITY_HIGH 0x00000000U
#define | PWR_PIN_POLARITY_LOW 0x00000001U
#define | PWR_PVM_1 PWR_CR2_PVME1
#define | PWR_PVM_3 PWR_CR2_PVME3
#define | PWR_PVM_MODE_NORMAL (0x00000000U)
#define | PWR_PVM_MODE_IT_RISING (PVM_MODE_IT | PVM_RISING_EDGE)
#define | PWR_PVM_MODE_IT_FALLING (PVM_MODE_IT | PVM_FALLING_EDGE)
#define | PWR_PVM_MODE_IT_RISING_FALLING (PVM_MODE_IT | PVM_RISING_FALLING_EDGE)
#define | PWR_PVM_MODE_EVENT_RISING (PVM_MODE_EVT | PVM_RISING_EDGE)
#define | PWR_PVM_MODE_EVENT_FALLING (PVM_MODE_EVT | PVM_FALLING_EDGE)
#define | PWR_PVM_MODE_EVENT_RISING_FALLING (PVM_MODE_EVT | PVM_RISING_FALLING_EDGE)
#define | PWR_FLASHPD_LPRUN PWR_CR1_FPDR
#define | PWR_FLASHPD_LPSLEEP PWR_CR1_FPDS
#define | PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0
#define | PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1
#define | PWR_BATTERY_CHARGING_RESISTOR_5 (0x00000000U)
#define | PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS
#define | PWR_BATTERY_CHARGING_DISABLE (0x00000000U)
#define | PWR_BATTERY_CHARGING_ENABLE PWR_CR4_VBE
#define | PWR_GPIO_BIT_0 PWR_PUCRA_PA0
#define | PWR_GPIO_BIT_1 PWR_PUCRA_PA1
#define | PWR_GPIO_BIT_2 PWR_PUCRA_PA2
#define | PWR_GPIO_BIT_3 PWR_PUCRA_PA3
#define | PWR_GPIO_BIT_4 PWR_PUCRA_PA4
#define | PWR_GPIO_BIT_5 PWR_PUCRA_PA5
#define | PWR_GPIO_BIT_6 PWR_PUCRA_PA6
#define | PWR_GPIO_BIT_7 PWR_PUCRA_PA7
#define | PWR_GPIO_BIT_8 PWR_PUCRA_PA8
#define | PWR_GPIO_BIT_9 PWR_PUCRA_PA9
#define | PWR_GPIO_BIT_10 PWR_PUCRA_PA10
#define | PWR_GPIO_BIT_11 PWR_PUCRA_PA11
#define | PWR_GPIO_BIT_12 PWR_PUCRA_PA12
#define | PWR_GPIO_BIT_13 PWR_PUCRA_PA13
#define | PWR_GPIO_BIT_14 PWR_PDCRC_PC14
#define | PWR_GPIO_BIT_15 PWR_PUCRC_PC15
#define | PWR_GPIO_A 0x00000000U
#define | PWR_GPIO_B 0x00000001U
#define | PWR_GPIO_C 0x00000002U
#define | PWR_GPIO_D 0x00000003U
#define | PWR_GPIO_E 0x00000004U
#define | PWR_GPIO_H 0x00000007U
#define | PWR_BOR_SYSTEM_RESET (LL_PWR_BOR_SYSTEM_RESET)
#define | PWR_BOR_SMPS_FORCE_BYPASS (LL_PWR_BOR_SMPS_FORCE_BYPASS)
#define | PWR_SMPS_BYPASS (PWR_SR2_SMPSBF)
#define | PWR_SMPS_STEP_DOWN (PWR_SR2_SMPSF)
#define | PWR_SMPS_STARTUP_CURRENT_80MA (0x00000000U)
#define | PWR_SMPS_STARTUP_CURRENT_100MA ( PWR_CR5_SMPSSC_0)
#define | PWR_SMPS_STARTUP_CURRENT_120MA ( PWR_CR5_SMPSSC_1 )
#define | PWR_SMPS_STARTUP_CURRENT_140MA ( PWR_CR5_SMPSSC_1 | PWR_CR5_SMPSSC_0)
#define | PWR_SMPS_STARTUP_CURRENT_160MA (PWR_CR5_SMPSSC_2 )
#define | PWR_SMPS_STARTUP_CURRENT_180MA (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_0)
#define | PWR_SMPS_STARTUP_CURRENT_200MA (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_1 )
#define | PWR_SMPS_STARTUP_CURRENT_220MA (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_1 | PWR_CR5_SMPSSC_0)
#define | PWR_SMPS_OUTPUT_VOLTAGE_1V20 (0x00000000U)
#define | PWR_SMPS_OUTPUT_VOLTAGE_1V25 ( PWR_CR5_SMPSVOS_0)
#define | PWR_SMPS_OUTPUT_VOLTAGE_1V30 ( PWR_CR5_SMPSVOS_1 )
#define | PWR_SMPS_OUTPUT_VOLTAGE_1V35 ( PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0)
#define | PWR_SMPS_OUTPUT_VOLTAGE_1V40 ( PWR_CR5_SMPSVOS_2 )
#define | PWR_SMPS_OUTPUT_VOLTAGE_1V45 ( PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_0)
#define | PWR_SMPS_OUTPUT_VOLTAGE_1V50 ( PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1 )
#define | PWR_SMPS_OUTPUT_VOLTAGE_1V55 ( PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0)
#define | PWR_SMPS_OUTPUT_VOLTAGE_1V60 (PWR_CR5_SMPSVOS_3 )
#define | PWR_SMPS_OUTPUT_VOLTAGE_1V65 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_0)
#define | PWR_SMPS_OUTPUT_VOLTAGE_1V70 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_1 )
#define | PWR_SMPS_OUTPUT_VOLTAGE_1V75 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0)
#define | PWR_SMPS_OUTPUT_VOLTAGE_1V80 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 )
#define | PWR_SMPS_OUTPUT_VOLTAGE_1V85 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_0)
#define | PWR_SMPS_OUTPUT_VOLTAGE_1V90 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1 )
#define | PWR_FLAG_WUF1 (0x0020U)
#define | PWR_FLAG_WUF2 (0x0021U)
#define | PWR_FLAG_WUF3 (0x0022U)
#define | PWR_FLAG_WUF4 (0x0023U)
#define | PWR_FLAG_WUF5 (0x0024U)
#define | PWR_FLAG_WU PWR_SR1_WUF
#define | PWR_FLAG_FRCBYPI (0x0027U)
#define | PWR_FLAG_BHWF (0x0029U)
#define | PWR_FLAG_RFPHASEI (0x002BU)
#define | PWR_FLAG_BLEACTI (0x002CU)
#define | PWR_FLAG_802ACTI (0x002DU)
#define | PWR_FLAG_HOLDC2I (0x002EU)
#define | PWR_FLAG_WUFI (0x002FU)
#define | PWR_FLAG_SMPSRDYF (0x0040U)
#define | PWR_FLAG_SMPSBYPF (0x0041U)
#define | PWR_FLAG_REGLPS (0x0048U)
#define | PWR_FLAG_REGLPF (0x0049U)
#define | PWR_FLAG_VOSF (0x004AU)
#define | PWR_FLAG_PVDO (0x004BU)
#define | PWR_FLAG_PVMO1 (0x004CU)
#define | PWR_FLAG_PVMO3 (0x004EU)
#define | PWR_FLAG_SB (0x0068U)
#define | PWR_FLAG_STOP (0x0069U)
#define | PWR_FLAG_C2SB (0x006AU)
#define | PWR_FLAG_C2STOP (0x006BU)
#define | PWR_FLAG_CRITICAL_RF_PHASE (0x006DU)
#define | PWR_FLAG_C1DEEPSLEEP (0x006EU)
#define | PWR_FLAG_C2DEEPSLEEP (0x006FU)
#define | PWR_WAKEUPTARGET_CPU1 (0x00000001U)
#define | PWR_WAKEUPTARGET_CPU2 (0x00000002U)
#define | PWR_WAKEUPTARGET_ALL_CPU (PWR_WAKEUPTARGET_CPU1 | PWR_WAKEUPTARGET_CPU2)
#define | PWR_WAKEUPTARGET_RF (0x00000004U)
#define | PWR_CORE_CPU1 (0x00000000U)
#define | PWR_CORE_CPU2 (0x00000001U)
#define | PWR_EXTI_LINE_PVM1 (LL_EXTI_LINE_31)
#define | PWR_EXTI_LINE_PVM3 (LL_EXTI_LINE_33)
#define | PVM_MODE_IT (0x00010000U)
#define | PVM_MODE_EVT (0x00020000U)
#define | PVM_RISING_EDGE (0x00000001U)
#define | PVM_FALLING_EDGE (0x00000002U)
#define | PVM_RISING_FALLING_EDGE (0x00000003U)
#define | __HAL_PWR_PVM1_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(PWR_EXTI_LINE_PVM1)
Enable the PVM1 Extended Interrupt C1 Line.
#define | __HAL_PWR_PVM1_EXTIC2_ENABLE_IT() LL_C2_EXTI_EnableIT_0_31(PWR_EXTI_LINE_PVM1)
Enable the PVM1 Extended Interrupt C2 Line.
#define | __HAL_PWR_PVM1_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(PWR_EXTI_LINE_PVM1)
Disable the PVM1 Extended Interrupt C1 Line.
#define | __HAL_PWR_PVM1_EXTIC2_DISABLE_IT() LL_C2_EXTI_DisableIT_0_31(PWR_EXTI_LINE_PVM1)
Disable the PVM1 Extended Interrupt C2 Line.
#define | __HAL_PWR_PVM1_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(PWR_EXTI_LINE_PVM1)
Enable the PVM1 Event C1 Line.
#define | __HAL_PWR_PVM1_EXTIC2_ENABLE_EVENT() LL_C2_EXTI_EnableEvent_0_31(PWR_EXTI_LINE_PVM1)
Enable the PVM1 Event C2 Line.
#define | __HAL_PWR_PVM1_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(PWR_EXTI_LINE_PVM1)
Disable the PVM1 Event C1 Line.
#define | __HAL_PWR_PVM1_EXTIC2_DISABLE_EVENT() LL_C2_EXTI_DisableEvent_0_31(PWR_EXTI_LINE_PVM1)
Disable the PVM1 Event C2 Line.
#define | __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(PWR_EXTI_LINE_PVM1)
Enable the PVM1 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(PWR_EXTI_LINE_PVM1)
Disable the PVM1 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(PWR_EXTI_LINE_PVM1)
Enable the PVM1 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(PWR_EXTI_LINE_PVM1)
Disable the PVM1 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE()
PVM1 EXTI line configuration: set rising & falling edge trigger.
#define | __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the PVM1 Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(PWR_EXTI_LINE_PVM1)
Generate a Software interrupt on selected EXTI line.
#define | __HAL_PWR_PVM1_EXTI_GET_FLAG() LL_EXTI_ReadFlag_0_31(PWR_EXTI_LINE_PVM1)
Check whether the specified PVM1 EXTI interrupt flag is set or not.
#define | __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(PWR_EXTI_LINE_PVM1)
Clear the PVM1 EXTI flag.
#define | __HAL_PWR_PVM3_EXTI_ENABLE_IT() LL_EXTI_EnableIT_32_63(PWR_EXTI_LINE_PVM3)
Enable the PVM3 Extended Interrupt C1 Line.
#define | __HAL_PWR_PVM3_EXTIC2_ENABLE_IT() LL_C2_EXTI_EnableIT_32_63(PWR_EXTI_LINE_PVM3)
Enable the PVM3 Extended Interrupt C2 Line.
#define | __HAL_PWR_PVM3_EXTI_DISABLE_IT() LL_EXTI_DisableIT_32_63(PWR_EXTI_LINE_PVM3)
Disable the PVM3 Extended Interrupt C1 Line.
#define | __HAL_PWR_PVM3_EXTIC2_DISABLE_IT() LL_C2_EXTI_DisableIT_32_63(PWR_EXTI_LINE_PVM3)
Disable the PVM3 Extended Interrupt C2 Line.
#define | __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_32_63(PWR_EXTI_LINE_PVM3)
Enable the PVM3 Event C1 Line.
#define | __HAL_PWR_PVM3_EXTIC2_ENABLE_EVENT() LL_C2_EXTI_EnableEvent_32_63(PWR_EXTI_LINE_PVM3)
Enable the PVM3 Event C2 Line.
#define | __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_32_63(PWR_EXTI_LINE_PVM3)
Disable the PVM3 Event C1 Line.
#define | __HAL_PWR_PVM3_EXTIC2_DISABLE_EVENT() LL_C2_EXTI_DisableEvent_32_63(PWR_EXTI_LINE_PVM3)
Disable the PVM3 Event C2 Line.
#define | __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_32_63(PWR_EXTI_LINE_PVM3)
Enable the PVM3 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_32_63(PWR_EXTI_LINE_PVM3)
Disable the PVM3 Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_32_63(PWR_EXTI_LINE_PVM3)
Enable the PVM3 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_32_63(PWR_EXTI_LINE_PVM3)
Disable the PVM3 Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE()
PVM3 EXTI line configuration: set rising & falling edge trigger.
#define | __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the PVM3 Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_32_63(PWR_EXTI_LINE_PVM3)
Generate a Software interrupt on selected EXTI line.
#define | __HAL_PWR_PVM3_EXTI_GET_FLAG() LL_EXTI_ReadFlag_32_63(PWR_EXTI_LINE_PVM3)
Check whether the specified PVM3 EXTI interrupt flag is set or not.
#define | __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_32_63(PWR_EXTI_LINE_PVM3)
Clear the PVM3 EXTI flag.
#define | __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__)
Configure the main internal regulator output voltage.
#define | __HAL_C2_PWR_WAKEUP_BLE() LL_C2_PWR_WakeUp_BLE()
Wakeup BLE controller from its sleep mode.
#define | __HAL_C2_PWR_WAKEUP_802_15_4() LL_C2_PWR_WakeUp_802_15_4()
Wakeup 802.15.4 controller from its sleep mode.
#define | IS_PWR_WAKEUP_PIN(PIN)
#define | IS_PWR_WAKEUP_PIN_POLARITY(POLARITY)
#define | IS_PWR_PVM_TYPE(TYPE)
#define | IS_PWR_PVM_MODE(MODE)
#define | IS_PWR_FLASH_POWERDOWN(__MODE__)
#define | IS_PWR_VOLTAGE_SCALING_RANGE(RANGE)
#define | IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR)
#define | IS_PWR_BATTERY_CHARGING(CHARGING)
#define | IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00)
#define | IS_PWR_GPIO(GPIO)
#define | IS_PWR_SMPS_MODE(SMPS_MODE)
#define | IS_PWR_SMPS_STARTUP_CURRENT(SMPS_STARTUP_CURRENT)
#define | IS_PWR_SMPS_OUTPUT_VOLTAGE(SMPS_OUTPUT_VOLTAGE)
#define | IS_PWR_CORE(CPU) (((CPU) == PWR_CORE_CPU1) || ((CPU) == PWR_CORE_CPU2))
#define | IS_PWR_CORE_HOLD_RELEASE(CPU) ((CPU) == PWR_CORE_CPU2)

Functions

uint32_t | HAL_PWREx_GetVoltageRange (void)
Return Voltage Scaling Range.
HAL_StatusTypeDef | HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling)
Configure the main internal regulator output voltage.
void | HAL_PWREx_EnableBatteryCharging (uint32_t ResistorSelection)
Enable battery charging.
void | HAL_PWREx_DisableBatteryCharging (void)
Disable battery charging.
void | HAL_PWREx_EnableVddUSB (void)
Enable VDDUSB supply.
void | HAL_PWREx_DisableVddUSB (void)
Disable VDDUSB supply.
void | HAL_PWREx_EnableInternalWakeUpLine (void)
Enable Internal Wake-up Line.
void | HAL_PWREx_DisableInternalWakeUpLine (void)
Disable Internal Wake-up Line.
void | HAL_PWREx_EnableBORH_SMPSBypassIT (void)
Enable BORH and SMPS step down converter forced in bypass mode interrupt for CPU1.
void | HAL_PWREx_DisableBORH_SMPSBypassIT (void)
Disable BORH and SMPS step down converter forced in bypass mode interrupt for CPU1.
void | HAL_PWREx_EnableRFPhaseIT (void)
Enable RF Phase interrupt.
void | HAL_PWREx_DisableRFPhaseIT (void)
Disable RF Phase interrupt.
void | HAL_PWREx_EnableBLEActivityIT (void)
Enable BLE Activity interrupt.
void | HAL_PWREx_DisableBLEActivityIT (void)
Disable BLE Activity interrupt.
void | HAL_PWREx_Enable802ActivityIT (void)
Enable 802.15.4 Activity interrupt.
void | HAL_PWREx_Disable802ActivityIT (void)
Disable 802.15.4 Activity interrupt.
void | HAL_PWREx_EnableHOLDC2IT (void)
Enable CPU2 on-Hold interrupt.
void | HAL_PWREx_DisableHOLDC2IT (void)
Disable CPU2 on-Hold interrupt.
void | HAL_PWREx_HoldCore (uint32_t CPU)
Hold the CPU and their allocated peripherals after reset or wakeup from stop or standby.
void | HAL_PWREx_ReleaseCore (uint32_t CPU)
Release Cortex CPU2 and allocated peripherals after reset or wakeup from stop or standby.
HAL_StatusTypeDef | HAL_PWREx_EnableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-up state in Standby and Shutdown modes.
HAL_StatusTypeDef | HAL_PWREx_DisableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-up state in Standby mode and Shutdown modes.
HAL_StatusTypeDef | HAL_PWREx_EnableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-down state in Standby and Shutdown modes.
HAL_StatusTypeDef | HAL_PWREx_DisableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-down state in Standby and Shutdown modes.
void | HAL_PWREx_EnablePullUpPullDownConfig (void)
Enable pull-up and pull-down configuration.
void | HAL_PWREx_DisablePullUpPullDownConfig (void)
Disable pull-up and pull-down configuration.
void | HAL_PWREx_SetBORConfig (uint32_t BORConfiguration)
Set BOR configuration.
uint32_t | HAL_PWREx_GetBORConfig (void)
Get BOR configuration.
void | HAL_PWREx_EnableSRAMRetention (void)
Enable BKRAM content retention in Standby mode.
void | HAL_PWREx_DisableSRAMRetention (void)
Disable BKRAM content retention in Standby mode.
void | HAL_PWREx_EnableFlashPowerDown (uint32_t PowerMode)
Enable Flash Power Down.
void | HAL_PWREx_DisableFlashPowerDown (uint32_t PowerMode)
Disable Flash Power Down.
void | HAL_PWREx_EnablePVM1 (void)
Enable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
void | HAL_PWREx_DisablePVM1 (void)
Disable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
void | HAL_PWREx_EnablePVM3 (void)
Enable the Power Voltage Monitoring 3: VDDA versus 1.62V.
void | HAL_PWREx_DisablePVM3 (void)
Disable the Power Voltage Monitoring 3: VDDA versus 1.62V.
HAL_StatusTypeDef | HAL_PWREx_ConfigPVM (PWR_PVMTypeDef *sConfigPVM)
Configure the Peripheral Voltage Monitoring (PVM).
HAL_StatusTypeDef | HAL_PWREx_ConfigSMPS (PWR_SMPSTypeDef *sConfigSMPS)
Configure the SMPS step down converter.
void | HAL_PWREx_SMPS_SetMode (uint32_t OperatingMode)
Set SMPS operating mode.
uint32_t | HAL_PWREx_SMPS_GetEffectiveMode (void)
Get SMPS effective operating mode.
void | HAL_PWREx_EnableWakeUpPin (uint32_t WakeUpPinPolarity, uint32_t wakeupTarget)
Enable the WakeUp PINx functionality.
uint32_t | HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag)
Get the Wake-Up pin flag.
HAL_StatusTypeDef | HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag)
Clear the Wake-Up pin flag.
void | HAL_PWREx_EnableLowPowerRunMode (void)
Enter Low-power Run mode.
HAL_StatusTypeDef | HAL_PWREx_DisableLowPowerRunMode (void)
Exit Low-power Run mode.
void | HAL_PWREx_EnterSTOP0Mode (uint8_t STOPEntry)
Enter Stop 0 mode.
void | HAL_PWREx_EnterSTOP1Mode (uint8_t STOPEntry)
Enter Stop 1 mode.
void | HAL_PWREx_EnterSTOP2Mode (uint8_t STOPEntry)
Enter Stop 2 mode.
void | HAL_PWREx_EnterSHUTDOWNMode (void)
Enter Shutdown mode.
void | HAL_PWREx_PVD_PVM_IRQHandler (void)
This function handles the PWR PVD/PVMx interrupt request.
__weak void | HAL_PWREx_PVM1Callback (void)
PWR PVM1 interrupt callback.
__weak void | HAL_PWREx_PVM3Callback (void)
PWR PVM3 interrupt callback.

Detailed Description

Header file of PWR HAL Extended module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_pwr_ex.h.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_qspi.h File Reference

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stm32wbxx_hal_qspi.h File Reference

Header file of QSPI HAL module. More...

#include "stm32wbxx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | QSPI_InitTypeDef
QSPI Init structure definition. More...
struct | __QSPI_HandleTypeDef
QSPI Handle Structure definition. More...
struct | QSPI_CommandTypeDef
QSPI Command structure definition. More...
struct | QSPI_AutoPollingTypeDef
QSPI Auto Polling mode configuration structure definition. More...
struct | QSPI_MemoryMappedTypeDef
QSPI Memory Mapped mode configuration structure definition. More...

Defines

#define | HAL_QSPI_ERROR_NONE 0x00000000U
#define | HAL_QSPI_ERROR_TIMEOUT 0x00000001U
#define | HAL_QSPI_ERROR_TRANSFER 0x00000002U
#define | HAL_QSPI_ERROR_DMA 0x00000004U
#define | HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U
#define | HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U
#define | QSPI_SAMPLE_SHIFTING_NONE 0x00000000U
#define | QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT)
#define | QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U
#define | QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0)
#define | QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1)
#define | QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1)
#define | QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2)
#define | QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0)
#define | QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1)
#define | QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT)
#define | QSPI_CLOCK_MODE_0 0x00000000U
#define | QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE)
#define | QSPI_ADDRESS_8_BITS 0x00000000U
#define | QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0)
#define | QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1)
#define | QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE)
#define | QSPI_ALTERNATE_BYTES_8_BITS 0x00000000U
#define | QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0)
#define | QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1)
#define | QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE)
#define | QSPI_INSTRUCTION_NONE 0x00000000U
#define | QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0)
#define | QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1)
#define | QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE)
#define | QSPI_ADDRESS_NONE 0x00000000U
#define | QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0)
#define | QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1)
#define | QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE)
#define | QSPI_ALTERNATE_BYTES_NONE 0x00000000U
#define | QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0)
#define | QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1)
#define | QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE)
#define | QSPI_DATA_NONE 0x00000000U
#define | QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0)
#define | QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1)
#define | QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE)
#define | QSPI_DDR_MODE_DISABLE 0x00000000U
#define | QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM)
#define | QSPI_SIOO_INST_EVERY_CMD 0x00000000U
#define | QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO)
#define | QSPI_MATCH_MODE_AND 0x00000000U
#define | QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM)
#define | QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U
#define | QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS)
#define | QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U
#define | QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN)
#define | QSPI_FLAG_BUSY QUADSPI_SR_BUSY
#define | QSPI_FLAG_TO QUADSPI_SR_TOF
#define | QSPI_FLAG_SM QUADSPI_SR_SMF
#define | QSPI_FLAG_FT QUADSPI_SR_FTF
#define | QSPI_FLAG_TC QUADSPI_SR_TCF
#define | QSPI_FLAG_TE QUADSPI_SR_TEF
#define | QSPI_IT_TO QUADSPI_CR_TOIE
#define | QSPI_IT_SM QUADSPI_CR_SMIE
#define | QSPI_IT_FT QUADSPI_CR_FTIE
#define | QSPI_IT_TC QUADSPI_CR_TCIE
#define | QSPI_IT_TE QUADSPI_CR_TEIE
#define | HAL_QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */
#define | __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__)
Reset QSPI handle state.
#define | __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
Enable the QSPI peripheral.
#define | __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
Disable the QSPI peripheral.
#define | __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
Enable the specified QSPI interrupt.
#define | __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
Disable the specified QSPI interrupt.
#define | __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the specified QSPI interrupt source is enabled or not.
#define | __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)
Check whether the selected QSPI flag is set or not.
#define | __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
Clears the specified QSPI's flag status.
#define | IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU)
#define | IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 16U))
#define | IS_QSPI_SSHIFT(SSHIFT)
#define | IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U))
#define | IS_QSPI_CS_HIGH_TIME(CSHTIME)
#define | IS_QSPI_CLOCK_MODE(CLKMODE)
#define | IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU)
#define | IS_QSPI_ADDRESS_SIZE(ADDR_SIZE)
#define | IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE)
#define | IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U)
#define | IS_QSPI_INSTRUCTION_MODE(MODE)
#define | IS_QSPI_ADDRESS_MODE(MODE)
#define | IS_QSPI_ALTERNATE_BYTES_MODE(MODE)
#define | IS_QSPI_DATA_MODE(MODE)
#define | IS_QSPI_DDR_MODE(DDR_MODE)
#define | IS_QSPI_SIOO_MODE(SIOO_MODE)
#define | IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
#define | IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U))
#define | IS_QSPI_MATCH_MODE(MODE)
#define | IS_QSPI_AUTOMATIC_STOP(APMS)
#define | IS_QSPI_TIMEOUT_ACTIVATION(TCEN)
#define | IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU)

Typedefs

typedef struct __QSPI_HandleTypeDef | QSPI_HandleTypeDef
QSPI Handle Structure definition.
typedef void(* | pQSPI_CallbackTypeDef )(QSPI_HandleTypeDef *hqspi)
HAL QSPI Callback pointer definition.

Enumerations

enum HAL_QSPI_StateTypeDef {
HAL_QSPI_STATE_RESET = 0x00U, HAL_QSPI_STATE_READY = 0x01U, HAL_QSPI_STATE_BUSY = 0x02U, HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U,
HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, HAL_QSPI_STATE_ABORT = 0x08U,
HAL_QSPI_STATE_ERROR = 0x04U
}
HAL QSPI State structures definition. More...
enum HAL_QSPI_CallbackIDTypeDef {
HAL_QSPI_ERROR_CB_ID = 0x00U, HAL_QSPI_ABORT_CB_ID = 0x01U, HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U, HAL_QSPI_CMD_CPLT_CB_ID = 0x03U,
HAL_QSPI_RX_CPLT_CB_ID = 0x04U, HAL_QSPI_TX_CPLT_CB_ID = 0x05U, HAL_QSPI_RX_HALF_CPLT_CB_ID = 0x06U, HAL_QSPI_TX_HALF_CPLT_CB_ID = 0x07U,
HAL_QSPI_STATUS_MATCH_CB_ID = 0x08U, HAL_QSPI_TIMEOUT_CB_ID = 0x09U, HAL_QSPI_MSP_INIT_CB_ID = 0x0AU, HAL_QSPI_MSP_DEINIT_CB_ID = 0x0B0
}
HAL QSPI Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi)
Initialize the QSPI mode according to the specified parameters in the QSPI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi)
De-Initialize the QSPI peripheral.
__weak void | HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi)
Initialize the QSPI MSP.
__weak void | HAL_QSPI_MspDeInit (QSPI_HandleTypeDef *hqspi)
DeInitialize the QSPI MSP.
void | HAL_QSPI_IRQHandler (QSPI_HandleTypeDef *hqspi)
Handle QSPI interrupt request.
HAL_StatusTypeDef | HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
Set the command configuration.
HAL_StatusTypeDef | HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
Set the command configuration in interrupt mode.
HAL_StatusTypeDef | HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Send an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Receive an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Send an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
Configure the QSPI Automatic Polling Mode in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_AutoPolling_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
Configure the QSPI Automatic Polling Mode in non-blocking mode.
HAL_StatusTypeDef | HAL_QSPI_MemoryMapped (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
Configure the Memory Mapped mode.
__weak void | HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi)
Transfer Error callback.
__weak void | HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi)
Abort completed callback.
__weak void | HAL_QSPI_FifoThresholdCallback (QSPI_HandleTypeDef *hqspi)
FIFO Threshold callback.
__weak void | HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi)
Command completed callback.
__weak void | HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi)
Rx Transfer completed callback.
__weak void | HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi)
Tx Transfer completed callback.
__weak void | HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi)
Rx Half Transfer completed callback.
__weak void | HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi)
Tx Half Transfer completed callback.
__weak void | HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi)
Status Match callback.
__weak void | HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi)
Timeout callback.
HAL_StatusTypeDef | HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback)
Register a User QSPI Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId)
Unregister a User QSPI Callback QSPI Callback is redirected to the weak (surcharged) predefined callback.
HAL_QSPI_StateTypeDef | HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi)
Return the QSPI handle state.
uint32_t | HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi)
Return the QSPI error code.
HAL_StatusTypeDef | HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi)
Abort the current transmission.
HAL_StatusTypeDef | HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi)
Abort the current transmission (non-blocking function)
void | HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
Set QSPI timeout.
HAL_StatusTypeDef | HAL_QSPI_SetFifoThreshold (QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
Set QSPI Fifo threshold.
uint32_t | HAL_QSPI_GetFifoThreshold (QSPI_HandleTypeDef *hqspi)
Get QSPI Fifo threshold.

Detailed Description

Header file of QSPI HAL module.

Author:
MCD Application Team
Attention:

© COPYRIGHT(c) 2019 STMicroelectronics

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_qspi.h.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_rcc.h File Reference

  • File List
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Data Structures | Defines | Functions
stm32wbxx_hal_rcc.h File Reference

Header file of RCC HAL module. More...

#include "stm32wbxx_hal_def.h"
#include "stm32wbxx_ll_rcc.h"
#include "stm32wbxx_ll_bus.h"
#include "stm32wbxx_hal_rcc_ex.h"

Go to the source code of this file.

Data Structures

struct | RCC_PLLInitTypeDef
RCC PLL configuration structure definition. More...
struct | RCC_OscInitTypeDef
RCC Internal/External Oscillator (HSE, HSI, HSI48, MSI, LSE and LSI) configuration structure definition. More...
struct | RCC_ClkInitTypeDef
RCC System, AHB and APB buses clock configuration structure definition. More...

Defines

#define | CR_REG_INDEX 1U
#define | BDCR_REG_INDEX 2U
#define | CSR_REG_INDEX 3U
#define | CRRCR_REG_INDEX 4U
#define | RCC_FLAG_MASK 0x1FU
#define | IS_RCC_OSCILLATORTYPE(__OSCILLATOR__)
#define | IS_RCC_HSE(__HSE__)
#define | IS_RCC_LSE(__LSE__)
#define | IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
#define | IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)127U)
#define | IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
#define | IS_RCC_LSI2_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)15U)
#define | IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))
#define | IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)255U)
#define | IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))
#define | IS_RCC_PLL(__PLL__)
#define | IS_RCC_PLLSOURCE(__SOURCE__)
#define | IS_RCC_PLLM_VALUE(__VALUE__)
#define | IS_RCC_PLLN_VALUE(__VALUE__) ((6U <= (__VALUE__)) && ((__VALUE__) <= 127U))
#define | IS_RCC_PLLP_VALUE(__VALUE__) ((RCC_PLLP_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLP_DIV32))
#define | IS_RCC_PLLQ_VALUE(__VALUE__) ((RCC_PLLQ_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLQ_DIV8))
#define | IS_RCC_PLLR_VALUE(__VALUE__) ((RCC_PLLR_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLR_DIV8))
#define | IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__)
#define | IS_RCC_MSI_CLOCK_RANGE(__RANGE__)
#define | IS_RCC_CLOCKTYPE(__CLK__)
#define | IS_RCC_SYSCLKSOURCE(__SOURCE__)
#define | IS_RCC_HCLKx(__HCLK__)
#define | IS_RCC_PCLKx(__PCLK__)
#define | IS_RCC_RTCCLKSOURCE(__SOURCE__)
#define | IS_RCC_MCO(__MCOX__) ( ((__MCOX__) == RCC_MCO1) || ((__MCOX__) == RCC_MCO2) || ((__MCOX__) == RCC_MCO3) )
#define | IS_RCC_MCO1SOURCE(__SOURCE__)
#define | IS_RCC_MCO2SOURCE(__SOURCE__) IS_RCC_MCO1SOURCE((__SOURCE__))
#define | IS_RCC_MCO3SOURCE(__SOURCE__) IS_RCC_MCO1SOURCE((__SOURCE__))
#define | IS_RCC_MCODIV(__DIV__)
#define | IS_RCC_LSE_DRIVE(__DRIVE__)
#define | IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__)
#define | RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
#define | RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT /* LSE timeout in ms */
#define | RCC_OSCILLATORTYPE_NONE 0x00000000U
#define | RCC_OSCILLATORTYPE_HSE 0x00000001U
#define | RCC_OSCILLATORTYPE_HSI 0x00000002U
#define | RCC_OSCILLATORTYPE_LSE 0x00000004U
#define | RCC_OSCILLATORTYPE_LSI1 0x00000008U
#define | RCC_OSCILLATORTYPE_LSI2 0x00000010U
#define | RCC_OSCILLATORTYPE_MSI 0x00000020U
#define | RCC_OSCILLATORTYPE_HSI48 0x00000040U
#define | RCC_HSE_OFF 0x00000000U
#define | RCC_HSE_ON RCC_CR_HSEON
#define | RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
#define | RCC_LSE_OFF 0x00000000U
#define | RCC_LSE_ON RCC_BDCR_LSEON
#define | RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
#define | RCC_HSI_OFF 0x00000000U
#define | RCC_HSI_ON RCC_CR_HSION
#define | RCC_HSICALIBRATION_DEFAULT 64U
#define | RCC_LSI_OFF 0x00000000U
#define | RCC_LSI_ON (RCC_CSR_LSI1ON | RCC_CSR_LSI2ON)
#define | RCC_MSI_OFF 0x00000000U
#define | RCC_MSI_ON RCC_CR_MSION
#define | RCC_MSICALIBRATION_DEFAULT 0U
#define | RCC_HSI48_OFF 0x00000000U
#define | RCC_HSI48_ON RCC_CRRCR_HSI48ON
#define | RCC_PLL_NONE 0x00000000U
#define | RCC_PLL_OFF 0x00000001U
#define | RCC_PLL_ON 0x00000002U
#define | RCC_PLLM_DIV1 LL_RCC_PLLM_DIV_1
#define | RCC_PLLM_DIV2 LL_RCC_PLLM_DIV_2
#define | RCC_PLLM_DIV3 LL_RCC_PLLM_DIV_3
#define | RCC_PLLM_DIV4 LL_RCC_PLLM_DIV_4
#define | RCC_PLLM_DIV5 LL_RCC_PLLM_DIV_5
#define | RCC_PLLM_DIV6 LL_RCC_PLLM_DIV_6
#define | RCC_PLLM_DIV7 LL_RCC_PLLM_DIV_7
#define | RCC_PLLM_DIV8 LL_RCC_PLLM_DIV_8
#define | RCC_PLLP_DIV2 LL_RCC_PLLP_DIV_2
#define | RCC_PLLP_DIV3 LL_RCC_PLLP_DIV_3
#define | RCC_PLLP_DIV4 LL_RCC_PLLP_DIV_4
#define | RCC_PLLP_DIV5 LL_RCC_PLLP_DIV_5
#define | RCC_PLLP_DIV6 LL_RCC_PLLP_DIV_6
#define | RCC_PLLP_DIV7 LL_RCC_PLLP_DIV_7
#define | RCC_PLLP_DIV8 LL_RCC_PLLP_DIV_8
#define | RCC_PLLP_DIV9 LL_RCC_PLLP_DIV_9
#define | RCC_PLLP_DIV10 LL_RCC_PLLP_DIV_10
#define | RCC_PLLP_DIV11 LL_RCC_PLLP_DIV_11
#define | RCC_PLLP_DIV12 LL_RCC_PLLP_DIV_12
#define | RCC_PLLP_DIV13 LL_RCC_PLLP_DIV_13
#define | RCC_PLLP_DIV14 LL_RCC_PLLP_DIV_14
#define | RCC_PLLP_DIV15 LL_RCC_PLLP_DIV_15
#define | RCC_PLLP_DIV16 LL_RCC_PLLP_DIV_16
#define | RCC_PLLP_DIV17 LL_RCC_PLLP_DIV_17
#define | RCC_PLLP_DIV18 LL_RCC_PLLP_DIV_18
#define | RCC_PLLP_DIV19 LL_RCC_PLLP_DIV_19
#define | RCC_PLLP_DIV20 LL_RCC_PLLP_DIV_20
#define | RCC_PLLP_DIV21 LL_RCC_PLLP_DIV_21
#define | RCC_PLLP_DIV22 LL_RCC_PLLP_DIV_22
#define | RCC_PLLP_DIV23 LL_RCC_PLLP_DIV_23
#define | RCC_PLLP_DIV24 LL_RCC_PLLP_DIV_24
#define | RCC_PLLP_DIV25 LL_RCC_PLLP_DIV_25
#define | RCC_PLLP_DIV26 LL_RCC_PLLP_DIV_26
#define | RCC_PLLP_DIV27 LL_RCC_PLLP_DIV_27
#define | RCC_PLLP_DIV28 LL_RCC_PLLP_DIV_28
#define | RCC_PLLP_DIV29 LL_RCC_PLLP_DIV_29
#define | RCC_PLLP_DIV30 LL_RCC_PLLP_DIV_30
#define | RCC_PLLP_DIV31 LL_RCC_PLLP_DIV_31
#define | RCC_PLLP_DIV32 LL_RCC_PLLP_DIV_32
#define | RCC_PLLQ_DIV2 LL_RCC_PLLQ_DIV_2
#define | RCC_PLLQ_DIV3 LL_RCC_PLLQ_DIV_3
#define | RCC_PLLQ_DIV4 LL_RCC_PLLQ_DIV_4
#define | RCC_PLLQ_DIV5 LL_RCC_PLLQ_DIV_5
#define | RCC_PLLQ_DIV6 LL_RCC_PLLQ_DIV_6
#define | RCC_PLLQ_DIV7 LL_RCC_PLLQ_DIV_7
#define | RCC_PLLQ_DIV8 LL_RCC_PLLQ_DIV_8
#define | RCC_PLLR_DIV2 LL_RCC_PLLR_DIV_2
#define | RCC_PLLR_DIV3 LL_RCC_PLLR_DIV_3
#define | RCC_PLLR_DIV4 LL_RCC_PLLR_DIV_4
#define | RCC_PLLR_DIV5 LL_RCC_PLLR_DIV_5
#define | RCC_PLLR_DIV6 LL_RCC_PLLR_DIV_6
#define | RCC_PLLR_DIV7 LL_RCC_PLLR_DIV_7
#define | RCC_PLLR_DIV8 LL_RCC_PLLR_DIV_8
#define | RCC_PLLSOURCE_NONE LL_RCC_PLLSOURCE_NONE
#define | RCC_PLLSOURCE_MSI LL_RCC_PLLSOURCE_MSI
#define | RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSI
#define | RCC_PLLSOURCE_HSE LL_RCC_PLLSOURCE_HSE
#define | RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN
#define | RCC_PLL_USBCLK RCC_PLLCFGR_PLLQEN
#define | RCC_PLL_RNGCLK RCC_PLLCFGR_PLLQEN
#define | RCC_PLL_SAI1CLK RCC_PLLCFGR_PLLPEN
#define | RCC_PLL_ADCCLK RCC_PLLCFGR_PLLPEN
#define | RCC_PLLSAI1_ADCCLK RCC_PLLSAI1CFGR_PLLREN
#define | RCC_PLLSAI1_USBCLK RCC_PLLSAI1CFGR_PLLQEN
#define | RCC_PLLSAI1_SAI1CLK RCC_PLLSAI1CFGR_PLLPEN
#define | RCC_MSIRANGE_0 LL_RCC_MSIRANGE_0
#define | RCC_MSIRANGE_1 LL_RCC_MSIRANGE_1
#define | RCC_MSIRANGE_2 LL_RCC_MSIRANGE_2
#define | RCC_MSIRANGE_3 LL_RCC_MSIRANGE_3
#define | RCC_MSIRANGE_4 LL_RCC_MSIRANGE_4
#define | RCC_MSIRANGE_5 LL_RCC_MSIRANGE_5
#define | RCC_MSIRANGE_6 LL_RCC_MSIRANGE_6
#define | RCC_MSIRANGE_7 LL_RCC_MSIRANGE_7
#define | RCC_MSIRANGE_8 LL_RCC_MSIRANGE_8
#define | RCC_MSIRANGE_9 LL_RCC_MSIRANGE_9
#define | RCC_MSIRANGE_10 LL_RCC_MSIRANGE_10
#define | RCC_MSIRANGE_11 LL_RCC_MSIRANGE_11
#define | RCC_CLOCKTYPE_SYSCLK 0x00000001U
#define | RCC_CLOCKTYPE_HCLK 0x00000002U
#define | RCC_CLOCKTYPE_PCLK1 0x00000004U
#define | RCC_CLOCKTYPE_PCLK2 0x00000008U
#define | RCC_CLOCKTYPE_HCLK2 0x00000020U
#define | RCC_CLOCKTYPE_HCLK4 0x00000040U
#define | RCC_SYSCLKSOURCE_MSI LL_RCC_SYS_CLKSOURCE_MSI
#define | RCC_SYSCLKSOURCE_HSI LL_RCC_SYS_CLKSOURCE_HSI
#define | RCC_SYSCLKSOURCE_HSE LL_RCC_SYS_CLKSOURCE_HSE
#define | RCC_SYSCLKSOURCE_PLLCLK LL_RCC_SYS_CLKSOURCE_PLL
#define | RCC_SYSCLKSOURCE_STATUS_MSI LL_RCC_SYS_CLKSOURCE_STATUS_MSI
#define | RCC_SYSCLKSOURCE_STATUS_HSI LL_RCC_SYS_CLKSOURCE_STATUS_HSI
#define | RCC_SYSCLKSOURCE_STATUS_HSE LL_RCC_SYS_CLKSOURCE_STATUS_HSE
#define | RCC_SYSCLKSOURCE_STATUS_PLLCLK LL_RCC_SYS_CLKSOURCE_STATUS_PLL
#define | RCC_SYSCLK_DIV1 LL_RCC_SYSCLK_DIV_1
#define | RCC_SYSCLK_DIV2 LL_RCC_SYSCLK_DIV_2
#define | RCC_SYSCLK_DIV3 LL_RCC_SYSCLK_DIV_3
#define | RCC_SYSCLK_DIV4 LL_RCC_SYSCLK_DIV_4
#define | RCC_SYSCLK_DIV5 LL_RCC_SYSCLK_DIV_5
#define | RCC_SYSCLK_DIV6 LL_RCC_SYSCLK_DIV_6
#define | RCC_SYSCLK_DIV8 LL_RCC_SYSCLK_DIV_8
#define | RCC_SYSCLK_DIV10 LL_RCC_SYSCLK_DIV_10
#define | RCC_SYSCLK_DIV16 LL_RCC_SYSCLK_DIV_16
#define | RCC_SYSCLK_DIV32 LL_RCC_SYSCLK_DIV_32
#define | RCC_SYSCLK_DIV64 LL_RCC_SYSCLK_DIV_64
#define | RCC_SYSCLK_DIV128 LL_RCC_SYSCLK_DIV_128
#define | RCC_SYSCLK_DIV256 LL_RCC_SYSCLK_DIV_256
#define | RCC_SYSCLK_DIV512 LL_RCC_SYSCLK_DIV_512
#define | RCC_HCLK_DIV1 LL_RCC_APB1_DIV_1
#define | RCC_HCLK_DIV2 LL_RCC_APB1_DIV_2
#define | RCC_HCLK_DIV4 LL_RCC_APB1_DIV_4
#define | RCC_HCLK_DIV8 LL_RCC_APB1_DIV_8
#define | RCC_HCLK_DIV16 LL_RCC_APB1_DIV_16
#define | RCC_RTCCLKSOURCE_NONE LL_RCC_RTC_CLKSOURCE_NONE
#define | RCC_RTCCLKSOURCE_LSE LL_RCC_RTC_CLKSOURCE_LSE
#define | RCC_RTCCLKSOURCE_LSI LL_RCC_RTC_CLKSOURCE_LSI
#define | RCC_RTCCLKSOURCE_HSE_DIV32 LL_RCC_RTC_CLKSOURCE_HSE_DIV32
#define | RCC_MCO1 0x00000000U
#define | RCC_MCO2 0x00000001U
#define | RCC_MCO3 0x00000002U
#define | RCC_MCO RCC_MCO1
#define | RCC_MCO1SOURCE_NOCLOCK LL_RCC_MCO1SOURCE_NOCLOCK
#define | RCC_MCO1SOURCE_SYSCLK LL_RCC_MCO1SOURCE_SYSCLK
#define | RCC_MCO1SOURCE_MSI LL_RCC_MCO1SOURCE_MSI
#define | RCC_MCO1SOURCE_HSI LL_RCC_MCO1SOURCE_HSI
#define | RCC_MCO1SOURCE_HSE LL_RCC_MCO1SOURCE_HSE
#define | RCC_MCO1SOURCE_PLLCLK LL_RCC_MCO1SOURCE_PLLCLK
#define | RCC_MCO1SOURCE_LSI1 LL_RCC_MCO1SOURCE_LSI1
#define | RCC_MCO1SOURCE_LSI2 LL_RCC_MCO1SOURCE_LSI2
#define | RCC_MCO1SOURCE_LSE LL_RCC_MCO1SOURCE_LSE
#define | RCC_MCO1SOURCE_HSI48 LL_RCC_MCO1SOURCE_HSI48
#define | RCC_MCO1SOURCE_HSE_BEFORE_STAB LL_RCC_MCO1SOURCE_HSE_BEFORE_STAB
#define | RCC_MCODIV_1 LL_RCC_MCO1_DIV_1
#define | RCC_MCODIV_2 LL_RCC_MCO1_DIV_2
#define | RCC_MCODIV_4 LL_RCC_MCO1_DIV_4
#define | RCC_MCODIV_8 LL_RCC_MCO1_DIV_8
#define | RCC_MCODIV_16 LL_RCC_MCO1_DIV_16
#define | RCC_HSEAMPTHRESHOLD_1_2 LL_RCC_HSEAMPTHRESHOLD_1_2
#define | RCC_HSEAMPTHRESHOLD_3_4 LL_RCC_HSEAMPTHRESHOLD_3_4
#define | RCC_HSE_CURRENTMAX_0 LL_RCC_HSE_CURRENTMAX_0
#define | RCC_HSE_CURRENTMAX_1 LL_RCC_HSE_CURRENTMAX_1
#define | RCC_HSE_CURRENTMAX_2 LL_RCC_HSE_CURRENTMAX_2
#define | RCC_HSE_CURRENTMAX_3 LL_RCC_HSE_CURRENTMAX_3
#define | RCC_HSE_CURRENTMAX_4 LL_RCC_HSE_CURRENTMAX_4
#define | RCC_HSE_CURRENTMAX_5 LL_RCC_HSE_CURRENTMAX_5
#define | RCC_HSE_CURRENTMAX_6 LL_RCC_HSE_CURRENTMAX_6
#define | RCC_HSE_CURRENTMAX_7 LL_RCC_HSE_CURRENTMAX_7
#define | RCC_IT_LSI1RDY LL_RCC_CIFR_LSI1RDYF
#define | RCC_IT_LSI2RDY LL_RCC_CIFR_LSI2RDYF
#define | RCC_IT_LSERDY LL_RCC_CIFR_LSERDYF
#define | RCC_IT_MSIRDY LL_RCC_CIFR_MSIRDYF
#define | RCC_IT_HSIRDY LL_RCC_CIFR_HSIRDYF
#define | RCC_IT_HSERDY LL_RCC_CIFR_HSERDYF
#define | RCC_IT_PLLRDY LL_RCC_CIFR_PLLRDYF
#define | RCC_IT_PLLSAI1RDY LL_RCC_CIFR_PLLSAI1RDYF
#define | RCC_IT_HSECSS LL_RCC_CIFR_CSSF
#define | RCC_IT_LSECSS LL_RCC_CIFR_LSECSSF
#define | RCC_IT_HSI48RDY LL_RCC_CIFR_HSI48RDYF
#define | RCC_FLAG_MSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos)
#define | RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)
#define | RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)
#define | RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)
#define | RCC_FLAG_PLLSAI1RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI1RDY_Pos)
#define | RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)
#define | RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos)
#define | RCC_FLAG_LSI1RDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSI1RDY_Pos)
#define | RCC_FLAG_LSI2RDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSI2RDY_Pos)
#define | RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos)
#define | RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)
#define | RCC_FLAG_BORRST ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos)
#define | RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)
#define | RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)
#define | RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)
#define | RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)
#define | RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos)
#define | RCC_LSEDRIVE_LOW LL_RCC_LSEDRIVE_LOW
#define | RCC_LSEDRIVE_MEDIUMLOW LL_RCC_LSEDRIVE_MEDIUMLOW
#define | RCC_LSEDRIVE_MEDIUMHIGH LL_RCC_LSEDRIVE_MEDIUMHIGH
#define | RCC_LSEDRIVE_HIGH LL_RCC_LSEDRIVE_HIGH
#define | RCC_STOP_WAKEUPCLOCK_MSI LL_RCC_STOP_WAKEUPCLOCK_MSI
#define | RCC_STOP_WAKEUPCLOCK_HSI LL_RCC_STOP_WAKEUPCLOCK_HSI
#define | __HAL_RCC_DMA1_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1)
#define | __HAL_RCC_DMA2_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA2)
#define | __HAL_RCC_DMAMUX1_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMAMUX1)
#define | __HAL_RCC_CRC_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_CRC)
#define | __HAL_RCC_TSC_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_TSC)
#define | __HAL_RCC_DMA1_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_DMA1)
#define | __HAL_RCC_DMA2_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_DMA2)
#define | __HAL_RCC_DMAMUX1_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_DMAMUX1)
#define | __HAL_RCC_CRC_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_CRC)
#define | __HAL_RCC_TSC_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_TSC)
#define | __HAL_RCC_GPIOA_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA)
#define | __HAL_RCC_GPIOB_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB)
#define | __HAL_RCC_GPIOC_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOC)
#define | __HAL_RCC_GPIOD_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOD)
#define | __HAL_RCC_GPIOE_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOE)
#define | __HAL_RCC_GPIOH_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOH)
#define | __HAL_RCC_ADC_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_ADC)
#define | __HAL_RCC_AES1_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_AES1)
#define | __HAL_RCC_GPIOA_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOA)
#define | __HAL_RCC_GPIOB_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOB)
#define | __HAL_RCC_GPIOC_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOC)
#define | __HAL_RCC_GPIOD_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOD)
#define | __HAL_RCC_GPIOE_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOE)
#define | __HAL_RCC_GPIOH_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOH)
#define | __HAL_RCC_ADC_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_ADC)
#define | __HAL_RCC_AES1_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_AES1)
#define | __HAL_RCC_QUADSPI_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_QUADSPI)
#define | __HAL_RCC_PKA_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PKA)
#define | __HAL_RCC_AES2_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_AES2)
#define | __HAL_RCC_RNG_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_RNG)
#define | __HAL_RCC_HSEM_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_HSEM)
#define | __HAL_RCC_IPCC_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_IPCC)
#define | __HAL_RCC_FLASH_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_FLASH)
#define | __HAL_RCC_QUADSPI_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_QUADSPI)
#define | __HAL_RCC_PKA_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_PKA)
#define | __HAL_RCC_AES2_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_AES2)
#define | __HAL_RCC_RNG_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_RNG)
#define | __HAL_RCC_HSEM_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_HSEM)
#define | __HAL_RCC_IPCC_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_IPCC)
#define | __HAL_RCC_FLASH_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_FLASH)
#define | __HAL_RCC_RTCAPB_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_RTCAPB)
#define | __HAL_RCC_WWDG_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_WWDG)
#define | __HAL_RCC_TIM2_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2)
#define | __HAL_RCC_LCD_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LCD)
#define | __HAL_RCC_SPI2_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI2)
#define | __HAL_RCC_I2C1_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C1)
#define | __HAL_RCC_I2C3_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C3)
#define | __HAL_RCC_CRS_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_CRS)
#define | __HAL_RCC_USB_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USB)
#define | __HAL_RCC_LPTIM1_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LPTIM1)
#define | __HAL_RCC_LPTIM2_CLK_ENABLE() LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_LPTIM2)
#define | __HAL_RCC_LPUART1_CLK_ENABLE() LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_LPUART1)
#define | __HAL_RCC_RTCAPB_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_RTCAPB)
#define | __HAL_RCC_TIM2_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM2)
#define | __HAL_RCC_LCD_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_LCD)
#define | __HAL_RCC_SPI2_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_SPI2)
#define | __HAL_RCC_I2C1_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C1)
#define | __HAL_RCC_I2C3_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C3)
#define | __HAL_RCC_CRS_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_CRS)
#define | __HAL_RCC_USB_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_USB)
#define | __HAL_RCC_LPTIM1_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_LPTIM1)
#define | __HAL_RCC_LPTIM2_CLK_DISABLE() LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_LPTIM2)
#define | __HAL_RCC_LPUART1_CLK_DISABLE() LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_LPUART1)
#define | __HAL_RCC_TIM1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM1)
#define | __HAL_RCC_SPI1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI1)
#define | __HAL_RCC_USART1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1)
#define | __HAL_RCC_TIM16_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM16)
#define | __HAL_RCC_TIM17_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM17)
#define | __HAL_RCC_SAI1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SAI1)
#define | __HAL_RCC_TIM1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM1)
#define | __HAL_RCC_SPI1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SPI1)
#define | __HAL_RCC_USART1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_USART1)
#define | __HAL_RCC_TIM16_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM16)
#define | __HAL_RCC_TIM17_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM17)
#define | __HAL_RCC_SAI1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SAI1)
#define | __HAL_RCC_DMA1_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA1)
#define | __HAL_RCC_DMA2_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA2)
#define | __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMAMUX1)
#define | __HAL_RCC_CRC_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_CRC)
#define | __HAL_RCC_TSC_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_TSC)
#define | __HAL_RCC_DMA1_IS_CLK_DISABLED() !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA1))
#define | __HAL_RCC_DMA2_IS_CLK_DISABLED() !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA2))
#define | __HAL_RCC_DMAMUX1_IS_CLK_DISABLED() !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMAMUX1))
#define | __HAL_RCC_CRC_IS_CLK_DISABLED() !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_CRC))
#define | __HAL_RCC_TSC_IS_CLK_DISABLED() !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_TSC))
#define | __HAL_RCC_GPIOA_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOA)
#define | __HAL_RCC_GPIOB_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOB)
#define | __HAL_RCC_GPIOC_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOC)
#define | __HAL_RCC_GPIOD_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOD)
#define | __HAL_RCC_GPIOE_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOE)
#define | __HAL_RCC_GPIOH_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOH)
#define | __HAL_RCC_ADC_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_ADC)
#define | __HAL_RCC_AES1_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_AES1)
#define | __HAL_RCC_GPIOA_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOA))
#define | __HAL_RCC_GPIOB_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOB))
#define | __HAL_RCC_GPIOC_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOC))
#define | __HAL_RCC_GPIOD_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOD))
#define | __HAL_RCC_GPIOE_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOE))
#define | __HAL_RCC_GPIOH_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOH))
#define | __HAL_RCC_ADC_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_ADC))
#define | __HAL_RCC_AES1_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_AES1))
#define | __HAL_RCC_QUADSPI_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_QUADSPI)
#define | __HAL_RCC_PKA_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_PKA)
#define | __HAL_RCC_AES2_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_AES2)
#define | __HAL_RCC_RNG_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_RNG)
#define | __HAL_RCC_HSEM_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_HSEM)
#define | __HAL_RCC_IPCC_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_IPCC)
#define | __HAL_RCC_FLASH_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_FLASH)
#define | __HAL_RCC_QUADSPI_IS_CLK_DISABLED() !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_QUADSPI))
#define | __HAL_RCC_PKA_IS_CLK_DISABLED() !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_PKA))
#define | __HAL_RCC_AES2_IS_CLK_DISABLED() !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_AES2))
#define | __HAL_RCC_RNG_IS_CLK_DISABLED() !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_RNG))
#define | __HAL_RCC_HSEM_IS_CLK_DISABLED() !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_HSEM))
#define | __HAL_RCC_IPCC_IS_CLK_DISABLED() !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_IPCC))
#define | __HAL_RCC_FLASH_IS_CLK_DISABLED() !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_FLASH))
#define | __HAL_RCC_RTCAPB_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_RTCAPB)
#define | __HAL_RCC_WWDG_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_WWDG)
#define | __HAL_RCC_TIM2_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM2)
#define | __HAL_RCC_LCD_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LCD)
#define | __HAL_RCC_SPI2_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_SPI2)
#define | __HAL_RCC_I2C1_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C1)
#define | __HAL_RCC_I2C3_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C3)
#define | __HAL_RCC_CRS_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_CRS)
#define | __HAL_RCC_USB_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_USB)
#define | __HAL_RCC_LPTIM1_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LPTIM1)
#define | __HAL_RCC_LPTIM2_IS_CLK_ENABLED() LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPTIM2)
#define | __HAL_RCC_LPUART1_IS_CLK_ENABLED() LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPUART1)
#define | __HAL_RCC_RTCAPB_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_RTCAPB))
#define | __HAL_RCC_WWDG_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_WWDG))
#define | __HAL_RCC_TIM2_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM2))
#define | __HAL_RCC_LCD_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LCD))
#define | __HAL_RCC_SPI2_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_SPI2))
#define | __HAL_RCC_I2C1_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C1))
#define | __HAL_RCC_I2C3_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C3))
#define | __HAL_RCC_CRS_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_CRS))
#define | __HAL_RCC_USB_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_USB))
#define | __HAL_RCC_LPTIM1_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LPTIM1))
#define | __HAL_RCC_LPTIM2_IS_CLK_DISABLED() !(LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPTIM2))
#define | __HAL_RCC_LPUART1_IS_CLK_DISABLED() !(LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPUART1))
#define | __HAL_RCC_TIM1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM1)
#define | __HAL_RCC_SPI1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SPI1)
#define | __HAL_RCC_USART1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_USART1)
#define | __HAL_RCC_TIM16_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM16)
#define | __HAL_RCC_TIM17_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM17)
#define | __HAL_RCC_SAI1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SAI1)
#define | __HAL_RCC_TIM1_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM1))
#define | __HAL_RCC_SPI1_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SPI1))
#define | __HAL_RCC_USART1_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_USART1))
#define | __HAL_RCC_TIM16_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM16))
#define | __HAL_RCC_TIM17_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM17))
#define | __HAL_RCC_SAI1_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SAI1))
#define | __HAL_RCC_C2DMA1_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMA1)
#define | __HAL_RCC_C2DMA2_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMA2)
#define | __HAL_RCC_C2DMAMUX1_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1)
#define | __HAL_RCC_C2SRAM1_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_SRAM1)
#define | __HAL_RCC_C2CRC_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_CRC)
#define | __HAL_RCC_C2TSC_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_TSC)
#define | __HAL_RCC_C2DMA1_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_DMA1)
#define | __HAL_RCC_C2DMA2_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_DMA2)
#define | __HAL_RCC_C2DMAMUX1_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1)
#define | __HAL_RCC_C2SRAM1_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_SRAM1)
#define | __HAL_RCC_C2CRC_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_CRC)
#define | __HAL_RCC_C2TSC_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_TSC)
#define | __HAL_RCC_C2GPIOA_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA)
#define | __HAL_RCC_C2GPIOB_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB)
#define | __HAL_RCC_C2GPIOC_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC)
#define | __HAL_RCC_C2GPIOD_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOD)
#define | __HAL_RCC_C2GPIOE_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE)
#define | __HAL_RCC_C2GPIOH_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH)
#define | __HAL_RCC_C2ADC_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_ADC)
#define | __HAL_RCC_C2AES1_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_AES1)
#define | __HAL_RCC_C2GPIOA_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA)
#define | __HAL_RCC_C2GPIOB_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB)
#define | __HAL_RCC_C2GPIOC_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC)
#define | __HAL_RCC_C2GPIOD_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOD)
#define | __HAL_RCC_C2GPIOE_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE)
#define | __HAL_RCC_C2GPIOH_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH)
#define | __HAL_RCC_C2ADC_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_ADC)
#define | __HAL_RCC_C2AES1_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_AES1)
#define | __HAL_RCC_C2PKA_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_PKA)
#define | __HAL_RCC_C2AES2_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_AES2)
#define | __HAL_RCC_C2RNG_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_RNG)
#define | __HAL_RCC_C2HSEM_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_HSEM)
#define | __HAL_RCC_C2IPCC_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_IPCC)
#define | __HAL_RCC_C2FLASH_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_FLASH)
#define | __HAL_RCC_C2PKA_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_PKA)
#define | __HAL_RCC_C2AES2_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_AES2)
#define | __HAL_RCC_C2RNG_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_RNG)
#define | __HAL_RCC_C2HSEM_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_HSEM)
#define | __HAL_RCC_C2IPCC_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_IPCC)
#define | __HAL_RCC_C2FLASH_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_FLASH)
#define | __HAL_RCC_C2RTCAPB_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB)
#define | __HAL_RCC_C2TIM2_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_TIM2)
#define | __HAL_RCC_C2LCD_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_LCD)
#define | __HAL_RCC_C2SPI2_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_SPI2)
#define | __HAL_RCC_C2I2C1_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_I2C1)
#define | __HAL_RCC_C2I2C3_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_I2C3)
#define | __HAL_RCC_C2CRS_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_CRS)
#define | __HAL_RCC_C2USB_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_USB)
#define | __HAL_RCC_C2LPTIM1_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1)
#define | __HAL_RCC_C2LPTIM2_CLK_ENABLE() LL_C2_APB1_GRP2_EnableClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2)
#define | __HAL_RCC_C2LPUART1_CLK_ENABLE() LL_C2_APB1_GRP2_EnableClock(LL_C2_APB1_GRP2_PERIPH_LPUART1)
#define | __HAL_RCC_C2RTCAPB_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB)
#define | __HAL_RCC_C2TIM2_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_TIM2)
#define | __HAL_RCC_C2LCD_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_LCD)
#define | __HAL_RCC_C2SPI2_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_SPI2)
#define | __HAL_RCC_C2I2C1_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_I2C1)
#define | __HAL_RCC_C2I2C3_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_I2C3)
#define | __HAL_RCC_C2CRS_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_CRS)
#define | __HAL_RCC_C2USB_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_USB)
#define | __HAL_RCC_C2LPTIM1_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1)
#define | __HAL_RCC_C2LPTIM2_CLK_DISABLE() LL_C2_APB1_GRP2_DisableClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2)
#define | __HAL_RCC_C2LPUART1_CLK_DISABLE() LL_C2_APB1_GRP2_DisableClock(LL_C2_APB1_GRP2_PERIPH_LPUART1)
#define | __HAL_RCC_C2TIM1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_TIM1)
#define | __HAL_RCC_C2SPI1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_SPI1)
#define | __HAL_RCC_C2USART1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_USART1)
#define | __HAL_RCC_C2TIM16_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_TIM16)
#define | __HAL_RCC_C2TIM17_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_TIM17)
#define | __HAL_RCC_C2SAI1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_SAI1)
#define | __HAL_RCC_C2TIM1_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_TIM1)
#define | __HAL_RCC_C2SPI1_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_SPI1)
#define | __HAL_RCC_C2USART1_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_USART1)
#define | __HAL_RCC_C2TIM16_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_TIM16)
#define | __HAL_RCC_C2TIM17_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_TIM17)
#define | __HAL_RCC_C2SAI1_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_SAI1)
#define | __HAL_RCC_C2BLE_CLK_ENABLE() LL_C2_APB3_GRP1_EnableClock(LL_C2_APB3_GRP1_PERIPH_BLE)
#define | __HAL_RCC_C2802_CLK_ENABLE() LL_C2_APB3_GRP1_EnableClock(LL_C2_APB3_GRP1_PERIPH_802)
#define | __HAL_RCC_C2BLE_CLK_DISABLE() LL_C2_APB3_GRP1_DisableClock(LL_C2_APB3_GRP1_PERIPH_BLE)
#define | __HAL_RCC_C2802_CLK_DISABLE() LL_C2_APB3_GRP1_DisableClock(LL_C2_APB3_GRP1_PERIPH_802)
#define | __HAL_RCC_C2DMA1_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMA1)
#define | __HAL_RCC_C2DMA2_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMA2)
#define | __HAL_RCC_C2DMAMUX1_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1)
#define | __HAL_RCC_C2SRAM1_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_SRAM1)
#define | __HAL_RCC_C2CRC_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_CRC)
#define | __HAL_RCC_C2TSC_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_TSC)
#define | __HAL_RCC_C2DMA1_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMA1))
#define | __HAL_RCC_C2DMA2_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMA2))
#define | __HAL_RCC_C2DMAMUX1_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1))
#define | __HAL_RCC_C2SRAM1_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_SRAM1))
#define | __HAL_RCC_C2CRC_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_CRC))
#define | __HAL_RCC_C2TSC_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_TSC))
#define | __HAL_RCC_C2GPIOA_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA)
#define | __HAL_RCC_C2GPIOB_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB)
#define | __HAL_RCC_C2GPIOC_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC)
#define | __HAL_RCC_C2GPIOD_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOD)
#define | __HAL_RCC_C2GPIOE_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE)
#define | __HAL_RCC_C2GPIOH_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH)
#define | __HAL_RCC_C2ADC_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_ADC)
#define | __HAL_RCC_C2AES1_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_AES1)
#define | __HAL_RCC_C2GPIOA_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA))
#define | __HAL_RCC_C2GPIOB_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB))
#define | __HAL_RCC_C2GPIOC_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC))
#define | __HAL_RCC_C2GPIOD_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOD))
#define | __HAL_RCC_C2GPIOE_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE))
#define | __HAL_RCC_C2GPIOH_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH))
#define | __HAL_RCC_C2ADC_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_ADC))
#define | __HAL_RCC_C2AES1_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_AES1))
#define | __HAL_RCC_C2PKA_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_PKA)
#define | __HAL_RCC_C2AES2_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_AES2)
#define | __HAL_RCC_C2RNG_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_RNG)
#define | __HAL_RCC_C2HSEM_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_HSEM)
#define | __HAL_RCC_C2IPCC_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_IPCC)
#define | __HAL_RCC_C2FLASH_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_FLASH)
#define | __HAL_RCC_C2PKA_IS_CLK_DISABLED() !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_PKA))
#define | __HAL_RCC_C2AES2_IS_CLK_DISABLED() !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_AES2))
#define | __HAL_RCC_C2RNG_IS_CLK_DISABLED() !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_RNG))
#define | __HAL_RCC_C2HSEM_IS_CLK_DISABLED() !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_HSEM))
#define | __HAL_RCC_C2IPCC_IS_CLK_DISABLED() !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_IPCC))
#define | __HAL_RCC_C2FLASH_IS_CLK_DISABLED() !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_FLASH))
#define | __HAL_RCC_C2RTCAPB_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB)
#define | __HAL_RCC_C2TIM2_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_TIM2)
#define | __HAL_RCC_C2LCD_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LCD)
#define | __HAL_RCC_C2SPI2_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_SPI2)
#define | __HAL_RCC_C2I2C1_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C1)
#define | __HAL_RCC_C2I2C3_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C3)
#define | __HAL_RCC_C2CRS_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_CRS)
#define | __HAL_RCC_C2USB_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_USB)
#define | __HAL_RCC_C2LPTIM1_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1)
#define | __HAL_RCC_C2LPTIM2_IS_CLK_ENABLED() LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2)
#define | __HAL_RCC_C2LPUART1_IS_CLK_ENABLED() LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP2_PERIPH_LPUART1)
#define | __HAL_RCC_C2RTCAPB_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB))
#define | __HAL_RCC_C2TIM2_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_TIM2))
#define | __HAL_RCC_C2LCD_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LCD))
#define | __HAL_RCC_C2SPI2_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_SPI2))
#define | __HAL_RCC_C2I2C1_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C1))
#define | __HAL_RCC_C2I2C3_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C3))
#define | __HAL_RCC_C2CRS_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_CRS))
#define | __HAL_RCC_C2USB_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_USB))
#define | __HAL_RCC_C2LPTIM1_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1))
#define | __HAL_RCC_C2LPTIM2_IS_CLK_DISABLED() !(LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2))
#define | __HAL_RCC_C2LPUART1_IS_CLK_DISABLED() !(LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1))
#define | __HAL_RCC_C2TIM1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM1)
#define | __HAL_RCC_C2SPI1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SPI1)
#define | __HAL_RCC_C2USART1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_USART1)
#define | __HAL_RCC_C2TIM16_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM16)
#define | __HAL_RCC_C2TIM17_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM17)
#define | __HAL_RCC_C2SAI1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SAI1)
#define | __HAL_RCC_C2TIM1_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM1))
#define | __HAL_RCC_C2SPI1_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SPI1))
#define | __HAL_RCC_C2USART1_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_USART1))
#define | __HAL_RCC_C2TIM16_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM16))
#define | __HAL_RCC_C2TIM17_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM17))
#define | __HAL_RCC_C2SAI1_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SAI1))
#define | __HAL_RCC_C2BLE_IS_CLK_ENABLED() LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_BLE)
#define | __HAL_RCC_C2802_IS_CLK_ENABLED() LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_802)
#define | __HAL_RCC_C2BLE_IS_CLK_DISABLED() !(LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_BLE))
#define | __HAL_RCC_C2802_IS_CLK_DISABLED() !(LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_802))
#define | __HAL_RCC_AHB1_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_ALL)
#define | __HAL_RCC_DMA1_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1)
#define | __HAL_RCC_DMA2_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2)
#define | __HAL_RCC_DMAMUX1_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMAMUX1)
#define | __HAL_RCC_CRC_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CRC)
#define | __HAL_RCC_TSC_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_TSC)
#define | __HAL_RCC_AHB1_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ALL)
#define | __HAL_RCC_DMA1_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1)
#define | __HAL_RCC_DMA2_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2)
#define | __HAL_RCC_DMAMUX1_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMAMUX1)
#define | __HAL_RCC_CRC_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC)
#define | __HAL_RCC_TSC_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_TSC)
#define | __HAL_RCC_AHB2_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ALL)
#define | __HAL_RCC_GPIOA_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOA)
#define | __HAL_RCC_GPIOB_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOB)
#define | __HAL_RCC_GPIOC_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOC)
#define | __HAL_RCC_GPIOD_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOD)
#define | __HAL_RCC_GPIOE_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOE)
#define | __HAL_RCC_GPIOH_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOH)
#define | __HAL_RCC_ADC_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC)
#define | __HAL_RCC_AES1_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_AES1)
#define | __HAL_RCC_AHB2_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ALL)
#define | __HAL_RCC_GPIOA_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOA)
#define | __HAL_RCC_GPIOB_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOB)
#define | __HAL_RCC_GPIOC_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOC)
#define | __HAL_RCC_GPIOD_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOD)
#define | __HAL_RCC_GPIOE_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOE)
#define | __HAL_RCC_GPIOH_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOH)
#define | __HAL_RCC_ADC_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC)
#define | __HAL_RCC_AES1_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_AES1)
#define | __HAL_RCC_AHB3_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ALL)
#define | __HAL_RCC_QUADSPI_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_QUADSPI)
#define | __HAL_RCC_PKA_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_PKA)
#define | __HAL_RCC_AES2_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_AES2)
#define | __HAL_RCC_RNG_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_RNG)
#define | __HAL_RCC_HSEM_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_HSEM)
#define | __HAL_RCC_IPCC_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_IPCC)
#define | __HAL_RCC_FLASH_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_FLASH)
#define | __HAL_RCC_AHB3_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ALL)
#define | __HAL_RCC_QUADSPI_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_QUADSPI)
#define | __HAL_RCC_PKA_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_PKA)
#define | __HAL_RCC_AES2_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_AES2)
#define | __HAL_RCC_RNG_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_RNG)
#define | __HAL_RCC_HSEM_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_HSEM)
#define | __HAL_RCC_IPCC_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_IPCC)
#define | __HAL_RCC_FLASH_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_FLASH)
#define | __HAL_RCC_APB1L_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_ALL)
#define | __HAL_RCC_TIM2_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2)
#define | __HAL_RCC_LCD_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LCD)
#define | __HAL_RCC_SPI2_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2)
#define | __HAL_RCC_I2C1_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1)
#define | __HAL_RCC_I2C3_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3)
#define | __HAL_RCC_CRS_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_CRS)
#define | __HAL_RCC_USB_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USB)
#define | __HAL_RCC_LPTIM1_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1)
#define | __HAL_RCC_APB1H_FORCE_RESET() LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_ALL)
#define | __HAL_RCC_LPUART1_FORCE_RESET() LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPUART1)
#define | __HAL_RCC_LPTIM2_FORCE_RESET() LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPTIM2)
#define | __HAL_RCC_APB1_FORCE_RESET()
#define | __HAL_RCC_APB1L_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_ALL)
#define | __HAL_RCC_TIM2_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2)
#define | __HAL_RCC_LCD_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LCD)
#define | __HAL_RCC_SPI2_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2)
#define | __HAL_RCC_I2C1_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1)
#define | __HAL_RCC_I2C3_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3)
#define | __HAL_RCC_CRS_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_CRS)
#define | __HAL_RCC_USB_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USB)
#define | __HAL_RCC_LPTIM1_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1)
#define | __HAL_RCC_APB1H_RELEASE_RESET() LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_ALL)
#define | __HAL_RCC_LPUART1_RELEASE_RESET() LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPUART1)
#define | __HAL_RCC_LPTIM2_RELEASE_RESET() LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPTIM2)
#define | __HAL_RCC_APB1_RELEASE_RESET()
#define | __HAL_RCC_APB2_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ALL)
#define | __HAL_RCC_TIM1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1)
#define | __HAL_RCC_SPI1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1)
#define | __HAL_RCC_USART1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1)
#define | __HAL_RCC_TIM16_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16)
#define | __HAL_RCC_TIM17_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17)
#define | __HAL_RCC_SAI1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SAI1)
#define | __HAL_RCC_APB2_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ALL)
#define | __HAL_RCC_TIM1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1)
#define | __HAL_RCC_SPI1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1)
#define | __HAL_RCC_USART1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1)
#define | __HAL_RCC_TIM16_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16)
#define | __HAL_RCC_TIM17_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17)
#define | __HAL_RCC_SAI1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SAI1)
#define | __HAL_RCC_APB3_FORCE_RESET() LL_APB3_GRP1_ForceReset(LL_APB3_GRP1_PERIPH_ALL)
#define | __HAL_RCC_RF_FORCE_RESET() LL_APB3_GRP1_ForceReset(LL_APB3_GRP1_PERIPH_RF)
#define | __HAL_RCC_APB3_RELEASE_RESET() LL_APB3_GRP1_ReleaseReset(LL_APB3_GRP1_PERIPH_ALL)
#define | __HAL_RCC_RF_RELEASE_RESET() LL_APB3_GRP1_ReleaseReset(LL_APB3_GRP1_PERIPH_RF)
#define | __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_DMA1)
#define | __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_DMA2)
#define | __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_DMAMUX1)
#define | __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_SRAM1)
#define | __HAL_RCC_CRC_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_CRC)
#define | __HAL_RCC_TSC_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_TSC)
#define | __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_DMA1)
#define | __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_DMA2)
#define | __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_DMAMUX1)
#define | __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_SRAM1)
#define | __HAL_RCC_CRC_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_CRC)
#define | __HAL_RCC_TSC_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_TSC)
#define | __HAL_RCC_C2DMA1_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA1)
#define | __HAL_RCC_C2DMA2_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA2)
#define | __HAL_RCC_C2DMAMUX1_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1)
#define | __HAL_RCC_C2SRAM1_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_SRAM1)
#define | __HAL_RCC_C2CRC_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_CRC)
#define | __HAL_RCC_C2TSC_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_TSC)
#define | __HAL_RCC_C2DMA1_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA1)
#define | __HAL_RCC_C2DMA2_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA2)
#define | __HAL_RCC_C2DMAMUX1_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1)
#define | __HAL_RCC_C2SRAM1_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_SRAM1)
#define | __HAL_RCC_C2CRC_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_CRC)
#define | __HAL_RCC_C2TSC_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_TSC)
#define | __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOA)
#define | __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOB)
#define | __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOC)
#define | __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOD)
#define | __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOE)
#define | __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOH)
#define | __HAL_RCC_ADC_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_ADC)
#define | __HAL_RCC_AES1_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_AES1)
#define | __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOA)
#define | __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOB)
#define | __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOC)
#define | __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOD)
#define | __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOE)
#define | __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOH)
#define | __HAL_RCC_ADC_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_ADC)
#define | __HAL_RCC_AES1_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_AES1)
#define | __HAL_RCC_C2GPIOA_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOA)
#define | __HAL_RCC_C2GPIOB_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOB)
#define | __HAL_RCC_C2GPIOC_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOC)
#define | __HAL_RCC_C2GPIOD_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOD)
#define | __HAL_RCC_C2GPIOE_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOE)
#define | __HAL_RCC_C2GPIOH_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOH)
#define | __HAL_RCC_C2ADC_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_ADC)
#define | __HAL_RCC_C2AES1_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_AES1)
#define | __HAL_RCC_C2GPIOA_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOA)
#define | __HAL_RCC_C2GPIOB_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOB)
#define | __HAL_RCC_C2GPIOC_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOC)
#define | __HAL_RCC_C2GPIOD_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOD)
#define | __HAL_RCC_C2GPIOE_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOE)
#define | __HAL_RCC_C2GPIOH_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOH)
#define | __HAL_RCC_C2ADC_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_ADC)
#define | __HAL_RCC_C2AES1_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_AES1)
#define | __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_QUADSPI)
#define | __HAL_RCC_PKA_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_PKA)
#define | __HAL_RCC_AES2_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_AES2)
#define | __HAL_RCC_RNG_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_RNG)
#define | __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_SRAM2)
#define | __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_FLASH)
#define | __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_QUADSPI)
#define | __HAL_RCC_PKA_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_PKA)
#define | __HAL_RCC_AES2_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_AES2)
#define | __HAL_RCC_RNG_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_RNG)
#define | __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_SRAM2)
#define | __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_FLASH)
#define | __HAL_RCC_C2PKA_CLK_SLEEP_ENABLE() LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_PKA)
#define | __HAL_RCC_C2AES2_CLK_SLEEP_ENABLE() LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_AES2)
#define | __HAL_RCC_C2RNG_CLK_SLEEP_ENABLE() LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_RNG)
#define | __HAL_RCC_C2SRAM2_CLK_SLEEP_ENABLE() LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_SRAM2)
#define | __HAL_RCC_C2FLASH_CLK_SLEEP_ENABLE() LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_FLASH)
#define | __HAL_RCC_C2PKA_CLK_SLEEP_DISABLE() LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_PKA)
#define | __HAL_RCC_C2AES2_CLK_SLEEP_DISABLE() LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_AES2)
#define | __HAL_RCC_C2RNG_CLK_SLEEP_DISABLE() LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_RNG)
#define | __HAL_RCC_C2SRAM2_CLK_SLEEP_DISABLE() LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_SRAM2)
#define | __HAL_RCC_C2FLASH_CLK_SLEEP_DISABLE() LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_FLASH)
#define | __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_TIM2)
#define | __HAL_RCC_LCD_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_LCD)
#define | __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_RTCAPB)
#define | __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_WWDG)
#define | __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_SPI2)
#define | __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_I2C1)
#define | __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_I2C3)
#define | __HAL_RCC_CRS_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_CRS)
#define | __HAL_RCC_USB_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_USB)
#define | __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_LPTIM1)
#define | __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() LL_APB1_GRP2_EnableClockSleep(LL_APB1_GRP2_PERIPH_LPUART1)
#define | __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() LL_APB1_GRP2_EnableClockSleep(LL_APB1_GRP2_PERIPH_LPTIM2)
#define | __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_TIM2)
#define | __HAL_RCC_LCD_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_LCD)
#define | __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_RTCAPB)
#define | __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_WWDG)
#define | __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_SPI2)
#define | __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_I2C1)
#define | __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_I2C3)
#define | __HAL_RCC_CRS_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_CRS)
#define | __HAL_RCC_USB_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_USB)
#define | __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_LPTIM1)
#define | __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() LL_APB1_GRP2_DisableClockSleep(LL_APB1_GRP2_PERIPH_LPUART1)
#define | __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() LL_APB1_GRP2_DisableClockSleep(LL_APB1_GRP2_PERIPH_LPTIM2)
#define | __HAL_RCC_C2TIM2_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_TIM2)
#define | __HAL_RCC_C2LCD_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_LCD)
#define | __HAL_RCC_C2RTCAPB_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_RTCAPB)
#define | __HAL_RCC_C2SPI2_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_SPI2)
#define | __HAL_RCC_C2I2C1_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C1)
#define | __HAL_RCC_C2I2C3_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C3)
#define | __HAL_RCC_C2CRS_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_CRS)
#define | __HAL_RCC_C2USB_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_USB)
#define | __HAL_RCC_C2LPTIM1_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_LPTIM1)
#define | __HAL_RCC_C2LPUART1_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP2_EnableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPUART1)
#define | __HAL_RCC_C2LPTIM2_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP2_EnableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPTIM2)
#define | __HAL_RCC_C2TIM2_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_TIM2)
#define | __HAL_RCC_C2LCD_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_LCD)
#define | __HAL_RCC_C2RTCAPB_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_RTCAPB)
#define | __HAL_RCC_C2SPI2_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_SPI2)
#define | __HAL_RCC_C2I2C1_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C1)
#define | __HAL_RCC_C2I2C3_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C3)
#define | __HAL_RCC_C2CRS_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_CRS)
#define | __HAL_RCC_C2USB_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_USB)
#define | __HAL_RCC_C2LPTIM1_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_LPTIM1)
#define | __HAL_RCC_C2LPUART1_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP2_DisableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPUART1)
#define | __HAL_RCC_C2LPTIM2_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP2_DisableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPTIM2)
#define | __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_TIM1)
#define | __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_SPI1)
#define | __HAL_RCC_USART1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_USART1)
#define | __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_TIM16)
#define | __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_TIM17)
#define | __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_SAI1)
#define | __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_TIM1)
#define | __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_SPI1)
#define | __HAL_RCC_USART1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_USART1)
#define | __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_TIM16)
#define | __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_TIM17)
#define | __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_SAI1)
#define | __HAL_RCC_C2TIM1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM1)
#define | __HAL_RCC_C2SPI1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_SPI1)
#define | __HAL_RCC_C2USART1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_USART1)
#define | __HAL_RCC_C2TIM16_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM16)
#define | __HAL_RCC_C2TIM17_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM17)
#define | __HAL_RCC_C2SAI1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_SAI1)
#define | __HAL_RCC_C2TIM1_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM1)
#define | __HAL_RCC_C2SPI1_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_SPI1)
#define | __HAL_RCC_C2USART1_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_USART1)
#define | __HAL_RCC_C2TIM16_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM16)
#define | __HAL_RCC_C2TIM17_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM17)
#define | __HAL_RCC_C2SAI1_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_SAI1)
#define | __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != RESET)
#define | __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != RESET)
#define | __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != RESET)
#define | __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != RESET)
#define | __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != RESET)
#define | __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != RESET)
#define | __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == RESET)
#define | __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == RESET)
#define | __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == RESET)
#define | __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == RESET)
#define | __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == RESET)
#define | __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == RESET)
#define | __HAL_RCC_C2DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMA1SMEN) != RESET)
#define | __HAL_RCC_C2DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMA2SMEN) != RESET)
#define | __HAL_RCC_C2DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMAMUX1SMEN) != RESET)
#define | __HAL_RCC_C2SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_SRAM1SMEN) != RESET)
#define | __HAL_RCC_C2CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_CRCSMEN) != RESET)
#define | __HAL_RCC_C2TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_TSCSMEN) != RESET)
#define | __HAL_RCC_C2DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMA1SMEN) == RESET)
#define | __HAL_RCC_C2DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMA2SMEN) == RESET)
#define | __HAL_RCC_C2DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMAMUX1SMEN) == RESET)
#define | __HAL_RCC_C2SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_SRAM1SMEN) == RESET)
#define | __HAL_RCC_C2CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_CRCSMEN) == RESET)
#define | __HAL_RCC_C2TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_TSCSMEN) == RESET)
#define | __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != RESET)
#define | __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != RESET)
#define | __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != RESET)
#define | __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != RESET)
#define | __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != RESET)
#define | __HAL_RCC_AES1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AES1SMEN) != RESET)
#define | __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == RESET)
#define | __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == RESET)
#define | __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == RESET)
#define | __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == RESET)
#define | __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == RESET)
#define | __HAL_RCC_AES1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AES1SMEN) == RESET)
#define | __HAL_RCC_C2GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOASMEN) != RESET)
#define | __HAL_RCC_C2GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOBSMEN) != RESET)
#define | __HAL_RCC_C2GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOCSMEN) != RESET)
#define | __HAL_RCC_C2GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIODSMEN) != RESET)
#define | __HAL_RCC_C2GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOESMEN) != RESET)
#define | __HAL_RCC_C2GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOHSMEN) != RESET)
#define | __HAL_RCC_C2ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_ADCSMEN) != RESET)
#define | __HAL_RCC_C2AES1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_AES1SMEN) != RESET)
#define | __HAL_RCC_C2GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOASMEN) == RESET)
#define | __HAL_RCC_C2GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOBSMEN) == RESET)
#define | __HAL_RCC_C2GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOCSMEN) == RESET)
#define | __HAL_RCC_C2GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIODSMEN) == RESET)
#define | __HAL_RCC_C2GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOESMEN) == RESET)
#define | __HAL_RCC_C2GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOHSMEN) == RESET)
#define | __HAL_RCC_C2ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_ADCSMEN) == RESET)
#define | __HAL_RCC_C2AES1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_AES1SMEN) == RESET)
#define | __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QUADSPISMEN) != RESET)
#define | __HAL_RCC_PKA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_PKASMEN) != RESET)
#define | __HAL_RCC_AES2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_AES2SMEN) != RESET)
#define | __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_RNGSMEN) != RESET)
#define | __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_SRAM2SMEN) != RESET)
#define | __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FLASHSMEN) != RESET)
#define | __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QUADSPISMEN) == RESET)
#define | __HAL_RCC_PKA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_PKASMEN) == RESET)
#define | __HAL_RCC_AES2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_AES2SMEN) == RESET)
#define | __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_RNGSMEN) == RESET)
#define | __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_SRAM2SMEN) == RESET)
#define | __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FLASHSMEN) == RESET)
#define | __HAL_RCC_C2PKA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_PKASMEN) != RESET)
#define | __HAL_RCC_C2AES2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_AES2SMEN) != RESET)
#define | __HAL_RCC_C2RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_RNGSMEN) != RESET)
#define | __HAL_RCC_C2SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_SRAM2SMEN) != RESET)
#define | __HAL_RCC_C2FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_FLASHSMEN) != RESET)
#define | __HAL_RCC_C2PKA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_PKASMEN) == RESET)
#define | __HAL_RCC_C2AES2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_AES2SMEN) == RESET)
#define | __HAL_RCC_C2RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_RNGSMEN) == RESET)
#define | __HAL_RCC_C2SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_SRAM2SMEN) == RESET)
#define | __HAL_RCC_C2FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_FLASHSMEN) == RESET)
#define | __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != RESET)
#define | __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != RESET)
#define | __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != RESET)
#define | __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != RESET)
#define | __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != RESET)
#define | __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != RESET)
#define | __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != RESET)
#define | __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != RESET)
#define | __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) != RESET)
#define | __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != RESET)
#define | __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != RESET)
#define | __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != RESET)
#define | __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == RESET)
#define | __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == RESET)
#define | __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == RESET)
#define | __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == RESET)
#define | __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == RESET)
#define | __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == RESET)
#define | __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == RESET)
#define | __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == RESET)
#define | __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) == RESET)
#define | __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == RESET)
#define | __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == RESET)
#define | __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == RESET)
#define | __HAL_RCC_C2TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_TIM2SMEN) != RESET)
#define | __HAL_RCC_C2LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_LCDSMEN) != RESET)
#define | __HAL_RCC_C2RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_RTCAPBSMEN) != RESET)
#define | __HAL_RCC_C2SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_SPI2SMEN) != RESET)
#define | __HAL_RCC_C2I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_I2C1SMEN) != RESET)
#define | __HAL_RCC_C2I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_I2C3SMEN) != RESET)
#define | __HAL_RCC_C2CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_CRSSMEN) != RESET)
#define | __HAL_RCC_C2USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_USBSMEN) != RESET)
#define | __HAL_RCC_C2LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_LPTIM1SMEN) != RESET)
#define | __HAL_RCC_C2LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR2, RCC_C2APB1SMENR2_LPUART1SMEN) != RESET)
#define | __HAL_RCC_C2LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR2, RCC_C2APB1SMENR2_LPTIM2SMEN) != RESET)
#define | __HAL_RCC_C2TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_TIM2SMEN) == RESET)
#define | __HAL_RCC_C2LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_LCDSMEN) == RESET)
#define | __HAL_RCC_C2RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_RTCAPBSMEN) == RESET)
#define | __HAL_RCC_C2SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_SPI2SMEN) == RESET)
#define | __HAL_RCC_C2I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_I2C1SMEN) == RESET)
#define | __HAL_RCC_C2I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_I2C3SMEN) == RESET)
#define | __HAL_RCC_C2CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_CRSSMEN) == RESET)
#define | __HAL_RCC_C2USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_USBSMEN) == RESET)
#define | __HAL_RCC_C2LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_LPTIM1SMEN) == RESET)
#define | __HAL_RCC_C2LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR2, RCC_C2APB1SMENR2_LPUART1SMEN) == RESET)
#define | __HAL_RCC_C2LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR2, RCC_C2APB1SMENR2_LPTIM2SMEN) == RESET)
#define | __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != RESET)
#define | __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != RESET)
#define | __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != RESET)
#define | __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != RESET)
#define | __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != RESET)
#define | __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != RESET)
#define | __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == RESET)
#define | __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == RESET)
#define | __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == RESET)
#define | __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == RESET)
#define | __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == RESET)
#define | __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == RESET)
#define | __HAL_RCC_C2TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM1SMEN) != RESET)
#define | __HAL_RCC_C2SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SPI1SMEN) != RESET)
#define | __HAL_RCC_C2USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_USART1SMEN) != RESET)
#define | __HAL_RCC_C2TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM16SMEN) != RESET)
#define | __HAL_RCC_C2TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM17SMEN) != RESET)
#define | __HAL_RCC_C2SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SAI1SMEN) != RESET)
#define | __HAL_RCC_C2TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM1SMEN) == RESET)
#define | __HAL_RCC_C2SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SPI1SMEN) == RESET)
#define | __HAL_RCC_C2USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_USART1SMEN) == RESET)
#define | __HAL_RCC_C2TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM16SMEN) == RESET)
#define | __HAL_RCC_C2TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM17SMEN) == RESET)
#define | __HAL_RCC_C2SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SAI1SMEN) == RESET)
#define | __HAL_RCC_C2BLE_CLK_SLEEP_ENABLE() LL_C2_APB3_GRP1_EnableClockSleep(LL_C2_APB3_GRP1_PERIPH_BLE)
#define | __HAL_RCC_C2802_CLK_SLEEP_ENABLE() LL_C2_APB3_GRP1_EnableClockSleep(LL_C2_APB3_GRP1_PERIPH_802)
#define | __HAL_RCC_C2BLE_CLK_SLEEP_DISABLE() LL_C2_APB3_GRP1_DisableClockSleep(LL_C2_APB3_GRP1_PERIPH_BLE)
#define | __HAL_RCC_C2802_CLK_SLEEP_DISABLE() LL_C2_APB3_GRP1_DisableClockSleep(LL_C2_APB3_GRP1_PERIPH_802)
#define | __HAL_RCC_C2BLE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_BLESMEN) != RESET)
#define | __HAL_RCC_C2802_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_802SMEN) != RESET)
#define | __HAL_RCC_C2BLE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_BLESMEN) == RESET)
#define | __HAL_RCC_C2802_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_802SMEN) == RESET)
#define | __HAL_RCC_BACKUPRESET_FORCE() LL_RCC_ForceBackupDomainReset()
Macros to force or release the Backup domain reset.
#define | __HAL_RCC_BACKUPRESET_RELEASE() LL_RCC_ReleaseBackupDomainReset()
#define | __HAL_RCC_RTC_ENABLE() LL_RCC_EnableRTC()
Macros to enable or disable the RTC clock.
#define | __HAL_RCC_RTC_DISABLE() LL_RCC_DisableRTC()
#define | __HAL_RCC_HSI_ENABLE() LL_RCC_HSI_Enable()
Macros to enable the Internal High Speed oscillator (HSI).
#define | __HAL_RCC_HSI_DISABLE() LL_RCC_HSI_Disable()
Macro to disable the Internal High Speed oscillator (HSI).
#define | __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) LL_RCC_HSI_SetCalibTrimming(__HSICALIBRATIONVALUE__)
Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
#define | __HAL_RCC_HSIAUTOMATIC_START_ENABLE() LL_RCC_HSI_EnableAutoFromStop()
Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI) in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup.
#define | __HAL_RCC_HSIAUTOMATIC_START_DISABLE() LL_RCC_HSI_DisableAutoFromStop()
#define | __HAL_RCC_HSISTOP_ENABLE() LL_RCC_HSI_EnableInStopMode()
Macros to enable or disable the force of the Internal High Speed oscillator (HSI) in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
#define | __HAL_RCC_HSISTOP_DISABLE() LL_RCC_HSI_DisableInStopMode()
#define | __HAL_RCC_MSI_ENABLE() LL_RCC_MSI_Enable()
Macros to enable or disable the Internal Multi Speed oscillator (MSI).
#define | __HAL_RCC_MSI_DISABLE() LL_RCC_MSI_Disable()
#define | __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) LL_RCC_MSI_SetCalibTrimming(__MSICALIBRATIONVALUE__)
Macro to adjust the Internal Multi Speed oscillator (MSI) calibration value.
#define | __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) LL_RCC_MSI_SetRange(__MSIRANGEVALUE__)
Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode.
#define | __HAL_RCC_GET_MSI_RANGE() LL_RCC_MSI_GetRange()
Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode.
#define | __HAL_RCC_LSI1_ENABLE() LL_RCC_LSI1_Enable()
Macros to enable or disable the Internal Low Speed oscillator (LSI1).
#define | __HAL_RCC_LSI1_DISABLE() LL_RCC_LSI1_Disable()
#define | __HAL_RCC_LSI2_ENABLE() LL_RCC_LSI2_Enable()
Macros to enable or disable the Internal Low Speed oscillator (LSI2).
#define | __HAL_RCC_LSI2_DISABLE() LL_RCC_LSI2_Disable()
#define | __HAL_RCC_LSI2_CALIBRATIONVALUE_ADJUST(__LSI2TRIMMINGVALUE__) LL_RCC_LSI2_SetTrimming(__LSI2TRIMMINGVALUE__)
Macro to adjust the Internal Low Speed oscillator (LSI2) calibration value.
#define | __HAL_RCC_HSE_CONFIG(__STATE__)
Macro to configure the External High Speed oscillator (HSE).
#define | __HAL_RCC_HSE_DIV2_ENABLE() LL_RCC_HSE_EnableDiv2()
Macros to enable or disable the HSE Prescaler.
#define | __HAL_RCC_HSE_DIV2_DISABLE() LL_RCC_HSE_DisableDiv2()
#define | __HAL_RCC_LSE_CONFIG(__STATE__)
Macro to configure the External Low Speed oscillator (LSE).
#define | __HAL_RCC_HSI48_ENABLE() LL_RCC_HSI48_Enable()
Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48).
#define | __HAL_RCC_HSI48_DISABLE() LL_RCC_HSI48_Disable()
#define | __HAL_RCC_HSE_AMPCONFIG(__HSE_AMPTHRES__) LL_RCC_HSE_SetSenseAmplifier(__HSE_AMPTHRES__)
Macros to configure HSE sense amplifier threshold.
#define | __HAL_RCC_HSE_CURRENTCONFIG(__HSE_CURRENTMAX__) LL_RCC_HSE_SetCurrentControl(__HSE_CURRENTMAX__)
Macros to configure HSE current control.
#define | __HAL_RCC_HSE_CAPACITORTUNING(__HSE_LOAD_CAPACITANCE__) LL_RCC_HSE_SetCapacitorTuning(__HSE_LOAD_CAPACITANCE__)
Macros to configure HSE capacitor tuning.
#define | __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) LL_RCC_SetRTCClockSource(__RTC_CLKSOURCE__)
Macros to configure the RTC clock (RTCCLK).
#define | __HAL_RCC_GET_RTC_SOURCE() LL_RCC_GetRTCClockSource()
Macro to get the RTC clock source.
#define | __HAL_RCC_PLL_ENABLE() LL_RCC_PLL_Enable()
Macros to enable or disable the main PLL.
#define | __HAL_RCC_PLL_DISABLE() LL_RCC_PLL_Disable()
#define | __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
Macro to configure the PLL clock source.
#define | __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
Macro to configure the PLL multiplication factor.
#define | __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__, __PLLR__)
Macro to configure the main PLL clock source, multiplication and division factors.
#define | __HAL_RCC_GET_PLL_OSCSOURCE() LL_RCC_PLL_GetMainSource()
Macro to get the oscillator used as PLL clock source.
#define | __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_USBCLK, RCC_PLL_SAI1CLK)
#define | __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
#define | __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_USBCLK, RCC_PLL_SAI1CLK)
#define | __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) LL_RCC_SetSysClkSource(__SYSCLKSOURCE__)
Macro to configure the system clock source.
#define | __HAL_RCC_GET_SYSCLK_SOURCE() LL_RCC_GetSysClkSource()
Macro to get the clock source used as system clock.
#define | __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) LL_RCC_LSE_SetDriveCapability(__LSEDRIVE__)
Macro to configure the External Low Speed oscillator (LSE) drive capability.
#define | __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) LL_RCC_SetClkAfterWakeFromStop(__STOPWUCLK__)
Macro to configure the wake up from stop clock.
#define | __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) LL_RCC_ConfigMCO((__MCOCLKSOURCE__), (__MCODIV__))
Macro to configure the MCO clock.
#define | __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
Enable RCC interrupt.
#define | __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
Disable RCC interrupt.
#define | __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
Clear RCC interrupt pending bits (Perform Byte access to RCC_CICR[17:0] bits to clear the selected interrupt pending bits.
#define | __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
Check whether the RCC interrupt has occurred or not.
#define | __HAL_RCC_CLEAR_RESET_FLAGS() LL_RCC_ClearResetFlags()
Set RMVF bit to clear the reset flags.
#define | __HAL_RCC_GET_FLAG(__FLAG__)
Check whether the selected RCC flag is set or not.

Functions

HAL_StatusTypeDef | HAL_RCC_DeInit (void)
Reset the RCC clock configuration to the default reset state.
HAL_StatusTypeDef | HAL_RCC_OscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Initialize the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.
HAL_StatusTypeDef | HAL_RCC_ClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
Initialize the CPU, AHB and APB buses clocks according to the specified parameters in the RCC_ClkInitStruct.
void | HAL_RCC_MCOConfig (uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
Select the clock source to output on MCO1 pin(PA8) or MC02 pin (PB6) or MCO3 pin (PA15).
void | HAL_RCC_EnableCSS (void)
Enable the Clock Security System.
uint32_t | HAL_RCC_GetSysClockFreq (void)
Return the SYSCLK frequency.
uint32_t | HAL_RCC_GetHCLKFreq (void)
Return the HCLK frequency.
uint32_t | HAL_RCC_GetHCLK2Freq (void)
Return the HCLK2 frequency.
uint32_t | HAL_RCC_GetHCLK4Freq (void)
Return the HCLK4 frequency.
uint32_t | HAL_RCC_GetPCLK1Freq (void)
Return the PCLK1 frequency.
uint32_t | HAL_RCC_GetPCLK2Freq (void)
Return the PCLK2 frequency.
void | HAL_RCC_GetOscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Configure the RCC_OscInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_GetClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
Configure the RCC_ClkInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_NMI_IRQHandler (void)
Handle the RCC HSE Clock Security System interrupt request.
__weak void | HAL_RCC_CSSCallback (void)
Handle the RCC HSE Clock Security System interrupt callback.

Detailed Description

Header file of RCC HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_rcc.h.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_rcc_ex.h File Reference

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Data Structures | Defines | Functions
stm32wbxx_hal_rcc_ex.h File Reference

Header file of RCC HAL Extended module. More...

#include "stm32wbxx_hal_def.h"
#include "stm32wbxx_ll_crs.h"
#include "stm32wbxx_ll_exti.h"
#include "stm32wbxx_ll_pwr.h"

Go to the source code of this file.

Data Structures

struct | RCC_PLLSAI1InitTypeDef
PLLSAI1 Clock structure definition. More...
struct | RCC_PeriphCLKInitTypeDef
RCC extended clocks structure definition. More...
struct | RCC_CRSInitTypeDef
RCC_CRS Init structure definition. More...
struct | RCC_CRSSynchroInfoTypeDef
RCC_CRS Synchronization structure definition. More...

Defines

#define | RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
#define | RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
#define | CLK48_MASK 0x10000000U
#define | IS_RCC_LSCO(__LSCOX__) ( ((__LSCOX__) == RCC_LSCO1) || ((__LSCOX__) == RCC_LSCO2) || ((__LSCOX__) == RCC_LSCO3) )
#define | IS_RCC_LSCOSOURCE(__SOURCE__)
#define | IS_RCC_PERIPHCLOCK(__SELECTION__)
#define | IS_RCC_USART1CLKSOURCE(__SOURCE__)
#define | IS_RCC_LPUART1CLKSOURCE(__SOURCE__)
#define | IS_RCC_I2C1CLKSOURCE(__SOURCE__)
#define | IS_RCC_I2C3CLKSOURCE(__SOURCE__)
#define | IS_RCC_SAI1CLK(__SOURCE__)
#define | IS_RCC_LPTIM1CLK(__SOURCE__)
#define | IS_RCC_LPTIM2CLK(__SOURCE__)
#define | IS_RCC_RNGCLKSOURCE(__SOURCE__)
#define | IS_RCC_USBCLKSOURCE(__SOURCE__)
#define | IS_RCC_ADCCLKSOURCE(__SOURCE__)
#define | IS_RCC_RFWKPCLKSOURCE(__SOURCE__)
#define | IS_RCC_SMPSCLKDIV(__DIV__)
#define | IS_RCC_SMPSCLKSOURCE(__SOURCE__)
#define | IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((6U <= (__VALUE__)) && ((__VALUE__) <= 127U))
#define | IS_RCC_PLLSAI1P_VALUE(__VALUE__) ((RCC_PLLP_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLP_DIV32))
#define | IS_RCC_PLLSAI1Q_VALUE(__VALUE__) ((RCC_PLLQ_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLQ_DIV8))
#define | IS_RCC_PLLSAI1R_VALUE(__VALUE__) ((RCC_PLLR_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLR_DIV8))
#define | IS_RCC_TRIMOSC(__VALUE__) ((__VALUE__) == RCC_OSCILLATORTYPE_LSI2)
#define | IS_RCC_CRS_SYNC_SOURCE(__SOURCE__)
#define | IS_RCC_CRS_SYNC_DIV(__DIV__)
#define | IS_RCC_CRS_SYNC_POLARITY(__POLARITY__)
#define | IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU))
#define | IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU))
#define | IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
#define | IS_RCC_CRS_FREQERRORDIR(__DIR__)
#define | RCC_LSCO1 0x00000000U
#define | RCC_LSCO2 0x00000001U
#define | RCC_LSCO3 0x00000002U
#define | RCC_LSCOSOURCE_LSI LL_RCC_LSCO_CLKSOURCE_LSI
#define | RCC_LSCOSOURCE_LSE LL_RCC_LSCO_CLKSOURCE_LSE
#define | RCC_PERIPHCLK_USART1 0x00000001U
#define | RCC_PERIPHCLK_LPUART1 0x00000002U
#define | RCC_PERIPHCLK_I2C1 0x00000004U
#define | RCC_PERIPHCLK_I2C3 0x00000008U
#define | RCC_PERIPHCLK_LPTIM1 0x00000010U
#define | RCC_PERIPHCLK_LPTIM2 0x00000020U
#define | RCC_PERIPHCLK_SAI1 0x00000040U
#define | RCC_PERIPHCLK_CLK48SEL 0x00000100U
#define | RCC_PERIPHCLK_USB RCC_PERIPHCLK_CLK48SEL
#define | RCC_PERIPHCLK_RNG 0x00000200U
#define | RCC_PERIPHCLK_ADC 0x00000400U
#define | RCC_PERIPHCLK_RTC 0x00000800U
#define | RCC_PERIPHCLK_RFWAKEUP 0x00001000U
#define | RCC_PERIPHCLK_SMPS 0x00002000U
#define | RCC_USART1CLKSOURCE_PCLK2 LL_RCC_USART1_CLKSOURCE_PCLK2
#define | RCC_USART1CLKSOURCE_SYSCLK LL_RCC_USART1_CLKSOURCE_SYSCLK
#define | RCC_USART1CLKSOURCE_HSI LL_RCC_USART1_CLKSOURCE_HSI
#define | RCC_USART1CLKSOURCE_LSE LL_RCC_USART1_CLKSOURCE_LSE
#define | RCC_LPUART1CLKSOURCE_PCLK1 LL_RCC_LPUART1_CLKSOURCE_PCLK1
#define | RCC_LPUART1CLKSOURCE_SYSCLK LL_RCC_LPUART1_CLKSOURCE_SYSCLK
#define | RCC_LPUART1CLKSOURCE_HSI LL_RCC_LPUART1_CLKSOURCE_HSI
#define | RCC_LPUART1CLKSOURCE_LSE LL_RCC_LPUART1_CLKSOURCE_LSE
#define | RCC_I2C1CLKSOURCE_PCLK1 LL_RCC_I2C1_CLKSOURCE_PCLK1
#define | RCC_I2C1CLKSOURCE_SYSCLK LL_RCC_I2C1_CLKSOURCE_SYSCLK
#define | RCC_I2C1CLKSOURCE_HSI LL_RCC_I2C1_CLKSOURCE_HSI
#define | RCC_I2C3CLKSOURCE_PCLK1 LL_RCC_I2C3_CLKSOURCE_PCLK1
#define | RCC_I2C3CLKSOURCE_SYSCLK LL_RCC_I2C3_CLKSOURCE_SYSCLK
#define | RCC_I2C3CLKSOURCE_HSI LL_RCC_I2C3_CLKSOURCE_HSI
#define | RCC_SAI1CLKSOURCE_PLLSAI1 LL_RCC_SAI1_CLKSOURCE_PLLSAI1
#define | RCC_SAI1CLKSOURCE_PLL LL_RCC_SAI1_CLKSOURCE_PLL
#define | RCC_SAI1CLKSOURCE_HSI LL_RCC_SAI1_CLKSOURCE_HSI
#define | RCC_SAI1CLKSOURCE_PIN LL_RCC_SAI1_CLKSOURCE_PIN
#define | RCC_LPTIM1CLKSOURCE_PCLK1 LL_RCC_LPTIM1_CLKSOURCE_PCLK1
#define | RCC_LPTIM1CLKSOURCE_LSI LL_RCC_LPTIM1_CLKSOURCE_LSI
#define | RCC_LPTIM1CLKSOURCE_HSI LL_RCC_LPTIM1_CLKSOURCE_HSI
#define | RCC_LPTIM1CLKSOURCE_LSE LL_RCC_LPTIM1_CLKSOURCE_LSE
#define | RCC_LPTIM2CLKSOURCE_PCLK1 LL_RCC_LPTIM2_CLKSOURCE_PCLK1
#define | RCC_LPTIM2CLKSOURCE_LSI LL_RCC_LPTIM2_CLKSOURCE_LSI
#define | RCC_LPTIM2CLKSOURCE_HSI LL_RCC_LPTIM2_CLKSOURCE_HSI
#define | RCC_LPTIM2CLKSOURCE_LSE LL_RCC_LPTIM2_CLKSOURCE_LSE
#define | RCC_RNGCLKSOURCE_HSI48 (CLK48_MASK | LL_RCC_CLK48_CLKSOURCE_HSI48)
#define | RCC_RNGCLKSOURCE_PLL (CLK48_MASK | LL_RCC_CLK48_CLKSOURCE_PLL)
#define | RCC_RNGCLKSOURCE_MSI (CLK48_MASK | LL_RCC_CLK48_CLKSOURCE_MSI)
#define | RCC_RNGCLKSOURCE_CLK48 LL_RCC_RNG_CLKSOURCE_CLK48
#define | RCC_RNGCLKSOURCE_LSI LL_RCC_RNG_CLKSOURCE_LSI
#define | RCC_RNGCLKSOURCE_LSE LL_RCC_RNG_CLKSOURCE_LSE
#define | RCC_USBCLKSOURCE_HSI48 LL_RCC_USB_CLKSOURCE_HSI48
#define | RCC_USBCLKSOURCE_PLLSAI1 LL_RCC_USB_CLKSOURCE_PLLSAI1
#define | RCC_USBCLKSOURCE_PLL LL_RCC_USB_CLKSOURCE_PLL
#define | RCC_USBCLKSOURCE_MSI LL_RCC_USB_CLKSOURCE_MSI
#define | RCC_ADCCLKSOURCE_NONE LL_RCC_ADC_CLKSOURCE_NONE
#define | RCC_ADCCLKSOURCE_PLLSAI1 LL_RCC_ADC_CLKSOURCE_PLLSAI1
#define | RCC_ADCCLKSOURCE_PLL LL_RCC_ADC_CLKSOURCE_PLL
#define | RCC_ADCCLKSOURCE_SYSCLK LL_RCC_ADC_CLKSOURCE_SYSCLK
#define | RCC_HCLK5SOURCE_HSI 0x00000001U
#define | RCC_HCLK5SOURCE_HSE 0x00000002U
#define | RCC_RFWKPCLKSOURCE_NONE LL_RCC_RFWKP_CLKSOURCE_NONE
#define | RCC_RFWKPCLKSOURCE_LSE LL_RCC_RFWKP_CLKSOURCE_LSE
#define | RCC_RFWKPCLKSOURCE_LSI LL_RCC_RFWKP_CLKSOURCE_LSI
#define | RCC_RFWKPCLKSOURCE_HSE_DIV1024 LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024
#define | RCC_SMPSCLKSOURCE_HSI LL_RCC_SMPS_CLKSOURCE_HSI
#define | RCC_SMPSCLKSOURCE_MSI LL_RCC_SMPS_CLKSOURCE_MSI
#define | RCC_SMPSCLKSOURCE_HSE LL_RCC_SMPS_CLKSOURCE_HSE
#define | RCC_SMPSCLKSOURCE_STATUS_HSI LL_RCC_SMPS_CLKSOURCE_STATUS_HSI
#define | RCC_SMPSCLKSOURCE_STATUS_MSI LL_RCC_SMPS_CLKSOURCE_STATUS_MSI
#define | RCC_SMPSCLKSOURCE_STATUS_HSE LL_RCC_SMPS_CLKSOURCE_STATUS_HSE
#define | RCC_SMPSCLKDIV_RANGE0 LL_RCC_SMPS_DIV_0
#define | RCC_SMPSCLKDIV_RANGE1 LL_RCC_SMPS_DIV_1
#define | RCC_SMPSCLKDIV_RANGE2 LL_RCC_SMPS_DIV_2
#define | RCC_SMPSCLKDIV_RANGE3 LL_RCC_SMPS_DIV_3
#define | RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM18
#define | RCC_CRS_NONE 0x00000000U
#define | RCC_CRS_TIMEOUT 0x00000001U
#define | RCC_CRS_SYNCOK 0x00000002U
#define | RCC_CRS_SYNCWARN 0x00000004U
#define | RCC_CRS_SYNCERR 0x00000008U
#define | RCC_CRS_SYNCMISS 0x00000010U
#define | RCC_CRS_TRIMOVF 0x00000020U
#define | RCC_CRS_SYNC_SOURCE_GPIO LL_CRS_SYNC_SOURCE_GPIO
#define | RCC_CRS_SYNC_SOURCE_LSE LL_CRS_SYNC_SOURCE_LSE
#define | RCC_CRS_SYNC_SOURCE_USB LL_CRS_SYNC_SOURCE_USB
#define | RCC_CRS_SYNC_DIV1 LL_CRS_SYNC_DIV_1
#define | RCC_CRS_SYNC_DIV2 LL_CRS_SYNC_DIV_2
#define | RCC_CRS_SYNC_DIV4 LL_CRS_SYNC_DIV_4
#define | RCC_CRS_SYNC_DIV8 LL_CRS_SYNC_DIV_8
#define | RCC_CRS_SYNC_DIV16 LL_CRS_SYNC_DIV_16
#define | RCC_CRS_SYNC_DIV32 LL_CRS_SYNC_DIV_32
#define | RCC_CRS_SYNC_DIV64 LL_CRS_SYNC_DIV_64
#define | RCC_CRS_SYNC_DIV128 LL_CRS_SYNC_DIV_128
#define | RCC_CRS_SYNC_POLARITY_RISING LL_CRS_SYNC_POLARITY_RISING
#define | RCC_CRS_SYNC_POLARITY_FALLING LL_CRS_SYNC_POLARITY_FALLING
#define | RCC_CRS_RELOADVALUE_DEFAULT LL_CRS_RELOADVALUE_DEFAULT
#define | RCC_CRS_ERRORLIMIT_DEFAULT LL_CRS_ERRORLIMIT_DEFAULT
#define | RCC_CRS_HSI48CALIBRATION_DEFAULT LL_CRS_HSI48CALIBRATION_DEFAULT
#define | RCC_CRS_FREQERRORDIR_UP LL_CRS_FREQ_ERROR_DIR_UP
#define | RCC_CRS_FREQERRORDIR_DOWN LL_CRS_FREQ_ERROR_DIR_DOWN
#define | RCC_CRS_IT_SYNCOK LL_CRS_CR_SYNCOKIE
#define | RCC_CRS_IT_SYNCWARN LL_CRS_CR_SYNCWARNIE
#define | RCC_CRS_IT_ERR LL_CRS_CR_ERRIE
#define | RCC_CRS_IT_ESYNC LL_CRS_CR_ESYNCIE
#define | RCC_CRS_IT_SYNCERR LL_CRS_CR_ERRIE
#define | RCC_CRS_IT_SYNCMISS LL_CRS_CR_ERRIE
#define | RCC_CRS_IT_TRIMOVF LL_CRS_CR_ERRIE
#define | RCC_CRS_FLAG_SYNCOK LL_CRS_ISR_SYNCOKF
#define | RCC_CRS_FLAG_SYNCWARN LL_CRS_ISR_SYNCWARNF
#define | RCC_CRS_FLAG_ERR LL_CRS_ISR_ERRF
#define | RCC_CRS_FLAG_ESYNC LL_CRS_ISR_ESYNCF
#define | RCC_CRS_FLAG_SYNCERR LL_CRS_ISR_SYNCERR
#define | RCC_CRS_FLAG_SYNCMISS LL_CRS_ISR_SYNCMISS
#define | RCC_CRS_FLAG_TRIMOVF LL_CRS_ISR_TRIMOVF
#define | __HAL_RCC_PLLSAI1_CONFIG(__PLLN__, __PLLP__, __PLLQ__, __PLLR__)
Macro to configure the PLLSAI1 clock multiplication and division factors.
#define | __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLN__) MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLN, (__PLLN__) << RCC_PLLSAI1CFGR_PLLN_Pos)
Macro to configure the PLLSAI1 clock multiplication factor N.
#define | __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLP__) MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLP, (__PLLP__))
Macro to configure the PLLSAI1 clock division factor P.
#define | __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLQ__) MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLQ, (__PLLQ__))
Macro to configure the PLLSAI1 clock division factor Q.
#define | __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLR__) MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLR, (__PLLR__))
Macro to configure the PLLSAI1 clock division factor R.
#define | __HAL_RCC_PLLSAI1_ENABLE() LL_RCC_PLLSAI1_Enable()
Macros to enable the PLLSAI1.
#define | __HAL_RCC_PLLSAI1_DISABLE() LL_RCC_PLLSAI1_Disable()
Macros to disable the PLLSAI1.
#define | __HAL_RCC_PLLSAI1CLKOUT_ENABLE(__PLLSAI1_CLOCKOUT__) SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
Macros to enable each clock output (RCC_PLLSAI1_SAI1CLK, RCC_PLLSAI1_USBCLK and RCC_PLLSAI1_ADCCLK).
#define | __HAL_RCC_PLLSAI1CLKOUT_DISABLE(__PLLSAI1_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
Macros to disable each clock output (RCC_PLLSAI1_SAI1CLK, RCC_PLLSAI1_USBCLK and RCC_PLLSAI1_ADCCLK).
#define | __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__) READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
Macro to get clock output enable status (RCC_PLLSAI1_SAI1CLK, RCC_PLLSAI1_USBCLK and RCC_PLLSAI1_ADCCLK).
#define | __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__) LL_RCC_SetSAIClockSource(__SAI1_CLKSOURCE__)
Macro to configure the SAI1 clock source.
#define | __HAL_RCC_GET_SAI1_SOURCE() LL_RCC_GetSAIClockSource(LL_RCC_SAI1_CLKSOURCE)
Macro to get the SAI1 clock source.
#define | __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) LL_RCC_SetI2CClockSource(__I2C1_CLKSOURCE__)
Macro to configure the I2C1 clock (I2C1CLK).
#define | __HAL_RCC_GET_I2C1_SOURCE() LL_RCC_GetI2CClockSource(LL_RCC_I2C1_CLKSOURCE)
Macro to get the I2C1 clock source.
#define | __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) LL_RCC_SetI2CClockSource(__I2C3_CLKSOURCE__)
Macro to configure the I2C3 clock (I2C3CLK).
#define | __HAL_RCC_GET_I2C3_SOURCE() LL_RCC_GetI2CClockSource(LL_RCC_I2C3_CLKSOURCE)
Macro to get the I2C3 clock source.
#define | __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) LL_RCC_SetUSARTClockSource(__USART1_CLKSOURCE__)
Macro to configure the USART1 clock (USART1CLK).
#define | __HAL_RCC_GET_USART1_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_USART1_CLKSOURCE)
Macro to get the USART1 clock source.
#define | __HAL_RCC_LPUART1_CONFIG(__LPUART_CLKSOURCE__) LL_RCC_SetLPUARTClockSource(__LPUART_CLKSOURCE__)
Macro to configure the LPUART clock (LPUARTCLK).
#define | __HAL_RCC_GET_LPUART1_SOURCE() LL_RCC_GetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE)
Macro to get the LPUART clock source.
#define | __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) LL_RCC_SetLPTIMClockSource(__LPTIM1_CLKSOURCE__)
Macro to configure the LPTIM1 clock (LPTIM1CLK).
#define | __HAL_RCC_GET_LPTIM1_SOURCE() LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE)
Macro to get the LPTIM1 clock source.
#define | __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) LL_RCC_SetLPTIMClockSource(__LPTIM2_CLKSOURCE__)
Macro to configure the LPTIM2 clock (LPTIM2CLK).
#define | __HAL_RCC_GET_LPTIM2_SOURCE() LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE)
Macro to get the LPTIM2 clock source.
#define | __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__)
Macro to configure the RNG clock.
#define | __HAL_RCC_GET_RNG_SOURCE() LL_RCC_GetRNGClockSource(LL_RCC_RNG_CLKSOURCE)
Macro to get the direct RNG clock.
#define | __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) LL_RCC_SetUSBClockSource(__USB_CLKSOURCE__)
Macro to configure the USB clock (USBCLK).
#define | __HAL_RCC_GET_USB_SOURCE() LL_RCC_GetUSBClockSource(LL_RCC_USB_CLKSOURCE)
Macro to get the USB clock source.
#define | __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) LL_RCC_SetADCClockSource(__ADC_CLKSOURCE__)
Macro to configure the ADC interface clock.
#define | __HAL_RCC_GET_ADC_SOURCE() LL_RCC_GetADCClockSource(LL_RCC_ADC_CLKSOURCE)
Macro to get the ADC clock source.
#define | __HAL_RCC_RFWAKEUP_CONFIG(__RFWKP_CLKSOURCE__) LL_RCC_SetRFWKPClockSource(__RFWKP_CLKSOURCE__)
Macro to configure the RFWKP interface clock.
#define | __HAL_RCC_GET_RFWAKEUP_SOURCE() LL_RCC_GetRFWKPClockSource()
Macro to get the RFWKP clock source.
#define | __HAL_RCC_SMPS_DIV_CONFIG(__SMPSCLKDIV__) LL_RCC_SetSMPSPrescaler(__SMPSCLKDIV__)
Macro to configure the SMPS clock division factor.
#define | __HAL_RCC_GET_SMPS_DIV() LL_RCC_GetSMPSPrescaler()
Macro to get the SMPS clock division factor.
#define | __HAL_RCC_SMPS_CONFIG(__SMPS_CLKSOURCE__) LL_RCC_SetSMPSClockSource(__SMPS_CLKSOURCE__)
Macro to configure the SMPS interface clock.
#define | __HAL_RCC_GET_SMPS_SOURCE() LL_RCC_GetSMPSClockSelection()
Macro to get the SMPS clock source.
#define | __HAL_RCC_GET_SMPS_SOURCE_STATUS() LL_RCC_GetSMPSClockSource()
Macro to get the SMPS clock source.
#define | __HAL_RCC_PLLSAI1_ENABLE_IT() LL_RCC_EnableIT_PLLSAI1RDY()
Enable PLLSAI1RDY interrupt.
#define | __HAL_RCC_PLLSAI1_DISABLE_IT() LL_RCC_DisableIT_PLLSAI1RDY()
Disable PLLSAI1RDY interrupt.
#define | __HAL_RCC_PLLSAI1_CLEAR_IT() LL_RCC_ClearFlag_PLLSAI1RDY()
Clear the PLLSAI1RDY interrupt pending bit.
#define | __HAL_RCC_PLLSAI1_GET_IT_SOURCE() LL_RCC_IsActiveFlag_PLLSAI1RDY()
Check whether PLLSAI1RDY interrupt has occurred or not.
#define | __HAL_RCC_PLLSAI1_GET_FLAG() LL_RCC_PLLSAI1_IsReady()
Check whether the PLLSAI1RDY flag is set or not.
#define | __HAL_RCC_LSECSS_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(RCC_EXTI_LINE_LSECSS)
Enable the RCC LSE CSS Extended Interrupt C1 Line.
#define | __HAL_C2_RCC_LSECSS_EXTI_ENABLE_IT() LL_C2_EXTI_EnableIT_0_31(RCC_EXTI_LINE_LSECSS)
Enable the RCC LSE CSS Extended Interrupt C2 Line.
#define | __HAL_RCC_LSECSS_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(RCC_EXTI_LINE_LSECSS)
Disable the RCC LSE CSS Extended Interrupt C1 Line.
#define | __HAL_C2_RCC_LSECSS_EXTI_DISABLE_IT() LL_C2_EXTI_DisableIT_0_31(RCC_EXTI_LINE_LSECSS)
Disable the RCC LSE CSS Extended Interrupt C2 Line.
#define | __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(RCC_EXTI_LINE_LSECSS)
Enable the RCC LSE CSS Event C1 Line.
#define | __HAL_C2_RCC_LSECSS_EXTI_ENABLE_EVENT() LL_C2_EXTI_EnableEvent_0_31(RCC_EXTI_LINE_LSECSS)
Enable the RCC LSE CSS Event C2 Line.
#define | __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(RCC_EXTI_LINE_LSECSS)
Disable the RCC LSE CSS Event C1 Line.
#define | __HAL_C2_RCC_LSECSS_EXTI_DISABLE_EVENT() LL_C2_EXTI_DisableEvent_0_31(RCC_EXTI_LINE_LSECSS)
Disable the RCC LSE CSS Event C2 Line.
#define | __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(RCC_EXTI_LINE_LSECSS)
Enable the RCC LSE CSS Extended Interrupt Falling Trigger.
#define | __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(RCC_EXTI_LINE_LSECSS)
Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
#define | __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(RCC_EXTI_LINE_LSECSS)
Enable the RCC LSE CSS Extended Interrupt Rising Trigger.
#define | __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(RCC_EXTI_LINE_LSECSS)
Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
#define | __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
#define | __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
#define | __HAL_RCC_LSECSS_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_0_31(RCC_EXTI_LINE_LSECSS)
Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
#define | __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(RCC_EXTI_LINE_LSECSS)
Clear the RCC LSE CSS EXTI flag.
#define | __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(RCC_EXTI_LINE_LSECSS)
Generate a Software interrupt on the RCC LSE CSS EXTI line.
#define | __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
Enable the specified CRS interrupts.
#define | __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__))
Disable the specified CRS interrupts.
#define | __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET)
Check whether the CRS interrupt has occurred or not.
#define | __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__)
Clear the CRS interrupt pending bits.
#define | __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
Check whether the specified CRS flag is set or not.
#define | __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__)
Clear the CRS specified FLAG.
#define | __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() LL_CRS_EnableFreqErrorCounter()
Enable the oscillator clock for frequency error counter.
#define | __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() LL_CRS_DisableFreqErrorCounter()
Disable the oscillator clock for frequency error counter.
#define | __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() LL_CRS_EnableAutoTrimming()
Enable the automatic hardware adjustement of TRIM bits.
#define | __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() LL_CRS_DisableAutoTrimming()
Enable or disable the automatic hardware adjustement of TRIM bits.
#define | __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) __LL_CRS_CALC_CALCULATE_RELOADVALUE((__FTARGET__),(__FSYNC__))
Macro to calculate reload value to be set in CRS register according to target and sync frequencies.

Functions

HAL_StatusTypeDef | HAL_RCCEx_PeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Initialize the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.
void | HAL_RCCEx_GetPeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
uint32_t | HAL_RCCEx_GetPeriphCLKFreq (uint32_t PeriphClk)
Return the peripheral clock frequency for peripherals with clock source.
uint32_t | HAL_RCCEx_GetRngCLKSource (void)
Return the RNG clock source.
HAL_StatusTypeDef | HAL_RCCEx_EnablePLLSAI1 (RCC_PLLSAI1InitTypeDef *PLLSAI1Init)
Enable PLLSAI1.
HAL_StatusTypeDef | HAL_RCCEx_DisablePLLSAI1 (void)
Disable PLLSAI1.
void | HAL_RCCEx_WakeUpStopCLKConfig (uint32_t WakeUpClk)
Configure the oscillator clock source for wakeup from Stop and CSS backup clock.
void | HAL_RCCEx_EnableLSECSS (void)
Enable the LSE Clock Security System.
void | HAL_RCCEx_DisableLSECSS (void)
Disable the LSE Clock Security System.
void | HAL_RCCEx_EnableLSECSS_IT (void)
Enable the LSE Clock Security System Interrupt & corresponding EXTI line.
void | HAL_RCCEx_LSECSS_IRQHandler (void)
Handle the RCC LSE Clock Security System interrupt request.
__weak void | HAL_RCCEx_LSECSS_Callback (void)
RCCEx LSE Clock Security System interrupt callback.
void | HAL_RCCEx_LSCOConfig (uint32_t RCC_LSCOx, uint32_t RCC_LSCOSource)
Select the clock source to output on LSCO1 pin(PA2) or LSC02 pin (PH3) or LSCO3 pin (PC12).
void | HAL_RCCEx_EnableLSCO (uint32_t LSCOSource)
Select the Low Speed clock source to output on LSCO pin (PA2).
void | HAL_RCCEx_DisableLSCO (void)
Disable the Low Speed clock output.
void | HAL_RCCEx_EnableMSIPLLMode (void)
Enable the PLL-mode of the MSI.
void | HAL_RCCEx_DisableMSIPLLMode (void)
Disable the PLL-mode of the MSI.
HAL_StatusTypeDef | HAL_RCCEx_TrimOsc (uint32_t OscillatorType)
Set trimming value.
void | HAL_RCCEx_CRSConfig (RCC_CRSInitTypeDef *pInit)
Start automatic synchronization for polling mode.
void | HAL_RCCEx_CRSSoftwareSynchronizationGenerate (void)
Generate the software synchronization event.
void | HAL_RCCEx_CRSGetSynchronizationInfo (RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
Return synchronization info.
uint32_t | HAL_RCCEx_CRSWaitSynchronization (uint32_t Timeout)
Wait for CRS Synchronization status.
void | HAL_RCCEx_CRS_IRQHandler (void)
Handle the Clock Recovery System interrupt request.
__weak void | HAL_RCCEx_CRS_SyncOkCallback (void)
RCCEx Clock Recovery System SYNCOK interrupt callback.
__weak void | HAL_RCCEx_CRS_SyncWarnCallback (void)
RCCEx Clock Recovery System SYNCWARN interrupt callback.
__weak void | HAL_RCCEx_CRS_ExpectedSyncCallback (void)
RCCEx Clock Recovery System Expected SYNC interrupt callback.
__weak void | HAL_RCCEx_CRS_ErrorCallback (uint32_t Error)
RCCEx Clock Recovery System Error interrupt callback.

Detailed Description

Header file of RCC HAL Extended module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_rcc_ex.h.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_rng.h File Reference

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stm32wbxx_hal_rng.h File Reference

Header file of RNG HAL module. More...

#include "stm32wbxx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | RNG_InitTypeDef
struct | __RNG_HandleTypeDef

Defines

#define | RNG_IT_DRDY RNG_SR_DRDY
#define | RNG_IT_CEI RNG_SR_CEIS
#define | RNG_IT_SEI RNG_SR_SEIS
#define | RNG_FLAG_DRDY RNG_SR_DRDY
#define | RNG_FLAG_CECS RNG_SR_CECS
#define | RNG_FLAG_SECS RNG_SR_SECS
#define | RNG_CED_ENABLE 0x00000000U
#define | RNG_CED_DISABLE RNG_CR_CED
#define | HAL_RNG_ERROR_NONE 0x00000000U
#define | HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U
#define | HAL_RNG_ERROR_TIMEOUT 0x00000002U
#define | HAL_RNG_ERROR_BUSY 0x00000004U
#define | HAL_RNG_ERROR_SEED 0x00000008U
#define | HAL_RNG_ERROR_CLOCK 0x00000010U
#define | __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__)
Reset RNG handle state.
#define | __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)
Enables the RNG peripheral.
#define | __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
Disables the RNG peripheral.
#define | __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check the selected RNG flag status.
#define | __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */
Clears the selected RNG flag status.
#define | __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)
Enables the RNG interrupts.
#define | __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
Disables the RNG interrupts.
#define | __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
Checks whether the specified RNG interrupt has occurred or not.
#define | __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
Clear the RNG interrupt status flags.
#define | IS_RNG_IT(IT)
#define | IS_RNG_FLAG(FLAG)
#define | IS_RNG_CED(__MODE__)
Verify the RNG Clock Error Detection mode.

Typedefs

typedef struct __RNG_HandleTypeDef | RNG_HandleTypeDef
typedef void(* | pRNG_CallbackTypeDef )(RNG_HandleTypeDef *hrng)
HAL RNG Callback pointer definition.
typedef void(* | pRNG_ReadyDataCallbackTypeDef )(RNG_HandleTypeDef *hrng, uint32_t random32bit)

Enumerations

enum HAL_RNG_StateTypeDef {
HAL_RNG_STATE_RESET = 0x00U, HAL_RNG_STATE_READY = 0x01U, HAL_RNG_STATE_BUSY = 0x02U, HAL_RNG_STATE_TIMEOUT = 0x03U,
HAL_RNG_STATE_ERROR = 0x04U
}
enum | HAL_RNG_CallbackIDTypeDef { HAL_RNG_ERROR_CB_ID = 0x00U, HAL_RNG_MSPINIT_CB_ID = 0x01U, HAL_RNG_MSPDEINIT_CB_ID = 0x02U }
HAL RNG Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_RNG_Init (RNG_HandleTypeDef *hrng)
Initializes the RNG peripheral and creates the associated handle.
HAL_StatusTypeDef | HAL_RNG_DeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG peripheral.
__weak void | HAL_RNG_MspInit (RNG_HandleTypeDef *hrng)
Initializes the RNG MSP.
__weak void | HAL_RNG_MspDeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG MSP.
HAL_StatusTypeDef | HAL_RNG_RegisterCallback (RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback)
Register a User RNG Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_RNG_UnRegisterCallback (RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID)
Unregister an RNG Callback RNG callabck is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_RNG_RegisterReadyDataCallback (RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback)
Register Data Ready RNG Callback To be used instead of the weak HAL_RNG_ReadyDataCallback() predefined callback.
HAL_StatusTypeDef | HAL_RNG_UnRegisterReadyDataCallback (RNG_HandleTypeDef *hrng)
UnRegister the Data Ready RNG Callback Data Ready RNG Callback is redirected to the weak HAL_RNG_ReadyDataCallback() predefined callback.
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber (RNG_HandleTypeDef *hrng, uint32_t *random32bit)
Generates a 32-bit random number.
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber_IT (RNG_HandleTypeDef *hrng)
Generates a 32-bit random number in interrupt mode.
uint32_t | HAL_RNG_ReadLastRandomNumber (RNG_HandleTypeDef *hrng)
Read latest generated random number.
void | HAL_RNG_IRQHandler (RNG_HandleTypeDef *hrng)
Handles RNG interrupt request.
__weak void | HAL_RNG_ErrorCallback (RNG_HandleTypeDef *hrng)
RNG error callbacks.
__weak void | HAL_RNG_ReadyDataCallback (RNG_HandleTypeDef *hrng, uint32_t random32bit)
Data Ready callback in non-blocking mode.
HAL_RNG_StateTypeDef | HAL_RNG_GetState (RNG_HandleTypeDef *hrng)
Returns the RNG state.
uint32_t | HAL_RNG_GetError (RNG_HandleTypeDef *hrng)
Return the RNG handle error code.

Detailed Description

Header file of RNG HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_rng.h.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_rtc.h File Reference

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stm32wbxx_hal_rtc.h File Reference

Header file of RTC HAL module. More...

#include "stm32wbxx_hal_def.h"
#include "stm32wbxx_ll_exti.h"
#include "stm32wbxx_hal_rtc_ex.h"

Go to the source code of this file.

Data Structures

struct | RTC_InitTypeDef
RTC Configuration Structure definition. More...
struct | RTC_TimeTypeDef
RTC Time structure definition. More...
struct | RTC_DateTypeDef
RTC Date structure definition. More...
struct | RTC_AlarmTypeDef
RTC Alarm structure definition. More...
struct | __RTC_HandleTypeDef
RTC Handle Structure definition. More...

Defines

#define | RTC_HOURFORMAT_24 ((uint32_t)0x00000000U)
#define | RTC_HOURFORMAT_12 ((uint32_t)RTC_CR_FMT)
#define | RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000U)
#define | RTC_OUTPUT_POLARITY_LOW ((uint32_t)RTC_CR_POL)
#define | RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000U)
#define | RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)RTC_OR_ALARMOUTTYPE)
#define | RTC_OUTPUT_REMAP_NONE ((uint32_t)0x00000000U)
#define | RTC_OUTPUT_REMAP_POS1 ((uint32_t)RTC_OR_OUT_RMP)
#define | RTC_HOURFORMAT12_AM ((uint8_t)0x00U)
#define | RTC_HOURFORMAT12_PM ((uint8_t)0x40U)
#define | RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)RTC_CR_SUB1H)
#define | RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)RTC_CR_ADD1H)
#define | RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000U)
#define | RTC_STOREOPERATION_RESET ((uint32_t)0x00000000U)
#define | RTC_STOREOPERATION_SET ((uint32_t)RTC_CR_BKP)
#define | RTC_FORMAT_BIN ((uint32_t)0x000000000U)
#define | RTC_FORMAT_BCD ((uint32_t)0x000000001U)
#define | RTC_MONTH_JANUARY ((uint8_t)0x01U)
#define | RTC_MONTH_FEBRUARY ((uint8_t)0x02U)
#define | RTC_MONTH_MARCH ((uint8_t)0x03U)
#define | RTC_MONTH_APRIL ((uint8_t)0x04U)
#define | RTC_MONTH_MAY ((uint8_t)0x05U)
#define | RTC_MONTH_JUNE ((uint8_t)0x06U)
#define | RTC_MONTH_JULY ((uint8_t)0x07U)
#define | RTC_MONTH_AUGUST ((uint8_t)0x08U)
#define | RTC_MONTH_SEPTEMBER ((uint8_t)0x09U)
#define | RTC_MONTH_OCTOBER ((uint8_t)0x10U)
#define | RTC_MONTH_NOVEMBER ((uint8_t)0x11U)
#define | RTC_MONTH_DECEMBER ((uint8_t)0x12U)
#define | RTC_WEEKDAY_MONDAY ((uint8_t)0x01U)
#define | RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U)
#define | RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U)
#define | RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U)
#define | RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U)
#define | RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U)
#define | RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U)
#define | RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000U)
#define | RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL
#define | RTC_ALARMMASK_NONE ((uint32_t)0x00000000U)
#define | RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define | RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
#define | RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
#define | RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
#define | RTC_ALARMMASK_ALL
#define | RTC_ALARM_A RTC_CR_ALRAE
#define | RTC_ALARM_B RTC_CR_ALRBE
#define | RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000U)
#define | RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0
#define | RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1
#define | RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1))
#define | RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2
#define | RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2))
#define | RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t) (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2))
#define | RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2))
#define | RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3
#define | RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3))
#define | RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t) (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3))
#define | RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3))
#define | RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t) (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3))
#define | RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3))
#define | RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t) (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3))
#define | RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS
#define | RTC_IT_TS ((uint32_t)RTC_CR_TSIE)
#define | RTC_IT_WUT ((uint32_t)RTC_CR_WUTIE)
#define | RTC_IT_ALRA ((uint32_t)RTC_CR_ALRAIE)
#define | RTC_IT_ALRB ((uint32_t)RTC_CR_ALRBIE)
#define | RTC_IT_TAMP ((uint32_t)RTC_TAMPCR_TAMPIE)
#define | RTC_IT_TAMP1 ((uint32_t)RTC_TAMPCR_TAMP1IE)
#define | RTC_IT_TAMP2 ((uint32_t)RTC_TAMPCR_TAMP2IE)
#define | RTC_FLAG_RECALPF ((uint32_t)RTC_ISR_RECALPF)
#define | RTC_FLAG_TAMP2F ((uint32_t)RTC_ISR_TAMP2F)
#define | RTC_FLAG_TAMP1F ((uint32_t)RTC_ISR_TAMP1F)
#define | RTC_FLAG_TSOVF ((uint32_t)RTC_ISR_TSOVF)
#define | RTC_FLAG_TSF ((uint32_t)RTC_ISR_TSF)
#define | RTC_FLAG_ITSF ((uint32_t)RTC_ISR_ITSF)
#define | RTC_FLAG_WUTF ((uint32_t)RTC_ISR_WUTF)
#define | RTC_FLAG_ALRBF ((uint32_t)RTC_ISR_ALRBF)
#define | RTC_FLAG_ALRAF ((uint32_t)RTC_ISR_ALRAF)
#define | RTC_FLAG_INITF ((uint32_t)RTC_ISR_INITF)
#define | RTC_FLAG_RSF ((uint32_t)RTC_ISR_RSF)
#define | RTC_FLAG_INITS ((uint32_t)RTC_ISR_INITS)
#define | RTC_FLAG_SHPF ((uint32_t)RTC_ISR_SHPF)
#define | RTC_FLAG_WUTWF ((uint32_t)RTC_ISR_WUTWF)
#define | RTC_FLAG_ALRBWF ((uint32_t)RTC_ISR_ALRBWF)
#define | RTC_FLAG_ALRAWF ((uint32_t)RTC_ISR_ALRAWF)
#define | __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__)
Reset RTC handle state.
#define | __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)
Disable the write protection for RTC registers.
#define | __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)
Enable the write protection for RTC registers.
#define | __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
Enable the RTC ALARMA peripheral.
#define | __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
Disable the RTC ALARMA peripheral.
#define | __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
Enable the RTC ALARMB peripheral.
#define | __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
Disable the RTC ALARMB peripheral.
#define | __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) != 0U)? 1U : 0U)
Check whether the specified RTC Alarm interrupt has occurred or not.
#define | __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
Check whether the specified RTC Alarm interrupt has been enabled or not.
#define | __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U)
Get the selected RTC Alarm's flag status.
#define | __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT) | ((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Alarm's pending flags.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable interrupt on the RTC Alarm associated Exti line by core 1.
#define | __HAL_RTC_ALARM_EXTIC2_ENABLE_IT() (EXTI->C2IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable interrupt on the RTC Alarm associated Exti line by core 2.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable interrupt on the RTC Alarm associated Exti line by core 1.
#define | __HAL_RTC_ALARM_EXTIC2_DISABLE_IT() (EXTI->C2IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable interrupt on the RTC Alarm associated Exti line by core 2.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable event on the RTC Alarm associated Exti line by core 1.
#define | __HAL_RTC_ALARM_EXTIC2_ENABLE_EVENT() (EXTI->C2EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable event on the RTC Alarm associated Exti line by core 2.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable event on the RTC Alarm associated Exti line by core 1.
#define | __HAL_RTC_ALARM_EXTIC2_DISABLE_EVENT() (EXTI->C2EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable event on the RTC Alarm associated Exti line by core 2.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
Enable rising edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
Disable rising edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
#define | __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR1 & RTC_EXTI_LINE_ALARM_EVENT)
Check whether the RTC Alarm associated Exti line interrupt flag is set or notby core 1.
#define | __HAL_RTC_ALARM_EXTIC2_GET_FLAG() (EXTI->PR2 & RTC_EXTI_LINE_ALARM_EVENT)
Check whether the RTC Alarm associated Exti line interrupt flag is set or not by core 2.
#define | __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR1 = (RTC_EXTI_LINE_ALARM_EVENT))
Clear the RTC Alarm associated Exti line flag.
#define | __HAL_RTC_ALARM_EXTIC2_CLEAR_FLAG() (EXTI->PR2 = (RTC_EXTI_LINE_ALARM_EVENT))
Clear the RTC Alarm associated Exti line flag.
#define | __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_ALARM_EVENT)
Generate a Software interrupt on RTC Alarm associated Exti line.
#define | RTC_TR_RESERVED_MASK
#define | RTC_DR_RESERVED_MASK
#define | RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU)
#define | RTC_RSF_MASK ((uint32_t)~(RTC_ISR_INIT | RTC_ISR_RSF))
#define | RTC_TIMEOUT_VALUE 1000U
#define | RTC_EXTI_LINE_ALARM_EVENT (LL_EXTI_LINE_17)
#define | IS_RTC_HOUR_FORMAT(FORMAT)
#define | IS_RTC_OUTPUT_POL(POL)
#define | IS_RTC_OUTPUT_TYPE(TYPE)
#define | IS_RTC_OUTPUT_REMAP(REMAP)
#define | IS_RTC_HOURFORMAT12(PM)
#define | IS_RTC_DAYLIGHT_SAVING(SAVE)
#define | IS_RTC_STORE_OPERATION(OPERATION)
#define | IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
#define | IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99U)
#define | IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1U) && ((MONTH) <= (uint32_t)12U))
#define | IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1U) && ((DATE) <= (uint32_t)31U))
#define | IS_RTC_WEEKDAY(WEEKDAY)
#define | IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t)0U) && ((DATE) <= (uint32_t)31U))
#define | IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY)
#define | IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL)
#define | IS_RTC_ALARM_MASK(MASK) (((MASK) & ~(RTC_ALARMMASK_ALL)) == 0U)
#define | IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
#define | IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS)
#define | IS_RTC_ALARM_SUB_SECOND_MASK(MASK)
#define | IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FU)
#define | IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFFU)
#define | IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0U) && ((HOUR) <= (uint32_t)12U))
#define | IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23U)
#define | IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59U)
#define | IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59U)

Typedefs

typedef struct __RTC_HandleTypeDef | RTC_HandleTypeDef
RTC Handle Structure definition.
typedef void(* | pRTC_CallbackTypeDef )(RTC_HandleTypeDef *hrtc)
HAL RTC Callback pointer definition.

Enumerations

enum HAL_RTCStateTypeDef {
HAL_RTC_STATE_RESET = 0x00U, HAL_RTC_STATE_READY = 0x01U, HAL_RTC_STATE_BUSY = 0x02U, HAL_RTC_STATE_TIMEOUT = 0x03U,
HAL_RTC_STATE_ERROR = 0x04U
}
HAL State structures definition. More...
enum HAL_RTC_CallbackIDTypeDef {
HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00U, HAL_RTC_ALARM_B_EVENT_CB_ID = 0x01U, HAL_RTC_TIMESTAMP_EVENT_CB_ID = 0x02U, HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03U,
HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04U, HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05U, HAL_RTC_TAMPER3_EVENT_CB_ID = 0x06U, HAL_RTC_MSPINIT_CB_ID = 0x0EU,
HAL_RTC_MSPDEINIT_CB_ID = 0x0FU
}
HAL LPTIM Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_RTC_Init (RTC_HandleTypeDef *hrtc)
Initialize the RTC peripheral.
HAL_StatusTypeDef | HAL_RTC_DeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC peripheral.
__weak void | HAL_RTC_MspInit (RTC_HandleTypeDef *hrtc)
Initialize the RTC MSP.
__weak void | HAL_RTC_MspDeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC MSP.
HAL_StatusTypeDef | HAL_RTC_RegisterCallback (RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback)
Register a User RTC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_RTC_UnRegisterCallback (RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID)
Unregister an RTC Callback RTC callabck is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_RTC_SetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Set RTC current time.
HAL_StatusTypeDef | HAL_RTC_GetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Get RTC current time.
HAL_StatusTypeDef | HAL_RTC_SetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Set RTC current date.
HAL_StatusTypeDef | HAL_RTC_GetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Get RTC current date.
HAL_StatusTypeDef | HAL_RTC_SetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_SetAlarm_IT (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm with Interrupt.
HAL_StatusTypeDef | HAL_RTC_DeactivateAlarm (RTC_HandleTypeDef *hrtc, uint32_t Alarm)
Deactivate the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_GetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
Get the RTC Alarm value and masks.
void | HAL_RTC_AlarmIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Alarm interrupt request.
HAL_StatusTypeDef | HAL_RTC_PollForAlarmAEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle AlarmA Polling request.
__weak void | HAL_RTC_AlarmAEventCallback (RTC_HandleTypeDef *hrtc)
Alarm A callback.
HAL_StatusTypeDef | HAL_RTC_WaitForSynchro (RTC_HandleTypeDef *hrtc)
Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.
HAL_RTCStateTypeDef | HAL_RTC_GetState (RTC_HandleTypeDef *hrtc)
Return the RTC handle state.
HAL_StatusTypeDef | RTC_EnterInitMode (RTC_HandleTypeDef *hrtc)
Enter the RTC Initialization mode.
uint8_t | RTC_ByteToBcd2 (uint8_t Value)
Convert a 2 digit decimal to BCD format.
uint8_t | RTC_Bcd2ToByte (uint8_t Value)
Convert from 2 digit BCD to Binary.

Detailed Description

Header file of RTC HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_rtc.h.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_rtc_ex.h File Reference

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Data Structures | Defines | Functions
stm32wbxx_hal_rtc_ex.h File Reference

Header file of RTC HAL Extended module. More...

#include "stm32wbxx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | RTC_TamperTypeDef
RTC Tamper structure definition. More...

Defines

#define | RTC_OUTPUT_DISABLE ((uint32_t)0x00000000U)
#define | RTC_OUTPUT_ALARMA ((uint32_t)RTC_CR_OSEL_0)
#define | RTC_OUTPUT_ALARMB ((uint32_t)RTC_CR_OSEL_1)
#define | RTC_OUTPUT_WAKEUP ((uint32_t)RTC_CR_OSEL)
#define | RTC_BKP_DR0 ((uint32_t)0x00000000U)
#define | RTC_BKP_DR1 ((uint32_t)0x00000001U)
#define | RTC_BKP_DR2 ((uint32_t)0x00000002U)
#define | RTC_BKP_DR3 ((uint32_t)0x00000003U)
#define | RTC_BKP_DR4 ((uint32_t)0x00000004U)
#define | RTC_BKP_DR5 ((uint32_t)0x00000005U)
#define | RTC_BKP_DR6 ((uint32_t)0x00000006U)
#define | RTC_BKP_DR7 ((uint32_t)0x00000007U)
#define | RTC_BKP_DR8 ((uint32_t)0x00000008U)
#define | RTC_BKP_DR9 ((uint32_t)0x00000009U)
#define | RTC_BKP_DR10 ((uint32_t)0x0000000AU)
#define | RTC_BKP_DR11 ((uint32_t)0x0000000BU)
#define | RTC_BKP_DR12 ((uint32_t)0x0000000CU)
#define | RTC_BKP_DR13 ((uint32_t)0x0000000DU)
#define | RTC_BKP_DR14 ((uint32_t)0x0000000EU)
#define | RTC_BKP_DR15 ((uint32_t)0x0000000FU)
#define | RTC_BKP_DR16 ((uint32_t)0x00000010U)
#define | RTC_BKP_DR17 ((uint32_t)0x00000011U)
#define | RTC_BKP_DR18 ((uint32_t)0x00000012U)
#define | RTC_BKP_DR19 ((uint32_t)0x00000013U)
#define | RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000U)
#define | RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE
#define | RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000U)
#define | RTC_TAMPER_1 RTC_TAMPCR_TAMP1E
#define | RTC_TAMPER_2 RTC_TAMPCR_TAMP2E
#define | RTC_TAMPER_3 RTC_TAMPCR_TAMP3E
#define | RTC_TAMPER1_INTERRUPT RTC_TAMPCR_TAMP1IE
#define | RTC_TAMPER2_INTERRUPT RTC_TAMPCR_TAMP2IE
#define | RTC_TAMPER3_INTERRUPT RTC_TAMPCR_TAMP3IE
#define | RTC_ALL_TAMPER_INTERRUPT RTC_TAMPCR_TAMPIE
#define | RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000U)
#define | RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002U)
#define | RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE
#define | RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE
#define | RTC_TAMPER_ERASE_BACKUP_ENABLE ((uint32_t)0x00000000U)
#define | RTC_TAMPER_ERASE_BACKUP_DISABLE ((uint32_t)0x00020000U)
#define | RTC_TAMPERMASK_FLAG_DISABLE ((uint32_t)0x00000000U)
#define | RTC_TAMPERMASK_FLAG_ENABLE ((uint32_t)0x00040000U)
#define | RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000U)
#define | RTC_TAMPERFILTER_2SAMPLE RTC_TAMPCR_TAMPFLT_0
#define | RTC_TAMPERFILTER_4SAMPLE RTC_TAMPCR_TAMPFLT_1
#define | RTC_TAMPERFILTER_8SAMPLE RTC_TAMPCR_TAMPFLT
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000U)
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 RTC_TAMPCR_TAMPFREQ_0
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 RTC_TAMPCR_TAMPFREQ_1
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 ((uint32_t) (RTC_TAMPCR_TAMPFREQ_0 | RTC_TAMPCR_TAMPFREQ_1))
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 RTC_TAMPCR_TAMPFREQ_2
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 ((uint32_t) (RTC_TAMPCR_TAMPFREQ_0 | RTC_TAMPCR_TAMPFREQ_2))
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 ((uint32_t) (RTC_TAMPCR_TAMPFREQ_1 | RTC_TAMPCR_TAMPFREQ_2))
#define | RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256
#define | RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000U)
#define | RTC_TAMPERPRECHARGEDURATION_2RTCCLK RTC_TAMPCR_TAMPPRCH_0
#define | RTC_TAMPERPRECHARGEDURATION_4RTCCLK RTC_TAMPCR_TAMPPRCH_1
#define | RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)(RTC_TAMPCR_TAMPPRCH_0 | RTC_TAMPCR_TAMPPRCH_1))
#define | RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_TAMPCR_TAMPTS
#define | RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000U)
#define | RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000U)
#define | RTC_TAMPER_PULLUP_DISABLE RTC_TAMPCR_TAMPPUDIS
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000U)
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1
#define | RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t) (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1))
#define | RTC_WAKEUPCLOCK_CK_SPRE_16BITS RTC_CR_WUCKSEL_2
#define | RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t) (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2))
#define | RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000U)
#define | RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16
#define | RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8
#define | RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP
#define | RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000U)
#define | RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000U)
#define | RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL
#define | RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000U)
#define | RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S
#define | RTC_IT_TAMP3 ((uint32_t)RTC_TAMPCR_TAMP3IE)
#define | RTC_FLAG_TAMP3F ((uint32_t)RTC_ISR_TAMP3F)
#define | __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
Enable the RTC WakeUp Timer peripheral.
#define | __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
Disable the RTC WakeUp Timer peripheral.
#define | __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC WakeUpTimer interrupt.
#define | __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC WakeUpTimer interrupt.
#define | __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != 0U) ? 1U : 0U)
Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
#define | __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
#define | __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)
Get the selected RTC WakeUpTimer's flag status.
#define | __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Wake Up timer's pending flags.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable interrupt on the RTC WakeUp Timer associated Exti line of core 1.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable interrupt on the RTC WakeUp Timer associated Exti line of core 1.
#define | __HAL_RTC_WAKEUPTIMER_EXTIC2_ENABLE_IT() (EXTI->C2IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable interrupt on the RTC WakeUp Timer associated Exti line of core 2.
#define | __HAL_RTC_WAKEUPTIMER_EXTIC2_DISABLE_IT() (EXTI->C2IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable interrupt on the RTC WakeUp Timer associated Exti line of core 2.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable event on the RTC WakeUp Timer associated Exti line of core 1.
#define | __HAL_RTC_WAKEUPTIMER_EXTIC2_ENABLE_EVENT() (EXTI->C2EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable event on the RTC WakeUp Timer associated Exti line of core 2.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable event on the RTC WakeUp Timer associated Exti line of core 1.
#define | __HAL_RTC_WAKEUPTIMER_EXTIC2_DISABLE_EVENT() (EXTI->C2EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable event on the RTC WakeUp Timer associated Exti line of core 2.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not of core 1.
#define | __HAL_RTC_WAKEUPTIMER_EXTIC2_GET_FLAG() (EXTI->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not of core 2.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Clear the RTC WakeUp Timer associated Exti line flag of core 1.
#define | __HAL_RTC_WAKEUPTIMER_EXTIC2_CLEAR_FLAG() (EXTI->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Clear the RTC WakeUp Timer associated Exti line flag of core 2.
#define | __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.
#define | __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
Enable the RTC TimeStamp peripheral.
#define | __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
Disable the RTC TimeStamp peripheral.
#define | __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
Enable the RTC TimeStamp interrupt.
#define | __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
Disable the RTC TimeStamp interrupt.
#define | __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != 0U) ? 1U : 0U)
Check whether the specified RTC TimeStamp interrupt has occurred or not.
#define | __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
Check whether the specified RTC Time Stamp interrupt has been enabled or not.
#define | __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)
Get the selected RTC TimeStamp's flag status.
#define | __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Time Stamp's pending flags.
#define | __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E))
Enable the RTC Tamper1 input detection.
#define | __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E))
Disable the RTC Tamper1 input detection.
#define | __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E))
Enable the RTC Tamper2 input detection.
#define | __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E))
Disable the RTC Tamper2 input detection.
#define | __HAL_RTC_TAMPER3_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E))
Enable the RTC Tamper3 input detection.
#define | __HAL_RTC_TAMPER3_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E))
Disable the RTC Tamper3 input detection.
#define | __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__))
Enable the RTC Tamper interrupt.
#define | __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__))
Disable the RTC Tamper interrupt.
#define | __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)
Check whether the specified RTC Tamper interrupt has occurred or not.
#define | __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
Check whether the specified RTC Tamper interrupt has been enabled or not.
#define | __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)
Get the selected RTC Tamper's flag status.
#define | __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Tamper's pending flags.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE))
Enable the RTC internal TimeStamp peripheral.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE))
Disable the RTC internal TimeStamp peripheral.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)
Get the selected RTC Internal Time Stamp's flag status.
#define | __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
Clear the RTC Internal Time Stamp's pending flags.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable interrupt on the RTC Tamper and Timestamp associated Exti line of core 1.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_ENABLE_IT() (EXTI->C2IMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable interrupt on the RTC Tamper and Timestamp associated Exti line of core 2.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable interrupt on the RTC Tamper and Timestamp associated Exti line of core 1.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_DISABLE_IT() (EXTI->C2IMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable interrupt on the RTC Tamper and Timestamp associated Exti line of core 2.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable event on the RTC Tamper and Timestamp associated Exti line of core 1.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_ENABLE_EVENT() (EXTI->C2EMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable event on the RTC Tamper and Timestamp associated Exti line of core 2.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable event on the RTC Tamper and Timestamp associated Exti line of core 1.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_DISABLE_EVENT() (EXTI->C2EMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable event on the RTC Tamper and Timestamp associated Exti line of core 2.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE()
Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR1 & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not of core 1.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_GET_FLAG() (EXTI->PR2 & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not of core 2.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI->PR1 = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Clear the RTC Tamper and Timestamp associated Exti line flag of core 1.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_CLEAR_FLAG() (EXTI->PR1 = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Clear the RTC Tamper and Timestamp associated Exti line flag of core 2.
#define | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line.
#define | __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
Enable the RTC calibration output.
#define | __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
Disable the calibration output.
#define | __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
Enable the clock reference detection.
#define | __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
Disable the clock reference detection.
#define | __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U)
Get the selected RTC shift operation's flag status.
#define | RTC_FLAGS_MASK
#define | RTC_TAMPCR_TAMPXE ((uint32_t) (RTC_TAMPCR_TAMP3E | RTC_TAMPCR_TAMP2E | RTC_TAMPCR_TAMP1E))
#define | RTC_TAMPCR_TAMPXIE
#define | RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT (EXTI_IMR1_IM18)
#define | RTC_EXTI_LINE_WAKEUPTIMER_EVENT (EXTI_IMR1_IM19)
#define | IS_RTC_OUTPUT(OUTPUT)
#define | IS_RTC_BKP(BKP) ((BKP) < (uint32_t) RTC_BKP_NUMBER)
#define | IS_TIMESTAMP_EDGE(EDGE)
#define | IS_RTC_TAMPER(TAMPER) ((((TAMPER) & ((uint32_t)(0xFFFFFFFFU ^ RTC_TAMPCR_TAMPXE))) == 0x00U) && ((TAMPER) != 0U))
#define | IS_RTC_TAMPER_INTERRUPT(INTERRUPT) ((((INTERRUPT) & (uint32_t)(0xFFFFFFFFU ^ RTC_TAMPCR_TAMPXIE)) == 0x00U) && ((INTERRUPT) != 0U))
#define | IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
#define | IS_RTC_TAMPER_TRIGGER(TRIGGER)
#define | IS_RTC_TAMPER_ERASE_MODE(MODE)
#define | IS_RTC_TAMPER_MASKFLAG_STATE(STATE)
#define | IS_RTC_TAMPER_FILTER(FILTER)
#define | IS_RTC_TAMPER_SAMPLING_FREQ(FREQ)
#define | IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION)
#define | IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION)
#define | IS_RTC_TAMPER_PULLUP_STATE(STATE)
#define | IS_RTC_WAKEUP_CLOCK(CLOCK)
#define | IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= RTC_WUTR_WUT)
#define | IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD)
#define | IS_RTC_SMOOTH_CALIB_PLUS(PLUS)
#define | IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= RTC_CALR_CALM)
#define | IS_RTC_SHIFT_ADD1S(SEL)
#define | IS_RTC_SHIFT_SUBFS(FS) ((FS) <= RTC_SHIFTR_SUBFS)
#define | IS_RTC_CALIB_OUTPUT(OUTPUT)

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp_IT (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp with Interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivate TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Set Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivate Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_GetTimeStamp (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
Get the RTC TimeStamp value.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper_IT (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper with interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTamper (RTC_HandleTypeDef *hrtc, uint32_t Tamper)
Deactivate Tamper.
void | HAL_RTCEx_TamperTimeStampIRQHandler (RTC_HandleTypeDef *hrtc)
Handle TimeStamp interrupt request.
__weak void | HAL_RTCEx_Tamper1EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 1 callback.
__weak void | HAL_RTCEx_Tamper2EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 2 callback.
__weak void | HAL_RTCEx_Tamper3EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 3 callback.
__weak void | HAL_RTCEx_TimeStampEventCallback (RTC_HandleTypeDef *hrtc)
TimeStamp callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForTimeStampEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle TimeStamp polling request.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper1Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper 1 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper2Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper 2 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper3Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper 3 Polling.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer_IT (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer with interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateWakeUpTimer (RTC_HandleTypeDef *hrtc)
Deactivate wake up timer counter.
uint32_t | HAL_RTCEx_GetWakeUpTimer (RTC_HandleTypeDef *hrtc)
Get wake up timer counter.
void | HAL_RTCEx_WakeUpTimerIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Wake Up Timer interrupt request.
__weak void | HAL_RTCEx_WakeUpTimerEventCallback (RTC_HandleTypeDef *hrtc)
Wake Up Timer callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForWakeUpTimerEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Wake Up Timer Polling.
void | HAL_RTCEx_BKUPWrite (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
Write a data in a specified RTC Backup data register.
uint32_t | HAL_RTCEx_BKUPRead (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
Reads data from the specified RTC Backup data Register.
HAL_StatusTypeDef | HAL_RTCEx_SetSmoothCalib (RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
Set the Smooth calibration parameters.
HAL_StatusTypeDef | HAL_RTCEx_SetSynchroShift (RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
Configure the Synchronization Shift Control Settings.
HAL_StatusTypeDef | HAL_RTCEx_SetCalibrationOutPut (RTC_HandleTypeDef *hrtc, uint32_t CalibOutput)
Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_DeactivateCalibrationOutPut (RTC_HandleTypeDef *hrtc)
Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_SetRefClock (RTC_HandleTypeDef *hrtc)
Enable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateRefClock (RTC_HandleTypeDef *hrtc)
Disable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_EnableBypassShadow (RTC_HandleTypeDef *hrtc)
Enable the Bypass Shadow feature.
HAL_StatusTypeDef | HAL_RTCEx_DisableBypassShadow (RTC_HandleTypeDef *hrtc)
Disable the Bypass Shadow feature.
__weak void | HAL_RTCEx_AlarmBEventCallback (RTC_HandleTypeDef *hrtc)
Alarm B callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForAlarmBEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Alarm B Polling request.

Detailed Description

Header file of RTC HAL Extended module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_rtc_ex.h.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_sai.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32wbxx_hal_sai.h File Reference

Header file of SAI HAL module. More...

#include "stm32wbxx_hal_def.h"
#include "stm32wbxx_hal_sai_ex.h"

Go to the source code of this file.

Data Structures

struct | SAI_PdmInitTypeDef
struct | SAI_InitTypeDef
struct | SAI_FrameInitTypeDef
struct | SAI_SlotInitTypeDef
struct | __SAI_HandleTypeDef

Defines

#define | HAL_SAI_ERROR_NONE 0x00000000U
#define | HAL_SAI_ERROR_OVR 0x00000001U
#define | HAL_SAI_ERROR_UDR 0x00000002U
#define | HAL_SAI_ERROR_AFSDET 0x00000004U
#define | HAL_SAI_ERROR_LFSDET 0x00000008U
#define | HAL_SAI_ERROR_CNREADY 0x00000010U
#define | HAL_SAI_ERROR_WCKCFG 0x00000020U
#define | HAL_SAI_ERROR_TIMEOUT 0x00000040U
#define | HAL_SAI_ERROR_DMA 0x00000080U
#define | HAL_SAI_ERROR_INVALID_CALLBACK 0x00000100U
#define | SAI_SYNCEXT_DISABLE 0U
#define | SAI_SYNCEXT_OUTBLOCKA_ENABLE 1U
#define | SAI_SYNCEXT_OUTBLOCKB_ENABLE 2U
#define | SAI_MCK_OUTPUT_DISABLE 0x00000000U
#define | SAI_MCK_OUTPUT_ENABLE SAI_xCR1_MCKEN
#define | SAI_I2S_STANDARD 0U
#define | SAI_I2S_MSBJUSTIFIED 1U
#define | SAI_I2S_LSBJUSTIFIED 2U
#define | SAI_PCM_LONG 3U
#define | SAI_PCM_SHORT 4U
#define | SAI_PROTOCOL_DATASIZE_16BIT 0U
#define | SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1U
#define | SAI_PROTOCOL_DATASIZE_24BIT 2U
#define | SAI_PROTOCOL_DATASIZE_32BIT 3U
#define | SAI_AUDIO_FREQUENCY_192K 192000U
#define | SAI_AUDIO_FREQUENCY_96K 96000U
#define | SAI_AUDIO_FREQUENCY_48K 48000U
#define | SAI_AUDIO_FREQUENCY_44K 44100U
#define | SAI_AUDIO_FREQUENCY_32K 32000U
#define | SAI_AUDIO_FREQUENCY_22K 22050U
#define | SAI_AUDIO_FREQUENCY_16K 16000U
#define | SAI_AUDIO_FREQUENCY_11K 11025U
#define | SAI_AUDIO_FREQUENCY_8K 8000U
#define | SAI_AUDIO_FREQUENCY_MCKDIV 0U
#define | SAI_MCK_OVERSAMPLING_DISABLE 0x00000000U
#define | SAI_MCK_OVERSAMPLING_ENABLE SAI_xCR1_OSR
#define | SAI_PDM_CLOCK1_ENABLE SAI_PDMCR_CKEN1
#define | SAI_PDM_CLOCK2_ENABLE SAI_PDMCR_CKEN2
#define | SAI_MODEMASTER_TX 0x00000000U
#define | SAI_MODEMASTER_RX SAI_xCR1_MODE_0
#define | SAI_MODESLAVE_TX SAI_xCR1_MODE_1
#define | SAI_MODESLAVE_RX (SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0)
#define | SAI_FREE_PROTOCOL 0x00000000U
#define | SAI_SPDIF_PROTOCOL SAI_xCR1_PRTCFG_0
#define | SAI_AC97_PROTOCOL SAI_xCR1_PRTCFG_1
#define | SAI_DATASIZE_8 SAI_xCR1_DS_1
#define | SAI_DATASIZE_10 (SAI_xCR1_DS_1 | SAI_xCR1_DS_0)
#define | SAI_DATASIZE_16 SAI_xCR1_DS_2
#define | SAI_DATASIZE_20 (SAI_xCR1_DS_2 | SAI_xCR1_DS_0)
#define | SAI_DATASIZE_24 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1)
#define | SAI_DATASIZE_32 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0)
#define | SAI_FIRSTBIT_MSB 0x00000000U
#define | SAI_FIRSTBIT_LSB SAI_xCR1_LSBFIRST
#define | SAI_CLOCKSTROBING_FALLINGEDGE 0U
#define | SAI_CLOCKSTROBING_RISINGEDGE 1U
#define | SAI_ASYNCHRONOUS 0U
#define | SAI_SYNCHRONOUS 1U
#define | SAI_SYNCHRONOUS_EXT_SAI1 2U
#define | SAI_SYNCHRONOUS_EXT_SAI2 3U
#define | SAI_OUTPUTDRIVE_DISABLE 0x00000000U
#define | SAI_OUTPUTDRIVE_ENABLE SAI_xCR1_OUTDRIV
#define | SAI_MASTERDIVIDER_ENABLE 0x00000000U
#define | SAI_MASTERDIVIDER_DISABLE SAI_xCR1_NODIV
#define | SAI_FS_STARTFRAME 0x00000000U
#define | SAI_FS_CHANNEL_IDENTIFICATION SAI_xFRCR_FSDEF
#define | SAI_FS_ACTIVE_LOW 0x00000000U
#define | SAI_FS_ACTIVE_HIGH SAI_xFRCR_FSPOL
#define | SAI_FS_FIRSTBIT 0x00000000U
#define | SAI_FS_BEFOREFIRSTBIT SAI_xFRCR_FSOFF
#define | SAI_SLOTSIZE_DATASIZE 0x00000000U
#define | SAI_SLOTSIZE_16B SAI_xSLOTR_SLOTSZ_0
#define | SAI_SLOTSIZE_32B SAI_xSLOTR_SLOTSZ_1
#define | SAI_SLOT_NOTACTIVE 0x00000000U
#define | SAI_SLOTACTIVE_0 0x00000001U
#define | SAI_SLOTACTIVE_1 0x00000002U
#define | SAI_SLOTACTIVE_2 0x00000004U
#define | SAI_SLOTACTIVE_3 0x00000008U
#define | SAI_SLOTACTIVE_4 0x00000010U
#define | SAI_SLOTACTIVE_5 0x00000020U
#define | SAI_SLOTACTIVE_6 0x00000040U
#define | SAI_SLOTACTIVE_7 0x00000080U
#define | SAI_SLOTACTIVE_8 0x00000100U
#define | SAI_SLOTACTIVE_9 0x00000200U
#define | SAI_SLOTACTIVE_10 0x00000400U
#define | SAI_SLOTACTIVE_11 0x00000800U
#define | SAI_SLOTACTIVE_12 0x00001000U
#define | SAI_SLOTACTIVE_13 0x00002000U
#define | SAI_SLOTACTIVE_14 0x00004000U
#define | SAI_SLOTACTIVE_15 0x00008000U
#define | SAI_SLOTACTIVE_ALL 0x0000FFFFU
#define | SAI_STEREOMODE 0x00000000U
#define | SAI_MONOMODE SAI_xCR1_MONO
#define | SAI_OUTPUT_NOTRELEASED 0x00000000U
#define | SAI_OUTPUT_RELEASED SAI_xCR2_TRIS
#define | SAI_FIFOTHRESHOLD_EMPTY 0x00000000U
#define | SAI_FIFOTHRESHOLD_1QF SAI_xCR2_FTH_0
#define | SAI_FIFOTHRESHOLD_HF SAI_xCR2_FTH_1
#define | SAI_FIFOTHRESHOLD_3QF (SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0)
#define | SAI_FIFOTHRESHOLD_FULL SAI_xCR2_FTH_2
#define | SAI_NOCOMPANDING 0x00000000U
#define | SAI_ULAW_1CPL_COMPANDING SAI_xCR2_COMP_1
#define | SAI_ALAW_1CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0)
#define | SAI_ULAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_CPL)
#define | SAI_ALAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL)
#define | SAI_ZERO_VALUE 0x00000000U
#define | SAI_LAST_SENT_VALUE SAI_xCR2_MUTEVAL
#define | SAI_IT_OVRUDR SAI_xIMR_OVRUDRIE
#define | SAI_IT_MUTEDET SAI_xIMR_MUTEDETIE
#define | SAI_IT_WCKCFG SAI_xIMR_WCKCFGIE
#define | SAI_IT_FREQ SAI_xIMR_FREQIE
#define | SAI_IT_CNRDY SAI_xIMR_CNRDYIE
#define | SAI_IT_AFSDET SAI_xIMR_AFSDETIE
#define | SAI_IT_LFSDET SAI_xIMR_LFSDETIE
#define | SAI_FLAG_OVRUDR SAI_xSR_OVRUDR
#define | SAI_FLAG_MUTEDET SAI_xSR_MUTEDET
#define | SAI_FLAG_WCKCFG SAI_xSR_WCKCFG
#define | SAI_FLAG_FREQ SAI_xSR_FREQ
#define | SAI_FLAG_CNRDY SAI_xSR_CNRDY
#define | SAI_FLAG_AFSDET SAI_xSR_AFSDET
#define | SAI_FLAG_LFSDET SAI_xSR_LFSDET
#define | SAI_FIFOSTATUS_EMPTY 0x00000000U
#define | SAI_FIFOSTATUS_LESS1QUARTERFULL 0x00010000U
#define | SAI_FIFOSTATUS_1QUARTERFULL 0x00020000U
#define | SAI_FIFOSTATUS_HALFFULL 0x00030000U
#define | SAI_FIFOSTATUS_3QUARTERFULL 0x00040000U
#define | SAI_FIFOSTATUS_FULL 0x00050000U
#define | __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__)
Reset SAI handle state.
#define | __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
Enable the specified SAI interrupts.
#define | __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))
Disable the specified SAI interrupts.
#define | __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified SAI interrupt source is enabled or not.
#define | __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Check whether the specified SAI flag is set or not.
#define | __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
Clear the specified SAI pending flag.
#define | __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN)
Enable SAI.
#define | __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN)
Disable SAI.
#define | IS_SAI_BLOCK_SYNCEXT(STATE)
#define | IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL)
#define | IS_SAI_PROTOCOL_DATASIZE(DATASIZE)
#define | IS_SAI_AUDIO_FREQUENCY(AUDIO)
#define | IS_SAI_BLOCK_MCK_OVERSAMPLING(VALUE)
#define | IS_SAI_PDM_MIC_PAIRS_NUMBER(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 3U))
#define | IS_SAI_PDM_CLOCK_ENABLE(CLOCK)
#define | IS_SAI_BLOCK_MODE(MODE)
#define | IS_SAI_BLOCK_PROTOCOL(PROTOCOL)
#define | IS_SAI_BLOCK_DATASIZE(DATASIZE)
#define | IS_SAI_BLOCK_FIRST_BIT(BIT)
#define | IS_SAI_BLOCK_CLOCK_STROBING(CLOCK)
#define | IS_SAI_BLOCK_SYNCHRO(SYNCHRO)
#define | IS_SAI_BLOCK_MCK_OUTPUT(VALUE)
#define | IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE)
#define | IS_SAI_BLOCK_NODIVIDER(NODIVIDER)
#define | IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63U)
#define | IS_SAI_BLOCK_MUTE_VALUE(VALUE)
#define | IS_SAI_BLOCK_COMPANDING_MODE(MODE)
#define | IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD)
#define | IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE)
#define | IS_SAI_MONO_STEREO_MODE(MODE)
#define | IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) <= SAI_SLOTACTIVE_ALL)
#define | IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1U <= (NUMBER)) && ((NUMBER) <= 16U))
#define | IS_SAI_BLOCK_SLOT_SIZE(SIZE)
#define | IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24U)
#define | IS_SAI_BLOCK_FS_OFFSET(OFFSET)
#define | IS_SAI_BLOCK_FS_POLARITY(POLARITY)
#define | IS_SAI_BLOCK_FS_DEFINITION(DEFINITION)
#define | IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 63U)
#define | IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8U <= (LENGTH)) && ((LENGTH) <= 256U))
#define | IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1U <= (LENGTH)) && ((LENGTH) <= 128U))

Typedefs

typedef void(* | SAIcallback )(void)
SAI Callback prototype.
typedef struct __SAI_HandleTypeDef | SAI_HandleTypeDef
typedef void(* | pSAI_CallbackTypeDef )(SAI_HandleTypeDef *hsai)
SAI callback pointer definition.

Enumerations

enum HAL_SAI_StateTypeDef {
HAL_SAI_STATE_RESET = 0x00U, HAL_SAI_STATE_READY = 0x01U, HAL_SAI_STATE_BUSY = 0x02U, HAL_SAI_STATE_BUSY_TX = 0x12U,
HAL_SAI_STATE_BUSY_RX = 0x22U
}
HAL State structures definition. More...
enum HAL_SAI_CallbackIDTypeDef {
HAL_SAI_RX_COMPLETE_CB_ID = 0x00U, HAL_SAI_RX_HALFCOMPLETE_CB_ID = 0x01U, HAL_SAI_TX_COMPLETE_CB_ID = 0x02U, HAL_SAI_TX_HALFCOMPLETE_CB_ID = 0x03U,
HAL_SAI_ERROR_CB_ID = 0x04U, HAL_SAI_MSPINIT_CB_ID = 0x05U, HAL_SAI_MSPDEINIT_CB_ID = 0x06U
}
SAI callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_SAI_InitProtocol (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initialize the structure FrameInit, SlotInit and the low part of Init according to the specified parameters and call the function HAL_SAI_Init to initialize the SAI block.
HAL_StatusTypeDef | HAL_SAI_Init (SAI_HandleTypeDef *hsai)
Initialize the SAI according to the specified parameters.
HAL_StatusTypeDef | HAL_SAI_DeInit (SAI_HandleTypeDef *hsai)
DeInitialize the SAI peripheral.
__weak void | HAL_SAI_MspInit (SAI_HandleTypeDef *hsai)
Initialize the SAI MSP.
__weak void | HAL_SAI_MspDeInit (SAI_HandleTypeDef *hsai)
DeInitialize the SAI MSP.
HAL_StatusTypeDef | HAL_SAI_RegisterCallback (SAI_HandleTypeDef *hsai, HAL_SAI_CallbackIDTypeDef CallbackID, pSAI_CallbackTypeDef pCallback)
Register a user SAI callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SAI_UnRegisterCallback (SAI_HandleTypeDef *hsai, HAL_SAI_CallbackIDTypeDef CallbackID)
Unregister a user SAI callback.
HAL_StatusTypeDef | HAL_SAI_Transmit (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SAI_Receive (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SAI_Transmit_IT (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SAI_Receive_IT (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SAI_Transmit_DMA (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SAI_Receive_DMA (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SAI_DMAPause (SAI_HandleTypeDef *hsai)
Pause the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_DMAResume (SAI_HandleTypeDef *hsai)
Resume the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_DMAStop (SAI_HandleTypeDef *hsai)
Stop the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_Abort (SAI_HandleTypeDef *hsai)
Abort the current transfer and disable the SAI.
HAL_StatusTypeDef | HAL_SAI_EnableTxMuteMode (SAI_HandleTypeDef *hsai, uint16_t val)
Enable the Tx mute mode.
HAL_StatusTypeDef | HAL_SAI_DisableTxMuteMode (SAI_HandleTypeDef *hsai)
Disable the Tx mute mode.
HAL_StatusTypeDef | HAL_SAI_EnableRxMuteMode (SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter)
Enable the Rx mute detection.
HAL_StatusTypeDef | HAL_SAI_DisableRxMuteMode (SAI_HandleTypeDef *hsai)
Disable the Rx mute detection.
void | HAL_SAI_IRQHandler (SAI_HandleTypeDef *hsai)
Handle SAI interrupt request.
__weak void | HAL_SAI_TxHalfCpltCallback (SAI_HandleTypeDef *hsai)
Tx Transfer Half completed callback.
__weak void | HAL_SAI_TxCpltCallback (SAI_HandleTypeDef *hsai)
Tx Transfer completed callback.
__weak void | HAL_SAI_RxHalfCpltCallback (SAI_HandleTypeDef *hsai)
Rx Transfer half completed callback.
__weak void | HAL_SAI_RxCpltCallback (SAI_HandleTypeDef *hsai)
Rx Transfer completed callback.
__weak void | HAL_SAI_ErrorCallback (SAI_HandleTypeDef *hsai)
SAI error callback.
HAL_SAI_StateTypeDef | HAL_SAI_GetState (SAI_HandleTypeDef *hsai)
Return the SAI handle state.
uint32_t | HAL_SAI_GetError (SAI_HandleTypeDef *hsai)
Return the SAI error code.

Detailed Description

Header file of SAI HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_sai.h.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_sai_ex.h File Reference

  • File List
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Data Structures | Defines | Functions
stm32wbxx_hal_sai_ex.h File Reference

Header file of SAI HAL extended module. More...

#include "stm32wbxx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | SAIEx_PdmMicDelayParamTypeDef
PDM microphone delay structure definition. More...

Defines

#define | IS_SAI_PDM_MIC_DELAY(VALUE) ((VALUE) <= 7U)

Functions

HAL_StatusTypeDef | HAL_SAIEx_ConfigPdmMicDelay (SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay)
Configure PDM microphone delays.

Detailed Description

Header file of SAI HAL extended module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_sai_ex.h.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_smartcard.h File Reference

  • File List
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  • STM32WBxx_HAL_Driver
  • Inc
Data Structures | Defines | Typedefs | Enumerations | Functions
stm32wbxx_hal_smartcard.h File Reference

Header file of SMARTCARD HAL module. More...

#include "stm32wbxx_hal_def.h"
#include "stm32wbxx_hal_smartcard_ex.h"

Go to the source code of this file.

Data Structures

struct | SMARTCARD_InitTypeDef
SMARTCARD Init Structure definition. More...
struct | SMARTCARD_AdvFeatureInitTypeDef
SMARTCARD advanced features initalization structure definition. More...
struct | __SMARTCARD_HandleTypeDef
SMARTCARD handle Structure definition. More...

Defines

#define | HAL_SMARTCARD_STATE_RESET 0x00000000U
#define | HAL_SMARTCARD_STATE_READY 0x00000020U
#define | HAL_SMARTCARD_STATE_BUSY 0x00000024U
#define | HAL_SMARTCARD_STATE_BUSY_TX 0x00000021U
#define | HAL_SMARTCARD_STATE_BUSY_RX 0x00000022U
#define | HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U
#define | HAL_SMARTCARD_STATE_TIMEOUT 0x000000A0U
#define | HAL_SMARTCARD_STATE_ERROR 0x000000E0U
#define | HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_SMARTCARD_ERROR_PE ((uint32_t)0x00000001U)
#define | HAL_SMARTCARD_ERROR_NE ((uint32_t)0x00000002U)
#define | HAL_SMARTCARD_ERROR_FE ((uint32_t)0x00000004U)
#define | HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x00000008U)
#define | HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x00000010U)
#define | HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x00000020U)
#define | HAL_SMARTCARD_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U)
#define | SMARTCARD_WORDLENGTH_9B USART_CR1_M0
#define | SMARTCARD_STOPBITS_0_5 USART_CR2_STOP_0
#define | SMARTCARD_STOPBITS_1_5 USART_CR2_STOP
#define | SMARTCARD_PARITY_EVEN USART_CR1_PCE
#define | SMARTCARD_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)
#define | SMARTCARD_MODE_RX USART_CR1_RE
#define | SMARTCARD_MODE_TX USART_CR1_TE
#define | SMARTCARD_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)
#define | SMARTCARD_POLARITY_LOW 0x00000000U
#define | SMARTCARD_POLARITY_HIGH USART_CR2_CPOL
#define | SMARTCARD_PHASE_1EDGE 0x00000000U
#define | SMARTCARD_PHASE_2EDGE USART_CR2_CPHA
#define | SMARTCARD_LASTBIT_DISABLE 0x00000000U
#define | SMARTCARD_LASTBIT_ENABLE USART_CR2_LBCL
#define | SMARTCARD_ONE_BIT_SAMPLE_DISABLE 0x00000000U
#define | SMARTCARD_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT
#define | SMARTCARD_NACK_DISABLE 0x00000000U
#define | SMARTCARD_NACK_ENABLE USART_CR3_NACK
#define | SMARTCARD_TIMEOUT_DISABLE 0x00000000U
#define | SMARTCARD_TIMEOUT_ENABLE USART_CR2_RTOEN
#define | SMARTCARD_PRESCALER_DIV1 0x00000000U
#define | SMARTCARD_PRESCALER_DIV2 0x00000001U
#define | SMARTCARD_PRESCALER_DIV4 0x00000002U
#define | SMARTCARD_PRESCALER_DIV6 0x00000003U
#define | SMARTCARD_PRESCALER_DIV8 0x00000004U
#define | SMARTCARD_PRESCALER_DIV10 0x00000005U
#define | SMARTCARD_PRESCALER_DIV12 0x00000006U
#define | SMARTCARD_PRESCALER_DIV16 0x00000007U
#define | SMARTCARD_PRESCALER_DIV32 0x00000008U
#define | SMARTCARD_PRESCALER_DIV64 0x00000009U
#define | SMARTCARD_PRESCALER_DIV128 0x0000000AU
#define | SMARTCARD_PRESCALER_DIV256 0x0000000BU
#define | SMARTCARD_ADVFEATURE_TXINV_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV
#define | SMARTCARD_ADVFEATURE_RXINV_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV
#define | SMARTCARD_ADVFEATURE_DATAINV_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV
#define | SMARTCARD_ADVFEATURE_SWAP_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP
#define | SMARTCARD_ADVFEATURE_OVERRUN_ENABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS
#define | SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U
#define | SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE
#define | SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U
#define | SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST
#define | SMARTCARD_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ
#define | SMARTCARD_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ
#define | SMARTCARD_IT_MASK 0x001FU
#define | SMARTCARD_CR_MASK 0x00E0U
#define | SMARTCARD_CR_POS 5U
#define | SMARTCARD_ISR_MASK 0x1F00U
#define | SMARTCARD_ISR_POS 8U
#define | __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)
Reset SMARTCARD handle states.
#define | __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__)
Flush the Smartcard Data registers.
#define | __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified SMARTCARD pending flag.
#define | __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
Clear the SMARTCARD PE pending flag.
#define | __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)
Clear the SMARTCARD FE pending flag.
#define | __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)
Clear the SMARTCARD NE pending flag.
#define | __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)
Clear the SMARTCARD ORE pending flag.
#define | __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
Clear the SMARTCARD IDLE pending flag.
#define | __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified Smartcard flag is set or not.
#define | __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified SmartCard interrupt.
#define | __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified SmartCard interrupt.
#define | __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET)
Check whether the specified SmartCard interrupt has occurred or not.
#define | __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified SmartCard interrupt source is enabled or not.
#define | __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))
Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
#define | __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific SMARTCARD request flag.
#define | __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the SMARTCARD one bit sample method.
#define | __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
Disable the SMARTCARD one bit sample method.
#define | __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable the USART associated to the SMARTCARD Handle.
#define | __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable the USART associated to the SMARTCARD Handle.
#define | SMARTCARD_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the SMARTCARD clock source.
#define | IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4000001U)
Check the Baud rate range.
#define | IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU)
Check the block length range.
#define | IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
Check the receiver timeout value.
#define | IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7U)
Check the SMARTCARD autoretry counter value.
#define | IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
Ensure that SMARTCARD frame length is valid.
#define | IS_SMARTCARD_STOPBITS(__STOPBITS__)
Ensure that SMARTCARD frame number of stop bits is valid.
#define | IS_SMARTCARD_PARITY(__PARITY__)
Ensure that SMARTCARD frame parity is valid.
#define | IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & 0xFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
Ensure that SMARTCARD communication mode is valid.
#define | IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
Ensure that SMARTCARD frame polarity is valid.
#define | IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
Ensure that SMARTCARD frame phase is valid.
#define | IS_SMARTCARD_LASTBIT(__LASTBIT__)
Ensure that SMARTCARD frame last bit clock pulse setting is valid.
#define | IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that SMARTCARD frame sampling is valid.
#define | IS_SMARTCARD_NACK(__NACK__)
Ensure that SMARTCARD NACK transmission setting is valid.
#define | IS_SMARTCARD_TIMEOUT(__TIMEOUT__)
Ensure that SMARTCARD receiver timeout setting is valid.
#define | IS_SMARTCARD_CLOCKPRESCALER(__CLOCKPRESCALER__)
Ensure that SMARTCARD clock Prescaler is valid.
#define | IS_SMARTCARD_ADVFEATURE_INIT(__INIT__)
Ensure that SMARTCARD advanced features initialization is valid.
#define | IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__)
Ensure that SMARTCARD frame TX inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__)
Ensure that SMARTCARD frame RX inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__)
Ensure that SMARTCARD frame data inversion setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__)
Ensure that SMARTCARD frame RX/TX pins swap setting is valid.
#define | IS_SMARTCARD_OVERRUN(__OVERRUN__)
Ensure that SMARTCARD frame overrun setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__)
Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.
#define | IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__)
Ensure that SMARTCARD frame MSB first setting is valid.
#define | IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__)
Ensure that SMARTCARD request parameter is valid.

Typedefs

typedef uint32_t | HAL_SMARTCARD_StateTypeDef
HAL SMARTCARD State definition.
typedef struct
__SMARTCARD_HandleTypeDef 		SMARTCARD_HandleTypeDef
SMARTCARD handle Structure definition.
typedef void(* | pSMARTCARD_CallbackTypeDef )(SMARTCARD_HandleTypeDef *hsmartcard)
HAL SMARTCARD Callback pointer definition.

Enumerations

enum HAL_SMARTCARD_CallbackIDTypeDef {
HAL_SMARTCARD_TX_COMPLETE_CB_ID = 0x00U, HAL_SMARTCARD_RX_COMPLETE_CB_ID = 0x01U, HAL_SMARTCARD_ERROR_CB_ID = 0x02U, HAL_SMARTCARD_ABORT_COMPLETE_CB_ID = 0x03U,
HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x04U, HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID = 0x05U, HAL_SMARTCARD_RX_FIFO_FULL_CB_ID = 0x06U, HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID = 0x07U,
HAL_SMARTCARD_MSPINIT_CB_ID = 0x08U, HAL_SMARTCARD_MSPDEINIT_CB_ID = 0x09U
}
HAL SMARTCARD Callback ID enumeration definition. More...
enum SMARTCARD_ClockSourceTypeDef {
SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01, SMARTCARD_CLOCKSOURCE_HSI = 0x02, SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04, SMARTCARD_CLOCKSOURCE_LSE = 0x08,
SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10
}
SMARTCARD clock sources. More...

Functions

HAL_StatusTypeDef | HAL_SMARTCARD_Init (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD mode according to the specified parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMARTCARD_DeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD peripheral.
__weak void | HAL_SMARTCARD_MspInit (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD MSP.
__weak void | HAL_SMARTCARD_MspDeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD MSP.
HAL_StatusTypeDef | HAL_SMARTCARD_RegisterCallback (SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback)
Register a User SMARTCARD Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SMARTCARD_UnRegisterCallback (SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID)
Unregister an SMARTCARD callback SMARTCARD callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_DMA (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_DMA (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Abort (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_Abort_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_SMARTCARD_IRQHandler (SMARTCARD_HandleTypeDef *hsmartcard)
Handle SMARTCARD interrupt requests.
__weak void | HAL_SMARTCARD_TxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Tx Transfer completed callback.
__weak void | HAL_SMARTCARD_RxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Rx Transfer completed callback.
__weak void | HAL_SMARTCARD_ErrorCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD error callback.
__weak void | HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Complete callback.
__weak void | HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Complete callback.
__weak void | HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Receive Complete callback.
HAL_SMARTCARD_StateTypeDef | HAL_SMARTCARD_GetState (SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle state.
uint32_t | HAL_SMARTCARD_GetError (SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle error code.

Detailed Description

Header file of SMARTCARD HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_smartcard.h.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_smartcard_ex.h File Reference

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Defines | Functions
stm32wbxx_hal_smartcard_ex.h File Reference

Header file of SMARTCARD HAL Extended module. More...

#include "stm32wbxx_hal_def.h"

Go to the source code of this file.

Defines

#define | SMARTCARD_TCBGT SMARTCARD_IT_TCBGT
#define | SMARTCARD_TC SMARTCARD_IT_TC
#define | SMARTCARD_ADVFEATURE_NO_INIT 0x00000000U
#define | SMARTCARD_ADVFEATURE_TXINVERT_INIT 0x00000001U
#define | SMARTCARD_ADVFEATURE_RXINVERT_INIT 0x00000002U
#define | SMARTCARD_ADVFEATURE_DATAINVERT_INIT 0x00000004U
#define | SMARTCARD_ADVFEATURE_SWAP_INIT 0x00000008U
#define | SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U
#define | SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U
#define | SMARTCARD_ADVFEATURE_MSBFIRST_INIT 0x00000080U
#define | SMARTCARD_ADVFEATURE_TXCOMPLETION 0x00000100U
#define | SMARTCARD_FIFOMODE_DISABLE 0x00000000U
#define | SMARTCARD_FIFOMODE_ENABLE USART_CR1_FIFOEN
#define | SMARTCARD_TXFIFO_THRESHOLD_1_8 0x00000000U
#define | SMARTCARD_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0
#define | SMARTCARD_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1
#define | SMARTCARD_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)
#define | SMARTCARD_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2
#define | SMARTCARD_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)
#define | SMARTCARD_RXFIFO_THRESHOLD_1_8 0x00000000U
#define | SMARTCARD_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0
#define | SMARTCARD_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1
#define | SMARTCARD_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)
#define | SMARTCARD_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2
#define | SMARTCARD_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)
#define | SMARTCARD_FLAG_TCBGT USART_ISR_TCBGT
#define | SMARTCARD_FLAG_REACK USART_ISR_REACK
#define | SMARTCARD_FLAG_TEACK USART_ISR_TEACK
#define | SMARTCARD_FLAG_BUSY USART_ISR_BUSY
#define | SMARTCARD_FLAG_EOBF USART_ISR_EOBF
#define | SMARTCARD_FLAG_RTOF USART_ISR_RTOF
#define | SMARTCARD_FLAG_TXE USART_ISR_TXE_TXFNF
#define | SMARTCARD_FLAG_TXFNF USART_ISR_TXE_TXFNF
#define | SMARTCARD_FLAG_TC USART_ISR_TC
#define | SMARTCARD_FLAG_RXNE USART_ISR_RXNE_RXFNE
#define | SMARTCARD_FLAG_RXFNE USART_ISR_RXNE_RXFNE
#define | SMARTCARD_FLAG_IDLE USART_ISR_IDLE
#define | SMARTCARD_FLAG_ORE USART_ISR_ORE
#define | SMARTCARD_FLAG_NE USART_ISR_NE
#define | SMARTCARD_FLAG_FE USART_ISR_FE
#define | SMARTCARD_FLAG_PE USART_ISR_PE
#define | SMARTCARD_FLAG_TXFE USART_ISR_TXFE
#define | SMARTCARD_FLAG_RXFF USART_ISR_RXFF
#define | SMARTCARD_FLAG_RXFT USART_ISR_RXFT
#define | SMARTCARD_FLAG_TXFT USART_ISR_TXFT
#define | SMARTCARD_IT_PE 0x0028U
#define | SMARTCARD_IT_TXE 0x0727U
#define | SMARTCARD_IT_TXFNF 0x0727U
#define | SMARTCARD_IT_TC 0x0626U
#define | SMARTCARD_IT_RXNE 0x0525U
#define | SMARTCARD_IT_RXFNE 0x0525U
#define | SMARTCARD_IT_IDLE 0x0424U
#define | SMARTCARD_IT_ERR 0x0060U
#define | SMARTCARD_IT_ORE 0x0300U
#define | SMARTCARD_IT_NE 0x0200U
#define | SMARTCARD_IT_FE 0x0100U
#define | SMARTCARD_IT_EOB 0x0C3BU
#define | SMARTCARD_IT_RTO 0x0B3AU
#define | SMARTCARD_IT_TCBGT 0x1978U
#define | SMARTCARD_IT_RXFF 0x183FU
#define | SMARTCARD_IT_TXFE 0x173EU
#define | SMARTCARD_IT_RXFT 0x1A7CU
#define | SMARTCARD_IT_TXFT 0x1B77U
#define | SMARTCARD_CLEAR_PEF USART_ICR_PECF
#define | SMARTCARD_CLEAR_FEF USART_ICR_FECF
#define | SMARTCARD_CLEAR_NEF USART_ICR_NECF
#define | SMARTCARD_CLEAR_OREF USART_ICR_ORECF
#define | SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF
#define | SMARTCARD_CLEAR_TXFECF USART_ICR_TXFECF
#define | SMARTCARD_CLEAR_TCF USART_ICR_TCCF
#define | SMARTCARD_CLEAR_TCBGTF USART_ICR_TCBGTCF
#define | SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF
#define | SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF
#define | SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__)
Set the Transmission Completion flag.
#define | SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) : (SMARTCARD_FLAG_TCBGT))
Return the transmission completion flag.
#define | IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__)
Ensure that SMARTCARD frame transmission completion used flag is valid.
#define | IS_SMARTCARD_FIFOMODE_STATE(__STATE__)
Ensure that SMARTCARD FIFO mode is valid.
#define | IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that SMARTCARD TXFIFO threshold level is valid.
#define | IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that SMARTCARD RXFIFO threshold level is valid.

Functions

void | HAL_SMARTCARDEx_BlockLength_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
Update on the fly the SMARTCARD block length in RTOR register.
void | HAL_SMARTCARDEx_TimeOut_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
Update on the fly the receiver timeout value in RTOR register.
HAL_StatusTypeDef | HAL_SMARTCARDEx_EnableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Enable the SMARTCARD receiver timeout feature.
HAL_StatusTypeDef | HAL_SMARTCARDEx_DisableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Disable the SMARTCARD receiver timeout feature.
__weak void | HAL_SMARTCARDEx_RxFifoFullCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD RX Fifo full callback.
__weak void | HAL_SMARTCARDEx_TxFifoEmptyCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD TX Fifo empty callback.
HAL_StatusTypeDef | HAL_SMARTCARDEx_EnableFifoMode (SMARTCARD_HandleTypeDef *hsmartcard)
Enable the FIFO mode.
HAL_StatusTypeDef | HAL_SMARTCARDEx_DisableFifoMode (SMARTCARD_HandleTypeDef *hsmartcard)
Disable the FIFO mode.
HAL_StatusTypeDef | HAL_SMARTCARDEx_SetTxFifoThreshold (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
Set the TXFIFO threshold.
HAL_StatusTypeDef | HAL_SMARTCARDEx_SetRxFifoThreshold (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
Set the RXFIFO threshold.

Detailed Description

Header file of SMARTCARD HAL Extended module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_smartcard_ex.h.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_smbus.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32wbxx_hal_smbus.h File Reference

Header file of SMBUS HAL module. More...

#include "stm32wbxx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | SMBUS_InitTypeDef
struct | __SMBUS_HandleTypeDef

Defines

#define | HAL_SMBUS_STATE_RESET (0x00000000U)
#define | HAL_SMBUS_STATE_READY (0x00000001U)
#define | HAL_SMBUS_STATE_BUSY (0x00000002U)
#define | HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U)
#define | HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U)
#define | HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U)
#define | HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U)
#define | HAL_SMBUS_STATE_TIMEOUT (0x00000003U)
#define | HAL_SMBUS_STATE_ERROR (0x00000004U)
#define | HAL_SMBUS_STATE_LISTEN (0x00000008U)
#define | HAL_SMBUS_ERROR_NONE (0x00000000U)
#define | HAL_SMBUS_ERROR_BERR (0x00000001U)
#define | HAL_SMBUS_ERROR_ARLO (0x00000002U)
#define | HAL_SMBUS_ERROR_ACKF (0x00000004U)
#define | HAL_SMBUS_ERROR_OVR (0x00000008U)
#define | HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U)
#define | HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U)
#define | HAL_SMBUS_ERROR_ALERT (0x00000040U)
#define | HAL_SMBUS_ERROR_PECERR (0x00000080U)
#define | HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U)
#define | HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U)
#define | SMBUS_ANALOGFILTER_ENABLE (0x00000000U)
#define | SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
#define | SMBUS_ADDRESSINGMODE_7BIT (0x00000001U)
#define | SMBUS_ADDRESSINGMODE_10BIT (0x00000002U)
#define | SMBUS_DUALADDRESS_DISABLE (0x00000000U)
#define | SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
#define | SMBUS_OA2_NOMASK ((uint8_t)0x00U)
#define | SMBUS_OA2_MASK01 ((uint8_t)0x01U)
#define | SMBUS_OA2_MASK02 ((uint8_t)0x02U)
#define | SMBUS_OA2_MASK03 ((uint8_t)0x03U)
#define | SMBUS_OA2_MASK04 ((uint8_t)0x04U)
#define | SMBUS_OA2_MASK05 ((uint8_t)0x05U)
#define | SMBUS_OA2_MASK06 ((uint8_t)0x06U)
#define | SMBUS_OA2_MASK07 ((uint8_t)0x07U)
#define | SMBUS_GENERALCALL_DISABLE (0x00000000U)
#define | SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN
#define | SMBUS_NOSTRETCH_DISABLE (0x00000000U)
#define | SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
#define | SMBUS_PEC_DISABLE (0x00000000U)
#define | SMBUS_PEC_ENABLE I2C_CR1_PECEN
#define | SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN
#define | SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U)
#define | SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN
#define | SMBUS_SOFTEND_MODE (0x00000000U)
#define | SMBUS_RELOAD_MODE I2C_CR2_RELOAD
#define | SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
#define | SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE
#define | SMBUS_NO_STARTSTOP (0x00000000U)
#define | SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define | SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define | SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
#define | SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE
#define | SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
#define | SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define | SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define | SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
#define | SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
#define | SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)
#define | SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)
#define | SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)
#define | SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)
#define | SMBUS_IT_ERRI I2C_CR1_ERRIE
#define | SMBUS_IT_TCI I2C_CR1_TCIE
#define | SMBUS_IT_STOPI I2C_CR1_STOPIE
#define | SMBUS_IT_NACKI I2C_CR1_NACKIE
#define | SMBUS_IT_ADDRI I2C_CR1_ADDRIE
#define | SMBUS_IT_RXI I2C_CR1_RXIE
#define | SMBUS_IT_TXI I2C_CR1_TXIE
#define | SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
#define | SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
#define | SMBUS_IT_ALERT (SMBUS_IT_ERRI)
#define | SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
#define | SMBUS_FLAG_TXE I2C_ISR_TXE
#define | SMBUS_FLAG_TXIS I2C_ISR_TXIS
#define | SMBUS_FLAG_RXNE I2C_ISR_RXNE
#define | SMBUS_FLAG_ADDR I2C_ISR_ADDR
#define | SMBUS_FLAG_AF I2C_ISR_NACKF
#define | SMBUS_FLAG_STOPF I2C_ISR_STOPF
#define | SMBUS_FLAG_TC I2C_ISR_TC
#define | SMBUS_FLAG_TCR I2C_ISR_TCR
#define | SMBUS_FLAG_BERR I2C_ISR_BERR
#define | SMBUS_FLAG_ARLO I2C_ISR_ARLO
#define | SMBUS_FLAG_OVR I2C_ISR_OVR
#define | SMBUS_FLAG_PECERR I2C_ISR_PECERR
#define | SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define | SMBUS_FLAG_ALERT I2C_ISR_ALERT
#define | SMBUS_FLAG_BUSY I2C_ISR_BUSY
#define | SMBUS_FLAG_DIR I2C_ISR_DIR
#define | __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__)
Reset SMBUS handle state.
#define | __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
Enable the specified SMBUS interrupts.
#define | __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
Disable the specified SMBUS interrupts.
#define | __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified SMBUS interrupt source is enabled or not.
#define | SMBUS_FLAG_MASK (0x0001FFFFU)
Check whether the specified SMBUS flag is set or not.
#define | __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
#define | __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
#define | __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Enable the specified SMBUS peripheral.
#define | __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
Disable the specified SMBUS peripheral.
#define | __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
#define | IS_SMBUS_ANALOG_FILTER(FILTER)
#define | IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define | IS_SMBUS_ADDRESSING_MODE(MODE)
#define | IS_SMBUS_DUAL_ADDRESS(ADDRESS)
#define | IS_SMBUS_OWN_ADDRESS2_MASK(MASK)
#define | IS_SMBUS_GENERAL_CALL(CALL)
#define | IS_SMBUS_NO_STRETCH(STRETCH)
#define | IS_SMBUS_PEC(PEC)
#define | IS_SMBUS_PERIPHERAL_MODE(MODE)
#define | IS_SMBUS_TRANSFER_MODE(MODE)
#define | IS_SMBUS_TRANSFER_REQUEST(REQUEST)
#define | IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST)
#define | IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)
#define | SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
#define | SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
#define | SMBUS_GENERATE_START(__ADDMODE__, __ADDRESS__)
#define | SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
#define | SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
#define | SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define | SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
#define | SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
#define | SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
#define | SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
#define | IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define | IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)

Typedefs

typedef struct
__SMBUS_HandleTypeDef 		SMBUS_HandleTypeDef
typedef void(* | pSMBUS_CallbackTypeDef )(SMBUS_HandleTypeDef *hsmbus)
HAL SMBUS Callback pointer definition.
typedef void(* | pSMBUS_AddrCallbackTypeDef )(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)

Enumerations

enum HAL_SMBUS_CallbackIDTypeDef {
HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U,
HAL_SMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, HAL_SMBUS_ERROR_CB_ID = 0x05U, HAL_SMBUS_MSPINIT_CB_ID = 0x06U, HAL_SMBUS_MSPDEINIT_CB_ID = 0x07U
}
HAL SMBUS Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_SMBUS_Init (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS according to the specified parameters in the SMBUS_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS peripheral.
__weak void | HAL_SMBUS_MspInit (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS MSP.
__weak void | HAL_SMBUS_MspDeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS MSP.
HAL_StatusTypeDef | HAL_SMBUS_ConfigAnalogFilter (SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter)
Configure Analog noise filter.
HAL_StatusTypeDef | HAL_SMBUS_ConfigDigitalFilter (SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter)
Configure Digital noise filter.
HAL_StatusTypeDef | HAL_SMBUS_RegisterCallback (SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback)
Register a User SMBUS Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_UnRegisterCallback (SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID)
Unregister an SMBUS Callback SMBUS callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_RegisterAddrCallback (SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback)
Register the Slave Address Match SMBUS Callback To be used instead of the weak HAL_SMBUS_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_UnRegisterAddrCallback (SMBUS_HandleTypeDef *hsmbus)
UnRegister the Slave Address Match SMBUS Callback Info Ready SMBUS Callback is redirected to the weak HAL_SMBUS_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_IsDeviceReady (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Check if target device is ready for communication.
HAL_StatusTypeDef | HAL_SMBUS_Master_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Abort_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
Abort a master/host SMBUS process communication with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the Address listen mode with Interrupt.
void | HAL_SMBUS_EV_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS event interrupt request.
void | HAL_SMBUS_ER_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS error interrupt request.
__weak void | HAL_SMBUS_MasterTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Tx Transfer completed callback.
__weak void | HAL_SMBUS_MasterRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Rx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Tx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Rx Transfer completed callback.
__weak void | HAL_SMBUS_AddrCallback (SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_SMBUS_ListenCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Listen Complete callback.
__weak void | HAL_SMBUS_ErrorCallback (SMBUS_HandleTypeDef *hsmbus)
SMBUS error callback.
uint32_t | HAL_SMBUS_GetState (SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS handle state.
uint32_t | HAL_SMBUS_GetError (SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS error code.

Detailed Description

Header file of SMBUS HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_smbus.h.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_spi.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32wbxx_hal_spi.h File Reference

Header file of SPI HAL module. More...

#include "stm32wbxx_hal_def.h"
#include "stm32wbxx_hal_spi_ex.h"

Go to the source code of this file.

Data Structures

struct | SPI_InitTypeDef
SPI Configuration Structure definition. More...
struct | __SPI_HandleTypeDef
SPI handle Structure definition. More...

Defines

#define | HAL_SPI_ERROR_NONE (0x00000000U)
#define | HAL_SPI_ERROR_MODF (0x00000001U)
#define | HAL_SPI_ERROR_CRC (0x00000002U)
#define | HAL_SPI_ERROR_OVR (0x00000004U)
#define | HAL_SPI_ERROR_FRE (0x00000008U)
#define | HAL_SPI_ERROR_DMA (0x00000010U)
#define | HAL_SPI_ERROR_FLAG (0x00000020U)
#define | HAL_SPI_ERROR_ABORT (0x00000040U)
#define | HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U)
#define | SPI_MODE_SLAVE (0x00000000U)
#define | SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
#define | SPI_DIRECTION_2LINES (0x00000000U)
#define | SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
#define | SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
#define | SPI_DATASIZE_4BIT (0x00000300U)
#define | SPI_DATASIZE_5BIT (0x00000400U)
#define | SPI_DATASIZE_6BIT (0x00000500U)
#define | SPI_DATASIZE_7BIT (0x00000600U)
#define | SPI_DATASIZE_8BIT (0x00000700U)
#define | SPI_DATASIZE_9BIT (0x00000800U)
#define | SPI_DATASIZE_10BIT (0x00000900U)
#define | SPI_DATASIZE_11BIT (0x00000A00U)
#define | SPI_DATASIZE_12BIT (0x00000B00U)
#define | SPI_DATASIZE_13BIT (0x00000C00U)
#define | SPI_DATASIZE_14BIT (0x00000D00U)
#define | SPI_DATASIZE_15BIT (0x00000E00U)
#define | SPI_DATASIZE_16BIT (0x00000F00U)
#define | SPI_POLARITY_LOW (0x00000000U)
#define | SPI_POLARITY_HIGH SPI_CR1_CPOL
#define | SPI_PHASE_1EDGE (0x00000000U)
#define | SPI_PHASE_2EDGE SPI_CR1_CPHA
#define | SPI_NSS_SOFT SPI_CR1_SSM
#define | SPI_NSS_HARD_INPUT (0x00000000U)
#define | SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U)
#define | SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP
#define | SPI_NSS_PULSE_DISABLE (0x00000000U)
#define | SPI_BAUDRATEPRESCALER_2 (0x00000000U)
#define | SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0)
#define | SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1)
#define | SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
#define | SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2)
#define | SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
#define | SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
#define | SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
#define | SPI_FIRSTBIT_MSB (0x00000000U)
#define | SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
#define | SPI_TIMODE_DISABLE (0x00000000U)
#define | SPI_TIMODE_ENABLE SPI_CR2_FRF
#define | SPI_CRCCALCULATION_DISABLE (0x00000000U)
#define | SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
#define | SPI_CRC_LENGTH_DATASIZE (0x00000000U)
#define | SPI_CRC_LENGTH_8BIT (0x00000001U)
#define | SPI_CRC_LENGTH_16BIT (0x00000002U)
#define | SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
#define | SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
#define | SPI_RXFIFO_THRESHOLD_HF (0x00000000U)
#define | SPI_IT_TXE SPI_CR2_TXEIE
#define | SPI_IT_RXNE SPI_CR2_RXNEIE
#define | SPI_IT_ERR SPI_CR2_ERRIE
#define | SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
#define | SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
#define | SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
#define | SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
#define | SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
#define | SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
#define | SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
#define | SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
#define | SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */
#define | SPI_FLAG_MASK
#define | SPI_FTLVL_EMPTY (0x00000000U)
#define | SPI_FTLVL_QUARTER_FULL (0x00000800U)
#define | SPI_FTLVL_HALF_FULL (0x00001000U)
#define | SPI_FTLVL_FULL (0x00001800U)
#define | SPI_FRLVL_EMPTY (0x00000000U)
#define | SPI_FRLVL_QUARTER_FULL (0x00000200U)
#define | SPI_FRLVL_HALF_FULL (0x00000400U)
#define | SPI_FRLVL_FULL (0x00000600U)
#define | __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__)
Reset SPI handle state.
#define | __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
Enable the specified SPI interrupts.
#define | __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
Disable the specified SPI interrupts.
#define | __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified SPI interrupt source is enabled or not.
#define | __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Check whether the specified SPI flag is set or not.
#define | __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
Clear the SPI CRCERR pending flag.
#define | __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)
Clear the SPI MODF pending flag.
#define | __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)
Clear the SPI OVR pending flag.
#define | __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)
Clear the SPI FRE pending flag.
#define | __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
Enable the SPI peripheral.
#define | __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
Disable the SPI peripheral.
#define | SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
Set the SPI transmit-only mode.
#define | SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
Set the SPI receive-only mode.
#define | SPI_RESET_CRC(__HANDLE__)
Reset the CRC calculation of the SPI.
#define | SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
Check whether the specified SPI flag is set or not.
#define | SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified SPI Interrupt is set or not.
#define | IS_SPI_MODE(__MODE__)
Checks if SPI Mode parameter is in allowed range.
#define | IS_SPI_DIRECTION(__MODE__)
Checks if SPI Direction Mode parameter is in allowed range.
#define | IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)
Checks if SPI Direction Mode parameter is 2 lines.
#define | IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__)
Checks if SPI Direction Mode parameter is 1 or 2 lines.
#define | IS_SPI_DATASIZE(__DATASIZE__)
Checks if SPI Data Size parameter is in allowed range.
#define | IS_SPI_CPOL(__CPOL__)
Checks if SPI Serial clock steady state parameter is in allowed range.
#define | IS_SPI_CPHA(__CPHA__)
Checks if SPI Clock Phase parameter is in allowed range.
#define | IS_SPI_NSS(__NSS__)
Checks if SPI Slave Select parameter is in allowed range.
#define | IS_SPI_NSSP(__NSSP__)
Checks if SPI NSS Pulse parameter is in allowed range.
#define | IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__)
Checks if SPI Baudrate prescaler parameter is in allowed range.
#define | IS_SPI_FIRST_BIT(__BIT__)
Checks if SPI MSB LSB transmission parameter is in allowed range.
#define | IS_SPI_TIMODE(__MODE__)
Checks if SPI TI mode parameter is in allowed range.
#define | IS_SPI_CRC_CALCULATION(__CALCULATION__)
Checks if SPI CRC calculation enabled state is in allowed range.
#define | IS_SPI_CRC_LENGTH(__LENGTH__)
Checks if SPI CRC length is in allowed range.
#define | IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU) && (((__POLYNOMIAL__)&0x1U) != 0U))
Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
#define | IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL)
Checks if DMA handle is valid.

Typedefs

typedef struct __SPI_HandleTypeDef | SPI_HandleTypeDef
SPI handle Structure definition.
typedef void(* | pSPI_CallbackTypeDef )(SPI_HandleTypeDef *hspi)
HAL SPI Callback pointer definition.

Enumerations

enum HAL_SPI_StateTypeDef {
HAL_SPI_STATE_RESET = 0x00U, HAL_SPI_STATE_READY = 0x01U, HAL_SPI_STATE_BUSY = 0x02U, HAL_SPI_STATE_BUSY_TX = 0x03U,
HAL_SPI_STATE_BUSY_RX = 0x04U, HAL_SPI_STATE_BUSY_TX_RX = 0x05U, HAL_SPI_STATE_ERROR = 0x06U, HAL_SPI_STATE_ABORT = 0x07U
}
HAL SPI State structure definition. More...
enum HAL_SPI_CallbackIDTypeDef {
HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U,
HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U, HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, HAL_SPI_ERROR_CB_ID = 0x06U, HAL_SPI_ABORT_CB_ID = 0x07U,
HAL_SPI_MSPINIT_CB_ID = 0x08U, HAL_SPI_MSPDEINIT_CB_ID = 0x09U
}
HAL SPI Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_SPI_Init (SPI_HandleTypeDef *hspi)
Initialize the SPI according to the specified parameters in the SPI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SPI_DeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI peripheral.
__weak void | HAL_SPI_MspInit (SPI_HandleTypeDef *hspi)
Initialize the SPI MSP.
__weak void | HAL_SPI_MspDeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI MSP.
HAL_StatusTypeDef | HAL_SPI_RegisterCallback (SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback)
Register a User SPI Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SPI_UnRegisterCallback (SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
Unregister an SPI Callback SPI callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_SPI_Transmit (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Receive (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Transmit and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Transmit_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Receive_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_IT (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Transmit_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Receive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_DMAPause (SPI_HandleTypeDef *hspi)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAResume (SPI_HandleTypeDef *hspi)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAStop (SPI_HandleTypeDef *hspi)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_Abort (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (blocking mode).
HAL_StatusTypeDef | HAL_SPI_Abort_IT (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (Interrupt mode).
void | HAL_SPI_IRQHandler (SPI_HandleTypeDef *hspi)
Handle SPI interrupt request.
__weak void | HAL_SPI_TxCpltCallback (SPI_HandleTypeDef *hspi)
Tx Transfer completed callback.
__weak void | HAL_SPI_RxCpltCallback (SPI_HandleTypeDef *hspi)
Rx Transfer completed callback.
__weak void | HAL_SPI_TxRxCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Transfer completed callback.
__weak void | HAL_SPI_TxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx Half Transfer completed callback.
__weak void | HAL_SPI_RxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Rx Half Transfer completed callback.
__weak void | HAL_SPI_TxRxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Half Transfer callback.
__weak void | HAL_SPI_ErrorCallback (SPI_HandleTypeDef *hspi)
SPI error callback.
__weak void | HAL_SPI_AbortCpltCallback (SPI_HandleTypeDef *hspi)
SPI Abort Complete callback.
HAL_SPI_StateTypeDef | HAL_SPI_GetState (SPI_HandleTypeDef *hspi)
Return the SPI handle state.
uint32_t | HAL_SPI_GetError (SPI_HandleTypeDef *hspi)
Return the SPI error code.

Detailed Description

Header file of SPI HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_spi.h.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_spi_ex.h File Reference

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Functions
stm32wbxx_hal_spi_ex.h File Reference

Header file of SPI HAL Extended module. More...

#include "stm32wbxx_hal_def.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo (SPI_HandleTypeDef *hspi)
Flush the RX fifo.

Detailed Description

Header file of SPI HAL Extended module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_spi_ex.h.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_tim.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32wbxx_hal_tim.h File Reference

Header file of TIM HAL module. More...

#include "stm32wbxx_hal_def.h"
#include "stm32wbxx_hal_tim_ex.h"

Go to the source code of this file.

Data Structures

struct | TIM_Base_InitTypeDef
TIM Time base Configuration Structure definition. More...
struct | TIM_OC_InitTypeDef
TIM Output Compare Configuration Structure definition. More...
struct | TIM_OnePulse_InitTypeDef
TIM One Pulse Mode Configuration Structure definition. More...
struct | TIM_IC_InitTypeDef
TIM Input Capture Configuration Structure definition. More...
struct | TIM_Encoder_InitTypeDef
TIM Encoder Configuration Structure definition. More...
struct | TIM_ClockConfigTypeDef
Clock Configuration Handle Structure definition. More...
struct | TIM_ClearInputConfigTypeDef
TIM Clear Input Configuration Handle Structure definition. More...
struct | TIM_MasterConfigTypeDef
TIM Master configuration Structure definition. More...
struct | TIM_SlaveConfigTypeDef
TIM Slave configuration Structure definition. More...
struct | TIM_BreakDeadTimeConfigTypeDef
TIM Break input(s) and Dead time configuration Structure definition. More...
struct | __TIM_HandleTypeDef
TIM Time Base Handle Structure definition. More...

Defines

#define | TIM_CLEARINPUTSOURCE_NONE 0x00000000U
#define | TIM_CLEARINPUTSOURCE_ETR 0x00000001U
#define | TIM_CLEARINPUTSOURCE_COMP1 TIM1_AF1_ETRSEL_0
#define | TIM_CLEARINPUTSOURCE_COMP2 TIM1_AF1_ETRSEL_1
#define | TIM_DMABASE_CR1 0x00000000U
#define | TIM_DMABASE_CR2 0x00000001U
#define | TIM_DMABASE_SMCR 0x00000002U
#define | TIM_DMABASE_DIER 0x00000003U
#define | TIM_DMABASE_SR 0x00000004U
#define | TIM_DMABASE_EGR 0x00000005U
#define | TIM_DMABASE_CCMR1 0x00000006U
#define | TIM_DMABASE_CCMR2 0x00000007U
#define | TIM_DMABASE_CCER 0x00000008U
#define | TIM_DMABASE_CNT 0x00000009U
#define | TIM_DMABASE_PSC 0x0000000AU
#define | TIM_DMABASE_ARR 0x0000000BU
#define | TIM_DMABASE_RCR 0x0000000CU
#define | TIM_DMABASE_CCR1 0x0000000DU
#define | TIM_DMABASE_CCR2 0x0000000EU
#define | TIM_DMABASE_CCR3 0x0000000FU
#define | TIM_DMABASE_CCR4 0x00000010U
#define | TIM_DMABASE_BDTR 0x00000011U
#define | TIM_DMABASE_DCR 0x00000012U
#define | TIM_DMABASE_DMAR 0x00000013U
#define | TIM_DMABASE_OR 0x00000014U
#define | TIM_DMABASE_CCMR3 0x00000015U
#define | TIM_DMABASE_CCR5 0x00000016U
#define | TIM_DMABASE_CCR6 0x00000017U
#define | TIM_DMABASE_AF1 0x00000018U
#define | TIM_DMABASE_AF2 0x00000019U
#define | TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
#define | TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
#define | TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
#define | TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
#define | TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
#define | TIM_EVENTSOURCE_COM TIM_EGR_COMG
#define | TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
#define | TIM_EVENTSOURCE_BREAK TIM_EGR_BG
#define | TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G
#define | TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U
#define | TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P
#define | TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)
#define | TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP
#define | TIM_ETRPOLARITY_NONINVERTED 0x00000000U
#define | TIM_ETRPRESCALER_DIV1 0x00000000U
#define | TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0
#define | TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1
#define | TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS
#define | TIM_COUNTERMODE_UP 0x00000000U
#define | TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define | TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
#define | TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
#define | TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
#define | TIM_CLOCKDIVISION_DIV1 0x00000000U
#define | TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0
#define | TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1
#define | TIM_OUTPUTSTATE_DISABLE 0x00000000U
#define | TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E
#define | TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U
#define | TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE
#define | TIM_OCFAST_DISABLE 0x00000000U
#define | TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE
#define | TIM_OUTPUTNSTATE_DISABLE 0x00000000U
#define | TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE
#define | TIM_OCPOLARITY_HIGH 0x00000000U
#define | TIM_OCPOLARITY_LOW TIM_CCER_CC1P
#define | TIM_OCNPOLARITY_HIGH 0x00000000U
#define | TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP
#define | TIM_OCIDLESTATE_SET TIM_CR2_OIS1
#define | TIM_OCIDLESTATE_RESET 0x00000000U
#define | TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N
#define | TIM_OCNIDLESTATE_RESET 0x00000000U
#define | TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
#define | TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0
#define | TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1
#define | TIM_ICSELECTION_TRC TIM_CCMR1_CC1S
#define | TIM_ICPSC_DIV1 0x00000000U
#define | TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0
#define | TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1
#define | TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC
#define | TIM_OPMODE_SINGLE TIM_CR1_OPM
#define | TIM_OPMODE_REPETITIVE 0x00000000U
#define | TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0
#define | TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1
#define | TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | TIM_IT_UPDATE TIM_DIER_UIE
#define | TIM_IT_CC1 TIM_DIER_CC1IE
#define | TIM_IT_CC2 TIM_DIER_CC2IE
#define | TIM_IT_CC3 TIM_DIER_CC3IE
#define | TIM_IT_CC4 TIM_DIER_CC4IE
#define | TIM_IT_COM TIM_DIER_COMIE
#define | TIM_IT_TRIGGER TIM_DIER_TIE
#define | TIM_IT_BREAK TIM_DIER_BIE
#define | TIM_COMMUTATION_TRGI TIM_CR2_CCUS
#define | TIM_COMMUTATION_SOFTWARE 0x00000000U
#define | TIM_DMA_UPDATE TIM_DIER_UDE
#define | TIM_DMA_CC1 TIM_DIER_CC1DE
#define | TIM_DMA_CC2 TIM_DIER_CC2DE
#define | TIM_DMA_CC3 TIM_DIER_CC3DE
#define | TIM_DMA_CC4 TIM_DIER_CC4DE
#define | TIM_DMA_COM TIM_DIER_COMDE
#define | TIM_DMA_TRIGGER TIM_DIER_TDE
#define | TIM_FLAG_UPDATE TIM_SR_UIF
#define | TIM_FLAG_CC1 TIM_SR_CC1IF
#define | TIM_FLAG_CC2 TIM_SR_CC2IF
#define | TIM_FLAG_CC3 TIM_SR_CC3IF
#define | TIM_FLAG_CC4 TIM_SR_CC4IF
#define | TIM_FLAG_CC5 TIM_SR_CC5IF
#define | TIM_FLAG_CC6 TIM_SR_CC6IF
#define | TIM_FLAG_COM TIM_SR_COMIF
#define | TIM_FLAG_TRIGGER TIM_SR_TIF
#define | TIM_FLAG_BREAK TIM_SR_BIF
#define | TIM_FLAG_BREAK2 TIM_SR_B2IF
#define | TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF
#define | TIM_FLAG_CC1OF TIM_SR_CC1OF
#define | TIM_FLAG_CC2OF TIM_SR_CC2OF
#define | TIM_FLAG_CC3OF TIM_SR_CC3OF
#define | TIM_FLAG_CC4OF TIM_SR_CC4OF
#define | TIM_CHANNEL_1 0x00000000U
#define | TIM_CHANNEL_2 0x00000004U
#define | TIM_CHANNEL_3 0x00000008U
#define | TIM_CHANNEL_4 0x0000000CU
#define | TIM_CHANNEL_5 0x00000010U
#define | TIM_CHANNEL_6 0x00000014U
#define | TIM_CHANNEL_ALL 0x0000003CU
#define | TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1
#define | TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0
#define | TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0
#define | TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1
#define | TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2
#define | TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3
#define | TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED
#define | TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1
#define | TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2
#define | TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF
#define | TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
#define | TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
#define | TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
#define | TIM_OSSR_ENABLE TIM_BDTR_OSSR
#define | TIM_OSSR_DISABLE 0x00000000U
#define | TIM_OSSI_ENABLE TIM_BDTR_OSSI
#define | TIM_OSSI_DISABLE 0x00000000U
#define | TIM_LOCKLEVEL_OFF 0x00000000U
#define | TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0
#define | TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1
#define | TIM_LOCKLEVEL_3 TIM_BDTR_LOCK
#define | TIM_BREAK_ENABLE TIM_BDTR_BKE
#define | TIM_BREAK_DISABLE 0x00000000U
#define | TIM_BREAKPOLARITY_LOW 0x00000000U
#define | TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP
#define | TIM_BREAK2_DISABLE 0x00000000U
#define | TIM_BREAK2_ENABLE TIM_BDTR_BK2E
#define | TIM_BREAK2POLARITY_LOW 0x00000000U
#define | TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P
#define | TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U
#define | TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE
#define | TIM_GROUPCH5_NONE 0x00000000U /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
#define | TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
#define | TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
#define | TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
#define | TIM_TRGO_RESET 0x00000000U
#define | TIM_TRGO_ENABLE TIM_CR2_MMS_0
#define | TIM_TRGO_UPDATE TIM_CR2_MMS_1
#define | TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
#define | TIM_TRGO_OC1REF TIM_CR2_MMS_2
#define | TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)
#define | TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)
#define | TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
#define | TIM_TRGO2_RESET 0x00000000U
#define | TIM_TRGO2_ENABLE TIM_CR2_MMS2_0
#define | TIM_TRGO2_UPDATE TIM_CR2_MMS2_1
#define | TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC1REF TIM_CR2_MMS2_2
#define | TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)
#define | TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC5REF TIM_CR2_MMS2_3
#define | TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)
#define | TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)
#define | TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
#define | TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)
#define | TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM
#define | TIM_MASTERSLAVEMODE_DISABLE 0x00000000U
#define | TIM_SLAVEMODE_DISABLE 0x00000000U
#define | TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2
#define | TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)
#define | TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)
#define | TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3
#define | TIM_OCMODE_TIMING 0x00000000U
#define | TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0
#define | TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1
#define | TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
#define | TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2
#define | TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3
#define | TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M
#define | TIM_TS_ITR0 0x00000000U
#define | TIM_TS_ITR1 TIM_SMCR_TS_0
#define | TIM_TS_ITR2 TIM_SMCR_TS_1
#define | TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
#define | TIM_TS_TI1F_ED TIM_SMCR_TS_2
#define | TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
#define | TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
#define | TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
#define | TIM_TS_NONE 0x0000FFFFU
#define | TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
#define | TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
#define | TIM_TI1SELECTION_CH1 0x00000000U
#define | TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S
#define | TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U
#define | TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U
#define | TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U
#define | TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U
#define | TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U
#define | TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U
#define | TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U
#define | TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U
#define | TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U
#define | TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U
#define | TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U
#define | TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U
#define | TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U
#define | TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U
#define | TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U
#define | TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U
#define | TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U
#define | TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U
#define | TIM_DMA_ID_UPDATE ((uint16_t) 0x0000)
#define | TIM_DMA_ID_CC1 ((uint16_t) 0x0001)
#define | TIM_DMA_ID_CC2 ((uint16_t) 0x0002)
#define | TIM_DMA_ID_CC3 ((uint16_t) 0x0003)
#define | TIM_DMA_ID_CC4 ((uint16_t) 0x0004)
#define | TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005)
#define | TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006)
#define | TIM_CCx_ENABLE 0x00000001U
#define | TIM_CCx_DISABLE 0x00000000U
#define | TIM_CCxN_ENABLE 0x00000004U
#define | TIM_CCxN_DISABLE 0x00000000U
#define | TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL
#define | TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL
#define | TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR SYSCFG_CFGR2_SPL
#define | TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL
#define | __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__)
Reset TIM handle state.
#define | __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
Enable the TIM peripheral.
#define | __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
Enable the TIM main Output.
#define | __HAL_TIM_DISABLE(__HANDLE__)
Disable the TIM peripheral.
#define | __HAL_TIM_MOE_DISABLE(__HANDLE__)
Disable the TIM main Output.
#define | __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
Disable the TIM main Output.
#define | __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
Enable the specified TIM interrupt.
#define | __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
Disable the specified TIM interrupt.
#define | __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
Enable the specified DMA request.
#define | __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
Disable the specified DMA request.
#define | __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
Check whether the specified TIM interrupt flag is set or not.
#define | __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clear the specified TIM interrupt flag.
#define | __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified TIM interrupt source is enabled or not.
#define | __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
Clear the TIM interrupt pending bits.
#define | __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
Indicates whether or not the TIM Counter is used as downcounter.
#define | __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
Set the TIM Prescaler on runtime.
#define | __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
Set the TIM Counter Register value on runtime.
#define | __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
Get the TIM Counter Register value on runtime.
#define | __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__)
Set the TIM Autoreload Register value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
Get the TIM Autoreload Register value on runtime.
#define | __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__)
Set the TIM Clock Division value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
Get the TIM Clock Division value on runtime.
#define | __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__)
Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
#define | __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)
Get the TIM Input Capture prescaler on runtime.
#define | __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__)
Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
#define | __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__)
Get the TIM Capture Compare Register value on runtime.
#define | __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)
Set the TIM Output compare preload.
#define | __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)
Reset the TIM Output compare preload.
#define | __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__)
Enable fast mode for a given channel.
#define | __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__)
Disable fast mode for a given channel.
#define | __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
Set the Update Request Source (URS) bit of the TIMx_CR1 register.
#define | __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
#define | __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
Set the TIM Capture x input polarity on runtime.
#define | TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
#define | TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
#define | IS_TIM_CLEARINPUT_SOURCE(__MODE__)
#define | IS_TIM_DMA_BASE(__BASE__)
#define | IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
#define | IS_TIM_COUNTER_MODE(__MODE__)
#define | IS_TIM_CLOCKDIVISION_DIV(__DIV__)
#define | IS_TIM_AUTORELOAD_PRELOAD(PRELOAD)
#define | IS_TIM_FAST_STATE(__STATE__)
#define | IS_TIM_OC_POLARITY(__POLARITY__)
#define | IS_TIM_OCN_POLARITY(__POLARITY__)
#define | IS_TIM_OCIDLE_STATE(__STATE__)
#define | IS_TIM_OCNIDLE_STATE(__STATE__)
#define | IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__)
#define | IS_TIM_IC_POLARITY(__POLARITY__)
#define | IS_TIM_IC_SELECTION(__SELECTION__)
#define | IS_TIM_IC_PRESCALER(__PRESCALER__)
#define | IS_TIM_OPM_MODE(__MODE__)
#define | IS_TIM_ENCODER_MODE(__MODE__)
#define | IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
#define | IS_TIM_CHANNELS(__CHANNEL__)
#define | IS_TIM_OPM_CHANNELS(__CHANNEL__)
#define | IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__)
#define | IS_TIM_CLOCKSOURCE(__CLOCK__)
#define | IS_TIM_CLOCKPOLARITY(__POLARITY__)
#define | IS_TIM_CLOCKPRESCALER(__PRESCALER__)
#define | IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define | IS_TIM_CLEARINPUT_POLARITY(__POLARITY__)
#define | IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__)
#define | IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define | IS_TIM_OSSR_STATE(__STATE__)
#define | IS_TIM_OSSI_STATE(__STATE__)
#define | IS_TIM_LOCK_LEVEL(__LEVEL__)
#define | IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
#define | IS_TIM_BREAK_STATE(__STATE__)
#define | IS_TIM_BREAK_POLARITY(__POLARITY__)
#define | IS_TIM_BREAK2_STATE(__STATE__)
#define | IS_TIM_BREAK2_POLARITY(__POLARITY__)
#define | IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__)
#define | IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
#define | IS_TIM_TRGO_SOURCE(__SOURCE__)
#define | IS_TIM_TRGO2_SOURCE(__SOURCE__)
#define | IS_TIM_MSM_STATE(__STATE__)
#define | IS_TIM_SLAVE_MODE(__MODE__)
#define | IS_TIM_PWM_MODE(__MODE__)
#define | IS_TIM_OC_MODE(__MODE__)
#define | IS_TIM_TRIGGER_SELECTION(__SELECTION__)
#define | IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__)
#define | IS_TIM_TRIGGERPOLARITY(__POLARITY__)
#define | IS_TIM_TRIGGERPRESCALER(__PRESCALER__)
#define | IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define | IS_TIM_TI1SELECTION(__TI1SELECTION__)
#define | IS_TIM_DMA_LENGTH(__LENGTH__)
#define | IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define | IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
#define | IS_TIM_BREAK_SYSTEM(__CONFIG__)
#define | IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__)
#define | TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__)
#define | TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__)
#define | TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
#define | TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__)

Typedefs

typedef struct __TIM_HandleTypeDef | TIM_HandleTypeDef
TIM Time Base Handle Structure definition.
typedef void(* | pTIM_CallbackTypeDef )(TIM_HandleTypeDef *htim)
HAL TIM Callback pointer definition.

Enumerations

enum HAL_TIM_StateTypeDef {
HAL_TIM_STATE_RESET = 0x00U, HAL_TIM_STATE_READY = 0x01U, HAL_TIM_STATE_BUSY = 0x02U, HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04U
}
HAL State structures definition. More...
enum HAL_TIM_ActiveChannel {
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U
}
HAL Active channel structures definition. More...
enum HAL_TIM_CallbackIDTypeDef {
HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U, HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U, HAL_TIM_IC_MSPINIT_CB_ID = 0x02U, HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U,
HAL_TIM_OC_MSPINIT_CB_ID = 0x04U, HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U, HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U, HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U,
HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U, HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU, HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU,
HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU, HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU, HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU,
HAL_TIM_TRIGGER_CB_ID = 0x10U, HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U, HAL_TIM_IC_CAPTURE_CB_ID = 0x12U, HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U,
HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U, HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U, HAL_TIM_ERROR_CB_ID = 0x17U,
HAL_TIM_COMMUTATION_CB_ID = 0x18U, HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U, HAL_TIM_BREAK_CB_ID = 0x1AU, HAL_TIM_BREAK2_CB_ID = 0x1BU
}
HAL TIM Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_TIM_Base_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_Base_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Base peripheral.
__weak void | HAL_TIM_Base_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Base MSP.
__weak void | HAL_TIM_Base_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Base MSP.
HAL_StatusTypeDef | HAL_TIM_Base_Start (TIM_HandleTypeDef *htim)
Starts the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_OC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_OC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare MSP.
__weak void | HAL_TIM_OC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Output Compare MSP.
HAL_StatusTypeDef | HAL_TIM_OC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Init (TIM_HandleTypeDef *htim)
Initializes the TIM PWM Time Base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_PWM_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_PWM_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM PWM MSP.
__weak void | HAL_TIM_PWM_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM PWM MSP.
HAL_StatusTypeDef | HAL_TIM_PWM_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_IC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_IC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture MSP.
__weak void | HAL_TIM_IC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Input Capture MSP.
HAL_StatusTypeDef | HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Input Capture measurement in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Init (TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
Initializes the TIM One Pulse Time Base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_OnePulse_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM One Pulse.
__weak void | HAL_TIM_OnePulse_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM One Pulse MSP.
__weak void | HAL_TIM_OnePulse_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM One Pulse MSP.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Init (TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
Initializes the TIM Encoder Interface and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_Encoder_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Encoder interface.
__weak void | HAL_TIM_Encoder_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Encoder Interface MSP.
__weak void | HAL_TIM_Encoder_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Encoder Interface MSP.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
Starts the TIM Encoder Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in DMA mode.
void | HAL_TIM_IRQHandler (TIM_HandleTypeDef *htim)
This function handles TIM interrupts requests.
HAL_StatusTypeDef | HAL_TIM_OC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_PWM_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_IC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_OnePulse_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
Initializes the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_ConfigOCrefClear (TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel)
Configures the OCRef clear feature.
HAL_StatusTypeDef | HAL_TIM_ConfigClockSource (TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
Configures the clock source to be used.
HAL_StatusTypeDef | HAL_TIM_ConfigTI1Input (TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchro (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchro_IT (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stops the TIM DMA Burst mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stop the DMA burst reading.
HAL_StatusTypeDef | HAL_TIM_GenerateEvent (TIM_HandleTypeDef *htim, uint32_t EventSource)
Generate a software event.
uint32_t | HAL_TIM_ReadCapturedValue (TIM_HandleTypeDef *htim, uint32_t Channel)
Read the captured value from Capture Compare unit.
__weak void | HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef *htim)
Period elapsed callback in non-blocking mode.
__weak void | HAL_TIM_PeriodElapsedHalfCpltCallback (TIM_HandleTypeDef *htim)
Period elapsed half complete callback in non-blocking mode.
__weak void | HAL_TIM_OC_DelayElapsedCallback (TIM_HandleTypeDef *htim)
Output Compare callback in non-blocking mode.
__weak void | HAL_TIM_IC_CaptureCallback (TIM_HandleTypeDef *htim)
Input Capture callback in non-blocking mode.
__weak void | HAL_TIM_IC_CaptureHalfCpltCallback (TIM_HandleTypeDef *htim)
Input Capture half complete callback in non-blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished callback in non-blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedHalfCpltCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished half complete callback in non-blocking mode.
__weak void | HAL_TIM_TriggerCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection callback in non-blocking mode.
__weak void | HAL_TIM_TriggerHalfCpltCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection half complete callback in non-blocking mode.
__weak void | HAL_TIM_ErrorCallback (TIM_HandleTypeDef *htim)
Timer error callback in non-blocking mode.
HAL_StatusTypeDef | HAL_TIM_RegisterCallback (TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback)
Register a User TIM callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_TIM_UnRegisterCallback (TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
Unregister a TIM callback TIM callback is redirected to the weak predefined callback.
HAL_TIM_StateTypeDef | HAL_TIM_Base_GetState (TIM_HandleTypeDef *htim)
Return the TIM Base handle state.
HAL_TIM_StateTypeDef | HAL_TIM_OC_GetState (TIM_HandleTypeDef *htim)
Return the TIM OC handle state.
HAL_TIM_StateTypeDef | HAL_TIM_PWM_GetState (TIM_HandleTypeDef *htim)
Return the TIM PWM handle state.
HAL_TIM_StateTypeDef | HAL_TIM_IC_GetState (TIM_HandleTypeDef *htim)
Return the TIM Input Capture handle state.
HAL_TIM_StateTypeDef | HAL_TIM_OnePulse_GetState (TIM_HandleTypeDef *htim)
Return the TIM One Pulse Mode handle state.
HAL_TIM_StateTypeDef | HAL_TIM_Encoder_GetState (TIM_HandleTypeDef *htim)
Return the TIM Encoder Mode handle state.
void | TIM_Base_SetConfig (TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
Time Base configuration.
void | TIM_TI1_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI1 as Input.
void | TIM_OC2_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 2 configuration.
void | TIM_ETR_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
void | TIM_DMADelayPulseCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse complete callback.
void | TIM_DMADelayPulseHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse half complete callback.
void | TIM_DMAError (DMA_HandleTypeDef *hdma)
TIM DMA error callback.
void | TIM_DMACaptureCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture complete callback.
void | TIM_DMACaptureHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture half complete callback.
void | TIM_CCxChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
Enables or disables the TIM Capture Compare Channel x.
void | TIM_ResetCallback (TIM_HandleTypeDef *htim)
Reset interrupt callbacks to the legacy weak callbacks.

Detailed Description

Header file of TIM HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_tim.h.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_tim_ex.h File Reference

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Data Structures | Defines | Functions
stm32wbxx_hal_tim_ex.h File Reference

Header file of TIM HAL Extended module. More...

#include "stm32wbxx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | TIM_HallSensor_InitTypeDef
TIM Hall sensor Configuration Structure definition. More...
struct | TIMEx_BreakInputConfigTypeDef
TIM Break/Break2 input configuration. More...

Defines

#define | TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is not connected to I/O */
#define | TIM_TIM1_ETR_ADC1_AWD1 TIM1_OR_ETR_ADC1_RMP_0 /* !< TIM1_ETR is connected to ADC1 AWD1 */
#define | TIM_TIM1_ETR_ADC1_AWD2 TIM1_OR_ETR_ADC1_RMP_1 /* !< TIM1_ETR is connected to ADC1 AWD2 */
#define | TIM_TIM1_ETR_ADC1_AWD3 (TIM1_OR_ETR_ADC1_RMP_0 | TIM1_OR_ETR_ADC1_RMP_1) /* !< TIM1_ETR is connected to ADC1 AWD3 */
#define | TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 output */
#define | TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 output */
#define | TIM_TIM1_TI1_GPIO 0x00000000U /* !< TIM1 Input capture 1 is connected to I/0 */
#define | TIM_TIM1_TI1_COMP1 TIM1_OR_TI1_RMP /* !< TIM1 Input capture 1is connected to COMP1 OUT */
#define | TIM_TIM2_ITR_NC 0x00000000U /* !< TIM2 Internal trigger ITR is not connected */
#define | TIM_TIM2_ITR_USB TIM2_OR_ITR1_RMP /* !< TIM2 Internal trigger ITR is connected to USBFS SOF */
#define | TIM_TIM2_ETR_GPIO 0x00000000U /* !< TIM2 External trigger ETR is connected to I/O */
#define | TIM_TIM2_ETR_LSE TIM2_OR_ETR_RMP /* !< TIM2 External trigger ETR is connected to LSE */
#define | TIM_TIM2_ETR_COMP1 TIM2_AF1_ETRSEL_0 /* !< TIM2_ETR is connected to COMP1 output */
#define | TIM_TIM2_ETR_COMP2 TIM2_AF1_ETRSEL_1 /* !< TIM2_ETR is connected to COMP2 output */
#define | TIM_TIM2_TI4_GPIO 0x00000000U /* !< TIM2_TI4 is connected to I/O */
#define | TIM_TIM2_TI4_COMP1 TIM2_OR_TI4_RMP_0 /* !< TIM2_TI4 is connected to COMP1 OUT */
#define | TIM_TIM2_TI4_COMP2 TIM2_OR_TI4_RMP_1 /* !< TIM2_TI4 is connected to COMP1 OUT */
#define | TIM_TIM2_TI4_COMP1_COMP2 (TIM2_OR_TI4_RMP_0 | TIM2_OR_TI4_RMP_1) /* !< TIM2_TI4 is connected to COMP1 and COMP2 OUT */
#define | TIM_TIM16_TI1_GPIO 0x00000000U /* !< TIM16_TI1 is connected to I/O */
#define | TIM_TIM16_TI1_LSI TIM16_OR_TI1_RMP_0 /* !< TIM16_TI1 is connected to LSI Clock */
#define | TIM_TIM16_TI1_LSE TIM16_OR_TI1_RMP_1 /* !< TIM16_TI1 is connected to LSE Clock */
#define | TIM_TIM16_TI1_RTC (TIM16_OR_TI1_RMP_0 | TIM16_OR_TI1_RMP_1) /* !< TIM16_TI1 is connected to RTC */
#define | TIM_TIM17_TI1_GPIO 0x00000000U /* !< TIM17_TI1 is connected to I/O */
#define | TIM_TIM17_TI1_MSI TIM17_OR_TI1_RMP_0 /* !< TIM17_TI1 is connected to MSI */
#define | TIM_TIM17_TI1_HSE TIM17_OR_TI1_RMP_1 /* !< TIM17_TI1 is connected to HSE/32 */
#define | TIM_TIM17_TI1_MCO (TIM17_OR_TI1_RMP_0 | TIM17_OR_TI1_RMP_1) /* !< TIM17_TI1 is connected to MCO */
#define | TIM_BREAKINPUT_BRK 0x00000001U /* !< Timer break input */
#define | TIM_BREAKINPUT_BRK2 0x00000002U /* !< Timer break2 input */
#define | TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */
#define | TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /* !< The COMP1 output is connected to the break input */
#define | TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /* !< The COMP2 output is connected to the break input */
#define | TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /* !< Break input source is disabled */
#define | TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /* !< Break input source is enabled */
#define | TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /* !< Break input source is active low */
#define | TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /* !< Break input source is active_high */
#define | IS_TIM_REMAP(__INSTANCE__, __REMAP__)
#define | IS_TIM_BREAKINPUT(__BREAKINPUT__)
#define | IS_TIM_BREAKINPUTSOURCE(__SOURCE__)
#define | IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__)
#define | IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__)

Functions

HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Init (TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
Initializes the TIM Hall Sensor Interface and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Hall Sensor interface.
__weak void | HAL_TIMEx_HallSensor_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Hall Sensor MSP.
__weak void | HAL_TIMEx_HallSensor_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Hall Sensor MSP.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Hall sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutEvent (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutEvent_IT (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with interrupt.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutEvent_DMA (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with DMA.
HAL_StatusTypeDef | HAL_TIMEx_MasterConfigSynchronization (TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig)
Configures the TIM in master mode.
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakDeadTime (TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakInput (TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
Configures the break input source.
HAL_StatusTypeDef | HAL_TIMEx_GroupChannel5 (TIM_HandleTypeDef *htim, uint32_t Channels)
Group channel 5 and channel 1, 2 or 3.
HAL_StatusTypeDef | HAL_TIMEx_RemapConfig (TIM_HandleTypeDef *htim, uint32_t Remap)
Configures the TIMx Remapping input capabilities.
__weak void | HAL_TIMEx_CommutCallback (TIM_HandleTypeDef *htim)
Hall commutation changed callback in non-blocking mode.
__weak void | HAL_TIMEx_CommutHalfCpltCallback (TIM_HandleTypeDef *htim)
Hall commutation changed half complete callback in non-blocking mode.
__weak void | HAL_TIMEx_BreakCallback (TIM_HandleTypeDef *htim)
Hall Break detection callback in non-blocking mode.
__weak void | HAL_TIMEx_Break2Callback (TIM_HandleTypeDef *htim)
Hall Break2 detection callback in non blocking mode.
HAL_TIM_StateTypeDef | HAL_TIMEx_HallSensor_GetState (TIM_HandleTypeDef *htim)
Return the TIM Hall Sensor interface handle state.
void | TIMEx_DMACommutationCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation callback.
void | TIMEx_DMACommutationHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation half complete callback.

Detailed Description

Header file of TIM HAL Extended module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_tim_ex.h.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_tsc.h File Reference

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stm32wbxx_hal_tsc.h File Reference

Header file of TSC HAL module. More...

#include "stm32wbxx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | TSC_InitTypeDef
TSC init structure definition. More...
struct | TSC_IOConfigTypeDef
TSC IOs configuration structure definition. More...
struct | __TSC_HandleTypeDef
TSC handle Structure definition. More...

Defines

#define | HAL_TSC_ERROR_NONE 0x00000000UL
#define | HAL_TSC_ERROR_INVALID_CALLBACK 0x00000001UL
#define | TSC_CTPH_1CYCLE 0x00000000UL
#define | TSC_CTPH_2CYCLES TSC_CR_CTPH_0
#define | TSC_CTPH_3CYCLES TSC_CR_CTPH_1
#define | TSC_CTPH_4CYCLES (TSC_CR_CTPH_1 | TSC_CR_CTPH_0)
#define | TSC_CTPH_5CYCLES TSC_CR_CTPH_2
#define | TSC_CTPH_6CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_0)
#define | TSC_CTPH_7CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1)
#define | TSC_CTPH_8CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0)
#define | TSC_CTPH_9CYCLES TSC_CR_CTPH_3
#define | TSC_CTPH_10CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_0)
#define | TSC_CTPH_11CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1)
#define | TSC_CTPH_12CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0)
#define | TSC_CTPH_13CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2)
#define | TSC_CTPH_14CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_0)
#define | TSC_CTPH_15CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1)
#define | TSC_CTPH_16CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0)
#define | TSC_CTPL_1CYCLE 0x00000000UL
#define | TSC_CTPL_2CYCLES TSC_CR_CTPL_0
#define | TSC_CTPL_3CYCLES TSC_CR_CTPL_1
#define | TSC_CTPL_4CYCLES (TSC_CR_CTPL_1 | TSC_CR_CTPL_0)
#define | TSC_CTPL_5CYCLES TSC_CR_CTPL_2
#define | TSC_CTPL_6CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_0)
#define | TSC_CTPL_7CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1)
#define | TSC_CTPL_8CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0)
#define | TSC_CTPL_9CYCLES TSC_CR_CTPL_3
#define | TSC_CTPL_10CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_0)
#define | TSC_CTPL_11CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1)
#define | TSC_CTPL_12CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0)
#define | TSC_CTPL_13CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2)
#define | TSC_CTPL_14CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0)
#define | TSC_CTPL_15CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1)
#define | TSC_CTPL_16CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0)
#define | TSC_SS_PRESC_DIV1 0x00000000UL
#define | TSC_SS_PRESC_DIV2 TSC_CR_SSPSC
#define | TSC_PG_PRESC_DIV1 0x00000000UL
#define | TSC_PG_PRESC_DIV2 TSC_CR_PGPSC_0
#define | TSC_PG_PRESC_DIV4 TSC_CR_PGPSC_1
#define | TSC_PG_PRESC_DIV8 (TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0)
#define | TSC_PG_PRESC_DIV16 TSC_CR_PGPSC_2
#define | TSC_PG_PRESC_DIV32 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_0)
#define | TSC_PG_PRESC_DIV64 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1)
#define | TSC_PG_PRESC_DIV128 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0)
#define | TSC_MCV_255 0x00000000UL
#define | TSC_MCV_511 TSC_CR_MCV_0
#define | TSC_MCV_1023 TSC_CR_MCV_1
#define | TSC_MCV_2047 (TSC_CR_MCV_1 | TSC_CR_MCV_0)
#define | TSC_MCV_4095 TSC_CR_MCV_2
#define | TSC_MCV_8191 (TSC_CR_MCV_2 | TSC_CR_MCV_0)
#define | TSC_MCV_16383 (TSC_CR_MCV_2 | TSC_CR_MCV_1)
#define | TSC_IODEF_OUT_PP_LOW 0x00000000UL
#define | TSC_IODEF_IN_FLOAT TSC_CR_IODEF
#define | TSC_SYNC_POLARITY_FALLING 0x00000000UL
#define | TSC_SYNC_POLARITY_RISING TSC_CR_SYNCPOL
#define | TSC_ACQ_MODE_NORMAL 0x00000000UL
#define | TSC_ACQ_MODE_SYNCHRO TSC_CR_AM
#define | TSC_IT_EOA TSC_IER_EOAIE
#define | TSC_IT_MCE TSC_IER_MCEIE
#define | TSC_FLAG_EOA TSC_ISR_EOAF
#define | TSC_FLAG_MCE TSC_ISR_MCEF
#define | TSC_GROUP1 (0x1UL << TSC_GROUP1_IDX)
#define | TSC_GROUP2 (0x1UL << TSC_GROUP2_IDX)
#define | TSC_GROUP3 (0x1UL << TSC_GROUP3_IDX)
#define | TSC_GROUP4 (0x1UL << TSC_GROUP4_IDX)
#define | TSC_GROUP5 (0x1UL << TSC_GROUP5_IDX)
#define | TSC_GROUP6 (0x1UL << TSC_GROUP6_IDX)
#define | TSC_GROUP7 (0x1UL << TSC_GROUP7_IDX)
#define | TSC_GROUP1_IO1 TSC_IOCCR_G1_IO1
#define | TSC_GROUP1_IO2 TSC_IOCCR_G1_IO2
#define | TSC_GROUP1_IO3 TSC_IOCCR_G1_IO3
#define | TSC_GROUP1_IO4 TSC_IOCCR_G1_IO4
#define | TSC_GROUP2_IO1 TSC_IOCCR_G2_IO1
#define | TSC_GROUP2_IO2 TSC_IOCCR_G2_IO2
#define | TSC_GROUP2_IO3 TSC_IOCCR_G2_IO3
#define | TSC_GROUP2_IO4 TSC_IOCCR_G2_IO4
#define | TSC_GROUP3_IO1 TSC_IOCCR_G3_IO1
#define | TSC_GROUP3_IO2 TSC_IOCCR_G3_IO2
#define | TSC_GROUP3_IO3 TSC_IOCCR_G3_IO3
#define | TSC_GROUP3_IO4 TSC_IOCCR_G3_IO4
#define | TSC_GROUP4_IO1 TSC_IOCCR_G4_IO1
#define | TSC_GROUP4_IO2 TSC_IOCCR_G4_IO2
#define | TSC_GROUP4_IO3 TSC_IOCCR_G4_IO3
#define | TSC_GROUP4_IO4 TSC_IOCCR_G4_IO4
#define | TSC_GROUP5_IO1 TSC_IOCCR_G5_IO1
#define | TSC_GROUP5_IO2 TSC_IOCCR_G5_IO2
#define | TSC_GROUP5_IO3 TSC_IOCCR_G5_IO3
#define | TSC_GROUP5_IO4 TSC_IOCCR_G5_IO4
#define | TSC_GROUP6_IO1 TSC_IOCCR_G6_IO1
#define | TSC_GROUP6_IO2 TSC_IOCCR_G6_IO2
#define | TSC_GROUP6_IO3 TSC_IOCCR_G6_IO3
#define | TSC_GROUP6_IO4 TSC_IOCCR_G6_IO4
#define | TSC_GROUP7_IO1 TSC_IOCCR_G7_IO1
#define | TSC_GROUP7_IO2 TSC_IOCCR_G7_IO2
#define | TSC_GROUP7_IO3 TSC_IOCCR_G7_IO3
#define | TSC_GROUP7_IO4 TSC_IOCCR_G7_IO4
#define | __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__)
Reset TSC handle state.
#define | __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE)
Enable the TSC peripheral.
#define | __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_TSCE))
Disable the TSC peripheral.
#define | __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START)
Start acquisition.
#define | __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_START))
Stop acquisition.
#define | __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_IODEF))
Set IO default mode to output push-pull low.
#define | __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF)
Set IO default mode to input floating.
#define | __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_SYNCPOL))
Set synchronization polarity to falling edge.
#define | __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL)
Set synchronization polarity to rising edge and high level.
#define | __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
Enable TSC interrupt.
#define | __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
Disable TSC interrupt.
#define | __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified TSC interrupt source is enabled or not.
#define | __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
Check whether the specified TSC flag is set or not.
#define | __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the TSC's pending flag.
#define | __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__))
Enable schmitt trigger hysteresis on a group of IOs.
#define | __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (~(__GX_IOY_MASK__)))
Disable schmitt trigger hysteresis on a group of IOs.
#define | __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (~(__GX_IOY_MASK__)))
Open analog switch on a group of IOs.
#define | __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__))
Close analog switch on a group of IOs.
#define | __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__))
Enable a group of IOs in channel mode.
#define | __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (~(__GX_IOY_MASK__)))
Disable a group of channel IOs.
#define | __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__))
Enable a group of IOs in sampling mode.
#define | __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (~(__GX_IOY_MASK__)))
Disable a group of sampling IOs.
#define | __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__))
Enable acquisition groups.
#define | __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (~(__GX_MASK__)))
Disable acquisition groups.
#define | __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) ((((__HANDLE__)->Instance->IOGCSR & (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) == (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING)
Gets acquisition group status.
#define | IS_TSC_CTPH(__VALUE__)
#define | IS_TSC_CTPL(__VALUE__)
#define | IS_TSC_SS(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE) || ((FunctionalState)(__VALUE__) == ENABLE))
#define | IS_TSC_SSD(__VALUE__) (((__VALUE__) == 0UL) || (((__VALUE__) > 0UL) && ((__VALUE__) < 128UL)))
#define | IS_TSC_SS_PRESC(__VALUE__) (((__VALUE__) == TSC_SS_PRESC_DIV1) || ((__VALUE__) == TSC_SS_PRESC_DIV2))
#define | IS_TSC_PG_PRESC(__VALUE__)
#define | IS_TSC_MCV(__VALUE__)
#define | IS_TSC_IODEF(__VALUE__) (((__VALUE__) == TSC_IODEF_OUT_PP_LOW) || ((__VALUE__) == TSC_IODEF_IN_FLOAT))
#define | IS_TSC_SYNC_POL(__VALUE__) (((__VALUE__) == TSC_SYNC_POLARITY_FALLING) || ((__VALUE__) == TSC_SYNC_POLARITY_RISING))
#define | IS_TSC_ACQ_MODE(__VALUE__) (((__VALUE__) == TSC_ACQ_MODE_NORMAL) || ((__VALUE__) == TSC_ACQ_MODE_SYNCHRO))
#define | IS_TSC_MCE_IT(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE) || ((FunctionalState)(__VALUE__) == ENABLE))
#define | IS_TSC_GROUP_INDEX(__VALUE__) (((__VALUE__) == 0UL) || (((__VALUE__) > 0UL) && ((__VALUE__) < (uint32_t)TSC_NB_OF_GROUPS)))
#define | IS_TSC_GROUP(__VALUE__)

Typedefs

typedef struct __TSC_HandleTypeDef | TSC_HandleTypeDef
TSC handle Structure definition.
typedef void(* | pTSC_CallbackTypeDef )(TSC_HandleTypeDef *htsc)
HAL TSC Callback pointer definition.

Enumerations

enum | HAL_TSC_StateTypeDef { HAL_TSC_STATE_RESET = 0x00UL, HAL_TSC_STATE_READY = 0x01UL, HAL_TSC_STATE_BUSY = 0x02UL, HAL_TSC_STATE_ERROR = 0x03UL }
TSC state structure definition. More...
enum | TSC_GroupStatusTypeDef { TSC_GROUP_ONGOING = 0x00UL, TSC_GROUP_COMPLETED = 0x01UL }
TSC group status structure definition. More...
enum {
TSC_GROUP1_IDX = 0x00UL, TSC_GROUP2_IDX, TSC_GROUP3_IDX, TSC_GROUP4_IDX,
TSC_GROUP5_IDX, TSC_GROUP6_IDX, TSC_GROUP7_IDX, TSC_NB_OF_GROUPS
}
enum | HAL_TSC_CallbackIDTypeDef { HAL_TSC_CONV_COMPLETE_CB_ID = 0x00UL, HAL_TSC_ERROR_CB_ID = 0x01UL, HAL_TSC_MSPINIT_CB_ID = 0x02UL, HAL_TSC_MSPDEINIT_CB_ID = 0x03UL }
HAL TSC Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_TSC_Init (TSC_HandleTypeDef *htsc)
Initialize the TSC peripheral according to the specified parameters in the TSC_InitTypeDef structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_TSC_DeInit (TSC_HandleTypeDef *htsc)
Deinitialize the TSC peripheral registers to their default reset values.
__weak void | HAL_TSC_MspInit (TSC_HandleTypeDef *htsc)
Initialize the TSC MSP.
__weak void | HAL_TSC_MspDeInit (TSC_HandleTypeDef *htsc)
DeInitialize the TSC MSP.
HAL_StatusTypeDef | HAL_TSC_RegisterCallback (TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID, pTSC_CallbackTypeDef pCallback)
Register a User TSC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_TSC_UnRegisterCallback (TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID)
Unregister an TSC Callback TSC callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_TSC_Start (TSC_HandleTypeDef *htsc)
Start the acquisition.
HAL_StatusTypeDef | HAL_TSC_Start_IT (TSC_HandleTypeDef *htsc)
Start the acquisition in interrupt mode.
HAL_StatusTypeDef | HAL_TSC_Stop (TSC_HandleTypeDef *htsc)
Stop the acquisition previously launched in polling mode.
HAL_StatusTypeDef | HAL_TSC_Stop_IT (TSC_HandleTypeDef *htsc)
Stop the acquisition previously launched in interrupt mode.
HAL_StatusTypeDef | HAL_TSC_PollForAcquisition (TSC_HandleTypeDef *htsc)
Start acquisition and wait until completion.
TSC_GroupStatusTypeDef | HAL_TSC_GroupGetStatus (TSC_HandleTypeDef *htsc, uint32_t gx_index)
Get the acquisition status for a group.
uint32_t | HAL_TSC_GroupGetValue (TSC_HandleTypeDef *htsc, uint32_t gx_index)
Get the acquisition measure for a group.
HAL_StatusTypeDef | HAL_TSC_IOConfig (TSC_HandleTypeDef *htsc, TSC_IOConfigTypeDef *config)
Configure TSC IOs.
HAL_StatusTypeDef | HAL_TSC_IODischarge (TSC_HandleTypeDef *htsc, FunctionalState choice)
Discharge TSC IOs.
HAL_TSC_StateTypeDef | HAL_TSC_GetState (TSC_HandleTypeDef *htsc)
Return the TSC handle state.
void | HAL_TSC_IRQHandler (TSC_HandleTypeDef *htsc)
Handle TSC interrupt request.
__weak void | HAL_TSC_ConvCpltCallback (TSC_HandleTypeDef *htsc)
Acquisition completed callback in non-blocking mode.
__weak void | HAL_TSC_ErrorCallback (TSC_HandleTypeDef *htsc)
Error callback in non-blocking mode.

Detailed Description

Header file of TSC HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_tsc.h.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_uart.h File Reference

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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32wbxx_hal_uart.h File Reference

Header file of UART HAL module. More...

#include "stm32wbxx_hal_def.h"
#include "stm32wbxx_hal_uart_ex.h"

Go to the source code of this file.

Data Structures

struct | UART_InitTypeDef
UART Init Structure definition. More...
struct | UART_AdvFeatureInitTypeDef
UART Advanced Features initialization structure definition. More...
struct | __UART_HandleTypeDef
UART handle Structure definition. More...

Defines

#define | HAL_UART_STATE_RESET 0x00000000U
#define | HAL_UART_STATE_READY 0x00000020U
#define | HAL_UART_STATE_BUSY 0x00000024U
#define | HAL_UART_STATE_BUSY_TX 0x00000021U
#define | HAL_UART_STATE_BUSY_RX 0x00000022U
#define | HAL_UART_STATE_BUSY_TX_RX 0x00000023U
#define | HAL_UART_STATE_TIMEOUT 0x000000A0U
#define | HAL_UART_STATE_ERROR 0x000000E0U
#define | HAL_UART_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_UART_ERROR_PE ((uint32_t)0x00000001U)
#define | HAL_UART_ERROR_NE ((uint32_t)0x00000002U)
#define | HAL_UART_ERROR_FE ((uint32_t)0x00000004U)
#define | HAL_UART_ERROR_ORE ((uint32_t)0x00000008U)
#define | HAL_UART_ERROR_DMA ((uint32_t)0x00000010U)
#define | HAL_UART_ERROR_RTO ((uint32_t)0x00000020U)
#define | HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U)
#define | UART_STOPBITS_0_5 USART_CR2_STOP_0
#define | UART_STOPBITS_1 0x00000000U
#define | UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define | UART_STOPBITS_2 USART_CR2_STOP_1
#define | UART_PARITY_NONE 0x00000000U
#define | UART_PARITY_EVEN USART_CR1_PCE
#define | UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)
#define | UART_HWCONTROL_NONE 0x00000000U
#define | UART_HWCONTROL_RTS USART_CR3_RTSE
#define | UART_HWCONTROL_CTS USART_CR3_CTSE
#define | UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
#define | UART_MODE_RX USART_CR1_RE
#define | UART_MODE_TX USART_CR1_TE
#define | UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)
#define | UART_STATE_DISABLE 0x00000000U
#define | UART_STATE_ENABLE USART_CR1_UE
#define | UART_OVERSAMPLING_16 0x00000000U
#define | UART_OVERSAMPLING_8 USART_CR1_OVER8
#define | UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U
#define | UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT
#define | UART_PRESCALER_DIV1 0x00000000U
#define | UART_PRESCALER_DIV2 0x00000001U
#define | UART_PRESCALER_DIV4 0x00000002U
#define | UART_PRESCALER_DIV6 0x00000003U
#define | UART_PRESCALER_DIV8 0x00000004U
#define | UART_PRESCALER_DIV10 0x00000005U
#define | UART_PRESCALER_DIV12 0x00000006U
#define | UART_PRESCALER_DIV16 0x00000007U
#define | UART_PRESCALER_DIV32 0x00000008U
#define | UART_PRESCALER_DIV64 0x00000009U
#define | UART_PRESCALER_DIV128 0x0000000AU
#define | UART_PRESCALER_DIV256 0x0000000BU
#define | UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U
#define | UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0
#define | UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1
#define | UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE
#define | UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U
#define | UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN
#define | UART_LIN_DISABLE 0x00000000U
#define | UART_LIN_ENABLE USART_CR2_LINEN
#define | UART_LINBREAKDETECTLENGTH_10B 0x00000000U
#define | UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL
#define | UART_DMA_TX_DISABLE 0x00000000U
#define | UART_DMA_TX_ENABLE USART_CR3_DMAT
#define | UART_DMA_RX_DISABLE 0x00000000U
#define | UART_DMA_RX_ENABLE USART_CR3_DMAR
#define | UART_HALF_DUPLEX_DISABLE 0x00000000U
#define | UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL
#define | UART_WAKEUPMETHOD_IDLELINE 0x00000000U
#define | UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE
#define | UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ
#define | UART_SENDBREAK_REQUEST USART_RQR_SBKRQ
#define | UART_MUTE_MODE_REQUEST USART_RQR_MMRQ
#define | UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ
#define | UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ
#define | UART_ADVFEATURE_NO_INIT 0x00000000U
#define | UART_ADVFEATURE_TXINVERT_INIT 0x00000001U
#define | UART_ADVFEATURE_RXINVERT_INIT 0x00000002U
#define | UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U
#define | UART_ADVFEATURE_SWAP_INIT 0x00000008U
#define | UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U
#define | UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U
#define | UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U
#define | UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U
#define | UART_ADVFEATURE_TXINV_DISABLE 0x00000000U
#define | UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV
#define | UART_ADVFEATURE_RXINV_DISABLE 0x00000000U
#define | UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV
#define | UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U
#define | UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV
#define | UART_ADVFEATURE_SWAP_DISABLE 0x00000000U
#define | UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP
#define | UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U
#define | UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS
#define | UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U
#define | UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN
#define | UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U
#define | UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE
#define | UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U
#define | UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST
#define | UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U
#define | UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM
#define | UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U
#define | UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME
#define | UART_CR2_ADDRESS_LSB_POS 24U
#define | UART_WAKEUP_ON_ADDRESS 0x00000000U
#define | UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1
#define | UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS
#define | UART_DE_POLARITY_HIGH 0x00000000U
#define | UART_DE_POLARITY_LOW USART_CR3_DEP
#define | UART_CR1_DEAT_ADDRESS_LSB_POS 21U
#define | UART_CR1_DEDT_ADDRESS_LSB_POS 16U
#define | UART_IT_MASK 0x001FU
#define | HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU
#define | UART_FLAG_TXFT USART_ISR_TXFT
#define | UART_FLAG_RXFT USART_ISR_RXFT
#define | UART_FLAG_RXFF USART_ISR_RXFF
#define | UART_FLAG_TXFE USART_ISR_TXFE
#define | UART_FLAG_REACK USART_ISR_REACK
#define | UART_FLAG_TEACK USART_ISR_TEACK
#define | UART_FLAG_WUF USART_ISR_WUF
#define | UART_FLAG_RWU USART_ISR_RWU
#define | UART_FLAG_SBKF USART_ISR_SBKF
#define | UART_FLAG_CMF USART_ISR_CMF
#define | UART_FLAG_BUSY USART_ISR_BUSY
#define | UART_FLAG_ABRF USART_ISR_ABRF
#define | UART_FLAG_ABRE USART_ISR_ABRE
#define | UART_FLAG_RTOF USART_ISR_RTOF
#define | UART_FLAG_CTS USART_ISR_CTS
#define | UART_FLAG_CTSIF USART_ISR_CTSIF
#define | UART_FLAG_LBDF USART_ISR_LBDF
#define | UART_FLAG_TXE USART_ISR_TXE_TXFNF
#define | UART_FLAG_TXFNF USART_ISR_TXE_TXFNF
#define | UART_FLAG_TC USART_ISR_TC
#define | UART_FLAG_RXNE USART_ISR_RXNE_RXFNE
#define | UART_FLAG_RXFNE USART_ISR_RXNE_RXFNE
#define | UART_FLAG_IDLE USART_ISR_IDLE
#define | UART_FLAG_ORE USART_ISR_ORE
#define | UART_FLAG_NE USART_ISR_NE
#define | UART_FLAG_FE USART_ISR_FE
#define | UART_FLAG_PE USART_ISR_PE
#define | UART_IT_PE 0x0028U
#define | UART_IT_TXE 0x0727U
#define | UART_IT_TXFNF 0x0727U
#define | UART_IT_TC 0x0626U
#define | UART_IT_RXNE 0x0525U
#define | UART_IT_RXFNE 0x0525U
#define | UART_IT_IDLE 0x0424U
#define | UART_IT_LBD 0x0846U
#define | UART_IT_CTS 0x096AU
#define | UART_IT_CM 0x112EU
#define | UART_IT_WUF 0x1476U
#define | UART_IT_RXFF 0x183FU
#define | UART_IT_TXFE 0x173EU
#define | UART_IT_RXFT 0x1A7CU
#define | UART_IT_TXFT 0x1B77U
#define | UART_IT_RTO 0x0B3AU
#define | UART_IT_ERR 0x0060U
#define | UART_IT_ORE 0x0300U
#define | UART_IT_NE 0x0200U
#define | UART_IT_FE 0x0100U
#define | UART_CLEAR_PEF USART_ICR_PECF
#define | UART_CLEAR_FEF USART_ICR_FECF
#define | UART_CLEAR_NEF USART_ICR_NECF
#define | UART_CLEAR_OREF USART_ICR_ORECF
#define | UART_CLEAR_IDLEF USART_ICR_IDLECF
#define | UART_CLEAR_TXFECF USART_ICR_TXFECF
#define | UART_CLEAR_TCF USART_ICR_TCCF
#define | UART_CLEAR_LBDF USART_ICR_LBDCF
#define | UART_CLEAR_CTSF USART_ICR_CTSCF
#define | UART_CLEAR_CMF USART_ICR_CMCF
#define | UART_CLEAR_WUF USART_ICR_WUCF
#define | UART_CLEAR_RTOF USART_ICR_RTOCF
#define | __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)
Reset UART handle states.
#define | __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)
Flush the UART Data registers.
#define | __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified UART pending flag.
#define | __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
Clear the UART PE pending flag.
#define | __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
Clear the UART FE pending flag.
#define | __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
Clear the UART NE pending flag.
#define | __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
Clear the UART ORE pending flag.
#define | __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
Clear the UART IDLE pending flag.
#define | __HAL_UART_CLEAR_TXFECF(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF)
Clear the UART TX FIFO empty clear flag.
#define | __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified UART flag is set or not.
#define | __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified UART interrupt.
#define | __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified UART interrupt.
#define | __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__)
Check whether the specified UART interrupt has occurred or not.
#define | __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified UART interrupt source is enabled or not.
#define | __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified UART ISR flag, in setting the proper ICR register flag.
#define | __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
Set a specific UART request flag.
#define | __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the UART one bit sample method.
#define | __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
Disable the UART one bit sample method.
#define | __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable UART.
#define | __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable UART.
#define | __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)
Enable CTS flow control.
#define | __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)
Disable CTS flow control.
#define | __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)
Enable RTS flow control.
#define | __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)
Disable RTS flow control.
#define | UART_GET_DIV_FACTOR(__CLOCKPRESCALER__)
Get UART clok division factor from clock prescaler value.
#define | UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__)
BRR division operation to set BRR register with LPUART.
#define | UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)
BRR division operation to set BRR register in 8-bit oversampling mode.
#define | UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__)
BRR division operation to set BRR register in 16-bit oversampling mode.
#define | UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance))
Check whether or not UART instance is Low Power UART.
#define | IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 8000001U)
Check UART Baud rate.
#define | IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
Check UART assertion time.
#define | IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
Check UART deassertion time.
#define | IS_UART_STOPBITS(__STOPBITS__)
Ensure that UART frame number of stop bits is valid.
#define | IS_LPUART_STOPBITS(__STOPBITS__)
Ensure that LPUART frame number of stop bits is valid.
#define | IS_UART_PARITY(__PARITY__)
Ensure that UART frame parity is valid.
#define | IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)
Ensure that UART hardware flow control is valid.
#define | IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
Ensure that UART communication mode is valid.
#define | IS_UART_STATE(__STATE__)
Ensure that UART state is valid.
#define | IS_UART_OVERSAMPLING(__SAMPLING__)
Ensure that UART oversampling is valid.
#define | IS_UART_ONE_BIT_SAMPLE(__ONEBIT__)
Ensure that UART frame sampling is valid.
#define | IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__)
Ensure that UART auto Baud rate detection mode is valid.
#define | IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__)
Ensure that UART receiver timeout setting is valid.
#define | IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
Check the receiver timeout value.
#define | IS_UART_LIN(__LIN__)
Ensure that UART LIN state is valid.
#define | IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__)
Ensure that UART LIN break detection length is valid.
#define | IS_UART_DMA_TX(__DMATX__)
Ensure that UART DMA TX state is valid.
#define | IS_UART_DMA_RX(__DMARX__)
Ensure that UART DMA RX state is valid.
#define | IS_UART_HALF_DUPLEX(__HDSEL__)
Ensure that UART half-duplex state is valid.
#define | IS_UART_WAKEUPMETHOD(__WAKEUP__)
Ensure that UART wake-up method is valid.
#define | IS_UART_REQUEST_PARAMETER(__PARAM__)
Ensure that UART request parameter is valid.
#define | IS_UART_ADVFEATURE_INIT(__INIT__)
Ensure that UART advanced features initialization is valid.
#define | IS_UART_ADVFEATURE_TXINV(__TXINV__)
Ensure that UART frame TX inversion setting is valid.
#define | IS_UART_ADVFEATURE_RXINV(__RXINV__)
Ensure that UART frame RX inversion setting is valid.
#define | IS_UART_ADVFEATURE_DATAINV(__DATAINV__)
Ensure that UART frame data inversion setting is valid.
#define | IS_UART_ADVFEATURE_SWAP(__SWAP__)
Ensure that UART frame RX/TX pins swap setting is valid.
#define | IS_UART_OVERRUN(__OVERRUN__)
Ensure that UART frame overrun setting is valid.
#define | IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__)
Ensure that UART auto Baud rate state is valid.
#define | IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__)
Ensure that UART DMA enabling or disabling on error setting is valid.
#define | IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__)
Ensure that UART frame MSB first setting is valid.
#define | IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__)
Ensure that UART stop mode state is valid.
#define | IS_UART_MUTE_MODE(__MUTE__)
Ensure that UART mute mode state is valid.
#define | IS_UART_WAKEUP_SELECTION(__WAKE__)
Ensure that UART wake-up selection is valid.
#define | IS_UART_DE_POLARITY(__POLARITY__)
Ensure that UART driver enable polarity is valid.
#define | IS_UART_PRESCALER(__CLOCKPRESCALER__)
Ensure that UART Prescaler is valid.

Typedefs

typedef uint32_t | HAL_UART_StateTypeDef
HAL UART State definition.
typedef struct __UART_HandleTypeDef | UART_HandleTypeDef
UART handle Structure definition.
typedef void(* | pUART_CallbackTypeDef )(UART_HandleTypeDef *huart)
HAL UART Callback pointer definition.

Enumerations

enum UART_ClockSourceTypeDef {
UART_CLOCKSOURCE_PCLK1 = 0x00U, UART_CLOCKSOURCE_PCLK2 = 0x01U, UART_CLOCKSOURCE_HSI = 0x02U, UART_CLOCKSOURCE_SYSCLK = 0x04U,
UART_CLOCKSOURCE_LSE = 0x08U, UART_CLOCKSOURCE_UNDEFINED = 0x10U
}
UART clock sources definition. More...
enum HAL_UART_CallbackIDTypeDef {
HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, HAL_UART_TX_COMPLETE_CB_ID = 0x01U, HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, HAL_UART_RX_COMPLETE_CB_ID = 0x03U,
HAL_UART_ERROR_CB_ID = 0x04U, HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U,
HAL_UART_WAKEUP_CB_ID = 0x08U, HAL_UART_RX_FIFO_FULL_CB_ID = 0x09U, HAL_UART_TX_FIFO_EMPTY_CB_ID = 0x0AU, HAL_UART_MSPINIT_CB_ID = 0x0BU,
HAL_UART_MSPDEINIT_CB_ID = 0x0CU
}
HAL UART Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_UART_Init (UART_HandleTypeDef *huart)
Initialize the UART mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_HalfDuplex_Init (UART_HandleTypeDef *huart)
Initialize the half-duplex mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_LIN_Init (UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
Initialize the LIN mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_MultiProcessor_Init (UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
Initialize the multiprocessor mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_UART_DeInit (UART_HandleTypeDef *huart)
DeInitialize the UART peripheral.
__weak void | HAL_UART_MspInit (UART_HandleTypeDef *huart)
Initialize the UART MSP.
__weak void | HAL_UART_MspDeInit (UART_HandleTypeDef *huart)
DeInitialize the UART MSP.
HAL_StatusTypeDef | HAL_UART_RegisterCallback (UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback)
Register a User UART Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_UART_UnRegisterCallback (UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID)
Unregister an UART Callback UART callaback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_UART_Transmit (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Transmit_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Receive_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Transmit_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_Receive_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_DMAPause (UART_HandleTypeDef *huart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAResume (UART_HandleTypeDef *huart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAStop (UART_HandleTypeDef *huart)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_Abort (UART_HandleTypeDef *huart)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_Abort_IT (UART_HandleTypeDef *huart)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit_IT (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive_IT (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_UART_IRQHandler (UART_HandleTypeDef *huart)
Handle UART interrupt request.
__weak void | HAL_UART_TxHalfCpltCallback (UART_HandleTypeDef *huart)
Tx Half Transfer completed callback.
__weak void | HAL_UART_TxCpltCallback (UART_HandleTypeDef *huart)
Tx Transfer completed callback.
__weak void | HAL_UART_RxHalfCpltCallback (UART_HandleTypeDef *huart)
Rx Half Transfer completed callback.
__weak void | HAL_UART_RxCpltCallback (UART_HandleTypeDef *huart)
Rx Transfer completed callback.
__weak void | HAL_UART_ErrorCallback (UART_HandleTypeDef *huart)
UART error callback.
__weak void | HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
UART Abort Receive Complete callback.
void | HAL_UART_ReceiverTimeout_Config (UART_HandleTypeDef *huart, uint32_t TimeoutValue)
Update on the fly the receiver timeout value in RTOR register.
HAL_StatusTypeDef | HAL_UART_EnableReceiverTimeout (UART_HandleTypeDef *huart)
Enable the UART receiver timeout feature.
HAL_StatusTypeDef | HAL_UART_DisableReceiverTimeout (UART_HandleTypeDef *huart)
Disable the UART receiver timeout feature.
HAL_StatusTypeDef | HAL_LIN_SendBreak (UART_HandleTypeDef *huart)
Transmit break characters.
HAL_StatusTypeDef | HAL_MultiProcessor_EnableMuteMode (UART_HandleTypeDef *huart)
Enable UART in mute mode (does not mean UART enters mute mode; to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
HAL_StatusTypeDef | HAL_MultiProcessor_DisableMuteMode (UART_HandleTypeDef *huart)
Disable UART mute mode (does not mean the UART actually exits mute mode as it may not have been in mute mode at this very moment).
void | HAL_MultiProcessor_EnterMuteMode (UART_HandleTypeDef *huart)
Enter UART mute mode (means UART actually enters mute mode).
HAL_StatusTypeDef | HAL_HalfDuplex_EnableTransmitter (UART_HandleTypeDef *huart)
Enable the UART transmitter and disable the UART receiver.
HAL_StatusTypeDef | HAL_HalfDuplex_EnableReceiver (UART_HandleTypeDef *huart)
Enable the UART receiver and disable the UART transmitter.
HAL_UART_StateTypeDef | HAL_UART_GetState (UART_HandleTypeDef *huart)
Return the UART handle state.
uint32_t | HAL_UART_GetError (UART_HandleTypeDef *huart)
Return the UART handle error code.
void | UART_InitCallbacksToDefault (UART_HandleTypeDef *huart)
Initialize the callbacks to their default values.
HAL_StatusTypeDef | UART_SetConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral.
HAL_StatusTypeDef | UART_CheckIdleState (UART_HandleTypeDef *huart)
Check the UART Idle State.
HAL_StatusTypeDef | UART_WaitOnFlagUntilTimeout (UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle UART Communication Timeout.
void | UART_AdvFeatureConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral advanced features.

Detailed Description

Header file of UART HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_uart.h.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_uart_ex.h File Reference

  • File List
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Data Structures | Defines | Functions
stm32wbxx_hal_uart_ex.h File Reference

Header file of UART HAL Extended module. More...

#include "stm32wbxx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | UART_WakeUpTypeDef
UART wake up from stop mode parameters. More...

Defines

#define | UART_WORDLENGTH_7B USART_CR1_M1
#define | UART_WORDLENGTH_8B 0x00000000U
#define | UART_WORDLENGTH_9B USART_CR1_M0
#define | UART_ADDRESS_DETECT_4B 0x00000000U
#define | UART_ADDRESS_DETECT_7B USART_CR2_ADDM7
#define | UART_FIFOMODE_DISABLE 0x00000000U
#define | UART_FIFOMODE_ENABLE USART_CR1_FIFOEN
#define | UART_TXFIFO_THRESHOLD_1_8 0x00000000U
#define | UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0
#define | UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1
#define | UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)
#define | UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2
#define | UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)
#define | UART_RXFIFO_THRESHOLD_1_8 0x00000000U
#define | UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0
#define | UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1
#define | UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)
#define | UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2
#define | UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)
#define | UART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the UART clock source.
#define | UART_MASK_COMPUTATION(__HANDLE__)
Report the UART mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_UART_WORD_LENGTH(__LENGTH__)
Ensure that UART frame length is valid.
#define | IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__)
Ensure that UART wake-up address length is valid.
#define | IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that UART TXFIFO threshold level is valid.
#define | IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that UART RXFIFO threshold level is valid.

Functions

HAL_StatusTypeDef | HAL_RS485Ex_Init (UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
Initialize the RS485 Driver enable feature according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
__weak void | HAL_UARTEx_WakeupCallback (UART_HandleTypeDef *huart)
UART wakeup from Stop mode callback.
__weak void | HAL_UARTEx_RxFifoFullCallback (UART_HandleTypeDef *huart)
UART RX Fifo full callback.
__weak void | HAL_UARTEx_TxFifoEmptyCallback (UART_HandleTypeDef *huart)
UART TX Fifo empty callback.
HAL_StatusTypeDef | HAL_UARTEx_StopModeWakeUpSourceConfig (UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
Set Wakeup from Stop mode interrupt flag selection.
HAL_StatusTypeDef | HAL_UARTEx_EnableStopMode (UART_HandleTypeDef *huart)
Enable UART Stop Mode.
HAL_StatusTypeDef | HAL_UARTEx_DisableStopMode (UART_HandleTypeDef *huart)
Disable UART Stop Mode.
HAL_StatusTypeDef | HAL_MultiProcessorEx_AddressLength_Set (UART_HandleTypeDef *huart, uint32_t AddressLength)
By default in multiprocessor mode, when the wake up method is set to address mark, the UART handles only 4-bit long addresses detection; this API allows to enable longer addresses detection (6-, 7- or 8-bit long).
HAL_StatusTypeDef | HAL_UARTEx_EnableFifoMode (UART_HandleTypeDef *huart)
Enable the FIFO mode.
HAL_StatusTypeDef | HAL_UARTEx_DisableFifoMode (UART_HandleTypeDef *huart)
Disable the FIFO mode.
HAL_StatusTypeDef | HAL_UARTEx_SetTxFifoThreshold (UART_HandleTypeDef *huart, uint32_t Threshold)
Set the TXFIFO threshold.
HAL_StatusTypeDef | HAL_UARTEx_SetRxFifoThreshold (UART_HandleTypeDef *huart, uint32_t Threshold)
Set the RXFIFO threshold.

Detailed Description

Header file of UART HAL Extended module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_uart_ex.h.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_usart.h File Reference

  • File List
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  • Drivers
  • STM32WBxx_HAL_Driver
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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32wbxx_hal_usart.h File Reference

Header file of USART HAL module. More...

#include "stm32wbxx_hal_def.h"
#include "stm32wbxx_hal_usart_ex.h"

Go to the source code of this file.

Data Structures

struct | USART_InitTypeDef
USART Init Structure definition. More...
struct | __USART_HandleTypeDef
USART handle Structure definition. More...

Defines

#define | HAL_USART_ERROR_NONE ((uint32_t)0x00000000U)
#define | HAL_USART_ERROR_PE ((uint32_t)0x00000001U)
#define | HAL_USART_ERROR_NE ((uint32_t)0x00000002U)
#define | HAL_USART_ERROR_FE ((uint32_t)0x00000004U)
#define | HAL_USART_ERROR_ORE ((uint32_t)0x00000008U)
#define | HAL_USART_ERROR_DMA ((uint32_t)0x00000010U)
#define | HAL_USART_ERROR_UDR ((uint32_t)0x00000020U)
#define | HAL_USART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U)
#define | USART_STOPBITS_0_5 USART_CR2_STOP_0
#define | USART_STOPBITS_1 0x00000000U
#define | USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define | USART_STOPBITS_2 USART_CR2_STOP_1
#define | USART_PARITY_NONE 0x00000000U
#define | USART_PARITY_EVEN USART_CR1_PCE
#define | USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)
#define | USART_MODE_RX USART_CR1_RE
#define | USART_MODE_TX USART_CR1_TE
#define | USART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE)
#define | USART_OVERSAMPLING_16 0x00000000U
#define | USART_OVERSAMPLING_8 USART_CR1_OVER8
#define | USART_CLOCK_DISABLE 0x00000000U
#define | USART_CLOCK_ENABLE USART_CR2_CLKEN
#define | USART_POLARITY_LOW 0x00000000U
#define | USART_POLARITY_HIGH USART_CR2_CPOL
#define | USART_PHASE_1EDGE 0x00000000U
#define | USART_PHASE_2EDGE USART_CR2_CPHA
#define | USART_LASTBIT_DISABLE 0x00000000U
#define | USART_LASTBIT_ENABLE USART_CR2_LBCL
#define | USART_PRESCALER_DIV1 0x00000000U
#define | USART_PRESCALER_DIV2 0x00000001U
#define | USART_PRESCALER_DIV4 0x00000002U
#define | USART_PRESCALER_DIV6 0x00000003U
#define | USART_PRESCALER_DIV8 0x00000004U
#define | USART_PRESCALER_DIV10 0x00000005U
#define | USART_PRESCALER_DIV12 0x00000006U
#define | USART_PRESCALER_DIV16 0x00000007U
#define | USART_PRESCALER_DIV32 0x00000008U
#define | USART_PRESCALER_DIV64 0x00000009U
#define | USART_PRESCALER_DIV128 0x0000000AU
#define | USART_PRESCALER_DIV256 0x0000000BU
#define | USART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ
#define | USART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ
#define | USART_FLAG_TXFT USART_ISR_TXFT
#define | USART_FLAG_RXFT USART_ISR_RXFT
#define | USART_FLAG_RXFF USART_ISR_RXFF
#define | USART_FLAG_TXFE USART_ISR_TXFE
#define | USART_FLAG_REACK USART_ISR_REACK
#define | USART_FLAG_TEACK USART_ISR_TEACK
#define | USART_FLAG_BUSY USART_ISR_BUSY
#define | USART_FLAG_UDR USART_ISR_UDR
#define | USART_FLAG_TXE USART_ISR_TXE_TXFNF
#define | USART_FLAG_TXFNF USART_ISR_TXE_TXFNF
#define | USART_FLAG_TC USART_ISR_TC
#define | USART_FLAG_RXNE USART_ISR_RXNE_RXFNE
#define | USART_FLAG_RXFNE USART_ISR_RXNE_RXFNE
#define | USART_FLAG_IDLE USART_ISR_IDLE
#define | USART_FLAG_ORE USART_ISR_ORE
#define | USART_FLAG_NE USART_ISR_NE
#define | USART_FLAG_FE USART_ISR_FE
#define | USART_FLAG_PE USART_ISR_PE
#define | USART_IT_PE 0x0028U
#define | USART_IT_TXE 0x0727U
#define | USART_IT_TXFNF 0x0727U
#define | USART_IT_TC 0x0626U
#define | USART_IT_RXNE 0x0525U
#define | USART_IT_RXFNE 0x0525U
#define | USART_IT_IDLE 0x0424U
#define | USART_IT_ERR 0x0060U
#define | USART_IT_ORE 0x0300U
#define | USART_IT_NE 0x0200U
#define | USART_IT_FE 0x0100U
#define | USART_IT_RXFF 0x183FU
#define | USART_IT_TXFE 0x173EU
#define | USART_IT_RXFT 0x1A7CU
#define | USART_IT_TXFT 0x1B77U
#define | USART_CLEAR_PEF USART_ICR_PECF
#define | USART_CLEAR_FEF USART_ICR_FECF
#define | USART_CLEAR_NEF USART_ICR_NECF
#define | USART_CLEAR_OREF USART_ICR_ORECF
#define | USART_CLEAR_IDLEF USART_ICR_IDLECF
#define | USART_CLEAR_TCF USART_ICR_TCCF
#define | USART_CLEAR_UDRF USART_ICR_UDRCF
#define | USART_CLEAR_TXFECF USART_ICR_TXFECF
#define | USART_IT_MASK 0x001FU
#define | USART_CR_MASK 0x00E0U
#define | USART_CR_POS 5U
#define | __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)
Reset USART handle state.
#define | __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
Check whether the specified USART flag is set or not.
#define | __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
Clear the specified USART pending flag.
#define | __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)
Clear the USART PE pending flag.
#define | __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)
Clear the USART FE pending flag.
#define | __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)
Clear the USART NE pending flag.
#define | __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)
Clear the USART ORE pending flag.
#define | __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)
Clear the USART IDLE pending flag.
#define | __HAL_USART_CLEAR_TXFECF(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_TXFECF)
Clear the USART TX FIFO empty clear flag.
#define | __HAL_USART_CLEAR_UDRFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_UDRF)
Clear SPI slave underrun error flag.
#define | __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified USART interrupt.
#define | __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified USART interrupt.
#define | __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__INTERRUPT__)>> 0x08))) != RESET) ? SET : RESET)
Check whether the specified USART interrupt has occurred or not.
#define | __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified USART interrupt source is enabled or not.
#define | __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
Clear the specified USART ISR flag, in setting the proper ICR register flag.
#define | __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (__REQ__))
Set a specific USART request flag.
#define | __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
Enable the USART one bit sample method.
#define | __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
Disable the USART one bit sample method.
#define | __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable USART.
#define | __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable USART.
#define | USART_GET_DIV_FACTOR(__CLOCKPRESCALER__)
Get USART clock division factor from clock prescaler value.
#define | USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U) + ((__BAUD__)/2U)) / (__BAUD__))
BRR division operation to set BRR register in 8-bit oversampling mode.
#define | USART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)
Report the USART clock source.
#define | IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 8000000U)
Check USART Baud rate.
#define | IS_USART_STOPBITS(__STOPBITS__)
Ensure that USART frame number of stop bits is valid.
#define | IS_USART_PARITY(__PARITY__)
Ensure that USART frame parity is valid.
#define | IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
Ensure that USART communication mode is valid.
#define | IS_USART_OVERSAMPLING(__SAMPLING__)
Ensure that USART oversampling is valid.
#define | IS_USART_CLOCK(__CLOCK__)
Ensure that USART clock state is valid.
#define | IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
Ensure that USART frame polarity is valid.
#define | IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
Ensure that USART frame phase is valid.
#define | IS_USART_LASTBIT(__LASTBIT__)
Ensure that USART frame last bit clock pulse setting is valid.
#define | IS_USART_REQUEST_PARAMETER(__PARAM__)
Ensure that USART request parameter is valid.
#define | IS_USART_PRESCALER(__CLOCKPRESCALER__)
Ensure that USART Prescaler is valid.

Typedefs

typedef struct
__USART_HandleTypeDef 		USART_HandleTypeDef
USART handle Structure definition.
typedef void(* | pUSART_CallbackTypeDef )(USART_HandleTypeDef *husart)
HAL USART Callback pointer definition.

Enumerations

enum HAL_USART_StateTypeDef {
HAL_USART_STATE_RESET = 0x00U, HAL_USART_STATE_READY = 0x01U, HAL_USART_STATE_BUSY = 0x02U, HAL_USART_STATE_BUSY_TX = 0x12U,
HAL_USART_STATE_BUSY_RX = 0x22U, HAL_USART_STATE_BUSY_TX_RX = 0x32U, HAL_USART_STATE_TIMEOUT = 0x03U, HAL_USART_STATE_ERROR = 0x04U
}
HAL USART State structures definition. More...
enum USART_ClockSourceTypeDef {
USART_CLOCKSOURCE_PCLK2 = 0x01U, USART_CLOCKSOURCE_HSI = 0x02U, USART_CLOCKSOURCE_SYSCLK = 0x04U, USART_CLOCKSOURCE_LSE = 0x08U,
USART_CLOCKSOURCE_UNDEFINED = 0x10U
}
USART clock sources definitions. More...
enum HAL_USART_CallbackIDTypeDef {
HAL_USART_TX_HALFCOMPLETE_CB_ID = 0x00U, HAL_USART_TX_COMPLETE_CB_ID = 0x01U, HAL_USART_RX_HALFCOMPLETE_CB_ID = 0x02U, HAL_USART_RX_COMPLETE_CB_ID = 0x03U,
HAL_USART_TX_RX_COMPLETE_CB_ID = 0x04U, HAL_USART_ERROR_CB_ID = 0x05U, HAL_USART_ABORT_COMPLETE_CB_ID = 0x06U, HAL_USART_RX_FIFO_FULL_CB_ID = 0x07U,
HAL_USART_TX_FIFO_EMPTY_CB_ID = 0x08U, HAL_USART_MSPINIT_CB_ID = 0x09U, HAL_USART_MSPDEINIT_CB_ID = 0x0AU
}
HAL USART Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_USART_Init (USART_HandleTypeDef *husart)
Initialize the USART mode according to the specified parameters in the USART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_USART_DeInit (USART_HandleTypeDef *husart)
DeInitialize the USART peripheral.
__weak void | HAL_USART_MspInit (USART_HandleTypeDef *husart)
Initialize the USART MSP.
__weak void | HAL_USART_MspDeInit (USART_HandleTypeDef *husart)
DeInitialize the USART MSP.
HAL_StatusTypeDef | HAL_USART_RegisterCallback (USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback)
Register a User USART Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_USART_UnRegisterCallback (USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID)
Unregister an UART Callback UART callaback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_USART_Transmit (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
Simplex send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Full-Duplex Send and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Transmit_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Receive_IT (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Send and Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Transmit_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_Receive_DMA (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Transmit Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_DMAPause (USART_HandleTypeDef *husart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAResume (USART_HandleTypeDef *husart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAStop (USART_HandleTypeDef *husart)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_Abort (USART_HandleTypeDef *husart)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_USART_Abort_IT (USART_HandleTypeDef *husart)
Abort ongoing transfers (Interrupt mode).
void | HAL_USART_IRQHandler (USART_HandleTypeDef *husart)
Handle USART interrupt request.
__weak void | HAL_USART_TxHalfCpltCallback (USART_HandleTypeDef *husart)
Tx Half Transfer completed callback.
__weak void | HAL_USART_TxCpltCallback (USART_HandleTypeDef *husart)
Tx Transfer completed callback.
__weak void | HAL_USART_RxCpltCallback (USART_HandleTypeDef *husart)
Rx Transfer completed callback.
__weak void | HAL_USART_RxHalfCpltCallback (USART_HandleTypeDef *husart)
Rx Half Transfer completed callback.
__weak void | HAL_USART_TxRxCpltCallback (USART_HandleTypeDef *husart)
Tx/Rx Transfers completed callback for the non-blocking process.
__weak void | HAL_USART_ErrorCallback (USART_HandleTypeDef *husart)
USART error callback.
__weak void | HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
USART Abort Complete callback.
HAL_USART_StateTypeDef | HAL_USART_GetState (USART_HandleTypeDef *husart)
Return the USART handle state.
uint32_t | HAL_USART_GetError (USART_HandleTypeDef *husart)
Return the USART error code.

Detailed Description

Header file of USART HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_usart.h.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_usart_ex.h File Reference

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stm32wbxx_hal_usart_ex.h File Reference

Header file of USART HAL Extended module. More...

#include "stm32wbxx_hal_def.h"

Go to the source code of this file.

Defines

#define | USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)
#define | USART_WORDLENGTH_8B 0x00000000U
#define | USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)
#define | USART_NSS_HARD 0x00000000U
#define | USART_NSS_SOFT USART_CR2_DIS_NSS
#define | USART_SLAVEMODE_DISABLE 0x00000000U
#define | USART_SLAVEMODE_ENABLE USART_CR2_SLVEN
#define | USART_FIFOMODE_DISABLE 0x00000000U
#define | USART_FIFOMODE_ENABLE USART_CR1_FIFOEN
#define | USART_TXFIFO_THRESHOLD_1_8 0x00000000U
#define | USART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0
#define | USART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1
#define | USART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)
#define | USART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2
#define | USART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)
#define | USART_RXFIFO_THRESHOLD_1_8 0x00000000U
#define | USART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0
#define | USART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1
#define | USART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)
#define | USART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2
#define | USART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)
#define | USART_MASK_COMPUTATION(__HANDLE__)
Compute the USART mask to apply to retrieve the received data according to the word length and to the parity bits activation.
#define | IS_USART_WORD_LENGTH(__LENGTH__)
Ensure that USART frame length is valid.
#define | IS_USART_NSS(__NSS__)
Ensure that USART Negative Slave Select (NSS) pin management is valid.
#define | IS_USART_SLAVEMODE(__STATE__)
Ensure that USART Slave Mode is valid.
#define | IS_USART_FIFO_MODE_STATE(__STATE__)
Ensure that USART FIFO mode is valid.
#define | IS_USART_TXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that USART TXFIFO threshold level is valid.
#define | IS_USART_RXFIFO_THRESHOLD(__THRESHOLD__)
Ensure that USART RXFIFO threshold level is valid.

Functions

__weak void | HAL_USARTEx_RxFifoFullCallback (USART_HandleTypeDef *husart)
USART RX Fifo full callback.
__weak void | HAL_USARTEx_TxFifoEmptyCallback (USART_HandleTypeDef *husart)
USART TX Fifo empty callback.
HAL_StatusTypeDef | HAL_USARTEx_EnableSlaveMode (USART_HandleTypeDef *husart)
Enable the SPI slave mode.
HAL_StatusTypeDef | HAL_USARTEx_DisableSlaveMode (USART_HandleTypeDef *husart)
Disable the SPI slave mode.
HAL_StatusTypeDef | HAL_USARTEx_ConfigNSS (USART_HandleTypeDef *husart, uint32_t NSSConfig)
Configure the Slave Select input pin (NSS).
HAL_StatusTypeDef | HAL_USARTEx_EnableFifoMode (USART_HandleTypeDef *husart)
Enable the FIFO mode.
HAL_StatusTypeDef | HAL_USARTEx_DisableFifoMode (USART_HandleTypeDef *husart)
Disable the FIFO mode.
HAL_StatusTypeDef | HAL_USARTEx_SetTxFifoThreshold (USART_HandleTypeDef *husart, uint32_t Threshold)
Set the TXFIFO threshold.
HAL_StatusTypeDef | HAL_USARTEx_SetRxFifoThreshold (USART_HandleTypeDef *husart, uint32_t Threshold)
Set the RXFIFO threshold.

Detailed Description

Header file of USART HAL Extended module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_usart_ex.h.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_wwdg.h File Reference

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stm32wbxx_hal_wwdg.h File Reference

Header file of WWDG HAL module. More...

#include "stm32wbxx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | WWDG_InitTypeDef
WWDG Init structure definition. More...
struct | __WWDG_HandleTypeDef
WWDG handle Structure definition. More...

Defines

#define | WWDG_IT_EWI WWDG_CFR_EWI
#define | WWDG_FLAG_EWIF WWDG_SR_EWIF
#define | WWDG_PRESCALER_1 0x00000000u
#define | WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0
#define | WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1
#define | WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)
#define | WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2
#define | WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0)
#define | WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1)
#define | WWDG_PRESCALER_128 WWDG_CFR_WDGTB
#define | WWDG_EWI_DISABLE 0x00000000u
#define | WWDG_EWI_ENABLE WWDG_CFR_EWI
#define | IS_WWDG_PRESCALER(__PRESCALER__)
#define | IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
#define | IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
#define | IS_WWDG_EWI_MODE(__MODE__)
#define | __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
Enable the WWDG peripheral.
#define | __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
Enable the WWDG early wakeup interrupt.
#define | __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
Check whether the selected WWDG interrupt has occurred or not.
#define | __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
Clear the WWDG interrupt pending bits.
#define | __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check whether the specified WWDG flag is set or not.
#define | __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clear the WWDG's pending flags.
#define | __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified WWDG interrupt source is enabled or not.

Typedefs

typedef struct __WWDG_HandleTypeDef | WWDG_HandleTypeDef
WWDG handle Structure definition.
typedef void(* | pWWDG_CallbackTypeDef )(WWDG_HandleTypeDef *hppp)
HAL WWDG Callback pointer definition.

Enumerations

enum | HAL_WWDG_CallbackIDTypeDef { HAL_WWDG_EWI_CB_ID = 0x00u, HAL_WWDG_MSPINIT_CB_ID = 0x01u }
HAL WWDG common Callback ID enumeration definition. More...

Functions

HAL_StatusTypeDef | HAL_WWDG_Init (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG according to the specified.
__weak void | HAL_WWDG_MspInit (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG MSP.
HAL_StatusTypeDef | HAL_WWDG_RegisterCallback (WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback)
Register a User WWDG Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_WWDG_UnRegisterCallback (WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID)
Unregister a WWDG Callback WWDG Callback is redirected to the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_WWDG_Refresh (WWDG_HandleTypeDef *hwwdg)
Refresh the WWDG.
void | HAL_WWDG_IRQHandler (WWDG_HandleTypeDef *hwwdg)
Handle WWDG interrupt request.
__weak void | HAL_WWDG_EarlyWakeupCallback (WWDG_HandleTypeDef *hwwdg)
WWDG Early Wakeup callback.

Detailed Description

Header file of WWDG HAL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_wwdg.h.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_adc.h File Reference

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stm32wbxx_ll_adc.h File Reference

Header file of ADC LL module. More...

#include "stm32wbxx.h"

Go to the source code of this file.

Data Structures

struct | LL_ADC_CommonInitTypeDef
Structure definition of some features of ADC common parameters and multimode (all ADC instances belonging to the same ADC common instance). More...
struct | LL_ADC_InitTypeDef
Structure definition of some features of ADC instance. More...
struct | LL_ADC_REG_InitTypeDef
Structure definition of some features of ADC group regular. More...
struct | LL_ADC_INJ_InitTypeDef
Structure definition of some features of ADC group injected. More...

Defines

#define | ADC_SQR1_REGOFFSET (0x00000000UL)
#define | ADC_SQR2_REGOFFSET (0x00000100UL)
#define | ADC_SQR3_REGOFFSET (0x00000200UL)
#define | ADC_SQR4_REGOFFSET (0x00000300UL)
#define | ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
#define | ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */
#define | ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
#define | ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR1_SQ1" position in register */
#define | ADC_REG_RANK_2_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR1_SQ2" position in register */
#define | ADC_REG_RANK_3_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR1_SQ3" position in register */
#define | ADC_REG_RANK_4_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR1_SQ4" position in register */
#define | ADC_REG_RANK_5_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR2_SQ5" position in register */
#define | ADC_REG_RANK_6_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR2_SQ6" position in register */
#define | ADC_REG_RANK_7_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR2_SQ7" position in register */
#define | ADC_REG_RANK_8_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR2_SQ8" position in register */
#define | ADC_REG_RANK_9_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR2_SQ9" position in register */
#define | ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR3_SQ10" position in register */
#define | ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR3_SQ11" position in register */
#define | ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR3_SQ12" position in register */
#define | ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR3_SQ13" position in register */
#define | ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR3_SQ14" position in register */
#define | ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR4_SQ15" position in register */
#define | ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR4_SQ16" position in register */
#define | ADC_JDR1_REGOFFSET (0x00000000UL)
#define | ADC_JDR2_REGOFFSET (0x00000100UL)
#define | ADC_JDR3_REGOFFSET (0x00000200UL)
#define | ADC_JDR4_REGOFFSET (0x00000300UL)
#define | ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
#define | ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
#define | ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */
#define | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ( 8UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ1" position in register */
#define | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (14UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ2" position in register */
#define | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ3" position in register */
#define | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (26UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ4" position in register */
#define | ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
#define | ADC_REG_TRIG_SOURCE_MASK
#define | ADC_REG_TRIG_EDGE_MASK
#define | ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_CFGR_EXTSEL" position in register */
#define | ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Value equivalent to bitfield "ADC_CFGR_EXTEN" position in register */
#define | ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
#define | ADC_INJ_TRIG_SOURCE_MASK
#define | ADC_INJ_TRIG_EDGE_MASK
#define | ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ( 2UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTSEL" position in register */
#define | ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTEN" position in register */
#define | ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
#define | ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
#define | ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */
#define | ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
#define | ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
#define | ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
#define | ADC_CHANNEL_ID_INTERNAL_CH_2 (0x00080000UL) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
#define | ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
#define | ADC_SMPR1_REGOFFSET (0x00000000UL)
#define | ADC_SMPR2_REGOFFSET (0x02000000UL)
#define | ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
#define | ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
#define | ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL)
#define | ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */
#define | ADC_CHANNEL_0_NUMBER (0x00000000UL)
#define | ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 )
#define | ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_4_NUMBER ( ADC_CFGR_AWD1CH_2 )
#define | ADC_CHANNEL_5_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_6_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
#define | ADC_CHANNEL_7_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_8_NUMBER ( ADC_CFGR_AWD1CH_3 )
#define | ADC_CHANNEL_9_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_10_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 )
#define | ADC_CHANNEL_11_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_12_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 )
#define | ADC_CHANNEL_13_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_14_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
#define | ADC_CHANNEL_15_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4 )
#define | ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
#define | ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 )
#define | ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
#define | ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
#define | ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
#define | ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
#define | ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
#define | ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
#define | ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
#define | ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
#define | ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
#define | ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
#define | ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
#define | ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
#define | ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
#define | ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
#define | ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
#define | ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
#define | ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
#define | ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
#define | ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
#define | ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP0" position in register */
#define | ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP1" position in register */
#define | ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP2" position in register */
#define | ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP3" position in register */
#define | ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP4" position in register */
#define | ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP5" position in register */
#define | ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP6" position in register */
#define | ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP7" position in register */
#define | ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP8" position in register */
#define | ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP9" position in register */
#define | ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP10" position in register */
#define | ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP11" position in register */
#define | ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP12" position in register */
#define | ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP13" position in register */
#define | ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP14" position in register */
#define | ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP15" position in register */
#define | ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP16" position in register */
#define | ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP17" position in register */
#define | ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP18" position in register */
#define | ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)
#define | ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
#define | ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
#define | ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen to perform of shift when single mode is selected, shift value out of channels bits range. */
#define | ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode: mask of bit */
#define | ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode: position of bit */
#define | ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a shift of 4 ranks */
#define | ADC_AWD_CR1_REGOFFSET (0x00000000UL)
#define | ADC_AWD_CR2_REGOFFSET (0x00100000UL)
#define | ADC_AWD_CR3_REGOFFSET (0x00200000UL)
#define | ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
#define | ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
#define | ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
#define | ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
#define | ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
#define | ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */
#define | ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
#define | ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
#define | ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
#define | ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
#define | ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */
#define | ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate threshold high: mask of bit */
#define | ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate threshold high: position of bit */
#define | ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */
#define | ADC_OFR1_REGOFFSET (0x00000000UL)
#define | ADC_OFR2_REGOFFSET (0x00000001UL)
#define | ADC_OFR3_REGOFFSET (0x00000002UL)
#define | ADC_OFR4_REGOFFSET (0x00000003UL)
#define | ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
#define | ADC_CFGR_RES_BITOFFSET_POS ( 3UL) /* Value equivalent to bitfield "ADC_CFGR_RES" position in register */
#define | ADC_CFGR_AWD1SGL_BITOFFSET_POS (22UL) /* Value equivalent to bitfield "ADC_CFGR_AWD1SGL" position in register */
#define | ADC_CFGR_AWD1EN_BITOFFSET_POS (23UL) /* Value equivalent to bitfield "ADC_CFGR_AWD1EN" position in register */
#define | ADC_CFGR_JAWD1EN_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_CFGR_JAWD1EN" position in register */
#define | ADC_TR1_HT1_BITOFFSET_POS (16UL) /* Value equivalent to bitfield "ADC_TR1_HT1" position in register */
#define | ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
#define | VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, address of parameter VREFINT: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.6 V (tolerance: +-10 mV). */
#define | VREFINT_CAL_VREF (3600UL) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
#define | TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32WB, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
#define | TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75CAUL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32WB, temperature sensor ADC raw data acquired at temperature 130 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
#define | TEMPSENSOR_CAL1_TEMP (30L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define | TEMPSENSOR_CAL2_TEMP (130L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define | TEMPSENSOR_CAL_VREFANALOG (3000UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
#define | __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.
#define | LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY
#define | LL_ADC_FLAG_EOC ADC_ISR_EOC
#define | LL_ADC_FLAG_EOS ADC_ISR_EOS
#define | LL_ADC_FLAG_OVR ADC_ISR_OVR
#define | LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP
#define | LL_ADC_FLAG_JEOC ADC_ISR_JEOC
#define | LL_ADC_FLAG_JEOS ADC_ISR_JEOS
#define | LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF
#define | LL_ADC_FLAG_AWD1 ADC_ISR_AWD1
#define | LL_ADC_FLAG_AWD2 ADC_ISR_AWD2
#define | LL_ADC_FLAG_AWD3 ADC_ISR_AWD3
#define | LL_ADC_IT_ADRDY ADC_IER_ADRDYIE
#define | LL_ADC_IT_EOC ADC_IER_EOCIE
#define | LL_ADC_IT_EOS ADC_IER_EOSIE
#define | LL_ADC_IT_OVR ADC_IER_OVRIE
#define | LL_ADC_IT_EOSMP ADC_IER_EOSMPIE
#define | LL_ADC_IT_JEOC ADC_IER_JEOCIE
#define | LL_ADC_IT_JEOS ADC_IER_JEOSIE
#define | LL_ADC_IT_JQOVF ADC_IER_JQOVFIE
#define | LL_ADC_IT_AWD1 ADC_IER_AWD1IE
#define | LL_ADC_IT_AWD2 ADC_IER_AWD2IE
#define | LL_ADC_IT_AWD3 ADC_IER_AWD3IE
#define | LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
#define | LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0)
#define | LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 )
#define | LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0)
#define | LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL)
#define | LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 )
#define | LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 )
#define | LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 )
#define | LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3)
#define | LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0)
#define | LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1)
#define | LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)
#define | LL_ADC_PATH_INTERNAL_NONE (0x00000000UL)
#define | LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN)
#define | LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN)
#define | LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN)
#define | LL_ADC_RESOLUTION_12B (0x00000000UL)
#define | LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_0)
#define | LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_1 )
#define | LL_ADC_RESOLUTION_6B (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)
#define | LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL)
#define | LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN)
#define | LL_ADC_LP_MODE_NONE (0x00000000UL)
#define | LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY)
#define | LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET
#define | LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET
#define | LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET
#define | LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET
#define | LL_ADC_OFFSET_DISABLE (0x00000000UL)
#define | LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN)
#define | LL_ADC_GROUP_REGULAR (0x00000001UL)
#define | LL_ADC_GROUP_INJECTED (0x00000002UL)
#define | LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL)
#define | LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD )
#define | LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD )
#define | LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD )
#define | LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD )
#define | LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD )
#define | LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD )
#define | LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | ADC_CHANNEL_6_BITFIELD )
#define | LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | ADC_CHANNEL_7_BITFIELD )
#define | LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | ADC_CHANNEL_8_BITFIELD )
#define | LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | ADC_CHANNEL_9_BITFIELD )
#define | LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD)
#define | LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD)
#define | LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD)
#define | LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD)
#define | LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD)
#define | LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD)
#define | LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD)
#define | LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD)
#define | LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD)
#define | LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_0 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL)
#define | LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR_EXTEN_0)
#define | LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1 )
#define | LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0)
#define | LL_ADC_REG_CONV_SINGLE (0x00000000UL)
#define | LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT)
#define | LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL)
#define | LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMAEN)
#define | LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN)
#define | LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL)
#define | LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD)
#define | LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL)
#define | LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
#define | LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS)
#define | LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL)
#define | LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define | LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0)
#define | LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 )
#define | LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0)
#define | LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL)
#define | LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO)
#define | LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */
#define | LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */
#define | LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */
#define | LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL)
#define | LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0)
#define | LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 )
#define | LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0)
#define | LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL)
#define | LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN)
#define | LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS)
#define | LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS)
#define | LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS)
#define | LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS)
#define | LL_ADC_SAMPLINGTIME_2CYCLES_5 (0x00000000UL)
#define | LL_ADC_SAMPLINGTIME_6CYCLES_5 ( ADC_SMPR2_SMP10_0)
#define | LL_ADC_SAMPLINGTIME_12CYCLES_5 ( ADC_SMPR2_SMP10_1 )
#define | LL_ADC_SAMPLINGTIME_24CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)
#define | LL_ADC_SAMPLINGTIME_47CYCLES_5 (ADC_SMPR2_SMP10_2 )
#define | LL_ADC_SAMPLINGTIME_92CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0)
#define | LL_ADC_SAMPLINGTIME_247CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 )
#define | LL_ADC_SAMPLINGTIME_640CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)
#define | LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S)
#define | LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D)
#define | LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED)
#define | LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET)
#define | LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET)
#define | LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET)
#define | LL_ADC_AWD_DISABLE (0x00000000UL)
#define | LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN )
#define | LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN )
#define | LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN )
#define | LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define | LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1 )
#define | LL_ADC_AWD_THRESHOLD_LOW ( ADC_TR1_LT1)
#define | LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR1_HT1 | ADC_TR1_LT1)
#define | LL_ADC_OVS_DISABLE (0x00000000UL)
#define | LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE)
#define | LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE)
#define | LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE )
#define | LL_ADC_OVS_GRP_INJ_REG_RESUMED ( ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)
#define | LL_ADC_OVS_REG_CONT (0x00000000UL)
#define | LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS)
#define | LL_ADC_OVS_RATIO_2 (0x00000000UL)
#define | LL_ADC_OVS_RATIO_4 ( ADC_CFGR2_OVSR_0)
#define | LL_ADC_OVS_RATIO_8 ( ADC_CFGR2_OVSR_1 )
#define | LL_ADC_OVS_RATIO_16 ( ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0)
#define | LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2 )
#define | LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0)
#define | LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 )
#define | LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0)
#define | LL_ADC_OVS_SHIFT_NONE (0x00000000UL)
#define | LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 )
#define | LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 )
#define | LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 )
#define | LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)
#define | LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 )
#define | LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 10UL)
#define | LL_ADC_DELAY_VREFINT_STAB_US ( 12UL)
#define | LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL)
#define | LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL)
#define | LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in ADC register.
#define | LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in ADC register.
#define | __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)
Helper macro to get ADC channel number in decimal format from literals LL_ADC_CHANNEL_x.
#define | __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)
Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x from number in decimal format.
#define | __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
Helper macro to determine whether the selected channel corresponds to literal definitions of driver.
#define | __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
Helper macro to convert a channel defined from parameter definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), to its equivalent parameter definition of a ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
#define | __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)
Helper macro to determine whether the internal channel selected is available on the ADC instance selected.
#define | __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)
Helper macro to define ADC analog watchdog parameter: define a single channel to monitor with analog watchdog from sequencer channel and groups definition.
#define | __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
Helper macro to set the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.
#define | __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
Helper macro to get the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.
#define | __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) & LL_ADC_AWD_THRESHOLD_LOW)
Helper macro to get the ADC analog watchdog threshold high or low from raw value containing both thresholds concatenated.
#define | __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))
Helper macro to set the ADC calibration value with both single ended and differential modes calibration factors concatenated.
#define | __LL_ADC_COMMON_INSTANCE(__ADCx__) (ADC1_COMMON)
Helper macro to select the ADC common instance to which is belonging the selected ADC instance.
#define | __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) (LL_ADC_IsEnabled(ADC1))
Helper macro to check if all ADC instances sharing the same ADC common instance are disabled.
#define | __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))
Helper macro to define the ADC conversion data full-scale digital value corresponding to the selected ADC resolution.
#define | __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__)
Helper macro to convert the ADC conversion data from a resolution to another resolution.
#define | __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__, __ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value).
#define | __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate analog reference voltage (Vref+) (unit: mVolt) from ADC conversion data of internal voltage reference VrefInt.
#define | __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.
#define | __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__, __TEMPSENSOR_TYP_CALX_V__, __TEMPSENSOR_CALX_TEMP__, __VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Functions

__STATIC_INLINE uint32_t | LL_ADC_DMA_GetRegAddr (ADC_TypeDef *ADCx, uint32_t Register)
Function to help to configure DMA transfer from ADC: retrieve the ADC register address from ADC instance and a list of ADC registers intended to be used (most commonly) with DMA transfer.
__STATIC_INLINE void | LL_ADC_SetCommonClock (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
Set parameter common to several ADC: Clock source and prescaler.
__STATIC_INLINE uint32_t | LL_ADC_GetCommonClock (ADC_Common_TypeDef *ADCxy_COMMON)
Get parameter common to several ADC: Clock source and prescaler.
__STATIC_INLINE void | LL_ADC_SetCommonPathInternalCh (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
Set parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).
__STATIC_INLINE uint32_t | LL_ADC_GetCommonPathInternalCh (ADC_Common_TypeDef *ADCxy_COMMON)
Get parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).
__STATIC_INLINE void | LL_ADC_SetCalibrationFactor (ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
Set ADC calibration factor in the mode single-ended or differential (for devices with differential mode available).
__STATIC_INLINE uint32_t | LL_ADC_GetCalibrationFactor (ADC_TypeDef *ADCx, uint32_t SingleDiff)
Get ADC calibration factor in the mode single-ended or differential (for devices with differential mode available).
__STATIC_INLINE void | LL_ADC_SetResolution (ADC_TypeDef *ADCx, uint32_t Resolution)
Set ADC resolution.
__STATIC_INLINE uint32_t | LL_ADC_GetResolution (ADC_TypeDef *ADCx)
Get ADC resolution.
__STATIC_INLINE void | LL_ADC_SetDataAlignment (ADC_TypeDef *ADCx, uint32_t DataAlignment)
Set ADC conversion data alignment.
__STATIC_INLINE uint32_t | LL_ADC_GetDataAlignment (ADC_TypeDef *ADCx)
Get ADC conversion data alignment.
__STATIC_INLINE void | LL_ADC_SetLowPowerMode (ADC_TypeDef *ADCx, uint32_t LowPowerMode)
Set ADC low power mode.
__STATIC_INLINE uint32_t | LL_ADC_GetLowPowerMode (ADC_TypeDef *ADCx)
Get ADC low power mode:
__STATIC_INLINE void | LL_ADC_SetOffset (ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
Set ADC selected offset number 1, 2, 3 or 4.
__STATIC_INLINE uint32_t | LL_ADC_GetOffsetChannel (ADC_TypeDef *ADCx, uint32_t Offsety)
Get for the ADC selected offset number 1, 2, 3 or 4: Channel to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)
__STATIC_INLINE uint32_t | LL_ADC_GetOffsetLevel (ADC_TypeDef *ADCx, uint32_t Offsety)
Get for the ADC selected offset number 1, 2, 3 or 4: Offset level (offset to be subtracted from the raw converted data).
__STATIC_INLINE void | LL_ADC_SetOffsetState (ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
Set for the ADC selected offset number 1, 2, 3 or 4: force offset state disable or enable without modifying offset channel or offset value.
__STATIC_INLINE uint32_t | LL_ADC_GetOffsetState (ADC_TypeDef *ADCx, uint32_t Offsety)
Get for the ADC selected offset number 1, 2, 3 or 4: offset state disabled or enabled.
__STATIC_INLINE void | LL_ADC_REG_SetTriggerSource (ADC_TypeDef *ADCx, uint32_t TriggerSource)
Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_REG_GetTriggerSource (ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_REG_IsTriggerSourceSWStart (ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger source internal (SW start) or external.
__STATIC_INLINE void | LL_ADC_REG_SetTriggerEdge (ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
Set ADC group regular conversion trigger polarity.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetTriggerEdge (ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger polarity.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerLength (ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
Set ADC group regular sequencer length and scan direction.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerLength (ADC_TypeDef *ADCx)
Get ADC group regular sequencer length and scan direction.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerDiscont (ADC_TypeDef *ADCx, uint32_t SeqDiscont)
Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerDiscont (ADC_TypeDef *ADCx)
Get ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
Set ADC group regular sequence: channel on the selected scan sequence rank.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group regular sequence: channel on the selected scan sequence rank.
__STATIC_INLINE void | LL_ADC_REG_SetContinuousMode (ADC_TypeDef *ADCx, uint32_t Continuous)
Set ADC continuous conversion mode on ADC group regular.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetContinuousMode (ADC_TypeDef *ADCx)
Get ADC continuous conversion mode on ADC group regular.
__STATIC_INLINE void | LL_ADC_REG_SetDMATransfer (ADC_TypeDef *ADCx, uint32_t DMATransfer)
Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetDMATransfer (ADC_TypeDef *ADCx)
Get ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
__STATIC_INLINE void | LL_ADC_REG_SetOverrun (ADC_TypeDef *ADCx, uint32_t Overrun)
Set ADC group regular behavior in case of overrun: data preserved or overwritten.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetOverrun (ADC_TypeDef *ADCx)
Get ADC group regular behavior in case of overrun: data preserved or overwritten.
__STATIC_INLINE void | LL_ADC_INJ_SetTriggerSource (ADC_TypeDef *ADCx, uint32_t TriggerSource)
Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetTriggerSource (ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_INJ_IsTriggerSourceSWStart (ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger source internal (SW start) or external.
__STATIC_INLINE void | LL_ADC_INJ_SetTriggerEdge (ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
Set ADC group injected conversion trigger polarity.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetTriggerEdge (ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger polarity.
__STATIC_INLINE void | LL_ADC_INJ_SetSequencerLength (ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
Set ADC group injected sequencer length and scan direction.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetSequencerLength (ADC_TypeDef *ADCx)
Get ADC group injected sequencer length and scan direction.
__STATIC_INLINE void | LL_ADC_INJ_SetSequencerDiscont (ADC_TypeDef *ADCx, uint32_t SeqDiscont)
Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetSequencerDiscont (ADC_TypeDef *ADCx)
Get ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE void | LL_ADC_INJ_SetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
Set ADC group injected sequence: channel on the selected sequence rank.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected sequence: channel on the selected sequence rank.
__STATIC_INLINE void | LL_ADC_INJ_SetTrigAuto (ADC_TypeDef *ADCx, uint32_t TrigAuto)
Set ADC group injected conversion trigger: independent or from ADC group regular.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetTrigAuto (ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger: independent or from ADC group regular.
__STATIC_INLINE void | LL_ADC_INJ_SetQueueMode (ADC_TypeDef *ADCx, uint32_t QueueMode)
Set ADC group injected contexts queue mode.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetQueueMode (ADC_TypeDef *ADCx)
Get ADC group injected context queue mode.
__STATIC_INLINE void | LL_ADC_INJ_ConfigQueueContext (ADC_TypeDef *ADCx, uint32_t TriggerSource, uint32_t ExternalTriggerEdge, uint32_t SequencerNbRanks, uint32_t Rank1_Channel, uint32_t Rank2_Channel, uint32_t Rank3_Channel, uint32_t Rank4_Channel)
Set one context on ADC group injected that will be checked in contexts queue.
__STATIC_INLINE void | LL_ADC_SetChannelSamplingTime (ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
Set sampling time of the selected ADC channel Unit: ADC clock cycles.
__STATIC_INLINE uint32_t | LL_ADC_GetChannelSamplingTime (ADC_TypeDef *ADCx, uint32_t Channel)
Get sampling time of the selected ADC channel Unit: ADC clock cycles.
__STATIC_INLINE void | LL_ADC_SetChannelSingleDiff (ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
Set mode single-ended or differential input of the selected ADC channel.
__STATIC_INLINE uint32_t | LL_ADC_GetChannelSingleDiff (ADC_TypeDef *ADCx, uint32_t Channel)
Get mode single-ended or differential input of the selected ADC channel.
__STATIC_INLINE void | LL_ADC_SetAnalogWDMonitChannels (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
Set ADC analog watchdog monitored channels: a single channel, multiple channels or all channels, on ADC groups regular and-or injected.
__STATIC_INLINE uint32_t | LL_ADC_GetAnalogWDMonitChannels (ADC_TypeDef *ADCx, uint32_t AWDy)
Get ADC analog watchdog monitored channel.
__STATIC_INLINE void | LL_ADC_ConfigAnalogWDThresholds (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue)
Set ADC analog watchdog thresholds value of both thresholds high and low.
__STATIC_INLINE void | LL_ADC_SetAnalogWDThresholds (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
Set ADC analog watchdog threshold value of threshold high or low.
__STATIC_INLINE uint32_t | LL_ADC_GetAnalogWDThresholds (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
Get ADC analog watchdog threshold value of threshold high, threshold low or raw data with ADC thresholds high and low concatenated.
__STATIC_INLINE void | LL_ADC_SetOverSamplingScope (ADC_TypeDef *ADCx, uint32_t OvsScope)
Set ADC oversampling scope: ADC groups regular and-or injected (availability of ADC group injected depends on STM32 families).
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingScope (ADC_TypeDef *ADCx)
Get ADC oversampling scope: ADC groups regular and-or injected (availability of ADC group injected depends on STM32 families).
__STATIC_INLINE void | LL_ADC_SetOverSamplingDiscont (ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
Set ADC oversampling discontinuous mode (triggered mode) on the selected ADC group.
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingDiscont (ADC_TypeDef *ADCx)
Get ADC oversampling discontinuous mode (triggered mode) on the selected ADC group.
__STATIC_INLINE void | LL_ADC_ConfigOverSamplingRatioShift (ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
Set ADC oversampling (impacting both ADC groups regular and injected)
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingRatio (ADC_TypeDef *ADCx)
Get ADC oversampling ratio (impacting both ADC groups regular and injected)
__STATIC_INLINE uint32_t | LL_ADC_GetOverSamplingShift (ADC_TypeDef *ADCx)
Get ADC oversampling shift (impacting both ADC groups regular and injected)
__STATIC_INLINE void | LL_ADC_EnableDeepPowerDown (ADC_TypeDef *ADCx)
Put ADC instance in deep power down state.
__STATIC_INLINE void | LL_ADC_DisableDeepPowerDown (ADC_TypeDef *ADCx)
Disable ADC deep power down mode.
__STATIC_INLINE uint32_t | LL_ADC_IsDeepPowerDownEnabled (ADC_TypeDef *ADCx)
Get the selected ADC instance deep power down state.
__STATIC_INLINE void | LL_ADC_EnableInternalRegulator (ADC_TypeDef *ADCx)
Enable ADC instance internal voltage regulator.
__STATIC_INLINE void | LL_ADC_DisableInternalRegulator (ADC_TypeDef *ADCx)
Disable ADC internal voltage regulator.
__STATIC_INLINE uint32_t | LL_ADC_IsInternalRegulatorEnabled (ADC_TypeDef *ADCx)
Get the selected ADC instance internal voltage regulator state.
__STATIC_INLINE void | LL_ADC_Enable (ADC_TypeDef *ADCx)
Enable the selected ADC instance.
__STATIC_INLINE void | LL_ADC_Disable (ADC_TypeDef *ADCx)
Disable the selected ADC instance.
__STATIC_INLINE uint32_t | LL_ADC_IsEnabled (ADC_TypeDef *ADCx)
Get the selected ADC instance enable state.
__STATIC_INLINE uint32_t | LL_ADC_IsDisableOngoing (ADC_TypeDef *ADCx)
Get the selected ADC instance disable state.
__STATIC_INLINE void | LL_ADC_StartCalibration (ADC_TypeDef *ADCx, uint32_t SingleDiff)
Start ADC calibration in the mode single-ended or differential (for devices with differential mode available).
__STATIC_INLINE uint32_t | LL_ADC_IsCalibrationOnGoing (ADC_TypeDef *ADCx)
Get ADC calibration state.
__STATIC_INLINE void | LL_ADC_REG_StartConversion (ADC_TypeDef *ADCx)
Start ADC group regular conversion.
__STATIC_INLINE void | LL_ADC_REG_StopConversion (ADC_TypeDef *ADCx)
Stop ADC group regular conversion.
__STATIC_INLINE uint32_t | LL_ADC_REG_IsConversionOngoing (ADC_TypeDef *ADCx)
Get ADC group regular conversion state.
__STATIC_INLINE uint32_t | LL_ADC_REG_IsStopConversionOngoing (ADC_TypeDef *ADCx)
Get ADC group regular command of conversion stop state.
__STATIC_INLINE uint32_t | LL_ADC_REG_ReadConversionData32 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).
__STATIC_INLINE uint16_t | LL_ADC_REG_ReadConversionData12 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 12 bits.
__STATIC_INLINE uint16_t | LL_ADC_REG_ReadConversionData10 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 10 bits.
__STATIC_INLINE uint8_t | LL_ADC_REG_ReadConversionData8 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 8 bits.
__STATIC_INLINE uint8_t | LL_ADC_REG_ReadConversionData6 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 6 bits.
__STATIC_INLINE void | LL_ADC_INJ_StartConversion (ADC_TypeDef *ADCx)
Start ADC group injected conversion.
__STATIC_INLINE void | LL_ADC_INJ_StopConversion (ADC_TypeDef *ADCx)
Stop ADC group injected conversion.
__STATIC_INLINE uint32_t | LL_ADC_INJ_IsConversionOngoing (ADC_TypeDef *ADCx)
Get ADC group injected conversion state.
__STATIC_INLINE uint32_t | LL_ADC_INJ_IsStopConversionOngoing (ADC_TypeDef *ADCx)
Get ADC group injected command of conversion stop state.
__STATIC_INLINE uint32_t | LL_ADC_INJ_ReadConversionData32 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).
__STATIC_INLINE uint16_t | LL_ADC_INJ_ReadConversionData12 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 12 bits.
__STATIC_INLINE uint16_t | LL_ADC_INJ_ReadConversionData10 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 10 bits.
__STATIC_INLINE uint8_t | LL_ADC_INJ_ReadConversionData8 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 8 bits.
__STATIC_INLINE uint8_t | LL_ADC_INJ_ReadConversionData6 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 6 bits.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_ADRDY (ADC_TypeDef *ADCx)
Get flag ADC ready.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_EOC (ADC_TypeDef *ADCx)
Get flag ADC group regular end of unitary conversion.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_EOS (ADC_TypeDef *ADCx)
Get flag ADC group regular end of sequence conversions.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_OVR (ADC_TypeDef *ADCx)
Get flag ADC group regular overrun.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_EOSMP (ADC_TypeDef *ADCx)
Get flag ADC group regular end of sampling phase.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_JEOC (ADC_TypeDef *ADCx)
Get flag ADC group injected end of unitary conversion.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_JEOS (ADC_TypeDef *ADCx)
Get flag ADC group injected end of sequence conversions.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_JQOVF (ADC_TypeDef *ADCx)
Get flag ADC group injected contexts queue overflow.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_AWD1 (ADC_TypeDef *ADCx)
Get flag ADC analog watchdog 1 flag.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_AWD2 (ADC_TypeDef *ADCx)
Get flag ADC analog watchdog 2.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_AWD3 (ADC_TypeDef *ADCx)
Get flag ADC analog watchdog 3.
__STATIC_INLINE void | LL_ADC_ClearFlag_ADRDY (ADC_TypeDef *ADCx)
Clear flag ADC ready.
__STATIC_INLINE void | LL_ADC_ClearFlag_EOC (ADC_TypeDef *ADCx)
Clear flag ADC group regular end of unitary conversion.
__STATIC_INLINE void | LL_ADC_ClearFlag_EOS (ADC_TypeDef *ADCx)
Clear flag ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_ClearFlag_OVR (ADC_TypeDef *ADCx)
Clear flag ADC group regular overrun.
__STATIC_INLINE void | LL_ADC_ClearFlag_EOSMP (ADC_TypeDef *ADCx)
Clear flag ADC group regular end of sampling phase.
__STATIC_INLINE void | LL_ADC_ClearFlag_JEOC (ADC_TypeDef *ADCx)
Clear flag ADC group injected end of unitary conversion.
__STATIC_INLINE void | LL_ADC_ClearFlag_JEOS (ADC_TypeDef *ADCx)
Clear flag ADC group injected end of sequence conversions.
__STATIC_INLINE void | LL_ADC_ClearFlag_JQOVF (ADC_TypeDef *ADCx)
Clear flag ADC group injected contexts queue overflow.
__STATIC_INLINE void | LL_ADC_ClearFlag_AWD1 (ADC_TypeDef *ADCx)
Clear flag ADC analog watchdog 1.
__STATIC_INLINE void | LL_ADC_ClearFlag_AWD2 (ADC_TypeDef *ADCx)
Clear flag ADC analog watchdog 2.
__STATIC_INLINE void | LL_ADC_ClearFlag_AWD3 (ADC_TypeDef *ADCx)
Clear flag ADC analog watchdog 3.
__STATIC_INLINE void | LL_ADC_EnableIT_ADRDY (ADC_TypeDef *ADCx)
Enable ADC ready.
__STATIC_INLINE void | LL_ADC_EnableIT_EOC (ADC_TypeDef *ADCx)
Enable interruption ADC group regular end of unitary conversion.
__STATIC_INLINE void | LL_ADC_EnableIT_EOS (ADC_TypeDef *ADCx)
Enable interruption ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_EnableIT_OVR (ADC_TypeDef *ADCx)
Enable ADC group regular interruption overrun.
__STATIC_INLINE void | LL_ADC_EnableIT_EOSMP (ADC_TypeDef *ADCx)
Enable interruption ADC group regular end of sampling.
__STATIC_INLINE void | LL_ADC_EnableIT_JEOC (ADC_TypeDef *ADCx)
Enable interruption ADC group injected end of unitary conversion.
__STATIC_INLINE void | LL_ADC_EnableIT_JEOS (ADC_TypeDef *ADCx)
Enable interruption ADC group injected end of sequence conversions.
__STATIC_INLINE void | LL_ADC_EnableIT_JQOVF (ADC_TypeDef *ADCx)
Enable interruption ADC group injected context queue overflow.
__STATIC_INLINE void | LL_ADC_EnableIT_AWD1 (ADC_TypeDef *ADCx)
Enable interruption ADC analog watchdog 1.
__STATIC_INLINE void | LL_ADC_EnableIT_AWD2 (ADC_TypeDef *ADCx)
Enable interruption ADC analog watchdog 2.
__STATIC_INLINE void | LL_ADC_EnableIT_AWD3 (ADC_TypeDef *ADCx)
Enable interruption ADC analog watchdog 3.
__STATIC_INLINE void | LL_ADC_DisableIT_ADRDY (ADC_TypeDef *ADCx)
Disable interruption ADC ready.
__STATIC_INLINE void | LL_ADC_DisableIT_EOC (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of unitary conversion.
__STATIC_INLINE void | LL_ADC_DisableIT_EOS (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_DisableIT_OVR (ADC_TypeDef *ADCx)
Disable interruption ADC group regular overrun.
__STATIC_INLINE void | LL_ADC_DisableIT_EOSMP (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of sampling.
__STATIC_INLINE void | LL_ADC_DisableIT_JEOC (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of unitary conversion.
__STATIC_INLINE void | LL_ADC_DisableIT_JEOS (ADC_TypeDef *ADCx)
Disable interruption ADC group injected end of sequence conversions.
__STATIC_INLINE void | LL_ADC_DisableIT_JQOVF (ADC_TypeDef *ADCx)
Disable interruption ADC group injected context queue overflow.
__STATIC_INLINE void | LL_ADC_DisableIT_AWD1 (ADC_TypeDef *ADCx)
Disable interruption ADC analog watchdog 1.
__STATIC_INLINE void | LL_ADC_DisableIT_AWD2 (ADC_TypeDef *ADCx)
Disable interruption ADC analog watchdog 2.
__STATIC_INLINE void | LL_ADC_DisableIT_AWD3 (ADC_TypeDef *ADCx)
Disable interruption ADC analog watchdog 3.
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_ADRDY (ADC_TypeDef *ADCx)
Get state of interruption ADC ready (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_EOC (ADC_TypeDef *ADCx)
Get state of interruption ADC group regular end of unitary conversion (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_EOS (ADC_TypeDef *ADCx)
Get state of interruption ADC group regular end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_OVR (ADC_TypeDef *ADCx)
Get state of interruption ADC group regular overrun (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_EOSMP (ADC_TypeDef *ADCx)
Get state of interruption ADC group regular end of sampling (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_JEOC (ADC_TypeDef *ADCx)
Get state of interruption ADC group injected end of unitary conversion (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_JEOS (ADC_TypeDef *ADCx)
Get state of interruption ADC group injected end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_JQOVF (ADC_TypeDef *ADCx)
Get state of interruption ADC group injected context queue overflow interrupt state (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_AWD1 (ADC_TypeDef *ADCx)
Get state of interruption ADC analog watchdog 1 (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_AWD2 (ADC_TypeDef *ADCx)
Get state of interruption Get ADC analog watchdog 2 (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_AWD3 (ADC_TypeDef *ADCx)
Get state of interruption Get ADC analog watchdog 3 (0: interrupt disabled, 1: interrupt enabled).
ErrorStatus | LL_ADC_CommonDeInit (ADC_Common_TypeDef *ADCxy_COMMON)
De-initialize registers of all ADC instances belonging to the same ADC common instance to their default reset values.
ErrorStatus | LL_ADC_CommonInit (ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Initialize some features of ADC common parameters (all ADC instances belonging to the same ADC common instance) and multimode (for devices with several ADC instances available).
void | LL_ADC_CommonStructInit (LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Set each LL_ADC_CommonInitTypeDef field to default value.
ErrorStatus | LL_ADC_DeInit (ADC_TypeDef *ADCx)
De-initialize registers of the selected ADC instance to their default reset values.
ErrorStatus | LL_ADC_Init (ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
Initialize some features of ADC instance.
void | LL_ADC_StructInit (LL_ADC_InitTypeDef *ADC_InitStruct)
Set each LL_ADC_InitTypeDef field to default value.
ErrorStatus | LL_ADC_REG_Init (ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
Initialize some features of ADC group regular.
void | LL_ADC_REG_StructInit (LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
Set each LL_ADC_REG_InitTypeDef field to default value.
ErrorStatus | LL_ADC_INJ_Init (ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
Initialize some features of ADC group injected.
void | LL_ADC_INJ_StructInit (LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
Set each LL_ADC_INJ_InitTypeDef field to default value.

Detailed Description

Header file of ADC LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_adc.h.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_bus.h File Reference

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Defines | Functions
stm32wbxx_ll_bus.h File Reference

Header file of BUS LL module. More...

#include "stm32wbxx.h"

Go to the source code of this file.

Defines

#define | LL_AHB1_GRP1_PERIPH_ALL (0xFFFFFFFFU)
#define | LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
#define | LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
#define | LL_AHB1_GRP1_PERIPH_DMAMUX1 RCC_AHB1ENR_DMAMUX1EN
#define | LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1SMENR_SRAM1SMEN
#define | LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
#define | LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN
#define | LL_AHB2_GRP1_PERIPH_ALL (0xFFFFFFFFU)
#define | LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN
#define | LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN
#define | LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN
#define | LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN
#define | LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN
#define | LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR_GPIOHEN
#define | LL_AHB2_GRP1_PERIPH_ADC RCC_AHB2ENR_ADCEN
#define | LL_AHB2_GRP1_PERIPH_AES1 RCC_AHB2ENR_AES1EN
#define | LL_AHB3_GRP1_PERIPH_ALL (0xFFFFFFFFU)
#define | LL_AHB3_GRP1_PERIPH_QUADSPI RCC_AHB3ENR_QUADSPIEN
#define | LL_AHB3_GRP1_PERIPH_PKA RCC_AHB3ENR_PKAEN
#define | LL_AHB3_GRP1_PERIPH_AES2 RCC_AHB3ENR_AES2EN
#define | LL_AHB3_GRP1_PERIPH_RNG RCC_AHB3ENR_RNGEN
#define | LL_AHB3_GRP1_PERIPH_HSEM RCC_AHB3ENR_HSEMEN
#define | LL_AHB3_GRP1_PERIPH_IPCC RCC_AHB3ENR_IPCCEN
#define | LL_AHB3_GRP1_PERIPH_SRAM2 RCC_AHB3SMENR_SRAM2SMEN
#define | LL_AHB3_GRP1_PERIPH_FLASH RCC_AHB3ENR_FLASHEN
#define | LL_APB1_GRP1_PERIPH_ALL (0xFFFFFFFFU)
#define | LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN
#define | LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR1_LCDEN
#define | LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR1_RTCAPBEN
#define | LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN
#define | LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN
#define | LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN
#define | LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN
#define | LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR1_CRSEN
#define | LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR1_USBEN
#define | LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN
#define | LL_APB1_GRP2_PERIPH_ALL (0xFFFFFFFFU)
#define | LL_APB1_GRP2_PERIPH_LPUART1 RCC_APB1ENR2_LPUART1EN
#define | LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1ENR2_LPTIM2EN
#define | LL_APB2_GRP1_PERIPH_ALL (0xFFFFFFFFU)
#define | LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
#define | LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
#define | LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
#define | LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
#define | LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
#define | LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
#define | LL_APB3_GRP1_PERIPH_ALL (0xFFFFFFFFU)
#define | LL_APB3_GRP1_PERIPH_RF RCC_APB3RSTR_RFRST
#define | LL_C2_AHB1_GRP1_PERIPH_DMA1 RCC_C2AHB1ENR_DMA1EN
#define | LL_C2_AHB1_GRP1_PERIPH_DMA2 RCC_C2AHB1ENR_DMA2EN
#define | LL_C2_AHB1_GRP1_PERIPH_DMAMUX1 RCC_C2AHB1ENR_DMAMUX1EN
#define | LL_C2_AHB1_GRP1_PERIPH_SRAM1 RCC_C2AHB1ENR_SRAM1EN
#define | LL_C2_AHB1_GRP1_PERIPH_CRC RCC_C2AHB1ENR_CRCEN
#define | LL_C2_AHB1_GRP1_PERIPH_TSC RCC_C2AHB1ENR_TSCEN
#define | LL_C2_AHB2_GRP1_PERIPH_GPIOA RCC_C2AHB2ENR_GPIOAEN
#define | LL_C2_AHB2_GRP1_PERIPH_GPIOB RCC_C2AHB2ENR_GPIOBEN
#define | LL_C2_AHB2_GRP1_PERIPH_GPIOC RCC_C2AHB2ENR_GPIOCEN
#define | LL_C2_AHB2_GRP1_PERIPH_GPIOD RCC_C2AHB2ENR_GPIODEN
#define | LL_C2_AHB2_GRP1_PERIPH_GPIOE RCC_C2AHB2ENR_GPIOEEN
#define | LL_C2_AHB2_GRP1_PERIPH_GPIOH RCC_C2AHB2ENR_GPIOHEN
#define | LL_C2_AHB2_GRP1_PERIPH_ADC RCC_C2AHB2ENR_ADCEN
#define | LL_C2_AHB2_GRP1_PERIPH_AES1 RCC_C2AHB2ENR_AES1EN
#define | LL_C2_AHB3_GRP1_PERIPH_PKA RCC_C2AHB3ENR_PKAEN
#define | LL_C2_AHB3_GRP1_PERIPH_AES2 RCC_C2AHB3ENR_AES2EN
#define | LL_C2_AHB3_GRP1_PERIPH_RNG RCC_C2AHB3ENR_RNGEN
#define | LL_C2_AHB3_GRP1_PERIPH_HSEM RCC_C2AHB3ENR_HSEMEN
#define | LL_C2_AHB3_GRP1_PERIPH_IPCC RCC_C2AHB3ENR_IPCCEN
#define | LL_C2_AHB3_GRP1_PERIPH_FLASH RCC_C2AHB3ENR_FLASHEN
#define | LL_C2_AHB3_GRP1_PERIPH_SRAM2 RCC_C2AHB3SMENR_SRAM2SMEN
#define | LL_C2_APB1_GRP1_PERIPH_TIM2 RCC_C2APB1ENR1_TIM2EN
#define | LL_C2_APB1_GRP1_PERIPH_LCD RCC_C2APB1ENR1_LCDEN
#define | LL_C2_APB1_GRP1_PERIPH_RTCAPB RCC_C2APB1ENR1_RTCAPBEN
#define | LL_C2_APB1_GRP1_PERIPH_SPI2 RCC_C2APB1ENR1_SPI2EN
#define | LL_C2_APB1_GRP1_PERIPH_I2C1 RCC_C2APB1ENR1_I2C1EN
#define | LL_C2_APB1_GRP1_PERIPH_I2C3 RCC_C2APB1ENR1_I2C3EN
#define | LL_C2_APB1_GRP1_PERIPH_CRS RCC_C2APB1ENR1_CRSEN
#define | LL_C2_APB1_GRP1_PERIPH_USB RCC_C2APB1ENR1_USBEN
#define | LL_C2_APB1_GRP1_PERIPH_LPTIM1 RCC_C2APB1ENR1_LPTIM1EN
#define | LL_C2_APB1_GRP2_PERIPH_LPUART1 RCC_C2APB1ENR2_LPUART1EN
#define | LL_C2_APB1_GRP2_PERIPH_LPTIM2 RCC_C2APB1ENR2_LPTIM2EN
#define | LL_C2_APB2_GRP1_PERIPH_TIM1 RCC_C2APB2ENR_TIM1EN
#define | LL_C2_APB2_GRP1_PERIPH_SPI1 RCC_C2APB2ENR_SPI1EN
#define | LL_C2_APB2_GRP1_PERIPH_USART1 RCC_C2APB2ENR_USART1EN
#define | LL_C2_APB2_GRP1_PERIPH_TIM16 RCC_C2APB2ENR_TIM16EN
#define | LL_C2_APB2_GRP1_PERIPH_TIM17 RCC_C2APB2ENR_TIM17EN
#define | LL_C2_APB2_GRP1_PERIPH_SAI1 RCC_C2APB2ENR_SAI1EN
#define | LL_C2_APB3_GRP1_PERIPH_BLE RCC_C2APB3ENR_BLEEN
#define | LL_C2_APB3_GRP1_PERIPH_802 RCC_C2APB3ENR_802EN

Functions

__STATIC_INLINE void | LL_AHB1_GRP1_EnableClock (uint32_t Periphs)
Enable AHB1 peripherals clock.
__STATIC_INLINE uint32_t | LL_AHB1_GRP1_IsEnabledClock (uint32_t Periphs)
Check if AHB1 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_AHB1_GRP1_DisableClock (uint32_t Periphs)
Disable AHB1 peripherals clock.
__STATIC_INLINE void | LL_AHB1_GRP1_ForceReset (uint32_t Periphs)
Force AHB1 peripherals reset.
__STATIC_INLINE void | LL_AHB1_GRP1_ReleaseReset (uint32_t Periphs)
Release AHB1 peripherals reset.
__STATIC_INLINE void | LL_AHB1_GRP1_EnableClockSleep (uint32_t Periphs)
Enable AHB1 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_AHB1_GRP1_DisableClockSleep (uint32_t Periphs)
Disable AHB1 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_AHB2_GRP1_EnableClock (uint32_t Periphs)
Enable AHB2 peripherals clock.
__STATIC_INLINE uint32_t | LL_AHB2_GRP1_IsEnabledClock (uint32_t Periphs)
Check if AHB2 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_AHB2_GRP1_DisableClock (uint32_t Periphs)
Disable AHB2 peripherals clock.
__STATIC_INLINE void | LL_AHB2_GRP1_ForceReset (uint32_t Periphs)
Force AHB2 peripherals reset.
__STATIC_INLINE void | LL_AHB2_GRP1_ReleaseReset (uint32_t Periphs)
Release AHB2 peripherals reset.
__STATIC_INLINE void | LL_AHB2_GRP1_EnableClockSleep (uint32_t Periphs)
Enable AHB2 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_AHB2_GRP1_DisableClockSleep (uint32_t Periphs)
Disable AHB2 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_AHB3_GRP1_EnableClock (uint32_t Periphs)
Enable AHB3 peripherals clock.
__STATIC_INLINE uint32_t | LL_AHB3_GRP1_IsEnabledClock (uint32_t Periphs)
Check if AHB3 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_AHB3_GRP1_DisableClock (uint32_t Periphs)
Disable AHB3 peripherals clock.
__STATIC_INLINE void | LL_AHB3_GRP1_ForceReset (uint32_t Periphs)
Force AHB3 peripherals reset.
__STATIC_INLINE void | LL_AHB3_GRP1_ReleaseReset (uint32_t Periphs)
Release AHB3 peripherals reset.
__STATIC_INLINE void | LL_AHB3_GRP1_EnableClockSleep (uint32_t Periphs)
Enable AHB3 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_AHB3_GRP1_DisableClockSleep (uint32_t Periphs)
Disable AHB3 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_APB1_GRP1_EnableClock (uint32_t Periphs)
Enable APB1 peripherals clock.
__STATIC_INLINE void | LL_APB1_GRP2_EnableClock (uint32_t Periphs)
Enable APB1 peripherals clock.
__STATIC_INLINE uint32_t | LL_APB1_GRP1_IsEnabledClock (uint32_t Periphs)
Check if APB1 peripheral clock is enabled or not.
__STATIC_INLINE uint32_t | LL_APB1_GRP2_IsEnabledClock (uint32_t Periphs)
Check if APB1 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_APB1_GRP1_DisableClock (uint32_t Periphs)
Disable APB1 peripherals clock.
__STATIC_INLINE void | LL_APB1_GRP2_DisableClock (uint32_t Periphs)
Disable APB1 peripherals clock.
__STATIC_INLINE void | LL_APB1_GRP1_ForceReset (uint32_t Periphs)
Force APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP2_ForceReset (uint32_t Periphs)
Force APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP1_ReleaseReset (uint32_t Periphs)
Release APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP2_ReleaseReset (uint32_t Periphs)
Release APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP1_EnableClockSleep (uint32_t Periphs)
Enable APB1 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_APB1_GRP2_EnableClockSleep (uint32_t Periphs)
Enable APB1 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_APB1_GRP1_DisableClockSleep (uint32_t Periphs)
Disable APB1 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_APB1_GRP2_DisableClockSleep (uint32_t Periphs)
Disable APB1 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_APB2_GRP1_EnableClock (uint32_t Periphs)
Enable APB2 peripherals clock.
__STATIC_INLINE uint32_t | LL_APB2_GRP1_IsEnabledClock (uint32_t Periphs)
Check if APB2 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_APB2_GRP1_DisableClock (uint32_t Periphs)
Disable APB2 peripherals clock.
__STATIC_INLINE void | LL_APB2_GRP1_ForceReset (uint32_t Periphs)
Force APB2 peripherals reset.
__STATIC_INLINE void | LL_APB2_GRP1_ReleaseReset (uint32_t Periphs)
Release APB2 peripherals reset.
__STATIC_INLINE void | LL_APB2_GRP1_EnableClockSleep (uint32_t Periphs)
Enable APB2 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_APB2_GRP1_DisableClockSleep (uint32_t Periphs)
Disable APB2 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_APB3_GRP1_ForceReset (uint32_t Periphs)
Force APB3 peripherals reset.
__STATIC_INLINE void | LL_APB3_GRP1_ReleaseReset (uint32_t Periphs)
Release APB3 peripherals reset.
__STATIC_INLINE void | LL_C2_AHB1_GRP1_EnableClock (uint32_t Periphs)
Enable C2AHB1 peripherals clock.
__STATIC_INLINE uint32_t | LL_C2_AHB1_GRP1_IsEnabledClock (uint32_t Periphs)
Check if C2AHB1 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_C2_AHB1_GRP1_DisableClock (uint32_t Periphs)
Disable C2AHB1 peripherals clock.
__STATIC_INLINE void | LL_C2_AHB1_GRP1_EnableClockSleep (uint32_t Periphs)
Enable C2AHB1 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_C2_AHB1_GRP1_DisableClockSleep (uint32_t Periphs)
Disable C2AHB1 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_C2_AHB2_GRP1_EnableClock (uint32_t Periphs)
Enable C2AHB2 peripherals clock.
__STATIC_INLINE uint32_t | LL_C2_AHB2_GRP1_IsEnabledClock (uint32_t Periphs)
Check if C2AHB2 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_C2_AHB2_GRP1_DisableClock (uint32_t Periphs)
Disable C2AHB2 peripherals clock.
__STATIC_INLINE void | LL_C2_AHB2_GRP1_EnableClockSleep (uint32_t Periphs)
Enable C2AHB2 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_C2_AHB2_GRP1_DisableClockSleep (uint32_t Periphs)
Disable C2AHB2 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_C2_AHB3_GRP1_EnableClock (uint32_t Periphs)
Enable C2AHB3 peripherals clock.
__STATIC_INLINE uint32_t | LL_C2_AHB3_GRP1_IsEnabledClock (uint32_t Periphs)
Check if C2AHB3 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_C2_AHB3_GRP1_DisableClock (uint32_t Periphs)
Disable C2AHB3 peripherals clock.
__STATIC_INLINE void | LL_C2_AHB3_GRP1_EnableClockSleep (uint32_t Periphs)
Enable C2AHB3 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_C2_AHB3_GRP1_DisableClockSleep (uint32_t Periphs)
Disable C2AHB3 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_C2_APB1_GRP1_EnableClock (uint32_t Periphs)
Enable C2APB1 peripherals clock.
__STATIC_INLINE void | LL_C2_APB1_GRP2_EnableClock (uint32_t Periphs)
Enable C2APB1 peripherals clock.
__STATIC_INLINE uint32_t | LL_C2_APB1_GRP1_IsEnabledClock (uint32_t Periphs)
Check if C2APB1 peripheral clock is enabled or not.
__STATIC_INLINE uint32_t | LL_C2_APB1_GRP2_IsEnabledClock (uint32_t Periphs)
Check if C2APB1 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_C2_APB1_GRP1_DisableClock (uint32_t Periphs)
Disable C2APB1 peripherals clock.
__STATIC_INLINE void | LL_C2_APB1_GRP2_DisableClock (uint32_t Periphs)
Disable C2APB1 peripherals clock.
__STATIC_INLINE void | LL_C2_APB1_GRP1_EnableClockSleep (uint32_t Periphs)
Enable C2APB1 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_C2_APB1_GRP2_EnableClockSleep (uint32_t Periphs)
Enable C2APB1 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_C2_APB1_GRP1_DisableClockSleep (uint32_t Periphs)
Disable C2APB1 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_C2_APB1_GRP2_DisableClockSleep (uint32_t Periphs)
Disable C2APB1 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_C2_APB2_GRP1_EnableClock (uint32_t Periphs)
Enable C2APB2 peripherals clock.
__STATIC_INLINE uint32_t | LL_C2_APB2_GRP1_IsEnabledClock (uint32_t Periphs)
Check if C2APB2 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_C2_APB2_GRP1_DisableClock (uint32_t Periphs)
Disable C2APB2 peripherals clock.
__STATIC_INLINE void | LL_C2_APB2_GRP1_EnableClockSleep (uint32_t Periphs)
Enable C2APB2 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_C2_APB2_GRP1_DisableClockSleep (uint32_t Periphs)
Disable C2APB2 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_C2_APB3_GRP1_EnableClock (uint32_t Periphs)
Enable C2APB3 peripherals clock.
__STATIC_INLINE uint32_t | LL_C2_APB3_GRP1_IsEnabledClock (uint32_t Periphs)
Check if C2APB3 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_C2_APB3_GRP1_DisableClock (uint32_t Periphs)
Disable C2APB3 peripherals clock.
__STATIC_INLINE void | LL_C2_APB3_GRP1_EnableClockSleep (uint32_t Periphs)
Enable C2APB3 peripherals clock during Low Power (Sleep) mode.
__STATIC_INLINE void | LL_C2_APB3_GRP1_DisableClockSleep (uint32_t Periphs)
Disable C2APB3 peripherals clock during Low Power (Sleep) mode.

Detailed Description

Header file of BUS LL module.

Author:
MCD Application Team
                      ##### RCC Limitations #####
  ==============================================================================
    [..]
      A delay between an RCC peripheral clock enable and the effective peripheral
      enabling should be taken into account in order to manage the peripheral read/write
      from/to registers.
      (+) This delay depends on the peripheral mapping.
        (++) AHB & APB peripherals, 1 dummy read is necessary

    [..]
      Workarounds:
      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
          inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_bus.h.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_comp.h File Reference

  • File List
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  • Firmware
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  • STM32WBxx_HAL_Driver
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Data Structures | Defines | Functions
stm32wbxx_ll_comp.h File Reference

Header file of COMP LL module. More...

#include "stm32wbxx.h"

Go to the source code of this file.

Data Structures

struct | LL_COMP_InitTypeDef
Structure definition of some features of COMP instance. More...

Defines

#define | LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS (30UL) /* Value equivalent to POSITION_VAL(COMP_CSR_VALUE) */
#define | LL_COMP_WINDOWMODE_DISABLE (0x00000000UL)
#define | LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE)
#define | LL_COMP_POWERMODE_HIGHSPEED (0x00000000UL)
#define | LL_COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0)
#define | LL_COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_PWRMODE_1 | COMP_CSR_PWRMODE_0)
#define | LL_COMP_INPUT_PLUS_IO1 (0x00000000UL)
#define | LL_COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0)
#define | LL_COMP_INPUT_PLUS_IO3 (COMP_CSR_INPSEL_1)
#define | LL_COMP_INPUT_MINUS_1_4VREFINT ( COMP_CSR_SCALEN | COMP_CSR_BRGEN)
#define | LL_COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)
#define | LL_COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)
#define | LL_COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN )
#define | LL_COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 )
#define | LL_COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)
#define | LL_COMP_INPUT_MINUS_IO3 ( COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)
#define | LL_COMP_INPUT_MINUS_IO4 (COMP_CSR_INMESEL_1 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)
#define | LL_COMP_INPUT_MINUS_IO5 (COMP_CSR_INMESEL_1 | COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)
#define | LL_COMP_HYSTERESIS_NONE (0x00000000UL)
#define | LL_COMP_HYSTERESIS_LOW ( COMP_CSR_HYST_0)
#define | LL_COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1 )
#define | LL_COMP_HYSTERESIS_HIGH (COMP_CSR_HYST_1 | COMP_CSR_HYST_0)
#define | LL_COMP_OUTPUTPOL_NONINVERTED (0x00000000UL)
#define | LL_COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY)
#define | LL_COMP_BLANKINGSRC_NONE (0x00000000UL)
#define | LL_COMP_BLANKINGSRC_TIM1_OC5 (COMP_CSR_BLANKING_0)
#define | LL_COMP_BLANKINGSRC_TIM2_OC3 (COMP_CSR_BLANKING_1)
#define | LL_COMP_OUTPUT_LEVEL_LOW (0x00000000UL)
#define | LL_COMP_OUTPUT_LEVEL_HIGH (0x00000001UL)
#define | LL_COMP_DELAY_STARTUP_US ( 80UL)
#define | LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US ( 200UL)
#define | LL_COMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
Write a value in COMP register.
#define | LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
Read a value in COMP register.
#define | __LL_COMP_COMMON_INSTANCE(__COMPx__) (COMP12_COMMON)
Helper macro to select the COMP common instance to which is belonging the selected COMP instance.

Functions

__STATIC_INLINE void | LL_COMP_SetCommonWindowMode (COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode)
Set window mode of a pair of comparators instances (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
__STATIC_INLINE uint32_t | LL_COMP_GetCommonWindowMode (COMP_Common_TypeDef *COMPxy_COMMON)
Get window mode of a pair of comparators instances (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
__STATIC_INLINE void | LL_COMP_SetPowerMode (COMP_TypeDef *COMPx, uint32_t PowerMode)
Set comparator instance operating mode to adjust power and speed.
__STATIC_INLINE uint32_t | LL_COMP_GetPowerMode (COMP_TypeDef *COMPx)
Get comparator instance operating mode to adjust power and speed.
__STATIC_INLINE void | LL_COMP_ConfigInputs (COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputPlus)
Set comparator inputs minus (inverting) and plus (non-inverting).
__STATIC_INLINE void | LL_COMP_SetInputPlus (COMP_TypeDef *COMPx, uint32_t InputPlus)
Set comparator input plus (non-inverting).
__STATIC_INLINE uint32_t | LL_COMP_GetInputPlus (COMP_TypeDef *COMPx)
Get comparator input plus (non-inverting).
__STATIC_INLINE void | LL_COMP_SetInputMinus (COMP_TypeDef *COMPx, uint32_t InputMinus)
Set comparator input minus (inverting).
__STATIC_INLINE uint32_t | LL_COMP_GetInputMinus (COMP_TypeDef *COMPx)
Get comparator input minus (inverting).
__STATIC_INLINE void | LL_COMP_SetInputHysteresis (COMP_TypeDef *COMPx, uint32_t InputHysteresis)
Set comparator instance hysteresis mode of the input minus (inverting input).
__STATIC_INLINE uint32_t | LL_COMP_GetInputHysteresis (COMP_TypeDef *COMPx)
Get comparator instance hysteresis mode of the minus (inverting) input.
__STATIC_INLINE void | LL_COMP_SetOutputPolarity (COMP_TypeDef *COMPx, uint32_t OutputPolarity)
Set comparator instance output polarity.
__STATIC_INLINE uint32_t | LL_COMP_GetOutputPolarity (COMP_TypeDef *COMPx)
Get comparator instance output polarity.
__STATIC_INLINE void | LL_COMP_SetOutputBlankingSource (COMP_TypeDef *COMPx, uint32_t BlankingSource)
Set comparator instance blanking source.
__STATIC_INLINE uint32_t | LL_COMP_GetOutputBlankingSource (COMP_TypeDef *COMPx)
Get comparator instance blanking source.
__STATIC_INLINE void | LL_COMP_Enable (COMP_TypeDef *COMPx)
Enable comparator instance.
__STATIC_INLINE void | LL_COMP_Disable (COMP_TypeDef *COMPx)
Disable comparator instance.
__STATIC_INLINE uint32_t | LL_COMP_IsEnabled (COMP_TypeDef *COMPx)
Get comparator enable state (0: COMP is disabled, 1: COMP is enabled)
__STATIC_INLINE void | LL_COMP_Lock (COMP_TypeDef *COMPx)
Lock comparator instance.
__STATIC_INLINE uint32_t | LL_COMP_IsLocked (COMP_TypeDef *COMPx)
Get comparator lock state (0: COMP is unlocked, 1: COMP is locked).
__STATIC_INLINE uint32_t | LL_COMP_ReadOutputLevel (COMP_TypeDef *COMPx)
Read comparator instance output level.
ErrorStatus | LL_COMP_DeInit (COMP_TypeDef *COMPx)
De-initialize registers of the selected COMP instance to their default reset values.
ErrorStatus | LL_COMP_Init (COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct)
Initialize some features of COMP instance.
void | LL_COMP_StructInit (LL_COMP_InitTypeDef *COMP_InitStruct)
Set each LL_COMP_InitTypeDef field to default value.

Detailed Description

Header file of COMP LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_comp.h.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_cortex.h File Reference

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Defines | Functions
stm32wbxx_ll_cortex.h File Reference

Header file of CORTEX LL module. More...

#include "stm32wbxx.h"

Go to the source code of this file.

Defines

#define | LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
#define | LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk
#define | LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk
#define | LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk
#define | LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk
#define | LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U
#define | LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk
#define | LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
#define | LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
#define | LL_MPU_REGION_NUMBER0 0x00U
#define | LL_MPU_REGION_NUMBER1 0x01U
#define | LL_MPU_REGION_NUMBER2 0x02U
#define | LL_MPU_REGION_NUMBER3 0x03U
#define | LL_MPU_REGION_NUMBER4 0x04U
#define | LL_MPU_REGION_NUMBER5 0x05U
#define | LL_MPU_REGION_NUMBER6 0x06U
#define | LL_MPU_REGION_NUMBER7 0x07U
#define | LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos)
#define | LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos)
#define | LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos)
#define | LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos)
#define | LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos)
#define | LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos)
#define | LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos)
#define | LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U
#define | LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk
#define | LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk
#define | LL_MPU_ACCESS_NOT_SHAREABLE 0x00U
#define | LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk
#define | LL_MPU_ACCESS_NOT_CACHEABLE 0x00U
#define | LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk
#define | LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U

Functions

__STATIC_INLINE uint32_t | LL_SYSTICK_IsActiveCounterFlag (void)
This function checks if the Systick counter flag is active or not.
__STATIC_INLINE void | LL_SYSTICK_SetClkSource (uint32_t Source)
Configures the SysTick clock source.
__STATIC_INLINE uint32_t | LL_SYSTICK_GetClkSource (void)
Get the SysTick clock source.
__STATIC_INLINE void | LL_SYSTICK_EnableIT (void)
Enable SysTick exception request.
__STATIC_INLINE void | LL_SYSTICK_DisableIT (void)
Disable SysTick exception request.
__STATIC_INLINE uint32_t | LL_SYSTICK_IsEnabledIT (void)
Checks if the SYSTICK interrupt is enabled or disabled.
__STATIC_INLINE void | LL_LPM_EnableSleep (void)
Processor uses sleep as its low power mode.
__STATIC_INLINE void | LL_LPM_EnableDeepSleep (void)
Processor uses deep sleep as its low power mode.
__STATIC_INLINE void | LL_LPM_EnableSleepOnExit (void)
Configures sleep-on-exit when returning from Handler mode to Thread mode.
__STATIC_INLINE void | LL_LPM_DisableSleepOnExit (void)
Do not sleep when returning to Thread mode.
__STATIC_INLINE void | LL_LPM_EnableEventOnPend (void)
Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.
__STATIC_INLINE void | LL_LPM_DisableEventOnPend (void)
Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.
__STATIC_INLINE void | LL_HANDLER_EnableFault (uint32_t Fault)
Enable a fault in System handler control register (SHCSR)
__STATIC_INLINE void | LL_HANDLER_DisableFault (uint32_t Fault)
Disable a fault in System handler control register (SHCSR)
__STATIC_INLINE uint32_t | LL_CPUID_GetImplementer (void)
Get Implementer code.
__STATIC_INLINE uint32_t | LL_CPUID_GetVariant (void)
Get Variant number (The r value in the rnpn product revision identifier)
__STATIC_INLINE uint32_t | LL_CPUID_GetConstant (void)
Get Constant number.
__STATIC_INLINE uint32_t | LL_CPUID_GetParNo (void)
Get Part number.
__STATIC_INLINE uint32_t | LL_CPUID_GetRevision (void)
Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
__STATIC_INLINE void | LL_MPU_Enable (uint32_t Options)
Enable MPU with input options.
__STATIC_INLINE void | LL_MPU_Disable (void)
Disable MPU.
__STATIC_INLINE uint32_t | LL_MPU_IsEnabled (void)
Check if MPU is enabled or not.
__STATIC_INLINE void | LL_MPU_EnableRegion (uint32_t Region)
Enable a MPU region.
__STATIC_INLINE void | LL_MPU_ConfigRegion (uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
Configure and enable a region.
__STATIC_INLINE void | LL_MPU_DisableRegion (uint32_t Region)
Disable a region.

Detailed Description

Header file of CORTEX LL module.

Author:
MCD Application Team
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The LL CORTEX driver contains a set of generic APIs that can be
    used by user:
      (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
          functions
      (+) Low power mode configuration (SCB register of Cortex-MCU)
      (+) MPU API to configure and enable regions
      (+) API to access to MCU info (CPUID register)
      (+) API to enable fault handler (SHCSR accesses)
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_cortex.h.

Generated on Fri Sep 6 2019 11:34:39 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_crc.h File Reference

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Defines | Functions
stm32wbxx_ll_crc.h File Reference

Header file of CRC LL module. More...

#include "stm32wbxx.h"

Go to the source code of this file.

Defines

#define | LL_CRC_POLYLENGTH_32B 0x00000000U
#define | LL_CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0
#define | LL_CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1
#define | LL_CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0)
#define | LL_CRC_INDATA_REVERSE_NONE 0x00000000U
#define | LL_CRC_INDATA_REVERSE_BYTE CRC_CR_REV_IN_0
#define | LL_CRC_INDATA_REVERSE_HALFWORD CRC_CR_REV_IN_1
#define | LL_CRC_INDATA_REVERSE_WORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0)
#define | LL_CRC_OUTDATA_REVERSE_NONE 0x00000000U
#define | LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT
#define | LL_CRC_DEFAULT_CRC32_POLY 0x04C11DB7U
#define | LL_CRC_DEFAULT_CRC_INITVALUE 0xFFFFFFFFU
#define | LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__)
Write a value in CRC register.
#define | LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in CRC register.

Functions

__STATIC_INLINE void | LL_CRC_ResetCRCCalculationUnit (CRC_TypeDef *CRCx)
Reset the CRC calculation unit.
__STATIC_INLINE void | LL_CRC_SetPolynomialSize (CRC_TypeDef *CRCx, uint32_t PolySize)
Configure size of the polynomial.
__STATIC_INLINE uint32_t | LL_CRC_GetPolynomialSize (CRC_TypeDef *CRCx)
Return size of the polynomial.
__STATIC_INLINE void | LL_CRC_SetInputDataReverseMode (CRC_TypeDef *CRCx, uint32_t ReverseMode)
Configure the reversal of the bit order of the input data.
__STATIC_INLINE uint32_t | LL_CRC_GetInputDataReverseMode (CRC_TypeDef *CRCx)
Return type of reversal for input data bit order.
__STATIC_INLINE void | LL_CRC_SetOutputDataReverseMode (CRC_TypeDef *CRCx, uint32_t ReverseMode)
Configure the reversal of the bit order of the Output data.
__STATIC_INLINE uint32_t | LL_CRC_GetOutputDataReverseMode (CRC_TypeDef *CRCx)
Configure the reversal of the bit order of the Output data.
__STATIC_INLINE void | LL_CRC_SetInitialData (CRC_TypeDef *CRCx, uint32_t InitCrc)
Initialize the Programmable initial CRC value.
__STATIC_INLINE uint32_t | LL_CRC_GetInitialData (CRC_TypeDef *CRCx)
Return current Initial CRC value.
__STATIC_INLINE void | LL_CRC_SetPolynomialCoef (CRC_TypeDef *CRCx, uint32_t PolynomCoef)
Initialize the Programmable polynomial value (coefficients of the polynomial to be used for CRC calculation).
__STATIC_INLINE uint32_t | LL_CRC_GetPolynomialCoef (CRC_TypeDef *CRCx)
Return current Programmable polynomial value.
__STATIC_INLINE void | LL_CRC_FeedData32 (CRC_TypeDef *CRCx, uint32_t InData)
Write given 32-bit data to the CRC calculator.
__STATIC_INLINE void | LL_CRC_FeedData16 (CRC_TypeDef *CRCx, uint16_t InData)
Write given 16-bit data to the CRC calculator.
__STATIC_INLINE void | LL_CRC_FeedData8 (CRC_TypeDef *CRCx, uint8_t InData)
Write given 8-bit data to the CRC calculator.
__STATIC_INLINE uint32_t | LL_CRC_ReadData32 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint16_t | LL_CRC_ReadData16 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint8_t | LL_CRC_ReadData8 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint8_t | LL_CRC_ReadData7 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint32_t | LL_CRC_Read_IDR (CRC_TypeDef *CRCx)
Return data stored in the Independent Data(IDR) register.
__STATIC_INLINE void | LL_CRC_Write_IDR (CRC_TypeDef *CRCx, uint32_t InData)
Store data in the Independent Data(IDR) register.
ErrorStatus | LL_CRC_DeInit (CRC_TypeDef *CRCx)
De-initialize CRC registers (Registers restored to their default values).

Detailed Description

Header file of CRC LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_crc.h.

Generated on Fri Sep 6 2019 11:34:39 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_crs.h File Reference

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Defines | Functions
stm32wbxx_ll_crs.h File Reference

CRS LL module driver. More...

#include "stm32wbxx.h"

Go to the source code of this file.

Defines

#define | CRS_POSITION_TRIM (CRS_CR_TRIM_Pos) /* bit position in CR reg */
#define | CRS_POSITION_FECAP (CRS_ISR_FECAP_Pos) /* bit position in ISR reg */
#define | CRS_POSITION_FELIM (CRS_CFGR_FELIM_Pos) /* bit position in CFGR reg */
#define | LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF
#define | LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF
#define | LL_CRS_ISR_ERRF CRS_ISR_ERRF
#define | LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF
#define | LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR
#define | LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS
#define | LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF
#define | LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE
#define | LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE
#define | LL_CRS_CR_ERRIE CRS_CR_ERRIE
#define | LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE
#define | LL_CRS_SYNC_DIV_1 0x00000000U
#define | LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0
#define | LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1
#define | LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0)
#define | LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2
#define | LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0)
#define | LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1)
#define | LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV
#define | LL_CRS_SYNC_SOURCE_GPIO 0x00000000U
#define | LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0
#define | LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1
#define | LL_CRS_SYNC_POLARITY_RISING 0x00000000U
#define | LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL
#define | LL_CRS_FREQ_ERROR_DIR_UP 0x00000000U
#define | LL_CRS_FREQ_ERROR_DIR_DOWN CRS_ISR_FEDIR
#define | LL_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU
Reset value of the RELOAD field.
#define | LL_CRS_ERRORLIMIT_DEFAULT 0x00000022U
Reset value of Frequency error limit.
#define | LL_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U
Reset value of the HSI48 Calibration field.
#define | LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in CRS register.
#define | LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in CRS register.
#define | __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
Macro to calculate reload value to be set in CRS register according to target and sync frequencies.

Functions

__STATIC_INLINE void | LL_CRS_EnableFreqErrorCounter (void)
Enable Frequency error counter.
__STATIC_INLINE void | LL_CRS_DisableFreqErrorCounter (void)
Disable Frequency error counter.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledFreqErrorCounter (void)
Check if Frequency error counter is enabled or not.
__STATIC_INLINE void | LL_CRS_EnableAutoTrimming (void)
Enable Automatic trimming counter.
__STATIC_INLINE void | LL_CRS_DisableAutoTrimming (void)
Disable Automatic trimming counter.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledAutoTrimming (void)
Check if Automatic trimming is enabled or not.
__STATIC_INLINE void | LL_CRS_SetHSI48SmoothTrimming (uint32_t Value)
Set HSI48 oscillator smooth trimming.
__STATIC_INLINE uint32_t | LL_CRS_GetHSI48SmoothTrimming (void)
Get HSI48 oscillator smooth trimming.
__STATIC_INLINE void | LL_CRS_SetReloadCounter (uint32_t Value)
Set counter reload value.
__STATIC_INLINE uint32_t | LL_CRS_GetReloadCounter (void)
Get counter reload value.
__STATIC_INLINE void | LL_CRS_SetFreqErrorLimit (uint32_t Value)
Set frequency error limit.
__STATIC_INLINE uint32_t | LL_CRS_GetFreqErrorLimit (void)
Get frequency error limit.
__STATIC_INLINE void | LL_CRS_SetSyncDivider (uint32_t Divider)
Set division factor for SYNC signal.
__STATIC_INLINE uint32_t | LL_CRS_GetSyncDivider (void)
Get division factor for SYNC signal.
__STATIC_INLINE void | LL_CRS_SetSyncSignalSource (uint32_t Source)
Set SYNC signal source.
__STATIC_INLINE uint32_t | LL_CRS_GetSyncSignalSource (void)
Get SYNC signal source.
__STATIC_INLINE void | LL_CRS_SetSyncPolarity (uint32_t Polarity)
Set input polarity for the SYNC signal source.
__STATIC_INLINE uint32_t | LL_CRS_GetSyncPolarity (void)
Get input polarity for the SYNC signal source.
__STATIC_INLINE void | LL_CRS_ConfigSynchronization (uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
Configure CRS for the synchronization.
__STATIC_INLINE void | LL_CRS_GenerateEvent_SWSYNC (void)
Generate software SYNC event.
__STATIC_INLINE uint32_t | LL_CRS_GetFreqErrorDirection (void)
Get the frequency error direction latched in the time of the last SYNC event.
__STATIC_INLINE uint32_t | LL_CRS_GetFreqErrorCapture (void)
Get the frequency error counter value latched in the time of the last SYNC event.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_SYNCOK (void)
Check if SYNC event OK signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_SYNCWARN (void)
Check if SYNC warning signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_ERR (void)
Check if Synchronization or trimming error signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_ESYNC (void)
Check if Expected SYNC signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_SYNCERR (void)
Check if SYNC error signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_SYNCMISS (void)
Check if SYNC missed error signal occurred or not.
__STATIC_INLINE uint32_t | LL_CRS_IsActiveFlag_TRIMOVF (void)
Check if Trimming overflow or underflow occurred or not.
__STATIC_INLINE void | LL_CRS_ClearFlag_SYNCOK (void)
Clear the SYNC event OK flag.
__STATIC_INLINE void | LL_CRS_ClearFlag_SYNCWARN (void)
Clear the SYNC warning flag.
__STATIC_INLINE void | LL_CRS_ClearFlag_ERR (void)
Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also the ERR flag.
__STATIC_INLINE void | LL_CRS_ClearFlag_ESYNC (void)
Clear Expected SYNC flag.
__STATIC_INLINE void | LL_CRS_EnableIT_SYNCOK (void)
Enable SYNC event OK interrupt.
__STATIC_INLINE void | LL_CRS_DisableIT_SYNCOK (void)
Disable SYNC event OK interrupt.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledIT_SYNCOK (void)
Check if SYNC event OK interrupt is enabled or not.
__STATIC_INLINE void | LL_CRS_EnableIT_SYNCWARN (void)
Enable SYNC warning interrupt.
__STATIC_INLINE void | LL_CRS_DisableIT_SYNCWARN (void)
Disable SYNC warning interrupt.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledIT_SYNCWARN (void)
Check if SYNC warning interrupt is enabled or not.
__STATIC_INLINE void | LL_CRS_EnableIT_ERR (void)
Enable Synchronization or trimming error interrupt.
__STATIC_INLINE void | LL_CRS_DisableIT_ERR (void)
Disable Synchronization or trimming error interrupt.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledIT_ERR (void)
Check if Synchronization or trimming error interrupt is enabled or not.
__STATIC_INLINE void | LL_CRS_EnableIT_ESYNC (void)
Enable Expected SYNC interrupt.
__STATIC_INLINE void | LL_CRS_DisableIT_ESYNC (void)
Disable Expected SYNC interrupt.
__STATIC_INLINE uint32_t | LL_CRS_IsEnabledIT_ESYNC (void)
Check if Expected SYNC interrupt is enabled or not.
ErrorStatus | LL_CRS_DeInit (void)
De-Initializes CRS peripheral registers to their default reset values.

Detailed Description

CRS LL module driver.

Header file of CRS LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_crs.h.

Generated on Fri Sep 6 2019 11:34:39 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_dma.h File Reference

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Data Structures | Defines | Functions
stm32wbxx_ll_dma.h File Reference

Header file of DMA LL module. More...

#include "stm32wbxx.h"
#include "stm32wbxx_ll_dmamux.h"

Go to the source code of this file.

Data Structures

struct | LL_DMA_InitTypeDef

Defines

#define | __LL_DMA_INSTANCE_TO_CHANNEL(__DMA_INSTANCE__, __CHANNEL_INDEX__) (((__DMA_INSTANCE__) == DMA1) ? (DMA1_Channel1 + (__CHANNEL_INDEX__)) : (DMA2_Channel1 + (__CHANNEL_INDEX__)))
Helper macro to convert DMA Instance and index into DMA channel.
#define | __LL_DMA_INSTANCE_TO_DMAMUX_CCR(__DMA_INSTANCE__, __CHANNEL_INDEX__) (((__DMA_INSTANCE__) == DMA1) ? (DMAMUX1_Channel0 + (__CHANNEL_INDEX__)) : (DMAMUX1_Channel7 + (__CHANNEL_INDEX__)))
Helper macro to convert DMA Instance and index into DMAMUX channel.
#define | LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1
#define | LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1
#define | LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1
#define | LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1
#define | LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2
#define | LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2
#define | LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2
#define | LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2
#define | LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3
#define | LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3
#define | LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3
#define | LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3
#define | LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4
#define | LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4
#define | LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4
#define | LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4
#define | LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5
#define | LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5
#define | LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5
#define | LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5
#define | LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6
#define | LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6
#define | LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6
#define | LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6
#define | LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7
#define | LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7
#define | LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7
#define | LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7
#define | LL_DMA_ISR_GIF1 DMA_ISR_GIF1
#define | LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1
#define | LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1
#define | LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1
#define | LL_DMA_ISR_GIF2 DMA_ISR_GIF2
#define | LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2
#define | LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2
#define | LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2
#define | LL_DMA_ISR_GIF3 DMA_ISR_GIF3
#define | LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3
#define | LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3
#define | LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3
#define | LL_DMA_ISR_GIF4 DMA_ISR_GIF4
#define | LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4
#define | LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4
#define | LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4
#define | LL_DMA_ISR_GIF5 DMA_ISR_GIF5
#define | LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5
#define | LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5
#define | LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5
#define | LL_DMA_ISR_GIF6 DMA_ISR_GIF6
#define | LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6
#define | LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6
#define | LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6
#define | LL_DMA_ISR_GIF7 DMA_ISR_GIF7
#define | LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7
#define | LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7
#define | LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7
#define | LL_DMA_CCR_TCIE DMA_CCR_TCIE
#define | LL_DMA_CCR_HTIE DMA_CCR_HTIE
#define | LL_DMA_CCR_TEIE DMA_CCR_TEIE
#define | LL_DMA_CHANNEL_1 0x00000001U
#define | LL_DMA_CHANNEL_2 0x00000002U
#define | LL_DMA_CHANNEL_3 0x00000003U
#define | LL_DMA_CHANNEL_4 0x00000004U
#define | LL_DMA_CHANNEL_5 0x00000005U
#define | LL_DMA_CHANNEL_6 0x00000006U
#define | LL_DMA_CHANNEL_7 0x00000007U
#define | LL_DMA_CHANNEL_ALL 0xFFFF0000U
#define | LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U
#define | LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR
#define | LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM
#define | LL_DMA_MODE_NORMAL 0x00000000U
#define | LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC
#define | LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC
#define | LL_DMA_PERIPH_NOINCREMENT 0x00000000U
#define | LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC
#define | LL_DMA_MEMORY_NOINCREMENT 0x00000000U
#define | LL_DMA_PDATAALIGN_BYTE 0x00000000U
#define | LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0
#define | LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1
#define | LL_DMA_MDATAALIGN_BYTE 0x00000000U
#define | LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0
#define | LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1
#define | LL_DMA_PRIORITY_LOW 0x00000000U
#define | LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0
#define | LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1
#define | LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL
#define | LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in DMA register.
#define | LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in DMA register.
#define | __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
Convert DMAx_Channely into DMAx.
#define | __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)
Convert DMAx_Channely into LL_DMA_CHANNEL_y.
#define | __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)
Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely.

Functions

__STATIC_INLINE void | LL_DMA_EnableChannel (DMA_TypeDef *DMAx, uint32_t Channel)
Enable DMA channel.
__STATIC_INLINE void | LL_DMA_DisableChannel (DMA_TypeDef *DMAx, uint32_t Channel)
Disable DMA channel.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledChannel (DMA_TypeDef *DMAx, uint32_t Channel)
Check if DMA channel is enabled or disabled.
__STATIC_INLINE void | LL_DMA_ConfigTransfer (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
Configure all parameters link to DMA transfer.
__STATIC_INLINE void | LL_DMA_SetDataTransferDirection (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
Set Data transfer direction (read from peripheral or from memory).
__STATIC_INLINE uint32_t | LL_DMA_GetDataTransferDirection (DMA_TypeDef *DMAx, uint32_t Channel)
Get Data transfer direction (read from peripheral or from memory).
__STATIC_INLINE void | LL_DMA_SetMode (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
Set DMA mode circular or normal.
__STATIC_INLINE uint32_t | LL_DMA_GetMode (DMA_TypeDef *DMAx, uint32_t Channel)
Get DMA mode circular or normal.
__STATIC_INLINE void | LL_DMA_SetPeriphIncMode (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
Set Peripheral increment mode.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphIncMode (DMA_TypeDef *DMAx, uint32_t Channel)
Get Peripheral increment mode.
__STATIC_INLINE void | LL_DMA_SetMemoryIncMode (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
Set Memory increment mode.
__STATIC_INLINE uint32_t | LL_DMA_GetMemoryIncMode (DMA_TypeDef *DMAx, uint32_t Channel)
Get Memory increment mode.
__STATIC_INLINE void | LL_DMA_SetPeriphSize (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
Set Peripheral size.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphSize (DMA_TypeDef *DMAx, uint32_t Channel)
Get Peripheral size.
__STATIC_INLINE void | LL_DMA_SetMemorySize (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
Set Memory size.
__STATIC_INLINE uint32_t | LL_DMA_GetMemorySize (DMA_TypeDef *DMAx, uint32_t Channel)
Get Memory size.
__STATIC_INLINE void | LL_DMA_SetChannelPriorityLevel (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
Set Channel priority level.
__STATIC_INLINE uint32_t | LL_DMA_GetChannelPriorityLevel (DMA_TypeDef *DMAx, uint32_t Channel)
Get Channel priority level.
__STATIC_INLINE void | LL_DMA_SetDataLength (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
Set Number of data to transfer.
__STATIC_INLINE uint32_t | LL_DMA_GetDataLength (DMA_TypeDef *DMAx, uint32_t Channel)
Get Number of data to transfer.
__STATIC_INLINE void | LL_DMA_ConfigAddresses (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
Configure the Source and Destination addresses.
__STATIC_INLINE void | LL_DMA_SetMemoryAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory address.
__STATIC_INLINE void | LL_DMA_SetPeriphAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
Set the Peripheral address.
__STATIC_INLINE uint32_t | LL_DMA_GetMemoryAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get Memory address.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get Peripheral address.
__STATIC_INLINE void | LL_DMA_SetM2MSrcAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory to Memory Source address.
__STATIC_INLINE void | LL_DMA_SetM2MDstAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory to Memory Destination address.
__STATIC_INLINE uint32_t | LL_DMA_GetM2MSrcAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get the Memory to Memory Source address.
__STATIC_INLINE uint32_t | LL_DMA_GetM2MDstAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get the Memory to Memory Destination address.
__STATIC_INLINE void | LL_DMA_SetPeriphRequest (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
Set DMA request for DMA Channels on DMAMUX Channel x.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphRequest (DMA_TypeDef *DMAx, uint32_t Channel)
Get DMA request for DMA Channels on DMAMUX Channel x.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI1 (DMA_TypeDef *DMAx)
Get Channel 1 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI2 (DMA_TypeDef *DMAx)
Get Channel 2 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI3 (DMA_TypeDef *DMAx)
Get Channel 3 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI4 (DMA_TypeDef *DMAx)
Get Channel 4 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI5 (DMA_TypeDef *DMAx)
Get Channel 5 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI6 (DMA_TypeDef *DMAx)
Get Channel 6 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI7 (DMA_TypeDef *DMAx)
Get Channel 7 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC1 (DMA_TypeDef *DMAx)
Get Channel 1 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC2 (DMA_TypeDef *DMAx)
Get Channel 2 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC3 (DMA_TypeDef *DMAx)
Get Channel 3 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC4 (DMA_TypeDef *DMAx)
Get Channel 4 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC5 (DMA_TypeDef *DMAx)
Get Channel 5 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC6 (DMA_TypeDef *DMAx)
Get Channel 6 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC7 (DMA_TypeDef *DMAx)
Get Channel 7 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT1 (DMA_TypeDef *DMAx)
Get Channel 1 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT2 (DMA_TypeDef *DMAx)
Get Channel 2 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT3 (DMA_TypeDef *DMAx)
Get Channel 3 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT4 (DMA_TypeDef *DMAx)
Get Channel 4 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT5 (DMA_TypeDef *DMAx)
Get Channel 5 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT6 (DMA_TypeDef *DMAx)
Get Channel 6 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT7 (DMA_TypeDef *DMAx)
Get Channel 7 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE1 (DMA_TypeDef *DMAx)
Get Channel 1 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE2 (DMA_TypeDef *DMAx)
Get Channel 2 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE3 (DMA_TypeDef *DMAx)
Get Channel 3 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE4 (DMA_TypeDef *DMAx)
Get Channel 4 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE5 (DMA_TypeDef *DMAx)
Get Channel 5 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE6 (DMA_TypeDef *DMAx)
Get Channel 6 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE7 (DMA_TypeDef *DMAx)
Get Channel 7 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI1 (DMA_TypeDef *DMAx)
Clear Channel 1 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI2 (DMA_TypeDef *DMAx)
Clear Channel 2 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI3 (DMA_TypeDef *DMAx)
Clear Channel 3 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI4 (DMA_TypeDef *DMAx)
Clear Channel 4 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI5 (DMA_TypeDef *DMAx)
Clear Channel 5 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI6 (DMA_TypeDef *DMAx)
Clear Channel 6 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI7 (DMA_TypeDef *DMAx)
Clear Channel 7 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC1 (DMA_TypeDef *DMAx)
Clear Channel 1 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC2 (DMA_TypeDef *DMAx)
Clear Channel 2 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC3 (DMA_TypeDef *DMAx)
Clear Channel 3 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC4 (DMA_TypeDef *DMAx)
Clear Channel 4 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC5 (DMA_TypeDef *DMAx)
Clear Channel 5 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC6 (DMA_TypeDef *DMAx)
Clear Channel 6 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC7 (DMA_TypeDef *DMAx)
Clear Channel 7 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT1 (DMA_TypeDef *DMAx)
Clear Channel 1 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT2 (DMA_TypeDef *DMAx)
Clear Channel 2 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT3 (DMA_TypeDef *DMAx)
Clear Channel 3 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT4 (DMA_TypeDef *DMAx)
Clear Channel 4 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT5 (DMA_TypeDef *DMAx)
Clear Channel 5 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT6 (DMA_TypeDef *DMAx)
Clear Channel 6 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT7 (DMA_TypeDef *DMAx)
Clear Channel 7 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE1 (DMA_TypeDef *DMAx)
Clear Channel 1 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE2 (DMA_TypeDef *DMAx)
Clear Channel 2 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE3 (DMA_TypeDef *DMAx)
Clear Channel 3 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE4 (DMA_TypeDef *DMAx)
Clear Channel 4 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE5 (DMA_TypeDef *DMAx)
Clear Channel 5 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE6 (DMA_TypeDef *DMAx)
Clear Channel 6 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE7 (DMA_TypeDef *DMAx)
Clear Channel 7 transfer error flag.
__STATIC_INLINE void | LL_DMA_EnableIT_TC (DMA_TypeDef *DMAx, uint32_t Channel)
Enable Transfer complete interrupt.
__STATIC_INLINE void | LL_DMA_EnableIT_HT (DMA_TypeDef *DMAx, uint32_t Channel)
Enable Half transfer interrupt.
__STATIC_INLINE void | LL_DMA_EnableIT_TE (DMA_TypeDef *DMAx, uint32_t Channel)
Enable Transfer error interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_TC (DMA_TypeDef *DMAx, uint32_t Channel)
Disable Transfer complete interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_HT (DMA_TypeDef *DMAx, uint32_t Channel)
Disable Half transfer interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_TE (DMA_TypeDef *DMAx, uint32_t Channel)
Disable Transfer error interrupt.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_TC (DMA_TypeDef *DMAx, uint32_t Channel)
Check if Transfer complete Interrupt is enabled.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_HT (DMA_TypeDef *DMAx, uint32_t Channel)
Check if Half transfer Interrupt is enabled.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_TE (DMA_TypeDef *DMAx, uint32_t Channel)
Check if Transfer error Interrupt is enabled.
ErrorStatus | LL_DMA_Init (DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
ErrorStatus | LL_DMA_DeInit (DMA_TypeDef *DMAx, uint32_t Channel)
De-initialize the DMA registers to their default reset values.
void | LL_DMA_StructInit (LL_DMA_InitTypeDef *DMA_InitStruct)
Set each LL_DMA_InitTypeDef field to default value.

Detailed Description

Header file of DMA LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_dma.h.

Generated on Fri Sep 6 2019 11:34:39 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_dmamux.h File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32WBxx_HAL_Driver
  • Inc
Defines | Functions
stm32wbxx_ll_dmamux.h File Reference

Header file of DMAMUX LL module. More...

#include "stm32wbxx.h"

Go to the source code of this file.

Defines

#define | DMAMUX_CCR_SIZE 0x00000004UL
#define | DMAMUX_RGCR_SIZE 0x00000004UL
#define | LL_DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0
#define | LL_DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1
#define | LL_DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2
#define | LL_DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3
#define | LL_DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4
#define | LL_DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5
#define | LL_DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6
#define | LL_DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7
#define | LL_DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8
#define | LL_DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9
#define | LL_DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10
#define | LL_DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11
#define | LL_DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12
#define | LL_DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13
#define | LL_DMAMUX_RGCFR_RGCOF0 DMAMUX_RGCFR_COF0
#define | LL_DMAMUX_RGCFR_RGCOF1 DMAMUX_RGCFR_COF1
#define | LL_DMAMUX_RGCFR_RGCOF2 DMAMUX_RGCFR_COF2
#define | LL_DMAMUX_RGCFR_RGCOF3 DMAMUX_RGCFR_COF3
#define | LL_DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0
#define | LL_DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1
#define | LL_DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2
#define | LL_DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3
#define | LL_DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4
#define | LL_DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5
#define | LL_DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6
#define | LL_DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7
#define | LL_DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8
#define | LL_DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9
#define | LL_DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10
#define | LL_DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11
#define | LL_DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12
#define | LL_DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13
#define | LL_DMAMUX_RGSR_RGOF0 DMAMUX_RGSR_OF0
#define | LL_DMAMUX_RGSR_RGOF1 DMAMUX_RGSR_OF1
#define | LL_DMAMUX_RGSR_RGOF2 DMAMUX_RGSR_OF2
#define | LL_DMAMUX_RGSR_RGOF3 DMAMUX_RGSR_OF3
#define | LL_DMAMUX_CCR_SOIE DMAMUX_CxCR_SOIE
#define | LL_DMAMUX_RGCR_RGOIE DMAMUX_RGxCR_OIE
#define | LL_DMAMUX_REQ_MEM2MEM 0x00000000U
#define | LL_DMAMUX_REQ_GENERATOR0 0x00000001U
#define | LL_DMAMUX_REQ_GENERATOR1 0x00000002U
#define | LL_DMAMUX_REQ_GENERATOR2 0x00000003U
#define | LL_DMAMUX_REQ_GENERATOR3 0x00000004U
#define | LL_DMAMUX_REQ_ADC1 0x00000005U
#define | LL_DMAMUX_REQ_SPI1_RX 0x00000006U
#define | LL_DMAMUX_REQ_SPI1_TX 0x00000007U
#define | LL_DMAMUX_REQ_SPI2_RX 0x00000008U
#define | LL_DMAMUX_REQ_SPI2_TX 0x00000009U
#define | LL_DMAMUX_REQ_I2C1_RX 0x0000000AU
#define | LL_DMAMUX_REQ_I2C1_TX 0x0000000BU
#define | LL_DMAMUX_REQ_I2C3_RX 0x0000000CU
#define | LL_DMAMUX_REQ_I2C3_TX 0x0000000DU
#define | LL_DMAMUX_REQ_USART1_RX 0x0000000EU
#define | LL_DMAMUX_REQ_USART1_TX 0x0000000FU
#define | LL_DMAMUX_REQ_LPUART1_RX 0x00000010U
#define | LL_DMAMUX_REQ_LPUART1_TX 0x00000011U
#define | LL_DMAMUX_REQ_SAI1_A 0x00000012U
#define | LL_DMAMUX_REQ_SAI1_B 0x00000013U
#define | LL_DMAMUX_REQ_QUADSPI 0x00000014U
#define | LL_DMAMUX_REQ_TIM1_CH1 0x00000015U
#define | LL_DMAMUX_REQ_TIM1_CH2 0x00000016U
#define | LL_DMAMUX_REQ_TIM1_CH3 0x00000017U
#define | LL_DMAMUX_REQ_TIM1_CH4 0x00000018U
#define | LL_DMAMUX_REQ_TIM1_UP 0x00000019U
#define | LL_DMAMUX_REQ_TIM1_TRIG 0x0000001AU
#define | LL_DMAMUX_REQ_TIM1_COM 0x0000001BU
#define | LL_DMAMUX_REQ_TIM2_CH1 0x0000001CU
#define | LL_DMAMUX_REQ_TIM2_CH2 0x0000001DU
#define | LL_DMAMUX_REQ_TIM2_CH3 0x0000001EU
#define | LL_DMAMUX_REQ_TIM2_CH4 0x0000001FU
#define | LL_DMAMUX_REQ_TIM2_UP 0x00000020U
#define | LL_DMAMUX_REQ_TIM16_CH1 0x00000021U
#define | LL_DMAMUX_REQ_TIM16_UP 0x00000022U
#define | LL_DMAMUX_REQ_TIM17_CH1 0x00000023U
#define | LL_DMAMUX_REQ_TIM17_UP 0x00000024U
#define | LL_DMAMUX_REQ_AES1_IN 0x00000025U
#define | LL_DMAMUX_REQ_AES1_OUT 0x00000026U
#define | LL_DMAMUX_REQ_AES2_IN 0x00000027U
#define | LL_DMAMUX_REQ_AES2_OUT 0x00000028U
#define | LL_DMAMUX_CHANNEL_0 0x00000000U
#define | LL_DMAMUX_CHANNEL_1 0x00000001U
#define | LL_DMAMUX_CHANNEL_2 0x00000002U
#define | LL_DMAMUX_CHANNEL_3 0x00000003U
#define | LL_DMAMUX_CHANNEL_4 0x00000004U
#define | LL_DMAMUX_CHANNEL_5 0x00000005U
#define | LL_DMAMUX_CHANNEL_6 0x00000006U
#define | LL_DMAMUX_CHANNEL_7 0x00000007U
#define | LL_DMAMUX_CHANNEL_8 0x00000008U
#define | LL_DMAMUX_CHANNEL_9 0x00000009U
#define | LL_DMAMUX_CHANNEL_10 0x0000000AU
#define | LL_DMAMUX_CHANNEL_11 0x0000000BU
#define | LL_DMAMUX_CHANNEL_12 0x0000000CU
#define | LL_DMAMUX_CHANNEL_13 0x0000000DU
#define | LL_DMAMUX_SYNC_NO_EVENT 0x00000000U
#define | LL_DMAMUX_SYNC_POL_RISING DMAMUX_CxCR_SPOL_0
#define | LL_DMAMUX_SYNC_POL_FALLING DMAMUX_CxCR_SPOL_1
#define | LL_DMAMUX_SYNC_POL_RISING_FALLING (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1)
#define | LL_DMAMUX_SYNC_EXTI_LINE0 0x00000000U
#define | LL_DMAMUX_SYNC_EXTI_LINE1 DMAMUX_CxCR_SYNC_ID_0
#define | LL_DMAMUX_SYNC_EXTI_LINE2 DMAMUX_CxCR_SYNC_ID_1
#define | LL_DMAMUX_SYNC_EXTI_LINE3 (DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_EXTI_LINE4 DMAMUX_CxCR_SYNC_ID_2
#define | LL_DMAMUX_SYNC_EXTI_LINE5 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_EXTI_LINE6 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1)
#define | LL_DMAMUX_SYNC_EXTI_LINE7 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_EXTI_LINE8 DMAMUX_CxCR_SYNC_ID_3
#define | LL_DMAMUX_SYNC_EXTI_LINE9 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_EXTI_LINE10 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1)
#define | LL_DMAMUX_SYNC_EXTI_LINE11 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_EXTI_LINE12 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2)
#define | LL_DMAMUX_SYNC_EXTI_LINE13 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_EXTI_LINE14 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1)
#define | LL_DMAMUX_SYNC_EXTI_LINE15 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_DMAMUX_CH0 DMAMUX_CxCR_SYNC_ID_4
#define | LL_DMAMUX_SYNC_DMAMUX_CH1 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_SYNC_LPTIM1_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1)
#define | LL_DMAMUX_SYNC_LPTIM2_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)
#define | LL_DMAMUX_REQ_GEN_0 0x00000000U
#define | LL_DMAMUX_REQ_GEN_1 0x00000001U
#define | LL_DMAMUX_REQ_GEN_2 0x00000002U
#define | LL_DMAMUX_REQ_GEN_3 0x00000003U
#define | LL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U
#define | LL_DMAMUX_REQ_GEN_POL_RISING DMAMUX_RGxCR_GPOL_0
#define | LL_DMAMUX_REQ_GEN_POL_FALLING DMAMUX_RGxCR_GPOL_1
#define | LL_DMAMUX_REQ_GEN_POL_RISING_FALLING (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE0 0x00000000U
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE1 DMAMUX_RGxCR_SIG_ID_0
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE2 DMAMUX_RGxCR_SIG_ID_1
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE3 (DMAMUX_RGxCR_SIG_ID_1 |DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE4 DMAMUX_RGxCR_SIG_ID_2
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE5 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE6 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE7 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE8 DMAMUX_RGxCR_SIG_ID_3
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE9 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE10 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE11 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE12 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE13 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE14 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1)
#define | LL_DMAMUX_REQ_GEN_EXTI_LINE15 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_DMAMUX_CH0 DMAMUX_RGxCR_SIG_ID_4
#define | LL_DMAMUX_REQ_GEN_DMAMUX_CH1 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_REQ_GEN_LPTIM1_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1)
#define | LL_DMAMUX_REQ_GEN_LPTIM2_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)
#define | LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in DMAMUX register.
#define | LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in DMAMUX register.

Functions

__STATIC_INLINE void | LL_DMAMUX_SetRequestID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request)
Set DMAMUX request ID for DMAMUX Channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetRequestID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Get DMAMUX request ID for DMAMUX Channel x.
__STATIC_INLINE void | LL_DMAMUX_SetSyncRequestNb (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb)
Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetSyncRequestNb (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
__STATIC_INLINE void | LL_DMAMUX_SetSyncPolarity (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity)
Set the polarity of the signal on which the DMA request is synchronized.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetSyncPolarity (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Get the polarity of the signal on which the DMA request is synchronized.
__STATIC_INLINE void | LL_DMAMUX_EnableEventGeneration (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Enable the Event Generation on DMAMUX channel x.
__STATIC_INLINE void | LL_DMAMUX_DisableEventGeneration (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Disable the Event Generation on DMAMUX channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledEventGeneration (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Check if the Event Generation on DMAMUX channel x is enabled or disabled.
__STATIC_INLINE void | LL_DMAMUX_EnableSync (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Enable the synchronization mode.
__STATIC_INLINE void | LL_DMAMUX_DisableSync (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Disable the synchronization mode.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledSync (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Check if the synchronization mode is enabled or disabled.
__STATIC_INLINE void | LL_DMAMUX_SetSyncID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID)
Set DMAMUX synchronization ID on DMAMUX Channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetSyncID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Get DMAMUX synchronization ID on DMAMUX Channel x.
__STATIC_INLINE void | LL_DMAMUX_EnableRequestGen (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Enable the Request Generator.
__STATIC_INLINE void | LL_DMAMUX_DisableRequestGen (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Disable the Request Generator.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledRequestGen (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Check if the Request Generator is enabled or disabled.
__STATIC_INLINE void | LL_DMAMUX_SetRequestGenPolarity (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity)
Set the polarity of the signal on which the DMA request is generated.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetRequestGenPolarity (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Get the polarity of the signal on which the DMA request is generated.
__STATIC_INLINE void | LL_DMAMUX_SetGenRequestNb (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb)
Set the number of DMA request that will be autorized after a generation event.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetGenRequestNb (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Get the number of DMA request that will be autorized after a generation event.
__STATIC_INLINE void | LL_DMAMUX_SetRequestSignalID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID)
Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_GetRequestSignalID (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Get DMAMUX external Request Signal ID set on DMAMUX Channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO0 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 0.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO1 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 1.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO2 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 2.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO3 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 3.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO4 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 4.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO5 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 5.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO6 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 6.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO7 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 7.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO8 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 8.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO9 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 9.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO10 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 10.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO11 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 11.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO12 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 12.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_SO13 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Synchronization Event Overrun Flag Channel 13.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO0 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 0 Trigger Event Overrun Flag.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO1 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 1 Trigger Event Overrun Flag.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO2 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 2 Trigger Event Overrun Flag.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsActiveFlag_RGO3 (DMAMUX_Channel_TypeDef *DMAMUXx)
Get Request Generator 3 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO0 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 0.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO1 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 1.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO2 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 2.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO3 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 3.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO4 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 4.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO5 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 5.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO6 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 6.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO7 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 7.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO8 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 8.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO9 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 9.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO10 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 10.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO11 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 11.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO12 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 12.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_SO13 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Synchronization Event Overrun Flag Channel 13.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO0 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 0 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO1 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 1 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO2 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 2 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_ClearFlag_RGO3 (DMAMUX_Channel_TypeDef *DMAMUXx)
Clear Request Generator 3 Trigger Event Overrun Flag.
__STATIC_INLINE void | LL_DMAMUX_EnableIT_SO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
__STATIC_INLINE void | LL_DMAMUX_DisableIT_SO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledIT_SO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
__STATIC_INLINE void | LL_DMAMUX_EnableIT_RGO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
__STATIC_INLINE void | LL_DMAMUX_DisableIT_RGO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
__STATIC_INLINE uint32_t | LL_DMAMUX_IsEnabledIT_RGO (DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.

Detailed Description

Header file of DMAMUX LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_dmamux.h.

Generated on Fri Sep 6 2019 11:34:39 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_exti.h File Reference

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Data Structures | Defines | Functions
stm32wbxx_ll_exti.h File Reference

Header file of EXTI LL module. More...

#include "stm32wbxx.h"

Go to the source code of this file.

Data Structures

struct | LL_EXTI_InitTypeDef

Defines

#define | LL_EXTI_LINE_0 EXTI_IMR1_IM0
#define | LL_EXTI_LINE_1 EXTI_IMR1_IM1
#define | LL_EXTI_LINE_2 EXTI_IMR1_IM2
#define | LL_EXTI_LINE_3 EXTI_IMR1_IM3
#define | LL_EXTI_LINE_4 EXTI_IMR1_IM4
#define | LL_EXTI_LINE_5 EXTI_IMR1_IM5
#define | LL_EXTI_LINE_6 EXTI_IMR1_IM6
#define | LL_EXTI_LINE_7 EXTI_IMR1_IM7
#define | LL_EXTI_LINE_8 EXTI_IMR1_IM8
#define | LL_EXTI_LINE_9 EXTI_IMR1_IM9
#define | LL_EXTI_LINE_10 EXTI_IMR1_IM10
#define | LL_EXTI_LINE_11 EXTI_IMR1_IM11
#define | LL_EXTI_LINE_12 EXTI_IMR1_IM12
#define | LL_EXTI_LINE_13 EXTI_IMR1_IM13
#define | LL_EXTI_LINE_14 EXTI_IMR1_IM14
#define | LL_EXTI_LINE_15 EXTI_IMR1_IM15
#define | LL_EXTI_LINE_16 EXTI_IMR1_IM16
#define | LL_EXTI_LINE_17 EXTI_IMR1_IM17
#define | LL_EXTI_LINE_18 EXTI_IMR1_IM18
#define | LL_EXTI_LINE_19 EXTI_IMR1_IM19
#define | LL_EXTI_LINE_20 EXTI_IMR1_IM20
#define | LL_EXTI_LINE_21 EXTI_IMR1_IM21
#define | LL_EXTI_LINE_22 EXTI_IMR1_IM22
#define | LL_EXTI_LINE_23 EXTI_IMR1_IM23
#define | LL_EXTI_LINE_24 EXTI_IMR1_IM24
#define | LL_EXTI_LINE_25 EXTI_IMR1_IM25
#define | LL_EXTI_LINE_28 EXTI_IMR1_IM28
#define | LL_EXTI_LINE_29 EXTI_IMR1_IM29
#define | LL_EXTI_LINE_30 EXTI_IMR1_IM30
#define | LL_EXTI_LINE_31 EXTI_IMR1_IM31
#define | LL_EXTI_LINE_ALL_0_31
#define | LL_EXTI_LINE_33 EXTI_IMR2_IM33
#define | LL_EXTI_LINE_36 EXTI_IMR2_IM36
#define | LL_EXTI_LINE_37 EXTI_IMR2_IM37
#define | LL_EXTI_LINE_38 EXTI_IMR2_IM38
#define | LL_EXTI_LINE_39 EXTI_IMR2_IM39
#define | LL_EXTI_LINE_40 EXTI_IMR2_IM40
#define | LL_EXTI_LINE_41 EXTI_IMR2_IM41
#define | LL_EXTI_LINE_42 EXTI_IMR2_IM42
#define | LL_EXTI_LINE_43 EXTI_IMR2_IM43
#define | LL_EXTI_LINE_44 EXTI_IMR2_IM44
#define | LL_EXTI_LINE_45 EXTI_IMR2_IM45
#define | LL_EXTI_LINE_46 EXTI_IMR2_IM46
#define | LL_EXTI_LINE_48 EXTI_IMR2_IM48
#define | LL_EXTI_LINE_ALL_32_63
#define | LL_EXTI_LINE_ALL (0xFFFFFFFFU)
#define | LL_EXTI_LINE_NONE (0x00000000U)
#define | LL_EXTI_MODE_IT ((uint8_t)0x00U)
#define | LL_EXTI_MODE_EVENT ((uint8_t)0x01U)
#define | LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U)
#define | LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U)
#define | LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U)
#define | LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U)
#define | LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U)
#define | LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
Write a value in EXTI register.
#define | LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
Read a value in EXTI register.

Functions

__STATIC_INLINE void | LL_EXTI_EnableIT_0_31 (uint32_t ExtiLine)
Enable ExtiLine Interrupt request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_C2_EXTI_EnableIT_0_31 (uint32_t ExtiLine)
Enable ExtiLine Interrupt request for Lines in range 0 to 31 for cpu2.
__STATIC_INLINE void | LL_EXTI_EnableIT_32_63 (uint32_t ExtiLine)
Enable ExtiLine Interrupt request for Lines in range 32 to 63.
__STATIC_INLINE void | LL_C2_EXTI_EnableIT_32_63 (uint32_t ExtiLine)
Enable ExtiLine Interrupt request for Lines in range 32 to 63 for cpu2.
__STATIC_INLINE void | LL_EXTI_DisableIT_0_31 (uint32_t ExtiLine)
Disable ExtiLine Interrupt request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_C2_EXTI_DisableIT_0_31 (uint32_t ExtiLine)
Disable ExtiLine Interrupt request for Lines in range 0 to 31 for cpu2.
__STATIC_INLINE void | LL_EXTI_DisableIT_32_63 (uint32_t ExtiLine)
Disable ExtiLine Interrupt request for Lines in range 32 to 63.
__STATIC_INLINE void | LL_C2_EXTI_DisableIT_32_63 (uint32_t ExtiLine)
Disable ExtiLine Interrupt request for Lines in range 32 to 63 for cpu2.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledIT_0_31 (uint32_t ExtiLine)
Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_C2_EXTI_IsEnabledIT_0_31 (uint32_t ExtiLine)
Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 for cpu2.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledIT_32_63 (uint32_t ExtiLine)
Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_C2_EXTI_IsEnabledIT_32_63 (uint32_t ExtiLine)
Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63 for cpu2.
__STATIC_INLINE void | LL_EXTI_EnableEvent_0_31 (uint32_t ExtiLine)
Enable ExtiLine Event request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_C2_EXTI_EnableEvent_0_31 (uint32_t ExtiLine)
Enable ExtiLine Event request for Lines in range 0 to 31 for cpu2.
__STATIC_INLINE void | LL_EXTI_EnableEvent_32_63 (uint32_t ExtiLine)
Enable ExtiLine Event request for Lines in range 32 to 63.
__STATIC_INLINE void | LL_C2_EXTI_EnableEvent_32_63 (uint32_t ExtiLine)
Enable ExtiLine Event request for Lines in range 32 to 63 for cpu2.
__STATIC_INLINE void | LL_EXTI_DisableEvent_0_31 (uint32_t ExtiLine)
Disable ExtiLine Event request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_C2_EXTI_DisableEvent_0_31 (uint32_t ExtiLine)
Disable ExtiLine Event request for Lines in range 0 to 31 for cpu2.
__STATIC_INLINE void | LL_EXTI_DisableEvent_32_63 (uint32_t ExtiLine)
Disable ExtiLine Event request for Lines in range 32 to 63.
__STATIC_INLINE void | LL_C2_EXTI_DisableEvent_32_63 (uint32_t ExtiLine)
Disable ExtiLine Event request for Lines in range 32 to 63 for cpu2.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledEvent_0_31 (uint32_t ExtiLine)
Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_C2_EXTI_IsEnabledEvent_0_31 (uint32_t ExtiLine)
Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 for cpu2.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledEvent_32_63 (uint32_t ExtiLine)
Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_C2_EXTI_IsEnabledEvent_32_63 (uint32_t ExtiLine)
Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63 for cpu2.
__STATIC_INLINE void | LL_EXTI_EnableRisingTrig_0_31 (uint32_t ExtiLine)
Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableRisingTrig_32_63 (uint32_t ExtiLine)
Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_DisableRisingTrig_0_31 (uint32_t ExtiLine)
Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableRisingTrig_32_63 (uint32_t ExtiLine)
Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledRisingTrig_0_31 (uint32_t ExtiLine)
Check if rising edge trigger is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledRisingTrig_32_63 (uint32_t ExtiLine)
Check if rising edge trigger is enabled for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_EnableFallingTrig_0_31 (uint32_t ExtiLine)
Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableFallingTrig_32_63 (uint32_t ExtiLine)
Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_DisableFallingTrig_0_31 (uint32_t ExtiLine)
Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableFallingTrig_32_63 (uint32_t ExtiLine)
Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledFallingTrig_0_31 (uint32_t ExtiLine)
Check if falling edge trigger is enabled for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledFallingTrig_32_63 (uint32_t ExtiLine)
Check if falling edge trigger is enabled for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_GenerateSWI_0_31 (uint32_t ExtiLine)
Generate a software Interrupt Event for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_GenerateSWI_32_63 (uint32_t ExtiLine)
Generate a software Interrupt Event for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_IsActiveFlag_0_31 (uint32_t ExtiLine)
Check if the ExtLine Flag is set or not for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsActiveFlag_32_63 (uint32_t ExtiLine)
Check if the ExtLine Flag is set or not for Lines in range 32 to 63.
__STATIC_INLINE uint32_t | LL_EXTI_ReadFlag_0_31 (uint32_t ExtiLine)
Read ExtLine Combination Flag for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_ReadFlag_32_63 (uint32_t ExtiLine)
Read ExtLine Combination Flag for Lines in range 32 to 63.
__STATIC_INLINE void | LL_EXTI_ClearFlag_0_31 (uint32_t ExtiLine)
Clear ExtLine Flags for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_ClearFlag_32_63 (uint32_t ExtiLine)
Clear ExtLine Flags for Lines in range 32 to 63.
ErrorStatus | LL_EXTI_Init (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
ErrorStatus | LL_EXTI_DeInit (void)
De-initialize the EXTI registers to their default reset values.
void | LL_EXTI_StructInit (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Set each LL_EXTI_InitTypeDef field to default value.

Detailed Description

Header file of EXTI LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_exti.h.

Generated on Fri Sep 6 2019 11:34:39 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_gpio.h File Reference

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Data Structures | Defines | Functions
stm32wbxx_ll_gpio.h File Reference

Header file of GPIO LL module. More...

#include "stm32wbxx.h"

Go to the source code of this file.

Data Structures

struct | LL_GPIO_InitTypeDef
LL GPIO Init Structure definition. More...

Defines

#define | LL_GPIO_PIN_0 GPIO_BSRR_BS0
#define | LL_GPIO_PIN_1 GPIO_BSRR_BS1
#define | LL_GPIO_PIN_2 GPIO_BSRR_BS2
#define | LL_GPIO_PIN_3 GPIO_BSRR_BS3
#define | LL_GPIO_PIN_4 GPIO_BSRR_BS4
#define | LL_GPIO_PIN_5 GPIO_BSRR_BS5
#define | LL_GPIO_PIN_6 GPIO_BSRR_BS6
#define | LL_GPIO_PIN_7 GPIO_BSRR_BS7
#define | LL_GPIO_PIN_8 GPIO_BSRR_BS8
#define | LL_GPIO_PIN_9 GPIO_BSRR_BS9
#define | LL_GPIO_PIN_10 GPIO_BSRR_BS10
#define | LL_GPIO_PIN_11 GPIO_BSRR_BS11
#define | LL_GPIO_PIN_12 GPIO_BSRR_BS12
#define | LL_GPIO_PIN_13 GPIO_BSRR_BS13
#define | LL_GPIO_PIN_14 GPIO_BSRR_BS14
#define | LL_GPIO_PIN_15 GPIO_BSRR_BS15
#define | LL_GPIO_PIN_ALL
#define | LL_GPIO_MODE_INPUT (0x00000000U)
#define | LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0
#define | LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1
#define | LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0
#define | LL_GPIO_OUTPUT_PUSHPULL (0x00000000U)
#define | LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT0
#define | LL_GPIO_SPEED_FREQ_LOW (0x00000000U)
#define | LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEED0_0
#define | LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEED0_1
#define | LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDR_OSPEED0
#define | LL_GPIO_PULL_NO (0x00000000U)
#define | LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0
#define | LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1
#define | LL_GPIO_AF_0 (0x0000000U)
#define | LL_GPIO_AF_1 (0x0000001U)
#define | LL_GPIO_AF_2 (0x0000002U)
#define | LL_GPIO_AF_3 (0x0000003U)
#define | LL_GPIO_AF_4 (0x0000004U)
#define | LL_GPIO_AF_5 (0x0000005U)
#define | LL_GPIO_AF_6 (0x0000006U)
#define | LL_GPIO_AF_7 (0x0000007U)
#define | LL_GPIO_AF_8 (0x0000008U)
#define | LL_GPIO_AF_9 (0x0000009U)
#define | LL_GPIO_AF_10 (0x000000AU)
#define | LL_GPIO_AF_11 (0x000000BU)
#define | LL_GPIO_AF_12 (0x000000CU)
#define | LL_GPIO_AF_13 (0x000000DU)
#define | LL_GPIO_AF_14 (0x000000EU)
#define | LL_GPIO_AF_15 (0x000000FU)
#define | LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in GPIO register.
#define | LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in GPIO register.

Functions

__STATIC_INLINE void | LL_GPIO_SetPinMode (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
Configure gpio mode for a dedicated pin on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinMode (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio mode for a dedicated pin on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinOutputType (GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
Configure gpio output type for several pins on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinOutputType (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio output type for several pins on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinSpeed (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
Configure gpio speed for a dedicated pin on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinSpeed (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio speed for a dedicated pin on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinPull (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinPull (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio pull-up or pull-down for a dedicated pin on a dedicated port.
__STATIC_INLINE void | LL_GPIO_SetAFPin_0_7 (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetAFPin_0_7 (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
__STATIC_INLINE void | LL_GPIO_SetAFPin_8_15 (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetAFPin_8_15 (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
__STATIC_INLINE void | LL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Lock configuration of several pins for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsPinLocked (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return 1 if all pins passed as parameter, of a dedicated port, are locked.
__STATIC_INLINE uint32_t | LL_GPIO_IsAnyPinLocked (GPIO_TypeDef *GPIOx)
Return 1 if one of the pin of a dedicated port is locked.
__STATIC_INLINE uint32_t | LL_GPIO_ReadInputPort (GPIO_TypeDef *GPIOx)
Return full input data register value for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsInputPinSet (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return if input data level for several pins of dedicated port is high or low.
__STATIC_INLINE void | LL_GPIO_WriteOutputPort (GPIO_TypeDef *GPIOx, uint32_t PortValue)
Write output data register for the port.
__STATIC_INLINE uint32_t | LL_GPIO_ReadOutputPort (GPIO_TypeDef *GPIOx)
Return full output data register value for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsOutputPinSet (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return if input data level for several pins of dedicated port is high or low.
__STATIC_INLINE void | LL_GPIO_SetOutputPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Set several pins to high level on dedicated gpio port.
__STATIC_INLINE void | LL_GPIO_ResetOutputPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Set several pins to low level on dedicated gpio port.
__STATIC_INLINE void | LL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Toggle data value for several pin of dedicated port.
ErrorStatus | LL_GPIO_DeInit (GPIO_TypeDef *GPIOx)
De-initialize GPIO registers (Registers restored to their default values).
ErrorStatus | LL_GPIO_Init (GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
void | LL_GPIO_StructInit (LL_GPIO_InitTypeDef *GPIO_InitStruct)
Set each LL_GPIO_InitTypeDef field to default value.

Detailed Description

Header file of GPIO LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_gpio.h.

Generated on Fri Sep 6 2019 11:34:39 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_hsem.h File Reference

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Defines | Functions
stm32wbxx_ll_hsem.h File Reference

Header file of HSEM LL module. More...

#include "stm32wbxx.h"

Go to the source code of this file.

Defines

#define | LL_HSEM_COREID_NONE 0U
#define | LL_HSEM_COREID_CPU1 HSEM_CR_COREID_CPU1
#define | LL_HSEM_COREID_CPU2 HSEM_CR_COREID_CPU2
#define | LL_HSEM_COREID HSEM_CR_COREID_CURRENT
#define | LL_HSEM_SEMAPHORE_0 HSEM_C1IER_ISE0
#define | LL_HSEM_SEMAPHORE_1 HSEM_C1IER_ISE1
#define | LL_HSEM_SEMAPHORE_2 HSEM_C1IER_ISE2
#define | LL_HSEM_SEMAPHORE_3 HSEM_C1IER_ISE3
#define | LL_HSEM_SEMAPHORE_4 HSEM_C1IER_ISE4
#define | LL_HSEM_SEMAPHORE_5 HSEM_C1IER_ISE5
#define | LL_HSEM_SEMAPHORE_6 HSEM_C1IER_ISE6
#define | LL_HSEM_SEMAPHORE_7 HSEM_C1IER_ISE7
#define | LL_HSEM_SEMAPHORE_8 HSEM_C1IER_ISE8
#define | LL_HSEM_SEMAPHORE_9 HSEM_C1IER_ISE9
#define | LL_HSEM_SEMAPHORE_10 HSEM_C1IER_ISE10
#define | LL_HSEM_SEMAPHORE_11 HSEM_C1IER_ISE11
#define | LL_HSEM_SEMAPHORE_12 HSEM_C1IER_ISE12
#define | LL_HSEM_SEMAPHORE_13 HSEM_C1IER_ISE13
#define | LL_HSEM_SEMAPHORE_14 HSEM_C1IER_ISE14
#define | LL_HSEM_SEMAPHORE_15 HSEM_C1IER_ISE15
#define | LL_HSEM_SEMAPHORE_16 HSEM_C1IER_ISE16
#define | LL_HSEM_SEMAPHORE_17 HSEM_C1IER_ISE17
#define | LL_HSEM_SEMAPHORE_18 HSEM_C1IER_ISE18
#define | LL_HSEM_SEMAPHORE_19 HSEM_C1IER_ISE19
#define | LL_HSEM_SEMAPHORE_20 HSEM_C1IER_ISE20
#define | LL_HSEM_SEMAPHORE_21 HSEM_C1IER_ISE21
#define | LL_HSEM_SEMAPHORE_22 HSEM_C1IER_ISE22
#define | LL_HSEM_SEMAPHORE_23 HSEM_C1IER_ISE23
#define | LL_HSEM_SEMAPHORE_24 HSEM_C1IER_ISE24
#define | LL_HSEM_SEMAPHORE_25 HSEM_C1IER_ISE25
#define | LL_HSEM_SEMAPHORE_26 HSEM_C1IER_ISE26
#define | LL_HSEM_SEMAPHORE_27 HSEM_C1IER_ISE27
#define | LL_HSEM_SEMAPHORE_28 HSEM_C1IER_ISE28
#define | LL_HSEM_SEMAPHORE_29 HSEM_C1IER_ISE29
#define | LL_HSEM_SEMAPHORE_30 HSEM_C1IER_ISE30
#define | LL_HSEM_SEMAPHORE_31 HSEM_C1IER_ISE31
#define | LL_HSEM_SEMAPHORE_ALL 0xFFFFFFFFU
#define | LL_HSEM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in HSEM register.
#define | LL_HSEM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in HSEM register.

Functions

__STATIC_INLINE uint32_t | LL_HSEM_IsSemaphoreLocked (HSEM_TypeDef *HSEMx, uint32_t Semaphore)
Return 1 if the semaphore is locked, else return 0.
__STATIC_INLINE uint32_t | LL_HSEM_GetCoreId (HSEM_TypeDef *HSEMx, uint32_t Semaphore)
Get core id.
__STATIC_INLINE uint32_t | LL_HSEM_GetProcessId (HSEM_TypeDef *HSEMx, uint32_t Semaphore)
Get process id.
__STATIC_INLINE void | LL_HSEM_SetLock (HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
Get the lock by writing in R register.
__STATIC_INLINE uint32_t | LL_HSEM_2StepLock (HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
Get the lock with 2-step lock.
__STATIC_INLINE uint32_t | LL_HSEM_1StepLock (HSEM_TypeDef *HSEMx, uint32_t Semaphore)
Get the lock with 1-step lock.
__STATIC_INLINE void | LL_HSEM_ReleaseLock (HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
Release the lock of the semaphore.
__STATIC_INLINE uint32_t | LL_HSEM_GetStatus (HSEM_TypeDef *HSEMx, uint32_t Semaphore)
Get the lock status of the semaphore.
__STATIC_INLINE void | LL_HSEM_SetKey (HSEM_TypeDef *HSEMx, uint32_t key)
Set the key.
__STATIC_INLINE uint32_t | LL_HSEM_GetKey (HSEM_TypeDef *HSEMx)
Get the key.
__STATIC_INLINE void | LL_HSEM_ResetAllLock (HSEM_TypeDef *HSEMx, uint32_t key, uint32_t core)
Release all semaphore with the same core id.
__STATIC_INLINE void | LL_HSEM_EnableIT_C1IER (HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
Enable interrupt.
__STATIC_INLINE void | LL_HSEM_DisableIT_C1IER (HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
Disable interrupt.
__STATIC_INLINE uint32_t | LL_HSEM_IsEnabledIT_C1IER (HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
Check if interrupt is enabled.
__STATIC_INLINE void | LL_HSEM_EnableIT_C2IER (HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
Enable interrupt.
__STATIC_INLINE void | LL_HSEM_DisableIT_C2IER (HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
Disable interrupt.
__STATIC_INLINE uint32_t | LL_HSEM_IsEnabledIT_C2IER (HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
Check if interrupt is enabled.
__STATIC_INLINE void | LL_HSEM_ClearFlag_C1ICR (HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
Clear interrupt status.
__STATIC_INLINE uint32_t | LL_HSEM_IsActiveFlag_C1ISR (HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
Get interrupt status from ISR register.
__STATIC_INLINE uint32_t | LL_HSEM_IsActiveFlag_C1MISR (HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
Get interrupt status from MISR register.
__STATIC_INLINE void | LL_HSEM_ClearFlag_C2ICR (HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
Clear interrupt status.
__STATIC_INLINE uint32_t | LL_HSEM_IsActiveFlag_C2ISR (HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
Get interrupt status from ISR register.
__STATIC_INLINE uint32_t | LL_HSEM_IsActiveFlag_C2MISR (HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
Get interrupt status from MISR register.

Detailed Description

Header file of HSEM LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_hsem.h.

Generated on Fri Sep 6 2019 11:34:39 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_i2c.h File Reference

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Data Structures | Defines | Functions
stm32wbxx_ll_i2c.h File Reference

Header file of I2C LL module. More...

#include "stm32wbxx.h"

Go to the source code of this file.

Data Structures

struct | LL_I2C_InitTypeDef

Defines

#define | LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF
#define | LL_I2C_ICR_NACKCF I2C_ICR_NACKCF
#define | LL_I2C_ICR_STOPCF I2C_ICR_STOPCF
#define | LL_I2C_ICR_BERRCF I2C_ICR_BERRCF
#define | LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF
#define | LL_I2C_ICR_OVRCF I2C_ICR_OVRCF
#define | LL_I2C_ICR_PECCF I2C_ICR_PECCF
#define | LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF
#define | LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF
#define | LL_I2C_ISR_TXE I2C_ISR_TXE
#define | LL_I2C_ISR_TXIS I2C_ISR_TXIS
#define | LL_I2C_ISR_RXNE I2C_ISR_RXNE
#define | LL_I2C_ISR_ADDR I2C_ISR_ADDR
#define | LL_I2C_ISR_NACKF I2C_ISR_NACKF
#define | LL_I2C_ISR_STOPF I2C_ISR_STOPF
#define | LL_I2C_ISR_TC I2C_ISR_TC
#define | LL_I2C_ISR_TCR I2C_ISR_TCR
#define | LL_I2C_ISR_BERR I2C_ISR_BERR
#define | LL_I2C_ISR_ARLO I2C_ISR_ARLO
#define | LL_I2C_ISR_OVR I2C_ISR_OVR
#define | LL_I2C_ISR_PECERR I2C_ISR_PECERR
#define | LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT
#define | LL_I2C_ISR_ALERT I2C_ISR_ALERT
#define | LL_I2C_ISR_BUSY I2C_ISR_BUSY
#define | LL_I2C_CR1_TXIE I2C_CR1_TXIE
#define | LL_I2C_CR1_RXIE I2C_CR1_RXIE
#define | LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE
#define | LL_I2C_CR1_NACKIE I2C_CR1_NACKIE
#define | LL_I2C_CR1_STOPIE I2C_CR1_STOPIE
#define | LL_I2C_CR1_TCIE I2C_CR1_TCIE
#define | LL_I2C_CR1_ERRIE I2C_CR1_ERRIE
#define | LL_I2C_MODE_I2C 0x00000000U
#define | LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN
#define | LL_I2C_MODE_SMBUS_DEVICE 0x00000000U
#define | LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN
#define | LL_I2C_ANALOGFILTER_ENABLE 0x00000000U
#define | LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
#define | LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U
#define | LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10
#define | LL_I2C_OWNADDRESS1_7BIT 0x00000000U
#define | LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE
#define | LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK
#define | LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01
#define | LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02
#define | LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03
#define | LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04
#define | LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05
#define | LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06
#define | LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07
#define | LL_I2C_ACK 0x00000000U
#define | LL_I2C_NACK I2C_CR2_NACK
#define | LL_I2C_ADDRSLAVE_7BIT 0x00000000U
#define | LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10
#define | LL_I2C_REQUEST_WRITE 0x00000000U
#define | LL_I2C_REQUEST_READ I2C_CR2_RD_WRN
#define | LL_I2C_MODE_RELOAD I2C_CR2_RELOAD
#define | LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND
#define | LL_I2C_MODE_SOFTEND 0x00000000U
#define | LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD
#define | LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND
#define | LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND
#define | LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)
#define | LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)
#define | LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U
#define | LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define | LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define | LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
#define | LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define | LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
#define | LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)
#define | LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
#define | LL_I2C_DIRECTION_WRITE 0x00000000U
#define | LL_I2C_DIRECTION_READ I2C_ISR_DIR
#define | LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U
#define | LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U
#define | LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U
#define | LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE
#define | LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN
#define | LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN
#define | LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)
#define | LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in I2C register.
#define | LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in I2C register.
#define | __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__)
Configure the SDA setup, hold time and the SCL high, low period.

Functions

__STATIC_INLINE void | LL_I2C_Enable (I2C_TypeDef *I2Cx)
Enable I2C peripheral (PE = 1).
__STATIC_INLINE void | LL_I2C_Disable (I2C_TypeDef *I2Cx)
Disable I2C peripheral (PE = 0).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabled (I2C_TypeDef *I2Cx)
Check if the I2C peripheral is enabled or disabled.
__STATIC_INLINE void | LL_I2C_ConfigFilters (I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
Configure Noise Filters (Analog and Digital).
__STATIC_INLINE void | LL_I2C_SetDigitalFilter (I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
Configure Digital Noise Filter.
__STATIC_INLINE uint32_t | LL_I2C_GetDigitalFilter (I2C_TypeDef *I2Cx)
Get the current Digital Noise Filter configuration.
__STATIC_INLINE void | LL_I2C_EnableAnalogFilter (I2C_TypeDef *I2Cx)
Enable Analog Noise Filter.
__STATIC_INLINE void | LL_I2C_DisableAnalogFilter (I2C_TypeDef *I2Cx)
Disable Analog Noise Filter.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledAnalogFilter (I2C_TypeDef *I2Cx)
Check if Analog Noise Filter is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableDMAReq_TX (I2C_TypeDef *I2Cx)
Enable DMA transmission requests.
__STATIC_INLINE void | LL_I2C_DisableDMAReq_TX (I2C_TypeDef *I2Cx)
Disable DMA transmission requests.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledDMAReq_TX (I2C_TypeDef *I2Cx)
Check if DMA transmission requests are enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableDMAReq_RX (I2C_TypeDef *I2Cx)
Enable DMA reception requests.
__STATIC_INLINE void | LL_I2C_DisableDMAReq_RX (I2C_TypeDef *I2Cx)
Disable DMA reception requests.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledDMAReq_RX (I2C_TypeDef *I2Cx)
Check if DMA reception requests are enabled or disabled.
__STATIC_INLINE uint32_t | LL_I2C_DMA_GetRegAddr (I2C_TypeDef *I2Cx, uint32_t Direction)
Get the data register address used for DMA transfer.
__STATIC_INLINE void | LL_I2C_EnableClockStretching (I2C_TypeDef *I2Cx)
Enable Clock stretching.
__STATIC_INLINE void | LL_I2C_DisableClockStretching (I2C_TypeDef *I2Cx)
Disable Clock stretching.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledClockStretching (I2C_TypeDef *I2Cx)
Check if Clock stretching is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableSlaveByteControl (I2C_TypeDef *I2Cx)
Enable hardware byte control in slave mode.
__STATIC_INLINE void | LL_I2C_DisableSlaveByteControl (I2C_TypeDef *I2Cx)
Disable hardware byte control in slave mode.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSlaveByteControl (I2C_TypeDef *I2Cx)
Check if hardware byte control in slave mode is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableWakeUpFromStop (I2C_TypeDef *I2Cx)
Enable Wakeup from STOP.
__STATIC_INLINE void | LL_I2C_DisableWakeUpFromStop (I2C_TypeDef *I2Cx)
Disable Wakeup from STOP.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledWakeUpFromStop (I2C_TypeDef *I2Cx)
Check if Wakeup from STOP is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableGeneralCall (I2C_TypeDef *I2Cx)
Enable General Call.
__STATIC_INLINE void | LL_I2C_DisableGeneralCall (I2C_TypeDef *I2Cx)
Disable General Call.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledGeneralCall (I2C_TypeDef *I2Cx)
Check if General Call is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetMasterAddressingMode (I2C_TypeDef *I2Cx, uint32_t AddressingMode)
Configure the Master to operate in 7-bit or 10-bit addressing mode.
__STATIC_INLINE uint32_t | LL_I2C_GetMasterAddressingMode (I2C_TypeDef *I2Cx)
Get the Master addressing mode.
__STATIC_INLINE void | LL_I2C_SetOwnAddress1 (I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
Set the Own Address1.
__STATIC_INLINE void | LL_I2C_EnableOwnAddress1 (I2C_TypeDef *I2Cx)
Enable acknowledge on Own Address1 match address.
__STATIC_INLINE void | LL_I2C_DisableOwnAddress1 (I2C_TypeDef *I2Cx)
Disable acknowledge on Own Address1 match address.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledOwnAddress1 (I2C_TypeDef *I2Cx)
Check if Own Address1 acknowledge is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetOwnAddress2 (I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
Set the 7bits Own Address2.
__STATIC_INLINE void | LL_I2C_EnableOwnAddress2 (I2C_TypeDef *I2Cx)
Enable acknowledge on Own Address2 match address.
__STATIC_INLINE void | LL_I2C_DisableOwnAddress2 (I2C_TypeDef *I2Cx)
Disable acknowledge on Own Address2 match address.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledOwnAddress2 (I2C_TypeDef *I2Cx)
Check if Own Address1 acknowledge is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetTiming (I2C_TypeDef *I2Cx, uint32_t Timing)
Configure the SDA setup, hold time and the SCL high, low period.
__STATIC_INLINE uint32_t | LL_I2C_GetTimingPrescaler (I2C_TypeDef *I2Cx)
Get the Timing Prescaler setting.
__STATIC_INLINE uint32_t | LL_I2C_GetClockLowPeriod (I2C_TypeDef *I2Cx)
Get the SCL low period setting.
__STATIC_INLINE uint32_t | LL_I2C_GetClockHighPeriod (I2C_TypeDef *I2Cx)
Get the SCL high period setting.
__STATIC_INLINE uint32_t | LL_I2C_GetDataHoldTime (I2C_TypeDef *I2Cx)
Get the SDA hold time.
__STATIC_INLINE uint32_t | LL_I2C_GetDataSetupTime (I2C_TypeDef *I2Cx)
Get the SDA setup time.
__STATIC_INLINE void | LL_I2C_SetMode (I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
Configure peripheral mode.
__STATIC_INLINE uint32_t | LL_I2C_GetMode (I2C_TypeDef *I2Cx)
Get peripheral mode.
__STATIC_INLINE void | LL_I2C_EnableSMBusAlert (I2C_TypeDef *I2Cx)
Enable SMBus alert (Host or Device mode)
__STATIC_INLINE void | LL_I2C_DisableSMBusAlert (I2C_TypeDef *I2Cx)
Disable SMBus alert (Host or Device mode)
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusAlert (I2C_TypeDef *I2Cx)
Check if SMBus alert (Host or Device mode) is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableSMBusPEC (I2C_TypeDef *I2Cx)
Enable SMBus Packet Error Calculation (PEC).
__STATIC_INLINE void | LL_I2C_DisableSMBusPEC (I2C_TypeDef *I2Cx)
Disable SMBus Packet Error Calculation (PEC).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusPEC (I2C_TypeDef *I2Cx)
Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
__STATIC_INLINE void | LL_I2C_ConfigSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode, uint32_t TimeoutB)
Configure the SMBus Clock Timeout.
__STATIC_INLINE void | LL_I2C_SetSMBusTimeoutA (I2C_TypeDef *I2Cx, uint32_t TimeoutA)
Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusTimeoutA (I2C_TypeDef *I2Cx)
Get the SMBus Clock TimeoutA setting.
__STATIC_INLINE void | LL_I2C_SetSMBusTimeoutAMode (I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
Set the SMBus Clock TimeoutA mode.
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusTimeoutAMode (I2C_TypeDef *I2Cx)
Get the SMBus Clock TimeoutA mode.
__STATIC_INLINE void | LL_I2C_SetSMBusTimeoutB (I2C_TypeDef *I2Cx, uint32_t TimeoutB)
Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusTimeoutB (I2C_TypeDef *I2Cx)
Get the SMBus Extented Cumulative Clock TimeoutB setting.
__STATIC_INLINE void | LL_I2C_EnableSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
Enable the SMBus Clock Timeout.
__STATIC_INLINE void | LL_I2C_DisableSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
Disable the SMBus Clock Timeout.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusTimeout (I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
Check if the SMBus Clock Timeout is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_TX (I2C_TypeDef *I2Cx)
Enable TXIS interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_TX (I2C_TypeDef *I2Cx)
Disable TXIS interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_TX (I2C_TypeDef *I2Cx)
Check if the TXIS Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_RX (I2C_TypeDef *I2Cx)
Enable RXNE interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_RX (I2C_TypeDef *I2Cx)
Disable RXNE interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_RX (I2C_TypeDef *I2Cx)
Check if the RXNE Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_ADDR (I2C_TypeDef *I2Cx)
Enable Address match interrupt (slave mode only).
__STATIC_INLINE void | LL_I2C_DisableIT_ADDR (I2C_TypeDef *I2Cx)
Disable Address match interrupt (slave mode only).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_ADDR (I2C_TypeDef *I2Cx)
Check if Address match interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_NACK (I2C_TypeDef *I2Cx)
Enable Not acknowledge received interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_NACK (I2C_TypeDef *I2Cx)
Disable Not acknowledge received interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_NACK (I2C_TypeDef *I2Cx)
Check if Not acknowledge received interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_STOP (I2C_TypeDef *I2Cx)
Enable STOP detection interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_STOP (I2C_TypeDef *I2Cx)
Disable STOP detection interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_STOP (I2C_TypeDef *I2Cx)
Check if STOP detection interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_TC (I2C_TypeDef *I2Cx)
Enable Transfer Complete interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_TC (I2C_TypeDef *I2Cx)
Disable Transfer Complete interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_TC (I2C_TypeDef *I2Cx)
Check if Transfer Complete interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_ERR (I2C_TypeDef *I2Cx)
Enable Error interrupts.
__STATIC_INLINE void | LL_I2C_DisableIT_ERR (I2C_TypeDef *I2Cx)
Disable Error interrupts.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_ERR (I2C_TypeDef *I2Cx)
Check if Error interrupts are enabled or disabled.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TXE (I2C_TypeDef *I2Cx)
Indicate the status of Transmit data register empty flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TXIS (I2C_TypeDef *I2Cx)
Indicate the status of Transmit interrupt flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_RXNE (I2C_TypeDef *I2Cx)
Indicate the status of Receive data register not empty flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_ADDR (I2C_TypeDef *I2Cx)
Indicate the status of Address matched flag (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_NACK (I2C_TypeDef *I2Cx)
Indicate the status of Not Acknowledge received flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_STOP (I2C_TypeDef *I2Cx)
Indicate the status of Stop detection flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TC (I2C_TypeDef *I2Cx)
Indicate the status of Transfer complete flag (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TCR (I2C_TypeDef *I2Cx)
Indicate the status of Transfer complete flag (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_BERR (I2C_TypeDef *I2Cx)
Indicate the status of Bus error flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_ARLO (I2C_TypeDef *I2Cx)
Indicate the status of Arbitration lost flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_OVR (I2C_TypeDef *I2Cx)
Indicate the status of Overrun/Underrun flag (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_PECERR (I2C_TypeDef *I2Cx)
Indicate the status of SMBus PEC error flag in reception.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_TIMEOUT (I2C_TypeDef *I2Cx)
Indicate the status of SMBus Timeout detection flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_ALERT (I2C_TypeDef *I2Cx)
Indicate the status of SMBus alert flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_BUSY (I2C_TypeDef *I2Cx)
Indicate the status of Bus Busy flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_ADDR (I2C_TypeDef *I2Cx)
Clear Address Matched flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_NACK (I2C_TypeDef *I2Cx)
Clear Not Acknowledge flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_STOP (I2C_TypeDef *I2Cx)
Clear Stop detection flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_TXE (I2C_TypeDef *I2Cx)
Clear Transmit data register empty flag (TXE).
__STATIC_INLINE void | LL_I2C_ClearFlag_BERR (I2C_TypeDef *I2Cx)
Clear Bus error flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_ARLO (I2C_TypeDef *I2Cx)
Clear Arbitration lost flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_OVR (I2C_TypeDef *I2Cx)
Clear Overrun/Underrun flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_PECERR (I2C_TypeDef *I2Cx)
Clear SMBus PEC error flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_TIMEOUT (I2C_TypeDef *I2Cx)
Clear SMBus Timeout detection flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_ALERT (I2C_TypeDef *I2Cx)
Clear SMBus Alert flag.
__STATIC_INLINE void | LL_I2C_EnableAutoEndMode (I2C_TypeDef *I2Cx)
Enable automatic STOP condition generation (master mode).
__STATIC_INLINE void | LL_I2C_DisableAutoEndMode (I2C_TypeDef *I2Cx)
Disable automatic STOP condition generation (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledAutoEndMode (I2C_TypeDef *I2Cx)
Check if automatic STOP condition is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableReloadMode (I2C_TypeDef *I2Cx)
Enable reload mode (master mode).
__STATIC_INLINE void | LL_I2C_DisableReloadMode (I2C_TypeDef *I2Cx)
Disable reload mode (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledReloadMode (I2C_TypeDef *I2Cx)
Check if reload mode is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetTransferSize (I2C_TypeDef *I2Cx, uint32_t TransferSize)
Configure the number of bytes for transfer.
__STATIC_INLINE uint32_t | LL_I2C_GetTransferSize (I2C_TypeDef *I2Cx)
Get the number of bytes configured for transfer.
__STATIC_INLINE void | LL_I2C_AcknowledgeNextData (I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
__STATIC_INLINE void | LL_I2C_GenerateStartCondition (I2C_TypeDef *I2Cx)
Generate a START or RESTART condition.
__STATIC_INLINE void | LL_I2C_GenerateStopCondition (I2C_TypeDef *I2Cx)
Generate a STOP condition after the current byte transfer (master mode).
__STATIC_INLINE void | LL_I2C_EnableAuto10BitRead (I2C_TypeDef *I2Cx)
Enable automatic RESTART Read request condition for 10bit address header (master mode).
__STATIC_INLINE void | LL_I2C_DisableAuto10BitRead (I2C_TypeDef *I2Cx)
Disable automatic RESTART Read request condition for 10bit address header (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledAuto10BitRead (I2C_TypeDef *I2Cx)
Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetTransferRequest (I2C_TypeDef *I2Cx, uint32_t TransferRequest)
Configure the transfer direction (master mode).
__STATIC_INLINE uint32_t | LL_I2C_GetTransferRequest (I2C_TypeDef *I2Cx)
Get the transfer direction requested (master mode).
__STATIC_INLINE void | LL_I2C_SetSlaveAddr (I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
Configure the slave address for transfer (master mode).
__STATIC_INLINE uint32_t | LL_I2C_GetSlaveAddr (I2C_TypeDef *I2Cx)
Get the slave address programmed for transfer.
__STATIC_INLINE void | LL_I2C_HandleTransfer (I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
__STATIC_INLINE uint32_t | LL_I2C_GetTransferDirection (I2C_TypeDef *I2Cx)
Indicate the value of transfer direction (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_GetAddressMatchCode (I2C_TypeDef *I2Cx)
Return the slave matched address.
__STATIC_INLINE void | LL_I2C_EnableSMBusPECCompare (I2C_TypeDef *I2Cx)
Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusPECCompare (I2C_TypeDef *I2Cx)
Check if the SMBus Packet Error byte internal comparison is requested or not.
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusPEC (I2C_TypeDef *I2Cx)
Get the SMBus Packet Error byte calculated.
__STATIC_INLINE uint8_t | LL_I2C_ReceiveData8 (I2C_TypeDef *I2Cx)
Read Receive Data register.
__STATIC_INLINE void | LL_I2C_TransmitData8 (I2C_TypeDef *I2Cx, uint8_t Data)
Write in Transmit Data Register .
ErrorStatus | LL_I2C_Init (I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
ErrorStatus | LL_I2C_DeInit (I2C_TypeDef *I2Cx)
De-initialize the I2C registers to their default reset values.
void | LL_I2C_StructInit (LL_I2C_InitTypeDef *I2C_InitStruct)
Set each LL_I2C_InitTypeDef field to default value.

Detailed Description

Header file of I2C LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_i2c.h.

Generated on Fri Sep 6 2019 11:34:39 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_ipcc.h File Reference

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Defines | Functions
stm32wbxx_ll_ipcc.h File Reference

Header file of IPCC LL module. More...

#include "stm32wbxx.h"

Go to the source code of this file.

Defines

#define | LL_IPCC_C1TOC2SR_CH1F IPCC_C1TOC2SR_CH1F_Msk
#define | LL_IPCC_C1TOC2SR_CH2F IPCC_C1TOC2SR_CH2F_Msk
#define | LL_IPCC_C1TOC2SR_CH3F IPCC_C1TOC2SR_CH3F_Msk
#define | LL_IPCC_C1TOC2SR_CH4F IPCC_C1TOC2SR_CH4F_Msk
#define | LL_IPCC_C1TOC2SR_CH5F IPCC_C1TOC2SR_CH5F_Msk
#define | LL_IPCC_C1TOC2SR_CH6F IPCC_C1TOC2SR_CH6F_Msk
#define | LL_IPCC_C2TOC1SR_CH1F IPCC_C2TOC1SR_CH1F_Msk
#define | LL_IPCC_C2TOC1SR_CH2F IPCC_C2TOC1SR_CH2F_Msk
#define | LL_IPCC_C2TOC1SR_CH3F IPCC_C2TOC1SR_CH3F_Msk
#define | LL_IPCC_C2TOC1SR_CH4F IPCC_C2TOC1SR_CH4F_Msk
#define | LL_IPCC_C2TOC1SR_CH5F IPCC_C2TOC1SR_CH5F_Msk
#define | LL_IPCC_C2TOC1SR_CH6F IPCC_C2TOC1SR_CH6F_Msk
#define | LL_IPCC_CHANNEL_1 (0x00000001U)
#define | LL_IPCC_CHANNEL_2 (0x00000002U)
#define | LL_IPCC_CHANNEL_3 (0x00000004U)
#define | LL_IPCC_CHANNEL_4 (0x00000008U)
#define | LL_IPCC_CHANNEL_5 (0x00000010U)
#define | LL_IPCC_CHANNEL_6 (0x00000020U)
#define | LL_IPCC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in IPCC register.
#define | LL_IPCC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in IPCC register.

Functions

__STATIC_INLINE void | LL_C1_IPCC_EnableIT_TXF (IPCC_TypeDef *IPCCx)
Enable Transmit channel free interrupt for processor 1.
__STATIC_INLINE void | LL_C1_IPCC_DisableIT_TXF (IPCC_TypeDef *IPCCx)
Disable Transmit channel free interrupt for processor 1.
__STATIC_INLINE uint32_t | LL_C1_IPCC_IsEnabledIT_TXF (IPCC_TypeDef const *const IPCCx)
Check if Transmit channel free interrupt for processor 1 is enabled.
__STATIC_INLINE void | LL_C1_IPCC_EnableIT_RXO (IPCC_TypeDef *IPCCx)
Enable Receive channel occupied interrupt for processor 1.
__STATIC_INLINE void | LL_C1_IPCC_DisableIT_RXO (IPCC_TypeDef *IPCCx)
Disable Receive channel occupied interrupt for processor 1.
__STATIC_INLINE uint32_t | LL_C1_IPCC_IsEnabledIT_RXO (IPCC_TypeDef const *const IPCCx)
Check if Receive channel occupied interrupt for processor 1 is enabled.
__STATIC_INLINE void | LL_C2_IPCC_EnableIT_TXF (IPCC_TypeDef *IPCCx)
Enable Transmit channel free interrupt for processor 2.
__STATIC_INLINE void | LL_C2_IPCC_DisableIT_TXF (IPCC_TypeDef *IPCCx)
Disable Transmit channel free interrupt for processor 2.
__STATIC_INLINE uint32_t | LL_C2_IPCC_IsEnabledIT_TXF (IPCC_TypeDef const *const IPCCx)
Check if Transmit channel free interrupt for processor 2 is enabled.
__STATIC_INLINE void | LL_C2_IPCC_EnableIT_RXO (IPCC_TypeDef *IPCCx)
Enable Receive channel occupied interrupt for processor 2.
__STATIC_INLINE void | LL_C2_IPCC_DisableIT_RXO (IPCC_TypeDef *IPCCx)
Disable Receive channel occupied interrupt for processor 2.
__STATIC_INLINE uint32_t | LL_C2_IPCC_IsEnabledIT_RXO (IPCC_TypeDef const *const IPCCx)
Check if Receive channel occupied interrupt for processor 2 is enabled.
__STATIC_INLINE void | LL_C1_IPCC_EnableTransmitChannel (IPCC_TypeDef *IPCCx, uint32_t Channel)
Unmask transmit channel free interrupt for processor 1.
__STATIC_INLINE void | LL_C1_IPCC_DisableTransmitChannel (IPCC_TypeDef *IPCCx, uint32_t Channel)
Mask transmit channel free interrupt for processor 1.
__STATIC_INLINE uint32_t | LL_C1_IPCC_IsEnabledTransmitChannel (IPCC_TypeDef const *const IPCCx, uint32_t Channel)
Check if Transmit channel free interrupt for processor 1 is masked.
__STATIC_INLINE void | LL_C1_IPCC_EnableReceiveChannel (IPCC_TypeDef *IPCCx, uint32_t Channel)
Unmask receive channel occupied interrupt for processor 1.
__STATIC_INLINE void | LL_C1_IPCC_DisableReceiveChannel (IPCC_TypeDef *IPCCx, uint32_t Channel)
Mask receive channel occupied interrupt for processor 1.
__STATIC_INLINE uint32_t | LL_C1_IPCC_IsEnabledReceiveChannel (IPCC_TypeDef const *const IPCCx, uint32_t Channel)
Check if Receive channel occupied interrupt for processor 1 is masked.
__STATIC_INLINE void | LL_C2_IPCC_EnableTransmitChannel (IPCC_TypeDef *IPCCx, uint32_t Channel)
Unmask transmit channel free interrupt for processor 2.
__STATIC_INLINE void | LL_C2_IPCC_DisableTransmitChannel (IPCC_TypeDef *IPCCx, uint32_t Channel)
Mask transmit channel free interrupt for processor 2.
__STATIC_INLINE uint32_t | LL_C2_IPCC_IsEnabledTransmitChannel (IPCC_TypeDef const *const IPCCx, uint32_t Channel)
Check if Transmit channel free interrupt for processor 2 is masked.
__STATIC_INLINE void | LL_C2_IPCC_EnableReceiveChannel (IPCC_TypeDef *IPCCx, uint32_t Channel)
Unmask receive channel occupied interrupt for processor 2.
__STATIC_INLINE void | LL_C2_IPCC_DisableReceiveChannel (IPCC_TypeDef *IPCCx, uint32_t Channel)
Mask receive channel occupied interrupt for processor 1.
__STATIC_INLINE uint32_t | LL_C2_IPCC_IsEnabledReceiveChannel (IPCC_TypeDef const *const IPCCx, uint32_t Channel)
Check if Receive channel occupied interrupt for processor 2 is masked.
__STATIC_INLINE void | LL_C1_IPCC_ClearFlag_CHx (IPCC_TypeDef *IPCCx, uint32_t Channel)
Clear IPCC receive channel status for processor 1.
__STATIC_INLINE void | LL_C1_IPCC_SetFlag_CHx (IPCC_TypeDef *IPCCx, uint32_t Channel)
Set IPCC transmit channel status for processor 1.
__STATIC_INLINE uint32_t | LL_C1_IPCC_IsActiveFlag_CHx (IPCC_TypeDef const *const IPCCx, uint32_t Channel)
Get channel status for processor 1.
__STATIC_INLINE void | LL_C2_IPCC_ClearFlag_CHx (IPCC_TypeDef *IPCCx, uint32_t Channel)
Clear IPCC receive channel status for processor 2.
__STATIC_INLINE void | LL_C2_IPCC_SetFlag_CHx (IPCC_TypeDef *IPCCx, uint32_t Channel)
Set IPCC transmit channel status for processor 2.
__STATIC_INLINE uint32_t | LL_C2_IPCC_IsActiveFlag_CHx (IPCC_TypeDef const *const IPCCx, uint32_t Channel)
Get channel status for processor 2.

Detailed Description

Header file of IPCC LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_ipcc.h.

Generated on Fri Sep 6 2019 11:34:39 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_iwdg.h File Reference

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stm32wbxx_ll_iwdg.h File Reference

Header file of IWDG LL module. More...

#include "stm32wbxx.h"

Go to the source code of this file.

Defines

#define | LL_IWDG_KEY_RELOAD 0x0000AAAAU
#define | LL_IWDG_KEY_ENABLE 0x0000CCCCU
#define | LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U
#define | LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U
#define | LL_IWDG_SR_PVU IWDG_SR_PVU
#define | LL_IWDG_SR_RVU IWDG_SR_RVU
#define | LL_IWDG_SR_WVU IWDG_SR_WVU
#define | LL_IWDG_PRESCALER_4 0x00000000U
#define | LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1)
#define | LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2)
#define | LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)
#define | LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in IWDG register.
#define | LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in IWDG register.

Functions

__STATIC_INLINE void | LL_IWDG_Enable (IWDG_TypeDef *IWDGx)
Start the Independent Watchdog.
__STATIC_INLINE void | LL_IWDG_ReloadCounter (IWDG_TypeDef *IWDGx)
Reloads IWDG counter with value defined in the reload register.
__STATIC_INLINE void | LL_IWDG_EnableWriteAccess (IWDG_TypeDef *IWDGx)
Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
__STATIC_INLINE void | LL_IWDG_DisableWriteAccess (IWDG_TypeDef *IWDGx)
Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
__STATIC_INLINE void | LL_IWDG_SetPrescaler (IWDG_TypeDef *IWDGx, uint32_t Prescaler)
Select the prescaler of the IWDG.
__STATIC_INLINE uint32_t | LL_IWDG_GetPrescaler (IWDG_TypeDef *IWDGx)
Get the selected prescaler of the IWDG.
__STATIC_INLINE void | LL_IWDG_SetReloadCounter (IWDG_TypeDef *IWDGx, uint32_t Counter)
Specify the IWDG down-counter reload value.
__STATIC_INLINE uint32_t | LL_IWDG_GetReloadCounter (IWDG_TypeDef *IWDGx)
Get the specified IWDG down-counter reload value.
__STATIC_INLINE void | LL_IWDG_SetWindow (IWDG_TypeDef *IWDGx, uint32_t Window)
Specify high limit of the window value to be compared to the down-counter.
__STATIC_INLINE uint32_t | LL_IWDG_GetWindow (IWDG_TypeDef *IWDGx)
Get the high limit of the window value specified.
__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_PVU (IWDG_TypeDef *IWDGx)
Check if flag Prescaler Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_RVU (IWDG_TypeDef *IWDGx)
Check if flag Reload Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_WVU (IWDG_TypeDef *IWDGx)
Check if flag Window Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsReady (IWDG_TypeDef *IWDGx)
Check if all flags Prescaler, Reload & Window Value Update are reset or not.

Detailed Description

Header file of IWDG LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_iwdg.h.

Generated on Fri Sep 6 2019 11:34:39 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_lptim.h File Reference

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stm32wbxx_ll_lptim.h File Reference

Header file of LPTIM LL module. More...

#include "stm32wbxx.h"

Go to the source code of this file.

Data Structures

struct | LL_LPTIM_InitTypeDef
LPTIM Init structure definition. More...

Defines

#define | LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM
#define | LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM
#define | LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG
#define | LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK
#define | LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK
#define | LL_LPTIM_ISR_UP LPTIM_ISR_UP
#define | LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN
#define | LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE
#define | LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE
#define | LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE
#define | LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE
#define | LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE
#define | LL_LPTIM_IER_UPIE LPTIM_IER_UPIE
#define | LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE
#define | LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT
#define | LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT
#define | LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U
#define | LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD
#define | LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U
#define | LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE
#define | LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U
#define | LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE
#define | LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U
#define | LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CFGR_WAVPOL
#define | LL_LPTIM_PRESCALER_DIV1 0x00000000U
#define | LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
#define | LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
#define | LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0)
#define | LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
#define | LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0)
#define | LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1)
#define | LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC
#define | LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U
#define | LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0
#define | LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1
#define | LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0)
#define | LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2
#define | LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0)
#define | LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1)
#define | LL_LPTIM_TRIG_SOURCE_COMP2 LPTIM_CFGR_TRIGSEL
#define | LL_LPTIM_TRIG_FILTER_NONE 0x00000000U
#define | LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0
#define | LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1
#define | LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT
#define | LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0
#define | LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1
#define | LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN
#define | LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U
#define | LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL
#define | LL_LPTIM_CLK_FILTER_NONE 0x00000000U
#define | LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0
#define | LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1
#define | LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT
#define | LL_LPTIM_CLK_POLARITY_RISING 0x00000000U
#define | LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0
#define | LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1
#define | LL_LPTIM_ENCODER_MODE_RISING 0x00000000U
#define | LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0
#define | LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1
#define | LL_LPTIM_INPUT1_SRC_GPIO 0x00000000U
#define | LL_LPTIM_INPUT1_SRC_COMP1 LPTIM_OR_OR_0
#define | LL_LPTIM_INPUT1_SRC_COMP2 LPTIM_OR_OR_1
#define | LL_LPTIM_INPUT1_SRC_COMP1_COMP2 LPTIM_OR_OR
#define | LL_LPTIM_INPUT2_SRC_GPIO 0x00000000U
#define | LL_LPTIM_INPUT2_SRC_COMP2 LPTIM_OR_OR_1
#define | LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
Write a value in LPTIM register.
#define | LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
Read a value in LPTIM register.

Functions

ErrorStatus | LL_LPTIM_DeInit (LPTIM_TypeDef *LPTIMx)
Set LPTIMx registers to their reset values.
void | LL_LPTIM_StructInit (LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
Set each fields of the LPTIM_InitStruct structure to its default value.
ErrorStatus | LL_LPTIM_Init (LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
Configure the LPTIMx peripheral according to the specified parameters.
void | LL_LPTIM_Disable (LPTIM_TypeDef *LPTIMx)
Disable the LPTIM instance.
__STATIC_INLINE void | LL_LPTIM_Enable (LPTIM_TypeDef *LPTIMx)
Enable the LPTIM instance.
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabled (LPTIM_TypeDef *LPTIMx)
Indicates whether the LPTIM instance is enabled.
__STATIC_INLINE void | LL_LPTIM_StartCounter (LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
Starts the LPTIM counter in the desired mode.
__STATIC_INLINE void | LL_LPTIM_EnableResetAfterRead (LPTIM_TypeDef *LPTIMx)
Enable reset after read.
__STATIC_INLINE void | LL_LPTIM_DisableResetAfterRead (LPTIM_TypeDef *LPTIMx)
Disable reset after read.
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledResetAfterRead (LPTIM_TypeDef *LPTIMx)
Indicate whether the reset after read feature is enabled.
__STATIC_INLINE void | LL_LPTIM_ResetCounter (LPTIM_TypeDef *LPTIMx)
Reset of the LPTIM_CNT counter register (synchronous).
__STATIC_INLINE void | LL_LPTIM_SetUpdateMode (LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
Set the LPTIM registers update mode (enable/disable register preload)
__STATIC_INLINE uint32_t | LL_LPTIM_GetUpdateMode (LPTIM_TypeDef *LPTIMx)
Get the LPTIM registers update mode.
__STATIC_INLINE void | LL_LPTIM_SetAutoReload (LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
Set the auto reload value.
__STATIC_INLINE uint32_t | LL_LPTIM_GetAutoReload (LPTIM_TypeDef *LPTIMx)
Get actual auto reload value.
__STATIC_INLINE void | LL_LPTIM_SetCompare (LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
Set the compare value.
__STATIC_INLINE uint32_t | LL_LPTIM_GetCompare (LPTIM_TypeDef *LPTIMx)
Get actual compare value.
__STATIC_INLINE uint32_t | LL_LPTIM_GetCounter (LPTIM_TypeDef *LPTIMx)
Get actual counter value.
__STATIC_INLINE void | LL_LPTIM_SetCounterMode (LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
Set the counter mode (selection of the LPTIM counter clock source).
__STATIC_INLINE uint32_t | LL_LPTIM_GetCounterMode (LPTIM_TypeDef *LPTIMx)
Get the counter mode.
__STATIC_INLINE void | LL_LPTIM_ConfigOutput (LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity)
Configure the LPTIM instance output (LPTIMx_OUT)
__STATIC_INLINE void | LL_LPTIM_SetWaveform (LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
Set waveform shape.
__STATIC_INLINE uint32_t | LL_LPTIM_GetWaveform (LPTIM_TypeDef *LPTIMx)
Get actual waveform shape.
__STATIC_INLINE void | LL_LPTIM_SetPolarity (LPTIM_TypeDef *LPTIMx, uint32_t Polarity)
Set output polarity.
__STATIC_INLINE uint32_t | LL_LPTIM_GetPolarity (LPTIM_TypeDef *LPTIMx)
Get actual output polarity.
__STATIC_INLINE void | LL_LPTIM_SetPrescaler (LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
Set actual prescaler division ratio.
__STATIC_INLINE uint32_t | LL_LPTIM_GetPrescaler (LPTIM_TypeDef *LPTIMx)
Get actual prescaler division ratio.
__STATIC_INLINE void | LL_LPTIM_SetInput1Src (LPTIM_TypeDef *LPTIMx, uint32_t Src)
Set LPTIM input 1 source (default GPIO).
__STATIC_INLINE void | LL_LPTIM_SetInput2Src (LPTIM_TypeDef *LPTIMx, uint32_t Src)
Set LPTIM input 2 source (default GPIO).
__STATIC_INLINE void | LL_LPTIM_EnableTimeout (LPTIM_TypeDef *LPTIMx)
Enable the timeout function.
__STATIC_INLINE void | LL_LPTIM_DisableTimeout (LPTIM_TypeDef *LPTIMx)
Disable the timeout function.
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledTimeout (LPTIM_TypeDef *LPTIMx)
Indicate whether the timeout function is enabled.
__STATIC_INLINE void | LL_LPTIM_TrigSw (LPTIM_TypeDef *LPTIMx)
Start the LPTIM counter.
__STATIC_INLINE void | LL_LPTIM_ConfigTrigger (LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
Configure the external trigger used as a trigger event for the LPTIM.
__STATIC_INLINE uint32_t | LL_LPTIM_GetTriggerSource (LPTIM_TypeDef *LPTIMx)
Get actual external trigger source.
__STATIC_INLINE uint32_t | LL_LPTIM_GetTriggerFilter (LPTIM_TypeDef *LPTIMx)
Get actual external trigger filter.
__STATIC_INLINE uint32_t | LL_LPTIM_GetTriggerPolarity (LPTIM_TypeDef *LPTIMx)
Get actual external trigger polarity.
__STATIC_INLINE void | LL_LPTIM_SetClockSource (LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
Set the source of the clock used by the LPTIM instance.
__STATIC_INLINE uint32_t | LL_LPTIM_GetClockSource (LPTIM_TypeDef *LPTIMx)
Get actual LPTIM instance clock source.
__STATIC_INLINE void | LL_LPTIM_ConfigClock (LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source.
__STATIC_INLINE uint32_t | LL_LPTIM_GetClockPolarity (LPTIM_TypeDef *LPTIMx)
Get actual clock polarity.
__STATIC_INLINE uint32_t | LL_LPTIM_GetClockFilter (LPTIM_TypeDef *LPTIMx)
Get actual clock digital filter.
__STATIC_INLINE void | LL_LPTIM_SetEncoderMode (LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
Configure the encoder mode.
__STATIC_INLINE uint32_t | LL_LPTIM_GetEncoderMode (LPTIM_TypeDef *LPTIMx)
Get actual encoder mode.
__STATIC_INLINE void | LL_LPTIM_EnableEncoderMode (LPTIM_TypeDef *LPTIMx)
Enable the encoder mode.
__STATIC_INLINE void | LL_LPTIM_DisableEncoderMode (LPTIM_TypeDef *LPTIMx)
Disable the encoder mode.
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledEncoderMode (LPTIM_TypeDef *LPTIMx)
Indicates whether the LPTIM operates in encoder mode.
__STATIC_INLINE void | LL_LPTIM_ClearFLAG_CMPM (LPTIM_TypeDef *LPTIMx)
Clear the compare match flag (CMPMCF)
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_CMPM (LPTIM_TypeDef *LPTIMx)
Inform application whether a compare match interrupt has occurred.
__STATIC_INLINE void | LL_LPTIM_ClearFLAG_ARRM (LPTIM_TypeDef *LPTIMx)
Clear the autoreload match flag (ARRMCF)
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_ARRM (LPTIM_TypeDef *LPTIMx)
Inform application whether a autoreload match interrupt has occured.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Clear the external trigger valid edge flag(EXTTRIGCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Inform application whether a valid edge on the selected external trigger input has occurred.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_CMPOK (LPTIM_TypeDef *LPTIMx)
Clear the compare register update interrupt flag (CMPOKCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_CMPOK (LPTIM_TypeDef *LPTIMx)
Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_ARROK (LPTIM_TypeDef *LPTIMx)
Clear the autoreload register update interrupt flag (ARROKCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_ARROK (LPTIM_TypeDef *LPTIMx)
Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed.
__STATIC_INLINE void | LL_LPTIM_ClearFlag_UP (LPTIM_TypeDef *LPTIMx)
Clear the counter direction change to up interrupt flag (UPCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_UP (LPTIM_TypeDef *LPTIMx)
Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode).
__STATIC_INLINE void | LL_LPTIM_ClearFlag_DOWN (LPTIM_TypeDef *LPTIMx)
Clear the counter direction change to down interrupt flag (DOWNCF).
__STATIC_INLINE uint32_t | LL_LPTIM_IsActiveFlag_DOWN (LPTIM_TypeDef *LPTIMx)
Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode).
__STATIC_INLINE void | LL_LPTIM_EnableIT_CMPM (LPTIM_TypeDef *LPTIMx)
Enable compare match interrupt (CMPMIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_CMPM (LPTIM_TypeDef *LPTIMx)
Disable compare match interrupt (CMPMIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_CMPM (LPTIM_TypeDef *LPTIMx)
Indicates whether the compare match interrupt (CMPMIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_ARRM (LPTIM_TypeDef *LPTIMx)
Enable autoreload match interrupt (ARRMIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_ARRM (LPTIM_TypeDef *LPTIMx)
Disable autoreload match interrupt (ARRMIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_ARRM (LPTIM_TypeDef *LPTIMx)
Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Enable external trigger valid edge interrupt (EXTTRIGIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Disable external trigger valid edge interrupt (EXTTRIGIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_EXTTRIG (LPTIM_TypeDef *LPTIMx)
Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_CMPOK (LPTIM_TypeDef *LPTIMx)
Enable compare register write completed interrupt (CMPOKIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_CMPOK (LPTIM_TypeDef *LPTIMx)
Disable compare register write completed interrupt (CMPOKIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_CMPOK (LPTIM_TypeDef *LPTIMx)
Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_ARROK (LPTIM_TypeDef *LPTIMx)
Enable autoreload register write completed interrupt (ARROKIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_ARROK (LPTIM_TypeDef *LPTIMx)
Disable autoreload register write completed interrupt (ARROKIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_ARROK (LPTIM_TypeDef *LPTIMx)
Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_UP (LPTIM_TypeDef *LPTIMx)
Enable direction change to up interrupt (UPIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_UP (LPTIM_TypeDef *LPTIMx)
Disable direction change to up interrupt (UPIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_UP (LPTIM_TypeDef *LPTIMx)
Indicates whether the direction change to up interrupt (UPIE) is enabled.
__STATIC_INLINE void | LL_LPTIM_EnableIT_DOWN (LPTIM_TypeDef *LPTIMx)
Enable direction change to down interrupt (DOWNIE).
__STATIC_INLINE void | LL_LPTIM_DisableIT_DOWN (LPTIM_TypeDef *LPTIMx)
Disable direction change to down interrupt (DOWNIE).
__STATIC_INLINE uint32_t | LL_LPTIM_IsEnabledIT_DOWN (LPTIM_TypeDef *LPTIMx)
Indicates whether the direction change to down interrupt (DOWNIE) is enabled.

Detailed Description

Header file of LPTIM LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_lptim.h.

Generated on Fri Sep 6 2019 11:34:39 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_lpuart.h File Reference

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Data Structures | Defines | Functions | Variables
stm32wbxx_ll_lpuart.h File Reference

Header file of LPUART LL module. More...

#include "stm32wbxx.h"

Go to the source code of this file.

Data Structures

struct | LL_LPUART_InitTypeDef
LL LPUART Init Structure definition. More...

Defines

#define | LPUART_LPUARTDIV_FREQ_MUL 256U
#define | LPUART_BRR_MASK 0x000FFFFFU
#define | LPUART_BRR_MIN_VALUE 0x00000300U
#define | LL_LPUART_ICR_PECF USART_ICR_PECF
#define | LL_LPUART_ICR_FECF USART_ICR_FECF
#define | LL_LPUART_ICR_NCF USART_ICR_NECF
#define | LL_LPUART_ICR_ORECF USART_ICR_ORECF
#define | LL_LPUART_ICR_IDLECF USART_ICR_IDLECF
#define | LL_LPUART_ICR_TXFECF USART_ICR_TXFECF
#define | LL_LPUART_ICR_TCCF USART_ICR_TCCF
#define | LL_LPUART_ICR_CTSCF USART_ICR_CTSCF
#define | LL_LPUART_ICR_CMCF USART_ICR_CMCF
#define | LL_LPUART_ICR_WUCF USART_ICR_WUCF
#define | LL_LPUART_ISR_PE USART_ISR_PE
#define | LL_LPUART_ISR_FE USART_ISR_FE
#define | LL_LPUART_ISR_NE USART_ISR_NE
#define | LL_LPUART_ISR_ORE USART_ISR_ORE
#define | LL_LPUART_ISR_IDLE USART_ISR_IDLE
#define | LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE
#define | LL_LPUART_ISR_TC USART_ISR_TC
#define | LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF
#define | LL_LPUART_ISR_CTSIF USART_ISR_CTSIF
#define | LL_LPUART_ISR_CTS USART_ISR_CTS
#define | LL_LPUART_ISR_BUSY USART_ISR_BUSY
#define | LL_LPUART_ISR_CMF USART_ISR_CMF
#define | LL_LPUART_ISR_SBKF USART_ISR_SBKF
#define | LL_LPUART_ISR_RWU USART_ISR_RWU
#define | LL_LPUART_ISR_WUF USART_ISR_WUF
#define | LL_LPUART_ISR_TEACK USART_ISR_TEACK
#define | LL_LPUART_ISR_REACK USART_ISR_REACK
#define | LL_LPUART_ISR_TXFE USART_ISR_TXFE
#define | LL_LPUART_ISR_RXFF USART_ISR_RXFF
#define | LL_LPUART_ISR_RXFT USART_ISR_RXFT
#define | LL_LPUART_ISR_TXFT USART_ISR_TXFT
#define | LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE
#define | LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE
#define | LL_LPUART_CR1_TCIE USART_CR1_TCIE
#define | LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE
#define | LL_LPUART_CR1_PEIE USART_CR1_PEIE
#define | LL_LPUART_CR1_CMIE USART_CR1_CMIE
#define | LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE
#define | LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE
#define | LL_LPUART_CR3_EIE USART_CR3_EIE
#define | LL_LPUART_CR3_CTSIE USART_CR3_CTSIE
#define | LL_LPUART_CR3_WUFIE USART_CR3_WUFIE
#define | LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE
#define | LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE
#define | LL_LPUART_FIFOTHRESHOLD_1_8 0x00000000U
#define | LL_LPUART_FIFOTHRESHOLD_1_4 0x00000001U
#define | LL_LPUART_FIFOTHRESHOLD_1_2 0x00000002U
#define | LL_LPUART_FIFOTHRESHOLD_3_4 0x00000003U
#define | LL_LPUART_FIFOTHRESHOLD_7_8 0x00000004U
#define | LL_LPUART_FIFOTHRESHOLD_8_8 0x00000005U
#define | LL_LPUART_DIRECTION_NONE 0x00000000U
#define | LL_LPUART_DIRECTION_RX USART_CR1_RE
#define | LL_LPUART_DIRECTION_TX USART_CR1_TE
#define | LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)
#define | LL_LPUART_PARITY_NONE 0x00000000U
#define | LL_LPUART_PARITY_EVEN USART_CR1_PCE
#define | LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)
#define | LL_LPUART_WAKEUP_IDLELINE 0x00000000U
#define | LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE
#define | LL_LPUART_DATAWIDTH_7B USART_CR1_M1
#define | LL_LPUART_DATAWIDTH_8B 0x00000000U
#define | LL_LPUART_DATAWIDTH_9B USART_CR1_M0
#define | LL_LPUART_PRESCALER_DIV1 0x00000000U
#define | LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0)
#define | LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1)
#define | LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)
#define | LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2)
#define | LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0)
#define | LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1)
#define | LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)
#define | LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3)
#define | LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0)
#define | LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1)
#define | LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)
#define | LL_LPUART_STOPBITS_1 0x00000000U
#define | LL_LPUART_STOPBITS_2 USART_CR2_STOP_1
#define | LL_LPUART_TXRX_STANDARD 0x00000000U
#define | LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP)
#define | LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U
#define | LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV)
#define | LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U
#define | LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV)
#define | LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U
#define | LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV
#define | LL_LPUART_BITORDER_LSBFIRST 0x00000000U
#define | LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST
#define | LL_LPUART_ADDRESS_DETECT_4B 0x00000000U
#define | LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7
#define | LL_LPUART_HWCONTROL_NONE 0x00000000U
#define | LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE
#define | LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE
#define | LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
#define | LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U
#define | LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1
#define | LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)
#define | LL_LPUART_DE_POLARITY_HIGH 0x00000000U
#define | LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP
#define | LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U
#define | LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U
#define | LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in LPUART register.
#define | LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in LPUART register.
#define | __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__)
Compute LPUARTDIV value according to Peripheral Clock and expected Baud Rate (20-bit value of LPUARTDIV is returned)
#define | LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE
#define | LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF
#define | LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE
#define | LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF
#define | LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE
#define | LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF
#define | LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE
#define | LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF

Functions

__STATIC_INLINE void | LL_LPUART_Enable (USART_TypeDef *LPUARTx)
LPUART Enable.
__STATIC_INLINE void | LL_LPUART_Disable (USART_TypeDef *LPUARTx)
LPUART Disable.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabled (USART_TypeDef *LPUARTx)
Indicate if LPUART is enabled.
__STATIC_INLINE void | LL_LPUART_EnableFIFO (USART_TypeDef *LPUARTx)
FIFO Mode Enable.
__STATIC_INLINE void | LL_LPUART_DisableFIFO (USART_TypeDef *LPUARTx)
FIFO Mode Disable.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledFIFO (USART_TypeDef *LPUARTx)
Indicate if FIFO Mode is enabled.
__STATIC_INLINE void | LL_LPUART_SetTXFIFOThreshold (USART_TypeDef *LPUARTx, uint32_t Threshold)
Configure TX FIFO Threshold.
__STATIC_INLINE uint32_t | LL_LPUART_GetTXFIFOThreshold (USART_TypeDef *LPUARTx)
Return TX FIFO Threshold Configuration.
__STATIC_INLINE void | LL_LPUART_SetRXFIFOThreshold (USART_TypeDef *LPUARTx, uint32_t Threshold)
Configure RX FIFO Threshold.
__STATIC_INLINE uint32_t | LL_LPUART_GetRXFIFOThreshold (USART_TypeDef *LPUARTx)
Return RX FIFO Threshold Configuration.
__STATIC_INLINE void | LL_LPUART_ConfigFIFOsThreshold (USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)
Configure TX and RX FIFOs Threshold.
__STATIC_INLINE void | LL_LPUART_EnableInStopMode (USART_TypeDef *LPUARTx)
LPUART enabled in STOP Mode.
__STATIC_INLINE void | LL_LPUART_DisableInStopMode (USART_TypeDef *LPUARTx)
LPUART disabled in STOP Mode.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledInStopMode (USART_TypeDef *LPUARTx)
Indicate if LPUART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
__STATIC_INLINE void | LL_LPUART_EnableDirectionRx (USART_TypeDef *LPUARTx)
Receiver Enable (Receiver is enabled and begins searching for a start bit)
__STATIC_INLINE void | LL_LPUART_DisableDirectionRx (USART_TypeDef *LPUARTx)
Receiver Disable.
__STATIC_INLINE void | LL_LPUART_EnableDirectionTx (USART_TypeDef *LPUARTx)
Transmitter Enable.
__STATIC_INLINE void | LL_LPUART_DisableDirectionTx (USART_TypeDef *LPUARTx)
Transmitter Disable.
__STATIC_INLINE void | LL_LPUART_SetTransferDirection (USART_TypeDef *LPUARTx, uint32_t TransferDirection)
Configure simultaneously enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE uint32_t | LL_LPUART_GetTransferDirection (USART_TypeDef *LPUARTx)
Return enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE void | LL_LPUART_SetParity (USART_TypeDef *LPUARTx, uint32_t Parity)
Configure Parity (enabled/disabled and parity mode if enabled)
__STATIC_INLINE uint32_t | LL_LPUART_GetParity (USART_TypeDef *LPUARTx)
Return Parity configuration (enabled/disabled and parity mode if enabled)
__STATIC_INLINE void | LL_LPUART_SetWakeUpMethod (USART_TypeDef *LPUARTx, uint32_t Method)
Set Receiver Wake Up method from Mute mode.
__STATIC_INLINE uint32_t | LL_LPUART_GetWakeUpMethod (USART_TypeDef *LPUARTx)
Return Receiver Wake Up method from Mute mode.
__STATIC_INLINE void | LL_LPUART_SetDataWidth (USART_TypeDef *LPUARTx, uint32_t DataWidth)
Set Word length (nb of data bits, excluding start and stop bits)
__STATIC_INLINE uint32_t | LL_LPUART_GetDataWidth (USART_TypeDef *LPUARTx)
Return Word length (i.e.
__STATIC_INLINE void | LL_LPUART_EnableMuteMode (USART_TypeDef *LPUARTx)
Allow switch between Mute Mode and Active mode.
__STATIC_INLINE void | LL_LPUART_DisableMuteMode (USART_TypeDef *LPUARTx)
Prevent Mute Mode use.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledMuteMode (USART_TypeDef *LPUARTx)
Indicate if switch between Mute Mode and Active mode is allowed.
__STATIC_INLINE void | LL_LPUART_SetPrescaler (USART_TypeDef *LPUARTx, uint32_t PrescalerValue)
Configure Clock source prescaler for baudrate generator and oversampling.
__STATIC_INLINE uint32_t | LL_LPUART_GetPrescaler (USART_TypeDef *LPUARTx)
Retrieve the Clock source prescaler for baudrate generator and oversampling.
__STATIC_INLINE void | LL_LPUART_SetStopBitsLength (USART_TypeDef *LPUARTx, uint32_t StopBits)
Set the length of the stop bits.
__STATIC_INLINE uint32_t | LL_LPUART_GetStopBitsLength (USART_TypeDef *LPUARTx)
Retrieve the length of the stop bits.
__STATIC_INLINE void | LL_LPUART_ConfigCharacter (USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity, uint32_t StopBits)
Configure Character frame format (Datawidth, Parity control, Stop Bits)
__STATIC_INLINE void | LL_LPUART_SetTXRXSwap (USART_TypeDef *LPUARTx, uint32_t SwapConfig)
Configure TX/RX pins swapping setting.
__STATIC_INLINE uint32_t | LL_LPUART_GetTXRXSwap (USART_TypeDef *LPUARTx)
Retrieve TX/RX pins swapping configuration.
__STATIC_INLINE void | LL_LPUART_SetRXPinLevel (USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
Configure RX pin active level logic.
__STATIC_INLINE uint32_t | LL_LPUART_GetRXPinLevel (USART_TypeDef *LPUARTx)
Retrieve RX pin active level logic configuration.
__STATIC_INLINE void | LL_LPUART_SetTXPinLevel (USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
Configure TX pin active level logic.
__STATIC_INLINE uint32_t | LL_LPUART_GetTXPinLevel (USART_TypeDef *LPUARTx)
Retrieve TX pin active level logic configuration.
__STATIC_INLINE void | LL_LPUART_SetBinaryDataLogic (USART_TypeDef *LPUARTx, uint32_t DataLogic)
Configure Binary data logic.
__STATIC_INLINE uint32_t | LL_LPUART_GetBinaryDataLogic (USART_TypeDef *LPUARTx)
Retrieve Binary data configuration.
__STATIC_INLINE void | LL_LPUART_SetTransferBitOrder (USART_TypeDef *LPUARTx, uint32_t BitOrder)
Configure transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE uint32_t | LL_LPUART_GetTransferBitOrder (USART_TypeDef *LPUARTx)
Return transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE void | LL_LPUART_ConfigNodeAddress (USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
Set Address of the LPUART node.
__STATIC_INLINE uint32_t | LL_LPUART_GetNodeAddress (USART_TypeDef *LPUARTx)
Return 8 bit Address of the LPUART node as set in ADD field of CR2.
__STATIC_INLINE uint32_t | LL_LPUART_GetNodeAddressLen (USART_TypeDef *LPUARTx)
Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
__STATIC_INLINE void | LL_LPUART_EnableRTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Enable RTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_DisableRTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Disable RTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_EnableCTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Enable CTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_DisableCTSHWFlowCtrl (USART_TypeDef *LPUARTx)
Disable CTS HW Flow Control.
__STATIC_INLINE void | LL_LPUART_SetHWFlowCtrl (USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
Configure HW Flow Control mode (both CTS and RTS)
__STATIC_INLINE uint32_t | LL_LPUART_GetHWFlowCtrl (USART_TypeDef *LPUARTx)
Return HW Flow Control configuration (both CTS and RTS)
__STATIC_INLINE void | LL_LPUART_EnableOverrunDetect (USART_TypeDef *LPUARTx)
Enable Overrun detection.
__STATIC_INLINE void | LL_LPUART_DisableOverrunDetect (USART_TypeDef *LPUARTx)
Disable Overrun detection.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledOverrunDetect (USART_TypeDef *LPUARTx)
Indicate if Overrun detection is enabled.
__STATIC_INLINE void | LL_LPUART_SetWKUPType (USART_TypeDef *LPUARTx, uint32_t Type)
Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE uint32_t | LL_LPUART_GetWKUPType (USART_TypeDef *LPUARTx)
Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE void | LL_LPUART_SetBaudRate (USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t BaudRate)
Configure LPUART BRR register for achieving expected Baud Rate value.
__STATIC_INLINE uint32_t | LL_LPUART_GetBaudRate (USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue)
Return current Baud Rate value, according to LPUARTDIV present in BRR register (full BRR content), and to used Peripheral Clock values.
__STATIC_INLINE void | LL_LPUART_EnableHalfDuplex (USART_TypeDef *LPUARTx)
Enable Single Wire Half-Duplex mode.
__STATIC_INLINE void | LL_LPUART_DisableHalfDuplex (USART_TypeDef *LPUARTx)
Disable Single Wire Half-Duplex mode.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledHalfDuplex (USART_TypeDef *LPUARTx)
Indicate if Single Wire Half-Duplex mode is enabled.
__STATIC_INLINE void | LL_LPUART_SetDEDeassertionTime (USART_TypeDef *LPUARTx, uint32_t Time)
Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_LPUART_GetDEDeassertionTime (USART_TypeDef *LPUARTx)
Return DEDT (Driver Enable De-Assertion Time)
__STATIC_INLINE void | LL_LPUART_SetDEAssertionTime (USART_TypeDef *LPUARTx, uint32_t Time)
Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_LPUART_GetDEAssertionTime (USART_TypeDef *LPUARTx)
Return DEAT (Driver Enable Assertion Time)
__STATIC_INLINE void | LL_LPUART_EnableDEMode (USART_TypeDef *LPUARTx)
Enable Driver Enable (DE) Mode.
__STATIC_INLINE void | LL_LPUART_DisableDEMode (USART_TypeDef *LPUARTx)
Disable Driver Enable (DE) Mode.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDEMode (USART_TypeDef *LPUARTx)
Indicate if Driver Enable (DE) Mode is enabled.
__STATIC_INLINE void | LL_LPUART_SetDESignalPolarity (USART_TypeDef *LPUARTx, uint32_t Polarity)
Select Driver Enable Polarity.
__STATIC_INLINE uint32_t | LL_LPUART_GetDESignalPolarity (USART_TypeDef *LPUARTx)
Return Driver Enable Polarity.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_PE (USART_TypeDef *LPUARTx)
Check if the LPUART Parity Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_FE (USART_TypeDef *LPUARTx)
Check if the LPUART Framing Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_NE (USART_TypeDef *LPUARTx)
Check if the LPUART Noise error detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_ORE (USART_TypeDef *LPUARTx)
Check if the LPUART OverRun Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_IDLE (USART_TypeDef *LPUARTx)
Check if the LPUART IDLE line detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_RXNE_RXFNE (USART_TypeDef *LPUARTx)
Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TC (USART_TypeDef *LPUARTx)
Check if the LPUART Transmission Complete Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TXE_TXFNF (USART_TypeDef *LPUARTx)
Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_nCTS (USART_TypeDef *LPUARTx)
Check if the LPUART CTS interrupt Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_CTS (USART_TypeDef *LPUARTx)
Check if the LPUART CTS Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_BUSY (USART_TypeDef *LPUARTx)
Check if the LPUART Busy Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_CM (USART_TypeDef *LPUARTx)
Check if the LPUART Character Match Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_SBK (USART_TypeDef *LPUARTx)
Check if the LPUART Send Break Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_RWU (USART_TypeDef *LPUARTx)
Check if the LPUART Receive Wake Up from mute mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_WKUP (USART_TypeDef *LPUARTx)
Check if the LPUART Wake Up from stop mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TEACK (USART_TypeDef *LPUARTx)
Check if the LPUART Transmit Enable Acknowledge Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_REACK (USART_TypeDef *LPUARTx)
Check if the LPUART Receive Enable Acknowledge Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TXFE (USART_TypeDef *LPUARTx)
Check if the LPUART TX FIFO Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_RXFF (USART_TypeDef *LPUARTx)
Check if the LPUART RX FIFO Full Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_TXFT (USART_TypeDef *LPUARTx)
Check if the LPUART TX FIFO Threshold Flag is set or not.
__STATIC_INLINE uint32_t | LL_LPUART_IsActiveFlag_RXFT (USART_TypeDef *LPUARTx)
Check if the LPUART RX FIFO Threshold Flag is set or not.
__STATIC_INLINE void | LL_LPUART_ClearFlag_PE (USART_TypeDef *LPUARTx)
Clear Parity Error Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_FE (USART_TypeDef *LPUARTx)
Clear Framing Error Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_NE (USART_TypeDef *LPUARTx)
Clear Noise detected Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_ORE (USART_TypeDef *LPUARTx)
Clear OverRun Error Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_IDLE (USART_TypeDef *LPUARTx)
Clear IDLE line detected Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_TXFE (USART_TypeDef *LPUARTx)
Clear TX FIFO Empty Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_TC (USART_TypeDef *LPUARTx)
Clear Transmission Complete Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_nCTS (USART_TypeDef *LPUARTx)
Clear CTS Interrupt Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_CM (USART_TypeDef *LPUARTx)
Clear Character Match Flag.
__STATIC_INLINE void | LL_LPUART_ClearFlag_WKUP (USART_TypeDef *LPUARTx)
Clear Wake Up from stop mode Flag.
__STATIC_INLINE void | LL_LPUART_EnableIT_IDLE (USART_TypeDef *LPUARTx)
Enable IDLE Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_RXNE_RXFNE (USART_TypeDef *LPUARTx)
Enable RX Not Empty and RX FIFO Not Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_TC (USART_TypeDef *LPUARTx)
Enable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_TXE_TXFNF (USART_TypeDef *LPUARTx)
Enable TX Empty and TX FIFO Not Full Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_PE (USART_TypeDef *LPUARTx)
Enable Parity Error Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_CM (USART_TypeDef *LPUARTx)
Enable Character Match Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_TXFE (USART_TypeDef *LPUARTx)
Enable TX FIFO Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_RXFF (USART_TypeDef *LPUARTx)
Enable RX FIFO Full Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_ERROR (USART_TypeDef *LPUARTx)
Enable Error Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_CTS (USART_TypeDef *LPUARTx)
Enable CTS Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_WKUP (USART_TypeDef *LPUARTx)
Enable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_TXFT (USART_TypeDef *LPUARTx)
Enable TX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_LPUART_EnableIT_RXFT (USART_TypeDef *LPUARTx)
Enable RX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_IDLE (USART_TypeDef *LPUARTx)
Disable IDLE Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_RXNE_RXFNE (USART_TypeDef *LPUARTx)
Disable RX Not Empty and RX FIFO Not Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_TC (USART_TypeDef *LPUARTx)
Disable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_TXE_TXFNF (USART_TypeDef *LPUARTx)
Disable TX Empty and TX FIFO Not Full Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_PE (USART_TypeDef *LPUARTx)
Disable Parity Error Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_CM (USART_TypeDef *LPUARTx)
Disable Character Match Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_TXFE (USART_TypeDef *LPUARTx)
Disable TX FIFO Empty Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_RXFF (USART_TypeDef *LPUARTx)
Disable RX FIFO Full Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_ERROR (USART_TypeDef *LPUARTx)
Disable Error Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_CTS (USART_TypeDef *LPUARTx)
Disable CTS Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_WKUP (USART_TypeDef *LPUARTx)
Disable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_TXFT (USART_TypeDef *LPUARTx)
Disable TX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_LPUART_DisableIT_RXFT (USART_TypeDef *LPUARTx)
Disable RX FIFO Threshold Interrupt.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_IDLE (USART_TypeDef *LPUARTx)
Check if the LPUART IDLE Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_RXNE_RXFNE (USART_TypeDef *LPUARTx)
Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_TC (USART_TypeDef *LPUARTx)
Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_TXE_TXFNF (USART_TypeDef *LPUARTx)
Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_PE (USART_TypeDef *LPUARTx)
Check if the LPUART Parity Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_CM (USART_TypeDef *LPUARTx)
Check if the LPUART Character Match Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_TXFE (USART_TypeDef *LPUARTx)
Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_RXFF (USART_TypeDef *LPUARTx)
Check if the LPUART RX FIFO Full Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_ERROR (USART_TypeDef *LPUARTx)
Check if the LPUART Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_CTS (USART_TypeDef *LPUARTx)
Check if the LPUART CTS Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_WKUP (USART_TypeDef *LPUARTx)
Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_TXFT (USART_TypeDef *LPUARTx)
Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledIT_RXFT (USART_TypeDef *LPUARTx)
Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_LPUART_EnableDMAReq_RX (USART_TypeDef *LPUARTx)
Enable DMA Mode for reception.
__STATIC_INLINE void | LL_LPUART_DisableDMAReq_RX (USART_TypeDef *LPUARTx)
Disable DMA Mode for reception.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDMAReq_RX (USART_TypeDef *LPUARTx)
Check if DMA Mode is enabled for reception.
__STATIC_INLINE void | LL_LPUART_EnableDMAReq_TX (USART_TypeDef *LPUARTx)
Enable DMA Mode for transmission.
__STATIC_INLINE void | LL_LPUART_DisableDMAReq_TX (USART_TypeDef *LPUARTx)
Disable DMA Mode for transmission.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDMAReq_TX (USART_TypeDef *LPUARTx)
Check if DMA Mode is enabled for transmission.
__STATIC_INLINE void | LL_LPUART_EnableDMADeactOnRxErr (USART_TypeDef *LPUARTx)
Enable DMA Disabling on Reception Error.
__STATIC_INLINE void | LL_LPUART_DisableDMADeactOnRxErr (USART_TypeDef *LPUARTx)
Disable DMA Disabling on Reception Error.
__STATIC_INLINE uint32_t | LL_LPUART_IsEnabledDMADeactOnRxErr (USART_TypeDef *LPUARTx)
Indicate if DMA Disabling on Reception Error is disabled.
__STATIC_INLINE uint32_t | LL_LPUART_DMA_GetRegAddr (USART_TypeDef *LPUARTx, uint32_t Direction)
Get the LPUART data register address used for DMA transfer.
__STATIC_INLINE uint8_t | LL_LPUART_ReceiveData8 (USART_TypeDef *LPUARTx)
Read Receiver Data register (Receive Data value, 8 bits)
__STATIC_INLINE uint16_t | LL_LPUART_ReceiveData9 (USART_TypeDef *LPUARTx)
Read Receiver Data register (Receive Data value, 9 bits)
__STATIC_INLINE void | LL_LPUART_TransmitData8 (USART_TypeDef *LPUARTx, uint8_t Value)
Write in Transmitter Data Register (Transmit Data value, 8 bits)
__STATIC_INLINE void | LL_LPUART_TransmitData9 (USART_TypeDef *LPUARTx, uint16_t Value)
Write in Transmitter Data Register (Transmit Data value, 9 bits)
__STATIC_INLINE void | LL_LPUART_RequestBreakSending (USART_TypeDef *LPUARTx)
Request Break sending.
__STATIC_INLINE void | LL_LPUART_RequestEnterMuteMode (USART_TypeDef *LPUARTx)
Put LPUART in mute mode and set the RWU flag.
__STATIC_INLINE void | LL_LPUART_RequestRxDataFlush (USART_TypeDef *LPUARTx)
Request a Receive Data and FIFO flush.
ErrorStatus | LL_LPUART_DeInit (USART_TypeDef *LPUARTx)
De-initialize LPUART registers (Registers restored to their default values).
ErrorStatus | LL_LPUART_Init (USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct)
Initialize LPUART registers according to the specified parameters in LPUART_InitStruct.
void | LL_LPUART_StructInit (LL_LPUART_InitTypeDef *LPUART_InitStruct)
Set each LL_LPUART_InitTypeDef field to default value.

Variables

static const uint16_t | LPUART_PRESCALER_TAB []

Detailed Description

Header file of LPUART LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_lpuart.h.

Generated on Fri Sep 6 2019 11:34:39 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_pka.h File Reference

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Data Structures | Defines | Functions
stm32wbxx_ll_pka.h File Reference

Header file of PKA LL module. More...

#include "stm32wbxx.h"

Go to the source code of this file.

Data Structures

struct | LL_PKA_InitTypeDef
PKA Init structures definition. More...

Defines

#define | LL_PKA_SR_ADDRERRF PKA_SR_ADDRERRF
#define | LL_PKA_SR_RAMERRF PKA_SR_RAMERRF
#define | LL_PKA_SR_PROCENDF PKA_SR_PROCENDF
#define | LL_PKA_SR_BUSY PKA_SR_BUSY
#define | LL_PKA_CR_ADDRERRIE PKA_CR_ADDRERRIE
#define | LL_PKA_CR_RAMERRIE PKA_CR_RAMERRIE
#define | LL_PKA_CR_PROCENDIE PKA_CR_PROCENDIE
#define | LL_PKA_CLRFR_PROCENDFC PKA_CLRFR_PROCENDFC
#define | LL_PKA_CLRFR_RAMERRFC PKA_CLRFR_RAMERRFC
#define | LL_PKA_CLRFR_ADDRERRFC PKA_CLRFR_ADDRERRFC
#define | LL_PKA_MODE_MONTGOMERY_PARAM_MOD_EXP ((uint32_t)0x00000000U)
#define | LL_PKA_MODE_MONTGOMERY_PARAM ((uint32_t)0x00000001U)
#define | LL_PKA_MODE_MODULAR_EXP ((uint32_t)0x00000002U)
#define | LL_PKA_MODE_MONTGOMERY_PARAM_ECC ((uint32_t)0x00000020U)
#define | LL_PKA_MODE_ECC_KP_PRIMITIVE ((uint32_t)0x00000022U)
#define | LL_PKA_MODE_ECDSA_SIGNATURE ((uint32_t)0x00000024U)
#define | LL_PKA_MODE_ECDSA_VERIFICATION ((uint32_t)0x00000026U)
#define | LL_PKA_MODE_POINT_CHECK ((uint32_t)0x00000028U)
#define | LL_PKA_MODE_RSA_CRT_EXP ((uint32_t)0x00000007U)
#define | LL_PKA_MODE_MODULAR_INV ((uint32_t)0x00000008U)
#define | LL_PKA_MODE_ARITHMETIC_ADD ((uint32_t)0x00000009U)
#define | LL_PKA_MODE_ARITHMETIC_SUB ((uint32_t)0x0000000AU)
#define | LL_PKA_MODE_ARITHMETIC_MUL ((uint32_t)0x0000000BU)
#define | LL_PKA_MODE_COMPARISON ((uint32_t)0x0000000CU)
#define | LL_PKA_MODE_MODULAR_REDUC ((uint32_t)0x0000000DU)
#define | LL_PKA_MODE_MODULAR_ADD ((uint32_t)0x0000000EU)
#define | LL_PKA_MODE_MODULAR_SUB ((uint32_t)0x0000000FU)
#define | LL_PKA_MODE_MONTGOMERY_MUL ((uint32_t)0x00000010U)
#define | LL_PKA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in PKA register.
#define | LL_PKA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in PKA register.

Functions

__STATIC_INLINE void | LL_PKA_Config (PKA_TypeDef *PKAx, uint32_t Mode)
Configure PKA peripheral.
__STATIC_INLINE void | LL_PKA_Enable (PKA_TypeDef *PKAx)
Enable PKA peripheral.
__STATIC_INLINE void | LL_PKA_Disable (PKA_TypeDef *PKAx)
Disable PKA peripheral.
__STATIC_INLINE uint32_t | LL_PKA_IsEnabled (PKA_TypeDef *PKAx)
Check if the PKA peripheral is enabled or disabled.
__STATIC_INLINE void | LL_PKA_SetMode (PKA_TypeDef *PKAx, uint32_t Mode)
Set PKA operating mode.
__STATIC_INLINE uint32_t | LL_PKA_GetMode (PKA_TypeDef *PKAx)
Get PKA operating mode.
__STATIC_INLINE void | LL_PKA_Start (PKA_TypeDef *PKAx)
Start the operation selected using LL_PKA_SetMode.
__STATIC_INLINE void | LL_PKA_EnableIT_ADDRERR (PKA_TypeDef *PKAx)
Enable address error interrupt.
__STATIC_INLINE void | LL_PKA_EnableIT_RAMERR (PKA_TypeDef *PKAx)
Enable RAM error interrupt.
__STATIC_INLINE void | LL_PKA_EnableIT_PROCEND (PKA_TypeDef *PKAx)
Enable end of operation interrupt.
__STATIC_INLINE void | LL_PKA_DisableIT_ADDERR (PKA_TypeDef *PKAx)
Disable address error interrupt.
__STATIC_INLINE void | LL_PKA_DisableIT_RAMERR (PKA_TypeDef *PKAx)
Disable RAM error interrupt.
__STATIC_INLINE void | LL_PKA_DisableIT_PROCEND (PKA_TypeDef *PKAx)
Disable End of operation interrupt.
__STATIC_INLINE uint32_t | LL_PKA_IsEnabledIT_ADDRERR (PKA_TypeDef *PKAx)
Check if address error interrupt is enabled.
__STATIC_INLINE uint32_t | LL_PKA_IsEnabledIT_RAMERR (PKA_TypeDef *PKAx)
Check if RAM error interrupt is enabled.
__STATIC_INLINE uint32_t | LL_PKA_IsEnabledIT_PROCEND (PKA_TypeDef *PKAx)
Check if end of operation interrupt is enabled.
__STATIC_INLINE uint32_t | LL_PKA_IsActiveFlag_ADDRERR (PKA_TypeDef *PKAx)
Get PKA address error flag.
__STATIC_INLINE uint32_t | LL_PKA_IsActiveFlag_RAMERR (PKA_TypeDef *PKAx)
Get PKA RAM error flag.
__STATIC_INLINE uint32_t | LL_PKA_IsActiveFlag_PROCEND (PKA_TypeDef *PKAx)
Get PKA end of operation flag.
__STATIC_INLINE uint32_t | LL_PKA_IsActiveFlag_BUSY (PKA_TypeDef *PKAx)
Get PKA busy flag.
__STATIC_INLINE void | LL_PKA_ClearFlag_ADDERR (PKA_TypeDef *PKAx)
Clear PKA address error flag.
__STATIC_INLINE void | LL_PKA_ClearFlag_RAMERR (PKA_TypeDef *PKAx)
Clear PKA RAM error flag.
__STATIC_INLINE void | LL_PKA_ClearFlag_PROCEND (PKA_TypeDef *PKAx)
Clear PKA end of operation flag.
ErrorStatus | LL_PKA_DeInit (PKA_TypeDef *PKAx)
De-initialize PKA registers (Registers restored to their default values).
ErrorStatus | LL_PKA_Init (PKA_TypeDef *PKAx, LL_PKA_InitTypeDef *PKA_InitStruct)
Initialize PKA registers according to the specified parameters in PKA_InitStruct.
void | LL_PKA_StructInit (LL_PKA_InitTypeDef *PKA_InitStruct)
Set each LL_PKA_InitTypeDef field to default value.

Detailed Description

Header file of PKA LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_pka.h.

Generated on Fri Sep 6 2019 11:34:39 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_pwr.h File Reference

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Defines | Functions
stm32wbxx_ll_pwr.h File Reference

Header file of PWR LL module. More...

#include "stm32wbxx.h"

Go to the source code of this file.

Defines

#define | SMPS_VOLTAGE_CAL_ADDR ((uint32_t*) (0x1FFF7558UL)) /* SMPS output voltage calibration level corresponding to voltage "SMPS_VOLTAGE_CAL_VOLTAGE_MV" */
#define | SMPS_VOLTAGE_CAL_POS (8UL) /* SMPS output voltage calibration level bitfield position */
#define | SMPS_VOLTAGE_CAL (0xFUL << SMPS_VOLTAGE_CAL_POS) /* SMPS output voltage calibration level bitfield mask */
#define | SMPS_VOLTAGE_CAL_VOLTAGE_MV (1500UL) /* SMPS output voltage calibration value (unit: mV) */
#define | SMPS_VOLTAGE_BASE_MV (1200UL) /* SMPS output voltage base value (unit: mV) */
#define | SMPS_VOLTAGE_STEP_MV ( 50UL) /* SMPS output voltage step (unit: mV) */
#define | LL_PWR_SCR_CWUF PWR_SCR_CWUF
#define | LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5
#define | LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4
#define | LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3
#define | LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2
#define | LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1
#define | LL_PWR_SCR_CC2HF PWR_SCR_CC2HF
#define | LL_PWR_SCR_C802AF PWR_SCR_C802AF
#define | LL_PWR_SCR_CBLEAF PWR_SCR_CBLEAF
#define | LL_PWR_SCR_CCRPEF PWR_SCR_CCRPEF
#define | LL_PWR_SCR_C802WUF PWR_SCR_C802WUF
#define | LL_PWR_SCR_CBLEWUF PWR_SCR_CBLEWUF
#define | LL_PWR_SCR_CBORHF PWR_SCR_CBORHF
#define | LL_PWR_SCR_CSMPSFBF PWR_SCR_CSMPSFBF
#define | LL_PWR_EXTSCR_CCRPF PWR_EXTSCR_CCRPF
#define | LL_PWR_EXTSCR_C2CSSF PWR_EXTSCR_C2CSSF
#define | LL_PWR_EXTSCR_C1CSSF PWR_EXTSCR_C1CSSF
#define | LL_PWR_SR1_WUFI PWR_SR1_WUFI
#define | LL_PWR_SR1_WUF5 PWR_SR1_WUF5
#define | LL_PWR_SR1_WUF4 PWR_SR1_WUF4
#define | LL_PWR_SR1_WUF3 PWR_SR1_WUF3
#define | LL_PWR_SR1_WUF2 PWR_SR1_WUF2
#define | LL_PWR_SR1_WUF1 PWR_SR1_WUF1
#define | LL_PWR_SR2_PVMO3 PWR_SR2_PVMO3
#define | LL_PWR_SR2_PVMO1 PWR_SR2_PVMO1
#define | LL_PWR_SR2_PVDO PWR_SR2_PVDO
#define | LL_PWR_SR2_VOSF PWR_SR2_VOSF
#define | LL_PWR_SR2_REGLPF PWR_SR2_REGLPF
#define | LL_PWR_SR2_REGLPS PWR_SR2_REGLPS
#define | LL_PWR_FLAG_BORH PWR_SR1_BORHF /* BORH interrupt flag */
#define | LL_PWR_FLAG_SMPS PWR_SR2_SMPSF /* SMPS step down converter ready flag */
#define | LL_PWR_FLAG_SMPSB PWR_SR2_SMPSBF /* SMPS step down converter in bypass mode flag */
#define | LL_PWR_FLAG_SMPSFB PWR_SR1_SMPSFB /* SMPS step down converter forced in bypass mode interrupt flag */
#define | LL_PWR_FLAG_BLEWU PWR_SR1_BLEWUF /* BLE wakeup interrupt flag */
#define | LL_PWR_FLAG_802WU PWR_SR1_802WUF /* 802.15.4 wakeup interrupt flag */
#define | LL_PWR_FLAG_BLEA PWR_SR1_BLEAF /* BLE end of activity interrupt flag */
#define | LL_PWR_FLAG_802A PWR_SR1_802AF /* 802.15.4 end of activity interrupt flag */
#define | LL_PWR_FLAG_CRPE PWR_SR1_CRPEF /* Critical radio phase end of activity interrupt flag */
#define | LL_PWR_FLAG_CRP PWR_EXTSCR_CRPF /* Critical radio system phase */
#define | LL_PWR_EXTSCR_C1SBF PWR_EXTSCR_C1SBF /* System standby flag for CPU1 */
#define | LL_PWR_EXTSCR_C1STOPF PWR_EXTSCR_C1STOPF /* System stop flag for CPU1 */
#define | LL_PWR_EXTSCR_C1DS PWR_EXTSCR_C1DS /* CPU1 deepsleep mode */
#define | LL_PWR_EXTSCR_C2SBF PWR_EXTSCR_C2SBF /* System standby flag for CPU2 */
#define | LL_PWR_EXTSCR_C2STOPF PWR_EXTSCR_C2STOPF /* System stop flag for CPU2 */
#define | LL_PWR_EXTSCR_C2DS PWR_EXTSCR_C2DS /* CPU2 deepsleep mode */
#define | LL_PWR_SR1_C2HF PWR_SR1_C2HF /* CPU2 hold interrupt flag */
#define | LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR1_VOS_0) /* Regulator voltage output range 1 mode, typical output voltage at 1.2 V, system frequency up to 64 MHz. */
#define | LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR1_VOS_1) /* Regulator voltage output range 2 mode, typical output voltage at 1.0 V, system frequency up to 16 MHz. */
#define | LL_PWR_MODE_STOP0 (0x000000000U)
#define | LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_0)
#define | LL_PWR_MODE_STOP2 (PWR_CR1_LPMS_1)
#define | LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_1 | PWR_CR1_LPMS_0)
#define | LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_2)
#define | LL_PWR_FLASH_LPRUN_MODE_IDLE (0x000000000U)
#define | LL_PWR_FLASH_LPRUN_MODE_POWER_DOWN (PWR_CR1_FPDR)
#define | LL_PWR_FLASH_SLEEP_MODE_IDLE (0x000000000U)
#define | LL_PWR_FLASH_SLEEP_MODE_POWER_DOWN (PWR_CR1_FPDS)
#define | LL_PWR_PVM_VDDUSB_1_2V (PWR_CR2_PVME1) /* Monitoring VDDUSB vs. 1.2V */
#define | LL_PWR_PVM_VDDA_1_62V (PWR_CR2_PVME3) /* Monitoring VDDA vs. 1.62V */
#define | LL_PWR_PVDLEVEL_0 (0x00000000U) /* VPVD0 around 2.0 V */
#define | LL_PWR_PVDLEVEL_1 (PWR_CR2_PLS_0) /* VPVD1 around 2.2 V */
#define | LL_PWR_PVDLEVEL_2 (PWR_CR2_PLS_1) /* VPVD2 around 2.4 V */
#define | LL_PWR_PVDLEVEL_3 (PWR_CR2_PLS_1 | PWR_CR2_PLS_0) /* VPVD3 around 2.5 V */
#define | LL_PWR_PVDLEVEL_4 (PWR_CR2_PLS_2) /* VPVD4 around 2.6 V */
#define | LL_PWR_PVDLEVEL_5 (PWR_CR2_PLS_2 | PWR_CR2_PLS_0) /* VPVD5 around 2.8 V */
#define | LL_PWR_PVDLEVEL_6 (PWR_CR2_PLS_2 | PWR_CR2_PLS_1) /* VPVD6 around 2.9 V */
#define | LL_PWR_PVDLEVEL_7 (PWR_CR2_PLS_2 | PWR_CR2_PLS_1 | PWR_CR2_PLS_0) /* External input analog voltage (Compare internally to VREFINT) */
#define | LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1)
#define | LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2)
#define | LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3)
#define | LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4)
#define | LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5)
#define | LL_PWR_BATT_CHARG_RESISTOR_5K (0x00000000U)
#define | LL_PWR_BATT_CHARGRESISTOR_1_5K (PWR_CR4_VBRS)
#define | LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA)))
#define | LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))
#define | LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC)))
#define | LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD)))
#define | LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE)))
#define | LL_PWR_GPIO_H ((uint32_t)(&(PWR->PUCRH)))
#define | LL_PWR_GPIO_BIT_0 (PWR_PUCRC_PC0)
#define | LL_PWR_GPIO_BIT_1 (PWR_PUCRC_PC1)
#define | LL_PWR_GPIO_BIT_2 (PWR_PUCRC_PC2)
#define | LL_PWR_GPIO_BIT_3 (PWR_PUCRC_PC3)
#define | LL_PWR_GPIO_BIT_4 (PWR_PUCRC_PC4)
#define | LL_PWR_GPIO_BIT_5 (PWR_PUCRC_PC5)
#define | LL_PWR_GPIO_BIT_6 (PWR_PUCRC_PC6)
#define | LL_PWR_GPIO_BIT_7 (PWR_PUCRC_PC7)
#define | LL_PWR_GPIO_BIT_8 (PWR_PUCRC_PC8)
#define | LL_PWR_GPIO_BIT_9 (PWR_PUCRC_PC9)
#define | LL_PWR_GPIO_BIT_10 (PWR_PUCRC_PC10)
#define | LL_PWR_GPIO_BIT_11 (PWR_PUCRC_PC11)
#define | LL_PWR_GPIO_BIT_12 (PWR_PUCRC_PC12)
#define | LL_PWR_GPIO_BIT_13 (PWR_PUCRC_PC13)
#define | LL_PWR_GPIO_BIT_14 (PWR_PUCRC_PC14)
#define | LL_PWR_GPIO_BIT_15 (PWR_PUCRC_PC15)
#define | LL_PWR_BOR_SYSTEM_RESET (0x00000000U)
#define | LL_PWR_BOR_SMPS_FORCE_BYPASS (PWR_CR5_BORHC)
#define | LL_PWR_SMPS_BYPASS (PWR_SR2_SMPSBF)
#define | LL_PWR_SMPS_STEP_DOWN (PWR_SR2_SMPSF)
#define | LL_PWR_SMPS_STARTUP_CURRENT_80MA (0x00000000U)
#define | LL_PWR_SMPS_STARTUP_CURRENT_100MA ( PWR_CR5_SMPSSC_0)
#define | LL_PWR_SMPS_STARTUP_CURRENT_120MA ( PWR_CR5_SMPSSC_1 )
#define | LL_PWR_SMPS_STARTUP_CURRENT_140MA ( PWR_CR5_SMPSSC_1 | PWR_CR5_SMPSSC_0)
#define | LL_PWR_SMPS_STARTUP_CURRENT_160MA (PWR_CR5_SMPSSC_2 )
#define | LL_PWR_SMPS_STARTUP_CURRENT_180MA (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_0)
#define | LL_PWR_SMPS_STARTUP_CURRENT_200MA (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_1 )
#define | LL_PWR_SMPS_STARTUP_CURRENT_220MA (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_1 | PWR_CR5_SMPSSC_0)
#define | LL_PWR_SMPS_OUTPUT_VOLTAGE_1V20 (0x00000000U)
#define | LL_PWR_SMPS_OUTPUT_VOLTAGE_1V25 ( PWR_CR5_SMPSVOS_0)
#define | LL_PWR_SMPS_OUTPUT_VOLTAGE_1V30 ( PWR_CR5_SMPSVOS_1 )
#define | LL_PWR_SMPS_OUTPUT_VOLTAGE_1V35 ( PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0)
#define | LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40 ( PWR_CR5_SMPSVOS_2 )
#define | LL_PWR_SMPS_OUTPUT_VOLTAGE_1V45 ( PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_0)
#define | LL_PWR_SMPS_OUTPUT_VOLTAGE_1V50 ( PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1 )
#define | LL_PWR_SMPS_OUTPUT_VOLTAGE_1V55 ( PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0)
#define | LL_PWR_SMPS_OUTPUT_VOLTAGE_1V60 (PWR_CR5_SMPSVOS_3 )
#define | LL_PWR_SMPS_OUTPUT_VOLTAGE_1V65 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_0)
#define | LL_PWR_SMPS_OUTPUT_VOLTAGE_1V70 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_1 )
#define | LL_PWR_SMPS_OUTPUT_VOLTAGE_1V75 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0)
#define | LL_PWR_SMPS_OUTPUT_VOLTAGE_1V80 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 )
#define | LL_PWR_SMPS_OUTPUT_VOLTAGE_1V85 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_0)
#define | LL_PWR_SMPS_OUTPUT_VOLTAGE_1V90 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1 )
#define | LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
Write a value in PWR register.
#define | LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
Read a value in PWR register.

Functions

__STATIC_INLINE void | LL_PWR_EnterLowPowerRunMode (void)
Switch from run main mode to run low-power mode.
__STATIC_INLINE void | LL_PWR_ExitLowPowerRunMode (void)
Switch from run main mode to low-power mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledLowPowerRunMode (void)
Check if the regulator is in low-power mode.
__STATIC_INLINE void | LL_PWR_SetRegulVoltageScaling (uint32_t VoltageScaling)
Set the main internal regulator output voltage.
__STATIC_INLINE uint32_t | LL_PWR_GetRegulVoltageScaling (void)
Get the main internal regulator output voltage.
__STATIC_INLINE void | LL_PWR_EnableBkUpAccess (void)
Enable access to the backup domain.
__STATIC_INLINE void | LL_PWR_DisableBkUpAccess (void)
Disable access to the backup domain.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledBkUpAccess (void)
Check if the backup domain is enabled.
__STATIC_INLINE void | LL_PWR_SetPowerMode (uint32_t LowPowerMode)
Set Low-Power mode.
__STATIC_INLINE uint32_t | LL_PWR_GetPowerMode (void)
Get Low-Power mode.
__STATIC_INLINE void | LL_PWR_SetFlashPowerModeLPRun (uint32_t FlashLowPowerMode)
Set flash power-down mode during low-power run mode.
__STATIC_INLINE uint32_t | LL_PWR_GetFlashPowerModeLPRun (void)
Get flash power-down mode during low-power run mode.
__STATIC_INLINE void | LL_PWR_SetFlashPowerModeSleep (uint32_t FlashLowPowerMode)
Set flash power-down mode during sleep mode.
__STATIC_INLINE uint32_t | LL_PWR_GetFlashPowerModeSleep (void)
Get flash power-down mode during sleep mode.
__STATIC_INLINE void | LL_PWR_EnableVddUSB (void)
Enable VDDUSB supply.
__STATIC_INLINE void | LL_PWR_DisableVddUSB (void)
Disable VDDUSB supply.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledVddUSB (void)
Check if VDDUSB supply is enabled.
__STATIC_INLINE void | LL_PWR_EnablePVM (uint32_t PeriphVoltage)
Enable the Power Voltage Monitoring on a peripheral.
__STATIC_INLINE void | LL_PWR_DisablePVM (uint32_t PeriphVoltage)
Disable the Power Voltage Monitoring on a peripheral.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledPVM (uint32_t PeriphVoltage)
Check if Power Voltage Monitoring is enabled on a peripheral.
__STATIC_INLINE void | LL_PWR_SetPVDLevel (uint32_t PVDLevel)
Configure the voltage threshold detected by the Power Voltage Detector.
__STATIC_INLINE uint32_t | LL_PWR_GetPVDLevel (void)
Get the voltage threshold detection.
__STATIC_INLINE void | LL_PWR_EnablePVD (void)
Enable Power Voltage Detector.
__STATIC_INLINE void | LL_PWR_DisablePVD (void)
Disable Power Voltage Detector.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledPVD (void)
Check if Power Voltage Detector is enabled.
__STATIC_INLINE void | LL_PWR_EnableInternWU (void)
Enable Internal Wake-up line.
__STATIC_INLINE void | LL_PWR_DisableInternWU (void)
Disable Internal Wake-up line.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledInternWU (void)
Check if Internal Wake-up line is enabled.
__STATIC_INLINE void | LL_PWR_EnablePUPDCfg (void)
Enable pull-up and pull-down configuration.
__STATIC_INLINE void | LL_PWR_DisablePUPDCfg (void)
Disable pull-up and pull-down configuration.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledPUPDCfg (void)
Check if pull-up and pull-down configuration is enabled.
__STATIC_INLINE void | LL_PWR_EnableSRAM2Retention (void)
Enable SRAM2 content retention in Standby mode.
__STATIC_INLINE void | LL_PWR_DisableSRAM2Retention (void)
Disable SRAM2 content retention in Standby mode.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledSRAM2Retention (void)
Check if SRAM2 content retention in Standby mode is enabled.
__STATIC_INLINE void | LL_PWR_EnableWakeUpPin (uint32_t WakeUpPin)
Enable the WakeUp PINx functionality.
__STATIC_INLINE void | LL_PWR_DisableWakeUpPin (uint32_t WakeUpPin)
Disable the WakeUp PINx functionality.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledWakeUpPin (uint32_t WakeUpPin)
Check if the WakeUp PINx functionality is enabled.
__STATIC_INLINE void | LL_PWR_SetBattChargResistor (uint32_t Resistor)
Set the resistor impedance.
__STATIC_INLINE uint32_t | LL_PWR_GetBattChargResistor (void)
Get the resistor impedance.
__STATIC_INLINE void | LL_PWR_EnableBatteryCharging (void)
Enable battery charging.
__STATIC_INLINE void | LL_PWR_DisableBatteryCharging (void)
Disable battery charging.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledBatteryCharging (void)
Check if battery charging is enabled.
__STATIC_INLINE void | LL_PWR_SetWakeUpPinPolarityLow (uint32_t WakeUpPin)
Set the Wake-Up pin polarity low for the event detection.
__STATIC_INLINE void | LL_PWR_SetWakeUpPinPolarityHigh (uint32_t WakeUpPin)
Set the Wake-Up pin polarity high for the event detection.
__STATIC_INLINE uint32_t | LL_PWR_IsWakeUpPinPolarityLow (uint32_t WakeUpPin)
Get the Wake-Up pin polarity for the event detection.
__STATIC_INLINE void | LL_PWR_EnableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-up state in Standby and Shutdown modes.
__STATIC_INLINE void | LL_PWR_DisableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-up state in Standby and Shutdown modes.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Check if GPIO pull-up state is enabled.
__STATIC_INLINE void | LL_PWR_EnableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-down state in Standby and Shutdown modes.
__STATIC_INLINE void | LL_PWR_DisableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-down state in Standby and Shutdown modes.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Check if GPIO pull-down state is enabled.
__STATIC_INLINE void | LL_PWR_SetBORConfig (uint32_t BORConfiguration)
Set BOR configuration.
__STATIC_INLINE uint32_t | LL_PWR_GetBORConfig (void)
Get BOR configuration.
__STATIC_INLINE void | LL_PWR_SMPS_SetMode (uint32_t OperatingMode)
Set SMPS operating mode.
__STATIC_INLINE uint32_t | LL_PWR_SMPS_GetMode (void)
Get SMPS operating mode.
__STATIC_INLINE uint32_t | LL_PWR_SMPS_GetEffectiveMode (void)
Get SMPS effective operating mode.
__STATIC_INLINE void | LL_PWR_SMPS_Enable (void)
SMPS step down converter enable.
__STATIC_INLINE void | LL_PWR_SMPS_Disable (void)
SMPS step down converter enable.
__STATIC_INLINE uint32_t | LL_PWR_SMPS_IsEnabled (void)
Check if the SMPS step down converter is enabled.
__STATIC_INLINE void | LL_PWR_SMPS_SetStartupCurrent (uint32_t StartupCurrent)
Set SMPS step down converter supply startup current selection.
__STATIC_INLINE uint32_t | LL_PWR_SMPS_GetStartupCurrent (void)
Get SMPS step down converter supply startup current selection.
__STATIC_INLINE void | LL_PWR_SMPS_SetOutputVoltageLevel (uint32_t OutputVoltageLevel)
Set SMPS step down converter output voltage scaling.
__STATIC_INLINE uint32_t | LL_PWR_SMPS_GetOutputVoltageLevel (void)
Get SMPS step down converter output voltage scaling.
__STATIC_INLINE void | LL_PWR_EnableBootC2 (void)
Boot CPU2 after reset or wakeup from stop or standby modes.
__STATIC_INLINE void | LL_PWR_DisableBootC2 (void)
Release bit to boot CPU2 after reset or wakeup from stop or standby modes.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledBootC2 (void)
Check if bit to boot CPU2 after reset or wakeup from stop or standby modes is set.
__STATIC_INLINE void | LL_C2_PWR_SetPowerMode (uint32_t LowPowerMode)
Set Low-Power mode for CPU2.
__STATIC_INLINE uint32_t | LL_C2_PWR_GetPowerMode (void)
Get Low-Power mode for CPU2.
__STATIC_INLINE void | LL_C2_PWR_SetFlashPowerModeLPRun (uint32_t FlashLowPowerMode)
Set flash power-down mode during low-power run mode for CPU2.
__STATIC_INLINE uint32_t | LL_C2_PWR_GetFlashPowerModeLPRun (void)
Get flash power-down mode during low-power run mode for CPU2.
__STATIC_INLINE void | LL_C2_PWR_SetFlashPowerModeSleep (uint32_t FlashLowPowerMode)
Set flash power-down mode during sleep mode for CPU2.
__STATIC_INLINE uint32_t | LL_C2_PWR_GetFlashPowerModeSleep (void)
Get flash power-down mode during sleep mode for CPU2.
__STATIC_INLINE void | LL_C2_PWR_EnableInternWU (void)
Enable Internal Wake-up line for CPU2.
__STATIC_INLINE void | LL_C2_PWR_DisableInternWU (void)
Disable Internal Wake-up line for CPU2.
__STATIC_INLINE uint32_t | LL_C2_PWR_IsEnabledInternWU (void)
Check if Internal Wake-up line is enabled for CPU2.
__STATIC_INLINE void | LL_C2_PWR_EnableWakeUpPin (uint32_t WakeUpPin)
Enable the WakeUp PINx functionality.
__STATIC_INLINE void | LL_C2_PWR_DisableWakeUpPin (uint32_t WakeUpPin)
Disable the WakeUp PINx functionality.
__STATIC_INLINE uint32_t | LL_C2_PWR_IsEnabledWakeUpPin (uint32_t WakeUpPin)
Check if the WakeUp PINx functionality is enabled.
__STATIC_INLINE void | LL_C2_PWR_EnablePUPDCfg (void)
Enable pull-up and pull-down configuration for CPU2.
__STATIC_INLINE void | LL_C2_PWR_DisablePUPDCfg (void)
Disable pull-up and pull-down configuration for CPU2.
__STATIC_INLINE uint32_t | LL_C2_PWR_IsEnabledPUPDCfg (void)
Check if pull-up and pull-down configuration is enabled for CPU2.
__STATIC_INLINE void | LL_C2_PWR_WakeUp_BLE (void)
Wakeup BLE controller from its sleep mode.
__STATIC_INLINE uint32_t | LL_C2_PWR_IsWokenUp_BLE (void)
Check if the BLE controller is woken-up from low-power mode.
__STATIC_INLINE void | LL_C2_PWR_WakeUp_802_15_4 (void)
Wakeup 802.15.4 controller from its sleep mode.
__STATIC_INLINE uint32_t | LL_C2_PWR_IsWokenUp_802_15_4 (void)
Check if the 802.15.4 controller is woken-up from low-power mode.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_InternWU (void)
Get Internal Wake-up line Flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU5 (void)
Get Wake-up Flag 5.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU4 (void)
Get Wake-up Flag 4.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU3 (void)
Get Wake-up Flag 3.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU2 (void)
Get Wake-up Flag 2.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU1 (void)
Get Wake-up Flag 1.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU (void)
Clear Wake-up Flags.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU5 (void)
Clear Wake-up Flag 5.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU4 (void)
Clear Wake-up Flag 4.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU3 (void)
Clear Wake-up Flag 3.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU2 (void)
Clear Wake-up Flag 2.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU1 (void)
Clear Wake-up Flag 1.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_PVMO3 (void)
Indicate whether VDDA voltage is below or above PVM3 threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_PVMO1 (void)
Indicate whether VDDUSB voltage is below or above PVM1 threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_PVDO (void)
Indicate whether VDD voltage is below or above the selected PVD threshold.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_VOS (void)
Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_REGLPF (void)
Indicate whether the regulator is ready in main mode or is in low-power mode.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_REGLPS (void)
Indicate whether or not the low-power regulator is ready.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_BORH (void)
Get BORH interrupt flag.
__STATIC_INLINE void | LL_PWR_ClearFlag_BORH (void)
Clear BORH interrupt flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_SMPSFB (void)
Get SMPS step down converter forced in bypass mode interrupt flag.
__STATIC_INLINE void | LL_PWR_ClearFlag_SMPSFB (void)
Clear SMPS step down converter forced in bypass mode interrupt flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_BLEWU (void)
Get BLE wakeup interrupt flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_802WU (void)
Get 802.15.4 wakeup interrupt flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_BLEA (void)
Get BLE end of activity interrupt flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_802A (void)
Get 802.15.4 end of activity interrupt flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_CRPE (void)
Get critical radio phase end of activity interrupt flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_CRP (void)
Get critical radio system phase flag.
__STATIC_INLINE void | LL_PWR_ClearFlag_BLEWU (void)
Clear BLE wakeup interrupt flag.
__STATIC_INLINE void | LL_PWR_ClearFlag_802WU (void)
Clear 802.15.4 wakeup interrupt flag.
__STATIC_INLINE void | LL_PWR_ClearFlag_BLEA (void)
Clear BLE end of activity interrupt flag.
__STATIC_INLINE void | LL_PWR_ClearFlag_802A (void)
Clear 802.15.4 end of activity interrupt flag.
__STATIC_INLINE void | LL_PWR_ClearFlag_CRPE (void)
Clear critical radio phase end of activity interrupt flag.
__STATIC_INLINE void | LL_PWR_ClearFlag_CRP (void)
Clear critical radio system phase flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_C2H (void)
Get CPU2 hold interrupt flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_C1STOP (void)
Get system stop flag for CPU1.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_C1SB (void)
Get system standby flag for CPU1.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_C1DS (void)
Get deepsleep mode for CPU1.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_C2STOP (void)
System stop flag for CPU2.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_C2SB (void)
System standby flag for CPU2.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_C2DS (void)
Get deepsleep mode for CPU2.
__STATIC_INLINE void | LL_PWR_ClearFlag_C2H (void)
Clear CPU2 hold interrupt flag.
__STATIC_INLINE void | LL_PWR_ClearFlag_C1STOP_C1STB (void)
Clear standby and stop flags for CPU1.
__STATIC_INLINE void | LL_PWR_ClearFlag_C2STOP_C2STB (void)
Clear standby and stop flags for CPU2.
__STATIC_INLINE void | LL_PWR_EnableIT_BORH_SMPSFB (void)
Enable SMPS step down converter forced in bypass mode by BORH interrupt for CPU1.
__STATIC_INLINE void | LL_PWR_DisableIT_BORH_SMPSFB (void)
Disable SMPS step down converter forced in bypass mode by BORH interrupt for CPU1.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledIT_BORH_SMPSFB (void)
Check if SMPS step down converter forced in bypass mode by BORH interrupt is enabled for CPU1.
__STATIC_INLINE void | LL_PWR_EnableIT_BLEA (void)
Enable BLE end of activity interrupt for CPU1.
__STATIC_INLINE void | LL_PWR_EnableIT_802A (void)
Enable 802.15.4 end of activity interrupt for CPU1.
__STATIC_INLINE void | LL_PWR_DisableIT_BLEA (void)
Disable BLE end of activity interrupt for CPU1.
__STATIC_INLINE void | LL_PWR_DisableIT_802A (void)
Disable 802.15.4 end of activity interrupt for CPU1.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledIT_BLEA (void)
Check if BLE end of activity interrupt is enabled for CPU1.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledIT_802A (void)
Check if 802.15.4 end of activity interrupt is enabled for CPU1.
__STATIC_INLINE void | LL_PWR_EnableIT_CRPE (void)
Enable critical radio phase end of activity interrupt for CPU1.
__STATIC_INLINE void | LL_PWR_DisableIT_CRPE (void)
Disable critical radio phase end of activity interrupt for CPU1.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledIT_CRPE (void)
Check if critical radio phase end of activity interrupt is enabled for CPU1.
__STATIC_INLINE void | LL_PWR_EnableIT_HoldCPU2 (void)
Enable CPU2 hold interrupt for CPU1.
__STATIC_INLINE void | LL_PWR_DisableIT_HoldCPU2 (void)
Disable 802.15.4 host wakeup interrupt for CPU2.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledIT_HoldCPU2 (void)
Check if BLE host wakeup interrupt is enabled for CPU2.
__STATIC_INLINE void | LL_C2_PWR_EnableIT_BLEWU (void)
Enable BLE host wakeup interrupt for CPU2.
__STATIC_INLINE void | LL_C2_PWR_EnableIT_802WU (void)
Enable 802.15.4 host wakeup interrupt for CPU2.
__STATIC_INLINE void | LL_C2_PWR_DisableIT_BLEWU (void)
Disable BLE host wakeup interrupt for CPU2.
__STATIC_INLINE void | LL_C2_PWR_DisableIT_802WU (void)
Disable 802.15.4 host wakeup interrupt for CPU2.
__STATIC_INLINE uint32_t | LL_C2_PWR_IsEnabledIT_BLEWU (void)
Check if BLE host wakeup interrupt is enabled for CPU2.
__STATIC_INLINE uint32_t | LL_C2_PWR_IsEnabledIT_802WU (void)
Check if 802.15.4 host wakeup interrupt is enabled for CPU2.
ErrorStatus | LL_PWR_DeInit (void)
De-initialize the PWR registers to their default reset values.

Detailed Description

Header file of PWR LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_pwr.h.

Generated on Fri Sep 6 2019 11:34:39 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_rcc.h File Reference

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Data Structures | Defines | Functions
stm32wbxx_ll_rcc.h File Reference

Header file of RCC LL module. More...

#include "stm32wbxx.h"

Go to the source code of this file.

Data Structures

struct | LL_RCC_ClocksTypeDef
RCC Clocks Frequency Structure. More...

Defines

#define | HSE_CONTROL_UNLOCK_KEY 0xCAFECAFEU
#define | LL_RCC_CICR_LSI1RDYC RCC_CICR_LSI1RDYC
#define | LL_RCC_CICR_LSI2RDYC RCC_CICR_LSI2RDYC
#define | LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC
#define | LL_RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC
#define | LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC
#define | LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC
#define | LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC
#define | LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC
#define | LL_RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC
#define | LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC
#define | LL_RCC_CICR_CSSC RCC_CICR_CSSC
#define | LL_RCC_CIFR_LSI1RDYF RCC_CIFR_LSI1RDYF
#define | LL_RCC_CIFR_LSI2RDYF RCC_CIFR_LSI2RDYF
#define | LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF
#define | LL_RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF
#define | LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF
#define | LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF
#define | LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF
#define | LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF
#define | LL_RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF
#define | LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF
#define | LL_RCC_CIFR_CSSF RCC_CIFR_CSSF
#define | LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF
#define | LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF
#define | LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF
#define | LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF
#define | LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF
#define | LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF
#define | LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF
#define | LL_RCC_CIER_LSI1RDYIE RCC_CIER_LSI1RDYIE
#define | LL_RCC_CIER_LSI2RDYIE RCC_CIER_LSI2RDYIE
#define | LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE
#define | LL_RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE
#define | LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE
#define | LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE
#define | LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE
#define | LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE
#define | LL_RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE
#define | LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE
#define | LL_RCC_LSEDRIVE_LOW 0x00000000U
#define | LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0
#define | LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1
#define | LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV
#define | LL_RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0
#define | LL_RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1
#define | LL_RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2
#define | LL_RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3
#define | LL_RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4
#define | LL_RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5
#define | LL_RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6
#define | LL_RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7
#define | LL_RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8
#define | LL_RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9
#define | LL_RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10
#define | LL_RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11
#define | LL_RCC_HSE_CURRENTMAX_0 0x000000000U
#define | LL_RCC_HSE_CURRENTMAX_1 RCC_HSECR_HSEGMC0
#define | LL_RCC_HSE_CURRENTMAX_2 RCC_HSECR_HSEGMC1
#define | LL_RCC_HSE_CURRENTMAX_3 (RCC_HSECR_HSEGMC1|RCC_HSECR_HSEGMC0)
#define | LL_RCC_HSE_CURRENTMAX_4 RCC_HSECR_HSEGMC2
#define | LL_RCC_HSE_CURRENTMAX_5 (RCC_HSECR_HSEGMC2|RCC_HSECR_HSEGMC0)
#define | LL_RCC_HSE_CURRENTMAX_6 (RCC_HSECR_HSEGMC2|RCC_HSECR_HSEGMC1)
#define | LL_RCC_HSE_CURRENTMAX_7 (RCC_HSECR_HSEGMC2|RCC_HSECR_HSEGMC1|RCC_HSECR_HSEGMC0)
#define | LL_RCC_HSEAMPTHRESHOLD_1_2 (0x000000000U)
#define | LL_RCC_HSEAMPTHRESHOLD_3_4 RCC_HSECR_HSES
#define | LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U
#define | LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL
#define | LL_RCC_SYS_CLKSOURCE_MSI 0x00000000U
#define | LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_0
#define | LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_1
#define | LL_RCC_SYS_CLKSOURCE_PLL (RCC_CFGR_SW_1 | RCC_CFGR_SW_0)
#define | LL_RCC_SYS_CLKSOURCE_STATUS_MSI 0x00000000U
#define | LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_0
#define | LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_1
#define | LL_RCC_SYS_CLKSOURCE_STATUS_PLL (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0)
#define | LL_RCC_RF_CLKSOURCE_HSI 0x00000000U
#define | LL_RCC_RF_CLKSOURCE_HSE_DIV2 RCC_EXTCFGR_RFCSS
#define | LL_RCC_SYSCLK_DIV_1 0x00000000U
#define | LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_3
#define | LL_RCC_SYSCLK_DIV_3 RCC_CFGR_HPRE_0
#define | LL_RCC_SYSCLK_DIV_4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0)
#define | LL_RCC_SYSCLK_DIV_5 RCC_CFGR_HPRE_1
#define | LL_RCC_SYSCLK_DIV_6 (RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0)
#define | LL_RCC_SYSCLK_DIV_8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1)
#define | LL_RCC_SYSCLK_DIV_10 (RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1)
#define | LL_RCC_SYSCLK_DIV_16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0)
#define | LL_RCC_SYSCLK_DIV_32 (RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0)
#define | LL_RCC_SYSCLK_DIV_64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2)
#define | LL_RCC_SYSCLK_DIV_128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0)
#define | LL_RCC_SYSCLK_DIV_256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1)
#define | LL_RCC_SYSCLK_DIV_512 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0)
#define | LL_RCC_APB1_DIV_1 0x00000000U
#define | LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_2
#define | LL_RCC_APB1_DIV_4 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_0)
#define | LL_RCC_APB1_DIV_8 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_1)
#define | LL_RCC_APB1_DIV_16 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_1 | RCC_CFGR_PPRE1_0)
#define | LL_RCC_APB2_DIV_1 0x00000000U
#define | LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_2
#define | LL_RCC_APB2_DIV_4 (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_0)
#define | LL_RCC_APB2_DIV_8 (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_1)
#define | LL_RCC_APB2_DIV_16 (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_1 | RCC_CFGR_PPRE2_0)
#define | LL_RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U
#define | LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK
#define | LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U
#define | LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0
#define | LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1
#define | LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1)
#define | LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2
#define | LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)
#define | LL_RCC_MCO1SOURCE_LSI1 (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)
#define | LL_RCC_MCO1SOURCE_LSI2 (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)
#define | LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_3
#define | LL_RCC_MCO1SOURCE_HSI48 (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_3)
#define | LL_RCC_MCO1SOURCE_HSE_BEFORE_STAB (RCC_CFGR_MCOSEL_2|RCC_CFGR_MCOSEL_3)
#define | LL_RCC_MCO1_DIV_1 0x00000000U
#define | LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_0
#define | LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_1
#define | LL_RCC_MCO1_DIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0)
#define | LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_2
#define | LL_RCC_SMPS_CLKSOURCE_HSI 0x00000000U
#define | LL_RCC_SMPS_CLKSOURCE_MSI RCC_SMPSCR_SMPSSEL_0
#define | LL_RCC_SMPS_CLKSOURCE_HSE RCC_SMPSCR_SMPSSEL_1
#define | LL_RCC_SMPS_CLKSOURCE_STATUS_HSI 0x00000000U
#define | LL_RCC_SMPS_CLKSOURCE_STATUS_MSI RCC_SMPSCR_SMPSSWS_0
#define | LL_RCC_SMPS_CLKSOURCE_STATUS_HSE RCC_SMPSCR_SMPSSWS_1
#define | LL_RCC_SMPS_CLKSOURCE_STATUS_NO_CLOCK (RCC_SMPSCR_SMPSSWS_0|RCC_SMPSCR_SMPSSWS_1)
#define | LL_RCC_SMPS_DIV_0 (0x00000000U)
#define | LL_RCC_SMPS_DIV_1 RCC_SMPSCR_SMPSDIV_0
#define | LL_RCC_SMPS_DIV_2 RCC_SMPSCR_SMPSDIV_1
#define | LL_RCC_SMPS_DIV_3 (RCC_SMPSCR_SMPSDIV_0|RCC_SMPSCR_SMPSDIV_1)
#define | LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U
#define | LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU
#define | LL_RCC_USART1_CLKSOURCE_PCLK2 0x00000000U
#define | LL_RCC_USART1_CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0
#define | LL_RCC_USART1_CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1
#define | LL_RCC_USART1_CLKSOURCE_LSE RCC_CCIPR_USART1SEL
#define | LL_RCC_LPUART1_CLKSOURCE_PCLK1 0x00000000U
#define | LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
#define | LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
#define | LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL
#define | LL_RCC_I2C1_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (0x00000000U >> 4))
#define | LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_0 >> 4))
#define | LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_1 >> 4))
#define | LL_RCC_I2C3_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (0x00000000U >> 4))
#define | LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_0 >> 4))
#define | LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_1 >> 4))
#define | LL_RCC_LPTIM1_CLKSOURCE_PCLK1 (uint32_t)(RCC_CCIPR_LPTIM1SEL | (0x00000000U >> 16))
#define | LL_RCC_LPTIM1_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16))
#define | LL_RCC_LPTIM1_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16))
#define | LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16))
#define | LL_RCC_LPTIM2_CLKSOURCE_PCLK1 (uint32_t)(RCC_CCIPR_LPTIM2SEL | (0x00000000U >> 16))
#define | LL_RCC_LPTIM2_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16))
#define | LL_RCC_LPTIM2_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16))
#define | LL_RCC_LPTIM2_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16))
#define | LL_RCC_SAI1_CLKSOURCE_PLLSAI1 0x00000000U
#define | LL_RCC_SAI1_CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_0
#define | LL_RCC_SAI1_CLKSOURCE_HSI RCC_CCIPR_SAI1SEL_1
#define | LL_RCC_SAI1_CLKSOURCE_PIN RCC_CCIPR_SAI1SEL
#define | LL_RCC_CLK48_CLKSOURCE_HSI48 0x00000000U
#define | LL_RCC_CLK48_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
#define | LL_RCC_CLK48_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
#define | LL_RCC_CLK48_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL
#define | LL_RCC_USB_CLKSOURCE_HSI48 LL_RCC_CLK48_CLKSOURCE_HSI48
#define | LL_RCC_USB_CLKSOURCE_PLLSAI1 LL_RCC_CLK48_CLKSOURCE_PLLSAI1
#define | LL_RCC_USB_CLKSOURCE_PLL LL_RCC_CLK48_CLKSOURCE_PLL
#define | LL_RCC_USB_CLKSOURCE_MSI LL_RCC_CLK48_CLKSOURCE_MSI
#define | LL_RCC_ADC_CLKSOURCE_NONE 0x00000000U
#define | LL_RCC_ADC_CLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0
#define | LL_RCC_ADC_CLKSOURCE_PLL RCC_CCIPR_ADCSEL_1
#define | LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL
#define | LL_RCC_RNG_CLKSOURCE_CLK48 0x00000000U
#define | LL_RCC_RNG_CLKSOURCE_LSI RCC_CCIPR_RNGSEL_0
#define | LL_RCC_RNG_CLKSOURCE_LSE RCC_CCIPR_RNGSEL_1
#define | LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL
#define | LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL
#define | LL_RCC_I2C1_CLKSOURCE RCC_CCIPR_I2C1SEL
#define | LL_RCC_I2C3_CLKSOURCE RCC_CCIPR_I2C3SEL
#define | LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL
#define | LL_RCC_LPTIM2_CLKSOURCE RCC_CCIPR_LPTIM2SEL
#define | LL_RCC_SAI1_CLKSOURCE RCC_CCIPR_SAI1SEL
#define | LL_RCC_CLK48_CLKSOURCE RCC_CCIPR_CLK48SEL
#define | LL_RCC_USB_CLKSOURCE LL_RCC_CLK48_CLKSOURCE
#define | LL_RCC_RNG_CLKSOURCE RCC_CCIPR_RNGSEL
#define | LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL
#define | LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U
#define | LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0
#define | LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1
#define | LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL
#define | LL_RCC_RFWKP_CLKSOURCE_NONE 0x00000000U
#define | LL_RCC_RFWKP_CLKSOURCE_LSE RCC_CSR_RFWKPSEL_0
#define | LL_RCC_RFWKP_CLKSOURCE_LSI RCC_CSR_RFWKPSEL_1
#define | LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024 RCC_CSR_RFWKPSEL
#define | LL_RCC_PLLSOURCE_NONE 0x00000000U
#define | LL_RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_0
#define | LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_1
#define | LL_RCC_PLLSOURCE_HSE (RCC_PLLCFGR_PLLSRC_1 | RCC_PLLCFGR_PLLSRC_0)
#define | LL_RCC_PLLM_DIV_1 0x00000000U
#define | LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0)
#define | LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1)
#define | LL_RCC_PLLM_DIV_4 ((RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0))
#define | LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2)
#define | LL_RCC_PLLM_DIV_6 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0))
#define | LL_RCC_PLLM_DIV_7 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1))
#define | LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM)
#define | LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_0)
#define | LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1)
#define | LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0)
#define | LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2)
#define | LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0)
#define | LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1)
#define | LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR)
#define | LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLP_0)
#define | LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLP_1)
#define | LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1)
#define | LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLP_2)
#define | LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2)
#define | LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2)
#define | LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2)
#define | LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLP_3)
#define | LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3)
#define | LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3)
#define | LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3)
#define | LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)
#define | LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)
#define | LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)
#define | LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)
#define | LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLP_DIV_32 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)
#define | LL_RCC_PLLQ_DIV_2 (RCC_PLLCFGR_PLLQ_0)
#define | LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1)
#define | LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0)
#define | LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2)
#define | LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0)
#define | LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1)
#define | LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ)
#define | LL_RCC_PLLSAI1Q_DIV_2 (RCC_PLLSAI1CFGR_PLLQ_0)
#define | LL_RCC_PLLSAI1Q_DIV_3 (RCC_PLLSAI1CFGR_PLLQ_1)
#define | LL_RCC_PLLSAI1Q_DIV_4 (RCC_PLLSAI1CFGR_PLLQ_1 | RCC_PLLSAI1CFGR_PLLQ_0)
#define | LL_RCC_PLLSAI1Q_DIV_5 (RCC_PLLSAI1CFGR_PLLQ_2)
#define | LL_RCC_PLLSAI1Q_DIV_6 (RCC_PLLSAI1CFGR_PLLQ_2 | RCC_PLLSAI1CFGR_PLLQ_0)
#define | LL_RCC_PLLSAI1Q_DIV_7 (RCC_PLLSAI1CFGR_PLLQ_2 | RCC_PLLSAI1CFGR_PLLQ_1)
#define | LL_RCC_PLLSAI1Q_DIV_8 (RCC_PLLSAI1CFGR_PLLQ_2 | RCC_PLLSAI1CFGR_PLLQ_1 | RCC_PLLSAI1CFGR_PLLQ_0)
#define | LL_RCC_PLLSAI1P_DIV_2 (RCC_PLLSAI1CFGR_PLLP_0)
#define | LL_RCC_PLLSAI1P_DIV_3 (RCC_PLLSAI1CFGR_PLLP_1)
#define | LL_RCC_PLLSAI1P_DIV_4 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1)
#define | LL_RCC_PLLSAI1P_DIV_5 (RCC_PLLSAI1CFGR_PLLP_2)
#define | LL_RCC_PLLSAI1P_DIV_6 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2)
#define | LL_RCC_PLLSAI1P_DIV_7 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2)
#define | LL_RCC_PLLSAI1P_DIV_8 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2)
#define | LL_RCC_PLLSAI1P_DIV_9 (RCC_PLLSAI1CFGR_PLLP_3)
#define | LL_RCC_PLLSAI1P_DIV_10 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_3)
#define | LL_RCC_PLLSAI1P_DIV_11 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3)
#define | LL_RCC_PLLSAI1P_DIV_12 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3)
#define | LL_RCC_PLLSAI1P_DIV_13 (RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3)
#define | LL_RCC_PLLSAI1P_DIV_14 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3)
#define | LL_RCC_PLLSAI1P_DIV_15 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3)
#define | LL_RCC_PLLSAI1P_DIV_16 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3)
#define | LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLP_4)
#define | LL_RCC_PLLSAI1P_DIV_18 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_4)
#define | LL_RCC_PLLSAI1P_DIV_19 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_4)
#define | LL_RCC_PLLSAI1P_DIV_20 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_4)
#define | LL_RCC_PLLSAI1P_DIV_21 (RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4)
#define | LL_RCC_PLLSAI1P_DIV_22 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4)
#define | LL_RCC_PLLSAI1P_DIV_23 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4)
#define | LL_RCC_PLLSAI1P_DIV_24 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4)
#define | LL_RCC_PLLSAI1P_DIV_25 (RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)
#define | LL_RCC_PLLSAI1P_DIV_26 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)
#define | LL_RCC_PLLSAI1P_DIV_27 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)
#define | LL_RCC_PLLSAI1P_DIV_28 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)
#define | LL_RCC_PLLSAI1P_DIV_29 (RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)
#define | LL_RCC_PLLSAI1P_DIV_30 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)
#define | LL_RCC_PLLSAI1P_DIV_31 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)
#define | LL_RCC_PLLSAI1P_DIV_32 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)
#define | LL_RCC_PLLSAI1R_DIV_2 (RCC_PLLSAI1CFGR_PLLR_0)
#define | LL_RCC_PLLSAI1R_DIV_3 (RCC_PLLSAI1CFGR_PLLR_1)
#define | LL_RCC_PLLSAI1R_DIV_4 (RCC_PLLSAI1CFGR_PLLR_1 | RCC_PLLSAI1CFGR_PLLR_0)
#define | LL_RCC_PLLSAI1R_DIV_5 (RCC_PLLSAI1CFGR_PLLR_2)
#define | LL_RCC_PLLSAI1R_DIV_6 (RCC_PLLSAI1CFGR_PLLR_2 | RCC_PLLSAI1CFGR_PLLR_0)
#define | LL_RCC_PLLSAI1R_DIV_7 (RCC_PLLSAI1CFGR_PLLR_2 | RCC_PLLSAI1CFGR_PLLR_1)
#define | LL_RCC_PLLSAI1R_DIV_8 (RCC_PLLSAI1CFGR_PLLR_2 | RCC_PLLSAI1CFGR_PLLR_1 | RCC_PLLSAI1CFGR_PLLR_0)
#define | LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
Write a value in RCC register.
#define | LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
Read a value in RCC register.
#define | __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__)
Helper macro to calculate the PLLRCLK frequency on system domain.
#define | __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__)
Helper macro to calculate the PLLPCLK frequency used on SAI domain.
#define | __LL_RCC_CALC_PLLCLK_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__)
Helper macro to calculate the PLLPCLK frequency used on ADC domain.
#define | __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__)
Helper macro to calculate the PLLQCLK frequency used on 48M domain.
#define | __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__)
Helper macro to calculate the PLLSAI1PCLK frequency used for SAI domain.
#define | __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1Q__)
Helper macro to calculate the PLLSAI1QCLK frequency used on 48M domain.
#define | __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1R__)
Helper macro to calculate the PLLSAI1RCLK frequency used on ADC domain.
#define | __LL_RCC_CALC_HCLK1_FREQ(__SYSCLKFREQ__, __CPU1PRESCALER__) ((__SYSCLKFREQ__) / AHBPrescTable[((__CPU1PRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
Helper macro to calculate the HCLK1 frequency.
#define | __LL_RCC_CALC_HCLK2_FREQ(__SYSCLKFREQ__, __CPU2PRESCALER__) ((__SYSCLKFREQ__) / AHBPrescTable[((__CPU2PRESCALER__) & RCC_EXTCFGR_C2HPRE) >> RCC_EXTCFGR_C2HPRE_Pos])
Helper macro to calculate the HCLK2 frequency.
#define | __LL_RCC_CALC_HCLK4_FREQ(__SYSCLKFREQ__, __AHB4PRESCALER__) ((__SYSCLKFREQ__) / AHBPrescTable[(((__AHB4PRESCALER__) >> 4U) & RCC_EXTCFGR_SHDHPRE) >> RCC_EXTCFGR_SHDHPRE_Pos])
Helper macro to calculate the HCLK4 frequency.
#define | __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> (APBPrescTable[(((__APB1PRESCALER__) & RCC_CFGR_PPRE1_Msk) >> RCC_CFGR_PPRE1_Pos)] & 31U))
Helper macro to calculate the PCLK1 frequency (ABP1)
#define | __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> (APBPrescTable[(((__APB2PRESCALER__) & RCC_CFGR_PPRE2_Msk) >> RCC_CFGR_PPRE2_Pos)] & 31U))
Helper macro to calculate the PCLK2 frequency (ABP2)
#define | __LL_RCC_CALC_MSI_FREQ(__MSIRANGE__) MSIRangeTable[((__MSIRANGE__) & RCC_CR_MSIRANGE_Msk) >> RCC_CR_MSIRANGE_Pos]
Helper macro to calculate the MSI frequency (in Hz)

Functions

__STATIC_INLINE void | LL_RCC_HSE_EnableDiv2 (void)
Enable HSE sysclk and pll prescaler division by 2.
__STATIC_INLINE void | LL_RCC_HSE_DisableDiv2 (void)
Disable HSE sysclk and pll prescaler.
__STATIC_INLINE uint32_t | LL_RCC_HSE_IsEnabledDiv2 (void)
Get HSE sysclk and pll prescaler.
__STATIC_INLINE void | LL_RCC_HSE_EnableCSS (void)
Enable the Clock Security System.
__STATIC_INLINE void | LL_RCC_HSE_EnableBypass (void)
Enable HSE external oscillator (HSE Bypass)
__STATIC_INLINE void | LL_RCC_HSE_DisableBypass (void)
Disable HSE external oscillator (HSE Bypass)
__STATIC_INLINE void | LL_RCC_HSE_Enable (void)
Enable HSE crystal oscillator (HSE ON)
__STATIC_INLINE void | LL_RCC_HSE_Disable (void)
Disable HSE crystal oscillator (HSE ON)
__STATIC_INLINE uint32_t | LL_RCC_HSE_IsReady (void)
Check if HSE oscillator Ready.
__STATIC_INLINE uint32_t | LL_RCC_HSE_IsClockControlLocked (void)
Check if HSE clock control register is locked or not.
__STATIC_INLINE void | LL_RCC_HSE_SetCapacitorTuning (uint32_t Value)
Set HSE capacitor tuning.
__STATIC_INLINE uint32_t | LL_RCC_HSE_GetCapacitorTuning (void)
Get HSE capacitor tuning.
__STATIC_INLINE void | LL_RCC_HSE_SetCurrentControl (uint32_t CurrentMax)
Set HSE current control.
__STATIC_INLINE uint32_t | LL_RCC_HSE_GetCurrentControl (void)
Get HSE current control.
__STATIC_INLINE void | LL_RCC_HSE_SetSenseAmplifier (uint32_t SenseAmplifier)
Set HSE sense amplifier threshold.
__STATIC_INLINE uint32_t | LL_RCC_HSE_GetSenseAmplifier (void)
Get HSE current control.
__STATIC_INLINE void | LL_RCC_HSI_EnableInStopMode (void)
Enable HSI even in stop mode.
__STATIC_INLINE void | LL_RCC_HSI_DisableInStopMode (void)
Disable HSI in stop mode.
__STATIC_INLINE uint32_t | LL_RCC_HSI_IsEnabledInStopMode (void)
Check if HSI in stop mode is ready.
__STATIC_INLINE void | LL_RCC_HSI_Enable (void)
Enable HSI oscillator.
__STATIC_INLINE void | LL_RCC_HSI_Disable (void)
Disable HSI oscillator.
__STATIC_INLINE uint32_t | LL_RCC_HSI_IsReady (void)
Check if HSI clock is ready.
__STATIC_INLINE void | LL_RCC_HSI_EnableAutoFromStop (void)
Enable HSI Automatic from stop mode.
__STATIC_INLINE void | LL_RCC_HSI_DisableAutoFromStop (void)
Disable HSI Automatic from stop mode.
__STATIC_INLINE uint32_t | LL_RCC_HSI_GetCalibration (void)
Get HSI Calibration value.
__STATIC_INLINE void | LL_RCC_HSI_SetCalibTrimming (uint32_t Value)
Set HSI Calibration trimming.
__STATIC_INLINE uint32_t | LL_RCC_HSI_GetCalibTrimming (void)
Get HSI Calibration trimming.
__STATIC_INLINE void | LL_RCC_HSI48_Enable (void)
Enable HSI48.
__STATIC_INLINE void | LL_RCC_HSI48_Disable (void)
Disable HSI48.
__STATIC_INLINE uint32_t | LL_RCC_HSI48_IsReady (void)
Check if HSI48 oscillator Ready.
__STATIC_INLINE uint32_t | LL_RCC_HSI48_GetCalibration (void)
Get HSI48 Calibration value.
__STATIC_INLINE void | LL_RCC_LSE_Enable (void)
Enable Low Speed External (LSE) crystal.
__STATIC_INLINE void | LL_RCC_LSE_Disable (void)
Disable Low Speed External (LSE) crystal.
__STATIC_INLINE uint32_t | LL_RCC_LSE_IsEnabled (void)
Check if Low Speed External (LSE) crystal has been enabled or not.
__STATIC_INLINE void | LL_RCC_LSE_EnableBypass (void)
Enable external clock source (LSE bypass).
__STATIC_INLINE void | LL_RCC_LSE_DisableBypass (void)
Disable external clock source (LSE bypass).
__STATIC_INLINE void | LL_RCC_LSE_SetDriveCapability (uint32_t LSEDrive)
Set LSE oscillator drive capability.
__STATIC_INLINE uint32_t | LL_RCC_LSE_GetDriveCapability (void)
Get LSE oscillator drive capability.
__STATIC_INLINE void | LL_RCC_LSE_EnableCSS (void)
Enable Clock security system on LSE.
__STATIC_INLINE void | LL_RCC_LSE_DisableCSS (void)
Disable Clock security system on LSE.
__STATIC_INLINE uint32_t | LL_RCC_LSE_IsReady (void)
Check if LSE oscillator Ready.
__STATIC_INLINE uint32_t | LL_RCC_LSE_IsCSSDetected (void)
Check if CSS on LSE failure Detection.
__STATIC_INLINE void | LL_RCC_LSI1_Enable (void)
Enable LSI1 Oscillator.
__STATIC_INLINE void | LL_RCC_LSI1_Disable (void)
Disable LSI1 Oscillator.
__STATIC_INLINE uint32_t | LL_RCC_LSI1_IsReady (void)
Check if LSI1 is Ready.
__STATIC_INLINE void | LL_RCC_LSI2_Enable (void)
Enable LSI2 Oscillator.
__STATIC_INLINE void | LL_RCC_LSI2_Disable (void)
Disable LSI2 Oscillator.
__STATIC_INLINE uint32_t | LL_RCC_LSI2_IsReady (void)
Check if LSI2 is Ready.
__STATIC_INLINE void | LL_RCC_LSI2_SetTrimming (uint32_t Value)
Set LSI2 trimming value.
__STATIC_INLINE uint32_t | LL_RCC_LSI2_GetTrimming (void)
Get LSI2 trimming value.
__STATIC_INLINE void | LL_RCC_MSI_Enable (void)
Enable MSI oscillator.
__STATIC_INLINE void | LL_RCC_MSI_Disable (void)
Disable MSI oscillator.
__STATIC_INLINE uint32_t | LL_RCC_MSI_IsReady (void)
Check if MSI oscillator Ready.
__STATIC_INLINE void | LL_RCC_MSI_EnablePLLMode (void)
Enable MSI PLL-mode (Hardware auto calibration with LSE)
__STATIC_INLINE void | LL_RCC_MSI_DisablePLLMode (void)
Disable MSI-PLL mode.
__STATIC_INLINE void | LL_RCC_MSI_SetRange (uint32_t Range)
Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.
__STATIC_INLINE uint32_t | LL_RCC_MSI_GetRange (void)
Get the Internal Multi Speed oscillator (MSI) clock range in run mode.
__STATIC_INLINE uint32_t | LL_RCC_MSI_GetCalibration (void)
Get MSI Calibration value.
__STATIC_INLINE void | LL_RCC_MSI_SetCalibTrimming (uint32_t Value)
Set MSI Calibration trimming.
__STATIC_INLINE uint32_t | LL_RCC_MSI_GetCalibTrimming (void)
Get MSI Calibration trimming.
__STATIC_INLINE void | LL_RCC_LSCO_Enable (void)
Enable Low speed clock.
__STATIC_INLINE void | LL_RCC_LSCO_Disable (void)
Disable Low speed clock.
__STATIC_INLINE void | LL_RCC_LSCO_SetSource (uint32_t Source)
Configure Low speed clock selection.
__STATIC_INLINE uint32_t | LL_RCC_LSCO_GetSource (void)
Get Low speed clock selection.
__STATIC_INLINE void | LL_RCC_SetSysClkSource (uint32_t Source)
Configure the system clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSysClkSource (void)
Get the system clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetRFClockSource (void)
Get the RF clock source.
__STATIC_INLINE void | LL_RCC_SetRFWKPClockSource (uint32_t Source)
Set RF Wakeup Clock Source.
__STATIC_INLINE uint32_t | LL_RCC_GetRFWKPClockSource (void)
Get RF Wakeup Clock Source.
__STATIC_INLINE uint32_t | LL_RCC_IsRFUnderReset (void)
Check if Radio System is reset.
__STATIC_INLINE void | LL_RCC_SetAHBPrescaler (uint32_t Prescaler)
Set AHB prescaler.
__STATIC_INLINE void | LL_C2_RCC_SetAHBPrescaler (uint32_t Prescaler)
Set CPU2 AHB prescaler.
__STATIC_INLINE void | LL_RCC_SetAHB4Prescaler (uint32_t Prescaler)
Set AHB4 prescaler.
__STATIC_INLINE void | LL_RCC_SetAPB1Prescaler (uint32_t Prescaler)
Set APB1 prescaler.
__STATIC_INLINE void | LL_RCC_SetAPB2Prescaler (uint32_t Prescaler)
Set APB2 prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAHBPrescaler (void)
Get AHB prescaler.
__STATIC_INLINE uint32_t | LL_C2_RCC_GetAHBPrescaler (void)
Get C2 AHB prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAHB4Prescaler (void)
Get AHB4 prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAPB1Prescaler (void)
Get APB1 prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAPB2Prescaler (void)
Get APB2 prescaler.
__STATIC_INLINE void | LL_RCC_SetClkAfterWakeFromStop (uint32_t Clock)
Set Clock After Wake-Up From Stop mode.
__STATIC_INLINE uint32_t | LL_RCC_GetClkAfterWakeFromStop (void)
Get Clock After Wake-Up From Stop mode.
__STATIC_INLINE void | LL_RCC_SetSMPSClockSource (uint32_t SMPSSource)
Configure SMPS step down converter clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSMPSClockSelection (void)
Get the SMPS clock source selection.
__STATIC_INLINE uint32_t | LL_RCC_GetSMPSClockSource (void)
Get the SMPS clock source.
__STATIC_INLINE void | LL_RCC_SetSMPSPrescaler (uint32_t Prescaler)
Set SMPS prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetSMPSPrescaler (void)
Get SMPS prescaler.
__STATIC_INLINE void | LL_RCC_ConfigMCO (uint32_t MCOxSource, uint32_t MCOxPrescaler)
Configure MCOx.
__STATIC_INLINE void | LL_RCC_SetUSARTClockSource (uint32_t USARTxSource)
Configure USARTx clock source.
__STATIC_INLINE void | LL_RCC_SetLPUARTClockSource (uint32_t LPUARTxSource)
Configure LPUART1x clock source.
__STATIC_INLINE void | LL_RCC_SetI2CClockSource (uint32_t I2CxSource)
Configure I2Cx clock source.
__STATIC_INLINE void | LL_RCC_SetLPTIMClockSource (uint32_t LPTIMxSource)
Configure LPTIMx clock source.
__STATIC_INLINE void | LL_RCC_SetSAIClockSource (uint32_t SAIxSource)
Configure SAIx clock source.
__STATIC_INLINE void | LL_RCC_SetRNGClockSource (uint32_t RNGxSource)
Configure RNG clock source.
__STATIC_INLINE void | LL_RCC_SetCLK48ClockSource (uint32_t CLK48xSource)
Configure CLK48 clock source.
__STATIC_INLINE void | LL_RCC_SetUSBClockSource (uint32_t USBxSource)
Configure USB clock source.
__STATIC_INLINE void | LL_RCC_ConfigRNGClockSource (uint32_t RNGxSource, uint32_t CLK48xSource)
Configure RNG clock source.
__STATIC_INLINE void | LL_RCC_SetADCClockSource (uint32_t ADCxSource)
Configure ADC clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetUSARTClockSource (uint32_t USARTx)
Get USARTx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetLPUARTClockSource (uint32_t LPUARTx)
Get LPUARTx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetI2CClockSource (uint32_t I2Cx)
Get I2Cx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetLPTIMClockSource (uint32_t LPTIMx)
Get LPTIMx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSAIClockSource (uint32_t SAIx)
Get SAIx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetRNGClockSource (uint32_t RNGx)
Get RNGx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetCLK48ClockSource (uint32_t CLK48x)
Get CLK48x clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetUSBClockSource (uint32_t USBx)
Get USBx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetADCClockSource (uint32_t ADCx)
Get ADCx clock source.
__STATIC_INLINE void | LL_RCC_SetRTCClockSource (uint32_t Source)
Set RTC Clock Source.
__STATIC_INLINE uint32_t | LL_RCC_GetRTCClockSource (void)
Get RTC Clock Source.
__STATIC_INLINE void | LL_RCC_EnableRTC (void)
Enable RTC.
__STATIC_INLINE void | LL_RCC_DisableRTC (void)
Disable RTC.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledRTC (void)
Check if RTC has been enabled or not.
__STATIC_INLINE void | LL_RCC_ForceBackupDomainReset (void)
Force the Backup domain reset.
__STATIC_INLINE void | LL_RCC_ReleaseBackupDomainReset (void)
Release the Backup domain reset.
__STATIC_INLINE void | LL_RCC_PLL_Enable (void)
Enable PLL.
__STATIC_INLINE void | LL_RCC_PLL_Disable (void)
Disable PLL.
__STATIC_INLINE uint32_t | LL_RCC_PLL_IsReady (void)
Check if PLL Ready.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_SYS (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
Configure PLL used for SYSCLK Domain.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_SAI (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
Configure PLL used for SAI domain clock.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_ADC (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
Configure PLL used for ADC domain clock.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_48M (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
Configure PLL used for 48Mhz domain clock.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetN (void)
Get Main PLL multiplication factor for VCO.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetP (void)
Get Main PLL division factor for PLLP.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetQ (void)
Get Main PLL division factor for PLLQ.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetR (void)
Get Main PLL division factor for PLLR.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetDivider (void)
Get Division factor for the main PLL and other PLL.
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_SAI (void)
Enable PLL output mapped on SAI domain clock.
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_SAI (void)
Disable PLL output mapped on SAI domain clock.
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_ADC (void)
Enable PLL output mapped on ADC domain clock.
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_ADC (void)
Disable PLL output mapped on ADC domain clock.
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_48M (void)
Enable PLL output mapped on 48MHz domain clock.
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_48M (void)
Disable PLL output mapped on 48MHz domain clock.
__STATIC_INLINE void | LL_RCC_PLL_EnableDomain_SYS (void)
Enable PLL output mapped on SYSCLK domain.
__STATIC_INLINE void | LL_RCC_PLL_DisableDomain_SYS (void)
Disable PLL output mapped on SYSCLK domain.
__STATIC_INLINE void | LL_RCC_PLLSAI1_Enable (void)
Enable PLLSAI1.
__STATIC_INLINE void | LL_RCC_PLLSAI1_Disable (void)
Disable PLLSAI1.
__STATIC_INLINE uint32_t | LL_RCC_PLLSAI1_IsReady (void)
Check if PLLSAI1 Ready.
__STATIC_INLINE void | LL_RCC_PLLSAI1_ConfigDomain_48M (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
Configure PLLSAI1 used for 48Mhz domain clock.
__STATIC_INLINE void | LL_RCC_PLLSAI1_ConfigDomain_SAI (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
Configure PLLSAI1 used for SAI domain clock.
__STATIC_INLINE void | LL_RCC_PLLSAI1_ConfigDomain_ADC (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
Configure PLLSAI1 used for ADC domain clock.
__STATIC_INLINE uint32_t | LL_RCC_PLLSAI1_GetN (void)
Get SAI1PLL multiplication factor for VCO.
__STATIC_INLINE uint32_t | LL_RCC_PLLSAI1_GetP (void)
Get SAI1PLL division factor for PLLSAI1P.
__STATIC_INLINE uint32_t | LL_RCC_PLLSAI1_GetQ (void)
Get SAI1PLL division factor for PLLQ.
__STATIC_INLINE uint32_t | LL_RCC_PLLSAI1_GetR (void)
Get PLLSAI1 division factor for PLLSAIR.
__STATIC_INLINE void | LL_RCC_PLLSAI1_EnableDomain_SAI (void)
Enable PLLSAI1 output mapped on SAI domain clock.
__STATIC_INLINE void | LL_RCC_PLLSAI1_DisableDomain_SAI (void)
Disable PLLSAI1 output mapped on SAI domain clock.
__STATIC_INLINE void | LL_RCC_PLLSAI1_EnableDomain_48M (void)
Enable PLLSAI1 output mapped on 48MHz domain clock.
__STATIC_INLINE void | LL_RCC_PLLSAI1_DisableDomain_48M (void)
Disable PLLSAI1 output mapped on 48MHz domain clock.
__STATIC_INLINE void | LL_RCC_PLLSAI1_EnableDomain_ADC (void)
Enable PLLSAI1 output mapped on ADC domain clock.
__STATIC_INLINE void | LL_RCC_PLLSAI1_DisableDomain_ADC (void)
Disable PLLSAI1 output mapped on ADC domain clock.
__STATIC_INLINE void | LL_RCC_ClearFlag_LSI1RDY (void)
Clear LSI1 ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_LSI2RDY (void)
Clear LSI2 ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_LSERDY (void)
Clear LSE ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_MSIRDY (void)
Clear MSI ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSIRDY (void)
Clear HSI ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSERDY (void)
Clear HSE ready interrupt flag.
__STATIC_INLINE void | LL_RCC_PLL_SetMainSource (uint32_t PLLSource)
Configure PLL clock source.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetMainSource (void)
Get the oscillator used as PLL clock source.
__STATIC_INLINE void | LL_RCC_ClearFlag_PLLRDY (void)
Clear PLL ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSI48RDY (void)
Clear HSI48 ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_PLLSAI1RDY (void)
Clear PLLSAI1 ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSECSS (void)
Clear Clock security system interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_LSECSS (void)
Clear LSE Clock security system interrupt flag.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSI1RDY (void)
Check if LSI1 ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSI2RDY (void)
Check if LSI2 ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSERDY (void)
Check if LSE ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_MSIRDY (void)
Check if MSI ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSIRDY (void)
Check if HSI ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSERDY (void)
Check if HSE ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PLLRDY (void)
Check if PLL ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSI48RDY (void)
Check if HSI48 ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PLLSAI1RDY (void)
Check if PLLSAI1 ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSECSS (void)
Check if Clock security system interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSECSS (void)
Check if LSE Clock security system interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HPRE (void)
Check if HCLK1 prescaler flag value has been applied or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_C2HPRE (void)
Check if HCLK2 prescaler flag value has been applied or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_SHDHPRE (void)
Check if HCLK4 prescaler flag value has been applied or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PPRE1 (void)
Check if PLCK1 prescaler flag value has been applied or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PPRE2 (void)
Check if PLCK2 prescaler flag value has been applied or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_IWDGRST (void)
Check if RCC flag Independent Watchdog reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LPWRRST (void)
Check if RCC flag Low Power reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_OBLRST (void)
Check if RCC flag Option byte reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PINRST (void)
Check if RCC flag Pin reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_SFTRST (void)
Check if RCC flag Software reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_WWDGRST (void)
Check if RCC flag Window Watchdog reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_BORRST (void)
Check if RCC flag BOR reset is set or not.
__STATIC_INLINE void | LL_RCC_ClearResetFlags (void)
Set RMVF bit to clear the reset flags.
__STATIC_INLINE void | LL_RCC_EnableIT_LSI1RDY (void)
Enable LSI1 ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_LSI2RDY (void)
Enable LSI2 ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_LSERDY (void)
Enable LSE ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_MSIRDY (void)
Enable MSI ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_HSIRDY (void)
Enable HSI ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_HSERDY (void)
Enable HSE ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_PLLRDY (void)
Enable PLL ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_HSI48RDY (void)
Enable HSI48 ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_PLLSAI1RDY (void)
Enable PLLSAI1 ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_LSECSS (void)
Enable LSE clock security system interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_LSI1RDY (void)
Disable LSI1 ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_LSI2RDY (void)
Disable LSI2 ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_LSERDY (void)
Disable LSE ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_MSIRDY (void)
Disable MSI ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_HSIRDY (void)
Disable HSI ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_HSERDY (void)
Disable HSE ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_PLLRDY (void)
Disable PLL ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_HSI48RDY (void)
Disable HSI48 ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_PLLSAI1RDY (void)
Disable PLLSAI1 ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_LSECSS (void)
Disable LSE clock security system interrupt.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_LSI1RDY (void)
Checks if LSI1 ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_LSI2RDY (void)
Checks if LSI2 ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_LSERDY (void)
Checks if LSE ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_MSIRDY (void)
Checks if MSI ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_HSIRDY (void)
Checks if HSI ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_HSERDY (void)
Checks if HSE ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_PLLRDY (void)
Checks if PLL ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_HSI48RDY (void)
Checks if HSI48 ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_PLLSAI1RDY (void)
Checks if PLLSAI1 ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_LSECSS (void)
Checks if LSECSS interrupt source is enabled or disabled.
ErrorStatus | LL_RCC_DeInit (void)
Reset the RCC clock to the default reset state.
void | LL_RCC_GetSystemClocksFreq (LL_RCC_ClocksTypeDef *RCC_Clocks)
Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks.
uint32_t | LL_RCC_GetSMPSClockFreq (void)
Return SMPS clock frequency.
uint32_t | LL_RCC_GetUSARTClockFreq (uint32_t USARTxSource)
Return USARTx clock frequency.
uint32_t | LL_RCC_GetI2CClockFreq (uint32_t I2CxSource)
Return I2Cx clock frequency.
uint32_t | LL_RCC_GetLPUARTClockFreq (uint32_t LPUARTxSource)
Return LPUARTx clock frequency.
uint32_t | LL_RCC_GetLPTIMClockFreq (uint32_t LPTIMxSource)
Return LPTIMx clock frequency.
uint32_t | LL_RCC_GetSAIClockFreq (uint32_t SAIxSource)
Return SAIx clock frequency.
uint32_t | LL_RCC_GetCLK48ClockFreq (uint32_t CLK48xSource)
Return CLK48x clock frequency.
uint32_t | LL_RCC_GetRNGClockFreq (uint32_t RNGxSource)
Return RNGx clock frequency.
uint32_t | LL_RCC_GetUSBClockFreq (uint32_t USBxSource)
Return USBx clock frequency.
uint32_t | LL_RCC_GetADCClockFreq (uint32_t ADCxSource)
Return ADCx clock frequency.
uint32_t | LL_RCC_GetRTCClockFreq (void)
Return RTC & LCD clock frequency.
uint32_t | LL_RCC_GetRFWKPClockFreq (void)
Return RF Wakeup clock frequency.

Detailed Description

Header file of RCC LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_rcc.h.

Generated on Fri Sep 6 2019 11:34:39 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_rng.h File Reference

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stm32wbxx_ll_rng.h File Reference

Header file of RNG LL module. More...

#include "stm32wbxx.h"

Go to the source code of this file.

Data Structures

struct | LL_RNG_InitTypeDef
LL RNG Init Structure Definition. More...

Defines

#define | LL_RNG_CED_ENABLE 0x00000000U
#define | LL_RNG_CED_DISABLE RNG_CR_CED
#define | LL_RNG_SR_DRDY RNG_SR_DRDY
#define | LL_RNG_SR_CECS RNG_SR_CECS
#define | LL_RNG_SR_SECS RNG_SR_SECS
#define | LL_RNG_SR_CEIS RNG_SR_CEIS
#define | LL_RNG_SR_SEIS RNG_SR_SEIS
#define | LL_RNG_CR_IE RNG_CR_IE
#define | LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in RNG register.
#define | LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in RNG register.

Functions

__STATIC_INLINE void | LL_RNG_Enable (RNG_TypeDef *RNGx)
Enable Random Number Generation.
__STATIC_INLINE void | LL_RNG_Disable (RNG_TypeDef *RNGx)
Disable Random Number Generation.
__STATIC_INLINE uint32_t | LL_RNG_IsEnabled (RNG_TypeDef *RNGx)
Check if Random Number Generator is enabled.
__STATIC_INLINE void | LL_RNG_EnableClkErrorDetect (RNG_TypeDef *RNGx)
Enable Clock Error Detection.
__STATIC_INLINE void | LL_RNG_DisableClkErrorDetect (RNG_TypeDef *RNGx)
Disable RNG Clock Error Detection.
__STATIC_INLINE uint32_t | LL_RNG_IsEnabledClkErrorDetect (RNG_TypeDef *RNGx)
Check if RNG Clock Error Detection is enabled.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_DRDY (RNG_TypeDef *RNGx)
Indicate if the RNG Data ready Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_CECS (RNG_TypeDef *RNGx)
Indicate if the Clock Error Current Status Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_SECS (RNG_TypeDef *RNGx)
Indicate if the Seed Error Current Status Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_CEIS (RNG_TypeDef *RNGx)
Indicate if the Clock Error Interrupt Status Flag is set or not.
__STATIC_INLINE uint32_t | LL_RNG_IsActiveFlag_SEIS (RNG_TypeDef *RNGx)
Indicate if the Seed Error Interrupt Status Flag is set or not.
__STATIC_INLINE void | LL_RNG_ClearFlag_CEIS (RNG_TypeDef *RNGx)
Clear Clock Error interrupt Status (CEIS) Flag.
__STATIC_INLINE void | LL_RNG_ClearFlag_SEIS (RNG_TypeDef *RNGx)
Clear Seed Error interrupt Status (SEIS) Flag.
__STATIC_INLINE void | LL_RNG_EnableIT (RNG_TypeDef *RNGx)
Enable Random Number Generator Interrupt (applies for either Seed error, Clock Error or Data ready interrupts)
__STATIC_INLINE void | LL_RNG_DisableIT (RNG_TypeDef *RNGx)
Disable Random Number Generator Interrupt (applies for either Seed error, Clock Error or Data ready interrupts)
__STATIC_INLINE uint32_t | LL_RNG_IsEnabledIT (RNG_TypeDef *RNGx)
Check if Random Number Generator Interrupt is enabled (applies for either Seed error, Clock Error or Data ready interrupts)
__STATIC_INLINE uint32_t | LL_RNG_ReadRandData32 (RNG_TypeDef *RNGx)
Return32-bit Random Number value.
ErrorStatus | LL_RNG_Init (RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct)
Initialize RNG registers according to the specified parameters in RNG_InitStruct.
void | LL_RNG_StructInit (LL_RNG_InitTypeDef *RNG_InitStruct)
Set each LL_RNG_InitTypeDef field to default value.
ErrorStatus | LL_RNG_DeInit (RNG_TypeDef *RNGx)
De-initialize RNG registers (Registers restored to their default values).

Detailed Description

Header file of RNG LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_rng.h.

Generated on Fri Sep 6 2019 11:34:39 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_rtc.h File Reference

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Data Structures | Defines | Functions
stm32wbxx_ll_rtc.h File Reference

Header file of RTC LL module. More...

#include "stm32wbxx.h"

Go to the source code of this file.

Data Structures

struct | LL_RTC_InitTypeDef
RTC Init structures definition. More...
struct | LL_RTC_TimeTypeDef
RTC Time structure definition. More...
struct | LL_RTC_DateTypeDef
RTC Date structure definition. More...
struct | LL_RTC_AlarmTypeDef
RTC Alarm structure definition. More...

Defines

#define | RTC_WRITE_PROTECTION_DISABLE ((uint8_t)0xFFU)
#define | RTC_WRITE_PROTECTION_ENABLE_1 ((uint8_t)0xCAU)
#define | RTC_WRITE_PROTECTION_ENABLE_2 ((uint8_t)0x53U)
#define | RTC_OFFSET_WEEKDAY (uint32_t)24U
#define | RTC_OFFSET_DAY (uint32_t)16U
#define | RTC_OFFSET_MONTH (uint32_t)8U
#define | RTC_OFFSET_HOUR (uint32_t)16U
#define | RTC_OFFSET_MINUTE (uint32_t)8U
#define | LL_RTC_FORMAT_BIN 0x000000000U
#define | LL_RTC_FORMAT_BCD 0x000000001U
#define | LL_RTC_ALMA_DATEWEEKDAYSEL_DATE 0x00000000U
#define | LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL
#define | LL_RTC_ALMB_DATEWEEKDAYSEL_DATE 0x00000000U
#define | LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL
#define | LL_RTC_ISR_ITSF RTC_ISR_ITSF
#define | LL_RTC_ISR_RECALPF RTC_ISR_RECALPF
#define | LL_RTC_ISR_TAMP3F RTC_ISR_TAMP3F
#define | LL_RTC_ISR_TAMP2F RTC_ISR_TAMP2F
#define | LL_RTC_ISR_TAMP1F RTC_ISR_TAMP1F
#define | LL_RTC_ISR_TSOVF RTC_ISR_TSOVF
#define | LL_RTC_ISR_TSF RTC_ISR_TSF
#define | LL_RTC_ISR_WUTF RTC_ISR_WUTF
#define | LL_RTC_ISR_ALRBF RTC_ISR_ALRBF
#define | LL_RTC_ISR_ALRAF RTC_ISR_ALRAF
#define | LL_RTC_ISR_INITF RTC_ISR_INITF
#define | LL_RTC_ISR_RSF RTC_ISR_RSF
#define | LL_RTC_ISR_INITS RTC_ISR_INITS
#define | LL_RTC_ISR_SHPF RTC_ISR_SHPF
#define | LL_RTC_ISR_WUTWF RTC_ISR_WUTWF
#define | LL_RTC_ISR_ALRBWF RTC_ISR_ALRBWF
#define | LL_RTC_ISR_ALRAWF RTC_ISR_ALRAWF
#define | LL_RTC_CR_TSIE RTC_CR_TSIE
#define | LL_RTC_CR_WUTIE RTC_CR_WUTIE
#define | LL_RTC_CR_ALRBIE RTC_CR_ALRBIE
#define | LL_RTC_CR_ALRAIE RTC_CR_ALRAIE
#define | LL_RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE
#define | LL_RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE
#define | LL_RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE
#define | LL_RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE
#define | LL_RTC_WEEKDAY_MONDAY ((uint8_t)0x01U)
#define | LL_RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U)
#define | LL_RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U)
#define | LL_RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U)
#define | LL_RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U)
#define | LL_RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U)
#define | LL_RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U)
#define | LL_RTC_MONTH_JANUARY ((uint8_t)0x01U)
#define | LL_RTC_MONTH_FEBRUARY ((uint8_t)0x02U)
#define | LL_RTC_MONTH_MARCH ((uint8_t)0x03U)
#define | LL_RTC_MONTH_APRIL ((uint8_t)0x04U)
#define | LL_RTC_MONTH_MAY ((uint8_t)0x05U)
#define | LL_RTC_MONTH_JUNE ((uint8_t)0x06U)
#define | LL_RTC_MONTH_JULY ((uint8_t)0x07U)
#define | LL_RTC_MONTH_AUGUST ((uint8_t)0x08U)
#define | LL_RTC_MONTH_SEPTEMBER ((uint8_t)0x09U)
#define | LL_RTC_MONTH_OCTOBER ((uint8_t)0x10U)
#define | LL_RTC_MONTH_NOVEMBER ((uint8_t)0x11U)
#define | LL_RTC_MONTH_DECEMBER ((uint8_t)0x12U)
#define | LL_RTC_HOURFORMAT_24HOUR 0x00000000U
#define | LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT
#define | LL_RTC_ALARMOUT_DISABLE 0x00000000U
#define | LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0
#define | LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1
#define | LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL
#define | LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN 0x00000000U
#define | LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL RTC_OR_ALARMOUTTYPE
#define | LL_RTC_OUTPUTPOLARITY_PIN_HIGH 0x00000000U
#define | LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL
#define | LL_RTC_TIME_FORMAT_AM_OR_24 0x00000000U
#define | LL_RTC_TIME_FORMAT_PM RTC_TR_PM
#define | LL_RTC_SHIFT_SECOND_DELAY 0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */
#define | LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */
#define | LL_RTC_ALMA_MASK_NONE 0x00000000U
#define | LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define | LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3
#define | LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2
#define | LL_RTC_ALMA_MASK_SECONDS RTC_ALRMAR_MSK1
#define | LL_RTC_ALMA_MASK_ALL (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1)
#define | LL_RTC_ALMA_TIME_FORMAT_AM 0x00000000U
#define | LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM
#define | LL_RTC_ALMB_MASK_NONE 0x00000000U
#define | LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4
#define | LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3
#define | LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2
#define | LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1
#define | LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1)
#define | LL_RTC_ALMB_TIME_FORMAT_AM 0x00000000U
#define | LL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PM
#define | LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U
#define | LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE
#define | LL_RTC_TS_TIME_FORMAT_AM 0x00000000U
#define | LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM
#define | LL_RTC_TAMPER_1 RTC_TAMPCR_TAMP1E
#define | LL_RTC_TAMPER_2 RTC_TAMPCR_TAMP2E
#define | LL_RTC_TAMPER_3 RTC_TAMPCR_TAMP3E
#define | LL_RTC_TAMPER_MASK_TAMPER1 RTC_TAMPCR_TAMP1MF
#define | LL_RTC_TAMPER_MASK_TAMPER2 RTC_TAMPCR_TAMP2MF
#define | LL_RTC_TAMPER_MASK_TAMPER3 RTC_TAMPCR_TAMP3MF
#define | LL_RTC_TAMPER_NOERASE_TAMPER1 RTC_TAMPCR_TAMP1NOERASE
#define | LL_RTC_TAMPER_NOERASE_TAMPER2 RTC_TAMPCR_TAMP2NOERASE
#define | LL_RTC_TAMPER_NOERASE_TAMPER3 RTC_TAMPCR_TAMP3NOERASE
#define | LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U
#define | LL_RTC_TAMPER_DURATION_2RTCCLK RTC_TAMPCR_TAMPPRCH_0
#define | LL_RTC_TAMPER_DURATION_4RTCCLK RTC_TAMPCR_TAMPPRCH_1
#define | LL_RTC_TAMPER_DURATION_8RTCCLK RTC_TAMPCR_TAMPPRCH
#define | LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U
#define | LL_RTC_TAMPER_FILTER_2SAMPLE RTC_TAMPCR_TAMPFLT_0
#define | LL_RTC_TAMPER_FILTER_4SAMPLE RTC_TAMPCR_TAMPFLT_1
#define | LL_RTC_TAMPER_FILTER_8SAMPLE RTC_TAMPCR_TAMPFLT
#define | LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U
#define | LL_RTC_TAMPER_SAMPLFREQDIV_16384 RTC_TAMPCR_TAMPFREQ_0
#define | LL_RTC_TAMPER_SAMPLFREQDIV_8192 RTC_TAMPCR_TAMPFREQ_1
#define | LL_RTC_TAMPER_SAMPLFREQDIV_4096 (RTC_TAMPCR_TAMPFREQ_1 | RTC_TAMPCR_TAMPFREQ_0)
#define | LL_RTC_TAMPER_SAMPLFREQDIV_2048 RTC_TAMPCR_TAMPFREQ_2
#define | LL_RTC_TAMPER_SAMPLFREQDIV_1024 (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_0)
#define | LL_RTC_TAMPER_SAMPLFREQDIV_512 (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_1)
#define | LL_RTC_TAMPER_SAMPLFREQDIV_256 RTC_TAMPCR_TAMPFREQ
#define | LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 RTC_TAMPCR_TAMP1TRG
#define | LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 RTC_TAMPCR_TAMP2TRG
#define | LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 RTC_TAMPCR_TAMP3TRG
#define | LL_RTC_WAKEUPCLOCK_DIV_16 0x00000000U
#define | LL_RTC_WAKEUPCLOCK_DIV_8 (RTC_CR_WUCKSEL_0)
#define | LL_RTC_WAKEUPCLOCK_DIV_4 (RTC_CR_WUCKSEL_1)
#define | LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0)
#define | LL_RTC_WAKEUPCLOCK_CKSPRE (RTC_CR_WUCKSEL_2)
#define | LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1)
#define | LL_RTC_BKP_DR0 0x00000000U
#define | LL_RTC_BKP_DR1 0x00000001U
#define | LL_RTC_BKP_DR2 0x00000002U
#define | LL_RTC_BKP_DR3 0x00000003U
#define | LL_RTC_BKP_DR4 0x00000004U
#define | LL_RTC_BKP_DR5 0x00000005U
#define | LL_RTC_BKP_DR6 0x00000006U
#define | LL_RTC_BKP_DR7 0x00000007U
#define | LL_RTC_BKP_DR8 0x00000008U
#define | LL_RTC_BKP_DR9 0x00000009U
#define | LL_RTC_BKP_DR10 0x0000000AU
#define | LL_RTC_BKP_DR11 0x0000000BU
#define | LL_RTC_BKP_DR12 0x0000000CU
#define | LL_RTC_BKP_DR13 0x0000000DU
#define | LL_RTC_BKP_DR14 0x0000000EU
#define | LL_RTC_BKP_DR15 0x0000000FU
#define | LL_RTC_BKP_DR16 0x00000010U
#define | LL_RTC_BKP_DR17 0x00000011U
#define | LL_RTC_BKP_DR18 0x00000012U
#define | LL_RTC_BKP_DR19 0x00000013U
#define | LL_RTC_CALIB_OUTPUT_NONE 0x00000000U
#define | LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL)
#define | LL_RTC_CALIB_OUTPUT_512HZ (RTC_CR_COE)
#define | LL_RTC_CALIB_INSERTPULSE_NONE 0x00000000U
#define | LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP
#define | LL_RTC_CALIB_PERIOD_32SEC 0x00000000U
#define | LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16
#define | LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8
#define | LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in RTC register.
#define | LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in RTC register.
#define | __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))
Helper macro to convert a value from 2 digit decimal format to BCD format.
#define | __LL_RTC_CONVERT_BCD2BIN(__VALUE__) (uint8_t)((((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U ) + ((__VALUE__) & (uint8_t)0x0FU))
Helper macro to convert a value from BCD format to 2 digit decimal format.
#define | __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)
Helper macro to retrieve weekday.
#define | __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU)
Helper macro to retrieve Year in BCD format.
#define | __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)
Helper macro to retrieve Month in BCD format.
#define | __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)
Helper macro to retrieve Day in BCD format.
#define | __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)
Helper macro to retrieve hour in BCD format.
#define | __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)
Helper macro to retrieve minute in BCD format.
#define | __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU)
Helper macro to retrieve second in BCD format.

Functions

__STATIC_INLINE void | LL_RTC_SetHourFormat (RTC_TypeDef *RTCx, uint32_t HourFormat)
Set Hours format (24 hour/day or AM/PM hour format)
__STATIC_INLINE uint32_t | LL_RTC_GetHourFormat (RTC_TypeDef *RTCx)
Get Hours format (24 hour/day or AM/PM hour format)
__STATIC_INLINE void | LL_RTC_SetAlarmOutEvent (RTC_TypeDef *RTCx, uint32_t AlarmOutput)
Select the flag to be routed to RTC_ALARM output.
__STATIC_INLINE uint32_t | LL_RTC_GetAlarmOutEvent (RTC_TypeDef *RTCx)
Get the flag to be routed to RTC_ALARM output.
__STATIC_INLINE void | LL_RTC_SetAlarmOutputType (RTC_TypeDef *RTCx, uint32_t Output)
Set RTC_ALARM output type (ALARM in push-pull or open-drain output)
__STATIC_INLINE uint32_t | LL_RTC_GetAlarmOutputType (RTC_TypeDef *RTCx)
Get RTC_ALARM output type (ALARM in push-pull or open-drain output)
__STATIC_INLINE void | LL_RTC_EnableInitMode (RTC_TypeDef *RTCx)
Enable initialization mode.
__STATIC_INLINE void | LL_RTC_DisableInitMode (RTC_TypeDef *RTCx)
Disable initialization mode (Free running mode)
__STATIC_INLINE void | LL_RTC_SetOutputPolarity (RTC_TypeDef *RTCx, uint32_t Polarity)
Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted)
__STATIC_INLINE uint32_t | LL_RTC_GetOutputPolarity (RTC_TypeDef *RTCx)
Get Output polarity.
__STATIC_INLINE void | LL_RTC_EnableShadowRegBypass (RTC_TypeDef *RTCx)
Enable Bypass the shadow registers.
__STATIC_INLINE void | LL_RTC_DisableShadowRegBypass (RTC_TypeDef *RTCx)
Disable Bypass the shadow registers.
__STATIC_INLINE uint32_t | LL_RTC_IsShadowRegBypassEnabled (RTC_TypeDef *RTCx)
Check if Shadow registers bypass is enabled or not.
__STATIC_INLINE void | LL_RTC_EnableRefClock (RTC_TypeDef *RTCx)
Enable RTC_REFIN reference clock detection (50 or 60 Hz)
__STATIC_INLINE void | LL_RTC_DisableRefClock (RTC_TypeDef *RTCx)
Disable RTC_REFIN reference clock detection (50 or 60 Hz)
__STATIC_INLINE void | LL_RTC_SetAsynchPrescaler (RTC_TypeDef *RTCx, uint32_t AsynchPrescaler)
Set Asynchronous prescaler factor.
__STATIC_INLINE void | LL_RTC_SetSynchPrescaler (RTC_TypeDef *RTCx, uint32_t SynchPrescaler)
Set Synchronous prescaler factor.
__STATIC_INLINE uint32_t | LL_RTC_GetAsynchPrescaler (RTC_TypeDef *RTCx)
Get Asynchronous prescaler factor.
__STATIC_INLINE uint32_t | LL_RTC_GetSynchPrescaler (RTC_TypeDef *RTCx)
Get Synchronous prescaler factor.
__STATIC_INLINE void | LL_RTC_EnableWriteProtection (RTC_TypeDef *RTCx)
Enable the write protection for RTC registers.
__STATIC_INLINE void | LL_RTC_DisableWriteProtection (RTC_TypeDef *RTCx)
Disable the write protection for RTC registers.
__STATIC_INLINE void | LL_RTC_EnableOutRemap (RTC_TypeDef *RTCx)
Enable RTC_OUT remap.
__STATIC_INLINE void | LL_RTC_DisableOutRemap (RTC_TypeDef *RTCx)
Disable RTC_OUT remap.
__STATIC_INLINE void | LL_RTC_TIME_SetFormat (RTC_TypeDef *RTCx, uint32_t TimeFormat)
Set time format (AM/24-hour or PM notation)
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetFormat (RTC_TypeDef *RTCx)
Get time format (AM or PM notation)
__STATIC_INLINE void | LL_RTC_TIME_SetHour (RTC_TypeDef *RTCx, uint32_t Hours)
Set Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetHour (RTC_TypeDef *RTCx)
Get Hours in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_SetMinute (RTC_TypeDef *RTCx, uint32_t Minutes)
Set Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetMinute (RTC_TypeDef *RTCx)
Get Minutes in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_SetSecond (RTC_TypeDef *RTCx, uint32_t Seconds)
Set Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetSecond (RTC_TypeDef *RTCx)
Get Seconds in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_Config (RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
Set time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TIME_Get (RTC_TypeDef *RTCx)
Get time (hour, minute and second) in BCD format.
__STATIC_INLINE void | LL_RTC_TIME_EnableDayLightStore (RTC_TypeDef *RTCx)
Memorize whether the daylight saving time change has been performed.
__STATIC_INLINE void | LL_RTC_TIME_DisableDayLightStore (RTC_TypeDef *RTCx)
Disable memorization whether the daylight saving time change has been performed.
__STATIC_INLINE uint32_t | LL_RTC_TIME_IsDayLightStoreEnabled (RTC_TypeDef *RTCx)
Check if RTC Day Light Saving stored operation has been enabled or not.
__STATIC_INLINE void | LL_RTC_TIME_DecHour (RTC_TypeDef *RTCx)
Subtract 1 hour (winter time change)
__STATIC_INLINE void | LL_RTC_TIME_IncHour (RTC_TypeDef *RTCx)
Add 1 hour (summer time change)
__STATIC_INLINE uint32_t | LL_RTC_TIME_GetSubSecond (RTC_TypeDef *RTCx)
Get Sub second value in the synchronous prescaler counter.
__STATIC_INLINE void | LL_RTC_TIME_Synchronize (RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction)
Synchronize to a remote clock with a high degree of precision.
__STATIC_INLINE void | LL_RTC_DATE_SetYear (RTC_TypeDef *RTCx, uint32_t Year)
Set Year in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetYear (RTC_TypeDef *RTCx)
Get Year in BCD format.
__STATIC_INLINE void | LL_RTC_DATE_SetWeekDay (RTC_TypeDef *RTCx, uint32_t WeekDay)
Set Week day.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetWeekDay (RTC_TypeDef *RTCx)
Get Week day.
__STATIC_INLINE void | LL_RTC_DATE_SetMonth (RTC_TypeDef *RTCx, uint32_t Month)
Set Month in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetMonth (RTC_TypeDef *RTCx)
Get Month in BCD format.
__STATIC_INLINE void | LL_RTC_DATE_SetDay (RTC_TypeDef *RTCx, uint32_t Day)
Set Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_GetDay (RTC_TypeDef *RTCx)
Get Day in BCD format.
__STATIC_INLINE void | LL_RTC_DATE_Config (RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year)
Set date (WeekDay, Day, Month and Year) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_DATE_Get (RTC_TypeDef *RTCx)
Get date (WeekDay, Day, Month and Year) in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_Enable (RTC_TypeDef *RTCx)
Enable Alarm A.
__STATIC_INLINE void | LL_RTC_ALMA_Disable (RTC_TypeDef *RTCx)
Disable Alarm A.
__STATIC_INLINE void | LL_RTC_ALMA_SetMask (RTC_TypeDef *RTCx, uint32_t Mask)
Specify the Alarm A masks.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetMask (RTC_TypeDef *RTCx)
Get the Alarm A masks.
__STATIC_INLINE void | LL_RTC_ALMA_EnableWeekday (RTC_TypeDef *RTCx)
Enable AlarmA Week day selection (DU[3:0] represents the week day.
__STATIC_INLINE void | LL_RTC_ALMA_DisableWeekday (RTC_TypeDef *RTCx)
Disable AlarmA Week day selection (DU[3:0] represents the date )
__STATIC_INLINE void | LL_RTC_ALMA_SetDay (RTC_TypeDef *RTCx, uint32_t Day)
Set ALARM A Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetDay (RTC_TypeDef *RTCx)
Get ALARM A Day in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetWeekDay (RTC_TypeDef *RTCx, uint32_t WeekDay)
Set ALARM A Weekday.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetWeekDay (RTC_TypeDef *RTCx)
Get ALARM A Weekday.
__STATIC_INLINE void | LL_RTC_ALMA_SetTimeFormat (RTC_TypeDef *RTCx, uint32_t TimeFormat)
Set Alarm A time format (AM/24-hour or PM notation)
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetTimeFormat (RTC_TypeDef *RTCx)
Get Alarm A time format (AM or PM notation)
__STATIC_INLINE void | LL_RTC_ALMA_SetHour (RTC_TypeDef *RTCx, uint32_t Hours)
Set ALARM A Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetHour (RTC_TypeDef *RTCx)
Get ALARM A Hours in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetMinute (RTC_TypeDef *RTCx, uint32_t Minutes)
Set ALARM A Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetMinute (RTC_TypeDef *RTCx)
Get ALARM A Minutes in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetSecond (RTC_TypeDef *RTCx, uint32_t Seconds)
Set ALARM A Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetSecond (RTC_TypeDef *RTCx)
Get ALARM A Seconds in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_ConfigTime (RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
Set Alarm A Time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetTime (RTC_TypeDef *RTCx)
Get Alarm B Time (hour, minute and second) in BCD format.
__STATIC_INLINE void | LL_RTC_ALMA_SetSubSecondMask (RTC_TypeDef *RTCx, uint32_t Mask)
Set Alarm A Mask the most-significant bits starting at this bit.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetSubSecondMask (RTC_TypeDef *RTCx)
Get Alarm A Mask the most-significant bits starting at this bit.
__STATIC_INLINE void | LL_RTC_ALMA_SetSubSecond (RTC_TypeDef *RTCx, uint32_t Subsecond)
Set Alarm A Sub seconds value.
__STATIC_INLINE uint32_t | LL_RTC_ALMA_GetSubSecond (RTC_TypeDef *RTCx)
Get Alarm A Sub seconds value.
__STATIC_INLINE void | LL_RTC_ALMB_Enable (RTC_TypeDef *RTCx)
Enable Alarm B.
__STATIC_INLINE void | LL_RTC_ALMB_Disable (RTC_TypeDef *RTCx)
Disable Alarm B.
__STATIC_INLINE void | LL_RTC_ALMB_SetMask (RTC_TypeDef *RTCx, uint32_t Mask)
Specify the Alarm B masks.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetMask (RTC_TypeDef *RTCx)
Get the Alarm B masks.
__STATIC_INLINE void | LL_RTC_ALMB_EnableWeekday (RTC_TypeDef *RTCx)
Enable AlarmB Week day selection (DU[3:0] represents the week day.
__STATIC_INLINE void | LL_RTC_ALMB_DisableWeekday (RTC_TypeDef *RTCx)
Disable AlarmB Week day selection (DU[3:0] represents the date )
__STATIC_INLINE void | LL_RTC_ALMB_SetDay (RTC_TypeDef *RTCx, uint32_t Day)
Set ALARM B Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetDay (RTC_TypeDef *RTCx)
Get ALARM B Day in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetWeekDay (RTC_TypeDef *RTCx, uint32_t WeekDay)
Set ALARM B Weekday.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetWeekDay (RTC_TypeDef *RTCx)
Get ALARM B Weekday.
__STATIC_INLINE void | LL_RTC_ALMB_SetTimeFormat (RTC_TypeDef *RTCx, uint32_t TimeFormat)
Set ALARM B time format (AM/24-hour or PM notation)
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetTimeFormat (RTC_TypeDef *RTCx)
Get ALARM B time format (AM or PM notation)
__STATIC_INLINE void | LL_RTC_ALMB_SetHour (RTC_TypeDef *RTCx, uint32_t Hours)
Set ALARM B Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetHour (RTC_TypeDef *RTCx)
Get ALARM B Hours in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetMinute (RTC_TypeDef *RTCx, uint32_t Minutes)
Set ALARM B Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetMinute (RTC_TypeDef *RTCx)
Get ALARM B Minutes in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetSecond (RTC_TypeDef *RTCx, uint32_t Seconds)
Set ALARM B Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetSecond (RTC_TypeDef *RTCx)
Get ALARM B Seconds in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_ConfigTime (RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
Set Alarm B Time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetTime (RTC_TypeDef *RTCx)
Get Alarm B Time (hour, minute and second) in BCD format.
__STATIC_INLINE void | LL_RTC_ALMB_SetSubSecondMask (RTC_TypeDef *RTCx, uint32_t Mask)
Set Alarm B Mask the most-significant bits starting at this bit.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetSubSecondMask (RTC_TypeDef *RTCx)
Get Alarm B Mask the most-significant bits starting at this bit.
__STATIC_INLINE void | LL_RTC_ALMB_SetSubSecond (RTC_TypeDef *RTCx, uint32_t Subsecond)
Set Alarm B Sub seconds value.
__STATIC_INLINE uint32_t | LL_RTC_ALMB_GetSubSecond (RTC_TypeDef *RTCx)
Get Alarm B Sub seconds value.
__STATIC_INLINE void | LL_RTC_TS_EnableInternalEvent (RTC_TypeDef *RTCx)
Enable internal event timestamp.
__STATIC_INLINE void | LL_RTC_TS_DisableInternalEvent (RTC_TypeDef *RTCx)
Disable internal event timestamp.
__STATIC_INLINE void | LL_RTC_TS_Enable (RTC_TypeDef *RTCx)
Enable Timestamp.
__STATIC_INLINE void | LL_RTC_TS_Disable (RTC_TypeDef *RTCx)
Disable Timestamp.
__STATIC_INLINE void | LL_RTC_TS_SetActiveEdge (RTC_TypeDef *RTCx, uint32_t Edge)
Set Time-stamp event active edge.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetActiveEdge (RTC_TypeDef *RTCx)
Get Time-stamp event active edge.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetTimeFormat (RTC_TypeDef *RTCx)
Get Timestamp AM/PM notation (AM or 24-hour format)
__STATIC_INLINE uint32_t | LL_RTC_TS_GetHour (RTC_TypeDef *RTCx)
Get Timestamp Hours in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetMinute (RTC_TypeDef *RTCx)
Get Timestamp Minutes in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetSecond (RTC_TypeDef *RTCx)
Get Timestamp Seconds in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetTime (RTC_TypeDef *RTCx)
Get Timestamp time (hour, minute and second) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetWeekDay (RTC_TypeDef *RTCx)
Get Timestamp Week day.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetMonth (RTC_TypeDef *RTCx)
Get Timestamp Month in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetDay (RTC_TypeDef *RTCx)
Get Timestamp Day in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetDate (RTC_TypeDef *RTCx)
Get Timestamp date (WeekDay, Day and Month) in BCD format.
__STATIC_INLINE uint32_t | LL_RTC_TS_GetSubSecond (RTC_TypeDef *RTCx)
Get time-stamp sub second value.
__STATIC_INLINE void | LL_RTC_TS_EnableOnTamper (RTC_TypeDef *RTCx)
Activate timestamp on tamper detection event.
__STATIC_INLINE void | LL_RTC_TS_DisableOnTamper (RTC_TypeDef *RTCx)
Disable timestamp on tamper detection event.
__STATIC_INLINE void | LL_RTC_TAMPER_Enable (RTC_TypeDef *RTCx, uint32_t Tamper)
Enable RTC_TAMPx input detection.
__STATIC_INLINE void | LL_RTC_TAMPER_Disable (RTC_TypeDef *RTCx, uint32_t Tamper)
Clear RTC_TAMPx input detection.
__STATIC_INLINE void | LL_RTC_TAMPER_EnableMask (RTC_TypeDef *RTCx, uint32_t Mask)
Enable Tamper mask flag.
__STATIC_INLINE void | LL_RTC_TAMPER_DisableMask (RTC_TypeDef *RTCx, uint32_t Mask)
Disable Tamper mask flag.
__STATIC_INLINE void | LL_RTC_TAMPER_EnableEraseBKP (RTC_TypeDef *RTCx, uint32_t Tamper)
Enable backup register erase after Tamper event detection.
__STATIC_INLINE void | LL_RTC_TAMPER_DisableEraseBKP (RTC_TypeDef *RTCx, uint32_t Tamper)
Disable backup register erase after Tamper event detection.
__STATIC_INLINE void | LL_RTC_TAMPER_DisablePullUp (RTC_TypeDef *RTCx)
Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)
__STATIC_INLINE void | LL_RTC_TAMPER_EnablePullUp (RTC_TypeDef *RTCx)
Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling)
__STATIC_INLINE void | LL_RTC_TAMPER_SetPrecharge (RTC_TypeDef *RTCx, uint32_t Duration)
Set RTC_TAMPx precharge duration.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_GetPrecharge (RTC_TypeDef *RTCx)
Get RTC_TAMPx precharge duration.
__STATIC_INLINE void | LL_RTC_TAMPER_SetFilterCount (RTC_TypeDef *RTCx, uint32_t FilterCount)
Set RTC_TAMPx filter count.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_GetFilterCount (RTC_TypeDef *RTCx)
Get RTC_TAMPx filter count.
__STATIC_INLINE void | LL_RTC_TAMPER_SetSamplingFreq (RTC_TypeDef *RTCx, uint32_t SamplingFreq)
Set Tamper sampling frequency.
__STATIC_INLINE uint32_t | LL_RTC_TAMPER_GetSamplingFreq (RTC_TypeDef *RTCx)
Get Tamper sampling frequency.
__STATIC_INLINE void | LL_RTC_TAMPER_EnableActiveLevel (RTC_TypeDef *RTCx, uint32_t Tamper)
Enable Active level for Tamper input.
__STATIC_INLINE void | LL_RTC_TAMPER_DisableActiveLevel (RTC_TypeDef *RTCx, uint32_t Tamper)
Disable Active level for Tamper input.
__STATIC_INLINE void | LL_RTC_WAKEUP_Enable (RTC_TypeDef *RTCx)
Enable Wakeup timer.
__STATIC_INLINE void | LL_RTC_WAKEUP_Disable (RTC_TypeDef *RTCx)
Disable Wakeup timer.
__STATIC_INLINE uint32_t | LL_RTC_WAKEUP_IsEnabled (RTC_TypeDef *RTCx)
Check if Wakeup timer is enabled or not.
__STATIC_INLINE void | LL_RTC_WAKEUP_SetClock (RTC_TypeDef *RTCx, uint32_t WakeupClock)
Select Wakeup clock.
__STATIC_INLINE uint32_t | LL_RTC_WAKEUP_GetClock (RTC_TypeDef *RTCx)
Get Wakeup clock.
__STATIC_INLINE void | LL_RTC_WAKEUP_SetAutoReload (RTC_TypeDef *RTCx, uint32_t Value)
Set Wakeup auto-reload value.
__STATIC_INLINE uint32_t | LL_RTC_WAKEUP_GetAutoReload (RTC_TypeDef *RTCx)
Get Wakeup auto-reload value.
__STATIC_INLINE void | LL_RTC_BAK_SetRegister (RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)
Writes a data in a specified RTC Backup data register.
__STATIC_INLINE uint32_t | LL_RTC_BAK_GetRegister (RTC_TypeDef *RTCx, uint32_t BackupRegister)
Reads data from the specified RTC Backup data Register.
__STATIC_INLINE void | LL_RTC_CAL_SetOutputFreq (RTC_TypeDef *RTCx, uint32_t Frequency)
Set Calibration output frequency (1 Hz or 512 Hz)
__STATIC_INLINE uint32_t | LL_RTC_CAL_GetOutputFreq (RTC_TypeDef *RTCx)
Get Calibration output frequency (1 Hz or 512 Hz)
__STATIC_INLINE void | LL_RTC_CAL_SetPulse (RTC_TypeDef *RTCx, uint32_t Pulse)
Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm)
__STATIC_INLINE uint32_t | LL_RTC_CAL_IsPulseInserted (RTC_TypeDef *RTCx)
Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm)
__STATIC_INLINE void | LL_RTC_CAL_SetPeriod (RTC_TypeDef *RTCx, uint32_t Period)
Set the calibration cycle period.
__STATIC_INLINE uint32_t | LL_RTC_CAL_GetPeriod (RTC_TypeDef *RTCx)
Get the calibration cycle period.
__STATIC_INLINE void | LL_RTC_CAL_SetMinus (RTC_TypeDef *RTCx, uint32_t CalibMinus)
Set Calibration minus.
__STATIC_INLINE uint32_t | LL_RTC_CAL_GetMinus (RTC_TypeDef *RTCx)
Get Calibration minus.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ITS (RTC_TypeDef *RTCx)
Get Internal Time-stamp flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_RECALP (RTC_TypeDef *RTCx)
Get Recalibration pending Flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP3 (RTC_TypeDef *RTCx)
Get RTC_TAMP3 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP2 (RTC_TypeDef *RTCx)
Get RTC_TAMP2 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TAMP1 (RTC_TypeDef *RTCx)
Get RTC_TAMP1 detection flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TSOV (RTC_TypeDef *RTCx)
Get Time-stamp overflow flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_TS (RTC_TypeDef *RTCx)
Get Time-stamp flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_WUT (RTC_TypeDef *RTCx)
Get Wakeup timer flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRB (RTC_TypeDef *RTCx)
Get Alarm B flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRA (RTC_TypeDef *RTCx)
Get Alarm A flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ITS (RTC_TypeDef *RTCx)
Clear Internal Time-stamp flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TAMP3 (RTC_TypeDef *RTCx)
Clear RTC_TAMP3 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TAMP2 (RTC_TypeDef *RTCx)
Clear RTC_TAMP2 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TAMP1 (RTC_TypeDef *RTCx)
Clear RTC_TAMP1 detection flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TSOV (RTC_TypeDef *RTCx)
Clear Time-stamp overflow flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_TS (RTC_TypeDef *RTCx)
Clear Time-stamp flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_WUT (RTC_TypeDef *RTCx)
Clear Wakeup timer flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ALRB (RTC_TypeDef *RTCx)
Clear Alarm B flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_ALRA (RTC_TypeDef *RTCx)
Clear Alarm A flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_INIT (RTC_TypeDef *RTCx)
Get Initialization flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_RS (RTC_TypeDef *RTCx)
Get Registers synchronization flag.
__STATIC_INLINE void | LL_RTC_ClearFlag_RS (RTC_TypeDef *RTCx)
Clear Registers synchronization flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_INITS (RTC_TypeDef *RTCx)
Get Initialization status flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_SHP (RTC_TypeDef *RTCx)
Get Shift operation pending flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_WUTW (RTC_TypeDef *RTCx)
Get Wakeup timer write flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRBW (RTC_TypeDef *RTCx)
Get Alarm B write flag.
__STATIC_INLINE uint32_t | LL_RTC_IsActiveFlag_ALRAW (RTC_TypeDef *RTCx)
Get Alarm A write flag.
__STATIC_INLINE void | LL_RTC_EnableIT_TS (RTC_TypeDef *RTCx)
Enable Time-stamp interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TS (RTC_TypeDef *RTCx)
Disable Time-stamp interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_WUT (RTC_TypeDef *RTCx)
Enable Wakeup timer interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_WUT (RTC_TypeDef *RTCx)
Disable Wakeup timer interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ALRB (RTC_TypeDef *RTCx)
Enable Alarm B interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ALRB (RTC_TypeDef *RTCx)
Disable Alarm B interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_ALRA (RTC_TypeDef *RTCx)
Enable Alarm A interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_ALRA (RTC_TypeDef *RTCx)
Disable Alarm A interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_TAMP3 (RTC_TypeDef *RTCx)
Enable Tamper 3 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TAMP3 (RTC_TypeDef *RTCx)
Disable Tamper 3 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_TAMP2 (RTC_TypeDef *RTCx)
Enable Tamper 2 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TAMP2 (RTC_TypeDef *RTCx)
Disable Tamper 2 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_TAMP1 (RTC_TypeDef *RTCx)
Enable Tamper 1 interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TAMP1 (RTC_TypeDef *RTCx)
Disable Tamper 1 interrupt.
__STATIC_INLINE void | LL_RTC_EnableIT_TAMP (RTC_TypeDef *RTCx)
Enable all Tamper Interrupt.
__STATIC_INLINE void | LL_RTC_DisableIT_TAMP (RTC_TypeDef *RTCx)
Disable all Tamper Interrupt.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TS (RTC_TypeDef *RTCx)
Check if Time-stamp interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_WUT (RTC_TypeDef *RTCx)
Check if Wakeup timer interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ALRB (RTC_TypeDef *RTCx)
Check if Alarm B interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_ALRA (RTC_TypeDef *RTCx)
Check if Alarm A interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TAMP3 (RTC_TypeDef *RTCx)
Check if Tamper 3 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TAMP2 (RTC_TypeDef *RTCx)
Check if Tamper 2 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TAMP1 (RTC_TypeDef *RTCx)
Check if Tamper 1 interrupt is enabled or not.
__STATIC_INLINE uint32_t | LL_RTC_IsEnabledIT_TAMP (RTC_TypeDef *RTCx)
Check if all the TAMPER interrupts are enabled or not.
ErrorStatus | LL_RTC_DeInit (RTC_TypeDef *RTCx)
De-Initializes the RTC registers to their default reset values.
ErrorStatus | LL_RTC_Init (RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
Initializes the RTC registers according to the specified parameters in RTC_InitStruct.
void | LL_RTC_StructInit (LL_RTC_InitTypeDef *RTC_InitStruct)
Set each LL_RTC_InitTypeDef field to default value.
ErrorStatus | LL_RTC_TIME_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
Set the RTC current time.
void | LL_RTC_TIME_StructInit (LL_RTC_TimeTypeDef *RTC_TimeStruct)
Set each LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
ErrorStatus | LL_RTC_DATE_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct)
Set the RTC current date.
void | LL_RTC_DATE_StructInit (LL_RTC_DateTypeDef *RTC_DateStruct)
Set each LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)
ErrorStatus | LL_RTC_ALMA_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the RTC Alarm A.
ErrorStatus | LL_RTC_ALMB_Init (RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the RTC Alarm B.
void | LL_RTC_ALMA_StructInit (LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).
void | LL_RTC_ALMB_StructInit (LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
Set each LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / Day = 1st day of the month/Mask = all fields are masked).
ErrorStatus | LL_RTC_EnterInitMode (RTC_TypeDef *RTCx)
Enters the RTC Initialization mode.
ErrorStatus | LL_RTC_ExitInitMode (RTC_TypeDef *RTCx)
Exit the RTC Initialization mode.
ErrorStatus | LL_RTC_WaitForSynchro (RTC_TypeDef *RTCx)
Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

Detailed Description

Header file of RTC LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_rtc.h.

Generated on Fri Sep 6 2019 11:34:39 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_spi.h File Reference

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Data Structures | Defines | Functions
stm32wbxx_ll_spi.h File Reference

Header file of SPI LL module. More...

#include "stm32wbxx.h"

Go to the source code of this file.

Data Structures

struct | LL_SPI_InitTypeDef
SPI Init structures definition. More...

Defines

#define | LL_SPI_SR_RXNE SPI_SR_RXNE
#define | LL_SPI_SR_TXE SPI_SR_TXE
#define | LL_SPI_SR_BSY SPI_SR_BSY
#define | LL_SPI_SR_CRCERR SPI_SR_CRCERR
#define | LL_SPI_SR_MODF SPI_SR_MODF
#define | LL_SPI_SR_OVR SPI_SR_OVR
#define | LL_SPI_SR_FRE SPI_SR_FRE
#define | LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE
#define | LL_SPI_CR2_TXEIE SPI_CR2_TXEIE
#define | LL_SPI_CR2_ERRIE SPI_CR2_ERRIE
#define | LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
#define | LL_SPI_MODE_SLAVE 0x00000000U
#define | LL_SPI_PROTOCOL_MOTOROLA 0x00000000U
#define | LL_SPI_PROTOCOL_TI (SPI_CR2_FRF)
#define | LL_SPI_PHASE_1EDGE 0x00000000U
#define | LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA)
#define | LL_SPI_POLARITY_LOW 0x00000000U
#define | LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL)
#define | LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U
#define | LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1)
#define | LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2)
#define | LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
#define | LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
#define | LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST)
#define | LL_SPI_MSB_FIRST 0x00000000U
#define | LL_SPI_FULL_DUPLEX 0x00000000U
#define | LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY)
#define | LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE)
#define | LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)
#define | LL_SPI_NSS_SOFT (SPI_CR1_SSM)
#define | LL_SPI_NSS_HARD_INPUT 0x00000000U
#define | LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U))
#define | LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2)
#define | LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3)
#define | LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2)
#define | LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0)
#define | LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1)
#define | LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)
#define | LL_SPI_CRCCALCULATION_DISABLE 0x00000000U
#define | LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN)
#define | LL_SPI_CRC_8BIT 0x00000000U
#define | LL_SPI_CRC_16BIT (SPI_CR1_CRCL)
#define | LL_SPI_RX_FIFO_TH_HALF 0x00000000U
#define | LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH)
#define | LL_SPI_RX_FIFO_EMPTY 0x00000000U
#define | LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0)
#define | LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1)
#define | LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0)
#define | LL_SPI_TX_FIFO_EMPTY 0x00000000U
#define | LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0)
#define | LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1)
#define | LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0)
#define | LL_SPI_DMA_PARITY_EVEN 0x00000000U
#define | LL_SPI_DMA_PARITY_ODD 0x00000001U
#define | LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in SPI register.
#define | LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in SPI register.

Functions

__STATIC_INLINE void | LL_SPI_Enable (SPI_TypeDef *SPIx)
Enable SPI peripheral.
__STATIC_INLINE void | LL_SPI_Disable (SPI_TypeDef *SPIx)
Disable SPI peripheral.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabled (SPI_TypeDef *SPIx)
Check if SPI peripheral is enabled.
__STATIC_INLINE void | LL_SPI_SetMode (SPI_TypeDef *SPIx, uint32_t Mode)
Set SPI operation mode to Master or Slave.
__STATIC_INLINE uint32_t | LL_SPI_GetMode (SPI_TypeDef *SPIx)
Get SPI operation mode (Master or Slave)
__STATIC_INLINE void | LL_SPI_SetStandard (SPI_TypeDef *SPIx, uint32_t Standard)
Set serial protocol used.
__STATIC_INLINE uint32_t | LL_SPI_GetStandard (SPI_TypeDef *SPIx)
Get serial protocol used.
__STATIC_INLINE void | LL_SPI_SetClockPhase (SPI_TypeDef *SPIx, uint32_t ClockPhase)
Set clock phase.
__STATIC_INLINE uint32_t | LL_SPI_GetClockPhase (SPI_TypeDef *SPIx)
Get clock phase.
__STATIC_INLINE void | LL_SPI_SetClockPolarity (SPI_TypeDef *SPIx, uint32_t ClockPolarity)
Set clock polarity.
__STATIC_INLINE uint32_t | LL_SPI_GetClockPolarity (SPI_TypeDef *SPIx)
Get clock polarity.
__STATIC_INLINE void | LL_SPI_SetBaudRatePrescaler (SPI_TypeDef *SPIx, uint32_t BaudRate)
Set baud rate prescaler.
__STATIC_INLINE uint32_t | LL_SPI_GetBaudRatePrescaler (SPI_TypeDef *SPIx)
Get baud rate prescaler.
__STATIC_INLINE void | LL_SPI_SetTransferBitOrder (SPI_TypeDef *SPIx, uint32_t BitOrder)
Set transfer bit order.
__STATIC_INLINE uint32_t | LL_SPI_GetTransferBitOrder (SPI_TypeDef *SPIx)
Get transfer bit order.
__STATIC_INLINE void | LL_SPI_SetTransferDirection (SPI_TypeDef *SPIx, uint32_t TransferDirection)
Set transfer direction mode.
__STATIC_INLINE uint32_t | LL_SPI_GetTransferDirection (SPI_TypeDef *SPIx)
Get transfer direction mode.
__STATIC_INLINE void | LL_SPI_SetDataWidth (SPI_TypeDef *SPIx, uint32_t DataWidth)
Set frame data width.
__STATIC_INLINE uint32_t | LL_SPI_GetDataWidth (SPI_TypeDef *SPIx)
Get frame data width.
__STATIC_INLINE void | LL_SPI_SetRxFIFOThreshold (SPI_TypeDef *SPIx, uint32_t Threshold)
Set threshold of RXFIFO that triggers an RXNE event.
__STATIC_INLINE uint32_t | LL_SPI_GetRxFIFOThreshold (SPI_TypeDef *SPIx)
Get threshold of RXFIFO that triggers an RXNE event.
__STATIC_INLINE void | LL_SPI_EnableCRC (SPI_TypeDef *SPIx)
Enable CRC.
__STATIC_INLINE void | LL_SPI_DisableCRC (SPI_TypeDef *SPIx)
Disable CRC.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledCRC (SPI_TypeDef *SPIx)
Check if CRC is enabled.
__STATIC_INLINE void | LL_SPI_SetCRCWidth (SPI_TypeDef *SPIx, uint32_t CRCLength)
Set CRC Length.
__STATIC_INLINE uint32_t | LL_SPI_GetCRCWidth (SPI_TypeDef *SPIx)
Get CRC Length.
__STATIC_INLINE void | LL_SPI_SetCRCNext (SPI_TypeDef *SPIx)
Set CRCNext to transfer CRC on the line.
__STATIC_INLINE void | LL_SPI_SetCRCPolynomial (SPI_TypeDef *SPIx, uint32_t CRCPoly)
Set polynomial for CRC calculation.
__STATIC_INLINE uint32_t | LL_SPI_GetCRCPolynomial (SPI_TypeDef *SPIx)
Get polynomial for CRC calculation.
__STATIC_INLINE uint32_t | LL_SPI_GetRxCRC (SPI_TypeDef *SPIx)
Get Rx CRC.
__STATIC_INLINE uint32_t | LL_SPI_GetTxCRC (SPI_TypeDef *SPIx)
Get Tx CRC.
__STATIC_INLINE void | LL_SPI_SetNSSMode (SPI_TypeDef *SPIx, uint32_t NSS)
Set NSS mode.
__STATIC_INLINE uint32_t | LL_SPI_GetNSSMode (SPI_TypeDef *SPIx)
Get NSS mode.
__STATIC_INLINE void | LL_SPI_EnableNSSPulseMgt (SPI_TypeDef *SPIx)
Enable NSS pulse management.
__STATIC_INLINE void | LL_SPI_DisableNSSPulseMgt (SPI_TypeDef *SPIx)
Disable NSS pulse management.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledNSSPulse (SPI_TypeDef *SPIx)
Check if NSS pulse is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_RXNE (SPI_TypeDef *SPIx)
Check if Rx buffer is not empty.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_TXE (SPI_TypeDef *SPIx)
Check if Tx buffer is empty.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_CRCERR (SPI_TypeDef *SPIx)
Get CRC error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_MODF (SPI_TypeDef *SPIx)
Get mode fault error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_OVR (SPI_TypeDef *SPIx)
Get overrun error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_BSY (SPI_TypeDef *SPIx)
Get busy flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_FRE (SPI_TypeDef *SPIx)
Get frame format error flag.
__STATIC_INLINE uint32_t | LL_SPI_GetRxFIFOLevel (SPI_TypeDef *SPIx)
Get FIFO reception Level.
__STATIC_INLINE uint32_t | LL_SPI_GetTxFIFOLevel (SPI_TypeDef *SPIx)
Get FIFO Transmission Level.
__STATIC_INLINE void | LL_SPI_ClearFlag_CRCERR (SPI_TypeDef *SPIx)
Clear CRC error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_MODF (SPI_TypeDef *SPIx)
Clear mode fault error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_OVR (SPI_TypeDef *SPIx)
Clear overrun error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_FRE (SPI_TypeDef *SPIx)
Clear frame format error flag.
__STATIC_INLINE void | LL_SPI_EnableIT_ERR (SPI_TypeDef *SPIx)
Enable error interrupt.
__STATIC_INLINE void | LL_SPI_EnableIT_RXNE (SPI_TypeDef *SPIx)
Enable Rx buffer not empty interrupt.
__STATIC_INLINE void | LL_SPI_EnableIT_TXE (SPI_TypeDef *SPIx)
Enable Tx buffer empty interrupt.
__STATIC_INLINE void | LL_SPI_DisableIT_ERR (SPI_TypeDef *SPIx)
Disable error interrupt.
__STATIC_INLINE void | LL_SPI_DisableIT_RXNE (SPI_TypeDef *SPIx)
Disable Rx buffer not empty interrupt.
__STATIC_INLINE void | LL_SPI_DisableIT_TXE (SPI_TypeDef *SPIx)
Disable Tx buffer empty interrupt.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_ERR (SPI_TypeDef *SPIx)
Check if error interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_RXNE (SPI_TypeDef *SPIx)
Check if Rx buffer not empty interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_TXE (SPI_TypeDef *SPIx)
Check if Tx buffer empty interrupt.
__STATIC_INLINE void | LL_SPI_EnableDMAReq_RX (SPI_TypeDef *SPIx)
Enable DMA Rx.
__STATIC_INLINE void | LL_SPI_DisableDMAReq_RX (SPI_TypeDef *SPIx)
Disable DMA Rx.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledDMAReq_RX (SPI_TypeDef *SPIx)
Check if DMA Rx is enabled.
__STATIC_INLINE void | LL_SPI_EnableDMAReq_TX (SPI_TypeDef *SPIx)
Enable DMA Tx.
__STATIC_INLINE void | LL_SPI_DisableDMAReq_TX (SPI_TypeDef *SPIx)
Disable DMA Tx.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledDMAReq_TX (SPI_TypeDef *SPIx)
Check if DMA Tx is enabled.
__STATIC_INLINE void | LL_SPI_SetDMAParity_RX (SPI_TypeDef *SPIx, uint32_t Parity)
Set parity of Last DMA reception.
__STATIC_INLINE uint32_t | LL_SPI_GetDMAParity_RX (SPI_TypeDef *SPIx)
Get parity configuration for Last DMA reception.
__STATIC_INLINE void | LL_SPI_SetDMAParity_TX (SPI_TypeDef *SPIx, uint32_t Parity)
Set parity of Last DMA transmission.
__STATIC_INLINE uint32_t | LL_SPI_GetDMAParity_TX (SPI_TypeDef *SPIx)
Get parity configuration for Last DMA transmission.
__STATIC_INLINE uint32_t | LL_SPI_DMA_GetRegAddr (SPI_TypeDef *SPIx)
Get the data register address used for DMA transfer.
__STATIC_INLINE uint8_t | LL_SPI_ReceiveData8 (SPI_TypeDef *SPIx)
Read 8-Bits in the data register.
__STATIC_INLINE uint16_t | LL_SPI_ReceiveData16 (SPI_TypeDef *SPIx)
Read 16-Bits in the data register.
__STATIC_INLINE void | LL_SPI_TransmitData8 (SPI_TypeDef *SPIx, uint8_t TxData)
Write 8-Bits in the data register.
__STATIC_INLINE void | LL_SPI_TransmitData16 (SPI_TypeDef *SPIx, uint16_t TxData)
Write 16-Bits in the data register.
ErrorStatus | LL_SPI_DeInit (SPI_TypeDef *SPIx)
De-initialize the SPI registers to their default reset values.
ErrorStatus | LL_SPI_Init (SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
void | LL_SPI_StructInit (LL_SPI_InitTypeDef *SPI_InitStruct)
Set each LL_SPI_InitTypeDef field to default value.

Detailed Description

Header file of SPI LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_spi.h.

Generated on Fri Sep 6 2019 11:34:39 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_system.h File Reference

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Defines | Functions
stm32wbxx_ll_system.h File Reference

Header file of SYSTEM LL module. More...

#include "stm32wbxx.h"

Go to the source code of this file.

Defines

#define | LL_SYSCFG_REMAP_FLASH 0x00000000U
#define | LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0
#define | LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0)
#define | LL_SYSCFG_REMAP_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1)
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP
#define | LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP
#define | LL_SYSCFG_EXTI_PORTA 0U
#define | LL_SYSCFG_EXTI_PORTB 1U
#define | LL_SYSCFG_EXTI_PORTC 2U
#define | LL_SYSCFG_EXTI_PORTD 3U
#define | LL_SYSCFG_EXTI_PORTE 4U
#define | LL_SYSCFG_EXTI_PORTH 7U
#define | LL_SYSCFG_EXTI_LINE0 (uint32_t)((0x000FU << 16U) | 0U)
#define | LL_SYSCFG_EXTI_LINE1 (uint32_t)((0x00F0U << 16U) | 0U)
#define | LL_SYSCFG_EXTI_LINE2 (uint32_t)((0x0F00U << 16U) | 0U)
#define | LL_SYSCFG_EXTI_LINE3 (uint32_t)((0xF000U << 16U) | 0U)
#define | LL_SYSCFG_EXTI_LINE4 (uint32_t)((0x000FU << 16U) | 1U)
#define | LL_SYSCFG_EXTI_LINE5 (uint32_t)((0x00F0U << 16U) | 1U)
#define | LL_SYSCFG_EXTI_LINE6 (uint32_t)((0x0F00U << 16U) | 1U)
#define | LL_SYSCFG_EXTI_LINE7 (uint32_t)((0xF000U << 16U) | 1U)
#define | LL_SYSCFG_EXTI_LINE8 (uint32_t)((0x000FU << 16U) | 2U)
#define | LL_SYSCFG_EXTI_LINE9 (uint32_t)((0x00F0U << 16U) | 2U)
#define | LL_SYSCFG_EXTI_LINE10 (uint32_t)((0x0F00U << 16U) | 2U)
#define | LL_SYSCFG_EXTI_LINE11 (uint32_t)((0xF000U << 16U) | 2U)
#define | LL_SYSCFG_EXTI_LINE12 (uint32_t)((0x000FU << 16U) | 3U)
#define | LL_SYSCFG_EXTI_LINE13 (uint32_t)((0x00F0U << 16U) | 3U)
#define | LL_SYSCFG_EXTI_LINE14 (uint32_t)((0x0F00U << 16U) | 3U)
#define | LL_SYSCFG_EXTI_LINE15 (uint32_t)((0xF000U << 16U) | 3U)
#define | LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL
#define | LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL
#define | LL_SYSCFG_TIMBREAK_SRAM2_PARITY SYSCFG_CFGR2_SPL
#define | LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL
#define | LL_SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR1_PAGE0
#define | LL_SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR1_PAGE1
#define | LL_SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR1_PAGE2
#define | LL_SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR1_PAGE3
#define | LL_SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR1_PAGE4
#define | LL_SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR1_PAGE5
#define | LL_SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR1_PAGE6
#define | LL_SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR1_PAGE7
#define | LL_SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR1_PAGE8
#define | LL_SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR1_PAGE9
#define | LL_SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR1_PAGE10
#define | LL_SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR1_PAGE11
#define | LL_SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR1_PAGE12
#define | LL_SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR1_PAGE13
#define | LL_SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR1_PAGE14
#define | LL_SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR1_PAGE15
#define | LL_SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR1_PAGE16
#define | LL_SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR1_PAGE17
#define | LL_SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR1_PAGE18
#define | LL_SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR1_PAGE19
#define | LL_SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR1_PAGE20
#define | LL_SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR1_PAGE21
#define | LL_SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR1_PAGE22
#define | LL_SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR1_PAGE23
#define | LL_SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR1_PAGE24
#define | LL_SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR1_PAGE25
#define | LL_SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR1_PAGE26
#define | LL_SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR1_PAGE27
#define | LL_SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR1_PAGE28
#define | LL_SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR1_PAGE29
#define | LL_SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR1_PAGE30
#define | LL_SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR1_PAGE31
#define | LL_SYSCFG_SRAM2WRP_PAGE32 SYSCFG_SWPR2_PAGE32
#define | LL_SYSCFG_SRAM2WRP_PAGE33 SYSCFG_SWPR2_PAGE33
#define | LL_SYSCFG_SRAM2WRP_PAGE34 SYSCFG_SWPR2_PAGE34
#define | LL_SYSCFG_SRAM2WRP_PAGE35 SYSCFG_SWPR2_PAGE35
#define | LL_SYSCFG_SRAM2WRP_PAGE36 SYSCFG_SWPR2_PAGE36
#define | LL_SYSCFG_SRAM2WRP_PAGE37 SYSCFG_SWPR2_PAGE37
#define | LL_SYSCFG_SRAM2WRP_PAGE38 SYSCFG_SWPR2_PAGE38
#define | LL_SYSCFG_SRAM2WRP_PAGE39 SYSCFG_SWPR2_PAGE39
#define | LL_SYSCFG_SRAM2WRP_PAGE40 SYSCFG_SWPR2_PAGE40
#define | LL_SYSCFG_SRAM2WRP_PAGE41 SYSCFG_SWPR2_PAGE41
#define | LL_SYSCFG_SRAM2WRP_PAGE42 SYSCFG_SWPR2_PAGE42
#define | LL_SYSCFG_SRAM2WRP_PAGE43 SYSCFG_SWPR2_PAGE43
#define | LL_SYSCFG_SRAM2WRP_PAGE44 SYSCFG_SWPR2_PAGE44
#define | LL_SYSCFG_SRAM2WRP_PAGE45 SYSCFG_SWPR2_PAGE45
#define | LL_SYSCFG_SRAM2WRP_PAGE46 SYSCFG_SWPR2_PAGE46
#define | LL_SYSCFG_SRAM2WRP_PAGE47 SYSCFG_SWPR2_PAGE47
#define | LL_SYSCFG_SRAM2WRP_PAGE48 SYSCFG_SWPR2_PAGE48
#define | LL_SYSCFG_SRAM2WRP_PAGE49 SYSCFG_SWPR2_PAGE49
#define | LL_SYSCFG_SRAM2WRP_PAGE50 SYSCFG_SWPR2_PAGE50
#define | LL_SYSCFG_SRAM2WRP_PAGE51 SYSCFG_SWPR2_PAGE51
#define | LL_SYSCFG_SRAM2WRP_PAGE52 SYSCFG_SWPR2_PAGE52
#define | LL_SYSCFG_SRAM2WRP_PAGE53 SYSCFG_SWPR2_PAGE53
#define | LL_SYSCFG_SRAM2WRP_PAGE54 SYSCFG_SWPR2_PAGE54
#define | LL_SYSCFG_SRAM2WRP_PAGE55 SYSCFG_SWPR2_PAGE55
#define | LL_SYSCFG_SRAM2WRP_PAGE56 SYSCFG_SWPR2_PAGE56
#define | LL_SYSCFG_SRAM2WRP_PAGE57 SYSCFG_SWPR2_PAGE57
#define | LL_SYSCFG_SRAM2WRP_PAGE58 SYSCFG_SWPR2_PAGE58
#define | LL_SYSCFG_SRAM2WRP_PAGE59 SYSCFG_SWPR2_PAGE59
#define | LL_SYSCFG_SRAM2WRP_PAGE60 SYSCFG_SWPR2_PAGE60
#define | LL_SYSCFG_SRAM2WRP_PAGE61 SYSCFG_SWPR2_PAGE61
#define | LL_SYSCFG_SRAM2WRP_PAGE62 SYSCFG_SWPR2_PAGE62
#define | LL_SYSCFG_SRAM2WRP_PAGE63 SYSCFG_SWPR2_PAGE63
#define | LL_SYSCFG_GRP1_TIM1 SYSCFG_IMR1_TIM1IM
#define | LL_SYSCFG_GRP1_TIM16 SYSCFG_IMR1_TIM16IM
#define | LL_SYSCFG_GRP1_TIM17 SYSCFG_IMR1_TIM17IM
#define | LL_SYSCFG_GRP1_EXTI5 SYSCFG_IMR1_EXTI5IM
#define | LL_SYSCFG_GRP1_EXTI6 SYSCFG_IMR1_EXTI6IM
#define | LL_SYSCFG_GRP1_EXTI7 SYSCFG_IMR1_EXTI7IM
#define | LL_SYSCFG_GRP1_EXTI8 SYSCFG_IMR1_EXTI8IM
#define | LL_SYSCFG_GRP1_EXTI9 SYSCFG_IMR1_EXTI9IM
#define | LL_SYSCFG_GRP1_EXTI10 SYSCFG_IMR1_EXTI10IM
#define | LL_SYSCFG_GRP1_EXTI11 SYSCFG_IMR1_EXTI11IM
#define | LL_SYSCFG_GRP1_EXTI12 SYSCFG_IMR1_EXTI12IM
#define | LL_SYSCFG_GRP1_EXTI13 SYSCFG_IMR1_EXTI13IM
#define | LL_SYSCFG_GRP1_EXTI14 SYSCFG_IMR1_EXTI14IM
#define | LL_SYSCFG_GRP1_EXTI15 SYSCFG_IMR1_EXTI15IM
#define | LL_SYSCFG_GRP2_PVM1 SYSCFG_IMR2_PVM1IM
#define | LL_SYSCFG_GRP2_PVM3 SYSCFG_IMR2_PVM3IM
#define | LL_SYSCFG_GRP2_PVD SYSCFG_IMR2_PVDIM
#define | LL_C2_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS SYSCFG_C2IMR1_RTCSTAMPTAMPLSECSSIM
#define | LL_C2_SYSCFG_GRP1_RTCWKUP SYSCFG_C2IMR1_RTCWKUPIM
#define | LL_C2_SYSCFG_GRP1_RTCALARM SYSCFG_C2IMR1_RTCALARMIM
#define | LL_C2_SYSCFG_GRP1_RCC SYSCFG_C2IMR1_RCCIM
#define | LL_C2_SYSCFG_GRP1_FLASH SYSCFG_C2IMR1_FLASHIM
#define | LL_C2_SYSCFG_GRP1_PKA SYSCFG_C2IMR1_PKAIM
#define | LL_C2_SYSCFG_GRP1_RNG SYSCFG_C2IMR1_RNGIM
#define | LL_C2_SYSCFG_GRP1_AES1 SYSCFG_C2IMR1_AES1IM
#define | LL_C2_SYSCFG_GRP1_COMP SYSCFG_C2IMR1_COMPIM
#define | LL_C2_SYSCFG_GRP1_ADC SYSCFG_C2IMR1_ADCIM
#define | LL_C2_SYSCFG_GRP1_EXTI0 SYSCFG_C2IMR1_EXTI0IM
#define | LL_C2_SYSCFG_GRP1_EXTI1 SYSCFG_C2IMR1_EXTI1IM
#define | LL_C2_SYSCFG_GRP1_EXTI2 SYSCFG_C2IMR1_EXTI2IM
#define | LL_C2_SYSCFG_GRP1_EXTI3 SYSCFG_C2IMR1_EXTI3IM
#define | LL_C2_SYSCFG_GRP1_EXTI4 SYSCFG_C2IMR1_EXTI4IM
#define | LL_C2_SYSCFG_GRP1_EXTI5 SYSCFG_C2IMR1_EXTI5IM
#define | LL_C2_SYSCFG_GRP1_EXTI6 SYSCFG_C2IMR1_EXTI6IM
#define | LL_C2_SYSCFG_GRP1_EXTI7 SYSCFG_C2IMR1_EXTI7IM
#define | LL_C2_SYSCFG_GRP1_EXTI8 SYSCFG_C2IMR1_EXTI8IM
#define | LL_C2_SYSCFG_GRP1_EXTI9 SYSCFG_C2IMR1_EXTI9IM
#define | LL_C2_SYSCFG_GRP1_EXTI10 SYSCFG_C2IMR1_EXTI10IM
#define | LL_C2_SYSCFG_GRP1_EXTI11 SYSCFG_C2IMR1_EXTI11IM
#define | LL_C2_SYSCFG_GRP1_EXTI12 SYSCFG_C2IMR1_EXTI12IM
#define | LL_C2_SYSCFG_GRP1_EXTI13 SYSCFG_C2IMR1_EXTI13IM
#define | LL_C2_SYSCFG_GRP1_EXTI14 SYSCFG_C2IMR1_EXTI14IM
#define | LL_C2_SYSCFG_GRP1_EXTI15 SYSCFG_C2IMR1_EXTI15IM
#define | LL_C2_SYSCFG_GRP2_DMA1CH1 SYSCFG_C2IMR2_DMA1CH1IM
#define | LL_C2_SYSCFG_GRP2_DMA1CH2 SYSCFG_C2IMR2_DMA1CH2IM
#define | LL_C2_SYSCFG_GRP2_DMA1CH3 SYSCFG_C2IMR2_DMA1CH3IM
#define | LL_C2_SYSCFG_GRP2_DMA1CH4 SYSCFG_C2IMR2_DMA1CH4IM
#define | LL_C2_SYSCFG_GRP2_DMA1CH5 SYSCFG_C2IMR2_DMA1CH5IM
#define | LL_C2_SYSCFG_GRP2_DMA1CH6 SYSCFG_C2IMR2_DMA1CH6IM
#define | LL_C2_SYSCFG_GRP2_DMA1CH7 SYSCFG_C2IMR2_DMA1CH7IM
#define | LL_C2_SYSCFG_GRP2_DMA2CH1 SYSCFG_C2IMR2_DMA2CH1IM
#define | LL_C2_SYSCFG_GRP2_DMA2CH2 SYSCFG_C2IMR2_DMA2CH2IM
#define | LL_C2_SYSCFG_GRP2_DMA2CH3 SYSCFG_C2IMR2_DMA2CH3IM
#define | LL_C2_SYSCFG_GRP2_DMA2CH4 SYSCFG_C2IMR2_DMA2CH4IM
#define | LL_C2_SYSCFG_GRP2_DMA2CH5 SYSCFG_C2IMR2_DMA2CH5IM
#define | LL_C2_SYSCFG_GRP2_DMA2CH6 SYSCFG_C2IMR2_DMA2CH6IM
#define | LL_C2_SYSCFG_GRP2_DMA2CH7 SYSCFG_C2IMR2_DMA2CH7IM
#define | LL_C2_SYSCFG_GRP2_DMAMUX1 SYSCFG_C2IMR2_DMAMUX1IM
#define | LL_C2_SYSCFG_GRP2_PVM1 SYSCFG_C2IMR2_PVM1IM
#define | LL_C2_SYSCFG_GRP2_PVM3 SYSCFG_C2IMR2_PVM3IM
#define | LL_C2_SYSCFG_GRP2_PVD SYSCFG_C2IMR2_PVDIM
#define | LL_C2_SYSCFG_GRP2_TSC SYSCFG_C2IMR2_TSCIM
#define | LL_C2_SYSCFG_GRP2_LCD SYSCFG_C2IMR2_LCDIM
#define | LL_SYSCFG_SECURE_ACCESS_AES1 SYSCFG_SIPCR_SAES1
#define | LL_SYSCFG_SECURE_ACCESS_AES2 SYSCFG_SIPCR_SAES2
#define | LL_SYSCFG_SECURE_ACCESS_PKA SYSCFG_SIPCR_SPKA
#define | LL_SYSCFG_SECURE_ACCESS_RNG SYSCFG_SIPCR_SRNG
#define | LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP
#define | LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP
#define | LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP
#define | LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP
#define | LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP
#define | LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP
#define | LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP
#define | LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_C2APB1FZR1_DBG_TIM2_STOP
#define | LL_C2_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_C2APB1FZR1_DBG_RTC_STOP
#define | LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_C2APB1FZR1_DBG_IWDG_STOP
#define | LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_C2APB1FZR1_DBG_I2C1_STOP
#define | LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_C2APB1FZR1_DBG_I2C3_STOP
#define | LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_C2APB1FZR1_DBG_LPTIM1_STOP
#define | LL_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP
#define | LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_C2APB1FZR2_DBG_LPTIM2_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP
#define | LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_C2APB2FZR_DBG_TIM1_STOP
#define | LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_C2APB2FZR_DBG_TIM16_STOP
#define | LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_C2APB2FZR_DBG_TIM17_STOP
#define | LL_VREFBUF_VOLTAGE_SCALE0 0x00000000U
#define | LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS
#define | LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS
#define | LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS
#define | LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS
#define | LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS
#define | LL_SYSCFG_EnableSRAM2PageWRP LL_SYSCFG_EnableSRAM2PageWRP_0_31
Enable SRAM2 page write protection for Pages in range 0 to 31.

Functions

__STATIC_INLINE void | LL_SYSCFG_SetRemapMemory (uint32_t Memory)
Set memory mapping at address 0x00000000.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetRemapMemory (void)
Get memory mapping at address 0x00000000.
__STATIC_INLINE void | LL_SYSCFG_EnableAnalogBooster (void)
Enable I/O analog switch voltage booster.
__STATIC_INLINE void | LL_SYSCFG_DisableAnalogBooster (void)
Disable I/O analog switch voltage booster.
__STATIC_INLINE void | LL_SYSCFG_EnableAnalogGpioSwitch (void)
Enable the Analog GPIO switch to control voltage selection when the supply voltage is supplied by VDDA.
__STATIC_INLINE void | LL_SYSCFG_DisableAnalogGpioSwitch (void)
Disable the Analog GPIO switch to control voltage selection when the supply voltage is supplied by VDDA.
__STATIC_INLINE void | LL_SYSCFG_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the I2C fast mode plus driving capability.
__STATIC_INLINE void | LL_SYSCFG_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the I2C fast mode plus driving capability.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_IOC (void)
Enable Floating Point Unit Invalid operation Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_DZC (void)
Enable Floating Point Unit Divide-by-zero Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_UFC (void)
Enable Floating Point Unit Underflow Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_OFC (void)
Enable Floating Point Unit Overflow Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_IDC (void)
Enable Floating Point Unit Input denormal Interrupt.
__STATIC_INLINE void | LL_SYSCFG_EnableIT_FPU_IXC (void)
Enable Floating Point Unit Inexact Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_IOC (void)
Disable Floating Point Unit Invalid operation Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_DZC (void)
Disable Floating Point Unit Divide-by-zero Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_UFC (void)
Disable Floating Point Unit Underflow Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_OFC (void)
Disable Floating Point Unit Overflow Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_IDC (void)
Disable Floating Point Unit Input denormal Interrupt.
__STATIC_INLINE void | LL_SYSCFG_DisableIT_FPU_IXC (void)
Disable Floating Point Unit Inexact Interrupt.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_IOC (void)
Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_DZC (void)
Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_UFC (void)
Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_OFC (void)
Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_IDC (void)
Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledIT_FPU_IXC (void)
Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
__STATIC_INLINE void | LL_SYSCFG_SetEXTISource (uint32_t Port, uint32_t Line)
Configure source input for the EXTI external interrupt.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetEXTISource (uint32_t Line)
Get the configured defined for specific EXTI Line.
__STATIC_INLINE void | LL_SYSCFG_EnableSRAM2Erase (void)
Enable SRAM2 Erase (starts a hardware SRAM2 erase operation.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsSRAM2EraseOngoing (void)
Check if SRAM2 erase operation is on going.
__STATIC_INLINE void | LL_SYSCFG_DisableSRAMFetch (void)
Disable CPU2 SRAM fetch (execution) (This bit can be set by Firmware and will only be reset by a Hardware reset, including a reset after Standby.)
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledSRAMFetch (void)
Check if CPU2 SRAM fetch is enabled.
__STATIC_INLINE void | LL_SYSCFG_SetTIMBreakInputs (uint32_t Break)
Set connections to TIM1/16/17 Break inputs.
__STATIC_INLINE uint32_t | LL_SYSCFG_GetTIMBreakInputs (void)
Get connections to TIM1/16/17 Break inputs.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsActiveFlag_SP (void)
Check if SRAM2 parity error detected.
__STATIC_INLINE void | LL_SYSCFG_ClearFlag_SP (void)
Clear SRAM2 parity error flag.
__STATIC_INLINE void | LL_SYSCFG_EnableSRAM2PageWRP_0_31 (uint32_t SRAM2WRP)
__STATIC_INLINE void | LL_SYSCFG_EnableSRAM2PageWRP_32_63 (uint32_t SRAM2WRP)
Enable SRAM2 page write protection for Pages in range 32 to 63.
__STATIC_INLINE void | LL_SYSCFG_LockSRAM2WRP (void)
SRAM2 page write protection lock prior to erase.
__STATIC_INLINE void | LL_SYSCFG_UnlockSRAM2WRP (void)
SRAM2 page write protection unlock prior to erase.
__STATIC_INLINE void | LL_SYSCFG_GRP1_EnableIT (uint32_t Interrupt)
Enable CPU1 Interrupt Mask.
__STATIC_INLINE void | LL_SYSCFG_GRP2_EnableIT (uint32_t Interrupt)
Enable CPU1 Interrupt Mask.
__STATIC_INLINE void | LL_SYSCFG_GRP1_DisableIT (uint32_t Interrupt)
Disable CPU1 Interrupt Mask.
__STATIC_INLINE void | LL_SYSCFG_GRP2_DisableIT (uint32_t Interrupt)
Disable CPU1 Interrupt Mask.
__STATIC_INLINE uint32_t | LL_SYSCFG_GRP1_IsEnabledIT (uint32_t Interrupt)
Indicate if CPU1 Interrupt Mask is enabled.
__STATIC_INLINE uint32_t | LL_SYSCFG_GRP2_IsEnabledIT (uint32_t Interrupt)
Indicate if CPU1 Interrupt Mask is enabled.
__STATIC_INLINE void | LL_C2_SYSCFG_GRP1_EnableIT (uint32_t Interrupt)
Enable CPU2 Interrupt Mask.
__STATIC_INLINE void | LL_C2_SYSCFG_GRP2_EnableIT (uint32_t Interrupt)
Enable CPU2 Interrupt Mask.
__STATIC_INLINE void | LL_C2_SYSCFG_GRP1_DisableIT (uint32_t Interrupt)
Disable CPU2 Interrupt Mask.
__STATIC_INLINE void | LL_C2_SYSCFG_GRP2_DisableIT (uint32_t Interrupt)
Disable CPU2 Interrupt Mask.
__STATIC_INLINE uint32_t | LL_C2_SYSCFG_GRP1_IsEnabledIT (uint32_t Interrupt)
Indicate if CPU2 Interrupt Mask is enabled.
__STATIC_INLINE uint32_t | LL_C2_SYSCFG_GRP2_IsEnabledIT (uint32_t Interrupt)
Indicate if CPU2 Interrupt Mask is enabled.
__STATIC_INLINE void | LL_SYSCFG_EnableSecurityAccess (uint32_t SecurityAccess)
Enable the access for security IP.
__STATIC_INLINE void | LL_SYSCFG_DisableSecurityAccess (uint32_t SecurityAccess)
Disable the access for security IP.
__STATIC_INLINE uint32_t | LL_SYSCFG_IsEnabledSecurityAccess (uint32_t SecurityAccess)
Indicate if access for security IP is enabled.
__STATIC_INLINE uint32_t | LL_DBGMCU_GetDeviceID (void)
Return the device identifier.
__STATIC_INLINE uint32_t | LL_DBGMCU_GetRevisionID (void)
Return the device revision identifier.
__STATIC_INLINE void | LL_DBGMCU_EnableDBGSleepMode (void)
Enable the Debug Module during SLEEP mode.
__STATIC_INLINE void | LL_DBGMCU_DisableDBGSleepMode (void)
Disable the Debug Module during SLEEP mode.
__STATIC_INLINE void | LL_DBGMCU_EnableDBGStopMode (void)
Enable the Debug Module during STOP mode.
__STATIC_INLINE void | LL_DBGMCU_DisableDBGStopMode (void)
Disable the Debug Module during STOP mode.
__STATIC_INLINE void | LL_DBGMCU_EnableDBGStandbyMode (void)
Enable the Debug Module during STANDBY mode.
__STATIC_INLINE void | LL_DBGMCU_DisableDBGStandbyMode (void)
Disable the Debug Module during STANDBY mode.
__STATIC_INLINE void | LL_DBGMCU_EnableTraceClock (void)
Enable the clock for Trace port.
__STATIC_INLINE void | LL_DBGMCU_DisableTraceClock (void)
Disable the clock for Trace port.
__STATIC_INLINE uint32_t | LL_DBGMCU_IsEnabledTraceClock (void)
Indicate if the clock for Trace port is enabled.
__STATIC_INLINE void | LL_DBGMCU_EnableTriggerOutput (void)
Enable the external trigger ouput.
__STATIC_INLINE void | LL_DBGMCU_DisableTriggerOutput (void)
Disable the external trigger ouput.
__STATIC_INLINE uint32_t | LL_DBGMCU_IsEnabledTriggerOutput (void)
Indicate if the external trigger is output or input direction.
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP1_FreezePeriph (uint32_t Periphs)
Freeze CPU1 APB1 peripherals (group1 peripherals)
__STATIC_INLINE void | LL_C2_DBGMCU_APB1_GRP1_FreezePeriph (uint32_t Periphs)
Freeze CPU2 APB1 peripherals (group1 peripherals)
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP2_FreezePeriph (uint32_t Periphs)
Freeze CPU1 APB1 peripherals (group2 peripherals)
__STATIC_INLINE void | LL_C2_DBGMCU_APB1_GRP2_FreezePeriph (uint32_t Periphs)
Freeze CPU2 APB1 peripherals (group2 peripherals)
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP1_UnFreezePeriph (uint32_t Periphs)
Unfreeze CPU1 APB1 peripherals (group1 peripherals)
__STATIC_INLINE void | LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph (uint32_t Periphs)
Unfreeze CPU2 APB1 peripherals (group1 peripherals)
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP2_UnFreezePeriph (uint32_t Periphs)
Unfreeze CPU1 APB1 peripherals (group2 peripherals)
__STATIC_INLINE void | LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph (uint32_t Periphs)
Unfreeze CPU2 APB1 peripherals (group2 peripherals)
__STATIC_INLINE void | LL_DBGMCU_APB2_GRP1_FreezePeriph (uint32_t Periphs)
Freeze CPU1 APB2 peripherals.
__STATIC_INLINE void | LL_C2_DBGMCU_APB2_GRP1_FreezePeriph (uint32_t Periphs)
Freeze CPU2 APB2 peripherals.
__STATIC_INLINE void | LL_DBGMCU_APB2_GRP1_UnFreezePeriph (uint32_t Periphs)
Unfreeze CPU1 APB2 peripherals.
__STATIC_INLINE void | LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph (uint32_t Periphs)
Unfreeze CPU2 APB2 peripherals.
__STATIC_INLINE void | LL_VREFBUF_Enable (void)
Enable Internal voltage reference.
__STATIC_INLINE void | LL_VREFBUF_Disable (void)
Disable Internal voltage reference.
__STATIC_INLINE void | LL_VREFBUF_EnableHIZ (void)
Enable high impedance (VREF+pin is high impedance)
__STATIC_INLINE void | LL_VREFBUF_DisableHIZ (void)
Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
__STATIC_INLINE void | LL_VREFBUF_SetVoltageScaling (uint32_t Scale)
Set the Voltage reference scale.
__STATIC_INLINE uint32_t | LL_VREFBUF_GetVoltageScaling (void)
Get the Voltage reference scale.
__STATIC_INLINE uint32_t | LL_VREFBUF_IsVREFReady (void)
Check if Voltage reference buffer is ready.
__STATIC_INLINE uint32_t | LL_VREFBUF_GetTrimming (void)
Get the trimming code for VREFBUF calibration.
__STATIC_INLINE void | LL_VREFBUF_SetTrimming (uint32_t Value)
Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)
__STATIC_INLINE void | LL_FLASH_SetLatency (uint32_t Latency)
Set FLASH Latency.
__STATIC_INLINE uint32_t | LL_FLASH_GetLatency (void)
Get FLASH Latency.
__STATIC_INLINE void | LL_FLASH_EnablePrefetch (void)
Enable Prefetch.
__STATIC_INLINE void | LL_FLASH_DisablePrefetch (void)
Disable Prefetch.
__STATIC_INLINE uint32_t | LL_FLASH_IsPrefetchEnabled (void)
Check if Prefetch buffer is enabled.
__STATIC_INLINE void | LL_FLASH_EnableInstCache (void)
Enable Instruction cache.
__STATIC_INLINE void | LL_FLASH_DisableInstCache (void)
Disable Instruction cache.
__STATIC_INLINE void | LL_FLASH_EnableDataCache (void)
Enable Data cache.
__STATIC_INLINE void | LL_FLASH_DisableDataCache (void)
Disable Data cache.
__STATIC_INLINE void | LL_FLASH_EnableInstCacheReset (void)
Enable Instruction cache reset.
__STATIC_INLINE void | LL_FLASH_DisableInstCacheReset (void)
Disable Instruction cache reset.
__STATIC_INLINE void | LL_FLASH_EnableDataCacheReset (void)
Enable Data cache reset.
__STATIC_INLINE void | LL_FLASH_DisableDataCacheReset (void)
Disable Data cache reset.
__STATIC_INLINE void | LL_FLASH_SuspendOperation (void)
Suspend new program or erase operation request.
__STATIC_INLINE void | LL_FLASH_AllowOperation (void)
Allow new program or erase operation request.
__STATIC_INLINE uint32_t | LL_FLASH_IsOperationSuspended (void)
Check if new program or erase operation request from CPU2 is suspended.
__STATIC_INLINE uint32_t | LL_FLASH_IsActiveFlag_OperationSuspended (void)
Check if new program or erase operation request from CPU1 or CPU2 is suspended.
__STATIC_INLINE void | LL_FLASH_SetEmptyFlag (void)
Set EMPTY flag information as Flash User area empty.
__STATIC_INLINE void | LL_FLASH_ClearEmptyFlag (void)
Clear EMPTY flag information as Flash User area programmed.
__STATIC_INLINE uint32_t | LL_FLASH_IsEmptyFlag (void)
Check if the EMPTY flag is set or reset.
__STATIC_INLINE uint32_t | LL_FLASH_GetIPCCBufferAddr (void)
Get IPCC buffer base address.
__STATIC_INLINE uint32_t | LL_FLASH_GetC2BootResetVect (void)
Get CPU2 boot reset vector.
__STATIC_INLINE uint32_t | LL_FLASH_GetUDN (void)
Return the Unique Device Number.
__STATIC_INLINE uint32_t | LL_FLASH_GetDeviceID (void)
Return the Device ID.
__STATIC_INLINE uint32_t | LL_FLASH_GetSTCompanyID (void)
Return the ST Company ID.

Detailed Description

Header file of SYSTEM LL module.

Author:
MCD Application Team
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The LL SYSTEM driver contains a set of generic APIs that can be
    used by user:
      (+) Some of the FLASH features need to be handled in the SYSTEM file.
      (+) Access to DBGCMU registers
      (+) Access to SYSCFG registers
      (+) Access to VREFBUF registers
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_system.h.

Generated on Fri Sep 6 2019 11:34:39 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_tim.h File Reference

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Data Structures | Defines | Functions | Variables
stm32wbxx_ll_tim.h File Reference

Header file of TIM LL module. More...

#include "stm32wbxx.h"

Go to the source code of this file.

Data Structures

struct | LL_TIM_InitTypeDef
TIM Time Base configuration structure definition. More...
struct | LL_TIM_OC_InitTypeDef
TIM Output Compare configuration structure definition. More...
struct | LL_TIM_IC_InitTypeDef
TIM Input Capture configuration structure definition. More...
struct | LL_TIM_ENCODER_InitTypeDef
TIM Encoder interface configuration structure definition. More...
struct | LL_TIM_HALLSENSOR_InitTypeDef
TIM Hall sensor interface configuration structure definition. More...
struct | LL_TIM_BDTR_InitTypeDef
BDTR (Break and Dead Time) structure definition. More...

Defines

#define | TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
#define | TIMx_AF1_BKINE TIM1_AF1_BKINE
#define | TIMx_AF1_BKCOMP1E TIM1_AF1_BKCMP1E
#define | TIMx_AF1_BKCOMP2E TIM1_AF1_BKCMP2E
#define | TIMx_AF1_BKINP TIM1_AF1_BKINP
#define | TIMx_AF1_BKCOMP1P TIM1_AF1_BKCMP1P
#define | TIMx_AF1_BKCOMP2P TIM1_AF1_BKCMP2P
#define | TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL
#define | TIMx_AF2_BK2INE TIM1_AF2_BK2INE
#define | TIMx_AF2_BK2COMP1E TIM1_AF2_BK2CMP1E
#define | TIMx_AF2_BK2COMP2E TIM1_AF2_BK2CMP2E
#define | TIMx_AF2_BK2INP TIM1_AF2_BK2INP
#define | TIMx_AF2_BK2COMP1P TIM1_AF2_BK2CMP1P
#define | TIMx_AF2_BK2COMP2P TIM1_AF2_BK2CMP2P
#define | TIMx_OR_RMP_SHIFT 16U
#define | TIMx_OR_RMP_MASK 0x0000FFFFU
#define | TIM1_OR_RMP_MASK ((TIM1_OR_ETR_ADC1_RMP | TIM1_OR_TI1_RMP) << TIMx_OR_RMP_SHIFT)
#define | TIM2_OR_RMP_MASK ((TIM2_OR_TI4_RMP | TIM2_OR_ETR_RMP | TIM2_OR_ITR1_RMP) << TIMx_OR_RMP_SHIFT)
#define | TIM16_OR_RMP_MASK (TIM16_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
#define | TIM17_OR_RMP_MASK (TIM17_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
#define | DT_DELAY_1 ((uint8_t)0x7F)
#define | DT_DELAY_2 ((uint8_t)0x3F)
#define | DT_DELAY_3 ((uint8_t)0x1F)
#define | DT_DELAY_4 ((uint8_t)0x1F)
#define | DT_RANGE_1 ((uint8_t)0x00)
#define | DT_RANGE_2 ((uint8_t)0x80)
#define | DT_RANGE_3 ((uint8_t)0xC0)
#define | DT_RANGE_4 ((uint8_t)0xE0)
#define | TIM_GET_CHANNEL_INDEX(__CHANNEL__)
Convert channel id into channel index.
#define | TIM_CALC_DTS(__TIMCLK__, __CKD__)
Calculate the deadtime sampling period(in ps).
#define | LL_TIM_SR_UIF TIM_SR_UIF
#define | LL_TIM_SR_CC1IF TIM_SR_CC1IF
#define | LL_TIM_SR_CC2IF TIM_SR_CC2IF
#define | LL_TIM_SR_CC3IF TIM_SR_CC3IF
#define | LL_TIM_SR_CC4IF TIM_SR_CC4IF
#define | LL_TIM_SR_CC5IF TIM_SR_CC5IF
#define | LL_TIM_SR_CC6IF TIM_SR_CC6IF
#define | LL_TIM_SR_COMIF TIM_SR_COMIF
#define | LL_TIM_SR_TIF TIM_SR_TIF
#define | LL_TIM_SR_BIF TIM_SR_BIF
#define | LL_TIM_SR_B2IF TIM_SR_B2IF
#define | LL_TIM_SR_CC1OF TIM_SR_CC1OF
#define | LL_TIM_SR_CC2OF TIM_SR_CC2OF
#define | LL_TIM_SR_CC3OF TIM_SR_CC3OF
#define | LL_TIM_SR_CC4OF TIM_SR_CC4OF
#define | LL_TIM_SR_SBIF TIM_SR_SBIF
#define | LL_TIM_BREAK_DISABLE 0x00000000U
#define | LL_TIM_BREAK_ENABLE TIM_BDTR_BKE
#define | LL_TIM_BREAK2_DISABLE 0x00000000U
#define | LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E
#define | LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U
#define | LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE
#define | LL_TIM_DIER_UIE TIM_DIER_UIE
#define | LL_TIM_DIER_CC1IE TIM_DIER_CC1IE
#define | LL_TIM_DIER_CC2IE TIM_DIER_CC2IE
#define | LL_TIM_DIER_CC3IE TIM_DIER_CC3IE
#define | LL_TIM_DIER_CC4IE TIM_DIER_CC4IE
#define | LL_TIM_DIER_COMIE TIM_DIER_COMIE
#define | LL_TIM_DIER_TIE TIM_DIER_TIE
#define | LL_TIM_DIER_BIE TIM_DIER_BIE
#define | LL_TIM_UPDATESOURCE_REGULAR 0x00000000U
#define | LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS
#define | LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM
#define | LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U
#define | LL_TIM_COUNTERMODE_UP 0x00000000U
#define | LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define | LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0
#define | LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1
#define | LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS
#define | LL_TIM_CLOCKDIVISION_DIV1 0x00000000U
#define | LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0
#define | LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1
#define | LL_TIM_COUNTERDIRECTION_UP 0x00000000U
#define | LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR
#define | LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U
#define | LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS
#define | LL_TIM_CCDMAREQUEST_CC 0x00000000U
#define | LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS
#define | LL_TIM_LOCKLEVEL_OFF 0x00000000U
#define | LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0
#define | LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1
#define | LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK
#define | LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E
#define | LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE
#define | LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E
#define | LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE
#define | LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E
#define | LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE
#define | LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E
#define | LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E
#define | LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E
#define | LL_TIM_OCSTATE_DISABLE 0x00000000U
#define | LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E
#define | LL_TIM_OCMODE_FROZEN 0x00000000U
#define | LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0
#define | LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1
#define | LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2
#define | LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
#define | LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3
#define | LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
#define | LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
#define | LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
#define | LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)
#define | LL_TIM_OCPOLARITY_HIGH 0x00000000U
#define | LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P
#define | LL_TIM_OCIDLESTATE_LOW 0x00000000U
#define | LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1
#define | LL_TIM_GROUPCH5_NONE 0x00000000U
#define | LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1
#define | LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2
#define | LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3
#define | LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U)
#define | LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U)
#define | LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U)
#define | LL_TIM_ICPSC_DIV1 0x00000000U
#define | LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U)
#define | LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U)
#define | LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U)
#define | LL_TIM_IC_FILTER_FDIV1 0x00000000U
#define | LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U)
#define | LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U)
#define | LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U)
#define | LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U)
#define | LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U)
#define | LL_TIM_IC_POLARITY_RISING 0x00000000U
#define | LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P
#define | LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)
#define | LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U
#define | LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE
#define | LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0
#define | LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1
#define | LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | LL_TIM_TRGO_RESET 0x00000000U
#define | LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0
#define | LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1
#define | LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
#define | LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2
#define | LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)
#define | LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)
#define | LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
#define | LL_TIM_TRGO2_RESET 0x00000000U
#define | LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0
#define | LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1
#define | LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2
#define | LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)
#define | LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3
#define | LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)
#define | LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)
#define | LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
#define | LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)
#define | LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
#define | LL_TIM_SLAVEMODE_DISABLED 0x00000000U
#define | LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2
#define | LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)
#define | LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)
#define | LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3
#define | LL_TIM_TS_ITR0 0x00000000U
#define | LL_TIM_TS_ITR1 TIM_SMCR_TS_0
#define | LL_TIM_TS_ITR2 TIM_SMCR_TS_1
#define | LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
#define | LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2
#define | LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)
#define | LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)
#define | LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)
#define | LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U
#define | LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP
#define | LL_TIM_ETR_PRESCALER_DIV1 0x00000000U
#define | LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0
#define | LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1
#define | LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS
#define | LL_TIM_ETR_FILTER_FDIV1 0x00000000U
#define | LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0
#define | LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1
#define | LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2
#define | LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)
#define | LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3
#define | LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)
#define | LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)
#define | LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)
#define | LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF
#define | LL_TIM_ETRSOURCE_LEGACY 0x00000000U
#define | LL_TIM_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0
#define | LL_TIM_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1
#define | LL_TIM_ETRSOURCE_GPIO LL_TIM_ETRSOURCE_LEGACY
#define | LL_TIM_ETRSOURCE_ADC1_AWD1 LL_TIM_ETRSOURCE_LEGACY
#define | LL_TIM_ETRSOURCE_ADC1_AWD2 LL_TIM_ETRSOURCE_LEGACY
#define | LL_TIM_ETRSOURCE_ADC1_AWD3 LL_TIM_ETRSOURCE_LEGACY
#define | LL_TIM_BREAK_POLARITY_LOW 0x00000000U
#define | LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP
#define | LL_TIM_BREAK_FILTER_FDIV1 0x00000000U
#define | LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U
#define | LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U
#define | LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U
#define | LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U
#define | LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U
#define | LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U
#define | LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U
#define | LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U
#define | LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U
#define | LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U
#define | LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U
#define | LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U
#define | LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U
#define | LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U
#define | LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U
#define | LL_TIM_BREAK2_POLARITY_LOW 0x00000000U
#define | LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P
#define | LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U
#define | LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U
#define | LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U
#define | LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U
#define | LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U
#define | LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U
#define | LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U
#define | LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U
#define | LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U
#define | LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U
#define | LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U
#define | LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U
#define | LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U
#define | LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U
#define | LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U
#define | LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U
#define | LL_TIM_OSSI_DISABLE 0x00000000U
#define | LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI
#define | LL_TIM_OSSR_DISABLE 0x00000000U
#define | LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR
#define | LL_TIM_BREAK_INPUT_BKIN 0x00000000U
#define | LL_TIM_BREAK_INPUT_BKIN2 0x00000004U
#define | LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE
#define | LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_AF1_BKCMP1E
#define | LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_AF1_BKCMP2E
#define | LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP
#define | LL_TIM_BKIN_POLARITY_HIGH 0x00000000U
#define | LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U
#define | LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0
#define | LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1
#define | LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2
#define | LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3
#define | LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)
#define | LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4
#define | LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2)
#define | LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3)
#define | LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U
#define | LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0
#define | LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1
#define | LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2
#define | LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3
#define | LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)
#define | LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4
#define | LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0)
#define | LL_TIM_TIM1_ETR_ADC1_RMP_NC TIM1_OR_RMP_MASK
#define | LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (TIM1_OR_ETR_ADC1_RMP_0 | TIM1_OR_RMP_MASK)
#define | LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (TIM1_OR_ETR_ADC1_RMP_1 | TIM1_OR_RMP_MASK)
#define | LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (TIM1_OR_ETR_ADC1_RMP | TIM1_OR_RMP_MASK)
#define | LL_TIM_TIM1_TI1_RMP_GPIO TIM1_OR_RMP_MASK
#define | LL_TIM_TIM1_TI1_RMP_COMP1 (TIM1_OR_TI1_RMP | TIM1_OR_RMP_MASK)
#define | LL_TIM_TIM2_ITR1_RMP_NONE TIM2_OR_RMP_MASK /* !< No internal trigger on TIM2_ITR1 */
#define | LL_TIM_TIM2_ITR1_RMP_USB_SOF (TIM2_OR_ITR1_RMP) /* !< TIM2_ITR1 is connected to USB SOF */
#define | LL_TIM_TIM2_ETR_RMP_GPIO TIM2_OR_RMP_MASK
#define | LL_TIM_TIM2_ETR_RMP_LSE (TIM2_OR_ETR_RMP | TIM2_OR_RMP_MASK)
#define | LL_TIM_TIM2_TI4_RMP_GPIO TIM2_OR_RMP_MASK
#define | LL_TIM_TIM2_TI4_RMP_COMP1 (TIM2_OR_TI4_RMP_0 | TIM2_OR_RMP_MASK)
#define | LL_TIM_TIM2_TI4_RMP_COMP2 (TIM2_OR_TI4_RMP_1 | TIM2_OR_RMP_MASK)
#define | LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM2_OR_TI4_RMP | TIM2_OR_RMP_MASK)
#define | LL_TIM_TIM16_TI1_RMP_GPIO TIM16_OR_RMP_MASK
#define | LL_TIM_TIM16_TI1_RMP_LSI (TIM16_OR_TI1_RMP_0 | TIM16_OR_RMP_MASK)
#define | LL_TIM_TIM16_TI1_RMP_LSE (TIM16_OR_TI1_RMP_1 | TIM16_OR_RMP_MASK)
#define | LL_TIM_TIM16_TI1_RMP_RTC (TIM16_OR_TI1_RMP_1 | TIM16_OR_TI1_RMP_0 | TIM16_OR_RMP_MASK)
#define | LL_TIM_TIM17_TI1_RMP_GPIO TIM17_OR_RMP_MASK
#define | LL_TIM_TIM17_TI1_RMP_MSI (TIM17_OR_TI1_RMP_0 | TIM17_OR_RMP_MASK)
#define | LL_TIM_TIM17_TI1_RMP_HSE_32 (TIM17_OR_TI1_RMP_1 | TIM17_OR_RMP_MASK)
#define | LL_TIM_TIM17_TI1_RMP_MCO (TIM17_OR_TI1_RMP | TIM17_OR_RMP_MASK)
#define | LL_TIM_OCREF_CLR_INT_OCREF_CLR 0x00000000U
#define | LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS
#define | LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
Write a value in TIM register.
#define | LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
Read a value in TIM register.
#define | __LL_TIM_GETFLAG_UIFCPY(__CNT__) (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
HELPER macro retrieving the UIFCPY flag from the counter value.
#define | __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)
HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
#define | __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
#define | __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
#define | __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)
HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
#define | __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)
HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
#define | __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
HELPER macro retrieving the ratio of the input capture prescaler.

Functions

__STATIC_INLINE void | LL_TIM_EnableCounter (TIM_TypeDef *TIMx)
Enable timer counter.
__STATIC_INLINE void | LL_TIM_DisableCounter (TIM_TypeDef *TIMx)
Disable timer counter.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledCounter (TIM_TypeDef *TIMx)
Indicates whether the timer counter is enabled.
__STATIC_INLINE void | LL_TIM_EnableUpdateEvent (TIM_TypeDef *TIMx)
Enable update event generation.
__STATIC_INLINE void | LL_TIM_DisableUpdateEvent (TIM_TypeDef *TIMx)
Disable update event generation.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledUpdateEvent (TIM_TypeDef *TIMx)
Indicates whether update event generation is enabled.
__STATIC_INLINE void | LL_TIM_SetUpdateSource (TIM_TypeDef *TIMx, uint32_t UpdateSource)
Set update event source.
__STATIC_INLINE uint32_t | LL_TIM_GetUpdateSource (TIM_TypeDef *TIMx)
Get actual event update source.
__STATIC_INLINE void | LL_TIM_SetOnePulseMode (TIM_TypeDef *TIMx, uint32_t OnePulseMode)
Set one pulse mode (one shot v.s.
__STATIC_INLINE uint32_t | LL_TIM_GetOnePulseMode (TIM_TypeDef *TIMx)
Get actual one pulse mode.
__STATIC_INLINE void | LL_TIM_SetCounterMode (TIM_TypeDef *TIMx, uint32_t CounterMode)
Set the timer counter counting mode.
__STATIC_INLINE uint32_t | LL_TIM_GetCounterMode (TIM_TypeDef *TIMx)
Get actual counter mode.
__STATIC_INLINE void | LL_TIM_EnableARRPreload (TIM_TypeDef *TIMx)
Enable auto-reload (ARR) preload.
__STATIC_INLINE void | LL_TIM_DisableARRPreload (TIM_TypeDef *TIMx)
Disable auto-reload (ARR) preload.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledARRPreload (TIM_TypeDef *TIMx)
Indicates whether auto-reload (ARR) preload is enabled.
__STATIC_INLINE void | LL_TIM_SetClockDivision (TIM_TypeDef *TIMx, uint32_t ClockDivision)
Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
__STATIC_INLINE uint32_t | LL_TIM_GetClockDivision (TIM_TypeDef *TIMx)
Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
__STATIC_INLINE void | LL_TIM_SetCounter (TIM_TypeDef *TIMx, uint32_t Counter)
Set the counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetCounter (TIM_TypeDef *TIMx)
Get the counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetDirection (TIM_TypeDef *TIMx)
Get the current direction of the counter.
__STATIC_INLINE void | LL_TIM_SetPrescaler (TIM_TypeDef *TIMx, uint32_t Prescaler)
Set the prescaler value.
__STATIC_INLINE uint32_t | LL_TIM_GetPrescaler (TIM_TypeDef *TIMx)
Get the prescaler value.
__STATIC_INLINE void | LL_TIM_SetAutoReload (TIM_TypeDef *TIMx, uint32_t AutoReload)
Set the auto-reload value.
__STATIC_INLINE uint32_t | LL_TIM_GetAutoReload (TIM_TypeDef *TIMx)
Get the auto-reload value.
__STATIC_INLINE void | LL_TIM_SetRepetitionCounter (TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
Set the repetition counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetRepetitionCounter (TIM_TypeDef *TIMx)
Get the repetition counter value.
__STATIC_INLINE void | LL_TIM_EnableUIFRemap (TIM_TypeDef *TIMx)
Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
__STATIC_INLINE void | LL_TIM_DisableUIFRemap (TIM_TypeDef *TIMx)
Disable update interrupt flag (UIF) remapping.
__STATIC_INLINE void | LL_TIM_CC_EnablePreload (TIM_TypeDef *TIMx)
Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
__STATIC_INLINE void | LL_TIM_CC_DisablePreload (TIM_TypeDef *TIMx)
Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
__STATIC_INLINE void | LL_TIM_CC_SetUpdate (TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
__STATIC_INLINE void | LL_TIM_CC_SetDMAReqTrigger (TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
Set the trigger of the capture/compare DMA request.
__STATIC_INLINE uint32_t | LL_TIM_CC_GetDMAReqTrigger (TIM_TypeDef *TIMx)
Get actual trigger of the capture/compare DMA request.
__STATIC_INLINE void | LL_TIM_CC_SetLockLevel (TIM_TypeDef *TIMx, uint32_t LockLevel)
Set the lock level to freeze the configuration of several capture/compare parameters.
__STATIC_INLINE void | LL_TIM_CC_EnableChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Enable capture/compare channels.
__STATIC_INLINE void | LL_TIM_CC_DisableChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Disable capture/compare channels.
__STATIC_INLINE uint32_t | LL_TIM_CC_IsEnabledChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Indicate whether channel(s) is(are) enabled.
__STATIC_INLINE void | LL_TIM_OC_ConfigOutput (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
Configure an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetMode (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
Define the behavior of the output reference signal OCxREF from which OCx and OCxN (when relevant) are derived.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetMode (TIM_TypeDef *TIMx, uint32_t Channel)
Get the output compare mode of an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetPolarity (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
Set the polarity of an output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetPolarity (TIM_TypeDef *TIMx, uint32_t Channel)
Get the polarity of an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetIdleState (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
Set the IDLE state of an output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetIdleState (TIM_TypeDef *TIMx, uint32_t Channel)
Get the IDLE state of an output channel.
__STATIC_INLINE void | LL_TIM_OC_EnableFast (TIM_TypeDef *TIMx, uint32_t Channel)
Enable fast mode for the output channel.
__STATIC_INLINE void | LL_TIM_OC_DisableFast (TIM_TypeDef *TIMx, uint32_t Channel)
Disable fast mode for the output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledFast (TIM_TypeDef *TIMx, uint32_t Channel)
Indicates whether fast mode is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_EnablePreload (TIM_TypeDef *TIMx, uint32_t Channel)
Enable compare register (TIMx_CCRx) preload for the output channel.
__STATIC_INLINE void | LL_TIM_OC_DisablePreload (TIM_TypeDef *TIMx, uint32_t Channel)
Disable compare register (TIMx_CCRx) preload for the output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledPreload (TIM_TypeDef *TIMx, uint32_t Channel)
Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_EnableClear (TIM_TypeDef *TIMx, uint32_t Channel)
Enable clearing the output channel on an external event.
__STATIC_INLINE void | LL_TIM_OC_DisableClear (TIM_TypeDef *TIMx, uint32_t Channel)
Disable clearing the output channel on an external event.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledClear (TIM_TypeDef *TIMx, uint32_t Channel)
Indicates clearing the output channel on an external event is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_SetDeadTime (TIM_TypeDef *TIMx, uint32_t DeadTime)
Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH1 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 1 (TIMx_CCR1).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH2 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 2 (TIMx_CCR2).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH3 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 3 (TIMx_CCR3).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH4 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 4 (TIMx_CCR4).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH5 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 5 (TIMx_CCR5).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH6 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 6 (TIMx_CCR6).
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH1 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR1) set for output channel 1.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH2 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR2) set for output channel 2.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH3 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR3) set for output channel 3.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH4 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR4) set for output channel 4.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH5 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR5) set for output channel 5.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH6 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR6) set for output channel 6.
__STATIC_INLINE void | LL_TIM_SetCH5CombinedChannels (TIM_TypeDef *TIMx, uint32_t GroupCH5)
Select on which reference signal the OC5REF is combined to.
__STATIC_INLINE void | LL_TIM_IC_Config (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
Configure input channel.
__STATIC_INLINE void | LL_TIM_IC_SetActiveInput (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
Set the active input.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetActiveInput (TIM_TypeDef *TIMx, uint32_t Channel)
Get the current active input.
__STATIC_INLINE void | LL_TIM_IC_SetPrescaler (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
Set the prescaler of input channel.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetPrescaler (TIM_TypeDef *TIMx, uint32_t Channel)
Get the current prescaler value acting on an input channel.
__STATIC_INLINE void | LL_TIM_IC_SetFilter (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
Set the input filter duration.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetFilter (TIM_TypeDef *TIMx, uint32_t Channel)
Get the input filter duration.
__STATIC_INLINE void | LL_TIM_IC_SetPolarity (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
Set the input channel polarity.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetPolarity (TIM_TypeDef *TIMx, uint32_t Channel)
Get the current input channel polarity.
__STATIC_INLINE void | LL_TIM_IC_EnableXORCombination (TIM_TypeDef *TIMx)
Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
__STATIC_INLINE void | LL_TIM_IC_DisableXORCombination (TIM_TypeDef *TIMx)
Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
__STATIC_INLINE uint32_t | LL_TIM_IC_IsEnabledXORCombination (TIM_TypeDef *TIMx)
Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH1 (TIM_TypeDef *TIMx)
Get captured value for input channel 1.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH2 (TIM_TypeDef *TIMx)
Get captured value for input channel 2.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH3 (TIM_TypeDef *TIMx)
Get captured value for input channel 3.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH4 (TIM_TypeDef *TIMx)
Get captured value for input channel 4.
__STATIC_INLINE void | LL_TIM_EnableExternalClock (TIM_TypeDef *TIMx)
Enable external clock mode 2.
__STATIC_INLINE void | LL_TIM_DisableExternalClock (TIM_TypeDef *TIMx)
Disable external clock mode 2.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledExternalClock (TIM_TypeDef *TIMx)
Indicate whether external clock mode 2 is enabled.
__STATIC_INLINE void | LL_TIM_SetClockSource (TIM_TypeDef *TIMx, uint32_t ClockSource)
Set the clock source of the counter clock.
__STATIC_INLINE void | LL_TIM_SetEncoderMode (TIM_TypeDef *TIMx, uint32_t EncoderMode)
Set the encoder interface mode.
__STATIC_INLINE void | LL_TIM_SetTriggerOutput (TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
Set the trigger output (TRGO) used for timer synchronization .
__STATIC_INLINE void | LL_TIM_SetTriggerOutput2 (TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
Set the trigger output 2 (TRGO2) used for ADC synchronization .
__STATIC_INLINE void | LL_TIM_SetSlaveMode (TIM_TypeDef *TIMx, uint32_t SlaveMode)
Set the synchronization mode of a slave timer.
__STATIC_INLINE void | LL_TIM_SetTriggerInput (TIM_TypeDef *TIMx, uint32_t TriggerInput)
Set the selects the trigger input to be used to synchronize the counter.
__STATIC_INLINE void | LL_TIM_EnableMasterSlaveMode (TIM_TypeDef *TIMx)
Enable the Master/Slave mode.
__STATIC_INLINE void | LL_TIM_DisableMasterSlaveMode (TIM_TypeDef *TIMx)
Disable the Master/Slave mode.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledMasterSlaveMode (TIM_TypeDef *TIMx)
Indicates whether the Master/Slave mode is enabled.
__STATIC_INLINE void | LL_TIM_ConfigETR (TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, uint32_t ETRFilter)
Configure the external trigger (ETR) input.
__STATIC_INLINE void | LL_TIM_SetETRSource (TIM_TypeDef *TIMx, uint32_t ETRSource)
Select the external trigger (ETR) input source.
__STATIC_INLINE void | LL_TIM_EnableBRK (TIM_TypeDef *TIMx)
Enable the break function.
__STATIC_INLINE void | LL_TIM_DisableBRK (TIM_TypeDef *TIMx)
Disable the break function.
__STATIC_INLINE void | LL_TIM_ConfigBRK (TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter)
Configure the break input.
__STATIC_INLINE void | LL_TIM_EnableBRK2 (TIM_TypeDef *TIMx)
Enable the break 2 function.
__STATIC_INLINE void | LL_TIM_DisableBRK2 (TIM_TypeDef *TIMx)
Disable the break 2 function.
__STATIC_INLINE void | LL_TIM_ConfigBRK2 (TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
Configure the break 2 input.
__STATIC_INLINE void | LL_TIM_SetOffStates (TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
Select the outputs off state (enabled v.s.
__STATIC_INLINE void | LL_TIM_EnableAutomaticOutput (TIM_TypeDef *TIMx)
Enable automatic output (MOE can be set by software or automatically when a break input is active).
__STATIC_INLINE void | LL_TIM_DisableAutomaticOutput (TIM_TypeDef *TIMx)
Disable automatic output (MOE can be set only by software).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledAutomaticOutput (TIM_TypeDef *TIMx)
Indicate whether automatic output is enabled.
__STATIC_INLINE void | LL_TIM_EnableAllOutputs (TIM_TypeDef *TIMx)
Enable the outputs (set the MOE bit in TIMx_BDTR register).
__STATIC_INLINE void | LL_TIM_DisableAllOutputs (TIM_TypeDef *TIMx)
Disable the outputs (reset the MOE bit in TIMx_BDTR register).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledAllOutputs (TIM_TypeDef *TIMx)
Indicates whether outputs are enabled.
__STATIC_INLINE void | LL_TIM_EnableBreakInputSource (TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
Enable the signals connected to the designated timer break input.
__STATIC_INLINE void | LL_TIM_DisableBreakInputSource (TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
Disable the signals connected to the designated timer break input.
__STATIC_INLINE void | LL_TIM_SetBreakInputSourcePolarity (TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source, uint32_t Polarity)
Set the polarity of the break signal for the timer break input.
__STATIC_INLINE void | LL_TIM_ConfigDMABurst (TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
Configures the timer DMA burst feature.
__STATIC_INLINE void | LL_TIM_SetRemap (TIM_TypeDef *TIMx, uint32_t Remap)
Remap TIM inputs (input channel, internal/external triggers).
__STATIC_INLINE void | LL_TIM_SetOCRefClearInputSource (TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
Set the OCREF clear input source.
__STATIC_INLINE void | LL_TIM_ClearFlag_UPDATE (TIM_TypeDef *TIMx)
Clear the update interrupt flag (UIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_UPDATE (TIM_TypeDef *TIMx)
Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC1 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 1 interrupt flag (CC1F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC1 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC2 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 2 interrupt flag (CC2F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC2 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC3 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 3 interrupt flag (CC3F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC3 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC4 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 4 interrupt flag (CC4F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC4 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC5 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 5 interrupt flag (CC5F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC5 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC6 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 6 interrupt flag (CC6F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC6 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_COM (TIM_TypeDef *TIMx)
Clear the commutation interrupt flag (COMIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_COM (TIM_TypeDef *TIMx)
Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_TRIG (TIM_TypeDef *TIMx)
Clear the trigger interrupt flag (TIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_TRIG (TIM_TypeDef *TIMx)
Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_BRK (TIM_TypeDef *TIMx)
Clear the break interrupt flag (BIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_BRK (TIM_TypeDef *TIMx)
Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_BRK2 (TIM_TypeDef *TIMx)
Clear the break 2 interrupt flag (B2IF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_BRK2 (TIM_TypeDef *TIMx)
Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC1OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC1OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC2OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC2OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC3OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC3OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC4OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC4OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_SYSBRK (TIM_TypeDef *TIMx)
Clear the system break interrupt flag (SBIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_SYSBRK (TIM_TypeDef *TIMx)
Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
__STATIC_INLINE void | LL_TIM_EnableIT_UPDATE (TIM_TypeDef *TIMx)
Enable update interrupt (UIE).
__STATIC_INLINE void | LL_TIM_DisableIT_UPDATE (TIM_TypeDef *TIMx)
Disable update interrupt (UIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_UPDATE (TIM_TypeDef *TIMx)
Indicates whether the update interrupt (UIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC1 (TIM_TypeDef *TIMx)
Enable capture/compare 1 interrupt (CC1IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC1 (TIM_TypeDef *TIMx)
Disable capture/compare 1 interrupt (CC1IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC1 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC2 (TIM_TypeDef *TIMx)
Enable capture/compare 2 interrupt (CC2IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC2 (TIM_TypeDef *TIMx)
Disable capture/compare 2 interrupt (CC2IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC2 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC3 (TIM_TypeDef *TIMx)
Enable capture/compare 3 interrupt (CC3IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC3 (TIM_TypeDef *TIMx)
Disable capture/compare 3 interrupt (CC3IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC3 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC4 (TIM_TypeDef *TIMx)
Enable capture/compare 4 interrupt (CC4IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC4 (TIM_TypeDef *TIMx)
Disable capture/compare 4 interrupt (CC4IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC4 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_COM (TIM_TypeDef *TIMx)
Enable commutation interrupt (COMIE).
__STATIC_INLINE void | LL_TIM_DisableIT_COM (TIM_TypeDef *TIMx)
Disable commutation interrupt (COMIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_COM (TIM_TypeDef *TIMx)
Indicates whether the commutation interrupt (COMIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_TRIG (TIM_TypeDef *TIMx)
Enable trigger interrupt (TIE).
__STATIC_INLINE void | LL_TIM_DisableIT_TRIG (TIM_TypeDef *TIMx)
Disable trigger interrupt (TIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_TRIG (TIM_TypeDef *TIMx)
Indicates whether the trigger interrupt (TIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_BRK (TIM_TypeDef *TIMx)
Enable break interrupt (BIE).
__STATIC_INLINE void | LL_TIM_DisableIT_BRK (TIM_TypeDef *TIMx)
Disable break interrupt (BIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_BRK (TIM_TypeDef *TIMx)
Indicates whether the break interrupt (BIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_UPDATE (TIM_TypeDef *TIMx)
Enable update DMA request (UDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_UPDATE (TIM_TypeDef *TIMx)
Disable update DMA request (UDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_UPDATE (TIM_TypeDef *TIMx)
Indicates whether the update DMA request (UDE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC1 (TIM_TypeDef *TIMx)
Enable capture/compare 1 DMA request (CC1DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC1 (TIM_TypeDef *TIMx)
Disable capture/compare 1 DMA request (CC1DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC1 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC2 (TIM_TypeDef *TIMx)
Enable capture/compare 2 DMA request (CC2DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC2 (TIM_TypeDef *TIMx)
Disable capture/compare 2 DMA request (CC2DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC2 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC3 (TIM_TypeDef *TIMx)
Enable capture/compare 3 DMA request (CC3DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC3 (TIM_TypeDef *TIMx)
Disable capture/compare 3 DMA request (CC3DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC3 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC4 (TIM_TypeDef *TIMx)
Enable capture/compare 4 DMA request (CC4DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC4 (TIM_TypeDef *TIMx)
Disable capture/compare 4 DMA request (CC4DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC4 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_COM (TIM_TypeDef *TIMx)
Enable commutation DMA request (COMDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_COM (TIM_TypeDef *TIMx)
Disable commutation DMA request (COMDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_COM (TIM_TypeDef *TIMx)
Indicates whether the commutation DMA request (COMDE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_TRIG (TIM_TypeDef *TIMx)
Enable trigger interrupt (TDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_TRIG (TIM_TypeDef *TIMx)
Disable trigger interrupt (TDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_TRIG (TIM_TypeDef *TIMx)
Indicates whether the trigger interrupt (TDE) is enabled.
__STATIC_INLINE void | LL_TIM_GenerateEvent_UPDATE (TIM_TypeDef *TIMx)
Generate an update event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC1 (TIM_TypeDef *TIMx)
Generate Capture/Compare 1 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC2 (TIM_TypeDef *TIMx)
Generate Capture/Compare 2 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC3 (TIM_TypeDef *TIMx)
Generate Capture/Compare 3 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC4 (TIM_TypeDef *TIMx)
Generate Capture/Compare 4 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_COM (TIM_TypeDef *TIMx)
Generate commutation event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_TRIG (TIM_TypeDef *TIMx)
Generate trigger event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_BRK (TIM_TypeDef *TIMx)
Generate break event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_BRK2 (TIM_TypeDef *TIMx)
Generate break 2 event.
ErrorStatus | LL_TIM_DeInit (TIM_TypeDef *TIMx)
Set TIMx registers to their reset values.
void | LL_TIM_StructInit (LL_TIM_InitTypeDef *TIM_InitStruct)
Set the fields of the time base unit configuration data structure to their default values.
ErrorStatus | LL_TIM_Init (TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
Configure the TIMx time base unit.
void | LL_TIM_OC_StructInit (LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Set the fields of the TIMx output channel configuration data structure to their default values.
ErrorStatus | LL_TIM_OC_Init (TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Configure the TIMx output channel.
void | LL_TIM_IC_StructInit (LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Set the fields of the TIMx input channel configuration data structure to their default values.
ErrorStatus | LL_TIM_IC_Init (TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
Configure the TIMx input channel.
void | LL_TIM_ENCODER_StructInit (LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Fills each TIM_EncoderInitStruct field with its default value.
ErrorStatus | LL_TIM_ENCODER_Init (TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Configure the encoder interface of the timer instance.
void | LL_TIM_HALLSENSOR_StructInit (LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
Set the fields of the TIMx Hall sensor interface configuration data structure to their default values.
ErrorStatus | LL_TIM_HALLSENSOR_Init (TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
Configure the Hall sensor interface of the timer instance.
void | LL_TIM_BDTR_StructInit (LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
Set the fields of the Break and Dead Time configuration data structure to their default values.
ErrorStatus | LL_TIM_BDTR_Init (TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
Configure the Break and Dead Time feature of the timer instance.

Variables

static const uint8_t | OFFSET_TAB_CCMRx []
static const uint8_t | SHIFT_TAB_OCxx []
static const uint8_t | SHIFT_TAB_ICxx []
static const uint8_t | SHIFT_TAB_CCxP []
static const uint8_t | SHIFT_TAB_OISx []

Detailed Description

Header file of TIM LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_tim.h.

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_usart.h File Reference

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stm32wbxx_ll_usart.h File Reference

Header file of USART LL module. More...

#include "stm32wbxx.h"

Go to the source code of this file.

Data Structures

struct | LL_USART_InitTypeDef
LL USART Init Structure definition. More...
struct | LL_USART_ClockInitTypeDef
LL USART Clock Init Structure definition. More...

Defines

#define | LL_USART_ICR_PECF USART_ICR_PECF
#define | LL_USART_ICR_FECF USART_ICR_FECF
#define | LL_USART_ICR_NECF USART_ICR_NECF
#define | LL_USART_ICR_ORECF USART_ICR_ORECF
#define | LL_USART_ICR_IDLECF USART_ICR_IDLECF
#define | LL_USART_ICR_TXFECF USART_ICR_TXFECF
#define | LL_USART_ICR_TCCF USART_ICR_TCCF
#define | LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF
#define | LL_USART_ICR_LBDCF USART_ICR_LBDCF
#define | LL_USART_ICR_CTSCF USART_ICR_CTSCF
#define | LL_USART_ICR_RTOCF USART_ICR_RTOCF
#define | LL_USART_ICR_EOBCF USART_ICR_EOBCF
#define | LL_USART_ICR_UDRCF USART_ICR_UDRCF
#define | LL_USART_ICR_CMCF USART_ICR_CMCF
#define | LL_USART_ICR_WUCF USART_ICR_WUCF
#define | LL_USART_ISR_PE USART_ISR_PE
#define | LL_USART_ISR_FE USART_ISR_FE
#define | LL_USART_ISR_NE USART_ISR_NE
#define | LL_USART_ISR_ORE USART_ISR_ORE
#define | LL_USART_ISR_IDLE USART_ISR_IDLE
#define | LL_USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE
#define | LL_USART_ISR_TC USART_ISR_TC
#define | LL_USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF
#define | LL_USART_ISR_LBDF USART_ISR_LBDF
#define | LL_USART_ISR_CTSIF USART_ISR_CTSIF
#define | LL_USART_ISR_CTS USART_ISR_CTS
#define | LL_USART_ISR_RTOF USART_ISR_RTOF
#define | LL_USART_ISR_EOBF USART_ISR_EOBF
#define | LL_USART_ISR_UDR USART_ISR_UDR
#define | LL_USART_ISR_ABRE USART_ISR_ABRE
#define | LL_USART_ISR_ABRF USART_ISR_ABRF
#define | LL_USART_ISR_BUSY USART_ISR_BUSY
#define | LL_USART_ISR_CMF USART_ISR_CMF
#define | LL_USART_ISR_SBKF USART_ISR_SBKF
#define | LL_USART_ISR_RWU USART_ISR_RWU
#define | LL_USART_ISR_WUF USART_ISR_WUF
#define | LL_USART_ISR_TEACK USART_ISR_TEACK
#define | LL_USART_ISR_REACK USART_ISR_REACK
#define | LL_USART_ISR_TXFE USART_ISR_TXFE
#define | LL_USART_ISR_RXFF USART_ISR_RXFF
#define | LL_USART_ISR_TCBGT USART_ISR_TCBGT
#define | LL_USART_ISR_RXFT USART_ISR_RXFT
#define | LL_USART_ISR_TXFT USART_ISR_TXFT
#define | LL_USART_CR1_IDLEIE USART_CR1_IDLEIE
#define | LL_USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE
#define | LL_USART_CR1_TCIE USART_CR1_TCIE
#define | LL_USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE
#define | LL_USART_CR1_PEIE USART_CR1_PEIE
#define | LL_USART_CR1_CMIE USART_CR1_CMIE
#define | LL_USART_CR1_RTOIE USART_CR1_RTOIE
#define | LL_USART_CR1_EOBIE USART_CR1_EOBIE
#define | LL_USART_CR1_TXFEIE USART_CR1_TXFEIE
#define | LL_USART_CR1_RXFFIE USART_CR1_RXFFIE
#define | LL_USART_CR2_LBDIE USART_CR2_LBDIE
#define | LL_USART_CR3_EIE USART_CR3_EIE
#define | LL_USART_CR3_CTSIE USART_CR3_CTSIE
#define | LL_USART_CR3_WUFIE USART_CR3_WUFIE
#define | LL_USART_CR3_TXFTIE USART_CR3_TXFTIE
#define | LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE
#define | LL_USART_CR3_RXFTIE USART_CR3_RXFTIE
#define | LL_USART_FIFOTHRESHOLD_1_8 0x00000000U
#define | LL_USART_FIFOTHRESHOLD_1_4 0x00000001U
#define | LL_USART_FIFOTHRESHOLD_1_2 0x00000002U
#define | LL_USART_FIFOTHRESHOLD_3_4 0x00000003U
#define | LL_USART_FIFOTHRESHOLD_7_8 0x00000004U
#define | LL_USART_FIFOTHRESHOLD_8_8 0x00000005U
#define | LL_USART_DIRECTION_NONE 0x00000000U
#define | LL_USART_DIRECTION_RX USART_CR1_RE
#define | LL_USART_DIRECTION_TX USART_CR1_TE
#define | LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)
#define | LL_USART_PARITY_NONE 0x00000000U
#define | LL_USART_PARITY_EVEN USART_CR1_PCE
#define | LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)
#define | LL_USART_WAKEUP_IDLELINE 0x00000000U
#define | LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE
#define | LL_USART_DATAWIDTH_7B USART_CR1_M1
#define | LL_USART_DATAWIDTH_8B 0x00000000U
#define | LL_USART_DATAWIDTH_9B USART_CR1_M0
#define | LL_USART_OVERSAMPLING_16 0x00000000U
#define | LL_USART_OVERSAMPLING_8 USART_CR1_OVER8
#define | LL_USART_CLOCK_DISABLE 0x00000000U
#define | LL_USART_CLOCK_ENABLE USART_CR2_CLKEN
#define | LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U
#define | LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL
#define | LL_USART_PHASE_1EDGE 0x00000000U
#define | LL_USART_PHASE_2EDGE USART_CR2_CPHA
#define | LL_USART_POLARITY_LOW 0x00000000U
#define | LL_USART_POLARITY_HIGH USART_CR2_CPOL
#define | LL_USART_PRESCALER_DIV1 0x00000000U
#define | LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1)
#define | LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2)
#define | LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1)
#define | LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3)
#define | LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0)
#define | LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1)
#define | LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)
#define | LL_USART_STOPBITS_0_5 USART_CR2_STOP_0
#define | LL_USART_STOPBITS_1 0x00000000U
#define | LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define | LL_USART_STOPBITS_2 USART_CR2_STOP_1
#define | LL_USART_TXRX_STANDARD 0x00000000U
#define | LL_USART_TXRX_SWAPPED (USART_CR2_SWAP)
#define | LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U
#define | LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV)
#define | LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U
#define | LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV)
#define | LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U
#define | LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV
#define | LL_USART_BITORDER_LSBFIRST 0x00000000U
#define | LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST
#define | LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U
#define | LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0
#define | LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1
#define | LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0)
#define | LL_USART_ADDRESS_DETECT_4B 0x00000000U
#define | LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7
#define | LL_USART_HWCONTROL_NONE 0x00000000U
#define | LL_USART_HWCONTROL_RTS USART_CR3_RTSE
#define | LL_USART_HWCONTROL_CTS USART_CR3_CTSE
#define | LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
#define | LL_USART_WAKEUP_ON_ADDRESS 0x00000000U
#define | LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1
#define | LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)
#define | LL_USART_IRDA_POWER_NORMAL 0x00000000U
#define | LL_USART_IRDA_POWER_LOW USART_CR3_IRLP
#define | LL_USART_LINBREAK_DETECT_10B 0x00000000U
#define | LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL
#define | LL_USART_DE_POLARITY_HIGH 0x00000000U
#define | LL_USART_DE_POLARITY_LOW USART_CR3_DEP
#define | LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U
#define | LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U
#define | LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in USART register.
#define | LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in USART register.
#define | __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (((((__PERIPHCLK__)/(uint32_t)(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U) + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
#define | __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((__PERIPHCLK__)/(uint32_t)(USART_PRESCALER_TAB[(__PRESCALER__)])) + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
#define | LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE
#define | LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF
#define | LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE
#define | LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF
#define | LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE
#define | LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF
#define | LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE
#define | LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF

Functions

__STATIC_INLINE void | LL_USART_Enable (USART_TypeDef *USARTx)
USART Enable.
__STATIC_INLINE void | LL_USART_Disable (USART_TypeDef *USARTx)
USART Disable (all USART prescalers and outputs are disabled)
__STATIC_INLINE uint32_t | LL_USART_IsEnabled (USART_TypeDef *USARTx)
Indicate if USART is enabled.
__STATIC_INLINE void | LL_USART_EnableFIFO (USART_TypeDef *USARTx)
FIFO Mode Enable.
__STATIC_INLINE void | LL_USART_DisableFIFO (USART_TypeDef *USARTx)
FIFO Mode Disable.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledFIFO (USART_TypeDef *USARTx)
Indicate if FIFO Mode is enabled.
__STATIC_INLINE void | LL_USART_SetTXFIFOThreshold (USART_TypeDef *USARTx, uint32_t Threshold)
Configure TX FIFO Threshold.
__STATIC_INLINE uint32_t | LL_USART_GetTXFIFOThreshold (USART_TypeDef *USARTx)
Return TX FIFO Threshold Configuration.
__STATIC_INLINE void | LL_USART_SetRXFIFOThreshold (USART_TypeDef *USARTx, uint32_t Threshold)
Configure RX FIFO Threshold.
__STATIC_INLINE uint32_t | LL_USART_GetRXFIFOThreshold (USART_TypeDef *USARTx)
Return RX FIFO Threshold Configuration.
__STATIC_INLINE void | LL_USART_ConfigFIFOsThreshold (USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold)
Configure TX and RX FIFOs Threshold.
__STATIC_INLINE void | LL_USART_EnableInStopMode (USART_TypeDef *USARTx)
USART enabled in STOP Mode.
__STATIC_INLINE void | LL_USART_DisableInStopMode (USART_TypeDef *USARTx)
USART disabled in STOP Mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledInStopMode (USART_TypeDef *USARTx)
Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
__STATIC_INLINE void | LL_USART_EnableDirectionRx (USART_TypeDef *USARTx)
Receiver Enable (Receiver is enabled and begins searching for a start bit)
__STATIC_INLINE void | LL_USART_DisableDirectionRx (USART_TypeDef *USARTx)
Receiver Disable.
__STATIC_INLINE void | LL_USART_EnableDirectionTx (USART_TypeDef *USARTx)
Transmitter Enable.
__STATIC_INLINE void | LL_USART_DisableDirectionTx (USART_TypeDef *USARTx)
Transmitter Disable.
__STATIC_INLINE void | LL_USART_SetTransferDirection (USART_TypeDef *USARTx, uint32_t TransferDirection)
Configure simultaneously enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE uint32_t | LL_USART_GetTransferDirection (USART_TypeDef *USARTx)
Return enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE void | LL_USART_SetParity (USART_TypeDef *USARTx, uint32_t Parity)
Configure Parity (enabled/disabled and parity mode if enabled).
__STATIC_INLINE uint32_t | LL_USART_GetParity (USART_TypeDef *USARTx)
Return Parity configuration (enabled/disabled and parity mode if enabled)
__STATIC_INLINE void | LL_USART_SetWakeUpMethod (USART_TypeDef *USARTx, uint32_t Method)
Set Receiver Wake Up method from Mute mode.
__STATIC_INLINE uint32_t | LL_USART_GetWakeUpMethod (USART_TypeDef *USARTx)
Return Receiver Wake Up method from Mute mode.
__STATIC_INLINE void | LL_USART_SetDataWidth (USART_TypeDef *USARTx, uint32_t DataWidth)
Set Word length (i.e.
__STATIC_INLINE uint32_t | LL_USART_GetDataWidth (USART_TypeDef *USARTx)
Return Word length (i.e.
__STATIC_INLINE void | LL_USART_EnableMuteMode (USART_TypeDef *USARTx)
Allow switch between Mute Mode and Active mode.
__STATIC_INLINE void | LL_USART_DisableMuteMode (USART_TypeDef *USARTx)
Prevent Mute Mode use.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledMuteMode (USART_TypeDef *USARTx)
Indicate if switch between Mute Mode and Active mode is allowed.
__STATIC_INLINE void | LL_USART_SetOverSampling (USART_TypeDef *USARTx, uint32_t OverSampling)
Set Oversampling to 8-bit or 16-bit mode.
__STATIC_INLINE uint32_t | LL_USART_GetOverSampling (USART_TypeDef *USARTx)
Return Oversampling mode.
__STATIC_INLINE void | LL_USART_SetLastClkPulseOutput (USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
Configure if Clock pulse of the last data bit is output to the SCLK pin or not.
__STATIC_INLINE uint32_t | LL_USART_GetLastClkPulseOutput (USART_TypeDef *USARTx)
Retrieve Clock pulse of the last data bit output configuration (Last bit Clock pulse output to the SCLK pin or not)
__STATIC_INLINE void | LL_USART_SetClockPhase (USART_TypeDef *USARTx, uint32_t ClockPhase)
Select the phase of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE uint32_t | LL_USART_GetClockPhase (USART_TypeDef *USARTx)
Return phase of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE void | LL_USART_SetClockPolarity (USART_TypeDef *USARTx, uint32_t ClockPolarity)
Select the polarity of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE uint32_t | LL_USART_GetClockPolarity (USART_TypeDef *USARTx)
Return polarity of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE void | LL_USART_ConfigClock (USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
__STATIC_INLINE void | LL_USART_SetPrescaler (USART_TypeDef *USARTx, uint32_t PrescalerValue)
Configure Clock source prescaler for baudrate generator and oversampling.
__STATIC_INLINE uint32_t | LL_USART_GetPrescaler (USART_TypeDef *USARTx)
Retrieve the Clock source prescaler for baudrate generator and oversampling.
__STATIC_INLINE void | LL_USART_EnableSCLKOutput (USART_TypeDef *USARTx)
Enable Clock output on SCLK pin.
__STATIC_INLINE void | LL_USART_DisableSCLKOutput (USART_TypeDef *USARTx)
Disable Clock output on SCLK pin.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSCLKOutput (USART_TypeDef *USARTx)
Indicate if Clock output on SCLK pin is enabled.
__STATIC_INLINE void | LL_USART_SetStopBitsLength (USART_TypeDef *USARTx, uint32_t StopBits)
Set the length of the stop bits.
__STATIC_INLINE uint32_t | LL_USART_GetStopBitsLength (USART_TypeDef *USARTx)
Retrieve the length of the stop bits.
__STATIC_INLINE void | LL_USART_ConfigCharacter (USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity, uint32_t StopBits)
Configure Character frame format (Datawidth, Parity control, Stop Bits)
__STATIC_INLINE void | LL_USART_SetTXRXSwap (USART_TypeDef *USARTx, uint32_t SwapConfig)
Configure TX/RX pins swapping setting.
__STATIC_INLINE uint32_t | LL_USART_GetTXRXSwap (USART_TypeDef *USARTx)
Retrieve TX/RX pins swapping configuration.
__STATIC_INLINE void | LL_USART_SetRXPinLevel (USART_TypeDef *USARTx, uint32_t PinInvMethod)
Configure RX pin active level logic.
__STATIC_INLINE uint32_t | LL_USART_GetRXPinLevel (USART_TypeDef *USARTx)
Retrieve RX pin active level logic configuration.
__STATIC_INLINE void | LL_USART_SetTXPinLevel (USART_TypeDef *USARTx, uint32_t PinInvMethod)
Configure TX pin active level logic.
__STATIC_INLINE uint32_t | LL_USART_GetTXPinLevel (USART_TypeDef *USARTx)
Retrieve TX pin active level logic configuration.
__STATIC_INLINE void | LL_USART_SetBinaryDataLogic (USART_TypeDef *USARTx, uint32_t DataLogic)
Configure Binary data logic.
__STATIC_INLINE uint32_t | LL_USART_GetBinaryDataLogic (USART_TypeDef *USARTx)
Retrieve Binary data configuration.
__STATIC_INLINE void | LL_USART_SetTransferBitOrder (USART_TypeDef *USARTx, uint32_t BitOrder)
Configure transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE uint32_t | LL_USART_GetTransferBitOrder (USART_TypeDef *USARTx)
Return transfer bit order (either Less or Most Significant Bit First)
__STATIC_INLINE void | LL_USART_EnableAutoBaudRate (USART_TypeDef *USARTx)
Enable Auto Baud-Rate Detection.
__STATIC_INLINE void | LL_USART_DisableAutoBaudRate (USART_TypeDef *USARTx)
Disable Auto Baud-Rate Detection.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledAutoBaud (USART_TypeDef *USARTx)
Indicate if Auto Baud-Rate Detection mechanism is enabled.
__STATIC_INLINE void | LL_USART_SetAutoBaudRateMode (USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
Set Auto Baud-Rate mode bits.
__STATIC_INLINE uint32_t | LL_USART_GetAutoBaudRateMode (USART_TypeDef *USARTx)
Return Auto Baud-Rate mode.
__STATIC_INLINE void | LL_USART_EnableRxTimeout (USART_TypeDef *USARTx)
Enable Receiver Timeout.
__STATIC_INLINE void | LL_USART_DisableRxTimeout (USART_TypeDef *USARTx)
Disable Receiver Timeout.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledRxTimeout (USART_TypeDef *USARTx)
Indicate if Receiver Timeout feature is enabled.
__STATIC_INLINE void | LL_USART_ConfigNodeAddress (USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
Set Address of the USART node.
__STATIC_INLINE uint32_t | LL_USART_GetNodeAddress (USART_TypeDef *USARTx)
Return 8 bit Address of the USART node as set in ADD field of CR2.
__STATIC_INLINE uint32_t | LL_USART_GetNodeAddressLen (USART_TypeDef *USARTx)
Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
__STATIC_INLINE void | LL_USART_EnableRTSHWFlowCtrl (USART_TypeDef *USARTx)
Enable RTS HW Flow Control.
__STATIC_INLINE void | LL_USART_DisableRTSHWFlowCtrl (USART_TypeDef *USARTx)
Disable RTS HW Flow Control.
__STATIC_INLINE void | LL_USART_EnableCTSHWFlowCtrl (USART_TypeDef *USARTx)
Enable CTS HW Flow Control.
__STATIC_INLINE void | LL_USART_DisableCTSHWFlowCtrl (USART_TypeDef *USARTx)
Disable CTS HW Flow Control.
__STATIC_INLINE void | LL_USART_SetHWFlowCtrl (USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
Configure HW Flow Control mode (both CTS and RTS)
__STATIC_INLINE uint32_t | LL_USART_GetHWFlowCtrl (USART_TypeDef *USARTx)
Return HW Flow Control configuration (both CTS and RTS)
__STATIC_INLINE void | LL_USART_EnableOneBitSamp (USART_TypeDef *USARTx)
Enable One bit sampling method.
__STATIC_INLINE void | LL_USART_DisableOneBitSamp (USART_TypeDef *USARTx)
Disable One bit sampling method.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledOneBitSamp (USART_TypeDef *USARTx)
Indicate if One bit sampling method is enabled.
__STATIC_INLINE void | LL_USART_EnableOverrunDetect (USART_TypeDef *USARTx)
Enable Overrun detection.
__STATIC_INLINE void | LL_USART_DisableOverrunDetect (USART_TypeDef *USARTx)
Disable Overrun detection.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledOverrunDetect (USART_TypeDef *USARTx)
Indicate if Overrun detection is enabled.
__STATIC_INLINE void | LL_USART_SetWKUPType (USART_TypeDef *USARTx, uint32_t Type)
Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE uint32_t | LL_USART_GetWKUPType (USART_TypeDef *USARTx)
Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
__STATIC_INLINE void | LL_USART_SetBaudRate (USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling, uint32_t BaudRate)
Configure USART BRR register for achieving expected Baud Rate value.
__STATIC_INLINE uint32_t | LL_USART_GetBaudRate (USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling)
Return current Baud Rate value, according to USARTDIV present in BRR register (full BRR content), and to used Peripheral Clock and Oversampling mode values.
__STATIC_INLINE void | LL_USART_SetRxTimeout (USART_TypeDef *USARTx, uint32_t Timeout)
Set Receiver Time Out Value (expressed in nb of bits duration)
__STATIC_INLINE uint32_t | LL_USART_GetRxTimeout (USART_TypeDef *USARTx)
Get Receiver Time Out Value (expressed in nb of bits duration)
__STATIC_INLINE void | LL_USART_SetBlockLength (USART_TypeDef *USARTx, uint32_t BlockLength)
Set Block Length value in reception.
__STATIC_INLINE uint32_t | LL_USART_GetBlockLength (USART_TypeDef *USARTx)
Get Block Length value in reception.
__STATIC_INLINE void | LL_USART_EnableIrda (USART_TypeDef *USARTx)
Enable IrDA mode.
__STATIC_INLINE void | LL_USART_DisableIrda (USART_TypeDef *USARTx)
Disable IrDA mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIrda (USART_TypeDef *USARTx)
Indicate if IrDA mode is enabled.
__STATIC_INLINE void | LL_USART_SetIrdaPowerMode (USART_TypeDef *USARTx, uint32_t PowerMode)
Configure IrDA Power Mode (Normal or Low Power)
__STATIC_INLINE uint32_t | LL_USART_GetIrdaPowerMode (USART_TypeDef *USARTx)
Retrieve IrDA Power Mode configuration (Normal or Low Power)
__STATIC_INLINE void | LL_USART_SetIrdaPrescaler (USART_TypeDef *USARTx, uint32_t PrescalerValue)
Set Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)
__STATIC_INLINE uint32_t | LL_USART_GetIrdaPrescaler (USART_TypeDef *USARTx)
Return Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)
__STATIC_INLINE void | LL_USART_EnableSmartcardNACK (USART_TypeDef *USARTx)
Enable Smartcard NACK transmission.
__STATIC_INLINE void | LL_USART_DisableSmartcardNACK (USART_TypeDef *USARTx)
Disable Smartcard NACK transmission.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSmartcardNACK (USART_TypeDef *USARTx)
Indicate if Smartcard NACK transmission is enabled.
__STATIC_INLINE void | LL_USART_EnableSmartcard (USART_TypeDef *USARTx)
Enable Smartcard mode.
__STATIC_INLINE void | LL_USART_DisableSmartcard (USART_TypeDef *USARTx)
Disable Smartcard mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSmartcard (USART_TypeDef *USARTx)
Indicate if Smartcard mode is enabled.
__STATIC_INLINE void | LL_USART_SetSmartcardAutoRetryCount (USART_TypeDef *USARTx, uint32_t AutoRetryCount)
Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardAutoRetryCount (USART_TypeDef *USARTx)
Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
__STATIC_INLINE void | LL_USART_SetSmartcardPrescaler (USART_TypeDef *USARTx, uint32_t PrescalerValue)
Set Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardPrescaler (USART_TypeDef *USARTx)
Return Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)
__STATIC_INLINE void | LL_USART_SetSmartcardGuardTime (USART_TypeDef *USARTx, uint32_t GuardTime)
Set Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardGuardTime (USART_TypeDef *USARTx)
Return Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)
__STATIC_INLINE void | LL_USART_EnableHalfDuplex (USART_TypeDef *USARTx)
Enable Single Wire Half-Duplex mode.
__STATIC_INLINE void | LL_USART_DisableHalfDuplex (USART_TypeDef *USARTx)
Disable Single Wire Half-Duplex mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledHalfDuplex (USART_TypeDef *USARTx)
Indicate if Single Wire Half-Duplex mode is enabled.
__STATIC_INLINE void | LL_USART_EnableSPISlave (USART_TypeDef *USARTx)
Enable SPI Synchronous Slave mode.
__STATIC_INLINE void | LL_USART_DisableSPISlave (USART_TypeDef *USARTx)
Disable SPI Synchronous Slave mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSPISlave (USART_TypeDef *USARTx)
Indicate if SPI Synchronous Slave mode is enabled.
__STATIC_INLINE void | LL_USART_EnableSPISlaveSelect (USART_TypeDef *USARTx)
Enable SPI Slave Selection using NSS input pin.
__STATIC_INLINE void | LL_USART_DisableSPISlaveSelect (USART_TypeDef *USARTx)
Disable SPI Slave Selection using NSS input pin.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSPISlaveSelect (USART_TypeDef *USARTx)
Indicate if SPI Slave Selection depends on NSS input pin.
__STATIC_INLINE void | LL_USART_SetLINBrkDetectionLen (USART_TypeDef *USARTx, uint32_t LINBDLength)
Set LIN Break Detection Length.
__STATIC_INLINE uint32_t | LL_USART_GetLINBrkDetectionLen (USART_TypeDef *USARTx)
Return LIN Break Detection Length.
__STATIC_INLINE void | LL_USART_EnableLIN (USART_TypeDef *USARTx)
Enable LIN mode.
__STATIC_INLINE void | LL_USART_DisableLIN (USART_TypeDef *USARTx)
Disable LIN mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledLIN (USART_TypeDef *USARTx)
Indicate if LIN mode is enabled.
__STATIC_INLINE void | LL_USART_SetDEDeassertionTime (USART_TypeDef *USARTx, uint32_t Time)
Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_USART_GetDEDeassertionTime (USART_TypeDef *USARTx)
Return DEDT (Driver Enable De-Assertion Time)
__STATIC_INLINE void | LL_USART_SetDEAssertionTime (USART_TypeDef *USARTx, uint32_t Time)
Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
__STATIC_INLINE uint32_t | LL_USART_GetDEAssertionTime (USART_TypeDef *USARTx)
Return DEAT (Driver Enable Assertion Time)
__STATIC_INLINE void | LL_USART_EnableDEMode (USART_TypeDef *USARTx)
Enable Driver Enable (DE) Mode.
__STATIC_INLINE void | LL_USART_DisableDEMode (USART_TypeDef *USARTx)
Disable Driver Enable (DE) Mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDEMode (USART_TypeDef *USARTx)
Indicate if Driver Enable (DE) Mode is enabled.
__STATIC_INLINE void | LL_USART_SetDESignalPolarity (USART_TypeDef *USARTx, uint32_t Polarity)
Select Driver Enable Polarity.
__STATIC_INLINE uint32_t | LL_USART_GetDESignalPolarity (USART_TypeDef *USARTx)
Return Driver Enable Polarity.
__STATIC_INLINE void | LL_USART_ConfigAsyncMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
__STATIC_INLINE void | LL_USART_ConfigSyncMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Synchronous Mode.
__STATIC_INLINE void | LL_USART_ConfigLINMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in LIN Mode.
__STATIC_INLINE void | LL_USART_ConfigHalfDuplexMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Half Duplex Mode.
__STATIC_INLINE void | LL_USART_ConfigSmartcardMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Smartcard Mode.
__STATIC_INLINE void | LL_USART_ConfigIrdaMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Irda Mode.
__STATIC_INLINE void | LL_USART_ConfigMultiProcessMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Multi processor Mode (several USARTs connected in a network, one of the USARTs can be the master, its TX output connected to the RX inputs of the other slaves USARTs).
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_PE (USART_TypeDef *USARTx)
Check if the USART Parity Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_FE (USART_TypeDef *USARTx)
Check if the USART Framing Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_NE (USART_TypeDef *USARTx)
Check if the USART Noise error detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_ORE (USART_TypeDef *USARTx)
Check if the USART OverRun Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_IDLE (USART_TypeDef *USARTx)
Check if the USART IDLE line detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RXNE_RXFNE (USART_TypeDef *USARTx)
Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TC (USART_TypeDef *USARTx)
Check if the USART Transmission Complete Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TXE_TXFNF (USART_TypeDef *USARTx)
Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_LBD (USART_TypeDef *USARTx)
Check if the USART LIN Break Detection Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_nCTS (USART_TypeDef *USARTx)
Check if the USART CTS interrupt Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_CTS (USART_TypeDef *USARTx)
Check if the USART CTS Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RTO (USART_TypeDef *USARTx)
Check if the USART Receiver Time Out Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_EOB (USART_TypeDef *USARTx)
Check if the USART End Of Block Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_UDR (USART_TypeDef *USARTx)
Check if the SPI Slave Underrun error flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_ABRE (USART_TypeDef *USARTx)
Check if the USART Auto-Baud Rate Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_ABR (USART_TypeDef *USARTx)
Check if the USART Auto-Baud Rate Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_BUSY (USART_TypeDef *USARTx)
Check if the USART Busy Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_CM (USART_TypeDef *USARTx)
Check if the USART Character Match Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_SBK (USART_TypeDef *USARTx)
Check if the USART Send Break Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RWU (USART_TypeDef *USARTx)
Check if the USART Receive Wake Up from mute mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_WKUP (USART_TypeDef *USARTx)
Check if the USART Wake Up from stop mode Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TEACK (USART_TypeDef *USARTx)
Check if the USART Transmit Enable Acknowledge Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_REACK (USART_TypeDef *USARTx)
Check if the USART Receive Enable Acknowledge Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TXFE (USART_TypeDef *USARTx)
Check if the USART TX FIFO Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RXFF (USART_TypeDef *USARTx)
Check if the USART RX FIFO Full Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TCBGT (USART_TypeDef *USARTx)
Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TXFT (USART_TypeDef *USARTx)
Check if the USART TX FIFO Threshold Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RXFT (USART_TypeDef *USARTx)
Check if the USART RX FIFO Threshold Flag is set or not.
__STATIC_INLINE void | LL_USART_ClearFlag_PE (USART_TypeDef *USARTx)
Clear Parity Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_FE (USART_TypeDef *USARTx)
Clear Framing Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_NE (USART_TypeDef *USARTx)
Clear Noise Error detected Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_ORE (USART_TypeDef *USARTx)
Clear OverRun Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_IDLE (USART_TypeDef *USARTx)
Clear IDLE line detected Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_TXFE (USART_TypeDef *USARTx)
Clear TX FIFO Empty Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_TC (USART_TypeDef *USARTx)
Clear Transmission Complete Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_TCBGT (USART_TypeDef *USARTx)
Clear Smartcard Transmission Complete Before Guard Time Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_LBD (USART_TypeDef *USARTx)
Clear LIN Break Detection Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_nCTS (USART_TypeDef *USARTx)
Clear CTS Interrupt Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_RTO (USART_TypeDef *USARTx)
Clear Receiver Time Out Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_EOB (USART_TypeDef *USARTx)
Clear End Of Block Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_UDR (USART_TypeDef *USARTx)
Clear SPI Slave Underrun Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_CM (USART_TypeDef *USARTx)
Clear Character Match Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_WKUP (USART_TypeDef *USARTx)
Clear Wake Up from stop mode Flag.
__STATIC_INLINE void | LL_USART_EnableIT_IDLE (USART_TypeDef *USARTx)
Enable IDLE Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RXNE_RXFNE (USART_TypeDef *USARTx)
Enable RX Not Empty and RX FIFO Not Empty Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TC (USART_TypeDef *USARTx)
Enable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TXE_TXFNF (USART_TypeDef *USARTx)
Enable TX Empty and TX FIFO Not Full Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_PE (USART_TypeDef *USARTx)
Enable Parity Error Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_CM (USART_TypeDef *USARTx)
Enable Character Match Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RTO (USART_TypeDef *USARTx)
Enable Receiver Timeout Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_EOB (USART_TypeDef *USARTx)
Enable End Of Block Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TXFE (USART_TypeDef *USARTx)
Enable TX FIFO Empty Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RXFF (USART_TypeDef *USARTx)
Enable RX FIFO Full Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_LBD (USART_TypeDef *USARTx)
Enable LIN Break Detection Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_ERROR (USART_TypeDef *USARTx)
Enable Error Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_CTS (USART_TypeDef *USARTx)
Enable CTS Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_WKUP (USART_TypeDef *USARTx)
Enable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TXFT (USART_TypeDef *USARTx)
Enable TX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TCBGT (USART_TypeDef *USARTx)
Enable Smartcard Transmission Complete Before Guard Time Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RXFT (USART_TypeDef *USARTx)
Enable RX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_IDLE (USART_TypeDef *USARTx)
Disable IDLE Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RXNE_RXFNE (USART_TypeDef *USARTx)
Disable RX Not Empty and RX FIFO Not Empty Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TC (USART_TypeDef *USARTx)
Disable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TXE_TXFNF (USART_TypeDef *USARTx)
Disable TX Empty and TX FIFO Not Full Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_PE (USART_TypeDef *USARTx)
Disable Parity Error Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_CM (USART_TypeDef *USARTx)
Disable Character Match Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RTO (USART_TypeDef *USARTx)
Disable Receiver Timeout Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_EOB (USART_TypeDef *USARTx)
Disable End Of Block Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TXFE (USART_TypeDef *USARTx)
Disable TX FIFO Empty Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RXFF (USART_TypeDef *USARTx)
Disable RX FIFO Full Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_LBD (USART_TypeDef *USARTx)
Disable LIN Break Detection Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_ERROR (USART_TypeDef *USARTx)
Disable Error Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_CTS (USART_TypeDef *USARTx)
Disable CTS Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_WKUP (USART_TypeDef *USARTx)
Disable Wake Up from Stop Mode Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TXFT (USART_TypeDef *USARTx)
Disable TX FIFO Threshold Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TCBGT (USART_TypeDef *USARTx)
Disable Smartcard Transmission Complete Before Guard Time Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RXFT (USART_TypeDef *USARTx)
Disable RX FIFO Threshold Interrupt.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_IDLE (USART_TypeDef *USARTx)
Check if the USART IDLE Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RXNE_RXFNE (USART_TypeDef *USARTx)
Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TC (USART_TypeDef *USARTx)
Check if the USART Transmission Complete Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TXE_TXFNF (USART_TypeDef *USARTx)
Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_PE (USART_TypeDef *USARTx)
Check if the USART Parity Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_CM (USART_TypeDef *USARTx)
Check if the USART Character Match Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RTO (USART_TypeDef *USARTx)
Check if the USART Receiver Timeout Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_EOB (USART_TypeDef *USARTx)
Check if the USART End Of Block Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TXFE (USART_TypeDef *USARTx)
Check if the USART TX FIFO Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RXFF (USART_TypeDef *USARTx)
Check if the USART RX FIFO Full Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_LBD (USART_TypeDef *USARTx)
Check if the USART LIN Break Detection Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_ERROR (USART_TypeDef *USARTx)
Check if the USART Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_CTS (USART_TypeDef *USARTx)
Check if the USART CTS Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_WKUP (USART_TypeDef *USARTx)
Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TXFT (USART_TypeDef *USARTx)
Check if USART TX FIFO Threshold Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TCBGT (USART_TypeDef *USARTx)
Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RXFT (USART_TypeDef *USARTx)
Check if USART RX FIFO Threshold Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_USART_EnableDMAReq_RX (USART_TypeDef *USARTx)
Enable DMA Mode for reception.
__STATIC_INLINE void | LL_USART_DisableDMAReq_RX (USART_TypeDef *USARTx)
Disable DMA Mode for reception.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMAReq_RX (USART_TypeDef *USARTx)
Check if DMA Mode is enabled for reception.
__STATIC_INLINE void | LL_USART_EnableDMAReq_TX (USART_TypeDef *USARTx)
Enable DMA Mode for transmission.
__STATIC_INLINE void | LL_USART_DisableDMAReq_TX (USART_TypeDef *USARTx)
Disable DMA Mode for transmission.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMAReq_TX (USART_TypeDef *USARTx)
Check if DMA Mode is enabled for transmission.
__STATIC_INLINE void | LL_USART_EnableDMADeactOnRxErr (USART_TypeDef *USARTx)
Enable DMA Disabling on Reception Error.
__STATIC_INLINE void | LL_USART_DisableDMADeactOnRxErr (USART_TypeDef *USARTx)
Disable DMA Disabling on Reception Error.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMADeactOnRxErr (USART_TypeDef *USARTx)
Indicate if DMA Disabling on Reception Error is disabled.
__STATIC_INLINE uint32_t | LL_USART_DMA_GetRegAddr (USART_TypeDef *USARTx, uint32_t Direction)
Get the data register address used for DMA transfer.
__STATIC_INLINE uint8_t | LL_USART_ReceiveData8 (USART_TypeDef *USARTx)
Read Receiver Data register (Receive Data value, 8 bits)
__STATIC_INLINE uint16_t | LL_USART_ReceiveData9 (USART_TypeDef *USARTx)
Read Receiver Data register (Receive Data value, 9 bits)
__STATIC_INLINE void | LL_USART_TransmitData8 (USART_TypeDef *USARTx, uint8_t Value)
Write in Transmitter Data Register (Transmit Data value, 8 bits)
__STATIC_INLINE void | LL_USART_TransmitData9 (USART_TypeDef *USARTx, uint16_t Value)
Write in Transmitter Data Register (Transmit Data value, 9 bits)
__STATIC_INLINE void | LL_USART_RequestAutoBaudRate (USART_TypeDef *USARTx)
Request an Automatic Baud Rate measurement on next received data frame.
__STATIC_INLINE void | LL_USART_RequestBreakSending (USART_TypeDef *USARTx)
Request Break sending.
__STATIC_INLINE void | LL_USART_RequestEnterMuteMode (USART_TypeDef *USARTx)
Put USART in mute mode and set the RWU flag.
__STATIC_INLINE void | LL_USART_RequestRxDataFlush (USART_TypeDef *USARTx)
Request a Receive Data and FIFO flush.
__STATIC_INLINE void | LL_USART_RequestTxDataFlush (USART_TypeDef *USARTx)
Request a Transmit data and FIFO flush.
ErrorStatus | LL_USART_DeInit (USART_TypeDef *USARTx)
De-initialize USART registers (Registers restored to their default values).
ErrorStatus | LL_USART_Init (USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
Initialize USART registers according to the specified parameters in USART_InitStruct.
void | LL_USART_StructInit (LL_USART_InitTypeDef *USART_InitStruct)
Set each LL_USART_InitTypeDef field to default value.
ErrorStatus | LL_USART_ClockInit (USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Initialize USART Clock related settings according to the specified parameters in the USART_ClockInitStruct.
void | LL_USART_ClockStructInit (LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Set each field of a LL_USART_ClockInitTypeDef type structure to default value.

Variables

static const uint16_t | USART_PRESCALER_TAB []

Detailed Description

Header file of USART LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_usart.h.

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_utils.h File Reference

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Data Structures | Defines | Functions
stm32wbxx_ll_utils.h File Reference

Header file of UTILS LL module. More...

#include "stm32wbxx.h"

Go to the source code of this file.

Data Structures

struct | LL_UTILS_PLLInitTypeDef
UTILS PLL structure definition. More...
struct | LL_UTILS_ClkInitTypeDef
UTILS System, AHB and APB buses clock configuration structure definition. More...

Defines

#define | LL_MAX_DELAY 0xFFFFFFFFU
#define | UID_BASE_ADDRESS UID_BASE
Unique device ID register base address.
#define | FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
Flash size data register base address.
#define | PACKAGE_BASE_ADDRESS PACKAGE_BASE
Package data register base address.
#define | LL_UTILS_HSEBYPASS_OFF 0x00000000U
#define | LL_UTILS_HSEBYPASS_ON 0x00000001U
#define | LL_UTILS_PACKAGETYPE_CSP100 0x00000011U
#define | LL_UTILS_PACKAGETYPE_CSP100_C 0x00000012U
#define | LL_UTILS_PACKAGETYPE_QFN68 0x00000013U
#define | LL_UTILS_PACKAGETYPE_QFN68_C 0x00000014U
#define | LL_UTILS_PACKAGETYPE_QFN48 0x0000000AU
#define | LL_UTILS_PACKAGETYPE_QFN48_C 0x00000015U

Functions

__STATIC_INLINE uint32_t | LL_GetUID_Word0 (void)
Get Word0 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetUID_Word1 (void)
Get Word1 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetUID_Word2 (void)
Get Word2 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetFlashSize (void)
Get Flash memory size.
__STATIC_INLINE uint32_t | LL_GetPackageType (void)
Get Package type.
__STATIC_INLINE void | LL_InitTick (uint32_t HCLKFrequency, uint32_t Ticks)
This function configures the Cortex-M SysTick source of the time base.
void | LL_Init1msTick (uint32_t HCLKFrequency)
This function configures the Cortex-M SysTick source to have 1ms time base.
void | LL_mDelay (uint32_t Delay)
This function provides accurate delay (in milliseconds) based on SysTick counter flag.
void | LL_SetSystemCoreClock (uint32_t HCLKFrequency)
This function sets directly SystemCoreClock CMSIS variable.
ErrorStatus | LL_PLL_ConfigSystemClock_MSI (LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock with MSI as clock source of the PLL.
ErrorStatus | LL_PLL_ConfigSystemClock_HSI (LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock at maximum frequency with HSI as clock source of the PLL.
ErrorStatus | LL_PLL_ConfigSystemClock_HSE (uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock with HSE as clock source of the PLL.

Detailed Description

Header file of UTILS LL module.

Author:
MCD Application Team
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The LL UTILS driver contains a set of generic APIs that can be
    used by user:
      (+) Device electronic signature
      (+) Timing functions
      (+) PLL configuration functions
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_utils.h.

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_wwdg.h File Reference

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Defines | Functions
stm32wbxx_ll_wwdg.h File Reference

Header file of WWDG LL module. More...

#include "stm32wbxx.h"

Go to the source code of this file.

Defines

#define | LL_WWDG_CFR_EWI WWDG_CFR_EWI
#define | LL_WWDG_PRESCALER_1 0x00000000u
#define | LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0
#define | LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1
#define | LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1)
#define | LL_WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2
#define | LL_WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0)
#define | LL_WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1)
#define | LL_WWDG_PRESCALER_128 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)
#define | LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in WWDG register.
#define | LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in WWDG register.

Functions

__STATIC_INLINE void | LL_WWDG_Enable (WWDG_TypeDef *WWDGx)
Enable Window Watchdog.
__STATIC_INLINE uint32_t | LL_WWDG_IsEnabled (WWDG_TypeDef *WWDGx)
Checks if Window Watchdog is enabled.
__STATIC_INLINE void | LL_WWDG_SetCounter (WWDG_TypeDef *WWDGx, uint32_t Counter)
Set the Watchdog counter value to provided value (7-bits T[6:0])
__STATIC_INLINE uint32_t | LL_WWDG_GetCounter (WWDG_TypeDef *WWDGx)
Return current Watchdog Counter Value (7 bits counter value)
__STATIC_INLINE void | LL_WWDG_SetPrescaler (WWDG_TypeDef *WWDGx, uint32_t Prescaler)
Set the time base of the prescaler (WDGTB).
__STATIC_INLINE uint32_t | LL_WWDG_GetPrescaler (WWDG_TypeDef *WWDGx)
Return current Watchdog Prescaler Value.
__STATIC_INLINE void | LL_WWDG_SetWindow (WWDG_TypeDef *WWDGx, uint32_t Window)
Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
__STATIC_INLINE uint32_t | LL_WWDG_GetWindow (WWDG_TypeDef *WWDGx)
Return current Watchdog Window Value (7 bits value)
__STATIC_INLINE uint32_t | LL_WWDG_IsActiveFlag_EWKUP (WWDG_TypeDef *WWDGx)
Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
__STATIC_INLINE void | LL_WWDG_ClearFlag_EWKUP (WWDG_TypeDef *WWDGx)
Clear WWDG Early Wakeup Interrupt Flag (EWIF)
__STATIC_INLINE void | LL_WWDG_EnableIT_EWKUP (WWDG_TypeDef *WWDGx)
Enable the Early Wakeup Interrupt.
__STATIC_INLINE uint32_t | LL_WWDG_IsEnabledIT_EWKUP (WWDG_TypeDef *WWDGx)
Check if Early Wakeup Interrupt is enabled.

Detailed Description

Header file of WWDG LL module.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_wwdg.h.

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal.c File Reference

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stm32wbxx_hal.c File Reference

HAL module driver. This is the common part of the HAL initialization. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Defines

#define | __STM32WBxx_HAL_VERSION_MAIN (0x01U)
STM32WBxx HAL Driver version number.
#define | __STM32WBxx_HAL_VERSION_SUB1 (0x03U)
#define | __STM32WBxx_HAL_VERSION_SUB2 (0x00U)
#define | __STM32WBxx_HAL_VERSION_RC (0x00U)
#define | __STM32WBxx_HAL_VERSION
#define | VREFBUF_TIMEOUT_VALUE 10U /* 10 ms */

Functions

HAL_StatusTypeDef | HAL_Init (void)
This function is used to initialize the HAL Library; it must be the first instruction to be executed in the main program (before to call any other HAL function), it performs the following: Configure the Flash prefetch, instruction and Data caches.
HAL_StatusTypeDef | HAL_DeInit (void)
This function de-Initializes common part of the HAL and stops the source of time base.
__weak void | HAL_MspInit (void)
Initialize the MSP.
__weak void | HAL_MspDeInit (void)
DeInitializes the MSP.
__weak HAL_StatusTypeDef | HAL_InitTick (uint32_t TickPriority)
This function configures the source of the time base: The time source is configured to have 1ms time base with a dedicated Tick interrupt priority.
__weak void | HAL_IncTick (void)
This function is called to increment a global variable "uwTick" used as application time base.
__weak uint32_t | HAL_GetTick (void)
Provides a tick value in millisecond.
uint32_t | HAL_GetTickPrio (void)
This function returns a tick priority.
HAL_StatusTypeDef | HAL_SetTickFreq (uint32_t Freq)
Set new tick Freq.
uint32_t | HAL_GetTickFreq (void)
Return tick frequency.
__weak void | HAL_Delay (uint32_t Delay)
This function provides minimum delay (in milliseconds) based on variable incremented.
__weak void | HAL_SuspendTick (void)
Suspend Tick increment.
__weak void | HAL_ResumeTick (void)
Resume Tick increment.
uint32_t | HAL_GetHalVersion (void)
Returns the HAL revision.
uint32_t | HAL_GetREVID (void)
Returns the device revision identifier.
uint32_t | HAL_GetDEVID (void)
Returns the device identifier.
uint32_t | HAL_GetUIDw0 (void)
Return the first word of the unique device identifier (UID based on 96 bits)
uint32_t | HAL_GetUIDw1 (void)
Return the second word of the unique device identifier (UID based on 96 bits)
uint32_t | HAL_GetUIDw2 (void)
Return the third word of the unique device identifier (UID based on 96 bits)
void | HAL_DBGMCU_EnableDBGSleepMode (void)
Enable the Debug Module during SLEEP mode.
void | HAL_DBGMCU_DisableDBGSleepMode (void)
Disable the Debug Module during SLEEP mode.
void | HAL_DBGMCU_EnableDBGStopMode (void)
Enable the Debug Module during STOP mode.
void | HAL_DBGMCU_DisableDBGStopMode (void)
Disable the Debug Module during STOP mode.
void | HAL_DBGMCU_EnableDBGStandbyMode (void)
Enable the Debug Module during STANDBY mode.
void | HAL_DBGMCU_DisableDBGStandbyMode (void)
Disable the Debug Module during STANDBY mode.
void | HAL_SYSCFG_SRAM2Erase (void)
Start a hardware SRAM2 erase operation.
void | HAL_SYSCFG_DisableSRAMFetch (void)
Disable CPU2 SRAM fetch (execution) (This bit can be set by Firmware and will only be reset by a Hardware reset, including a reset after Standby.)
uint32_t | HAL_SYSCFG_IsEnabledSRAMFetch (void)
Check if CPU2 SRAM fetch is enabled.
void | HAL_SYSCFG_VREFBUF_VoltageScalingConfig (uint32_t VoltageScaling)
Configure the internal voltage reference buffer voltage scale.
void | HAL_SYSCFG_VREFBUF_HighImpedanceConfig (uint32_t Mode)
Configure the internal voltage reference buffer high impedance mode.
void | HAL_SYSCFG_VREFBUF_TrimmingConfig (uint32_t TrimmingValue)
Tune the Internal Voltage Reference buffer (VREFBUF).
HAL_StatusTypeDef | HAL_SYSCFG_EnableVREFBUF (void)
Enable the Internal Voltage Reference buffer (VREFBUF).
void | HAL_SYSCFG_DisableVREFBUF (void)
Disable the Internal Voltage Reference buffer (VREFBUF).
void | HAL_SYSCFG_EnableIOBooster (void)
Enable the I/O analog switch voltage booster.
void | HAL_SYSCFG_DisableIOBooster (void)
Disable the I/O analog switch voltage booster.
void | HAL_SYSCFG_EnableIOVdd (void)
Enable the I/O analog switch supplied by VDD.
void | HAL_SYSCFG_DisableIOVdd (void)
Disable the I/O analog switch supplied by VDD.
void | HAL_SYSCFG_EnableSecurityAccess (uint32_t SecurityAccess)
Enable the access for security IP.
void | HAL_SYSCFG_DisableSecurityAccess (uint32_t SecurityAccess)
Disable the access for security IP.
uint32_t | HAL_SYSCFG_IsEnabledSecurityAccess (uint32_t SecurityAccess)
Indicate if access for security IP is enabled.

Variables

__IO uint32_t | uwTick
uint32_t | uwTickPrio = (1UL << __NVIC_PRIO_BITS)
uint32_t | uwTickFreq = HAL_TICK_FREQ_DEFAULT

Detailed Description

HAL module driver. This is the common part of the HAL initialization.

Author:
MCD Application Team
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The common HAL driver contains a set of generic and common APIs that can be
    used by the PPP peripheral drivers and the user to start using the HAL.
    [..]
    The HAL contains two APIs' categories:
         (+) Common HAL APIs
         (+) Services HAL APIs
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal.c.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_adc.c File Reference

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stm32wbxx_hal_adc.c File Reference

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Initialization and de-initialization functions ++ Initialization and Configuration of ADC + Operation functions ++ Start, stop, get result of conversions of regular group, using 3 possible modes: polling, interruption or DMA. + Control functions ++ Channels configuration on regular group ++ Analog Watchdog configuration + State functions ++ ADC state machine management ++ Interrupts and flags management Other functions (extended functions) are available in file "stm32wbxx_hal_adc_ex.c". More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Defines

#define | ADC_CFGR_FIELDS_1
#define | ADC_ENABLE_TIMEOUT (2UL)
#define | ADC_DISABLE_TIMEOUT (2UL)
#define | ADC_CONVERSION_TIME_MAX_CPU_CYCLES (653UL * 4096UL * 256UL)

Functions

HAL_StatusTypeDef | HAL_ADC_Init (ADC_HandleTypeDef *hadc)
Initialize the ADC peripheral and regular group according to parameters specified in structure "ADC_InitTypeDef".
HAL_StatusTypeDef | HAL_ADC_DeInit (ADC_HandleTypeDef *hadc)
Deinitialize the ADC peripheral registers to their default reset values, with deinitialization of the ADC MSP.
__weak void | HAL_ADC_MspInit (ADC_HandleTypeDef *hadc)
Initialize the ADC MSP.
__weak void | HAL_ADC_MspDeInit (ADC_HandleTypeDef *hadc)
DeInitialize the ADC MSP.
HAL_StatusTypeDef | HAL_ADC_RegisterCallback (ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
Register a User ADC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_ADC_UnRegisterCallback (ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
Unregister a ADC Callback ADC callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_ADC_Start (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of regular group.
HAL_StatusTypeDef | HAL_ADC_Stop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_PollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for regular group conversion to be completed.
HAL_StatusTypeDef | HAL_ADC_PollForEvent (ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
Poll for ADC event.
HAL_StatusTypeDef | HAL_ADC_Start_IT (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of regular group with interruption.
HAL_StatusTypeDef | HAL_ADC_Stop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable interrution of end-of-conversion, disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_Start_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enable ADC, start conversion of regular group and transfer result through DMA.
HAL_StatusTypeDef | HAL_ADC_Stop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral.
uint32_t | HAL_ADC_GetValue (ADC_HandleTypeDef *hadc)
Get ADC regular group conversion result.
void | HAL_ADC_IRQHandler (ADC_HandleTypeDef *hadc)
Handle ADC interrupt request.
__weak void | HAL_ADC_ConvCpltCallback (ADC_HandleTypeDef *hadc)
Conversion complete callback in non-blocking mode.
__weak void | HAL_ADC_ConvHalfCpltCallback (ADC_HandleTypeDef *hadc)
Conversion DMA half-transfer callback in non-blocking mode.
__weak void | HAL_ADC_LevelOutOfWindowCallback (ADC_HandleTypeDef *hadc)
Analog watchdog 1 callback in non-blocking mode.
__weak void | HAL_ADC_ErrorCallback (ADC_HandleTypeDef *hadc)
ADC error callback in non-blocking mode (ADC conversion with interruption or transfer by DMA).
HAL_StatusTypeDef | HAL_ADC_ConfigChannel (ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
Configure a channel to be assigned to ADC group regular.
HAL_StatusTypeDef | HAL_ADC_AnalogWDGConfig (ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
Configure the analog watchdog.
uint32_t | HAL_ADC_GetState (ADC_HandleTypeDef *hadc)
Return the ADC handle state.
uint32_t | HAL_ADC_GetError (ADC_HandleTypeDef *hadc)
Return the ADC error code.
HAL_StatusTypeDef | ADC_ConversionStop (ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
Stop ADC conversion.
HAL_StatusTypeDef | ADC_Enable (ADC_HandleTypeDef *hadc)
Enable the selected ADC.
HAL_StatusTypeDef | ADC_Disable (ADC_HandleTypeDef *hadc)
Disable the selected ADC.
void | ADC_DMAConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
void | ADC_DMAHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
void | ADC_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.

Detailed Description

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Initialization and de-initialization functions ++ Initialization and Configuration of ADC + Operation functions ++ Start, stop, get result of conversions of regular group, using 3 possible modes: polling, interruption or DMA. + Control functions ++ Channels configuration on regular group ++ Analog Watchdog configuration + State functions ++ ADC state machine management ++ Interrupts and flags management Other functions (extended functions) are available in file "stm32wbxx_hal_adc_ex.c".

Author:
MCD Application Team
  ==============================================================================
                     ##### ADC peripheral features #####
  ==============================================================================
  [..]
  (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.

  (+) Interrupt generation at the end of regular conversion and in case of
      analog watchdog or overrun events.

  (+) Single and continuous conversion modes.

  (+) Scan mode for conversion of several channels sequentially.

  (+) Data alignment with in-built data coherency.

  (+) Programmable sampling time (channel wise)

  (+) External trigger (timer or EXTI) with configurable polarity

  (+) DMA request generation for transfer of conversions data of regular group.

  (+) ADC channels selectable single/differential input.

  (+) ADC offset shared on 4 offset instances.
  (+) ADC calibration

  (+) ADC conversion of regular group.

  (+) ADC supply requirements: 1.62 V to 3.6 V.

  (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
      Vdda or to an external voltage reference).

                     ##### How to use this driver #####
  ==============================================================================
    [..]

     *** Configuration of top level parameters related to ADC ***
     ============================================================
     [..]

    (#) Enable the ADC interface
        (++) As prerequisite, ADC clock must be configured at RCC top level.

        (++) Two clock settings are mandatory:
             (+++) ADC clock (core clock, also possibly conversion clock).

             (+++) ADC clock (conversions clock).
                   Two possible clock sources: synchronous clock derived from AHB2 clock
                   or asynchronous clock derived from system clock, PLLSAI1 (output divider R) or the PLL system (output divider P)
                   running up to 64MHz.

             (+++) Example:
                   Into HAL_ADC_MspInit() (recommended code location) or with
                   other device clock parameters configuration:
               (+++) __HAL_RCC_ADC_CLK_ENABLE();                  (mandatory)

               RCC_ADCCLKSOURCE_PLL enable:                       (optional: if asynchronous clock selected)
               (+++) RCC_PeriphClkInitTypeDef   RCC_PeriphClkInit;
               (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
               (+++) PeriphClkInit.AdcClockSelection    = RCC_ADCCLKSOURCE_PLL;
               (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);

        (++) ADC clock source and clock prescaler are configured at ADC level with
             parameter "ClockPrescaler" using function HAL_ADC_Init().

    (#) ADC pins configuration
         (++) Enable the clock for the ADC GPIOs
              using macro __HAL_RCC_GPIOx_CLK_ENABLE()
         (++) Configure these ADC pins in analog mode
              using function HAL_GPIO_Init()

    (#) Optionally, in case of usage of ADC with interruptions:
         (++) Configure the NVIC for ADC
              using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
              into the function of corresponding ADC interruption vector
              ADCx_IRQHandler().

    (#) Optionally, in case of usage of DMA:
         (++) Configure the DMA (DMA channel, mode normal or circular, ...)
              using function HAL_DMA_Init().
         (++) Configure the NVIC for DMA
              using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
              into the function of corresponding DMA interruption vector
              DMAx_Channelx_IRQHandler().

     *** Configuration of ADC, group regular, channels parameters ***
     ================================================================
     [..]

    (#) Configure the ADC parameters (resolution, data alignment, ...)
        and regular group parameters (conversion trigger, sequencer, ...)
        using function HAL_ADC_Init().

    (#) Configure the channels for regular group parameters (channel number,
        channel rank into sequencer, ..., into regular group)
        using function HAL_ADC_ConfigChannel().

    (#) Optionally, configure the analog watchdog parameters (channels
        monitored, thresholds, ...)
        using function HAL_ADC_AnalogWDGConfig().

     *** Execution of ADC conversions ***
     ====================================
     [..]

    (#) Optionally, perform an automatic ADC calibration to improve the
        conversion accuracy
        using function HAL_ADCEx_Calibration_Start().

    (#) ADC driver can be used among three modes: polling, interruption,
        transfer by DMA.

        (++) ADC conversion by polling:
          (+++) Activate the ADC peripheral and start conversions
                using function HAL_ADC_Start()
          (+++) Wait for ADC conversion completion
                using function HAL_ADC_PollForConversion()
          (+++) Retrieve conversion results
                using function HAL_ADC_GetValue()
          (+++) Stop conversion and disable the ADC peripheral
                using function HAL_ADC_Stop()

        (++) ADC conversion by interruption:
          (+++) Activate the ADC peripheral and start conversions
                using function HAL_ADC_Start_IT()
          (+++) Wait for ADC conversion completion by call of function
                HAL_ADC_ConvCpltCallback()
                (this function must be implemented in user program)
          (+++) Retrieve conversion results
                using function HAL_ADC_GetValue()
          (+++) Stop conversion and disable the ADC peripheral
                using function HAL_ADC_Stop_IT()

        (++) ADC conversion with transfer by DMA:
          (+++) Activate the ADC peripheral and start conversions
                using function HAL_ADC_Start_DMA()
          (+++) Wait for ADC conversion completion by call of function
                HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
                (these functions must be implemented in user program)
          (+++) Conversion results are automatically transferred by DMA into
                destination variable address.
          (+++) Stop conversion and disable the ADC peripheral
                using function HAL_ADC_Stop_DMA()

     [..]

    (@) Callback functions must be implemented in user program:
      (+@) HAL_ADC_ErrorCallback()
      (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
      (+@) HAL_ADC_ConvCpltCallback()
      (+@) HAL_ADC_ConvHalfCpltCallback

     *** Deinitialization of ADC ***
     ============================================================
     [..]

    (#) Disable the ADC interface
      (++) ADC clock can be hard reset and disabled at RCC top level.
        (++) Hard reset of ADC peripherals
             using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
        (++) ADC clock disable
             using the equivalent macro/functions as configuration step.
             (+++) Example:
                   Into HAL_ADC_MspDeInit() (recommended code location) or with
                   other device clock parameters configuration:
               (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14;
               (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock)
               (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);

    (#) ADC pins configuration
         (++) Disable the clock for the ADC GPIOs
              using macro __HAL_RCC_GPIOx_CLK_DISABLE()

    (#) Optionally, in case of usage of ADC with interruptions:
         (++) Disable the NVIC for ADC
              using function HAL_NVIC_EnableIRQ(ADCx_IRQn)

    (#) Optionally, in case of usage of DMA:
         (++) Deinitialize the DMA
              using function HAL_DMA_Init().
         (++) Disable the NVIC for DMA
              using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)

    [..]

    *** Callback registration ***
    =============================================
    [..]

     The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
     allows the user to configure dynamically the driver callbacks.
     Use Functions @ref HAL_ADC_RegisterCallback()
     to register an interrupt callback.
    [..]

     Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks:
       (+) ConvCpltCallback               : ADC conversion complete callback
       (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
       (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
       (+) ErrorCallback                  : ADC error callback
       (+) InjectedConvCpltCallback       : ADC group injected conversion complete callback
       (+) InjectedQueueOverflowCallback  : ADC group injected context queue overflow callback
       (+) LevelOutOfWindow2Callback      : ADC analog watchdog 2 callback
       (+) LevelOutOfWindow3Callback      : ADC analog watchdog 3 callback
       (+) EndOfSamplingCallback          : ADC end of sampling callback
       (+) MspInitCallback                : ADC Msp Init callback
       (+) MspDeInitCallback              : ADC Msp DeInit callback
     This function takes as parameters the HAL peripheral handle, the Callback ID
     and a pointer to the user callback function.
    [..]

     Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default
     weak function.
    [..]

     @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
     and the Callback ID.
     This function allows to reset following callbacks:
       (+) ConvCpltCallback               : ADC conversion complete callback
       (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
       (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
       (+) ErrorCallback                  : ADC error callback
       (+) InjectedConvCpltCallback       : ADC group injected conversion complete callback
       (+) InjectedQueueOverflowCallback  : ADC group injected context queue overflow callback
       (+) LevelOutOfWindow2Callback      : ADC analog watchdog 2 callback
       (+) LevelOutOfWindow3Callback      : ADC analog watchdog 3 callback
       (+) EndOfSamplingCallback          : ADC end of sampling callback
       (+) MspInitCallback                : ADC Msp Init callback
       (+) MspDeInitCallback              : ADC Msp DeInit callback
     [..]

     By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET
     all callbacks are set to the corresponding weak functions:
     examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback().
     Exception done for MspInit and MspDeInit functions that are
     reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when
     these callbacks are null (not registered beforehand).
    [..]

     If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit()
     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
     [..]

     Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only.
     Exception done MspInit/MspDeInit functions that can be registered/unregistered
     in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state,
     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
    [..]

     Then, the user first registers the MspInit/MspDeInit user callbacks
     using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit()
     or @ref HAL_ADC_Init() function.
     [..]

     When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
     not defined, the callback registration feature is not available and all callbacks
     are set to the corresponding weak functions.
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_adc.c.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_adc_ex.c File Reference

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Defines | Functions
stm32wbxx_hal_adc_ex.c File Reference

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Operation functions ++ Start, stop, get result of conversions of ADC group injected, using 2 possible modes: polling, interruption. ++ Calibration +++ ADC automatic self-calibration +++ Calibration factors get or set + Control functions ++ Channels configuration on ADC group injected + State functions ++ ADC group injected contexts queue management Other functions (generic functions) are available in file "stm32wbxx_hal_adc.c". More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Defines

#define | ADC_JSQR_FIELDS
#define | ADC_CALIBRATION_TIMEOUT (158379UL)

Functions

HAL_StatusTypeDef | HAL_ADCEx_Calibration_Start (ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
Perform an ADC automatic self-calibration Calibration prerequisite: ADC must be disabled (execute this function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
uint32_t | HAL_ADCEx_Calibration_GetValue (ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
Get the calibration factor.
HAL_StatusTypeDef | HAL_ADCEx_Calibration_SetValue (ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
Set the calibration factor to overwrite automatic conversion result.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of injected group.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels.
HAL_StatusTypeDef | HAL_ADCEx_InjectedPollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for injected group conversion to be completed.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart_IT (ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of injected group with interruption.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop_IT (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels, disable interruption of end-of-conversion.
uint32_t | HAL_ADCEx_InjectedGetValue (ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
Get ADC injected group conversion result.
__weak void | HAL_ADCEx_InjectedConvCpltCallback (ADC_HandleTypeDef *hadc)
Injected conversion complete callback in non-blocking mode.
__weak void | HAL_ADCEx_InjectedQueueOverflowCallback (ADC_HandleTypeDef *hadc)
Injected context queue overflow callback.
__weak void | HAL_ADCEx_LevelOutOfWindow2Callback (ADC_HandleTypeDef *hadc)
Analog watchdog 2 callback in non-blocking mode.
__weak void | HAL_ADCEx_LevelOutOfWindow3Callback (ADC_HandleTypeDef *hadc)
Analog watchdog 3 callback in non-blocking mode.
__weak void | HAL_ADCEx_EndOfSamplingCallback (ADC_HandleTypeDef *hadc)
End Of Sampling callback in non-blocking mode.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral if no conversion is on going on injected group.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of ADC groups regular and injected, disable interrution of end-of-conversion, disable ADC peripheral if no conversion is on going on injected group.
HAL_StatusTypeDef | HAL_ADCEx_RegularStop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral if no conversion is on going on injected group.
HAL_StatusTypeDef | HAL_ADCEx_InjectedConfigChannel (ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected)
Configure a channel to be assigned to ADC group injected.
HAL_StatusTypeDef | HAL_ADCEx_EnableInjectedQueue (ADC_HandleTypeDef *hadc)
Enable Injected Queue.
HAL_StatusTypeDef | HAL_ADCEx_DisableInjectedQueue (ADC_HandleTypeDef *hadc)
Disable Injected Queue.
HAL_StatusTypeDef | HAL_ADCEx_DisableVoltageRegulator (ADC_HandleTypeDef *hadc)
Disable ADC voltage regulator.
HAL_StatusTypeDef | HAL_ADCEx_EnterADCDeepPowerDownMode (ADC_HandleTypeDef *hadc)
Enter ADC deep-power-down mode.

Detailed Description

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Operation functions ++ Start, stop, get result of conversions of ADC group injected, using 2 possible modes: polling, interruption. ++ Calibration +++ ADC automatic self-calibration +++ Calibration factors get or set + Control functions ++ Channels configuration on ADC group injected + State functions ++ ADC group injected contexts queue management Other functions (generic functions) are available in file "stm32wbxx_hal_adc.c".

Author:
MCD Application Team
  [..]
  (@) Sections "ADC peripheral features" and "How to use this driver" are
      available in file of generic functions "stm32wbxx_hal_adc.c".
  [..]
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_adc_ex.c.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_comp.c File Reference

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Defines | Functions
stm32wbxx_hal_comp.c File Reference

COMP HAL module driver. This file provides firmware functions to manage the following functionalities of the COMP peripheral: + Initialization and de-initialization functions + Start/Stop operation functions in polling mode + Start/Stop operation functions in interrupt mode (through EXTI interrupt) + Peripheral control functions + Peripheral state functions. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Defines

#define | COMP_DELAY_STARTUP_US (80UL)
#define | COMP_DELAY_VOLTAGE_SCALER_STAB_US (200UL)
#define | COMP_OUTPUT_LEVEL_BITOFFSET_POS (30UL)

Functions

HAL_StatusTypeDef | HAL_COMP_Init (COMP_HandleTypeDef *hcomp)
Initialize the COMP according to the specified parameters in the COMP_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP peripheral.
__weak void | HAL_COMP_MspInit (COMP_HandleTypeDef *hcomp)
Initialize the COMP MSP.
__weak void | HAL_COMP_MspDeInit (COMP_HandleTypeDef *hcomp)
DeInitialize the COMP MSP.
HAL_StatusTypeDef | HAL_COMP_RegisterCallback (COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback)
Register a User COMP Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_COMP_UnRegisterCallback (COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID)
Unregister a COMP Callback COMP callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_COMP_Start (COMP_HandleTypeDef *hcomp)
Start the comparator.
HAL_StatusTypeDef | HAL_COMP_Stop (COMP_HandleTypeDef *hcomp)
Stop the comparator.
void | HAL_COMP_IRQHandler (COMP_HandleTypeDef *hcomp)
Comparator IRQ handler.
HAL_StatusTypeDef | HAL_COMP_Lock (COMP_HandleTypeDef *hcomp)
Lock the selected comparator configuration.
uint32_t | HAL_COMP_GetOutputLevel (COMP_HandleTypeDef *hcomp)
Return the output level (high or low) of the selected comparator.
__weak void | HAL_COMP_TriggerCallback (COMP_HandleTypeDef *hcomp)
Comparator trigger callback.
HAL_COMP_StateTypeDef | HAL_COMP_GetState (COMP_HandleTypeDef *hcomp)
Return the COMP handle state.
uint32_t | HAL_COMP_GetError (COMP_HandleTypeDef *hcomp)
Return the COMP error code.

Detailed Description

COMP HAL module driver. This file provides firmware functions to manage the following functionalities of the COMP peripheral: + Initialization and de-initialization functions + Start/Stop operation functions in polling mode + Start/Stop operation functions in interrupt mode (through EXTI interrupt) + Peripheral control functions + Peripheral state functions.

Author:
MCD Application Team
================================================================================
          ##### COMP Peripheral features #####
================================================================================

  [..]
      The STM32WBxx device family integrates two analog comparators instances:
      COMP1, COMP2.
      (#) Comparators input minus (inverting input) and input plus (non inverting input)
          can be set to internal references or to GPIO pins
          (refer to GPIO list in reference manual).

      (#) Comparators output level is available using HAL_COMP_GetOutputLevel()
          and can be redirected to other peripherals: GPIO pins (in mode
          alternate functions for comparator), timers.
          (refer to GPIO list in reference manual).

      (#) The comparators have interrupt capability through the EXTI controller
          with wake-up from sleep and stop modes.

      (#) Pairs of comparators instances can be combined in window mode
          (2 consecutive instances odd and even COMP<x> and COMP<x+1>).

          From the corresponding IRQ handler, the right interrupt source can be retrieved
          using macro __HAL_COMP_COMPx_EXTI_GET_FLAG().

            ##### How to use this driver #####
================================================================================
  [..]
      This driver provides functions to configure and program the comparator instances
      of STM32WBxx devices.

      To use the comparator, perform the following steps:

      (#)  Initialize the COMP low level resources by implementing the HAL_COMP_MspInit():
      (++) Configure the GPIO connected to comparator inputs plus and minus in analog mode
           using HAL_GPIO_Init().
      (++) If needed, configure the GPIO connected to comparator output in alternate function mode
           using HAL_GPIO_Init().
      (++) If required enable the COMP interrupt by configuring and enabling EXTI line in Interrupt mode and
           selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator
           interrupt vector using HAL_NVIC_EnableIRQ() function.

      (#) Configure the comparator using HAL_COMP_Init() function:
      (++) Select the input minus (inverting input)
      (++) Select the input plus (non-inverting input)
      (++) Select the hysteresis
      (++) Select the blanking source
      (++) Select the output polarity
      (++) Select the power mode
      (++) Select the window mode

      -@@- HAL_COMP_Init() calls internally __HAL_RCC_SYSCFG_CLK_ENABLE()
          to enable internal control clock of the comparators.
          However, this is a legacy strategy. In future STM32 families,
          COMP clock enable must be implemented by user in "HAL_COMP_MspInit()".
          Therefore, for compatibility anticipation, it is recommended to
          implement __HAL_RCC_SYSCFG_CLK_ENABLE() in "HAL_COMP_MspInit()".

      (#) Reconfiguration on-the-fly of comparator can be done by calling again
          function HAL_COMP_Init() with new input structure parameters values.

      (#) Enable the comparator using HAL_COMP_Start() function.

      (#) Use HAL_COMP_TriggerCallback() or HAL_COMP_GetOutputLevel() functions
          to manage comparator outputs (events and output level).

      (#) Disable the comparator using HAL_COMP_Stop() function.

      (#) De-initialize the comparator using HAL_COMP_DeInit() function.

      (#) For safety purpose, comparator configuration can be locked using HAL_COMP_Lock() function.
          The only way to unlock the comparator is a device hardware reset.

    *** Callback registration ***
    =============================================
    [..]

     The compilation flag USE_HAL_COMP_REGISTER_CALLBACKS, when set to 1,
     allows the user to configure dynamically the driver callbacks.
     Use Functions @ref HAL_COMP_RegisterCallback()
     to register an interrupt callback.
    [..]

     Function @ref HAL_COMP_RegisterCallback() allows to register following callbacks:
       (+) TriggerCallback       : callback for COMP trigger.
       (+) MspInitCallback       : callback for Msp Init.
       (+) MspDeInitCallback     : callback for Msp DeInit.
     This function takes as parameters the HAL peripheral handle, the Callback ID
     and a pointer to the user callback function.
    [..]

     Use function @ref HAL_COMP_UnRegisterCallback to reset a callback to the default
     weak function.
    [..]

     @ref HAL_COMP_UnRegisterCallback takes as parameters the HAL peripheral handle,
     and the Callback ID.
     This function allows to reset following callbacks:
       (+) TriggerCallback       : callback for COMP trigger.
       (+) MspInitCallback       : callback for Msp Init.
       (+) MspDeInitCallback     : callback for Msp DeInit.
     [..]

     By default, after the @ref HAL_COMP_Init() and when the state is @ref HAL_COMP_STATE_RESET
     all callbacks are set to the corresponding weak functions:
     example @ref HAL_COMP_TriggerCallback().
     Exception done for MspInit and MspDeInit functions that are
     reset to the legacy weak functions in the @ref HAL_COMP_Init()/ @ref HAL_COMP_DeInit() only when
     these callbacks are null (not registered beforehand).
    [..]

     If MspInit or MspDeInit are not null, the @ref HAL_COMP_Init()/ @ref HAL_COMP_DeInit()
     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
     [..]

     Callbacks can be registered/unregistered in @ref HAL_COMP_STATE_READY state only.
     Exception done MspInit/MspDeInit functions that can be registered/unregistered
     in @ref HAL_COMP_STATE_READY or @ref HAL_COMP_STATE_RESET state,
     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
    [..]

     Then, the user first registers the MspInit/MspDeInit user callbacks
     using @ref HAL_COMP_RegisterCallback() before calling @ref HAL_COMP_DeInit()
     or @ref HAL_COMP_Init() function.
     [..]

     When the compilation flag USE_HAL_COMP_REGISTER_CALLBACKS is set to 0 or
     not defined, the callback registration feature is not available and all callbacks
     are set to the corresponding weak functions.
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_comp.c.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_cortex.c File Reference

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Functions
stm32wbxx_hal_cortex.c File Reference

CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and Configuration functions + Peripheral Control functions. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Functions

void | HAL_NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
Set the priority grouping field (pre-emption priority and subpriority) using the required unlock sequence.
void | HAL_NVIC_SetPriority (IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
Set the priority of an interrupt.
void | HAL_NVIC_EnableIRQ (IRQn_Type IRQn)
Enable a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_DisableIRQ (IRQn_Type IRQn)
Disable a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_SystemReset (void)
Initiate a system reset request to reset the MCU.
uint32_t | HAL_SYSTICK_Config (uint32_t TicksNumb)
Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): Counter is in free running mode to generate periodic interrupts.
uint32_t | HAL_NVIC_GetPriorityGrouping (void)
Get the priority grouping field from the NVIC Interrupt Controller.
void | HAL_NVIC_GetPriority (IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
Get the priority of an interrupt.
void | HAL_NVIC_SetPendingIRQ (IRQn_Type IRQn)
Set Pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetPendingIRQ (IRQn_Type IRQn)
Get Pending Interrupt (read the pending register in the NVIC and return the pending bit for the specified interrupt).
void | HAL_NVIC_ClearPendingIRQ (IRQn_Type IRQn)
Clear the pending bit of an external interrupt.
void | HAL_SYSTICK_CLKSourceConfig (uint32_t CLKSource)
Configure the SysTick clock source.
void | HAL_SYSTICK_IRQHandler (void)
Handle SYSTICK interrupt request.
__weak void | HAL_SYSTICK_Callback (void)
SYSTICK callback.
void | HAL_MPU_Disable (void)
Disables the MPU.
void | HAL_MPU_Enable (uint32_t MPU_Control)
Enable the MPU.
void | HAL_MPU_ConfigRegion (MPU_Region_InitTypeDef *MPU_Init)
Initialize and configure the Region and the memory to be protected.

Detailed Description

CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and Configuration functions + Peripheral Control functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
    *** How to configure Interrupts using CORTEX HAL driver ***
    ===========================================================
    [..]
    This section provides functions allowing to configure the NVIC interrupts (IRQ).
    The Cortex M0+ exceptions are managed by CMSIS functions.
      (#) Enable and Configure the priority of the selected IRQ Channels.
             The priority can be 0..3.

        -@- Lower priority values gives higher priority.
        -@- Priority Order:
            (#@) Lowest priority.
            (#@) Lowest hardware priority (IRQn position).

      (#)  Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()

      (#)  Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()

      -@-  Negative value of IRQn_Type are not allowed.

    *** How to configure Systick using CORTEX HAL driver ***
    ========================================================
    [..]
    Setup SysTick Timer for time base.

   (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
       is a CMSIS function that:
        (++) Configures the SysTick Reload register with value passed as function parameter.
        (++) Configures the SysTick IRQ priority to the lowest value (0x03).
        (++) Resets the SysTick Counter register.
        (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
        (++) Enables the SysTick Interrupt.
        (++) Starts the SysTick Counter.

   (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
       __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
       HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
       inside the stm32wbxx_hal_cortex.h file.

   (+) You can change the SysTick IRQ priority by calling the
       HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
       call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.

   (+) To adjust the SysTick time base, use the following formula:

       Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
       (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
       (++) Reload Value should not exceed 0xFFFFFF
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_cortex.c.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_crc.c File Reference

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Functions
stm32wbxx_hal_crc.c File Reference

CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the Cyclic Redundancy Check (CRC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Functions

static uint32_t | CRC_Handle_8 (CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
Enter 8-bit input data to the CRC calculator.
static uint32_t | CRC_Handle_16 (CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
Enter 16-bit input data to the CRC calculator.
HAL_StatusTypeDef | HAL_CRC_Init (CRC_HandleTypeDef *hcrc)
Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC peripheral.
__weak void | HAL_CRC_MspInit (CRC_HandleTypeDef *hcrc)
Initializes the CRC MSP.
__weak void | HAL_CRC_MspDeInit (CRC_HandleTypeDef *hcrc)
DeInitialize the CRC MSP.
uint32_t | HAL_CRC_Accumulate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with the previously computed CRC as initialization value.
uint32_t | HAL_CRC_Calculate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer starting with hcrc->Instance->INIT as initialization value.
HAL_CRC_StateTypeDef | HAL_CRC_GetState (CRC_HandleTypeDef *hcrc)
Return the CRC handle state.

Detailed Description

CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the Cyclic Redundancy Check (CRC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
 ===============================================================================
                     ##### How to use this driver #####
 ===============================================================================
    [..]
         (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
         (+) Initialize CRC calculator
             (++) specify generating polynomial (peripheral default or non-default one)
             (++) specify initialization value (peripheral default or non-default one)
             (++) specify input data format
             (++) specify input or output data inversion mode if any
         (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
             input data buffer starting with the previously computed CRC as
             initialization value
         (+) Use HAL_CRC_Calculate() function to compute the CRC value of the
             input data buffer starting with the defined initialization value
             (default or non-default) to initiate CRC calculation
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_crc.c.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_crc_ex.c File Reference

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Functions
stm32wbxx_hal_crc_ex.c File Reference

Extended CRC HAL module driver. This file provides firmware functions to manage the extended functionalities of the CRC peripheral. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_CRCEx_Polynomial_Set (CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
Initialize the CRC polynomial if different from default one.
HAL_StatusTypeDef | HAL_CRCEx_Input_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
Set the Reverse Input data mode.
HAL_StatusTypeDef | HAL_CRCEx_Output_Data_Reverse (CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
Set the Reverse Output data mode.

Detailed Description

Extended CRC HAL module driver. This file provides firmware functions to manage the extended functionalities of the CRC peripheral.

Author:
MCD Application Team
================================================================================
            ##### How to use this driver #####
================================================================================
    [..]
         (+) Set user-defined generating polynomial thru HAL_CRCEx_Polynomial_Set()
         (+) Configure Input or Output data inversion
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_crc_ex.c.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_cryp.c File Reference

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Defines | Functions
stm32wbxx_hal_cryp.c File Reference

CRYP HAL module driver. This file provides firmware functions to manage the following functionalities of the Cryptography (CRYP) peripheral: + Initialization, de-initialization, set config and get config functions + DES/TDES, AES processing functions + DMA callback functions + CRYP IRQ handler management + Peripheral State functions. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Defines

#define | CRYP_TIMEOUT_KEYPREPARATION 82U /* The latency of key preparation operation is 82 clock cycles.*/
#define | CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/
#define | CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/
#define | CRYP_PHASE_READY 0x00000001U
#define | CRYP_PHASE_PROCESS 0x00000002U
#define | CRYP_OPERATINGMODE_ENCRYPT 0x00000000U
#define | CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0
#define | CRYP_OPERATINGMODE_DECRYPT AES_CR_MODE_1
#define | CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT AES_CR_MODE
#define | CRYP_PHASE_INIT 0x00000000U
#define | CRYP_PHASE_HEADER AES_CR_GCMPH_0
#define | CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1
#define | CRYP_PHASE_FINAL AES_CR_GCMPH
#define | CRYP_CCM_CTR1_0 0x07FFFFFFU
#define | CRYP_CCM_CTR1_1 0xFFFFFF00U
#define | CRYP_CCM_CTR1_2 0x00000001U
#define | CRYP_SET_PHASE(__HANDLE__, __PHASE__)

Functions

static void | CRYP_SetDMAConfig (CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
Set the DMA configuration and start the DMA transfer.
static void | CRYP_DMAInCplt (DMA_HandleTypeDef *hdma)
DMA CRYP input data process complete callback.
static void | CRYP_DMAOutCplt (DMA_HandleTypeDef *hdma)
DMA CRYP output data process complete callback.
static void | CRYP_DMAError (DMA_HandleTypeDef *hdma)
DMA CRYP communication error callback.
static void | CRYP_SetKey (CRYP_HandleTypeDef *hcryp, uint32_t KeySize)
Writes Key in Key registers.
static void | CRYP_AES_IT (CRYP_HandleTypeDef *hcryp)
Handle CRYP block input/output data handling under interruption.
static HAL_StatusTypeDef | CRYP_GCMCCM_SetHeaderPhase (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Sets the header phase in polling mode.
static void | CRYP_GCMCCM_SetPayloadPhase_IT (CRYP_HandleTypeDef *hcryp)
Sets the payload phase in interrupt mode.
static void | CRYP_GCMCCM_SetHeaderPhase_IT (CRYP_HandleTypeDef *hcryp)
Sets the header phase in interrupt mode.
static HAL_StatusTypeDef | CRYP_GCMCCM_SetHeaderPhase_DMA (CRYP_HandleTypeDef *hcryp)
Sets the header phase when using DMA in process.
static HAL_StatusTypeDef | CRYP_AESGCM_Process_DMA (CRYP_HandleTypeDef *hcryp)
Encryption/Decryption process in AES GCM mode and prepare the authentication TAG using DMA.
static HAL_StatusTypeDef | CRYP_AESGCM_Process_IT (CRYP_HandleTypeDef *hcryp)
Encryption/Decryption process in AES GCM mode and prepare the authentication TAG in interrupt mode.
static HAL_StatusTypeDef | CRYP_AESGCM_Process (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Encryption/Decryption process in AES GCM mode and prepare the authentication TAG.
static HAL_StatusTypeDef | CRYP_AESCCM_Process (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
AES CCM encryption/decryption processing in polling mode for TinyAES peripheral, no encrypt/decrypt performed, only authentication preparation.
static HAL_StatusTypeDef | CRYP_AESCCM_Process_IT (CRYP_HandleTypeDef *hcryp)
AES CCM encryption/decryption process in interrupt mode for TinyAES peripheral, no encrypt/decrypt performed, only authentication preparation.
static HAL_StatusTypeDef | CRYP_AESCCM_Process_DMA (CRYP_HandleTypeDef *hcryp)
AES CCM encryption/decryption process in DMA mode for TinyAES peripheral, no encrypt/decrypt performed, only authentication preparation.
static void | CRYP_AES_ProcessData (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Process Data: Write Input data in polling mode and used in AES functions.
static HAL_StatusTypeDef | CRYP_AES_Encrypt (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Encryption in ECB/CBC & CTR Algorithm with AES Standard.
static HAL_StatusTypeDef | CRYP_AES_Decrypt (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Decryption in ECB/CBC & CTR mode with AES Standard.
static HAL_StatusTypeDef | CRYP_AES_Decrypt_IT (CRYP_HandleTypeDef *hcryp)
Decryption in ECB/CBC & CTR mode with AES Standard using interrupt mode.
static HAL_StatusTypeDef | CRYP_AES_Encrypt_IT (CRYP_HandleTypeDef *hcryp)
Encryption in ECB/CBC & CTR mode with AES Standard using interrupt mode.
static HAL_StatusTypeDef | CRYP_AES_Decrypt_DMA (CRYP_HandleTypeDef *hcryp)
Decryption in ECB/CBC & CTR mode with AES Standard using DMA mode.
static HAL_StatusTypeDef | CRYP_WaitOnCCFlag (CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Handle CRYP hardware block Timeout when waiting for CCF flag to be raised.
HAL_StatusTypeDef | HAL_CRYP_Init (CRYP_HandleTypeDef *hcryp)
Initializes the CRYP according to the specified parameters in the CRYP_ConfigTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_CRYP_DeInit (CRYP_HandleTypeDef *hcryp)
De-Initializes the CRYP peripheral.
HAL_StatusTypeDef | HAL_CRYP_SetConfig (CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
Configure the CRYP according to the specified parameters in the CRYP_ConfigTypeDef.
HAL_StatusTypeDef | HAL_CRYP_GetConfig (CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
Get CRYP Configuration parameters in associated handle.
__weak void | HAL_CRYP_MspInit (CRYP_HandleTypeDef *hcryp)
Initializes the CRYP MSP.
__weak void | HAL_CRYP_MspDeInit (CRYP_HandleTypeDef *hcryp)
DeInitializes CRYP MSP.
HAL_StatusTypeDef | HAL_CRYP_RegisterCallback (CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback)
Register a User CRYP Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_CRYP_UnRegisterCallback (CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID)
Unregister an CRYP Callback CRYP callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_CRYP_Encrypt (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
Encryption mode.
HAL_StatusTypeDef | HAL_CRYP_Decrypt (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
Decryption mode.
HAL_StatusTypeDef | HAL_CRYP_Encrypt_IT (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Encryption in interrupt mode.
HAL_StatusTypeDef | HAL_CRYP_Decrypt_IT (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Decryption in interrupt mode.
HAL_StatusTypeDef | HAL_CRYP_Encrypt_DMA (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Encryption in DMA mode.
HAL_StatusTypeDef | HAL_CRYP_Decrypt_DMA (CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Decryption in DMA mode.
void | HAL_CRYP_IRQHandler (CRYP_HandleTypeDef *hcryp)
This function handles cryptographic interrupt request.
uint32_t | HAL_CRYP_GetError (CRYP_HandleTypeDef *hcryp)
Return the CRYP error code.
HAL_CRYP_STATETypeDef | HAL_CRYP_GetState (CRYP_HandleTypeDef *hcryp)
Returns the CRYP state.
__weak void | HAL_CRYP_InCpltCallback (CRYP_HandleTypeDef *hcryp)
Input FIFO transfer completed callback.
__weak void | HAL_CRYP_OutCpltCallback (CRYP_HandleTypeDef *hcryp)
Output FIFO transfer completed callback.
__weak void | HAL_CRYP_ErrorCallback (CRYP_HandleTypeDef *hcryp)
CRYP error callback.

Detailed Description

CRYP HAL module driver. This file provides firmware functions to manage the following functionalities of the Cryptography (CRYP) peripheral: + Initialization, de-initialization, set config and get config functions + DES/TDES, AES processing functions + DMA callback functions + CRYP IRQ handler management + Peripheral State functions.

Author:
MCD Application Team
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
      The CRYP HAL driver can be used in CRYP or TinyAES peripheral as follows:

      (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
         (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()or __HAL_RCC_AES_CLK_ENABLE for TinyAES peripheral
         (##) In case of using interrupts (e.g. HAL_CRYP_Encrypt_IT())
             (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
             (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
             (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
         (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_Encrypt_DMA())
             (+++) Enable the DMAx interface clock using __RCC_DMAx_CLK_ENABLE()
             (+++) Configure and enable two DMA streams one for managing data transfer from
                 memory to peripheral (input stream) and another stream for managing data
                 transfer from peripheral to memory (output stream)
             (+++) Associate the initialized DMA handle to the CRYP DMA handle
                 using  __HAL_LINKDMA()
             (+++) Configure the priority and enable the NVIC for the transfer complete
                 interrupt on the two DMA Streams. The output stream should have higher
                 priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()

      (#)Initialize the CRYP according to the specified parameters :
         (##) The data type: 1-bit, 8-bit, 16-bit or 32-bit.
         (##) The key size: 128, 192 or 256.
         (##) The AlgoMode DES/ TDES Algorithm ECB/CBC or AES Algorithm ECB/CBC/CTR/GCM or CCM.
         (##) The initialization vector (counter). It is not used in ECB mode.
         (##) The key buffer used for encryption/decryption.
             (+++) In some specific configurations, the key is written by the application
                   code out of the HAL scope. In that case, user can still resort to the
                   HAL APIs as usual but must make sure that pKey pointer is set to NULL.
         (##) The Header used only in AES GCM and CCM Algorithm for authentication.
         (##) The HeaderSize The size of header buffer in word.
         (##) The B0 block is the first authentication block used only  in AES CCM mode.

      (#)Three processing (encryption/decryption) functions are available:
         (##) Polling mode: encryption and decryption APIs are blocking functions
              i.e. they process the data and wait till the processing is finished,
              e.g. HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
         (##) Interrupt mode: encryption and decryption APIs are not blocking functions
              i.e. they process the data under interrupt,
              e.g. HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
         (##) DMA mode: encryption and decryption APIs are not blocking functions
              i.e. the data transfer is ensured by DMA,
              e.g. HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA

      (#)When the processing function is called at first time after HAL_CRYP_Init()
         the CRYP peripheral is configured and processes the buffer in input.
         At second call, no need to Initialize the CRYP, user have to get current configuration via
         HAL_CRYP_GetConfig() API, then only  HAL_CRYP_SetConfig() is requested to set
         new parametres, finally user can  start encryption/decryption.

       (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.

       (#)To process a single message with consecutive calls to HAL_CRYP_Encrypt() or HAL_CRYP_Decrypt()
          without having to configure again the Key or the Initialization Vector between each API call,
          the field KeyIVConfigSkip of the initialization structure must be set to CRYP_KEYIVCONFIG_ONCE.
          Same is true for consecutive calls of HAL_CRYP_Encrypt_IT(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt_DMA()
          or HAL_CRYP_Decrypt_DMA().

    [..]
      The cryptographic processor supports following standards:
      (#) The data encryption standard (DES) and Triple-DES (TDES) supported only by CRYP1 peripheral:
         (##)64-bit data block processing
         (##) chaining modes supported :
             (+++)  Electronic Code Book(ECB)
             (+++)  Cipher Block Chaining (CBC)
         (##) keys length supported :64-bit, 128-bit and 192-bit.
      (#) The advanced encryption standard (AES) supported  by CRYP1 & TinyAES peripheral:
         (##)128-bit data block processing
         (##) chaining modes supported :
             (+++)  Electronic Code Book(ECB)
             (+++)  Cipher Block Chaining (CBC)
             (+++)  Counter mode (CTR)
             (+++)  Galois/counter mode (GCM/GMAC)
             (+++)  Counter with Cipher Block Chaining-Message(CCM)
         (##) keys length Supported :
             (+++) for CRYP1 peripheral: 128-bit, 192-bit and 256-bit.
             (+++) for TinyAES peripheral:  128-bit and 256-bit

    [..]
    (@) Specific care must be taken to format the key and the Initialization Vector IV!

    [..] If the key is defined as a 128-bit long array key[127..0] = {b127 ... b0} where
         b127 is the MSB and b0 the LSB, the key must be stored in MCU memory
         (+) as a sequence of words where the MSB word comes first (occupies the
           lowest memory address)
          (++)   address n+0 : 0b b127 .. b120 b119 .. b112 b111 .. b104 b103 .. b96
          (++)   address n+4 : 0b b95 .. b88 b87 .. b80 b79 .. b72 b71 .. b64
          (++)   address n+8 : 0b b63 .. b56 b55 .. b48 b47 .. b40 b39 .. b32
          (++)   address n+C : 0b b31 .. b24 b23 .. b16 b15 .. b8 b7 .. b0
     [..] Hereafter, another illustration when considering a 128-bit long key made of 16 bytes {B15..B0}.
         The 4 32-bit words that make the key must be stored as follows in MCU memory:
          (+)    address n+0 : 0x B15 B14 B13 B12
          (+)    address n+4 : 0x B11 B10 B9 B8
          (+)    address n+8 : 0x B7 B6 B5 B4
          (+)    address n+C : 0x B3 B2 B1 B0
     [..]  which leads to the expected setting
       (+)       AES_KEYR3 = 0x B15 B14 B13 B12
       (+)       AES_KEYR2 = 0x B11 B10 B9 B8
       (+)       AES_KEYR1 = 0x B7 B6 B5 B4
       (+)       AES_KEYR0 = 0x B3 B2 B1 B0

    [..]  Same format must be applied for a 256-bit long key made of 32 bytes {B31..B0}.
          The 8 32-bit words that make the key must be stored as follows in MCU memory:
          (+)    address n+00 : 0x B31 B30 B29 B28
          (+)    address n+04 : 0x B27 B26 B25 B24
          (+)    address n+08 : 0x B23 B22 B21 B20
          (+)    address n+0C : 0x B19 B18 B17 B16
          (+)    address n+10 : 0x B15 B14 B13 B12
          (+)    address n+14 : 0x B11 B10 B9 B8
          (+)    address n+18 : 0x B7 B6 B5 B4
          (+)    address n+1C : 0x B3 B2 B1 B0
     [..]  which leads to the expected setting
       (+)       AES_KEYR7 = 0x B31 B30 B29 B28
       (+)       AES_KEYR6 = 0x B27 B26 B25 B24
       (+)       AES_KEYR5 = 0x B23 B22 B21 B20
       (+)       AES_KEYR4 = 0x B19 B18 B17 B16
       (+)       AES_KEYR3 = 0x B15 B14 B13 B12
       (+)       AES_KEYR2 = 0x B11 B10 B9 B8
       (+)       AES_KEYR1 = 0x B7 B6 B5 B4
       (+)       AES_KEYR0 = 0x B3 B2 B1 B0

    [..] Initialization Vector IV (4 32-bit words) format must follow the same as
         that of a 128-bit long key.

    [..] Note that key and IV registers are not sensitive to swap mode selection.

    [..]  This section describes the AES Galois/counter mode (GCM) supported by both CRYP1 and TinyAES peripherals:
      (#)  Algorithm supported :
         (##) Galois/counter mode (GCM)
         (##) Galois message authentication code (GMAC) :is exactly the same as
              GCM algorithm composed only by an header.
      (#)  Four phases are performed in GCM :
         (##) Init phase: peripheral prepares the GCM hash subkey (H) and do the IV processing
         (##) Header phase: peripheral processes the Additional Authenticated Data (AAD), with hash
          computation only.
         (##) Payload phase: peripheral processes the plaintext (P) with hash computation + keystream
          encryption + data XORing. It works in a similar way for ciphertext (C).
         (##) Final phase: peripheral generates the authenticated tag (T) using the last block of data.
      (#)  structure of message construction in GCM is defined as below  :
         (##) 16 bytes Initial Counter Block (ICB)composed of IV and counter
         (##) The authenticated header A (also knows as Additional Authentication Data AAD)
          this part of the message is only authenticated, not encrypted.
         (##) The plaintext message P is both authenticated and encrypted as ciphertext.
          GCM standard specifies that ciphertext has same bit length as the plaintext.
         (##) The last block is composed of the length of A (on 64 bits) and the length of ciphertext
          (on 64 bits)

    [..]  A more detailed description of the GCM message structure is available below.

    [..]  This section describe The AES Counter with Cipher Block Chaining-Message
          Authentication Code (CCM) supported by both CRYP1 and TinyAES peripheral:
      (#)  Specific parameters for CCM  :

         (##) B0 block  : follows NIST Special Publication 800-38C,
         (##) B1 block (header)
         (##) CTRx block  : control blocks

    [..]  A detailed description of the CCM message structure is available below.

      (#)  Four phases are performed in CCM for CRYP1 peripheral:
         (##) Init phase: peripheral prepares the GCM hash subkey (H) and do the IV processing
         (##) Header phase: peripheral processes the Additional Authenticated Data (AAD), with hash
          computation only.
         (##) Payload phase: peripheral processes the plaintext (P) with hash computation + keystream
          encryption + data XORing. It works in a similar way for ciphertext (C).
         (##) Final phase: peripheral generates the authenticated tag (T) using the last block of data.
      (#)    CCM in TinyAES peripheral:
         (##) To perform message payload encryption or decryption AES is configured in CTR mode.
         (##) For authentication two phases are performed :
          - Header phase: peripheral processes the Additional Authenticated Data (AAD) first, then the cleartext message
          only cleartext payload (not the ciphertext payload) is used and no outpout.
         (##) Final phase: peripheral generates the authenticated tag (T) using the last block of data.

  *** Callback registration ***
  =============================

  [..]
  The compilation define  USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1
  allows the user to configure dynamically the driver callbacks.
  Use Functions @ref HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback()
  to register an interrupt callback.

  [..]
  Function @ref HAL_CRYP_RegisterCallback() allows to register following callbacks:
    (+) InCpltCallback     :  Input FIFO transfer completed callback.
    (+) OutCpltCallback    : Output FIFO transfer completed callback.
    (+) ErrorCallback      : callback for error detection.
    (+) MspInitCallback    : CRYP MspInit.
    (+) MspDeInitCallback  : CRYP MspDeInit.
  This function takes as parameters the HAL peripheral handle, the Callback ID
  and a pointer to the user callback function.

  [..]
  Use function @ref HAL_CRYP_UnRegisterCallback() to reset a callback to the default
  weak function.
  @ref HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle,
  and the Callback ID.
  This function allows to reset following callbacks:
    (+) InCpltCallback     :  Input FIFO transfer completed callback.
    (+) OutCpltCallback    : Output FIFO transfer completed callback.
    (+) ErrorCallback      : callback for error detection.
    (+) MspInitCallback    : CRYP MspInit.
    (+) MspDeInitCallback  : CRYP MspDeInit.

  [..]
  By default, after the @ref HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET
  all callbacks are set to the corresponding weak functions :
  examples @ref HAL_CRYP_InCpltCallback() , @ref HAL_CRYP_OutCpltCallback().
  Exception done for MspInit and MspDeInit functions that are
  reset to the legacy weak function in the @ref HAL_CRYP_Init()/ @ref HAL_CRYP_DeInit() only when
  these callbacks are null (not registered beforehand).
  if not, MspInit or MspDeInit are not null, the @ref HAL_CRYP_Init() / @ref HAL_CRYP_DeInit()
  keep and use the user MspInit/MspDeInit functions (registered beforehand)

  [..]
  Callbacks can be registered/unregistered in HAL_CRYP_STATE_READY state only.
  Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
  in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state,
  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
  In that case first register the MspInit/MspDeInit user callbacks
  using @ref HAL_CRYP_RegisterCallback() before calling @ref HAL_CRYP_DeInit()
  or @ref HAL_CRYP_Init() function.

  [..]
  When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or
  not defined, the callback registration feature is not available and all callbacks
  are set to the corresponding weak functions.

  *** Suspend/Resume feature ***
  ==============================

  [..]
  The compilation define USE_HAL_CRYP_SUSPEND_RESUME when set to 1
  allows the user to resort to the suspend/resume feature.
  A low priority block processing can be suspended to process a high priority block
  instead. When the high priority block processing is over, the low priority block
  processing can be resumed, restarting from the point where it was suspended. This
  feature is applicable only in non-blocking interrupt mode.

  [..] User must resort to HAL_CRYP_Suspend() to suspend the low priority block
  processing. This API manages the hardware block processing suspension and saves all the
  internal data that will be needed to restart later on. Upon HAL_CRYP_Suspend() completion,
  the user can launch the processing of any other block (high priority block processing).

  [..] When the high priority block processing is over, user must invoke HAL_CRYP_Resume()
  to resume the low priority block processing. Ciphering (or deciphering) restarts from
  the suspension point and ends as usual.

  [..] HAL_CRYP_Suspend() reports an error when the suspension request is sent too late
  (i.e when the low priority block processing is about to end). There is no use to
  suspend the tag generation processing for authentication algorithms.

    [..]
    (@) If the key is written out of HAL scope (case pKey pointer set to NULL by the user),
        the block processing suspension/resumption mechanism is NOT applicable.

    [..]
    (@) If the Key and Initialization Vector are configured only once and configuration is
        skipped for consecutive processings (case KeyIVConfigSkip set to CRYP_KEYIVCONFIG_ONCE),
        the block processing suspension/resumption mechanism is NOT applicable.
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_cryp.c.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_cryp_ex.c File Reference

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Defines | Functions
stm32wbxx_hal_cryp_ex.c File Reference

CRYPEx HAL module driver. This file provides firmware functions to manage the extended functionalities of the Cryptography (CRYP) peripheral. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Defines

#define | CRYP_PHASE_INIT 0x00000000U
#define | CRYP_PHASE_HEADER AES_CR_GCMPH_0
#define | CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1
#define | CRYP_PHASE_FINAL AES_CR_GCMPH
#define | CRYP_OPERATINGMODE_ENCRYPT 0x00000000U
#define | CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0
#define | CRYP_OPERATINGMODE_DECRYPT AES_CR_MODE_1
#define | CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT AES_CR_MODE
#define | CRYPEx_PHASE_PROCESS 0x02U
#define | CRYPEx_PHASE_FINAL 0x03U
#define | CRYP_CCM_CTR0_0 0x07FFFFFFU
#define | CRYP_CCM_CTR0_3 0xFFFFFF00U

Functions

HAL_StatusTypeDef | HAL_CRYPEx_AESGCM_GenerateAuthTAG (CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
generate the GCM authentication TAG.
HAL_StatusTypeDef | HAL_CRYPEx_AESCCM_GenerateAuthTAG (CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
AES CCM Authentication TAG generation.
void | HAL_CRYPEx_EnableAutoKeyDerivation (CRYP_HandleTypeDef *hcryp)
AES enable key derivation functions.
void | HAL_CRYPEx_DisableAutoKeyDerivation (CRYP_HandleTypeDef *hcryp)
AES disable key derivation functions.

Detailed Description

CRYPEx HAL module driver. This file provides firmware functions to manage the extended functionalities of the Cryptography (CRYP) peripheral.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_cryp_ex.c.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_dma.c File Reference

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Functions
stm32wbxx_hal_dma.c File Reference

DMA HAL module driver. This file provides firmware functions to manage the following functionalities of the Direct Memory Access (DMA) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and errors functions. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Functions

static void | DMA_SetConfig (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Sets the DMA Transfer parameter.
static void | DMA_CalcDMAMUXChannelBaseAndMask (DMA_HandleTypeDef *hdma)
Updates the DMA handle with the DMAMUX channel and status mask depending on channel number.
static void | DMA_CalcDMAMUXRequestGenBaseAndMask (DMA_HandleTypeDef *hdma)
Updates the DMA handle with the DMAMUX request generator params.
HAL_StatusTypeDef | HAL_DMA_Init (DMA_HandleTypeDef *hdma)
Initialize the DMA according to the specified parameters in the DMA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_DMA_DeInit (DMA_HandleTypeDef *hdma)
DeInitialize the DMA peripheral.
HAL_StatusTypeDef | HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Start_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA_Abort (DMA_HandleTypeDef *hdma)
Abort the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Abort_IT (DMA_HandleTypeDef *hdma)
Aborts the DMA Transfer in Interrupt mode.
HAL_StatusTypeDef | HAL_DMA_PollForTransfer (DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
Polling for transfer complete.
void | HAL_DMA_IRQHandler (DMA_HandleTypeDef *hdma)
Handle DMA interrupt request.
HAL_StatusTypeDef | HAL_DMA_RegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void(*pCallback)(DMA_HandleTypeDef *_hdma))
Register callbacks.
HAL_StatusTypeDef | HAL_DMA_UnRegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
UnRegister callbacks.
HAL_DMA_StateTypeDef | HAL_DMA_GetState (DMA_HandleTypeDef *hdma)
Return the DMA handle state.
uint32_t | HAL_DMA_GetError (DMA_HandleTypeDef *hdma)
Return the DMA error code.

Detailed Description

DMA HAL module driver. This file provides firmware functions to manage the following functionalities of the Direct Memory Access (DMA) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and errors functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
   (#) Enable and configure the peripheral to be connected to the DMA Channel
       (except for internal SRAM / FLASH memories: no initialization is
       necessary). Please refer to the Reference manual for connection between peripherals
       and DMA requests.

   (#) For a given Channel, program the required configuration through the following parameters:
       Channel request, Transfer Direction, Source and Destination data formats,
       Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
       using HAL_DMA_Init() function.

       Prior to HAL_DMA_Init the peripheral clock shall be enabled for both DMA & DMAMUX
       thanks to:
      (##) DMA1 or DMA2: __HAL_RCC_DMA1_CLK_ENABLE() or  __HAL_RCC_DMA2_CLK_ENABLE() ;
      (##) DMAMUX1:      __HAL_RCC_DMAMUX1_CLK_ENABLE();

   (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
       detection.

   (#) Use HAL_DMA_Abort() function to abort the current transfer

     -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.

     *** Polling mode IO operation ***
     =================================
    [..]
          (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
              address and destination address and the Length of data to be transferred
          (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
              case a fixed Timeout can be configured by User depending from his application.

     *** Interrupt mode IO operation ***
     ===================================
    [..]
          (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
          (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
          (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
              Source address and destination address and the Length of data to be transferred.
              In this case the DMA interrupt is configured
          (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
          (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
              add his own function to register callbacks with HAL_DMA_RegisterCallback().

     *** DMA HAL driver macros list ***
     =============================================
      [..]
       Below the list of macros in DMA HAL driver.

       (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
       (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
       (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
       (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
       (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
       (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
       (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt is enabled or not.

     [..]
      (@) You can refer to the DMA HAL driver header file for more useful macros
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_dma.c.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_dma_ex.c File Reference

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Functions
stm32wbxx_hal_dma_ex.c File Reference

DMA Extension HAL module driver This file provides firmware functions to manage the following functionalities of the DMA Extension peripheral: + Extended features functions. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_DMAEx_ConfigMuxSync (DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
Configure the DMAMUX synchronization parameters for a given DMA channel (instance).
HAL_StatusTypeDef | HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
Configure the DMAMUX request generator block used by the given DMA channel (instance).
HAL_StatusTypeDef | HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
Enable the DMAMUX request generator block used by the given DMA channel (instance).
HAL_StatusTypeDef | HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
Disable the DMAMUX request generator block used by the given DMA channel (instance).
void | HAL_DMAEx_MUX_IRQHandler (DMA_HandleTypeDef *hdma)
Handles DMAMUX interrupt request.

Detailed Description

DMA Extension HAL module driver This file provides firmware functions to manage the following functionalities of the DMA Extension peripheral: + Extended features functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
  The DMA Extension HAL driver can be used as follows:

   (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
   (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
       Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
       to respectively enable/disable the request generator.

   (+) To handle the DMAMUX Interrupts, the function  HAL_DMAEx_MUX_IRQHandler should be called from
       the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler.
       As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMAEx_MUX_IRQHandler should be
       called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project
      (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator)
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_dma_ex.c.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_exti.c File Reference

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Defines | Functions
stm32wbxx_hal_exti.c File Reference

EXTI HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (EXTI) peripheral: + Initialization and de-initialization functions + IO operation functions. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Defines

#define | EXTI_MODE_OFFSET 0x04u /* 0x10: offset between CPU IMR/EMR registers */
#define | EXTI_CONFIG_OFFSET 0x08u /* 0x20: offset between CPU Rising/Falling configuration registers */

Functions

HAL_StatusTypeDef | HAL_EXTI_SetConfigLine (EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
Set configuration of a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_GetConfigLine (EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
Get configuration of a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_ClearConfigLine (EXTI_HandleTypeDef *hexti)
Clear whole configuration of a dedicated Exti line.
HAL_StatusTypeDef | HAL_EXTI_RegisterCallback (EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void(*pPendingCbfn)(void))
Register callback for a dedicaated Exti line.
HAL_StatusTypeDef | HAL_EXTI_GetHandle (EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
Store line number as handle private field.
void | HAL_EXTI_IRQHandler (EXTI_HandleTypeDef *hexti)
Handle EXTI interrupt request.
uint32_t | HAL_EXTI_GetPending (EXTI_HandleTypeDef *hexti, uint32_t Edge)
Get interrupt pending bit of a dedicated line.
void | HAL_EXTI_ClearPending (EXTI_HandleTypeDef *hexti, uint32_t Edge)
Clear interrupt pending bit of a dedicated line.
void | HAL_EXTI_GenerateSWI (EXTI_HandleTypeDef *hexti)
Generate a software interrupt for a dedicated line.

Detailed Description

EXTI HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (EXTI) peripheral: + Initialization and de-initialization functions + IO operation functions.

Author:
MCD Application Team
  ==============================================================================
                    ##### EXTI Peripheral features #####
  ==============================================================================
  [..]
    (+) Each Exti line can be configured within this driver.

    (+) Exti line can be configured in 3 different modes
        (++) Interrupt
        (++) Event
        (++) Both of them

    (+) Configurable Exti lines can be configured with 3 different triggers
        (++) Rising
        (++) Falling
        (++) Both of them

    (+) When set in interrupt mode, configurable Exti lines have one
        interrupt pending register:
        (++) Trigger request occurred

    (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
        be selected throught multiplexer.

                     ##### How to use this driver #####
  ==============================================================================
  [..]

    (#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
        (++) Choose the interrupt line number by setting "Line" member from
             EXTI_ConfigTypeDef structure.
        (++) Configure the interrupt and/or event mode using "Mode" member from
             EXTI_ConfigTypeDef structure.
        (++) For configurable lines, configure rising and/or falling trigger
             "Trigger" member from EXTI_ConfigTypeDef structure.
        (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
             member from GPIO_InitTypeDef structure.

    (#) Get current Exti configuration of a dedicated line using
        HAL_EXTI_GetConfigLine().
        (++) Provide exiting handle as parameter.
        (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.

    (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
        (++) Provide exiting handle as parameter.

    (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
        (++) Provide exiting handle as first parameter.
        (++) Provide which callback will be registered using one value from
             EXTI_CallbackIDTypeDef.
        (++) Provide callback function pointer.

    (#) Get interrupt pending bit using HAL_EXTI_GetPending().

    (#) Clear interrupt pending bit using HAL_EXTI_GetPending().

    (#) Generate software interrupt using HAL_EXTI_GenerateSWI().
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_exti.c.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_flash.c File Reference

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Defines | Functions | Variables
stm32wbxx_hal_flash.c File Reference

FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral Errors functions. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Defines

#define | FLASH_NB_DOUBLE_WORDS_IN_ROW 64

Functions

static void | FLASH_Program_DoubleWord (uint32_t Address, uint64_t Data)
Program double-word (64-bit) at a specified address.
static void | FLASH_Program_Fast (uint32_t Address, uint32_t DataAddress)
Fast program a 32 row double-word (64-bit) at a specified address.
HAL_StatusTypeDef | HAL_FLASH_Program (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program double word or fast program of a row at a specified address.
HAL_StatusTypeDef | HAL_FLASH_Program_IT (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program double word or fast program of a row at a specified address with interrupt enabled.
void | HAL_FLASH_IRQHandler (void)
Handle FLASH interrupt request.
__weak void | HAL_FLASH_EndOfOperationCallback (uint32_t ReturnValue)
FLASH end of operation interrupt callback.
__weak void | HAL_FLASH_OperationErrorCallback (uint32_t ReturnValue)
FLASH operation error interrupt callback.
HAL_StatusTypeDef | HAL_FLASH_Unlock (void)
Unlock the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_Lock (void)
Lock the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_OB_Unlock (void)
Unlock the FLASH Option Bytes Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Lock (void)
Lock the FLASH Option Bytes Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Launch (void)
Launch the option byte loading.
uint32_t | HAL_FLASH_GetError (void)
Get the specific FLASH error flag.
HAL_StatusTypeDef | FLASH_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH operation to complete.

Variables

FLASH_ProcessTypeDef pFlash
Variable used for Program/Erase sectors under interruption.

Detailed Description

FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral Errors functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### FLASH peripheral features #####
  ==============================================================================

  [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
       to the Flash memory. It implements the erase and program Flash memory operations
       and the read and write protection mechanisms.

  [..] The Flash memory interface accelerates code execution with a system of instruction
       prefetch and cache lines.

  [..] The FLASH main features are:
      (+) Flash memory read operations
      (+) Flash memory program/erase operations
      (+) Program and Erase suspension
      (+) Read / write protections (2 areas per features)
      (+) CPU2 Security area
      (+) Option bytes programming
      (+) Prefetch on CPU1 I-Code and CPU2 S-bus
      (+) 32 instruction cache lines of 4*64 bits on I-Code for CPU1
      (+) 8 data cache lines of 4*64 bits on D-Code for CPU1
      (+) 4 instruction cache lines of 1*64 bits on S-bus for CPU2
      (+) 4 data cache lines of 1*64 bits on S-Bus for CPU2
      (+) Error code correction (ECC) : Data in flash are 72-bits word
          (8 bits added per double word)

                        ##### How to use this driver #####
 ==============================================================================
    [..]
      This driver provides functions and macros to configure and program the FLASH
      memory of all STM32WBxx devices.

      (#) Flash Memory IO Programming functions:
           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
                HAL_FLASH_Lock() functions
           (++) Program functions: double word and fast program (full row programming)
           (++) There are two modes of programming:
            (+++) Polling mode using HAL_FLASH_Program() function
            (+++) Interrupt mode using HAL_FLASH_Program_IT() function

      (#) Interrupts and flags management functions:
           (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
           (++) Callback functions are called when the flash operations are finished :
                HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise
                HAL_FLASH_OperationErrorCallback()
           (++) Get error flag status by calling HAL_GetError()

      (#) Option bytes management functions :
           (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and
                HAL_FLASH_OB_Lock() functions
           (++) Launch the reload of the option bytes using HAL_FLASH_OB_Launch() function.
                In this case, a reset is generated

    [..]
      In addition to these functions, this driver includes a set of macros allowing
      to handle the following operations:
       (+) Set the latency
       (+) Enable/Disable the prefetch buffer
       (+) Enable/Disable the suspend program or erase request
       (+) Enable/Disable the Instruction cache and the Data cache
       (+) Reset the Instruction cache and the Data cache
       (+) Enable/Disable the Flash interrupts
       (+) Monitor the Flash flags status
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_flash.c.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_flash_ex.c File Reference

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Functions
stm32wbxx_hal_flash_ex.c File Reference

Extended FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the FLASH extended peripheral: + Extended programming operations functions. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Functions

static void | FLASH_MassErase (void)
Mass erase of FLASH memory.
static void | FLASH_AcknowledgePageErase (void)
Acknlowldge the page erase operation.
static void | FLASH_FlushCaches (void)
Flush the instruction and data caches.
static void | FLASH_OB_WRPConfig (uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset)
Configure the write protection of the desired pages.
static void | FLASH_OB_OptrConfig (uint32_t UserType, uint32_t UserConfig, uint32_t RDPLevel)
Set user & RDP configuration.
static void | FLASH_OB_PCROP1AConfig (uint32_t PCROPConfig, uint32_t PCROP1AStartAddr, uint32_t PCROP1AEndAddr)
Configure the Zone 1A Proprietary code readout protection of the desired addresses, and erase configuration on RDP regression.
static void | FLASH_OB_PCROP1BConfig (uint32_t PCROP1BStartAddr, uint32_t PCROP1BEndAddr)
Configure the Zone 1B Proprietary code readout protection of the desired addresses.
static void | FLASH_OB_IPCCBufferAddrConfig (uint32_t IPCCDataBufAddr)
Program the FLASH IPCC data buffer address.
static void | FLASH_OB_SecureConfig (FLASH_OBProgramInitTypeDef *pOBParam)
Configure the secure start address of the different memories (FLASH and SRAM2), the secure mode and the CPU2 Secure Boot reset vector.
static void | FLASH_OB_GetWRP (uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRDPEndOffset)
Return the FLASH Write Protection Option Bytes value.
static uint32_t | FLASH_OB_GetRDP (void)
Return the FLASH Read Protection level.
static uint32_t | FLASH_OB_GetUser (void)
Return the FLASH User Option Byte value.
static void | FLASH_OB_GetPCROP (uint32_t *PCROPConfig, uint32_t *PCROP1AStartAddr, uint32_t *PCROP1AEndAddr, uint32_t *PCROP1BStartAddr, uint32_t *PCROP1BEndAddr)
Return the FLASH Write Protection Option Bytes value.
static uint32_t | FLASH_OB_GetIPCCBufferAddr (void)
Return the FLASH IPCC data buffer base address Option Byte value.
static void | FLASH_OB_GetSecureMemoryConfig (uint32_t *SecureFlashStartAddr, uint32_t *SecureRAM2aStartAddr, uint32_t *SecureRAM2bStartAddr, uint32_t *SecureMode)
Return the Secure Flash start address, Secure Backup RAM2a start address, Secure non-Backup RAM2b start address and the SecureMode.
static void | FLASH_OB_GetC2BootResetConfig (uint32_t *C2BootResetVectAddr, uint32_t *C2BootResetRegion)
Return the CPU2 Secure Boot reset vector address and the CPU2 Secure Boot Region.
static HAL_StatusTypeDef | FLASH_OB_ProceedWriteOperation (void)
Proceed the OB Write Operation.
HAL_StatusTypeDef | HAL_FLASHEx_Erase (FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
Perform a mass erase or erase the specified FLASH memory pages.
HAL_StatusTypeDef | HAL_FLASHEx_Erase_IT (FLASH_EraseInitTypeDef *pEraseInit)
Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.
HAL_StatusTypeDef | HAL_FLASHEx_OBProgram (FLASH_OBProgramInitTypeDef *pOBInit)
Program Option bytes.
void | HAL_FLASHEx_OBGetConfig (FLASH_OBProgramInitTypeDef *pOBInit)
Get the Option bytes configuration.
uint32_t | HAL_FLASHEx_FlashEmptyCheck (void)
Flash Empty check.
void | HAL_FLASHEx_ForceFlashEmpty (uint32_t FlashEmpty)
Force Empty check value.
void | HAL_FLASHEx_SuspendOperation (void)
Suspend new program or erase operation request.
void | HAL_FLASHEx_AllowOperation (void)
Allow new program or erase operation request.
uint32_t | HAL_FLASHEx_IsOperationSuspended (void)
Check if new program or erase operation request from CPU1 or CPU2 is suspended.
void | FLASH_PageErase (uint32_t Page)
Erase the specified FLASH memory page.

Detailed Description

Extended FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the FLASH extended peripheral: + Extended programming operations functions.

Author:
MCD Application Team
 ==============================================================================
                   ##### Flash Extended features #####
  ==============================================================================

  [..] Comparing to other previous devices, the FLASH interface for STM32WBxx
       devices contains the following additional features

       (+) Capacity up to 1 Mbyte with single bank architecture supporting read-while-write
           capability (RWW)
       (+) Single bank memory organization
       (+) PCROP protection
       (+) WRP protection
       (+) CPU2 Security area
       (+) Program Erase Suspend feature

                        ##### How to use this driver #####
 ==============================================================================
  [..] This driver provides functions to configure and program the FLASH memory
       of all STM32WBxx devices. It includes
      (#) Flash Memory Erase functions:
           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
                HAL_FLASH_Lock() functions
           (++) Erase function: Erase page, erase all sectors
           (++) There are two modes of erase :
             (+++) Polling Mode using HAL_FLASHEx_Erase()
             (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()

      (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to :
        (++) Set/Reset the write protection (per 4 KByte)
        (++) Set the Read protection Level
        (++) Program the user Option Bytes
        (++) Configure the PCROP protection (per 2 KByte)
        (++) Configure the IPCC Buffer start Address
        (++) Configure the CPU2 boot region and reset vector start Address
        (++) Configure the Flash and SRAM2 secure area

      (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to :
        (++) Get the value of a write protection area
        (++) Know if the read protection is activated
        (++) Get the value of the user Option Bytes
        (++) Get the value of a PCROP area
        (++) Get the IPCC Buffer start Address
        (++) Get the CPU2 boot region and reset vector start Address
        (++) Get the Flash and SRAM2 secure area

      (#) Flash Suspend, Allow functions:
           (++) Suspend or Allow new program or erase operation request using HAL_FLASHEx_SuspendOperation() and
                HAL_FLASHEx_AllowOperation() functions

      (#) Check is flash content is empty or not using HAL_FLASHEx_FlashEmptyCheck().
          and modify this setting (for flash loader purpose e.g.) using
          HAL_FLASHEx_ForceFlashEmpty().
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_flash_ex.c.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_gpio.c File Reference

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Defines | Functions
stm32wbxx_hal_gpio.c File Reference

GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Defines

#define | GPIO_MODE (0x00000003u)
#define | EXTI_MODE (0x10000000u)
#define | GPIO_MODE_IT (0x00010000u)
#define | GPIO_MODE_EVT (0x00020000u)
#define | RISING_EDGE (0x00100000u)
#define | FALLING_EDGE (0x00200000u)
#define | GPIO_OUTPUT_TYPE (0x00000010u)
#define | GPIO_NUMBER (16u)

Functions

void | HAL_GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
void | HAL_GPIO_DeInit (GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
De-initialize the GPIOx peripheral registers to their default reset values.
GPIO_PinState | HAL_GPIO_ReadPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Read the specified input port pin.
void | HAL_GPIO_WritePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
Set or clear the selected data port bit.
void | HAL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Toggle the specified GPIO pin.
HAL_StatusTypeDef | HAL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Lock GPIO Pins configuration registers.
void | HAL_GPIO_EXTI_IRQHandler (uint16_t GPIO_Pin)
Handle EXTI interrupt request.
__weak void | HAL_GPIO_EXTI_Callback (uint16_t GPIO_Pin)
EXTI line detection callback.

Detailed Description

GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions.

Author:
MCD Application Team
  ==============================================================================
                    ##### GPIO Peripheral features #####
  ==============================================================================
  [..]
    (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
        configured by software in several modes:
        (++) Input mode
        (++) Analog mode
        (++) Output mode
        (++) Alternate function mode
        (++) External interrupt/event lines

    (+) During and just after reset, the alternate functions and external interrupt
        lines are not active and the I/O ports are configured in input floating mode.

    (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
        activated or not.

    (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
        type and the IO speed can be selected depending on the VDD value.

    (+) The microcontroller IO pins are connected to onboard peripherals/modules through a
        multiplexer that allows only one peripheral alternate function (AF) connected
       to an IO pin at a time. In this way, there can be no conflict between peripherals
       sharing the same IO pin.

    (+) All ports have external interrupt/event capability. To use external interrupt
        lines, the port must be configured in input mode. All available GPIO pins are
        connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.

    (+) The external interrupt/event controller consists of up to 28 edge detectors
        (16 lines are connected to GPIO) for generating event/interrupt requests (each
        input line can be independently configured to select the type (interrupt or event)
        and the corresponding trigger event (rising or falling or both). Each line can
        also be masked independently.

                     ##### How to use this driver #####
  ==============================================================================
  [..]
    (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().

    (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
        (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
        (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
             structure.
        (++) In case of Output or alternate function mode selection: the speed is
             configured through "Speed" member from GPIO_InitTypeDef structure.
        (++) In alternate mode is selection, the alternate function connected to the IO
             is configured through "Alternate" member from GPIO_InitTypeDef structure.
        (++) Analog mode is required when a pin is to be used as ADC channel
             or DAC output.
        (++) In case of external interrupt/event selection the "Mode" member from
             GPIO_InitTypeDef structure select the type (interrupt or event) and
             the corresponding trigger event (rising or falling or both).

    (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
        mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
        HAL_NVIC_EnableIRQ().

    (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().

    (#) To set/reset the level of a pin configured in output mode use
        HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().

   (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().

    (#) During and just after reset, the alternate functions are not
        active and the GPIO pins are configured in input floating mode (except JTAG
        pins).

    (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
        (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
        priority over the GPIO function.

    (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
        general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
        The HSE has priority over the GPIO function.
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_gpio.c.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_hsem.c File Reference

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Functions
stm32wbxx_hal_hsem.c File Reference

HSEM HAL module driver. This file provides firmware functions to manage the following functionalities of the semaphore peripheral: + Semaphore Take function (2-Step Procedure) , non blocking + Semaphore FastTake function (1-Step Procedure) , non blocking + Semaphore Status check + Semaphore Clear Key Set and Get + Release and release all functions + Semaphore notification enabling and disabling and callnack functions + IRQ handler management. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_HSEM_Take (uint32_t SemID, uint32_t ProcessID)
Take a semaphore in 2 Step mode.
HAL_StatusTypeDef | HAL_HSEM_FastTake (uint32_t SemID)
Fast Take a semaphore with 1 Step mode.
uint32_t | HAL_HSEM_IsSemTaken (uint32_t SemID)
Check semaphore state Taken or not.
void | HAL_HSEM_Release (uint32_t SemID, uint32_t ProcessID)
Release a semaphore.
void | HAL_HSEM_ReleaseAll (uint32_t Key, uint32_t CoreID)
Release All semaphore used by a given Master .
void | HAL_HSEM_SetClearKey (uint32_t Key)
Set semaphore Key .
uint32_t | HAL_HSEM_GetClearKey (void)
Get semaphore Key .
void | HAL_HSEM_ActivateNotification (uint32_t SemMask)
Activate Semaphore release Notification for a given Semaphores Mask .
void | HAL_HSEM_DeactivateNotification (uint32_t SemMask)
Deactivate Semaphore release Notification for a given Semaphores Mask .
void | HAL_HSEM_IRQHandler (void)
This function handles HSEM interrupt request.
__weak void | HAL_HSEM_FreeCallback (uint32_t SemMask)
Semaphore Released Callback.

Detailed Description

HSEM HAL module driver. This file provides firmware functions to manage the following functionalities of the semaphore peripheral: + Semaphore Take function (2-Step Procedure) , non blocking + Semaphore FastTake function (1-Step Procedure) , non blocking + Semaphore Status check + Semaphore Clear Key Set and Get + Release and release all functions + Semaphore notification enabling and disabling and callnack functions + IRQ handler management.

Author:
MCD Application Team
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
  [..]
      (#)Take a semaphore In 2-Step mode Using function HAL_HSEM_Take. This function takes as parameters :
           (++) the semaphore ID from 0 to 31
           (++) the process ID from 0 to 255
      (#) Fast Take semaphore In 1-Step mode Using function HAL_HSEM_FastTake. This function takes as parameter :
           (++) the semaphore ID from 0_ID to 31. Note that the process ID value is implicitly assumed as zero
      (#) Check if a semaphore is Taken using function HAL_HSEM_IsSemTaken. This function takes as parameter :
          (++) the semaphore ID from 0_ID to 31
          (++) It returns 1 if the given semaphore is taken otherwise (Free) zero
      (#)Release a semaphore using function with HAL_HSEM_Release. This function takes as parameters :
           (++) the semaphore ID from 0 to 31
           (++) the process ID from 0 to 255:
           (++) Note: If ProcessID and MasterID match, semaphore is freed, and an interrupt
         may be generated when enabled (notification activated). If ProcessID or MasterID does not match,
         semaphore remains taken (locked)

      (#)Release all semaphores at once taken by a given Master using function HAL_HSEM_Release_All
          This function takes as parameters :
           (++) the Release Key (value from 0 to 0xFFFF) can be Set or Get respectively by
              HAL_HSEM_SetClearKey() or HAL_HSEM_GetClearKey functions
           (++) the Master ID:
           (++) Note: If the Key and MasterID match, all semaphores taken by the given CPU that corresponds
           to MasterID  will be freed, and an interrupt may be generated when enabled (notification activated). If the
           Key or the MasterID doesn't match, semaphores remains taken (locked)

      (#)Semaphores Release all key functions:
         (++)  HAL_HSEM_SetClearKey() to set semaphore release all Key
         (++)  HAL_HSEM_GetClearKey() to get release all Key
      (#)Semaphores notification functions :
         (++)  HAL_HSEM_ActivateNotification to activate a notification callback on
               a given semaphores Mask (bitfield). When one or more semaphores defined by the mask are released
               the callback HAL_HSEM_FreeCallback will be asserted giving as parameters a mask of the released
               semaphores (bitfield).

         (++)  HAL_HSEM_DeactivateNotification to deactivate the notification of a given semaphores Mask (bitfield).
         (++) See the description of the macro __HAL_HSEM_SEMID_TO_MASK to check how to calculate a semaphore mask
                Used by the notification functions
     *** HSEM HAL driver macros list ***
     =============================================
     [..] Below the list of most used macros in HSEM HAL driver.

      (+) __HAL_HSEM_SEMID_TO_MASK: Helper macro to convert a Semaphore ID to a Mask.
      [..] Example of use :
      [..] mask = __HAL_HSEM_SEMID_TO_MASK(8)  |  __HAL_HSEM_SEMID_TO_MASK(21) | __HAL_HSEM_SEMID_TO_MASK(25).
      [..] All next macros take as parameter a semaphore Mask (bitfiled) that can be constructed using  __HAL_HSEM_SEMID_TO_MASK as the above example.
      (+) __HAL_HSEM_ENABLE_IT: Enable the specified semaphores Mask interrupts.
      (+) __HAL_HSEM_DISABLE_IT: Disable the specified semaphores Mask interrupts.
      (+) __HAL_HSEM_GET_IT: Checks whether the specified semaphore interrupt has occurred or not.
      (+) __HAL_HSEM_GET_FLAG: Get the semaphores status release flags.
      (+) __HAL_HSEM_CLEAR_FLAG: Clear the semaphores status release flags.
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_hsem.c.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_i2c.c File Reference

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Defines | Functions
stm32wbxx_hal_i2c.c File Reference

I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Defines

#define | TIMING_CLEAR_MASK (0xF0FFFFFFU)
#define | I2C_TIMEOUT_ADDR (10000U)
#define | I2C_TIMEOUT_BUSY (25U)
#define | I2C_TIMEOUT_DIR (25U)
#define | I2C_TIMEOUT_RXNE (25U)
#define | I2C_TIMEOUT_STOPF (25U)
#define | I2C_TIMEOUT_TC (25U)
#define | I2C_TIMEOUT_TCR (25U)
#define | I2C_TIMEOUT_TXIS (25U)
#define | I2C_TIMEOUT_FLAG (25U)
#define | MAX_NBYTE_SIZE 255U
#define | SlaveAddr_SHIFT 7U
#define | SlaveAddr_MSK 0x06U
#define | I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY))))
#define | I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
#define | I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))
#define | I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))
#define | I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))
#define | I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))
#define | I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM))
#define | I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM))
#define | I2C_XFER_TX_IT (0x00000001U)
#define | I2C_XFER_RX_IT (0x00000002U)
#define | I2C_XFER_LISTEN_IT (0x00000004U)
#define | I2C_XFER_ERROR_IT (0x00000011U)
#define | I2C_XFER_CPLT_IT (0x00000012U)
#define | I2C_XFER_RELOAD_IT (0x00000012U)
#define | I2C_NO_OPTION_FRAME (0xFFFF0000U)

Functions

static void | I2C_DMAMasterTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C master transmit process complete callback.
static void | I2C_DMAMasterReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C master receive process complete callback.
static void | I2C_DMASlaveTransmitCplt (DMA_HandleTypeDef *hdma)
DMA I2C slave transmit process complete callback.
static void | I2C_DMASlaveReceiveCplt (DMA_HandleTypeDef *hdma)
DMA I2C slave receive process complete callback.
static void | I2C_DMAError (DMA_HandleTypeDef *hdma)
DMA I2C communication error callback.
static void | I2C_DMAAbort (DMA_HandleTypeDef *hdma)
DMA I2C communication abort callback (To be called at end of DMA Abort procedure).
static void | I2C_ITAddrCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Address complete process callback.
static void | I2C_ITMasterSeqCplt (I2C_HandleTypeDef *hi2c)
I2C Master sequential complete process.
static void | I2C_ITSlaveSeqCplt (I2C_HandleTypeDef *hi2c)
I2C Slave sequential complete process.
static void | I2C_ITMasterCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Master complete process.
static void | I2C_ITSlaveCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Slave complete process.
static void | I2C_ITListenCplt (I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C Listen complete process.
static void | I2C_ITError (I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
I2C interrupts error process.
static HAL_StatusTypeDef | I2C_RequestMemoryWrite (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
Master sends target device address followed by internal memory address for write request.
static HAL_StatusTypeDef | I2C_RequestMemoryRead (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
Master sends target device address followed by internal memory address for read request.
static HAL_StatusTypeDef | I2C_Master_ISR_IT (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
static HAL_StatusTypeDef | I2C_Slave_ISR_IT (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
static HAL_StatusTypeDef | I2C_Master_ISR_DMA (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
static HAL_StatusTypeDef | I2C_Slave_ISR_DMA (struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
static HAL_StatusTypeDef | I2C_WaitOnFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout.
static HAL_StatusTypeDef | I2C_WaitOnTXISFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of TXIS flag.
static HAL_StatusTypeDef | I2C_WaitOnRXNEFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of RXNE flag.
static HAL_StatusTypeDef | I2C_WaitOnSTOPFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of STOP flag.
static HAL_StatusTypeDef | I2C_IsAcknowledgeFailed (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles Acknowledge failed detection during an I2C Communication.
static void | I2C_Enable_IRQ (I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
Manage the enabling of Interrupts.
static void | I2C_Disable_IRQ (I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
Manage the disabling of Interrupts.
static void | I2C_Flush_TXDR (I2C_HandleTypeDef *hi2c)
I2C Tx data register flush process.
static void | I2C_TransferConfig (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
static void | I2C_ConvertOtherXferOptions (I2C_HandleTypeDef *hi2c)
Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions.
HAL_StatusTypeDef | HAL_I2C_Init (I2C_HandleTypeDef *hi2c)
Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C peripheral.
__weak void | HAL_I2C_MspInit (I2C_HandleTypeDef *hi2c)
Initialize the I2C MSP.
__weak void | HAL_I2C_MspDeInit (I2C_HandleTypeDef *hi2c)
DeInitialize the I2C MSP.
HAL_StatusTypeDef | HAL_I2C_RegisterCallback (I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)
Register a User I2C Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_I2C_UnRegisterCallback (I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
Unregister an I2C Callback I2C callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_I2C_RegisterAddrCallback (I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
Register the Slave Address Match I2C Callback To be used instead of the weak HAL_I2C_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_I2C_UnRegisterAddrCallback (I2C_HandleTypeDef *hi2c)
UnRegister the Slave Address Match I2C Callback Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Receive (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Mem_Write (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Write an amount of data in blocking mode to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Read an amount of data in blocking mode from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with Interrupt to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Read an amount of data in non-blocking mode with Interrupt from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with DMA to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Reads an amount of data in non-blocking mode with DMA from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_IsDeviceReady (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Checks if target device is ready for communication.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Seq_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Seq_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_EnableListen_IT (I2C_HandleTypeDef *hi2c)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_DisableListen_IT (I2C_HandleTypeDef *hi2c)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Abort_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
Abort a master I2C IT or DMA process communication with Interrupt.
void | HAL_I2C_EV_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C event interrupt request.
void | HAL_I2C_ER_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C error interrupt request.
__weak void | HAL_I2C_MasterTxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Tx Transfer completed callback.
__weak void | HAL_I2C_MasterRxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Rx Transfer completed callback.
__weak void | HAL_I2C_SlaveTxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Tx Transfer completed callback.
__weak void | HAL_I2C_SlaveRxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Rx Transfer completed callback.
__weak void | HAL_I2C_AddrCallback (I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_I2C_ListenCpltCallback (I2C_HandleTypeDef *hi2c)
Listen Complete callback.
__weak void | HAL_I2C_MemTxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Tx Transfer completed callback.
__weak void | HAL_I2C_MemRxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Rx Transfer completed callback.
__weak void | HAL_I2C_ErrorCallback (I2C_HandleTypeDef *hi2c)
I2C error callback.
__weak void | HAL_I2C_AbortCpltCallback (I2C_HandleTypeDef *hi2c)
I2C abort callback.
HAL_I2C_StateTypeDef | HAL_I2C_GetState (I2C_HandleTypeDef *hi2c)
Return the I2C handle state.
HAL_I2C_ModeTypeDef | HAL_I2C_GetMode (I2C_HandleTypeDef *hi2c)
Returns the I2C Master, Slave, Memory or no mode.
uint32_t | HAL_I2C_GetError (I2C_HandleTypeDef *hi2c)
Return the I2C error code.

Detailed Description

I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
    The I2C HAL driver can be used as follows:

    (#) Declare a I2C_HandleTypeDef handle structure, for example:
        I2C_HandleTypeDef  hi2c;

    (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API:
        (##) Enable the I2Cx interface clock
        (##) I2C pins configuration
            (+++) Enable the clock for the I2C GPIOs
            (+++) Configure I2C pins as alternate function open-drain
        (##) NVIC configuration if you need to use interrupt process
            (+++) Configure the I2Cx interrupt priority
            (+++) Enable the NVIC I2C IRQ Channel
        (##) DMA Configuration if you need to use DMA process
            (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
            (+++) Enable the DMAx interface clock using
            (+++) Configure the DMA handle parameters
            (+++) Configure the DMA Tx or Rx channel
            (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
                  the DMA Tx or Rx channel

    (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
        Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.

    (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware
        (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit(&hi2c) API.

    (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady()

    (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :

    *** Polling mode IO operation ***
    =================================
    [..]
      (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit()
      (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive()
      (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit()
      (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive()

    *** Polling mode IO MEM operation ***
    =====================================
    [..]
      (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write()
      (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read()

    *** Interrupt mode IO operation ***
    ===================================
    [..]
      (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT()
      (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
      (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT()
      (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
      (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT()
      (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
      (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT()
      (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
      (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
      (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
      (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
           This action will inform Master to generate a Stop condition to discard the communication.

    *** Interrupt mode or DMA mode IO sequential operation ***
    ==========================================================
    [..]
      (@) These interfaces allow to manage a sequential transfer with a repeated start condition
          when a direction change during transfer
    [..]
      (+) A specific option field manage the different steps of a sequential transfer
      (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
      (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
      (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
                            and data to transfer without a final stop condition
      (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
                            and data to transfer without a final stop condition, an then permit a call the same master sequential interface
                            several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT()
                            or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA())
      (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
                            and with new data to transfer if the direction change or manage only the new data to transfer
                            if no direction change and without a final stop condition in both cases
      (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
                            and with new data to transfer if the direction change or manage only the new data to transfer
                            if no direction change and with a final stop condition in both cases
      (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential
                            interface several times (link with option I2C_FIRST_AND_NEXT_FRAME).
                            Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
                              or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
                              or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
                              or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).
                            Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit
                              without stopping the communication and so generate a restart condition.
      (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential
                            interface.
                            Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
                              or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
                              or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
                              or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME).
                            Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition.

      (+) Differents sequential I2C interfaces are listed below:
      (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT()
            or using @ref HAL_I2C_Master_Seq_Transmit_DMA()
      (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
      (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Receive_IT()
            or using @ref HAL_I2C_Master_Seq_Receive_DMA()
      (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
      (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
      (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
      (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT()
      (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can
           add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
      (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback()
      (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Transmit_IT()
            or using @ref HAL_I2C_Slave_Seq_Transmit_DMA()
      (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
      (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Receive_IT()
            or using @ref HAL_I2C_Slave_Seq_Receive_DMA()
      (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
      (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
      (++) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
           This action will inform Master to generate a Stop condition to discard the communication.

    *** Interrupt mode IO MEM operation ***
    =======================================
    [..]
      (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
          @ref HAL_I2C_Mem_Write_IT()
      (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
      (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
          @ref HAL_I2C_Mem_Read_IT()
      (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()

    *** DMA mode IO operation ***
    ==============================
    [..]
      (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
          @ref HAL_I2C_Master_Transmit_DMA()
      (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
      (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
          @ref HAL_I2C_Master_Receive_DMA()
      (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
      (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
          @ref HAL_I2C_Slave_Transmit_DMA()
      (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
      (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
          @ref HAL_I2C_Slave_Receive_DMA()
      (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
      (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
      (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
      (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
           This action will inform Master to generate a Stop condition to discard the communication.

    *** DMA mode IO MEM operation ***
    =================================
    [..]
      (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
          @ref HAL_I2C_Mem_Write_DMA()
      (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
      (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
          @ref HAL_I2C_Mem_Read_DMA()
      (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()

     *** I2C HAL driver macros list ***
     ==================================
     [..]
       Below the list of most used macros in I2C HAL driver.

      (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral
      (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral
      (+) @ref __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
      (+) @ref __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
      (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
      (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
      (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt

     *** Callback registration ***
     =============================================
    [..]
     The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
     allows the user to configure dynamically the driver callbacks.
     Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback()
     to register an interrupt callback.
    [..]
     Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks:
       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
       (+) ListenCpltCallback   : callback for end of listen mode.
       (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
       (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
       (+) ErrorCallback        : callback for error detection.
       (+) AbortCpltCallback    : callback for abort completion process.
       (+) MspInitCallback      : callback for Msp Init.
       (+) MspDeInitCallback    : callback for Msp DeInit.
     This function takes as parameters the HAL peripheral handle, the Callback ID
     and a pointer to the user callback function.
    [..]
     For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback().
    [..]
     Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default
     weak function.
     @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
     and the Callback ID.
     This function allows to reset following callbacks:
       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
       (+) ListenCpltCallback   : callback for end of listen mode.
       (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
       (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
       (+) ErrorCallback        : callback for error detection.
       (+) AbortCpltCallback    : callback for abort completion process.
       (+) MspInitCallback      : callback for Msp Init.
       (+) MspDeInitCallback    : callback for Msp DeInit.
    [..]
     For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback().
    [..]
     By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET
     all callbacks are set to the corresponding weak functions:
     examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback().
     Exception done for MspInit and MspDeInit functions that are
     reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when
     these callbacks are null (not registered beforehand).
     If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit()
     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
    [..]
     Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
     Exception done MspInit/MspDeInit functions that can be registered/unregistered
     in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
     Then, the user first registers the MspInit/MspDeInit user callbacks
     using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit()
     or @ref HAL_I2C_Init() function.
    [..]
     When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
     not defined, the callback registration feature is not available and all callbacks
     are set to the corresponding weak functions.

     [..]
       (@) You can refer to the I2C HAL driver header file for more useful macros
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_i2c.c.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_i2c_ex.c File Reference

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  • STM32WBxx_HAL_Driver
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Functions
stm32wbxx_hal_i2c_ex.c File Reference

I2C Extended HAL module driver. This file provides firmware functions to manage the following functionalities of I2C Extended peripheral: + Extended features functions. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_I2CEx_ConfigAnalogFilter (I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
Configure I2C Analog noise filter.
HAL_StatusTypeDef | HAL_I2CEx_ConfigDigitalFilter (I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
Configure I2C Digital noise filter.
HAL_StatusTypeDef | HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
Enable I2C wakeup from Stop mode(s).
HAL_StatusTypeDef | HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
Disable I2C wakeup from Stop mode(s).
void | HAL_I2CEx_EnableFastModePlus (uint32_t ConfigFastModePlus)
Enable the I2C fast mode plus driving capability.
void | HAL_I2CEx_DisableFastModePlus (uint32_t ConfigFastModePlus)
Disable the I2C fast mode plus driving capability.

Detailed Description

I2C Extended HAL module driver. This file provides firmware functions to manage the following functionalities of I2C Extended peripheral: + Extended features functions.

Author:
MCD Application Team
  ==============================================================================
               ##### I2C peripheral Extended features  #####
  ==============================================================================

  [..] Comparing to other previous devices, the I2C interface for STM32WBxx
       devices contains the following additional features

       (+) Possibility to disable or enable Analog Noise Filter
       (+) Use of a configured Digital Noise Filter
       (+) Disable or enable wakeup from Stop mode(s)
       (+) Disable or enable Fast Mode Plus

                     ##### How to use this driver #####
  ==============================================================================
  [..] This driver provides functions to configure Noise Filter and Wake Up Feature
    (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
    (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
    (#) Configure the enable or disable of I2C Wake Up Mode using the functions :
          (++) HAL_I2CEx_EnableWakeUp()
          (++) HAL_I2CEx_DisableWakeUp()
    (#) Configure the enable or disable of fast mode plus driving capability using the functions :
          (++) HAL_I2CEx_EnableFastModePlus()
          (++) HAL_I2CEx_DisableFastModePlus()
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_i2c_ex.c.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_ipcc.c File Reference

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Defines | Functions
stm32wbxx_hal_ipcc.c File Reference

IPCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter-Processor communication controller peripherals (IPCC). + Initialization and de-initialization functions + Configuration, notification and interrupts handling + Peripheral State and Error functions. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Defines

#define | IPCC_ALL_RX_BUF 0x0000003FU
#define | IPCC_ALL_TX_BUF 0x003F0000U
#define | CHANNEL_INDEX_Msk 0x0000000FU

Functions

void | IPCC_MaskInterrupt (uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
Mask IPCC interrupts.
void | IPCC_UnmaskInterrupt (uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
Unmask IPCC interrupts.
void | IPCC_SetDefaultCallbacks (IPCC_HandleTypeDef *hipcc)
Reset all callbacks of the handle to NULL.
void | IPCC_Reset_Register (IPCC_CommonTypeDef *Instance)
Reset IPCC register to default value for the concerned instance.
HAL_StatusTypeDef | HAL_IPCC_Init (IPCC_HandleTypeDef *hipcc)
Initialize the IPCC peripheral.
HAL_StatusTypeDef | HAL_IPCC_DeInit (IPCC_HandleTypeDef *hipcc)
DeInitialize the IPCC peripheral.
__weak void | HAL_IPCC_MspInit (IPCC_HandleTypeDef *hipcc)
Initialize the IPCC MSP.
__weak void | HAL_IPCC_MspDeInit (IPCC_HandleTypeDef *hipcc)
IPCC MSP DeInit.
HAL_StatusTypeDef | HAL_IPCC_ActivateNotification (IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir, ChannelCb cb)
Activate the callback notification on receive/transmit interrupt.
HAL_StatusTypeDef | HAL_IPCC_DeActivateNotification (IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
Remove the callback notification on receive/transmit interrupt.
IPCC_CHANNELStatusTypeDef | HAL_IPCC_GetChannelStatus (IPCC_HandleTypeDef const *const hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
Get state of IPCC channel.
HAL_StatusTypeDef | HAL_IPCC_NotifyCPU (IPCC_HandleTypeDef const *const hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
Notify remote processor.
void | HAL_IPCC_TX_IRQHandler (IPCC_HandleTypeDef *const hipcc)
This function handles IPCC Tx Free interrupt request.
void | HAL_IPCC_RX_IRQHandler (IPCC_HandleTypeDef *const hipcc)
This function handles IPCC Rx Occupied interrupt request.
__weak void | HAL_IPCC_RxCallback (IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
Rx occupied callback.
__weak void | HAL_IPCC_TxCallback (IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
Tx free callback.
HAL_IPCC_StateTypeDef | HAL_IPCC_GetState (IPCC_HandleTypeDef const *const hipcc)
Return the IPCC handle state.

Detailed Description

IPCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter-Processor communication controller peripherals (IPCC). + Initialization and de-initialization functions + Configuration, notification and interrupts handling + Peripheral State and Error functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
      The IPCC HAL driver can be used as follows:

      (#) Declare a IPCC_HandleTypeDef handle structure, for example: IPCC_HandleTypeDef hipcc;
      (#) Initialize the IPCC low level resources by implementing the HAL_IPCC_MspInit() API:
        (##) Enable the IPCC interface clock
        (##) NVIC configuration if you need to use interrupt process
            (+++) Configure the IPCC interrupt priority
            (+++) Enable the NVIC IPCC IRQ

      (#) Initialize the IPCC registers by calling the HAL_IPCC_Init() API which trig
          HAL_IPCC_MspInit().

      (#) Implement the interrupt callbacks for transmission and reception to use the driver in interrupt mode

      (#) Associate those callback to the corresponding channel and direction using HAL_IPCC_ConfigChannel().
          This is the interrupt mode.
          If no callback are configured for a given channel and direction, it is up to the user to poll the
          status of the communication (polling mode).

      (#) Notify the other MCU when a message is available in a chosen channel
          or when a message has been retrieved from a chosen channel by calling
          the HAL_IPCC_NotifyCPU() API.
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_ipcc.c.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_irda.c File Reference

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Defines | Functions
stm32wbxx_hal_irda.c File Reference

IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA (Infrared Data Association) Peripheral (IRDA) + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions + Peripheral Control functions. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Defines

#define | IRDA_TEACK_REACK_TIMEOUT 1000U
#define | IRDA_CR1_FIELDS
#define | USART_BRR_MIN 0x10U
#define | USART_BRR_MAX 0x0000FFFFU
#define | IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__, __PRESCALER__) ((((__PCLK__)/IRDAPrescTable[(__PRESCALER__)]) + ((__BAUD__)/2U)) / (__BAUD__))
BRR division operation to set BRR register in 16-bit oversampling mode.

Functions

void | IRDA_InitCallbacksToDefault (IRDA_HandleTypeDef *hirda)
Initialize the callbacks to their default values.
static HAL_StatusTypeDef | IRDA_SetConfig (IRDA_HandleTypeDef *hirda)
Configure the IRDA peripheral.
static HAL_StatusTypeDef | IRDA_CheckIdleState (IRDA_HandleTypeDef *hirda)
Check the IRDA Idle State.
static HAL_StatusTypeDef | IRDA_WaitOnFlagUntilTimeout (IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle IRDA Communication Timeout.
static void | IRDA_EndTxTransfer (IRDA_HandleTypeDef *hirda)
End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
static void | IRDA_EndRxTransfer (IRDA_HandleTypeDef *hirda)
End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
static void | IRDA_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA IRDA transmit process complete callback.
static void | IRDA_DMATransmitHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA transmit process half complete callback.
static void | IRDA_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process complete callback.
static void | IRDA_DMAReceiveHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process half complete callback.
static void | IRDA_DMAError (DMA_HandleTypeDef *hdma)
DMA IRDA communication error callback.
static void | IRDA_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA IRDA communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | IRDA_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | IRDA_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | IRDA_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Tx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | IRDA_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Rx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static void | IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda)
Send an amount of data in interrupt mode.
static void | IRDA_EndTransmit_IT (IRDA_HandleTypeDef *hirda)
Wrap up transmission in non-blocking mode.
static void | IRDA_Receive_IT (IRDA_HandleTypeDef *hirda)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Init (IRDA_HandleTypeDef *hirda)
Initialize the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_IRDA_DeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA peripheral.
__weak void | HAL_IRDA_MspInit (IRDA_HandleTypeDef *hirda)
Initialize the IRDA MSP.
__weak void | HAL_IRDA_MspDeInit (IRDA_HandleTypeDef *hirda)
DeInitialize the IRDA MSP.
HAL_StatusTypeDef | HAL_IRDA_RegisterCallback (IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback)
Register a User IRDA Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_IRDA_UnRegisterCallback (IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID)
Unregister an IRDA callback IRDA callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_IRDA_Transmit (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_IRDA_DMAPause (IRDA_HandleTypeDef *hirda)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAResume (IRDA_HandleTypeDef *hirda)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAStop (IRDA_HandleTypeDef *hirda)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_Abort (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_Abort_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_IRDA_IRQHandler (IRDA_HandleTypeDef *hirda)
Handle IRDA interrupt request.
__weak void | HAL_IRDA_TxCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Transfer completed callback.
__weak void | HAL_IRDA_TxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Half Transfer completed callback.
__weak void | HAL_IRDA_RxCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Transfer completed callback.
__weak void | HAL_IRDA_RxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Half Transfer complete callback.
__weak void | HAL_IRDA_ErrorCallback (IRDA_HandleTypeDef *hirda)
IRDA error callback.
__weak void | HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Complete callback.
__weak void | HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Complete callback.
__weak void | HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Receive Complete callback.
HAL_IRDA_StateTypeDef | HAL_IRDA_GetState (IRDA_HandleTypeDef *hirda)
Return the IRDA handle state.
uint32_t | HAL_IRDA_GetError (IRDA_HandleTypeDef *hirda)
Return the IRDA handle error code.

Detailed Description

IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA (Infrared Data Association) Peripheral (IRDA) + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions + Peripheral Control functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
    The IRDA HAL driver can be used as follows:

    (#) Declare a IRDA_HandleTypeDef handle structure (eg. IRDA_HandleTypeDef hirda).
    (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API
        in setting the associated USART or UART in IRDA mode:
        (++) Enable the USARTx/UARTx interface clock.
        (++) USARTx/UARTx pins configuration:
            (+++) Enable the clock for the USARTx/UARTx GPIOs.
            (+++) Configure these USARTx/UARTx pins (TX as alternate function pull-up, RX as alternate function Input).
        (++) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
             and HAL_IRDA_Receive_IT() APIs):
            (+++) Configure the USARTx/UARTx interrupt priority.
            (+++) Enable the NVIC USARTx/UARTx IRQ handle.
            (+++) The specific IRDA interrupts (Transmission complete interrupt,
                  RXNE interrupt and Error Interrupts) will be managed using the macros
                  __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.

        (++) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
             and HAL_IRDA_Receive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx channel.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx channel.
            (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.

    (#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter),
        the normal or low power mode and the clock prescaler in the hirda handle Init structure.

    (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
        (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
             by calling the customized HAL_IRDA_MspInit() API.

         -@@- The specific IRDA interrupts (Transmission complete interrupt,
             RXNE interrupt and Error Interrupts) will be managed using the macros
             __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.

    (#) Three operation modes are available within this driver :

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
       (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()

     *** Interrupt mode IO operation ***
     ===================================
     [..]
       (+) Send an amount of data in non-blocking mode using HAL_IRDA_Transmit_IT()
       (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
       (+) Receive an amount of data in non-blocking mode using HAL_IRDA_Receive_IT()
       (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
       (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_IRDA_ErrorCallback()

     *** DMA mode IO operation ***
     ==============================
     [..]
       (+) Send an amount of data in non-blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
       (+) At transmission half of transfer HAL_IRDA_TxHalfCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback()
       (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
       (+) Receive an amount of data in non-blocking mode (DMA) using HAL_IRDA_Receive_DMA()
       (+) At reception half of transfer HAL_IRDA_RxHalfCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback()
       (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
       (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_IRDA_ErrorCallback()

     *** IRDA HAL driver macros list ***
     ====================================
     [..]
       Below the list of most used macros in IRDA HAL driver.

       (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
       (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
       (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
       (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
       (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
       (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
       (+) __HAL_IRDA_GET_IT_SOURCE: Check whether or not the specified IRDA interrupt is enabled

     [..]
       (@) You can refer to the IRDA HAL driver header file for more useful macros

    ##### Callback registration #####
    ==================================

    [..]
    The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS when set to 1
    allows the user to configure dynamically the driver callbacks.

    [..]
    Use Function @ref HAL_IRDA_RegisterCallback() to register a user callback.
    Function @ref HAL_IRDA_RegisterCallback() allows to register following callbacks:
    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
    (+) TxCpltCallback            : Tx Complete Callback.
    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
    (+) RxCpltCallback            : Rx Complete Callback.
    (+) ErrorCallback             : Error Callback.
    (+) AbortCpltCallback         : Abort Complete Callback.
    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
    (+) MspInitCallback           : IRDA MspInit.
    (+) MspDeInitCallback         : IRDA MspDeInit.
    This function takes as parameters the HAL peripheral handle, the Callback ID
    and a pointer to the user callback function.

    [..]
    Use function @ref HAL_IRDA_UnRegisterCallback() to reset a callback to the default
    weak (surcharged) function.
    @ref HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle,
    and the Callback ID.
    This function allows to reset following callbacks:
    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
    (+) TxCpltCallback            : Tx Complete Callback.
    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
    (+) RxCpltCallback            : Rx Complete Callback.
    (+) ErrorCallback             : Error Callback.
    (+) AbortCpltCallback         : Abort Complete Callback.
    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
    (+) MspInitCallback           : IRDA MspInit.
    (+) MspDeInitCallback         : IRDA MspDeInit.

    [..]
    By default, after the @ref HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET
    all callbacks are set to the corresponding weak (surcharged) functions:
    examples @ref HAL_IRDA_TxCpltCallback(), @ref HAL_IRDA_RxHalfCpltCallback().
    Exception done for MspInit and MspDeInit functions that are respectively
    reset to the legacy weak (surcharged) functions in the @ref HAL_IRDA_Init()
    and @ref HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand).
    If not, MspInit or MspDeInit are not null, the @ref HAL_IRDA_Init() and @ref HAL_IRDA_DeInit()
    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).

    [..]
    Callbacks can be registered/unregistered in HAL_IRDA_STATE_READY state only.
    Exception done MspInit/MspDeInit that can be registered/unregistered
    in HAL_IRDA_STATE_READY or HAL_IRDA_STATE_RESET state, thus registered (user)
    MspInit/DeInit callbacks can be used during the Init/DeInit.
    In that case first register the MspInit/MspDeInit user callbacks
    using @ref HAL_IRDA_RegisterCallback() before calling @ref HAL_IRDA_DeInit()
    or @ref HAL_IRDA_Init() function.

    [..]
    When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or
    not defined, the callback registration feature is not available
    and weak (surcharged) callbacks are used.
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_irda.c.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_iwdg.c File Reference

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  • STM32WBxx_HAL_Driver
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stm32wbxx_hal_iwdg.c File Reference

IWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Independent Watchdog (IWDG) peripheral: + Initialization and Start functions + IO operation functions. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Defines

#define | HAL_IWDG_DEFAULT_TIMEOUT 48u

Functions

HAL_StatusTypeDef | HAL_IWDG_Init (IWDG_HandleTypeDef *hiwdg)
Initialize the IWDG according to the specified parameters in the IWDG_InitTypeDef and start watchdog.
HAL_StatusTypeDef | HAL_IWDG_Refresh (IWDG_HandleTypeDef *hiwdg)
Refresh the IWDG.

Detailed Description

IWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Independent Watchdog (IWDG) peripheral: + Initialization and Start functions + IO operation functions.

Author:
MCD Application Team
  ==============================================================================
                    ##### IWDG Generic features #####
  ==============================================================================
  [..]
    (+) The IWDG can be started by either software or hardware (configurable
        through option byte).

    (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
        if the main clock fails.

    (+) Once the IWDG is started, the LSI is forced ON and both can not be
        disabled. The counter starts counting down from the reset value (0xFFF).
        When it reaches the end of count value (0x000) a reset signal is
        generated (IWDG reset).

    (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
        the IWDG_RLR value is reloaded in the counter and the watchdog reset is
        prevented.

    (+) The IWDG is implemented in the VDD voltage domain that is still functional
        in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
        IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
        reset occurs.

    (+) Debug mode : When the microcontroller enters debug mode (core halted),
        the IWDG counter either continues to work normally or stops, depending
        on DBG_IWDG_STOP configuration bit in DBG module, accessible through
        __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros.

    [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
         The IWDG timeout may vary due to LSI frequency dispersion. STM32WBxx
         devices provide the capability to measure the LSI frequency (LSI clock
         connected internally to TIM16 CH1 input capture). The measured value
         can be used to have an IWDG timeout with an acceptable accuracy.

                     ##### How to use this driver #####
  ==============================================================================
  [..]
    (#) Use IWDG using HAL_IWDG_Init() function to :
      (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
           clock is forced ON and IWDG counter starts counting down.
      (++) Enable write access to configuration registers:
          IWDG_PR, IWDG_RLR and IWDG_WINR.
      (++) Configure the IWDG prescaler and counter reload value. This reload
           value will be loaded in the IWDG counter each time the watchdog is
           reloaded, then the IWDG will start counting down from this value.
      (++) Wait for status flags to be reset.
      (++) Depending on window parameter:
        (+++) If Window Init parameter is same as Window register value,
             nothing more is done but reload counter value in order to exit
             function with exact time base.
        (+++) Else modify Window register. This will automatically reload
             watchdog counter.

    (#) Then the application program must refresh the IWDG counter at regular
        intervals during normal operation to prevent an MCU reset, using
        HAL_IWDG_Refresh() function.

     *** IWDG HAL driver macros list ***
     ====================================
     [..]
       Below the list of most used macros in IWDG HAL driver:
      (+) __HAL_IWDG_START: Enable the IWDG peripheral
      (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
          the reload register
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_iwdg.c.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_lcd.c File Reference

  • File List
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Defines | Functions
stm32wbxx_hal_lcd.c File Reference

LCD Controller HAL module driver. This file provides firmware functions to manage the following functionalities of the LCD Controller (LCD) peripheral: + Initialization/de-initialization methods + I/O operation methods + Peripheral State methods. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Defines

#define | LCD_TIMEOUT_VALUE 1000U

Functions

HAL_StatusTypeDef | HAL_LCD_Init (LCD_HandleTypeDef *hlcd)
Initialize the LCD peripheral according to the specified parameters in the LCD_InitStruct and initialize the associated handle.
HAL_StatusTypeDef | HAL_LCD_DeInit (LCD_HandleTypeDef *hlcd)
DeInitialize the LCD peripheral.
__weak void | HAL_LCD_MspDeInit (LCD_HandleTypeDef *hlcd)
DeInitialize the LCD MSP.
__weak void | HAL_LCD_MspInit (LCD_HandleTypeDef *hlcd)
Initialize the LCD MSP.
HAL_StatusTypeDef | HAL_LCD_Write (LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterIndex, uint32_t RAMRegisterMask, uint32_t Data)
Write a word in the specific LCD RAM.
HAL_StatusTypeDef | HAL_LCD_Clear (LCD_HandleTypeDef *hlcd)
Clear the LCD RAM registers.
HAL_StatusTypeDef | HAL_LCD_UpdateDisplayRequest (LCD_HandleTypeDef *hlcd)
Enable the Update Display Request.
HAL_LCD_StateTypeDef | HAL_LCD_GetState (LCD_HandleTypeDef *hlcd)
Return the LCD handle state.
uint32_t | HAL_LCD_GetError (LCD_HandleTypeDef *hlcd)
Return the LCD error code.
HAL_StatusTypeDef | LCD_WaitForSynchro (LCD_HandleTypeDef *hlcd)
Wait until the LCD FCR register is synchronized in the LCDCLK domain.

Detailed Description

LCD Controller HAL module driver. This file provides firmware functions to manage the following functionalities of the LCD Controller (LCD) peripheral: + Initialization/de-initialization methods + I/O operation methods + Peripheral State methods.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
      [..] The LCD HAL driver can be used as follows:

      (#) Declare a LCD_HandleTypeDef handle structure.

      -@- The frequency generator allows you to achieve various LCD frame rates
          starting from an LCD input clock frequency (LCDCLK) which can vary
          from 32 kHz up to 1 MHz.

      (#) Initialize the LCD low level resources by implementing the HAL_LCD_MspInit() API:

          (++) Enable the LCDCLK (same as RTCCLK): to configure the RTCCLK/LCDCLK, proceed as follows:
               (+++) Use RCC function HAL_RCCEx_PeriphCLKConfig in indicating RCC_PERIPHCLK_LCD and
                  selected clock source (HSE, LSI or LSE)

          (++) LCD pins configuration:
              (+++) Enable the clock for the LCD GPIOs.
              (+++) Configure these LCD pins as alternate function no-pull.
          (++) Enable the LCD interface clock.

      (#) Program the Prescaler, Divider, Blink mode, Blink Frequency Duty, Bias,
          Voltage Source, Dead Time, Pulse On Duration, Contrast, High drive and Multiplexer
          Segment in the Init structure of the LCD handle.

      (#) Initialize the LCD registers by calling the HAL_LCD_Init() API.

      -@- The HAL_LCD_Init() API configures also the low level Hardware GPIO, CLOCK, ...etc)
          by calling the customized HAL_LCD_MspInit() API.
      -@- After calling the HAL_LCD_Init() the LCD RAM memory is cleared

      (#) Optionally you can update the LCD configuration using these macros:
              (++) LCD High Drive using the __HAL_LCD_HIGHDRIVER_ENABLE() and __HAL_LCD_HIGHDRIVER_DISABLE() macros
              (++) Voltage output buffer using __HAL_LCD_VOLTAGE_BUFFER_ENABLE() and __HAL_LCD_VOLTAGE_BUFFER_DISABLE() macros
              (++) LCD Pulse ON Duration using the __HAL_LCD_PULSEONDURATION_CONFIG() macro
              (++) LCD Dead Time using the __HAL_LCD_DEADTIME_CONFIG() macro
              (++) The LCD Blink mode and frequency using the __HAL_LCD_BLINK_CONFIG() macro
              (++) The LCD Contrast using the __HAL_LCD_CONTRAST_CONFIG() macro

      (#) Write to the LCD RAM memory using the HAL_LCD_Write() API, this API can be called
          more time to update the different LCD RAM registers before calling
          HAL_LCD_UpdateDisplayRequest() API.

      (#) The HAL_LCD_Clear() API can be used to clear the LCD RAM memory.

      (#) When LCD RAM memory is updated enable the update display request using
          the HAL_LCD_UpdateDisplayRequest() API.

      [..] LCD and low power modes:
           (#) The LCD remain active during Sleep, Low Power run, Low Power Sleep and
               STOP modes.
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_lcd.c.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_lptim.c File Reference

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Defines | Functions
stm32wbxx_hal_lptim.c File Reference

LPTIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Low Power Timer (LPTIM) peripheral: + Initialization and de-initialization functions. + Start/Stop operation functions in polling mode. + Start/Stop operation functions in interrupt mode. + Reading operation functions. + Peripheral State functions. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Defines

#define | TIMEOUT 1000UL /* Timeout is 1s */

Functions

static void | LPTIM_ResetCallback (LPTIM_HandleTypeDef *lptim)
Reset interrupt callbacks to the legacy weak callbacks.
static HAL_StatusTypeDef | LPTIM_WaitForFlag (LPTIM_HandleTypeDef *hlptim, uint32_t flag)
LPTimer Wait for flag set.
HAL_StatusTypeDef | HAL_LPTIM_Init (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM according to the specified parameters in the LPTIM_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_LPTIM_DeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize the LPTIM peripheral.
__weak void | HAL_LPTIM_MspInit (LPTIM_HandleTypeDef *hlptim)
Initialize the LPTIM MSP.
__weak void | HAL_LPTIM_MspDeInit (LPTIM_HandleTypeDef *hlptim)
DeInitialize LPTIM MSP.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_PWM_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM PWM generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_OnePulse_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM One pulse generation in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM in Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
Start the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_SetOnce_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the LPTIM Set once mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Encoder_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Encoder interface in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
Start the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_TimeOut_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Timeout function in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Start_IT (LPTIM_HandleTypeDef *hlptim, uint32_t Period)
Start the Counter mode in interrupt mode.
HAL_StatusTypeDef | HAL_LPTIM_Counter_Stop_IT (LPTIM_HandleTypeDef *hlptim)
Stop the Counter mode in interrupt mode.
uint32_t | HAL_LPTIM_ReadCounter (LPTIM_HandleTypeDef *hlptim)
Return the current counter value.
uint32_t | HAL_LPTIM_ReadAutoReload (LPTIM_HandleTypeDef *hlptim)
Return the current Autoreload (Period) value.
uint32_t | HAL_LPTIM_ReadCompare (LPTIM_HandleTypeDef *hlptim)
Return the current Compare (Pulse) value.
void | HAL_LPTIM_IRQHandler (LPTIM_HandleTypeDef *hlptim)
Handle LPTIM interrupt request.
__weak void | HAL_LPTIM_CompareMatchCallback (LPTIM_HandleTypeDef *hlptim)
Compare match callback in non-blocking mode.
__weak void | HAL_LPTIM_AutoReloadMatchCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload match callback in non-blocking mode.
__weak void | HAL_LPTIM_TriggerCallback (LPTIM_HandleTypeDef *hlptim)
Trigger detected callback in non-blocking mode.
__weak void | HAL_LPTIM_CompareWriteCallback (LPTIM_HandleTypeDef *hlptim)
Compare write callback in non-blocking mode.
__weak void | HAL_LPTIM_AutoReloadWriteCallback (LPTIM_HandleTypeDef *hlptim)
Autoreload write callback in non-blocking mode.
__weak void | HAL_LPTIM_DirectionUpCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Down to Up callback in non-blocking mode.
__weak void | HAL_LPTIM_DirectionDownCallback (LPTIM_HandleTypeDef *hlptim)
Direction counter changed from Up to Down callback in non-blocking mode.
HAL_StatusTypeDef | HAL_LPTIM_RegisterCallback (LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback)
Register a User LPTIM callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_LPTIM_UnRegisterCallback (LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID)
Unregister a LPTIM callback LLPTIM callback is redirected to the weak predefined callback.
HAL_LPTIM_StateTypeDef | HAL_LPTIM_GetState (LPTIM_HandleTypeDef *hlptim)
Return the LPTIM handle state.
void | LPTIM_Disable (LPTIM_HandleTypeDef *hlptim)
Disable LPTIM HW instance.

Detailed Description

LPTIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Low Power Timer (LPTIM) peripheral: + Initialization and de-initialization functions. + Start/Stop operation functions in polling mode. + Start/Stop operation functions in interrupt mode. + Reading operation functions. + Peripheral State functions.

Author:
MCD Application Team
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
      The LPTIM HAL driver can be used as follows:

      (#)Initialize the LPTIM low level resources by implementing the
        HAL_LPTIM_MspInit():
         (++) Enable the LPTIM interface clock using __HAL_RCC_LPTIMx_CLK_ENABLE().
         (++) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):
             (+++) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().
             (+++) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().
             (+++) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().

      (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function
         configures mainly:
         (++) The instance: LPTIM1 or LPTIM2.
         (++) Clock: the counter clock.
             (+++) Source   : it can be either the ULPTIM input (IN1) or one of
                              the internal clock; (APB, LSE, LSI or MSI).
             (+++) Prescaler: select the clock divider.
         (++)  UltraLowPowerClock : To be used only if the ULPTIM is selected
               as counter clock source.
             (+++) Polarity:   polarity of the active edge for the counter unit
                               if the ULPTIM input is selected.
             (+++) SampleTime: clock sampling time to configure the clock glitch
                               filter.
         (++) Trigger: How the counter start.
             (+++) Source: trigger can be software or one of the hardware triggers.
             (+++) ActiveEdge : only for hardware trigger.
             (+++) SampleTime : trigger sampling time to configure the trigger
                                glitch filter.
         (++) OutputPolarity : 2 opposite polarities are possible.
         (++) UpdateMode: specifies whether the update of the autoreload and
              the compare values is done immediately or after the end of current
              period.
         (++) Input1Source: Source selected for input1 (GPIO or comparator output).
         (++) Input2Source: Source selected for input2 (GPIO or comparator output).
              Input2 is used only for encoder feature so is used only for LPTIM1 instance.

      (#)Six modes are available:

         (++) PWM Mode: To generate a PWM signal with specified period and pulse,
         call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption
         mode.

         (++) One Pulse Mode: To generate pulse with specified width in response
         to a stimulus, call HAL_LPTIM_OnePulse_Start() or
         HAL_LPTIM_OnePulse_Start_IT() for interruption mode.

         (++) Set once Mode: In this mode, the output changes the level (from
         low level to high level if the output polarity is configured high, else
         the opposite) when a compare match occurs. To start this mode, call
         HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for
         interruption mode.

         (++) Encoder Mode: To use the encoder interface call
         HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for
         interruption mode. Only available for LPTIM1 instance.

         (++) Time out Mode: an active edge on one selected trigger input rests
         the counter. The first trigger event will start the timer, any
         successive trigger event will reset the counter and the timer will
         restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or
         HAL_LPTIM_TimeOut_Start_IT() for interruption mode.

         (++) Counter Mode: counter can be used to count external events on
         the LPTIM Input1 or it can be used to count internal clock cycles.
         To start this mode, call HAL_LPTIM_Counter_Start() or
         HAL_LPTIM_Counter_Start_IT() for interruption mode.

      (#) User can stop any process by calling the corresponding API:
          HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is
          already started in interruption mode.

      (#) De-initialize the LPTIM peripheral using HAL_LPTIM_DeInit().

    *** Callback registration ***
  =============================================
  [..]
  The compilation define  USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1
  allows the user to configure dynamically the driver callbacks.
  [..]
  Use Function @ref HAL_LPTIM_RegisterCallback() to register a callback.
  @ref HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle,
  the Callback ID and a pointer to the user callback function.
  [..]
  Use function @ref HAL_LPTIM_UnRegisterCallback() to reset a callback to the
  default weak function.
  @ref HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
  and the Callback ID.
  [..]
  These functions allow to register/unregister following callbacks:

    (+) MspInitCallback         : LPTIM Base Msp Init Callback.
    (+) MspDeInitCallback       : LPTIM Base Msp DeInit Callback.
    (+) CompareMatchCallback    : Compare match Callback.
    (+) AutoReloadMatchCallback : Auto-reload match Callback.
    (+) TriggerCallback         : External trigger event detection Callback.
    (+) CompareWriteCallback    : Compare register write complete Callback.
    (+) AutoReloadWriteCallback : Auto-reload register write complete Callback.
    (+) DirectionUpCallback     : Up-counting direction change Callback.
    (+) DirectionDownCallback   : Down-counting direction change Callback.

  [..]
  By default, after the Init and when the state is HAL_LPTIM_STATE_RESET
  all interrupt callbacks are set to the corresponding weak functions:
  examples @ref HAL_LPTIM_TriggerCallback(), @ref HAL_LPTIM_CompareMatchCallback().

  [..]
  Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
  functionalities in the Init/DeInit only when these callbacks are null
  (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init/DeInit
  keep and use the user MspInit/MspDeInit callbacks (registered beforehand)

  [..]
  Callbacks can be registered/unregistered in HAL_LPTIM_STATE_READY state only.
  Exception done MspInit/MspDeInit that can be registered/unregistered
  in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state,
  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
  In that case first register the MspInit/MspDeInit user callbacks
  using @ref HAL_LPTIM_RegisterCallback() before calling DeInit or Init function.

  [..]
  When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or
  not defined, the callback registration feature is not available and all callbacks
  are set to the corresponding weak functions.
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_lptim.c.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_pcd.c File Reference

  • File List
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  • STM32WBxx_HAL_Driver
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Defines | Functions
stm32wbxx_hal_pcd.c File Reference

PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Defines

#define | PCD_MIN(a, b) (((a) < (b)) ? (a) : (b))
#define | PCD_MAX(a, b) (((a) > (b)) ? (a) : (b))

Functions

static HAL_StatusTypeDef | PCD_EP_ISR_Handler (PCD_HandleTypeDef *hpcd)
This function handles PCD Endpoint interrupt request.
HAL_StatusTypeDef | HAL_PCD_Init (PCD_HandleTypeDef *hpcd)
Initializes the PCD according to the specified parameters in the PCD_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd)
DeInitializes the PCD peripheral.
__weak void | HAL_PCD_MspInit (PCD_HandleTypeDef *hpcd)
Initializes the PCD MSP.
__weak void | HAL_PCD_MspDeInit (PCD_HandleTypeDef *hpcd)
DeInitializes PCD MSP.
HAL_StatusTypeDef | HAL_PCD_RegisterCallback (PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback)
Register a User USB PCD Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterCallback (PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID)
Unregister an USB PCD Callback USB PCD callabck is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterDataOutStageCallback (PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback)
Register USB PCD Data OUT Stage Callback To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterDataOutStageCallback (PCD_HandleTypeDef *hpcd)
UnRegister the USB PCD Data OUT Stage Callback USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterDataInStageCallback (PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback)
Register USB PCD Data IN Stage Callback To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterDataInStageCallback (PCD_HandleTypeDef *hpcd)
UnRegister the USB PCD Data IN Stage Callback USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterIsoOutIncpltCallback (PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback)
Register USB PCD Iso OUT incomplete Callback To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterIsoOutIncpltCallback (PCD_HandleTypeDef *hpcd)
UnRegister the USB PCD Iso OUT incomplete Callback USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterIsoInIncpltCallback (PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback)
Register USB PCD Iso IN incomplete Callback To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterIsoInIncpltCallback (PCD_HandleTypeDef *hpcd)
UnRegister the USB PCD Iso IN incomplete Callback USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterBcdCallback (PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback)
Register USB PCD BCD Callback To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterBcdCallback (PCD_HandleTypeDef *hpcd)
UnRegister the USB PCD BCD Callback USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_RegisterLpmCallback (PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback)
Register USB PCD LPM Callback To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_UnRegisterLpmCallback (PCD_HandleTypeDef *hpcd)
UnRegister the USB PCD LPM Callback USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback.
HAL_StatusTypeDef | HAL_PCD_Start (PCD_HandleTypeDef *hpcd)
Start the USB device.
HAL_StatusTypeDef | HAL_PCD_Stop (PCD_HandleTypeDef *hpcd)
Stop the USB device.
void | HAL_PCD_IRQHandler (PCD_HandleTypeDef *hpcd)
This function handles PCD interrupt request.
__weak void | HAL_PCD_DataOutStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data OUT stage callback.
__weak void | HAL_PCD_DataInStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data IN stage callback.
__weak void | HAL_PCD_SetupStageCallback (PCD_HandleTypeDef *hpcd)
Setup stage callback.
__weak void | HAL_PCD_SOFCallback (PCD_HandleTypeDef *hpcd)
USB Start Of Frame callback.
__weak void | HAL_PCD_ResetCallback (PCD_HandleTypeDef *hpcd)
USB Reset callback.
__weak void | HAL_PCD_SuspendCallback (PCD_HandleTypeDef *hpcd)
Suspend event callback.
__weak void | HAL_PCD_ResumeCallback (PCD_HandleTypeDef *hpcd)
Resume event callback.
__weak void | HAL_PCD_ISOOUTIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO OUT callback.
__weak void | HAL_PCD_ISOINIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO IN callback.
__weak void | HAL_PCD_ConnectCallback (PCD_HandleTypeDef *hpcd)
Connection event callback.
__weak void | HAL_PCD_DisconnectCallback (PCD_HandleTypeDef *hpcd)
Disconnection event callback.
HAL_StatusTypeDef | HAL_PCD_DevConnect (PCD_HandleTypeDef *hpcd)
Connect the USB device.
HAL_StatusTypeDef | HAL_PCD_DevDisconnect (PCD_HandleTypeDef *hpcd)
Disconnect the USB device.
HAL_StatusTypeDef | HAL_PCD_SetAddress (PCD_HandleTypeDef *hpcd, uint8_t address)
Set the USB Device address.
HAL_StatusTypeDef | HAL_PCD_EP_Open (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
Open and configure an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Close (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Deactivate an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Receive (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Receive an amount of data.
uint32_t | HAL_PCD_EP_GetRxCount (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Get Received Data Size.
HAL_StatusTypeDef | HAL_PCD_EP_Transmit (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Send an amount of data.
HAL_StatusTypeDef | HAL_PCD_EP_SetStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Set a STALL condition over an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_ClrStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Clear a STALL condition over in an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Flush (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Flush an endpoint.
HAL_StatusTypeDef | HAL_PCD_ActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
Activate remote wakeup signalling.
HAL_StatusTypeDef | HAL_PCD_DeActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
De-activate remote wakeup signalling.
PCD_StateTypeDef | HAL_PCD_GetState (PCD_HandleTypeDef *hpcd)
Return the PCD handle state.

Detailed Description

PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
  ==============================================================================
                    ##### How to use this driver #####
  ==============================================================================
    [..]
      The PCD HAL driver can be used as follows:

     (#) Declare a PCD_HandleTypeDef handle structure, for example:
         PCD_HandleTypeDef  hpcd;

     (#) Fill parameters of Init structure in HCD handle

     (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...)

     (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
         (##) Enable the PCD/USB Low Level interface clock using
              (+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device only FS peripheral

         (##) Initialize the related GPIO clocks
         (##) Configure PCD pin-out
         (##) Configure PCD NVIC interrupt

     (#)Associate the Upper USB device stack to the HAL PCD Driver:
         (##) hpcd.pData = pdev;

     (#)Enable PCD transmission and reception:
         (##) HAL_PCD_Start();
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_pcd.c.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_pcd_ex.c File Reference

  • File List
  • Globals
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  • STM32WBxx_HAL_Driver
  • Src
Functions
stm32wbxx_hal_pcd_ex.c File Reference

PCD Extended HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Extended features functions. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_PCDEx_PMAConfig (PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pmaadress)
Configure PMA for EP.
HAL_StatusTypeDef | HAL_PCDEx_ActivateBCD (PCD_HandleTypeDef *hpcd)
Activate BatteryCharging feature.
HAL_StatusTypeDef | HAL_PCDEx_DeActivateBCD (PCD_HandleTypeDef *hpcd)
Deactivate BatteryCharging feature.
void | HAL_PCDEx_BCD_VBUSDetect (PCD_HandleTypeDef *hpcd)
Handle BatteryCharging Process.
HAL_StatusTypeDef | HAL_PCDEx_ActivateLPM (PCD_HandleTypeDef *hpcd)
Activate LPM feature.
HAL_StatusTypeDef | HAL_PCDEx_DeActivateLPM (PCD_HandleTypeDef *hpcd)
Deactivate LPM feature.
__weak void | HAL_PCDEx_LPM_Callback (PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
Send LPM message to user layer callback.
__weak void | HAL_PCDEx_BCD_Callback (PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
Send BatteryCharging message to user layer callback.

Detailed Description

PCD Extended HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Extended features functions.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_pcd_ex.c.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_pka.c File Reference

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stm32wbxx_hal_pka.c File Reference

PKA HAL module driver. This file provides firmware functions to manage the following functionalities of public key accelerator(PKA): + Initialization and de-initialization functions + Start an operation + Retrieve the operation result. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Defines

#define | PKA_RAM_SIZE 894U

Functions

uint32_t | PKA_GetMode (PKA_HandleTypeDef *hpka)
Get PKA operating mode.
HAL_StatusTypeDef | PKA_PollEndOfOperation (PKA_HandleTypeDef *hpka, uint32_t Timeout, uint32_t Tickstart)
Wait for operation completion or timeout.
uint32_t | PKA_CheckError (PKA_HandleTypeDef *hpka, uint32_t mode)
Return a hal error code based on PKA error flags.
uint32_t | PKA_GetBitSize_u8 (uint32_t byteNumber)
Get number of bits inside an array of u8.
uint32_t | PKA_GetOptBitSize_u8 (uint32_t byteNumber, uint8_t msb)
Get optimal number of bits inside an array of u8.
uint32_t | PKA_GetBitSize_u32 (uint32_t wordNumber)
Get number of bits inside an array of u32.
uint32_t | PKA_GetArraySize_u8 (uint32_t bitSize)
Get number of uint8_t element in an array of bitSize bits.
void | PKA_Memcpy_u32_to_u8 (uint8_t dst[], __IO const uint32_t src[], size_t n)
Copy uint32_t array to uint8_t array to fit PKA number representation.
void | PKA_Memcpy_u8_to_u32 (__IO uint32_t dst[], const uint8_t src[], size_t n)
Copy uint8_t array to uint32_t array to fit PKA number representation.
void | PKA_Memcpy_u32_to_u32 (__IO uint32_t dst[], __IO const uint32_t src[], size_t n)
Copy uint32_t array to uint32_t array.
HAL_StatusTypeDef | PKA_Process (PKA_HandleTypeDef *hpka, uint32_t mode, uint32_t Timeout)
Generic function to start a PKA operation in blocking mode.
HAL_StatusTypeDef | PKA_Process_IT (PKA_HandleTypeDef *hpka, uint32_t mode)
Generic function to start a PKA operation in non-blocking mode with Interrupt.
void | PKA_ModExp_Set (PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in)
Set input parameters.
void | PKA_ModExpFastMode_Set (PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in)
Set input parameters.
void | PKA_ECDSASign_Set (PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in)
Set input parameters.
void | PKA_ECDSAVerif_Set (PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in)
Set input parameters.
void | PKA_RSACRTExp_Set (PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in)
Set input parameters.
void | PKA_PointCheck_Set (PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in)
Set input parameters.
void | PKA_ECCMul_Set (PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in)
Set input parameters.
void | PKA_ECCMulFastMode_Set (PKA_HandleTypeDef *hpka, PKA_ECCMulFastModeInTypeDef *in)
Set input parameters.
void | PKA_ModRed_Set (PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in)
Set input parameters.
void | PKA_ModInv_Set (PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in)
Set input parameters.
void | PKA_MontgomeryParam_Set (PKA_HandleTypeDef *hpka, const uint32_t size, const uint8_t *pOp1)
Set input parameters.
void | PKA_ARI_Set (PKA_HandleTypeDef *hpka, const uint32_t size, const uint32_t *pOp1, const uint32_t *pOp2, const uint8_t *pOp3)
Generic function to set input parameters.
HAL_StatusTypeDef | HAL_PKA_Init (PKA_HandleTypeDef *hpka)
Initialize the PKA according to the specified parameters in the PKA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_PKA_DeInit (PKA_HandleTypeDef *hpka)
DeInitialize the PKA peripheral.
__weak void | HAL_PKA_MspInit (PKA_HandleTypeDef *hpka)
Initialize the PKA MSP.
__weak void | HAL_PKA_MspDeInit (PKA_HandleTypeDef *hpka)
DeInitialize the PKA MSP.
HAL_StatusTypeDef | HAL_PKA_RegisterCallback (PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID, pPKA_CallbackTypeDef pCallback)
Register a User PKA Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_PKA_UnRegisterCallback (PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID)
Unregister a PKA Callback PKA callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_PKA_ModExp (PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in, uint32_t Timeout)
Modular exponentiation in blocking mode.
HAL_StatusTypeDef | HAL_PKA_ModExp_IT (PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in)
Modular exponentiation in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_PKA_ModExpFastMode (PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in, uint32_t Timeout)
Modular exponentiation in blocking mode.
HAL_StatusTypeDef | HAL_PKA_ModExpFastMode_IT (PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in)
Modular exponentiation in non-blocking mode with Interrupt.
void | HAL_PKA_ModExp_GetResult (PKA_HandleTypeDef *hpka, uint8_t *pRes)
Retrieve operation result.
HAL_StatusTypeDef | HAL_PKA_ECDSASign (PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in, uint32_t Timeout)
Sign a message using elliptic curves over prime fields in blocking mode.
HAL_StatusTypeDef | HAL_PKA_ECDSASign_IT (PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in)
Sign a message using elliptic curves over prime fields in non-blocking mode with Interrupt.
void | HAL_PKA_ECDSASign_GetResult (PKA_HandleTypeDef *hpka, PKA_ECDSASignOutTypeDef *out, PKA_ECDSASignOutExtParamTypeDef *outExt)
Retrieve operation result.
HAL_StatusTypeDef | HAL_PKA_ECDSAVerif (PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in, uint32_t Timeout)
Verify the validity of a signature using elliptic curves over prime fields in blocking mode.
HAL_StatusTypeDef | HAL_PKA_ECDSAVerif_IT (PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in)
Verify the validity of a signature using elliptic curves over prime fields in non-blocking mode with Interrupt.
uint32_t | HAL_PKA_ECDSAVerif_IsValidSignature (PKA_HandleTypeDef const *const hpka)
Return the result of the ECDSA verification operation.
HAL_StatusTypeDef | HAL_PKA_RSACRTExp (PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in, uint32_t Timeout)
RSA CRT exponentiation in blocking mode.
HAL_StatusTypeDef | HAL_PKA_RSACRTExp_IT (PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in)
RSA CRT exponentiation in non-blocking mode with Interrupt.
void | HAL_PKA_RSACRTExp_GetResult (PKA_HandleTypeDef *hpka, uint8_t *pRes)
Retrieve operation result.
HAL_StatusTypeDef | HAL_PKA_PointCheck (PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in, uint32_t Timeout)
Point on elliptic curve check in blocking mode.
HAL_StatusTypeDef | HAL_PKA_PointCheck_IT (PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in)
Point on elliptic curve check in non-blocking mode with Interrupt.
uint32_t | HAL_PKA_PointCheck_IsOnCurve (PKA_HandleTypeDef const *const hpka)
Return the result of the point check operation.
HAL_StatusTypeDef | HAL_PKA_ECCMul (PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in, uint32_t Timeout)
ECC scalar multiplication in blocking mode.
HAL_StatusTypeDef | HAL_PKA_ECCMul_IT (PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in)
ECC scalar multiplication in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_PKA_ECCMulFastMode (PKA_HandleTypeDef *hpka, PKA_ECCMulFastModeInTypeDef *in, uint32_t Timeout)
ECC scalar multiplication in blocking mode.
HAL_StatusTypeDef | HAL_PKA_ECCMulFastMode_IT (PKA_HandleTypeDef *hpka, PKA_ECCMulFastModeInTypeDef *in)
ECC scalar multiplication in non-blocking mode with Interrupt.
void | HAL_PKA_ECCMul_GetResult (PKA_HandleTypeDef *hpka, PKA_ECCMulOutTypeDef *out)
Retrieve operation result.
HAL_StatusTypeDef | HAL_PKA_Add (PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in, uint32_t Timeout)
Arithmetic addition in blocking mode.
HAL_StatusTypeDef | HAL_PKA_Add_IT (PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in)
Arithmetic addition in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_PKA_Sub (PKA_HandleTypeDef *hpka, PKA_SubInTypeDef *in, uint32_t Timeout)
Arithmetic substraction in blocking mode.
HAL_StatusTypeDef | HAL_PKA_Sub_IT (PKA_HandleTypeDef *hpka, PKA_SubInTypeDef *in)
Arithmetic substraction in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_PKA_Mul (PKA_HandleTypeDef *hpka, PKA_MulInTypeDef *in, uint32_t Timeout)
Arithmetic multiplication in blocking mode.
HAL_StatusTypeDef | HAL_PKA_Mul_IT (PKA_HandleTypeDef *hpka, PKA_MulInTypeDef *in)
Arithmetic multiplication in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_PKA_Cmp (PKA_HandleTypeDef *hpka, PKA_CmpInTypeDef *in, uint32_t Timeout)
Comparison in blocking mode.
HAL_StatusTypeDef | HAL_PKA_Cmp_IT (PKA_HandleTypeDef *hpka, PKA_CmpInTypeDef *in)
Comparison in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_PKA_ModAdd (PKA_HandleTypeDef *hpka, PKA_ModAddInTypeDef *in, uint32_t Timeout)
Modular addition in blocking mode.
HAL_StatusTypeDef | HAL_PKA_ModAdd_IT (PKA_HandleTypeDef *hpka, PKA_ModAddInTypeDef *in)
Modular addition in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_PKA_ModInv (PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in, uint32_t Timeout)
Modular inversion in blocking mode.
HAL_StatusTypeDef | HAL_PKA_ModInv_IT (PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in)
Modular inversion in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_PKA_ModSub (PKA_HandleTypeDef *hpka, PKA_ModSubInTypeDef *in, uint32_t Timeout)
Modular substraction in blocking mode.
HAL_StatusTypeDef | HAL_PKA_ModSub_IT (PKA_HandleTypeDef *hpka, PKA_ModSubInTypeDef *in)
Modular substraction in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_PKA_ModRed (PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in, uint32_t Timeout)
Modular reduction in blocking mode.
HAL_StatusTypeDef | HAL_PKA_ModRed_IT (PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in)
Modular reduction in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_PKA_MontgomeryMul (PKA_HandleTypeDef *hpka, PKA_MontgomeryMulInTypeDef *in, uint32_t Timeout)
Montgomery multiplication in blocking mode.
HAL_StatusTypeDef | HAL_PKA_MontgomeryMul_IT (PKA_HandleTypeDef *hpka, PKA_MontgomeryMulInTypeDef *in)
Montgomery multiplication in non-blocking mode with Interrupt.
void | HAL_PKA_Arithmetic_GetResult (PKA_HandleTypeDef *hpka, uint32_t *pRes)
Retrieve operation result.
HAL_StatusTypeDef | HAL_PKA_MontgomeryParam (PKA_HandleTypeDef *hpka, PKA_MontgomeryParamInTypeDef *in, uint32_t Timeout)
Montgomery parameter computation in blocking mode.
HAL_StatusTypeDef | HAL_PKA_MontgomeryParam_IT (PKA_HandleTypeDef *hpka, PKA_MontgomeryParamInTypeDef *in)
Montgomery parameter computation in non-blocking mode with Interrupt.
void | HAL_PKA_MontgomeryParam_GetResult (PKA_HandleTypeDef *hpka, uint32_t *pRes)
Retrieve operation result.
HAL_StatusTypeDef | HAL_PKA_Abort (PKA_HandleTypeDef *hpka)
Abort any ongoing operation.
void | HAL_PKA_RAMReset (PKA_HandleTypeDef *hpka)
Reset the PKA RAM.
void | HAL_PKA_IRQHandler (PKA_HandleTypeDef *hpka)
This function handles PKA event interrupt request.
__weak void | HAL_PKA_OperationCpltCallback (PKA_HandleTypeDef *hpka)
Process completed callback.
__weak void | HAL_PKA_ErrorCallback (PKA_HandleTypeDef *hpka)
Error callback.
HAL_PKA_StateTypeDef | HAL_PKA_GetState (PKA_HandleTypeDef *hpka)
Return the PKA handle state.
uint32_t | HAL_PKA_GetError (PKA_HandleTypeDef *hpka)
Return the PKA error code.

Detailed Description

PKA HAL module driver. This file provides firmware functions to manage the following functionalities of public key accelerator(PKA): + Initialization and de-initialization functions + Start an operation + Retrieve the operation result.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
    The PKA HAL driver can be used as follows:

    (#) Declare a PKA_HandleTypeDef handle structure, for example: PKA_HandleTypeDef  hpka;

    (#) Initialize the PKA low level resources by implementing the HAL_PKA_MspInit() API:
        (##) Enable the PKA interface clock
        (##) NVIC configuration if you need to use interrupt process
            (+++) Configure the PKA interrupt priority
            (+++) Enable the NVIC PKA IRQ Channel

    (#) Initialize the PKA registers by calling the HAL_PKA_Init() API which trig
        HAL_PKA_MspInit().

    (#) Fill entirely the input structure corresponding to your operation:
        For instance: PKA_ModExpInTypeDef for HAL_PKA_ModExp().

    (#) Execute the operation (in polling or interrupt) and check the returned value.

    (#) Retrieve the result of the operation (For instance, HAL_PKA_ModExp_GetResult for
        HAL_PKA_ModExp operation). The function to gather the result is different for each
        kind of operation. The correspondence can be found in the following section.

    (#) Call the function HAL_PKA_DeInit() to restore the default configuration which trig
        HAL_PKA_MspDeInit().

    *** High level operation ***
    =================================
    [..]
      (+) Input structure requires buffers as uint8_t array.

      (+) Output structure requires buffers as uint8_t array.

      (+) Modular exponentiation using:
      (++) HAL_PKA_ModExp().
      (++) HAL_PKA_ModExp_IT().
      (++) HAL_PKA_ModExpFastMode().
      (++) HAL_PKA_ModExpFastMode_IT().
      (++) HAL_PKA_ModExp_GetResult() to retrieve the result of the operation.

      (+) RSA Chinese Remainder Theorem (CRT) using:
      (++) HAL_PKA_RSACRTExp().
      (++) HAL_PKA_RSACRTExp_IT().
      (++) HAL_PKA_RSACRTExp_GetResult() to retrieve the result of the operation.

      (+) ECC Point Check using:
      (++) HAL_PKA_PointCheck().
      (++) HAL_PKA_PointCheck_IT().
      (++) HAL_PKA_PointCheck_IsOnCurve() to retrieve the result of the operation.

      (+) ECDSA Sign
      (++) HAL_PKA_ECDSASign().
      (++) HAL_PKA_ECDSASign_IT().
      (++) HAL_PKA_ECDSASign_GetResult() to retrieve the result of the operation.

      (+) ECDSA Verify
      (++) HAL_PKA_ECDSAVerif().
      (++) HAL_PKA_ECDSAVerif_IT().
      (++) HAL_PKA_ECDSAVerif_IsValidSignature() to retrieve the result of the operation.

      (+) ECC Scalar Multiplication using:
      (++) HAL_PKA_ECCMul().
      (++) HAL_PKA_ECCMul_IT().
      (++) HAL_PKA_ECCMulFastMode().
      (++) HAL_PKA_ECCMulFastMode_IT().
      (++) HAL_PKA_ECCMul_GetResult() to retrieve the result of the operation.

    *** Low level operation ***
    =================================
    [..]
      (+) Input structure requires buffers as uint32_t array.

      (+) Output structure requires buffers as uint32_t array.

      (+) Arithmetic addition using:
      (++) HAL_PKA_Add().
      (++) HAL_PKA_Add_IT().
      (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
            The resulting size can be the input parameter or the input parameter size + 1 (overflow).

      (+) Arithmetic substraction using:
      (++) HAL_PKA_Sub().
      (++) HAL_PKA_Sub_IT().
      (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.

      (+) Arithmetic multiplication using:
      (++) HAL_PKA_Mul().
      (++) HAL_PKA_Mul_IT().
      (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.

      (+) Comparison using:
      (++) HAL_PKA_Cmp().
      (++) HAL_PKA_Cmp_IT().
      (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.

      (+) Modular addition using:
      (++) HAL_PKA_ModAdd().
      (++) HAL_PKA_ModAdd_IT().
      (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.

      (+) Modular substraction using:
      (++) HAL_PKA_ModSub().
      (++) HAL_PKA_ModSub_IT().
      (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.

      (+) Modular inversion using:
      (++) HAL_PKA_ModInv().
      (++) HAL_PKA_ModInv_IT().
      (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.

      (+) Modular reduction using:
      (++) HAL_PKA_ModRed().
      (++) HAL_PKA_ModRed_IT().
      (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.

      (+) Montgomery multiplication using:
      (++) HAL_PKA_MontgomeryMul().
      (++) HAL_PKA_MontgomeryMul_IT().
      (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.

    *** Montgomery parameter ***
    =================================
      (+) For some operation, the computation of the Montgomery parameter is a prerequisite.
      (+) Input structure requires buffers as uint8_t array.
      (+) Output structure requires buffers as uint32_t array.(Only used inside PKA).
      (+) You can compute the Montgomery parameter using:
      (++) HAL_PKA_MontgomeryParam().
      (++) HAL_PKA_MontgomeryParam_IT().
      (++) HAL_PKA_MontgomeryParam_GetResult() to retrieve the result of the operation.
      (+) You can save computation time by storing this parameter for a later usage.
          Use it again with HAL_PKA_MontgomeryParam_Set();

    *** Polling mode operation ***
    ===================================
    [..]
      (+) When an operation is started in polling mode, the function returns when:
      (++) A timeout is encounter.
      (++) The operation is completed.

    *** Interrupt mode operation ***
    ===================================
    [..]
      (+) Add HAL_PKA_IRQHandler to the IRQHandler of PKA.
      (+) Enable the IRQ using HAL_NVIC_EnableIRQ().
      (+) When an operation is started in interrupt mode, the function returns immediatly.
      (+) When the operation is completed, the callback HAL_PKA_OperationCpltCallback is called.
      (+) When an error is encountered, the callback HAL_PKA_ErrorCallback is called.
      (+) To stop any operation in interrupt mode, use HAL_PKA_Abort().

    *** Utilities ***
    ===================================
    [..]
      (+) To clear the PKA RAM, use HAL_PKA_RAMReset().
      (+) To get current state, use HAL_PKA_GetState().
      (+) To get current error, use HAL_PKA_GetError().

    *** Callback registration ***
    =============================================
    [..]

     The compilation flag USE_HAL_PKA_REGISTER_CALLBACKS, when set to 1,
     allows the user to configure dynamically the driver callbacks.
     Use Functions @ref HAL_PKA_RegisterCallback()
     to register an interrupt callback.
    [..]

     Function @ref HAL_PKA_RegisterCallback() allows to register following callbacks:
       (+) OperationCpltCallback : callback for End of operation.
       (+) ErrorCallback         : callback for error detection.
       (+) MspInitCallback       : callback for Msp Init.
       (+) MspDeInitCallback     : callback for Msp DeInit.
     This function takes as parameters the HAL peripheral handle, the Callback ID
     and a pointer to the user callback function.
    [..]

     Use function @ref HAL_PKA_UnRegisterCallback to reset a callback to the default
     weak function.
    [..]

     @ref HAL_PKA_UnRegisterCallback takes as parameters the HAL peripheral handle,
     and the Callback ID.
     This function allows to reset following callbacks:
       (+) OperationCpltCallback : callback for End of operation.
       (+) ErrorCallback         : callback for error detection.
       (+) MspInitCallback       : callback for Msp Init.
       (+) MspDeInitCallback     : callback for Msp DeInit.
     [..]

     By default, after the @ref HAL_PKA_Init() and when the state is @ref HAL_PKA_STATE_RESET
     all callbacks are set to the corresponding weak functions:
     examples @ref HAL_PKA_OperationCpltCallback(), @ref HAL_PKA_ErrorCallback().
     Exception done for MspInit and MspDeInit functions that are
     reset to the legacy weak functions in the @ref HAL_PKA_Init()/ @ref HAL_PKA_DeInit() only when
     these callbacks are null (not registered beforehand).
    [..]

     If MspInit or MspDeInit are not null, the @ref HAL_PKA_Init()/ @ref HAL_PKA_DeInit()
     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
     [..]

     Callbacks can be registered/unregistered in @ref HAL_PKA_STATE_READY state only.
     Exception done MspInit/MspDeInit functions that can be registered/unregistered
     in @ref HAL_PKA_STATE_READY or @ref HAL_PKA_STATE_RESET state,
     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
    [..]

     Then, the user first registers the MspInit/MspDeInit user callbacks
     using @ref HAL_PKA_RegisterCallback() before calling @ref HAL_PKA_DeInit()
     or @ref HAL_PKA_Init() function.
     [..]

     When the compilation flag USE_HAL_PKA_REGISTER_CALLBACKS is set to 0 or
     not defined, the callback registration feature is not available and all callbacks
     are set to the corresponding weak functions.
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_pka.c.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_pwr.c File Reference

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Defines | Functions
stm32wbxx_hal_pwr.c File Reference

PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Initialization/de-initialization functions + Peripheral Control functions. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Defines

#define | PWR_CR1_RESET_VALUE (0x00000200U)
#define | PWR_CR2_RESET_VALUE (0x00000000U)
#define | PWR_CR3_RESET_VALUE (0x00008000U)
#define | PWR_CR4_RESET_VALUE (0x00000000U)
#define | PWR_CR5_RESET_VALUE (0x00004204U)
#define | PWR_PUCRA_RESET_VALUE (0x00000000U)
#define | PWR_PDCRA_RESET_VALUE (0x00000000U)
#define | PWR_PUCRB_RESET_VALUE (0x00000000U)
#define | PWR_PDCRB_RESET_VALUE (0x00000000U)
#define | PWR_PUCRC_RESET_VALUE (0x00000000U)
#define | PWR_PDCRC_RESET_VALUE (0x00000000U)
#define | PWR_PUCRD_RESET_VALUE (0x00000000U)
#define | PWR_PDCRD_RESET_VALUE (0x00000000U)
#define | PWR_PUCRE_RESET_VALUE (0x00000000U)
#define | PWR_PDCRE_RESET_VALUE (0x00000000U)
#define | PWR_PUCRH_RESET_VALUE (0x00000000U)
#define | PWR_PDCRH_RESET_VALUE (0x00000000U)
#define | PWR_C2CR1_RESET_VALUE (0x00000000U)
#define | PWR_C2CR3_RESET_VALUE (0x00008000U)

Functions

void | HAL_PWR_DeInit (void)
Deinitialize the HAL PWR peripheral registers to their default reset values.
void | HAL_PWR_EnableBkUpAccess (void)
Enable access to the backup domain (RTC registers, RTC backup data registers).
void | HAL_PWR_DisableBkUpAccess (void)
Disable access to the backup domain (RTC registers, RTC backup data registers).
HAL_StatusTypeDef | HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
Configure the voltage threshold detected by the Power Voltage Detector (PVD).
void | HAL_PWR_EnablePVD (void)
Enables the Power Voltage Detector(PVD).
void | HAL_PWR_DisablePVD (void)
Disables the Power Voltage Detector(PVD).
void | HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity)
Enable the WakeUp PINx functionality.
void | HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
Disable the WakeUp PINx functionality.
void | HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
Enter Sleep or Low-power Sleep mode.
void | HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
Enter Stop mode.
void | HAL_PWR_EnterSTANDBYMode (void)
Enter Standby mode.
void | HAL_PWR_EnableSleepOnExit (void)
Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.
void | HAL_PWR_DisableSleepOnExit (void)
Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
void | HAL_PWR_EnableSEVOnPend (void)
Enable CORTEX M4 SEVONPEND bit.
void | HAL_PWR_DisableSEVOnPend (void)
Disable CORTEX M4 SEVONPEND bit.
__weak void | HAL_PWR_PVDCallback (void)
PWR PVD interrupt callback.

Detailed Description

PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Initialization/de-initialization functions + Peripheral Control functions.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_pwr.c.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_pwr_ex.c File Reference

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stm32wbxx_hal_pwr_ex.c File Reference

Extended PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Extended Initialization and de-initialization functions + Extended Peripheral Control functions. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Defines

#define | PWR_PORTE_AVAILABLE_PINS (PWR_GPIO_BIT_4 | PWR_GPIO_BIT_3 | PWR_GPIO_BIT_2 | PWR_GPIO_BIT_1 | PWR_GPIO_BIT_0)
#define | PWR_PORTH_AVAILABLE_PINS (PWR_GPIO_BIT_3 | PWR_GPIO_BIT_1 | PWR_GPIO_BIT_0)
#define | PWR_FLAG_SETTING_DELAY_US 50U

Functions

uint32_t | HAL_PWREx_GetVoltageRange (void)
Return Voltage Scaling Range.
HAL_StatusTypeDef | HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling)
Configure the main internal regulator output voltage.
void | HAL_PWREx_EnableBatteryCharging (uint32_t ResistorSelection)
Enable battery charging.
void | HAL_PWREx_DisableBatteryCharging (void)
Disable battery charging.
void | HAL_PWREx_EnableVddUSB (void)
Enable VDDUSB supply.
void | HAL_PWREx_DisableVddUSB (void)
Disable VDDUSB supply.
void | HAL_PWREx_EnableInternalWakeUpLine (void)
Enable Internal Wake-up Line.
void | HAL_PWREx_DisableInternalWakeUpLine (void)
Disable Internal Wake-up Line.
void | HAL_PWREx_EnableBORH_SMPSBypassIT (void)
Enable BORH and SMPS step down converter forced in bypass mode interrupt for CPU1.
void | HAL_PWREx_DisableBORH_SMPSBypassIT (void)
Disable BORH and SMPS step down converter forced in bypass mode interrupt for CPU1.
void | HAL_PWREx_EnableRFPhaseIT (void)
Enable RF Phase interrupt.
void | HAL_PWREx_DisableRFPhaseIT (void)
Disable RF Phase interrupt.
void | HAL_PWREx_EnableBLEActivityIT (void)
Enable BLE Activity interrupt.
void | HAL_PWREx_DisableBLEActivityIT (void)
Disable BLE Activity interrupt.
void | HAL_PWREx_Enable802ActivityIT (void)
Enable 802.15.4 Activity interrupt.
void | HAL_PWREx_Disable802ActivityIT (void)
Disable 802.15.4 Activity interrupt.
void | HAL_PWREx_EnableHOLDC2IT (void)
Enable CPU2 on-Hold interrupt.
void | HAL_PWREx_DisableHOLDC2IT (void)
Disable CPU2 on-Hold interrupt.
HAL_StatusTypeDef | HAL_PWREx_EnableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-up state in Standby and Shutdown modes.
HAL_StatusTypeDef | HAL_PWREx_DisableGPIOPullUp (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-up state in Standby mode and Shutdown modes.
HAL_StatusTypeDef | HAL_PWREx_EnableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Enable GPIO pull-down state in Standby and Shutdown modes.
HAL_StatusTypeDef | HAL_PWREx_DisableGPIOPullDown (uint32_t GPIO, uint32_t GPIONumber)
Disable GPIO pull-down state in Standby and Shutdown modes.
void | HAL_PWREx_EnablePullUpPullDownConfig (void)
Enable pull-up and pull-down configuration.
void | HAL_PWREx_DisablePullUpPullDownConfig (void)
Disable pull-up and pull-down configuration.
void | HAL_PWREx_SetBORConfig (uint32_t BORConfiguration)
Set BOR configuration.
uint32_t | HAL_PWREx_GetBORConfig (void)
Get BOR configuration.
void | HAL_PWREx_HoldCore (uint32_t CPU)
Hold the CPU and their allocated peripherals after reset or wakeup from stop or standby.
void | HAL_PWREx_ReleaseCore (uint32_t CPU)
Release Cortex CPU2 and allocated peripherals after reset or wakeup from stop or standby.
void | HAL_PWREx_EnableSRAMRetention (void)
Enable BKRAM content retention in Standby mode.
void | HAL_PWREx_DisableSRAMRetention (void)
Disable BKRAM content retention in Standby mode.
void | HAL_PWREx_EnableFlashPowerDown (uint32_t PowerMode)
Enable Flash Power Down.
void | HAL_PWREx_DisableFlashPowerDown (uint32_t PowerMode)
Disable Flash Power Down.
void | HAL_PWREx_EnablePVM1 (void)
Enable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
void | HAL_PWREx_DisablePVM1 (void)
Disable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
void | HAL_PWREx_EnablePVM3 (void)
Enable the Power Voltage Monitoring 3: VDDA versus 1.62V.
void | HAL_PWREx_DisablePVM3 (void)
Disable the Power Voltage Monitoring 3: VDDA versus 1.62V.
HAL_StatusTypeDef | HAL_PWREx_ConfigPVM (PWR_PVMTypeDef *sConfigPVM)
Configure the Peripheral Voltage Monitoring (PVM).
HAL_StatusTypeDef | HAL_PWREx_ConfigSMPS (PWR_SMPSTypeDef *sConfigSMPS)
Configure the SMPS step down converter.
void | HAL_PWREx_SMPS_SetMode (uint32_t OperatingMode)
Set SMPS operating mode.
uint32_t | HAL_PWREx_SMPS_GetEffectiveMode (void)
Get SMPS effective operating mode.
void | HAL_PWREx_EnableWakeUpPin (uint32_t WakeUpPinPolarity, uint32_t wakeupTarget)
Enable the WakeUp PINx functionality.
uint32_t | HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag)
Get the Wake-Up pin flag.
HAL_StatusTypeDef | HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag)
Clear the Wake-Up pin flag.
void | HAL_PWREx_EnableLowPowerRunMode (void)
Enter Low-power Run mode.
HAL_StatusTypeDef | HAL_PWREx_DisableLowPowerRunMode (void)
Exit Low-power Run mode.
void | HAL_PWREx_EnterSTOP0Mode (uint8_t STOPEntry)
Enter Stop 0 mode.
void | HAL_PWREx_EnterSTOP1Mode (uint8_t STOPEntry)
Enter Stop 1 mode.
void | HAL_PWREx_EnterSTOP2Mode (uint8_t STOPEntry)
Enter Stop 2 mode.
void | HAL_PWREx_EnterSHUTDOWNMode (void)
Enter Shutdown mode.
void | HAL_PWREx_PVD_PVM_IRQHandler (void)
This function handles the PWR PVD/PVMx interrupt request.
__weak void | HAL_PWREx_PVM1Callback (void)
PWR PVM1 interrupt callback.
__weak void | HAL_PWREx_PVM3Callback (void)
PWR PVM3 interrupt callback.

Detailed Description

Extended PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Extended Initialization and de-initialization functions + Extended Peripheral Control functions.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_pwr_ex.c.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_qspi.c File Reference

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Defines | Functions
stm32wbxx_hal_qspi.c File Reference

QSPI HAL module driver. This file provides firmware functions to manage the following functionalities of the QuadSPI interface (QSPI). + Initialization and de-initialization functions + Indirect functional mode management + Memory-mapped functional mode management + Auto-polling functional mode management + Interrupts and flags management + DMA channel configuration for indirect functional mode + Errors management and abort functionality. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Defines

#define | QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE 0x00000000U
#define | QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0)
#define | QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1)
#define | QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE)
#define | IS_QSPI_FUNCTIONAL_MODE(MODE)

Functions

static void | QSPI_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA QSPI receive process complete callback.
static void | QSPI_DMATxCplt (DMA_HandleTypeDef *hdma)
DMA QSPI transmit process complete callback.
static void | QSPI_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA QSPI receive process half complete callback.
static void | QSPI_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA QSPI transmit process half complete callback.
static void | QSPI_DMAError (DMA_HandleTypeDef *hdma)
DMA QSPI communication error callback.
static void | QSPI_DMAAbortCplt (DMA_HandleTypeDef *hdma)
DMA QSPI abort complete callback.
static HAL_StatusTypeDef | QSPI_WaitFlagStateUntilTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout)
Wait for a flag state until timeout.
static void | QSPI_Config (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)
Configure the communication registers.
HAL_StatusTypeDef | HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi)
Initialize the QSPI mode according to the specified parameters in the QSPI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi)
De-Initialize the QSPI peripheral.
__weak void | HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi)
Initialize the QSPI MSP.
__weak void | HAL_QSPI_MspDeInit (QSPI_HandleTypeDef *hqspi)
DeInitialize the QSPI MSP.
void | HAL_QSPI_IRQHandler (QSPI_HandleTypeDef *hqspi)
Handle QSPI interrupt request.
HAL_StatusTypeDef | HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
Set the command configuration.
HAL_StatusTypeDef | HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
Set the command configuration in interrupt mode.
HAL_StatusTypeDef | HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Send an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Receive an amount of data in non-blocking mode with interrupt.
HAL_StatusTypeDef | HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Send an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
Configure the QSPI Automatic Polling Mode in blocking mode.
HAL_StatusTypeDef | HAL_QSPI_AutoPolling_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
Configure the QSPI Automatic Polling Mode in non-blocking mode.
HAL_StatusTypeDef | HAL_QSPI_MemoryMapped (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
Configure the Memory Mapped mode.
__weak void | HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi)
Transfer Error callback.
__weak void | HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi)
Abort completed callback.
__weak void | HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi)
Command completed callback.
__weak void | HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi)
Rx Transfer completed callback.
__weak void | HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi)
Tx Transfer completed callback.
__weak void | HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi)
Rx Half Transfer completed callback.
__weak void | HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi)
Tx Half Transfer completed callback.
__weak void | HAL_QSPI_FifoThresholdCallback (QSPI_HandleTypeDef *hqspi)
FIFO Threshold callback.
__weak void | HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi)
Status Match callback.
__weak void | HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi)
Timeout callback.
HAL_StatusTypeDef | HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback)
Register a User QSPI Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId)
Unregister a User QSPI Callback QSPI Callback is redirected to the weak (surcharged) predefined callback.
HAL_QSPI_StateTypeDef | HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi)
Return the QSPI handle state.
uint32_t | HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi)
Return the QSPI error code.
HAL_StatusTypeDef | HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi)
Abort the current transmission.
HAL_StatusTypeDef | HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi)
Abort the current transmission (non-blocking function)
void | HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
Set QSPI timeout.
HAL_StatusTypeDef | HAL_QSPI_SetFifoThreshold (QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
Set QSPI Fifo threshold.
uint32_t | HAL_QSPI_GetFifoThreshold (QSPI_HandleTypeDef *hqspi)
Get QSPI Fifo threshold.

Detailed Description

QSPI HAL module driver. This file provides firmware functions to manage the following functionalities of the QuadSPI interface (QSPI). + Initialization and de-initialization functions + Indirect functional mode management + Memory-mapped functional mode management + Auto-polling functional mode management + Interrupts and flags management + DMA channel configuration for indirect functional mode + Errors management and abort functionality.

Author:
MCD Application Team
 ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
  [..]
    *** Initialization ***
    ======================
    [..]
      (#) As prerequisite, fill in the HAL_QSPI_MspInit() :
        (++) Enable QuadSPI clock interface with __HAL_RCC_QUADSPI_CLK_ENABLE().
        (++) Reset QuadSPI Peripheral with __HAL_RCC_QUADSPI_FORCE_RESET() and __HAL_RCC_QUADSPI_RELEASE_RESET().
        (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
        (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
        (++) If interrupt mode is used, enable and configure QuadSPI global
            interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
        (++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
            with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
            link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
            DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
      (#) Configure the flash size, the clock prescaler, the fifo threshold, the
          clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.

    *** Indirect functional mode ***
    ================================
    [..]
      (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
          functions :
         (++) Instruction phase : the mode used and if present the instruction opcode.
         (++) Address phase : the mode used and if present the size and the address value.
         (++) Alternate-bytes phase : the mode used and if present the size and the alternate
             bytes values.
         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
         (++) Data phase : the mode used and if present the number of bytes.
         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
             if activated.
         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
      (#) If no data is required for the command, it is sent directly to the memory :
         (++) In polling mode, the output of the function is done when the transfer is complete.
         (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
      (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
          HAL_QSPI_Transmit_IT() after the command configuration :
         (++) In polling mode, the output of the function is done when the transfer is complete.
         (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
             is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
         (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
             HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
      (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
          HAL_QSPI_Receive_IT() after the command configuration :
         (++) In polling mode, the output of the function is done when the transfer is complete.
         (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
             is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
         (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
             HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.

    *** Auto-polling functional mode ***
    ====================================
    [..]
      (#) Configure the command sequence and the auto-polling functional mode using the
          HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
         (++) Instruction phase : the mode used and if present the instruction opcode.
         (++) Address phase : the mode used and if present the size and the address value.
         (++) Alternate-bytes phase : the mode used and if present the size and the alternate
             bytes values.
         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
         (++) Data phase : the mode used.
         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
             if activated.
         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
         (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
             the polling interval and the automatic stop activation.
      (#) After the configuration :
         (++) In polling mode, the output of the function is done when the status match is reached. The
             automatic stop is activated to avoid an infinite loop.
         (++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.

    *** Memory-mapped functional mode ***
    =====================================
    [..]
      (#) Configure the command sequence and the memory-mapped functional mode using the
          HAL_QSPI_MemoryMapped() functions :
         (++) Instruction phase : the mode used and if present the instruction opcode.
         (++) Address phase : the mode used and the size.
         (++) Alternate-bytes phase : the mode used and if present the size and the alternate
             bytes values.
         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
         (++) Data phase : the mode used.
         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
             if activated.
         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
         (++) The timeout activation and the timeout period.
      (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
          the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.

    *** Errors management and abort functionality ***
    =================================================
    [..]
      (#) HAL_QSPI_GetError() function gives the error raised during the last operation.
      (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and
          flushes the fifo :
         (++) In polling mode, the output of the function is done when the transfer
              complete bit is set and the busy bit cleared.
         (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when
              the transfer complete bit is set.

    *** Control functions ***
    =========================
    [..]
      (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
      (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.
      (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.
      (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold

    *** Callback registration ***
    =============================================
    [..]
      The compilation define  USE_HAL_QSPI_REGISTER_CALLBACKS when set to 1
      allows the user to configure dynamically the driver callbacks.

      Use Functions @ref HAL_QSPI_RegisterCallback() to register a user callback,
      it allows to register following callbacks:
        (+) ErrorCallback : callback when error occurs.
        (+) AbortCpltCallback : callback when abort is completed.
        (+) FifoThresholdCallback : callback when the fifo threshold is reached.
        (+) CmdCpltCallback : callback when a command without data is completed.
        (+) RxCpltCallback : callback when a reception transfer is completed.
        (+) TxCpltCallback : callback when a transmission transfer is completed.
        (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
        (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
        (+) StatusMatchCallback : callback when a status match occurs.
        (+) TimeOutCallback : callback when the timeout perioed expires.
        (+) MspInitCallback    : QSPI MspInit.
        (+) MspDeInitCallback  : QSPI MspDeInit.
      This function takes as parameters the HAL peripheral handle, the Callback ID
      and a pointer to the user callback function.

      Use function @ref HAL_QSPI_UnRegisterCallback() to reset a callback to the default
      weak (surcharged) function. It allows to reset following callbacks:
        (+) ErrorCallback : callback when error occurs.
        (+) AbortCpltCallback : callback when abort is completed.
        (+) FifoThresholdCallback : callback when the fifo threshold is reached.
        (+) CmdCpltCallback : callback when a command without data is completed.
        (+) RxCpltCallback : callback when a reception transfer is completed.
        (+) TxCpltCallback : callback when a transmission transfer is completed.
        (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
        (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
        (+) StatusMatchCallback : callback when a status match occurs.
        (+) TimeOutCallback : callback when the timeout perioed expires.
        (+) MspInitCallback    : QSPI MspInit.
        (+) MspDeInitCallback  : QSPI MspDeInit.
      This function) takes as parameters the HAL peripheral handle and the Callback ID.

      By default, after the @ref HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET
      all callbacks are reset to the corresponding legacy weak (surcharged) functions.
      Exception done for MspInit and MspDeInit callbacks that are respectively
      reset to the legacy weak (surcharged) functions in the @ref HAL_QSPI_Init
      and @ref  HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand).
      If not, MspInit or MspDeInit are not null, the @ref HAL_QSPI_Init and @ref HAL_QSPI_DeInit
      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)

      Callbacks can be registered/unregistered in READY state only.
      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
      during the Init/DeInit.
      In that case first register the MspInit/MspDeInit user callbacks
      using @ref HAL_QSPI_RegisterCallback before calling @ref HAL_QSPI_DeInit
      or @ref HAL_QSPI_Init function.

      When The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS is set to 0 or
      not defined, the callback registering feature is not available
      and weak (surcharged) callbacks are used.

    *** Workarounds linked to Silicon Limitation ***
    ====================================================
    [..]
      (#) Workarounds Implemented inside HAL Driver
         (++) Extra data written in the FIFO at the end of a read transfer
Attention:

© COPYRIGHT(c) 2019 STMicroelectronics

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_qspi.c.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_rcc.c File Reference

  • File List
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Defines | Functions
stm32wbxx_hal_rcc.c File Reference

RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Defines

#define | HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
#define | HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
#define | MSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
#define | LSI1_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
#define | LSI2_TIMEOUT_VALUE (3U) /* to be adjusted with DS */
#define | HSI48_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
#define | PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
#define | PLLSAI1_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
#define | PRESCALER_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
#define | LATENCY_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
#define | CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */
#define | PLLSOURCE_NONE (0U)
#define | MEGA_HZ 1000000U /* Division factor to convert Hz in Mhz */
#define | __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define | MCO1_GPIO_PORT GPIOA
#define | MCO1_PIN GPIO_PIN_8
#define | __MCO2_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
#define | MCO2_GPIO_PORT GPIOB
#define | MCO2_PIN GPIO_PIN_6
#define | __MCO3_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define | MCO3_GPIO_PORT GPIOA
#define | MCO3_PIN GPIO_PIN_15
#define | RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (uint32_t)(__HAL_RCC_PLLSOURCE__)))
#define | __COUNTOF(_A_) (sizeof(_A_) / sizeof(*(_A_)))

Functions

static HAL_StatusTypeDef | RCC_SetFlashLatencyFromMSIRange (uint32_t MSI_Range)
Update number of Flash wait states in line with MSI range and current voltage range.
static HAL_StatusTypeDef | RCC_SetFlashLatency (uint32_t Flash_ClkSrcFreq, uint32_t VCORE_Voltage)
Update number of Flash wait states.
HAL_StatusTypeDef | HAL_RCC_DeInit (void)
Reset the RCC clock configuration to the default reset state.
HAL_StatusTypeDef | HAL_RCC_OscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Initialize the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.
HAL_StatusTypeDef | HAL_RCC_ClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
Initialize the CPU, AHB and APB buses clocks according to the specified parameters in the RCC_ClkInitStruct.
void | HAL_RCC_MCOConfig (uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
Select the clock source to output on MCO1 pin(PA8) or MC02 pin (PB6) or MCO3 pin (PA15).
uint32_t | HAL_RCC_GetSysClockFreq (void)
Return the SYSCLK frequency.
uint32_t | HAL_RCC_GetHCLKFreq (void)
Return the HCLK frequency.
uint32_t | HAL_RCC_GetHCLK2Freq (void)
Return the HCLK2 frequency.
uint32_t | HAL_RCC_GetHCLK4Freq (void)
Return the HCLK4 frequency.
uint32_t | HAL_RCC_GetPCLK1Freq (void)
Return the PCLK1 frequency.
uint32_t | HAL_RCC_GetPCLK2Freq (void)
Return the PCLK2 frequency.
void | HAL_RCC_GetOscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Configure the RCC_OscInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_GetClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
Configure the RCC_ClkInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_EnableCSS (void)
Enable the Clock Security System.
void | HAL_RCC_NMI_IRQHandler (void)
Handle the RCC HSE Clock Security System interrupt request.
__weak void | HAL_RCC_CSSCallback (void)
Handle the RCC HSE Clock Security System interrupt callback.

Detailed Description

RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions.

Author:
MCD Application Team
  ==============================================================================

                      ##### RCC specific features #####
  ==============================================================================
    [..]
      After reset the device is running from Multiple Speed Internal oscillator
      (4 MHz) with Flash 0 wait state. Flash prefetch buffer, D-Cache
      and I-Cache are disabled, and all peripherals are off except internal
      SRAM, Flash and JTAG.

      (+) There is no prescaler on High speed (AHBs) and Low speed (APBs) buses:
          all peripherals mapped on these buses are running at MSI speed.
      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
      (+) All GPIOs are in analog mode, except the JTAG pins which
          are assigned to be used for debug purpose.

    [..]
      Once the device started from reset, the user application has to:
      (+) Configure the clock source to be used to drive the System clock
          (if the application needs higher frequency/performance)
      (+) Configure the System clock frequency and Flash settings
      (+) Configure the AHB and APB buses prescalers
      (+) Enable the clock for the peripheral(s) to be used
      (+) Configure the clock source(s) for peripherals which clocks are not
          derived from the System clock (SAI1, RTC, ADC, USB/RNG, USART1, LPUART1, LPTIMx, I2Cx, SMPS)
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_rcc.c.

Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_rng.c File Reference

  • File List
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  • STM32WBxx_HAL_Driver
  • Src
Defines | Functions
stm32wbxx_hal_rng.c File Reference

RNG HAL module driver. This file provides firmware functions to manage the following functionalities of the Random Number Generator (RNG) peripheral: + Initialization and configuration functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Defines

#define | RNG_TIMEOUT_VALUE 2U

Functions

HAL_StatusTypeDef | HAL_RNG_Init (RNG_HandleTypeDef *hrng)
Initializes the RNG peripheral and creates the associated handle.
HAL_StatusTypeDef | HAL_RNG_DeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG peripheral.
__weak void | HAL_RNG_MspInit (RNG_HandleTypeDef *hrng)
Initializes the RNG MSP.
__weak void | HAL_RNG_MspDeInit (RNG_HandleTypeDef *hrng)
DeInitializes the RNG MSP.
HAL_StatusTypeDef | HAL_RNG_RegisterCallback (RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback)
Register a User RNG Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_RNG_UnRegisterCallback (RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID)
Unregister an RNG Callback RNG callabck is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_RNG_RegisterReadyDataCallback (RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback)
Register Data Ready RNG Callback To be used instead of the weak HAL_RNG_ReadyDataCallback() predefined callback.
HAL_StatusTypeDef | HAL_RNG_UnRegisterReadyDataCallback (RNG_HandleTypeDef *hrng)
UnRegister the Data Ready RNG Callback Data Ready RNG Callback is redirected to the weak HAL_RNG_ReadyDataCallback() predefined callback.
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber (RNG_HandleTypeDef *hrng, uint32_t *random32bit)
Generates a 32-bit random number.
HAL_StatusTypeDef | HAL_RNG_GenerateRandomNumber_IT (RNG_HandleTypeDef *hrng)
Generates a 32-bit random number in interrupt mode.
void | HAL_RNG_IRQHandler (RNG_HandleTypeDef *hrng)
Handles RNG interrupt request.
uint32_t | HAL_RNG_ReadLastRandomNumber (RNG_HandleTypeDef *hrng)
Read latest generated random number.
__weak void | HAL_RNG_ReadyDataCallback (RNG_HandleTypeDef *hrng, uint32_t random32bit)
Data Ready callback in non-blocking mode.
__weak void | HAL_RNG_ErrorCallback (RNG_HandleTypeDef *hrng)
RNG error callbacks.
HAL_RNG_StateTypeDef | HAL_RNG_GetState (RNG_HandleTypeDef *hrng)
Returns the RNG state.
uint32_t | HAL_RNG_GetError (RNG_HandleTypeDef *hrng)
Return the RNG handle error code.

Detailed Description

RNG HAL module driver. This file provides firmware functions to manage the following functionalities of the Random Number Generator (RNG) peripheral: + Initialization and configuration functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
  [..]
      The RNG HAL driver can be used as follows:

      (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro
          in HAL_RNG_MspInit().
      (#) Activate the RNG peripheral using HAL_RNG_Init() function.
      (#) Wait until the 32 bit Random Number Generator contains a valid
          random data using (polling/interrupt) mode.
      (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.

    ##### Callback registration #####
    ==================================

    [..]
    The compilation define USE_HAL_RNG_REGISTER_CALLBACKS when set to 1
    allows the user to configure dynamically the driver callbacks.

    [..]
    Use Function @ref HAL_RNG_RegisterCallback() to register a user callback.
    Function @ref HAL_RNG_RegisterCallback() allows to register following callbacks:
    (+) ErrorCallback             : RNG Error Callback.
    (+) MspInitCallback           : RNG MspInit.
    (+) MspDeInitCallback         : RNG MspDeInit.
    This function takes as parameters the HAL peripheral handle, the Callback ID
    and a pointer to the user callback function.

    [..]
    Use function @ref HAL_RNG_UnRegisterCallback() to reset a callback to the default
    weak (surcharged) function.
    @ref HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle,
    and the Callback ID.
    This function allows to reset following callbacks:
    (+) ErrorCallback             : RNG Error Callback.
    (+) MspInitCallback           : RNG MspInit.
    (+) MspDeInitCallback         : RNG MspDeInit.

    [..]
    For specific callback ReadyDataCallback, use dedicated register callbacks:
    respectively @ref HAL_RNG_RegisterReadyDataCallback() , @ref HAL_RNG_UnRegisterReadyDataCallback().

    [..]
    By default, after the @ref HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET
    all callbacks are set to the corresponding weak (surcharged) functions:
    example @ref HAL_RNG_ErrorCallback().
    Exception done for MspInit and MspDeInit functions that are respectively
    reset to the legacy weak (surcharged) functions in the @ref HAL_RNG_Init()
    and @ref HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand).
    If not, MspInit or MspDeInit are not null, the @ref HAL_RNG_Init() and @ref HAL_RNG_DeInit()
    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).

    [..]
    Callbacks can be registered/unregistered in HAL_RNG_STATE_READY state only.
    Exception done MspInit/MspDeInit that can be registered/unregistered
    in HAL_RNG_STATE_READY or HAL_RNG_STATE_RESET state, thus registered (user)
    MspInit/DeInit callbacks can be used during the Init/DeInit.
    In that case first register the MspInit/MspDeInit user callbacks
    using @ref HAL_RNG_RegisterCallback() before calling @ref HAL_RNG_DeInit()
    or @ref HAL_RNG_Init() function.

    [..]
    When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or
    not defined, the callback registration feature is not available
    and weak (surcharged) callbacks are used.
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_rng.c.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_rtc.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32WBxx_HAL_Driver
  • Src
Functions
stm32wbxx_hal_rtc.c File Reference

RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real-Time Clock (RTC) peripheral: + Initialization + Calendar (Time and Date) configuration + Alarms (Alarm A and Alarm B) configuration + WakeUp Timer configuration + TimeStamp configuration + Tampers configuration + Backup Data Registers configuration + RTC Tamper and TimeStamp Pins Selection + Interrupts and flags management. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_RTC_Init (RTC_HandleTypeDef *hrtc)
Initialize the RTC peripheral.
HAL_StatusTypeDef | HAL_RTC_DeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC peripheral.
HAL_StatusTypeDef | HAL_RTC_RegisterCallback (RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback)
Register a User RTC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_RTC_UnRegisterCallback (RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID)
Unregister an RTC Callback RTC callabck is redirected to the weak predefined callback.
__weak void | HAL_RTC_MspInit (RTC_HandleTypeDef *hrtc)
Initialize the RTC MSP.
__weak void | HAL_RTC_MspDeInit (RTC_HandleTypeDef *hrtc)
DeInitialize the RTC MSP.
HAL_StatusTypeDef | HAL_RTC_SetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Set RTC current time.
HAL_StatusTypeDef | HAL_RTC_GetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Get RTC current time.
HAL_StatusTypeDef | HAL_RTC_SetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Set RTC current date.
HAL_StatusTypeDef | HAL_RTC_GetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Get RTC current date.
HAL_StatusTypeDef | HAL_RTC_SetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_SetAlarm_IT (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Set the specified RTC Alarm with Interrupt.
HAL_StatusTypeDef | HAL_RTC_DeactivateAlarm (RTC_HandleTypeDef *hrtc, uint32_t Alarm)
Deactivate the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_GetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
Get the RTC Alarm value and masks.
void | HAL_RTC_AlarmIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Alarm interrupt request.
__weak void | HAL_RTC_AlarmAEventCallback (RTC_HandleTypeDef *hrtc)
Alarm A callback.
HAL_StatusTypeDef | HAL_RTC_PollForAlarmAEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle AlarmA Polling request.
HAL_StatusTypeDef | HAL_RTC_WaitForSynchro (RTC_HandleTypeDef *hrtc)
Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.
HAL_RTCStateTypeDef | HAL_RTC_GetState (RTC_HandleTypeDef *hrtc)
Return the RTC handle state.
HAL_StatusTypeDef | RTC_EnterInitMode (RTC_HandleTypeDef *hrtc)
Enter the RTC Initialization mode.
uint8_t | RTC_ByteToBcd2 (uint8_t Value)
Convert a 2 digit decimal to BCD format.
uint8_t | RTC_Bcd2ToByte (uint8_t Value)
Convert from 2 digit BCD to Binary.

Detailed Description

RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real-Time Clock (RTC) peripheral: + Initialization + Calendar (Time and Date) configuration + Alarms (Alarm A and Alarm B) configuration + WakeUp Timer configuration + TimeStamp configuration + Tampers configuration + Backup Data Registers configuration + RTC Tamper and TimeStamp Pins Selection + Interrupts and flags management.

Author:
MCD Application Team
 ===============================================================================
                          ##### RTC Operating Condition #####
 ===============================================================================
  [..] The real-time clock (RTC) and the RTC backup registers can be powered
       from the VBAT voltage when the main VDD supply is powered off.
       To retain the content of the RTC backup registers and supply the RTC
       when VDD is turned off, VBAT pin can be connected to an optional
       standby voltage supplied by a battery or by another source.

                   ##### Backup Domain Reset #####
 ===============================================================================
  [..] The backup domain reset sets all RTC registers and the RCC_BDCR register
       to their reset values.
       A backup domain reset is generated when one of the following events occurs:
    (+) Software reset, triggered by setting the BDRST bit in the
        RCC Backup domain control register (RCC_BDCR).
    (+) VDD or VBAT power on, if both supplies have previously been powered off.
    (+) Tamper detection event resets all data backup registers.

                   ##### Backup Domain Access #####
 ===================================================================
  [..] After reset, the backup domain (RTC registers, RTC backup data
       registers and backup SRAM) is protected against possible unwanted write
       accesses.

  [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
    (+) Call the function HAL_RCCEx_PeriphCLKConfig with RCC_PERIPHCLK_RTC for
        PeriphClockSelection and select RTCClockSelection (LSE, LSI or HSEdiv32)
    (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() macro.

                  ##### How to use RTC Driver #####
 ===================================================================
  [..]
    (+) Enable the RTC domain access (see description in the section above).
    (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
        format using the HAL_RTC_Init() function.

  *** Time and Date configuration ***
  ===================================
  [..]
    (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
        and HAL_RTC_SetDate() functions.
    (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.

  *** Alarm configuration ***
  ===========================
  [..]
    (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
            You can also configure the RTC Alarm with interrupt mode using the
            HAL_RTC_SetAlarm_IT() function.
    (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.

                  ##### RTC and low power modes #####
  ==================================================================
  [..] The MCU can be woken up from a low power mode by an RTC alternate
       function.
  [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
       RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
       These RTC alternate functions can wake up the system from the Stop and
       Standby low power modes.
  [..] The system can also wake up from low power modes without depending
       on an external interrupt (Auto-wakeup mode), by using the RTC alarm
       or the RTC wakeup events.
  [..] The RTC provides a programmable time base for waking up from the
       Stop or Standby mode at regular intervals.
       Wakeup from STOP and STANDBY modes is possible only when the RTC clock source
       is LSE or LSI.

  *** Callback registration ***
  =============================================

  [..]
  The compilation define  USE_RTC_REGISTER_CALLBACKS when set to 1
  allows the user to configure dynamically the driver callbacks.
  Use Function @ref HAL_RTC_RegisterCallback() to register an interrupt callback.

  [..]
  Function @ref HAL_RTC_RegisterCallback() allows to register following callbacks:
    (+) AlarmAEventCallback          : RTC Alarm A Event callback.
    (+) AlarmBEventCallback          : RTC Alarm B Event callback.
    (+) TimeStampEventCallback       : RTC TimeStamp Event callback.
    (+) WakeUpTimerEventCallback     : RTC WakeUpTimer Event callback.
    (+) Tamper1EventCallback         : RTC Tamper 1 Event callback.
    (+) Tamper2EventCallback         : RTC Tamper 2 Event callback.
    (+) Tamper3EventCallback         : RTC Tamper 3 Event callback.
    (+) MspInitCallback              : RTC MspInit callback.
    (+) MspDeInitCallback            : RTC MspDeInit callback.
  [..]
  This function takes as parameters the HAL peripheral handle, the Callback ID
  and a pointer to the user callback function.

  [..]
  Use function @ref HAL_RTC_UnRegisterCallback() to reset a callback to the default
  weak function.
  @ref HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
  and the Callback ID.
  This function allows to reset following callbacks:
    (+) AlarmAEventCallback          : RTC Alarm A Event callback.
    (+) AlarmBEventCallback          : RTC Alarm B Event callback.
    (+) TimeStampEventCallback       : RTC TimeStamp Event callback.
    (+) WakeUpTimerEventCallback     : RTC WakeUpTimer Event callback.
    (+) Tamper1EventCallback         : RTC Tamper 1 Event callback.
    (+) Tamper2EventCallback         : RTC Tamper 2 Event callback.
    (+) Tamper3EventCallback         : RTC Tamper 3 Event callback.
    (+) MspInitCallback              : RTC MspInit callback.
    (+) MspDeInitCallback            : RTC MspDeInit callback.

  [..]
  By default, after the @ref HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET,
  all callbacks are set to the corresponding weak functions :
  examples @ref AlarmAEventCallback(), @ref WakeUpTimerEventCallback().
  Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function
  in the @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() only when these callbacks are null
  (not registered beforehand).
  If not, MspInit or MspDeInit are not null, @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit()
  keep and use the user MspInit/MspDeInit callbacks (registered beforehand)

  [..]
  Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only.
  Exception done MspInit/MspDeInit that can be registered/unregistered
  in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state,
  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
  In that case first register the MspInit/MspDeInit user callbacks
  using @ref HAL_RTC_RegisterCallback() before calling @ref HAL_RTC_DeInit()
  or @ref HAL_RTC_Init() function.

  [..]
  When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or
  not defined, the callback registration feature is not available and all callbacks
  are set to the corresponding weak functions.
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_rtc.c.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_rtc_ex.c File Reference

  • File List
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  • STM32WBxx_HAL_Driver
  • Src
Defines | Functions
stm32wbxx_hal_rtc_ex.c File Reference

Extended RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extended peripheral: + RTC Time Stamp functions + RTC Tamper functions + RTC Wake-up functions + Extended Control functions + Extended RTC features functions. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Defines

#define | RTC_TAMPCR_MASK

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetTimeStamp_IT (RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
Set TimeStamp with Interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivate TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_SetInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Set Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateInternalTimeStamp (RTC_HandleTypeDef *hrtc)
Deactivate Internal TimeStamp.
HAL_StatusTypeDef | HAL_RTCEx_GetTimeStamp (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
Get the RTC TimeStamp value.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper_IT (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Set Tamper with interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTamper (RTC_HandleTypeDef *hrtc, uint32_t Tamper)
Deactivate Tamper.
void | HAL_RTCEx_TamperTimeStampIRQHandler (RTC_HandleTypeDef *hrtc)
Handle TimeStamp interrupt request.
__weak void | HAL_RTCEx_TimeStampEventCallback (RTC_HandleTypeDef *hrtc)
TimeStamp callback.
__weak void | HAL_RTCEx_Tamper1EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 1 callback.
__weak void | HAL_RTCEx_Tamper2EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 2 callback.
__weak void | HAL_RTCEx_Tamper3EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 3 callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForTimeStampEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle TimeStamp polling request.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper1Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper 1 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper2Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper 2 Polling.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper3Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Tamper 3 Polling.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer.
HAL_StatusTypeDef | HAL_RTCEx_SetWakeUpTimer_IT (RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
Set wake up timer with interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateWakeUpTimer (RTC_HandleTypeDef *hrtc)
Deactivate wake up timer counter.
uint32_t | HAL_RTCEx_GetWakeUpTimer (RTC_HandleTypeDef *hrtc)
Get wake up timer counter.
void | HAL_RTCEx_WakeUpTimerIRQHandler (RTC_HandleTypeDef *hrtc)
Handle Wake Up Timer interrupt request.
__weak void | HAL_RTCEx_WakeUpTimerEventCallback (RTC_HandleTypeDef *hrtc)
Wake Up Timer callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForWakeUpTimerEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Wake Up Timer Polling.
void | HAL_RTCEx_BKUPWrite (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
Write a data in a specified RTC Backup data register.
uint32_t | HAL_RTCEx_BKUPRead (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
Reads data from the specified RTC Backup data Register.
HAL_StatusTypeDef | HAL_RTCEx_SetSmoothCalib (RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
Set the Smooth calibration parameters.
HAL_StatusTypeDef | HAL_RTCEx_SetSynchroShift (RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
Configure the Synchronization Shift Control Settings.
HAL_StatusTypeDef | HAL_RTCEx_SetCalibrationOutPut (RTC_HandleTypeDef *hrtc, uint32_t CalibOutput)
Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_DeactivateCalibrationOutPut (RTC_HandleTypeDef *hrtc)
Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
HAL_StatusTypeDef | HAL_RTCEx_SetRefClock (RTC_HandleTypeDef *hrtc)
Enable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateRefClock (RTC_HandleTypeDef *hrtc)
Disable the RTC reference clock detection.
HAL_StatusTypeDef | HAL_RTCEx_EnableBypassShadow (RTC_HandleTypeDef *hrtc)
Enable the Bypass Shadow feature.
HAL_StatusTypeDef | HAL_RTCEx_DisableBypassShadow (RTC_HandleTypeDef *hrtc)
Disable the Bypass Shadow feature.
__weak void | HAL_RTCEx_AlarmBEventCallback (RTC_HandleTypeDef *hrtc)
Alarm B callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForAlarmBEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
Handle Alarm B Polling request.

Detailed Description

Extended RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extended peripheral: + RTC Time Stamp functions + RTC Tamper functions + RTC Wake-up functions + Extended Control functions + Extended RTC features functions.

Author:
MCD Application Team
  ==============================================================================
                  ##### How to use this driver #####
  ==============================================================================
  [..]
    (+) Enable the RTC domain access.
    (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
        format using the HAL_RTC_Init() function.

  *** RTC Wakeup configuration ***
  ================================
  [..]
    (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer()
        function. You can also configure the RTC Wakeup timer with interrupt mode
        using the HAL_RTCEx_SetWakeUpTimer_IT() function.
    (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer()
        function.

  *** Outputs configuration ***
  =============================
  [..]  The RTC has 2 different outputs:
    (+) RTC_ALARM: this output is used to manage the RTC Alarm A, Alarm B
        and WaKeUp signals.
        To output the selected RTC signal, use the HAL_RTC_Init() function.
    (+) RTC_CALIB: this output is 512Hz signal or 1Hz.
        To enable the RTC_CALIB, use the HAL_RTCEx_SetCalibrationOutPut() function.
    (+) Two pins can be used as RTC_ALARM or RTC_CALIB (PC13, PB2) managed on
        the RTC_OR register.
    (+) When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is
        automatically configured in output alternate function.

  *** Smooth digital Calibration configuration ***
  ================================================
  [..]
    (+) Configure the RTC Original Digital Calibration Value and the corresponding
        calibration cycle period (32s,16s and 8s) using the HAL_RTCEx_SetSmoothCalib()
        function.

  *** TimeStamp configuration ***
  ===============================
  [..]
    (+) Enable the RTC TimeStamp using the HAL_RTCEx_SetTimeStamp() function.
        You can also configure the RTC TimeStamp with interrupt mode using the
        HAL_RTCEx_SetTimeStamp_IT() function.
    (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
        function.

  *** Internal TimeStamp configuration ***
  ===============================
  [..]
    (+) Enable the RTC internal TimeStamp using the HAL_RTCEx_SetInternalTimeStamp() function.
        User has to check internal timestamp occurrence using __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG.
    (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
        function.

  *** Tamper configuration ***
  ============================
  [..]
    (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge
        or Level according to the Tamper filter (if equal to 0 Edge else Level)
        value, sampling frequency, NoErase, MaskFlag,  precharge or discharge and
        Pull-UP using the HAL_RTCEx_SetTamper() function. You can configure RTC Tamper
        with interrupt mode using HAL_RTCEx_SetTamper_IT() function.
    (+) The default configuration of the Tamper erases the backup registers. To avoid
        erase, enable the NoErase field on the RTC_TAMPCR register.

  *** Backup Data Registers configuration ***
  ===========================================
  [..]
    (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite()
        function.
    (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
        function.
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_rtc_ex.c.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_sai.c File Reference

  • File List
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Defines | Enumerations | Functions
stm32wbxx_hal_sai.c File Reference

SAI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Audio Interface (SAI) peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Defines

#define | SAI_DEFAULT_TIMEOUT 4U
#define | SAI_LONG_TIMEOUT 1000U

Enumerations

enum | SAI_ModeTypedef { SAI_MODE_DMA, SAI_MODE_IT }

Functions

static void | SAI_FillFifo (SAI_HandleTypeDef *hsai)
Fill the fifo.
static uint32_t | SAI_InterruptFlag (const SAI_HandleTypeDef *hsai, SAI_ModeTypedef mode)
Return the interrupt flag to set according the SAI setup.
static HAL_StatusTypeDef | SAI_InitI2S (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initialize the SAI I2S protocol according to the specified parameters in the SAI_InitTypeDef and create the associated handle.
static HAL_StatusTypeDef | SAI_InitPCM (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initialize the SAI PCM protocol according to the specified parameters in the SAI_InitTypeDef and create the associated handle.
static HAL_StatusTypeDef | SAI_Disable (SAI_HandleTypeDef *hsai)
Disable the SAI and wait for the disabling.
static void | SAI_Transmit_IT8Bit (SAI_HandleTypeDef *hsai)
Tx Handler for Transmit in Interrupt mode 8-Bit transfer.
static void | SAI_Transmit_IT16Bit (SAI_HandleTypeDef *hsai)
Tx Handler for Transmit in Interrupt mode for 16-Bit transfer.
static void | SAI_Transmit_IT32Bit (SAI_HandleTypeDef *hsai)
Tx Handler for Transmit in Interrupt mode for 32-Bit transfer.
static void | SAI_Receive_IT8Bit (SAI_HandleTypeDef *hsai)
Rx Handler for Receive in Interrupt mode 8-Bit transfer.
static void | SAI_Receive_IT16Bit (SAI_HandleTypeDef *hsai)
Rx Handler for Receive in Interrupt mode for 16-Bit transfer.
static void | SAI_Receive_IT32Bit (SAI_HandleTypeDef *hsai)
Rx Handler for Receive in Interrupt mode for 32-Bit transfer.
static void | SAI_DMATxCplt (DMA_HandleTypeDef *hdma)
DMA SAI transmit process complete callback.
static void | SAI_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SAI transmit process half complete callback.
static void | SAI_DMARxCplt (DMA_HandleTypeDef *hdma)
DMA SAI receive process complete callback.
static void | SAI_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA SAI receive process half complete callback.
static void | SAI_DMAError (DMA_HandleTypeDef *hdma)
DMA SAI communication error callback.
static void | SAI_DMAAbort (DMA_HandleTypeDef *hdma)
DMA SAI Abort callback.
HAL_StatusTypeDef | HAL_SAI_InitProtocol (SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
Initialize the structure FrameInit, SlotInit and the low part of Init according to the specified parameters and call the function HAL_SAI_Init to initialize the SAI block.
HAL_StatusTypeDef | HAL_SAI_Init (SAI_HandleTypeDef *hsai)
Initialize the SAI according to the specified parameters.
HAL_StatusTypeDef | HAL_SAI_DeInit (SAI_HandleTypeDef *hsai)
DeInitialize the SAI peripheral.
__weak void | HAL_SAI_MspInit (SAI_HandleTypeDef *hsai)
Initialize the SAI MSP.
__weak void | HAL_SAI_MspDeInit (SAI_HandleTypeDef *hsai)
DeInitialize the SAI MSP.
HAL_StatusTypeDef | HAL_SAI_RegisterCallback (SAI_HandleTypeDef *hsai, HAL_SAI_CallbackIDTypeDef CallbackID, pSAI_CallbackTypeDef pCallback)
Register a user SAI callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SAI_UnRegisterCallback (SAI_HandleTypeDef *hsai, HAL_SAI_CallbackIDTypeDef CallbackID)
Unregister a user SAI callback.
HAL_StatusTypeDef | HAL_SAI_Transmit (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SAI_Receive (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SAI_Transmit_IT (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SAI_Receive_IT (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SAI_DMAPause (SAI_HandleTypeDef *hsai)
Pause the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_DMAResume (SAI_HandleTypeDef *hsai)
Resume the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_DMAStop (SAI_HandleTypeDef *hsai)
Stop the audio stream playing from the Media.
HAL_StatusTypeDef | HAL_SAI_Abort (SAI_HandleTypeDef *hsai)
Abort the current transfer and disable the SAI.
HAL_StatusTypeDef | HAL_SAI_Transmit_DMA (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SAI_Receive_DMA (SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SAI_EnableTxMuteMode (SAI_HandleTypeDef *hsai, uint16_t val)
Enable the Tx mute mode.
HAL_StatusTypeDef | HAL_SAI_DisableTxMuteMode (SAI_HandleTypeDef *hsai)
Disable the Tx mute mode.
HAL_StatusTypeDef | HAL_SAI_EnableRxMuteMode (SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter)
Enable the Rx mute detection.
HAL_StatusTypeDef | HAL_SAI_DisableRxMuteMode (SAI_HandleTypeDef *hsai)
Disable the Rx mute detection.
void | HAL_SAI_IRQHandler (SAI_HandleTypeDef *hsai)
Handle SAI interrupt request.
__weak void | HAL_SAI_TxCpltCallback (SAI_HandleTypeDef *hsai)
Tx Transfer completed callback.
__weak void | HAL_SAI_TxHalfCpltCallback (SAI_HandleTypeDef *hsai)
Tx Transfer Half completed callback.
__weak void | HAL_SAI_RxCpltCallback (SAI_HandleTypeDef *hsai)
Rx Transfer completed callback.
__weak void | HAL_SAI_RxHalfCpltCallback (SAI_HandleTypeDef *hsai)
Rx Transfer half completed callback.
__weak void | HAL_SAI_ErrorCallback (SAI_HandleTypeDef *hsai)
SAI error callback.
HAL_SAI_StateTypeDef | HAL_SAI_GetState (SAI_HandleTypeDef *hsai)
Return the SAI handle state.
uint32_t | HAL_SAI_GetError (SAI_HandleTypeDef *hsai)
Return the SAI error code.

Detailed Description

SAI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Audio Interface (SAI) peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
  ==============================================================================
                  ##### How to use this driver #####
  ==============================================================================

  [..]
    The SAI HAL driver can be used as follows:

    (#) Declare a SAI_HandleTypeDef handle structure (eg. SAI_HandleTypeDef hsai).
    (#) Initialize the SAI low level resources by implementing the HAL_SAI_MspInit() API:
        (##) Enable the SAI interface clock.
        (##) SAI pins configuration:
            (+++) Enable the clock for the SAI GPIOs.
            (+++) Configure these SAI pins as alternate function pull-up.
        (##) NVIC configuration if you need to use interrupt process (HAL_SAI_Transmit_IT()
             and HAL_SAI_Receive_IT() APIs):
            (+++) Configure the SAI interrupt priority.
            (+++) Enable the NVIC SAI IRQ handle.

        (##) DMA Configuration if you need to use DMA process (HAL_SAI_Transmit_DMA()
             and HAL_SAI_Receive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx stream.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx Stream.
            (+++) Associate the initialized DMA handle to the SAI DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
                DMA Tx/Rx Stream.

    (#) The initialization can be done by two ways
        (##) Expert mode : Initialize the structures Init, FrameInit and SlotInit and call HAL_SAI_Init().
        (##) Simplified mode : Initialize the high part of Init Structure and call HAL_SAI_InitProtocol().

  [..]
    (@) The specific SAI interrupts (FIFO request and Overrun underrun interrupt)
        will be managed using the macros __HAL_SAI_ENABLE_IT() and __HAL_SAI_DISABLE_IT()
        inside the transmit and receive process.
  [..]
    (@) Make sure that either:
        (+@) PLLSAI1CLK output is configured or
        (+@) PLLSAI2CLK output is configured or
        (+@) PLLSAI3CLK output is configured or
        (+@) External clock source is configured after setting correctly
             the define constant EXTERNAL_SAI1_CLOCK_VALUE or EXTERNAL_SAI2_CLOCK_VALUE in the stm32wbxx_hal_conf.h file.

  [..]
    (@) In master Tx mode: enabling the audio block immediately generates the bit clock
        for the external slaves even if there is no data in the FIFO, However FS signal
        generation is conditioned by the presence of data in the FIFO.

  [..]
    (@) In master Rx mode: enabling the audio block immediately generates the bit clock
        and FS signal for the external slaves.

  [..]
    (@) It is mandatory to respect the following conditions in order to avoid bad SAI behavior:
        (+@) First bit Offset <= (SLOT size - Data size)
        (+@) Data size <= SLOT size
        (+@) Number of SLOT x SLOT size = Frame length
        (+@) The number of slots should be even when SAI_FS_CHANNEL_IDENTIFICATION is selected.

  [..]
    (@) PDM interface can be activated through HAL_SAI_Init function.
        Please note that PDM interface is only available for SAI1 sub-block A.
        PDM microphone delays can be tuned with HAL_SAIEx_ConfigPdmMicDelay function.

  [..]
    Three operation modes are available within this driver :

    *** Polling mode IO operation ***
    =================================
    [..]
      (+) Send an amount of data in blocking mode using HAL_SAI_Transmit()
      (+) Receive an amount of data in blocking mode using HAL_SAI_Receive()

    *** Interrupt mode IO operation ***
    ===================================
    [..]
      (+) Send an amount of data in non-blocking mode using HAL_SAI_Transmit_IT()
      (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can
          add his own code by customization of function pointer HAL_SAI_TxCpltCallback()
      (+) Receive an amount of data in non-blocking mode using HAL_SAI_Receive_IT()
      (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can
          add his own code by customization of function pointer HAL_SAI_RxCpltCallback()
      (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can
          add his own code by customization of function pointer HAL_SAI_ErrorCallback()

    *** DMA mode IO operation ***
    =============================
    [..]
      (+) Send an amount of data in non-blocking mode (DMA) using HAL_SAI_Transmit_DMA()
      (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can
          add his own code by customization of function pointer HAL_SAI_TxCpltCallback()
      (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SAI_Receive_DMA()
      (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can
          add his own code by customization of function pointer HAL_SAI_RxCpltCallback()
      (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can
          add his own code by customization of function pointer HAL_SAI_ErrorCallback()
      (+) Pause the DMA Transfer using HAL_SAI_DMAPause()
      (+) Resume the DMA Transfer using HAL_SAI_DMAResume()
      (+) Stop the DMA Transfer using HAL_SAI_DMAStop()

    *** SAI HAL driver additional function list ***
    ===============================================
    [..]
      Below the list the others API available SAI HAL driver :

      (+) HAL_SAI_EnableTxMuteMode(): Enable the mute in tx mode
      (+) HAL_SAI_DisableTxMuteMode(): Disable the mute in tx mode
      (+) HAL_SAI_EnableRxMuteMode(): Enable the mute in Rx mode
      (+) HAL_SAI_DisableRxMuteMode(): Disable the mute in Rx mode
      (+) HAL_SAI_FlushRxFifo(): Flush the rx fifo.
      (+) HAL_SAI_Abort(): Abort the current transfer

    *** SAI HAL driver macros list ***
    ==================================
    [..]
      Below the list of most used macros in SAI HAL driver :

      (+) __HAL_SAI_ENABLE(): Enable the SAI peripheral
      (+) __HAL_SAI_DISABLE(): Disable the SAI peripheral
      (+) __HAL_SAI_ENABLE_IT(): Enable the specified SAI interrupts
      (+) __HAL_SAI_DISABLE_IT(): Disable the specified SAI interrupts
      (+) __HAL_SAI_GET_IT_SOURCE(): Check if the specified SAI interrupt source is
          enabled or disabled
      (+) __HAL_SAI_GET_FLAG(): Check whether the specified SAI flag is set or not

    *** Callback registration ***
    =============================
    [..]
    The compilation define USE_HAL_SAI_REGISTER_CALLBACKS when set to 1
    allows the user to configure dynamically the driver callbacks.
    Use functions HAL_SAI_RegisterCallback() to register a user callback.

    [..]
    Function HAL_SAI_RegisterCallback() allows to register following callbacks:
      (+) RxCpltCallback     : SAI receive complete.
      (+) RxHalfCpltCallback : SAI receive half complete.
      (+) TxCpltCallback     : SAI transmit complete.
      (+) TxHalfCpltCallback : SAI transmit half complete.
      (+) ErrorCallback      : SAI error.
      (+) MspInitCallback    : SAI MspInit.
      (+) MspDeInitCallback  : SAI MspDeInit.
    [..]
    This function takes as parameters the HAL peripheral handle, the callback ID
    and a pointer to the user callback function.

    [..]
    Use function HAL_SAI_UnRegisterCallback() to reset a callback to the default
    weak (surcharged) function.
    HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
    and the callback ID.
    [..]
    This function allows to reset following callbacks:
      (+) RxCpltCallback     : SAI receive complete.
      (+) RxHalfCpltCallback : SAI receive half complete.
      (+) TxCpltCallback     : SAI transmit complete.
      (+) TxHalfCpltCallback : SAI transmit half complete.
      (+) ErrorCallback      : SAI error.
      (+) MspInitCallback    : SAI MspInit.
      (+) MspDeInitCallback  : SAI MspDeInit.

    [..]
    By default, after the HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET
    all callbacks are reset to the corresponding legacy weak (surcharged) functions:
    examples HAL_SAI_RxCpltCallback(), HAL_SAI_ErrorCallback().
    Exception done for MspInit and MspDeInit callbacks that are respectively
    reset to the legacy weak (surcharged) functions in the HAL_SAI_Init
    and HAL_SAI_DeInit only when these callbacks are null (not registered beforehand).
    If not, MspInit or MspDeInit are not null, the HAL_SAI_Init and HAL_SAI_DeInit
    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).

    [..]
    Callbacks can be registered/unregistered in READY state only.
    Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
    in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
    during the Init/DeInit.
    In that case first register the MspInit/MspDeInit user callbacks
    using HAL_SAI_RegisterCallback before calling HAL_SAI_DeInit
    or HAL_SAI_Init function.

    [..]
    When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or
    not defined, the callback registering feature is not available
    and weak (surcharged) callbacks are used.
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_sai.c.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_sai_ex.c File Reference

  • File List
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  • STM32WBxx_HAL_Driver
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Defines | Functions
stm32wbxx_hal_sai_ex.c File Reference

SAI Extended HAL module driver. This file provides firmware functions to manage the following functionality of the SAI Peripheral Controller: + Modify PDM microphone delays. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Defines

#define | SAI_PDM_DELAY_MASK 0x77U
#define | SAI_PDM_DELAY_OFFSET 8U
#define | SAI_PDM_RIGHT_DELAY_OFFSET 4U

Functions

HAL_StatusTypeDef | HAL_SAIEx_ConfigPdmMicDelay (SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay)
Configure PDM microphone delays.

Detailed Description

SAI Extended HAL module driver. This file provides firmware functions to manage the following functionality of the SAI Peripheral Controller: + Modify PDM microphone delays.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_sai_ex.c.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_smartcard.c File Reference

  • File List
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stm32wbxx_hal_smartcard.c File Reference

SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Defines

#define | SMARTCARD_TEACK_REACK_TIMEOUT 1000U
#define | USART_CR1_FIELDS
#define | USART_CR2_CLK_FIELDS
#define | USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | USART_CR2_STOP))
#define | USART_CR3_FIELDS
#define | USART_BRR_MIN 0x10U
#define | USART_BRR_MAX 0x0000FFFFU

Functions

void | SMARTCARD_InitCallbacksToDefault (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the callbacks to their default values.
static HAL_StatusTypeDef | SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsmartcard)
Configure the SMARTCARD associated USART peripheral.
static void | SMARTCARD_AdvFeatureConfig (SMARTCARD_HandleTypeDef *hsmartcard)
Configure the SMARTCARD associated USART peripheral advanced features.
static HAL_StatusTypeDef | SMARTCARD_CheckIdleState (SMARTCARD_HandleTypeDef *hsmartcard)
Check the SMARTCARD Idle State.
static HAL_StatusTypeDef | SMARTCARD_WaitOnFlagUntilTimeout (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle SMARTCARD Communication Timeout.
static void | SMARTCARD_EndTxTransfer (SMARTCARD_HandleTypeDef *hsmartcard)
End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
static void | SMARTCARD_EndRxTransfer (SMARTCARD_HandleTypeDef *hsmartcard)
End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
static void | SMARTCARD_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD transmit process complete callback.
static void | SMARTCARD_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD receive process complete callback.
static void | SMARTCARD_DMAError (DMA_HandleTypeDef *hdma)
DMA SMARTCARD communication error callback.
static void | SMARTCARD_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA SMARTCARD communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | SMARTCARD_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | SMARTCARD_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | SMARTCARD_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | SMARTCARD_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static void | SMARTCARD_TxISR (SMARTCARD_HandleTypeDef *hsmartcard)
Send an amount of data in non-blocking mode.
static void | SMARTCARD_TxISR_FIFOEN (SMARTCARD_HandleTypeDef *hsmartcard)
Send an amount of data in non-blocking mode.
static void | SMARTCARD_EndTransmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Wrap up transmission in non-blocking mode.
static void | SMARTCARD_RxISR (SMARTCARD_HandleTypeDef *hsmartcard)
Receive an amount of data in non-blocking mode.
static void | SMARTCARD_RxISR_FIFOEN (SMARTCARD_HandleTypeDef *hsmartcard)
Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Init (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD mode according to the specified parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMARTCARD_DeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD peripheral.
__weak void | HAL_SMARTCARD_MspInit (SMARTCARD_HandleTypeDef *hsmartcard)
Initialize the SMARTCARD MSP.
__weak void | HAL_SMARTCARD_MspDeInit (SMARTCARD_HandleTypeDef *hsmartcard)
DeInitialize the SMARTCARD MSP.
HAL_StatusTypeDef | HAL_SMARTCARD_RegisterCallback (SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback)
Register a User SMARTCARD Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SMARTCARD_UnRegisterCallback (SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID)
Unregister an SMARTCARD callback SMARTCARD callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_DMA (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_DMA (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Abort (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_Abort_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_SMARTCARD_IRQHandler (SMARTCARD_HandleTypeDef *hsmartcard)
Handle SMARTCARD interrupt requests.
__weak void | HAL_SMARTCARD_TxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Tx Transfer completed callback.
__weak void | HAL_SMARTCARD_RxCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
Rx Transfer completed callback.
__weak void | HAL_SMARTCARD_ErrorCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD error callback.
__weak void | HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Complete callback.
__weak void | HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Complete callback.
__weak void | HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD Abort Receive Complete callback.
HAL_SMARTCARD_StateTypeDef | HAL_SMARTCARD_GetState (SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle state.
uint32_t | HAL_SMARTCARD_GetError (SMARTCARD_HandleTypeDef *hsmartcard)
Return the SMARTCARD handle error code.

Detailed Description

SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
    The SMARTCARD HAL driver can be used as follows:

    (#) Declare a SMARTCARD_HandleTypeDef handle structure (eg. SMARTCARD_HandleTypeDef hsmartcard).
    (#) Associate a USART to the SMARTCARD handle hsmartcard.
    (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
        (++) Enable the USARTx interface clock.
        (++) USART pins configuration:
             (+++) Enable the clock for the USART GPIOs.
             (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
        (++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
             and HAL_SMARTCARD_Receive_IT() APIs):
             (+++) Configure the USARTx interrupt priority.
             (+++) Enable the NVIC USART IRQ handle.
        (++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
             and HAL_SMARTCARD_Receive_DMA() APIs):
             (+++) Declare a DMA handle structure for the Tx/Rx channel.
             (+++) Enable the DMAx interface clock.
             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
             (+++) Configure the DMA Tx/Rx channel.
             (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.

    (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
        the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
        error enabling or disabling in the hsmartcard handle Init structure.

    (#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...)
        in the hsmartcard handle AdvancedInit structure.

    (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
        (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
             by calling the customized HAL_SMARTCARD_MspInit() API.
        [..]
        (@) The specific SMARTCARD interrupts (Transmission complete interrupt,
             RXNE interrupt and Error Interrupts) will be managed using the macros
             __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.

    [..]
    [..] Three operation modes are available within this driver :

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
       (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()

     *** Interrupt mode IO operation ***
     ===================================
     [..]
       (+) Send an amount of data in non-blocking mode using HAL_SMARTCARD_Transmit_IT()
       (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
       (+) Receive an amount of data in non-blocking mode using HAL_SMARTCARD_Receive_IT()
       (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
       (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()

     *** DMA mode IO operation ***
     ==============================
     [..]
       (+) Send an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
       (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
       (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
       (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
       (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()

     *** SMARTCARD HAL driver macros list ***
     ========================================
     [..]
       Below the list of most used macros in SMARTCARD HAL driver.

       (+) __HAL_SMARTCARD_GET_FLAG : Check whether or not the specified SMARTCARD flag is set
       (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
       (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
       (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
       (+) __HAL_SMARTCARD_GET_IT_SOURCE: Check whether or not the specified SMARTCARD interrupt is enabled

     [..]
       (@) You can refer to the SMARTCARD HAL driver header file for more useful macros

    ##### Callback registration #####
    ==================================

    [..]
    The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS when set to 1
    allows the user to configure dynamically the driver callbacks.

    [..]
    Use Function @ref HAL_SMARTCARD_RegisterCallback() to register a user callback.
    Function @ref HAL_SMARTCARD_RegisterCallback() allows to register following callbacks:
    (+) TxCpltCallback            : Tx Complete Callback.
    (+) RxCpltCallback            : Rx Complete Callback.
    (+) ErrorCallback             : Error Callback.
    (+) AbortCpltCallback         : Abort Complete Callback.
    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
    (+) MspInitCallback           : SMARTCARD MspInit.
    (+) MspDeInitCallback         : SMARTCARD MspDeInit.
    This function takes as parameters the HAL peripheral handle, the Callback ID
    and a pointer to the user callback function.

    [..]
    Use function @ref HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default
    weak (surcharged) function.
    @ref HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle,
    and the Callback ID.
    This function allows to reset following callbacks:
    (+) TxCpltCallback            : Tx Complete Callback.
    (+) RxCpltCallback            : Rx Complete Callback.
    (+) ErrorCallback             : Error Callback.
    (+) AbortCpltCallback         : Abort Complete Callback.
    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
    (+) MspInitCallback           : SMARTCARD MspInit.
    (+) MspDeInitCallback         : SMARTCARD MspDeInit.

    [..]
    By default, after the @ref HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET
    all callbacks are set to the corresponding weak (surcharged) functions:
    examples @ref HAL_SMARTCARD_TxCpltCallback(), @ref HAL_SMARTCARD_RxCpltCallback().
    Exception done for MspInit and MspDeInit functions that are respectively
    reset to the legacy weak (surcharged) functions in the @ref HAL_SMARTCARD_Init()
    and @ref HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand).
    If not, MspInit or MspDeInit are not null, the @ref HAL_SMARTCARD_Init() and @ref HAL_SMARTCARD_DeInit()
    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).

    [..]
    Callbacks can be registered/unregistered in HAL_SMARTCARD_STATE_READY state only.
    Exception done MspInit/MspDeInit that can be registered/unregistered
    in HAL_SMARTCARD_STATE_READY or HAL_SMARTCARD_STATE_RESET state, thus registered (user)
    MspInit/DeInit callbacks can be used during the Init/DeInit.
    In that case first register the MspInit/MspDeInit user callbacks
    using @ref HAL_SMARTCARD_RegisterCallback() before calling @ref HAL_SMARTCARD_DeInit()
    or @ref HAL_SMARTCARD_Init() function.

    [..]
    When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or
    not defined, the callback registration feature is not available
    and weak (surcharged) callbacks are used.
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_smartcard.c.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_smartcard_ex.c File Reference

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  • STM32WBxx_HAL_Driver
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Defines | Functions
stm32wbxx_hal_smartcard_ex.c File Reference

SMARTCARD HAL module driver. This file provides extended firmware functions to manage the following functionalities of the SmartCard. + Initialization and de-initialization functions + Peripheral Control functions. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Defines

#define | RX_FIFO_DEPTH 8U
#define | TX_FIFO_DEPTH 8U

Functions

static void | SMARTCARDEx_SetNbDataToProcess (SMARTCARD_HandleTypeDef *hsmartcard)
Calculate the number of data to process in RX/TX ISR.
void | HAL_SMARTCARDEx_BlockLength_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
Update on the fly the SMARTCARD block length in RTOR register.
void | HAL_SMARTCARDEx_TimeOut_Config (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
Update on the fly the receiver timeout value in RTOR register.
HAL_StatusTypeDef | HAL_SMARTCARDEx_EnableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Enable the SMARTCARD receiver timeout feature.
HAL_StatusTypeDef | HAL_SMARTCARDEx_DisableReceiverTimeOut (SMARTCARD_HandleTypeDef *hsmartcard)
Disable the SMARTCARD receiver timeout feature.
__weak void | HAL_SMARTCARDEx_RxFifoFullCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD RX Fifo full callback.
__weak void | HAL_SMARTCARDEx_TxFifoEmptyCallback (SMARTCARD_HandleTypeDef *hsmartcard)
SMARTCARD TX Fifo empty callback.
HAL_StatusTypeDef | HAL_SMARTCARDEx_EnableFifoMode (SMARTCARD_HandleTypeDef *hsmartcard)
Enable the FIFO mode.
HAL_StatusTypeDef | HAL_SMARTCARDEx_DisableFifoMode (SMARTCARD_HandleTypeDef *hsmartcard)
Disable the FIFO mode.
HAL_StatusTypeDef | HAL_SMARTCARDEx_SetTxFifoThreshold (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
Set the TXFIFO threshold.
HAL_StatusTypeDef | HAL_SMARTCARDEx_SetRxFifoThreshold (SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
Set the RXFIFO threshold.

Detailed Description

SMARTCARD HAL module driver. This file provides extended firmware functions to manage the following functionalities of the SmartCard. + Initialization and de-initialization functions + Peripheral Control functions.

Author:
MCD Application Team
  =============================================================================
               ##### SMARTCARD peripheral extended features  #####
  =============================================================================
  [..]
  The Extended SMARTCARD HAL driver can be used as follows:

    (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(),
        then program SMARTCARD advanced features if required (TX/RX pins swap, TimeOut,
        auto-retry counter,...) in the hsmartcard AdvancedInit structure.

    (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.

        -@- When SMARTCARD operates in FIFO mode, FIFO mode must be enabled prior
            starting RX/TX transfers. Also RX/TX FIFO thresholds must be
            configured prior starting RX/TX transfers.
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_smartcard_ex.c.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_smbus.c File Reference

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Defines | Functions
stm32wbxx_hal_smbus.c File Reference

SMBUS HAL module driver. This file provides firmware functions to manage the following functionalities of the System Management Bus (SMBus) peripheral, based on I2C principles of operation : + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Defines

#define | TIMING_CLEAR_MASK (0xF0FFFFFFUL)
#define | HAL_TIMEOUT_ADDR (10000U)
#define | HAL_TIMEOUT_BUSY (25U)
#define | HAL_TIMEOUT_DIR (25U)
#define | HAL_TIMEOUT_RXNE (25U)
#define | HAL_TIMEOUT_STOPF (25U)
#define | HAL_TIMEOUT_TC (25U)
#define | HAL_TIMEOUT_TCR (25U)
#define | HAL_TIMEOUT_TXIS (25U)
#define | MAX_NBYTE_SIZE 255U

Functions

static HAL_StatusTypeDef | SMBUS_WaitOnFlagUntilTimeout (struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
Handle SMBUS Communication Timeout.
static void | SMBUS_Enable_IRQ (struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
Manage the enabling of Interrupts.
static void | SMBUS_Disable_IRQ (struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
Manage the disabling of Interrupts.
static HAL_StatusTypeDef | SMBUS_Master_ISR (struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
static HAL_StatusTypeDef | SMBUS_Slave_ISR (struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
static void | SMBUS_ConvertOtherXferOptions (struct __SMBUS_HandleTypeDef *hsmbus)
Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions.
static void | SMBUS_ITErrorHandler (struct __SMBUS_HandleTypeDef *hsmbus)
SMBUS interrupts error handler.
static void | SMBUS_TransferConfig (struct __SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
HAL_StatusTypeDef | HAL_SMBUS_Init (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS according to the specified parameters in the SMBUS_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS peripheral.
__weak void | HAL_SMBUS_MspInit (SMBUS_HandleTypeDef *hsmbus)
Initialize the SMBUS MSP.
__weak void | HAL_SMBUS_MspDeInit (SMBUS_HandleTypeDef *hsmbus)
DeInitialize the SMBUS MSP.
HAL_StatusTypeDef | HAL_SMBUS_ConfigAnalogFilter (SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter)
Configure Analog noise filter.
HAL_StatusTypeDef | HAL_SMBUS_ConfigDigitalFilter (SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter)
Configure Digital noise filter.
HAL_StatusTypeDef | HAL_SMBUS_RegisterCallback (SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback)
Register a User SMBUS Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_UnRegisterCallback (SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID)
Unregister an SMBUS Callback SMBUS callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_RegisterAddrCallback (SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback)
Register the Slave Address Match SMBUS Callback To be used instead of the weak HAL_SMBUS_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_UnRegisterAddrCallback (SMBUS_HandleTypeDef *hsmbus)
UnRegister the Slave Address Match SMBUS Callback Info Ready SMBUS Callback is redirected to the weak HAL_SMBUS_AddrCallback() predefined callback.
HAL_StatusTypeDef | HAL_SMBUS_Master_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Master_Abort_IT (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
Abort a master/host SMBUS process communication with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Transmit_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_Slave_Receive_IT (SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableListen_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_EnableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Enable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_DisableAlert_IT (SMBUS_HandleTypeDef *hsmbus)
Disable the SMBUS alert mode with Interrupt.
HAL_StatusTypeDef | HAL_SMBUS_IsDeviceReady (SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Check if target device is ready for communication.
void | HAL_SMBUS_EV_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS event interrupt request.
void | HAL_SMBUS_ER_IRQHandler (SMBUS_HandleTypeDef *hsmbus)
Handle SMBUS error interrupt request.
__weak void | HAL_SMBUS_MasterTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Tx Transfer completed callback.
__weak void | HAL_SMBUS_MasterRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Master Rx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveTxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Tx Transfer completed callback.
__weak void | HAL_SMBUS_SlaveRxCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Slave Rx Transfer completed callback.
__weak void | HAL_SMBUS_AddrCallback (SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_SMBUS_ListenCpltCallback (SMBUS_HandleTypeDef *hsmbus)
Listen Complete callback.
__weak void | HAL_SMBUS_ErrorCallback (SMBUS_HandleTypeDef *hsmbus)
SMBUS error callback.
uint32_t | HAL_SMBUS_GetState (SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS handle state.
uint32_t | HAL_SMBUS_GetError (SMBUS_HandleTypeDef *hsmbus)
Return the SMBUS error code.

Detailed Description

SMBUS HAL module driver. This file provides firmware functions to manage the following functionalities of the System Management Bus (SMBus) peripheral, based on I2C principles of operation : + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
    The SMBUS HAL driver can be used as follows:

    (#) Declare a SMBUS_HandleTypeDef handle structure, for example:
        SMBUS_HandleTypeDef  hsmbus;

    (#)Initialize the SMBUS low level resources by implementing the @ref HAL_SMBUS_MspInit() API:
        (##) Enable the SMBUSx interface clock
        (##) SMBUS pins configuration
            (+++) Enable the clock for the SMBUS GPIOs
            (+++) Configure SMBUS pins as alternate function open-drain
        (##) NVIC configuration if you need to use interrupt process
            (+++) Configure the SMBUSx interrupt priority
            (+++) Enable the NVIC SMBUS IRQ Channel

    (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing mode,
        Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode,
        Peripheral mode and Packet Error Check mode in the hsmbus Init structure.

    (#) Initialize the SMBUS registers by calling the @ref HAL_SMBUS_Init() API:
        (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
             by calling the customized @ref HAL_SMBUS_MspInit(&hsmbus) API.

    (#) To check if target device is ready for communication, use the function @ref HAL_SMBUS_IsDeviceReady()

    (#) For SMBUS IO operations, only one mode of operations is available within this driver

    *** Interrupt mode IO operation ***
    ===================================
    [..]
      (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Master_Transmit_IT()
      (++) At transmission end of transfer @ref HAL_SMBUS_MasterTxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_SMBUS_MasterTxCpltCallback()
      (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Master_Receive_IT()
      (++) At reception end of transfer @ref HAL_SMBUS_MasterRxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_SMBUS_MasterRxCpltCallback()
      (+) Abort a master/host SMBUS process communication with Interrupt using @ref HAL_SMBUS_Master_Abort_IT()
      (++) The associated previous transfer callback is called at the end of abort process
      (++) mean @ref HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
      (++) mean @ref HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
      (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode
           using @ref HAL_SMBUS_EnableListen_IT() @ref HAL_SMBUS_DisableListen_IT()
      (++) When address slave/device SMBUS match, @ref HAL_SMBUS_AddrCallback() is executed and user can
           add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read).
      (++) At Listen mode end @ref HAL_SMBUS_ListenCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_SMBUS_ListenCpltCallback()
      (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Slave_Transmit_IT()
      (++) At transmission end of transfer @ref HAL_SMBUS_SlaveTxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_SMBUS_SlaveTxCpltCallback()
      (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Slave_Receive_IT()
      (++) At reception end of transfer @ref HAL_SMBUS_SlaveRxCpltCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_SMBUS_SlaveRxCpltCallback()
      (+) Enable/Disable the SMBUS alert mode using @ref HAL_SMBUS_EnableAlert_IT() @ref HAL_SMBUS_DisableAlert_IT()
      (++) When SMBUS Alert is generated @ref HAL_SMBUS_ErrorCallback() is executed and user can
           add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback()
           to check the Alert Error Code using function @ref HAL_SMBUS_GetError()
      (+) Get HAL state machine or error values using @ref HAL_SMBUS_GetState() or @ref HAL_SMBUS_GetError()
      (+) In case of transfer Error, @ref HAL_SMBUS_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback()
           to check the Error Code using function @ref HAL_SMBUS_GetError()

     *** SMBUS HAL driver macros list ***
     ==================================
     [..]
       Below the list of most used macros in SMBUS HAL driver.

      (+) @ref __HAL_SMBUS_ENABLE:      Enable the SMBUS peripheral
      (+) @ref __HAL_SMBUS_DISABLE:     Disable the SMBUS peripheral
      (+) @ref __HAL_SMBUS_GET_FLAG:    Check whether the specified SMBUS flag is set or not
      (+) @ref __HAL_SMBUS_CLEAR_FLAG:  Clear the specified SMBUS pending flag
      (+) @ref __HAL_SMBUS_ENABLE_IT:   Enable the specified SMBUS interrupt
      (+) @ref __HAL_SMBUS_DISABLE_IT:  Disable the specified SMBUS interrupt

     *** Callback registration ***
     =============================================
    [..]
     The compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS when set to 1
     allows the user to configure dynamically the driver callbacks.
     Use Functions @ref HAL_SMBUS_RegisterCallback() or @ref HAL_SMBUS_RegisterAddrCallback()
     to register an interrupt callback.
    [..]
     Function @ref HAL_SMBUS_RegisterCallback() allows to register following callbacks:
       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
       (+) ListenCpltCallback   : callback for end of listen mode.
       (+) ErrorCallback        : callback for error detection.
       (+) MspInitCallback      : callback for Msp Init.
       (+) MspDeInitCallback    : callback for Msp DeInit.
     This function takes as parameters the HAL peripheral handle, the Callback ID
     and a pointer to the user callback function.
    [..]
     For specific callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_RegisterAddrCallback.
    [..]
     Use function @ref HAL_SMBUS_UnRegisterCallback to reset a callback to the default
     weak function.
     @ref HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle,
     and the Callback ID.
     This function allows to reset following callbacks:
       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
       (+) ListenCpltCallback   : callback for end of listen mode.
       (+) ErrorCallback        : callback for error detection.
       (+) MspInitCallback      : callback for Msp Init.
       (+) MspDeInitCallback    : callback for Msp DeInit.
    [..]
     For callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_UnRegisterAddrCallback.
    [..]
     By default, after the @ref HAL_SMBUS_Init() and when the state is @ref HAL_I2C_STATE_RESET
     all callbacks are set to the corresponding weak functions:
     examples @ref HAL_SMBUS_MasterTxCpltCallback(), @ref HAL_SMBUS_MasterRxCpltCallback().
     Exception done for MspInit and MspDeInit functions that are
     reset to the legacy weak functions in the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit() only when
     these callbacks are null (not registered beforehand).
     If MspInit or MspDeInit are not null, the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit()
     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
    [..]
     Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
     Exception done MspInit/MspDeInit functions that can be registered/unregistered
     in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
     Then, the user first registers the MspInit/MspDeInit user callbacks
     using @ref HAL_SMBUS_RegisterCallback() before calling @ref HAL_SMBUS_DeInit()
     or @ref HAL_SMBUS_Init() function.
    [..]
     When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or
     not defined, the callback registration feature is not available and all callbacks
     are set to the corresponding weak functions.

     [..]
       (@) You can refer to the SMBUS HAL driver header file for more useful macros
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_smbus.c.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_spi.c File Reference

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Defines | Functions
stm32wbxx_hal_spi.c File Reference

SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Defines

#define | SPI_DEFAULT_TIMEOUT 100U

Functions

static void | SPI_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit process complete callback.
static void | SPI_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI receive process complete callback.
static void | SPI_DMATransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit receive process complete callback.
static void | SPI_DMAHalfTransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI half transmit process complete callback.
static void | SPI_DMAHalfReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI half receive process complete callback.
static void | SPI_DMAHalfTransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI half transmit receive process complete callback.
static void | SPI_DMAError (DMA_HandleTypeDef *hdma)
DMA SPI communication error callback.
static void | SPI_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA SPI communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | SPI_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SPI Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | SPI_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SPI Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static HAL_StatusTypeDef | SPI_WaitFlagStateUntilTimeout (SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, uint32_t Timeout, uint32_t Tickstart)
Handle SPI Communication Timeout.
static HAL_StatusTypeDef | SPI_WaitFifoStateUntilTimeout (SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
Handle SPI FIFO Communication Timeout.
static void | SPI_TxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Handle the data 8-bit transmit in Interrupt mode.
static void | SPI_TxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Handle the data 16-bit transmit in Interrupt mode.
static void | SPI_RxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Manage the receive 8-bit in Interrupt context.
static void | SPI_RxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Manage the 16-bit receive in Interrupt context.
static void | SPI_2linesRxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Rx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesTxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Tx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesTxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Tx 16-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesRxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Rx 16-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_RxISR_8BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 8-bit receive in Interrupt context.
static void | SPI_RxISR_16BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 16-bit receive in Interrupt context.
static void | SPI_2linesRxISR_8BITCRC (struct __SPI_HandleTypeDef *hspi)
Rx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesRxISR_16BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
static void | SPI_AbortRx_ISR (SPI_HandleTypeDef *hspi)
Handle abort a Rx transaction.
static void | SPI_AbortTx_ISR (SPI_HandleTypeDef *hspi)
Handle abort a Tx or Rx/Tx transaction.
static void | SPI_CloseRxTx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the RXTX transaction.
static void | SPI_CloseRx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the RX transaction.
static void | SPI_CloseTx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the TX transaction.
static HAL_StatusTypeDef | SPI_EndRxTransaction (SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
Handle the check of the RX transaction complete.
static HAL_StatusTypeDef | SPI_EndRxTxTransaction (SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
Handle the check of the RXTX or TX transaction complete.
HAL_StatusTypeDef | HAL_SPI_Init (SPI_HandleTypeDef *hspi)
Initialize the SPI according to the specified parameters in the SPI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SPI_DeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI peripheral.
__weak void | HAL_SPI_MspInit (SPI_HandleTypeDef *hspi)
Initialize the SPI MSP.
__weak void | HAL_SPI_MspDeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI MSP.
HAL_StatusTypeDef | HAL_SPI_RegisterCallback (SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback)
Register a User SPI Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_SPI_UnRegisterCallback (SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
Unregister an SPI Callback SPI callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_SPI_Transmit (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Receive (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Transmit and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Transmit_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Receive_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_IT (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Transmit_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Receive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Abort (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (blocking mode).
HAL_StatusTypeDef | HAL_SPI_Abort_IT (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_SPI_DMAPause (SPI_HandleTypeDef *hspi)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAResume (SPI_HandleTypeDef *hspi)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAStop (SPI_HandleTypeDef *hspi)
Stop the DMA Transfer.
void | HAL_SPI_IRQHandler (SPI_HandleTypeDef *hspi)
Handle SPI interrupt request.
__weak void | HAL_SPI_TxCpltCallback (SPI_HandleTypeDef *hspi)
Tx Transfer completed callback.
__weak void | HAL_SPI_RxCpltCallback (SPI_HandleTypeDef *hspi)
Rx Transfer completed callback.
__weak void | HAL_SPI_TxRxCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Transfer completed callback.
__weak void | HAL_SPI_TxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx Half Transfer completed callback.
__weak void | HAL_SPI_RxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Rx Half Transfer completed callback.
__weak void | HAL_SPI_TxRxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Half Transfer callback.
__weak void | HAL_SPI_ErrorCallback (SPI_HandleTypeDef *hspi)
SPI error callback.
__weak void | HAL_SPI_AbortCpltCallback (SPI_HandleTypeDef *hspi)
SPI Abort Complete callback.
HAL_SPI_StateTypeDef | HAL_SPI_GetState (SPI_HandleTypeDef *hspi)
Return the SPI handle state.
uint32_t | HAL_SPI_GetError (SPI_HandleTypeDef *hspi)
Return the SPI error code.

Detailed Description

SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
      The SPI HAL driver can be used as follows:

      (#) Declare a SPI_HandleTypeDef handle structure, for example:
          SPI_HandleTypeDef  hspi;

      (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
          (##) Enable the SPIx interface clock
          (##) SPI pins configuration
              (+++) Enable the clock for the SPI GPIOs
              (+++) Configure these SPI pins as alternate function push-pull
          (##) NVIC configuration if you need to use interrupt process
              (+++) Configure the SPIx interrupt priority
              (+++) Enable the NVIC SPI IRQ handle
          (##) DMA Configuration if you need to use DMA process
              (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
              (+++) Enable the DMAx clock
              (+++) Configure the DMA handle parameters
              (+++) Configure the DMA Tx or Rx Stream/Channel
              (+++) Associate the initialized hdma_tx(or _rx)  handle to the hspi DMA Tx or Rx handle
              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel

      (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
          management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.

      (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
              by calling the customized HAL_SPI_MspInit() API.
     [..]
       Circular mode restriction:
      (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
          (##) Master 2Lines RxOnly
          (##) Master 1Line Rx
      (#) The CRC feature is not managed when the DMA circular mode is enabled
      (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
          the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
     [..]
       Master Receive mode restriction:
      (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or
          bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
          does not initiate a new transfer the following procedure has to be respected:
          (##) HAL_SPI_DeInit()
          (##) HAL_SPI_Init()
     [..]
       Callback registration:

      (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
          allows the user to configure dynamically the driver callbacks.
          Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.

          Function HAL_SPI_RegisterCallback() allows to register following callbacks:
            (++) TxCpltCallback        : SPI Tx Completed callback
            (++) RxCpltCallback        : SPI Rx Completed callback
            (++) TxRxCpltCallback      : SPI TxRx Completed callback
            (++) TxHalfCpltCallback    : SPI Tx Half Completed callback
            (++) RxHalfCpltCallback    : SPI Rx Half Completed callback
            (++) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback
            (++) ErrorCallback         : SPI Error callback
            (++) AbortCpltCallback     : SPI Abort callback
            (++) MspInitCallback       : SPI Msp Init callback
            (++) MspDeInitCallback     : SPI Msp DeInit callback
          This function takes as parameters the HAL peripheral handle, the Callback ID
          and a pointer to the user callback function.

      (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
          weak function.
          HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
          and the Callback ID.
          This function allows to reset following callbacks:
            (++) TxCpltCallback        : SPI Tx Completed callback
            (++) RxCpltCallback        : SPI Rx Completed callback
            (++) TxRxCpltCallback      : SPI TxRx Completed callback
            (++) TxHalfCpltCallback    : SPI Tx Half Completed callback
            (++) RxHalfCpltCallback    : SPI Rx Half Completed callback
            (++) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback
            (++) ErrorCallback         : SPI Error callback
            (++) AbortCpltCallback     : SPI Abort callback
            (++) MspInitCallback       : SPI Msp Init callback
            (++) MspDeInitCallback     : SPI Msp DeInit callback

       [..]
       By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
       all callbacks are set to the corresponding weak functions:
       examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
       Exception done for MspInit and MspDeInit functions that are
       reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
       these callbacks are null (not registered beforehand).
       If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
       keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.

       [..]
       Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
       Exception done MspInit/MspDeInit functions that can be registered/unregistered
       in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
       thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
       Then, the user first registers the MspInit/MspDeInit user callbacks
       using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
       or HAL_SPI_Init() function.

       [..]
       When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
       not defined, the callback registering feature is not available
       and weak (surcharged) callbacks are used.

     [..]
       Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,
       the following table resume the max SPI frequency reached with data size 8bits/16bits,
         according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.

Additional table :

DataSize = SPI_DATASIZE_8BIT: +----------------------------------------------------------------------------------------------+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | | Process | Tranfert mode |---------------------|----------------------|----------------------| | | | Master | Slave | Master | Slave | Master | Slave | |==============================================================================================| | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | | X |----------------|----------|----------|-----------|----------|-----------|----------| | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA | | R |----------------|----------|----------|-----------|----------|-----------|----------| | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | |=========|================|==========|==========|===========|==========|===========|==========| | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | | |----------------|----------|----------|-----------|----------|-----------|----------| | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 | | X |----------------|----------|----------|-----------|----------|-----------|----------| | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 | |=========|================|==========|==========|===========|==========|===========|==========| | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 | | |----------------|----------|----------|-----------|----------|-----------|----------| | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 | | X |----------------|----------|----------|-----------|----------|-----------|----------| | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 | +----------------------------------------------------------------------------------------------+

DataSize = SPI_DATASIZE_16BIT: +----------------------------------------------------------------------------------------------+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | | Process | Tranfert mode |---------------------|----------------------|----------------------| | | | Master | Slave | Master | Slave | Master | Slave | |==============================================================================================| | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | | X |----------------|----------|----------|-----------|----------|-----------|----------| | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA | | R |----------------|----------|----------|-----------|----------|-----------|----------| | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | |=========|================|==========|==========|===========|==========|===========|==========| | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | | |----------------|----------|----------|-----------|----------|-----------|----------| | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 | | X |----------------|----------|----------|-----------|----------|-----------|----------| | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 | |=========|================|==========|==========|===========|==========|===========|==========| | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 | | |----------------|----------|----------|-----------|----------|-----------|----------| | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 | | X |----------------|----------|----------|-----------|----------|-----------|----------| | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 | +----------------------------------------------------------------------------------------------+

Note:
The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits), SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
(#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_spi.c.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_spi_ex.c File Reference

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Defines | Functions
stm32wbxx_hal_spi_ex.c File Reference

Extended SPI HAL module driver. This file provides firmware functions to manage the following SPI peripheral extended functionalities : + IO operation functions. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Defines

#define | SPI_FIFO_SIZE 4UL

Functions

HAL_StatusTypeDef | HAL_SPIEx_FlushRxFifo (SPI_HandleTypeDef *hspi)
Flush the RX fifo.

Detailed Description

Extended SPI HAL module driver. This file provides firmware functions to manage the following SPI peripheral extended functionalities : + IO operation functions.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_spi_ex.c.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_tim.c File Reference

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stm32wbxx_hal_tim.c File Reference

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + TIM Time Base Initialization + TIM Time Base Start + TIM Time Base Start Interruption + TIM Time Base Start DMA + TIM Output Compare/PWM Initialization + TIM Output Compare/PWM Channel Configuration + TIM Output Compare/PWM Start + TIM Output Compare/PWM Start Interruption + TIM Output Compare/PWM Start DMA + TIM Input Capture Initialization + TIM Input Capture Channel Configuration + TIM Input Capture Start + TIM Input Capture Start Interruption + TIM Input Capture Start DMA + TIM One Pulse Initialization + TIM One Pulse Channel Configuration + TIM One Pulse Start + TIM Encoder Interface Initialization + TIM Encoder Interface Start + TIM Encoder Interface Start Interruption + TIM Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + TIM OCRef clear configuration + TIM External Clock configuration. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Defines

#define | TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL

Functions

static void | TIM_OC1_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 1 configuration.
static void | TIM_OC3_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 3 configuration.
static void | TIM_OC4_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 4 configuration.
static void | TIM_OC5_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 5 configuration.
static void | TIM_OC6_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 6 configuration.
static void | TIM_TI1_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI1.
static void | TIM_TI2_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI2 as Input.
static void | TIM_TI2_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI2.
static void | TIM_TI3_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI3 as Input.
static void | TIM_TI4_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI4 as Input.
static void | TIM_ITRx_SetConfig (TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
Selects the Input Trigger source.
static void | TIM_DMAPeriodElapsedCplt (DMA_HandleTypeDef *hdma)
TIM DMA Period Elapse complete callback.
static void | TIM_DMAPeriodElapsedHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Period Elapse half complete callback.
static void | TIM_DMATriggerCplt (DMA_HandleTypeDef *hdma)
TIM DMA Trigger callback.
static void | TIM_DMATriggerHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Trigger half complete callback.
static HAL_StatusTypeDef | TIM_SlaveTimer_SetConfig (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Slave Timer configuration function.
HAL_StatusTypeDef | HAL_TIM_Base_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_Base_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Base peripheral.
__weak void | HAL_TIM_Base_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Base MSP.
__weak void | HAL_TIM_Base_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Base MSP.
HAL_StatusTypeDef | HAL_TIM_Base_Start (TIM_HandleTypeDef *htim)
Starts the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_OC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_OC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare MSP.
__weak void | HAL_TIM_OC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Output Compare MSP.
HAL_StatusTypeDef | HAL_TIM_OC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Init (TIM_HandleTypeDef *htim)
Initializes the TIM PWM Time Base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_PWM_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_PWM_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM PWM MSP.
__weak void | HAL_TIM_PWM_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM PWM MSP.
HAL_StatusTypeDef | HAL_TIM_PWM_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_IC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_IC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture MSP.
__weak void | HAL_TIM_IC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Input Capture MSP.
HAL_StatusTypeDef | HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Input Capture measurement in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Init (TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
Initializes the TIM One Pulse Time Base according to the specified parameters in the TIM_HandleTypeDef and initializes the associated handle.
HAL_StatusTypeDef | HAL_TIM_OnePulse_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM One Pulse.
__weak void | HAL_TIM_OnePulse_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM One Pulse MSP.
__weak void | HAL_TIM_OnePulse_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM One Pulse MSP.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Init (TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
Initializes the TIM Encoder Interface and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIM_Encoder_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Encoder interface.
__weak void | HAL_TIM_Encoder_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Encoder Interface MSP.
__weak void | HAL_TIM_Encoder_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Encoder Interface MSP.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
Starts the TIM Encoder Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in DMA mode.
void | HAL_TIM_IRQHandler (TIM_HandleTypeDef *htim)
This function handles TIM interrupts requests.
HAL_StatusTypeDef | HAL_TIM_OC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_IC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_PWM_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_OnePulse_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
Initializes the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stops the TIM DMA Burst mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stop the DMA burst reading.
HAL_StatusTypeDef | HAL_TIM_GenerateEvent (TIM_HandleTypeDef *htim, uint32_t EventSource)
Generate a software event.
HAL_StatusTypeDef | HAL_TIM_ConfigOCrefClear (TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel)
Configures the OCRef clear feature.
HAL_StatusTypeDef | HAL_TIM_ConfigClockSource (TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
Configures the clock source to be used.
HAL_StatusTypeDef | HAL_TIM_ConfigTI1Input (TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchro (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchro_IT (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode in interrupt mode.
uint32_t | HAL_TIM_ReadCapturedValue (TIM_HandleTypeDef *htim, uint32_t Channel)
Read the captured value from Capture Compare unit.
__weak void | HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef *htim)
Period elapsed callback in non-blocking mode.
__weak void | HAL_TIM_PeriodElapsedHalfCpltCallback (TIM_HandleTypeDef *htim)
Period elapsed half complete callback in non-blocking mode.
__weak void | HAL_TIM_OC_DelayElapsedCallback (TIM_HandleTypeDef *htim)
Output Compare callback in non-blocking mode.
__weak void | HAL_TIM_IC_CaptureCallback (TIM_HandleTypeDef *htim)
Input Capture callback in non-blocking mode.
__weak void | HAL_TIM_IC_CaptureHalfCpltCallback (TIM_HandleTypeDef *htim)
Input Capture half complete callback in non-blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished callback in non-blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedHalfCpltCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished half complete callback in non-blocking mode.
__weak void | HAL_TIM_TriggerCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection callback in non-blocking mode.
__weak void | HAL_TIM_TriggerHalfCpltCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection half complete callback in non-blocking mode.
__weak void | HAL_TIM_ErrorCallback (TIM_HandleTypeDef *htim)
Timer error callback in non-blocking mode.
HAL_StatusTypeDef | HAL_TIM_RegisterCallback (TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback)
Register a User TIM callback to be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_TIM_UnRegisterCallback (TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
Unregister a TIM callback TIM callback is redirected to the weak predefined callback.
HAL_TIM_StateTypeDef | HAL_TIM_Base_GetState (TIM_HandleTypeDef *htim)
Return the TIM Base handle state.
HAL_TIM_StateTypeDef | HAL_TIM_OC_GetState (TIM_HandleTypeDef *htim)
Return the TIM OC handle state.
HAL_TIM_StateTypeDef | HAL_TIM_PWM_GetState (TIM_HandleTypeDef *htim)
Return the TIM PWM handle state.
HAL_TIM_StateTypeDef | HAL_TIM_IC_GetState (TIM_HandleTypeDef *htim)
Return the TIM Input Capture handle state.
HAL_TIM_StateTypeDef | HAL_TIM_OnePulse_GetState (TIM_HandleTypeDef *htim)
Return the TIM One Pulse Mode handle state.
HAL_TIM_StateTypeDef | HAL_TIM_Encoder_GetState (TIM_HandleTypeDef *htim)
Return the TIM Encoder Mode handle state.
void | TIM_DMAError (DMA_HandleTypeDef *hdma)
TIM DMA error callback.
void | TIM_DMADelayPulseCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse complete callback.
void | TIM_DMADelayPulseHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse half complete callback.
void | TIM_DMACaptureCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture complete callback.
void | TIM_DMACaptureHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture half complete callback.
void | TIM_Base_SetConfig (TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
Time Base configuration.
void | TIM_OC2_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 2 configuration.
void | TIM_TI1_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI1 as Input.
void | TIM_ETR_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
void | TIM_CCxChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
Enables or disables the TIM Capture Compare Channel x.
void | TIM_ResetCallback (TIM_HandleTypeDef *htim)
Reset interrupt callbacks to the legacy weak callbacks.

Detailed Description

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + TIM Time Base Initialization + TIM Time Base Start + TIM Time Base Start Interruption + TIM Time Base Start DMA + TIM Output Compare/PWM Initialization + TIM Output Compare/PWM Channel Configuration + TIM Output Compare/PWM Start + TIM Output Compare/PWM Start Interruption + TIM Output Compare/PWM Start DMA + TIM Input Capture Initialization + TIM Input Capture Channel Configuration + TIM Input Capture Start + TIM Input Capture Start Interruption + TIM Input Capture Start DMA + TIM One Pulse Initialization + TIM One Pulse Channel Configuration + TIM One Pulse Start + TIM Encoder Interface Initialization + TIM Encoder Interface Start + TIM Encoder Interface Start Interruption + TIM Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + TIM OCRef clear configuration + TIM External Clock configuration.

Author:
MCD Application Team
  ==============================================================================
                      ##### TIMER Generic features #####
  ==============================================================================
  [..] The Timer features include:
       (#) 16-bit up, down, up/down auto-reload counter.
       (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
           counter clock frequency either by any factor between 1 and 65536.
       (#) Up to 4 independent channels for:
           (++) Input Capture
           (++) Output Compare
           (++) PWM generation (Edge and Center-aligned Mode)
           (++) One-pulse mode output
       (#) Synchronization circuit to control the timer with external signals and to interconnect
            several timers together.
       (#) Supports incremental encoder for positioning purposes

            ##### How to use this driver #####
  ==============================================================================
    [..]
     (#) Initialize the TIM low level resources by implementing the following functions
         depending on the selected feature:
           (++) Time Base : HAL_TIM_Base_MspInit()
           (++) Input Capture : HAL_TIM_IC_MspInit()
           (++) Output Compare : HAL_TIM_OC_MspInit()
           (++) PWM generation : HAL_TIM_PWM_MspInit()
           (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
           (++) Encoder mode output : HAL_TIM_Encoder_MspInit()

     (#) Initialize the TIM low level resources :
        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
        (##) TIM pins configuration
            (+++) Enable the clock for the TIM GPIOs using the following function:
             __HAL_RCC_GPIOx_CLK_ENABLE();
            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();

     (#) The external Clock can be configured, if needed (the default clock is the
         internal clock from the APBx), using the following function:
         HAL_TIM_ConfigClockSource, the clock configuration should be done before
         any start function.

     (#) Configure the TIM in the desired functioning mode using one of the
       Initialization function of this driver:
       (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
       (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
            Output Compare signal.
       (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
            PWM signal.
       (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
            external signal.
       (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
            in One Pulse Mode.
       (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.

     (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
           (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
           (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
           (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
           (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
           (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
           (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().

     (#) The DMA Burst is managed with the two following functions:
         HAL_TIM_DMABurst_WriteStart()
         HAL_TIM_DMABurst_ReadStart()

    *** Callback registration ***
  =============================================

  [..]
  The compilation define  USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
  allows the user to configure dynamically the driver callbacks.

  [..]
  Use Function @ref HAL_TIM_RegisterCallback() to register a callback.
  @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
  the Callback ID and a pointer to the user callback function.

  [..]
  Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default
  weak function.
  @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
  and the Callback ID.

  [..]
  These functions allow to register/unregister following callbacks:
    (+) Base_MspInitCallback              : TIM Base Msp Init Callback.
    (+) Base_MspDeInitCallback            : TIM Base Msp DeInit Callback.
    (+) IC_MspInitCallback                : TIM IC Msp Init Callback.
    (+) IC_MspDeInitCallback              : TIM IC Msp DeInit Callback.
    (+) OC_MspInitCallback                : TIM OC Msp Init Callback.
    (+) OC_MspDeInitCallback              : TIM OC Msp DeInit Callback.
    (+) PWM_MspInitCallback               : TIM PWM Msp Init Callback.
    (+) PWM_MspDeInitCallback             : TIM PWM Msp DeInit Callback.
    (+) OnePulse_MspInitCallback          : TIM One Pulse Msp Init Callback.
    (+) OnePulse_MspDeInitCallback        : TIM One Pulse Msp DeInit Callback.
    (+) Encoder_MspInitCallback           : TIM Encoder Msp Init Callback.
    (+) Encoder_MspDeInitCallback         : TIM Encoder Msp DeInit Callback.
    (+) HallSensor_MspInitCallback        : TIM Hall Sensor Msp Init Callback.
    (+) HallSensor_MspDeInitCallback      : TIM Hall Sensor Msp DeInit Callback.
    (+) PeriodElapsedCallback             : TIM Period Elapsed Callback.
    (+) PeriodElapsedHalfCpltCallback     : TIM Period Elapsed half complete Callback.
    (+) TriggerCallback                   : TIM Trigger Callback.
    (+) TriggerHalfCpltCallback           : TIM Trigger half complete Callback.
    (+) IC_CaptureCallback                : TIM Input Capture Callback.
    (+) IC_CaptureHalfCpltCallback        : TIM Input Capture half complete Callback.
    (+) OC_DelayElapsedCallback           : TIM Output Compare Delay Elapsed Callback.
    (+) PWM_PulseFinishedCallback         : TIM PWM Pulse Finished Callback.
    (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
    (+) ErrorCallback                     : TIM Error Callback.
    (+) CommutationCallback               : TIM Commutation Callback.
    (+) CommutationHalfCpltCallback       : TIM Commutation half complete Callback.
    (+) BreakCallback                     : TIM Break Callback.
    (+) Break2Callback                    : TIM Break2 Callback.

  [..]
By default, after the Init and when the state is HAL_TIM_STATE_RESET
all interrupt callbacks are set to the corresponding weak functions:
  examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().

  [..]
  Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
  functionalities in the Init / DeInit only when these callbacks are null
  (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
    keep and use the user MspInit / MspDeInit callbacks(registered beforehand)

  [..]
    Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
    Exception done MspInit / MspDeInit that can be registered / unregistered
    in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
    thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
  In that case first register the MspInit/MspDeInit user callbacks
      using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.

  [..]
      When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
      not defined, the callback registration feature is not available and all callbacks
      are set to the corresponding weak functions.
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_tim.c.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_tim_ex.c File Reference

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Defines | Functions
stm32wbxx_hal_tim_ex.c File Reference

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer Extended peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal break and dead time configuration + Time Master and Slave synchronization configuration + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + Time OCRef clear configuration + Timer remapping capabilities configuration. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Defines

#define | TIM_GET_OR_MASK(__INSTANCE__)

Functions

static void | TIM_CCxNChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
Enables or disables the TIM Capture Compare Channel xN.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Init (TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
Initializes the TIM Hall Sensor Interface and initialize the associated handle.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Hall Sensor interface.
__weak void | HAL_TIMEx_HallSensor_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Hall Sensor MSP.
__weak void | HAL_TIMEx_HallSensor_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Hall Sensor MSP.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Hall sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutEvent (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutEvent_IT (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with interrupt.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutEvent_DMA (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with DMA.
HAL_StatusTypeDef | HAL_TIMEx_MasterConfigSynchronization (TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig)
Configures the TIM in master mode.
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakDeadTime (TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakInput (TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
Configures the break input source.
HAL_StatusTypeDef | HAL_TIMEx_RemapConfig (TIM_HandleTypeDef *htim, uint32_t Remap)
Configures the TIMx Remapping input capabilities.
HAL_StatusTypeDef | HAL_TIMEx_GroupChannel5 (TIM_HandleTypeDef *htim, uint32_t Channels)
Group channel 5 and channel 1, 2 or 3.
__weak void | HAL_TIMEx_CommutCallback (TIM_HandleTypeDef *htim)
Hall commutation changed callback in non-blocking mode.
__weak void | HAL_TIMEx_CommutHalfCpltCallback (TIM_HandleTypeDef *htim)
Hall commutation changed half complete callback in non-blocking mode.
__weak void | HAL_TIMEx_BreakCallback (TIM_HandleTypeDef *htim)
Hall Break detection callback in non-blocking mode.
__weak void | HAL_TIMEx_Break2Callback (TIM_HandleTypeDef *htim)
Hall Break2 detection callback in non blocking mode.
HAL_TIM_StateTypeDef | HAL_TIMEx_HallSensor_GetState (TIM_HandleTypeDef *htim)
Return the TIM Hall Sensor interface handle state.
void | TIMEx_DMACommutationCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation callback.
void | TIMEx_DMACommutationHalfCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation half complete callback.

Detailed Description

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer Extended peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal break and dead time configuration + Time Master and Slave synchronization configuration + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + Time OCRef clear configuration + Timer remapping capabilities configuration.

Author:
MCD Application Team
  ==============================================================================
                      ##### TIMER Extended features #####
  ==============================================================================
  [..]
    The Timer Extended features include:
    (#) Complementary outputs with programmable dead-time for :
        (++) Output Compare
        (++) PWM generation (Edge and Center-aligned Mode)
        (++) One-pulse mode output
    (#) Synchronization circuit to control the timer with external signals and to
        interconnect several timers together.
    (#) Break input to put the timer output signals in reset state or in a known state.
    (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
        positioning purposes

            ##### How to use this driver #####
  ==============================================================================
    [..]
     (#) Initialize the TIM low level resources by implementing the following functions
         depending on the selected feature:
           (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()

     (#) Initialize the TIM low level resources :
        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
        (##) TIM pins configuration
            (+++) Enable the clock for the TIM GPIOs using the following function:
              __HAL_RCC_GPIOx_CLK_ENABLE();
            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();

     (#) The external Clock can be configured, if needed (the default clock is the
         internal clock from the APBx), using the following function:
         HAL_TIM_ConfigClockSource, the clock configuration should be done before
         any start function.

     (#) Configure the TIM in the desired functioning mode using one of the
         initialization function of this driver:
          (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
               Timer Hall Sensor Interface and the commutation event with the corresponding
               Interrupt and DMA request if needed (Note that One Timer is used to interface
               with the Hall sensor Interface and another Timer should be used to use
               the commutation event).

     (#) Activate the TIM peripheral using one of the start functions:
           (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
           (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
           (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
           (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_tim_ex.c.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_tsc.c File Reference

  • File List
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  • STM32WBxx_HAL_Driver
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Functions
stm32wbxx_hal_tsc.c File Reference

This file provides firmware functions to manage the following functionalities of the Touch Sensing Controller (TSC) peripheral: + Initialization and De-initialization + Channel IOs, Shield IOs and Sampling IOs configuration + Start and Stop an acquisition + Read acquisition result + Interrupts and flags management. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Functions

static uint32_t | TSC_extract_groups (uint32_t iomask)
Utility function used to set the acquired groups mask.
HAL_StatusTypeDef | HAL_TSC_Init (TSC_HandleTypeDef *htsc)
Initialize the TSC peripheral according to the specified parameters in the TSC_InitTypeDef structure and initialize the associated handle.
HAL_StatusTypeDef | HAL_TSC_DeInit (TSC_HandleTypeDef *htsc)
Deinitialize the TSC peripheral registers to their default reset values.
__weak void | HAL_TSC_MspInit (TSC_HandleTypeDef *htsc)
Initialize the TSC MSP.
__weak void | HAL_TSC_MspDeInit (TSC_HandleTypeDef *htsc)
DeInitialize the TSC MSP.
HAL_StatusTypeDef | HAL_TSC_RegisterCallback (TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID, pTSC_CallbackTypeDef pCallback)
Register a User TSC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_TSC_UnRegisterCallback (TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID)
Unregister an TSC Callback TSC callback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_TSC_Start (TSC_HandleTypeDef *htsc)
Start the acquisition.
HAL_StatusTypeDef | HAL_TSC_Start_IT (TSC_HandleTypeDef *htsc)
Start the acquisition in interrupt mode.
HAL_StatusTypeDef | HAL_TSC_Stop (TSC_HandleTypeDef *htsc)
Stop the acquisition previously launched in polling mode.
HAL_StatusTypeDef | HAL_TSC_Stop_IT (TSC_HandleTypeDef *htsc)
Stop the acquisition previously launched in interrupt mode.
HAL_StatusTypeDef | HAL_TSC_PollForAcquisition (TSC_HandleTypeDef *htsc)
Start acquisition and wait until completion.
TSC_GroupStatusTypeDef | HAL_TSC_GroupGetStatus (TSC_HandleTypeDef *htsc, uint32_t gx_index)
Get the acquisition status for a group.
uint32_t | HAL_TSC_GroupGetValue (TSC_HandleTypeDef *htsc, uint32_t gx_index)
Get the acquisition measure for a group.
HAL_StatusTypeDef | HAL_TSC_IOConfig (TSC_HandleTypeDef *htsc, TSC_IOConfigTypeDef *config)
Configure TSC IOs.
HAL_StatusTypeDef | HAL_TSC_IODischarge (TSC_HandleTypeDef *htsc, FunctionalState choice)
Discharge TSC IOs.
HAL_TSC_StateTypeDef | HAL_TSC_GetState (TSC_HandleTypeDef *htsc)
Return the TSC handle state.
void | HAL_TSC_IRQHandler (TSC_HandleTypeDef *htsc)
Handle TSC interrupt request.
__weak void | HAL_TSC_ConvCpltCallback (TSC_HandleTypeDef *htsc)
Acquisition completed callback in non-blocking mode.
__weak void | HAL_TSC_ErrorCallback (TSC_HandleTypeDef *htsc)
Error callback in non-blocking mode.

Detailed Description

This file provides firmware functions to manage the following functionalities of the Touch Sensing Controller (TSC) peripheral: + Initialization and De-initialization + Channel IOs, Shield IOs and Sampling IOs configuration + Start and Stop an acquisition + Read acquisition result + Interrupts and flags management.

Author:
MCD Application Team
================================================================================
                       ##### TSC specific features #####
================================================================================
  [..]
  (#) Proven and robust surface charge transfer acquisition principle

  (#) Supports up to 3 capacitive sensing channels per group

  (#) Capacitive sensing channels can be acquired in parallel offering a very good
      response time

  (#) Spread spectrum feature to improve system robustness in noisy environments

  (#) Full hardware management of the charge transfer acquisition sequence

  (#) Programmable charge transfer frequency

  (#) Programmable sampling capacitor I/O pin

  (#) Programmable channel I/O pin

  (#) Programmable max count value to avoid long acquisition when a channel is faulty

  (#) Dedicated end of acquisition and max count error flags with interrupt capability

  (#) One sampling capacitor for up to 3 capacitive sensing channels to reduce the system
      components

  (#) Compatible with proximity, touchkey, linear and rotary touch sensor implementation

                          ##### How to use this driver #####
================================================================================
  [..]
    (#) Enable the TSC interface clock using __HAL_RCC_TSC_CLK_ENABLE() macro.

    (#) GPIO pins configuration
      (++) Enable the clock for the TSC GPIOs using __HAL_RCC_GPIOx_CLK_ENABLE() macro.
      (++) Configure the TSC pins used as sampling IOs in alternate function output Open-Drain mode,
           and TSC pins used as channel/shield IOs in alternate function output Push-Pull mode
           using HAL_GPIO_Init() function.

    (#) Interrupts configuration
      (++) Configure the NVIC (if the interrupt model is used) using HAL_NVIC_SetPriority()
           and HAL_NVIC_EnableIRQ() and function.

    (#) TSC configuration
      (++) Configure all TSC parameters and used TSC IOs using HAL_TSC_Init() function.

 [..]   TSC peripheral alternate functions are mapped on AF9.

  *** Acquisition sequence ***
  ===================================
  [..]
    (+) Discharge all IOs using HAL_TSC_IODischarge() function.
    (+) Wait a certain time allowing a good discharge of all capacitors. This delay depends
        of the sampling capacitor and electrodes design.
    (+) Select the channel IOs to be acquired using HAL_TSC_IOConfig() function.
    (+) Launch the acquisition using either HAL_TSC_Start() or HAL_TSC_Start_IT() function.
        If the synchronized mode is selected, the acquisition will start as soon as the signal
        is received on the synchro pin.
    (+) Wait the end of acquisition using either HAL_TSC_PollForAcquisition() or
        HAL_TSC_GetState() function or using WFI instruction for example.
    (+) Check the group acquisition status using HAL_TSC_GroupGetStatus() function.
    (+) Read the acquisition value using HAL_TSC_GroupGetValue() function.

     *** Callback registration ***
     =============================================

  [..]
     The compilation flag USE_HAL_TSC_REGISTER_CALLBACKS when set to 1
     allows the user to configure dynamically the driver callbacks.
     Use Functions @ref HAL_TSC_RegisterCallback() to register an interrupt callback.

  [..]
     Function @ref HAL_TSC_RegisterCallback() allows to register following callbacks:
       (+) ConvCpltCallback   : callback for conversion complete process.
       (+) ErrorCallback      : callback for error detection.
       (+) MspInitCallback    : callback for Msp Init.
       (+) MspDeInitCallback  : callback for Msp DeInit.
  [..]
     This function takes as parameters the HAL peripheral handle, the Callback ID
     and a pointer to the user callback function.

  [..]
     Use function @ref HAL_TSC_UnRegisterCallback to reset a callback to the default
     weak function.
     @ref HAL_TSC_UnRegisterCallback takes as parameters the HAL peripheral handle,
     and the Callback ID.
  [..]
     This function allows to reset following callbacks:
       (+) ConvCpltCallback   : callback for conversion complete process.
       (+) ErrorCallback      : callback for error detection.
       (+) MspInitCallback    : callback for Msp Init.
       (+) MspDeInitCallback  : callback for Msp DeInit.

  [..]
     By default, after the @ref HAL_TSC_Init() and when the state is @ref HAL_TSC_STATE_RESET
     all callbacks are set to the corresponding weak functions:
     examples @ref HAL_TSC_ConvCpltCallback(), @ref HAL_TSC_ErrorCallback().
     Exception done for MspInit and MspDeInit functions that are
     reset to the legacy weak functions in the @ref HAL_TSC_Init()/ @ref HAL_TSC_DeInit() only when
     these callbacks are null (not registered beforehand).
     If MspInit or MspDeInit are not null, the @ref HAL_TSC_Init()/ @ref HAL_TSC_DeInit()
     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.

  [..]
     Callbacks can be registered/unregistered in @ref HAL_TSC_STATE_READY state only.
     Exception done MspInit/MspDeInit functions that can be registered/unregistered
     in @ref HAL_TSC_STATE_READY or @ref HAL_TSC_STATE_RESET state,
     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
     Then, the user first registers the MspInit/MspDeInit user callbacks
     using @ref HAL_TSC_RegisterCallback() before calling @ref HAL_TSC_DeInit()
     or @ref HAL_TSC_Init() function.

  [..]
     When the compilation flag USE_HAL_TSC_REGISTER_CALLBACKS is set to 0 or
     not defined, the callback registration feature is not available and all callbacks
     are set to the corresponding weak functions.

Table 1. IOs for the STM32WBxx devices +--------------------------------+ | IOs | TSC functions | |--------------|-----------------| | PB12 (AF) | TSC_G1_IO1 | | PB13 (AF) | TSC_G1_IO2 | | PB14 (AF) | TSC_G1_IO3 | | PB15 (AF) | TSC_G1_IO4 | |--------------|-----------------| | PB4 (AF) | TSC_G2_IO1 | | PB5 (AF) | TSC_G2_IO2 | | PB6 (AF) | TSC_G2_IO3 | | PB7 (AF) | TSC_G2_IO4 | |--------------|-----------------| | PA15 (AF) | TSC_G3_IO1 | | PC10 (AF) | TSC_G3_IO2 | | PC11 (AF) | TSC_G3_IO3 | | PC12 (AF) | TSC_G3_IO4 | |--------------|-----------------| | PC6 (AF) | TSC_G4_IO1 | | PC7 (AF) | TSC_G4_IO2 | | PC8 (AF) | TSC_G4_IO3 | | PC9 (AF) | TSC_G4_IO4 | |--------------|-----------------| | PD4 (AF) | TSC_G5_IO1 | | PD5 (AF) | TSC_G5_IO2 | | PD6 (AF) | TSC_G5_IO3 | | PD7 (AF) | TSC_G5_IO4 | |--------------|-----------------| | PD10 (AF) | TSC_G6_IO1 | | PD11 (AF) | TSC_G6_IO2 | | PD12 (AF) | TSC_G6_IO3 | | PD13 (AF) | TSC_G6_IO4 | |--------------|-----------------| | PE2 (AF) | TSC_G7_IO1 | | PE1 (AF) | TSC_G7_IO2 | | PE0 (AF) | TSC_G7_IO3 | | PB9 (AF) | TSC_G7_IO4 | |--------------|-----------------| | PB10 (AF) | TSC_SYNC | | PD2 (AF) | | +--------------------------------+

Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_tsc.c.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_uart.c File Reference

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Defines | Functions
stm32wbxx_hal_uart.c File Reference

UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Defines

#define | USART_CR1_FIELDS
#define | USART_CR3_FIELDS
#define | LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */
#define | LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */
#define | UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */
#define | UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */

Functions

static void | UART_EndTxTransfer (UART_HandleTypeDef *huart)
End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
static void | UART_EndRxTransfer (UART_HandleTypeDef *huart)
End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
static void | UART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process complete callback.
static void | UART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process complete callback.
static void | UART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process half complete callback.
static void | UART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process half complete callback.
static void | UART_DMAError (DMA_HandleTypeDef *hdma)
DMA UART communication error callback.
static void | UART_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA UART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | UART_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | UART_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | UART_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Tx communication abort callback, when initiated by user by a call to HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | UART_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Rx communication abort callback, when initiated by user by a call to HAL_UART_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static void | UART_TxISR_8BIT (UART_HandleTypeDef *huart)
TX interrrupt handler for 7 or 8 bits data word length .
static void | UART_TxISR_16BIT (UART_HandleTypeDef *huart)
TX interrrupt handler for 9 bits data word length.
static void | UART_TxISR_8BIT_FIFOEN (UART_HandleTypeDef *huart)
TX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
static void | UART_TxISR_16BIT_FIFOEN (UART_HandleTypeDef *huart)
TX interrrupt handler for 9 bits data word length and FIFO mode is enabled.
static void | UART_EndTransmit_IT (UART_HandleTypeDef *huart)
Wrap up transmission in non-blocking mode.
static void | UART_RxISR_8BIT (UART_HandleTypeDef *huart)
RX interrrupt handler for 7 or 8 bits data word length .
static void | UART_RxISR_16BIT (UART_HandleTypeDef *huart)
RX interrrupt handler for 9 bits data word length .
static void | UART_RxISR_8BIT_FIFOEN (UART_HandleTypeDef *huart)
RX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
static void | UART_RxISR_16BIT_FIFOEN (UART_HandleTypeDef *huart)
RX interrrupt handler for 9 bits data word length and FIFO mode is enabled.
HAL_StatusTypeDef | HAL_UART_Init (UART_HandleTypeDef *huart)
Initialize the UART mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_HalfDuplex_Init (UART_HandleTypeDef *huart)
Initialize the half-duplex mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_LIN_Init (UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
Initialize the LIN mode according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_MultiProcessor_Init (UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
Initialize the multiprocessor mode according to the specified parameters in the UART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_UART_DeInit (UART_HandleTypeDef *huart)
DeInitialize the UART peripheral.
__weak void | HAL_UART_MspInit (UART_HandleTypeDef *huart)
Initialize the UART MSP.
__weak void | HAL_UART_MspDeInit (UART_HandleTypeDef *huart)
DeInitialize the UART MSP.
HAL_StatusTypeDef | HAL_UART_RegisterCallback (UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback)
Register a User UART Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_UART_UnRegisterCallback (UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID)
Unregister an UART Callback UART callaback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_UART_Transmit (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Transmit_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Receive_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_UART_Transmit_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_Receive_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_UART_DMAPause (UART_HandleTypeDef *huart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAResume (UART_HandleTypeDef *huart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAStop (UART_HandleTypeDef *huart)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_Abort (UART_HandleTypeDef *huart)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_Abort_IT (UART_HandleTypeDef *huart)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit_IT (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive_IT (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_UART_IRQHandler (UART_HandleTypeDef *huart)
Handle UART interrupt request.
__weak void | HAL_UART_TxCpltCallback (UART_HandleTypeDef *huart)
Tx Transfer completed callback.
__weak void | HAL_UART_TxHalfCpltCallback (UART_HandleTypeDef *huart)
Tx Half Transfer completed callback.
__weak void | HAL_UART_RxCpltCallback (UART_HandleTypeDef *huart)
Rx Transfer completed callback.
__weak void | HAL_UART_RxHalfCpltCallback (UART_HandleTypeDef *huart)
Rx Half Transfer completed callback.
__weak void | HAL_UART_ErrorCallback (UART_HandleTypeDef *huart)
UART error callback.
__weak void | HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
UART Abort Receive Complete callback.
void | HAL_UART_ReceiverTimeout_Config (UART_HandleTypeDef *huart, uint32_t TimeoutValue)
Update on the fly the receiver timeout value in RTOR register.
HAL_StatusTypeDef | HAL_UART_EnableReceiverTimeout (UART_HandleTypeDef *huart)
Enable the UART receiver timeout feature.
HAL_StatusTypeDef | HAL_UART_DisableReceiverTimeout (UART_HandleTypeDef *huart)
Disable the UART receiver timeout feature.
HAL_StatusTypeDef | HAL_MultiProcessor_EnableMuteMode (UART_HandleTypeDef *huart)
Enable UART in mute mode (does not mean UART enters mute mode; to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
HAL_StatusTypeDef | HAL_MultiProcessor_DisableMuteMode (UART_HandleTypeDef *huart)
Disable UART mute mode (does not mean the UART actually exits mute mode as it may not have been in mute mode at this very moment).
void | HAL_MultiProcessor_EnterMuteMode (UART_HandleTypeDef *huart)
Enter UART mute mode (means UART actually enters mute mode).
HAL_StatusTypeDef | HAL_HalfDuplex_EnableTransmitter (UART_HandleTypeDef *huart)
Enable the UART transmitter and disable the UART receiver.
HAL_StatusTypeDef | HAL_HalfDuplex_EnableReceiver (UART_HandleTypeDef *huart)
Enable the UART receiver and disable the UART transmitter.
HAL_StatusTypeDef | HAL_LIN_SendBreak (UART_HandleTypeDef *huart)
Transmit break characters.
HAL_UART_StateTypeDef | HAL_UART_GetState (UART_HandleTypeDef *huart)
Return the UART handle state.
uint32_t | HAL_UART_GetError (UART_HandleTypeDef *huart)
Return the UART handle error code.
void | UART_InitCallbacksToDefault (UART_HandleTypeDef *huart)
Initialize the callbacks to their default values.
HAL_StatusTypeDef | UART_SetConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral.
void | UART_AdvFeatureConfig (UART_HandleTypeDef *huart)
Configure the UART peripheral advanced features.
HAL_StatusTypeDef | UART_CheckIdleState (UART_HandleTypeDef *huart)
Check the UART Idle State.
HAL_StatusTypeDef | UART_WaitOnFlagUntilTimeout (UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle UART Communication Timeout.

Detailed Description

UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions.

Author:
MCD Application Team
 ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
  [..]
    The UART HAL driver can be used as follows:

    (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
    (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
        (++) Enable the USARTx interface clock.
        (++) UART pins configuration:
            (+++) Enable the clock for the UART GPIOs.
            (+++) Configure these UART pins as alternate function pull-up.
        (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
             and HAL_UART_Receive_IT() APIs):
            (+++) Configure the USARTx interrupt priority.
            (+++) Enable the NVIC USART IRQ handle.
        (++) UART interrupts handling:
              -@@-  The specific UART interrupts (Transmission complete interrupt,
                RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts)
                are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT()
                inside the transmit and receive processes.
        (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
             and HAL_UART_Receive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx channel.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx channel.
            (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.

    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value , Hardware
        flow control and Mode (Receiver/Transmitter) in the huart handle Init structure.

    (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...)
        in the huart handle AdvancedInit structure.

    (#) For the UART asynchronous mode, initialize the UART registers by calling
        the HAL_UART_Init() API.

    (#) For the UART Half duplex mode, initialize the UART registers by calling
        the HAL_HalfDuplex_Init() API.

    (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers
        by calling the HAL_LIN_Init() API.

    (#) For the UART Multiprocessor mode, initialize the UART registers
        by calling the HAL_MultiProcessor_Init() API.

    (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
        by calling the HAL_RS485Ex_Init() API.

    [..]
    (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(),
        also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by
        calling the customized HAL_UART_MspInit() API.

    ##### Callback registration #####
    ==================================

    [..]
    The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1
    allows the user to configure dynamically the driver callbacks.

    [..]
    Use Function @ref HAL_UART_RegisterCallback() to register a user callback.
    Function @ref HAL_UART_RegisterCallback() allows to register following callbacks:
    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
    (+) TxCpltCallback            : Tx Complete Callback.
    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
    (+) RxCpltCallback            : Rx Complete Callback.
    (+) ErrorCallback             : Error Callback.
    (+) AbortCpltCallback         : Abort Complete Callback.
    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
    (+) WakeupCallback            : Wakeup Callback.
    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
    (+) MspInitCallback           : UART MspInit.
    (+) MspDeInitCallback         : UART MspDeInit.
    This function takes as parameters the HAL peripheral handle, the Callback ID
    and a pointer to the user callback function.

    [..]
    Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default
    weak (surcharged) function.
    @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
    and the Callback ID.
    This function allows to reset following callbacks:
    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
    (+) TxCpltCallback            : Tx Complete Callback.
    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
    (+) RxCpltCallback            : Rx Complete Callback.
    (+) ErrorCallback             : Error Callback.
    (+) AbortCpltCallback         : Abort Complete Callback.
    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
    (+) WakeupCallback            : Wakeup Callback.
    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
    (+) MspInitCallback           : UART MspInit.
    (+) MspDeInitCallback         : UART MspDeInit.

    [..]
    By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
    all callbacks are set to the corresponding weak (surcharged) functions:
    examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback().
    Exception done for MspInit and MspDeInit functions that are respectively
    reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init()
    and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
    If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit()
    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).

    [..]
    Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only.
    Exception done MspInit/MspDeInit that can be registered/unregistered
    in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user)
    MspInit/DeInit callbacks can be used during the Init/DeInit.
    In that case first register the MspInit/MspDeInit user callbacks
    using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit()
    or @ref HAL_UART_Init() function.

    [..]
    When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
    not defined, the callback registration feature is not available
    and weak (surcharged) callbacks are used.
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_uart.c.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_uart_ex.c File Reference

  • File List
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  • STM32WBxx_HAL_Driver
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Defines | Functions
stm32wbxx_hal_uart_ex.c File Reference

Extended UART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + Peripheral Control functions. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Defines

#define | RX_FIFO_DEPTH 8U
#define | TX_FIFO_DEPTH 8U

Functions

static void | UARTEx_Wakeup_AddressConfig (UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
Initialize the UART wake-up from stop mode parameters when triggered by address detection.
static void | UARTEx_SetNbDataToProcess (UART_HandleTypeDef *huart)
Calculate the number of data to process in RX/TX ISR.
HAL_StatusTypeDef | HAL_RS485Ex_Init (UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
Initialize the RS485 Driver enable feature according to the specified parameters in the UART_InitTypeDef and creates the associated handle.
__weak void | HAL_UARTEx_WakeupCallback (UART_HandleTypeDef *huart)
UART wakeup from Stop mode callback.
__weak void | HAL_UARTEx_RxFifoFullCallback (UART_HandleTypeDef *huart)
UART RX Fifo full callback.
__weak void | HAL_UARTEx_TxFifoEmptyCallback (UART_HandleTypeDef *huart)
UART TX Fifo empty callback.
HAL_StatusTypeDef | HAL_MultiProcessorEx_AddressLength_Set (UART_HandleTypeDef *huart, uint32_t AddressLength)
By default in multiprocessor mode, when the wake up method is set to address mark, the UART handles only 4-bit long addresses detection; this API allows to enable longer addresses detection (6-, 7- or 8-bit long).
HAL_StatusTypeDef | HAL_UARTEx_StopModeWakeUpSourceConfig (UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
Set Wakeup from Stop mode interrupt flag selection.
HAL_StatusTypeDef | HAL_UARTEx_EnableStopMode (UART_HandleTypeDef *huart)
Enable UART Stop Mode.
HAL_StatusTypeDef | HAL_UARTEx_DisableStopMode (UART_HandleTypeDef *huart)
Disable UART Stop Mode.
HAL_StatusTypeDef | HAL_UARTEx_EnableFifoMode (UART_HandleTypeDef *huart)
Enable the FIFO mode.
HAL_StatusTypeDef | HAL_UARTEx_DisableFifoMode (UART_HandleTypeDef *huart)
Disable the FIFO mode.
HAL_StatusTypeDef | HAL_UARTEx_SetTxFifoThreshold (UART_HandleTypeDef *huart, uint32_t Threshold)
Set the TXFIFO threshold.
HAL_StatusTypeDef | HAL_UARTEx_SetRxFifoThreshold (UART_HandleTypeDef *huart, uint32_t Threshold)
Set the RXFIFO threshold.

Detailed Description

Extended UART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + Peripheral Control functions.

Author:
MCD Application Team
  ==============================================================================
               ##### UART peripheral extended features  #####
  ==============================================================================

    (#) Declare a UART_HandleTypeDef handle structure.

    (#) For the UART RS485 Driver Enable mode, initialize the UART registers
        by calling the HAL_RS485Ex_Init() API.

    (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.

        -@- When UART operates in FIFO mode, FIFO mode must be enabled prior
            starting RX/TX transfers. Also RX/TX FIFO thresholds must be
            configured prior starting RX/TX transfers.
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_uart_ex.c.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_usart.c File Reference

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  • STM32WBxx_HAL_Driver
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Defines | Functions
stm32wbxx_hal_usart.c File Reference

USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter Peripheral (USART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Defines

#define | USART_DUMMY_DATA ((uint16_t) 0xFFFF)
#define | USART_TEACK_REACK_TIMEOUT 1000U
#define | USART_CR1_FIELDS
#define | USART_CR2_FIELDS
#define | USART_CR3_FIELDS ((uint32_t)(USART_CR3_TXFTCFG | USART_CR3_RXFTCFG ))
#define | USART_BRR_MIN 0x10U /* USART BRR minimum authorized value */
#define | USART_BRR_MAX 0xFFFFU /* USART BRR maximum authorized value */

Functions

void | USART_InitCallbacksToDefault (USART_HandleTypeDef *husart)
Initialize the callbacks to their default values.
static void | USART_EndTransfer (USART_HandleTypeDef *husart)
End ongoing transfer on USART peripheral (following error detection or Transfer completion).
static void | USART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process complete callback.
static void | USART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process complete callback.
static void | USART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process half complete callback.
static void | USART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process half complete callback.
static void | USART_DMAError (DMA_HandleTypeDef *hdma)
DMA USART communication error callback.
static void | USART_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA USART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | USART_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA USART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | USART_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA USART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static HAL_StatusTypeDef | USART_WaitOnFlagUntilTimeout (USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
Handle USART Communication Timeout.
static HAL_StatusTypeDef | USART_SetConfig (USART_HandleTypeDef *husart)
Configure the USART peripheral.
static HAL_StatusTypeDef | USART_CheckIdleState (USART_HandleTypeDef *husart)
Check the USART Idle State.
static void | USART_TxISR_8BIT (USART_HandleTypeDef *husart)
Simplex send an amount of data in non-blocking mode.
static void | USART_TxISR_16BIT (USART_HandleTypeDef *husart)
Simplex send an amount of data in non-blocking mode.
static void | USART_TxISR_8BIT_FIFOEN (USART_HandleTypeDef *husart)
Simplex send an amount of data in non-blocking mode.
static void | USART_TxISR_16BIT_FIFOEN (USART_HandleTypeDef *husart)
Simplex send an amount of data in non-blocking mode.
static void | USART_EndTransmit_IT (USART_HandleTypeDef *husart)
Wraps up transmission in non-blocking mode.
static void | USART_RxISR_8BIT (USART_HandleTypeDef *husart)
Simplex receive an amount of data in non-blocking mode.
static void | USART_RxISR_16BIT (USART_HandleTypeDef *husart)
Simplex receive an amount of data in non-blocking mode.
static void | USART_RxISR_8BIT_FIFOEN (USART_HandleTypeDef *husart)
Simplex receive an amount of data in non-blocking mode.
static void | USART_RxISR_16BIT_FIFOEN (USART_HandleTypeDef *husart)
Simplex receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_Init (USART_HandleTypeDef *husart)
Initialize the USART mode according to the specified parameters in the USART_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_USART_DeInit (USART_HandleTypeDef *husart)
DeInitialize the USART peripheral.
__weak void | HAL_USART_MspInit (USART_HandleTypeDef *husart)
Initialize the USART MSP.
__weak void | HAL_USART_MspDeInit (USART_HandleTypeDef *husart)
DeInitialize the USART MSP.
HAL_StatusTypeDef | HAL_USART_RegisterCallback (USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback)
Register a User USART Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef | HAL_USART_UnRegisterCallback (USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID)
Unregister an UART Callback UART callaback is redirected to the weak predefined callback.
HAL_StatusTypeDef | HAL_USART_Transmit (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
Simplex send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Full-Duplex Send and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Transmit_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Send an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Receive_IT (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Send and Receive an amount of data in interrupt mode.
HAL_StatusTypeDef | HAL_USART_Transmit_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Send an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_Receive_DMA (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Receive an amount of data in DMA mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Transmit Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_DMAPause (USART_HandleTypeDef *husart)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAResume (USART_HandleTypeDef *husart)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAStop (USART_HandleTypeDef *husart)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_Abort (USART_HandleTypeDef *husart)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_USART_Abort_IT (USART_HandleTypeDef *husart)
Abort ongoing transfers (Interrupt mode).
void | HAL_USART_IRQHandler (USART_HandleTypeDef *husart)
Handle USART interrupt request.
__weak void | HAL_USART_TxCpltCallback (USART_HandleTypeDef *husart)
Tx Transfer completed callback.
__weak void | HAL_USART_TxHalfCpltCallback (USART_HandleTypeDef *husart)
Tx Half Transfer completed callback.
__weak void | HAL_USART_RxCpltCallback (USART_HandleTypeDef *husart)
Rx Transfer completed callback.
__weak void | HAL_USART_RxHalfCpltCallback (USART_HandleTypeDef *husart)
Rx Half Transfer completed callback.
__weak void | HAL_USART_TxRxCpltCallback (USART_HandleTypeDef *husart)
Tx/Rx Transfers completed callback for the non-blocking process.
__weak void | HAL_USART_ErrorCallback (USART_HandleTypeDef *husart)
USART error callback.
__weak void | HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
USART Abort Complete callback.
HAL_USART_StateTypeDef | HAL_USART_GetState (USART_HandleTypeDef *husart)
Return the USART handle state.
uint32_t | HAL_USART_GetError (USART_HandleTypeDef *husart)
Return the USART error code.

Detailed Description

USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter Peripheral (USART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

Author:
MCD Application Team
 ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
    [..]
      The USART HAL driver can be used as follows:

      (#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart).
      (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API:
          (++) Enable the USARTx interface clock.
          (++) USART pins configuration:
            (+++) Enable the clock for the USART GPIOs.
            (+++) Configure these USART pins as alternate function pull-up.
          (++) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
                HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
            (+++) Configure the USARTx interrupt priority.
            (+++) Enable the NVIC USART IRQ handle.
            (++) USART interrupts handling:
              -@@-   The specific USART interrupts (Transmission complete interrupt,
                  RXNE interrupt and Error Interrupts) will be managed using the macros
                  __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
          (++) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
               HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx channel.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx channel.
            (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.

      (#) Program the Baud Rate, Word Length, Stop Bit, Parity, and Mode
          (Receiver/Transmitter) in the husart handle Init structure.

      (#) Initialize the USART registers by calling the HAL_USART_Init() API:
          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
               by calling the customized HAL_USART_MspInit(&husart) API.

    [..]
     (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's
        HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and
        HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef.

    ##### Callback registration #####
    ==================================

    [..]
    The compilation define USE_HAL_USART_REGISTER_CALLBACKS when set to 1
    allows the user to configure dynamically the driver callbacks.

    [..]
    Use Function @ref HAL_USART_RegisterCallback() to register a user callback.
    Function @ref HAL_USART_RegisterCallback() allows to register following callbacks:
    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
    (+) TxCpltCallback            : Tx Complete Callback.
    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
    (+) RxCpltCallback            : Rx Complete Callback.
    (+) TxRxCpltCallback          : Tx Rx Complete Callback.
    (+) ErrorCallback             : Error Callback.
    (+) AbortCpltCallback         : Abort Complete Callback.
    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
    (+) MspInitCallback           : USART MspInit.
    (+) MspDeInitCallback         : USART MspDeInit.
    This function takes as parameters the HAL peripheral handle, the Callback ID
    and a pointer to the user callback function.

    [..]
    Use function @ref HAL_USART_UnRegisterCallback() to reset a callback to the default
    weak (surcharged) function.
    @ref HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
    and the Callback ID.
    This function allows to reset following callbacks:
    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
    (+) TxCpltCallback            : Tx Complete Callback.
    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
    (+) RxCpltCallback            : Rx Complete Callback.
    (+) TxRxCpltCallback          : Tx Rx Complete Callback.
    (+) ErrorCallback             : Error Callback.
    (+) AbortCpltCallback         : Abort Complete Callback.
    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
    (+) MspInitCallback           : USART MspInit.
    (+) MspDeInitCallback         : USART MspDeInit.

    [..]
    By default, after the @ref HAL_USART_Init() and when the state is HAL_USART_STATE_RESET
    all callbacks are set to the corresponding weak (surcharged) functions:
    examples @ref HAL_USART_TxCpltCallback(), @ref HAL_USART_RxHalfCpltCallback().
    Exception done for MspInit and MspDeInit functions that are respectively
    reset to the legacy weak (surcharged) functions in the @ref HAL_USART_Init()
    and @ref HAL_USART_DeInit() only when these callbacks are null (not registered beforehand).
    If not, MspInit or MspDeInit are not null, the @ref HAL_USART_Init() and @ref HAL_USART_DeInit()
    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).

    [..]
    Callbacks can be registered/unregistered in HAL_USART_STATE_READY state only.
    Exception done MspInit/MspDeInit that can be registered/unregistered
    in HAL_USART_STATE_READY or HAL_USART_STATE_RESET state, thus registered (user)
    MspInit/DeInit callbacks can be used during the Init/DeInit.
    In that case first register the MspInit/MspDeInit user callbacks
    using @ref HAL_USART_RegisterCallback() before calling @ref HAL_USART_DeInit()
    or @ref HAL_USART_Init() function.

    [..]
    When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or
    not defined, the callback registration feature is not available
    and weak (surcharged) callbacks are used.
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_usart.c.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_usart_ex.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32WBxx_HAL_Driver
  • Src
Defines | Functions
stm32wbxx_hal_usart_ex.c File Reference

Extended USART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Synchronous Receiver Transmitter Peripheral (USART). + Peripheral Control functions. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Defines

#define | RX_FIFO_DEPTH 8U
#define | TX_FIFO_DEPTH 8U

Functions

static void | USARTEx_SetNbDataToProcess (USART_HandleTypeDef *husart)
Calculate the number of data to process in RX/TX ISR.
__weak void | HAL_USARTEx_RxFifoFullCallback (USART_HandleTypeDef *husart)
USART RX Fifo full callback.
__weak void | HAL_USARTEx_TxFifoEmptyCallback (USART_HandleTypeDef *husart)
USART TX Fifo empty callback.
HAL_StatusTypeDef | HAL_USARTEx_EnableSlaveMode (USART_HandleTypeDef *husart)
Enable the SPI slave mode.
HAL_StatusTypeDef | HAL_USARTEx_DisableSlaveMode (USART_HandleTypeDef *husart)
Disable the SPI slave mode.
HAL_StatusTypeDef | HAL_USARTEx_ConfigNSS (USART_HandleTypeDef *husart, uint32_t NSSConfig)
Configure the Slave Select input pin (NSS).
HAL_StatusTypeDef | HAL_USARTEx_EnableFifoMode (USART_HandleTypeDef *husart)
Enable the FIFO mode.
HAL_StatusTypeDef | HAL_USARTEx_DisableFifoMode (USART_HandleTypeDef *husart)
Disable the FIFO mode.
HAL_StatusTypeDef | HAL_USARTEx_SetTxFifoThreshold (USART_HandleTypeDef *husart, uint32_t Threshold)
Set the TXFIFO threshold.
HAL_StatusTypeDef | HAL_USARTEx_SetRxFifoThreshold (USART_HandleTypeDef *husart, uint32_t Threshold)
Set the RXFIFO threshold.

Detailed Description

Extended USART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Synchronous Receiver Transmitter Peripheral (USART). + Peripheral Control functions.

Author:
MCD Application Team
  ==============================================================================
               ##### USART peripheral extended features  #####
  ==============================================================================

    (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.

        -@- When USART operates in FIFO mode, FIFO mode must be enabled prior
            starting RX/TX transfers. Also RX/TX FIFO thresholds must be
            configured prior starting RX/TX transfers.

    (#) Slave mode enabling/disabling and NSS pin configuration.

        -@- When USART operates in Slave mode, Slave mode must be enabled prior
            starting RX/TX transfers.
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_usart_ex.c.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_wwdg.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32WBxx_HAL_Driver
  • Src
Functions
stm32wbxx_hal_wwdg.c File Reference

WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and Configuration functions + IO operation functions. More...

#include "stm32wbxx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_WWDG_Init (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG according to the specified.
__weak void | HAL_WWDG_MspInit (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG MSP.
HAL_StatusTypeDef | HAL_WWDG_RegisterCallback (WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback)
Register a User WWDG Callback To be used instead of the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_WWDG_UnRegisterCallback (WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID)
Unregister a WWDG Callback WWDG Callback is redirected to the weak (surcharged) predefined callback.
HAL_StatusTypeDef | HAL_WWDG_Refresh (WWDG_HandleTypeDef *hwwdg)
Refresh the WWDG.
void | HAL_WWDG_IRQHandler (WWDG_HandleTypeDef *hwwdg)
Handle WWDG interrupt request.
__weak void | HAL_WWDG_EarlyWakeupCallback (WWDG_HandleTypeDef *hwwdg)
WWDG Early Wakeup callback.

Detailed Description

WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and Configuration functions + IO operation functions.

Author:
MCD Application Team
  ==============================================================================
                      ##### WWDG Specific features #####
  ==============================================================================
  [..]
    Once enabled the WWDG generates a system reset on expiry of a programmed
    time period, unless the program refreshes the counter (T[6;0] downcounter)
    before reaching 0x3F value (i.e. a reset is generated when the counter
    value rolls down from 0x40 to 0x3F).

    (+) An MCU reset is also generated if the counter value is refreshed
        before the counter has reached the refresh window value. This
        implies that the counter must be refreshed in a limited window.
    (+) Once enabled the WWDG cannot be disabled except by a system reset.
    (+) WWDGRST flag in RCC CSR register can be used to inform when a WWDG
        reset occurs.
    (+) The WWDG counter input clock is derived from the APB clock divided
        by a programmable prescaler.
    (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler)
    (+) WWDG timeout (mS) = 1000 * (T[5;0] + 1) / WWDG clock (Hz)
        where T[5;0] are the lowest 6 bits of Counter.
    (+) WWDG Counter refresh is allowed between the following limits :
        (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock
        (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
    (+) Typical values:
        (++) Counter min (T[5;0] = 0x00) @64 MHz (PCLK1) with zero prescaler:
             max timeout before reset: approximately 64µs
        (++) Counter max (T[5;0] = 0x3F) @64 MHz (PCLK1) with prescaler dividing by 128:
             max timeout before reset: approximately 524.28ms

  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================

    *** Common driver usage ***
    ===========================

  [..]
    (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
    (+) Set the WWDG prescaler, refresh window and counter value
        using HAL_WWDG_Init() function.
    (+) Start the WWDG using HAL_WWDG_Start() function.
        When the WWDG is enabled the counter value should be configured to
        a value greater than 0x40 to prevent generating an immediate reset.
    (+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is
        generated when the counter reaches 0x40, and then start the WWDG using
        HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can
        add his own code by customization of callback HAL_WWDG_WakeupCallback.
        Once enabled, EWI interrupt cannot be disabled except by a system reset.
    (+) Then the application program must refresh the WWDG counter at regular
        intervals during normal operation to prevent an MCU reset, using
        HAL_WWDG_Refresh() function. This operation must occur only when
        the counter is lower than the refresh window value already programmed.

    *** Callback registration ***
    =============================

  [..]
    The compilation define  USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows
    the user to configure dynamically the driver callbacks. Use Functions
    @ref HAL_WWDG_RegisterCallback() to register a user callback.

    (+) Function @ref HAL_WWDG_RegisterCallback() allows to register following
        callbacks:
        (++) EwiCallback : callback for Early WakeUp Interrupt.
        (++) MspInitCallback : WWDG MspInit.
    This function takes as parameters the HAL peripheral handle, the Callback ID
    and a pointer to the user callback function.

    (+) Use function @ref HAL_WWDG_UnRegisterCallback() to reset a callback to
    the default weak (surcharged) function. @ref HAL_WWDG_UnRegisterCallback()
    takes as parameters the HAL peripheral handle and the Callback ID.
    This function allows to reset following callbacks:
        (++) EwiCallback : callback for  Early WakeUp Interrupt.
        (++) MspInitCallback : WWDG MspInit.

    [..]
    When calling @ref HAL_WWDG_Init function, callbacks are reset to the
    corresponding legacy weak (surcharged) functions:
    @ref HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have
    not been registered before.

    [..]
    When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or
    not defined, the callback registering feature is not available
    and weak (surcharged) callbacks are used.

    *** WWDG HAL driver macros list ***
    ===================================
    [..]
      Below the list of most used macros in WWDG HAL driver.
      (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
      (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
      (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
      (+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_hal_wwdg.c.

Generated on Fri Sep 6 2019 11:34:38 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_crs.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32WBxx_HAL_Driver
  • Src
Functions
stm32wbxx_ll_crs.c File Reference
#include "stm32wbxx_ll_crs.h"
#include "stm32wbxx_ll_bus.h"

Go to the source code of this file.

Functions

ErrorStatus LL_CRS_DeInit (void)
De-Initializes CRS peripheral registers to their default reset values.
Generated on Fri Sep 6 2019 11:34:39 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_pwr.c File Reference

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32WBxx_HAL_Driver
  • Src
Defines | Functions
stm32wbxx_ll_pwr.c File Reference

PWR LL module driver. More...

#include "stm32wbxx_ll_pwr.h"
#include "stm32wbxx_ll_bus.h"

Go to the source code of this file.

Defines

#define | PWR_CR1_RESET_VALUE (0x00000200)
#define | PWR_CR2_RESET_VALUE (0x00000000)
#define | PWR_CR3_RESET_VALUE (0x00008000)
#define | PWR_CR4_RESET_VALUE (0x00000000)
#define | PWR_CR5_RESET_VALUE (0x00004272)
#define | PWR_PUCRA_RESET_VALUE (0x00000000)
#define | PWR_PDCRA_RESET_VALUE (0x00000000)
#define | PWR_PUCRB_RESET_VALUE (0x00000000)
#define | PWR_PDCRB_RESET_VALUE (0x00000000)
#define | PWR_PUCRC_RESET_VALUE (0x00000000)
#define | PWR_PDCRC_RESET_VALUE (0x00000000)
#define | PWR_PUCRD_RESET_VALUE (0x00000000)
#define | PWR_PDCRD_RESET_VALUE (0x00000000)
#define | PWR_PUCRE_RESET_VALUE (0x00000000)
#define | PWR_PDCRE_RESET_VALUE (0x00000000)
#define | PWR_PUCRH_RESET_VALUE (0x00000000)
#define | PWR_PDCRH_RESET_VALUE (0x00000000)
#define | PWR_C2CR1_RESET_VALUE (0x00000000)
#define | PWR_C2CR3_RESET_VALUE (0x00008000)

Functions

ErrorStatus | LL_PWR_DeInit (void)
De-initialize the PWR registers to their default reset values.

Detailed Description

PWR LL module driver.

Author:
MCD Application Team
Attention:

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32wbxx_ll_pwr.c.

Generated on Fri Sep 6 2019 11:34:39 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC_rmtollPages.txt File Reference

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  • Globals
ADC_rmtollPages.txt File Reference
Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Structures

  • Data Structure Index
  • Data Fields
Data Structures
Here are the data structures with brief descriptions:
__ADC_HandleTypeDef | ADC handle Structure definition
__COMP_HandleTypeDef | COMP Handle Structure definition
__CRYP_HandleTypeDef | CRYP handle Structure definition
__DMA_HandleTypeDef | DMA handle Structure definition
__I2C_HandleTypeDef |
__IPCC_HandleTypeDef | IPCC handle structure definition
__IRDA_HandleTypeDef | IRDA handle Structure definition
__LPTIM_HandleTypeDef | LPTIM handle Structure definition
__PCD_HandleTypeDef | PCD Handle Structure definition
__PKA_HandleTypeDef |
__QSPI_HandleTypeDef | QSPI Handle Structure definition
__RNG_HandleTypeDef |
__RTC_HandleTypeDef | RTC Handle Structure definition
__SAI_HandleTypeDef |
__SMARTCARD_HandleTypeDef | SMARTCARD handle Structure definition
__SMBUS_HandleTypeDef |
__SPI_HandleTypeDef | SPI handle Structure definition
__TIM_HandleTypeDef | TIM Time Base Handle Structure definition
__TSC_HandleTypeDef | TSC handle Structure definition
__UART_HandleTypeDef | UART handle Structure definition
__USART_HandleTypeDef | USART handle Structure definition
__WWDG_HandleTypeDef | WWDG handle Structure definition
ADC_AnalogWDGConfTypeDef | Structure definition of ADC analog watchdog
ADC_ChannelConfTypeDef | Structure definition of ADC channel for regular group
ADC_InitTypeDef | Structure definition of ADC instance and ADC group regular
ADC_InjectionConfigTypeDef | ADC group injected contexts queue configuration
ADC_InjectionConfTypeDef | Structure definition of ADC group injected and ADC channel affected to ADC group injected
ADC_InjOversamplingTypeDef | ADC Injected Conversion Oversampling structure definition
ADC_OversamplingTypeDef | ADC group regular oversampling structure definition
COMP_InitTypeDef | COMP Init structure definition
CRC_HandleTypeDef | CRC Handle Structure definition
CRC_InitTypeDef | CRC Init Structure definition
CRYP_ConfigTypeDef | CRYP Init Structure definition
DMA_InitTypeDef | DMA Configuration Structure definition
EXTI_ConfigTypeDef | EXTI Configuration structure definition
EXTI_HandleTypeDef | EXTI Handle structure definition
FLASH_EraseInitTypeDef | FLASH Erase structure definition
FLASH_OBProgramInitTypeDef | FLASH Option Bytes Program structure definition
FLASH_ProcessTypeDef | FLASH handle Structure definition
GPIO_InitTypeDef | GPIO Init structure definition
HAL_DMA_MuxRequestGeneratorConfigTypeDef | HAL DMAMUX request generator parameters structure definition
HAL_DMA_MuxSyncConfigTypeDef | HAL DMA Synchro definition
I2C_InitTypeDef |
IRDA_InitTypeDef | IRDA Init Structure definition
IWDG_HandleTypeDef | IWDG Handle Structure definition
IWDG_InitTypeDef | IWDG Init structure definition
LCD_HandleTypeDef | UART handle Structure definition
LCD_InitTypeDef | LCD Init structure definition
LL_ADC_CommonInitTypeDef | Structure definition of some features of ADC common parameters and multimode (all ADC instances belonging to the same ADC common instance)
LL_ADC_InitTypeDef | Structure definition of some features of ADC instance
LL_ADC_INJ_InitTypeDef | Structure definition of some features of ADC group injected
LL_ADC_REG_InitTypeDef | Structure definition of some features of ADC group regular
LL_COMP_InitTypeDef | Structure definition of some features of COMP instance
LL_DMA_InitTypeDef |
LL_EXTI_InitTypeDef |
LL_GPIO_InitTypeDef | LL GPIO Init Structure definition
LL_I2C_InitTypeDef |
LL_LPTIM_InitTypeDef | LPTIM Init structure definition
LL_LPUART_InitTypeDef | LL LPUART Init Structure definition
LL_PKA_InitTypeDef | PKA Init structures definition
LL_RCC_ClocksTypeDef | RCC Clocks Frequency Structure
LL_RNG_InitTypeDef | LL RNG Init Structure Definition
LL_RTC_AlarmTypeDef | RTC Alarm structure definition
LL_RTC_DateTypeDef | RTC Date structure definition
LL_RTC_InitTypeDef | RTC Init structures definition
LL_RTC_TimeTypeDef | RTC Time structure definition
LL_SPI_InitTypeDef | SPI Init structures definition
LL_TIM_BDTR_InitTypeDef | BDTR (Break and Dead Time) structure definition
LL_TIM_ENCODER_InitTypeDef | TIM Encoder interface configuration structure definition
LL_TIM_HALLSENSOR_InitTypeDef | TIM Hall sensor interface configuration structure definition
LL_TIM_IC_InitTypeDef | TIM Input Capture configuration structure definition
LL_TIM_InitTypeDef | TIM Time Base configuration structure definition
LL_TIM_OC_InitTypeDef | TIM Output Compare configuration structure definition
LL_USART_ClockInitTypeDef | LL USART Clock Init Structure definition
LL_USART_InitTypeDef | LL USART Init Structure definition
LL_UTILS_ClkInitTypeDef | UTILS System, AHB and APB buses clock configuration structure definition
LL_UTILS_PLLInitTypeDef | UTILS PLL structure definition
LPTIM_ClockConfigTypeDef | LPTIM Clock configuration definition
LPTIM_InitTypeDef | LPTIM Initialization Structure definition
LPTIM_TriggerConfigTypeDef | LPTIM Trigger configuration definition
LPTIM_ULPClockConfigTypeDef | LPTIM Clock configuration definition
MPU_Region_InitTypeDef |
PKA_AddInTypeDef |
PKA_ECCMulFastModeInTypeDef |
PKA_ECCMulInTypeDef |
PKA_ECDSASignInTypeDef |
PKA_ECDSASignOutExtParamTypeDef |
PKA_ECDSASignOutTypeDef |
PKA_ECDSAVerifInTypeDef |
PKA_ModAddInTypeDef |
PKA_ModExpFastModeInTypeDef |
PKA_ModExpInTypeDef |
PKA_ModInvInTypeDef |
PKA_ModRedInTypeDef |
PKA_MontgomeryParamInTypeDef |
PKA_PointCheckInTypeDef |
PKA_RSACRTExpInTypeDef |
PWR_PVDTypeDef | PWR PVD configuration structure definition
PWR_PVMTypeDef | PWR PVM configuration structure definition
PWR_SMPSTypeDef | PWR SMPS step down configuration structure definition
QSPI_AutoPollingTypeDef | QSPI Auto Polling mode configuration structure definition
QSPI_CommandTypeDef | QSPI Command structure definition
QSPI_InitTypeDef | QSPI Init structure definition
QSPI_MemoryMappedTypeDef | QSPI Memory Mapped mode configuration structure definition
RCC_ClkInitTypeDef | RCC System, AHB and APB buses clock configuration structure definition
RCC_CRSInitTypeDef | RCC_CRS Init structure definition
RCC_CRSSynchroInfoTypeDef | RCC_CRS Synchronization structure definition
RCC_OscInitTypeDef | RCC Internal/External Oscillator (HSE, HSI, HSI48, MSI, LSE and LSI) configuration structure definition
RCC_PeriphCLKInitTypeDef | RCC extended clocks structure definition
RCC_PLLInitTypeDef | RCC PLL configuration structure definition
RCC_PLLSAI1InitTypeDef | PLLSAI1 Clock structure definition
RNG_InitTypeDef |
RTC_AlarmTypeDef | RTC Alarm structure definition
RTC_DateTypeDef | RTC Date structure definition
RTC_InitTypeDef | RTC Configuration Structure definition
RTC_TamperTypeDef | RTC Tamper structure definition
RTC_TimeTypeDef | RTC Time structure definition
SAI_FrameInitTypeDef |
SAI_InitTypeDef |
SAI_PdmInitTypeDef |
SAI_SlotInitTypeDef |
SAIEx_PdmMicDelayParamTypeDef | PDM microphone delay structure definition
SMARTCARD_AdvFeatureInitTypeDef | SMARTCARD advanced features initalization structure definition
SMARTCARD_InitTypeDef | SMARTCARD Init Structure definition
SMBUS_InitTypeDef |
SPI_InitTypeDef | SPI Configuration Structure definition
TIM_Base_InitTypeDef | TIM Time base Configuration Structure definition
TIM_BreakDeadTimeConfigTypeDef | TIM Break input(s) and Dead time configuration Structure definition
TIM_ClearInputConfigTypeDef | TIM Clear Input Configuration Handle Structure definition
TIM_ClockConfigTypeDef | Clock Configuration Handle Structure definition
TIM_Encoder_InitTypeDef | TIM Encoder Configuration Structure definition
TIM_HallSensor_InitTypeDef | TIM Hall sensor Configuration Structure definition
TIM_IC_InitTypeDef | TIM Input Capture Configuration Structure definition
TIM_MasterConfigTypeDef | TIM Master configuration Structure definition
TIM_OC_InitTypeDef | TIM Output Compare Configuration Structure definition
TIM_OnePulse_InitTypeDef | TIM One Pulse Mode Configuration Structure definition
TIM_SlaveConfigTypeDef | TIM Slave configuration Structure definition
TIMEx_BreakInputConfigTypeDef | TIM Break/Break2 input configuration
TSC_InitTypeDef | TSC init structure definition
TSC_IOConfigTypeDef | TSC IOs configuration structure definition
UART_AdvFeatureInitTypeDef | UART Advanced Features initialization structure definition
UART_InitTypeDef | UART Init Structure definition
UART_WakeUpTypeDef | UART wake up from stop mode parameters
USART_InitTypeDef | USART Init Structure definition
WWDG_InitTypeDef | WWDG Init structure definition
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: BUS_rmtollPages.txt File Reference

  • File List
  • Globals
BUS_rmtollPages.txt File Reference
Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Data Structure Index

  • Data Structure Index
  • Data Fields
Data Structure Index
A | C | D | E | F | G | H | I | L | M | P | Q | R | S | T | U | W | _
A
IRDA_InitTypeDef LPTIM_InitTypeDef RCC_OscInitTypeDef
U
IWDG_HandleTypeDef LPTIM_TriggerConfigTypeDef RCC_PeriphCLKInitTypeDef
ADC_AnalogWDGConfTypeDef IWDG_InitTypeDef LPTIM_ULPClockConfigTypeDef RCC_PLLInitTypeDef UART_AdvFeatureInitTypeDef
ADC_ChannelConfTypeDef
L
M
RCC_PLLSAI1InitTypeDef UART_InitTypeDef
ADC_InitTypeDef RNG_InitTypeDef UART_WakeUpTypeDef
ADC_InjectionConfigTypeDef LCD_HandleTypeDef MPU_Region_InitTypeDef RTC_AlarmTypeDef USART_InitTypeDef
ADC_InjectionConfTypeDef LCD_InitTypeDef
P
RTC_DateTypeDef
W
ADC_InjOversamplingTypeDef LL_ADC_CommonInitTypeDef RTC_InitTypeDef
ADC_OversamplingTypeDef LL_ADC_InitTypeDef PKA_AddInTypeDef RTC_TamperTypeDef WWDG_InitTypeDef
C
LL_ADC_INJ_InitTypeDef PKA_ECCMulFastModeInTypeDef RTC_TimeTypeDef
_
LL_ADC_REG_InitTypeDef PKA_ECCMulInTypeDef
S
COMP_InitTypeDef LL_COMP_InitTypeDef PKA_ECDSASignInTypeDef __ADC_HandleTypeDef
CRC_HandleTypeDef LL_DMA_InitTypeDef PKA_ECDSASignOutExtParamTypeDef SAI_FrameInitTypeDef __COMP_HandleTypeDef
CRC_InitTypeDef LL_EXTI_InitTypeDef PKA_ECDSASignOutTypeDef SAI_InitTypeDef __CRYP_HandleTypeDef
CRYP_ConfigTypeDef LL_GPIO_InitTypeDef PKA_ECDSAVerifInTypeDef SAI_PdmInitTypeDef __DMA_HandleTypeDef
D
LL_I2C_InitTypeDef PKA_ModAddInTypeDef SAI_SlotInitTypeDef __I2C_HandleTypeDef
LL_LPTIM_InitTypeDef PKA_ModExpFastModeInTypeDef SAIEx_PdmMicDelayParamTypeDef __IPCC_HandleTypeDef
DMA_InitTypeDef LL_LPUART_InitTypeDef PKA_ModExpInTypeDef SMARTCARD_AdvFeatureInitTypeDef __IRDA_HandleTypeDef
E
LL_PKA_InitTypeDef PKA_ModInvInTypeDef SMARTCARD_InitTypeDef __LPTIM_HandleTypeDef
LL_RCC_ClocksTypeDef PKA_ModRedInTypeDef SMBUS_InitTypeDef __PCD_HandleTypeDef
EXTI_ConfigTypeDef LL_RNG_InitTypeDef PKA_MontgomeryParamInTypeDef SPI_InitTypeDef __PKA_HandleTypeDef
EXTI_HandleTypeDef LL_RTC_AlarmTypeDef PKA_PointCheckInTypeDef
T
__QSPI_HandleTypeDef
F
LL_RTC_DateTypeDef PKA_RSACRTExpInTypeDef __RNG_HandleTypeDef
LL_RTC_InitTypeDef PWR_PVDTypeDef TIM_Base_InitTypeDef __RTC_HandleTypeDef
FLASH_EraseInitTypeDef LL_RTC_TimeTypeDef PWR_PVMTypeDef TIM_BreakDeadTimeConfigTypeDef __SAI_HandleTypeDef
FLASH_OBProgramInitTypeDef LL_SPI_InitTypeDef PWR_SMPSTypeDef TIM_ClearInputConfigTypeDef __SMARTCARD_HandleTypeDef
FLASH_ProcessTypeDef LL_TIM_BDTR_InitTypeDef
Q
TIM_ClockConfigTypeDef __SMBUS_HandleTypeDef
G
LL_TIM_ENCODER_InitTypeDef TIM_Encoder_InitTypeDef __SPI_HandleTypeDef
LL_TIM_HALLSENSOR_InitTypeDef QSPI_AutoPollingTypeDef TIM_HallSensor_InitTypeDef __TIM_HandleTypeDef
GPIO_InitTypeDef LL_TIM_IC_InitTypeDef QSPI_CommandTypeDef TIM_IC_InitTypeDef __TSC_HandleTypeDef
H
LL_TIM_InitTypeDef QSPI_InitTypeDef TIM_MasterConfigTypeDef __UART_HandleTypeDef
LL_TIM_OC_InitTypeDef QSPI_MemoryMappedTypeDef TIM_OC_InitTypeDef __USART_HandleTypeDef
HAL_DMA_MuxRequestGeneratorConfigTypeDef LL_USART_ClockInitTypeDef
R
TIM_OnePulse_InitTypeDef __WWDG_HandleTypeDef
HAL_DMA_MuxSyncConfigTypeDef LL_USART_InitTypeDef TIM_SlaveConfigTypeDef
I
LL_UTILS_ClkInitTypeDef RCC_ClkInitTypeDef TIMEx_BreakInputConfigTypeDef
LL_UTILS_PLLInitTypeDef RCC_CRSInitTypeDef TSC_InitTypeDef
I2C_InitTypeDef LPTIM_ClockConfigTypeDef RCC_CRSSynchroInfoTypeDef TSC_IOConfigTypeDef
A | C | D | E | F | G | H | I | L | M | P | Q | R | S | T | U | W | _
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: COMP_rmtollPages.txt File Reference

  • File List
  • Globals
COMP_rmtollPages.txt File Reference
Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CORTEX_rmtollPages.txt File Reference

  • File List
  • Globals
CORTEX_rmtollPages.txt File Reference
Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CRC_rmtollPages.txt File Reference

  • File List
  • Globals
CRC_rmtollPages.txt File Reference
Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CRS_rmtollPages.txt File Reference

  • File List
  • Globals
CRS_rmtollPages.txt File Reference
Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: C:/git/wb_release_v1.3.0/Firmware/ Directory Reference

  • Firmware
Firmware Directory Reference

Directories

directory Drivers
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: C:/git/wb_release_v1.3.0/Firmware/Drivers/STM32WBxx_HAL_Driver/Src/ Directory Reference

  • Firmware
  • Drivers
  • STM32WBxx_HAL_Driver
  • Src
Src Directory Reference

Files

file | stm32wbxx_hal.c [code]

HAL module driver. This is the common part of the HAL initialization.

file | stm32wbxx_hal_adc.c [code]

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Initialization and de-initialization functions ++ Initialization and Configuration of ADC + Operation functions ++ Start, stop, get result of conversions of regular group, using 3 possible modes: polling, interruption or DMA. + Control functions ++ Channels configuration on regular group ++ Analog Watchdog configuration + State functions ++ ADC state machine management ++ Interrupts and flags management Other functions (extended functions) are available in file "stm32wbxx_hal_adc_ex.c".

file | stm32wbxx_hal_adc_ex.c [code]

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Operation functions ++ Start, stop, get result of conversions of ADC group injected, using 2 possible modes: polling, interruption. ++ Calibration +++ ADC automatic self-calibration +++ Calibration factors get or set + Control functions ++ Channels configuration on ADC group injected + State functions ++ ADC group injected contexts queue management Other functions (generic functions) are available in file "stm32wbxx_hal_adc.c".

file | stm32wbxx_hal_comp.c [code]

COMP HAL module driver. This file provides firmware functions to manage the following functionalities of the COMP peripheral: + Initialization and de-initialization functions + Start/Stop operation functions in polling mode + Start/Stop operation functions in interrupt mode (through EXTI interrupt) + Peripheral control functions + Peripheral state functions.

file | stm32wbxx_hal_cortex.c [code]

CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and Configuration functions + Peripheral Control functions.

file | stm32wbxx_hal_crc.c [code]

CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the Cyclic Redundancy Check (CRC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions.

file | stm32wbxx_hal_crc_ex.c [code]

Extended CRC HAL module driver. This file provides firmware functions to manage the extended functionalities of the CRC peripheral.

file | stm32wbxx_hal_cryp.c [code]

CRYP HAL module driver. This file provides firmware functions to manage the following functionalities of the Cryptography (CRYP) peripheral: + Initialization, de-initialization, set config and get config functions + DES/TDES, AES processing functions + DMA callback functions + CRYP IRQ handler management + Peripheral State functions.

file | stm32wbxx_hal_cryp_ex.c [code]

CRYPEx HAL module driver. This file provides firmware functions to manage the extended functionalities of the Cryptography (CRYP) peripheral.

file | stm32wbxx_hal_dma.c [code]

DMA HAL module driver. This file provides firmware functions to manage the following functionalities of the Direct Memory Access (DMA) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and errors functions.

file | stm32wbxx_hal_dma_ex.c [code]

DMA Extension HAL module driver This file provides firmware functions to manage the following functionalities of the DMA Extension peripheral: + Extended features functions.

file | stm32wbxx_hal_exti.c [code]

EXTI HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (EXTI) peripheral: + Initialization and de-initialization functions + IO operation functions.

file | stm32wbxx_hal_flash.c [code]

FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral Errors functions.

file | stm32wbxx_hal_flash_ex.c [code]

Extended FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the FLASH extended peripheral: + Extended programming operations functions.

file | stm32wbxx_hal_gpio.c [code]

GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions.

file | stm32wbxx_hal_hsem.c [code]

HSEM HAL module driver. This file provides firmware functions to manage the following functionalities of the semaphore peripheral: + Semaphore Take function (2-Step Procedure) , non blocking + Semaphore FastTake function (1-Step Procedure) , non blocking + Semaphore Status check + Semaphore Clear Key Set and Get + Release and release all functions + Semaphore notification enabling and disabling and callnack functions + IRQ handler management.

file | stm32wbxx_hal_i2c.c [code]

I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

file | stm32wbxx_hal_i2c_ex.c [code]

I2C Extended HAL module driver. This file provides firmware functions to manage the following functionalities of I2C Extended peripheral: + Extended features functions.

file | stm32wbxx_hal_ipcc.c [code]

IPCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter-Processor communication controller peripherals (IPCC). + Initialization and de-initialization functions + Configuration, notification and interrupts handling + Peripheral State and Error functions.

file | stm32wbxx_hal_irda.c [code]

IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA (Infrared Data Association) Peripheral (IRDA) + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions + Peripheral Control functions.

file | stm32wbxx_hal_iwdg.c [code]

IWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Independent Watchdog (IWDG) peripheral: + Initialization and Start functions + IO operation functions.

file | stm32wbxx_hal_lcd.c [code]

LCD Controller HAL module driver. This file provides firmware functions to manage the following functionalities of the LCD Controller (LCD) peripheral: + Initialization/de-initialization methods + I/O operation methods + Peripheral State methods.

file | stm32wbxx_hal_lptim.c [code]

LPTIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Low Power Timer (LPTIM) peripheral: + Initialization and de-initialization functions. + Start/Stop operation functions in polling mode. + Start/Stop operation functions in interrupt mode. + Reading operation functions. + Peripheral State functions.

file | stm32wbxx_hal_pcd.c [code]

PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32wbxx_hal_pcd_ex.c [code]

PCD Extended HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Extended features functions.

file | stm32wbxx_hal_pka.c [code]

PKA HAL module driver. This file provides firmware functions to manage the following functionalities of public key accelerator(PKA): + Initialization and de-initialization functions + Start an operation + Retrieve the operation result.

file | stm32wbxx_hal_pwr.c [code]

PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Initialization/de-initialization functions + Peripheral Control functions.

file | stm32wbxx_hal_pwr_ex.c [code]

Extended PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Extended Initialization and de-initialization functions + Extended Peripheral Control functions.

file | stm32wbxx_hal_qspi.c [code]

QSPI HAL module driver. This file provides firmware functions to manage the following functionalities of the QuadSPI interface (QSPI). + Initialization and de-initialization functions + Indirect functional mode management + Memory-mapped functional mode management + Auto-polling functional mode management + Interrupts and flags management + DMA channel configuration for indirect functional mode + Errors management and abort functionality.

file | stm32wbxx_hal_rcc.c [code]

RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions.

file | stm32wbxx_hal_rcc_ex.c [code]

Extended RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extended peripheral: + Extended Peripheral Control functions + Extended Clock management functions + Extended Clock Recovery System Control functions.

file | stm32wbxx_hal_rng.c [code]

RNG HAL module driver. This file provides firmware functions to manage the following functionalities of the Random Number Generator (RNG) peripheral: + Initialization and configuration functions + Peripheral Control functions + Peripheral State functions.

file | stm32wbxx_hal_rtc.c [code]

RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real-Time Clock (RTC) peripheral: + Initialization + Calendar (Time and Date) configuration + Alarms (Alarm A and Alarm B) configuration + WakeUp Timer configuration + TimeStamp configuration + Tampers configuration + Backup Data Registers configuration + RTC Tamper and TimeStamp Pins Selection + Interrupts and flags management.

file | stm32wbxx_hal_rtc_ex.c [code]

Extended RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extended peripheral: + RTC Time Stamp functions + RTC Tamper functions + RTC Wake-up functions + Extended Control functions + Extended RTC features functions.

file | stm32wbxx_hal_sai.c [code]

SAI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Audio Interface (SAI) peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32wbxx_hal_sai_ex.c [code]

SAI Extended HAL module driver. This file provides firmware functions to manage the following functionality of the SAI Peripheral Controller: + Modify PDM microphone delays.

file | stm32wbxx_hal_smartcard.c [code]

SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

file | stm32wbxx_hal_smartcard_ex.c [code]

SMARTCARD HAL module driver. This file provides extended firmware functions to manage the following functionalities of the SmartCard. + Initialization and de-initialization functions + Peripheral Control functions.

file | stm32wbxx_hal_smbus.c [code]

SMBUS HAL module driver. This file provides firmware functions to manage the following functionalities of the System Management Bus (SMBus) peripheral, based on I2C principles of operation : + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

file | stm32wbxx_hal_spi.c [code]

SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32wbxx_hal_spi_ex.c [code]

Extended SPI HAL module driver. This file provides firmware functions to manage the following SPI peripheral extended functionalities : + IO operation functions.

file | stm32wbxx_hal_tim.c [code]

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + TIM Time Base Initialization + TIM Time Base Start + TIM Time Base Start Interruption + TIM Time Base Start DMA + TIM Output Compare/PWM Initialization + TIM Output Compare/PWM Channel Configuration + TIM Output Compare/PWM Start + TIM Output Compare/PWM Start Interruption + TIM Output Compare/PWM Start DMA + TIM Input Capture Initialization + TIM Input Capture Channel Configuration + TIM Input Capture Start + TIM Input Capture Start Interruption + TIM Input Capture Start DMA + TIM One Pulse Initialization + TIM One Pulse Channel Configuration + TIM One Pulse Start + TIM Encoder Interface Initialization + TIM Encoder Interface Start + TIM Encoder Interface Start Interruption + TIM Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + TIM OCRef clear configuration + TIM External Clock configuration.

file | stm32wbxx_hal_tim_ex.c [code]

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer Extended peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal break and dead time configuration + Time Master and Slave synchronization configuration + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + Time OCRef clear configuration + Timer remapping capabilities configuration.

file | stm32wbxx_hal_tsc.c [code]

This file provides firmware functions to manage the following functionalities of the Touch Sensing Controller (TSC) peripheral: + Initialization and De-initialization + Channel IOs, Shield IOs and Sampling IOs configuration + Start and Stop an acquisition + Read acquisition result + Interrupts and flags management.

file | stm32wbxx_hal_uart.c [code]

UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions.

file | stm32wbxx_hal_uart_ex.c [code]

Extended UART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + Peripheral Control functions.

file | stm32wbxx_hal_usart.c [code]

USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter Peripheral (USART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

file | stm32wbxx_hal_usart_ex.c [code]

Extended USART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Synchronous Receiver Transmitter Peripheral (USART). + Peripheral Control functions.

file | stm32wbxx_hal_wwdg.c [code]

WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and Configuration functions + IO operation functions.

file | stm32wbxx_ll_adc.c [code]

ADC LL module driver.

file | stm32wbxx_ll_comp.c [code]

COMP LL module driver.

file | stm32wbxx_ll_crc.c [code]

CRC LL module driver.

file | stm32wbxx_ll_crs.c [code]
file | stm32wbxx_ll_dma.c [code]

DMA LL module driver.

file | stm32wbxx_ll_exti.c [code]

EXTI LL module driver.

file | stm32wbxx_ll_gpio.c [code]

GPIO LL module driver.

file | stm32wbxx_ll_i2c.c [code]

I2C LL module driver.

file | stm32wbxx_ll_lptim.c [code]

LPTIM LL module driver.

file | stm32wbxx_ll_lpuart.c [code]

LPUART LL module driver.

file | stm32wbxx_ll_pka.c [code]

PKA LL module driver.

file | stm32wbxx_ll_pwr.c [code]

PWR LL module driver.

file | stm32wbxx_ll_rcc.c [code]

RCC LL module driver.

file | stm32wbxx_ll_rng.c [code]

RNG LL module driver.

file | stm32wbxx_ll_rtc.c [code]

RTC LL module driver.

file | stm32wbxx_ll_spi.c [code]

SPI LL module driver.

file | stm32wbxx_ll_tim.c [code]

TIM LL module driver.

file | stm32wbxx_ll_usart.c [code]

USART LL module driver.

file | stm32wbxx_ll_utils.c [code]

UTILS LL module driver.

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STM32WB55xx HAL User Manual: C:/git/wb_release_v1.3.0/Firmware/Drivers/ Directory Reference

  • Firmware
  • Drivers
Drivers Directory Reference

Directories

directory STM32WBxx_HAL_Driver
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: C:/git/wb_release_v1.3.0/Firmware/Drivers/STM32WBxx_HAL_Driver/ Directory Reference

  • Firmware
  • Drivers
  • STM32WBxx_HAL_Driver
STM32WBxx_HAL_Driver Directory Reference

Directories

directory | Inc
directory | Src
Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: C:/git/wb_release_v1.3.0/Firmware/Drivers/STM32WBxx_HAL_Driver/Inc/ Directory Reference

  • Firmware
  • Drivers
  • STM32WBxx_HAL_Driver
  • Inc
Inc Directory Reference

Files

file | stm32wbxx_hal.h [code]

This file contains all the functions prototypes for the HAL module driver.

file | stm32wbxx_hal_adc.h [code]

Header file of ADC HAL module.

file | stm32wbxx_hal_adc_ex.h [code]

Header file of ADC HAL extended module.

file | stm32wbxx_hal_comp.h [code]

Header file of COMP HAL module.

file | stm32wbxx_hal_cortex.h [code]

Header file of CORTEX HAL module.

file | stm32wbxx_hal_crc.h [code]

Header file of CRC HAL module.

file | stm32wbxx_hal_crc_ex.h [code]

Header file of CRC HAL extended module.

file | stm32wbxx_hal_cryp.h [code]

Header file of CRYP HAL module.

file | stm32wbxx_hal_cryp_ex.h [code]

Header file of CRYPEx HAL module.

file | stm32wbxx_hal_dma.h [code]

Header file of DMA HAL module.

file | stm32wbxx_hal_dma_ex.h [code]

Header file of DMA HAL extension module.

file | stm32wbxx_hal_exti.h [code]

Header file of EXTI HAL module.

file | stm32wbxx_hal_flash.h [code]

Header file of FLASH HAL module.

file | stm32wbxx_hal_flash_ex.h [code]

Header file of FLASH HAL Extended module.

file | stm32wbxx_hal_gpio.h [code]

Header file of GPIO HAL module.

file | stm32wbxx_hal_gpio_ex.h [code]

Header file of GPIO HAL Extended module.

file | stm32wbxx_hal_hsem.h [code]

Header file of HSEM HAL module.

file | stm32wbxx_hal_i2c.h [code]

Header file of I2C HAL module.

file | stm32wbxx_hal_i2c_ex.h [code]

Header file of I2C HAL Extended module.

file | stm32wbxx_hal_ipcc.h [code]

Header file of Mailbox HAL module.

file | stm32wbxx_hal_irda.h [code]

Header file of IRDA HAL module.

file | stm32wbxx_hal_irda_ex.h [code]

Header file of IRDA HAL Extended module.

file | stm32wbxx_hal_iwdg.h [code]

Header file of IWDG HAL module.

file | stm32wbxx_hal_lcd.h [code]

Header file of LCD Controller HAL module.

file | stm32wbxx_hal_lptim.h [code]

Header file of LPTIM HAL module.

file | stm32wbxx_hal_pcd.h [code]

Header file of PCD HAL module.

file | stm32wbxx_hal_pcd_ex.h [code]

Header file of PCD HAL Extension module.

file | stm32wbxx_hal_pka.h [code]

Header file of PKA HAL module.

file | stm32wbxx_hal_pwr.h [code]

Header file of PWR HAL module.

file | stm32wbxx_hal_pwr_ex.h [code]

Header file of PWR HAL Extended module.

file | stm32wbxx_hal_qspi.h [code]

Header file of QSPI HAL module.

file | stm32wbxx_hal_rcc.h [code]

Header file of RCC HAL module.

file | stm32wbxx_hal_rcc_ex.h [code]

Header file of RCC HAL Extended module.

file | stm32wbxx_hal_rng.h [code]

Header file of RNG HAL module.

file | stm32wbxx_hal_rtc.h [code]

Header file of RTC HAL module.

file | stm32wbxx_hal_rtc_ex.h [code]

Header file of RTC HAL Extended module.

file | stm32wbxx_hal_sai.h [code]

Header file of SAI HAL module.

file | stm32wbxx_hal_sai_ex.h [code]

Header file of SAI HAL extended module.

file | stm32wbxx_hal_smartcard.h [code]

Header file of SMARTCARD HAL module.

file | stm32wbxx_hal_smartcard_ex.h [code]

Header file of SMARTCARD HAL Extended module.

file | stm32wbxx_hal_smbus.h [code]

Header file of SMBUS HAL module.

file | stm32wbxx_hal_spi.h [code]

Header file of SPI HAL module.

file | stm32wbxx_hal_spi_ex.h [code]

Header file of SPI HAL Extended module.

file | stm32wbxx_hal_tim.h [code]

Header file of TIM HAL module.

file | stm32wbxx_hal_tim_ex.h [code]

Header file of TIM HAL Extended module.

file | stm32wbxx_hal_tsc.h [code]

Header file of TSC HAL module.

file | stm32wbxx_hal_uart.h [code]

Header file of UART HAL module.

file | stm32wbxx_hal_uart_ex.h [code]

Header file of UART HAL Extended module.

file | stm32wbxx_hal_usart.h [code]

Header file of USART HAL module.

file | stm32wbxx_hal_usart_ex.h [code]

Header file of USART HAL Extended module.

file | stm32wbxx_hal_wwdg.h [code]

Header file of WWDG HAL module.

file | stm32wbxx_ll_adc.h [code]

Header file of ADC LL module.

file | stm32wbxx_ll_bus.h [code]

Header file of BUS LL module.

file | stm32wbxx_ll_comp.h [code]

Header file of COMP LL module.

file | stm32wbxx_ll_cortex.h [code]

Header file of CORTEX LL module.

file | stm32wbxx_ll_crc.h [code]

Header file of CRC LL module.

file | stm32wbxx_ll_crs.h [code]

CRS LL module driver.

file | stm32wbxx_ll_dma.h [code]

Header file of DMA LL module.

file | stm32wbxx_ll_dmamux.h [code]

Header file of DMAMUX LL module.

file | stm32wbxx_ll_exti.h [code]

Header file of EXTI LL module.

file | stm32wbxx_ll_gpio.h [code]

Header file of GPIO LL module.

file | stm32wbxx_ll_hsem.h [code]

Header file of HSEM LL module.

file | stm32wbxx_ll_i2c.h [code]

Header file of I2C LL module.

file | stm32wbxx_ll_ipcc.h [code]

Header file of IPCC LL module.

file | stm32wbxx_ll_iwdg.h [code]

Header file of IWDG LL module.

file | stm32wbxx_ll_lptim.h [code]

Header file of LPTIM LL module.

file | stm32wbxx_ll_lpuart.h [code]

Header file of LPUART LL module.

file | stm32wbxx_ll_pka.h [code]

Header file of PKA LL module.

file | stm32wbxx_ll_pwr.h [code]

Header file of PWR LL module.

file | stm32wbxx_ll_rcc.h [code]

Header file of RCC LL module.

file | stm32wbxx_ll_rng.h [code]

Header file of RNG LL module.

file | stm32wbxx_ll_rtc.h [code]

Header file of RTC LL module.

file | stm32wbxx_ll_spi.h [code]

Header file of SPI LL module.

file | stm32wbxx_ll_system.h [code]

Header file of SYSTEM LL module.

file | stm32wbxx_ll_tim.h [code]

Header file of TIM LL module.

file | stm32wbxx_ll_usart.h [code]

Header file of USART LL module.

file | stm32wbxx_ll_utils.h [code]

Header file of UTILS LL module.

file | stm32wbxx_ll_wwdg.h [code]

Header file of WWDG LL module.

Generated on Fri Sep 6 2019 11:34:57 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: Directories

Directories
This directory hierarchy is sorted roughly, but not completely, alphabetically:
  • Firmware
    • Drivers
      • STM32WBxx_HAL_Driver
        • Inc
        • Src
Generated on Fri Sep 6 2019 11:34:58 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DMA_rmtollPages.txt File Reference

  • File List
  • Globals
DMA_rmtollPages.txt File Reference
Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: DMAMUX_rmtollPages.txt File Reference

  • File List
  • Globals
DMAMUX_rmtollPages.txt File Reference
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STM32WB55xx HAL User Manual: EXTI_rmtollPages.txt File Reference

  • File List
  • Globals
EXTI_rmtollPages.txt File Reference
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STM32WB55xx HAL User Manual: File List

  • File List
  • Globals
File List
Here is a list of all files with brief descriptions:
stm32wbxx_hal.c [code] | HAL module driver. This is the common part of the HAL initialization
stm32wbxx_hal.h [code] | This file contains all the functions prototypes for the HAL module driver
stm32wbxx_hal_adc.c [code] | This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Initialization and de-initialization functions ++ Initialization and Configuration of ADC + Operation functions ++ Start, stop, get result of conversions of regular group, using 3 possible modes: polling, interruption or DMA. + Control functions ++ Channels configuration on regular group ++ Analog Watchdog configuration + State functions ++ ADC state machine management ++ Interrupts and flags management Other functions (extended functions) are available in file "stm32wbxx_hal_adc_ex.c"
stm32wbxx_hal_adc.h [code] | Header file of ADC HAL module
stm32wbxx_hal_adc_ex.c [code] | This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Operation functions ++ Start, stop, get result of conversions of ADC group injected, using 2 possible modes: polling, interruption. ++ Calibration +++ ADC automatic self-calibration +++ Calibration factors get or set + Control functions ++ Channels configuration on ADC group injected + State functions ++ ADC group injected contexts queue management Other functions (generic functions) are available in file "stm32wbxx_hal_adc.c"
stm32wbxx_hal_adc_ex.h [code] | Header file of ADC HAL extended module
stm32wbxx_hal_comp.c [code] | COMP HAL module driver. This file provides firmware functions to manage the following functionalities of the COMP peripheral: + Initialization and de-initialization functions + Start/Stop operation functions in polling mode + Start/Stop operation functions in interrupt mode (through EXTI interrupt) + Peripheral control functions + Peripheral state functions
stm32wbxx_hal_comp.h [code] | Header file of COMP HAL module
stm32wbxx_hal_conf.h [code] | HAL configuration file
stm32wbxx_hal_cortex.c [code] | CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and Configuration functions + Peripheral Control functions
stm32wbxx_hal_cortex.h [code] | Header file of CORTEX HAL module
stm32wbxx_hal_crc.c [code] | CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the Cyclic Redundancy Check (CRC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions
stm32wbxx_hal_crc.h [code] | Header file of CRC HAL module
stm32wbxx_hal_crc_ex.c [code] | Extended CRC HAL module driver. This file provides firmware functions to manage the extended functionalities of the CRC peripheral
stm32wbxx_hal_crc_ex.h [code] | Header file of CRC HAL extended module
stm32wbxx_hal_cryp.c [code] | CRYP HAL module driver. This file provides firmware functions to manage the following functionalities of the Cryptography (CRYP) peripheral: + Initialization, de-initialization, set config and get config functions + DES/TDES, AES processing functions + DMA callback functions + CRYP IRQ handler management + Peripheral State functions
stm32wbxx_hal_cryp.h [code] | Header file of CRYP HAL module
stm32wbxx_hal_cryp_ex.c [code] | CRYPEx HAL module driver. This file provides firmware functions to manage the extended functionalities of the Cryptography (CRYP) peripheral
stm32wbxx_hal_cryp_ex.h [code] | Header file of CRYPEx HAL module
stm32wbxx_hal_dma.c [code] | DMA HAL module driver. This file provides firmware functions to manage the following functionalities of the Direct Memory Access (DMA) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and errors functions
stm32wbxx_hal_dma.h [code] | Header file of DMA HAL module
stm32wbxx_hal_dma_ex.c [code] | DMA Extension HAL module driver This file provides firmware functions to manage the following functionalities of the DMA Extension peripheral: + Extended features functions
stm32wbxx_hal_dma_ex.h [code] | Header file of DMA HAL extension module
stm32wbxx_hal_exti.c [code] | EXTI HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (EXTI) peripheral: + Initialization and de-initialization functions + IO operation functions
stm32wbxx_hal_exti.h [code] | Header file of EXTI HAL module
stm32wbxx_hal_flash.c [code] | FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral Errors functions
stm32wbxx_hal_flash.h [code] | Header file of FLASH HAL module
stm32wbxx_hal_flash_ex.c [code] | Extended FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the FLASH extended peripheral: + Extended programming operations functions
stm32wbxx_hal_flash_ex.h [code] | Header file of FLASH HAL Extended module
stm32wbxx_hal_gpio.c [code] | GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions
stm32wbxx_hal_gpio.h [code] | Header file of GPIO HAL module
stm32wbxx_hal_gpio_ex.h [code] | Header file of GPIO HAL Extended module
stm32wbxx_hal_hsem.c [code] | HSEM HAL module driver. This file provides firmware functions to manage the following functionalities of the semaphore peripheral: + Semaphore Take function (2-Step Procedure) , non blocking + Semaphore FastTake function (1-Step Procedure) , non blocking + Semaphore Status check + Semaphore Clear Key Set and Get + Release and release all functions + Semaphore notification enabling and disabling and callnack functions + IRQ handler management
stm32wbxx_hal_hsem.h [code] | Header file of HSEM HAL module
stm32wbxx_hal_i2c.c [code] | I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions
stm32wbxx_hal_i2c.h [code] | Header file of I2C HAL module
stm32wbxx_hal_i2c_ex.c [code] | I2C Extended HAL module driver. This file provides firmware functions to manage the following functionalities of I2C Extended peripheral: + Extended features functions
stm32wbxx_hal_i2c_ex.h [code] | Header file of I2C HAL Extended module
stm32wbxx_hal_ipcc.c [code] | IPCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter-Processor communication controller peripherals (IPCC). + Initialization and de-initialization functions + Configuration, notification and interrupts handling + Peripheral State and Error functions
stm32wbxx_hal_ipcc.h [code] | Header file of Mailbox HAL module
stm32wbxx_hal_irda.c [code] | IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA (Infrared Data Association) Peripheral (IRDA) + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions + Peripheral Control functions
stm32wbxx_hal_irda.h [code] | Header file of IRDA HAL module
stm32wbxx_hal_irda_ex.h [code] | Header file of IRDA HAL Extended module
stm32wbxx_hal_iwdg.c [code] | IWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Independent Watchdog (IWDG) peripheral: + Initialization and Start functions + IO operation functions
stm32wbxx_hal_iwdg.h [code] | Header file of IWDG HAL module
stm32wbxx_hal_lcd.c [code] | LCD Controller HAL module driver. This file provides firmware functions to manage the following functionalities of the LCD Controller (LCD) peripheral: + Initialization/de-initialization methods + I/O operation methods + Peripheral State methods
stm32wbxx_hal_lcd.h [code] | Header file of LCD Controller HAL module
stm32wbxx_hal_lptim.c [code] | LPTIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Low Power Timer (LPTIM) peripheral: + Initialization and de-initialization functions. + Start/Stop operation functions in polling mode. + Start/Stop operation functions in interrupt mode. + Reading operation functions. + Peripheral State functions
stm32wbxx_hal_lptim.h [code] | Header file of LPTIM HAL module
stm32wbxx_hal_pcd.c [code] | PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions
stm32wbxx_hal_pcd.h [code] | Header file of PCD HAL module
stm32wbxx_hal_pcd_ex.c [code] | PCD Extended HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Extended features functions
stm32wbxx_hal_pcd_ex.h [code] | Header file of PCD HAL Extension module
stm32wbxx_hal_pka.c [code] | PKA HAL module driver. This file provides firmware functions to manage the following functionalities of public key accelerator(PKA): + Initialization and de-initialization functions + Start an operation + Retrieve the operation result
stm32wbxx_hal_pka.h [code] | Header file of PKA HAL module
stm32wbxx_hal_pwr.c [code] | PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Initialization/de-initialization functions + Peripheral Control functions
stm32wbxx_hal_pwr.h [code] | Header file of PWR HAL module
stm32wbxx_hal_pwr_ex.c [code] | Extended PWR HAL module driver. This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Extended Initialization and de-initialization functions + Extended Peripheral Control functions
stm32wbxx_hal_pwr_ex.h [code] | Header file of PWR HAL Extended module
stm32wbxx_hal_qspi.c [code] | QSPI HAL module driver. This file provides firmware functions to manage the following functionalities of the QuadSPI interface (QSPI). + Initialization and de-initialization functions + Indirect functional mode management + Memory-mapped functional mode management + Auto-polling functional mode management + Interrupts and flags management + DMA channel configuration for indirect functional mode + Errors management and abort functionality
stm32wbxx_hal_qspi.h [code] | Header file of QSPI HAL module
stm32wbxx_hal_rcc.c [code] | RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions
stm32wbxx_hal_rcc.h [code] | Header file of RCC HAL module
stm32wbxx_hal_rcc_ex.c [code] | Extended RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extended peripheral: + Extended Peripheral Control functions + Extended Clock management functions + Extended Clock Recovery System Control functions
stm32wbxx_hal_rcc_ex.h [code] | Header file of RCC HAL Extended module
stm32wbxx_hal_rng.c [code] | RNG HAL module driver. This file provides firmware functions to manage the following functionalities of the Random Number Generator (RNG) peripheral: + Initialization and configuration functions + Peripheral Control functions + Peripheral State functions
stm32wbxx_hal_rng.h [code] | Header file of RNG HAL module
stm32wbxx_hal_rtc.c [code] | RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real-Time Clock (RTC) peripheral: + Initialization + Calendar (Time and Date) configuration + Alarms (Alarm A and Alarm B) configuration + WakeUp Timer configuration + TimeStamp configuration + Tampers configuration + Backup Data Registers configuration + RTC Tamper and TimeStamp Pins Selection + Interrupts and flags management
stm32wbxx_hal_rtc.h [code] | Header file of RTC HAL module
stm32wbxx_hal_rtc_ex.c [code] | Extended RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extended peripheral: + RTC Time Stamp functions + RTC Tamper functions + RTC Wake-up functions + Extended Control functions + Extended RTC features functions
stm32wbxx_hal_rtc_ex.h [code] | Header file of RTC HAL Extended module
stm32wbxx_hal_sai.c [code] | SAI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Audio Interface (SAI) peripheral: + Initialization/de-initialization functions + I/O operation functions + Peripheral Control functions + Peripheral State functions
stm32wbxx_hal_sai.h [code] | Header file of SAI HAL module
stm32wbxx_hal_sai_ex.c [code] | SAI Extended HAL module driver. This file provides firmware functions to manage the following functionality of the SAI Peripheral Controller: + Modify PDM microphone delays
stm32wbxx_hal_sai_ex.h [code] | Header file of SAI HAL extended module
stm32wbxx_hal_smartcard.c [code] | SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions
stm32wbxx_hal_smartcard.h [code] | Header file of SMARTCARD HAL module
stm32wbxx_hal_smartcard_ex.c [code] | SMARTCARD HAL module driver. This file provides extended firmware functions to manage the following functionalities of the SmartCard. + Initialization and de-initialization functions + Peripheral Control functions
stm32wbxx_hal_smartcard_ex.h [code] | Header file of SMARTCARD HAL Extended module
stm32wbxx_hal_smbus.c [code] | SMBUS HAL module driver. This file provides firmware functions to manage the following functionalities of the System Management Bus (SMBus) peripheral, based on I2C principles of operation : + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions
stm32wbxx_hal_smbus.h [code] | Header file of SMBUS HAL module
stm32wbxx_hal_spi.c [code] | SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions
stm32wbxx_hal_spi.h [code] | Header file of SPI HAL module
stm32wbxx_hal_spi_ex.c [code] | Extended SPI HAL module driver. This file provides firmware functions to manage the following SPI peripheral extended functionalities : + IO operation functions
stm32wbxx_hal_spi_ex.h [code] | Header file of SPI HAL Extended module
stm32wbxx_hal_tim.c [code] | TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + TIM Time Base Initialization + TIM Time Base Start + TIM Time Base Start Interruption + TIM Time Base Start DMA + TIM Output Compare/PWM Initialization + TIM Output Compare/PWM Channel Configuration + TIM Output Compare/PWM Start + TIM Output Compare/PWM Start Interruption + TIM Output Compare/PWM Start DMA + TIM Input Capture Initialization + TIM Input Capture Channel Configuration + TIM Input Capture Start + TIM Input Capture Start Interruption + TIM Input Capture Start DMA + TIM One Pulse Initialization + TIM One Pulse Channel Configuration + TIM One Pulse Start + TIM Encoder Interface Initialization + TIM Encoder Interface Start + TIM Encoder Interface Start Interruption + TIM Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + TIM OCRef clear configuration + TIM External Clock configuration
stm32wbxx_hal_tim.h [code] | Header file of TIM HAL module
stm32wbxx_hal_tim_ex.c [code] | TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer Extended peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal break and dead time configuration + Time Master and Slave synchronization configuration + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + Time OCRef clear configuration + Timer remapping capabilities configuration
stm32wbxx_hal_tim_ex.h [code] | Header file of TIM HAL Extended module
stm32wbxx_hal_tsc.c [code] | This file provides firmware functions to manage the following functionalities of the Touch Sensing Controller (TSC) peripheral: + Initialization and De-initialization + Channel IOs, Shield IOs and Sampling IOs configuration + Start and Stop an acquisition + Read acquisition result + Interrupts and flags management
stm32wbxx_hal_tsc.h [code] | Header file of TSC HAL module
stm32wbxx_hal_uart.c [code] | UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions
stm32wbxx_hal_uart.h [code] | Header file of UART HAL module
stm32wbxx_hal_uart_ex.c [code] | Extended UART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + Initialization and de-initialization functions + Peripheral Control functions
stm32wbxx_hal_uart_ex.h [code] | Header file of UART HAL Extended module
stm32wbxx_hal_usart.c [code] | USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter Peripheral (USART). + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions
stm32wbxx_hal_usart.h [code] | Header file of USART HAL module
stm32wbxx_hal_usart_ex.c [code] | Extended USART HAL module driver. This file provides firmware functions to manage the following extended functionalities of the Universal Synchronous Receiver Transmitter Peripheral (USART). + Peripheral Control functions
stm32wbxx_hal_usart_ex.h [code] | Header file of USART HAL Extended module
stm32wbxx_hal_wwdg.c [code] | WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and Configuration functions + IO operation functions
stm32wbxx_hal_wwdg.h [code] | Header file of WWDG HAL module
stm32wbxx_ll_adc.c [code] | ADC LL module driver
stm32wbxx_ll_adc.h [code] | Header file of ADC LL module
stm32wbxx_ll_bus.h [code] | Header file of BUS LL module
stm32wbxx_ll_comp.c [code] | COMP LL module driver
stm32wbxx_ll_comp.h [code] | Header file of COMP LL module
stm32wbxx_ll_cortex.h [code] | Header file of CORTEX LL module
stm32wbxx_ll_crc.c [code] | CRC LL module driver
stm32wbxx_ll_crc.h [code] | Header file of CRC LL module
stm32wbxx_ll_crs.c [code] |
stm32wbxx_ll_crs.h [code] | CRS LL module driver
stm32wbxx_ll_dma.c [code] | DMA LL module driver
stm32wbxx_ll_dma.h [code] | Header file of DMA LL module
stm32wbxx_ll_dmamux.h [code] | Header file of DMAMUX LL module
stm32wbxx_ll_exti.c [code] | EXTI LL module driver
stm32wbxx_ll_exti.h [code] | Header file of EXTI LL module
stm32wbxx_ll_gpio.c [code] | GPIO LL module driver
stm32wbxx_ll_gpio.h [code] | Header file of GPIO LL module
stm32wbxx_ll_hsem.h [code] | Header file of HSEM LL module
stm32wbxx_ll_i2c.c [code] | I2C LL module driver
stm32wbxx_ll_i2c.h [code] | Header file of I2C LL module
stm32wbxx_ll_ipcc.h [code] | Header file of IPCC LL module
stm32wbxx_ll_iwdg.h [code] | Header file of IWDG LL module
stm32wbxx_ll_lptim.c [code] | LPTIM LL module driver
stm32wbxx_ll_lptim.h [code] | Header file of LPTIM LL module
stm32wbxx_ll_lpuart.c [code] | LPUART LL module driver
stm32wbxx_ll_lpuart.h [code] | Header file of LPUART LL module
stm32wbxx_ll_pka.c [code] | PKA LL module driver
stm32wbxx_ll_pka.h [code] | Header file of PKA LL module
stm32wbxx_ll_pwr.c [code] | PWR LL module driver
stm32wbxx_ll_pwr.h [code] | Header file of PWR LL module
stm32wbxx_ll_rcc.c [code] | RCC LL module driver
stm32wbxx_ll_rcc.h [code] | Header file of RCC LL module
stm32wbxx_ll_rng.c [code] | RNG LL module driver
stm32wbxx_ll_rng.h [code] | Header file of RNG LL module
stm32wbxx_ll_rtc.c [code] | RTC LL module driver
stm32wbxx_ll_rtc.h [code] | Header file of RTC LL module
stm32wbxx_ll_spi.c [code] | SPI LL module driver
stm32wbxx_ll_spi.h [code] | Header file of SPI LL module
stm32wbxx_ll_system.h [code] | Header file of SYSTEM LL module
stm32wbxx_ll_tim.c [code] | TIM LL module driver
stm32wbxx_ll_tim.h [code] | Header file of TIM LL module
stm32wbxx_ll_usart.c [code] | USART LL module driver
stm32wbxx_ll_usart.h [code] | Header file of USART LL module
stm32wbxx_ll_utils.c [code] | UTILS LL module driver
stm32wbxx_ll_utils.h [code] | Header file of UTILS LL module
stm32wbxx_ll_wwdg.h [code] | Header file of WWDG LL module
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STM32WB55xx HAL User Manual: GPIO_rmtollPages.txt File Reference

  • File List
  • Globals
GPIO_rmtollPages.txt File Reference
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STM32WB55xx HAL User Manual: ADC

Modules
ADC
STM32WBxx_HAL_Driver

ADC HAL module driver. More...

Modules

ADC Private Constants
ADC Exported Functions
ADC Private Functions
ADC Exported Types
ADC Exported Constants
ADC Private Macros
ADC Exported Macros

Detailed Description

ADC HAL module driver.

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STM32WB55xx HAL User Manual: ADC Exported Functions

Modules
ADC Exported Functions
ADC

Modules

Initialization and de-initialization functions

ADC Initialization and Configuration functions.

ADC Input and Output operation functions

ADC IO operation functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State functions

ADC Peripheral State functions.

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STM32WB55xx HAL User Manual: ADC Exported Macros

Modules
ADC Exported Macros
ADC

Modules

HAL ADC macro to manage HAL ADC handle, IT and flags.
HAL ADC helper macro
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STM32WB55xx HAL User Manual: ADC Exported Init structure

Data Structures
ADC Exported Init structure
ADC

Data Structures

struct | LL_ADC_CommonInitTypeDef
Structure definition of some features of ADC common parameters and multimode (all ADC instances belonging to the same ADC common instance). More...
struct | LL_ADC_InitTypeDef
Structure definition of some features of ADC instance. More...
struct | LL_ADC_REG_InitTypeDef
Structure definition of some features of ADC group regular. More...
struct | LL_ADC_INJ_InitTypeDef
Structure definition of some features of ADC group injected. More...
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STM32WB55xx HAL User Manual: ADC Exported Constants

Modules
ADC Exported Constants
ADC

Modules

ADC flags

Flags defines which can be used with LL_ADC_ReadReg function.

ADC interruptions for configuration (interruption enable or disable)

IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions.

ADC registers compliant with specific purpose
ADC common - Clock source
ADC common - Measurement path to internal channels
ADC instance - Resolution
ADC instance - Data alignment
ADC instance - Low power mode
ADC instance - Offset number
ADC instance - Offset state
ADC instance - Groups
ADC instance - Channel number
ADC group regular - Trigger source
ADC group regular - Trigger edge
ADC group regular - Continuous mode
ADC group regular - DMA transfer of ADC conversion data
ADC group regular - Overrun behavior on conversion data
ADC group regular - Sequencer scan length
ADC group regular - Sequencer discontinuous mode
ADC group regular - Sequencer ranks
ADC group injected - Trigger source
ADC group injected - Trigger edge
ADC group injected - Automatic trigger mode
ADC group injected - Context queue mode
ADC group injected - Sequencer scan length
ADC group injected - Sequencer discontinuous mode
ADC group injected - Sequencer ranks
Channel - Sampling time
Channel - Single or differential ending
Analog watchdog - Analog watchdog number
Analog watchdog - Monitored channels
Analog watchdog - Thresholds
Oversampling - Oversampling scope
Oversampling - Discontinuous mode
Oversampling - Ratio
Oversampling - Data shift
Definitions of ADC hardware constraints delays
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STM32WB55xx HAL User Manual: ADC Exported Functions

Modules
ADC Exported Functions
ADC

Modules

ADC DMA management
Configuration of ADC hierarchical scope: common to several ADC instances
Configuration of ADC hierarchical scope: ADC instance
Configuration of ADC hierarchical scope: group regular
Configuration of ADC hierarchical scope: group injected
Configuration of ADC hierarchical scope: channels
Configuration of ADC transversal scope: analog watchdog
Configuration of ADC transversal scope: oversampling
Operation on ADC hierarchical scope: ADC instance
Operation on ADC hierarchical scope: group regular
Operation on ADC hierarchical scope: group injected
ADC flag management
ADC IT management
Initialization and de-initialization functions
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STM32WB55xx HAL User Manual: ADC Exported Macros

Modules
ADC Exported Macros
ADC

Modules

Common write and read registers Macros
ADC helper macro
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STM32WB55xx HAL User Manual: ADCEx

Modules
ADCEx
STM32WBxx_HAL_Driver

ADC Extended HAL module driver. More...

Modules

ADC Extended Private Constants
ADC Extended Exported Functions
ADC Extended Exported Types
ADC Extended Exported Constants
ADC Extended Private Macros

Detailed Description

ADC Extended HAL module driver.

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC Extended Exported Constants

Modules
ADC Extended Exported Constants
ADCEx

Modules

ADC group injected trigger source
ADC group injected trigger edge (when external trigger is selected)
Channel - Single or differential ending
ADC instance - Offset number
ADC group injected - Sequencer ranks
ADC instance - Groups
ADCx CFGR fields
ADCx SMPR1 fields
ADCx CFGR sub fields
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STM32WB55xx HAL User Manual: ADC Extended Exported Functions

Modules
ADC Extended Exported Functions
ADCEx

Modules

Extended Input and Output operation functions

Extended IO operation functions.

ADC Extended Peripheral Control functions

ADC Extended Peripheral Control functions.

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: ADC Extended Exported Types

Data Structures
ADC Extended Exported Types
ADCEx

Data Structures

struct | ADC_InjOversamplingTypeDef
ADC Injected Conversion Oversampling structure definition. More...
struct | ADC_InjectionConfTypeDef
Structure definition of ADC group injected and ADC channel affected to ADC group injected. More...
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STM32WB55xx HAL User Manual: BUS Exported Constants

Modules
BUS Exported Constants
BUS

Modules

AHB1 GRP1 PERIPH
AHB2 GRP1 PERIPH
AHB3 GRP1 PERIPH
APB1 GRP1 PERIPH
APB1 GRP2 PERIPH
APB2 GRP1 PERIPH
APB3 GRP1 PERIPH
C2 AHB1 GRP1 PERIPH
C2 AHB2 GRP1 PERIPH
C2 AHB3 GRP1 PERIPH
C2 APB1 GRP1 PERIPH
C2 APB1 GRP2 PERIPH
C2 APB2 GRP1 PERIPH
C2 APB3 GRP1 PERIPH
Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: BUS Exported Functions

Modules
BUS Exported Functions
BUS

Modules

AHB1
AHB2
AHB3
APB1
APB2
APB3
C2 AHB1
C2 AHB2
C2 AHB3
C2 APB1
C2 APB2
C2 APB3
Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: COMP

Modules
COMP
STM32WBxx_HAL_Driver

COMP HAL module driver. More...

Modules

COMP Exported Functions
COMP Exported Types
COMP Exported Constants
COMP Exported Macros
COMP Private Constants
COMP Private Macros

Detailed Description

COMP HAL module driver.

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STM32WB55xx HAL User Manual: COMP Exported Constants

Modules
COMP Exported Constants
COMP

Modules

COMP Error Code
COMP Window Mode
COMP power mode
COMP input plus (non-inverting input)
COMP input minus (inverting input)
COMP hysteresis
COMP output Polarity
COMP blanking source
COMP Output Level
COMP output to EXTI
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STM32WB55xx HAL User Manual: COMP Exported Functions

Modules
COMP Exported Functions
COMP

Modules

Initialization/de-initialization functions

Initialization and de-initialization functions.

Start-Stop operation functions

Start-Stop operation functions.

Peripheral Control functions

Management functions.

Peripheral State functions

Peripheral State functions.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: COMP Exported Macros

Modules
COMP Exported Macros
COMP

Modules

COMP Handle Management
COMP external interrupt line management
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STM32WB55xx HAL User Manual: COMP Exported Init structure

Data Structures
COMP Exported Init structure
COMP

Data Structures

struct LL_COMP_InitTypeDef
Structure definition of some features of COMP instance. More...
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STM32WB55xx HAL User Manual: COMP Exported Constants

Modules
COMP Exported Constants
COMP

Modules

Comparator common modes - Window mode
Comparator modes - Power mode
Comparator inputs - Input plus (input non-inverting) selection
Comparator inputs - Input minus (input inverting) selection
Comparator input - Hysteresis
Comparator output - Output polarity
Comparator output - Blanking source
Comparator output - Output level
Definitions of COMP hardware constraints delays
Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: COMP Exported Functions

Modules
COMP Exported Functions
COMP

Modules

Configuration of COMP hierarchical scope: common to several COMP instances
Configuration of comparator modes
Configuration of comparator inputs
Configuration of comparator output
Operation on comparator instance
Initialization and de-initialization functions
Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: COMP Exported Macros

Modules
COMP Exported Macros
COMP

Modules

Common write and read registers macro
COMP helper macro
Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: COMP Private Macros

Modules
COMP Private Macros
COMP

Modules

COMP private macros to get EXTI line associated with comparators
COMP private macros to check input parameters
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STM32WB55xx HAL User Manual: CORTEX

Modules
CORTEX
STM32WBxx_HAL_Driver

CORTEX HAL module driver. More...

Modules

CORTEX Exported Types
CORTEX Exported Constants
CORTEX Exported Macros
CORTEX Exported Functions
CORTEX Private Macros

Detailed Description

CORTEX HAL module driver.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CORTEX Exported Constants

Modules
CORTEX Exported Constants
CORTEX

Modules

CORTEX Preemption Priority Group
CORTEX SysTick clock source
CORTEX MPU HFNMI and PRIVILEGED Access control
CORTEX MPU Region Enable
CORTEX MPU Instruction Access
CORTEX MPU Instruction Access Shareable
CORTEX MPU Instruction Access Cacheable
CORTEX MPU Instruction Access Bufferable
CORTEX MPU TEX Levels
CORTEX MPU Region Size
CORTEX MPU Region Permission Attributes
CORTEX MPU Region Number
Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CORTEX Exported Functions

Modules
CORTEX Exported Functions
CORTEX

Modules

Initialization and Configuration functions

Initialization and Configuration functions.

Peripheral Control functions

Cortex control functions.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CORTEX Exported Types

Modules
CORTEX Exported Types
CORTEX

Modules

MPU Region Initialization Structure Definition

MPU Region initialization structure.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CORTEX Exported Constants

Modules
CORTEX Exported Constants
CORTEX

Modules

SYSTICK Clock Source
Handler Fault type
MPU Control
MPU Region Number
MPU Region Size
MPU Region Privileges
MPU TEX Level
MPU Instruction Access
MPU Shareable Access
MPU Cacheable Access
MPU Bufferable Access
Generated on Fri Sep 6 2019 11:34:49 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CORTEX Exported Functions

Modules
CORTEX Exported Functions
CORTEX

Modules

SYSTICK
LOW POWER MODE
HANDLER
MCU INFO
MPU
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STM32WB55xx HAL User Manual: MPU Region Initialization Structure Definition

Data Structures
MPU Region Initialization Structure Definition
CORTEX Exported Types

MPU Region initialization structure. More...

Data Structures

struct MPU_Region_InitTypeDef

Detailed Description

MPU Region initialization structure.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CRC

Modules
CRC
STM32WBxx_HAL_Driver

CRC HAL module driver. More...

Modules

CRC Private Functions
CRC Exported Functions
CRC Exported Types
CRC Exported Constants
CRC Exported Macros
CRC Private Macros

Detailed Description

CRC HAL module driver.

Generated on Fri Sep 6 2019 11:34:41 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: CRC Exported Constants

Modules
CRC Exported Constants
CRC

Modules

Default CRC generating polynomial
Default CRC computation initialization value
Indicates whether or not default polynomial is used
Indicates whether or not default init value is used
Polynomial sizes to configure the peripheral
CRC polynomial possible sizes actual definitions
Input Buffer Format
CRC API aliases
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STM32WB55xx HAL User Manual: CRC Exported Functions

Modules
CRC Exported Functions
CRC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Peripheral Control functions

management functions.

Peripheral State functions

Peripheral State functions.

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STM32WB55xx HAL User Manual: CRC Exported Constants

Modules
CRC Exported Constants
CRC

Modules

Polynomial length
Input Data Reverse
Output Data Reverse
Default CRC generating polynomial value

Normal representation of this polynomial value is X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 .

Default CRC computation initialization value
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STM32WB55xx HAL User Manual: CRC Exported Functions

Modules
CRC Exported Functions
CRC

Modules

CRC Configuration functions
Data_Management
Initialization and de-initialization functions
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STM32WB55xx HAL User Manual: CRC Exported Macros

Modules
CRC Exported Macros
CRC

Modules

Common Write and read registers Macros
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STM32WB55xx HAL User Manual: CRCEx

Modules
CRCEx
STM32WBxx_HAL_Driver

CRC Extended HAL module driver. More...

Modules

CRC Extended Exported Functions
CRC Extended Exported Constants
CRC Extended Exported Macros
CRC Extended Private Macros

Detailed Description

CRC Extended HAL module driver.

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STM32WB55xx HAL User Manual: CRC Extended Exported Constants

Modules
CRC Extended Exported Constants
CRCEx

Modules

Input Data Inversion Modes
Output Data Inversion Modes
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STM32WB55xx HAL User Manual: CRC Extended Exported Functions

Modules
CRC Extended Exported Functions
CRCEx

Modules

Extended Initialization/de-initialization functions

Extended Initialization and Configuration functions.

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STM32WB55xx HAL User Manual: CRS Exported Constants

Modules
CRS Exported Constants
CRS

Modules

Get Flags Defines

Flags defines which can be used with LL_CRS_ReadReg function.

IT Defines

IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions.

Synchronization Signal Divider
Synchronization Signal Source
Synchronization Signal Polarity
Frequency Error Direction
Default Values
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STM32WB55xx HAL User Manual: CRS Exported Functions

Modules
CRS Exported Functions
CRS

Modules

Configuration
CRS_Management
FLAG_Management
IT_Management
Initialization and de-initialization functions
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STM32WB55xx HAL User Manual: CRS Exported Macros

Modules
CRS Exported Macros
CRS

Modules

Common Write and read registers Macros
Exported_Macros_Calculate_Reload
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STM32WB55xx HAL User Manual: CRYP

Modules
CRYP
STM32WBxx_HAL_Driver

CRYP HAL module driver. More...

Modules

CRYP Exported Types
CRYP Exported Constants
CRYP Exported Macros
CRYP Exported Functions
CRYP Private Macros
CRYP Private Constants
CRYP Private Defines
CRYP Private Variables
CRYP Private Functions

Detailed Description

CRYP HAL module driver.

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STM32WB55xx HAL User Manual: CRYP Exported Constants

Modules
CRYP Exported Constants
CRYP

Modules

CRYP Error Definition
CRYP Data Width Unit
CRYP Algorithm Mode
CRYP Key Size
CRYP Data Type
CRYP Interrupt
CRYP Flags
CRYP Key and IV Configuration Skip Mode
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STM32WB55xx HAL User Manual: CRYP Exported Functions

Modules
CRYP Exported Functions
CRYP

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Encryption Decryption functions

Encryption Decryption functions.

CRYP IRQ handler management

CRYP IRQ handler.

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STM32WB55xx HAL User Manual: CRYPEx

Modules
CRYPEx
STM32WBxx_HAL_Driver

CRYP Extension HAL module driver. More...

Modules

CRYPEx Private Types
CRYPEx Private Variables
CRYPEx Private Constants
CRYPEx Private Macros
CRYPEx Private Functions
CRYPEx Exported Functions
CRYPEx_Private_Defines

Detailed Description

CRYP Extension HAL module driver.

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STM32WB55xx HAL User Manual: CRYPEx Exported Functions

Modules
CRYPEx Exported Functions
CRYPEx

Modules

Extended AES processing functions

Extended processing functions.

Extended AES Key Derivations functions

Extended Key Derivations functions.

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STM32WB55xx HAL User Manual: DBGMCU Exported Macros

Modules
DBGMCU Exported Macros
HAL Exported Macros

Modules

DBGMCU CPU1 APBx GRPx STOP IP

Freeze and Unfreeze Peripherals in Debug mode.

DBGMCU CPU2 APBx GRPx STOP IP
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STM32WB55xx HAL User Manual: DMA

Modules
DMA
STM32WBxx_HAL_Driver

DMA HAL module driver. More...

Modules

DMA Private Functions
DMA Exported Functions
DMA Exported Types
DMA Exported Constants
DMA Exported Macros
DMA Private Macros

Detailed Description

DMA HAL module driver.

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STM32WB55xx HAL User Manual: DMA Exported Constants

Modules
DMA Exported Constants
DMA

Modules

DMA Error Code
DMA request
DMA Data transfer direction
DMA Peripheral incremented mode
DMA Memory incremented mode
DMA Peripheral data size
DMA Memory data size
DMA mode
DMA Priority level
DMA interrupt enable definitions
DMA flag definitions
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STM32WB55xx HAL User Manual: DMA Exported Functions

Modules
DMA Exported Functions
DMA

Modules

Initialization and de-initialization functions

Initialization and de-initialization functions.

Input and Output operation functions

Input and Output operation functions.

Peripheral State and Errors functions

Peripheral State and Errors functions.

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STM32WB55xx HAL User Manual: DMA Exported Init structure

Data Structures
DMA Exported Init structure
DMA

Data Structures

struct LL_DMA_InitTypeDef
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STM32WB55xx HAL User Manual: DMA Exported Constants

Modules
DMA Exported Constants
DMA

Modules

Clear Flags Defines

Flags defines which can be used with LL_DMA_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_DMA_ReadReg function.

IT Defines

IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions.

CHANNEL
Transfer Direction
Transfer mode
Peripheral increment mode
Memory increment mode
Peripheral data alignment
Memory data alignment
Transfer Priority level
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STM32WB55xx HAL User Manual: DMA Exported Functions

Modules
DMA Exported Functions
DMA

Modules

Configuration
FLAG_Management
IT_Management
Initialization and de-initialization functions
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STM32WB55xx HAL User Manual: DMA Exported Macros

Modules
DMA Exported Macros
DMA

Modules

Common Write and read registers macros
Convert DMAxChannely
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STM32WB55xx HAL User Manual: DMAEx

Modules
DMAEx
STM32WBxx_HAL_Driver

DMA Extended HAL module driver. More...

Modules

DMAEx Exported Functions
DMAEx Exported Types
DMAEx Exported Constants
DMAEx Private Macros

DMAEx private macros.

Detailed Description

DMA Extended HAL module driver.

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STM32WB55xx HAL User Manual: DMAEx Exported Constants

Modules
DMAEx Exported Constants
DMAEx

Modules

DMAMUX SyncSignalID selection
DMAMUX SyncPolarity selection
DMAMUX SignalGeneratorID selection
DMAMUX RequestGeneneratorPolarity selection
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STM32WB55xx HAL User Manual: DMAEx Exported Functions

Modules
DMAEx Exported Functions
DMAEx

Modules

DMAEx Extended features functions

Extended features functions.

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STM32WB55xx HAL User Manual: DMAEx Exported Types

Data Structures
DMAEx Exported Types
DMAEx

Data Structures

struct | HAL_DMA_MuxSyncConfigTypeDef
HAL DMA Synchro definition. More...
struct | HAL_DMA_MuxRequestGeneratorConfigTypeDef
HAL DMAMUX request generator parameters structure definition. More...
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STM32WB55xx HAL User Manual: DMAMUX Exported Constants

Modules
DMAMUX Exported Constants
DMAMUX

Modules

Clear Flags Defines

Flags defines which can be used with LL_DMAMUX_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_DMAMUX_ReadReg function.

IT Defines

IT defines which can be used with LL_DMA_ReadReg and LL_DMAMUX_WriteReg functions.

Transfer request
DMAMUX Channel
Synchronization Signal Polarity
Synchronization Signal Event
Request Generator Channel
External Request Signal Generation Polarity
External Request Signal Generation
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STM32WB55xx HAL User Manual: DMAMUX Exported Functions

Modules
DMAMUX Exported Functions
DMAMUX

Modules

Configuration
FLAG_Management
IT_Management
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STM32WB55xx HAL User Manual: DMAMUX Exported Macros

Modules
DMAMUX Exported Macros
DMAMUX

Modules

Common Write and read registers macros
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STM32WB55xx HAL User Manual: EXTI

Modules
EXTI
STM32WBxx_HAL_Driver

EXTI HAL module driver. More...

Modules

EXTI Private Constants

MISRA C:2012 deviation rule has been granted for following rule: Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out of bounds [0,3] in following API : HAL_EXTI_SetConfigLine HAL_EXTI_GetConfigLine HAL_EXTI_ClearConfigLine.

EXTI Exported Types
EXTI Exported Constants
EXTI Exported Macros
EXTI Private Macros
EXTI Exported Functions

EXTI Exported Functions.

Detailed Description

EXTI HAL module driver.

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STM32WB55xx HAL User Manual: EXTI Exported Constants

Modules
EXTI Exported Constants
EXTI

Modules

EXTI Line
EXTI Mode
EXTI Trigger
EXTI GPIOSel
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STM32WB55xx HAL User Manual: EXTI Exported Functions

Modules
EXTI Exported Functions
EXTI

EXTI Exported Functions. More...

Modules

Configuration functions

Configuration functions.

IO operation functions

IO operation functions.

Detailed Description

EXTI Exported Functions.

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STM32WB55xx HAL User Manual: EXTI Exported Init structure

Data Structures
EXTI Exported Init structure
EXTI

Data Structures

struct LL_EXTI_InitTypeDef
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STM32WB55xx HAL User Manual: EXTI Exported Constants

Modules
EXTI Exported Constants
EXTI

Modules

LINE
Mode
Edge Trigger
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STM32WB55xx HAL User Manual: EXTI Exported Functions

Modules
EXTI Exported Functions
EXTI

Modules

IT_Management
Event_Management
Rising_Trigger_Management
Falling_Trigger_Management
Software_Interrupt_Management
Flag_Management
Initialization and de-initialization functions
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STM32WB55xx HAL User Manual: EXTI Exported Macros

Modules
EXTI Exported Macros
EXTI

Modules

Common Write and read registers Macros
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STM32WB55xx HAL User Manual: FLASH

Modules
FLASH
STM32WBxx_HAL_Driver

FLASH HAL module driver. More...

Modules

FLASH Private Variables
FLASH Private Functions
FLASH Exported Functions
FLASH Exported Types
FLASH Exported Constants
FLASH Exported Macros

macros to control FLASH features

FLASH Interrupts Macros

macros to handle FLASH interrupts

FLASH Exported Variables
FLASH Private Types
FLASH Private Constants
SRAM memory size
FLASH Private Macros

Detailed Description

FLASH HAL module driver.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: FLASH Exported Constants

Modules
FLASH Exported Constants
FLASH

Modules

FLASH Keys
FLASH Latency
FLASH Flags Definition
RAM2A address range in secure mode
RAM2B address range in secure mode
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STM32WB55xx HAL User Manual: FLASH Exported Functions

Modules
FLASH Exported Functions
FLASH

Modules

Programming operation functions

Programming operation functions.

Peripheral Control functions

Management functions.

Peripheral State and Errors functions

Peripheral Errors functions.

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STM32WB55xx HAL User Manual: FLASH Exported Types

Data Structures
FLASH Exported Types
FLASH

Data Structures

struct | FLASH_EraseInitTypeDef
FLASH Erase structure definition. More...
struct | FLASH_OBProgramInitTypeDef
FLASH Option Bytes Program structure definition. More...
struct | FLASH_ProcessTypeDef
FLASH handle Structure definition. More...
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STM32WB55xx HAL User Manual: FLASHEx

Modules
FLASHEx
STM32WBxx_HAL_Driver

FLASH Extended HAL module driver. More...

Modules

FLASHEx Private Functions
FLASH Extended Exported Functions
FLASH Exported Constants
FLASHEx Private Macros

Detailed Description

FLASH Extended HAL module driver.

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STM32WB55xx HAL User Manual: FLASH Exported Constants

Modules
FLASH Exported Constants
FLASHEx

Modules

FLASHEx Empty Check
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STM32WB55xx HAL User Manual: FLASH Extended Exported Functions

Modules
FLASH Extended Exported Functions
FLASHEx

Modules

Extended IO operation functions

Extended IO operation functions.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: GPIO

Modules
GPIO
STM32WBxx_HAL_Driver

GPIO HAL module driver. More...

Modules

GPIO Private Constants

MISRA C:2012 deviation rule has been granted for following rules: Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of range of the shift operator in following API : HAL_GPIO_Init HAL_GPIO_DeInit.

GPIO Exported Types
GPIO Exported Constants
GPIO Exported Macros
GPIO Private Macros
GPIO Exported Functions

GPIO Exported Functions.

Detailed Description

GPIO HAL module driver.

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STM32WB55xx HAL User Manual: GPIO Exported Constants

Modules
GPIO Exported Constants
GPIO

Modules

GPIO pins
GPIO mode

GPIO Configuration Mode Elements values convention: 0xX0yz00YZ.

GPIO speed

GPIO Output Maximum frequency.

GPIO pull

GPIO Pull-Up or Pull-Down Activation.

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STM32WB55xx HAL User Manual: GPIO Exported Functions

Modules
GPIO Exported Functions
GPIO

GPIO Exported Functions. More...

Modules

Initialization/de-initialization functions

Initialization and Configuration functions.

IO operation functions

IO operation functions.

Detailed Description

GPIO Exported Functions.

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STM32WB55xx HAL User Manual: GPIO Exported Init structures

Data Structures
GPIO Exported Init structures
GPIO

Data Structures

struct LL_GPIO_InitTypeDef
LL GPIO Init Structure definition. More...
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STM32WB55xx HAL User Manual: GPIO Exported Constants

Modules
GPIO Exported Constants
GPIO

Modules

PIN
Mode
Output Type
Output Speed
Pull Up Pull Down
Alternate Function
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STM32WB55xx HAL User Manual: GPIO Exported Functions

Modules
GPIO Exported Functions
GPIO

Modules

Port Configuration
Data Access
Initialization and de-initialization functions
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STM32WB55xx HAL User Manual: GPIO Exported Macros

Modules
GPIO Exported Macros
GPIO

Modules

Common Write and read registers Macros
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STM32WB55xx HAL User Manual: GPIOEx

Modules
GPIOEx
STM32WBxx_HAL_Driver

GPIO Extended HAL module driver. More...

Modules

GPIOEx Exported Constants
GPIOEx Exported Macros

Detailed Description

GPIO Extended HAL module driver.

Generated on Fri Sep 6 2019 11:34:42 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: GPIOEx Exported Constants

Modules
GPIOEx Exported Constants
GPIOEx

Modules

GPIOEx Alternate function selection
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STM32WB55xx HAL User Manual: GPIOEx Exported Macros

Modules
GPIOEx Exported Macros
GPIOEx

Modules

GPIOEx Get Port Index
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STM32WB55xx HAL User Manual: HAL

Modules
HAL
STM32WBxx_HAL_Driver

HAL module driver. More...

Modules

HAL Private Constants
HAL Exported Variables
HAL Exported Constants
HAL Exported Macros
HAL Private Macros
HAL Exported Functions

Detailed Description

HAL module driver.

Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: HAL Exported Constants

Modules
HAL Exported Constants
HAL

Modules

Tick Frequency
SYSCFG Exported Constants
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STM32WB55xx HAL User Manual: HAL Exported Functions

Modules
HAL Exported Functions
HAL

Modules

HAL System Configuration functions

HAL System Configuration functions.

HAL Initialization and Configuration functions

HAL Initialization and Configuration functions.

HAL Control functions

HAL Control functions.

HAL Debug functions

HAL Debug functions.

HAL Exported Variables
Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: HAL Exported Macros

Modules
HAL Exported Macros
HAL

Modules

DBGMCU Exported Macros
SYSCFG Exported Macros
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STM32WB55xx HAL User Manual: HSEM

Modules
HSEM
STM32WBxx_HAL_Driver

HSEM HAL module driver. More...

Modules

HSEM Exported Functions
HSEM Exported Macros
HSEM Private Macros

Detailed Description

HSEM HAL module driver.

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STM32WB55xx HAL User Manual: HSEM Exported Functions

Modules
HSEM Exported Functions
HSEM

Modules

Take and Release functions

HSEM Take and Release functions.

HSEM Set and Get Key functions

HSEM Set and Get Key functions.

HSEM IRQ handler management

HSEM Notification functions.

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STM32WB55xx HAL User Manual: HSEM Exported Constants

Modules
HSEM Exported Constants
HSEM

Modules

COREID Defines
Get Flags Defines

Flags defines which can be used with LL_HSEM_ReadReg function.

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STM32WB55xx HAL User Manual: HSEM Exported Functions

Modules
HSEM Exported Functions
HSEM

Modules

Data_Management
IT_Management
FLAG_Management
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STM32WB55xx HAL User Manual: HSEM Exported Macros

Modules
HSEM Exported Macros
HSEM

Modules

Common Write and read registers Macros
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STM32WB55xx HAL User Manual: I2C

Modules
I2C
STM32WBxx_HAL_Driver

I2C HAL module driver. More...

Modules

I2C Private Define
I2C Private Functions
I2C Exported Functions
I2C Exported Types
I2C Exported Constants
I2C Exported Macros
I2C Private Constants
I2C Private Macros

Detailed Description

I2C HAL module driver.

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STM32WB55xx HAL User Manual: I2C Configuration Structure definition

Data Structures
I2C Configuration Structure definition
I2C Exported Types

I2C Configuration Structure definition. More...

Data Structures

struct I2C_InitTypeDef

Detailed Description

I2C Configuration Structure definition.

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STM32WB55xx HAL User Manual: I2C Exported Constants

Modules
I2C Exported Constants
I2C

Modules

I2C Sequential Transfer Options
I2C Addressing Mode
I2C Dual Addressing Mode
I2C Own Address2 Masks
I2C General Call Addressing Mode
I2C No-Stretch Mode
I2C Memory Address Size
I2C Transfer Direction Master Point of View
I2C Reload End Mode
I2C Start or Stop Mode
I2C Interrupt configuration definition

I2C Interrupt definition Elements values convention: 0xXXXXXXXX.

I2C Flag definition
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STM32WB55xx HAL User Manual: I2C Exported Functions

Modules
I2C Exported Functions
I2C

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

Data transfers functions.

IRQ Handler and Callbacks
Peripheral State, Mode and Error functions

Peripheral State, Mode and Error functions.

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STM32WB55xx HAL User Manual: I2C Exported Types

Modules
I2C Exported Types
I2C

Modules

I2C Configuration Structure definition

I2C Configuration Structure definition.

HAL state structure definition

HAL State structure definition.

HAL mode structure definition

HAL Mode structure definition.

I2C Error Code definition

I2C Error Code definition.

I2C handle Structure definition

I2C handle Structure definition.

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STM32WB55xx HAL User Manual: I2C Exported Init structure

Data Structures
I2C Exported Init structure
I2C

Data Structures

struct LL_I2C_InitTypeDef
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STM32WB55xx HAL User Manual: I2C Exported Constants

Modules
I2C Exported Constants
I2C

Modules

Clear Flags Defines

Flags defines which can be used with LL_I2C_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_I2C_ReadReg function.

IT Defines

IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions.

Peripheral Mode
Analog Filter Selection
Master Addressing Mode
Own Address 1 Length
Own Address 2 Masks
Acknowledge Generation
Slave Address Length
Transfer Request Direction
Transfer End Mode
Start And Stop Generation
Read Write Direction
DMA Register Data
SMBus TimeoutA Mode SCL SDA Timeout
SMBus Timeout Selection
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STM32WB55xx HAL User Manual: I2C Exported Functions

Modules
I2C Exported Functions
I2C

Modules

Configuration
IT_Management
FLAG_management
Data_Management
Initialization and de-initialization functions
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STM32WB55xx HAL User Manual: I2C Exported Macros

Modules
I2C Exported Macros
I2C

Modules

Common Write and read registers Macros
Convert SDA SCL timings
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STM32WB55xx HAL User Manual: I2CEx

Modules
I2CEx
STM32WBxx_HAL_Driver

I2C Extended HAL module driver. More...

Modules

I2C Extended Exported Functions
I2C Extended Exported Constants

Detailed Description

I2C Extended HAL module driver.

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STM32WB55xx HAL User Manual: I2C Extended Exported Constants

Modules
I2C Extended Exported Constants
I2CEx

Modules

I2C Extended Analog Filter
I2C Extended Fast Mode Plus
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STM32WB55xx HAL User Manual: I2C Extended Exported Functions

Modules
I2C Extended Exported Functions
I2CEx

Modules

Extended features functions

Extended features functions.

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STM32WB55xx HAL User Manual: IPCC

Modules
IPCC
STM32WBxx_HAL_Driver

IPCC HAL module driver. More...

Modules

IPCC Private Constants
IPCC Private Functions
IPCC Exported Constants
IPCC Exported Types
IPCC Exported Macros
IPCC Exported Functions

Detailed Description

IPCC HAL module driver.

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STM32WB55xx HAL User Manual: IPCC Exported Constants

Modules
IPCC Exported Constants
IPCC

Modules

IPCC Channel
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STM32WB55xx HAL User Manual: IPCC Exported Functions

Modules
IPCC Exported Functions
IPCC

Modules

Initialization and deinitialization functions

Initialization and de-initialization functions.

Communication functions

Configuration, notification and Irq handling functions.

Peripheral State and Error functions

IPCC Peripheral State and Error functions.

Peripheral IRQ Handler and Callbacks
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STM32WB55xx HAL User Manual: IPCC Exported Constants

Modules
IPCC Exported Constants
IPCC

Modules

Get Flags Defines

Flags defines which can be used with LL_IPCC_ReadReg function.

Channel
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STM32WB55xx HAL User Manual: IPCC Exported Functions

Modules
IPCC Exported Functions
IPCC

Modules

IT_Management
Configuration
FLAG_Management
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STM32WB55xx HAL User Manual: IPCC Exported Macros

Modules
IPCC Exported Macros
IPCC

Modules

Common Write and read registers Macros
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STM32WB55xx HAL User Manual: IRDA

Modules
IRDA
STM32WBxx_HAL_Driver

HAL IRDA module driver. More...

Modules

IRDA Private Constants
IRDA Private Macros
IRDA Exported Functions
IRDA Private Functions
IRDA Exported Types
IRDA Exported Constants
IRDA Exported Macros

Detailed Description

HAL IRDA module driver.

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STM32WB55xx HAL User Manual: IRDA Exported Constants

Modules
IRDA Exported Constants
IRDA

Modules

IRDA State Code Definition
IRDA Error Code Definition
IRDA Word Length
IRDA Parity
IRDA Transfer Mode
IRDA Low Power
Clock Prescaler
IRDA State
IRDA Mode
IRDA One Bit Sampling
IRDA DMA Tx
IRDA DMA Rx
IRDA Request Parameters
IRDA Flags

Elements values convention: 0xXXXX.

IRDA Interrupts Definition

Elements values convention: 0000ZZZZ0XXYYYYYb.

IRDA Interruption Clear Flags
IRDA interruptions flags mask
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STM32WB55xx HAL User Manual: IRDA Exported Functions

Modules
IRDA Exported Functions
IRDA

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

IRDA Transmit and Receive functions.

Peripheral State and Error functions

IRDA State and Errors functions.

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STM32WB55xx HAL User Manual: IRDAEx

Modules
IRDAEx
STM32WBxx_HAL_Driver

Modules

IRDAEx Private Macros
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STM32WB55xx HAL User Manual: IWDG

Modules
IWDG
STM32WBxx_HAL_Driver

IWDG HAL module driver. More...

Modules

IWDG Private Defines
IWDG Exported Types
IWDG Exported Constants
IWDG Exported Macros
IWDG Exported Functions
IWDG Private Constants
IWDG Private Macros

Detailed Description

IWDG HAL module driver.

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STM32WB55xx HAL User Manual: IWDG Exported Constants

Modules
IWDG Exported Constants
IWDG

Modules

IWDG Prescaler
IWDG Window option
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STM32WB55xx HAL User Manual: IWDG Exported Functions

Modules
IWDG Exported Functions
IWDG

Modules

Initialization and Start functions

Initialization and Start functions.

IO operation functions

IO operation functions.

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STM32WB55xx HAL User Manual: IWDG Exported Types

Data Structures
IWDG Exported Types
IWDG

Data Structures

struct | IWDG_InitTypeDef
IWDG Init structure definition. More...
struct | IWDG_HandleTypeDef
IWDG Handle Structure definition. More...
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STM32WB55xx HAL User Manual: IWDG Exported Constants

Modules
IWDG Exported Constants
IWDG

Modules

Get Flags Defines

Flags defines which can be used with LL_IWDG_ReadReg function.

Prescaler Divider
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STM32WB55xx HAL User Manual: IWDG Exported Functions

Modules
IWDG Exported Functions
IWDG

Modules

Configuration
FLAG_Management
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STM32WB55xx HAL User Manual: IWDG Exported Macros

Modules
IWDG Exported Macros
IWDG

Modules

Common Write and read registers Macros
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STM32WB55xx HAL User Manual: LCD

Modules
LCD
STM32WBxx_HAL_Driver

LCD HAL module driver. More...

Modules

LCD Private Defines
LCD Exported Functions
LCD Private Functions
LCD Exported Types
LCD Exported Constants
LCD Exported Macros
LCD Private Macros

Detailed Description

LCD HAL module driver.

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STM32WB55xx HAL User Manual: LCD Exported Constants

Modules
LCD Exported Constants
LCD

Modules

LCD Error Code
LCD Prescaler
LCD Divider
LCD Duty
LCD Bias
LCD Voltage Source
LCD Interrupts
LCD Pulse On Duration
LCD Dead Time
LCD Blink Mode
LCD Blink Frequency
LCD Contrast
LCD RAMRegister
LCD High Drive
LCD Mux Segment
LCD Flags Definition
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STM32WB55xx HAL User Manual: LCD Exported Functions

Modules
LCD Exported Functions
LCD

Modules

Initialization/de-initialization methods

Initialization and Configuration functions.

IO operation methods

LCD RAM functions.

Peripheral State methods

LCD State functions.

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STM32WB55xx HAL User Manual: Clocks Frequency Structure

Data Structures
Clocks Frequency Structure
RCC Exported Types

Data Structures

struct LL_RCC_ClocksTypeDef
RCC Clocks Frequency Structure. More...
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STM32WB55xx HAL User Manual: LPTIM Exported Constants

Modules
LPTIM Exported Constants
LPTIM

Modules

LPTIM Clock Source
LPTIM Clock Prescaler
LPTIM Output Polarity
LPTIM Clock Sample Time
LPTIM Clock Polarity
LPTIM Trigger Source
LPTIM External Trigger Polarity
LPTIM Trigger Sample Time
LPTIM Updating Mode
LPTIM Counter Source
LPTIM Input1 Source
LPTIM Input2 Source
LPTIM Flags Definition
LPTIM Interrupts Definition
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STM32WB55xx HAL User Manual: LPTIM Exported Init structure

Data Structures
LPTIM Exported Init structure
LPTIM

Data Structures

struct LL_LPTIM_InitTypeDef
LPTIM Init structure definition. More...
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STM32WB55xx HAL User Manual: LPTIM Exported Constants

Modules
LPTIM Exported Constants
LPTIM

Modules

Get Flags Defines

Flags defines which can be used with LL_LPTIM_ReadReg function.

IT Defines

IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions.

Operating Mode
Update Mode
Counter Mode
Output Waveform Type
Output Polarity
Prescaler Value
Trigger Source
Trigger Filter
Trigger Polarity
Clock Source
Clock Filter
Clock Polarity
Encoder Mode
Input1 Source
Input2 Source
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STM32WB55xx HAL User Manual: LPTIM Exported Functions

Modules
LPTIM Exported Functions
LPTIM

Modules

Initialisation and deinitialisation functions
LPTIM Configuration
Trigger Configuration
Clock Configuration
Encoder Mode
FLAG Management
Interrupt Management
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STM32WB55xx HAL User Manual: LPTIM Exported Macros

Modules
LPTIM Exported Macros
LPTIM

Modules

Common Write and read registers Macros
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STM32WB55xx HAL User Manual: LPUART Exported Init structures

Data Structures
LPUART Exported Init structures
LPUART

Data Structures

struct LL_LPUART_InitTypeDef
LL LPUART Init Structure definition. More...
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STM32WB55xx HAL User Manual: LPUART Exported Constants

Modules
LPUART Exported Constants
LPUART

Modules

Clear Flags Defines

Flags defines which can be used with LL_LPUART_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_LPUART_ReadReg function.

IT Defines

IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions.

FIFO Threshold
Direction
Parity Control
Wakeup
Datawidth
Clock Source Prescaler
Stop Bits
TX RX Pins Swap
RX Pin Active Level Inversion
TX Pin Active Level Inversion
Binary Data Inversion
Bit Order
Address Length Detection
Hardware Control
Wakeup Activation
Driver Enable Polarity
DMA Register Data
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STM32WB55xx HAL User Manual: LPUART Exported Functions

Modules
LPUART Exported Functions
LPUART

Modules

Configuration functions
Configuration functions related to Half Duplex feature
Configuration functions related to Driver Enable feature
FLAG_Management
IT_Management
DMA_Management
Data_Management
Execution
Initialization and de-initialization functions
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STM32WB55xx HAL User Manual: LPUART Exported Macros

Modules
LPUART Exported Macros
LPUART

Modules

Common Write and read registers Macros
Helper Macros
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STM32WB55xx HAL User Manual: PCD

Modules
PCD
STM32WBxx_HAL_Driver

PCD HAL module driver. More...

Modules

PCD Private Macros
PCD Private Functions
PCD Exported Functions
PCD Exported Types
PCD Exported Constants
PCD Exported Macros

macros to handle interrupts and specific clock configurations

PCD Private Constants

Detailed Description

PCD HAL module driver.

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STM32WB55xx HAL User Manual: PCD Exported Constants

Modules
PCD Exported Constants
PCD

Modules

PCD Speed
PCD PHY Module
PCD Error Code definition

PCD Error Code definition.

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STM32WB55xx HAL User Manual: PCD Exported Functions

Modules
PCD Exported Functions
PCD

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

Data transfers functions.

Peripheral Control functions

management functions

Peripheral State functions

Peripheral State functions.

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STM32WB55xx HAL User Manual: PCD Private Constants

Modules
PCD Private Constants
PCD

Modules

USB EXTI line interrupt
PCD EP0 MPS
PCD ENDP
PCD Endpoint Kind
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STM32WB55xx HAL User Manual: PCDEx

Modules
PCDEx
STM32WBxx_HAL_Driver

PCD Extended HAL module driver. More...

Modules

PCDEx Exported Functions

Detailed Description

PCD Extended HAL module driver.

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STM32WB55xx HAL User Manual: PCDEx Exported Functions

Modules
PCDEx Exported Functions
PCDEx

Modules

Peripheral Control functions

PCDEx control functions.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PKA

Modules
PKA
STM32WBxx_HAL_Driver

PKA HAL module driver. More...

Modules

PKA Private Define
PKA Private Functions
PKA Exported Functions
PKA Exported Types
PKA Exported Constants
PKA Exported Macros

Detailed Description

PKA HAL module driver.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PKA Exported Constants

Modules
PKA Exported Constants
PKA

Modules

PKA mode
PKA Interrupt configuration definition

PKA Interrupt definition.

PKA Flag definition
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STM32WB55xx HAL User Manual: PKA Exported Functions

Modules
PKA Exported Functions
PKA

Modules

Initialization and de-initialization functions

Initialization and de-initialization functions.

IO operation functions

IO operation functions.

Peripheral State and Error functions

Peripheral State and Error functions.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PKA Exported Types

Modules
PKA Exported Types
PKA

Modules

HAL state structure definition

HAL State structure definition.

HAL callback ID enumeration
PKA Error Code definition

PKA Error Code definition.

PKA handle Structure definition

PKA handle Structure definition.

PKA Callback pointer definition

PKA Callback pointer definition.

PKA operation structure definition

Input and output data definition.

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STM32WB55xx HAL User Manual: PKA Exported Init structure

Data Structures
PKA Exported Init structure
PKA

Data Structures

struct LL_PKA_InitTypeDef
PKA Init structures definition. More...
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STM32WB55xx HAL User Manual: PKA Exported Constants

Modules
PKA Exported Constants
PKA

Modules

Get Flags Defines

Flags defines which can be used with LL_PKA_ReadReg function.

IT Defines

IT defines which can be used with LL_PKA_ReadReg and LL_PKA_WriteReg functions.

Operation Mode

List of opearation mode.

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PKA Exported Functions

Modules
PKA Exported Functions
PKA

Modules

Configuration
IT_Management
PKA flag management
Initialization and de-initialization functions
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STM32WB55xx HAL User Manual: PKA Exported Macros

Modules
PKA Exported Macros
PKA

Modules

Common Write and read registers Macros
Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PWR

Modules
PWR
STM32WBxx_HAL_Driver

PWR HAL module driver. More...

Modules

PWR Exported Types
PWR Exported Constants
PWR Private Defines
PWR Exported Macros
PWR Private Macros
PWR Exported Functions

Detailed Description

PWR HAL module driver.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PWR Exported Constants

Modules
PWR Exported Constants
PWR

Modules

Power Voltage Detector Level selection
PWR PVD interrupt and event mode
PWR Low Power Mode Selection
PWR regulator mode
PWR SLEEP mode entry
PWR STOP mode entry
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STM32WB55xx HAL User Manual: PWR Exported Functions

Modules
PWR Exported Functions
PWR

Modules

Initialization and de-initialization functions

Initialization and de-initialization functions.

Peripheral Control functions

Low Power modes configuration functions.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PWR Exported Types

Data Structures
PWR Exported Types
PWR

Data Structures

struct PWR_PVDTypeDef
PWR PVD configuration structure definition. More...
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STM32WB55xx HAL User Manual: PWR Exported Constants

Modules
PWR Exported Constants
PWR

Modules

Clear Flags Defines

Flags defines which can be used with LL_PWR_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_PWR_ReadReg function.

REGU VOLTAGE
MODE PWR
Flash power-down mode during low-power run mode
Flash power-down mode during sleep mode
Peripheral voltage monitoring
PVDLEVEL
WAKEUP
BATT CHARG RESISTOR
GPIO
GPIO BIT
BOR configuration
SMPS step down converter operating modes
SMPS step down converter supply startup current selection
SMPS step down converter output voltage scaling voltage level
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STM32WB55xx HAL User Manual: PWR Exported Functions

Modules
PWR Exported Functions
PWR

Modules

Configuration
Configuration of SMPS
Configuration of multicore, intended to be executed by CPU1
Configuration of CPU2, intended to be executed by CPU2
Configuration of radio (BLE or 802.15.4) of CPU2, intended to be executed by CPU2
FLAG_Management
FLAG management for SMPS
FLAG management for radio (BLE or 802.15.4)
FLAG management for multicore
PWR IT management for SMPS
PWR IT management for radio (BLE or 802.15.4)
PWR IT management for multicore
PWR IT management of CPU2, intended to be executed by CPU2
De-initialization function
Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PWR Exported Macros

Modules
PWR Exported Macros
PWR

Modules

Common Write and read registers Macros
Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PWR Private Defines

Modules
PWR Private Defines
PWR | PWREx

Modules

PWR Register Reset Values
PWR PVD external interrupt line
PWR PVD Mode Mask
PWR PVM external interrupts lines
PWR PVM Mode Mask
Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PWREx

Modules
PWREx
STM32WBxx_HAL_Driver

PWR Extended HAL module driver. More...

Modules

PWR Extended Private Defines
PWR Extended Exported Types
PWR Extended Exported Constants
PWR Private Defines
PWR Extended Exported Macros
PWR Extended Exported Functions
PWR Extended Private Macros

Detailed Description

PWR Extended HAL module driver.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PWR Extended Exported Functions

Modules
PWR Extended Exported Functions
PWREx

Modules

Extended Peripheral Control functions

Extended Peripheral Control functions.

Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: PWR Extended Exported Types

Data Structures
PWR Extended Exported Types
PWREx

Data Structures

struct | PWR_PVMTypeDef
PWR PVM configuration structure definition. More...
struct | PWR_SMPSTypeDef
PWR SMPS step down configuration structure definition. More...
Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: QSPI

Modules
QSPI
STM32WBxx_HAL_Driver

QSPI HAL module driver. More...

Modules

QSPI Private Constants
QSPI Private Macros
QSPI Exported Functions
QSPI Private Functions
QSPI Exported Types
QSPI Exported Constants
QSPI Exported Macros

Detailed Description

QSPI HAL module driver.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: QSPI Exported Constants

Modules
QSPI Exported Constants
QSPI

Modules

QSPI Error Code
QSPI Sample Shifting
QSPI ChipSelect High Time
QSPI Clock Mode
QSPI Address Size
QSPI Alternate Bytes Size
QSPI Instruction Mode
QSPI Address Mode
QSPI Alternate Bytes Mode
QSPI Data Mode
QSPI DDR Mode
QSPI Send Instruction Mode
QSPI Match Mode
QSPI Automatic Stop
QSPI Timeout Activation
QSPI Flags
QSPI Interrupts
QSPI Timeout definition

QSPI Timeout definition.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: QSPI Exported Functions

Modules
QSPI Exported Functions
QSPI

Modules

Initialization/de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

QSPI Transmit/Receive functions.

Peripheral Control and State functions

QSPI control and State functions.

Generated on Fri Sep 6 2019 11:34:43 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RCC

Modules
RCC
STM32WBxx_HAL_Driver

RCC HAL module driver. More...

Modules

RCC Private Constants
RCC Private Macros
RCC Private Variables
RCC Private Functions
RCC Exported Functions
RCC Exported Types
RCC Exported Constants
RCC Exported Macros

Detailed Description

RCC HAL module driver.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RCC Exported Constants

Modules
RCC Exported Constants
RCC

Modules

Timeout Values
Oscillator Type
HSE Config
LSE Config
HSI Config
LSI Config
MSI Config
HSI48 Config
PLL Config
PLLM Clock Divider
PLLP Clock Divider
PLLQ Clock Divider
PLLR Clock Divider
PLL Clock Source
PLL Clock Output
PLLSAI1 Clock Output
MSI Clock Range
System Clock Type
System Clock Source
System Clock Source Status
AHB Clock Source
APB1 Clock Source
RTC Clock Source
MCO Index
MCO1 Clock Source
MCO Clock Prescaler
HSE bias current factor
HSE current max limit
Interrupts
Flags

Elements values convention: XXXYYYYYb.

LSE Drive Configuration
Wake-Up from STOP Clock
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STM32WB55xx HAL User Manual: RCC Exported Functions

Modules
RCC Exported Functions
RCC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Peripheral Control functions

RCC clocks control functions.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RCC Exported Types

Data Structures
RCC Exported Types
RCC

Data Structures

struct | RCC_PLLInitTypeDef
RCC PLL configuration structure definition. More...
struct | RCC_OscInitTypeDef
RCC Internal/External Oscillator (HSE, HSI, HSI48, MSI, LSE and LSI) configuration structure definition. More...
struct | RCC_ClkInitTypeDef
RCC System, AHB and APB buses clock configuration structure definition. More...
Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RCC Exported Constants

Modules
RCC Exported Constants
RCC

Modules

Oscillator Values adaptation

Defines used to adapt values of different oscillators.

Clear Flags Defines

Flags defines which can be used with LL_RCC_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_RCC_ReadReg function.

IT Defines

IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions.

LSE oscillator drive capability
MSI clock ranges
HSE current control max limits
HSE sense amplifier threshold
LSCO Selection
System clock switch
System clock switch status
RF system clock switch status
AHB prescaler
APB low-speed prescaler (APB1)
APB high-speed prescaler (APB2)
Wakeup from Stop and CSS backup clock selection
MCO1 SOURCE selection
MCO1 prescaler
SMPS clock switch
SMPS clock switch status
SMPS prescaler
Peripheral clock frequency
USART1 CLKSOURCE
LPUART1 CLKSOURCE
I2Cx CLKSOURCE
LPTIMx CLKSOURCE
SAI1 CLKSOURCE
CLK48 CLKSOURCE
USB CLKSOURCE
ADC CLKSRC
RNG CLKSRC
USART1
LPUART1
I2C1
LPTIM1
SAI1
CLK48
USB
RNG
ADC
RTC clock source selection
RF Wakeup clock source selection
PLL and PLLSAI1 entry clock source
PLL and PLLSAI1 division factor
PLL division factor (PLLR)
PLL division factor (PLLP)
PLL division factor (PLLQ)
PLLSAI1 division factor (PLLQ)
PLLSAI1 division factor (PLLP)
PLLSAI1 division factor (PLLR)
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STM32WB55xx HAL User Manual: RCC Exported Functions

Modules
RCC Exported Functions
RCC

Modules

HSE
HSI
HSI48
LSE
LSI1
LSI2
MSI
LSCO
System
SMPS
MCO
Peripheral Clock Source
RTC
PLL
PLLSAI1
FLAG Management
IT Management
De-initialization function
Get system and peripherals clocks frequency functions

Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks and different peripheral clocks available on the device.

Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RCC Exported Macros

Modules
RCC Exported Macros
RCC

Modules

Common Write and read registers Macros
Calculate frequencies
Generated on Fri Sep 6 2019 11:34:52 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RCC Exported Types

Modules
RCC Exported Types
RCC

Modules

Clocks Frequency Structure
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STM32WB55xx HAL User Manual: RCCEx

Modules
RCCEx
STM32WBxx_HAL_Driver

RCC Extended HAL module driver. More...

Modules

RCCEx Private Constants
RCCEx Private Functions
RCCEx Exported Functions
RCCEx Exported Types
RCCEx Exported Constants
RCCEx Exported Macros
RCC Private Constants
RCCEx_Private_Macros

Detailed Description

RCC Extended HAL module driver.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RCCEx Exported Constants

Modules
RCCEx Exported Constants
RCCEx

Modules

LSCO Index
Low Speed Clock Source
Periph Clock Selection
USART1 Clock Source
LPUART1 Clock Source
I2C1 Clock Source
I2C3 Clock Source
SAI1 Clock Source
LPTIM1 Clock Source
LPTIM2 Clock Source
RNG Clock Source
USB Clock Source
ADC Clock Source
HCLK RF Clock Source
RF WKP Clock Source
SMPS Clock Source
System Clock Source Status
SMPS Clock Division Factor
RCC LSE CSS external interrupt line
RCCEx CRS Status
RCCEx CRS SynchroSource
RCCEx CRS SynchroDivider
RCCEx CRS SynchroPolarity
RCCEx CRS ReloadValueDefault
RCCEx CRS ErrorLimitDefault
RCCEx CRS HSI48CalibrationDefault
RCCEx CRS FreqErrorDirection
RCCEx CRS Interrupt Sources
RCCEx CRS Flags
Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RCCEx Exported Functions

Modules
RCCEx Exported Functions
RCCEx

Modules

Extended Peripheral Control functions

Extended Peripheral Control functions.

Extended Clock management functions

Extended Clock management functions.

Extended Clock Recovery System Control functions

Extended Clock Recovery System Control functions.

Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RCCEx Exported Types

Data Structures
RCCEx Exported Types
RCCEx

Data Structures

struct | RCC_PLLSAI1InitTypeDef
PLLSAI1 Clock structure definition. More...
struct | RCC_PeriphCLKInitTypeDef
RCC extended clocks structure definition. More...
struct | RCC_CRSInitTypeDef
RCC_CRS Init structure definition. More...
struct | RCC_CRSSynchroInfoTypeDef
RCC_CRS Synchronization structure definition. More...
Generated on Fri Sep 6 2019 11:34:44 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RNG

Modules
RNG
STM32WBxx_HAL_Driver

RNG HAL module driver. More...

Modules

RNG Private Constants
RNG Exported Types
RNG Exported Constants
RNG Exported Macros
RNG Exported Functions
RNG Private Macros

Detailed Description

RNG HAL module driver.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RNG Exported Constants

Modules
RNG Exported Constants
RNG

Modules

RNG Interrupt definition
RNG Flag definition
RNG Clock Error Detection
RNG Error Definition
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STM32WB55xx HAL User Manual: RNG Exported Functions

Modules
RNG Exported Functions
RNG

Modules

Initialization and configuration functions

Initialization and configuration functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State functions

Peripheral State functions.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RNG Exported Types

Modules
RNG Exported Types
RNG

Modules

RNG Init Structure definition
RNG State Structure definition
RNG Handle Structure definition
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STM32WB55xx HAL User Manual: RNG Init Structure definition

Data Structures
RNG Init Structure definition
RNG Exported Types

Data Structures

struct RNG_InitTypeDef
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STM32WB55xx HAL User Manual: RNG Exported Init structures

Data Structures
RNG Exported Init structures
RNG

Data Structures

struct LL_RNG_InitTypeDef
LL RNG Init Structure Definition. More...
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STM32WB55xx HAL User Manual: RNG Exported Constants

Modules
RNG Exported Constants
RNG

Modules

Clock Error Detection
Get Flags Defines

Flags defines which can be used with LL_RNG_ReadReg function.

IT Defines

IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros.

Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RNG Exported Functions

Modules
RNG Exported Functions
RNG

Modules

RNG Configuration functions
FLAG Management
IT Management
Data Management
Initialization and de-initialization functions
Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RNG Exported Macros

Modules
RNG Exported Macros
RNG

Modules

Common Write and read registers Macros
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STM32WB55xx HAL User Manual: RTC

Modules
RTC
STM32WBxx_HAL_Driver

RTC HAL module driver. More...

Modules

RTC Exported Types
RTC Exported Constants
RTC Exported Macros
RTC Exported Functions
RTC Private Constants
RTC Private Macros
RTC Private Functions

Detailed Description

RTC HAL module driver.

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STM32WB55xx HAL User Manual: RTC Exported Constants

Modules
RTC Exported Constants
RTC

Modules

RTC Hour Formats
RTC Output Polarity Definitions
RTC Output Type ALARM OUT
RTC Output ALARM OUT Remap
RTC AM PM Definitions
RTC DayLightSaving Definitions
RTC StoreOperation Definitions
RTC Input Parameter Format Definitions
RTC Month Date Definitions
RTC WeekDay Definitions
RTC AlarmDateWeekDay Definitions
RTC AlarmMask Definitions
RTC Alarms Definitions
RTC Alarm Sub Seconds Masks Definitions
RTC Interrupts Definitions
RTC Flags Definitions
Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC Exported Functions

Modules
RTC Exported Functions
RTC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

RTC Time and Date functions

RTC Time and Date functions.

RTC Alarm functions

RTC Alarm functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State functions

Peripheral State functions.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC Exported Init structure

Data Structures
RTC Exported Init structure
RTC

Data Structures

struct | LL_RTC_InitTypeDef
RTC Init structures definition. More...
struct | LL_RTC_TimeTypeDef
RTC Time structure definition. More...
struct | LL_RTC_DateTypeDef
RTC Date structure definition. More...
struct | LL_RTC_AlarmTypeDef
RTC Alarm structure definition. More...
Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC Exported Constants

Modules
RTC Exported Constants
RTC

Modules

FORMAT
RTC Alarm A Date WeekDay
RTC Alarm B Date WeekDay
Get Flags Defines

Flags defines which can be used with LL_RTC_ReadReg function.

IT Defines

IT defines which can be used with LL_RTC_ReadReg and LL_RTC_WriteReg functions.

WEEK DAY
MONTH
HOUR FORMAT
ALARM OUTPUT
ALARM OUTPUT TYPE
OUTPUT POLARITY PIN
TIME FORMAT
SHIFT SECOND
ALARMA MASK
ALARMA TIME FORMAT
ALARMB MASK
ALARMB TIME FORMAT
TIMESTAMP EDGE
TIMESTAMP TIME FORMAT
TAMPER
TAMPER MASK
TAMPER NO ERASE
TAMPER DURATION
TAMPER FILTER
TAMPER SAMPLING FREQUENCY DIVIDER
TAMPER ACTIVE LEVEL
WAKEUP CLOCK DIV
BACKUP
Calibration output
Calibration pulse insertion
Calibration period
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STM32WB55xx HAL User Manual: RTC Exported Functions

Modules
RTC Exported Functions
RTC

Modules

Configuration
Time
Date
ALARMA
ALARMB
Timestamp
Tamper
Wakeup
Backup_Registers
Calibration
FLAG_Management
IT_Management
Initialization and de-initialization functions
Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC Exported Macros

Modules
RTC Exported Macros
RTC

Modules

Common Write and read registers Macros
Convert helper Macros
Date helper Macros
Time helper Macros
Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTC Private Macros

Modules
RTC Private Macros
RTC

Modules

RTC Private macros to check input parameters
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STM32WB55xx HAL User Manual: RTCEx

Modules
RTCEx
STM32WBxx_HAL_Driver

RTC Extended HAL module driver. More...

Modules

RTCEx Private Constants
RTCEx Exported Types
RTCEx Exported Constants
RTCEx Exported Macros
RTCEx Exported Functions
RTCEx Private Macros

Detailed Description

RTC Extended HAL module driver.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTCEx Exported Constants

Modules
RTCEx Exported Constants
RTCEx

Modules

RTCEx Output Selection Definition
RTCEx Backup Registers Definition
RTCEx Time Stamp Edges definition
RTCEx TimeStamp Pin Selection
RTCEx Tamper Pins Definition
RTCEx Tamper Interrupt Definitions
RTCEx Tamper Trigger Definitions
RTCEx Tamper EraseBackUp Definitions
RTCEx Tamper MaskFlag Definitions
RTCEx Tamper Filter Definitions
RTCEx Tamper Sampling Frequencies Definitions
RTCEx Tamper Pin Precharge Duration Definitions
RTCEx Tamper TimeStampOnTamperDetection Definitions
RTCEx Tamper Pull UP Definitions
RTCEx Wakeup Timer Definitions
RTCEx Smooth calib period Definitions
RTCEx Smooth calib Plus pulses Definitions
RTCEx Calib Output selection Definitions
RTCEx Add 1 Second Parameter Definitions
RTCEx Interrupts Definitions
RTCEx Flags Definitions
Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTCEx Exported Functions

Modules
RTCEx Exported Functions
RTCEx

Modules

Extended RTC TimeStamp and Tamper functions

RTC TimeStamp and Tamper functions.

Extended RTC Wake-up functions

RTC Wake-up functions.

Extended Peripheral Control functions

Extended Peripheral Control functions.

Extended features functions

Extended features functions.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTCEx Exported Macros

Modules
RTCEx Exported Macros
RTCEx

Modules

RTC WakeUp Timer
RTC Timestamp
RTC Tamper
EXTI RTC Tamper Timestamp EXTI
RTC Calibration
Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTCEx Exported Types

Data Structures
RTCEx Exported Types
RTCEx

Data Structures

struct RTC_TamperTypeDef
RTC Tamper structure definition. More...
Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: RTCEx Private Macros

Modules
RTCEx Private Macros
RTCEx

Modules

Private macros to check input parameters
Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAI

Modules
SAI
STM32WBxx_HAL_Driver

SAI HAL module driver. More...

Modules

SAI Private Typedefs
SAI Private Constants
SAI Private Functions

Private functions.

SAI Exported Functions
SAI Exported Types
SAI Exported Constants
SAI Exported Macros

macros to handle interrupts and specific configurations

SAI Private Macros

Detailed Description

SAI HAL module driver.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAI Exported Constants

Modules
SAI Exported Constants
SAI

Modules

SAI Error Code
SAI External synchronisation
SAI Block Master Clock Output
SAI Supported protocol
SAI protocol data size
SAI Audio Frequency
SAI Block Master Clock OverSampling
SAI PDM Clock Enable
SAI Block Mode
SAI Block Protocol
SAI Block Data Size
SAI Block MSB LSB transmission
SAI Block Clock Strobing
SAI Block Synchronization
SAI Block Output Drive
SAI Block NoDivider
SAI Block FS Definition
SAI Block FS Polarity
SAI Block FS Offset
SAI Block Slot Size
SAI Block Slot Active
SAI Mono Stereo Mode
SAI TRIState Management
SAI Block Fifo Threshold
SAI Block Companding Mode
SAI Block Mute Value
SAI Block Interrupts Definition
SAI Block Flags Definition
SAI Block Fifo Status Level
Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAI Exported Functions

Modules
SAI Exported Functions
SAI

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

Data transfers functions.

Peripheral State functions

Peripheral State functions.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAI Frame Structure definition

Data Structures
SAI Frame Structure definition
SAI Exported Types

SAI Frame Init structure definition. More...

Data Structures

struct SAI_FrameInitTypeDef

Detailed Description

SAI Frame Init structure definition.

Note:
For SPDIF and AC97 protocol, these parameters are not used (set by hardware).
Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAI Init Structure definition

Data Structures
SAI Init Structure definition
SAI Exported Types

SAI Init Structure definition. More...

Data Structures

struct SAI_InitTypeDef

Detailed Description

SAI Init Structure definition.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAI PDM Structure definition

Data Structures
SAI PDM Structure definition
SAI Exported Types

SAI PDM Init structure definition. More...

Data Structures

struct SAI_PdmInitTypeDef

Detailed Description

SAI PDM Init structure definition.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAI Slot Structure definition

Data Structures
SAI Slot Structure definition
SAI Exported Types

SAI Block Slot Init Structure definition. More...

Data Structures

struct SAI_SlotInitTypeDef

Detailed Description

SAI Block Slot Init Structure definition.

Note:
For SPDIF protocol, these parameters are not used (set by hardware).
For AC97 protocol, only SlotActive parameter is used (the others are set by hardware).
Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAIEx

Modules
SAIEx
STM32WBxx_HAL_Driver

SAI Extended HAL module driver. More...

Modules

SAIEx Extended Private Defines
SAIEx Extended Exported Functions
SAIEx Exported Types
SAIEx Extended Private Macros

Detailed Description

SAI Extended HAL module driver.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAIEx Extended Exported Functions

Modules
SAIEx Extended Exported Functions
SAIEx

Modules

Peripheral Control functions

SAIEx control functions.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SAIEx Exported Types

Data Structures
SAIEx Exported Types
SAIEx

Data Structures

struct SAIEx_PdmMicDelayParamTypeDef
PDM microphone delay structure definition. More...
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STM32WB55xx HAL User Manual: SMARTCARD

Modules
SMARTCARD
STM32WBxx_HAL_Driver

HAL SMARTCARD module driver. More...

Modules

SMARTCARD Private Constants
SMARTCARD Exported Functions
SMARTCARD Private Functions
SMARTCARD Exported Types
SMARTCARD Exported Constants
SMARTCARD Exported Macros
SMARTCARD Private Macros

Detailed Description

HAL SMARTCARD module driver.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMARTCARD Exported Constants

Modules
SMARTCARD Exported Constants
SMARTCARD

Modules

SMARTCARD State Code Definition
SMARTCARD Error Code Definition
SMARTCARD Word Length
SMARTCARD Number of Stop Bits
SMARTCARD Parity
SMARTCARD Transfer Mode
SMARTCARD Clock Polarity
SMARTCARD Clock Phase
SMARTCARD Last Bit
SMARTCARD One Bit Sampling Method
SMARTCARD NACK Enable
SMARTCARD Timeout Enable
Clock Prescaler
SMARTCARD advanced feature TX pin active level inversion
SMARTCARD advanced feature RX pin active level inversion
SMARTCARD advanced feature Binary Data inversion
SMARTCARD advanced feature RX TX pins swap
SMARTCARD advanced feature Overrun Disable
SMARTCARD advanced feature DMA Disable on Rx Error
SMARTCARD advanced feature MSB first
SMARTCARD Request Parameters
SMARTCARD interruptions flags mask
Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMARTCARD Exported Functions

Modules
SMARTCARD Exported Functions
SMARTCARD

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

SMARTCARD Transmit and Receive functions.

Peripheral State and Errors functions

SMARTCARD State and Errors functions.

Generated on Fri Sep 6 2019 11:34:45 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMARTCARD Extended Exported Constants

Modules
SMARTCARD Extended Exported Constants
SMARTCARDEx

Modules

SMARTCARD Transmission Completion Indication
SMARTCARD advanced feature initialization type
SMARTCARDEx FIFO mode

SMARTCARD FIFO mode.

SMARTCARDEx TXFIFO threshold level

SMARTCARD TXFIFO level.

SMARTCARDEx RXFIFO threshold level

SMARTCARD RXFIFO level.

SMARTCARD Flags

Elements values convention: 0xXXXX.

SMARTCARD Interrupts Definition

Elements values convention: 000ZZZZZ0XXYYYYYb.

SMARTCARD Interruption Clear Flags
Generated on Fri Sep 6 2019 11:34:56 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMARTCARD Extended Exported Functions

Modules
SMARTCARD Extended Exported Functions
SMARTCARDEx

Modules

Extended Peripheral Control functions

Extended control functions.

Extended Peripheral IO operation functions

SMARTCARD Transmit and Receive functions.

Extended Peripheral Peripheral Control functions

SMARTCARD control functions.

SMARTCARDEx_Exported_Functions_Group3
Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMBUS

Modules
SMBUS
STM32WBxx_HAL_Driver

SMBUS HAL module driver. More...

Modules

SMBUS Private Constants
SMBUS Exported Functions
SMBUS Exported Types
SMBUS Exported Constants
SMBUS Exported Macros
SMBUS Private Macros
SMBUS Private Functions

Data transfers Private functions.

Detailed Description

SMBUS HAL module driver.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMBUS Configuration Structure definition

Data Structures
SMBUS Configuration Structure definition
SMBUS Exported Types

SMBUS Configuration Structure definition. More...

Data Structures

struct SMBUS_InitTypeDef

Detailed Description

SMBUS Configuration Structure definition.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMBUS Exported Constants

Modules
SMBUS Exported Constants
SMBUS

Modules

SMBUS Analog Filter
SMBUS addressing mode
SMBUS dual addressing mode
SMBUS ownaddress2 masks
SMBUS general call addressing mode
SMBUS nostretch mode
SMBUS packet error check mode
SMBUS peripheral mode
SMBUS ReloadEndMode definition
SMBUS StartStopMode definition
SMBUS XferOptions definition
SMBUS Interrupt configuration definition

SMBUS Interrupt definition Elements values convention: 0xXXXXXXXX.

SMBUS Flag definition

Flag definition Elements values convention: 0xXXXXYYYY.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMBUS Exported Functions

Modules
SMBUS Exported Functions
SMBUS

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

Data transfers functions.

IRQ Handler and Callbacks
Peripheral State and Errors functions

Peripheral State and Errors functions.

SMBUS Private Functions

Data transfers Private functions.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SMBUS Exported Types

Modules
SMBUS Exported Types
SMBUS

Modules

SMBUS Configuration Structure definition

SMBUS Configuration Structure definition.

HAL state definition

HAL State definition.

SMBUS Error Code definition

SMBUS Error Code definition.

SMBUS handle Structure definition

SMBUS handle Structure definition.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SPI

Modules
SPI
STM32WBxx_HAL_Driver

SPI HAL module driver. More...

Modules

SPI Private Constants
SPI Private Functions

Private functions.

SPI Exported Functions
SPI Exported Types
SPI Exported Constants
SPI Exported Macros
SPI Private Macros

Detailed Description

SPI HAL module driver.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SPI Exported Constants

Modules
SPI Exported Constants
SPI

Modules

SPI Error Code
SPI Mode
SPI Direction Mode
SPI Data Size
SPI Clock Polarity
SPI Clock Phase
SPI Slave Select Management
SPI NSS Pulse Mode
SPI BaudRate Prescaler
SPI MSB LSB Transmission
SPI TI Mode
SPI CRC Calculation
SPI CRC Length

This parameter can be one of the following values: SPI_CRC_LENGTH_DATASIZE: aligned with the data size SPI_CRC_LENGTH_8BIT : CRC 8bit SPI_CRC_LENGTH_16BIT : CRC 16bit.

SPI FIFO Reception Threshold

This parameter can be one of the following values: SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF : RXNE event is generated if the FIFO level is greater or equal to 1/4(8-bits).

SPI Interrupt Definition
SPI Flags Definition
SPI Transmission FIFO Status Level
SPI Reception FIFO Status Level
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STM32WB55xx HAL User Manual: SPI Exported Functions

Modules
SPI Exported Functions
SPI

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

Data transfers functions.

Peripheral State and Errors functions

SPI control functions.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SPI Exported Init structure

Data Structures
SPI Exported Init structure
SPI

Data Structures

struct LL_SPI_InitTypeDef
SPI Init structures definition. More...
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STM32WB55xx HAL User Manual: SPI Exported Constants

Modules
SPI Exported Constants
SPI

Modules

Get Flags Defines

Flags defines which can be used with LL_SPI_ReadReg function.

IT Defines

IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions.

Operation Mode
Serial Protocol
Clock Phase
Clock Polarity
Baud Rate Prescaler
Transmission Bit Order
Transfer Mode
Slave Select Pin Mode
Datawidth
CRC Calculation
CRC Length
RX FIFO Threshold
RX FIFO Level
TX FIFO Level
DMA Parity
Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SPI Exported Functions

Modules
SPI Exported Functions
SPI

Modules

Configuration
CRC Management
Slave Select Pin Management
FLAG Management
Interrupt Management
DMA Management
DATA Management
Initialization and de-initialization functions
Generated on Fri Sep 6 2019 11:34:53 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SPI Exported Macros

Modules
SPI Exported Macros
SPI

Modules

Common Write and read registers Macros
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STM32WB55xx HAL User Manual: SPIEx

Modules
SPIEx
STM32WBxx_HAL_Driver

SPI Extended HAL module driver. More...

Modules

SPIEx Private Constants
SPIEx Exported Functions

Detailed Description

SPI Extended HAL module driver.

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STM32WB55xx HAL User Manual: SPIEx Exported Functions

Modules
SPIEx Exported Functions
SPIEx

Modules

IO operation functions

Data transfers functions.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: STM32WBxx_HAL_Driver

Modules
STM32WBxx_HAL_Driver

Modules

HAL

HAL module driver.

ADC

ADC HAL module driver.

ADCEx

ADC Extended HAL module driver.

COMP

COMP HAL module driver.

CORTEX

CORTEX HAL module driver.

CRC

CRC HAL module driver.

CRCEx

CRC Extended HAL module driver.

CRYP

CRYP HAL module driver.

CRYPEx

CRYP Extension HAL module driver.

DMA

DMA HAL module driver.

DMAEx

DMA Extended HAL module driver.

EXTI

EXTI HAL module driver.

FLASH

FLASH HAL module driver.

FLASHEx

FLASH Extended HAL module driver.

GPIO

GPIO HAL module driver.

GPIOEx

GPIO Extended HAL module driver.

HSEM

HSEM HAL module driver.

I2C

I2C HAL module driver.

I2CEx

I2C Extended HAL module driver.

IPCC

IPCC HAL module driver.

IRDA

HAL IRDA module driver.

IRDAEx
IWDG

IWDG HAL module driver.

LCD

LCD HAL module driver.

LPTIM

LPTIM HAL module driver.

PCD

PCD HAL module driver.

PCDEx

PCD Extended HAL module driver.

PKA

PKA HAL module driver.

PWR

PWR HAL module driver.

PWREx

PWR Extended HAL module driver.

QSPI

QSPI HAL module driver.

RCC

RCC HAL module driver.

RCCEx

RCC Extended HAL module driver.

RNG

RNG HAL module driver.

RTC

RTC HAL module driver.

RTCEx

RTC Extended HAL module driver.

SAI

SAI HAL module driver.

SAIEx

SAI Extended HAL module driver.

SMARTCARD

HAL SMARTCARD module driver.

SMARTCARDEx

SMARTCARD Extended HAL module driver.

SMBUS

SMBUS HAL module driver.

SPI

SPI HAL module driver.

SPIEx

SPI Extended HAL module driver.

TIM

TIM HAL module driver.

TIMEx

TIM Extended HAL module driver.

TSC

HAL TSC module driver.

UART

HAL UART module driver.

UARTEx

UART Extended HAL module driver.

USART

HAL USART Synchronous module driver.

USARTEx

USART Extended HAL module driver.

WWDG

WWDG HAL module driver.

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STM32WB55xx HAL User Manual: STM32WBxx_LL_Driver

Modules
STM32WBxx_LL_Driver

Modules

ADC
BUS
COMP
CORTEX
CRC
CRS
DMA
DMAMUX
EXTI
GPIO
HSEM
I2C
IPCC
IWDG
LPTIM
LPUART
PKA
PWR
RCC
RNG
RTC
SPI
SYSTEM
TIM
USART
UTILS
WWDG
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STM32WB55xx HAL User Manual: SYSCFG Exported Constants

Modules
SYSCFG Exported Constants
HAL Exported Constants

Modules

BOOT Mode
FPU Interrupts
SRAM2 Page Write protection (0 to 31)
SRAM2 Page Write protection (32 to 63)
VREFBUF Voltage Scale
VREFBUF High Impedance
SRAM Flags
Fast-mode Plus on GPIO
Secure IP Write Access
Generated on Fri Sep 6 2019 11:34:40 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SYSTEM Exported Constants

Modules
SYSTEM Exported Constants
SYSTEM

Modules

SYSCFG REMAP
SYSCFG I2C FASTMODEPLUS
SYSCFG EXTI PORT
SYSCFG EXTI LINE
SYSCFG TIMER BREAK
SYSCFG SRAM2 WRITE PROTECTION
SYSCFG CPU1 INTERRUPT MASK
SYSCFG CPU2 INTERRUPT MASK
SYSCFG SECURE IP ACCESS
DBGMCU CPU1 APB1 GRP1 STOP IP
DBGMCU CPU2 APB1 GRP1 STOP IP
DBGMCU CPU1 APB1 GRP2 STOP IP
DBGMCU CPU2 APB1 GRP2 STOP IP
DBGMCU CPU1 APB2 GRP1 STOP IP
DBGMCU CPU2 APB2 GRP1 STOP IP
VREFBUF VOLTAGE
FLASH LATENCY
Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: SYSTEM Exported Functions

Modules
SYSTEM Exported Functions
SYSTEM

Modules

SYSCFG
DBGMCU
VREFBUF
FLASH
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STM32WB55xx HAL User Manual: TIM

Modules
TIM
STM32WBxx_HAL_Driver

TIM HAL module driver. More...

Modules

TIM Exported Functions
TIM Private Functions
TIM Exported Types
TIM Exported Constants
TIM Exported Macros
TIM Private Constants
TIM Private Macros

Detailed Description

TIM HAL module driver.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM Exported Constants

Modules
TIM Exported Constants
TIM

Modules

TIM Clear Input Source
TIM DMA Base Address
TIM Event Source
TIM Input Channel polarity
TIM ETR Polarity
TIM ETR Prescaler
TIM Counter Mode
TIM Clock Division
TIM Output Compare State
TIM Auto-Reload Preload
TIM Output Fast State
TIM Complementary Output Compare State
TIM Output Compare Polarity
TIM Complementary Output Compare Polarity
TIM Output Compare Idle State
TIM Complementary Output Compare Idle State
TIM Input Capture Polarity
TIM Encoder Input Polarity
TIM Input Capture Selection
TIM Input Capture Prescaler
TIM One Pulse Mode
TIM Encoder Mode
TIM interrupt Definition
TIM Commutation Source
TIM DMA Sources
TIM Flag Definition
TIM Channel
TIM Clock Source
TIM Clock Polarity
TIM Clock Prescaler
TIM Clear Input Polarity
TIM Clear Input Prescaler
TIM OSSR OffState Selection for Run mode state
TIM OSSI OffState Selection for Idle mode state
TIM Lock level
TIM Break Input Enable
TIM Break Input Polarity
TIM Break input 2 Enable
TIM Break Input 2 Polarity
TIM Automatic Output Enable
Group Channel 5 and Channel 1, 2 or 3
TIM Master Mode Selection
TIM Master Mode Selection 2 (TRGO2)
TIM Master/Slave Mode
TIM Slave mode
TIM Output Compare and PWM Modes
TIM Trigger Selection
TIM Trigger Polarity
TIM Trigger Prescaler
TIM TI1 Input Selection
TIM DMA Burst Length
TIM DMA Handle Index
TIM Capture/Compare Channel State
TIM Break System
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STM32WB55xx HAL User Manual: TIM Exported Functions

Modules
TIM Exported Functions
TIM

Modules

TIM Time Base functions

Time Base functions.

TIM Output Compare functions

TIM Output Compare functions.

TIM PWM functions

TIM PWM functions.

TIM Input Capture functions

TIM Input Capture functions.

TIM One Pulse functions

TIM One Pulse functions.

TIM Encoder functions

TIM Encoder functions.

TIM IRQ handler management

TIM IRQ handler management.

TIM Peripheral Control functions

TIM Peripheral Control functions.

TIM Callbacks functions

TIM Callbacks functions.

TIM Peripheral State functions

TIM Peripheral State functions.

Generated on Fri Sep 6 2019 11:34:46 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM Exported Init structure

Data Structures
TIM Exported Init structure
TIM

Data Structures

struct | LL_TIM_InitTypeDef
TIM Time Base configuration structure definition. More...
struct | LL_TIM_OC_InitTypeDef
TIM Output Compare configuration structure definition. More...
struct | LL_TIM_IC_InitTypeDef
TIM Input Capture configuration structure definition. More...
struct | LL_TIM_ENCODER_InitTypeDef
TIM Encoder interface configuration structure definition. More...
struct | LL_TIM_HALLSENSOR_InitTypeDef
TIM Hall sensor interface configuration structure definition. More...
struct | LL_TIM_BDTR_InitTypeDef
BDTR (Break and Dead Time) structure definition. More...
Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM Exported Constants

Modules
TIM Exported Constants
TIM

Modules

Get Flags Defines

Flags defines which can be used with LL_TIM_ReadReg function.

Break Enable
Break2 Enable
Automatic output enable
IT Defines

IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.

Update Source
One Pulse Mode
Counter Mode
Clock Division
Counter Direction
Capture Compare Update Source
Capture Compare DMA Request
Lock Level
Channel
Output Configuration State
Output Configuration Mode
Output Configuration Polarity
Output Configuration Idle State
GROUPCH5
Active Input Selection
Input Configuration Prescaler
Input Configuration Filter
Input Configuration Polarity
Clock Source
Encoder Mode
Trigger Output
Trigger Output 2
Slave Mode
Trigger Selection
External Trigger Polarity
External Trigger Prescaler
External Trigger Filter
External Trigger Source
break polarity
break filter
BREAK2 POLARITY
BREAK2 FILTER
OSSI
OSSR
BREAK INPUT
BKIN SOURCE
BKIN POLARITY
DMA Burst Base Address
DMA Burst Length
TIM1 External Trigger ADC1 Remap
TIM1 External Input Ch1 Remap
TIM2 Internal Trigger1 Remap
TIM2 External Trigger Remap
TIM2 External Input Ch4 Remap
TIM16 External Input Ch1 Remap
TIM17 Timer Input Ch1 Remap
OCREF clear input selection
Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM Exported Functions

Modules
TIM Exported Functions
TIM

Modules

Time Base configuration
Capture Compare configuration
Output channel configuration
Input channel configuration
Counter clock selection
Timer synchronisation configuration
Break function configuration
DMA burst mode configuration
Timer input remapping
OCREF_Clear_Management
FLAG-Management
IT-Management
DMA-Management
EVENT-Management
Initialisation and deinitialisation functions
Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM Exported Macros

Modules
TIM Exported Macros
TIM

Modules

Common Write and read registers Macros
Exported_Macros
Generated on Fri Sep 6 2019 11:34:54 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIMEx

Modules
TIMEx
STM32WBxx_HAL_Driver

TIM Extended HAL module driver. More...

Modules

TIM Extended Exported Functions
TIMEx Private Functions
TIM Extended Exported Types
TIM Extended Exported Constants
TIM Extended Exported Macros
TIM Extended Private Macros

Detailed Description

TIM Extended HAL module driver.

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM Extended Exported Constants

Modules
TIM Extended Exported Constants
TIMEx

Modules

TIM Extended Remapping
TIM Extended Break input
TIM Extended Break input source
TIM Extended Break input source enabling
TIM Extended Break input polarity
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STM32WB55xx HAL User Manual: TIM Extended Exported Functions

Modules
TIM Extended Exported Functions
TIMEx

Modules

Extended Timer Hall Sensor functions

Timer Hall Sensor functions.

Extended Timer Complementary Output Compare functions

Timer Complementary Output Compare functions.

Extended Timer Complementary PWM functions

Timer Complementary PWM functions.

Extended Timer Complementary One Pulse functions

Timer Complementary One Pulse functions.

Extended Peripheral Control functions

Peripheral Control functions.

Extended Callbacks functions

Extended Callbacks functions.

Extended Peripheral State functions

Extended Peripheral State functions.

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TIM Extended Exported Types

Data Structures
TIM Extended Exported Types
TIMEx

Data Structures

struct | TIM_HallSensor_InitTypeDef
TIM Hall sensor Configuration Structure definition. More...
struct | TIMEx_BreakInputConfigTypeDef
TIM Break/Break2 input configuration. More...
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STM32WB55xx HAL User Manual: TSC

Modules
TSC
STM32WBxx_HAL_Driver

HAL TSC module driver. More...

Modules

TSC Exported Functions
TSC Private Functions
TSC Exported Types
TSC Exported Constants
TSC Exported Macros
TSC Private Macros

Detailed Description

HAL TSC module driver.

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: TSC Exported Constants

Modules
TSC Exported Constants
TSC

Modules

TSC Error Code definition

TSC Error Code definition.

CTPulse High Length
CTPulse Low Length
Spread Spectrum Prescaler
Pulse Generator Prescaler
Max Count Value
IO Default Mode
Synchro Pin Polarity
Acquisition Mode
Interrupts definition
Flags definition
Group definition
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STM32WB55xx HAL User Manual: TSC Exported Functions

Modules
TSC Exported Functions
TSC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

Input and Output operation functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State and Errors functions

Peripheral State and Errors functions.

IRQ Handler and Callbacks
Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: UART

Modules
UART
STM32WBxx_HAL_Driver

HAL UART module driver. More...

Modules

UART Private Constants
UART Exported Functions
UART Private Functions
UART Exported Types
UART Exported Constants
UART Exported Macros
UART Private Macros

Detailed Description

HAL UART module driver.

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: UART Exported Constants

Modules
UART Exported Constants
UART

Modules

UART State Code Definition
UART Error Definition
UART Number of Stop Bits
UART Parity
UART Hardware Flow Control
UART Transfer Mode
UART State
UART Over Sampling
UART One Bit Sampling Method
UART Clock Prescaler
UART Advanced Feature AutoBaud Rate Mode
UART Receiver Timeout
UART Local Interconnection Network mode
UART LIN Break Detection
UART DMA Tx
UART DMA Rx
UART Half Duplex Selection
UART WakeUp Methods
UART Request Parameters
UART Advanced Feature Initialization Type
UART Advanced Feature TX Pin Active Level Inversion
UART Advanced Feature RX Pin Active Level Inversion
UART Advanced Feature Binary Data Inversion
UART Advanced Feature RX TX Pins Swap
UART Advanced Feature Overrun Disable
UART Advanced Feature Auto BaudRate Enable
UART Advanced Feature DMA Disable On Rx Error
UART Advanced Feature MSB First
UART Advanced Feature Stop Mode Enable
UART Advanced Feature Mute Mode Enable
UART Address-matching LSB Position In CR2 Register
UART WakeUp From Stop Selection
UART DriverEnable Polarity
UART Driver Enable Assertion Time LSB Position In CR1 Register
UART Driver Enable DeAssertion Time LSB Position In CR1 Register
UART Interruptions Flag Mask
UART polling-based communications time-out value
UART Status Flags

Elements values convention: 0xXXXX.

UART Interrupts Definition

Elements values convention: 000ZZZZZ0XXYYYYYb.

UART Interruption Clear Flags
Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: UART Exported Functions

Modules
UART Exported Functions
UART

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

UART Transmit/Receive functions.

Peripheral Control functions

UART control functions.

Peripheral State and Error functions

UART Peripheral State functions.

Generated on Fri Sep 6 2019 11:34:47 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: UARTEx

Modules
UARTEx
STM32WBxx_HAL_Driver

UART Extended HAL module driver. More...

Modules

UARTEx Private Constants
UARTEx Private Functions
UARTEx Exported Functions
UARTEx Exported Types
UARTEx Exported Constants
UARTEx Private Macros

Detailed Description

UART Extended HAL module driver.

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: UARTEx Exported Constants

Modules
UARTEx Exported Constants
UARTEx

Modules

UARTEx Word Length
UARTEx WakeUp Address Length
UARTEx FIFO mode

UART FIFO mode.

UARTEx TXFIFO threshold level

UART TXFIFO threshold level.

UARTEx RXFIFO threshold level

UART RXFIFO threshold level.

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: UARTEx Exported Functions

Modules
UARTEx Exported Functions
UARTEx

Modules

Initialization and de-initialization functions

Extended Initialization and Configuration Functions.

IO operation functions

Extended functions.

Peripheral Control functions

Extended Peripheral Control functions.

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: UARTEx Exported Types

Data Structures
UARTEx Exported Types
UARTEx

Data Structures

struct UART_WakeUpTypeDef
UART wake up from stop mode parameters. More...
Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: USART

Modules
USART
STM32WBxx_HAL_Driver

HAL USART Synchronous module driver. More...

Modules

USART Private Constants
USART Exported Functions
USART Private Functions
USART Exported Types
USART Exported Constants
USART Exported Macros
USART Private Macros

Detailed Description

HAL USART Synchronous module driver.

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: USART Exported Constants

Modules
USART Exported Constants
USART

Modules

USART Error Definition
USART Number of Stop Bits
USART Parity
USART Mode
USART Over Sampling
USART Clock
USART Clock Polarity
USART Clock Phase
USART Last Bit
USART Clock Prescaler
USART Request Parameters
USART Flags

Elements values convention: 0xXXXX.

USART Interrupts Definition

Elements values convention: 0000ZZZZ0XXYYYYYb.

USART Interruption Clear Flags
USART Interruption Flags Mask
Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: USART Exported Functions

Modules
USART Exported Functions
USART

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

USART Transmit and Receive functions.

Peripheral State and Error functions

USART Peripheral State and Error functions.

Generated on Fri Sep 6 2019 11:34:48 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: USART Exported Init structures

Data Structures
USART Exported Init structures
USART

Data Structures

struct | LL_USART_InitTypeDef
LL USART Init Structure definition. More...
struct | LL_USART_ClockInitTypeDef
LL USART Clock Init Structure definition. More...
Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: USART Exported Constants

Modules
USART Exported Constants
USART

Modules

Clear Flags Defines

Flags defines which can be used with LL_USART_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_USART_ReadReg function.

IT Defines

IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions.

FIFO Threshold
Communication Direction
Parity Control
Wakeup
Datawidth
Oversampling
Clock Signal
Last Clock Pulse
Clock Phase
Clock Polarity
Clock Source Prescaler
Stop Bits
TX RX Pins Swap
RX Pin Active Level Inversion
TX Pin Active Level Inversion
Binary Data Inversion
Bit Order
Autobaud Detection
Address Length Detection
Hardware Control
Wakeup Activation
IrDA Power
LIN Break Detection Length
Driver Enable Polarity
DMA Register Data
Generated on Fri Sep 6 2019 11:34:55 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: USART Exported Functions

Modules
USART Exported Functions
USART

Modules

Configuration functions
Configuration functions related to Irda feature
Configuration functions related to Smartcard feature
Configuration functions related to Half Duplex feature
Configuration functions related to SPI Slave feature
Configuration functions related to LIN feature
Configuration functions related to Driver Enable feature
Advanced Configurations services
FLAG_Management
IT_Management
DMA_Management
Data_Management
Execution
Initialization and de-initialization functions
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STM32WB55xx HAL User Manual: USART Exported Macros

Modules
USART Exported Macros
USART

Modules

Common Write and read registers Macros
Exported_Macros_Helper
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STM32WB55xx HAL User Manual: USARTEx Exported Constants

Modules
USARTEx Exported Constants
USARTEx

Modules

USARTEx Word Length
USARTEx Slave Select Management
USARTEx Synchronous Slave mode enable

USART SLAVE mode.

USARTEx FIFO mode

USART FIFO mode.

USARTEx TXFIFO threshold level

USART TXFIFO level.

USARTEx RXFIFO threshold level

USART RXFIFO level.

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STM32WB55xx HAL User Manual: USARTEx Exported Functions

Modules
USARTEx Exported Functions
USARTEx

Modules

IO operation functions

Extended USART Transmit/Receive functions.

Peripheral Control functions

Extended Peripheral Control functions.

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STM32WB55xx HAL User Manual: UTILS

Modules
UTILS
STM32WBxx_LL_Driver

Modules

UTILS Private functions
UTILS Private Constants
UTILS Private Macros
UTILS Exported structures
UTILS Exported Constants
UTILS Exported Functions
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STM32WB55xx HAL User Manual: UTILS Exported structures

Data Structures
UTILS Exported structures
UTILS

Data Structures

struct | LL_UTILS_PLLInitTypeDef
UTILS PLL structure definition. More...
struct | LL_UTILS_ClkInitTypeDef
UTILS System, AHB and APB buses clock configuration structure definition. More...
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STM32WB55xx HAL User Manual: UTILS Exported Constants

Modules
UTILS Exported Constants
UTILS

Modules

HSE Bypass activation
PACKAGE TYPE
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STM32WB55xx HAL User Manual: UTILS Exported Functions

Modules
UTILS Exported Functions
UTILS

Modules

DEVICE ELECTRONIC SIGNATURE
DELAY
SYSTEM

System Configuration functions.

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STM32WB55xx HAL User Manual: WWDG

Modules
WWDG
STM32WBxx_HAL_Driver

WWDG HAL module driver. More...

Modules

WWDG Exported Functions
WWDG Exported Types
WWDG Exported Constants
WWDG Private Macros
WWDG Exported Macros

Detailed Description

WWDG HAL module driver.

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STM32WB55xx HAL User Manual: WWDG Exported Constants

Modules
WWDG Exported Constants
WWDG

Modules

WWDG Interrupt definition
WWDG Flag definition

WWDG Flag definition.

WWDG Prescaler
WWDG Early Wakeup Interrupt Mode
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STM32WB55xx HAL User Manual: WWDG Exported Functions

Modules
WWDG Exported Functions
WWDG

Modules

Initialization and Configuration functions

Initialization and Configuration functions.

IO operation functions

IO operation functions.

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STM32WB55xx HAL User Manual: WWDG Exported Constants

Modules
WWDG Exported Constants
WWDG

Modules

IT Defines

IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions.

PRESCALER
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STM32WB55xx HAL User Manual: WWDG Exported Functions

Modules
WWDG Exported Functions
WWDG

Modules

Configuration
FLAG_Management
IT_Management
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STM32WB55xx HAL User Manual: WWDG Exported Macros

Modules
WWDG Exported Macros
WWDG

Modules

Common Write and read registers macros
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STM32WB55xx HAL User Manual: HSEM_rmtollPages.txt File Reference

  • File List
  • Globals
HSEM_rmtollPages.txt File Reference
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STM32WB55xx HAL User Manual: I2C_rmtollPages.txt File Reference

  • File List
  • Globals
I2C_rmtollPages.txt File Reference
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STM32WB55xx HAL User Manual: IPCC_rmtollPages.txt File Reference

  • File List
  • Globals
IPCC_rmtollPages.txt File Reference
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STM32WB55xx HAL User Manual: IWDG_rmtollPages.txt File Reference

  • File List
  • Globals
IWDG_rmtollPages.txt File Reference
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STM32WB55xx HAL User Manual: LPTIM_rmtollPages.txt File Reference

  • File List
  • Globals
LPTIM_rmtollPages.txt File Reference
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STM32WB55xx HAL User Manual: LPUART_rmtollPages.txt File Reference

  • File List
  • Globals
LPUART_rmtollPages.txt File Reference
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STM32WB55xx HAL User Manual: Modules

Modules
Here is a list of all modules:
  • STM32WBxx_LL_Driver
    • ADC
      • ADC Private Constants
      • ADC Private Macros
      • ADC Exported Init structure
      • ADC Exported Constants
        • ADC flags
        • ADC interruptions for configuration (interruption enable or disable)
        • ADC registers compliant with specific purpose
        • ADC common - Clock source
        • ADC common - Measurement path to internal channels
        • ADC instance - Resolution
        • ADC instance - Data alignment
        • ADC instance - Low power mode
        • ADC instance - Offset number
        • ADC instance - Offset state
        • ADC instance - Groups
        • ADC instance - Channel number
        • ADC group regular - Trigger source
        • ADC group regular - Trigger edge
        • ADC group regular - Continuous mode
        • ADC group regular - DMA transfer of ADC conversion data
        • ADC group regular - Overrun behavior on conversion data
        • ADC group regular - Sequencer scan length
        • ADC group regular - Sequencer discontinuous mode
        • ADC group regular - Sequencer ranks
        • ADC group injected - Trigger source
        • ADC group injected - Trigger edge
        • ADC group injected - Automatic trigger mode
        • ADC group injected - Context queue mode
        • ADC group injected - Sequencer scan length
        • ADC group injected - Sequencer discontinuous mode
        • ADC group injected - Sequencer ranks
        • Channel - Sampling time
        • Channel - Single or differential ending
        • Analog watchdog - Analog watchdog number
        • Analog watchdog - Monitored channels
        • Analog watchdog - Thresholds
        • Oversampling - Oversampling scope
        • Oversampling - Discontinuous mode
        • Oversampling - Ratio
        • Oversampling - Data shift
        • Definitions of ADC hardware constraints delays
      • ADC Exported Macros
        • Common write and read registers Macros
        • ADC helper macro
      • ADC Exported Functions
        • ADC DMA management
        • Configuration of ADC hierarchical scope: common to several ADC instances
        • Configuration of ADC hierarchical scope: ADC instance
        • Configuration of ADC hierarchical scope: group regular
        • Configuration of ADC hierarchical scope: group injected
        • Configuration of ADC hierarchical scope: channels
        • Configuration of ADC transversal scope: analog watchdog
        • Configuration of ADC transversal scope: oversampling
        • Operation on ADC hierarchical scope: ADC instance
        • Operation on ADC hierarchical scope: group regular
        • Operation on ADC hierarchical scope: group injected
        • ADC flag management
        • ADC IT management
        • Initialization and de-initialization functions
    • BUS
      • BUS Exported Constants
        • AHB1 GRP1 PERIPH
        • AHB2 GRP1 PERIPH
        • AHB3 GRP1 PERIPH
        • APB1 GRP1 PERIPH
        • APB1 GRP2 PERIPH
        • APB2 GRP1 PERIPH
        • APB3 GRP1 PERIPH
        • C2 AHB1 GRP1 PERIPH
        • C2 AHB2 GRP1 PERIPH
        • C2 AHB3 GRP1 PERIPH
        • C2 APB1 GRP1 PERIPH
        • C2 APB1 GRP2 PERIPH
        • C2 APB2 GRP1 PERIPH
        • C2 APB3 GRP1 PERIPH
      • BUS Exported Functions
        • AHB1
        • AHB2
        • AHB3
        • APB1
        • APB2
        • APB3
        • C2 AHB1
        • C2 AHB2
        • C2 AHB3
        • C2 APB1
        • C2 APB2
        • C2 APB3
    • COMP
      • COMP Private Constants
      • COMP Exported Init structure
      • COMP Exported Constants
        • Comparator common modes - Window mode
        • Comparator modes - Power mode
        • Comparator inputs - Input plus (input non-inverting) selection
        • Comparator inputs - Input minus (input inverting) selection
        • Comparator input - Hysteresis
        • Comparator output - Output polarity
        • Comparator output - Blanking source
        • Comparator output - Output level
        • Definitions of COMP hardware constraints delays
      • COMP Exported Macros
        • Common write and read registers macro
        • COMP helper macro
      • COMP Exported Functions
        • Configuration of COMP hierarchical scope: common to several COMP instances
        • Configuration of comparator modes
        • Configuration of comparator inputs
        • Configuration of comparator output
        • Operation on comparator instance
        • Initialization and de-initialization functions
      • COMP_LL_Private_Macros
    • CORTEX
      • CORTEX Exported Constants
        • SYSTICK Clock Source
        • Handler Fault type
        • MPU Control
        • MPU Region Number
        • MPU Region Size
        • MPU Region Privileges
        • MPU TEX Level
        • MPU Instruction Access
        • MPU Shareable Access
        • MPU Cacheable Access
        • MPU Bufferable Access
      • CORTEX Exported Functions
        • SYSTICK
        • LOW POWER MODE
        • HANDLER
        • MCU INFO
        • MPU
    • CRC
      • CRC Exported Constants
        • Polynomial length
        • Input Data Reverse
        • Output Data Reverse
        • Default CRC generating polynomial value
        • Default CRC computation initialization value
      • CRC Exported Macros
        • Common Write and read registers Macros
      • CRC Exported Functions
        • CRC Configuration functions
        • Data_Management
        • Initialization and de-initialization functions
    • CRS
      • CRS Private Constants
      • CRS Exported Constants
        • Get Flags Defines
        • IT Defines
        • Synchronization Signal Divider
        • Synchronization Signal Source
        • Synchronization Signal Polarity
        • Frequency Error Direction
        • Default Values
      • CRS Exported Macros
        • Common Write and read registers Macros
        • Exported_Macros_Calculate_Reload
      • CRS Exported Functions
        • Configuration
        • CRS_Management
        • FLAG_Management
        • IT_Management
        • Initialization and de-initialization functions
    • DMA
      • DMA Private Macros
      • DMA Exported Init structure
      • DMA Exported Constants
        • Clear Flags Defines
        • Get Flags Defines
        • IT Defines
        • CHANNEL
        • Transfer Direction
        • Transfer mode
        • Peripheral increment mode
        • Memory increment mode
        • Peripheral data alignment
        • Memory data alignment
        • Transfer Priority level
      • DMA Exported Macros
        • Common Write and read registers macros
        • Convert DMAxChannely
      • DMA Exported Functions
        • Configuration
        • FLAG_Management
        • IT_Management
        • Initialization and de-initialization functions
    • DMAMUX
      • DMAMUX Private Constants
      • DMAMUX Exported Constants
        • Clear Flags Defines
        • Get Flags Defines
        • IT Defines
        • Transfer request
        • DMAMUX Channel
        • Synchronization Signal Polarity
        • Synchronization Signal Event
        • Request Generator Channel
        • External Request Signal Generation Polarity
        • External Request Signal Generation
      • DMAMUX Exported Macros
        • Common Write and read registers macros
      • DMAMUX Exported Functions
        • Configuration
        • FLAG_Management
        • IT_Management
    • EXTI
      • EXTI Private Macros
      • EXTI Exported Init structure
      • EXTI Exported Constants
        • LINE
        • Mode
        • Edge Trigger
      • EXTI Exported Macros
        • Common Write and read registers Macros
      • EXTI Exported Functions
        • IT_Management
        • Event_Management
        • Rising_Trigger_Management
        • Falling_Trigger_Management
        • Software_Interrupt_Management
        • Flag_Management
        • Initialization and de-initialization functions
    • GPIO
      • GPIO Private Macros
      • GPIO Exported Init structures
      • GPIO Exported Constants
        • PIN
        • Mode
        • Output Type
        • Output Speed
        • Pull Up Pull Down
        • Alternate Function
      • GPIO Exported Macros
        • Common Write and read registers Macros
      • GPIO Exported Functions
        • Port Configuration
        • Data Access
        • Initialization and de-initialization functions
    • HSEM
      • HSEM Exported Constants
        • COREID Defines
        • Get Flags Defines
      • HSEM Exported Macros
        • Common Write and read registers Macros
      • HSEM Exported Functions
        • Data_Management
        • IT_Management
        • FLAG_Management
    • I2C
      • I2C Private Constants
      • I2C Private Macros
      • I2C Exported Init structure
      • I2C Exported Constants
        • Clear Flags Defines
        • Get Flags Defines
        • IT Defines
        • Peripheral Mode
        • Analog Filter Selection
        • Master Addressing Mode
        • Own Address 1 Length
        • Own Address 2 Masks
        • Acknowledge Generation
        • Slave Address Length
        • Transfer Request Direction
        • Transfer End Mode
        • Start And Stop Generation
        • Read Write Direction
        • DMA Register Data
        • SMBus TimeoutA Mode SCL SDA Timeout
        • SMBus Timeout Selection
      • I2C Exported Macros
        • Common Write and read registers Macros
        • Convert SDA SCL timings
      • I2C Exported Functions
        • Configuration
        • IT_Management
        • FLAG_management
        • Data_Management
        • Initialization and de-initialization functions
    • IPCC
      • IPCC Exported Constants
        • Get Flags Defines
        • Channel
      • IPCC Exported Macros
        • Common Write and read registers Macros
      • IPCC Exported Functions
        • IT_Management
        • Configuration
        • FLAG_Management
    • IWDG
      • IWDG Private Constants
      • IWDG Exported Constants
        • Get Flags Defines
        • Prescaler Divider
      • IWDG Exported Macros
        • Common Write and read registers Macros
      • IWDG Exported Functions
        • Configuration
        • FLAG_Management
    • LPTIM
      • LPTIM Private Functions
      • LPTIM Private Macros
      • LPTIM Exported Init structure
      • LPTIM Exported Constants
        • Get Flags Defines
        • IT Defines
        • Operating Mode
        • Update Mode
        • Counter Mode
        • Output Waveform Type
        • Output Polarity
        • Prescaler Value
        • Trigger Source
        • Trigger Filter
        • Trigger Polarity
        • Clock Source
        • Clock Filter
        • Clock Polarity
        • Encoder Mode
        • Input1 Source
        • Input2 Source
      • LPTIM Exported Macros
        • Common Write and read registers Macros
      • LPTIM Exported Functions
        • Initialisation and deinitialisation functions
        • LPTIM Configuration
        • Trigger Configuration
        • Clock Configuration
        • Encoder Mode
        • FLAG Management
        • Interrupt Management
    • LPUART
      • LPUART Private Variables
      • LPUART Private Constants
      • LPUART Private Macros
      • LPUART Exported Init structures
      • LPUART Exported Constants
        • Clear Flags Defines
        • Get Flags Defines
        • IT Defines
        • FIFO Threshold
        • Direction
        • Parity Control
        • Wakeup
        • Datawidth
        • Clock Source Prescaler
        • Stop Bits
        • TX RX Pins Swap
        • RX Pin Active Level Inversion
        • TX Pin Active Level Inversion
        • Binary Data Inversion
        • Bit Order
        • Address Length Detection
        • Hardware Control
        • Wakeup Activation
        • Driver Enable Polarity
        • DMA Register Data
      • LPUART Exported Macros
        • Common Write and read registers Macros
        • Helper Macros
      • LPUART Exported Functions
        • Configuration functions
        • Configuration functions related to Half Duplex feature
        • Configuration functions related to Driver Enable feature
        • FLAG_Management
        • IT_Management
        • DMA_Management
        • Data_Management
        • Execution
        • Initialization and de-initialization functions
    • PKA
      • PKA Private Constants
      • PKA Exported Init structure
      • PKA Exported Constants
        • Get Flags Defines
        • IT Defines
        • Operation Mode
      • PKA Exported Macros
        • Common Write and read registers Macros
      • PKA Exported Functions
        • Configuration
        • IT_Management
        • PKA flag management
        • Initialization and de-initialization functions
    • PWR
      • PWR Private Constants
        • PWR SMPS calibration
      • PWR Exported Constants
        • Clear Flags Defines
        • Get Flags Defines
        • REGU VOLTAGE
        • MODE PWR
        • Flash power-down mode during low-power run mode
        • Flash power-down mode during sleep mode
        • Peripheral voltage monitoring
        • PVDLEVEL
        • WAKEUP
        • BATT CHARG RESISTOR
        • GPIO
        • GPIO BIT
        • BOR configuration
        • SMPS step down converter operating modes
        • SMPS step down converter supply startup current selection
        • SMPS step down converter output voltage scaling voltage level
      • PWR Exported Macros
        • Common Write and read registers Macros
      • PWR Exported Functions
        • Configuration
        • Configuration of SMPS
        • Configuration of multicore, intended to be executed by CPU1
        • Configuration of CPU2, intended to be executed by CPU2
        • Configuration of radio (BLE or 802.15.4) of CPU2, intended to be executed by CPU2
        • FLAG_Management
        • FLAG management for SMPS
        • FLAG management for radio (BLE or 802.15.4)
        • FLAG management for multicore
        • PWR IT management for SMPS
        • PWR IT management for radio (BLE or 802.15.4)
        • PWR IT management for multicore
        • PWR IT management of CPU2, intended to be executed by CPU2
        • De-initialization function
    • RCC
      • RCC Private functions
      • RCC Private Variables
      • RCC Private Macros
      • RCC Exported Types
        • Clocks Frequency Structure
      • RCC Exported Constants
        • Oscillator Values adaptation
        • Clear Flags Defines
        • Get Flags Defines
        • IT Defines
        • LSE oscillator drive capability
        • MSI clock ranges
        • HSE current control max limits
        • HSE sense amplifier threshold
        • LSCO Selection
        • System clock switch
        • System clock switch status
        • RF system clock switch status
        • AHB prescaler
        • APB low-speed prescaler (APB1)
        • APB high-speed prescaler (APB2)
        • Wakeup from Stop and CSS backup clock selection
        • MCO1 SOURCE selection
        • MCO1 prescaler
        • SMPS clock switch
        • SMPS clock switch status
        • SMPS prescaler
        • Peripheral clock frequency
        • USART1 CLKSOURCE
        • LPUART1 CLKSOURCE
        • I2Cx CLKSOURCE
        • LPTIMx CLKSOURCE
        • SAI1 CLKSOURCE
        • CLK48 CLKSOURCE
        • USB CLKSOURCE
        • ADC CLKSRC
        • RNG CLKSRC
        • USART1
        • LPUART1
        • I2C1
        • LPTIM1
        • SAI1
        • CLK48
        • USB
        • RNG
        • ADC
        • RTC clock source selection
        • RF Wakeup clock source selection
        • PLL and PLLSAI1 entry clock source
        • PLL and PLLSAI1 division factor
        • PLL division factor (PLLR)
        • PLL division factor (PLLP)
        • PLL division factor (PLLQ)
        • PLLSAI1 division factor (PLLQ)
        • PLLSAI1 division factor (PLLP)
        • PLLSAI1 division factor (PLLR)
      • RCC Exported Macros
        • Common Write and read registers Macros
        • Calculate frequencies
      • RCC Exported Functions
        • HSE
        • HSI
        • HSI48
        • LSE
        • LSI1
        • LSI2
        • MSI
        • LSCO
        • System
        • SMPS
        • MCO
        • Peripheral Clock Source
        • RTC
        • PLL
        • PLLSAI1
        • FLAG Management
        • IT Management
        • De-initialization function
        • Get system and peripherals clocks frequency functions
    • RNG
      • RNG Exported Init structures
      • RNG Exported Constants
        • Clock Error Detection
        • Get Flags Defines
        • IT Defines
      • RNG Exported Macros
        • Common Write and read registers Macros
      • RNG Exported Functions
        • RNG Configuration functions
        • FLAG Management
        • IT Management
        • Data Management
        • Initialization and de-initialization functions
      • RNG_LL_Private_Macros
    • RTC
      • RTC Private Constants
      • RTC Private Macros
      • RTC Exported Init structure
      • RTC Exported Constants
        • FORMAT
        • RTC Alarm A Date WeekDay
        • RTC Alarm B Date WeekDay
        • Get Flags Defines
        • IT Defines
        • WEEK DAY
        • MONTH
        • HOUR FORMAT
        • ALARM OUTPUT
        • ALARM OUTPUT TYPE
        • OUTPUT POLARITY PIN
        • TIME FORMAT
        • SHIFT SECOND
        • ALARMA MASK
        • ALARMA TIME FORMAT
        • ALARMB MASK
        • ALARMB TIME FORMAT
        • TIMESTAMP EDGE
        • TIMESTAMP TIME FORMAT
        • TAMPER
        • TAMPER MASK
        • TAMPER NO ERASE
        • TAMPER DURATION
        • TAMPER FILTER
        • TAMPER SAMPLING FREQUENCY DIVIDER
        • TAMPER ACTIVE LEVEL
        • WAKEUP CLOCK DIV
        • BACKUP
        • Calibration output
        • Calibration pulse insertion
        • Calibration period
      • RTC Exported Macros
        • Common Write and read registers Macros
        • Convert helper Macros
        • Date helper Macros
        • Time helper Macros
      • RTC Exported Functions
        • Configuration
        • Time
        • Date
        • ALARMA
        • ALARMB
        • Timestamp
        • Tamper
        • Wakeup
        • Backup_Registers
        • Calibration
        • FLAG_Management
        • IT_Management
        • Initialization and de-initialization functions
    • SPI
      • SPI Private Constants
      • SPI Private Macros
      • SPI Exported Init structure
      • SPI Exported Constants
        • Get Flags Defines
        • IT Defines
        • Operation Mode
        • Serial Protocol
        • Clock Phase
        • Clock Polarity
        • Baud Rate Prescaler
        • Transmission Bit Order
        • Transfer Mode
        • Slave Select Pin Mode
        • Datawidth
        • CRC Calculation
        • CRC Length
        • RX FIFO Threshold
        • RX FIFO Level
        • TX FIFO Level
        • DMA Parity
      • SPI Exported Macros
        • Common Write and read registers Macros
      • SPI Exported Functions
        • Configuration
        • CRC Management
        • Slave Select Pin Management
        • FLAG Management
        • Interrupt Management
        • DMA Management
        • DATA Management
        • Initialization and de-initialization functions
    • SYSTEM
      • SYSTEM Private Constants
      • SYSTEM Exported Constants
        • SYSCFG REMAP
        • SYSCFG I2C FASTMODEPLUS
        • SYSCFG EXTI PORT
        • SYSCFG EXTI LINE
        • SYSCFG TIMER BREAK
        • SYSCFG SRAM2 WRITE PROTECTION
        • SYSCFG CPU1 INTERRUPT MASK
        • SYSCFG CPU2 INTERRUPT MASK
        • SYSCFG SECURE IP ACCESS
        • DBGMCU CPU1 APB1 GRP1 STOP IP
        • DBGMCU CPU2 APB1 GRP1 STOP IP
        • DBGMCU CPU1 APB1 GRP2 STOP IP
        • DBGMCU CPU2 APB1 GRP2 STOP IP
        • DBGMCU CPU1 APB2 GRP1 STOP IP
        • DBGMCU CPU2 APB2 GRP1 STOP IP
        • VREFBUF VOLTAGE
        • FLASH LATENCY
      • SYSTEM Exported Functions
        • SYSCFG
        • DBGMCU
        • VREFBUF
        • FLASH
    • TIM
      • TIM Private Functions
      • TIM Private Variables
      • TIM Private Constants
      • TIM Private Macros
      • TIM Exported Init structure
      • TIM Exported Constants
        • Get Flags Defines
        • Break Enable
        • Break2 Enable
        • Automatic output enable
        • IT Defines
        • Update Source
        • One Pulse Mode
        • Counter Mode
        • Clock Division
        • Counter Direction
        • Capture Compare Update Source
        • Capture Compare DMA Request
        • Lock Level
        • Channel
        • Output Configuration State
        • Output Configuration Mode
        • Output Configuration Polarity
        • Output Configuration Idle State
        • GROUPCH5
        • Active Input Selection
        • Input Configuration Prescaler
        • Input Configuration Filter
        • Input Configuration Polarity
        • Clock Source
        • Encoder Mode
        • Trigger Output
        • Trigger Output 2
        • Slave Mode
        • Trigger Selection
        • External Trigger Polarity
        • External Trigger Prescaler
        • External Trigger Filter
        • External Trigger Source
        • break polarity
        • break filter
        • BREAK2 POLARITY
        • BREAK2 FILTER
        • OSSI
        • OSSR
        • BREAK INPUT
        • BKIN SOURCE
        • BKIN POLARITY
        • DMA Burst Base Address
        • DMA Burst Length
        • TIM1 External Trigger ADC1 Remap
        • TIM1 External Input Ch1 Remap
        • TIM2 Internal Trigger1 Remap
        • TIM2 External Trigger Remap
        • TIM2 External Input Ch4 Remap
        • TIM16 External Input Ch1 Remap
        • TIM17 Timer Input Ch1 Remap
        • OCREF clear input selection
      • TIM Exported Macros
        • Common Write and read registers Macros
        • Exported_Macros
      • TIM Exported Functions
        • Time Base configuration
        • Capture Compare configuration
        • Output channel configuration
        • Input channel configuration
        • Counter clock selection
        • Timer synchronisation configuration
        • Break function configuration
        • DMA burst mode configuration
        • Timer input remapping
        • OCREF_Clear_Management
        • FLAG-Management
        • IT-Management
        • DMA-Management
        • EVENT-Management
        • Initialisation and deinitialisation functions
    • USART
      • USART Private Variables
      • USART Private Constants
      • USART Private Macros
      • USART Exported Init structures
      • USART Exported Constants
        • Clear Flags Defines
        • Get Flags Defines
        • IT Defines
        • FIFO Threshold
        • Communication Direction
        • Parity Control
        • Wakeup
        • Datawidth
        • Oversampling
        • Clock Signal
        • Last Clock Pulse
        • Clock Phase
        • Clock Polarity
        • Clock Source Prescaler
        • Stop Bits
        • TX RX Pins Swap
        • RX Pin Active Level Inversion
        • TX Pin Active Level Inversion
        • Binary Data Inversion
        • Bit Order
        • Autobaud Detection
        • Address Length Detection
        • Hardware Control
        • Wakeup Activation
        • IrDA Power
        • LIN Break Detection Length
        • Driver Enable Polarity
        • DMA Register Data
      • USART Exported Macros
        • Common Write and read registers Macros
        • Exported_Macros_Helper
      • USART Exported Functions
        • Configuration functions
        • Configuration functions related to Irda feature
        • Configuration functions related to Smartcard feature
        • Configuration functions related to Half Duplex feature
        • Configuration functions related to SPI Slave feature
        • Configuration functions related to LIN feature
        • Configuration functions related to Driver Enable feature
        • Advanced Configurations services
        • FLAG_Management
        • IT_Management
        • DMA_Management
        • Data_Management
        • Execution
        • Initialization and de-initialization functions
    • UTILS
      • UTILS Private functions
      • UTILS Private Constants
      • UTILS Private Macros
      • UTILS Exported structures
      • UTILS Exported Constants
        • HSE Bypass activation
        • PACKAGE TYPE
      • UTILS Exported Functions
        • DEVICE ELECTRONIC SIGNATURE
        • DELAY
        • SYSTEM
    • WWDG
      • WWDG Exported Constants
        • IT Defines
        • PRESCALER
      • WWDG Exported Macros
        • Common Write and read registers macros
      • WWDG Exported Functions
        • Configuration
        • FLAG_Management
        • IT_Management
  • STM32WBxx_HAL_Driver
    • HAL
      • HAL Private Constants
      • HAL Exported Variables
      • HAL Exported Constants
        • Tick Frequency
        • SYSCFG Exported Constants
          • BOOT Mode
          • FPU Interrupts
          • SRAM2 Page Write protection (0 to 31)
          • SRAM2 Page Write protection (32 to 63)
          • VREFBUF Voltage Scale
          • VREFBUF High Impedance
          • SRAM Flags
          • Fast-mode Plus on GPIO
          • Secure IP Write Access
      • HAL Exported Macros
        • DBGMCU Exported Macros
          • DBGMCU CPU1 APBx GRPx STOP IP
          • DBGMCU CPU2 APBx GRPx STOP IP
        • SYSCFG Exported Macros
      • HAL Private Macros
        • SYSCFG Private Macros
      • HAL Exported Functions
        • HAL System Configuration functions
        • HAL Initialization and Configuration functions
        • HAL Control functions
        • HAL Debug functions
        • HAL Exported Variables
    • ADC
      • ADC Private Constants
      • ADC Exported Functions
        • Initialization and de-initialization functions
        • ADC Input and Output operation functions
        • Peripheral Control functions
        • Peripheral State functions
      • ADC Private Functions
      • ADC Exported Types
        • ADC States
      • ADC Exported Constants
        • ADC Error Code
        • ADC common - Clock source
        • ADC instance - Resolution
        • ADC conversion data alignment
        • ADC sequencer scan mode
        • ADC group regular trigger source
        • ADC group regular trigger edge (when external trigger is selected)
        • ADC sequencer end of unitary conversion or sequence conversions
        • ADC group regular - Overrun behavior on conversion data
        • ADC group regular - Sequencer ranks
        • Channel - Sampling time
        • ADC instance - Channel number
        • Analog watchdog - Analog watchdog number
        • ADC Analog Watchdog Mode
        • Oversampling - Ratio
        • Oversampling - Data shift
        • Oversampling - Discontinuous mode
        • Oversampling - Oversampling scope for ADC group regular
        • ADC Event type
        • ADC interrupts definition
        • ADC flags definition
      • ADC Private Macros
      • ADC Exported Macros
        • HAL ADC macro to manage HAL ADC handle, IT and flags.
        • HAL ADC helper macro
    • ADCEx
      • ADC Extended Private Constants
      • ADC Extended Exported Functions
        • Extended Input and Output operation functions
        • ADC Extended Peripheral Control functions
      • ADC Extended Exported Types
      • ADC Extended Exported Constants
        • ADC group injected trigger source
        • ADC group injected trigger edge (when external trigger is selected)
        • Channel - Single or differential ending
        • ADC instance - Offset number
        • ADC group injected - Sequencer ranks
        • ADC instance - Groups
        • ADCx CFGR fields
        • ADCx SMPR1 fields
        • ADCx CFGR sub fields
      • ADC Extended Private Macros
    • COMP
      • COMP Exported Functions
        • Initialization/de-initialization functions
        • Start-Stop operation functions
        • Peripheral Control functions
        • Peripheral State functions
      • COMP Exported Types
      • COMP Exported Constants
        • COMP Error Code
        • COMP Window Mode
        • COMP power mode
        • COMP input plus (non-inverting input)
        • COMP input minus (inverting input)
        • COMP hysteresis
        • COMP output Polarity
        • COMP blanking source
        • COMP Output Level
        • COMP output to EXTI
      • COMP Exported Macros
        • COMP Handle Management
        • COMP external interrupt line management
      • COMP Private Constants
        • COMP EXTI Lines
      • COMP Private Macros
        • COMP private macros to get EXTI line associated with comparators
        • COMP private macros to check input parameters
    • CORTEX
      • CORTEX Exported Types
        • MPU Region Initialization Structure Definition
      • CORTEX Exported Constants
        • CORTEX Preemption Priority Group
        • CORTEX SysTick clock source
        • CORTEX MPU HFNMI and PRIVILEGED Access control
        • CORTEX MPU Region Enable
        • CORTEX MPU Instruction Access
        • CORTEX MPU Instruction Access Shareable
        • CORTEX MPU Instruction Access Cacheable
        • CORTEX MPU Instruction Access Bufferable
        • CORTEX MPU TEX Levels
        • CORTEX MPU Region Size
        • CORTEX MPU Region Permission Attributes
        • CORTEX MPU Region Number
      • CORTEX Exported Macros
      • CORTEX Exported Functions
        • Initialization and Configuration functions
        • Peripheral Control functions
      • CORTEX Private Macros
    • CRC
      • CRC Private Functions
      • CRC Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
        • Peripheral State functions
      • CRC Exported Types
      • CRC Exported Constants
        • Default CRC generating polynomial
        • Default CRC computation initialization value
        • Indicates whether or not default polynomial is used
        • Indicates whether or not default init value is used
        • Polynomial sizes to configure the peripheral
        • CRC polynomial possible sizes actual definitions
        • Input Buffer Format
        • CRC API aliases
      • CRC Exported Macros
      • CRC Private Macros
    • CRCEx
      • CRC Extended Exported Functions
        • Extended Initialization/de-initialization functions
      • CRC Extended Exported Constants
        • Input Data Inversion Modes
        • Output Data Inversion Modes
      • CRC Extended Exported Macros
      • CRC Extended Private Macros
    • CRYP
      • CRYP Exported Types
        • HAL CRYP Callback ID enumeration definition
        • HAL CRYP Callback pointer definition
      • CRYP Exported Constants
        • CRYP Error Definition
        • CRYP Data Width Unit
        • CRYP Algorithm Mode
        • CRYP Key Size
        • CRYP Data Type
        • CRYP Interrupt
        • CRYP Flags
        • CRYP Key and IV Configuration Skip Mode
      • CRYP Exported Macros
      • CRYP Exported Functions
        • Initialization and de-initialization functions
        • Encryption Decryption functions
        • CRYP IRQ handler management
      • CRYP Private Macros
        • CRYP Private macros to check input parameters
      • CRYP Private Constants
      • CRYP Private Defines
      • CRYP Private Variables
      • CRYP Private Functions
    • CRYPEx
      • CRYPEx Private Types
      • CRYPEx Private Variables
      • CRYPEx Private Constants
      • CRYPEx Private Macros
      • CRYPEx Private Functions
      • CRYPEx Exported Functions
        • Extended AES processing functions
        • Extended AES Key Derivations functions
      • CRYPEx_Private_Defines
    • DMA
      • DMA Private Functions
      • DMA Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • Peripheral State and Errors functions
      • DMA Exported Types
      • DMA Exported Constants
        • DMA Error Code
        • DMA request
        • DMA Data transfer direction
        • DMA Peripheral incremented mode
        • DMA Memory incremented mode
        • DMA Peripheral data size
        • DMA Memory data size
        • DMA mode
        • DMA Priority level
        • DMA interrupt enable definitions
        • DMA flag definitions
      • DMA Exported Macros
      • DMA Private Macros
    • DMAEx
      • DMAEx Exported Functions
        • DMAEx Extended features functions
      • DMAEx Exported Types
      • DMAEx Exported Constants
        • DMAMUX SyncSignalID selection
        • DMAMUX SyncPolarity selection
        • DMAMUX SignalGeneratorID selection
        • DMAMUX RequestGeneneratorPolarity selection
      • DMAEx Private Macros
    • EXTI
      • EXTI Private Constants
      • EXTI Exported Types
      • EXTI Exported Constants
        • EXTI Line
        • EXTI Mode
        • EXTI Trigger
        • EXTI GPIOSel
      • EXTI Exported Macros
      • EXTI Private Macros
      • EXTI Exported Functions
        • Configuration functions
        • IO operation functions
    • FLASH
      • FLASH Private Variables
      • FLASH Private Functions
      • FLASH Exported Functions
        • Programming operation functions
        • Peripheral Control functions
        • Peripheral State and Errors functions
      • FLASH Exported Types
      • FLASH Exported Constants
        • FLASH Keys
        • FLASH Latency
        • FLASH Flags Definition
          • FLASH Interrupts Definition
          • FLASH Error
          • FLASH Erase Type
          • FLASH Program Type
          • FLASH Option Bytes Type
          • FLASH WRP Area
          • FLASH Option Bytes Read Protection
          • FLASH Option Bytes User Type
          • FLASH Option Bytes Automatic Gain Control Trimming
          • FLASH Option Bytes User BOR Level
          • FLASH Option Bytes User Reset On Stop
          • FLASH Option Bytes User Reset On Standby
          • FLASH Option Bytes User Reset On Shutdown
          • FLASH Option Bytes User IWDG Type
          • FLASH Option Bytes User IWDG Mode On Stop
          • FLASH Option Bytes User IWDG Mode On Standby
          • FLASH Option Bytes User WWDG Type
          • FLASH Option Bytes SRAM2 parity check
          • FLASH Option Bytes SRAM2 erase when system reset
          • FLASH Option Bytes User BOOT1 Type
          • FLASH Option Bytes User Software BOOT0
          • FLASH Option Bytes User nBOOT0 option bit
          • FLASH PCROP ZONE
          • FLASH Option Bytes PCROP On RDP Level Type
          • Option Bytes FLASH Secure mode
          • CPU2 Option Bytes Reset Boot Vector
        • RAM2A address range in secure mode
        • RAM2B address range in secure mode
      • FLASH Exported Macros
      • FLASH Interrupts Macros
      • FLASH Exported Variables
      • FLASH Private Types
      • FLASH Private Constants
      • SRAM memory size
      • FLASH Private Macros
    • FLASHEx
      • FLASHEx Private Functions
      • FLASH Extended Exported Functions
        • Extended IO operation functions
      • FLASH Exported Constants
        • FLASHEx Empty Check
      • FLASHEx Private Macros
    • GPIO
      • GPIO Private Constants
      • GPIO Exported Types
      • GPIO Exported Constants
        • GPIO pins
        • GPIO mode
        • GPIO speed
        • GPIO pull
      • GPIO Exported Macros
      • GPIO Private Macros
      • GPIO Exported Functions
        • Initialization/de-initialization functions
        • IO operation functions
    • GPIOEx
      • GPIOEx Exported Constants
        • GPIOEx Alternate function selection
      • GPIOEx Exported Macros
        • GPIOEx Get Port Index
    • HSEM
      • HSEM Exported Functions
        • Take and Release functions
        • HSEM Set and Get Key functions
        • HSEM IRQ handler management
      • HSEM Exported Macros
      • HSEM Private Macros
    • I2C
      • I2C Private Define
      • I2C Private Functions
      • I2C Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • IRQ Handler and Callbacks
        • Peripheral State, Mode and Error functions
      • I2C Exported Types
        • I2C Configuration Structure definition
        • HAL state structure definition
        • HAL mode structure definition
        • I2C Error Code definition
        • I2C handle Structure definition
      • I2C Exported Constants
        • I2C Sequential Transfer Options
        • I2C Addressing Mode
        • I2C Dual Addressing Mode
        • I2C Own Address2 Masks
        • I2C General Call Addressing Mode
        • I2C No-Stretch Mode
        • I2C Memory Address Size
        • I2C Transfer Direction Master Point of View
        • I2C Reload End Mode
        • I2C Start or Stop Mode
        • I2C Interrupt configuration definition
        • I2C Flag definition
      • I2C Exported Macros
      • I2C Private Constants
      • I2C Private Macros
    • I2CEx
      • I2C Extended Exported Functions
        • Extended features functions
          • I2C Extended Private Constants
          • I2C Extended Private Macros
          • I2C Extended Private Functions
      • I2C Extended Exported Constants
        • I2C Extended Analog Filter
        • I2C Extended Fast Mode Plus
    • IPCC
      • IPCC Private Constants
      • IPCC Private Functions
      • IPCC Exported Constants
        • IPCC Channel
      • IPCC Exported Types
      • IPCC Exported Macros
      • IPCC Exported Functions
        • Initialization and deinitialization functions
        • Communication functions
        • Peripheral State and Error functions
        • Peripheral IRQ Handler and Callbacks
    • IRDA
      • IRDA Private Constants
      • IRDA Private Macros
      • IRDA Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Error functions
      • IRDA Private Functions
      • IRDA Exported Types
      • IRDA Exported Constants
        • IRDA State Code Definition
        • IRDA Error Code Definition
        • IRDA Word Length
        • IRDA Parity
        • IRDA Transfer Mode
        • IRDA Low Power
        • Clock Prescaler
        • IRDA State
        • IRDA Mode
        • IRDA One Bit Sampling
        • IRDA DMA Tx
        • IRDA DMA Rx
        • IRDA Request Parameters
        • IRDA Flags
        • IRDA Interrupts Definition
        • IRDA Interruption Clear Flags
        • IRDA interruptions flags mask
      • IRDA Exported Macros
    • IRDAEx
      • IRDAEx Private Macros
    • IWDG
      • IWDG Private Defines
      • IWDG Exported Types
      • IWDG Exported Constants
        • IWDG Prescaler
        • IWDG Window option
      • IWDG Exported Macros
      • IWDG Exported Functions
        • Initialization and Start functions
        • IO operation functions
      • IWDG Private Constants
      • IWDG Private Macros
    • LCD
      • LCD Private Defines
      • LCD Exported Functions
        • Initialization/de-initialization methods
        • IO operation methods
        • Peripheral State methods
      • LCD Private Functions
      • LCD Exported Types
      • LCD Exported Constants
        • LCD Error Code
        • LCD Prescaler
        • LCD Divider
        • LCD Duty
        • LCD Bias
        • LCD Voltage Source
        • LCD Interrupts
        • LCD Pulse On Duration
        • LCD Dead Time
        • LCD Blink Mode
        • LCD Blink Frequency
        • LCD Contrast
        • LCD RAMRegister
        • LCD High Drive
        • LCD Mux Segment
        • LCD Flags Definition
      • LCD Exported Macros
      • LCD Private Macros
    • LPTIM
      • LPTIM Exported Functions
        • Initialization/de-initialization functions
        • LPTIM Start-Stop operation functions
        • LPTIM Read operation functions
        • LPTIM IRQ handler and callbacks
        • Peripheral State functions
      • LPTIM Private Functions
      • LPTIM Exported Types
      • LPTIM Exported Constants
        • LPTIM Clock Source
        • LPTIM Clock Prescaler
        • LPTIM Output Polarity
        • LPTIM Clock Sample Time
        • LPTIM Clock Polarity
        • LPTIM Trigger Source
        • LPTIM External Trigger Polarity
        • LPTIM Trigger Sample Time
        • LPTIM Updating Mode
        • LPTIM Counter Source
        • LPTIM Input1 Source
        • LPTIM Input2 Source
        • LPTIM Flags Definition
        • LPTIM Interrupts Definition
      • LPTIM Exported Macros
      • LPTIM Private Types
      • LPTIM Private Variables
      • LPTIM Private Constants
      • LPTIM Private Macros
    • PCD
      • PCD Private Macros
      • PCD Private Functions
      • PCD Exported Functions
        • Initialization and de-initialization functions
          • HAL USB OTG PCD Callback ID enumeration definition
          • HAL USB OTG PCD Callback pointer definition
        • Input and Output operation functions
        • Peripheral Control functions
        • Peripheral State functions
      • PCD Exported Types
      • PCD Exported Constants
        • PCD Speed
        • PCD PHY Module
        • PCD Error Code definition
      • PCD Exported Macros
      • PCD Private Constants
        • USB EXTI line interrupt
        • PCD EP0 MPS
        • PCD ENDP
        • PCD Endpoint Kind
    • PCDEx
      • PCDEx Exported Functions
        • Peripheral Control functions
    • PKA
      • PKA Private Define
      • PKA Private Functions
      • PKA Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Error functions
      • PKA Exported Types
        • HAL state structure definition
        • HAL callback ID enumeration
        • PKA Error Code definition
        • PKA handle Structure definition
        • PKA Callback pointer definition
        • PKA operation structure definition
      • PKA Exported Constants
        • PKA mode
        • PKA Interrupt configuration definition
        • PKA Flag definition
      • PKA Exported Macros
    • PWR
      • PWR Exported Types
      • PWR Exported Constants
        • Power Voltage Detector Level selection
        • PWR PVD interrupt and event mode
        • PWR Low Power Mode Selection
        • PWR regulator mode
        • PWR SLEEP mode entry
        • PWR STOP mode entry
      • PWR Private Defines
        • PWR Register Reset Values
        • PWR PVD external interrupt line
        • PWR PVD Mode Mask
        • PWR PVM external interrupts lines
        • PWR PVM Mode Mask
      • PWR Exported Macros
      • PWR Private Macros
      • PWR Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
    • PWREx
      • PWR Extended Private Defines
        • PWR Extended Flag Setting Time Out Value
      • PWR Extended Exported Types
      • PWR Extended Exported Constants
        • Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants
        • PWR wake-up pins
        • PWREx Pin Polarity configuration
        • Peripheral Voltage Monitoring type
        • PWR PVM interrupt and event mode
        • Flash Power Down modes
        • PWR Regulator voltage scale
        • PWR battery charging resistor selection
        • PWR battery charging
        • GPIO bit number for I/O setting in standby/shutdown mode
        • GPIO port
        • BOR configuration
        • SMPS step down converter operating modes
        • SMPS step down converter supply startup current selection
        • SMPS step down converter output voltage scaling voltage level
        • PWR Status Flags
        • PWR Wakeup Target Definition
        • PWREx Core definition
      • PWR Private Defines
        • PWR Register Reset Values
        • PWR PVD external interrupt line
        • PWR PVD Mode Mask
        • PWR PVM external interrupts lines
        • PWR PVM Mode Mask
      • PWR Extended Exported Macros
      • PWR Extended Exported Functions
        • Extended Peripheral Control functions
      • PWR Extended Private Macros
    • QSPI
      • QSPI Private Constants
      • QSPI Private Macros
      • QSPI Exported Functions
        • Initialization/de-initialization functions
        • Input and Output operation functions
        • Peripheral Control and State functions
      • QSPI Private Functions
      • QSPI Exported Types
      • QSPI Exported Constants
        • QSPI Error Code
        • QSPI Sample Shifting
        • QSPI ChipSelect High Time
        • QSPI Clock Mode
        • QSPI Address Size
        • QSPI Alternate Bytes Size
        • QSPI Instruction Mode
        • QSPI Address Mode
        • QSPI Alternate Bytes Mode
        • QSPI Data Mode
        • QSPI DDR Mode
        • QSPI Send Instruction Mode
        • QSPI Match Mode
        • QSPI Automatic Stop
        • QSPI Timeout Activation
        • QSPI Flags
        • QSPI Interrupts
        • QSPI Timeout definition
      • QSPI Exported Macros
    • RCC
      • RCC Private Constants
      • RCC Private Macros
      • RCC Private Variables
      • RCC Private Functions
      • RCC Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
      • RCC Exported Types
      • RCC Exported Constants
        • Timeout Values
        • Oscillator Type
        • HSE Config
        • LSE Config
        • HSI Config
        • LSI Config
        • MSI Config
        • HSI48 Config
        • PLL Config
        • PLLM Clock Divider
        • PLLP Clock Divider
        • PLLQ Clock Divider
        • PLLR Clock Divider
        • PLL Clock Source
        • PLL Clock Output
        • PLLSAI1 Clock Output
        • MSI Clock Range
        • System Clock Type
        • System Clock Source
        • System Clock Source Status
        • AHB Clock Source
        • APB1 Clock Source
        • RTC Clock Source
        • MCO Index
        • MCO1 Clock Source
        • MCO Clock Prescaler
        • HSE bias current factor
        • HSE current max limit
        • Interrupts
        • Flags
        • LSE Drive Configuration
        • Wake-Up from STOP Clock
      • RCC Exported Macros
        • AHB1 Peripheral Clock Enable Disable
        • AHB2 Peripheral Clock Enable Disable
        • AHB3 Peripheral Clock Enable Disable
        • APB1 Peripheral Clock Enable Disable
        • APB2 Peripheral Clock Enable Disable
        • AHB1 Peripheral Clock Enabled or Disabled Status
        • AHB2 Peripheral Clock Enabled or Disabled Status
        • AHB3 Peripheral Clock Enabled or Disabled Status
        • APB1 Peripheral Clock Enabled or Disabled Status
        • APB2 Peripheral Clock Enabled or Disabled Status
        • APB3 Peripheral Clock Enable Disable
        • APB3 Peripheral Clock Enabled or Disabled Status
        • AHB1 Peripheral Force Release Reset
        • AHB2 Peripheral Force Release Reset
        • AHB3 Peripheral Force Release Reset
        • APB1 Peripheral Force Release Reset
        • APB2 Peripheral Force Release Reset
        • APB3 Peripheral Force Release Reset
        • AHB1 Peripheral Clock Sleep Enable Disable
        • AHB2 Peripheral Clock Sleep Enable Disable
        • AHB3 Peripheral Clock Sleep Enable Disable
        • APB1 Peripheral Clock Sleep Enable Disable
        • APB2 Peripheral Clock Sleep Enable Disable
        • AHB1 Peripheral Clock Sleep Enabled or Disabled Status
        • AHB2 Peripheral Clock Sleep Enabled or Disabled Status
        • AHB3 Peripheral Clock Sleep Enabled or Disabled Status
        • APB1 Peripheral Clock Sleep Enabled or Disabled Status
        • APB2 Peripheral Clock Sleep Enabled or Disabled Status
        • APB3 Peripheral Clock Sleep Enable Disable
        • APB3 Peripheral Clock Sleep Enabled or Disabled Status
        • RCC Backup Domain Reset
        • RCC RTC Clock Configuration
        • Flags Interrupts Management
    • RCCEx
      • RCCEx Private Constants
      • RCCEx Private Functions
      • RCCEx Exported Functions
        • Extended Peripheral Control functions
        • Extended Clock management functions
        • Extended Clock Recovery System Control functions
      • RCCEx Exported Types
      • RCCEx Exported Constants
        • LSCO Index
        • Low Speed Clock Source
        • Periph Clock Selection
        • USART1 Clock Source
        • LPUART1 Clock Source
        • I2C1 Clock Source
        • I2C3 Clock Source
        • SAI1 Clock Source
        • LPTIM1 Clock Source
        • LPTIM2 Clock Source
        • RNG Clock Source
        • USB Clock Source
        • ADC Clock Source
        • HCLK RF Clock Source
        • RF WKP Clock Source
        • SMPS Clock Source
        • System Clock Source Status
        • SMPS Clock Division Factor
        • RCC LSE CSS external interrupt line
        • RCCEx CRS Status
        • RCCEx CRS SynchroSource
        • RCCEx CRS SynchroDivider
        • RCCEx CRS SynchroPolarity
        • RCCEx CRS ReloadValueDefault
        • RCCEx CRS ErrorLimitDefault
        • RCCEx CRS HSI48CalibrationDefault
        • RCCEx CRS FreqErrorDirection
        • RCCEx CRS Interrupt Sources
        • RCCEx CRS Flags
      • RCCEx Exported Macros
        • Flags Interrupts Management
        • RCCEx CRS Extended Features
      • RCC Private Constants
      • RCCEx_Private_Macros
    • RNG
      • RNG Private Constants
      • RNG Exported Types
        • RNG Init Structure definition
        • RNG State Structure definition
        • RNG Handle Structure definition
      • RNG Exported Constants
        • RNG Interrupt definition
        • RNG Flag definition
        • RNG Clock Error Detection
        • RNG Error Definition
      • RNG Exported Macros
      • RNG Exported Functions
        • Initialization and configuration functions
        • Peripheral Control functions
        • Peripheral State functions
      • RNG Private Macros
    • RTC
      • RTC Exported Types
      • RTC Exported Constants
        • RTC Hour Formats
        • RTC Output Polarity Definitions
        • RTC Output Type ALARM OUT
        • RTC Output ALARM OUT Remap
        • RTC AM PM Definitions
        • RTC DayLightSaving Definitions
        • RTC StoreOperation Definitions
        • RTC Input Parameter Format Definitions
        • RTC Month Date Definitions
        • RTC WeekDay Definitions
        • RTC AlarmDateWeekDay Definitions
        • RTC AlarmMask Definitions
        • RTC Alarms Definitions
        • RTC Alarm Sub Seconds Masks Definitions
        • RTC Interrupts Definitions
        • RTC Flags Definitions
      • RTC Exported Macros
      • RTC Exported Functions
        • Initialization and de-initialization functions
        • RTC Time and Date functions
        • RTC Alarm functions
        • Peripheral Control functions
        • Peripheral State functions
      • RTC Private Constants
      • RTC Private Macros
        • RTC Private macros to check input parameters
      • RTC Private Functions
    • RTCEx
      • RTCEx Private Constants
      • RTCEx Exported Types
      • RTCEx Exported Constants
        • RTCEx Output Selection Definition
        • RTCEx Backup Registers Definition
        • RTCEx Time Stamp Edges definition
        • RTCEx TimeStamp Pin Selection
        • RTCEx Tamper Pins Definition
        • RTCEx Tamper Interrupt Definitions
        • RTCEx Tamper Trigger Definitions
        • RTCEx Tamper EraseBackUp Definitions
        • RTCEx Tamper MaskFlag Definitions
        • RTCEx Tamper Filter Definitions
        • RTCEx Tamper Sampling Frequencies Definitions
        • RTCEx Tamper Pin Precharge Duration Definitions
        • RTCEx Tamper TimeStampOnTamperDetection Definitions
        • RTCEx Tamper Pull UP Definitions
        • RTCEx Wakeup Timer Definitions
        • RTCEx Smooth calib period Definitions
        • RTCEx Smooth calib Plus pulses Definitions
        • RTCEx Calib Output selection Definitions
        • RTCEx Add 1 Second Parameter Definitions
        • RTCEx Interrupts Definitions
        • RTCEx Flags Definitions
      • RTCEx Exported Macros
        • RTC WakeUp Timer
        • RTC Timestamp
        • RTC Tamper
        • EXTI RTC Tamper Timestamp EXTI
        • RTC Calibration
      • RTCEx Exported Functions
        • Extended RTC TimeStamp and Tamper functions
        • Extended RTC Wake-up functions
        • Extended Peripheral Control functions
        • Extended features functions
      • RTCEx Private Macros
        • Private macros to check input parameters
          • RTCEx Smooth calib Minus pulses Definitions
          • RTCEx Substract Fraction Of Second Value
    • SAI
      • SAI Private Typedefs
      • SAI Private Constants
      • SAI Private Functions
      • SAI Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State functions
      • SAI Exported Types
        • SAI PDM Structure definition
        • SAI Init Structure definition
        • SAI Frame Structure definition
        • SAI Slot Structure definition
        • SAI Handle Structure definition
      • SAI Exported Constants
        • SAI Error Code
        • SAI External synchronisation
        • SAI Block Master Clock Output
        • SAI Supported protocol
        • SAI protocol data size
        • SAI Audio Frequency
        • SAI Block Master Clock OverSampling
        • SAI PDM Clock Enable
        • SAI Block Mode
        • SAI Block Protocol
        • SAI Block Data Size
        • SAI Block MSB LSB transmission
        • SAI Block Clock Strobing
        • SAI Block Synchronization
        • SAI Block Output Drive
        • SAI Block NoDivider
        • SAI Block FS Definition
        • SAI Block FS Polarity
        • SAI Block FS Offset
        • SAI Block Slot Size
        • SAI Block Slot Active
        • SAI Mono Stereo Mode
        • SAI TRIState Management
        • SAI Block Fifo Threshold
        • SAI Block Companding Mode
        • SAI Block Mute Value
        • SAI Block Interrupts Definition
        • SAI Block Flags Definition
        • SAI Block Fifo Status Level
      • SAI Exported Macros
      • SAI Private Macros
    • SAIEx
      • SAIEx Extended Private Defines
      • SAIEx Extended Exported Functions
        • Peripheral Control functions
      • SAIEx Exported Types
      • SAIEx Extended Private Macros
    • SMARTCARD
      • SMARTCARD Private Constants
      • SMARTCARD Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Errors functions
      • SMARTCARD Private Functions
      • SMARTCARD Exported Types
      • SMARTCARD Exported Constants
        • SMARTCARD State Code Definition
        • SMARTCARD Error Code Definition
        • SMARTCARD Word Length
        • SMARTCARD Number of Stop Bits
        • SMARTCARD Parity
        • SMARTCARD Transfer Mode
        • SMARTCARD Clock Polarity
        • SMARTCARD Clock Phase
        • SMARTCARD Last Bit
        • SMARTCARD One Bit Sampling Method
        • SMARTCARD NACK Enable
        • SMARTCARD Timeout Enable
        • Clock Prescaler
        • SMARTCARD advanced feature TX pin active level inversion
        • SMARTCARD advanced feature RX pin active level inversion
        • SMARTCARD advanced feature Binary Data inversion
        • SMARTCARD advanced feature RX TX pins swap
        • SMARTCARD advanced feature Overrun Disable
        • SMARTCARD advanced feature DMA Disable on Rx Error
        • SMARTCARD advanced feature MSB first
        • SMARTCARD Request Parameters
        • SMARTCARD interruptions flags mask
      • SMARTCARD Exported Macros
      • SMARTCARD Private Macros
    • SMARTCARDEx
      • SMARTCARD Extended Exported Functions
        • Extended Peripheral Control functions
        • Extended Peripheral IO operation functions
        • Extended Peripheral Peripheral Control functions
        • SMARTCARDEx_Exported_Functions_Group3
      • SMARTCARD Extended private Functions
      • SMARTCARD Extended Private Macros
      • SMARTCARD Extended Exported Constants
        • SMARTCARD Transmission Completion Indication
        • SMARTCARD advanced feature initialization type
        • SMARTCARDEx FIFO mode
        • SMARTCARDEx TXFIFO threshold level
        • SMARTCARDEx RXFIFO threshold level
        • SMARTCARD Flags
        • SMARTCARD Interrupts Definition
        • SMARTCARD Interruption Clear Flags
    • SMBUS
      • SMBUS Private Constants
      • SMBUS Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
          • Blocking mode Polling
          • Non-Blocking mode Interrupt
          • IRQ Handler and Callbacks
          • Peripheral State and Errors functions
        • IRQ Handler and Callbacks
        • Peripheral State and Errors functions
        • SMBUS Private Functions
      • SMBUS Exported Types
        • SMBUS Configuration Structure definition
        • HAL state definition
        • SMBUS Error Code definition
        • SMBUS handle Structure definition
      • SMBUS Exported Constants
        • SMBUS Analog Filter
        • SMBUS addressing mode
        • SMBUS dual addressing mode
        • SMBUS ownaddress2 masks
        • SMBUS general call addressing mode
        • SMBUS nostretch mode
        • SMBUS packet error check mode
        • SMBUS peripheral mode
        • SMBUS ReloadEndMode definition
        • SMBUS StartStopMode definition
        • SMBUS XferOptions definition
        • SMBUS Interrupt configuration definition
        • SMBUS Flag definition
      • SMBUS Exported Macros
      • SMBUS Private Macros
      • SMBUS Private Functions
    • SPI
      • SPI Private Constants
      • SPI Private Functions
      • SPI Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Errors functions
      • SPI Exported Types
      • SPI Exported Constants
        • SPI Error Code
        • SPI Mode
        • SPI Direction Mode
        • SPI Data Size
        • SPI Clock Polarity
        • SPI Clock Phase
        • SPI Slave Select Management
        • SPI NSS Pulse Mode
        • SPI BaudRate Prescaler
        • SPI MSB LSB Transmission
        • SPI TI Mode
        • SPI CRC Calculation
        • SPI CRC Length
        • SPI FIFO Reception Threshold
        • SPI Interrupt Definition
        • SPI Flags Definition
        • SPI Transmission FIFO Status Level
        • SPI Reception FIFO Status Level
      • SPI Exported Macros
      • SPI Private Macros
    • SPIEx
      • SPIEx Private Constants
      • SPIEx Exported Functions
        • IO operation functions
    • TIM
      • TIM Exported Functions
        • TIM Time Base functions
        • TIM Output Compare functions
        • TIM PWM functions
        • TIM Input Capture functions
        • TIM One Pulse functions
        • TIM Encoder functions
        • TIM IRQ handler management
        • TIM Peripheral Control functions
        • TIM Callbacks functions
        • TIM Peripheral State functions
      • TIM Private Functions
      • TIM Exported Types
      • TIM Exported Constants
        • TIM Clear Input Source
        • TIM DMA Base Address
        • TIM Event Source
        • TIM Input Channel polarity
        • TIM ETR Polarity
        • TIM ETR Prescaler
        • TIM Counter Mode
        • TIM Clock Division
        • TIM Output Compare State
        • TIM Auto-Reload Preload
        • TIM Output Fast State
        • TIM Complementary Output Compare State
        • TIM Output Compare Polarity
        • TIM Complementary Output Compare Polarity
        • TIM Output Compare Idle State
        • TIM Complementary Output Compare Idle State
        • TIM Input Capture Polarity
        • TIM Encoder Input Polarity
        • TIM Input Capture Selection
        • TIM Input Capture Prescaler
        • TIM One Pulse Mode
        • TIM Encoder Mode
        • TIM interrupt Definition
        • TIM Commutation Source
        • TIM DMA Sources
        • TIM Flag Definition
        • TIM Channel
        • TIM Clock Source
        • TIM Clock Polarity
        • TIM Clock Prescaler
        • TIM Clear Input Polarity
        • TIM Clear Input Prescaler
        • TIM OSSR OffState Selection for Run mode state
        • TIM OSSI OffState Selection for Idle mode state
        • TIM Lock level
        • TIM Break Input Enable
        • TIM Break Input Polarity
        • TIM Break input 2 Enable
        • TIM Break Input 2 Polarity
        • TIM Automatic Output Enable
        • Group Channel 5 and Channel 1, 2 or 3
        • TIM Master Mode Selection
        • TIM Master Mode Selection 2 (TRGO2)
        • TIM Master/Slave Mode
        • TIM Slave mode
        • TIM Output Compare and PWM Modes
        • TIM Trigger Selection
        • TIM Trigger Polarity
        • TIM Trigger Prescaler
        • TIM TI1 Input Selection
        • TIM DMA Burst Length
        • TIM DMA Handle Index
        • TIM Capture/Compare Channel State
        • TIM Break System
      • TIM Exported Macros
      • TIM Private Constants
      • TIM Private Macros
    • TIMEx
      • TIM Extended Exported Functions
        • Extended Timer Hall Sensor functions
        • Extended Timer Complementary Output Compare functions
        • Extended Timer Complementary PWM functions
        • Extended Timer Complementary One Pulse functions
        • Extended Peripheral Control functions
        • Extended Callbacks functions
        • Extended Peripheral State functions
      • TIMEx Private Functions
      • TIM Extended Exported Types
      • TIM Extended Exported Constants
        • TIM Extended Remapping
        • TIM Extended Break input
        • TIM Extended Break input source
        • TIM Extended Break input source enabling
        • TIM Extended Break input polarity
      • TIM Extended Exported Macros
      • TIM Extended Private Macros
    • TSC
      • TSC Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • Peripheral Control functions
        • Peripheral State and Errors functions
        • IRQ Handler and Callbacks
      • TSC Private Functions
      • TSC Exported Types
      • TSC Exported Constants
        • TSC Error Code definition
        • CTPulse High Length
        • CTPulse Low Length
        • Spread Spectrum Prescaler
        • Pulse Generator Prescaler
        • Max Count Value
        • IO Default Mode
        • Synchro Pin Polarity
        • Acquisition Mode
        • Interrupts definition
        • Flags definition
        • Group definition
      • TSC Exported Macros
      • TSC Private Macros
    • UART
      • UART Private Constants
      • UART Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral Control functions
        • Peripheral State and Error functions
      • UART Private Functions
      • UART Exported Types
      • UART Exported Constants
        • UART State Code Definition
        • UART Error Definition
        • UART Number of Stop Bits
        • UART Parity
        • UART Hardware Flow Control
        • UART Transfer Mode
        • UART State
        • UART Over Sampling
        • UART One Bit Sampling Method
        • UART Clock Prescaler
        • UART Advanced Feature AutoBaud Rate Mode
        • UART Receiver Timeout
        • UART Local Interconnection Network mode
        • UART LIN Break Detection
        • UART DMA Tx
        • UART DMA Rx
        • UART Half Duplex Selection
        • UART WakeUp Methods
        • UART Request Parameters
        • UART Advanced Feature Initialization Type
        • UART Advanced Feature TX Pin Active Level Inversion
        • UART Advanced Feature RX Pin Active Level Inversion
        • UART Advanced Feature Binary Data Inversion
        • UART Advanced Feature RX TX Pins Swap
        • UART Advanced Feature Overrun Disable
        • UART Advanced Feature Auto BaudRate Enable
        • UART Advanced Feature DMA Disable On Rx Error
        • UART Advanced Feature MSB First
        • UART Advanced Feature Stop Mode Enable
        • UART Advanced Feature Mute Mode Enable
        • UART Address-matching LSB Position In CR2 Register
        • UART WakeUp From Stop Selection
        • UART DriverEnable Polarity
        • UART Driver Enable Assertion Time LSB Position In CR1 Register
        • UART Driver Enable DeAssertion Time LSB Position In CR1 Register
        • UART Interruptions Flag Mask
        • UART polling-based communications time-out value
        • UART Status Flags
        • UART Interrupts Definition
        • UART Interruption Clear Flags
      • UART Exported Macros
      • UART Private Macros
    • UARTEx
      • UARTEx Private Constants
      • UARTEx Private Functions
      • UARTEx Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral Control functions
      • UARTEx Exported Types
      • UARTEx Exported Constants
        • UARTEx Word Length
        • UARTEx WakeUp Address Length
        • UARTEx FIFO mode
        • UARTEx TXFIFO threshold level
        • UARTEx RXFIFO threshold level
      • UARTEx Private Macros
    • USART
      • USART Private Constants
      • USART Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Error functions
      • USART Private Functions
      • USART Exported Types
      • USART Exported Constants
        • USART Error Definition
        • USART Number of Stop Bits
        • USART Parity
        • USART Mode
        • USART Over Sampling
        • USART Clock
        • USART Clock Polarity
        • USART Clock Phase
        • USART Last Bit
        • USART Clock Prescaler
        • USART Request Parameters
        • USART Flags
        • USART Interrupts Definition
        • USART Interruption Clear Flags
        • USART Interruption Flags Mask
      • USART Exported Macros
      • USART Private Macros
    • USARTEx
      • USARTEx Private Functions
      • USARTEx Exported Functions
        • IO operation functions
        • Peripheral Control functions
      • USARTEx Exported Constants
        • USARTEx Word Length
        • USARTEx Slave Select Management
        • USARTEx Synchronous Slave mode enable
        • USARTEx FIFO mode
        • USARTEx TXFIFO threshold level
        • USARTEx RXFIFO threshold level
      • USARTEx Private Macros
    • WWDG
      • WWDG Exported Functions
        • Initialization and Configuration functions
        • IO operation functions
      • WWDG Exported Types
      • WWDG Exported Constants
        • WWDG Interrupt definition
        • WWDG Flag definition
        • WWDG Prescaler
        • WWDG Early Wakeup Interrupt Mode
      • WWDG Private Macros
      • WWDG Exported Macros
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STM32WB55xx HAL User Manual: PKA_rmtollPages.txt File Reference

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STM32WB55xx HAL User Manual: RCC_rmtollPages.txt File Reference

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STM32WB55xx HAL User Manual: RTC_rmtollPages.txt File Reference

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STM32WB55xx HAL User Manual: stm32wbxx_hal.c Source File

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stm32wbxx_hal.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal.c
00004   * @author  MCD Application Team
00005   * @brief   HAL module driver.
00006   *          This is the common part of the HAL initialization
00007   *
00008   @verbatim
00009   ==============================================================================
00010                      ##### How to use this driver #####
00011   ==============================================================================
00012     [..]
00013     The common HAL driver contains a set of generic and common APIs that can be
00014     used by the PPP peripheral drivers and the user to start using the HAL.
00015     [..]
00016     The HAL contains two APIs' categories:
00017          (+) Common HAL APIs
00018          (+) Services HAL APIs
00019
00020   @endverbatim
00021   ******************************************************************************
00022   * @attention
00023   *
00024   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00025   * All rights reserved.</center></h2>
00026   *
00027   * This software component is licensed by ST under BSD 3-Clause license,
00028   * the "License"; You may not use this file except in compliance with the
00029   * License. You may obtain a copy of the License at:
00030   *                        opensource.org/licenses/BSD-3-Clause
00031   *
00032   ******************************************************************************
00033   */
00034
00035 /* Includes ------------------------------------------------------------------*/
00036 #include "stm32wbxx_hal.h"
00037
00038 /** @addtogroup STM32WBxx_HAL_Driver
00039   * @{
00040   */
00041
00042 /** @addtogroup HAL
00043   * @brief HAL module driver
00044   * @{
00045   */
00046
00047 #ifdef HAL_MODULE_ENABLED
00048
00049 /* Private typedef -----------------------------------------------------------*/
00050 /* Private define ------------------------------------------------------------*/
00051
00052 /** @defgroup HAL_Private_Constants HAL Private Constants
00053   * @{
00054   */
00055 /**
00056  * @brief STM32WBxx HAL Driver version number
00057    */
00058 #define __STM32WBxx_HAL_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
00059 #define __STM32WBxx_HAL_VERSION_SUB1   (0x03U) /*!< [23:16] sub1 version */
00060 #define __STM32WBxx_HAL_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
00061 #define __STM32WBxx_HAL_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
00062 #define __STM32WBxx_HAL_VERSION         ((__STM32WBxx_HAL_VERSION_MAIN << 24U)\
00063                                         |(__STM32WBxx_HAL_VERSION_SUB1 << 16U)\
00064                                         |(__STM32WBxx_HAL_VERSION_SUB2 << 8U )\
00065                                         |(__STM32WBxx_HAL_VERSION_RC))
00066
00067 #if defined(VREFBUF)
00068 #define VREFBUF_TIMEOUT_VALUE     10U   /* 10 ms */
00069 #endif
00070
00071 /**
00072   * @}
00073   */
00074
00075 /* Private macro -------------------------------------------------------------*/
00076 /* Exported variables ---------------------------------------------------------*/
00077 /** @defgroup HAL_Exported_Variables HAL Exported Variables
00078   * @{
00079   */
00080 __IO uint32_t uwTick;
00081 uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
00082 uint32_t uwTickFreq = HAL_TICK_FREQ_DEFAULT;  /* 1KHz */
00083 /**
00084   * @}
00085   */
00086
00087 /* Private function prototypes -----------------------------------------------*/
00088 /* Exported functions --------------------------------------------------------*/
00089
00090 /** @addtogroup HAL_Exported_Functions
00091   * @{
00092   */
00093
00094 /** @addtogroup HAL_Exported_Functions_Group1
00095  *  @brief    HAL Initialization and Configuration functions
00096  *
00097 @verbatim
00098  ===============================================================================
00099            ##### HAL Initialization and Configuration functions #####
00100  ===============================================================================
00101     [..]  This section provides functions allowing to:
00102       (+) Initialize the Flash interface the NVIC allocation and initial time base
00103           clock configuration.
00104       (+) De-initialize common part of the HAL.
00105       (+) Configure the time base source to have 1ms time base with a dedicated
00106           Tick interrupt priority.
00107         (++) SysTick timer is used by default as source of time base, but user
00108              can eventually implement his proper time base source (a general purpose
00109              timer for example or other time source), keeping in mind that Time base
00110              duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
00111              handled in milliseconds basis.
00112         (++) Time base configuration function (HAL_InitTick ()) is called automatically
00113              at the beginning of the program after reset by HAL_Init() or at any time
00114              when clock is configured, by HAL_RCC_ClockConfig().
00115         (++) Source of time base is configured  to generate interrupts at regular
00116              time intervals. Care must be taken if HAL_Delay() is called from a
00117              peripheral ISR process, the Tick interrupt line must have higher priority
00118             (numerically lower) than the peripheral interrupt. Otherwise the caller
00119             ISR process will be blocked.
00120        (++) functions affecting time base configurations are declared as __weak
00121              to make  override possible  in case of other  implementations in user file.
00122 @endverbatim
00123   * @{
00124   */
00125
00126 /**
00127   * @brief  This function is used to initialize the HAL Library; it must be the first
00128   *         instruction to be executed in the main program (before to call any other
00129   *         HAL function), it performs the following:
00130   *           Configure the Flash prefetch, instruction and Data caches.
00131   *           Configures the SysTick to generate an interrupt each 1 millisecond,
00132   *           which is clocked by the MSI (at this stage, the clock is not yet
00133   *           configured and thus the system is running from the internal MSI at 4 MHz).
00134   *           Set NVIC Group Priority to 4.
00135   *           Calls the HAL_MspInit() callback function defined in user file
00136   *           "stm32wbxx_hal_msp.c" to do the global low level hardware initialization
00137   *
00138   * @note   SysTick is used as time base for the HAL_Delay() function, the application
00139   *         need to ensure that the SysTick time base is always set to 1 millisecond
00140   *         to have correct HAL operation.
00141   * @retval HAL status
00142   */
00143 HAL_StatusTypeDef HAL_Init(void)
00144 {
00145   HAL_StatusTypeDef  status = HAL_OK;
00146   /* Configure Flash prefetch, Instruction cache, Data cache */
00147   /* Default configuration at reset is:                      */
00148   /* - Prefetch disabled                                     */
00149   /* - Instruction cache enabled                             */
00150   /* - Data cache enabled                                    */
00151 #if (INSTRUCTION_CACHE_ENABLE == 0U)
00152    __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
00153 #endif /* INSTRUCTION_CACHE_ENABLE */
00154
00155 #if (DATA_CACHE_ENABLE == 0U)
00156    __HAL_FLASH_DATA_CACHE_DISABLE();
00157 #endif /* DATA_CACHE_ENABLE */
00158
00159 #if (PREFETCH_ENABLE != 0U)
00160   __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
00161 #endif /* PREFETCH_ENABLE */
00162
00163   /* Set Interrupt Group Priority */
00164   HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
00165
00166   /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
00167   if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
00168   {
00169     status = HAL_ERROR;
00170   }
00171   else
00172   {
00173     /* Init the low level hardware */
00174     HAL_MspInit();
00175   }
00176
00177   /* Return function status */
00178   return status;
00179 }
00180
00181 /**
00182   * @brief  This function de-Initializes common part of the HAL and stops the source of time base.
00183   * @note   This function is optional.
00184   * @retval HAL status
00185   */
00186 HAL_StatusTypeDef HAL_DeInit(void)
00187 {
00188   /* Reset of all peripherals */
00189   __HAL_RCC_APB1_FORCE_RESET();
00190   __HAL_RCC_APB1_RELEASE_RESET();
00191
00192   __HAL_RCC_APB2_FORCE_RESET();
00193   __HAL_RCC_APB2_RELEASE_RESET();
00194
00195   __HAL_RCC_APB3_FORCE_RESET();
00196   __HAL_RCC_APB3_RELEASE_RESET();
00197
00198   __HAL_RCC_AHB1_FORCE_RESET();
00199   __HAL_RCC_AHB1_RELEASE_RESET();
00200
00201   __HAL_RCC_AHB2_FORCE_RESET();
00202   __HAL_RCC_AHB2_RELEASE_RESET();
00203
00204   __HAL_RCC_AHB3_FORCE_RESET();
00205   __HAL_RCC_AHB3_RELEASE_RESET();
00206
00207   /* De-Init the low level hardware */
00208   HAL_MspDeInit();
00209
00210   /* Return function status */
00211   return HAL_OK;
00212 }
00213
00214 /**
00215   * @brief  Initialize the MSP.
00216   * @retval None
00217   */
00218 __weak void HAL_MspInit(void)
00219 {
00220   /* NOTE : This function should not be modified, when the callback is needed,
00221             the HAL_MspInit could be implemented in the user file
00222    */
00223 }
00224
00225 /**
00226   * @brief  DeInitializes the MSP.
00227   * @retval None
00228   */
00229 __weak void HAL_MspDeInit(void)
00230 {
00231   /* NOTE : This function should not be modified, when the callback is needed,
00232             the HAL_MspDeInit could be implemented in the user file
00233    */
00234 }
00235
00236 /**
00237   * @brief This function configures the source of the time base:
00238   *        The time source is configured  to have 1ms time base with a dedicated
00239   *        Tick interrupt priority.
00240   * @note This function is called  automatically at the beginning of program after
00241   *       reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().
00242   * @note In the default implementation, SysTick timer is the source of time base.
00243   *       It is used to generate interrupts at regular time intervals.
00244   *       Care must be taken if HAL_Delay() is called from a peripheral ISR process,
00245   *       The SysTick interrupt must have higher priority (numerically lower)
00246   *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
00247   *       The function is declared as __weak  to be overwritten  in case of other
00248   *       implementation  in user file.
00249   * @param TickPriority Tick interrupt priority.
00250   * @retval HAL status
00251   */
00252 __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
00253 {
00254   HAL_StatusTypeDef  status = HAL_OK;
00255
00256   if (uwTickFreq != 0U)
00257   {
00258     /*Configure the SysTick to have interrupt in 1ms time basis*/
00259     if (HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/ (1000U /uwTickFreq)) == 0U)
00260     {
00261       /* Configure the SysTick IRQ priority */
00262       if (TickPriority < (1UL << __NVIC_PRIO_BITS))
00263       {
00264         HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
00265         uwTickPrio = TickPriority;
00266       }
00267       else
00268       {
00269         status = HAL_ERROR;
00270       }
00271     }
00272     else
00273     {
00274       status = HAL_ERROR;
00275     }
00276   }
00277   else
00278   {
00279     status = HAL_ERROR;
00280   }
00281
00282   /* Return function status */
00283   return status;
00284 }
00285
00286 /**
00287   * @}
00288   */
00289
00290 /** @addtogroup HAL_Exported_Functions_Group2
00291  *  @brief    HAL Control functions
00292  *
00293 @verbatim
00294  ===============================================================================
00295                       ##### HAL Control functions #####
00296  ===============================================================================
00297     [..]  This section provides functions allowing to:
00298       (+) Provide a tick value in millisecond
00299       (+) Provide a blocking delay in millisecond
00300       (+) Suspend the time base source interrupt
00301       (+) Resume the time base source interrupt
00302       (+) Get the HAL API driver version
00303       (+) Get the device revision identifier
00304       (+) Get the device identifier
00305       (+) Get the unique device identifier
00306
00307 @endverbatim
00308   * @{
00309   */
00310
00311 /**
00312   * @brief This function is called to increment  a global variable "uwTick"
00313   *        used as application time base.
00314   * @note In the default implementation, this variable is incremented each 1ms
00315   *       in SysTick ISR.
00316  * @note This function is declared as __weak to be overwritten in case of other
00317   *      implementations in user file.
00318   * @retval None
00319   */
00320 __weak void HAL_IncTick(void)
00321 {
00322   uwTick += (uint32_t)uwTickFreq;
00323 }
00324
00325 /**
00326   * @brief Provides a tick value in millisecond.
00327   * @note This function is declared as __weak to be overwritten in case of other
00328   *       implementations in user file.
00329   * @retval tick value
00330   */
00331 __weak uint32_t HAL_GetTick(void)
00332 {
00333   return uwTick;
00334 }
00335
00336 /**
00337   * @brief This function returns a tick priority.
00338   * @retval tick priority
00339   */
00340 uint32_t HAL_GetTickPrio(void)
00341 {
00342   return uwTickPrio;
00343 }
00344
00345 /**
00346   * @brief Set new tick Freq.
00347   * @retval Status
00348   */
00349 HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq)
00350 {
00351   HAL_StatusTypeDef status  = HAL_OK;
00352   assert_param(IS_TICKFREQ(Freq));
00353
00354   if (uwTickFreq != Freq)
00355   {
00356     uwTickFreq = Freq;
00357
00358     /* Apply the new tick Freq  */
00359     status = HAL_InitTick(uwTickPrio);
00360   }
00361
00362   return status;
00363 }
00364
00365 /**
00366   * @brief Return tick frequency.
00367   * @retval tick period in Hz
00368   */
00369 uint32_t HAL_GetTickFreq(void)
00370 {
00371   return uwTickFreq;
00372 }
00373
00374 /**
00375   * @brief This function provides minimum delay (in milliseconds) based
00376   *        on variable incremented.
00377   * @note In the default implementation , SysTick timer is the source of time base.
00378   *       It is used to generate interrupts at regular time intervals where uwTick
00379   *       is incremented.
00380   * @note This function is declared as __weak to be overwritten in case of other
00381   *       implementations in user file.
00382   * @param Delay  specifies the delay time length, in milliseconds.
00383   * @retval None
00384   */
00385   __weak void HAL_Delay(uint32_t Delay)
00386   {
00387     uint32_t tickstart = HAL_GetTick();
00388     uint32_t wait = Delay;
00389
00390     /* Add a freq to guarantee minimum wait */
00391     if (wait < HAL_MAX_DELAY)
00392     {
00393       wait += (uint32_t)(uwTickFreq);
00394     }
00395
00396     while ((HAL_GetTick() - tickstart) < wait)
00397     {
00398     }
00399   }
00400
00401
00402 /**
00403   * @brief Suspend Tick increment.
00404   * @note In the default implementation , SysTick timer is the source of time base. It is
00405   *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
00406   *       is called, the SysTick interrupt will be disabled and so Tick increment
00407   *       is suspended.
00408   * @note This function is declared as __weak to be overwritten in case of other
00409   *       implementations in user file.
00410   * @retval None
00411   */
00412 __weak void HAL_SuspendTick(void)
00413 {
00414   /* Disable SysTick Interrupt */
00415   CLEAR_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk);
00416 }
00417
00418 /**
00419   * @brief Resume Tick increment.
00420   * @note In the default implementation , SysTick timer is the source of time base. It is
00421   *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
00422   *       is called, the SysTick interrupt will be enabled and so Tick increment
00423   *       is resumed.
00424   * @note This function is declared as __weak to be overwritten in case of other
00425   *       implementations in user file.
00426   * @retval None
00427   */
00428 __weak void HAL_ResumeTick(void)
00429 {
00430   /* Enable SysTick Interrupt */
00431   SET_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk);
00432 }
00433
00434 /**
00435   * @brief  Returns the HAL revision
00436   * @retval version : 0xXYZR (8bits for each decimal, R for RC)
00437   */
00438 uint32_t HAL_GetHalVersion(void)
00439 {
00440  return __STM32WBxx_HAL_VERSION;
00441 }
00442
00443 /**
00444   * @brief  Returns the device revision identifier.
00445   * @retval Device revision identifier
00446   */
00447 uint32_t HAL_GetREVID(void)
00448 {
00449    return(LL_DBGMCU_GetRevisionID());
00450 }
00451
00452 /**
00453   * @brief  Returns the device identifier.
00454   * @retval Device identifier
00455   */
00456 uint32_t HAL_GetDEVID(void)
00457 {
00458    return(LL_DBGMCU_GetDeviceID());
00459 }
00460
00461 /**
00462   * @brief  Return the first word of the unique device identifier (UID based on 96 bits)
00463   * @retval Device identifier
00464   */
00465 uint32_t HAL_GetUIDw0(void)
00466 {
00467   return(READ_REG(*((uint32_t *)UID_BASE)));
00468 }
00469
00470 /**
00471   * @brief  Return the second word of the unique device identifier (UID based on 96 bits)
00472   * @retval Device identifier
00473   */
00474 uint32_t HAL_GetUIDw1(void)
00475 {
00476   return(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
00477 }
00478
00479 /**
00480   * @brief  Return the third word of the unique device identifier (UID based on 96 bits)
00481   * @retval Device identifier
00482   */
00483 uint32_t HAL_GetUIDw2(void)
00484 {
00485   return(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
00486 }
00487
00488 /**
00489   * @}
00490   */
00491
00492 /** @addtogroup HAL_Exported_Functions_Group3
00493  *  @brief    HAL Debug functions
00494  *
00495 @verbatim
00496  ===============================================================================
00497                       ##### HAL Debug functions #####
00498  ===============================================================================
00499     [..]  This section provides functions allowing to:
00500       (+) Enable/Disable Debug module during SLEEP mode
00501       (+) Enable/Disable Debug module during STOP mode
00502       (+) Enable/Disable Debug module during STANDBY mode
00503
00504 @endverbatim
00505   * @{
00506   */
00507
00508 /**
00509   * @brief  Enable the Debug Module during SLEEP mode
00510   * @retval None
00511   */
00512 void HAL_DBGMCU_EnableDBGSleepMode(void)
00513 {
00514   LL_DBGMCU_EnableDBGSleepMode();
00515 }
00516
00517 /**
00518   * @brief  Disable the Debug Module during SLEEP mode
00519   * @retval None
00520   */
00521 void HAL_DBGMCU_DisableDBGSleepMode(void)
00522 {
00523   LL_DBGMCU_DisableDBGSleepMode();
00524 }
00525
00526 /**
00527   * @brief  Enable the Debug Module during STOP mode
00528   * @retval None
00529   */
00530 void HAL_DBGMCU_EnableDBGStopMode(void)
00531 {
00532   LL_DBGMCU_EnableDBGStopMode();
00533 }
00534
00535 /**
00536   * @brief  Disable the Debug Module during STOP mode
00537   * @retval None
00538   */
00539 void HAL_DBGMCU_DisableDBGStopMode(void)
00540 {
00541   LL_DBGMCU_DisableDBGStopMode();
00542 }
00543
00544 /**
00545   * @brief  Enable the Debug Module during STANDBY mode
00546   * @retval None
00547   */
00548 void HAL_DBGMCU_EnableDBGStandbyMode(void)
00549 {
00550   LL_DBGMCU_EnableDBGStandbyMode();
00551 }
00552
00553 /**
00554   * @brief  Disable the Debug Module during STANDBY mode
00555   * @retval None
00556   */
00557 void HAL_DBGMCU_DisableDBGStandbyMode(void)
00558 {
00559   LL_DBGMCU_DisableDBGStandbyMode();
00560 }
00561
00562 /**
00563   * @}
00564   */
00565
00566 /** @defgroup HAL_Exported_Functions_Group4 HAL System Configuration functions
00567  *  @brief    HAL System Configuration functions
00568  *
00569 @verbatim
00570  ===============================================================================
00571                  ##### HAL system configuration functions #####
00572  ===============================================================================
00573     [..]  This section provides functions allowing to:
00574       (+) Start a hardware SRAM2 erase operation
00575       (+) Disable CPU2 SRAM fetch (execution)
00576       (+) Configure the Voltage reference buffer
00577       (+) Enable/Disable the Voltage reference buffer
00578       (+) Enable/Disable the I/O analog switch voltage booster
00579       (+) Enable/Disable the access for security IP (AES1, AES2, PKA, RNG)
00580       (+) Enable/Disable the access for security IP (AES2, PKA, RNG)
00581
00582 @endverbatim
00583   * @{
00584   */
00585
00586 /**
00587   * @brief  Start a hardware SRAM2 erase operation.
00588   * @note   As long as SRAM2 is not erased the SRAM2ER bit will be set.
00589   *         This bit is automatically reset at the end of the SRAM2 erase operation.
00590   * @retval None
00591   */
00592 void HAL_SYSCFG_SRAM2Erase(void)
00593 {
00594   /* unlock the write protection of the SRAM2ER bit */
00595   __HAL_SYSCFG_SRAM2_WRP_UNLOCK();
00596   /* Starts a hardware SRAM2 erase operation*/
00597   __HAL_SYSCFG_SRAM2_ERASE();
00598 }
00599
00600 /**
00601   * @brief  Disable CPU2 SRAM fetch (execution) (This bit can be set by Firmware
00602   *         and will only be reset by a Hardware reset, including a reset after Standby.)
00603   * @note Firmware writing 0 has no effect.
00604   * @retval None
00605   */
00606 void HAL_SYSCFG_DisableSRAMFetch(void)
00607 {
00608   LL_SYSCFG_DisableSRAMFetch();
00609 }
00610
00611 /**
00612   * @brief  Check if CPU2 SRAM fetch is enabled
00613   * @retval State of bit (1 or 0).
00614   */
00615 uint32_t HAL_SYSCFG_IsEnabledSRAMFetch(void)
00616 {
00617   return (LL_SYSCFG_IsEnabledSRAMFetch());
00618 }
00619
00620 #if defined(VREFBUF)
00621 /**
00622   * @brief Configure the internal voltage reference buffer voltage scale.
00623   * @param VoltageScaling  specifies the output voltage to achieve
00624   *          This parameter can be one of the following values:
00625   *            @arg @ref SYSCFG_VREFBUF_VOLTAGE_SCALE0 : VREF_OUT1 around 2.048 V.
00626   *                                                This requires VDDA equal to or higher than 2.4 V.
00627   *            @arg @ref SYSCFG_VREFBUF_VOLTAGE_SCALE1 : VREF_OUT1 around 2.5 V.
00628   *                                                This requires VDDA equal to or higher than 2.8 V.
00629   * @retval None
00630   */
00631 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)
00632 {
00633   /* Check the parameters */
00634   assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling));
00635
00636   LL_VREFBUF_SetVoltageScaling(VoltageScaling);
00637 }
00638
00639 /**
00640   * @brief Configure the internal voltage reference buffer high impedance mode.
00641   * @param Mode  specifies the high impedance mode
00642   *          This parameter can be one of the following values:
00643   *            @arg @ref SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE : VREF+ pin is internally connect to VREFINT output.
00644   *            @arg @ref SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE : VREF+ pin is high impedance.
00645   * @retval HAL_OK/HAL_TIMEOUT
00646   */
00647 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode)
00648 {
00649
00650   /* Check the parameters */
00651   assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode));
00652
00653   MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode);
00654 }
00655
00656 /**
00657   * @brief Tune the Internal Voltage Reference buffer (VREFBUF).
00658   * @param TrimmingValue specifies trimming code for VREFBUF calibration
00659   *          This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x3F
00660   * @retval None
00661   */
00662 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue)
00663 {
00664   /* Check the parameters */
00665   assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue));
00666
00667   LL_VREFBUF_SetTrimming(TrimmingValue);
00668
00669 }
00670
00671 /**
00672   * @brief  Enable the Internal Voltage Reference buffer (VREFBUF).
00673   * @retval HAL_OK/HAL_TIMEOUT
00674   */
00675 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void)
00676 {
00677   uint32_t tickstart;
00678
00679   LL_VREFBUF_Enable();
00680
00681   /* Get Start Tick*/
00682   tickstart = HAL_GetTick();
00683
00684   /* Wait for VRR bit  */
00685   while(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0U)
00686   {
00687     if((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE)
00688     {
00689       return HAL_TIMEOUT;
00690     }
00691   }
00692
00693   return HAL_OK;
00694 }
00695
00696 /**
00697   * @brief  Disable the Internal Voltage Reference buffer (VREFBUF).
00698   *
00699   * @retval None
00700   */
00701 void HAL_SYSCFG_DisableVREFBUF(void)
00702 {
00703   LL_VREFBUF_Disable();
00704 }
00705 #endif /* VREFBUF */
00706
00707 /**
00708   * @brief  Enable the I/O analog switch voltage booster
00709   *
00710   * @retval None
00711   */
00712 void HAL_SYSCFG_EnableIOBooster(void)
00713 {
00714   LL_SYSCFG_EnableAnalogBooster();
00715 }
00716
00717 /**
00718   * @brief  Disable the I/O analog switch voltage booster
00719   *
00720   * @retval None
00721   */
00722 void HAL_SYSCFG_DisableIOBooster(void)
00723 {
00724   LL_SYSCFG_DisableAnalogBooster();
00725 }
00726
00727 /**
00728   * @brief  Enable the I/O analog switch supplied by VDD
00729   * @note   To be used when I/O analog switch voltage booster is not enabled
00730   * @retval None
00731   */
00732 void HAL_SYSCFG_EnableIOVdd(void)
00733 {
00734   LL_SYSCFG_EnableAnalogGpioSwitch();
00735 }
00736
00737 /**
00738   * @brief  Disable the I/O analog switch supplied by VDD
00739   *
00740   * @retval None
00741   */
00742 void HAL_SYSCFG_DisableIOVdd(void)
00743 {
00744   LL_SYSCFG_DisableAnalogGpioSwitch();
00745 }
00746
00747 /**
00748   * @brief  Enable the access for security IP
00749   * @note   When the system is secure (ESE = 1), this register provides write access security and can
00750   *         only be written by the CPU2. A write access from the CPU1 will be ignored and a bus error
00751   *         is generated.
00752   * @param  SecurityAccess This parameter can be a combination of the following values:
00753   *         @arg @ref HAL_SYSCFG_SECURE_ACCESS_AES1
00754   *         @arg @ref HAL_SYSCFG_SECURE_ACCESS_AES2
00755   *         @arg @ref HAL_SYSCFG_SECURE_ACCESS_PKA
00756   *         @arg @ref HAL_SYSCFG_SECURE_ACCESS_RNG
00757   * @retval None
00758   */
00759 void HAL_SYSCFG_EnableSecurityAccess(uint32_t SecurityAccess)
00760 {
00761   /* Check the parameters */
00762   assert_param(IS_SYSCFG_SECURITY_ACCESS(SecurityAccess));
00763
00764   LL_SYSCFG_EnableSecurityAccess(SecurityAccess);
00765 }
00766
00767 /**
00768   * @brief  Disable the access for security IP
00769   * @note   When the system is secure (ESE = 1), this register provides write access security and can
00770   *         only be written by the CPU2. A write access from the CPU1 will be ignored and a bus error
00771   *         is generated.
00772   * @param  SecurityAccess This parameter can be a combination of the following values:
00773   *         @arg @ref HAL_SYSCFG_SECURE_ACCESS_AES1
00774   *         @arg @ref HAL_SYSCFG_SECURE_ACCESS_AES2
00775   *         @arg @ref HAL_SYSCFG_SECURE_ACCESS_PKA
00776   *         @arg @ref HAL_SYSCFG_SECURE_ACCESS_RNG
00777   * @retval None
00778   */
00779 void HAL_SYSCFG_DisableSecurityAccess(uint32_t SecurityAccess)
00780 {
00781   /* Check the parameters */
00782   assert_param(IS_SYSCFG_SECURITY_ACCESS(SecurityAccess));
00783
00784   LL_SYSCFG_DisableSecurityAccess(SecurityAccess);
00785 }
00786
00787 /**
00788   * @brief  Indicate if access for security IP is enabled
00789   * @param  SecurityAccess This parameter can be one of the following values:
00790   *         @arg @ref HAL_SYSCFG_SECURE_ACCESS_AES1
00791   *         @arg @ref HAL_SYSCFG_SECURE_ACCESS_AES2
00792   *         @arg @ref HAL_SYSCFG_SECURE_ACCESS_PKA
00793   *         @arg @ref HAL_SYSCFG_SECURE_ACCESS_RNG
00794   * @retval State of bit (1 or 0).
00795   */
00796 uint32_t HAL_SYSCFG_IsEnabledSecurityAccess(uint32_t SecurityAccess)
00797 {
00798   return (LL_SYSCFG_IsEnabledSecurityAccess(SecurityAccess));
00799 }
00800 /**
00801   * @}
00802   */
00803
00804 /**
00805   * @}
00806   */
00807
00808 #endif /* HAL_MODULE_ENABLED */
00809 /**
00810   * @}
00811   */
00812
00813 /**
00814   * @}
00815   */
00816
00817 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:33 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal.h Source File

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stm32wbxx_hal.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal.h
00004   * @author  MCD Application Team
00005   * @brief   This file contains all the functions prototypes for the HAL
00006   *          module driver.
00007   ******************************************************************************
00008   * @attention
00009   *
00010   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00011   * All rights reserved.</center></h2>
00012   *
00013   * This software component is licensed by ST under BSD 3-Clause license,
00014   * the "License"; You may not use this file except in compliance with the
00015   * License. You may obtain a copy of the License at:
00016   *                        opensource.org/licenses/BSD-3-Clause
00017   *
00018   ******************************************************************************
00019   */
00020
00021 /* Define to prevent recursive inclusion -------------------------------------*/
00022 #ifndef STM32WBxx_HAL_H
00023 #define STM32WBxx_HAL_H
00024
00025 #ifdef __cplusplus
00026  extern "C" {
00027 #endif
00028
00029 /* Includes ------------------------------------------------------------------*/
00030 #include "stm32wbxx_hal_conf.h"
00031 #include "stm32wbxx_ll_system.h"
00032
00033 /** @addtogroup STM32WBxx_HAL_Driver
00034   * @{
00035   */
00036
00037 /** @defgroup HAL HAL
00038   * @{
00039   */
00040
00041 /* Exported constants --------------------------------------------------------*/
00042 /** @defgroup HAL_Exported_Constants HAL Exported Constants
00043   * @{
00044   */
00045
00046 /** @defgroup HAL_TICK_FREQ Tick Frequency
00047   * @{
00048   */
00049 #define  HAL_TICK_FREQ_10HZ         100U
00050 #define  HAL_TICK_FREQ_100HZ        10U
00051 #define  HAL_TICK_FREQ_1KHZ         1U
00052 #define  HAL_TICK_FREQ_DEFAULT      HAL_TICK_FREQ_1KHZ
00053
00054 /**
00055   * @}
00056   */
00057
00058 /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
00059   * @{
00060   */
00061
00062 /** @defgroup SYSCFG_BootMode BOOT Mode
00063   * @{
00064   */
00065 #define SYSCFG_BOOT_MAINFLASH           LL_SYSCFG_REMAP_FLASH           /*!< Main Flash memory mapped at 0x00000000   */
00066 #define SYSCFG_BOOT_SYSTEMFLASH         LL_SYSCFG_REMAP_SYSTEMFLASH     /*!< System Flash memory mapped at 0x00000000 */
00067 #define SYSCFG_BOOT_SRAM                LL_SYSCFG_REMAP_SRAM            /*!< SRAM1 mapped at 0x00000000               */
00068 #if defined(LL_SYSCFG_REMAP_QUADSPI)
00069 #define SYSCFG_BOOT_QUADSPI             LL_SYSCFG_REMAP_QUADSPI         /*!< QUADSPI memory mapped at 0x00000000      */
00070 #endif
00071 /**
00072   * @}
00073   */
00074
00075 /** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts
00076   * @{
00077   */
00078 #define SYSCFG_IT_FPU_IOC               SYSCFG_CFGR1_FPU_IE_0           /*!< Floating Point Unit Invalid operation Interrupt */
00079 #define SYSCFG_IT_FPU_DZC               SYSCFG_CFGR1_FPU_IE_1           /*!< Floating Point Unit Divide-by-zero Interrupt    */
00080 #define SYSCFG_IT_FPU_UFC               SYSCFG_CFGR1_FPU_IE_2           /*!< Floating Point Unit Underflow Interrupt         */
00081 #define SYSCFG_IT_FPU_OFC               SYSCFG_CFGR1_FPU_IE_3           /*!< Floating Point Unit Overflow Interrupt          */
00082 #define SYSCFG_IT_FPU_IDC               SYSCFG_CFGR1_FPU_IE_4           /*!< Floating Point Unit Input denormal Interrupt    */
00083 #define SYSCFG_IT_FPU_IXC               SYSCFG_CFGR1_FPU_IE_5           /*!< Floating Point Unit Inexact Interrupt           */
00084
00085 /**
00086   * @}
00087   */
00088
00089 /** @defgroup SYSCFG_SRAM2WRP SRAM2 Page Write protection (0 to 31)
00090   * @{
00091   */
00092 #define SYSCFG_SRAM2WRP_PAGE0           LL_SYSCFG_SRAM2WRP_PAGE0        /*!< SRAM2A Write protection page 0  */
00093 #define SYSCFG_SRAM2WRP_PAGE1           LL_SYSCFG_SRAM2WRP_PAGE1        /*!< SRAM2A Write protection page 1  */
00094 #define SYSCFG_SRAM2WRP_PAGE2           LL_SYSCFG_SRAM2WRP_PAGE2        /*!< SRAM2A Write protection page 2  */
00095 #define SYSCFG_SRAM2WRP_PAGE3           LL_SYSCFG_SRAM2WRP_PAGE3        /*!< SRAM2A Write protection page 3  */
00096 #define SYSCFG_SRAM2WRP_PAGE4           LL_SYSCFG_SRAM2WRP_PAGE4        /*!< SRAM2A Write protection page 4  */
00097 #define SYSCFG_SRAM2WRP_PAGE5           LL_SYSCFG_SRAM2WRP_PAGE5        /*!< SRAM2A Write protection page 5  */
00098 #define SYSCFG_SRAM2WRP_PAGE6           LL_SYSCFG_SRAM2WRP_PAGE6        /*!< SRAM2A Write protection page 6  */
00099 #define SYSCFG_SRAM2WRP_PAGE7           LL_SYSCFG_SRAM2WRP_PAGE7        /*!< SRAM2A Write protection page 7  */
00100 #define SYSCFG_SRAM2WRP_PAGE8           LL_SYSCFG_SRAM2WRP_PAGE8        /*!< SRAM2A Write protection page 8  */
00101 #define SYSCFG_SRAM2WRP_PAGE9           LL_SYSCFG_SRAM2WRP_PAGE9        /*!< SRAM2A Write protection page 9  */
00102 #define SYSCFG_SRAM2WRP_PAGE10          LL_SYSCFG_SRAM2WRP_PAGE10       /*!< SRAM2A Write protection page 10 */
00103 #define SYSCFG_SRAM2WRP_PAGE11          LL_SYSCFG_SRAM2WRP_PAGE11       /*!< SRAM2A Write protection page 11 */
00104 #define SYSCFG_SRAM2WRP_PAGE12          LL_SYSCFG_SRAM2WRP_PAGE12       /*!< SRAM2A Write protection page 12 */
00105 #define SYSCFG_SRAM2WRP_PAGE13          LL_SYSCFG_SRAM2WRP_PAGE13       /*!< SRAM2A Write protection page 13 */
00106 #define SYSCFG_SRAM2WRP_PAGE14          LL_SYSCFG_SRAM2WRP_PAGE14       /*!< SRAM2A Write protection page 14 */
00107 #define SYSCFG_SRAM2WRP_PAGE15          LL_SYSCFG_SRAM2WRP_PAGE15       /*!< SRAM2A Write protection page 15 */
00108 #define SYSCFG_SRAM2WRP_PAGE16          LL_SYSCFG_SRAM2WRP_PAGE16       /*!< SRAM2A Write protection page 16 */
00109 #define SYSCFG_SRAM2WRP_PAGE17          LL_SYSCFG_SRAM2WRP_PAGE17       /*!< SRAM2A Write protection page 17 */
00110 #define SYSCFG_SRAM2WRP_PAGE18          LL_SYSCFG_SRAM2WRP_PAGE18       /*!< SRAM2A Write protection page 18 */
00111 #define SYSCFG_SRAM2WRP_PAGE19          LL_SYSCFG_SRAM2WRP_PAGE19       /*!< SRAM2A Write protection page 19 */
00112 #define SYSCFG_SRAM2WRP_PAGE20          LL_SYSCFG_SRAM2WRP_PAGE20       /*!< SRAM2A Write protection page 20 */
00113 #define SYSCFG_SRAM2WRP_PAGE21          LL_SYSCFG_SRAM2WRP_PAGE21       /*!< SRAM2A Write protection page 21 */
00114 #define SYSCFG_SRAM2WRP_PAGE22          LL_SYSCFG_SRAM2WRP_PAGE22       /*!< SRAM2A Write protection page 22 */
00115 #define SYSCFG_SRAM2WRP_PAGE23          LL_SYSCFG_SRAM2WRP_PAGE23       /*!< SRAM2A Write protection page 23 */
00116 #define SYSCFG_SRAM2WRP_PAGE24          LL_SYSCFG_SRAM2WRP_PAGE24       /*!< SRAM2A Write protection page 24 */
00117 #define SYSCFG_SRAM2WRP_PAGE25          LL_SYSCFG_SRAM2WRP_PAGE25       /*!< SRAM2A Write protection page 25 */
00118 #define SYSCFG_SRAM2WRP_PAGE26          LL_SYSCFG_SRAM2WRP_PAGE26       /*!< SRAM2A Write protection page 26 */
00119 #define SYSCFG_SRAM2WRP_PAGE27          LL_SYSCFG_SRAM2WRP_PAGE27       /*!< SRAM2A Write protection page 27 */
00120 #define SYSCFG_SRAM2WRP_PAGE28          LL_SYSCFG_SRAM2WRP_PAGE28       /*!< SRAM2A Write protection page 28 */
00121 #define SYSCFG_SRAM2WRP_PAGE29          LL_SYSCFG_SRAM2WRP_PAGE29       /*!< SRAM2A Write protection page 29 */
00122 #define SYSCFG_SRAM2WRP_PAGE30          LL_SYSCFG_SRAM2WRP_PAGE30       /*!< SRAM2A Write protection page 30 */
00123 #define SYSCFG_SRAM2WRP_PAGE31          LL_SYSCFG_SRAM2WRP_PAGE31       /*!< SRAM2A Write protection page 31 */
00124
00125 /**
00126   * @}
00127   */
00128
00129 /** @defgroup SYSCFG_SRAM2WRP_32_63 SRAM2 Page Write protection (32 to 63)
00130   * @{
00131   */
00132 #define SYSCFG_SRAM2WRP_PAGE32          LL_SYSCFG_SRAM2WRP_PAGE32       /*!< SRAM2B Write protection page 32 */
00133 #define SYSCFG_SRAM2WRP_PAGE33          LL_SYSCFG_SRAM2WRP_PAGE33       /*!< SRAM2B Write protection page 33 */
00134 #define SYSCFG_SRAM2WRP_PAGE34          LL_SYSCFG_SRAM2WRP_PAGE34       /*!< SRAM2B Write protection page 34 */
00135 #define SYSCFG_SRAM2WRP_PAGE35          LL_SYSCFG_SRAM2WRP_PAGE35       /*!< SRAM2B Write protection page 35 */
00136 #define SYSCFG_SRAM2WRP_PAGE36          LL_SYSCFG_SRAM2WRP_PAGE36       /*!< SRAM2B Write protection page 36 */
00137 #define SYSCFG_SRAM2WRP_PAGE37          LL_SYSCFG_SRAM2WRP_PAGE37       /*!< SRAM2B Write protection page 37 */
00138 #define SYSCFG_SRAM2WRP_PAGE38          LL_SYSCFG_SRAM2WRP_PAGE38       /*!< SRAM2B Write protection page 38 */
00139 #define SYSCFG_SRAM2WRP_PAGE39          LL_SYSCFG_SRAM2WRP_PAGE39       /*!< SRAM2B Write protection page 39 */
00140 #define SYSCFG_SRAM2WRP_PAGE40          LL_SYSCFG_SRAM2WRP_PAGE40       /*!< SRAM2B Write protection page 40 */
00141 #define SYSCFG_SRAM2WRP_PAGE41          LL_SYSCFG_SRAM2WRP_PAGE41       /*!< SRAM2B Write protection page 41 */
00142 #define SYSCFG_SRAM2WRP_PAGE42          LL_SYSCFG_SRAM2WRP_PAGE42       /*!< SRAM2B Write protection page 42 */
00143 #define SYSCFG_SRAM2WRP_PAGE43          LL_SYSCFG_SRAM2WRP_PAGE43       /*!< SRAM2B Write protection page 43 */
00144 #define SYSCFG_SRAM2WRP_PAGE44          LL_SYSCFG_SRAM2WRP_PAGE44       /*!< SRAM2B Write protection page 44 */
00145 #define SYSCFG_SRAM2WRP_PAGE45          LL_SYSCFG_SRAM2WRP_PAGE45       /*!< SRAM2B Write protection page 45 */
00146 #define SYSCFG_SRAM2WRP_PAGE46          LL_SYSCFG_SRAM2WRP_PAGE46       /*!< SRAM2B Write protection page 46 */
00147 #define SYSCFG_SRAM2WRP_PAGE47          LL_SYSCFG_SRAM2WRP_PAGE47       /*!< SRAM2B Write protection page 47 */
00148 #define SYSCFG_SRAM2WRP_PAGE48          LL_SYSCFG_SRAM2WRP_PAGE48       /*!< SRAM2B Write protection page 48 */
00149 #define SYSCFG_SRAM2WRP_PAGE49          LL_SYSCFG_SRAM2WRP_PAGE49       /*!< SRAM2B Write protection page 49 */
00150 #define SYSCFG_SRAM2WRP_PAGE50          LL_SYSCFG_SRAM2WRP_PAGE50       /*!< SRAM2B Write protection page 50 */
00151 #define SYSCFG_SRAM2WRP_PAGE51          LL_SYSCFG_SRAM2WRP_PAGE51       /*!< SRAM2B Write protection page 51 */
00152 #define SYSCFG_SRAM2WRP_PAGE52          LL_SYSCFG_SRAM2WRP_PAGE52       /*!< SRAM2B Write protection page 52 */
00153 #define SYSCFG_SRAM2WRP_PAGE53          LL_SYSCFG_SRAM2WRP_PAGE53       /*!< SRAM2B Write protection page 53 */
00154 #define SYSCFG_SRAM2WRP_PAGE54          LL_SYSCFG_SRAM2WRP_PAGE54       /*!< SRAM2B Write protection page 54 */
00155 #define SYSCFG_SRAM2WRP_PAGE55          LL_SYSCFG_SRAM2WRP_PAGE55       /*!< SRAM2B Write protection page 55 */
00156 #define SYSCFG_SRAM2WRP_PAGE56          LL_SYSCFG_SRAM2WRP_PAGE56       /*!< SRAM2B Write protection page 56 */
00157 #define SYSCFG_SRAM2WRP_PAGE57          LL_SYSCFG_SRAM2WRP_PAGE57       /*!< SRAM2B Write protection page 57 */
00158 #define SYSCFG_SRAM2WRP_PAGE58          LL_SYSCFG_SRAM2WRP_PAGE58       /*!< SRAM2B Write protection page 58 */
00159 #define SYSCFG_SRAM2WRP_PAGE59          LL_SYSCFG_SRAM2WRP_PAGE59       /*!< SRAM2B Write protection page 59 */
00160 #define SYSCFG_SRAM2WRP_PAGE60          LL_SYSCFG_SRAM2WRP_PAGE60       /*!< SRAM2B Write protection page 60 */
00161 #define SYSCFG_SRAM2WRP_PAGE61          LL_SYSCFG_SRAM2WRP_PAGE61       /*!< SRAM2B Write protection page 61 */
00162 #define SYSCFG_SRAM2WRP_PAGE62          LL_SYSCFG_SRAM2WRP_PAGE62       /*!< SRAM2B Write protection page 62 */
00163 #define SYSCFG_SRAM2WRP_PAGE63          LL_SYSCFG_SRAM2WRP_PAGE63       /*!< SRAM2B Write protection page 63 */
00164
00165 /**
00166   * @}
00167   */
00168
00169 #if defined(VREFBUF)
00170 /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
00171   * @{
00172   */
00173 #define SYSCFG_VREFBUF_VOLTAGE_SCALE0   LL_VREFBUF_VOLTAGE_SCALE0       /*!< Voltage reference scale 0 (VREF_OUT1) */
00174 #define SYSCFG_VREFBUF_VOLTAGE_SCALE1   LL_VREFBUF_VOLTAGE_SCALE1       /*!< Voltage reference scale 1 (VREF_OUT2) */
00175
00176 /**
00177   * @}
00178   */
00179
00180 /** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
00181   * @{
00182   */
00183 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE   0x00000000U             /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
00184 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE    VREFBUF_CSR_HIZ         /*!< VREF_plus pin is high impedance */
00185
00186 /**
00187   * @}
00188   */
00189 #endif /* VREFBUF */
00190
00191 /** @defgroup SYSCFG_SRAM_flags_definition SRAM Flags
00192   * @{
00193   */
00194
00195 #define SYSCFG_FLAG_SRAM2_PE            SYSCFG_CFGR2_SPF                /*!< SRAM2 parity error */
00196 #define SYSCFG_FLAG_SRAM2_BUSY          SYSCFG_SCSR_SRAM2BSY            /*!< SRAM2 busy by erase operation */
00197
00198 /**
00199   * @}
00200   */
00201
00202 /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
00203   * @{
00204   */
00205
00206 /** @brief  Fast-mode Plus driving capability on a specific GPIO
00207   */
00208 #define SYSCFG_FASTMODEPLUS_PB6         SYSCFG_CFGR1_I2C_PB6_FMP        /*!< Enable Fast-mode Plus on PB6 */
00209 #define SYSCFG_FASTMODEPLUS_PB7         SYSCFG_CFGR1_I2C_PB7_FMP        /*!< Enable Fast-mode Plus on PB7 */
00210 #define SYSCFG_FASTMODEPLUS_PB8         SYSCFG_CFGR1_I2C_PB8_FMP        /*!< Enable Fast-mode Plus on PB8 */
00211 #define SYSCFG_FASTMODEPLUS_PB9         SYSCFG_CFGR1_I2C_PB9_FMP        /*!< Enable Fast-mode Plus on PB9 */
00212
00213 /**
00214  * @}
00215  */
00216
00217 /** @defgroup Secure_IP_Write_Access Secure IP Write Access
00218   * @{
00219   */
00220 #if defined(LL_SYSCFG_SECURE_ACCESS_AES1)
00221 #define HAL_SYSCFG_SECURE_ACCESS_AES1   LL_SYSCFG_SECURE_ACCESS_AES1    /*!< Enabling the security access of Advanced Encryption Standard 1 KEY[7:0] */
00222 #endif
00223 #define HAL_SYSCFG_SECURE_ACCESS_AES2   LL_SYSCFG_SECURE_ACCESS_AES2    /*!< Enabling the security access of Advanced Encryption Standard 2          */
00224 #define HAL_SYSCFG_SECURE_ACCESS_PKA    LL_SYSCFG_SECURE_ACCESS_PKA     /*!< Enabling the security access of Public Key Accelerator                  */
00225 #define HAL_SYSCFG_SECURE_ACCESS_RNG    LL_SYSCFG_SECURE_ACCESS_RNG     /*!< Enabling the security access of Random Number Generator                 */
00226 /**
00227   * @}
00228   */
00229
00230 /**
00231   * @}
00232   */
00233
00234 /**
00235   * @}
00236   */
00237
00238 /* Exported macros -----------------------------------------------------------*/
00239 /** @defgroup HAL_Exported_Macros HAL Exported Macros
00240   * @{
00241   */
00242
00243 /** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros
00244   * @{
00245   */
00246
00247 /** @brief  Freeze and Unfreeze Peripherals in Debug mode
00248   */
00249
00250 /** @defgroup DBGMCU_APBx_GRPx_STOP_IP DBGMCU CPU1 APBx GRPx STOP IP
00251   * @{
00252   */
00253 #if defined(LL_DBGMCU_APB1_GRP1_TIM2_STOP)
00254 #define __HAL_DBGMCU_FREEZE_TIM2()              LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_TIM2_STOP)
00255 #define __HAL_DBGMCU_UNFREEZE_TIM2()            LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_TIM2_STOP)
00256 #endif
00257
00258 #if defined(LL_DBGMCU_APB1_GRP1_RTC_STOP)
00259 #define __HAL_DBGMCU_FREEZE_RTC()               LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_RTC_STOP)
00260 #define __HAL_DBGMCU_UNFREEZE_RTC()             LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_RTC_STOP)
00261 #endif
00262
00263 #if defined(LL_DBGMCU_APB1_GRP1_WWDG_STOP)
00264 #define __HAL_DBGMCU_FREEZE_WWDG()              LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG_STOP)
00265 #define __HAL_DBGMCU_UNFREEZE_WWDG()            LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG_STOP)
00266 #endif
00267
00268 #if defined(LL_DBGMCU_APB1_GRP1_IWDG_STOP)
00269 #define __HAL_DBGMCU_FREEZE_IWDG()              LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP)
00270 #define __HAL_DBGMCU_UNFREEZE_IWDG()            LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP)
00271 #endif
00272
00273 #if defined(LL_DBGMCU_APB1_GRP1_I2C1_STOP)
00274 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()      LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_I2C1_STOP)
00275 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT()    LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_I2C1_STOP)
00276 #endif
00277
00278 #if defined(LL_DBGMCU_APB1_GRP1_I2C3_STOP)
00279 #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT()      LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_I2C3_STOP)
00280 #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT()    LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_I2C3_STOP)
00281 #endif
00282
00283 #if defined(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP)
00284 #define __HAL_DBGMCU_FREEZE_LPTIM1()            LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP)
00285 #define __HAL_DBGMCU_UNFREEZE_LPTIM1()          LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP)
00286 #endif
00287
00288 #if defined(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP)
00289 #define __HAL_DBGMCU_FREEZE_LPTIM2()            LL_DBGMCU_APB1_GRP2_FreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP)
00290 #define __HAL_DBGMCU_UNFREEZE_LPTIM2()          LL_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP)
00291 #endif
00292
00293 #if defined(LL_DBGMCU_APB2_GRP1_TIM1_STOP)
00294 #define __HAL_DBGMCU_FREEZE_TIM1()              LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM1_STOP)
00295 #define __HAL_DBGMCU_UNFREEZE_TIM1()            LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM1_STOP)
00296 #endif
00297
00298 #if defined(LL_DBGMCU_APB2_GRP1_TIM16_STOP)
00299 #define __HAL_DBGMCU_FREEZE_TIM16()             LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM16_STOP)
00300 #define __HAL_DBGMCU_UNFREEZE_TIM16()           LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM16_STOP)
00301 #endif
00302
00303 #if defined(LL_DBGMCU_APB2_GRP1_TIM17_STOP)
00304 #define __HAL_DBGMCU_FREEZE_TIM17()             LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM17_STOP)
00305 #define __HAL_DBGMCU_UNFREEZE_TIM17()           LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM17_STOP)
00306 #endif
00307
00308 /**
00309   * @}
00310   */
00311
00312 /** @defgroup DBGMCU_C2_APBx_GRPx_STOP_IP DBGMCU CPU2 APBx GRPx STOP IP
00313   * @{
00314   */
00315 #if defined(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP)
00316 #define __HAL_C2_DBGMCU_FREEZE_TIM2()           LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP)
00317 #define __HAL_C2_DBGMCU_UNFREEZE_TIM2()         LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP)
00318 #endif
00319
00320 #if defined(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP)
00321 #define __HAL_C2_DBGMCU_FREEZE_RTC()            LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP)
00322 #define __HAL_C2_DBGMCU_UNFREEZE_RTC()          LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP)
00323 #endif
00324
00325 #if defined(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP)
00326 #define __HAL_C2_DBGMCU_FREEZE_IWDG()           LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP)
00327 #define __HAL_C2_DBGMCU_UNFREEZE_IWDG()         LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP)
00328 #endif
00329
00330 #if defined(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP)
00331 #define __HAL_C2_DBGMCU_FREEZE_I2C1_TIMEOUT()   LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP)
00332 #define __HAL_C2_DBGMCU_UNFREEZE_I2C1_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP)
00333 #endif
00334
00335 #if defined(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP)
00336 #define __HAL_C2_DBGMCU_FREEZE_I2C3_TIMEOUT()   LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP)
00337 #define __HAL_C2_DBGMCU_UNFREEZE_I2C3_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP)
00338 #endif
00339
00340 #if defined(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP)
00341 #define __HAL_C2_DBGMCU_FREEZE_LPTIM1()         LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP)
00342 #define __HAL_C2_DBGMCU_UNFREEZE_LPTIM1()       LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP)
00343 #endif
00344
00345 #if defined(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP)
00346 #define __HAL_C2_DBGMCU_FREEZE_LPTIM2()         LL_C2_DBGMCU_APB1_GRP2_FreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP)
00347 #define __HAL_C2_DBGMCU_UNFREEZE_LPTIM2()       LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP)
00348 #endif
00349
00350 #if defined(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP)
00351 #define __HAL_C2_DBGMCU_FREEZE_TIM1()           LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP)
00352 #define __HAL_C2_DBGMCU_UNFREEZE_TIM1()         LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP)
00353 #endif
00354
00355 #if defined(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP)
00356 #define __HAL_C2_DBGMCU_FREEZE_TIM16()          LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP)
00357 #define __HAL_C2_DBGMCU_UNFREEZE_TIM16()        LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP)
00358 #endif
00359
00360 #if defined(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP)
00361 #define __HAL_C2_DBGMCU_FREEZE_TIM17()          LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP)
00362 #define __HAL_C2_DBGMCU_UNFREEZE_TIM17()        LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP)
00363 #endif
00364
00365 /**
00366   * @}
00367   */
00368
00369 /**
00370   * @}
00371   */
00372
00373 /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
00374   * @{
00375   */
00376
00377 /** @brief  Main Flash memory mapped at 0x00000000
00378   */
00379 #define __HAL_SYSCFG_REMAPMEMORY_FLASH()        LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_FLASH)
00380
00381 /** @brief  System Flash memory mapped at 0x00000000
00382   */
00383 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH()  LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_SYSTEMFLASH)
00384
00385 /** @brief  Embedded SRAM mapped at 0x00000000
00386   */
00387 #define __HAL_SYSCFG_REMAPMEMORY_SRAM()         LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_SRAM)
00388
00389 #if defined(LL_SYSCFG_REMAP_QUADSPI)
00390 /** @brief  QUADSPI mapped at 0x00000000.
00391   */
00392 #define __HAL_SYSCFG_REMAPMEMORY_QUADSPI()      LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_QUADSPI)
00393 #endif
00394
00395 /**
00396   * @brief  Return the boot mode as configured by user.
00397   * @retval The boot mode as configured by user. The returned value can be one
00398   *         of the following values:
00399   *           @arg @ref SYSCFG_BOOT_MAINFLASH
00400   *           @arg @ref SYSCFG_BOOT_SYSTEMFLASH
00401   *           @arg @ref SYSCFG_BOOT_SRAM
00402 #if defined(LL_SYSCFG_REMAP_QUADSPI)
00403   *           @arg @ref SYSCFG_BOOT_QUADSPI
00404 #endif
00405   */
00406 #define __HAL_SYSCFG_GET_BOOT_MODE()            LL_SYSCFG_GetRemapMemory()
00407
00408 /** @brief  SRAM2 page 0 to 31 write protection enable macro
00409   * @param  __SRAM2WRP__  This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP
00410   * @note   Write protection can only be disabled by a system reset
00411   */
00412 /* Legacy define */
00413 #define __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE      __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
00414 #define __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE(__SRAM2WRP__)    do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\
00415                                                                 LL_SYSCFG_EnableSRAM2PageWRP_0_31(__SRAM2WRP__);\
00416                                                             }while(0)
00417
00418 /** @brief  SRAM2 page 32 to 63 write protection enable macro
00419   * @param  __SRAM2WRP__  This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP_32_63
00420   * @note   Write protection can only be disabled by a system reset
00421   */
00422 #define __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE(__SRAM2WRP__)   do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\
00423                                                                 LL_SYSCFG_EnableSRAM2PageWRP_32_63(__SRAM2WRP__);\
00424                                                             }while(0)
00425
00426 /** @brief  SRAM2 page write protection unlock prior to erase
00427   * @note   Writing a wrong key reactivates the write protection
00428   */
00429 #define __HAL_SYSCFG_SRAM2_WRP_UNLOCK()         LL_SYSCFG_UnlockSRAM2WRP()
00430
00431 /** @brief  SRAM2 erase
00432   * @note   __SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM2_BUSY) may be used to check end of erase
00433   */
00434 #define __HAL_SYSCFG_SRAM2_ERASE()              LL_SYSCFG_EnableSRAM2Erase()
00435
00436 /** @brief  Floating Point Unit interrupt enable/disable macros
00437   * @param __INTERRUPT__  This parameter can be a value of @ref SYSCFG_FPU_Interrupts
00438   */
00439 #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__)    do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
00440                                                                 SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
00441                                                             }while(0)
00442
00443 #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__)   do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
00444                                                                 CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
00445                                                             }while(0)
00446
00447 /** @brief  SYSCFG Break ECC lock.
00448   *         Enable and lock the connection of Flash ECC error connection to TIM1/16/17 Break input.
00449   * @note   The selected configuration is locked and can be unlocked only by system reset.
00450   */
00451 #define __HAL_SYSCFG_BREAK_ECC_LOCK()           LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_ECC)
00452
00453 /** @brief  SYSCFG Break Cortex-M4 Lockup lock.
00454   *         Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/16/17 Break input.
00455   * @note   The selected configuration is locked and can be unlocked only by system reset.
00456   */
00457 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK()        LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_LOCKUP)
00458
00459 /** @brief  SYSCFG Break PVD lock.
00460   *         Enable and lock the PVD connection to Timer1/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register.
00461   * @note   The selected configuration is locked and can be unlocked only by system reset.
00462   */
00463 #define __HAL_SYSCFG_BREAK_PVD_LOCK()           LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_PVD)
00464
00465 /** @brief  SYSCFG Break SRAM2 parity lock.
00466   *         Enable and lock the SRAM2 parity error signal connection to TIM1/16/17 Break input.
00467   * @note   The selected configuration is locked and can be unlocked by system reset.
00468   */
00469 #define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK()   LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_SRAM2_PARITY)
00470
00471 /** @brief  Check SYSCFG flag is set or not.
00472   * @param  __FLAG__  specifies the flag to check.
00473   *         This parameter can be one of the following values:
00474   *            @arg @ref SYSCFG_FLAG_SRAM2_PE   SRAM2 Parity Error Flag
00475   *            @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing
00476   * @retval The new state of __FLAG__ (TRUE or FALSE).
00477   */
00478 #define __HAL_SYSCFG_GET_FLAG(__FLAG__)         ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0U) ? 1U : 0U)
00479
00480 /** @brief  Set the SPF bit to clear the SRAM Parity Error Flag.
00481   */
00482 #define __HAL_SYSCFG_CLEAR_FLAG()               LL_SYSCFG_ClearFlag_SP()
00483
00484 /** @brief  Fast mode Plus driving capability enable/disable macros
00485   * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO
00486   */
00487 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)  do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \
00488                                                                 LL_SYSCFG_EnableFastModePlus(__FASTMODEPLUS__);           \
00489                                                                }while(0)
00490
00491 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \
00492                                                                 LL_SYSCFG_DisableFastModePlus(__FASTMODEPLUS__);          \
00493                                                                }while(0)
00494
00495 /**
00496   * @}
00497   */
00498
00499 /**
00500   * @}
00501   */
00502
00503 /* Private macros ------------------------------------------------------------*/
00504 /** @defgroup HAL_Private_Macros HAL Private Macros
00505   * @{
00506   */
00507
00508 /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros
00509   * @{
00510   */
00511
00512 #define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__)          ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \
00513                                                          (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \
00514                                                          (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \
00515                                                          (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \
00516                                                          (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \
00517                                                          (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC))
00518
00519 #define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__)               (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFU))
00520
00521 #if defined(VREFBUF)
00522 #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)      (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
00523                                                          ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1))
00524
00525 #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__)     (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
00526                                                          ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
00527
00528 #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__)           (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
00529 #endif
00530
00531 #define IS_SYSCFG_FASTMODEPLUS(__PIN__)                 ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6)  == SYSCFG_FASTMODEPLUS_PB6)  || \
00532                                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7)  == SYSCFG_FASTMODEPLUS_PB7)  || \
00533                                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8)  == SYSCFG_FASTMODEPLUS_PB8)  || \
00534                                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9)  == SYSCFG_FASTMODEPLUS_PB9))
00535
00536 #if defined(LL_SYSCFG_SECURE_ACCESS_AES1)
00537 #define IS_SYSCFG_SECURITY_ACCESS(__VALUE__)            ((((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_AES1)  == HAL_SYSCFG_SECURE_ACCESS_AES1)  || \
00538                                                          (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_AES2)  == HAL_SYSCFG_SECURE_ACCESS_AES2)  || \
00539                                                          (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_PKA)   == HAL_SYSCFG_SECURE_ACCESS_PKA)   || \
00540                                                          (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_RNG)   == HAL_SYSCFG_SECURE_ACCESS_RNG))
00541 #else
00542 #define IS_SYSCFG_SECURITY_ACCESS(__VALUE__)            ((((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_AES2)  == HAL_SYSCFG_SECURE_ACCESS_AES2)  || \
00543                                                          (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_PKA)   == HAL_SYSCFG_SECURE_ACCESS_PKA)   || \
00544                                                          (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_RNG)   == HAL_SYSCFG_SECURE_ACCESS_RNG))
00545 #endif
00546
00547 /**
00548   * @}
00549   */
00550
00551 /**
00552   * @}
00553   */
00554
00555 /** @defgroup HAL_Private_Macros HAL Private Macros
00556   * @{
00557   */
00558 #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ)  || \
00559                            ((FREQ) == HAL_TICK_FREQ_100HZ) || \
00560                            ((FREQ) == HAL_TICK_FREQ_1KHZ))
00561 /**
00562   * @}
00563   */
00564
00565
00566 /* Exported functions --------------------------------------------------------*/
00567
00568 /** @defgroup HAL_Exported_Functions HAL Exported Functions
00569   * @{
00570   */
00571
00572 /** @defgroup HAL_Exported_Functions_Group1 HAL Initialization and Configuration functions
00573   * @{
00574   */
00575
00576 /* Initialization and Configuration functions  ******************************/
00577 HAL_StatusTypeDef HAL_Init(void);
00578 HAL_StatusTypeDef HAL_DeInit(void);
00579 void HAL_MspInit(void);
00580 void HAL_MspDeInit(void);
00581
00582 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
00583
00584 /**
00585   * @}
00586   */
00587
00588 /** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
00589   * @{
00590   */
00591
00592 /* Peripheral Control functions  ************************************************/
00593 void HAL_IncTick(void);
00594 void HAL_Delay(uint32_t Delay);
00595 uint32_t HAL_GetTick(void);
00596 uint32_t HAL_GetTickPrio(void);
00597 HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq);
00598 uint32_t HAL_GetTickFreq(void);
00599 void HAL_SuspendTick(void);
00600 void HAL_ResumeTick(void);
00601 uint32_t HAL_GetHalVersion(void);
00602 uint32_t HAL_GetREVID(void);
00603 uint32_t HAL_GetDEVID(void);
00604 uint32_t HAL_GetUIDw0(void);
00605 uint32_t HAL_GetUIDw1(void);
00606 uint32_t HAL_GetUIDw2(void);
00607
00608 /**
00609   * @}
00610   */
00611
00612 /** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions
00613   * @{
00614   */
00615
00616 /* DBGMCU Peripheral Control functions  *****************************************/
00617 void HAL_DBGMCU_EnableDBGSleepMode(void);
00618 void HAL_DBGMCU_DisableDBGSleepMode(void);
00619 void HAL_DBGMCU_EnableDBGStopMode(void);
00620 void HAL_DBGMCU_DisableDBGStopMode(void);
00621 void HAL_DBGMCU_EnableDBGStandbyMode(void);
00622 void HAL_DBGMCU_DisableDBGStandbyMode(void);
00623 /**
00624   * @}
00625   */
00626
00627 /* Exported variables ---------------------------------------------------------*/
00628 /** @addtogroup HAL_Exported_Variables
00629   * @{
00630   */
00631 extern __IO uint32_t uwTick;
00632 extern uint32_t uwTickPrio;
00633 extern uint32_t uwTickFreq;
00634 /**
00635   * @}
00636   */
00637
00638 /** @addtogroup HAL_Exported_Functions_Group4 HAL System Configuration functions
00639   * @{
00640   */
00641
00642 /* SYSCFG Control functions  ****************************************************/
00643 void HAL_SYSCFG_SRAM2Erase(void);
00644 void HAL_SYSCFG_DisableSRAMFetch(void);
00645 uint32_t HAL_SYSCFG_IsEnabledSRAMFetch(void);
00646
00647 #if defined(VREFBUF)
00648 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
00649 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
00650 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
00651 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
00652 void HAL_SYSCFG_DisableVREFBUF(void);
00653 #endif
00654
00655 void HAL_SYSCFG_EnableIOBooster(void);
00656 void HAL_SYSCFG_DisableIOBooster(void);
00657 void HAL_SYSCFG_EnableIOVdd(void);
00658 void HAL_SYSCFG_DisableIOVdd(void);
00659
00660 void HAL_SYSCFG_EnableSecurityAccess(uint32_t SecurityAccess);
00661 void HAL_SYSCFG_DisableSecurityAccess(uint32_t SecurityAccess);
00662 uint32_t HAL_SYSCFG_IsEnabledSecurityAccess(uint32_t SecurityAccess);
00663
00664 /**
00665   * @}
00666   */
00667
00668 /**
00669   * @}
00670   */
00671
00672 /**
00673   * @}
00674   */
00675
00676 /**
00677   * @}
00678   */
00679
00680 #ifdef __cplusplus
00681 }
00682 #endif
00683
00684 #endif /* STM32WBxx_HAL_H */
00685
00686 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:33 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_adc.c Source File

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stm32wbxx_hal_adc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_adc.c
00004   * @author  MCD Application Team
00005   * @brief   This file provides firmware functions to manage the following
00006   *          functionalities of the Analog to Digital Convertor (ADC)
00007   *          peripheral:
00008   *           + Initialization and de-initialization functions
00009   *             ++ Initialization and Configuration of ADC
00010   *           + Operation functions
00011   *             ++ Start, stop, get result of conversions of regular
00012   *                group, using 3 possible modes: polling, interruption or DMA.
00013   *           + Control functions
00014   *             ++ Channels configuration on regular group
00015   *             ++ Analog Watchdog configuration
00016   *           + State functions
00017   *             ++ ADC state machine management
00018   *             ++ Interrupts and flags management
00019   *          Other functions (extended functions) are available in file
00020   *          "stm32wbxx_hal_adc_ex.c".
00021   *
00022   @verbatim
00023   ==============================================================================
00024                      ##### ADC peripheral features #####
00025   ==============================================================================
00026   [..]
00027   (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
00028
00029   (+) Interrupt generation at the end of regular conversion and in case of
00030       analog watchdog or overrun events.
00031
00032   (+) Single and continuous conversion modes.
00033
00034   (+) Scan mode for conversion of several channels sequentially.
00035
00036   (+) Data alignment with in-built data coherency.
00037
00038   (+) Programmable sampling time (channel wise)
00039
00040   (+) External trigger (timer or EXTI) with configurable polarity
00041
00042   (+) DMA request generation for transfer of conversions data of regular group.
00043
00044   (+) ADC channels selectable single/differential input.
00045
00046   (+) ADC offset shared on 4 offset instances.
00047   (+) ADC calibration
00048
00049   (+) ADC conversion of regular group.
00050
00051   (+) ADC supply requirements: 1.62 V to 3.6 V.
00052
00053   (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
00054       Vdda or to an external voltage reference).
00055
00056
00057                      ##### How to use this driver #####
00058   ==============================================================================
00059     [..]
00060
00061      *** Configuration of top level parameters related to ADC ***
00062      ============================================================
00063      [..]
00064
00065     (#) Enable the ADC interface
00066         (++) As prerequisite, ADC clock must be configured at RCC top level.
00067
00068         (++) Two clock settings are mandatory:
00069              (+++) ADC clock (core clock, also possibly conversion clock).
00070
00071              (+++) ADC clock (conversions clock).
00072                    Two possible clock sources: synchronous clock derived from AHB2 clock
00073                    or asynchronous clock derived from system clock, PLLSAI1 (output divider R) or the PLL system (output divider P)
00074                    running up to 64MHz.
00075
00076              (+++) Example:
00077                    Into HAL_ADC_MspInit() (recommended code location) or with
00078                    other device clock parameters configuration:
00079                (+++) __HAL_RCC_ADC_CLK_ENABLE();                  (mandatory)
00080
00081                RCC_ADCCLKSOURCE_PLL enable:                       (optional: if asynchronous clock selected)
00082                (+++) RCC_PeriphClkInitTypeDef   RCC_PeriphClkInit;
00083                (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
00084                (+++) PeriphClkInit.AdcClockSelection    = RCC_ADCCLKSOURCE_PLL;
00085                (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
00086
00087         (++) ADC clock source and clock prescaler are configured at ADC level with
00088              parameter "ClockPrescaler" using function HAL_ADC_Init().
00089
00090     (#) ADC pins configuration
00091          (++) Enable the clock for the ADC GPIOs
00092               using macro __HAL_RCC_GPIOx_CLK_ENABLE()
00093          (++) Configure these ADC pins in analog mode
00094               using function HAL_GPIO_Init()
00095
00096     (#) Optionally, in case of usage of ADC with interruptions:
00097          (++) Configure the NVIC for ADC
00098               using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
00099          (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
00100               into the function of corresponding ADC interruption vector
00101               ADCx_IRQHandler().
00102
00103     (#) Optionally, in case of usage of DMA:
00104          (++) Configure the DMA (DMA channel, mode normal or circular, ...)
00105               using function HAL_DMA_Init().
00106          (++) Configure the NVIC for DMA
00107               using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
00108          (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
00109               into the function of corresponding DMA interruption vector
00110               DMAx_Channelx_IRQHandler().
00111
00112      *** Configuration of ADC, group regular, channels parameters ***
00113      ================================================================
00114      [..]
00115
00116     (#) Configure the ADC parameters (resolution, data alignment, ...)
00117         and regular group parameters (conversion trigger, sequencer, ...)
00118         using function HAL_ADC_Init().
00119
00120     (#) Configure the channels for regular group parameters (channel number,
00121         channel rank into sequencer, ..., into regular group)
00122         using function HAL_ADC_ConfigChannel().
00123
00124     (#) Optionally, configure the analog watchdog parameters (channels
00125         monitored, thresholds, ...)
00126         using function HAL_ADC_AnalogWDGConfig().
00127
00128      *** Execution of ADC conversions ***
00129      ====================================
00130      [..]
00131
00132     (#) Optionally, perform an automatic ADC calibration to improve the
00133         conversion accuracy
00134         using function HAL_ADCEx_Calibration_Start().
00135
00136     (#) ADC driver can be used among three modes: polling, interruption,
00137         transfer by DMA.
00138
00139         (++) ADC conversion by polling:
00140           (+++) Activate the ADC peripheral and start conversions
00141                 using function HAL_ADC_Start()
00142           (+++) Wait for ADC conversion completion
00143                 using function HAL_ADC_PollForConversion()
00144           (+++) Retrieve conversion results
00145                 using function HAL_ADC_GetValue()
00146           (+++) Stop conversion and disable the ADC peripheral
00147                 using function HAL_ADC_Stop()
00148
00149         (++) ADC conversion by interruption:
00150           (+++) Activate the ADC peripheral and start conversions
00151                 using function HAL_ADC_Start_IT()
00152           (+++) Wait for ADC conversion completion by call of function
00153                 HAL_ADC_ConvCpltCallback()
00154                 (this function must be implemented in user program)
00155           (+++) Retrieve conversion results
00156                 using function HAL_ADC_GetValue()
00157           (+++) Stop conversion and disable the ADC peripheral
00158                 using function HAL_ADC_Stop_IT()
00159
00160         (++) ADC conversion with transfer by DMA:
00161           (+++) Activate the ADC peripheral and start conversions
00162                 using function HAL_ADC_Start_DMA()
00163           (+++) Wait for ADC conversion completion by call of function
00164                 HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
00165                 (these functions must be implemented in user program)
00166           (+++) Conversion results are automatically transferred by DMA into
00167                 destination variable address.
00168           (+++) Stop conversion and disable the ADC peripheral
00169                 using function HAL_ADC_Stop_DMA()
00170
00171      [..]
00172
00173     (@) Callback functions must be implemented in user program:
00174       (+@) HAL_ADC_ErrorCallback()
00175       (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
00176       (+@) HAL_ADC_ConvCpltCallback()
00177       (+@) HAL_ADC_ConvHalfCpltCallback
00178
00179      *** Deinitialization of ADC ***
00180      ============================================================
00181      [..]
00182
00183     (#) Disable the ADC interface
00184       (++) ADC clock can be hard reset and disabled at RCC top level.
00185         (++) Hard reset of ADC peripherals
00186              using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
00187         (++) ADC clock disable
00188              using the equivalent macro/functions as configuration step.
00189              (+++) Example:
00190                    Into HAL_ADC_MspDeInit() (recommended code location) or with
00191                    other device clock parameters configuration:
00192                (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14;
00193                (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock)
00194                (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
00195
00196     (#) ADC pins configuration
00197          (++) Disable the clock for the ADC GPIOs
00198               using macro __HAL_RCC_GPIOx_CLK_DISABLE()
00199
00200     (#) Optionally, in case of usage of ADC with interruptions:
00201          (++) Disable the NVIC for ADC
00202               using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
00203
00204     (#) Optionally, in case of usage of DMA:
00205          (++) Deinitialize the DMA
00206               using function HAL_DMA_Init().
00207          (++) Disable the NVIC for DMA
00208               using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
00209
00210     [..]
00211
00212     *** Callback registration ***
00213     =============================================
00214     [..]
00215
00216      The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
00217      allows the user to configure dynamically the driver callbacks.
00218      Use Functions @ref HAL_ADC_RegisterCallback()
00219      to register an interrupt callback.
00220     [..]
00221
00222      Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks:
00223        (+) ConvCpltCallback               : ADC conversion complete callback
00224        (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
00225        (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
00226        (+) ErrorCallback                  : ADC error callback
00227        (+) InjectedConvCpltCallback       : ADC group injected conversion complete callback
00228        (+) InjectedQueueOverflowCallback  : ADC group injected context queue overflow callback
00229        (+) LevelOutOfWindow2Callback      : ADC analog watchdog 2 callback
00230        (+) LevelOutOfWindow3Callback      : ADC analog watchdog 3 callback
00231        (+) EndOfSamplingCallback          : ADC end of sampling callback
00232        (+) MspInitCallback                : ADC Msp Init callback
00233        (+) MspDeInitCallback              : ADC Msp DeInit callback
00234      This function takes as parameters the HAL peripheral handle, the Callback ID
00235      and a pointer to the user callback function.
00236     [..]
00237
00238      Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default
00239      weak function.
00240     [..]
00241
00242      @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
00243      and the Callback ID.
00244      This function allows to reset following callbacks:
00245        (+) ConvCpltCallback               : ADC conversion complete callback
00246        (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
00247        (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
00248        (+) ErrorCallback                  : ADC error callback
00249        (+) InjectedConvCpltCallback       : ADC group injected conversion complete callback
00250        (+) InjectedQueueOverflowCallback  : ADC group injected context queue overflow callback
00251        (+) LevelOutOfWindow2Callback      : ADC analog watchdog 2 callback
00252        (+) LevelOutOfWindow3Callback      : ADC analog watchdog 3 callback
00253        (+) EndOfSamplingCallback          : ADC end of sampling callback
00254        (+) MspInitCallback                : ADC Msp Init callback
00255        (+) MspDeInitCallback              : ADC Msp DeInit callback
00256      [..]
00257
00258      By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET
00259      all callbacks are set to the corresponding weak functions:
00260      examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback().
00261      Exception done for MspInit and MspDeInit functions that are
00262      reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when
00263      these callbacks are null (not registered beforehand).
00264     [..]
00265
00266      If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit()
00267      keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
00268      [..]
00269
00270      Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only.
00271      Exception done MspInit/MspDeInit functions that can be registered/unregistered
00272      in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state,
00273      thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00274     [..]
00275
00276      Then, the user first registers the MspInit/MspDeInit user callbacks
00277      using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit()
00278      or @ref HAL_ADC_Init() function.
00279      [..]
00280
00281      When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
00282      not defined, the callback registration feature is not available and all callbacks
00283      are set to the corresponding weak functions.
00284
00285   @endverbatim
00286   ******************************************************************************
00287   * @attention
00288   *
00289   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00290   * All rights reserved.</center></h2>
00291   *
00292   * This software component is licensed by ST under BSD 3-Clause license,
00293   * the "License"; You may not use this file except in compliance with the
00294   * License. You may obtain a copy of the License at:
00295   *                        opensource.org/licenses/BSD-3-Clause
00296   *
00297   ******************************************************************************
00298   */
00299
00300 /* Includes ------------------------------------------------------------------*/
00301 #include "stm32wbxx_hal.h"
00302
00303 /** @addtogroup STM32WBxx_HAL_Driver
00304   * @{
00305   */
00306
00307 /** @defgroup ADC ADC
00308   * @brief ADC HAL module driver
00309   * @{
00310   */
00311
00312 #ifdef HAL_ADC_MODULE_ENABLED
00313
00314 /* Private typedef -----------------------------------------------------------*/
00315 /* Private define ------------------------------------------------------------*/
00316
00317 /** @defgroup ADC_Private_Constants ADC Private Constants
00318   * @{
00319   */
00320
00321 #define ADC_CFGR_FIELDS_1  ((ADC_CFGR_RES    | ADC_CFGR_ALIGN   |\
00322                              ADC_CFGR_CONT   | ADC_CFGR_OVRMOD  |\
00323                              ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\
00324                              ADC_CFGR_EXTEN  | ADC_CFGR_EXTSEL))   /*!< ADC_CFGR fields of parameters that can be updated
00325                                                                         when no regular conversion is on-going */
00326
00327 /* Timeout values for ADC operations (enable settling time,                   */
00328 /*   disable settling time, ...).                                             */
00329 /*   Values defined to be higher than worst cases: low clock frequency,       */
00330 /*   maximum prescalers.                                                      */
00331 #define ADC_ENABLE_TIMEOUT              (2UL)    /*!< ADC enable time-out value  */
00332 #define ADC_DISABLE_TIMEOUT             (2UL)    /*!< ADC disable time-out value */
00333
00334 /* Timeout to wait for current conversion on going to be completed.           */
00335 /* Timeout fixed to longest ADC conversion possible, for 1 channel:           */
00336 /*   - maximum sampling time (640.5 adc_clk)                                  */
00337 /*   - ADC resolution (Tsar 12 bits= 12.5 adc_clk)                            */
00338 /*   - System clock / ADC clock <= 4096 (hypothesis of maximum clock ratio)   */
00339 /*   - ADC oversampling ratio 256                                             */
00340 /*   Calculation: 653 * 4096 * 256 CPU clock cycles max                       */
00341 /* Unit: cycles of CPU clock.                                                 */
00342 #define ADC_CONVERSION_TIME_MAX_CPU_CYCLES (653UL * 4096UL * 256UL)  /*!< ADC conversion completion time-out value */
00343
00344
00345 /**
00346   * @}
00347   */
00348
00349 /* Private macro -------------------------------------------------------------*/
00350 /* Private variables ---------------------------------------------------------*/
00351 /* Private function prototypes -----------------------------------------------*/
00352 /* Exported functions --------------------------------------------------------*/
00353
00354 /** @defgroup ADC_Exported_Functions ADC Exported Functions
00355   * @{
00356   */
00357
00358 /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
00359   * @brief    ADC Initialization and Configuration functions
00360   *
00361 @verbatim
00362  ===============================================================================
00363               ##### Initialization and de-initialization functions #####
00364  ===============================================================================
00365     [..]  This section provides functions allowing to:
00366       (+) Initialize and configure the ADC.
00367       (+) De-initialize the ADC.
00368 @endverbatim
00369   * @{
00370   */
00371
00372 /**
00373   * @brief  Initialize the ADC peripheral and regular group according to
00374   *         parameters specified in structure "ADC_InitTypeDef".
00375   * @note   As prerequisite, ADC clock must be configured at RCC top level
00376   *         (refer to description of RCC configuration for ADC
00377   *         in header of this file).
00378   * @note   Possibility to update parameters on the fly:
00379   *         This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
00380   *         coming from ADC state reset. Following calls to this function can
00381   *         be used to reconfigure some parameters of ADC_InitTypeDef
00382   *         structure on the fly, without modifying MSP configuration. If ADC
00383   *         MSP has to be modified again, HAL_ADC_DeInit() must be called
00384   *         before HAL_ADC_Init().
00385   *         The setting of these parameters is conditioned to ADC state.
00386   *         For parameters constraints, see comments of structure
00387   *         "ADC_InitTypeDef".
00388   * @note   This function configures the ADC within 2 scopes: scope of entire
00389   *         ADC and scope of regular group. For parameters details, see comments
00390   *         of structure "ADC_InitTypeDef".
00391   * @param hadc ADC handle
00392   * @retval HAL status
00393   */
00394 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
00395 {
00396   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
00397   uint32_t tmpCFGR;
00398   uint32_t tmp_adc_reg_is_conversion_on_going;
00399   __IO uint32_t wait_loop_index = 0UL;
00400   uint32_t tmp_adc_is_conversion_on_going_regular;
00401   uint32_t tmp_adc_is_conversion_on_going_injected;
00402
00403   /* Check ADC handle */
00404   if (hadc == NULL)
00405   {
00406     return HAL_ERROR;
00407   }
00408
00409   /* Check the parameters */
00410   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00411   assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
00412   assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
00413   assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
00414   assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
00415   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
00416   assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
00417   assert_param(IS_ADC_EXTTRIG(hadc, hadc->Init.ExternalTrigConv));
00418   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
00419   assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
00420   assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
00421   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
00422   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
00423
00424   if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
00425   {
00426     assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
00427     assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
00428
00429     if (hadc->Init.DiscontinuousConvMode == ENABLE)
00430     {
00431       assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
00432     }
00433   }
00434
00435   /* DISCEN and CONT bits cannot be set at the same time */
00436   assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
00437
00438   /* Actions performed only if ADC is coming from state reset:                */
00439   /* - Initialization of ADC MSP                                              */
00440   if (hadc->State == HAL_ADC_STATE_RESET)
00441   {
00442 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
00443     /* Init the ADC Callback settings */
00444     hadc->ConvCpltCallback              = HAL_ADC_ConvCpltCallback;                 /* Legacy weak callback */
00445     hadc->ConvHalfCpltCallback          = HAL_ADC_ConvHalfCpltCallback;             /* Legacy weak callback */
00446     hadc->LevelOutOfWindowCallback      = HAL_ADC_LevelOutOfWindowCallback;         /* Legacy weak callback */
00447     hadc->ErrorCallback                 = HAL_ADC_ErrorCallback;                    /* Legacy weak callback */
00448     hadc->InjectedConvCpltCallback      = HAL_ADCEx_InjectedConvCpltCallback;       /* Legacy weak callback */
00449     hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback;  /* Legacy weak callback */
00450     hadc->LevelOutOfWindow2Callback     = HAL_ADCEx_LevelOutOfWindow2Callback;      /* Legacy weak callback */
00451     hadc->LevelOutOfWindow3Callback     = HAL_ADCEx_LevelOutOfWindow3Callback;      /* Legacy weak callback */
00452     hadc->EndOfSamplingCallback         = HAL_ADCEx_EndOfSamplingCallback;          /* Legacy weak callback */
00453
00454     if (hadc->MspInitCallback == NULL)
00455     {
00456       hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit  */
00457     }
00458
00459     /* Init the low level hardware */
00460     hadc->MspInitCallback(hadc);
00461 #else
00462     /* Init the low level hardware */
00463     HAL_ADC_MspInit(hadc);
00464 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
00465
00466     /* Set ADC error code to none */
00467     ADC_CLEAR_ERRORCODE(hadc);
00468
00469     /* Initialize Lock */
00470     hadc->Lock = HAL_UNLOCKED;
00471   }
00472
00473   /* - Exit from deep-power-down mode and ADC voltage regulator enable        */
00474   if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL)
00475   {
00476     /* Disable ADC deep power down mode */
00477     LL_ADC_DisableDeepPowerDown(hadc->Instance);
00478
00479     /* System was in deep power down mode, calibration must
00480      be relaunched or a previously saved calibration factor
00481      re-applied once the ADC voltage regulator is enabled */
00482   }
00483
00484   if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
00485   {
00486     /* Enable ADC internal voltage regulator */
00487     LL_ADC_EnableInternalRegulator(hadc->Instance);
00488
00489     /* Note: Variable divided by 2 to compensate partially              */
00490     /*       CPU processing cycles, scaling in us split to not          */
00491     /*       exceed 32 bits register capacity and handle low frequency. */
00492     wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
00493     while (wait_loop_index != 0UL)
00494     {
00495       wait_loop_index--;
00496     }
00497   }
00498
00499   /* Verification that ADC voltage regulator is correctly enabled, whether    */
00500   /* or not ADC is coming from state reset (if any potential problem of       */
00501   /* clocking, voltage regulator would not be enabled).                       */
00502   if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
00503   {
00504     /* Update ADC state machine to error */
00505     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
00506
00507     /* Set ADC error code to ADC peripheral internal error */
00508     SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
00509
00510     tmp_hal_status = HAL_ERROR;
00511   }
00512
00513   /* Configuration of ADC parameters if previous preliminary actions are      */
00514   /* correctly completed and if there is no conversion on going on regular    */
00515   /* group (ADC may already be enabled at this point if HAL_ADC_Init() is     */
00516   /* called to update a parameter on the fly).                                */
00517   tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
00518
00519   if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
00520       && (tmp_adc_reg_is_conversion_on_going == 0UL)
00521      )
00522   {
00523     /* Set ADC state */
00524     ADC_STATE_CLR_SET(hadc->State,
00525                       HAL_ADC_STATE_REG_BUSY,
00526                       HAL_ADC_STATE_BUSY_INTERNAL);
00527
00528     /* Configuration of common ADC parameters                                 */
00529
00530     /* Parameters update conditioned to ADC state:                            */
00531     /* Parameters that can be updated only when ADC is disabled:              */
00532     /*  - clock configuration                                                 */
00533     if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
00534     {
00535       if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
00536       {
00537         /* Reset configuration of ADC common register CCR:                      */
00538         /*                                                                      */
00539         /*   - ADC clock mode and ACC prescaler (CKMODE and PRESC bits)are set  */
00540         /*     according to adc->Init.ClockPrescaler. It selects the clock      */
00541         /*    source and sets the clock division factor.                        */
00542         /*                                                                      */
00543         /* Some parameters of this register are not reset, since they are set   */
00544         /* by other functions and must be kept in case of usage of this         */
00545         /* function on the fly (update of a parameter of ADC_InitTypeDef        */
00546         /* without needing to reconfigure all other ADC groups/channels         */
00547         /* parameters):                                                         */
00548         /*   - when multimode feature is available, multimode-related           */
00549         /*     parameters: MDMA, DMACFG, DELAY, DUAL (set by API                */
00550         /*     HAL_ADCEx_MultiModeConfigChannel() )                             */
00551         /*   - internal measurement paths: Vbat, temperature sensor, Vref       */
00552         /*     (set into HAL_ADC_ConfigChannel() or                             */
00553         /*     HAL_ADCEx_InjectedConfigChannel() )                              */
00554         LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler);
00555       }
00556     }
00557
00558     /* Configuration of ADC:                                                  */
00559     /*  - resolution                               Init.Resolution            */
00560     /*  - data alignment                           Init.DataAlign             */
00561     /*  - external trigger to start conversion     Init.ExternalTrigConv      */
00562     /*  - external trigger polarity                Init.ExternalTrigConvEdge  */
00563     /*  - continuous conversion mode               Init.ContinuousConvMode    */
00564     /*  - overrun                                  Init.Overrun               */
00565     /*  - discontinuous mode                       Init.DiscontinuousConvMode */
00566     /*  - discontinuous mode channel count         Init.NbrOfDiscConversion   */
00567     tmpCFGR  = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)           |
00568                 hadc->Init.Overrun                                                     |
00569                 hadc->Init.DataAlign                                                   |
00570                 hadc->Init.Resolution                                                  |
00571                 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
00572
00573     if (hadc->Init.DiscontinuousConvMode == ENABLE)
00574     {
00575       tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
00576     }
00577
00578     /* Enable external trigger if trigger selection is different of software  */
00579     /* start.                                                                 */
00580     /* Note: This configuration keeps the hardware feature of parameter       */
00581     /*       ExternalTrigConvEdge "trigger edge none" equivalent to           */
00582     /*       software start.                                                  */
00583     if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
00584     {
00585       tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
00586                   | hadc->Init.ExternalTrigConvEdge
00587                  );
00588     }
00589
00590     /* Update Configuration Register CFGR */
00591     MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR);
00592
00593     /* Parameters update conditioned to ADC state:                            */
00594     /* Parameters that can be updated when ADC is disabled or enabled without */
00595     /* conversion on going on regular and injected groups:                    */
00596     /*  - DMA continuous request          Init.DMAContinuousRequests          */
00597     /*  - LowPowerAutoWait feature        Init.LowPowerAutoWait               */
00598     /*  - Oversampling parameters         Init.Oversampling                   */
00599     tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
00600     tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
00601     if ((tmp_adc_is_conversion_on_going_regular == 0UL)
00602         && (tmp_adc_is_conversion_on_going_injected == 0UL)
00603        )
00604     {
00605       tmpCFGR = (ADC_CFGR_DFSDM(hadc)                                            |
00606                  ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait)        |
00607                  ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
00608
00609       MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR);
00610
00611       if (hadc->Init.OversamplingMode == ENABLE)
00612       {
00613         assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio));
00614         assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift));
00615         assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode));
00616         assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset));
00617
00618         /* Configuration of Oversampler:                                      */
00619         /*  - Oversampling Ratio                                              */
00620         /*  - Right bit shift                                                 */
00621         /*  - Triggered mode                                                  */
00622         /*  - Oversampling mode (continued/resumed)                           */
00623         MODIFY_REG(hadc->Instance->CFGR2,
00624                    ADC_CFGR2_OVSR  |
00625                    ADC_CFGR2_OVSS  |
00626                    ADC_CFGR2_TROVS |
00627                    ADC_CFGR2_ROVSM,
00628                    ADC_CFGR2_ROVSE                       |
00629                    hadc->Init.Oversampling.Ratio         |
00630                    hadc->Init.Oversampling.RightBitShift |
00631                    hadc->Init.Oversampling.TriggeredMode |
00632                    hadc->Init.Oversampling.OversamplingStopReset
00633                   );
00634       }
00635       else
00636       {
00637         /* Disable ADC oversampling scope on ADC group regular */
00638         CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
00639       }
00640
00641     }
00642
00643     /* Configuration of regular group sequencer:                              */
00644     /* - if scan mode is disabled, regular channels sequence length is set to */
00645     /*   0x00: 1 channel converted (channel on regular rank 1)                */
00646     /*   Parameter "NbrOfConversion" is discarded.                            */
00647     /*   Note: Scan mode is not present by hardware on this device, but       */
00648     /*   emulated by software for alignment over all STM32 devices.           */
00649     /* - if scan mode is enabled, regular channels sequence length is set to  */
00650     /*   parameter "NbrOfConversion".                                         */
00651
00652     if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
00653     {
00654       /* Set number of ranks in regular group sequencer */
00655       MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
00656     }
00657     else
00658     {
00659       CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
00660     }
00661
00662     /* Initialize the ADC state */
00663     /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
00664     ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
00665   }
00666   else
00667   {
00668     /* Update ADC state machine to error */
00669     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
00670
00671     tmp_hal_status = HAL_ERROR;
00672   }
00673
00674   /* Return function status */
00675   return tmp_hal_status;
00676 }
00677
00678 /**
00679   * @brief  Deinitialize the ADC peripheral registers to their default reset
00680   *         values, with deinitialization of the ADC MSP.
00681   * @note   For devices with several ADCs: reset of ADC common registers is done
00682   *         only if all ADCs sharing the same common group are disabled.
00683   *         (function "HAL_ADC_MspDeInit()" is also called under the same conditions:
00684   *         all ADC instances use the same core clock at RCC level, disabling
00685   *         the core clock reset all ADC instances).
00686   *         If this is not the case, reset of these common parameters reset is
00687   *         bypassed without error reporting: it can be the intended behavior in
00688   *         case of reset of a single ADC while the other ADCs sharing the same
00689   *         common group is still running.
00690   * @note   By default, HAL_ADC_DeInit() set ADC in mode deep power-down:
00691   *         this saves more power by reducing leakage currents
00692   *         and is particularly interesting before entering MCU low-power modes.
00693   * @param hadc ADC handle
00694   * @retval HAL status
00695   */
00696 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
00697 {
00698   HAL_StatusTypeDef tmp_hal_status;
00699
00700   /* Check ADC handle */
00701   if (hadc == NULL)
00702   {
00703     return HAL_ERROR;
00704   }
00705
00706   /* Check the parameters */
00707   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00708
00709   /* Set ADC state */
00710   SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
00711
00712   /* Stop potential conversion on going */
00713   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
00714
00715   /* Disable ADC peripheral if conversions are effectively stopped            */
00716   /* Flush register JSQR: reset the queue sequencer when injected             */
00717   /* queue sequencer is enabled and ADC disabled.                             */
00718   /* The software and hardware triggers of the injected sequence are both     */
00719   /* internally disabled just after the completion of the last valid          */
00720   /* injected sequence.                                                       */
00721   SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM);
00722
00723   /* Disable ADC peripheral if conversions are effectively stopped */
00724   if (tmp_hal_status == HAL_OK)
00725   {
00726     /* Disable the ADC peripheral */
00727     tmp_hal_status = ADC_Disable(hadc);
00728
00729     /* Check if ADC is effectively disabled */
00730     if (tmp_hal_status == HAL_OK)
00731     {
00732       /* Change ADC state */
00733       hadc->State = HAL_ADC_STATE_READY;
00734     }
00735   }
00736
00737   /* Note: HAL ADC deInit is done independently of ADC conversion stop        */
00738   /*       and disable return status. In case of status fail, attempt to      */
00739   /*       perform deinitialization anyway and it is up user code in          */
00740   /*       in HAL_ADC_MspDeInit() to reset the ADC peripheral using           */
00741   /*       system RCC hard reset.                                             */
00742
00743   /* ========== Reset ADC registers ========== */
00744   /* Reset register IER */
00745   __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3  | ADC_IT_AWD2 | ADC_IT_AWD1 |
00746                               ADC_IT_JQOVF | ADC_IT_OVR  |
00747                               ADC_IT_JEOS  | ADC_IT_JEOC |
00748                               ADC_IT_EOS   | ADC_IT_EOC  |
00749                               ADC_IT_EOSMP | ADC_IT_RDY));
00750
00751   /* Reset register ISR */
00752   __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3  | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
00753                               ADC_FLAG_JQOVF | ADC_FLAG_OVR  |
00754                               ADC_FLAG_JEOS  | ADC_FLAG_JEOC |
00755                               ADC_FLAG_EOS   | ADC_FLAG_EOC  |
00756                               ADC_FLAG_EOSMP | ADC_FLAG_RDY));
00757
00758   /* Reset register CR */
00759   /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART,
00760      ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set":
00761      no direct reset applicable.
00762      Update CR register to reset value where doable by software */
00763   CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
00764   SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
00765
00766   /* Reset register CFGR */
00767   CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_FIELDS);
00768   SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
00769
00770   /* Reset register CFGR2 */
00771   CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM  | ADC_CFGR2_TROVS   | ADC_CFGR2_OVSS |
00772             ADC_CFGR2_OVSR  | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE);
00773
00774   /* Reset register SMPR1 */
00775   CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_FIELDS);
00776
00777   /* Reset register SMPR2 */
00778   CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 |
00779             ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 |
00780             ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10);
00781
00782   /* Reset register TR1 */
00783   CLEAR_BIT(hadc->Instance->TR1, ADC_TR1_HT1 | ADC_TR1_LT1);
00784
00785   /* Reset register TR2 */
00786   CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2);
00787
00788   /* Reset register TR3 */
00789   CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3);
00790
00791   /* Reset register SQR1 */
00792   CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 |
00793             ADC_SQR1_SQ1 | ADC_SQR1_L);
00794
00795   /* Reset register SQR2 */
00796   CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 |
00797             ADC_SQR2_SQ6 | ADC_SQR2_SQ5);
00798
00799   /* Reset register SQR3 */
00800   CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 |
00801             ADC_SQR3_SQ11 | ADC_SQR3_SQ10);
00802
00803   /* Reset register SQR4 */
00804   CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
00805
00806   /* Register JSQR was reset when the ADC was disabled */
00807
00808   /* Reset register DR */
00809   /* bits in access mode read only, no direct reset applicable*/
00810
00811   /* Reset register OFR1 */
00812   CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
00813   /* Reset register OFR2 */
00814   CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
00815   /* Reset register OFR3 */
00816   CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
00817   /* Reset register OFR4 */
00818   CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
00819
00820   /* Reset registers JDR1, JDR2, JDR3, JDR4 */
00821   /* bits in access mode read only, no direct reset applicable*/
00822
00823   /* Reset register AWD2CR */
00824   CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
00825
00826   /* Reset register AWD3CR */
00827   CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
00828
00829   /* Reset register DIFSEL */
00830   CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL);
00831
00832   /* Reset register CALFACT */
00833   CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
00834
00835
00836   /* ========== Reset common ADC registers ========== */
00837
00838   /* Software is allowed to change common parameters only when all the other
00839      ADCs are disabled.   */
00840   if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
00841   {
00842     /* Reset configuration of ADC common register CCR:
00843       - clock mode: CKMODE, PRESCEN
00844       - multimode related parameters (when this feature is available): MDMA,
00845         DMACFG, DELAY, DUAL (set by HAL_ADCEx_MultiModeConfigChannel() API)
00846       - internal measurement paths: Vbat, temperature sensor, Vref (set into
00847         HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() )
00848     */
00849     ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc);
00850   }
00851
00852   /* DeInit the low level hardware.
00853
00854      For example:
00855     __HAL_RCC_ADC_FORCE_RESET();
00856     __HAL_RCC_ADC_RELEASE_RESET();
00857     __HAL_RCC_ADC_CLK_DISABLE();
00858
00859     Keep in mind that all ADCs use the same clock: disabling
00860     the clock will reset all ADCs.
00861
00862   */
00863 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
00864   if (hadc->MspDeInitCallback == NULL)
00865   {
00866     hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit  */
00867   }
00868
00869   /* DeInit the low level hardware: RCC clock, NVIC */
00870   hadc->MspDeInitCallback(hadc);
00871 #else
00872   /* DeInit the low level hardware: RCC clock, NVIC */
00873   HAL_ADC_MspDeInit(hadc);
00874 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
00875
00876   /* Set ADC error code to none */
00877   ADC_CLEAR_ERRORCODE(hadc);
00878
00879   /* Reset injected channel configuration parameters */
00880   hadc->InjectionConfig.ContextQueue = 0;
00881   hadc->InjectionConfig.ChannelCount = 0;
00882
00883   /* Set ADC state */
00884   hadc->State = HAL_ADC_STATE_RESET;
00885
00886   /* Process unlocked */
00887   __HAL_UNLOCK(hadc);
00888
00889   /* Return function status */
00890   return tmp_hal_status;
00891 }
00892
00893 /**
00894   * @brief  Initialize the ADC MSP.
00895   * @param hadc ADC handle
00896   * @retval None
00897   */
00898 __weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc)
00899 {
00900   /* Prevent unused argument(s) compilation warning */
00901   UNUSED(hadc);
00902
00903   /* NOTE : This function should not be modified. When the callback is needed,
00904             function HAL_ADC_MspInit must be implemented in the user file.
00905    */
00906 }
00907
00908 /**
00909   * @brief  DeInitialize the ADC MSP.
00910   * @param hadc ADC handle
00911   * @note   All ADC instances use the same core clock at RCC level, disabling
00912   *         the core clock reset all ADC instances).
00913   * @retval None
00914   */
00915 __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)
00916 {
00917   /* Prevent unused argument(s) compilation warning */
00918   UNUSED(hadc);
00919
00920   /* NOTE : This function should not be modified. When the callback is needed,
00921             function HAL_ADC_MspDeInit must be implemented in the user file.
00922    */
00923 }
00924
00925 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
00926 /**
00927   * @brief  Register a User ADC Callback
00928   *         To be used instead of the weak predefined callback
00929   * @param  hadc Pointer to a ADC_HandleTypeDef structure that contains
00930   *                the configuration information for the specified ADC.
00931   * @param  CallbackID ID of the callback to be registered
00932   *         This parameter can be one of the following values:
00933   *          @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID      ADC conversion complete callback ID
00934   *          @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID          ADC conversion DMA half-transfer callback ID
00935   *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID    ADC analog watchdog 1 callback ID
00936   *          @arg @ref HAL_ADC_ERROR_CB_ID                    ADC error callback ID
00937   *          @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID  ADC group injected conversion complete callback ID
00938   *          @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID        ADC group injected context queue overflow callback ID
00939   *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID    ADC analog watchdog 2 callback ID
00940   *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID    ADC analog watchdog 3 callback ID
00941   *          @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID          ADC end of sampling callback ID
00942   *          @arg @ref HAL_ADC_MSPINIT_CB_ID                  ADC Msp Init callback ID
00943   *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID                ADC Msp DeInit callback ID
00944   *          @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
00945   *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
00946   * @param  pCallback pointer to the Callback function
00947   * @retval HAL status
00948   */
00949 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
00950 {
00951   HAL_StatusTypeDef status = HAL_OK;
00952
00953   if (pCallback == NULL)
00954   {
00955     /* Update the error code */
00956     hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
00957
00958     return HAL_ERROR;
00959   }
00960
00961   if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
00962   {
00963     switch (CallbackID)
00964     {
00965       case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
00966         hadc->ConvCpltCallback = pCallback;
00967         break;
00968
00969       case HAL_ADC_CONVERSION_HALF_CB_ID :
00970         hadc->ConvHalfCpltCallback = pCallback;
00971         break;
00972
00973       case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
00974         hadc->LevelOutOfWindowCallback = pCallback;
00975         break;
00976
00977       case HAL_ADC_ERROR_CB_ID :
00978         hadc->ErrorCallback = pCallback;
00979         break;
00980
00981       case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
00982         hadc->InjectedConvCpltCallback = pCallback;
00983         break;
00984
00985       case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID :
00986         hadc->InjectedQueueOverflowCallback = pCallback;
00987         break;
00988
00989       case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
00990         hadc->LevelOutOfWindow2Callback = pCallback;
00991         break;
00992
00993       case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
00994         hadc->LevelOutOfWindow3Callback = pCallback;
00995         break;
00996
00997       case HAL_ADC_END_OF_SAMPLING_CB_ID :
00998         hadc->EndOfSamplingCallback = pCallback;
00999         break;
01000
01001       case HAL_ADC_MSPINIT_CB_ID :
01002         hadc->MspInitCallback = pCallback;
01003         break;
01004
01005       case HAL_ADC_MSPDEINIT_CB_ID :
01006         hadc->MspDeInitCallback = pCallback;
01007         break;
01008
01009       default :
01010         /* Update the error code */
01011         hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
01012
01013         /* Return error status */
01014         status = HAL_ERROR;
01015         break;
01016     }
01017   }
01018   else if (HAL_ADC_STATE_RESET == hadc->State)
01019   {
01020     switch (CallbackID)
01021     {
01022       case HAL_ADC_MSPINIT_CB_ID :
01023         hadc->MspInitCallback = pCallback;
01024         break;
01025
01026       case HAL_ADC_MSPDEINIT_CB_ID :
01027         hadc->MspDeInitCallback = pCallback;
01028         break;
01029
01030       default :
01031         /* Update the error code */
01032         hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
01033
01034         /* Return error status */
01035         status = HAL_ERROR;
01036         break;
01037     }
01038   }
01039   else
01040   {
01041     /* Update the error code */
01042     hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
01043
01044     /* Return error status */
01045     status =  HAL_ERROR;
01046   }
01047
01048   return status;
01049 }
01050
01051 /**
01052   * @brief  Unregister a ADC Callback
01053   *         ADC callback is redirected to the weak predefined callback
01054   * @param  hadc Pointer to a ADC_HandleTypeDef structure that contains
01055   *                the configuration information for the specified ADC.
01056   * @param  CallbackID ID of the callback to be unregistered
01057   *         This parameter can be one of the following values:
01058   *          @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID      ADC conversion complete callback ID
01059   *          @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID          ADC conversion DMA half-transfer callback ID
01060   *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID    ADC analog watchdog 1 callback ID
01061   *          @arg @ref HAL_ADC_ERROR_CB_ID                    ADC error callback ID
01062   *          @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID  ADC group injected conversion complete callback ID
01063   *          @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID        ADC group injected context queue overflow callback ID
01064   *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID    ADC analog watchdog 2 callback ID
01065   *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID    ADC analog watchdog 3 callback ID
01066   *          @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID          ADC end of sampling callback ID
01067   *          @arg @ref HAL_ADC_MSPINIT_CB_ID                  ADC Msp Init callback ID
01068   *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID                ADC Msp DeInit callback ID
01069   *          @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
01070   *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
01071   * @retval HAL status
01072   */
01073 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
01074 {
01075   HAL_StatusTypeDef status = HAL_OK;
01076
01077   if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
01078   {
01079     switch (CallbackID)
01080     {
01081       case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
01082         hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
01083         break;
01084
01085       case HAL_ADC_CONVERSION_HALF_CB_ID :
01086         hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
01087         break;
01088
01089       case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
01090         hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
01091         break;
01092
01093       case HAL_ADC_ERROR_CB_ID :
01094         hadc->ErrorCallback = HAL_ADC_ErrorCallback;
01095         break;
01096
01097       case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
01098         hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback;
01099         break;
01100
01101       case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID :
01102         hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback;
01103         break;
01104
01105       case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
01106         hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback;
01107         break;
01108
01109       case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
01110         hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback;
01111         break;
01112
01113       case HAL_ADC_END_OF_SAMPLING_CB_ID :
01114         hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback;
01115         break;
01116
01117       case HAL_ADC_MSPINIT_CB_ID :
01118         hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit              */
01119         break;
01120
01121       case HAL_ADC_MSPDEINIT_CB_ID :
01122         hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit            */
01123         break;
01124
01125       default :
01126         /* Update the error code */
01127         hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
01128
01129         /* Return error status */
01130         status =  HAL_ERROR;
01131         break;
01132     }
01133   }
01134   else if (HAL_ADC_STATE_RESET == hadc->State)
01135   {
01136     switch (CallbackID)
01137     {
01138       case HAL_ADC_MSPINIT_CB_ID :
01139         hadc->MspInitCallback = HAL_ADC_MspInit;                   /* Legacy weak MspInit              */
01140         break;
01141
01142       case HAL_ADC_MSPDEINIT_CB_ID :
01143         hadc->MspDeInitCallback = HAL_ADC_MspDeInit;               /* Legacy weak MspDeInit            */
01144         break;
01145
01146       default :
01147         /* Update the error code */
01148         hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
01149
01150         /* Return error status */
01151         status =  HAL_ERROR;
01152         break;
01153     }
01154   }
01155   else
01156   {
01157     /* Update the error code */
01158     hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
01159
01160     /* Return error status */
01161     status =  HAL_ERROR;
01162   }
01163
01164   return status;
01165 }
01166
01167 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
01168
01169 /**
01170   * @}
01171   */
01172
01173 /** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions
01174   * @brief    ADC IO operation functions
01175   *
01176 @verbatim
01177  ===============================================================================
01178                       ##### IO operation functions #####
01179  ===============================================================================
01180     [..]  This section provides functions allowing to:
01181       (+) Start conversion of regular group.
01182       (+) Stop conversion of regular group.
01183       (+) Poll for conversion complete on regular group.
01184       (+) Poll for conversion event.
01185       (+) Get result of regular channel conversion.
01186       (+) Start conversion of regular group and enable interruptions.
01187       (+) Stop conversion of regular group and disable interruptions.
01188       (+) Handle ADC interrupt request
01189       (+) Start conversion of regular group and enable DMA transfer.
01190       (+) Stop conversion of regular group and disable ADC DMA transfer.
01191 @endverbatim
01192   * @{
01193   */
01194
01195 /**
01196   * @brief  Enable ADC, start conversion of regular group.
01197   * @note   Interruptions enabled in this function: None.
01198   * @param hadc ADC handle
01199   * @retval HAL status
01200   */
01201 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
01202 {
01203   HAL_StatusTypeDef tmp_hal_status;
01204
01205   /* Check the parameters */
01206   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01207
01208   /* Perform ADC enable and conversion start if no conversion is on going */
01209   if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
01210   {
01211     /* Process locked */
01212     __HAL_LOCK(hadc);
01213
01214     /* Enable the ADC peripheral */
01215     tmp_hal_status = ADC_Enable(hadc);
01216
01217     /* Start conversion if ADC is effectively enabled */
01218     if (tmp_hal_status == HAL_OK)
01219     {
01220       /* Set ADC state                                                        */
01221       /* - Clear state bitfield related to regular group conversion results   */
01222       /* - Set state bitfield related to regular operation                    */
01223       ADC_STATE_CLR_SET(hadc->State,
01224                         HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
01225                         HAL_ADC_STATE_REG_BUSY);
01226
01227       /* Set ADC error code */
01228       /* Check if a conversion is on going on ADC group injected */
01229       if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
01230       {
01231         /* Reset ADC error code fields related to regular conversions only */
01232         CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
01233       }
01234       else
01235       {
01236         /* Reset all ADC error code fields */
01237         ADC_CLEAR_ERRORCODE(hadc);
01238       }
01239
01240       /* Clear ADC group regular conversion flag and overrun flag               */
01241       /* (To ensure of no unknown state from potential previous ADC operations) */
01242       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
01243
01244       /* Process unlocked */
01245       /* Unlock before starting ADC conversions: in case of potential         */
01246       /* interruption, to let the process to ADC IRQ Handler.                 */
01247       __HAL_UNLOCK(hadc);
01248
01249       /* Enable conversion of regular group.                                  */
01250       /* If software start has been selected, conversion starts immediately.  */
01251       /* If external trigger has been selected, conversion will start at next */
01252       /* trigger event.                                                       */
01253       /* Start ADC group regular conversion */
01254       LL_ADC_REG_StartConversion(hadc->Instance);
01255     }
01256     else
01257     {
01258       /* Process unlocked */
01259       __HAL_UNLOCK(hadc);
01260     }
01261   }
01262   else
01263   {
01264     tmp_hal_status = HAL_BUSY;
01265   }
01266
01267   /* Return function status */
01268   return tmp_hal_status;
01269 }
01270
01271 /**
01272   * @brief  Stop ADC conversion of regular group (and injected channels in
01273   *         case of auto_injection mode), disable ADC peripheral.
01274   * @note:  ADC peripheral disable is forcing stop of potential
01275   *         conversion on injected group. If injected group is under use, it
01276   *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
01277   * @param hadc ADC handle
01278   * @retval HAL status.
01279   */
01280 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc)
01281 {
01282   HAL_StatusTypeDef tmp_hal_status;
01283
01284   /* Check the parameters */
01285   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01286
01287   /* Process locked */
01288   __HAL_LOCK(hadc);
01289
01290   /* 1. Stop potential conversion on going, on ADC groups regular and injected */
01291   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
01292
01293   /* Disable ADC peripheral if conversions are effectively stopped */
01294   if (tmp_hal_status == HAL_OK)
01295   {
01296     /* 2. Disable the ADC peripheral */
01297     tmp_hal_status = ADC_Disable(hadc);
01298
01299     /* Check if ADC is effectively disabled */
01300     if (tmp_hal_status == HAL_OK)
01301     {
01302       /* Set ADC state */
01303       ADC_STATE_CLR_SET(hadc->State,
01304                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
01305                         HAL_ADC_STATE_READY);
01306     }
01307   }
01308
01309   /* Process unlocked */
01310   __HAL_UNLOCK(hadc);
01311
01312   /* Return function status */
01313   return tmp_hal_status;
01314 }
01315
01316 /**
01317   * @brief  Wait for regular group conversion to be completed.
01318   * @note   ADC conversion flags EOS (end of sequence) and EOC (end of
01319   *         conversion) are cleared by this function, with an exception:
01320   *         if low power feature "LowPowerAutoWait" is enabled, flags are
01321   *         not cleared to not interfere with this feature until data register
01322   *         is read using function HAL_ADC_GetValue().
01323   * @note   This function cannot be used in a particular setup: ADC configured
01324   *         in DMA mode and polling for end of each conversion (ADC init
01325   *         parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
01326   *         In this case, DMA resets the flag EOC and polling cannot be
01327   *         performed on each conversion. Nevertheless, polling can still
01328   *         be performed on the complete sequence (ADC init
01329   *         parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
01330   * @param hadc ADC handle
01331   * @param Timeout Timeout value in millisecond.
01332   * @retval HAL status
01333   */
01334 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
01335 {
01336   uint32_t tickstart;
01337   uint32_t tmp_Flag_End;
01338
01339   /* Check the parameters */
01340   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01341
01342   /* If end of conversion selected to end of sequence conversions */
01343   if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
01344   {
01345     tmp_Flag_End = ADC_FLAG_EOS;
01346   }
01347   /* If end of conversion selected to end of unitary conversion */
01348   else /* ADC_EOC_SINGLE_CONV */
01349   {
01350     /* Verification that ADC configuration is compliant with polling for      */
01351     /* each conversion:                                                       */
01352     /* Particular case is ADC configured in DMA mode and ADC sequencer with   */
01353     /* several ranks and polling for end of each conversion.                  */
01354     /* For code simplicity sake, this particular case is generalized to       */
01355     /* ADC configured in DMA mode and and polling for end of each conversion. */
01356     if(READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL)
01357     {
01358       /* Update ADC state machine to error */
01359       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
01360
01361       return HAL_ERROR;
01362     }
01363     else
01364     {
01365       tmp_Flag_End = (ADC_FLAG_EOC);
01366     }
01367   }
01368
01369   /* Get tick count */
01370   tickstart = HAL_GetTick();
01371
01372   /* Wait until End of unitary conversion or sequence conversions flag is raised */
01373   while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
01374   {
01375     /* Check if timeout is disabled (set to infinite wait) */
01376     if (Timeout != HAL_MAX_DELAY)
01377     {
01378       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
01379       {
01380         /* Update ADC state machine to timeout */
01381         SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
01382
01383         /* Process unlocked */
01384         __HAL_UNLOCK(hadc);
01385
01386         return HAL_TIMEOUT;
01387       }
01388     }
01389   }
01390
01391   /* Update ADC state machine */
01392   SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
01393
01394   /* Determine whether any further conversion upcoming on group regular       */
01395   /* by external trigger, continuous mode or scan sequence on going.          */
01396   if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
01397       && (hadc->Init.ContinuousConvMode == DISABLE)
01398      )
01399   {
01400     /* Check whether end of sequence is reached */
01401     if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
01402     {
01403       /* Set ADC state */
01404       CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
01405
01406       if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
01407       {
01408         SET_BIT(hadc->State, HAL_ADC_STATE_READY);
01409       }
01410     }
01411   }
01412
01413   /* Clear polled flag */
01414   if (tmp_Flag_End == ADC_FLAG_EOS)
01415   {
01416     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS);
01417   }
01418   else
01419   {
01420     /* Clear end of conversion EOC flag of regular group if low power feature */
01421     /* "LowPowerAutoWait " is disabled, to not interfere with this feature    */
01422     /* until data register is read using function HAL_ADC_GetValue().         */
01423     if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_AUTDLY) == 0UL)
01424     {
01425       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
01426     }
01427   }
01428
01429   /* Return function status */
01430   return HAL_OK;
01431 }
01432
01433 /**
01434   * @brief  Poll for ADC event.
01435   * @param hadc ADC handle
01436   * @param EventType the ADC event type.
01437   *          This parameter can be one of the following values:
01438   *            @arg @ref ADC_EOSMP_EVENT  ADC End of Sampling event
01439   *            @arg @ref ADC_AWD1_EVENT   ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
01440   *            @arg @ref ADC_AWD2_EVENT   ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families)
01441   *            @arg @ref ADC_AWD3_EVENT   ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families)
01442   *            @arg @ref ADC_OVR_EVENT    ADC Overrun event
01443   *            @arg @ref ADC_JQOVF_EVENT  ADC Injected context queue overflow event
01444   * @param Timeout Timeout value in millisecond.
01445   * @note   The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
01446   *         Indeed, the latter is reset only if hadc->Init.Overrun field is set
01447   *         to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten
01448   *         by a new converted data as soon as OVR is cleared.
01449   *         To reset OVR flag once the preserved data is retrieved, the user can resort
01450   *         to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
01451   * @retval HAL status
01452   */
01453 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
01454 {
01455   uint32_t tickstart;
01456
01457   /* Check the parameters */
01458   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01459   assert_param(IS_ADC_EVENT_TYPE(EventType));
01460
01461   /* Get tick count */
01462   tickstart = HAL_GetTick();
01463
01464   /* Check selected event flag */
01465   while (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
01466   {
01467     /* Check if timeout is disabled (set to infinite wait) */
01468     if (Timeout != HAL_MAX_DELAY)
01469     {
01470       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
01471       {
01472         /* Update ADC state machine to timeout */
01473         SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
01474
01475         /* Process unlocked */
01476         __HAL_UNLOCK(hadc);
01477
01478         return HAL_TIMEOUT;
01479       }
01480     }
01481   }
01482
01483   switch (EventType)
01484   {
01485     /* End Of Sampling event */
01486     case ADC_EOSMP_EVENT:
01487       /* Set ADC state */
01488       SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
01489
01490       /* Clear the End Of Sampling flag */
01491       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
01492
01493       break;
01494
01495     /* Analog watchdog (level out of window) event */
01496     /* Note: In case of several analog watchdog enabled, if needed to know      */
01497     /* which one triggered and on which ADCx, test ADC state of analog watchdog */
01498     /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()".        */
01499     /* For example:                                                             */
01500     /*  " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "          */
01501     /*  " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD2) != 0UL) "          */
01502     /*  " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD3) != 0UL) "          */
01503
01504     /* Check analog watchdog 1 flag */
01505     case ADC_AWD_EVENT:
01506       /* Set ADC state */
01507       SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
01508
01509       /* Clear ADC analog watchdog flag */
01510       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
01511
01512       break;
01513
01514     /* Check analog watchdog 2 flag */
01515     case ADC_AWD2_EVENT:
01516       /* Set ADC state */
01517       SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
01518
01519       /* Clear ADC analog watchdog flag */
01520       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
01521
01522       break;
01523
01524     /* Check analog watchdog 3 flag */
01525     case ADC_AWD3_EVENT:
01526       /* Set ADC state */
01527       SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
01528
01529       /* Clear ADC analog watchdog flag */
01530       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
01531
01532       break;
01533
01534     /* Injected context queue overflow event */
01535     case ADC_JQOVF_EVENT:
01536       /* Set ADC state */
01537       SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
01538
01539       /* Set ADC error code to Injected context queue overflow */
01540       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
01541
01542       /* Clear ADC Injected context queue overflow flag */
01543       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
01544
01545       break;
01546
01547     /* Overrun event */
01548     default: /* Case ADC_OVR_EVENT */
01549       /* If overrun is set to overwrite previous data, overrun event is not     */
01550       /* considered as an error.                                                */
01551       /* (cf ref manual "Managing conversions without using the DMA and without */
01552       /* overrun ")                                                             */
01553       if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
01554       {
01555         /* Set ADC state */
01556         SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
01557
01558         /* Set ADC error code to overrun */
01559         SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
01560       }
01561       else
01562       {
01563         /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN
01564            otherwise, data register is potentially overwritten by new converted data as soon
01565            as OVR is cleared. */
01566         __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
01567       }
01568       break;
01569   }
01570
01571   /* Return function status */
01572   return HAL_OK;
01573 }
01574
01575 /**
01576   * @brief  Enable ADC, start conversion of regular group with interruption.
01577   * @note   Interruptions enabled in this function according to initialization
01578   *         setting : EOC (end of conversion), EOS (end of sequence),
01579   *         OVR overrun.
01580   *         Each of these interruptions has its dedicated callback function.
01581   * @note   To guarantee a proper reset of all interruptions once all the needed
01582   *         conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure
01583   *         a correct stop of the IT-based conversions.
01584   * @note   By default, HAL_ADC_Start_IT() does not enable the End Of Sampling
01585   *         interruption. If required (e.g. in case of oversampling with trigger
01586   *         mode), the user must:
01587   *          1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP)
01588   *          2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP)
01589   *          before calling HAL_ADC_Start_IT().
01590   * @param hadc ADC handle
01591   * @retval HAL status
01592   */
01593 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
01594 {
01595   HAL_StatusTypeDef tmp_hal_status;
01596
01597   /* Check the parameters */
01598   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01599
01600   /* Perform ADC enable and conversion start if no conversion is on going */
01601   if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
01602   {
01603     /* Process locked */
01604     __HAL_LOCK(hadc);
01605
01606     /* Enable the ADC peripheral */
01607     tmp_hal_status = ADC_Enable(hadc);
01608
01609     /* Start conversion if ADC is effectively enabled */
01610     if (tmp_hal_status == HAL_OK)
01611     {
01612       /* Set ADC state                                                        */
01613       /* - Clear state bitfield related to regular group conversion results   */
01614       /* - Set state bitfield related to regular operation                    */
01615       ADC_STATE_CLR_SET(hadc->State,
01616                         HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
01617                         HAL_ADC_STATE_REG_BUSY);
01618
01619       /* Set ADC error code */
01620       /* Check if a conversion is on going on ADC group injected */
01621       if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
01622       {
01623         /* Reset ADC error code fields related to regular conversions only */
01624         CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
01625       }
01626       else
01627       {
01628         /* Reset all ADC error code fields */
01629         ADC_CLEAR_ERRORCODE(hadc);
01630       }
01631
01632       /* Clear ADC group regular conversion flag and overrun flag               */
01633       /* (To ensure of no unknown state from potential previous ADC operations) */
01634       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
01635
01636       /* Process unlocked */
01637       /* Unlock before starting ADC conversions: in case of potential         */
01638       /* interruption, to let the process to ADC IRQ Handler.                 */
01639       __HAL_UNLOCK(hadc);
01640
01641       /* Disable all interruptions before enabling the desired ones */
01642       __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
01643
01644       /* Enable ADC end of conversion interrupt */
01645       switch (hadc->Init.EOCSelection)
01646       {
01647         case ADC_EOC_SEQ_CONV:
01648           __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS);
01649           break;
01650         /* case ADC_EOC_SINGLE_CONV */
01651         default:
01652           __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
01653           break;
01654       }
01655
01656       /* Enable ADC overrun interrupt */
01657       /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is
01658          ADC_IT_OVR enabled; otherwise data overwrite is considered as normal
01659          behavior and no CPU time is lost for a non-processed interruption */
01660       if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
01661       {
01662         __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
01663       }
01664
01665       /* Enable conversion of regular group.                                  */
01666       /* If software start has been selected, conversion starts immediately.  */
01667       /* If external trigger has been selected, conversion will start at next */
01668       /* trigger event.                                                       */
01669       /* Start ADC group regular conversion */
01670       LL_ADC_REG_StartConversion(hadc->Instance);
01671     }
01672     else
01673     {
01674       /* Process unlocked */
01675       __HAL_UNLOCK(hadc);
01676     }
01677
01678   }
01679   else
01680   {
01681     tmp_hal_status = HAL_BUSY;
01682   }
01683
01684   /* Return function status */
01685   return tmp_hal_status;
01686 }
01687
01688 /**
01689   * @brief  Stop ADC conversion of regular group (and injected group in
01690   *         case of auto_injection mode), disable interrution of
01691   *         end-of-conversion, disable ADC peripheral.
01692   * @param hadc ADC handle
01693   * @retval HAL status.
01694   */
01695 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc)
01696 {
01697   HAL_StatusTypeDef tmp_hal_status;
01698
01699   /* Check the parameters */
01700   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01701
01702   /* Process locked */
01703   __HAL_LOCK(hadc);
01704
01705   /* 1. Stop potential conversion on going, on ADC groups regular and injected */
01706   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
01707
01708   /* Disable ADC peripheral if conversions are effectively stopped */
01709   if (tmp_hal_status == HAL_OK)
01710   {
01711     /* Disable ADC end of conversion interrupt for regular group */
01712     /* Disable ADC overrun interrupt */
01713     __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
01714
01715     /* 2. Disable the ADC peripheral */
01716     tmp_hal_status = ADC_Disable(hadc);
01717
01718     /* Check if ADC is effectively disabled */
01719     if (tmp_hal_status == HAL_OK)
01720     {
01721       /* Set ADC state */
01722       ADC_STATE_CLR_SET(hadc->State,
01723                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
01724                         HAL_ADC_STATE_READY);
01725     }
01726   }
01727
01728   /* Process unlocked */
01729   __HAL_UNLOCK(hadc);
01730
01731   /* Return function status */
01732   return tmp_hal_status;
01733 }
01734
01735 /**
01736   * @brief  Enable ADC, start conversion of regular group and transfer result through DMA.
01737   * @note   Interruptions enabled in this function:
01738   *         overrun (if applicable), DMA half transfer, DMA transfer complete.
01739   *         Each of these interruptions has its dedicated callback function.
01740   * @param hadc ADC handle
01741   * @param pData Destination Buffer address.
01742   * @param Length Number of data to be transferred from ADC peripheral to memory
01743   * @retval HAL status.
01744   */
01745 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
01746 {
01747   HAL_StatusTypeDef tmp_hal_status;
01748
01749   /* Check the parameters */
01750   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01751
01752   /* Perform ADC enable and conversion start if no conversion is on going */
01753   if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
01754   {
01755     /* Process locked */
01756     __HAL_LOCK(hadc);
01757
01758       /* Enable the ADC peripheral */
01759       tmp_hal_status = ADC_Enable(hadc);
01760
01761       /* Start conversion if ADC is effectively enabled */
01762       if (tmp_hal_status == HAL_OK)
01763       {
01764         /* Set ADC state                                                        */
01765         /* - Clear state bitfield related to regular group conversion results   */
01766         /* - Set state bitfield related to regular operation                    */
01767         ADC_STATE_CLR_SET(hadc->State,
01768                           HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
01769                           HAL_ADC_STATE_REG_BUSY);
01770
01771         /* Check if a conversion is on going on ADC group injected */
01772         if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
01773         {
01774           /* Reset ADC error code fields related to regular conversions only */
01775           CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
01776         }
01777         else
01778         {
01779           /* Reset all ADC error code fields */
01780           ADC_CLEAR_ERRORCODE(hadc);
01781         }
01782
01783         /* Set the DMA transfer complete callback */
01784         hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
01785
01786         /* Set the DMA half transfer complete callback */
01787         hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
01788
01789         /* Set the DMA error callback */
01790         hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
01791
01792
01793         /* Manage ADC and DMA start: ADC overrun interruption, DMA start,     */
01794         /* ADC start (in case of SW start):                                   */
01795
01796         /* Clear regular group conversion flag and overrun flag               */
01797         /* (To ensure of no unknown state from potential previous ADC         */
01798         /* operations)                                                        */
01799         __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
01800
01801         /* Process unlocked */
01802         /* Unlock before starting ADC conversions: in case of potential         */
01803         /* interruption, to let the process to ADC IRQ Handler.                 */
01804         __HAL_UNLOCK(hadc);
01805
01806         /* With DMA, overrun event is always considered as an error even if
01807            hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore,
01808            ADC_IT_OVR is enabled. */
01809         __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
01810
01811         /* Enable ADC DMA mode */
01812         SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
01813
01814         /* Start the DMA channel */
01815         tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
01816
01817         /* Enable conversion of regular group.                                  */
01818         /* If software start has been selected, conversion starts immediately.  */
01819         /* If external trigger has been selected, conversion will start at next */
01820         /* trigger event.                                                       */
01821         /* Start ADC group regular conversion */
01822         LL_ADC_REG_StartConversion(hadc->Instance);
01823       }
01824       else
01825       {
01826         /* Process unlocked */
01827         __HAL_UNLOCK(hadc);
01828       }
01829   }
01830   else
01831   {
01832     tmp_hal_status = HAL_BUSY;
01833   }
01834
01835   /* Return function status */
01836   return tmp_hal_status;
01837 }
01838
01839 /**
01840   * @brief  Stop ADC conversion of regular group (and injected group in
01841   *         case of auto_injection mode), disable ADC DMA transfer, disable
01842   *         ADC peripheral.
01843   * @note:  ADC peripheral disable is forcing stop of potential
01844   *         conversion on ADC group injected. If ADC group injected is under use, it
01845   *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
01846   * @param hadc ADC handle
01847   * @retval HAL status.
01848   */
01849 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc)
01850 {
01851   HAL_StatusTypeDef tmp_hal_status;
01852
01853   /* Check the parameters */
01854   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01855
01856   /* Process locked */
01857   __HAL_LOCK(hadc);
01858
01859   /* 1. Stop potential ADC group regular conversion on going */
01860   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
01861
01862   /* Disable ADC peripheral if conversions are effectively stopped */
01863   if (tmp_hal_status == HAL_OK)
01864   {
01865     /* Disable ADC DMA (ADC DMA configuration of continous requests is kept) */
01866     CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
01867
01868     /* Disable the DMA channel (in case of DMA in circular mode or stop       */
01869     /* while DMA transfer is on going)                                        */
01870     if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
01871     {
01872       tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
01873
01874       /* Check if DMA channel effectively disabled */
01875       if (tmp_hal_status != HAL_OK)
01876       {
01877         /* Update ADC state machine to error */
01878         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
01879       }
01880     }
01881
01882     /* Disable ADC overrun interrupt */
01883     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
01884
01885     /* 2. Disable the ADC peripheral */
01886     /* Update "tmp_hal_status" only if DMA channel disabling passed,          */
01887     /* to keep in memory a potential failing status.                          */
01888     if (tmp_hal_status == HAL_OK)
01889     {
01890       tmp_hal_status = ADC_Disable(hadc);
01891     }
01892     else
01893     {
01894       (void)ADC_Disable(hadc);
01895     }
01896
01897     /* Check if ADC is effectively disabled */
01898     if (tmp_hal_status == HAL_OK)
01899     {
01900       /* Set ADC state */
01901       ADC_STATE_CLR_SET(hadc->State,
01902                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
01903                         HAL_ADC_STATE_READY);
01904     }
01905
01906   }
01907
01908   /* Process unlocked */
01909   __HAL_UNLOCK(hadc);
01910
01911   /* Return function status */
01912   return tmp_hal_status;
01913 }
01914
01915 /**
01916   * @brief  Get ADC regular group conversion result.
01917   * @note   Reading register DR automatically clears ADC flag EOC
01918   *         (ADC group regular end of unitary conversion).
01919   * @note   This function does not clear ADC flag EOS
01920   *         (ADC group regular end of sequence conversion).
01921   *         Occurrence of flag EOS rising:
01922   *          - If sequencer is composed of 1 rank, flag EOS is equivalent
01923   *            to flag EOC.
01924   *          - If sequencer is composed of several ranks, during the scan
01925   *            sequence flag EOC only is raised, at the end of the scan sequence
01926   *            both flags EOC and EOS are raised.
01927   *         To clear this flag, either use function:
01928   *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
01929   *         model polling: @ref HAL_ADC_PollForConversion()
01930   *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
01931   * @param hadc ADC handle
01932   * @retval ADC group regular conversion data
01933   */
01934 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc)
01935 {
01936   /* Check the parameters */
01937   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01938
01939   /* Note: EOC flag is not cleared here by software because automatically     */
01940   /*       cleared by hardware when reading register DR.                      */
01941
01942   /* Return ADC converted value */
01943   return hadc->Instance->DR;
01944 }
01945
01946 /**
01947   * @brief  Handle ADC interrupt request.
01948   * @param hadc ADC handle
01949   * @retval None
01950   */
01951 void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
01952 {
01953   uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */
01954   uint32_t tmp_isr = hadc->Instance->ISR;
01955   uint32_t tmp_ier = hadc->Instance->IER;
01956   uint32_t tmp_adc_inj_is_trigger_source_sw_start;
01957   uint32_t tmp_adc_reg_is_trigger_source_sw_start;
01958   uint32_t tmp_cfgr;
01959
01960   /* Check the parameters */
01961   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01962   assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
01963
01964   /* ========== Check End of Sampling flag for ADC group regular ========== */
01965   if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP))
01966   {
01967     /* Update state machine on end of sampling status if not in error state */
01968     if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
01969     {
01970       /* Set ADC state */
01971       SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
01972     }
01973
01974     /* End Of Sampling callback */
01975 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
01976     hadc->EndOfSamplingCallback(hadc);
01977 #else
01978     HAL_ADCEx_EndOfSamplingCallback(hadc);
01979 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
01980
01981     /* Clear regular group conversion flag */
01982     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
01983   }
01984
01985   /* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */
01986   if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
01987       (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)))
01988   {
01989     /* Update state machine on conversion status if not in error state */
01990     if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
01991     {
01992       /* Set ADC state */
01993       SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
01994     }
01995
01996     /* Determine whether any further conversion upcoming on group regular     */
01997     /* by external trigger, continuous mode or scan sequence on going         */
01998     /* to disable interruption.                                               */
01999     if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
02000     {
02001       /* Carry on if continuous mode is disabled */
02002       if (READ_BIT (hadc->Instance->CFGR, ADC_CFGR_CONT) != ADC_CFGR_CONT)
02003       {
02004         /* If End of Sequence is reached, disable interrupts */
02005         if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
02006         {
02007           /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit         */
02008           /* ADSTART==0 (no conversion on going)                              */
02009           if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
02010           {
02011             /* Disable ADC end of sequence conversion interrupt */
02012             /* Note: Overrun interrupt was enabled with EOC interrupt in      */
02013             /* HAL_Start_IT(), but is not disabled here because can be used   */
02014             /* by overrun IRQ process below.                                  */
02015             __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
02016
02017             /* Set ADC state */
02018             CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
02019
02020             if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
02021             {
02022               SET_BIT(hadc->State, HAL_ADC_STATE_READY);
02023             }
02024           }
02025           else
02026           {
02027             /* Change ADC state to error state */
02028             SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
02029
02030             /* Set ADC error code to ADC peripheral internal error */
02031             SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
02032           }
02033         }
02034       }
02035     }
02036
02037     /* Conversion complete callback */
02038     /* Note: Into callback function "HAL_ADC_ConvCpltCallback()",             */
02039     /*       to determine if conversion has been triggered from EOC or EOS,   */
02040     /*       possibility to use:                                              */
02041     /*        " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) "                */
02042 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
02043     hadc->ConvCpltCallback(hadc);
02044 #else
02045     HAL_ADC_ConvCpltCallback(hadc);
02046 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
02047
02048     /* Clear regular group conversion flag */
02049     /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of         */
02050     /*       conversion flags clear induces the release of the preserved data.*/
02051     /*       Therefore, if the preserved data value is needed, it must be     */
02052     /*       read preliminarily into HAL_ADC_ConvCpltCallback().              */
02053     __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
02054   }
02055
02056   /* ====== Check ADC group injected end of unitary conversion sequence conversions ===== */
02057   if ((((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) ||
02058       (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)))
02059   {
02060     /* Update state machine on conversion status if not in error state */
02061     if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
02062     {
02063       /* Set ADC state */
02064       SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
02065     }
02066
02067     /* Retrieve ADC configuration */
02068     tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
02069     tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
02070     tmp_cfgr = READ_REG(hadc->Instance->CFGR);
02071
02072     /* Disable interruption if no further conversion upcoming by injected     */
02073     /* external trigger or by automatic injected conversion with regular      */
02074     /* group having no further conversion upcoming (same conditions as        */
02075     /* regular group interruption disabling above),                           */
02076     /* and if injected scan sequence is completed.                            */
02077     if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL)            ||
02078         ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL)      &&
02079          ((tmp_adc_reg_is_trigger_source_sw_start != 0UL)  &&
02080           (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL))))
02081     {
02082       /* If End of Sequence is reached, disable interrupts */
02083       if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
02084       {
02085         /* Particular case if injected contexts queue is enabled:             */
02086         /* when the last context has been fully processed, JSQR is reset      */
02087         /* by the hardware. Even if no injected conversion is planned to come */
02088         /* (queue empty, triggers are ignored), it can start again            */
02089         /* immediately after setting a new context (JADSTART is still set).   */
02090         /* Therefore, state of HAL ADC injected group is kept to busy.        */
02091         if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM) == 0UL)
02092         {
02093           /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit       */
02094           /* JADSTART==0 (no conversion on going)                             */
02095           if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
02096           {
02097             /* Disable ADC end of sequence conversion interrupt  */
02098             __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
02099
02100             /* Set ADC state */
02101             CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
02102
02103             if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
02104             {
02105               SET_BIT(hadc->State, HAL_ADC_STATE_READY);
02106             }
02107           }
02108           else
02109           {
02110             /* Update ADC state machine to error */
02111             SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
02112
02113             /* Set ADC error code to ADC peripheral internal error */
02114             SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
02115           }
02116         }
02117       }
02118     }
02119
02120     /* Injected Conversion complete callback */
02121     /* Note:  HAL_ADCEx_InjectedConvCpltCallback can resort to
02122               if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or
02123               if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether
02124               interruption has been triggered by end of conversion or end of
02125               sequence.    */
02126 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
02127     hadc->InjectedConvCpltCallback(hadc);
02128 #else
02129     HAL_ADCEx_InjectedConvCpltCallback(hadc);
02130 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
02131
02132     /* Clear injected group conversion flag */
02133     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS);
02134   }
02135
02136   /* ========== Check Analog watchdog 1 flag ========== */
02137   if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))
02138   {
02139     /* Set ADC state */
02140     SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
02141
02142     /* Level out of window 1 callback */
02143 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
02144     hadc->LevelOutOfWindowCallback(hadc);
02145 #else
02146     HAL_ADC_LevelOutOfWindowCallback(hadc);
02147 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
02148
02149     /* Clear ADC analog watchdog flag */
02150     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
02151   }
02152
02153   /* ========== Check analog watchdog 2 flag ========== */
02154   if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2))
02155   {
02156     /* Set ADC state */
02157     SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
02158
02159     /* Level out of window 2 callback */
02160 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
02161     hadc->LevelOutOfWindow2Callback(hadc);
02162 #else
02163     HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
02164 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
02165
02166     /* Clear ADC analog watchdog flag */
02167     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
02168   }
02169
02170   /* ========== Check analog watchdog 3 flag ========== */
02171   if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3))
02172   {
02173     /* Set ADC state */
02174     SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
02175
02176     /* Level out of window 3 callback */
02177 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
02178     hadc->LevelOutOfWindow3Callback(hadc);
02179 #else
02180     HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
02181 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
02182
02183     /* Clear ADC analog watchdog flag */
02184     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
02185   }
02186
02187   /* ========== Check Overrun flag ========== */
02188   if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR))
02189   {
02190     /* If overrun is set to overwrite previous data (default setting),        */
02191     /* overrun event is not considered as an error.                           */
02192     /* (cf ref manual "Managing conversions without using the DMA and without */
02193     /* overrun ")                                                             */
02194     /* Exception for usage with DMA overrun event always considered as an     */
02195     /* error.                                                                 */
02196     if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
02197     {
02198       overrun_error = 1UL;
02199     }
02200     else
02201     {
02202       /* Check DMA configuration */
02203       if (LL_ADC_REG_GetDMATransfer(hadc->Instance) != LL_ADC_REG_DMA_TRANSFER_NONE)
02204       {
02205         overrun_error = 1UL;
02206       }
02207     }
02208
02209     if (overrun_error == 1UL)
02210     {
02211       /* Change ADC state to error state */
02212       SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
02213
02214       /* Set ADC error code to overrun */
02215       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
02216
02217       /* Error callback */
02218       /* Note: In case of overrun, ADC conversion data is preserved until     */
02219       /*       flag OVR is reset.                                             */
02220       /*       Therefore, old ADC conversion data can be retrieved in         */
02221       /*       function "HAL_ADC_ErrorCallback()".                            */
02222 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
02223       hadc->ErrorCallback(hadc);
02224 #else
02225       HAL_ADC_ErrorCallback(hadc);
02226 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
02227     }
02228
02229     /* Clear ADC overrun flag */
02230     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
02231   }
02232
02233   /* ========== Check Injected context queue overflow flag ========== */
02234   if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF))
02235   {
02236     /* Change ADC state to overrun state */
02237     SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
02238
02239     /* Set ADC error code to Injected context queue overflow */
02240     SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
02241
02242     /* Clear the Injected context queue overflow flag */
02243     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
02244
02245     /* Injected context queue overflow callback */
02246 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
02247     hadc->InjectedQueueOverflowCallback(hadc);
02248 #else
02249     HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
02250 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
02251   }
02252
02253 }
02254
02255 /**
02256   * @brief  Conversion complete callback in non-blocking mode.
02257   * @param hadc ADC handle
02258   * @retval None
02259   */
02260 __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
02261 {
02262   /* Prevent unused argument(s) compilation warning */
02263   UNUSED(hadc);
02264
02265   /* NOTE : This function should not be modified. When the callback is needed,
02266             function HAL_ADC_ConvCpltCallback must be implemented in the user file.
02267    */
02268 }
02269
02270 /**
02271   * @brief  Conversion DMA half-transfer callback in non-blocking mode.
02272   * @param hadc ADC handle
02273   * @retval None
02274   */
02275 __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc)
02276 {
02277   /* Prevent unused argument(s) compilation warning */
02278   UNUSED(hadc);
02279
02280   /* NOTE : This function should not be modified. When the callback is needed,
02281             function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
02282   */
02283 }
02284
02285 /**
02286   * @brief  Analog watchdog 1 callback in non-blocking mode.
02287   * @param hadc ADC handle
02288   * @retval None
02289   */
02290 __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc)
02291 {
02292   /* Prevent unused argument(s) compilation warning */
02293   UNUSED(hadc);
02294
02295   /* NOTE : This function should not be modified. When the callback is needed,
02296             function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
02297   */
02298 }
02299
02300 /**
02301   * @brief  ADC error callback in non-blocking mode
02302   *         (ADC conversion with interruption or transfer by DMA).
02303   * @note   In case of error due to overrun when using ADC with DMA transfer
02304   *         (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
02305   *         - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
02306   *         - If needed, restart a new ADC conversion using function
02307   *           "HAL_ADC_Start_DMA()"
02308   *           (this function is also clearing overrun flag)
02309   * @param hadc ADC handle
02310   * @retval None
02311   */
02312 __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
02313 {
02314   /* Prevent unused argument(s) compilation warning */
02315   UNUSED(hadc);
02316
02317   /* NOTE : This function should not be modified. When the callback is needed,
02318             function HAL_ADC_ErrorCallback must be implemented in the user file.
02319   */
02320 }
02321
02322 /**
02323   * @}
02324   */
02325
02326 /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
02327   * @brief    Peripheral Control functions
02328   *
02329 @verbatim
02330  ===============================================================================
02331              ##### Peripheral Control functions #####
02332  ===============================================================================
02333     [..]  This section provides functions allowing to:
02334       (+) Configure channels on regular group
02335       (+) Configure the analog watchdog
02336
02337 @endverbatim
02338   * @{
02339   */
02340
02341 /**
02342   * @brief  Configure a channel to be assigned to ADC group regular.
02343   * @note   In case of usage of internal measurement channels:
02344   *         Vbat/VrefInt/TempSensor.
02345   *         These internal paths can be disabled using function
02346   *         HAL_ADC_DeInit().
02347   * @note   Possibility to update parameters on the fly:
02348   *         This function initializes channel into ADC group regular,
02349   *         following calls to this function can be used to reconfigure
02350   *         some parameters of structure "ADC_ChannelConfTypeDef" on the fly,
02351   *         without resetting the ADC.
02352   *         The setting of these parameters is conditioned to ADC state:
02353   *         Refer to comments of structure "ADC_ChannelConfTypeDef".
02354   * @param hadc ADC handle
02355   * @param sConfig Structure of ADC channel assigned to ADC group regular.
02356   * @retval HAL status
02357   */
02358 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
02359 {
02360   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
02361   uint32_t tmpOffsetShifted;
02362   uint32_t tmp_config_internal_channel;
02363   __IO uint32_t wait_loop_index = 0;
02364   uint32_t tmp_adc_is_conversion_on_going_regular;
02365   uint32_t tmp_adc_is_conversion_on_going_injected;
02366
02367   /* Check the parameters */
02368   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02369   assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
02370   assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
02371   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff));
02372   assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber));
02373   assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset));
02374
02375   /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
02376      ignored (considered as reset) */
02377   assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE)));
02378
02379   /* Verification of channel number */
02380   if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
02381   {
02382     assert_param(IS_ADC_CHANNEL(hadc, sConfig->Channel));
02383   }
02384   else
02385   {
02386     assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfig->Channel));
02387   }
02388
02389   /* Process locked */
02390   __HAL_LOCK(hadc);
02391
02392   /* Parameters update conditioned to ADC state:                              */
02393   /* Parameters that can be updated when ADC is disabled or enabled without   */
02394   /* conversion on going on regular group:                                    */
02395   /*  - Channel number                                                        */
02396   /*  - Channel rank                                                          */
02397   if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
02398   {
02399     /* Set ADC group regular sequence: channel on the selected scan sequence rank */
02400     LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel);
02401
02402     /* Parameters update conditioned to ADC state:                              */
02403     /* Parameters that can be updated when ADC is disabled or enabled without   */
02404     /* conversion on going on regular group:                                    */
02405     /*  - Channel sampling time                                                 */
02406     /*  - Channel offset                                                        */
02407     tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
02408     tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
02409     if ((tmp_adc_is_conversion_on_going_regular == 0UL)
02410         && (tmp_adc_is_conversion_on_going_injected == 0UL)
02411        )
02412     {
02413       /* Set sampling time of the selected ADC channel */
02414       LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime);
02415
02416       /* Configure the offset: offset enable/disable, channel, offset value */
02417
02418       /* Shift the offset with respect to the selected ADC resolution. */
02419       /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
02420       tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset);
02421
02422       if (sConfig->OffsetNumber != ADC_OFFSET_NONE)
02423       {
02424         /* Set ADC selected offset number */
02425         LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted);
02426
02427       }
02428       else
02429       {
02430         /* Scan each offset register to check if the selected channel is targeted. */
02431         /* If this is the case, the corresponding offset number is disabled.       */
02432         if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
02433         {
02434           LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
02435         }
02436         if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
02437         {
02438           LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
02439         }
02440         if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
02441         {
02442           LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
02443         }
02444         if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
02445         {
02446           LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
02447         }
02448       }
02449     }
02450
02451     /* Parameters update conditioned to ADC state:                              */
02452     /* Parameters that can be updated only when ADC is disabled:                */
02453     /*  - Single or differential mode                                           */
02454     /*  - Internal measurement channels: Vbat/VrefInt/TempSensor                */
02455     if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
02456     {
02457       /* Set mode single-ended or differential input of the selected ADC channel */
02458       LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff);
02459
02460       /* Configuration of differential mode */
02461       if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED)
02462       {
02463         /* Set sampling time of the selected ADC channel */
02464         /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
02465         LL_ADC_SetChannelSamplingTime(hadc->Instance,
02466                                       (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)),
02467                                       sConfig->SamplingTime);
02468       }
02469
02470       /* Management of internal measurement channels: Vbat/VrefInt/TempSensor.  */
02471       /* If internal channel selected, enable dedicated internal buffers and    */
02472       /* paths.                                                                 */
02473       /* Note: these internal measurement paths can be disabled using           */
02474       /* HAL_ADC_DeInit().                                                      */
02475
02476       if(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
02477       {
02478         /* Configuration of common ADC parameters                                 */
02479
02480         tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
02481
02482         /* Software is allowed to change common parameters only when all ADCs   */
02483         /* of the common group are disabled.                                    */
02484         if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
02485         {
02486           /* If the requested internal measurement path has already been enabled, */
02487           /* bypass the configuration processing.                                 */
02488           if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
02489           {
02490             if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
02491             {
02492               LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
02493
02494               /* Delay for temperature sensor stabilization time */
02495               /* Wait loop initialization and execution */
02496               /* Note: Variable divided by 2 to compensate partially              */
02497               /*       CPU processing cycles, scaling in us split to not          */
02498               /*       exceed 32 bits register capacity and handle low frequency. */
02499               wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
02500               while(wait_loop_index != 0UL)
02501               {
02502                 wait_loop_index--;
02503               }
02504             }
02505           }
02506           else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
02507           {
02508             if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
02509             {
02510               LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
02511             }
02512           }
02513           else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
02514           {
02515             if (ADC_VREFINT_INSTANCE(hadc))
02516             {
02517               LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
02518             }
02519           }
02520           else
02521           {
02522             /* nothing to do */
02523           }
02524         }
02525         /* If the requested internal measurement path has already been          */
02526         /* enabled and other ADC of the common group are enabled, internal      */
02527         /* measurement paths cannot be enabled.                                 */
02528         else
02529         {
02530           /* Update ADC state machine to error */
02531           SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
02532
02533           tmp_hal_status = HAL_ERROR;
02534         }
02535       }
02536     }
02537   }
02538
02539   /* If a conversion is on going on regular group, no update on regular       */
02540   /* channel could be done on neither of the channel configuration structure  */
02541   /* parameters.                                                              */
02542   else
02543   {
02544     /* Update ADC state machine to error */
02545     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
02546
02547     tmp_hal_status = HAL_ERROR;
02548   }
02549
02550   /* Process unlocked */
02551   __HAL_UNLOCK(hadc);
02552
02553   /* Return function status */
02554   return tmp_hal_status;
02555 }
02556
02557 /**
02558   * @brief  Configure the analog watchdog.
02559   * @note   Possibility to update parameters on the fly:
02560   *         This function initializes the selected analog watchdog, successive
02561   *         calls to this function can be used to reconfigure some parameters
02562   *         of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting
02563   *         the ADC.
02564   *         The setting of these parameters is conditioned to ADC state.
02565   *         For parameters constraints, see comments of structure
02566   *         "ADC_AnalogWDGConfTypeDef".
02567   * @note   On this STM32 serie, analog watchdog thresholds cannot be modified
02568   *         while ADC conversion is on going.
02569   * @param hadc ADC handle
02570   * @param AnalogWDGConfig Structure of ADC analog watchdog configuration
02571   * @retval HAL status
02572   */
02573 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
02574 {
02575   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
02576   uint32_t tmpAWDHighThresholdShifted;
02577   uint32_t tmpAWDLowThresholdShifted;
02578   uint32_t tmp_adc_is_conversion_on_going_regular;
02579   uint32_t tmp_adc_is_conversion_on_going_injected;
02580
02581   /* Check the parameters */
02582   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02583   assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber));
02584   assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
02585   assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
02586
02587   if ((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG)     ||
02588       (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC)   ||
02589       (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC))
02590   {
02591     assert_param(IS_ADC_CHANNEL(hadc, AnalogWDGConfig->Channel));
02592   }
02593
02594   /* Verify thresholds range */
02595   if (hadc->Init.OversamplingMode == ENABLE)
02596   {
02597     /* Case of oversampling enabled: depending on ratio and shift configuration,
02598        analog watchdog thresholds can be higher than ADC resolution.
02599        Verify if thresholds are within maximum thresholds range. */
02600     assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->HighThreshold));
02601     assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->LowThreshold));
02602   }
02603   else
02604   {
02605     /* Verify if thresholds are within the selected ADC resolution */
02606     assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
02607     assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
02608   }
02609
02610   /* Process locked */
02611   __HAL_LOCK(hadc);
02612
02613   /* Parameters update conditioned to ADC state:                              */
02614   /* Parameters that can be updated when ADC is disabled or enabled without   */
02615   /* conversion on going on ADC groups regular and injected:                  */
02616   /*  - Analog watchdog channels                                              */
02617   /*  - Analog watchdog thresholds                                            */
02618   tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
02619   tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
02620   if ((tmp_adc_is_conversion_on_going_regular == 0UL)
02621       && (tmp_adc_is_conversion_on_going_injected == 0UL)
02622      )
02623   {
02624     /* Analog watchdog configuration */
02625     if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
02626     {
02627       /* Configuration of analog watchdog:                                    */
02628       /*  - Set the analog watchdog enable mode: one or overall group of      */
02629       /*    channels, on groups regular and-or injected.                      */
02630       switch (AnalogWDGConfig->WatchdogMode)
02631       {
02632         case ADC_ANALOGWATCHDOG_SINGLE_REG:
02633           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
02634                                           LL_ADC_GROUP_REGULAR));
02635           break;
02636
02637         case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
02638           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
02639                                           LL_ADC_GROUP_INJECTED));
02640           break;
02641
02642         case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
02643           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
02644                                           LL_ADC_GROUP_REGULAR_INJECTED));
02645           break;
02646
02647         case ADC_ANALOGWATCHDOG_ALL_REG:
02648           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG);
02649           break;
02650
02651         case ADC_ANALOGWATCHDOG_ALL_INJEC:
02652           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_INJ);
02653           break;
02654
02655         case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
02656           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
02657           break;
02658
02659         default: /* ADC_ANALOGWATCHDOG_NONE */
02660           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE);
02661           break;
02662       }
02663
02664       /* Shift the offset in function of the selected ADC resolution:         */
02665       /* Thresholds have to be left-aligned on bit 11, the LSB (right bits)   */
02666       /* are set to 0                                                         */
02667       tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
02668       tmpAWDLowThresholdShifted  = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
02669
02670       /* Set ADC analog watchdog thresholds value of both thresholds high and low */
02671       LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted, tmpAWDLowThresholdShifted);
02672
02673       /* Update state, clear previous result related to AWD1 */
02674       CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
02675
02676       /* Clear flag ADC analog watchdog */
02677       /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready  */
02678       /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent()          */
02679       /* (in case left enabled by previous ADC operations).                 */
02680       LL_ADC_ClearFlag_AWD1(hadc->Instance);
02681
02682       /* Configure ADC analog watchdog interrupt */
02683       if (AnalogWDGConfig->ITMode == ENABLE)
02684       {
02685         LL_ADC_EnableIT_AWD1(hadc->Instance);
02686       }
02687       else
02688       {
02689         LL_ADC_DisableIT_AWD1(hadc->Instance);
02690       }
02691     }
02692     /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */
02693     else
02694     {
02695       switch (AnalogWDGConfig->WatchdogMode)
02696       {
02697         case ADC_ANALOGWATCHDOG_SINGLE_REG:
02698         case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
02699         case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
02700           /* Update AWD by bitfield to keep the possibility to monitor        */
02701           /* several channels by successive calls of this function.           */
02702           if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
02703           {
02704             SET_BIT(hadc->Instance->AWD2CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL)));
02705           }
02706           else
02707           {
02708             SET_BIT(hadc->Instance->AWD3CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL)));
02709           }
02710           break;
02711
02712         case ADC_ANALOGWATCHDOG_ALL_REG:
02713         case ADC_ANALOGWATCHDOG_ALL_INJEC:
02714         case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
02715           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
02716           break;
02717
02718         default: /* ADC_ANALOGWATCHDOG_NONE */
02719           LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE);
02720           break;
02721       }
02722
02723       /* Shift the thresholds in function of the selected ADC resolution      */
02724       /* have to be left-aligned on bit 7, the LSB (right bits) are set to 0  */
02725       tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
02726       tmpAWDLowThresholdShifted  = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
02727
02728       /* Set ADC analog watchdog thresholds value of both thresholds high and low */
02729       LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted, tmpAWDLowThresholdShifted);
02730
02731       if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
02732       {
02733         /* Update state, clear previous result related to AWD2 */
02734         CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
02735
02736         /* Clear flag ADC analog watchdog */
02737         /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready  */
02738         /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent()          */
02739         /* (in case left enabled by previous ADC operations).                 */
02740         LL_ADC_ClearFlag_AWD2(hadc->Instance);
02741
02742         /* Configure ADC analog watchdog interrupt */
02743         if (AnalogWDGConfig->ITMode == ENABLE)
02744         {
02745           LL_ADC_EnableIT_AWD2(hadc->Instance);
02746         }
02747         else
02748         {
02749           LL_ADC_DisableIT_AWD2(hadc->Instance);
02750         }
02751       }
02752       /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
02753       else
02754       {
02755         /* Update state, clear previous result related to AWD3 */
02756         CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3);
02757
02758         /* Clear flag ADC analog watchdog */
02759         /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready  */
02760         /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent()          */
02761         /* (in case left enabled by previous ADC operations).                 */
02762         LL_ADC_ClearFlag_AWD3(hadc->Instance);
02763
02764         /* Configure ADC analog watchdog interrupt */
02765         if (AnalogWDGConfig->ITMode == ENABLE)
02766         {
02767           LL_ADC_EnableIT_AWD3(hadc->Instance);
02768         }
02769         else
02770         {
02771           LL_ADC_DisableIT_AWD3(hadc->Instance);
02772         }
02773       }
02774     }
02775
02776   }
02777   /* If a conversion is on going on ADC group regular or injected, no update  */
02778   /* could be done on neither of the AWD configuration structure parameters.  */
02779   else
02780   {
02781     /* Update ADC state machine to error */
02782     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
02783
02784     tmp_hal_status = HAL_ERROR;
02785   }
02786   /* Process unlocked */
02787   __HAL_UNLOCK(hadc);
02788
02789   /* Return function status */
02790   return tmp_hal_status;
02791 }
02792
02793
02794 /**
02795   * @}
02796   */
02797
02798 /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
02799   *  @brief    ADC Peripheral State functions
02800   *
02801 @verbatim
02802  ===============================================================================
02803             ##### Peripheral state and errors functions #####
02804  ===============================================================================
02805     [..]
02806     This subsection provides functions to get in run-time the status of the
02807     peripheral.
02808       (+) Check the ADC state
02809       (+) Check the ADC error code
02810
02811 @endverbatim
02812   * @{
02813   */
02814
02815 /**
02816   * @brief  Return the ADC handle state.
02817   * @note   ADC state machine is managed by bitfields, ADC status must be
02818   *         compared with states bits.
02819   *         For example:
02820   *           " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
02821   *           " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
02822   * @param hadc ADC handle
02823   * @retval ADC handle state (bitfield on 32 bits)
02824   */
02825 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc)
02826 {
02827   /* Check the parameters */
02828   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02829
02830   /* Return ADC handle state */
02831   return hadc->State;
02832 }
02833
02834 /**
02835   * @brief  Return the ADC error code.
02836   * @param hadc ADC handle
02837   * @retval ADC error code (bitfield on 32 bits)
02838   */
02839 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
02840 {
02841   /* Check the parameters */
02842   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02843
02844   return hadc->ErrorCode;
02845 }
02846
02847 /**
02848   * @}
02849   */
02850
02851 /**
02852   * @}
02853   */
02854
02855 /** @defgroup ADC_Private_Functions ADC Private Functions
02856   * @{
02857   */
02858
02859 /**
02860   * @brief  Stop ADC conversion.
02861   * @param hadc ADC handle
02862   * @param ConversionGroup ADC group regular and/or injected.
02863   *          This parameter can be one of the following values:
02864   *            @arg @ref ADC_REGULAR_GROUP           ADC regular conversion type.
02865   *            @arg @ref ADC_INJECTED_GROUP          ADC injected conversion type.
02866   *            @arg @ref ADC_REGULAR_INJECTED_GROUP  ADC regular and injected conversion type.
02867   * @retval HAL status.
02868   */
02869 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
02870 {
02871   uint32_t tickstart;
02872   uint32_t Conversion_Timeout_CPU_cycles = 0UL;
02873   uint32_t conversion_group_reassigned = ConversionGroup;
02874   uint32_t tmp_ADC_CR_ADSTART_JADSTART;
02875   uint32_t tmp_adc_is_conversion_on_going_regular;
02876   uint32_t tmp_adc_is_conversion_on_going_injected;
02877
02878   /* Check the parameters */
02879   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02880   assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
02881
02882   /* Verification if ADC is not already stopped (on regular and injected      */
02883   /* groups) to bypass this function if not needed.                           */
02884   tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
02885   tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
02886   if ((tmp_adc_is_conversion_on_going_regular != 0UL)
02887       || (tmp_adc_is_conversion_on_going_injected != 0UL)
02888      )
02889   {
02890     /* Particular case of continuous auto-injection mode combined with        */
02891     /* auto-delay mode.                                                       */
02892     /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not   */
02893     /* injected group stop ADC_CR_JADSTP).                                    */
02894     /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1   */
02895     /* (see reference manual).                                                */
02896     if (((hadc->Instance->CFGR & ADC_CFGR_JAUTO) != 0UL)
02897         && (hadc->Init.ContinuousConvMode == ENABLE)
02898         && (hadc->Init.LowPowerAutoWait == ENABLE)
02899        )
02900     {
02901       /* Use stop of regular group */
02902       conversion_group_reassigned = ADC_REGULAR_GROUP;
02903
02904       /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
02905       while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL)
02906       {
02907         if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES * 4UL))
02908         {
02909           /* Update ADC state machine to error */
02910           SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
02911
02912           /* Set ADC error code to ADC peripheral internal error */
02913           SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
02914
02915           return HAL_ERROR;
02916         }
02917         Conversion_Timeout_CPU_cycles ++;
02918       }
02919
02920       /* Clear JEOS */
02921       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
02922     }
02923
02924     /* Stop potential conversion on going on ADC group regular */
02925     if (conversion_group_reassigned != ADC_INJECTED_GROUP)
02926     {
02927       /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
02928       if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
02929       {
02930         if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
02931         {
02932           /* Stop ADC group regular conversion */
02933           LL_ADC_REG_StopConversion(hadc->Instance);
02934         }
02935       }
02936     }
02937
02938     /* Stop potential conversion on going on ADC group injected */
02939     if (conversion_group_reassigned != ADC_REGULAR_GROUP)
02940     {
02941       /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */
02942       if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
02943       {
02944         if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
02945         {
02946           /* Stop ADC group injected conversion */
02947           LL_ADC_INJ_StopConversion(hadc->Instance);
02948         }
02949       }
02950     }
02951
02952     /* Selection of start and stop bits with respect to the regular or injected group */
02953     switch (conversion_group_reassigned)
02954     {
02955       case ADC_REGULAR_INJECTED_GROUP:
02956         tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART);
02957         break;
02958       case ADC_INJECTED_GROUP:
02959         tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART;
02960         break;
02961       /* Case ADC_REGULAR_GROUP only*/
02962       default:
02963         tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART;
02964         break;
02965     }
02966
02967     /* Wait for conversion effectively stopped */
02968     tickstart = HAL_GetTick();
02969
02970     while ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
02971     {
02972       if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
02973       {
02974         /* Update ADC state machine to error */
02975         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
02976
02977         /* Set ADC error code to ADC peripheral internal error */
02978         SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
02979
02980         return HAL_ERROR;
02981       }
02982     }
02983
02984   }
02985
02986   /* Return HAL status */
02987   return HAL_OK;
02988 }
02989
02990
02991
02992 /**
02993   * @brief  Enable the selected ADC.
02994   * @note   Prerequisite condition to use this function: ADC must be disabled
02995   *         and voltage regulator must be enabled (done into HAL_ADC_Init()).
02996   * @param hadc ADC handle
02997   * @retval HAL status.
02998   */
02999 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
03000 {
03001   uint32_t tickstart;
03002
03003   /* ADC enable and wait for ADC ready (in case of ADC is disabled or         */
03004   /* enabling phase not yet completed: flag ADC ready not yet set).           */
03005   /* Timeout implemented to not be stuck if ADC cannot be enabled (possible   */
03006   /* causes: ADC clock not running, ...).                                     */
03007   if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
03008   {
03009     /* Check if conditions to enable the ADC are fulfilled */
03010     if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
03011     {
03012       /* Update ADC state machine to error */
03013       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
03014
03015       /* Set ADC error code to ADC peripheral internal error */
03016       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
03017
03018       return HAL_ERROR;
03019     }
03020
03021     /* Enable the ADC peripheral */
03022     LL_ADC_Enable(hadc->Instance);
03023
03024     /* Wait for ADC effectively enabled */
03025     tickstart = HAL_GetTick();
03026
03027     while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
03028     {
03029       /*  If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit
03030           has been cleared (after a calibration), ADEN bit is reset by the
03031           calibration logic.
03032           The workaround is to continue setting ADEN until ADRDY is becomes 1.
03033           Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
03034           4 ADC clock cycle duration */
03035       /* Note: Test of ADC enabled required due to hardware constraint to     */
03036       /*       not enable ADC if already enabled.                             */
03037       if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
03038       {
03039         LL_ADC_Enable(hadc->Instance);
03040       }
03041
03042       if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
03043       {
03044         /* Update ADC state machine to error */
03045         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
03046
03047         /* Set ADC error code to ADC peripheral internal error */
03048         SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
03049
03050         return HAL_ERROR;
03051       }
03052     }
03053   }
03054
03055   /* Return HAL status */
03056   return HAL_OK;
03057 }
03058
03059 /**
03060   * @brief  Disable the selected ADC.
03061   * @note   Prerequisite condition to use this function: ADC conversions must be
03062   *         stopped.
03063   * @param hadc ADC handle
03064   * @retval HAL status.
03065   */
03066 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc)
03067 {
03068   uint32_t tickstart;
03069   const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance);
03070
03071   /* Verification if ADC is not already disabled:                             */
03072   /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already  */
03073   /*       disabled.                                                          */
03074   if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
03075       && (tmp_adc_is_disable_on_going == 0UL)
03076      )
03077   {
03078     /* Check if conditions to disable the ADC are fulfilled */
03079     if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN)
03080     {
03081       /* Disable the ADC peripheral */
03082       LL_ADC_Disable(hadc->Instance);
03083       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY));
03084     }
03085     else
03086     {
03087       /* Update ADC state machine to error */
03088       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
03089
03090       /* Set ADC error code to ADC peripheral internal error */
03091       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
03092
03093       return HAL_ERROR;
03094     }
03095
03096     /* Wait for ADC effectively disabled */
03097     /* Get tick count */
03098     tickstart = HAL_GetTick();
03099
03100     while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
03101     {
03102       if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
03103       {
03104         /* Update ADC state machine to error */
03105         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
03106
03107         /* Set ADC error code to ADC peripheral internal error */
03108         SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
03109
03110         return HAL_ERROR;
03111       }
03112     }
03113   }
03114
03115   /* Return HAL status */
03116   return HAL_OK;
03117 }
03118
03119 /**
03120   * @brief  DMA transfer complete callback.
03121   * @param hdma pointer to DMA handle.
03122   * @retval None
03123   */
03124 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
03125 {
03126   /* Retrieve ADC handle corresponding to current DMA handle */
03127   ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
03128
03129   /* Update state machine on conversion status if not in error state */
03130   if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL)
03131   {
03132     /* Set ADC state */
03133     SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
03134
03135     /* Determine whether any further conversion upcoming on group regular     */
03136     /* by external trigger, continuous mode or scan sequence on going         */
03137     /* to disable interruption.                                               */
03138     /* Is it the end of the regular sequence ? */
03139     if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL)
03140     {
03141       /* Are conversions software-triggered ? */
03142       if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
03143       {
03144         /* Is CONT bit set ? */
03145         if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL)
03146         {
03147           /* CONT bit is not set, no more conversions expected */
03148           CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
03149           if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
03150           {
03151             SET_BIT(hadc->State, HAL_ADC_STATE_READY);
03152           }
03153         }
03154       }
03155     }
03156     else
03157     {
03158       /* DMA End of Transfer interrupt was triggered but conversions sequence
03159          is not over. If DMACFG is set to 0, conversions are stopped. */
03160       if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMACFG) == 0UL)
03161       {
03162         /* DMACFG bit is not set, conversions are stopped. */
03163         CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
03164         if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
03165         {
03166           SET_BIT(hadc->State, HAL_ADC_STATE_READY);
03167         }
03168       }
03169     }
03170
03171     /* Conversion complete callback */
03172 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
03173     hadc->ConvCpltCallback(hadc);
03174 #else
03175     HAL_ADC_ConvCpltCallback(hadc);
03176 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
03177   }
03178   else /* DMA and-or internal error occurred */
03179   {
03180     if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL)
03181     {
03182       /* Call HAL ADC Error Callback function */
03183 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
03184       hadc->ErrorCallback(hadc);
03185 #else
03186       HAL_ADC_ErrorCallback(hadc);
03187 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
03188     }
03189     else
03190     {
03191       /* Call ADC DMA error callback */
03192       hadc->DMA_Handle->XferErrorCallback(hdma);
03193     }
03194   }
03195 }
03196
03197 /**
03198   * @brief  DMA half transfer complete callback.
03199   * @param hdma pointer to DMA handle.
03200   * @retval None
03201   */
03202 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
03203 {
03204   /* Retrieve ADC handle corresponding to current DMA handle */
03205   ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
03206
03207   /* Half conversion callback */
03208 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
03209   hadc->ConvHalfCpltCallback(hadc);
03210 #else
03211   HAL_ADC_ConvHalfCpltCallback(hadc);
03212 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
03213 }
03214
03215 /**
03216   * @brief  DMA error callback.
03217   * @param hdma pointer to DMA handle.
03218   * @retval None
03219   */
03220 void ADC_DMAError(DMA_HandleTypeDef *hdma)
03221 {
03222   /* Retrieve ADC handle corresponding to current DMA handle */
03223   ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
03224
03225   /* Set ADC state */
03226   SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
03227
03228   /* Set ADC error code to DMA error */
03229   SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
03230
03231   /* Error callback */
03232 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
03233   hadc->ErrorCallback(hadc);
03234 #else
03235   HAL_ADC_ErrorCallback(hadc);
03236 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
03237 }
03238
03239 /**
03240   * @}
03241   */
03242
03243 #endif /* HAL_ADC_MODULE_ENABLED */
03244 /**
03245   * @}
03246   */
03247
03248 /**
03249   * @}
03250   */
03251
03252 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:33 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_adc.h Source File

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stm32wbxx_hal_adc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_adc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of ADC HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_ADC_H
00022 #define STM32WBxx_HAL_ADC_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 /* Include low level driver */
00032 #include "stm32wbxx_ll_adc.h"
00033
00034 /** @addtogroup STM32WBxx_HAL_Driver
00035   * @{
00036   */
00037
00038 /** @addtogroup ADC
00039   * @{
00040   */
00041
00042 /* Exported types ------------------------------------------------------------*/
00043 /** @defgroup ADC_Exported_Types ADC Exported Types
00044   * @{
00045   */
00046
00047 /**
00048   * @brief  ADC group regular oversampling structure definition
00049   */
00050 typedef struct
00051 {
00052   uint32_t Ratio;                         /*!< Configures the oversampling ratio.
00053                                                This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
00054
00055   uint32_t RightBitShift;                 /*!< Configures the division coefficient for the Oversampler.
00056                                                This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
00057
00058   uint32_t TriggeredMode;                 /*!< Selects the regular triggered oversampling mode.
00059                                                This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */
00060
00061   uint32_t OversamplingStopReset;         /*!< Selects the regular oversampling mode.
00062                                                The oversampling is either temporary stopped or reset upon an injected
00063                                                sequence interruption.
00064                                                If oversampling is enabled on both regular and injected groups, this parameter
00065                                                is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE"
00066                                                (the oversampling buffer is zeroed during injection sequence).
00067                                                This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */
00068
00069 } ADC_OversamplingTypeDef;
00070
00071 /**
00072   * @brief  Structure definition of ADC instance and ADC group regular.
00073   * @note   Parameters of this structure are shared within 2 scopes:
00074   *          - Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign,
00075   *            ScanConvMode, EOCSelection, LowPowerAutoWait.
00076   *          - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion,
00077   *            ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling.
00078   * @note   The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state.
00079   *         ADC state can be either:
00080   *          - For all parameters: ADC disabled
00081   *          - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on group regular.
00082   *          - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on groups regular and injected.
00083   *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
00084   *         without error reporting (as it can be the expected behavior in case of intended action to update another parameter
00085   *         (which fulfills the ADC state condition) on the fly).
00086   */
00087 typedef struct
00088 {
00089   uint32_t ClockPrescaler;        /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler.
00090                                        This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE.
00091                                        Note: The ADC clock configuration is common to all ADC instances.
00092                                        Note: ADC clock source and prescaler must be selected in function of system clock to not exceed ADC maximum frequency, depending on devices.
00093                                              Example: STM32WB55xx ADC maximum frequency is 64MHz (corresponding to 4.27Msmp/s maximum)
00094                                              Example: STM32WB50xx ADC maximum frequency is 32MHz (corresponding to 2.13Msmp/s maximum)
00095                                              For ADC maximum frequency, refer to datasheet of the selected device.
00096                                        Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits,
00097                                              AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits.
00098                                        Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only
00099                                              if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC
00100                                              must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details.
00101                                        Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level.
00102                                        Note: This parameter can be modified only if all ADC instances are disabled. */
00103
00104   uint32_t Resolution;            /*!< Configure the ADC resolution.
00105                                        This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */
00106
00107   uint32_t DataAlign;             /*!< Specify ADC data alignment in conversion data register (right or left).
00108                                        Refer to reference manual for alignments formats versus resolutions.
00109                                        This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */
00110
00111   uint32_t ScanConvMode;          /*!< Configure the sequencer of ADC groups regular and injected.
00112                                        This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
00113                                        If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
00114                                                     Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
00115                                        If enabled:  Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each channel in sequencer).
00116                                                     Scan direction is upward: from rank 1 to rank 'n'.
00117                                        This parameter can be a value of @ref ADC_Scan_mode */
00118
00119   uint32_t EOCSelection;          /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions.
00120                                        This parameter can be a value of @ref ADC_EOCSelection. */
00121
00122   FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous
00123                                        conversion (for ADC group regular) or previous sequence (for ADC group injected) has been retrieved by user software,
00124                                        using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue().
00125                                        This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun
00126                                        for low frequency applications.
00127                                        This parameter can be set to ENABLE or DISABLE.
00128                                        Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag
00129                                              to free the IRQ vector sequencer.
00130                                              Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed:
00131                                              use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start.
00132                                              (in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */
00133
00134   FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,
00135                                        after the first ADC conversion start trigger occurred (software start or external trigger).
00136                                        This parameter can be set to ENABLE or DISABLE. */
00137
00138   uint32_t NbrOfConversion;       /*!< Specify the number of ranks that will be converted within the regular group sequencer.
00139                                        To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
00140                                        This parameter must be a number between Min_Data = 1 and Max_Data = 16.
00141                                        Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without
00142                                        continuous mode or external trigger that could launch a conversion). */
00143
00144   FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence
00145                                        (main sequence subdivided in successive parts).
00146                                        Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
00147                                        Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
00148                                        This parameter can be set to ENABLE or DISABLE. */
00149
00150   uint32_t NbrOfDiscConversion;   /*!< Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided.
00151                                        If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
00152                                        This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
00153
00154   uint32_t ExternalTrigConv;      /*!< Select the external event source used to trigger ADC group regular conversion start.
00155                                        If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
00156                                        This parameter can be a value of @ref ADC_regular_external_trigger_source.
00157                                        Caution: external trigger source is common to all ADC instances. */
00158
00159   uint32_t ExternalTrigConvEdge;  /*!< Select the external event edge used to trigger ADC group regular conversion start.
00160                                        If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.
00161                                        This parameter can be a value of @ref ADC_regular_external_trigger_edge */
00162
00163   FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached)
00164                                        or in continuous mode (DMA transfer unlimited, whatever number of conversions).
00165                                        This parameter can be set to ENABLE or DISABLE.
00166                                        Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */
00167
00168   uint32_t Overrun;               /*!< Select the behavior in case of overrun: data overwritten or preserved (default).
00169                                        This parameter applies to ADC group regular only.
00170                                        This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR.
00171                                        Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear
00172                                        end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function
00173                                        HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear).
00174                                        Note: Error reporting with respect to the conversion mode:
00175                                              - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data
00176                                                overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
00177                                              - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */
00178
00179   FunctionalState OversamplingMode;       /*!< Specify whether the oversampling feature is enabled or disabled.
00180                                                This parameter can be set to ENABLE or DISABLE.
00181                                                Note: This parameter can be modified only if there is no conversion is ongoing on ADC groups regular and injected */
00182
00183   ADC_OversamplingTypeDef Oversampling;   /*!< Specify the Oversampling parameters.
00184                                                Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */
00185
00186 } ADC_InitTypeDef;
00187
00188 /**
00189   * @brief  Structure definition of ADC channel for regular group
00190   * @note   The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state.
00191   *         ADC state can be either:
00192   *          - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff')
00193   *          - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group.
00194   *          - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups.
00195   *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
00196   *         without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition)
00197   *         on the fly).
00198   */
00199 typedef struct
00200 {
00201   uint32_t Channel;                /*!< Specify the channel to configure into ADC regular group.
00202                                         This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
00203                                         Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
00204
00205   uint32_t Rank;                   /*!< Specify the rank in the regular group sequencer.
00206                                         This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS
00207                                         Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by
00208                                         the new channel setting (or parameter number of conversions adjusted) */
00209
00210   uint32_t SamplingTime;           /*!< Sampling time value to be set for the selected channel.
00211                                         Unit: ADC clock cycles
00212                                         Conversion time is the addition of sampling time and processing time
00213                                         (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
00214                                         This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME
00215                                         Caution: This parameter applies to a channel that can be used into regular and/or injected group.
00216                                                  It overwrites the last setting.
00217                                         Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
00218                                               sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
00219                                               Refer to device datasheet for timings values. */
00220
00221   uint32_t SingleDiff;             /*!< Select single-ended or differential input.
00222                                         In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
00223                                                               Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
00224                                         This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING
00225                                         Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
00226                                                  It overwrites the last setting.
00227                                         Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.
00228                                         Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
00229                                         Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
00230                                               If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case
00231                                         of another parameter update on the fly) */
00232
00233   uint32_t OffsetNumber;           /*!< Select the offset number
00234                                         This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB
00235                                         Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */
00236
00237   uint32_t Offset;                 /*!< Define the offset to be subtracted from the raw converted data.
00238                                         Offset value must be a positive number.
00239                                         Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF,
00240                                         0x3FF, 0xFF or 0x3F respectively.
00241                                         Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
00242                                               without continuous mode or external trigger that could launch a conversion). */
00243
00244 } ADC_ChannelConfTypeDef;
00245
00246 /**
00247   * @brief  Structure definition of ADC analog watchdog
00248   * @note   The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
00249   *         ADC state can be either:
00250   *          - For all parameters: ADC disabled or ADC enabled without conversion on going on ADC groups regular and injected.
00251   */
00252 typedef struct
00253 {
00254   uint32_t WatchdogNumber;    /*!< Select which ADC analog watchdog is monitoring the selected channel.
00255                                    For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode')
00256                                    For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel)
00257                                    This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */
00258
00259   uint32_t WatchdogMode;      /*!< Configure the ADC analog watchdog mode: single/all/none channels.
00260                                    For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC groups regular and-or injected.
00261                                    For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure. Channels on ADC group regular and injected are not differentiated: Set value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no channel.
00262                                    This parameter can be a value of @ref ADC_analog_watchdog_mode. */
00263
00264   uint32_t Channel;           /*!< Select which ADC channel to monitor by analog watchdog.
00265                                    For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored).
00266                                    For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE').
00267                                    This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */
00268
00269   FunctionalState ITMode;     /*!< Specify whether the analog watchdog is configured in interrupt or polling mode.
00270                                    This parameter can be set to ENABLE or DISABLE */
00271
00272   uint32_t HighThreshold;     /*!< Configure the ADC analog watchdog High threshold value.
00273                                    Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
00274                                    between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
00275                                    Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
00276                                          the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
00277                                    Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
00278                                          impacted: the comparison of analog watchdog thresholds is done on
00279                                          oversampling final computation (after ratio and shift application):
00280                                          ADC data register bitfield [15:4] (12 most significant bits). */
00281
00282   uint32_t LowThreshold;      /*!< Configures the ADC analog watchdog Low threshold value.
00283                                    Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
00284                                    between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
00285                                    Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
00286                                          the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
00287                                    Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
00288                                          impacted: the comparison of analog watchdog thresholds is done on
00289                                          oversampling final computation (after ratio and shift application):
00290                                          ADC data register bitfield [15:4] (12 most significant bits). */
00291 } ADC_AnalogWDGConfTypeDef;
00292
00293 /**
00294   * @brief  ADC group injected contexts queue configuration
00295   * @note   Structure intended to be used only through structure "ADC_HandleTypeDef"
00296   */
00297 typedef struct
00298 {
00299   uint32_t ContextQueue;                 /*!< Injected channel configuration context: build-up over each
00300                                               HAL_ADCEx_InjectedConfigChannel() call to finally initialize
00301                                               JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */
00302
00303   uint32_t ChannelCount;                 /*!< Number of channels in the injected sequence */
00304 } ADC_InjectionConfigTypeDef;
00305
00306 /** @defgroup ADC_States ADC States
00307   * @{
00308   */
00309
00310 /**
00311   * @brief  HAL ADC state machine: ADC states definition (bitfields)
00312   * @note   ADC state machine is managed by bitfields, state must be compared
00313   *         with bit by bit.
00314   *         For example:
00315   *           " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
00316   *           " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
00317   */
00318 /* States of ADC global scope */
00319 #define HAL_ADC_STATE_RESET             (0x00000000UL)   /*!< ADC not yet initialized or disabled */
00320 #define HAL_ADC_STATE_READY             (0x00000001UL)   /*!< ADC peripheral ready for use */
00321 #define HAL_ADC_STATE_BUSY_INTERNAL     (0x00000002UL)   /*!< ADC is busy due to an internal process (initialization, calibration) */
00322 #define HAL_ADC_STATE_TIMEOUT           (0x00000004UL)   /*!< TimeOut occurrence */
00323
00324 /* States of ADC errors */
00325 #define HAL_ADC_STATE_ERROR_INTERNAL    (0x00000010UL)   /*!< Internal error occurrence */
00326 #define HAL_ADC_STATE_ERROR_CONFIG      (0x00000020UL)   /*!< Configuration error occurrence */
00327 #define HAL_ADC_STATE_ERROR_DMA         (0x00000040UL)   /*!< DMA error occurrence */
00328
00329 /* States of ADC group regular */
00330 #define HAL_ADC_STATE_REG_BUSY          (0x00000100UL)   /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode,
00331                                                               external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
00332 #define HAL_ADC_STATE_REG_EOC           (0x00000200UL)   /*!< Conversion data available on group regular */
00333 #define HAL_ADC_STATE_REG_OVR           (0x00000400UL)   /*!< Overrun occurrence */
00334 #define HAL_ADC_STATE_REG_EOSMP         (0x00000800UL)   /*!< Not available on this STM32 serie: End Of Sampling flag raised  */
00335
00336 /* States of ADC group injected */
00337 #define HAL_ADC_STATE_INJ_BUSY          (0x00001000UL)   /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode,
00338                                                               external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
00339 #define HAL_ADC_STATE_INJ_EOC           (0x00002000UL)   /*!< Conversion data available on group injected */
00340 #define HAL_ADC_STATE_INJ_JQOVF         (0x00004000UL)   /*!< Injected queue overflow occurrence */
00341
00342 /* States of ADC analog watchdogs */
00343 #define HAL_ADC_STATE_AWD1              (0x00010000UL)   /*!< Out-of-window occurrence of ADC analog watchdog 1 */
00344 #define HAL_ADC_STATE_AWD2              (0x00020000UL)   /*!< Out-of-window occurrence of ADC analog watchdog 2 */
00345 #define HAL_ADC_STATE_AWD3              (0x00040000UL)   /*!< Out-of-window occurrence of ADC analog watchdog 3 */
00346
00347 /* States of ADC multi-mode */
00348 #define HAL_ADC_STATE_MULTIMODE_SLAVE   (0x00100000UL)   /*!< Not available on this STM32 serie: ADC in multimode slave state, controlled by another ADC master (when feature available) */
00349
00350
00351 /**
00352   * @}
00353   */
00354
00355 /**
00356   * @brief  ADC handle Structure definition
00357   */
00358 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
00359 typedef struct __ADC_HandleTypeDef
00360 #else
00361 typedef struct
00362 #endif
00363 {
00364   ADC_TypeDef                   *Instance;              /*!< Register base address */
00365   ADC_InitTypeDef               Init;                   /*!< ADC initialization parameters and regular conversions setting */
00366   DMA_HandleTypeDef             *DMA_Handle;            /*!< Pointer DMA Handler */
00367   HAL_LockTypeDef               Lock;                   /*!< ADC locking object */
00368   __IO uint32_t                 State;                  /*!< ADC communication state (bitmap of ADC states) */
00369   __IO uint32_t                 ErrorCode;              /*!< ADC Error code */
00370   ADC_InjectionConfigTypeDef    InjectionConfig ;       /*!< ADC injected channel configuration build-up structure */
00371 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
00372   void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc);              /*!< ADC conversion complete callback */
00373   void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc);          /*!< ADC conversion DMA half-transfer callback */
00374   void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc);      /*!< ADC analog watchdog 1 callback */
00375   void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc);                 /*!< ADC error callback */
00376   void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc);      /*!< ADC group injected conversion complete callback */
00377   void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue overflow callback */
00378   void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc);     /*!< ADC analog watchdog 2 callback */
00379   void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc);     /*!< ADC analog watchdog 3 callback */
00380   void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc);         /*!< ADC end of sampling callback */
00381   void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc);               /*!< ADC Msp Init callback */
00382   void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc);             /*!< ADC Msp DeInit callback */
00383 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
00384 } ADC_HandleTypeDef;
00385
00386 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
00387 /**
00388   * @brief  HAL ADC Callback ID enumeration definition
00389   */
00390 typedef enum
00391 {
00392   HAL_ADC_CONVERSION_COMPLETE_CB_ID     = 0x00U,  /*!< ADC conversion complete callback ID */
00393   HAL_ADC_CONVERSION_HALF_CB_ID         = 0x01U,  /*!< ADC conversion DMA half-transfer callback ID */
00394   HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID   = 0x02U,  /*!< ADC analog watchdog 1 callback ID */
00395   HAL_ADC_ERROR_CB_ID                   = 0x03U,  /*!< ADC error callback ID */
00396   HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U,  /*!< ADC group injected conversion complete callback ID */
00397   HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID       = 0x05U,  /*!< ADC group injected context queue overflow callback ID */
00398   HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID   = 0x06U,  /*!< ADC analog watchdog 2 callback ID */
00399   HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID   = 0x07U,  /*!< ADC analog watchdog 3 callback ID */
00400   HAL_ADC_END_OF_SAMPLING_CB_ID         = 0x08U,  /*!< ADC end of sampling callback ID */
00401   HAL_ADC_MSPINIT_CB_ID                 = 0x09U,  /*!< ADC Msp Init callback ID          */
00402   HAL_ADC_MSPDEINIT_CB_ID               = 0x0AU   /*!< ADC Msp DeInit callback ID        */
00403 } HAL_ADC_CallbackIDTypeDef;
00404
00405 /**
00406   * @brief  HAL ADC Callback pointer definition
00407   */
00408 typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */
00409
00410 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
00411
00412 /**
00413   * @}
00414   */
00415
00416
00417 /* Exported constants --------------------------------------------------------*/
00418
00419 /** @defgroup ADC_Exported_Constants ADC Exported Constants
00420   * @{
00421   */
00422
00423 /** @defgroup ADC_Error_Code ADC Error Code
00424   * @{
00425   */
00426 #define HAL_ADC_ERROR_NONE              (0x00U)   /*!< No error                                    */
00427 #define HAL_ADC_ERROR_INTERNAL          (0x01U)   /*!< ADC peripheral internal error (problem of clocking,
00428                                                        enable/disable, erroneous state, ...)       */
00429 #define HAL_ADC_ERROR_OVR               (0x02U)   /*!< Overrun error                               */
00430 #define HAL_ADC_ERROR_DMA               (0x04U)   /*!< DMA transfer error                          */
00431 #define HAL_ADC_ERROR_JQOVF             (0x08U)   /*!< Injected context queue overflow error       */
00432 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
00433 #define HAL_ADC_ERROR_INVALID_CALLBACK  (0x10U)   /*!< Invalid Callback error */
00434 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
00435 /**
00436   * @}
00437   */
00438
00439 /** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE  ADC common - Clock source
00440   * @{
00441   */
00442 #define ADC_CLOCK_SYNC_PCLK_DIV1           (LL_ADC_CLOCK_SYNC_PCLK_DIV1)  /*!< ADC synchronous clock derived from AHB clock without prescaler */
00443 #define ADC_CLOCK_SYNC_PCLK_DIV2           (LL_ADC_CLOCK_SYNC_PCLK_DIV2)  /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
00444 #define ADC_CLOCK_SYNC_PCLK_DIV4           (LL_ADC_CLOCK_SYNC_PCLK_DIV4)  /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
00445
00446 #define ADC_CLOCK_ASYNC_DIV1               (LL_ADC_CLOCK_ASYNC_DIV1)      /*!< ADC asynchronous clock without prescaler */
00447 #define ADC_CLOCK_ASYNC_DIV2               (LL_ADC_CLOCK_ASYNC_DIV2)      /*!< ADC asynchronous clock with prescaler division by 2   */
00448 #define ADC_CLOCK_ASYNC_DIV4               (LL_ADC_CLOCK_ASYNC_DIV4)      /*!< ADC asynchronous clock with prescaler division by 4   */
00449 #define ADC_CLOCK_ASYNC_DIV6               (LL_ADC_CLOCK_ASYNC_DIV6)      /*!< ADC asynchronous clock with prescaler division by 6   */
00450 #define ADC_CLOCK_ASYNC_DIV8               (LL_ADC_CLOCK_ASYNC_DIV8)      /*!< ADC asynchronous clock with prescaler division by 8   */
00451 #define ADC_CLOCK_ASYNC_DIV10              (LL_ADC_CLOCK_ASYNC_DIV10)     /*!< ADC asynchronous clock with prescaler division by 10  */
00452 #define ADC_CLOCK_ASYNC_DIV12              (LL_ADC_CLOCK_ASYNC_DIV12)     /*!< ADC asynchronous clock with prescaler division by 12  */
00453 #define ADC_CLOCK_ASYNC_DIV16              (LL_ADC_CLOCK_ASYNC_DIV16)     /*!< ADC asynchronous clock with prescaler division by 16  */
00454 #define ADC_CLOCK_ASYNC_DIV32              (LL_ADC_CLOCK_ASYNC_DIV32)     /*!< ADC asynchronous clock with prescaler division by 32  */
00455 #define ADC_CLOCK_ASYNC_DIV64              (LL_ADC_CLOCK_ASYNC_DIV64)     /*!< ADC asynchronous clock with prescaler division by 64  */
00456 #define ADC_CLOCK_ASYNC_DIV128             (LL_ADC_CLOCK_ASYNC_DIV128)    /*!< ADC asynchronous clock with prescaler division by 128 */
00457 #define ADC_CLOCK_ASYNC_DIV256             (LL_ADC_CLOCK_ASYNC_DIV256)    /*!< ADC asynchronous clock with prescaler division by 256 */
00458 /**
00459   * @}
00460   */
00461
00462 /** @defgroup ADC_HAL_EC_RESOLUTION  ADC instance - Resolution
00463   * @{
00464   */
00465 #define ADC_RESOLUTION_12B                 (LL_ADC_RESOLUTION_12B)  /*!< ADC resolution 12 bits */
00466 #define ADC_RESOLUTION_10B                 (LL_ADC_RESOLUTION_10B)  /*!< ADC resolution 10 bits */
00467 #define ADC_RESOLUTION_8B                  (LL_ADC_RESOLUTION_8B)   /*!< ADC resolution  8 bits */
00468 #define ADC_RESOLUTION_6B                  (LL_ADC_RESOLUTION_6B)   /*!< ADC resolution  6 bits */
00469 /**
00470   * @}
00471   */
00472
00473 /** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment
00474   * @{
00475   */
00476 #define ADC_DATAALIGN_RIGHT                (LL_ADC_DATA_ALIGN_RIGHT)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
00477 #define ADC_DATAALIGN_LEFT                 (LL_ADC_DATA_ALIGN_LEFT)       /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
00478 /**
00479   * @}
00480   */
00481
00482 /** @defgroup ADC_Scan_mode ADC sequencer scan mode
00483   * @{
00484   */
00485 #define ADC_SCAN_DISABLE         (0x00000000UL)       /*!< Scan mode disabled */
00486 #define ADC_SCAN_ENABLE          (0x00000001UL)       /*!< Scan mode enabled  */
00487 /**
00488   * @}
00489   */
00490
00491 /** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source
00492   * @{
00493   */
00494 /* ADC group regular trigger sources for all ADC instances */
00495 #define ADC_SOFTWARE_START            (LL_ADC_REG_TRIG_SOFTWARE)                 /*!< ADC group regular conversion trigger internal: SW start. */
00496 #define ADC_EXTERNALTRIG_T1_TRGO      (LL_ADC_REG_TRIG_EXT_TIM1_TRGO)            /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
00497 #define ADC_EXTERNALTRIG_T1_TRGO2     (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)           /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
00498 #define ADC_EXTERNALTRIG_T1_CC1       (LL_ADC_REG_TRIG_EXT_TIM1_CH1)             /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00499 #define ADC_EXTERNALTRIG_T1_CC2       (LL_ADC_REG_TRIG_EXT_TIM1_CH2)             /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00500 #define ADC_EXTERNALTRIG_T1_CC3       (LL_ADC_REG_TRIG_EXT_TIM1_CH3)             /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00501 #define ADC_EXTERNALTRIG_T2_TRGO      (LL_ADC_REG_TRIG_EXT_TIM2_TRGO)            /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
00502 #define ADC_EXTERNALTRIG_T2_CC2       (LL_ADC_REG_TRIG_EXT_TIM2_CH2)             /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00503 #define ADC_EXTERNALTRIG_EXT_IT11     (LL_ADC_REG_TRIG_EXT_EXTI_LINE11)          /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */
00504 /**
00505   * @}
00506   */
00507
00508 /** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected)
00509   * @{
00510   */
00511 #define ADC_EXTERNALTRIGCONVEDGE_NONE           (0x00000000UL)                      /*!< Regular conversions hardware trigger detection disabled */
00512 #define ADC_EXTERNALTRIGCONVEDGE_RISING         (LL_ADC_REG_TRIG_EXT_RISING)        /*!< ADC group regular conversion trigger polarity set to rising edge */
00513 #define ADC_EXTERNALTRIGCONVEDGE_FALLING        (LL_ADC_REG_TRIG_EXT_FALLING)       /*!< ADC group regular conversion trigger polarity set to falling edge */
00514 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING  (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
00515 /**
00516   * @}
00517   */
00518
00519 /** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions
00520   * @{
00521   */
00522 #define ADC_EOC_SINGLE_CONV         (ADC_ISR_EOC)                 /*!< End of unitary conversion flag  */
00523 #define ADC_EOC_SEQ_CONV            (ADC_ISR_EOS)                 /*!< End of sequence conversions flag    */
00524 /**
00525   * @}
00526   */
00527
00528 /** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR  ADC group regular - Overrun behavior on conversion data
00529   * @{
00530   */
00531 #define ADC_OVR_DATA_PRESERVED             (LL_ADC_REG_OVR_DATA_PRESERVED)    /*!< ADC group regular behavior in case of overrun: data preserved */
00532 #define ADC_OVR_DATA_OVERWRITTEN           (LL_ADC_REG_OVR_DATA_OVERWRITTEN)  /*!< ADC group regular behavior in case of overrun: data overwritten */
00533 /**
00534   * @}
00535   */
00536
00537 /** @defgroup ADC_HAL_EC_REG_SEQ_RANKS  ADC group regular - Sequencer ranks
00538   * @{
00539   */
00540 #define ADC_REGULAR_RANK_1                 (LL_ADC_REG_RANK_1)  /*!< ADC group regular sequencer rank 1 */
00541 #define ADC_REGULAR_RANK_2                 (LL_ADC_REG_RANK_2)  /*!< ADC group regular sequencer rank 2 */
00542 #define ADC_REGULAR_RANK_3                 (LL_ADC_REG_RANK_3)  /*!< ADC group regular sequencer rank 3 */
00543 #define ADC_REGULAR_RANK_4                 (LL_ADC_REG_RANK_4)  /*!< ADC group regular sequencer rank 4 */
00544 #define ADC_REGULAR_RANK_5                 (LL_ADC_REG_RANK_5)  /*!< ADC group regular sequencer rank 5 */
00545 #define ADC_REGULAR_RANK_6                 (LL_ADC_REG_RANK_6)  /*!< ADC group regular sequencer rank 6 */
00546 #define ADC_REGULAR_RANK_7                 (LL_ADC_REG_RANK_7)  /*!< ADC group regular sequencer rank 7 */
00547 #define ADC_REGULAR_RANK_8                 (LL_ADC_REG_RANK_8)  /*!< ADC group regular sequencer rank 8 */
00548 #define ADC_REGULAR_RANK_9                 (LL_ADC_REG_RANK_9)  /*!< ADC group regular sequencer rank 9 */
00549 #define ADC_REGULAR_RANK_10                (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */
00550 #define ADC_REGULAR_RANK_11                (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */
00551 #define ADC_REGULAR_RANK_12                (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */
00552 #define ADC_REGULAR_RANK_13                (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */
00553 #define ADC_REGULAR_RANK_14                (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */
00554 #define ADC_REGULAR_RANK_15                (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */
00555 #define ADC_REGULAR_RANK_16                (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */
00556 /**
00557   * @}
00558   */
00559
00560 /** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME  Channel - Sampling time
00561   * @{
00562   */
00563 #define ADC_SAMPLETIME_2CYCLES_5         (LL_ADC_SAMPLINGTIME_2CYCLES_5)    /*!< Sampling time 2.5 ADC clock cycles */
00564 #define ADC_SAMPLETIME_6CYCLES_5         (LL_ADC_SAMPLINGTIME_6CYCLES_5)    /*!< Sampling time 6.5 ADC clock cycles */
00565 #define ADC_SAMPLETIME_12CYCLES_5        (LL_ADC_SAMPLINGTIME_12CYCLES_5)   /*!< Sampling time 12.5 ADC clock cycles */
00566 #define ADC_SAMPLETIME_24CYCLES_5        (LL_ADC_SAMPLINGTIME_24CYCLES_5)   /*!< Sampling time 24.5 ADC clock cycles */
00567 #define ADC_SAMPLETIME_47CYCLES_5        (LL_ADC_SAMPLINGTIME_47CYCLES_5)   /*!< Sampling time 47.5 ADC clock cycles */
00568 #define ADC_SAMPLETIME_92CYCLES_5        (LL_ADC_SAMPLINGTIME_92CYCLES_5)   /*!< Sampling time 92.5 ADC clock cycles */
00569 #define ADC_SAMPLETIME_247CYCLES_5       (LL_ADC_SAMPLINGTIME_247CYCLES_5)  /*!< Sampling time 247.5 ADC clock cycles */
00570 #define ADC_SAMPLETIME_640CYCLES_5       (LL_ADC_SAMPLINGTIME_640CYCLES_5)  /*!< Sampling time 640.5 ADC clock cycles */
00571 /**
00572   * @}
00573   */
00574
00575 /** @defgroup ADC_HAL_EC_CHANNEL  ADC instance - Channel number
00576   * @{
00577   */
00578 /* Note: VrefInt, TempSensor and Vbat internal channels are not available on  */
00579 /*        all ADC instances (refer to Reference Manual).                      */
00580 #define ADC_CHANNEL_0                      (LL_ADC_CHANNEL_0)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0  */
00581 #define ADC_CHANNEL_1                      (LL_ADC_CHANNEL_1)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1  */
00582 #define ADC_CHANNEL_2                      (LL_ADC_CHANNEL_2)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2  */
00583 #define ADC_CHANNEL_3                      (LL_ADC_CHANNEL_3)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3  */
00584 #define ADC_CHANNEL_4                      (LL_ADC_CHANNEL_4)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4  */
00585 #define ADC_CHANNEL_5                      (LL_ADC_CHANNEL_5)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5  */
00586 #define ADC_CHANNEL_6                      (LL_ADC_CHANNEL_6)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6  */
00587 #define ADC_CHANNEL_7                      (LL_ADC_CHANNEL_7)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7  */
00588 #define ADC_CHANNEL_8                      (LL_ADC_CHANNEL_8)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8  */
00589 #define ADC_CHANNEL_9                      (LL_ADC_CHANNEL_9)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9  */
00590 #define ADC_CHANNEL_10                     (LL_ADC_CHANNEL_10)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
00591 #define ADC_CHANNEL_11                     (LL_ADC_CHANNEL_11)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
00592 #define ADC_CHANNEL_12                     (LL_ADC_CHANNEL_12)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
00593 #define ADC_CHANNEL_13                     (LL_ADC_CHANNEL_13)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
00594 #define ADC_CHANNEL_14                     (LL_ADC_CHANNEL_14)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
00595 #define ADC_CHANNEL_15                     (LL_ADC_CHANNEL_15)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
00596 #define ADC_CHANNEL_16                     (LL_ADC_CHANNEL_16)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
00597 #define ADC_CHANNEL_17                     (LL_ADC_CHANNEL_17)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
00598 #define ADC_CHANNEL_18                     (LL_ADC_CHANNEL_18)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
00599 #define ADC_CHANNEL_VREFINT                (LL_ADC_CHANNEL_VREFINT)         /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */
00600 #define ADC_CHANNEL_TEMPSENSOR             (LL_ADC_CHANNEL_TEMPSENSOR)      /*!< ADC internal channel connected to Temperature sensor. */
00601 #define ADC_CHANNEL_VBAT                   (LL_ADC_CHANNEL_VBAT)            /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. */
00602 /**
00603   * @}
00604   */
00605
00606 /** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
00607   * @{
00608   */
00609 #define ADC_ANALOGWATCHDOG_1               (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */
00610 #define ADC_ANALOGWATCHDOG_2               (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */
00611 #define ADC_ANALOGWATCHDOG_3               (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */
00612 /**
00613   * @}
00614   */
00615
00616 /** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode
00617   * @{
00618   */
00619 #define ADC_ANALOGWATCHDOG_NONE                 (0x00000000UL)                                          /*!< No analog watchdog selected                                             */
00620 #define ADC_ANALOGWATCHDOG_SINGLE_REG           (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN)                    /*!< Analog watchdog applied to a regular group single channel               */
00621 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC         (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN)                   /*!< Analog watchdog applied to an injected group single channel             */
00622 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC      (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to a regular and injected groups single channel */
00623 #define ADC_ANALOGWATCHDOG_ALL_REG              (ADC_CFGR_AWD1EN)                                       /*!< Analog watchdog applied to regular group all channels                   */
00624 #define ADC_ANALOGWATCHDOG_ALL_INJEC            (ADC_CFGR_JAWD1EN)                                      /*!< Analog watchdog applied to injected group all channels                  */
00625 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC         (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)                    /*!< Analog watchdog applied to regular and injected groups all channels     */
00626 /**
00627   * @}
00628   */
00629
00630 /** @defgroup ADC_HAL_EC_OVS_RATIO  Oversampling - Ratio
00631   * @{
00632   */
00633 #define ADC_OVERSAMPLING_RATIO_2           (LL_ADC_OVS_RATIO_2)   /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
00634 #define ADC_OVERSAMPLING_RATIO_4           (LL_ADC_OVS_RATIO_4)   /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
00635 #define ADC_OVERSAMPLING_RATIO_8           (LL_ADC_OVS_RATIO_8)   /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
00636 #define ADC_OVERSAMPLING_RATIO_16          (LL_ADC_OVS_RATIO_16)  /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
00637 #define ADC_OVERSAMPLING_RATIO_32          (LL_ADC_OVS_RATIO_32)  /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
00638 #define ADC_OVERSAMPLING_RATIO_64          (LL_ADC_OVS_RATIO_64)  /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
00639 #define ADC_OVERSAMPLING_RATIO_128         (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
00640 #define ADC_OVERSAMPLING_RATIO_256         (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
00641 /**
00642   * @}
00643   */
00644
00645 /** @defgroup ADC_HAL_EC_OVS_SHIFT  Oversampling - Data shift
00646   * @{
00647   */
00648 #define ADC_RIGHTBITSHIFT_NONE             (LL_ADC_OVS_SHIFT_NONE)    /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
00649 #define ADC_RIGHTBITSHIFT_1                (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
00650 #define ADC_RIGHTBITSHIFT_2                (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
00651 #define ADC_RIGHTBITSHIFT_3                (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
00652 #define ADC_RIGHTBITSHIFT_4                (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
00653 #define ADC_RIGHTBITSHIFT_5                (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
00654 #define ADC_RIGHTBITSHIFT_6                (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
00655 #define ADC_RIGHTBITSHIFT_7                (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
00656 #define ADC_RIGHTBITSHIFT_8                (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
00657 /**
00658   * @}
00659   */
00660
00661 /** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE  Oversampling - Discontinuous mode
00662   * @{
00663   */
00664 #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER   (LL_ADC_OVS_REG_CONT)          /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
00665 #define ADC_TRIGGEREDMODE_MULTI_TRIGGER    (LL_ADC_OVS_REG_DISCONT)       /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
00666 /**
00667   * @}
00668   */
00669
00670 /** @defgroup ADC_HAL_EC_OVS_SCOPE_REG  Oversampling - Oversampling scope for ADC group regular
00671   * @{
00672   */
00673 #define ADC_REGOVERSAMPLING_CONTINUED_MODE    (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained during injection sequence */
00674 #define ADC_REGOVERSAMPLING_RESUMED_MODE      (LL_ADC_OVS_GRP_REGULAR_RESUMED)   /*!< Oversampling buffer zeroed during injection sequence     */
00675 /**
00676   * @}
00677   */
00678
00679
00680 /** @defgroup ADC_Event_type ADC Event type
00681   * @{
00682   */
00683 #define ADC_EOSMP_EVENT          (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */
00684 #define ADC_AWD1_EVENT           (ADC_FLAG_AWD1)  /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */
00685 #define ADC_AWD2_EVENT           (ADC_FLAG_AWD2)  /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */
00686 #define ADC_AWD3_EVENT           (ADC_FLAG_AWD3)  /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */
00687 #define ADC_OVR_EVENT            (ADC_FLAG_OVR)   /*!< ADC overrun event */
00688 #define ADC_JQOVF_EVENT          (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */
00689 /**
00690   * @}
00691   */
00692 #define ADC_AWD_EVENT            ADC_AWD1_EVENT      /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */
00693
00694 /** @defgroup ADC_interrupts_definition ADC interrupts definition
00695   * @{
00696   */
00697 #define ADC_IT_RDY           ADC_IER_ADRDYIE    /*!< ADC Ready interrupt source */
00698 #define ADC_IT_EOSMP         ADC_IER_EOSMPIE    /*!< ADC End of sampling interrupt source */
00699 #define ADC_IT_EOC           ADC_IER_EOCIE      /*!< ADC End of regular conversion interrupt source */
00700 #define ADC_IT_EOS           ADC_IER_EOSIE      /*!< ADC End of regular sequence of conversions interrupt source */
00701 #define ADC_IT_OVR           ADC_IER_OVRIE      /*!< ADC overrun interrupt source */
00702 #define ADC_IT_JEOC          ADC_IER_JEOCIE     /*!< ADC End of injected conversion interrupt source */
00703 #define ADC_IT_JEOS          ADC_IER_JEOSIE     /*!< ADC End of injected sequence of conversions interrupt source */
00704 #define ADC_IT_AWD1          ADC_IER_AWD1IE     /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */
00705 #define ADC_IT_AWD2          ADC_IER_AWD2IE     /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */
00706 #define ADC_IT_AWD3          ADC_IER_AWD3IE     /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */
00707 #define ADC_IT_JQOVF         ADC_IER_JQOVFIE    /*!< ADC Injected Context Queue Overflow interrupt source */
00708
00709 #define ADC_IT_AWD           ADC_IT_AWD1        /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */
00710
00711 /**
00712   * @}
00713   */
00714
00715 /** @defgroup ADC_flags_definition ADC flags definition
00716   * @{
00717   */
00718 #define ADC_FLAG_RDY           ADC_ISR_ADRDY    /*!< ADC Ready flag */
00719 #define ADC_FLAG_EOSMP         ADC_ISR_EOSMP    /*!< ADC End of Sampling flag */
00720 #define ADC_FLAG_EOC           ADC_ISR_EOC      /*!< ADC End of Regular Conversion flag */
00721 #define ADC_FLAG_EOS           ADC_ISR_EOS      /*!< ADC End of Regular sequence of Conversions flag */
00722 #define ADC_FLAG_OVR           ADC_ISR_OVR      /*!< ADC overrun flag */
00723 #define ADC_FLAG_JEOC          ADC_ISR_JEOC     /*!< ADC End of Injected Conversion flag */
00724 #define ADC_FLAG_JEOS          ADC_ISR_JEOS     /*!< ADC End of Injected sequence of Conversions flag */
00725 #define ADC_FLAG_AWD1          ADC_ISR_AWD1     /*!< ADC Analog watchdog 1 flag (main analog watchdog) */
00726 #define ADC_FLAG_AWD2          ADC_ISR_AWD2     /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */
00727 #define ADC_FLAG_AWD3          ADC_ISR_AWD3     /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */
00728 #define ADC_FLAG_JQOVF         ADC_ISR_JQOVF    /*!< ADC Injected Context Queue Overflow flag */
00729
00730 /**
00731   * @}
00732   */
00733
00734 /**
00735   * @}
00736   */
00737
00738 /* Private macro -------------------------------------------------------------*/
00739
00740 /** @defgroup ADC_Private_Macros ADC Private Macros
00741   * @{
00742   */
00743 /* Macro reserved for internal HAL driver usage, not intended to be used in   */
00744 /* code of final user.                                                        */
00745
00746 /**
00747   * @brief Return resolution bits in CFGR register RES[1:0] field.
00748   * @param __HANDLE__ ADC handle
00749   * @retval Value of bitfield RES in CFGR register.
00750   */
00751 #define ADC_GET_RESOLUTION(__HANDLE__)                                         \
00752   (LL_ADC_GetResolution((__HANDLE__)->Instance))
00753
00754 /**
00755   * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").
00756   * @param __HANDLE__ ADC handle
00757   * @retval None
00758   */
00759 #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
00760
00761 /**
00762   * @brief Simultaneously clear and set specific bits of the handle State.
00763   * @note  ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
00764   *        the first parameter is the ADC handle State, the second parameter is the
00765   *        bit field to clear, the third and last parameter is the bit field to set.
00766   * @retval None
00767   */
00768 #define ADC_STATE_CLR_SET MODIFY_REG
00769
00770 /**
00771   * @brief Verify that a given value is aligned with the ADC resolution range.
00772   * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits).
00773   * @param __ADC_VALUE__ value checked against the resolution.
00774   * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__)
00775   */
00776 #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \
00777   ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__))
00778
00779 /**
00780   * @brief Verify the length of the scheduled regular conversions group.
00781   * @param __LENGTH__ number of programmed conversions.
00782   * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large)
00783   */
00784 #define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL)))
00785
00786
00787 /**
00788   * @brief Verify the number of scheduled regular conversions in discontinuous mode.
00789   * @param NUMBER number of scheduled regular conversions in discontinuous mode.
00790   * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) or RESET (NUMBER is null or too large)
00791   */
00792 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL)))
00793
00794
00795 /**
00796   * @brief Verify the ADC clock setting.
00797   * @param __ADC_CLOCK__ programmed ADC clock.
00798   * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid)
00799   */
00800 #define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \
00801                                               ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
00802                                               ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
00803                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1)     || \
00804                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2)     || \
00805                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4)     || \
00806                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6)     || \
00807                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8)     || \
00808                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10)    || \
00809                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12)    || \
00810                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16)    || \
00811                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32)    || \
00812                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64)    || \
00813                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128)   || \
00814                                               ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) )
00815
00816 /**
00817   * @brief Verify the ADC resolution setting.
00818   * @param __RESOLUTION__ programmed ADC resolution.
00819   * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
00820   */
00821 #define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
00822                                            ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
00823                                            ((__RESOLUTION__) == ADC_RESOLUTION_8B)  || \
00824                                            ((__RESOLUTION__) == ADC_RESOLUTION_6B)    )
00825
00826 /**
00827   * @brief Verify the ADC resolution setting when limited to 6 or 8 bits.
00828   * @param __RESOLUTION__ programmed ADC resolution when limited to 6 or 8 bits.
00829   * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
00830   */
00831 #define IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B) || \
00832                                                     ((__RESOLUTION__) == ADC_RESOLUTION_6B)   )
00833
00834 /**
00835   * @brief Verify the ADC converted data alignment.
00836   * @param __ALIGN__ programmed ADC converted data alignment.
00837   * @retval SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid)
00838   */
00839 #define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \
00840                                       ((__ALIGN__) == ADC_DATAALIGN_LEFT)    )
00841
00842 /**
00843   * @brief Verify the ADC scan mode.
00844   * @param __SCAN_MODE__ programmed ADC scan mode.
00845   * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid)
00846   */
00847 #define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \
00848                                          ((__SCAN_MODE__) == ADC_SCAN_ENABLE)    )
00849
00850 /**
00851   * @brief Verify the ADC edge trigger setting for regular group.
00852   * @param __EDGE__ programmed ADC edge trigger setting.
00853   * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
00854   */
00855 #define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE)         || \
00856                                        ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING)       || \
00857                                        ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING)      || \
00858                                        ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)  )
00859
00860 /**
00861   * @brief Verify the ADC regular conversions external trigger.
00862   * @param __HANDLE__ ADC handle
00863   * @param __REGTRIG__ programmed ADC regular conversions external trigger.
00864   * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid)
00865   */
00866 #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1)   || \
00867                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2)   || \
00868                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3)   || \
00869                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2)   || \
00870                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \
00871                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO)  || \
00872                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
00873                                                  ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO)  || \
00874                                                  ((__REGTRIG__) == ADC_SOFTWARE_START)           )
00875
00876 /**
00877   * @brief Verify the ADC regular conversions check for converted data availability.
00878   * @param __EOC_SELECTION__ converted data availability check.
00879   * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid)
00880   */
00881 #define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV)    || \
00882                                                  ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV)  )
00883
00884 /**
00885   * @brief Verify the ADC regular conversions overrun handling.
00886   * @param __OVR__ ADC regular conversions overrun handling.
00887   * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid)
00888   */
00889 #define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED)  || \
00890                                  ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN)  )
00891
00892 /**
00893   * @brief Verify the ADC conversions sampling time.
00894   * @param __TIME__ ADC conversions sampling time.
00895   * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid)
00896   */
00897 #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5)   || \
00898                                       ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5)   || \
00899                                       ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5)  || \
00900                                       ((__TIME__) == ADC_SAMPLETIME_24CYCLES_5)  || \
00901                                       ((__TIME__) == ADC_SAMPLETIME_47CYCLES_5)  || \
00902                                       ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5)  || \
00903                                       ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \
00904                                       ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5)   )
00905
00906 /**
00907   * @brief Verify the ADC regular channel setting.
00908   * @param  __CHANNEL__ programmed ADC regular channel.
00909   * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
00910   */
00911 #define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \
00912                                           ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \
00913                                           ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \
00914                                           ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \
00915                                           ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \
00916                                           ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \
00917                                           ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \
00918                                           ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \
00919                                           ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \
00920                                           ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \
00921                                           ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \
00922                                           ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \
00923                                           ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \
00924                                           ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \
00925                                           ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \
00926                                           ((__CHANNEL__) == ADC_REGULAR_RANK_16)   )
00927
00928 /**
00929   * @}
00930   */
00931
00932
00933 /* Private constants ---------------------------------------------------------*/
00934
00935 /** @defgroup ADC_Private_Constants ADC Private Constants
00936   * @{
00937   */
00938
00939 /* Fixed timeout values for ADC conversion (including sampling time)        */
00940 /* Maximum sampling time is 640.5 ADC clock cycle (SMPx[2:0] = 0b111        */
00941 /* Maximum conversion time is 12.5 + Maximum sampling time                  */
00942 /*                       or 12.5  + 640.5 = 653 ADC clock cycles            */
00943 /* Minimum ADC Clock frequency is 0.14 MHz                                  */
00944 /* Maximum conversion time is                                               */
00945 /*              653 / 0.14 MHz = 4.66 ms                                    */
00946 #define ADC_STOP_CONVERSION_TIMEOUT     ( 5UL)     /*!< ADC stop time-out value */
00947
00948 /* Delay for temperature sensor stabilization time.                         */
00949 /* Maximum delay is 120us (refer device datasheet, parameter tSTART).       */
00950 /* Unit: us                                                                 */
00951 #define ADC_TEMPSENSOR_DELAY_US         (LL_ADC_DELAY_TEMPSENSOR_STAB_US)
00952
00953 /**
00954   * @}
00955   */
00956
00957 /* Exported macro ------------------------------------------------------------*/
00958
00959 /** @defgroup ADC_Exported_Macros ADC Exported Macros
00960   * @{
00961   */
00962 /* Macro for internal HAL driver usage, and possibly can be used into code of */
00963 /* final user.                                                                */
00964
00965 /** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags.
00966   * @{
00967   */
00968
00969 /** @brief  Reset ADC handle state.
00970   * @param __HANDLE__ ADC handle
00971   * @retval None
00972   */
00973 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
00974 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
00975   do{                                                                          \
00976     (__HANDLE__)->State = HAL_ADC_STATE_RESET;                                 \
00977     (__HANDLE__)->MspInitCallback = NULL;                                      \
00978     (__HANDLE__)->MspDeInitCallback = NULL;                                    \
00979   } while(0)
00980 #else
00981 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
00982   ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
00983 #endif
00984
00985 /**
00986   * @brief Enable ADC interrupt.
00987   * @param __HANDLE__ ADC handle
00988   * @param __INTERRUPT__ ADC Interrupt
00989   *        This parameter can be one of the following values:
00990   *            @arg @ref ADC_IT_RDY    ADC Ready interrupt source
00991   *            @arg @ref ADC_IT_EOSMP  ADC End of Sampling interrupt source
00992   *            @arg @ref ADC_IT_EOC    ADC End of Regular Conversion interrupt source
00993   *            @arg @ref ADC_IT_EOS    ADC End of Regular sequence of Conversions interrupt source
00994   *            @arg @ref ADC_IT_OVR    ADC overrun interrupt source
00995   *            @arg @ref ADC_IT_JEOC   ADC End of Injected Conversion interrupt source
00996   *            @arg @ref ADC_IT_JEOS   ADC End of Injected sequence of Conversions interrupt source
00997   *            @arg @ref ADC_IT_AWD1   ADC Analog watchdog 1 interrupt source (main analog watchdog)
00998   *            @arg @ref ADC_IT_AWD2   ADC Analog watchdog 2 interrupt source (additional analog watchdog)
00999   *            @arg @ref ADC_IT_AWD3   ADC Analog watchdog 3 interrupt source (additional analog watchdog)
01000   *            @arg @ref ADC_IT_JQOVF  ADC Injected Context Queue Overflow interrupt source.
01001   * @retval None
01002   */
01003 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__)                         \
01004   (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
01005
01006 /**
01007   * @brief Disable ADC interrupt.
01008   * @param __HANDLE__ ADC handle
01009   * @param __INTERRUPT__ ADC Interrupt
01010   *        This parameter can be one of the following values:
01011   *            @arg @ref ADC_IT_RDY    ADC Ready interrupt source
01012   *            @arg @ref ADC_IT_EOSMP  ADC End of Sampling interrupt source
01013   *            @arg @ref ADC_IT_EOC    ADC End of Regular Conversion interrupt source
01014   *            @arg @ref ADC_IT_EOS    ADC End of Regular sequence of Conversions interrupt source
01015   *            @arg @ref ADC_IT_OVR    ADC overrun interrupt source
01016   *            @arg @ref ADC_IT_JEOC   ADC End of Injected Conversion interrupt source
01017   *            @arg @ref ADC_IT_JEOS   ADC End of Injected sequence of Conversions interrupt source
01018   *            @arg @ref ADC_IT_AWD1   ADC Analog watchdog 1 interrupt source (main analog watchdog)
01019   *            @arg @ref ADC_IT_AWD2   ADC Analog watchdog 2 interrupt source (additional analog watchdog)
01020   *            @arg @ref ADC_IT_AWD3   ADC Analog watchdog 3 interrupt source (additional analog watchdog)
01021   *            @arg @ref ADC_IT_JQOVF  ADC Injected Context Queue Overflow interrupt source.
01022   * @retval None
01023   */
01024 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__)                        \
01025   (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
01026
01027 /** @brief  Checks if the specified ADC interrupt source is enabled or disabled.
01028   * @param __HANDLE__ ADC handle
01029   * @param __INTERRUPT__ ADC interrupt source to check
01030   *          This parameter can be one of the following values:
01031   *            @arg @ref ADC_IT_RDY    ADC Ready interrupt source
01032   *            @arg @ref ADC_IT_EOSMP  ADC End of Sampling interrupt source
01033   *            @arg @ref ADC_IT_EOC    ADC End of Regular Conversion interrupt source
01034   *            @arg @ref ADC_IT_EOS    ADC End of Regular sequence of Conversions interrupt source
01035   *            @arg @ref ADC_IT_OVR    ADC overrun interrupt source
01036   *            @arg @ref ADC_IT_JEOC   ADC End of Injected Conversion interrupt source
01037   *            @arg @ref ADC_IT_JEOS   ADC End of Injected sequence of Conversions interrupt source
01038   *            @arg @ref ADC_IT_AWD1   ADC Analog watchdog 1 interrupt source (main analog watchdog)
01039   *            @arg @ref ADC_IT_AWD2   ADC Analog watchdog 2 interrupt source (additional analog watchdog)
01040   *            @arg @ref ADC_IT_AWD3   ADC Analog watchdog 3 interrupt source (additional analog watchdog)
01041   *            @arg @ref ADC_IT_JQOVF  ADC Injected Context Queue Overflow interrupt source.
01042   * @retval State of interruption (SET or RESET)
01043   */
01044 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)                     \
01045   (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
01046
01047 /**
01048   * @brief Check whether the specified ADC flag is set or not.
01049   * @param __HANDLE__ ADC handle
01050   * @param __FLAG__ ADC flag
01051   *        This parameter can be one of the following values:
01052   *            @arg @ref ADC_FLAG_RDY     ADC Ready flag
01053   *            @arg @ref ADC_FLAG_EOSMP   ADC End of Sampling flag
01054   *            @arg @ref ADC_FLAG_EOC     ADC End of Regular Conversion flag
01055   *            @arg @ref ADC_FLAG_EOS     ADC End of Regular sequence of Conversions flag
01056   *            @arg @ref ADC_FLAG_OVR     ADC overrun flag
01057   *            @arg @ref ADC_FLAG_JEOC    ADC End of Injected Conversion flag
01058   *            @arg @ref ADC_FLAG_JEOS    ADC End of Injected sequence of Conversions flag
01059   *            @arg @ref ADC_FLAG_AWD1    ADC Analog watchdog 1 flag (main analog watchdog)
01060   *            @arg @ref ADC_FLAG_AWD2    ADC Analog watchdog 2 flag (additional analog watchdog)
01061   *            @arg @ref ADC_FLAG_AWD3    ADC Analog watchdog 3 flag (additional analog watchdog)
01062   *            @arg @ref ADC_FLAG_JQOVF   ADC Injected Context Queue Overflow flag.
01063   * @retval State of flag (TRUE or FALSE).
01064   */
01065 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__)                               \
01066   ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
01067
01068 /**
01069   * @brief Clear the specified ADC flag.
01070   * @param __HANDLE__ ADC handle
01071   * @param __FLAG__ ADC flag
01072   *        This parameter can be one of the following values:
01073   *            @arg @ref ADC_FLAG_RDY     ADC Ready flag
01074   *            @arg @ref ADC_FLAG_EOSMP   ADC End of Sampling flag
01075   *            @arg @ref ADC_FLAG_EOC     ADC End of Regular Conversion flag
01076   *            @arg @ref ADC_FLAG_EOS     ADC End of Regular sequence of Conversions flag
01077   *            @arg @ref ADC_FLAG_OVR     ADC overrun flag
01078   *            @arg @ref ADC_FLAG_JEOC    ADC End of Injected Conversion flag
01079   *            @arg @ref ADC_FLAG_JEOS    ADC End of Injected sequence of Conversions flag
01080   *            @arg @ref ADC_FLAG_AWD1    ADC Analog watchdog 1 flag (main analog watchdog)
01081   *            @arg @ref ADC_FLAG_AWD2    ADC Analog watchdog 2 flag (additional analog watchdog)
01082   *            @arg @ref ADC_FLAG_AWD3    ADC Analog watchdog 3 flag (additional analog watchdog)
01083   *            @arg @ref ADC_FLAG_JQOVF   ADC Injected Context Queue Overflow flag.
01084   * @retval None
01085   */
01086 /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */
01087 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__)                             \
01088   (((__HANDLE__)->Instance->ISR) = (__FLAG__))
01089
01090 /**
01091   * @}
01092   */
01093
01094 /** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro
01095   * @{
01096   */
01097
01098 /**
01099   * @brief  Helper macro to get ADC channel number in decimal format
01100   *         from literals ADC_CHANNEL_x.
01101   * @note   Example:
01102   *           __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4)
01103   *           will return decimal number "4".
01104   * @note   The input can be a value from functions where a channel
01105   *         number is returned, either defined with number
01106   *         or with bitfield (only one bit must be set).
01107   * @param  __CHANNEL__ This parameter can be one of the following values:
01108   *         @arg @ref ADC_CHANNEL_0
01109   *         @arg @ref ADC_CHANNEL_1            (7)
01110   *         @arg @ref ADC_CHANNEL_2            (7)
01111   *         @arg @ref ADC_CHANNEL_3            (7)
01112   *         @arg @ref ADC_CHANNEL_4            (7)
01113   *         @arg @ref ADC_CHANNEL_5            (7)
01114   *         @arg @ref ADC_CHANNEL_6
01115   *         @arg @ref ADC_CHANNEL_7
01116   *         @arg @ref ADC_CHANNEL_8
01117   *         @arg @ref ADC_CHANNEL_9
01118   *         @arg @ref ADC_CHANNEL_10
01119   *         @arg @ref ADC_CHANNEL_11
01120   *         @arg @ref ADC_CHANNEL_12
01121   *         @arg @ref ADC_CHANNEL_13
01122   *         @arg @ref ADC_CHANNEL_14
01123   *         @arg @ref ADC_CHANNEL_15
01124   *         @arg @ref ADC_CHANNEL_16
01125   *         @arg @ref ADC_CHANNEL_17
01126   *         @arg @ref ADC_CHANNEL_18
01127   *         @arg @ref ADC_CHANNEL_VREFINT
01128   *         @arg @ref ADC_CHANNEL_TEMPSENSOR
01129   *         @arg @ref ADC_CHANNEL_VBAT
01130   *
01131   *         (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
01132   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
01133   * @retval Value between Min_Data=0 and Max_Data=18
01134   */
01135 #define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                           \
01136   __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))
01137
01138 /**
01139   * @brief  Helper macro to get ADC channel in literal format ADC_CHANNEL_x
01140   *         from number in decimal format.
01141   * @note   Example:
01142   *           __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4)
01143   *           will return a data equivalent to "ADC_CHANNEL_4".
01144   * @param  __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
01145   * @retval Returned value can be one of the following values:
01146   *         @arg @ref ADC_CHANNEL_0
01147   *         @arg @ref ADC_CHANNEL_1            (7)
01148   *         @arg @ref ADC_CHANNEL_2            (7)
01149   *         @arg @ref ADC_CHANNEL_3            (7)
01150   *         @arg @ref ADC_CHANNEL_4            (7)
01151   *         @arg @ref ADC_CHANNEL_5            (7)
01152   *         @arg @ref ADC_CHANNEL_6
01153   *         @arg @ref ADC_CHANNEL_7
01154   *         @arg @ref ADC_CHANNEL_8
01155   *         @arg @ref ADC_CHANNEL_9
01156   *         @arg @ref ADC_CHANNEL_10
01157   *         @arg @ref ADC_CHANNEL_11
01158   *         @arg @ref ADC_CHANNEL_12
01159   *         @arg @ref ADC_CHANNEL_13
01160   *         @arg @ref ADC_CHANNEL_14
01161   *         @arg @ref ADC_CHANNEL_15
01162   *         @arg @ref ADC_CHANNEL_16
01163   *         @arg @ref ADC_CHANNEL_17
01164   *         @arg @ref ADC_CHANNEL_18
01165   *         @arg @ref ADC_CHANNEL_VREFINT      (1)
01166   *         @arg @ref ADC_CHANNEL_TEMPSENSOR   (4)
01167   *         @arg @ref ADC_CHANNEL_VBAT         (4)
01168   *
01169   *         (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
01170   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
01171   *         (4) For ADC channel read back from ADC register,
01172   *             comparison with internal channel parameter to be done
01173   *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
01174   */
01175 #define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                        \
01176   __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))
01177
01178 /**
01179   * @brief  Helper macro to determine whether the selected channel
01180   *         corresponds to literal definitions of driver.
01181   * @note   The different literal definitions of ADC channels are:
01182   *         - ADC internal channel:
01183   *           ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...
01184   *         - ADC external channel (channel connected to a GPIO pin):
01185   *           ADC_CHANNEL_1, ADC_CHANNEL_2, ...
01186   * @note   The channel parameter must be a value defined from literal
01187   *         definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
01188   *         ADC_CHANNEL_TEMPSENSOR, ...),
01189   *         ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...),
01190   *         must not be a value from functions where a channel number is
01191   *         returned from ADC registers,
01192   *         because internal and external channels share the same channel
01193   *         number in ADC registers. The differentiation is made only with
01194   *         parameters definitions of driver.
01195   * @param  __CHANNEL__ This parameter can be one of the following values:
01196   *         @arg @ref ADC_CHANNEL_0
01197   *         @arg @ref ADC_CHANNEL_1            (7)
01198   *         @arg @ref ADC_CHANNEL_2            (7)
01199   *         @arg @ref ADC_CHANNEL_3            (7)
01200   *         @arg @ref ADC_CHANNEL_4            (7)
01201   *         @arg @ref ADC_CHANNEL_5            (7)
01202   *         @arg @ref ADC_CHANNEL_6
01203   *         @arg @ref ADC_CHANNEL_7
01204   *         @arg @ref ADC_CHANNEL_8
01205   *         @arg @ref ADC_CHANNEL_9
01206   *         @arg @ref ADC_CHANNEL_10
01207   *         @arg @ref ADC_CHANNEL_11
01208   *         @arg @ref ADC_CHANNEL_12
01209   *         @arg @ref ADC_CHANNEL_13
01210   *         @arg @ref ADC_CHANNEL_14
01211   *         @arg @ref ADC_CHANNEL_15
01212   *         @arg @ref ADC_CHANNEL_16
01213   *         @arg @ref ADC_CHANNEL_17
01214   *         @arg @ref ADC_CHANNEL_18
01215   *         @arg @ref ADC_CHANNEL_VREFINT
01216   *         @arg @ref ADC_CHANNEL_TEMPSENSOR
01217   *         @arg @ref ADC_CHANNEL_VBAT
01218   *
01219   *         (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
01220   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
01221   * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
01222   *         Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
01223   */
01224 #define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                             \
01225   __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))
01226
01227 /**
01228   * @brief  Helper macro to convert a channel defined from parameter
01229   *         definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
01230   *         ADC_CHANNEL_TEMPSENSOR, ...),
01231   *         to its equivalent parameter definition of a ADC external channel
01232   *         (ADC_CHANNEL_1, ADC_CHANNEL_2, ...).
01233   * @note   The channel parameter can be, additionally to a value
01234   *         defined from parameter definition of a ADC internal channel
01235   *         (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...),
01236   *         a value defined from parameter definition of
01237   *         ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
01238   *         or a value from functions where a channel number is returned
01239   *         from ADC registers.
01240   * @param  __CHANNEL__ This parameter can be one of the following values:
01241   *         @arg @ref ADC_CHANNEL_0
01242   *         @arg @ref ADC_CHANNEL_1            (7)
01243   *         @arg @ref ADC_CHANNEL_2            (7)
01244   *         @arg @ref ADC_CHANNEL_3            (7)
01245   *         @arg @ref ADC_CHANNEL_4            (7)
01246   *         @arg @ref ADC_CHANNEL_5            (7)
01247   *         @arg @ref ADC_CHANNEL_6
01248   *         @arg @ref ADC_CHANNEL_7
01249   *         @arg @ref ADC_CHANNEL_8
01250   *         @arg @ref ADC_CHANNEL_9
01251   *         @arg @ref ADC_CHANNEL_10
01252   *         @arg @ref ADC_CHANNEL_11
01253   *         @arg @ref ADC_CHANNEL_12
01254   *         @arg @ref ADC_CHANNEL_13
01255   *         @arg @ref ADC_CHANNEL_14
01256   *         @arg @ref ADC_CHANNEL_15
01257   *         @arg @ref ADC_CHANNEL_16
01258   *         @arg @ref ADC_CHANNEL_17
01259   *         @arg @ref ADC_CHANNEL_18
01260   *         @arg @ref ADC_CHANNEL_VREFINT
01261   *         @arg @ref ADC_CHANNEL_TEMPSENSOR
01262   *         @arg @ref ADC_CHANNEL_VBAT
01263   *
01264   *         (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
01265   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
01266   * @retval Returned value can be one of the following values:
01267   *         @arg @ref ADC_CHANNEL_0
01268   *         @arg @ref ADC_CHANNEL_1
01269   *         @arg @ref ADC_CHANNEL_2
01270   *         @arg @ref ADC_CHANNEL_3
01271   *         @arg @ref ADC_CHANNEL_4
01272   *         @arg @ref ADC_CHANNEL_5
01273   *         @arg @ref ADC_CHANNEL_6
01274   *         @arg @ref ADC_CHANNEL_7
01275   *         @arg @ref ADC_CHANNEL_8
01276   *         @arg @ref ADC_CHANNEL_9
01277   *         @arg @ref ADC_CHANNEL_10
01278   *         @arg @ref ADC_CHANNEL_11
01279   *         @arg @ref ADC_CHANNEL_12
01280   *         @arg @ref ADC_CHANNEL_13
01281   *         @arg @ref ADC_CHANNEL_14
01282   *         @arg @ref ADC_CHANNEL_15
01283   *         @arg @ref ADC_CHANNEL_16
01284   *         @arg @ref ADC_CHANNEL_17
01285   *         @arg @ref ADC_CHANNEL_18
01286   */
01287 #define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)                    \
01288   __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))
01289
01290 /**
01291   * @brief  Helper macro to determine whether the internal channel
01292   *         selected is available on the ADC instance selected.
01293   * @note   The channel parameter must be a value defined from parameter
01294   *         definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
01295   *         ADC_CHANNEL_TEMPSENSOR, ...),
01296   *         must not be a value defined from parameter definition of
01297   *         ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
01298   *         or a value from functions where a channel number is
01299   *         returned from ADC registers,
01300   *         because internal and external channels share the same channel
01301   *         number in ADC registers. The differentiation is made only with
01302   *         parameters definitions of driver.
01303   * @param  __ADC_INSTANCE__ ADC instance
01304   * @param  __CHANNEL__ This parameter can be one of the following values:
01305   *         @arg @ref ADC_CHANNEL_VREFINT
01306   *         @arg @ref ADC_CHANNEL_TEMPSENSOR
01307   *         @arg @ref ADC_CHANNEL_VBAT
01308   * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
01309   *         Value "1" if the internal channel selected is available on the ADC instance selected.
01310   */
01311 #define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
01312   __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))
01313
01314 /**
01315   * @brief  Helper macro to select the ADC common instance
01316   *         to which is belonging the selected ADC instance.
01317   * @note   ADC common register instance can be used for:
01318   *         - Set parameters common to several ADC instances
01319   *         - Multimode (for devices with several ADC instances)
01320   *         Refer to functions having argument "ADCxy_COMMON" as parameter.
01321   * @param  __ADCx__ ADC instance
01322   * @retval ADC common register instance
01323   */
01324 #define __HAL_ADC_COMMON_INSTANCE(__ADCx__)                                    \
01325   __LL_ADC_COMMON_INSTANCE((__ADCx__))
01326
01327 /**
01328   * @brief  Helper macro to check if all ADC instances sharing the same
01329   *         ADC common instance are disabled.
01330   * @note   This check is required by functions with setting conditioned to
01331   *         ADC state:
01332   *         All ADC instances of the ADC common group must be disabled.
01333   *         Refer to functions having argument "ADCxy_COMMON" as parameter.
01334   * @note   On devices with only 1 ADC common instance, parameter of this macro
01335   *         is useless and can be ignored (parameter kept for compatibility
01336   *         with devices featuring several ADC common instances).
01337   * @param  __ADCXY_COMMON__ ADC common instance
01338   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
01339   * @retval Value "0" if all ADC instances sharing the same ADC common instance
01340   *         are disabled.
01341   *         Value "1" if at least one ADC instance sharing the same ADC common instance
01342   *         is enabled.
01343   */
01344 #define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
01345   __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))
01346
01347 /**
01348   * @brief  Helper macro to define the ADC conversion data full-scale digital
01349   *         value corresponding to the selected ADC resolution.
01350   * @note   ADC conversion data full-scale corresponds to voltage range
01351   *         determined by analog voltage references Vref+ and Vref-
01352   *         (refer to reference manual).
01353   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
01354   *         @arg @ref ADC_RESOLUTION_12B
01355   *         @arg @ref ADC_RESOLUTION_10B
01356   *         @arg @ref ADC_RESOLUTION_8B
01357   *         @arg @ref ADC_RESOLUTION_6B
01358   * @retval ADC conversion data full-scale digital value
01359   */
01360 #define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \
01361   __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))
01362
01363 /**
01364   * @brief  Helper macro to convert the ADC conversion data from
01365   *         a resolution to another resolution.
01366   * @param  __DATA__ ADC conversion data to be converted
01367   * @param  __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
01368   *         This parameter can be one of the following values:
01369   *         @arg @ref ADC_RESOLUTION_12B
01370   *         @arg @ref ADC_RESOLUTION_10B
01371   *         @arg @ref ADC_RESOLUTION_8B
01372   *         @arg @ref ADC_RESOLUTION_6B
01373   * @param  __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
01374   *         This parameter can be one of the following values:
01375   *         @arg @ref ADC_RESOLUTION_12B
01376   *         @arg @ref ADC_RESOLUTION_10B
01377   *         @arg @ref ADC_RESOLUTION_8B
01378   *         @arg @ref ADC_RESOLUTION_6B
01379   * @retval ADC conversion data to the requested resolution
01380   */
01381 #define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
01382                                           __ADC_RESOLUTION_CURRENT__,\
01383                                           __ADC_RESOLUTION_TARGET__)            \
01384   __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),                                  \
01385                                    (__ADC_RESOLUTION_CURRENT__),                \
01386                                    (__ADC_RESOLUTION_TARGET__))
01387
01388 /**
01389   * @brief  Helper macro to calculate the voltage (unit: mVolt)
01390   *         corresponding to a ADC conversion data (unit: digital value).
01391   * @note   Analog reference voltage (Vref+) must be either known from
01392   *         user board environment or can be calculated using ADC measurement
01393   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
01394   * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
01395   * @param  __ADC_DATA__ ADC conversion data (resolution 12 bits)
01396   *                       (unit: digital value).
01397   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
01398   *         @arg @ref ADC_RESOLUTION_12B
01399   *         @arg @ref ADC_RESOLUTION_10B
01400   *         @arg @ref ADC_RESOLUTION_8B
01401   *         @arg @ref ADC_RESOLUTION_6B
01402   * @retval ADC conversion data equivalent voltage value (unit: mVolt)
01403   */
01404 #define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
01405                                        __ADC_DATA__,\
01406                                        __ADC_RESOLUTION__)                     \
01407   __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),                      \
01408                                 (__ADC_DATA__),                                \
01409                                 (__ADC_RESOLUTION__))
01410
01411 /**
01412   * @brief  Helper macro to calculate analog reference voltage (Vref+)
01413   *         (unit: mVolt) from ADC conversion data of internal voltage
01414   *         reference VrefInt.
01415   * @note   Computation is using VrefInt calibration value
01416   *         stored in system memory for each device during production.
01417   * @note   This voltage depends on user board environment: voltage level
01418   *         connected to pin Vref+.
01419   *         On devices with small package, the pin Vref+ is not present
01420   *         and internally bonded to pin Vdda.
01421   * @note   On this STM32 serie, calibration data of internal voltage reference
01422   *         VrefInt corresponds to a resolution of 12 bits,
01423   *         this is the recommended ADC resolution to convert voltage of
01424   *         internal voltage reference VrefInt.
01425   *         Otherwise, this macro performs the processing to scale
01426   *         ADC conversion data to 12 bits.
01427   * @param  __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
01428   *         of internal voltage reference VrefInt (unit: digital value).
01429   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
01430   *         @arg @ref ADC_RESOLUTION_12B
01431   *         @arg @ref ADC_RESOLUTION_10B
01432   *         @arg @ref ADC_RESOLUTION_8B
01433   *         @arg @ref ADC_RESOLUTION_6B
01434   * @retval Analog reference voltage (unit: mV)
01435   */
01436 #define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
01437                                           __ADC_RESOLUTION__)                  \
01438   __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),                     \
01439                                   (__ADC_RESOLUTION__))
01440
01441 /**
01442   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
01443   *         from ADC conversion data of internal temperature sensor.
01444   * @note   Computation is using temperature sensor calibration values
01445   *         stored in system memory for each device during production.
01446   * @note   Calculation formula:
01447   *           Temperature = ((TS_ADC_DATA - TS_CAL1)
01448   *                           * (TS_CAL2_TEMP - TS_CAL1_TEMP))
01449   *                         / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
01450   *           with TS_ADC_DATA = temperature sensor raw data measured by ADC
01451   *                Avg_Slope = (TS_CAL2 - TS_CAL1)
01452   *                            / (TS_CAL2_TEMP - TS_CAL1_TEMP)
01453   *                TS_CAL1   = equivalent TS_ADC_DATA at temperature
01454   *                            TEMP_DEGC_CAL1 (calibrated in factory)
01455   *                TS_CAL2   = equivalent TS_ADC_DATA at temperature
01456   *                            TEMP_DEGC_CAL2 (calibrated in factory)
01457   *         Caution: Calculation relevancy under reserve that calibration
01458   *                  parameters are correct (address and data).
01459   *                  To calculate temperature using temperature sensor
01460   *                  datasheet typical values (generic values less, therefore
01461   *                  less accurate than calibrated values),
01462   *                  use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
01463   * @note   As calculation input, the analog reference voltage (Vref+) must be
01464   *         defined as it impacts the ADC LSB equivalent voltage.
01465   * @note   Analog reference voltage (Vref+) must be either known from
01466   *         user board environment or can be calculated using ADC measurement
01467   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
01468   * @note   On this STM32 serie, calibration data of temperature sensor
01469   *         corresponds to a resolution of 12 bits,
01470   *         this is the recommended ADC resolution to convert voltage of
01471   *         temperature sensor.
01472   *         Otherwise, this macro performs the processing to scale
01473   *         ADC conversion data to 12 bits.
01474   * @param  __VREFANALOG_VOLTAGE__  Analog reference voltage (unit: mV)
01475   * @param  __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
01476   *                                 temperature sensor (unit: digital value).
01477   * @param  __ADC_RESOLUTION__      ADC resolution at which internal temperature
01478   *                                 sensor voltage has been measured.
01479   *         This parameter can be one of the following values:
01480   *         @arg @ref ADC_RESOLUTION_12B
01481   *         @arg @ref ADC_RESOLUTION_10B
01482   *         @arg @ref ADC_RESOLUTION_8B
01483   *         @arg @ref ADC_RESOLUTION_6B
01484   * @retval Temperature (unit: degree Celsius)
01485   */
01486 #define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
01487                                    __TEMPSENSOR_ADC_DATA__,\
01488                                    __ADC_RESOLUTION__)                         \
01489   __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),                          \
01490                             (__TEMPSENSOR_ADC_DATA__),                         \
01491                             (__ADC_RESOLUTION__))
01492
01493 /**
01494   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
01495   *         from ADC conversion data of internal temperature sensor.
01496   * @note   Computation is using temperature sensor typical values
01497   *         (refer to device datasheet).
01498   * @note   Calculation formula:
01499   *           Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
01500   *                         / Avg_Slope + CALx_TEMP
01501   *           with TS_ADC_DATA      = temperature sensor raw data measured by ADC
01502   *                                   (unit: digital value)
01503   *                Avg_Slope        = temperature sensor slope
01504   *                                   (unit: uV/Degree Celsius)
01505   *                TS_TYP_CALx_VOLT = temperature sensor digital value at
01506   *                                   temperature CALx_TEMP (unit: mV)
01507   *         Caution: Calculation relevancy under reserve the temperature sensor
01508   *                  of the current device has characteristics in line with
01509   *                  datasheet typical values.
01510   *                  If temperature sensor calibration values are available on
01511   *                  on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
01512   *                  temperature calculation will be more accurate using
01513   *                  helper macro @ref __LL_ADC_CALC_TEMPERATURE().
01514   * @note   As calculation input, the analog reference voltage (Vref+) must be
01515   *         defined as it impacts the ADC LSB equivalent voltage.
01516   * @note   Analog reference voltage (Vref+) must be either known from
01517   *         user board environment or can be calculated using ADC measurement
01518   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
01519   * @note   ADC measurement data must correspond to a resolution of 12bits
01520   *         (full scale digital value 4095). If not the case, the data must be
01521   *         preliminarily rescaled to an equivalent resolution of 12 bits.
01522   * @param  __TEMPSENSOR_TYP_AVGSLOPE__   Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
01523   *                                       On STM32WB, refer to device datasheet parameter "Avg_Slope".
01524   * @param  __TEMPSENSOR_TYP_CALX_V__     Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
01525   *                                       On STM32WB, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
01526   * @param  __TEMPSENSOR_CALX_TEMP__      Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
01527   * @param  __VREFANALOG_VOLTAGE__        Analog voltage reference (Vref+) voltage (unit: mV)
01528   * @param  __TEMPSENSOR_ADC_DATA__       ADC conversion data of internal temperature sensor (unit: digital value).
01529   * @param  __ADC_RESOLUTION__            ADC resolution at which internal temperature sensor voltage has been measured.
01530   *         This parameter can be one of the following values:
01531   *         @arg @ref ADC_RESOLUTION_12B
01532   *         @arg @ref ADC_RESOLUTION_10B
01533   *         @arg @ref ADC_RESOLUTION_8B
01534   *         @arg @ref ADC_RESOLUTION_6B
01535   * @retval Temperature (unit: degree Celsius)
01536   */
01537 #define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
01538                                               __TEMPSENSOR_TYP_CALX_V__,\
01539                                               __TEMPSENSOR_CALX_TEMP__,\
01540                                               __VREFANALOG_VOLTAGE__,\
01541                                               __TEMPSENSOR_ADC_DATA__,\
01542                                               __ADC_RESOLUTION__)              \
01543   __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),          \
01544                                       (__TEMPSENSOR_TYP_CALX_V__),             \
01545                                       (__TEMPSENSOR_CALX_TEMP__),              \
01546                                       (__VREFANALOG_VOLTAGE__),                \
01547                                       (__TEMPSENSOR_ADC_DATA__),               \
01548                                       (__ADC_RESOLUTION__))
01549
01550 /**
01551   * @}
01552   */
01553
01554 /**
01555   * @}
01556   */
01557
01558 /* Include ADC HAL Extended module */
01559 #include "stm32wbxx_hal_adc_ex.h"
01560
01561 /* Exported functions --------------------------------------------------------*/
01562 /** @addtogroup ADC_Exported_Functions
01563   * @{
01564   */
01565
01566 /** @addtogroup ADC_Exported_Functions_Group1
01567   * @brief    Initialization and Configuration functions
01568   * @{
01569   */
01570 /* Initialization and de-initialization functions  ****************************/
01571 HAL_StatusTypeDef       HAL_ADC_Init(ADC_HandleTypeDef *hadc);
01572 HAL_StatusTypeDef       HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
01573 void                    HAL_ADC_MspInit(ADC_HandleTypeDef *hadc);
01574 void                    HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc);
01575
01576 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
01577 /* Callbacks Register/UnRegister functions  ***********************************/
01578 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
01579                                            pADC_CallbackTypeDef pCallback);
01580 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
01581 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
01582 /**
01583   * @}
01584   */
01585
01586 /** @addtogroup ADC_Exported_Functions_Group2
01587   * @brief    IO operation functions
01588   * @{
01589   */
01590 /* IO operation functions  *****************************************************/
01591
01592 /* Blocking mode: Polling */
01593 HAL_StatusTypeDef       HAL_ADC_Start(ADC_HandleTypeDef *hadc);
01594 HAL_StatusTypeDef       HAL_ADC_Stop(ADC_HandleTypeDef *hadc);
01595 HAL_StatusTypeDef       HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
01596 HAL_StatusTypeDef       HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout);
01597
01598 /* Non-blocking mode: Interruption */
01599 HAL_StatusTypeDef       HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc);
01600 HAL_StatusTypeDef       HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc);
01601
01602 /* Non-blocking mode: DMA */
01603 HAL_StatusTypeDef       HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
01604 HAL_StatusTypeDef       HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc);
01605
01606 /* ADC retrieve conversion value intended to be used with polling or interruption */
01607 uint32_t                HAL_ADC_GetValue(ADC_HandleTypeDef *hadc);
01608
01609 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
01610 void                    HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc);
01611 void                    HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc);
01612 void                    HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc);
01613 void                    HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc);
01614 void                    HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
01615 /**
01616   * @}
01617   */
01618
01619 /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
01620   *  @brief    Peripheral Control functions
01621   * @{
01622   */
01623 /* Peripheral Control functions ***********************************************/
01624 HAL_StatusTypeDef       HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig);
01625 HAL_StatusTypeDef       HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig);
01626
01627 /**
01628   * @}
01629   */
01630
01631 /* Peripheral State functions *************************************************/
01632 /** @addtogroup ADC_Exported_Functions_Group4
01633   * @{
01634   */
01635 uint32_t                HAL_ADC_GetState(ADC_HandleTypeDef *hadc);
01636 uint32_t                HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
01637
01638 /**
01639   * @}
01640   */
01641
01642 /**
01643   * @}
01644   */
01645
01646 /* Private functions -----------------------------------------------------------*/
01647 /** @addtogroup ADC_Private_Functions ADC Private Functions
01648   * @{
01649   */
01650 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup);
01651 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc);
01652 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc);
01653 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
01654 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
01655 void ADC_DMAError(DMA_HandleTypeDef *hdma);
01656
01657 /**
01658   * @}
01659   */
01660
01661 /**
01662   * @}
01663   */
01664
01665 /**
01666   * @}
01667   */
01668
01669 #ifdef __cplusplus
01670 }
01671 #endif
01672
01673
01674 #endif /* STM32WBxx_HAL_ADC_H */
01675
01676 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:33 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_adc_ex.c Source File

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stm32wbxx_hal_adc_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_adc_ex.c
00004   * @author  MCD Application Team
00005   * @brief   This file provides firmware functions to manage the following
00006   *          functionalities of the Analog to Digital Convertor (ADC)
00007   *          peripheral:
00008   *           + Operation functions
00009   *             ++ Start, stop, get result of conversions of ADC group injected,
00010   *                using 2 possible modes: polling, interruption.
00011   *             ++ Calibration
00012   *               +++ ADC automatic self-calibration
00013   *               +++ Calibration factors get or set
00014   *           + Control functions
00015   *             ++ Channels configuration on ADC group injected
00016   *           + State functions
00017   *             ++ ADC group injected contexts queue management
00018   *          Other functions (generic functions) are available in file
00019   *          "stm32wbxx_hal_adc.c".
00020   *
00021   @verbatim
00022   [..]
00023   (@) Sections "ADC peripheral features" and "How to use this driver" are
00024       available in file of generic functions "stm32wbxx_hal_adc.c".
00025   [..]
00026   @endverbatim
00027   ******************************************************************************
00028   * @attention
00029   *
00030   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00031   * All rights reserved.</center></h2>
00032   *
00033   * This software component is licensed by ST under BSD 3-Clause license,
00034   * the "License"; You may not use this file except in compliance with the
00035   * License. You may obtain a copy of the License at:
00036   *                        opensource.org/licenses/BSD-3-Clause
00037   *
00038   ******************************************************************************
00039   */
00040
00041 /* Includes ------------------------------------------------------------------*/
00042 #include "stm32wbxx_hal.h"
00043
00044 /** @addtogroup STM32WBxx_HAL_Driver
00045   * @{
00046   */
00047
00048 /** @defgroup ADCEx ADCEx
00049   * @brief ADC Extended HAL module driver
00050   * @{
00051   */
00052
00053 #ifdef HAL_ADC_MODULE_ENABLED
00054
00055 /* Private typedef -----------------------------------------------------------*/
00056 /* Private define ------------------------------------------------------------*/
00057
00058 /** @defgroup ADCEx_Private_Constants ADC Extended Private Constants
00059   * @{
00060   */
00061
00062 #define ADC_JSQR_FIELDS  ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
00063                            ADC_JSQR_JSQ1  | ADC_JSQR_JSQ2 |\
00064                            ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 ))  /*!< ADC_JSQR fields of parameters that can be updated anytime
00065                                                                   once the ADC is enabled */
00066
00067 /* Fixed timeout value for ADC calibration.                                   */
00068 /* Values defined to be higher than worst cases: maximum ratio between ADC    */
00069 /* and CPU clock frequencies.                                                 */
00070 /* Example of profile low frequency : ADC frequency at 46.9kHz (ADC clock     */
00071 /* source PLL SAI 12MHz, ADC clock prescaler 256), CPU frequency 64MHz.       */
00072 /* Calibration time max = 116 / fADC (refer to datasheet)                     */
00073 /*                      = 158 379 CPU cycles                                  */
00074 #define ADC_CALIBRATION_TIMEOUT         (158379UL)   /*!< ADC calibration time-out value (unit: CPU cycles) */
00075
00076 /**
00077   * @}
00078   */
00079
00080 /* Private macro -------------------------------------------------------------*/
00081 /* Private variables ---------------------------------------------------------*/
00082 /* Private function prototypes -----------------------------------------------*/
00083 /* Exported functions --------------------------------------------------------*/
00084
00085 /** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions
00086   * @{
00087   */
00088
00089 /** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
00090   * @brief    Extended IO operation functions
00091   *
00092 @verbatim
00093  ===============================================================================
00094                       ##### IO operation functions #####
00095  ===============================================================================
00096     [..]  This section provides functions allowing to:
00097
00098       (+) Perform the ADC self-calibration for single or differential ending.
00099       (+) Get calibration factors for single or differential ending.
00100       (+) Set calibration factors for single or differential ending.
00101
00102       (+) Start conversion of ADC group injected.
00103       (+) Stop conversion of ADC group injected.
00104       (+) Poll for conversion complete on ADC group injected.
00105       (+) Get result of ADC group injected channel conversion.
00106       (+) Start conversion of ADC group injected and enable interruptions.
00107       (+) Stop conversion of ADC group injected and disable interruptions.
00108
00109 @endverbatim
00110   * @{
00111   */
00112
00113 /**
00114   * @brief  Perform an ADC automatic self-calibration
00115   *         Calibration prerequisite: ADC must be disabled (execute this
00116   *         function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
00117   * @param  hadc       ADC handle
00118   * @param  SingleDiff Selection of single-ended or differential input
00119   *         This parameter can be one of the following values:
00120   *           @arg @ref ADC_SINGLE_ENDED       Channel in mode input single ended
00121   *           @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
00122   * @retval HAL status
00123   */
00124 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
00125 {
00126   HAL_StatusTypeDef tmp_hal_status;
00127   __IO uint32_t wait_loop_index = 0UL;
00128
00129   /* Check the parameters */
00130   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00131   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
00132
00133   /* Process locked */
00134   __HAL_LOCK(hadc);
00135
00136   /* Calibration prerequisite: ADC must be disabled. */
00137
00138   /* Disable the ADC (if not already disabled) */
00139   tmp_hal_status = ADC_Disable(hadc);
00140
00141   /* Check if ADC is effectively disabled */
00142   if (tmp_hal_status == HAL_OK)
00143   {
00144     /* Set ADC state */
00145     ADC_STATE_CLR_SET(hadc->State,
00146                       HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
00147                       HAL_ADC_STATE_BUSY_INTERNAL);
00148
00149     /* Start ADC calibration in mode single-ended or differential */
00150     LL_ADC_StartCalibration(hadc->Instance, SingleDiff);
00151
00152     /* Wait for calibration completion */
00153     while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
00154     {
00155       wait_loop_index++;
00156       if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
00157       {
00158         /* Update ADC state machine to error */
00159         ADC_STATE_CLR_SET(hadc->State,
00160                           HAL_ADC_STATE_BUSY_INTERNAL,
00161                           HAL_ADC_STATE_ERROR_INTERNAL);
00162
00163         /* Process unlocked */
00164         __HAL_UNLOCK(hadc);
00165
00166         return HAL_ERROR;
00167       }
00168     }
00169
00170     /* Set ADC state */
00171     ADC_STATE_CLR_SET(hadc->State,
00172                       HAL_ADC_STATE_BUSY_INTERNAL,
00173                       HAL_ADC_STATE_READY);
00174   }
00175   else
00176   {
00177     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
00178
00179     /* Note: No need to update variable "tmp_hal_status" here: already set    */
00180     /*       to state "HAL_ERROR" by function disabling the ADC.              */
00181   }
00182
00183   /* Process unlocked */
00184   __HAL_UNLOCK(hadc);
00185
00186   /* Return function status */
00187   return tmp_hal_status;
00188 }
00189
00190 /**
00191   * @brief  Get the calibration factor.
00192   * @param hadc ADC handle.
00193   * @param SingleDiff This parameter can be only:
00194   *           @arg @ref ADC_SINGLE_ENDED       Channel in mode input single ended
00195   *           @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
00196   * @retval Calibration value.
00197   */
00198 uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
00199 {
00200   /* Check the parameters */
00201   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00202   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
00203
00204   /* Return the selected ADC calibration value */
00205   return LL_ADC_GetCalibrationFactor(hadc->Instance, SingleDiff);
00206 }
00207
00208 /**
00209   * @brief  Set the calibration factor to overwrite automatic conversion result.
00210   *         ADC must be enabled and no conversion is ongoing.
00211   * @param hadc ADC handle
00212   * @param SingleDiff This parameter can be only:
00213   *           @arg @ref ADC_SINGLE_ENDED       Channel in mode input single ended
00214   *           @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
00215   * @param CalibrationFactor Calibration factor (coded on 7 bits maximum)
00216   * @retval HAL state
00217   */
00218 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
00219 {
00220   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
00221   uint32_t tmp_adc_is_conversion_on_going_regular;
00222   uint32_t tmp_adc_is_conversion_on_going_injected;
00223
00224   /* Check the parameters */
00225   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00226   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
00227   assert_param(IS_ADC_CALFACT(CalibrationFactor));
00228
00229   /* Process locked */
00230   __HAL_LOCK(hadc);
00231
00232   /* Verification of hardware constraints before modifying the calibration    */
00233   /* factors register: ADC must be enabled, no conversion on going.           */
00234   tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
00235   tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
00236
00237   if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
00238       && (tmp_adc_is_conversion_on_going_regular == 0UL)
00239       && (tmp_adc_is_conversion_on_going_injected == 0UL)
00240      )
00241   {
00242     /* Set the selected ADC calibration value */
00243     LL_ADC_SetCalibrationFactor(hadc->Instance, SingleDiff, CalibrationFactor);
00244   }
00245   else
00246   {
00247     /* Update ADC state machine */
00248     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
00249     /* Update ADC error code */
00250     SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
00251
00252     /* Update ADC state machine to error */
00253     tmp_hal_status = HAL_ERROR;
00254   }
00255
00256   /* Process unlocked */
00257   __HAL_UNLOCK(hadc);
00258
00259   /* Return function status */
00260   return tmp_hal_status;
00261 }
00262
00263 /**
00264   * @brief  Enable ADC, start conversion of injected group.
00265   * @note   Interruptions enabled in this function: None.
00266   * @param hadc ADC handle.
00267   * @retval HAL status
00268   */
00269 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc)
00270 {
00271   HAL_StatusTypeDef tmp_hal_status;
00272   uint32_t tmp_config_injected_queue;
00273
00274   /* Check the parameters */
00275   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00276
00277   if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
00278   {
00279     return HAL_BUSY;
00280   }
00281   else
00282   {
00283     /* In case of software trigger detection enabled, JQDIS must be set
00284       (which can be done only if ADSTART and JADSTART are both cleared).
00285        If JQDIS is not set at that point, returns an error
00286        - since software trigger detection is disabled. User needs to
00287        resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
00288        - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
00289          the queue is empty */
00290     tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
00291
00292     if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL)
00293         && (tmp_config_injected_queue == 0UL)
00294        )
00295     {
00296       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
00297       return HAL_ERROR;
00298     }
00299
00300     /* Process locked */
00301     __HAL_LOCK(hadc);
00302
00303     /* Enable the ADC peripheral */
00304     tmp_hal_status = ADC_Enable(hadc);
00305
00306     /* Start conversion if ADC is effectively enabled */
00307     if (tmp_hal_status == HAL_OK)
00308     {
00309       /* Check if a regular conversion is ongoing */
00310       if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL)
00311       {
00312         /* Reset ADC error code field related to injected conversions only */
00313         CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
00314       }
00315       else
00316       {
00317         /* Set ADC error code to none */
00318         ADC_CLEAR_ERRORCODE(hadc);
00319       }
00320
00321       /* Set ADC state                                                        */
00322       /* - Clear state bitfield related to injected group conversion results  */
00323       /* - Set state bitfield related to injected operation                   */
00324       ADC_STATE_CLR_SET(hadc->State,
00325                         HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
00326                         HAL_ADC_STATE_INJ_BUSY);
00327
00328       /* Clear ADC group injected group conversion flag */
00329       /* (To ensure of no unknown state from potential previous ADC operations) */
00330       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
00331
00332       /* Process unlocked */
00333       /* Unlock before starting ADC conversions: in case of potential         */
00334       /* interruption, to let the process to ADC IRQ Handler.                 */
00335       __HAL_UNLOCK(hadc);
00336
00337       /* Enable conversion of injected group, if automatic injected conversion  */
00338       /* is disabled.                                                           */
00339       /* If software start has been selected, conversion starts immediately.    */
00340       /* If external trigger has been selected, conversion will start at next   */
00341       /* trigger event.                                                         */
00342       if(LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
00343       {
00344         /* Start ADC group injected conversion */
00345         LL_ADC_INJ_StartConversion(hadc->Instance);
00346       }
00347     }
00348     else
00349     {
00350       /* Process unlocked */
00351       __HAL_UNLOCK(hadc);
00352     }
00353
00354     /* Return function status */
00355     return tmp_hal_status;
00356   }
00357 }
00358
00359 /**
00360   * @brief  Stop conversion of injected channels. Disable ADC peripheral if
00361   *         no regular conversion is on going.
00362   * @note   If ADC must be disabled and if conversion is on going on
00363   *         regular group, function HAL_ADC_Stop must be used to stop both
00364   *         injected and regular groups, and disable the ADC.
00365   * @note   If injected group mode auto-injection is enabled,
00366   *         function HAL_ADC_Stop must be used.
00367   * @param hadc ADC handle.
00368   * @retval HAL status
00369   */
00370 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc)
00371 {
00372   HAL_StatusTypeDef tmp_hal_status;
00373
00374   /* Check the parameters */
00375   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00376
00377   /* Process locked */
00378   __HAL_LOCK(hadc);
00379
00380   /* 1. Stop potential conversion on going on injected group only. */
00381   tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
00382
00383   /* Disable ADC peripheral if injected conversions are effectively stopped   */
00384   /* and if no conversion on regular group is on-going                       */
00385   if (tmp_hal_status == HAL_OK)
00386   {
00387     if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
00388     {
00389       /* 2. Disable the ADC peripheral */
00390       tmp_hal_status = ADC_Disable(hadc);
00391
00392       /* Check if ADC is effectively disabled */
00393       if (tmp_hal_status == HAL_OK)
00394       {
00395         /* Set ADC state */
00396         ADC_STATE_CLR_SET(hadc->State,
00397                           HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
00398                           HAL_ADC_STATE_READY);
00399       }
00400     }
00401     /* Conversion on injected group is stopped, but ADC not disabled since    */
00402     /* conversion on regular group is still running.                          */
00403     else
00404     {
00405       /* Set ADC state */
00406       CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
00407     }
00408   }
00409
00410   /* Process unlocked */
00411   __HAL_UNLOCK(hadc);
00412
00413   /* Return function status */
00414   return tmp_hal_status;
00415 }
00416
00417 /**
00418   * @brief  Wait for injected group conversion to be completed.
00419   * @param hadc ADC handle
00420   * @param Timeout Timeout value in millisecond.
00421   * @note   Depending on hadc->Init.EOCSelection, JEOS or JEOC is
00422   *         checked and cleared depending on AUTDLY bit status.
00423   * @retval HAL status
00424   */
00425 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
00426 {
00427   uint32_t tickstart;
00428   uint32_t tmp_Flag_End;
00429   uint32_t tmp_adc_inj_is_trigger_source_sw_start;
00430   uint32_t tmp_adc_reg_is_trigger_source_sw_start;
00431   uint32_t tmp_cfgr;
00432
00433   /* Check the parameters */
00434   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00435
00436   /* If end of sequence selected */
00437   if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
00438   {
00439     tmp_Flag_End = ADC_FLAG_JEOS;
00440   }
00441   else /* end of conversion selected */
00442   {
00443     tmp_Flag_End = ADC_FLAG_JEOC;
00444   }
00445
00446   /* Get timeout */
00447   tickstart = HAL_GetTick();
00448
00449   /* Wait until End of Conversion or Sequence flag is raised */
00450   while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
00451   {
00452     /* Check if timeout is disabled (set to infinite wait) */
00453     if (Timeout != HAL_MAX_DELAY)
00454     {
00455       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
00456       {
00457         /* Update ADC state machine to timeout */
00458         SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
00459
00460         /* Process unlocked */
00461         __HAL_UNLOCK(hadc);
00462
00463         return HAL_TIMEOUT;
00464       }
00465     }
00466   }
00467
00468   /* Retrieve ADC configuration */
00469   tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
00470   tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
00471   tmp_cfgr = READ_REG(hadc->Instance->CFGR);
00472
00473   /* Update ADC state machine */
00474   SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
00475
00476   /* Determine whether any further conversion upcoming on group injected      */
00477   /* by external trigger or by automatic injected conversion                  */
00478   /* from group regular.                                                      */
00479   if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL)            ||
00480       ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL)      &&
00481        ((tmp_adc_reg_is_trigger_source_sw_start != 0UL)  &&
00482         (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL))))
00483   {
00484     /* Check whether end of sequence is reached */
00485     if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
00486     {
00487       /* Particular case if injected contexts queue is enabled:             */
00488       /* when the last context has been fully processed, JSQR is reset      */
00489       /* by the hardware. Even if no injected conversion is planned to come */
00490       /* (queue empty, triggers are ignored), it can start again            */
00491       /* immediately after setting a new context (JADSTART is still set).   */
00492       /* Therefore, state of HAL ADC injected group is kept to busy.        */
00493       if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM) == 0UL)
00494       {
00495         /* Set ADC state */
00496         CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
00497
00498         if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
00499         {
00500           SET_BIT(hadc->State, HAL_ADC_STATE_READY);
00501         }
00502       }
00503     }
00504   }
00505
00506   /* Clear polled flag */
00507   if (tmp_Flag_End == ADC_FLAG_JEOS)
00508   {
00509     /* Clear end of sequence JEOS flag of injected group if low power feature */
00510     /* "LowPowerAutoWait " is disabled, to not interfere with this feature.   */
00511     /* For injected groups, no new conversion will start before JEOS is       */
00512     /* cleared.                                                               */
00513     if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_AUTDLY) == 0UL)
00514     {
00515       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
00516     }
00517   }
00518   else
00519   {
00520     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
00521   }
00522
00523   /* Return API HAL status */
00524   return HAL_OK;
00525 }
00526
00527 /**
00528   * @brief  Enable ADC, start conversion of injected group with interruption.
00529   * @note   Interruptions enabled in this function according to initialization
00530   *         setting : JEOC (end of conversion) or JEOS (end of sequence)
00531   * @param hadc ADC handle.
00532   * @retval HAL status.
00533   */
00534 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc)
00535 {
00536   HAL_StatusTypeDef tmp_hal_status;
00537   uint32_t tmp_config_injected_queue;
00538
00539   /* Check the parameters */
00540   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00541
00542   if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
00543   {
00544     return HAL_BUSY;
00545   }
00546   else
00547   {
00548     /* In case of software trigger detection enabled, JQDIS must be set
00549       (which can be done only if ADSTART and JADSTART are both cleared).
00550        If JQDIS is not set at that point, returns an error
00551        - since software trigger detection is disabled. User needs to
00552        resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
00553        - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
00554          the queue is empty */
00555     tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
00556
00557     if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL)
00558         && (tmp_config_injected_queue == 0UL)
00559        )
00560     {
00561       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
00562       return HAL_ERROR;
00563     }
00564
00565     /* Process locked */
00566     __HAL_LOCK(hadc);
00567
00568     /* Enable the ADC peripheral */
00569     tmp_hal_status = ADC_Enable(hadc);
00570
00571     /* Start conversion if ADC is effectively enabled */
00572     if (tmp_hal_status == HAL_OK)
00573     {
00574       /* Check if a regular conversion is ongoing */
00575       if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL)
00576       {
00577         /* Reset ADC error code field related to injected conversions only */
00578         CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
00579       }
00580       else
00581       {
00582         /* Set ADC error code to none */
00583         ADC_CLEAR_ERRORCODE(hadc);
00584       }
00585
00586       /* Set ADC state                                                        */
00587       /* - Clear state bitfield related to injected group conversion results  */
00588       /* - Set state bitfield related to injected operation                   */
00589       ADC_STATE_CLR_SET(hadc->State,
00590                         HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
00591                         HAL_ADC_STATE_INJ_BUSY);
00592
00593       /* Clear ADC group injected group conversion flag */
00594       /* (To ensure of no unknown state from potential previous ADC operations) */
00595       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
00596
00597       /* Process unlocked */
00598       /* Unlock before starting ADC conversions: in case of potential         */
00599       /* interruption, to let the process to ADC IRQ Handler.                 */
00600       __HAL_UNLOCK(hadc);
00601
00602       /* Enable ADC Injected context queue overflow interrupt if this feature   */
00603       /* is enabled.                                                            */
00604       if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != 0UL)
00605       {
00606         __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF);
00607       }
00608
00609       /* Enable ADC end of conversion interrupt */
00610       switch (hadc->Init.EOCSelection)
00611       {
00612         case ADC_EOC_SEQ_CONV:
00613           __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
00614           __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
00615           break;
00616         /* case ADC_EOC_SINGLE_CONV */
00617         default:
00618           __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
00619           __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
00620           break;
00621       }
00622
00623       /* Enable conversion of injected group, if automatic injected conversion  */
00624       /* is disabled.                                                           */
00625       /* If software start has been selected, conversion starts immediately.    */
00626       /* If external trigger has been selected, conversion will start at next   */
00627       /* trigger event.                                                         */
00628       if(LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
00629       {
00630         /* Start ADC group injected conversion */
00631         LL_ADC_INJ_StartConversion(hadc->Instance);
00632       }
00633     }
00634     else
00635     {
00636       /* Process unlocked */
00637       __HAL_UNLOCK(hadc);
00638     }
00639
00640     /* Return function status */
00641     return tmp_hal_status;
00642   }
00643 }
00644
00645 /**
00646   * @brief  Stop conversion of injected channels, disable interruption of
00647   *         end-of-conversion. Disable ADC peripheral if no regular conversion
00648   *         is on going.
00649   * @note   If ADC must be disabled and if conversion is on going on
00650   *         regular group, function HAL_ADC_Stop must be used to stop both
00651   *         injected and regular groups, and disable the ADC.
00652   * @note   If injected group mode auto-injection is enabled,
00653   *         function HAL_ADC_Stop must be used.
00654   * @note   In case of auto-injection mode, HAL_ADC_Stop() must be used.
00655   * @param hadc ADC handle
00656   * @retval HAL status
00657   */
00658 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc)
00659 {
00660   HAL_StatusTypeDef tmp_hal_status;
00661
00662   /* Check the parameters */
00663   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00664
00665   /* Process locked */
00666   __HAL_LOCK(hadc);
00667
00668   /* 1. Stop potential conversion on going on injected group only. */
00669   tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
00670
00671   /* Disable ADC peripheral if injected conversions are effectively stopped   */
00672   /* and if no conversion on the other group (regular group) is intended to   */
00673   /* continue.                                                                */
00674   if (tmp_hal_status == HAL_OK)
00675   {
00676     /* Disable ADC end of conversion interrupt for injected channels */
00677     __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_FLAG_JQOVF));
00678
00679     if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
00680     {
00681       /* 2. Disable the ADC peripheral */
00682       tmp_hal_status = ADC_Disable(hadc);
00683
00684       /* Check if ADC is effectively disabled */
00685       if (tmp_hal_status == HAL_OK)
00686       {
00687         /* Set ADC state */
00688         ADC_STATE_CLR_SET(hadc->State,
00689                           HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
00690                           HAL_ADC_STATE_READY);
00691       }
00692     }
00693     /* Conversion on injected group is stopped, but ADC not disabled since    */
00694     /* conversion on regular group is still running.                          */
00695     else
00696     {
00697       /* Set ADC state */
00698       CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
00699     }
00700   }
00701
00702   /* Process unlocked */
00703   __HAL_UNLOCK(hadc);
00704
00705   /* Return function status */
00706   return tmp_hal_status;
00707 }
00708
00709 /**
00710   * @brief  Get ADC injected group conversion result.
00711   * @note   Reading register JDRx automatically clears ADC flag JEOC
00712   *         (ADC group injected end of unitary conversion).
00713   * @note   This function does not clear ADC flag JEOS
00714   *         (ADC group injected end of sequence conversion)
00715   *         Occurrence of flag JEOS rising:
00716   *          - If sequencer is composed of 1 rank, flag JEOS is equivalent
00717   *            to flag JEOC.
00718   *          - If sequencer is composed of several ranks, during the scan
00719   *            sequence flag JEOC only is raised, at the end of the scan sequence
00720   *            both flags JEOC and EOS are raised.
00721   *         Flag JEOS must not be cleared by this function because
00722   *         it would not be compliant with low power features
00723   *         (feature low power auto-wait, not available on all STM32 families).
00724   *         To clear this flag, either use function:
00725   *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
00726   *         model polling: @ref HAL_ADCEx_InjectedPollForConversion()
00727   *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
00728   * @param hadc ADC handle
00729   * @param InjectedRank the converted ADC injected rank.
00730   *          This parameter can be one of the following values:
00731   *            @arg @ref ADC_INJECTED_RANK_1 ADC group injected rank 1
00732   *            @arg @ref ADC_INJECTED_RANK_2 ADC group injected rank 2
00733   *            @arg @ref ADC_INJECTED_RANK_3 ADC group injected rank 3
00734   *            @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4
00735   * @retval ADC group injected conversion data
00736   */
00737 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
00738 {
00739   uint32_t tmp_jdr;
00740
00741   /* Check the parameters */
00742   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00743   assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
00744
00745   /* Get ADC converted value */
00746   switch (InjectedRank)
00747   {
00748     case ADC_INJECTED_RANK_4:
00749       tmp_jdr = hadc->Instance->JDR4;
00750       break;
00751     case ADC_INJECTED_RANK_3:
00752       tmp_jdr = hadc->Instance->JDR3;
00753       break;
00754     case ADC_INJECTED_RANK_2:
00755       tmp_jdr = hadc->Instance->JDR2;
00756       break;
00757     case ADC_INJECTED_RANK_1:
00758     default:
00759       tmp_jdr = hadc->Instance->JDR1;
00760       break;
00761   }
00762
00763   /* Return ADC converted value */
00764   return tmp_jdr;
00765 }
00766
00767 /**
00768   * @brief  Injected conversion complete callback in non-blocking mode.
00769   * @param hadc ADC handle
00770   * @retval None
00771   */
00772 __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc)
00773 {
00774   /* Prevent unused argument(s) compilation warning */
00775   UNUSED(hadc);
00776
00777   /* NOTE : This function should not be modified. When the callback is needed,
00778             function HAL_ADCEx_InjectedConvCpltCallback must be implemented in the user file.
00779   */
00780 }
00781
00782 /**
00783   * @brief  Injected context queue overflow callback.
00784   * @note   This callback is called if injected context queue is enabled
00785             (parameter "QueueInjectedContext" in injected channel configuration)
00786             and if a new injected context is set when queue is full (maximum 2
00787             contexts).
00788   * @param hadc ADC handle
00789   * @retval None
00790   */
00791 __weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc)
00792 {
00793   /* Prevent unused argument(s) compilation warning */
00794   UNUSED(hadc);
00795
00796   /* NOTE : This function should not be modified. When the callback is needed,
00797             function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file.
00798   */
00799 }
00800
00801 /**
00802   * @brief  Analog watchdog 2 callback in non-blocking mode.
00803   * @param hadc ADC handle
00804   * @retval None
00805   */
00806 __weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc)
00807 {
00808   /* Prevent unused argument(s) compilation warning */
00809   UNUSED(hadc);
00810
00811   /* NOTE : This function should not be modified. When the callback is needed,
00812             function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file.
00813   */
00814 }
00815
00816 /**
00817   * @brief  Analog watchdog 3 callback in non-blocking mode.
00818   * @param hadc ADC handle
00819   * @retval None
00820   */
00821 __weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc)
00822 {
00823   /* Prevent unused argument(s) compilation warning */
00824   UNUSED(hadc);
00825
00826   /* NOTE : This function should not be modified. When the callback is needed,
00827             function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file.
00828   */
00829 }
00830
00831
00832 /**
00833   * @brief  End Of Sampling callback in non-blocking mode.
00834   * @param hadc ADC handle
00835   * @retval None
00836   */
00837 __weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc)
00838 {
00839   /* Prevent unused argument(s) compilation warning */
00840   UNUSED(hadc);
00841
00842   /* NOTE : This function should not be modified. When the callback is needed,
00843             function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file.
00844   */
00845 }
00846
00847 /**
00848   * @brief  Stop ADC conversion of regular group (and injected channels in
00849   *         case of auto_injection mode), disable ADC peripheral if no
00850   *         conversion is on going on injected group.
00851   * @param hadc ADC handle
00852   * @retval HAL status.
00853   */
00854 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc)
00855 {
00856   HAL_StatusTypeDef tmp_hal_status;
00857
00858   /* Check the parameters */
00859   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00860
00861   /* Process locked */
00862   __HAL_LOCK(hadc);
00863
00864   /* 1. Stop potential regular conversion on going */
00865   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
00866
00867   /* Disable ADC peripheral if regular conversions are effectively stopped
00868      and if no injected conversions are on-going */
00869   if (tmp_hal_status == HAL_OK)
00870   {
00871     /* Clear HAL_ADC_STATE_REG_BUSY bit */
00872     CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
00873
00874     if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
00875     {
00876       /* 2. Disable the ADC peripheral */
00877       tmp_hal_status = ADC_Disable(hadc);
00878
00879       /* Check if ADC is effectively disabled */
00880       if (tmp_hal_status == HAL_OK)
00881       {
00882         /* Set ADC state */
00883         ADC_STATE_CLR_SET(hadc->State,
00884                           HAL_ADC_STATE_INJ_BUSY,
00885                           HAL_ADC_STATE_READY);
00886       }
00887     }
00888     /* Conversion on injected group is stopped, but ADC not disabled since    */
00889     /* conversion on regular group is still running.                          */
00890     else
00891     {
00892       SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
00893     }
00894   }
00895
00896   /* Process unlocked */
00897   __HAL_UNLOCK(hadc);
00898
00899   /* Return function status */
00900   return tmp_hal_status;
00901 }
00902
00903
00904 /**
00905   * @brief  Stop ADC conversion of ADC groups regular and injected,
00906   *         disable interrution of end-of-conversion,
00907   *         disable ADC peripheral if no conversion is on going
00908   *         on injected group.
00909   * @param hadc ADC handle
00910   * @retval HAL status.
00911   */
00912 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc)
00913 {
00914   HAL_StatusTypeDef tmp_hal_status;
00915
00916   /* Check the parameters */
00917   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00918
00919   /* Process locked */
00920   __HAL_LOCK(hadc);
00921
00922   /* 1. Stop potential regular conversion on going */
00923   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
00924
00925   /* Disable ADC peripheral if conversions are effectively stopped
00926     and if no injected conversion is on-going */
00927   if (tmp_hal_status == HAL_OK)
00928   {
00929     /* Clear HAL_ADC_STATE_REG_BUSY bit */
00930     CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
00931
00932     /* Disable all regular-related interrupts */
00933     __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
00934
00935     /* 2. Disable ADC peripheral if no injected conversions are on-going */
00936     if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
00937     {
00938       tmp_hal_status = ADC_Disable(hadc);
00939       /* if no issue reported */
00940       if (tmp_hal_status == HAL_OK)
00941       {
00942         /* Set ADC state */
00943         ADC_STATE_CLR_SET(hadc->State,
00944                           HAL_ADC_STATE_INJ_BUSY,
00945                           HAL_ADC_STATE_READY);
00946       }
00947     }
00948     else
00949     {
00950       SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
00951     }
00952   }
00953
00954   /* Process unlocked */
00955   __HAL_UNLOCK(hadc);
00956
00957   /* Return function status */
00958   return tmp_hal_status;
00959 }
00960
00961 /**
00962   * @brief  Stop ADC conversion of regular group (and injected group in
00963   *         case of auto_injection mode), disable ADC DMA transfer, disable
00964   *         ADC peripheral if no conversion is on going
00965   *         on injected group.
00966   * @param hadc ADC handle
00967   * @retval HAL status.
00968   */
00969 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc)
00970 {
00971   HAL_StatusTypeDef tmp_hal_status;
00972
00973   /* Check the parameters */
00974   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00975
00976   /* Process locked */
00977   __HAL_LOCK(hadc);
00978
00979   /* 1. Stop potential regular conversion on going */
00980   tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
00981
00982   /* Disable ADC peripheral if conversions are effectively stopped
00983      and if no injected conversion is on-going */
00984   if (tmp_hal_status == HAL_OK)
00985   {
00986     /* Clear HAL_ADC_STATE_REG_BUSY bit */
00987     CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
00988
00989     /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
00990     CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
00991
00992     /* Disable the DMA channel (in case of DMA in circular mode or stop while */
00993     /* while DMA transfer is on going)                                        */
00994     tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
00995
00996     /* Check if DMA channel effectively disabled */
00997     if (tmp_hal_status != HAL_OK)
00998     {
00999       /* Update ADC state machine to error */
01000       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
01001     }
01002
01003     /* Disable ADC overrun interrupt */
01004     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
01005
01006     /* 2. Disable the ADC peripheral */
01007     /* Update "tmp_hal_status" only if DMA channel disabling passed,          */
01008     /* to keep in memory a potential failing status.                          */
01009     if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
01010     {
01011       if (tmp_hal_status == HAL_OK)
01012       {
01013         tmp_hal_status = ADC_Disable(hadc);
01014       }
01015       else
01016       {
01017         (void)ADC_Disable(hadc);
01018       }
01019
01020       /* Check if ADC is effectively disabled */
01021       if (tmp_hal_status == HAL_OK)
01022       {
01023         /* Set ADC state */
01024         ADC_STATE_CLR_SET(hadc->State,
01025                           HAL_ADC_STATE_INJ_BUSY,
01026                           HAL_ADC_STATE_READY);
01027       }
01028     }
01029     else
01030     {
01031       SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
01032     }
01033   }
01034
01035   /* Process unlocked */
01036   __HAL_UNLOCK(hadc);
01037
01038   /* Return function status */
01039   return tmp_hal_status;
01040 }
01041
01042 /**
01043   * @}
01044   */
01045
01046 /** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions
01047   * @brief    ADC Extended Peripheral Control functions
01048   *
01049 @verbatim
01050  ===============================================================================
01051              ##### Peripheral Control functions #####
01052  ===============================================================================
01053     [..]  This section provides functions allowing to:
01054       (+) Configure channels on injected group
01055       (+) Enable or Disable Injected Queue
01056       (+) Disable ADC voltage regulator
01057       (+) Enter ADC deep-power-down mode
01058
01059 @endverbatim
01060   * @{
01061   */
01062
01063 /**
01064   * @brief  Configure a channel to be assigned to ADC group injected.
01065   * @note   Possibility to update parameters on the fly:
01066   *         This function initializes injected group, following calls to this
01067   *         function can be used to reconfigure some parameters of structure
01068   *         "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC.
01069   *         The setting of these parameters is conditioned to ADC state:
01070   *         Refer to comments of structure "ADC_InjectionConfTypeDef".
01071   * @note   In case of usage of internal measurement channels:
01072   *         Vbat/VrefInt/TempSensor.
01073   *         These internal paths can be disabled using function
01074   *         HAL_ADC_DeInit().
01075   * @note   Caution: For Injected Context Queue use, a context must be fully
01076   *         defined before start of injected conversion. All channels are configured
01077   *         consecutively for the same ADC instance. Therefore, the number of calls to
01078   *         HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter
01079   *         InjectedNbrOfConversion for each context.
01080   *  - Example 1: If 1 context is intended to be used (or if there is no use of the
01081   *    Injected Queue Context feature) and if the context contains 3 injected ranks
01082   *    (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be
01083   *    called once for each channel (i.e. 3 times) before starting a conversion.
01084   *    This function must not be called to configure a 4th injected channel:
01085   *    it would start a new context into context queue.
01086   *  - Example 2: If 2 contexts are intended to be used and each of them contains
01087   *    3 injected ranks (InjectedNbrOfConversion = 3),
01088   *    HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and
01089   *    for each context (3 channels x 2 contexts = 6 calls). Conversion can
01090   *    start once the 1st context is set, that is after the first three
01091   *    HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly.
01092   * @param hadc ADC handle
01093   * @param sConfigInjected Structure of ADC injected group and ADC channel for
01094   *         injected group.
01095   * @retval HAL status
01096   */
01097 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected)
01098 {
01099   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
01100   uint32_t tmpOffsetShifted;
01101   uint32_t tmp_config_internal_channel;
01102   uint32_t tmp_adc_is_conversion_on_going_regular;
01103   uint32_t tmp_adc_is_conversion_on_going_injected;
01104   __IO uint32_t wait_loop_index = 0;
01105
01106   uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0U;
01107
01108   /* Check the parameters */
01109   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01110   assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
01111   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfigInjected->InjectedSingleDiff));
01112   assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
01113   assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->QueueInjectedContext));
01114   assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
01115   assert_param(IS_ADC_EXTTRIGINJEC(hadc, sConfigInjected->ExternalTrigInjecConv));
01116   assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber));
01117   assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset));
01118   assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjecOversamplingMode));
01119
01120   if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
01121   {
01122     assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
01123     assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
01124     assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
01125   }
01126
01127
01128   /* if JOVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
01129      ignored (considered as reset) */
01130   assert_param(!((sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) && (sConfigInjected->InjecOversamplingMode == ENABLE)));
01131
01132   /* JDISCEN and JAUTO bits can't be set at the same time  */
01133   assert_param(!((sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE)));
01134
01135   /*  DISCEN and JAUTO bits can't be set at the same time */
01136   assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE)));
01137
01138   /* Verification of channel number */
01139   if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
01140   {
01141     assert_param(IS_ADC_CHANNEL(hadc, sConfigInjected->InjectedChannel));
01142   }
01143   else
01144   {
01145     assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfigInjected->InjectedChannel));
01146   }
01147
01148   /* Process locked */
01149   __HAL_LOCK(hadc);
01150
01151   /* Configuration of injected group sequencer:                               */
01152   /* Hardware constraint: Must fully define injected context register JSQR    */
01153   /* before make it entering into injected sequencer queue.                   */
01154   /*                                                                          */
01155   /* - if scan mode is disabled:                                              */
01156   /*    * Injected channels sequence length is set to 0x00: 1 channel         */
01157   /*      converted (channel on injected rank 1)                              */
01158   /*      Parameter "InjectedNbrOfConversion" is discarded.                   */
01159   /*    * Injected context register JSQR setting is simple: register is fully */
01160   /*      defined on one call of this function (for injected rank 1) and can  */
01161   /*      be entered into queue directly.                                     */
01162   /* - if scan mode is enabled:                                               */
01163   /*    * Injected channels sequence length is set to parameter               */
01164   /*      "InjectedNbrOfConversion".                                          */
01165   /*    * Injected context register JSQR setting more complex: register is    */
01166   /*      fully defined over successive calls of this function, for each      */
01167   /*      injected channel rank. It is entered into queue only when all       */
01168   /*      injected ranks have been set.                                       */
01169   /*   Note: Scan mode is not present by hardware on this device, but used    */
01170   /*   by software for alignment over all STM32 devices.                      */
01171
01172   if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)  ||
01173       (sConfigInjected->InjectedNbrOfConversion == 1U))
01174   {
01175     /* Configuration of context register JSQR:                                */
01176     /*  - number of ranks in injected group sequencer: fixed to 1st rank      */
01177     /*    (scan mode disabled, only rank 1 used)                              */
01178     /*  - external trigger to start conversion                                */
01179     /*  - external trigger polarity                                           */
01180     /*  - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */
01181
01182     if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
01183     {
01184       /* Enable external trigger if trigger selection is different of         */
01185       /* software start.                                                      */
01186       /* Note: This configuration keeps the hardware feature of parameter     */
01187       /*       ExternalTrigInjecConvEdge "trigger edge none" equivalent to    */
01188       /*       software start.                                                */
01189       if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
01190       {
01191         tmp_JSQR_ContextQueueBeingBuilt = (ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1)
01192                                            | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
01193                                            | sConfigInjected->ExternalTrigInjecConvEdge
01194                                           );
01195       }
01196       else
01197       {
01198         tmp_JSQR_ContextQueueBeingBuilt = (ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1));
01199       }
01200
01201       MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_JSQR_ContextQueueBeingBuilt);
01202       /* For debug and informative reasons, hadc handle saves JSQR setting */
01203       hadc->InjectionConfig.ContextQueue = tmp_JSQR_ContextQueueBeingBuilt;
01204
01205     }
01206   }
01207   else
01208   {
01209     /* Case of scan mode enabled, several channels to set into injected group */
01210     /* sequencer.                                                             */
01211     /*                                                                        */
01212     /* Procedure to define injected context register JSQR over successive     */
01213     /* calls of this function, for each injected channel rank:                */
01214     /* 1. Start new context and set parameters related to all injected        */
01215     /*    channels: injected sequence length and trigger.                     */
01216
01217     /* if hadc->InjectionConfig.ChannelCount is equal to 0, this is the first */
01218     /*   call of the context under setting                                    */
01219     if (hadc->InjectionConfig.ChannelCount == 0U)
01220     {
01221       /* Initialize number of channels that will be configured on the context */
01222       /*  being built                                                         */
01223       hadc->InjectionConfig.ChannelCount = sConfigInjected->InjectedNbrOfConversion;
01224       /* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel()
01225          call, this context will be written in JSQR register at the last call.
01226          At this point, the context is merely reset  */
01227       hadc->InjectionConfig.ContextQueue = 0x00000000U;
01228
01229       /* Configuration of context register JSQR:                              */
01230       /*  - number of ranks in injected group sequencer                       */
01231       /*  - external trigger to start conversion                              */
01232       /*  - external trigger polarity                                         */
01233
01234       /* Enable external trigger if trigger selection is different of         */
01235       /* software start.                                                      */
01236       /* Note: This configuration keeps the hardware feature of parameter     */
01237       /*       ExternalTrigInjecConvEdge "trigger edge none" equivalent to    */
01238       /*       software start.                                                */
01239       if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
01240       {
01241         tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U)
01242                                            | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
01243                                            | sConfigInjected->ExternalTrigInjecConvEdge
01244                                           );
01245       }
01246       else
01247       {
01248         tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U));
01249       }
01250
01251     }
01252
01253     /* 2. Continue setting of context under definition with parameter       */
01254     /*    related to each channel: channel rank sequence                    */
01255     /* Clear the old JSQx bits for the selected rank */
01256     tmp_JSQR_ContextQueueBeingBuilt &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, sConfigInjected->InjectedRank);
01257
01258     /* Set the JSQx bits for the selected rank */
01259     tmp_JSQR_ContextQueueBeingBuilt |= ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank);
01260
01261     /* Decrease channel count  */
01262     hadc->InjectionConfig.ChannelCount--;
01263
01264     /* 3. tmp_JSQR_ContextQueueBeingBuilt is fully built for this HAL_ADCEx_InjectedConfigChannel()
01265           call, aggregate the setting to those already built during the previous
01266           HAL_ADCEx_InjectedConfigChannel() calls (for the same context of course)  */
01267     hadc->InjectionConfig.ContextQueue |= tmp_JSQR_ContextQueueBeingBuilt;
01268
01269     /* 4. End of context setting: if this is the last channel set, then write context
01270         into register JSQR and make it enter into queue                   */
01271     if (hadc->InjectionConfig.ChannelCount == 0U)
01272     {
01273       MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, hadc->InjectionConfig.ContextQueue);
01274     }
01275   }
01276
01277   /* Parameters update conditioned to ADC state:                              */
01278   /* Parameters that can be updated when ADC is disabled or enabled without   */
01279   /* conversion on going on injected group:                                   */
01280   /*  - Injected context queue: Queue disable (active context is kept) or     */
01281   /*    enable (context decremented, up to 2 contexts queued)                 */
01282   /*  - Injected discontinuous mode: can be enabled only if auto-injected     */
01283   /*    mode is disabled.                                                     */
01284   if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
01285   {
01286     /* If auto-injected mode is disabled: no constraint                       */
01287     if (sConfigInjected->AutoInjectedConv == DISABLE)
01288     {
01289       MODIFY_REG(hadc->Instance->CFGR,
01290                  ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
01291                  ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext)           |
01292                  ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)sConfigInjected->InjectedDiscontinuousConvMode));
01293     }
01294     /* If auto-injected mode is enabled: Injected discontinuous setting is    */
01295     /* discarded.                                                             */
01296     else
01297     {
01298       MODIFY_REG(hadc->Instance->CFGR,
01299                  ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
01300                  ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext));
01301     }
01302
01303   }
01304
01305   /* Parameters update conditioned to ADC state:                              */
01306   /* Parameters that can be updated when ADC is disabled or enabled without   */
01307   /* conversion on going on regular and injected groups:                      */
01308   /*  - Automatic injected conversion: can be enabled if injected group       */
01309   /*    external triggers are disabled.                                       */
01310   /*  - Channel sampling time                                                 */
01311   /*  - Channel offset                                                        */
01312   tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
01313   tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
01314
01315   if ((tmp_adc_is_conversion_on_going_regular == 0UL)
01316       && (tmp_adc_is_conversion_on_going_injected == 0UL)
01317      )
01318   {
01319     /* If injected group external triggers are disabled (set to injected      */
01320     /* software start): no constraint                                         */
01321     if ((sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
01322         || (sConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
01323     {
01324       if (sConfigInjected->AutoInjectedConv == ENABLE)
01325       {
01326         SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
01327       }
01328       else
01329       {
01330         CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
01331       }
01332     }
01333     /* If Automatic injected conversion was intended to be set and could not  */
01334     /* due to injected group external triggers enabled, error is reported.    */
01335     else
01336     {
01337       if (sConfigInjected->AutoInjectedConv == ENABLE)
01338       {
01339         /* Update ADC state machine to error */
01340         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
01341
01342         tmp_hal_status = HAL_ERROR;
01343       }
01344       else
01345       {
01346         CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
01347       }
01348     }
01349
01350     if (sConfigInjected->InjecOversamplingMode == ENABLE)
01351     {
01352       assert_param(IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio));
01353       assert_param(IS_ADC_RIGHT_BIT_SHIFT(sConfigInjected->InjecOversampling.RightBitShift));
01354
01355       /*  JOVSE must be reset in case of triggered regular mode  */
01356       assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS) == (ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS)));
01357
01358       /* Configuration of Injected Oversampler:                                 */
01359       /*  - Oversampling Ratio                                                  */
01360       /*  - Right bit shift                                                     */
01361
01362       /* Enable OverSampling mode */
01363       MODIFY_REG(hadc->Instance->CFGR2,
01364                  ADC_CFGR2_JOVSE |
01365                  ADC_CFGR2_OVSR  |
01366                  ADC_CFGR2_OVSS,
01367                  ADC_CFGR2_JOVSE                                  |
01368                  sConfigInjected->InjecOversampling.Ratio         |
01369                  sConfigInjected->InjecOversampling.RightBitShift
01370                 );
01371     }
01372     else
01373     {
01374       /* Disable Regular OverSampling */
01375       CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_JOVSE);
01376     }
01377
01378       /* Set sampling time of the selected ADC channel */
01379       LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSamplingTime);
01380
01381     /* Configure the offset: offset enable/disable, channel, offset value */
01382
01383     /* Shift the offset with respect to the selected ADC resolution. */
01384     /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
01385     tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset);
01386
01387     if (sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE)
01388     {
01389       /* Set ADC selected offset number */
01390       LL_ADC_SetOffset(hadc->Instance, sConfigInjected->InjectedOffsetNumber, sConfigInjected->InjectedChannel,
01391                        tmpOffsetShifted);
01392
01393     }
01394     else
01395     {
01396       /* Scan each offset register to check if the selected channel is targeted. */
01397       /* If this is the case, the corresponding offset number is disabled.       */
01398       if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
01399       {
01400         LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
01401       }
01402       if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
01403       {
01404         LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
01405       }
01406       if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
01407       {
01408         LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
01409       }
01410       if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
01411       {
01412         LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
01413       }
01414     }
01415
01416   }
01417
01418   /* Parameters update conditioned to ADC state:                              */
01419   /* Parameters that can be updated only when ADC is disabled:                */
01420   /*  - Single or differential mode                                           */
01421   /*  - Internal measurement channels: Vbat/VrefInt/TempSensor                */
01422   if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
01423   {
01424     /* Set mode single-ended or differential input of the selected ADC channel */
01425     LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSingleDiff);
01426
01427     /* Configuration of differential mode */
01428     /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
01429     if (sConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED)
01430     {
01431       /* Set sampling time of the selected ADC channel */
01432       LL_ADC_SetChannelSamplingTime(hadc->Instance, (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfigInjected->InjectedChannel) + 1UL) & 0x1FUL)), sConfigInjected->InjectedSamplingTime);
01433     }
01434
01435     /* Management of internal measurement channels: Vbat/VrefInt/TempSensor   */
01436     /* internal measurement paths enable: If internal channel selected,       */
01437     /* enable dedicated internal buffers and path.                            */
01438     /* Note: these internal measurement paths can be disabled using           */
01439     /* HAL_ADC_DeInit().                                                      */
01440
01441     if(__LL_ADC_IS_CHANNEL_INTERNAL(sConfigInjected->InjectedChannel))
01442     {
01443       /* Configuration of common ADC parameters (continuation)                */
01444       /* Software is allowed to change common parameters only when all ADCs   */
01445       /* of the common group are disabled.                                    */
01446       if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
01447       {
01448         tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
01449
01450         /* If the requested internal measurement path has already been enabled, */
01451         /* bypass the configuration processing.                                 */
01452         if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
01453         {
01454           if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
01455           {
01456             LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
01457
01458             /* Delay for temperature sensor stabilization time */
01459             /* Wait loop initialization and execution */
01460             /* Note: Variable divided by 2 to compensate partially              */
01461             /*       CPU processing cycles, scaling in us split to not          */
01462             /*       exceed 32 bits register capacity and handle low frequency. */
01463             wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
01464             while(wait_loop_index != 0UL)
01465             {
01466               wait_loop_index--;
01467             }
01468           }
01469         }
01470         else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
01471         {
01472           if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
01473           {
01474             LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
01475           }
01476         }
01477         else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
01478         {
01479           if (ADC_VREFINT_INSTANCE(hadc))
01480           {
01481             LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
01482           }
01483         }
01484         else
01485         {
01486           /* nothing to do */
01487         }
01488       }
01489       /* If the requested internal measurement path has already been enabled  */
01490       /* and other ADC of the common group are enabled, internal              */
01491       /* measurement paths cannot be enabled.                                 */
01492       else
01493       {
01494         /* Update ADC state machine to error */
01495         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
01496
01497         tmp_hal_status = HAL_ERROR;
01498       }
01499     }
01500
01501   }
01502
01503   /* Process unlocked */
01504   __HAL_UNLOCK(hadc);
01505
01506   /* Return function status */
01507   return tmp_hal_status;
01508 }
01509
01510 /**
01511   * @brief  Enable Injected Queue
01512   * @note   This function resets CFGR register JQDIS bit in order to enable the
01513   *         Injected Queue. JQDIS can be written only when ADSTART and JDSTART
01514   *         are both equal to 0 to ensure that no regular nor injected
01515   *         conversion is ongoing.
01516   * @param hadc ADC handle
01517   * @retval HAL status
01518   */
01519 HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc)
01520 {
01521   HAL_StatusTypeDef tmp_hal_status;
01522   uint32_t tmp_adc_is_conversion_on_going_regular;
01523   uint32_t tmp_adc_is_conversion_on_going_injected;
01524
01525   /* Check the parameters */
01526   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01527
01528   tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
01529   tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
01530
01531   /* Parameter can be set only if no conversion is on-going */
01532   if ((tmp_adc_is_conversion_on_going_regular == 0UL)
01533       && (tmp_adc_is_conversion_on_going_injected == 0UL)
01534      )
01535   {
01536     CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
01537
01538     /* Update state, clear previous result related to injected queue overflow */
01539     CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
01540
01541     tmp_hal_status = HAL_OK;
01542   }
01543   else
01544   {
01545     tmp_hal_status = HAL_ERROR;
01546   }
01547
01548   return tmp_hal_status;
01549 }
01550
01551 /**
01552   * @brief  Disable Injected Queue
01553   * @note   This function sets CFGR register JQDIS bit in order to disable the
01554   *         Injected Queue. JQDIS can be written only when ADSTART and JDSTART
01555   *         are both equal to 0 to ensure that no regular nor injected
01556   *         conversion is ongoing.
01557   * @param hadc ADC handle
01558   * @retval HAL status
01559   */
01560 HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc)
01561 {
01562   HAL_StatusTypeDef tmp_hal_status;
01563   uint32_t tmp_adc_is_conversion_on_going_regular;
01564   uint32_t tmp_adc_is_conversion_on_going_injected;
01565
01566   /* Check the parameters */
01567   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01568
01569   tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
01570   tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
01571
01572   /* Parameter can be set only if no conversion is on-going */
01573   if ((tmp_adc_is_conversion_on_going_regular == 0UL)
01574       && (tmp_adc_is_conversion_on_going_injected == 0UL)
01575      )
01576   {
01577     LL_ADC_INJ_SetQueueMode(hadc->Instance, LL_ADC_INJ_QUEUE_DISABLE);
01578     tmp_hal_status = HAL_OK;
01579   }
01580   else
01581   {
01582     tmp_hal_status = HAL_ERROR;
01583   }
01584
01585   return tmp_hal_status;
01586 }
01587
01588 /**
01589   * @brief  Disable ADC voltage regulator.
01590   * @note   Disabling voltage regulator allows to save power. This operation can
01591   *         be carried out only when ADC is disabled.
01592   * @note   To enable again the voltage regulator, the user is expected to
01593   *         resort to HAL_ADC_Init() API.
01594   * @param hadc ADC handle
01595   * @retval HAL status
01596   */
01597 HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc)
01598 {
01599   HAL_StatusTypeDef tmp_hal_status;
01600
01601   /* Check the parameters */
01602   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01603
01604   /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
01605   if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
01606   {
01607     LL_ADC_DisableInternalRegulator(hadc->Instance);
01608     tmp_hal_status = HAL_OK;
01609   }
01610   else
01611   {
01612     tmp_hal_status = HAL_ERROR;
01613   }
01614
01615   return tmp_hal_status;
01616 }
01617
01618 /**
01619   * @brief  Enter ADC deep-power-down mode
01620   * @note   This mode is achieved in setting DEEPPWD bit and allows to save power
01621   *         in reducing leakage currents. It is particularly interesting before
01622   *         entering stop modes.
01623   * @note   Setting DEEPPWD automatically clears ADVREGEN bit and disables the
01624   *         ADC voltage regulator. This means that this API encompasses
01625   *         HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal
01626   *         calibration is lost.
01627   * @note   To exit the ADC deep-power-down mode, the user is expected to
01628   *         resort to HAL_ADC_Init() API as well as to relaunch a calibration
01629   *         with HAL_ADCEx_Calibration_Start() API or to re-apply a previously
01630   *         saved calibration factor.
01631   * @param hadc ADC handle
01632   * @retval HAL status
01633   */
01634 HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc)
01635 {
01636   HAL_StatusTypeDef tmp_hal_status;
01637
01638   /* Check the parameters */
01639   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01640
01641   /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
01642   if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
01643   {
01644     LL_ADC_EnableDeepPowerDown(hadc->Instance);
01645     tmp_hal_status = HAL_OK;
01646   }
01647   else
01648   {
01649     tmp_hal_status = HAL_ERROR;
01650   }
01651
01652   return tmp_hal_status;
01653 }
01654
01655 /**
01656   * @}
01657   */
01658
01659 /**
01660   * @}
01661   */
01662
01663 #endif /* HAL_ADC_MODULE_ENABLED */
01664 /**
01665   * @}
01666   */
01667
01668 /**
01669   * @}
01670   */
01671
01672 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:33 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_adc_ex.h Source File

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stm32wbxx_hal_adc_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_adc_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of ADC HAL extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_ADC_EX_H
00022 #define STM32WBxx_HAL_ADC_EX_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 /** @addtogroup STM32WBxx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup ADCEx
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup ADCEx_Exported_Types ADC Extended Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief  ADC Injected Conversion Oversampling structure definition
00046   */
00047 typedef struct
00048 {
00049   uint32_t Ratio;                         /*!< Configures the oversampling ratio.
00050                                                This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
00051
00052   uint32_t RightBitShift;                 /*!< Configures the division coefficient for the Oversampler.
00053                                                This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
00054 } ADC_InjOversamplingTypeDef;
00055
00056 /**
00057   * @brief  Structure definition of ADC group injected and ADC channel affected to ADC group injected
00058   * @note   Parameters of this structure are shared within 2 scopes:
00059   *          - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset
00060   *          - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
00061   *            AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling.
00062   * @note   The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
00063   *         ADC state can be either:
00064   *          - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff')
00065   *          - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group.
00066   *          - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups.
00067   *          - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going
00068   *            on ADC groups regular and injected.
00069   *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
00070   *         without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
00071   */
00072 typedef struct
00073 {
00074   uint32_t InjectedChannel;               /*!< Specifies the channel to configure into ADC group injected.
00075                                                This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
00076                                                Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
00077
00078   uint32_t InjectedRank;                  /*!< Specifies the rank in the ADC group injected sequencer.
00079                                                This parameter must be a value of @ref ADC_INJ_SEQ_RANKS.
00080                                                Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by
00081                                                the new channel setting (or parameter number of conversions adjusted) */
00082
00083   uint32_t InjectedSamplingTime;          /*!< Sampling time value to be set for the selected channel.
00084                                                Unit: ADC clock cycles.
00085                                                Conversion time is the addition of sampling time and processing time
00086                                                (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
00087                                                This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME.
00088                                                Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
00089                                                         It overwrites the last setting.
00090                                                Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
00091                                                      sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
00092                                                      Refer to device datasheet for timings values. */
00093
00094   uint32_t InjectedSingleDiff;            /*!< Selection of single-ended or differential input.
00095                                                In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
00096                                                Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
00097                                                This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING.
00098                                                Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
00099                                                         It overwrites the last setting.
00100                                                Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.
00101                                                Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
00102                                                Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
00103                                                If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case
00104                                                of another parameter update on the fly) */
00105
00106   uint32_t InjectedOffsetNumber;          /*!< Selects the offset number.
00107                                                This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB.
00108                                                Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */
00109
00110   uint32_t InjectedOffset;                /*!< Defines the offset to be subtracted from the raw converted data.
00111                                                Offset value must be a positive number.
00112                                                Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
00113                                                between Min_Data = 0x000 and Max_Data = 0xFFF,  0x3FF, 0xFF or 0x3F respectively.
00114                                                Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
00115                                                without continuous mode or external trigger that could launch a conversion). */
00116
00117   uint32_t InjectedNbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer.
00118                                                To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
00119                                                This parameter must be a number between Min_Data = 1 and Max_Data = 4.
00120                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00121                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00122
00123   FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence
00124                                                (main sequence subdivided in successive parts).
00125                                                Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
00126                                                Discontinuous mode can be enabled only if continuous mode is disabled.
00127                                                This parameter can be set to ENABLE or DISABLE.
00128                                                Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
00129                                                Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank).
00130                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00131                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00132
00133   FunctionalState AutoInjectedConv;       /*!< Enables or disables the selected ADC group injected automatic conversion after regular one
00134                                                This parameter can be set to ENABLE or DISABLE.
00135                                                Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
00136                                                Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START)
00137                                                Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
00138                                                      To maintain JAUTO always enabled, DMA must be configured in circular mode.
00139                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00140                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00141
00142   FunctionalState QueueInjectedContext;   /*!< Specifies whether the context queue feature is enabled.
00143                                                This parameter can be set to ENABLE or DISABLE.
00144                                                If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a
00145                                                new injected context is set when queue is full, error is triggered by interruption and through function
00146                                                'HAL_ADCEx_InjectedQueueOverflowCallback'.
00147                                                Caution: This feature request that the sequence is fully configured before injected conversion start.
00148                                                         Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter.
00149                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00150                                                         configure a channel on injected group can impact the configuration of other channels previously set.
00151                                                Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */
00152
00153   uint32_t ExternalTrigInjecConv;         /*!< Selects the external event used to trigger the conversion start of injected group.
00154                                                If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
00155                                                This parameter can be a value of @ref ADC_injected_external_trigger_source.
00156                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00157                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00158
00159   uint32_t ExternalTrigInjecConvEdge;     /*!< Selects the external trigger edge of injected group.
00160                                                This parameter can be a value of @ref ADC_injected_external_trigger_edge.
00161                                                If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
00162                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00163                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00164
00165   FunctionalState InjecOversamplingMode;         /*!< Specifies whether the oversampling feature is enabled or disabled.
00166                                                       This parameter can be set to ENABLE or DISABLE.
00167                                                       Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
00168
00169   ADC_InjOversamplingTypeDef  InjecOversampling; /*!< Specifies the Oversampling parameters.
00170                                                       Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled.
00171                                                       Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
00172 } ADC_InjectionConfTypeDef;
00173
00174 /**
00175   * @}
00176   */
00177
00178 /* Exported constants --------------------------------------------------------*/
00179
00180 /** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants
00181   * @{
00182   */
00183
00184 /** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source
00185   * @{
00186   */
00187 /* ADC group regular trigger sources for all ADC instances */
00188 #define ADC_INJECTED_SOFTWARE_START        (LL_ADC_INJ_TRIG_SOFTWARE)            /*!< Software triggers injected group conversion start */
00189 #define ADC_EXTERNALTRIGINJEC_T1_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)       /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
00190 #define ADC_EXTERNALTRIGINJEC_T1_TRGO2     (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)      /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
00191 #define ADC_EXTERNALTRIGINJEC_T1_CC4       (LL_ADC_INJ_TRIG_EXT_TIM1_CH4)        /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00192 #define ADC_EXTERNALTRIGINJEC_T2_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)       /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
00193 #define ADC_EXTERNALTRIGINJEC_T2_CC1       (LL_ADC_INJ_TRIG_EXT_TIM2_CH1)        /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00194 #define ADC_EXTERNALTRIGINJEC_EXT_IT15     (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)     /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */
00195 /**
00196   * @}
00197   */
00198
00199 /** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected)
00200   * @{
00201   */
00202 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE           (0x00000000UL)        /*!< Injected conversions hardware trigger detection disabled                             */
00203 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING         (ADC_JSQR_JEXTEN_0)   /*!< Injected conversions hardware trigger detection on the rising edge                   */
00204 #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING        (ADC_JSQR_JEXTEN_1)   /*!< Injected conversions hardware trigger detection on the falling edge                  */
00205 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING  (ADC_JSQR_JEXTEN)     /*!< Injected conversions hardware trigger detection on both the rising and falling edges */
00206 /**
00207   * @}
00208   */
00209
00210 /** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING  Channel - Single or differential ending
00211   * @{
00212   */
00213 #define ADC_SINGLE_ENDED                (LL_ADC_SINGLE_ENDED)         /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
00214 #define ADC_DIFFERENTIAL_ENDED          (LL_ADC_DIFFERENTIAL_ENDED)   /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
00215 /**
00216   * @}
00217   */
00218
00219 /** @defgroup ADC_HAL_EC_OFFSET_NB  ADC instance - Offset number
00220   * @{
00221   */
00222 #define ADC_OFFSET_NONE              (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected ADC channel */
00223 #define ADC_OFFSET_1                 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
00224 #define ADC_OFFSET_2                 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
00225 #define ADC_OFFSET_3                 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
00226 #define ADC_OFFSET_4                 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
00227 /**
00228   * @}
00229   */
00230
00231 /** @defgroup ADC_INJ_SEQ_RANKS  ADC group injected - Sequencer ranks
00232   * @{
00233   */
00234 #define ADC_INJECTED_RANK_1                (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */
00235 #define ADC_INJECTED_RANK_2                (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */
00236 #define ADC_INJECTED_RANK_3                (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */
00237 #define ADC_INJECTED_RANK_4                (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */
00238 /**
00239   * @}
00240   */
00241
00242 /** @defgroup ADC_HAL_EC_GROUPS  ADC instance - Groups
00243   * @{
00244   */
00245 #define ADC_REGULAR_GROUP                  (LL_ADC_GROUP_REGULAR)           /*!< ADC group regular (available on all STM32 devices) */
00246 #define ADC_INJECTED_GROUP                 (LL_ADC_GROUP_INJECTED)          /*!< ADC group injected (not available on all STM32 devices)*/
00247 #define ADC_REGULAR_INJECTED_GROUP         (LL_ADC_GROUP_REGULAR_INJECTED)  /*!< ADC both groups regular and injected */
00248 /**
00249   * @}
00250   */
00251
00252 /** @defgroup ADC_CFGR_fields ADCx CFGR fields
00253   * @{
00254   */
00255 #define ADC_CFGR_FIELDS    (ADC_CFGR_AWD1CH  | ADC_CFGR_JAUTO   | ADC_CFGR_JAWD1EN |\
00256                             ADC_CFGR_AWD1EN  | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM     |\
00257                             ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN  |\
00258                             ADC_CFGR_AUTDLY  | ADC_CFGR_CONT    | ADC_CFGR_OVRMOD  |\
00259                             ADC_CFGR_EXTEN   | ADC_CFGR_EXTSEL  | ADC_CFGR_ALIGN   |\
00260                             ADC_CFGR_RES     | ADC_CFGR_DMACFG  | ADC_CFGR_DMAEN   )
00261 /**
00262   * @}
00263   */
00264
00265 /** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields
00266   * @{
00267   */
00268 #define ADC_SMPR1_FIELDS    (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\
00269                              ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\
00270                              ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\
00271                              ADC_SMPR1_SMP0)
00272 /**
00273   * @}
00274   */
00275
00276 /** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields
00277   * @{
00278   */
00279 /* ADC_CFGR fields of parameters that can be updated when no conversion
00280    (neither regular nor injected) is on-going  */
00281 #define ADC_CFGR_FIELDS_2  ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY))
00282 /**
00283   * @}
00284   */
00285
00286
00287 /**
00288   * @}
00289   */
00290
00291 /* Exported macros -----------------------------------------------------------*/
00292
00293 /* Private macros ------------------------------------------------------------*/
00294
00295 /** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros
00296   * @{
00297   */
00298 /* Macro reserved for internal HAL driver usage, not intended to be used in   */
00299 /* code of final user.                                                        */
00300
00301 /**
00302   * @brief Test if conversion trigger of injected group is software start
00303   *        or external trigger.
00304   * @param __HANDLE__ ADC handle.
00305   * @retval SET (software start) or RESET (external trigger).
00306   */
00307 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__)                             \
00308   (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL)
00309
00310 /**
00311   * @brief Check whether or not ADC is independent.
00312   * @param __HANDLE__ ADC handle.
00313   * @note  When multimode feature is not available, the macro always returns SET.
00314   * @retval SET (ADC is independent) or RESET (ADC is not).
00315   */
00316 #define ADC_IS_INDEPENDENT(__HANDLE__)   (SET)
00317
00318 /**
00319   * @brief Set the selected injected Channel rank.
00320   * @param __CHANNELNB__ Channel number.
00321   * @param __RANKNB__ Rank number.
00322   * @retval None
00323   */
00324 #define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))
00325
00326 /**
00327   * @brief Configure ADC injected context queue
00328   * @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode.
00329   * @retval None
00330   */
00331 #define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos)
00332
00333 /**
00334   * @brief Configure ADC discontinuous conversion mode for injected group
00335   * @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode.
00336   * @retval None
00337   */
00338 #define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) <<  ADC_CFGR_JDISCEN_Pos)
00339
00340 /**
00341   * @brief Configure ADC discontinuous conversion mode for regular group
00342   * @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode.
00343   * @retval None
00344   */
00345 #define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos)
00346
00347 /**
00348   * @brief Configure the number of discontinuous conversions for regular group.
00349   * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions.
00350   * @retval None
00351   */
00352 #define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos)
00353
00354 /**
00355   * @brief Configure the ADC auto delay mode.
00356   * @param __AUTOWAIT__ Auto delay bit enable or disable.
00357   * @retval None
00358   */
00359 #define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos)
00360
00361 /**
00362   * @brief Configure ADC continuous conversion mode.
00363   * @param __CONTINUOUS_MODE__ Continuous mode.
00364   * @retval None
00365   */
00366 #define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos)
00367
00368 /**
00369   * @brief Configure the ADC DMA continuous request.
00370   * @param __DMACONTREQ_MODE__ DMA continuous request mode.
00371   * @retval None
00372   */
00373 #define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) <<  ADC_CFGR_DMACFG_Pos)
00374
00375
00376 /**
00377   * @brief Shift the offset with respect to the selected ADC resolution.
00378   * @note   Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0.
00379   *         If resolution 12 bits, no shift.
00380   *         If resolution 10 bits, shift of 2 ranks on the left.
00381   *         If resolution 8 bits, shift of 4 ranks on the left.
00382   *         If resolution 6 bits, shift of 6 ranks on the left.
00383   *         Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
00384   * @param __HANDLE__ ADC handle
00385   * @param __OFFSET__ Value to be shifted
00386   * @retval None
00387   */
00388 #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \
00389   ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL))
00390
00391 /**
00392   * @brief Shift the AWD1 threshold with respect to the selected ADC resolution.
00393   * @note  Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0.
00394   *        If resolution 12 bits, no shift.
00395   *        If resolution 10 bits, shift of 2 ranks on the left.
00396   *        If resolution 8 bits, shift of 4 ranks on the left.
00397   *        If resolution 6 bits, shift of 6 ranks on the left.
00398   *        Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
00399   * @param __HANDLE__ ADC handle
00400   * @param __THRESHOLD__ Value to be shifted
00401   * @retval None
00402   */
00403 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
00404   ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL))
00405
00406 /**
00407   * @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution.
00408   * @note  Thresholds have to be left-aligned on bit 7.
00409   *        If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded).
00410   *        If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded).
00411   *        If resolution 8 bits, no shift.
00412   *        If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0).
00413   * @param __HANDLE__ ADC handle
00414   * @param __THRESHOLD__ Value to be shifted
00415   * @retval None
00416   */
00417 #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__)                                       \
00418   ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0))                    ? \
00419    ((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \
00420    ((__THRESHOLD__) << 2UL)                                                                                 \
00421   )
00422
00423 /**
00424   * @brief Clear Common Control Register.
00425   * @param __HANDLE__ ADC handle.
00426   * @retval None
00427   */
00428 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE | \
00429                                                                                                       ADC_CCR_PRESC  | \
00430                                                                                                       ADC_CCR_VBATEN | \
00431                                                                                                       ADC_CCR_TSEN   | \
00432                                                                                                       ADC_CCR_VREFEN )
00433
00434
00435 /**
00436   * @brief Verify the ADC instance connected to the temperature sensor.
00437   * @param __HANDLE__ ADC handle.
00438   * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
00439   */
00440 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC1)
00441
00442 /**
00443   * @brief Verify the ADC instance connected to the battery voltage VBAT.
00444   * @param __HANDLE__ ADC handle.
00445   * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
00446   */
00447 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC1)
00448
00449 /**
00450   * @brief Verify the ADC instance connected to the internal voltage reference VREFINT.
00451   * @param __HANDLE__ ADC handle.
00452   * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
00453   */
00454 #define ADC_VREFINT_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC1)
00455
00456 /**
00457   * @brief Verify the length of scheduled injected conversions group.
00458   * @param __LENGTH__ number of programmed conversions.
00459   * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large)
00460   */
00461 #define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))
00462
00463 /**
00464   * @brief Calibration factor size verification (7 bits maximum).
00465   * @param __CALIBRATION_FACTOR__ Calibration factor value.
00466   * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)
00467   */
00468 #define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
00469
00470
00471 /**
00472   * @brief Verify the ADC channel setting.
00473   * @param __HANDLE__ ADC handle.
00474   * @param __CHANNEL__ programmed ADC channel.
00475   * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
00476   */
00477 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ((((__HANDLE__)->Instance) == ADC1)  && \
00478                                                          (((__CHANNEL__) == ADC_CHANNEL_0)           || \
00479                                                           ((__CHANNEL__) == ADC_CHANNEL_1)           || \
00480                                                           ((__CHANNEL__) == ADC_CHANNEL_2)           || \
00481                                                           ((__CHANNEL__) == ADC_CHANNEL_3)           || \
00482                                                           ((__CHANNEL__) == ADC_CHANNEL_4)           || \
00483                                                           ((__CHANNEL__) == ADC_CHANNEL_5)           || \
00484                                                           ((__CHANNEL__) == ADC_CHANNEL_6)           || \
00485                                                           ((__CHANNEL__) == ADC_CHANNEL_7)           || \
00486                                                           ((__CHANNEL__) == ADC_CHANNEL_8)           || \
00487                                                           ((__CHANNEL__) == ADC_CHANNEL_9)           || \
00488                                                           ((__CHANNEL__) == ADC_CHANNEL_10)          || \
00489                                                           ((__CHANNEL__) == ADC_CHANNEL_11)          || \
00490                                                           ((__CHANNEL__) == ADC_CHANNEL_12)          || \
00491                                                           ((__CHANNEL__) == ADC_CHANNEL_13)          || \
00492                                                           ((__CHANNEL__) == ADC_CHANNEL_14)          || \
00493                                                           ((__CHANNEL__) == ADC_CHANNEL_15)          || \
00494                                                           ((__CHANNEL__) == ADC_CHANNEL_16)          || \
00495                                                           ((__CHANNEL__) == ADC_CHANNEL_17)          || \
00496                                                           ((__CHANNEL__) == ADC_CHANNEL_18)          || \
00497                                                           ((__CHANNEL__) == ADC_CHANNEL_VREFINT)     || \
00498                                                           ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR)  || \
00499                                                           ((__CHANNEL__) == ADC_CHANNEL_VBAT)))
00500
00501 /**
00502   * @brief Verify the ADC channel setting in differential mode.
00503   * @param __HANDLE__ ADC handle.
00504   * @param __CHANNEL__ programmed ADC channel.
00505   * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
00506   */
00507 #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1)      || \
00508                                                       ((__CHANNEL__) == ADC_CHANNEL_2)      || \
00509                                                       ((__CHANNEL__) == ADC_CHANNEL_3)      || \
00510                                                       ((__CHANNEL__) == ADC_CHANNEL_4)      || \
00511                                                       ((__CHANNEL__) == ADC_CHANNEL_5)      || \
00512                                                       ((__CHANNEL__) == ADC_CHANNEL_6)      || \
00513                                                       ((__CHANNEL__) == ADC_CHANNEL_7)      || \
00514                                                       ((__CHANNEL__) == ADC_CHANNEL_8)      || \
00515                                                       ((__CHANNEL__) == ADC_CHANNEL_9)      || \
00516                                                       ((__CHANNEL__) == ADC_CHANNEL_10)     || \
00517                                                       ((__CHANNEL__) == ADC_CHANNEL_11)     || \
00518                                                       ((__CHANNEL__) == ADC_CHANNEL_12)     || \
00519                                                       ((__CHANNEL__) == ADC_CHANNEL_13)     || \
00520                                                       ((__CHANNEL__) == ADC_CHANNEL_14)     || \
00521                                                       ((__CHANNEL__) == ADC_CHANNEL_15)       )
00522
00523 /**
00524   * @brief Verify the ADC single-ended input or differential mode setting.
00525   * @param __SING_DIFF__ programmed channel setting.
00526   * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid)
00527   */
00528 #define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED)      || \
00529                                                    ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED)  )
00530
00531 /**
00532   * @brief Verify the ADC offset management setting.
00533   * @param __OFFSET_NUMBER__ ADC offset management.
00534   * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid)
00535   */
00536 #define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \
00537                                                  ((__OFFSET_NUMBER__) == ADC_OFFSET_1)    || \
00538                                                  ((__OFFSET_NUMBER__) == ADC_OFFSET_2)    || \
00539                                                  ((__OFFSET_NUMBER__) == ADC_OFFSET_3)    || \
00540                                                  ((__OFFSET_NUMBER__) == ADC_OFFSET_4)      )
00541
00542 /**
00543   * @brief Verify the ADC injected channel setting.
00544   * @param __CHANNEL__ programmed ADC injected channel.
00545   * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
00546   */
00547 #define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \
00548                                            ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \
00549                                            ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \
00550                                            ((__CHANNEL__) == ADC_INJECTED_RANK_4)   )
00551
00552 /**
00553   * @brief Verify the ADC injected conversions external trigger.
00554   * @param __HANDLE__ ADC handle.
00555   * @param __INJTRIG__ programmed ADC injected conversions external trigger.
00556   * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid)
00557   */
00558 #define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO)     || \
00559                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4)      || \
00560                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO)     || \
00561                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1)      || \
00562                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15)    || \
00563                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2)    || \
00564                                                       ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START)       )
00565
00566 /**
00567   * @brief Verify the ADC edge trigger setting for injected group.
00568   * @param __EDGE__ programmed ADC edge trigger setting.
00569   * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
00570   */
00571 #define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)         || \
00572                                             ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING)       || \
00573                                             ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING)      || \
00574                                             ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )
00575
00576 /**
00577   * @brief Verify the ADC analog watchdog setting.
00578   * @param __WATCHDOG__ programmed ADC analog watchdog setting.
00579   * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid)
00580   */
00581 #define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \
00582                                                      ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \
00583                                                      ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3)   )
00584
00585 /**
00586   * @brief Verify the ADC analog watchdog mode setting.
00587   * @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting.
00588   * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid)
00589   */
00590 #define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE)             || \
00591                                                         ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG)       || \
00592                                                         ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)     || \
00593                                                         ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)  || \
00594                                                         ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG)          || \
00595                                                         ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC)        || \
00596                                                         ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)       )
00597
00598 /**
00599   * @brief Verify the ADC conversion (regular or injected or both).
00600   * @param __CONVERSION__ ADC conversion group.
00601   * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid)
00602   */
00603 #define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP)         || \
00604                                                  ((__CONVERSION__) == ADC_INJECTED_GROUP)        || \
00605                                                  ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP)  )
00606
00607 /**
00608   * @brief Verify the ADC event type.
00609   * @param __EVENT__ ADC event.
00610   * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid)
00611   */
00612 #define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT)  || \
00613                                       ((__EVENT__) == ADC_AWD_EVENT)    || \
00614                                       ((__EVENT__) == ADC_AWD2_EVENT)   || \
00615                                       ((__EVENT__) == ADC_AWD3_EVENT)   || \
00616                                       ((__EVENT__) == ADC_OVR_EVENT)    || \
00617                                       ((__EVENT__) == ADC_JQOVF_EVENT)  )
00618
00619 /**
00620   * @brief Verify the ADC oversampling ratio.
00621   * @param __RATIO__ programmed ADC oversampling ratio.
00622   * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid)
00623   */
00624 #define IS_ADC_OVERSAMPLING_RATIO(__RATIO__)      (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2   ) || \
00625                                                    ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4   ) || \
00626                                                    ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8   ) || \
00627                                                    ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16  ) || \
00628                                                    ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32  ) || \
00629                                                    ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64  ) || \
00630                                                    ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \
00631                                                    ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 ))
00632
00633 /**
00634   * @brief Verify the ADC oversampling shift.
00635   * @param __SHIFT__ programmed ADC oversampling shift.
00636   * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)
00637   */
00638 #define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__)        (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \
00639                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_1   ) || \
00640                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_2   ) || \
00641                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_3   ) || \
00642                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_4   ) || \
00643                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_5   ) || \
00644                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_6   ) || \
00645                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_7   ) || \
00646                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_8   ))
00647
00648 /**
00649   * @brief Verify the ADC oversampling triggered mode.
00650   * @param __MODE__ programmed ADC oversampling triggered mode.
00651   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00652   */
00653 #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
00654                                                       ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
00655
00656 /**
00657   * @brief Verify the ADC oversampling regular conversion resumed or continued mode.
00658   * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode.
00659   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00660   */
00661 #define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \
00662                                                ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) )
00663
00664 /**
00665   * @brief Verify the DFSDM mode configuration.
00666   * @param __HANDLE__ ADC handle.
00667   * @note When DMSDFM configuration is not supported, the macro systematically reports SET. For
00668   *      this reason, the input parameter is the ADC handle and not the configuration parameter
00669   *      directly.
00670   * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid)
00671   */
00672 #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET)
00673
00674 /**
00675   * @brief Return the DFSDM configuration mode.
00676   * @param __HANDLE__ ADC handle.
00677   * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled).
00678   *       For this reason, the input parameter is the ADC handle and not the configuration parameter
00679   *       directly.
00680   * @retval DFSDM configuration mode
00681   */
00682 #define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL)
00683
00684 /**
00685   * @}
00686   */
00687
00688
00689 /* Exported functions --------------------------------------------------------*/
00690 /** @addtogroup ADCEx_Exported_Functions
00691   * @{
00692   */
00693
00694 /** @addtogroup ADCEx_Exported_Functions_Group1
00695   * @{
00696   */
00697 /* IO operation functions *****************************************************/
00698
00699 /* ADC calibration */
00700 HAL_StatusTypeDef       HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
00701 uint32_t                HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
00702 HAL_StatusTypeDef       HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff,
00703                                                        uint32_t CalibrationFactor);
00704
00705 /* Blocking mode: Polling */
00706 HAL_StatusTypeDef       HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc);
00707 HAL_StatusTypeDef       HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc);
00708 HAL_StatusTypeDef       HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
00709
00710 /* Non-blocking mode: Interruption */
00711 HAL_StatusTypeDef       HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc);
00712 HAL_StatusTypeDef       HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc);
00713
00714 /* ADC retrieve conversion value intended to be used with polling or interruption */
00715 uint32_t                HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank);
00716
00717 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
00718 void                    HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc);
00719 void                    HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc);
00720 void                    HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc);
00721 void                    HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc);
00722 void                    HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc);
00723
00724 /* ADC group regular conversions stop */
00725 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc);
00726 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc);
00727 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc);
00728 /**
00729   * @}
00730   */
00731
00732 /** @addtogroup ADCEx_Exported_Functions_Group2
00733   * @{
00734   */
00735 /* Peripheral Control functions ***********************************************/
00736 HAL_StatusTypeDef       HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,ADC_InjectionConfTypeDef* sConfigInjected);
00737 HAL_StatusTypeDef       HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc);
00738 HAL_StatusTypeDef       HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc);
00739 HAL_StatusTypeDef       HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc);
00740 HAL_StatusTypeDef       HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc);
00741
00742 /**
00743   * @}
00744   */
00745
00746 /**
00747   * @}
00748   */
00749
00750 /**
00751   * @}
00752   */
00753
00754 /**
00755   * @}
00756   */
00757
00758 #ifdef __cplusplus
00759 }
00760 #endif
00761
00762 #endif /* STM32WBxx_HAL_ADC_EX_H */
00763
00764
00765 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:33 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_comp.c Source File

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stm32wbxx_hal_comp.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_comp.c
00004   * @author  MCD Application Team
00005   * @brief   COMP HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the COMP peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + Start/Stop operation functions in polling mode
00010   *           + Start/Stop operation functions in interrupt mode (through EXTI interrupt)
00011   *           + Peripheral control functions
00012   *           + Peripheral state functions
00013   *
00014   @verbatim
00015 ================================================================================
00016           ##### COMP Peripheral features #####
00017 ================================================================================
00018
00019   [..]
00020       The STM32WBxx device family integrates two analog comparators instances:
00021       COMP1, COMP2.
00022       (#) Comparators input minus (inverting input) and input plus (non inverting input)
00023           can be set to internal references or to GPIO pins
00024           (refer to GPIO list in reference manual).
00025
00026       (#) Comparators output level is available using HAL_COMP_GetOutputLevel()
00027           and can be redirected to other peripherals: GPIO pins (in mode
00028           alternate functions for comparator), timers.
00029           (refer to GPIO list in reference manual).
00030
00031       (#) The comparators have interrupt capability through the EXTI controller
00032           with wake-up from sleep and stop modes.
00033
00034       (#) Pairs of comparators instances can be combined in window mode
00035           (2 consecutive instances odd and even COMP<x> and COMP<x+1>).
00036
00037           From the corresponding IRQ handler, the right interrupt source can be retrieved
00038           using macro __HAL_COMP_COMPx_EXTI_GET_FLAG().
00039
00040             ##### How to use this driver #####
00041 ================================================================================
00042   [..]
00043       This driver provides functions to configure and program the comparator instances
00044       of STM32WBxx devices.
00045
00046       To use the comparator, perform the following steps:
00047
00048       (#)  Initialize the COMP low level resources by implementing the HAL_COMP_MspInit():
00049       (++) Configure the GPIO connected to comparator inputs plus and minus in analog mode
00050            using HAL_GPIO_Init().
00051       (++) If needed, configure the GPIO connected to comparator output in alternate function mode
00052            using HAL_GPIO_Init().
00053       (++) If required enable the COMP interrupt by configuring and enabling EXTI line in Interrupt mode and
00054            selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator
00055            interrupt vector using HAL_NVIC_EnableIRQ() function.
00056
00057       (#) Configure the comparator using HAL_COMP_Init() function:
00058       (++) Select the input minus (inverting input)
00059       (++) Select the input plus (non-inverting input)
00060       (++) Select the hysteresis
00061       (++) Select the blanking source
00062       (++) Select the output polarity
00063       (++) Select the power mode
00064       (++) Select the window mode
00065
00066       -@@- HAL_COMP_Init() calls internally __HAL_RCC_SYSCFG_CLK_ENABLE()
00067           to enable internal control clock of the comparators.
00068           However, this is a legacy strategy. In future STM32 families,
00069           COMP clock enable must be implemented by user in "HAL_COMP_MspInit()".
00070           Therefore, for compatibility anticipation, it is recommended to
00071           implement __HAL_RCC_SYSCFG_CLK_ENABLE() in "HAL_COMP_MspInit()".
00072
00073       (#) Reconfiguration on-the-fly of comparator can be done by calling again
00074           function HAL_COMP_Init() with new input structure parameters values.
00075
00076       (#) Enable the comparator using HAL_COMP_Start() function.
00077
00078       (#) Use HAL_COMP_TriggerCallback() or HAL_COMP_GetOutputLevel() functions
00079           to manage comparator outputs (events and output level).
00080
00081       (#) Disable the comparator using HAL_COMP_Stop() function.
00082
00083       (#) De-initialize the comparator using HAL_COMP_DeInit() function.
00084
00085       (#) For safety purpose, comparator configuration can be locked using HAL_COMP_Lock() function.
00086           The only way to unlock the comparator is a device hardware reset.
00087
00088     *** Callback registration ***
00089     =============================================
00090     [..]
00091
00092      The compilation flag USE_HAL_COMP_REGISTER_CALLBACKS, when set to 1,
00093      allows the user to configure dynamically the driver callbacks.
00094      Use Functions @ref HAL_COMP_RegisterCallback()
00095      to register an interrupt callback.
00096     [..]
00097
00098      Function @ref HAL_COMP_RegisterCallback() allows to register following callbacks:
00099        (+) TriggerCallback       : callback for COMP trigger.
00100        (+) MspInitCallback       : callback for Msp Init.
00101        (+) MspDeInitCallback     : callback for Msp DeInit.
00102      This function takes as parameters the HAL peripheral handle, the Callback ID
00103      and a pointer to the user callback function.
00104     [..]
00105
00106      Use function @ref HAL_COMP_UnRegisterCallback to reset a callback to the default
00107      weak function.
00108     [..]
00109
00110      @ref HAL_COMP_UnRegisterCallback takes as parameters the HAL peripheral handle,
00111      and the Callback ID.
00112      This function allows to reset following callbacks:
00113        (+) TriggerCallback       : callback for COMP trigger.
00114        (+) MspInitCallback       : callback for Msp Init.
00115        (+) MspDeInitCallback     : callback for Msp DeInit.
00116      [..]
00117
00118      By default, after the @ref HAL_COMP_Init() and when the state is @ref HAL_COMP_STATE_RESET
00119      all callbacks are set to the corresponding weak functions:
00120      example @ref HAL_COMP_TriggerCallback().
00121      Exception done for MspInit and MspDeInit functions that are
00122      reset to the legacy weak functions in the @ref HAL_COMP_Init()/ @ref HAL_COMP_DeInit() only when
00123      these callbacks are null (not registered beforehand).
00124     [..]
00125
00126      If MspInit or MspDeInit are not null, the @ref HAL_COMP_Init()/ @ref HAL_COMP_DeInit()
00127      keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
00128      [..]
00129
00130      Callbacks can be registered/unregistered in @ref HAL_COMP_STATE_READY state only.
00131      Exception done MspInit/MspDeInit functions that can be registered/unregistered
00132      in @ref HAL_COMP_STATE_READY or @ref HAL_COMP_STATE_RESET state,
00133      thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00134     [..]
00135
00136      Then, the user first registers the MspInit/MspDeInit user callbacks
00137      using @ref HAL_COMP_RegisterCallback() before calling @ref HAL_COMP_DeInit()
00138      or @ref HAL_COMP_Init() function.
00139      [..]
00140
00141      When the compilation flag USE_HAL_COMP_REGISTER_CALLBACKS is set to 0 or
00142      not defined, the callback registration feature is not available and all callbacks
00143      are set to the corresponding weak functions.
00144
00145   @endverbatim
00146   ******************************************************************************
00147
00148   ******************************************************************************
00149   * @attention
00150   *
00151   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00152   * All rights reserved.</center></h2>
00153   *
00154   * This software component is licensed by ST under BSD 3-Clause license,
00155   * the "License"; You may not use this file except in compliance with the
00156   * License. You may obtain a copy of the License at:
00157   *                        opensource.org/licenses/BSD-3-Clause
00158   *
00159   ******************************************************************************
00160   */
00161
00162 /* Includes ------------------------------------------------------------------*/
00163 #include "stm32wbxx_hal.h"
00164
00165 /** @addtogroup STM32WBxx_HAL_Driver
00166   * @{
00167   */
00168
00169 #ifdef HAL_COMP_MODULE_ENABLED
00170
00171 #if defined (COMP1) || defined (COMP2)
00172
00173 /** @defgroup COMP COMP
00174   * @brief COMP HAL module driver
00175   * @{
00176   */
00177
00178 /* Private typedef -----------------------------------------------------------*/
00179 /* Private define ------------------------------------------------------------*/
00180 /** @addtogroup COMP_Private_Constants
00181   * @{
00182   */
00183
00184 /* Delay for COMP startup time.                                               */
00185 /* Note: Delay required to reach propagation delay specification.             */
00186 /* Literal set to maximum value (refer to device datasheet,                   */
00187 /* parameter "tSTART").                                                       */
00188 /* Unit: us                                                                   */
00189 #define COMP_DELAY_STARTUP_US          (80UL) /*!< Delay for COMP startup time */
00190
00191 /* Delay for COMP voltage scaler stabilization time.                          */
00192 /* Literal set to maximum value (refer to device datasheet,                   */
00193 /* parameter "tSTART_SCALER").                                                */
00194 /* Unit: us                                                                   */
00195 #define COMP_DELAY_VOLTAGE_SCALER_STAB_US (200UL)  /*!< Delay for COMP voltage scaler stabilization time */
00196
00197 #define COMP_OUTPUT_LEVEL_BITOFFSET_POS    (30UL)
00198
00199 /**
00200   * @}
00201   */
00202
00203 /* Private macro -------------------------------------------------------------*/
00204 /* Private variables ---------------------------------------------------------*/
00205 /* Private function prototypes -----------------------------------------------*/
00206 /* Exported functions --------------------------------------------------------*/
00207
00208 /** @defgroup COMP_Exported_Functions COMP Exported Functions
00209   * @{
00210   */
00211
00212 /** @defgroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions
00213   *  @brief    Initialization and de-initialization functions.
00214   *
00215 @verbatim
00216  ===============================================================================
00217               ##### Initialization and de-initialization functions #####
00218  ===============================================================================
00219     [..]  This section provides functions to initialize and de-initialize comparators
00220
00221 @endverbatim
00222   * @{
00223   */
00224
00225 /**
00226   * @brief  Initialize the COMP according to the specified
00227   *         parameters in the COMP_InitTypeDef and initialize the associated handle.
00228   * @note   If the selected comparator is locked, initialization can't be performed.
00229   *         To unlock the configuration, perform a system reset.
00230   * @param  hcomp  COMP handle
00231   * @retval HAL status
00232   */
00233 HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
00234 {
00235   uint32_t tmp_csr;
00236   uint32_t exti_line;
00237   uint32_t comp_voltage_scaler_initialized; /* Value "0" if comparator voltage scaler is not initialized */
00238   __IO uint32_t wait_loop_index = 0UL;
00239   HAL_StatusTypeDef status = HAL_OK;
00240
00241   /* Check the COMP handle allocation and lock status */
00242   if(hcomp == NULL)
00243   {
00244     status = HAL_ERROR;
00245   }
00246   else if(__HAL_COMP_IS_LOCKED(hcomp))
00247   {
00248     status = HAL_ERROR;
00249   }
00250   else
00251   {
00252     /* Check the parameters */
00253     assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00254     assert_param(IS_COMP_INPUT_PLUS(hcomp->Instance, hcomp->Init.InputPlus));
00255     assert_param(IS_COMP_INPUT_MINUS(hcomp->Instance, hcomp->Init.InputMinus));
00256     assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol));
00257     assert_param(IS_COMP_POWERMODE(hcomp->Init.Mode));
00258     assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis));
00259     assert_param(IS_COMP_BLANKINGSRC_INSTANCE(hcomp->Instance, hcomp->Init.BlankingSrce));
00260     assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode));
00261     assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode));
00262
00263     if(hcomp->State == HAL_COMP_STATE_RESET)
00264     {
00265       /* Allocate lock resource and initialize it */
00266       hcomp->Lock = HAL_UNLOCKED;
00267
00268       /* Set COMP error code to none */
00269       COMP_CLEAR_ERRORCODE(hcomp);
00270
00271
00272 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00273       /* Init the COMP Callback settings */
00274       hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */
00275
00276       if (hcomp->MspInitCallback == NULL)
00277       {
00278         hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit  */
00279       }
00280
00281       /* Init the low level hardware */
00282       /* Note: Internal control clock of the comparators must                 */
00283       /*       be enabled in "HAL_COMP_MspInit()"                             */
00284       /*       using "__HAL_RCC_SYSCFG_CLK_ENABLE()".                         */
00285       hcomp->MspInitCallback(hcomp);
00286 #else
00287       /* Init the low level hardware */
00288       /* Note: Internal control clock of the comparators must                 */
00289       /*       be enabled in "HAL_COMP_MspInit()"                             */
00290       /*       using "__HAL_RCC_SYSCFG_CLK_ENABLE()".                         */
00291       HAL_COMP_MspInit(hcomp);
00292 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
00293     }
00294
00295     /* Memorize voltage scaler state before initialization */
00296     comp_voltage_scaler_initialized = READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN);
00297
00298     /* Set COMP parameters */
00299     tmp_csr = (  hcomp->Init.InputMinus
00300                | hcomp->Init.InputPlus
00301                | hcomp->Init.BlankingSrce
00302                | hcomp->Init.Hysteresis
00303                | hcomp->Init.OutputPol
00304                | hcomp->Init.Mode
00305               );
00306
00307     /* Set parameters in COMP register */
00308     /* Note: Update all bits except read-only, lock and enable bits */
00309     MODIFY_REG(hcomp->Instance->CSR,
00310                COMP_CSR_PWRMODE  | COMP_CSR_INMSEL   | COMP_CSR_INPSEL  |
00311                COMP_CSR_WINMODE  | COMP_CSR_POLARITY | COMP_CSR_HYST    |
00312                COMP_CSR_BLANKING | COMP_CSR_BRGEN    | COMP_CSR_SCALEN  | COMP_CSR_INMESEL,
00313                tmp_csr
00314               );
00315
00316     /* Set window mode */
00317     /* Note: Window mode bit is located into 1 out of the 2 pairs of COMP     */
00318     /*       instances. Therefore, this function can update another COMP      */
00319     /*       instance that the one currently selected.                        */
00320     if(hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)
00321     {
00322       SET_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE);
00323     }
00324     else
00325     {
00326       CLEAR_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE);
00327     }
00328
00329     /* Delay for COMP scaler bridge voltage stabilization */
00330     /* Apply the delay if voltage scaler bridge is required and not already enabled */
00331     if ((READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN) != 0UL) &&
00332         (comp_voltage_scaler_initialized == 0UL)               )
00333     {
00334       /* Wait loop initialization and execution */
00335       /* Note: Variable divided by 2 to compensate partially              */
00336       /*       CPU processing cycles, scaling in us split to not          */
00337       /*       exceed 32 bits register capacity and handle low frequency. */
00338       wait_loop_index = ((COMP_DELAY_VOLTAGE_SCALER_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
00339       while(wait_loop_index != 0UL)
00340       {
00341         wait_loop_index--;
00342       }
00343     }
00344
00345     /* Get the EXTI line corresponding to the selected COMP instance */
00346     exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
00347
00348     /* Manage EXTI settings */
00349     if((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != 0UL)
00350     {
00351       /* Configure EXTI rising edge */
00352       if((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != 0UL)
00353       {
00354         LL_EXTI_EnableRisingTrig_0_31(exti_line);
00355       }
00356       else
00357       {
00358         LL_EXTI_DisableRisingTrig_0_31(exti_line);
00359       }
00360
00361       /* Configure EXTI falling edge */
00362       if((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != 0UL)
00363       {
00364         LL_EXTI_EnableFallingTrig_0_31(exti_line);
00365       }
00366       else
00367       {
00368         LL_EXTI_DisableFallingTrig_0_31(exti_line);
00369       }
00370
00371       /* Clear COMP EXTI pending bit (if any) */
00372       LL_EXTI_ClearFlag_0_31(exti_line);
00373
00374       /* Configure EXTI event mode */
00375       if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL)
00376       {
00377         LL_EXTI_EnableEvent_0_31(exti_line);
00378       }
00379       else
00380       {
00381         LL_EXTI_DisableEvent_0_31(exti_line);
00382       }
00383
00384       /* Configure EXTI interrupt mode */
00385       if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL)
00386       {
00387         LL_EXTI_EnableIT_0_31(exti_line);
00388       }
00389       else
00390       {
00391         LL_EXTI_DisableIT_0_31(exti_line);
00392       }
00393     }
00394     else
00395     {
00396       /* Disable EXTI event mode */
00397       LL_EXTI_DisableEvent_0_31(exti_line);
00398
00399       /* Disable EXTI interrupt mode */
00400       LL_EXTI_DisableIT_0_31(exti_line);
00401     }
00402
00403     /* Set HAL COMP handle state */
00404     /* Note: Transition from state reset to state ready,                      */
00405     /*       otherwise (coming from state ready or busy) no state update.     */
00406     if (hcomp->State == HAL_COMP_STATE_RESET)
00407     {
00408       hcomp->State = HAL_COMP_STATE_READY;
00409     }
00410   }
00411
00412   return status;
00413 }
00414
00415 /**
00416   * @brief  DeInitialize the COMP peripheral.
00417   * @note   Deinitialization cannot be performed if the COMP configuration is locked.
00418   *         To unlock the configuration, perform a system reset.
00419   * @param  hcomp  COMP handle
00420   * @retval HAL status
00421   */
00422 HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp)
00423 {
00424   HAL_StatusTypeDef status = HAL_OK;
00425
00426   /* Check the COMP handle allocation and lock status */
00427   if(hcomp == NULL)
00428   {
00429     status = HAL_ERROR;
00430   }
00431   else if(__HAL_COMP_IS_LOCKED(hcomp))
00432   {
00433     status = HAL_ERROR;
00434   }
00435   else
00436   {
00437     /* Check the parameter */
00438     assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00439
00440     /* Set COMP_CSR register to reset value */
00441     WRITE_REG(hcomp->Instance->CSR, 0x00000000UL);
00442
00443 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00444     if (hcomp->MspDeInitCallback == NULL)
00445     {
00446       hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit  */
00447     }
00448
00449     /* DeInit the low level hardware: GPIO, RCC clock, NVIC */
00450     hcomp->MspDeInitCallback(hcomp);
00451 #else
00452     /* DeInit the low level hardware: GPIO, RCC clock, NVIC */
00453     HAL_COMP_MspDeInit(hcomp);
00454 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
00455
00456     /* Set HAL COMP handle state */
00457     hcomp->State = HAL_COMP_STATE_RESET;
00458
00459     /* Release Lock */
00460     __HAL_UNLOCK(hcomp);
00461   }
00462
00463   return status;
00464 }
00465
00466 /**
00467   * @brief  Initialize the COMP MSP.
00468   * @param  hcomp  COMP handle
00469   * @retval None
00470   */
00471 __weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp)
00472 {
00473   /* Prevent unused argument(s) compilation warning */
00474   UNUSED(hcomp);
00475
00476   /* NOTE : This function should not be modified, when the callback is needed,
00477             the HAL_COMP_MspInit could be implemented in the user file
00478    */
00479 }
00480
00481 /**
00482   * @brief  DeInitialize the COMP MSP.
00483   * @param  hcomp  COMP handle
00484   * @retval None
00485   */
00486 __weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp)
00487 {
00488   /* Prevent unused argument(s) compilation warning */
00489   UNUSED(hcomp);
00490
00491   /* NOTE : This function should not be modified, when the callback is needed,
00492             the HAL_COMP_MspDeInit could be implemented in the user file
00493    */
00494 }
00495
00496 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00497 /**
00498   * @brief  Register a User COMP Callback
00499   *         To be used instead of the weak predefined callback
00500   * @param  hcomp Pointer to a COMP_HandleTypeDef structure that contains
00501   *                the configuration information for the specified COMP.
00502   * @param  CallbackID ID of the callback to be registered
00503   *         This parameter can be one of the following values:
00504   *          @arg @ref HAL_COMP_TRIGGER_CB_ID Trigger callback ID
00505   *          @arg @ref HAL_COMP_MSPINIT_CB_ID MspInit callback ID
00506   *          @arg @ref HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID
00507   * @param  pCallback pointer to the Callback function
00508   * @retval HAL status
00509   */
00510 HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback)
00511 {
00512   HAL_StatusTypeDef status = HAL_OK;
00513
00514   if (pCallback == NULL)
00515   {
00516     /* Update the error code */
00517     hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
00518
00519     return HAL_ERROR;
00520   }
00521
00522   if (HAL_COMP_STATE_READY == hcomp->State)
00523   {
00524     switch (CallbackID)
00525     {
00526       case HAL_COMP_TRIGGER_CB_ID :
00527         hcomp->TriggerCallback = pCallback;
00528         break;
00529
00530       case HAL_COMP_MSPINIT_CB_ID :
00531         hcomp->MspInitCallback = pCallback;
00532         break;
00533
00534       case HAL_COMP_MSPDEINIT_CB_ID :
00535         hcomp->MspDeInitCallback = pCallback;
00536         break;
00537
00538       default :
00539         /* Update the error code */
00540         hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
00541
00542         /* Return error status */
00543         status = HAL_ERROR;
00544         break;
00545     }
00546   }
00547   else if (HAL_COMP_STATE_RESET == hcomp->State)
00548   {
00549     switch (CallbackID)
00550     {
00551       case HAL_COMP_MSPINIT_CB_ID :
00552         hcomp->MspInitCallback = pCallback;
00553         break;
00554
00555       case HAL_COMP_MSPDEINIT_CB_ID :
00556         hcomp->MspDeInitCallback = pCallback;
00557         break;
00558
00559       default :
00560         /* Update the error code */
00561         hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
00562
00563         /* Return error status */
00564         status = HAL_ERROR;
00565         break;
00566     }
00567   }
00568   else
00569   {
00570     /* Update the error code */
00571     hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
00572
00573     /* Return error status */
00574     status =  HAL_ERROR;
00575   }
00576
00577   return status;
00578 }
00579
00580 /**
00581   * @brief  Unregister a COMP Callback
00582   *         COMP callback is redirected to the weak predefined callback
00583   * @param  hcomp Pointer to a COMP_HandleTypeDef structure that contains
00584   *                the configuration information for the specified COMP.
00585   * @param  CallbackID ID of the callback to be unregistered
00586   *         This parameter can be one of the following values:
00587   *          @arg @ref HAL_COMP_TRIGGER_CB_ID Trigger callback ID
00588   *          @arg @ref HAL_COMP_MSPINIT_CB_ID MspInit callback ID
00589   *          @arg @ref HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID
00590   * @retval HAL status
00591   */
00592 HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID)
00593 {
00594   HAL_StatusTypeDef status = HAL_OK;
00595
00596   if (HAL_COMP_STATE_READY == hcomp->State)
00597   {
00598     switch (CallbackID)
00599     {
00600       case HAL_COMP_TRIGGER_CB_ID :
00601         hcomp->TriggerCallback = HAL_COMP_TriggerCallback;         /* Legacy weak callback */
00602         break;
00603
00604       case HAL_COMP_MSPINIT_CB_ID :
00605         hcomp->MspInitCallback = HAL_COMP_MspInit;                 /* Legacy weak MspInit */
00606         break;
00607
00608       case HAL_COMP_MSPDEINIT_CB_ID :
00609         hcomp->MspDeInitCallback = HAL_COMP_MspDeInit;             /* Legacy weak MspDeInit */
00610         break;
00611
00612       default :
00613         /* Update the error code */
00614         hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
00615
00616         /* Return error status */
00617         status =  HAL_ERROR;
00618         break;
00619     }
00620   }
00621   else if (HAL_COMP_STATE_RESET == hcomp->State)
00622   {
00623     switch (CallbackID)
00624     {
00625       case HAL_COMP_MSPINIT_CB_ID :
00626         hcomp->MspInitCallback = HAL_COMP_MspInit;                 /* Legacy weak MspInit */
00627         break;
00628
00629       case HAL_COMP_MSPDEINIT_CB_ID :
00630         hcomp->MspDeInitCallback = HAL_COMP_MspDeInit;             /* Legacy weak MspDeInit */
00631         break;
00632
00633       default :
00634         /* Update the error code */
00635         hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
00636
00637         /* Return error status */
00638         status =  HAL_ERROR;
00639         break;
00640     }
00641   }
00642   else
00643   {
00644     /* Update the error code */
00645     hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
00646
00647     /* Return error status */
00648     status =  HAL_ERROR;
00649   }
00650
00651   return status;
00652 }
00653
00654 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
00655
00656 /**
00657   * @}
00658   */
00659
00660 /** @defgroup COMP_Exported_Functions_Group2 Start-Stop operation functions
00661   *  @brief   Start-Stop operation functions.
00662   *
00663 @verbatim
00664  ===============================================================================
00665                       ##### IO operation functions #####
00666  ===============================================================================
00667     [..]  This section provides functions allowing to:
00668       (+) Start a comparator instance.
00669       (+) Stop a comparator instance.
00670
00671 @endverbatim
00672   * @{
00673   */
00674
00675 /**
00676   * @brief  Start the comparator.
00677   * @param  hcomp  COMP handle
00678   * @retval HAL status
00679   */
00680 HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
00681 {
00682   __IO uint32_t wait_loop_index = 0UL;
00683   HAL_StatusTypeDef status = HAL_OK;
00684
00685   /* Check the COMP handle allocation and lock status */
00686   if(hcomp == NULL)
00687   {
00688     status = HAL_ERROR;
00689   }
00690   else if(__HAL_COMP_IS_LOCKED(hcomp))
00691   {
00692     status = HAL_ERROR;
00693   }
00694   else
00695   {
00696     /* Check the parameter */
00697     assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00698
00699     if(hcomp->State == HAL_COMP_STATE_READY)
00700     {
00701       /* Enable the selected comparator */
00702       SET_BIT(hcomp->Instance->CSR, COMP_CSR_EN);
00703
00704       /* Set HAL COMP handle state */
00705       hcomp->State = HAL_COMP_STATE_BUSY;
00706
00707       /* Delay for COMP startup time */
00708       /* Wait loop initialization and execution */
00709       /* Note: Variable divided by 2 to compensate partially              */
00710       /*       CPU processing cycles, scaling in us split to not          */
00711       /*       exceed 32 bits register capacity and handle low frequency. */
00712       wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
00713       while(wait_loop_index != 0UL)
00714       {
00715         wait_loop_index--;
00716       }
00717     }
00718     else
00719     {
00720       status = HAL_ERROR;
00721     }
00722   }
00723
00724   return status;
00725 }
00726
00727 /**
00728   * @brief  Stop the comparator.
00729   * @param  hcomp  COMP handle
00730   * @retval HAL status
00731   */
00732 HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
00733 {
00734   HAL_StatusTypeDef status = HAL_OK;
00735
00736   /* Check the COMP handle allocation and lock status */
00737   if(hcomp == NULL)
00738   {
00739     status = HAL_ERROR;
00740   }
00741   else if(__HAL_COMP_IS_LOCKED(hcomp))
00742   {
00743     status = HAL_ERROR;
00744   }
00745   else
00746   {
00747     /* Check the parameter */
00748     assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00749
00750     /* Check compliant states: HAL_COMP_STATE_READY or HAL_COMP_STATE_BUSY    */
00751     /* (all states except HAL_COMP_STATE_RESET and except locked status.      */
00752     if(hcomp->State != HAL_COMP_STATE_RESET)
00753     {
00754       /* Disable the selected comparator */
00755       CLEAR_BIT(hcomp->Instance->CSR, COMP_CSR_EN);
00756
00757       /* Set HAL COMP handle state */
00758       hcomp->State = HAL_COMP_STATE_READY;
00759     }
00760     else
00761     {
00762       status = HAL_ERROR;
00763     }
00764   }
00765
00766   return status;
00767 }
00768
00769 /**
00770   * @brief  Comparator IRQ handler.
00771   * @param  hcomp  COMP handle
00772   * @retval None
00773   */
00774 void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
00775 {
00776   /* Get the EXTI line corresponding to the selected COMP instance */
00777   uint32_t exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
00778
00779   /* Check COMP EXTI flag */
00780   if(LL_EXTI_IsActiveFlag_0_31(exti_line) != 0UL)
00781   {
00782     /* Check whether comparator is in independent or window mode */
00783     if(READ_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE) != 0UL)
00784     {
00785       /* Clear COMP EXTI line pending bit of the pair of comparators          */
00786       /* in window mode.                                                      */
00787       /* Note: Pair of comparators in window mode can both trig IRQ when      */
00788       /*       input voltage is changing from "out of window" area            */
00789       /*       (low or high ) to the other "out of window" area (high or low).*/
00790       /*       Both flags must be cleared to call comparator trigger          */
00791       /*       callback is called once.                                       */
00792       LL_EXTI_ClearFlag_0_31((COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2));
00793     }
00794     else
00795     {
00796       /* Clear COMP EXTI line pending bit */
00797       LL_EXTI_ClearFlag_0_31(exti_line);
00798     }
00799
00800     /* COMP trigger user callback */
00801 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00802     hcomp->TriggerCallback(hcomp);
00803 #else
00804     HAL_COMP_TriggerCallback(hcomp);
00805 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
00806   }
00807 }
00808
00809 /**
00810   * @}
00811   */
00812
00813 /** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions
00814   *  @brief   Management functions.
00815   *
00816 @verbatim
00817  ===============================================================================
00818                       ##### Peripheral Control functions #####
00819  ===============================================================================
00820     [..]
00821     This subsection provides a set of functions allowing to control the comparators.
00822
00823 @endverbatim
00824   * @{
00825   */
00826
00827 /**
00828   * @brief  Lock the selected comparator configuration.
00829   * @note   A system reset is required to unlock the comparator configuration.
00830   * @note   Locking the comparator from reset state is possible
00831   *         if __HAL_RCC_SYSCFG_CLK_ENABLE() is being called before.
00832   * @param  hcomp  COMP handle
00833   * @retval HAL status
00834   */
00835 HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
00836 {
00837   HAL_StatusTypeDef status = HAL_OK;
00838
00839   /* Check the COMP handle allocation and lock status */
00840   if(hcomp == NULL)
00841   {
00842     status = HAL_ERROR;
00843   }
00844   else if(__HAL_COMP_IS_LOCKED(hcomp))
00845   {
00846     status = HAL_ERROR;
00847   }
00848   else
00849   {
00850     /* Check the parameter */
00851     assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00852
00853     /* Set HAL COMP handle state */
00854     switch(hcomp->State)
00855     {
00856       case HAL_COMP_STATE_RESET:
00857         hcomp->State = HAL_COMP_STATE_RESET_LOCKED;
00858         break;
00859       case HAL_COMP_STATE_READY:
00860         hcomp->State = HAL_COMP_STATE_READY_LOCKED;
00861         break;
00862       default: /* HAL_COMP_STATE_BUSY */
00863         hcomp->State = HAL_COMP_STATE_BUSY_LOCKED;
00864         break;
00865     }
00866   }
00867
00868   if(status == HAL_OK)
00869   {
00870     /* Set the lock bit corresponding to selected comparator */
00871     __HAL_COMP_LOCK(hcomp);
00872   }
00873
00874   return status;
00875 }
00876
00877 /**
00878   * @brief  Return the output level (high or low) of the selected comparator.
00879   *         The output level depends on the selected polarity.
00880   *         If the polarity is not inverted:
00881   *           - Comparator output is low when the input plus is at a lower
00882   *             voltage than the input minus
00883   *           - Comparator output is high when the input plus is at a higher
00884   *             voltage than the input minus
00885   *         If the polarity is inverted:
00886   *           - Comparator output is high when the input plus is at a lower
00887   *             voltage than the input minus
00888   *           - Comparator output is low when the input plus is at a higher
00889   *             voltage than the input minus
00890   * @param  hcomp  COMP handle
00891   * @retval Returns the selected comparator output level:
00892   *         @arg COMP_OUTPUT_LEVEL_LOW
00893   *         @arg COMP_OUTPUT_LEVEL_HIGH
00894   *
00895   */
00896 uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp)
00897 {
00898   /* Check the parameter */
00899   assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00900
00901   return (uint32_t)(READ_BIT(hcomp->Instance->CSR, COMP_CSR_VALUE)
00902                     >> COMP_OUTPUT_LEVEL_BITOFFSET_POS);
00903 }
00904
00905 /**
00906   * @brief  Comparator trigger callback.
00907   * @param  hcomp  COMP handle
00908   * @retval None
00909   */
00910 __weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp)
00911 {
00912   /* Prevent unused argument(s) compilation warning */
00913   UNUSED(hcomp);
00914
00915   /* NOTE : This function should not be modified, when the callback is needed,
00916             the HAL_COMP_TriggerCallback should be implemented in the user file
00917    */
00918 }
00919
00920
00921 /**
00922   * @}
00923   */
00924
00925 /** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions
00926   *  @brief   Peripheral State functions.
00927   *
00928 @verbatim
00929  ===============================================================================
00930                       ##### Peripheral State functions #####
00931  ===============================================================================
00932     [..]
00933     This subsection permit to get in run-time the status of the peripheral.
00934
00935 @endverbatim
00936   * @{
00937   */
00938
00939 /**
00940   * @brief  Return the COMP handle state.
00941   * @param  hcomp  COMP handle
00942   * @retval HAL state
00943   */
00944 HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp)
00945 {
00946   /* Check the COMP handle allocation */
00947   if(hcomp == NULL)
00948   {
00949     return HAL_COMP_STATE_RESET;
00950   }
00951
00952   /* Check the parameter */
00953   assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00954
00955   /* Return HAL COMP handle state */
00956   return hcomp->State;
00957 }
00958
00959 /**
00960   * @brief  Return the COMP error code.
00961   * @param hcomp COMP handle
00962   * @retval COMP error code
00963   */
00964 uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp)
00965 {
00966   /* Check the parameters */
00967   assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
00968
00969   return hcomp->ErrorCode;
00970 }
00971
00972 /**
00973   * @}
00974   */
00975
00976 /**
00977   * @}
00978   */
00979
00980 /**
00981   * @}
00982   */
00983
00984 #endif /* COMP1 || COMP2 */
00985
00986 #endif /* HAL_COMP_MODULE_ENABLED */
00987
00988 /**
00989   * @}
00990   */
00991
00992 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:33 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_comp.h Source File

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stm32wbxx_hal_comp.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_comp.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of COMP HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_COMP_H
00022 #define STM32WBxx_HAL_COMP_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030 #include "stm32wbxx_ll_exti.h"
00031
00032 /** @addtogroup STM32WBxx_HAL_Driver
00033   * @{
00034   */
00035 #if defined (COMP1) || defined (COMP2)
00036
00037 /** @addtogroup COMP
00038   * @{
00039   */
00040
00041 /* Exported types ------------------------------------------------------------*/
00042 /** @defgroup COMP_Exported_Types COMP Exported Types
00043   * @{
00044   */
00045
00046 /**
00047   * @brief  COMP Init structure definition
00048   */
00049 typedef struct
00050 {
00051
00052   uint32_t WindowMode;         /*!< Set window mode of a pair of comparators instances
00053                                     (2 consecutive instances odd and even COMP<x> and COMP<x+1>).
00054                                     Note: HAL COMP driver allows to set window mode from any COMP instance of the pair of COMP instances composing window mode.
00055                                     This parameter can be a value of @ref COMP_WindowMode */
00056
00057   uint32_t Mode;               /*!< Set comparator operating mode to adjust power and speed.
00058                                     Note: For the characteristics of comparator power modes
00059                                           (propagation delay and power consumption), refer to device datasheet.
00060                                     This parameter can be a value of @ref COMP_PowerMode */
00061
00062   uint32_t InputPlus;          /*!< Set comparator input plus (non-inverting input).
00063                                     This parameter can be a value of @ref COMP_InputPlus */
00064
00065   uint32_t InputMinus;         /*!< Set comparator input minus (inverting input).
00066                                     This parameter can be a value of @ref COMP_InputMinus */
00067
00068   uint32_t Hysteresis;         /*!< Set comparator hysteresis mode of the input minus.
00069                                     This parameter can be a value of @ref COMP_Hysteresis */
00070
00071   uint32_t OutputPol;          /*!< Set comparator output polarity.
00072                                     This parameter can be a value of @ref COMP_OutputPolarity */
00073
00074   uint32_t BlankingSrce;       /*!< Set comparator blanking source.
00075                                     This parameter can be a value of @ref COMP_BlankingSrce */
00076
00077   uint32_t TriggerMode;        /*!< Set the comparator output triggering External Interrupt Line (EXTI).
00078                                     This parameter can be a value of @ref COMP_EXTI_TriggerMode */
00079
00080 } COMP_InitTypeDef;
00081
00082 /**
00083   * @brief  HAL COMP state machine: HAL COMP states definition
00084   */
00085 #define COMP_STATE_BITFIELD_LOCK  (0x10U)
00086 typedef enum
00087 {
00088   HAL_COMP_STATE_RESET             = 0x00U,                                             /*!< COMP not yet initialized                             */
00089   HAL_COMP_STATE_RESET_LOCKED      = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), /*!< COMP not yet initialized and configuration is locked */
00090   HAL_COMP_STATE_READY             = 0x01U,                                             /*!< COMP initialized and ready for use                   */
00091   HAL_COMP_STATE_READY_LOCKED      = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK), /*!< COMP initialized but configuration is locked         */
00092   HAL_COMP_STATE_BUSY              = 0x02U,                                             /*!< COMP is running                                      */
00093   HAL_COMP_STATE_BUSY_LOCKED       = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK)   /*!< COMP is running and configuration is locked          */
00094 } HAL_COMP_StateTypeDef;
00095
00096 /**
00097   * @brief  COMP Handle Structure definition
00098   */
00099 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00100 typedef struct __COMP_HandleTypeDef
00101 #else
00102 typedef struct
00103 #endif
00104 {
00105   COMP_TypeDef       *Instance;       /*!< Register base address    */
00106   COMP_InitTypeDef   Init;            /*!< COMP required parameters */
00107   HAL_LockTypeDef    Lock;            /*!< Locking object           */
00108   __IO HAL_COMP_StateTypeDef  State;  /*!< COMP communication state */
00109   __IO uint32_t      ErrorCode;       /*!< COMP error code */
00110 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00111   void (* TriggerCallback)(struct __COMP_HandleTypeDef *hcomp);   /*!< COMP trigger callback */
00112   void (* MspInitCallback)(struct __COMP_HandleTypeDef *hcomp);   /*!< COMP Msp Init callback */
00113   void (* MspDeInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp DeInit callback */
00114 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
00115 } COMP_HandleTypeDef;
00116
00117 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00118 /**
00119   * @brief  HAL COMP Callback ID enumeration definition
00120   */
00121 typedef enum
00122 {
00123   HAL_COMP_TRIGGER_CB_ID                = 0x00U,  /*!< COMP trigger callback ID */
00124   HAL_COMP_MSPINIT_CB_ID                = 0x01U,  /*!< COMP Msp Init callback ID */
00125   HAL_COMP_MSPDEINIT_CB_ID              = 0x02U   /*!< COMP Msp DeInit callback ID */
00126 } HAL_COMP_CallbackIDTypeDef;
00127
00128 /**
00129   * @brief  HAL COMP Callback pointer definition
00130   */
00131 typedef  void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer to a COMP callback function */
00132
00133 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
00134
00135 /**
00136   * @}
00137   */
00138
00139 /* Exported constants --------------------------------------------------------*/
00140 /** @defgroup COMP_Exported_Constants COMP Exported Constants
00141   * @{
00142   */
00143
00144 /** @defgroup COMP_Error_Code COMP Error Code
00145   * @{
00146   */
00147 #define HAL_COMP_ERROR_NONE             (0x00UL)  /*!< No error */
00148 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00149 #define HAL_COMP_ERROR_INVALID_CALLBACK (0x01UL)  /*!< Invalid Callback error */
00150 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
00151 /**
00152   * @}
00153   */
00154
00155 /** @defgroup COMP_WindowMode COMP Window Mode
00156   * @{
00157   */
00158 #define COMP_WINDOWMODE_DISABLE                 (0x00000000UL)         /*!< Window mode disable: Comparators instances pair COMP1 and COMP2 are independent */
00159 #define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE)     /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */
00160 /**
00161   * @}
00162   */
00163
00164 /** @defgroup COMP_PowerMode COMP power mode
00165   * @{
00166   */
00167 /* Note: For the characteristics of comparator power modes                    */
00168 /*       (propagation delay and power consumption),                           */
00169 /*       refer to device datasheet.                                           */
00170 #define COMP_POWERMODE_HIGHSPEED       (0x00000000UL)         /*!< High Speed */
00171 #define COMP_POWERMODE_MEDIUMSPEED     (COMP_CSR_PWRMODE_0)   /*!< Medium Speed */
00172 #define COMP_POWERMODE_ULTRALOWPOWER   (COMP_CSR_PWRMODE)     /*!< Ultra-low power mode */
00173 /**
00174   * @}
00175   */
00176
00177 /** @defgroup COMP_InputPlus COMP input plus (non-inverting input)
00178   * @{
00179   */
00180 #define COMP_INPUT_PLUS_IO1            (0x00000000UL)         /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2) */
00181 #define COMP_INPUT_PLUS_IO2            (COMP_CSR_INPSEL_0)    /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2) */
00182 #if defined(COMP_CSR_INPSEL_1)
00183 #define COMP_INPUT_PLUS_IO3            (COMP_CSR_INPSEL_1)    /*!< Comparator input plus connected to IO3 (pin PA1 for COMP1, pin PA3 for COMP2) */
00184 #endif
00185 /**
00186   * @}
00187   */
00188
00189 /** @defgroup COMP_InputMinus COMP input minus (inverting input)
00190   * @{
00191   */
00192 #define COMP_INPUT_MINUS_1_4VREFINT    (                                                            COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 1/4 VrefInt */
00193 #define COMP_INPUT_MINUS_1_2VREFINT    (                                        COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 1/2 VrefInt */
00194 #define COMP_INPUT_MINUS_3_4VREFINT    (                    COMP_CSR_INMSEL_1                     | COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 3/4 VrefInt */
00195 #define COMP_INPUT_MINUS_VREFINT       (                    COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN                 )        /*!< Comparator input minus connected to VrefInt */
00196 #define COMP_INPUT_MINUS_IO1           (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1                    )                                           /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB3 for COMP2) */
00197 #define COMP_INPUT_MINUS_IO2           (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)                                           /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PB7 for COMP2) */
00198 #define COMP_INPUT_MINUS_IO3           (                     COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO3 (pin PA0 for COMP1, pin PA2 for COMP2) */
00199 #define COMP_INPUT_MINUS_IO4           (COMP_CSR_INMESEL_1                      | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO4 (pin PA4 for COMP1, pin PA4 for COMP2) */
00200 #define COMP_INPUT_MINUS_IO5           (COMP_CSR_INMESEL_1 | COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO5 (pin PA5 for COMP1, pin PA5 for COMP2) */
00201 /**
00202   * @}
00203   */
00204
00205 /** @defgroup COMP_Hysteresis COMP hysteresis
00206   * @{
00207   */
00208 #define COMP_HYSTERESIS_NONE           (0x00000000UL)                       /*!< No hysteresis */
00209 #define COMP_HYSTERESIS_LOW            (                  COMP_CSR_HYST_0)  /*!< Hysteresis level low */
00210 #define COMP_HYSTERESIS_MEDIUM         (COMP_CSR_HYST_1                  )  /*!< Hysteresis level medium */
00211 #define COMP_HYSTERESIS_HIGH           (COMP_CSR_HYST_1 | COMP_CSR_HYST_0)  /*!< Hysteresis level high */
00212 /**
00213   * @}
00214   */
00215
00216 /** @defgroup COMP_OutputPolarity COMP output Polarity
00217   * @{
00218   */
00219 #define COMP_OUTPUTPOL_NONINVERTED     (0x00000000UL)         /*!< COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus) */
00220 #define COMP_OUTPUTPOL_INVERTED        (COMP_CSR_POLARITY)    /*!< COMP output level is inverted     (comparator output is low  when the input plus is at a higher voltage than the input minus) */
00221 /**
00222   * @}
00223   */
00224
00225 /** @defgroup COMP_BlankingSrce  COMP blanking source
00226   * @{
00227   */
00228 #define COMP_BLANKINGSRC_NONE            (0x00000000UL)          /*!<Comparator output without blanking */
00229 /* Note: Output blanking source common to all COMP instances */
00230 #define COMP_BLANKINGSRC_TIM1_OC5        (COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM1 OC5 (common to all COMP instances: COMP1, COMP2) */
00231 #define COMP_BLANKINGSRC_TIM2_OC3        (COMP_CSR_BLANKING_1)   /*!< Comparator output blanking source TIM2 OC3 (common to all COMP instances: COMP1, COMP2) */
00232 /**
00233   * @}
00234   */
00235
00236 /** @defgroup COMP_OutputLevel COMP Output Level
00237   * @{
00238   */
00239 /* Note: Comparator output level values are fixed to "0" and "1",             */
00240 /* corresponding COMP register bit is managed by HAL function to match        */
00241 /* with these values (independently of bit position in register).             */
00242
00243 /* When output polarity is not inverted, comparator output is low when
00244    the input plus is at a lower voltage than the input minus */
00245 #define COMP_OUTPUT_LEVEL_LOW              (0x00000000UL)
00246 /* When output polarity is not inverted, comparator output is high when
00247    the input plus is at a higher voltage than the input minus */
00248 #define COMP_OUTPUT_LEVEL_HIGH             (0x00000001UL)
00249 /**
00250   * @}
00251   */
00252
00253 /** @defgroup COMP_EXTI_TriggerMode COMP output to EXTI
00254   * @{
00255   */
00256 #define COMP_TRIGGERMODE_NONE                 (0x00000000UL)                                            /*!< Comparator output triggering no External Interrupt Line */
00257 #define COMP_TRIGGERMODE_IT_RISING            (COMP_EXTI_IT | COMP_EXTI_RISING)                         /*!< Comparator output triggering External Interrupt Line event with interruption, on rising edge */
00258 #define COMP_TRIGGERMODE_IT_FALLING           (COMP_EXTI_IT | COMP_EXTI_FALLING)                        /*!< Comparator output triggering External Interrupt Line event with interruption, on falling edge */
00259 #define COMP_TRIGGERMODE_IT_RISING_FALLING    (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING)     /*!< Comparator output triggering External Interrupt Line event with interruption, on both rising and falling edges */
00260 #define COMP_TRIGGERMODE_EVENT_RISING         (COMP_EXTI_EVENT | COMP_EXTI_RISING)                      /*!< Comparator output triggering External Interrupt Line event only (without interruption), on rising edge */
00261 #define COMP_TRIGGERMODE_EVENT_FALLING        (COMP_EXTI_EVENT | COMP_EXTI_FALLING)                     /*!< Comparator output triggering External Interrupt Line event only (without interruption), on falling edge */
00262 #define COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING)  /*!< Comparator output triggering External Interrupt Line event only (without interruption), on both rising and falling edges */
00263 /**
00264   * @}
00265   */
00266
00267 /**
00268   * @}
00269   */
00270
00271 /* Exported macro ------------------------------------------------------------*/
00272 /** @defgroup COMP_Exported_Macros COMP Exported Macros
00273   * @{
00274   */
00275
00276 /** @defgroup COMP_Handle_Management  COMP Handle Management
00277   * @{
00278   */
00279
00280 /** @brief  Reset COMP handle state.
00281   * @param  __HANDLE__  COMP handle
00282   * @retval None
00283   */
00284 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00285 #define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) do{                                                  \
00286                                                       (__HANDLE__)->State = HAL_COMP_STATE_RESET;      \
00287                                                       (__HANDLE__)->MspInitCallback = NULL;            \
00288                                                       (__HANDLE__)->MspDeInitCallback = NULL;          \
00289                                                     } while(0)
00290 #else
00291 #define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
00292 #endif
00293
00294 /**
00295   * @brief Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE").
00296   * @param __HANDLE__ COMP handle
00297   * @retval None
00298   */
00299 #define COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE)
00300
00301 /**
00302   * @brief  Enable the specified comparator.
00303   * @param  __HANDLE__  COMP handle
00304   * @retval None
00305   */
00306 #define __HAL_COMP_ENABLE(__HANDLE__)              SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
00307
00308 /**
00309   * @brief  Disable the specified comparator.
00310   * @param  __HANDLE__  COMP handle
00311   * @retval None
00312   */
00313 #define __HAL_COMP_DISABLE(__HANDLE__)             CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
00314
00315 /**
00316   * @brief  Lock the specified comparator configuration.
00317   * @note   Using this macro induce HAL COMP handle state machine being no
00318   *         more in line with COMP instance state.
00319   *         To keep HAL COMP handle state machine updated, it is recommended
00320   *         to use function "HAL_COMP_Lock')".
00321   * @param  __HANDLE__  COMP handle
00322   * @retval None
00323   */
00324 #define __HAL_COMP_LOCK(__HANDLE__)                SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK)
00325
00326 /**
00327   * @brief  Check whether the specified comparator is locked.
00328   * @param  __HANDLE__  COMP handle
00329   * @retval Value 0 if COMP instance is not locked, value 1 if COMP instance is locked
00330   */
00331 #define __HAL_COMP_IS_LOCKED(__HANDLE__)           (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK)
00332
00333 /**
00334   * @}
00335   */
00336
00337 /** @defgroup COMP_Exti_Management  COMP external interrupt line management
00338   * @{
00339   */
00340
00341 /**
00342   * @brief  Enable the COMP1 EXTI line rising edge trigger.
00343   * @retval None
00344   */
00345 #define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE()    LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)
00346
00347 /**
00348   * @brief  Disable the COMP1 EXTI line rising edge trigger.
00349   * @retval None
00350   */
00351 #define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE()   LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)
00352
00353 /**
00354   * @brief  Enable the COMP1 EXTI line falling edge trigger.
00355   * @retval None
00356   */
00357 #define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE()   LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)
00358
00359 /**
00360   * @brief  Disable the COMP1 EXTI line falling edge trigger.
00361   * @retval None
00362   */
00363 #define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE()  LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)
00364
00365 /**
00366   * @brief  Enable the COMP1 EXTI line rising & falling edge trigger.
00367   * @retval None
00368   */
00369 #define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE()   do { \
00370                                                                LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \
00371                                                                LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \
00372                                                              } while(0)
00373
00374 /**
00375   * @brief  Disable the COMP1 EXTI line rising & falling edge trigger.
00376   * @retval None
00377   */
00378 #define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE()  do { \
00379                                                                LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \
00380                                                                LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \
00381                                                              } while(0)
00382
00383 /**
00384   * @brief  Enable the COMP1 EXTI line in interrupt mode.
00385   * @retval None
00386   */
00387 #define __HAL_COMP_COMP1_EXTI_ENABLE_IT()             LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP1)
00388
00389 /**
00390   * @brief  Disable the COMP1 EXTI line in interrupt mode.
00391   * @retval None
00392   */
00393 #define __HAL_COMP_COMP1_EXTI_DISABLE_IT()            LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP1)
00394
00395 /**
00396   * @brief  Generate a software interrupt on the COMP1 EXTI line.
00397   * @retval None
00398   */
00399 #define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT()         LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP1)
00400
00401 /**
00402   * @brief  Enable the COMP1 EXTI line in event mode.
00403   * @retval None
00404   */
00405 #define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT()          LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP1)
00406
00407 /**
00408   * @brief  Disable the COMP1 EXTI line in event mode.
00409   * @retval None
00410   */
00411 #define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT()         LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP1)
00412
00413 /**
00414   * @brief  Check whether the COMP1 EXTI line flag is set.
00415   * @retval RESET or SET
00416   */
00417 #define __HAL_COMP_COMP1_EXTI_GET_FLAG()              LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP1)
00418
00419 /**
00420   * @brief  Clear the COMP1 EXTI flag.
00421   * @retval None
00422   */
00423 #define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG()            LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP1)
00424
00425 /**
00426   * @brief  Enable the COMP2 EXTI line rising edge trigger.
00427   * @retval None
00428   */
00429 #define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()    LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)
00430
00431 /**
00432   * @brief  Disable the COMP2 EXTI line rising edge trigger.
00433   * @retval None
00434   */
00435 #define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()   LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)
00436
00437 /**
00438   * @brief  Enable the COMP2 EXTI line falling edge trigger.
00439   * @retval None
00440   */
00441 #define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()   LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)
00442
00443 /**
00444   * @brief  Disable the COMP2 EXTI line falling edge trigger.
00445   * @retval None
00446   */
00447 #define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()  LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)
00448
00449 /**
00450   * @brief  Enable the COMP2 EXTI line rising & falling edge trigger.
00451   * @retval None
00452   */
00453 #define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE()   do { \
00454                                                                LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \
00455                                                                LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \
00456                                                              } while(0)
00457
00458 /**
00459   * @brief  Disable the COMP2 EXTI line rising & falling edge trigger.
00460   * @retval None
00461   */
00462 #define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE()  do { \
00463                                                                LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \
00464                                                                LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \
00465                                                              } while(0)
00466
00467 /**
00468   * @brief  Enable the COMP2 EXTI line in interrupt mode.
00469   * @retval None
00470   */
00471 #define __HAL_COMP_COMP2_EXTI_ENABLE_IT()             LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP2)
00472
00473 /**
00474   * @brief  Disable the COMP2 EXTI line in interrupt mode.
00475   * @retval None
00476   */
00477 #define __HAL_COMP_COMP2_EXTI_DISABLE_IT()            LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP2)
00478
00479 /**
00480   * @brief  Generate a software interrupt on the COMP2 EXTI line.
00481   * @retval None
00482   */
00483 #define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT()         LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP2)
00484
00485 /**
00486   * @brief  Enable the COMP2 EXTI line in event mode.
00487   * @retval None
00488   */
00489 #define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT()          LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP2)
00490
00491 /**
00492   * @brief  Disable the COMP2 EXTI line in event mode.
00493   * @retval None
00494   */
00495 #define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT()         LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP2)
00496
00497 /**
00498   * @brief  Check whether the COMP2 EXTI line flag is set.
00499   * @retval RESET or SET
00500   */
00501 #define __HAL_COMP_COMP2_EXTI_GET_FLAG()              LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP2)
00502
00503 /**
00504   * @brief  Clear the COMP2 EXTI flag.
00505   * @retval None
00506   */
00507 #define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()            LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP2)
00508
00509 /**
00510   * @}
00511   */
00512
00513 /**
00514   * @}
00515   */
00516
00517
00518 /* Private types -------------------------------------------------------------*/
00519 /* Private constants ---------------------------------------------------------*/
00520 /** @defgroup COMP_Private_Constants COMP Private Constants
00521   * @{
00522   */
00523
00524 /** @defgroup COMP_ExtiLine COMP EXTI Lines
00525   * @{
00526   */
00527 #define COMP_EXTI_LINE_COMP1           (LL_EXTI_LINE_20)  /*!< EXTI line 20 connected to COMP1 output */
00528 #define COMP_EXTI_LINE_COMP2           (LL_EXTI_LINE_21)  /*!< EXTI line 21 connected to COMP2 output */
00529 /**
00530   * @}
00531   */
00532
00533 /** @defgroup COMP_ExtiLine COMP EXTI Lines
00534   * @{
00535   */
00536 #define COMP_EXTI_IT                        (0x00000001UL)  /*!< EXTI line event with interruption */
00537 #define COMP_EXTI_EVENT                     (0x00000002UL)  /*!< EXTI line event only (without interruption) */
00538 #define COMP_EXTI_RISING                    (0x00000010UL)  /*!< EXTI line event on rising edge */
00539 #define COMP_EXTI_FALLING                   (0x00000020UL)  /*!< EXTI line event on falling edge */
00540 /**
00541   * @}
00542   */
00543
00544 /**
00545   * @}
00546   */
00547
00548 /* Private macros ------------------------------------------------------------*/
00549 /** @defgroup COMP_Private_Macros COMP Private Macros
00550   * @{
00551   */
00552
00553 /** @defgroup COMP_GET_EXTI_LINE COMP private macros to get EXTI line associated with comparators
00554   * @{
00555   */
00556 /**
00557   * @brief  Get the specified EXTI line for a comparator instance.
00558   * @param  __INSTANCE__  specifies the COMP instance.
00559   * @retval value of @ref COMP_ExtiLine
00560   */
00561 #define COMP_GET_EXTI_LINE(__INSTANCE__)    (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1  \
00562                                              : COMP_EXTI_LINE_COMP2)
00563 /**
00564   * @}
00565   */
00566
00567 /** @defgroup COMP_IS_COMP_Definitions COMP private macros to check input parameters
00568   * @{
00569   */
00570 #define IS_COMP_WINDOWMODE(__WINDOWMODE__)  (((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE)                || \
00571                                              ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)  )
00572
00573 #define IS_COMP_POWERMODE(__POWERMODE__)    (((__POWERMODE__) == COMP_POWERMODE_HIGHSPEED)    || \
00574                                              ((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED)  || \
00575                                              ((__POWERMODE__) == COMP_POWERMODE_ULTRALOWPOWER)  )
00576
00577 #define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \
00578                                                                ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2) || \
00579                                                                ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO3))
00580
00581 /* Note: On this STM32 serie, comparator input minus parameters are           */
00582 /*       the same on all COMP instances.                                      */
00583 /*       However, comparator instance kept as macro parameter for             */
00584 /*       compatibility with other STM32 families.                             */
00585 #define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT)  || \
00586                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT)  || \
00587                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT)  || \
00588                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT)     || \
00589                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1)         || \
00590                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2)         || \
00591                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO3)         || \
00592                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO4)         || \
00593                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO5))
00594
00595 #define IS_COMP_HYSTERESIS(__HYSTERESIS__)  (((__HYSTERESIS__) == COMP_HYSTERESIS_NONE)   || \
00596                                              ((__HYSTERESIS__) == COMP_HYSTERESIS_LOW)    || \
00597                                              ((__HYSTERESIS__) == COMP_HYSTERESIS_MEDIUM) || \
00598                                              ((__HYSTERESIS__) == COMP_HYSTERESIS_HIGH))
00599
00600 #define IS_COMP_OUTPUTPOL(__POL__)          (((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \
00601                                              ((__POL__) == COMP_OUTPUTPOL_INVERTED))
00602
00603 #define IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__)                    \
00604   (   ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)               \
00605    || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5)           \
00606    || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3)           \
00607   )
00608
00609 /* Note: Output blanking source common to all COMP instances */
00610 /*       Macro kept for compatibility with other STM32 series */
00611 #define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__)  \
00612    (IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__))
00613
00614
00615 #define IS_COMP_TRIGGERMODE(__MODE__)       (((__MODE__) == COMP_TRIGGERMODE_NONE)                 || \
00616                                              ((__MODE__) == COMP_TRIGGERMODE_IT_RISING)            || \
00617                                              ((__MODE__) == COMP_TRIGGERMODE_IT_FALLING)           || \
00618                                              ((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING)    || \
00619                                              ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING)         || \
00620                                              ((__MODE__) == COMP_TRIGGERMODE_EVENT_FALLING)        || \
00621                                              ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING))
00622
00623 #define IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__) (((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_LOW)     || \
00624                                                 ((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_HIGH))
00625
00626 /**
00627   * @}
00628   */
00629
00630 /**
00631   * @}
00632   */
00633
00634
00635 /* Exported functions --------------------------------------------------------*/
00636 /** @addtogroup COMP_Exported_Functions
00637   * @{
00638   */
00639
00640 /** @addtogroup COMP_Exported_Functions_Group1
00641   * @{
00642   */
00643
00644 /* Initialization and de-initialization functions  **********************************/
00645 HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);
00646 HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp);
00647 void              HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
00648 void              HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
00649
00650 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
00651 /* Callbacks Register/UnRegister functions  ***********************************/
00652 HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID,
00653                                             pCOMP_CallbackTypeDef pCallback);
00654 HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID);
00655 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
00656 /**
00657   * @}
00658   */
00659
00660 /* IO operation functions  *****************************************************/
00661 /** @addtogroup COMP_Exported_Functions_Group2
00662   * @{
00663   */
00664 HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp);
00665 HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp);
00666 void              HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp);
00667 /**
00668   * @}
00669   */
00670
00671 /* Peripheral Control functions  ************************************************/
00672 /** @addtogroup COMP_Exported_Functions_Group3
00673   * @{
00674   */
00675 HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp);
00676 uint32_t          HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp);
00677 /* Callback in interrupt mode */
00678 void              HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
00679 /**
00680   * @}
00681   */
00682
00683 /* Peripheral State functions  **************************************************/
00684 /** @addtogroup COMP_Exported_Functions_Group4
00685   * @{
00686   */
00687 HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
00688 uint32_t              HAL_COMP_GetError(COMP_HandleTypeDef *hcomp);
00689 /**
00690   * @}
00691   */
00692
00693 /**
00694   * @}
00695   */
00696
00697 /**
00698   * @}
00699   */
00700 #endif /* COMP1 || COMP2 */
00701 /**
00702   * @}
00703   */
00704
00705 #ifdef __cplusplus
00706 }
00707 #endif
00708
00709 #endif /* STM32WBxx_HAL_COMP_H */
00710
00711 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_conf.h Source File

  • File List
  • Globals
stm32wbxx_hal_conf.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_conf.h
00004   * @author  MCD Application Team
00005   * @brief   HAL configuration file.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_CONF_H
00022 #define STM32WBxx_HAL_CONF_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 /* Exported types ------------------------------------------------------------*/
00029 /* Exported constants --------------------------------------------------------*/
00030
00031 /* ########################## Module Selection ############################## */
00032 /**
00033   * @brief This is the list of modules to be used in the HAL driver
00034   */
00035 #define HAL_MODULE_ENABLED
00036 #define HAL_ADC_MODULE_ENABLED
00037 #define HAL_COMP_MODULE_ENABLED
00038 #define HAL_CORTEX_MODULE_ENABLED
00039 #define HAL_CRC_MODULE_ENABLED
00040 #define HAL_CRYP_MODULE_ENABLED
00041 #define HAL_DMA_MODULE_ENABLED
00042 #define HAL_EXTI_MODULE_ENABLED
00043 #define HAL_FLASH_MODULE_ENABLED
00044 #define HAL_GPIO_MODULE_ENABLED
00045 #define HAL_HSEM_MODULE_ENABLED
00046 #define HAL_I2C_MODULE_ENABLED
00047 #define HAL_IPCC_MODULE_ENABLED
00048 #define HAL_IRDA_MODULE_ENABLED
00049 #define HAL_IWDG_MODULE_ENABLED
00050 #define HAL_LCD_MODULE_ENABLED
00051 #define HAL_LPTIM_MODULE_ENABLED
00052 #define HAL_PCD_MODULE_ENABLED
00053 #define HAL_PKA_MODULE_ENABLED
00054 #define HAL_PWR_MODULE_ENABLED
00055 #define HAL_QSPI_MODULE_ENABLED
00056 #define HAL_RCC_MODULE_ENABLED
00057 #define HAL_RNG_MODULE_ENABLED
00058 #define HAL_RTC_MODULE_ENABLED
00059 #define HAL_SAI_MODULE_ENABLED
00060 #define HAL_SMARTCARD_MODULE_ENABLED
00061 #define HAL_SMBUS_MODULE_ENABLED
00062 #define HAL_SPI_MODULE_ENABLED
00063 #define HAL_TIM_MODULE_ENABLED
00064 #define HAL_TSC_MODULE_ENABLED
00065 #define HAL_UART_MODULE_ENABLED
00066 #define HAL_USART_MODULE_ENABLED
00067 #define HAL_WWDG_MODULE_ENABLED
00068
00069 #define USE_HAL_ADC_REGISTER_CALLBACKS 1u
00070 #define USE_HAL_COMP_REGISTER_CALLBACKS 1u
00071 #define USE_HAL_CRYP_REGISTER_CALLBACKS 1u
00072 #define USE_HAL_I2C_REGISTER_CALLBACKS 1u
00073 #define USE_HAL_IRDA_REGISTER_CALLBACKS 1u
00074 #define USE_HAL_LPTIM_REGISTER_CALLBACKS 1u
00075 #define USE_HAL_PCD_REGISTER_CALLBACKS 1u
00076 #define USE_HAL_PKA_REGISTER_CALLBACKS 1u
00077 #define USE_HAL_QSPI_REGISTER_CALLBACKS 1u
00078 #define USE_HAL_RNG_REGISTER_CALLBACKS 1u
00079 #define USE_HAL_RTC_REGISTER_CALLBACKS 1u
00080 #define USE_HAL_SAI_REGISTER_CALLBACKS 1u
00081 #define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 1u
00082 #define USE_HAL_SMBUS_REGISTER_CALLBACKS 1u
00083 #define USE_HAL_SPI_REGISTER_CALLBACKS 1u
00084 #define USE_HAL_TIM_REGISTER_CALLBACKS 1u
00085 #define USE_HAL_TSC_REGISTER_CALLBACKS 1u
00086 #define USE_HAL_UART_REGISTER_CALLBACKS 1u
00087 #define USE_HAL_USART_REGISTER_CALLBACKS 1u
00088 #define USE_HAL_WWDG_REGISTER_CALLBACKS 1u
00089
00090 /* ########################## Oscillator Values adaptation ####################*/
00091 /**
00092   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
00093   *        This value is used by the RCC HAL module to compute the system frequency
00094   *        (when HSE is used as system clock source, directly or through the PLL).
00095   */
00096
00097 #if !defined  (HSE_VALUE)
00098   #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
00099 #endif /* HSE_VALUE */
00100
00101 #if !defined  (HSE_STARTUP_TIMEOUT)
00102   #define HSE_STARTUP_TIMEOUT    (100UL)   /*!< Time out for HSE start up, in ms */
00103 #endif /* HSE_STARTUP_TIMEOUT */
00104
00105 /**
00106   * @brief Internal Multiple Speed oscillator (MSI) default value.
00107   *        This value is the default MSI range value after Reset.
00108   */
00109 #if !defined  (MSI_VALUE)
00110   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
00111 #endif /* MSI_VALUE */
00112
00113 /**
00114   * @brief Internal High Speed oscillator (HSI) value.
00115   *        This value is used by the RCC HAL module to compute the system frequency
00116   *        (when HSI is used as system clock source, directly or through the PLL).
00117   */
00118 #if !defined  (HSI_VALUE)
00119   #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
00120 #endif /* HSI_VALUE */
00121
00122 /**
00123   * @brief Internal Low Speed oscillator (LSI1) value.
00124   */
00125 #if !defined  (LSI1_VALUE)
00126  #define LSI1_VALUE  (32000UL)       /*!< LSI1 Typical Value in Hz*/
00127 #endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
00128                                              The real value may vary depending on the variations
00129                                              in voltage and temperature.*/
00130 /**
00131   * @brief Internal Low Speed oscillator (LSI2) value.
00132   */
00133 #if !defined  (LSI2_VALUE)
00134  #define LSI2_VALUE  (32000UL)       /*!< LSI2 Typical Value in Hz*/
00135 #endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
00136                                              The real value may vary depending on the variations
00137                                              in voltage and temperature.*/
00138
00139 /**
00140   * @brief External Low Speed oscillator (LSE) value.
00141   *        This value is used by the UART, RTC HAL module to compute the system frequency
00142   */
00143 #if !defined  (LSE_VALUE)
00144   #define LSE_VALUE    (32768UL) /*!< Value of the External oscillator in Hz*/
00145 #endif /* LSE_VALUE */
00146
00147 /**
00148   * @brief Internal Multiple Speed oscillator (HSI48) default value.
00149   *        This value is the default HSI48 range value after Reset.
00150   */
00151 #if !defined (HSI48_VALUE)
00152   #define HSI48_VALUE    (48000000UL) /*!< Value of the Internal oscillator in Hz*/
00153 #endif /* HSI48_VALUE */
00154
00155 #if !defined (LSE_STARTUP_TIMEOUT)
00156   #define LSE_STARTUP_TIMEOUT    (5000UL)   /*!< Time out for LSE start up, in ms */
00157 #endif /* LSE_STARTUP_TIMEOUT */
00158
00159 /**
00160   * @brief External clock source for SAI1 peripheral
00161   *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
00162   *        frequency.
00163   */
00164 #if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
00165   #define EXTERNAL_SAI1_CLOCK_VALUE    (48000UL) /*!< Value of the SAI1 External clock source in Hz*/
00166 #endif /* EXTERNAL_SAI1_CLOCK_VALUE */
00167
00168 /* Tip: To avoid modifying this file each time you need to use different HSE,
00169    ===  you can define the HSE value in your toolchain compiler preprocessor. */
00170
00171 /* ########################### System Configuration ######################### */
00172 /**
00173   * @brief This is the HAL system configuration section
00174   */
00175 #define  VDD_VALUE                    (3300UL) /*!< Value of VDD in mv */
00176 #define  TICK_INT_PRIORITY            ((1UL<<__NVIC_PRIO_BITS) - 1UL) /*!< tick interrupt priority (lowest by default) */
00177 #define  USE_RTOS                     0
00178 #define  PREFETCH_ENABLE              0
00179 #define  INSTRUCTION_CACHE_ENABLE     1
00180 #define  DATA_CACHE_ENABLE            1
00181
00182 /* ########################## Assert Selection ############################## */
00183 /**
00184   * @brief Uncomment the line below to expanse the "assert_param" macro in the
00185   *        HAL drivers code
00186   */
00187 /* #define USE_FULL_ASSERT    1 */
00188
00189 /* ################## SPI peripheral configuration ########################## */
00190
00191 /* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
00192  * Activated: CRC code is present inside driver
00193  * Deactivated: CRC code cleaned from driver
00194  */
00195
00196 #define USE_SPI_CRC                   1U
00197
00198 /* Includes ------------------------------------------------------------------*/
00199 /**
00200   * @brief Include module's header file
00201   */
00202 #ifdef HAL_DMA_MODULE_ENABLED
00203   #include "stm32wbxx_hal_dma.h"
00204 #endif /* HAL_DMA_MODULE_ENABLED */
00205
00206 #ifdef HAL_ADC_MODULE_ENABLED
00207   #include "stm32wbxx_hal_adc.h"
00208 #endif /* HAL_ADC_MODULE_ENABLED */
00209
00210 #ifdef HAL_COMP_MODULE_ENABLED
00211   #include "stm32wbxx_hal_comp.h"
00212 #endif /* HAL_COMP_MODULE_ENABLED */
00213
00214 #ifdef HAL_CORTEX_MODULE_ENABLED
00215   #include "stm32wbxx_hal_cortex.h"
00216 #endif /* HAL_CORTEX_MODULE_ENABLED */
00217
00218 #ifdef HAL_CRC_MODULE_ENABLED
00219   #include "stm32wbxx_hal_crc.h"
00220 #endif /* HAL_CRC_MODULE_ENABLED */
00221
00222 #ifdef HAL_CRYP_MODULE_ENABLED
00223   #include "stm32wbxx_hal_cryp.h"
00224 #endif /* HAL_CRYP_MODULE_ENABLED */
00225
00226 #ifdef HAL_EXTI_MODULE_ENABLED
00227   #include "stm32wbxx_hal_exti.h"
00228 #endif /* HAL_EXTI_MODULE_ENABLED */
00229
00230 #ifdef HAL_FLASH_MODULE_ENABLED
00231   #include "stm32wbxx_hal_flash.h"
00232 #endif /* HAL_FLASH_MODULE_ENABLED */
00233
00234 #ifdef HAL_GPIO_MODULE_ENABLED
00235   #include "stm32wbxx_hal_gpio.h"
00236 #endif /* HAL_GPIO_MODULE_ENABLED */
00237
00238 #ifdef HAL_HSEM_MODULE_ENABLED
00239   #include "stm32wbxx_hal_hsem.h"
00240 #endif /* HAL_HSEM_MODULE_ENABLED */
00241
00242 #ifdef HAL_I2C_MODULE_ENABLED
00243  #include "stm32wbxx_hal_i2c.h"
00244 #endif /* HAL_I2C_MODULE_ENABLED */
00245
00246 #ifdef HAL_IPCC_MODULE_ENABLED
00247  #include "stm32wbxx_hal_ipcc.h"
00248 #endif /* HAL_IPCC_MODULE_ENABLED */
00249
00250 #ifdef HAL_IRDA_MODULE_ENABLED
00251  #include "stm32wbxx_hal_irda.h"
00252 #endif /* HAL_IRDA_MODULE_ENABLED */
00253
00254 #ifdef HAL_IWDG_MODULE_ENABLED
00255  #include "stm32wbxx_hal_iwdg.h"
00256 #endif /* HAL_IWDG_MODULE_ENABLED */
00257
00258 #ifdef HAL_LCD_MODULE_ENABLED
00259  #include "stm32wbxx_hal_lcd.h"
00260 #endif /* HAL_LCD_MODULE_ENABLED */
00261
00262 #ifdef HAL_LPTIM_MODULE_ENABLED
00263   #include "stm32wbxx_hal_lptim.h"
00264 #endif /* HAL_LPTIM_MODULE_ENABLED */
00265
00266 #ifdef HAL_PCD_MODULE_ENABLED
00267   #include "stm32wbxx_hal_pcd.h"
00268 #endif /* HAL_PCD_MODULE_ENABLED */
00269
00270 #ifdef HAL_PKA_MODULE_ENABLED
00271   #include "stm32wbxx_hal_pka.h"
00272 #endif /* HAL_PKA_MODULE_ENABLED */
00273
00274 #ifdef HAL_PWR_MODULE_ENABLED
00275  #include "stm32wbxx_hal_pwr.h"
00276 #endif /* HAL_PWR_MODULE_ENABLED */
00277
00278 #ifdef HAL_QSPI_MODULE_ENABLED
00279  #include "stm32wbxx_hal_qspi.h"
00280 #endif /* HAL_QSPI_MODULE_ENABLED */
00281
00282 #ifdef HAL_RCC_MODULE_ENABLED
00283   #include "stm32wbxx_hal_rcc.h"
00284 #endif /* HAL_RCC_MODULE_ENABLED */
00285
00286 #ifdef HAL_RNG_MODULE_ENABLED
00287   #include "stm32wbxx_hal_rng.h"
00288 #endif /* HAL_RNG_MODULE_ENABLED */
00289
00290 #ifdef HAL_RTC_MODULE_ENABLED
00291  #include "stm32wbxx_hal_rtc.h"
00292 #endif /* HAL_RTC_MODULE_ENABLED */
00293
00294 #ifdef HAL_SAI_MODULE_ENABLED
00295  #include "stm32wbxx_hal_sai.h"
00296 #endif /* HAL_SAI_MODULE_ENABLED */
00297
00298 #ifdef HAL_SMARTCARD_MODULE_ENABLED
00299  #include "stm32wbxx_hal_smartcard.h"
00300 #endif /* HAL_SMARTCARD_MODULE_ENABLED */
00301
00302 #ifdef HAL_SMBUS_MODULE_ENABLED
00303  #include "stm32wbxx_hal_smbus.h"
00304 #endif /* HAL_SMBUS_MODULE_ENABLED */
00305
00306 #ifdef HAL_SPI_MODULE_ENABLED
00307  #include "stm32wbxx_hal_spi.h"
00308 #endif /* HAL_SPI_MODULE_ENABLED */
00309
00310 #ifdef HAL_TIM_MODULE_ENABLED
00311  #include "stm32wbxx_hal_tim.h"
00312 #endif /* HAL_TIM_MODULE_ENABLED */
00313
00314 #ifdef HAL_TSC_MODULE_ENABLED
00315   #include "stm32wbxx_hal_tsc.h"
00316 #endif /* HAL_TSC_MODULE_ENABLED */
00317
00318 #ifdef HAL_UART_MODULE_ENABLED
00319  #include "stm32wbxx_hal_uart.h"
00320 #endif /* HAL_UART_MODULE_ENABLED */
00321
00322 #ifdef HAL_USART_MODULE_ENABLED
00323  #include "stm32wbxx_hal_usart.h"
00324 #endif /* HAL_USART_MODULE_ENABLED */
00325
00326 #ifdef HAL_WWDG_MODULE_ENABLED
00327  #include "stm32wbxx_hal_wwdg.h"
00328 #endif /* HAL_WWDG_MODULE_ENABLED */
00329
00330 /* Exported macro ------------------------------------------------------------*/
00331 #ifdef  USE_FULL_ASSERT
00332 /**
00333   * @brief  The assert_param macro is used for function's parameters check.
00334   * @param expr If expr is false, it calls assert_failed function
00335   *         which reports the name of the source file and the source
00336   *         line number of the call that failed.
00337   *         If expr is true, it returns no value.
00338   * @retval None
00339   */
00340   #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
00341 /* Exported functions ------------------------------------------------------- */
00342   void assert_failed(uint8_t* file, uint32_t line);
00343 #else
00344   #define assert_param(expr) ((void)0U)
00345 #endif /* USE_FULL_ASSERT */
00346
00347 #ifdef __cplusplus
00348 }
00349 #endif
00350
00351 #endif /* STM32WBxx_HAL_CONF_H */
00352
00353 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_cortex.c Source File

  • File List
  • Globals
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  • Drivers
  • STM32WBxx_HAL_Driver
  • Src
stm32wbxx_hal_cortex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_cortex.c
00004   * @author  MCD Application Team
00005   * @brief   CORTEX HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the CORTEX:
00008   *           + Initialization and Configuration functions
00009   *           + Peripheral Control functions
00010   *
00011   @verbatim
00012   ==============================================================================
00013                         ##### How to use this driver #####
00014   ==============================================================================
00015     [..]
00016     *** How to configure Interrupts using CORTEX HAL driver ***
00017     ===========================================================
00018     [..]
00019     This section provides functions allowing to configure the NVIC interrupts (IRQ).
00020     The Cortex M0+ exceptions are managed by CMSIS functions.
00021       (#) Enable and Configure the priority of the selected IRQ Channels.
00022              The priority can be 0..3.
00023
00024         -@- Lower priority values gives higher priority.
00025         -@- Priority Order:
00026             (#@) Lowest priority.
00027             (#@) Lowest hardware priority (IRQn position).
00028
00029       (#)  Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
00030
00031       (#)  Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
00032
00033       -@-  Negative value of IRQn_Type are not allowed.
00034
00035     *** How to configure Systick using CORTEX HAL driver ***
00036     ========================================================
00037     [..]
00038     Setup SysTick Timer for time base.
00039
00040    (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
00041        is a CMSIS function that:
00042         (++) Configures the SysTick Reload register with value passed as function parameter.
00043         (++) Configures the SysTick IRQ priority to the lowest value (0x03).
00044         (++) Resets the SysTick Counter register.
00045         (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
00046         (++) Enables the SysTick Interrupt.
00047         (++) Starts the SysTick Counter.
00048
00049    (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
00050        __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
00051        HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
00052        inside the stm32wbxx_hal_cortex.h file.
00053
00054    (+) You can change the SysTick IRQ priority by calling the
00055        HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
00056        call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
00057
00058    (+) To adjust the SysTick time base, use the following formula:
00059
00060        Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
00061        (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
00062        (++) Reload Value should not exceed 0xFFFFFF
00063
00064   @endverbatim
00065   ******************************************************************************
00066   * @attention
00067   *
00068   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00069   * All rights reserved.</center></h2>
00070   *
00071   * This software component is licensed by ST under BSD 3-Clause license,
00072   * the "License"; You may not use this file except in compliance with the
00073   * License. You may obtain a copy of the License at:
00074   *                        opensource.org/licenses/BSD-3-Clause
00075   *
00076   ******************************************************************************
00077   */
00078
00079 /* Includes ------------------------------------------------------------------*/
00080 #include "stm32wbxx_hal.h"
00081
00082 /** @addtogroup STM32WBxx_HAL_Driver
00083   * @{
00084   */
00085
00086 /** @addtogroup CORTEX
00087   * @{
00088   */
00089
00090 #ifdef HAL_CORTEX_MODULE_ENABLED
00091
00092 /* Private types -------------------------------------------------------------*/
00093 /* Private variables ---------------------------------------------------------*/
00094 /* Private constants ---------------------------------------------------------*/
00095 /* Private macros ------------------------------------------------------------*/
00096 /* Private function prototypes -----------------------------------------------*/
00097 /* Exported functions --------------------------------------------------------*/
00098
00099 /** @addtogroup CORTEX_Exported_Functions
00100   * @{
00101   */
00102
00103
00104 /** @addtogroup CORTEX_Exported_Functions_Group1
00105  *  @brief    Initialization and Configuration functions
00106  *
00107 @verbatim
00108   ==============================================================================
00109               ##### Initialization and Configuration functions #####
00110   ==============================================================================
00111     [..]
00112       This section provides the CORTEX HAL driver functions allowing to configure Interrupts
00113       Systick functionalities
00114
00115 @endverbatim
00116   * @{
00117   */
00118
00119 /**
00120   * @brief  Set the priority grouping field (pre-emption priority and subpriority)
00121   *         using the required unlock sequence.
00122   * @param PriorityGroup The priority grouping bits length.
00123   *         This parameter can be one of the following values:
00124   *         @arg NVIC_PRIORITYGROUP_0: 0 bit  for pre-emption priority,
00125   *                                    4 bits for subpriority
00126   *         @arg NVIC_PRIORITYGROUP_1: 1 bit  for pre-emption priority,
00127   *                                    3 bits for subpriority
00128   *         @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
00129   *                                    2 bits for subpriority
00130   *         @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
00131   *                                    1 bit  for subpriority
00132   *         @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
00133   *                                    0 bit  for subpriority
00134   * @note   When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
00135   *         The pending IRQ priority will be managed only by the subpriority.
00136   * @retval None
00137   */
00138 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
00139 {
00140   /* Check the parameters */
00141   assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
00142
00143   /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
00144   NVIC_SetPriorityGrouping(PriorityGroup);
00145 }
00146
00147 /**
00148   * @brief  Set the priority of an interrupt.
00149   * @param IRQn External interrupt number.
00150   *         This parameter can be an enumerator of IRQn_Type enumeration
00151   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
00152   * @param PreemptPriority The pre-emption priority for the IRQn channel.
00153   *         This parameter can be a value between 0 and 15
00154   *         A lower priority value indicates a higher priority
00155   * @param SubPriority the subpriority level for the IRQ channel.
00156   *         This parameter can be a value between 0 and 15
00157   *         A lower priority value indicates a higher priority.
00158   * @retval None
00159   */
00160 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
00161 {
00162   uint32_t prioritygroup;
00163
00164   /* Check the parameters */
00165   assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
00166   assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
00167
00168   prioritygroup = NVIC_GetPriorityGrouping();
00169
00170   NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
00171 }
00172
00173 /**
00174   * @brief  Enable a device specific interrupt in the NVIC interrupt controller.
00175   * @param  IRQn External interrupt number.
00176   *         This parameter can be an enumerator of IRQn_Type enumeration
00177   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
00178   * @retval None
00179   */
00180 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
00181 {
00182   /* Check the parameters */
00183   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00184
00185   /* Enable interrupt */
00186   NVIC_EnableIRQ(IRQn);
00187 }
00188
00189 /**
00190   * @brief  Disable a device specific interrupt in the NVIC interrupt controller.
00191   * @param  IRQn External interrupt number.
00192   *         This parameter can be an enumerator of IRQn_Type enumeration
00193   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
00194   * @retval None
00195   */
00196 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
00197 {
00198   /* Check the parameters */
00199   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00200
00201   /* Disable interrupt */
00202   NVIC_DisableIRQ(IRQn);
00203 }
00204
00205 /**
00206   * @brief  Initiate a system reset request to reset the MCU.
00207   * @retval None
00208   */
00209 void HAL_NVIC_SystemReset(void)
00210 {
00211   /* System Reset */
00212   NVIC_SystemReset();
00213 }
00214
00215 /**
00216   * @brief  Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick):
00217   *         Counter is in free running mode to generate periodic interrupts.
00218   * @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
00219   * @retval status:  - 0  Function succeeded.
00220   *                  - 1  Function failed.
00221   */
00222 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
00223 {
00224    return SysTick_Config(TicksNumb);
00225 }
00226 /**
00227   * @}
00228   */
00229
00230 /** @addtogroup CORTEX_Exported_Functions_Group2
00231  *  @brief   Cortex control functions
00232  *
00233 @verbatim
00234   ==============================================================================
00235                       ##### Peripheral Control functions #####
00236   ==============================================================================
00237     [..]
00238       This subsection provides a set of functions allowing to control the CORTEX
00239       (NVIC, SYSTICK, MPU) functionalities.
00240
00241
00242 @endverbatim
00243   * @{
00244   */
00245
00246
00247 /**
00248   * @brief  Get the priority grouping field from the NVIC Interrupt Controller.
00249   * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
00250   */
00251 uint32_t HAL_NVIC_GetPriorityGrouping(void)
00252 {
00253   /* Get the PRIGROUP[10:8] field value */
00254   return NVIC_GetPriorityGrouping();
00255 }
00256
00257 /**
00258   * @brief  Get the priority of an interrupt.
00259   * @param IRQn External interrupt number.
00260   *         This parameter can be an enumerator of IRQn_Type enumeration
00261   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
00262   * @param PriorityGroup the priority grouping bits length.
00263   *         This parameter can be one of the following values:
00264   *           @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
00265   *                                      4 bits for subpriority
00266   *           @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
00267   *                                      3 bits for subpriority
00268   *           @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
00269   *                                      2 bits for subpriority
00270   *           @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
00271   *                                      1 bit for subpriority
00272   *           @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
00273   *                                      0 bit for subpriority
00274   * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
00275   * @param pSubPriority Pointer on the Subpriority value (starting from 0).
00276   * @retval None
00277   */
00278 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
00279 {
00280   /* Check the parameters */
00281   assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
00282  /* Get priority for Cortex-M system or device specific interrupts */
00283   NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
00284 }
00285
00286 /**
00287   * @brief  Set Pending bit of an external interrupt.
00288   * @param  IRQn External interrupt number
00289   *         This parameter can be an enumerator of IRQn_Type enumeration
00290   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
00291   * @retval None
00292   */
00293 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
00294 {
00295   /* Check the parameters */
00296   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00297
00298   /* Set interrupt pending */
00299   NVIC_SetPendingIRQ(IRQn);
00300 }
00301
00302 /**
00303   * @brief  Get Pending Interrupt (read the pending register in the NVIC
00304   *         and return the pending bit for the specified interrupt).
00305   * @param  IRQn External interrupt number.
00306   *         This parameter can be an enumerator of IRQn_Type enumeration
00307   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
00308   * @retval status: - 0  Interrupt status is not pending.
00309   *                 - 1  Interrupt status is pending.
00310   */
00311 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
00312 {
00313   /* Check the parameters */
00314   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00315
00316   /* Return 1 if pending else 0 */
00317   return NVIC_GetPendingIRQ(IRQn);
00318 }
00319
00320 /**
00321   * @brief  Clear the pending bit of an external interrupt.
00322   * @param  IRQn External interrupt number.
00323   *         This parameter can be an enumerator of IRQn_Type enumeration
00324   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
00325   * @retval None
00326   */
00327 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
00328 {
00329   /* Check the parameters */
00330   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00331
00332   /* Clear pending interrupt */
00333   NVIC_ClearPendingIRQ(IRQn);
00334 }
00335
00336 /**
00337   * @brief  Configure the SysTick clock source.
00338   * @param CLKSource specifies the SysTick clock source.
00339   *         This parameter can be one of the following values:
00340   *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
00341   *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
00342   * @retval None
00343   */
00344 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
00345 {
00346   /* Check the parameters */
00347   assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
00348   if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
00349   {
00350     SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
00351   }
00352   else
00353   {
00354     SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
00355   }
00356 }
00357
00358 /**
00359   * @brief  Handle SYSTICK interrupt request.
00360   * @retval None
00361   */
00362 void HAL_SYSTICK_IRQHandler(void)
00363 {
00364   HAL_SYSTICK_Callback();
00365 }
00366
00367 /**
00368   * @brief  SYSTICK callback.
00369   * @retval None
00370   */
00371 __weak void HAL_SYSTICK_Callback(void)
00372 {
00373   /* NOTE : This function should not be modified, when the callback is needed,
00374             the HAL_SYSTICK_Callback could be implemented in the user file
00375    */
00376 }
00377
00378 #if (__MPU_PRESENT == 1U)
00379 /**
00380   * @brief  Disables the MPU
00381   * @retval None
00382   */
00383 void HAL_MPU_Disable(void)
00384 {
00385   /* Make sure outstanding transfers are done */
00386   __DMB();
00387
00388   /* Disable fault exceptions */
00389   SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
00390
00391   /* Disable the MPU and clear the control register*/
00392   MPU->CTRL = 0U;
00393 }
00394
00395 /**
00396   * @brief  Enable the MPU.
00397   * @param  MPU_Control: Specifies the control mode of the MPU during hard fault,
00398   *          NMI, FAULTMASK and privileged access to the default memory
00399   *          This parameter can be one of the following values:
00400   *            @arg MPU_HFNMI_PRIVDEF_NONE
00401   *            @arg MPU_HARDFAULT_NMI
00402   *            @arg MPU_PRIVILEGED_DEFAULT
00403   *            @arg MPU_HFNMI_PRIVDEF
00404   * @retval None
00405   */
00406 void HAL_MPU_Enable(uint32_t MPU_Control)
00407 {
00408   /* Enable the MPU */
00409   MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
00410
00411   /* Enable fault exceptions */
00412   SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
00413
00414   /* Ensure MPU setting take effects */
00415   __DSB();
00416   __ISB();
00417 }
00418
00419 /**
00420   * @brief  Initialize and configure the Region and the memory to be protected.
00421   * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
00422   *                the initialization and configuration information.
00423   * @retval None
00424   */
00425 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
00426 {
00427   /* Check the parameters */
00428   assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
00429   assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
00430
00431   /* Set the Region number */
00432   MPU->RNR = MPU_Init->Number;
00433
00434   if ((MPU_Init->Enable) != 0U)
00435   {
00436     /* Check the parameters */
00437     assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
00438     assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
00439     assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
00440     assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
00441     assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
00442     assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
00443     assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
00444     assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
00445
00446     MPU->RBAR = MPU_Init->BaseAddress;
00447     MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
00448                 ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
00449                 ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
00450                 ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
00451                 ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
00452                 ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
00453                 ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
00454                 ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
00455                 ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);
00456   }
00457   else
00458   {
00459     MPU->RBAR = 0x00U;
00460     MPU->RASR = 0x00U;
00461   }
00462 }
00463 #endif /* __MPU_PRESENT */
00464
00465 /**
00466   * @}
00467   */
00468
00469 /**
00470   * @}
00471   */
00472
00473 #endif /* HAL_CORTEX_MODULE_ENABLED */
00474 /**
00475   * @}
00476   */
00477
00478 /**
00479   * @}
00480   */
00481
00482 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_cortex.h Source File

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stm32wbxx_hal_cortex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_cortex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CORTEX HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_CORTEX_H
00022 #define STM32WBxx_HAL_CORTEX_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 /** @addtogroup STM32WBxx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @defgroup CORTEX CORTEX
00036   * @brief CORTEX HAL module driver
00037   * @{
00038   */
00039
00040 /* Exported types ------------------------------------------------------------*/
00041 /** @defgroup CORTEX_Exported_Types CORTEX Exported Types
00042   * @{
00043   */
00044
00045 #if (__MPU_PRESENT == 1)
00046 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
00047   * @brief  MPU Region initialization structure
00048   * @{
00049   */
00050 typedef struct
00051 {
00052   uint8_t Enable;                /*!< Specifies the status of the region.
00053                                       This parameter can be a value of @ref CORTEX_MPU_Region_Enable                */
00054   uint8_t Number;                /*!< Specifies the number of the region to protect.
00055                                       This parameter can be a value of @ref CORTEX_MPU_Region_Number                */
00056   uint32_t BaseAddress;          /*!< Specifies the base address of the region to protect.
00057                                                                                                                     */
00058   uint8_t Size;                  /*!< Specifies the size of the region to protect.
00059                                       This parameter can be a value of @ref CORTEX_MPU_Region_Size                  */
00060   uint8_t SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable.
00061                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF   */
00062   uint8_t TypeExtField;          /*!< Specifies the TEX field level.
00063                                       This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                   */
00064   uint8_t AccessPermission;      /*!< Specifies the region access permission type.
00065                                       This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
00066   uint8_t DisableExec;           /*!< Specifies the instruction access status.
00067                                       This parameter can be a value of @ref CORTEX_MPU_Instruction_Access           */
00068   uint8_t IsShareable;           /*!< Specifies the shareability status of the protected region.
00069                                       This parameter can be a value of @ref CORTEX_MPU_Access_Shareable             */
00070   uint8_t IsCacheable;           /*!< Specifies the cacheable status of the region protected.
00071                                       This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable             */
00072   uint8_t IsBufferable;          /*!< Specifies the bufferable status of the protected region.
00073                                       This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable            */
00074 }MPU_Region_InitTypeDef;
00075 /**
00076   * @}
00077   */
00078 #endif /* __MPU_PRESENT */
00079
00080 /**
00081   * @}
00082   */
00083
00084 /* Exported constants --------------------------------------------------------*/
00085
00086 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
00087   * @{
00088   */
00089 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
00090   * @{
00091   */
00092 #define NVIC_PRIORITYGROUP_0         (0x00000007U) /*!< 0 bit  for pre-emption priority,
00093                                                         4 bits for subpriority */
00094 #define NVIC_PRIORITYGROUP_1         (0x00000006U) /*!< 1 bit  for pre-emption priority,
00095                                                         3 bits for subpriority */
00096 #define NVIC_PRIORITYGROUP_2         (0x00000005U) /*!< 2 bits for pre-emption priority,
00097                                                         2 bits for subpriority */
00098 #define NVIC_PRIORITYGROUP_3         (0x00000004U) /*!< 3 bits for pre-emption priority,
00099                                                         1 bit  for subpriority */
00100 #define NVIC_PRIORITYGROUP_4         (0x00000003U) /*!< 4 bits for pre-emption priority,
00101                                                         0 bit  for subpriority */
00102 /**
00103   * @}
00104   */
00105
00106 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
00107   * @{
00108   */
00109 #define SYSTICK_CLKSOURCE_HCLK_DIV8       0x00000000U
00110 #define SYSTICK_CLKSOURCE_HCLK            0x00000004U
00111
00112 /**
00113   * @}
00114   */
00115
00116 #if (__MPU_PRESENT == 1)
00117 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
00118   * @{
00119   */
00120 #define  MPU_HFNMI_PRIVDEF_NONE           0x00000000U
00121 #define  MPU_HARDFAULT_NMI                (MPU_CTRL_HFNMIENA_Msk)
00122 #define  MPU_PRIVILEGED_DEFAULT           (MPU_CTRL_PRIVDEFENA_Msk)
00123 #define  MPU_HFNMI_PRIVDEF                (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
00124 /**
00125   * @}
00126   */
00127
00128 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
00129   * @{
00130   */
00131 #define  MPU_REGION_ENABLE                ((uint8_t)0x01)
00132 #define  MPU_REGION_DISABLE               ((uint8_t)0x00)
00133 /**
00134   * @}
00135   */
00136
00137 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
00138   * @{
00139   */
00140 #define  MPU_INSTRUCTION_ACCESS_ENABLE    ((uint8_t)0x00)
00141 #define  MPU_INSTRUCTION_ACCESS_DISABLE   ((uint8_t)0x01)
00142 /**
00143   * @}
00144   */
00145
00146 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
00147   * @{
00148   */
00149 #define  MPU_ACCESS_SHAREABLE             ((uint8_t)0x01)
00150 #define  MPU_ACCESS_NOT_SHAREABLE         ((uint8_t)0x00)
00151 /**
00152   * @}
00153   */
00154
00155 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
00156   * @{
00157   */
00158 #define  MPU_ACCESS_CACHEABLE             ((uint8_t)0x01)
00159 #define  MPU_ACCESS_NOT_CACHEABLE         ((uint8_t)0x00)
00160 /**
00161   * @}
00162   */
00163
00164 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
00165   * @{
00166   */
00167 #define  MPU_ACCESS_BUFFERABLE            ((uint8_t)0x01)
00168 #define  MPU_ACCESS_NOT_BUFFERABLE        ((uint8_t)0x00)
00169 /**
00170   * @}
00171   */
00172
00173 /** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels
00174   * @{
00175   */
00176 #define  MPU_TEX_LEVEL0                   ((uint8_t)0x00)
00177 #define  MPU_TEX_LEVEL1                   ((uint8_t)0x01)
00178 #define  MPU_TEX_LEVEL2                   ((uint8_t)0x02)
00179 /**
00180   * @}
00181   */
00182
00183 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
00184   * @{
00185   */
00186 #define   MPU_REGION_SIZE_32B             ((uint8_t)0x04)
00187 #define   MPU_REGION_SIZE_64B             ((uint8_t)0x05)
00188 #define   MPU_REGION_SIZE_128B            ((uint8_t)0x06)
00189 #define   MPU_REGION_SIZE_256B            ((uint8_t)0x07)
00190 #define   MPU_REGION_SIZE_512B            ((uint8_t)0x08)
00191 #define   MPU_REGION_SIZE_1KB             ((uint8_t)0x09)
00192 #define   MPU_REGION_SIZE_2KB             ((uint8_t)0x0A)
00193 #define   MPU_REGION_SIZE_4KB             ((uint8_t)0x0B)
00194 #define   MPU_REGION_SIZE_8KB             ((uint8_t)0x0C)
00195 #define   MPU_REGION_SIZE_16KB            ((uint8_t)0x0D)
00196 #define   MPU_REGION_SIZE_32KB            ((uint8_t)0x0E)
00197 #define   MPU_REGION_SIZE_64KB            ((uint8_t)0x0F)
00198 #define   MPU_REGION_SIZE_128KB           ((uint8_t)0x10)
00199 #define   MPU_REGION_SIZE_256KB           ((uint8_t)0x11)
00200 #define   MPU_REGION_SIZE_512KB           ((uint8_t)0x12)
00201 #define   MPU_REGION_SIZE_1MB             ((uint8_t)0x13)
00202 #define   MPU_REGION_SIZE_2MB             ((uint8_t)0x14)
00203 #define   MPU_REGION_SIZE_4MB             ((uint8_t)0x15)
00204 #define   MPU_REGION_SIZE_8MB             ((uint8_t)0x16)
00205 #define   MPU_REGION_SIZE_16MB            ((uint8_t)0x17)
00206 #define   MPU_REGION_SIZE_32MB            ((uint8_t)0x18)
00207 #define   MPU_REGION_SIZE_64MB            ((uint8_t)0x19)
00208 #define   MPU_REGION_SIZE_128MB           ((uint8_t)0x1A)
00209 #define   MPU_REGION_SIZE_256MB           ((uint8_t)0x1B)
00210 #define   MPU_REGION_SIZE_512MB           ((uint8_t)0x1C)
00211 #define   MPU_REGION_SIZE_1GB             ((uint8_t)0x1D)
00212 #define   MPU_REGION_SIZE_2GB             ((uint8_t)0x1E)
00213 #define   MPU_REGION_SIZE_4GB             ((uint8_t)0x1F)
00214 /**
00215   * @}
00216   */
00217
00218 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
00219   * @{
00220   */
00221 #define  MPU_REGION_NO_ACCESS             ((uint8_t)0x00)
00222 #define  MPU_REGION_PRIV_RW               ((uint8_t)0x01)
00223 #define  MPU_REGION_PRIV_RW_URO           ((uint8_t)0x02)
00224 #define  MPU_REGION_FULL_ACCESS           ((uint8_t)0x03)
00225 #define  MPU_REGION_PRIV_RO               ((uint8_t)0x05)
00226 #define  MPU_REGION_PRIV_RO_URO           ((uint8_t)0x06)
00227 /**
00228   * @}
00229   */
00230
00231 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
00232   * @{
00233   */
00234 #define  MPU_REGION_NUMBER0               ((uint8_t)0x00)
00235 #define  MPU_REGION_NUMBER1               ((uint8_t)0x01)
00236 #define  MPU_REGION_NUMBER2               ((uint8_t)0x02)
00237 #define  MPU_REGION_NUMBER3               ((uint8_t)0x03)
00238 #define  MPU_REGION_NUMBER4               ((uint8_t)0x04)
00239 #define  MPU_REGION_NUMBER5               ((uint8_t)0x05)
00240 #define  MPU_REGION_NUMBER6               ((uint8_t)0x06)
00241 #define  MPU_REGION_NUMBER7               ((uint8_t)0x07)
00242 /**
00243   * @}
00244   */
00245 #endif /* __MPU_PRESENT */
00246
00247 /**
00248   * @}
00249   */
00250
00251 /* Exported macros -----------------------------------------------------------*/
00252 /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
00253   * @{
00254   */
00255
00256 /**
00257   * @}
00258   */
00259
00260 /* Exported functions --------------------------------------------------------*/
00261 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
00262   * @{
00263   */
00264
00265 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions
00266  *  @brief    Initialization and Configuration functions
00267  * @{
00268  */
00269 /* Initialization and Configuration functions *****************************/
00270 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
00271 void HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority, uint32_t SubPriority);
00272 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
00273 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
00274 void HAL_NVIC_SystemReset(void);
00275 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
00276 /**
00277   * @}
00278   */
00279
00280 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
00281  *  @brief   Cortex control functions
00282  * @{
00283  */
00284 /* Peripheral Control functions *************************************************/
00285 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
00286 uint32_t HAL_NVIC_GetPriorityGrouping(void);
00287 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
00288 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
00289 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
00290 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
00291 void HAL_SYSTICK_IRQHandler(void);
00292 void HAL_SYSTICK_Callback(void);
00293
00294 #if (__MPU_PRESENT == 1U)
00295 void HAL_MPU_Enable(uint32_t MPU_Control);
00296 void HAL_MPU_Disable(void);
00297 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
00298 #endif /* __MPU_PRESENT */
00299 /**
00300   * @}
00301   */
00302
00303 /**
00304   * @}
00305   */
00306
00307 /* Private types -------------------------------------------------------------*/
00308 /* Private variables ---------------------------------------------------------*/
00309 /* Private constants ---------------------------------------------------------*/
00310 /* Private macros ------------------------------------------------------------*/
00311 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros
00312   * @{
00313   */
00314 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
00315                                        ((GROUP) == NVIC_PRIORITYGROUP_1) || \
00316                                        ((GROUP) == NVIC_PRIORITYGROUP_2) || \
00317                                        ((GROUP) == NVIC_PRIORITYGROUP_3) || \
00318                                        ((GROUP) == NVIC_PRIORITYGROUP_4))
00319
00320 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10U)
00321
00322 #define IS_NVIC_SUB_PRIORITY(PRIORITY)         ((PRIORITY) < 0x10U)
00323
00324 #define IS_NVIC_DEVICE_IRQ(IRQ)                   ((IRQ) > SysTick_IRQn)
00325
00326 #define IS_SYSTICK_CLK_SOURCE(SOURCE)             (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
00327                                                    ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
00328
00329 #if (__MPU_PRESENT == 1)
00330 #define IS_MPU_REGION_ENABLE(STATE)               (((STATE) == MPU_REGION_ENABLE) || \
00331                                                    ((STATE) == MPU_REGION_DISABLE))
00332
00333 #define IS_MPU_INSTRUCTION_ACCESS(STATE)          (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
00334                                                    ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
00335
00336 #define IS_MPU_ACCESS_SHAREABLE(STATE)            (((STATE) == MPU_ACCESS_SHAREABLE) || \
00337                                                    ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
00338
00339 #define IS_MPU_ACCESS_CACHEABLE(STATE)            (((STATE) == MPU_ACCESS_CACHEABLE) || \
00340                                                    ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
00341
00342 #define IS_MPU_ACCESS_BUFFERABLE(STATE)           (((STATE) == MPU_ACCESS_BUFFERABLE) || \
00343                                                    ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
00344
00345 #define IS_MPU_TEX_LEVEL(TYPE)                    (((TYPE) == MPU_TEX_LEVEL0)  || \
00346                                                    ((TYPE) == MPU_TEX_LEVEL1)  || \
00347                                                    ((TYPE) == MPU_TEX_LEVEL2))
00348
00349 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE)  (((TYPE) == MPU_REGION_NO_ACCESS)   || \
00350                                                    ((TYPE) == MPU_REGION_PRIV_RW)     || \
00351                                                    ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
00352                                                    ((TYPE) == MPU_REGION_FULL_ACCESS) || \
00353                                                    ((TYPE) == MPU_REGION_PRIV_RO)     || \
00354                                                    ((TYPE) == MPU_REGION_PRIV_RO_URO))
00355
00356 #define IS_MPU_REGION_NUMBER(NUMBER)              (((NUMBER) == MPU_REGION_NUMBER0) || \
00357                                                    ((NUMBER) == MPU_REGION_NUMBER1) || \
00358                                                    ((NUMBER) == MPU_REGION_NUMBER2) || \
00359                                                    ((NUMBER) == MPU_REGION_NUMBER3) || \
00360                                                    ((NUMBER) == MPU_REGION_NUMBER4) || \
00361                                                    ((NUMBER) == MPU_REGION_NUMBER5) || \
00362                                                    ((NUMBER) == MPU_REGION_NUMBER6) || \
00363                                                    ((NUMBER) == MPU_REGION_NUMBER7))
00364
00365 #define IS_MPU_REGION_SIZE(SIZE)                  (((SIZE) == MPU_REGION_SIZE_32B)   || \
00366                                                    ((SIZE) == MPU_REGION_SIZE_64B)   || \
00367                                                    ((SIZE) == MPU_REGION_SIZE_128B)  || \
00368                                                    ((SIZE) == MPU_REGION_SIZE_256B)  || \
00369                                                    ((SIZE) == MPU_REGION_SIZE_512B)  || \
00370                                                    ((SIZE) == MPU_REGION_SIZE_1KB)   || \
00371                                                    ((SIZE) == MPU_REGION_SIZE_2KB)   || \
00372                                                    ((SIZE) == MPU_REGION_SIZE_4KB)   || \
00373                                                    ((SIZE) == MPU_REGION_SIZE_8KB)   || \
00374                                                    ((SIZE) == MPU_REGION_SIZE_16KB)  || \
00375                                                    ((SIZE) == MPU_REGION_SIZE_32KB)  || \
00376                                                    ((SIZE) == MPU_REGION_SIZE_64KB)  || \
00377                                                    ((SIZE) == MPU_REGION_SIZE_128KB) || \
00378                                                    ((SIZE) == MPU_REGION_SIZE_256KB) || \
00379                                                    ((SIZE) == MPU_REGION_SIZE_512KB) || \
00380                                                    ((SIZE) == MPU_REGION_SIZE_1MB)   || \
00381                                                    ((SIZE) == MPU_REGION_SIZE_2MB)   || \
00382                                                    ((SIZE) == MPU_REGION_SIZE_4MB)   || \
00383                                                    ((SIZE) == MPU_REGION_SIZE_8MB)   || \
00384                                                    ((SIZE) == MPU_REGION_SIZE_16MB)  || \
00385                                                    ((SIZE) == MPU_REGION_SIZE_32MB)  || \
00386                                                    ((SIZE) == MPU_REGION_SIZE_64MB)  || \
00387                                                    ((SIZE) == MPU_REGION_SIZE_128MB) || \
00388                                                    ((SIZE) == MPU_REGION_SIZE_256MB) || \
00389                                                    ((SIZE) == MPU_REGION_SIZE_512MB) || \
00390                                                    ((SIZE) == MPU_REGION_SIZE_1GB)   || \
00391                                                    ((SIZE) == MPU_REGION_SIZE_2GB)   || \
00392                                                    ((SIZE) == MPU_REGION_SIZE_4GB))
00393
00394 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION)      ((SUBREGION) < (uint16_t)0x00FFU)
00395 #endif /* __MPU_PRESENT */
00396
00397 /**
00398   * @}
00399   */
00400
00401 /* Private functions ---------------------------------------------------------*/
00402
00403 /**
00404   * @}
00405   */
00406
00407 /**
00408   * @}
00409   */
00410
00411 #ifdef __cplusplus
00412 }
00413 #endif
00414
00415 #endif /* STM32WBxx_HAL_CORTEX_H */
00416
00417
00418 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00419
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_crc.c Source File

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stm32wbxx_hal_crc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_crc.c
00004   * @author  MCD Application Team
00005   * @brief   CRC HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Cyclic Redundancy Check (CRC) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + Peripheral Control functions
00010   *           + Peripheral State functions
00011   *
00012   @verbatim
00013  ===============================================================================
00014                      ##### How to use this driver #####
00015  ===============================================================================
00016     [..]
00017          (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
00018          (+) Initialize CRC calculator
00019              (++) specify generating polynomial (peripheral default or non-default one)
00020              (++) specify initialization value (peripheral default or non-default one)
00021              (++) specify input data format
00022              (++) specify input or output data inversion mode if any
00023          (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
00024              input data buffer starting with the previously computed CRC as
00025              initialization value
00026          (+) Use HAL_CRC_Calculate() function to compute the CRC value of the
00027              input data buffer starting with the defined initialization value
00028              (default or non-default) to initiate CRC calculation
00029
00030   @endverbatim
00031   ******************************************************************************
00032   * @attention
00033   *
00034   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00035   * All rights reserved.</center></h2>
00036   *
00037   * This software component is licensed by ST under BSD 3-Clause license,
00038   * the "License"; You may not use this file except in compliance with the
00039   * License. You may obtain a copy of the License at:
00040   *                        opensource.org/licenses/BSD-3-Clause
00041   *
00042   ******************************************************************************
00043   */
00044
00045 /* Includes ------------------------------------------------------------------*/
00046 #include "stm32wbxx_hal.h"
00047
00048 /** @addtogroup STM32WBxx_HAL_Driver
00049   * @{
00050   */
00051
00052 /** @defgroup CRC CRC
00053   * @brief CRC HAL module driver.
00054   * @{
00055   */
00056
00057 #ifdef HAL_CRC_MODULE_ENABLED
00058
00059 /* Private typedef -----------------------------------------------------------*/
00060 /* Private define ------------------------------------------------------------*/
00061 /* Private macro -------------------------------------------------------------*/
00062 /* Private variables ---------------------------------------------------------*/
00063 /* Private function prototypes -----------------------------------------------*/
00064 /** @defgroup CRC_Private_Functions CRC Private Functions
00065  * @{
00066  */
00067 static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
00068 static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
00069 /**
00070   * @}
00071   */
00072
00073 /* Exported functions --------------------------------------------------------*/
00074
00075 /** @defgroup CRC_Exported_Functions CRC Exported Functions
00076   * @{
00077   */
00078
00079 /** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
00080  *  @brief    Initialization and Configuration functions.
00081  *
00082 @verbatim
00083  ===============================================================================
00084             ##### Initialization and de-initialization functions #####
00085  ===============================================================================
00086     [..]  This section provides functions allowing to:
00087       (+) Initialize the CRC according to the specified parameters
00088           in the CRC_InitTypeDef and create the associated handle
00089       (+) DeInitialize the CRC peripheral
00090       (+) Initialize the CRC MSP (MCU Specific Package)
00091       (+) DeInitialize the CRC MSP
00092
00093 @endverbatim
00094   * @{
00095   */
00096
00097 /**
00098   * @brief  Initialize the CRC according to the specified
00099   *         parameters in the CRC_InitTypeDef and create the associated handle.
00100   * @param  hcrc CRC handle
00101   * @retval HAL status
00102   */
00103 HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
00104 {
00105   /* Check the CRC handle allocation */
00106   if (hcrc == NULL)
00107   {
00108     return HAL_ERROR;
00109   }
00110
00111   /* Check the parameters */
00112   assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
00113
00114   if (hcrc->State == HAL_CRC_STATE_RESET)
00115   {
00116     /* Allocate lock resource and initialize it */
00117     hcrc->Lock = HAL_UNLOCKED;
00118     /* Init the low level hardware */
00119     HAL_CRC_MspInit(hcrc);
00120   }
00121
00122   hcrc->State = HAL_CRC_STATE_BUSY;
00123
00124   /* check whether or not non-default generating polynomial has been
00125    * picked up by user */
00126   assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
00127   if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
00128   {
00129     /* initialize peripheral with default generating polynomial */
00130     WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
00131     MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
00132   }
00133   else
00134   {
00135     /* initialize CRC peripheral with generating polynomial defined by user */
00136     if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
00137     {
00138       return HAL_ERROR;
00139     }
00140   }
00141
00142   /* check whether or not non-default CRC initial value has been
00143    * picked up by user */
00144   assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
00145   if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
00146   {
00147     WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
00148   }
00149   else
00150   {
00151     WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
00152   }
00153
00154
00155   /* set input data inversion mode */
00156   assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode));
00157   MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
00158
00159   /* set output data inversion mode */
00160   assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode));
00161   MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
00162
00163   /* makes sure the input data format (bytes, halfwords or words stream)
00164    * is properly specified by user */
00165   assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));
00166
00167   /* Change CRC peripheral state */
00168   hcrc->State = HAL_CRC_STATE_READY;
00169
00170   /* Return function status */
00171   return HAL_OK;
00172 }
00173
00174 /**
00175   * @brief  DeInitialize the CRC peripheral.
00176   * @param  hcrc CRC handle
00177   * @retval HAL status
00178   */
00179 HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
00180 {
00181   /* Check the CRC handle allocation */
00182   if (hcrc == NULL)
00183   {
00184     return HAL_ERROR;
00185   }
00186
00187   /* Check the parameters */
00188   assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
00189
00190   /* Check the CRC peripheral state */
00191   if (hcrc->State == HAL_CRC_STATE_BUSY)
00192   {
00193     return HAL_BUSY;
00194   }
00195
00196   /* Change CRC peripheral state */
00197   hcrc->State = HAL_CRC_STATE_BUSY;
00198
00199   /* Reset CRC calculation unit */
00200   __HAL_CRC_DR_RESET(hcrc);
00201
00202   /* Reset IDR register content */
00203   CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR);
00204
00205   /* DeInit the low level hardware */
00206   HAL_CRC_MspDeInit(hcrc);
00207
00208   /* Change CRC peripheral state */
00209   hcrc->State = HAL_CRC_STATE_RESET;
00210
00211   /* Process unlocked */
00212   __HAL_UNLOCK(hcrc);
00213
00214   /* Return function status */
00215   return HAL_OK;
00216 }
00217
00218 /**
00219   * @brief  Initializes the CRC MSP.
00220   * @param  hcrc CRC handle
00221   * @retval None
00222   */
00223 __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
00224 {
00225   /* Prevent unused argument(s) compilation warning */
00226   UNUSED(hcrc);
00227
00228   /* NOTE : This function should not be modified, when the callback is needed,
00229             the HAL_CRC_MspInit can be implemented in the user file
00230    */
00231 }
00232
00233 /**
00234   * @brief  DeInitialize the CRC MSP.
00235   * @param  hcrc CRC handle
00236   * @retval None
00237   */
00238 __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
00239 {
00240   /* Prevent unused argument(s) compilation warning */
00241   UNUSED(hcrc);
00242
00243   /* NOTE : This function should not be modified, when the callback is needed,
00244             the HAL_CRC_MspDeInit can be implemented in the user file
00245    */
00246 }
00247
00248 /**
00249   * @}
00250   */
00251
00252 /** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
00253  *  @brief    management functions.
00254  *
00255 @verbatim
00256  ===============================================================================
00257                       ##### Peripheral Control functions #####
00258  ===============================================================================
00259     [..]  This section provides functions allowing to:
00260       (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
00261           using combination of the previous CRC value and the new one.
00262
00263        [..]  or
00264
00265       (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
00266           independently of the previous CRC value.
00267
00268 @endverbatim
00269   * @{
00270   */
00271
00272 /**
00273   * @brief  Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
00274   *         starting with the previously computed CRC as initialization value.
00275   * @param  hcrc CRC handle
00276   * @param  pBuffer pointer to the input data buffer, exact input data format is
00277   *         provided by hcrc->InputDataFormat.
00278   * @param  BufferLength input data buffer length (number of bytes if pBuffer
00279   *         type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
00280   *         number of words if pBuffer type is * uint32_t).
00281   * @note  By default, the API expects a uint32_t pointer as input buffer parameter.
00282   *        Input buffer pointers with other types simply need to be cast in uint32_t
00283   *        and the API will internally adjust its input data processing based on the
00284   *        handle field hcrc->InputDataFormat.
00285   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
00286   */
00287 uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
00288 {
00289   uint32_t index;      /* CRC input data buffer index */
00290   uint32_t temp = 0U;  /* CRC output (read from hcrc->Instance->DR register) */
00291
00292   /* Change CRC peripheral state */
00293   hcrc->State = HAL_CRC_STATE_BUSY;
00294
00295   switch (hcrc->InputDataFormat)
00296   {
00297     case CRC_INPUTDATA_FORMAT_WORDS:
00298       /* Enter Data to the CRC calculator */
00299       for (index = 0U; index < BufferLength; index++)
00300       {
00301         hcrc->Instance->DR = pBuffer[index];
00302       }
00303       temp = hcrc->Instance->DR;
00304       break;
00305
00306     case CRC_INPUTDATA_FORMAT_BYTES:
00307       temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
00308       break;
00309
00310     case CRC_INPUTDATA_FORMAT_HALFWORDS:
00311       temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength);    /* Derogation MisraC2012 R.11.5 */
00312       break;
00313     default:
00314       break;
00315   }
00316
00317   /* Change CRC peripheral state */
00318   hcrc->State = HAL_CRC_STATE_READY;
00319
00320   /* Return the CRC computed value */
00321   return temp;
00322 }
00323
00324 /**
00325   * @brief  Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
00326   *         starting with hcrc->Instance->INIT as initialization value.
00327   * @param  hcrc CRC handle
00328   * @param  pBuffer pointer to the input data buffer, exact input data format is
00329   *         provided by hcrc->InputDataFormat.
00330   * @param  BufferLength input data buffer length (number of bytes if pBuffer
00331   *         type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
00332   *         number of words if pBuffer type is * uint32_t).
00333   * @note  By default, the API expects a uint32_t pointer as input buffer parameter.
00334   *        Input buffer pointers with other types simply need to be cast in uint32_t
00335   *        and the API will internally adjust its input data processing based on the
00336   *        handle field hcrc->InputDataFormat.
00337   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
00338   */
00339 uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
00340 {
00341   uint32_t index;      /* CRC input data buffer index */
00342   uint32_t temp = 0U;  /* CRC output (read from hcrc->Instance->DR register) */
00343
00344   /* Change CRC peripheral state */
00345   hcrc->State = HAL_CRC_STATE_BUSY;
00346
00347   /* Reset CRC Calculation Unit (hcrc->Instance->INIT is
00348   *  written in hcrc->Instance->DR) */
00349   __HAL_CRC_DR_RESET(hcrc);
00350
00351   switch (hcrc->InputDataFormat)
00352   {
00353     case CRC_INPUTDATA_FORMAT_WORDS:
00354       /* Enter 32-bit input data to the CRC calculator */
00355       for (index = 0U; index < BufferLength; index++)
00356       {
00357         hcrc->Instance->DR = pBuffer[index];
00358       }
00359       temp = hcrc->Instance->DR;
00360       break;
00361
00362     case CRC_INPUTDATA_FORMAT_BYTES:
00363       /* Specific 8-bit input data handling  */
00364       temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
00365       break;
00366
00367     case CRC_INPUTDATA_FORMAT_HALFWORDS:
00368       /* Specific 16-bit input data handling  */
00369       temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength);    /* Derogation MisraC2012 R.11.5 */
00370       break;
00371
00372     default:
00373       break;
00374   }
00375
00376   /* Change CRC peripheral state */
00377   hcrc->State = HAL_CRC_STATE_READY;
00378
00379   /* Return the CRC computed value */
00380   return temp;
00381 }
00382
00383 /**
00384   * @}
00385   */
00386
00387 /** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
00388  *  @brief    Peripheral State functions.
00389  *
00390 @verbatim
00391  ===============================================================================
00392                       ##### Peripheral State functions #####
00393  ===============================================================================
00394     [..]
00395     This subsection permits to get in run-time the status of the peripheral.
00396
00397 @endverbatim
00398   * @{
00399   */
00400
00401 /**
00402   * @brief  Return the CRC handle state.
00403   * @param  hcrc CRC handle
00404   * @retval HAL state
00405   */
00406 HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
00407 {
00408   /* Return CRC handle state */
00409   return hcrc->State;
00410 }
00411
00412 /**
00413   * @}
00414   */
00415
00416 /**
00417   * @}
00418   */
00419
00420 /** @addtogroup CRC_Private_Functions
00421  * @{
00422  */
00423
00424 /**
00425   * @brief  Enter 8-bit input data to the CRC calculator.
00426   *         Specific data handling to optimize processing time.
00427   * @param  hcrc CRC handle
00428   * @param  pBuffer pointer to the input data buffer
00429   * @param  BufferLength input data buffer length
00430   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
00431   */
00432 static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
00433 {
00434   uint32_t i; /* input data buffer index */
00435   uint16_t data;
00436   __IO uint16_t *pReg;
00437
00438   /* Processing time optimization: 4 bytes are entered in a row with a single word write,
00439    * last bytes must be carefully fed to the CRC calculator to ensure a correct type
00440    * handling by the peripheral */
00441   for (i = 0U; i < (BufferLength / 4U); i++)
00442   {
00443     hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \
00444                          ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \
00445                          ((uint32_t)pBuffer[(4U * i) + 2U] << 8U)  | \
00446                          (uint32_t)pBuffer[(4U * i) + 3U];
00447   }
00448   /* last bytes specific handling */
00449   if ((BufferLength % 4U) != 0U)
00450   {
00451     if ((BufferLength % 4U) == 1U)
00452     {
00453       *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i];         /* Derogation MisraC2012 R.11.5 */
00454     }
00455     if ((BufferLength % 4U) == 2U)
00456     {
00457       data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
00458       pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR);                    /* Derogation MisraC2012 R.11.5 */
00459       *pReg = data;
00460     }
00461     if ((BufferLength % 4U) == 3U)
00462     {
00463       data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
00464       pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR);                    /* Derogation MisraC2012 R.11.5 */
00465       *pReg = data;
00466
00467       *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U];  /* Derogation MisraC2012 R.11.5 */
00468     }
00469   }
00470
00471   /* Return the CRC computed value */
00472   return hcrc->Instance->DR;
00473 }
00474
00475 /**
00476   * @brief  Enter 16-bit input data to the CRC calculator.
00477   *         Specific data handling to optimize processing time.
00478   * @param  hcrc CRC handle
00479   * @param  pBuffer pointer to the input data buffer
00480   * @param  BufferLength input data buffer length
00481   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
00482   */
00483 static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
00484 {
00485   uint32_t i;  /* input data buffer index */
00486   __IO uint16_t *pReg;
00487
00488   /* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
00489    * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
00490    * a correct type handling by the peripheral */
00491   for (i = 0U; i < (BufferLength / 2U); i++)
00492   {
00493     hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U];
00494   }
00495   if ((BufferLength % 2U) != 0U)
00496   {
00497     pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR);                 /* Derogation MisraC2012 R.11.5 */
00498     *pReg = pBuffer[2U * i];
00499   }
00500
00501   /* Return the CRC computed value */
00502   return hcrc->Instance->DR;
00503 }
00504
00505 /**
00506   * @}
00507   */
00508
00509 #endif /* HAL_CRC_MODULE_ENABLED */
00510 /**
00511   * @}
00512   */
00513
00514 /**
00515   * @}
00516   */
00517
00518 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_crc.h Source File

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stm32wbxx_hal_crc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_crc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CRC HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_CRC_H
00022 #define STM32WBxx_HAL_CRC_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 /** @addtogroup STM32WBxx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup CRC
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup CRC_Exported_Types CRC Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief  CRC HAL State Structure definition
00046   */
00047 typedef enum
00048 {
00049   HAL_CRC_STATE_RESET     = 0x00U,  /*!< CRC not yet initialized or disabled */
00050   HAL_CRC_STATE_READY     = 0x01U,  /*!< CRC initialized and ready for use   */
00051   HAL_CRC_STATE_BUSY      = 0x02U,  /*!< CRC internal process is ongoing     */
00052   HAL_CRC_STATE_TIMEOUT   = 0x03U,  /*!< CRC timeout state                   */
00053   HAL_CRC_STATE_ERROR     = 0x04U   /*!< CRC error state                     */
00054 } HAL_CRC_StateTypeDef;
00055
00056 /**
00057   * @brief CRC Init Structure definition
00058   */
00059 typedef struct
00060 {
00061   uint8_t DefaultPolynomialUse;       /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
00062                                             If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
00063                                             X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1.
00064                                             In that case, there is no need to set GeneratingPolynomial field.
00065                                             If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set. */
00066
00067   uint8_t DefaultInitValueUse;        /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
00068                                            If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
00069                                            0xFFFFFFFF value. In that case, there is no need to set InitValue field.
00070                                            If otherwise set to DEFAULT_INIT_VALUE_DISABLE,  InitValue field must be set. */
00071
00072   uint32_t GeneratingPolynomial;      /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree
00073                                            respectively equal to 7, 8, 16 or 32. This field is written in normal representation,
00074                                            e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65.
00075                                            No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE.   */
00076
00077   uint32_t CRCLength;                 /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
00078                                            Value can be either one of
00079                                            @arg @ref CRC_POLYLENGTH_32B                  (32-bit CRC),
00080                                            @arg @ref CRC_POLYLENGTH_16B                  (16-bit CRC),
00081                                            @arg @ref CRC_POLYLENGTH_8B                   (8-bit CRC),
00082                                            @arg @ref CRC_POLYLENGTH_7B                   (7-bit CRC). */
00083
00084   uint32_t InitValue;                 /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
00085                                            is set to DEFAULT_INIT_VALUE_ENABLE.   */
00086
00087   uint32_t InputDataInversionMode;    /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
00088                                            Can be either one of the following values
00089                                            @arg @ref CRC_INPUTDATA_INVERSION_NONE       no input data inversion
00090                                            @arg @ref CRC_INPUTDATA_INVERSION_BYTE       byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
00091                                            @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD   halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
00092                                            @arg @ref CRC_INPUTDATA_INVERSION_WORD       word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */
00093
00094   uint32_t OutputDataInversionMode;   /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
00095                                             Can be either
00096                                             @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE   no CRC inversion,
00097                                             @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE    CRC 0x11223344 is converted into 0x22CC4488 */
00098 } CRC_InitTypeDef;
00099
00100 /**
00101   * @brief  CRC Handle Structure definition
00102   */
00103 typedef struct
00104 {
00105   CRC_TypeDef                 *Instance;   /*!< Register base address        */
00106
00107   CRC_InitTypeDef             Init;        /*!< CRC configuration parameters */
00108
00109   HAL_LockTypeDef             Lock;        /*!< CRC Locking object           */
00110
00111   __IO HAL_CRC_StateTypeDef   State;       /*!< CRC communication state      */
00112
00113   uint32_t InputDataFormat;                /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
00114                                             Can be either
00115                                             @arg @ref CRC_INPUTDATA_FORMAT_BYTES       input data is a stream of bytes (8-bit data)
00116                                             @arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS   input data is a stream of half-words (16-bit data)
00117                                             @arg @ref CRC_INPUTDATA_FORMAT_WORDS       input data is a stream of words (32-bit data)
00118
00119                                            Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error
00120                                            must occur if InputBufferFormat is not one of the three values listed above  */
00121 } CRC_HandleTypeDef;
00122 /**
00123   * @}
00124   */
00125
00126 /* Exported constants --------------------------------------------------------*/
00127 /** @defgroup CRC_Exported_Constants CRC Exported Constants
00128   * @{
00129   */
00130
00131 /** @defgroup CRC_Default_Polynomial_Value    Default CRC generating polynomial
00132   * @{
00133   */
00134 #define DEFAULT_CRC32_POLY      0x04C11DB7U  /*!<  X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */
00135 /**
00136   * @}
00137   */
00138
00139 /** @defgroup CRC_Default_InitValue    Default CRC computation initialization value
00140   * @{
00141   */
00142 #define DEFAULT_CRC_INITVALUE   0xFFFFFFFFU  /*!< Initial CRC default value */
00143 /**
00144   * @}
00145   */
00146
00147 /** @defgroup CRC_Default_Polynomial    Indicates whether or not default polynomial is used
00148   * @{
00149   */
00150 #define DEFAULT_POLYNOMIAL_ENABLE       ((uint8_t)0x00U)  /*!< Enable default generating polynomial 0x04C11DB7  */
00151 #define DEFAULT_POLYNOMIAL_DISABLE      ((uint8_t)0x01U)  /*!< Disable default generating polynomial 0x04C11DB7 */
00152 /**
00153   * @}
00154   */
00155
00156 /** @defgroup CRC_Default_InitValue_Use    Indicates whether or not default init value is used
00157   * @{
00158   */
00159 #define DEFAULT_INIT_VALUE_ENABLE      ((uint8_t)0x00U) /*!< Enable initial CRC default value  */
00160 #define DEFAULT_INIT_VALUE_DISABLE     ((uint8_t)0x01U) /*!< Disable initial CRC default value */
00161 /**
00162   * @}
00163   */
00164
00165 /** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the peripheral
00166   * @{
00167   */
00168 #define CRC_POLYLENGTH_32B                  0x00000000U        /*!< Resort to a 32-bit long generating polynomial */
00169 #define CRC_POLYLENGTH_16B                  CRC_CR_POLYSIZE_0  /*!< Resort to a 16-bit long generating polynomial */
00170 #define CRC_POLYLENGTH_8B                   CRC_CR_POLYSIZE_1  /*!< Resort to a 8-bit long generating polynomial  */
00171 #define CRC_POLYLENGTH_7B                   CRC_CR_POLYSIZE    /*!< Resort to a 7-bit long generating polynomial  */
00172 /**
00173   * @}
00174   */
00175
00176 /** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
00177   * @{
00178   */
00179 #define HAL_CRC_LENGTH_32B     32U          /*!< 32-bit long CRC */
00180 #define HAL_CRC_LENGTH_16B     16U          /*!< 16-bit long CRC */
00181 #define HAL_CRC_LENGTH_8B       8U          /*!< 8-bit long CRC  */
00182 #define HAL_CRC_LENGTH_7B       7U          /*!< 7-bit long CRC  */
00183 /**
00184   * @}
00185   */
00186
00187 /** @defgroup CRC_Input_Buffer_Format Input Buffer Format
00188   * @{
00189   */
00190 /* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
00191  * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
00192  * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
00193  * the CRC APIs to provide a correct result */
00194 #define CRC_INPUTDATA_FORMAT_UNDEFINED             0x00000000U  /*!< Undefined input data format    */
00195 #define CRC_INPUTDATA_FORMAT_BYTES                 0x00000001U  /*!< Input data in byte format      */
00196 #define CRC_INPUTDATA_FORMAT_HALFWORDS             0x00000002U  /*!< Input data in half-word format */
00197 #define CRC_INPUTDATA_FORMAT_WORDS                 0x00000003U  /*!< Input data in word format      */
00198 /**
00199   * @}
00200   */
00201
00202 /** @defgroup CRC_Aliases CRC API aliases
00203   * @{
00204   */
00205 #define HAL_CRC_Input_Data_Reverse   HAL_CRCEx_Input_Data_Reverse    /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility  */
00206 #define HAL_CRC_Output_Data_Reverse  HAL_CRCEx_Output_Data_Reverse   /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
00207 /**
00208   * @}
00209   */
00210
00211 /**
00212   * @}
00213   */
00214
00215 /* Exported macros -----------------------------------------------------------*/
00216 /** @defgroup CRC_Exported_Macros CRC Exported Macros
00217   * @{
00218   */
00219
00220 /** @brief Reset CRC handle state.
00221   * @param  __HANDLE__ CRC handle.
00222   * @retval None
00223   */
00224 #define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
00225
00226 /**
00227   * @brief  Reset CRC Data Register.
00228   * @param  __HANDLE__ CRC handle
00229   * @retval None
00230   */
00231 #define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
00232
00233 /**
00234   * @brief  Set CRC INIT non-default value
00235   * @param  __HANDLE__ CRC handle
00236   * @param  __INIT__ 32-bit initial value
00237   * @retval None
00238   */
00239 #define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
00240
00241 /**
00242   * @brief Store data in the Independent Data (ID) register.
00243   * @param __HANDLE__ CRC handle
00244   * @param __VALUE__  Value to be stored in the ID register
00245   * @note  Refer to the Reference Manual to get the authorized __VALUE__ length in bits
00246   * @retval None
00247   */
00248 #define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
00249
00250 /**
00251   * @brief Return the data stored in the Independent Data (ID) register.
00252   * @param __HANDLE__ CRC handle
00253   * @note  Refer to the Reference Manual to get the authorized __VALUE__ length in bits
00254   * @retval Value of the ID register
00255   */
00256 #define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
00257 /**
00258   * @}
00259   */
00260
00261
00262 /* Private macros --------------------------------------------------------*/
00263 /** @defgroup  CRC_Private_Macros CRC Private Macros
00264   * @{
00265   */
00266
00267 #define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
00268                                         ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
00269
00270
00271 #define IS_DEFAULT_INIT_VALUE(VALUE)  (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
00272                                        ((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
00273
00274 #define IS_CRC_POL_LENGTH(LENGTH)     (((LENGTH) == CRC_POLYLENGTH_32B) || \
00275                                        ((LENGTH) == CRC_POLYLENGTH_16B) || \
00276                                        ((LENGTH) == CRC_POLYLENGTH_8B)  || \
00277                                        ((LENGTH) == CRC_POLYLENGTH_7B))
00278
00279 #define IS_CRC_INPUTDATA_FORMAT(FORMAT)           (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES)     || \
00280                                                    ((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
00281                                                    ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))
00282
00283 /**
00284   * @}
00285   */
00286
00287 /* Include CRC HAL Extended module */
00288 #include "stm32wbxx_hal_crc_ex.h"
00289
00290 /* Exported functions --------------------------------------------------------*/
00291 /** @defgroup CRC_Exported_Functions CRC Exported Functions
00292   * @{
00293   */
00294
00295 /* Initialization and de-initialization functions  ****************************/
00296 /** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
00297   * @{
00298   */
00299 HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
00300 HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc);
00301 void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
00302 void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
00303 /**
00304   * @}
00305   */
00306
00307 /* Peripheral Control functions ***********************************************/
00308 /** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
00309   * @{
00310   */
00311 uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
00312 uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
00313 /**
00314   * @}
00315   */
00316
00317 /* Peripheral State and Error functions ***************************************/
00318 /** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
00319   * @{
00320   */
00321 HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
00322 /**
00323   * @}
00324   */
00325
00326 /**
00327   * @}
00328   */
00329
00330 /**
00331   * @}
00332   */
00333
00334 /**
00335   * @}
00336   */
00337
00338 #ifdef __cplusplus
00339 }
00340 #endif
00341
00342 #endif /* STM32WBxx_HAL_CRC_H */
00343
00344 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_crc_ex.c Source File

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stm32wbxx_hal_crc_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_crc_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended CRC HAL module driver.
00006   *          This file provides firmware functions to manage the extended
00007   *          functionalities of the CRC peripheral.
00008   *
00009   @verbatim
00010 ================================================================================
00011             ##### How to use this driver #####
00012 ================================================================================
00013     [..]
00014          (+) Set user-defined generating polynomial thru HAL_CRCEx_Polynomial_Set()
00015          (+) Configure Input or Output data inversion
00016
00017   @endverbatim
00018   ******************************************************************************
00019   * @attention
00020   *
00021   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00022   * All rights reserved.</center></h2>
00023   *
00024   * This software component is licensed by ST under BSD 3-Clause license,
00025   * the "License"; You may not use this file except in compliance with the
00026   * License. You may obtain a copy of the License at:
00027   *                        opensource.org/licenses/BSD-3-Clause
00028   *
00029   ******************************************************************************
00030   */
00031
00032 /* Includes ------------------------------------------------------------------*/
00033 #include "stm32wbxx_hal.h"
00034
00035 /** @addtogroup STM32WBxx_HAL_Driver
00036   * @{
00037   */
00038
00039 /** @defgroup CRCEx CRCEx
00040   * @brief CRC Extended HAL module driver
00041   * @{
00042   */
00043
00044 #ifdef HAL_CRC_MODULE_ENABLED
00045
00046 /* Private typedef -----------------------------------------------------------*/
00047 /* Private define ------------------------------------------------------------*/
00048 /* Private macro -------------------------------------------------------------*/
00049 /* Private variables ---------------------------------------------------------*/
00050 /* Private function prototypes -----------------------------------------------*/
00051 /* Exported functions --------------------------------------------------------*/
00052
00053 /** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions
00054   * @{
00055   */
00056
00057 /** @defgroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions
00058   * @brief    Extended Initialization and Configuration functions.
00059   *
00060 @verbatim
00061  ===============================================================================
00062             ##### Extended configuration functions #####
00063  ===============================================================================
00064     [..]  This section provides functions allowing to:
00065       (+) Configure the generating polynomial
00066       (+) Configure the input data inversion
00067       (+) Configure the output data inversion
00068
00069 @endverbatim
00070   * @{
00071   */
00072
00073
00074 /**
00075   * @brief  Initialize the CRC polynomial if different from default one.
00076   * @param  hcrc CRC handle
00077   * @param  Pol CRC generating polynomial (7, 8, 16 or 32-bit long).
00078   *         This parameter is written in normal representation, e.g.
00079   *         @arg for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
00080   *         @arg for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
00081   * @param  PolyLength CRC polynomial length.
00082   *         This parameter can be one of the following values:
00083   *          @arg @ref CRC_POLYLENGTH_7B  7-bit long CRC (generating polynomial of degree 7)
00084   *          @arg @ref CRC_POLYLENGTH_8B  8-bit long CRC (generating polynomial of degree 8)
00085   *          @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16)
00086   *          @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32)
00087   * @retval HAL status
00088   */
00089 HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
00090 {
00091   HAL_StatusTypeDef status = HAL_OK;
00092   uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */
00093
00094   /* Check the parameters */
00095   assert_param(IS_CRC_POL_LENGTH(PolyLength));
00096
00097   /* check polynomial definition vs polynomial size:
00098    * polynomial length must be aligned with polynomial
00099    * definition. HAL_ERROR is reported if Pol degree is
00100    * larger than that indicated by PolyLength.
00101    * Look for MSB position: msb will contain the degree of
00102    *  the second to the largest polynomial member. E.g., for
00103    *  X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
00104   while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
00105   {
00106   }
00107
00108   switch (PolyLength)
00109   {
00110     case CRC_POLYLENGTH_7B:
00111       if (msb >= HAL_CRC_LENGTH_7B)
00112       {
00113         status =   HAL_ERROR;
00114       }
00115       break;
00116     case CRC_POLYLENGTH_8B:
00117       if (msb >= HAL_CRC_LENGTH_8B)
00118       {
00119         status =   HAL_ERROR;
00120       }
00121       break;
00122     case CRC_POLYLENGTH_16B:
00123       if (msb >= HAL_CRC_LENGTH_16B)
00124       {
00125         status =   HAL_ERROR;
00126       }
00127       break;
00128
00129     case CRC_POLYLENGTH_32B:
00130       /* no polynomial definition vs. polynomial length issue possible */
00131       break;
00132     default:
00133       status =  HAL_ERROR;
00134       break;
00135   }
00136   if (status == HAL_OK)
00137   {
00138     /* set generating polynomial */
00139     WRITE_REG(hcrc->Instance->POL, Pol);
00140
00141     /* set generating polynomial size */
00142     MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
00143   }
00144   /* Return function status */
00145   return status;
00146 }
00147
00148 /**
00149   * @brief  Set the Reverse Input data mode.
00150   * @param  hcrc CRC handle
00151   * @param  InputReverseMode Input Data inversion mode.
00152   *         This parameter can be one of the following values:
00153   *          @arg @ref CRC_INPUTDATA_INVERSION_NONE     no change in bit order (default value)
00154   *          @arg @ref CRC_INPUTDATA_INVERSION_BYTE     Byte-wise bit reversal
00155   *          @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD HalfWord-wise bit reversal
00156   *          @arg @ref CRC_INPUTDATA_INVERSION_WORD     Word-wise bit reversal
00157   * @retval HAL status
00158   */
00159 HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
00160 {
00161   /* Check the parameters */
00162   assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode));
00163
00164   /* Change CRC peripheral state */
00165   hcrc->State = HAL_CRC_STATE_BUSY;
00166
00167   /* set input data inversion mode */
00168   MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode);
00169   /* Change CRC peripheral state */
00170   hcrc->State = HAL_CRC_STATE_READY;
00171
00172   /* Return function status */
00173   return HAL_OK;
00174 }
00175
00176 /**
00177   * @brief  Set the Reverse Output data mode.
00178   * @param  hcrc CRC handle
00179   * @param  OutputReverseMode Output Data inversion mode.
00180   *         This parameter can be one of the following values:
00181   *          @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion (default value)
00182   *          @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE  bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD)
00183   * @retval HAL status
00184   */
00185 HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
00186 {
00187   /* Check the parameters */
00188   assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode));
00189
00190   /* Change CRC peripheral state */
00191   hcrc->State = HAL_CRC_STATE_BUSY;
00192
00193   /* set output data inversion mode */
00194   MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode);
00195
00196   /* Change CRC peripheral state */
00197   hcrc->State = HAL_CRC_STATE_READY;
00198
00199   /* Return function status */
00200   return HAL_OK;
00201 }
00202
00203
00204
00205
00206 /**
00207   * @}
00208   */
00209
00210
00211 /**
00212   * @}
00213   */
00214
00215
00216 #endif /* HAL_CRC_MODULE_ENABLED */
00217 /**
00218   * @}
00219   */
00220
00221 /**
00222   * @}
00223   */
00224
00225 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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STM32WB55xx HAL User Manual: stm32wbxx_hal_crc_ex.h Source File

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stm32wbxx_hal_crc_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_crc_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CRC HAL extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_CRC_EX_H
00022 #define STM32WBxx_HAL_CRC_EX_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 /** @addtogroup STM32WBxx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup CRCEx
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /* Exported constants --------------------------------------------------------*/
00041 /** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants
00042   * @{
00043   */
00044
00045 /** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes
00046   * @{
00047   */
00048 #define CRC_INPUTDATA_INVERSION_NONE               0x00000000U     /*!< No input data inversion            */
00049 #define CRC_INPUTDATA_INVERSION_BYTE               CRC_CR_REV_IN_0 /*!< Byte-wise input data inversion     */
00050 #define CRC_INPUTDATA_INVERSION_HALFWORD           CRC_CR_REV_IN_1 /*!< HalfWord-wise input data inversion */
00051 #define CRC_INPUTDATA_INVERSION_WORD               CRC_CR_REV_IN   /*!< Word-wise input data inversion     */
00052 /**
00053   * @}
00054   */
00055
00056 /** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes
00057   * @{
00058   */
00059 #define CRC_OUTPUTDATA_INVERSION_DISABLE         0x00000000U       /*!< No output data inversion       */
00060 #define CRC_OUTPUTDATA_INVERSION_ENABLE          CRC_CR_REV_OUT    /*!< Bit-wise output data inversion */
00061 /**
00062   * @}
00063   */
00064
00065 /**
00066   * @}
00067   */
00068
00069 /* Exported macro ------------------------------------------------------------*/
00070 /** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros
00071   * @{
00072   */
00073
00074 /**
00075   * @brief  Set CRC output reversal
00076   * @param  __HANDLE__ CRC handle
00077   * @retval None
00078   */
00079 #define  __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
00080
00081 /**
00082   * @brief  Unset CRC output reversal
00083   * @param  __HANDLE__ CRC handle
00084   * @retval None
00085   */
00086 #define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
00087
00088 /**
00089   * @brief  Set CRC non-default polynomial
00090   * @param  __HANDLE__ CRC handle
00091   * @param  __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial
00092   * @retval None
00093   */
00094 #define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
00095
00096 /**
00097   * @}
00098   */
00099
00100 /* Private macros --------------------------------------------------------*/
00101 /** @defgroup CRCEx_Private_Macros CRC Extended Private Macros
00102   * @{
00103   */
00104
00105 #define IS_CRC_INPUTDATA_INVERSION_MODE(MODE)     (((MODE) == CRC_INPUTDATA_INVERSION_NONE)     || \
00106                                                    ((MODE) == CRC_INPUTDATA_INVERSION_BYTE)     || \
00107                                                    ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
00108                                                    ((MODE) == CRC_INPUTDATA_INVERSION_WORD))
00109
00110 #define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE)    (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
00111                                                    ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))
00112
00113 /**
00114   * @}
00115   */
00116
00117 /* Exported functions --------------------------------------------------------*/
00118
00119 /** @addtogroup CRCEx_Exported_Functions
00120   * @{
00121   */
00122
00123 /** @addtogroup CRCEx_Exported_Functions_Group1
00124   * @{
00125   */
00126 /* Initialization and de-initialization functions  ****************************/
00127 HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
00128 HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
00129 HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
00130
00131 /**
00132   * @}
00133   */
00134
00135 /**
00136   * @}
00137   */
00138
00139 /**
00140   * @}
00141   */
00142
00143 /**
00144   * @}
00145   */
00146
00147 #ifdef __cplusplus
00148 }
00149 #endif
00150
00151 #endif /* STM32WBxx_HAL_CRC_EX_H */
00152
00153 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_cryp.c Source File

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stm32wbxx_hal_cryp.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_cryp.c
00004   * @author  MCD Application Team
00005   * @brief   CRYP HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Cryptography (CRYP) peripheral:
00008   *           + Initialization, de-initialization, set config and get config  functions
00009   *           + DES/TDES, AES processing functions
00010   *           + DMA callback functions
00011   *           + CRYP IRQ handler management
00012   *           + Peripheral State functions
00013   *
00014   @verbatim
00015   ==============================================================================
00016                      ##### How to use this driver #####
00017   ==============================================================================
00018     [..]
00019       The CRYP HAL driver can be used in CRYP or TinyAES peripheral as follows:
00020
00021       (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
00022          (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()or __HAL_RCC_AES_CLK_ENABLE for TinyAES peripheral
00023          (##) In case of using interrupts (e.g. HAL_CRYP_Encrypt_IT())
00024              (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
00025              (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
00026              (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
00027          (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_Encrypt_DMA())
00028              (+++) Enable the DMAx interface clock using __RCC_DMAx_CLK_ENABLE()
00029              (+++) Configure and enable two DMA streams one for managing data transfer from
00030                  memory to peripheral (input stream) and another stream for managing data
00031                  transfer from peripheral to memory (output stream)
00032              (+++) Associate the initialized DMA handle to the CRYP DMA handle
00033                  using  __HAL_LINKDMA()
00034              (+++) Configure the priority and enable the NVIC for the transfer complete
00035                  interrupt on the two DMA Streams. The output stream should have higher
00036                  priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
00037
00038       (#)Initialize the CRYP according to the specified parameters :
00039          (##) The data type: 1-bit, 8-bit, 16-bit or 32-bit.
00040          (##) The key size: 128, 192 or 256.
00041          (##) The AlgoMode DES/ TDES Algorithm ECB/CBC or AES Algorithm ECB/CBC/CTR/GCM or CCM.
00042          (##) The initialization vector (counter). It is not used in ECB mode.
00043          (##) The key buffer used for encryption/decryption.
00044              (+++) In some specific configurations, the key is written by the application
00045                    code out of the HAL scope. In that case, user can still resort to the
00046                    HAL APIs as usual but must make sure that pKey pointer is set to NULL.
00047          (##) The Header used only in AES GCM and CCM Algorithm for authentication.
00048          (##) The HeaderSize The size of header buffer in word.
00049          (##) The B0 block is the first authentication block used only  in AES CCM mode.
00050
00051       (#)Three processing (encryption/decryption) functions are available:
00052          (##) Polling mode: encryption and decryption APIs are blocking functions
00053               i.e. they process the data and wait till the processing is finished,
00054               e.g. HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
00055          (##) Interrupt mode: encryption and decryption APIs are not blocking functions
00056               i.e. they process the data under interrupt,
00057               e.g. HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
00058          (##) DMA mode: encryption and decryption APIs are not blocking functions
00059               i.e. the data transfer is ensured by DMA,
00060               e.g. HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
00061
00062       (#)When the processing function is called at first time after HAL_CRYP_Init()
00063          the CRYP peripheral is configured and processes the buffer in input.
00064          At second call, no need to Initialize the CRYP, user have to get current configuration via
00065          HAL_CRYP_GetConfig() API, then only  HAL_CRYP_SetConfig() is requested to set
00066          new parametres, finally user can  start encryption/decryption.
00067
00068        (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
00069
00070        (#)To process a single message with consecutive calls to HAL_CRYP_Encrypt() or HAL_CRYP_Decrypt()
00071           without having to configure again the Key or the Initialization Vector between each API call,
00072           the field KeyIVConfigSkip of the initialization structure must be set to CRYP_KEYIVCONFIG_ONCE.
00073           Same is true for consecutive calls of HAL_CRYP_Encrypt_IT(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt_DMA()
00074           or HAL_CRYP_Decrypt_DMA().
00075
00076     [..]
00077       The cryptographic processor supports following standards:
00078       (#) The data encryption standard (DES) and Triple-DES (TDES) supported only by CRYP1 peripheral:
00079          (##)64-bit data block processing
00080          (##) chaining modes supported :
00081              (+++)  Electronic Code Book(ECB)
00082              (+++)  Cipher Block Chaining (CBC)
00083          (##) keys length supported :64-bit, 128-bit and 192-bit.
00084       (#) The advanced encryption standard (AES) supported  by CRYP1 & TinyAES peripheral:
00085          (##)128-bit data block processing
00086          (##) chaining modes supported :
00087              (+++)  Electronic Code Book(ECB)
00088              (+++)  Cipher Block Chaining (CBC)
00089              (+++)  Counter mode (CTR)
00090              (+++)  Galois/counter mode (GCM/GMAC)
00091              (+++)  Counter with Cipher Block Chaining-Message(CCM)
00092          (##) keys length Supported :
00093              (+++) for CRYP1 peripheral: 128-bit, 192-bit and 256-bit.
00094              (+++) for TinyAES peripheral:  128-bit and 256-bit
00095
00096     [..]
00097     (@) Specific care must be taken to format the key and the Initialization Vector IV!
00098
00099     [..] If the key is defined as a 128-bit long array key[127..0] = {b127 ... b0} where
00100          b127 is the MSB and b0 the LSB, the key must be stored in MCU memory
00101          (+) as a sequence of words where the MSB word comes first (occupies the
00102            lowest memory address)
00103           (++)   address n+0 : 0b b127 .. b120 b119 .. b112 b111 .. b104 b103 .. b96
00104           (++)   address n+4 : 0b b95 .. b88 b87 .. b80 b79 .. b72 b71 .. b64
00105           (++)   address n+8 : 0b b63 .. b56 b55 .. b48 b47 .. b40 b39 .. b32
00106           (++)   address n+C : 0b b31 .. b24 b23 .. b16 b15 .. b8 b7 .. b0
00107      [..] Hereafter, another illustration when considering a 128-bit long key made of 16 bytes {B15..B0}.
00108          The 4 32-bit words that make the key must be stored as follows in MCU memory:
00109           (+)    address n+0 : 0x B15 B14 B13 B12
00110           (+)    address n+4 : 0x B11 B10 B9 B8
00111           (+)    address n+8 : 0x B7 B6 B5 B4
00112           (+)    address n+C : 0x B3 B2 B1 B0
00113      [..]  which leads to the expected setting
00114        (+)       AES_KEYR3 = 0x B15 B14 B13 B12
00115        (+)       AES_KEYR2 = 0x B11 B10 B9 B8
00116        (+)       AES_KEYR1 = 0x B7 B6 B5 B4
00117        (+)       AES_KEYR0 = 0x B3 B2 B1 B0
00118
00119     [..]  Same format must be applied for a 256-bit long key made of 32 bytes {B31..B0}.
00120           The 8 32-bit words that make the key must be stored as follows in MCU memory:
00121           (+)    address n+00 : 0x B31 B30 B29 B28
00122           (+)    address n+04 : 0x B27 B26 B25 B24
00123           (+)    address n+08 : 0x B23 B22 B21 B20
00124           (+)    address n+0C : 0x B19 B18 B17 B16
00125           (+)    address n+10 : 0x B15 B14 B13 B12
00126           (+)    address n+14 : 0x B11 B10 B9 B8
00127           (+)    address n+18 : 0x B7 B6 B5 B4
00128           (+)    address n+1C : 0x B3 B2 B1 B0
00129      [..]  which leads to the expected setting
00130        (+)       AES_KEYR7 = 0x B31 B30 B29 B28
00131        (+)       AES_KEYR6 = 0x B27 B26 B25 B24
00132        (+)       AES_KEYR5 = 0x B23 B22 B21 B20
00133        (+)       AES_KEYR4 = 0x B19 B18 B17 B16
00134        (+)       AES_KEYR3 = 0x B15 B14 B13 B12
00135        (+)       AES_KEYR2 = 0x B11 B10 B9 B8
00136        (+)       AES_KEYR1 = 0x B7 B6 B5 B4
00137        (+)       AES_KEYR0 = 0x B3 B2 B1 B0
00138
00139     [..] Initialization Vector IV (4 32-bit words) format must follow the same as
00140          that of a 128-bit long key.
00141
00142     [..] Note that key and IV registers are not sensitive to swap mode selection.
00143
00144     [..]  This section describes the AES Galois/counter mode (GCM) supported by both CRYP1 and TinyAES peripherals:
00145       (#)  Algorithm supported :
00146          (##) Galois/counter mode (GCM)
00147          (##) Galois message authentication code (GMAC) :is exactly the same as
00148               GCM algorithm composed only by an header.
00149       (#)  Four phases are performed in GCM :
00150          (##) Init phase: peripheral prepares the GCM hash subkey (H) and do the IV processing
00151          (##) Header phase: peripheral processes the Additional Authenticated Data (AAD), with hash
00152           computation only.
00153          (##) Payload phase: peripheral processes the plaintext (P) with hash computation + keystream
00154           encryption + data XORing. It works in a similar way for ciphertext (C).
00155          (##) Final phase: peripheral generates the authenticated tag (T) using the last block of data.
00156       (#)  structure of message construction in GCM is defined as below  :
00157          (##) 16 bytes Initial Counter Block (ICB)composed of IV and counter
00158          (##) The authenticated header A (also knows as Additional Authentication Data AAD)
00159           this part of the message is only authenticated, not encrypted.
00160          (##) The plaintext message P is both authenticated and encrypted as ciphertext.
00161           GCM standard specifies that ciphertext has same bit length as the plaintext.
00162          (##) The last block is composed of the length of A (on 64 bits) and the length of ciphertext
00163           (on 64 bits)
00164
00165     [..]  A more detailed description of the GCM message structure is available below.
00166
00167     [..]  This section describe The AES Counter with Cipher Block Chaining-Message
00168           Authentication Code (CCM) supported by both CRYP1 and TinyAES peripheral:
00169       (#)  Specific parameters for CCM  :
00170
00171          (##) B0 block  : follows NIST Special Publication 800-38C,
00172          (##) B1 block (header)
00173          (##) CTRx block  : control blocks
00174
00175     [..]  A detailed description of the CCM message structure is available below.
00176
00177       (#)  Four phases are performed in CCM for CRYP1 peripheral:
00178          (##) Init phase: peripheral prepares the GCM hash subkey (H) and do the IV processing
00179          (##) Header phase: peripheral processes the Additional Authenticated Data (AAD), with hash
00180           computation only.
00181          (##) Payload phase: peripheral processes the plaintext (P) with hash computation + keystream
00182           encryption + data XORing. It works in a similar way for ciphertext (C).
00183          (##) Final phase: peripheral generates the authenticated tag (T) using the last block of data.
00184       (#)    CCM in TinyAES peripheral:
00185          (##) To perform message payload encryption or decryption AES is configured in CTR mode.
00186          (##) For authentication two phases are performed :
00187           - Header phase: peripheral processes the Additional Authenticated Data (AAD) first, then the cleartext message
00188           only cleartext payload (not the ciphertext payload) is used and no outpout.
00189          (##) Final phase: peripheral generates the authenticated tag (T) using the last block of data.
00190
00191   *** Callback registration ***
00192   =============================
00193
00194   [..]
00195   The compilation define  USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1
00196   allows the user to configure dynamically the driver callbacks.
00197   Use Functions @ref HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback()
00198   to register an interrupt callback.
00199
00200   [..]
00201   Function @ref HAL_CRYP_RegisterCallback() allows to register following callbacks:
00202     (+) InCpltCallback     :  Input FIFO transfer completed callback.
00203     (+) OutCpltCallback    : Output FIFO transfer completed callback.
00204     (+) ErrorCallback      : callback for error detection.
00205     (+) MspInitCallback    : CRYP MspInit.
00206     (+) MspDeInitCallback  : CRYP MspDeInit.
00207   This function takes as parameters the HAL peripheral handle, the Callback ID
00208   and a pointer to the user callback function.
00209
00210   [..]
00211   Use function @ref HAL_CRYP_UnRegisterCallback() to reset a callback to the default
00212   weak function.
00213   @ref HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00214   and the Callback ID.
00215   This function allows to reset following callbacks:
00216     (+) InCpltCallback     :  Input FIFO transfer completed callback.
00217     (+) OutCpltCallback    : Output FIFO transfer completed callback.
00218     (+) ErrorCallback      : callback for error detection.
00219     (+) MspInitCallback    : CRYP MspInit.
00220     (+) MspDeInitCallback  : CRYP MspDeInit.
00221
00222   [..]
00223   By default, after the @ref HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET
00224   all callbacks are set to the corresponding weak functions :
00225   examples @ref HAL_CRYP_InCpltCallback() , @ref HAL_CRYP_OutCpltCallback().
00226   Exception done for MspInit and MspDeInit functions that are
00227   reset to the legacy weak function in the @ref HAL_CRYP_Init()/ @ref HAL_CRYP_DeInit() only when
00228   these callbacks are null (not registered beforehand).
00229   if not, MspInit or MspDeInit are not null, the @ref HAL_CRYP_Init() / @ref HAL_CRYP_DeInit()
00230   keep and use the user MspInit/MspDeInit functions (registered beforehand)
00231
00232   [..]
00233   Callbacks can be registered/unregistered in HAL_CRYP_STATE_READY state only.
00234   Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
00235   in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state,
00236   thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00237   In that case first register the MspInit/MspDeInit user callbacks
00238   using @ref HAL_CRYP_RegisterCallback() before calling @ref HAL_CRYP_DeInit()
00239   or @ref HAL_CRYP_Init() function.
00240
00241   [..]
00242   When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or
00243   not defined, the callback registration feature is not available and all callbacks
00244   are set to the corresponding weak functions.
00245
00246
00247   *** Suspend/Resume feature ***
00248   ==============================
00249
00250   [..]
00251   The compilation define USE_HAL_CRYP_SUSPEND_RESUME when set to 1
00252   allows the user to resort to the suspend/resume feature.
00253   A low priority block processing can be suspended to process a high priority block
00254   instead. When the high priority block processing is over, the low priority block
00255   processing can be resumed, restarting from the point where it was suspended. This
00256   feature is applicable only in non-blocking interrupt mode.
00257
00258   [..] User must resort to HAL_CRYP_Suspend() to suspend the low priority block
00259   processing. This API manages the hardware block processing suspension and saves all the
00260   internal data that will be needed to restart later on. Upon HAL_CRYP_Suspend() completion,
00261   the user can launch the processing of any other block (high priority block processing).
00262
00263   [..] When the high priority block processing is over, user must invoke HAL_CRYP_Resume()
00264   to resume the low priority block processing. Ciphering (or deciphering) restarts from
00265   the suspension point and ends as usual.
00266
00267   [..] HAL_CRYP_Suspend() reports an error when the suspension request is sent too late
00268   (i.e when the low priority block processing is about to end). There is no use to
00269   suspend the tag generation processing for authentication algorithms.
00270
00271     [..]
00272     (@) If the key is written out of HAL scope (case pKey pointer set to NULL by the user),
00273         the block processing suspension/resumption mechanism is NOT applicable.
00274
00275     [..]
00276     (@) If the Key and Initialization Vector are configured only once and configuration is
00277         skipped for consecutive processings (case KeyIVConfigSkip set to CRYP_KEYIVCONFIG_ONCE),
00278         the block processing suspension/resumption mechanism is NOT applicable.
00279
00280   @endverbatim
00281   ******************************************************************************
00282   * @attention
00283   *
00284   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00285   * All rights reserved.</center></h2>
00286   *
00287   * This software component is licensed by ST under BSD 3-Clause license,
00288   * the "License"; You may not use this file except in compliance with the
00289   * License. You may obtain a copy of the License at:
00290   *                        opensource.org/licenses/BSD-3-Clause
00291   *
00292   ******************************************************************************
00293   */
00294
00295 /* Includes ------------------------------------------------------------------*/
00296 #include "stm32wbxx_hal.h"
00297
00298 /** @addtogroup STM32WBxx_HAL_Driver
00299   * @{
00300   */
00301
00302 /** @addtogroup CRYP
00303   * @{
00304   */
00305
00306
00307 #ifdef HAL_CRYP_MODULE_ENABLED
00308
00309 /* Private typedef -----------------------------------------------------------*/
00310 /* Private define ------------------------------------------------------------*/
00311 /** @addtogroup CRYP_Private_Defines
00312   * @{
00313   */
00314 #define CRYP_TIMEOUT_KEYPREPARATION      82U         /* The latency of key preparation operation is 82 clock cycles.*/
00315 #define CRYP_TIMEOUT_GCMCCMINITPHASE     299U        /* The latency of  GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/
00316 #define CRYP_TIMEOUT_GCMCCMHEADERPHASE   290U        /* The latency of  GCM/CCM header phase is 290 clock cycles.*/
00317
00318 #define CRYP_PHASE_READY                 0x00000001U /*!< CRYP peripheral is ready for initialization. */
00319 #define CRYP_PHASE_PROCESS               0x00000002U /*!< CRYP peripheral is in processing phase */
00320 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
00321 #define  CRYP_PHASE_HEADER_SUSPENDED     0x00000004U    /*!< GCM/GMAC/CCM header phase is suspended */
00322 #define  CRYP_PHASE_PAYLOAD_SUSPENDED    0x00000005U    /*!< GCM/CCM payload phase is suspended     */
00323 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
00324
00325 #define CRYP_OPERATINGMODE_ENCRYPT                   0x00000000U     /*!< Encryption mode(Mode 1)  */
00326 #define CRYP_OPERATINGMODE_KEYDERIVATION             AES_CR_MODE_0   /*!< Key derivation mode  only used when performing ECB and CBC decryptions (Mode 2) */
00327 #define CRYP_OPERATINGMODE_DECRYPT                   AES_CR_MODE_1   /*!< Decryption    (Mode 3)    */
00328 #define CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT     AES_CR_MODE     /*!< Key derivation and decryption only used when performing ECB and CBC decryptions (Mode 4) */
00329 #define CRYP_PHASE_INIT                              0x00000000U     /*!< GCM/GMAC (or CCM) init phase */
00330 #define CRYP_PHASE_HEADER                            AES_CR_GCMPH_0  /*!< GCM/GMAC or CCM header phase */
00331 #define CRYP_PHASE_PAYLOAD                           AES_CR_GCMPH_1  /*!< GCM(/CCM) payload phase      */
00332 #define CRYP_PHASE_FINAL                             AES_CR_GCMPH    /*!< GCM/GMAC or CCM  final phase */
00333
00334 /*  CTR1 information to use in CCM algorithm */
00335 #define CRYP_CCM_CTR1_0                  0x07FFFFFFU
00336 #define CRYP_CCM_CTR1_1                  0xFFFFFF00U
00337 #define CRYP_CCM_CTR1_2                  0x00000001U
00338
00339 /**
00340   * @}
00341   */
00342
00343 /* Private macro -------------------------------------------------------------*/
00344 /** @addtogroup CRYP_Private_Macros
00345   * @{
00346   */
00347
00348 #define CRYP_SET_PHASE(__HANDLE__, __PHASE__)  do{(__HANDLE__)->Instance->CR &= (uint32_t)(~AES_CR_GCMPH);\
00349                                                   (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
00350                                                  }while(0U)
00351
00352 /**
00353   * @}
00354   */
00355
00356 /* Private struct -------------------------------------------------------------*/
00357 /* Private variables ---------------------------------------------------------*/
00358 /* Private function prototypes -----------------------------------------------*/
00359 /** @addtogroup CRYP_Private_Functions
00360   * @{
00361   */
00362
00363 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
00364 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
00365 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
00366 static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
00367 static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize);
00368 static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp);
00369 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00370 static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp);
00371 static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp);
00372 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp);
00373 static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
00374 static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp);
00375 static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00376 static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00377 static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp);
00378 static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
00379 static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcrypt, uint32_t Timeout);
00380 static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00381 static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00382 static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp);
00383 static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp);
00384 static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp);
00385 static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
00386 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
00387 static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output);
00388 static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input);
00389 static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output);
00390 static void CRYP_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input);
00391 static void CRYP_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output, uint32_t KeySize);
00392 static void CRYP_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input, uint32_t KeySize);
00393 static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp);
00394 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
00395
00396
00397 /**
00398   * @}
00399   */
00400
00401 /* Exported functions ---------------------------------------------------------*/
00402
00403 /** @addtogroup CRYP_Exported_Functions
00404   * @{
00405   */
00406
00407 /** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
00408   * @brief    Initialization and Configuration functions.
00409   *
00410 @verbatim
00411   ========================================================================================
00412      ##### Initialization, de-initialization and Set and Get configuration functions #####
00413   ========================================================================================
00414     [..]  This section provides functions allowing to:
00415       (+) Initialize the CRYP
00416       (+) DeInitialize the CRYP
00417       (+) Initialize the CRYP MSP
00418       (+) DeInitialize the CRYP MSP
00419       (+) configure CRYP (HAL_CRYP_SetConfig) with the specified parameters in the CRYP_ConfigTypeDef
00420           Parameters which are configured in This section are :
00421           (+) Key size
00422           (+) Data Type : 32,16, 8 or 1bit
00423           (+) AlgoMode :
00424               - for CRYP1 peripheral :
00425                  ECB and CBC in DES/TDES Standard
00426                  ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard.
00427               - for TinyAES2 peripheral, only ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard are supported.
00428       (+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef
00429
00430 @endverbatim
00431   * @{
00432   */
00433
00434 /**
00435   * @brief  Initializes the CRYP according to the specified
00436   *         parameters in the CRYP_ConfigTypeDef and creates the associated handle.
00437   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
00438   *         the configuration information for CRYP module
00439   * @retval HAL status
00440   */
00441 HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
00442 {
00443   /* Check the CRYP handle allocation */
00444   if (hcryp == NULL)
00445   {
00446     return HAL_ERROR;
00447   }
00448
00449   /* Check parameters */
00450   assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
00451   assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
00452   assert_param(IS_CRYP_ALGORITHM(hcryp->Init.Algorithm));
00453   assert_param(IS_CRYP_INIT(hcryp->Init.KeyIVConfigSkip));
00454
00455 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
00456   if (hcryp->State == HAL_CRYP_STATE_RESET)
00457   {
00458     /* Allocate lock resource and initialize it */
00459     hcryp->Lock = HAL_UNLOCKED;
00460
00461     hcryp->InCpltCallback  = HAL_CRYP_InCpltCallback;  /* Legacy weak InCpltCallback   */
00462     hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback  */
00463     hcryp->ErrorCallback   = HAL_CRYP_ErrorCallback;   /* Legacy weak ErrorCallback    */
00464
00465     if (hcryp->MspInitCallback == NULL)
00466     {
00467       hcryp->MspInitCallback = HAL_CRYP_MspInit; /* Legacy weak MspInit  */
00468     }
00469
00470     /* Init the low level hardware */
00471     hcryp->MspInitCallback(hcryp);
00472   }
00473 #else
00474   if (hcryp->State == HAL_CRYP_STATE_RESET)
00475   {
00476     /* Allocate lock resource and initialize it */
00477     hcryp->Lock = HAL_UNLOCKED;
00478
00479     /* Init the low level hardware */
00480     HAL_CRYP_MspInit(hcryp);
00481   }
00482 #endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
00483
00484   /* Set the key size (This bit field is do not care in the DES or TDES modes), data type and Algorithm */
00485   MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
00486
00487   /* Reset Error Code field */
00488   hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
00489
00490   /* Reset peripheral Key and IV configuration flag */
00491   hcryp->KeyIVConfig = 0U;
00492
00493   /* Change the CRYP state */
00494   hcryp->State = HAL_CRYP_STATE_READY;
00495
00496   /* Set the default CRYP phase */
00497   hcryp->Phase = CRYP_PHASE_READY;
00498
00499   /* Return function status */
00500   return HAL_OK;
00501 }
00502
00503 /**
00504   * @brief  De-Initializes the CRYP peripheral.
00505   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
00506   *         the configuration information for CRYP module
00507   * @retval HAL status
00508 */
00509 HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
00510 {
00511   /* Check the CRYP handle allocation */
00512   if (hcryp == NULL)
00513   {
00514     return HAL_ERROR;
00515   }
00516
00517   /* Set the default CRYP phase */
00518   hcryp->Phase = CRYP_PHASE_READY;
00519
00520   /* Reset CrypInCount and CrypOutCount */
00521   hcryp->CrypInCount = 0;
00522   hcryp->CrypOutCount = 0;
00523   hcryp->CrypHeaderCount = 0;
00524
00525   /* Disable the CRYP peripheral clock */
00526   __HAL_CRYP_DISABLE(hcryp);
00527
00528 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
00529
00530   if (hcryp->MspDeInitCallback == NULL)
00531   {
00532     hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; /* Legacy weak MspDeInit  */
00533   }
00534   /* DeInit the low level hardware */
00535   hcryp->MspDeInitCallback(hcryp);
00536
00537 #else
00538
00539   /* DeInit the low level hardware: CLOCK, NVIC.*/
00540   HAL_CRYP_MspDeInit(hcryp);
00541
00542 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
00543
00544   /* Change the CRYP state */
00545   hcryp->State = HAL_CRYP_STATE_RESET;
00546
00547   /* Release Lock */
00548   __HAL_UNLOCK(hcryp);
00549
00550   /* Return function status */
00551   return HAL_OK;
00552 }
00553
00554 /**
00555   * @brief  Configure the CRYP according to the specified
00556   *         parameters in the CRYP_ConfigTypeDef
00557   * @param  hcryp pointer to a CRYP_HandleTypeDef structure
00558   * @param  pConf pointer to a CRYP_ConfigTypeDef structure that contains
00559   *         the configuration information for CRYP module
00560   * @retval HAL status
00561   */
00562 HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
00563 {
00564   /* Check the CRYP handle allocation */
00565   if ((hcryp == NULL) || (pConf == NULL))
00566   {
00567     return HAL_ERROR;
00568   }
00569
00570   /* Check parameters */
00571   assert_param(IS_CRYP_KEYSIZE(pConf->KeySize));
00572   assert_param(IS_CRYP_DATATYPE(pConf->DataType));
00573   assert_param(IS_CRYP_ALGORITHM(pConf->Algorithm));
00574
00575   if (hcryp->State == HAL_CRYP_STATE_READY)
00576   {
00577     /* Change the CRYP state */
00578     hcryp->State = HAL_CRYP_STATE_BUSY;
00579
00580     /* Process locked */
00581     __HAL_LOCK(hcryp);
00582
00583     /* Set  CRYP parameters  */
00584     hcryp->Init.DataType   = pConf->DataType;
00585     hcryp->Init.pKey       = pConf->pKey;
00586     hcryp->Init.Algorithm  = pConf->Algorithm;
00587     hcryp->Init.KeySize    = pConf->KeySize;
00588     hcryp->Init.pInitVect  = pConf->pInitVect;
00589     hcryp->Init.Header     = pConf->Header;
00590     hcryp->Init.HeaderSize = pConf->HeaderSize;
00591     hcryp->Init.B0         = pConf->B0;
00592     hcryp->Init.DataWidthUnit = pConf->DataWidthUnit;
00593
00594     /* Set the key size (This bit field is do not care in the DES or TDES modes), data type and operating mode*/
00595     MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
00596
00597     /*clear error flags*/
00598     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_ERR_CLEAR);
00599
00600     /* Process Unlocked */
00601     __HAL_UNLOCK(hcryp);
00602
00603     /* Reset Error Code field */
00604     hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
00605
00606     /* Change the CRYP state */
00607     hcryp->State = HAL_CRYP_STATE_READY;
00608
00609     /* Set the default CRYP phase */
00610     hcryp->Phase = CRYP_PHASE_READY;
00611
00612     /* Return function status */
00613     return HAL_OK;
00614   }
00615   else
00616   {
00617     /* Process Unlocked */
00618     __HAL_UNLOCK(hcryp);
00619
00620     /* Busy error code field */
00621     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
00622     return HAL_ERROR;
00623   }
00624 }
00625
00626 /**
00627   * @brief  Get CRYP Configuration parameters in associated handle.
00628   * @param  pConf pointer to a CRYP_ConfigTypeDef structure
00629   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
00630   *         the configuration information for CRYP module
00631   * @retval HAL status
00632   */
00633 HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
00634 {
00635   /* Check the CRYP handle allocation */
00636   if ((hcryp == NULL) || (pConf == NULL))
00637   {
00638     return HAL_ERROR;
00639   }
00640
00641   if (hcryp->State == HAL_CRYP_STATE_READY)
00642   {
00643     /* Change the CRYP state */
00644     hcryp->State = HAL_CRYP_STATE_BUSY;
00645
00646     /* Process locked */
00647     __HAL_LOCK(hcryp);
00648
00649     /* Get  CRYP parameters  */
00650     pConf->DataType        = hcryp->Init.DataType;
00651     pConf->pKey            = hcryp->Init.pKey;
00652     pConf->Algorithm       = hcryp->Init.Algorithm;
00653     pConf->KeySize         = hcryp->Init.KeySize ;
00654     pConf->pInitVect       = hcryp->Init.pInitVect;
00655     pConf->Header          = hcryp->Init.Header ;
00656     pConf->HeaderSize      = hcryp->Init.HeaderSize;
00657     pConf->B0              = hcryp->Init.B0;
00658     pConf->DataWidthUnit    = hcryp->Init.DataWidthUnit;
00659
00660     /* Process Unlocked */
00661     __HAL_UNLOCK(hcryp);
00662
00663     /* Change the CRYP state */
00664     hcryp->State = HAL_CRYP_STATE_READY;
00665
00666     /* Return function status */
00667     return HAL_OK;
00668   }
00669   else
00670   {
00671     /* Process Unlocked */
00672     __HAL_UNLOCK(hcryp);
00673
00674     /* Busy error code field */
00675     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
00676     return HAL_ERROR;
00677   }
00678 }
00679 /**
00680   * @brief  Initializes the CRYP MSP.
00681   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
00682   *         the configuration information for CRYP module
00683   * @retval None
00684   */
00685 __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
00686 {
00687   /* Prevent unused argument(s) compilation warning */
00688   UNUSED(hcryp);
00689
00690   /* NOTE : This function Should not be modified, when the callback is needed,
00691             the HAL_CRYP_MspInit could be implemented in the user file
00692    */
00693 }
00694
00695 /**
00696   * @brief  DeInitializes CRYP MSP.
00697   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
00698   *         the configuration information for CRYP module
00699   * @retval None
00700   */
00701 __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
00702 {
00703   /* Prevent unused argument(s) compilation warning */
00704   UNUSED(hcryp);
00705
00706   /* NOTE : This function Should not be modified, when the callback is needed,
00707             the HAL_CRYP_MspDeInit could be implemented in the user file
00708    */
00709 }
00710
00711 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
00712 /**
00713   * @brief  Register a User CRYP Callback
00714   *         To be used instead of the weak predefined callback
00715   * @param hcryp cryp handle
00716   * @param CallbackID ID of the callback to be registered
00717   *        This parameter can be one of the following values:
00718   *          @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
00719   *          @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
00720   *          @arg @ref HAL_CRYP_ERROR_CB_ID Error callback ID
00721   *          @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
00722   *          @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
00723   * @param pCallback pointer to the Callback function
00724   * @retval status
00725   */
00726 HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback)
00727 {
00728   HAL_StatusTypeDef status = HAL_OK;
00729
00730   if (pCallback == NULL)
00731   {
00732     /* Update the error code */
00733     hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
00734
00735     return HAL_ERROR;
00736   }
00737   /* Process locked */
00738   __HAL_LOCK(hcryp);
00739
00740   if (hcryp->State == HAL_CRYP_STATE_READY)
00741   {
00742     switch (CallbackID)
00743     {
00744       case HAL_CRYP_INPUT_COMPLETE_CB_ID :
00745         hcryp->InCpltCallback = pCallback;
00746         break;
00747
00748       case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
00749         hcryp->OutCpltCallback = pCallback;
00750         break;
00751
00752       case HAL_CRYP_ERROR_CB_ID :
00753         hcryp->ErrorCallback = pCallback;
00754         break;
00755
00756       case HAL_CRYP_MSPINIT_CB_ID :
00757         hcryp->MspInitCallback = pCallback;
00758         break;
00759
00760       case HAL_CRYP_MSPDEINIT_CB_ID :
00761         hcryp->MspDeInitCallback = pCallback;
00762         break;
00763
00764       default :
00765         /* Update the error code */
00766         hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
00767         /* Return error status */
00768         status =  HAL_ERROR;
00769         break;
00770     }
00771   }
00772   else if (hcryp->State == HAL_CRYP_STATE_RESET)
00773   {
00774     switch (CallbackID)
00775     {
00776       case HAL_CRYP_MSPINIT_CB_ID :
00777         hcryp->MspInitCallback = pCallback;
00778         break;
00779
00780       case HAL_CRYP_MSPDEINIT_CB_ID :
00781         hcryp->MspDeInitCallback = pCallback;
00782         break;
00783
00784       default :
00785         /* Update the error code */
00786         hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
00787         /* Return error status */
00788         status =  HAL_ERROR;
00789         break;
00790     }
00791   }
00792   else
00793   {
00794     /* Update the error code */
00795     hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
00796     /* Return error status */
00797     status =  HAL_ERROR;
00798   }
00799
00800   /* Release Lock */
00801   __HAL_UNLOCK(hcryp);
00802
00803   return status;
00804 }
00805
00806 /**
00807   * @brief  Unregister an CRYP Callback
00808   *         CRYP callback is redirected to the weak predefined callback
00809   * @param hcryp cryp handle
00810   * @param CallbackID ID of the callback to be unregistered
00811   *        This parameter can be one of the following values:
00812   *          @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
00813   *          @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
00814   *          @arg @ref HAL_CRYP_ERROR_CB_ID Error callback ID
00815   *          @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
00816   *          @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
00817   * @retval status
00818   */
00819 HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID)
00820 {
00821   HAL_StatusTypeDef status = HAL_OK;
00822
00823   /* Process locked */
00824   __HAL_LOCK(hcryp);
00825
00826   if (hcryp->State == HAL_CRYP_STATE_READY)
00827   {
00828     switch (CallbackID)
00829     {
00830       case HAL_CRYP_INPUT_COMPLETE_CB_ID :
00831         hcryp->InCpltCallback = HAL_CRYP_InCpltCallback;  /* Legacy weak  InCpltCallback  */
00832         break;
00833
00834       case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
00835         hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback;         /* Legacy weak OutCpltCallback       */
00836         break;
00837
00838       case HAL_CRYP_ERROR_CB_ID :
00839         hcryp->ErrorCallback = HAL_CRYP_ErrorCallback;           /* Legacy weak ErrorCallback        */
00840         break;
00841
00842       case HAL_CRYP_MSPINIT_CB_ID :
00843         hcryp->MspInitCallback = HAL_CRYP_MspInit;
00844         break;
00845
00846       case HAL_CRYP_MSPDEINIT_CB_ID :
00847         hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
00848         break;
00849
00850       default :
00851         /* Update the error code */
00852         hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
00853         /* Return error status */
00854         status =  HAL_ERROR;
00855         break;
00856     }
00857   }
00858   else if (hcryp->State == HAL_CRYP_STATE_RESET)
00859   {
00860     switch (CallbackID)
00861     {
00862       case HAL_CRYP_MSPINIT_CB_ID :
00863         hcryp->MspInitCallback = HAL_CRYP_MspInit;
00864         break;
00865
00866       case HAL_CRYP_MSPDEINIT_CB_ID :
00867         hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
00868         break;
00869
00870       default :
00871         /* Update the error code */
00872         hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
00873         /* Return error status */
00874         status =  HAL_ERROR;
00875         break;
00876     }
00877   }
00878   else
00879   {
00880     /* Update the error code */
00881     hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;;
00882     /* Return error status */
00883     status =  HAL_ERROR;
00884   }
00885
00886   /* Release Lock */
00887   __HAL_UNLOCK(hcryp);
00888
00889   return status;
00890 }
00891 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
00892
00893 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
00894 /**
00895   * @brief  Request CRYP processing suspension when in interruption mode.
00896   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
00897   *         the configuration information for CRYP module.
00898   * @note   Set the handle field SuspendRequest to the appropriate value so that
00899   *         the on-going CRYP processing is suspended as soon as the required
00900   *         conditions are met.
00901   * @note   HAL_CRYP_ProcessSuspend() can only be invoked when the processing is done
00902   *         in non-blocking interrupt mode.
00903   * @note   It is advised not to suspend the CRYP processing when the DMA controller
00904   *         is managing the data transfer.
00905   * @retval None
00906   */
00907 void HAL_CRYP_ProcessSuspend(CRYP_HandleTypeDef *hcryp)
00908 {
00909   /* Set Handle SuspendRequest field */
00910   hcryp->SuspendRequest = HAL_CRYP_SUSPEND;
00911 }
00912
00913
00914
00915 /**
00916   * @brief  CRYP processing suspension and peripheral internal parameters storage.
00917   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
00918   *         the configuration information for CRYP module
00919   * @note   peripheral internal parameters are stored to be readily available when
00920   *         suspended processing is resumed later on.
00921   * @retval HAL status
00922   */
00923 HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp)
00924 {
00925   HAL_CRYP_STATETypeDef state;
00926
00927   /* Request suspension */
00928   HAL_CRYP_ProcessSuspend(hcryp);
00929
00930   do
00931   {
00932     state = HAL_CRYP_GetState(hcryp);
00933   } while ((state != HAL_CRYP_STATE_SUSPENDED) && (state != HAL_CRYP_STATE_READY));
00934
00935   if (HAL_CRYP_GetState(hcryp) == HAL_CRYP_STATE_READY)
00936   {
00937     /* Processing was already over or was about to end. No suspension done */
00938     return HAL_ERROR;
00939   }
00940   else
00941   {
00942     /* Suspend Processing */
00943
00944     /* If authentication algorithms on-going, carry out first saving steps
00945        before disable the peripheral */
00946     if ((hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) || \
00947          (hcryp->Init.Algorithm == CRYP_AES_CCM))
00948     {
00949         /* Save Suspension registers */
00950         CRYP_Read_SuspendRegisters(hcryp, hcryp->SUSPxR_saved);
00951         /* Save Key */
00952         CRYP_Read_KeyRegisters(hcryp, hcryp->Key_saved, hcryp->Init.KeySize);
00953         /* Save IV */
00954         CRYP_Read_IVRegisters(hcryp, hcryp->IV_saved);
00955     }
00956     /* Disable AES */
00957     __HAL_CRYP_DISABLE(hcryp);
00958
00959     /* Save low-priority block CRYP handle parameters */
00960     hcryp->Init_saved              = hcryp->Init;
00961     hcryp->pCrypInBuffPtr_saved    = hcryp->pCrypInBuffPtr;
00962     hcryp->pCrypOutBuffPtr_saved   = hcryp->pCrypOutBuffPtr;
00963     hcryp->CrypInCount_saved       = hcryp->CrypInCount;
00964     hcryp->CrypOutCount_saved      = hcryp->CrypOutCount;
00965     hcryp->Phase_saved             = hcryp->Phase;
00966     hcryp->State_saved             = hcryp->State;
00967     hcryp->Size_saved              = ( (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) ? (hcryp->Size /4U) : hcryp->Size);
00968     hcryp->AutoKeyDerivation_saved = hcryp->AutoKeyDerivation;
00969     hcryp->CrypHeaderCount_saved   = hcryp->CrypHeaderCount;
00970     hcryp->SuspendRequest          = HAL_CRYP_SUSPEND_NONE;
00971
00972     if ((hcryp->Init.Algorithm == CRYP_AES_CBC) || \
00973         (hcryp->Init.Algorithm == CRYP_AES_CTR))
00974     {
00975       /* Save Initialisation Vector registers */
00976       CRYP_Read_IVRegisters(hcryp, hcryp->IV_saved);
00977     }
00978
00979     /* Save Control register */
00980     hcryp->CR_saved = hcryp->Instance->CR;
00981
00982   }
00983   return HAL_OK;
00984 }
00985
00986
00987 /**
00988   * @brief  CRYP processing resumption.
00989   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
00990   *         the configuration information for CRYP module
00991   * @note   Processing restarts at the exact point where it was suspended, based
00992   *         on the parameters saved at suspension time.
00993   * @retval HAL status
00994   */
00995 HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp)
00996 {
00997   /* Check the CRYP handle allocation */
00998   if (hcryp == NULL)
00999   {
01000     return HAL_ERROR;
01001   }
01002
01003   if (hcryp->State_saved != HAL_CRYP_STATE_SUSPENDED)
01004   {
01005     /* CRYP was not suspended */
01006     return HAL_ERROR;
01007   }
01008   else
01009   {
01010
01011     /* Restore low-priority block CRYP handle parameters */
01012     hcryp->Init            = hcryp->Init_saved;
01013     hcryp->State           = hcryp->State_saved;
01014
01015     /* Chaining algorithms case */
01016     if ((hcryp->Init_saved.Algorithm == CRYP_AES_ECB) || \
01017         (hcryp->Init_saved.Algorithm == CRYP_AES_CBC) || \
01018         (hcryp->Init_saved.Algorithm == CRYP_AES_CTR))
01019     {
01020       /* Restore low-priority block CRYP handle parameters */
01021       hcryp->AutoKeyDerivation = hcryp->AutoKeyDerivation_saved;
01022
01023       if ((hcryp->Init.Algorithm == CRYP_AES_CBC) || \
01024         (hcryp->Init.Algorithm == CRYP_AES_CTR))
01025       {
01026         hcryp->Init.pInitVect     = hcryp->IV_saved;
01027       }
01028       __HAL_CRYP_DISABLE(hcryp);
01029       (void) HAL_CRYP_Init(hcryp);
01030     }
01031     else    /* Authentication algorithms case */
01032     {
01033       /* Restore low-priority block CRYP handle parameters */
01034       hcryp->Phase           = hcryp->Phase_saved;
01035       hcryp->CrypHeaderCount = hcryp->CrypHeaderCount_saved;
01036
01037       /* Disable AES and write-back SUSPxR registers */;
01038       __HAL_CRYP_DISABLE(hcryp);
01039       /* Restore AES Suspend Registers */
01040       CRYP_Write_SuspendRegisters(hcryp, hcryp->SUSPxR_saved);
01041       /* Restore Control,  Key and IV Registers, then enable AES */
01042       hcryp->Instance->CR = hcryp->CR_saved;
01043       CRYP_Write_KeyRegisters(hcryp, hcryp->Key_saved, hcryp->Init.KeySize);
01044       CRYP_Write_IVRegisters(hcryp, hcryp->IV_saved);
01045       __HAL_CRYP_ENABLE_IT(hcryp,CRYP_IT_CCFIE | CRYP_IT_ERRIE);
01046       __HAL_CRYP_ENABLE(hcryp);
01047
01048       /* At the same time, set handle state back to READY to be able to resume the AES calculations
01049       without the processing APIs returning HAL_BUSY when called. */
01050       hcryp->State        = HAL_CRYP_STATE_READY;
01051     }
01052
01053
01054     /* Resume low-priority block processing under IT */
01055     hcryp->ResumingFlag = 1U;
01056     if (READ_BIT(hcryp->CR_saved, AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
01057     {
01058       if (HAL_CRYP_Encrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved, hcryp->Size_saved, hcryp->pCrypOutBuffPtr_saved) != HAL_OK)
01059       {
01060         return HAL_ERROR;
01061       }
01062     }
01063     else
01064     {
01065       if (HAL_CRYP_Decrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved, hcryp->Size_saved, hcryp->pCrypOutBuffPtr_saved) != HAL_OK)
01066       {
01067         return HAL_ERROR;
01068       }
01069     }
01070   }
01071   return HAL_OK;
01072 }
01073 #endif /* defined (USE_HAL_CRYP_SUSPEND_RESUME) */
01074
01075 /**
01076   * @}
01077   */
01078
01079 /** @defgroup CRYP_Exported_Functions_Group2 Encryption Decryption functions
01080   * @brief    Encryption Decryption functions.
01081   *
01082 @verbatim
01083   ==============================================================================
01084                       ##### Encrypt Decrypt  functions #####
01085   ==============================================================================
01086     [..]  This section provides API allowing to Encrypt/Decrypt Data following
01087           Standard DES/TDES or AES, and Algorithm configured by the user:
01088       (+) Standard DES/TDES only supported by CRYP1 peripheral, below list of Algorithm supported :
01089            - Electronic Code Book(ECB)
01090            - Cipher Block Chaining (CBC)
01091       (+) Standard AES  supported by CRYP1 peripheral & TinyAES, list of Algorithm supported:
01092            - Electronic Code Book(ECB)
01093            - Cipher Block Chaining (CBC)
01094            - Counter mode (CTR)
01095            - Cipher Block Chaining (CBC)
01096            - Counter mode (CTR)
01097            - Galois/counter mode (GCM)
01098            - Counter with Cipher Block Chaining-Message(CCM)
01099     [..]  Three processing functions are available:
01100       (+) Polling mode : HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
01101       (+) Interrupt mode : HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
01102       (+) DMA mode : HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
01103
01104 @endverbatim
01105   * @{
01106   */
01107
01108 /* GCM message structure additional details
01109
01110                                   ICB
01111           +-------------------------------------------------------+
01112           |       Initialization vector (IV)      |  Counter      |
01113           |----------------|----------------|-----------|---------|
01114          127              95                63            31       0
01115
01116
01117               Bit Number    Register           Contents
01118               ----------   ---------------       -----------
01119               127 ...96    CRYP_IV1R[31:0]     ICB[127:96]
01120               95  ...64    CRYP_IV1L[31:0]     B0[95:64]
01121               63 ... 32    CRYP_IV0R[31:0]     ICB[63:32]
01122               31 ... 0     CRYP_IV0L[31:0]     ICB[31:0], where 32-bit counter= 0x2
01123
01124
01125
01126                                  GCM last block definition
01127           +-------------------------------------------------------------------+
01128           |  Bit[0]   |  Bit[32]           |  Bit[64]  | Bit[96]              |
01129           |-----------|--------------------|-----------|----------------------|
01130           |   0x0     | Header length[31:0]|     0x0   | Payload length[31:0] |
01131           |-----------|--------------------|-----------|----------------------|
01132
01133 */
01134
01135 /* CCM message blocks description
01136
01137          (##) B0 block  : According to NIST Special Publication 800-38C,
01138             The first block B0 is formatted as follows, where l(m) is encoded in
01139             most-significant-byte first order:
01140
01141                 Octet Number   Contents
01142                 ------------   ---------
01143                 0              Flags
01144                 1 ... 15-q     Nonce N
01145                 16-q ... 15    Q
01146
01147             the Flags field is formatted as follows:
01148
01149                 Bit Number   Contents
01150                 ----------   ----------------------
01151                 7            Reserved (always zero)
01152                 6            Adata
01153                 5 ... 3      (t-2)/2
01154                 2 ... 0      [q-1]3
01155
01156               - Q: a bit string representation of the octet length of P (plaintext)
01157               - q The octet length of the binary representation of the octet length of the payload
01158               - A nonce (N), n The octet length of the where n+q=15.
01159               - Flags: most significant octet containing four flags for control information,
01160               - t The octet length of the MAC.
01161          (##) B1 block (header) : associated data length(a) concatenated with Associated Data (A)
01162               the associated data length expressed in bytes (a) defined as below:
01163             - If 0 < a < 216-28, then it is encoded as [a]16, i.e. two octets
01164             - If 216-28 < a < 232, then it is encoded as 0xff || 0xfe || [a]32, i.e. six octets
01165             - If 232 < a < 264, then it is encoded as 0xff || 0xff || [a]64, i.e. ten octets
01166          (##) CTRx block  : control blocks
01167             - Generation of CTR1 from first block B0 information :
01168               equal to B0 with first 5 bits zeroed and most significant bits storing octet
01169               length of P also zeroed, then incremented by one
01170
01171                 Bit Number    Register           Contents
01172                 ----------   ---------------       -----------
01173                 127 ...96    CRYP_IV1R[31:0]     B0[127:96], where Q length bits are set to 0, except for
01174                                                  bit 0 that is set to 1
01175                 95  ...64    CRYP_IV1L[31:0]     B0[95:64]
01176                 63 ... 32    CRYP_IV0R[31:0]     B0[63:32]
01177                 31 ... 0     CRYP_IV0L[31:0]     B0[31:0], where flag bits set to 0
01178
01179             - Generation of CTR0: same as CTR1 with bit[0] set to zero.
01180
01181 */
01182
01183 /**
01184   * @brief  Encryption mode.
01185   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
01186   *         the configuration information for CRYP module
01187   * @param  Input Pointer to the input buffer (plaintext)
01188   * @param  Size Length of the plaintext buffer in word.
01189   * @param  Output Pointer to the output buffer(ciphertext)
01190   * @param  Timeout Specify Timeout value
01191   * @retval HAL status
01192   */
01193 HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
01194 {
01195   uint32_t algo;
01196   HAL_StatusTypeDef status;
01197 #ifdef  USE_FULL_ASSERT
01198   uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
01199
01200   /* Check input buffer size */
01201   assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
01202 #endif
01203
01204   if (hcryp->State == HAL_CRYP_STATE_READY)
01205   {
01206     /* Change state Busy */
01207     hcryp->State = HAL_CRYP_STATE_BUSY;
01208
01209     /* Process locked */
01210     __HAL_LOCK(hcryp);
01211
01212     /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
01213     hcryp->CrypInCount = 0U;
01214     hcryp->CrypOutCount = 0U;
01215     hcryp->pCrypInBuffPtr = Input;
01216     hcryp->pCrypOutBuffPtr = Output;
01217
01218     /*  Calculate Size parameter in Byte*/
01219     if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
01220     {
01221       hcryp->Size = Size * 4U;
01222     }
01223     else
01224     {
01225       hcryp->Size = Size;
01226     }
01227
01228     /* Set the operating mode*/
01229     MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
01230
01231     /* algo get algorithm selected */
01232     algo = hcryp->Instance->CR & AES_CR_CHMOD;
01233
01234     switch (algo)
01235     {
01236
01237       case CRYP_AES_ECB:
01238       case CRYP_AES_CBC:
01239       case CRYP_AES_CTR:
01240
01241         /* AES encryption */
01242         status = CRYP_AES_Encrypt(hcryp, Timeout);
01243         break;
01244
01245       case CRYP_AES_GCM_GMAC:
01246
01247         /* AES GCM encryption */
01248         status = CRYP_AESGCM_Process(hcryp, Timeout) ;
01249         break;
01250
01251       case CRYP_AES_CCM:
01252
01253         /* AES CCM encryption */
01254         status = CRYP_AESCCM_Process(hcryp, Timeout);
01255         break;
01256
01257       default:
01258         hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
01259         status = HAL_ERROR;
01260         break;
01261     }
01262
01263     if (status == HAL_OK)
01264     {
01265       /* Change the CRYP peripheral state */
01266       hcryp->State = HAL_CRYP_STATE_READY;
01267
01268       /* Process unlocked */
01269       __HAL_UNLOCK(hcryp);
01270     }
01271   }
01272   else
01273   {
01274     /* Busy error code field */
01275     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
01276     status = HAL_ERROR;
01277   }
01278
01279   /* Return function status */
01280   return status;
01281 }
01282
01283 /**
01284   * @brief  Decryption mode.
01285   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
01286   *         the configuration information for CRYP module
01287   * @param  Input Pointer to the input buffer (ciphertext )
01288   * @param  Size Length of the plaintext buffer in word.
01289   * @param  Output Pointer to the output buffer(plaintext)
01290   * @param  Timeout Specify Timeout value
01291   * @retval HAL status
01292   */
01293 HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
01294 {
01295   HAL_StatusTypeDef status;
01296   uint32_t algo;
01297 #ifdef  USE_FULL_ASSERT
01298   uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
01299
01300   /* Check input buffer size */
01301   assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
01302 #endif
01303
01304   if (hcryp->State == HAL_CRYP_STATE_READY)
01305   {
01306     /* Change state Busy */
01307     hcryp->State = HAL_CRYP_STATE_BUSY;
01308
01309     /* Process locked */
01310     __HAL_LOCK(hcryp);
01311
01312     /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr  parameters*/
01313     hcryp->CrypInCount = 0U;
01314     hcryp->CrypOutCount = 0U;
01315     hcryp->pCrypInBuffPtr = Input;
01316     hcryp->pCrypOutBuffPtr = Output;
01317
01318     /*  Calculate Size parameter in Byte*/
01319     if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
01320     {
01321       hcryp->Size = Size * 4U;
01322     }
01323     else
01324     {
01325       hcryp->Size = Size;
01326     }
01327
01328     /* Set Decryption operating mode*/
01329     MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
01330
01331     /* algo get algorithm selected */
01332     algo = hcryp->Instance->CR & AES_CR_CHMOD;
01333
01334     switch (algo)
01335     {
01336
01337       case CRYP_AES_ECB:
01338       case CRYP_AES_CBC:
01339       case CRYP_AES_CTR:
01340
01341         /* AES decryption */
01342         status = CRYP_AES_Decrypt(hcryp, Timeout);
01343         break;
01344
01345       case CRYP_AES_GCM_GMAC:
01346
01347         /* AES GCM decryption */
01348         status = CRYP_AESGCM_Process(hcryp, Timeout) ;
01349         break;
01350
01351       case CRYP_AES_CCM:
01352
01353         /* AES CCM decryption */
01354         status = CRYP_AESCCM_Process(hcryp, Timeout);
01355         break;
01356
01357       default:
01358         hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
01359         status = HAL_ERROR;
01360         break;
01361     }
01362
01363     if (status == HAL_OK)
01364     {
01365       /* Change the CRYP peripheral state */
01366       hcryp->State = HAL_CRYP_STATE_READY;
01367
01368       /* Process unlocked */
01369       __HAL_UNLOCK(hcryp);
01370     }
01371   }
01372   else
01373   {
01374     /* Busy error code field */
01375     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
01376     status = HAL_ERROR;
01377   }
01378
01379   /* Return function status */
01380   return status;
01381 }
01382
01383 /**
01384   * @brief  Encryption in interrupt mode.
01385   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
01386   *         the configuration information for CRYP module
01387   * @param  Input Pointer to the input buffer (plaintext)
01388   * @param  Size Length of the plaintext buffer in word
01389   * @param  Output Pointer to the output buffer(ciphertext)
01390   * @retval HAL status
01391   */
01392 HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
01393 {
01394   HAL_StatusTypeDef status;
01395   uint32_t algo;
01396 #ifdef  USE_FULL_ASSERT
01397   uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
01398
01399   /* Check input buffer size */
01400   assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
01401 #endif
01402
01403   if (hcryp->State == HAL_CRYP_STATE_READY)
01404   {
01405     /* Change state Busy */
01406     hcryp->State = HAL_CRYP_STATE_BUSY;
01407
01408     /* Process locked */
01409     __HAL_LOCK(hcryp);
01410
01411     /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
01412 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
01413    if (hcryp->ResumingFlag == 1U)
01414    {
01415      hcryp->ResumingFlag = 0U;
01416      if (hcryp->Phase != CRYP_PHASE_HEADER_SUSPENDED)
01417      {
01418        hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved;
01419        hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved;
01420      }
01421      else
01422      {
01423     hcryp->CrypInCount = 0U;
01424     hcryp->CrypOutCount = 0U;
01425      }
01426    }
01427    else
01428 #endif  /* USE_HAL_CRYP_SUSPEND_RESUME */
01429    {
01430     hcryp->CrypInCount = 0U;
01431     hcryp->CrypOutCount = 0U;
01432    }
01433
01434     hcryp->pCrypInBuffPtr = Input;
01435     hcryp->pCrypOutBuffPtr = Output;
01436
01437     /*  Calculate Size parameter in Byte*/
01438     if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
01439     {
01440       hcryp->Size = Size * 4U;
01441     }
01442     else
01443     {
01444       hcryp->Size = Size;
01445     }
01446
01447     /* Set encryption operating mode*/
01448     MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
01449
01450     /* algo get algorithm selected */
01451     algo = hcryp->Instance->CR & AES_CR_CHMOD;
01452
01453     switch (algo)
01454     {
01455
01456       case CRYP_AES_ECB:
01457       case CRYP_AES_CBC:
01458       case CRYP_AES_CTR:
01459
01460         /* AES encryption */
01461         status = CRYP_AES_Encrypt_IT(hcryp);
01462         break;
01463
01464       case CRYP_AES_GCM_GMAC:
01465
01466         /* AES GCM encryption */
01467         status = CRYP_AESGCM_Process_IT(hcryp) ;
01468         break;
01469
01470       case CRYP_AES_CCM:
01471
01472         /* AES CCM encryption */
01473         status = CRYP_AESCCM_Process_IT(hcryp);
01474         break;
01475
01476       default:
01477         hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
01478         status = HAL_ERROR;
01479         break;
01480     }
01481   }
01482   else
01483   {
01484     /* Busy error code field */
01485     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
01486     status = HAL_ERROR;
01487   }
01488
01489   /* Return function status */
01490   return status;
01491 }
01492
01493 /**
01494   * @brief  Decryption in interrupt mode.
01495   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
01496   *         the configuration information for CRYP module
01497   * @param  Input Pointer to the input buffer (ciphertext )
01498   * @param  Size Length of the plaintext buffer in word.
01499   * @param  Output Pointer to the output buffer(plaintext)
01500   * @retval HAL status
01501   */
01502 HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
01503 {
01504   HAL_StatusTypeDef status;
01505   uint32_t algo;
01506 #ifdef  USE_FULL_ASSERT
01507   uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
01508
01509   /* Check input buffer size */
01510   assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
01511 #endif
01512
01513   if (hcryp->State == HAL_CRYP_STATE_READY)
01514   {
01515     /* Change state Busy */
01516     hcryp->State = HAL_CRYP_STATE_BUSY;
01517
01518     /* Process locked */
01519     __HAL_LOCK(hcryp);
01520
01521     /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
01522 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
01523    if (hcryp->ResumingFlag == 1U)
01524    {
01525      hcryp->ResumingFlag = 0U;
01526      if (hcryp->Phase != CRYP_PHASE_HEADER_SUSPENDED)
01527      {
01528        hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved;
01529        hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved;
01530      }
01531      else
01532      {
01533     hcryp->CrypInCount = 0U;
01534     hcryp->CrypOutCount = 0U;
01535      }
01536    }
01537    else
01538 #endif  /* USE_HAL_CRYP_SUSPEND_RESUME */
01539    {
01540      hcryp->CrypInCount = 0U;
01541      hcryp->CrypOutCount = 0U;
01542    }
01543     hcryp->pCrypInBuffPtr = Input;
01544     hcryp->pCrypOutBuffPtr = Output;
01545
01546     /*  Calculate Size parameter in Byte*/
01547     if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
01548     {
01549       hcryp->Size = Size * 4U;
01550     }
01551     else
01552     {
01553       hcryp->Size = Size;
01554     }
01555
01556     /* Set decryption operating mode*/
01557     MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
01558
01559     /* algo get algorithm selected */
01560     algo = hcryp->Instance->CR & AES_CR_CHMOD;
01561
01562     switch (algo)
01563     {
01564
01565       case CRYP_AES_ECB:
01566       case CRYP_AES_CBC:
01567       case CRYP_AES_CTR:
01568
01569         /* AES decryption */
01570         status = CRYP_AES_Decrypt_IT(hcryp);
01571         break;
01572
01573       case CRYP_AES_GCM_GMAC:
01574
01575         /* AES GCM decryption */
01576         status = CRYP_AESGCM_Process_IT(hcryp) ;
01577         break;
01578
01579       case CRYP_AES_CCM:
01580
01581         /* AES CCM decryption */
01582         status = CRYP_AESCCM_Process_IT(hcryp);
01583         break;
01584
01585       default:
01586         hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
01587         status = HAL_ERROR;
01588         break;
01589     }
01590   }
01591   else
01592   {
01593     /* Busy error code field */
01594     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
01595     status = HAL_ERROR;
01596   }
01597
01598   /* Return function status */
01599   return status;
01600 }
01601
01602 /**
01603   * @brief  Encryption in DMA mode.
01604   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
01605   *         the configuration information for CRYP module
01606   * @param  Input Pointer to the input buffer (plaintext)
01607   * @param  Size Length of the plaintext buffer in word.
01608   * @param  Output Pointer to the output buffer(ciphertext)
01609   * @retval HAL status
01610   */
01611 HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
01612 {
01613   HAL_StatusTypeDef status;
01614   uint32_t algo;
01615   uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
01616 #ifdef  USE_FULL_ASSERT
01617   uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
01618
01619   /* Check input buffer size */
01620   assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
01621 #endif
01622
01623   if (hcryp->State == HAL_CRYP_STATE_READY)
01624   {
01625     /* Change state Busy */
01626     hcryp->State = HAL_CRYP_STATE_BUSY;
01627
01628     /* Process locked */
01629     __HAL_LOCK(hcryp);
01630
01631     /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
01632     hcryp->CrypInCount = 0U;
01633     hcryp->CrypOutCount = 0U;
01634     hcryp->pCrypInBuffPtr = Input;
01635     hcryp->pCrypOutBuffPtr = Output;
01636
01637     /*  Calculate Size parameter in Byte*/
01638     if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
01639     {
01640       hcryp->Size = Size * 4U;
01641     }
01642     else
01643     {
01644       hcryp->Size = Size;
01645     }
01646
01647     /* Set encryption operating mode*/
01648     MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
01649
01650     /* algo get algorithm selected */
01651     algo = hcryp->Instance->CR & AES_CR_CHMOD;
01652
01653     switch (algo)
01654     {
01655
01656       case CRYP_AES_ECB:
01657       case CRYP_AES_CBC:
01658       case CRYP_AES_CTR:
01659
01660         if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
01661         {
01662           if (hcryp->KeyIVConfig == 1U)
01663           {
01664             /* If the Key and IV configuration has to be done only once
01665                and if it has already been done, skip it */
01666             DoKeyIVConfig = 0U;
01667           }
01668           else
01669           {
01670             /* If the Key and IV configuration has to be done only once
01671                and if it has not been done already, do it and set KeyIVConfig
01672                to keep track it won't have to be done again next time */
01673             hcryp->KeyIVConfig = 1U;
01674           }
01675         }
01676
01677         if (DoKeyIVConfig == 1U)
01678         {
01679           /*  Set the Key*/
01680           CRYP_SetKey(hcryp, hcryp->Init.KeySize);
01681
01682           /* Set the Initialization Vector*/
01683           if (hcryp->Init.Algorithm != CRYP_AES_ECB)
01684           {
01685             hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
01686             hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
01687             hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
01688             hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
01689           }
01690         } /* if (DoKeyIVConfig == 1U) */
01691
01692         /* Set the phase */
01693         hcryp->Phase = CRYP_PHASE_PROCESS;
01694
01695         /* Start DMA process transfer for AES */
01696         CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
01697         status = HAL_OK;
01698         break;
01699
01700       case CRYP_AES_GCM_GMAC:
01701
01702         /* AES GCM encryption */
01703         status = CRYP_AESGCM_Process_DMA(hcryp) ;
01704         break;
01705
01706       case CRYP_AES_CCM:
01707
01708         /* AES CCM encryption */
01709         status = CRYP_AESCCM_Process_DMA(hcryp);
01710         break;
01711
01712       default:
01713         hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
01714         status = HAL_ERROR;
01715         break;
01716     }
01717   }
01718   else
01719   {
01720     /* Busy error code field */
01721     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
01722     status = HAL_ERROR;
01723   }
01724
01725   /* Return function status */
01726   return status;
01727 }
01728
01729 /**
01730   * @brief  Decryption in DMA mode.
01731   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
01732   *         the configuration information for CRYP module
01733   * @param  Input Pointer to the input buffer (ciphertext )
01734   * @param  Size Length of the plaintext buffer in word
01735   * @param  Output Pointer to the output buffer(plaintext)
01736   * @retval HAL status
01737   */
01738 HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
01739 {
01740   HAL_StatusTypeDef status;
01741   uint32_t algo;
01742 #ifdef  USE_FULL_ASSERT
01743   uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
01744
01745   /* Check input buffer size */
01746   assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
01747 #endif
01748
01749   if (hcryp->State == HAL_CRYP_STATE_READY)
01750   {
01751
01752     /* Change state Busy */
01753     hcryp->State = HAL_CRYP_STATE_BUSY;
01754
01755     /* Process locked */
01756     __HAL_LOCK(hcryp);
01757
01758     /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
01759     hcryp->CrypInCount = 0U;
01760     hcryp->CrypOutCount = 0U;
01761     hcryp->pCrypInBuffPtr = Input;
01762     hcryp->pCrypOutBuffPtr = Output;
01763
01764     /*  Calculate Size parameter in Byte*/
01765     if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
01766     {
01767       hcryp->Size = Size * 4U;
01768     }
01769     else
01770     {
01771       hcryp->Size = Size;
01772     }
01773
01774     /* Set decryption operating mode*/
01775     MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
01776
01777     /* algo get algorithm selected */
01778     algo = hcryp->Instance->CR & AES_CR_CHMOD;
01779
01780     switch (algo)
01781     {
01782
01783       case CRYP_AES_ECB:
01784       case CRYP_AES_CBC:
01785       case CRYP_AES_CTR:
01786
01787         /* AES decryption */
01788         status = CRYP_AES_Decrypt_DMA(hcryp);
01789         break;
01790
01791       case CRYP_AES_GCM_GMAC:
01792
01793         /* AES GCM decryption */
01794         status = CRYP_AESGCM_Process_DMA(hcryp) ;
01795         break;
01796
01797       case CRYP_AES_CCM:
01798
01799         /* AES CCM decryption */
01800         status = CRYP_AESCCM_Process_DMA(hcryp);
01801         break;
01802
01803       default:
01804         hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
01805         status = HAL_ERROR;
01806         break;
01807     }
01808   }
01809   else
01810   {
01811     /* Busy error code field */
01812     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
01813     status = HAL_ERROR;
01814   }
01815   /* Return function status */
01816   return status;
01817 }
01818
01819 /**
01820   * @}
01821   */
01822
01823 /** @defgroup CRYP_Exported_Functions_Group3 CRYP IRQ handler management
01824   * @brief    CRYP IRQ handler.
01825   *
01826 @verbatim
01827   ==============================================================================
01828                 ##### CRYP IRQ handler management #####
01829   ==============================================================================
01830 [..]  This section provides CRYP IRQ handler and callback functions.
01831       (+) HAL_CRYP_IRQHandler CRYP interrupt request
01832       (+) HAL_CRYP_InCpltCallback input data transfer complete callback
01833       (+) HAL_CRYP_OutCpltCallback output data transfer complete callback
01834       (+) HAL_CRYP_ErrorCallback  CRYP error callback
01835       (+) HAL_CRYP_GetState return the CRYP state
01836       (+) HAL_CRYP_GetError return the CRYP error code
01837 @endverbatim
01838   * @{
01839   */
01840
01841 /**
01842   * @brief  This function handles cryptographic interrupt request.
01843   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
01844   *         the configuration information for CRYP module
01845   * @retval None
01846   */
01847 void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
01848 {
01849
01850   /* Check if error occurred */
01851   if (__HAL_CRYP_GET_IT_SOURCE(hcryp,CRYP_IT_ERRIE) != RESET)
01852   {
01853     /* If write Error occurred */
01854     if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_IT_WRERR) != RESET)
01855     {
01856       hcryp->ErrorCode |= HAL_CRYP_ERROR_WRITE;
01857     }
01858     /* If read Error occurred */
01859     if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_IT_RDERR) != RESET)
01860     {
01861       hcryp->ErrorCode |= HAL_CRYP_ERROR_READ;
01862     }
01863   }
01864
01865   if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_CCF) != RESET)
01866   {
01867     if(__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET)
01868   {
01869     /* Clear computation complete flag */
01870     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
01871
01872     if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
01873     {
01874
01875       /* if header phase */
01876       if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER)
01877       {
01878         CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
01879       }
01880       else  /* if payload phase */
01881       {
01882         CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
01883       }
01884     }
01885     else if (hcryp->Init.Algorithm == CRYP_AES_CCM)
01886     {
01887       /* if header phase */
01888       if (hcryp->Init.HeaderSize >=  hcryp->CrypHeaderCount)
01889       {
01890         CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
01891       }
01892       else   /* if payload phase */
01893       {
01894         CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
01895       }
01896     }
01897     else  /* AES Algorithm ECB,CBC or CTR*/
01898     {
01899       CRYP_AES_IT(hcryp);
01900     }
01901   }
01902 }
01903 }
01904
01905 /**
01906   * @brief  Return the CRYP error code.
01907   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
01908   *                 the configuration information for the  CRYP peripheral
01909   * @retval CRYP error code
01910   */
01911 uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp)
01912 {
01913   return hcryp->ErrorCode;
01914 }
01915
01916 /**
01917   * @brief  Returns the CRYP state.
01918   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
01919   *         the configuration information for CRYP module.
01920   * @retval HAL state
01921   */
01922 HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
01923 {
01924   return hcryp->State;
01925 }
01926
01927 /**
01928   * @brief  Input FIFO transfer completed callback.
01929   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
01930   *         the configuration information for CRYP module.
01931   * @retval None
01932   */
01933 __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
01934 {
01935   /* Prevent unused argument(s) compilation warning */
01936   UNUSED(hcryp);
01937
01938   /* NOTE : This function Should not be modified, when the callback is needed,
01939             the HAL_CRYP_InCpltCallback could be implemented in the user file
01940    */
01941 }
01942
01943 /**
01944   * @brief  Output FIFO transfer completed callback.
01945   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
01946   *         the configuration information for CRYP module.
01947   * @retval None
01948   */
01949 __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
01950 {
01951   /* Prevent unused argument(s) compilation warning */
01952   UNUSED(hcryp);
01953
01954   /* NOTE : This function Should not be modified, when the callback is needed,
01955             the HAL_CRYP_OutCpltCallback could be implemented in the user file
01956    */
01957 }
01958
01959 /**
01960   * @brief  CRYP error callback.
01961   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
01962   *         the configuration information for CRYP module.
01963   * @retval None
01964   */
01965 __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
01966 {
01967   /* Prevent unused argument(s) compilation warning */
01968   UNUSED(hcryp);
01969
01970   /* NOTE : This function Should not be modified, when the callback is needed,
01971             the HAL_CRYP_ErrorCallback could be implemented in the user file
01972    */
01973 }
01974 /**
01975   * @}
01976   */
01977
01978 /**
01979   * @}
01980   */
01981
01982 /* Private functions ---------------------------------------------------------*/
01983 /** @addtogroup CRYP_Private_Functions
01984   * @{
01985   */
01986
01987 /**
01988   * @brief  Encryption in ECB/CBC & CTR Algorithm with AES Standard
01989   * @param  hcryp pointer to a CRYP_HandleTypeDef structure
01990   * @param  Timeout specify Timeout value
01991   * @retval HAL status
01992   */
01993 static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
01994 {
01995   uint16_t incount;  /* Temporary CrypInCount Value */
01996   uint16_t outcount;  /* Temporary CrypOutCount Value */
01997   uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
01998
01999   if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
02000   {
02001     if (hcryp->KeyIVConfig == 1U)
02002     {
02003       /* If the Key and IV configuration has to be done only once
02004          and if it has already been done, skip it */
02005       DoKeyIVConfig = 0U;
02006     }
02007     else
02008     {
02009       /* If the Key and IV configuration has to be done only once
02010          and if it has not been done already, do it and set KeyIVConfig
02011          to keep track it won't have to be done again next time */
02012       hcryp->KeyIVConfig = 1U;
02013     }
02014   }
02015
02016   if (DoKeyIVConfig == 1U)
02017   {
02018     /*  Set the Key*/
02019     CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02020
02021     if (hcryp->Init.Algorithm != CRYP_AES_ECB)
02022     {
02023       /* Set the Initialization Vector*/
02024       hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
02025       hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
02026       hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
02027       hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
02028     }
02029   } /* if (DoKeyIVConfig == 1U) */
02030
02031   /* Set the phase */
02032   hcryp->Phase = CRYP_PHASE_PROCESS;
02033
02034   /* Enable CRYP */
02035   __HAL_CRYP_ENABLE(hcryp);
02036
02037   incount = hcryp->CrypInCount;
02038   outcount = hcryp->CrypOutCount;
02039   while ((incount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
02040   {
02041     /* Write plain Ddta and get cipher data */
02042     CRYP_AES_ProcessData(hcryp, Timeout);
02043     incount = hcryp->CrypInCount;
02044     outcount = hcryp->CrypOutCount;
02045   }
02046
02047   /* Disable CRYP */
02048   __HAL_CRYP_DISABLE(hcryp);
02049
02050   /* Change the CRYP state */
02051   hcryp->State = HAL_CRYP_STATE_READY;
02052
02053   /* Return function status */
02054   return HAL_OK;
02055 }
02056
02057 /**
02058   * @brief  Encryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
02059   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
02060   *         the configuration information for CRYP module
02061   * @retval HAL status
02062   */
02063 static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp)
02064 {
02065   uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
02066
02067   if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
02068   {
02069     if (hcryp->KeyIVConfig == 1U)
02070     {
02071       /* If the Key and IV configuration has to be done only once
02072          and if it has already been done, skip it */
02073       DoKeyIVConfig = 0U;
02074     }
02075     else
02076     {
02077       /* If the Key and IV configuration has to be done only once
02078          and if it has not been done already, do it and set KeyIVConfig
02079          to keep track it won't have to be done again next time */
02080       hcryp->KeyIVConfig = 1U;
02081     }
02082   }
02083
02084   if (DoKeyIVConfig == 1U)
02085   {
02086     /*  Set the Key*/
02087     CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02088
02089     if (hcryp->Init.Algorithm != CRYP_AES_ECB)
02090     {
02091       /* Set the Initialization Vector*/
02092       hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
02093       hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
02094       hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
02095       hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
02096     }
02097   } /* if (DoKeyIVConfig == 1U) */
02098
02099   /* Set the phase */
02100   hcryp->Phase = CRYP_PHASE_PROCESS;
02101
02102   if (hcryp->Size != 0U)
02103   {
02104
02105     /* Enable computation complete flag and error interrupts */
02106     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
02107
02108     /* Enable CRYP */
02109     __HAL_CRYP_ENABLE(hcryp);
02110
02111     /* Write the input block in the IN FIFO */
02112     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02113     hcryp->CrypInCount++;
02114     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02115     hcryp->CrypInCount++;
02116     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02117     hcryp->CrypInCount++;
02118     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02119     hcryp->CrypInCount++;
02120   }
02121   else
02122   {
02123     /* Change the CRYP state */
02124     hcryp->State = HAL_CRYP_STATE_READY;
02125
02126     /* Process unlocked */
02127     __HAL_UNLOCK(hcryp);
02128   }
02129
02130   /* Return function status */
02131   return HAL_OK;
02132 }
02133
02134 /**
02135   * @brief  Decryption in ECB/CBC & CTR mode with AES Standard
02136   * @param  hcryp pointer to a CRYP_HandleTypeDef structure
02137   * @param  Timeout Specify Timeout value
02138   * @retval HAL status
02139 */
02140 static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
02141 {
02142   uint16_t incount;  /* Temporary CrypInCount Value */
02143   uint16_t outcount;  /* Temporary CrypOutCount Value */
02144   uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
02145
02146   if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
02147   {
02148     if (hcryp->KeyIVConfig == 1U)
02149     {
02150       /* If the Key and IV configuration has to be done only once
02151          and if it has already been done, skip it */
02152       DoKeyIVConfig = 0U;
02153     }
02154     else
02155     {
02156       /* If the Key and IV configuration has to be done only once
02157          and if it has not been done already, do it and set KeyIVConfig
02158          to keep track it won't have to be done again next time */
02159       hcryp->KeyIVConfig = 1U;
02160     }
02161   }
02162
02163   if (DoKeyIVConfig == 1U)
02164   {
02165     /*  Key preparation for ECB/CBC */
02166     if (hcryp->Init.Algorithm != CRYP_AES_CTR)   /*ECB or CBC*/
02167     {
02168       if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/
02169       {
02170         /* Set key preparation for decryption operating mode*/
02171         MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
02172
02173         /*  Set the Key*/
02174         CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02175
02176         /* Enable CRYP */
02177         __HAL_CRYP_ENABLE(hcryp);
02178
02179         /* Wait for CCF flag to be raised */
02180         if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
02181         {
02182           /* Disable the CRYP peripheral clock */
02183           __HAL_CRYP_DISABLE(hcryp);
02184
02185           /* Change state & error code*/
02186           hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
02187           hcryp->State = HAL_CRYP_STATE_READY;
02188
02189           /* Process unlocked */
02190           __HAL_UNLOCK(hcryp);
02191           return HAL_ERROR;
02192         }
02193         /* Clear CCF Flag */
02194         __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
02195
02196         /* Return to decryption operating mode(Mode 3)*/
02197         MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
02198       }
02199       else /*Mode 4 : decryption & Key preparation*/
02200       {
02201         /*  Set the Key*/
02202         CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02203
02204         /* Set decryption & Key preparation operating mode*/
02205         MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
02206       }
02207     }
02208     else  /*Algorithm CTR */
02209     {
02210       /*  Set the Key*/
02211       CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02212     }
02213
02214     /* Set IV */
02215     if (hcryp->Init.Algorithm != CRYP_AES_ECB)
02216     {
02217       /* Set the Initialization Vector*/
02218       hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
02219       hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
02220       hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
02221       hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
02222     }
02223   } /* if (DoKeyIVConfig == 1U) */
02224
02225   /* Set the phase */
02226   hcryp->Phase = CRYP_PHASE_PROCESS;
02227
02228   /* Enable CRYP */
02229   __HAL_CRYP_ENABLE(hcryp);
02230
02231   incount = hcryp->CrypInCount;
02232   outcount = hcryp->CrypOutCount;
02233   while ((incount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
02234   {
02235     /* Write plain data and get cipher data */
02236     CRYP_AES_ProcessData(hcryp, Timeout);
02237     incount = hcryp->CrypInCount;
02238     outcount = hcryp->CrypOutCount;
02239   }
02240
02241   /* Disable CRYP */
02242   __HAL_CRYP_DISABLE(hcryp);
02243
02244   /* Change the CRYP state */
02245   hcryp->State = HAL_CRYP_STATE_READY;
02246
02247   /* Return function status */
02248   return HAL_OK;
02249 }
02250 /**
02251   * @brief  Decryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
02252   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
02253   *         the configuration information for CRYP module
02254   * @retval HAL status
02255   */
02256 static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp)
02257 {
02258   __IO uint32_t count = 0U;
02259   uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
02260
02261   if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
02262   {
02263     if (hcryp->KeyIVConfig == 1U)
02264     {
02265       /* If the Key and IV configuration has to be done only once
02266          and if it has already been done, skip it */
02267       DoKeyIVConfig = 0U;
02268     }
02269     else
02270     {
02271       /* If the Key and IV configuration has to be done only once
02272          and if it has not been done already, do it and set KeyIVConfig
02273          to keep track it won't have to be done again next time */
02274       hcryp->KeyIVConfig = 1U;
02275     }
02276   }
02277
02278   if (DoKeyIVConfig == 1U)
02279   {
02280     /*  Key preparation for ECB/CBC */
02281     if (hcryp->Init.Algorithm != CRYP_AES_CTR)
02282     {
02283       if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/
02284       {
02285         /* Set key preparation for decryption operating mode*/
02286         MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
02287
02288         /*  Set the Key*/
02289         CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02290
02291         /* Enable CRYP */
02292         __HAL_CRYP_ENABLE(hcryp);
02293
02294         /* Wait for CCF flag to be raised */
02295         count = CRYP_TIMEOUT_KEYPREPARATION;
02296         do
02297         {
02298           count-- ;
02299           if (count == 0U)
02300           {
02301             /* Disable the CRYP peripheral clock */
02302             __HAL_CRYP_DISABLE(hcryp);
02303
02304             /* Change state */
02305             hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
02306             hcryp->State = HAL_CRYP_STATE_READY;
02307
02308             /* Process unlocked */
02309             __HAL_UNLOCK(hcryp);
02310             return HAL_ERROR;
02311           }
02312         }
02313         while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
02314
02315         /* Clear CCF Flag */
02316         __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
02317
02318         /* Return to decryption operating mode(Mode 3)*/
02319         MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
02320       }
02321       else /*Mode 4 : decryption & key preparation*/
02322       {
02323         /*  Set the Key*/
02324         CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02325
02326         /* Set decryption & key preparation operating mode*/
02327         MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
02328       }
02329     }
02330     else  /*Algorithm CTR */
02331     {
02332       /*  Set the Key*/
02333       CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02334     }
02335
02336     /* Set IV */
02337     if (hcryp->Init.Algorithm != CRYP_AES_ECB)
02338     {
02339       /* Set the Initialization Vector*/
02340       hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
02341       hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
02342       hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
02343       hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
02344     }
02345   } /* if (DoKeyIVConfig == 1U) */
02346
02347   /* Set the phase */
02348   hcryp->Phase = CRYP_PHASE_PROCESS;
02349   if (hcryp->Size != 0U)
02350   {
02351     /* Enable computation complete flag and error interrupts */
02352     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
02353
02354     /* Enable CRYP */
02355     __HAL_CRYP_ENABLE(hcryp);
02356
02357     /* Write the input block in the IN FIFO */
02358     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02359     hcryp->CrypInCount++;
02360     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02361     hcryp->CrypInCount++;
02362     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02363     hcryp->CrypInCount++;
02364     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02365     hcryp->CrypInCount++;
02366   }
02367   else
02368   {
02369     /* Process locked */
02370     __HAL_UNLOCK(hcryp);
02371
02372     /* Change the CRYP state */
02373     hcryp->State = HAL_CRYP_STATE_READY;
02374   }
02375
02376   /* Return function status */
02377   return HAL_OK;
02378 }
02379 /**
02380   * @brief  Decryption in ECB/CBC & CTR mode with AES Standard using DMA mode
02381   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
02382   *         the configuration information for CRYP module
02383   * @retval HAL status
02384   */
02385 static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp)
02386 {
02387   __IO uint32_t count = 0U;
02388   uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
02389
02390   if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
02391   {
02392     if (hcryp->KeyIVConfig == 1U)
02393     {
02394       /* If the Key and IV configuration has to be done only once
02395          and if it has already been done, skip it */
02396       DoKeyIVConfig = 0U;
02397     }
02398     else
02399     {
02400       /* If the Key and IV configuration has to be done only once
02401          and if it has not been done already, do it and set KeyIVConfig
02402          to keep track it won't have to be done again next time */
02403       hcryp->KeyIVConfig = 1U;
02404     }
02405   }
02406
02407   if (DoKeyIVConfig == 1U)
02408   {
02409     /*  Key preparation for ECB/CBC */
02410     if (hcryp->Init.Algorithm != CRYP_AES_CTR)
02411     {
02412       if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 key preparation*/
02413       {
02414         /* Set key preparation for decryption operating mode*/
02415         MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
02416
02417         /*  Set the Key*/
02418         CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02419
02420         /* Enable CRYP */
02421         __HAL_CRYP_ENABLE(hcryp);
02422
02423         /* Wait for CCF flag to be raised */
02424         count = CRYP_TIMEOUT_KEYPREPARATION;
02425         do
02426         {
02427           count-- ;
02428           if (count == 0U)
02429           {
02430             /* Disable the CRYP peripheral clock */
02431             __HAL_CRYP_DISABLE(hcryp);
02432
02433             /* Change state */
02434             hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
02435             hcryp->State = HAL_CRYP_STATE_READY;
02436
02437             /* Process unlocked */
02438             __HAL_UNLOCK(hcryp);
02439             return HAL_ERROR;
02440           }
02441         }
02442         while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
02443
02444         /* Clear CCF Flag */
02445         __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
02446
02447         /* Return to decryption operating mode(Mode 3)*/
02448         MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
02449       }
02450       else /*Mode 4 : decryption & key preparation*/
02451       {
02452         /*  Set the Key*/
02453         CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02454
02455         /* Set decryption & Key preparation operating mode*/
02456         MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
02457       }
02458     }
02459     else  /*Algorithm CTR */
02460     {
02461       /*  Set the Key*/
02462       CRYP_SetKey(hcryp, hcryp->Init.KeySize);
02463     }
02464
02465     if (hcryp->Init.Algorithm != CRYP_AES_ECB)
02466     {
02467       /* Set the Initialization Vector*/
02468       hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
02469       hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
02470       hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
02471       hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
02472     }
02473   } /* if (DoKeyIVConfig == 1U) */
02474
02475   /* Set the phase */
02476   hcryp->Phase = CRYP_PHASE_PROCESS;
02477
02478   if (hcryp->Size != 0U)
02479   {
02480     /* Set the input and output addresses and start DMA transfer */
02481     CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
02482   }
02483   else
02484   {
02485     /* Process unlocked */
02486     __HAL_UNLOCK(hcryp);
02487
02488     /* Change the CRYP state */
02489     hcryp->State = HAL_CRYP_STATE_READY;
02490   }
02491
02492   /* Return function status */
02493   return HAL_OK;
02494 }
02495
02496
02497 /**
02498   * @brief  DMA CRYP input data process complete callback.
02499   * @param  hdma DMA handle
02500   * @retval None
02501   */
02502 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
02503 {
02504   CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02505
02506   /* Stop the DMA transfers to the IN FIFO by clearing to "0" the DMAINEN */
02507   CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
02508
02509   /* Call input data transfer complete callback */
02510 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
02511   /*Call registered Input complete callback*/
02512   hcryp->InCpltCallback(hcryp);
02513 #else
02514   /*Call legacy weak Input complete callback*/
02515   HAL_CRYP_InCpltCallback(hcryp);
02516 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
02517 }
02518
02519 /**
02520   * @brief  DMA CRYP output data process complete callback.
02521   * @param  hdma DMA handle
02522   * @retval None
02523   */
02524 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
02525 {
02526   uint32_t count;
02527   uint32_t npblb;
02528   uint32_t lastwordsize;
02529   uint32_t temp;  /* Temporary CrypOutBuff */
02530   uint32_t mode;
02531
02532   CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02533
02534   /* Stop the DMA transfers to the OUT FIFO by clearing to "0" the DMAOUTEN */
02535   CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);
02536
02537   /* Clear CCF flag */
02538   __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
02539
02540   /* Last block transfer in case of GCM or CCM with Size not %16*/
02541   if (((hcryp->Size) % 16U) != 0U)
02542   {
02543     /* set CrypInCount and CrypOutCount to exact number of word already computed via DMA  */
02544     hcryp->CrypInCount = (hcryp->Size / 16U) * 4U;
02545     hcryp->CrypOutCount = hcryp->CrypInCount;
02546
02547     /* Compute the number of padding bytes in last block of payload */
02548     npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - ((uint32_t)hcryp->Size);
02549
02550     mode = hcryp->Instance->CR & AES_CR_MODE;
02551     if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) ||
02552         ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
02553     {
02554       /* Specify the number of non-valid bytes using NPBLB register*/
02555       MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
02556     }
02557
02558     /* Number of valid words (lastwordsize) in last block */
02559     if ((npblb % 4U) == 0U)
02560     {
02561       lastwordsize = (16U - npblb) / 4U;
02562     }
02563     else
02564     {
02565       lastwordsize = ((16U - npblb) / 4U) + 1U;
02566     }
02567
02568     /*  Last block optionally pad the data with zeros*/
02569     for (count = 0U; count < lastwordsize; count++)
02570     {
02571       hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02572       hcryp->CrypInCount++;
02573     }
02574     while (count < 4U)
02575     {
02576       /* Pad the data with zeros to have a complete block */
02577       hcryp->Instance->DINR = 0x0U;
02578       count++;
02579     }
02580
02581     /*Wait on CCF flag*/
02582     count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
02583     do
02584     {
02585       count-- ;
02586       if (count == 0U)
02587       {
02588         /* Disable the CRYP peripheral clock */
02589         __HAL_CRYP_DISABLE(hcryp);
02590
02591         /* Change state */
02592         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
02593         hcryp->State = HAL_CRYP_STATE_READY;
02594
02595         /* Process unlocked */
02596         __HAL_UNLOCK(hcryp);
02597
02598 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
02599         /*Call registered error callback*/
02600         hcryp->ErrorCallback(hcryp);
02601 #else
02602         /*Call legacy weak error callback*/
02603         HAL_CRYP_ErrorCallback(hcryp);
02604 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
02605       }
02606     }
02607     while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
02608
02609     /* Clear CCF flag */
02610     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
02611
02612     /*Read the output block from the output FIFO */
02613     for (count = 0U; count < 4U; count++)
02614     {
02615       /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
02616       temp = hcryp->Instance->DOUTR;
02617
02618       *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
02619       hcryp->CrypOutCount++;
02620     }
02621   }
02622
02623   if (((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC) && ((hcryp->Init.Algorithm & CRYP_AES_CCM) != CRYP_AES_CCM))
02624   {
02625     /* Disable CRYP (not allowed in  GCM)*/
02626     __HAL_CRYP_DISABLE(hcryp);
02627   }
02628
02629   /* Change the CRYP state to ready */
02630   hcryp->State = HAL_CRYP_STATE_READY;
02631
02632   /* Process unlocked */
02633   __HAL_UNLOCK(hcryp);
02634
02635   /* Call output data transfer complete callback */
02636 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
02637   /*Call registered Output complete callback*/
02638   hcryp->OutCpltCallback(hcryp);
02639 #else
02640   /*Call legacy weak Output complete callback*/
02641   HAL_CRYP_OutCpltCallback(hcryp);
02642 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
02643 }
02644
02645 /**
02646   * @brief  DMA CRYP communication error callback.
02647   * @param  hdma DMA handle
02648   * @retval None
02649   */
02650 static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
02651 {
02652   CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02653
02654   /* Change the CRYP peripheral state */
02655   hcryp->State = HAL_CRYP_STATE_READY;
02656
02657   /* DMA error code field */
02658   hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
02659
02660   /* Clear CCF flag */
02661   __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
02662
02663   /* Call error callback */
02664 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
02665   /*Call registered error callback*/
02666   hcryp->ErrorCallback(hcryp);
02667 #else
02668   /*Call legacy weak error callback*/
02669   HAL_CRYP_ErrorCallback(hcryp);
02670 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
02671 }
02672
02673 /**
02674   * @brief  Set the DMA configuration and start the DMA transfer
02675   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
02676   *         the configuration information for CRYP module
02677   * @param  inputaddr address of the input buffer
02678   * @param  Size size of the input buffer, must be a multiple of 16.
02679   * @param  outputaddr address of the output buffer
02680   * @retval None
02681   */
02682 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
02683 {
02684   /* Set the CRYP DMA transfer complete callback */
02685   hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
02686
02687   /* Set the DMA input error callback */
02688   hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
02689
02690   /* Set the CRYP DMA transfer complete callback */
02691   hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
02692
02693   /* Set the DMA output error callback */
02694   hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
02695
02696   if ((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC)
02697   {
02698     /* Enable CRYP (not allowed in  GCM & CCM)*/
02699     __HAL_CRYP_ENABLE(hcryp);
02700   }
02701
02702   /* Enable the DMA input stream */
02703   if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size) != HAL_OK)
02704   {
02705     /* DMA error code field */
02706     hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
02707
02708     /* Call error callback */
02709 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
02710     /*Call registered error callback*/
02711     hcryp->ErrorCallback(hcryp);
02712 #else
02713     /*Call legacy weak error callback*/
02714     HAL_CRYP_ErrorCallback(hcryp);
02715 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
02716   }
02717   /* Enable the DMA output stream */
02718   if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size) != HAL_OK)
02719   {
02720     /* DMA error code field */
02721     hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
02722
02723     /* Call error callback */
02724 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
02725     /*Call registered error callback*/
02726     hcryp->ErrorCallback(hcryp);
02727 #else
02728     /*Call legacy weak error callback*/
02729     HAL_CRYP_ErrorCallback(hcryp);
02730 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
02731   }
02732   /* Enable In and Out DMA requests */
02733   SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN));
02734 }
02735
02736 /**
02737   * @brief  Process Data: Write Input data in polling mode and used in AES functions.
02738   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
02739   *         the configuration information for CRYP module
02740   * @param  Timeout Specify Timeout value
02741   * @retval None
02742   */
02743 static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
02744 {
02745
02746   uint32_t temp;  /* Temporary CrypOutBuff */
02747
02748   /* Write the input block in the IN FIFO */
02749   hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02750   hcryp->CrypInCount++;
02751   hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02752   hcryp->CrypInCount++;
02753   hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02754   hcryp->CrypInCount++;
02755   hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02756   hcryp->CrypInCount++;
02757
02758   /* Wait for CCF flag to be raised */
02759   if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
02760   {
02761     /* Disable the CRYP peripheral clock */
02762     __HAL_CRYP_DISABLE(hcryp);
02763
02764     /* Change state */
02765     hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
02766     hcryp->State = HAL_CRYP_STATE_READY;
02767
02768     /* Process unlocked */
02769     __HAL_UNLOCK(hcryp);
02770     /*Call registered error callback*/
02771 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
02772     hcryp->ErrorCallback(hcryp);
02773 #else
02774     /*Call legacy weak error callback*/
02775     HAL_CRYP_ErrorCallback(hcryp);
02776 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
02777   }
02778
02779   /* Clear CCF Flag */
02780   __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
02781
02782   /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
02783   temp  = hcryp->Instance->DOUTR;
02784   *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
02785   hcryp->CrypOutCount++;
02786   temp  = hcryp->Instance->DOUTR;
02787   *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount)   = temp;
02788   hcryp->CrypOutCount++;
02789   temp  = hcryp->Instance->DOUTR;
02790   *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
02791   hcryp->CrypOutCount++;
02792   temp  = hcryp->Instance->DOUTR;
02793   *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount)   = temp;
02794   hcryp->CrypOutCount++;
02795
02796 }
02797
02798 /**
02799   * @brief  Handle CRYP block input/output data handling under interruption.
02800   * @note   The function is called under interruption only, once
02801   *         interruptions have been enabled by HAL_CRYP_Encrypt_IT or HAL_CRYP_Decrypt_IT.
02802   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
02803   *         the configuration information for CRYP module.
02804   * @retval HAL status
02805   */
02806 static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
02807 {
02808   uint32_t temp;  /* Temporary CrypOutBuff */
02809
02810   if (hcryp->State == HAL_CRYP_STATE_BUSY)
02811   {
02812     /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
02813     temp  = hcryp->Instance->DOUTR;
02814     *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
02815     hcryp->CrypOutCount++;
02816     temp  = hcryp->Instance->DOUTR;
02817     *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount)   = temp;
02818     hcryp->CrypOutCount++;
02819     temp  = hcryp->Instance->DOUTR;
02820     *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
02821     hcryp->CrypOutCount++;
02822     temp  = hcryp->Instance->DOUTR;
02823     *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount)   = temp;
02824     hcryp->CrypOutCount++;
02825
02826     if (hcryp->CrypOutCount ==  (hcryp->Size / 4U))
02827     {
02828       /* Disable Computation Complete flag and errors interrupts */
02829       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
02830
02831       /* Change the CRYP state */
02832       hcryp->State = HAL_CRYP_STATE_READY;
02833
02834       /* Disable CRYP */
02835       __HAL_CRYP_DISABLE(hcryp);
02836
02837       /* Process Unlocked */
02838       __HAL_UNLOCK(hcryp);
02839
02840       /* Call Output transfer complete callback */
02841 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
02842       /*Call registered Output complete callback*/
02843       hcryp->OutCpltCallback(hcryp);
02844 #else
02845       /*Call legacy weak Output complete callback*/
02846       HAL_CRYP_OutCpltCallback(hcryp);
02847 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
02848     }
02849     else
02850     {
02851 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
02852       /* If suspension flag has been raised, suspend processing
02853          only if not already at the end of the payload */
02854       if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
02855       {
02856         /* Clear CCF Flag */
02857         __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
02858
02859         /* reset SuspendRequest */
02860         hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
02861         /* Disable Computation Complete Flag and Errors Interrupts */
02862         __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE);
02863         /* Change the CRYP state */
02864         hcryp->State = HAL_CRYP_STATE_SUSPENDED;
02865         /* Mark that the payload phase is suspended */
02866         hcryp->Phase = CRYP_PHASE_PAYLOAD_SUSPENDED;
02867
02868        /* Process Unlocked */
02869         __HAL_UNLOCK(hcryp);
02870       }
02871       else
02872 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
02873       {
02874         /* Write the input block in the IN FIFO */
02875         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02876         hcryp->CrypInCount++;
02877         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02878         hcryp->CrypInCount++;
02879         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02880         hcryp->CrypInCount++;
02881         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
02882         hcryp->CrypInCount++;
02883
02884         if (hcryp->CrypInCount ==  (hcryp->Size / 4U))
02885         {
02886           /* Call Input transfer complete callback */
02887 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
02888           /*Call registered Input complete callback*/
02889           hcryp->InCpltCallback(hcryp);
02890 #else
02891           /*Call legacy weak Input complete callback*/
02892           HAL_CRYP_InCpltCallback(hcryp);
02893 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
02894         }
02895       }
02896     }
02897   }
02898   else
02899   {
02900     /* Busy error code field */
02901     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
02902 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
02903     /*Call registered error callback*/
02904     hcryp->ErrorCallback(hcryp);
02905 #else
02906     /*Call legacy weak error callback*/
02907     HAL_CRYP_ErrorCallback(hcryp);
02908 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
02909   }
02910 }
02911
02912 /**
02913   * @brief  Writes Key in Key registers.
02914   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
02915   *         the configuration information for CRYP module
02916   * @param  KeySize Size of Key
02917   * @note   If pKey is NULL, the Key registers are not written. This configuration
02918   *         occurs when the key is written out of HAL scope.
02919   * @retval None
02920   */
02921 static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize)
02922 {
02923   if (hcryp->Init.pKey != NULL)
02924   {
02925     switch (KeySize)
02926     {
02927       case CRYP_KEYSIZE_256B:
02928         hcryp->Instance->KEYR7 = *(uint32_t *)(hcryp->Init.pKey);
02929         hcryp->Instance->KEYR6 = *(uint32_t *)(hcryp->Init.pKey + 1U);
02930         hcryp->Instance->KEYR5 = *(uint32_t *)(hcryp->Init.pKey + 2U);
02931         hcryp->Instance->KEYR4 = *(uint32_t *)(hcryp->Init.pKey + 3U);
02932         hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey + 4U);
02933         hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 5U);
02934         hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 6U);
02935         hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 7U);
02936         break;
02937       case CRYP_KEYSIZE_128B:
02938         hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey);
02939         hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 1U);
02940         hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 2U);
02941         hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 3U);
02942
02943         break;
02944       default:
02945         break;
02946     }
02947   }
02948 }
02949
02950 /**
02951   * @brief  Encryption/Decryption process in AES GCM mode and prepare the authentication TAG
02952   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
02953   *         the configuration information for CRYP module
02954   * @param  Timeout Timeout duration
02955   * @retval HAL status
02956   */
02957 static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
02958 {
02959   uint32_t tickstart;
02960   uint32_t wordsize = ((uint32_t)hcryp->Size / 4U) ;
02961   uint32_t npblb;
02962   uint32_t temp;  /* Temporary CrypOutBuff */
02963   uint32_t index;
02964   uint32_t lastwordsize;
02965   uint32_t incount;  /* Temporary CrypInCount Value */
02966   uint32_t outcount;  /* Temporary CrypOutCount Value */
02967   uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
02968
02969   if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
02970   {
02971     if (hcryp->KeyIVConfig == 1U)
02972     {
02973       /* If the Key and IV configuration has to be done only once
02974          and if it has already been done, skip it */
02975       DoKeyIVConfig = 0U;
02976       hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
02977     }
02978     else
02979     {
02980       /* If the Key and IV configuration has to be done only once
02981          and if it has not been done already, do it and set KeyIVConfig
02982          to keep track it won't have to be done again next time */
02983       hcryp->KeyIVConfig = 1U;
02984       hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
02985     }
02986   }
02987   else
02988   {
02989     hcryp->SizesSum = hcryp->Size;
02990   }
02991
02992   if (DoKeyIVConfig == 1U)
02993   {
02994
02995     /*  Reset CrypHeaderCount */
02996     hcryp->CrypHeaderCount = 0U;
02997
02998     /****************************** Init phase **********************************/
02999
03000     CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
03001
03002     /* Set the key */
03003     CRYP_SetKey(hcryp, hcryp->Init.KeySize);
03004
03005     /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
03006     hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
03007     hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
03008     hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
03009     hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
03010
03011     /* Enable the CRYP peripheral */
03012     __HAL_CRYP_ENABLE(hcryp);
03013
03014     /* just wait for hash computation */
03015     if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
03016     {
03017       /* Change state */
03018       hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03019       hcryp->State = HAL_CRYP_STATE_READY;
03020
03021       /* Process unlocked & return error */
03022       __HAL_UNLOCK(hcryp);
03023       return HAL_ERROR;
03024     }
03025     /* Clear CCF flag */
03026     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
03027
03028     /************************ Header phase *************************************/
03029
03030     if (CRYP_GCMCCM_SetHeaderPhase(hcryp,  Timeout) != HAL_OK)
03031     {
03032       return HAL_ERROR;
03033     }
03034
03035     /*************************Payload phase ************************************/
03036
03037     /* Set the phase */
03038     hcryp->Phase = CRYP_PHASE_PROCESS;
03039
03040     /* Select payload phase once the header phase is performed */
03041     CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
03042
03043     /* Set to 0 the number of non-valid bytes using NPBLB register*/
03044     MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
03045
03046   } /* if (DoKeyIVConfig == 1U) */
03047
03048   if ((hcryp->Size % 16U) != 0U)
03049   {
03050     /* recalculate  wordsize */
03051     wordsize = ((wordsize / 4U) * 4U) ;
03052   }
03053
03054   /* Get tick */
03055   tickstart = HAL_GetTick();
03056
03057   /* Write input data and get output Data */
03058   incount = hcryp->CrypInCount;
03059   outcount = hcryp->CrypOutCount;
03060   while ((incount < wordsize) && (outcount < wordsize))
03061   {
03062     /* Write plain data and get cipher data */
03063     CRYP_AES_ProcessData(hcryp, Timeout);
03064
03065     /* Check for the Timeout */
03066     if (Timeout != HAL_MAX_DELAY)
03067     {
03068       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
03069       {
03070         /* Disable the CRYP peripheral clock */
03071         __HAL_CRYP_DISABLE(hcryp);
03072
03073         /* Change state & error code */
03074         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03075         hcryp->State = HAL_CRYP_STATE_READY;
03076
03077         /* Process unlocked */
03078         __HAL_UNLOCK(hcryp);
03079         return HAL_ERROR;
03080       }
03081     }
03082     incount = hcryp->CrypInCount;
03083     outcount = hcryp->CrypOutCount;
03084   }
03085
03086   if ((hcryp->Size % 16U) != 0U)
03087   {
03088     /* Compute the number of padding bytes in last block of payload */
03089     npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - ((uint32_t)hcryp->Size);
03090
03091     /*  Set Npblb in case of AES GCM payload encryption to get right tag*/
03092     if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
03093     {
03094       /* Set to 0 the number of non-valid bytes using NPBLB register*/
03095       MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
03096     }
03097     /* Number of valid words (lastwordsize) in last block */
03098     if ((npblb % 4U) == 0U)
03099     {
03100       lastwordsize = (16U - npblb) / 4U;
03101     }
03102     else
03103     {
03104       lastwordsize = ((16U - npblb) / 4U) + 1U;
03105     }
03106     /*  last block optionally pad the data with zeros*/
03107     for (index = 0U; index < lastwordsize; index ++)
03108     {
03109       /* Write the last Input block in the IN FIFO */
03110       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03111       hcryp->CrypInCount++;
03112     }
03113     while (index < 4U)
03114     {
03115       /* pad the data with zeros to have a complete block */
03116       hcryp->Instance->DINR  = 0U;
03117       index++;
03118     }
03119     /* Wait for CCF flag to be raised */
03120     if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
03121     {
03122       hcryp->State = HAL_CRYP_STATE_READY;
03123       __HAL_UNLOCK(hcryp);
03124
03125 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
03126       /*Call registered error callback*/
03127       hcryp->ErrorCallback(hcryp);
03128 #else
03129       /*Call legacy weak error callback*/
03130       HAL_CRYP_ErrorCallback(hcryp);
03131 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
03132     }
03133
03134     /* Clear CCF Flag */
03135     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
03136
03137     /*Read the output block from the output FIFO */
03138     for (index = 0U; index < 4U; index++)
03139     {
03140       /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
03141       temp = hcryp->Instance->DOUTR;
03142
03143       *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
03144       hcryp->CrypOutCount++;
03145     }
03146   }
03147
03148   /* Return function status */
03149   return HAL_OK;
03150 }
03151
03152 /**
03153   * @brief  Encryption/Decryption process in AES GCM mode and prepare the authentication TAG in interrupt mode
03154   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
03155   *         the configuration information for CRYP module
03156   * @retval HAL status
03157   */
03158 static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
03159 {
03160   __IO uint32_t count = 0U;
03161   uint32_t loopcounter;
03162   uint32_t lastwordsize;
03163   uint32_t npblb;
03164   uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
03165
03166 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
03167   if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED))
03168   {
03169     CRYP_PhaseProcessingResume(hcryp);
03170     return HAL_OK;
03171   }
03172 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
03173
03174   if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
03175   {
03176     if (hcryp->KeyIVConfig == 1U)
03177     {
03178       /* If the Key and IV configuration has to be done only once
03179          and if it has already been done, skip it */
03180       DoKeyIVConfig = 0U;
03181       hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
03182     }
03183     else
03184     {
03185       /* If the Key and IV configuration has to be done only once
03186          and if it has not been done already, do it and set KeyIVConfig
03187          to keep track it won't have to be done again next time */
03188       hcryp->KeyIVConfig = 1U;
03189       hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
03190     }
03191   }
03192   else
03193   {
03194     hcryp->SizesSum = hcryp->Size;
03195   }
03196
03197   /* Configure Key, IV and process message (header and payload) */
03198   if (DoKeyIVConfig == 1U)
03199   {
03200     /*  Reset CrypHeaderCount */
03201     hcryp->CrypHeaderCount = 0U;
03202
03203     /******************************* Init phase *********************************/
03204
03205     CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
03206
03207     /* Set the key */
03208     CRYP_SetKey(hcryp, hcryp->Init.KeySize);
03209
03210     /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
03211     hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
03212     hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
03213     hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
03214     hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
03215
03216     /* Enable the CRYP peripheral */
03217     __HAL_CRYP_ENABLE(hcryp);
03218
03219     /* just wait for hash computation */
03220     count = CRYP_TIMEOUT_GCMCCMINITPHASE;
03221     do
03222     {
03223       count-- ;
03224       if (count == 0U)
03225       {
03226         /* Disable the CRYP peripheral clock */
03227         __HAL_CRYP_DISABLE(hcryp);
03228
03229         /* Change state */
03230         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03231         hcryp->State = HAL_CRYP_STATE_READY;
03232
03233         /* Process unlocked */
03234         __HAL_UNLOCK(hcryp);
03235         return HAL_ERROR;
03236       }
03237     }
03238     while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
03239
03240     /* Clear CCF flag */
03241     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
03242
03243     /***************************** Header phase *********************************/
03244
03245     /* Select header phase */
03246     CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
03247
03248     /* Enable computation complete flag and error interrupts */
03249     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
03250
03251     /* Enable the CRYP peripheral */
03252     __HAL_CRYP_ENABLE(hcryp);
03253
03254     if (hcryp->Init.HeaderSize == 0U) /*header phase is  skipped*/
03255     {
03256       /* Set the phase */
03257       hcryp->Phase = CRYP_PHASE_PROCESS;
03258
03259       /* Select payload phase once the header phase is performed */
03260       MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
03261
03262       /* Set to 0 the number of non-valid bytes using NPBLB register*/
03263       MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
03264
03265       /* Write the payload Input block in the IN FIFO */
03266       if (hcryp->Size == 0U)
03267       {
03268         /* Disable interrupts */
03269         __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
03270
03271         /* Change the CRYP state */
03272         hcryp->State = HAL_CRYP_STATE_READY;
03273
03274         /* Process unlocked */
03275         __HAL_UNLOCK(hcryp);
03276       }
03277       else if (hcryp->Size >= 16U)
03278       {
03279         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03280         hcryp->CrypInCount++;
03281         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03282         hcryp->CrypInCount++;
03283         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03284         hcryp->CrypInCount++;
03285         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03286         hcryp->CrypInCount++;
03287         if (hcryp->CrypInCount ==  (hcryp->Size / 4U))
03288         {
03289           /* Call Input transfer complete callback */
03290 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
03291           /*Call registered Input complete callback*/
03292           hcryp->InCpltCallback(hcryp);
03293 #else
03294           /*Call legacy weak Input complete callback*/
03295           HAL_CRYP_InCpltCallback(hcryp);
03296 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
03297         }
03298       }
03299       else /* Size < 16Bytes  : first block is the last block*/
03300       {
03301         /* Workaround not implemented for TinyAES2*/
03302         /* Size should be %4  otherwise Tag will  be incorrectly generated for GCM Encryption:
03303         Workaround is implemented in polling mode, so if last block of
03304         payload <128bit do not use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
03305
03306
03307         /* Compute the number of padding bytes in last block of payload */
03308         npblb = 16U - ((uint32_t)hcryp->Size);
03309
03310         if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
03311         {
03312           /* Set to 0 the number of non-valid bytes using NPBLB register*/
03313           MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
03314         }
03315
03316         /* Number of valid words (lastwordsize) in last block */
03317         if ((npblb % 4U) == 0U)
03318         {
03319           lastwordsize = (16U - npblb) / 4U;
03320         }
03321         else
03322         {
03323           lastwordsize = ((16U - npblb) / 4U) + 1U;
03324         }
03325
03326         /*  last block optionally pad the data with zeros*/
03327         for (loopcounter = 0U; loopcounter < lastwordsize ; loopcounter++)
03328         {
03329           hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03330           hcryp->CrypInCount++;
03331         }
03332         while (loopcounter < 4U)
03333         {
03334           /* pad the data with zeros to have a complete block */
03335           hcryp->Instance->DINR = 0x0U;
03336           loopcounter++;
03337         }
03338       }
03339     }
03340     else if ((hcryp->Init.HeaderSize) < 4U)
03341     {
03342       for (loopcounter = 0U; loopcounter < hcryp->Init.HeaderSize ; loopcounter++)
03343       {
03344         hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
03345         hcryp->CrypHeaderCount++ ;
03346       }
03347       while (loopcounter < 4U)
03348       {
03349         /* pad the data with zeros to have a complete block */
03350         hcryp->Instance->DINR = 0x0U;
03351         loopcounter++;
03352       }
03353       /* Set the phase */
03354       hcryp->Phase = CRYP_PHASE_PROCESS;
03355
03356       /* Select payload phase once the header phase is performed */
03357       CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
03358
03359       /* Set to 0 the number of non-valid bytes using NPBLB register*/
03360       MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
03361
03362       /* Call Input transfer complete callback */
03363 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
03364       /*Call registered Input complete callback*/
03365       hcryp->InCpltCallback(hcryp);
03366 #else
03367       /*Call legacy weak Input complete callback*/
03368       HAL_CRYP_InCpltCallback(hcryp);
03369 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
03370     }
03371     else
03372     {
03373       /* Write the input block in the IN FIFO */
03374       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
03375       hcryp->CrypHeaderCount++;
03376       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
03377       hcryp->CrypHeaderCount++;
03378       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
03379       hcryp->CrypHeaderCount++;
03380       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
03381       hcryp->CrypHeaderCount++;
03382     }
03383
03384   } /* end of if (DoKeyIVConfig == 1U) */
03385   else  /* Key and IV have already been configured,
03386           header has already been processed;
03387           only process here message payload */
03388   {
03389
03390     /* Enable computation complete flag and error interrupts */
03391     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
03392
03393     /* Set to 0 the number of non-valid bytes using NPBLB register*/
03394     MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
03395
03396     /* Write the payload Input block in the IN FIFO */
03397     if (hcryp->Size == 0U)
03398     {
03399       /* Disable interrupts */
03400       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
03401
03402       /* Change the CRYP state */
03403       hcryp->State = HAL_CRYP_STATE_READY;
03404
03405       /* Process unlocked */
03406       __HAL_UNLOCK(hcryp);
03407     }
03408     else if (hcryp->Size >= 16U)
03409     {
03410       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03411       hcryp->CrypInCount++;
03412       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03413       hcryp->CrypInCount++;
03414       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03415       hcryp->CrypInCount++;
03416       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03417       hcryp->CrypInCount++;
03418       if (hcryp->CrypInCount ==  (hcryp->Size / 4U))
03419       {
03420         /* Call Input transfer complete callback */
03421 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
03422         /*Call registered Input complete callback*/
03423         hcryp->InCpltCallback(hcryp);
03424 #else
03425         /*Call legacy weak Input complete callback*/
03426         HAL_CRYP_InCpltCallback(hcryp);
03427 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
03428       }
03429     }
03430     else /* Size < 16Bytes  : first block is the last block*/
03431     {
03432       /* Workaround not implemented for TinyAES2*/
03433       /* Size should be %4  otherwise Tag will  be incorrectly generated for GCM Encryption:
03434       Workaround is implemented in polling mode, so if last block of
03435       payload <128bit do not use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
03436
03437
03438       /* Compute the number of padding bytes in last block of payload */
03439       npblb = 16U - ((uint32_t)hcryp->Size);
03440
03441       if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
03442       {
03443         /* Set to 0 the number of non-valid bytes using NPBLB register*/
03444         MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
03445       }
03446
03447       /* Number of valid words (lastwordsize) in last block */
03448       if ((npblb % 4U) == 0U)
03449       {
03450         lastwordsize = (16U - npblb) / 4U;
03451       }
03452       else
03453       {
03454         lastwordsize = ((16U - npblb) / 4U) + 1U;
03455       }
03456
03457       /*  last block optionally pad the data with zeros*/
03458       for (loopcounter = 0U; loopcounter < lastwordsize ; loopcounter++)
03459       {
03460         hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03461         hcryp->CrypInCount++;
03462       }
03463       while (loopcounter < 4U)
03464       {
03465         /* pad the data with zeros to have a complete block */
03466         hcryp->Instance->DINR = 0x0U;
03467         loopcounter++;
03468       }
03469     }
03470   }
03471
03472   /* Return function status */
03473   return HAL_OK;
03474 }
03475
03476
03477 /**
03478   * @brief  Encryption/Decryption process in AES GCM mode and prepare the authentication TAG using DMA
03479   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
03480   *         the configuration information for CRYP module
03481   * @retval HAL status
03482   */
03483 static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
03484 {
03485   __IO uint32_t count;
03486   uint16_t wordsize = hcryp->Size / 4U ;
03487   uint32_t index;
03488   uint32_t npblb;
03489   uint32_t lastwordsize;
03490   uint32_t temp;  /* Temporary CrypOutBuff */
03491   uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
03492
03493   if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
03494   {
03495     if (hcryp->KeyIVConfig == 1U)
03496     {
03497       /* If the Key and IV configuration has to be done only once
03498          and if it has already been done, skip it */
03499       DoKeyIVConfig = 0U;
03500       hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
03501     }
03502     else
03503     {
03504       /* If the Key and IV configuration has to be done only once
03505          and if it has not been done already, do it and set KeyIVConfig
03506          to keep track it won't have to be done again next time */
03507       hcryp->KeyIVConfig = 1U;
03508       hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
03509     }
03510   }
03511   else
03512   {
03513     hcryp->SizesSum = hcryp->Size;
03514   }
03515
03516   if (DoKeyIVConfig == 1U)
03517   {
03518
03519     /*  Reset CrypHeaderCount */
03520     hcryp->CrypHeaderCount = 0U;
03521
03522     /*************************** Init phase ************************************/
03523
03524     CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
03525
03526     /* Set the key */
03527     CRYP_SetKey(hcryp, hcryp->Init.KeySize);
03528
03529     /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
03530     hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
03531     hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
03532     hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
03533     hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
03534
03535     /* Enable the CRYP peripheral */
03536     __HAL_CRYP_ENABLE(hcryp);
03537
03538     /* just wait for hash computation */
03539     count = CRYP_TIMEOUT_GCMCCMINITPHASE;
03540     do
03541     {
03542       count-- ;
03543       if (count == 0U)
03544       {
03545         /* Disable the CRYP peripheral clock */
03546         __HAL_CRYP_DISABLE(hcryp);
03547
03548         /* Change state */
03549         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03550         hcryp->State = HAL_CRYP_STATE_READY;
03551
03552         /* Process unlocked */
03553         __HAL_UNLOCK(hcryp);
03554         return HAL_ERROR;
03555       }
03556     }
03557     while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
03558
03559     /* Clear CCF flag */
03560     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
03561
03562     /************************ Header phase *************************************/
03563
03564     if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
03565     {
03566       return HAL_ERROR;
03567     }
03568
03569     /************************ Payload phase ************************************/
03570
03571     /* Set the phase */
03572     hcryp->Phase = CRYP_PHASE_PROCESS;
03573
03574     /* Set to 0 the number of non-valid bytes using NPBLB register*/
03575     MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
03576
03577     /* Select payload phase once the header phase is performed */
03578     CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
03579
03580   } /* if (DoKeyIVConfig == 1U) */
03581
03582   if (hcryp->Size == 0U)
03583   {
03584     /* Process unLocked */
03585     __HAL_UNLOCK(hcryp);
03586
03587     /* Change the CRYP state and phase */
03588     hcryp->State = HAL_CRYP_STATE_READY;
03589   }
03590   else if (hcryp->Size >= 16U)
03591   {
03592     /*DMA transfer must not include the last block in case of Size is not %16 */
03593     wordsize = wordsize - (wordsize % 4U);
03594
03595     /*DMA transfer */
03596     CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), wordsize, (uint32_t)(hcryp->pCrypOutBuffPtr));
03597   }
03598   else /* length of input data is < 16 */
03599   {
03600     /* Compute the number of padding bytes in last block of payload */
03601     npblb = 16U - (uint32_t)hcryp->Size;
03602
03603     /* Set Npblb in case of AES GCM payload encryption to get right tag*/
03604     if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
03605     {
03606       /* Specify the number of non-valid bytes using NPBLB register*/
03607       MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
03608     }
03609
03610     /* Enable CRYP to start the final phase */
03611     __HAL_CRYP_ENABLE(hcryp);
03612
03613     /* Number of valid words (lastwordsize) in last block */
03614     if ((npblb % 4U) == 0U)
03615     {
03616       lastwordsize = (16U - npblb) / 4U;
03617     }
03618     else
03619     {
03620       lastwordsize = ((16U - npblb) / 4U) + 1U;
03621     }
03622
03623     /*  last block optionally pad the data with zeros*/
03624     for (index = 0U; index < lastwordsize; index ++)
03625     {
03626       /* Write the last Input block in the IN FIFO */
03627       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03628       hcryp->CrypInCount++;
03629     }
03630     while (index < 4U)
03631     {
03632       /* pad the data with zeros to have a complete block */
03633       hcryp->Instance->DINR  = 0U;
03634       index++;
03635     }
03636     /* Wait for CCF flag to be raised */
03637     count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
03638     do
03639     {
03640       count-- ;
03641       if (count == 0U)
03642       {
03643         /* Disable the CRYP peripheral clock */
03644         __HAL_CRYP_DISABLE(hcryp);
03645
03646         /* Change state */
03647         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03648         hcryp->State = HAL_CRYP_STATE_READY;
03649
03650         /* Process unlocked */
03651         __HAL_UNLOCK(hcryp);
03652 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
03653         /*Call registered error callback*/
03654         hcryp->ErrorCallback(hcryp);
03655 #else
03656         /*Call legacy weak error callback*/
03657         HAL_CRYP_ErrorCallback(hcryp);
03658 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
03659       }
03660     }
03661     while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
03662
03663     /* Clear CCF Flag */
03664     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
03665
03666     /*Read the output block from the output FIFO */
03667     for (index = 0U; index < 4U; index++)
03668     {
03669       /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
03670       temp = hcryp->Instance->DOUTR;
03671
03672       *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
03673       hcryp->CrypOutCount++;
03674     }
03675
03676     /* Change the CRYP state to ready */
03677     hcryp->State = HAL_CRYP_STATE_READY;
03678
03679     /* Process unlocked */
03680     __HAL_UNLOCK(hcryp);
03681   }
03682
03683   /* Return function status */
03684   return HAL_OK;
03685 }
03686
03687
03688 /**
03689   * @brief  AES CCM encryption/decryption processing in polling mode
03690   *         for TinyAES peripheral, no encrypt/decrypt performed, only authentication preparation.
03691   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
03692   *         the configuration information for CRYP module
03693   * @param  Timeout Timeout duration
03694   * @retval HAL status
03695   */
03696 static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
03697 {
03698   uint32_t tickstart;
03699   uint32_t wordsize = ((uint32_t)hcryp->Size / 4U) ;
03700   uint32_t loopcounter;
03701   uint32_t npblb;
03702   uint32_t lastwordsize;
03703   uint32_t temp;  /* Temporary CrypOutBuff */
03704   uint32_t incount;  /* Temporary CrypInCount Value */
03705   uint32_t outcount;  /* Temporary CrypOutCount Value */
03706   uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
03707
03708   if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
03709   {
03710     if (hcryp->KeyIVConfig == 1U)
03711     {
03712       /* If the Key and IV configuration has to be done only once
03713          and if it has already been done, skip it */
03714       DoKeyIVConfig = 0U;
03715       hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
03716     }
03717     else
03718     {
03719       /* If the Key and IV configuration has to be done only once
03720          and if it has not been done already, do it and set KeyIVConfig
03721          to keep track it won't have to be done again next time */
03722       hcryp->KeyIVConfig = 1U;
03723       hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
03724     }
03725   }
03726   else
03727   {
03728     hcryp->SizesSum = hcryp->Size;
03729   }
03730
03731   if (DoKeyIVConfig == 1U)
03732   {
03733     /*  Reset CrypHeaderCount */
03734     hcryp->CrypHeaderCount = 0U;
03735
03736     /********************** Init phase ******************************************/
03737
03738     CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
03739
03740     /* Set the key */
03741     CRYP_SetKey(hcryp, hcryp->Init.KeySize);
03742
03743     /* Set the initialization vector (IV) with B0 */
03744     hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.B0);
03745     hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U);
03746     hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.B0 + 2U);
03747     hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.B0 + 3U);
03748
03749     /* Enable the CRYP peripheral */
03750     __HAL_CRYP_ENABLE(hcryp);
03751
03752     /* just wait for hash computation */
03753     if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
03754     {
03755       /* Change state */
03756       hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03757       hcryp->State = HAL_CRYP_STATE_READY;
03758
03759       /* Process unlocked & return error */
03760       __HAL_UNLOCK(hcryp);
03761       return HAL_ERROR;
03762     }
03763     /* Clear CCF flag */
03764     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
03765
03766     /************************ Header phase *************************************/
03767     /* Header block(B1) : associated data length expressed in bytes concatenated
03768     with Associated Data (A)*/
03769     if (CRYP_GCMCCM_SetHeaderPhase(hcryp,  Timeout) != HAL_OK)
03770     {
03771       return HAL_ERROR;
03772     }
03773
03774     /*************************Payload phase ************************************/
03775
03776     /* Set the phase */
03777     hcryp->Phase = CRYP_PHASE_PROCESS;
03778
03779     /* Select payload phase once the header phase is performed */
03780     MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
03781
03782     /* Set to 0 the number of non-valid bytes using NPBLB register*/
03783     MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
03784
03785   } /* if (DoKeyIVConfig == 1U) */
03786
03787   if ((hcryp->Size % 16U) != 0U)
03788   {
03789     /* recalculate  wordsize */
03790     wordsize = ((wordsize / 4U) * 4U) ;
03791   }
03792   /* Get tick */
03793   tickstart = HAL_GetTick();
03794
03795   /* Write input data and get output data */
03796   incount = hcryp->CrypInCount;
03797   outcount = hcryp->CrypOutCount;
03798   while ((incount < wordsize) && (outcount < wordsize))
03799   {
03800     /* Write plain data and get cipher data */
03801     CRYP_AES_ProcessData(hcryp, Timeout);
03802
03803     /* Check for the Timeout */
03804     if (Timeout != HAL_MAX_DELAY)
03805     {
03806       if (((HAL_GetTick() - tickstart) > Timeout) ||(Timeout == 0U))
03807       {
03808         /* Disable the CRYP peripheral clock */
03809         __HAL_CRYP_DISABLE(hcryp);
03810
03811         /* Change state */
03812         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03813         hcryp->State = HAL_CRYP_STATE_READY;
03814
03815         /* Process unlocked */
03816         __HAL_UNLOCK(hcryp);
03817         return HAL_ERROR;
03818       }
03819     }
03820     incount = hcryp->CrypInCount;
03821     outcount = hcryp->CrypOutCount;
03822   }
03823
03824   if ((hcryp->Size % 16U) != 0U)
03825   {
03826     /* Compute the number of padding bytes in last block of payload */
03827     npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - ((uint32_t)hcryp->Size);
03828
03829     if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_DECRYPT)
03830     {
03831       /* Set Npblb in case of AES CCM payload decryption to get right tag  */
03832       MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20);
03833
03834     }
03835     /* Number of valid words (lastwordsize) in last block */
03836     if ((npblb % 4U) == 0U)
03837     {
03838       lastwordsize = (16U - npblb) / 4U;
03839     }
03840     else
03841     {
03842       lastwordsize = ((16U - npblb) / 4U) + 1U;
03843     }
03844
03845     /* Write the last input block in the IN FIFO */
03846     for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter ++)
03847     {
03848       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
03849       hcryp->CrypInCount++;
03850     }
03851
03852     /* Pad the data with zeros to have a complete block */
03853     while (loopcounter < 4U)
03854     {
03855       hcryp->Instance->DINR  = 0U;
03856       loopcounter++;
03857     }
03858     /* just wait for hash computation */
03859     if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
03860     {
03861       /* Change state */
03862       hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03863       hcryp->State = HAL_CRYP_STATE_READY;
03864
03865       /* Process unlocked & return error */
03866       __HAL_UNLOCK(hcryp);
03867       return HAL_ERROR;
03868     }
03869     /* Clear CCF flag */
03870     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
03871
03872     for (loopcounter = 0U; loopcounter < 4U; loopcounter++)
03873     {
03874       /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
03875       temp = hcryp->Instance->DOUTR;
03876
03877       *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
03878       hcryp->CrypOutCount++;
03879     }
03880   }
03881
03882   /* Return function status */
03883   return HAL_OK;
03884 }
03885
03886 /**
03887   * @brief  AES CCM encryption/decryption process in interrupt mode
03888   *         for TinyAES peripheral, no encrypt/decrypt performed, only authentication preparation.
03889   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
03890   *         the configuration information for CRYP module
03891   * @retval HAL status
03892   */
03893 static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
03894 {
03895   __IO uint32_t count = 0U;
03896   uint32_t loopcounter;
03897   uint32_t lastwordsize;
03898   uint32_t npblb;
03899   uint32_t mode;
03900   uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
03901
03902 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
03903   if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED))
03904   {
03905     CRYP_PhaseProcessingResume(hcryp);
03906     return HAL_OK;
03907   }
03908 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
03909
03910   if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
03911   {
03912     if (hcryp->KeyIVConfig == 1U)
03913     {
03914       /* If the Key and IV configuration has to be done only once
03915          and if it has already been done, skip it */
03916       DoKeyIVConfig = 0U;
03917       hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
03918     }
03919     else
03920     {
03921       /* If the Key and IV configuration has to be done only once
03922          and if it has not been done already, do it and set KeyIVConfig
03923          to keep track it won't have to be done again next time */
03924       hcryp->KeyIVConfig = 1U;
03925       hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
03926     }
03927   }
03928   else
03929   {
03930     hcryp->SizesSum = hcryp->Size;
03931   }
03932
03933   /* Configure Key, IV and process message (header and payload) */
03934   if (DoKeyIVConfig == 1U)
03935   {
03936     /*  Reset CrypHeaderCount */
03937     hcryp->CrypHeaderCount = 0U;
03938
03939     /********************** Init phase ******************************************/
03940
03941     CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
03942
03943     /* Set the key */
03944     CRYP_SetKey(hcryp, hcryp->Init.KeySize);
03945
03946     /* Set the initialization vector (IV) with B0 */
03947     hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.B0);
03948     hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U);
03949     hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.B0 + 2U);
03950     hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.B0 + 3U);
03951
03952     /* Enable the CRYP peripheral */
03953     __HAL_CRYP_ENABLE(hcryp);
03954
03955     /* just wait for hash computation */
03956     count = CRYP_TIMEOUT_GCMCCMINITPHASE;
03957     do
03958     {
03959       count-- ;
03960       if (count == 0U)
03961       {
03962         /* Disable the CRYP peripheral clock */
03963         __HAL_CRYP_DISABLE(hcryp);
03964
03965         /* Change state */
03966         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
03967         hcryp->State = HAL_CRYP_STATE_READY;
03968
03969         /* Process unlocked */
03970         __HAL_UNLOCK(hcryp);
03971         return HAL_ERROR;
03972       }
03973     }
03974     while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
03975
03976     /* Clear CCF flag */
03977     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
03978
03979     /***************************** Header phase *********************************/
03980
03981     /* Select header phase */
03982     CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
03983
03984     /* Enable computation complete flag and error interrupts */
03985     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
03986
03987     /* Enable the CRYP peripheral */
03988     __HAL_CRYP_ENABLE(hcryp);
03989
03990     if (hcryp->Init.HeaderSize ==   0U) /*header phase is  skipped*/
03991     {
03992       /* Set the phase */
03993       hcryp->Phase = CRYP_PHASE_PROCESS;
03994       /* Select payload phase once the header phase is performed */
03995       CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
03996       /* Set to 0 the number of non-valid bytes using NPBLB register*/
03997       MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
03998
03999       if (hcryp->Init.Algorithm == CRYP_AES_CCM)
04000       {
04001         /* Increment CrypHeaderCount to pass in CRYP_GCMCCM_SetPayloadPhase_IT */
04002         hcryp->CrypHeaderCount++;
04003       }
04004       /* Write the payload Input block in the IN FIFO */
04005       if (hcryp->Size == 0U)
04006       {
04007         /* Disable interrupts */
04008         __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
04009
04010         /* Change the CRYP state */
04011         hcryp->State = HAL_CRYP_STATE_READY;
04012
04013         /* Process unlocked */
04014         __HAL_UNLOCK(hcryp);
04015       }
04016       else if (hcryp->Size >= 16U)
04017       {
04018         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04019         hcryp->CrypInCount++;
04020         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04021         hcryp->CrypInCount++;
04022         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04023         hcryp->CrypInCount++;
04024         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04025         hcryp->CrypInCount++;
04026
04027         if ((hcryp->CrypInCount ==  (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
04028         {
04029           /* Call Input transfer complete callback */
04030 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
04031           /*Call registered Input complete callback*/
04032           hcryp->InCpltCallback(hcryp);
04033 #else
04034           /*Call legacy weak Input complete callback*/
04035           HAL_CRYP_InCpltCallback(hcryp);
04036 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
04037         }
04038       }
04039       else /* Size < 4 words  : first block is the last block*/
04040       {
04041         /* Compute the number of padding bytes in last block of payload */
04042         npblb = 16U - (uint32_t)hcryp->Size;
04043
04044         mode = hcryp->Instance->CR & AES_CR_MODE;
04045         if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) ||
04046             ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
04047         {
04048           /* Specify the number of non-valid bytes using NPBLB register*/
04049           MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
04050         }
04051
04052         /* Number of valid words (lastwordsize) in last block */
04053         if ((npblb % 4U) == 0U)
04054         {
04055           lastwordsize = (16U - npblb) / 4U;
04056         }
04057         else
04058         {
04059           lastwordsize = ((16U - npblb) / 4U) + 1U;
04060         }
04061
04062         /*  Last block optionally pad the data with zeros*/
04063         for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
04064         {
04065           hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04066           hcryp->CrypInCount++;
04067         }
04068         while (loopcounter < 4U)
04069         {
04070           /* Pad the data with zeros to have a complete block */
04071           hcryp->Instance->DINR = 0x0U;
04072           loopcounter++;
04073         }
04074       }
04075     }
04076     else if ((hcryp->Init.HeaderSize) < 4U) /*HeaderSize < 4 */
04077     {
04078       /*  Last block optionally pad the data with zeros*/
04079       for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++)
04080       {
04081         hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04082         hcryp->CrypHeaderCount++ ;
04083       }
04084       while (loopcounter < 4U)
04085       {
04086         /* pad the data with zeros to have a complete block */
04087         hcryp->Instance->DINR = 0x0U;
04088         loopcounter++;
04089       }
04090     }
04091     else
04092     {
04093       /* Write the input block in the IN FIFO */
04094       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04095       hcryp->CrypHeaderCount++;
04096       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04097       hcryp->CrypHeaderCount++;
04098       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04099       hcryp->CrypHeaderCount++;
04100       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04101       hcryp->CrypHeaderCount++;
04102     }
04103
04104   } /* end of if (DoKeyIVConfig == 1U) */
04105   else  /* Key and IV have already been configured,
04106           header has already been processed;
04107           only process here message payload */
04108   {
04109     /* Write the payload Input block in the IN FIFO */
04110     if (hcryp->Size == 0U)
04111     {
04112       /* Disable interrupts */
04113       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
04114
04115       /* Change the CRYP state */
04116       hcryp->State = HAL_CRYP_STATE_READY;
04117
04118       /* Process unlocked */
04119       __HAL_UNLOCK(hcryp);
04120     }
04121     else if (hcryp->Size >= 16U)
04122     {
04123       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04124       hcryp->CrypInCount++;
04125       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04126       hcryp->CrypInCount++;
04127       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04128       hcryp->CrypInCount++;
04129       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04130       hcryp->CrypInCount++;
04131
04132       if ((hcryp->CrypInCount ==  (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
04133       {
04134         /* Call Input transfer complete callback */
04135 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
04136         /*Call registered Input complete callback*/
04137         hcryp->InCpltCallback(hcryp);
04138 #else
04139         /*Call legacy weak Input complete callback*/
04140         HAL_CRYP_InCpltCallback(hcryp);
04141 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
04142       }
04143     }
04144     else /* Size < 4 words  : first block is the last block*/
04145     {
04146       /* Compute the number of padding bytes in last block of payload */
04147       npblb = 16U - (uint32_t)hcryp->Size;
04148
04149       mode = hcryp->Instance->CR & AES_CR_MODE;
04150       if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) ||
04151           ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
04152       {
04153         /* Specify the number of non-valid bytes using NPBLB register*/
04154         MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
04155       }
04156
04157       /* Number of valid words (lastwordsize) in last block */
04158       if ((npblb % 4U) == 0U)
04159       {
04160         lastwordsize = (16U - npblb) / 4U;
04161       }
04162       else
04163       {
04164         lastwordsize = ((16U - npblb) / 4U) + 1U;
04165       }
04166
04167       /*  Last block optionally pad the data with zeros*/
04168       for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
04169       {
04170         hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04171         hcryp->CrypInCount++;
04172       }
04173       while (loopcounter < 4U)
04174       {
04175         /* Pad the data with zeros to have a complete block */
04176         hcryp->Instance->DINR = 0x0U;
04177         loopcounter++;
04178       }
04179     }
04180   }
04181
04182   /* Return function status */
04183   return HAL_OK;
04184 }
04185
04186 /**
04187   * @brief  AES CCM encryption/decryption process in DMA mode
04188   *         for TinyAES peripheral, no encrypt/decrypt performed, only authentication preparation.
04189   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
04190   *         the configuration information for CRYP module
04191   * @retval HAL status
04192   */
04193 static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
04194 {
04195   __IO uint32_t count    = 0U;
04196   uint16_t wordsize = hcryp->Size / 4U ;
04197   uint32_t index;
04198   uint32_t npblb;
04199   uint32_t lastwordsize;
04200   uint32_t temp;  /* Temporary CrypOutBuff */
04201   uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
04202
04203   if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
04204   {
04205     if (hcryp->KeyIVConfig == 1U)
04206     {
04207       /* If the Key and IV configuration has to be done only once
04208          and if it has already been done, skip it */
04209       DoKeyIVConfig = 0U;
04210       hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
04211     }
04212     else
04213     {
04214       /* If the Key and IV configuration has to be done only once
04215          and if it has not been done already, do it and set KeyIVConfig
04216          to keep track it won't have to be done again next time */
04217       hcryp->KeyIVConfig = 1U;
04218       hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
04219     }
04220   }
04221   else
04222   {
04223     hcryp->SizesSum = hcryp->Size;
04224   }
04225
04226   if (DoKeyIVConfig == 1U)
04227   {
04228
04229     /*  Reset CrypHeaderCount */
04230     hcryp->CrypHeaderCount = 0U;
04231
04232
04233     /********************** Init phase ******************************************/
04234
04235     CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
04236
04237     /* Set the key */
04238     CRYP_SetKey(hcryp, hcryp->Init.KeySize);
04239
04240     /* Set the initialization vector (IV) with B0 */
04241     hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.B0);
04242     hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U);
04243     hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.B0 + 2U);
04244     hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.B0 + 3U);
04245
04246     /* Enable the CRYP peripheral */
04247     __HAL_CRYP_ENABLE(hcryp);
04248
04249     /* just wait for hash computation */
04250     count = CRYP_TIMEOUT_GCMCCMINITPHASE;
04251     do
04252     {
04253       count-- ;
04254       if (count == 0U)
04255       {
04256         /* Disable the CRYP peripheral clock */
04257         __HAL_CRYP_DISABLE(hcryp);
04258
04259         /* Change state */
04260         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
04261         hcryp->State = HAL_CRYP_STATE_READY;
04262
04263         /* Process unlocked */
04264         __HAL_UNLOCK(hcryp);
04265         return HAL_ERROR;
04266       }
04267     }
04268     while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
04269
04270     /* Clear CCF flag */
04271     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
04272
04273
04274     /********************* Header phase *****************************************/
04275
04276     if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
04277     {
04278       return HAL_ERROR;
04279     }
04280
04281     /******************** Payload phase *****************************************/
04282
04283     /* Set the phase */
04284     hcryp->Phase = CRYP_PHASE_PROCESS;
04285
04286     /* Set to 0 the number of non-valid bytes using NPBLB register*/
04287     MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
04288
04289     /* Select payload phase once the header phase is performed */
04290     MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
04291
04292   } /* if (DoKeyIVConfig == 1U) */
04293
04294   if (hcryp->Size == 0U)
04295   {
04296     /* Process unLocked */
04297     __HAL_UNLOCK(hcryp);
04298
04299     /* Change the CRYP state and phase */
04300     hcryp->State = HAL_CRYP_STATE_READY;
04301   }
04302   else if (hcryp->Size >= 16U)
04303   {
04304     /*DMA transfer must not include the last block in case of Size is not %16 */
04305     wordsize = wordsize - (wordsize % 4U);
04306
04307     /*DMA transfer */
04308     CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), wordsize, (uint32_t)(hcryp->pCrypOutBuffPtr));
04309   }
04310   else /* length of input data is < 16 */
04311   {
04312     /* Compute the number of padding bytes in last block of payload */
04313     npblb = 16U - (uint32_t)hcryp->Size;
04314
04315     /* Set Npblb in case of AES CCM payload decryption to get right tag*/
04316     if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_DECRYPT)
04317     {
04318       /* Specify the number of non-valid bytes using NPBLB register*/
04319       MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
04320     }
04321
04322     /* Number of valid words (lastwordsize) in last block */
04323     if ((npblb % 4U) == 0U)
04324     {
04325       lastwordsize = (16U - npblb) / 4U;
04326     }
04327     else
04328     {
04329       lastwordsize = ((16U - npblb) / 4U) + 1U;
04330     }
04331
04332     /*  last block optionally pad the data with zeros*/
04333     for (index = 0U; index < lastwordsize; index ++)
04334     {
04335       /* Write the last Input block in the IN FIFO */
04336       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04337       hcryp->CrypInCount++;
04338     }
04339     while (index < 4U)
04340     {
04341       /* pad the data with zeros to have a complete block */
04342       hcryp->Instance->DINR  = 0U;
04343       index++;
04344     }
04345     /* Wait for CCF flag to be raised */
04346     count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
04347     do
04348     {
04349       count-- ;
04350       if (count == 0U)
04351       {
04352         /* Disable the CRYP peripheral clock */
04353         __HAL_CRYP_DISABLE(hcryp);
04354
04355         /* Change state */
04356         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
04357         hcryp->State = HAL_CRYP_STATE_READY;
04358
04359         /* Process unlocked */
04360         __HAL_UNLOCK(hcryp);
04361 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
04362         /*Call registered error callback*/
04363         hcryp->ErrorCallback(hcryp);
04364 #else
04365         /*Call legacy weak error callback*/
04366         HAL_CRYP_ErrorCallback(hcryp);
04367 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
04368       }
04369     }
04370     while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
04371
04372     /* Clear CCF Flag */
04373     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
04374
04375     /*Read the output block from the output FIFO */
04376     for (index = 0U; index < 4U; index++)
04377     {
04378       /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
04379       temp = hcryp->Instance->DOUTR;
04380
04381       *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
04382       hcryp->CrypOutCount++;
04383     }
04384
04385     /* Change the CRYP state to ready */
04386     hcryp->State = HAL_CRYP_STATE_READY;
04387
04388     /* Process unlocked */
04389     __HAL_UNLOCK(hcryp);
04390   }
04391
04392   /* Return function status */
04393   return HAL_OK;
04394 }
04395
04396 /**
04397   * @brief  Sets the payload phase in interrupt mode
04398   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
04399   *         the configuration information for CRYP module
04400   * @retval state
04401   */
04402 static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
04403 {
04404   uint32_t loopcounter;
04405   uint32_t temp;  /* Temporary CrypOutBuff */
04406   uint32_t lastwordsize;
04407   uint32_t npblb;
04408   uint32_t mode;
04409   uint16_t incount;  /* Temporary CrypInCount Value */
04410   uint16_t outcount;  /* Temporary CrypOutCount Value */
04411
04412   /***************************** Payload phase *******************************/
04413
04414   /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
04415   temp  = hcryp->Instance->DOUTR;
04416   *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
04417   hcryp->CrypOutCount++;
04418   temp  = hcryp->Instance->DOUTR;
04419   *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount)   = temp;
04420   hcryp->CrypOutCount++;
04421   temp  = hcryp->Instance->DOUTR;
04422   *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
04423   hcryp->CrypOutCount++;
04424   temp  = hcryp->Instance->DOUTR;
04425   *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount)   = temp;
04426   hcryp->CrypOutCount++;
04427
04428   incount = hcryp->CrypInCount;
04429   outcount = hcryp->CrypOutCount;
04430   if ((outcount >=  (hcryp->Size / 4U)) && ((incount * 4U) >=  hcryp->Size))
04431   {
04432
04433      /* When in CCM with Key and IV configuration skipped, don't disable interruptions */
04434      if (!((hcryp->Init.Algorithm == CRYP_AES_CCM) && (hcryp->KeyIVConfig == 1U)))
04435      {
04436       /* Disable computation complete flag and errors interrupts */
04437       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
04438      }
04439
04440     /* Change the CRYP state */
04441     hcryp->State = HAL_CRYP_STATE_READY;
04442
04443     /* Process unlocked */
04444     __HAL_UNLOCK(hcryp);
04445
04446     /* Call output transfer complete callback */
04447 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
04448     /*Call registered Output complete callback*/
04449     hcryp->OutCpltCallback(hcryp);
04450 #else
04451     /*Call legacy weak Output complete callback*/
04452     HAL_CRYP_OutCpltCallback(hcryp);
04453 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
04454   }
04455
04456   else if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U)
04457   {
04458
04459 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
04460     /* If suspension flag has been raised, suspend processing
04461        only if not already at the end of the payload */
04462     if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
04463     {
04464       /* Clear CCF Flag */
04465       __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
04466
04467       /* reset SuspendRequest */
04468       hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
04469       /* Disable Computation Complete Flag and Errors Interrupts */
04470       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE);
04471       /* Change the CRYP state */
04472       hcryp->State = HAL_CRYP_STATE_SUSPENDED;
04473       /* Mark that the payload phase is suspended */
04474       hcryp->Phase = CRYP_PHASE_PAYLOAD_SUSPENDED;
04475
04476      /* Process Unlocked */
04477       __HAL_UNLOCK(hcryp);
04478     }
04479     else
04480 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
04481     {
04482     /* Write the input block in the IN FIFO */
04483     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04484     hcryp->CrypInCount++;
04485     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04486     hcryp->CrypInCount++;
04487     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04488     hcryp->CrypInCount++;
04489     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04490     hcryp->CrypInCount++;
04491     if ((hcryp->CrypInCount ==  hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC))
04492     {
04493       /* Call output transfer complete callback */
04494 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
04495       /*Call registered Input complete callback*/
04496       hcryp->InCpltCallback(hcryp);
04497 #else
04498       /*Call legacy weak Input complete callback*/
04499       HAL_CRYP_InCpltCallback(hcryp);
04500 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
04501     }
04502   }
04503   }
04504   else /* Last block of payload < 128bit*/
04505   {
04506     /* Compute the number of padding bytes in last block of payload */
04507     npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - ((uint32_t)hcryp->Size);
04508
04509     mode = hcryp->Instance->CR & AES_CR_MODE;
04510     if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) ||
04511         ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
04512     {
04513       /* Specify the number of non-valid bytes using NPBLB register*/
04514       MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
04515     }
04516
04517     /* Number of valid words (lastwordsize) in last block */
04518     if ((npblb % 4U) == 0U)
04519     {
04520       lastwordsize = (16U - npblb) / 4U;
04521     }
04522     else
04523     {
04524       lastwordsize = ((16U - npblb) / 4U) + 1U;
04525     }
04526
04527     /*  Last block optionally pad the data with zeros*/
04528     for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
04529     {
04530       hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04531       hcryp->CrypInCount++;
04532     }
04533     while (loopcounter < 4U)
04534     {
04535       /* pad the data with zeros to have a complete block */
04536       hcryp->Instance->DINR = 0x0U;
04537       loopcounter++;
04538     }
04539   }
04540 }
04541
04542
04543 /**
04544   * @brief  Sets the header phase in polling mode
04545   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
04546   *         the configuration information for CRYP module(Header & HeaderSize)
04547   * @param  Timeout Timeout value
04548   * @retval state
04549   */
04550 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
04551 {
04552   uint32_t loopcounter;
04553
04554   /***************************** Header phase for GCM/GMAC or CCM *********************************/
04555
04556   if ((hcryp->Init.HeaderSize != 0U))
04557   {
04558     /* Select header phase */
04559     CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
04560
04561     /* Enable the CRYP peripheral */
04562     __HAL_CRYP_ENABLE(hcryp);
04563
04564     if ((hcryp->Init.HeaderSize % 4U) == 0U)
04565     {
04566       /* HeaderSize %4, no padding */
04567       for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
04568       {
04569         /* Write the input block in the data input register */
04570         hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04571         hcryp->CrypHeaderCount++ ;
04572         hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04573         hcryp->CrypHeaderCount++ ;
04574         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04575         hcryp->CrypHeaderCount++ ;
04576         hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04577         hcryp->CrypHeaderCount++ ;
04578
04579         if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
04580         {
04581           /* Disable the CRYP peripheral clock */
04582           __HAL_CRYP_DISABLE(hcryp);
04583
04584           /* Change state */
04585           hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
04586           hcryp->State = HAL_CRYP_STATE_READY;
04587
04588           /* Process unlocked */
04589           __HAL_UNLOCK(hcryp);
04590           return HAL_ERROR;
04591         }
04592         /* Clear CCF flag */
04593         __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
04594       }
04595     }
04596     else
04597     {
04598       /*Write header block in the IN FIFO without last block */
04599       for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
04600       {
04601         /* Write the input block in the data input register */
04602         hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04603         hcryp->CrypHeaderCount++ ;
04604         hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04605         hcryp->CrypHeaderCount++ ;
04606         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04607         hcryp->CrypHeaderCount++ ;
04608         hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04609         hcryp->CrypHeaderCount++ ;
04610
04611         if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
04612         {
04613           /* Disable the CRYP peripheral clock */
04614           __HAL_CRYP_DISABLE(hcryp);
04615
04616           /* Change state */
04617           hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
04618           hcryp->State = HAL_CRYP_STATE_READY;
04619
04620           /* Process unlocked */
04621           __HAL_UNLOCK(hcryp);
04622           return HAL_ERROR;
04623         }
04624         /* Clear CCF flag */
04625         __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
04626       }
04627       /*  Last block optionally pad the data with zeros*/
04628       for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
04629       {
04630         hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04631         hcryp->CrypHeaderCount++ ;
04632       }
04633       while (loopcounter < 4U)
04634       {
04635         /*Pad the data with zeros to have a complete block */
04636         hcryp->Instance->DINR = 0x0U;
04637         loopcounter++;
04638       }
04639
04640       if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
04641       {
04642         /* Disable the CRYP peripheral clock */
04643         __HAL_CRYP_DISABLE(hcryp);
04644
04645         /* Change state */
04646         hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
04647         hcryp->State = HAL_CRYP_STATE_READY;
04648
04649         /* Process unlocked */
04650         __HAL_UNLOCK(hcryp);
04651         return HAL_ERROR;
04652       }
04653       /* Clear CCF flag */
04654       __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
04655     }
04656   }
04657   else
04658   {
04659     if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
04660     {
04661       /*Workaround 1: only AES, before re-enabling the peripheral, datatype can be configured.*/
04662       MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
04663
04664       /* Select header phase */
04665       CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
04666
04667       /* Enable the CRYP peripheral */
04668       __HAL_CRYP_ENABLE(hcryp);
04669     }
04670   }
04671   /* Return function status */
04672   return HAL_OK;
04673 }
04674
04675 /**
04676   * @brief  Sets the header phase when using DMA in process
04677   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
04678   *         the configuration information for CRYP module(Header & HeaderSize)
04679   * @retval None
04680   */
04681 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp)
04682 {
04683   __IO uint32_t count  = 0U;
04684   uint32_t loopcounter;
04685
04686   /***************************** Header phase for GCM/GMAC or CCM *********************************/
04687   if ((hcryp->Init.HeaderSize != 0U))
04688   {
04689     /* Select header phase */
04690     CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
04691
04692     /* Enable the CRYP peripheral */
04693     __HAL_CRYP_ENABLE(hcryp);
04694
04695     if ((hcryp->Init.HeaderSize % 4U) == 0U)
04696     {
04697       /* HeaderSize %4, no padding */
04698       for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
04699       {
04700         /* Write the input block in the data input register */
04701         hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04702         hcryp->CrypHeaderCount++ ;
04703         hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04704         hcryp->CrypHeaderCount++ ;
04705         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04706         hcryp->CrypHeaderCount++ ;
04707         hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04708         hcryp->CrypHeaderCount++ ;
04709
04710         /*Wait on CCF flag*/
04711         count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
04712         do
04713         {
04714           count-- ;
04715           if (count == 0U)
04716           {
04717             /* Disable the CRYP peripheral clock */
04718             __HAL_CRYP_DISABLE(hcryp);
04719
04720             /* Change state */
04721             hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
04722             hcryp->State = HAL_CRYP_STATE_READY;
04723
04724             /* Process unlocked */
04725             __HAL_UNLOCK(hcryp);
04726             return HAL_ERROR;
04727           }
04728         }
04729         while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
04730
04731         /* Clear CCF flag */
04732         __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
04733       }
04734     }
04735     else
04736     {
04737       /*Write header block in the IN FIFO without last block */
04738       for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
04739       {
04740         /* Write the Input block in the Data Input register */
04741         hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04742         hcryp->CrypHeaderCount++ ;
04743         hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04744         hcryp->CrypHeaderCount++ ;
04745         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04746         hcryp->CrypHeaderCount++ ;
04747         hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04748         hcryp->CrypHeaderCount++ ;
04749
04750         /*Wait on CCF flag*/
04751         count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
04752         do
04753         {
04754           count-- ;
04755           if (count == 0U)
04756           {
04757             /* Disable the CRYP peripheral clock */
04758             __HAL_CRYP_DISABLE(hcryp);
04759
04760             /* Change state */
04761             hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
04762             hcryp->State = HAL_CRYP_STATE_READY;
04763
04764             /* Process unlocked */
04765             __HAL_UNLOCK(hcryp);
04766             return HAL_ERROR;
04767           }
04768         }
04769         while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
04770
04771         /* Clear CCF flag */
04772         __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
04773       }
04774       /*  Last block optionally pad the data with zeros*/
04775       for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
04776       {
04777         hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04778         hcryp->CrypHeaderCount++ ;
04779       }
04780       while (loopcounter < 4U)
04781       {
04782         /* Pad the data with zeros to have a complete block */
04783         hcryp->Instance->DINR = 0x0U;
04784         loopcounter++;
04785       }
04786
04787       /*Wait on CCF flag*/
04788       count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
04789       do
04790       {
04791         count-- ;
04792         if (count == 0U)
04793         {
04794           /* Disable the CRYP peripheral clock */
04795           __HAL_CRYP_DISABLE(hcryp);
04796
04797           /* Change state */
04798           hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
04799           hcryp->State = HAL_CRYP_STATE_READY;
04800
04801           /* Process unlocked */
04802           __HAL_UNLOCK(hcryp);
04803           return HAL_ERROR;
04804         }
04805       }
04806       while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
04807
04808       /* Clear CCF flag */
04809       __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
04810     }
04811   }
04812   else
04813   {
04814     /* Select header phase */
04815     CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
04816
04817     /* Enable the CRYP peripheral */
04818     __HAL_CRYP_ENABLE(hcryp);
04819   }
04820   /* Return function status */
04821   return HAL_OK;
04822 }
04823
04824 /**
04825   * @brief  Sets the header phase in interrupt mode
04826   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
04827   *         the configuration information for CRYP module(Header & HeaderSize)
04828   * @retval None
04829   */
04830 static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
04831 {
04832   uint32_t loopcounter;
04833   uint32_t lastwordsize;
04834   uint32_t npblb;
04835   uint32_t mode;
04836
04837   /***************************** Header phase *********************************/
04838   if (hcryp->Init.HeaderSize ==  hcryp->CrypHeaderCount)
04839   {
04840     /* Set the phase */
04841     hcryp->Phase = CRYP_PHASE_PROCESS;
04842     /* Select payload phase */
04843     MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
04844     /* Set to 0 the number of non-valid bytes using NPBLB register*/
04845     MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
04846
04847     if (hcryp->Init.Algorithm == CRYP_AES_CCM)
04848     {
04849       /* Increment CrypHeaderCount to pass in CRYP_GCMCCM_SetPayloadPhase_IT */
04850       hcryp->CrypHeaderCount++;
04851     }
04852     /* Write the payload Input block in the IN FIFO */
04853     if (hcryp->Size == 0U)
04854     {
04855       /* Disable interrupts */
04856       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
04857
04858       /* Change the CRYP state */
04859       hcryp->State = HAL_CRYP_STATE_READY;
04860
04861       /* Process unlocked */
04862       __HAL_UNLOCK(hcryp);
04863     }
04864     else if (hcryp->Size >= 16U)
04865     {
04866       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04867       hcryp->CrypInCount++;
04868       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04869       hcryp->CrypInCount++;
04870       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04871       hcryp->CrypInCount++;
04872       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04873       hcryp->CrypInCount++;
04874
04875       if ((hcryp->CrypInCount ==  (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
04876       {
04877         /* Call the input data transfer complete callback */
04878 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
04879         /*Call registered Input complete callback*/
04880         hcryp->InCpltCallback(hcryp);
04881 #else
04882         /*Call legacy weak Input complete callback*/
04883         HAL_CRYP_InCpltCallback(hcryp);
04884 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
04885       }
04886     }
04887     else /* Size < 4 words  : first block is the last block*/
04888     {
04889       /* Compute the number of padding bytes in last block of payload */
04890       npblb = 16U - ((uint32_t)hcryp->Size);
04891       mode = hcryp->Instance->CR & AES_CR_MODE;
04892       if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) ||
04893           ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
04894       {
04895         /* Specify the number of non-valid bytes using NPBLB register*/
04896         MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
04897       }
04898
04899       /* Number of valid words (lastwordsize) in last block */
04900       if ((npblb % 4U) == 0U)
04901       {
04902         lastwordsize = (16U - npblb) / 4U;
04903       }
04904       else
04905       {
04906         lastwordsize = ((16U - npblb) / 4U) + 1U;
04907       }
04908
04909       /*  Last block optionally pad the data with zeros*/
04910       for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
04911       {
04912         hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
04913         hcryp->CrypInCount++;
04914       }
04915       while (loopcounter < 4U)
04916       {
04917         /* Pad the data with zeros to have a complete block */
04918         hcryp->Instance->DINR = 0x0U;
04919         loopcounter++;
04920       }
04921     }
04922   }
04923   else if ((((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U))
04924   {
04925
04926 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
04927     /* If suspension flag has been raised, suspend processing
04928        only if not already at the end of the header */
04929     if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
04930     {
04931       /* Clear CCF Flag */
04932       __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
04933
04934       /* reset SuspendRequest */
04935       hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
04936       /* Disable Computation Complete Flag and Errors Interrupts */
04937       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE);
04938       /* Change the CRYP state */
04939       hcryp->State = HAL_CRYP_STATE_SUSPENDED;
04940       /* Mark that the payload phase is suspended */
04941       hcryp->Phase = CRYP_PHASE_HEADER_SUSPENDED;
04942
04943      /* Process Unlocked */
04944       __HAL_UNLOCK(hcryp);
04945     }
04946     else
04947 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
04948     {
04949     /* Write the input block in the IN FIFO */
04950     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04951     hcryp->CrypHeaderCount++;
04952     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04953     hcryp->CrypHeaderCount++;
04954     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04955     hcryp->CrypHeaderCount++;
04956     hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04957     hcryp->CrypHeaderCount++;
04958   }
04959   }
04960   else /*HeaderSize < 4 or HeaderSize >4 & HeaderSize %4 != 0*/
04961   {
04962     /*  Last block optionally pad the data with zeros*/
04963     for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++)
04964     {
04965       hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
04966       hcryp->CrypHeaderCount++ ;
04967     }
04968     while (loopcounter < 4U)
04969     {
04970       /* pad the data with zeros to have a complete block */
04971       hcryp->Instance->DINR = 0x0U;
04972       loopcounter++;
04973     }
04974   }
04975 }
04976
04977 /**
04978   * @brief  Handle CRYP hardware block Timeout when waiting for CCF flag to be raised.
04979   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
04980   *         the configuration information for CRYP module.
04981   * @param  Timeout Timeout duration.
04982   * @retval HAL status
04983   */
04984 static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
04985 {
04986   uint32_t tickstart;
04987
04988   /* Get timeout */
04989   tickstart = HAL_GetTick();
04990
04991   while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
04992   {
04993     /* Check for the Timeout */
04994     if (Timeout != HAL_MAX_DELAY)
04995     {
04996       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
04997       {
04998         return HAL_ERROR;
04999       }
05000     }
05001   }
05002   return HAL_OK;
05003 }
05004
05005
05006 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
05007 /**
05008   * @brief  In case of message processing suspension, read the Initialization Vector.
05009   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
05010   *         the configuration information for CRYP module.
05011   * @param  Output Pointer to the buffer containing the saved Initialization Vector.
05012   * @note   This value has to be stored for reuse by writing the AES_IVRx registers
05013   *         as soon as the suspended processing has to be resumed.
05014   * @retval None
05015   */
05016 static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output)
05017 {
05018   uint32_t outputaddr = (uint32_t)Output;
05019
05020   *(uint32_t*)(outputaddr) = hcryp->Instance->IVR3;
05021   outputaddr+=4U;
05022   *(uint32_t*)(outputaddr) = hcryp->Instance->IVR2;
05023   outputaddr+=4U;
05024   *(uint32_t*)(outputaddr) = hcryp->Instance->IVR1;
05025   outputaddr+=4U;
05026   *(uint32_t*)(outputaddr) = hcryp->Instance->IVR0;
05027 }
05028
05029 /**
05030   * @brief  In case of message processing resumption, rewrite the Initialization
05031   *         Vector in the AES_IVRx registers.
05032   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
05033   *         the configuration information for CRYP module.
05034   * @param  Input Pointer to the buffer containing the saved Initialization Vector to
05035   *         write back in the CRYP hardware block.
05036   * @note   AES must be disabled when reconfiguring the IV values.
05037   * @retval None
05038   */
05039 static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input)
05040 {
05041   uint32_t ivaddr = (uint32_t)Input;
05042
05043   hcryp->Instance->IVR3 = *(uint32_t*)(ivaddr);
05044   ivaddr+=4U;
05045   hcryp->Instance->IVR2 = *(uint32_t*)(ivaddr);
05046   ivaddr+=4U;
05047   hcryp->Instance->IVR1 = *(uint32_t*)(ivaddr);
05048   ivaddr+=4U;
05049   hcryp->Instance->IVR0 = *(uint32_t*)(ivaddr);
05050 }
05051
05052 /**
05053   * @brief  In case of message GCM/GMAC/CCM processing suspension,
05054   *         read the Suspend Registers.
05055   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
05056   *         the configuration information for CRYP module.
05057   * @param  Output Pointer to the buffer containing the saved Suspend Registers.
05058   * @note   These values have to be stored for reuse by writing back the AES_SUSPxR registers
05059   *         as soon as the suspended processing has to be resumed.
05060   * @retval None
05061   */
05062 static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output)
05063 {
05064   uint32_t outputaddr = (uint32_t)Output;
05065   __IO uint32_t count = 0U;
05066
05067   /* In case of GCM payload phase encryption, check that suspension can be carried out */
05068   if (READ_BIT(hcryp->Instance->CR, (AES_CR_CHMOD|AES_CR_GCMPH|AES_CR_MODE)) == (CRYP_AES_GCM_GMAC|AES_CR_GCMPH_1|0x0U))
05069   {
05070
05071       /* Wait for BUSY flag to be cleared */
05072       count = 0xFFF;
05073       do
05074       {
05075         count-- ;
05076         if(count == 0U)
05077         {
05078           /* Change state */
05079           hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
05080           hcryp->State = HAL_CRYP_STATE_READY;
05081
05082           /* Process unlocked */
05083           __HAL_UNLOCK(hcryp);
05084           HAL_CRYP_ErrorCallback(hcryp);
05085           return;
05086         }
05087       }
05088       while(HAL_IS_BIT_SET(hcryp->Instance->SR, AES_SR_BUSY));
05089
05090   }
05091
05092
05093   *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP7R;
05094   outputaddr+=4U;
05095   *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP6R;
05096   outputaddr+=4U;
05097   *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP5R;
05098   outputaddr+=4U;
05099   *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP4R;
05100   outputaddr+=4U;
05101   *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP3R;
05102   outputaddr+=4U;
05103   *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP2R;
05104   outputaddr+=4U;
05105   *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP1R;
05106   outputaddr+=4U;
05107   *(uint32_t*)(outputaddr) = hcryp->Instance->SUSP0R;
05108 }
05109
05110 /**
05111   * @brief  In case of message GCM/GMAC/CCM processing resumption, rewrite the Suspend
05112   *         Registers in the AES_SUSPxR registers.
05113   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
05114   *         the configuration information for CRYP module.
05115   * @param  Input Pointer to the buffer containing the saved suspend registers to
05116   *         write back in the CRYP hardware block.
05117   * @note   AES must be disabled when reconfiguring the suspend registers.
05118   * @retval None
05119   */
05120 static void CRYP_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input)
05121 {
05122   uint32_t ivaddr = (uint32_t)Input;
05123
05124   hcryp->Instance->SUSP7R = *(uint32_t*)(ivaddr);
05125   ivaddr+=4U;
05126   hcryp->Instance->SUSP6R = *(uint32_t*)(ivaddr);
05127   ivaddr+=4U;
05128   hcryp->Instance->SUSP5R = *(uint32_t*)(ivaddr);
05129   ivaddr+=4U;
05130   hcryp->Instance->SUSP4R = *(uint32_t*)(ivaddr);
05131   ivaddr+=4U;
05132   hcryp->Instance->SUSP3R = *(uint32_t*)(ivaddr);
05133   ivaddr+=4U;
05134   hcryp->Instance->SUSP2R = *(uint32_t*)(ivaddr);
05135   ivaddr+=4U;
05136   hcryp->Instance->SUSP1R = *(uint32_t*)(ivaddr);
05137   ivaddr+=4U;
05138   hcryp->Instance->SUSP0R = *(uint32_t*)(ivaddr);
05139 }
05140
05141 /**
05142   * @brief  In case of message GCM/GMAC/CCM processing suspension, read the Key Registers.
05143   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
05144   *         the configuration information for CRYP module.
05145   * @param  Output Pointer to the buffer containing the saved Key Registers.
05146   * @param  KeySize Indicates the key size (128 or 256 bits).
05147   * @note   These values have to be stored for reuse by writing back the AES_KEYRx registers
05148   *         as soon as the suspended processing has to be resumed.
05149   * @retval None
05150   */
05151 static void CRYP_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output, uint32_t KeySize)
05152 {
05153   uint32_t keyaddr = (uint32_t)Output;
05154
05155   switch (KeySize)
05156   {
05157     case CRYP_KEYSIZE_256B:
05158       *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey);
05159       keyaddr+=4U;
05160       *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 1U);
05161       keyaddr+=4U;
05162       *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 2U);
05163       keyaddr+=4U;
05164       *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 3U);
05165       keyaddr+=4U;
05166       *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 4U);
05167       keyaddr+=4U;
05168       *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 5U);
05169       keyaddr+=4U;
05170       *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 6U);
05171       keyaddr+=4U;
05172       *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 7U);
05173       break;
05174     case CRYP_KEYSIZE_128B:
05175       *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey);
05176       keyaddr+=4U;
05177       *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 1U);
05178       keyaddr+=4U;
05179       *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 2U);
05180       keyaddr+=4U;
05181       *(uint32_t*)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 3U);
05182       break;
05183     default:
05184       break;
05185   }
05186 }
05187
05188 /**
05189   * @brief  In case of message GCM/GMAC (CCM/CMAC when applicable) processing resumption, rewrite the Key
05190   *         Registers in the AES_KEYRx registers.
05191   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
05192   *         the configuration information for CRYP module.
05193   * @param  Input Pointer to the buffer containing the saved key registers to
05194   *         write back in the CRYP hardware block.
05195   * @param  KeySize Indicates the key size (128 or 256 bits)
05196   * @note   AES must be disabled when reconfiguring the Key registers.
05197   * @retval None
05198   */
05199 static void CRYP_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input, uint32_t KeySize)
05200 {
05201   uint32_t keyaddr = (uint32_t)Input;
05202
05203   if (KeySize == CRYP_KEYSIZE_256B)
05204   {
05205     hcryp->Instance->KEYR7 = *(uint32_t*)(keyaddr);
05206     keyaddr+=4U;
05207     hcryp->Instance->KEYR6 = *(uint32_t*)(keyaddr);
05208     keyaddr+=4U;
05209     hcryp->Instance->KEYR5 = *(uint32_t*)(keyaddr);
05210     keyaddr+=4U;
05211     hcryp->Instance->KEYR4 = *(uint32_t*)(keyaddr);
05212     keyaddr+=4U;
05213   }
05214
05215     hcryp->Instance->KEYR3 = *(uint32_t*)(keyaddr);
05216     keyaddr+=4U;
05217     hcryp->Instance->KEYR2 = *(uint32_t*)(keyaddr);
05218     keyaddr+=4U;
05219     hcryp->Instance->KEYR1 = *(uint32_t*)(keyaddr);
05220     keyaddr+=4U;
05221     hcryp->Instance->KEYR0 = *(uint32_t*)(keyaddr);
05222 }
05223
05224 /**
05225   * @brief  Authentication phase resumption in case of GCM/GMAC/CCM process in interrupt mode
05226   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
05227   *         the configuration information for CRYP module(Header & HeaderSize)
05228   * @retval None
05229   */
05230 static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp)
05231 {
05232   uint32_t loopcounter;
05233   uint16_t lastwordsize;
05234   uint16_t npblb;
05235   uint32_t cr_temp;
05236
05237   /* Case of header phase resumption =================================================*/
05238   if (hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED)
05239   {
05240       /* Set the phase */
05241     hcryp->Phase = CRYP_PHASE_PROCESS;
05242
05243     /* Select header phase */
05244     CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
05245
05246     if ((((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U))
05247     {
05248       /* Write the input block in the IN FIFO */
05249       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
05250       hcryp->CrypHeaderCount++;
05251       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
05252       hcryp->CrypHeaderCount++;
05253       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
05254       hcryp->CrypHeaderCount++;
05255       hcryp->Instance->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
05256       hcryp->CrypHeaderCount++;
05257     }
05258     else /*HeaderSize < 4 or HeaderSize >4 & HeaderSize %4 != 0*/
05259     {
05260       /*  Last block optionally pad the data with zeros*/
05261       for(loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize %4U ); loopcounter++)
05262       {
05263         hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
05264         hcryp->CrypHeaderCount++ ;
05265       }
05266       while(loopcounter <4U )
05267       {
05268         /* pad the data with zeros to have a complete block */
05269         hcryp->Instance->DINR = 0x0U;
05270         loopcounter++;
05271       }
05272     }
05273   }
05274   /* Case of payload phase resumption =================================================*/
05275   else
05276   {
05277     if (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED)
05278     {
05279
05280       /* Set the phase */
05281       hcryp->Phase = CRYP_PHASE_PROCESS;
05282
05283       /* Select payload phase once the header phase is performed */
05284       MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
05285
05286       /* Set to 0 the number of non-valid bytes using NPBLB register*/
05287       MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
05288
05289       if (((hcryp->Size/4U) - (hcryp->CrypInCount)) >= 4U)
05290       {
05291         /* Write the input block in the IN FIFO */
05292         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
05293         hcryp->CrypInCount++;
05294         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
05295         hcryp->CrypInCount++;
05296         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
05297         hcryp->CrypInCount++;
05298         hcryp->Instance->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
05299         hcryp->CrypInCount++;
05300         if((hcryp->CrypInCount ==  hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC))
05301         {
05302           /* Call output transfer complete callback */
05303 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
05304           /*Call registered Input complete callback*/
05305           hcryp->InCpltCallback(hcryp);
05306 #else
05307           /*Call legacy weak Input complete callback*/
05308           HAL_CRYP_InCpltCallback(hcryp);
05309 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
05310         }
05311       }
05312       else /* Last block of payload < 128bit*/
05313       {
05314         /* Compute the number of padding bytes in last block of payload */
05315         npblb = (((hcryp->Size/16U)+1U)*16U) - (hcryp->Size);
05316         cr_temp = hcryp->Instance->CR;
05317         if((((cr_temp & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) ||
05318            (((cr_temp& AES_CR_MODE) == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
05319         {
05320           /* Specify the number of non-valid bytes using NPBLB register*/
05321             MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, ((uint32_t)npblb)<< 20U);
05322         }
05323
05324         /* Number of valid words (lastwordsize) in last block */
05325         if ((npblb % 4U) ==0U)
05326         {
05327           lastwordsize = (16U-npblb)/4U;
05328         }
05329         else
05330         {
05331           lastwordsize = ((16U-npblb)/4U) +1U;
05332         }
05333
05334         /*  Last block optionally pad the data with zeros*/
05335         for(loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
05336         {
05337           hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
05338           hcryp->CrypInCount++;
05339         }
05340         while(loopcounter < 4U )
05341         {
05342           /* pad the data with zeros to have a complete block */
05343           hcryp->Instance->DINR = 0x0U;
05344           loopcounter++;
05345         }
05346       }
05347     }
05348   }
05349 }
05350 #endif /* defined (USE_HAL_CRYP_SUSPEND_RESUME) */
05351 /**
05352   * @}
05353   */
05354
05355
05356 #endif /* HAL_CRYP_MODULE_ENABLED */
05357
05358
05359 /**
05360   * @}
05361   */
05362
05363 /**
05364  * @}
05365  */
05366 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_cryp.h Source File

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stm32wbxx_hal_cryp.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_cryp.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CRYP HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_CRYP_H
00022 #define STM32WBxx_HAL_CRYP_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 /** @addtogroup STM32WBxx_HAL_Driver
00032   * @{
00033   */
00034
00035
00036
00037 /** @defgroup CRYP CRYP
00038   * @brief CRYP HAL module driver.
00039   * @{
00040   */
00041
00042 /* Exported types ------------------------------------------------------------*/
00043
00044 /** @defgroup CRYP_Exported_Types CRYP Exported Types
00045   * @{
00046   */
00047
00048 /**
00049   * @brief CRYP Init Structure definition
00050   */
00051
00052 typedef struct
00053 {
00054   uint32_t DataType;                   /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
00055                                         This parameter can be a value of @ref CRYP_Data_Type */
00056   uint32_t KeySize;                    /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
00057                                         128 or 256 bit key length in TinyAES This parameter can be a value of @ref CRYP_Key_Size */
00058   uint32_t *pKey;                      /*!< The key used for encryption/decryption */
00059   uint32_t *pInitVect;                 /*!< The initialization vector used also as initialization
00060                                          counter in CTR mode */
00061   uint32_t Algorithm;                  /*!<  DES/ TDES Algorithm ECB/CBC
00062                                         AES Algorithm ECB/CBC/CTR/GCM or CCM
00063                                         This parameter can be a value of @ref CRYP_Algorithm_Mode */
00064   uint32_t *Header;                    /*!< used only in AES GCM and CCM Algorithm for authentication,
00065                                         GCM : also known as Additional Authentication Data
00066                                         CCM : named B1 composed of the associated data length and Associated Data. */
00067   uint32_t HeaderSize;                 /*!< The size of header buffer in word  */
00068   uint32_t *B0;                        /*!< B0 is first authentication block used only  in AES CCM mode */
00069   uint32_t DataWidthUnit;              /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
00070   uint32_t KeyIVConfigSkip;            /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization
00071                                            Vector only once and to skip configuration for consecutive processings.
00072                                            This parameter can be a value of @ref CRYP_Configuration_Skip */
00073
00074 } CRYP_ConfigTypeDef;
00075
00076
00077 /**
00078   * @brief  CRYP State Structure definition
00079   */
00080
00081 typedef enum
00082 {
00083   HAL_CRYP_STATE_RESET             = 0x00U,  /*!< CRYP not yet initialized or disabled  */
00084   HAL_CRYP_STATE_READY             = 0x01U,  /*!< CRYP initialized and ready for use    */
00085   HAL_CRYP_STATE_BUSY              = 0x02U,  /*!< CRYP BUSY, internal processing is ongoing  */
00086 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
00087   HAL_CRYP_STATE_SUSPENDED         = 0x03U,   /*!< CRYP suspended                        */
00088 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
00089 } HAL_CRYP_STATETypeDef;
00090
00091 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
00092 /**
00093   * @brief HAL CRYP mode suspend definitions
00094   */
00095 typedef enum
00096 {
00097   HAL_CRYP_SUSPEND_NONE            = 0x00U,    /*!< CRYP processing suspension not requested */
00098   HAL_CRYP_SUSPEND                 = 0x01U     /*!< CRYP processing suspension requested     */
00099 }HAL_SuspendTypeDef;
00100 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
00101
00102 /**
00103   * @brief  CRYP handle Structure definition
00104   */
00105 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
00106 typedef struct __CRYP_HandleTypeDef
00107 #else
00108 typedef struct
00109 #endif
00110 {
00111   AES_TypeDef                       *Instance;            /*!< AES Register base address */
00112
00113   CRYP_ConfigTypeDef                Init;             /*!< CRYP required parameters */
00114
00115   FunctionalState                   AutoKeyDerivation;   /*!< Used only in TinyAES to allow to bypass or not key write-up before decryption.
00116                                                          This parameter can be a value of ENABLE/DISABLE */
00117
00118   uint32_t                          *pCrypInBuffPtr;  /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
00119
00120   uint32_t                          *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
00121
00122   __IO uint16_t                     CrypHeaderCount;   /*!< Counter of header data */
00123
00124   __IO uint16_t                     CrypInCount;      /*!< Counter of input data */
00125
00126   __IO uint16_t                     CrypOutCount;     /*!< Counter of output data */
00127
00128   uint16_t                          Size;             /*!< length of input data in words */
00129
00130   uint32_t                          Phase;            /*!< CRYP peripheral phase */
00131
00132   DMA_HandleTypeDef                 *hdmain;          /*!< CRYP In DMA handle parameters */
00133
00134   DMA_HandleTypeDef                 *hdmaout;         /*!< CRYP Out DMA handle parameters */
00135
00136   HAL_LockTypeDef                   Lock;             /*!< CRYP locking object */
00137
00138   __IO  HAL_CRYP_STATETypeDef       State;            /*!< CRYP peripheral state */
00139
00140   __IO uint32_t                     ErrorCode;        /*!< CRYP peripheral error code */
00141
00142   uint32_t                          KeyIVConfig;      /*!< CRYP peripheral Key and IV configuration flag, used when
00143                                                            configuration can be skipped */
00144
00145   uint32_t                          SizesSum;         /*!< Sum of successive payloads lengths (in bytes), stored
00146                                                            for a single signature computation after several
00147                                                            messages processing */
00148
00149 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
00150   void (*InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp);      /*!< CRYP Input FIFO transfer completed callback  */
00151   void (*OutCpltCallback)(struct __CRYP_HandleTypeDef *hcryp);     /*!< CRYP Output FIFO transfer completed callback */
00152   void (*ErrorCallback)(struct __CRYP_HandleTypeDef *hcryp);       /*!< CRYP Error callback */
00153
00154   void (* MspInitCallback)(struct __CRYP_HandleTypeDef *hcryp);    /*!< CRYP Msp Init callback  */
00155   void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef *hcryp);  /*!< CRYP Msp DeInit callback  */
00156
00157 #endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
00158
00159 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
00160
00161   __IO HAL_SuspendTypeDef     SuspendRequest;          /*!< CRYP peripheral suspension request flag */
00162
00163   CRYP_ConfigTypeDef          Init_saved;              /*!< copy of CRYP required parameters when processing is suspended */
00164
00165   uint32_t                    *pCrypInBuffPtr_saved;   /*!< copy of CRYP input pointer when processing is suspended */
00166
00167   uint32_t                    *pCrypOutBuffPtr_saved;  /*!< copy of CRYP output pointer when processing is suspended */
00168
00169   uint32_t                    CrypInCount_saved;       /*!< copy of CRYP input data counter when processing is suspended */
00170
00171   uint32_t                    CrypOutCount_saved;      /*!< copy of CRYP output data counter when processing is suspended */
00172
00173   uint32_t                    Phase_saved;             /*!< copy of CRYP authentication phase when processing is suspended */
00174
00175   __IO HAL_CRYP_STATETypeDef  State_saved;             /*!< copy of CRYP peripheral state when processing is suspended */
00176
00177   uint32_t                    IV_saved[4];             /*!< copy of Initialisation Vector registers */
00178
00179   uint32_t                    SUSPxR_saved[8];         /*!< copy of suspension registers */
00180
00181   uint32_t                    CR_saved;                /*!< copy of CRYP control register  when processing is suspended*/
00182
00183   uint32_t                    Key_saved[8];            /*!< copy of key registers */
00184
00185   uint16_t                    Size_saved;              /*!< copy of input buffer size */
00186
00187   uint16_t                    CrypHeaderCount_saved;   /*!< copy of CRYP header data counter when processing is suspended */
00188
00189   uint32_t                    ResumingFlag;            /*!< resumption flag to bypass steps already carried out */
00190
00191   FunctionalState             AutoKeyDerivation_saved; /*!< copy of CRYP handle auto key derivation parameter */
00192
00193 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
00194
00195 } CRYP_HandleTypeDef;
00196
00197 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
00198 /** @defgroup HAL_CRYP_Callback_ID_enumeration_definition HAL CRYP Callback ID enumeration definition
00199   * @brief  HAL CRYP Callback ID enumeration definition
00200   * @{
00201   */
00202 typedef enum
00203 {
00204   HAL_CRYP_MSPINIT_CB_ID           = 0x00U,    /*!< CRYP MspInit callback ID                        */
00205   HAL_CRYP_MSPDEINIT_CB_ID         = 0x01U,     /*!< CRYP MspDeInit callback ID                      */
00206   HAL_CRYP_INPUT_COMPLETE_CB_ID    = 0x02U,    /*!< CRYP Input FIFO transfer completed callback ID  */
00207   HAL_CRYP_OUTPUT_COMPLETE_CB_ID   = 0x03U,    /*!< CRYP Output FIFO transfer completed callback ID */
00208   HAL_CRYP_ERROR_CB_ID             = 0x04U,    /*!< CRYP Error callback ID                          */
00209 } HAL_CRYP_CallbackIDTypeDef;
00210 /**
00211   * @}
00212   */
00213
00214 /** @defgroup HAL_CRYP_Callback_pointer_definition HAL CRYP Callback pointer definition
00215   * @brief  HAL CRYP Callback pointer definition
00216   * @{
00217   */
00218
00219 typedef  void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp);    /*!< pointer to a common CRYP callback function */
00220
00221 /**
00222   * @}
00223   */
00224
00225 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
00226
00227 /**
00228   * @}
00229   */
00230
00231 /* Exported constants --------------------------------------------------------*/
00232 /** @defgroup CRYP_Exported_Constants CRYP Exported Constants
00233   * @{
00234   */
00235
00236 /** @defgroup CRYP_Error_Definition   CRYP Error Definition
00237   * @{
00238   */
00239 #define HAL_CRYP_ERROR_NONE              0x00000000U  /*!< No error        */
00240 #define HAL_CRYP_ERROR_WRITE             0x00000001U  /*!< Write error     */
00241 #define HAL_CRYP_ERROR_READ              0x00000002U  /*!< Read error      */
00242 #define HAL_CRYP_ERROR_DMA               0x00000004U  /*!< DMA error       */
00243 #define HAL_CRYP_ERROR_BUSY              0x00000008U  /*!< Busy flag error */
00244 #define HAL_CRYP_ERROR_TIMEOUT           0x00000010U  /*!< Timeout error */
00245 #define HAL_CRYP_ERROR_NOT_SUPPORTED     0x00000020U  /*!< Not supported mode */
00246 #define HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U  /*!< Sequence are not respected only for GCM or CCM */
00247 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
00248 #define  HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U)    /*!< Invalid Callback error  */
00249 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
00250
00251 /**
00252   * @}
00253   */
00254
00255 /** @defgroup CRYP_Data_Width_Unit CRYP Data Width Unit
00256   * @{
00257   */
00258
00259 #define CRYP_DATAWIDTHUNIT_WORD   0x00000000U  /*!< By default, size unit is word */
00260 #define CRYP_DATAWIDTHUNIT_BYTE   0x00000001U  /*!< By default, size unit is byte */
00261
00262 /**
00263   * @}
00264   */
00265
00266 /** @defgroup CRYP_Algorithm_Mode CRYP Algorithm Mode
00267   * @{
00268   */
00269
00270 #define CRYP_AES_ECB            0x00000000U                       /*!< Electronic codebook chaining algorithm                   */
00271 #define CRYP_AES_CBC            AES_CR_CHMOD_0                    /*!< Cipher block chaining algorithm                          */
00272 #define CRYP_AES_CTR            AES_CR_CHMOD_1                    /*!< Counter mode chaining algorithm                          */
00273 #define CRYP_AES_GCM_GMAC       (AES_CR_CHMOD_0 | AES_CR_CHMOD_1) /*!< Galois counter mode - Galois message authentication code */
00274 #define CRYP_AES_CCM            AES_CR_CHMOD_2                    /*!< Counter with Cipher Mode                                 */
00275
00276 /**
00277   * @}
00278   */
00279
00280 /** @defgroup CRYP_Key_Size CRYP Key Size
00281   * @{
00282   */
00283
00284 #define CRYP_KEYSIZE_128B         0x00000000U          /*!< 128-bit long key */
00285 #define CRYP_KEYSIZE_256B         AES_CR_KEYSIZE       /*!< 256-bit long key */
00286
00287 /**
00288   * @}
00289   */
00290
00291 /** @defgroup CRYP_Data_Type CRYP Data Type
00292   * @{
00293   */
00294
00295 #define CRYP_DATATYPE_32B         0x00000000U  /*!< 32-bit data type (no swapping)        */
00296 #define CRYP_DATATYPE_16B         AES_CR_DATATYPE_0       /*!< 16-bit data type (half-word swapping) */
00297 #define CRYP_DATATYPE_8B          AES_CR_DATATYPE_1       /*!< 8-bit data type (byte swapping)       */
00298 #define CRYP_DATATYPE_1B          AES_CR_DATATYPE         /*!< 1-bit data type (bit swapping)        */
00299
00300 /**
00301   * @}
00302   */
00303
00304 /** @defgroup CRYP_Interrupt  CRYP Interrupt
00305   * @{
00306   */
00307
00308 #define CRYP_IT_CCFIE     AES_CR_CCFIE /*!< Computation Complete interrupt enable */
00309 #define CRYP_IT_ERRIE     AES_CR_ERRIE /*!< Error interrupt enable                */
00310 #define CRYP_IT_WRERR     AES_SR_WRERR  /*!< Write Error           */
00311 #define CRYP_IT_RDERR     AES_SR_RDERR  /*!< Read Error            */
00312 #define CRYP_IT_CCF       AES_SR_CCF    /*!< Computation completed */
00313
00314 /**
00315   * @}
00316   */
00317
00318 /** @defgroup CRYP_Flags CRYP Flags
00319   * @{
00320   */
00321
00322 /* status flags */
00323 #define CRYP_FLAG_BUSY    AES_SR_BUSY   /*!< GCM process suspension forbidden */
00324 #define CRYP_FLAG_WRERR   AES_SR_WRERR  /*!< Write Error                      */
00325 #define CRYP_FLAG_RDERR   AES_SR_RDERR  /*!< Read error                       */
00326 #define CRYP_FLAG_CCF     AES_SR_CCF    /*!< Computation completed            */
00327 /* clearing flags */
00328 #define CRYP_CCF_CLEAR    AES_CR_CCFC   /*!< Computation Complete Flag Clear */
00329 #define CRYP_ERR_CLEAR    AES_CR_ERRC   /*!< Error Flag Clear  */
00330
00331 /**
00332   * @}
00333   */
00334
00335 /** @defgroup CRYP_Configuration_Skip CRYP Key and IV Configuration Skip Mode
00336   * @{
00337   */
00338
00339 #define CRYP_KEYIVCONFIG_ALWAYS        0x00000000U            /*!< Peripheral Key and IV configuration to do systematically */
00340 #define CRYP_KEYIVCONFIG_ONCE          0x00000001U            /*!< Peripheral Key and IV configuration to do only once      */
00341
00342 /**
00343   * @}
00344   */
00345
00346
00347 /**
00348   * @}
00349   */
00350
00351 /* Exported macros -----------------------------------------------------------*/
00352 /** @defgroup CRYP_Exported_Macros CRYP Exported Macros
00353   * @{
00354   */
00355
00356 /** @brief Reset CRYP handle state
00357   * @param  __HANDLE__ specifies the CRYP handle.
00358   * @retval None
00359   */
00360 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
00361 #define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) do{\
00362                                                       (__HANDLE__)->State = HAL_CRYP_STATE_RESET;\
00363                                                       (__HANDLE__)->MspInitCallback = NULL;\
00364                                                       (__HANDLE__)->MspDeInitCallback = NULL;\
00365                                                      }while(0U)
00366 #else
00367 #define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_CRYP_STATE_RESET)
00368 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
00369
00370 /**
00371   * @brief  Enable/Disable the CRYP peripheral.
00372   * @param  __HANDLE__ specifies the CRYP handle.
00373   * @retval None
00374   */
00375
00376 #define __HAL_CRYP_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  AES_CR_EN)
00377 #define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &=  ~AES_CR_EN)
00378
00379
00380 /** @brief  Check whether the specified CRYP status flag is set or not.
00381   * @param  __HANDLE__ specifies the CRYP handle.
00382   * @param  __FLAG__ specifies the flag to check.
00383   *         This parameter can be one of the following values for TinyAES:
00384   *            @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden
00385   *            @arg @ref CRYP_IT_WRERR Write Error
00386   *            @arg @ref CRYP_IT_RDERR Read Error
00387   *            @arg @ref CRYP_IT_CCF Computation Complete
00388   *         This parameter can be one of the following values for CRYP:
00389   *            @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
00390   *                                 or a key preparation (for AES decryption).
00391   *            @arg CRYP_FLAG_IFEM: Input FIFO is empty
00392   *            @arg CRYP_FLAG_IFNF: Input FIFO is not full
00393   *            @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending
00394   *            @arg CRYP_FLAG_OFNE: Output FIFO is not empty
00395   *            @arg CRYP_FLAG_OFFU: Output FIFO is full
00396   *            @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
00397  * @retval The state of __FLAG__ (TRUE or FALSE).
00398   */
00399
00400 #define CRYP_FLAG_MASK  0x0000001FU
00401 #define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
00402
00403 /** @brief  Clear the CRYP pending status flag.
00404   * @param  __HANDLE__ specifies the CRYP handle.
00405   * @param  __FLAG__ specifies the flag to clear.
00406   *         This parameter can be one of the following values:
00407   *            @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
00408   *            @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
00409   * @retval None
00410   */
00411
00412 #define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT((__HANDLE__)->Instance->CR, (__FLAG__))
00413
00414
00415 /** @brief  Check whether the specified CRYP interrupt source is enabled or not.
00416   * @param  __HANDLE__ specifies the CRYP handle.
00417   * @param __INTERRUPT__ CRYP interrupt source to check
00418   *         This parameter can be one of the following values for TinyAES:
00419   *            @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
00420   *            @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
00421   * @retval State of interruption (TRUE or FALSE).
00422   */
00423
00424 #define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
00425
00426 /** @brief  Check whether the specified CRYP interrupt is set or not.
00427   * @param  __HANDLE__ specifies the CRYP handle.
00428   * @param  __INTERRUPT__ specifies the interrupt to check.
00429   *         This parameter can be one of the following values for TinyAES:
00430   *            @arg @ref CRYP_IT_WRERR Write Error
00431   *            @arg @ref CRYP_IT_RDERR Read Error
00432   *            @arg @ref CRYP_IT_CCF  Computation Complete
00433   *         This parameter can be one of the following values for CRYP:
00434   *            @arg CRYP_IT_INI: Input FIFO service masked interrupt status
00435   *            @arg CRYP_IT_OUTI: Output FIFO service masked interrupt status
00436   * @retval The state of __INTERRUPT__ (TRUE or FALSE).
00437   */
00438
00439 #define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
00440
00441 /**
00442   * @brief  Enable the CRYP interrupt.
00443   * @param  __HANDLE__ specifies the CRYP handle.
00444   * @param  __INTERRUPT__ CRYP Interrupt.
00445   *         This parameter can be one of the following values for TinyAES:
00446   *            @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
00447   *            @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
00448   *         This parameter can be one of the following values for CRYP:
00449   *            @ CRYP_IT_INI : Input FIFO service interrupt mask.
00450   *            @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
00451   * @retval None
00452   */
00453
00454 #define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
00455
00456 /**
00457   * @brief  Disable the CRYP interrupt.
00458   * @param  __HANDLE__ specifies the CRYP handle.
00459   * @param  __INTERRUPT__ CRYP Interrupt.
00460   *         This parameter can be one of the following values for TinyAES:
00461   *            @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
00462   *            @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
00463   *         This parameter can be one of the following values for CRYP:
00464   *            @ CRYP_IT_INI : Input FIFO service interrupt mask.
00465   *            @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
00466   * @retval None
00467   */
00468
00469 #define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
00470
00471 /**
00472   * @}
00473   */
00474
00475 /* Include CRYP HAL Extended module */
00476 #include "stm32wbxx_hal_cryp_ex.h"
00477
00478 /* Exported functions --------------------------------------------------------*/
00479 /** @defgroup CRYP_Exported_Functions CRYP Exported Functions
00480   * @{
00481   */
00482
00483 /** @addtogroup CRYP_Exported_Functions_Group1
00484   * @{
00485   */
00486 HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
00487 HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
00488 void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
00489 void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
00490 HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
00491 HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
00492 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
00493 HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback);
00494 HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID);
00495 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
00496 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
00497 void HAL_CRYP_ProcessSuspend(CRYP_HandleTypeDef *hcryp);
00498 HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp);
00499 HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp);
00500 #endif /* defined (USE_HAL_CRYP_SUSPEND_RESUME) */
00501 /**
00502   * @}
00503   */
00504
00505 /** @addtogroup CRYP_Exported_Functions_Group2
00506   * @{
00507   */
00508
00509 /* encryption/decryption ***********************************/
00510 HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
00511 HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
00512 HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
00513 HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
00514 HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
00515 HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
00516
00517 /**
00518   * @}
00519   */
00520
00521
00522 /** @addtogroup CRYP_Exported_Functions_Group3
00523   * @{
00524   */
00525 /* Interrupt Handler functions  **********************************************/
00526 void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
00527 HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
00528 void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
00529 void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
00530 void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
00531 uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
00532
00533 /**
00534   * @}
00535   */
00536
00537 /**
00538   * @}
00539   */
00540
00541 /* Private macros --------------------------------------------------------*/
00542 /** @defgroup CRYP_Private_Macros CRYP Private Macros
00543   * @{
00544   */
00545
00546 /** @defgroup CRYP_IS_CRYP_Definitions CRYP Private macros to check input parameters
00547   * @{
00548   */
00549
00550 #define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_AES_ECB)      || \
00551                                       ((ALGORITHM)  == CRYP_AES_CBC)     || \
00552                                       ((ALGORITHM)  == CRYP_AES_CTR)     || \
00553                                       ((ALGORITHM)  == CRYP_AES_GCM_GMAC)|| \
00554                                       ((ALGORITHM)  == CRYP_AES_CCM))
00555
00556
00557 #define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B)   || \
00558                                  ((KEYSIZE) == CRYP_KEYSIZE_256B))
00559
00560 #define IS_CRYP_DATATYPE(DATATYPE)(((DATATYPE) == CRYP_DATATYPE_32B) || \
00561                                    ((DATATYPE) == CRYP_DATATYPE_16B) || \
00562                                    ((DATATYPE) == CRYP_DATATYPE_8B)  || \
00563                                    ((DATATYPE) == CRYP_DATATYPE_1B))
00564
00565 #define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \
00566                              ((CONFIG) == CRYP_KEYIVCONFIG_ONCE))
00567
00568 #define IS_CRYP_BUFFERSIZE(ALGO, DATAWIDTH, SIZE)                                             \
00569       (((((ALGO) == CRYP_AES_ECB) || ((ALGO) == CRYP_AES_CBC) || ((ALGO) == CRYP_AES_CTR)) && \
00570             ((((DATAWIDTH) == CRYP_DATAWIDTHUNIT_WORD) && (((SIZE) % 4U) == 0U))           || \
00571              (((DATAWIDTH) == CRYP_DATAWIDTHUNIT_BYTE) && (((SIZE) % 16U) == 0U))))        || \
00572         (((ALGO)== CRYP_AES_GCM_GMAC) || ((ALGO) == CRYP_AES_CCM)))
00573
00574 /**
00575   * @}
00576   */
00577
00578 /**
00579   * @}
00580   */
00581
00582
00583 /* Private constants ---------------------------------------------------------*/
00584 /** @defgroup CRYP_Private_Constants CRYP Private Constants
00585   * @{
00586   */
00587
00588 /**
00589   * @}
00590   */
00591 /* Private defines -----------------------------------------------------------*/
00592 /** @defgroup CRYP_Private_Defines CRYP Private Defines
00593   * @{
00594   */
00595
00596 /**
00597   * @}
00598   */
00599
00600 /* Private variables ---------------------------------------------------------*/
00601 /** @defgroup CRYP_Private_Variables CRYP Private Variables
00602   * @{
00603   */
00604
00605 /**
00606   * @}
00607   */
00608
00609 /* Private functions ---------------------------------------------------------*/
00610 /** @defgroup CRYP_Private_Functions CRYP Private Functions
00611   * @{
00612   */
00613
00614 /**
00615   * @}
00616   */
00617
00618 /**
00619   * @}
00620   */
00621
00622
00623 /**
00624   * @}
00625   */
00626
00627 #ifdef __cplusplus
00628 }
00629 #endif
00630
00631 #endif /* STM32WBxx_HAL_CRYP_H */
00632
00633 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_cryp_ex.c Source File

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stm32wbxx_hal_cryp_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_cryp_ex.c
00004   * @author  MCD Application Team
00005   * @brief   CRYPEx HAL module driver.
00006   *          This file provides firmware functions to manage the extended
00007   *          functionalities of the Cryptography (CRYP) peripheral.
00008   *
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00013   * All rights reserved.</center></h2>
00014   *
00015   * This software component is licensed by ST under BSD 3-Clause license,
00016   * the "License"; You may not use this file except in compliance with the
00017   * License. You may obtain a copy of the License at:
00018   *                        opensource.org/licenses/BSD-3-Clause
00019   *
00020   ******************************************************************************
00021   */
00022
00023 /* Includes ------------------------------------------------------------------*/
00024 #include "stm32wbxx_hal.h"
00025
00026 /** @addtogroup STM32WBxx_HAL_Driver
00027   * @{
00028   */
00029
00030 /** @addtogroup CRYPEx
00031   * @{
00032   */
00033
00034
00035
00036 #ifdef HAL_CRYP_MODULE_ENABLED
00037
00038 /* Private typedef -----------------------------------------------------------*/
00039 /* Private define ------------------------------------------------------------*/
00040 /** @addtogroup CRYPEx_Private_Defines
00041   * @{
00042   */
00043
00044 #define CRYP_PHASE_INIT                              0x00000000U             /*!< GCM/GMAC (or CCM) init phase */
00045 #define CRYP_PHASE_HEADER                            AES_CR_GCMPH_0          /*!< GCM/GMAC or CCM header phase */
00046 #define CRYP_PHASE_PAYLOAD                           AES_CR_GCMPH_1          /*!< GCM(/CCM) payload phase   */
00047 #define CRYP_PHASE_FINAL                             AES_CR_GCMPH            /*!< GCM/GMAC or CCM  final phase  */
00048
00049 #define CRYP_OPERATINGMODE_ENCRYPT                   0x00000000U             /*!< Encryption mode   */
00050 #define CRYP_OPERATINGMODE_KEYDERIVATION             AES_CR_MODE_0           /*!< Key derivation mode  only used when performing ECB and CBC decryptions  */
00051 #define CRYP_OPERATINGMODE_DECRYPT                   AES_CR_MODE_1           /*!< Decryption       */
00052 #define CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT     AES_CR_MODE             /*!< Key derivation and decryption only used when performing ECB and CBC decryptions  */
00053
00054 #define  CRYPEx_PHASE_PROCESS       0x02U     /*!< CRYP peripheral is in processing phase */
00055 #define  CRYPEx_PHASE_FINAL         0x03U     /*!< CRYP peripheral is in final phase this is relevant only with CCM and GCM modes */
00056
00057 /*  CTR0 information to use in CCM algorithm */
00058 #define CRYP_CCM_CTR0_0            0x07FFFFFFU
00059 #define CRYP_CCM_CTR0_3            0xFFFFFF00U
00060
00061 /**
00062   * @}
00063   */
00064
00065 /* Private macro -------------------------------------------------------------*/
00066 /* Private variables ---------------------------------------------------------*/
00067 /* Private function prototypes -----------------------------------------------*/
00068
00069 /* Exported functions---------------------------------------------------------*/
00070 /** @addtogroup CRYPEx_Exported_Functions
00071   * @{
00072   */
00073
00074 /** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions
00075  *  @brief   Extended processing functions.
00076  *
00077 @verbatim
00078   ==============================================================================
00079               ##### Extended AES processing functions #####
00080   ==============================================================================
00081     [..]  This section provides functions allowing to generate the authentication
00082           TAG in Polling mode
00083       (#)HAL_CRYPEx_AESGCM_GenerateAuthTAG
00084       (#)HAL_CRYPEx_AESCCM_GenerateAuthTAG
00085          they should be used after Encrypt/Decrypt operation.
00086
00087 @endverbatim
00088   * @{
00089   */
00090
00091 /**
00092   * @brief  generate the GCM authentication TAG.
00093   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
00094   *         the configuration information for CRYP module
00095   * @param  AuthTag Pointer to the authentication buffer
00096   * @param  Timeout Timeout duration
00097   * @retval HAL status
00098   */
00099 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
00100 {
00101   uint32_t tickstart;
00102   uint64_t headerlength = (uint64_t)hcryp->Init.HeaderSize * 32U; /* Header length in bits */
00103   uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* input length in bits */
00104   uint32_t tagaddr = (uint32_t)AuthTag;
00105
00106   if (hcryp->State == HAL_CRYP_STATE_READY)
00107   {
00108     /* Process locked */
00109     __HAL_LOCK(hcryp);
00110
00111     /* Change the CRYP peripheral state */
00112     hcryp->State = HAL_CRYP_STATE_BUSY;
00113
00114     /* Check if initialization phase has already been performed */
00115     if (hcryp->Phase == CRYPEx_PHASE_PROCESS)
00116     {
00117       /* Change the CRYP phase */
00118       hcryp->Phase = CRYPEx_PHASE_FINAL;
00119     }
00120     else /* Initialization phase has not been performed*/
00121     {
00122       /* Disable the Peripheral */
00123       __HAL_CRYP_DISABLE(hcryp);
00124
00125       /* Sequence error code field */
00126       hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE;
00127
00128       /* Change the CRYP peripheral state */
00129       hcryp->State = HAL_CRYP_STATE_READY;
00130
00131       /* Process unlocked */
00132       __HAL_UNLOCK(hcryp);
00133       return HAL_ERROR;
00134     }
00135
00136     /* Select final phase */
00137     MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL);
00138
00139     /* Set the encrypt operating mode*/
00140     MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
00141
00142     /*TinyAES peripheral from V3.1.1 : data has to be inserted normally (no swapping)*/
00143     /* Write into the AES_DINR register the number of bits in header (64 bits)
00144     followed by the number of bits in the payload */
00145
00146     hcryp->Instance->DINR = 0U;
00147     hcryp->Instance->DINR = (uint32_t)(headerlength);
00148     hcryp->Instance->DINR = 0U;
00149     hcryp->Instance->DINR = (uint32_t)(inputlength);
00150
00151     /* Wait for CCF flag to be raised */
00152     tickstart = HAL_GetTick();
00153     while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
00154     {
00155       /* Check for the Timeout */
00156       if (Timeout != HAL_MAX_DELAY)
00157       {
00158         if (((HAL_GetTick() - tickstart) > Timeout)||(Timeout == 0U))
00159         {
00160           /* Disable the CRYP peripheral clock */
00161           __HAL_CRYP_DISABLE(hcryp);
00162
00163           /* Change state */
00164           hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
00165           hcryp->State = HAL_CRYP_STATE_READY;
00166
00167           /* Process unlocked */
00168           __HAL_UNLOCK(hcryp);
00169           return HAL_ERROR;
00170         }
00171       }
00172     }
00173
00174     /* Read the authentication TAG in the output FIFO */
00175     *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
00176     tagaddr += 4U;
00177     *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
00178     tagaddr += 4U;
00179     *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
00180     tagaddr += 4U;
00181     *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
00182
00183     /* Clear CCF flag */
00184     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
00185
00186     /* Disable the peripheral */
00187     __HAL_CRYP_DISABLE(hcryp);
00188
00189     /* Change the CRYP peripheral state */
00190     hcryp->State = HAL_CRYP_STATE_READY;
00191
00192     /* Process unlocked */
00193     __HAL_UNLOCK(hcryp);
00194   }
00195   else
00196   {
00197     /* Busy error code field */
00198     hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
00199     return HAL_ERROR;
00200   }
00201   /* Return function status */
00202   return HAL_OK;
00203 }
00204
00205 /**
00206   * @brief  AES CCM Authentication TAG generation.
00207   * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
00208   *         the configuration information for CRYP module
00209   * @param  AuthTag Pointer to the authentication buffer
00210   * @param  Timeout Timeout duration
00211   * @retval HAL status
00212   */
00213 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
00214 {
00215   uint32_t tagaddr = (uint32_t)AuthTag;
00216   uint32_t tickstart;
00217
00218   if (hcryp->State == HAL_CRYP_STATE_READY)
00219   {
00220     /* Process locked */
00221     __HAL_LOCK(hcryp);
00222
00223     /* Disable interrupts in case they were kept enabled to proceed
00224        a single message in several iterations */
00225     __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
00226
00227     /* Change the CRYP peripheral state */
00228     hcryp->State = HAL_CRYP_STATE_BUSY;
00229
00230     /* Check if initialization phase has already been performed */
00231     if (hcryp->Phase == CRYPEx_PHASE_PROCESS)
00232     {
00233       /* Change the CRYP phase */
00234       hcryp->Phase = CRYPEx_PHASE_FINAL;
00235     }
00236     else /* Initialization phase has not been performed*/
00237     {
00238       /* Disable the peripheral */
00239       __HAL_CRYP_DISABLE(hcryp);
00240
00241       /* Sequence error code field */
00242       hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE;
00243
00244       /* Change the CRYP peripheral state */
00245       hcryp->State = HAL_CRYP_STATE_READY;
00246
00247       /* Process unlocked */
00248       __HAL_UNLOCK(hcryp);
00249       return HAL_ERROR;
00250     }
00251     /* Select final phase */
00252     MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL);
00253
00254     /* Set encrypt  operating mode*/
00255     MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
00256
00257     /* Wait for CCF flag to be raised */
00258     tickstart = HAL_GetTick();
00259     while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
00260     {
00261       /* Check for the Timeout */
00262       if (Timeout != HAL_MAX_DELAY)
00263       {
00264         if (((HAL_GetTick() - tickstart) > Timeout) ||(Timeout == 0U))
00265         {
00266           /* Disable the CRYP peripheral Clock */
00267           __HAL_CRYP_DISABLE(hcryp);
00268
00269           /* Change state */
00270           hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
00271           hcryp->State = HAL_CRYP_STATE_READY;
00272
00273           /* Process unlocked */
00274           __HAL_UNLOCK(hcryp);
00275           return HAL_ERROR;
00276         }
00277       }
00278     }
00279
00280     /* Read the authentication TAG in the output FIFO */
00281     *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
00282     tagaddr += 4U;
00283     *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
00284     tagaddr += 4U;
00285     *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
00286     tagaddr += 4U;
00287     *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
00288
00289     /* Clear CCF Flag */
00290     __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
00291
00292
00293     /* Change the CRYP peripheral state */
00294     hcryp->State = HAL_CRYP_STATE_READY;
00295
00296     /* Process unlocked */
00297     __HAL_UNLOCK(hcryp);
00298
00299     /* Disable CRYP  */
00300     __HAL_CRYP_DISABLE(hcryp);
00301   }
00302   else
00303   {
00304     /* Busy error code field */
00305     hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY;
00306     return HAL_ERROR;
00307   }
00308   /* Return function status */
00309   return HAL_OK;
00310 }
00311
00312 /**
00313   * @}
00314   */
00315
00316 /** @defgroup CRYPEx_Exported_Functions_Group2 Extended AES Key Derivations functions
00317   * @brief   Extended Key Derivations functions.
00318   *
00319 @verbatim
00320   ==============================================================================
00321               ##### Key Derivation functions #####
00322   ==============================================================================
00323     [..]  This section provides functions allowing to Enable or Disable the
00324           the AutoKeyDerivation parameter in CRYP_HandleTypeDef structure
00325           These function are allowed only in TinyAES peripheral.
00326 @endverbatim
00327   * @{
00328   */
00329
00330 /**
00331   * @brief  AES enable key derivation functions
00332   * @param  hcryp pointer to a CRYP_HandleTypeDef structure.
00333   */
00334 void  HAL_CRYPEx_EnableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp)
00335 {
00336   if (hcryp->State == HAL_CRYP_STATE_READY)
00337   {
00338     hcryp->AutoKeyDerivation = ENABLE;
00339   }
00340   else
00341   {
00342     /* Busy error code field */
00343     hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY;
00344   }
00345 }
00346 /**
00347   * @brief  AES disable key derivation functions
00348   * @param  hcryp pointer to a CRYP_HandleTypeDef structure.
00349   */
00350 void  HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp)
00351 {
00352   if (hcryp->State == HAL_CRYP_STATE_READY)
00353   {
00354     hcryp->AutoKeyDerivation = DISABLE;
00355   }
00356   else
00357   {
00358     /* Busy error code field */
00359     hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY;
00360   }
00361 }
00362
00363 /**
00364   * @}
00365   */
00366
00367 /**
00368   * @}
00369   */
00370
00371 #endif /* HAL_CRYP_MODULE_ENABLED */
00372
00373
00374 /**
00375   * @}
00376   */
00377
00378 /**
00379   * @}
00380   */
00381
00382 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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STM32WB55xx HAL User Manual: stm32wbxx_hal_cryp_ex.h Source File

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stm32wbxx_hal_cryp_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_cryp_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CRYPEx HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_CRYP_EX_H
00022 #define STM32WBxx_HAL_CRYP_EX_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 /** @addtogroup STM32WBxx_HAL_Driver
00032   * @{
00033   */
00034
00035
00036
00037 /** @defgroup CRYPEx CRYPEx
00038   * @brief CRYP Extension HAL module driver.
00039   * @{
00040   */
00041
00042 /* Exported types ------------------------------------------------------------*/
00043 /* Exported constants --------------------------------------------------------*/
00044 /* Private types -------------------------------------------------------------*/
00045 /** @defgroup CRYPEx_Private_Types CRYPEx Private Types
00046   * @{
00047   */
00048
00049 /**
00050   * @}
00051   */
00052
00053 /* Private variables ---------------------------------------------------------*/
00054 /** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables
00055   * @{
00056   */
00057
00058 /**
00059   * @}
00060   */
00061
00062 /* Private constants ---------------------------------------------------------*/
00063 /** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants
00064   * @{
00065   */
00066
00067 /**
00068   * @}
00069   */
00070
00071 /* Private macros ------------------------------------------------------------*/
00072 /** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros
00073   * @{
00074   */
00075
00076 /**
00077  * @}
00078  */
00079
00080 /* Private functions ---------------------------------------------------------*/
00081 /** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
00082   * @{
00083   */
00084
00085 /**
00086   * @}
00087   */
00088
00089 /* Exported functions --------------------------------------------------------*/
00090 /** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
00091   * @{
00092   */
00093
00094 /** @addtogroup CRYPEx_Exported_Functions_Group1
00095   * @{
00096   */
00097 HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
00098 HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
00099
00100 /**
00101   * @}
00102   */
00103
00104 /** @addtogroup CRYPEx_Exported_Functions_Group2
00105   * @{
00106   */
00107 void  HAL_CRYPEx_EnableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
00108 void  HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
00109
00110 /**
00111   * @}
00112   */
00113
00114 /**
00115   * @}
00116   */
00117
00118 /**
00119   * @}
00120   */
00121
00122
00123 /**
00124   * @}
00125   */
00126
00127 #ifdef __cplusplus
00128 }
00129 #endif
00130
00131 #endif /* STM32WBxx_HAL_CRYP_EX_H */
00132
00133 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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STM32WB55xx HAL User Manual: stm32wbxx_hal_dma.c Source File

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stm32wbxx_hal_dma.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_dma.c
00004   * @author  MCD Application Team
00005   * @brief   DMA HAL module driver.
00006   *         This file provides firmware functions to manage the following
00007   *         functionalities of the Direct Memory Access (DMA) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral State and errors functions
00011   @verbatim
00012   ==============================================================================
00013                         ##### How to use this driver #####
00014   ==============================================================================
00015   [..]
00016    (#) Enable and configure the peripheral to be connected to the DMA Channel
00017        (except for internal SRAM / FLASH memories: no initialization is
00018        necessary). Please refer to the Reference manual for connection between peripherals
00019        and DMA requests.
00020
00021    (#) For a given Channel, program the required configuration through the following parameters:
00022        Channel request, Transfer Direction, Source and Destination data formats,
00023        Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
00024        using HAL_DMA_Init() function.
00025
00026        Prior to HAL_DMA_Init the peripheral clock shall be enabled for both DMA & DMAMUX
00027        thanks to:
00028       (##) DMA1 or DMA2: __HAL_RCC_DMA1_CLK_ENABLE() or  __HAL_RCC_DMA2_CLK_ENABLE() ;
00029       (##) DMAMUX1:      __HAL_RCC_DMAMUX1_CLK_ENABLE();
00030
00031    (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
00032        detection.
00033
00034    (#) Use HAL_DMA_Abort() function to abort the current transfer
00035
00036      -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
00037
00038      *** Polling mode IO operation ***
00039      =================================
00040     [..]
00041           (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
00042               address and destination address and the Length of data to be transferred
00043           (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
00044               case a fixed Timeout can be configured by User depending from his application.
00045
00046      *** Interrupt mode IO operation ***
00047      ===================================
00048     [..]
00049           (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
00050           (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
00051           (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
00052               Source address and destination address and the Length of data to be transferred.
00053               In this case the DMA interrupt is configured
00054           (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
00055           (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
00056               add his own function to register callbacks with HAL_DMA_RegisterCallback().
00057
00058      *** DMA HAL driver macros list ***
00059      =============================================
00060       [..]
00061        Below the list of macros in DMA HAL driver.
00062
00063        (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
00064        (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
00065        (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
00066        (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
00067        (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
00068        (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
00069        (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt is enabled or not.
00070
00071      [..]
00072       (@) You can refer to the DMA HAL driver header file for more useful macros
00073
00074   @endverbatim
00075   ******************************************************************************
00076   * @attention
00077   *
00078   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00079   * All rights reserved.</center></h2>
00080   *
00081   * This software component is licensed by ST under BSD 3-Clause license,
00082   * the "License"; You may not use this file except in compliance with the
00083   * License. You may obtain a copy of the License at:
00084   *                        opensource.org/licenses/BSD-3-Clause
00085   *
00086   ******************************************************************************
00087   */
00088
00089 /* Includes ------------------------------------------------------------------*/
00090 #include "stm32wbxx_hal.h"
00091
00092 /** @addtogroup STM32WBxx_HAL_Driver
00093   * @{
00094   */
00095
00096 /** @defgroup DMA DMA
00097   * @brief DMA HAL module driver
00098   * @{
00099   */
00100
00101 #ifdef HAL_DMA_MODULE_ENABLED
00102
00103 /* Private typedef -----------------------------------------------------------*/
00104 /* Private define ------------------------------------------------------------*/
00105 /* Private macro -------------------------------------------------------------*/
00106 /* Private variables ---------------------------------------------------------*/
00107 /* Private function prototypes -----------------------------------------------*/
00108 /** @defgroup DMA_Private_Functions DMA Private Functions
00109   * @{
00110   */
00111 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
00112 static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma);
00113 static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma);
00114
00115 /**
00116   * @}
00117   */
00118
00119 /* Exported functions ---------------------------------------------------------*/
00120
00121 /** @defgroup DMA_Exported_Functions DMA Exported Functions
00122   * @{
00123   */
00124
00125 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
00126  *  @brief   Initialization and de-initialization functions
00127  *
00128 @verbatim
00129  ===============================================================================
00130              ##### Initialization and de-initialization functions  #####
00131  ===============================================================================
00132     [..]
00133     This section provides functions allowing to initialize the DMA Channel source
00134     and destination addresses, incrementation and data sizes, transfer direction,
00135     circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
00136     [..]
00137     The HAL_DMA_Init() function follows the DMA configuration procedures as described in
00138     reference manual.
00139
00140 @endverbatim
00141   * @{
00142   */
00143
00144 /**
00145   * @brief  Initialize the DMA according to the specified
00146   *         parameters in the DMA_InitTypeDef and initialize the associated handle.
00147   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
00148   *               the configuration information for the specified DMA Channel.
00149   * @retval HAL status
00150   */
00151 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
00152 {
00153   uint32_t tmp;
00154
00155   /* Check the DMA handle allocation */
00156   if (hdma == NULL)
00157   {
00158     return HAL_ERROR;
00159   }
00160
00161   /* Check the parameters */
00162   assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
00163   assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
00164   assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
00165   assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
00166   assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
00167   assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
00168   assert_param(IS_DMA_MODE(hdma->Init.Mode));
00169   assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
00170
00171   assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request));
00172
00173 #if defined(DMA2)
00174   /* Compute the channel index */
00175   if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
00176   {
00177     /* DMA1 */
00178     hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
00179     hdma->DmaBaseAddress = DMA1;
00180   }
00181   else
00182   {
00183     /* DMA2 */
00184     hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
00185     hdma->DmaBaseAddress = DMA2;
00186   }
00187 #else
00188   /* DMA1 */
00189   hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
00190   hdma->DmaBaseAddress = DMA1;
00191 #endif
00192
00193   /* Change DMA peripheral state */
00194   hdma->State = HAL_DMA_STATE_BUSY;
00195
00196   /* Get the CR register value */
00197   tmp = hdma->Instance->CCR;
00198
00199   /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */
00200   tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  |
00201                       DMA_CCR_MINC  | DMA_CCR_PINC   | DMA_CCR_CIRC   |
00202                       DMA_CCR_DIR   | DMA_CCR_MEM2MEM));
00203
00204   /* Prepare the DMA Channel configuration */
00205   tmp |=  hdma->Init.Direction        |
00206           hdma->Init.PeriphInc           | hdma->Init.MemInc           |
00207           hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
00208           hdma->Init.Mode                | hdma->Init.Priority;
00209
00210   /* Write to DMA Channel CR register */
00211   hdma->Instance->CCR = tmp;
00212
00213   /* Initialize parameters for DMAMUX channel :
00214      DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask
00215   */
00216   DMA_CalcDMAMUXChannelBaseAndMask(hdma);
00217
00218   if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
00219   {
00220     /* if memory to memory force the request to 0*/
00221     hdma->Init.Request = DMA_REQUEST_MEM2MEM;
00222   }
00223
00224   /* Set peripheral request  to DMAMUX channel */
00225   hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
00226
00227   /* Clear the DMAMUX synchro overrun flag */
00228   hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
00229
00230   if (((hdma->Init.Request >  0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
00231   {
00232     /* Initialize parameters for DMAMUX request generator :
00233        DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
00234     */
00235     DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
00236
00237     /* Reset the DMAMUX request generator register*/
00238     hdma->DMAmuxRequestGen->RGCR = 0U;
00239
00240     /* Clear the DMAMUX request generator overrun flag */
00241     hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
00242   }
00243   else
00244   {
00245     hdma->DMAmuxRequestGen = 0U;
00246     hdma->DMAmuxRequestGenStatus = 0U;
00247     hdma->DMAmuxRequestGenStatusMask = 0U;
00248   }
00249
00250   /* Initialize the error code */
00251   hdma->ErrorCode = HAL_DMA_ERROR_NONE;
00252
00253   /* Initialize the DMA state*/
00254   hdma->State  = HAL_DMA_STATE_READY;
00255
00256   /* Allocate lock resource and initialize it */
00257   hdma->Lock = HAL_UNLOCKED;
00258
00259   return HAL_OK;
00260 }
00261
00262 /**
00263   * @brief  DeInitialize the DMA peripheral.
00264   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
00265   *               the configuration information for the specified DMA Channel.
00266   * @retval HAL status
00267   */
00268 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
00269 {
00270
00271   /* Check the DMA handle allocation */
00272   if (NULL == hdma)
00273   {
00274     return HAL_ERROR;
00275   }
00276
00277   /* Check the parameters */
00278   assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
00279
00280   /* Disable the selected DMA Channelx */
00281   __HAL_DMA_DISABLE(hdma);
00282
00283 #if defined(DMA2)
00284   /* Compute the channel index */
00285   if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
00286   {
00287     /* DMA1 */
00288     hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
00289     hdma->DmaBaseAddress = DMA1;
00290   }
00291   else
00292   {
00293     /* DMA2 */
00294     hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
00295     hdma->DmaBaseAddress = DMA2;
00296   }
00297 #else
00298   /* DMA1 */
00299   hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
00300   hdma->DmaBaseAddress = DMA1;
00301 #endif
00302
00303   /* Reset DMA Channel control register */
00304   hdma->Instance->CCR  = 0U;
00305
00306   /* Clear all flags */
00307   hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
00308
00309   /* Initialize parameters for DMAMUX channel :
00310      DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */
00311
00312   DMA_CalcDMAMUXChannelBaseAndMask(hdma);
00313
00314   /* Reset the DMAMUX channel that corresponds to the DMA channel */
00315   hdma->DMAmuxChannel->CCR = 0U;
00316
00317   /* Clear the DMAMUX synchro overrun flag */
00318   hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
00319
00320   /* Reset Request generator parameters if any */
00321   if (((hdma->Init.Request >  0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
00322   {
00323     /* Initialize parameters for DMAMUX request generator :
00324        DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
00325     */
00326     DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
00327
00328     /* Reset the DMAMUX request generator register*/
00329     hdma->DMAmuxRequestGen->RGCR = 0U;
00330
00331     /* Clear the DMAMUX request generator overrun flag */
00332     hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
00333   }
00334
00335   hdma->DMAmuxRequestGen = 0U;
00336   hdma->DMAmuxRequestGenStatus = 0U;
00337   hdma->DMAmuxRequestGenStatusMask = 0U;
00338
00339   /* Clean callbacks */
00340   hdma->XferCpltCallback = NULL;
00341   hdma->XferHalfCpltCallback = NULL;
00342   hdma->XferErrorCallback = NULL;
00343   hdma->XferAbortCallback = NULL;
00344
00345   /* Initialize the error code */
00346   hdma->ErrorCode = HAL_DMA_ERROR_NONE;
00347
00348   /* Initialize the DMA state */
00349   hdma->State = HAL_DMA_STATE_RESET;
00350
00351   /* Release Lock */
00352   __HAL_UNLOCK(hdma);
00353
00354   return HAL_OK;
00355 }
00356
00357 /**
00358   * @}
00359   */
00360
00361 /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
00362  *  @brief   Input and Output operation functions
00363  *
00364 @verbatim
00365  ===============================================================================
00366                       #####  IO operation functions  #####
00367  ===============================================================================
00368     [..]  This section provides functions allowing to:
00369       (+) Configure the source, destination address and data length and Start DMA transfer
00370       (+) Configure the source, destination address and data length and
00371           Start DMA transfer with interrupt
00372       (+) Abort DMA transfer
00373       (+) Poll for transfer complete
00374       (+) Handle DMA interrupt request
00375
00376 @endverbatim
00377   * @{
00378   */
00379
00380 /**
00381   * @brief  Start the DMA Transfer.
00382   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
00383   *               the configuration information for the specified DMA Channel.
00384   * @param SrcAddress The source memory Buffer address
00385   * @param DstAddress The destination memory Buffer address
00386   * @param DataLength The length of data to be transferred from source to destination
00387   * @retval HAL status
00388   */
00389 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
00390 {
00391   HAL_StatusTypeDef status = HAL_OK;
00392
00393   /* Check the parameters */
00394   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
00395
00396   /* Process locked */
00397   __HAL_LOCK(hdma);
00398
00399   if (HAL_DMA_STATE_READY == hdma->State)
00400   {
00401     /* Change DMA peripheral state */
00402     hdma->State = HAL_DMA_STATE_BUSY;
00403     hdma->ErrorCode = HAL_DMA_ERROR_NONE;
00404
00405     /* Disable the peripheral */
00406     __HAL_DMA_DISABLE(hdma);
00407
00408     /* Configure the source, destination address and the data length & clear flags*/
00409     DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
00410
00411     /* Enable the Peripheral */
00412     __HAL_DMA_ENABLE(hdma);
00413   }
00414   else
00415   {
00416     /* Process Unlocked */
00417     __HAL_UNLOCK(hdma);
00418     status = HAL_BUSY;
00419   }
00420   return status;
00421 }
00422
00423 /**
00424   * @brief  Start the DMA Transfer with interrupt enabled.
00425   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
00426   *               the configuration information for the specified DMA Channel.
00427   * @param SrcAddress The source memory Buffer address
00428   * @param DstAddress The destination memory Buffer address
00429   * @param DataLength The length of data to be transferred from source to destination
00430   * @retval HAL status
00431   */
00432 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
00433 {
00434   HAL_StatusTypeDef status = HAL_OK;
00435
00436   /* Check the parameters */
00437   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
00438
00439   /* Process locked */
00440   __HAL_LOCK(hdma);
00441
00442   if (HAL_DMA_STATE_READY == hdma->State)
00443   {
00444     /* Change DMA peripheral state */
00445     hdma->State = HAL_DMA_STATE_BUSY;
00446     hdma->ErrorCode = HAL_DMA_ERROR_NONE;
00447
00448     /* Disable the peripheral */
00449     __HAL_DMA_DISABLE(hdma);
00450
00451     /* Configure the source, destination address and the data length & clear flags*/
00452     DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
00453
00454     /* Enable the transfer complete interrupt */
00455     /* Enable the transfer Error interrupt */
00456     if (NULL != hdma->XferHalfCpltCallback)
00457     {
00458       /* Enable the Half transfer complete interrupt as well */
00459       __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
00460     }
00461     else
00462     {
00463       __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
00464       __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
00465     }
00466
00467     /* Check if DMAMUX Synchronization is enabled*/
00468     if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
00469     {
00470       /* Enable DMAMUX sync overrun IT*/
00471       hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
00472     }
00473
00474     if (hdma->DMAmuxRequestGen != 0U)
00475     {
00476       /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
00477       /* enable the request gen overrun IT*/
00478       hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
00479     }
00480
00481     /* Enable the Peripheral */
00482     __HAL_DMA_ENABLE(hdma);
00483   }
00484   else
00485   {
00486     /* Process Unlocked */
00487     __HAL_UNLOCK(hdma);
00488
00489     /* Remain BUSY */
00490     status = HAL_BUSY;
00491   }
00492   return status;
00493 }
00494
00495 /**
00496   * @brief  Abort the DMA Transfer.
00497   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
00498   *               the configuration information for the specified DMA Channel.
00499     * @retval HAL status
00500   */
00501 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
00502 {
00503
00504   /* Check the DMA peripheral handle */
00505   if (NULL == hdma)
00506   {
00507     return HAL_ERROR;
00508   }
00509
00510   /* Check the DMA peripheral state */
00511   if(hdma->State != HAL_DMA_STATE_BUSY)
00512   {
00513     hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
00514
00515     /* Process Unlocked */
00516     __HAL_UNLOCK(hdma);
00517
00518     return HAL_ERROR;
00519   }
00520   else
00521   {
00522     /* Disable DMA IT */
00523     __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
00524
00525     /* disable the DMAMUX sync overrun IT*/
00526     hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
00527
00528     /* Disable the channel */
00529     __HAL_DMA_DISABLE(hdma);
00530
00531     /* Clear all flags */
00532     hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
00533
00534     /* Clear the DMAMUX synchro overrun flag */
00535     hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
00536
00537     if (hdma->DMAmuxRequestGen != 0U)
00538     {
00539       /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
00540       /* disable the request gen overrun IT*/
00541       hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
00542
00543       /* Clear the DMAMUX request generator overrun flag */
00544       hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
00545     }
00546
00547     /* Change the DMA state */
00548     hdma->State = HAL_DMA_STATE_READY;
00549
00550     /* Process Unlocked */
00551     __HAL_UNLOCK(hdma);
00552   }
00553
00554   return HAL_OK;
00555 }
00556
00557 /**
00558   * @brief  Aborts the DMA Transfer in Interrupt mode.
00559   * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
00560   *                 the configuration information for the specified DMA Channel.
00561   * @retval HAL status
00562   */
00563 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
00564 {
00565   HAL_StatusTypeDef status = HAL_OK;
00566
00567   if (HAL_DMA_STATE_BUSY != hdma->State)
00568   {
00569     /* no transfer ongoing */
00570     hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
00571
00572     status = HAL_ERROR;
00573   }
00574   else
00575   {
00576     /* Disable DMA IT */
00577     __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
00578
00579     /* Disable the channel */
00580     __HAL_DMA_DISABLE(hdma);
00581
00582     /* disable the DMAMUX sync overrun IT*/
00583     hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
00584
00585     /* Clear all flags */
00586     hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
00587
00588     /* Clear the DMAMUX synchro overrun flag */
00589     hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
00590
00591     if (hdma->DMAmuxRequestGen != 0U)
00592     {
00593       /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
00594       /* disable the request gen overrun IT*/
00595       hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
00596
00597       /* Clear the DMAMUX request generator overrun flag */
00598       hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
00599     }
00600
00601     /* Change the DMA state */
00602     hdma->State = HAL_DMA_STATE_READY;
00603
00604     /* Process Unlocked */
00605     __HAL_UNLOCK(hdma);
00606
00607     /* Call User Abort callback */
00608     if (hdma->XferAbortCallback != NULL)
00609     {
00610       hdma->XferAbortCallback(hdma);
00611     }
00612   }
00613   return status;
00614 }
00615
00616 /**
00617   * @brief  Polling for transfer complete.
00618   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
00619   *                  the configuration information for the specified DMA Channel.
00620   * @param CompleteLevel Specifies the DMA level complete.
00621   * @param Timeout Timeout duration.
00622   * @retval HAL status
00623   */
00624 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
00625 {
00626   uint32_t temp;
00627   uint32_t tickstart;
00628
00629   if (HAL_DMA_STATE_BUSY != hdma->State)
00630   {
00631     /* no transfer ongoing */
00632     hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
00633     __HAL_UNLOCK(hdma);
00634     return HAL_ERROR;
00635   }
00636
00637   /* Polling mode not supported in circular mode */
00638   if ((hdma->Instance->CCR & DMA_CCR_CIRC) != 0U)
00639   {
00640     hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
00641     return HAL_ERROR;
00642   }
00643
00644   /* Get the level transfer complete flag */
00645   if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
00646   {
00647     /* Transfer Complete flag */
00648     temp = DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU);
00649   }
00650   else
00651   {
00652     /* Half Transfer Complete flag */
00653     temp = DMA_FLAG_HT1 << (hdma->ChannelIndex  & 0x1cU);
00654   }
00655
00656   /* Get tick */
00657   tickstart = HAL_GetTick();
00658
00659   while((hdma->DmaBaseAddress->ISR & temp) == 0U)
00660   {
00661     if((hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex& 0x1CU))) != 0U)
00662     {
00663       /* When a DMA transfer error occurs */
00664       /* A hardware clear of its EN bits is performed */
00665       /* Clear all flags */
00666       hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
00667
00668       /* Update error code */
00669       hdma->ErrorCode = HAL_DMA_ERROR_TE;
00670
00671       /* Change the DMA state */
00672       hdma->State = HAL_DMA_STATE_READY;
00673
00674       /* Process Unlocked */
00675       __HAL_UNLOCK(hdma);
00676
00677       return HAL_ERROR;
00678     }
00679     /* Check for the Timeout */
00680     if (Timeout != HAL_MAX_DELAY)
00681     {
00682       if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
00683       {
00684         /* Update error code */
00685         hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
00686
00687         /* Change the DMA state */
00688         hdma->State = HAL_DMA_STATE_READY;
00689
00690         /* Process Unlocked */
00691         __HAL_UNLOCK(hdma);
00692
00693         return HAL_ERROR;
00694       }
00695     }
00696   }
00697
00698   /*Check for DMAMUX Request generator (if used) overrun status */
00699   if (hdma->DMAmuxRequestGen != 0U)
00700   {
00701     /* if using DMAMUX request generator Check for DMAMUX request generator overrun */
00702     if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
00703     {
00704       /* Disable the request gen overrun interrupt */
00705       hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
00706
00707       /* Clear the DMAMUX request generator overrun flag */
00708       hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
00709
00710       /* Update error code */
00711       hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
00712     }
00713   }
00714
00715   /* Check for DMAMUX Synchronization overrun */
00716   if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
00717   {
00718     /* Clear the DMAMUX synchro overrun flag */
00719     hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
00720
00721     /* Update error code */
00722     hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
00723   }
00724
00725   if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
00726   {
00727     /* Clear the transfer complete flag */
00728     hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU));
00729
00730     /* The selected Channelx EN bit is cleared (DMA is disabled and
00731     all transfers are complete) */
00732     hdma->State = HAL_DMA_STATE_READY;
00733   }
00734   else
00735   {
00736     /* Clear the half transfer complete flag */
00737     hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU));
00738   }
00739
00740   /* Process unlocked */
00741   __HAL_UNLOCK(hdma);
00742
00743   return HAL_OK;
00744 }
00745
00746 /**
00747   * @brief  Handle DMA interrupt request.
00748   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
00749   *               the configuration information for the specified DMA Channel.
00750   * @retval None
00751   */
00752 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
00753 {
00754   uint32_t flag_it = hdma->DmaBaseAddress->ISR;
00755   uint32_t source_it = hdma->Instance->CCR;
00756
00757   /* Half Transfer Complete Interrupt management ******************************/
00758   if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_HT) != 0U))
00759   {
00760     /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
00761     if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
00762     {
00763       /* Disable the half transfer interrupt */
00764       __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
00765     }
00766     /* Clear the half transfer complete flag */
00767     hdma->DmaBaseAddress->IFCR = (DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU));
00768
00769     /* DMA peripheral state is not updated in Half Transfer */
00770     /* but in Transfer Complete case */
00771
00772     if (hdma->XferHalfCpltCallback != NULL)
00773     {
00774       /* Half transfer callback */
00775       hdma->XferHalfCpltCallback(hdma);
00776     }
00777   }
00778
00779   /* Transfer Complete Interrupt management ***********************************/
00780   else if (((flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_TC) != 0U))
00781   {
00782     if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
00783     {
00784       /* Disable the transfer complete and error interrupt */
00785       __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
00786
00787       /* Change the DMA state */
00788       hdma->State = HAL_DMA_STATE_READY;
00789     }
00790     /* Clear the transfer complete flag */
00791     hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1cU));
00792
00793     /* Process Unlocked */
00794     __HAL_UNLOCK(hdma);
00795
00796     if (hdma->XferCpltCallback != NULL)
00797     {
00798       /* Transfer complete callback */
00799       hdma->XferCpltCallback(hdma);
00800     }
00801   }
00802
00803   /* Transfer Error Interrupt management **************************************/
00804   else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1cU)))!= 0U) && ((source_it & DMA_IT_TE) != 0U))
00805   {
00806     /* When a DMA transfer error occurs */
00807     /* A hardware clear of its EN bits is performed */
00808     /* Disable ALL DMA IT */
00809     __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
00810
00811     /* Clear all flags */
00812     hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
00813
00814     /* Update error code */
00815     hdma->ErrorCode = HAL_DMA_ERROR_TE;
00816
00817     /* Change the DMA state */
00818     hdma->State = HAL_DMA_STATE_READY;
00819
00820     /* Process Unlocked */
00821     __HAL_UNLOCK(hdma);
00822
00823     if (hdma->XferErrorCallback != NULL)
00824     {
00825       /* Transfer error callback */
00826       hdma->XferErrorCallback(hdma);
00827     }
00828   }
00829   else
00830   {
00831     /* Nothing To Do */
00832   }
00833   return;
00834 }
00835
00836 /**
00837   * @brief  Register callbacks
00838   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
00839   *                               the configuration information for the specified DMA Channel.
00840   * @param CallbackID User Callback identifer
00841   *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
00842   * @param pCallback Pointer to private callbacsk function which has pointer to
00843   *                               a DMA_HandleTypeDef structure as parameter.
00844   * @retval HAL status
00845   */
00846 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
00847 {
00848   HAL_StatusTypeDef status = HAL_OK;
00849
00850   /* Process locked */
00851   __HAL_LOCK(hdma);
00852
00853   if (HAL_DMA_STATE_READY == hdma->State)
00854   {
00855     switch (CallbackID)
00856     {
00857       case  HAL_DMA_XFER_CPLT_CB_ID:
00858         hdma->XferCpltCallback = pCallback;
00859         break;
00860
00861       case  HAL_DMA_XFER_HALFCPLT_CB_ID:
00862         hdma->XferHalfCpltCallback = pCallback;
00863         break;
00864
00865       case  HAL_DMA_XFER_ERROR_CB_ID:
00866         hdma->XferErrorCallback = pCallback;
00867         break;
00868
00869       case  HAL_DMA_XFER_ABORT_CB_ID:
00870         hdma->XferAbortCallback = pCallback;
00871         break;
00872
00873       default:
00874         status = HAL_ERROR;
00875         break;
00876     }
00877   }
00878   else
00879   {
00880     status = HAL_ERROR;
00881   }
00882
00883   /* Release Lock */
00884   __HAL_UNLOCK(hdma);
00885
00886   return status;
00887 }
00888
00889 /**
00890   * @brief  UnRegister callbacks
00891   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
00892   *                               the configuration information for the specified DMA Channel.
00893   * @param CallbackID User Callback identifer
00894   *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
00895   * @retval HAL status
00896   */
00897 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
00898 {
00899   HAL_StatusTypeDef status = HAL_OK;
00900
00901   /* Process locked */
00902   __HAL_LOCK(hdma);
00903
00904   if (HAL_DMA_STATE_READY == hdma->State)
00905   {
00906     switch (CallbackID)
00907     {
00908       case  HAL_DMA_XFER_CPLT_CB_ID:
00909         hdma->XferCpltCallback = NULL;
00910         break;
00911
00912       case  HAL_DMA_XFER_HALFCPLT_CB_ID:
00913         hdma->XferHalfCpltCallback = NULL;
00914         break;
00915
00916       case  HAL_DMA_XFER_ERROR_CB_ID:
00917         hdma->XferErrorCallback = NULL;
00918         break;
00919
00920       case  HAL_DMA_XFER_ABORT_CB_ID:
00921         hdma->XferAbortCallback = NULL;
00922         break;
00923
00924       case   HAL_DMA_XFER_ALL_CB_ID:
00925         hdma->XferCpltCallback = NULL;
00926         hdma->XferHalfCpltCallback = NULL;
00927         hdma->XferErrorCallback = NULL;
00928         hdma->XferAbortCallback = NULL;
00929         break;
00930
00931       default:
00932         status = HAL_ERROR;
00933         break;
00934     }
00935   }
00936   else
00937   {
00938     status = HAL_ERROR;
00939   }
00940
00941   /* Release Lock */
00942   __HAL_UNLOCK(hdma);
00943
00944   return status;
00945 }
00946
00947 /**
00948   * @}
00949   */
00950
00951
00952
00953 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
00954  *  @brief    Peripheral State and Errors functions
00955  *
00956 @verbatim
00957  ===============================================================================
00958             ##### Peripheral State and Errors functions #####
00959  ===============================================================================
00960     [..]
00961     This subsection provides functions allowing to
00962       (+) Check the DMA state
00963       (+) Get error code
00964
00965 @endverbatim
00966   * @{
00967   */
00968
00969 /**
00970   * @brief  Return the DMA handle state.
00971   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
00972   *               the configuration information for the specified DMA Channel.
00973   * @retval HAL state
00974   */
00975 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
00976 {
00977   /* Return DMA handle state */
00978   return hdma->State;
00979 }
00980
00981 /**
00982   * @brief  Return the DMA error code.
00983   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
00984   *              the configuration information for the specified DMA Channel.
00985   * @retval DMA Error Code
00986   */
00987 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
00988 {
00989   return hdma->ErrorCode;
00990 }
00991
00992 /**
00993   * @}
00994   */
00995
00996 /**
00997   * @}
00998   */
00999
01000 /** @addtogroup DMA_Private_Functions
01001   * @{
01002   */
01003
01004 /**
01005   * @brief  Sets the DMA Transfer parameter.
01006   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
01007   *                     the configuration information for the specified DMA Channel.
01008   * @param SrcAddress The source memory Buffer address
01009   * @param DstAddress The destination memory Buffer address
01010   * @param DataLength The length of data to be transferred from source to destination
01011   * @retval HAL status
01012   */
01013 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
01014 {
01015   /* Clear the DMAMUX synchro overrun flag */
01016   hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
01017
01018   if (hdma->DMAmuxRequestGen != 0U)
01019   {
01020     /* Clear the DMAMUX request generator overrun flag */
01021     hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
01022   }
01023
01024   /* Clear all flags */
01025   hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
01026
01027   /* Configure DMA Channel data length */
01028   hdma->Instance->CNDTR = DataLength;
01029
01030   /* Memory to Peripheral */
01031   if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
01032   {
01033     /* Configure DMA Channel destination address */
01034     hdma->Instance->CPAR = DstAddress;
01035
01036     /* Configure DMA Channel source address */
01037     hdma->Instance->CMAR = SrcAddress;
01038   }
01039   /* Peripheral to Memory */
01040   else
01041   {
01042     /* Configure DMA Channel source address */
01043     hdma->Instance->CPAR = SrcAddress;
01044
01045     /* Configure DMA Channel destination address */
01046     hdma->Instance->CMAR = DstAddress;
01047   }
01048 }
01049
01050 /**
01051   * @brief  Updates the DMA handle with the DMAMUX  channel and status mask depending on channel number
01052   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
01053   *                     the configuration information for the specified DMA Channel.
01054   * @retval None
01055   */
01056 static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
01057 {
01058   uint32_t channel_number;
01059
01060   /* check if instance is not outside the DMA channel range */
01061 #if defined(DMA2)
01062   if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1)
01063   {
01064     /* DMA1 */
01065     hdma->DMAmuxChannel = (DMAMUX1_Channel0 + (hdma->ChannelIndex >> 2U));
01066   }
01067   else
01068   {
01069     /* DMA2 */
01070     hdma->DMAmuxChannel = (DMAMUX1_Channel7 + (hdma->ChannelIndex >> 2U));
01071   }
01072 #else
01073   /* DMA1 */
01074   hdma->DMAmuxChannel = (DMAMUX1_Channel0 + (hdma->ChannelIndex >> 2U));
01075 #endif
01076   channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;
01077   hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
01078   hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1cU);
01079 }
01080
01081 /**
01082   * @brief  Updates the DMA handle with the DMAMUX  request generator params
01083   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
01084   *                     the configuration information for the specified DMA Channel.
01085   * @retval None
01086   */
01087
01088 static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)
01089 {
01090   uint32_t request =  hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;
01091
01092   /* DMA Channels are connected to DMAMUX1 request generator blocks*/
01093   hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U)));
01094
01095   hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
01096
01097   /* here "Request" is either DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR3, i.e. <= 4*/
01098   hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U);
01099 }
01100
01101 /**
01102   * @}
01103   */
01104
01105 /**
01106   * @}
01107   */
01108
01109 #endif /* HAL_DMA_MODULE_ENABLED */
01110 /**
01111   * @}
01112   */
01113
01114 /**
01115   * @}
01116   */
01117
01118 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_dma.h Source File

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stm32wbxx_hal_dma.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_dma.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DMA HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_DMA_H
00022 #define STM32WBxx_HAL_DMA_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030 #include "stm32wbxx_ll_dma.h"
00031
00032 /** @addtogroup STM32WBxx_HAL_Driver
00033   * @{
00034   */
00035
00036 /** @addtogroup DMA
00037   * @{
00038   */
00039
00040 /* Exported types ------------------------------------------------------------*/
00041 /** @defgroup DMA_Exported_Types DMA Exported Types
00042   * @{
00043   */
00044
00045 /**
00046   * @brief  DMA Configuration Structure definition
00047   */
00048 typedef struct
00049 {
00050   uint32_t Request;                   /*!< Specifies the request selected for the specified channel.
00051                                            This parameter can be a value of @ref DMA_request */
00052
00053   uint32_t Direction;                 /*!< Specifies if the data will be transferred from memory to peripheral,
00054                                            from memory to memory or from peripheral to memory.
00055                                            This parameter can be a value of @ref DMA_Data_transfer_direction */
00056
00057   uint32_t PeriphInc;                 /*!< Specifies whether the Peripheral address register should be incremented or not.
00058                                            This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
00059
00060   uint32_t MemInc;                    /*!< Specifies whether the memory address register should be incremented or not.
00061                                            This parameter can be a value of @ref DMA_Memory_incremented_mode */
00062
00063   uint32_t PeriphDataAlignment;       /*!< Specifies the Peripheral data width.
00064                                            This parameter can be a value of @ref DMA_Peripheral_data_size */
00065
00066   uint32_t MemDataAlignment;          /*!< Specifies the Memory data width.
00067                                            This parameter can be a value of @ref DMA_Memory_data_size */
00068
00069   uint32_t Mode;                      /*!< Specifies the operation mode of the DMAy Channelx.
00070                                            This parameter can be a value of @ref DMA_mode
00071                                            @note The circular buffer mode cannot be used if the memory-to-memory
00072                                                  data transfer is configured on the selected Channel */
00073
00074   uint32_t Priority;                  /*!< Specifies the software priority for the DMAy Channelx.
00075                                            This parameter can be a value of @ref DMA_Priority_level */
00076 } DMA_InitTypeDef;
00077
00078 /**
00079   * @brief  HAL DMA State structures definition
00080   */
00081 typedef enum
00082 {
00083   HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled    */
00084   HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use      */
00085   HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing                 */
00086   HAL_DMA_STATE_TIMEOUT           = 0x03U,  /*!< DMA timeout state                      */
00087 } HAL_DMA_StateTypeDef;
00088
00089 /**
00090   * @brief  HAL DMA Error Code structure definition
00091   */
00092 typedef enum
00093 {
00094   HAL_DMA_FULL_TRANSFER      = 0x00U,    /*!< Full transfer     */
00095   HAL_DMA_HALF_TRANSFER      = 0x01U     /*!< Half Transfer     */
00096 } HAL_DMA_LevelCompleteTypeDef;
00097
00098
00099 /**
00100   * @brief  HAL DMA Callback ID structure definition
00101   */
00102 typedef enum
00103 {
00104   HAL_DMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer     */
00105   HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01U,    /*!< Half transfer     */
00106   HAL_DMA_XFER_ERROR_CB_ID         = 0x02U,    /*!< Error             */
00107   HAL_DMA_XFER_ABORT_CB_ID         = 0x03U,    /*!< Abort             */
00108   HAL_DMA_XFER_ALL_CB_ID           = 0x04U     /*!< All               */
00109
00110 } HAL_DMA_CallbackIDTypeDef;
00111
00112 /**
00113   * @brief  DMA handle Structure definition
00114   */
00115 typedef struct __DMA_HandleTypeDef
00116 {
00117   DMA_Channel_TypeDef    *Instance;                                                  /*!< Register base address                 */
00118
00119   DMA_InitTypeDef       Init;                                                        /*!< DMA communication parameters          */
00120
00121   HAL_LockTypeDef       Lock;                                                        /*!< DMA locking object                    */
00122
00123   __IO HAL_DMA_StateTypeDef  State;                                                  /*!< DMA transfer state                    */
00124
00125   void                  *Parent;                                                     /*!< Parent object state                   */
00126
00127   void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma);                       /*!< DMA transfer complete callback        */
00128
00129   void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma);                   /*!< DMA Half transfer complete callback   */
00130
00131   void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma);                      /*!< DMA transfer error callback           */
00132
00133   void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma);                      /*!< DMA transfer abort callback           */
00134
00135   __IO uint32_t          ErrorCode;                                                  /*!< DMA Error code                        */
00136
00137   DMA_TypeDef            *DmaBaseAddress;                                            /*!< DMA Channel Base Address              */
00138
00139   uint32_t               ChannelIndex;                                               /*!< DMA Channel Index                     */
00140
00141   DMAMUX_Channel_TypeDef           *DMAmuxChannel;                                   /*!< Register base address                 */
00142
00143   DMAMUX_ChannelStatus_TypeDef     *DMAmuxChannelStatus;                             /*!< DMAMUX Channels Status Base Address   */
00144
00145   uint32_t                         DMAmuxChannelStatusMask;                          /*!< DMAMUX Channel Status Mask            */
00146
00147   DMAMUX_RequestGen_TypeDef        *DMAmuxRequestGen;                                /*!< DMAMUX request generator Base Address */
00148
00149   DMAMUX_RequestGenStatus_TypeDef  *DMAmuxRequestGenStatus;                          /*!< DMAMUX request generator Address      */
00150
00151   uint32_t                         DMAmuxRequestGenStatusMask;                       /*!< DMAMUX request generator Status mask  */
00152 } DMA_HandleTypeDef;
00153 /**
00154   * @}
00155   */
00156
00157 /* Exported constants --------------------------------------------------------*/
00158
00159 /** @defgroup DMA_Exported_Constants DMA Exported Constants
00160   * @{
00161   */
00162
00163 /** @defgroup DMA_Error_Code DMA Error Code
00164   * @{
00165   */
00166 #define HAL_DMA_ERROR_NONE              0x00000000U                     /*!< No error                                */
00167 #define HAL_DMA_ERROR_TE                0x00000001U                     /*!< Transfer error                          */
00168 #define HAL_DMA_ERROR_NO_XFER           0x00000004U                     /*!< Abort requested with no Xfer ongoing    */
00169 #define HAL_DMA_ERROR_TIMEOUT           0x00000020U                     /*!< Timeout error                           */
00170 #define HAL_DMA_ERROR_NOT_SUPPORTED     0x00000100U                     /*!< Not supported mode                      */
00171 #define HAL_DMA_ERROR_SYNC              0x00000200U                     /*!< DMAMUX sync overrun  error              */
00172 #define HAL_DMA_ERROR_REQGEN            0x00000400U                     /*!< DMAMUX request generator overrun  error */
00173
00174 /**
00175   * @}
00176   */
00177
00178 /** @defgroup DMA_request DMA request
00179   * @{
00180   */
00181
00182 #define DMA_REQUEST_MEM2MEM             LL_DMAMUX_REQ_MEM2MEM           /*!< memory to memory transfer  */
00183
00184 #define DMA_REQUEST_GENERATOR0          LL_DMAMUX_REQ_GENERATOR0        /*!< DMAMUX request generator 0 */
00185 #define DMA_REQUEST_GENERATOR1          LL_DMAMUX_REQ_GENERATOR1        /*!< DMAMUX request generator 1 */
00186 #define DMA_REQUEST_GENERATOR2          LL_DMAMUX_REQ_GENERATOR2        /*!< DMAMUX request generator 2 */
00187 #define DMA_REQUEST_GENERATOR3          LL_DMAMUX_REQ_GENERATOR3        /*!< DMAMUX request generator 3 */
00188
00189 #define DMA_REQUEST_ADC1                LL_DMAMUX_REQ_ADC1              /*!< DMAMUX ADC1 request        */
00190
00191 #define DMA_REQUEST_SPI1_RX             LL_DMAMUX_REQ_SPI1_RX           /*!< DMAMUX SPI1 RX request     */
00192 #define DMA_REQUEST_SPI1_TX             LL_DMAMUX_REQ_SPI1_TX           /*!< DMAMUX SPI1 TX request     */
00193 #define DMA_REQUEST_SPI2_RX             LL_DMAMUX_REQ_SPI2_RX           /*!< DMAMUX SPI2 RX request     */
00194 #define DMA_REQUEST_SPI2_TX             LL_DMAMUX_REQ_SPI2_TX           /*!< DMAMUX SPI2 TX request     */
00195
00196 #define DMA_REQUEST_I2C1_RX             LL_DMAMUX_REQ_I2C1_RX           /*!< DMAMUX I2C1 RX request     */
00197 #define DMA_REQUEST_I2C1_TX             LL_DMAMUX_REQ_I2C1_TX           /*!< DMAMUX I2C1 TX request     */
00198 #define DMA_REQUEST_I2C3_RX             LL_DMAMUX_REQ_I2C3_RX           /*!< DMAMUX I2C3 RX request     */
00199 #define DMA_REQUEST_I2C3_TX             LL_DMAMUX_REQ_I2C3_TX           /*!< DMAMUX I2C3 TX request     */
00200
00201 #define DMA_REQUEST_USART1_RX           LL_DMAMUX_REQ_USART1_RX         /*!< DMAMUX USART1 RX request   */
00202 #define DMA_REQUEST_USART1_TX           LL_DMAMUX_REQ_USART1_TX         /*!< DMAMUX USART1 TX request   */
00203
00204 #define DMA_REQUEST_LPUART1_RX          LL_DMAMUX_REQ_LPUART1_RX        /*!< DMAMUX LP_UART1_RX request */
00205 #define DMA_REQUEST_LPUART1_TX          LL_DMAMUX_REQ_LPUART1_TX        /*!< DMAMUX LP_UART1_RX request */
00206
00207 #if defined (SAI1)
00208 #define DMA_REQUEST_SAI1_A              LL_DMAMUX_REQ_SAI1_A            /*!< DMAMUX SAI1 A request      */
00209 #define DMA_REQUEST_SAI1_B              LL_DMAMUX_REQ_SAI1_B            /*!< DMAMUX SAI1 B request      */
00210 #endif /* SAI1 */
00211
00212 #define DMA_REQUEST_QUADSPI             LL_DMAMUX_REQ_QUADSPI           /*!< DMAMUX QUADSPI request     */
00213
00214 #define DMA_REQUEST_TIM1_CH1            LL_DMAMUX_REQ_TIM1_CH1          /*!< DMAMUX TIM1 CH1 request    */
00215 #define DMA_REQUEST_TIM1_CH2            LL_DMAMUX_REQ_TIM1_CH2          /*!< DMAMUX TIM1 CH2 request    */
00216 #define DMA_REQUEST_TIM1_CH3            LL_DMAMUX_REQ_TIM1_CH3          /*!< DMAMUX TIM1 CH3 request    */
00217 #define DMA_REQUEST_TIM1_CH4            LL_DMAMUX_REQ_TIM1_CH4          /*!< DMAMUX TIM1 CH4 request    */
00218 #define DMA_REQUEST_TIM1_UP             LL_DMAMUX_REQ_TIM1_UP           /*!< DMAMUX TIM1 UP  request    */
00219 #define DMA_REQUEST_TIM1_TRIG           LL_DMAMUX_REQ_TIM1_TRIG         /*!< DMAMUX TIM1 TRIG request   */
00220 #define DMA_REQUEST_TIM1_COM            LL_DMAMUX_REQ_TIM1_COM          /*!< DMAMUX TIM1 COM request    */
00221
00222 #define DMA_REQUEST_TIM2_CH1            LL_DMAMUX_REQ_TIM2_CH1          /*!< DMAMUX TIM2 CH1 request    */
00223 #define DMA_REQUEST_TIM2_CH2            LL_DMAMUX_REQ_TIM2_CH2          /*!< DMAMUX TIM2 CH2 request    */
00224 #define DMA_REQUEST_TIM2_CH3            LL_DMAMUX_REQ_TIM2_CH3          /*!< DMAMUX TIM2 CH3 request    */
00225 #define DMA_REQUEST_TIM2_CH4            LL_DMAMUX_REQ_TIM2_CH4          /*!< DMAMUX TIM2 CH4 request    */
00226 #define DMA_REQUEST_TIM2_UP             LL_DMAMUX_REQ_TIM2_UP           /*!< DMAMUX TIM2 UP  request    */
00227
00228 #define DMA_REQUEST_TIM16_CH1           LL_DMAMUX_REQ_TIM16_CH1         /*!< DMAMUX TIM16 CH1 request   */
00229 #define DMA_REQUEST_TIM16_UP            LL_DMAMUX_REQ_TIM16_UP          /*!< DMAMUX TIM16 UP  request   */
00230
00231 #define DMA_REQUEST_TIM17_CH1           LL_DMAMUX_REQ_TIM17_CH1         /*!< DMAMUX TIM17 CH1 request   */
00232 #define DMA_REQUEST_TIM17_UP            LL_DMAMUX_REQ_TIM17_UP          /*!< DMAMUX TIM17 UP  request   */
00233
00234 #define DMA_REQUEST_AES1_IN             LL_DMAMUX_REQ_AES1_IN           /*!< DMAMUX AES1 IN request     */
00235 #define DMA_REQUEST_AES1_OUT            LL_DMAMUX_REQ_AES1_OUT          /*!< DMAMUX AES1 OUT request    */
00236
00237 #define DMA_REQUEST_AES2_IN             LL_DMAMUX_REQ_AES2_IN           /*!< DMAMUX AES2 IN request     */
00238 #define DMA_REQUEST_AES2_OUT            LL_DMAMUX_REQ_AES2_OUT          /*!< DMAMUX AES2 OUT request    */
00239 /**
00240   * @}
00241   */
00242
00243 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
00244   * @{
00245   */
00246 #define DMA_PERIPH_TO_MEMORY            LL_DMA_DIRECTION_PERIPH_TO_MEMORY  /*!< Peripheral to memory direction */
00247 #define DMA_MEMORY_TO_PERIPH            LL_DMA_DIRECTION_MEMORY_TO_PERIPH  /*!< Memory to peripheral direction */
00248 #define DMA_MEMORY_TO_MEMORY            LL_DMA_DIRECTION_MEMORY_TO_MEMORY  /*!< Memory to memory direction     */
00249 /**
00250   * @}
00251   */
00252
00253 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
00254   * @{
00255   */
00256 #define DMA_PINC_ENABLE                 LL_DMA_PERIPH_INCREMENT         /*!< Peripheral increment mode Enable */
00257 #define DMA_PINC_DISABLE                LL_DMA_PERIPH_NOINCREMENT       /*!< Peripheral increment mode Disable */
00258 /**
00259   * @}
00260   */
00261
00262 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
00263   * @{
00264   */
00265 #define DMA_MINC_ENABLE                 LL_DMA_MEMORY_INCREMENT         /*!< Memory increment mode Enable  */
00266 #define DMA_MINC_DISABLE                LL_DMA_MEMORY_NOINCREMENT       /*!< Memory increment mode Disable */
00267 /**
00268   * @}
00269   */
00270
00271 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
00272   * @{
00273   */
00274 #define DMA_PDATAALIGN_BYTE             LL_DMA_PDATAALIGN_BYTE          /*!< Peripheral data alignment : Byte     */
00275 #define DMA_PDATAALIGN_HALFWORD         LL_DMA_PDATAALIGN_HALFWORD      /*!< Peripheral data alignment : HalfWord */
00276 #define DMA_PDATAALIGN_WORD             LL_DMA_PDATAALIGN_WORD          /*!< Peripheral data alignment : Word     */
00277 /**
00278   * @}
00279   */
00280
00281 /** @defgroup DMA_Memory_data_size DMA Memory data size
00282   * @{
00283   */
00284 #define DMA_MDATAALIGN_BYTE             LL_DMA_MDATAALIGN_BYTE          /*!< Memory data alignment : Byte     */
00285 #define DMA_MDATAALIGN_HALFWORD         LL_DMA_MDATAALIGN_HALFWORD      /*!< Memory data alignment : HalfWord */
00286 #define DMA_MDATAALIGN_WORD             LL_DMA_MDATAALIGN_WORD          /*!< Memory data alignment : Word     */
00287 /**
00288   * @}
00289   */
00290
00291 /** @defgroup DMA_mode DMA mode
00292   * @{
00293   */
00294 #define DMA_NORMAL                      LL_DMA_MODE_NORMAL              /*!< Normal mode                  */
00295 #define DMA_CIRCULAR                    LL_DMA_MODE_CIRCULAR            /*!< Circular mode                */
00296 /**
00297   * @}
00298   */
00299
00300 /** @defgroup DMA_Priority_level DMA Priority level
00301   * @{
00302   */
00303 #define DMA_PRIORITY_LOW                LL_DMA_PRIORITY_LOW             /*!< Priority level : Low       */
00304 #define DMA_PRIORITY_MEDIUM             LL_DMA_PRIORITY_MEDIUM          /*!< Priority level : Medium    */
00305 #define DMA_PRIORITY_HIGH               LL_DMA_PRIORITY_HIGH            /*!< Priority level : High      */
00306 #define DMA_PRIORITY_VERY_HIGH          LL_DMA_PRIORITY_VERYHIGH        /*!< Priority level : Very_High */
00307 /**
00308   * @}
00309   */
00310
00311
00312 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
00313   * @{
00314   */
00315 #define DMA_IT_TC                       LL_DMA_CCR_TCIE                 /*!< Transfer complete interrupt */
00316 #define DMA_IT_HT                       LL_DMA_CCR_HTIE                 /*!< Half Transfer interrupt     */
00317 #define DMA_IT_TE                       LL_DMA_CCR_TEIE                 /*!< Transfer error interrupt    */
00318 /**
00319   * @}
00320   */
00321
00322 /** @defgroup DMA_flag_definitions DMA flag definitions
00323   * @{
00324   */
00325 #define DMA_FLAG_GL1                      LL_DMA_ISR_GIF1               /*!< Channel 1 global flag            */
00326 #define DMA_FLAG_TC1                      LL_DMA_ISR_TCIF1              /*!< Channel 1 transfer complete flag */
00327 #define DMA_FLAG_HT1                      LL_DMA_ISR_HTIF1              /*!< Channel 1 half transfer flag     */
00328 #define DMA_FLAG_TE1                      LL_DMA_ISR_TEIF1              /*!< Channel 1 transfer error flag    */
00329 #define DMA_FLAG_GL2                      LL_DMA_ISR_GIF2               /*!< Channel 2 global flag            */
00330 #define DMA_FLAG_TC2                      LL_DMA_ISR_TCIF2              /*!< Channel 2 transfer complete flag */
00331 #define DMA_FLAG_HT2                      LL_DMA_ISR_HTIF2              /*!< Channel 2 half transfer flag     */
00332 #define DMA_FLAG_TE2                      LL_DMA_ISR_TEIF2              /*!< Channel 2 transfer error flag    */
00333 #define DMA_FLAG_GL3                      LL_DMA_ISR_GIF3               /*!< Channel 3 global flag            */
00334 #define DMA_FLAG_TC3                      LL_DMA_ISR_TCIF3              /*!< Channel 3 transfer complete flag */
00335 #define DMA_FLAG_HT3                      LL_DMA_ISR_HTIF3              /*!< Channel 3 half transfer flag     */
00336 #define DMA_FLAG_TE3                      LL_DMA_ISR_TEIF3              /*!< Channel 3 transfer error flag    */
00337 #define DMA_FLAG_GL4                      LL_DMA_ISR_GIF4               /*!< Channel 4 global flag            */
00338 #define DMA_FLAG_TC4                      LL_DMA_ISR_TCIF4              /*!< Channel 4 transfer complete flag */
00339 #define DMA_FLAG_HT4                      LL_DMA_ISR_HTIF4              /*!< Channel 4 half transfer flag     */
00340 #define DMA_FLAG_TE4                      LL_DMA_ISR_TEIF4              /*!< Channel 4 transfer error flag    */
00341 #define DMA_FLAG_GL5                      LL_DMA_ISR_GIF5               /*!< Channel 5 global flag            */
00342 #define DMA_FLAG_TC5                      LL_DMA_ISR_TCIF5              /*!< Channel 5 transfer complete flag */
00343 #define DMA_FLAG_HT5                      LL_DMA_ISR_HTIF5              /*!< Channel 5 half transfer flag     */
00344 #define DMA_FLAG_TE5                      LL_DMA_ISR_TEIF5              /*!< Channel 5 transfer error flag    */
00345 #define DMA_FLAG_GL6                      LL_DMA_ISR_GIF6               /*!< Channel 6 global flag            */
00346 #define DMA_FLAG_TC6                      LL_DMA_ISR_TCIF6              /*!< Channel 6 transfer complete flag */
00347 #define DMA_FLAG_HT6                      LL_DMA_ISR_HTIF6              /*!< Channel 6 half transfer flag     */
00348 #define DMA_FLAG_TE6                      LL_DMA_ISR_TEIF6              /*!< Channel 6 transfer error flag    */
00349 #define DMA_FLAG_GL7                      LL_DMA_ISR_GIF7               /*!< Channel 7 global flag            */
00350 #define DMA_FLAG_TC7                      LL_DMA_ISR_TCIF7              /*!< Channel 7 transfer complete flag */
00351 #define DMA_FLAG_HT7                      LL_DMA_ISR_HTIF7              /*!< Channel 7 half transfer flag     */
00352 #define DMA_FLAG_TE7                      LL_DMA_ISR_TEIF7              /*!< Channel 7 transfer error flag    */
00353 /**
00354   * @}
00355   */
00356
00357 /**
00358   * @}
00359   */
00360
00361 /* Exported macros -----------------------------------------------------------*/
00362 /** @defgroup DMA_Exported_Macros DMA Exported Macros
00363   * @{
00364   */
00365
00366 /** @brief  Reset DMA handle state.
00367   * @param __HANDLE__ DMA handle
00368   * @retval None
00369   */
00370 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
00371
00372 /**
00373   * @brief  Enable the specified DMA Channel.
00374   * @param __HANDLE__ DMA handle
00375   * @retval None
00376   */
00377 #define __HAL_DMA_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CCR |=  DMA_CCR_EN)
00378
00379 /**
00380   * @brief  Disable the specified DMA Channel.
00381   * @param __HANDLE__ DMA handle
00382   * @retval None
00383   */
00384 #define __HAL_DMA_DISABLE(__HANDLE__)       ((__HANDLE__)->Instance->CCR &=  ~DMA_CCR_EN)
00385
00386
00387 /* Interrupt & Flag management */
00388
00389 /**
00390   * @brief  Return the current DMA Channel transfer complete flag.
00391   * @param __HANDLE__ DMA handle
00392   * @retval The specified transfer complete flag index.
00393   */
00394
00395 #if defined(DMA2)
00396 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
00397 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
00398  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
00399  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
00400  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
00401  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
00402  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
00403  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
00404  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
00405  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
00406  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
00407  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
00408  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\
00409    DMA_FLAG_TC7)
00410 #else
00411 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
00412 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
00413  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
00414  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
00415  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
00416  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
00417  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
00418    DMA_FLAG_TC7)
00419 #endif
00420
00421 /**
00422   * @brief  Return the current DMA Channel half transfer complete flag.
00423   * @param __HANDLE__ DMA handle
00424   * @retval The specified half transfer complete flag index.
00425   */
00426 #if defined(DMA2)
00427 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
00428 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
00429  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
00430  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
00431  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
00432  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
00433  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
00434  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
00435  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
00436  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
00437  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
00438  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
00439  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\
00440    DMA_FLAG_HT7)
00441 #else
00442 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
00443 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
00444  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
00445  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
00446  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
00447  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
00448  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
00449    DMA_FLAG_HT7)
00450 #endif
00451
00452 /**
00453   * @brief  Return the current DMA Channel transfer error flag.
00454   * @param __HANDLE__ DMA handle
00455   * @retval The specified transfer error flag index.
00456   */
00457 #if defined(DMA2)
00458 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
00459 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
00460  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
00461  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
00462  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
00463  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
00464  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
00465  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
00466  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
00467  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
00468  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
00469  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
00470  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\
00471    DMA_FLAG_TE7)
00472 #else
00473 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
00474 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
00475  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
00476  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
00477  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
00478  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
00479  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
00480    DMA_FLAG_TE7)
00481 #endif
00482
00483 /**
00484   * @brief  Return the current DMA Channel Global interrupt flag.
00485   * @param __HANDLE__ DMA handle
00486   * @retval The specified transfer error flag index.
00487   */
00488 #if defined(DMA2)
00489 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
00490 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
00491  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
00492  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
00493  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
00494  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
00495  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
00496  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
00497  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
00498  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
00499  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
00500  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
00501  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\
00502    DMA_ISR_GIF7)
00503 #else
00504 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
00505 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
00506  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
00507  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
00508  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
00509  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
00510  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
00511    DMA_ISR_GIF7)
00512 #endif
00513
00514 /**
00515   * @brief  Get the DMA Channel pending flags.
00516   * @param __HANDLE__ DMA handle
00517   * @param __FLAG__ Get the specified flag.
00518   *          This parameter can be any combination of the following values:
00519   *            @arg DMA_FLAG_TCx:  Transfer complete flag
00520   *            @arg DMA_FLAG_HTx:  Half transfer complete flag
00521   *            @arg DMA_FLAG_TEx:  Transfer error flag
00522   *            @arg DMA_FLAG_GLx:  Global interrupt flag
00523   *         Where x can be from 1 to 7 to select the DMA Channel x flag.
00524   * @retval The state of FLAG (SET or RESET).
00525   */
00526 #if defined(DMA2)
00527 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
00528  (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
00529 #else
00530 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
00531 #endif
00532
00533 /**
00534   * @brief  Clear the DMA Channel pending flags.
00535   * @param __HANDLE__ DMA handle
00536   * @param __FLAG__ specifies the flag to clear.
00537   *          This parameter can be any combination of the following values:
00538   *            @arg DMA_FLAG_TCx:  Transfer complete flag
00539   *            @arg DMA_FLAG_HTx:  Half transfer complete flag
00540   *            @arg DMA_FLAG_TEx:  Transfer error flag
00541   *            @arg DMA_FLAG_GLx:  Global interrupt flag
00542   *         Where x can be from 1 to 7 to select the DMA Channel x flag.
00543   * @retval None
00544   */
00545 #if defined(DMA2)
00546 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
00547  (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
00548 #else
00549 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
00550 #endif
00551
00552 /**
00553   * @brief  Enable the specified DMA Channel interrupts.
00554   * @param __HANDLE__ DMA handle
00555   * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
00556   *          This parameter can be any combination of the following values:
00557   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
00558   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
00559   *            @arg DMA_IT_TE:  Transfer error interrupt mask
00560   * @retval None
00561   */
00562 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
00563
00564 /**
00565   * @brief  Disable the specified DMA Channel interrupts.
00566   * @param __HANDLE__ DMA handle
00567   * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
00568   *          This parameter can be any combination of the following values:
00569   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
00570   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
00571   *            @arg DMA_IT_TE:  Transfer error interrupt mask
00572   * @retval None
00573   */
00574 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
00575
00576 /**
00577   * @brief  Check whether the specified DMA Channel interrupt is enabled or not.
00578   * @param __HANDLE__ DMA handle
00579   * @param __INTERRUPT__ specifies the DMA interrupt source to check.
00580   *          This parameter can be one of the following values:
00581   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
00582   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
00583   *            @arg DMA_IT_TE:  Transfer error interrupt mask
00584   * @retval The state of DMA_IT (SET or RESET).
00585   */
00586 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
00587
00588 /**
00589   * @brief  Return the number of remaining data units in the current DMA Channel transfer.
00590   * @param __HANDLE__ DMA handle
00591   * @retval The number of remaining data units in the current DMA Channel transfer.
00592   */
00593 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
00594
00595 /**
00596   * @}
00597   */
00598
00599 /* Include DMA HAL Extension module */
00600 #include "stm32wbxx_hal_dma_ex.h"
00601
00602 /* Exported functions --------------------------------------------------------*/
00603
00604 /** @addtogroup DMA_Exported_Functions
00605   * @{
00606   */
00607
00608 /** @addtogroup DMA_Exported_Functions_Group1
00609   * @{
00610   */
00611 /* Initialization and de-initialization functions *****************************/
00612 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
00613 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
00614 /**
00615   * @}
00616   */
00617
00618 /** @addtogroup DMA_Exported_Functions_Group2
00619   * @{
00620   */
00621 /* IO operation functions *****************************************************/
00622 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
00623 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
00624 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
00625 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
00626 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
00627 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
00628 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
00629 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
00630
00631 /**
00632   * @}
00633   */
00634
00635 /** @addtogroup DMA_Exported_Functions_Group3
00636   * @{
00637   */
00638 /* Peripheral State and Error functions ***************************************/
00639 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
00640 uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
00641 /**
00642   * @}
00643   */
00644
00645 /**
00646   * @}
00647   */
00648
00649 /* Private macros ------------------------------------------------------------*/
00650 /** @defgroup DMA_Private_Macros DMA Private Macros
00651   * @{
00652   */
00653
00654 #define IS_DMA_DIRECTION(DIRECTION)             (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
00655                                                  ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
00656                                                  ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
00657
00658 #define IS_DMA_BUFFER_SIZE(SIZE)                (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
00659
00660 #define IS_DMA_PERIPHERAL_INC_STATE(STATE)      (((STATE) == DMA_PINC_ENABLE)   || \
00661                                                  ((STATE) == DMA_PINC_DISABLE))
00662
00663 #define IS_DMA_MEMORY_INC_STATE(STATE)          (((STATE) == DMA_MINC_ENABLE)   || \
00664                                                  ((STATE) == DMA_MINC_DISABLE))
00665
00666
00667 #define IS_DMA_ALL_REQUEST(REQUEST)             ((REQUEST) <= DMA_REQUEST_AES2_OUT)
00668
00669 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE)       (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
00670                                                  ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
00671                                                  ((SIZE) == DMA_PDATAALIGN_WORD))
00672
00673 #define IS_DMA_MEMORY_DATA_SIZE(SIZE)           (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
00674                                                  ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
00675                                                  ((SIZE) == DMA_MDATAALIGN_WORD ))
00676
00677 #define IS_DMA_MODE(MODE)                       (((MODE) == DMA_NORMAL )  || \
00678                                                  ((MODE) == DMA_CIRCULAR))
00679
00680 #define IS_DMA_PRIORITY(PRIORITY)               (((PRIORITY) == DMA_PRIORITY_LOW )   || \
00681                                                  ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
00682                                                  ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
00683                                                  ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
00684
00685 /**
00686   * @}
00687   */
00688
00689 /* Private functions ---------------------------------------------------------*/
00690
00691 /**
00692   * @}
00693   */
00694
00695 /**
00696   * @}
00697   */
00698
00699 #ifdef __cplusplus
00700 }
00701 #endif
00702
00703 #endif /* STM32WBxx_HAL_DMA_H */
00704
00705 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_dma_ex.c Source File

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stm32wbxx_hal_dma_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_dma_ex.c
00004   * @author  MCD Application Team
00005   * @brief   DMA Extension HAL module driver
00006   *         This file provides firmware functions to manage the following
00007   *         functionalities of the DMA Extension peripheral:
00008   *           + Extended features functions
00009   *
00010   @verbatim
00011   ==============================================================================
00012                         ##### How to use this driver #####
00013   ==============================================================================
00014   [..]
00015   The DMA Extension HAL driver can be used as follows:
00016
00017    (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
00018    (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
00019        Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
00020        to respectively enable/disable the request generator.
00021
00022    (+) To handle the DMAMUX Interrupts, the function  HAL_DMAEx_MUX_IRQHandler should be called from
00023        the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler.
00024        As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMAEx_MUX_IRQHandler should be
00025        called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project
00026       (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator)
00027
00028   @endverbatim
00029   ******************************************************************************
00030   * @attention
00031   *
00032   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00033   * All rights reserved.</center></h2>
00034   *
00035   * This software component is licensed by ST under BSD 3-Clause license,
00036   * the "License"; You may not use this file except in compliance with the
00037   * License. You may obtain a copy of the License at:
00038   *                        opensource.org/licenses/BSD-3-Clause
00039   *
00040   ******************************************************************************
00041   */
00042
00043 /* Includes ------------------------------------------------------------------*/
00044 #include "stm32wbxx_hal.h"
00045
00046 /** @addtogroup STM32WBxx_HAL_Driver
00047   * @{
00048   */
00049
00050 /** @defgroup DMAEx DMAEx
00051   * @brief DMA Extended HAL module driver
00052   * @{
00053   */
00054
00055 #ifdef HAL_DMA_MODULE_ENABLED
00056
00057 /* Private typedef -----------------------------------------------------------*/
00058 /* Private define ------------------------------------------------------------*/
00059 /* Private macro -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 /* Private Constants ---------------------------------------------------------*/
00062 /* Private function prototypes -----------------------------------------------*/
00063 /* Private functions ---------------------------------------------------------*/
00064
00065
00066 /** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
00067   * @{
00068   */
00069
00070 /** @defgroup DMAEx_Exported_Functions_Group1 DMAEx Extended features functions
00071  *  @brief   Extended features functions
00072  *
00073 @verbatim
00074  ===============================================================================
00075                 #####  Extended features functions  #####
00076  ===============================================================================
00077     [..]  This section provides functions allowing to:
00078
00079     (+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
00080     (+) Configure the DMAMUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
00081        Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
00082        to respectively enable/disable the request generator.
00083
00084 @endverbatim
00085   * @{
00086   */
00087
00088 /**
00089   * @brief  Configure the DMAMUX synchronization parameters for a given DMA channel (instance).
00090   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
00091   *                     the configuration information for the specified DMA channel.
00092   * @param  pSyncConfig Pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters
00093   * @retval HAL status
00094   */
00095 HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
00096 {
00097   /* Check the parameters */
00098   assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
00099
00100   assert_param(IS_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
00101   assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig-> SyncPolarity));
00102   assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable));
00103   assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable));
00104   assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber));
00105
00106   /*Check if the DMA state is ready */
00107   if (hdma->State == HAL_DMA_STATE_READY)
00108   {
00109     /* Process Locked */
00110     __HAL_LOCK(hdma);
00111
00112     /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/
00113     MODIFY_REG(hdma->DMAmuxChannel->CCR, \
00114                (DMAMUX_CxCR_SYNC_ID | DMAMUX_CxCR_NBREQ | DMAMUX_CxCR_SPOL | DMAMUX_CxCR_SE | DMAMUX_CxCR_EGE), \
00115                (pSyncConfig->SyncSignalID                                       | \
00116                 ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos)    | \
00117                 pSyncConfig->SyncPolarity                                       | \
00118                 ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos)                 | \
00119                 ((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos)));
00120
00121     /* Process UnLocked */
00122     __HAL_UNLOCK(hdma);
00123
00124     return HAL_OK;
00125   }
00126   else
00127   {
00128     /*DMA State not Ready*/
00129     return HAL_ERROR;
00130   }
00131 }
00132
00133 /**
00134   * @brief  Configure the DMAMUX request generator block used by the given DMA channel (instance).
00135   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
00136   *                     the configuration information for the specified DMA channel.
00137 * @param  pRequestGeneratorConfig Pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef :
00138   *         contains the request generator parameters.
00139   *
00140   * @retval HAL status
00141   */
00142 HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
00143 {
00144   /* Check the parameters */
00145   assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
00146
00147   assert_param(IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
00148   assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity));
00149   assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber));
00150
00151   /* check if the DMA state is ready
00152      and DMA is using a DMAMUX request generator block
00153   */
00154   if ((hdma->State == HAL_DMA_STATE_READY) && (hdma->DMAmuxRequestGen != 0U))
00155   {
00156     /* Process Locked */
00157     __HAL_LOCK(hdma);
00158
00159     /* Set the request generator new parameters*/
00160     WRITE_REG(hdma->DMAmuxRequestGen->RGCR, (pRequestGeneratorConfig->SignalID       | \
00161                                              pRequestGeneratorConfig->Polarity       | \
00162                                              ((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos)));
00163
00164     /* Process UnLocked */
00165     __HAL_UNLOCK(hdma);
00166
00167     return HAL_OK;
00168   }
00169   else
00170   {
00171     return HAL_ERROR;
00172   }
00173 }
00174
00175 /**
00176   * @brief  Enable the DMAMUX request generator block used by the given DMA channel (instance).
00177   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
00178   *                     the configuration information for the specified DMA channel.
00179   * @retval HAL status
00180   */
00181 HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma)
00182 {
00183   /* Check the parameters */
00184   assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
00185
00186   /* check if the DMA state is ready
00187      and DMA is using a DMAMUX request generator block
00188   */
00189   if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U))
00190   {
00191     /* Enable the request generator*/
00192     SET_BIT(hdma->DMAmuxRequestGen->RGCR, DMAMUX_RGxCR_GE);
00193
00194     return HAL_OK;
00195   }
00196   else
00197   {
00198     return HAL_ERROR;
00199   }
00200 }
00201
00202 /**
00203   * @brief  Disable the DMAMUX request generator block used by the given DMA channel (instance).
00204   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
00205   *                     the configuration information for the specified DMA channel.
00206   * @retval HAL status
00207   */
00208 HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma)
00209 {
00210   /* Check the parameters */
00211   assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
00212
00213   /* check if the DMA state is ready
00214      and DMA is using a DMAMUX request generator block
00215   */
00216   if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))
00217   {
00218     /* Disable the request generator*/
00219     CLEAR_BIT(hdma->DMAmuxRequestGen->RGCR, DMAMUX_RGxCR_GE);
00220
00221     return HAL_OK;
00222   }
00223   else
00224   {
00225     return HAL_ERROR;
00226   }
00227 }
00228
00229 /**
00230   * @brief  Handles DMAMUX interrupt request.
00231   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
00232   *               the configuration information for the specified DMA channel.
00233   * @retval None
00234   */
00235 void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)
00236 {
00237   /* Check for DMAMUX Synchronization overrun */
00238   if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
00239   {
00240     /* Disable the synchro overrun interrupt */
00241     CLEAR_BIT(hdma->DMAmuxChannel->CCR, DMAMUX_CxCR_SOIE);
00242
00243     /* Clear the DMAMUX synchro overrun flag */
00244     WRITE_REG(hdma->DMAmuxChannelStatus->CFR, hdma->DMAmuxChannelStatusMask);
00245
00246     /* Update error code */
00247     hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
00248
00249     if (hdma->XferErrorCallback != NULL)
00250     {
00251       /* Transfer error callback */
00252       hdma->XferErrorCallback(hdma);
00253     }
00254   }
00255
00256   if (hdma->DMAmuxRequestGen != 0U)
00257   {
00258     /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */
00259     if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
00260     {
00261       /* Disable the request gen overrun interrupt */
00262       CLEAR_BIT(hdma->DMAmuxRequestGen->RGCR, DMAMUX_RGxCR_OIE);
00263
00264       /* Clear the DMAMUX request generator overrun flag */
00265       WRITE_REG(hdma->DMAmuxRequestGenStatus->RGCFR, hdma->DMAmuxRequestGenStatusMask);
00266
00267       /* Update error code */
00268       hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
00269
00270       if (hdma->XferErrorCallback != NULL)
00271       {
00272         /* Transfer error callback */
00273         hdma->XferErrorCallback(hdma);
00274       }
00275     }
00276   }
00277 }
00278
00279 /**
00280   * @}
00281   */
00282
00283 /**
00284   * @}
00285   */
00286
00287 #endif /* HAL_DMA_MODULE_ENABLED */
00288 /**
00289   * @}
00290   */
00291
00292 /**
00293   * @}
00294   */
00295
00296 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_dma_ex.h Source File

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stm32wbxx_hal_dma_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_dma_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DMA HAL extension module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_DMA_EX_H
00022 #define STM32WBxx_HAL_DMA_EX_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030 #include "stm32wbxx_ll_dmamux.h"
00031
00032 /** @addtogroup STM32WBxx_HAL_Driver
00033   * @{
00034   */
00035
00036 /** @addtogroup DMAEx
00037   * @{
00038   */
00039
00040 /* Exported types ------------------------------------------------------------*/
00041 /** @defgroup DMAEx_Exported_Types DMAEx Exported Types
00042   * @{
00043   */
00044
00045 /**
00046   * @brief  HAL DMA Synchro definition
00047   */
00048
00049
00050 /**
00051   * @brief  HAL DMAMUX Synchronization configuration structure definition
00052   */
00053 typedef struct
00054 {
00055   uint32_t SyncSignalID;        /*!< Specifies the synchronization signal gating the DMA request in periodic mode.
00056                                      This parameter can be a value of @ref DMAEx_DMAMUX_SyncSignalID_selection */
00057
00058   uint32_t SyncPolarity;        /*!< Specifies the polarity of the signal on which the DMA request is synchronized.
00059                                      This parameter can be a value of @ref DMAEx_DMAMUX_SyncPolarity_selection */
00060
00061   FunctionalState SyncEnable;   /*!< Specifies if the synchronization shall be enabled or disabled
00062                                      This parameter can take the value ENABLE or DISABLE*/
00063
00064   FunctionalState EventEnable;  /*!< Specifies if an event shall be generated once the RequestNumber is reached.
00065                                      This parameter can take the value ENABLE or DISABLE */
00066
00067   uint32_t RequestNumber;       /*!< Specifies the number of DMA request that will be authorized after a sync event
00068                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
00069
00070
00071 } HAL_DMA_MuxSyncConfigTypeDef;
00072
00073
00074 /**
00075   * @brief  HAL DMAMUX request generator parameters structure definition
00076   */
00077 typedef struct
00078 {
00079   uint32_t SignalID;             /*!< Specifies the ID of the signal used for DMAMUX request generator
00080                                      This parameter can be a value of @ref DMAEx_DMAMUX_SignalGeneratorID_selection */
00081
00082   uint32_t Polarity;            /*!< Specifies the polarity of the signal on which the request is generated.
00083                                      This parameter can be a value of @ref DMAEx_DMAMUX_RequestGeneneratorPolarity_selection */
00084
00085   uint32_t RequestNumber;       /*!< Specifies the number of DMA request that will be generated after a signal event
00086                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
00087
00088 } HAL_DMA_MuxRequestGeneratorConfigTypeDef;
00089
00090 /**
00091   * @}
00092   */
00093
00094 /* Exported constants --------------------------------------------------------*/
00095 /** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
00096   * @{
00097   */
00098
00099 /** @defgroup DMAEx_DMAMUX_SyncSignalID_selection DMAMUX SyncSignalID selection
00100   * @{
00101   */
00102 #define HAL_DMAMUX1_SYNC_EXTI0                  LL_DMAMUX_SYNC_EXTI_LINE0       /*!<  Synchronization Signal is EXTI0  IT   */
00103 #define HAL_DMAMUX1_SYNC_EXTI1                  LL_DMAMUX_SYNC_EXTI_LINE1       /*!<  Synchronization Signal is EXTI1  IT   */
00104 #define HAL_DMAMUX1_SYNC_EXTI2                  LL_DMAMUX_SYNC_EXTI_LINE2       /*!<  Synchronization Signal is EXTI2  IT   */
00105 #define HAL_DMAMUX1_SYNC_EXTI3                  LL_DMAMUX_SYNC_EXTI_LINE3       /*!<  Synchronization Signal is EXTI3  IT   */
00106 #define HAL_DMAMUX1_SYNC_EXTI4                  LL_DMAMUX_SYNC_EXTI_LINE4       /*!<  Synchronization Signal is EXTI4  IT   */
00107 #define HAL_DMAMUX1_SYNC_EXTI5                  LL_DMAMUX_SYNC_EXTI_LINE5       /*!<  Synchronization Signal is EXTI5  IT   */
00108 #define HAL_DMAMUX1_SYNC_EXTI6                  LL_DMAMUX_SYNC_EXTI_LINE6       /*!<  Synchronization Signal is EXTI6  IT   */
00109 #define HAL_DMAMUX1_SYNC_EXTI7                  LL_DMAMUX_SYNC_EXTI_LINE7       /*!<  Synchronization Signal is EXTI7  IT   */
00110 #define HAL_DMAMUX1_SYNC_EXTI8                  LL_DMAMUX_SYNC_EXTI_LINE8       /*!<  Synchronization Signal is EXTI8  IT   */
00111 #define HAL_DMAMUX1_SYNC_EXTI9                  LL_DMAMUX_SYNC_EXTI_LINE9       /*!<  Synchronization Signal is EXTI9  IT   */
00112 #define HAL_DMAMUX1_SYNC_EXTI10                 LL_DMAMUX_SYNC_EXTI_LINE10      /*!<  Synchronization Signal is EXTI10 IT   */
00113 #define HAL_DMAMUX1_SYNC_EXTI11                 LL_DMAMUX_SYNC_EXTI_LINE11      /*!<  Synchronization Signal is EXTI11 IT   */
00114 #define HAL_DMAMUX1_SYNC_EXTI12                 LL_DMAMUX_SYNC_EXTI_LINE12      /*!<  Synchronization Signal is EXTI12 IT   */
00115 #define HAL_DMAMUX1_SYNC_EXTI13                 LL_DMAMUX_SYNC_EXTI_LINE13      /*!<  Synchronization Signal is EXTI13 IT   */
00116 #define HAL_DMAMUX1_SYNC_EXTI14                 LL_DMAMUX_SYNC_EXTI_LINE14      /*!<  Synchronization Signal is EXTI14 IT   */
00117 #define HAL_DMAMUX1_SYNC_EXTI15                 LL_DMAMUX_SYNC_EXTI_LINE15      /*!<  Synchronization Signal is EXTI15 IT   */
00118 #define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT        LL_DMAMUX_SYNC_DMAMUX_CH0       /*!<  Synchronization Signal is DMAMUX1 Channel0 Event  */
00119 #define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT        LL_DMAMUX_SYNC_DMAMUX_CH1       /*!<  Synchronization Signal is DMAMUX1 Channel1 Event  */
00120 #define HAL_DMAMUX1_SYNC_LPTIM1_OUT             LL_DMAMUX_SYNC_LPTIM1_OUT       /*!<  Synchronization Signal is LPTIM1 OUT */
00121 #define HAL_DMAMUX1_SYNC_LPTIM2_OUT             LL_DMAMUX_SYNC_LPTIM2_OUT       /*!<  Synchronization Signal is LPTIM2 OUT */
00122
00123 /**
00124   * @}
00125   */
00126
00127 /** @defgroup DMAEx_DMAMUX_SyncPolarity_selection DMAMUX SyncPolarity selection
00128   * @{
00129   */
00130 #define HAL_DMAMUX_SYNC_NO_EVENT                LL_DMAMUX_SYNC_NO_EVENT            /*!< block synchronization events                    */
00131 #define HAL_DMAMUX_SYNC_RISING                  LL_DMAMUX_SYNC_POL_RISING          /*!< synchronize with rising edge events             */
00132 #define HAL_DMAMUX_SYNC_FALLING                 LL_DMAMUX_SYNC_POL_FALLING         /*!< synchronize with falling edge events            */
00133 #define HAL_DMAMUX_SYNC_RISING_FALLING          LL_DMAMUX_SYNC_POL_RISING_FALLING  /*!< synchronize with rising and falling edge events */
00134
00135 /**
00136   * @}
00137   */
00138
00139 /** @defgroup DMAEx_DMAMUX_SignalGeneratorID_selection DMAMUX SignalGeneratorID selection
00140   * @{
00141   */
00142 #define HAL_DMAMUX1_REQ_GEN_EXTI0               LL_DMAMUX_REQ_GEN_EXTI_LINE0    /*!< Request generator Signal is EXTI0 IT    */
00143 #define HAL_DMAMUX1_REQ_GEN_EXTI1               LL_DMAMUX_REQ_GEN_EXTI_LINE1    /*!< Request generator Signal is EXTI1 IT    */
00144 #define HAL_DMAMUX1_REQ_GEN_EXTI2               LL_DMAMUX_REQ_GEN_EXTI_LINE2    /*!< Request generator Signal is EXTI2 IT    */
00145 #define HAL_DMAMUX1_REQ_GEN_EXTI3               LL_DMAMUX_REQ_GEN_EXTI_LINE3    /*!< Request generator Signal is EXTI3 IT    */
00146 #define HAL_DMAMUX1_REQ_GEN_EXTI4               LL_DMAMUX_REQ_GEN_EXTI_LINE4    /*!< Request generator Signal is EXTI4 IT    */
00147 #define HAL_DMAMUX1_REQ_GEN_EXTI5               LL_DMAMUX_REQ_GEN_EXTI_LINE5    /*!< Request generator Signal is EXTI5 IT    */
00148 #define HAL_DMAMUX1_REQ_GEN_EXTI6               LL_DMAMUX_REQ_GEN_EXTI_LINE6    /*!< Request generator Signal is EXTI6 IT    */
00149 #define HAL_DMAMUX1_REQ_GEN_EXTI7               LL_DMAMUX_REQ_GEN_EXTI_LINE7    /*!< Request generator Signal is EXTI7 IT    */
00150 #define HAL_DMAMUX1_REQ_GEN_EXTI8               LL_DMAMUX_REQ_GEN_EXTI_LINE8    /*!< Request generator Signal is EXTI8 IT    */
00151 #define HAL_DMAMUX1_REQ_GEN_EXTI9               LL_DMAMUX_REQ_GEN_EXTI_LINE9    /*!< Request generator Signal is EXTI9 IT    */
00152 #define HAL_DMAMUX1_REQ_GEN_EXTI10              LL_DMAMUX_REQ_GEN_EXTI_LINE10   /*!< Request generator Signal is EXTI10 IT   */
00153 #define HAL_DMAMUX1_REQ_GEN_EXTI11              LL_DMAMUX_REQ_GEN_EXTI_LINE11   /*!< Request generator Signal is EXTI11 IT   */
00154 #define HAL_DMAMUX1_REQ_GEN_EXTI12              LL_DMAMUX_REQ_GEN_EXTI_LINE12   /*!< Request generator Signal is EXTI12 IT   */
00155 #define HAL_DMAMUX1_REQ_GEN_EXTI13              LL_DMAMUX_REQ_GEN_EXTI_LINE13   /*!< Request generator Signal is EXTI13 IT   */
00156 #define HAL_DMAMUX1_REQ_GEN_EXTI14              LL_DMAMUX_REQ_GEN_EXTI_LINE14   /*!< Request generator Signal is EXTI14 IT   */
00157 #define HAL_DMAMUX1_REQ_GEN_EXTI15              LL_DMAMUX_REQ_GEN_EXTI_LINE15   /*!< Request generator Signal is EXTI15 IT   */
00158 #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT     LL_DMAMUX_REQ_GEN_DMAMUX_CH0    /*!< Request generator Signal is DMAMUX1 Channel0 Event */
00159 #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT     LL_DMAMUX_REQ_GEN_DMAMUX_CH1    /*!< Request generator Signal is DMAMUX1 Channel1 Event */
00160 #define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT          LL_DMAMUX_REQ_GEN_LPTIM1_OUT    /*!< Request generator Signal is LPTIM1 OUT  */
00161 #define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT          LL_DMAMUX_REQ_GEN_LPTIM2_OUT    /*!< Request generator Signal is LPTIM2 OUT  */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX RequestGeneneratorPolarity selection
00168   * @{
00169   */
00170 #define HAL_DMAMUX_REQ_GEN_NO_EVENT             LL_DMAMUX_REQ_GEN_NO_EVENT              /*!< block request generator events                     */
00171 #define HAL_DMAMUX_REQ_GEN_RISING               LL_DMAMUX_REQ_GEN_POL_RISING            /*!< generate request on rising edge events             */
00172 #define HAL_DMAMUX_REQ_GEN_FALLING              LL_DMAMUX_REQ_GEN_POL_FALLING           /*!< generate request on falling edge events            */
00173 #define HAL_DMAMUX_REQ_GEN_RISING_FALLING       LL_DMAMUX_REQ_GEN_POL_RISING_FALLING    /*!< generate request on rising and falling edge events */
00174
00175 /**
00176   * @}
00177   */
00178
00179 /**
00180   * @}
00181   */
00182
00183 /* Exported macro ------------------------------------------------------------*/
00184
00185 /* Exported functions --------------------------------------------------------*/
00186 /** @addtogroup DMAEx_Exported_Functions
00187   * @{
00188   */
00189
00190 /* IO operation functions *****************************************************/
00191 /** @addtogroup DMAEx_Exported_Functions_Group1
00192   * @{
00193   */
00194
00195 /* ------------------------- REQUEST -----------------------------------------*/
00196 HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma,
00197                                                       HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);
00198 HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
00199 HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
00200 /* -------------------------------------------------------------------------- */
00201
00202 /* ------------------------- SYNCHRO -----------------------------------------*/
00203 HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig);
00204 /* -------------------------------------------------------------------------- */
00205
00206 void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma);
00207
00208 /**
00209   * @}
00210   */
00211
00212 /**
00213   * @}
00214   */
00215
00216
00217 /* Private macros ------------------------------------------------------------*/
00218 /** @defgroup DMAEx_Private_Macros DMAEx Private Macros
00219   * @brief    DMAEx private macros
00220   * @{
00221   */
00222
00223 #define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID)                     ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_LPTIM2_OUT)
00224
00225 #define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER)           (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
00226
00227 #define IS_DMAMUX_SYNC_POLARITY(POLARITY)                       (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT)     || \
00228                                                                  ((POLARITY) == HAL_DMAMUX_SYNC_RISING)       || \
00229                                                                  ((POLARITY) == HAL_DMAMUX_SYNC_FALLING)      || \
00230                                                                  ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))
00231
00232 #define IS_DMAMUX_SYNC_STATE(SYNC)                              (((SYNC) == DISABLE)   || ((SYNC) == ENABLE))
00233
00234 #define IS_DMAMUX_SYNC_EVENT(EVENT)                             (((EVENT) == DISABLE)   || \
00235                                                                  ((EVENT) == ENABLE))
00236
00237 #define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID)              ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT)
00238
00239 #define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER)    (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
00240
00241 #define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY)                (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT)    || \
00242                                                                  ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING)      || \
00243                                                                  ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING)     || \
00244                                                                  ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING))
00245
00246 /**
00247   * @}
00248   */
00249
00250
00251 /**
00252   * @}
00253   */
00254
00255 /**
00256   * @}
00257   */
00258
00259 #ifdef __cplusplus
00260 }
00261 #endif
00262
00263 #endif /* STM32WBxx_HAL_DMA_EX_H */
00264
00265 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_exti.c Source File

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stm32wbxx_hal_exti.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_exti.c
00004   * @author  MCD Application Team
00005   * @brief   EXTI HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the General Purpose Input/Output (EXTI) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *
00011   @verbatim
00012   ==============================================================================
00013                     ##### EXTI Peripheral features #####
00014   ==============================================================================
00015   [..]
00016     (+) Each Exti line can be configured within this driver.
00017
00018     (+) Exti line can be configured in 3 different modes
00019         (++) Interrupt
00020         (++) Event
00021         (++) Both of them
00022
00023     (+) Configurable Exti lines can be configured with 3 different triggers
00024         (++) Rising
00025         (++) Falling
00026         (++) Both of them
00027
00028     (+) When set in interrupt mode, configurable Exti lines have one
00029         interrupt pending register:
00030         (++) Trigger request occurred
00031
00032     (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
00033         be selected throught multiplexer.
00034
00035                      ##### How to use this driver #####
00036   ==============================================================================
00037   [..]
00038
00039     (#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
00040         (++) Choose the interrupt line number by setting "Line" member from
00041              EXTI_ConfigTypeDef structure.
00042         (++) Configure the interrupt and/or event mode using "Mode" member from
00043              EXTI_ConfigTypeDef structure.
00044         (++) For configurable lines, configure rising and/or falling trigger
00045              "Trigger" member from EXTI_ConfigTypeDef structure.
00046         (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
00047              member from GPIO_InitTypeDef structure.
00048
00049     (#) Get current Exti configuration of a dedicated line using
00050         HAL_EXTI_GetConfigLine().
00051         (++) Provide exiting handle as parameter.
00052         (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
00053
00054     (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
00055         (++) Provide exiting handle as parameter.
00056
00057     (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
00058         (++) Provide exiting handle as first parameter.
00059         (++) Provide which callback will be registered using one value from
00060              EXTI_CallbackIDTypeDef.
00061         (++) Provide callback function pointer.
00062
00063     (#) Get interrupt pending bit using HAL_EXTI_GetPending().
00064
00065     (#) Clear interrupt pending bit using HAL_EXTI_GetPending().
00066
00067     (#) Generate software interrupt using HAL_EXTI_GenerateSWI().
00068
00069   @endverbatim
00070   ******************************************************************************
00071   * @attention
00072   *
00073   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00074   * All rights reserved.</center></h2>
00075   *
00076   * This software component is licensed by ST under BSD 3-Clause license,
00077   * the "License"; You may not use this file except in compliance with the
00078   * License. You may obtain a copy of the License at:
00079   *                        opensource.org/licenses/BSD-3-Clause
00080   *
00081   ******************************************************************************
00082   */
00083
00084 /* Includes ------------------------------------------------------------------*/
00085 #include "stm32wbxx_hal.h"
00086
00087 /** @addtogroup STM32WBxx_HAL_Driver
00088   * @{
00089   */
00090
00091 /** @addtogroup EXTI
00092   * @{
00093   */
00094 /** MISRA C:2012 deviation rule has been granted for following rule:
00095   * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out
00096   * of bounds [0,3] in following API :
00097   * HAL_EXTI_SetConfigLine
00098   * HAL_EXTI_GetConfigLine
00099   * HAL_EXTI_ClearConfigLine
00100   */
00101
00102 #ifdef HAL_EXTI_MODULE_ENABLED
00103
00104 /* Private typedef -----------------------------------------------------------*/
00105 /* Private defines ------------------------------------------------------------*/
00106 /** @defgroup EXTI_Private_Constants EXTI Private Constants
00107   * @{
00108   */
00109 #define EXTI_MODE_OFFSET                    0x04u   /* 0x10: offset between CPU IMR/EMR registers */
00110 #define EXTI_CONFIG_OFFSET                  0x08u   /* 0x20: offset between CPU Rising/Falling configuration registers */
00111 /**
00112   * @}
00113   */
00114
00115 /* Private macros ------------------------------------------------------------*/
00116 /* Private variables ---------------------------------------------------------*/
00117 /* Private function prototypes -----------------------------------------------*/
00118 /* Exported functions --------------------------------------------------------*/
00119
00120 /** @addtogroup EXTI_Exported_Functions
00121   * @{
00122   */
00123
00124 /** @addtogroup EXTI_Exported_Functions_Group1
00125  *  @brief    Configuration functions
00126  *
00127 @verbatim
00128  ===============================================================================
00129               ##### Configuration functions #####
00130  ===============================================================================
00131
00132 @endverbatim
00133   * @{
00134   */
00135
00136 /**
00137   * @brief  Set configuration of a dedicated Exti line.
00138   * @param  hexti Exti handle.
00139   * @param  pExtiConfig Pointer on EXTI configuration to be set.
00140   * @retval HAL Status.
00141   */
00142 HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
00143 {
00144   __IO uint32_t *regaddr;
00145   uint32_t regval;
00146   uint32_t linepos;
00147   uint32_t maskline;
00148   uint32_t offset;
00149
00150   /* Check null pointer */
00151   if ((hexti == NULL) || (pExtiConfig == NULL))
00152   {
00153     return HAL_ERROR;
00154   }
00155
00156   /* Check parameters */
00157   assert_param(IS_EXTI_LINE(pExtiConfig->Line));
00158   assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
00159
00160   /* Assign line number to handle */
00161   hexti->Line = pExtiConfig->Line;
00162
00163   /* compute line register offset and line mask */
00164   offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
00165   linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
00166   maskline = (1uL << linepos);
00167
00168   /* Configure triggers for configurable lines */
00169   if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
00170   {
00171     assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
00172
00173     /* Configure rising trigger */
00174     regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
00175     regval = *regaddr;
00176
00177     /* Mask or set line */
00178     if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)
00179     {
00180       regval |= maskline;
00181     }
00182     else
00183     {
00184       regval &= ~maskline;
00185     }
00186
00187     /* Store rising trigger mode */
00188     *regaddr = regval;
00189
00190     /* Configure falling trigger */
00191     regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
00192     regval = *regaddr;
00193
00194     /* Mask or set line */
00195     if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)
00196     {
00197       regval |= maskline;
00198     }
00199     else
00200     {
00201       regval &= ~maskline;
00202     }
00203
00204     /* Store falling trigger mode */
00205     *regaddr = regval;
00206
00207     /* Configure gpio port selection in case of gpio exti line */
00208     if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
00209     {
00210       assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
00211       assert_param(IS_EXTI_GPIO_PIN(linepos));
00212
00213       regval = SYSCFG->EXTICR[linepos >> 2u];
00214       regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
00215       regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
00216       SYSCFG->EXTICR[linepos >> 2u] = regval;
00217     }
00218   }
00219
00220   /* Configure interrupt mode : read current mode */
00221   regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
00222   regval = *regaddr;
00223
00224   /* Mask or set line */
00225   if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)
00226   {
00227     regval |= maskline;
00228   }
00229   else
00230   {
00231     regval &= ~maskline;
00232   }
00233
00234   /* Store interrupt mode */
00235   *regaddr = regval;
00236
00237   /* The event mode cannot be configured if the line does not support it */
00238   assert_param(((pExtiConfig->Line & EXTI_EVENT) == EXTI_EVENT) || ((pExtiConfig->Mode & EXTI_MODE_EVENT) != EXTI_MODE_EVENT));
00239
00240   /* Configure event mode : read current mode */
00241   regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
00242   regval = *regaddr;
00243
00244   /* Mask or set line */
00245   if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
00246   {
00247     regval |= maskline;
00248   }
00249   else
00250   {
00251     regval &= ~maskline;
00252   }
00253
00254   /* Store event mode */
00255   *regaddr = regval;
00256
00257   return HAL_OK;
00258 }
00259
00260
00261 /**
00262   * @brief  Get configuration of a dedicated Exti line.
00263   * @param  hexti Exti handle.
00264   * @param  pExtiConfig Pointer on structure to store Exti configuration.
00265   * @retval HAL Status.
00266   */
00267 HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
00268 {
00269   __IO uint32_t *regaddr;
00270   uint32_t regval;
00271   uint32_t linepos;
00272   uint32_t maskline;
00273   uint32_t offset;
00274
00275   /* Check null pointer */
00276   if ((hexti == NULL) || (pExtiConfig == NULL))
00277   {
00278     return HAL_ERROR;
00279   }
00280
00281   /* Check the parameter */
00282   assert_param(IS_EXTI_LINE(hexti->Line));
00283
00284   /* Store handle line number to configiguration structure */
00285   pExtiConfig->Line = hexti->Line;
00286
00287   /* compute line register offset and line mask */
00288   offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
00289   linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
00290   maskline = (1uL << linepos);
00291
00292   /* 1] Get core mode : interrupt */
00293   regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
00294   regval = *regaddr;
00295
00296   /* Check if selected line is enable */
00297   if ((regval & maskline) != 0x00u)
00298   {
00299     pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
00300   }
00301   else
00302   {
00303     pExtiConfig->Mode = EXTI_MODE_NONE;
00304   }
00305
00306   /* Get event mode */
00307   regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
00308   regval = *regaddr;
00309
00310   /* Check if selected line is enable */
00311   if ((regval & maskline) != 0x00u)
00312   {
00313     pExtiConfig->Mode |= EXTI_MODE_EVENT;
00314   }
00315
00316   /* 2] Get trigger for configurable lines : rising */
00317   if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
00318   {
00319     regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
00320     regval = *regaddr;
00321
00322     /* Check if configuration of selected line is enable */
00323     if ((regval & maskline) != 0x00u)
00324     {
00325       pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
00326     }
00327     else
00328     {
00329       pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
00330     }
00331
00332     /* Get falling configuration */
00333     regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
00334     regval = *regaddr;
00335
00336     /* Check if configuration of selected line is enable */
00337     if ((regval & maskline) != 0x00u)
00338     {
00339       pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
00340     }
00341
00342     /* Get Gpio port selection for gpio lines */
00343     if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
00344     {
00345       assert_param(IS_EXTI_GPIO_PIN(linepos));
00346
00347       regval = SYSCFG->EXTICR[linepos >> 2u];
00348       pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24);
00349     }
00350     else
00351     {
00352       pExtiConfig->GPIOSel = 0x00u;
00353     }
00354   }
00355   else
00356   {
00357     pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
00358     pExtiConfig->GPIOSel = 0x00u;
00359   }
00360
00361   return HAL_OK;
00362 }
00363
00364
00365 /**
00366   * @brief  Clear whole configuration of a dedicated Exti line.
00367   * @param  hexti Exti handle.
00368   * @retval HAL Status.
00369   */
00370 HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
00371 {
00372   __IO uint32_t *regaddr;
00373   uint32_t regval;
00374   uint32_t linepos;
00375   uint32_t maskline;
00376   uint32_t offset;
00377
00378   /* Check null pointer */
00379   if (hexti == NULL)
00380   {
00381     return HAL_ERROR;
00382   }
00383
00384   /* Check the parameter */
00385   assert_param(IS_EXTI_LINE(hexti->Line));
00386
00387   /* compute line register offset and line mask */
00388   offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
00389   linepos = (hexti->Line & EXTI_PIN_MASK);
00390   maskline = (1uL << linepos);
00391
00392   /* 1] Clear interrupt mode */
00393   regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
00394   regval = (*regaddr & ~maskline);
00395   *regaddr = regval;
00396
00397   /* 2] Clear event mode */
00398   regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
00399   regval = (*regaddr & ~maskline);
00400   *regaddr = regval;
00401
00402   /* 3] Clear triggers in case of configurable lines */
00403   if ((hexti->Line & EXTI_CONFIG) != 0x00u)
00404   {
00405     regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
00406     regval = (*regaddr & ~maskline);
00407     *regaddr = regval;
00408
00409     regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
00410     regval = (*regaddr & ~maskline);
00411     *regaddr = regval;
00412
00413     /* Get Gpio port selection for gpio lines */
00414     if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
00415     {
00416       assert_param(IS_EXTI_GPIO_PIN(linepos));
00417
00418       regval = SYSCFG->EXTICR[linepos >> 2u];
00419       regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
00420       SYSCFG->EXTICR[linepos >> 2u] = regval;
00421     }
00422   }
00423
00424   return HAL_OK;
00425 }
00426
00427
00428 /**
00429   * @brief  Register callback for a dedicaated Exti line.
00430   * @param  hexti Exti handle.
00431   * @param  CallbackID User callback identifier.
00432   *         This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
00433   * @param  pPendingCbfn function pointer to be stored as callback.
00434   * @retval HAL Status.
00435   */
00436 HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
00437 {
00438   HAL_StatusTypeDef status = HAL_OK;
00439
00440   switch (CallbackID)
00441   {
00442     case  HAL_EXTI_COMMON_CB_ID:
00443       hexti->PendingCallback = pPendingCbfn;
00444       break;
00445
00446     default:
00447       status = HAL_ERROR;
00448       break;
00449   }
00450
00451   return status;
00452 }
00453
00454
00455 /**
00456   * @brief  Store line number as handle private field.
00457   * @param  hexti Exti handle.
00458   * @param  ExtiLine Exti line number.
00459   *         This parameter can be from 0 to @ref EXTI_LINE_NB.
00460   * @retval HAL Status.
00461   */
00462 HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
00463 {
00464   /* Check the parameters */
00465   assert_param(IS_EXTI_LINE(ExtiLine));
00466
00467   /* Check null pointer */
00468   if (hexti == NULL)
00469   {
00470     return HAL_ERROR;
00471   }
00472   else
00473   {
00474     /* Store line number as handle private field */
00475     hexti->Line = ExtiLine;
00476
00477     return HAL_OK;
00478   }
00479 }
00480
00481
00482 /**
00483   * @}
00484   */
00485
00486 /** @addtogroup EXTI_Exported_Functions_Group2
00487  *  @brief EXTI IO functions.
00488  *
00489 @verbatim
00490  ===============================================================================
00491                        ##### IO operation functions #####
00492  ===============================================================================
00493
00494 @endverbatim
00495   * @{
00496   */
00497
00498 /**
00499   * @brief  Handle EXTI interrupt request.
00500   * @param  hexti Exti handle.
00501   * @retval none.
00502   */
00503 void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
00504 {
00505   __IO uint32_t *regaddr;
00506   uint32_t regval;
00507   uint32_t maskline;
00508   uint32_t offset;
00509
00510   /* Compute line register offset and line mask */
00511   offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
00512   maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
00513
00514   /* Get pending bit  */
00515   regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset));
00516   regval = (*regaddr & maskline);
00517
00518   if (regval != 0x00u)
00519   {
00520     /* Clear pending bit */
00521     *regaddr = maskline;
00522
00523     /* Call callback */
00524     if (hexti->PendingCallback != NULL)
00525     {
00526       hexti->PendingCallback();
00527     }
00528   }
00529 }
00530
00531
00532 /**
00533   * @brief  Get interrupt pending bit of a dedicated line.
00534   * @param  hexti Exti handle.
00535   * @param  Edge Specify which pending edge as to be checked.
00536   *         This parameter can be one of the following values:
00537   *           @arg @ref EXTI_TRIGGER_RISING_FALLING
00538   *         This parameter is kept for compatibility with other series.
00539   * @retval 1 if interrupt is pending else 0.
00540   */
00541 uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
00542 {
00543   __IO uint32_t *regaddr;
00544   uint32_t regval;
00545   uint32_t linepos;
00546   uint32_t maskline;
00547   uint32_t offset;
00548
00549   /* Check parameters */
00550   assert_param(IS_EXTI_LINE(hexti->Line));
00551   assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
00552   assert_param(IS_EXTI_PENDING_EDGE(Edge));
00553
00554   /* compute line register offset and line mask */
00555   offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
00556   linepos = (hexti->Line & EXTI_PIN_MASK);
00557   maskline = (1uL << linepos);
00558
00559   /* Get pending bit */
00560   regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset));
00561
00562   /* return 1 if bit is set else 0 */
00563   regval = ((*regaddr & maskline) >> linepos);
00564   return regval;
00565 }
00566
00567
00568 /**
00569   * @brief  Clear interrupt pending bit of a dedicated line.
00570   * @param  hexti Exti handle.
00571   * @param  Edge Specify which pending edge as to be clear.
00572   *         This parameter can be one of the following values:
00573   *           @arg @ref EXTI_TRIGGER_RISING_FALLING
00574   *         This parameter is kept for compatibility with other series.
00575   * @retval None.
00576   */
00577 void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
00578 {
00579   __IO uint32_t *regaddr;
00580   uint32_t maskline;
00581   uint32_t offset;
00582
00583   /* Check parameters */
00584   assert_param(IS_EXTI_LINE(hexti->Line));
00585   assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
00586   assert_param(IS_EXTI_PENDING_EDGE(Edge));
00587
00588   /* compute line register offset and line mask */
00589   offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
00590   maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
00591
00592   /* Get pending register address */
00593   regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset));
00594
00595   /* Clear Pending bit */
00596   *regaddr =  maskline;
00597 }
00598
00599
00600 /**
00601   * @brief  Generate a software interrupt for a dedicated line.
00602   * @param  hexti Exti handle.
00603   * @retval None.
00604   */
00605 void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
00606 {
00607   __IO uint32_t *regaddr;
00608   uint32_t maskline;
00609   uint32_t offset;
00610
00611   /* Check parameters */
00612   assert_param(IS_EXTI_LINE(hexti->Line));
00613   assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
00614
00615   /* compute line register offset and line mask */
00616   offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
00617   maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
00618
00619   regaddr = (&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset));
00620   *regaddr = maskline;
00621 }
00622
00623
00624 /**
00625   * @}
00626   */
00627
00628 /**
00629   * @}
00630   */
00631
00632 #endif /* HAL_EXTI_MODULE_ENABLED */
00633 /**
00634   * @}
00635   */
00636
00637 /**
00638   * @}
00639   */
00640
00641 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_exti.h Source File

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stm32wbxx_hal_exti.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_exti.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of EXTI HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_EXTI_H
00022 #define STM32WBxx_HAL_EXTI_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 /** @addtogroup STM32WBxx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @defgroup EXTI EXTI
00036   * @brief EXTI HAL module driver
00037   * @{
00038   */
00039
00040 /* Exported types ------------------------------------------------------------*/
00041
00042 /** @defgroup EXTI_Exported_Types EXTI Exported Types
00043   * @{
00044   */
00045 typedef enum
00046 {
00047   HAL_EXTI_COMMON_CB_ID          = 0x00U,
00048 } EXTI_CallbackIDTypeDef;
00049
00050
00051 /**
00052   * @brief  EXTI Handle structure definition
00053   */
00054 typedef struct
00055 {
00056   uint32_t Line;                    /*!<  Exti line number */
00057   void (* PendingCallback)(void);   /*!<  Exti pending callback */
00058 } EXTI_HandleTypeDef;
00059
00060 /**
00061   * @brief  EXTI Configuration structure definition
00062   */
00063 typedef struct
00064 {
00065   uint32_t Line;      /*!< The Exti line to be configured. This parameter
00066                            can be a value of @ref EXTI_Line */
00067   uint32_t Mode;      /*!< The Exit Mode to be configured for a core.
00068                            This parameter can be a combination of @ref EXTI_Mode */
00069   uint32_t Trigger;   /*!< The Exti Trigger to be configured. This parameter
00070                            can be a value of @ref EXTI_Trigger */
00071   uint32_t GPIOSel;   /*!< The Exti GPIO multiplexer selection to be configured.
00072                            This parameter is only possible for line 0 to 15. It
00073                            can be a value of @ref EXTI_GPIOSel */
00074 } EXTI_ConfigTypeDef;
00075
00076 /**
00077   * @}
00078   */
00079
00080 /* Exported constants --------------------------------------------------------*/
00081 /** @defgroup EXTI_Exported_Constants EXTI Exported Constants
00082   * @{
00083   */
00084
00085 /** @defgroup EXTI_Line  EXTI Line
00086   * @{
00087   */
00088 #define EXTI_LINE_0                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | 0x00u)
00089 #define EXTI_LINE_1                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | 0x01u)
00090 #define EXTI_LINE_2                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | 0x02u)
00091 #define EXTI_LINE_3                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | 0x03u)
00092 #define EXTI_LINE_4                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | 0x04u)
00093 #define EXTI_LINE_5                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | 0x05u)
00094 #define EXTI_LINE_6                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | 0x06u)
00095 #define EXTI_LINE_7                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | 0x07u)
00096 #define EXTI_LINE_8                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | 0x08u)
00097 #define EXTI_LINE_9                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | 0x09u)
00098 #define EXTI_LINE_10                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | 0x0Au)
00099 #define EXTI_LINE_11                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | 0x0Bu)
00100 #define EXTI_LINE_12                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | 0x0Cu)
00101 #define EXTI_LINE_13                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | 0x0Du)
00102 #define EXTI_LINE_14                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | 0x0Eu)
00103 #define EXTI_LINE_15                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | 0x0Fu)
00104 #define EXTI_LINE_16                        (EXTI_CONFIG   |              EXTI_REG1 | 0x10u)
00105 #define EXTI_LINE_17                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | 0x11u)
00106 #define EXTI_LINE_18                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | 0x12u)
00107 #define EXTI_LINE_19                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | 0x13u)
00108 #define EXTI_LINE_20                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | 0x14u)
00109 #define EXTI_LINE_21                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | 0x15u)
00110 #define EXTI_LINE_22                        (EXTI_DIRECT   |              EXTI_REG1 | 0x16u)
00111 #define EXTI_LINE_23                        (EXTI_DIRECT   |              EXTI_REG1 | 0x17u)
00112 #define EXTI_LINE_24                        (EXTI_DIRECT   |              EXTI_REG1 | 0x18u)
00113 #define EXTI_LINE_25                        (EXTI_DIRECT   |              EXTI_REG1 | 0x19u)
00114 #define EXTI_LINE_26                        (EXTI_RESERVED |              EXTI_REG1 | 0x1Au)
00115 #define EXTI_LINE_27                        (EXTI_RESERVED |              EXTI_REG1 | 0x1Bu)
00116 #define EXTI_LINE_28                        (EXTI_DIRECT   |              EXTI_REG1 | 0x1Cu)
00117 #define EXTI_LINE_29                        (EXTI_DIRECT   |              EXTI_REG1 | 0x1Du)
00118 #define EXTI_LINE_30                        (EXTI_DIRECT   |              EXTI_REG1 | 0x1Eu)
00119 #define EXTI_LINE_31                        (EXTI_CONFIG   |              EXTI_REG1 | 0x1Fu)
00120 #define EXTI_LINE_32                        (EXTI_RESERVED |              EXTI_REG2 | 0x00u)
00121 #define EXTI_LINE_33                        (EXTI_CONFIG   |              EXTI_REG2 | 0x01u)
00122 #define EXTI_LINE_34                        (EXTI_RESERVED |              EXTI_REG2 | 0x02u)
00123 #define EXTI_LINE_35                        (EXTI_RESERVED |              EXTI_REG2 | 0x03u)
00124 #define EXTI_LINE_36                        (EXTI_DIRECT   |              EXTI_REG2 | 0x04u)
00125 #define EXTI_LINE_37                        (EXTI_DIRECT   |              EXTI_REG2 | 0x05u)
00126 #define EXTI_LINE_38                        (EXTI_DIRECT   |              EXTI_REG2 | 0x06u)
00127 #define EXTI_LINE_39                        (EXTI_DIRECT   |              EXTI_REG2 | 0x07u)
00128 #define EXTI_LINE_40                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG2 | 0x08u)
00129 #define EXTI_LINE_41                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG2 | 0x09u)
00130 #define EXTI_LINE_42                        (EXTI_DIRECT   |              EXTI_REG2 | 0x0Au)
00131 #if defined (STM32WB55xx)
00132 #define EXTI_LINE_43                        (EXTI_DIRECT   |              EXTI_REG2 | 0x0Bu)
00133 #else
00134 #define EXTI_LINE_43                        (EXTI_RESERVED |              EXTI_REG2 | 0x0Bu)
00135 #endif
00136 #define EXTI_LINE_44                        (EXTI_DIRECT   |              EXTI_REG2 | 0x0Cu)
00137 #define EXTI_LINE_45                        (EXTI_DIRECT   |              EXTI_REG2 | 0x0Du)
00138 #define EXTI_LINE_46                        (EXTI_DIRECT   |              EXTI_REG2 | 0x0Eu)
00139 #define EXTI_LINE_47                        (EXTI_RESERVED |              EXTI_REG2 | 0x0Fu)
00140 #define EXTI_LINE_48                        (EXTI_DIRECT   |              EXTI_REG2 | 0x10u)
00141 /**
00142   * @}
00143   */
00144
00145 /** @defgroup EXTI_Mode  EXTI Mode
00146   * @{
00147   */
00148 #define EXTI_MODE_NONE                      0x00000000u
00149 #define EXTI_MODE_INTERRUPT                 0x00000001u
00150 #define EXTI_MODE_EVENT                     0x00000002u
00151 /**
00152   * @}
00153   */
00154
00155 /** @defgroup EXTI_Trigger  EXTI Trigger
00156   * @{
00157   */
00158 #define EXTI_TRIGGER_NONE                   0x00000000u
00159 #define EXTI_TRIGGER_RISING                 0x00000001u
00160 #define EXTI_TRIGGER_FALLING                0x00000002u
00161 #define EXTI_TRIGGER_RISING_FALLING         (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
00162 /**
00163   * @}
00164   */
00165
00166 /** @defgroup EXTI_GPIOSel  EXTI GPIOSel
00167   * @brief
00168   * @{
00169   */
00170 #define EXTI_GPIOA                          0x00000000u
00171 #define EXTI_GPIOB                          0x00000001u
00172 #define EXTI_GPIOC                          0x00000002u
00173 #if defined (STM32WB55xx)
00174 #define EXTI_GPIOD                          0x00000003u
00175 #endif
00176 #define EXTI_GPIOE                          0x00000004u
00177 #define EXTI_GPIOH                          0x00000007u
00178 /**
00179   * @}
00180   */
00181
00182 /**
00183   * @}
00184   */
00185
00186 /* Exported macro ------------------------------------------------------------*/
00187 /** @defgroup EXTI_Exported_Macros EXTI Exported Macros
00188   * @{
00189   */
00190
00191 /**
00192   * @}
00193   */
00194
00195 /* Private constants --------------------------------------------------------*/
00196 /** @defgroup EXTI_Private_Constants EXTI Private Constants
00197   * @{
00198   */
00199 /**
00200   * @brief  EXTI Line property definition
00201   */
00202 #define EXTI_PROPERTY_SHIFT                 24u
00203 #define EXTI_DIRECT                         (0x01uL << EXTI_PROPERTY_SHIFT)
00204 #define EXTI_CONFIG                         (0x02uL << EXTI_PROPERTY_SHIFT)
00205 #define EXTI_GPIO                           ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
00206 #define EXTI_RESERVED                       (0x08uL << EXTI_PROPERTY_SHIFT)
00207 #define EXTI_PROPERTY_MASK                  (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
00208
00209 /**
00210   * @brief  EXTI Event presence definition
00211   */
00212 #define EXTI_EVENT_PRESENCE_SHIFT           28u
00213 #define EXTI_EVENT                          (0x01uL << EXTI_EVENT_PRESENCE_SHIFT)
00214 #define EXTI_EVENT_PRESENCE_MASK            (EXTI_EVENT)
00215
00216 /**
00217   * @brief  EXTI Register and bit usage
00218   */
00219 #define EXTI_REG_SHIFT                      16u
00220 #define EXTI_REG1                           (0x00uL << EXTI_REG_SHIFT)
00221 #define EXTI_REG2                           (0x01uL << EXTI_REG_SHIFT)
00222 #define EXTI_REG_MASK                       (EXTI_REG1 | EXTI_REG2)
00223 #define EXTI_PIN_MASK                       0x0000001Fu
00224
00225 /**
00226   * @brief  EXTI Mask for interrupt & event mode
00227   */
00228 #define EXTI_MODE_MASK                      (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
00229
00230 /**
00231   * @brief  EXTI Mask for trigger possibilities
00232   */
00233 #define EXTI_TRIGGER_MASK                   (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
00234
00235 /**
00236   * @brief  EXTI Line number
00237   */
00238 #define EXTI_LINE_NB                        49uL
00239
00240 /**
00241   * @}
00242   */
00243
00244 /* Private macros ------------------------------------------------------------*/
00245 /** @defgroup EXTI_Private_Macros EXTI Private Macros
00246   * @{
00247   */
00248 #define IS_EXTI_LINE(__LINE__)          ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \
00249                                         ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT)   || \
00250                                          (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG)   || \
00251                                          (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO))    && \
00252                                          (((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK))      < \
00253                                          (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))))
00254
00255 #define IS_EXTI_MODE(__LINE__)          ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \
00256                                          (((__LINE__) & ~EXTI_MODE_MASK) == 0x00u))
00257
00258 #define IS_EXTI_TRIGGER(__LINE__)       (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
00259
00260 #define IS_EXTI_PENDING_EDGE(__LINE__)  ((__LINE__) == EXTI_TRIGGER_RISING_FALLING)
00261
00262 #define IS_EXTI_CONFIG_LINE(__LINE__)   (((__LINE__) & EXTI_CONFIG) != 0x00u)
00263
00264 #if defined (STM32WB55xx)
00265 #define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
00266                                          ((__PORT__) == EXTI_GPIOB) || \
00267                                          ((__PORT__) == EXTI_GPIOC) || \
00268                                          ((__PORT__) == EXTI_GPIOD) || \
00269                                          ((__PORT__) == EXTI_GPIOE) || \
00270                                          ((__PORT__) == EXTI_GPIOH))
00271 #else
00272 #define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
00273                                          ((__PORT__) == EXTI_GPIOB) || \
00274                                          ((__PORT__) == EXTI_GPIOC) || \
00275                                          ((__PORT__) == EXTI_GPIOE) || \
00276                                          ((__PORT__) == EXTI_GPIOH))
00277 #endif
00278
00279 #define IS_EXTI_GPIO_PIN(__PIN__)       ((__PIN__) < 16u)
00280
00281 /**
00282   * @}
00283   */
00284
00285
00286 /* Exported functions --------------------------------------------------------*/
00287 /** @defgroup EXTI_Exported_Functions EXTI Exported Functions
00288   * @brief    EXTI Exported Functions
00289   * @{
00290   */
00291
00292 /** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
00293   * @brief    Configuration functions
00294   * @{
00295   */
00296 /* Configuration functions ****************************************************/
00297 HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
00298 HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
00299 HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
00300 HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
00301 HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
00302 /**
00303   * @}
00304   */
00305
00306 /** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
00307   * @brief    IO operation functions
00308   * @{
00309   */
00310 /* IO operation functions *****************************************************/
00311 void              HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
00312 uint32_t          HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
00313 void              HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
00314 void              HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
00315
00316 /**
00317   * @}
00318   */
00319
00320 /**
00321   * @}
00322   */
00323
00324 /**
00325   * @}
00326   */
00327
00328 /**
00329   * @}
00330   */
00331
00332 #ifdef __cplusplus
00333 }
00334 #endif
00335
00336 #endif /* STM32WBxx_HAL_EXTI_H */
00337
00338 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_flash.c Source File

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stm32wbxx_hal_flash.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_flash.c
00004   * @author  MCD Application Team
00005   * @brief   FLASH HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the internal FLASH memory:
00008   *           + Program operations functions
00009   *           + Memory Control functions
00010   *           + Peripheral Errors functions
00011   *
00012  @verbatim
00013   ==============================================================================
00014                         ##### FLASH peripheral features #####
00015   ==============================================================================
00016
00017   [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
00018        to the Flash memory. It implements the erase and program Flash memory operations
00019        and the read and write protection mechanisms.
00020
00021   [..] The Flash memory interface accelerates code execution with a system of instruction
00022        prefetch and cache lines.
00023
00024   [..] The FLASH main features are:
00025       (+) Flash memory read operations
00026       (+) Flash memory program/erase operations
00027       (+) Program and Erase suspension
00028       (+) Read / write protections (2 areas per features)
00029       (+) CPU2 Security area
00030       (+) Option bytes programming
00031       (+) Prefetch on CPU1 I-Code and CPU2 S-bus
00032       (+) 32 instruction cache lines of 4*64 bits on I-Code for CPU1
00033       (+) 8 data cache lines of 4*64 bits on D-Code for CPU1
00034       (+) 4 instruction cache lines of 1*64 bits on S-bus for CPU2
00035       (+) 4 data cache lines of 1*64 bits on S-Bus for CPU2
00036       (+) Error code correction (ECC) : Data in flash are 72-bits word
00037           (8 bits added per double word)
00038
00039                         ##### How to use this driver #####
00040  ==============================================================================
00041     [..]
00042       This driver provides functions and macros to configure and program the FLASH
00043       memory of all STM32WBxx devices.
00044
00045       (#) Flash Memory IO Programming functions:
00046            (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
00047                 HAL_FLASH_Lock() functions
00048            (++) Program functions: double word and fast program (full row programming)
00049            (++) There are two modes of programming:
00050             (+++) Polling mode using HAL_FLASH_Program() function
00051             (+++) Interrupt mode using HAL_FLASH_Program_IT() function
00052
00053       (#) Interrupts and flags management functions:
00054            (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
00055            (++) Callback functions are called when the flash operations are finished :
00056                 HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise
00057                 HAL_FLASH_OperationErrorCallback()
00058            (++) Get error flag status by calling HAL_GetError()
00059
00060       (#) Option bytes management functions :
00061            (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and
00062                 HAL_FLASH_OB_Lock() functions
00063            (++) Launch the reload of the option bytes using HAL_FLASH_OB_Launch() function.
00064                 In this case, a reset is generated
00065
00066     [..]
00067       In addition to these functions, this driver includes a set of macros allowing
00068       to handle the following operations:
00069        (+) Set the latency
00070        (+) Enable/Disable the prefetch buffer
00071        (+) Enable/Disable the suspend program or erase request
00072        (+) Enable/Disable the Instruction cache and the Data cache
00073        (+) Reset the Instruction cache and the Data cache
00074        (+) Enable/Disable the Flash interrupts
00075        (+) Monitor the Flash flags status
00076
00077  @endverbatim
00078   ******************************************************************************
00079   * @attention
00080   *
00081   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00082   * All rights reserved.</center></h2>
00083   *
00084   * This software component is licensed by ST under BSD 3-Clause license,
00085   * the "License"; You may not use this file except in compliance with the
00086   * License. You may obtain a copy of the License at:
00087   *                        opensource.org/licenses/BSD-3-Clause
00088   *
00089   ******************************************************************************
00090   */
00091
00092 /* Includes ------------------------------------------------------------------*/
00093 #include "stm32wbxx_hal.h"
00094
00095 /** @addtogroup STM32WBxx_HAL_Driver
00096   * @{
00097   */
00098
00099 /** @defgroup FLASH FLASH
00100   * @brief FLASH HAL module driver
00101   * @{
00102   */
00103
00104 #ifdef HAL_FLASH_MODULE_ENABLED
00105
00106 /* Private typedef -----------------------------------------------------------*/
00107 /* Private defines -----------------------------------------------------------*/
00108 /** @addtogroup FLASH_Private_Constants
00109   * @{
00110   */
00111 #define FLASH_NB_DOUBLE_WORDS_IN_ROW  64
00112 /**
00113   * @}
00114   */
00115
00116 /* Private macros ------------------------------------------------------------*/
00117 /* Private variables ---------------------------------------------------------*/
00118 /** @defgroup FLASH_Private_Variables FLASH Private Variables
00119  * @{
00120  */
00121 /**
00122   * @brief  Variable used for Program/Erase sectors under interruption
00123   */
00124 FLASH_ProcessTypeDef pFlash = {.Lock = HAL_UNLOCKED, \
00125                                .ErrorCode = HAL_FLASH_ERROR_NONE, \
00126                                .ProcedureOnGoing = 0U, \
00127                                .Address = 0U, \
00128                                .Page = 0U, \
00129                                .NbPagesToErase = 0U
00130                               };
00131 /**
00132   * @}
00133   */
00134
00135 /* Private function prototypes -----------------------------------------------*/
00136 /** @defgroup FLASH_Private_Functions FLASH Private Functions
00137  * @{
00138  */
00139 static void          FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);
00140 static void          FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress);
00141 /**
00142   * @}
00143   */
00144
00145 /* Exported functions --------------------------------------------------------*/
00146 /** @defgroup FLASH_Exported_Functions FLASH Exported Functions
00147   * @{
00148   */
00149
00150 /** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
00151  *  @brief   Programming operation functions
00152  *
00153 @verbatim
00154  ===============================================================================
00155                   ##### Programming operation functions #####
00156  ===============================================================================
00157     [..]
00158     This subsection provides a set of functions allowing to manage the FLASH
00159     program operations.
00160
00161 @endverbatim
00162   * @{
00163   */
00164
00165 /**
00166   * @brief  Program double word or fast program of a row at a specified address.
00167   * @note   Before any operation, it is possible to check there is no operation suspended
00168   *         by call HAL_FLASHEx_IsOperationSuspended()
00169   * @param  TypeProgram Indicate the way to program at a specified address
00170   *                       This parameter can be a value of @ref FLASH_TYPE_PROGRAM
00171   * @param  Address Specifies the address to be programmed.
00172   * @param  Data Specifies the data to be programmed
00173   *                This parameter is the data for the double word program and the address where
00174   *                are stored the data for the row fast program.
00175   *
00176   * @retval HAL_StatusTypeDef HAL Status
00177   */
00178 HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
00179 {
00180   HAL_StatusTypeDef status;
00181
00182   /* Check the parameters */
00183   assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
00184   assert_param(IS_ADDR_ALIGNED_64BITS(Address));
00185   assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
00186
00187   /* Process Locked */
00188   __HAL_LOCK(&pFlash);
00189
00190   /* Reset error code */
00191   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00192
00193   /* Verify that next operation can be proceed */
00194   status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
00195
00196   if (status == HAL_OK)
00197   {
00198     if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)
00199     {
00200       /* Check the parameters */
00201       assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
00202
00203       /* Program double-word (64-bit) at a specified address */
00204       FLASH_Program_DoubleWord(Address, Data);
00205     }
00206     else
00207     {
00208       /* Check the parameters */
00209       assert_param(IS_FLASH_FAST_PROGRAM_ADDRESS(Address));
00210
00211       /* Fast program a 64 row double-word (64-bit) at a specified address */
00212       FLASH_Program_Fast(Address, (uint32_t)Data);
00213     }
00214
00215     /* Wait for last operation to be completed */
00216     status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
00217
00218     /* If the program operation is completed, disable the PG or FSTPG Bit */
00219     CLEAR_BIT(FLASH->CR, TypeProgram);
00220   }
00221
00222   /* Process Unlocked */
00223   __HAL_UNLOCK(&pFlash);
00224
00225   /* return status */
00226   return status;
00227 }
00228
00229 /**
00230   * @brief  Program double word or fast program of a row at a specified address with interrupt enabled.
00231   * @note   Before any operation, it is possible to check there is no operation suspended
00232   *         by call HAL_FLASHEx_IsOperationSuspended()
00233   * @param  TypeProgram Indicate the way to program at a specified address.
00234   *                           This parameter can be a value of @ref FLASH_TYPE_PROGRAM
00235   * @param  Address Specifies the address to be programmed.
00236   * @param  Data Specifies the data to be programmed
00237   *                This parameter is the data for the double word program and the address where
00238   *                are stored the data for the row fast program.
00239   *
00240   * @retval HAL Status
00241   */
00242 HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
00243 {
00244   HAL_StatusTypeDef status;
00245
00246   /* Check the parameters */
00247   assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
00248   assert_param(IS_ADDR_ALIGNED_64BITS(Address));
00249   assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
00250
00251   /* Process Locked */
00252   __HAL_LOCK(&pFlash);
00253
00254   /* Reset error code */
00255   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00256
00257   /* Verify that next operation can be proceed */
00258   status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
00259
00260   if (status != HAL_OK)
00261   {
00262     /* Process Unlocked */
00263     __HAL_UNLOCK(&pFlash);
00264   }
00265   else
00266   {
00267     /* Set internal variables used by the IRQ handler */
00268     pFlash.ProcedureOnGoing = TypeProgram;
00269     pFlash.Address = Address;
00270
00271     /* Enable End of Operation and Error interrupts */
00272     __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
00273
00274     if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)
00275     {
00276       /* Check the parameters */
00277       assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
00278
00279       /* Program double-word (64-bit) at a specified address */
00280       FLASH_Program_DoubleWord(Address, Data);
00281     }
00282     else
00283     {
00284       /* Check the parameters */
00285       assert_param(IS_FLASH_FAST_PROGRAM_ADDRESS(Address));
00286
00287       /* Fast program a 64 row double-word (64-bit) at a specified address */
00288       FLASH_Program_Fast(Address, (uint32_t)Data);
00289     }
00290   }
00291
00292   /* return status */
00293   return status;
00294 }
00295
00296 /**
00297   * @brief Handle FLASH interrupt request.
00298   * @retval None
00299   */
00300 void HAL_FLASH_IRQHandler(void)
00301 {
00302   uint32_t param = 0xFFFFFFFFU;
00303   uint32_t error;
00304
00305   /* Check FLASH operation error flags */
00306   error = (FLASH->SR & FLASH_FLAG_SR_ERRORS);
00307
00308   /* Clear Current operation */
00309   CLEAR_BIT(FLASH->CR, pFlash.ProcedureOnGoing);
00310
00311   /* A] Set parameter for user or error callbacks */
00312   /* check operation was a program or erase */
00313   if ((pFlash.ProcedureOnGoing & (FLASH_TYPEPROGRAM_DOUBLEWORD | FLASH_TYPEPROGRAM_FAST)) != 0U)
00314   {
00315     /* return adress being programmed */
00316     param = pFlash.Address;
00317   }
00318   else if ((pFlash.ProcedureOnGoing & (FLASH_TYPEERASE_MASSERASE | FLASH_TYPEERASE_PAGES)) != 0U)
00319   {
00320     /* return page number being erased (0 for mass erase) */
00321     param = pFlash.Page;
00322   }
00323   else
00324   {
00325     /* No Procedure on-going */
00326     /* Nothing to do, but check error if any */
00327   }
00328
00329   /* B] Check errors */
00330   if (error != 0U)
00331   {
00332     /*Save the error code*/
00333     pFlash.ErrorCode |= error;
00334
00335     /* clear error flags */
00336     __HAL_FLASH_CLEAR_FLAG(error);
00337
00338     /*Stop the procedure ongoing*/
00339     pFlash.ProcedureOnGoing = FLASH_TYPENONE;
00340
00341     /* Error callback */
00342     HAL_FLASH_OperationErrorCallback(param);
00343   }
00344
00345   /* C] Check FLASH End of Operation flag */
00346   if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
00347   {
00348     /* Clear FLASH End of Operation pending bit */
00349     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
00350
00351     if (pFlash.ProcedureOnGoing == FLASH_TYPEERASE_PAGES)
00352     {
00353       /* Nb of pages to erased can be decreased */
00354       pFlash.NbPagesToErase--;
00355
00356       /* Check if there are still pages to erase*/
00357       if (pFlash.NbPagesToErase != 0U)
00358       {
00359         /* Increment page number */
00360         pFlash.Page++;
00361         FLASH_PageErase(pFlash.Page);
00362       }
00363       else
00364       {
00365         /* No more pages to erase: stop erase pages procedure */
00366         pFlash.ProcedureOnGoing = FLASH_TYPENONE;
00367       }
00368     }
00369     else
00370     {
00371       /*Stop the ongoing procedure */
00372       pFlash.ProcedureOnGoing = FLASH_TYPENONE;
00373     }
00374
00375     /* User callback */
00376     HAL_FLASH_EndOfOperationCallback(param);
00377   }
00378
00379   if (pFlash.ProcedureOnGoing == FLASH_TYPENONE)
00380   {
00381     /* Disable End of Operation and Error interrupts */
00382     __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
00383
00384     /* Process Unlocked */
00385     __HAL_UNLOCK(&pFlash);
00386   }
00387 }
00388
00389 /**
00390   * @brief  FLASH end of operation interrupt callback.
00391   * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
00392   *                  Mass Erase: 0
00393   *                  Page Erase: Page which has been erased
00394   *                  Program: Address which was selected for data program
00395   * @retval None
00396   */
00397 __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
00398 {
00399   /* Prevent unused argument(s) compilation warning */
00400   UNUSED(ReturnValue);
00401
00402   /* NOTE : This function should not be modified, when the callback is needed,
00403             the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
00404    */
00405 }
00406
00407 /**
00408   * @brief  FLASH operation error interrupt callback.
00409   * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
00410   *                 Mass Erase: 0
00411   *                 Page Erase: Page number which returned an error
00412   *                 Program: Address which was selected for data program
00413   * @retval None
00414   */
00415 __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
00416 {
00417   /* Prevent unused argument(s) compilation warning */
00418   UNUSED(ReturnValue);
00419
00420   /* NOTE : This function should not be modified, when the callback is needed,
00421             the HAL_FLASH_OperationErrorCallback could be implemented in the user file
00422    */
00423 }
00424
00425 /**
00426   * @}
00427   */
00428
00429 /** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
00430  *  @brief   Management functions
00431  *
00432 @verbatim
00433  ===============================================================================
00434                       ##### Peripheral Control functions #####
00435  ===============================================================================
00436     [..]
00437     This subsection provides a set of functions allowing to control the FLASH
00438     memory operations.
00439
00440 @endverbatim
00441   * @{
00442   */
00443
00444 /**
00445   * @brief  Unlock the FLASH control register access.
00446   * @retval HAL Status
00447   */
00448 HAL_StatusTypeDef HAL_FLASH_Unlock(void)
00449 {
00450   HAL_StatusTypeDef status = HAL_OK;
00451
00452   if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U)
00453   {
00454     /* Authorize the FLASH Registers access */
00455     WRITE_REG(FLASH->KEYR, FLASH_KEY1);
00456     WRITE_REG(FLASH->KEYR, FLASH_KEY2);
00457
00458     /* verify Flash is unlock */
00459     if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U)
00460     {
00461       status = HAL_ERROR;
00462     }
00463   }
00464
00465   return status;
00466 }
00467
00468 /**
00469   * @brief  Lock the FLASH control register access.
00470   * @retval HAL Status
00471   */
00472 HAL_StatusTypeDef HAL_FLASH_Lock(void)
00473 {
00474   HAL_StatusTypeDef status = HAL_OK;
00475
00476   /* Set the LOCK Bit to lock the FLASH Registers access */
00477   /* @Note  The lock and unlock procedure is done only using CR registers even from CPU2 */
00478   SET_BIT(FLASH->CR, FLASH_CR_LOCK);
00479
00480   /* verify Flash is locked */
00481   if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) == 0U)
00482   {
00483     status = HAL_ERROR;
00484   }
00485
00486   return status;
00487 }
00488
00489 /**
00490   * @brief  Unlock the FLASH Option Bytes Registers access.
00491   * @retval HAL Status
00492   */
00493 HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
00494 {
00495   HAL_StatusTypeDef status = HAL_ERROR;
00496
00497   /* @Note The lock and unlock procedure is done only using CR registers even from CPU2 */
00498   if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0U)
00499   {
00500     /* Authorizes the Option Byte register programming */
00501     WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
00502     WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
00503
00504     /* verify option bytes are unlocked */
00505     if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) == 0U)
00506     {
00507       status = HAL_OK;
00508     }
00509   }
00510
00511   return status;
00512 }
00513
00514 /**
00515   * @brief  Lock the FLASH Option Bytes Registers access.
00516   * @retval HAL Status
00517   */
00518 HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
00519 {
00520   HAL_StatusTypeDef status = HAL_OK;
00521
00522   /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
00523   /* @Note The lock and unlock procedure is done only using CR registers even from CPU2 */
00524   SET_BIT(FLASH->CR, FLASH_CR_OPTLOCK);
00525
00526   /* verify option bytes are lock */
00527   if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) == 0U)
00528   {
00529     status = HAL_ERROR;
00530   }
00531
00532   return status;
00533 }
00534
00535 /**
00536   * @brief  Launch the option byte loading.
00537   * @retval HAL Status
00538   */
00539 HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
00540 {
00541   /* Set the bit to force the option byte reloading */
00542   /* The OB launch is done from the same register either from CPU1 or CPU2 */
00543   SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
00544
00545   /* We should not reach here : Option byte launch generates Option byte reset
00546      so return error */
00547   return HAL_ERROR;
00548 }
00549
00550 /**
00551   * @}
00552   */
00553
00554 /** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
00555  *  @brief   Peripheral Errors functions
00556  *
00557 @verbatim
00558  ===============================================================================
00559                 ##### Peripheral Errors functions #####
00560  ===============================================================================
00561     [..]
00562     This subsection permits to get in run-time Errors of the FLASH peripheral.
00563
00564 @endverbatim
00565   * @{
00566   */
00567
00568 /**
00569   * @brief  Get the specific FLASH error flag.
00570   * @retval FLASH_ErrorCode The returned value can be
00571   *            @arg @ref HAL_FLASH_ERROR_NONE No error set
00572   *            @arg @ref HAL_FLASH_ERROR_OP FLASH Operation error
00573   *            @arg @ref HAL_FLASH_ERROR_PROG FLASH Programming error
00574   *            @arg @ref HAL_FLASH_ERROR_WRP FLASH Write protection error
00575   *            @arg @ref HAL_FLASH_ERROR_PGA FLASH Programming alignment error
00576   *            @arg @ref HAL_FLASH_ERROR_SIZ FLASH Size error
00577   *            @arg @ref HAL_FLASH_ERROR_PGS FLASH Programming sequence error
00578   *            @arg @ref HAL_FLASH_ERROR_MIS FLASH Fast programming data miss error
00579   *            @arg @ref HAL_FLASH_ERROR_FAST FLASH Fast programming error
00580   *            @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error (PCROP)
00581   *            @arg @ref HAL_FLASH_ERROR_OPTV FLASH Option validity error
00582   */
00583 uint32_t HAL_FLASH_GetError(void)
00584 {
00585   return pFlash.ErrorCode;
00586 }
00587
00588 /**
00589   * @}
00590   */
00591
00592 /**
00593   * @}
00594   */
00595
00596 /* Private functions ---------------------------------------------------------*/
00597
00598 /** @addtogroup FLASH_Private_Functions
00599   * @{
00600   */
00601
00602 /**
00603   * @brief  Wait for a FLASH operation to complete.
00604   * @param  Timeout Maximum flash operation timeout
00605   * @retval HAL_StatusTypeDef HAL Status
00606   */
00607 HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
00608 {
00609   uint32_t error;
00610   uint32_t tickstart = HAL_GetTick();
00611
00612   /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
00613      Even if the FLASH operation fails, the BUSY flag will be reset and an error
00614      flag will be set */
00615   while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
00616   {
00617     if ((HAL_GetTick() - tickstart) >= Timeout)
00618     {
00619       return HAL_TIMEOUT;
00620     }
00621   }
00622
00623   /* Check FLASH operation error flags */
00624   error = FLASH->SR;
00625
00626   /* Check FLASH End of Operation flag */
00627   if ((error & FLASH_FLAG_EOP) != 0U)
00628   {
00629     /* Clear FLASH End of Operation pending bit */
00630     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
00631   }
00632
00633   /* Now update error variable to only error value */
00634   error &= FLASH_FLAG_SR_ERRORS;
00635
00636   /* clear error flags */
00637   __HAL_FLASH_CLEAR_FLAG(error);
00638
00639   if (error != 0U)
00640   {
00641     /*Save the error code*/
00642     pFlash.ErrorCode = error;
00643
00644     return HAL_ERROR;
00645   }
00646
00647   /* Wait for control register to be written */
00648   while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_CFGBSY))
00649   {
00650     if ((HAL_GetTick() - tickstart) >= Timeout)
00651     {
00652       return HAL_TIMEOUT;
00653     }
00654   }
00655
00656   return HAL_OK;
00657 }
00658
00659 /**
00660   * @brief  Program double-word (64-bit) at a specified address.
00661   * @param  Address Specifies the address to be programmed.
00662   * @param  Data Specifies the data to be programmed.
00663   * @retval None
00664   */
00665 static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
00666 {
00667   /* Set PG bit */
00668   SET_BIT(FLASH->CR, FLASH_CR_PG);
00669
00670   /* Program first word */
00671   *(uint32_t *)Address = (uint32_t)Data;
00672
00673   /* Barrier to ensure programming is performed in 2 steps, in right order
00674     (independently of compiler optimization behavior) */
00675   __ISB();
00676
00677   /* Program second word */
00678   *(uint32_t *)(Address + 4U) = (uint32_t)(Data >> 32U);
00679 }
00680
00681 /**
00682   * @brief  Fast program a 32 row double-word (64-bit) at a specified address.
00683   * @param  Address Specifies the address to be programmed.
00684   * @param  DataAddress Specifies the address where the data are stored.
00685   * @retval None
00686   */
00687 static __RAM_FUNC void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress)
00688 {
00689   uint8_t row_index = (2 * FLASH_NB_DOUBLE_WORDS_IN_ROW);
00690   __IO uint32_t *dest_addr = (__IO uint32_t *)Address;
00691   __IO uint32_t *src_addr = (__IO uint32_t *)DataAddress;
00692   uint32_t primask_bit;
00693
00694   /* Set FSTPG bit */
00695   SET_BIT(FLASH->CR, FLASH_CR_FSTPG);
00696
00697   /* Enter critical section: row programming should not be longer than 7 ms */
00698   primask_bit = __get_PRIMASK();
00699   __disable_irq();
00700
00701   /* Program the double word of the row */
00702   do
00703   {
00704     *dest_addr = *src_addr;
00705     dest_addr++;
00706     src_addr++;
00707     row_index--;
00708   }
00709   while (row_index != 0U);
00710
00711   /* wait for BSY in order to be sure that flash operation is ended before
00712      allowing prefetch in flash. Timeout does not return status, as it will
00713      be anyway done later */
00714   while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != 0U)
00715   {
00716   }
00717
00718   /* Exit critical section: restore previous priority mask */
00719   __set_PRIMASK(primask_bit);
00720 }
00721
00722 /**
00723   * @}
00724   */
00725
00726 #endif /* HAL_FLASH_MODULE_ENABLED */
00727
00728 /**
00729   * @}
00730   */
00731
00732 /**
00733   * @}
00734   */
00735
00736 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_flash.h Source File

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stm32wbxx_hal_flash.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_flash.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of FLASH HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_FLASH_H
00022 #define STM32WBxx_HAL_FLASH_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 /** @addtogroup STM32WBxx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup FLASH
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup FLASH_Exported_Types FLASH Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief  FLASH Erase structure definition
00046   */
00047 typedef struct
00048 {
00049   uint32_t TypeErase;   /*!< Mass erase or page erase.
00050                              This parameter can be a value of @ref FLASH_TYPE_ERASE */
00051   uint32_t Page;        /*!< Initial Flash page to erase when page erase is enabled
00052                              This parameter must be a value between 0 and (FLASH_PAGE_NB - 1) */
00053   uint32_t NbPages;     /*!< Number of pages to be erased.
00054                              This parameter must be a value between 1 and (FLASH_PAGE_NB - value of initial page)*/
00055 } FLASH_EraseInitTypeDef;
00056
00057 /**
00058   * @brief  FLASH Option Bytes Program structure definition
00059   */
00060 typedef struct
00061 {
00062   uint32_t OptionType;             /*!< Option byte to be configured.
00063                                         This parameter can be a combination of the values of @ref FLASH_OB_TYPE */
00064   uint32_t WRPArea;                 /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP).
00065                                         Only one WRP area could be programmed at the same time.
00066                                         This parameter can be value of @ref FLASH_OB_WRP_AREA */
00067   uint32_t WRPStartOffset;         /*!< Write protection start offset (used for OPTIONBYTE_WRP).
00068                                         This parameter must be a value between 0 and (max number of pages - 1) */
00069   uint32_t WRPEndOffset;           /*!< Write protection end offset (used for OPTIONBYTE_WRP).
00070                                         This parameter must be a value between WRPStartOffset and (max number of pages - 1) */
00071   uint32_t RDPLevel;               /*!< Set the read protection level (used for OPTIONBYTE_RDP).
00072                                         This parameter can be a value of @ref FLASH_OB_READ_PROTECTION */
00073   uint32_t UserType;               /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).
00074                                         This parameter can be a combination of @ref FLASH_OB_USER_TYPE */
00075   uint32_t UserConfig;             /*!< Value of the user option byte (used for OPTIONBYTE_USER).
00076                                         This parameter can be a combination of the values of
00077                                             @ref FLASH_OB_USER_AGC_TRIM, @ref FLASH_OB_USER_BOR_LEVEL
00078                                             @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
00079                                             @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW,
00080                                             @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY,
00081                                             @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_nBOOT1,
00082                                             @ref FLASH_OB_USER_SRAM2PE, @ref FLASH_OB_USER_SRAM2RST,
00083                                             @ref FLASH_OB_USER_nSWBOOT0, @ref FLASH_OB_USER_nBOOT0 */
00084   uint32_t PCROPConfig;            /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP).
00085                                         This parameter must be a combination of values of @ref FLASH_OB_PCROP_ZONE
00086                                         and @ref FLASH_OB_PCROP_RDP */
00087   uint32_t PCROP1AStartAddr;       /*!< PCROP Zone A Start address (used for OPTIONBYTE_PCROP). It represents first address of start block
00088                                         to protect. Make sure this parameter is multiple of PCROP granularity */
00089   uint32_t PCROP1AEndAddr;         /*!< PCROP Zone A End address (used for OPTIONBYTE_PCROP). It represents first address of end block
00090                                         to protect. Make sure this parameter is multiple of PCROP granularity */
00091   uint32_t PCROP1BStartAddr;       /*!< PCROP Zone B Start address (used for OPTIONBYTE_PCROP). It represents first address of start block
00092                                         to protect. Make sure this parameter is multiple of PCROP granularity */
00093   uint32_t PCROP1BEndAddr;         /*!< PCROP Zone B End address (used for OPTIONBYTE_PCROP). It represents first address of end block
00094                                         to protect. Make sure this parameter is multiple of PCROP granularity */
00095   uint32_t SecureFlashStartAddr;   /*!< Secure Flash start address (used for OPTIONBYTE_SECURE_MODE).
00096                                         This parameter must be a value between begin and end of Flash bank
00097                                         => Contains the start address of the first 4kB page of the secure Flash area */
00098   uint32_t SecureRAM2aStartAddr;   /*!< Secure Backup RAM2a start address (used for OPTIONBYTE_SECURE_MODE).
00099                                         This parameter can be a value of @ref FLASH_SRAM2A_ADDRESS_RANGE */
00100   uint32_t SecureRAM2bStartAddr;   /*!< Secure non-Backup RAM2b start address (used for OPTIONBYTE_SECURE_MODE)
00101                                         This parameter can be a value of @ref FLASH_SRAM2B_ADDRESS_RANGE */
00102   uint32_t SecureMode;             /*!< Secure mode activated or desactivated.
00103                                         This parameter can be a value of @ref FLASH_OB_SECURITY_MODE */
00104   uint32_t C2BootRegion;           /*!< CPU2 Secure Boot memory region(used for OPTIONBYTE_C2_BOOT_VECT).
00105                                         This parameter can be a value of @ref C2_FLASH_OB_BOOT_REGION */
00106   uint32_t C2SecureBootVectAddr;   /*!< CPU2 Secure Boot reset vector (used for OPTIONBYTE_C2_BOOT_VECT).
00107                                         This parameter contains the CPU2 boot reset start address within
00108                                         the selected memory region. Make sure this parameter is word aligned. */
00109   uint32_t IPCCdataBufAddr;        /*!< IPCC mailbox data buffer base address (used for OPTIONBYTE_IPCC_BUF_ADDR).
00110                                         This parameter contains the IPCC mailbox data buffer start address area in SRAM2.
00111                                         Make sure this parameter is double-word aligned.  */
00112 } FLASH_OBProgramInitTypeDef;
00113
00114 /**
00115 * @brief  FLASH handle Structure definition
00116 */
00117 typedef struct
00118 {
00119   HAL_LockTypeDef   Lock;              /* FLASH locking object */
00120   uint32_t          ErrorCode;         /* FLASH error code */
00121   uint32_t          ProcedureOnGoing;  /* Internal variable to indicate which procedure is ongoing or not in IT context */
00122   uint32_t          Address;           /* Internal variable to save address selected for program in IT context */
00123   uint32_t          Page;              /* Internal variable to define the current page which is erasing in IT context */
00124   uint32_t          NbPagesToErase;    /* Internal variable to save the remaining pages to erase in IT context */
00125 } FLASH_ProcessTypeDef;
00126
00127 /**
00128   * @}
00129   */
00130
00131 /* Exported constants --------------------------------------------------------*/
00132 /** @defgroup FLASH_Exported_Constants FLASH Exported Constants
00133   * @{
00134   */
00135
00136 /** @defgroup FLASH_KEYS FLASH Keys
00137   * @{
00138   */
00139 #define FLASH_KEY1                      0x45670123U  /*!< Flash key1 */
00140 #define FLASH_KEY2                      0xCDEF89ABU  /*!< Flash key2: used with FLASH_KEY1
00141                                                           to unlock the FLASH registers access */
00142
00143 #define FLASH_OPTKEY1                   0x08192A3BU  /*!< Flash option byte key1 */
00144 #define FLASH_OPTKEY2                   0x4C5D6E7FU  /*!< Flash option byte key2: used with FLASH_OPTKEY1
00145                                                         to allow option bytes operations */
00146 /**
00147   * @}
00148   */
00149
00150 /** @defgroup FLASH_LATENCY FLASH Latency
00151   * @{
00152   */
00153 #define FLASH_LATENCY_0                 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state   */
00154 #define FLASH_LATENCY_1                 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state    */
00155 #define FLASH_LATENCY_2                 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states   */
00156 #define FLASH_LATENCY_3                 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */
00157 /**
00158   * @}
00159   */
00160
00161 /** @defgroup FLASH_FLAGS FLASH Flags Definition
00162   * @{
00163   */
00164 #define FLASH_FLAG_EOP                  FLASH_SR_EOP      /*!< FLASH End of operation flag */
00165 #define FLASH_FLAG_OPERR                FLASH_SR_OPERR    /*!< FLASH Operation error flag */
00166 #define FLASH_FLAG_PROGERR              FLASH_SR_PROGERR  /*!< FLASH Programming error flag */
00167 #define FLASH_FLAG_WRPERR               FLASH_SR_WRPERR   /*!< FLASH Write protection error flag */
00168 #define FLASH_FLAG_PGAERR               FLASH_SR_PGAERR   /*!< FLASH Programming alignment error flag */
00169 #define FLASH_FLAG_SIZERR               FLASH_SR_SIZERR   /*!< FLASH Size error flag  */
00170 #define FLASH_FLAG_PGSERR               FLASH_SR_PGSERR   /*!< FLASH Programming sequence error flag */
00171 #define FLASH_FLAG_MISERR               FLASH_SR_MISERR   /*!< FLASH Fast programming data miss error flag */
00172 #define FLASH_FLAG_FASTERR              FLASH_SR_FASTERR  /*!< FLASH Fast programming error flag */
00173 #define FLASH_FLAG_OPTNV                FLASH_SR_OPTNV    /*!< FLASH User Option OPTVAL indication */
00174 #define FLASH_FLAG_RDERR                FLASH_SR_RDERR    /*!< FLASH PCROP read error flag */
00175 #define FLASH_FLAG_OPTVERR              FLASH_SR_OPTVERR  /*!< FLASH Option validity error flag  */
00176 #define FLASH_FLAG_BSY                  FLASH_SR_BSY      /*!< FLASH Busy flag */
00177 #define FLASH_FLAG_CFGBSY               FLASH_SR_CFGBSY   /*!< FLASH Programming/erase configuration busy */
00178 #define FLASH_FLAG_PESD                 FLASH_SR_PESD     /*!< FLASH Programming/erase operation suspended */
00179 #define FLASH_FLAG_ECCC                 FLASH_ECCR_ECCC   /*!< FLASH ECC correction */
00180 #define FLASH_FLAG_ECCD                 FLASH_ECCR_ECCD   /*!< FLASH ECC detection */
00181
00182 #define FLASH_FLAG_SR_ERRORS            (FLASH_FLAG_OPERR   | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \
00183                                          FLASH_FLAG_PGAERR  | FLASH_FLAG_SIZERR  | FLASH_FLAG_PGSERR | \
00184                                          FLASH_FLAG_MISERR  | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR  | \
00185                                          FLASH_FLAG_OPTVERR)     /*!< All SR error flags */
00186
00187 #define FLASH_FLAG_ECCR_ERRORS          (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)
00188
00189 #define FLASH_FLAG_ALL_ERRORS           (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_ECCR_ERRORS)
00190
00191 /** @defgroup FLASH_INTERRUPT_DEFINITION FLASH Interrupts Definition
00192   * @brief FLASH Interrupt definition
00193   * @{
00194   */
00195 #define FLASH_IT_EOP                    FLASH_CR_EOPIE     /*!< End of FLASH Operation Interrupt source */
00196 #define FLASH_IT_OPERR                  FLASH_CR_ERRIE     /*!< Error Interrupt source */
00197 #define FLASH_IT_RDERR                  FLASH_CR_RDERRIE   /*!< PCROP Read Error Interrupt source */
00198 #define FLASH_IT_ECCC                   (FLASH_ECCR_ECCCIE >> FLASH_ECCR_ECCCIE_Pos)  /*!< ECC Correction Interrupt source */
00199 /**
00200   * @}
00201   */
00202
00203 /** @defgroup FLASH_ERROR FLASH Error
00204   * @{
00205   */
00206 #define HAL_FLASH_ERROR_NONE            0x00000000U
00207 #define HAL_FLASH_ERROR_OP              FLASH_FLAG_OPERR
00208 #define HAL_FLASH_ERROR_PROG            FLASH_FLAG_PROGERR
00209 #define HAL_FLASH_ERROR_WRP             FLASH_FLAG_WRPERR
00210 #define HAL_FLASH_ERROR_PGA             FLASH_FLAG_PGAERR
00211 #define HAL_FLASH_ERROR_SIZ             FLASH_FLAG_SIZERR
00212 #define HAL_FLASH_ERROR_PGS             FLASH_FLAG_PGSERR
00213 #define HAL_FLASH_ERROR_MIS             FLASH_FLAG_MISERR
00214 #define HAL_FLASH_ERROR_FAST            FLASH_FLAG_FASTERR
00215 #define HAL_FLASH_ERROR_RD              FLASH_FLAG_RDERR
00216 #define HAL_FLASH_ERROR_OPTV            FLASH_FLAG_OPTVERR
00217 /**
00218   * @}
00219   */
00220
00221 /** @defgroup FLASH_TYPE_ERASE FLASH Erase Type
00222   * @{
00223   */
00224 #define FLASH_TYPEERASE_PAGES           FLASH_CR_PER  /*!< Pages erase only*/
00225 #define FLASH_TYPEERASE_MASSERASE       FLASH_CR_MER  /*!< Flash mass erase activation*/
00226 /**
00227   * @}
00228   */
00229
00230 /** @defgroup FLASH_TYPE_PROGRAM FLASH Program Type
00231   * @{
00232   */
00233 #define FLASH_TYPEPROGRAM_DOUBLEWORD    FLASH_CR_PG     /*!< Program a double-word (64-bit) at a specified address.*/
00234 #define FLASH_TYPEPROGRAM_FAST          FLASH_CR_FSTPG  /*!< Fast program a 64 row double-word (64-bit) at a specified address.
00235                                                              And another 64 row double-word (64-bit) will be programmed */
00236 /**
00237   * @}
00238   */
00239
00240 /** @defgroup FLASH_OB_TYPE FLASH Option Bytes Type
00241   * @{
00242   */
00243 #define OPTIONBYTE_WRP                  0x00000001U  /*!< WRP option byte configuration             */
00244 #define OPTIONBYTE_RDP                  0x00000002U  /*!< RDP option byte configuration             */
00245 #define OPTIONBYTE_USER                 0x00000004U  /*!< User option byte configuration            */
00246 #define OPTIONBYTE_PCROP                0x00000008U  /*!< PCROP option byte configuration           */
00247 #define OPTIONBYTE_IPCC_BUF_ADDR        0x00000010U  /*!< IPCC mailbox buffer address configuration */
00248 #define OPTIONBYTE_C2_BOOT_VECT         0x00000100U  /*!< CPU2 Secure Boot reset vector             */
00249 #define OPTIONBYTE_SECURE_MODE          0x00000200U  /*!< Secure mode on activated or not           */
00250 #define OPTIONBYTE_ALL                  (OPTIONBYTE_WRP   | OPTIONBYTE_RDP           | OPTIONBYTE_USER         | \
00251                                          OPTIONBYTE_PCROP | OPTIONBYTE_IPCC_BUF_ADDR | OPTIONBYTE_C2_BOOT_VECT | \
00252                                          OPTIONBYTE_SECURE_MODE) /*!< All option byte configuration */
00253 /**
00254   * @}
00255   */
00256
00257 /** @defgroup FLASH_OB_WRP_AREA FLASH WRP Area
00258   * @{
00259   */
00260 #define OB_WRPAREA_BANK1_AREAA          0x00000000U  /*!< Flash Area A */
00261 #define OB_WRPAREA_BANK1_AREAB          0x00000001U  /*!< Flash Area B */
00262 /**
00263   * @}
00264   */
00265
00266 /** @defgroup FLASH_OB_READ_PROTECTION FLASH Option Bytes Read Protection
00267   * @{
00268   */
00269 #define OB_RDP_LEVEL_0                  0x000000AAU
00270 #define OB_RDP_LEVEL_1                  0x000000BBU
00271 #define OB_RDP_LEVEL_2                  0x000000CCU  /*!< Warning: When enabling read protection level 2
00272                                                           it's no more possible to go back to level 1 or 0 */
00273 /**
00274   * @}
00275   */
00276
00277 /** @defgroup FLASH_OB_USER_TYPE FLASH Option Bytes User Type
00278   * @{
00279   */
00280 #define OB_USER_BOR_LEV                 FLASH_OPTR_BOR_LEV    /*!< BOR reset Level */
00281 #define OB_USER_nRST_STOP               FLASH_OPTR_nRST_STOP  /*!< Reset generated when entering the stop mode */
00282 #define OB_USER_nRST_STDBY              FLASH_OPTR_nRST_STDBY /*!< Reset generated when entering the standby mode */
00283 #define OB_USER_nRST_SHDW               FLASH_OPTR_nRST_SHDW  /*!< Reset generated when entering the shutdown mode */
00284 #define OB_USER_IWDG_SW                 FLASH_OPTR_IWDG_SW    /*!< Independent watchdog selection */
00285 #define OB_USER_IWDG_STOP               FLASH_OPTR_IWDG_STOP  /*!< Independent watchdog counter freeze in stop mode */
00286 #define OB_USER_IWDG_STDBY              FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter freeze in standby mode */
00287 #define OB_USER_WWDG_SW                 FLASH_OPTR_WWDG_SW    /*!< Window watchdog selection */
00288 #define OB_USER_nBOOT1                  FLASH_OPTR_nBOOT1     /*!< Boot configuration */
00289 #define OB_USER_SRAM2PE                 FLASH_OPTR_SRAM2PE    /*!< SRAM2 parity check enable     */
00290 #define OB_USER_SRAM2RST                FLASH_OPTR_SRAM2RST   /*!< SRAM2 erase when system reset */
00291 #define OB_USER_nSWBOOT0                FLASH_OPTR_nSWBOOT0   /*!< Software BOOT0 */
00292 #define OB_USER_nBOOT0                  FLASH_OPTR_nBOOT0     /*!< nBOOT0 option bit */
00293 #define OB_USER_AGC_TRIM                FLASH_OPTR_AGC_TRIM   /*!< Automatic Gain Control Trimming */
00294 #define OB_USER_ALL                     (OB_USER_BOR_LEV    | OB_USER_nRST_STOP | OB_USER_nRST_STDBY | \
00295                                          OB_USER_nRST_SHDW  | OB_USER_IWDG_SW   | OB_USER_IWDG_STOP  | \
00296                                          OB_USER_IWDG_STDBY | OB_USER_WWDG_SW   | OB_USER_nBOOT1     | \
00297                                          OB_USER_SRAM2PE    | OB_USER_SRAM2RST  | OB_USER_nSWBOOT0   | \
00298                                          OB_USER_nBOOT0     | OB_USER_AGC_TRIM)   /*!< all option bits */
00299
00300 /**
00301   * @}
00302   */
00303
00304 /** @defgroup FLASH_OB_USER_AGC_TRIM FLASH Option Bytes Automatic Gain Control Trimming
00305   * @{
00306   */
00307 #define OB_AGC_TRIM_0                   0x00000000U                                                              /*!< Automatic Gain Control Trimming Value 0 */
00308 #define OB_AGC_TRIM_1                   FLASH_OPTR_AGC_TRIM_0                                                    /*!< Automatic Gain Control Trimming Value 1 */
00309 #define OB_AGC_TRIM_2                   FLASH_OPTR_AGC_TRIM_1                                                    /*!< Automatic Gain Control Trimming Value 2 */
00310 #define OB_AGC_TRIM_3                   (FLASH_OPTR_AGC_TRIM_1 | FLASH_OPTR_AGC_TRIM_0)                          /*!< Automatic Gain Control Trimming Value 3 */
00311 #define OB_AGC_TRIM_4                   FLASH_OPTR_AGC_TRIM_2                                                    /*!< Automatic Gain Control Trimming Value 4 */
00312 #define OB_AGC_TRIM_5                   (FLASH_OPTR_AGC_TRIM_2 | FLASH_OPTR_AGC_TRIM_0)                          /*!< Automatic Gain Control Trimming Value 5 */
00313 #define OB_AGC_TRIM_6                   (FLASH_OPTR_AGC_TRIM_2 | FLASH_OPTR_AGC_TRIM_1)                          /*!< Automatic Gain Control Trimming Value 6 */
00314 #define OB_AGC_TRIM_7                   (FLASH_OPTR_AGC_TRIM_2 | FLASH_OPTR_AGC_TRIM_1 | FLASH_OPTR_AGC_TRIM_0)  /*!< Automatic Gain Control Trimming Value 7 */
00315 /**
00316   * @}
00317   */
00318
00319 /** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level
00320   * @{
00321   */
00322 #define OB_BOR_LEVEL_0                  0x00000000U                                    /*!< Reset level threshold is around 1.7V */
00323 #define OB_BOR_LEVEL_1                  FLASH_OPTR_BOR_LEV_0                           /*!< Reset level threshold is around 2.0V */
00324 #define OB_BOR_LEVEL_2                  FLASH_OPTR_BOR_LEV_1                           /*!< Reset level threshold is around 2.2V */
00325 #define OB_BOR_LEVEL_3                  (FLASH_OPTR_BOR_LEV_0 | FLASH_OPTR_BOR_LEV_1)  /*!< Reset level threshold is around 2.5V */
00326 #define OB_BOR_LEVEL_4                  FLASH_OPTR_BOR_LEV_2                           /*!< Reset level threshold is around 2.8V */
00327 /**
00328   * @}
00329   */
00330
00331 /** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop
00332   * @{
00333   */
00334 #define OB_STOP_RST                     0x00000000U           /*!< Reset generated when entering the stop mode    */
00335 #define OB_STOP_NORST                   FLASH_OPTR_nRST_STOP  /*!< No reset generated when entering the stop mode */
00336 /**
00337   * @}
00338   */
00339
00340 /** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby
00341   * @{
00342   */
00343 #define OB_STANDBY_RST                  0x00000000U           /*!< Reset generated when entering the standby mode    */
00344 #define OB_STANDBY_NORST                FLASH_OPTR_nRST_STDBY /*!< No reset generated when entering the standby mode */
00345 /**
00346   * @}
00347   */
00348
00349 /** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown
00350   * @{
00351   */
00352 #define OB_SHUTDOWN_RST                 0x00000000U           /*!< Reset generated when entering the shutdown mode    */
00353 #define OB_SHUTDOWN_NORST               FLASH_OPTR_nRST_SHDW  /*!< No reset generated when entering the shutdown mode */
00354 /**
00355   * @}
00356   */
00357
00358 /** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type
00359   * @{
00360   */
00361 #define OB_IWDG_HW                      0x00000000U         /*!< Hardware independent watchdog */
00362 #define OB_IWDG_SW                      FLASH_OPTR_IWDG_SW  /*!< Software independent watchdog */
00363 /**
00364   * @}
00365   */
00366
00367 /** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop
00368   * @{
00369   */
00370 #define OB_IWDG_STOP_FREEZE             0x00000000U           /*!< Independent watchdog counter is frozen in Stop mode  */
00371 #define OB_IWDG_STOP_RUN                FLASH_OPTR_IWDG_STOP  /*!< Independent watchdog counter is running in Stop mode */
00372 /**
00373   * @}
00374   */
00375
00376 /** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby
00377   * @{
00378   */
00379 #define OB_IWDG_STDBY_FREEZE            0x00000000U            /*!< Independent watchdog counter is frozen in Standby mode  */
00380 #define OB_IWDG_STDBY_RUN               FLASH_OPTR_IWDG_STDBY  /*!< Independent watchdog counter is running in Standby mode */
00381 /**
00382   * @}
00383   */
00384
00385 /** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type
00386   * @{
00387   */
00388 #define OB_WWDG_HW                      0x00000000U         /*!< Hardware window watchdog */
00389 #define OB_WWDG_SW                      FLASH_OPTR_WWDG_SW  /*!< Software window watchdog */
00390 /**
00391   * @}
00392   */
00393
00394 /** @defgroup FLASH_OB_USER_SRAM2PE FLASH Option Bytes SRAM2 parity check
00395   * @{
00396   */
00397 #define OB_SRAM2_PARITY_ENABLE          0x00000000U         /*!< SRAM2 parity check enable  */
00398 #define OB_SRAM2_PARITY_DISABLE         FLASH_OPTR_SRAM2PE  /*!< SRAM2 parity check disable */
00399 /**
00400   * @}
00401   */
00402
00403 /** @defgroup FLASH_OB_USER_SRAM2RST FLASH Option Bytes SRAM2 erase when system reset
00404   * @{
00405   */
00406 #define OB_SRAM2_RST_ERASE              0x00000000U          /*!< SRAM2 erased when a system reset        */
00407 #define OB_SRAM2_RST_NOT_ERASE          FLASH_OPTR_SRAM2RST  /*!< SRAM2 is not erased when a system reset */
00408 /**
00409   * @}
00410   */
00411
00412 /** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type
00413   * @{
00414   */
00415 #define OB_BOOT1_SRAM                   0x00000000U        /*!< Embedded SRAM is selected as boot space (if BOOT0=1) */
00416 #define OB_BOOT1_SYSTEM                 FLASH_OPTR_nBOOT1  /*!< System memory is selected as boot space (if BOOT0=1) */
00417 /**
00418   * @}
00419   */
00420
00421 /** @defgroup FLASH_OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0
00422   * @{
00423   */
00424 #define OB_BOOT0_FROM_OB                0x00000000U          /*!< BOOT0 taken from the option bit nBOOT0 */
00425 #define OB_BOOT0_FROM_PIN               FLASH_OPTR_nSWBOOT0  /*!< BOOT0 taken from PH3/BOOT0 pin         */
00426 /**
00427   * @}
00428   */
00429
00430 /** @defgroup FLASH_OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit
00431   * @{
00432   */
00433 #define OB_BOOT0_RESET                  0x00000000U        /*!< nBOOT0 = 0 */
00434 #define OB_BOOT0_SET                    FLASH_OPTR_nBOOT0  /*!< nBOOT0 = 1 */
00435 /**
00436   * @}
00437   */
00438
00439 /** @defgroup FLASH_OB_PCROP_ZONE FLASH PCROP ZONE
00440   * @{
00441   */
00442 #define OB_PCROP_ZONE_A                 0x00000001U  /*!< PCROP Zone A */
00443 #define OB_PCROP_ZONE_B                 0x00000002U  /*!< PCROP Zone B */
00444 /**
00445   * @}
00446   */
00447
00448 /** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type
00449   * @{
00450   */
00451 #define OB_PCROP_RDP_NOT_ERASE          0x00000000U                /*!< PCROP area is not erased when the RDP level
00452                                                                         is decreased from Level 1 to Level 0 */
00453 #define OB_PCROP_RDP_ERASE              FLASH_PCROP1AER_PCROP_RDP  /*!< PCROP area is erased when the RDP level is
00454                                                                         decreased from Level 1 to Level 0 (full mass erase) */
00455 /**
00456   * @}
00457   */
00458
00459 /** @defgroup FLASH_OB_SECURITY_MODE Option Bytes FLASH Secure mode
00460   * @{
00461   */
00462 #define SYSTEM_NOT_IN_SECURE_MODE       0x00000000U     /*!< Unsecure mode: Security disabled  */
00463 #define SYSTEM_IN_SECURE_MODE           FLASH_OPTR_ESE  /*!< Secure mode  : Security enabled   */
00464 /**
00465   * @}
00466   */
00467
00468 /** @defgroup C2_FLASH_OB_BOOT_REGION CPU2 Option Bytes Reset Boot Vector
00469   * @{
00470   */
00471 #define OB_C2_BOOT_FROM_SRAM            0x00000000U        /*!< CPU2 boot from Sram  */
00472 #define OB_C2_BOOT_FROM_FLASH           FLASH_SRRVR_C2OPT  /*!< CPU2 boot from Flash */
00473 /**
00474   * @}
00475   */
00476 /**
00477   * @}
00478   */
00479
00480 /** @defgroup FLASH_SRAM2A_ADDRESS_RANGE RAM2A address range in secure mode
00481   * @{
00482   */
00483
00484 #define SRAM2A_START_SECURE_ADDR_0       (SRAM2A_BASE + 0x0000U)  /*  When in secure mode (SRAM2A_BASE + 0x0000) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00485 #define SRAM2A_START_SECURE_ADDR_1       (SRAM2A_BASE + 0x0400U)  /*  When in secure mode (SRAM2A_BASE + 0x0400) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00486 #define SRAM2A_START_SECURE_ADDR_2       (SRAM2A_BASE + 0x0800U)  /*  When in secure mode (SRAM2A_BASE + 0x0800) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00487 #define SRAM2A_START_SECURE_ADDR_3       (SRAM2A_BASE + 0x0C00U)  /*  When in secure mode (SRAM2A_BASE + 0x0C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00488 #define SRAM2A_START_SECURE_ADDR_4       (SRAM2A_BASE + 0x1000U)  /*  When in secure mode (SRAM2A_BASE + 0x1000) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00489 #define SRAM2A_START_SECURE_ADDR_5       (SRAM2A_BASE + 0x1400U)  /*  When in secure mode (SRAM2A_BASE + 0x1400) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00490 #define SRAM2A_START_SECURE_ADDR_6       (SRAM2A_BASE + 0x1800U)  /*  When in secure mode (SRAM2A_BASE + 0x1800) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00491 #define SRAM2A_START_SECURE_ADDR_7       (SRAM2A_BASE + 0x1C00U)  /*  When in secure mode (SRAM2A_BASE + 0x1C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00492 #define SRAM2A_START_SECURE_ADDR_8       (SRAM2A_BASE + 0x2000U)  /*  When in secure mode (SRAM2A_BASE + 0x2000) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00493 #define SRAM2A_START_SECURE_ADDR_9       (SRAM2A_BASE + 0x2400U)  /*  When in secure mode (SRAM2A_BASE + 0x2400) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00494 #define SRAM2A_START_SECURE_ADDR_10      (SRAM2A_BASE + 0x2800U)  /*  When in secure mode (SRAM2A_BASE + 0x2800) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00495 #define SRAM2A_START_SECURE_ADDR_11      (SRAM2A_BASE + 0x2C00U)  /*  When in secure mode (SRAM2A_BASE + 0x2C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00496 #define SRAM2A_START_SECURE_ADDR_12      (SRAM2A_BASE + 0x3000U)  /*  When in secure mode (SRAM2A_BASE + 0x3000) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00497 #define SRAM2A_START_SECURE_ADDR_13      (SRAM2A_BASE + 0x3400U)  /*  When in secure mode (SRAM2A_BASE + 0x3400) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00498 #define SRAM2A_START_SECURE_ADDR_14      (SRAM2A_BASE + 0x3800U)  /*  When in secure mode (SRAM2A_BASE + 0x3800) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00499 #define SRAM2A_START_SECURE_ADDR_15      (SRAM2A_BASE + 0x3C00U)  /*  When in secure mode (SRAM2A_BASE + 0x3C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00500 #define SRAM2A_START_SECURE_ADDR_16      (SRAM2A_BASE + 0x4000U)  /*  When in secure mode (SRAM2A_BASE + 0x4000) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00501 #define SRAM2A_START_SECURE_ADDR_17      (SRAM2A_BASE + 0x4400U)  /*  When in secure mode (SRAM2A_BASE + 0x4400) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00502 #define SRAM2A_START_SECURE_ADDR_18      (SRAM2A_BASE + 0x4800U)  /*  When in secure mode (SRAM2A_BASE + 0x4800) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00503 #define SRAM2A_START_SECURE_ADDR_19      (SRAM2A_BASE + 0x4C00U)  /*  When in secure mode (SRAM2A_BASE + 0x4C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00504 #define SRAM2A_START_SECURE_ADDR_20      (SRAM2A_BASE + 0x5000U)  /*  When in secure mode (SRAM2A_BASE + 0x5000) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00505 #define SRAM2A_START_SECURE_ADDR_21      (SRAM2A_BASE + 0x5400U)  /*  When in secure mode (SRAM2A_BASE + 0x5400) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00506 #define SRAM2A_START_SECURE_ADDR_22      (SRAM2A_BASE + 0x5800U)  /*  When in secure mode (SRAM2A_BASE + 0x5800) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00507 #define SRAM2A_START_SECURE_ADDR_23      (SRAM2A_BASE + 0x5C00U)  /*  When in secure mode (SRAM2A_BASE + 0x5C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00508 #define SRAM2A_START_SECURE_ADDR_24      (SRAM2A_BASE + 0x6000U)  /*  When in secure mode (SRAM2A_BASE + 0x6000) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00509 #define SRAM2A_START_SECURE_ADDR_25      (SRAM2A_BASE + 0x6400U)  /*  When in secure mode (SRAM2A_BASE + 0x6400) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00510 #define SRAM2A_START_SECURE_ADDR_26      (SRAM2A_BASE + 0x6800U)  /*  When in secure mode (SRAM2A_BASE + 0x6800) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00511 #define SRAM2A_START_SECURE_ADDR_27      (SRAM2A_BASE + 0x6C00U)  /*  When in secure mode (SRAM2A_BASE + 0x6C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00512 #define SRAM2A_START_SECURE_ADDR_28      (SRAM2A_BASE + 0x7000U)  /*  When in secure mode (SRAM2A_BASE + 0x7000) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00513 #define SRAM2A_START_SECURE_ADDR_29      (SRAM2A_BASE + 0x7400U)  /*  When in secure mode (SRAM2A_BASE + 0x7400) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00514 #define SRAM2A_START_SECURE_ADDR_30      (SRAM2A_BASE + 0x7800U)  /*  When in secure mode (SRAM2A_BASE + 0x7800) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00515 #define SRAM2A_START_SECURE_ADDR_31      (SRAM2A_BASE + 0x7C00U)  /*  When in secure mode (SRAM2A_BASE + 0x7C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00516 #define SRAM2A_FULL_UNSECURE             (SRAM2A_BASE + 0x8000U)  /*  The RAM2A is accessible to M0 Plus and M4                                  */
00517
00518 /**
00519   * @}
00520   */
00521
00522 /** @defgroup FLASH_SRAM2B_ADDRESS_RANGE RAM2B address range in secure mode
00523   * @{
00524   */
00525
00526 #define SRAM2B_START_SECURE_ADDR_0       (SRAM2B_BASE + 0x0000U)  /*  When in secure mode (SRAM2B_BASE + 0x0000) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00527 #define SRAM2B_START_SECURE_ADDR_1       (SRAM2B_BASE + 0x0400U)  /*  When in secure mode (SRAM2B_BASE + 0x0400) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00528 #define SRAM2B_START_SECURE_ADDR_2       (SRAM2B_BASE + 0x0800U)  /*  When in secure mode (SRAM2B_BASE + 0x0800) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00529 #define SRAM2B_START_SECURE_ADDR_3       (SRAM2B_BASE + 0x0C00U)  /*  When in secure mode (SRAM2B_BASE + 0x0C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00530 #define SRAM2B_START_SECURE_ADDR_4       (SRAM2B_BASE + 0x1000U)  /*  When in secure mode (SRAM2B_BASE + 0x1000) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00531 #define SRAM2B_START_SECURE_ADDR_5       (SRAM2B_BASE + 0x1400U)  /*  When in secure mode (SRAM2B_BASE + 0x1400) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00532 #define SRAM2B_START_SECURE_ADDR_6       (SRAM2B_BASE + 0x1800U)  /*  When in secure mode (SRAM2B_BASE + 0x1800) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00533 #define SRAM2B_START_SECURE_ADDR_7       (SRAM2B_BASE + 0x1C00U)  /*  When in secure mode (SRAM2B_BASE + 0x1C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00534 #define SRAM2B_START_SECURE_ADDR_8       (SRAM2B_BASE + 0x2000U)  /*  When in secure mode (SRAM2B_BASE + 0x2000) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00535 #define SRAM2B_START_SECURE_ADDR_9       (SRAM2B_BASE + 0x2400U)  /*  When in secure mode (SRAM2B_BASE + 0x2400) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00536 #define SRAM2B_START_SECURE_ADDR_10      (SRAM2B_BASE + 0x2800U)  /*  When in secure mode (SRAM2B_BASE + 0x2800) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00537 #define SRAM2B_START_SECURE_ADDR_11      (SRAM2B_BASE + 0x2C00U)  /*  When in secure mode (SRAM2B_BASE + 0x2C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00538 #define SRAM2B_START_SECURE_ADDR_12      (SRAM2B_BASE + 0x3000U)  /*  When in secure mode (SRAM2B_BASE + 0x3000) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00539 #define SRAM2B_START_SECURE_ADDR_13      (SRAM2B_BASE + 0x3400U)  /*  When in secure mode (SRAM2B_BASE + 0x3400) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00540 #define SRAM2B_START_SECURE_ADDR_14      (SRAM2B_BASE + 0x3800U)  /*  When in secure mode (SRAM2B_BASE + 0x3800) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00541 #define SRAM2B_START_SECURE_ADDR_15      (SRAM2B_BASE + 0x3C00U)  /*  When in secure mode (SRAM2B_BASE + 0x3C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00542 #define SRAM2B_START_SECURE_ADDR_16      (SRAM2B_BASE + 0x4000U)  /*  When in secure mode (SRAM2B_BASE + 0x4000) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00543 #define SRAM2B_START_SECURE_ADDR_17      (SRAM2B_BASE + 0x4400U)  /*  When in secure mode (SRAM2B_BASE + 0x4400) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00544 #define SRAM2B_START_SECURE_ADDR_18      (SRAM2B_BASE + 0x4800U)  /*  When in secure mode (SRAM2B_BASE + 0x4800) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00545 #define SRAM2B_START_SECURE_ADDR_19      (SRAM2B_BASE + 0x4C00U)  /*  When in secure mode (SRAM2B_BASE + 0x4C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00546 #define SRAM2B_START_SECURE_ADDR_20      (SRAM2B_BASE + 0x5000U)  /*  When in secure mode (SRAM2B_BASE + 0x5000) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00547 #define SRAM2B_START_SECURE_ADDR_21      (SRAM2B_BASE + 0x5400U)  /*  When in secure mode (SRAM2B_BASE + 0x5400) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00548 #define SRAM2B_START_SECURE_ADDR_22      (SRAM2B_BASE + 0x5800U)  /*  When in secure mode (SRAM2B_BASE + 0x5800) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00549 #define SRAM2B_START_SECURE_ADDR_23      (SRAM2B_BASE + 0x5C00U)  /*  When in secure mode (SRAM2B_BASE + 0x5C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00550 #define SRAM2B_START_SECURE_ADDR_24      (SRAM2B_BASE + 0x6000U)  /*  When in secure mode (SRAM2B_BASE + 0x6000) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00551 #define SRAM2B_START_SECURE_ADDR_25      (SRAM2B_BASE + 0x6400U)  /*  When in secure mode (SRAM2B_BASE + 0x6400) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00552 #define SRAM2B_START_SECURE_ADDR_26      (SRAM2B_BASE + 0x6800U)  /*  When in secure mode (SRAM2B_BASE + 0x6800) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00553 #define SRAM2B_START_SECURE_ADDR_27      (SRAM2B_BASE + 0x6C00U)  /*  When in secure mode (SRAM2B_BASE + 0x6C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00554 #define SRAM2B_START_SECURE_ADDR_28      (SRAM2B_BASE + 0x7000U)  /*  When in secure mode (SRAM2B_BASE + 0x7000) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00555 #define SRAM2B_START_SECURE_ADDR_29      (SRAM2B_BASE + 0x7400U)  /*  When in secure mode (SRAM2B_BASE + 0x7400) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00556 #define SRAM2B_START_SECURE_ADDR_30      (SRAM2B_BASE + 0x7800U)  /*  When in secure mode (SRAM2B_BASE + 0x7800) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00557 #define SRAM2B_START_SECURE_ADDR_31      (SRAM2B_BASE + 0x7C00U)  /*  When in secure mode (SRAM2B_BASE + 0x7C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus  */
00558 #define SRAM2B_FULL_UNSECURE             (SRAM2B_BASE + 0x8000U)  /*  The RAM2B is accessible to M0 Plus and M4                                  */
00559
00560 /**
00561   * @}
00562   */
00563
00564 /**
00565   * @}
00566   */
00567
00568 /* Exported macros -----------------------------------------------------------*/
00569 /** @defgroup FLASH_Exported_Macros FLASH Exported Macros
00570   *  @brief macros to control FLASH features
00571   *  @{
00572   */
00573
00574 /**
00575   * @brief  Set the FLASH Latency.
00576   * @param __LATENCY__ FLASH Latency
00577   *         This parameter can be one of the following values :
00578   *     @arg @ref FLASH_LATENCY_0 FLASH Zero wait state
00579   *     @arg @ref FLASH_LATENCY_1 FLASH One wait state
00580   *     @arg @ref FLASH_LATENCY_2 FLASH Two wait states
00581   *     @arg @ref FLASH_LATENCY_3 FLASH Three wait states
00582   * @retval None
00583   */
00584 #define __HAL_FLASH_SET_LATENCY(__LATENCY__)    MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__))
00585
00586 /**
00587   * @brief  Get the FLASH Latency.
00588   * @retval FLASH Latency
00589   *         Returned value can be one of the following values :
00590   *     @arg @ref FLASH_LATENCY_0 FLASH Zero wait state
00591   *     @arg @ref FLASH_LATENCY_1 FLASH One wait state
00592   *     @arg @ref FLASH_LATENCY_2 FLASH Two wait states
00593   *     @arg @ref FLASH_LATENCY_3 FLASH Three wait states
00594   */
00595 #define __HAL_FLASH_GET_LATENCY()               READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)
00596
00597 /**
00598   * @brief  Enable the FLASH prefetch buffer.
00599   * @retval None
00600   */
00601 #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE()    SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
00602
00603 /**
00604   * @brief  Disable the FLASH prefetch buffer.
00605   * @retval None
00606   */
00607 #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE()   CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
00608
00609 /**
00610   * @brief  Enable the FLASH instruction cache.
00611   * @retval none
00612   */
00613 #define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE()  SET_BIT(FLASH->ACR, FLASH_ACR_ICEN)
00614
00615 /**
00616   * @brief  Disable the FLASH instruction cache.
00617   * @retval none
00618   */
00619 #define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN)
00620
00621 /**
00622   * @brief  Enable the FLASH data cache.
00623   * @retval none
00624   */
00625 #define __HAL_FLASH_DATA_CACHE_ENABLE()         SET_BIT(FLASH->ACR, FLASH_ACR_DCEN)
00626
00627 /**
00628   * @brief  Disable the FLASH data cache.
00629   * @retval none
00630   */
00631 #define __HAL_FLASH_DATA_CACHE_DISABLE()        CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN)
00632
00633 /**
00634   * @brief  Reset the FLASH instruction Cache.
00635   * @note   This function must be used only when the Instruction Cache is disabled.
00636   * @retval None
00637   */
00638 #define __HAL_FLASH_INSTRUCTION_CACHE_RESET()   do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);   \
00639                                                      CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
00640                                                    } while (0)
00641
00642 /**
00643   * @brief  Reset the FLASH data Cache.
00644   * @note   This function must be used only when the data Cache is disabled.
00645   * @retval None
00646   */
00647 #define __HAL_FLASH_DATA_CACHE_RESET()          do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);   \
00648                                                      CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \
00649                                                    } while (0)
00650
00651 /**
00652   * @}
00653   */
00654
00655 /** @defgroup FLASH_Interrupt FLASH Interrupts Macros
00656  *  @brief macros to handle FLASH interrupts
00657  * @{
00658  */
00659
00660 /**
00661   * @brief  Enable the specified FLASH interrupt.
00662   * @param __INTERRUPT__ FLASH interrupt
00663   *         This parameter can be any combination of the following values:
00664   *     @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
00665   *     @arg @ref FLASH_IT_OPERR Error Interrupt
00666   *     @arg @ref FLASH_IT_RDERR PCROP Read Error Interrupt
00667   *     @arg @ref FLASH_IT_ECCC ECC Correction Interrupt
00668   * @retval none
00669   */
00670 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)    do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCCIE); }\
00671                                                      if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
00672                                                    } while(0)
00673
00674 /**
00675   * @brief  Disable the specified FLASH interrupt.
00676   * @param __INTERRUPT__ FLASH interrupt
00677   *         This parameter can be any combination of the following values:
00678   *     @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
00679   *     @arg @ref FLASH_IT_OPERR Error Interrupt
00680   *     @arg @ref FLASH_IT_RDERR PCROP Read Error Interrupt
00681   *     @arg @ref FLASH_IT_ECCC ECC Correction Interrupt
00682   * @retval none
00683   */
00684 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)   do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCCIE); }\
00685                                                      if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
00686                                                    } while(0)
00687
00688 /**
00689   * @brief  Check whether the specified FLASH flag is set or not.
00690   * @param __FLAG__ specifies the FLASH flag to check.
00691   *   This parameter can be one of the following values:
00692   *     @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
00693   *     @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag
00694   *     @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag
00695   *     @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag
00696   *     @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag
00697   *     @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag
00698   *     @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag
00699   *     @arg @ref FLASH_FLAG_MISERR FLASH Fast programming data miss error flag
00700   *     @arg @ref FLASH_FLAG_FASTERR FLASH Fast programming error flag
00701   *     @arg @ref FLASH_FLAG_OPTNV FLASH User Option OPTVAL indication
00702   *     @arg @ref FLASH_FLAG_RDERR FLASH PCROP read  error flag
00703   *     @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag
00704   *     @arg @ref FLASH_FLAG_BSY FLASH write/erase operations in progress flag
00705   *     @arg @ref FLASH_FLAG_CFGBSY Programming/erase configuration busy
00706   *     @arg @ref FLASH_FLAG_PESD FLASH Programming/erase operation suspended
00707   *     @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected
00708   *     @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected
00709   * @retval The new state of FLASH_FLAG (SET or RESET).
00710   */
00711 #define __HAL_FLASH_GET_FLAG(__FLAG__)          ((((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS)) != 0U) ? \
00712                                                  (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__))  : \
00713                                                  (READ_BIT(FLASH->SR,   (__FLAG__)) == (__FLAG__)))
00714 /**
00715   * @brief  Clear the FLASH's pending flags.
00716   * @param __FLAG__ specifies the FLASH flags to clear.
00717   *   This parameter can be any combination of the following values:
00718   *     @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
00719   *     @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag
00720   *     @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag
00721   *     @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag
00722   *     @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag
00723   *     @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag
00724   *     @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag
00725   *     @arg @ref FLASH_FLAG_MISERR FLASH Fast programming data miss error flag
00726   *     @arg @ref FLASH_FLAG_FASTERR FLASH Fast programming error flag
00727   *     @arg @ref FLASH_FLAG_RDERR FLASH PCROP read  error flag
00728   *     @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag
00729   *     @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected
00730   *     @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected
00731   *     @arg @ref FLASH_FLAG_SR_ERRORS FLASH All SR errors flags
00732   *     @arg @ref FLASH_FLAG_ECCR_ERRORS FLASH All ECCR errors flags
00733   *     @arg @ref FLASH_FLAG_ALL_ERRORS FLASH All errors flags
00734   * @retval None
00735   */
00736 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__)        do { if(((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS)) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS))); }\
00737                                                      if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); }\
00738                                                    } while(0)
00739 /**
00740   * @}
00741   */
00742
00743 /* Include FLASH HAL Extended module */
00744 #include "stm32wbxx_hal_flash_ex.h"
00745 /* Exported variables --------------------------------------------------------*/
00746 /** @defgroup FLASH_Exported_Variables FLASH Exported Variables
00747   * @{
00748   */
00749 extern FLASH_ProcessTypeDef pFlash;
00750 /**
00751   * @}
00752   */
00753
00754 /* Exported functions --------------------------------------------------------*/
00755 /** @addtogroup FLASH_Exported_Functions
00756   * @{
00757   */
00758
00759 /* Program operation functions  ***********************************************/
00760 /** @addtogroup FLASH_Exported_Functions_Group1
00761   * @{
00762   */
00763 HAL_StatusTypeDef  HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
00764 HAL_StatusTypeDef  HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
00765 /* FLASH IRQ handler method */
00766 void               HAL_FLASH_IRQHandler(void);
00767 /* Callbacks in non blocking modes */
00768 void               HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
00769 void               HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
00770 /**
00771   * @}
00772   */
00773
00774 /* Peripheral Control functions  **********************************************/
00775 /** @addtogroup FLASH_Exported_Functions_Group2
00776   * @{
00777   */
00778 HAL_StatusTypeDef  HAL_FLASH_Unlock(void);
00779 HAL_StatusTypeDef  HAL_FLASH_Lock(void);
00780 /* Option bytes control */
00781 HAL_StatusTypeDef  HAL_FLASH_OB_Unlock(void);
00782 HAL_StatusTypeDef  HAL_FLASH_OB_Lock(void);
00783 HAL_StatusTypeDef  HAL_FLASH_OB_Launch(void);
00784 /**
00785   * @}
00786   */
00787
00788 /* Peripheral State functions  ************************************************/
00789 /** @addtogroup FLASH_Exported_Functions_Group3
00790   * @{
00791   */
00792 uint32_t HAL_FLASH_GetError(void);
00793 /**
00794   * @}
00795   */
00796
00797 /**
00798   * @}
00799   */
00800
00801 /* Private types --------------------------------------------------------*/
00802 /** @defgroup FLASH_Private_types FLASH Private Types
00803   * @{
00804   */
00805 HAL_StatusTypeDef  FLASH_WaitForLastOperation(uint32_t Timeout);
00806 /**
00807   * @}
00808   */
00809
00810 /* Private constants --------------------------------------------------------*/
00811 /** @defgroup FLASH_Private_Constants FLASH Private Constants
00812   * @{
00813   */
00814 #define FLASH_END_ADDR                          (FLASH_BASE + FLASH_SIZE - 1U)
00815
00816 #define FLASH_BANK_SIZE                         FLASH_SIZE   /*!< FLASH Bank Size */
00817 #define FLASH_PAGE_SIZE                         0x00001000U  /*!< FLASH Page Size, 4 KBytes */
00818 #define FLASH_PAGE_NB                           (FLASH_SIZE / FLASH_PAGE_SIZE)
00819 #define FLASH_TIMEOUT_VALUE                     1000U        /*!< FLASH Execution Timeout, 1 s */
00820
00821 #define FLASH_PCROP_GRANULARITY_OFFSET          11U                                      /*!< FLASH Code Readout Protection granularity offset */
00822 #define FLASH_PCROP_GRANULARITY                 (1UL << FLASH_PCROP_GRANULARITY_OFFSET)  /*!< FLASH Code Readout Protection granularity, 2 KBytes */
00823
00824 #define FLASH_TYPENONE                          0x00000000U                                /*!< No Programmation Procedure On Going */
00825 /**
00826   * @}
00827   */
00828
00829 /** @defgroup SRAM_MEMORY_SIZE  SRAM memory size
00830   * @{
00831   */
00832 #define SRAM_SECURE_PAGE_GRANULARITY_OFFSET     10U                                      /*!< Secure SRAM2A and SRAM2B Protection granularity offset */
00833 #define SRAM_SECURE_PAGE_GRANULARITY            (1UL << FLASH_PCROP_GRANULARITY_OFFSET)  /*!< Secure SRAM2A and SRAM2B Protection granularity, 1KBytes */
00834 /**
00835   * @}
00836   */
00837
00838 /* Private macros ------------------------------------------------------------*/
00839 /** @defgroup FLASH_Private_Macros FLASH Private Macros
00840  *  @{
00841  */
00842 #define IS_FLASH_MAIN_MEM_ADDRESS(__VALUE__)        (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 1UL)))
00843
00844 #define IS_FLASH_FAST_PROGRAM_ADDRESS(__VALUE__)    (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 256UL)) && (((__VALUE__) % 256UL) == 0UL))
00845
00846 #define IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__VALUE__)   (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 8UL)) && (((__VALUE__) % 8UL) == 0UL))
00847
00848 #define IS_FLASH_PROGRAM_OTP_ADDRESS(__VALUE__)     (((__VALUE__) >= OTP_AREA_BASE) && ((__VALUE__) <= (OTP_AREA_END_ADDR + 1UL - 8UL)) && (((__VALUE__) % 8UL) == 0UL))
00849
00850 #define IS_FLASH_PROGRAM_ADDRESS(__VALUE__)         (IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__VALUE__) || IS_FLASH_PROGRAM_OTP_ADDRESS(__VALUE__))
00851
00852 #define IS_FLASH_PAGE(__VALUE__)                    ((__VALUE__) < FLASH_PAGE_NB)
00853
00854 #define IS_ADDR_ALIGNED_64BITS(__VALUE__)           (((__VALUE__) & 0x7U) == (0x00UL))
00855
00856 #define IS_FLASH_TYPEERASE(__VALUE__)               (((__VALUE__) == FLASH_TYPEERASE_PAGES) || \
00857                                                      ((__VALUE__) == FLASH_TYPEERASE_MASSERASE))
00858
00859 #define IS_FLASH_TYPEPROGRAM(__VALUE__)             (((__VALUE__) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \
00860                                                      ((__VALUE__) == FLASH_TYPEPROGRAM_FAST))
00861
00862 #define IS_OB_SFSA_START_ADDR(__VALUE__)            (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= FLASH_END_ADDR) && (((__VALUE__) & ~(uint32_t)0xFFFU) == (__VALUE__)))
00863 #define IS_OB_SBRSA_START_ADDR(__VALUE__)           (((__VALUE__) >= SRAM2A_BASE) && ((__VALUE__) <= (SRAM2A_BASE + SRAM2A_SIZE - 1U)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__)))
00864 #define IS_OB_SNBRSA_START_ADDR(__VALUE__)          (((__VALUE__) >= SRAM2B_BASE) && ((__VALUE__) <= (SRAM2B_BASE + SRAM2B_SIZE - 1U)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__)))
00865 #define IS_OB_SECURE_MODE(__VALUE__)                (((__VALUE__) == SYSTEM_IN_SECURE_MODE) || ((__VALUE__) == SYSTEM_NOT_IN_SECURE_MODE))
00866
00867 #define IS_OPTIONBYTE(__VALUE__)                    (((__VALUE__) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP | \
00868                                                               OPTIONBYTE_IPCC_BUF_ADDR | OPTIONBYTE_C2_BOOT_VECT | OPTIONBYTE_SECURE_MODE)))
00869
00870 #define IS_OB_WRPAREA(__VALUE__)                    (((__VALUE__) == OB_WRPAREA_BANK1_AREAA) || ((__VALUE__) == OB_WRPAREA_BANK1_AREAB))
00871
00872 #define IS_OB_RDP_LEVEL(__VALUE__)                  (((__VALUE__) == OB_RDP_LEVEL_0)   ||\
00873                                                      ((__VALUE__) == OB_RDP_LEVEL_1)   ||\
00874                                                      ((__VALUE__) == OB_RDP_LEVEL_2))
00875
00876 #define IS_OB_USER_TYPE(__VALUE__)                  ((((__VALUE__) & OB_USER_ALL) != 0U) && \
00877                                                      (((__VALUE__) & ~OB_USER_ALL) == 0U))
00878
00879 #define IS_OB_USER_CONFIG(__TYPE__, __VALUE__)      ((((__TYPE__) & OB_USER_BOR_LEV) == OB_USER_BOR_LEV) \
00880                                                       ? ((((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_0) || \
00881                                                          (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_1) || \
00882                                                          (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_2) || \
00883                                                          (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_3) || \
00884                                                          (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_4)) \
00885                                                       : ((((__TYPE__) & OB_USER_AGC_TRIM) == OB_USER_AGC_TRIM) \
00886                                                        ? ((((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_0) || \
00887                                                           (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_1) || \
00888                                                           (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_2) || \
00889                                                           (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_3) || \
00890                                                           (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_4) || \
00891                                                           (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_5) || \
00892                                                           (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_6) || \
00893                                                           (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_7)) \
00894                                                        : ((~(__TYPE__) & (__VALUE__)) == 0U)))
00895
00896 #define IS_OB_USER_AGC_TRIMMING(__VALUE__)          (((__VALUE__) == OB_AGC_TRIM_0) || ((__VALUE__) == OB_AGC_TRIM_1) || \
00897                                                      ((__VALUE__) == OB_AGC_TRIM_2) || ((__VALUE__) == OB_AGC_TRIM_3) || \
00898                                                      ((__VALUE__) == OB_AGC_TRIM_4) || ((__VALUE__) == OB_AGC_TRIM_5) || \
00899                                                      ((__VALUE__) == OB_AGC_TRIM_6) || ((__VALUE__) == OB_AGC_TRIM_7))
00900
00901 #define IS_OB_USER_BOR_LEVEL(__VALUE__)             (((__VALUE__) == OB_BOR_LEVEL_0) || ((__VALUE__) == OB_BOR_LEVEL_1) || \
00902                                                      ((__VALUE__) == OB_BOR_LEVEL_2) || ((__VALUE__) == OB_BOR_LEVEL_3) || \
00903                                                      ((__VALUE__) == OB_BOR_LEVEL_4))
00904
00905 #define IS_OB_PCROP_CONFIG(__VALUE__)               (((__VALUE__) & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | OB_PCROP_RDP_ERASE)) == 0U)
00906
00907 #define IS_OB_IPCC_BUF_ADDR(__VALUE__)              (IS_OB_SBRSA_START_ADDR(__VALUE__) || IS_OB_SNBRSA_START_ADDR(__VALUE__))
00908
00909 #define IS_OB_BOOT_VECTOR_ADDR(__VALUE__)           ((((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 1U)))    || \
00910                                                      (((__VALUE__) >= SRAM1_BASE) && ((__VALUE__) <= (SRAM1_BASE + SRAM1_SIZE - 1U)))    || \
00911                                                      (((__VALUE__) >= SRAM2A_BASE) && ((__VALUE__) <= (SRAM2A_BASE + SRAM2A_SIZE - 1U))) || \
00912                                                      (((__VALUE__) >= SRAM2B_BASE) && ((__VALUE__) <= (SRAM2B_BASE + SRAM2B_SIZE - 1U))))
00913
00914 #define IS_OB_BOOT_REGION(__VALUE__)                (((__VALUE__) == OB_C2_BOOT_FROM_FLASH) || ((__VALUE__) == OB_C2_BOOT_FROM_SRAM))
00915
00916 #define IS_OB_SECURE_CONFIG(__VALUE__)              (((__VALUE__) & ~(OB_SECURE_CONFIG_MEMORY | OB_SECURE_CONFIG_BOOT_RESET)) == 0U)
00917
00918 #define IS_FLASH_LATENCY(__VALUE__)                 (((__VALUE__) == FLASH_LATENCY_0) || \
00919                                                      ((__VALUE__) == FLASH_LATENCY_1) || \
00920                                                      ((__VALUE__) == FLASH_LATENCY_2) || \
00921                                                      ((__VALUE__) == FLASH_LATENCY_3))
00922 /**
00923   * @}
00924   */
00925
00926 /**
00927   * @}
00928   */
00929
00930 /**
00931   * @}
00932   */
00933
00934 #ifdef __cplusplus
00935 }
00936 #endif
00937
00938 #endif /* STM32WBxx_HAL_FLASH_H */
00939
00940 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_flash_ex.c Source File

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stm32wbxx_hal_flash_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_flash_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended FLASH HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the FLASH extended peripheral:
00008   *           + Extended programming operations functions
00009   *
00010  @verbatim
00011  ==============================================================================
00012                    ##### Flash Extended features #####
00013   ==============================================================================
00014
00015   [..] Comparing to other previous devices, the FLASH interface for STM32WBxx
00016        devices contains the following additional features
00017
00018        (+) Capacity up to 1 Mbyte with single bank architecture supporting read-while-write
00019            capability (RWW)
00020        (+) Single bank memory organization
00021        (+) PCROP protection
00022        (+) WRP protection
00023        (+) CPU2 Security area
00024        (+) Program Erase Suspend feature
00025
00026                         ##### How to use this driver #####
00027  ==============================================================================
00028   [..] This driver provides functions to configure and program the FLASH memory
00029        of all STM32WBxx devices. It includes
00030       (#) Flash Memory Erase functions:
00031            (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
00032                 HAL_FLASH_Lock() functions
00033            (++) Erase function: Erase page, erase all sectors
00034            (++) There are two modes of erase :
00035              (+++) Polling Mode using HAL_FLASHEx_Erase()
00036              (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
00037
00038       (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to :
00039         (++) Set/Reset the write protection (per 4 KByte)
00040         (++) Set the Read protection Level
00041         (++) Program the user Option Bytes
00042         (++) Configure the PCROP protection (per 2 KByte)
00043         (++) Configure the IPCC Buffer start Address
00044         (++) Configure the CPU2 boot region and reset vector start Address
00045         (++) Configure the Flash and SRAM2 secure area
00046
00047       (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to :
00048         (++) Get the value of a write protection area
00049         (++) Know if the read protection is activated
00050         (++) Get the value of the user Option Bytes
00051         (++) Get the value of a PCROP area
00052         (++) Get the IPCC Buffer start Address
00053         (++) Get the CPU2 boot region and reset vector start Address
00054         (++) Get the Flash and SRAM2 secure area
00055
00056       (#) Flash Suspend, Allow functions:
00057            (++) Suspend or Allow new program or erase operation request using HAL_FLASHEx_SuspendOperation() and
00058                 HAL_FLASHEx_AllowOperation() functions
00059
00060       (#) Check is flash content is empty or not using HAL_FLASHEx_FlashEmptyCheck().
00061           and modify this setting (for flash loader purpose e.g.) using
00062           HAL_FLASHEx_ForceFlashEmpty().
00063
00064  @endverbatim
00065   ******************************************************************************
00066   * @attention
00067   *
00068   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00069   * All rights reserved.</center></h2>
00070   *
00071   * This software component is licensed by ST under BSD 3-Clause license,
00072   * the "License"; You may not use this file except in compliance with the
00073   * License. You may obtain a copy of the License at:
00074   *                        opensource.org/licenses/BSD-3-Clause
00075   *
00076   ******************************************************************************
00077   */
00078
00079 /* Includes ------------------------------------------------------------------*/
00080 #include "stm32wbxx_hal.h"
00081
00082 /** @addtogroup STM32WBxx_HAL_Driver
00083   * @{
00084   */
00085
00086 /** @defgroup FLASHEx FLASHEx
00087   * @brief FLASH Extended HAL module driver
00088   * @{
00089   */
00090
00091 #ifdef HAL_FLASH_MODULE_ENABLED
00092
00093 /* Private typedef -----------------------------------------------------------*/
00094 /* Private define ------------------------------------------------------------*/
00095 /* Private macro -------------------------------------------------------------*/
00096 /* Private variables ---------------------------------------------------------*/
00097 /* Private function prototypes -----------------------------------------------*/
00098 /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
00099  * @{
00100  */
00101 static void              FLASH_MassErase(void);
00102 static void              FLASH_AcknowledgePageErase(void);
00103 static void              FLASH_FlushCaches(void);
00104 static void              FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset);
00105 static void              FLASH_OB_OptrConfig(uint32_t UserType, uint32_t UserConfig, uint32_t RDPLevel);
00106 static void              FLASH_OB_PCROP1AConfig(uint32_t PCROPConfig, uint32_t PCROP1AStartAddr, uint32_t PCROP1AEndAddr);
00107 static void              FLASH_OB_PCROP1BConfig(uint32_t PCROP1BStartAddr, uint32_t PCROP1BEndAddr);
00108 static void              FLASH_OB_IPCCBufferAddrConfig(uint32_t IPCCDataBufAddr);
00109 static void              FLASH_OB_SecureConfig(FLASH_OBProgramInitTypeDef *pOBParam);
00110 static void              FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRDPEndOffset);
00111 static uint32_t          FLASH_OB_GetRDP(void);
00112 static uint32_t          FLASH_OB_GetUser(void);
00113 static void              FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROP1AStartAddr, uint32_t *PCROP1AEndAddr, uint32_t *PCROP1BStartAddr, uint32_t *PCROP1BEndAddr);
00114 static uint32_t          FLASH_OB_GetIPCCBufferAddr(void);
00115 static void              FLASH_OB_GetSecureMemoryConfig(uint32_t *SecureFlashStartAddr, uint32_t *SecureRAM2aStartAddr, uint32_t *SecureRAM2bStartAddr, uint32_t *SecureMode);
00116 static void              FLASH_OB_GetC2BootResetConfig(uint32_t *C2BootResetVectAddr, uint32_t *C2BootResetRegion);
00117 static HAL_StatusTypeDef FLASH_OB_ProceedWriteOperation(void);
00118 /**
00119   * @}
00120   */
00121
00122 /* Exported functions -------------------------------------------------------*/
00123 /** @defgroup FLASHEx_Exported_Functions FLASH Extended Exported Functions
00124   * @{
00125   */
00126
00127 /** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
00128  *  @brief   Extended IO operation functions
00129  *
00130 @verbatim
00131  ===============================================================================
00132                 ##### Extended programming operation functions #####
00133  ===============================================================================
00134     [..]
00135     This subsection provides a set of functions allowing to manage the Extended FLASH
00136     programming operations Operations.
00137
00138 @endverbatim
00139   * @{
00140   */
00141 /**
00142   * @brief  Perform a mass erase or erase the specified FLASH memory pages.
00143   * @note   Before any operation, it is possible to check there is no operation suspended
00144   *         by call HAL_FLASHEx_IsOperationSuspended()
00145   * @param[in]  pEraseInit Pointer to an @ref FLASH_EraseInitTypeDef structure that
00146   *         contains the configuration information for the erasing.
00147   * @param[out]  PageError Pointer to variable that contains the configuration
00148   *         information on faulty page in case of error (0xFFFFFFFF means that all
00149   *         the pages have been correctly erased)
00150   * @retval HAL Status
00151   */
00152 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
00153 {
00154   HAL_StatusTypeDef status;
00155   uint32_t index;
00156
00157   /* Check the parameters */
00158   assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
00159
00160   /* Process Locked */
00161   __HAL_LOCK(&pFlash);
00162
00163   /* Reset error code */
00164   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00165
00166   /* Verify that next operation can be proceed */
00167   status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
00168
00169   if (status == HAL_OK)
00170   {
00171     if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
00172     {
00173       /* Mass erase to be done */
00174       FLASH_MassErase();
00175
00176       /* Wait for last operation to be completed */
00177       status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
00178
00179       /* If operation is completed or interrupted, no need to clear the Mass Erase Bit */
00180     }
00181     else
00182     {
00183       /*Initialization of PageError variable*/
00184       *PageError = 0xFFFFFFFFU;
00185
00186       for (index = pEraseInit->Page; index < (pEraseInit->Page + pEraseInit->NbPages); index++)
00187       {
00188         /* Start erase page */
00189         FLASH_PageErase(index);
00190
00191         /* Wait for last operation to be completed */
00192         status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
00193
00194         if (status != HAL_OK)
00195         {
00196           /* In case of error, stop erase procedure and return the faulty address */
00197           *PageError = index;
00198           break;
00199         }
00200       }
00201
00202       /* If operation is completed or interrupted, disable the Page Erase Bit */
00203       FLASH_AcknowledgePageErase();
00204     }
00205
00206     /* Flush the caches to be sure of the data consistency */
00207     FLASH_FlushCaches();
00208   }
00209
00210   /* Process Unlocked */
00211   __HAL_UNLOCK(&pFlash);
00212
00213   return status;
00214 }
00215
00216 /**
00217   * @brief  Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.
00218   * @note   Before any operation, it is possible to check there is no operation suspended
00219   *         by call HAL_FLASHEx_IsOperationSuspended()
00220   * @param  pEraseInit Pointer to an @ref FLASH_EraseInitTypeDef structure that
00221   *         contains the configuration information for the erasing.
00222   * @retval HAL Status
00223   */
00224 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
00225 {
00226   HAL_StatusTypeDef status;
00227
00228   /* Check the parameters */
00229   assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
00230
00231   /* Process Locked */
00232   __HAL_LOCK(&pFlash);
00233
00234   /* Reset error code */
00235   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00236
00237   /* save procedure for interrupt treatment */
00238   pFlash.ProcedureOnGoing = pEraseInit->TypeErase;
00239
00240   /* Verify that next operation can be proceed */
00241   status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
00242
00243   if (status != HAL_OK)
00244   {
00245     /* Process Unlocked */
00246     __HAL_UNLOCK(&pFlash);
00247   }
00248   else
00249   {
00250     /* Enable End of Operation and Error interrupts */
00251     __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
00252
00253     if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
00254     {
00255       /* Set Page to 0 for Interrupt callback managment */
00256       pFlash.Page = 0;
00257
00258       /* Proceed to Mass Erase */
00259       FLASH_MassErase();
00260     }
00261     else
00262     {
00263       /* Erase by page to be done */
00264       pFlash.NbPagesToErase = pEraseInit->NbPages;
00265       pFlash.Page = pEraseInit->Page;
00266
00267       /*Erase 1st page and wait for IT */
00268       FLASH_PageErase(pEraseInit->Page);
00269     }
00270   }
00271
00272   /* return status */
00273   return status;
00274 }
00275
00276 /**
00277   * @brief  Program Option bytes.
00278   * @param  pOBInit Pointer to an @ref FLASH_OBProgramInitTypeDef structure that
00279   *         contains the configuration information for the programming.
00280   * @note   To configure any option bytes, the option lock bit OPTLOCK must be
00281   *         cleared with the call of @ref HAL_FLASH_OB_Unlock() function.
00282   * @note   New option bytes configuration will be taken into account only
00283   *         - after an option bytes launch through the call of @ref HAL_FLASH_OB_Launch()
00284   *         - a Power On Reset
00285   *         - an exit from Standby or Shutdown mode.
00286   * @retval HAL Status
00287   */
00288 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
00289 {
00290   uint32_t optr;
00291   HAL_StatusTypeDef status;
00292
00293   /* Check the parameters */
00294   assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
00295
00296   /* Process Locked */
00297   __HAL_LOCK(&pFlash);
00298
00299   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00300
00301   /* Write protection configuration */
00302   if ((pOBInit->OptionType & OPTIONBYTE_WRP) != 0U)
00303   {
00304     /* Configure of Write protection on the selected area */
00305     FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset);
00306   }
00307
00308   /* Option register */
00309   if ((pOBInit->OptionType & (OPTIONBYTE_RDP | OPTIONBYTE_USER)) == (OPTIONBYTE_RDP | OPTIONBYTE_USER))
00310   {
00311     /* Fully modify OPTR register with RDP & user datas */
00312     FLASH_OB_OptrConfig(pOBInit->UserType, pOBInit->UserConfig, pOBInit->RDPLevel);
00313   }
00314   else if ((pOBInit->OptionType & OPTIONBYTE_RDP) != 0U)
00315   {
00316     /* Only modify RDP so get current user data */
00317     optr = FLASH_OB_GetUser();
00318
00319     /* Remove BOR LEVEL User Type*/
00320     optr &= ~OB_USER_BOR_LEV;
00321
00322     FLASH_OB_OptrConfig(optr, optr, pOBInit->RDPLevel);
00323   }
00324   else if ((pOBInit->OptionType & OPTIONBYTE_USER) != 0U)
00325   {
00326     /* Only modify user so get current RDP level */
00327     optr = FLASH_OB_GetRDP();
00328     FLASH_OB_OptrConfig(pOBInit->UserType, pOBInit->UserConfig, optr);
00329   }
00330   else
00331   {
00332     /* Do Nothing */
00333   }
00334
00335   /* PCROP Configuration */
00336   if ((pOBInit->OptionType & OPTIONBYTE_PCROP) != 0U)
00337   {
00338     /* Check the parameters */
00339     assert_param(IS_OB_PCROP_CONFIG(pOBInit->PCROPConfig));
00340
00341     if ((pOBInit->PCROPConfig & (OB_PCROP_ZONE_A | OB_PCROP_RDP_ERASE)) != 0U)
00342     {
00343       /* Configure the Zone 1A Proprietary code readout protection */
00344       FLASH_OB_PCROP1AConfig(pOBInit->PCROPConfig, pOBInit->PCROP1AStartAddr, pOBInit->PCROP1AEndAddr);
00345     }
00346
00347     if ((pOBInit->PCROPConfig & OB_PCROP_ZONE_B) != 0U)
00348     {
00349       /* Configure the Zone 1B Proprietary code readout protection */
00350       FLASH_OB_PCROP1BConfig(pOBInit->PCROP1BStartAddr, pOBInit->PCROP1BEndAddr);
00351     }
00352   }
00353
00354   /*  Secure mode and CPU2 Boot Vector */
00355   if ((pOBInit->OptionType & (OPTIONBYTE_SECURE_MODE | OPTIONBYTE_C2_BOOT_VECT)) != 0U)
00356   {
00357     /* Set the secure flash and SRAM memory start address */
00358     FLASH_OB_SecureConfig(pOBInit);
00359   }
00360
00361   /* IPCC mailbox data buffer address */
00362   if ((pOBInit->OptionType & OPTIONBYTE_IPCC_BUF_ADDR) != 0U)
00363   {
00364     /* Configure the IPCC data buffer address */
00365     FLASH_OB_IPCCBufferAddrConfig(pOBInit->IPCCdataBufAddr);
00366   }
00367
00368   /* Proceed the OB Write Operation */
00369   status = FLASH_OB_ProceedWriteOperation();
00370
00371   /* Process Unlocked */
00372   __HAL_UNLOCK(&pFlash);
00373
00374   /* return status */
00375   return status;
00376 }
00377
00378 /**
00379   * @brief  Get the Option bytes configuration.
00380   * @note   warning: this API only read flash register, it does not reflect any
00381   *         change that would have been programmed between previous Option byte
00382   *         loading and current call.
00383   * @param  pOBInit Pointer to an @ref FLASH_OBProgramInitTypeDef structure that contains the
00384   *                  configuration information. The fields pOBInit->WRPArea and
00385   *                  pOBInit->PCROPConfig should indicate which area is requested
00386   *                  for the WRP and PCROP.
00387   * @retval None
00388   */
00389 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
00390 {
00391   pOBInit->OptionType = OPTIONBYTE_ALL;
00392
00393   if ((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB))
00394   {
00395     /* Get write protection on the selected area */
00396     FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset));
00397   }
00398
00399   /* Get Read protection level */
00400   pOBInit->RDPLevel = FLASH_OB_GetRDP();
00401
00402   /* Get the user option bytes */
00403   pOBInit->UserConfig = FLASH_OB_GetUser();
00404   pOBInit->UserType = OB_USER_ALL;
00405
00406   /* Get the Zone 1A and 1B Proprietary code readout protection */
00407   FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROP1AStartAddr), &(pOBInit->PCROP1AEndAddr), &(pOBInit->PCROP1BStartAddr), &(pOBInit->PCROP1BEndAddr));
00408   pOBInit->PCROPConfig |= (OB_PCROP_ZONE_A | OB_PCROP_ZONE_B);
00409
00410   /* Get the IPCC start Address */
00411   pOBInit->IPCCdataBufAddr = FLASH_OB_GetIPCCBufferAddr();
00412
00413   /* Get the Secure Flash start address, Secure Backup RAM2a start address, Secure non-Backup RAM2b start address and the Security Mode, */
00414   FLASH_OB_GetSecureMemoryConfig(&(pOBInit->SecureFlashStartAddr), &(pOBInit->SecureRAM2aStartAddr), &(pOBInit->SecureRAM2bStartAddr), &(pOBInit->SecureMode));
00415
00416   /* Get the M0+ Secure Boot reset vector and Secure Boot memory selection */
00417   FLASH_OB_GetC2BootResetConfig(&(pOBInit->C2SecureBootVectAddr), &(pOBInit->C2BootRegion));
00418 }
00419
00420 /**
00421   * @brief  Flash Empty check
00422   * @note   This API checks if first location in Flash is programmed or not.
00423   *         This check is done once by Option Byte Loader.
00424   * @retval Returned value can be one of the following values:
00425   *         @arg @ref FLASH_PROG_NOT_EMPTY 1st location in Flash is programmed
00426   *         @arg @ref FLASH_PROG_EMPTY 1st location in Flash is empty
00427   */
00428 uint32_t HAL_FLASHEx_FlashEmptyCheck(void)
00429 {
00430   return (READ_BIT(FLASH->ACR, FLASH_ACR_EMPTY));
00431 }
00432
00433
00434 /**
00435   * @brief  Force Empty check value.
00436   * @note   Allows to modify program empty check value in order to force this
00437   *         information in Flash Interface, for all next reset that do not launch
00438   *         Option Byte Loader.
00439   * @param  FlashEmpty Specifies the empty check value
00440   *          This parameter can be one of the following values:
00441   *            @arg @ref FLASH_PROG_NOT_EMPTY 1st location in Flash is programmed
00442   *            @arg @ref FLASH_PROG_EMPTY 1st location in Flash is empty
00443   * @retval None
00444   */
00445 void HAL_FLASHEx_ForceFlashEmpty(uint32_t FlashEmpty)
00446 {
00447   assert_param(IS_FLASH_EMPTY_CHECK(FlashEmpty));
00448
00449   MODIFY_REG(FLASH->ACR, FLASH_ACR_EMPTY, FlashEmpty);
00450 }
00451
00452 /**
00453   * @brief  Suspend new program or erase operation request.
00454   * @note   Any new Flash program and erase operation on both CPU side will be suspended
00455   *         until this bit and the same bit in Flash CPU2 access control register (FLASH_C2ACR) are
00456   *         cleared. The PESD bit in both the Flash status register (FLASH_SR) and Flash
00457   *         CPU2 status register (FLASH_C2SR) register will be set when at least one PES
00458   *         bit in FLASH_ACR or FLASH_C2ACR is set.
00459   * @retval None
00460   */
00461 void HAL_FLASHEx_SuspendOperation(void)
00462 {
00463   SET_BIT(FLASH->ACR, FLASH_ACR_PES);
00464 }
00465
00466 /**
00467   * @brief  Allow new program or erase operation request.
00468   * @note   Any new Flash program and erase operation on both CPU side will be allowed
00469   *         until one of this bit or the same bit in Flash CPU2 access control register (FLASH_C2ACR) is
00470   *         set. The PESD bit in both the Flash status register (FLASH_SR) and Flash
00471   *         CPU2 status register (FLASH_C2SR) register will be clear when both PES
00472   *         bit in FLASH_ACR or FLASH_C2ACR is cleared.
00473   * @retval None
00474   */
00475 void HAL_FLASHEx_AllowOperation(void)
00476 {
00477   CLEAR_BIT(FLASH->ACR, FLASH_ACR_PES);
00478 }
00479
00480 /**
00481   * @brief  Check if new program or erase operation request from CPU1 or CPU2 is suspended
00482   * @note   Any new Flash program and erase operation on both CPU side will be allowed
00483   *         until one of this bit or the same bit in Flash CPU2 access control register (FLASH_C2ACR) is
00484   *         set. The PESD bit in both the Flash status register (FLASH_SR) and Flash
00485   *         CPU2 status register (FLASH_C2SR) register will be cleared when both PES
00486   *         bit in FLASH_ACR and FLASH_C2ACR are cleared.
00487   * @retval Status
00488   *          - 0 : No suspended flash operation
00489   *          - 1 : Flash operation is suspended
00490   */
00491 uint32_t HAL_FLASHEx_IsOperationSuspended(void)
00492 {
00493   uint32_t status = 0U;
00494
00495   if (READ_BIT(FLASH->SR, FLASH_SR_PESD) == FLASH_SR_PESD)
00496   {
00497     status = 1U;
00498   }
00499
00500   return status;
00501 }
00502
00503 /**
00504   * @}
00505   */
00506
00507 /**
00508   * @}
00509   */
00510
00511 /* Private functions ---------------------------------------------------------*/
00512 /** @addtogroup FLASHEx_Private_Functions
00513   * @{
00514   */
00515
00516 /**
00517   * @brief  Mass erase of FLASH memory.
00518   * @retval None
00519   */
00520 static void FLASH_MassErase(void)
00521 {
00522   /* Set the Mass Erase Bit and start bit */
00523   SET_BIT(FLASH->CR, (FLASH_CR_MER | FLASH_CR_STRT));
00524 }
00525
00526 /**
00527   * @brief  Erase the specified FLASH memory page.
00528   * @param  Page FLASH page to erase
00529   *         This parameter must be a value between 0 and (max number of pages in Flash - 1)
00530   * @retval None
00531   */
00532 void FLASH_PageErase(uint32_t Page)
00533 {
00534   /* Check the parameters */
00535   assert_param(IS_FLASH_PAGE(Page));
00536
00537   /* Proceed to erase the page */
00538   MODIFY_REG(FLASH->CR, FLASH_CR_PNB, ((Page << FLASH_CR_PNB_Pos) | FLASH_CR_PER | FLASH_CR_STRT));
00539 }
00540
00541 /**
00542   * @brief  Flush the instruction and data caches.
00543   * @retval None
00544   */
00545 static void FLASH_FlushCaches(void)
00546 {
00547   /* Flush instruction cache  */
00548   if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) == FLASH_ACR_ICEN)
00549   {
00550     /* Disable instruction cache  */
00551     __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
00552     /* Reset instruction cache */
00553     __HAL_FLASH_INSTRUCTION_CACHE_RESET();
00554     /* Enable instruction cache */
00555     __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
00556   }
00557
00558   /* Flush data cache */
00559   if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) == FLASH_ACR_DCEN)
00560   {
00561     /* Disable data cache  */
00562     __HAL_FLASH_DATA_CACHE_DISABLE();
00563     /* Reset data cache */
00564     __HAL_FLASH_DATA_CACHE_RESET();
00565     /* Enable data cache */
00566     __HAL_FLASH_DATA_CACHE_ENABLE();
00567   }
00568 }
00569
00570 /**
00571   * @brief  Acknlowldge the page erase operation.
00572   * @retval None
00573   */
00574 static void FLASH_AcknowledgePageErase(void)
00575 {
00576   CLEAR_BIT(FLASH->CR, (FLASH_CR_PER | FLASH_CR_PNB));
00577 }
00578
00579 /**
00580   * @brief  Configure the write protection of the desired pages.
00581   * @note   When WRP is active in a zone, it cannot be erased or programmed.
00582   *         Consequently, a software mass erase cannot be performed if one zone
00583   *         is write-protected.
00584   * @note   When the memory read protection level is selected (RDP level = 1),
00585   *         it is not possible to program or erase Flash memory if the CPU debug
00586   *         features are connected (JTAG or single wire) or boot code is being
00587   *         executed from RAM or System flash, even if WRP is not activated.
00588   * @note   To configure the WRP options, the option lock bit OPTLOCK must be
00589   *         cleared with the call of the @ref HAL_FLASH_OB_Unlock() function.
00590   * @note   To validate the WRP options, the option bytes must be reloaded
00591   *         through the call of the @ref HAL_FLASH_OB_Launch() function.
00592   * @param  WRPArea Specifies the area to be configured.
00593   *          This parameter can be one of the following values:
00594   *            @arg @ref OB_WRPAREA_BANK1_AREAA Flash Bank 1 Area A
00595   *            @arg @ref OB_WRPAREA_BANK1_AREAB Flash Bank 1 Area B
00596   * @param  WRPStartOffset Specifies the start page of the write protected area
00597   *          This parameter can be page number between 0 and (max number of pages in the Flash - 1)
00598   * @param  WRDPEndOffset Specifies the end page of the write protected area
00599   *          This parameter can be page number between WRPStartOffset and (max number of pages in the Flash - 1)
00600   * @retval None
00601   */
00602 static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset)
00603 {
00604   /* Check the parameters */
00605   assert_param(IS_OB_WRPAREA(WRPArea));
00606   assert_param(IS_FLASH_PAGE(WRPStartOffset));
00607   assert_param(IS_FLASH_PAGE(WRDPEndOffset));
00608
00609   /* Configure the write protected area */
00610   if (WRPArea == OB_WRPAREA_BANK1_AREAA)
00611   {
00612     MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END),
00613                (WRPStartOffset | (WRDPEndOffset << FLASH_WRP1AR_WRP1A_END_Pos)));
00614   }
00615   else /* OB_WRPAREA_BANK1_AREAB */
00616   {
00617     MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END),
00618                (WRPStartOffset | (WRDPEndOffset << FLASH_WRP1AR_WRP1A_END_Pos)));
00619   }
00620 }
00621
00622 /**
00623   * @brief  Set user & RDP configuration
00624   * @note   !!! Warning : When enabling OB_RDP level 2 it's no more possible
00625   *         to go back to level 1 or 0 !!!
00626   * @param  UserType The FLASH User Option Bytes to be modified
00627   *         This parameter can be a combination of all the following values:
00628   *         @arg @ref OB_USER_BOR_LEV or @ref OB_USER_nRST_STOP or @ref OB_USER_nRST_STDBY or
00629   *         @arg @ref OB_USER_nRST_SHDW or @ref OB_USER_IWDG_SW or @ref OB_USER_IWDG_STOP or
00630   *         @arg @ref OB_USER_IWDG_STDBY or @ref OB_USER_WWDG_SW or @ref OB_USER_nBOOT1 or
00631   *         @arg @ref OB_USER_SRAM2PE or @ref OB_USER_SRAM2RST or @ref OB_USER_nSWBOOT0 or
00632   *         @arg @ref OB_USER_nBOOT0 or @ref OB_USER_AGC_TRIM or @ref OB_USER_ALL
00633   * @param  UserConfig The FLASH User Option Bytes values.
00634   *         This parameter can be a combination of all the following values:
00635   *         @arg @ref OB_BOR_LEVEL_0 or @ref OB_BOR_LEVEL_1 or ... or @ref OB_BOR_LEVEL_4
00636   *         @arg @ref OB_STOP_RST or @ref OB_STOP_NORST
00637   *         @arg @ref OB_STANDBY_RST or @ref OB_STANDBY_NORST
00638   *         @arg @ref OB_SHUTDOWN_RST or @ref OB_SHUTDOWN_NORST
00639   *         @arg @ref OB_IWDG_SW or @ref OB_IWDG_HW
00640   *         @arg @ref OB_IWDG_STOP_FREEZE or @ref OB_IWDG_STOP_RUN
00641   *         @arg @ref OB_IWDG_STDBY_FREEZE or @ref OB_IWDG_STDBY_RUN
00642   *         @arg @ref OB_WWDG_SW or @ref OB_WWDG_HW
00643   *         @arg @ref OB_BOOT1_SRAM or @ref OB_BOOT1_SYSTEM
00644   *         @arg @ref OB_SRAM2_PARITY_ENABLE or @ref OB_SRAM2_PARITY_DISABLE
00645   *         @arg @ref OB_SRAM2_RST_ERASE or @ref OB_SRAM2_RST_NOT_ERASE
00646   *         @arg @ref OB_BOOT0_FROM_OB or @ref OB_BOOT0_FROM_PIN
00647   *         @arg @ref OB_BOOT0_RESET or @ref OB_BOOT0_SET
00648   *         @arg @ref OB_AGC_TRIM_0 or @ref OB_AGC_TRIM_1 or ... or @ref OB_AGC_TRIM_7
00649   * @param  RDPLevel: specifies the read protection level.
00650   *         This parameter can be one of the following values:
00651   *            @arg @ref OB_RDP_LEVEL_0 No protection
00652   *            @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
00653   *            @arg @ref OB_RDP_LEVEL_2 Full chip protection
00654   * @retval None
00655   */
00656 static void FLASH_OB_OptrConfig(uint32_t UserType, uint32_t UserConfig, uint32_t RDPLevel)
00657 {
00658   uint32_t optr;
00659
00660   /* Check the parameters */
00661   assert_param(IS_OB_USER_TYPE(UserType));
00662   assert_param(IS_OB_USER_CONFIG(UserType, UserConfig));
00663   assert_param(IS_OB_RDP_LEVEL(RDPLevel));
00664
00665   /* Configure the RDP level in the option bytes register */
00666   optr = FLASH->OPTR;
00667   optr &= ~(UserType | FLASH_OPTR_RDP);
00668   FLASH->OPTR = (optr | UserConfig | RDPLevel);
00669 }
00670
00671 /**
00672   * @brief  Configure the Zone 1A Proprietary code readout protection of the desired addresses,
00673   *         and erase configuration on RDP regression.
00674   * @note   To configure the PCROP options, the option lock bit OPTLOCK must be
00675   *         cleared with the call of the @ref HAL_FLASH_OB_Unlock() function.
00676   * @note   To validate the PCROP options, the option bytes must be reloaded
00677   *         through the call of the @ref HAL_FLASH_OB_Launch() function.
00678   * @param  PCROPConfig: specifies the erase configuration (OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE)
00679   *         on RDP level 1 regression.
00680   * @param  PCROP1AStartAddr Specifies the Zone 1A Start address of the Proprietary code readout protection
00681   *         This parameter can be an address between begin and end of the flash
00682   * @param  PCROP1AEndAddr Specifies the Zone 1A end address of the Proprietary code readout protection
00683   *         This parameter can be an address between PCROP1AStartAddr and end of the flash
00684   * @retval None
00685   */
00686 static void FLASH_OB_PCROP1AConfig(uint32_t PCROPConfig, uint32_t PCROP1AStartAddr, uint32_t PCROP1AEndAddr)
00687 {
00688   uint32_t startoffset;
00689   uint32_t endoffset;
00690   uint32_t pcrop1aend;
00691
00692   /* Check the parameters */
00693   assert_param(IS_OB_PCROP_CONFIG(PCROPConfig));
00694   assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROP1AStartAddr));
00695   assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROP1AEndAddr));
00696
00697   /* get pcrop 1A end register */
00698   pcrop1aend = FLASH->PCROP1AER;
00699
00700   /* Configure the Proprietary code readout protection offset */
00701   if ((PCROPConfig & OB_PCROP_ZONE_A) != 0U)
00702   {
00703     /* Compute offset depending on pcrop granularity */
00704     startoffset = ((PCROP1AStartAddr - FLASH_BASE) >> FLASH_PCROP_GRANULARITY_OFFSET); /* 2K pages */
00705     endoffset = ((PCROP1AEndAddr - FLASH_BASE) >> FLASH_PCROP_GRANULARITY_OFFSET); /* 2K pages */
00706
00707     /* Set Zone A start offset */
00708     WRITE_REG(FLASH->PCROP1ASR, startoffset);
00709
00710     /* Set Zone A end offset */
00711     pcrop1aend &= ~FLASH_PCROP1AER_PCROP1A_END;
00712     pcrop1aend |= endoffset;
00713   }
00714
00715   /* Set RDP erase protection if needed. This bit is only set & will be reset by mass erase */
00716   if ((PCROPConfig & OB_PCROP_RDP_ERASE) != 0U)
00717   {
00718     pcrop1aend |= FLASH_PCROP1AER_PCROP_RDP;
00719   }
00720
00721   /* set 1A End register */
00722   WRITE_REG(FLASH->PCROP1AER, pcrop1aend);
00723 }
00724
00725 /**
00726   * @brief  Configure the Zone 1B Proprietary code readout protection of the desired addresses.
00727   * @note   To configure the PCROP options, the option lock bit OPTLOCK must be
00728   *         cleared with the call of the @ref HAL_FLASH_OB_Unlock() function.
00729   * @note   To validate the PCROP options, the option bytes must be reloaded
00730   *         through the call of the @ref HAL_FLASH_OB_Launch() function.
00731   * @param  PCROP1BStartAddr Specifies the Zone 1BStart address of the Proprietary code readout protection
00732   *         This parameter can be an address between begin and end of the flash
00733   * @param  PCROP1BEndAddr Specifies the Zone 1B end address of the Proprietary code readout protection
00734   *         This parameter can be an address between PCROP1BStartAddr and end of the flash
00735   * @retval None
00736   */
00737 static void FLASH_OB_PCROP1BConfig(uint32_t PCROP1BStartAddr, uint32_t PCROP1BEndAddr)
00738 {
00739   uint32_t startoffset;
00740   uint32_t endoffset;
00741
00742   /* Check the parameters */
00743   assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROP1BStartAddr));
00744   assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROP1BEndAddr));
00745
00746   /* Compute offset depending on pcrop granularity */
00747   startoffset = ((PCROP1BStartAddr - FLASH_BASE) >> FLASH_PCROP_GRANULARITY_OFFSET); /* 2K pages */
00748   endoffset = ((PCROP1BEndAddr - FLASH_BASE) >> FLASH_PCROP_GRANULARITY_OFFSET); /* 2K pages */
00749
00750   /* Configure the Proprietary code readout protection start address */
00751   WRITE_REG(FLASH->PCROP1BSR, startoffset);
00752
00753   /* Configure the Proprietary code readout protection end address */
00754   WRITE_REG(FLASH->PCROP1BER, endoffset);
00755 }
00756
00757 /**
00758   * @brief  Program the FLASH IPCC data buffer address.
00759   * @note   To configure the extra user option bytes, the option lock bit OPTLOCK must
00760   *         be cleared with the call of the @ref HAL_FLASH_OB_Unlock() function.
00761   * @note   To validate the extra user option bytes, the option bytes must be reloaded
00762   *         through the call of the @ref HAL_FLASH_OB_Launch() function.
00763   * @param  IPCCDataBufAddr IPCC data buffer start address area in SRAM2
00764   *         This parameter must be the double-word aligned
00765   * @retval None
00766   */
00767 static void FLASH_OB_IPCCBufferAddrConfig(uint32_t IPCCDataBufAddr)
00768 {
00769   assert_param(IS_OB_IPCC_BUF_ADDR(IPCCDataBufAddr));
00770
00771   /* Configure the option bytes register */
00772   WRITE_REG(FLASH->IPCCBR, (uint32_t)((IPCCDataBufAddr - SRAM2A_BASE) >> 4));
00773 }
00774
00775 /**
00776   * @brief  Configure the secure start address of the different memories (FLASH and SRAM2),
00777   *         the secure mode and the CPU2 Secure Boot reset vector
00778   * @note   To configure the PCROP options, the option lock bit OPTLOCK must be
00779   *         cleared with the call of the @ref HAL_FLASH_OB_Unlock() function.
00780   * @param  pOBParam Pointer to an @ref FLASH_OBProgramInitTypeDef structure that
00781   *         contains the configuration information for the programming
00782   * @retval void
00783   */
00784 static void FLASH_OB_SecureConfig(FLASH_OBProgramInitTypeDef *pOBParam)
00785 {
00786   uint32_t sfr_reg_val = READ_REG(FLASH->SFR);
00787   uint32_t srrvr_reg_val = READ_REG(FLASH->SRRVR);
00788
00789   if ((pOBParam->OptionType & OPTIONBYTE_SECURE_MODE) != 0U)
00790   {
00791     assert_param(IS_OB_SFSA_START_ADDR(pOBParam->SecureFlashStartAddr));
00792     assert_param(IS_OB_SBRSA_START_ADDR(pOBParam->SecureRAM2aStartAddr));
00793     assert_param(IS_OB_SNBRSA_START_ADDR(pOBParam->SecureRAM2bStartAddr));
00794     assert_param(IS_OB_SECURE_MODE(pOBParam->SecureMode));
00795
00796     /* Configure SFR register content with start PAGE index to secure */
00797     MODIFY_REG(sfr_reg_val, FLASH_SFR_SFSA, (((pOBParam->SecureFlashStartAddr - FLASH_BASE) / FLASH_PAGE_SIZE) << FLASH_SFR_SFSA_Pos));
00798
00799     /* Configure SRRVR register */
00800     MODIFY_REG(srrvr_reg_val, (FLASH_SRRVR_SBRSA | FLASH_SRRVR_SNBRSA), \
00801                (((((pOBParam->SecureRAM2aStartAddr - SRAM2A_BASE) >> SRAM_SECURE_PAGE_GRANULARITY_OFFSET) << FLASH_SRRVR_SBRSA_Pos)) | \
00802                 ((((pOBParam->SecureRAM2bStartAddr - SRAM2B_BASE) >> SRAM_SECURE_PAGE_GRANULARITY_OFFSET) << FLASH_SRRVR_SNBRSA_Pos))));
00803
00804     /* If Full System Secure mode is requested, clear all the corresponding bit */
00805     /* Else set the corresponding bit */
00806     if (pOBParam->SecureMode == SYSTEM_IN_SECURE_MODE)
00807     {
00808       CLEAR_BIT(sfr_reg_val, FLASH_SFR_FSD);
00809       CLEAR_BIT(srrvr_reg_val, (FLASH_SRRVR_BRSD | FLASH_SRRVR_NBRSD));
00810     }
00811     else
00812     {
00813       SET_BIT(sfr_reg_val, FLASH_SFR_FSD);
00814       SET_BIT(srrvr_reg_val, (FLASH_SRRVR_BRSD | FLASH_SRRVR_NBRSD));
00815     }
00816
00817     /* Update Flash registers */
00818     WRITE_REG(FLASH->SFR, sfr_reg_val);
00819   }
00820
00821   /* Boot vector */
00822   if ((pOBParam->OptionType & OPTIONBYTE_C2_BOOT_VECT) != 0U)
00823   {
00824     /* Check the parameters */
00825     assert_param(IS_OB_BOOT_VECTOR_ADDR(pOBParam->C2SecureBootVectAddr));
00826     assert_param(IS_OB_BOOT_REGION(pOBParam->C2BootRegion));
00827
00828     /* Set the boot vector */
00829     if (pOBParam->C2BootRegion == OB_C2_BOOT_FROM_FLASH)
00830     {
00831       MODIFY_REG(srrvr_reg_val, (FLASH_SRRVR_SBRV | FLASH_SRRVR_C2OPT), (((pOBParam->C2SecureBootVectAddr - FLASH_BASE) >> 2) | pOBParam->C2BootRegion));
00832     }
00833     else
00834     {
00835       MODIFY_REG(srrvr_reg_val, (FLASH_SRRVR_SBRV | FLASH_SRRVR_C2OPT), (((pOBParam->C2SecureBootVectAddr - SRAM1_BASE) >> 2) | pOBParam->C2BootRegion));
00836     }
00837   }
00838
00839   /* Update Flash registers */
00840   WRITE_REG(FLASH->SRRVR, srrvr_reg_val);
00841 }
00842
00843 /**
00844   * @brief  Return the FLASH Write Protection Option Bytes value.
00845   * @param[in]   WRPArea Specifies the area to be returned.
00846   *              This parameter can be one of the following values:
00847   *              @arg @ref OB_WRPAREA_BANK1_AREAA Flash Bank 1 Area A
00848   *              @arg @ref OB_WRPAREA_BANK1_AREAB Flash Bank 1 Area B
00849   * @param[out]  WRPStartOffset Specifies the address where to copied the start page
00850   *                             of the write protected area
00851   * @param[out]  WRDPEndOffset Specifies the address where to copied the end page of
00852   *                            the write protected area
00853   * @retval None
00854   */
00855 static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRDPEndOffset)
00856 {
00857   /* Check the parameters */
00858   assert_param(IS_OB_WRPAREA(WRPArea));
00859
00860   /* Get the configuration of the write protected area */
00861   if (WRPArea == OB_WRPAREA_BANK1_AREAA)
00862   {
00863     *WRPStartOffset = READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_STRT);
00864     *WRDPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_END) >> FLASH_WRP1AR_WRP1A_END_Pos);
00865   }
00866   else /* OB_WRPAREA_BANK1_AREAB */
00867   {
00868     *WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_STRT);
00869     *WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >> FLASH_WRP1BR_WRP1B_END_Pos);
00870   }
00871 }
00872
00873 /**
00874   * @brief  Return the FLASH Read Protection level.
00875   * @retval FLASH ReadOut Protection Status:
00876   *         This return value can be one of the following values:
00877   *            @arg @ref OB_RDP_LEVEL_0 No protection
00878   *            @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
00879   *            @arg @ref OB_RDP_LEVEL_2 Full chip protection
00880   */
00881 static uint32_t FLASH_OB_GetRDP(void)
00882 {
00883   uint32_t rdplvl = READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP);
00884
00885   if ((rdplvl != OB_RDP_LEVEL_0) && (rdplvl != OB_RDP_LEVEL_2))
00886   {
00887     return (OB_RDP_LEVEL_1);
00888   }
00889   else
00890   {
00891     return rdplvl;
00892   }
00893 }
00894
00895 /**
00896   * @brief  Return the FLASH User Option Byte value.
00897   * @retval This return value can be a combination of all the following values:
00898   *         @arg @ref OB_BOR_LEVEL_0 or @ref OB_BOR_LEVEL_1 or ... or @ref OB_BOR_LEVEL_4
00899   *         @arg @ref OB_STOP_RST or @ref OB_STOP_RST
00900   *         @arg @ref OB_STANDBY_RST or @ref OB_STANDBY_NORST
00901   *         @arg @ref OB_SHUTDOWN_RST or @ref OB_SHUTDOWN_NORST
00902   *         @arg @ref OB_IWDG_SW or @ref OB_IWDG_HW
00903   *         @arg @ref OB_IWDG_STOP_FREEZE or @ref OB_IWDG_STOP_RUN
00904   *         @arg @ref OB_IWDG_STDBY_FREEZE or @ref OB_IWDG_STDBY_RUN
00905   *         @arg @ref OB_WWDG_SW or @ref OB_WWDG_HW
00906   *         @arg @ref OB_BOOT1_SRAM or @ref OB_BOOT1_SYSTEM
00907   *         @arg @ref OB_SRAM2_PARITY_ENABLE or @ref OB_SRAM2_PARITY_DISABLE
00908   *         @arg @ref OB_SRAM2_RST_ERASE or @ref OB_SRAM2_RST_NOT_ERASE
00909   *         @arg @ref OB_BOOT0_FROM_OB or @ref OB_BOOT0_FROM_PIN
00910   *         @arg @ref OB_BOOT0_RESET or @ref OB_BOOT0_SET
00911   *         @arg @ref OB_AGC_TRIM_0 or @ref OB_AGC_TRIM_1 or ... or @ref OB_AGC_TRIM_7
00912   */
00913 static uint32_t FLASH_OB_GetUser(void)
00914 {
00915   uint32_t user_config = (READ_REG(FLASH->OPTR) & OB_USER_ALL);
00916   CLEAR_BIT(user_config, (FLASH_OPTR_RDP | FLASH_OPTR_ESE));
00917
00918   return user_config;
00919 }
00920
00921 /**
00922   * @brief  Return the FLASH Write Protection Option Bytes value.
00923   * @param PCROPConfig [out] Specifies the address where to copied the configuration of PCROP_RDP option
00924   * @param PCROP1AStartAddr [out] Specifies the address where to copied the start address
00925   *                         of the Zone 1A Proprietary code readout protection
00926   * @param PCROP1AEndAddr [out] Specifies the address where to copied the end address of
00927   *                       the Zone 1A Proprietary code readout protection
00928   * @param PCROP1BStartAddr [out] Specifies the address where to copied the start address
00929   *                         of the Zone 1B Proprietary code readout protection
00930   * @param PCROP1BEndAddr [out] Specifies the address where to copied the end address of
00931   *                       the Zone 1B Proprietary code readout protection
00932   * @retval None
00933   */
00934 static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROP1AStartAddr, uint32_t *PCROP1AEndAddr, uint32_t *PCROP1BStartAddr, uint32_t *PCROP1BEndAddr)
00935 {
00936   uint32_t pcrop;
00937
00938   pcrop             = (READ_BIT(FLASH->PCROP1BSR, FLASH_PCROP1BSR_PCROP1B_STRT));
00939   *PCROP1BStartAddr = ((pcrop << FLASH_PCROP_GRANULARITY_OFFSET) + FLASH_BASE);
00940
00941   pcrop             = (READ_BIT(FLASH->PCROP1BER, FLASH_PCROP1BER_PCROP1B_END));
00942   *PCROP1BEndAddr   = ((pcrop << FLASH_PCROP_GRANULARITY_OFFSET) + FLASH_BASE);
00943
00944   pcrop             = (READ_BIT(FLASH->PCROP1ASR, FLASH_PCROP1ASR_PCROP1A_STRT));
00945   *PCROP1AStartAddr = ((pcrop << FLASH_PCROP_GRANULARITY_OFFSET) + FLASH_BASE);
00946
00947   pcrop             = (READ_BIT(FLASH->PCROP1AER, FLASH_PCROP1AER_PCROP1A_END));
00948   *PCROP1AEndAddr   = ((pcrop << FLASH_PCROP_GRANULARITY_OFFSET) + FLASH_BASE);
00949
00950   *PCROPConfig      = (READ_REG(FLASH->PCROP1AER) & FLASH_PCROP1AER_PCROP_RDP);
00951 }
00952
00953 /**
00954   * @brief  Return the FLASH IPCC data buffer base address Option Byte value.
00955   * @retval Returned value is the IPCC data buffer start address area in SRAM2.
00956   */
00957 static uint32_t FLASH_OB_GetIPCCBufferAddr(void)
00958 {
00959   return (uint32_t)((READ_BIT(FLASH->IPCCBR, FLASH_IPCCBR_IPCCDBA) << 4) + SRAM2A_BASE);
00960 }
00961
00962 /**
00963   * @brief  Return the Secure Flash start address, Secure Backup RAM2a start address, Secure non-Backup RAM2b start address and the SecureMode
00964   * @param  SecureFlashStartAddr Specifies the address where to copied the Secure Flash start address
00965   * @param  SecureRAM2aStartAddr Specifies the address where to copied the Secure Backup RAM2a start address
00966   * @param  SecureRAM2bStartAddr Specifies the address where to copied the Secure non-Backup RAM2b start address
00967   * @param  SecureMode           Specifies the address where to copied the Secure Mode.
00968   *                              This return value can be one of the following values:
00969   *                              @arg @ref SYSTEM_IN_SECURE_MODE : Security enabled
00970   *                              @arg @ref SYSTEM_NOT_IN_SECURE_MODE : Security disabled
00971   * @retval None
00972   */
00973 static void FLASH_OB_GetSecureMemoryConfig(uint32_t *SecureFlashStartAddr, uint32_t *SecureRAM2aStartAddr, uint32_t *SecureRAM2bStartAddr, uint32_t *SecureMode)
00974 {
00975   uint32_t sfr_reg_val = READ_REG(FLASH->SFR);
00976   uint32_t srrvr_reg_val = READ_REG(FLASH->SRRVR);
00977
00978   /* Get Secure Flash start address */
00979   uint32_t user_config = (READ_BIT(sfr_reg_val, FLASH_SFR_SFSA) >> FLASH_SFR_SFSA_Pos);
00980
00981   *SecureFlashStartAddr = ((user_config * FLASH_PAGE_SIZE) + FLASH_BASE);
00982
00983   /* Get Secure SRAM2a start address */
00984   user_config = (READ_BIT(srrvr_reg_val, FLASH_SRRVR_SBRSA) >> FLASH_SRRVR_SBRSA_Pos);
00985
00986   *SecureRAM2aStartAddr = ((user_config << SRAM_SECURE_PAGE_GRANULARITY_OFFSET) + SRAM2A_BASE);
00987
00988   /* Get Secure SRAM2b start address */
00989   user_config = (READ_BIT(srrvr_reg_val, FLASH_SRRVR_SNBRSA) >> FLASH_SRRVR_SNBRSA_Pos);
00990
00991   *SecureRAM2bStartAddr = ((user_config << SRAM_SECURE_PAGE_GRANULARITY_OFFSET) + SRAM2B_BASE);
00992
00993   /* Get Secure Area mode */
00994   *SecureMode = (READ_BIT(FLASH->OPTR, FLASH_OPTR_ESE));
00995 }
00996
00997 /**
00998   * @brief  Return the CPU2 Secure Boot reset vector address and the CPU2 Secure Boot Region
00999   * @param  C2BootResetVectAddr Specifies the address where to copied the CPU2 Secure Boot reset vector address
01000   * @param  C2BootResetRegion   Specifies the Secure Boot reset memory region
01001   * @retval None
01002   */
01003 static void FLASH_OB_GetC2BootResetConfig(uint32_t *C2BootResetVectAddr, uint32_t *C2BootResetRegion)
01004 {
01005   *C2BootResetRegion = (READ_BIT(FLASH->SRRVR, FLASH_SRRVR_C2OPT));
01006
01007   if (*C2BootResetRegion == OB_C2_BOOT_FROM_FLASH)
01008   {
01009     *C2BootResetVectAddr = (uint32_t)((READ_BIT(FLASH->SRRVR, FLASH_SRRVR_SBRV) << 2) + FLASH_BASE);
01010   }
01011   else
01012   {
01013     *C2BootResetVectAddr = (uint32_t)((READ_BIT(FLASH->SRRVR, FLASH_SRRVR_SBRV) << 2) + SRAM1_BASE);
01014   }
01015 }
01016
01017 /**
01018   * @brief  Proceed the OB Write Operation.
01019   * @retval HAL Status
01020   */
01021 static HAL_StatusTypeDef FLASH_OB_ProceedWriteOperation(void)
01022 {
01023   HAL_StatusTypeDef status;
01024
01025   /* Verify that next operation can be proceed */
01026   status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
01027
01028   if (status == HAL_OK)
01029   {
01030     /* Set OPTSTRT Bit */
01031     SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
01032
01033     /* Wait for last operation to be completed */
01034     status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
01035   }
01036
01037   return status;
01038 }
01039
01040 /**
01041   * @}
01042   */
01043
01044 /**
01045   * @}
01046   */
01047
01048 #endif /* HAL_FLASH_MODULE_ENABLED */
01049
01050 /**
01051   * @}
01052   */
01053
01054 /**
01055   * @}
01056   */
01057
01058 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_flash_ex.h Source File

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stm32wbxx_hal_flash_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_flash_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of FLASH HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_FLASH_EX_H
00022 #define STM32WBxx_HAL_FLASH_EX_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 /** @addtogroup STM32WBxx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup FLASHEx
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /* Exported constants --------------------------------------------------------*/
00041 /** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
00042   * @{
00043   */
00044 /** @defgroup FLASHEx_EMPTY_CHECK FLASHEx Empty Check
00045   * @{
00046   */
00047 #define FLASH_PROG_NOT_EMPTY            0x00000000U     /*!< 1st location in Flash is programmed */
00048 #define FLASH_PROG_EMPTY                FLASH_ACR_EMPTY /*!< 1st location in Flash is empty      */
00049 /**
00050   * @}
00051   */
00052 /**
00053   * @}
00054   */
00055
00056 /* Exported macro ------------------------------------------------------------*/
00057 /* Exported functions --------------------------------------------------------*/
00058 /** @addtogroup FLASHEx_Exported_Functions
00059   * @{
00060   */
00061
00062 /* Extended Program operation functions  *************************************/
00063 /** @addtogroup FLASHEx_Exported_Functions_Group1
00064   * @{
00065   */
00066 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
00067 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
00068 uint32_t          HAL_FLASHEx_FlashEmptyCheck(void);
00069 void              HAL_FLASHEx_ForceFlashEmpty(uint32_t FlashEmpty);
00070 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
00071 void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
00072 void              HAL_FLASHEx_SuspendOperation(void);
00073 void              HAL_FLASHEx_AllowOperation(void);
00074 uint32_t          HAL_FLASHEx_IsOperationSuspended(void);
00075 /**
00076   * @}
00077   */
00078
00079 /**
00080   * @}
00081   */
00082
00083 /* Private macros ------------------------------------------------------------*/
00084 /** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros
00085   *  @{
00086   */
00087 #define IS_FLASH_EMPTY_CHECK(__VALUE__)     (((__VALUE__) == FLASH_PROG_EMPTY) || ((__VALUE__) == FLASH_PROG_NOT_EMPTY))
00088 /**
00089   * @}
00090   */
00091
00092 /* Private Functions ---------------------------------------------------------*/
00093 /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
00094   * @{
00095   */
00096 void              FLASH_PageErase(uint32_t Page);
00097 /**
00098   * @}
00099   */
00100
00101 /**
00102   * @}
00103   */
00104
00105 /**
00106   * @}
00107   */
00108
00109 #ifdef __cplusplus
00110 }
00111 #endif
00112
00113 #endif /* STM32WBxx_HAL_FLASH_EX_H */
00114
00115 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_gpio.c Source File

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stm32wbxx_hal_gpio.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_gpio.c
00004   * @author  MCD Application Team
00005   * @brief   GPIO HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *
00011   @verbatim
00012   ==============================================================================
00013                     ##### GPIO Peripheral features #####
00014   ==============================================================================
00015   [..]
00016     (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
00017         configured by software in several modes:
00018         (++) Input mode
00019         (++) Analog mode
00020         (++) Output mode
00021         (++) Alternate function mode
00022         (++) External interrupt/event lines
00023
00024     (+) During and just after reset, the alternate functions and external interrupt
00025         lines are not active and the I/O ports are configured in input floating mode.
00026
00027     (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
00028         activated or not.
00029
00030     (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
00031         type and the IO speed can be selected depending on the VDD value.
00032
00033     (+) The microcontroller IO pins are connected to onboard peripherals/modules through a
00034         multiplexer that allows only one peripheral alternate function (AF) connected
00035        to an IO pin at a time. In this way, there can be no conflict between peripherals
00036        sharing the same IO pin.
00037
00038     (+) All ports have external interrupt/event capability. To use external interrupt
00039         lines, the port must be configured in input mode. All available GPIO pins are
00040         connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
00041
00042     (+) The external interrupt/event controller consists of up to 28 edge detectors
00043         (16 lines are connected to GPIO) for generating event/interrupt requests (each
00044         input line can be independently configured to select the type (interrupt or event)
00045         and the corresponding trigger event (rising or falling or both). Each line can
00046         also be masked independently.
00047
00048                      ##### How to use this driver #####
00049   ==============================================================================
00050   [..]
00051     (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
00052
00053     (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
00054         (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
00055         (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
00056              structure.
00057         (++) In case of Output or alternate function mode selection: the speed is
00058              configured through "Speed" member from GPIO_InitTypeDef structure.
00059         (++) In alternate mode is selection, the alternate function connected to the IO
00060              is configured through "Alternate" member from GPIO_InitTypeDef structure.
00061         (++) Analog mode is required when a pin is to be used as ADC channel
00062              or DAC output.
00063         (++) In case of external interrupt/event selection the "Mode" member from
00064              GPIO_InitTypeDef structure select the type (interrupt or event) and
00065              the corresponding trigger event (rising or falling or both).
00066
00067     (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
00068         mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
00069         HAL_NVIC_EnableIRQ().
00070
00071     (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
00072
00073     (#) To set/reset the level of a pin configured in output mode use
00074         HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
00075
00076    (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
00077
00078     (#) During and just after reset, the alternate functions are not
00079         active and the GPIO pins are configured in input floating mode (except JTAG
00080         pins).
00081
00082     (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
00083         (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
00084         priority over the GPIO function.
00085
00086     (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
00087         general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
00088         The HSE has priority over the GPIO function.
00089
00090   @endverbatim
00091   ******************************************************************************
00092   * @attention
00093   *
00094   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00095   * All rights reserved.</center></h2>
00096   *
00097   * This software component is licensed by ST under BSD 3-Clause license,
00098   * the "License"; You may not use this file except in compliance with the
00099   * License. You may obtain a copy of the License at:
00100   *                        opensource.org/licenses/BSD-3-Clause
00101   *
00102   ******************************************************************************
00103   */
00104
00105 /* Includes ------------------------------------------------------------------*/
00106 #include "stm32wbxx_hal.h"
00107
00108 /** @addtogroup STM32WBxx_HAL_Driver
00109   * @{
00110   */
00111
00112 /** @addtogroup GPIO
00113   * @{
00114   */
00115 /** MISRA C:2012 deviation rule has been granted for following rules:
00116   * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of
00117   * range of the shift operator in following API :
00118   * HAL_GPIO_Init
00119   * HAL_GPIO_DeInit
00120   */
00121
00122 #ifdef HAL_GPIO_MODULE_ENABLED
00123
00124 /* Private typedef -----------------------------------------------------------*/
00125 /* Private defines ------------------------------------------------------------*/
00126 /** @defgroup GPIO_Private_Constants GPIO Private Constants
00127   * @{
00128   */
00129 #define GPIO_MODE             (0x00000003u)
00130 #define EXTI_MODE             (0x10000000u)
00131 #define GPIO_MODE_IT          (0x00010000u)
00132 #define GPIO_MODE_EVT         (0x00020000u)
00133 #define RISING_EDGE           (0x00100000u)
00134 #define FALLING_EDGE          (0x00200000u)
00135 #define GPIO_OUTPUT_TYPE      (0x00000010u)
00136
00137 #define GPIO_NUMBER           (16u)
00138 /**
00139   * @}
00140   */
00141
00142 /* Private macros ------------------------------------------------------------*/
00143 /* Private variables ---------------------------------------------------------*/
00144 /* Private function prototypes -----------------------------------------------*/
00145 /* Exported functions --------------------------------------------------------*/
00146
00147 /** @addtogroup GPIO_Exported_Functions
00148   * @{
00149   */
00150
00151 /** @addtogroup GPIO_Exported_Functions_Group1
00152  *  @brief    Initialization and Configuration functions
00153  *
00154 @verbatim
00155  ===============================================================================
00156               ##### Initialization and de-initialization functions #####
00157  ===============================================================================
00158
00159 @endverbatim
00160   * @{
00161   */
00162
00163 /**
00164   * @brief  Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
00165   * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32WBxx family
00166   * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
00167   *         the configuration information for the specified GPIO peripheral.
00168   * @retval None
00169   */
00170 void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
00171 {
00172   uint32_t position = 0x00u;
00173   uint32_t iocurrent;
00174   uint32_t temp;
00175
00176   /* Check the parameters */
00177   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
00178   assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
00179   assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
00180   assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
00181
00182   /* Configure the port pins */
00183   while (((GPIO_Init->Pin) >> position) != 0x00u)
00184   {
00185     /* Get current io position */
00186     iocurrent = (GPIO_Init->Pin) & (1uL << position);
00187
00188     if (iocurrent != 0x00u)
00189     {
00190       /*--------------------- GPIO Mode Configuration ------------------------*/
00191       /* In case of Alternate function mode selection */
00192       if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
00193       {
00194         /* Check the Alternate function parameters */
00195         assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
00196         assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
00197
00198         /* Configure Alternate function mapped with the current IO */
00199         temp = GPIOx->AFR[position >> 3u];
00200         temp &= ~(0xFu << ((position & 0x07u) * 4u));
00201         temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
00202         GPIOx->AFR[position >> 3u] = temp;
00203       }
00204
00205       /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
00206       temp = GPIOx->MODER;
00207       temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
00208       temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
00209       GPIOx->MODER = temp;
00210
00211       /* In case of Output or Alternate function mode selection */
00212       if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
00213          (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
00214       {
00215         /* Check the Speed parameter */
00216         assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
00217         /* Configure the IO Speed */
00218         temp = GPIOx->OSPEEDR;
00219         temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
00220         temp |= (GPIO_Init->Speed << (position * 2u));
00221         GPIOx->OSPEEDR = temp;
00222
00223         /* Configure the IO Output Type */
00224         temp = GPIOx->OTYPER;
00225         temp &= ~(GPIO_OTYPER_OT0 << position) ;
00226         temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4u) << position);
00227         GPIOx->OTYPER = temp;
00228       }
00229
00230       /* Activate the Pull-up or Pull down resistor for the current IO */
00231       temp = GPIOx->PUPDR;
00232       temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));
00233       temp |= ((GPIO_Init->Pull) << (position * 2u));
00234       GPIOx->PUPDR = temp;
00235
00236       /*--------------------- EXTI Mode Configuration ------------------------*/
00237       /* Configure the External Interrupt or event for the current IO */
00238       if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
00239       {
00240         temp = SYSCFG->EXTICR[position >> 2u];
00241         temp &= ~(0x0FuL << (4u * (position & 0x03u)));
00242         temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
00243         SYSCFG->EXTICR[position >> 2u] = temp;
00244
00245         /* Clear EXTI line configuration */
00246         temp = EXTI->IMR1;
00247         temp &= ~(iocurrent);
00248         if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
00249         {
00250           temp |= iocurrent;
00251         }
00252         EXTI->IMR1 = temp;
00253
00254         temp = EXTI->EMR1;
00255         temp &= ~(iocurrent);
00256         if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
00257         {
00258           temp |= iocurrent;
00259         }
00260         EXTI->EMR1 = temp;
00261
00262         /* Clear Rising Falling edge configuration */
00263         temp = EXTI->RTSR1;
00264         temp &= ~(iocurrent);
00265         if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
00266         {
00267           temp |= iocurrent;
00268         }
00269         EXTI->RTSR1 = temp;
00270
00271         temp = EXTI->FTSR1;
00272         temp &= ~(iocurrent);
00273         if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
00274         {
00275           temp |= iocurrent;
00276         }
00277         EXTI->FTSR1 = temp;
00278       }
00279     }
00280
00281     position++;
00282   }
00283 }
00284
00285 /**
00286   * @brief  De-initialize the GPIOx peripheral registers to their default reset values.
00287   * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32WBxx family
00288   * @param GPIO_Pin specifies the port bit to be written.
00289   *         This parameter can be one of GPIO_PIN_x where x can be (0..15).
00290   * @retval None
00291   */
00292 void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
00293 {
00294   uint32_t position = 0x00u;
00295   uint32_t iocurrent;
00296   uint32_t tmp;
00297
00298   /* Check the parameters */
00299   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
00300   assert_param(IS_GPIO_PIN(GPIO_Pin));
00301
00302   /* Configure the port pins */
00303   while ((GPIO_Pin >> position) != 0x00u)
00304   {
00305     /* Get current io position */
00306     iocurrent = (GPIO_Pin) & (1uL << position);
00307
00308     if (iocurrent != 0x00u)
00309     {
00310       /*------------------------- EXTI Mode Configuration --------------------*/
00311       /* Clear the External Interrupt or Event for the current IO */
00312
00313       tmp = SYSCFG->EXTICR[position >> 2u];
00314       tmp &= (0x0FUL << (4u * (position & 0x03u)));
00315       if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))))
00316       {
00317         tmp = 0x0FuL << (4u * (position & 0x03u));
00318         SYSCFG->EXTICR[position >> 2u] &= ~tmp;
00319
00320         /* Clear EXTI line configuration */
00321         EXTI->IMR1 &= ~(iocurrent);
00322         EXTI->EMR1 &= ~(iocurrent);
00323
00324         /* Clear Rising Falling edge configuration */
00325         EXTI->RTSR1 &= ~(iocurrent);
00326         EXTI->FTSR1 &= ~(iocurrent);
00327       }
00328
00329       /*------------------------- GPIO Mode Configuration --------------------*/
00330       /* Configure IO in Analog Mode */
00331       GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2u));
00332
00333       /* Configure the default Alternate Function in current IO */
00334       GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u)) ;
00335
00336       /* Configure the default value for IO Speed */
00337       GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
00338
00339       /* Configure the default value IO Output Type */
00340       GPIOx->OTYPER  &= ~(GPIO_OTYPER_OT0 << position) ;
00341
00342       /* Deactivate the Pull-up and Pull-down resistor for the current IO */
00343       GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));
00344     }
00345
00346     position++;
00347   }
00348 }
00349
00350 /**
00351   * @}
00352   */
00353
00354 /** @addtogroup GPIO_Exported_Functions_Group2
00355  *  @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
00356  *
00357 @verbatim
00358  ===============================================================================
00359                        ##### IO operation functions #####
00360  ===============================================================================
00361
00362 @endverbatim
00363   * @{
00364   */
00365
00366 /**
00367   * @brief  Read the specified input port pin.
00368   * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32WBxx family
00369   * @param GPIO_Pin specifies the port bit to read.
00370   *         This parameter can be GPIO_PIN_x where x can be (0..15).
00371   * @retval The input port pin value.
00372   */
00373 GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
00374 {
00375   GPIO_PinState bitstatus;
00376
00377   /* Check the parameters */
00378   assert_param(IS_GPIO_PIN(GPIO_Pin));
00379
00380   if ((GPIOx->IDR & GPIO_Pin) != 0x00u)
00381   {
00382     bitstatus = GPIO_PIN_SET;
00383   }
00384   else
00385   {
00386     bitstatus = GPIO_PIN_RESET;
00387   }
00388   return bitstatus;
00389 }
00390
00391 /**
00392   * @brief  Set or clear the selected data port bit.
00393   *
00394   * @note   This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify
00395   *         accesses. In this way, there is no risk of an IRQ occurring between
00396   *         the read and the modify access.
00397   *
00398   * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32WBxx family
00399   * @param GPIO_Pin specifies the port bit to be written.
00400   *         This parameter can be one of GPIO_PIN_x where x can be (0..15).
00401   * @param PinState specifies the value to be written to the selected bit.
00402   *         This parameter can be one of the GPIO_PinState enum values:
00403   *            @arg GPIO_PIN_RESET: to clear the port pin
00404   *            @arg GPIO_PIN_SET: to set the port pin
00405   * @retval None
00406   */
00407 void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
00408 {
00409   /* Check the parameters */
00410   assert_param(IS_GPIO_PIN(GPIO_Pin));
00411   assert_param(IS_GPIO_PIN_ACTION(PinState));
00412
00413   if(PinState != GPIO_PIN_RESET)
00414   {
00415     GPIOx->BSRR = (uint32_t)GPIO_Pin;
00416   }
00417   else
00418   {
00419     GPIOx->BRR = (uint32_t)GPIO_Pin;
00420   }
00421 }
00422
00423 /**
00424   * @brief  Toggle the specified GPIO pin.
00425   * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32WBxx family
00426   * @param GPIO_Pin specifies the pin to be toggled.
00427   * @retval None
00428   */
00429 void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
00430 {
00431   /* Check the parameters */
00432   assert_param(IS_GPIO_PIN(GPIO_Pin));
00433
00434   if ((GPIOx->ODR & GPIO_Pin) != 0x00u)
00435   {
00436     GPIOx->BRR = (uint32_t)GPIO_Pin;
00437   }
00438   else
00439   {
00440     GPIOx->BSRR = (uint32_t)GPIO_Pin;
00441   }
00442 }
00443
00444 /**
00445 * @brief  Lock GPIO Pins configuration registers.
00446   * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
00447   *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
00448   * @note   The configuration of the locked GPIO pins can no longer be modified
00449   *         until the next reset.
00450   * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32WBxx family
00451   * @param GPIO_Pin specifies the port bits to be locked.
00452   *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
00453   * @retval None
00454   */
00455 HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
00456 {
00457   __IO uint32_t tmp = GPIO_LCKR_LCKK;
00458
00459   /* Check the parameters */
00460   assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
00461   assert_param(IS_GPIO_PIN(GPIO_Pin));
00462
00463   /* Apply lock key write sequence */
00464   tmp |= GPIO_Pin;
00465   /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
00466   GPIOx->LCKR = tmp;
00467   /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
00468   GPIOx->LCKR = GPIO_Pin;
00469   /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
00470   GPIOx->LCKR = tmp;
00471   /* Read LCKK register. This read is mandatory to complete key lock sequence */
00472   tmp = GPIOx->LCKR;
00473
00474   /* read again in order to confirm lock is active */
00475   if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u)
00476   {
00477     return HAL_OK;
00478   }
00479   else
00480   {
00481     return HAL_ERROR;
00482   }
00483 }
00484
00485 /**
00486   * @brief  Handle EXTI interrupt request.
00487   * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
00488   * @retval None
00489   */
00490 void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
00491 {
00492   /* EXTI line interrupt detected */
00493   if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u)
00494   {
00495     __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
00496     HAL_GPIO_EXTI_Callback(GPIO_Pin);
00497   }
00498 }
00499
00500 /**
00501   * @brief  EXTI line detection callback.
00502   * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
00503   * @retval None
00504   */
00505 __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
00506 {
00507   /* Prevent unused argument(s) compilation warning */
00508   UNUSED(GPIO_Pin);
00509
00510   /* NOTE: This function should not be modified, when the callback is needed,
00511            the HAL_GPIO_EXTI_Callback could be implemented in the user file
00512    */
00513 }
00514
00515 /**
00516   * @}
00517   */
00518
00519
00520 /**
00521   * @}
00522   */
00523
00524 #endif /* HAL_GPIO_MODULE_ENABLED */
00525 /**
00526   * @}
00527   */
00528
00529 /**
00530   * @}
00531   */
00532
00533 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_gpio.h Source File

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stm32wbxx_hal_gpio.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_gpio.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of GPIO HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_GPIO_H
00022 #define STM32WBxx_HAL_GPIO_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 /** @addtogroup STM32WBxx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @defgroup GPIO GPIO
00036   * @brief GPIO HAL module driver
00037   * @{
00038   */
00039
00040 /* Exported types ------------------------------------------------------------*/
00041
00042 /** @defgroup GPIO_Exported_Types GPIO Exported Types
00043   * @{
00044   */
00045 /**
00046   * @brief   GPIO Init structure definition
00047   */
00048 typedef struct
00049 {
00050   uint32_t Pin;        /*!< Specifies the GPIO pins to be configured.
00051                            This parameter can be any value of @ref GPIO_pins */
00052
00053   uint32_t Mode;       /*!< Specifies the operating mode for the selected pins.
00054                            This parameter can be a value of @ref GPIO_mode */
00055
00056   uint32_t Pull;       /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
00057                            This parameter can be a value of @ref GPIO_pull */
00058
00059   uint32_t Speed;      /*!< Specifies the speed for the selected pins.
00060                            This parameter can be a value of @ref GPIO_speed */
00061
00062   uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins
00063                             This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
00064 }GPIO_InitTypeDef;
00065
00066 /**
00067   * @brief  GPIO Bit SET and Bit RESET enumeration
00068   */
00069 typedef enum
00070 {
00071   GPIO_PIN_RESET = 0U,
00072   GPIO_PIN_SET
00073 }GPIO_PinState;
00074 /**
00075   * @}
00076   */
00077
00078 /* Exported constants --------------------------------------------------------*/
00079 /** @defgroup GPIO_Exported_Constants GPIO Exported Constants
00080   * @{
00081   */
00082 /** @defgroup GPIO_pins GPIO pins
00083   * @{
00084   */
00085 #define GPIO_PIN_0                 ((uint16_t)0x0001)  /* Pin 0 selected    */
00086 #define GPIO_PIN_1                 ((uint16_t)0x0002)  /* Pin 1 selected    */
00087 #define GPIO_PIN_2                 ((uint16_t)0x0004)  /* Pin 2 selected    */
00088 #define GPIO_PIN_3                 ((uint16_t)0x0008)  /* Pin 3 selected    */
00089 #define GPIO_PIN_4                 ((uint16_t)0x0010)  /* Pin 4 selected    */
00090 #define GPIO_PIN_5                 ((uint16_t)0x0020)  /* Pin 5 selected    */
00091 #define GPIO_PIN_6                 ((uint16_t)0x0040)  /* Pin 6 selected    */
00092 #define GPIO_PIN_7                 ((uint16_t)0x0080)  /* Pin 7 selected    */
00093 #define GPIO_PIN_8                 ((uint16_t)0x0100)  /* Pin 8 selected    */
00094 #define GPIO_PIN_9                 ((uint16_t)0x0200)  /* Pin 9 selected    */
00095 #define GPIO_PIN_10                ((uint16_t)0x0400)  /* Pin 10 selected   */
00096 #define GPIO_PIN_11                ((uint16_t)0x0800)  /* Pin 11 selected   */
00097 #define GPIO_PIN_12                ((uint16_t)0x1000)  /* Pin 12 selected   */
00098 #define GPIO_PIN_13                ((uint16_t)0x2000)  /* Pin 13 selected   */
00099 #define GPIO_PIN_14                ((uint16_t)0x4000)  /* Pin 14 selected   */
00100 #define GPIO_PIN_15                ((uint16_t)0x8000)  /* Pin 15 selected   */
00101 #define GPIO_PIN_All               ((uint16_t)0xFFFF)  /* All pins selected */
00102
00103 #define GPIO_PIN_MASK              ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
00104 /**
00105   * @}
00106   */
00107
00108 /** @defgroup GPIO_mode GPIO mode
00109   * @brief GPIO Configuration Mode
00110   *        Elements values convention: 0xX0yz00YZ
00111   *           - X  : GPIO mode or EXTI Mode
00112   *           - y  : External IT or Event trigger detection
00113   *           - z  : IO configuration on External IT or Event
00114   *           - Y  : Output type (Push Pull or Open Drain)
00115   *           - Z  : IO Direction mode (Input, Output, Alternate or Analog)
00116   * @{
00117   */
00118 #define  GPIO_MODE_INPUT                        (0x00000000u)   /*!< Input Floating Mode                   */
00119 #define  GPIO_MODE_OUTPUT_PP                    (0x00000001u)   /*!< Output Push Pull Mode                 */
00120 #define  GPIO_MODE_OUTPUT_OD                    (0x00000011u)   /*!< Output Open Drain Mode                */
00121 #define  GPIO_MODE_AF_PP                        (0x00000002u)   /*!< Alternate Function Push Pull Mode     */
00122 #define  GPIO_MODE_AF_OD                        (0x00000012u)   /*!< Alternate Function Open Drain Mode    */
00123 #define  GPIO_MODE_ANALOG                       (0x00000003u)   /*!< Analog Mode  */
00124 #define  GPIO_MODE_IT_RISING                    (0x10110000u)   /*!< External Interrupt Mode with Rising edge trigger detection          */
00125 #define  GPIO_MODE_IT_FALLING                   (0x10210000u)   /*!< External Interrupt Mode with Falling edge trigger detection         */
00126 #define  GPIO_MODE_IT_RISING_FALLING            (0x10310000u)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
00127 #define  GPIO_MODE_EVT_RISING                   (0x10120000u)   /*!< External Event Mode with Rising edge trigger detection               */
00128 #define  GPIO_MODE_EVT_FALLING                  (0x10220000u)   /*!< External Event Mode with Falling edge trigger detection              */
00129 #define  GPIO_MODE_EVT_RISING_FALLING           (0x10320000u)   /*!< External Event Mode with Rising/Falling edge trigger detection       */
00130 /**
00131   * @}
00132   */
00133
00134 /** @defgroup GPIO_speed GPIO speed
00135   * @brief GPIO Output Maximum frequency
00136   * @{
00137   */
00138 #define  GPIO_SPEED_FREQ_LOW        (0x00000000u)  /*!< Low speed       */
00139 #define  GPIO_SPEED_FREQ_MEDIUM     (0x00000001u)  /*!< Medium speed    */
00140 #define  GPIO_SPEED_FREQ_HIGH       (0x00000002u)  /*!< High speed      */
00141 #define  GPIO_SPEED_FREQ_VERY_HIGH  (0x00000003u)  /*!< Very high speed */
00142 /**
00143   * @}
00144   */
00145
00146  /** @defgroup GPIO_pull GPIO pull
00147    * @brief GPIO Pull-Up or Pull-Down Activation
00148    * @{
00149    */
00150 #define  GPIO_NOPULL        (0x00000000u)   /*!< No Pull-up or Pull-down activation  */
00151 #define  GPIO_PULLUP        (0x00000001u)   /*!< Pull-up activation                  */
00152 #define  GPIO_PULLDOWN      (0x00000002u)   /*!< Pull-down activation                */
00153 /**
00154   * @}
00155   */
00156
00157 /**
00158   * @}
00159   */
00160
00161 /* Exported macro ------------------------------------------------------------*/
00162 /** @defgroup GPIO_Exported_Macros GPIO Exported Macros
00163   * @{
00164   */
00165
00166 /**
00167   * @brief  Check whether the specified EXTI line flag is set or not.
00168   * @param __EXTI_LINE__ specifies the EXTI line flag to check.
00169   *         This parameter can be GPIO_PIN_x where x can be(0..15)
00170   * @retval The new state of __EXTI_LINE__ (SET or RESET).
00171   */
00172 #define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__)       (EXTI->PR1 & (__EXTI_LINE__))
00173
00174 /**
00175   * @brief  Clear the EXTI's line pending flags.
00176   * @param __EXTI_LINE__ specifies the EXTI lines flags to clear.
00177   *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
00178   * @retval None
00179   */
00180 #define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__)     (EXTI->PR1 = (__EXTI_LINE__))
00181
00182 /**
00183   * @brief  Check whether the specified EXTI line is asserted or not.
00184   * @param __EXTI_LINE__ specifies the EXTI line to check.
00185   *          This parameter can be GPIO_PIN_x where x can be(0..15)
00186   * @retval The new state of __EXTI_LINE__ (SET or RESET).
00187   */
00188 #define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__)         (EXTI->PR1 & (__EXTI_LINE__))
00189
00190 /**
00191   * @brief  Clear the EXTI's line pending bits.
00192   * @param __EXTI_LINE__ specifies the EXTI lines to clear.
00193   *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
00194   * @retval None
00195   */
00196 #define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__)       (EXTI->PR1 = (__EXTI_LINE__))
00197
00198 /**
00199   * @brief  Generate a Software interrupt on selected EXTI line.
00200   * @param __EXTI_LINE__ specifies the EXTI line to check.
00201   *          This parameter can be GPIO_PIN_x where x can be(0..15)
00202   * @retval None
00203   */
00204 #define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__)  (EXTI->SWIER1 |= (__EXTI_LINE__))
00205
00206 /**
00207   * @}
00208   */
00209
00210 /* Private macros ------------------------------------------------------------*/
00211 /** @defgroup GPIO_Private_Macros GPIO Private Macros
00212   * @{
00213   */
00214 #define IS_GPIO_PIN_ACTION(ACTION)  (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
00215
00216 #define IS_GPIO_PIN(__PIN__)        ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00u) &&\
00217                                      (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00u))
00218
00219 #define IS_GPIO_MODE(__MODE__)      (((__MODE__) == GPIO_MODE_INPUT)              ||\
00220                                      ((__MODE__) == GPIO_MODE_OUTPUT_PP)          ||\
00221                                      ((__MODE__) == GPIO_MODE_OUTPUT_OD)          ||\
00222                                      ((__MODE__) == GPIO_MODE_AF_PP)              ||\
00223                                      ((__MODE__) == GPIO_MODE_AF_OD)              ||\
00224                                      ((__MODE__) == GPIO_MODE_IT_RISING)          ||\
00225                                      ((__MODE__) == GPIO_MODE_IT_FALLING)         ||\
00226                                      ((__MODE__) == GPIO_MODE_IT_RISING_FALLING)  ||\
00227                                      ((__MODE__) == GPIO_MODE_EVT_RISING)         ||\
00228                                      ((__MODE__) == GPIO_MODE_EVT_FALLING)        ||\
00229                                      ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
00230                                      ((__MODE__) == GPIO_MODE_ANALOG))
00231
00232 #define IS_GPIO_SPEED(__SPEED__)    (((__SPEED__) == GPIO_SPEED_FREQ_LOW)       ||\
00233                                      ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM)    ||\
00234                                      ((__SPEED__) == GPIO_SPEED_FREQ_HIGH)      ||\
00235                                      ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH))
00236
00237 #define IS_GPIO_PULL(__PULL__)      (((__PULL__) == GPIO_NOPULL)   ||\
00238                                      ((__PULL__) == GPIO_PULLUP)   || \
00239                                      ((__PULL__) == GPIO_PULLDOWN))
00240 /**
00241   * @}
00242   */
00243
00244 /* Include GPIO HAL Extended module */
00245 #include "stm32wbxx_hal_gpio_ex.h"
00246
00247 /* Exported functions --------------------------------------------------------*/
00248 /** @defgroup GPIO_Exported_Functions GPIO Exported Functions
00249  *  @brief    GPIO Exported Functions
00250   * @{
00251   */
00252
00253 /** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
00254  *  @brief    Initialization and Configuration functions
00255  * @{
00256  */
00257
00258 /* Initialization and de-initialization functions *****************************/
00259 void              HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);
00260 void              HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);
00261
00262 /**
00263   * @}
00264   */
00265
00266 /** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
00267  *  @brief    IO operation functions
00268  * @{
00269  */
00270
00271 /* IO operation functions *****************************************************/
00272 GPIO_PinState     HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
00273 void              HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
00274 void              HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
00275 HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
00276 void              HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
00277 void              HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
00278
00279 /**
00280   * @}
00281   */
00282
00283 /**
00284   * @}
00285   */
00286
00287 /**
00288   * @}
00289   */
00290
00291 /**
00292   * @}
00293   */
00294
00295 #ifdef __cplusplus
00296 }
00297 #endif
00298
00299 #endif /* STM32WBxx_HAL_GPIO_H */
00300
00301 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_gpio_ex.h Source File

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  • Firmware
  • Drivers
  • STM32WBxx_HAL_Driver
  • Inc
stm32wbxx_hal_gpio_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_gpio_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of GPIO HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_GPIO_EX_H
00022 #define STM32WBxx_HAL_GPIO_EX_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 /** @addtogroup STM32WBxx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @defgroup GPIOEx GPIOEx
00036   * @brief GPIO Extended HAL module driver
00037   * @{
00038   */
00039
00040 /* Exported types ------------------------------------------------------------*/
00041 /* Exported constants --------------------------------------------------------*/
00042 /** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
00043   * @{
00044   */
00045
00046 /** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection
00047   * @{
00048   */
00049
00050
00051  /* The table below gives an overview of the different alternate functions per port.
00052   * For more details refer yourself to the product data sheet.
00053   *
00054   */
00055
00056 #if defined (STM32WB55xx) || defined (STM32WB50xx)
00057
00058   /*     |   AF0    |   AF1    |   AF2    |   AF3    |   AF4    |   AF5    |   AF6    |   AF7    |
00059   *_____________________________________________________________________________________________
00060   *     |SYS_AF    |TIM       |TIM       |SPI/SAI/TI|I2C       | I2C      | RF       |  USART   |
00061   *_____________________________________________________________________________________________
00062   * PA0 |          |TIM2_CH1  |          |          |          |          |RF_DTB2   |          |
00063   * PA1 |          |TIM2_CH2  |          |          |I2C1_SMBA |SPI1_SCK  |RF_DTB3   |          |
00064   * PA2 |          |TIM2_CH3  |          |          |          |          |RF_DTB4   |          |
00065   * PA3 |          |TIM2_CH4  |          |SAI1_CK1  |          |          |RF_DTB5   |          |
00066   * PA4 |          |          |          |          |          |SPI1_NSS  |RF_DTB6   |          |
00067   * PA5 |          |TIM2_CH1  |TIM2_ETR  |          |          |SPI1_SCK  |RF_DTB7   |          |
00068   * PA6 |          |TIM1_BKIN |          |          |          |SPI1_MISO |RF_DTB8   |          |
00069   * PA7 |          |TIM1_CH1N |          |          |I2C3_SCL  |SPI1_MOSI |RF_DTB9   |          |
00070   * PA8 |MCO       |TIM1_CH1  |          |SAI1_CK2  |          |          |RF_DTB12  |USART1_CK |
00071   * PA9 |          |TIM2_CH2  |          |SAI1_DI2  |I2C1_SCL  |SPI2_SCK  |RF_DTB13  |USART1_TX |
00072   * PA10|          |TIM2_CH3  |          |SAI1_DI1  |I2C1_SDA  |          |RF_DTB14  |USART1_RX |
00073   * PA11|          |TIM2_CH4  |TIM1_BKIN2|          |          |SPI1_MISO |RF_DTB15  |USART1_CTS|
00074   * PA12|          |TIM2_ETR  |          |          |          |SPI1_MOSI |RF_MISO   |USART1_RTS|
00075   * PA13|JTMS_SWDIO|          |          |          |          |          |          |          |
00076   * PA14|JTCK_SWCLK|LPTIM1_OUT|          |          |I2C1_SMBA |          |          |          |
00077   * PA15|JTDI      |TIM2_CH1  |TIM2_ETR  |          |          |SPI1_NSS  |          |          |
00078   *______________________________________________________________________________________________
00079   * PB0 |          |          |          |          |          |          |          |          |
00080   * PB1 |          |          |          |          |          |          |          |          |
00081   * PB2 |RTC_OUT   |LPTIM1_OUT|          |          |I2C3_SMBA |SPI1_NSS  |RF_DTB10  |          |
00082   * PB3 |JTDO      |TIM2_CH2  |          |          |          |SPI1_SCK  |          |USART1_RTS|
00083   * PB4 |NJTRST    |          |          |          |I2C3_SDA  |SPI1_MISO |          |USART1_CTS|
00084   * PB5 |          |LPTIM1_IN1|          |          |I2C1_SMBA |SPI1_MOSI |RF_MOSI   |USART1_CK |
00085   * PB6 |          |LPTIM1_ETR|          |          |I2C1_SCL  |          |RF_SCK    |USART1_TX |
00086   * PB7 |          |LPTIM1_IN2|          |TIM1_BKIN |I2C1_SDA  |          |RF_DTB11  |USART1_RX |
00087   * PB8 |          |TIM1_CH2N |          |SAI1_CK1  |I2C1_SCL  |          |RF_DTB16  |          |
00088   * PB9 |          |TIM1_CH3N |          |SAI1_DI2  |I2C1_SDA  |SPI2_NSS  |          |          |
00089   * PB10|          |TIM2_CH3  |          |          |I2C3_SCL  |SPI2_SCK  |RF_DTB18  |          |
00090   * PB11|          |TIM2_CH4  |          |          |I2C3_SDA  |          |RF_DTB17  |          |
00091   * PB12|          |TIM1_BKIN |          |TIM1_BKIN |I2C3_SMBA |SPI2_NSS  |          |          |
00092   * PB13|          |TIM1_CH1N |          |          |I2C3_SCL  |SPI2_SCK  |          |          |
00093   * PB14|          |TIM1_CH2N |          |          |I2C3_SDA  |SPI2_MISO |          |          |
00094   * PB15|RTC_REFIN |TIM1_CH3N |          |          |          |SPI2_MOSI |          |          |
00095   *______________________________________________________________________________________________
00096   * PC0 |          |LPTIM1_IN1|          |          |I2C3_SCL  |          |          |          |
00097   * PC1 |          |LPTIM1_OUT|          |SPI2_MOSI |I2C3_SDA  |          |          |          |
00098   * PC2 |          |LPTIM1_IN2|          |          |          |SPI2_MISO |          |          |
00099   * PC3 |          |LPTIM1_ETR|          |SAI1_DI1  |          |SPI2_MOSI |          |          |
00100   * PC4 |          |          |          |          |          |          |          |          |
00101   * PC5 |          |          |          |SAI1_DI3  |          |          |          |          |
00102   * PC6 |          |          |          |          |          |          |          |          |
00103   * PC7 |          |          |          |          |          |          |          |          |
00104   * PC8 |          |          |          |          |          |          |          |          |
00105   * PC9 |          |          |          |TIM1_BKIN |          |          |          |          |
00106   * PC10|TRACED1   |          |          |          |          |          |          |          |
00107   * PC11|          |          |          |          |          |          |          |          |
00108   * PC12|TRACED3   |          |          |          |          |          |          |          |
00109   * PC13|          |          |          |          |          |          |          |          |
00110   * PC14|          |          |          |          |          |          |RF_DTB0   |          |
00111   * PC15|          |          |          |          |          |          |RF_DTB1   |          |
00112   *______________________________________________________________________________________________
00113   * PD0 |          |          |          |          |          |SPI2_NSS  |          |          |
00114   * PD1 |          |          |          |          |          |SPI2_SCK  |          |          |
00115   * PD2 |TRACED2   |          |          |          |          |          |          |          |
00116   * PD3 |          |          |          |SPI2_SCK  |          |SPI2_MISO |          |          |
00117   * PD4 |          |          |          |          |          |SPI2_MOSI |          |          |
00118   * PD5 |          |          |          |          |          |          |          |          |
00119   * PD6 |          |          |          |SAI1_DI1  |          |          |          |          |
00120   * PD7 |          |          |          |          |          |          |          |          |
00121   * PD8 |          |          |TIM1_BKIN2|          |          |          |          |          |
00122   * PD9 |TRACED0   |          |          |          |          |          |          |          |
00123   * PD10|TRIG_IO   |          |          |          |          |          |          |          |
00124   * PD11|          |          |          |          |          |          |          |          |
00125   * PD12|          |          |          |          |          |          |          |          |
00126   * PD13|          |          |          |          |          |          |          |          |
00127   * PD14|          |TIM1_CH1  |          |          |          |          |          |          |
00128   * PD15|          |TIM1_CH2  |          |          |          |          |          |          |
00129   *______________________________________________________________________________________________
00130   * PE0 |          |TIM1_ETR  |          |          |          |          |          |          |
00131   * PE1 |          |          |          |          |          |          |          |          |
00132   * PE2 |TRACED2   |          |          |SAI1_CK1  |          |          |          |          |
00133   * PE3 |          |          |          |          |          |          |          |          |
00134   * PE4 |          |          |          |          |          |          |          |          |
00135   *______________________________________________________________________________________________
00136   * PH0 |          |          |          |          |          |          |          |          |
00137   * PH1 |          |          |          |          |          |          |          |          |
00138   * PE2 |          |          |          |          |          |          |          |          |
00139   * PH3 |          |          |          |          |          |          |RF_NSS    |          |
00140   *______________________________________________________________________________________________*/
00141
00142
00143  /*     |   AF8    |   AF9    |   AF10   |   AF11   |  AF12    |  AF13    | AF14     | AF15     |
00144   *_____________________________________________________________________________________________
00145   *     |LPUART1   |TSC       |USB/QUADSP|LCD       |COMP/TIM  |SAI       |TIM       |EVENTOUT  |
00146   *_____________________________________________________________________________________________
00147   * PA0 |          |          |          |          |COMP1_OUT |SAI1_E_CLK|TIM2_ETR  |EVENTOUT  |
00148   * PA1 |          |          |          |LCD_SEG0  |          |          |          |EVENTOUT  |
00149   * PA2 |LPUART1_TX|          |QSPI_NCS  |LCD_SEG1  |COMP2_OUT |          |          |EVENTOUT  |
00150   * PA3 |LPUART1_RX|          |QSPI_CLK  |LCD_SEG2  |          |SAI1_CLK_A|          |EVENTOUT  |
00151   * PA4 |          |          |          |          |          |SAI1_FS_B |LPTIM2_OUT|EVENTOUT  |
00152   * PA5 |          |          |          |          |          |          |LPTIM2_ETR|EVENTOUT  |
00153   * PA6 |LPUART1_CT|          |QSPI_IO3  |LCD_SEG3  |TIM1_BKIN |          |TIM16_CH1 |EVENTOUT  |
00154   * PA7 |          |          |QSPI_IO2  |LCD_SEG4  |COMP2_OUT |          |TIM17_CH1 |EVENTOUT  |
00155   * PA8 |          |          |          |LCD_COM0  |          |SAI1_SCK_A|LPTIM2_OUT|EVENTOUT  |
00156   * PA9 |          |          |          |LCD_COM1  |          |SAI1_FS_A |          |EVENTOUT  |
00157   * PA10|          |          |USB_CRS_SY|LCD_COM2  |          |SAI1_SD_A |TIM17_BKIN|EVENTOUT  |
00158   * PA11|          |          |USB_DM    |          |TIM1_BKIN2|          |          |EVENTOUT  |
00159   * PA12|          |          |USB_DP    |          |          |          |          |EVENTOUT  |
00160   * PA13|IR_OUT    |          |USB_NOE   |          |          |SAI1_SD_B |          |EVENTOUT  |
00161   * PA14|          |          |          |          |          |SAI1_FS_B |          |EVENTOUT  |
00162   * PA15|          |TSC_G3_IO1|          |LCD_SEG17 |          |          |          |EVENTOUT  |
00163   *______________________________________________________________________________________________
00164   * PB0 |          |          |          |LCD_SEG5  |COMP1_OUT |          |          |EVENTOUT  |
00165   * PB1 |LPUART1_RT|          |          |LCD_SEG6  |          |          |LPTIM2_IN1|EVENTOUT  |
00166   * PB2 |          |          |          |LCD_VLCD  |          |SAI1_E_CLK|          |EVENTOUT  |
00167   * PB3 |          |          |          |LCD_SEG7  |          |SAI1_SCK_B|          |EVENTOUT  |
00168   * PB4 |          |TSC_G2_IO1|          |LCD_SEG8  |          |SAI1_CLK_B|TIM17_BKIN|EVENTOUT  |
00169   * PB5 |          |TSC_G2_IO2|          |LCD_SEG9  |COMP2_OUT |SAI1_SD_B |TIM16_BKIN|EVENTOUT  |
00170   * PB6 |          |TSC_G2_IO3|          |          |          |SAI1_FS_B |TIM16_CH1N|EVENTOUT  |
00171   * PB7 |          |TSC_G2_IO4|          |LCD_SEG21 |          |          |TIM17_CH1N|EVENTOUT  |
00172   * PB8 |          |          |QSPI_IO1  |LCD_SEG16 |          |SAI1_CLK_A|TIM16_CH1 |EVENTOUT  |
00173   * PB9 |IR_OUT    |TSC_G7_IO4|QSPI_IO0  |LCD_COM3  |          |SAI1_FS_A |TIM17_CH1 |EVENTOUT  |
00174   * PB10|LPUART1_RX|TSC_SYNC  |QSPI_CLK  |LCD_SEG10 |COMP1_OUT |SAI1_SCK_A|          |EVENTOUT  |
00175   * PB11|LPUART1_TX|          |QSPI_NCS  |LCD_SEG11 |COMP2_OUT |          |          |EVENTOUT  |
00176   * PB12|LPUART1_RT|TSC_G1_IO1|          |LCD_SEG12 |          |SAI1_FS_A |          |EVENTOUT  |
00177   * PB13|LPUART1_CT|TSC_G1_IO2|          |LCD_SEG13 |          |SAI1_SCK_A|          |EVENTOUT  |
00178   * PB14|          |TSC_G1_IO3|          |LCD_SEG14 |          |SAI1_CLK_A|          |EVENTOUT  |
00179   * PB15|          |TSC_G1_IO4|          |LCD_SEG15 |          |SAI1_SD_A |          |EVENTOUT  |
00180   *______________________________________________________________________________________________
00181   * PC0 |LPUART1_RX|          |          |LCD_SEG18 |          |          |LPTIM2_IN1|EVENTOUT  |
00182   * PC1 |LPUART1_TX|          |          |LCD_SEG19 |          |          |          |EVENTOUT  |
00183   * PC2 |          |          |          |LCD_SEG20 |          |          |          |EVENTOUT  |
00184   * PC3 |          |          |          |LCD_VLCD  |          |SAI1_SD_A |LPTIM2_ETR|EVENTOUT  |
00185   * PC4 |          |          |          |LCD_SEG22 |          |          |          |EVENTOUT  |
00186   * PC5 |          |          |          |LCD_SEG23 |          |          |          |EVENTOUT  |
00187   * PC6 |          |TSC_G4_IO1|          |LCD_SEG24 |          |          |          |EVENTOUT  |
00188   * PC7 |          |TSC_G4_IO2|          |LCD_SEG25 |          |          |          |EVENTOUT  |
00189   * PC8 |          |TSC_G4_IO3|          |LCD_SEG26 |          |          |          |EVENTOUT  |
00190   * PC9 |          |TSC_G4_IO4|USB_NOE   |LCD_SEG27 |          |SAI1_SCK_B|          |EVENTOUT  |
00191   * PC10|          |TSC_G3_IO2|          |LCD_Cx_SEx|          |          |          |EVENTOUT  |
00192   * PC11|          |TSC_G3_IO3|          |LCD_Cx_SEx|          |          |          |EVENTOUT  |
00193   * PC12|          |TSC_G3_IO4|          |LCD_Cx_SEx|          |          |          |EVENTOUT  |
00194   * PC13|          |          |          |          |          |          |          |EVENTOUT  |
00195   * PC14|          |          |          |          |          |          |          |EVENTOUT  |
00196   * PC15|          |          |          |          |          |          |          |EVENTOUT  |
00197   *______________________________________________________________________________________________
00198   * PD0 |          |          |          |          |          |          |          |EVENTOUT  |
00199   * PD1 |          |          |          |          |          |          |          |EVENTOUT  |
00200   * PD2 |          |TSC_SYNC  |          |LCD_Cx_SEx|          |          |          |EVENTOUT  |
00201   * PD3 |          |          |QSPI_NCS  |          |          |          |          |EVENTOUT  |
00202   * PD4 |          |TSC_G5_IO1|QSPI_IO0  |          |          |          |          |EVENTOUT  |
00203   * PD5 |          |TSC_G5_IO2|QSPI_IO1  |          |          |SAI1_CLK_B|          |EVENTOUT  |
00204   * PD6 |          |TSC_G5_IO3|QSPI_IO2  |          |          |SAI1_SD_A |          |EVENTOUT  |
00205   * PD7 |          |TSC_G5_IO4|QSPI_IO3  |LCD_SEG39 |          |          |          |EVENTOUT  |
00206   * PD8 |          |          |          |LCD_SEG28 |          |          |          |EVENTOUT  |
00207   * PD9 |          |          |          |LCD_SEG29 |          |          |          |EVENTOUT  |
00208   * PD10|          |TSC_G6_IO1|          |LCD_SEG30 |          |          |          |EVENTOUT  |
00209   * PD11|          |TSC_G6_IO2|          |LCD_SEG31 |          |          |LPTIM2_ETR|EVENTOUT  |
00210   * PD12|          |TSC_G6_IO3|          |LCD_SEG32 |          |          |LPTIM2_IN1|EVENTOUT  |
00211   * PD13|          |TSC_G6_IO4|          |LCD_SEG33 |          |          |LPTIM2_OUT|EVENTOUT  |
00212   * PD14|          |          |          |LCD_SEG34 |          |          |          |EVENTOUT  |
00213   * PD15|          |          |          |LCD_SEG35 |          |          |          |EVENTOUT  |
00214   *______________________________________________________________________________________________
00215   * PE0 |          |TSC_G7_IO3|          |LCD_SEG36 |          |          |TIM16_CH1 |EVENTOUT  |
00216   * PE1 |          |TSC_G7_IO2|          |LCD_SEG37 |          |          |TIM17_CH1 |EVENTOUT  |
00217   * PE2 |          |TSC_G7_IO1|          |LCD_SEG38 |          |SAI1_CLK_A|          |EVENTOUT  |
00218   * PE3 |          |          |          |          |          |          |          |EVENTOUT  |
00219   * PE4 |          |          |          |          |          |          |          |EVENTOUT  |
00220   *______________________________________________________________________________________________
00221   * PH0 |          |          |          |          |          |          |          |EVENTOUT  |
00222   * PH1 |          |          |          |          |          |          |          |EVENTOUT  |
00223   * PE2 |          |          |          |          |          |          |          |EVENTOUT  |
00224   * PH3 |          |          |          |          |          |          |          |EVENTOUT  |
00225   *______________________________________________________________________________________________*/
00226
00227 /**
00228   * @brief   AF 0 selection
00229   */
00230
00231 #define GPIO_AF0_MCO           ((uint8_t)0x00)  /*!< MCO Alternate Function mapping                 */
00232 #define GPIO_AF0_LSCO          ((uint8_t)0x00)  /*!< LSCO Alternate Function mapping                */
00233 #define GPIO_AF0_JTMS_SWDIO    ((uint8_t)0x00)  /*!< JTMS-SWDIO Alternate Function mapping          */
00234 #define GPIO_AF0_JTCK_SWCLK    ((uint8_t)0x00)  /*!< JTCK-SWCLK Alternate Function mapping          */
00235 #define GPIO_AF0_JTDI          ((uint8_t)0x00)  /*!< JTDI Alternate Function mapping                */
00236 #define GPIO_AF0_RTC_OUT       ((uint8_t)0x00)  /*!< RCT_OUT Alternate Function mapping             */
00237 #define GPIO_AF0_JTD_TRACE     ((uint8_t)0x00)  /*!< JTDO-TRACESWO Alternate Function mapping       */
00238 #define GPIO_AF0_NJTRST        ((uint8_t)0x00)  /*!< NJTRST Alternate Function mapping              */
00239 #define GPIO_AF0_RTC_REFIN     ((uint8_t)0x00)  /*!< RTC_REFIN Alternate Function mapping           */
00240 #define GPIO_AF0_TRACED0       ((uint8_t)0x00)  /*!< TRACED0 Alternate Function mapping             */
00241 #define GPIO_AF0_TRACED1       ((uint8_t)0x00)  /*!< TRACED1 Alternate Function mapping             */
00242 #define GPIO_AF0_TRACED2       ((uint8_t)0x00)  /*!< TRACED2 Alternate Function mapping             */
00243 #define GPIO_AF0_TRACED3       ((uint8_t)0x00)  /*!< TRACED3 Alternate Function mapping             */
00244 #define GPIO_AF0_TRIG_INOUT    ((uint8_t)0x00)  /*!< TRIG_INOUT Alternate Function mapping          */
00245 #define GPIO_AF0_TRACECK       ((uint8_t)0x00)  /*!< TRACECK Alternate Function mapping             */
00246 #define GPIO_AF0_SYS           ((uint8_t)0x00)  /*!< System Function mapping                        */
00247
00248  /**
00249   * @brief   AF 1 selection
00250   */
00251 #define GPIO_AF1_TIM1           ((uint8_t)0x01)  /*!< TIM1 Alternate Function mapping           */
00252 #define GPIO_AF1_TIM2           ((uint8_t)0x01)  /*!< TIM2 Alternate Function mapping            */
00253 #define GPIO_AF1_LPTIM1         ((uint8_t)0x01)  /*!< LPTIM1 Alternate Function mapping          */
00254
00255 /**
00256   * @brief   AF 2 selection
00257   */
00258
00259 #define GPIO_AF2_TIM2           ((uint8_t)0x02)  /*!< TIM2 Alternate Function mapping           */
00260 #define GPIO_AF2_TIM1           ((uint8_t)0x02)  /*!< TIM1 Alternate Function mapping         */
00261 /**
00262   * @brief   AF 3 selection
00263   */
00264 #define GPIO_AF3_SAI1           ((uint8_t)0x03)  /*!< SAI1_CK1 Alternate Function mapping           */
00265 #define GPIO_AF3_SPI2           ((uint8_t)0x03)  /*!< SPI2 Alternate Function mapping          */
00266 #define GPIO_AF3_TIM1           ((uint8_t)0x03)  /*!< TIM1 Alternate Function mapping          */
00267
00268 /**
00269   * @brief   AF 4 selection
00270   */
00271 #define GPIO_AF4_I2C1           ((uint8_t)0x04)  /*!< I2C1 Alternate Function mapping         */
00272 #define GPIO_AF4_I2C3           ((uint8_t)0x04)  /*!< I2C3 Alternate Function mapping          */
00273
00274 /**
00275   * @brief   AF 5 selection
00276   */
00277 #define GPIO_AF5_SPI1           ((uint8_t)0x05)  /*!< SPI1 Alternate Function mapping        */
00278 #define GPIO_AF5_SPI2           ((uint8_t)0x05)  /*!< SPI2 Alternate Function mapping        */
00279 /**
00280   * @brief   AF 6 selection
00281   */
00282 #define GPIO_AF6_MCO            ((uint8_t)0x06)  /*!< MCO Alternate Function mapping       */
00283 #define GPIO_AF6_LSCO           ((uint8_t)0x06)  /*!< LSCO Alternate Function mapping      */
00284 #define GPIO_AF6_RF_DTB0        ((uint8_t)0x06)  /*!< RF_DTB0 Alternate Function mapping   */
00285 #define GPIO_AF6_RF_DTB1        ((uint8_t)0x06)  /*!< RF_DTB1 Alternate Function mapping   */
00286 #define GPIO_AF6_RF_DTB2        ((uint8_t)0x06)  /*!< RF_DTB2 Alternate Function mapping   */
00287 #define GPIO_AF6_RF_DTB3        ((uint8_t)0x06)  /*!< RF_DTB3 Alternate Function mapping   */
00288 #define GPIO_AF6_RF_DTB4        ((uint8_t)0x06)  /*!< RF_DTB4 Alternate Function mapping   */
00289 #define GPIO_AF6_RF_DTB5        ((uint8_t)0x06)  /*!< RF_DTB5 Alternate Function mapping   */
00290 #define GPIO_AF6_RF_DTB6        ((uint8_t)0x06)  /*!< RF_DTB6 Alternate Function mapping   */
00291 #define GPIO_AF6_RF_DTB7        ((uint8_t)0x06)  /*!< RF_DTB7 Alternate Function mapping   */
00292 #define GPIO_AF6_RF_DTB8        ((uint8_t)0x06)  /*!< RF_DTB8 Alternate Function mapping   */
00293 #define GPIO_AF6_RF_DTB9        ((uint8_t)0x06)  /*!< RF_DTB9 Alternate Function mapping   */
00294 #define GPIO_AF6_RF_DTB10       ((uint8_t)0x06)  /*!< RF_DTB10 Alternate Function mapping  */
00295 #define GPIO_AF6_RF_DTB11       ((uint8_t)0x06)  /*!< RF_DTB11 Alternate Function mapping  */
00296 #define GPIO_AF6_RF_DTB12       ((uint8_t)0x06)  /*!< RF_DTB12 Alternate Function mapping  */
00297 #define GPIO_AF6_RF_DTB13       ((uint8_t)0x06)  /*!< RF_DTB13 Alternate Function mapping  */
00298 #define GPIO_AF6_RF_DTB14       ((uint8_t)0x06)  /*!< RF_DTB14 Alternate Function mapping  */
00299 #define GPIO_AF6_RF_DTB15       ((uint8_t)0x06)  /*!< RF_DTB15 Alternate Function mapping  */
00300 #define GPIO_AF6_RF_DTB16       ((uint8_t)0x06)  /*!< RF_DTB16 Alternate Function mapping  */
00301 #define GPIO_AF6_RF_DTB17       ((uint8_t)0x06)  /*!< RF_DTB17 Alternate Function mapping  */
00302 #define GPIO_AF6_RF_DTB18       ((uint8_t)0x06)  /*!< RF_DTB18 Alternate Function mapping  */
00303 #define GPIO_AF6_RF_MISO        ((uint8_t)0x06)  /*!< RF_MISO Alternate Function mapping   */
00304 #define GPIO_AF6_RF_MOSI        ((uint8_t)0x06)  /*!< RF_MOSI Alternate Function mapping   */
00305 #define GPIO_AF6_RF_SCK         ((uint8_t)0x06)  /*!< RF_SCK Alternate Function mapping    */
00306 #define GPIO_AF6_RF_NSS         ((uint8_t)0x06)  /*!< RF_NSS Alternate Function mapping    */
00307 /**
00308   * @brief   AF 7 selection
00309   */
00310 #define GPIO_AF7_USART1         ((uint8_t)0x07)  /*!< USART1 Alternate Function mapping     */
00311
00312 /**
00313   * @brief   AF 8 selection
00314   */
00315 #define GPIO_AF8_LPUART1        ((uint8_t)0x08)  /*!< LPUART1 Alternate Function mapping      */
00316 #define GPIO_AF8_IR             ((uint8_t)0x08)  /*!< IR Alternate Function mapping          */
00317
00318 /**
00319   * @brief   AF 9 selection
00320   */
00321  #define GPIO_AF9_TSC           ((uint8_t)0x09)  /*!< TSC Alternate Function mapping      */
00322
00323 /**
00324   * @brief   AF 10 selection
00325   */
00326 #define GPIO_AF10_QUADSPI       ((uint8_t)0x0a)  /*!< QUADSPI Alternate Function mapping  */
00327 #define GPIO_AF10_USB           ((uint8_t)0x0a)  /*!< USB Alternate Function mapping      */
00328
00329 /**
00330    * @brief   AF 11 selection
00331    */
00332 #define GPIO_AF11_LCD           ((uint8_t)0x0b)  /*!< LCD Alternate Function mapping      */
00333
00334 /**
00335  * @brief   AF 12 selection
00336  */
00337 #define GPIO_AF12_COMP1         ((uint8_t)0x0c)  /*!< COMP1 Alternate Function mapping      */
00338 #define GPIO_AF12_COMP2         ((uint8_t)0x0c)  /*!< COMP2 Alternate Function mapping      */
00339 #define GPIO_AF12_TIM1          ((uint8_t)0x0c)  /*!< TIM1 Alternate Function mapping      */
00340
00341 /**
00342  * @brief   AF 13 selection
00343  */
00344 #define GPIO_AF13_SAI1          ((uint8_t)0x0d)  /*!< SAI1 Alternate Function mapping      */
00345
00346 /**
00347  * @brief   AF 14 selection
00348  */
00349 #define GPIO_AF14_TIM2          ((uint8_t)0x0e)  /*!< TIM2 Alternate Function mapping       */
00350 #define GPIO_AF14_TIM16         ((uint8_t)0x0e)  /*!< TIM16 Alternate Function mapping      */
00351 #define GPIO_AF14_TIM17         ((uint8_t)0x0e)  /*!< TIM17 Alternate Function mapping      */
00352 #define GPIO_AF14_LPTIM2        ((uint8_t)0x0e)  /*!< LPTIM2 Alternate Function mapping     */
00353
00354
00355 /**
00356 * @brief   AF 15 selection
00357 */
00358
00359 #define GPIO_AF15_EVENTOUT          ((uint8_t)0x0f)  /*!< EVENTOUT Alternate Function mapping      */
00360
00361 #define IS_GPIO_AF(AF)              ((AF) <= (uint8_t)0x0f)
00362
00363 #endif
00364
00365
00366
00367 /**
00368   * @}
00369   */
00370
00371 /**
00372   * @}
00373   */
00374
00375 /* Exported macro ------------------------------------------------------------*/
00376 /** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros
00377   * @{
00378   */
00379
00380 /** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index
00381 * @{
00382   */
00383 #if defined (STM32WB55xx)
00384 #define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0uL :\
00385                                       ((__GPIOx__) == (GPIOB))? 1uL :\
00386                                       ((__GPIOx__) == (GPIOC))? 2uL :\
00387                                       ((__GPIOx__) == (GPIOD))? 3uL :\
00388                                       ((__GPIOx__) == (GPIOE))? 4uL : 7uL)
00389 #else
00390 #define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0uL :\
00391                                       ((__GPIOx__) == (GPIOB))? 1uL :\
00392                                       ((__GPIOx__) == (GPIOC))? 2uL :\
00393                                       ((__GPIOx__) == (GPIOE))? 4uL : 7uL)
00394 #endif
00395  /**
00396   * @}
00397   */
00398
00399 /**
00400   * @}
00401   */
00402
00403 /* Exported functions --------------------------------------------------------*/
00404 /**
00405   * @}
00406   */
00407
00408 /**
00409   * @}
00410   */
00411
00412 #ifdef __cplusplus
00413 }
00414 #endif
00415
00416 #endif /* STM32WBxx_HAL_GPIO_EX_H */
00417
00418 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_hsem.c Source File

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stm32wbxx_hal_hsem.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_hsem.c
00004   * @author  MCD Application Team
00005   * @brief   HSEM HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the semaphore peripheral:
00008   *           + Semaphore Take function (2-Step Procedure) , non blocking
00009   *           + Semaphore FastTake function (1-Step Procedure) , non blocking
00010   *           + Semaphore Status check
00011   *           + Semaphore Clear Key Set and Get
00012   *           + Release and release all functions
00013   *           + Semaphore notification enabling and disabling and callnack functions
00014   *           + IRQ handler management
00015   *
00016   *
00017   @verbatim
00018   ==============================================================================
00019                      ##### How to use this driver #####
00020   ==============================================================================
00021   [..]
00022       (#)Take a semaphore In 2-Step mode Using function HAL_HSEM_Take. This function takes as parameters :
00023            (++) the semaphore ID from 0 to 31
00024            (++) the process ID from 0 to 255
00025       (#) Fast Take semaphore In 1-Step mode Using function HAL_HSEM_FastTake. This function takes as parameter :
00026            (++) the semaphore ID from 0_ID to 31. Note that the process ID value is implicitly assumed as zero
00027       (#) Check if a semaphore is Taken using function HAL_HSEM_IsSemTaken. This function takes as parameter :
00028           (++) the semaphore ID from 0_ID to 31
00029           (++) It returns 1 if the given semaphore is taken otherwise (Free) zero
00030       (#)Release a semaphore using function with HAL_HSEM_Release. This function takes as parameters :
00031            (++) the semaphore ID from 0 to 31
00032            (++) the process ID from 0 to 255:
00033            (++) Note: If ProcessID and MasterID match, semaphore is freed, and an interrupt
00034          may be generated when enabled (notification activated). If ProcessID or MasterID does not match,
00035          semaphore remains taken (locked)
00036
00037       (#)Release all semaphores at once taken by a given Master using function HAL_HSEM_Release_All
00038           This function takes as parameters :
00039            (++) the Release Key (value from 0 to 0xFFFF) can be Set or Get respectively by
00040               HAL_HSEM_SetClearKey() or HAL_HSEM_GetClearKey functions
00041            (++) the Master ID:
00042            (++) Note: If the Key and MasterID match, all semaphores taken by the given CPU that corresponds
00043            to MasterID  will be freed, and an interrupt may be generated when enabled (notification activated). If the
00044            Key or the MasterID doesn't match, semaphores remains taken (locked)
00045
00046       (#)Semaphores Release all key functions:
00047          (++)  HAL_HSEM_SetClearKey() to set semaphore release all Key
00048          (++)  HAL_HSEM_GetClearKey() to get release all Key
00049       (#)Semaphores notification functions :
00050          (++)  HAL_HSEM_ActivateNotification to activate a notification callback on
00051                a given semaphores Mask (bitfield). When one or more semaphores defined by the mask are released
00052                the callback HAL_HSEM_FreeCallback will be asserted giving as parameters a mask of the released
00053                semaphores (bitfield).
00054
00055          (++)  HAL_HSEM_DeactivateNotification to deactivate the notification of a given semaphores Mask (bitfield).
00056          (++) See the description of the macro __HAL_HSEM_SEMID_TO_MASK to check how to calculate a semaphore mask
00057                 Used by the notification functions
00058      *** HSEM HAL driver macros list ***
00059      =============================================
00060      [..] Below the list of most used macros in HSEM HAL driver.
00061
00062       (+) __HAL_HSEM_SEMID_TO_MASK: Helper macro to convert a Semaphore ID to a Mask.
00063       [..] Example of use :
00064       [..] mask = __HAL_HSEM_SEMID_TO_MASK(8)  |  __HAL_HSEM_SEMID_TO_MASK(21) | __HAL_HSEM_SEMID_TO_MASK(25).
00065       [..] All next macros take as parameter a semaphore Mask (bitfiled) that can be constructed using  __HAL_HSEM_SEMID_TO_MASK as the above example.
00066       (+) __HAL_HSEM_ENABLE_IT: Enable the specified semaphores Mask interrupts.
00067       (+) __HAL_HSEM_DISABLE_IT: Disable the specified semaphores Mask interrupts.
00068       (+) __HAL_HSEM_GET_IT: Checks whether the specified semaphore interrupt has occurred or not.
00069       (+) __HAL_HSEM_GET_FLAG: Get the semaphores status release flags.
00070       (+) __HAL_HSEM_CLEAR_FLAG: Clear the semaphores status release flags.
00071
00072   @endverbatim
00073   ******************************************************************************
00074   * @attention
00075   *
00076   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00077   * All rights reserved.</center></h2>
00078   *
00079   * This software component is licensed by ST under BSD 3-Clause license,
00080   * the "License"; You may not use this file except in compliance with the
00081   * License. You may obtain a copy of the License at:
00082   *                        opensource.org/licenses/BSD-3-Clause
00083   *
00084   ******************************************************************************
00085   */
00086
00087 /* Includes ------------------------------------------------------------------*/
00088 #include "stm32wbxx_hal.h"
00089
00090 /** @addtogroup STM32WBxx_HAL_Driver
00091   * @{
00092   */
00093
00094 /** @defgroup HSEM HSEM
00095   * @brief HSEM HAL module driver
00096   * @{
00097   */
00098
00099 #ifdef HAL_HSEM_MODULE_ENABLED
00100
00101 /* Private typedef -----------------------------------------------------------*/
00102 /* Private define ------------------------------------------------------------*/
00103 #if defined(DUAL_CORE)
00104 #ifndef HSEM_R_MASTERID
00105 #define HSEM_R_MASTERID HSEM_R_COREID
00106 #endif
00107
00108 #ifndef HSEM_RLR_MASTERID
00109 #define HSEM_RLR_MASTERID HSEM_RLR_COREID
00110 #endif
00111
00112 #ifndef HSEM_CR_MASTERID
00113 #define HSEM_CR_MASTERID HSEM_CR_COREID
00114 #endif
00115 #endif /* DUAL_CORE */
00116 /* Private macro -------------------------------------------------------------*/
00117 /* Private variables ---------------------------------------------------------*/
00118 /* Private function prototypes -----------------------------------------------*/
00119 /* Private functions ---------------------------------------------------------*/
00120 /* Exported functions --------------------------------------------------------*/
00121
00122 /** @defgroup HSEM_Exported_Functions  HSEM Exported Functions
00123   * @{
00124   */
00125
00126 /** @defgroup HSEM_Exported_Functions_Group1 Take and Release functions
00127   *  @brief    HSEM Take and Release functions
00128   *
00129 @verbatim
00130  ==============================================================================
00131               ##### HSEM Take and Release functions #####
00132  ==============================================================================
00133 [..] This section provides functions allowing to:
00134       (+) Take a semaphore with 2 Step method
00135       (+) Fast Take a semaphore with 1 Step method
00136       (+) Check semaphore state Taken or not
00137       (+) Release a semaphore
00138       (+) Release all semaphore at once
00139
00140 @endverbatim
00141   * @{
00142   */
00143
00144
00145 /**
00146   * @brief  Take a semaphore in 2 Step mode.
00147   * @param  SemID: semaphore ID from 0 to 31
00148   * @param  ProcessID: Process ID from 0 to 255
00149   * @retval HAL status
00150   */
00151 HAL_StatusTypeDef  HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID)
00152 {
00153   /* Check the parameters */
00154   assert_param(IS_HSEM_SEMID(SemID));
00155   assert_param(IS_HSEM_PROCESSID(ProcessID));
00156
00157   /* First step  write R register with MasterID, processID and take bit=1*/
00158   HSEM->R[SemID] = (ProcessID | HSEM_CR_COREID_CURRENT | HSEM_R_LOCK);
00159
00160   /* second step : read the R register . Take achieved if MasterID and processID match and take bit set to 1 */
00161   if (HSEM->R[SemID] == (ProcessID | HSEM_CR_COREID_CURRENT | HSEM_R_LOCK))
00162   {
00163     /*take success when MasterID and ProcessID match and take bit set*/
00164     return HAL_OK;
00165   }
00166
00167   /* Semaphore take fails*/
00168   return HAL_ERROR;
00169 }
00170
00171 /**
00172   * @brief  Fast Take a semaphore with 1 Step mode.
00173   * @param  SemID: semaphore ID from 0 to 31
00174   * @retval HAL status
00175   */
00176 HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID)
00177 {
00178   /* Check the parameters */
00179   assert_param(IS_HSEM_SEMID(SemID));
00180
00181   /* Read the RLR register to take the semaphore */
00182   if (HSEM->RLR[SemID] == (HSEM_CR_COREID_CURRENT | HSEM_RLR_LOCK))
00183   {
00184     /*take success when MasterID match and take bit set*/
00185     return HAL_OK;
00186   }
00187
00188   /* Semaphore take fails */
00189   return HAL_ERROR;
00190 }
00191 /**
00192   * @brief  Check semaphore state Taken or not.
00193   * @param  SemID: semaphore ID
00194   * @retval HAL HSEM state
00195   */
00196 uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID)
00197 {
00198   return (((HSEM->R[SemID] & HSEM_R_LOCK) != 0U) ? 1UL : 0UL);
00199 }
00200
00201
00202 /**
00203   * @brief  Release a semaphore.
00204   * @param  SemID: semaphore ID from 0 to 31
00205   * @param  ProcessID: Process ID from 0 to 255
00206   * @retval None
00207   */
00208 void  HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID)
00209 {
00210   /* Check the parameters */
00211   assert_param(IS_HSEM_SEMID(SemID));
00212   assert_param(IS_HSEM_PROCESSID(ProcessID));
00213
00214   /* Clear the semaphore by writing to the R register : the MasterID , the processID and take bit = 0  */
00215   HSEM->R[SemID] = (ProcessID | HSEM_CR_COREID_CURRENT);
00216
00217 }
00218
00219 /**
00220   * @brief  Release All semaphore used by a given Master .
00221   * @param  Key: Semaphore Key , value from 0 to 0xFFFF
00222   * @param  CoreID: CoreID of the CPU that is using semaphores to be released
00223   * @retval None
00224   */
00225 void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID)
00226 {
00227   assert_param(IS_HSEM_KEY(Key));
00228   assert_param(IS_HSEM_COREID(CoreID));
00229
00230   HSEM->CR = ((Key << HSEM_CR_KEY_Pos) | (CoreID << HSEM_CR_COREID_Pos));
00231 }
00232
00233 /**
00234   * @}
00235   */
00236
00237 /** @defgroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions
00238   *  @brief    HSEM Set and Get Key functions.
00239   *
00240 @verbatim
00241   ==============================================================================
00242               ##### HSEM Set and Get Key functions #####
00243   ==============================================================================
00244     [..]  This section provides functions allowing to:
00245       (+) Set semaphore Key
00246       (+) Get semaphore Key
00247 @endverbatim
00248
00249   * @{
00250   */
00251
00252 /**
00253   * @brief  Set semaphore Key .
00254   * @param  Key: Semaphore Key , value from 0 to 0xFFFF
00255   * @retval None
00256   */
00257 void  HAL_HSEM_SetClearKey(uint32_t Key)
00258 {
00259   assert_param(IS_HSEM_KEY(Key));
00260
00261   MODIFY_REG(HSEM->KEYR, HSEM_KEYR_KEY, (Key << HSEM_KEYR_KEY_Pos));
00262
00263 }
00264
00265 /**
00266   * @brief  Get semaphore Key .
00267   * @retval Semaphore Key , value from 0 to 0xFFFF
00268   */
00269 uint32_t HAL_HSEM_GetClearKey(void)
00270 {
00271   return (HSEM->KEYR >> HSEM_KEYR_KEY_Pos);
00272 }
00273
00274 /**
00275   * @}
00276   */
00277
00278 /** @defgroup HSEM_Exported_Functions_Group3 HSEM IRQ handler management
00279   *  @brief    HSEM Notification functions.
00280   *
00281 @verbatim
00282   ==============================================================================
00283       ##### HSEM IRQ handler management and Notification functions #####
00284   ==============================================================================
00285 [..]  This section provides HSEM IRQ handler and Notification function.
00286
00287 @endverbatim
00288   * @{
00289   */
00290
00291 /**
00292   * @brief  Activate Semaphore release Notification for a given Semaphores Mask .
00293   * @param  SemMask: Mask of Released semaphores
00294   * @retval Semaphore Key
00295   */
00296 void HAL_HSEM_ActivateNotification(uint32_t SemMask)
00297 {
00298   HSEM_COMMON->IER |= SemMask;
00299 }
00300
00301 /**
00302   * @brief  Deactivate Semaphore release Notification for a given Semaphores Mask .
00303   * @param  SemMask: Mask of Released semaphores
00304   * @retval Semaphore Key
00305   */
00306 void HAL_HSEM_DeactivateNotification(uint32_t SemMask)
00307 {
00308   HSEM_COMMON->IER &= ~SemMask;
00309 }
00310
00311 /**
00312   * @brief  This function handles HSEM interrupt request
00313   * @retval None
00314   */
00315 void HAL_HSEM_IRQHandler(void)
00316 {
00317   uint32_t statusreg;
00318   /* Get the list of masked freed semaphores*/
00319   statusreg = HSEM_COMMON->MISR;
00320
00321   /*Disable Interrupts*/
00322   HSEM_COMMON->IER &= ~((uint32_t)statusreg);
00323
00324   /*Clear Flags*/
00325   HSEM_COMMON->ICR = ((uint32_t)statusreg);
00326
00327   /* Call FreeCallback */
00328   HAL_HSEM_FreeCallback(statusreg);
00329 }
00330
00331 /**
00332   * @brief Semaphore Released Callback.
00333   * @param SemMask: Mask of Released semaphores
00334   * @retval None
00335   */
00336 __weak void HAL_HSEM_FreeCallback(uint32_t SemMask)
00337 {
00338   /* Prevent unused argument(s) compilation warning */
00339   UNUSED(SemMask);
00340
00341   /* NOTE : This function should not be modified, when the callback is needed,
00342   the HAL_HSEM_FreeCallback can be implemented in the user file
00343     */
00344 }
00345
00346 /**
00347   * @}
00348   */
00349
00350 /**
00351   * @}
00352   */
00353
00354 #endif /* HAL_HSEM_MODULE_ENABLED */
00355 /**
00356   * @}
00357   */
00358
00359 /**
00360   * @}
00361   */
00362
00363 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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STM32WB55xx HAL User Manual: stm32wbxx_hal_hsem.h Source File

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stm32wbxx_hal_hsem.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_hsem.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of HSEM HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_HSEM_H
00022 #define STM32WBxx_HAL_HSEM_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 /** @addtogroup STM32WBxx_HAL_Driver
00032    * @{
00033    */
00034
00035 /** @addtogroup HSEM
00036    * @{
00037    */
00038
00039 /* Exported macro ------------------------------------------------------------*/
00040 /** @defgroup HSEM_Exported_Macros HSEM Exported Macros
00041   * @{
00042   */
00043
00044 /**
00045   * @brief  SemID to mask helper Macro.
00046   * @param  __SEMID__: semaphore ID from 0 to 31
00047   * @retval Semaphore Mask.
00048   */
00049 #define __HAL_HSEM_SEMID_TO_MASK(__SEMID__) (1 << (__SEMID__))
00050
00051 /**
00052   * @brief  Enables the specified HSEM interrupts.
00053   * @param  __SEM_MASK__: semaphores Mask
00054   * @retval None.
00055   */
00056 #if defined(DUAL_CORE)
00057 #define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
00058                                             (HSEM->C1IER |= (__SEM_MASK__)) : \
00059                                             (HSEM->C2IER |= (__SEM_MASK__)))
00060 #else
00061 #define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->IER |= (__SEM_MASK__))
00062 #endif /* DUAL_CORE */
00063 /**
00064   * @brief  Disables the specified HSEM interrupts.
00065   * @param  __SEM_MASK__: semaphores Mask
00066   * @retval None.
00067   */
00068 #if defined(DUAL_CORE)
00069 #define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
00070                                              (HSEM->C1IER &= ~(__SEM_MASK__)) :       \
00071                                              (HSEM->C2IER &= ~(__SEM_MASK__)))
00072 #else
00073 #define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->IER &= ~(__SEM_MASK__))
00074 #endif /* DUAL_CORE */
00075
00076 /**
00077   * @brief  Checks whether interrupt has occurred or not for semaphores specified by a mask.
00078   * @param  __SEM_MASK__: semaphores Mask
00079   * @retval semaphores Mask : Semaphores where an interrupt occurred.
00080   */
00081 #if defined(DUAL_CORE)
00082 #define __HAL_HSEM_GET_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
00083                                          ((__SEM_MASK__) & HSEM->C1MISR) :        \
00084                                          ((__SEM_MASK__) & HSEM->C2MISR1))
00085 #else
00086 #define __HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->MISR)
00087 #endif /* DUAL_CORE */
00088
00089 /**
00090   * @brief  Get the semaphores release status flags.
00091   * @param  __SEM_MASK__: semaphores Mask
00092   * @retval semaphores Mask : Semaphores where Release flags rise.
00093   */
00094 #if defined(DUAL_CORE)
00095 #define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
00096                                            (__SEM_MASK__) & HSEM->C1ISR :           \
00097                                            (__SEM_MASK__) & HSEM->C2ISR)
00098 #else
00099 #define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->ISR)
00100 #endif /* DUAL_CORE */
00101
00102 /**
00103   * @brief  Clears the HSEM Interrupt flags.
00104   * @param  __SEM_MASK__: semaphores Mask
00105   * @retval None.
00106   */
00107 #if defined(DUAL_CORE)
00108 #define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
00109                                              (HSEM->C1ICR |= (__SEM_MASK__)) :        \
00110                                              (HSEM->C2ICR |= (__SEM_MASK__)))
00111 #else
00112 #define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->ICR |= (__SEM_MASK__))
00113 #endif /* DUAL_CORE */
00114
00115 /**
00116   * @}
00117   */
00118
00119 /* Exported functions --------------------------------------------------------*/
00120 /** @defgroup HSEM_Exported_Functions HSEM Exported Functions
00121   * @{
00122   */
00123
00124 /** @addtogroup HSEM_Exported_Functions_Group1 Take and Release functions
00125   * @brief    HSEM Take and Release functions
00126   * @{
00127   */
00128
00129 /* HSEM semaphore take (lock) using 2-Step  method ****************************/
00130 HAL_StatusTypeDef  HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID);
00131 /* HSEM semaphore fast take (lock) using 1-Step  method ***********************/
00132 HAL_StatusTypeDef  HAL_HSEM_FastTake(uint32_t SemID);
00133 /* HSEM Check semaphore state Taken or not   **********************************/
00134 uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID);
00135 /* HSEM Release  **************************************************************/
00136 void  HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID);
00137 /* HSEM Release All************************************************************/
00138 void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID);
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @addtogroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions
00145   * @brief    HSEM Set and Get Key functions.
00146   * @{
00147   */
00148 /* HSEM Set Clear Key *********************************************************/
00149 void  HAL_HSEM_SetClearKey(uint32_t Key);
00150 /* HSEM Get Clear Key *********************************************************/
00151 uint32_t HAL_HSEM_GetClearKey(void);
00152 /**
00153   * @}
00154   */
00155
00156 /** @addtogroup HSEM_Exported_Functions_Group3
00157   * @brief   HSEM Notification functions
00158   * @{
00159   */
00160 /* HSEM Activate HSEM Notification (When a semaphore is released) ) *****************/
00161 void HAL_HSEM_ActivateNotification(uint32_t SemMask);
00162 /* HSEM Deactivate HSEM Notification (When a semaphore is released)  ****************/
00163 void HAL_HSEM_DeactivateNotification(uint32_t SemMask);
00164 /* HSEM Free Callback (When a semaphore is released)  *******************************/
00165 void HAL_HSEM_FreeCallback(uint32_t SemMask);
00166 /* HSEM IRQ Handler  **********************************************************/
00167 void HAL_HSEM_IRQHandler(void);
00168
00169 /**
00170   * @}
00171   */
00172
00173 /**
00174   * @}
00175   */
00176
00177 /* Private macros ------------------------------------------------------------*/
00178 /** @defgroup HSEM_Private_Macros HSEM Private Macros
00179   * @{
00180   */
00181
00182 #define IS_HSEM_SEMID(__SEMID__) ((__SEMID__) <= HSEM_SEMID_MAX )
00183
00184 #define IS_HSEM_PROCESSID(__PROCESSID__) ((__PROCESSID__) <= HSEM_PROCESSID_MAX )
00185
00186 #define IS_HSEM_KEY(__KEY__) ((__KEY__) <= HSEM_CLEAR_KEY_MAX )
00187
00188 #define IS_HSEM_COREID(__COREID__) (((__COREID__) == HSEM_CPU1_COREID) || \
00189                                     ((__COREID__) == HSEM_CPU2_COREID))
00190
00191
00192 /**
00193   * @}
00194   */
00195
00196 /**
00197   * @}
00198   */
00199
00200 /**
00201   * @}
00202   */
00203
00204 #ifdef __cplusplus
00205 }
00206 #endif
00207
00208 #endif /* STM32WBxx_HAL_HSEM_H */
00209
00210 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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STM32WB55xx HAL User Manual: stm32wbxx_hal_i2c.c Source File

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stm32wbxx_hal_i2c.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_i2c.c
00004   * @author  MCD Application Team
00005   * @brief   I2C HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Inter Integrated Circuit (I2C) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral State and Errors functions
00011   *
00012   @verbatim
00013   ==============================================================================
00014                         ##### How to use this driver #####
00015   ==============================================================================
00016     [..]
00017     The I2C HAL driver can be used as follows:
00018
00019     (#) Declare a I2C_HandleTypeDef handle structure, for example:
00020         I2C_HandleTypeDef  hi2c;
00021
00022     (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API:
00023         (##) Enable the I2Cx interface clock
00024         (##) I2C pins configuration
00025             (+++) Enable the clock for the I2C GPIOs
00026             (+++) Configure I2C pins as alternate function open-drain
00027         (##) NVIC configuration if you need to use interrupt process
00028             (+++) Configure the I2Cx interrupt priority
00029             (+++) Enable the NVIC I2C IRQ Channel
00030         (##) DMA Configuration if you need to use DMA process
00031             (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
00032             (+++) Enable the DMAx interface clock using
00033             (+++) Configure the DMA handle parameters
00034             (+++) Configure the DMA Tx or Rx channel
00035             (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
00036             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
00037                   the DMA Tx or Rx channel
00038
00039     (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
00040         Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
00041
00042     (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware
00043         (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit(&hi2c) API.
00044
00045     (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady()
00046
00047     (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
00048
00049     *** Polling mode IO operation ***
00050     =================================
00051     [..]
00052       (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit()
00053       (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive()
00054       (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit()
00055       (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive()
00056
00057     *** Polling mode IO MEM operation ***
00058     =====================================
00059     [..]
00060       (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write()
00061       (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read()
00062
00063
00064     *** Interrupt mode IO operation ***
00065     ===================================
00066     [..]
00067       (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT()
00068       (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
00069            add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
00070       (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT()
00071       (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
00072            add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
00073       (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT()
00074       (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
00075            add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
00076       (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT()
00077       (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
00078            add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
00079       (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
00080            add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
00081       (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
00082       (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
00083            add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
00084       (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
00085            This action will inform Master to generate a Stop condition to discard the communication.
00086
00087
00088     *** Interrupt mode or DMA mode IO sequential operation ***
00089     ==========================================================
00090     [..]
00091       (@) These interfaces allow to manage a sequential transfer with a repeated start condition
00092           when a direction change during transfer
00093     [..]
00094       (+) A specific option field manage the different steps of a sequential transfer
00095       (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
00096       (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
00097       (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
00098                             and data to transfer without a final stop condition
00099       (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
00100                             and data to transfer without a final stop condition, an then permit a call the same master sequential interface
00101                             several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT()
00102                             or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA())
00103       (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
00104                             and with new data to transfer if the direction change or manage only the new data to transfer
00105                             if no direction change and without a final stop condition in both cases
00106       (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
00107                             and with new data to transfer if the direction change or manage only the new data to transfer
00108                             if no direction change and with a final stop condition in both cases
00109       (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential
00110                             interface several times (link with option I2C_FIRST_AND_NEXT_FRAME).
00111                             Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
00112                               or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
00113                               or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
00114                               or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).
00115                             Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit
00116                               without stopping the communication and so generate a restart condition.
00117       (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential
00118                             interface.
00119                             Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
00120                               or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
00121                               or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
00122                               or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME).
00123                             Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition.
00124
00125       (+) Differents sequential I2C interfaces are listed below:
00126       (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT()
00127             or using @ref HAL_I2C_Master_Seq_Transmit_DMA()
00128       (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
00129            add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
00130       (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Receive_IT()
00131             or using @ref HAL_I2C_Master_Seq_Receive_DMA()
00132       (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
00133            add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
00134       (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
00135       (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
00136            add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
00137       (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT()
00138       (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can
00139            add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
00140       (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can
00141            add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback()
00142       (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Transmit_IT()
00143             or using @ref HAL_I2C_Slave_Seq_Transmit_DMA()
00144       (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
00145            add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
00146       (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Receive_IT()
00147             or using @ref HAL_I2C_Slave_Seq_Receive_DMA()
00148       (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
00149            add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
00150       (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
00151            add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
00152       (++) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
00153            This action will inform Master to generate a Stop condition to discard the communication.
00154
00155     *** Interrupt mode IO MEM operation ***
00156     =======================================
00157     [..]
00158       (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
00159           @ref HAL_I2C_Mem_Write_IT()
00160       (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
00161            add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
00162       (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
00163           @ref HAL_I2C_Mem_Read_IT()
00164       (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
00165            add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
00166       (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
00167            add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
00168
00169     *** DMA mode IO operation ***
00170     ==============================
00171     [..]
00172       (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
00173           @ref HAL_I2C_Master_Transmit_DMA()
00174       (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
00175            add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
00176       (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
00177           @ref HAL_I2C_Master_Receive_DMA()
00178       (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
00179            add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
00180       (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
00181           @ref HAL_I2C_Slave_Transmit_DMA()
00182       (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
00183            add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
00184       (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
00185           @ref HAL_I2C_Slave_Receive_DMA()
00186       (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
00187            add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
00188       (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
00189            add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
00190       (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
00191       (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
00192            add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
00193       (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
00194            This action will inform Master to generate a Stop condition to discard the communication.
00195
00196     *** DMA mode IO MEM operation ***
00197     =================================
00198     [..]
00199       (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
00200           @ref HAL_I2C_Mem_Write_DMA()
00201       (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
00202            add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
00203       (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
00204           @ref HAL_I2C_Mem_Read_DMA()
00205       (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
00206            add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
00207       (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
00208            add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
00209
00210
00211      *** I2C HAL driver macros list ***
00212      ==================================
00213      [..]
00214        Below the list of most used macros in I2C HAL driver.
00215
00216       (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral
00217       (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral
00218       (+) @ref __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
00219       (+) @ref __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
00220       (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
00221       (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
00222       (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
00223
00224      *** Callback registration ***
00225      =============================================
00226     [..]
00227      The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
00228      allows the user to configure dynamically the driver callbacks.
00229      Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback()
00230      to register an interrupt callback.
00231     [..]
00232      Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks:
00233        (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
00234        (+) MasterRxCpltCallback : callback for Master reception end of transfer.
00235        (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
00236        (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
00237        (+) ListenCpltCallback   : callback for end of listen mode.
00238        (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
00239        (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
00240        (+) ErrorCallback        : callback for error detection.
00241        (+) AbortCpltCallback    : callback for abort completion process.
00242        (+) MspInitCallback      : callback for Msp Init.
00243        (+) MspDeInitCallback    : callback for Msp DeInit.
00244      This function takes as parameters the HAL peripheral handle, the Callback ID
00245      and a pointer to the user callback function.
00246     [..]
00247      For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback().
00248     [..]
00249      Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default
00250      weak function.
00251      @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
00252      and the Callback ID.
00253      This function allows to reset following callbacks:
00254        (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
00255        (+) MasterRxCpltCallback : callback for Master reception end of transfer.
00256        (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
00257        (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
00258        (+) ListenCpltCallback   : callback for end of listen mode.
00259        (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
00260        (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
00261        (+) ErrorCallback        : callback for error detection.
00262        (+) AbortCpltCallback    : callback for abort completion process.
00263        (+) MspInitCallback      : callback for Msp Init.
00264        (+) MspDeInitCallback    : callback for Msp DeInit.
00265     [..]
00266      For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback().
00267     [..]
00268      By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET
00269      all callbacks are set to the corresponding weak functions:
00270      examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback().
00271      Exception done for MspInit and MspDeInit functions that are
00272      reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when
00273      these callbacks are null (not registered beforehand).
00274      If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit()
00275      keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
00276     [..]
00277      Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
00278      Exception done MspInit/MspDeInit functions that can be registered/unregistered
00279      in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
00280      thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00281      Then, the user first registers the MspInit/MspDeInit user callbacks
00282      using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit()
00283      or @ref HAL_I2C_Init() function.
00284     [..]
00285      When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
00286      not defined, the callback registration feature is not available and all callbacks
00287      are set to the corresponding weak functions.
00288
00289      [..]
00290        (@) You can refer to the I2C HAL driver header file for more useful macros
00291
00292   @endverbatim
00293   ******************************************************************************
00294   * @attention
00295   *
00296   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00297   * All rights reserved.</center></h2>
00298   *
00299   * This software component is licensed by ST under BSD 3-Clause license,
00300   * the "License"; You may not use this file except in compliance with the
00301   * License. You may obtain a copy of the License at:
00302   *                        opensource.org/licenses/BSD-3-Clause
00303   *
00304   ******************************************************************************
00305   */
00306
00307 /* Includes ------------------------------------------------------------------*/
00308 #include "stm32wbxx_hal.h"
00309
00310 /** @addtogroup STM32WBxx_HAL_Driver
00311   * @{
00312   */
00313
00314 /** @defgroup I2C I2C
00315   * @brief I2C HAL module driver
00316   * @{
00317   */
00318
00319 #ifdef HAL_I2C_MODULE_ENABLED
00320
00321 /* Private typedef -----------------------------------------------------------*/
00322 /* Private define ------------------------------------------------------------*/
00323
00324 /** @defgroup I2C_Private_Define I2C Private Define
00325   * @{
00326   */
00327 #define TIMING_CLEAR_MASK   (0xF0FFFFFFU)  /*!< I2C TIMING clear register Mask */
00328 #define I2C_TIMEOUT_ADDR    (10000U)       /*!< 10 s  */
00329 #define I2C_TIMEOUT_BUSY    (25U)          /*!< 25 ms */
00330 #define I2C_TIMEOUT_DIR     (25U)          /*!< 25 ms */
00331 #define I2C_TIMEOUT_RXNE    (25U)          /*!< 25 ms */
00332 #define I2C_TIMEOUT_STOPF   (25U)          /*!< 25 ms */
00333 #define I2C_TIMEOUT_TC      (25U)          /*!< 25 ms */
00334 #define I2C_TIMEOUT_TCR     (25U)          /*!< 25 ms */
00335 #define I2C_TIMEOUT_TXIS    (25U)          /*!< 25 ms */
00336 #define I2C_TIMEOUT_FLAG    (25U)          /*!< 25 ms */
00337
00338 #define MAX_NBYTE_SIZE      255U
00339 #define SlaveAddr_SHIFT     7U
00340 #define SlaveAddr_MSK       0x06U
00341
00342 /* Private define for @ref PreviousState usage */
00343 #define I2C_STATE_MSK             ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits            */
00344 #define I2C_STATE_NONE            ((uint32_t)(HAL_I2C_MODE_NONE))                                                        /*!< Default Value                                          */
00345 #define I2C_STATE_MASTER_BUSY_TX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))            /*!< Master Busy TX, combinaison of State LSB and Mode enum */
00346 #define I2C_STATE_MASTER_BUSY_RX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))            /*!< Master Busy RX, combinaison of State LSB and Mode enum */
00347 #define I2C_STATE_SLAVE_BUSY_TX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))             /*!< Slave Busy TX, combinaison of State LSB and Mode enum  */
00348 #define I2C_STATE_SLAVE_BUSY_RX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))             /*!< Slave Busy RX, combinaison of State LSB and Mode enum  */
00349 #define I2C_STATE_MEM_BUSY_TX     ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM))               /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
00350 #define I2C_STATE_MEM_BUSY_RX     ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM))               /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
00351
00352
00353 /* Private define to centralize the enable/disable of Interrupts */
00354 #define I2C_XFER_TX_IT          (0x00000001U)
00355 #define I2C_XFER_RX_IT          (0x00000002U)
00356 #define I2C_XFER_LISTEN_IT      (0x00000004U)
00357
00358 #define I2C_XFER_ERROR_IT       (0x00000011U)
00359 #define I2C_XFER_CPLT_IT        (0x00000012U)
00360 #define I2C_XFER_RELOAD_IT      (0x00000012U)
00361
00362 /* Private define Sequential Transfer Options default/reset value */
00363 #define I2C_NO_OPTION_FRAME     (0xFFFF0000U)
00364 /**
00365   * @}
00366   */
00367
00368 /* Private macro -------------------------------------------------------------*/
00369 /* Private variables ---------------------------------------------------------*/
00370 /* Private function prototypes -----------------------------------------------*/
00371
00372 /** @defgroup I2C_Private_Functions I2C Private Functions
00373   * @{
00374   */
00375 /* Private functions to handle DMA transfer */
00376 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
00377 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
00378 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
00379 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
00380 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
00381 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
00382
00383 /* Private functions to handle IT transfer */
00384 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
00385 static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
00386 static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c);
00387 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
00388 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
00389 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
00390 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
00391
00392 /* Private functions to handle IT transfer */
00393 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
00394 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
00395
00396 /* Private functions for I2C transfer IRQ handler */
00397 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
00398 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
00399 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
00400 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
00401
00402 /* Private functions to handle flags during polling transfer */
00403 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
00404 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
00405 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
00406 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
00407 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
00408
00409 /* Private functions to centralize the enable/disable of Interrupts */
00410 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
00411 static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
00412
00413 /* Private function to flush TXDR register */
00414 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
00415
00416 /* Private function to handle  start, restart or stop a transfer */
00417 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
00418
00419 /* Private function to Convert Specific options */
00420 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
00421 /**
00422   * @}
00423   */
00424
00425 /* Exported functions --------------------------------------------------------*/
00426
00427 /** @defgroup I2C_Exported_Functions I2C Exported Functions
00428   * @{
00429   */
00430
00431 /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
00432  *  @brief    Initialization and Configuration functions
00433  *
00434 @verbatim
00435  ===============================================================================
00436               ##### Initialization and de-initialization functions #####
00437  ===============================================================================
00438     [..]  This subsection provides a set of functions allowing to initialize and
00439           deinitialize the I2Cx peripheral:
00440
00441       (+) User must Implement HAL_I2C_MspInit() function in which he configures
00442           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00443
00444       (+) Call the function HAL_I2C_Init() to configure the selected device with
00445           the selected configuration:
00446         (++) Clock Timing
00447         (++) Own Address 1
00448         (++) Addressing mode (Master, Slave)
00449         (++) Dual Addressing mode
00450         (++) Own Address 2
00451         (++) Own Address 2 Mask
00452         (++) General call mode
00453         (++) Nostretch mode
00454
00455       (+) Call the function HAL_I2C_DeInit() to restore the default configuration
00456           of the selected I2Cx peripheral.
00457
00458 @endverbatim
00459   * @{
00460   */
00461
00462 /**
00463   * @brief  Initializes the I2C according to the specified parameters
00464   *         in the I2C_InitTypeDef and initialize the associated handle.
00465   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00466   *                the configuration information for the specified I2C.
00467   * @retval HAL status
00468   */
00469 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
00470 {
00471   /* Check the I2C handle allocation */
00472   if (hi2c == NULL)
00473   {
00474     return HAL_ERROR;
00475   }
00476
00477   /* Check the parameters */
00478   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00479   assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
00480   assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
00481   assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
00482   assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
00483   assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
00484   assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
00485   assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
00486
00487   if (hi2c->State == HAL_I2C_STATE_RESET)
00488   {
00489     /* Allocate lock resource and initialize it */
00490     hi2c->Lock = HAL_UNLOCKED;
00491
00492 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
00493     /* Init the I2C Callback settings */
00494     hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
00495     hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
00496     hi2c->SlaveTxCpltCallback  = HAL_I2C_SlaveTxCpltCallback;  /* Legacy weak SlaveTxCpltCallback  */
00497     hi2c->SlaveRxCpltCallback  = HAL_I2C_SlaveRxCpltCallback;  /* Legacy weak SlaveRxCpltCallback  */
00498     hi2c->ListenCpltCallback   = HAL_I2C_ListenCpltCallback;   /* Legacy weak ListenCpltCallback   */
00499     hi2c->MemTxCpltCallback    = HAL_I2C_MemTxCpltCallback;    /* Legacy weak MemTxCpltCallback    */
00500     hi2c->MemRxCpltCallback    = HAL_I2C_MemRxCpltCallback;    /* Legacy weak MemRxCpltCallback    */
00501     hi2c->ErrorCallback        = HAL_I2C_ErrorCallback;        /* Legacy weak ErrorCallback        */
00502     hi2c->AbortCpltCallback    = HAL_I2C_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    */
00503     hi2c->AddrCallback         = HAL_I2C_AddrCallback;         /* Legacy weak AddrCallback         */
00504
00505     if (hi2c->MspInitCallback == NULL)
00506     {
00507       hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit  */
00508     }
00509
00510     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00511     hi2c->MspInitCallback(hi2c);
00512 #else
00513     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00514     HAL_I2C_MspInit(hi2c);
00515 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
00516   }
00517
00518   hi2c->State = HAL_I2C_STATE_BUSY;
00519
00520   /* Disable the selected I2C peripheral */
00521   __HAL_I2C_DISABLE(hi2c);
00522
00523   /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
00524   /* Configure I2Cx: Frequency range */
00525   hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
00526
00527   /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
00528   /* Disable Own Address1 before set the Own Address1 configuration */
00529   hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
00530
00531   /* Configure I2Cx: Own Address1 and ack own address1 mode */
00532   if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
00533   {
00534     hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
00535   }
00536   else /* I2C_ADDRESSINGMODE_10BIT */
00537   {
00538     hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
00539   }
00540
00541   /*---------------------------- I2Cx CR2 Configuration ----------------------*/
00542   /* Configure I2Cx: Addressing Master mode */
00543   if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
00544   {
00545     hi2c->Instance->CR2 = (I2C_CR2_ADD10);
00546   }
00547   /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
00548   hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
00549
00550   /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
00551   /* Disable Own Address2 before set the Own Address2 configuration */
00552   hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
00553
00554   /* Configure I2Cx: Dual mode and Own Address2 */
00555   hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));
00556
00557   /*---------------------------- I2Cx CR1 Configuration ----------------------*/
00558   /* Configure I2Cx: Generalcall and NoStretch mode */
00559   hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
00560
00561   /* Enable the selected I2C peripheral */
00562   __HAL_I2C_ENABLE(hi2c);
00563
00564   hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00565   hi2c->State = HAL_I2C_STATE_READY;
00566   hi2c->PreviousState = I2C_STATE_NONE;
00567   hi2c->Mode = HAL_I2C_MODE_NONE;
00568
00569   return HAL_OK;
00570 }
00571
00572 /**
00573   * @brief  DeInitialize the I2C peripheral.
00574   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00575   *                the configuration information for the specified I2C.
00576   * @retval HAL status
00577   */
00578 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
00579 {
00580   /* Check the I2C handle allocation */
00581   if (hi2c == NULL)
00582   {
00583     return HAL_ERROR;
00584   }
00585
00586   /* Check the parameters */
00587   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00588
00589   hi2c->State = HAL_I2C_STATE_BUSY;
00590
00591   /* Disable the I2C Peripheral Clock */
00592   __HAL_I2C_DISABLE(hi2c);
00593
00594 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
00595   if (hi2c->MspDeInitCallback == NULL)
00596   {
00597     hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit  */
00598   }
00599
00600   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00601   hi2c->MspDeInitCallback(hi2c);
00602 #else
00603   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00604   HAL_I2C_MspDeInit(hi2c);
00605 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
00606
00607   hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00608   hi2c->State = HAL_I2C_STATE_RESET;
00609   hi2c->PreviousState = I2C_STATE_NONE;
00610   hi2c->Mode = HAL_I2C_MODE_NONE;
00611
00612   /* Release Lock */
00613   __HAL_UNLOCK(hi2c);
00614
00615   return HAL_OK;
00616 }
00617
00618 /**
00619   * @brief Initialize the I2C MSP.
00620   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00621   *                the configuration information for the specified I2C.
00622   * @retval None
00623   */
00624 __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
00625 {
00626   /* Prevent unused argument(s) compilation warning */
00627   UNUSED(hi2c);
00628
00629   /* NOTE : This function should not be modified, when the callback is needed,
00630             the HAL_I2C_MspInit could be implemented in the user file
00631    */
00632 }
00633
00634 /**
00635   * @brief DeInitialize the I2C MSP.
00636   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00637   *                the configuration information for the specified I2C.
00638   * @retval None
00639   */
00640 __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
00641 {
00642   /* Prevent unused argument(s) compilation warning */
00643   UNUSED(hi2c);
00644
00645   /* NOTE : This function should not be modified, when the callback is needed,
00646             the HAL_I2C_MspDeInit could be implemented in the user file
00647    */
00648 }
00649
00650 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
00651 /**
00652   * @brief  Register a User I2C Callback
00653   *         To be used instead of the weak predefined callback
00654   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00655   *                the configuration information for the specified I2C.
00656   * @param  CallbackID ID of the callback to be registered
00657   *         This parameter can be one of the following values:
00658   *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
00659   *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
00660   *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
00661   *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
00662   *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
00663   *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
00664   *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
00665   *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
00666   *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
00667   *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
00668   *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
00669   * @param  pCallback pointer to the Callback function
00670   * @retval HAL status
00671   */
00672 HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)
00673 {
00674   HAL_StatusTypeDef status = HAL_OK;
00675
00676   if (pCallback == NULL)
00677   {
00678     /* Update the error code */
00679     hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
00680
00681     return HAL_ERROR;
00682   }
00683   /* Process locked */
00684   __HAL_LOCK(hi2c);
00685
00686   if (HAL_I2C_STATE_READY == hi2c->State)
00687   {
00688     switch (CallbackID)
00689     {
00690       case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
00691         hi2c->MasterTxCpltCallback = pCallback;
00692         break;
00693
00694       case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
00695         hi2c->MasterRxCpltCallback = pCallback;
00696         break;
00697
00698       case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
00699         hi2c->SlaveTxCpltCallback = pCallback;
00700         break;
00701
00702       case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
00703         hi2c->SlaveRxCpltCallback = pCallback;
00704         break;
00705
00706       case HAL_I2C_LISTEN_COMPLETE_CB_ID :
00707         hi2c->ListenCpltCallback = pCallback;
00708         break;
00709
00710       case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
00711         hi2c->MemTxCpltCallback = pCallback;
00712         break;
00713
00714       case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
00715         hi2c->MemRxCpltCallback = pCallback;
00716         break;
00717
00718       case HAL_I2C_ERROR_CB_ID :
00719         hi2c->ErrorCallback = pCallback;
00720         break;
00721
00722       case HAL_I2C_ABORT_CB_ID :
00723         hi2c->AbortCpltCallback = pCallback;
00724         break;
00725
00726       case HAL_I2C_MSPINIT_CB_ID :
00727         hi2c->MspInitCallback = pCallback;
00728         break;
00729
00730       case HAL_I2C_MSPDEINIT_CB_ID :
00731         hi2c->MspDeInitCallback = pCallback;
00732         break;
00733
00734       default :
00735         /* Update the error code */
00736         hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
00737
00738         /* Return error status */
00739         status =  HAL_ERROR;
00740         break;
00741     }
00742   }
00743   else if (HAL_I2C_STATE_RESET == hi2c->State)
00744   {
00745     switch (CallbackID)
00746     {
00747       case HAL_I2C_MSPINIT_CB_ID :
00748         hi2c->MspInitCallback = pCallback;
00749         break;
00750
00751       case HAL_I2C_MSPDEINIT_CB_ID :
00752         hi2c->MspDeInitCallback = pCallback;
00753         break;
00754
00755       default :
00756         /* Update the error code */
00757         hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
00758
00759         /* Return error status */
00760         status =  HAL_ERROR;
00761         break;
00762     }
00763   }
00764   else
00765   {
00766     /* Update the error code */
00767     hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
00768
00769     /* Return error status */
00770     status =  HAL_ERROR;
00771   }
00772
00773   /* Release Lock */
00774   __HAL_UNLOCK(hi2c);
00775   return status;
00776 }
00777
00778 /**
00779   * @brief  Unregister an I2C Callback
00780   *         I2C callback is redirected to the weak predefined callback
00781   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00782   *                the configuration information for the specified I2C.
00783   * @param  CallbackID ID of the callback to be unregistered
00784   *         This parameter can be one of the following values:
00785   *         This parameter can be one of the following values:
00786   *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
00787   *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
00788   *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
00789   *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
00790   *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
00791   *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
00792   *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
00793   *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
00794   *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
00795   *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
00796   *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
00797   * @retval HAL status
00798   */
00799 HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
00800 {
00801   HAL_StatusTypeDef status = HAL_OK;
00802
00803   /* Process locked */
00804   __HAL_LOCK(hi2c);
00805
00806   if (HAL_I2C_STATE_READY == hi2c->State)
00807   {
00808     switch (CallbackID)
00809     {
00810       case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
00811         hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
00812         break;
00813
00814       case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
00815         hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
00816         break;
00817
00818       case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
00819         hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback;   /* Legacy weak SlaveTxCpltCallback  */
00820         break;
00821
00822       case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
00823         hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback;   /* Legacy weak SlaveRxCpltCallback  */
00824         break;
00825
00826       case HAL_I2C_LISTEN_COMPLETE_CB_ID :
00827         hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback;     /* Legacy weak ListenCpltCallback   */
00828         break;
00829
00830       case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
00831         hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback;       /* Legacy weak MemTxCpltCallback    */
00832         break;
00833
00834       case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
00835         hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback;       /* Legacy weak MemRxCpltCallback    */
00836         break;
00837
00838       case HAL_I2C_ERROR_CB_ID :
00839         hi2c->ErrorCallback = HAL_I2C_ErrorCallback;               /* Legacy weak ErrorCallback        */
00840         break;
00841
00842       case HAL_I2C_ABORT_CB_ID :
00843         hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback;       /* Legacy weak AbortCpltCallback    */
00844         break;
00845
00846       case HAL_I2C_MSPINIT_CB_ID :
00847         hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit              */
00848         break;
00849
00850       case HAL_I2C_MSPDEINIT_CB_ID :
00851         hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit            */
00852         break;
00853
00854       default :
00855         /* Update the error code */
00856         hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
00857
00858         /* Return error status */
00859         status =  HAL_ERROR;
00860         break;
00861     }
00862   }
00863   else if (HAL_I2C_STATE_RESET == hi2c->State)
00864   {
00865     switch (CallbackID)
00866     {
00867       case HAL_I2C_MSPINIT_CB_ID :
00868         hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit              */
00869         break;
00870
00871       case HAL_I2C_MSPDEINIT_CB_ID :
00872         hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit            */
00873         break;
00874
00875       default :
00876         /* Update the error code */
00877         hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
00878
00879         /* Return error status */
00880         status =  HAL_ERROR;
00881         break;
00882     }
00883   }
00884   else
00885   {
00886     /* Update the error code */
00887     hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
00888
00889     /* Return error status */
00890     status =  HAL_ERROR;
00891   }
00892
00893   /* Release Lock */
00894   __HAL_UNLOCK(hi2c);
00895   return status;
00896 }
00897
00898 /**
00899   * @brief  Register the Slave Address Match I2C Callback
00900   *         To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
00901   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00902   *                the configuration information for the specified I2C.
00903   * @param  pCallback pointer to the Address Match Callback function
00904   * @retval HAL status
00905   */
00906 HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
00907 {
00908   HAL_StatusTypeDef status = HAL_OK;
00909
00910   if (pCallback == NULL)
00911   {
00912     /* Update the error code */
00913     hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
00914
00915     return HAL_ERROR;
00916   }
00917   /* Process locked */
00918   __HAL_LOCK(hi2c);
00919
00920   if (HAL_I2C_STATE_READY == hi2c->State)
00921   {
00922     hi2c->AddrCallback = pCallback;
00923   }
00924   else
00925   {
00926     /* Update the error code */
00927     hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
00928
00929     /* Return error status */
00930     status =  HAL_ERROR;
00931   }
00932
00933   /* Release Lock */
00934   __HAL_UNLOCK(hi2c);
00935   return status;
00936 }
00937
00938 /**
00939   * @brief  UnRegister the Slave Address Match I2C Callback
00940   *         Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
00941   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00942   *                the configuration information for the specified I2C.
00943   * @retval HAL status
00944   */
00945 HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
00946 {
00947   HAL_StatusTypeDef status = HAL_OK;
00948
00949   /* Process locked */
00950   __HAL_LOCK(hi2c);
00951
00952   if (HAL_I2C_STATE_READY == hi2c->State)
00953   {
00954     hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback  */
00955   }
00956   else
00957   {
00958     /* Update the error code */
00959     hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
00960
00961     /* Return error status */
00962     status =  HAL_ERROR;
00963   }
00964
00965   /* Release Lock */
00966   __HAL_UNLOCK(hi2c);
00967   return status;
00968 }
00969
00970 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
00971
00972 /**
00973   * @}
00974   */
00975
00976 /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
00977  *  @brief   Data transfers functions
00978  *
00979 @verbatim
00980  ===============================================================================
00981                       ##### IO operation functions #####
00982  ===============================================================================
00983     [..]
00984     This subsection provides a set of functions allowing to manage the I2C data
00985     transfers.
00986
00987     (#) There are two modes of transfer:
00988        (++) Blocking mode : The communication is performed in the polling mode.
00989             The status of all data processing is returned by the same function
00990             after finishing transfer.
00991        (++) No-Blocking mode : The communication is performed using Interrupts
00992             or DMA. These functions return the status of the transfer startup.
00993             The end of the data processing will be indicated through the
00994             dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
00995             using DMA mode.
00996
00997     (#) Blocking mode functions are :
00998         (++) HAL_I2C_Master_Transmit()
00999         (++) HAL_I2C_Master_Receive()
01000         (++) HAL_I2C_Slave_Transmit()
01001         (++) HAL_I2C_Slave_Receive()
01002         (++) HAL_I2C_Mem_Write()
01003         (++) HAL_I2C_Mem_Read()
01004         (++) HAL_I2C_IsDeviceReady()
01005
01006     (#) No-Blocking mode functions with Interrupt are :
01007         (++) HAL_I2C_Master_Transmit_IT()
01008         (++) HAL_I2C_Master_Receive_IT()
01009         (++) HAL_I2C_Slave_Transmit_IT()
01010         (++) HAL_I2C_Slave_Receive_IT()
01011         (++) HAL_I2C_Mem_Write_IT()
01012         (++) HAL_I2C_Mem_Read_IT()
01013         (++) HAL_I2C_Master_Seq_Transmit_IT()
01014         (++) HAL_I2C_Master_Seq_Receive_IT()
01015         (++) HAL_I2C_Slave_Seq_Transmit_IT()
01016         (++) HAL_I2C_Slave_Seq_Receive_IT()
01017         (++) HAL_I2C_EnableListen_IT()
01018         (++) HAL_I2C_DisableListen_IT()
01019         (++) HAL_I2C_Master_Abort_IT()
01020
01021     (#) No-Blocking mode functions with DMA are :
01022         (++) HAL_I2C_Master_Transmit_DMA()
01023         (++) HAL_I2C_Master_Receive_DMA()
01024         (++) HAL_I2C_Slave_Transmit_DMA()
01025         (++) HAL_I2C_Slave_Receive_DMA()
01026         (++) HAL_I2C_Mem_Write_DMA()
01027         (++) HAL_I2C_Mem_Read_DMA()
01028         (++) HAL_I2C_Master_Seq_Transmit_DMA()
01029         (++) HAL_I2C_Master_Seq_Receive_DMA()
01030         (++) HAL_I2C_Slave_Seq_Transmit_DMA()
01031         (++) HAL_I2C_Slave_Seq_Receive_DMA()
01032
01033     (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
01034         (++) HAL_I2C_MasterTxCpltCallback()
01035         (++) HAL_I2C_MasterRxCpltCallback()
01036         (++) HAL_I2C_SlaveTxCpltCallback()
01037         (++) HAL_I2C_SlaveRxCpltCallback()
01038         (++) HAL_I2C_MemTxCpltCallback()
01039         (++) HAL_I2C_MemRxCpltCallback()
01040         (++) HAL_I2C_AddrCallback()
01041         (++) HAL_I2C_ListenCpltCallback()
01042         (++) HAL_I2C_ErrorCallback()
01043         (++) HAL_I2C_AbortCpltCallback()
01044
01045 @endverbatim
01046   * @{
01047   */
01048
01049 /**
01050   * @brief  Transmits in master mode an amount of data in blocking mode.
01051   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01052   *                the configuration information for the specified I2C.
01053   * @param  DevAddress Target device address: The device 7 bits address value
01054   *         in datasheet must be shifted to the left before calling the interface
01055   * @param  pData Pointer to data buffer
01056   * @param  Size Amount of data to be sent
01057   * @param  Timeout Timeout duration
01058   * @retval HAL status
01059   */
01060 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
01061 {
01062   uint32_t tickstart;
01063
01064   if (hi2c->State == HAL_I2C_STATE_READY)
01065   {
01066     /* Process Locked */
01067     __HAL_LOCK(hi2c);
01068
01069     /* Init tickstart for timeout management*/
01070     tickstart = HAL_GetTick();
01071
01072     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
01073     {
01074       return HAL_ERROR;
01075     }
01076
01077     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
01078     hi2c->Mode      = HAL_I2C_MODE_MASTER;
01079     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01080
01081     /* Prepare transfer parameters */
01082     hi2c->pBuffPtr  = pData;
01083     hi2c->XferCount = Size;
01084     hi2c->XferISR   = NULL;
01085
01086     /* Send Slave Address */
01087     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
01088     if (hi2c->XferCount > MAX_NBYTE_SIZE)
01089     {
01090       hi2c->XferSize = MAX_NBYTE_SIZE;
01091       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
01092     }
01093     else
01094     {
01095       hi2c->XferSize = hi2c->XferCount;
01096       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
01097     }
01098
01099     while (hi2c->XferCount > 0U)
01100     {
01101       /* Wait until TXIS flag is set */
01102       if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01103       {
01104         return HAL_ERROR;
01105       }
01106       /* Write data to TXDR */
01107       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
01108
01109       /* Increment Buffer pointer */
01110       hi2c->pBuffPtr++;
01111
01112       hi2c->XferCount--;
01113       hi2c->XferSize--;
01114
01115       if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
01116       {
01117         /* Wait until TCR flag is set */
01118         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
01119         {
01120           return HAL_ERROR;
01121         }
01122
01123         if (hi2c->XferCount > MAX_NBYTE_SIZE)
01124         {
01125           hi2c->XferSize = MAX_NBYTE_SIZE;
01126           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
01127         }
01128         else
01129         {
01130           hi2c->XferSize = hi2c->XferCount;
01131           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
01132         }
01133       }
01134     }
01135
01136     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
01137     /* Wait until STOPF flag is set */
01138     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01139     {
01140       return HAL_ERROR;
01141     }
01142
01143     /* Clear STOP Flag */
01144     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
01145
01146     /* Clear Configuration Register 2 */
01147     I2C_RESET_CR2(hi2c);
01148
01149     hi2c->State = HAL_I2C_STATE_READY;
01150     hi2c->Mode  = HAL_I2C_MODE_NONE;
01151
01152     /* Process Unlocked */
01153     __HAL_UNLOCK(hi2c);
01154
01155     return HAL_OK;
01156   }
01157   else
01158   {
01159     return HAL_BUSY;
01160   }
01161 }
01162
01163 /**
01164   * @brief  Receives in master mode an amount of data in blocking mode.
01165   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01166   *                the configuration information for the specified I2C.
01167   * @param  DevAddress Target device address: The device 7 bits address value
01168   *         in datasheet must be shifted to the left before calling the interface
01169   * @param  pData Pointer to data buffer
01170   * @param  Size Amount of data to be sent
01171   * @param  Timeout Timeout duration
01172   * @retval HAL status
01173   */
01174 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
01175 {
01176   uint32_t tickstart;
01177
01178   if (hi2c->State == HAL_I2C_STATE_READY)
01179   {
01180     /* Process Locked */
01181     __HAL_LOCK(hi2c);
01182
01183     /* Init tickstart for timeout management*/
01184     tickstart = HAL_GetTick();
01185
01186     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
01187     {
01188       return HAL_ERROR;
01189     }
01190
01191     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
01192     hi2c->Mode      = HAL_I2C_MODE_MASTER;
01193     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01194
01195     /* Prepare transfer parameters */
01196     hi2c->pBuffPtr  = pData;
01197     hi2c->XferCount = Size;
01198     hi2c->XferISR   = NULL;
01199
01200     /* Send Slave Address */
01201     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
01202     if (hi2c->XferCount > MAX_NBYTE_SIZE)
01203     {
01204       hi2c->XferSize = MAX_NBYTE_SIZE;
01205       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
01206     }
01207     else
01208     {
01209       hi2c->XferSize = hi2c->XferCount;
01210       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
01211     }
01212
01213     while (hi2c->XferCount > 0U)
01214     {
01215       /* Wait until RXNE flag is set */
01216       if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01217       {
01218         return HAL_ERROR;
01219       }
01220
01221       /* Read data from RXDR */
01222       *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
01223
01224       /* Increment Buffer pointer */
01225       hi2c->pBuffPtr++;
01226
01227       hi2c->XferSize--;
01228       hi2c->XferCount--;
01229
01230       if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
01231       {
01232         /* Wait until TCR flag is set */
01233         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
01234         {
01235           return HAL_ERROR;
01236         }
01237
01238         if (hi2c->XferCount > MAX_NBYTE_SIZE)
01239         {
01240           hi2c->XferSize = MAX_NBYTE_SIZE;
01241           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
01242         }
01243         else
01244         {
01245           hi2c->XferSize = hi2c->XferCount;
01246           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
01247         }
01248       }
01249     }
01250
01251     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
01252     /* Wait until STOPF flag is set */
01253     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01254     {
01255       return HAL_ERROR;
01256     }
01257
01258     /* Clear STOP Flag */
01259     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
01260
01261     /* Clear Configuration Register 2 */
01262     I2C_RESET_CR2(hi2c);
01263
01264     hi2c->State = HAL_I2C_STATE_READY;
01265     hi2c->Mode  = HAL_I2C_MODE_NONE;
01266
01267     /* Process Unlocked */
01268     __HAL_UNLOCK(hi2c);
01269
01270     return HAL_OK;
01271   }
01272   else
01273   {
01274     return HAL_BUSY;
01275   }
01276 }
01277
01278 /**
01279   * @brief  Transmits in slave mode an amount of data in blocking mode.
01280   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01281   *                the configuration information for the specified I2C.
01282   * @param  pData Pointer to data buffer
01283   * @param  Size Amount of data to be sent
01284   * @param  Timeout Timeout duration
01285   * @retval HAL status
01286   */
01287 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
01288 {
01289   uint32_t tickstart;
01290
01291   if (hi2c->State == HAL_I2C_STATE_READY)
01292   {
01293     if ((pData == NULL) || (Size == 0U))
01294     {
01295       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
01296       return  HAL_ERROR;
01297     }
01298     /* Process Locked */
01299     __HAL_LOCK(hi2c);
01300
01301     /* Init tickstart for timeout management*/
01302     tickstart = HAL_GetTick();
01303
01304     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
01305     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
01306     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01307
01308     /* Prepare transfer parameters */
01309     hi2c->pBuffPtr  = pData;
01310     hi2c->XferCount = Size;
01311     hi2c->XferISR   = NULL;
01312
01313     /* Enable Address Acknowledge */
01314     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01315
01316     /* Wait until ADDR flag is set */
01317     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
01318     {
01319       /* Disable Address Acknowledge */
01320       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01321       return HAL_ERROR;
01322     }
01323
01324     /* Clear ADDR flag */
01325     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
01326
01327     /* If 10bit addressing mode is selected */
01328     if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
01329     {
01330       /* Wait until ADDR flag is set */
01331       if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
01332       {
01333         /* Disable Address Acknowledge */
01334         hi2c->Instance->CR2 |= I2C_CR2_NACK;
01335         return HAL_ERROR;
01336       }
01337
01338       /* Clear ADDR flag */
01339       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
01340     }
01341
01342     /* Wait until DIR flag is set Transmitter mode */
01343     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
01344     {
01345       /* Disable Address Acknowledge */
01346       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01347       return HAL_ERROR;
01348     }
01349
01350     while (hi2c->XferCount > 0U)
01351     {
01352       /* Wait until TXIS flag is set */
01353       if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01354       {
01355         /* Disable Address Acknowledge */
01356         hi2c->Instance->CR2 |= I2C_CR2_NACK;
01357         return HAL_ERROR;
01358       }
01359
01360       /* Write data to TXDR */
01361       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
01362
01363       /* Increment Buffer pointer */
01364       hi2c->pBuffPtr++;
01365
01366       hi2c->XferCount--;
01367     }
01368
01369     /* Wait until STOP flag is set */
01370     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01371     {
01372       /* Disable Address Acknowledge */
01373       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01374
01375       if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01376       {
01377         /* Normal use case for Transmitter mode */
01378         /* A NACK is generated to confirm the end of transfer */
01379         hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01380       }
01381       else
01382       {
01383         return HAL_ERROR;
01384       }
01385     }
01386
01387     /* Clear STOP flag */
01388     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
01389
01390     /* Wait until BUSY flag is reset */
01391     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
01392     {
01393       /* Disable Address Acknowledge */
01394       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01395       return HAL_ERROR;
01396     }
01397
01398     /* Disable Address Acknowledge */
01399     hi2c->Instance->CR2 |= I2C_CR2_NACK;
01400
01401     hi2c->State = HAL_I2C_STATE_READY;
01402     hi2c->Mode  = HAL_I2C_MODE_NONE;
01403
01404     /* Process Unlocked */
01405     __HAL_UNLOCK(hi2c);
01406
01407     return HAL_OK;
01408   }
01409   else
01410   {
01411     return HAL_BUSY;
01412   }
01413 }
01414
01415 /**
01416   * @brief  Receive in slave mode an amount of data in blocking mode
01417   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01418   *                the configuration information for the specified I2C.
01419   * @param  pData Pointer to data buffer
01420   * @param  Size Amount of data to be sent
01421   * @param  Timeout Timeout duration
01422   * @retval HAL status
01423   */
01424 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
01425 {
01426   uint32_t tickstart;
01427
01428   if (hi2c->State == HAL_I2C_STATE_READY)
01429   {
01430     if ((pData == NULL) || (Size == 0U))
01431     {
01432       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
01433       return  HAL_ERROR;
01434     }
01435     /* Process Locked */
01436     __HAL_LOCK(hi2c);
01437
01438     /* Init tickstart for timeout management*/
01439     tickstart = HAL_GetTick();
01440
01441     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
01442     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
01443     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01444
01445     /* Prepare transfer parameters */
01446     hi2c->pBuffPtr  = pData;
01447     hi2c->XferCount = Size;
01448     hi2c->XferISR   = NULL;
01449
01450     /* Enable Address Acknowledge */
01451     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01452
01453     /* Wait until ADDR flag is set */
01454     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
01455     {
01456       /* Disable Address Acknowledge */
01457       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01458       return HAL_ERROR;
01459     }
01460
01461     /* Clear ADDR flag */
01462     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
01463
01464     /* Wait until DIR flag is reset Receiver mode */
01465     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
01466     {
01467       /* Disable Address Acknowledge */
01468       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01469       return HAL_ERROR;
01470     }
01471
01472     while (hi2c->XferCount > 0U)
01473     {
01474       /* Wait until RXNE flag is set */
01475       if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01476       {
01477         /* Disable Address Acknowledge */
01478         hi2c->Instance->CR2 |= I2C_CR2_NACK;
01479
01480         /* Store Last receive data if any */
01481         if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
01482         {
01483           /* Read data from RXDR */
01484           *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
01485
01486           /* Increment Buffer pointer */
01487           hi2c->pBuffPtr++;
01488
01489           hi2c->XferCount--;
01490         }
01491
01492         return HAL_ERROR;
01493       }
01494
01495       /* Read data from RXDR */
01496       *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
01497
01498       /* Increment Buffer pointer */
01499       hi2c->pBuffPtr++;
01500
01501       hi2c->XferCount--;
01502     }
01503
01504     /* Wait until STOP flag is set */
01505     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01506     {
01507       /* Disable Address Acknowledge */
01508       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01509       return HAL_ERROR;
01510     }
01511
01512     /* Clear STOP flag */
01513     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
01514
01515     /* Wait until BUSY flag is reset */
01516     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
01517     {
01518       /* Disable Address Acknowledge */
01519       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01520       return HAL_ERROR;
01521     }
01522
01523     /* Disable Address Acknowledge */
01524     hi2c->Instance->CR2 |= I2C_CR2_NACK;
01525
01526     hi2c->State = HAL_I2C_STATE_READY;
01527     hi2c->Mode  = HAL_I2C_MODE_NONE;
01528
01529     /* Process Unlocked */
01530     __HAL_UNLOCK(hi2c);
01531
01532     return HAL_OK;
01533   }
01534   else
01535   {
01536     return HAL_BUSY;
01537   }
01538 }
01539
01540 /**
01541   * @brief  Transmit in master mode an amount of data in non-blocking mode with Interrupt
01542   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01543   *                the configuration information for the specified I2C.
01544   * @param  DevAddress Target device address: The device 7 bits address value
01545   *         in datasheet must be shifted to the left before calling the interface
01546   * @param  pData Pointer to data buffer
01547   * @param  Size Amount of data to be sent
01548   * @retval HAL status
01549   */
01550 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
01551 {
01552   uint32_t xfermode;
01553
01554   if (hi2c->State == HAL_I2C_STATE_READY)
01555   {
01556     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
01557     {
01558       return HAL_BUSY;
01559     }
01560
01561     /* Process Locked */
01562     __HAL_LOCK(hi2c);
01563
01564     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
01565     hi2c->Mode        = HAL_I2C_MODE_MASTER;
01566     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01567
01568     /* Prepare transfer parameters */
01569     hi2c->pBuffPtr    = pData;
01570     hi2c->XferCount   = Size;
01571     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01572     hi2c->XferISR     = I2C_Master_ISR_IT;
01573
01574     if (hi2c->XferCount > MAX_NBYTE_SIZE)
01575     {
01576       hi2c->XferSize = MAX_NBYTE_SIZE;
01577       xfermode = I2C_RELOAD_MODE;
01578     }
01579     else
01580     {
01581       hi2c->XferSize = hi2c->XferCount;
01582       xfermode = I2C_AUTOEND_MODE;
01583     }
01584
01585     /* Send Slave Address */
01586     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
01587     I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
01588
01589     /* Process Unlocked */
01590     __HAL_UNLOCK(hi2c);
01591
01592     /* Note : The I2C interrupts must be enabled after unlocking current process
01593               to avoid the risk of I2C interrupt handle execution before current
01594               process unlock */
01595
01596     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
01597     /* possible to enable all of these */
01598     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01599     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
01600
01601     return HAL_OK;
01602   }
01603   else
01604   {
01605     return HAL_BUSY;
01606   }
01607 }
01608
01609 /**
01610   * @brief  Receive in master mode an amount of data in non-blocking mode with Interrupt
01611   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01612   *                the configuration information for the specified I2C.
01613   * @param  DevAddress Target device address: The device 7 bits address value
01614   *         in datasheet must be shifted to the left before calling the interface
01615   * @param  pData Pointer to data buffer
01616   * @param  Size Amount of data to be sent
01617   * @retval HAL status
01618   */
01619 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
01620 {
01621   uint32_t xfermode;
01622
01623   if (hi2c->State == HAL_I2C_STATE_READY)
01624   {
01625     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
01626     {
01627       return HAL_BUSY;
01628     }
01629
01630     /* Process Locked */
01631     __HAL_LOCK(hi2c);
01632
01633     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
01634     hi2c->Mode        = HAL_I2C_MODE_MASTER;
01635     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01636
01637     /* Prepare transfer parameters */
01638     hi2c->pBuffPtr    = pData;
01639     hi2c->XferCount   = Size;
01640     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01641     hi2c->XferISR     = I2C_Master_ISR_IT;
01642
01643     if (hi2c->XferCount > MAX_NBYTE_SIZE)
01644     {
01645       hi2c->XferSize = MAX_NBYTE_SIZE;
01646       xfermode = I2C_RELOAD_MODE;
01647     }
01648     else
01649     {
01650       hi2c->XferSize = hi2c->XferCount;
01651       xfermode = I2C_AUTOEND_MODE;
01652     }
01653
01654     /* Send Slave Address */
01655     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
01656     I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
01657
01658     /* Process Unlocked */
01659     __HAL_UNLOCK(hi2c);
01660
01661     /* Note : The I2C interrupts must be enabled after unlocking current process
01662               to avoid the risk of I2C interrupt handle execution before current
01663               process unlock */
01664
01665     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
01666     /* possible to enable all of these */
01667     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01668     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
01669
01670     return HAL_OK;
01671   }
01672   else
01673   {
01674     return HAL_BUSY;
01675   }
01676 }
01677
01678 /**
01679   * @brief  Transmit in slave mode an amount of data in non-blocking mode with Interrupt
01680   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01681   *                the configuration information for the specified I2C.
01682   * @param  pData Pointer to data buffer
01683   * @param  Size Amount of data to be sent
01684   * @retval HAL status
01685   */
01686 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
01687 {
01688   if (hi2c->State == HAL_I2C_STATE_READY)
01689   {
01690     /* Process Locked */
01691     __HAL_LOCK(hi2c);
01692
01693     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
01694     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
01695     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01696
01697     /* Enable Address Acknowledge */
01698     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01699
01700     /* Prepare transfer parameters */
01701     hi2c->pBuffPtr    = pData;
01702     hi2c->XferCount   = Size;
01703     hi2c->XferSize    = hi2c->XferCount;
01704     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01705     hi2c->XferISR     = I2C_Slave_ISR_IT;
01706
01707     /* Process Unlocked */
01708     __HAL_UNLOCK(hi2c);
01709
01710     /* Note : The I2C interrupts must be enabled after unlocking current process
01711               to avoid the risk of I2C interrupt handle execution before current
01712               process unlock */
01713
01714     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
01715     /* possible to enable all of these */
01716     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01717     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
01718
01719     return HAL_OK;
01720   }
01721   else
01722   {
01723     return HAL_BUSY;
01724   }
01725 }
01726
01727 /**
01728   * @brief  Receive in slave mode an amount of data in non-blocking mode with Interrupt
01729   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01730   *                the configuration information for the specified I2C.
01731   * @param  pData Pointer to data buffer
01732   * @param  Size Amount of data to be sent
01733   * @retval HAL status
01734   */
01735 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
01736 {
01737   if (hi2c->State == HAL_I2C_STATE_READY)
01738   {
01739     /* Process Locked */
01740     __HAL_LOCK(hi2c);
01741
01742     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
01743     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
01744     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01745
01746     /* Enable Address Acknowledge */
01747     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01748
01749     /* Prepare transfer parameters */
01750     hi2c->pBuffPtr    = pData;
01751     hi2c->XferCount   = Size;
01752     hi2c->XferSize    = hi2c->XferCount;
01753     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01754     hi2c->XferISR     = I2C_Slave_ISR_IT;
01755
01756     /* Process Unlocked */
01757     __HAL_UNLOCK(hi2c);
01758
01759     /* Note : The I2C interrupts must be enabled after unlocking current process
01760               to avoid the risk of I2C interrupt handle execution before current
01761               process unlock */
01762
01763     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
01764     /* possible to enable all of these */
01765     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01766     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
01767
01768     return HAL_OK;
01769   }
01770   else
01771   {
01772     return HAL_BUSY;
01773   }
01774 }
01775
01776 /**
01777   * @brief  Transmit in master mode an amount of data in non-blocking mode with DMA
01778   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01779   *                the configuration information for the specified I2C.
01780   * @param  DevAddress Target device address: The device 7 bits address value
01781   *         in datasheet must be shifted to the left before calling the interface
01782   * @param  pData Pointer to data buffer
01783   * @param  Size Amount of data to be sent
01784   * @retval HAL status
01785   */
01786 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
01787 {
01788   uint32_t xfermode;
01789   HAL_StatusTypeDef dmaxferstatus;
01790
01791   if (hi2c->State == HAL_I2C_STATE_READY)
01792   {
01793     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
01794     {
01795       return HAL_BUSY;
01796     }
01797
01798     /* Process Locked */
01799     __HAL_LOCK(hi2c);
01800
01801     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
01802     hi2c->Mode        = HAL_I2C_MODE_MASTER;
01803     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01804
01805     /* Prepare transfer parameters */
01806     hi2c->pBuffPtr    = pData;
01807     hi2c->XferCount   = Size;
01808     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01809     hi2c->XferISR     = I2C_Master_ISR_DMA;
01810
01811     if (hi2c->XferCount > MAX_NBYTE_SIZE)
01812     {
01813       hi2c->XferSize = MAX_NBYTE_SIZE;
01814       xfermode = I2C_RELOAD_MODE;
01815     }
01816     else
01817     {
01818       hi2c->XferSize = hi2c->XferCount;
01819       xfermode = I2C_AUTOEND_MODE;
01820     }
01821
01822     if (hi2c->XferSize > 0U)
01823     {
01824       if (hi2c->hdmatx != NULL)
01825       {
01826         /* Set the I2C DMA transfer complete callback */
01827         hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
01828
01829         /* Set the DMA error callback */
01830         hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
01831
01832         /* Set the unused DMA callbacks to NULL */
01833         hi2c->hdmatx->XferHalfCpltCallback = NULL;
01834         hi2c->hdmatx->XferAbortCallback = NULL;
01835
01836         /* Enable the DMA channel */
01837         dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
01838       }
01839       else
01840       {
01841         /* Update I2C state */
01842         hi2c->State     = HAL_I2C_STATE_READY;
01843         hi2c->Mode      = HAL_I2C_MODE_NONE;
01844
01845         /* Update I2C error code */
01846         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
01847
01848         /* Process Unlocked */
01849         __HAL_UNLOCK(hi2c);
01850
01851         return HAL_ERROR;
01852       }
01853
01854       if (dmaxferstatus == HAL_OK)
01855       {
01856         /* Send Slave Address */
01857         /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
01858         I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
01859
01860         /* Update XferCount value */
01861         hi2c->XferCount -= hi2c->XferSize;
01862
01863         /* Process Unlocked */
01864         __HAL_UNLOCK(hi2c);
01865
01866         /* Note : The I2C interrupts must be enabled after unlocking current process
01867                   to avoid the risk of I2C interrupt handle execution before current
01868                   process unlock */
01869         /* Enable ERR and NACK interrupts */
01870         I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
01871
01872         /* Enable DMA Request */
01873         hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
01874       }
01875       else
01876       {
01877         /* Update I2C state */
01878         hi2c->State     = HAL_I2C_STATE_READY;
01879         hi2c->Mode      = HAL_I2C_MODE_NONE;
01880
01881         /* Update I2C error code */
01882         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
01883
01884         /* Process Unlocked */
01885         __HAL_UNLOCK(hi2c);
01886
01887         return HAL_ERROR;
01888       }
01889     }
01890     else
01891     {
01892       /* Update Transfer ISR function pointer */
01893       hi2c->XferISR = I2C_Master_ISR_IT;
01894
01895       /* Send Slave Address */
01896       /* Set NBYTES to write and generate START condition */
01897       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
01898
01899       /* Process Unlocked */
01900       __HAL_UNLOCK(hi2c);
01901
01902       /* Note : The I2C interrupts must be enabled after unlocking current process
01903                 to avoid the risk of I2C interrupt handle execution before current
01904                 process unlock */
01905       /* Enable ERR, TC, STOP, NACK, TXI interrupt */
01906       /* possible to enable all of these */
01907       /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01908       I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
01909     }
01910
01911     return HAL_OK;
01912   }
01913   else
01914   {
01915     return HAL_BUSY;
01916   }
01917 }
01918
01919 /**
01920   * @brief  Receive in master mode an amount of data in non-blocking mode with DMA
01921   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01922   *                the configuration information for the specified I2C.
01923   * @param  DevAddress Target device address: The device 7 bits address value
01924   *         in datasheet must be shifted to the left before calling the interface
01925   * @param  pData Pointer to data buffer
01926   * @param  Size Amount of data to be sent
01927   * @retval HAL status
01928   */
01929 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
01930 {
01931   uint32_t xfermode;
01932   HAL_StatusTypeDef dmaxferstatus;
01933
01934   if (hi2c->State == HAL_I2C_STATE_READY)
01935   {
01936     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
01937     {
01938       return HAL_BUSY;
01939     }
01940
01941     /* Process Locked */
01942     __HAL_LOCK(hi2c);
01943
01944     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
01945     hi2c->Mode        = HAL_I2C_MODE_MASTER;
01946     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01947
01948     /* Prepare transfer parameters */
01949     hi2c->pBuffPtr    = pData;
01950     hi2c->XferCount   = Size;
01951     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01952     hi2c->XferISR     = I2C_Master_ISR_DMA;
01953
01954     if (hi2c->XferCount > MAX_NBYTE_SIZE)
01955     {
01956       hi2c->XferSize = MAX_NBYTE_SIZE;
01957       xfermode = I2C_RELOAD_MODE;
01958     }
01959     else
01960     {
01961       hi2c->XferSize = hi2c->XferCount;
01962       xfermode = I2C_AUTOEND_MODE;
01963     }
01964
01965     if (hi2c->XferSize > 0U)
01966     {
01967       if (hi2c->hdmarx != NULL)
01968       {
01969         /* Set the I2C DMA transfer complete callback */
01970         hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
01971
01972         /* Set the DMA error callback */
01973         hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
01974
01975         /* Set the unused DMA callbacks to NULL */
01976         hi2c->hdmarx->XferHalfCpltCallback = NULL;
01977         hi2c->hdmarx->XferAbortCallback = NULL;
01978
01979         /* Enable the DMA channel */
01980         dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
01981       }
01982       else
01983       {
01984         /* Update I2C state */
01985         hi2c->State     = HAL_I2C_STATE_READY;
01986         hi2c->Mode      = HAL_I2C_MODE_NONE;
01987
01988         /* Update I2C error code */
01989         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
01990
01991         /* Process Unlocked */
01992         __HAL_UNLOCK(hi2c);
01993
01994         return HAL_ERROR;
01995       }
01996
01997       if (dmaxferstatus == HAL_OK)
01998       {
01999         /* Send Slave Address */
02000         /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
02001         I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
02002
02003         /* Update XferCount value */
02004         hi2c->XferCount -= hi2c->XferSize;
02005
02006         /* Process Unlocked */
02007         __HAL_UNLOCK(hi2c);
02008
02009         /* Note : The I2C interrupts must be enabled after unlocking current process
02010                   to avoid the risk of I2C interrupt handle execution before current
02011                   process unlock */
02012         /* Enable ERR and NACK interrupts */
02013         I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
02014
02015         /* Enable DMA Request */
02016         hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
02017       }
02018       else
02019       {
02020         /* Update I2C state */
02021         hi2c->State     = HAL_I2C_STATE_READY;
02022         hi2c->Mode      = HAL_I2C_MODE_NONE;
02023
02024         /* Update I2C error code */
02025         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
02026
02027         /* Process Unlocked */
02028         __HAL_UNLOCK(hi2c);
02029
02030         return HAL_ERROR;
02031       }
02032     }
02033     else
02034     {
02035       /* Update Transfer ISR function pointer */
02036       hi2c->XferISR = I2C_Master_ISR_IT;
02037
02038       /* Send Slave Address */
02039       /* Set NBYTES to read and generate START condition */
02040       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
02041
02042       /* Process Unlocked */
02043       __HAL_UNLOCK(hi2c);
02044
02045       /* Note : The I2C interrupts must be enabled after unlocking current process
02046                 to avoid the risk of I2C interrupt handle execution before current
02047                 process unlock */
02048       /* Enable ERR, TC, STOP, NACK, TXI interrupt */
02049       /* possible to enable all of these */
02050       /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
02051       I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
02052     }
02053
02054     return HAL_OK;
02055   }
02056   else
02057   {
02058     return HAL_BUSY;
02059   }
02060 }
02061
02062 /**
02063   * @brief  Transmit in slave mode an amount of data in non-blocking mode with DMA
02064   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02065   *                the configuration information for the specified I2C.
02066   * @param  pData Pointer to data buffer
02067   * @param  Size Amount of data to be sent
02068   * @retval HAL status
02069   */
02070 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
02071 {
02072   HAL_StatusTypeDef dmaxferstatus;
02073
02074   if (hi2c->State == HAL_I2C_STATE_READY)
02075   {
02076     if ((pData == NULL) || (Size == 0U))
02077     {
02078       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
02079       return  HAL_ERROR;
02080     }
02081     /* Process Locked */
02082     __HAL_LOCK(hi2c);
02083
02084     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
02085     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
02086     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02087
02088     /* Prepare transfer parameters */
02089     hi2c->pBuffPtr    = pData;
02090     hi2c->XferCount   = Size;
02091     hi2c->XferSize    = hi2c->XferCount;
02092     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02093     hi2c->XferISR     = I2C_Slave_ISR_DMA;
02094
02095     if (hi2c->hdmatx != NULL)
02096     {
02097       /* Set the I2C DMA transfer complete callback */
02098       hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
02099
02100       /* Set the DMA error callback */
02101       hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
02102
02103       /* Set the unused DMA callbacks to NULL */
02104       hi2c->hdmatx->XferHalfCpltCallback = NULL;
02105       hi2c->hdmatx->XferAbortCallback = NULL;
02106
02107       /* Enable the DMA channel */
02108       dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
02109     }
02110     else
02111     {
02112       /* Update I2C state */
02113       hi2c->State     = HAL_I2C_STATE_LISTEN;
02114       hi2c->Mode      = HAL_I2C_MODE_NONE;
02115
02116       /* Update I2C error code */
02117       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
02118
02119       /* Process Unlocked */
02120       __HAL_UNLOCK(hi2c);
02121
02122       return HAL_ERROR;
02123     }
02124
02125     if (dmaxferstatus == HAL_OK)
02126     {
02127       /* Enable Address Acknowledge */
02128       hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
02129
02130       /* Process Unlocked */
02131       __HAL_UNLOCK(hi2c);
02132
02133       /* Note : The I2C interrupts must be enabled after unlocking current process
02134                 to avoid the risk of I2C interrupt handle execution before current
02135                 process unlock */
02136       /* Enable ERR, STOP, NACK, ADDR interrupts */
02137       I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
02138
02139       /* Enable DMA Request */
02140       hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
02141     }
02142     else
02143     {
02144       /* Update I2C state */
02145       hi2c->State     = HAL_I2C_STATE_LISTEN;
02146       hi2c->Mode      = HAL_I2C_MODE_NONE;
02147
02148       /* Update I2C error code */
02149       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
02150
02151       /* Process Unlocked */
02152       __HAL_UNLOCK(hi2c);
02153
02154       return HAL_ERROR;
02155     }
02156
02157     return HAL_OK;
02158   }
02159   else
02160   {
02161     return HAL_BUSY;
02162   }
02163 }
02164
02165 /**
02166   * @brief  Receive in slave mode an amount of data in non-blocking mode with DMA
02167   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02168   *                the configuration information for the specified I2C.
02169   * @param  pData Pointer to data buffer
02170   * @param  Size Amount of data to be sent
02171   * @retval HAL status
02172   */
02173 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
02174 {
02175   HAL_StatusTypeDef dmaxferstatus;
02176
02177   if (hi2c->State == HAL_I2C_STATE_READY)
02178   {
02179     if ((pData == NULL) || (Size == 0U))
02180     {
02181       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
02182       return  HAL_ERROR;
02183     }
02184     /* Process Locked */
02185     __HAL_LOCK(hi2c);
02186
02187     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
02188     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
02189     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02190
02191     /* Prepare transfer parameters */
02192     hi2c->pBuffPtr    = pData;
02193     hi2c->XferCount   = Size;
02194     hi2c->XferSize    = hi2c->XferCount;
02195     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02196     hi2c->XferISR     = I2C_Slave_ISR_DMA;
02197
02198     if (hi2c->hdmarx != NULL)
02199     {
02200       /* Set the I2C DMA transfer complete callback */
02201       hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
02202
02203       /* Set the DMA error callback */
02204       hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
02205
02206       /* Set the unused DMA callbacks to NULL */
02207       hi2c->hdmarx->XferHalfCpltCallback = NULL;
02208       hi2c->hdmarx->XferAbortCallback = NULL;
02209
02210       /* Enable the DMA channel */
02211       dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
02212     }
02213     else
02214     {
02215       /* Update I2C state */
02216       hi2c->State     = HAL_I2C_STATE_LISTEN;
02217       hi2c->Mode      = HAL_I2C_MODE_NONE;
02218
02219       /* Update I2C error code */
02220       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
02221
02222       /* Process Unlocked */
02223       __HAL_UNLOCK(hi2c);
02224
02225       return HAL_ERROR;
02226     }
02227
02228     if (dmaxferstatus == HAL_OK)
02229     {
02230       /* Enable Address Acknowledge */
02231       hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
02232
02233       /* Process Unlocked */
02234       __HAL_UNLOCK(hi2c);
02235
02236       /* Note : The I2C interrupts must be enabled after unlocking current process
02237                 to avoid the risk of I2C interrupt handle execution before current
02238                 process unlock */
02239       /* Enable ERR, STOP, NACK, ADDR interrupts */
02240       I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
02241
02242       /* Enable DMA Request */
02243       hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
02244     }
02245     else
02246     {
02247       /* Update I2C state */
02248       hi2c->State     = HAL_I2C_STATE_LISTEN;
02249       hi2c->Mode      = HAL_I2C_MODE_NONE;
02250
02251       /* Update I2C error code */
02252       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
02253
02254       /* Process Unlocked */
02255       __HAL_UNLOCK(hi2c);
02256
02257       return HAL_ERROR;
02258     }
02259
02260     return HAL_OK;
02261   }
02262   else
02263   {
02264     return HAL_BUSY;
02265   }
02266 }
02267 /**
02268   * @brief  Write an amount of data in blocking mode to a specific memory address
02269   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02270   *                the configuration information for the specified I2C.
02271   * @param  DevAddress Target device address: The device 7 bits address value
02272   *         in datasheet must be shifted to the left before calling the interface
02273   * @param  MemAddress Internal memory address
02274   * @param  MemAddSize Size of internal memory address
02275   * @param  pData Pointer to data buffer
02276   * @param  Size Amount of data to be sent
02277   * @param  Timeout Timeout duration
02278   * @retval HAL status
02279   */
02280 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
02281 {
02282   uint32_t tickstart;
02283
02284   /* Check the parameters */
02285   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02286
02287   if (hi2c->State == HAL_I2C_STATE_READY)
02288   {
02289     if ((pData == NULL) || (Size == 0U))
02290     {
02291       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
02292       return  HAL_ERROR;
02293     }
02294
02295     /* Process Locked */
02296     __HAL_LOCK(hi2c);
02297
02298     /* Init tickstart for timeout management*/
02299     tickstart = HAL_GetTick();
02300
02301     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
02302     {
02303       return HAL_ERROR;
02304     }
02305
02306     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
02307     hi2c->Mode      = HAL_I2C_MODE_MEM;
02308     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02309
02310     /* Prepare transfer parameters */
02311     hi2c->pBuffPtr  = pData;
02312     hi2c->XferCount = Size;
02313     hi2c->XferISR   = NULL;
02314
02315     /* Send Slave Address and Memory Address */
02316     if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
02317     {
02318       /* Process Unlocked */
02319       __HAL_UNLOCK(hi2c);
02320       return HAL_ERROR;
02321     }
02322
02323     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
02324     if (hi2c->XferCount > MAX_NBYTE_SIZE)
02325     {
02326       hi2c->XferSize = MAX_NBYTE_SIZE;
02327       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
02328     }
02329     else
02330     {
02331       hi2c->XferSize = hi2c->XferCount;
02332       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
02333     }
02334
02335     do
02336     {
02337       /* Wait until TXIS flag is set */
02338       if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
02339       {
02340         return HAL_ERROR;
02341       }
02342
02343       /* Write data to TXDR */
02344       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
02345
02346       /* Increment Buffer pointer */
02347       hi2c->pBuffPtr++;
02348
02349       hi2c->XferCount--;
02350       hi2c->XferSize--;
02351
02352       if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
02353       {
02354         /* Wait until TCR flag is set */
02355         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
02356         {
02357           return HAL_ERROR;
02358         }
02359
02360         if (hi2c->XferCount > MAX_NBYTE_SIZE)
02361         {
02362           hi2c->XferSize = MAX_NBYTE_SIZE;
02363           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
02364         }
02365         else
02366         {
02367           hi2c->XferSize = hi2c->XferCount;
02368           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
02369         }
02370       }
02371
02372     }
02373     while (hi2c->XferCount > 0U);
02374
02375     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
02376     /* Wait until STOPF flag is reset */
02377     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
02378     {
02379       return HAL_ERROR;
02380     }
02381
02382     /* Clear STOP Flag */
02383     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
02384
02385     /* Clear Configuration Register 2 */
02386     I2C_RESET_CR2(hi2c);
02387
02388     hi2c->State = HAL_I2C_STATE_READY;
02389     hi2c->Mode  = HAL_I2C_MODE_NONE;
02390
02391     /* Process Unlocked */
02392     __HAL_UNLOCK(hi2c);
02393
02394     return HAL_OK;
02395   }
02396   else
02397   {
02398     return HAL_BUSY;
02399   }
02400 }
02401
02402 /**
02403   * @brief  Read an amount of data in blocking mode from a specific memory address
02404   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02405   *                the configuration information for the specified I2C.
02406   * @param  DevAddress Target device address: The device 7 bits address value
02407   *         in datasheet must be shifted to the left before calling the interface
02408   * @param  MemAddress Internal memory address
02409   * @param  MemAddSize Size of internal memory address
02410   * @param  pData Pointer to data buffer
02411   * @param  Size Amount of data to be sent
02412   * @param  Timeout Timeout duration
02413   * @retval HAL status
02414   */
02415 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
02416 {
02417   uint32_t tickstart;
02418
02419   /* Check the parameters */
02420   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02421
02422   if (hi2c->State == HAL_I2C_STATE_READY)
02423   {
02424     if ((pData == NULL) || (Size == 0U))
02425     {
02426       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
02427       return  HAL_ERROR;
02428     }
02429
02430     /* Process Locked */
02431     __HAL_LOCK(hi2c);
02432
02433     /* Init tickstart for timeout management*/
02434     tickstart = HAL_GetTick();
02435
02436     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
02437     {
02438       return HAL_ERROR;
02439     }
02440
02441     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
02442     hi2c->Mode      = HAL_I2C_MODE_MEM;
02443     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02444
02445     /* Prepare transfer parameters */
02446     hi2c->pBuffPtr  = pData;
02447     hi2c->XferCount = Size;
02448     hi2c->XferISR   = NULL;
02449
02450     /* Send Slave Address and Memory Address */
02451     if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
02452     {
02453       /* Process Unlocked */
02454       __HAL_UNLOCK(hi2c);
02455       return HAL_ERROR;
02456     }
02457
02458     /* Send Slave Address */
02459     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
02460     if (hi2c->XferCount > MAX_NBYTE_SIZE)
02461     {
02462       hi2c->XferSize = MAX_NBYTE_SIZE;
02463       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
02464     }
02465     else
02466     {
02467       hi2c->XferSize = hi2c->XferCount;
02468       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
02469     }
02470
02471     do
02472     {
02473       /* Wait until RXNE flag is set */
02474       if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
02475       {
02476         return HAL_ERROR;
02477       }
02478
02479       /* Read data from RXDR */
02480       *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
02481
02482       /* Increment Buffer pointer */
02483       hi2c->pBuffPtr++;
02484
02485       hi2c->XferSize--;
02486       hi2c->XferCount--;
02487
02488       if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
02489       {
02490         /* Wait until TCR flag is set */
02491         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
02492         {
02493           return HAL_ERROR;
02494         }
02495
02496         if (hi2c->XferCount > MAX_NBYTE_SIZE)
02497         {
02498           hi2c->XferSize = MAX_NBYTE_SIZE;
02499           I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
02500         }
02501         else
02502         {
02503           hi2c->XferSize = hi2c->XferCount;
02504           I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
02505         }
02506       }
02507     }
02508     while (hi2c->XferCount > 0U);
02509
02510     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
02511     /* Wait until STOPF flag is reset */
02512     if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
02513     {
02514       return HAL_ERROR;
02515     }
02516
02517     /* Clear STOP Flag */
02518     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
02519
02520     /* Clear Configuration Register 2 */
02521     I2C_RESET_CR2(hi2c);
02522
02523     hi2c->State = HAL_I2C_STATE_READY;
02524     hi2c->Mode  = HAL_I2C_MODE_NONE;
02525
02526     /* Process Unlocked */
02527     __HAL_UNLOCK(hi2c);
02528
02529     return HAL_OK;
02530   }
02531   else
02532   {
02533     return HAL_BUSY;
02534   }
02535 }
02536 /**
02537   * @brief  Write an amount of data in non-blocking mode with Interrupt to a specific memory address
02538   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02539   *                the configuration information for the specified I2C.
02540   * @param  DevAddress Target device address: The device 7 bits address value
02541   *         in datasheet must be shifted to the left before calling the interface
02542   * @param  MemAddress Internal memory address
02543   * @param  MemAddSize Size of internal memory address
02544   * @param  pData Pointer to data buffer
02545   * @param  Size Amount of data to be sent
02546   * @retval HAL status
02547   */
02548 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02549 {
02550   uint32_t tickstart;
02551   uint32_t xfermode;
02552
02553   /* Check the parameters */
02554   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02555
02556   if (hi2c->State == HAL_I2C_STATE_READY)
02557   {
02558     if ((pData == NULL) || (Size == 0U))
02559     {
02560       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
02561       return  HAL_ERROR;
02562     }
02563
02564     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02565     {
02566       return HAL_BUSY;
02567     }
02568
02569     /* Process Locked */
02570     __HAL_LOCK(hi2c);
02571
02572     /* Init tickstart for timeout management*/
02573     tickstart = HAL_GetTick();
02574
02575     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
02576     hi2c->Mode        = HAL_I2C_MODE_MEM;
02577     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02578
02579     /* Prepare transfer parameters */
02580     hi2c->pBuffPtr    = pData;
02581     hi2c->XferCount   = Size;
02582     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02583     hi2c->XferISR     = I2C_Master_ISR_IT;
02584
02585     if (hi2c->XferCount > MAX_NBYTE_SIZE)
02586     {
02587       hi2c->XferSize = MAX_NBYTE_SIZE;
02588       xfermode = I2C_RELOAD_MODE;
02589     }
02590     else
02591     {
02592       hi2c->XferSize = hi2c->XferCount;
02593       xfermode = I2C_AUTOEND_MODE;
02594     }
02595
02596     /* Send Slave Address and Memory Address */
02597     if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
02598     {
02599       /* Process Unlocked */
02600       __HAL_UNLOCK(hi2c);
02601       return HAL_ERROR;
02602     }
02603
02604     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
02605     I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
02606
02607     /* Process Unlocked */
02608     __HAL_UNLOCK(hi2c);
02609
02610     /* Note : The I2C interrupts must be enabled after unlocking current process
02611               to avoid the risk of I2C interrupt handle execution before current
02612               process unlock */
02613
02614     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
02615     /* possible to enable all of these */
02616     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
02617     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
02618
02619     return HAL_OK;
02620   }
02621   else
02622   {
02623     return HAL_BUSY;
02624   }
02625 }
02626
02627 /**
02628   * @brief  Read an amount of data in non-blocking mode with Interrupt from a specific memory address
02629   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02630   *                the configuration information for the specified I2C.
02631   * @param  DevAddress Target device address: The device 7 bits address value
02632   *         in datasheet must be shifted to the left before calling the interface
02633   * @param  MemAddress Internal memory address
02634   * @param  MemAddSize Size of internal memory address
02635   * @param  pData Pointer to data buffer
02636   * @param  Size Amount of data to be sent
02637   * @retval HAL status
02638   */
02639 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02640 {
02641   uint32_t tickstart;
02642   uint32_t xfermode;
02643
02644   /* Check the parameters */
02645   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02646
02647   if (hi2c->State == HAL_I2C_STATE_READY)
02648   {
02649     if ((pData == NULL) || (Size == 0U))
02650     {
02651       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
02652       return  HAL_ERROR;
02653     }
02654
02655     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02656     {
02657       return HAL_BUSY;
02658     }
02659
02660     /* Process Locked */
02661     __HAL_LOCK(hi2c);
02662
02663     /* Init tickstart for timeout management*/
02664     tickstart = HAL_GetTick();
02665
02666     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
02667     hi2c->Mode        = HAL_I2C_MODE_MEM;
02668     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02669
02670     /* Prepare transfer parameters */
02671     hi2c->pBuffPtr    = pData;
02672     hi2c->XferCount   = Size;
02673     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02674     hi2c->XferISR     = I2C_Master_ISR_IT;
02675
02676     if (hi2c->XferCount > MAX_NBYTE_SIZE)
02677     {
02678       hi2c->XferSize = MAX_NBYTE_SIZE;
02679       xfermode = I2C_RELOAD_MODE;
02680     }
02681     else
02682     {
02683       hi2c->XferSize = hi2c->XferCount;
02684       xfermode = I2C_AUTOEND_MODE;
02685     }
02686
02687     /* Send Slave Address and Memory Address */
02688     if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
02689     {
02690       /* Process Unlocked */
02691       __HAL_UNLOCK(hi2c);
02692       return HAL_ERROR;
02693     }
02694
02695     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
02696     I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
02697
02698     /* Process Unlocked */
02699     __HAL_UNLOCK(hi2c);
02700
02701     /* Note : The I2C interrupts must be enabled after unlocking current process
02702               to avoid the risk of I2C interrupt handle execution before current
02703               process unlock */
02704
02705     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
02706     /* possible to enable all of these */
02707     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
02708     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
02709
02710     return HAL_OK;
02711   }
02712   else
02713   {
02714     return HAL_BUSY;
02715   }
02716 }
02717 /**
02718   * @brief  Write an amount of data in non-blocking mode with DMA to a specific memory address
02719   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02720   *                the configuration information for the specified I2C.
02721   * @param  DevAddress Target device address: The device 7 bits address value
02722   *         in datasheet must be shifted to the left before calling the interface
02723   * @param  MemAddress Internal memory address
02724   * @param  MemAddSize Size of internal memory address
02725   * @param  pData Pointer to data buffer
02726   * @param  Size Amount of data to be sent
02727   * @retval HAL status
02728   */
02729 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02730 {
02731   uint32_t tickstart;
02732   uint32_t xfermode;
02733   HAL_StatusTypeDef dmaxferstatus;
02734
02735   /* Check the parameters */
02736   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02737
02738   if (hi2c->State == HAL_I2C_STATE_READY)
02739   {
02740     if ((pData == NULL) || (Size == 0U))
02741     {
02742       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
02743       return  HAL_ERROR;
02744     }
02745
02746     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02747     {
02748       return HAL_BUSY;
02749     }
02750
02751     /* Process Locked */
02752     __HAL_LOCK(hi2c);
02753
02754     /* Init tickstart for timeout management*/
02755     tickstart = HAL_GetTick();
02756
02757     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
02758     hi2c->Mode        = HAL_I2C_MODE_MEM;
02759     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02760
02761     /* Prepare transfer parameters */
02762     hi2c->pBuffPtr    = pData;
02763     hi2c->XferCount   = Size;
02764     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02765     hi2c->XferISR     = I2C_Master_ISR_DMA;
02766
02767     if (hi2c->XferCount > MAX_NBYTE_SIZE)
02768     {
02769       hi2c->XferSize = MAX_NBYTE_SIZE;
02770       xfermode = I2C_RELOAD_MODE;
02771     }
02772     else
02773     {
02774       hi2c->XferSize = hi2c->XferCount;
02775       xfermode = I2C_AUTOEND_MODE;
02776     }
02777
02778     /* Send Slave Address and Memory Address */
02779     if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
02780     {
02781       /* Process Unlocked */
02782       __HAL_UNLOCK(hi2c);
02783       return HAL_ERROR;
02784     }
02785
02786
02787     if (hi2c->hdmatx != NULL)
02788     {
02789       /* Set the I2C DMA transfer complete callback */
02790       hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
02791
02792       /* Set the DMA error callback */
02793       hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
02794
02795       /* Set the unused DMA callbacks to NULL */
02796       hi2c->hdmatx->XferHalfCpltCallback = NULL;
02797       hi2c->hdmatx->XferAbortCallback = NULL;
02798
02799       /* Enable the DMA channel */
02800       dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
02801     }
02802     else
02803     {
02804       /* Update I2C state */
02805       hi2c->State     = HAL_I2C_STATE_READY;
02806       hi2c->Mode      = HAL_I2C_MODE_NONE;
02807
02808       /* Update I2C error code */
02809       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
02810
02811       /* Process Unlocked */
02812       __HAL_UNLOCK(hi2c);
02813
02814       return HAL_ERROR;
02815     }
02816
02817     if (dmaxferstatus == HAL_OK)
02818     {
02819       /* Send Slave Address */
02820       /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
02821       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
02822
02823       /* Update XferCount value */
02824       hi2c->XferCount -= hi2c->XferSize;
02825
02826       /* Process Unlocked */
02827       __HAL_UNLOCK(hi2c);
02828
02829       /* Note : The I2C interrupts must be enabled after unlocking current process
02830                 to avoid the risk of I2C interrupt handle execution before current
02831                 process unlock */
02832       /* Enable ERR and NACK interrupts */
02833       I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
02834
02835       /* Enable DMA Request */
02836       hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
02837     }
02838     else
02839     {
02840       /* Update I2C state */
02841       hi2c->State     = HAL_I2C_STATE_READY;
02842       hi2c->Mode      = HAL_I2C_MODE_NONE;
02843
02844       /* Update I2C error code */
02845       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
02846
02847       /* Process Unlocked */
02848       __HAL_UNLOCK(hi2c);
02849
02850       return HAL_ERROR;
02851     }
02852
02853     return HAL_OK;
02854   }
02855   else
02856   {
02857     return HAL_BUSY;
02858   }
02859 }
02860
02861 /**
02862   * @brief  Reads an amount of data in non-blocking mode with DMA from a specific memory address.
02863   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02864   *                the configuration information for the specified I2C.
02865   * @param  DevAddress Target device address: The device 7 bits address value
02866   *         in datasheet must be shifted to the left before calling the interface
02867   * @param  MemAddress Internal memory address
02868   * @param  MemAddSize Size of internal memory address
02869   * @param  pData Pointer to data buffer
02870   * @param  Size Amount of data to be read
02871   * @retval HAL status
02872   */
02873 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02874 {
02875   uint32_t tickstart;
02876   uint32_t xfermode;
02877   HAL_StatusTypeDef dmaxferstatus;
02878
02879   /* Check the parameters */
02880   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02881
02882   if (hi2c->State == HAL_I2C_STATE_READY)
02883   {
02884     if ((pData == NULL) || (Size == 0U))
02885     {
02886       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
02887       return  HAL_ERROR;
02888     }
02889
02890     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02891     {
02892       return HAL_BUSY;
02893     }
02894
02895     /* Process Locked */
02896     __HAL_LOCK(hi2c);
02897
02898     /* Init tickstart for timeout management*/
02899     tickstart = HAL_GetTick();
02900
02901     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
02902     hi2c->Mode        = HAL_I2C_MODE_MEM;
02903     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02904
02905     /* Prepare transfer parameters */
02906     hi2c->pBuffPtr    = pData;
02907     hi2c->XferCount   = Size;
02908     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02909     hi2c->XferISR     = I2C_Master_ISR_DMA;
02910
02911     if (hi2c->XferCount > MAX_NBYTE_SIZE)
02912     {
02913       hi2c->XferSize = MAX_NBYTE_SIZE;
02914       xfermode = I2C_RELOAD_MODE;
02915     }
02916     else
02917     {
02918       hi2c->XferSize = hi2c->XferCount;
02919       xfermode = I2C_AUTOEND_MODE;
02920     }
02921
02922     /* Send Slave Address and Memory Address */
02923     if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
02924     {
02925       /* Process Unlocked */
02926       __HAL_UNLOCK(hi2c);
02927       return HAL_ERROR;
02928     }
02929
02930     if (hi2c->hdmarx != NULL)
02931     {
02932       /* Set the I2C DMA transfer complete callback */
02933       hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
02934
02935       /* Set the DMA error callback */
02936       hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
02937
02938       /* Set the unused DMA callbacks to NULL */
02939       hi2c->hdmarx->XferHalfCpltCallback = NULL;
02940       hi2c->hdmarx->XferAbortCallback = NULL;
02941
02942       /* Enable the DMA channel */
02943       dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
02944     }
02945     else
02946     {
02947       /* Update I2C state */
02948       hi2c->State     = HAL_I2C_STATE_READY;
02949       hi2c->Mode      = HAL_I2C_MODE_NONE;
02950
02951       /* Update I2C error code */
02952       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
02953
02954       /* Process Unlocked */
02955       __HAL_UNLOCK(hi2c);
02956
02957       return HAL_ERROR;
02958     }
02959
02960     if (dmaxferstatus == HAL_OK)
02961     {
02962       /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
02963       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
02964
02965       /* Update XferCount value */
02966       hi2c->XferCount -= hi2c->XferSize;
02967
02968       /* Process Unlocked */
02969       __HAL_UNLOCK(hi2c);
02970
02971       /* Note : The I2C interrupts must be enabled after unlocking current process
02972                 to avoid the risk of I2C interrupt handle execution before current
02973                 process unlock */
02974       /* Enable ERR and NACK interrupts */
02975       I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
02976
02977       /* Enable DMA Request */
02978       hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
02979     }
02980     else
02981     {
02982       /* Update I2C state */
02983       hi2c->State     = HAL_I2C_STATE_READY;
02984       hi2c->Mode      = HAL_I2C_MODE_NONE;
02985
02986       /* Update I2C error code */
02987       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
02988
02989       /* Process Unlocked */
02990       __HAL_UNLOCK(hi2c);
02991
02992       return HAL_ERROR;
02993     }
02994
02995     return HAL_OK;
02996   }
02997   else
02998   {
02999     return HAL_BUSY;
03000   }
03001 }
03002
03003 /**
03004   * @brief  Checks if target device is ready for communication.
03005   * @note   This function is used with Memory devices
03006   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03007   *                the configuration information for the specified I2C.
03008   * @param  DevAddress Target device address: The device 7 bits address value
03009   *         in datasheet must be shifted to the left before calling the interface
03010   * @param  Trials Number of trials
03011   * @param  Timeout Timeout duration
03012   * @retval HAL status
03013   */
03014 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
03015 {
03016   uint32_t tickstart;
03017
03018   __IO uint32_t I2C_Trials = 0UL;
03019
03020   FlagStatus tmp1;
03021   FlagStatus tmp2;
03022
03023   if (hi2c->State == HAL_I2C_STATE_READY)
03024   {
03025     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
03026     {
03027       return HAL_BUSY;
03028     }
03029
03030     /* Process Locked */
03031     __HAL_LOCK(hi2c);
03032
03033     hi2c->State = HAL_I2C_STATE_BUSY;
03034     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
03035
03036     do
03037     {
03038       /* Generate Start */
03039       hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);
03040
03041       /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
03042       /* Wait until STOPF flag is set or a NACK flag is set*/
03043       tickstart = HAL_GetTick();
03044
03045       tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
03046       tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
03047
03048       while ((tmp1 == RESET) && (tmp2 == RESET))
03049       {
03050         if (Timeout != HAL_MAX_DELAY)
03051         {
03052           if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
03053           {
03054             /* Update I2C state */
03055             hi2c->State = HAL_I2C_STATE_READY;
03056
03057             /* Update I2C error code */
03058             hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
03059
03060             /* Process Unlocked */
03061             __HAL_UNLOCK(hi2c);
03062
03063             return HAL_ERROR;
03064           }
03065         }
03066
03067         tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
03068         tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
03069       }
03070
03071       /* Check if the NACKF flag has not been set */
03072       if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
03073       {
03074         /* Wait until STOPF flag is reset */
03075         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
03076         {
03077           return HAL_ERROR;
03078         }
03079
03080         /* Clear STOP Flag */
03081         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
03082
03083         /* Device is ready */
03084         hi2c->State = HAL_I2C_STATE_READY;
03085
03086         /* Process Unlocked */
03087         __HAL_UNLOCK(hi2c);
03088
03089         return HAL_OK;
03090       }
03091       else
03092       {
03093         /* Wait until STOPF flag is reset */
03094         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
03095         {
03096           return HAL_ERROR;
03097         }
03098
03099         /* Clear NACK Flag */
03100         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03101
03102         /* Clear STOP Flag, auto generated with autoend*/
03103         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
03104       }
03105
03106       /* Check if the maximum allowed number of trials has been reached */
03107       if (I2C_Trials == Trials)
03108       {
03109         /* Generate Stop */
03110         hi2c->Instance->CR2 |= I2C_CR2_STOP;
03111
03112         /* Wait until STOPF flag is reset */
03113         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
03114         {
03115           return HAL_ERROR;
03116         }
03117
03118         /* Clear STOP Flag */
03119         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
03120       }
03121
03122       /* Increment Trials */
03123       I2C_Trials++;
03124     }
03125     while (I2C_Trials < Trials);
03126
03127     /* Update I2C state */
03128     hi2c->State = HAL_I2C_STATE_READY;
03129
03130     /* Update I2C error code */
03131     hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
03132
03133     /* Process Unlocked */
03134     __HAL_UNLOCK(hi2c);
03135
03136     return HAL_ERROR;
03137   }
03138   else
03139   {
03140     return HAL_BUSY;
03141   }
03142 }
03143
03144 /**
03145   * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
03146   * @note   This interface allow to manage repeated start condition when a direction change during transfer
03147   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03148   *                the configuration information for the specified I2C.
03149   * @param  DevAddress Target device address: The device 7 bits address value
03150   *         in datasheet must be shifted to the left before calling the interface
03151   * @param  pData Pointer to data buffer
03152   * @param  Size Amount of data to be sent
03153   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
03154   * @retval HAL status
03155   */
03156 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
03157 {
03158   uint32_t xfermode;
03159   uint32_t xferrequest = I2C_GENERATE_START_WRITE;
03160
03161   /* Check the parameters */
03162   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
03163
03164   if (hi2c->State == HAL_I2C_STATE_READY)
03165   {
03166     /* Process Locked */
03167     __HAL_LOCK(hi2c);
03168
03169     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
03170     hi2c->Mode      = HAL_I2C_MODE_MASTER;
03171     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
03172
03173     /* Prepare transfer parameters */
03174     hi2c->pBuffPtr    = pData;
03175     hi2c->XferCount   = Size;
03176     hi2c->XferOptions = XferOptions;
03177     hi2c->XferISR     = I2C_Master_ISR_IT;
03178
03179     /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
03180     if (hi2c->XferCount > MAX_NBYTE_SIZE)
03181     {
03182       hi2c->XferSize = MAX_NBYTE_SIZE;
03183       xfermode = I2C_RELOAD_MODE;
03184     }
03185     else
03186     {
03187       hi2c->XferSize = hi2c->XferCount;
03188       xfermode = hi2c->XferOptions;
03189     }
03190
03191     /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
03192     /* Mean Previous state is same as current state */
03193     if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
03194     {
03195       xferrequest = I2C_NO_STARTSTOP;
03196     }
03197     else
03198     {
03199       /* Convert OTHER_xxx XferOptions if any */
03200       I2C_ConvertOtherXferOptions(hi2c);
03201
03202       /* Update xfermode accordingly if no reload is necessary */
03203       if (hi2c->XferCount < MAX_NBYTE_SIZE)
03204       {
03205         xfermode = hi2c->XferOptions;
03206       }
03207     }
03208
03209     /* Send Slave Address and set NBYTES to write */
03210     I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
03211
03212     /* Process Unlocked */
03213     __HAL_UNLOCK(hi2c);
03214
03215     /* Note : The I2C interrupts must be enabled after unlocking current process
03216               to avoid the risk of I2C interrupt handle execution before current
03217               process unlock */
03218     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
03219
03220     return HAL_OK;
03221   }
03222   else
03223   {
03224     return HAL_BUSY;
03225   }
03226 }
03227
03228 /**
03229   * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
03230   * @note   This interface allow to manage repeated start condition when a direction change during transfer
03231   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03232   *                the configuration information for the specified I2C.
03233   * @param  DevAddress Target device address: The device 7 bits address value
03234   *         in datasheet must be shifted to the left before calling the interface
03235   * @param  pData Pointer to data buffer
03236   * @param  Size Amount of data to be sent
03237   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
03238   * @retval HAL status
03239   */
03240 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
03241 {
03242   uint32_t xfermode;
03243   uint32_t xferrequest = I2C_GENERATE_START_WRITE;
03244   HAL_StatusTypeDef dmaxferstatus;
03245
03246   /* Check the parameters */
03247   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
03248
03249   if (hi2c->State == HAL_I2C_STATE_READY)
03250   {
03251     /* Process Locked */
03252     __HAL_LOCK(hi2c);
03253
03254     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
03255     hi2c->Mode      = HAL_I2C_MODE_MASTER;
03256     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
03257
03258     /* Prepare transfer parameters */
03259     hi2c->pBuffPtr    = pData;
03260     hi2c->XferCount   = Size;
03261     hi2c->XferOptions = XferOptions;
03262     hi2c->XferISR     = I2C_Master_ISR_DMA;
03263
03264     /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
03265     if (hi2c->XferCount > MAX_NBYTE_SIZE)
03266     {
03267       hi2c->XferSize = MAX_NBYTE_SIZE;
03268       xfermode = I2C_RELOAD_MODE;
03269     }
03270     else
03271     {
03272       hi2c->XferSize = hi2c->XferCount;
03273       xfermode = hi2c->XferOptions;
03274     }
03275
03276     /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
03277     /* Mean Previous state is same as current state */
03278     if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
03279     {
03280       xferrequest = I2C_NO_STARTSTOP;
03281     }
03282     else
03283     {
03284       /* Convert OTHER_xxx XferOptions if any */
03285       I2C_ConvertOtherXferOptions(hi2c);
03286
03287       /* Update xfermode accordingly if no reload is necessary */
03288       if (hi2c->XferCount < MAX_NBYTE_SIZE)
03289       {
03290         xfermode = hi2c->XferOptions;
03291       }
03292     }
03293
03294     if (hi2c->XferSize > 0U)
03295     {
03296       if (hi2c->hdmatx != NULL)
03297       {
03298         /* Set the I2C DMA transfer complete callback */
03299         hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
03300
03301         /* Set the DMA error callback */
03302         hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
03303
03304         /* Set the unused DMA callbacks to NULL */
03305         hi2c->hdmatx->XferHalfCpltCallback = NULL;
03306         hi2c->hdmatx->XferAbortCallback = NULL;
03307
03308         /* Enable the DMA channel */
03309         dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
03310       }
03311       else
03312       {
03313         /* Update I2C state */
03314         hi2c->State     = HAL_I2C_STATE_READY;
03315         hi2c->Mode      = HAL_I2C_MODE_NONE;
03316
03317         /* Update I2C error code */
03318         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
03319
03320         /* Process Unlocked */
03321         __HAL_UNLOCK(hi2c);
03322
03323         return HAL_ERROR;
03324       }
03325
03326       if (dmaxferstatus == HAL_OK)
03327       {
03328         /* Send Slave Address and set NBYTES to write */
03329         I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
03330
03331         /* Update XferCount value */
03332         hi2c->XferCount -= hi2c->XferSize;
03333
03334         /* Process Unlocked */
03335         __HAL_UNLOCK(hi2c);
03336
03337         /* Note : The I2C interrupts must be enabled after unlocking current process
03338                   to avoid the risk of I2C interrupt handle execution before current
03339                   process unlock */
03340         /* Enable ERR and NACK interrupts */
03341         I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
03342
03343         /* Enable DMA Request */
03344         hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
03345       }
03346       else
03347       {
03348         /* Update I2C state */
03349         hi2c->State     = HAL_I2C_STATE_READY;
03350         hi2c->Mode      = HAL_I2C_MODE_NONE;
03351
03352         /* Update I2C error code */
03353         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
03354
03355         /* Process Unlocked */
03356         __HAL_UNLOCK(hi2c);
03357
03358         return HAL_ERROR;
03359       }
03360     }
03361     else
03362     {
03363       /* Update Transfer ISR function pointer */
03364       hi2c->XferISR = I2C_Master_ISR_IT;
03365
03366       /* Send Slave Address */
03367       /* Set NBYTES to write and generate START condition */
03368       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
03369
03370       /* Process Unlocked */
03371       __HAL_UNLOCK(hi2c);
03372
03373       /* Note : The I2C interrupts must be enabled after unlocking current process
03374                 to avoid the risk of I2C interrupt handle execution before current
03375                 process unlock */
03376       /* Enable ERR, TC, STOP, NACK, TXI interrupt */
03377       /* possible to enable all of these */
03378       /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
03379       I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
03380     }
03381
03382     return HAL_OK;
03383   }
03384   else
03385   {
03386     return HAL_BUSY;
03387   }
03388 }
03389
03390 /**
03391   * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
03392   * @note   This interface allow to manage repeated start condition when a direction change during transfer
03393   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03394   *                the configuration information for the specified I2C.
03395   * @param  DevAddress Target device address: The device 7 bits address value
03396   *         in datasheet must be shifted to the left before calling the interface
03397   * @param  pData Pointer to data buffer
03398   * @param  Size Amount of data to be sent
03399   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
03400   * @retval HAL status
03401   */
03402 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
03403 {
03404   uint32_t xfermode;
03405   uint32_t xferrequest = I2C_GENERATE_START_READ;
03406
03407   /* Check the parameters */
03408   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
03409
03410   if (hi2c->State == HAL_I2C_STATE_READY)
03411   {
03412     /* Process Locked */
03413     __HAL_LOCK(hi2c);
03414
03415     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
03416     hi2c->Mode      = HAL_I2C_MODE_MASTER;
03417     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
03418
03419     /* Prepare transfer parameters */
03420     hi2c->pBuffPtr    = pData;
03421     hi2c->XferCount   = Size;
03422     hi2c->XferOptions = XferOptions;
03423     hi2c->XferISR     = I2C_Master_ISR_IT;
03424
03425     /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
03426     if (hi2c->XferCount > MAX_NBYTE_SIZE)
03427     {
03428       hi2c->XferSize = MAX_NBYTE_SIZE;
03429       xfermode = I2C_RELOAD_MODE;
03430     }
03431     else
03432     {
03433       hi2c->XferSize = hi2c->XferCount;
03434       xfermode = hi2c->XferOptions;
03435     }
03436
03437     /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
03438     /* Mean Previous state is same as current state */
03439     if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
03440     {
03441       xferrequest = I2C_NO_STARTSTOP;
03442     }
03443     else
03444     {
03445       /* Convert OTHER_xxx XferOptions if any */
03446       I2C_ConvertOtherXferOptions(hi2c);
03447
03448       /* Update xfermode accordingly if no reload is necessary */
03449       if (hi2c->XferCount < MAX_NBYTE_SIZE)
03450       {
03451         xfermode = hi2c->XferOptions;
03452       }
03453     }
03454
03455     /* Send Slave Address and set NBYTES to read */
03456     I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
03457
03458     /* Process Unlocked */
03459     __HAL_UNLOCK(hi2c);
03460
03461     /* Note : The I2C interrupts must be enabled after unlocking current process
03462               to avoid the risk of I2C interrupt handle execution before current
03463               process unlock */
03464     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
03465
03466     return HAL_OK;
03467   }
03468   else
03469   {
03470     return HAL_BUSY;
03471   }
03472 }
03473
03474 /**
03475   * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA
03476   * @note   This interface allow to manage repeated start condition when a direction change during transfer
03477   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03478   *                the configuration information for the specified I2C.
03479   * @param  DevAddress Target device address: The device 7 bits address value
03480   *         in datasheet must be shifted to the left before calling the interface
03481   * @param  pData Pointer to data buffer
03482   * @param  Size Amount of data to be sent
03483   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
03484   * @retval HAL status
03485   */
03486 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
03487 {
03488   uint32_t xfermode;
03489   uint32_t xferrequest = I2C_GENERATE_START_READ;
03490   HAL_StatusTypeDef dmaxferstatus;
03491
03492   /* Check the parameters */
03493   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
03494
03495   if (hi2c->State == HAL_I2C_STATE_READY)
03496   {
03497     /* Process Locked */
03498     __HAL_LOCK(hi2c);
03499
03500     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
03501     hi2c->Mode      = HAL_I2C_MODE_MASTER;
03502     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
03503
03504     /* Prepare transfer parameters */
03505     hi2c->pBuffPtr    = pData;
03506     hi2c->XferCount   = Size;
03507     hi2c->XferOptions = XferOptions;
03508     hi2c->XferISR     = I2C_Master_ISR_DMA;
03509
03510     /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
03511     if (hi2c->XferCount > MAX_NBYTE_SIZE)
03512     {
03513       hi2c->XferSize = MAX_NBYTE_SIZE;
03514       xfermode = I2C_RELOAD_MODE;
03515     }
03516     else
03517     {
03518       hi2c->XferSize = hi2c->XferCount;
03519       xfermode = hi2c->XferOptions;
03520     }
03521
03522     /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
03523     /* Mean Previous state is same as current state */
03524     if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
03525     {
03526       xferrequest = I2C_NO_STARTSTOP;
03527     }
03528     else
03529     {
03530       /* Convert OTHER_xxx XferOptions if any */
03531       I2C_ConvertOtherXferOptions(hi2c);
03532
03533       /* Update xfermode accordingly if no reload is necessary */
03534       if (hi2c->XferCount < MAX_NBYTE_SIZE)
03535       {
03536         xfermode = hi2c->XferOptions;
03537       }
03538     }
03539
03540     if (hi2c->XferSize > 0U)
03541     {
03542       if (hi2c->hdmarx != NULL)
03543       {
03544         /* Set the I2C DMA transfer complete callback */
03545         hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
03546
03547         /* Set the DMA error callback */
03548         hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
03549
03550         /* Set the unused DMA callbacks to NULL */
03551         hi2c->hdmarx->XferHalfCpltCallback = NULL;
03552         hi2c->hdmarx->XferAbortCallback = NULL;
03553
03554         /* Enable the DMA channel */
03555         dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
03556       }
03557       else
03558       {
03559         /* Update I2C state */
03560         hi2c->State     = HAL_I2C_STATE_READY;
03561         hi2c->Mode      = HAL_I2C_MODE_NONE;
03562
03563         /* Update I2C error code */
03564         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
03565
03566         /* Process Unlocked */
03567         __HAL_UNLOCK(hi2c);
03568
03569         return HAL_ERROR;
03570       }
03571
03572       if (dmaxferstatus == HAL_OK)
03573       {
03574         /* Send Slave Address and set NBYTES to read */
03575         I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
03576
03577         /* Update XferCount value */
03578         hi2c->XferCount -= hi2c->XferSize;
03579
03580         /* Process Unlocked */
03581         __HAL_UNLOCK(hi2c);
03582
03583         /* Note : The I2C interrupts must be enabled after unlocking current process
03584                   to avoid the risk of I2C interrupt handle execution before current
03585                   process unlock */
03586         /* Enable ERR and NACK interrupts */
03587         I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
03588
03589         /* Enable DMA Request */
03590         hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
03591       }
03592       else
03593       {
03594         /* Update I2C state */
03595         hi2c->State     = HAL_I2C_STATE_READY;
03596         hi2c->Mode      = HAL_I2C_MODE_NONE;
03597
03598         /* Update I2C error code */
03599         hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
03600
03601         /* Process Unlocked */
03602         __HAL_UNLOCK(hi2c);
03603
03604         return HAL_ERROR;
03605       }
03606     }
03607     else
03608     {
03609       /* Update Transfer ISR function pointer */
03610       hi2c->XferISR = I2C_Master_ISR_IT;
03611
03612       /* Send Slave Address */
03613       /* Set NBYTES to read and generate START condition */
03614       I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
03615
03616       /* Process Unlocked */
03617       __HAL_UNLOCK(hi2c);
03618
03619       /* Note : The I2C interrupts must be enabled after unlocking current process
03620                 to avoid the risk of I2C interrupt handle execution before current
03621                 process unlock */
03622       /* Enable ERR, TC, STOP, NACK, TXI interrupt */
03623       /* possible to enable all of these */
03624       /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
03625       I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
03626     }
03627
03628     return HAL_OK;
03629   }
03630   else
03631   {
03632     return HAL_BUSY;
03633   }
03634 }
03635
03636 /**
03637   * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
03638   * @note   This interface allow to manage repeated start condition when a direction change during transfer
03639   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03640   *                the configuration information for the specified I2C.
03641   * @param  pData Pointer to data buffer
03642   * @param  Size Amount of data to be sent
03643   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
03644   * @retval HAL status
03645   */
03646 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
03647 {
03648   /* Check the parameters */
03649   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
03650
03651   if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
03652   {
03653     if ((pData == NULL) || (Size == 0U))
03654     {
03655       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
03656       return  HAL_ERROR;
03657     }
03658
03659     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
03660     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
03661
03662     /* Process Locked */
03663     __HAL_LOCK(hi2c);
03664
03665     /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
03666     /* and then toggle the HAL slave RX state to TX state */
03667     if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
03668     {
03669       /* Disable associated Interrupts */
03670       I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
03671
03672       /* Abort DMA Xfer if any */
03673       if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
03674       {
03675         hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
03676
03677         if (hi2c->hdmarx != NULL)
03678         {
03679           /* Set the I2C DMA Abort callback :
03680            will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
03681           hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
03682
03683           /* Abort DMA RX */
03684           if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
03685           {
03686             /* Call Directly XferAbortCallback function in case of error */
03687             hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
03688           }
03689         }
03690       }
03691     }
03692
03693     hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
03694     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
03695     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
03696
03697     /* Enable Address Acknowledge */
03698     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
03699
03700     /* Prepare transfer parameters */
03701     hi2c->pBuffPtr    = pData;
03702     hi2c->XferCount   = Size;
03703     hi2c->XferSize    = hi2c->XferCount;
03704     hi2c->XferOptions = XferOptions;
03705     hi2c->XferISR     = I2C_Slave_ISR_IT;
03706
03707     if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
03708     {
03709       /* Clear ADDR flag after prepare the transfer parameters */
03710       /* This action will generate an acknowledge to the Master */
03711       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
03712     }
03713
03714     /* Process Unlocked */
03715     __HAL_UNLOCK(hi2c);
03716
03717     /* Note : The I2C interrupts must be enabled after unlocking current process
03718     to avoid the risk of I2C interrupt handle execution before current
03719     process unlock */
03720     /* REnable ADDR interrupt */
03721     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
03722
03723     return HAL_OK;
03724   }
03725   else
03726   {
03727     return HAL_ERROR;
03728   }
03729 }
03730
03731 /**
03732   * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA
03733   * @note   This interface allow to manage repeated start condition when a direction change during transfer
03734   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03735   *                the configuration information for the specified I2C.
03736   * @param  pData Pointer to data buffer
03737   * @param  Size Amount of data to be sent
03738   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
03739   * @retval HAL status
03740   */
03741 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
03742 {
03743   HAL_StatusTypeDef dmaxferstatus;
03744
03745   /* Check the parameters */
03746   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
03747
03748   if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
03749   {
03750     if ((pData == NULL) || (Size == 0U))
03751     {
03752       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
03753       return  HAL_ERROR;
03754     }
03755
03756     /* Process Locked */
03757     __HAL_LOCK(hi2c);
03758
03759     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
03760     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
03761
03762     /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
03763     /* and then toggle the HAL slave RX state to TX state */
03764     if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
03765     {
03766       /* Disable associated Interrupts */
03767       I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
03768
03769       if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
03770       {
03771         /* Abort DMA Xfer if any */
03772         if (hi2c->hdmarx != NULL)
03773         {
03774           hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
03775
03776           /* Set the I2C DMA Abort callback :
03777            will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
03778           hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
03779
03780           /* Abort DMA RX */
03781           if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
03782           {
03783             /* Call Directly XferAbortCallback function in case of error */
03784             hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
03785           }
03786         }
03787       }
03788     }
03789     else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
03790     {
03791       if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
03792       {
03793         hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
03794
03795         /* Abort DMA Xfer if any */
03796         if (hi2c->hdmatx != NULL)
03797         {
03798           /* Set the I2C DMA Abort callback :
03799            will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
03800           hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
03801
03802           /* Abort DMA TX */
03803           if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
03804           {
03805             /* Call Directly XferAbortCallback function in case of error */
03806             hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
03807           }
03808         }
03809       }
03810     }
03811     else
03812     {
03813       /* Nothing to do */
03814     }
03815
03816     hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
03817     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
03818     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
03819
03820     /* Enable Address Acknowledge */
03821     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
03822
03823     /* Prepare transfer parameters */
03824     hi2c->pBuffPtr    = pData;
03825     hi2c->XferCount   = Size;
03826     hi2c->XferSize    = hi2c->XferCount;
03827     hi2c->XferOptions = XferOptions;
03828     hi2c->XferISR     = I2C_Slave_ISR_DMA;
03829
03830     if (hi2c->hdmatx != NULL)
03831     {
03832       /* Set the I2C DMA transfer complete callback */
03833       hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
03834
03835       /* Set the DMA error callback */
03836       hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
03837
03838       /* Set the unused DMA callbacks to NULL */
03839       hi2c->hdmatx->XferHalfCpltCallback = NULL;
03840       hi2c->hdmatx->XferAbortCallback = NULL;
03841
03842       /* Enable the DMA channel */
03843       dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
03844     }
03845     else
03846     {
03847       /* Update I2C state */
03848       hi2c->State     = HAL_I2C_STATE_LISTEN;
03849       hi2c->Mode      = HAL_I2C_MODE_NONE;
03850
03851       /* Update I2C error code */
03852       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
03853
03854       /* Process Unlocked */
03855       __HAL_UNLOCK(hi2c);
03856
03857       return HAL_ERROR;
03858     }
03859
03860     if (dmaxferstatus == HAL_OK)
03861     {
03862       /* Update XferCount value */
03863       hi2c->XferCount -= hi2c->XferSize;
03864
03865       /* Reset XferSize */
03866       hi2c->XferSize = 0;
03867     }
03868     else
03869     {
03870       /* Update I2C state */
03871       hi2c->State     = HAL_I2C_STATE_LISTEN;
03872       hi2c->Mode      = HAL_I2C_MODE_NONE;
03873
03874       /* Update I2C error code */
03875       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
03876
03877       /* Process Unlocked */
03878       __HAL_UNLOCK(hi2c);
03879
03880       return HAL_ERROR;
03881     }
03882
03883     if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
03884     {
03885       /* Clear ADDR flag after prepare the transfer parameters */
03886       /* This action will generate an acknowledge to the Master */
03887       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
03888     }
03889
03890     /* Process Unlocked */
03891     __HAL_UNLOCK(hi2c);
03892
03893     /* Note : The I2C interrupts must be enabled after unlocking current process
03894     to avoid the risk of I2C interrupt handle execution before current
03895     process unlock */
03896     /* Enable ERR, STOP, NACK, ADDR interrupts */
03897     I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
03898
03899     /* Enable DMA Request */
03900     hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
03901
03902     return HAL_OK;
03903   }
03904   else
03905   {
03906     return HAL_ERROR;
03907   }
03908 }
03909
03910 /**
03911   * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
03912   * @note   This interface allow to manage repeated start condition when a direction change during transfer
03913   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03914   *                the configuration information for the specified I2C.
03915   * @param  pData Pointer to data buffer
03916   * @param  Size Amount of data to be sent
03917   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
03918   * @retval HAL status
03919   */
03920 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
03921 {
03922   /* Check the parameters */
03923   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
03924
03925   if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
03926   {
03927     if ((pData == NULL) || (Size == 0U))
03928     {
03929       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
03930       return  HAL_ERROR;
03931     }
03932
03933     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
03934     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
03935
03936     /* Process Locked */
03937     __HAL_LOCK(hi2c);
03938
03939     /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
03940     /* and then toggle the HAL slave TX state to RX state */
03941     if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
03942     {
03943       /* Disable associated Interrupts */
03944       I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
03945
03946       if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
03947       {
03948         hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
03949
03950         /* Abort DMA Xfer if any */
03951         if (hi2c->hdmatx != NULL)
03952         {
03953           /* Set the I2C DMA Abort callback :
03954            will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
03955           hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
03956
03957           /* Abort DMA TX */
03958           if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
03959           {
03960             /* Call Directly XferAbortCallback function in case of error */
03961             hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
03962           }
03963         }
03964       }
03965     }
03966
03967     hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
03968     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
03969     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
03970
03971     /* Enable Address Acknowledge */
03972     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
03973
03974     /* Prepare transfer parameters */
03975     hi2c->pBuffPtr    = pData;
03976     hi2c->XferCount   = Size;
03977     hi2c->XferSize    = hi2c->XferCount;
03978     hi2c->XferOptions = XferOptions;
03979     hi2c->XferISR     = I2C_Slave_ISR_IT;
03980
03981     if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
03982     {
03983       /* Clear ADDR flag after prepare the transfer parameters */
03984       /* This action will generate an acknowledge to the Master */
03985       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
03986     }
03987
03988     /* Process Unlocked */
03989     __HAL_UNLOCK(hi2c);
03990
03991     /* Note : The I2C interrupts must be enabled after unlocking current process
03992     to avoid the risk of I2C interrupt handle execution before current
03993     process unlock */
03994     /* REnable ADDR interrupt */
03995     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
03996
03997     return HAL_OK;
03998   }
03999   else
04000   {
04001     return HAL_ERROR;
04002   }
04003 }
04004
04005 /**
04006   * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA
04007   * @note   This interface allow to manage repeated start condition when a direction change during transfer
04008   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04009   *                the configuration information for the specified I2C.
04010   * @param  pData Pointer to data buffer
04011   * @param  Size Amount of data to be sent
04012   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
04013   * @retval HAL status
04014   */
04015 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
04016 {
04017   HAL_StatusTypeDef dmaxferstatus;
04018
04019   /* Check the parameters */
04020   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
04021
04022   if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
04023   {
04024     if ((pData == NULL) || (Size == 0U))
04025     {
04026       hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
04027       return  HAL_ERROR;
04028     }
04029
04030     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
04031     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
04032
04033     /* Process Locked */
04034     __HAL_LOCK(hi2c);
04035
04036     /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
04037     /* and then toggle the HAL slave TX state to RX state */
04038     if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
04039     {
04040       /* Disable associated Interrupts */
04041       I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
04042
04043       if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
04044       {
04045         /* Abort DMA Xfer if any */
04046         if (hi2c->hdmatx != NULL)
04047         {
04048           hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
04049
04050           /* Set the I2C DMA Abort callback :
04051            will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
04052           hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
04053
04054           /* Abort DMA TX */
04055           if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
04056           {
04057             /* Call Directly XferAbortCallback function in case of error */
04058             hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
04059           }
04060         }
04061       }
04062     }
04063     else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
04064     {
04065       if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
04066       {
04067         hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
04068
04069         /* Abort DMA Xfer if any */
04070         if (hi2c->hdmarx != NULL)
04071         {
04072           /* Set the I2C DMA Abort callback :
04073            will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
04074           hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
04075
04076           /* Abort DMA RX */
04077           if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
04078           {
04079             /* Call Directly XferAbortCallback function in case of error */
04080             hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
04081           }
04082         }
04083       }
04084     }
04085     else
04086     {
04087       /* Nothing to do */
04088     }
04089
04090     hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
04091     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
04092     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
04093
04094     /* Enable Address Acknowledge */
04095     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
04096
04097     /* Prepare transfer parameters */
04098     hi2c->pBuffPtr    = pData;
04099     hi2c->XferCount   = Size;
04100     hi2c->XferSize    = hi2c->XferCount;
04101     hi2c->XferOptions = XferOptions;
04102     hi2c->XferISR     = I2C_Slave_ISR_DMA;
04103
04104     if (hi2c->hdmarx != NULL)
04105     {
04106       /* Set the I2C DMA transfer complete callback */
04107       hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
04108
04109       /* Set the DMA error callback */
04110       hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
04111
04112       /* Set the unused DMA callbacks to NULL */
04113       hi2c->hdmarx->XferHalfCpltCallback = NULL;
04114       hi2c->hdmarx->XferAbortCallback = NULL;
04115
04116       /* Enable the DMA channel */
04117       dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
04118     }
04119     else
04120     {
04121       /* Update I2C state */
04122       hi2c->State     = HAL_I2C_STATE_LISTEN;
04123       hi2c->Mode      = HAL_I2C_MODE_NONE;
04124
04125       /* Update I2C error code */
04126       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
04127
04128       /* Process Unlocked */
04129       __HAL_UNLOCK(hi2c);
04130
04131       return HAL_ERROR;
04132     }
04133
04134     if (dmaxferstatus == HAL_OK)
04135     {
04136       /* Update XferCount value */
04137       hi2c->XferCount -= hi2c->XferSize;
04138
04139       /* Reset XferSize */
04140       hi2c->XferSize = 0;
04141     }
04142     else
04143     {
04144       /* Update I2C state */
04145       hi2c->State     = HAL_I2C_STATE_LISTEN;
04146       hi2c->Mode      = HAL_I2C_MODE_NONE;
04147
04148       /* Update I2C error code */
04149       hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
04150
04151       /* Process Unlocked */
04152       __HAL_UNLOCK(hi2c);
04153
04154       return HAL_ERROR;
04155     }
04156
04157     if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
04158     {
04159       /* Clear ADDR flag after prepare the transfer parameters */
04160       /* This action will generate an acknowledge to the Master */
04161       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
04162     }
04163
04164     /* Process Unlocked */
04165     __HAL_UNLOCK(hi2c);
04166
04167     /* Note : The I2C interrupts must be enabled after unlocking current process
04168     to avoid the risk of I2C interrupt handle execution before current
04169     process unlock */
04170     /* REnable ADDR interrupt */
04171     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
04172
04173     /* Enable DMA Request */
04174     hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
04175
04176     return HAL_OK;
04177   }
04178   else
04179   {
04180     return HAL_ERROR;
04181   }
04182 }
04183
04184 /**
04185   * @brief  Enable the Address listen mode with Interrupt.
04186   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04187   *                the configuration information for the specified I2C.
04188   * @retval HAL status
04189   */
04190 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
04191 {
04192   if (hi2c->State == HAL_I2C_STATE_READY)
04193   {
04194     hi2c->State = HAL_I2C_STATE_LISTEN;
04195     hi2c->XferISR = I2C_Slave_ISR_IT;
04196
04197     /* Enable the Address Match interrupt */
04198     I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
04199
04200     return HAL_OK;
04201   }
04202   else
04203   {
04204     return HAL_BUSY;
04205   }
04206 }
04207
04208 /**
04209   * @brief  Disable the Address listen mode with Interrupt.
04210   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04211   *                the configuration information for the specified I2C
04212   * @retval HAL status
04213   */
04214 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
04215 {
04216   /* Declaration of tmp to prevent undefined behavior of volatile usage */
04217   uint32_t tmp;
04218
04219   /* Disable Address listen mode only if a transfer is not ongoing */
04220   if (hi2c->State == HAL_I2C_STATE_LISTEN)
04221   {
04222     tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
04223     hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
04224     hi2c->State = HAL_I2C_STATE_READY;
04225     hi2c->Mode = HAL_I2C_MODE_NONE;
04226     hi2c->XferISR = NULL;
04227
04228     /* Disable the Address Match interrupt */
04229     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
04230
04231     return HAL_OK;
04232   }
04233   else
04234   {
04235     return HAL_BUSY;
04236   }
04237 }
04238
04239 /**
04240   * @brief  Abort a master I2C IT or DMA process communication with Interrupt.
04241   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04242   *                the configuration information for the specified I2C.
04243   * @param  DevAddress Target device address: The device 7 bits address value
04244   *         in datasheet must be shifted to the left before calling the interface
04245   * @retval HAL status
04246   */
04247 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
04248 {
04249   if (hi2c->Mode == HAL_I2C_MODE_MASTER)
04250   {
04251     /* Process Locked */
04252     __HAL_LOCK(hi2c);
04253
04254     /* Disable Interrupts */
04255     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
04256     I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
04257
04258     /* Set State at HAL_I2C_STATE_ABORT */
04259     hi2c->State = HAL_I2C_STATE_ABORT;
04260
04261     /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
04262     /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
04263     I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
04264
04265     /* Process Unlocked */
04266     __HAL_UNLOCK(hi2c);
04267
04268     /* Note : The I2C interrupts must be enabled after unlocking current process
04269               to avoid the risk of I2C interrupt handle execution before current
04270               process unlock */
04271     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
04272
04273     return HAL_OK;
04274   }
04275   else
04276   {
04277     /* Wrong usage of abort function */
04278     /* This function should be used only in case of abort monitored by master device */
04279     return HAL_ERROR;
04280   }
04281 }
04282
04283 /**
04284   * @}
04285   */
04286
04287 /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
04288  * @{
04289  */
04290
04291 /**
04292   * @brief  This function handles I2C event interrupt request.
04293   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04294   *                the configuration information for the specified I2C.
04295   * @retval None
04296   */
04297 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
04298 {
04299   /* Get current IT Flags and IT sources value */
04300   uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
04301   uint32_t itsources = READ_REG(hi2c->Instance->CR1);
04302
04303   /* I2C events treatment -------------------------------------*/
04304   if (hi2c->XferISR != NULL)
04305   {
04306     hi2c->XferISR(hi2c, itflags, itsources);
04307   }
04308 }
04309
04310 /**
04311   * @brief  This function handles I2C error interrupt request.
04312   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04313   *                the configuration information for the specified I2C.
04314   * @retval None
04315   */
04316 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
04317 {
04318   uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
04319   uint32_t itsources = READ_REG(hi2c->Instance->CR1);
04320   uint32_t tmperror;
04321
04322   /* I2C Bus error interrupt occurred ------------------------------------*/
04323   if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
04324   {
04325     hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
04326
04327     /* Clear BERR flag */
04328     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
04329   }
04330
04331   /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
04332   if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
04333   {
04334     hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
04335
04336     /* Clear OVR flag */
04337     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
04338   }
04339
04340   /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
04341   if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
04342   {
04343     hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
04344
04345     /* Clear ARLO flag */
04346     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
04347   }
04348
04349   /* Store current volatile hi2c->ErrorCode, misra rule */
04350   tmperror = hi2c->ErrorCode;
04351
04352   /* Call the Error Callback in case of Error detected */
04353   if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) !=  HAL_I2C_ERROR_NONE)
04354   {
04355     I2C_ITError(hi2c, tmperror);
04356   }
04357 }
04358
04359 /**
04360   * @brief  Master Tx Transfer completed callback.
04361   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04362   *                the configuration information for the specified I2C.
04363   * @retval None
04364   */
04365 __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
04366 {
04367   /* Prevent unused argument(s) compilation warning */
04368   UNUSED(hi2c);
04369
04370   /* NOTE : This function should not be modified, when the callback is needed,
04371             the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
04372    */
04373 }
04374
04375 /**
04376   * @brief  Master Rx Transfer completed callback.
04377   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04378   *                the configuration information for the specified I2C.
04379   * @retval None
04380   */
04381 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
04382 {
04383   /* Prevent unused argument(s) compilation warning */
04384   UNUSED(hi2c);
04385
04386   /* NOTE : This function should not be modified, when the callback is needed,
04387             the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
04388    */
04389 }
04390
04391 /** @brief  Slave Tx Transfer completed callback.
04392   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04393   *                the configuration information for the specified I2C.
04394   * @retval None
04395   */
04396 __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
04397 {
04398   /* Prevent unused argument(s) compilation warning */
04399   UNUSED(hi2c);
04400
04401   /* NOTE : This function should not be modified, when the callback is needed,
04402             the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
04403    */
04404 }
04405
04406 /**
04407   * @brief  Slave Rx Transfer completed callback.
04408   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04409   *                the configuration information for the specified I2C.
04410   * @retval None
04411   */
04412 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
04413 {
04414   /* Prevent unused argument(s) compilation warning */
04415   UNUSED(hi2c);
04416
04417   /* NOTE : This function should not be modified, when the callback is needed,
04418             the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
04419    */
04420 }
04421
04422 /**
04423   * @brief  Slave Address Match callback.
04424   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04425   *                the configuration information for the specified I2C.
04426   * @param  TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
04427   * @param  AddrMatchCode Address Match Code
04428   * @retval None
04429   */
04430 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
04431 {
04432   /* Prevent unused argument(s) compilation warning */
04433   UNUSED(hi2c);
04434   UNUSED(TransferDirection);
04435   UNUSED(AddrMatchCode);
04436
04437   /* NOTE : This function should not be modified, when the callback is needed,
04438             the HAL_I2C_AddrCallback() could be implemented in the user file
04439    */
04440 }
04441
04442 /**
04443   * @brief  Listen Complete callback.
04444   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04445   *                the configuration information for the specified I2C.
04446   * @retval None
04447   */
04448 __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
04449 {
04450   /* Prevent unused argument(s) compilation warning */
04451   UNUSED(hi2c);
04452
04453   /* NOTE : This function should not be modified, when the callback is needed,
04454             the HAL_I2C_ListenCpltCallback() could be implemented in the user file
04455    */
04456 }
04457
04458 /**
04459   * @brief  Memory Tx Transfer completed callback.
04460   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04461   *                the configuration information for the specified I2C.
04462   * @retval None
04463   */
04464 __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
04465 {
04466   /* Prevent unused argument(s) compilation warning */
04467   UNUSED(hi2c);
04468
04469   /* NOTE : This function should not be modified, when the callback is needed,
04470             the HAL_I2C_MemTxCpltCallback could be implemented in the user file
04471    */
04472 }
04473
04474 /**
04475   * @brief  Memory Rx Transfer completed callback.
04476   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04477   *                the configuration information for the specified I2C.
04478   * @retval None
04479   */
04480 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
04481 {
04482   /* Prevent unused argument(s) compilation warning */
04483   UNUSED(hi2c);
04484
04485   /* NOTE : This function should not be modified, when the callback is needed,
04486             the HAL_I2C_MemRxCpltCallback could be implemented in the user file
04487    */
04488 }
04489
04490 /**
04491   * @brief  I2C error callback.
04492   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04493   *                the configuration information for the specified I2C.
04494   * @retval None
04495   */
04496 __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
04497 {
04498   /* Prevent unused argument(s) compilation warning */
04499   UNUSED(hi2c);
04500
04501   /* NOTE : This function should not be modified, when the callback is needed,
04502             the HAL_I2C_ErrorCallback could be implemented in the user file
04503    */
04504 }
04505
04506 /**
04507   * @brief  I2C abort callback.
04508   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04509   *                the configuration information for the specified I2C.
04510   * @retval None
04511   */
04512 __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
04513 {
04514   /* Prevent unused argument(s) compilation warning */
04515   UNUSED(hi2c);
04516
04517   /* NOTE : This function should not be modified, when the callback is needed,
04518             the HAL_I2C_AbortCpltCallback could be implemented in the user file
04519    */
04520 }
04521
04522 /**
04523   * @}
04524   */
04525
04526 /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
04527  *  @brief   Peripheral State, Mode and Error functions
04528  *
04529 @verbatim
04530  ===============================================================================
04531             ##### Peripheral State, Mode and Error functions #####
04532  ===============================================================================
04533     [..]
04534     This subsection permit to get in run-time the status of the peripheral
04535     and the data flow.
04536
04537 @endverbatim
04538   * @{
04539   */
04540
04541 /**
04542   * @brief  Return the I2C handle state.
04543   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04544   *                the configuration information for the specified I2C.
04545   * @retval HAL state
04546   */
04547 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
04548 {
04549   /* Return I2C handle state */
04550   return hi2c->State;
04551 }
04552
04553 /**
04554   * @brief  Returns the I2C Master, Slave, Memory or no mode.
04555   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04556   *         the configuration information for I2C module
04557   * @retval HAL mode
04558   */
04559 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
04560 {
04561   return hi2c->Mode;
04562 }
04563
04564 /**
04565 * @brief  Return the I2C error code.
04566   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04567   *              the configuration information for the specified I2C.
04568 * @retval I2C Error Code
04569 */
04570 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
04571 {
04572   return hi2c->ErrorCode;
04573 }
04574
04575 /**
04576   * @}
04577   */
04578
04579 /**
04580   * @}
04581   */
04582
04583 /** @addtogroup I2C_Private_Functions
04584   * @{
04585   */
04586
04587 /**
04588   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
04589   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04590   *                the configuration information for the specified I2C.
04591   * @param  ITFlags Interrupt flags to handle.
04592   * @param  ITSources Interrupt sources enabled.
04593   * @retval HAL status
04594   */
04595 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
04596 {
04597   uint16_t devaddress;
04598   uint32_t tmpITFlags = ITFlags;
04599
04600   /* Process Locked */
04601   __HAL_LOCK(hi2c);
04602
04603   if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
04604   {
04605     /* Clear NACK Flag */
04606     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
04607
04608     /* Set corresponding Error Code */
04609     /* No need to generate STOP, it is automatically done */
04610     /* Error callback will be send during stop flag treatment */
04611     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
04612
04613     /* Flush TX register */
04614     I2C_Flush_TXDR(hi2c);
04615   }
04616   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
04617   {
04618     /* Remove RXNE flag on temporary variable as read done */
04619     tmpITFlags &= ~I2C_FLAG_RXNE;
04620
04621     /* Read data from RXDR */
04622     *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
04623
04624     /* Increment Buffer pointer */
04625     hi2c->pBuffPtr++;
04626
04627     hi2c->XferSize--;
04628     hi2c->XferCount--;
04629   }
04630   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
04631   {
04632     /* Write data to TXDR */
04633     hi2c->Instance->TXDR = *hi2c->pBuffPtr;
04634
04635     /* Increment Buffer pointer */
04636     hi2c->pBuffPtr++;
04637
04638     hi2c->XferSize--;
04639     hi2c->XferCount--;
04640   }
04641   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
04642   {
04643     if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
04644     {
04645       devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
04646
04647       if (hi2c->XferCount > MAX_NBYTE_SIZE)
04648       {
04649         hi2c->XferSize = MAX_NBYTE_SIZE;
04650         I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
04651       }
04652       else
04653       {
04654         hi2c->XferSize = hi2c->XferCount;
04655         if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
04656         {
04657           I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);
04658         }
04659         else
04660         {
04661           I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
04662         }
04663       }
04664     }
04665     else
04666     {
04667       /* Call TxCpltCallback() if no stop mode is set */
04668       if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
04669       {
04670         /* Call I2C Master Sequential complete process */
04671         I2C_ITMasterSeqCplt(hi2c);
04672       }
04673       else
04674       {
04675         /* Wrong size Status regarding TCR flag event */
04676         /* Call the corresponding callback to inform upper layer of End of Transfer */
04677         I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
04678       }
04679     }
04680   }
04681   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
04682   {
04683     if (hi2c->XferCount == 0U)
04684     {
04685       if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
04686       {
04687         /* Generate a stop condition in case of no transfer option */
04688         if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
04689         {
04690           /* Generate Stop */
04691           hi2c->Instance->CR2 |= I2C_CR2_STOP;
04692         }
04693         else
04694         {
04695           /* Call I2C Master Sequential complete process */
04696           I2C_ITMasterSeqCplt(hi2c);
04697         }
04698       }
04699     }
04700     else
04701     {
04702       /* Wrong size Status regarding TC flag event */
04703       /* Call the corresponding callback to inform upper layer of End of Transfer */
04704       I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
04705     }
04706   }
04707   else
04708   {
04709     /* Nothing to do */
04710   }
04711
04712   if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
04713   {
04714     /* Call I2C Master complete process */
04715     I2C_ITMasterCplt(hi2c, tmpITFlags);
04716   }
04717
04718   /* Process Unlocked */
04719   __HAL_UNLOCK(hi2c);
04720
04721   return HAL_OK;
04722 }
04723
04724 /**
04725   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
04726   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04727   *                the configuration information for the specified I2C.
04728   * @param  ITFlags Interrupt flags to handle.
04729   * @param  ITSources Interrupt sources enabled.
04730   * @retval HAL status
04731   */
04732 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
04733 {
04734   uint32_t tmpoptions = hi2c->XferOptions;
04735   uint32_t tmpITFlags = ITFlags;
04736
04737   /* Process locked */
04738   __HAL_LOCK(hi2c);
04739
04740   if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
04741   {
04742     /* Check that I2C transfer finished */
04743     /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
04744     /* Mean XferCount == 0*/
04745     /* So clear Flag NACKF only */
04746     if (hi2c->XferCount == 0U)
04747     {
04748       if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
04749       {
04750         /* Call I2C Listen complete process */
04751         I2C_ITListenCplt(hi2c, tmpITFlags);
04752       }
04753       else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
04754       {
04755         /* Clear NACK Flag */
04756         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
04757
04758         /* Flush TX register */
04759         I2C_Flush_TXDR(hi2c);
04760
04761         /* Last Byte is Transmitted */
04762         /* Call I2C Slave Sequential complete process */
04763         I2C_ITSlaveSeqCplt(hi2c);
04764       }
04765       else
04766       {
04767         /* Clear NACK Flag */
04768         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
04769       }
04770     }
04771     else
04772     {
04773       /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
04774       /* Clear NACK Flag */
04775       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
04776
04777       /* Set ErrorCode corresponding to a Non-Acknowledge */
04778       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
04779
04780       if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
04781       {
04782         /* Call the corresponding callback to inform upper layer of End of Transfer */
04783         I2C_ITError(hi2c, hi2c->ErrorCode);
04784       }
04785     }
04786   }
04787   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
04788   {
04789     if (hi2c->XferCount > 0U)
04790     {
04791       /* Remove RXNE flag on temporary variable as read done */
04792       tmpITFlags &= ~I2C_FLAG_RXNE;
04793
04794       /* Read data from RXDR */
04795       *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
04796
04797       /* Increment Buffer pointer */
04798       hi2c->pBuffPtr++;
04799
04800       hi2c->XferSize--;
04801       hi2c->XferCount--;
04802     }
04803
04804     if ((hi2c->XferCount == 0U) && \
04805         (tmpoptions != I2C_NO_OPTION_FRAME))
04806     {
04807       /* Call I2C Slave Sequential complete process */
04808       I2C_ITSlaveSeqCplt(hi2c);
04809     }
04810   }
04811   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
04812   {
04813     I2C_ITAddrCplt(hi2c, tmpITFlags);
04814   }
04815   else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
04816   {
04817     /* Write data to TXDR only if XferCount not reach "0" */
04818     /* A TXIS flag can be set, during STOP treatment      */
04819     /* Check if all Datas have already been sent */
04820     /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
04821     if (hi2c->XferCount > 0U)
04822     {
04823       /* Write data to TXDR */
04824       hi2c->Instance->TXDR = *hi2c->pBuffPtr;
04825
04826       /* Increment Buffer pointer */
04827       hi2c->pBuffPtr++;
04828
04829       hi2c->XferCount--;
04830       hi2c->XferSize--;
04831     }
04832     else
04833     {
04834       if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
04835       {
04836         /* Last Byte is Transmitted */
04837         /* Call I2C Slave Sequential complete process */
04838         I2C_ITSlaveSeqCplt(hi2c);
04839       }
04840     }
04841   }
04842   else
04843   {
04844     /* Nothing to do */
04845   }
04846
04847   /* Check if STOPF is set */
04848   if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
04849   {
04850     /* Call I2C Slave complete process */
04851     I2C_ITSlaveCplt(hi2c, tmpITFlags);
04852   }
04853
04854   /* Process Unlocked */
04855   __HAL_UNLOCK(hi2c);
04856
04857   return HAL_OK;
04858 }
04859
04860 /**
04861   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
04862   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04863   *                the configuration information for the specified I2C.
04864   * @param  ITFlags Interrupt flags to handle.
04865   * @param  ITSources Interrupt sources enabled.
04866   * @retval HAL status
04867   */
04868 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
04869 {
04870   uint16_t devaddress;
04871   uint32_t xfermode;
04872
04873   /* Process Locked */
04874   __HAL_LOCK(hi2c);
04875
04876   if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
04877   {
04878     /* Clear NACK Flag */
04879     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
04880
04881     /* Set corresponding Error Code */
04882     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
04883
04884     /* No need to generate STOP, it is automatically done */
04885     /* But enable STOP interrupt, to treat it */
04886     /* Error callback will be send during stop flag treatment */
04887     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
04888
04889     /* Flush TX register */
04890     I2C_Flush_TXDR(hi2c);
04891   }
04892   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
04893   {
04894     /* Disable TC interrupt */
04895     __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
04896
04897     if (hi2c->XferCount != 0U)
04898     {
04899       /* Recover Slave address */
04900       devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
04901
04902       /* Prepare the new XferSize to transfer */
04903       if (hi2c->XferCount > MAX_NBYTE_SIZE)
04904       {
04905         hi2c->XferSize = MAX_NBYTE_SIZE;
04906         xfermode = I2C_RELOAD_MODE;
04907       }
04908       else
04909       {
04910         hi2c->XferSize = hi2c->XferCount;
04911         if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
04912         {
04913           xfermode = hi2c->XferOptions;
04914         }
04915         else
04916         {
04917           xfermode = I2C_AUTOEND_MODE;
04918         }
04919       }
04920
04921       /* Set the new XferSize in Nbytes register */
04922       I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
04923
04924       /* Update XferCount value */
04925       hi2c->XferCount -= hi2c->XferSize;
04926
04927       /* Enable DMA Request */
04928       if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
04929       {
04930         hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
04931       }
04932       else
04933       {
04934         hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
04935       }
04936     }
04937     else
04938     {
04939       /* Call TxCpltCallback() if no stop mode is set */
04940       if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
04941       {
04942         /* Call I2C Master Sequential complete process */
04943         I2C_ITMasterSeqCplt(hi2c);
04944       }
04945       else
04946       {
04947         /* Wrong size Status regarding TCR flag event */
04948         /* Call the corresponding callback to inform upper layer of End of Transfer */
04949         I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
04950       }
04951     }
04952   }
04953   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
04954   {
04955     if (hi2c->XferCount == 0U)
04956     {
04957       if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
04958       {
04959         /* Generate a stop condition in case of no transfer option */
04960         if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
04961         {
04962           /* Generate Stop */
04963           hi2c->Instance->CR2 |= I2C_CR2_STOP;
04964         }
04965         else
04966         {
04967           /* Call I2C Master Sequential complete process */
04968           I2C_ITMasterSeqCplt(hi2c);
04969         }
04970       }
04971     }
04972     else
04973     {
04974       /* Wrong size Status regarding TC flag event */
04975       /* Call the corresponding callback to inform upper layer of End of Transfer */
04976       I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
04977     }
04978   }
04979   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
04980   {
04981     /* Call I2C Master complete process */
04982     I2C_ITMasterCplt(hi2c, ITFlags);
04983   }
04984   else
04985   {
04986     /* Nothing to do */
04987   }
04988
04989   /* Process Unlocked */
04990   __HAL_UNLOCK(hi2c);
04991
04992   return HAL_OK;
04993 }
04994
04995 /**
04996   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
04997   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04998   *                the configuration information for the specified I2C.
04999   * @param  ITFlags Interrupt flags to handle.
05000   * @param  ITSources Interrupt sources enabled.
05001   * @retval HAL status
05002   */
05003 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
05004 {
05005   uint32_t tmpoptions = hi2c->XferOptions;
05006   uint32_t treatdmanack = 0U;
05007
05008   /* Process locked */
05009   __HAL_LOCK(hi2c);
05010
05011   if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
05012   {
05013     /* Check that I2C transfer finished */
05014     /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
05015     /* Mean XferCount == 0 */
05016     /* So clear Flag NACKF only */
05017     if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
05018         (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
05019     {
05020       /* Split check of hdmarx, for MISRA compliance */
05021       if (hi2c->hdmarx != NULL)
05022       {
05023         if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
05024         {
05025           if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U)
05026           {
05027             treatdmanack = 1U;
05028           }
05029         }
05030       }
05031
05032       /* Split check of hdmatx, for MISRA compliance  */
05033       if (hi2c->hdmatx != NULL)
05034       {
05035         if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
05036         {
05037           if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U)
05038           {
05039             treatdmanack = 1U;
05040           }
05041         }
05042       }
05043
05044       if (treatdmanack == 1U)
05045       {
05046         if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
05047         {
05048           /* Call I2C Listen complete process */
05049           I2C_ITListenCplt(hi2c, ITFlags);
05050         }
05051         else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
05052         {
05053           /* Clear NACK Flag */
05054           __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
05055
05056           /* Flush TX register */
05057           I2C_Flush_TXDR(hi2c);
05058
05059           /* Last Byte is Transmitted */
05060           /* Call I2C Slave Sequential complete process */
05061           I2C_ITSlaveSeqCplt(hi2c);
05062         }
05063         else
05064         {
05065           /* Clear NACK Flag */
05066           __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
05067         }
05068       }
05069       else
05070       {
05071         /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
05072         /* Clear NACK Flag */
05073         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
05074
05075         /* Set ErrorCode corresponding to a Non-Acknowledge */
05076         hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
05077
05078         if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
05079         {
05080           /* Call the corresponding callback to inform upper layer of End of Transfer */
05081           I2C_ITError(hi2c, hi2c->ErrorCode);
05082         }
05083       }
05084     }
05085     else
05086     {
05087       /* Only Clear NACK Flag, no DMA treatment is pending */
05088       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
05089     }
05090   }
05091   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
05092   {
05093     I2C_ITAddrCplt(hi2c, ITFlags);
05094   }
05095   else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
05096   {
05097     /* Call I2C Slave complete process */
05098     I2C_ITSlaveCplt(hi2c, ITFlags);
05099   }
05100   else
05101   {
05102     /* Nothing to do */
05103   }
05104
05105   /* Process Unlocked */
05106   __HAL_UNLOCK(hi2c);
05107
05108   return HAL_OK;
05109 }
05110
05111 /**
05112   * @brief  Master sends target device address followed by internal memory address for write request.
05113   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
05114   *                the configuration information for the specified I2C.
05115   * @param  DevAddress Target device address: The device 7 bits address value
05116   *         in datasheet must be shifted to the left before calling the interface
05117   * @param  MemAddress Internal memory address
05118   * @param  MemAddSize Size of internal memory address
05119   * @param  Timeout Timeout duration
05120   * @param  Tickstart Tick start value
05121   * @retval HAL status
05122   */
05123 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
05124 {
05125   I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
05126
05127   /* Wait until TXIS flag is set */
05128   if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
05129   {
05130     return HAL_ERROR;
05131   }
05132
05133   /* If Memory address size is 8Bit */
05134   if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
05135   {
05136     /* Send Memory Address */
05137     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
05138   }
05139   /* If Memory address size is 16Bit */
05140   else
05141   {
05142     /* Send MSB of Memory Address */
05143     hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
05144
05145     /* Wait until TXIS flag is set */
05146     if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
05147     {
05148       return HAL_ERROR;
05149     }
05150
05151     /* Send LSB of Memory Address */
05152     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
05153   }
05154
05155   /* Wait until TCR flag is set */
05156   if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
05157   {
05158     return HAL_ERROR;
05159   }
05160
05161   return HAL_OK;
05162 }
05163
05164 /**
05165   * @brief  Master sends target device address followed by internal memory address for read request.
05166   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
05167   *                the configuration information for the specified I2C.
05168   * @param  DevAddress Target device address: The device 7 bits address value
05169   *         in datasheet must be shifted to the left before calling the interface
05170   * @param  MemAddress Internal memory address
05171   * @param  MemAddSize Size of internal memory address
05172   * @param  Timeout Timeout duration
05173   * @param  Tickstart Tick start value
05174   * @retval HAL status
05175   */
05176 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
05177 {
05178   I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
05179
05180   /* Wait until TXIS flag is set */
05181   if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
05182   {
05183     return HAL_ERROR;
05184   }
05185
05186   /* If Memory address size is 8Bit */
05187   if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
05188   {
05189     /* Send Memory Address */
05190     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
05191   }
05192   /* If Memory address size is 16Bit */
05193   else
05194   {
05195     /* Send MSB of Memory Address */
05196     hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
05197
05198     /* Wait until TXIS flag is set */
05199     if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
05200     {
05201       return HAL_ERROR;
05202     }
05203
05204     /* Send LSB of Memory Address */
05205     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
05206   }
05207
05208   /* Wait until TC flag is set */
05209   if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
05210   {
05211     return HAL_ERROR;
05212   }
05213
05214   return HAL_OK;
05215 }
05216
05217 /**
05218   * @brief  I2C Address complete process callback.
05219   * @param  hi2c I2C handle.
05220   * @param  ITFlags Interrupt flags to handle.
05221   * @retval None
05222   */
05223 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
05224 {
05225   uint8_t transferdirection;
05226   uint16_t slaveaddrcode;
05227   uint16_t ownadd1code;
05228   uint16_t ownadd2code;
05229
05230   /* Prevent unused argument(s) compilation warning */
05231   UNUSED(ITFlags);
05232
05233   /* In case of Listen state, need to inform upper layer of address match code event */
05234   if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
05235   {
05236     transferdirection = I2C_GET_DIR(hi2c);
05237     slaveaddrcode     = I2C_GET_ADDR_MATCH(hi2c);
05238     ownadd1code       = I2C_GET_OWN_ADDRESS1(hi2c);
05239     ownadd2code       = I2C_GET_OWN_ADDRESS2(hi2c);
05240
05241     /* If 10bits addressing mode is selected */
05242     if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
05243     {
05244       if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))
05245       {
05246         slaveaddrcode = ownadd1code;
05247         hi2c->AddrEventCount++;
05248         if (hi2c->AddrEventCount == 2U)
05249         {
05250           /* Reset Address Event counter */
05251           hi2c->AddrEventCount = 0U;
05252
05253           /* Clear ADDR flag */
05254           __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
05255
05256           /* Process Unlocked */
05257           __HAL_UNLOCK(hi2c);
05258
05259           /* Call Slave Addr callback */
05260 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05261           hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
05262 #else
05263           HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
05264 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05265         }
05266       }
05267       else
05268       {
05269         slaveaddrcode = ownadd2code;
05270
05271         /* Disable ADDR Interrupts */
05272         I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
05273
05274         /* Process Unlocked */
05275         __HAL_UNLOCK(hi2c);
05276
05277         /* Call Slave Addr callback */
05278 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05279         hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
05280 #else
05281         HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
05282 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05283       }
05284     }
05285     /* else 7 bits addressing mode is selected */
05286     else
05287     {
05288       /* Disable ADDR Interrupts */
05289       I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
05290
05291       /* Process Unlocked */
05292       __HAL_UNLOCK(hi2c);
05293
05294       /* Call Slave Addr callback */
05295 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05296       hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
05297 #else
05298       HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
05299 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05300     }
05301   }
05302   /* Else clear address flag only */
05303   else
05304   {
05305     /* Clear ADDR flag */
05306     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
05307
05308     /* Process Unlocked */
05309     __HAL_UNLOCK(hi2c);
05310   }
05311 }
05312
05313 /**
05314   * @brief  I2C Master sequential complete process.
05315   * @param  hi2c I2C handle.
05316   * @retval None
05317   */
05318 static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
05319 {
05320   /* Reset I2C handle mode */
05321   hi2c->Mode = HAL_I2C_MODE_NONE;
05322
05323   /* No Generate Stop, to permit restart mode */
05324   /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
05325   if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
05326   {
05327     hi2c->State         = HAL_I2C_STATE_READY;
05328     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
05329     hi2c->XferISR       = NULL;
05330
05331     /* Disable Interrupts */
05332     I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
05333
05334     /* Process Unlocked */
05335     __HAL_UNLOCK(hi2c);
05336
05337     /* Call the corresponding callback to inform upper layer of End of Transfer */
05338 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05339     hi2c->MasterTxCpltCallback(hi2c);
05340 #else
05341     HAL_I2C_MasterTxCpltCallback(hi2c);
05342 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05343   }
05344   /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
05345   else
05346   {
05347     hi2c->State         = HAL_I2C_STATE_READY;
05348     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
05349     hi2c->XferISR       = NULL;
05350
05351     /* Disable Interrupts */
05352     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
05353
05354     /* Process Unlocked */
05355     __HAL_UNLOCK(hi2c);
05356
05357     /* Call the corresponding callback to inform upper layer of End of Transfer */
05358 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05359     hi2c->MasterRxCpltCallback(hi2c);
05360 #else
05361     HAL_I2C_MasterRxCpltCallback(hi2c);
05362 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05363   }
05364 }
05365
05366 /**
05367   * @brief  I2C Slave sequential complete process.
05368   * @param  hi2c I2C handle.
05369   * @retval None
05370   */
05371 static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
05372 {
05373   /* Reset I2C handle mode */
05374   hi2c->Mode = HAL_I2C_MODE_NONE;
05375
05376   if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
05377   {
05378     /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
05379     hi2c->State         = HAL_I2C_STATE_LISTEN;
05380     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
05381
05382     /* Disable Interrupts */
05383     I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
05384
05385     /* Process Unlocked */
05386     __HAL_UNLOCK(hi2c);
05387
05388     /* Call the corresponding callback to inform upper layer of End of Transfer */
05389 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05390     hi2c->SlaveTxCpltCallback(hi2c);
05391 #else
05392     HAL_I2C_SlaveTxCpltCallback(hi2c);
05393 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05394   }
05395
05396   else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
05397   {
05398     /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
05399     hi2c->State         = HAL_I2C_STATE_LISTEN;
05400     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
05401
05402     /* Disable Interrupts */
05403     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
05404
05405     /* Process Unlocked */
05406     __HAL_UNLOCK(hi2c);
05407
05408     /* Call the corresponding callback to inform upper layer of End of Transfer */
05409 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05410     hi2c->SlaveRxCpltCallback(hi2c);
05411 #else
05412     HAL_I2C_SlaveRxCpltCallback(hi2c);
05413 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05414   }
05415   else
05416   {
05417     /* Nothing to do */
05418   }
05419 }
05420
05421 /**
05422   * @brief  I2C Master complete process.
05423   * @param  hi2c I2C handle.
05424   * @param  ITFlags Interrupt flags to handle.
05425   * @retval None
05426   */
05427 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
05428 {
05429   uint32_t tmperror;
05430
05431   /* Clear STOP Flag */
05432   __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
05433
05434   /* Clear Configuration Register 2 */
05435   I2C_RESET_CR2(hi2c);
05436
05437   /* Reset handle parameters */
05438   hi2c->PreviousState = I2C_STATE_NONE;
05439   hi2c->XferISR       = NULL;
05440   hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
05441
05442   if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET)
05443   {
05444     /* Clear NACK Flag */
05445     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
05446
05447     /* Set acknowledge error code */
05448     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
05449   }
05450
05451   /* Flush TX register */
05452   I2C_Flush_TXDR(hi2c);
05453
05454   /* Disable Interrupts */
05455   I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT);
05456
05457   /* Store current volatile hi2c->ErrorCode, misra rule */
05458   tmperror = hi2c->ErrorCode;
05459
05460   /* Call the corresponding callback to inform upper layer of End of Transfer */
05461   if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))
05462   {
05463     /* Call the corresponding callback to inform upper layer of End of Transfer */
05464     I2C_ITError(hi2c, hi2c->ErrorCode);
05465   }
05466   /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
05467   else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
05468   {
05469     hi2c->State = HAL_I2C_STATE_READY;
05470
05471     if (hi2c->Mode == HAL_I2C_MODE_MEM)
05472     {
05473       hi2c->Mode = HAL_I2C_MODE_NONE;
05474
05475       /* Process Unlocked */
05476       __HAL_UNLOCK(hi2c);
05477
05478       /* Call the corresponding callback to inform upper layer of End of Transfer */
05479 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05480       hi2c->MemTxCpltCallback(hi2c);
05481 #else
05482       HAL_I2C_MemTxCpltCallback(hi2c);
05483 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05484     }
05485     else
05486     {
05487       hi2c->Mode = HAL_I2C_MODE_NONE;
05488
05489       /* Process Unlocked */
05490       __HAL_UNLOCK(hi2c);
05491
05492       /* Call the corresponding callback to inform upper layer of End of Transfer */
05493 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05494       hi2c->MasterTxCpltCallback(hi2c);
05495 #else
05496       HAL_I2C_MasterTxCpltCallback(hi2c);
05497 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05498     }
05499   }
05500   /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
05501   else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
05502   {
05503     hi2c->State = HAL_I2C_STATE_READY;
05504
05505     if (hi2c->Mode == HAL_I2C_MODE_MEM)
05506     {
05507       hi2c->Mode = HAL_I2C_MODE_NONE;
05508
05509       /* Process Unlocked */
05510       __HAL_UNLOCK(hi2c);
05511
05512       /* Call the corresponding callback to inform upper layer of End of Transfer */
05513 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05514       hi2c->MemRxCpltCallback(hi2c);
05515 #else
05516       HAL_I2C_MemRxCpltCallback(hi2c);
05517 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05518     }
05519     else
05520     {
05521       hi2c->Mode = HAL_I2C_MODE_NONE;
05522
05523       /* Process Unlocked */
05524       __HAL_UNLOCK(hi2c);
05525
05526       /* Call the corresponding callback to inform upper layer of End of Transfer */
05527 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05528       hi2c->MasterRxCpltCallback(hi2c);
05529 #else
05530       HAL_I2C_MasterRxCpltCallback(hi2c);
05531 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05532     }
05533   }
05534   else
05535   {
05536     /* Nothing to do */
05537   }
05538 }
05539
05540 /**
05541   * @brief  I2C Slave complete process.
05542   * @param  hi2c I2C handle.
05543   * @param  ITFlags Interrupt flags to handle.
05544   * @retval None
05545   */
05546 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
05547 {
05548   uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
05549   uint32_t tmpITFlags = ITFlags;
05550
05551   /* Clear STOP Flag */
05552   __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
05553
05554   /* Disable all interrupts */
05555   I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
05556
05557   /* Disable Address Acknowledge */
05558   hi2c->Instance->CR2 |= I2C_CR2_NACK;
05559
05560   /* Clear Configuration Register 2 */
05561   I2C_RESET_CR2(hi2c);
05562
05563   /* Flush TX register */
05564   I2C_Flush_TXDR(hi2c);
05565
05566   /* If a DMA is ongoing, Update handle size context */
05567   if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
05568   {
05569     if (hi2c->hdmatx != NULL)
05570     {
05571       hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx);
05572     }
05573   }
05574   else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
05575   {
05576     if (hi2c->hdmarx != NULL)
05577     {
05578       hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx);
05579     }
05580   }
05581   else
05582   {
05583     /* Do nothing */
05584   }
05585
05586   /* Store Last receive data if any */
05587   if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
05588   {
05589     /* Remove RXNE flag on temporary variable as read done */
05590     tmpITFlags &= ~I2C_FLAG_RXNE;
05591
05592     /* Read data from RXDR */
05593     *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
05594
05595     /* Increment Buffer pointer */
05596     hi2c->pBuffPtr++;
05597
05598     if ((hi2c->XferSize > 0U))
05599     {
05600       hi2c->XferSize--;
05601       hi2c->XferCount--;
05602     }
05603   }
05604
05605   /* All data are not transferred, so set error code accordingly */
05606   if (hi2c->XferCount != 0U)
05607   {
05608     /* Set ErrorCode corresponding to a Non-Acknowledge */
05609     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
05610   }
05611
05612   hi2c->PreviousState = I2C_STATE_NONE;
05613   hi2c->Mode = HAL_I2C_MODE_NONE;
05614   hi2c->XferISR = NULL;
05615
05616   if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
05617   {
05618     /* Call the corresponding callback to inform upper layer of End of Transfer */
05619     I2C_ITError(hi2c, hi2c->ErrorCode);
05620
05621     /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
05622     if (hi2c->State == HAL_I2C_STATE_LISTEN)
05623     {
05624       /* Call I2C Listen complete process */
05625       I2C_ITListenCplt(hi2c, tmpITFlags);
05626     }
05627   }
05628   else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
05629   {
05630     /* Call the Sequential Complete callback, to inform upper layer of the end of Tranfer */
05631     I2C_ITSlaveSeqCplt(hi2c);
05632
05633     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
05634     hi2c->State = HAL_I2C_STATE_READY;
05635
05636     /* Process Unlocked */
05637     __HAL_UNLOCK(hi2c);
05638
05639     /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
05640 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05641     hi2c->ListenCpltCallback(hi2c);
05642 #else
05643     HAL_I2C_ListenCpltCallback(hi2c);
05644 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05645   }
05646   /* Call the corresponding callback to inform upper layer of End of Transfer */
05647   else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
05648   {
05649     hi2c->State = HAL_I2C_STATE_READY;
05650
05651     /* Process Unlocked */
05652     __HAL_UNLOCK(hi2c);
05653
05654     /* Call the corresponding callback to inform upper layer of End of Transfer */
05655 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05656     hi2c->SlaveRxCpltCallback(hi2c);
05657 #else
05658     HAL_I2C_SlaveRxCpltCallback(hi2c);
05659 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05660   }
05661   else
05662   {
05663     hi2c->State = HAL_I2C_STATE_READY;
05664
05665     /* Process Unlocked */
05666     __HAL_UNLOCK(hi2c);
05667
05668     /* Call the corresponding callback to inform upper layer of End of Transfer */
05669 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05670     hi2c->SlaveTxCpltCallback(hi2c);
05671 #else
05672     HAL_I2C_SlaveTxCpltCallback(hi2c);
05673 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05674   }
05675 }
05676
05677 /**
05678   * @brief  I2C Listen complete process.
05679   * @param  hi2c I2C handle.
05680   * @param  ITFlags Interrupt flags to handle.
05681   * @retval None
05682   */
05683 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
05684 {
05685   /* Reset handle parameters */
05686   hi2c->XferOptions = I2C_NO_OPTION_FRAME;
05687   hi2c->PreviousState = I2C_STATE_NONE;
05688   hi2c->State = HAL_I2C_STATE_READY;
05689   hi2c->Mode = HAL_I2C_MODE_NONE;
05690   hi2c->XferISR = NULL;
05691
05692   /* Store Last receive data if any */
05693   if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)
05694   {
05695     /* Read data from RXDR */
05696     *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
05697
05698     /* Increment Buffer pointer */
05699     hi2c->pBuffPtr++;
05700
05701     if ((hi2c->XferSize > 0U))
05702     {
05703       hi2c->XferSize--;
05704       hi2c->XferCount--;
05705
05706       /* Set ErrorCode corresponding to a Non-Acknowledge */
05707       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
05708     }
05709   }
05710
05711   /* Disable all Interrupts*/
05712   I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
05713
05714   /* Clear NACK Flag */
05715   __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
05716
05717   /* Process Unlocked */
05718   __HAL_UNLOCK(hi2c);
05719
05720   /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
05721 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05722   hi2c->ListenCpltCallback(hi2c);
05723 #else
05724   HAL_I2C_ListenCpltCallback(hi2c);
05725 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05726 }
05727
05728 /**
05729   * @brief  I2C interrupts error process.
05730   * @param  hi2c I2C handle.
05731   * @param  ErrorCode Error code to handle.
05732   * @retval None
05733   */
05734 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
05735 {
05736   HAL_I2C_StateTypeDef tmpstate = hi2c->State;
05737
05738   /* Reset handle parameters */
05739   hi2c->Mode          = HAL_I2C_MODE_NONE;
05740   hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
05741   hi2c->XferCount     = 0U;
05742
05743   /* Set new error code */
05744   hi2c->ErrorCode |= ErrorCode;
05745
05746   /* Disable Interrupts */
05747   if ((tmpstate == HAL_I2C_STATE_LISTEN)         ||
05748       (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
05749       (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
05750   {
05751     /* Disable all interrupts, except interrupts related to LISTEN state */
05752     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
05753
05754     /* keep HAL_I2C_STATE_LISTEN if set */
05755     hi2c->State         = HAL_I2C_STATE_LISTEN;
05756     hi2c->PreviousState = I2C_STATE_NONE;
05757     hi2c->XferISR       = I2C_Slave_ISR_IT;
05758   }
05759   else
05760   {
05761     /* Disable all interrupts */
05762     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
05763
05764     /* If state is an abort treatment on goind, don't change state */
05765     /* This change will be do later */
05766     if (hi2c->State != HAL_I2C_STATE_ABORT)
05767     {
05768       /* Set HAL_I2C_STATE_READY */
05769       hi2c->State         = HAL_I2C_STATE_READY;
05770     }
05771     hi2c->PreviousState = I2C_STATE_NONE;
05772     hi2c->XferISR       = NULL;
05773   }
05774
05775   /* Abort DMA TX transfer if any */
05776   if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
05777   {
05778     hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
05779
05780     if (hi2c->hdmatx != NULL)
05781     {
05782       /* Set the I2C DMA Abort callback :
05783        will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
05784       hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
05785
05786       /* Process Unlocked */
05787       __HAL_UNLOCK(hi2c);
05788
05789       /* Abort DMA TX */
05790       if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
05791       {
05792         /* Call Directly XferAbortCallback function in case of error */
05793         hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
05794       }
05795     }
05796   }
05797   /* Abort DMA RX transfer if any */
05798   else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
05799   {
05800     hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
05801
05802     if (hi2c->hdmarx != NULL)
05803     {
05804       /* Set the I2C DMA Abort callback :
05805         will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
05806       hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
05807
05808       /* Process Unlocked */
05809       __HAL_UNLOCK(hi2c);
05810
05811       /* Abort DMA RX */
05812       if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
05813       {
05814         /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
05815         hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
05816       }
05817     }
05818   }
05819   else if (hi2c->State == HAL_I2C_STATE_ABORT)
05820   {
05821     hi2c->State = HAL_I2C_STATE_READY;
05822
05823     /* Process Unlocked */
05824     __HAL_UNLOCK(hi2c);
05825
05826     /* Call the corresponding callback to inform upper layer of End of Transfer */
05827 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05828     hi2c->AbortCpltCallback(hi2c);
05829 #else
05830     HAL_I2C_AbortCpltCallback(hi2c);
05831 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05832   }
05833   else
05834   {
05835     /* Process Unlocked */
05836     __HAL_UNLOCK(hi2c);
05837
05838     /* Call the corresponding callback to inform upper layer of End of Transfer */
05839 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
05840     hi2c->ErrorCallback(hi2c);
05841 #else
05842     HAL_I2C_ErrorCallback(hi2c);
05843 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
05844   }
05845 }
05846
05847 /**
05848   * @brief  I2C Tx data register flush process.
05849   * @param  hi2c I2C handle.
05850   * @retval None
05851   */
05852 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
05853 {
05854   /* If a pending TXIS flag is set */
05855   /* Write a dummy data in TXDR to clear it */
05856   if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
05857   {
05858     hi2c->Instance->TXDR = 0x00U;
05859   }
05860
05861   /* Flush TX register if not empty */
05862   if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
05863   {
05864     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
05865   }
05866 }
05867
05868 /**
05869   * @brief  DMA I2C master transmit process complete callback.
05870   * @param  hdma DMA handle
05871   * @retval None
05872   */
05873 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
05874 {
05875   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
05876
05877   /* Disable DMA Request */
05878   hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
05879
05880   /* If last transfer, enable STOP interrupt */
05881   if (hi2c->XferCount == 0U)
05882   {
05883     /* Enable STOP interrupt */
05884     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
05885   }
05886   /* else prepare a new DMA transfer and enable TCReload interrupt */
05887   else
05888   {
05889     /* Update Buffer pointer */
05890     hi2c->pBuffPtr += hi2c->XferSize;
05891
05892     /* Set the XferSize to transfer */
05893     if (hi2c->XferCount > MAX_NBYTE_SIZE)
05894     {
05895       hi2c->XferSize = MAX_NBYTE_SIZE;
05896     }
05897     else
05898     {
05899       hi2c->XferSize = hi2c->XferCount;
05900     }
05901
05902     /* Enable the DMA channel */
05903     if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize) != HAL_OK)
05904     {
05905       /* Call the corresponding callback to inform upper layer of End of Transfer */
05906       I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
05907     }
05908     else
05909     {
05910       /* Enable TC interrupts */
05911       I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
05912     }
05913   }
05914 }
05915
05916 /**
05917   * @brief  DMA I2C slave transmit process complete callback.
05918   * @param  hdma DMA handle
05919   * @retval None
05920   */
05921 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
05922 {
05923   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
05924   uint32_t tmpoptions = hi2c->XferOptions;
05925
05926   if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
05927   {
05928     /* Disable DMA Request */
05929     hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
05930
05931     /* Last Byte is Transmitted */
05932     /* Call I2C Slave Sequential complete process */
05933     I2C_ITSlaveSeqCplt(hi2c);
05934   }
05935   else
05936   {
05937     /* No specific action, Master fully manage the generation of STOP condition */
05938     /* Mean that this generation can arrive at any time, at the end or during DMA process */
05939     /* So STOP condition should be manage through Interrupt treatment */
05940   }
05941 }
05942
05943 /**
05944   * @brief DMA I2C master receive process complete callback.
05945   * @param  hdma DMA handle
05946   * @retval None
05947   */
05948 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
05949 {
05950   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
05951
05952   /* Disable DMA Request */
05953   hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
05954
05955   /* If last transfer, enable STOP interrupt */
05956   if (hi2c->XferCount == 0U)
05957   {
05958     /* Enable STOP interrupt */
05959     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
05960   }
05961   /* else prepare a new DMA transfer and enable TCReload interrupt */
05962   else
05963   {
05964     /* Update Buffer pointer */
05965     hi2c->pBuffPtr += hi2c->XferSize;
05966
05967     /* Set the XferSize to transfer */
05968     if (hi2c->XferCount > MAX_NBYTE_SIZE)
05969     {
05970       hi2c->XferSize = MAX_NBYTE_SIZE;
05971     }
05972     else
05973     {
05974       hi2c->XferSize = hi2c->XferCount;
05975     }
05976
05977     /* Enable the DMA channel */
05978     if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize) != HAL_OK)
05979     {
05980       /* Call the corresponding callback to inform upper layer of End of Transfer */
05981       I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
05982     }
05983     else
05984     {
05985       /* Enable TC interrupts */
05986       I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
05987     }
05988   }
05989 }
05990
05991 /**
05992   * @brief  DMA I2C slave receive process complete callback.
05993   * @param  hdma DMA handle
05994   * @retval None
05995   */
05996 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
05997 {
05998   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
05999   uint32_t tmpoptions = hi2c->XferOptions;
06000
06001   if ((__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) && \
06002       (tmpoptions != I2C_NO_OPTION_FRAME))
06003   {
06004     /* Disable DMA Request */
06005     hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
06006
06007     /* Call I2C Slave Sequential complete process */
06008     I2C_ITSlaveSeqCplt(hi2c);
06009   }
06010   else
06011   {
06012     /* No specific action, Master fully manage the generation of STOP condition */
06013     /* Mean that this generation can arrive at any time, at the end or during DMA process */
06014     /* So STOP condition should be manage through Interrupt treatment */
06015   }
06016 }
06017
06018 /**
06019   * @brief  DMA I2C communication error callback.
06020   * @param hdma DMA handle
06021   * @retval None
06022   */
06023 static void I2C_DMAError(DMA_HandleTypeDef *hdma)
06024 {
06025   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
06026
06027   /* Disable Acknowledge */
06028   hi2c->Instance->CR2 |= I2C_CR2_NACK;
06029
06030   /* Call the corresponding callback to inform upper layer of End of Transfer */
06031   I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
06032 }
06033
06034 /**
06035   * @brief DMA I2C communication abort callback
06036   *        (To be called at end of DMA Abort procedure).
06037   * @param hdma DMA handle.
06038   * @retval None
06039   */
06040 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
06041 {
06042   I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
06043
06044   /* Reset AbortCpltCallback */
06045   hi2c->hdmatx->XferAbortCallback = NULL;
06046   hi2c->hdmarx->XferAbortCallback = NULL;
06047
06048   /* Check if come from abort from user */
06049   if (hi2c->State == HAL_I2C_STATE_ABORT)
06050   {
06051     hi2c->State = HAL_I2C_STATE_READY;
06052
06053     /* Call the corresponding callback to inform upper layer of End of Transfer */
06054 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
06055     hi2c->AbortCpltCallback(hi2c);
06056 #else
06057     HAL_I2C_AbortCpltCallback(hi2c);
06058 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
06059   }
06060   else
06061   {
06062     /* Call the corresponding callback to inform upper layer of End of Transfer */
06063 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
06064     hi2c->ErrorCallback(hi2c);
06065 #else
06066     HAL_I2C_ErrorCallback(hi2c);
06067 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
06068   }
06069 }
06070
06071 /**
06072   * @brief  This function handles I2C Communication Timeout.
06073   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
06074   *                the configuration information for the specified I2C.
06075   * @param  Flag Specifies the I2C flag to check.
06076   * @param  Status The new Flag status (SET or RESET).
06077   * @param  Timeout Timeout duration
06078   * @param  Tickstart Tick start value
06079   * @retval HAL status
06080   */
06081 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
06082 {
06083   while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
06084   {
06085     /* Check for the Timeout */
06086     if (Timeout != HAL_MAX_DELAY)
06087     {
06088       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
06089       {
06090         hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
06091         hi2c->State = HAL_I2C_STATE_READY;
06092         hi2c->Mode = HAL_I2C_MODE_NONE;
06093
06094         /* Process Unlocked */
06095         __HAL_UNLOCK(hi2c);
06096         return HAL_ERROR;
06097       }
06098     }
06099   }
06100   return HAL_OK;
06101 }
06102
06103 /**
06104   * @brief  This function handles I2C Communication Timeout for specific usage of TXIS flag.
06105   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
06106   *                the configuration information for the specified I2C.
06107   * @param  Timeout Timeout duration
06108   * @param  Tickstart Tick start value
06109   * @retval HAL status
06110   */
06111 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
06112 {
06113   while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
06114   {
06115     /* Check if a NACK is detected */
06116     if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
06117     {
06118       return HAL_ERROR;
06119     }
06120
06121     /* Check for the Timeout */
06122     if (Timeout != HAL_MAX_DELAY)
06123     {
06124       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
06125       {
06126         hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
06127         hi2c->State = HAL_I2C_STATE_READY;
06128         hi2c->Mode = HAL_I2C_MODE_NONE;
06129
06130         /* Process Unlocked */
06131         __HAL_UNLOCK(hi2c);
06132
06133         return HAL_ERROR;
06134       }
06135     }
06136   }
06137   return HAL_OK;
06138 }
06139
06140 /**
06141   * @brief  This function handles I2C Communication Timeout for specific usage of STOP flag.
06142   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
06143   *                the configuration information for the specified I2C.
06144   * @param  Timeout Timeout duration
06145   * @param  Tickstart Tick start value
06146   * @retval HAL status
06147   */
06148 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
06149 {
06150   while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
06151   {
06152     /* Check if a NACK is detected */
06153     if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
06154     {
06155       return HAL_ERROR;
06156     }
06157
06158     /* Check for the Timeout */
06159     if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
06160     {
06161       hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
06162       hi2c->State = HAL_I2C_STATE_READY;
06163       hi2c->Mode = HAL_I2C_MODE_NONE;
06164
06165       /* Process Unlocked */
06166       __HAL_UNLOCK(hi2c);
06167
06168       return HAL_ERROR;
06169     }
06170   }
06171   return HAL_OK;
06172 }
06173
06174 /**
06175   * @brief  This function handles I2C Communication Timeout for specific usage of RXNE flag.
06176   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
06177   *                the configuration information for the specified I2C.
06178   * @param  Timeout Timeout duration
06179   * @param  Tickstart Tick start value
06180   * @retval HAL status
06181   */
06182 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
06183 {
06184   while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
06185   {
06186     /* Check if a NACK is detected */
06187     if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
06188     {
06189       return HAL_ERROR;
06190     }
06191
06192     /* Check if a STOPF is detected */
06193     if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
06194     {
06195       /* Check if an RXNE is pending */
06196       /* Store Last receive data if any */
06197       if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))
06198       {
06199         /* Return HAL_OK */
06200         /* The Reading of data from RXDR will be done in caller function */
06201         return HAL_OK;
06202       }
06203       else
06204       {
06205         /* Clear STOP Flag */
06206         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
06207
06208         /* Clear Configuration Register 2 */
06209         I2C_RESET_CR2(hi2c);
06210
06211         hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
06212         hi2c->State = HAL_I2C_STATE_READY;
06213         hi2c->Mode = HAL_I2C_MODE_NONE;
06214
06215         /* Process Unlocked */
06216         __HAL_UNLOCK(hi2c);
06217
06218         return HAL_ERROR;
06219       }
06220     }
06221
06222     /* Check for the Timeout */
06223     if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
06224     {
06225       hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
06226       hi2c->State = HAL_I2C_STATE_READY;
06227
06228       /* Process Unlocked */
06229       __HAL_UNLOCK(hi2c);
06230
06231       return HAL_ERROR;
06232     }
06233   }
06234   return HAL_OK;
06235 }
06236
06237 /**
06238   * @brief  This function handles Acknowledge failed detection during an I2C Communication.
06239   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
06240   *                the configuration information for the specified I2C.
06241   * @param  Timeout Timeout duration
06242   * @param  Tickstart Tick start value
06243   * @retval HAL status
06244   */
06245 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
06246 {
06247   if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
06248   {
06249     /* Wait until STOP Flag is reset */
06250     /* AutoEnd should be initiate after AF */
06251     while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
06252     {
06253       /* Check for the Timeout */
06254       if (Timeout != HAL_MAX_DELAY)
06255       {
06256         if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
06257         {
06258           hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
06259           hi2c->State = HAL_I2C_STATE_READY;
06260           hi2c->Mode = HAL_I2C_MODE_NONE;
06261
06262           /* Process Unlocked */
06263           __HAL_UNLOCK(hi2c);
06264
06265           return HAL_ERROR;
06266         }
06267       }
06268     }
06269
06270     /* Clear NACKF Flag */
06271     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
06272
06273     /* Clear STOP Flag */
06274     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
06275
06276     /* Flush TX register */
06277     I2C_Flush_TXDR(hi2c);
06278
06279     /* Clear Configuration Register 2 */
06280     I2C_RESET_CR2(hi2c);
06281
06282     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
06283     hi2c->State = HAL_I2C_STATE_READY;
06284     hi2c->Mode = HAL_I2C_MODE_NONE;
06285
06286     /* Process Unlocked */
06287     __HAL_UNLOCK(hi2c);
06288
06289     return HAL_ERROR;
06290   }
06291   return HAL_OK;
06292 }
06293
06294 /**
06295   * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
06296   * @param  hi2c I2C handle.
06297   * @param  DevAddress Specifies the slave address to be programmed.
06298   * @param  Size Specifies the number of bytes to be programmed.
06299   *   This parameter must be a value between 0 and 255.
06300   * @param  Mode New state of the I2C START condition generation.
06301   *   This parameter can be one of the following values:
06302   *     @arg @ref I2C_RELOAD_MODE Enable Reload mode .
06303   *     @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
06304   *     @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
06305   * @param  Request New state of the I2C START condition generation.
06306   *   This parameter can be one of the following values:
06307   *     @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
06308   *     @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
06309   *     @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
06310   *     @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
06311   * @retval None
06312   */
06313 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
06314 {
06315   /* Check the parameters */
06316   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
06317   assert_param(IS_TRANSFER_MODE(Mode));
06318   assert_param(IS_TRANSFER_REQUEST(Request));
06319
06320   /* update CR2 register */
06321   MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \
06322              (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
06323 }
06324
06325 /**
06326   * @brief  Manage the enabling of Interrupts.
06327   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
06328   *                the configuration information for the specified I2C.
06329   * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
06330   * @retval None
06331   */
06332 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
06333 {
06334   uint32_t tmpisr = 0U;
06335
06336   if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \
06337       (hi2c->XferISR == I2C_Slave_ISR_DMA))
06338   {
06339     if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
06340     {
06341       /* Enable ERR, STOP, NACK and ADDR interrupts */
06342       tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
06343     }
06344
06345     if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
06346     {
06347       /* Enable ERR and NACK interrupts */
06348       tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
06349     }
06350
06351     if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
06352     {
06353       /* Enable STOP interrupts */
06354       tmpisr |= I2C_IT_STOPI;
06355     }
06356
06357     if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
06358     {
06359       /* Enable TC interrupts */
06360       tmpisr |= I2C_IT_TCI;
06361     }
06362   }
06363   else
06364   {
06365     if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
06366     {
06367       /* Enable ERR, STOP, NACK, and ADDR interrupts */
06368       tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
06369     }
06370
06371     if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
06372     {
06373       /* Enable ERR, TC, STOP, NACK and RXI interrupts */
06374       tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
06375     }
06376
06377     if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
06378     {
06379       /* Enable ERR, TC, STOP, NACK and TXI interrupts */
06380       tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
06381     }
06382
06383     if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
06384     {
06385       /* Enable STOP interrupts */
06386       tmpisr |= I2C_IT_STOPI;
06387     }
06388   }
06389
06390   /* Enable interrupts only at the end */
06391   /* to avoid the risk of I2C interrupt handle execution before */
06392   /* all interrupts requested done */
06393   __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
06394 }
06395
06396 /**
06397   * @brief  Manage the disabling of Interrupts.
06398   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
06399   *                the configuration information for the specified I2C.
06400   * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
06401   * @retval None
06402   */
06403 static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
06404 {
06405   uint32_t tmpisr = 0U;
06406
06407   if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
06408   {
06409     /* Disable TC and TXI interrupts */
06410     tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
06411
06412     if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
06413     {
06414       /* Disable NACK and STOP interrupts */
06415       tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
06416     }
06417   }
06418
06419   if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
06420   {
06421     /* Disable TC and RXI interrupts */
06422     tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
06423
06424     if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
06425     {
06426       /* Disable NACK and STOP interrupts */
06427       tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
06428     }
06429   }
06430
06431   if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
06432   {
06433     /* Disable ADDR, NACK and STOP interrupts */
06434     tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
06435   }
06436
06437   if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
06438   {
06439     /* Enable ERR and NACK interrupts */
06440     tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
06441   }
06442
06443   if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
06444   {
06445     /* Enable STOP interrupts */
06446     tmpisr |= I2C_IT_STOPI;
06447   }
06448
06449   if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
06450   {
06451     /* Enable TC interrupts */
06452     tmpisr |= I2C_IT_TCI;
06453   }
06454
06455   /* Disable interrupts only at the end */
06456   /* to avoid a breaking situation like at "t" time */
06457   /* all disable interrupts request are not done */
06458   __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
06459 }
06460
06461 /**
06462   * @brief  Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions.
06463   * @param  hi2c I2C handle.
06464   * @retval None
06465   */
06466 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
06467 {
06468   /* if user set XferOptions to I2C_OTHER_FRAME            */
06469   /* it request implicitly to generate a restart condition */
06470   /* set XferOptions to I2C_FIRST_FRAME                    */
06471   if (hi2c->XferOptions == I2C_OTHER_FRAME)
06472   {
06473     hi2c->XferOptions = I2C_FIRST_FRAME;
06474   }
06475   /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
06476   /* it request implicitly to generate a restart condition    */
06477   /* then generate a stop condition at the end of transfer    */
06478   /* set XferOptions to I2C_FIRST_AND_LAST_FRAME              */
06479   else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
06480   {
06481     hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
06482   }
06483   else
06484   {
06485     /* Nothing to do */
06486   }
06487 }
06488
06489 /**
06490   * @}
06491   */
06492
06493 #endif /* HAL_I2C_MODULE_ENABLED */
06494 /**
06495   * @}
06496   */
06497
06498 /**
06499   * @}
06500   */
06501
06502 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_i2c.h Source File

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stm32wbxx_hal_i2c.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_i2c.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of I2C HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_I2C_H
00022 #define STM32WBxx_HAL_I2C_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 /** @addtogroup STM32WBxx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup I2C
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup I2C_Exported_Types I2C Exported Types
00041   * @{
00042   */
00043
00044 /** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
00045   * @brief  I2C Configuration Structure definition
00046   * @{
00047   */
00048 typedef struct
00049 {
00050   uint32_t Timing;              /*!< Specifies the I2C_TIMINGR_register value.
00051                                   This parameter calculated by referring to I2C initialization
00052                                          section in Reference manual */
00053
00054   uint32_t OwnAddress1;         /*!< Specifies the first device own address.
00055                                   This parameter can be a 7-bit or 10-bit address. */
00056
00057   uint32_t AddressingMode;      /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
00058                                   This parameter can be a value of @ref I2C_ADDRESSING_MODE */
00059
00060   uint32_t DualAddressMode;     /*!< Specifies if dual addressing mode is selected.
00061                                   This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
00062
00063   uint32_t OwnAddress2;         /*!< Specifies the second device own address if dual addressing mode is selected
00064                                   This parameter can be a 7-bit address. */
00065
00066   uint32_t OwnAddress2Masks;    /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
00067                                   This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
00068
00069   uint32_t GeneralCallMode;     /*!< Specifies if general call mode is selected.
00070                                   This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
00071
00072   uint32_t NoStretchMode;       /*!< Specifies if nostretch mode is selected.
00073                                   This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
00074
00075 } I2C_InitTypeDef;
00076
00077 /**
00078   * @}
00079   */
00080
00081 /** @defgroup HAL_state_structure_definition HAL state structure definition
00082   * @brief  HAL State structure definition
00083   * @note  HAL I2C State value coding follow below described bitmap :\n
00084   *          b7-b6  Error information\n
00085   *             00 : No Error\n
00086   *             01 : Abort (Abort user request on going)\n
00087   *             10 : Timeout\n
00088   *             11 : Error\n
00089   *          b5     Peripheral initialization status\n
00090   *             0  : Reset (peripheral not initialized)\n
00091   *             1  : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
00092   *          b4     (not used)\n
00093   *             x  : Should be set to 0\n
00094   *          b3\n
00095   *             0  : Ready or Busy (No Listen mode ongoing)\n
00096   *             1  : Listen (peripheral in Address Listen Mode)\n
00097   *          b2     Intrinsic process state\n
00098   *             0  : Ready\n
00099   *             1  : Busy (peripheral busy with some configuration or internal operations)\n
00100   *          b1     Rx state\n
00101   *             0  : Ready (no Rx operation ongoing)\n
00102   *             1  : Busy (Rx operation ongoing)\n
00103   *          b0     Tx state\n
00104   *             0  : Ready (no Tx operation ongoing)\n
00105   *             1  : Busy (Tx operation ongoing)
00106   * @{
00107   */
00108 typedef enum
00109 {
00110   HAL_I2C_STATE_RESET             = 0x00U,   /*!< Peripheral is not yet Initialized         */
00111   HAL_I2C_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use  */
00112   HAL_I2C_STATE_BUSY              = 0x24U,   /*!< An internal process is ongoing            */
00113   HAL_I2C_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing      */
00114   HAL_I2C_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing         */
00115   HAL_I2C_STATE_LISTEN            = 0x28U,   /*!< Address Listen Mode is ongoing            */
00116   HAL_I2C_STATE_BUSY_TX_LISTEN    = 0x29U,   /*!< Address Listen Mode and Data Transmission
00117                                                  process is ongoing                         */
00118   HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2AU,   /*!< Address Listen Mode and Data Reception
00119                                                  process is ongoing                         */
00120   HAL_I2C_STATE_ABORT             = 0x60U,   /*!< Abort user request ongoing                */
00121   HAL_I2C_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state                             */
00122   HAL_I2C_STATE_ERROR             = 0xE0U    /*!< Error                                     */
00123
00124 } HAL_I2C_StateTypeDef;
00125
00126 /**
00127   * @}
00128   */
00129
00130 /** @defgroup HAL_mode_structure_definition HAL mode structure definition
00131   * @brief  HAL Mode structure definition
00132   * @note  HAL I2C Mode value coding follow below described bitmap :\n
00133   *          b7     (not used)\n
00134   *             x  : Should be set to 0\n
00135   *          b6\n
00136   *             0  : None\n
00137   *             1  : Memory (HAL I2C communication is in Memory Mode)\n
00138   *          b5\n
00139   *             0  : None\n
00140   *             1  : Slave (HAL I2C communication is in Slave Mode)\n
00141   *          b4\n
00142   *             0  : None\n
00143   *             1  : Master (HAL I2C communication is in Master Mode)\n
00144   *          b3-b2-b1-b0  (not used)\n
00145   *             xxxx : Should be set to 0000
00146   * @{
00147   */
00148 typedef enum
00149 {
00150   HAL_I2C_MODE_NONE               = 0x00U,   /*!< No I2C communication on going             */
00151   HAL_I2C_MODE_MASTER             = 0x10U,   /*!< I2C communication is in Master Mode       */
00152   HAL_I2C_MODE_SLAVE              = 0x20U,   /*!< I2C communication is in Slave Mode        */
00153   HAL_I2C_MODE_MEM                = 0x40U    /*!< I2C communication is in Memory Mode       */
00154
00155 } HAL_I2C_ModeTypeDef;
00156
00157 /**
00158   * @}
00159   */
00160
00161 /** @defgroup I2C_Error_Code_definition I2C Error Code definition
00162   * @brief  I2C Error Code definition
00163   * @{
00164   */
00165 #define HAL_I2C_ERROR_NONE      (0x00000000U)    /*!< No error              */
00166 #define HAL_I2C_ERROR_BERR      (0x00000001U)    /*!< BERR error            */
00167 #define HAL_I2C_ERROR_ARLO      (0x00000002U)    /*!< ARLO error            */
00168 #define HAL_I2C_ERROR_AF        (0x00000004U)    /*!< ACKF error            */
00169 #define HAL_I2C_ERROR_OVR       (0x00000008U)    /*!< OVR error             */
00170 #define HAL_I2C_ERROR_DMA       (0x00000010U)    /*!< DMA transfer error    */
00171 #define HAL_I2C_ERROR_TIMEOUT   (0x00000020U)    /*!< Timeout error         */
00172 #define HAL_I2C_ERROR_SIZE      (0x00000040U)    /*!< Size Management error */
00173 #define HAL_I2C_ERROR_DMA_PARAM (0x00000080U)    /*!< DMA Parameter Error   */
00174 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
00175 #define HAL_I2C_ERROR_INVALID_CALLBACK  (0x00000100U)    /*!< Invalid Callback error */
00176 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
00177 #define HAL_I2C_ERROR_INVALID_PARAM     (0x00000200U)    /*!< Invalid Parameters error  */
00178 /**
00179   * @}
00180   */
00181
00182 /** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
00183   * @brief  I2C handle Structure definition
00184   * @{
00185   */
00186 typedef struct __I2C_HandleTypeDef
00187 {
00188   I2C_TypeDef                *Instance;      /*!< I2C registers base address                */
00189
00190   I2C_InitTypeDef            Init;           /*!< I2C communication parameters              */
00191
00192   uint8_t                    *pBuffPtr;      /*!< Pointer to I2C transfer buffer            */
00193
00194   uint16_t                   XferSize;       /*!< I2C transfer size                         */
00195
00196   __IO uint16_t              XferCount;      /*!< I2C transfer counter                      */
00197
00198   __IO uint32_t              XferOptions;    /*!< I2C sequantial transfer options, this parameter can
00199                                                   be a value of @ref I2C_XFEROPTIONS */
00200
00201   __IO uint32_t              PreviousState;  /*!< I2C communication Previous state          */
00202
00203   HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);  /*!< I2C transfer IRQ handler function pointer */
00204
00205   DMA_HandleTypeDef          *hdmatx;        /*!< I2C Tx DMA handle parameters              */
00206
00207   DMA_HandleTypeDef          *hdmarx;        /*!< I2C Rx DMA handle parameters              */
00208
00209   HAL_LockTypeDef            Lock;           /*!< I2C locking object                        */
00210
00211   __IO HAL_I2C_StateTypeDef  State;          /*!< I2C communication state                   */
00212
00213   __IO HAL_I2C_ModeTypeDef   Mode;           /*!< I2C communication mode                    */
00214
00215   __IO uint32_t              ErrorCode;      /*!< I2C Error code                            */
00216
00217   __IO uint32_t              AddrEventCount; /*!< I2C Address Event counter                 */
00218
00219 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
00220   void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);           /*!< I2C Master Tx Transfer completed callback */
00221   void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);           /*!< I2C Master Rx Transfer completed callback */
00222   void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);            /*!< I2C Slave Tx Transfer completed callback  */
00223   void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);            /*!< I2C Slave Rx Transfer completed callback  */
00224   void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);             /*!< I2C Listen Complete callback              */
00225   void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Memory Tx Transfer completed callback */
00226   void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Memory Rx Transfer completed callback */
00227   void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);                  /*!< I2C Error callback                        */
00228   void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Abort callback                        */
00229
00230   void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);  /*!< I2C Slave Address Match callback */
00231
00232   void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);                /*!< I2C Msp Init callback                     */
00233   void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Msp DeInit callback                   */
00234
00235 #endif  /* USE_HAL_I2C_REGISTER_CALLBACKS */
00236 } I2C_HandleTypeDef;
00237
00238 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
00239 /**
00240   * @brief  HAL I2C Callback ID enumeration definition
00241   */
00242 typedef enum
00243 {
00244   HAL_I2C_MASTER_TX_COMPLETE_CB_ID      = 0x00U,    /*!< I2C Master Tx Transfer completed callback ID  */
00245   HAL_I2C_MASTER_RX_COMPLETE_CB_ID      = 0x01U,    /*!< I2C Master Rx Transfer completed callback ID  */
00246   HAL_I2C_SLAVE_TX_COMPLETE_CB_ID       = 0x02U,    /*!< I2C Slave Tx Transfer completed callback ID   */
00247   HAL_I2C_SLAVE_RX_COMPLETE_CB_ID       = 0x03U,    /*!< I2C Slave Rx Transfer completed callback ID   */
00248   HAL_I2C_LISTEN_COMPLETE_CB_ID         = 0x04U,    /*!< I2C Listen Complete callback ID               */
00249   HAL_I2C_MEM_TX_COMPLETE_CB_ID         = 0x05U,    /*!< I2C Memory Tx Transfer callback ID            */
00250   HAL_I2C_MEM_RX_COMPLETE_CB_ID         = 0x06U,    /*!< I2C Memory Rx Transfer completed callback ID  */
00251   HAL_I2C_ERROR_CB_ID                   = 0x07U,    /*!< I2C Error callback ID                         */
00252   HAL_I2C_ABORT_CB_ID                   = 0x08U,    /*!< I2C Abort callback ID                         */
00253
00254   HAL_I2C_MSPINIT_CB_ID                 = 0x09U,    /*!< I2C Msp Init callback ID                      */
00255   HAL_I2C_MSPDEINIT_CB_ID               = 0x0AU     /*!< I2C Msp DeInit callback ID                    */
00256
00257 } HAL_I2C_CallbackIDTypeDef;
00258
00259 /**
00260   * @brief  HAL I2C Callback pointer definition
00261   */
00262 typedef  void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */
00263 typedef  void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */
00264
00265 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
00266 /**
00267   * @}
00268   */
00269
00270 /**
00271   * @}
00272   */
00273 /* Exported constants --------------------------------------------------------*/
00274
00275 /** @defgroup I2C_Exported_Constants I2C Exported Constants
00276   * @{
00277   */
00278
00279 /** @defgroup I2C_XFEROPTIONS  I2C Sequential Transfer Options
00280   * @{
00281   */
00282 #define I2C_FIRST_FRAME                 ((uint32_t)I2C_SOFTEND_MODE)
00283 #define I2C_FIRST_AND_NEXT_FRAME        ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
00284 #define I2C_NEXT_FRAME                  ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
00285 #define I2C_FIRST_AND_LAST_FRAME        ((uint32_t)I2C_AUTOEND_MODE)
00286 #define I2C_LAST_FRAME                  ((uint32_t)I2C_AUTOEND_MODE)
00287 #define I2C_LAST_FRAME_NO_STOP          ((uint32_t)I2C_SOFTEND_MODE)
00288
00289 /* List of XferOptions in usage of :
00290  * 1- Restart condition in all use cases (direction change or not)
00291  */
00292 #define  I2C_OTHER_FRAME                (0x000000AAU)
00293 #define  I2C_OTHER_AND_LAST_FRAME       (0x0000AA00U)
00294 /**
00295   * @}
00296   */
00297
00298 /** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
00299   * @{
00300   */
00301 #define I2C_ADDRESSINGMODE_7BIT         (0x00000001U)
00302 #define I2C_ADDRESSINGMODE_10BIT        (0x00000002U)
00303 /**
00304   * @}
00305   */
00306
00307 /** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
00308   * @{
00309   */
00310 #define I2C_DUALADDRESS_DISABLE         (0x00000000U)
00311 #define I2C_DUALADDRESS_ENABLE          I2C_OAR2_OA2EN
00312 /**
00313   * @}
00314   */
00315
00316 /** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
00317   * @{
00318   */
00319 #define I2C_OA2_NOMASK                  ((uint8_t)0x00U)
00320 #define I2C_OA2_MASK01                  ((uint8_t)0x01U)
00321 #define I2C_OA2_MASK02                  ((uint8_t)0x02U)
00322 #define I2C_OA2_MASK03                  ((uint8_t)0x03U)
00323 #define I2C_OA2_MASK04                  ((uint8_t)0x04U)
00324 #define I2C_OA2_MASK05                  ((uint8_t)0x05U)
00325 #define I2C_OA2_MASK06                  ((uint8_t)0x06U)
00326 #define I2C_OA2_MASK07                  ((uint8_t)0x07U)
00327 /**
00328   * @}
00329   */
00330
00331 /** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
00332   * @{
00333   */
00334 #define I2C_GENERALCALL_DISABLE         (0x00000000U)
00335 #define I2C_GENERALCALL_ENABLE          I2C_CR1_GCEN
00336 /**
00337   * @}
00338   */
00339
00340 /** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
00341   * @{
00342   */
00343 #define I2C_NOSTRETCH_DISABLE           (0x00000000U)
00344 #define I2C_NOSTRETCH_ENABLE            I2C_CR1_NOSTRETCH
00345 /**
00346   * @}
00347   */
00348
00349 /** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
00350   * @{
00351   */
00352 #define I2C_MEMADD_SIZE_8BIT            (0x00000001U)
00353 #define I2C_MEMADD_SIZE_16BIT           (0x00000002U)
00354 /**
00355   * @}
00356   */
00357
00358 /** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
00359   * @{
00360   */
00361 #define I2C_DIRECTION_TRANSMIT          (0x00000000U)
00362 #define I2C_DIRECTION_RECEIVE           (0x00000001U)
00363 /**
00364   * @}
00365   */
00366
00367 /** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
00368   * @{
00369   */
00370 #define  I2C_RELOAD_MODE                I2C_CR2_RELOAD
00371 #define  I2C_AUTOEND_MODE               I2C_CR2_AUTOEND
00372 #define  I2C_SOFTEND_MODE               (0x00000000U)
00373 /**
00374   * @}
00375   */
00376
00377 /** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
00378   * @{
00379   */
00380 #define  I2C_NO_STARTSTOP               (0x00000000U)
00381 #define  I2C_GENERATE_STOP              (uint32_t)(0x80000000U | I2C_CR2_STOP)
00382 #define  I2C_GENERATE_START_READ        (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
00383 #define  I2C_GENERATE_START_WRITE       (uint32_t)(0x80000000U | I2C_CR2_START)
00384 /**
00385   * @}
00386   */
00387
00388 /** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
00389   * @brief I2C Interrupt definition
00390   *        Elements values convention: 0xXXXXXXXX
00391   *           - XXXXXXXX  : Interrupt control mask
00392   * @{
00393   */
00394 #define I2C_IT_ERRI                     I2C_CR1_ERRIE
00395 #define I2C_IT_TCI                      I2C_CR1_TCIE
00396 #define I2C_IT_STOPI                    I2C_CR1_STOPIE
00397 #define I2C_IT_NACKI                    I2C_CR1_NACKIE
00398 #define I2C_IT_ADDRI                    I2C_CR1_ADDRIE
00399 #define I2C_IT_RXI                      I2C_CR1_RXIE
00400 #define I2C_IT_TXI                      I2C_CR1_TXIE
00401 /**
00402   * @}
00403   */
00404
00405 /** @defgroup I2C_Flag_definition I2C Flag definition
00406   * @{
00407   */
00408 #define I2C_FLAG_TXE                    I2C_ISR_TXE
00409 #define I2C_FLAG_TXIS                   I2C_ISR_TXIS
00410 #define I2C_FLAG_RXNE                   I2C_ISR_RXNE
00411 #define I2C_FLAG_ADDR                   I2C_ISR_ADDR
00412 #define I2C_FLAG_AF                     I2C_ISR_NACKF
00413 #define I2C_FLAG_STOPF                  I2C_ISR_STOPF
00414 #define I2C_FLAG_TC                     I2C_ISR_TC
00415 #define I2C_FLAG_TCR                    I2C_ISR_TCR
00416 #define I2C_FLAG_BERR                   I2C_ISR_BERR
00417 #define I2C_FLAG_ARLO                   I2C_ISR_ARLO
00418 #define I2C_FLAG_OVR                    I2C_ISR_OVR
00419 #define I2C_FLAG_PECERR                 I2C_ISR_PECERR
00420 #define I2C_FLAG_TIMEOUT                I2C_ISR_TIMEOUT
00421 #define I2C_FLAG_ALERT                  I2C_ISR_ALERT
00422 #define I2C_FLAG_BUSY                   I2C_ISR_BUSY
00423 #define I2C_FLAG_DIR                    I2C_ISR_DIR
00424 /**
00425   * @}
00426   */
00427
00428 /**
00429   * @}
00430   */
00431
00432 /* Exported macros -----------------------------------------------------------*/
00433
00434 /** @defgroup I2C_Exported_Macros I2C Exported Macros
00435   * @{
00436   */
00437
00438 /** @brief Reset I2C handle state.
00439   * @param  __HANDLE__ specifies the I2C Handle.
00440   * @retval None
00441   */
00442 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
00443 #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                do{                                                   \
00444                                                                     (__HANDLE__)->State = HAL_I2C_STATE_RESET;       \
00445                                                                     (__HANDLE__)->MspInitCallback = NULL;            \
00446                                                                     (__HANDLE__)->MspDeInitCallback = NULL;          \
00447                                                                   } while(0)
00448 #else
00449 #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
00450 #endif
00451
00452 /** @brief  Enable the specified I2C interrupt.
00453   * @param  __HANDLE__ specifies the I2C Handle.
00454   * @param  __INTERRUPT__ specifies the interrupt source to enable.
00455   *        This parameter can be one of the following values:
00456   *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
00457   *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
00458   *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
00459   *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
00460   *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
00461   *            @arg @ref I2C_IT_RXI   RX interrupt enable
00462   *            @arg @ref I2C_IT_TXI   TX interrupt enable
00463   *
00464   * @retval None
00465   */
00466 #define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
00467
00468 /** @brief  Disable the specified I2C interrupt.
00469   * @param  __HANDLE__ specifies the I2C Handle.
00470   * @param  __INTERRUPT__ specifies the interrupt source to disable.
00471   *        This parameter can be one of the following values:
00472   *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
00473   *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
00474   *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
00475   *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
00476   *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
00477   *            @arg @ref I2C_IT_RXI   RX interrupt enable
00478   *            @arg @ref I2C_IT_TXI   TX interrupt enable
00479   *
00480   * @retval None
00481   */
00482 #define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
00483
00484 /** @brief  Check whether the specified I2C interrupt source is enabled or not.
00485   * @param  __HANDLE__ specifies the I2C Handle.
00486   * @param  __INTERRUPT__ specifies the I2C interrupt source to check.
00487   *          This parameter can be one of the following values:
00488   *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
00489   *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
00490   *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
00491   *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
00492   *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
00493   *            @arg @ref I2C_IT_RXI   RX interrupt enable
00494   *            @arg @ref I2C_IT_TXI   TX interrupt enable
00495   *
00496   * @retval The new state of __INTERRUPT__ (SET or RESET).
00497   */
00498 #define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00499
00500 /** @brief  Check whether the specified I2C flag is set or not.
00501   * @param  __HANDLE__ specifies the I2C Handle.
00502   * @param  __FLAG__ specifies the flag to check.
00503   *        This parameter can be one of the following values:
00504   *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
00505   *            @arg @ref I2C_FLAG_TXIS    Transmit interrupt status
00506   *            @arg @ref I2C_FLAG_RXNE    Receive data register not empty
00507   *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
00508   *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
00509   *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
00510   *            @arg @ref I2C_FLAG_TC      Transfer complete (master mode)
00511   *            @arg @ref I2C_FLAG_TCR     Transfer complete reload
00512   *            @arg @ref I2C_FLAG_BERR    Bus error
00513   *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
00514   *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
00515   *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
00516   *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
00517   *            @arg @ref I2C_FLAG_ALERT   SMBus alert
00518   *            @arg @ref I2C_FLAG_BUSY    Bus busy
00519   *            @arg @ref I2C_FLAG_DIR     Transfer direction (slave mode)
00520   *
00521   * @retval The new state of __FLAG__ (SET or RESET).
00522   */
00523 #define I2C_FLAG_MASK  (0x0001FFFFU)
00524 #define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
00525
00526 /** @brief  Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
00527   * @param  __HANDLE__ specifies the I2C Handle.
00528   * @param  __FLAG__ specifies the flag to clear.
00529   *          This parameter can be any combination of the following values:
00530   *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
00531   *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
00532   *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
00533   *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
00534   *            @arg @ref I2C_FLAG_BERR    Bus error
00535   *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
00536   *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
00537   *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
00538   *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
00539   *            @arg @ref I2C_FLAG_ALERT   SMBus alert
00540   *
00541   * @retval None
00542   */
00543 #define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
00544                                                                                  : ((__HANDLE__)->Instance->ICR = (__FLAG__)))
00545
00546 /** @brief  Enable the specified I2C peripheral.
00547   * @param  __HANDLE__ specifies the I2C Handle.
00548   * @retval None
00549   */
00550 #define __HAL_I2C_ENABLE(__HANDLE__)                            (SET_BIT((__HANDLE__)->Instance->CR1,  I2C_CR1_PE))
00551
00552 /** @brief  Disable the specified I2C peripheral.
00553   * @param  __HANDLE__ specifies the I2C Handle.
00554   * @retval None
00555   */
00556 #define __HAL_I2C_DISABLE(__HANDLE__)                           (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
00557
00558 /** @brief  Generate a Non-Acknowledge I2C peripheral in Slave mode.
00559   * @param  __HANDLE__ specifies the I2C Handle.
00560   * @retval None
00561   */
00562 #define __HAL_I2C_GENERATE_NACK(__HANDLE__)                     (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
00563 /**
00564   * @}
00565   */
00566
00567 /* Include I2C HAL Extended module */
00568 #include "stm32wbxx_hal_i2c_ex.h"
00569
00570 /* Exported functions --------------------------------------------------------*/
00571 /** @addtogroup I2C_Exported_Functions
00572   * @{
00573   */
00574
00575 /** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
00576   * @{
00577   */
00578 /* Initialization and de-initialization functions******************************/
00579 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
00580 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
00581 void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
00582 void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
00583
00584 /* Callbacks Register/UnRegister functions  ***********************************/
00585 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
00586 HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback);
00587 HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
00588
00589 HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
00590 HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
00591 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
00592 /**
00593   * @}
00594   */
00595
00596 /** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
00597   * @{
00598   */
00599 /* IO operation functions  ****************************************************/
00600 /******* Blocking mode: Polling */
00601 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00602 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00603 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00604 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00605 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00606 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00607 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
00608
00609 /******* Non-Blocking mode: Interrupt */
00610 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
00611 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
00612 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00613 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00614 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00615 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00616
00617 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00618 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00619 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00620 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00621 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
00622 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
00623 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
00624
00625 /******* Non-Blocking mode: DMA */
00626 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
00627 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
00628 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00629 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00630 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00631 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00632
00633 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00634 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00635 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00636 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00637 /**
00638   * @}
00639   */
00640
00641 /** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
00642  * @{
00643  */
00644 /******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
00645 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
00646 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
00647 void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
00648 void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
00649 void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
00650 void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
00651 void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
00652 void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
00653 void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
00654 void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
00655 void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
00656 void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
00657 /**
00658   * @}
00659   */
00660
00661 /** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
00662   * @{
00663   */
00664 /* Peripheral State, Mode and Error functions  *********************************/
00665 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
00666 HAL_I2C_ModeTypeDef  HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
00667 uint32_t             HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
00668
00669 /**
00670   * @}
00671   */
00672
00673 /**
00674   * @}
00675   */
00676
00677 /* Private constants ---------------------------------------------------------*/
00678 /** @defgroup I2C_Private_Constants I2C Private Constants
00679   * @{
00680   */
00681
00682 /**
00683   * @}
00684   */
00685
00686 /* Private macros ------------------------------------------------------------*/
00687 /** @defgroup I2C_Private_Macro I2C Private Macros
00688   * @{
00689   */
00690
00691 #define IS_I2C_ADDRESSING_MODE(MODE)    (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
00692                                          ((MODE) == I2C_ADDRESSINGMODE_10BIT))
00693
00694 #define IS_I2C_DUAL_ADDRESS(ADDRESS)    (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
00695                                          ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
00696
00697 #define IS_I2C_OWN_ADDRESS2_MASK(MASK)  (((MASK) == I2C_OA2_NOMASK)  || \
00698                                          ((MASK) == I2C_OA2_MASK01) || \
00699                                          ((MASK) == I2C_OA2_MASK02) || \
00700                                          ((MASK) == I2C_OA2_MASK03) || \
00701                                          ((MASK) == I2C_OA2_MASK04) || \
00702                                          ((MASK) == I2C_OA2_MASK05) || \
00703                                          ((MASK) == I2C_OA2_MASK06) || \
00704                                          ((MASK) == I2C_OA2_MASK07))
00705
00706 #define IS_I2C_GENERAL_CALL(CALL)       (((CALL) == I2C_GENERALCALL_DISABLE) || \
00707                                          ((CALL) == I2C_GENERALCALL_ENABLE))
00708
00709 #define IS_I2C_NO_STRETCH(STRETCH)      (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
00710                                          ((STRETCH) == I2C_NOSTRETCH_ENABLE))
00711
00712 #define IS_I2C_MEMADD_SIZE(SIZE)        (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
00713                                          ((SIZE) == I2C_MEMADD_SIZE_16BIT))
00714
00715 #define IS_TRANSFER_MODE(MODE)          (((MODE) == I2C_RELOAD_MODE)   || \
00716                                          ((MODE) == I2C_AUTOEND_MODE) || \
00717                                          ((MODE) == I2C_SOFTEND_MODE))
00718
00719 #define IS_TRANSFER_REQUEST(REQUEST)    (((REQUEST) == I2C_GENERATE_STOP)        || \
00720                                          ((REQUEST) == I2C_GENERATE_START_READ)  || \
00721                                          ((REQUEST) == I2C_GENERATE_START_WRITE) || \
00722                                          ((REQUEST) == I2C_NO_STARTSTOP))
00723
00724 #define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)  (((REQUEST) == I2C_FIRST_FRAME)          || \
00725                                                    ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
00726                                                    ((REQUEST) == I2C_NEXT_FRAME)           || \
00727                                                    ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
00728                                                    ((REQUEST) == I2C_LAST_FRAME)           || \
00729                                                    ((REQUEST) == I2C_LAST_FRAME_NO_STOP)   || \
00730                                                    IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
00731
00732 #define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME)     || \
00733                                                         ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
00734
00735 #define I2C_RESET_CR2(__HANDLE__)                 ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
00736
00737 #define I2C_GET_ADDR_MATCH(__HANDLE__)            ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U))
00738 #define I2C_GET_DIR(__HANDLE__)                   ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U))
00739 #define I2C_GET_STOP_MODE(__HANDLE__)             ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
00740 #define I2C_GET_OWN_ADDRESS1(__HANDLE__)          ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
00741 #define I2C_GET_OWN_ADDRESS2(__HANDLE__)          ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
00742
00743 #define IS_I2C_OWN_ADDRESS1(ADDRESS1)             ((ADDRESS1) <= 0x000003FFU)
00744 #define IS_I2C_OWN_ADDRESS2(ADDRESS2)             ((ADDRESS2) <= (uint16_t)0x00FFU)
00745
00746 #define I2C_MEM_ADD_MSB(__ADDRESS__)              ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
00747 #define I2C_MEM_ADD_LSB(__ADDRESS__)              ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
00748
00749 #define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
00750                                                           (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
00751
00752 #define I2C_CHECK_FLAG(__ISR__, __FLAG__)         ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
00753 #define I2C_CHECK_IT_SOURCE(__CR1__, __IT__)      ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
00754 /**
00755   * @}
00756   */
00757
00758 /* Private Functions ---------------------------------------------------------*/
00759 /** @defgroup I2C_Private_Functions I2C Private Functions
00760   * @{
00761   */
00762 /* Private functions are defined in stm32wbxx_hal_i2c.c file */
00763 /**
00764   * @}
00765   */
00766
00767 /**
00768   * @}
00769   */
00770
00771 /**
00772   * @}
00773   */
00774
00775 #ifdef __cplusplus
00776 }
00777 #endif
00778
00779
00780 #endif /* STM32WBxx_HAL_I2C_H */
00781
00782 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_i2c_ex.c Source File

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stm32wbxx_hal_i2c_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_i2c_ex.c
00004   * @author  MCD Application Team
00005   * @brief   I2C Extended HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of I2C Extended peripheral:
00008   *           + Extended features functions
00009   *
00010   @verbatim
00011   ==============================================================================
00012                ##### I2C peripheral Extended features  #####
00013   ==============================================================================
00014
00015   [..] Comparing to other previous devices, the I2C interface for STM32WBxx
00016        devices contains the following additional features
00017
00018        (+) Possibility to disable or enable Analog Noise Filter
00019        (+) Use of a configured Digital Noise Filter
00020        (+) Disable or enable wakeup from Stop mode(s)
00021        (+) Disable or enable Fast Mode Plus
00022
00023                      ##### How to use this driver #####
00024   ==============================================================================
00025   [..] This driver provides functions to configure Noise Filter and Wake Up Feature
00026     (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
00027     (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
00028     (#) Configure the enable or disable of I2C Wake Up Mode using the functions :
00029           (++) HAL_I2CEx_EnableWakeUp()
00030           (++) HAL_I2CEx_DisableWakeUp()
00031     (#) Configure the enable or disable of fast mode plus driving capability using the functions :
00032           (++) HAL_I2CEx_EnableFastModePlus()
00033           (++) HAL_I2CEx_DisableFastModePlus()
00034   @endverbatim
00035   ******************************************************************************
00036   * @attention
00037   *
00038   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00039   * All rights reserved.</center></h2>
00040   *
00041   * This software component is licensed by ST under BSD 3-Clause license,
00042   * the "License"; You may not use this file except in compliance with the
00043   * License. You may obtain a copy of the License at:
00044   *                        opensource.org/licenses/BSD-3-Clause
00045   *
00046   ******************************************************************************
00047   */
00048
00049 /* Includes ------------------------------------------------------------------*/
00050 #include "stm32wbxx_hal.h"
00051
00052 /** @addtogroup STM32WBxx_HAL_Driver
00053   * @{
00054   */
00055
00056 /** @defgroup I2CEx I2CEx
00057   * @brief I2C Extended HAL module driver
00058   * @{
00059   */
00060
00061 #ifdef HAL_I2C_MODULE_ENABLED
00062
00063 /* Private typedef -----------------------------------------------------------*/
00064 /* Private define ------------------------------------------------------------*/
00065 /* Private macro -------------------------------------------------------------*/
00066 /* Private variables ---------------------------------------------------------*/
00067 /* Private function prototypes -----------------------------------------------*/
00068 /* Private functions ---------------------------------------------------------*/
00069
00070 /** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
00071   * @{
00072   */
00073
00074 /** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions
00075   * @brief    Extended features functions
00076  *
00077 @verbatim
00078  ===============================================================================
00079                       ##### Extended features functions #####
00080  ===============================================================================
00081     [..] This section provides functions allowing to:
00082       (+) Configure Noise Filters
00083       (+) Configure Wake Up Feature
00084       (+) Configure Fast Mode Plus
00085
00086 @endverbatim
00087   * @{
00088   */
00089
00090 /**
00091   * @brief  Configure I2C Analog noise filter.
00092   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00093   *                the configuration information for the specified I2Cx peripheral.
00094   * @param  AnalogFilter New state of the Analog filter.
00095   * @retval HAL status
00096   */
00097 HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
00098 {
00099   /* Check the parameters */
00100   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00101   assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
00102
00103   if (hi2c->State == HAL_I2C_STATE_READY)
00104   {
00105     /* Process Locked */
00106     __HAL_LOCK(hi2c);
00107
00108     hi2c->State = HAL_I2C_STATE_BUSY;
00109
00110     /* Disable the selected I2C peripheral */
00111     __HAL_I2C_DISABLE(hi2c);
00112
00113     /* Reset I2Cx ANOFF bit */
00114     hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
00115
00116     /* Set analog filter bit*/
00117     hi2c->Instance->CR1 |= AnalogFilter;
00118
00119     __HAL_I2C_ENABLE(hi2c);
00120
00121     hi2c->State = HAL_I2C_STATE_READY;
00122
00123     /* Process Unlocked */
00124     __HAL_UNLOCK(hi2c);
00125
00126     return HAL_OK;
00127   }
00128   else
00129   {
00130     return HAL_BUSY;
00131   }
00132 }
00133
00134 /**
00135   * @brief  Configure I2C Digital noise filter.
00136   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00137   *                the configuration information for the specified I2Cx peripheral.
00138   * @param  DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
00139   * @retval HAL status
00140   */
00141 HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
00142 {
00143   uint32_t tmpreg;
00144
00145   /* Check the parameters */
00146   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00147   assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
00148
00149   if (hi2c->State == HAL_I2C_STATE_READY)
00150   {
00151     /* Process Locked */
00152     __HAL_LOCK(hi2c);
00153
00154     hi2c->State = HAL_I2C_STATE_BUSY;
00155
00156     /* Disable the selected I2C peripheral */
00157     __HAL_I2C_DISABLE(hi2c);
00158
00159     /* Get the old register value */
00160     tmpreg = hi2c->Instance->CR1;
00161
00162     /* Reset I2Cx DNF bits [11:8] */
00163     tmpreg &= ~(I2C_CR1_DNF);
00164
00165     /* Set I2Cx DNF coefficient */
00166     tmpreg |= DigitalFilter << 8U;
00167
00168     /* Store the new register value */
00169     hi2c->Instance->CR1 = tmpreg;
00170
00171     __HAL_I2C_ENABLE(hi2c);
00172
00173     hi2c->State = HAL_I2C_STATE_READY;
00174
00175     /* Process Unlocked */
00176     __HAL_UNLOCK(hi2c);
00177
00178     return HAL_OK;
00179   }
00180   else
00181   {
00182     return HAL_BUSY;
00183   }
00184 }
00185
00186 /**
00187   * @brief  Enable I2C wakeup from Stop mode(s).
00188   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00189   *                the configuration information for the specified I2Cx peripheral.
00190   * @retval HAL status
00191   */
00192 HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)
00193 {
00194   /* Check the parameters */
00195   assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
00196
00197   if (hi2c->State == HAL_I2C_STATE_READY)
00198   {
00199     /* Process Locked */
00200     __HAL_LOCK(hi2c);
00201
00202     hi2c->State = HAL_I2C_STATE_BUSY;
00203
00204     /* Disable the selected I2C peripheral */
00205     __HAL_I2C_DISABLE(hi2c);
00206
00207     /* Enable wakeup from stop mode */
00208     hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
00209
00210     __HAL_I2C_ENABLE(hi2c);
00211
00212     hi2c->State = HAL_I2C_STATE_READY;
00213
00214     /* Process Unlocked */
00215     __HAL_UNLOCK(hi2c);
00216
00217     return HAL_OK;
00218   }
00219   else
00220   {
00221     return HAL_BUSY;
00222   }
00223 }
00224
00225 /**
00226   * @brief  Disable I2C wakeup from Stop mode(s).
00227   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00228   *                the configuration information for the specified I2Cx peripheral.
00229   * @retval HAL status
00230   */
00231 HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
00232 {
00233   /* Check the parameters */
00234   assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
00235
00236   if (hi2c->State == HAL_I2C_STATE_READY)
00237   {
00238     /* Process Locked */
00239     __HAL_LOCK(hi2c);
00240
00241     hi2c->State = HAL_I2C_STATE_BUSY;
00242
00243     /* Disable the selected I2C peripheral */
00244     __HAL_I2C_DISABLE(hi2c);
00245
00246     /* Enable wakeup from stop mode */
00247     hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
00248
00249     __HAL_I2C_ENABLE(hi2c);
00250
00251     hi2c->State = HAL_I2C_STATE_READY;
00252
00253     /* Process Unlocked */
00254     __HAL_UNLOCK(hi2c);
00255
00256     return HAL_OK;
00257   }
00258   else
00259   {
00260     return HAL_BUSY;
00261   }
00262 }
00263
00264 /**
00265   * @brief Enable the I2C fast mode plus driving capability.
00266   * @param ConfigFastModePlus Selects the pin.
00267   *   This parameter can be one of the @ref I2CEx_FastModePlus values
00268   * @note  For I2C1, fast mode plus driving capability can be enabled on all selected
00269   *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
00270   *        on each one of the following pins PB6, PB7, PB8 and PB9.
00271   * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
00272   *        can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
00273   * @note  For all I2C3 pins fast mode plus driving capability can be enabled
00274   *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
00275   * @retval None
00276   */
00277 void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
00278 {
00279   /* Check the parameter */
00280   assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
00281
00282   /* Enable fast mode plus driving capability for selected pin */
00283   SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
00284 }
00285
00286 /**
00287   * @brief Disable the I2C fast mode plus driving capability.
00288   * @param ConfigFastModePlus Selects the pin.
00289   *   This parameter can be one of the @ref I2CEx_FastModePlus values
00290   * @note  For I2C1, fast mode plus driving capability can be disabled on all selected
00291   *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
00292   *        on each one of the following pins PB6, PB7, PB8 and PB9.
00293   * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
00294   *        can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
00295   * @note  For all I2C3 pins fast mode plus driving capability can be disabled
00296   *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
00297   * @retval None
00298   */
00299 void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
00300 {
00301   /* Check the parameter */
00302   assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
00303
00304   /* Disable fast mode plus driving capability for selected pin */
00305   CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
00306 }
00307
00308 /**
00309   * @}
00310   */
00311
00312 /**
00313   * @}
00314   */
00315
00316 #endif /* HAL_I2C_MODULE_ENABLED */
00317 /**
00318   * @}
00319   */
00320
00321 /**
00322   * @}
00323   */
00324
00325 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_i2c_ex.h Source File

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stm32wbxx_hal_i2c_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_i2c_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of I2C HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_I2C_EX_H
00022 #define STM32WBxx_HAL_I2C_EX_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 /** @addtogroup STM32WBxx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup I2CEx
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /* Exported constants --------------------------------------------------------*/
00041
00042 /** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
00043   * @{
00044   */
00045
00046 /** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
00047   * @{
00048   */
00049 #define I2C_ANALOGFILTER_ENABLE         0x00000000U
00050 #define I2C_ANALOGFILTER_DISABLE        I2C_CR1_ANFOFF
00051 /**
00052   * @}
00053   */
00054
00055 /** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
00056   * @{
00057   */
00058 #define I2C_FMP_NOT_SUPPORTED           0xAAAA0000U                                     /*!< Fast Mode Plus not supported       */
00059 #define I2C_FASTMODEPLUS_PB6            SYSCFG_CFGR1_I2C_PB6_FMP                        /*!< Enable Fast Mode Plus on PB6       */
00060 #define I2C_FASTMODEPLUS_PB7            SYSCFG_CFGR1_I2C_PB7_FMP                        /*!< Enable Fast Mode Plus on PB7       */
00061 #define I2C_FASTMODEPLUS_PB8            SYSCFG_CFGR1_I2C_PB8_FMP                        /*!< Enable Fast Mode Plus on PB8       */
00062 #define I2C_FASTMODEPLUS_PB9            SYSCFG_CFGR1_I2C_PB9_FMP                        /*!< Enable Fast Mode Plus on PB9       */
00063 #define I2C_FASTMODEPLUS_I2C1           SYSCFG_CFGR1_I2C1_FMP                           /*!< Enable Fast Mode Plus on I2C1 pins */
00064 #if defined(SYSCFG_CFGR1_I2C3_FMP)
00065 #define I2C_FASTMODEPLUS_I2C3           SYSCFG_CFGR1_I2C3_FMP                           /*!< Enable Fast Mode Plus on I2C3 pins */
00066 #else
00067 #define I2C_FASTMODEPLUS_I2C3           (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported  */
00068 #endif
00069 /**
00070   * @}
00071   */
00072
00073 /**
00074   * @}
00075   */
00076
00077 /* Exported macro ------------------------------------------------------------*/
00078 /* Exported functions --------------------------------------------------------*/
00079
00080 /** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
00081   * @{
00082   */
00083
00084 /** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions
00085   * @brief    Extended features functions
00086   * @{
00087   */
00088
00089 /* Peripheral Control functions  ************************************************/
00090 HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
00091 HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
00092 HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
00093 HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
00094 void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
00095 void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
00096
00097 /* Private constants ---------------------------------------------------------*/
00098 /** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
00099   * @{
00100   */
00101
00102 /**
00103   * @}
00104   */
00105
00106 /* Private macros ------------------------------------------------------------*/
00107 /** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
00108   * @{
00109   */
00110 #define IS_I2C_ANALOG_FILTER(FILTER)    (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
00111                                           ((FILTER) == I2C_ANALOGFILTER_DISABLE))
00112
00113 #define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000FU)
00114
00115 #define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6))  == I2C_FASTMODEPLUS_PB6)     || \
00116                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7))  == I2C_FASTMODEPLUS_PB7)     || \
00117                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8))  == I2C_FASTMODEPLUS_PB8)     || \
00118                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9))  == I2C_FASTMODEPLUS_PB9)     || \
00119                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1)    || \
00120                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3))
00121 /**
00122   * @}
00123   */
00124
00125 /* Private Functions ---------------------------------------------------------*/
00126 /** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
00127   * @{
00128   */
00129 /* Private functions are defined in stm32wbxx_hal_i2c_ex.c file */
00130 /**
00131   * @}
00132   */
00133
00134 /**
00135   * @}
00136   */
00137
00138 /**
00139   * @}
00140   */
00141
00142 /**
00143   * @}
00144   */
00145
00146 /**
00147   * @}
00148   */
00149
00150 #ifdef __cplusplus
00151 }
00152 #endif
00153
00154 #endif /* STM32WBxx_HAL_I2C_EX_H */
00155
00156 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_ipcc.c Source File

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stm32wbxx_hal_ipcc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_ipcc.c
00004   * @author  MCD Application Team
00005   * @brief   IPCC HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Inter-Processor communication controller
00008   *          peripherals (IPCC).
00009   *           + Initialization and de-initialization functions
00010   *           + Configuration, notification and interrupts handling
00011   *           + Peripheral State and Error functions
00012   @verbatim
00013   ==============================================================================
00014                         ##### How to use this driver #####
00015   ==============================================================================
00016     [..]
00017       The IPCC HAL driver can be used as follows:
00018
00019       (#) Declare a IPCC_HandleTypeDef handle structure, for example: IPCC_HandleTypeDef hipcc;
00020       (#) Initialize the IPCC low level resources by implementing the HAL_IPCC_MspInit() API:
00021         (##) Enable the IPCC interface clock
00022         (##) NVIC configuration if you need to use interrupt process
00023             (+++) Configure the IPCC interrupt priority
00024             (+++) Enable the NVIC IPCC IRQ
00025
00026       (#) Initialize the IPCC registers by calling the HAL_IPCC_Init() API which trig
00027           HAL_IPCC_MspInit().
00028
00029       (#) Implement the interrupt callbacks for transmission and reception to use the driver in interrupt mode
00030
00031       (#) Associate those callback to the corresponding channel and direction using HAL_IPCC_ConfigChannel().
00032           This is the interrupt mode.
00033           If no callback are configured for a given channel and direction, it is up to the user to poll the
00034           status of the communication (polling mode).
00035
00036       (#) Notify the other MCU when a message is available in a chosen channel
00037           or when a message has been retrieved from a chosen channel by calling
00038           the HAL_IPCC_NotifyCPU() API.
00039
00040 @endverbatim
00041   ******************************************************************************
00042   * @attention
00043   *
00044   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00045   * All rights reserved.</center></h2>
00046   *
00047   * This software component is licensed by ST under BSD 3-Clause license,
00048   * the "License"; You may not use this file except in compliance with the
00049   * License. You may obtain a copy of the License at:
00050   *                        opensource.org/licenses/BSD-3-Clause
00051   *
00052   ******************************************************************************
00053   */
00054
00055 /* Includes ------------------------------------------------------------------*/
00056 #include "stm32wbxx_hal.h"
00057
00058 /** @addtogroup STM32WBxx_HAL_Driver
00059   * @{
00060   */
00061
00062 /** @addtogroup IPCC
00063   * @{
00064   */
00065
00066 #ifdef HAL_IPCC_MODULE_ENABLED
00067
00068 /* Private typedef -----------------------------------------------------------*/
00069 /* Private define ------------------------------------------------------------*/
00070 /** @defgroup IPCC_Private_Constants IPCC Private Constants
00071   * @{
00072   */
00073 #define IPCC_ALL_RX_BUF 0x0000003FU /*!< Mask for all RX buffers. */
00074 #define IPCC_ALL_TX_BUF 0x003F0000U /*!< Mask for all TX buffers. */
00075 #define CHANNEL_INDEX_Msk 0x0000000FU /*!< Mask the channel index to avoid overflow */
00076 /**
00077   * @}
00078   */
00079
00080 /* Private macros ------------------------------------------------------------*/
00081 /* Private variables ---------------------------------------------------------*/
00082 /* Private function prototypes -----------------------------------------------*/
00083 /** @defgroup IPCC_Private_Functions IPCC Private Functions
00084   * @{
00085   */
00086 void IPCC_MaskInterrupt(uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
00087 void IPCC_UnmaskInterrupt(uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
00088 void IPCC_SetDefaultCallbacks(IPCC_HandleTypeDef *hipcc);
00089 void IPCC_Reset_Register(IPCC_CommonTypeDef *Instance);
00090 /**
00091   * @}
00092   */
00093
00094 /** @addtogroup IPCC_Exported_Functions
00095   * @{
00096   */
00097
00098 /** @addtogroup IPCC_Exported_Functions_Group1
00099  *  @brief    Initialization and de-initialization functions
00100  *
00101 @verbatim
00102  ===============================================================================
00103              ##### Initialization and de-initialization functions  #####
00104  ===============================================================================
00105     [..]  This subsection provides a set of functions allowing to initialize and
00106           deinitialize the IPCC peripheral:
00107
00108       (+) User must Implement HAL_IPCC_MspInit() function in which he configures
00109           all related peripherals resources (CLOCK and NVIC ).
00110
00111       (+) Call the function HAL_IPCC_Init() to configure the IPCC register.
00112
00113       (+) Call the function HAL_PKA_DeInit() to restore the default configuration
00114           of the selected IPCC peripheral.
00115
00116 @endverbatim
00117   * @{
00118   */
00119
00120 /**
00121   * @brief  Initialize the IPCC peripheral.
00122   * @param  hipcc IPCC handle
00123   * @retval HAL status
00124   */
00125 HAL_StatusTypeDef HAL_IPCC_Init(IPCC_HandleTypeDef *hipcc)
00126 {
00127   HAL_StatusTypeDef err = HAL_OK;
00128
00129   /* Check the IPCC handle allocation */
00130   if (hipcc != NULL)
00131   {
00132     /* Check the parameters */
00133     assert_param(IS_IPCC_ALL_INSTANCE(hipcc->Instance));
00134
00135     IPCC_CommonTypeDef *currentInstance = IPCC_C1;
00136
00137     if (hipcc->State == HAL_IPCC_STATE_RESET)
00138     {
00139       /* Init the low level hardware : CLOCK, NVIC */
00140       HAL_IPCC_MspInit(hipcc);
00141     }
00142
00143     /* Reset all registers of the current cpu to default state */
00144     IPCC_Reset_Register(currentInstance);
00145
00146     /* Activate the interrupts */
00147     currentInstance->CR |= (IPCC_CR_RXOIE | IPCC_CR_TXFIE);
00148
00149     /* Clear callback pointers */
00150     IPCC_SetDefaultCallbacks(hipcc);
00151
00152     /* Reset all callback notification request */
00153     hipcc->callbackRequest = 0;
00154
00155     hipcc->State = HAL_IPCC_STATE_READY;
00156   }
00157   else
00158   {
00159     err = HAL_ERROR;
00160   }
00161
00162   return err;
00163 }
00164
00165 /**
00166   * @brief  DeInitialize the IPCC peripheral.
00167   * @param  hipcc IPCC handle
00168   * @retval HAL status
00169   */
00170 HAL_StatusTypeDef HAL_IPCC_DeInit(IPCC_HandleTypeDef *hipcc)
00171 {
00172   HAL_StatusTypeDef err = HAL_OK;
00173
00174   /* Check the IPCC handle allocation */
00175   if (hipcc != NULL)
00176   {
00177     assert_param(IS_IPCC_ALL_INSTANCE(hipcc->Instance));
00178     IPCC_CommonTypeDef *currentInstance = IPCC_C1;
00179
00180     /* Set the state to busy */
00181     hipcc->State = HAL_IPCC_STATE_BUSY;
00182
00183     /* Reset all registers of the current cpu to default state */
00184     IPCC_Reset_Register(currentInstance);
00185
00186     /* Clear callback pointers */
00187     IPCC_SetDefaultCallbacks(hipcc);
00188
00189     /* Reset all callback notification request */
00190     hipcc->callbackRequest = 0;
00191
00192     /* DeInit the low level hardware : CLOCK, NVIC */
00193     HAL_IPCC_MspDeInit(hipcc);
00194
00195     hipcc->State = HAL_IPCC_STATE_RESET;
00196   }
00197   else
00198   {
00199     err = HAL_ERROR;
00200   }
00201
00202   return err;
00203 }
00204
00205 /**
00206   * @brief Initialize the IPCC MSP.
00207   * @param  hipcc IPCC handle
00208   * @retval None
00209   */
00210 __weak void HAL_IPCC_MspInit(IPCC_HandleTypeDef *hipcc)
00211 {
00212   /* Prevent unused argument(s) compilation warning */
00213   UNUSED(hipcc);
00214
00215   /* NOTE : This function should not be modified. When the callback is needed
00216             the HAL_IPCC_MspInit should be implemented in the user file
00217    */
00218 }
00219
00220 /**
00221   * @brief IPCC MSP DeInit
00222   * @param  hipcc IPCC handle
00223   * @retval None
00224   */
00225 __weak void HAL_IPCC_MspDeInit(IPCC_HandleTypeDef *hipcc)
00226 {
00227   /* Prevent unused argument(s) compilation warning */
00228   UNUSED(hipcc);
00229
00230   /* NOTE : This function should not be modified. When the callback is needed
00231             the HAL_IPCC_MspDeInit should be implemented in the user file
00232    */
00233 }
00234
00235 /**
00236   * @}
00237   */
00238
00239
00240 /** @addtogroup IPCC_Exported_Functions_Group2
00241  *  @brief    Configuration, notification and Irq handling functions.
00242  *
00243 @verbatim
00244  ===============================================================================
00245               ##### IO operation functions #####
00246  ===============================================================================
00247     [..]  This section provides functions to allow two MCU to communicate.
00248
00249     (#) For a given channel (from 0 to IPCC_CHANNEL_NUMBER), for a given direction
00250         IPCC_CHANNEL_DIR_TX or IPCC_CHANNEL_DIR_RX, you can choose to communicate
00251         in polling mode or in interrupt mode using IPCC.
00252         By default, the IPCC HAL driver handle the communication in polling mode.
00253         By setting a callback for a channel/direction, this communication use
00254         the interrupt mode.
00255
00256     (#) Polling mode:
00257        (++) To transmit information, use HAL_IPCC_NotifyCPU() with
00258             IPCC_CHANNEL_DIR_TX. To know when the other processor has handled
00259             the notification, poll the communication using HAL_IPCC_NotifyCPU
00260             with IPCC_CHANNEL_DIR_TX.
00261
00262        (++) To receive information, poll the status of the communication with
00263             HAL_IPCC_GetChannelStatus with IPCC_CHANNEL_DIR_RX. To notify the other
00264             processor that the information has been received, use HAL_IPCC_NotifyCPU
00265             with IPCC_CHANNEL_DIR_RX.
00266
00267     (#) Interrupt mode:
00268        (++) Configure a callback for the channel and the direction using HAL_IPCC_ConfigChannel().
00269             This callback will be triggered under interrupt.
00270
00271        (++) To transmit information, use HAL_IPCC_NotifyCPU() with
00272             IPCC_CHANNEL_DIR_TX. The callback configured with HAL_IPCC_ConfigChannel() and
00273             IPCC_CHANNEL_DIR_TX will be triggered once the communication has been handled by the
00274             other processor.
00275
00276        (++) To receive information, the callback configured with HAL_IPCC_ConfigChannel() and
00277             IPCC_CHANNEL_DIR_RX will be triggered on reception of a communication.To notify the other
00278             processor that the information has been received, use HAL_IPCC_NotifyCPU
00279             with IPCC_CHANNEL_DIR_RX.
00280
00281        (++) HAL_IPCC_TX_IRQHandler must be added to the IPCC TX IRQHandler
00282
00283        (++) HAL_IPCC_RX_IRQHandler must be added to the IPCC RX IRQHandler
00284 @endverbatim
00285   * @{
00286   */
00287
00288 /**
00289   * @brief  Activate the callback notification on receive/transmit interrupt
00290   * @param  hipcc IPCC handle
00291   * @param  ChannelIndex Channel number
00292   *          This parameter can be one of the following values:
00293   *            @arg IPCC_CHANNEL_1: IPCC Channel 1
00294   *            @arg IPCC_CHANNEL_2: IPCC Channel 2
00295   *            @arg IPCC_CHANNEL_3: IPCC Channel 3
00296   *            @arg IPCC_CHANNEL_4: IPCC Channel 4
00297   *            @arg IPCC_CHANNEL_5: IPCC Channel 5
00298   *            @arg IPCC_CHANNEL_6: IPCC Channel 6
00299   * @param  ChannelDir Channel direction
00300   * @param  cb Interrupt callback
00301   * @retval HAL status
00302   */
00303 HAL_StatusTypeDef HAL_IPCC_ActivateNotification(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir, ChannelCb cb)
00304 {
00305   HAL_StatusTypeDef err = HAL_OK;
00306
00307   /* Check the IPCC handle allocation */
00308   if (hipcc != NULL)
00309   {
00310     /* Check the parameters */
00311     assert_param(IS_IPCC_ALL_INSTANCE(hipcc->Instance));
00312
00313     /* Check IPCC state */
00314     if (hipcc->State == HAL_IPCC_STATE_READY)
00315     {
00316       /* Set callback and register masking information */
00317       if (ChannelDir == IPCC_CHANNEL_DIR_TX)
00318       {
00319         hipcc->ChannelCallbackTx[ChannelIndex] = cb;
00320         hipcc->callbackRequest |= (IPCC_MR_CH1FM_Msk << (ChannelIndex & CHANNEL_INDEX_Msk));
00321       }
00322       else
00323       {
00324         hipcc->ChannelCallbackRx[ChannelIndex] = cb;
00325         hipcc->callbackRequest |= (IPCC_MR_CH1OM_Msk << (ChannelIndex & CHANNEL_INDEX_Msk));
00326       }
00327
00328       /* Unmask only the channels in reception (Transmission channel mask/unmask is done in HAL_IPCC_NotifyCPU) */
00329       if (ChannelDir == IPCC_CHANNEL_DIR_RX)
00330       {
00331         IPCC_UnmaskInterrupt(ChannelIndex, ChannelDir);
00332       }
00333     }
00334     else
00335     {
00336       err = HAL_ERROR;
00337     }
00338   }
00339   else
00340   {
00341     err = HAL_ERROR;
00342   }
00343   return err;
00344 }
00345
00346 /**
00347   * @brief  Remove the callback notification on receive/transmit interrupt
00348   * @param  hipcc IPCC handle
00349   * @param  ChannelIndex Channel number
00350   *          This parameter can be one of the following values:
00351   *            @arg IPCC_CHANNEL_1: IPCC Channel 1
00352   *            @arg IPCC_CHANNEL_2: IPCC Channel 2
00353   *            @arg IPCC_CHANNEL_3: IPCC Channel 3
00354   *            @arg IPCC_CHANNEL_4: IPCC Channel 4
00355   *            @arg IPCC_CHANNEL_5: IPCC Channel 5
00356   *            @arg IPCC_CHANNEL_6: IPCC Channel 6
00357   * @param  ChannelDir Channel direction
00358   * @retval HAL status
00359   */
00360 HAL_StatusTypeDef HAL_IPCC_DeActivateNotification(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
00361 {
00362   HAL_StatusTypeDef err = HAL_OK;
00363
00364   /* Check the IPCC handle allocation */
00365   if (hipcc != NULL)
00366   {
00367     /* Check the parameters */
00368     assert_param(IS_IPCC_ALL_INSTANCE(hipcc->Instance));
00369
00370     /* Check IPCC state */
00371     if (hipcc->State == HAL_IPCC_STATE_READY)
00372     {
00373       /* Set default callback and register masking information */
00374       if (ChannelDir == IPCC_CHANNEL_DIR_TX)
00375       {
00376         hipcc->ChannelCallbackTx[ChannelIndex] = HAL_IPCC_TxCallback;
00377         hipcc->callbackRequest &= ~(IPCC_MR_CH1FM_Msk << (ChannelIndex & CHANNEL_INDEX_Msk));
00378       }
00379       else
00380       {
00381         hipcc->ChannelCallbackRx[ChannelIndex] = HAL_IPCC_RxCallback;
00382         hipcc->callbackRequest &= ~(IPCC_MR_CH1OM_Msk << (ChannelIndex & CHANNEL_INDEX_Msk));
00383       }
00384
00385       /* Mask the interrupt */
00386       IPCC_MaskInterrupt(ChannelIndex, ChannelDir);
00387     }
00388     else
00389     {
00390       err = HAL_ERROR;
00391     }
00392   }
00393   else
00394   {
00395     err = HAL_ERROR;
00396   }
00397   return err;
00398 }
00399
00400 /**
00401   * @brief  Get state of IPCC channel
00402   * @param  hipcc IPCC handle
00403   * @param  ChannelIndex Channel number
00404   *          This parameter can be one of the following values:
00405   *            @arg IPCC_CHANNEL_1: IPCC Channel 1
00406   *            @arg IPCC_CHANNEL_2: IPCC Channel 2
00407   *            @arg IPCC_CHANNEL_3: IPCC Channel 3
00408   *            @arg IPCC_CHANNEL_4: IPCC Channel 4
00409   *            @arg IPCC_CHANNEL_5: IPCC Channel 5
00410   *            @arg IPCC_CHANNEL_6: IPCC Channel 6
00411   * @param  ChannelDir Channel direction
00412   * @retval Channel status
00413   */
00414 IPCC_CHANNELStatusTypeDef HAL_IPCC_GetChannelStatus(IPCC_HandleTypeDef const *const hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
00415 {
00416   uint32_t channel_state;
00417   IPCC_CommonTypeDef *currentInstance = IPCC_C1;
00418   IPCC_CommonTypeDef *otherInstance = IPCC_C2;
00419
00420   /* Check the parameters */
00421   assert_param(IS_IPCC_ALL_INSTANCE(hipcc->Instance));
00422
00423   /* Read corresponding channel depending of the MCU and the direction */
00424   if (ChannelDir == IPCC_CHANNEL_DIR_TX)
00425   {
00426     channel_state = (currentInstance->SR) & (IPCC_SR_CH1F_Msk << (ChannelIndex & CHANNEL_INDEX_Msk));
00427   }
00428   else
00429   {
00430     channel_state = (otherInstance->SR) & (IPCC_SR_CH1F_Msk << (ChannelIndex & CHANNEL_INDEX_Msk));
00431   }
00432
00433   return (channel_state == 0UL) ? IPCC_CHANNEL_STATUS_FREE : IPCC_CHANNEL_STATUS_OCCUPIED ;
00434 }
00435
00436 /**
00437   * @brief  Notify remote processor
00438   * @param  hipcc IPCC handle
00439   * @param  ChannelIndex Channel number
00440   *          This parameter can be one of the following values:
00441   *            @arg IPCC_CHANNEL_1: IPCC Channel 1
00442   *            @arg IPCC_CHANNEL_2: IPCC Channel 2
00443   *            @arg IPCC_CHANNEL_3: IPCC Channel 3
00444   *            @arg IPCC_CHANNEL_4: IPCC Channel 4
00445   *            @arg IPCC_CHANNEL_5: IPCC Channel 5
00446   *            @arg IPCC_CHANNEL_6: IPCC Channel 6
00447   * @param  ChannelDir Channel direction
00448   * @retval HAL status
00449   */
00450 HAL_StatusTypeDef HAL_IPCC_NotifyCPU(IPCC_HandleTypeDef const *const hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
00451 {
00452   HAL_StatusTypeDef err = HAL_OK;
00453   uint32_t mask;
00454   IPCC_CommonTypeDef *currentInstance = IPCC_C1;
00455
00456   /* Check the parameters */
00457   assert_param(IS_IPCC_ALL_INSTANCE(hipcc->Instance));
00458
00459   /* Check if IPCC is initiliased */
00460   if (hipcc->State == HAL_IPCC_STATE_READY)
00461   {
00462     /* For IPCC_CHANNEL_DIR_TX, set the status. For IPCC_CHANNEL_DIR_RX, clear the status */
00463     currentInstance->SCR |= ((ChannelDir == IPCC_CHANNEL_DIR_TX) ? IPCC_SCR_CH1S : IPCC_SCR_CH1C) << (ChannelIndex & CHANNEL_INDEX_Msk) ;
00464
00465     /* Unmask interrupt if the callback is requested */
00466     mask = ((ChannelDir == IPCC_CHANNEL_DIR_TX) ? IPCC_MR_CH1FM_Msk : IPCC_MR_CH1OM_Msk) << (ChannelIndex & CHANNEL_INDEX_Msk) ;
00467     if ((hipcc->callbackRequest & mask) == mask)
00468     {
00469       IPCC_UnmaskInterrupt(ChannelIndex, ChannelDir);
00470     }
00471   }
00472   else
00473   {
00474     err = HAL_ERROR;
00475   }
00476
00477   return err;
00478 }
00479
00480 /**
00481   * @}
00482   */
00483
00484 /** @addtogroup IPCC_IRQ_Handler_and_Callbacks
00485  * @{
00486  */
00487
00488 /**
00489   * @brief  This function handles IPCC Tx Free interrupt request.
00490   * @param  hipcc IPCC handle
00491   * @retval None
00492   */
00493 void HAL_IPCC_TX_IRQHandler(IPCC_HandleTypeDef *const hipcc)
00494 {
00495   uint32_t irqmask;
00496   uint32_t bit_pos;
00497   uint32_t ch_count = 0U;
00498   IPCC_CommonTypeDef *currentInstance = IPCC_C1;
00499
00500   /* check the Tx free channels which are not masked */
00501   irqmask = ~(currentInstance->MR) & IPCC_ALL_TX_BUF;
00502   irqmask = irqmask & ~(currentInstance->SR << IPCC_MR_CH1FM_Pos);
00503
00504   while (irqmask != 0UL)  /* if several bits are set, it loops to serve all of them */
00505   {
00506     bit_pos = 1UL << (IPCC_MR_CH1FM_Pos + (ch_count & CHANNEL_INDEX_Msk));
00507
00508     if ((irqmask & bit_pos) != 0U)
00509     {
00510       /* mask the channel Free interrupt  */
00511       currentInstance->MR |= bit_pos;
00512       if (hipcc->ChannelCallbackTx[ch_count] != NULL)
00513       {
00514         hipcc->ChannelCallbackTx[ch_count](hipcc, ch_count, IPCC_CHANNEL_DIR_TX);
00515       }
00516       irqmask =  irqmask & ~(bit_pos);
00517     }
00518     ch_count++;
00519   }
00520 }
00521
00522 /**
00523   * @brief  This function handles IPCC Rx Occupied interrupt request.
00524   * @param  hipcc : IPCC handle
00525   * @retval None
00526   */
00527 void HAL_IPCC_RX_IRQHandler(IPCC_HandleTypeDef *const hipcc)
00528 {
00529   uint32_t irqmask;
00530   uint32_t bit_pos;
00531   uint32_t ch_count = 0U;
00532   IPCC_CommonTypeDef *currentInstance = IPCC_C1;
00533   IPCC_CommonTypeDef *otherInstance = IPCC_C2;
00534
00535   /* check the Rx occupied channels which are not masked */
00536   irqmask = ~(currentInstance->MR) & IPCC_ALL_RX_BUF;
00537   irqmask = irqmask & otherInstance->SR;
00538
00539   while (irqmask != 0UL)  /* if several bits are set, it loops to serve all of them */
00540   {
00541     bit_pos = 1UL << (ch_count & CHANNEL_INDEX_Msk);
00542
00543     if ((irqmask & bit_pos) != 0U)
00544     {
00545       /* mask the channel occupied interrupt */
00546       currentInstance->MR |= bit_pos;
00547       if (hipcc->ChannelCallbackRx[ch_count] != NULL)
00548       {
00549         hipcc->ChannelCallbackRx[ch_count](hipcc, ch_count, IPCC_CHANNEL_DIR_RX);
00550       }
00551       irqmask = irqmask & ~(bit_pos);
00552     }
00553     ch_count++;
00554   }
00555 }
00556
00557 /**
00558   * @brief Rx occupied callback
00559   * @param hipcc IPCC handle
00560   * @param ChannelIndex Channel number
00561   *          This parameter can be one of the following values:
00562   *            @arg IPCC_CHANNEL_1: IPCC Channel 1
00563   *            @arg IPCC_CHANNEL_2: IPCC Channel 2
00564   *            @arg IPCC_CHANNEL_3: IPCC Channel 3
00565   *            @arg IPCC_CHANNEL_4: IPCC Channel 4
00566   *            @arg IPCC_CHANNEL_5: IPCC Channel 5
00567   *            @arg IPCC_CHANNEL_6: IPCC Channel 6
00568   * @param ChannelDir Channel direction
00569   */
00570 __weak void HAL_IPCC_RxCallback(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
00571 {
00572   /* Prevent unused argument(s) compilation warning */
00573   UNUSED(hipcc);
00574   UNUSED(ChannelIndex);
00575   UNUSED(ChannelDir);
00576
00577   /* NOTE : This function should not be modified, when the callback is needed,
00578             the HAL_IPCC_RxCallback can be implemented in the user file
00579    */
00580 }
00581
00582 /**
00583   * @brief Tx free callback
00584   * @param hipcc IPCC handle
00585   * @param ChannelIndex Channel number
00586   *          This parameter can be one of the following values:
00587   *            @arg IPCC_CHANNEL_1: IPCC Channel 1
00588   *            @arg IPCC_CHANNEL_2: IPCC Channel 2
00589   *            @arg IPCC_CHANNEL_3: IPCC Channel 3
00590   *            @arg IPCC_CHANNEL_4: IPCC Channel 4
00591   *            @arg IPCC_CHANNEL_5: IPCC Channel 5
00592   *            @arg IPCC_CHANNEL_6: IPCC Channel 6
00593   * @param ChannelDir Channel direction
00594   */
00595 __weak void HAL_IPCC_TxCallback(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
00596 {
00597   /* Prevent unused argument(s) compilation warning */
00598   UNUSED(hipcc);
00599   UNUSED(ChannelIndex);
00600   UNUSED(ChannelDir);
00601
00602   /* NOTE : This function should not be modified, when the callback is needed,
00603             the HAL_IPCC_TxCallback can be implemented in the user file
00604    */
00605 }
00606
00607 /**
00608   * @}
00609   */
00610
00611 /** @addtogroup IPCC_Exported_Functions_Group3
00612  *  @brief   IPCC Peripheral State and Error functions
00613  *
00614 @verbatim
00615   ==============================================================================
00616             ##### Peripheral State and Error functions #####
00617   ==============================================================================
00618     [..]
00619     This subsection permit to get in run-time the status of the peripheral
00620     and the data flow.
00621
00622 @endverbatim
00623   * @{
00624   */
00625
00626 /**
00627   * @brief Return the IPCC handle state.
00628   * @param  hipcc IPCC handle
00629   * @retval IPCC handle state
00630   */
00631 HAL_IPCC_StateTypeDef HAL_IPCC_GetState(IPCC_HandleTypeDef const *const hipcc)
00632 {
00633   return hipcc->State;
00634 }
00635
00636 /**
00637   * @}
00638   */
00639
00640 /**
00641   * @}
00642   */
00643
00644 /** @addtogroup IPCC_Private_Functions
00645   * @{
00646   */
00647
00648 /**
00649   * @brief  Mask IPCC interrupts.
00650   * @param  ChannelIndex Channel number
00651   *          This parameter can be one of the following values:
00652   *            @arg IPCC_CHANNEL_1: IPCC Channel 1
00653   *            @arg IPCC_CHANNEL_2: IPCC Channel 2
00654   *            @arg IPCC_CHANNEL_3: IPCC Channel 3
00655   *            @arg IPCC_CHANNEL_4: IPCC Channel 4
00656   *            @arg IPCC_CHANNEL_5: IPCC Channel 5
00657   *            @arg IPCC_CHANNEL_6: IPCC Channel 6
00658   * @param  ChannelDir Channel direction
00659   */
00660 void IPCC_MaskInterrupt(uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
00661 {
00662   IPCC_CommonTypeDef *currentInstance = IPCC_C1;
00663   if (ChannelDir == IPCC_CHANNEL_DIR_TX)
00664   {
00665     /* Mask interrupt */
00666     currentInstance->MR |= (IPCC_MR_CH1FM_Msk << (ChannelIndex & CHANNEL_INDEX_Msk));
00667   }
00668   else
00669   {
00670     /* Mask interrupt */
00671     currentInstance->MR |= (IPCC_MR_CH1OM_Msk << (ChannelIndex & CHANNEL_INDEX_Msk));
00672   }
00673 }
00674 /**
00675   * @brief  Unmask IPCC interrupts.
00676   * @param  ChannelIndex Channel number
00677   *          This parameter can be one of the following values:
00678   *            @arg IPCC_CHANNEL_1: IPCC Channel 1
00679   *            @arg IPCC_CHANNEL_2: IPCC Channel 2
00680   *            @arg IPCC_CHANNEL_3: IPCC Channel 3
00681   *            @arg IPCC_CHANNEL_4: IPCC Channel 4
00682   *            @arg IPCC_CHANNEL_5: IPCC Channel 5
00683   *            @arg IPCC_CHANNEL_6: IPCC Channel 6
00684   * @param  ChannelDir Channel direction
00685   */
00686 void IPCC_UnmaskInterrupt(uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
00687 {
00688   IPCC_CommonTypeDef *currentInstance = IPCC_C1;
00689   if (ChannelDir == IPCC_CHANNEL_DIR_TX)
00690   {
00691     /* Unmask interrupt */
00692     currentInstance->MR &= ~(IPCC_MR_CH1FM_Msk << (ChannelIndex & CHANNEL_INDEX_Msk));
00693   }
00694   else
00695   {
00696     /* Unmask interrupt */
00697     currentInstance->MR &= ~(IPCC_MR_CH1OM_Msk << (ChannelIndex & CHANNEL_INDEX_Msk));
00698   }
00699 }
00700
00701 /**
00702   * @brief Reset all callbacks of the handle to NULL.
00703   * @param  hipcc IPCC handle
00704   */
00705 void IPCC_SetDefaultCallbacks(IPCC_HandleTypeDef *hipcc)
00706 {
00707   uint32_t i;
00708   /* Set all callbacks to default */
00709   for (i = 0; i < IPCC_CHANNEL_NUMBER; i++)
00710   {
00711     hipcc->ChannelCallbackRx[i] = HAL_IPCC_RxCallback;
00712     hipcc->ChannelCallbackTx[i] = HAL_IPCC_TxCallback;
00713   }
00714 }
00715
00716 /**
00717   * @brief Reset IPCC register to default value for the concerned instance.
00718   * @param  Instance pointer to register
00719   */
00720 void IPCC_Reset_Register(IPCC_CommonTypeDef *Instance)
00721 {
00722   /* Disable RX and TX interrupts */
00723   Instance->CR  = 0x00000000U;
00724
00725   /* Mask RX and TX interrupts */
00726   Instance->MR  = (IPCC_ALL_TX_BUF | IPCC_ALL_RX_BUF);
00727
00728   /* Clear RX status */
00729   Instance->SCR = IPCC_ALL_RX_BUF;
00730 }
00731
00732 /**
00733   * @}
00734   */
00735
00736 #endif /* HAL_IPCC_MODULE_ENABLED */
00737
00738 /**
00739   * @}
00740   */
00741
00742 /**
00743   * @}
00744   */
00745
00746 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_ipcc.h Source File

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stm32wbxx_hal_ipcc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_ipcc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of Mailbox HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_IPCC_H
00022 #define STM32WBxx_HAL_IPCC_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031
00032 /** @addtogroup STM32WBxx_HAL_Driver
00033   * @{
00034   */
00035
00036 /** @defgroup IPCC IPCC
00037   * @brief IPCC HAL module driver
00038   * @{
00039   */
00040
00041 /* Exported constants --------------------------------------------------------*/
00042
00043 /** @defgroup IPCC_Exported_Constants IPCC Exported Constants
00044   * @{
00045   */
00046
00047 /** @defgroup IPCC_Channel IPCC Channel
00048   * @{
00049   */
00050 #define IPCC_CHANNEL_1 0x00000000U
00051 #define IPCC_CHANNEL_2 0x00000001U
00052 #define IPCC_CHANNEL_3 0x00000002U
00053 #define IPCC_CHANNEL_4 0x00000003U
00054 #define IPCC_CHANNEL_5 0x00000004U
00055 #define IPCC_CHANNEL_6 0x00000005U
00056 /**
00057   * @}
00058   */
00059
00060 /**
00061   * @}
00062   */
00063
00064 /* Exported types ------------------------------------------------------------*/
00065 /** @defgroup IPCC_Exported_Types IPCC Exported Types
00066   * @{
00067   */
00068
00069 /**
00070   * @brief HAL IPCC State structures definition
00071   */
00072 typedef enum
00073 {
00074   HAL_IPCC_STATE_RESET             = 0x00U,  /*!< IPCC not yet initialized or disabled  */
00075   HAL_IPCC_STATE_READY             = 0x01U,  /*!< IPCC initialized and ready for use    */
00076   HAL_IPCC_STATE_BUSY              = 0x02U   /*!< IPCC internal processing is ongoing   */
00077 } HAL_IPCC_StateTypeDef;
00078
00079 /**
00080   * @brief  IPCC channel direction structure definition
00081   */
00082 typedef enum
00083 {
00084   IPCC_CHANNEL_DIR_TX  = 0x00U,  /*!< Channel direction Tx is used by an MCU to transmit */
00085   IPCC_CHANNEL_DIR_RX  = 0x01U   /*!< Channel direction Rx is used by an MCU to receive */
00086 } IPCC_CHANNELDirTypeDef;
00087
00088 /**
00089   * @brief  IPCC channel status structure definition
00090   */
00091 typedef enum
00092 {
00093   IPCC_CHANNEL_STATUS_FREE       = 0x00U,  /*!< Means that a new msg can be posted on that channel */
00094   IPCC_CHANNEL_STATUS_OCCUPIED   = 0x01U   /*!< An MCU has posted a msg the other MCU hasn't retrieved */
00095 } IPCC_CHANNELStatusTypeDef;
00096
00097 /**
00098   * @brief  IPCC handle structure definition
00099   */
00100 typedef struct __IPCC_HandleTypeDef
00101 {
00102   IPCC_TypeDef                   *Instance;     /*!< IPCC registers base address */
00103   void (* ChannelCallbackRx[IPCC_CHANNEL_NUMBER])(struct __IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);                            /*!< Rx Callback registration table */
00104   void (* ChannelCallbackTx[IPCC_CHANNEL_NUMBER])(struct __IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);                            /*!< Tx Callback registration table */
00105   uint32_t                       callbackRequest; /*!< Store information about callback notification by channel */
00106   __IO HAL_IPCC_StateTypeDef      State;         /*!< IPCC State: initialized or not */
00107 } IPCC_HandleTypeDef;
00108
00109 /**
00110   * @brief  IPCC callback typedef
00111   */
00112 typedef void ChannelCb(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
00113
00114 /**
00115   * @}
00116   */
00117
00118 /* Exported macros -----------------------------------------------------------*/
00119 /** @defgroup IPCC_Exported_Macros IPCC Exported Macros
00120   * @{
00121   */
00122
00123 /**
00124   * @brief  Enable the specified interrupt.
00125   * @param  __HANDLE__ specifies the IPCC Handle
00126   * @param  __CHDIRECTION__ specifies the channels Direction
00127   *          This parameter can be one of the following values:
00128   *            @arg @ref IPCC_CHANNEL_DIR_TX Transmit channel free interrupt enable
00129   *            @arg @ref IPCC_CHANNEL_DIR_RX Receive channel occupied interrupt enable
00130   */
00131 #define __HAL_IPCC_ENABLE_IT(__HANDLE__, __CHDIRECTION__) \
00132             (((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
00133                 ((__HANDLE__)->Instance->C1CR |= IPCC_C1CR_RXOIE) : \
00134                 ((__HANDLE__)->Instance->C1CR |= IPCC_C1CR_TXFIE))
00135
00136 /**
00137   * @brief  Disable the specified interrupt.
00138   * @param  __HANDLE__ specifies the IPCC Handle
00139   * @param  __CHDIRECTION__ specifies the channels Direction
00140   *          This parameter can be one of the following values:
00141   *            @arg @ref IPCC_CHANNEL_DIR_TX Transmit channel free interrupt enable
00142   *            @arg @ref IPCC_CHANNEL_DIR_RX Receive channel occupied interrupt enable
00143   */
00144 #define __HAL_IPCC_DISABLE_IT(__HANDLE__, __CHDIRECTION__) \
00145             (((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
00146                 ((__HANDLE__)->Instance->C1CR &= ~IPCC_C1CR_RXOIE) : \
00147                 ((__HANDLE__)->Instance->C1CR &= ~IPCC_C1CR_TXFIE))
00148
00149 /**
00150   * @brief  Mask the specified interrupt.
00151   * @param  __HANDLE__ specifies the IPCC Handle
00152   * @param  __CHDIRECTION__ specifies the channels Direction
00153   *          This parameter can be one of the following values:
00154   *            @arg @ref IPCC_CHANNEL_DIR_TX Transmit channel free interrupt enable
00155   *            @arg @ref IPCC_CHANNEL_DIR_RX Receive channel occupied interrupt enable
00156   * @param  __CHINDEX__ specifies the channels number:
00157   *         This parameter can be one of the following values:
00158   *            @arg IPCC_CHANNEL_1: IPCC Channel 1
00159   *            @arg IPCC_CHANNEL_2: IPCC Channel 2
00160   *            @arg IPCC_CHANNEL_3: IPCC Channel 3
00161   *            @arg IPCC_CHANNEL_4: IPCC Channel 4
00162   *            @arg IPCC_CHANNEL_5: IPCC Channel 5
00163   *            @arg IPCC_CHANNEL_6: IPCC Channel 6
00164   */
00165 #define __HAL_IPCC_MASK_CHANNEL_IT(__HANDLE__, __CHDIRECTION__, __CHINDEX__) \
00166             (((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
00167                 ((__HANDLE__)->Instance->C1MR |= (IPCC_C1MR_CH1OM_Msk << (__CHINDEX__))) : \
00168                 ((__HANDLE__)->Instance->C1MR |= (IPCC_C1MR_CH1FM_Msk << (__CHINDEX__))))
00169
00170 /**
00171   * @brief  Unmask the specified interrupt.
00172   * @param  __HANDLE__ specifies the IPCC Handle
00173   * @param  __CHDIRECTION__ specifies the channels Direction
00174   *          This parameter can be one of the following values:
00175   *            @arg @ref IPCC_CHANNEL_DIR_TX Transmit channel free interrupt enable
00176   *            @arg @ref IPCC_CHANNEL_DIR_RX Receive channel occupied interrupt enable
00177   * @param  __CHINDEX__ specifies the channels number:
00178   *         This parameter can be one of the following values:
00179   *            @arg IPCC_CHANNEL_1: IPCC Channel 1
00180   *            @arg IPCC_CHANNEL_2: IPCC Channel 2
00181   *            @arg IPCC_CHANNEL_3: IPCC Channel 3
00182   *            @arg IPCC_CHANNEL_4: IPCC Channel 4
00183   *            @arg IPCC_CHANNEL_5: IPCC Channel 5
00184   *            @arg IPCC_CHANNEL_6: IPCC Channel 6
00185   */
00186 #define __HAL_IPCC_UNMASK_CHANNEL_IT(__HANDLE__, __CHDIRECTION__, __CHINDEX__) \
00187             (((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
00188                 ((__HANDLE__)->Instance->C1MR &= ~(IPCC_C1MR_CH1OM_Msk << (__CHINDEX__))) : \
00189                 ((__HANDLE__)->Instance->C1MR &= ~(IPCC_C1MR_CH1FM_Msk << (__CHINDEX__))))
00190
00191 /**
00192   * @}
00193   */
00194
00195 /* Exported functions --------------------------------------------------------*/
00196 /** @defgroup IPCC_Exported_Functions IPCC Exported Functions
00197   * @{
00198   */
00199
00200 /* Initialization and de-initialization functions *******************************/
00201 /** @defgroup IPCC_Exported_Functions_Group1 Initialization and deinitialization functions
00202  *  @{
00203  */
00204 HAL_StatusTypeDef HAL_IPCC_Init(IPCC_HandleTypeDef *hipcc);
00205 HAL_StatusTypeDef HAL_IPCC_DeInit(IPCC_HandleTypeDef *hipcc);
00206 void HAL_IPCC_MspInit(IPCC_HandleTypeDef *hipcc);
00207 void HAL_IPCC_MspDeInit(IPCC_HandleTypeDef *hipcc);
00208 /**
00209   * @}
00210   */
00211
00212 /** @defgroup IPCC_Exported_Functions_Group2 Communication functions
00213  *  @{
00214  */
00215 /* IO operation functions  *****************************************************/
00216 HAL_StatusTypeDef HAL_IPCC_ActivateNotification(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir, ChannelCb cb);
00217 HAL_StatusTypeDef HAL_IPCC_DeActivateNotification(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
00218 IPCC_CHANNELStatusTypeDef HAL_IPCC_GetChannelStatus(IPCC_HandleTypeDef const *const hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
00219 HAL_StatusTypeDef HAL_IPCC_NotifyCPU(IPCC_HandleTypeDef const *const hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
00220 /**
00221   * @}
00222   */
00223
00224 /** @defgroup IPCC_Exported_Functions_Group3 Peripheral State and Error functions
00225  *  @{
00226  */
00227 /* Peripheral State and Error functions ****************************************/
00228 HAL_IPCC_StateTypeDef HAL_IPCC_GetState(IPCC_HandleTypeDef const *const hipcc);
00229 /**
00230   * @}
00231   */
00232
00233 /** @defgroup IPCC_IRQ_Handler_and_Callbacks Peripheral IRQ Handler and Callbacks
00234  *  @{
00235  */
00236 /* IRQHandler and Callbacks used in non blocking modes  ************************/
00237 void HAL_IPCC_TX_IRQHandler(IPCC_HandleTypeDef   *const hipcc);
00238 void HAL_IPCC_RX_IRQHandler(IPCC_HandleTypeDef *const hipcc);
00239 void HAL_IPCC_TxCallback(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
00240 void HAL_IPCC_RxCallback(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
00241 /**
00242   * @}
00243   */
00244
00245 /**
00246   * @}
00247   */
00248
00249 /**
00250   * @}
00251   */
00252
00253 /**
00254   * @}
00255   */
00256
00257 #ifdef __cplusplus
00258 }
00259 #endif
00260
00261 #endif /* STM32WBxx_HAL_IPCC_H */
00262
00263 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_irda.c Source File

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stm32wbxx_hal_irda.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_irda.c
00004   * @author  MCD Application Team
00005   * @brief   IRDA HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the IrDA (Infrared Data Association) Peripheral
00008   *          (IRDA)
00009   *           + Initialization and de-initialization functions
00010   *           + IO operation functions
00011   *           + Peripheral State and Errors functions
00012   *           + Peripheral Control functions
00013   *
00014   @verbatim
00015   ==============================================================================
00016                         ##### How to use this driver #####
00017   ==============================================================================
00018   [..]
00019     The IRDA HAL driver can be used as follows:
00020
00021     (#) Declare a IRDA_HandleTypeDef handle structure (eg. IRDA_HandleTypeDef hirda).
00022     (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API
00023         in setting the associated USART or UART in IRDA mode:
00024         (++) Enable the USARTx/UARTx interface clock.
00025         (++) USARTx/UARTx pins configuration:
00026             (+++) Enable the clock for the USARTx/UARTx GPIOs.
00027             (+++) Configure these USARTx/UARTx pins (TX as alternate function pull-up, RX as alternate function Input).
00028         (++) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
00029              and HAL_IRDA_Receive_IT() APIs):
00030             (+++) Configure the USARTx/UARTx interrupt priority.
00031             (+++) Enable the NVIC USARTx/UARTx IRQ handle.
00032             (+++) The specific IRDA interrupts (Transmission complete interrupt,
00033                   RXNE interrupt and Error Interrupts) will be managed using the macros
00034                   __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
00035
00036         (++) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
00037              and HAL_IRDA_Receive_DMA() APIs):
00038             (+++) Declare a DMA handle structure for the Tx/Rx channel.
00039             (+++) Enable the DMAx interface clock.
00040             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00041             (+++) Configure the DMA Tx/Rx channel.
00042             (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
00043             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
00044
00045     (#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter),
00046         the normal or low power mode and the clock prescaler in the hirda handle Init structure.
00047
00048     (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
00049         (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00050              by calling the customized HAL_IRDA_MspInit() API.
00051
00052          -@@- The specific IRDA interrupts (Transmission complete interrupt,
00053              RXNE interrupt and Error Interrupts) will be managed using the macros
00054              __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
00055
00056     (#) Three operation modes are available within this driver :
00057
00058      *** Polling mode IO operation ***
00059      =================================
00060      [..]
00061        (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
00062        (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
00063
00064      *** Interrupt mode IO operation ***
00065      ===================================
00066      [..]
00067        (+) Send an amount of data in non-blocking mode using HAL_IRDA_Transmit_IT()
00068        (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
00069             add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
00070        (+) Receive an amount of data in non-blocking mode using HAL_IRDA_Receive_IT()
00071        (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
00072             add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
00073        (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
00074             add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
00075
00076      *** DMA mode IO operation ***
00077      ==============================
00078      [..]
00079        (+) Send an amount of data in non-blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
00080        (+) At transmission half of transfer HAL_IRDA_TxHalfCpltCallback() is executed and user can
00081             add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback()
00082        (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
00083             add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
00084        (+) Receive an amount of data in non-blocking mode (DMA) using HAL_IRDA_Receive_DMA()
00085        (+) At reception half of transfer HAL_IRDA_RxHalfCpltCallback() is executed and user can
00086             add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback()
00087        (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
00088             add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
00089        (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
00090             add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
00091
00092      *** IRDA HAL driver macros list ***
00093      ====================================
00094      [..]
00095        Below the list of most used macros in IRDA HAL driver.
00096
00097        (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
00098        (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
00099        (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
00100        (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
00101        (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
00102        (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
00103        (+) __HAL_IRDA_GET_IT_SOURCE: Check whether or not the specified IRDA interrupt is enabled
00104
00105      [..]
00106        (@) You can refer to the IRDA HAL driver header file for more useful macros
00107
00108     ##### Callback registration #####
00109     ==================================
00110
00111     [..]
00112     The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS when set to 1
00113     allows the user to configure dynamically the driver callbacks.
00114
00115     [..]
00116     Use Function @ref HAL_IRDA_RegisterCallback() to register a user callback.
00117     Function @ref HAL_IRDA_RegisterCallback() allows to register following callbacks:
00118     (+) TxHalfCpltCallback        : Tx Half Complete Callback.
00119     (+) TxCpltCallback            : Tx Complete Callback.
00120     (+) RxHalfCpltCallback        : Rx Half Complete Callback.
00121     (+) RxCpltCallback            : Rx Complete Callback.
00122     (+) ErrorCallback             : Error Callback.
00123     (+) AbortCpltCallback         : Abort Complete Callback.
00124     (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
00125     (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
00126     (+) MspInitCallback           : IRDA MspInit.
00127     (+) MspDeInitCallback         : IRDA MspDeInit.
00128     This function takes as parameters the HAL peripheral handle, the Callback ID
00129     and a pointer to the user callback function.
00130
00131     [..]
00132     Use function @ref HAL_IRDA_UnRegisterCallback() to reset a callback to the default
00133     weak (surcharged) function.
00134     @ref HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00135     and the Callback ID.
00136     This function allows to reset following callbacks:
00137     (+) TxHalfCpltCallback        : Tx Half Complete Callback.
00138     (+) TxCpltCallback            : Tx Complete Callback.
00139     (+) RxHalfCpltCallback        : Rx Half Complete Callback.
00140     (+) RxCpltCallback            : Rx Complete Callback.
00141     (+) ErrorCallback             : Error Callback.
00142     (+) AbortCpltCallback         : Abort Complete Callback.
00143     (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
00144     (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
00145     (+) MspInitCallback           : IRDA MspInit.
00146     (+) MspDeInitCallback         : IRDA MspDeInit.
00147
00148     [..]
00149     By default, after the @ref HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET
00150     all callbacks are set to the corresponding weak (surcharged) functions:
00151     examples @ref HAL_IRDA_TxCpltCallback(), @ref HAL_IRDA_RxHalfCpltCallback().
00152     Exception done for MspInit and MspDeInit functions that are respectively
00153     reset to the legacy weak (surcharged) functions in the @ref HAL_IRDA_Init()
00154     and @ref HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand).
00155     If not, MspInit or MspDeInit are not null, the @ref HAL_IRDA_Init() and @ref HAL_IRDA_DeInit()
00156     keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
00157
00158     [..]
00159     Callbacks can be registered/unregistered in HAL_IRDA_STATE_READY state only.
00160     Exception done MspInit/MspDeInit that can be registered/unregistered
00161     in HAL_IRDA_STATE_READY or HAL_IRDA_STATE_RESET state, thus registered (user)
00162     MspInit/DeInit callbacks can be used during the Init/DeInit.
00163     In that case first register the MspInit/MspDeInit user callbacks
00164     using @ref HAL_IRDA_RegisterCallback() before calling @ref HAL_IRDA_DeInit()
00165     or @ref HAL_IRDA_Init() function.
00166
00167     [..]
00168     When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or
00169     not defined, the callback registration feature is not available
00170     and weak (surcharged) callbacks are used.
00171
00172
00173   @endverbatim
00174   ******************************************************************************
00175   * @attention
00176   *
00177   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00178   * All rights reserved.</center></h2>
00179   *
00180   * This software component is licensed by ST under BSD 3-Clause license,
00181   * the "License"; You may not use this file except in compliance with the
00182   * License. You may obtain a copy of the License at:
00183   *                        opensource.org/licenses/BSD-3-Clause
00184   *
00185   ******************************************************************************
00186   */
00187
00188 /* Includes ------------------------------------------------------------------*/
00189 #include "stm32wbxx_hal.h"
00190
00191 /** @addtogroup STM32WBxx_HAL_Driver
00192   * @{
00193   */
00194
00195 /** @defgroup IRDA IRDA
00196   * @brief HAL IRDA module driver
00197   * @{
00198   */
00199
00200 #ifdef HAL_IRDA_MODULE_ENABLED
00201
00202 /* Private typedef -----------------------------------------------------------*/
00203 /* Private define ------------------------------------------------------------*/
00204 /** @defgroup IRDA_Private_Constants IRDA Private Constants
00205   * @{
00206   */
00207 #define IRDA_TEACK_REACK_TIMEOUT            1000U                                   /*!< IRDA TX or RX enable acknowledge time-out value  */
00208
00209 #define IRDA_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE \
00210                                    | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE))  /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */
00211
00212 #define USART_BRR_MIN    0x10U        /*!< USART BRR minimum authorized value */
00213
00214 #define USART_BRR_MAX    0x0000FFFFU  /*!< USART BRR maximum authorized value */
00215 /**
00216   * @}
00217   */
00218
00219 /* Private macros ------------------------------------------------------------*/
00220 /** @defgroup IRDA_Private_Macros IRDA Private Macros
00221   * @{
00222   */
00223 /** @brief  BRR division operation to set BRR register in 16-bit oversampling mode.
00224   * @param  __PCLK__ IRDA clock source.
00225   * @param  __BAUD__ Baud rate set by the user.
00226   * @param  __PRESCALER__ IRDA clock prescaler value.
00227   * @retval Division result
00228   */
00229 #define IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__, __PRESCALER__)  ((((__PCLK__)/IRDAPrescTable[(__PRESCALER__)]) + ((__BAUD__)/2U)) / (__BAUD__))
00230 /**
00231   * @}
00232   */
00233
00234 /* Private variables ---------------------------------------------------------*/
00235 /* Private function prototypes -----------------------------------------------*/
00236 /** @addtogroup IRDA_Private_Functions
00237   * @{
00238   */
00239 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
00240 void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda);
00241 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
00242 static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda);
00243 static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);
00244 static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
00245 static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);
00246 static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
00247 static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00248 static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
00249 static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00250 static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
00251 static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
00252 static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma);
00253 static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
00254 static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
00255 static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00256 static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00257 static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
00258 static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
00259 static void IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
00260 /**
00261   * @}
00262   */
00263
00264 /* Exported functions --------------------------------------------------------*/
00265
00266 /** @defgroup IRDA_Exported_Functions IRDA Exported Functions
00267   * @{
00268   */
00269
00270 /** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
00271   *  @brief    Initialization and Configuration functions
00272   *
00273 @verbatim
00274   ==============================================================================
00275               ##### Initialization and Configuration functions #####
00276   ==============================================================================
00277   [..]
00278   This subsection provides a set of functions allowing to initialize the USARTx
00279   in asynchronous IRDA mode.
00280   (+) For the asynchronous mode only these parameters can be configured:
00281       (++) Baud Rate
00282       (++) Word Length
00283       (++) Parity: If the parity is enabled, then the MSB bit of the data written
00284            in the data register is transmitted but is changed by the parity bit.
00285       (++) Power mode
00286       (++) Prescaler setting
00287       (++) Receiver/transmitter modes
00288
00289   [..]
00290   The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures
00291   (details for the procedures are available in reference manual).
00292
00293 @endverbatim
00294
00295   Depending on the frame length defined by the M1 and M0 bits (7-bit,
00296   8-bit or 9-bit), the possible IRDA frame formats are listed in the
00297   following table.
00298
00299     Table 1. IRDA frame format.
00300     +-----------------------------------------------------------------------+
00301     |  M1 bit |  M0 bit |  PCE bit  |             IRDA frame                |
00302     |---------|---------|-----------|---------------------------------------|
00303     |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
00304     |---------|---------|-----------|---------------------------------------|
00305     |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
00306     |---------|---------|-----------|---------------------------------------|
00307     |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
00308     |---------|---------|-----------|---------------------------------------|
00309     |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
00310     |---------|---------|-----------|---------------------------------------|
00311     |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
00312     |---------|---------|-----------|---------------------------------------|
00313     |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
00314     +-----------------------------------------------------------------------+
00315
00316   * @{
00317   */
00318
00319 /**
00320   * @brief Initialize the IRDA mode according to the specified
00321   *        parameters in the IRDA_InitTypeDef and initialize the associated handle.
00322   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
00323   *               the configuration information for the specified IRDA module.
00324   * @retval HAL status
00325   */
00326 HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
00327 {
00328   /* Check the IRDA handle allocation */
00329   if (hirda == NULL)
00330   {
00331     return HAL_ERROR;
00332   }
00333
00334   /* Check the USART/UART associated to the IRDA handle */
00335   assert_param(IS_IRDA_INSTANCE(hirda->Instance));
00336
00337   if (hirda->gState == HAL_IRDA_STATE_RESET)
00338   {
00339     /* Allocate lock resource and initialize it */
00340     hirda->Lock = HAL_UNLOCKED;
00341
00342 #if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
00343     IRDA_InitCallbacksToDefault(hirda);
00344
00345     if (hirda->MspInitCallback == NULL)
00346     {
00347       hirda->MspInitCallback = HAL_IRDA_MspInit;
00348     }
00349
00350     /* Init the low level hardware */
00351     hirda->MspInitCallback(hirda);
00352 #else
00353     /* Init the low level hardware : GPIO, CLOCK */
00354     HAL_IRDA_MspInit(hirda);
00355 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
00356   }
00357
00358   hirda->gState = HAL_IRDA_STATE_BUSY;
00359
00360   /* Disable the Peripheral to update the configuration registers */
00361   __HAL_IRDA_DISABLE(hirda);
00362
00363   /* Set the IRDA Communication parameters */
00364   if (IRDA_SetConfig(hirda) == HAL_ERROR)
00365   {
00366     return HAL_ERROR;
00367   }
00368
00369   /* In IRDA mode, the following bits must be kept cleared:
00370   - LINEN, STOP and CLKEN bits in the USART_CR2 register,
00371   - SCEN and HDSEL bits in the USART_CR3 register.*/
00372   CLEAR_BIT(hirda->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
00373   CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
00374
00375   /* set the UART/USART in IRDA mode */
00376   hirda->Instance->CR3 |= USART_CR3_IREN;
00377
00378   /* Enable the Peripheral */
00379   __HAL_IRDA_ENABLE(hirda);
00380
00381   /* TEACK and/or REACK to check before moving hirda->gState and hirda->RxState to Ready */
00382   return (IRDA_CheckIdleState(hirda));
00383 }
00384
00385 /**
00386   * @brief DeInitialize the IRDA peripheral.
00387   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
00388   *               the configuration information for the specified IRDA module.
00389   * @retval HAL status
00390   */
00391 HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
00392 {
00393   /* Check the IRDA handle allocation */
00394   if (hirda == NULL)
00395   {
00396     return HAL_ERROR;
00397   }
00398
00399   /* Check the USART/UART associated to the IRDA handle */
00400   assert_param(IS_IRDA_INSTANCE(hirda->Instance));
00401
00402   hirda->gState = HAL_IRDA_STATE_BUSY;
00403
00404   /* DeInit the low level hardware */
00405 #if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
00406   if (hirda->MspDeInitCallback == NULL)
00407   {
00408     hirda->MspDeInitCallback = HAL_IRDA_MspDeInit;
00409   }
00410   /* DeInit the low level hardware */
00411   hirda->MspDeInitCallback(hirda);
00412 #else
00413   HAL_IRDA_MspDeInit(hirda);
00414 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
00415   /* Disable the Peripheral */
00416   __HAL_IRDA_DISABLE(hirda);
00417
00418   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00419   hirda->gState    = HAL_IRDA_STATE_RESET;
00420   hirda->RxState   = HAL_IRDA_STATE_RESET;
00421
00422   /* Process Unlock */
00423   __HAL_UNLOCK(hirda);
00424
00425   return HAL_OK;
00426 }
00427
00428 /**
00429   * @brief Initialize the IRDA MSP.
00430   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
00431   *               the configuration information for the specified IRDA module.
00432   * @retval None
00433   */
00434 __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
00435 {
00436   /* Prevent unused argument(s) compilation warning */
00437   UNUSED(hirda);
00438
00439   /* NOTE: This function should not be modified, when the callback is needed,
00440            the HAL_IRDA_MspInit can be implemented in the user file
00441    */
00442 }
00443
00444 /**
00445   * @brief DeInitialize the IRDA MSP.
00446   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
00447   *               the configuration information for the specified IRDA module.
00448   * @retval None
00449   */
00450 __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
00451 {
00452   /* Prevent unused argument(s) compilation warning */
00453   UNUSED(hirda);
00454
00455   /* NOTE: This function should not be modified, when the callback is needed,
00456            the HAL_IRDA_MspDeInit can be implemented in the user file
00457    */
00458 }
00459
00460 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
00461 /**
00462   * @brief  Register a User IRDA Callback
00463   *         To be used instead of the weak predefined callback
00464   * @param  hirda irda handle
00465   * @param  CallbackID ID of the callback to be registered
00466   *         This parameter can be one of the following values:
00467   *           @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
00468   *           @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID
00469   *           @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
00470   *           @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID
00471   *           @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID
00472   *           @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
00473   *           @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
00474   *           @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
00475   *           @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID
00476   *           @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID
00477   * @param  pCallback pointer to the Callback function
00478   * @retval HAL status
00479   */
00480 HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback)
00481 {
00482   HAL_StatusTypeDef status = HAL_OK;
00483
00484   if (pCallback == NULL)
00485   {
00486     /* Update the error code */
00487     hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
00488
00489     return HAL_ERROR;
00490   }
00491   /* Process locked */
00492   __HAL_LOCK(hirda);
00493
00494   if (hirda->gState == HAL_IRDA_STATE_READY)
00495   {
00496     switch (CallbackID)
00497     {
00498       case HAL_IRDA_TX_HALFCOMPLETE_CB_ID :
00499         hirda->TxHalfCpltCallback = pCallback;
00500         break;
00501
00502       case HAL_IRDA_TX_COMPLETE_CB_ID :
00503         hirda->TxCpltCallback = pCallback;
00504         break;
00505
00506       case HAL_IRDA_RX_HALFCOMPLETE_CB_ID :
00507         hirda->RxHalfCpltCallback = pCallback;
00508         break;
00509
00510       case HAL_IRDA_RX_COMPLETE_CB_ID :
00511         hirda->RxCpltCallback = pCallback;
00512         break;
00513
00514       case HAL_IRDA_ERROR_CB_ID :
00515         hirda->ErrorCallback = pCallback;
00516         break;
00517
00518       case HAL_IRDA_ABORT_COMPLETE_CB_ID :
00519         hirda->AbortCpltCallback = pCallback;
00520         break;
00521
00522       case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID :
00523         hirda->AbortTransmitCpltCallback = pCallback;
00524         break;
00525
00526       case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID :
00527         hirda->AbortReceiveCpltCallback = pCallback;
00528         break;
00529
00530       case HAL_IRDA_MSPINIT_CB_ID :
00531         hirda->MspInitCallback = pCallback;
00532         break;
00533
00534       case HAL_IRDA_MSPDEINIT_CB_ID :
00535         hirda->MspDeInitCallback = pCallback;
00536         break;
00537
00538       default :
00539         /* Update the error code */
00540         hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
00541
00542         /* Return error status */
00543         status =  HAL_ERROR;
00544         break;
00545     }
00546   }
00547   else if (hirda->gState == HAL_IRDA_STATE_RESET)
00548   {
00549     switch (CallbackID)
00550     {
00551       case HAL_IRDA_MSPINIT_CB_ID :
00552         hirda->MspInitCallback = pCallback;
00553         break;
00554
00555       case HAL_IRDA_MSPDEINIT_CB_ID :
00556         hirda->MspDeInitCallback = pCallback;
00557         break;
00558
00559       default :
00560         /* Update the error code */
00561         hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
00562
00563         /* Return error status */
00564         status =  HAL_ERROR;
00565         break;
00566     }
00567   }
00568   else
00569   {
00570     /* Update the error code */
00571     hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
00572
00573     /* Return error status */
00574     status =  HAL_ERROR;
00575   }
00576
00577   /* Release Lock */
00578   __HAL_UNLOCK(hirda);
00579
00580   return status;
00581 }
00582
00583 /**
00584   * @brief  Unregister an IRDA callback
00585   *         IRDA callback is redirected to the weak predefined callback
00586   * @param  hirda irda handle
00587   * @param  CallbackID ID of the callback to be unregistered
00588   *         This parameter can be one of the following values:
00589   *           @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
00590   *           @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID
00591   *           @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
00592   *           @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID
00593   *           @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID
00594   *           @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
00595   *           @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
00596   *           @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
00597   *           @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID
00598   *           @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID
00599   * @retval HAL status
00600   */
00601 HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID)
00602 {
00603   HAL_StatusTypeDef status = HAL_OK;
00604
00605   /* Process locked */
00606   __HAL_LOCK(hirda);
00607
00608   if (HAL_IRDA_STATE_READY == hirda->gState)
00609   {
00610     switch (CallbackID)
00611     {
00612       case HAL_IRDA_TX_HALFCOMPLETE_CB_ID :
00613         hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback;               /* Legacy weak  TxHalfCpltCallback       */
00614         break;
00615
00616       case HAL_IRDA_TX_COMPLETE_CB_ID :
00617         hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback;                       /* Legacy weak TxCpltCallback            */
00618         break;
00619
00620       case HAL_IRDA_RX_HALFCOMPLETE_CB_ID :
00621         hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback;               /* Legacy weak RxHalfCpltCallback        */
00622         break;
00623
00624       case HAL_IRDA_RX_COMPLETE_CB_ID :
00625         hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback;                       /* Legacy weak RxCpltCallback            */
00626         break;
00627
00628       case HAL_IRDA_ERROR_CB_ID :
00629         hirda->ErrorCallback = HAL_IRDA_ErrorCallback;                         /* Legacy weak ErrorCallback             */
00630         break;
00631
00632       case HAL_IRDA_ABORT_COMPLETE_CB_ID :
00633         hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback;                 /* Legacy weak AbortCpltCallback         */
00634         break;
00635
00636       case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID :
00637         hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
00638         break;
00639
00640       case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID :
00641         hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback;   /* Legacy weak AbortReceiveCpltCallback  */
00642         break;
00643
00644       case HAL_IRDA_MSPINIT_CB_ID :
00645         hirda->MspInitCallback = HAL_IRDA_MspInit;                             /* Legacy weak MspInitCallback           */
00646         break;
00647
00648       case HAL_IRDA_MSPDEINIT_CB_ID :
00649         hirda->MspDeInitCallback = HAL_IRDA_MspDeInit;                         /* Legacy weak MspDeInitCallback         */
00650         break;
00651
00652       default :
00653         /* Update the error code */
00654         hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
00655
00656         /* Return error status */
00657         status =  HAL_ERROR;
00658         break;
00659     }
00660   }
00661   else if (HAL_IRDA_STATE_RESET == hirda->gState)
00662   {
00663     switch (CallbackID)
00664     {
00665       case HAL_IRDA_MSPINIT_CB_ID :
00666         hirda->MspInitCallback = HAL_IRDA_MspInit;
00667         break;
00668
00669       case HAL_IRDA_MSPDEINIT_CB_ID :
00670         hirda->MspDeInitCallback = HAL_IRDA_MspDeInit;
00671         break;
00672
00673       default :
00674         /* Update the error code */
00675         hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
00676
00677         /* Return error status */
00678         status =  HAL_ERROR;
00679         break;
00680     }
00681   }
00682   else
00683   {
00684     /* Update the error code */
00685     hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
00686
00687     /* Return error status */
00688     status =  HAL_ERROR;
00689   }
00690
00691   /* Release Lock */
00692   __HAL_UNLOCK(hirda);
00693
00694   return status;
00695 }
00696 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
00697
00698 /**
00699   * @}
00700   */
00701
00702 /** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
00703   *  @brief   IRDA Transmit and Receive functions
00704   *
00705 @verbatim
00706  ===============================================================================
00707                          ##### IO operation functions #####
00708  ===============================================================================
00709   [..]
00710     This subsection provides a set of functions allowing to manage the IRDA data transfers.
00711
00712   [..]
00713     IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
00714     on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
00715     is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
00716     While receiving data, transmission should be avoided as the data to be transmitted
00717     could be corrupted.
00718
00719     (#) There are two modes of transfer:
00720         (++) Blocking mode: the communication is performed in polling mode.
00721              The HAL status of all data processing is returned by the same function
00722              after finishing transfer.
00723         (++) Non-Blocking mode: the communication is performed using Interrupts
00724              or DMA, these API's return the HAL status.
00725              The end of the data processing will be indicated through the
00726              dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
00727              using DMA mode.
00728              The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
00729              will be executed respectively at the end of the Transmit or Receive process
00730              The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
00731
00732     (#) Blocking mode APIs are :
00733         (++) HAL_IRDA_Transmit()
00734         (++) HAL_IRDA_Receive()
00735
00736     (#) Non Blocking mode APIs with Interrupt are :
00737         (++) HAL_IRDA_Transmit_IT()
00738         (++) HAL_IRDA_Receive_IT()
00739         (++) HAL_IRDA_IRQHandler()
00740
00741     (#) Non Blocking mode functions with DMA are :
00742         (++) HAL_IRDA_Transmit_DMA()
00743         (++) HAL_IRDA_Receive_DMA()
00744         (++) HAL_IRDA_DMAPause()
00745         (++) HAL_IRDA_DMAResume()
00746         (++) HAL_IRDA_DMAStop()
00747
00748     (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode:
00749         (++) HAL_IRDA_TxHalfCpltCallback()
00750         (++) HAL_IRDA_TxCpltCallback()
00751         (++) HAL_IRDA_RxHalfCpltCallback()
00752         (++) HAL_IRDA_RxCpltCallback()
00753         (++) HAL_IRDA_ErrorCallback()
00754
00755     (#) Non-Blocking mode transfers could be aborted using Abort API's :
00756         (+) HAL_IRDA_Abort()
00757         (+) HAL_IRDA_AbortTransmit()
00758         (+) HAL_IRDA_AbortReceive()
00759         (+) HAL_IRDA_Abort_IT()
00760         (+) HAL_IRDA_AbortTransmit_IT()
00761         (+) HAL_IRDA_AbortReceive_IT()
00762
00763     (#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
00764         (+) HAL_IRDA_AbortCpltCallback()
00765         (+) HAL_IRDA_AbortTransmitCpltCallback()
00766         (+) HAL_IRDA_AbortReceiveCpltCallback()
00767
00768     (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
00769         Errors are handled as follows :
00770        (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
00771            to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
00772            Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
00773            and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
00774            If user wants to abort it, Abort services should be called by user.
00775        (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
00776            This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
00777            Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
00778
00779 @endverbatim
00780   * @{
00781   */
00782
00783 /**
00784   * @brief Send an amount of data in blocking mode.
00785   * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
00786   *        the sent data is handled as a set of u16. In this case, Size must reflect the number
00787   *        of u16 available through pData.
00788   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
00789   *               the configuration information for the specified IRDA module.
00790   * @param pData Pointer to data buffer (u8 or u16 data elements).
00791   * @param Size Amount of data elements (u8 or u16) to be sent.
00792   * @param Timeout Specify timeout value.
00793   * @retval HAL status
00794   */
00795 HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00796 {
00797   uint8_t  *pdata8bits;
00798   uint16_t *pdata16bits;
00799   uint32_t tickstart;
00800
00801   /* Check that a Tx process is not already ongoing */
00802   if (hirda->gState == HAL_IRDA_STATE_READY)
00803   {
00804     if ((pData == NULL) || (Size == 0U))
00805     {
00806       return  HAL_ERROR;
00807     }
00808
00809     /* Process Locked */
00810     __HAL_LOCK(hirda);
00811
00812     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00813     hirda->gState = HAL_IRDA_STATE_BUSY_TX;
00814
00815     /* Init tickstart for timeout managment*/
00816     tickstart = HAL_GetTick();
00817
00818     hirda->TxXferSize = Size;
00819     hirda->TxXferCount = Size;
00820
00821     /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
00822     if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
00823     {
00824       pdata8bits  = NULL;
00825       pdata16bits = (uint16_t *) pData; /* Derogation R.11.3 */
00826     }
00827     else
00828     {
00829       pdata8bits  = pData;
00830       pdata16bits = NULL;
00831     }
00832
00833     while (hirda->TxXferCount > 0U)
00834     {
00835       hirda->TxXferCount--;
00836
00837       if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
00838       {
00839         return HAL_TIMEOUT;
00840       }
00841       if (pdata8bits == NULL)
00842       {
00843         hirda->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
00844         pdata16bits++;
00845       }
00846       else
00847       {
00848         hirda->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
00849         pdata8bits++;
00850       }
00851     }
00852
00853     if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
00854     {
00855       return HAL_TIMEOUT;
00856     }
00857
00858     /* At end of Tx process, restore hirda->gState to Ready */
00859     hirda->gState = HAL_IRDA_STATE_READY;
00860
00861     /* Process Unlocked */
00862     __HAL_UNLOCK(hirda);
00863
00864     return HAL_OK;
00865   }
00866   else
00867   {
00868     return HAL_BUSY;
00869   }
00870 }
00871
00872 /**
00873   * @brief Receive an amount of data in blocking mode.
00874   * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
00875   *        the received data is handled as a set of u16. In this case, Size must reflect the number
00876   *        of u16 available through pData.
00877   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
00878   *                the configuration information for the specified IRDA module.
00879   * @param pData Pointer to data buffer (u8 or u16 data elements).
00880   * @param Size Amount of data elements (u8 or u16) to be received.
00881   * @param Timeout Specify timeout value.
00882   * @retval HAL status
00883   */
00884 HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00885 {
00886   uint8_t  *pdata8bits;
00887   uint16_t *pdata16bits;
00888   uint16_t uhMask;
00889   uint32_t tickstart;
00890
00891   /* Check that a Rx process is not already ongoing */
00892   if (hirda->RxState == HAL_IRDA_STATE_READY)
00893   {
00894     if ((pData == NULL) || (Size == 0U))
00895     {
00896       return  HAL_ERROR;
00897     }
00898
00899     /* Process Locked */
00900     __HAL_LOCK(hirda);
00901
00902     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00903     hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
00904
00905     /* Init tickstart for timeout managment*/
00906     tickstart = HAL_GetTick();
00907
00908     hirda->RxXferSize = Size;
00909     hirda->RxXferCount = Size;
00910
00911     /* Computation of the mask to apply to RDR register
00912        of the UART associated to the IRDA */
00913     IRDA_MASK_COMPUTATION(hirda);
00914     uhMask = hirda->Mask;
00915
00916     /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
00917     if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
00918     {
00919       pdata8bits  = NULL;
00920       pdata16bits = (uint16_t *) pData; /* Derogation R.11.3 */
00921     }
00922     else
00923     {
00924       pdata8bits  = pData;
00925       pdata16bits = NULL;
00926     }
00927
00928     /* Check data remaining to be received */
00929     while (hirda->RxXferCount > 0U)
00930     {
00931       hirda->RxXferCount--;
00932
00933       if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
00934       {
00935         return HAL_TIMEOUT;
00936       }
00937       if (pdata8bits == NULL)
00938       {
00939         *pdata16bits = (uint16_t)(hirda->Instance->RDR & uhMask);
00940         pdata16bits++;
00941       }
00942       else
00943       {
00944         *pdata8bits = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
00945         pdata8bits++;
00946       }
00947     }
00948
00949     /* At end of Rx process, restore hirda->RxState to Ready */
00950     hirda->RxState = HAL_IRDA_STATE_READY;
00951
00952     /* Process Unlocked */
00953     __HAL_UNLOCK(hirda);
00954
00955     return HAL_OK;
00956   }
00957   else
00958   {
00959     return HAL_BUSY;
00960   }
00961 }
00962
00963 /**
00964   * @brief Send an amount of data in interrupt mode.
00965   * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
00966   *        the sent data is handled as a set of u16. In this case, Size must reflect the number
00967   *        of u16 available through pData.
00968   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
00969   *                the configuration information for the specified IRDA module.
00970   * @param pData Pointer to data buffer (u8 or u16 data elements).
00971   * @param Size Amount of data elements (u8 or u16) to be sent.
00972   * @retval HAL status
00973   */
00974 HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
00975 {
00976   /* Check that a Tx process is not already ongoing */
00977   if (hirda->gState == HAL_IRDA_STATE_READY)
00978   {
00979     if ((pData == NULL) || (Size == 0U))
00980     {
00981       return HAL_ERROR;
00982     }
00983
00984     /* Process Locked */
00985     __HAL_LOCK(hirda);
00986
00987     hirda->pTxBuffPtr = pData;
00988     hirda->TxXferSize = Size;
00989     hirda->TxXferCount = Size;
00990
00991     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00992     hirda->gState = HAL_IRDA_STATE_BUSY_TX;
00993
00994     /* Process Unlocked */
00995     __HAL_UNLOCK(hirda);
00996
00997     /* Enable the IRDA Transmit Data Register Empty Interrupt */
00998     SET_BIT(hirda->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
00999
01000     return HAL_OK;
01001   }
01002   else
01003   {
01004     return HAL_BUSY;
01005   }
01006 }
01007
01008 /**
01009   * @brief Receive an amount of data in interrupt mode.
01010   * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01011   *        the received data is handled as a set of u16. In this case, Size must reflect the number
01012   *        of u16 available through pData.
01013   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01014   *                the configuration information for the specified IRDA module.
01015   * @param pData Pointer to data buffer (u8 or u16 data elements).
01016   * @param Size Amount of data elements (u8 or u16) to be received.
01017   * @retval HAL status
01018   */
01019 HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
01020 {
01021   /* Check that a Rx process is not already ongoing */
01022   if (hirda->RxState == HAL_IRDA_STATE_READY)
01023   {
01024     if ((pData == NULL) || (Size == 0U))
01025     {
01026       return HAL_ERROR;
01027     }
01028
01029     /* Process Locked */
01030     __HAL_LOCK(hirda);
01031
01032     hirda->pRxBuffPtr = pData;
01033     hirda->RxXferSize = Size;
01034     hirda->RxXferCount = Size;
01035
01036     /* Computation of the mask to apply to the RDR register
01037        of the UART associated to the IRDA */
01038     IRDA_MASK_COMPUTATION(hirda);
01039
01040     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
01041     hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
01042
01043     /* Process Unlocked */
01044     __HAL_UNLOCK(hirda);
01045
01046     /* Enable the IRDA Parity Error and Data Register not empty Interrupts */
01047     SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
01048
01049     /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
01050     SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01051
01052     return HAL_OK;
01053   }
01054   else
01055   {
01056     return HAL_BUSY;
01057   }
01058 }
01059
01060 /**
01061   * @brief Send an amount of data in DMA mode.
01062   * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01063   *        the sent data is handled as a set of u16. In this case, Size must reflect the number
01064   *        of u16 available through pData.
01065   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
01066   *               the configuration information for the specified IRDA module.
01067   * @param pData pointer to data buffer (u8 or u16 data elements).
01068   * @param Size Amount of data elements (u8 or u16) to be sent.
01069   * @retval HAL status
01070   */
01071 HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
01072 {
01073   /* Check that a Tx process is not already ongoing */
01074   if (hirda->gState == HAL_IRDA_STATE_READY)
01075   {
01076     if ((pData == NULL) || (Size == 0U))
01077     {
01078       return HAL_ERROR;
01079     }
01080
01081     /* Process Locked */
01082     __HAL_LOCK(hirda);
01083
01084     hirda->pTxBuffPtr = pData;
01085     hirda->TxXferSize = Size;
01086     hirda->TxXferCount = Size;
01087
01088     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
01089     hirda->gState = HAL_IRDA_STATE_BUSY_TX;
01090
01091     /* Set the IRDA DMA transfer complete callback */
01092     hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
01093
01094     /* Set the IRDA DMA half transfer complete callback */
01095     hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
01096
01097     /* Set the DMA error callback */
01098     hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
01099
01100     /* Set the DMA abort callback */
01101     hirda->hdmatx->XferAbortCallback = NULL;
01102
01103     /* Enable the IRDA transmit DMA channel */
01104     if (HAL_DMA_Start_IT(hirda->hdmatx, (uint32_t)hirda->pTxBuffPtr, (uint32_t)&hirda->Instance->TDR, Size) == HAL_OK)
01105     {
01106       /* Clear the TC flag in the ICR register */
01107       __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_TCF);
01108
01109       /* Process Unlocked */
01110       __HAL_UNLOCK(hirda);
01111
01112       /* Enable the DMA transfer for transmit request by setting the DMAT bit
01113          in the USART CR3 register */
01114       SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01115
01116       return HAL_OK;
01117     }
01118     else
01119     {
01120       /* Set error code to DMA */
01121       hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
01122
01123       /* Process Unlocked */
01124       __HAL_UNLOCK(hirda);
01125
01126       /* Restore hirda->gState to ready */
01127       hirda->gState = HAL_IRDA_STATE_READY;
01128
01129       return HAL_ERROR;
01130     }
01131   }
01132   else
01133   {
01134     return HAL_BUSY;
01135   }
01136 }
01137
01138 /**
01139   * @brief Receive an amount of data in DMA mode.
01140   * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01141   *        the received data is handled as a set of u16. In this case, Size must reflect the number
01142   *        of u16 available through pData.
01143   * @note   When the IRDA parity is enabled (PCE = 1), the received data contains
01144   *         the parity bit (MSB position).
01145   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
01146   *               the configuration information for the specified IRDA module.
01147   * @param pData Pointer to data buffer (u8 or u16 data elements).
01148   * @param Size Amount of data elements (u8 or u16) to be received.
01149   * @retval HAL status
01150   */
01151 HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
01152 {
01153   /* Check that a Rx process is not already ongoing */
01154   if (hirda->RxState == HAL_IRDA_STATE_READY)
01155   {
01156     if ((pData == NULL) || (Size == 0U))
01157     {
01158       return HAL_ERROR;
01159     }
01160
01161     /* Process Locked */
01162     __HAL_LOCK(hirda);
01163
01164     hirda->pRxBuffPtr = pData;
01165     hirda->RxXferSize = Size;
01166
01167     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
01168     hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
01169
01170     /* Set the IRDA DMA transfer complete callback */
01171     hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
01172
01173     /* Set the IRDA DMA half transfer complete callback */
01174     hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
01175
01176     /* Set the DMA error callback */
01177     hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
01178
01179     /* Set the DMA abort callback */
01180     hirda->hdmarx->XferAbortCallback = NULL;
01181
01182     /* Enable the DMA channel */
01183     if (HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, (uint32_t)hirda->pRxBuffPtr, Size) == HAL_OK)
01184     {
01185       /* Process Unlocked */
01186       __HAL_UNLOCK(hirda);
01187
01188       /* Enable the UART Parity Error Interrupt */
01189       SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
01190
01191       /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
01192       SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01193
01194       /* Enable the DMA transfer for the receiver request by setting the DMAR bit
01195          in the USART CR3 register */
01196       SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01197
01198       return HAL_OK;
01199     }
01200     else
01201     {
01202       /* Set error code to DMA */
01203       hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
01204
01205       /* Process Unlocked */
01206       __HAL_UNLOCK(hirda);
01207
01208       /* Restore hirda->RxState to ready */
01209       hirda->RxState = HAL_IRDA_STATE_READY;
01210
01211       return HAL_ERROR;
01212     }
01213   }
01214   else
01215   {
01216     return HAL_BUSY;
01217   }
01218 }
01219
01220
01221 /**
01222   * @brief Pause the DMA Transfer.
01223   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01224   *                the configuration information for the specified IRDA module.
01225   * @retval HAL status
01226   */
01227 HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
01228 {
01229   /* Process Locked */
01230   __HAL_LOCK(hirda);
01231
01232   if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
01233   {
01234     if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01235     {
01236       /* Disable the IRDA DMA Tx request */
01237       CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01238     }
01239   }
01240   if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
01241   {
01242     if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01243     {
01244       /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
01245       CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
01246       CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01247
01248       /* Disable the IRDA DMA Rx request */
01249       CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01250     }
01251   }
01252
01253   /* Process Unlocked */
01254   __HAL_UNLOCK(hirda);
01255
01256   return HAL_OK;
01257 }
01258
01259 /**
01260   * @brief Resume the DMA Transfer.
01261   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01262   *                the configuration information for the specified UART module.
01263   * @retval HAL status
01264   */
01265 HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
01266 {
01267   /* Process Locked */
01268   __HAL_LOCK(hirda);
01269
01270   if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
01271   {
01272     /* Enable the IRDA DMA Tx request */
01273     SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01274   }
01275   if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
01276   {
01277     /* Clear the Overrun flag before resuming the Rx transfer*/
01278     __HAL_IRDA_CLEAR_OREFLAG(hirda);
01279
01280     /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
01281     SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
01282     SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01283
01284     /* Enable the IRDA DMA Rx request */
01285     SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01286   }
01287
01288   /* Process Unlocked */
01289   __HAL_UNLOCK(hirda);
01290
01291   return HAL_OK;
01292 }
01293
01294 /**
01295   * @brief Stop the DMA Transfer.
01296   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01297   *                the configuration information for the specified UART module.
01298   * @retval HAL status
01299   */
01300 HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
01301 {
01302   /* The Lock is not implemented on this API to allow the user application
01303      to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() /
01304      HAL_IRDA_TxHalfCpltCallback / HAL_IRDA_RxHalfCpltCallback:
01305      indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
01306      interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
01307      the stream and the corresponding call back is executed. */
01308
01309   /* Stop IRDA DMA Tx request if ongoing */
01310   if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
01311   {
01312     if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01313     {
01314       CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01315
01316       /* Abort the IRDA DMA Tx channel */
01317       if (hirda->hdmatx != NULL)
01318       {
01319         if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK)
01320         {
01321           if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
01322           {
01323             /* Set error code to DMA */
01324             hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
01325
01326             return HAL_TIMEOUT;
01327           }
01328         }
01329       }
01330
01331       IRDA_EndTxTransfer(hirda);
01332     }
01333   }
01334
01335   /* Stop IRDA DMA Rx request if ongoing */
01336   if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
01337   {
01338     if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01339     {
01340       CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01341
01342       /* Abort the IRDA DMA Rx channel */
01343       if (hirda->hdmarx != NULL)
01344       {
01345         if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK)
01346         {
01347           if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
01348           {
01349             /* Set error code to DMA */
01350             hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
01351
01352             return HAL_TIMEOUT;
01353           }
01354         }
01355       }
01356
01357       IRDA_EndRxTransfer(hirda);
01358     }
01359   }
01360
01361   return HAL_OK;
01362 }
01363
01364 /**
01365   * @brief  Abort ongoing transfers (blocking mode).
01366   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01367   *               the configuration information for the specified UART module.
01368   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01369   *         This procedure performs following operations :
01370   *           - Disable IRDA Interrupts (Tx and Rx)
01371   *           - Disable the DMA transfer in the peripheral register (if enabled)
01372   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01373   *           - Set handle State to READY
01374   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01375   * @retval HAL status
01376 */
01377 HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
01378 {
01379   /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01380   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
01381   CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01382
01383   /* Disable the IRDA DMA Tx request if enabled */
01384   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01385   {
01386     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01387
01388     /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
01389     if (hirda->hdmatx != NULL)
01390     {
01391       /* Set the IRDA DMA Abort callback to Null.
01392          No call back execution at end of DMA abort procedure */
01393       hirda->hdmatx->XferAbortCallback = NULL;
01394
01395       if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK)
01396       {
01397         if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
01398         {
01399           /* Set error code to DMA */
01400           hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
01401
01402           return HAL_TIMEOUT;
01403         }
01404       }
01405     }
01406   }
01407
01408   /* Disable the IRDA DMA Rx request if enabled */
01409   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01410   {
01411     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01412
01413     /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
01414     if (hirda->hdmarx != NULL)
01415     {
01416       /* Set the IRDA DMA Abort callback to Null.
01417          No call back execution at end of DMA abort procedure */
01418       hirda->hdmarx->XferAbortCallback = NULL;
01419
01420       if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK)
01421       {
01422         if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
01423         {
01424           /* Set error code to DMA */
01425           hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
01426
01427           return HAL_TIMEOUT;
01428         }
01429       }
01430     }
01431   }
01432
01433   /* Reset Tx and Rx transfer counters */
01434   hirda->TxXferCount = 0U;
01435   hirda->RxXferCount = 0U;
01436
01437   /* Clear the Error flags in the ICR register */
01438   __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
01439
01440   /* Restore hirda->gState and hirda->RxState to Ready */
01441   hirda->gState  = HAL_IRDA_STATE_READY;
01442   hirda->RxState = HAL_IRDA_STATE_READY;
01443
01444   /* Reset Handle ErrorCode to No Error */
01445   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
01446
01447   return HAL_OK;
01448 }
01449
01450 /**
01451   * @brief  Abort ongoing Transmit transfer (blocking mode).
01452   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01453   *               the configuration information for the specified UART module.
01454   * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
01455   *         This procedure performs following operations :
01456   *           - Disable IRDA Interrupts (Tx)
01457   *           - Disable the DMA transfer in the peripheral register (if enabled)
01458   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01459   *           - Set handle State to READY
01460   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01461   * @retval HAL status
01462 */
01463 HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda)
01464 {
01465   /* Disable TXEIE and TCIE interrupts */
01466   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
01467
01468   /* Disable the IRDA DMA Tx request if enabled */
01469   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01470   {
01471     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01472
01473     /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
01474     if (hirda->hdmatx != NULL)
01475     {
01476       /* Set the IRDA DMA Abort callback to Null.
01477          No call back execution at end of DMA abort procedure */
01478       hirda->hdmatx->XferAbortCallback = NULL;
01479
01480       if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK)
01481       {
01482         if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
01483         {
01484           /* Set error code to DMA */
01485           hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
01486
01487           return HAL_TIMEOUT;
01488         }
01489       }
01490     }
01491   }
01492
01493   /* Reset Tx transfer counter */
01494   hirda->TxXferCount = 0U;
01495
01496   /* Restore hirda->gState to Ready */
01497   hirda->gState = HAL_IRDA_STATE_READY;
01498
01499   return HAL_OK;
01500 }
01501
01502 /**
01503   * @brief  Abort ongoing Receive transfer (blocking mode).
01504   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01505   *               the configuration information for the specified UART module.
01506   * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
01507   *         This procedure performs following operations :
01508   *           - Disable IRDA Interrupts (Rx)
01509   *           - Disable the DMA transfer in the peripheral register (if enabled)
01510   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01511   *           - Set handle State to READY
01512   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01513   * @retval HAL status
01514 */
01515 HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda)
01516 {
01517   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01518   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
01519   CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01520
01521   /* Disable the IRDA DMA Rx request if enabled */
01522   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01523   {
01524     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01525
01526     /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
01527     if (hirda->hdmarx != NULL)
01528     {
01529       /* Set the IRDA DMA Abort callback to Null.
01530          No call back execution at end of DMA abort procedure */
01531       hirda->hdmarx->XferAbortCallback = NULL;
01532
01533       if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK)
01534       {
01535         if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
01536         {
01537           /* Set error code to DMA */
01538           hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
01539
01540           return HAL_TIMEOUT;
01541         }
01542       }
01543     }
01544   }
01545
01546   /* Reset Rx transfer counter */
01547   hirda->RxXferCount = 0U;
01548
01549   /* Clear the Error flags in the ICR register */
01550   __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
01551
01552   /* Restore hirda->RxState to Ready */
01553   hirda->RxState = HAL_IRDA_STATE_READY;
01554
01555   return HAL_OK;
01556 }
01557
01558 /**
01559   * @brief  Abort ongoing transfers (Interrupt mode).
01560   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01561   *               the configuration information for the specified UART module.
01562   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01563   *         This procedure performs following operations :
01564   *           - Disable IRDA Interrupts (Tx and Rx)
01565   *           - Disable the DMA transfer in the peripheral register (if enabled)
01566   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01567   *           - Set handle State to READY
01568   *           - At abort completion, call user abort complete callback
01569   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01570   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01571   * @retval HAL status
01572 */
01573 HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
01574 {
01575   uint32_t abortcplt = 1U;
01576
01577   /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01578   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
01579   CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01580
01581   /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised
01582      before any call to DMA Abort functions */
01583   /* DMA Tx Handle is valid */
01584   if (hirda->hdmatx != NULL)
01585   {
01586     /* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled.
01587        Otherwise, set it to NULL */
01588     if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01589     {
01590       hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback;
01591     }
01592     else
01593     {
01594       hirda->hdmatx->XferAbortCallback = NULL;
01595     }
01596   }
01597   /* DMA Rx Handle is valid */
01598   if (hirda->hdmarx != NULL)
01599   {
01600     /* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled.
01601        Otherwise, set it to NULL */
01602     if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01603     {
01604       hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback;
01605     }
01606     else
01607     {
01608       hirda->hdmarx->XferAbortCallback = NULL;
01609     }
01610   }
01611
01612   /* Disable the IRDA DMA Tx request if enabled */
01613   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01614   {
01615     /* Disable DMA Tx at UART level */
01616     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01617
01618     /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
01619     if (hirda->hdmatx != NULL)
01620     {
01621       /* IRDA Tx DMA Abort callback has already been initialised :
01622          will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
01623
01624       /* Abort DMA TX */
01625       if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
01626       {
01627         hirda->hdmatx->XferAbortCallback = NULL;
01628       }
01629       else
01630       {
01631         abortcplt = 0U;
01632       }
01633     }
01634   }
01635
01636   /* Disable the IRDA DMA Rx request if enabled */
01637   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01638   {
01639     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01640
01641     /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
01642     if (hirda->hdmarx != NULL)
01643     {
01644       /* IRDA Rx DMA Abort callback has already been initialised :
01645          will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
01646
01647       /* Abort DMA RX */
01648       if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
01649       {
01650         hirda->hdmarx->XferAbortCallback = NULL;
01651         abortcplt = 1U;
01652       }
01653       else
01654       {
01655         abortcplt = 0U;
01656       }
01657     }
01658   }
01659
01660   /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
01661   if (abortcplt == 1U)
01662   {
01663     /* Reset Tx and Rx transfer counters */
01664     hirda->TxXferCount = 0U;
01665     hirda->RxXferCount = 0U;
01666
01667     /* Reset errorCode */
01668     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
01669
01670     /* Clear the Error flags in the ICR register */
01671     __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
01672
01673     /* Restore hirda->gState and hirda->RxState to Ready */
01674     hirda->gState  = HAL_IRDA_STATE_READY;
01675     hirda->RxState = HAL_IRDA_STATE_READY;
01676
01677     /* As no DMA to be aborted, call directly user Abort complete callback */
01678 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
01679     /* Call registered Abort complete callback */
01680     hirda->AbortCpltCallback(hirda);
01681 #else
01682     /* Call legacy weak Abort complete callback */
01683     HAL_IRDA_AbortCpltCallback(hirda);
01684 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
01685   }
01686
01687   return HAL_OK;
01688 }
01689
01690 /**
01691   * @brief  Abort ongoing Transmit transfer (Interrupt mode).
01692   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01693   *               the configuration information for the specified UART module.
01694   * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
01695   *         This procedure performs following operations :
01696   *           - Disable IRDA Interrupts (Tx)
01697   *           - Disable the DMA transfer in the peripheral register (if enabled)
01698   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01699   *           - Set handle State to READY
01700   *           - At abort completion, call user abort complete callback
01701   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01702   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01703   * @retval HAL status
01704 */
01705 HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
01706 {
01707   /* Disable TXEIE and TCIE interrupts */
01708   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
01709
01710   /* Disable the IRDA DMA Tx request if enabled */
01711   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01712   {
01713     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01714
01715     /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
01716     if (hirda->hdmatx != NULL)
01717     {
01718       /* Set the IRDA DMA Abort callback :
01719          will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
01720       hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback;
01721
01722       /* Abort DMA TX */
01723       if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
01724       {
01725         /* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */
01726         hirda->hdmatx->XferAbortCallback(hirda->hdmatx);
01727       }
01728     }
01729     else
01730     {
01731       /* Reset Tx transfer counter */
01732       hirda->TxXferCount = 0U;
01733
01734       /* Restore hirda->gState to Ready */
01735       hirda->gState = HAL_IRDA_STATE_READY;
01736
01737       /* As no DMA to be aborted, call directly user Abort complete callback */
01738 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
01739       /* Call registered Abort Transmit Complete Callback */
01740       hirda->AbortTransmitCpltCallback(hirda);
01741 #else
01742       /* Call legacy weak Abort Transmit Complete Callback */
01743       HAL_IRDA_AbortTransmitCpltCallback(hirda);
01744 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
01745     }
01746   }
01747   else
01748   {
01749     /* Reset Tx transfer counter */
01750     hirda->TxXferCount = 0U;
01751
01752     /* Restore hirda->gState to Ready */
01753     hirda->gState = HAL_IRDA_STATE_READY;
01754
01755     /* As no DMA to be aborted, call directly user Abort complete callback */
01756 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
01757     /* Call registered Abort Transmit Complete Callback */
01758     hirda->AbortTransmitCpltCallback(hirda);
01759 #else
01760     /* Call legacy weak Abort Transmit Complete Callback */
01761     HAL_IRDA_AbortTransmitCpltCallback(hirda);
01762 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
01763   }
01764
01765   return HAL_OK;
01766 }
01767
01768 /**
01769   * @brief  Abort ongoing Receive transfer (Interrupt mode).
01770   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
01771   *               the configuration information for the specified UART module.
01772   * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
01773   *         This procedure performs following operations :
01774   *           - Disable IRDA Interrupts (Rx)
01775   *           - Disable the DMA transfer in the peripheral register (if enabled)
01776   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01777   *           - Set handle State to READY
01778   *           - At abort completion, call user abort complete callback
01779   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01780   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01781   * @retval HAL status
01782 */
01783 HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
01784 {
01785   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01786   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
01787   CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01788
01789   /* Disable the IRDA DMA Rx request if enabled */
01790   if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01791   {
01792     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01793
01794     /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
01795     if (hirda->hdmarx != NULL)
01796     {
01797       /* Set the IRDA DMA Abort callback :
01798          will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
01799       hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback;
01800
01801       /* Abort DMA RX */
01802       if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
01803       {
01804         /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
01805         hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
01806       }
01807     }
01808     else
01809     {
01810       /* Reset Rx transfer counter */
01811       hirda->RxXferCount = 0U;
01812
01813       /* Clear the Error flags in the ICR register */
01814       __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
01815
01816       /* Restore hirda->RxState to Ready */
01817       hirda->RxState = HAL_IRDA_STATE_READY;
01818
01819       /* As no DMA to be aborted, call directly user Abort complete callback */
01820 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
01821       /* Call registered Abort Receive Complete Callback */
01822       hirda->AbortReceiveCpltCallback(hirda);
01823 #else
01824       /* Call legacy weak Abort Receive Complete Callback */
01825       HAL_IRDA_AbortReceiveCpltCallback(hirda);
01826 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
01827     }
01828   }
01829   else
01830   {
01831     /* Reset Rx transfer counter */
01832     hirda->RxXferCount = 0U;
01833
01834     /* Clear the Error flags in the ICR register */
01835     __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
01836
01837     /* Restore hirda->RxState to Ready */
01838     hirda->RxState = HAL_IRDA_STATE_READY;
01839
01840     /* As no DMA to be aborted, call directly user Abort complete callback */
01841 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
01842     /* Call registered Abort Receive Complete Callback */
01843     hirda->AbortReceiveCpltCallback(hirda);
01844 #else
01845     /* Call legacy weak Abort Receive Complete Callback */
01846     HAL_IRDA_AbortReceiveCpltCallback(hirda);
01847 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
01848   }
01849
01850   return HAL_OK;
01851 }
01852
01853 /**
01854   * @brief Handle IRDA interrupt request.
01855   * @param hirda  Pointer to a IRDA_HandleTypeDef structure that contains
01856   *               the configuration information for the specified IRDA module.
01857   * @retval None
01858   */
01859 void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
01860 {
01861   uint32_t isrflags   = READ_REG(hirda->Instance->ISR);
01862   uint32_t cr1its     = READ_REG(hirda->Instance->CR1);
01863   uint32_t cr3its;
01864   uint32_t errorflags;
01865
01866   /* If no error occurs */
01867   errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
01868   if (errorflags == 0U)
01869   {
01870     /* IRDA in mode Receiver ---------------------------------------------------*/
01871     if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) && ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U))
01872     {
01873       IRDA_Receive_IT(hirda);
01874       return;
01875     }
01876   }
01877
01878   /* If some errors occur */
01879   cr3its = READ_REG(hirda->Instance->CR3);
01880   if ((errorflags != 0U)
01881       && (((cr3its & USART_CR3_EIE) != 0U)
01882           || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U)))
01883   {
01884     /* IRDA parity error interrupt occurred -------------------------------------*/
01885     if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
01886     {
01887       __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF);
01888
01889       hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
01890     }
01891
01892     /* IRDA frame error interrupt occurred --------------------------------------*/
01893     if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
01894     {
01895       __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF);
01896
01897       hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
01898     }
01899
01900     /* IRDA noise error interrupt occurred --------------------------------------*/
01901     if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
01902     {
01903       __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF);
01904
01905       hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
01906     }
01907
01908     /* IRDA Over-Run interrupt occurred -----------------------------------------*/
01909     if (((isrflags & USART_ISR_ORE) != 0U) &&
01910         (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || ((cr3its & USART_CR3_EIE) != 0U)))
01911     {
01912       __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);
01913
01914       hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
01915     }
01916
01917     /* Call IRDA Error Call back function if need be --------------------------*/
01918     if (hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
01919     {
01920       /* IRDA in mode Receiver ---------------------------------------------------*/
01921       if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) && ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U))
01922       {
01923         IRDA_Receive_IT(hirda);
01924       }
01925
01926       /* If Overrun error occurs, or if any error occurs in DMA mode reception,
01927          consider error as blocking */
01928       if ((HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) ||
01929           ((hirda->ErrorCode & HAL_IRDA_ERROR_ORE) != 0U))
01930       {
01931         /* Blocking error : transfer is aborted
01932            Set the IRDA state ready to be able to start again the process,
01933            Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
01934         IRDA_EndRxTransfer(hirda);
01935
01936         /* Disable the IRDA DMA Rx request if enabled */
01937         if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01938         {
01939           CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01940
01941           /* Abort the IRDA DMA Rx channel */
01942           if (hirda->hdmarx != NULL)
01943           {
01944             /* Set the IRDA DMA Abort callback :
01945                will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */
01946             hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError;
01947
01948             /* Abort DMA RX */
01949             if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
01950             {
01951               /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
01952               hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
01953             }
01954           }
01955           else
01956           {
01957 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
01958             /* Call registered user error callback */
01959             hirda->ErrorCallback(hirda);
01960 #else
01961             /* Call legacy weak user error callback */
01962             HAL_IRDA_ErrorCallback(hirda);
01963 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
01964           }
01965         }
01966         else
01967         {
01968 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
01969           /* Call registered user error callback */
01970           hirda->ErrorCallback(hirda);
01971 #else
01972           /* Call legacy weak user error callback */
01973           HAL_IRDA_ErrorCallback(hirda);
01974 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
01975         }
01976       }
01977       else
01978       {
01979         /* Non Blocking error : transfer could go on.
01980            Error is notified to user through user error callback */
01981 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
01982         /* Call registered user error callback */
01983         hirda->ErrorCallback(hirda);
01984 #else
01985         /* Call legacy weak user error callback */
01986         HAL_IRDA_ErrorCallback(hirda);
01987 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
01988         hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
01989       }
01990     }
01991     return;
01992
01993   } /* End if some error occurs */
01994
01995   /* IRDA in mode Transmitter ------------------------------------------------*/
01996   if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) && ((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U))
01997   {
01998     IRDA_Transmit_IT(hirda);
01999     return;
02000   }
02001
02002   /* IRDA in mode Transmitter (transmission end) -----------------------------*/
02003   if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
02004   {
02005     IRDA_EndTransmit_IT(hirda);
02006     return;
02007   }
02008
02009 }
02010
02011 /**
02012   * @brief  Tx Transfer completed callback.
02013   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02014   *               the configuration information for the specified IRDA module.
02015   * @retval None
02016   */
02017 __weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
02018 {
02019   /* Prevent unused argument(s) compilation warning */
02020   UNUSED(hirda);
02021
02022   /* NOTE : This function should not be modified, when the callback is needed,
02023             the HAL_IRDA_TxCpltCallback can be implemented in the user file.
02024    */
02025 }
02026
02027 /**
02028   * @brief  Tx Half Transfer completed callback.
02029   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02030   *               the configuration information for the specified USART module.
02031   * @retval None
02032   */
02033 __weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
02034 {
02035   /* Prevent unused argument(s) compilation warning */
02036   UNUSED(hirda);
02037
02038   /* NOTE : This function should not be modified, when the callback is needed,
02039             the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file.
02040    */
02041 }
02042
02043 /**
02044   * @brief  Rx Transfer completed callback.
02045   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02046   *               the configuration information for the specified IRDA module.
02047   * @retval None
02048   */
02049 __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
02050 {
02051   /* Prevent unused argument(s) compilation warning */
02052   UNUSED(hirda);
02053
02054   /* NOTE : This function should not be modified, when the callback is needed,
02055             the HAL_IRDA_RxCpltCallback can be implemented in the user file.
02056    */
02057 }
02058
02059 /**
02060   * @brief  Rx Half Transfer complete callback.
02061   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02062   *               the configuration information for the specified IRDA module.
02063   * @retval None
02064   */
02065 __weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
02066 {
02067   /* Prevent unused argument(s) compilation warning */
02068   UNUSED(hirda);
02069
02070   /* NOTE : This function should not be modified, when the callback is needed,
02071             the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file.
02072    */
02073 }
02074
02075 /**
02076   * @brief  IRDA error callback.
02077   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02078   *               the configuration information for the specified IRDA module.
02079   * @retval None
02080   */
02081 __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
02082 {
02083   /* Prevent unused argument(s) compilation warning */
02084   UNUSED(hirda);
02085
02086   /* NOTE : This function should not be modified, when the callback is needed,
02087             the HAL_IRDA_ErrorCallback can be implemented in the user file.
02088    */
02089 }
02090
02091 /**
02092   * @brief  IRDA Abort Complete callback.
02093   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02094   *               the configuration information for the specified IRDA module.
02095   * @retval None
02096   */
02097 __weak void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda)
02098 {
02099   /* Prevent unused argument(s) compilation warning */
02100   UNUSED(hirda);
02101
02102   /* NOTE : This function should not be modified, when the callback is needed,
02103             the HAL_IRDA_AbortCpltCallback can be implemented in the user file.
02104    */
02105 }
02106
02107 /**
02108   * @brief  IRDA Abort Complete callback.
02109   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02110   *               the configuration information for the specified IRDA module.
02111   * @retval None
02112   */
02113 __weak void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda)
02114 {
02115   /* Prevent unused argument(s) compilation warning */
02116   UNUSED(hirda);
02117
02118   /* NOTE : This function should not be modified, when the callback is needed,
02119             the HAL_IRDA_AbortTransmitCpltCallback can be implemented in the user file.
02120    */
02121 }
02122
02123 /**
02124   * @brief  IRDA Abort Receive Complete callback.
02125   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02126   *               the configuration information for the specified IRDA module.
02127   * @retval None
02128   */
02129 __weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda)
02130 {
02131   /* Prevent unused argument(s) compilation warning */
02132   UNUSED(hirda);
02133
02134   /* NOTE : This function should not be modified, when the callback is needed,
02135             the HAL_IRDA_AbortReceiveCpltCallback can be implemented in the user file.
02136    */
02137 }
02138
02139 /**
02140   * @}
02141   */
02142
02143 /** @defgroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
02144   *  @brief   IRDA State and Errors functions
02145   *
02146 @verbatim
02147   ==============================================================================
02148             ##### Peripheral State and Error functions #####
02149   ==============================================================================
02150   [..]
02151     This subsection provides a set of functions allowing to return the State of IrDA
02152     communication process and also return Peripheral Errors occurred during communication process
02153      (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state
02154          of the IRDA peripheral handle.
02155      (+) HAL_IRDA_GetError() checks in run-time errors that could occur during
02156          communication.
02157
02158 @endverbatim
02159   * @{
02160   */
02161
02162 /**
02163   * @brief Return the IRDA handle state.
02164   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
02165   *                the configuration information for the specified IRDA module.
02166   * @retval HAL state
02167   */
02168 HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
02169 {
02170   /* Return IRDA handle state */
02171   uint32_t temp1, temp2;
02172   temp1 = (uint32_t)hirda->gState;
02173   temp2 = (uint32_t)hirda->RxState;
02174
02175   return (HAL_IRDA_StateTypeDef)(temp1 | temp2);
02176 }
02177
02178 /**
02179   * @brief Return the IRDA handle error code.
02180   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
02181   *               the configuration information for the specified IRDA module.
02182   * @retval IRDA Error Code
02183   */
02184 uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
02185 {
02186   return hirda->ErrorCode;
02187 }
02188
02189 /**
02190   * @}
02191   */
02192
02193 /**
02194   * @}
02195   */
02196
02197 /** @defgroup IRDA_Private_Functions IRDA Private Functions
02198   * @{
02199   */
02200
02201 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02202 /**
02203   * @brief  Initialize the callbacks to their default values.
02204   * @param  hirda IRDA handle.
02205   * @retval none
02206   */
02207 void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda)
02208 {
02209   /* Init the IRDA Callback settings */
02210   hirda->TxHalfCpltCallback        = HAL_IRDA_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback        */
02211   hirda->TxCpltCallback            = HAL_IRDA_TxCpltCallback;            /* Legacy weak TxCpltCallback            */
02212   hirda->RxHalfCpltCallback        = HAL_IRDA_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback        */
02213   hirda->RxCpltCallback            = HAL_IRDA_RxCpltCallback;            /* Legacy weak RxCpltCallback            */
02214   hirda->ErrorCallback             = HAL_IRDA_ErrorCallback;             /* Legacy weak ErrorCallback             */
02215   hirda->AbortCpltCallback         = HAL_IRDA_AbortCpltCallback;         /* Legacy weak AbortCpltCallback         */
02216   hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
02217   hirda->AbortReceiveCpltCallback  = HAL_IRDA_AbortReceiveCpltCallback;  /* Legacy weak AbortReceiveCpltCallback  */
02218
02219 }
02220 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
02221
02222 /**
02223   * @brief Configure the IRDA peripheral.
02224   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
02225   *               the configuration information for the specified IRDA module.
02226   * @retval HAL status
02227   */
02228 static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
02229 {
02230   uint32_t tmpreg;
02231   IRDA_ClockSourceTypeDef clocksource;
02232   HAL_StatusTypeDef ret               = HAL_OK;
02233   const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
02234   uint32_t pclk;
02235
02236   /* Check the communication parameters */
02237   assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
02238   assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
02239   assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
02240   assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode));
02241   assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler));
02242   assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode));
02243   assert_param(IS_IRDA_CLOCKPRESCALER(hirda->Init.ClockPrescaler));
02244
02245   /*-------------------------- USART CR1 Configuration -----------------------*/
02246   /* Configure the IRDA Word Length, Parity and transfer Mode:
02247      Set the M bits according to hirda->Init.WordLength value
02248      Set PCE and PS bits according to hirda->Init.Parity value
02249      Set TE and RE bits according to hirda->Init.Mode value */
02250   tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ;
02251
02252   MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg);
02253
02254   /*-------------------------- USART CR3 Configuration -----------------------*/
02255   MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode);
02256
02257   /*--------------------- USART clock PRESC Configuration ----------------*/
02258   /* Configure
02259   * - IRDA Clock Prescaler: set PRESCALER according to hirda->Init.ClockPrescaler value */
02260   MODIFY_REG(hirda->Instance->PRESC, USART_PRESC_PRESCALER, hirda->Init.ClockPrescaler);
02261
02262   /*-------------------------- USART GTPR Configuration ----------------------*/
02263   MODIFY_REG(hirda->Instance->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)hirda->Init.Prescaler);
02264
02265   /*-------------------------- USART BRR Configuration -----------------------*/
02266   IRDA_GETCLOCKSOURCE(hirda, clocksource);
02267   tmpreg =   0U;
02268   switch (clocksource)
02269   {
02270     case IRDA_CLOCKSOURCE_PCLK2:
02271       pclk = HAL_RCC_GetPCLK2Freq();
02272       tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
02273       break;
02274     case IRDA_CLOCKSOURCE_HSI:
02275       tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
02276       break;
02277     case IRDA_CLOCKSOURCE_SYSCLK:
02278       pclk = HAL_RCC_GetSysClockFreq();
02279       tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
02280       break;
02281     case IRDA_CLOCKSOURCE_LSE:
02282       tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
02283       break;
02284     default:
02285       ret = HAL_ERROR;
02286       break;
02287   }
02288
02289   /* USARTDIV must be greater than or equal to 0d16 */
02290   if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX))
02291   {
02292     hirda->Instance->BRR = tmpreg;
02293   }
02294   else
02295   {
02296     ret = HAL_ERROR;
02297   }
02298
02299   return ret;
02300 }
02301
02302 /**
02303   * @brief Check the IRDA Idle State.
02304   * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
02305   *               the configuration information for the specified IRDA module.
02306   * @retval HAL status
02307   */
02308 static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
02309 {
02310   uint32_t tickstart;
02311
02312   /* Initialize the IRDA ErrorCode */
02313   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
02314
02315   /* Init tickstart for timeout managment*/
02316   tickstart = HAL_GetTick();
02317
02318   /* Check if the Transmitter is enabled */
02319   if ((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
02320   {
02321     /* Wait until TEACK flag is set */
02322     if (IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
02323     {
02324       /* Timeout occurred */
02325       return HAL_TIMEOUT;
02326     }
02327   }
02328   /* Check if the Receiver is enabled */
02329   if ((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
02330   {
02331     /* Wait until REACK flag is set */
02332     if (IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
02333     {
02334       /* Timeout occurred */
02335       return HAL_TIMEOUT;
02336     }
02337   }
02338
02339   /* Initialize the IRDA state*/
02340   hirda->gState  = HAL_IRDA_STATE_READY;
02341   hirda->RxState = HAL_IRDA_STATE_READY;
02342
02343   /* Process Unlocked */
02344   __HAL_UNLOCK(hirda);
02345
02346   return HAL_OK;
02347 }
02348
02349 /**
02350   * @brief  Handle IRDA Communication Timeout.
02351   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02352   *               the configuration information for the specified IRDA module.
02353   * @param  Flag Specifies the IRDA flag to check.
02354   * @param  Status Flag status (SET or RESET)
02355   * @param  Tickstart Tick start value
02356   * @param  Timeout Timeout duration
02357   * @retval HAL status
02358   */
02359 static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
02360 {
02361   /* Wait until flag is set */
02362   while ((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
02363   {
02364     /* Check for the Timeout */
02365     if (Timeout != HAL_MAX_DELAY)
02366     {
02367       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
02368       {
02369         /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
02370         CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
02371         CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
02372
02373         hirda->gState  = HAL_IRDA_STATE_READY;
02374         hirda->RxState = HAL_IRDA_STATE_READY;
02375
02376         /* Process Unlocked */
02377         __HAL_UNLOCK(hirda);
02378         return HAL_TIMEOUT;
02379       }
02380     }
02381   }
02382   return HAL_OK;
02383 }
02384
02385
02386 /**
02387   * @brief  End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
02388   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02389   *               the configuration information for the specified IRDA module.
02390   * @retval None
02391   */
02392 static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)
02393 {
02394   /* Disable TXEIE and TCIE interrupts */
02395   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
02396
02397   /* At end of Tx process, restore hirda->gState to Ready */
02398   hirda->gState = HAL_IRDA_STATE_READY;
02399 }
02400
02401
02402 /**
02403   * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
02404   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02405   *               the configuration information for the specified IRDA module.
02406   * @retval None
02407   */
02408 static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)
02409 {
02410   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
02411   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
02412   CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
02413
02414   /* At end of Rx process, restore hirda->RxState to Ready */
02415   hirda->RxState = HAL_IRDA_STATE_READY;
02416 }
02417
02418
02419 /**
02420   * @brief  DMA IRDA transmit process complete callback.
02421   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
02422   *              the configuration information for the specified DMA module.
02423   * @retval None
02424   */
02425 static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
02426 {
02427   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
02428
02429   /* DMA Normal mode */
02430   if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
02431   {
02432     hirda->TxXferCount = 0U;
02433
02434     /* Disable the DMA transfer for transmit request by resetting the DMAT bit
02435        in the IRDA CR3 register */
02436     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
02437
02438     /* Enable the IRDA Transmit Complete Interrupt */
02439     SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
02440   }
02441   /* DMA Circular mode */
02442   else
02443   {
02444 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02445     /* Call registered Tx complete callback */
02446     hirda->TxCpltCallback(hirda);
02447 #else
02448     /* Call legacy weak Tx complete callback */
02449     HAL_IRDA_TxCpltCallback(hirda);
02450 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02451   }
02452
02453 }
02454
02455 /**
02456   * @brief  DMA IRDA transmit process half complete callback.
02457   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
02458   *              the configuration information for the specified DMA module.
02459   * @retval None
02460   */
02461 static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
02462 {
02463   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
02464
02465 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02466   /* Call registered Tx Half complete callback */
02467   hirda->TxHalfCpltCallback(hirda);
02468 #else
02469   /* Call legacy weak Tx complete callback */
02470   HAL_IRDA_TxHalfCpltCallback(hirda);
02471 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02472 }
02473
02474 /**
02475   * @brief  DMA IRDA receive process complete callback.
02476   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
02477   *               the configuration information for the specified DMA module.
02478   * @retval None
02479   */
02480 static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
02481 {
02482   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
02483
02484   /* DMA Normal mode */
02485   if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
02486   {
02487     hirda->RxXferCount = 0U;
02488
02489     /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
02490     CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
02491     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
02492
02493     /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
02494        in the IRDA CR3 register */
02495     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
02496
02497     /* At end of Rx process, restore hirda->RxState to Ready */
02498     hirda->RxState = HAL_IRDA_STATE_READY;
02499   }
02500
02501 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02502   /* Call registered Rx complete callback */
02503   hirda->RxCpltCallback(hirda);
02504 #else
02505   /* Call legacy weak Rx complete callback */
02506   HAL_IRDA_RxCpltCallback(hirda);
02507 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
02508 }
02509
02510 /**
02511   * @brief DMA IRDA receive process half complete callback.
02512   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
02513   *              the configuration information for the specified DMA module.
02514   * @retval None
02515   */
02516 static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
02517 {
02518   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
02519
02520 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02521   /*Call registered Rx Half complete callback*/
02522   hirda->RxHalfCpltCallback(hirda);
02523 #else
02524   /* Call legacy weak Rx Half complete callback */
02525   HAL_IRDA_RxHalfCpltCallback(hirda);
02526 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02527 }
02528
02529 /**
02530   * @brief DMA IRDA communication error callback.
02531   * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
02532   *              the configuration information for the specified DMA module.
02533   * @retval None
02534   */
02535 static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
02536 {
02537   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
02538
02539   /* Stop IRDA DMA Tx request if ongoing */
02540   if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
02541   {
02542     if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
02543     {
02544       hirda->TxXferCount = 0U;
02545       IRDA_EndTxTransfer(hirda);
02546     }
02547   }
02548
02549   /* Stop IRDA DMA Rx request if ongoing */
02550   if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
02551   {
02552     if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
02553     {
02554       hirda->RxXferCount = 0U;
02555       IRDA_EndRxTransfer(hirda);
02556     }
02557   }
02558
02559   hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
02560 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02561   /* Call registered user error callback */
02562   hirda->ErrorCallback(hirda);
02563 #else
02564   /* Call legacy weak user error callback */
02565   HAL_IRDA_ErrorCallback(hirda);
02566 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02567 }
02568
02569 /**
02570   * @brief  DMA IRDA communication abort callback, when initiated by HAL services on Error
02571   *         (To be called at end of DMA Abort procedure following error occurrence).
02572   * @param  hdma DMA handle.
02573   * @retval None
02574   */
02575 static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)
02576 {
02577   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
02578   hirda->RxXferCount = 0U;
02579   hirda->TxXferCount = 0U;
02580
02581 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02582   /* Call registered user error callback */
02583   hirda->ErrorCallback(hirda);
02584 #else
02585   /* Call legacy weak user error callback */
02586   HAL_IRDA_ErrorCallback(hirda);
02587 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02588 }
02589
02590 /**
02591   * @brief  DMA IRDA Tx communication abort callback, when initiated by user
02592   *         (To be called at end of DMA Tx Abort procedure following user abort request).
02593   * @note   When this callback is executed, User Abort complete call back is called only if no
02594   *         Abort still ongoing for Rx DMA Handle.
02595   * @param  hdma DMA handle.
02596   * @retval None
02597   */
02598 static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
02599 {
02600   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
02601
02602   hirda->hdmatx->XferAbortCallback = NULL;
02603
02604   /* Check if an Abort process is still ongoing */
02605   if (hirda->hdmarx != NULL)
02606   {
02607     if (hirda->hdmarx->XferAbortCallback != NULL)
02608     {
02609       return;
02610     }
02611   }
02612
02613   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02614   hirda->TxXferCount = 0U;
02615   hirda->RxXferCount = 0U;
02616
02617   /* Reset errorCode */
02618   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
02619
02620   /* Clear the Error flags in the ICR register */
02621   __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
02622
02623   /* Restore hirda->gState and hirda->RxState to Ready */
02624   hirda->gState  = HAL_IRDA_STATE_READY;
02625   hirda->RxState = HAL_IRDA_STATE_READY;
02626
02627   /* Call user Abort complete callback */
02628 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02629   /* Call registered Abort complete callback */
02630   hirda->AbortCpltCallback(hirda);
02631 #else
02632   /* Call legacy weak Abort complete callback */
02633   HAL_IRDA_AbortCpltCallback(hirda);
02634 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02635 }
02636
02637
02638 /**
02639   * @brief  DMA IRDA Rx communication abort callback, when initiated by user
02640   *         (To be called at end of DMA Rx Abort procedure following user abort request).
02641   * @note   When this callback is executed, User Abort complete call back is called only if no
02642   *         Abort still ongoing for Tx DMA Handle.
02643   * @param  hdma DMA handle.
02644   * @retval None
02645   */
02646 static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
02647 {
02648   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
02649
02650   hirda->hdmarx->XferAbortCallback = NULL;
02651
02652   /* Check if an Abort process is still ongoing */
02653   if (hirda->hdmatx != NULL)
02654   {
02655     if (hirda->hdmatx->XferAbortCallback != NULL)
02656     {
02657       return;
02658     }
02659   }
02660
02661   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02662   hirda->TxXferCount = 0U;
02663   hirda->RxXferCount = 0U;
02664
02665   /* Reset errorCode */
02666   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
02667
02668   /* Clear the Error flags in the ICR register */
02669   __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
02670
02671   /* Restore hirda->gState and hirda->RxState to Ready */
02672   hirda->gState  = HAL_IRDA_STATE_READY;
02673   hirda->RxState = HAL_IRDA_STATE_READY;
02674
02675   /* Call user Abort complete callback */
02676 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02677   /* Call registered Abort complete callback */
02678   hirda->AbortCpltCallback(hirda);
02679 #else
02680   /* Call legacy weak Abort complete callback */
02681   HAL_IRDA_AbortCpltCallback(hirda);
02682 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02683 }
02684
02685
02686 /**
02687   * @brief  DMA IRDA Tx communication abort callback, when initiated by user by a call to
02688   *         HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer)
02689   *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
02690   *         and leads to user Tx Abort Complete callback execution).
02691   * @param  hdma DMA handle.
02692   * @retval None
02693   */
02694 static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
02695 {
02696   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
02697
02698   hirda->TxXferCount = 0U;
02699
02700   /* Restore hirda->gState to Ready */
02701   hirda->gState = HAL_IRDA_STATE_READY;
02702
02703   /* Call user Abort complete callback */
02704 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02705   /* Call registered Abort Transmit Complete Callback */
02706   hirda->AbortTransmitCpltCallback(hirda);
02707 #else
02708   /* Call legacy weak Abort Transmit Complete Callback */
02709   HAL_IRDA_AbortTransmitCpltCallback(hirda);
02710 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02711 }
02712
02713 /**
02714   * @brief  DMA IRDA Rx communication abort callback, when initiated by user by a call to
02715   *         HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer)
02716   *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
02717   *         and leads to user Rx Abort Complete callback execution).
02718   * @param  hdma DMA handle.
02719   * @retval None
02720   */
02721 static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
02722 {
02723   IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02724
02725   hirda->RxXferCount = 0U;
02726
02727   /* Clear the Error flags in the ICR register */
02728   __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
02729
02730   /* Restore hirda->RxState to Ready */
02731   hirda->RxState = HAL_IRDA_STATE_READY;
02732
02733   /* Call user Abort complete callback */
02734 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02735   /* Call registered Abort Receive Complete Callback */
02736   hirda->AbortReceiveCpltCallback(hirda);
02737 #else
02738   /* Call legacy weak Abort Receive Complete Callback */
02739   HAL_IRDA_AbortReceiveCpltCallback(hirda);
02740 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02741 }
02742
02743 /**
02744   * @brief  Send an amount of data in interrupt mode.
02745   * @note   Function is called under interruption only, once
02746   *         interruptions have been enabled by HAL_IRDA_Transmit_IT().
02747   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02748   *               the configuration information for the specified IRDA module.
02749   * @retval None
02750   */
02751 static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
02752 {
02753   uint16_t *tmp;
02754
02755   /* Check that a Tx process is ongoing */
02756   if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
02757   {
02758     if (hirda->TxXferCount == 0U)
02759     {
02760       /* Disable the IRDA Transmit Data Register Empty Interrupt */
02761       CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
02762
02763       /* Enable the IRDA Transmit Complete Interrupt */
02764       SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
02765     }
02766     else
02767     {
02768       if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
02769       {
02770         tmp = (uint16_t *) hirda->pTxBuffPtr; /* Derogation R.11.3 */
02771         hirda->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);
02772         hirda->pTxBuffPtr += 2U;
02773       }
02774       else
02775       {
02776         hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr & 0xFFU);
02777         hirda->pTxBuffPtr++;
02778       }
02779       hirda->TxXferCount--;
02780     }
02781   }
02782 }
02783
02784 /**
02785   * @brief  Wrap up transmission in non-blocking mode.
02786   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02787   *               the configuration information for the specified IRDA module.
02788   * @retval None
02789   */
02790 static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
02791 {
02792   /* Disable the IRDA Transmit Complete Interrupt */
02793   CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
02794
02795   /* Tx process is ended, restore hirda->gState to Ready */
02796   hirda->gState = HAL_IRDA_STATE_READY;
02797
02798 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02799   /* Call registered Tx complete callback */
02800   hirda->TxCpltCallback(hirda);
02801 #else
02802   /* Call legacy weak Tx complete callback */
02803   HAL_IRDA_TxCpltCallback(hirda);
02804 #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
02805 }
02806
02807 /**
02808   * @brief  Receive an amount of data in interrupt mode.
02809   * @note   Function is called under interruption only, once
02810   *         interruptions have been enabled by HAL_IRDA_Receive_IT()
02811   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
02812   *               the configuration information for the specified IRDA module.
02813   * @retval None
02814   */
02815 static void IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
02816 {
02817   uint16_t *tmp;
02818   uint16_t  uhMask = hirda->Mask;
02819   uint16_t  uhdata;
02820
02821   /* Check that a Rx process is ongoing */
02822   if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
02823   {
02824     uhdata = (uint16_t) READ_REG(hirda->Instance->RDR);
02825     if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
02826     {
02827       tmp = (uint16_t *) hirda->pRxBuffPtr; /* Derogation R.11.3 */
02828       *tmp = (uint16_t)(uhdata & uhMask);
02829       hirda->pRxBuffPtr  += 2U;
02830     }
02831     else
02832     {
02833       *hirda->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
02834       hirda->pRxBuffPtr++;
02835     }
02836
02837     hirda->RxXferCount--;
02838     if (hirda->RxXferCount == 0U)
02839     {
02840       /* Disable the IRDA Parity Error Interrupt and RXNE interrupt */
02841       CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
02842
02843       /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
02844       CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
02845
02846       /* Rx process is completed, restore hirda->RxState to Ready */
02847       hirda->RxState = HAL_IRDA_STATE_READY;
02848
02849 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
02850       /* Call registered Rx complete callback */
02851       hirda->RxCpltCallback(hirda);
02852 #else
02853       /* Call legacy weak Rx complete callback */
02854       HAL_IRDA_RxCpltCallback(hirda);
02855 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
02856     }
02857   }
02858   else
02859   {
02860     /* Clear RXNE interrupt flag */
02861     __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST);
02862   }
02863 }
02864
02865 /**
02866   * @}
02867   */
02868
02869 #endif /* HAL_IRDA_MODULE_ENABLED */
02870 /**
02871   * @}
02872   */
02873
02874 /**
02875   * @}
02876   */
02877
02878 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_irda.h Source File

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stm32wbxx_hal_irda.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_irda.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of IRDA HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_IRDA_H
00022 #define STM32WBxx_HAL_IRDA_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 /** @addtogroup STM32WBxx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup IRDA
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup IRDA_Exported_Types IRDA Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief IRDA Init Structure definition
00046   */
00047 typedef struct
00048 {
00049   uint32_t BaudRate;                  /*!< This member configures the IRDA communication baud rate.
00050                                            The baud rate register is computed using the following formula:
00051                                               Baud Rate Register = ((usart_ker_ckpres) / ((hirda->Init.BaudRate)))
00052                                            where usart_ker_ckpres is the IRDA input clock divided by a prescaler */
00053
00054   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
00055                                            This parameter can be a value of @ref IRDA_Word_Length */
00056
00057   uint32_t Parity;                    /*!< Specifies the parity mode.
00058                                            This parameter can be a value of @ref IRDA_Parity
00059                                            @note When parity is enabled, the computed parity is inserted
00060                                                  at the MSB position of the transmitted data (9th bit when
00061                                                  the word length is set to 9 data bits; 8th bit when the
00062                                                  word length is set to 8 data bits). */
00063
00064   uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
00065                                            This parameter can be a value of @ref IRDA_Transfer_Mode */
00066
00067   uint8_t  Prescaler;                 /*!< Specifies the Prescaler value for dividing the UART/USART source clock
00068                                            to achieve low-power frequency.
00069                                            @note Prescaler value 0 is forbidden */
00070
00071   uint16_t PowerMode;                 /*!< Specifies the IRDA power mode.
00072                                            This parameter can be a value of @ref IRDA_Low_Power */
00073
00074   uint32_t ClockPrescaler;            /*!< Specifies the prescaler value used to divide the IRDA clock source.
00075                                            This parameter can be a value of @ref IRDA_ClockPrescaler. */
00076
00077 } IRDA_InitTypeDef;
00078
00079 /**
00080   * @brief HAL IRDA State definition
00081   * @note  HAL IRDA State value is a combination of 2 different substates: gState and RxState (see @ref IRDA_State_Definition).
00082   *        - gState contains IRDA state information related to global Handle management
00083   *          and also information related to Tx operations.
00084   *          gState value coding follow below described bitmap :
00085   *          b7-b6  Error information
00086   *             00 : No Error
00087   *             01 : (Not Used)
00088   *             10 : Timeout
00089   *             11 : Error
00090   *          b5     IP initilisation status
00091   *             0  : Reset (IP not initialized)
00092   *             1  : Init done (IP not initialized. HAL IRDA Init function already called)
00093   *          b4-b3  (not used)
00094   *             xx : Should be set to 00
00095   *          b2     Intrinsic process state
00096   *             0  : Ready
00097   *             1  : Busy (IP busy with some configuration or internal operations)
00098   *          b1     (not used)
00099   *             x  : Should be set to 0
00100   *          b0     Tx state
00101   *             0  : Ready (no Tx operation ongoing)
00102   *             1  : Busy (Tx operation ongoing)
00103   *        - RxState contains information related to Rx operations.
00104   *          RxState value coding follow below described bitmap :
00105   *          b7-b6  (not used)
00106   *             xx : Should be set to 00
00107   *          b5     IP initilisation status
00108   *             0  : Reset (IP not initialized)
00109   *             1  : Init done (IP not initialized)
00110   *          b4-b2  (not used)
00111   *            xxx : Should be set to 000
00112   *          b1     Rx state
00113   *             0  : Ready (no Rx operation ongoing)
00114   *             1  : Busy (Rx operation ongoing)
00115   *          b0     (not used)
00116   *             x  : Should be set to 0.
00117   */
00118 typedef uint32_t HAL_IRDA_StateTypeDef;
00119
00120 /**
00121   * @brief IRDA clock sources definition
00122   */
00123 typedef enum
00124 {
00125   IRDA_CLOCKSOURCE_PCLK2      = 0x01U,    /*!< PCLK2 clock source         */
00126   IRDA_CLOCKSOURCE_HSI        = 0x02U,    /*!< HSI clock source           */
00127   IRDA_CLOCKSOURCE_SYSCLK     = 0x04U,    /*!< SYSCLK clock source        */
00128   IRDA_CLOCKSOURCE_LSE        = 0x10U,    /*!< LSE clock source           */
00129   IRDA_CLOCKSOURCE_UNDEFINED  = 0x20U     /*!< Undefined clock source     */
00130 } IRDA_ClockSourceTypeDef;
00131
00132 /**
00133   * @brief  IRDA handle Structure definition
00134   */
00135 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
00136 typedef struct __IRDA_HandleTypeDef
00137 #else
00138 typedef struct
00139 #endif  /* USE_HAL_IRDA_REGISTER_CALLBACKS */
00140 {
00141   USART_TypeDef            *Instance;        /*!< USART registers base address       */
00142
00143   IRDA_InitTypeDef         Init;             /*!< IRDA communication parameters      */
00144
00145   uint8_t                  *pTxBuffPtr;      /*!< Pointer to IRDA Tx transfer Buffer */
00146
00147   uint16_t                 TxXferSize;       /*!< IRDA Tx Transfer size              */
00148
00149   __IO uint16_t            TxXferCount;      /*!< IRDA Tx Transfer Counter           */
00150
00151   uint8_t                  *pRxBuffPtr;      /*!< Pointer to IRDA Rx transfer Buffer */
00152
00153   uint16_t                 RxXferSize;       /*!< IRDA Rx Transfer size              */
00154
00155   __IO uint16_t            RxXferCount;      /*!< IRDA Rx Transfer Counter           */
00156
00157   uint16_t                 Mask;             /*!< USART RX RDR register mask         */
00158
00159   DMA_HandleTypeDef        *hdmatx;          /*!< IRDA Tx DMA Handle parameters      */
00160
00161   DMA_HandleTypeDef        *hdmarx;          /*!< IRDA Rx DMA Handle parameters      */
00162
00163   HAL_LockTypeDef          Lock;             /*!< Locking object                     */
00164
00165   __IO HAL_IRDA_StateTypeDef    gState;      /*!< IRDA state information related to global Handle management
00166                                                   and also related to Tx operations.
00167                                                   This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
00168
00169   __IO HAL_IRDA_StateTypeDef    RxState;     /*!< IRDA state information related to Rx operations.
00170                                                   This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
00171
00172   uint32_t                 ErrorCode;        /*!< IRDA Error code                    */
00173
00174 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
00175   void (* TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda);        /*!< IRDA Tx Half Complete Callback        */
00176
00177   void (* TxCpltCallback)(struct __IRDA_HandleTypeDef *hirda);            /*!< IRDA Tx Complete Callback             */
00178
00179   void (* RxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda);        /*!< IRDA Rx Half Complete Callback        */
00180
00181   void (* RxCpltCallback)(struct __IRDA_HandleTypeDef *hirda);            /*!< IRDA Rx Complete Callback             */
00182
00183   void (* ErrorCallback)(struct __IRDA_HandleTypeDef *hirda);             /*!< IRDA Error Callback                   */
00184
00185   void (* AbortCpltCallback)(struct __IRDA_HandleTypeDef *hirda);         /*!< IRDA Abort Complete Callback          */
00186
00187   void (* AbortTransmitCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Transmit Complete Callback */
00188
00189   void (* AbortReceiveCpltCallback)(struct __IRDA_HandleTypeDef *hirda);  /*!< IRDA Abort Receive Complete Callback  */
00190
00191
00192   void (* MspInitCallback)(struct __IRDA_HandleTypeDef *hirda);           /*!< IRDA Msp Init callback                */
00193
00194   void (* MspDeInitCallback)(struct __IRDA_HandleTypeDef *hirda);         /*!< IRDA Msp DeInit callback              */
00195 #endif  /* USE_HAL_IRDA_REGISTER_CALLBACKS */
00196
00197 } IRDA_HandleTypeDef;
00198
00199 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
00200 /**
00201   * @brief  HAL IRDA Callback ID enumeration definition
00202   */
00203 typedef enum
00204 {
00205   HAL_IRDA_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< IRDA Tx Half Complete Callback ID        */
00206   HAL_IRDA_TX_COMPLETE_CB_ID             = 0x01U,    /*!< IRDA Tx Complete Callback ID             */
00207   HAL_IRDA_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< IRDA Rx Half Complete Callback ID        */
00208   HAL_IRDA_RX_COMPLETE_CB_ID             = 0x03U,    /*!< IRDA Rx Complete Callback ID             */
00209   HAL_IRDA_ERROR_CB_ID                   = 0x04U,    /*!< IRDA Error Callback ID                   */
00210   HAL_IRDA_ABORT_COMPLETE_CB_ID          = 0x05U,    /*!< IRDA Abort Complete Callback ID          */
00211   HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U,    /*!< IRDA Abort Transmit Complete Callback ID */
00212   HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x07U,    /*!< IRDA Abort Receive Complete Callback ID  */
00213
00214   HAL_IRDA_MSPINIT_CB_ID                 = 0x08U,    /*!< IRDA MspInit callback ID                 */
00215   HAL_IRDA_MSPDEINIT_CB_ID               = 0x09U     /*!< IRDA MspDeInit callback ID               */
00216
00217 } HAL_IRDA_CallbackIDTypeDef;
00218
00219 /**
00220   * @brief  HAL IRDA Callback pointer definition
00221   */
00222 typedef  void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda);  /*!< pointer to an IRDA callback function */
00223
00224 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
00225
00226 /**
00227   * @}
00228   */
00229
00230 /* Exported constants --------------------------------------------------------*/
00231 /** @defgroup IRDA_Exported_Constants IRDA Exported Constants
00232   * @{
00233   */
00234
00235 /** @defgroup IRDA_State_Definition IRDA State Code Definition
00236   * @{
00237   */
00238 #define HAL_IRDA_STATE_RESET                0x00000000U   /*!< Peripheral is not initialized
00239                                                                Value is allowed for gState and RxState */
00240 #define HAL_IRDA_STATE_READY                0x00000020U   /*!< Peripheral Initialized and ready for use
00241                                                                Value is allowed for gState and RxState */
00242 #define HAL_IRDA_STATE_BUSY                 0x00000024U   /*!< An internal process is ongoing
00243                                                                Value is allowed for gState only */
00244 #define HAL_IRDA_STATE_BUSY_TX              0x00000021U   /*!< Data Transmission process is ongoing
00245                                                                Value is allowed for gState only */
00246 #define HAL_IRDA_STATE_BUSY_RX              0x00000022U   /*!< Data Reception process is ongoing
00247                                                                Value is allowed for RxState only */
00248 #define HAL_IRDA_STATE_BUSY_TX_RX           0x00000023U   /*!< Data Transmission and Reception process is ongoing
00249                                                                Not to be used for neither gState nor RxState.
00250                                                                Value is result of combination (Or) between gState and RxState values */
00251 #define HAL_IRDA_STATE_TIMEOUT              0x000000A0U   /*!< Timeout state
00252                                                                Value is allowed for gState only */
00253 #define HAL_IRDA_STATE_ERROR                0x000000E0U   /*!< Error
00254                                                                Value is allowed for gState only */
00255 /**
00256   * @}
00257   */
00258
00259 /** @defgroup IRDA_Error_Definition IRDA Error Code Definition
00260   * @{
00261   */
00262 #define HAL_IRDA_ERROR_NONE                 ((uint32_t)0x00000000U)          /*!< No error                */
00263 #define HAL_IRDA_ERROR_PE                   ((uint32_t)0x00000001U)          /*!< Parity error            */
00264 #define HAL_IRDA_ERROR_NE                   ((uint32_t)0x00000002U)          /*!< Noise error             */
00265 #define HAL_IRDA_ERROR_FE                   ((uint32_t)0x00000004U)          /*!< frame error             */
00266 #define HAL_IRDA_ERROR_ORE                  ((uint32_t)0x00000008U)          /*!< Overrun error           */
00267 #define HAL_IRDA_ERROR_DMA                  ((uint32_t)0x00000010U)          /*!< DMA transfer error      */
00268 #define HAL_IRDA_ERROR_BUSY                 ((uint32_t)0x00000020U)          /*!< Busy Error              */
00269 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
00270 #define HAL_IRDA_ERROR_INVALID_CALLBACK     ((uint32_t)0x00000040U)          /*!< Invalid Callback error  */
00271 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
00272 /**
00273   * @}
00274   */
00275
00276 /** @defgroup IRDA_Word_Length IRDA Word Length
00277   * @{
00278   */
00279 #define IRDA_WORDLENGTH_7B                  USART_CR1_M1   /*!< 7-bit long frame */
00280 #define IRDA_WORDLENGTH_8B                  0x00000000U    /*!< 8-bit long frame */
00281 #define IRDA_WORDLENGTH_9B                  USART_CR1_M0   /*!< 9-bit long frame */
00282 /**
00283   * @}
00284   */
00285
00286 /** @defgroup IRDA_Parity IRDA Parity
00287   * @{
00288   */
00289 #define IRDA_PARITY_NONE                    0x00000000U                      /*!< No parity   */
00290 #define IRDA_PARITY_EVEN                    USART_CR1_PCE                    /*!< Even parity */
00291 #define IRDA_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)   /*!< Odd parity  */
00292 /**
00293   * @}
00294   */
00295
00296 /** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
00297   * @{
00298   */
00299 #define IRDA_MODE_RX                        USART_CR1_RE                   /*!< RX mode        */
00300 #define IRDA_MODE_TX                        USART_CR1_TE                   /*!< TX mode        */
00301 #define IRDA_MODE_TX_RX                     (USART_CR1_TE |USART_CR1_RE)   /*!< RX and TX mode */
00302 /**
00303   * @}
00304   */
00305
00306 /** @defgroup IRDA_Low_Power IRDA Low Power
00307   * @{
00308   */
00309 #define IRDA_POWERMODE_NORMAL               0x00000000U       /*!< IRDA normal power mode */
00310 #define IRDA_POWERMODE_LOWPOWER             USART_CR3_IRLP    /*!< IRDA low power mode    */
00311 /**
00312   * @}
00313   */
00314
00315 /** @defgroup IRDA_ClockPrescaler  Clock Prescaler
00316   * @{
00317   */
00318 #define IRDA_PRESCALER_DIV1    0x00000000U  /*!< fclk_pres = fclk     */
00319 #define IRDA_PRESCALER_DIV2    0x00000001U  /*!< fclk_pres = fclk/2   */
00320 #define IRDA_PRESCALER_DIV4    0x00000002U  /*!< fclk_pres = fclk/4   */
00321 #define IRDA_PRESCALER_DIV6    0x00000003U  /*!< fclk_pres = fclk/6   */
00322 #define IRDA_PRESCALER_DIV8    0x00000004U  /*!< fclk_pres = fclk/8   */
00323 #define IRDA_PRESCALER_DIV10   0x00000005U  /*!< fclk_pres = fclk/10  */
00324 #define IRDA_PRESCALER_DIV12   0x00000006U  /*!< fclk_pres = fclk/12  */
00325 #define IRDA_PRESCALER_DIV16   0x00000007U  /*!< fclk_pres = fclk/16  */
00326 #define IRDA_PRESCALER_DIV32   0x00000008U  /*!< fclk_pres = fclk/32  */
00327 #define IRDA_PRESCALER_DIV64   0x00000009U  /*!< fclk_pres = fclk/64  */
00328 #define IRDA_PRESCALER_DIV128  0x0000000AU  /*!< fclk_pres = fclk/128 */
00329 #define IRDA_PRESCALER_DIV256  0x0000000BU  /*!< fclk_pres = fclk/256 */
00330 /**
00331   * @}
00332   */
00333
00334 /** @defgroup IRDA_State IRDA State
00335   * @{
00336   */
00337 #define IRDA_STATE_DISABLE                  0x00000000U     /*!< IRDA disabled  */
00338 #define IRDA_STATE_ENABLE                   USART_CR1_UE    /*!< IRDA enabled   */
00339 /**
00340   * @}
00341   */
00342
00343 /** @defgroup IRDA_Mode  IRDA Mode
00344   * @{
00345   */
00346 #define IRDA_MODE_DISABLE                   0x00000000U      /*!< Associated UART disabled in IRDA mode */
00347 #define IRDA_MODE_ENABLE                    USART_CR3_IREN   /*!< Associated UART enabled in IRDA mode  */
00348 /**
00349   * @}
00350   */
00351
00352 /** @defgroup IRDA_One_Bit  IRDA One Bit Sampling
00353   * @{
00354   */
00355 #define IRDA_ONE_BIT_SAMPLE_DISABLE         0x00000000U       /*!< One-bit sampling disabled */
00356 #define IRDA_ONE_BIT_SAMPLE_ENABLE          USART_CR3_ONEBIT  /*!< One-bit sampling enabled  */
00357 /**
00358   * @}
00359   */
00360
00361 /** @defgroup IRDA_DMA_Tx IRDA DMA Tx
00362   * @{
00363   */
00364 #define IRDA_DMA_TX_DISABLE                 0x00000000U       /*!< IRDA DMA TX disabled */
00365 #define IRDA_DMA_TX_ENABLE                  USART_CR3_DMAT    /*!< IRDA DMA TX enabled  */
00366 /**
00367   * @}
00368   */
00369
00370 /** @defgroup IRDA_DMA_Rx  IRDA DMA Rx
00371   * @{
00372   */
00373 #define IRDA_DMA_RX_DISABLE                 0x00000000U       /*!< IRDA DMA RX disabled */
00374 #define IRDA_DMA_RX_ENABLE                  USART_CR3_DMAR    /*!< IRDA DMA RX enabled  */
00375 /**
00376   * @}
00377   */
00378
00379 /** @defgroup IRDA_Request_Parameters IRDA Request Parameters
00380   * @{
00381   */
00382 #define IRDA_AUTOBAUD_REQUEST            USART_RQR_ABRRQ        /*!< Auto-Baud Rate Request      */
00383 #define IRDA_RXDATA_FLUSH_REQUEST        USART_RQR_RXFRQ        /*!< Receive Data flush Request  */
00384 #define IRDA_TXDATA_FLUSH_REQUEST        USART_RQR_TXFRQ        /*!< Transmit data flush Request */
00385 /**
00386   * @}
00387   */
00388
00389 /** @defgroup IRDA_Flags IRDA Flags
00390   *        Elements values convention: 0xXXXX
00391   *           - 0xXXXX  : Flag mask in the ISR register
00392   * @{
00393   */
00394 #define IRDA_FLAG_REACK                     USART_ISR_REACK         /*!< IRDA receive enable acknowledge flag      */
00395 #define IRDA_FLAG_TEACK                     USART_ISR_TEACK         /*!< IRDA transmit enable acknowledge flag     */
00396 #define IRDA_FLAG_BUSY                      USART_ISR_BUSY          /*!< IRDA busy flag                            */
00397 #define IRDA_FLAG_ABRF                      USART_ISR_ABRF          /*!< IRDA auto Baud rate flag                  */
00398 #define IRDA_FLAG_ABRE                      USART_ISR_ABRE          /*!< IRDA auto Baud rate error                 */
00399 #define IRDA_FLAG_TXE                       USART_ISR_TXE_TXFNF     /*!< IRDA transmit data register empty         */
00400 #define IRDA_FLAG_TC                        USART_ISR_TC            /*!< IRDA transmission complete                */
00401 #define IRDA_FLAG_RXNE                      USART_ISR_RXNE_RXFNE    /*!< IRDA read data register not empty         */
00402 #define IRDA_FLAG_ORE                       USART_ISR_ORE           /*!< IRDA overrun error                        */
00403 #define IRDA_FLAG_NE                        USART_ISR_NE            /*!< IRDA noise error                          */
00404 #define IRDA_FLAG_FE                        USART_ISR_FE            /*!< IRDA frame error                          */
00405 #define IRDA_FLAG_PE                        USART_ISR_PE            /*!< IRDA parity error                         */
00406 /**
00407   * @}
00408   */
00409
00410 /** @defgroup IRDA_Interrupt_definition IRDA Interrupts Definition
00411   *        Elements values convention: 0000ZZZZ0XXYYYYYb
00412   *           - YYYYY  : Interrupt source position in the XX register (5bits)
00413   *           - XX  : Interrupt source register (2bits)
00414   *                 - 01: CR1 register
00415   *                 - 10: CR2 register
00416   *                 - 11: CR3 register
00417   *           - ZZZZ  : Flag position in the ISR register(4bits)
00418   * @{
00419   */
00420 #define IRDA_IT_PE                          0x0028U     /*!< IRDA Parity error interruption                 */
00421 #define IRDA_IT_TXE                         0x0727U     /*!< IRDA Transmit data register empty interruption */
00422 #define IRDA_IT_TC                          0x0626U     /*!< IRDA Transmission complete interruption        */
00423 #define IRDA_IT_RXNE                        0x0525U     /*!< IRDA Read data register not empty interruption */
00424 #define IRDA_IT_IDLE                        0x0424U     /*!< IRDA Idle interruption                         */
00425
00426 /*       Elements values convention: 000000000XXYYYYYb
00427              - YYYYY  : Interrupt source position in the XX register (5bits)
00428              - XX  : Interrupt source register (2bits)
00429                    - 01: CR1 register
00430                    - 10: CR2 register
00431                    - 11: CR3 register */
00432 #define IRDA_IT_ERR                         0x0060U       /*!< IRDA Error interruption        */
00433
00434 /*       Elements values convention: 0000ZZZZ00000000b
00435              - ZZZZ  : Flag position in the ISR register(4bits) */
00436 #define IRDA_IT_ORE                         0x0300U      /*!< IRDA Overrun error interruption */
00437 #define IRDA_IT_NE                          0x0200U      /*!< IRDA Noise error interruption   */
00438 #define IRDA_IT_FE                          0x0100U      /*!< IRDA Frame error interruption   */
00439 /**
00440   * @}
00441   */
00442
00443 /** @defgroup IRDA_IT_CLEAR_Flags   IRDA Interruption Clear Flags
00444   * @{
00445   */
00446 #define IRDA_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag          */
00447 #define IRDA_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag         */
00448 #define IRDA_CLEAR_NEF                       USART_ICR_NECF            /*!< Noise Error detected Clear Flag  */
00449 #define IRDA_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag         */
00450 #define IRDA_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag    */
00451 #define IRDA_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag */
00452 /**
00453   * @}
00454   */
00455
00456 /** @defgroup IRDA_Interruption_Mask    IRDA interruptions flags mask
00457   * @{
00458   */
00459 #define IRDA_IT_MASK  0x001FU  /*!< IRDA Interruptions flags mask  */
00460 #define IRDA_CR_MASK  0x00E0U  /*!< IRDA control register mask     */
00461 #define IRDA_CR_POS   5U       /*!< IRDA control register position */
00462 #define IRDA_ISR_MASK 0x1F00U  /*!< IRDA ISR register mask         */
00463 #define IRDA_ISR_POS  8U       /*!< IRDA ISR register position     */
00464 /**
00465   * @}
00466   */
00467
00468 /**
00469  * @}
00470  */
00471
00472
00473 /* Exported macros -----------------------------------------------------------*/
00474 /** @defgroup IRDA_Exported_Macros IRDA Exported Macros
00475   * @{
00476   */
00477
00478 /** @brief  Reset IRDA handle state.
00479   * @param  __HANDLE__ IRDA handle.
00480   * @retval None
00481   */
00482 #if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
00483 #define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
00484                                                        (__HANDLE__)->gState = HAL_IRDA_STATE_RESET;      \
00485                                                        (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET;     \
00486                                                        (__HANDLE__)->MspInitCallback = NULL;             \
00487                                                        (__HANDLE__)->MspDeInitCallback = NULL;           \
00488                                                      } while(0)
00489 #else
00490 #define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
00491                                                        (__HANDLE__)->gState = HAL_IRDA_STATE_RESET;      \
00492                                                        (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET;     \
00493                                                      } while(0)
00494 #endif /*USE_HAL_IRDA_REGISTER_CALLBACKS  */
00495
00496 /** @brief  Flush the IRDA DR register.
00497   * @param  __HANDLE__ specifies the IRDA Handle.
00498   * @retval None
00499   */
00500 #define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__)                            \
00501     do{                                                                    \
00502          SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
00503          SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
00504       } while(0)
00505
00506 /** @brief  Clear the specified IRDA pending flag.
00507   * @param  __HANDLE__ specifies the IRDA Handle.
00508   * @param  __FLAG__ specifies the flag to check.
00509   *          This parameter can be any combination of the following values:
00510   *            @arg @ref IRDA_CLEAR_PEF
00511   *            @arg @ref IRDA_CLEAR_FEF
00512   *            @arg @ref IRDA_CLEAR_NEF
00513   *            @arg @ref IRDA_CLEAR_OREF
00514   *            @arg @ref IRDA_CLEAR_TCF
00515   *            @arg @ref IRDA_CLEAR_IDLEF
00516   * @retval None
00517   */
00518 #define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00519
00520 /** @brief  Clear the IRDA PE pending flag.
00521   * @param  __HANDLE__ specifies the IRDA Handle.
00522   * @retval None
00523   */
00524 #define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
00525
00526
00527 /** @brief  Clear the IRDA FE pending flag.
00528   * @param  __HANDLE__ specifies the IRDA Handle.
00529   * @retval None
00530   */
00531 #define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
00532
00533 /** @brief  Clear the IRDA NE pending flag.
00534   * @param  __HANDLE__ specifies the IRDA Handle.
00535   * @retval None
00536   */
00537 #define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
00538
00539 /** @brief  Clear the IRDA ORE pending flag.
00540   * @param  __HANDLE__ specifies the IRDA Handle.
00541   * @retval None
00542   */
00543 #define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
00544
00545 /** @brief  Clear the IRDA IDLE pending flag.
00546   * @param  __HANDLE__ specifies the IRDA Handle.
00547   * @retval None
00548   */
00549 #define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
00550
00551 /** @brief  Check whether the specified IRDA flag is set or not.
00552   * @param  __HANDLE__ specifies the IRDA Handle.
00553   * @param  __FLAG__ specifies the flag to check.
00554   *        This parameter can be one of the following values:
00555   *            @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag
00556   *            @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag
00557   *            @arg @ref IRDA_FLAG_BUSY  Busy flag
00558   *            @arg @ref IRDA_FLAG_ABRF  Auto Baud rate detection flag
00559   *            @arg @ref IRDA_FLAG_ABRE  Auto Baud rate detection error flag
00560   *            @arg @ref IRDA_FLAG_TXE   Transmit data register empty flag
00561   *            @arg @ref IRDA_FLAG_TC    Transmission Complete flag
00562   *            @arg @ref IRDA_FLAG_RXNE  Receive data register not empty flag
00563   *            @arg @ref IRDA_FLAG_ORE   OverRun Error flag
00564   *            @arg @ref IRDA_FLAG_NE    Noise Error flag
00565   *            @arg @ref IRDA_FLAG_FE    Framing Error flag
00566   *            @arg @ref IRDA_FLAG_PE    Parity Error flag
00567   * @retval The new state of __FLAG__ (TRUE or FALSE).
00568   */
00569 #define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
00570
00571
00572 /** @brief  Enable the specified IRDA interrupt.
00573   * @param  __HANDLE__ specifies the IRDA Handle.
00574   * @param  __INTERRUPT__ specifies the IRDA interrupt source to enable.
00575   *          This parameter can be one of the following values:
00576   *            @arg @ref IRDA_IT_TXE  Transmit Data Register empty interrupt
00577   *            @arg @ref IRDA_IT_TC   Transmission complete interrupt
00578   *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
00579   *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
00580   *            @arg @ref IRDA_IT_PE   Parity Error interrupt
00581   *            @arg @ref IRDA_IT_ERR  Error interrupt(Frame error, noise error, overrun error)
00582   * @retval None
00583   */
00584 #define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
00585                                                            ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
00586                                                            ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
00587
00588 /** @brief  Disable the specified IRDA interrupt.
00589   * @param  __HANDLE__ specifies the IRDA Handle.
00590   * @param  __INTERRUPT__ specifies the IRDA interrupt source to disable.
00591   *          This parameter can be one of the following values:
00592   *            @arg @ref IRDA_IT_TXE  Transmit Data Register empty interrupt
00593   *            @arg @ref IRDA_IT_TC   Transmission complete interrupt
00594   *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
00595   *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
00596   *            @arg @ref IRDA_IT_PE   Parity Error interrupt
00597   *            @arg @ref IRDA_IT_ERR  Error interrupt(Frame error, noise error, overrun error)
00598   * @retval None
00599   */
00600 #define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
00601                                                            ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
00602                                                            ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
00603
00604
00605 /** @brief  Check whether the specified IRDA interrupt has occurred or not.
00606   * @param  __HANDLE__ specifies the IRDA Handle.
00607   * @param  __INTERRUPT__ specifies the IRDA interrupt source to check.
00608   *          This parameter can be one of the following values:
00609   *            @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
00610   *            @arg @ref IRDA_IT_TC  Transmission complete interrupt
00611   *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
00612   *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
00613   *            @arg @ref IRDA_IT_ORE OverRun Error interrupt
00614   *            @arg @ref IRDA_IT_NE Noise Error interrupt
00615   *            @arg @ref IRDA_IT_FE Framing Error interrupt
00616   *            @arg @ref IRDA_IT_PE Parity Error interrupt
00617   * @retval The new state of __IT__ (SET or RESET).
00618   */
00619 #define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET)
00620
00621 /** @brief  Check whether the specified IRDA interrupt source is enabled or not.
00622   * @param  __HANDLE__ specifies the IRDA Handle.
00623   * @param  __INTERRUPT__ specifies the IRDA interrupt source to check.
00624   *          This parameter can be one of the following values:
00625   *            @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
00626   *            @arg @ref IRDA_IT_TC  Transmission complete interrupt
00627   *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
00628   *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
00629   *            @arg @ref IRDA_IT_ERR Framing, overrun or noise error interrupt
00630   *            @arg @ref IRDA_IT_PE Parity Error interrupt
00631   * @retval The new state of __IT__ (SET or RESET).
00632   */
00633 #define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \
00634                                                                (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
00635                                                                (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
00636
00637 /** @brief  Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
00638   * @param  __HANDLE__ specifies the IRDA Handle.
00639   * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
00640   *                       to clear the corresponding interrupt
00641   *          This parameter can be one of the following values:
00642   *            @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag
00643   *            @arg @ref IRDA_CLEAR_FEF Framing Error Clear Flag
00644   *            @arg @ref IRDA_CLEAR_NEF Noise detected Clear Flag
00645   *            @arg @ref IRDA_CLEAR_OREF OverRun Error Clear Flag
00646   *            @arg @ref IRDA_CLEAR_TCF Transmission Complete Clear Flag
00647   * @retval None
00648   */
00649 #define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
00650
00651
00652 /** @brief  Set a specific IRDA request flag.
00653   * @param  __HANDLE__ specifies the IRDA Handle.
00654   * @param  __REQ__ specifies the request flag to set
00655   *          This parameter can be one of the following values:
00656   *            @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request
00657   *            @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request
00658   *            @arg @ref IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request
00659   *
00660   * @retval None
00661   */
00662 #define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
00663
00664 /** @brief  Enable the IRDA one bit sample method.
00665   * @param  __HANDLE__ specifies the IRDA Handle.
00666   * @retval None
00667   */
00668 #define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
00669
00670 /** @brief  Disable the IRDA one bit sample method.
00671   * @param  __HANDLE__ specifies the IRDA Handle.
00672   * @retval None
00673   */
00674 #define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
00675
00676 /** @brief  Enable UART/USART associated to IRDA Handle.
00677   * @param  __HANDLE__ specifies the IRDA Handle.
00678   * @retval None
00679   */
00680 #define __HAL_IRDA_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
00681
00682 /** @brief  Disable UART/USART associated to IRDA Handle.
00683   * @param  __HANDLE__ specifies the IRDA Handle.
00684   * @retval None
00685   */
00686 #define __HAL_IRDA_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
00687
00688 /**
00689   * @}
00690   */
00691
00692 /* Private macros --------------------------------------------------------*/
00693 /** @addtogroup IRDA_Private_Macros
00694   * @{
00695   */
00696
00697 /** @brief  Compute the mask to apply to retrieve the received data
00698   *         according to the word length and to the parity bits activation.
00699   * @param  __HANDLE__ specifies the IRDA Handle.
00700   * @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.
00701   */
00702 #define IRDA_MASK_COMPUTATION(__HANDLE__)                             \
00703   do {                                                                \
00704   if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B)            \
00705   {                                                                   \
00706      if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)               \
00707      {                                                                \
00708         (__HANDLE__)->Mask = 0x01FF ;                                 \
00709      }                                                                \
00710      else                                                             \
00711      {                                                                \
00712         (__HANDLE__)->Mask = 0x00FF ;                                 \
00713      }                                                                \
00714   }                                                                   \
00715   else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B)       \
00716   {                                                                   \
00717      if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)               \
00718      {                                                                \
00719         (__HANDLE__)->Mask = 0x00FF ;                                 \
00720      }                                                                \
00721      else                                                             \
00722      {                                                                \
00723         (__HANDLE__)->Mask = 0x007F ;                                 \
00724      }                                                                \
00725   }                                                                   \
00726   else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B)       \
00727   {                                                                   \
00728      if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)               \
00729      {                                                                \
00730         (__HANDLE__)->Mask = 0x007F ;                                 \
00731      }                                                                \
00732      else                                                             \
00733      {                                                                \
00734         (__HANDLE__)->Mask = 0x003F ;                                 \
00735      }                                                                \
00736   }                                                                   \
00737   else                                                                \
00738   {                                                                   \
00739     (__HANDLE__)->Mask = 0x0000U;                                     \
00740   }                                                                   \
00741 } while(0)
00742
00743 /** @brief  Ensure that IRDA Baud rate is less or equal to maximum value.
00744   * @param  __BAUDRATE__ specifies the IRDA Baudrate set by the user.
00745   * @retval True or False
00746   */
00747 #define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U)
00748
00749 /** @brief  Ensure that IRDA prescaler value is strictly larger than 0.
00750   * @param  __PRESCALER__ specifies the IRDA prescaler value set by the user.
00751   * @retval True or False
00752   */
00753 #define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U)
00754
00755 /**
00756   * @brief Ensure that IRDA frame length is valid.
00757   * @param __LENGTH__ IRDA frame length.
00758   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
00759   */
00760 #define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \
00761                                          ((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
00762                                          ((__LENGTH__) == IRDA_WORDLENGTH_9B))
00763
00764 /**
00765   * @brief Ensure that IRDA frame parity is valid.
00766   * @param __PARITY__ IRDA frame parity.
00767   * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
00768   */
00769 #define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \
00770                                     ((__PARITY__) == IRDA_PARITY_EVEN) || \
00771                                     ((__PARITY__) == IRDA_PARITY_ODD))
00772
00773 /**
00774   * @brief Ensure that IRDA communication mode is valid.
00775   * @param __MODE__ IRDA communication mode.
00776   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00777   */
00778 #define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
00779
00780 /**
00781   * @brief Ensure that IRDA power mode is valid.
00782   * @param __MODE__ IRDA power mode.
00783   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00784   */
00785 #define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
00786                                      ((__MODE__) == IRDA_POWERMODE_NORMAL))
00787
00788 /**
00789   * @brief Ensure that IRDA clock Prescaler is valid.
00790   * @param __CLOCKPRESCALER__ IRDA clock Prescaler value.
00791   * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
00792   */
00793 #define IS_IRDA_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV1) || \
00794               ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV2)   || \
00795               ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV4)   || \
00796               ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV6)   || \
00797               ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV8)   || \
00798               ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV10)  || \
00799               ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV12)  || \
00800               ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV16)  || \
00801               ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV32)  || \
00802               ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV64)  || \
00803               ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV128) || \
00804               ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV256))
00805
00806 /**
00807   * @brief Ensure that IRDA state is valid.
00808   * @param __STATE__ IRDA state mode.
00809   * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
00810   */
00811 #define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \
00812                                   ((__STATE__) == IRDA_STATE_ENABLE))
00813
00814 /**
00815   * @brief Ensure that IRDA associated UART/USART mode is valid.
00816   * @param __MODE__ IRDA associated UART/USART mode.
00817   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00818   */
00819 #define IS_IRDA_MODE(__MODE__)  (((__MODE__) == IRDA_MODE_DISABLE) || \
00820                                  ((__MODE__) == IRDA_MODE_ENABLE))
00821
00822 /**
00823   * @brief Ensure that IRDA sampling rate is valid.
00824   * @param __ONEBIT__ IRDA sampling rate.
00825   * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
00826   */
00827 #define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__)      (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
00828                                                  ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))
00829
00830 /**
00831   * @brief Ensure that IRDA DMA TX mode is valid.
00832   * @param __DMATX__ IRDA DMA TX mode.
00833   * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
00834   */
00835 #define IS_IRDA_DMA_TX(__DMATX__)     (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
00836                                        ((__DMATX__) == IRDA_DMA_TX_ENABLE))
00837
00838 /**
00839   * @brief Ensure that IRDA DMA RX mode is valid.
00840   * @param __DMARX__ IRDA DMA RX mode.
00841   * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
00842   */
00843 #define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
00844                                    ((__DMARX__) == IRDA_DMA_RX_ENABLE))
00845
00846 /**
00847   * @brief Ensure that IRDA request is valid.
00848   * @param __PARAM__ IRDA request.
00849   * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
00850   */
00851 #define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \
00852                                               ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
00853                                               ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))
00854 /**
00855  * @}
00856  */
00857
00858 /* Include IRDA HAL Extended module */
00859 #include "stm32wbxx_hal_irda_ex.h"
00860
00861 /* Exported functions --------------------------------------------------------*/
00862 /** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
00863   * @{
00864   */
00865
00866 /** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
00867   * @{
00868   */
00869
00870 /* Initialization and de-initialization functions  ****************************/
00871 HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
00872 HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
00873 void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
00874 void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
00875
00876 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
00877 /* Callbacks Register/UnRegister functions  ***********************************/
00878 HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback);
00879 HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID);
00880 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
00881
00882 /**
00883   * @}
00884   */
00885
00886 /** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions
00887   * @{
00888   */
00889
00890 /* IO operation functions *****************************************************/
00891 HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00892 HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00893 HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
00894 HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
00895 HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
00896 HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
00897 HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
00898 HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
00899 HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
00900 /* Transfer Abort functions */
00901 HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
00902 HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
00903 HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
00904 HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
00905 HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
00906 HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
00907
00908 void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
00909 void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
00910 void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
00911 void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
00912 void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
00913 void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
00914 void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda);
00915 void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda);
00916 void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda);
00917
00918 /**
00919   * @}
00920   */
00921
00922 /* Peripheral Control functions  ************************************************/
00923
00924 /** @addtogroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
00925   * @{
00926   */
00927
00928 /* Peripheral State and Error functions ***************************************/
00929 HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
00930 uint32_t              HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
00931
00932 /**
00933   * @}
00934   */
00935
00936 /**
00937   * @}
00938   */
00939
00940 /**
00941   * @}
00942   */
00943
00944 /**
00945   * @}
00946   */
00947
00948 #ifdef __cplusplus
00949 }
00950 #endif
00951
00952 #endif /* STM32WBxx_HAL_IRDA_H */
00953
00954 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_irda_ex.h Source File

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stm32wbxx_hal_irda_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_irda_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of IRDA HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_IRDA_EX_H
00022 #define STM32WBxx_HAL_IRDA_EX_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 /** @addtogroup STM32WBxx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @defgroup IRDAEx IRDAEx
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /* Exported constants --------------------------------------------------------*/
00041 /* Exported macros -----------------------------------------------------------*/
00042 /* Exported functions --------------------------------------------------------*/
00043
00044 /* Private macros ------------------------------------------------------------*/
00045
00046 /** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros
00047   * @{
00048   */
00049
00050 /** @brief  Report the IRDA clock source.
00051   * @param  __HANDLE__ specifies the IRDA Handle.
00052   * @param  __CLOCKSOURCE__ output variable.
00053   * @retval IRDA clocking source, written in __CLOCKSOURCE__.
00054   */
00055 #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)        \
00056   do {                                                         \
00057     if((__HANDLE__)->Instance == USART1)                       \
00058     {                                                          \
00059        switch(__HAL_RCC_GET_USART1_SOURCE())                   \
00060        {                                                       \
00061         case RCC_USART1CLKSOURCE_PCLK2:                        \
00062           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2;          \
00063           break;                                               \
00064         case RCC_USART1CLKSOURCE_HSI:                          \
00065           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;            \
00066           break;                                               \
00067         case RCC_USART1CLKSOURCE_SYSCLK:                       \
00068           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;         \
00069           break;                                               \
00070         case RCC_USART1CLKSOURCE_LSE:                          \
00071           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;            \
00072           break;                                               \
00073         default:                                               \
00074           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;      \
00075           break;                                               \
00076        }                                                       \
00077     }                                                          \
00078     else                                                       \
00079     {                                                          \
00080       (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;          \
00081     }                                                          \
00082   } while(0U)
00083
00084 /**
00085   * @}
00086   */
00087
00088 /* Exported functions --------------------------------------------------------*/
00089
00090 /**
00091   * @}
00092   */
00093
00094 /**
00095   * @}
00096   */
00097
00098 #ifdef __cplusplus
00099 }
00100 #endif
00101
00102 #endif /* STM32WBxx_HAL_IRDA_EX_H */
00103
00104 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_iwdg.c Source File

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stm32wbxx_hal_iwdg.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_iwdg.c
00004   * @author  MCD Application Team
00005   * @brief   IWDG HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Independent Watchdog (IWDG) peripheral:
00008   *           + Initialization and Start functions
00009   *           + IO operation functions
00010   *
00011   @verbatim
00012   ==============================================================================
00013                     ##### IWDG Generic features #####
00014   ==============================================================================
00015   [..]
00016     (+) The IWDG can be started by either software or hardware (configurable
00017         through option byte).
00018
00019     (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
00020         if the main clock fails.
00021
00022     (+) Once the IWDG is started, the LSI is forced ON and both can not be
00023         disabled. The counter starts counting down from the reset value (0xFFF).
00024         When it reaches the end of count value (0x000) a reset signal is
00025         generated (IWDG reset).
00026
00027     (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
00028         the IWDG_RLR value is reloaded in the counter and the watchdog reset is
00029         prevented.
00030
00031     (+) The IWDG is implemented in the VDD voltage domain that is still functional
00032         in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
00033         IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
00034         reset occurs.
00035
00036     (+) Debug mode : When the microcontroller enters debug mode (core halted),
00037         the IWDG counter either continues to work normally or stops, depending
00038         on DBG_IWDG_STOP configuration bit in DBG module, accessible through
00039         __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros.
00040
00041     [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
00042          The IWDG timeout may vary due to LSI frequency dispersion. STM32WBxx
00043          devices provide the capability to measure the LSI frequency (LSI clock
00044          connected internally to TIM16 CH1 input capture). The measured value
00045          can be used to have an IWDG timeout with an acceptable accuracy.
00046
00047                      ##### How to use this driver #####
00048   ==============================================================================
00049   [..]
00050     (#) Use IWDG using HAL_IWDG_Init() function to :
00051       (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
00052            clock is forced ON and IWDG counter starts counting down.
00053       (++) Enable write access to configuration registers:
00054           IWDG_PR, IWDG_RLR and IWDG_WINR.
00055       (++) Configure the IWDG prescaler and counter reload value. This reload
00056            value will be loaded in the IWDG counter each time the watchdog is
00057            reloaded, then the IWDG will start counting down from this value.
00058       (++) Wait for status flags to be reset.
00059       (++) Depending on window parameter:
00060         (+++) If Window Init parameter is same as Window register value,
00061              nothing more is done but reload counter value in order to exit
00062              function with exact time base.
00063         (+++) Else modify Window register. This will automatically reload
00064              watchdog counter.
00065
00066     (#) Then the application program must refresh the IWDG counter at regular
00067         intervals during normal operation to prevent an MCU reset, using
00068         HAL_IWDG_Refresh() function.
00069
00070      *** IWDG HAL driver macros list ***
00071      ====================================
00072      [..]
00073        Below the list of most used macros in IWDG HAL driver:
00074       (+) __HAL_IWDG_START: Enable the IWDG peripheral
00075       (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
00076           the reload register
00077
00078   @endverbatim
00079   ******************************************************************************
00080   * @attention
00081   *
00082   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00083   * All rights reserved.</center></h2>
00084   *
00085   * This software component is licensed by ST under BSD 3-Clause license,
00086   * the "License"; You may not use this file except in compliance with the
00087   * License. You may obtain a copy of the License at:
00088   *                        opensource.org/licenses/BSD-3-Clause
00089   *
00090   ******************************************************************************
00091   */
00092
00093 /* Includes ------------------------------------------------------------------*/
00094 #include "stm32wbxx_hal.h"
00095
00096 /** @addtogroup STM32WBxx_HAL_Driver
00097   * @{
00098   */
00099
00100 #ifdef HAL_IWDG_MODULE_ENABLED
00101 /** @addtogroup IWDG
00102   * @brief IWDG HAL module driver.
00103   * @{
00104   */
00105
00106 /* Private typedef -----------------------------------------------------------*/
00107 /* Private define ------------------------------------------------------------*/
00108 /** @defgroup IWDG_Private_Defines IWDG Private Defines
00109   * @{
00110   */
00111 /* Status register need 5 RC LSI divided by prescaler clock to be updated. With
00112    higher prescaler (256), and according to LSI variation, we need to wait at
00113    least 6 cycles so 48 ms. */
00114 #define HAL_IWDG_DEFAULT_TIMEOUT            48u
00115 /**
00116   * @}
00117   */
00118
00119 /* Private macro -------------------------------------------------------------*/
00120 /* Private variables ---------------------------------------------------------*/
00121 /* Private function prototypes -----------------------------------------------*/
00122 /* Exported functions --------------------------------------------------------*/
00123
00124 /** @addtogroup IWDG_Exported_Functions
00125   * @{
00126   */
00127
00128 /** @addtogroup IWDG_Exported_Functions_Group1
00129  *  @brief    Initialization and Start functions.
00130  *
00131 @verbatim
00132  ===============================================================================
00133           ##### Initialization and Start functions #####
00134  ===============================================================================
00135  [..]  This section provides functions allowing to:
00136       (+) Initialize the IWDG according to the specified parameters in the
00137           IWDG_InitTypeDef of associated handle.
00138       (+) Manage Window option.
00139       (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
00140           is reloaded in order to exit function with correct time base.
00141
00142 @endverbatim
00143   * @{
00144   */
00145
00146 /**
00147   * @brief  Initialize the IWDG according to the specified parameters in the
00148   *         IWDG_InitTypeDef and start watchdog. Before exiting function,
00149   *         watchdog is refreshed in order to have correct time base.
00150   * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
00151   *                the configuration information for the specified IWDG module.
00152   * @retval HAL status
00153   */
00154 HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
00155 {
00156   uint32_t tickstart;
00157
00158   /* Check the IWDG handle allocation */
00159   if (hiwdg == NULL)
00160   {
00161     return HAL_ERROR;
00162   }
00163
00164   /* Check the parameters */
00165   assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
00166   assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
00167   assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
00168   assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
00169
00170   /* Enable IWDG. LSI is turned on automatically */
00171   __HAL_IWDG_START(hiwdg);
00172
00173   /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing
00174   0x5555 in KR */
00175   IWDG_ENABLE_WRITE_ACCESS(hiwdg);
00176
00177   /* Write to IWDG registers the Prescaler & Reload values to work with */
00178   hiwdg->Instance->PR = hiwdg->Init.Prescaler;
00179   hiwdg->Instance->RLR = hiwdg->Init.Reload;
00180
00181   /* Check pending flag, if previous update not done, return timeout */
00182   tickstart = HAL_GetTick();
00183
00184   /* Wait for register to be updated */
00185   while (hiwdg->Instance->SR != 0x00u)
00186   {
00187     if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
00188     {
00189       return HAL_TIMEOUT;
00190     }
00191   }
00192
00193   /* If window parameter is different than current value, modify window
00194   register */
00195   if (hiwdg->Instance->WINR != hiwdg->Init.Window)
00196   {
00197     /* Write to IWDG WINR the IWDG_Window value to compare with. In any case,
00198     even if window feature is disabled, Watchdog will be reloaded by writing
00199     windows register */
00200     hiwdg->Instance->WINR = hiwdg->Init.Window;
00201   }
00202   else
00203   {
00204     /* Reload IWDG counter with value defined in the reload register */
00205     __HAL_IWDG_RELOAD_COUNTER(hiwdg);
00206   }
00207
00208   /* Return function status */
00209   return HAL_OK;
00210 }
00211
00212 /**
00213   * @}
00214   */
00215
00216
00217 /** @addtogroup IWDG_Exported_Functions_Group2
00218  *  @brief   IO operation functions
00219  *
00220 @verbatim
00221  ===============================================================================
00222                       ##### IO operation functions #####
00223  ===============================================================================
00224  [..]  This section provides functions allowing to:
00225       (+) Refresh the IWDG.
00226
00227 @endverbatim
00228   * @{
00229   */
00230
00231
00232 /**
00233   * @brief  Refresh the IWDG.
00234   * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
00235   *                the configuration information for the specified IWDG module.
00236   * @retval HAL status
00237   */
00238 HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
00239 {
00240   /* Reload IWDG counter with value defined in the reload register */
00241   __HAL_IWDG_RELOAD_COUNTER(hiwdg);
00242
00243   /* Return function status */
00244   return HAL_OK;
00245 }
00246
00247 /**
00248   * @}
00249   */
00250
00251 /**
00252   * @}
00253   */
00254
00255 #endif /* HAL_IWDG_MODULE_ENABLED */
00256 /**
00257   * @}
00258   */
00259
00260 /**
00261   * @}
00262   */
00263
00264 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_iwdg.h Source File

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stm32wbxx_hal_iwdg.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_iwdg.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of IWDG HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_IWDG_H
00022 #define STM32WBxx_HAL_IWDG_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 /** @addtogroup STM32WBxx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @defgroup IWDG IWDG
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup IWDG_Exported_Types IWDG Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief  IWDG Init structure definition
00046   */
00047 typedef struct
00048 {
00049   uint32_t Prescaler;  /*!< Select the prescaler of the IWDG.
00050                             This parameter can be a value of @ref IWDG_Prescaler */
00051
00052   uint32_t Reload;     /*!< Specifies the IWDG down-counter reload value.
00053                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
00054
00055   uint32_t Window;     /*!< Specifies the window value to be compared to the down-counter.
00056                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
00057
00058 } IWDG_InitTypeDef;
00059
00060 /**
00061   * @brief  IWDG Handle Structure definition
00062   */
00063 typedef struct
00064 {
00065   IWDG_TypeDef                 *Instance;  /*!< Register base address    */
00066
00067   IWDG_InitTypeDef             Init;       /*!< IWDG required parameters */
00068 } IWDG_HandleTypeDef;
00069
00070
00071 /**
00072   * @}
00073   */
00074
00075 /* Exported constants --------------------------------------------------------*/
00076 /** @defgroup IWDG_Exported_Constants IWDG Exported Constants
00077   * @{
00078   */
00079
00080 /** @defgroup IWDG_Prescaler IWDG Prescaler
00081   * @{
00082   */
00083 #define IWDG_PRESCALER_4                0x00000000u                                     /*!< IWDG prescaler set to 4   */
00084 #define IWDG_PRESCALER_8                IWDG_PR_PR_0                                    /*!< IWDG prescaler set to 8   */
00085 #define IWDG_PRESCALER_16               IWDG_PR_PR_1                                    /*!< IWDG prescaler set to 16  */
00086 #define IWDG_PRESCALER_32               (IWDG_PR_PR_1 | IWDG_PR_PR_0)                   /*!< IWDG prescaler set to 32  */
00087 #define IWDG_PRESCALER_64               IWDG_PR_PR_2                                    /*!< IWDG prescaler set to 64  */
00088 #define IWDG_PRESCALER_128              (IWDG_PR_PR_2 | IWDG_PR_PR_0)                   /*!< IWDG prescaler set to 128 */
00089 #define IWDG_PRESCALER_256              (IWDG_PR_PR_2 | IWDG_PR_PR_1)                   /*!< IWDG prescaler set to 256 */
00090
00091 /**
00092   * @}
00093   */
00094
00095 /** @defgroup IWDG_Window_option IWDG Window option
00096   * @{
00097   */
00098 #define IWDG_WINDOW_DISABLE             IWDG_WINR_WIN
00099 /**
00100   * @}
00101   */
00102
00103
00104 /**
00105   * @}
00106   */
00107
00108 /* Exported macros -----------------------------------------------------------*/
00109 /** @defgroup IWDG_Exported_Macros IWDG Exported Macros
00110   * @{
00111   */
00112
00113 /**
00114   * @brief  Enable the IWDG peripheral.
00115   * @param  __HANDLE__  IWDG handle
00116   * @retval None
00117   */
00118 #define __HAL_IWDG_START(__HANDLE__)                WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
00119
00120 /**
00121   * @brief  Reload IWDG counter with value defined in the reload register
00122   *         (write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers disabled).
00123   * @param  __HANDLE__  IWDG handle
00124   * @retval None
00125   */
00126 #define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__)       WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
00127
00128 /**
00129   * @}
00130   */
00131
00132 /* Exported functions --------------------------------------------------------*/
00133 /** @defgroup IWDG_Exported_Functions  IWDG Exported Functions
00134   * @{
00135   */
00136
00137 /** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
00138   * @{
00139   */
00140 /* Initialization/Start functions  ********************************************/
00141 HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
00142 /**
00143   * @}
00144   */
00145
00146 /** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
00147   * @{
00148   */
00149 /* I/O operation functions ****************************************************/
00150 HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
00151 /**
00152   * @}
00153   */
00154
00155 /**
00156   * @}
00157   */
00158
00159 /* Private constants ---------------------------------------------------------*/
00160 /** @defgroup IWDG_Private_Constants IWDG Private Constants
00161   * @{
00162   */
00163
00164 /**
00165   * @brief  IWDG Key Register BitMask
00166   */
00167 #define IWDG_KEY_RELOAD                 0x0000AAAAu  /*!< IWDG Reload Counter Enable   */
00168 #define IWDG_KEY_ENABLE                 0x0000CCCCu  /*!< IWDG Peripheral Enable       */
00169 #define IWDG_KEY_WRITE_ACCESS_ENABLE    0x00005555u  /*!< IWDG KR Write Access Enable  */
00170 #define IWDG_KEY_WRITE_ACCESS_DISABLE   0x00000000u  /*!< IWDG KR Write Access Disable */
00171
00172 /**
00173   * @}
00174   */
00175
00176 /* Private macros ------------------------------------------------------------*/
00177 /** @defgroup IWDG_Private_Macros IWDG Private Macros
00178   * @{
00179   */
00180
00181 /**
00182   * @brief  Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
00183   * @param  __HANDLE__  IWDG handle
00184   * @retval None
00185   */
00186 #define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__)  WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
00187
00188 /**
00189   * @brief  Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
00190   * @param  __HANDLE__  IWDG handle
00191   * @retval None
00192   */
00193 #define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
00194
00195 /**
00196   * @brief  Check IWDG prescaler value.
00197   * @param  __PRESCALER__  IWDG prescaler value
00198   * @retval None
00199   */
00200 #define IS_IWDG_PRESCALER(__PRESCALER__)      (((__PRESCALER__) == IWDG_PRESCALER_4)  || \
00201                                                ((__PRESCALER__) == IWDG_PRESCALER_8)  || \
00202                                                ((__PRESCALER__) == IWDG_PRESCALER_16) || \
00203                                                ((__PRESCALER__) == IWDG_PRESCALER_32) || \
00204                                                ((__PRESCALER__) == IWDG_PRESCALER_64) || \
00205                                                ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
00206                                                ((__PRESCALER__) == IWDG_PRESCALER_256))
00207
00208 /**
00209   * @brief  Check IWDG reload value.
00210   * @param  __RELOAD__  IWDG reload value
00211   * @retval None
00212   */
00213 #define IS_IWDG_RELOAD(__RELOAD__)            ((__RELOAD__) <= IWDG_RLR_RL)
00214
00215 /**
00216   * @brief  Check IWDG window value.
00217   * @param  __WINDOW__  IWDG window value
00218   * @retval None
00219   */
00220 #define IS_IWDG_WINDOW(__WINDOW__)            ((__WINDOW__) <= IWDG_WINR_WIN)
00221
00222
00223 /**
00224   * @}
00225   */
00226
00227 /**
00228   * @}
00229   */
00230
00231 /**
00232   * @}
00233   */
00234
00235
00236 #ifdef __cplusplus
00237 }
00238 #endif
00239
00240 #endif /* STM32WBxx_HAL_IWDG_H */
00241
00242 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_lcd.c Source File

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stm32wbxx_hal_lcd.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_lcd.c
00004   * @author  MCD Application Team
00005   * @brief   LCD Controller HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the LCD Controller (LCD) peripheral:
00008   *           + Initialization/de-initialization methods
00009   *           + I/O operation methods
00010   *           + Peripheral State methods
00011   *
00012   @verbatim
00013   ==============================================================================
00014                         ##### How to use this driver #####
00015   ==============================================================================
00016       [..] The LCD HAL driver can be used as follows:
00017
00018       (#) Declare a LCD_HandleTypeDef handle structure.
00019
00020       -@- The frequency generator allows you to achieve various LCD frame rates
00021           starting from an LCD input clock frequency (LCDCLK) which can vary
00022           from 32 kHz up to 1 MHz.
00023
00024       (#) Initialize the LCD low level resources by implementing the HAL_LCD_MspInit() API:
00025
00026           (++) Enable the LCDCLK (same as RTCCLK): to configure the RTCCLK/LCDCLK, proceed as follows:
00027                (+++) Use RCC function HAL_RCCEx_PeriphCLKConfig in indicating RCC_PERIPHCLK_LCD and
00028                   selected clock source (HSE, LSI or LSE)
00029
00030           (++) LCD pins configuration:
00031               (+++) Enable the clock for the LCD GPIOs.
00032               (+++) Configure these LCD pins as alternate function no-pull.
00033           (++) Enable the LCD interface clock.
00034
00035
00036       (#) Program the Prescaler, Divider, Blink mode, Blink Frequency Duty, Bias,
00037           Voltage Source, Dead Time, Pulse On Duration, Contrast, High drive and Multiplexer
00038           Segment in the Init structure of the LCD handle.
00039
00040       (#) Initialize the LCD registers by calling the HAL_LCD_Init() API.
00041
00042       -@- The HAL_LCD_Init() API configures also the low level Hardware GPIO, CLOCK, ...etc)
00043           by calling the customized HAL_LCD_MspInit() API.
00044       -@- After calling the HAL_LCD_Init() the LCD RAM memory is cleared
00045
00046       (#) Optionally you can update the LCD configuration using these macros:
00047               (++) LCD High Drive using the __HAL_LCD_HIGHDRIVER_ENABLE() and __HAL_LCD_HIGHDRIVER_DISABLE() macros
00048               (++) Voltage output buffer using __HAL_LCD_VOLTAGE_BUFFER_ENABLE() and __HAL_LCD_VOLTAGE_BUFFER_DISABLE() macros
00049               (++) LCD Pulse ON Duration using the __HAL_LCD_PULSEONDURATION_CONFIG() macro
00050               (++) LCD Dead Time using the __HAL_LCD_DEADTIME_CONFIG() macro
00051               (++) The LCD Blink mode and frequency using the __HAL_LCD_BLINK_CONFIG() macro
00052               (++) The LCD Contrast using the __HAL_LCD_CONTRAST_CONFIG() macro
00053
00054       (#) Write to the LCD RAM memory using the HAL_LCD_Write() API, this API can be called
00055           more time to update the different LCD RAM registers before calling
00056           HAL_LCD_UpdateDisplayRequest() API.
00057
00058       (#) The HAL_LCD_Clear() API can be used to clear the LCD RAM memory.
00059
00060       (#) When LCD RAM memory is updated enable the update display request using
00061           the HAL_LCD_UpdateDisplayRequest() API.
00062
00063       [..] LCD and low power modes:
00064            (#) The LCD remain active during Sleep, Low Power run, Low Power Sleep and
00065                STOP modes.
00066
00067   @endverbatim
00068   ******************************************************************************
00069   * @attention
00070   *
00071   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00072   * All rights reserved.</center></h2>
00073   *
00074   * This software component is licensed by ST under BSD 3-Clause license,
00075   * the "License"; You may not use this file except in compliance with the
00076   * License. You may obtain a copy of the License at:
00077   *                        opensource.org/licenses/BSD-3-Clause
00078   *
00079   ******************************************************************************
00080   */
00081
00082 /* Includes ------------------------------------------------------------------*/
00083 #include "stm32wbxx_hal.h"
00084
00085
00086 /** @addtogroup STM32WBxx_HAL_Driver
00087   * @{
00088   */
00089
00090 #ifdef HAL_LCD_MODULE_ENABLED
00091
00092 #if defined (LCD)
00093
00094 /** @defgroup LCD LCD
00095   * @brief LCD HAL module driver
00096   * @{
00097   */
00098
00099 /* Private typedef -----------------------------------------------------------*/
00100 /* Private define ------------------------------------------------------------*/
00101 /** @defgroup LCD_Private_Defines LCD Private Defines
00102   * @{
00103   */
00104
00105 #define LCD_TIMEOUT_VALUE             1000U
00106
00107 /**
00108   * @}
00109   */
00110
00111 /* Private macro -------------------------------------------------------------*/
00112 /* Private variables ---------------------------------------------------------*/
00113 /* Private function prototypes -----------------------------------------------*/
00114 /* Exported functions --------------------------------------------------------*/
00115
00116 /** @defgroup LCD_Exported_Functions LCD Exported Functions
00117   * @{
00118   */
00119
00120 /** @defgroup LCD_Exported_Functions_Group1 Initialization/de-initialization methods
00121   *  @brief    Initialization and Configuration functions
00122   *
00123 @verbatim
00124 ===============================================================================
00125             ##### Initialization and Configuration functions #####
00126  ===============================================================================
00127     [..]
00128
00129 @endverbatim
00130   * @{
00131   */
00132
00133 /**
00134   * @brief  Initialize the LCD peripheral according to the specified parameters
00135   *         in the LCD_InitStruct and initialize the associated handle.
00136   * @note   This function can be used only when the LCD is disabled.
00137   * @param hlcd LCD handle
00138   * @retval None
00139   */
00140 HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd)
00141 {
00142   uint32_t tickstart;
00143   uint32_t counter;
00144   HAL_StatusTypeDef status;
00145
00146   /* Check the LCD handle allocation */
00147   if (hlcd == NULL)
00148   {
00149     return HAL_ERROR;
00150   }
00151
00152   /* Check function parameters */
00153   assert_param(IS_LCD_ALL_INSTANCE(hlcd->Instance));
00154   assert_param(IS_LCD_PRESCALER(hlcd->Init.Prescaler));
00155   assert_param(IS_LCD_DIVIDER(hlcd->Init.Divider));
00156   assert_param(IS_LCD_DUTY(hlcd->Init.Duty));
00157   assert_param(IS_LCD_BIAS(hlcd->Init.Bias));
00158   assert_param(IS_LCD_VOLTAGE_SOURCE(hlcd->Init.VoltageSource));
00159   assert_param(IS_LCD_PULSE_ON_DURATION(hlcd->Init.PulseOnDuration));
00160   assert_param(IS_LCD_HIGH_DRIVE(hlcd->Init.HighDrive));
00161   assert_param(IS_LCD_DEAD_TIME(hlcd->Init.DeadTime));
00162   assert_param(IS_LCD_CONTRAST(hlcd->Init.Contrast));
00163   assert_param(IS_LCD_BLINK_FREQUENCY(hlcd->Init.BlinkFrequency));
00164   assert_param(IS_LCD_BLINK_MODE(hlcd->Init.BlinkMode));
00165   assert_param(IS_LCD_MUX_SEGMENT(hlcd->Init.MuxSegment));
00166
00167   if (hlcd->State == HAL_LCD_STATE_RESET)
00168   {
00169     /* Allocate lock resource and initialize it */
00170     hlcd->Lock = HAL_UNLOCKED;
00171
00172     /* Initialize the low level hardware (MSP) */
00173     HAL_LCD_MspInit(hlcd);
00174   }
00175
00176   hlcd->State = HAL_LCD_STATE_BUSY;
00177
00178   /* Disable the peripheral */
00179   __HAL_LCD_DISABLE(hlcd);
00180
00181   /* Clear the LCD_RAM registers and enable the display request by setting the UDR bit
00182      in the LCD_SR register */
00183   for (counter = LCD_RAM_REGISTER0; counter <= LCD_RAM_REGISTER7; counter++)
00184   {
00185     hlcd->Instance->RAM[counter] = 0;
00186   }
00187   /* Enable the display request */
00188   /* hlcd->Instance->SR |= LCD_SR_UDR */
00189   /* Configure the LCD Prescaler, Divider, Blink mode and Blink Frequency:
00190      Set PS[3:0] bits according to hlcd->Init.Prescaler value
00191      Set DIV[3:0] bits according to hlcd->Init.Divider value
00192      Set BLINK[1:0] bits according to hlcd->Init.BlinkMode value
00193      Set BLINKF[2:0] bits according to hlcd->Init.BlinkFrequency value
00194      Set DEAD[2:0] bits according to hlcd->Init.DeadTime value
00195      Set PON[2:0] bits according to hlcd->Init.PulseOnDuration value
00196      Set CC[2:0] bits according to hlcd->Init.Contrast value
00197      Set HD bit according to hlcd->Init.HighDrive value */
00198   MODIFY_REG(hlcd->Instance->FCR, \
00199              (LCD_FCR_PS | LCD_FCR_DIV | LCD_FCR_BLINK | LCD_FCR_BLINKF | \
00200               LCD_FCR_DEAD | LCD_FCR_PON | LCD_FCR_CC | LCD_FCR_HD), \
00201              (hlcd->Init.Prescaler | hlcd->Init.Divider | hlcd->Init.BlinkMode | hlcd->Init.BlinkFrequency | \
00202               hlcd->Init.DeadTime | hlcd->Init.PulseOnDuration | hlcd->Init.Contrast | hlcd->Init.HighDrive));
00203
00204   /* Wait until LCD Frame Control Register Synchronization flag (FCRSF) is set in the LCD_SR register
00205      This bit is set by hardware each time the LCD_FCR register is updated in the LCDCLK
00206      domain. It is cleared by hardware when writing to the LCD_FCR register.*/
00207   status = LCD_WaitForSynchro(hlcd);
00208   if (status != HAL_OK)
00209   {
00210     return status;
00211   }
00212
00213   /* Configure the LCD Duty, Bias, Voltage Source, Dead Time, Pulse On Duration and Contrast:
00214      Set DUTY[2:0] bits according to hlcd->Init.Duty value
00215      Set BIAS[1:0] bits according to hlcd->Init.Bias value
00216      Set VSEL bit according to hlcd->Init.VoltageSource value
00217      Set MUX_SEG bit according to hlcd->Init.MuxSegment value */
00218   MODIFY_REG(hlcd->Instance->CR, \
00219              (LCD_CR_DUTY | LCD_CR_BIAS | LCD_CR_VSEL | LCD_CR_MUX_SEG), \
00220              (hlcd->Init.Duty | hlcd->Init.Bias | hlcd->Init.VoltageSource | hlcd->Init.MuxSegment));
00221
00222   /* Enable the peripheral */
00223   __HAL_LCD_ENABLE(hlcd);
00224
00225   /* Get timeout */
00226   tickstart = HAL_GetTick();
00227
00228   /* Wait Until the LCD is enabled */
00229   while (__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_ENS) == RESET)
00230   {
00231     if ((HAL_GetTick() - tickstart) > LCD_TIMEOUT_VALUE)
00232     {
00233       hlcd->ErrorCode = HAL_LCD_ERROR_ENS;
00234       return HAL_TIMEOUT;
00235     }
00236   }
00237
00238   /* Get timeout */
00239   tickstart = HAL_GetTick();
00240
00241   /*!< Wait Until the LCD Booster is ready */
00242   while (__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_RDY) == RESET)
00243   {
00244     if ((HAL_GetTick() - tickstart) > LCD_TIMEOUT_VALUE)
00245     {
00246       hlcd->ErrorCode = HAL_LCD_ERROR_RDY;
00247       return HAL_TIMEOUT;
00248     }
00249   }
00250
00251   /* Initialize the LCD state */
00252   hlcd->ErrorCode = HAL_LCD_ERROR_NONE;
00253   hlcd->State = HAL_LCD_STATE_READY;
00254
00255   return status;
00256 }
00257
00258 /**
00259   * @brief  DeInitialize the LCD peripheral.
00260   * @param hlcd LCD handle
00261   * @retval HAL status
00262   */
00263 HAL_StatusTypeDef HAL_LCD_DeInit(LCD_HandleTypeDef *hlcd)
00264 {
00265   /* Check the LCD handle allocation */
00266   if (hlcd == NULL)
00267   {
00268     return HAL_ERROR;
00269   }
00270
00271   /* Check the parameters */
00272   assert_param(IS_LCD_ALL_INSTANCE(hlcd->Instance));
00273
00274   hlcd->State = HAL_LCD_STATE_BUSY;
00275
00276   /* DeInit the low level hardware */
00277   HAL_LCD_MspDeInit(hlcd);
00278
00279   hlcd->ErrorCode = HAL_LCD_ERROR_NONE;
00280   hlcd->State = HAL_LCD_STATE_RESET;
00281
00282   /* Release Lock */
00283   __HAL_UNLOCK(hlcd);
00284
00285   return HAL_OK;
00286 }
00287
00288 /**
00289   * @brief  DeInitialize the LCD MSP.
00290   * @param hlcd LCD handle
00291   * @retval None
00292   */
00293 __weak void HAL_LCD_MspDeInit(LCD_HandleTypeDef *hlcd)
00294 {
00295   /* Prevent unused argument(s) compilation warning */
00296   UNUSED(hlcd);
00297
00298   /* NOTE: This function should not be modified, when the callback is needed,
00299            the HAL_LCD_MspDeInit it to be implemented in the user file
00300    */
00301 }
00302
00303 /**
00304   * @brief  Initialize the LCD MSP.
00305   * @param hlcd LCD handle
00306   * @retval None
00307   */
00308 __weak void HAL_LCD_MspInit(LCD_HandleTypeDef *hlcd)
00309 {
00310   /* Prevent unused argument(s) compilation warning */
00311   UNUSED(hlcd);
00312
00313   /* NOTE: This function should not be modified, when the callback is needed,
00314            the HAL_LCD_MspInit is to be implemented in the user file
00315    */
00316 }
00317
00318 /**
00319   * @}
00320   */
00321
00322 /** @defgroup LCD_Exported_Functions_Group2 IO operation methods
00323   *  @brief LCD RAM functions
00324   *
00325 @verbatim
00326  ===============================================================================
00327                       ##### IO operation functions #####
00328  ===============================================================================
00329  [..] Using its double buffer memory the LCD controller ensures the coherency of the
00330  displayed information without having to use interrupts to control LCD_RAM
00331  modification.
00332  The application software can access the first buffer level (LCD_RAM) through
00333  the APB interface. Once it has modified the LCD_RAM using the HAL_LCD_Write() API,
00334  it sets the UDR flag in the LCD_SR register using the HAL_LCD_UpdateDisplayRequest() API.
00335  This UDR flag (update display request) requests the updated information to be
00336  moved into the second buffer level (LCD_DISPLAY).
00337  This operation is done synchronously with the frame (at the beginning of the
00338  next frame), until the update is completed, the LCD_RAM is write protected and
00339  the UDR flag stays high.
00340  Once the update is completed another flag (UDD - Update Display Done) is set and
00341  generates an interrupt if the UDDIE bit in the LCD_FCR register is set.
00342  The time it takes to update LCD_DISPLAY is, in the worst case, one odd and one
00343  even frame.
00344  The update will not occur (UDR = 1 and UDD = 0) until the display is
00345  enabled (LCDEN = 1).
00346
00347 @endverbatim
00348   * @{
00349   */
00350
00351 /**
00352   * @brief  Write a word in the specific LCD RAM.
00353   * @param hlcd LCD handle
00354   * @param RAMRegisterIndex specifies the LCD RAM Register.
00355   *   This parameter can be one of the following values:
00356   *     @arg LCD_RAM_REGISTER0: LCD RAM Register 0
00357   *     @arg LCD_RAM_REGISTER1: LCD RAM Register 1
00358   *     @arg LCD_RAM_REGISTER2: LCD RAM Register 2
00359   *     @arg LCD_RAM_REGISTER3: LCD RAM Register 3
00360   *     @arg LCD_RAM_REGISTER4: LCD RAM Register 4
00361   *     @arg LCD_RAM_REGISTER5: LCD RAM Register 5
00362   *     @arg LCD_RAM_REGISTER6: LCD RAM Register 6
00363   *     @arg LCD_RAM_REGISTER7: LCD RAM Register 7
00364   *     @arg LCD_RAM_REGISTER8: LCD RAM Register 8
00365   *     @arg LCD_RAM_REGISTER9: LCD RAM Register 9
00366   *     @arg LCD_RAM_REGISTER10: LCD RAM Register 10
00367   *     @arg LCD_RAM_REGISTER11: LCD RAM Register 11
00368   *     @arg LCD_RAM_REGISTER12: LCD RAM Register 12
00369   *     @arg LCD_RAM_REGISTER13: LCD RAM Register 13
00370   *     @arg LCD_RAM_REGISTER14: LCD RAM Register 14
00371   *     @arg LCD_RAM_REGISTER15: LCD RAM Register 15
00372   * @param RAMRegisterMask specifies the LCD RAM Register Data Mask.
00373   * @param Data specifies LCD Data Value to be written.
00374   * @retval None
00375   */
00376 HAL_StatusTypeDef HAL_LCD_Write(LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterIndex, uint32_t RAMRegisterMask, uint32_t Data)
00377 {
00378   uint32_t tickstart;
00379   HAL_LCD_StateTypeDef state = hlcd->State;
00380
00381   if ((state == HAL_LCD_STATE_READY) || (state == HAL_LCD_STATE_BUSY))
00382   {
00383     /* Check the parameters */
00384     assert_param(IS_LCD_RAM_REGISTER(RAMRegisterIndex));
00385
00386     if (hlcd->State == HAL_LCD_STATE_READY)
00387     {
00388       /* Process Locked */
00389       __HAL_LOCK(hlcd);
00390       hlcd->State = HAL_LCD_STATE_BUSY;
00391
00392       /* Get timeout */
00393       tickstart = HAL_GetTick();
00394
00395       /*!< Wait Until the LCD is ready */
00396       while (__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_UDR) != RESET)
00397       {
00398         if ((HAL_GetTick() - tickstart) > LCD_TIMEOUT_VALUE)
00399         {
00400           hlcd->ErrorCode = HAL_LCD_ERROR_UDR;
00401
00402           /* Process Unlocked */
00403           __HAL_UNLOCK(hlcd);
00404
00405           return HAL_TIMEOUT;
00406         }
00407       }
00408     }
00409
00410     /* Copy the new Data bytes to LCD RAM register */
00411     MODIFY_REG(hlcd->Instance->RAM[RAMRegisterIndex], ~(RAMRegisterMask), Data);
00412
00413     return HAL_OK;
00414   }
00415   else
00416   {
00417     return HAL_ERROR;
00418   }
00419 }
00420
00421 /**
00422   * @brief Clear the LCD RAM registers.
00423   * @param hlcd LCD handle
00424   * @retval None
00425   */
00426 HAL_StatusTypeDef HAL_LCD_Clear(LCD_HandleTypeDef *hlcd)
00427 {
00428   uint32_t tickstart;
00429   uint32_t counter;
00430   HAL_StatusTypeDef status = HAL_ERROR;
00431   HAL_LCD_StateTypeDef state = hlcd->State;
00432
00433   if ((state == HAL_LCD_STATE_READY) || (state == HAL_LCD_STATE_BUSY))
00434   {
00435     /* Process Locked */
00436     __HAL_LOCK(hlcd);
00437
00438     hlcd->State = HAL_LCD_STATE_BUSY;
00439
00440     /* Get timeout */
00441     tickstart = HAL_GetTick();
00442
00443     /*!< Wait Until the LCD is ready */
00444     while (__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_UDR) != RESET)
00445     {
00446       if ((HAL_GetTick() - tickstart) > LCD_TIMEOUT_VALUE)
00447       {
00448         hlcd->ErrorCode = HAL_LCD_ERROR_UDR;
00449
00450         /* Process Unlocked */
00451         __HAL_UNLOCK(hlcd);
00452
00453         return HAL_TIMEOUT;
00454       }
00455     }
00456     /* Clear the LCD_RAM registers */
00457     for (counter = LCD_RAM_REGISTER0; counter <= LCD_RAM_REGISTER15; counter++)
00458     {
00459       hlcd->Instance->RAM[counter] = 0;
00460     }
00461
00462     /* Update the LCD display */
00463     status = HAL_LCD_UpdateDisplayRequest(hlcd);
00464   }
00465   return status;
00466 }
00467
00468 /**
00469   * @brief  Enable the Update Display Request.
00470   * @param hlcd LCD handle
00471   * @note   Each time software modifies the LCD_RAM it must set the UDR bit to
00472   *         transfer the updated data to the second level buffer.
00473   *         The UDR bit stays set until the end of the update and during this
00474   *         time the LCD_RAM is write protected.
00475   * @note   When the display is disabled, the update is performed for all
00476   *         LCD_DISPLAY locations.
00477   *         When the display is enabled, the update is performed only for locations
00478   *         for which commons are active (depending on DUTY). For example if
00479   *         DUTY = 1/2, only the LCD_DISPLAY of COM0 and COM1 will be updated.
00480   * @retval None
00481   */
00482 HAL_StatusTypeDef HAL_LCD_UpdateDisplayRequest(LCD_HandleTypeDef *hlcd)
00483 {
00484   uint32_t tickstart;
00485
00486   /* Clear the Update Display Done flag before starting the update display request */
00487   __HAL_LCD_CLEAR_FLAG(hlcd, LCD_FLAG_UDD);
00488
00489   /* Enable the display request */
00490   hlcd->Instance->SR |= LCD_SR_UDR;
00491
00492   /* Get timeout */
00493   tickstart = HAL_GetTick();
00494
00495   /*!< Wait Until the LCD display is done */
00496   while (__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_UDD) == RESET)
00497   {
00498     if ((HAL_GetTick() - tickstart) > LCD_TIMEOUT_VALUE)
00499     {
00500       hlcd->ErrorCode = HAL_LCD_ERROR_UDD;
00501
00502       /* Process Unlocked */
00503       __HAL_UNLOCK(hlcd);
00504
00505       return HAL_TIMEOUT;
00506     }
00507   }
00508
00509   hlcd->State = HAL_LCD_STATE_READY;
00510
00511   /* Process Unlocked */
00512   __HAL_UNLOCK(hlcd);
00513
00514   return HAL_OK;
00515 }
00516
00517 /**
00518   * @}
00519   */
00520
00521 /** @defgroup LCD_Exported_Functions_Group3 Peripheral State methods
00522   *  @brief   LCD State functions
00523   *
00524 @verbatim
00525  ===============================================================================
00526                       ##### Peripheral State functions #####
00527  ===============================================================================
00528     [..]
00529      This subsection provides a set of functions allowing to control the LCD:
00530       (+) HAL_LCD_GetState() API can be helpful to check in run-time the state of the LCD peripheral State.
00531       (+) HAL_LCD_GetError() API to return the LCD error code.
00532 @endverbatim
00533   * @{
00534   */
00535
00536 /**
00537   * @brief Return the LCD handle state.
00538   * @param hlcd LCD handle
00539   * @retval HAL state
00540   */
00541 HAL_LCD_StateTypeDef HAL_LCD_GetState(LCD_HandleTypeDef *hlcd)
00542 {
00543   /* Return LCD handle state */
00544   return hlcd->State;
00545 }
00546
00547 /**
00548   * @brief Return the LCD error code.
00549   * @param hlcd LCD handle
00550   * @retval LCD Error Code
00551   */
00552 uint32_t HAL_LCD_GetError(LCD_HandleTypeDef *hlcd)
00553 {
00554   return hlcd->ErrorCode;
00555 }
00556
00557 /**
00558   * @}
00559   */
00560
00561 /**
00562   * @}
00563   */
00564
00565 /** @defgroup LCD_Private_Functions LCD Private Functions
00566   * @{
00567   */
00568
00569 /**
00570   * @brief  Wait until the LCD FCR register is synchronized in the LCDCLK domain.
00571   *   This function must be called after any write operation to LCD_FCR register.
00572   * @retval None
00573   */
00574 HAL_StatusTypeDef LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd)
00575 {
00576   uint32_t tickstart;
00577
00578   /* Get timeout */
00579   tickstart = HAL_GetTick();
00580
00581   /* Loop until FCRSF flag is set */
00582   while (__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_FCRSF) == RESET)
00583   {
00584     if ((HAL_GetTick() - tickstart) > LCD_TIMEOUT_VALUE)
00585     {
00586       hlcd->ErrorCode = HAL_LCD_ERROR_FCRSF;
00587       return HAL_TIMEOUT;
00588     }
00589   }
00590
00591   return HAL_OK;
00592 }
00593
00594 /**
00595   * @}
00596   */
00597
00598 /**
00599   * @}
00600   */
00601
00602 #endif /* LCD */
00603
00604 #endif /* HAL_LCD_MODULE_ENABLED */
00605
00606 /**
00607   * @}
00608   */
00609
00610
00611 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_lcd.h Source File

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stm32wbxx_hal_lcd.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_lcd.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of LCD Controller HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_LCD_H
00022 #define STM32WBxx_HAL_LCD_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028
00029 /* Includes ------------------------------------------------------------------*/
00030 #include "stm32wbxx_hal_def.h"
00031
00032 /** @addtogroup STM32WBxx_HAL_Driver
00033   * @{
00034   */
00035
00036 #if defined (LCD)
00037
00038 /** @addtogroup LCD
00039   * @{
00040   */
00041
00042 /* Exported types ------------------------------------------------------------*/
00043 /** @defgroup LCD_Exported_Types LCD Exported Types
00044   * @{
00045   */
00046
00047 /**
00048   * @brief LCD Init structure definition
00049   */
00050
00051 typedef struct
00052 {
00053   uint32_t Prescaler;       /*!< Configures the LCD Prescaler.
00054                                  This parameter can be one value of @ref LCD_Prescaler */
00055   uint32_t Divider;         /*!< Configures the LCD Divider.
00056                                  This parameter can be one value of @ref LCD_Divider */
00057   uint32_t Duty;            /*!< Configures the LCD Duty.
00058                                  This parameter can be one value of @ref LCD_Duty */
00059   uint32_t Bias;            /*!< Configures the LCD Bias.
00060                                  This parameter can be one value of @ref LCD_Bias */
00061   uint32_t VoltageSource;   /*!< Selects the LCD Voltage source.
00062                                  This parameter can be one value of @ref LCD_Voltage_Source */
00063   uint32_t Contrast;        /*!< Configures the LCD Contrast.
00064                                  This parameter can be one value of @ref LCD_Contrast */
00065   uint32_t DeadTime;        /*!< Configures the LCD Dead Time.
00066                                  This parameter can be one value of @ref LCD_DeadTime */
00067   uint32_t PulseOnDuration; /*!< Configures the LCD Pulse On Duration.
00068                                  This parameter can be one value of @ref LCD_PulseOnDuration */
00069   uint32_t HighDrive;       /*!< Enable or disable the low resistance divider.
00070                                  This parameter can be one value of @ref LCD_HighDrive */
00071   uint32_t BlinkMode;       /*!< Configures the LCD Blink Mode.
00072                                  This parameter can be one value of @ref LCD_BlinkMode */
00073   uint32_t BlinkFrequency;  /*!< Configures the LCD Blink frequency.
00074                                  This parameter can be one value of @ref LCD_BlinkFrequency */
00075   uint32_t MuxSegment;      /*!< Enable or disable mux segment.
00076                                  This parameter can be one value of @ref LCD_MuxSegment */
00077 } LCD_InitTypeDef;
00078
00079 /**
00080   * @brief HAL LCD State structures definition
00081   */
00082 typedef enum
00083 {
00084   HAL_LCD_STATE_RESET             = 0x00,    /*!< Peripheral is not yet Initialized */
00085   HAL_LCD_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use */
00086   HAL_LCD_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing */
00087   HAL_LCD_STATE_TIMEOUT           = 0x03,    /*!< Timeout state */
00088   HAL_LCD_STATE_ERROR             = 0x04     /*!< Error */
00089 } HAL_LCD_StateTypeDef;
00090
00091 /**
00092   * @brief  UART handle Structure definition
00093   */
00094 typedef struct
00095 {
00096   LCD_TypeDef                   *Instance;  /* LCD registers base address */
00097
00098   LCD_InitTypeDef               Init;       /* LCD communication parameters */
00099
00100   HAL_LockTypeDef               Lock;       /* Locking object */
00101
00102   __IO HAL_LCD_StateTypeDef     State;      /* LCD communication state */
00103
00104   __IO uint32_t                 ErrorCode;  /* LCD Error code */
00105
00106 } LCD_HandleTypeDef;
00107 /**
00108   * @}
00109   */
00110
00111 /* Exported constants --------------------------------------------------------*/
00112 /** @defgroup LCD_Exported_Constants LCD Exported Constants
00113   * @{
00114   */
00115
00116 /** @defgroup  LCD_ErrorCode LCD Error Code
00117   * @{
00118   */
00119 #define HAL_LCD_ERROR_NONE       (0x00000000U)    /*!< No error */
00120 #define HAL_LCD_ERROR_FCRSF      (0x00000001U)    /*!< Synchro flag timeout error */
00121 #define HAL_LCD_ERROR_UDR        (0x00000002U)    /*!< Update display request flag timeout error */
00122 #define HAL_LCD_ERROR_UDD        (0x00000004U)    /*!< Update display done flag timeout error */
00123 #define HAL_LCD_ERROR_ENS        (0x00000008U)    /*!< LCD enabled status flag timeout error */
00124 #define HAL_LCD_ERROR_RDY        (0x00000010U)    /*!< LCD Booster ready timeout error */
00125 /**
00126   * @}
00127   */
00128
00129 /** @defgroup LCD_Prescaler LCD Prescaler
00130   * @{
00131   */
00132 #define LCD_PRESCALER_1        (0x00000000U)  /*!< CLKPS = LCDCLK        */
00133 #define LCD_PRESCALER_2        (0x00400000U)  /*!< CLKPS = LCDCLK/2      */
00134 #define LCD_PRESCALER_4        (0x00800000U)  /*!< CLKPS = LCDCLK/4      */
00135 #define LCD_PRESCALER_8        (0x00C00000U)  /*!< CLKPS = LCDCLK/8      */
00136 #define LCD_PRESCALER_16       (0x01000000U)  /*!< CLKPS = LCDCLK/16     */
00137 #define LCD_PRESCALER_32       (0x01400000U)  /*!< CLKPS = LCDCLK/32     */
00138 #define LCD_PRESCALER_64       (0x01800000U)  /*!< CLKPS = LCDCLK/64     */
00139 #define LCD_PRESCALER_128      (0x01C00000U)  /*!< CLKPS = LCDCLK/128    */
00140 #define LCD_PRESCALER_256      (0x02000000U)  /*!< CLKPS = LCDCLK/256    */
00141 #define LCD_PRESCALER_512      (0x02400000U)  /*!< CLKPS = LCDCLK/512    */
00142 #define LCD_PRESCALER_1024     (0x02800000U)  /*!< CLKPS = LCDCLK/1024   */
00143 #define LCD_PRESCALER_2048     (0x02C00000U)  /*!< CLKPS = LCDCLK/2048   */
00144 #define LCD_PRESCALER_4096     (0x03000000U)  /*!< CLKPS = LCDCLK/4096   */
00145 #define LCD_PRESCALER_8192     (0x03400000U)  /*!< CLKPS = LCDCLK/8192   */
00146 #define LCD_PRESCALER_16384    (0x03800000U)  /*!< CLKPS = LCDCLK/16384  */
00147 #define LCD_PRESCALER_32768    (0x03C00000U)  /*!< CLKPS = LCDCLK/32768  */
00148 /**
00149   * @}
00150   */
00151
00152 /** @defgroup LCD_Divider LCD Divider
00153   * @{
00154   */
00155 #define LCD_DIVIDER_16    (0x00000000U)  /*!< LCD frequency = CLKPS/16 */
00156 #define LCD_DIVIDER_17    (0x00040000U)  /*!< LCD frequency = CLKPS/17 */
00157 #define LCD_DIVIDER_18    (0x00080000U)  /*!< LCD frequency = CLKPS/18 */
00158 #define LCD_DIVIDER_19    (0x000C0000U)  /*!< LCD frequency = CLKPS/19 */
00159 #define LCD_DIVIDER_20    (0x00100000U)  /*!< LCD frequency = CLKPS/20 */
00160 #define LCD_DIVIDER_21    (0x00140000U)  /*!< LCD frequency = CLKPS/21 */
00161 #define LCD_DIVIDER_22    (0x00180000U)  /*!< LCD frequency = CLKPS/22 */
00162 #define LCD_DIVIDER_23    (0x001C0000U)  /*!< LCD frequency = CLKPS/23 */
00163 #define LCD_DIVIDER_24    (0x00200000U)  /*!< LCD frequency = CLKPS/24 */
00164 #define LCD_DIVIDER_25    (0x00240000U)  /*!< LCD frequency = CLKPS/25 */
00165 #define LCD_DIVIDER_26    (0x00280000U)  /*!< LCD frequency = CLKPS/26 */
00166 #define LCD_DIVIDER_27    (0x002C0000U)  /*!< LCD frequency = CLKPS/27 */
00167 #define LCD_DIVIDER_28    (0x00300000U)  /*!< LCD frequency = CLKPS/28 */
00168 #define LCD_DIVIDER_29    (0x00340000U)  /*!< LCD frequency = CLKPS/29 */
00169 #define LCD_DIVIDER_30    (0x00380000U)  /*!< LCD frequency = CLKPS/30 */
00170 #define LCD_DIVIDER_31    (0x003C0000U)  /*!< LCD frequency = CLKPS/31 */
00171 /**
00172   * @}
00173   */
00174
00175
00176 /** @defgroup LCD_Duty LCD Duty
00177   * @{
00178   */
00179 #define LCD_DUTY_STATIC                 (0x00000000U)                     /*!< Static duty */
00180 #define LCD_DUTY_1_2                    (LCD_CR_DUTY_0)                   /*!< 1/2 duty    */
00181 #define LCD_DUTY_1_3                    (LCD_CR_DUTY_1)                   /*!< 1/3 duty    */
00182 #define LCD_DUTY_1_4                    ((LCD_CR_DUTY_1 | LCD_CR_DUTY_0)) /*!< 1/4 duty    */
00183 #define LCD_DUTY_1_8                    (LCD_CR_DUTY_2)                   /*!< 1/8 duty    */
00184 /**
00185   * @}
00186   */
00187
00188
00189 /** @defgroup LCD_Bias LCD Bias
00190   * @{
00191   */
00192 #define LCD_BIAS_1_4                    (0x00000000U) /*!< 1/4 Bias */
00193 #define LCD_BIAS_1_2                    LCD_CR_BIAS_0 /*!< 1/2 Bias */
00194 #define LCD_BIAS_1_3                    LCD_CR_BIAS_1 /*!< 1/3 Bias */
00195 /**
00196   * @}
00197   */
00198
00199 /** @defgroup LCD_Voltage_Source LCD Voltage Source
00200   * @{
00201   */
00202 #define LCD_VOLTAGESOURCE_INTERNAL      (0x00000000U)  /*!< Internal voltage source for the LCD */
00203 #define LCD_VOLTAGESOURCE_EXTERNAL      LCD_CR_VSEL    /*!< External voltage source for the LCD */
00204 /**
00205   * @}
00206   */
00207
00208 /** @defgroup LCD_Interrupts LCD Interrupts
00209   * @{
00210   */
00211 #define LCD_IT_SOF                      LCD_FCR_SOFIE
00212 #define LCD_IT_UDD                      LCD_FCR_UDDIE
00213 /**
00214   * @}
00215   */
00216
00217 /** @defgroup LCD_PulseOnDuration LCD Pulse On Duration
00218   * @{
00219   */
00220 #define LCD_PULSEONDURATION_0           (0x00000000U)                   /*!< Pulse ON duration = 0 pulse  */
00221 #define LCD_PULSEONDURATION_1           (LCD_FCR_PON_0)                 /*!< Pulse ON duration = 1/CK_PS  */
00222 #define LCD_PULSEONDURATION_2           (LCD_FCR_PON_1)                 /*!< Pulse ON duration = 2/CK_PS  */
00223 #define LCD_PULSEONDURATION_3           (LCD_FCR_PON_1 | LCD_FCR_PON_0) /*!< Pulse ON duration = 3/CK_PS  */
00224 #define LCD_PULSEONDURATION_4           (LCD_FCR_PON_2)                 /*!< Pulse ON duration = 4/CK_PS  */
00225 #define LCD_PULSEONDURATION_5           (LCD_FCR_PON_2 | LCD_FCR_PON_0) /*!< Pulse ON duration = 5/CK_PS  */
00226 #define LCD_PULSEONDURATION_6           (LCD_FCR_PON_2 | LCD_FCR_PON_1) /*!< Pulse ON duration = 6/CK_PS  */
00227 #define LCD_PULSEONDURATION_7           (LCD_FCR_PON)                   /*!< Pulse ON duration = 7/CK_PS  */
00228 /**
00229   * @}
00230   */
00231
00232
00233 /** @defgroup LCD_DeadTime LCD Dead Time
00234   * @{
00235   */
00236 #define LCD_DEADTIME_0                  (0x00000000U)                     /*!< No dead Time                                  */
00237 #define LCD_DEADTIME_1                  (LCD_FCR_DEAD_0)                  /*!< One Phase between different couple of Frame   */
00238 #define LCD_DEADTIME_2                  (LCD_FCR_DEAD_1)                  /*!< Two Phase between different couple of Frame   */
00239 #define LCD_DEADTIME_3                  (LCD_FCR_DEAD_1 | LCD_FCR_DEAD_0) /*!< Three Phase between different couple of Frame */
00240 #define LCD_DEADTIME_4                  (LCD_FCR_DEAD_2)                  /*!< Four Phase between different couple of Frame  */
00241 #define LCD_DEADTIME_5                  (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_0) /*!< Five Phase between different couple of Frame  */
00242 #define LCD_DEADTIME_6                  (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_1) /*!< Six Phase between different couple of Frame   */
00243 #define LCD_DEADTIME_7                  (LCD_FCR_DEAD)                    /*!< Seven Phase between different couple of Frame */
00244 /**
00245   * @}
00246   */
00247
00248 /** @defgroup LCD_BlinkMode LCD Blink Mode
00249   * @{
00250   */
00251 #define LCD_BLINKMODE_OFF               (0x00000000U)           /*!< Blink disabled                                     */
00252 #define LCD_BLINKMODE_SEG0_COM0         (LCD_FCR_BLINK_0)       /*!< Blink enabled on SEG[0], COM[0] (1 pixel)          */
00253 #define LCD_BLINKMODE_SEG0_ALLCOM       (LCD_FCR_BLINK_1)       /*!< Blink enabled on SEG[0], all COM (up to
00254                                                                     8 pixels according to the programmed duty)          */
00255 #define LCD_BLINKMODE_ALLSEG_ALLCOM     (LCD_FCR_BLINK)         /*!< Blink enabled on all SEG and all COM (all pixels)  */
00256 /**
00257   * @}
00258   */
00259
00260 /** @defgroup LCD_BlinkFrequency LCD Blink Frequency
00261   * @{
00262   */
00263 #define LCD_BLINKFREQUENCY_DIV8         (0x00000000U)                         /*!< The Blink frequency = fLCD/8    */
00264 #define LCD_BLINKFREQUENCY_DIV16        (LCD_FCR_BLINKF_0)                    /*!< The Blink frequency = fLCD/16   */
00265 #define LCD_BLINKFREQUENCY_DIV32        (LCD_FCR_BLINKF_1)                    /*!< The Blink frequency = fLCD/32   */
00266 #define LCD_BLINKFREQUENCY_DIV64        (LCD_FCR_BLINKF_1 | LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/64   */
00267 #define LCD_BLINKFREQUENCY_DIV128       (LCD_FCR_BLINKF_2)                    /*!< The Blink frequency = fLCD/128  */
00268 #define LCD_BLINKFREQUENCY_DIV256       (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_0)  /*!< The Blink frequency = fLCD/256  */
00269 #define LCD_BLINKFREQUENCY_DIV512       (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_1)  /*!< The Blink frequency = fLCD/512  */
00270 #define LCD_BLINKFREQUENCY_DIV1024      (LCD_FCR_BLINKF)                      /*!< The Blink frequency = fLCD/1024 */
00271 /**
00272   * @}
00273   */
00274
00275 /** @defgroup LCD_Contrast LCD Contrast
00276   * @{
00277   */
00278 #define LCD_CONTRASTLEVEL_0               (0x00000000U)                 /*!< Maximum Voltage = 2.60V    */
00279 #define LCD_CONTRASTLEVEL_1               (LCD_FCR_CC_0)                /*!< Maximum Voltage = 2.73V    */
00280 #define LCD_CONTRASTLEVEL_2               (LCD_FCR_CC_1)                /*!< Maximum Voltage = 2.86V    */
00281 #define LCD_CONTRASTLEVEL_3               (LCD_FCR_CC_1 | LCD_FCR_CC_0) /*!< Maximum Voltage = 2.99V    */
00282 #define LCD_CONTRASTLEVEL_4               (LCD_FCR_CC_2)                /*!< Maximum Voltage = 3.12V    */
00283 #define LCD_CONTRASTLEVEL_5               (LCD_FCR_CC_2 | LCD_FCR_CC_0) /*!< Maximum Voltage = 3.26V    */
00284 #define LCD_CONTRASTLEVEL_6               (LCD_FCR_CC_2 | LCD_FCR_CC_1) /*!< Maximum Voltage = 3.40V    */
00285 #define LCD_CONTRASTLEVEL_7               (LCD_FCR_CC)                  /*!< Maximum Voltage = 3.55V    */
00286 /**
00287   * @}
00288   */
00289
00290 /** @defgroup LCD_RAMRegister LCD RAMRegister
00291   * @{
00292   */
00293 #define LCD_RAM_REGISTER0               (0x00000000U) /*!< LCD RAM Register 0  */
00294 #define LCD_RAM_REGISTER1               (0x00000001U) /*!< LCD RAM Register 1  */
00295 #define LCD_RAM_REGISTER2               (0x00000002U) /*!< LCD RAM Register 2  */
00296 #define LCD_RAM_REGISTER3               (0x00000003U) /*!< LCD RAM Register 3  */
00297 #define LCD_RAM_REGISTER4               (0x00000004U) /*!< LCD RAM Register 4  */
00298 #define LCD_RAM_REGISTER5               (0x00000005U) /*!< LCD RAM Register 5  */
00299 #define LCD_RAM_REGISTER6               (0x00000006U) /*!< LCD RAM Register 6  */
00300 #define LCD_RAM_REGISTER7               (0x00000007U) /*!< LCD RAM Register 7  */
00301 #define LCD_RAM_REGISTER8               (0x00000008U) /*!< LCD RAM Register 8  */
00302 #define LCD_RAM_REGISTER9               (0x00000009U) /*!< LCD RAM Register 9  */
00303 #define LCD_RAM_REGISTER10              (0x0000000AU) /*!< LCD RAM Register 10 */
00304 #define LCD_RAM_REGISTER11              (0x0000000BU) /*!< LCD RAM Register 11 */
00305 #define LCD_RAM_REGISTER12              (0x0000000CU) /*!< LCD RAM Register 12 */
00306 #define LCD_RAM_REGISTER13              (0x0000000DU) /*!< LCD RAM Register 13 */
00307 #define LCD_RAM_REGISTER14              (0x0000000EU) /*!< LCD RAM Register 14 */
00308 #define LCD_RAM_REGISTER15              (0x0000000FU) /*!< LCD RAM Register 15 */
00309 /**
00310   * @}
00311   */
00312
00313 /** @defgroup LCD_HighDrive LCD High Drive
00314   * @{
00315   */
00316
00317 #define LCD_HIGHDRIVE_DISABLE             ((uint32_t)0x00000000)        /*!< High drive disabled */
00318 #define LCD_HIGHDRIVE_ENABLE              (LCD_FCR_HD)                  /*!< High drive enabled  */
00319 /**
00320   * @}
00321   */
00322
00323 /** @defgroup LCD_MuxSegment LCD Mux Segment
00324   * @{
00325   */
00326
00327 #define LCD_MUXSEGMENT_DISABLE            (0x00000000U)                 /*!< SEG pin multiplexing disabled                 */
00328 #define LCD_MUXSEGMENT_ENABLE             (LCD_CR_MUX_SEG)              /*!< SEG[31:28] are multiplexed with SEG[43:40]    */
00329 /**
00330   * @}
00331   */
00332
00333 /** @defgroup LCD_Flag_Definition LCD Flags Definition
00334   * @{
00335   */
00336 #define LCD_FLAG_ENS                    LCD_SR_ENS   /*!< LCD enabled status */
00337 #define LCD_FLAG_SOF                    LCD_SR_SOF   /*!< Start of frame flag */
00338 #define LCD_FLAG_UDR                    LCD_SR_UDR   /*!< Update display request */
00339 #define LCD_FLAG_UDD                    LCD_SR_UDD   /*!< Update display done */
00340 #define LCD_FLAG_RDY                    LCD_SR_RDY   /*!< Ready flag */
00341 #define LCD_FLAG_FCRSF                  LCD_SR_FCRSR /*!< LCD Frame Control Register Synchronization flag */
00342 /**
00343   * @}
00344   */
00345
00346 /**
00347   * @}
00348   */
00349
00350 /* Exported macros -----------------------------------------------------------*/
00351 /** @defgroup LCD_Exported_Macros LCD Exported Macros
00352   * @{
00353   */
00354
00355 /** @brief Reset LCD handle state.
00356   * @param __HANDLE__ specifies the LCD Handle.
00357   * @retval None
00358   */
00359 #define __HAL_LCD_RESET_HANDLE_STATE(__HANDLE__)  ((__HANDLE__)->State = HAL_LCD_STATE_RESET)
00360
00361 /** @brief  Enable the LCD peripheral.
00362   * @param __HANDLE__ specifies the LCD Handle.
00363   * @retval None
00364   */
00365 #define __HAL_LCD_ENABLE(__HANDLE__)              SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN)
00366
00367 /** @brief  Disable the LCD peripheral.
00368   * @param __HANDLE__ specifies the LCD Handle.
00369   * @retval None
00370   */
00371 #define __HAL_LCD_DISABLE(__HANDLE__)             CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN)
00372
00373 /** @brief  Enable the low resistance divider.
00374   * @param __HANDLE__ specifies the LCD Handle.
00375   * @note   Displays with high internal resistance may need a longer drive time to
00376   *         achieve satisfactory contrast. This function is useful in this case if
00377   *         some additional power consumption can be tolerated.
00378   * @note   When this mode is enabled, the PulseOn Duration (PON) have to be
00379   *         programmed to 1/CK_PS (LCD_PULSEONDURATION_1).
00380   * @retval None
00381   */
00382 #define __HAL_LCD_HIGHDRIVER_ENABLE(__HANDLE__)                       \
00383                   do {                                                \
00384                     SET_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
00385                     LCD_WaitForSynchro(__HANDLE__);                   \
00386                   } while(0)
00387
00388 /** @brief  Disable the low resistance divider.
00389   * @param __HANDLE__ specifies the LCD Handle.
00390   * @retval None
00391   */
00392 #define __HAL_LCD_HIGHDRIVER_DISABLE(__HANDLE__)                        \
00393                   do {                                                  \
00394                     CLEAR_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
00395                     LCD_WaitForSynchro(__HANDLE__);                     \
00396                   } while(0)
00397
00398 /** @brief  Enable the voltage output buffer for higher driving capability.
00399   * @param __HANDLE__ specifies the LCD Handle.
00400   * @retval None
00401   */
00402 #define __HAL_LCD_VOLTAGE_BUFFER_ENABLE(__HANDLE__)   SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_BUFEN)
00403
00404 /** @brief  Disable the voltage output buffer for higher driving capability.
00405   * @param __HANDLE__ specifies the LCD Handle.
00406   * @retval None
00407   */
00408 #define __HAL_LCD_VOLTAGE_BUFFER_DISABLE(__HANDLE__)  CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_BUFEN)
00409
00410 /**
00411   * @brief  Configure the LCD pulse on duration.
00412   * @param __HANDLE__ specifies the LCD Handle.
00413   * @param __DURATION__ specifies the LCD pulse on duration in terms of
00414   *         CK_PS (prescaled LCD clock period) pulses.
00415   *   This parameter can be one of the following values:
00416   *     @arg LCD_PULSEONDURATION_0: 0 pulse
00417   *     @arg LCD_PULSEONDURATION_1: Pulse ON duration = 1/CK_PS
00418   *     @arg LCD_PULSEONDURATION_2: Pulse ON duration = 2/CK_PS
00419   *     @arg LCD_PULSEONDURATION_3: Pulse ON duration = 3/CK_PS
00420   *     @arg LCD_PULSEONDURATION_4: Pulse ON duration = 4/CK_PS
00421   *     @arg LCD_PULSEONDURATION_5: Pulse ON duration = 5/CK_PS
00422   *     @arg LCD_PULSEONDURATION_6: Pulse ON duration = 6/CK_PS
00423   *     @arg LCD_PULSEONDURATION_7: Pulse ON duration = 7/CK_PS
00424   * @retval None
00425   */
00426 #define __HAL_LCD_PULSEONDURATION_CONFIG(__HANDLE__, __DURATION__)                        \
00427                   do {                                                                    \
00428                     MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_PON, (__DURATION__)); \
00429                     LCD_WaitForSynchro(__HANDLE__);                                       \
00430                   } while(0)
00431
00432 /**
00433   * @brief  Configure the LCD dead time.
00434   * @param __HANDLE__ specifies the LCD Handle.
00435   * @param __DEADTIME__ specifies the LCD dead time.
00436   *   This parameter can be one of the following values:
00437   *     @arg LCD_DEADTIME_0: No dead Time
00438   *     @arg LCD_DEADTIME_1: One Phase between different couple of Frame
00439   *     @arg LCD_DEADTIME_2: Two Phase between different couple of Frame
00440   *     @arg LCD_DEADTIME_3: Three Phase between different couple of Frame
00441   *     @arg LCD_DEADTIME_4: Four Phase between different couple of Frame
00442   *     @arg LCD_DEADTIME_5: Five Phase between different couple of Frame
00443   *     @arg LCD_DEADTIME_6: Six Phase between different couple of Frame
00444   *     @arg LCD_DEADTIME_7: Seven Phase between different couple of Frame
00445   * @retval None
00446   */
00447 #define __HAL_LCD_DEADTIME_CONFIG(__HANDLE__, __DEADTIME__)                                \
00448                   do {                                                                     \
00449                     MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_DEAD, (__DEADTIME__)); \
00450                     LCD_WaitForSynchro(__HANDLE__);                                        \
00451                   } while(0)
00452
00453 /**
00454   * @brief  Configure the LCD contrast.
00455   * @param __HANDLE__ specifies the LCD Handle.
00456   * @param __CONTRAST__ specifies the LCD Contrast.
00457   *   This parameter can be one of the following values:
00458   *     @arg LCD_CONTRASTLEVEL_0: Maximum Voltage = 2.60V
00459   *     @arg LCD_CONTRASTLEVEL_1: Maximum Voltage = 2.73V
00460   *     @arg LCD_CONTRASTLEVEL_2: Maximum Voltage = 2.86V
00461   *     @arg LCD_CONTRASTLEVEL_3: Maximum Voltage = 2.99V
00462   *     @arg LCD_CONTRASTLEVEL_4: Maximum Voltage = 3.12V
00463   *     @arg LCD_CONTRASTLEVEL_5: Maximum Voltage = 3.25V
00464   *     @arg LCD_CONTRASTLEVEL_6: Maximum Voltage = 3.38V
00465   *     @arg LCD_CONTRASTLEVEL_7: Maximum Voltage = 3.51V
00466   * @retval None
00467   */
00468 #define __HAL_LCD_CONTRAST_CONFIG(__HANDLE__, __CONTRAST__)                           \
00469               do {                                                                    \
00470                 MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_CC, (__CONTRAST__));  \
00471                 LCD_WaitForSynchro(__HANDLE__);                                       \
00472               } while(0)
00473
00474 /**
00475   * @brief  Configure the LCD Blink mode and Blink frequency.
00476   * @param __HANDLE__ specifies the LCD Handle.
00477   * @param __BLINKMODE__ specifies the LCD blink mode.
00478   *   This parameter can be one of the following values:
00479   *     @arg LCD_BLINKMODE_OFF:           Blink disabled
00480   *     @arg LCD_BLINKMODE_SEG0_COM0:     Blink enabled on SEG[0], COM[0] (1 pixel)
00481   *     @arg LCD_BLINKMODE_SEG0_ALLCOM:   Blink enabled on SEG[0], all COM (up to 8
00482   *                                       pixels according to the programmed duty)
00483   *     @arg LCD_BLINKMODE_ALLSEG_ALLCOM: Blink enabled on all SEG and all COM
00484   *                                       (all pixels)
00485   * @param __BLINKFREQUENCY__ specifies the LCD blink frequency.
00486   *     @arg LCD_BLINKFREQUENCY_DIV8:    The Blink frequency = fLcd/8
00487   *     @arg LCD_BLINKFREQUENCY_DIV16:   The Blink frequency = fLcd/16
00488   *     @arg LCD_BLINKFREQUENCY_DIV32:   The Blink frequency = fLcd/32
00489   *     @arg LCD_BLINKFREQUENCY_DIV64:   The Blink frequency = fLcd/64
00490   *     @arg LCD_BLINKFREQUENCY_DIV128:  The Blink frequency = fLcd/128
00491   *     @arg LCD_BLINKFREQUENCY_DIV256:  The Blink frequency = fLcd/256
00492   *     @arg LCD_BLINKFREQUENCY_DIV512:  The Blink frequency = fLcd/512
00493   *     @arg LCD_BLINKFREQUENCY_DIV1024: The Blink frequency = fLcd/1024
00494   * @retval None
00495   */
00496 #define __HAL_LCD_BLINK_CONFIG(__HANDLE__, __BLINKMODE__, __BLINKFREQUENCY__)         \
00497               do {                                                                    \
00498                 MODIFY_REG((__HANDLE__)->Instance->FCR, (LCD_FCR_BLINKF | LCD_FCR_BLINK), ((__BLINKMODE__) | (__BLINKFREQUENCY__))); \
00499                 LCD_WaitForSynchro(__HANDLE__);                                       \
00500               } while(0)
00501
00502 /** @brief  Enable the specified LCD interrupt.
00503   * @param __HANDLE__ specifies the LCD Handle.
00504   * @param __INTERRUPT__ specifies the LCD interrupt source to be enabled.
00505   *          This parameter can be one of the following values:
00506   *     @arg LCD_IT_SOF: Start of Frame Interrupt
00507   *     @arg LCD_IT_UDD: Update Display Done Interrupt
00508   * @retval None
00509   */
00510 #define __HAL_LCD_ENABLE_IT(__HANDLE__, __INTERRUPT__)                      \
00511                   do {                                                      \
00512                     SET_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__));  \
00513                     LCD_WaitForSynchro(__HANDLE__);                         \
00514                   } while(0)
00515
00516 /** @brief  Disable the specified LCD interrupt.
00517   * @param __HANDLE__ specifies the LCD Handle.
00518   * @param __INTERRUPT__ specifies the LCD interrupt source to be disabled.
00519   *          This parameter can be one of the following values:
00520   *     @arg LCD_IT_SOF: Start of Frame Interrupt
00521   *     @arg LCD_IT_UDD: Update Display Done Interrupt
00522   * @retval None
00523   */
00524 #define __HAL_LCD_DISABLE_IT(__HANDLE__, __INTERRUPT__)                      \
00525                   do {                                                       \
00526                     CLEAR_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__)); \
00527                     LCD_WaitForSynchro(__HANDLE__);                          \
00528                   } while(0)
00529
00530 /** @brief  Check whether the specified LCD interrupt source is enabled or not.
00531   * @param __HANDLE__ specifies the LCD Handle.
00532   * @param __IT__ specifies the LCD interrupt source to check.
00533   *        This parameter can be one of the following values:
00534   *        @arg LCD_IT_SOF: Start of Frame Interrupt
00535   *        @arg LCD_IT_UDD: Update Display Done Interrupt.
00536   * @note If the device is in STOP mode (PCLK not provided) UDD will not
00537   *          generate an interrupt even if UDDIE = 1.
00538   *          If the display is not enabled the UDD interrupt will never occur.
00539   * @retval The state of __IT__ (TRUE or FALSE).
00540   */
00541 #define __HAL_LCD_GET_IT_SOURCE(__HANDLE__, __IT__) (((__HANDLE__)->Instance->FCR) & (__IT__))
00542
00543 /** @brief  Check whether the specified LCD flag is set or not.
00544   * @param __HANDLE__ specifies the LCD Handle.
00545   * @param __FLAG__ specifies the flag to check.
00546   *        This parameter can be one of the following values:
00547   *        @arg LCD_FLAG_ENS: LCD Enabled flag. It indicates the LCD controller status.
00548   * @note  The ENS bit is set immediately when the LCDEN bit in the LCD_CR
00549   *             goes from 0 to 1. On deactivation it reflects the real status of
00550   *             LCD so it becomes 0 at the end of the last displayed frame.
00551   *        @arg LCD_FLAG_SOF: Start of Frame flag. This flag is set by hardware at
00552   *             the beginning of a new frame, at the same time as the display data is
00553   *             updated.
00554   *        @arg LCD_FLAG_UDR: Update Display Request flag.
00555   *        @arg LCD_FLAG_UDD: Update Display Done flag.
00556   *        @arg LCD_FLAG_RDY: Step_up converter Ready flag. It indicates the status
00557   *             of the step-up converter.
00558   *        @arg LCD_FLAG_FCRSF: LCD Frame Control Register Synchronization Flag.
00559   *             This flag is set by hardware each time the LCD_FCR register is updated
00560   *             in the LCDCLK domain.
00561   * @retval The new state of __FLAG__ (TRUE or FALSE).
00562   */
00563 #define __HAL_LCD_GET_FLAG(__HANDLE__, __FLAG__)    (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
00564
00565 /** @brief  Clear the specified LCD pending flag.
00566   * @param __HANDLE__ specifies the LCD Handle.
00567   * @param __FLAG__ specifies the flag to clear.
00568   *        This parameter can be any combination of the following values:
00569   *        @arg LCD_FLAG_SOF: Start of Frame Interrupt
00570   *        @arg LCD_FLAG_UDD: Update Display Done Interrupt
00571   * @retval None
00572   */
00573 #define __HAL_LCD_CLEAR_FLAG(__HANDLE__, __FLAG__)  WRITE_REG((__HANDLE__)->Instance->CLR, (__FLAG__))
00574
00575 /**
00576   * @}
00577   */
00578
00579 /* Exported functions ------------------------------------------------------- */
00580 /** @addtogroup LCD_Exported_Functions
00581   * @{
00582   */
00583
00584 /* Initialization/de-initialization methods  **********************************/
00585 /** @addtogroup LCD_Exported_Functions_Group1
00586   * @{
00587   */
00588 HAL_StatusTypeDef    HAL_LCD_DeInit(LCD_HandleTypeDef *hlcd);
00589 HAL_StatusTypeDef    HAL_LCD_Init(LCD_HandleTypeDef *hlcd);
00590 void                 HAL_LCD_MspInit(LCD_HandleTypeDef *hlcd);
00591 void                 HAL_LCD_MspDeInit(LCD_HandleTypeDef *hlcd);
00592 /**
00593   * @}
00594   */
00595
00596 /* IO operation methods *******************************************************/
00597 /** @addtogroup LCD_Exported_Functions_Group2
00598   * @{
00599   */
00600 HAL_StatusTypeDef    HAL_LCD_Write(LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterIndex, uint32_t RAMRegisterMask, uint32_t Data);
00601 HAL_StatusTypeDef    HAL_LCD_Clear(LCD_HandleTypeDef *hlcd);
00602 HAL_StatusTypeDef    HAL_LCD_UpdateDisplayRequest(LCD_HandleTypeDef *hlcd);
00603 /**
00604   * @}
00605   */
00606
00607 /* Peripheral State methods  **************************************************/
00608 /** @addtogroup LCD_Exported_Functions_Group3
00609   * @{
00610   */
00611 HAL_LCD_StateTypeDef HAL_LCD_GetState(LCD_HandleTypeDef *hlcd);
00612 uint32_t             HAL_LCD_GetError(LCD_HandleTypeDef *hlcd);
00613 /**
00614   * @}
00615   */
00616
00617 /**
00618   * @}
00619   */
00620
00621 /* Private types -------------------------------------------------------------*/
00622 /* Private variables ---------------------------------------------------------*/
00623 /* Private constants ---------------------------------------------------------*/
00624 /* Private macros ------------------------------------------------------------*/
00625 /** @defgroup LCD_Private_Macros LCD Private Macros
00626   * @{
00627   */
00628
00629 #define IS_LCD_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LCD_PRESCALER_1)     || \
00630                                          ((__PRESCALER__) == LCD_PRESCALER_2)     || \
00631                                          ((__PRESCALER__) == LCD_PRESCALER_4)     || \
00632                                          ((__PRESCALER__) == LCD_PRESCALER_8)     || \
00633                                          ((__PRESCALER__) == LCD_PRESCALER_16)    || \
00634                                          ((__PRESCALER__) == LCD_PRESCALER_32)    || \
00635                                          ((__PRESCALER__) == LCD_PRESCALER_64)    || \
00636                                          ((__PRESCALER__) == LCD_PRESCALER_128)   || \
00637                                          ((__PRESCALER__) == LCD_PRESCALER_256)   || \
00638                                          ((__PRESCALER__) == LCD_PRESCALER_512)   || \
00639                                          ((__PRESCALER__) == LCD_PRESCALER_1024)  || \
00640                                          ((__PRESCALER__) == LCD_PRESCALER_2048)  || \
00641                                          ((__PRESCALER__) == LCD_PRESCALER_4096)  || \
00642                                          ((__PRESCALER__) == LCD_PRESCALER_8192)  || \
00643                                          ((__PRESCALER__) == LCD_PRESCALER_16384) || \
00644                                          ((__PRESCALER__) == LCD_PRESCALER_32768))
00645
00646 #define IS_LCD_DIVIDER(__DIVIDER__) (((__DIVIDER__) == LCD_DIVIDER_16) || \
00647                                      ((__DIVIDER__) == LCD_DIVIDER_17) || \
00648                                      ((__DIVIDER__) == LCD_DIVIDER_18) || \
00649                                      ((__DIVIDER__) == LCD_DIVIDER_19) || \
00650                                      ((__DIVIDER__) == LCD_DIVIDER_20) || \
00651                                      ((__DIVIDER__) == LCD_DIVIDER_21) || \
00652                                      ((__DIVIDER__) == LCD_DIVIDER_22) || \
00653                                      ((__DIVIDER__) == LCD_DIVIDER_23) || \
00654                                      ((__DIVIDER__) == LCD_DIVIDER_24) || \
00655                                      ((__DIVIDER__) == LCD_DIVIDER_25) || \
00656                                      ((__DIVIDER__) == LCD_DIVIDER_26) || \
00657                                      ((__DIVIDER__) == LCD_DIVIDER_27) || \
00658                                      ((__DIVIDER__) == LCD_DIVIDER_28) || \
00659                                      ((__DIVIDER__) == LCD_DIVIDER_29) || \
00660                                      ((__DIVIDER__) == LCD_DIVIDER_30) || \
00661                                      ((__DIVIDER__) == LCD_DIVIDER_31))
00662
00663 #define IS_LCD_DUTY(__DUTY__) (((__DUTY__) == LCD_DUTY_STATIC)  || \
00664                                ((__DUTY__) == LCD_DUTY_1_2)     || \
00665                                ((__DUTY__) == LCD_DUTY_1_3)     || \
00666                                ((__DUTY__) == LCD_DUTY_1_4)     || \
00667                                ((__DUTY__) == LCD_DUTY_1_8))
00668
00669 #define IS_LCD_BIAS(__BIAS__) (((__BIAS__) == LCD_BIAS_1_4) || \
00670                                ((__BIAS__) == LCD_BIAS_1_2) || \
00671                                ((__BIAS__) == LCD_BIAS_1_3))
00672
00673 #define IS_LCD_VOLTAGE_SOURCE(SOURCE) (((SOURCE) == LCD_VOLTAGESOURCE_INTERNAL) || \
00674                                        ((SOURCE) == LCD_VOLTAGESOURCE_EXTERNAL))
00675
00676
00677 #define IS_LCD_PULSE_ON_DURATION(__DURATION__) (((__DURATION__) == LCD_PULSEONDURATION_0) || \
00678                                                 ((__DURATION__) == LCD_PULSEONDURATION_1) || \
00679                                                 ((__DURATION__) == LCD_PULSEONDURATION_2) || \
00680                                                 ((__DURATION__) == LCD_PULSEONDURATION_3) || \
00681                                                 ((__DURATION__) == LCD_PULSEONDURATION_4) || \
00682                                                 ((__DURATION__) == LCD_PULSEONDURATION_5) || \
00683                                                 ((__DURATION__) == LCD_PULSEONDURATION_6) || \
00684                                                 ((__DURATION__) == LCD_PULSEONDURATION_7))
00685
00686 #define IS_LCD_DEAD_TIME(__TIME__) (((__TIME__) == LCD_DEADTIME_0) || \
00687                                     ((__TIME__) == LCD_DEADTIME_1) || \
00688                                     ((__TIME__) == LCD_DEADTIME_2) || \
00689                                     ((__TIME__) == LCD_DEADTIME_3) || \
00690                                     ((__TIME__) == LCD_DEADTIME_4) || \
00691                                     ((__TIME__) == LCD_DEADTIME_5) || \
00692                                     ((__TIME__) == LCD_DEADTIME_6) || \
00693                                     ((__TIME__) == LCD_DEADTIME_7))
00694
00695 #define IS_LCD_BLINK_MODE(__MODE__) (((__MODE__) == LCD_BLINKMODE_OFF)            || \
00696                                      ((__MODE__) == LCD_BLINKMODE_SEG0_COM0)      || \
00697                                      ((__MODE__) == LCD_BLINKMODE_SEG0_ALLCOM)    || \
00698                                      ((__MODE__) == LCD_BLINKMODE_ALLSEG_ALLCOM))
00699
00700 #define IS_LCD_BLINK_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV8)   || \
00701                                                ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV16)  || \
00702                                                ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV32)  || \
00703                                                ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV64)  || \
00704                                                ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV128) || \
00705                                                ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV256) || \
00706                                                ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV512) || \
00707                                                ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV1024))
00708
00709 #define IS_LCD_CONTRAST(__CONTRAST__) (((__CONTRAST__) == LCD_CONTRASTLEVEL_0) || \
00710                                        ((__CONTRAST__) == LCD_CONTRASTLEVEL_1) || \
00711                                        ((__CONTRAST__) == LCD_CONTRASTLEVEL_2) || \
00712                                        ((__CONTRAST__) == LCD_CONTRASTLEVEL_3) || \
00713                                        ((__CONTRAST__) == LCD_CONTRASTLEVEL_4) || \
00714                                        ((__CONTRAST__) == LCD_CONTRASTLEVEL_5) || \
00715                                        ((__CONTRAST__) == LCD_CONTRASTLEVEL_6) || \
00716                                        ((__CONTRAST__) == LCD_CONTRASTLEVEL_7))
00717
00718 #define IS_LCD_RAM_REGISTER(__REGISTER__) (((__REGISTER__) == LCD_RAM_REGISTER0)  || \
00719                                            ((__REGISTER__) == LCD_RAM_REGISTER1)  || \
00720                                            ((__REGISTER__) == LCD_RAM_REGISTER2)  || \
00721                                            ((__REGISTER__) == LCD_RAM_REGISTER3)  || \
00722                                            ((__REGISTER__) == LCD_RAM_REGISTER4)  || \
00723                                            ((__REGISTER__) == LCD_RAM_REGISTER5)  || \
00724                                            ((__REGISTER__) == LCD_RAM_REGISTER6)  || \
00725                                            ((__REGISTER__) == LCD_RAM_REGISTER7)  || \
00726                                            ((__REGISTER__) == LCD_RAM_REGISTER8)  || \
00727                                            ((__REGISTER__) == LCD_RAM_REGISTER9)  || \
00728                                            ((__REGISTER__) == LCD_RAM_REGISTER10) || \
00729                                            ((__REGISTER__) == LCD_RAM_REGISTER11) || \
00730                                            ((__REGISTER__) == LCD_RAM_REGISTER12) || \
00731                                            ((__REGISTER__) == LCD_RAM_REGISTER13) || \
00732                                            ((__REGISTER__) == LCD_RAM_REGISTER14) || \
00733                                            ((__REGISTER__) == LCD_RAM_REGISTER15))
00734
00735 #define IS_LCD_HIGH_DRIVE(__VALUE__) (((__VALUE__) == LCD_HIGHDRIVE_DISABLE) || \
00736                                       ((__VALUE__) == LCD_HIGHDRIVE_ENABLE))
00737
00738 #define IS_LCD_MUX_SEGMENT(__VALUE__) (((__VALUE__) == LCD_MUXSEGMENT_ENABLE) || \
00739                                        ((__VALUE__) == LCD_MUXSEGMENT_DISABLE))
00740
00741 /**
00742   * @}
00743   */
00744
00745 /* Private functions ---------------------------------------------------------*/
00746 /** @addtogroup LCD_Private_Functions
00747   * @{
00748   */
00749
00750 HAL_StatusTypeDef     LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd);
00751
00752 /**
00753   * @}
00754   */
00755
00756 /**
00757   * @}
00758   */
00759
00760 #endif /* LCD */
00761
00762 /**
00763   * @}
00764   */
00765
00766 #ifdef __cplusplus
00767 }
00768 #endif
00769
00770 #endif /* STM32WBxx_HAL_LCD_H */
00771
00772 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_lptim.c Source File

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stm32wbxx_hal_lptim.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_lptim.c
00004   * @author  MCD Application Team
00005   * @brief   LPTIM HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Low Power Timer (LPTIM) peripheral:
00008   *           + Initialization and de-initialization functions.
00009   *           + Start/Stop operation functions in polling mode.
00010   *           + Start/Stop operation functions in interrupt mode.
00011   *           + Reading operation functions.
00012   *           + Peripheral State functions.
00013   *
00014   @verbatim
00015   ==============================================================================
00016                      ##### How to use this driver #####
00017   ==============================================================================
00018     [..]
00019       The LPTIM HAL driver can be used as follows:
00020
00021       (#)Initialize the LPTIM low level resources by implementing the
00022         HAL_LPTIM_MspInit():
00023          (++) Enable the LPTIM interface clock using __HAL_RCC_LPTIMx_CLK_ENABLE().
00024          (++) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):
00025              (+++) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().
00026              (+++) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().
00027              (+++) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().
00028
00029       (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function
00030          configures mainly:
00031          (++) The instance: LPTIM1 or LPTIM2.
00032          (++) Clock: the counter clock.
00033              (+++) Source   : it can be either the ULPTIM input (IN1) or one of
00034                               the internal clock; (APB, LSE, LSI or MSI).
00035              (+++) Prescaler: select the clock divider.
00036          (++)  UltraLowPowerClock : To be used only if the ULPTIM is selected
00037                as counter clock source.
00038              (+++) Polarity:   polarity of the active edge for the counter unit
00039                                if the ULPTIM input is selected.
00040              (+++) SampleTime: clock sampling time to configure the clock glitch
00041                                filter.
00042          (++) Trigger: How the counter start.
00043              (+++) Source: trigger can be software or one of the hardware triggers.
00044              (+++) ActiveEdge : only for hardware trigger.
00045              (+++) SampleTime : trigger sampling time to configure the trigger
00046                                 glitch filter.
00047          (++) OutputPolarity : 2 opposite polarities are possible.
00048          (++) UpdateMode: specifies whether the update of the autoreload and
00049               the compare values is done immediately or after the end of current
00050               period.
00051          (++) Input1Source: Source selected for input1 (GPIO or comparator output).
00052          (++) Input2Source: Source selected for input2 (GPIO or comparator output).
00053               Input2 is used only for encoder feature so is used only for LPTIM1 instance.
00054
00055       (#)Six modes are available:
00056
00057          (++) PWM Mode: To generate a PWM signal with specified period and pulse,
00058          call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption
00059          mode.
00060
00061          (++) One Pulse Mode: To generate pulse with specified width in response
00062          to a stimulus, call HAL_LPTIM_OnePulse_Start() or
00063          HAL_LPTIM_OnePulse_Start_IT() for interruption mode.
00064
00065          (++) Set once Mode: In this mode, the output changes the level (from
00066          low level to high level if the output polarity is configured high, else
00067          the opposite) when a compare match occurs. To start this mode, call
00068          HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for
00069          interruption mode.
00070
00071          (++) Encoder Mode: To use the encoder interface call
00072          HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for
00073          interruption mode. Only available for LPTIM1 instance.
00074
00075          (++) Time out Mode: an active edge on one selected trigger input rests
00076          the counter. The first trigger event will start the timer, any
00077          successive trigger event will reset the counter and the timer will
00078          restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or
00079          HAL_LPTIM_TimeOut_Start_IT() for interruption mode.
00080
00081          (++) Counter Mode: counter can be used to count external events on
00082          the LPTIM Input1 or it can be used to count internal clock cycles.
00083          To start this mode, call HAL_LPTIM_Counter_Start() or
00084          HAL_LPTIM_Counter_Start_IT() for interruption mode.
00085
00086
00087       (#) User can stop any process by calling the corresponding API:
00088           HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is
00089           already started in interruption mode.
00090
00091       (#) De-initialize the LPTIM peripheral using HAL_LPTIM_DeInit().
00092
00093     *** Callback registration ***
00094   =============================================
00095   [..]
00096   The compilation define  USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1
00097   allows the user to configure dynamically the driver callbacks.
00098   [..]
00099   Use Function @ref HAL_LPTIM_RegisterCallback() to register a callback.
00100   @ref HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle,
00101   the Callback ID and a pointer to the user callback function.
00102   [..]
00103   Use function @ref HAL_LPTIM_UnRegisterCallback() to reset a callback to the
00104   default weak function.
00105   @ref HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
00106   and the Callback ID.
00107   [..]
00108   These functions allow to register/unregister following callbacks:
00109
00110     (+) MspInitCallback         : LPTIM Base Msp Init Callback.
00111     (+) MspDeInitCallback       : LPTIM Base Msp DeInit Callback.
00112     (+) CompareMatchCallback    : Compare match Callback.
00113     (+) AutoReloadMatchCallback : Auto-reload match Callback.
00114     (+) TriggerCallback         : External trigger event detection Callback.
00115     (+) CompareWriteCallback    : Compare register write complete Callback.
00116     (+) AutoReloadWriteCallback : Auto-reload register write complete Callback.
00117     (+) DirectionUpCallback     : Up-counting direction change Callback.
00118     (+) DirectionDownCallback   : Down-counting direction change Callback.
00119
00120   [..]
00121   By default, after the Init and when the state is HAL_LPTIM_STATE_RESET
00122   all interrupt callbacks are set to the corresponding weak functions:
00123   examples @ref HAL_LPTIM_TriggerCallback(), @ref HAL_LPTIM_CompareMatchCallback().
00124
00125   [..]
00126   Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
00127   functionalities in the Init/DeInit only when these callbacks are null
00128   (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init/DeInit
00129   keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
00130
00131   [..]
00132   Callbacks can be registered/unregistered in HAL_LPTIM_STATE_READY state only.
00133   Exception done MspInit/MspDeInit that can be registered/unregistered
00134   in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state,
00135   thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00136   In that case first register the MspInit/MspDeInit user callbacks
00137   using @ref HAL_LPTIM_RegisterCallback() before calling DeInit or Init function.
00138
00139   [..]
00140   When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or
00141   not defined, the callback registration feature is not available and all callbacks
00142   are set to the corresponding weak functions.
00143
00144   @endverbatim
00145   ******************************************************************************
00146     * @attention
00147   *
00148   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00149   * All rights reserved.</center></h2>
00150   *
00151   * This software component is licensed by ST under BSD 3-Clause license,
00152   * the "License"; You may not use this file except in compliance with the
00153   * License. You may obtain a copy of the License at:
00154   *                        opensource.org/licenses/BSD-3-Clause
00155   *
00156   ******************************************************************************
00157   */
00158
00159 /* Includes ------------------------------------------------------------------*/
00160 #include "stm32wbxx_hal.h"
00161
00162 /** @addtogroup STM32WBxx_HAL_Driver
00163   * @{
00164   */
00165
00166 /** @defgroup LPTIM LPTIM
00167   * @brief LPTIM HAL module driver.
00168   * @{
00169   */
00170
00171 #ifdef HAL_LPTIM_MODULE_ENABLED
00172
00173 #if defined (LPTIM1) || defined (LPTIM2)
00174
00175 /* Private typedef -----------------------------------------------------------*/
00176 /* Private define ------------------------------------------------------------*/
00177 /* Private macro -------------------------------------------------------------*/
00178 #define TIMEOUT                                     1000UL /* Timeout is 1s */
00179 /* Private variables ---------------------------------------------------------*/
00180 /* Private function prototypes -----------------------------------------------*/
00181 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
00182 static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim);
00183 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
00184 static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag);
00185
00186 /* Exported functions --------------------------------------------------------*/
00187
00188 /** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
00189   * @{
00190   */
00191
00192 /** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions
00193  *  @brief    Initialization and Configuration functions.
00194  *
00195 @verbatim
00196   ==============================================================================
00197               ##### Initialization and de-initialization functions #####
00198   ==============================================================================
00199     [..]  This section provides functions allowing to:
00200       (+) Initialize the LPTIM according to the specified parameters in the
00201           LPTIM_InitTypeDef and initialize the associated handle.
00202       (+) DeInitialize the LPTIM peripheral.
00203       (+) Initialize the LPTIM MSP.
00204       (+) DeInitialize the LPTIM MSP.
00205
00206 @endverbatim
00207   * @{
00208   */
00209
00210 /**
00211   * @brief  Initialize the LPTIM according to the specified parameters in the
00212   *         LPTIM_InitTypeDef and initialize the associated handle.
00213   * @param  hlptim LPTIM handle
00214   * @retval HAL status
00215   */
00216 HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
00217 {
00218   uint32_t tmpcfgr;
00219
00220   /* Check the LPTIM handle allocation */
00221   if (hlptim == NULL)
00222   {
00223     return HAL_ERROR;
00224   }
00225
00226   /* Check the parameters */
00227   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00228
00229   assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
00230   assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
00231   if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM)
00232   {
00233     assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
00234     assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
00235   }
00236   assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));
00237   if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
00238   {
00239     assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
00240     assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
00241   }
00242   assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity));
00243   assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
00244   assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource));
00245
00246   if (hlptim->State == HAL_LPTIM_STATE_RESET)
00247   {
00248     /* Allocate lock resource and initialize it */
00249     hlptim->Lock = HAL_UNLOCKED;
00250
00251 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
00252     /* Reset interrupt callbacks to legacy weak callbacks */
00253     LPTIM_ResetCallback(hlptim);
00254
00255     if (hlptim->MspInitCallback == NULL)
00256     {
00257       hlptim->MspInitCallback = HAL_LPTIM_MspInit;
00258     }
00259
00260     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00261     hlptim->MspInitCallback(hlptim);
00262 #else
00263     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00264     HAL_LPTIM_MspInit(hlptim);
00265 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
00266   }
00267
00268   /* Change the LPTIM state */
00269   hlptim->State = HAL_LPTIM_STATE_BUSY;
00270
00271   /* Get the LPTIMx CFGR value */
00272   tmpcfgr = hlptim->Instance->CFGR;
00273
00274   if (((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) || ((hlptim->Init.CounterSource) == LPTIM_COUNTERSOURCE_EXTERNAL))
00275   {
00276     tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
00277   }
00278   if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
00279   {
00280     tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
00281   }
00282
00283   /* Clear CKSEL, CKPOL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
00284   tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_CKPOL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
00285                           LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE));
00286
00287   /* Set initialization parameters */
00288   tmpcfgr |= (hlptim->Init.Clock.Source    |
00289               hlptim->Init.Clock.Prescaler |
00290               hlptim->Init.OutputPolarity  |
00291               hlptim->Init.UpdateMode      |
00292               hlptim->Init.CounterSource);
00293
00294   if (((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) || ((hlptim->Init.CounterSource) == LPTIM_COUNTERSOURCE_EXTERNAL))
00295   {
00296     tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
00297                 hlptim->Init.UltraLowPowerClock.SampleTime);
00298   }
00299
00300   if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
00301   {
00302     /* Enable External trigger and set the trigger source */
00303     tmpcfgr |= (hlptim->Init.Trigger.Source     |
00304                 hlptim->Init.Trigger.ActiveEdge |
00305                 hlptim->Init.Trigger.SampleTime);
00306   }
00307
00308   /* Write to LPTIMx CFGR */
00309   hlptim->Instance->CFGR = tmpcfgr;
00310
00311   /* Configure LPTIM input sources */
00312   if (hlptim->Instance == LPTIM1)
00313   {
00314     /* Check LPTIM Input1 and Input2 sources */
00315     assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source));
00316     assert_param(IS_LPTIM_INPUT2_SOURCE(hlptim->Instance, hlptim->Init.Input2Source));
00317
00318     /* Configure LPTIM Input1 and Input2 sources */
00319     hlptim->Instance->OR = (hlptim->Init.Input1Source | hlptim->Init.Input2Source);
00320   }
00321   else
00322   {
00323     /* Check LPTIM2 Input1 source */
00324     assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source));
00325
00326     /* Configure LPTIM2 Input1 source */
00327     hlptim->Instance->OR = hlptim->Init.Input1Source;
00328   }
00329
00330   /* Change the LPTIM state */
00331   hlptim->State = HAL_LPTIM_STATE_READY;
00332
00333   /* Return function status */
00334   return HAL_OK;
00335 }
00336
00337 /**
00338   * @brief  DeInitialize the LPTIM peripheral.
00339   * @param  hlptim LPTIM handle
00340   * @retval HAL status
00341   */
00342 HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim)
00343 {
00344   /* Check the LPTIM handle allocation */
00345   if (hlptim == NULL)
00346   {
00347     return HAL_ERROR;
00348   }
00349
00350   /* Change the LPTIM state */
00351   hlptim->State = HAL_LPTIM_STATE_BUSY;
00352
00353   /* Disable the LPTIM Peripheral Clock */
00354   __HAL_LPTIM_DISABLE(hlptim);
00355
00356   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
00357   {
00358     return HAL_TIMEOUT;
00359   }
00360
00361 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
00362   if (hlptim->MspDeInitCallback == NULL)
00363   {
00364     hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
00365   }
00366
00367   /* DeInit the low level hardware: CLOCK, NVIC.*/
00368   hlptim->MspDeInitCallback(hlptim);
00369 #else
00370   /* DeInit the low level hardware: CLOCK, NVIC.*/
00371   HAL_LPTIM_MspDeInit(hlptim);
00372 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
00373
00374   /* Change the LPTIM state */
00375   hlptim->State = HAL_LPTIM_STATE_RESET;
00376
00377   /* Release Lock */
00378   __HAL_UNLOCK(hlptim);
00379
00380   /* Return function status */
00381   return HAL_OK;
00382 }
00383
00384 /**
00385   * @brief  Initialize the LPTIM MSP.
00386   * @param  hlptim LPTIM handle
00387   * @retval None
00388   */
00389 __weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim)
00390 {
00391   /* Prevent unused argument(s) compilation warning */
00392   UNUSED(hlptim);
00393
00394   /* NOTE : This function should not be modified, when the callback is needed,
00395             the HAL_LPTIM_MspInit could be implemented in the user file
00396    */
00397 }
00398
00399 /**
00400   * @brief  DeInitialize LPTIM MSP.
00401   * @param  hlptim LPTIM handle
00402   * @retval None
00403   */
00404 __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)
00405 {
00406   /* Prevent unused argument(s) compilation warning */
00407   UNUSED(hlptim);
00408
00409   /* NOTE : This function should not be modified, when the callback is needed,
00410             the HAL_LPTIM_MspDeInit could be implemented in the user file
00411    */
00412 }
00413
00414 /**
00415   * @}
00416   */
00417
00418 /** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions
00419  *  @brief   Start-Stop operation functions.
00420  *
00421 @verbatim
00422   ==============================================================================
00423                 ##### LPTIM Start Stop operation functions #####
00424   ==============================================================================
00425     [..]  This section provides functions allowing to:
00426       (+) Start the PWM mode.
00427       (+) Stop the PWM mode.
00428       (+) Start the One pulse mode.
00429       (+) Stop the One pulse mode.
00430       (+) Start the Set once mode.
00431       (+) Stop the Set once mode.
00432       (+) Start the Encoder mode.
00433       (+) Stop the Encoder mode.
00434       (+) Start the Timeout mode.
00435       (+) Stop the Timeout mode.
00436       (+) Start the Counter mode.
00437       (+) Stop the Counter mode.
00438
00439
00440 @endverbatim
00441   * @{
00442   */
00443
00444 /**
00445   * @brief  Start the LPTIM PWM generation.
00446   * @param  hlptim LPTIM handle
00447   * @param  Period Specifies the Autoreload value.
00448   *         This parameter must be a value between 0x0000 and 0xFFFF.
00449   * @param  Pulse Specifies the compare value.
00450   *         This parameter must be a value between 0x0000 and 0xFFFF.
00451   * @retval HAL status
00452   */
00453 HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00454 {
00455   /* Check the parameters */
00456   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00457   assert_param(IS_LPTIM_PERIOD(Period));
00458   assert_param(IS_LPTIM_PULSE(Pulse));
00459
00460   /* Set the LPTIM state */
00461   hlptim->State = HAL_LPTIM_STATE_BUSY;
00462
00463   /* Reset WAVE bit to set PWM mode */
00464   hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
00465
00466   /* Enable the Peripheral */
00467   __HAL_LPTIM_ENABLE(hlptim);
00468
00469   /* Clear flag */
00470   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
00471
00472   /* Load the period value in the autoreload register */
00473   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00474
00475   /* Wait for the completion of the write operation to the LPTIM_ARR register */
00476   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
00477   {
00478     return HAL_TIMEOUT;
00479   }
00480
00481   /* Clear flag */
00482   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
00483
00484   /* Load the pulse value in the compare register */
00485   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00486
00487   /* Wait for the completion of the write operation to the LPTIM_CMP register */
00488   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
00489   {
00490     return HAL_TIMEOUT;
00491   }
00492
00493   /* Start timer in continuous mode */
00494   __HAL_LPTIM_START_CONTINUOUS(hlptim);
00495
00496   /* Change the TIM state*/
00497   hlptim->State = HAL_LPTIM_STATE_READY;
00498
00499   /* Return function status */
00500   return HAL_OK;
00501 }
00502
00503 /**
00504   * @brief  Stop the LPTIM PWM generation.
00505   * @param  hlptim LPTIM handle
00506   * @retval HAL status
00507   */
00508 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim)
00509 {
00510   /* Check the parameters */
00511   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00512
00513   /* Set the LPTIM state */
00514   hlptim->State = HAL_LPTIM_STATE_BUSY;
00515
00516   /* Disable the Peripheral */
00517   __HAL_LPTIM_DISABLE(hlptim);
00518
00519   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
00520   {
00521     return HAL_TIMEOUT;
00522   }
00523
00524   /* Change the TIM state*/
00525   hlptim->State = HAL_LPTIM_STATE_READY;
00526
00527   /* Return function status */
00528   return HAL_OK;
00529 }
00530
00531 /**
00532   * @brief  Start the LPTIM PWM generation in interrupt mode.
00533   * @param  hlptim LPTIM handle
00534   * @param  Period Specifies the Autoreload value.
00535   *         This parameter must be a value between 0x0000 and 0xFFFF
00536   * @param  Pulse Specifies the compare value.
00537   *         This parameter must be a value between 0x0000 and 0xFFFF
00538   * @retval HAL status
00539   */
00540 HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00541 {
00542   /* Check the parameters */
00543   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00544   assert_param(IS_LPTIM_PERIOD(Period));
00545   assert_param(IS_LPTIM_PULSE(Pulse));
00546
00547   /* Set the LPTIM state */
00548   hlptim->State = HAL_LPTIM_STATE_BUSY;
00549
00550   /* Reset WAVE bit to set PWM mode */
00551   hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
00552
00553   /* Enable the Peripheral */
00554   __HAL_LPTIM_ENABLE(hlptim);
00555
00556   /* Clear flag */
00557   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
00558
00559   /* Load the period value in the autoreload register */
00560   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00561
00562   /* Wait for the completion of the write operation to the LPTIM_ARR register */
00563   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
00564   {
00565     return HAL_TIMEOUT;
00566   }
00567
00568   /* Clear flag */
00569   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
00570
00571   /* Load the pulse value in the compare register */
00572   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00573
00574   /* Wait for the completion of the write operation to the LPTIM_CMP register */
00575   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
00576   {
00577     return HAL_TIMEOUT;
00578   }
00579
00580   /* Disable the Peripheral */
00581   __HAL_LPTIM_DISABLE(hlptim);
00582
00583   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
00584   {
00585     return HAL_TIMEOUT;
00586   }
00587
00588   /* Enable Autoreload write complete interrupt */
00589   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
00590
00591   /* Enable Compare write complete interrupt */
00592   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
00593
00594   /* Enable Autoreload match interrupt */
00595   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
00596
00597   /* Enable Compare match interrupt */
00598   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
00599
00600   /* If external trigger source is used, then enable external trigger interrupt */
00601   if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
00602   {
00603     /* Enable external trigger interrupt */
00604     __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00605   }
00606
00607   /* Enable the Peripheral */
00608   __HAL_LPTIM_ENABLE(hlptim);
00609
00610   /* Start timer in continuous mode */
00611   __HAL_LPTIM_START_CONTINUOUS(hlptim);
00612
00613   /* Change the TIM state*/
00614   hlptim->State = HAL_LPTIM_STATE_READY;
00615
00616   /* Return function status */
00617   return HAL_OK;
00618 }
00619
00620 /**
00621   * @brief  Stop the LPTIM PWM generation in interrupt mode.
00622   * @param  hlptim LPTIM handle
00623   * @retval HAL status
00624   */
00625 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim)
00626 {
00627   /* Check the parameters */
00628   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00629
00630   /* Set the LPTIM state */
00631   hlptim->State = HAL_LPTIM_STATE_BUSY;
00632
00633   /* Disable the Peripheral */
00634   __HAL_LPTIM_DISABLE(hlptim);
00635
00636   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
00637   {
00638     return HAL_TIMEOUT;
00639   }
00640
00641   /* Disable Autoreload write complete interrupt */
00642   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
00643
00644   /* Disable Compare write complete interrupt */
00645   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
00646
00647   /* Disable Autoreload match interrupt */
00648   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
00649
00650   /* Disable Compare match interrupt */
00651   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
00652
00653   /* If external trigger source is used, then disable external trigger interrupt */
00654   if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
00655   {
00656     /* Disable external trigger interrupt */
00657     __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00658   }
00659
00660   /* Change the TIM state*/
00661   hlptim->State = HAL_LPTIM_STATE_READY;
00662
00663   /* Return function status */
00664   return HAL_OK;
00665 }
00666
00667 /**
00668   * @brief  Start the LPTIM One pulse generation.
00669   * @param  hlptim LPTIM handle
00670   * @param  Period Specifies the Autoreload value.
00671   *         This parameter must be a value between 0x0000 and 0xFFFF.
00672   * @param  Pulse Specifies the compare value.
00673   *         This parameter must be a value between 0x0000 and 0xFFFF.
00674   * @retval HAL status
00675   */
00676 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00677 {
00678   /* Check the parameters */
00679   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00680   assert_param(IS_LPTIM_PERIOD(Period));
00681   assert_param(IS_LPTIM_PULSE(Pulse));
00682
00683   /* Set the LPTIM state */
00684   hlptim->State = HAL_LPTIM_STATE_BUSY;
00685
00686   /* Reset WAVE bit to set one pulse mode */
00687   hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
00688
00689   /* Enable the Peripheral */
00690   __HAL_LPTIM_ENABLE(hlptim);
00691
00692   /* Clear flag */
00693   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
00694
00695   /* Load the period value in the autoreload register */
00696   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00697
00698   /* Wait for the completion of the write operation to the LPTIM_ARR register */
00699   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
00700   {
00701     return HAL_TIMEOUT;
00702   }
00703
00704   /* Clear flag */
00705   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
00706
00707   /* Load the pulse value in the compare register */
00708   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00709
00710   /* Wait for the completion of the write operation to the LPTIM_CMP register */
00711   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
00712   {
00713     return HAL_TIMEOUT;
00714   }
00715
00716   /* Start timer in single (one shot) mode */
00717   __HAL_LPTIM_START_SINGLE(hlptim);
00718
00719   /* Change the TIM state*/
00720   hlptim->State = HAL_LPTIM_STATE_READY;
00721
00722   /* Return function status */
00723   return HAL_OK;
00724 }
00725
00726 /**
00727   * @brief  Stop the LPTIM One pulse generation.
00728   * @param  hlptim LPTIM handle
00729   * @retval HAL status
00730   */
00731 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim)
00732 {
00733   /* Check the parameters */
00734   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00735
00736   /* Set the LPTIM state */
00737   hlptim->State = HAL_LPTIM_STATE_BUSY;
00738
00739   /* Disable the Peripheral */
00740   __HAL_LPTIM_DISABLE(hlptim);
00741
00742   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
00743   {
00744     return HAL_TIMEOUT;
00745   }
00746
00747   /* Change the TIM state*/
00748   hlptim->State = HAL_LPTIM_STATE_READY;
00749
00750   /* Return function status */
00751   return HAL_OK;
00752 }
00753
00754 /**
00755   * @brief  Start the LPTIM One pulse generation in interrupt mode.
00756   * @param  hlptim LPTIM handle
00757   * @param  Period Specifies the Autoreload value.
00758   *         This parameter must be a value between 0x0000 and 0xFFFF.
00759   * @param  Pulse Specifies the compare value.
00760   *         This parameter must be a value between 0x0000 and 0xFFFF.
00761   * @retval HAL status
00762   */
00763 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00764 {
00765   /* Check the parameters */
00766   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00767   assert_param(IS_LPTIM_PERIOD(Period));
00768   assert_param(IS_LPTIM_PULSE(Pulse));
00769
00770   /* Set the LPTIM state */
00771   hlptim->State = HAL_LPTIM_STATE_BUSY;
00772
00773   /* Reset WAVE bit to set one pulse mode */
00774   hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
00775
00776   /* Enable the Peripheral */
00777   __HAL_LPTIM_ENABLE(hlptim);
00778
00779   /* Clear flag */
00780   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
00781
00782   /* Load the period value in the autoreload register */
00783   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00784
00785   /* Wait for the completion of the write operation to the LPTIM_ARR register */
00786   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
00787   {
00788     return HAL_TIMEOUT;
00789   }
00790
00791   /* Clear flag */
00792   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
00793
00794   /* Load the pulse value in the compare register */
00795   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00796
00797   /* Wait for the completion of the write operation to the LPTIM_CMP register */
00798   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
00799   {
00800     return HAL_TIMEOUT;
00801   }
00802
00803   /* Disable the Peripheral */
00804   __HAL_LPTIM_DISABLE(hlptim);
00805
00806   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
00807   {
00808     return HAL_TIMEOUT;
00809   }
00810
00811   /* Enable Autoreload write complete interrupt */
00812   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
00813
00814   /* Enable Compare write complete interrupt */
00815   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
00816
00817   /* Enable Autoreload match interrupt */
00818   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
00819
00820   /* Enable Compare match interrupt */
00821   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
00822
00823   /* If external trigger source is used, then enable external trigger interrupt */
00824   if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
00825   {
00826     /* Enable external trigger interrupt */
00827     __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00828   }
00829
00830   /* Enable the Peripheral */
00831   __HAL_LPTIM_ENABLE(hlptim);
00832
00833   /* Start timer in single (one shot) mode */
00834   __HAL_LPTIM_START_SINGLE(hlptim);
00835
00836   /* Change the TIM state*/
00837   hlptim->State = HAL_LPTIM_STATE_READY;
00838
00839   /* Return function status */
00840   return HAL_OK;
00841 }
00842
00843 /**
00844   * @brief  Stop the LPTIM One pulse generation in interrupt mode.
00845   * @param  hlptim LPTIM handle
00846   * @retval HAL status
00847   */
00848 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim)
00849 {
00850   /* Check the parameters */
00851   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00852
00853   /* Set the LPTIM state */
00854   hlptim->State = HAL_LPTIM_STATE_BUSY;
00855
00856   /* Disable the Peripheral */
00857   __HAL_LPTIM_DISABLE(hlptim);
00858
00859   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
00860   {
00861     return HAL_TIMEOUT;
00862   }
00863
00864   /* Disable Autoreload write complete interrupt */
00865   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
00866
00867   /* Disable Compare write complete interrupt */
00868   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
00869
00870   /* Disable Autoreload match interrupt */
00871   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
00872
00873   /* Disable Compare match interrupt */
00874   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
00875
00876   /* If external trigger source is used, then disable external trigger interrupt */
00877   if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
00878   {
00879     /* Disable external trigger interrupt */
00880     __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
00881   }
00882
00883   /* Change the TIM state*/
00884   hlptim->State = HAL_LPTIM_STATE_READY;
00885
00886   /* Return function status */
00887   return HAL_OK;
00888 }
00889
00890 /**
00891   * @brief  Start the LPTIM in Set once mode.
00892   * @param  hlptim LPTIM handle
00893   * @param  Period Specifies the Autoreload value.
00894   *         This parameter must be a value between 0x0000 and 0xFFFF.
00895   * @param  Pulse Specifies the compare value.
00896   *         This parameter must be a value between 0x0000 and 0xFFFF.
00897   * @retval HAL status
00898   */
00899 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00900 {
00901   /* Check the parameters */
00902   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00903   assert_param(IS_LPTIM_PERIOD(Period));
00904   assert_param(IS_LPTIM_PULSE(Pulse));
00905
00906   /* Set the LPTIM state */
00907   hlptim->State = HAL_LPTIM_STATE_BUSY;
00908
00909   /* Set WAVE bit to enable the set once mode */
00910   hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
00911
00912   /* Enable the Peripheral */
00913   __HAL_LPTIM_ENABLE(hlptim);
00914
00915   /* Clear flag */
00916   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
00917
00918   /* Load the period value in the autoreload register */
00919   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
00920
00921   /* Wait for the completion of the write operation to the LPTIM_ARR register */
00922   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
00923   {
00924     return HAL_TIMEOUT;
00925   }
00926
00927   /* Clear flag */
00928   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
00929
00930   /* Load the pulse value in the compare register */
00931   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
00932
00933   /* Wait for the completion of the write operation to the LPTIM_CMP register */
00934   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
00935   {
00936     return HAL_TIMEOUT;
00937   }
00938
00939   /* Start timer in single (one shot) mode */
00940   __HAL_LPTIM_START_SINGLE(hlptim);
00941
00942   /* Change the TIM state*/
00943   hlptim->State = HAL_LPTIM_STATE_READY;
00944
00945   /* Return function status */
00946   return HAL_OK;
00947 }
00948
00949 /**
00950   * @brief  Stop the LPTIM Set once mode.
00951   * @param  hlptim LPTIM handle
00952   * @retval HAL status
00953   */
00954 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim)
00955 {
00956   /* Check the parameters */
00957   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00958
00959   /* Set the LPTIM state */
00960   hlptim->State = HAL_LPTIM_STATE_BUSY;
00961
00962   /* Disable the Peripheral */
00963   __HAL_LPTIM_DISABLE(hlptim);
00964
00965   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
00966   {
00967     return HAL_TIMEOUT;
00968   }
00969
00970   /* Change the TIM state*/
00971   hlptim->State = HAL_LPTIM_STATE_READY;
00972
00973   /* Return function status */
00974   return HAL_OK;
00975 }
00976
00977 /**
00978   * @brief  Start the LPTIM Set once mode in interrupt mode.
00979   * @param  hlptim LPTIM handle
00980   * @param  Period Specifies the Autoreload value.
00981   *         This parameter must be a value between 0x0000 and 0xFFFF.
00982   * @param  Pulse Specifies the compare value.
00983   *         This parameter must be a value between 0x0000 and 0xFFFF.
00984   * @retval HAL status
00985   */
00986 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
00987 {
00988   /* Check the parameters */
00989   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
00990   assert_param(IS_LPTIM_PERIOD(Period));
00991   assert_param(IS_LPTIM_PULSE(Pulse));
00992
00993   /* Set the LPTIM state */
00994   hlptim->State = HAL_LPTIM_STATE_BUSY;
00995
00996   /* Set WAVE bit to enable the set once mode */
00997   hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
00998
00999   /* Enable the Peripheral */
01000   __HAL_LPTIM_ENABLE(hlptim);
01001
01002   /* Clear flag */
01003   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
01004
01005   /* Load the period value in the autoreload register */
01006   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01007
01008   /* Wait for the completion of the write operation to the LPTIM_ARR register */
01009   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
01010   {
01011     return HAL_TIMEOUT;
01012   }
01013
01014   /* Clear flag */
01015   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
01016
01017   /* Load the pulse value in the compare register */
01018   __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
01019
01020   /* Wait for the completion of the write operation to the LPTIM_CMP register */
01021   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
01022   {
01023     return HAL_TIMEOUT;
01024   }
01025
01026   /* Disable the Peripheral */
01027   __HAL_LPTIM_DISABLE(hlptim);
01028
01029   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01030   {
01031     return HAL_TIMEOUT;
01032   }
01033
01034   /* Enable Autoreload write complete interrupt */
01035   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
01036
01037   /* Enable Compare write complete interrupt */
01038   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
01039
01040   /* Enable Autoreload match interrupt */
01041   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
01042
01043   /* Enable Compare match interrupt */
01044   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
01045
01046   /* If external trigger source is used, then enable external trigger interrupt */
01047   if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
01048   {
01049     /* Enable external trigger interrupt */
01050     __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
01051   }
01052
01053   /* Enable the Peripheral */
01054   __HAL_LPTIM_ENABLE(hlptim);
01055
01056   /* Start timer in single (one shot) mode */
01057   __HAL_LPTIM_START_SINGLE(hlptim);
01058
01059   /* Change the TIM state*/
01060   hlptim->State = HAL_LPTIM_STATE_READY;
01061
01062   /* Return function status */
01063   return HAL_OK;
01064 }
01065
01066 /**
01067   * @brief  Stop the LPTIM Set once mode in interrupt mode.
01068   * @param  hlptim LPTIM handle
01069   * @retval HAL status
01070   */
01071 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim)
01072 {
01073   /* Check the parameters */
01074   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01075
01076   /* Set the LPTIM state */
01077   hlptim->State = HAL_LPTIM_STATE_BUSY;
01078
01079   /* Disable the Peripheral */
01080   __HAL_LPTIM_DISABLE(hlptim);
01081
01082   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01083   {
01084     return HAL_TIMEOUT;
01085   }
01086
01087   /* Disable Autoreload write complete interrupt */
01088   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
01089
01090   /* Disable Compare write complete interrupt */
01091   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
01092
01093   /* Disable Autoreload match interrupt */
01094   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
01095
01096   /* Disable Compare match interrupt */
01097   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
01098
01099   /* If external trigger source is used, then disable external trigger interrupt */
01100   if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
01101   {
01102     /* Disable external trigger interrupt */
01103     __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
01104   }
01105
01106   /* Change the TIM state*/
01107   hlptim->State = HAL_LPTIM_STATE_READY;
01108
01109   /* Return function status */
01110   return HAL_OK;
01111 }
01112
01113 /**
01114   * @brief  Start the Encoder interface.
01115   * @param  hlptim LPTIM handle
01116   * @param  Period Specifies the Autoreload value.
01117   *         This parameter must be a value between 0x0000 and 0xFFFF.
01118   * @retval HAL status
01119   */
01120 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
01121 {
01122   uint32_t          tmpcfgr;
01123
01124   /* Check the parameters */
01125   assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
01126   assert_param(IS_LPTIM_PERIOD(Period));
01127   assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
01128   assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
01129   assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
01130
01131   /* Set the LPTIM state */
01132   hlptim->State = HAL_LPTIM_STATE_BUSY;
01133
01134   /* Get the LPTIMx CFGR value */
01135   tmpcfgr = hlptim->Instance->CFGR;
01136
01137   /* Clear CKPOL bits */
01138   tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
01139
01140   /* Set Input polarity */
01141   tmpcfgr |=  hlptim->Init.UltraLowPowerClock.Polarity;
01142
01143   /* Write to LPTIMx CFGR */
01144   hlptim->Instance->CFGR = tmpcfgr;
01145
01146   /* Set ENC bit to enable the encoder interface */
01147   hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
01148
01149   /* Enable the Peripheral */
01150   __HAL_LPTIM_ENABLE(hlptim);
01151
01152   /* Clear flag */
01153   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
01154
01155   /* Load the period value in the autoreload register */
01156   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01157
01158   /* Wait for the completion of the write operation to the LPTIM_ARR register */
01159   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
01160   {
01161     return HAL_TIMEOUT;
01162   }
01163
01164   /* Start timer in continuous mode */
01165   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01166
01167   /* Change the TIM state*/
01168   hlptim->State = HAL_LPTIM_STATE_READY;
01169
01170   /* Return function status */
01171   return HAL_OK;
01172 }
01173
01174 /**
01175   * @brief  Stop the Encoder interface.
01176   * @param  hlptim LPTIM handle
01177   * @retval HAL status
01178   */
01179 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)
01180 {
01181   /* Check the parameters */
01182   assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
01183
01184   /* Set the LPTIM state */
01185   hlptim->State = HAL_LPTIM_STATE_BUSY;
01186
01187   /* Disable the Peripheral */
01188   __HAL_LPTIM_DISABLE(hlptim);
01189
01190   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01191   {
01192     return HAL_TIMEOUT;
01193   }
01194
01195   /* Reset ENC bit to disable the encoder interface */
01196   hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
01197
01198   /* Change the TIM state*/
01199   hlptim->State = HAL_LPTIM_STATE_READY;
01200
01201   /* Return function status */
01202   return HAL_OK;
01203 }
01204
01205 /**
01206   * @brief  Start the Encoder interface in interrupt mode.
01207   * @param  hlptim LPTIM handle
01208   * @param  Period Specifies the Autoreload value.
01209   *         This parameter must be a value between 0x0000 and 0xFFFF.
01210   * @retval HAL status
01211   */
01212 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
01213 {
01214   uint32_t          tmpcfgr;
01215
01216   /* Check the parameters */
01217   assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
01218   assert_param(IS_LPTIM_PERIOD(Period));
01219   assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
01220   assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
01221   assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
01222
01223   /* Set the LPTIM state */
01224   hlptim->State = HAL_LPTIM_STATE_BUSY;
01225
01226   /* Configure edge sensitivity for encoder mode */
01227   /* Get the LPTIMx CFGR value */
01228   tmpcfgr = hlptim->Instance->CFGR;
01229
01230   /* Clear CKPOL bits */
01231   tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
01232
01233   /* Set Input polarity */
01234   tmpcfgr |=  hlptim->Init.UltraLowPowerClock.Polarity;
01235
01236   /* Write to LPTIMx CFGR */
01237   hlptim->Instance->CFGR = tmpcfgr;
01238
01239   /* Set ENC bit to enable the encoder interface */
01240   hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
01241
01242   /* Enable the Peripheral */
01243   __HAL_LPTIM_ENABLE(hlptim);
01244
01245   /* Clear flag */
01246   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
01247
01248   /* Load the period value in the autoreload register */
01249   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01250
01251   /* Wait for the completion of the write operation to the LPTIM_ARR register */
01252   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
01253   {
01254     return HAL_TIMEOUT;
01255   }
01256
01257   /* Disable the Peripheral */
01258   __HAL_LPTIM_DISABLE(hlptim);
01259
01260   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01261   {
01262     return HAL_TIMEOUT;
01263   }
01264
01265   /* Enable "switch to down direction" interrupt */
01266   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_DOWN);
01267
01268   /* Enable "switch to up direction" interrupt */
01269   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP);
01270
01271   /* Enable the Peripheral */
01272   __HAL_LPTIM_ENABLE(hlptim);
01273
01274   /* Start timer in continuous mode */
01275   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01276
01277   /* Change the TIM state*/
01278   hlptim->State = HAL_LPTIM_STATE_READY;
01279
01280   /* Return function status */
01281   return HAL_OK;
01282 }
01283
01284 /**
01285   * @brief  Stop the Encoder interface in interrupt mode.
01286   * @param  hlptim LPTIM handle
01287   * @retval HAL status
01288   */
01289 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)
01290 {
01291   /* Check the parameters */
01292   assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
01293
01294   /* Set the LPTIM state */
01295   hlptim->State = HAL_LPTIM_STATE_BUSY;
01296
01297   /* Disable the Peripheral */
01298   __HAL_LPTIM_DISABLE(hlptim);
01299
01300   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01301   {
01302     return HAL_TIMEOUT;
01303   }
01304
01305   /* Reset ENC bit to disable the encoder interface */
01306   hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
01307
01308   /* Disable "switch to down direction" interrupt */
01309   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_DOWN);
01310
01311   /* Disable "switch to up direction" interrupt */
01312   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP);
01313
01314   /* Change the TIM state*/
01315   hlptim->State = HAL_LPTIM_STATE_READY;
01316
01317   /* Return function status */
01318   return HAL_OK;
01319 }
01320
01321 /**
01322   * @brief  Start the Timeout function.
01323   * @note   The first trigger event will start the timer, any successive
01324   *         trigger event will reset the counter and the timer restarts.
01325   * @param  hlptim LPTIM handle
01326   * @param  Period Specifies the Autoreload value.
01327   *         This parameter must be a value between 0x0000 and 0xFFFF.
01328   * @param  Timeout Specifies the TimeOut value to reset the counter.
01329   *         This parameter must be a value between 0x0000 and 0xFFFF.
01330   * @retval HAL status
01331   */
01332 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
01333 {
01334   /* Check the parameters */
01335   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01336   assert_param(IS_LPTIM_PERIOD(Period));
01337   assert_param(IS_LPTIM_PULSE(Timeout));
01338
01339   /* Set the LPTIM state */
01340   hlptim->State = HAL_LPTIM_STATE_BUSY;
01341
01342   /* Set TIMOUT bit to enable the timeout function */
01343   hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
01344
01345   /* Enable the Peripheral */
01346   __HAL_LPTIM_ENABLE(hlptim);
01347
01348   /* Clear flag */
01349   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
01350
01351   /* Load the period value in the autoreload register */
01352   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01353
01354   /* Wait for the completion of the write operation to the LPTIM_ARR register */
01355   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
01356   {
01357     return HAL_TIMEOUT;
01358   }
01359
01360   /* Clear flag */
01361   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
01362
01363   /* Load the Timeout value in the compare register */
01364   __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
01365
01366   /* Wait for the completion of the write operation to the LPTIM_CMP register */
01367   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
01368   {
01369     return HAL_TIMEOUT;
01370   }
01371
01372   /* Start timer in continuous mode */
01373   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01374
01375   /* Change the TIM state*/
01376   hlptim->State = HAL_LPTIM_STATE_READY;
01377
01378   /* Return function status */
01379   return HAL_OK;
01380 }
01381
01382 /**
01383   * @brief  Stop the Timeout function.
01384   * @param  hlptim LPTIM handle
01385   * @retval HAL status
01386   */
01387 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)
01388 {
01389   /* Check the parameters */
01390   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01391
01392   /* Set the LPTIM state */
01393   hlptim->State = HAL_LPTIM_STATE_BUSY;
01394
01395   /* Disable the Peripheral */
01396   __HAL_LPTIM_DISABLE(hlptim);
01397
01398   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01399   {
01400     return HAL_TIMEOUT;
01401   }
01402
01403   /* Reset TIMOUT bit to enable the timeout function */
01404   hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
01405
01406   /* Change the TIM state*/
01407   hlptim->State = HAL_LPTIM_STATE_READY;
01408
01409   /* Return function status */
01410   return HAL_OK;
01411 }
01412
01413 /**
01414   * @brief  Start the Timeout function in interrupt mode.
01415   * @note   The first trigger event will start the timer, any successive
01416   *         trigger event will reset the counter and the timer restarts.
01417   * @param  hlptim LPTIM handle
01418   * @param  Period Specifies the Autoreload value.
01419   *         This parameter must be a value between 0x0000 and 0xFFFF.
01420   * @param  Timeout Specifies the TimeOut value to reset the counter.
01421   *         This parameter must be a value between 0x0000 and 0xFFFF.
01422   * @retval HAL status
01423   */
01424 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
01425 {
01426   /* Check the parameters */
01427   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01428   assert_param(IS_LPTIM_PERIOD(Period));
01429   assert_param(IS_LPTIM_PULSE(Timeout));
01430
01431   /* Set the LPTIM state */
01432   hlptim->State = HAL_LPTIM_STATE_BUSY;
01433
01434   /* Set TIMOUT bit to enable the timeout function */
01435   hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
01436
01437   /* Enable the Peripheral */
01438   __HAL_LPTIM_ENABLE(hlptim);
01439
01440   /* Clear flag */
01441   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
01442
01443   /* Load the period value in the autoreload register */
01444   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01445
01446   /* Wait for the completion of the write operation to the LPTIM_ARR register */
01447   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
01448   {
01449     return HAL_TIMEOUT;
01450   }
01451
01452   /* Clear flag */
01453   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
01454
01455   /* Load the Timeout value in the compare register */
01456   __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
01457
01458   /* Wait for the completion of the write operation to the LPTIM_CMP register */
01459   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
01460   {
01461     return HAL_TIMEOUT;
01462   }
01463
01464   /* Disable the Peripheral */
01465   __HAL_LPTIM_DISABLE(hlptim);
01466
01467   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01468   {
01469     return HAL_TIMEOUT;
01470   }
01471
01472   /* Enable Compare match interrupt */
01473   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
01474
01475   /* Enable the Peripheral */
01476   __HAL_LPTIM_ENABLE(hlptim);
01477
01478   /* Start timer in continuous mode */
01479   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01480
01481   /* Change the TIM state*/
01482   hlptim->State = HAL_LPTIM_STATE_READY;
01483
01484   /* Return function status */
01485   return HAL_OK;
01486 }
01487
01488 /**
01489   * @brief  Stop the Timeout function in interrupt mode.
01490   * @param  hlptim LPTIM handle
01491   * @retval HAL status
01492   */
01493 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
01494 {
01495   /* Check the parameters */
01496   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01497
01498   /* Set the LPTIM state */
01499   hlptim->State = HAL_LPTIM_STATE_BUSY;
01500
01501   /* Disable the Peripheral */
01502   __HAL_LPTIM_DISABLE(hlptim);
01503
01504   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01505   {
01506     return HAL_TIMEOUT;
01507   }
01508
01509   /* Reset TIMOUT bit to enable the timeout function */
01510   hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
01511
01512   /* Disable Compare match interrupt */
01513   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
01514
01515   /* Change the TIM state*/
01516   hlptim->State = HAL_LPTIM_STATE_READY;
01517
01518   /* Return function status */
01519   return HAL_OK;
01520 }
01521
01522 /**
01523   * @brief  Start the Counter mode.
01524   * @param  hlptim LPTIM handle
01525   * @param  Period Specifies the Autoreload value.
01526   *         This parameter must be a value between 0x0000 and 0xFFFF.
01527   * @retval HAL status
01528   */
01529 HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
01530 {
01531   /* Check the parameters */
01532   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01533   assert_param(IS_LPTIM_PERIOD(Period));
01534
01535   /* Set the LPTIM state */
01536   hlptim->State = HAL_LPTIM_STATE_BUSY;
01537
01538   /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
01539   if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
01540   {
01541     /* Check if clock is prescaled */
01542     assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
01543     /* Set clock prescaler to 0 */
01544     hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
01545   }
01546
01547   /* Enable the Peripheral */
01548   __HAL_LPTIM_ENABLE(hlptim);
01549
01550   /* Clear flag */
01551   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
01552
01553   /* Load the period value in the autoreload register */
01554   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01555
01556   /* Wait for the completion of the write operation to the LPTIM_ARR register */
01557   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
01558   {
01559     return HAL_TIMEOUT;
01560   }
01561
01562   /* Start timer in continuous mode */
01563   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01564
01565   /* Change the TIM state*/
01566   hlptim->State = HAL_LPTIM_STATE_READY;
01567
01568   /* Return function status */
01569   return HAL_OK;
01570 }
01571
01572 /**
01573   * @brief  Stop the Counter mode.
01574   * @param  hlptim LPTIM handle
01575   * @retval HAL status
01576   */
01577 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)
01578 {
01579   /* Check the parameters */
01580   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01581
01582   /* Set the LPTIM state */
01583   hlptim->State = HAL_LPTIM_STATE_BUSY;
01584
01585   /* Disable the Peripheral */
01586   __HAL_LPTIM_DISABLE(hlptim);
01587
01588   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01589   {
01590     return HAL_TIMEOUT;
01591   }
01592
01593   /* Change the TIM state*/
01594   hlptim->State = HAL_LPTIM_STATE_READY;
01595
01596   /* Return function status */
01597   return HAL_OK;
01598 }
01599
01600 /**
01601   * @brief  Start the Counter mode in interrupt mode.
01602   * @param  hlptim LPTIM handle
01603   * @param  Period Specifies the Autoreload value.
01604   *         This parameter must be a value between 0x0000 and 0xFFFF.
01605   * @retval HAL status
01606   */
01607 HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
01608 {
01609   /* Check the parameters */
01610   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01611   assert_param(IS_LPTIM_PERIOD(Period));
01612
01613   /* Set the LPTIM state */
01614   hlptim->State = HAL_LPTIM_STATE_BUSY;
01615
01616   /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
01617   if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
01618   {
01619     /* Check if clock is prescaled */
01620     assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
01621     /* Set clock prescaler to 0 */
01622     hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
01623   }
01624
01625   /* Enable the Peripheral */
01626   __HAL_LPTIM_ENABLE(hlptim);
01627
01628   /* Clear flag */
01629   __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
01630
01631   /* Load the period value in the autoreload register */
01632   __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
01633
01634   /* Wait for the completion of the write operation to the LPTIM_ARR register */
01635   if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
01636   {
01637     return HAL_TIMEOUT;
01638   }
01639
01640   /* Disable the Peripheral */
01641   __HAL_LPTIM_DISABLE(hlptim);
01642
01643   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01644   {
01645     return HAL_TIMEOUT;
01646   }
01647
01648   /* Enable Autoreload write complete interrupt */
01649   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
01650
01651   /* Enable Autoreload match interrupt */
01652   __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
01653
01654   /* Enable the Peripheral */
01655   __HAL_LPTIM_ENABLE(hlptim);
01656
01657   /* Start timer in continuous mode */
01658   __HAL_LPTIM_START_CONTINUOUS(hlptim);
01659
01660   /* Change the TIM state*/
01661   hlptim->State = HAL_LPTIM_STATE_READY;
01662
01663   /* Return function status */
01664   return HAL_OK;
01665 }
01666
01667 /**
01668   * @brief  Stop the Counter mode in interrupt mode.
01669   * @param  hlptim LPTIM handle
01670   * @retval HAL status
01671   */
01672 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
01673 {
01674   /* Check the parameters */
01675   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01676
01677   /* Set the LPTIM state */
01678   hlptim->State = HAL_LPTIM_STATE_BUSY;
01679
01680   /* Disable the Peripheral */
01681   __HAL_LPTIM_DISABLE(hlptim);
01682
01683   if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
01684   {
01685     return HAL_TIMEOUT;
01686   }
01687
01688   /* Disable Autoreload write complete interrupt */
01689   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
01690
01691   /* Disable Autoreload match interrupt */
01692   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
01693   /* Change the TIM state*/
01694   hlptim->State = HAL_LPTIM_STATE_READY;
01695
01696   /* Return function status */
01697   return HAL_OK;
01698 }
01699
01700 /**
01701   * @}
01702   */
01703
01704 /** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions
01705  *  @brief  Read operation functions.
01706  *
01707 @verbatim
01708   ==============================================================================
01709                   ##### LPTIM Read operation functions #####
01710   ==============================================================================
01711 [..]  This section provides LPTIM Reading functions.
01712       (+) Read the counter value.
01713       (+) Read the period (Auto-reload) value.
01714       (+) Read the pulse (Compare)value.
01715 @endverbatim
01716   * @{
01717   */
01718
01719 /**
01720   * @brief  Return the current counter value.
01721   * @param  hlptim LPTIM handle
01722   * @retval Counter value.
01723   */
01724 uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim)
01725 {
01726   /* Check the parameters */
01727   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01728
01729   return (hlptim->Instance->CNT);
01730 }
01731
01732 /**
01733   * @brief  Return the current Autoreload (Period) value.
01734   * @param  hlptim LPTIM handle
01735   * @retval Autoreload value.
01736   */
01737 uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim)
01738 {
01739   /* Check the parameters */
01740   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01741
01742   return (hlptim->Instance->ARR);
01743 }
01744
01745 /**
01746   * @brief  Return the current Compare (Pulse) value.
01747   * @param  hlptim LPTIM handle
01748   * @retval Compare value.
01749   */
01750 uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim)
01751 {
01752   /* Check the parameters */
01753   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
01754
01755   return (hlptim->Instance->CMP);
01756 }
01757
01758 /**
01759   * @}
01760   */
01761
01762 /** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks
01763  *  @brief  LPTIM  IRQ handler.
01764  *
01765 @verbatim
01766   ==============================================================================
01767                       ##### LPTIM IRQ handler and callbacks  #####
01768   ==============================================================================
01769 [..]  This section provides LPTIM IRQ handler and callback functions called within
01770       the IRQ handler:
01771    (+) LPTIM interrupt request handler
01772    (+) Compare match Callback
01773    (+) Auto-reload match Callback
01774    (+) External trigger event detection Callback
01775    (+) Compare register write complete Callback
01776    (+) Auto-reload register write complete Callback
01777    (+) Up-counting direction change Callback
01778    (+) Down-counting direction change Callback
01779
01780 @endverbatim
01781   * @{
01782   */
01783
01784 /**
01785   * @brief  Handle LPTIM interrupt request.
01786   * @param  hlptim LPTIM handle
01787   * @retval None
01788   */
01789 void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim)
01790 {
01791   /* Compare match interrupt */
01792   if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPM) != RESET)
01793   {
01794     if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPM) != RESET)
01795     {
01796       /* Clear Compare match flag */
01797       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPM);
01798
01799       /* Compare match Callback */
01800 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
01801       hlptim->CompareMatchCallback(hlptim);
01802 #else
01803       HAL_LPTIM_CompareMatchCallback(hlptim);
01804 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
01805     }
01806   }
01807
01808   /* Autoreload match interrupt */
01809   if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET)
01810   {
01811     if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) != RESET)
01812     {
01813       /* Clear Autoreload match flag */
01814       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM);
01815
01816       /* Autoreload match Callback */
01817 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
01818       hlptim->AutoReloadMatchCallback(hlptim);
01819 #else
01820       HAL_LPTIM_AutoReloadMatchCallback(hlptim);
01821 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
01822     }
01823   }
01824
01825   /* Trigger detected interrupt */
01826   if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET)
01827   {
01828     if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) != RESET)
01829     {
01830       /* Clear Trigger detected flag */
01831       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG);
01832
01833       /* Trigger detected callback */
01834 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
01835       hlptim->TriggerCallback(hlptim);
01836 #else
01837       HAL_LPTIM_TriggerCallback(hlptim);
01838 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
01839     }
01840   }
01841
01842   /* Compare write interrupt */
01843   if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPOK) != RESET)
01844   {
01845     if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPOK) != RESET)
01846     {
01847       /* Clear Compare write flag */
01848       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
01849
01850       /* Compare write Callback */
01851 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
01852       hlptim->CompareWriteCallback(hlptim);
01853 #else
01854       HAL_LPTIM_CompareWriteCallback(hlptim);
01855 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
01856     }
01857   }
01858
01859   /* Autoreload write interrupt */
01860   if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET)
01861   {
01862     if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) != RESET)
01863     {
01864       /* Clear Autoreload write flag */
01865       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
01866
01867       /* Autoreload write Callback */
01868 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
01869       hlptim->AutoReloadWriteCallback(hlptim);
01870 #else
01871       HAL_LPTIM_AutoReloadWriteCallback(hlptim);
01872 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
01873     }
01874   }
01875
01876   /* Direction counter changed from Down to Up interrupt */
01877   if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET)
01878   {
01879     if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) != RESET)
01880     {
01881       /* Clear Direction counter changed from Down to Up flag */
01882       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP);
01883
01884       /* Direction counter changed from Down to Up Callback */
01885 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
01886       hlptim->DirectionUpCallback(hlptim);
01887 #else
01888       HAL_LPTIM_DirectionUpCallback(hlptim);
01889 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
01890     }
01891   }
01892
01893   /* Direction counter changed from Up to Down interrupt */
01894   if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET)
01895   {
01896     if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) != RESET)
01897     {
01898       /* Clear Direction counter changed from Up to Down flag */
01899       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN);
01900
01901       /* Direction counter changed from Up to Down Callback */
01902 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
01903       hlptim->DirectionDownCallback(hlptim);
01904 #else
01905       HAL_LPTIM_DirectionDownCallback(hlptim);
01906 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
01907     }
01908   }
01909 }
01910
01911 /**
01912   * @brief  Compare match callback in non-blocking mode.
01913   * @param  hlptim LPTIM handle
01914   * @retval None
01915   */
01916 __weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)
01917 {
01918   /* Prevent unused argument(s) compilation warning */
01919   UNUSED(hlptim);
01920
01921   /* NOTE : This function should not be modified, when the callback is needed,
01922             the HAL_LPTIM_CompareMatchCallback could be implemented in the user file
01923    */
01924 }
01925
01926 /**
01927   * @brief  Autoreload match callback in non-blocking mode.
01928   * @param  hlptim LPTIM handle
01929   * @retval None
01930   */
01931 __weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
01932 {
01933   /* Prevent unused argument(s) compilation warning */
01934   UNUSED(hlptim);
01935
01936   /* NOTE : This function should not be modified, when the callback is needed,
01937             the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file
01938    */
01939 }
01940
01941 /**
01942   * @brief  Trigger detected callback in non-blocking mode.
01943   * @param  hlptim LPTIM handle
01944   * @retval None
01945   */
01946 __weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim)
01947 {
01948   /* Prevent unused argument(s) compilation warning */
01949   UNUSED(hlptim);
01950
01951   /* NOTE : This function should not be modified, when the callback is needed,
01952             the HAL_LPTIM_TriggerCallback could be implemented in the user file
01953    */
01954 }
01955
01956 /**
01957   * @brief  Compare write callback in non-blocking mode.
01958   * @param  hlptim LPTIM handle
01959   * @retval None
01960   */
01961 __weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim)
01962 {
01963   /* Prevent unused argument(s) compilation warning */
01964   UNUSED(hlptim);
01965
01966   /* NOTE : This function should not be modified, when the callback is needed,
01967             the HAL_LPTIM_CompareWriteCallback could be implemented in the user file
01968    */
01969 }
01970
01971 /**
01972   * @brief  Autoreload write callback in non-blocking mode.
01973   * @param  hlptim LPTIM handle
01974   * @retval None
01975   */
01976 __weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim)
01977 {
01978   /* Prevent unused argument(s) compilation warning */
01979   UNUSED(hlptim);
01980
01981   /* NOTE : This function should not be modified, when the callback is needed,
01982             the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file
01983    */
01984 }
01985
01986 /**
01987   * @brief  Direction counter changed from Down to Up callback in non-blocking mode.
01988   * @param  hlptim LPTIM handle
01989   * @retval None
01990   */
01991 __weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim)
01992 {
01993   /* Prevent unused argument(s) compilation warning */
01994   UNUSED(hlptim);
01995
01996   /* NOTE : This function should not be modified, when the callback is needed,
01997             the HAL_LPTIM_DirectionUpCallback could be implemented in the user file
01998    */
01999 }
02000
02001 /**
02002   * @brief  Direction counter changed from Up to Down callback in non-blocking mode.
02003   * @param  hlptim LPTIM handle
02004   * @retval None
02005   */
02006 __weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim)
02007 {
02008   /* Prevent unused argument(s) compilation warning */
02009   UNUSED(hlptim);
02010
02011   /* NOTE : This function should not be modified, when the callback is needed,
02012             the HAL_LPTIM_DirectionDownCallback could be implemented in the user file
02013    */
02014 }
02015
02016 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
02017 /**
02018   * @brief  Register a User LPTIM callback to be used instead of the weak predefined callback
02019   * @param hlptim LPTIM handle
02020   * @param CallbackID ID of the callback to be registered
02021   *        This parameter can be one of the following values:
02022   *          @arg @ref HAL_LPTIM_MSPINIT_CB_ID          LPTIM Base Msp Init Callback ID
02023   *          @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID        LPTIM Base Msp DeInit Callback ID
02024   *          @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID    Compare match Callback ID
02025   *          @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
02026   *          @arg @ref HAL_LPTIM_TRIGGER_CB_ID          External trigger event detection Callback ID
02027   *          @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID    Compare register write complete Callback ID
02028   *          @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
02029   *          @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID     Up-counting direction change Callback ID
02030   *          @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID   Down-counting direction change Callback ID
02031   * @param pCallback pointer to the callback function
02032   * @retval status
02033   */
02034 HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef        *hlptim,
02035                                              HAL_LPTIM_CallbackIDTypeDef CallbackID,
02036                                              pLPTIM_CallbackTypeDef      pCallback)
02037 {
02038   HAL_StatusTypeDef status = HAL_OK;
02039
02040   if (pCallback == NULL)
02041   {
02042     return HAL_ERROR;
02043   }
02044
02045   /* Process locked */
02046   __HAL_LOCK(hlptim);
02047
02048   if (hlptim->State == HAL_LPTIM_STATE_READY)
02049   {
02050     switch (CallbackID)
02051     {
02052       case HAL_LPTIM_MSPINIT_CB_ID :
02053         hlptim->MspInitCallback = pCallback;
02054         break;
02055
02056       case HAL_LPTIM_MSPDEINIT_CB_ID :
02057         hlptim->MspDeInitCallback = pCallback;
02058         break;
02059
02060       case HAL_LPTIM_COMPARE_MATCH_CB_ID :
02061         hlptim->CompareMatchCallback = pCallback;
02062         break;
02063
02064       case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID :
02065         hlptim->AutoReloadMatchCallback = pCallback;
02066         break;
02067
02068       case HAL_LPTIM_TRIGGER_CB_ID :
02069         hlptim->TriggerCallback = pCallback;
02070         break;
02071
02072       case HAL_LPTIM_COMPARE_WRITE_CB_ID :
02073         hlptim->CompareWriteCallback = pCallback;
02074         break;
02075
02076       case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID :
02077         hlptim->AutoReloadWriteCallback = pCallback;
02078         break;
02079
02080       case HAL_LPTIM_DIRECTION_UP_CB_ID :
02081         hlptim->DirectionUpCallback = pCallback;
02082         break;
02083
02084       case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
02085         hlptim->DirectionDownCallback = pCallback;
02086         break;
02087
02088       default :
02089         /* Return error status */
02090         status =  HAL_ERROR;
02091         break;
02092     }
02093   }
02094   else if (hlptim->State == HAL_LPTIM_STATE_RESET)
02095   {
02096     switch (CallbackID)
02097     {
02098       case HAL_LPTIM_MSPINIT_CB_ID :
02099         hlptim->MspInitCallback = pCallback;
02100         break;
02101
02102       case HAL_LPTIM_MSPDEINIT_CB_ID :
02103         hlptim->MspDeInitCallback = pCallback;
02104         break;
02105
02106       default :
02107         /* Return error status */
02108         status =  HAL_ERROR;
02109         break;
02110     }
02111   }
02112   else
02113   {
02114     /* Return error status */
02115     status =  HAL_ERROR;
02116   }
02117
02118   /* Release Lock */
02119   __HAL_UNLOCK(hlptim);
02120
02121   return status;
02122 }
02123
02124 /**
02125   * @brief  Unregister a LPTIM callback
02126   *         LLPTIM callback is redirected to the weak predefined callback
02127   * @param hlptim LPTIM handle
02128   * @param CallbackID ID of the callback to be unregistered
02129   *        This parameter can be one of the following values:
02130   *          @arg @ref HAL_LPTIM_MSPINIT_CB_ID          LPTIM Base Msp Init Callback ID
02131   *          @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID        LPTIM Base Msp DeInit Callback ID
02132   *          @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID    Compare match Callback ID
02133   *          @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
02134   *          @arg @ref HAL_LPTIM_TRIGGER_CB_ID          External trigger event detection Callback ID
02135   *          @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID    Compare register write complete Callback ID
02136   *          @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
02137   *          @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID     Up-counting direction change Callback ID
02138   *          @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID   Down-counting direction change Callback ID
02139   * @retval status
02140   */
02141 HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef        *hlptim,
02142                                                HAL_LPTIM_CallbackIDTypeDef CallbackID)
02143 {
02144   HAL_StatusTypeDef status = HAL_OK;
02145
02146   /* Process locked */
02147   __HAL_LOCK(hlptim);
02148
02149   if (hlptim->State == HAL_LPTIM_STATE_READY)
02150   {
02151     switch (CallbackID)
02152     {
02153       case HAL_LPTIM_MSPINIT_CB_ID :
02154         hlptim->MspInitCallback = HAL_LPTIM_MspInit;                          /* Legacy weak MspInit Callback */
02155         break;
02156
02157       case HAL_LPTIM_MSPDEINIT_CB_ID :
02158         hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;                       /* Legacy weak Msp DeInit Callback */
02159         break;
02160
02161       case HAL_LPTIM_COMPARE_MATCH_CB_ID :
02162         hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback;         /* Legacy weak Compare match Callback */
02163         break;
02164
02165       case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID :
02166         hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback;   /* Legacy weak Auto-reload match Callback */
02167         break;
02168
02169       case HAL_LPTIM_TRIGGER_CB_ID :
02170         hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback;                   /* Legacy weak External trigger event detection Callback */
02171         break;
02172
02173       case HAL_LPTIM_COMPARE_WRITE_CB_ID :
02174         hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback;         /* Legacy weak Compare register write complete Callback */
02175         break;
02176
02177       case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID :
02178         hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback;   /* Legacy weak Auto-reload register write complete Callback */
02179         break;
02180
02181       case HAL_LPTIM_DIRECTION_UP_CB_ID :
02182         hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback;           /* Legacy weak Up-counting direction change Callback */
02183         break;
02184
02185       case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
02186         hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback;       /* Legacy weak Down-counting direction change Callback */
02187         break;
02188
02189       default :
02190         /* Return error status */
02191         status =  HAL_ERROR;
02192         break;
02193     }
02194   }
02195   else if (hlptim->State == HAL_LPTIM_STATE_RESET)
02196   {
02197     switch (CallbackID)
02198     {
02199       case HAL_LPTIM_MSPINIT_CB_ID :
02200         hlptim->MspInitCallback = HAL_LPTIM_MspInit;                           /* Legacy weak MspInit Callback */
02201         break;
02202
02203       case HAL_LPTIM_MSPDEINIT_CB_ID :
02204         hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;                        /* Legacy weak Msp DeInit Callback */
02205         break;
02206
02207       default :
02208         /* Return error status */
02209         status =  HAL_ERROR;
02210         break;
02211     }
02212   }
02213   else
02214   {
02215     /* Return error status */
02216     status =  HAL_ERROR;
02217   }
02218
02219   /* Release Lock */
02220   __HAL_UNLOCK(hlptim);
02221
02222   return status;
02223 }
02224 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
02225
02226 /**
02227   * @}
02228   */
02229
02230 /** @defgroup LPTIM_Group5 Peripheral State functions
02231  *  @brief   Peripheral State functions.
02232  *
02233 @verbatim
02234   ==============================================================================
02235                       ##### Peripheral State functions #####
02236   ==============================================================================
02237     [..]
02238     This subsection permits to get in run-time the status of the peripheral.
02239
02240 @endverbatim
02241   * @{
02242   */
02243
02244 /**
02245   * @brief  Return the LPTIM handle state.
02246   * @param  hlptim LPTIM handle
02247   * @retval HAL state
02248   */
02249 HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim)
02250 {
02251   /* Return LPTIM handle state */
02252   return hlptim->State;
02253 }
02254
02255 /**
02256   * @}
02257   */
02258
02259
02260 /**
02261   * @}
02262   */
02263
02264 /* Private functions ---------------------------------------------------------*/
02265
02266 /** @defgroup LPTIM_Private_Functions LPTIM Private Functions
02267   * @{
02268   */
02269 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
02270 /**
02271   * @brief  Reset interrupt callbacks to the legacy weak callbacks.
02272   * @param  lptim pointer to a LPTIM_HandleTypeDef structure that contains
02273   *                the configuration information for LPTIM module.
02274   * @retval None
02275   */
02276 static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim)
02277 {
02278   /* Reset the LPTIM callback to the legacy weak callbacks */
02279   lptim->CompareMatchCallback    = HAL_LPTIM_CompareMatchCallback;    /* Compare match Callback                       */
02280   lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; /* Auto-reload match Callback                   */
02281   lptim->TriggerCallback         = HAL_LPTIM_TriggerCallback;         /* External trigger event detection Callback    */
02282   lptim->CompareWriteCallback    = HAL_LPTIM_CompareWriteCallback;    /* Compare register write complete Callback     */
02283   lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; /* Auto-reload register write complete Callback */
02284   lptim->DirectionUpCallback     = HAL_LPTIM_DirectionUpCallback;     /* Up-counting direction change Callback        */
02285   lptim->DirectionDownCallback   = HAL_LPTIM_DirectionDownCallback;   /* Down-counting direction change Callback      */
02286 }
02287 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
02288
02289 /**
02290   * @brief  LPTimer Wait for flag set
02291   * @param  hlptim pointer to a LPTIM_HandleTypeDef structure that contains
02292   *                the configuration information for LPTIM module.
02293   * @param  flag   The lptim flag
02294   * @retval HAL status
02295   */
02296 static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag)
02297 {
02298   HAL_StatusTypeDef result = HAL_OK;
02299   uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL);
02300     do
02301     {
02302       count--;
02303       if (count == 0UL)
02304       {
02305         result = HAL_TIMEOUT;
02306       }
02307     }
02308     while((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
02309
02310     return result;
02311 }
02312
02313 /**
02314   * @brief  Disable LPTIM HW instance.
02315   * @param  hlptim pointer to a LPTIM_HandleTypeDef structure that contains
02316   *                the configuration information for LPTIM module.
02317   * @note   The following sequence is required to solve LPTIM disable HW limitation.
02318   *         Please check Errata Sheet ES0335 for more details under "MCU may remain
02319   *         stuck in LPTIM interrupt when entering Stop mode" section.
02320   * @retval None
02321   */
02322 void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim)
02323 {
02324   uint32_t tmpclksource = 0;
02325   uint32_t tmpIER;
02326   uint32_t tmpCFGR;
02327   uint32_t tmpCMP;
02328   uint32_t tmpARR;
02329   uint32_t tmpOR;
02330
02331   __disable_irq();
02332
02333   /*********** Save LPTIM Config ***********/
02334   /* Save LPTIM source clock */
02335   switch ((uint32_t)hlptim->Instance)
02336   {
02337      case LPTIM1_BASE:
02338        tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE();
02339        break;
02340 #if defined(LPTIM2)
02341      case LPTIM2_BASE:
02342        tmpclksource = __HAL_RCC_GET_LPTIM2_SOURCE();
02343        break;
02344 #endif /* LPTIM2 */
02345      default:
02346        break;
02347   }
02348
02349   /* Save LPTIM configuration registers */
02350   tmpIER = hlptim->Instance->IER;
02351   tmpCFGR = hlptim->Instance->CFGR;
02352   tmpCMP = hlptim->Instance->CMP;
02353   tmpARR = hlptim->Instance->ARR;
02354   tmpOR = hlptim->Instance->OR;
02355
02356   /*********** Reset LPTIM ***********/
02357   switch ((uint32_t)hlptim->Instance)
02358   {
02359      case LPTIM1_BASE:
02360        __HAL_RCC_LPTIM1_FORCE_RESET();
02361        __HAL_RCC_LPTIM1_RELEASE_RESET();
02362        break;
02363 #if defined(LPTIM2)
02364      case LPTIM2_BASE:
02365        __HAL_RCC_LPTIM2_FORCE_RESET();
02366        __HAL_RCC_LPTIM2_RELEASE_RESET();
02367        break;
02368 #endif /* LPTIM2 */
02369      default:
02370        break;
02371   }
02372
02373   /*********** Restore LPTIM Config ***********/
02374   if ((tmpCMP != 0UL) || (tmpARR != 0UL))
02375   {
02376     /* Force LPTIM source kernel clock from APB */
02377     switch ((uint32_t)hlptim->Instance)
02378     {
02379        case LPTIM1_BASE:
02380          __HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_PCLK1);
02381          break;
02382 #if defined(LPTIM2)
02383        case LPTIM2_BASE:
02384          __HAL_RCC_LPTIM2_CONFIG(RCC_LPTIM2CLKSOURCE_PCLK1);
02385          break;
02386 #endif /* LPTIM2 */
02387        default:
02388          break;
02389     }
02390
02391     if (tmpCMP != 0UL)
02392     {
02393       /* Restore CMP register (LPTIM should be enabled first) */
02394       hlptim->Instance->CR |= LPTIM_CR_ENABLE;
02395       hlptim->Instance->CMP = tmpCMP;
02396
02397       /* Wait for the completion of the write operation to the LPTIM_CMP register */
02398       if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
02399       {
02400         hlptim->State = HAL_LPTIM_STATE_TIMEOUT;
02401       }
02402       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
02403     }
02404
02405     if (tmpARR != 0UL)
02406     {
02407       /* Restore ARR register (LPTIM should be enabled first) */
02408       hlptim->Instance->CR |= LPTIM_CR_ENABLE;
02409       hlptim->Instance->ARR = tmpARR;
02410
02411       /* Wait for the completion of the write operation to the LPTIM_ARR register */
02412       if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
02413       {
02414         hlptim->State = HAL_LPTIM_STATE_TIMEOUT;
02415       }
02416
02417       __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
02418     }
02419
02420     /* Restore LPTIM source kernel clock */
02421     switch ((uint32_t)hlptim->Instance)
02422     {
02423        case LPTIM1_BASE:
02424          __HAL_RCC_LPTIM1_CONFIG(tmpclksource);
02425          break;
02426 #if defined(LPTIM2)
02427        case LPTIM2_BASE:
02428          __HAL_RCC_LPTIM2_CONFIG(tmpclksource);
02429          break;
02430 #endif /* LPTIM2 */
02431        default:
02432          break;
02433     }
02434   }
02435
02436   /* Restore configuration registers (LPTIM should be disabled first) */
02437   hlptim->Instance->CR &= ~(LPTIM_CR_ENABLE);
02438   hlptim->Instance->IER = tmpIER;
02439   hlptim->Instance->CFGR = tmpCFGR;
02440   hlptim->Instance->OR = tmpOR;
02441
02442   __enable_irq();
02443 }
02444 /**
02445   * @}
02446   */
02447 #endif /* LPTIM1 || LPTIM2 */
02448
02449 #endif /* HAL_LPTIM_MODULE_ENABLED */
02450 /**
02451   * @}
02452   */
02453
02454 /**
02455   * @}
02456   */
02457
02458 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_lptim.h Source File

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stm32wbxx_hal_lptim.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_lptim.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of LPTIM HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_LPTIM_H
00022 #define STM32WBxx_HAL_LPTIM_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 /** @addtogroup STM32WBxx_HAL_Driver
00032   * @{
00033   */
00034
00035 #if defined (LPTIM1) || defined (LPTIM2)
00036
00037 /** @addtogroup LPTIM
00038   * @{
00039   */
00040
00041 /* Exported types ------------------------------------------------------------*/
00042 /** @defgroup LPTIM_Exported_Types LPTIM Exported Types
00043   * @{
00044   */
00045 #define LPTIM_EXTI_LINE_LPTIM1  EXTI_IMR1_IM29  /*!< External interrupt line 29 Connected to the LPTIM1 EXTI Line */
00046 #define LPTIM_EXTI_LINE_LPTIM2  EXTI_IMR1_IM30  /*!< External interrupt line 30 Connected to the LPTIM2 EXTI Line */
00047
00048 /**
00049   * @brief  LPTIM Clock configuration definition
00050   */
00051 typedef struct
00052 {
00053   uint32_t Source;         /*!< Selects the clock source.
00054                            This parameter can be a value of @ref LPTIM_Clock_Source   */
00055
00056   uint32_t Prescaler;      /*!< Specifies the counter clock Prescaler.
00057                            This parameter can be a value of @ref LPTIM_Clock_Prescaler */
00058
00059 } LPTIM_ClockConfigTypeDef;
00060
00061 /**
00062   * @brief  LPTIM Clock configuration definition
00063   */
00064 typedef struct
00065 {
00066   uint32_t Polarity;      /*!< Selects the polarity of the active edge for the counter unit
00067                            if the ULPTIM input is selected.
00068                            Note: This parameter is used only when Ultra low power clock source is used.
00069                            Note: If the polarity is configured on 'both edges', an auxiliary clock
00070                            (one of the Low power oscillator) must be active.
00071                            This parameter can be a value of @ref LPTIM_Clock_Polarity */
00072
00073   uint32_t SampleTime;     /*!< Selects the clock sampling time to configure the clock glitch filter.
00074                            Note: This parameter is used only when Ultra low power clock source is used.
00075                            This parameter can be a value of @ref LPTIM_Clock_Sample_Time */
00076
00077 } LPTIM_ULPClockConfigTypeDef;
00078
00079 /**
00080   * @brief  LPTIM Trigger configuration definition
00081   */
00082 typedef struct
00083 {
00084   uint32_t Source;        /*!< Selects the Trigger source.
00085                           This parameter can be a value of @ref LPTIM_Trigger_Source */
00086
00087   uint32_t ActiveEdge;    /*!< Selects the Trigger active edge.
00088                           Note: This parameter is used only when an external trigger is used.
00089                           This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */
00090
00091   uint32_t SampleTime;    /*!< Selects the trigger sampling time to configure the clock glitch filter.
00092                           Note: This parameter is used only when an external trigger is used.
00093                           This parameter can be a value of @ref LPTIM_Trigger_Sample_Time  */
00094 } LPTIM_TriggerConfigTypeDef;
00095
00096 /**
00097   * @brief  LPTIM Initialization Structure definition
00098   */
00099 typedef struct
00100 {
00101   LPTIM_ClockConfigTypeDef     Clock;               /*!< Specifies the clock parameters */
00102
00103   LPTIM_ULPClockConfigTypeDef  UltraLowPowerClock;  /*!< Specifies the Ultra Low Power clock parameters */
00104
00105   LPTIM_TriggerConfigTypeDef   Trigger;             /*!< Specifies the Trigger parameters */
00106
00107   uint32_t                     OutputPolarity;      /*!< Specifies the Output polarity.
00108                                                     This parameter can be a value of @ref LPTIM_Output_Polarity */
00109
00110   uint32_t                     UpdateMode;          /*!< Specifies whether the update of the autoreload and the compare
00111                                                     values is done immediately or after the end of current period.
00112                                                     This parameter can be a value of @ref LPTIM_Updating_Mode */
00113
00114   uint32_t                     CounterSource;       /*!< Specifies whether the counter is incremented each internal event
00115                                                     or each external event.
00116                                                     This parameter can be a value of @ref LPTIM_Counter_Source */
00117
00118   uint32_t                     Input1Source;        /*!< Specifies source selected for input1 (GPIO or comparator output).
00119                                                     This parameter can be a value of @ref LPTIM_Input1_Source */
00120
00121   uint32_t                     Input2Source;        /*!< Specifies source selected for input2 (GPIO or comparator output).
00122                                                     Note: This parameter is used only for encoder feature so is used only
00123                                                     for LPTIM1 instance.
00124                                                     This parameter can be a value of @ref LPTIM_Input2_Source */
00125 } LPTIM_InitTypeDef;
00126
00127 /**
00128   * @brief  HAL LPTIM State structure definition
00129   */
00130 typedef enum
00131 {
00132   HAL_LPTIM_STATE_RESET            = 0x00U,    /*!< Peripheral not yet initialized or disabled  */
00133   HAL_LPTIM_STATE_READY            = 0x01U,    /*!< Peripheral Initialized and ready for use    */
00134   HAL_LPTIM_STATE_BUSY             = 0x02U,    /*!< An internal process is ongoing              */
00135   HAL_LPTIM_STATE_TIMEOUT          = 0x03U,    /*!< Timeout state                               */
00136   HAL_LPTIM_STATE_ERROR            = 0x04U     /*!< Internal Process is ongoing                 */
00137 } HAL_LPTIM_StateTypeDef;
00138
00139 /**
00140   * @brief  LPTIM handle Structure definition
00141   */
00142 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
00143 typedef struct __LPTIM_HandleTypeDef
00144 #else
00145 typedef struct
00146 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
00147 {
00148   LPTIM_TypeDef                 *Instance;         /*!< Register base address     */
00149
00150   LPTIM_InitTypeDef              Init;             /*!< LPTIM required parameters */
00151
00152   HAL_StatusTypeDef              Status;           /*!< LPTIM peripheral status   */
00153
00154   HAL_LockTypeDef                Lock;             /*!< LPTIM locking object      */
00155
00156   __IO  HAL_LPTIM_StateTypeDef   State;            /*!< LPTIM peripheral state    */
00157
00158 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
00159   void (* MspInitCallback)(struct __LPTIM_HandleTypeDef *hlptim);            /*!< LPTIM Base Msp Init Callback                 */
00160   void (* MspDeInitCallback)(struct __LPTIM_HandleTypeDef *hlptim);          /*!< LPTIM Base Msp DeInit Callback               */
00161   void (* CompareMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim);       /*!< Compare match Callback                       */
00162   void (* AutoReloadMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim);    /*!< Auto-reload match Callback                   */
00163   void (* TriggerCallback)(struct __LPTIM_HandleTypeDef *hlptim);            /*!< External trigger event detection Callback    */
00164   void (* CompareWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim);       /*!< Compare register write complete Callback     */
00165   void (* AutoReloadWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim);    /*!< Auto-reload register write complete Callback */
00166   void (* DirectionUpCallback)(struct __LPTIM_HandleTypeDef *hlptim);        /*!< Up-counting direction change Callback        */
00167   void (* DirectionDownCallback)(struct __LPTIM_HandleTypeDef *hlptim);      /*!< Down-counting direction change Callback      */
00168 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
00169 } LPTIM_HandleTypeDef;
00170
00171 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
00172 /**
00173   * @brief  HAL LPTIM Callback ID enumeration definition
00174   */
00175 typedef enum
00176 {
00177   HAL_LPTIM_MSPINIT_CB_ID          = 0x00U,    /*!< LPTIM Base Msp Init Callback ID                  */
00178   HAL_LPTIM_MSPDEINIT_CB_ID        = 0x01U,    /*!< LPTIM Base Msp DeInit Callback ID                */
00179   HAL_LPTIM_COMPARE_MATCH_CB_ID    = 0x02U,    /*!< Compare match Callback ID                        */
00180   HAL_LPTIM_AUTORELOAD_MATCH_CB_ID = 0x03U,    /*!< Auto-reload match Callback ID                    */
00181   HAL_LPTIM_TRIGGER_CB_ID          = 0x04U,    /*!< External trigger event detection Callback ID     */
00182   HAL_LPTIM_COMPARE_WRITE_CB_ID    = 0x05U,    /*!< Compare register write complete Callback ID      */
00183   HAL_LPTIM_AUTORELOAD_WRITE_CB_ID = 0x06U,    /*!< Auto-reload register write complete Callback ID  */
00184   HAL_LPTIM_DIRECTION_UP_CB_ID     = 0x07U,    /*!< Up-counting direction change Callback ID         */
00185   HAL_LPTIM_DIRECTION_DOWN_CB_ID   = 0x08U,    /*!< Down-counting direction change Callback ID       */
00186 } HAL_LPTIM_CallbackIDTypeDef;
00187
00188 /**
00189   * @brief  HAL TIM Callback pointer definition
00190   */
00191 typedef  void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim);  /*!< pointer to the LPTIM callback function */
00192
00193 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
00194 /**
00195   * @}
00196   */
00197
00198 /* Exported constants --------------------------------------------------------*/
00199 /** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants
00200   * @{
00201   */
00202
00203 /** @defgroup LPTIM_Clock_Source LPTIM Clock Source
00204   * @{
00205   */
00206 #define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC        0x00000000U
00207 #define LPTIM_CLOCKSOURCE_ULPTIM                LPTIM_CFGR_CKSEL
00208 /**
00209   * @}
00210   */
00211
00212 /** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler
00213   * @{
00214   */
00215 #define LPTIM_PRESCALER_DIV1                    0x00000000U
00216 #define LPTIM_PRESCALER_DIV2                    LPTIM_CFGR_PRESC_0
00217 #define LPTIM_PRESCALER_DIV4                    LPTIM_CFGR_PRESC_1
00218 #define LPTIM_PRESCALER_DIV8                    (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1)
00219 #define LPTIM_PRESCALER_DIV16                   LPTIM_CFGR_PRESC_2
00220 #define LPTIM_PRESCALER_DIV32                   (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2)
00221 #define LPTIM_PRESCALER_DIV64                   (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2)
00222 #define LPTIM_PRESCALER_DIV128                  LPTIM_CFGR_PRESC
00223 /**
00224   * @}
00225   */
00226
00227 /** @defgroup LPTIM_Output_Polarity LPTIM Output Polarity
00228   * @{
00229   */
00230
00231 #define LPTIM_OUTPUTPOLARITY_HIGH               0x00000000U
00232 #define LPTIM_OUTPUTPOLARITY_LOW                LPTIM_CFGR_WAVPOL
00233 /**
00234   * @}
00235   */
00236
00237 /** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time
00238   * @{
00239   */
00240 #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION  0x00000000U
00241 #define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS      LPTIM_CFGR_CKFLT_0
00242 #define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS      LPTIM_CFGR_CKFLT_1
00243 #define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS      LPTIM_CFGR_CKFLT
00244 /**
00245   * @}
00246   */
00247
00248 /** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity
00249   * @{
00250   */
00251 #define LPTIM_CLOCKPOLARITY_RISING              0x00000000U
00252 #define LPTIM_CLOCKPOLARITY_FALLING             LPTIM_CFGR_CKPOL_0
00253 #define LPTIM_CLOCKPOLARITY_RISING_FALLING      LPTIM_CFGR_CKPOL_1
00254 /**
00255   * @}
00256   */
00257
00258 /** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source
00259   * @{
00260   */
00261 #define LPTIM_TRIGSOURCE_SOFTWARE               0x0000FFFFU
00262 #define LPTIM_TRIGSOURCE_0                      0x00000000U
00263 #define LPTIM_TRIGSOURCE_1                      LPTIM_CFGR_TRIGSEL_0
00264 #define LPTIM_TRIGSOURCE_2                      LPTIM_CFGR_TRIGSEL_1
00265 #define LPTIM_TRIGSOURCE_3                      (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
00266 #define LPTIM_TRIGSOURCE_4                      LPTIM_CFGR_TRIGSEL_2
00267 #define LPTIM_TRIGSOURCE_5                      (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
00268 #define LPTIM_TRIGSOURCE_6                      (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)
00269 #define LPTIM_TRIGSOURCE_7                      LPTIM_CFGR_TRIGSEL
00270 /**
00271   * @}
00272   */
00273
00274 /** @defgroup LPTIM_External_Trigger_Polarity LPTIM External Trigger Polarity
00275   * @{
00276   */
00277 #define LPTIM_ACTIVEEDGE_RISING                LPTIM_CFGR_TRIGEN_0
00278 #define LPTIM_ACTIVEEDGE_FALLING               LPTIM_CFGR_TRIGEN_1
00279 #define LPTIM_ACTIVEEDGE_RISING_FALLING        LPTIM_CFGR_TRIGEN
00280 /**
00281   * @}
00282   */
00283
00284 /** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time
00285   * @{
00286   */
00287 #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION  0x00000000U
00288 #define LPTIM_TRIGSAMPLETIME_2TRANSITIONS      LPTIM_CFGR_TRGFLT_0
00289 #define LPTIM_TRIGSAMPLETIME_4TRANSITIONS      LPTIM_CFGR_TRGFLT_1
00290 #define LPTIM_TRIGSAMPLETIME_8TRANSITIONS      LPTIM_CFGR_TRGFLT
00291 /**
00292   * @}
00293   */
00294
00295 /** @defgroup LPTIM_Updating_Mode LPTIM Updating Mode
00296   * @{
00297   */
00298
00299 #define LPTIM_UPDATE_IMMEDIATE                  0x00000000U
00300 #define LPTIM_UPDATE_ENDOFPERIOD                LPTIM_CFGR_PRELOAD
00301 /**
00302   * @}
00303   */
00304
00305 /** @defgroup LPTIM_Counter_Source LPTIM Counter Source
00306   * @{
00307   */
00308
00309 #define LPTIM_COUNTERSOURCE_INTERNAL            0x00000000U
00310 #define LPTIM_COUNTERSOURCE_EXTERNAL            LPTIM_CFGR_COUNTMODE
00311 /**
00312   * @}
00313   */
00314
00315 /** @defgroup LPTIM_Input1_Source LPTIM Input1 Source
00316   * @{
00317   */
00318
00319 #define LPTIM_INPUT1SOURCE_GPIO          0x00000000U   /*!< For LPTIM1 and LPTIM2 */
00320 #define LPTIM_INPUT1SOURCE_COMP1         LPTIM_OR_OR_0 /*!< For LPTIM1 and LPTIM2 */
00321 #define LPTIM_INPUT1SOURCE_COMP2         LPTIM_OR_OR_1 /*!< For LPTIM2 */
00322 #define LPTIM_INPUT1SOURCE_COMP1_COMP2   LPTIM_OR_OR   /*!< For LPTIM2 */
00323 /**
00324   * @}
00325   */
00326
00327 /** @defgroup LPTIM_Input2_Source LPTIM Input2 Source
00328   * @{
00329   */
00330
00331 #define LPTIM_INPUT2SOURCE_GPIO         0x00000000U                    /*!< For LPTIM1 */
00332 #define LPTIM_INPUT2SOURCE_COMP2        LPTIM_OR_OR_1                  /*!< For LPTIM1 */
00333 /**
00334   * @}
00335   */
00336
00337 /** @defgroup LPTIM_Flag_Definition LPTIM Flags Definition
00338   * @{
00339   */
00340
00341 #define LPTIM_FLAG_DOWN                          LPTIM_ISR_DOWN
00342 #define LPTIM_FLAG_UP                            LPTIM_ISR_UP
00343 #define LPTIM_FLAG_ARROK                         LPTIM_ISR_ARROK
00344 #define LPTIM_FLAG_CMPOK                         LPTIM_ISR_CMPOK
00345 #define LPTIM_FLAG_EXTTRIG                       LPTIM_ISR_EXTTRIG
00346 #define LPTIM_FLAG_ARRM                          LPTIM_ISR_ARRM
00347 #define LPTIM_FLAG_CMPM                          LPTIM_ISR_CMPM
00348 /**
00349   * @}
00350   */
00351
00352 /** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition
00353   * @{
00354   */
00355 #define LPTIM_IT_DOWN                            LPTIM_IER_DOWNIE
00356 #define LPTIM_IT_UP                              LPTIM_IER_UPIE
00357 #define LPTIM_IT_ARROK                           LPTIM_IER_ARROKIE
00358 #define LPTIM_IT_CMPOK                           LPTIM_IER_CMPOKIE
00359 #define LPTIM_IT_EXTTRIG                         LPTIM_IER_EXTTRIGIE
00360 #define LPTIM_IT_ARRM                            LPTIM_IER_ARRMIE
00361 #define LPTIM_IT_CMPM                            LPTIM_IER_CMPMIE
00362 /**
00363   * @}
00364   */
00365
00366 /**
00367   * @}
00368   */
00369
00370 /* Exported macros -----------------------------------------------------------*/
00371 /** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros
00372   * @{
00373   */
00374
00375 /** @brief Reset LPTIM handle state.
00376   * @param  __HANDLE__ LPTIM handle
00377   * @retval None
00378   */
00379 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
00380 #define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                        \
00381                                                       (__HANDLE__)->State             = HAL_LPTIM_STATE_RESET; \
00382                                                       (__HANDLE__)->MspInitCallback   = NULL;                  \
00383                                                       (__HANDLE__)->MspDeInitCallback = NULL;                  \
00384                                                      } while(0)
00385 #else
00386 #define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
00387 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
00388
00389 /**
00390   * @brief  Enable the LPTIM peripheral.
00391   * @param  __HANDLE__ LPTIM handle
00392   * @retval None
00393   */
00394 #define __HAL_LPTIM_ENABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
00395
00396 /**
00397   * @brief  Disable the LPTIM peripheral.
00398   * @param  __HANDLE__ LPTIM handle
00399   * @note   The following sequence is required to solve LPTIM disable HW limitation.
00400   *         Please check Errata Sheet ES0335 for more details under "MCU may remain
00401   *         stuck in LPTIM interrupt when entering Stop mode" section.
00402   * @note   Please call @ref HAL_LPTIM_GetState() after a call to __HAL_LPTIM_DISABLE to
00403   *         check for TIMEOUT.
00404   * @retval None
00405   */
00406 #define __HAL_LPTIM_DISABLE(__HANDLE__)   LPTIM_Disable(__HANDLE__)
00407
00408 /**
00409   * @brief  Start the LPTIM peripheral in Continuous mode.
00410   * @param  __HANDLE__ LPTIM handle
00411   * @retval None
00412   */
00413 #define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  LPTIM_CR_CNTSTRT)
00414 /**
00415   * @brief  Start the LPTIM peripheral in single mode.
00416   * @param  __HANDLE__ LPTIM handle
00417   * @retval None
00418   */
00419 #define __HAL_LPTIM_START_SINGLE(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  LPTIM_CR_SNGSTRT)
00420
00421 /**
00422   * @brief  Reset the LPTIM Counter register in synchronous mode.
00423   * @param  __HANDLE__ LPTIM handle
00424   * @retval None
00425   */
00426 #define __HAL_LPTIM_RESET_COUNTER(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  LPTIM_CR_COUNTRST)
00427
00428 /**
00429   * @brief  Reset after read of the LPTIM Counter register in asynchronous mode.
00430   * @param  __HANDLE__ LPTIM handle
00431   * @retval None
00432   */
00433 #define __HAL_LPTIM_RESET_COUNTER_AFTERREAD(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  LPTIM_CR_RSTARE)
00434
00435 /**
00436   * @brief  Write the passed parameter in the Autoreload register.
00437   * @param  __HANDLE__ LPTIM handle
00438   * @param  __VALUE__ Autoreload value
00439   * @retval None
00440   * @note   The ARR register can only be modified when the LPTIM instance is enabled.
00441   */
00442 #define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__)  ((__HANDLE__)->Instance->ARR =  (__VALUE__))
00443
00444 /**
00445   * @brief  Write the passed parameter in the Compare register.
00446   * @param  __HANDLE__ LPTIM handle
00447   * @param  __VALUE__ Compare value
00448   * @retval None
00449   * @note   The CMP register can only be modified when the LPTIM instance is enabled.
00450   */
00451 #define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__)     ((__HANDLE__)->Instance->CMP =  (__VALUE__))
00452
00453 /**
00454   * @brief  Check whether the specified LPTIM flag is set or not.
00455   * @param  __HANDLE__ LPTIM handle
00456   * @param  __FLAG__ LPTIM flag to check
00457   *            This parameter can be a value of:
00458   *            @arg LPTIM_FLAG_DOWN    : Counter direction change up Flag.
00459   *            @arg LPTIM_FLAG_UP      : Counter direction change down to up Flag.
00460   *            @arg LPTIM_FLAG_ARROK   : Autoreload register update OK Flag.
00461   *            @arg LPTIM_FLAG_CMPOK   : Compare register update OK Flag.
00462   *            @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
00463   *            @arg LPTIM_FLAG_ARRM    : Autoreload match Flag.
00464   *            @arg LPTIM_FLAG_CMPM    : Compare match Flag.
00465   * @retval The state of the specified flag (SET or RESET).
00466   */
00467 #define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
00468
00469 /**
00470   * @brief  Clear the specified LPTIM flag.
00471   * @param  __HANDLE__ LPTIM handle.
00472   * @param  __FLAG__ LPTIM flag to clear.
00473   *            This parameter can be a value of:
00474   *            @arg LPTIM_FLAG_DOWN    : Counter direction change up Flag.
00475   *            @arg LPTIM_FLAG_UP      : Counter direction change down to up Flag.
00476   *            @arg LPTIM_FLAG_ARROK   : Autoreload register update OK Flag.
00477   *            @arg LPTIM_FLAG_CMPOK   : Compare register update OK Flag.
00478   *            @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
00479   *            @arg LPTIM_FLAG_ARRM    : Autoreload match Flag.
00480   *            @arg LPTIM_FLAG_CMPM    : Compare match Flag.
00481   * @retval None.
00482   */
00483 #define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->ICR  = (__FLAG__))
00484
00485 /**
00486   * @brief  Enable the specified LPTIM interrupt.
00487   * @param  __HANDLE__ LPTIM handle.
00488   * @param  __INTERRUPT__ LPTIM interrupt to set.
00489   *            This parameter can be a value of:
00490   *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
00491   *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
00492   *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
00493   *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
00494   *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
00495   *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
00496   *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
00497   * @retval None.
00498   * @note   The LPTIM interrupts can only be enabled when the LPTIM instance is disabled.
00499   */
00500 #define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->IER  |= (__INTERRUPT__))
00501
00502 /**
00503   * @brief  Disable the specified LPTIM interrupt.
00504   * @param  __HANDLE__ LPTIM handle.
00505   * @param  __INTERRUPT__ LPTIM interrupt to set.
00506   *            This parameter can be a value of:
00507   *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
00508   *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
00509   *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
00510   *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
00511   *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
00512   *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
00513   *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
00514   * @retval None.
00515   * @note   The LPTIM interrupts can only be disabled when the LPTIM instance is disabled.
00516   */
00517 #define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->IER  &= (~(__INTERRUPT__)))
00518
00519 /**
00520   * @brief  Check whether the specified LPTIM interrupt source is enabled or not.
00521   * @param  __HANDLE__ LPTIM handle.
00522   * @param  __INTERRUPT__ LPTIM interrupt to check.
00523   *            This parameter can be a value of:
00524   *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
00525   *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
00526   *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
00527   *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
00528   *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
00529   *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
00530   *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
00531   * @retval Interrupt status.
00532   */
00533
00534 #define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00535
00536 /**
00537   * @brief  Enable the LPTIM1 EXTI line in interrupt mode.
00538   * @retval None
00539   */
00540 #define __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT()            (EXTI->IMR1 |= LPTIM_EXTI_LINE_LPTIM1)
00541
00542 /**
00543   * @brief  Disable the LPTIM1 EXTI line in interrupt mode.
00544   * @retval None
00545   */
00546 #define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT()           (EXTI->IMR1 &= ~(LPTIM_EXTI_LINE_LPTIM1))
00547
00548
00549 /**
00550   * @brief  Enable the LPTIM1 EXTI line in event mode.
00551   * @retval None
00552   */
00553 #define __HAL_LPTIM_LPTIM1_EXTI_ENABLE_EVENT()         (EXTI->EMR1 |= LPTIM_EXTI_LINE_LPTIM1)
00554
00555 /**
00556   * @brief  Disable the LPTIM1 EXTI line in event mode.
00557   * @retval None
00558   */
00559 #define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_EVENT()        (EXTI->EMR1 &= ~(LPTIM_EXTI_LINE_LPTIM1))
00560
00561 /**
00562   * @brief  Enable the LPTIM2 EXTI line in interrupt mode.
00563   * @retval None
00564   */
00565 #define __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT()            (EXTI->IMR1 |= LPTIM_EXTI_LINE_LPTIM2)
00566
00567 /**
00568   * @brief  Disable the LPTIM2 EXTI line in interrupt mode.
00569   * @retval None
00570   */
00571 #define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT()           (EXTI->IMR1 &= ~(LPTIM_EXTI_LINE_LPTIM2))
00572
00573
00574 /**
00575   * @brief  Enable the LPTIM2 EXTI line in event mode.
00576   * @retval None
00577   */
00578 #define __HAL_LPTIM_LPTIM2_EXTI_ENABLE_EVENT()         (EXTI->EMR1 |= LPTIM_EXTI_LINE_LPTIM2)
00579
00580 /**
00581   * @brief  Disable the LPTIM2 EXTI line in event mode.
00582   * @retval None
00583   */
00584 #define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_EVENT()        (EXTI->EMR1 &= ~(LPTIM_EXTI_LINE_LPTIM2))
00585
00586 /**
00587   * @}
00588   */
00589
00590 /* Exported functions --------------------------------------------------------*/
00591 /** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
00592   * @{
00593   */
00594
00595 /* Initialization/de-initialization functions  ********************************/
00596 HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
00597 HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
00598
00599 /* MSP functions  *************************************************************/
00600 void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);
00601 void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
00602
00603 /* Start/Stop operation functions  *********************************************/
00604 /* ################################# PWM Mode ################################*/
00605 /* Blocking mode: Polling */
00606 HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00607 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim);
00608 /* Non-Blocking mode: Interrupt */
00609 HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00610 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00611
00612 /* ############################# One Pulse Mode ##############################*/
00613 /* Blocking mode: Polling */
00614 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00615 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim);
00616 /* Non-Blocking mode: Interrupt */
00617 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00618 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00619
00620 /* ############################## Set once Mode ##############################*/
00621 /* Blocking mode: Polling */
00622 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00623 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim);
00624 /* Non-Blocking mode: Interrupt */
00625 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
00626 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00627
00628 /* ############################### Encoder Mode ##############################*/
00629 /* Blocking mode: Polling */
00630 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
00631 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim);
00632 /* Non-Blocking mode: Interrupt */
00633 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
00634 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00635
00636 /* ############################# Time out  Mode ##############################*/
00637 /* Blocking mode: Polling */
00638 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
00639 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim);
00640 /* Non-Blocking mode: Interrupt */
00641 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
00642 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00643
00644 /* ############################## Counter Mode ###############################*/
00645 /* Blocking mode: Polling */
00646 HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
00647 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim);
00648 /* Non-Blocking mode: Interrupt */
00649 HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
00650 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
00651
00652 /* Reading operation functions ************************************************/
00653 uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
00654 uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
00655 uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);
00656
00657 /* LPTIM IRQ functions  *******************************************************/
00658 void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
00659
00660 /* CallBack functions  ********************************************************/
00661 void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim);
00662 void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim);
00663 void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim);
00664 void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim);
00665 void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim);
00666 void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim);
00667 void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
00668
00669 /* Callbacks Register/UnRegister functions  ***********************************/
00670 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
00671 HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback);
00672 HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID);
00673 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
00674
00675 /* Peripheral State functions  ************************************************/
00676 HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
00677
00678 /**
00679   * @}
00680   */
00681
00682 /* Private types -------------------------------------------------------------*/
00683 /** @defgroup LPTIM_Private_Types LPTIM Private Types
00684   * @{
00685   */
00686
00687 /**
00688   * @}
00689   */
00690
00691 /* Private variables ---------------------------------------------------------*/
00692 /** @defgroup LPTIM_Private_Variables LPTIM Private Variables
00693   * @{
00694   */
00695
00696 /**
00697   * @}
00698   */
00699
00700 /* Private constants ---------------------------------------------------------*/
00701 /** @defgroup LPTIM_Private_Constants LPTIM Private Constants
00702   * @{
00703   */
00704
00705 /**
00706   * @}
00707   */
00708
00709 /* Private macros ------------------------------------------------------------*/
00710 /** @defgroup LPTIM_Private_Macros LPTIM Private Macros
00711   * @{
00712   */
00713
00714 #define IS_LPTIM_CLOCK_SOURCE(__SOURCE__)       (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
00715                                                  ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))
00716
00717
00718 #define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1  ) || \
00719                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV2  ) || \
00720                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV4  ) || \
00721                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV8  ) || \
00722                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV16 ) || \
00723                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV32 ) || \
00724                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV64 ) || \
00725                                                  ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV128))
00726
00727 #define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1)
00728
00729 #define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__)  (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \
00730                                                  ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))
00731
00732 #define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
00733                                                     ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS)     || \
00734                                                     ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS)     || \
00735                                                     ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))
00736
00737 #define IS_LPTIM_CLOCK_POLARITY(__POLARITY__)   (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING)  || \
00738                                                  ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
00739                                                  ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))
00740
00741 #define IS_LPTIM_TRG_SOURCE(__TRIG__)           (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
00742                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
00743                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
00744                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
00745                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
00746                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
00747                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_5) || \
00748                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_6) || \
00749                                                  ((__TRIG__) == LPTIM_TRIGSOURCE_7))
00750
00751 #define IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING         ) || \
00752                                                  ((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING        ) || \
00753                                                  ((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))
00754
00755 #define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
00756                                                    ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS    ) || \
00757                                                    ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS    ) || \
00758                                                    ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS    ))
00759
00760 #define IS_LPTIM_UPDATE_MODE(__MODE__)          (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
00761                                                  ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))
00762
00763 #define IS_LPTIM_COUNTER_SOURCE(__SOURCE__)     (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
00764                                                  ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
00765
00766 #define IS_LPTIM_AUTORELOAD(__AUTORELOAD__)     ((__AUTORELOAD__) <= 0x0000FFFFUL)
00767
00768 #define IS_LPTIM_COMPARE(__COMPARE__)           ((__COMPARE__) <= 0x0000FFFFUL)
00769
00770 #define IS_LPTIM_PERIOD(__PERIOD__)             ((__PERIOD__) <= 0x0000FFFFUL)
00771
00772 #define IS_LPTIM_PULSE(__PULSE__)               ((__PULSE__) <= 0x0000FFFFUL)
00773
00774 #define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__)  \
00775     ((((__INSTANCE__) == LPTIM1) &&                       \
00776      (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) ||        \
00777       ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1)))        \
00778      ||                                                   \
00779      (((__INSTANCE__) == LPTIM2) &&                       \
00780      (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) ||        \
00781       ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) ||       \
00782       ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) ||       \
00783       ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2))))
00784
00785 #define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__)  \
00786      (((__INSTANCE__) == LPTIM1) &&                       \
00787      (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) ||        \
00788       ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2)))
00789
00790 /**
00791   * @}
00792   */
00793
00794 /* Private functions ---------------------------------------------------------*/
00795 /** @defgroup LPTIM_Private_Functions LPTIM Private Functions
00796   * @{
00797   */
00798 void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim);
00799 /**
00800   * @}
00801   */
00802
00803 /**
00804   * @}
00805   */
00806
00807 #endif /* LPTIM1 || LPTIM2 */
00808 /**
00809   * @}
00810   */
00811
00812 #ifdef __cplusplus
00813 }
00814 #endif
00815
00816 #endif /* STM32WBxx_HAL_LPTIM_H */
00817
00818 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_pcd.c Source File

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stm32wbxx_hal_pcd.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_pcd.c
00004   * @author  MCD Application Team
00005   * @brief   PCD HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the USB Peripheral Controller:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral Control functions
00011   *           + Peripheral State functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                     ##### How to use this driver #####
00016   ==============================================================================
00017     [..]
00018       The PCD HAL driver can be used as follows:
00019
00020      (#) Declare a PCD_HandleTypeDef handle structure, for example:
00021          PCD_HandleTypeDef  hpcd;
00022
00023      (#) Fill parameters of Init structure in HCD handle
00024
00025      (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...)
00026
00027      (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
00028          (##) Enable the PCD/USB Low Level interface clock using
00029               (+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device only FS peripheral
00030
00031          (##) Initialize the related GPIO clocks
00032          (##) Configure PCD pin-out
00033          (##) Configure PCD NVIC interrupt
00034
00035      (#)Associate the Upper USB device stack to the HAL PCD Driver:
00036          (##) hpcd.pData = pdev;
00037
00038      (#)Enable PCD transmission and reception:
00039          (##) HAL_PCD_Start();
00040
00041   @endverbatim
00042   ******************************************************************************
00043   * @attention
00044   *
00045   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00046   * All rights reserved.</center></h2>
00047   *
00048   * This software component is licensed by ST under BSD 3-Clause license,
00049   * the "License"; You may not use this file except in compliance with the
00050   * License. You may obtain a copy of the License at:
00051   *                        opensource.org/licenses/BSD-3-Clause
00052   *
00053   ******************************************************************************
00054   */
00055
00056 /* Includes ------------------------------------------------------------------*/
00057 #include "stm32wbxx_hal.h"
00058
00059 /** @addtogroup STM32WBxx_HAL_Driver
00060   * @{
00061   */
00062
00063 /** @defgroup PCD PCD
00064   * @brief PCD HAL module driver
00065   * @{
00066   */
00067
00068 #ifdef HAL_PCD_MODULE_ENABLED
00069
00070 #if defined (USB)
00071
00072 /* Private types -------------------------------------------------------------*/
00073 /* Private variables ---------------------------------------------------------*/
00074 /* Private constants ---------------------------------------------------------*/
00075 /* Private macros ------------------------------------------------------------*/
00076 /** @defgroup PCD_Private_Macros PCD Private Macros
00077   * @{
00078   */
00079 #define PCD_MIN(a, b)  (((a) < (b)) ? (a) : (b))
00080 #define PCD_MAX(a, b)  (((a) > (b)) ? (a) : (b))
00081 /**
00082   * @}
00083   */
00084
00085 /* Private functions prototypes ----------------------------------------------*/
00086 /** @defgroup PCD_Private_Functions PCD Private Functions
00087   * @{
00088   */
00089
00090 static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd);
00091
00092 /**
00093   * @}
00094   */
00095
00096 /* Exported functions --------------------------------------------------------*/
00097 /** @defgroup PCD_Exported_Functions PCD Exported Functions
00098   * @{
00099   */
00100
00101 /** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
00102  *  @brief    Initialization and Configuration functions
00103  *
00104 @verbatim
00105  ===============================================================================
00106             ##### Initialization and de-initialization functions #####
00107  ===============================================================================
00108     [..]  This section provides functions allowing to:
00109
00110 @endverbatim
00111   * @{
00112   */
00113
00114 /**
00115   * @brief  Initializes the PCD according to the specified
00116   *         parameters in the PCD_InitTypeDef and initialize the associated handle.
00117   * @param  hpcd PCD handle
00118   * @retval HAL status
00119   */
00120 HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
00121 {
00122   uint8_t i;
00123
00124   /* Check the PCD handle allocation */
00125   if (hpcd == NULL)
00126   {
00127     return HAL_ERROR;
00128   }
00129
00130   /* Check the parameters */
00131   assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
00132
00133   if (hpcd->State == HAL_PCD_STATE_RESET)
00134   {
00135     /* Allocate lock resource and initialize it */
00136     hpcd->Lock = HAL_UNLOCKED;
00137
00138 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00139     hpcd->SOFCallback = HAL_PCD_SOFCallback;
00140     hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
00141     hpcd->ResetCallback = HAL_PCD_ResetCallback;
00142     hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
00143     hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
00144     hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
00145     hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
00146     hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback;
00147     hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback;
00148     hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback;
00149     hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback;
00150     hpcd->LPMCallback = HAL_PCDEx_LPM_Callback;
00151     hpcd->BCDCallback = HAL_PCDEx_BCD_Callback;
00152
00153     if (hpcd->MspInitCallback == NULL)
00154     {
00155       hpcd->MspInitCallback = HAL_PCD_MspInit;
00156     }
00157
00158     /* Init the low level hardware */
00159     hpcd->MspInitCallback(hpcd);
00160 #else
00161     /* Init the low level hardware : GPIO, CLOCK, NVIC... */
00162     HAL_PCD_MspInit(hpcd);
00163 #endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
00164   }
00165
00166   hpcd->State = HAL_PCD_STATE_BUSY;
00167
00168   /* Disable the Interrupts */
00169   __HAL_PCD_DISABLE(hpcd);
00170
00171   /* Init endpoints structures */
00172   for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
00173   {
00174     /* Init ep structure */
00175     hpcd->IN_ep[i].is_in = 1U;
00176     hpcd->IN_ep[i].num = i;
00177     hpcd->IN_ep[i].tx_fifo_num = i;
00178     /* Control until ep is activated */
00179     hpcd->IN_ep[i].type = EP_TYPE_CTRL;
00180     hpcd->IN_ep[i].maxpacket = 0U;
00181     hpcd->IN_ep[i].xfer_buff = 0U;
00182     hpcd->IN_ep[i].xfer_len = 0U;
00183   }
00184
00185   for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
00186   {
00187     hpcd->OUT_ep[i].is_in = 0U;
00188     hpcd->OUT_ep[i].num = i;
00189     /* Control until ep is activated */
00190     hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
00191     hpcd->OUT_ep[i].maxpacket = 0U;
00192     hpcd->OUT_ep[i].xfer_buff = 0U;
00193     hpcd->OUT_ep[i].xfer_len = 0U;
00194   }
00195
00196   /* Init Device */
00197   (void)USB_DevInit(hpcd->Instance, hpcd->Init);
00198
00199   hpcd->USB_Address = 0U;
00200   hpcd->State = HAL_PCD_STATE_READY;
00201
00202   /* Activate LPM */
00203   if (hpcd->Init.lpm_enable == 1U)
00204   {
00205     (void)HAL_PCDEx_ActivateLPM(hpcd);
00206   }
00207
00208   return HAL_OK;
00209 }
00210
00211 /**
00212   * @brief  DeInitializes the PCD peripheral.
00213   * @param  hpcd PCD handle
00214   * @retval HAL status
00215   */
00216 HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
00217 {
00218   /* Check the PCD handle allocation */
00219   if (hpcd == NULL)
00220   {
00221     return HAL_ERROR;
00222   }
00223
00224   hpcd->State = HAL_PCD_STATE_BUSY;
00225
00226   /* Stop Device */
00227   (void)HAL_PCD_Stop(hpcd);
00228
00229 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00230   if (hpcd->MspDeInitCallback == NULL)
00231   {
00232     hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; /* Legacy weak MspDeInit  */
00233   }
00234
00235   /* DeInit the low level hardware */
00236   hpcd->MspDeInitCallback(hpcd);
00237 #else
00238   /* DeInit the low level hardware: CLOCK, NVIC.*/
00239   HAL_PCD_MspDeInit(hpcd);
00240 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00241
00242   hpcd->State = HAL_PCD_STATE_RESET;
00243
00244   return HAL_OK;
00245 }
00246
00247 /**
00248   * @brief  Initializes the PCD MSP.
00249   * @param  hpcd PCD handle
00250   * @retval None
00251   */
00252 __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
00253 {
00254   /* Prevent unused argument(s) compilation warning */
00255   UNUSED(hpcd);
00256
00257   /* NOTE : This function should not be modified, when the callback is needed,
00258             the HAL_PCD_MspInit could be implemented in the user file
00259    */
00260 }
00261
00262 /**
00263   * @brief  DeInitializes PCD MSP.
00264   * @param  hpcd PCD handle
00265   * @retval None
00266   */
00267 __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
00268 {
00269   /* Prevent unused argument(s) compilation warning */
00270   UNUSED(hpcd);
00271
00272   /* NOTE : This function should not be modified, when the callback is needed,
00273             the HAL_PCD_MspDeInit could be implemented in the user file
00274    */
00275 }
00276
00277 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00278 /**
00279   * @brief  Register a User USB PCD Callback
00280   *         To be used instead of the weak predefined callback
00281   * @param  hpcd USB PCD handle
00282   * @param  CallbackID ID of the callback to be registered
00283   *         This parameter can be one of the following values:
00284   *          @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
00285   *          @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
00286   *          @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
00287   *          @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
00288   *          @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
00289   *          @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
00290   *          @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
00291   *          @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
00292   *          @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
00293   * @param  pCallback pointer to the Callback function
00294   * @retval HAL status
00295   */
00296 HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback)
00297 {
00298   HAL_StatusTypeDef status = HAL_OK;
00299
00300   if (pCallback == NULL)
00301   {
00302     /* Update the error code */
00303     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00304     return HAL_ERROR;
00305   }
00306   /* Process locked */
00307   __HAL_LOCK(hpcd);
00308
00309   if (hpcd->State == HAL_PCD_STATE_READY)
00310   {
00311     switch (CallbackID)
00312     {
00313       case HAL_PCD_SOF_CB_ID :
00314         hpcd->SOFCallback = pCallback;
00315         break;
00316
00317       case HAL_PCD_SETUPSTAGE_CB_ID :
00318         hpcd->SetupStageCallback = pCallback;
00319         break;
00320
00321       case HAL_PCD_RESET_CB_ID :
00322         hpcd->ResetCallback = pCallback;
00323         break;
00324
00325       case HAL_PCD_SUSPEND_CB_ID :
00326         hpcd->SuspendCallback = pCallback;
00327         break;
00328
00329       case HAL_PCD_RESUME_CB_ID :
00330         hpcd->ResumeCallback = pCallback;
00331         break;
00332
00333       case HAL_PCD_CONNECT_CB_ID :
00334         hpcd->ConnectCallback = pCallback;
00335         break;
00336
00337       case HAL_PCD_DISCONNECT_CB_ID :
00338         hpcd->DisconnectCallback = pCallback;
00339         break;
00340
00341       case HAL_PCD_MSPINIT_CB_ID :
00342         hpcd->MspInitCallback = pCallback;
00343         break;
00344
00345       case HAL_PCD_MSPDEINIT_CB_ID :
00346         hpcd->MspDeInitCallback = pCallback;
00347         break;
00348
00349       default :
00350         /* Update the error code */
00351         hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00352         /* Return error status */
00353         status =  HAL_ERROR;
00354         break;
00355     }
00356   }
00357   else if (hpcd->State == HAL_PCD_STATE_RESET)
00358   {
00359     switch (CallbackID)
00360     {
00361       case HAL_PCD_MSPINIT_CB_ID :
00362         hpcd->MspInitCallback = pCallback;
00363         break;
00364
00365       case HAL_PCD_MSPDEINIT_CB_ID :
00366         hpcd->MspDeInitCallback = pCallback;
00367         break;
00368
00369       default :
00370         /* Update the error code */
00371         hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00372         /* Return error status */
00373         status =  HAL_ERROR;
00374         break;
00375     }
00376   }
00377   else
00378   {
00379     /* Update the error code */
00380     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00381     /* Return error status */
00382     status =  HAL_ERROR;
00383   }
00384
00385   /* Release Lock */
00386   __HAL_UNLOCK(hpcd);
00387   return status;
00388 }
00389
00390 /**
00391   * @brief  Unregister an USB PCD Callback
00392   *         USB PCD callabck is redirected to the weak predefined callback
00393   * @param  hpcd USB PCD handle
00394   * @param  CallbackID ID of the callback to be unregistered
00395   *         This parameter can be one of the following values:
00396   *          @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
00397   *          @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
00398   *          @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
00399   *          @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
00400   *          @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
00401   *          @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
00402   *          @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
00403   *          @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
00404   *          @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
00405   * @retval HAL status
00406   */
00407 HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID)
00408 {
00409   HAL_StatusTypeDef status = HAL_OK;
00410
00411   /* Process locked */
00412   __HAL_LOCK(hpcd);
00413
00414   /* Setup Legacy weak Callbacks  */
00415   if (hpcd->State == HAL_PCD_STATE_READY)
00416   {
00417     switch (CallbackID)
00418     {
00419       case HAL_PCD_SOF_CB_ID :
00420         hpcd->SOFCallback = HAL_PCD_SOFCallback;
00421         break;
00422
00423       case HAL_PCD_SETUPSTAGE_CB_ID :
00424         hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
00425         break;
00426
00427       case HAL_PCD_RESET_CB_ID :
00428         hpcd->ResetCallback = HAL_PCD_ResetCallback;
00429         break;
00430
00431       case HAL_PCD_SUSPEND_CB_ID :
00432         hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
00433         break;
00434
00435       case HAL_PCD_RESUME_CB_ID :
00436         hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
00437         break;
00438
00439       case HAL_PCD_CONNECT_CB_ID :
00440         hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
00441         break;
00442
00443       case HAL_PCD_DISCONNECT_CB_ID :
00444         hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
00445         break;
00446
00447       case HAL_PCD_MSPINIT_CB_ID :
00448         hpcd->MspInitCallback = HAL_PCD_MspInit;
00449         break;
00450
00451       case HAL_PCD_MSPDEINIT_CB_ID :
00452         hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
00453         break;
00454
00455       default :
00456         /* Update the error code */
00457         hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00458
00459         /* Return error status */
00460         status =  HAL_ERROR;
00461         break;
00462     }
00463   }
00464   else if (hpcd->State == HAL_PCD_STATE_RESET)
00465   {
00466     switch (CallbackID)
00467     {
00468       case HAL_PCD_MSPINIT_CB_ID :
00469         hpcd->MspInitCallback = HAL_PCD_MspInit;
00470         break;
00471
00472       case HAL_PCD_MSPDEINIT_CB_ID :
00473         hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
00474         break;
00475
00476       default :
00477         /* Update the error code */
00478         hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00479
00480         /* Return error status */
00481         status =  HAL_ERROR;
00482         break;
00483     }
00484   }
00485   else
00486   {
00487     /* Update the error code */
00488     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00489
00490     /* Return error status */
00491     status =  HAL_ERROR;
00492   }
00493
00494   /* Release Lock */
00495   __HAL_UNLOCK(hpcd);
00496   return status;
00497 }
00498
00499 /**
00500   * @brief  Register USB PCD Data OUT Stage Callback
00501   *         To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback
00502   * @param  hpcd PCD handle
00503   * @param  pCallback pointer to the USB PCD Data OUT Stage Callback function
00504   * @retval HAL status
00505   */
00506 HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback)
00507 {
00508   HAL_StatusTypeDef status = HAL_OK;
00509
00510   if (pCallback == NULL)
00511   {
00512     /* Update the error code */
00513     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00514
00515     return HAL_ERROR;
00516   }
00517
00518   /* Process locked */
00519   __HAL_LOCK(hpcd);
00520
00521   if (hpcd->State == HAL_PCD_STATE_READY)
00522   {
00523     hpcd->DataOutStageCallback = pCallback;
00524   }
00525   else
00526   {
00527     /* Update the error code */
00528     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00529
00530     /* Return error status */
00531     status =  HAL_ERROR;
00532   }
00533
00534   /* Release Lock */
00535   __HAL_UNLOCK(hpcd);
00536
00537   return status;
00538 }
00539
00540 /**
00541   * @brief  UnRegister the USB PCD Data OUT Stage Callback
00542   *         USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback
00543   * @param  hpcd PCD handle
00544   * @retval HAL status
00545   */
00546 HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd)
00547 {
00548   HAL_StatusTypeDef status = HAL_OK;
00549
00550   /* Process locked */
00551   __HAL_LOCK(hpcd);
00552
00553   if (hpcd->State == HAL_PCD_STATE_READY)
00554   {
00555     hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; /* Legacy weak DataOutStageCallback  */
00556   }
00557   else
00558   {
00559     /* Update the error code */
00560     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00561
00562     /* Return error status */
00563     status =  HAL_ERROR;
00564   }
00565
00566   /* Release Lock */
00567   __HAL_UNLOCK(hpcd);
00568
00569   return status;
00570 }
00571
00572 /**
00573   * @brief  Register USB PCD Data IN Stage Callback
00574   *         To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback
00575   * @param  hpcd PCD handle
00576   * @param  pCallback pointer to the USB PCD Data IN Stage Callback function
00577   * @retval HAL status
00578   */
00579 HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback)
00580 {
00581   HAL_StatusTypeDef status = HAL_OK;
00582
00583   if (pCallback == NULL)
00584   {
00585     /* Update the error code */
00586     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00587
00588     return HAL_ERROR;
00589   }
00590
00591   /* Process locked */
00592   __HAL_LOCK(hpcd);
00593
00594   if (hpcd->State == HAL_PCD_STATE_READY)
00595   {
00596     hpcd->DataInStageCallback = pCallback;
00597   }
00598   else
00599   {
00600     /* Update the error code */
00601     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00602
00603     /* Return error status */
00604     status =  HAL_ERROR;
00605   }
00606
00607   /* Release Lock */
00608   __HAL_UNLOCK(hpcd);
00609
00610   return status;
00611 }
00612
00613 /**
00614   * @brief  UnRegister the USB PCD Data IN Stage Callback
00615   *         USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback
00616   * @param  hpcd PCD handle
00617   * @retval HAL status
00618   */
00619 HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd)
00620 {
00621   HAL_StatusTypeDef status = HAL_OK;
00622
00623   /* Process locked */
00624   __HAL_LOCK(hpcd);
00625
00626   if (hpcd->State == HAL_PCD_STATE_READY)
00627   {
00628     hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; /* Legacy weak DataInStageCallback  */
00629   }
00630   else
00631   {
00632     /* Update the error code */
00633     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00634
00635     /* Return error status */
00636     status =  HAL_ERROR;
00637   }
00638
00639   /* Release Lock */
00640   __HAL_UNLOCK(hpcd);
00641
00642   return status;
00643 }
00644
00645 /**
00646   * @brief  Register USB PCD Iso OUT incomplete Callback
00647   *         To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
00648   * @param  hpcd PCD handle
00649   * @param  pCallback pointer to the USB PCD Iso OUT incomplete Callback function
00650   * @retval HAL status
00651   */
00652 HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback)
00653 {
00654   HAL_StatusTypeDef status = HAL_OK;
00655
00656   if (pCallback == NULL)
00657   {
00658     /* Update the error code */
00659     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00660
00661     return HAL_ERROR;
00662   }
00663
00664   /* Process locked */
00665   __HAL_LOCK(hpcd);
00666
00667   if (hpcd->State == HAL_PCD_STATE_READY)
00668   {
00669     hpcd->ISOOUTIncompleteCallback = pCallback;
00670   }
00671   else
00672   {
00673     /* Update the error code */
00674     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00675
00676     /* Return error status */
00677     status =  HAL_ERROR;
00678   }
00679
00680   /* Release Lock */
00681   __HAL_UNLOCK(hpcd);
00682
00683   return status;
00684 }
00685
00686 /**
00687   * @brief  UnRegister the USB PCD Iso OUT incomplete Callback
00688   *         USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
00689   * @param  hpcd PCD handle
00690   * @retval HAL status
00691   */
00692 HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd)
00693 {
00694   HAL_StatusTypeDef status = HAL_OK;
00695
00696   /* Process locked */
00697   __HAL_LOCK(hpcd);
00698
00699   if (hpcd->State == HAL_PCD_STATE_READY)
00700   {
00701     hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; /* Legacy weak ISOOUTIncompleteCallback  */
00702   }
00703   else
00704   {
00705     /* Update the error code */
00706     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00707
00708     /* Return error status */
00709     status =  HAL_ERROR;
00710   }
00711
00712   /* Release Lock */
00713   __HAL_UNLOCK(hpcd);
00714
00715   return status;
00716 }
00717
00718 /**
00719   * @brief  Register USB PCD Iso IN incomplete Callback
00720   *         To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
00721   * @param  hpcd PCD handle
00722   * @param  pCallback pointer to the USB PCD Iso IN incomplete Callback function
00723   * @retval HAL status
00724   */
00725 HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback)
00726 {
00727   HAL_StatusTypeDef status = HAL_OK;
00728
00729   if (pCallback == NULL)
00730   {
00731     /* Update the error code */
00732     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00733
00734     return HAL_ERROR;
00735   }
00736
00737   /* Process locked */
00738   __HAL_LOCK(hpcd);
00739
00740   if (hpcd->State == HAL_PCD_STATE_READY)
00741   {
00742     hpcd->ISOINIncompleteCallback = pCallback;
00743   }
00744   else
00745   {
00746     /* Update the error code */
00747     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00748
00749     /* Return error status */
00750     status =  HAL_ERROR;
00751   }
00752
00753   /* Release Lock */
00754   __HAL_UNLOCK(hpcd);
00755
00756   return status;
00757 }
00758
00759 /**
00760   * @brief  UnRegister the USB PCD Iso IN incomplete Callback
00761   *         USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
00762   * @param  hpcd PCD handle
00763   * @retval HAL status
00764   */
00765 HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd)
00766 {
00767   HAL_StatusTypeDef status = HAL_OK;
00768
00769   /* Process locked */
00770   __HAL_LOCK(hpcd);
00771
00772   if (hpcd->State == HAL_PCD_STATE_READY)
00773   {
00774     hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; /* Legacy weak ISOINIncompleteCallback  */
00775   }
00776   else
00777   {
00778     /* Update the error code */
00779     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00780
00781     /* Return error status */
00782     status =  HAL_ERROR;
00783   }
00784
00785   /* Release Lock */
00786   __HAL_UNLOCK(hpcd);
00787
00788   return status;
00789 }
00790
00791 /**
00792   * @brief  Register USB PCD BCD Callback
00793   *         To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback
00794   * @param  hpcd PCD handle
00795   * @param  pCallback pointer to the USB PCD BCD Callback function
00796   * @retval HAL status
00797   */
00798 HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback)
00799 {
00800   HAL_StatusTypeDef status = HAL_OK;
00801
00802   if (pCallback == NULL)
00803   {
00804     /* Update the error code */
00805     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00806
00807     return HAL_ERROR;
00808   }
00809
00810   /* Process locked */
00811   __HAL_LOCK(hpcd);
00812
00813   if (hpcd->State == HAL_PCD_STATE_READY)
00814   {
00815     hpcd->BCDCallback = pCallback;
00816   }
00817   else
00818   {
00819     /* Update the error code */
00820     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00821
00822     /* Return error status */
00823     status =  HAL_ERROR;
00824   }
00825
00826   /* Release Lock */
00827   __HAL_UNLOCK(hpcd);
00828
00829   return status;
00830 }
00831
00832 /**
00833   * @brief  UnRegister the USB PCD BCD Callback
00834   *         USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback
00835   * @param  hpcd PCD handle
00836   * @retval HAL status
00837   */
00838 HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd)
00839 {
00840   HAL_StatusTypeDef status = HAL_OK;
00841
00842   /* Process locked */
00843   __HAL_LOCK(hpcd);
00844
00845   if (hpcd->State == HAL_PCD_STATE_READY)
00846   {
00847     hpcd->BCDCallback = HAL_PCDEx_BCD_Callback; /* Legacy weak HAL_PCDEx_BCD_Callback  */
00848   }
00849   else
00850   {
00851     /* Update the error code */
00852     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00853
00854     /* Return error status */
00855     status =  HAL_ERROR;
00856   }
00857
00858   /* Release Lock */
00859   __HAL_UNLOCK(hpcd);
00860
00861   return status;
00862 }
00863
00864 /**
00865   * @brief  Register USB PCD LPM Callback
00866   *         To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback
00867   * @param  hpcd PCD handle
00868   * @param  pCallback pointer to the USB PCD LPM Callback function
00869   * @retval HAL status
00870   */
00871 HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback)
00872 {
00873   HAL_StatusTypeDef status = HAL_OK;
00874
00875   if (pCallback == NULL)
00876   {
00877     /* Update the error code */
00878     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00879
00880     return HAL_ERROR;
00881   }
00882
00883   /* Process locked */
00884   __HAL_LOCK(hpcd);
00885
00886   if (hpcd->State == HAL_PCD_STATE_READY)
00887   {
00888     hpcd->LPMCallback = pCallback;
00889   }
00890   else
00891   {
00892     /* Update the error code */
00893     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00894
00895     /* Return error status */
00896     status =  HAL_ERROR;
00897   }
00898
00899   /* Release Lock */
00900   __HAL_UNLOCK(hpcd);
00901
00902   return status;
00903 }
00904
00905 /**
00906   * @brief  UnRegister the USB PCD LPM Callback
00907   *         USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback
00908   * @param  hpcd PCD handle
00909   * @retval HAL status
00910   */
00911 HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd)
00912 {
00913   HAL_StatusTypeDef status = HAL_OK;
00914
00915   /* Process locked */
00916   __HAL_LOCK(hpcd);
00917
00918   if (hpcd->State == HAL_PCD_STATE_READY)
00919   {
00920     hpcd->LPMCallback = HAL_PCDEx_LPM_Callback; /* Legacy weak HAL_PCDEx_LPM_Callback  */
00921   }
00922   else
00923   {
00924     /* Update the error code */
00925     hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
00926
00927     /* Return error status */
00928     status =  HAL_ERROR;
00929   }
00930
00931   /* Release Lock */
00932   __HAL_UNLOCK(hpcd);
00933
00934   return status;
00935 }
00936 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00937
00938 /**
00939   * @}
00940   */
00941
00942 /** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions
00943  *  @brief   Data transfers functions
00944  *
00945 @verbatim
00946  ===============================================================================
00947                       ##### IO operation functions #####
00948  ===============================================================================
00949     [..]
00950     This subsection provides a set of functions allowing to manage the PCD data
00951     transfers.
00952
00953 @endverbatim
00954   * @{
00955   */
00956
00957 /**
00958   * @brief  Start the USB device
00959   * @param  hpcd PCD handle
00960   * @retval HAL status
00961   */
00962 HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
00963 {
00964   __HAL_LOCK(hpcd);
00965   (void)USB_DevConnect(hpcd->Instance);
00966   __HAL_PCD_ENABLE(hpcd);
00967   __HAL_UNLOCK(hpcd);
00968   return HAL_OK;
00969 }
00970
00971 /**
00972   * @brief  Stop the USB device.
00973   * @param  hpcd PCD handle
00974   * @retval HAL status
00975   */
00976 HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
00977 {
00978   __HAL_LOCK(hpcd);
00979   __HAL_PCD_DISABLE(hpcd);
00980
00981   (void)USB_StopDevice(hpcd->Instance);
00982
00983   __HAL_UNLOCK(hpcd);
00984
00985   return HAL_OK;
00986 }
00987
00988
00989 /**
00990   * @brief  This function handles PCD interrupt request.
00991   * @param  hpcd PCD handle
00992   * @retval HAL status
00993   */
00994 void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
00995 {
00996   if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_CTR))
00997   {
00998     /* servicing of the endpoint correct transfer interrupt */
00999     /* clear of the CTR flag into the sub */
01000     (void)PCD_EP_ISR_Handler(hpcd);
01001   }
01002
01003   if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_RESET))
01004   {
01005     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
01006
01007 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01008     hpcd->ResetCallback(hpcd);
01009 #else
01010     HAL_PCD_ResetCallback(hpcd);
01011 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01012
01013     (void)HAL_PCD_SetAddress(hpcd, 0U);
01014   }
01015
01016   if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_PMAOVR))
01017   {
01018     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR);
01019   }
01020
01021   if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_ERR))
01022   {
01023     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR);
01024   }
01025
01026   if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_WKUP))
01027   {
01028     hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_LPMODE);
01029     hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);
01030
01031     if (hpcd->LPM_State == LPM_L1)
01032     {
01033       hpcd->LPM_State = LPM_L0;
01034 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01035       hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE);
01036 #else
01037       HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
01038 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01039     }
01040
01041 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01042     hpcd->ResumeCallback(hpcd);
01043 #else
01044     HAL_PCD_ResumeCallback(hpcd);
01045 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01046
01047     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);
01048   }
01049
01050   if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_SUSP))
01051   {
01052     /* Force low-power mode in the macrocell */
01053     hpcd->Instance->CNTR |= USB_CNTR_FSUSP;
01054
01055     /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
01056     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);
01057
01058     hpcd->Instance->CNTR |= USB_CNTR_LPMODE;
01059
01060     if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_WKUP) == 0U)
01061     {
01062 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01063       hpcd->SuspendCallback(hpcd);
01064 #else
01065       HAL_PCD_SuspendCallback(hpcd);
01066 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01067     }
01068   }
01069
01070   /* Handle LPM Interrupt */
01071   if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_L1REQ))
01072   {
01073     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_L1REQ);
01074     if (hpcd->LPM_State == LPM_L0)
01075     {
01076       /* Force suspend and low-power mode before going to L1 state*/
01077       hpcd->Instance->CNTR |= USB_CNTR_LPMODE;
01078       hpcd->Instance->CNTR |= USB_CNTR_FSUSP;
01079
01080       hpcd->LPM_State = LPM_L1;
01081       hpcd->BESL = ((uint32_t)hpcd->Instance->LPMCSR & USB_LPMCSR_BESL) >> 2;
01082 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01083       hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE);
01084 #else
01085       HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
01086 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01087     }
01088     else
01089     {
01090 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01091       hpcd->SuspendCallback(hpcd);
01092 #else
01093       HAL_PCD_SuspendCallback(hpcd);
01094 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01095     }
01096   }
01097
01098   if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_SOF))
01099   {
01100     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF);
01101
01102 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01103     hpcd->SOFCallback(hpcd);
01104 #else
01105     HAL_PCD_SOFCallback(hpcd);
01106 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01107   }
01108
01109   if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_ESOF))
01110   {
01111     /* clear ESOF flag in ISTR */
01112     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF);
01113   }
01114 }
01115
01116
01117 /**
01118   * @brief  Data OUT stage callback.
01119   * @param  hpcd PCD handle
01120   * @param  epnum endpoint number
01121   * @retval None
01122   */
01123 __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
01124 {
01125   /* Prevent unused argument(s) compilation warning */
01126   UNUSED(hpcd);
01127   UNUSED(epnum);
01128
01129   /* NOTE : This function should not be modified, when the callback is needed,
01130             the HAL_PCD_DataOutStageCallback could be implemented in the user file
01131    */
01132 }
01133
01134 /**
01135   * @brief  Data IN stage callback
01136   * @param  hpcd PCD handle
01137   * @param  epnum endpoint number
01138   * @retval None
01139   */
01140 __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
01141 {
01142   /* Prevent unused argument(s) compilation warning */
01143   UNUSED(hpcd);
01144   UNUSED(epnum);
01145
01146   /* NOTE : This function should not be modified, when the callback is needed,
01147             the HAL_PCD_DataInStageCallback could be implemented in the user file
01148    */
01149 }
01150 /**
01151   * @brief  Setup stage callback
01152   * @param  hpcd PCD handle
01153   * @retval None
01154   */
01155 __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
01156 {
01157   /* Prevent unused argument(s) compilation warning */
01158   UNUSED(hpcd);
01159
01160   /* NOTE : This function should not be modified, when the callback is needed,
01161             the HAL_PCD_SetupStageCallback could be implemented in the user file
01162    */
01163 }
01164
01165 /**
01166   * @brief  USB Start Of Frame callback.
01167   * @param  hpcd PCD handle
01168   * @retval None
01169   */
01170 __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
01171 {
01172   /* Prevent unused argument(s) compilation warning */
01173   UNUSED(hpcd);
01174
01175   /* NOTE : This function should not be modified, when the callback is needed,
01176             the HAL_PCD_SOFCallback could be implemented in the user file
01177    */
01178 }
01179
01180 /**
01181   * @brief  USB Reset callback.
01182   * @param  hpcd PCD handle
01183   * @retval None
01184   */
01185 __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
01186 {
01187   /* Prevent unused argument(s) compilation warning */
01188   UNUSED(hpcd);
01189
01190   /* NOTE : This function should not be modified, when the callback is needed,
01191             the HAL_PCD_ResetCallback could be implemented in the user file
01192    */
01193 }
01194
01195 /**
01196   * @brief  Suspend event callback.
01197   * @param  hpcd PCD handle
01198   * @retval None
01199   */
01200 __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
01201 {
01202   /* Prevent unused argument(s) compilation warning */
01203   UNUSED(hpcd);
01204
01205   /* NOTE : This function should not be modified, when the callback is needed,
01206             the HAL_PCD_SuspendCallback could be implemented in the user file
01207    */
01208 }
01209
01210 /**
01211   * @brief  Resume event callback.
01212   * @param  hpcd PCD handle
01213   * @retval None
01214   */
01215 __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
01216 {
01217   /* Prevent unused argument(s) compilation warning */
01218   UNUSED(hpcd);
01219
01220   /* NOTE : This function should not be modified, when the callback is needed,
01221             the HAL_PCD_ResumeCallback could be implemented in the user file
01222    */
01223 }
01224
01225 /**
01226   * @brief  Incomplete ISO OUT callback.
01227   * @param  hpcd PCD handle
01228   * @param  epnum endpoint number
01229   * @retval None
01230   */
01231 __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
01232 {
01233   /* Prevent unused argument(s) compilation warning */
01234   UNUSED(hpcd);
01235   UNUSED(epnum);
01236
01237   /* NOTE : This function should not be modified, when the callback is needed,
01238             the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
01239    */
01240 }
01241
01242 /**
01243   * @brief  Incomplete ISO IN callback.
01244   * @param  hpcd PCD handle
01245   * @param  epnum endpoint number
01246   * @retval None
01247   */
01248 __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
01249 {
01250   /* Prevent unused argument(s) compilation warning */
01251   UNUSED(hpcd);
01252   UNUSED(epnum);
01253
01254   /* NOTE : This function should not be modified, when the callback is needed,
01255             the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
01256    */
01257 }
01258
01259 /**
01260   * @brief  Connection event callback.
01261   * @param  hpcd PCD handle
01262   * @retval None
01263   */
01264 __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
01265 {
01266   /* Prevent unused argument(s) compilation warning */
01267   UNUSED(hpcd);
01268
01269   /* NOTE : This function should not be modified, when the callback is needed,
01270             the HAL_PCD_ConnectCallback could be implemented in the user file
01271    */
01272 }
01273
01274 /**
01275   * @brief  Disconnection event callback.
01276   * @param  hpcd PCD handle
01277   * @retval None
01278   */
01279 __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
01280 {
01281   /* Prevent unused argument(s) compilation warning */
01282   UNUSED(hpcd);
01283
01284   /* NOTE : This function should not be modified, when the callback is needed,
01285             the HAL_PCD_DisconnectCallback could be implemented in the user file
01286    */
01287 }
01288
01289 /**
01290   * @}
01291   */
01292
01293 /** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
01294  *  @brief   management functions
01295  *
01296 @verbatim
01297  ===============================================================================
01298                       ##### Peripheral Control functions #####
01299  ===============================================================================
01300     [..]
01301     This subsection provides a set of functions allowing to control the PCD data
01302     transfers.
01303
01304 @endverbatim
01305   * @{
01306   */
01307
01308 /**
01309   * @brief  Connect the USB device
01310   * @param  hpcd PCD handle
01311   * @retval HAL status
01312   */
01313 HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
01314 {
01315   __HAL_LOCK(hpcd);
01316   (void)USB_DevConnect(hpcd->Instance);
01317   __HAL_UNLOCK(hpcd);
01318   return HAL_OK;
01319 }
01320
01321 /**
01322   * @brief  Disconnect the USB device.
01323   * @param  hpcd PCD handle
01324   * @retval HAL status
01325   */
01326 HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
01327 {
01328   __HAL_LOCK(hpcd);
01329   (void)USB_DevDisconnect(hpcd->Instance);
01330   __HAL_UNLOCK(hpcd);
01331   return HAL_OK;
01332 }
01333
01334 /**
01335   * @brief  Set the USB Device address.
01336   * @param  hpcd PCD handle
01337   * @param  address new device address
01338   * @retval HAL status
01339   */
01340 HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
01341 {
01342   __HAL_LOCK(hpcd);
01343   hpcd->USB_Address = address;
01344   (void)USB_SetDevAddress(hpcd->Instance, address);
01345   __HAL_UNLOCK(hpcd);
01346   return HAL_OK;
01347 }
01348 /**
01349   * @brief  Open and configure an endpoint.
01350   * @param  hpcd PCD handle
01351   * @param  ep_addr endpoint address
01352   * @param  ep_mps endpoint max packet size
01353   * @param  ep_type endpoint type
01354   * @retval HAL status
01355   */
01356 HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
01357 {
01358   HAL_StatusTypeDef  ret = HAL_OK;
01359   PCD_EPTypeDef *ep;
01360
01361   if ((ep_addr & 0x80U) == 0x80U)
01362   {
01363     ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
01364     ep->is_in = 1U;
01365   }
01366   else
01367   {
01368     ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
01369     ep->is_in = 0U;
01370   }
01371
01372   ep->num = ep_addr & EP_ADDR_MSK;
01373   ep->maxpacket = ep_mps;
01374   ep->type = ep_type;
01375
01376   if (ep->is_in != 0U)
01377   {
01378     /* Assign a Tx FIFO */
01379     ep->tx_fifo_num = ep->num;
01380   }
01381   /* Set initial data PID. */
01382   if (ep_type == EP_TYPE_BULK)
01383   {
01384     ep->data_pid_start = 0U;
01385   }
01386
01387   __HAL_LOCK(hpcd);
01388   (void)USB_ActivateEndpoint(hpcd->Instance, ep);
01389   __HAL_UNLOCK(hpcd);
01390
01391   return ret;
01392 }
01393
01394 /**
01395   * @brief  Deactivate an endpoint.
01396   * @param  hpcd PCD handle
01397   * @param  ep_addr endpoint address
01398   * @retval HAL status
01399   */
01400 HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01401 {
01402   PCD_EPTypeDef *ep;
01403
01404   if ((ep_addr & 0x80U) == 0x80U)
01405   {
01406     ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
01407     ep->is_in = 1U;
01408   }
01409   else
01410   {
01411     ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
01412     ep->is_in = 0U;
01413   }
01414   ep->num   = ep_addr & EP_ADDR_MSK;
01415
01416   __HAL_LOCK(hpcd);
01417   (void)USB_DeactivateEndpoint(hpcd->Instance, ep);
01418   __HAL_UNLOCK(hpcd);
01419   return HAL_OK;
01420 }
01421
01422
01423 /**
01424   * @brief  Receive an amount of data.
01425   * @param  hpcd PCD handle
01426   * @param  ep_addr endpoint address
01427   * @param  pBuf pointer to the reception buffer
01428   * @param  len amount of data to be received
01429   * @retval HAL status
01430   */
01431 HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
01432 {
01433   PCD_EPTypeDef *ep;
01434
01435   ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
01436
01437   /*setup and start the Xfer */
01438   ep->xfer_buff = pBuf;
01439   ep->xfer_len = len;
01440   ep->xfer_count = 0U;
01441   ep->is_in = 0U;
01442   ep->num = ep_addr & EP_ADDR_MSK;
01443
01444   if ((ep_addr & EP_ADDR_MSK) == 0U)
01445   {
01446     (void)USB_EP0StartXfer(hpcd->Instance, ep);
01447   }
01448   else
01449   {
01450     (void)USB_EPStartXfer(hpcd->Instance, ep);
01451   }
01452
01453   return HAL_OK;
01454 }
01455
01456 /**
01457   * @brief  Get Received Data Size
01458   * @param  hpcd PCD handle
01459   * @param  ep_addr endpoint address
01460   * @retval Data Size
01461   */
01462 uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01463 {
01464   return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count;
01465 }
01466 /**
01467   * @brief  Send an amount of data
01468   * @param  hpcd PCD handle
01469   * @param  ep_addr endpoint address
01470   * @param  pBuf pointer to the transmission buffer
01471   * @param  len amount of data to be sent
01472   * @retval HAL status
01473   */
01474 HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
01475 {
01476   PCD_EPTypeDef *ep;
01477
01478   ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
01479
01480   /*setup and start the Xfer */
01481   ep->xfer_buff = pBuf;
01482   ep->xfer_len = len;
01483   ep->xfer_count = 0U;
01484   ep->is_in = 1U;
01485   ep->num = ep_addr & EP_ADDR_MSK;
01486
01487   if ((ep_addr & EP_ADDR_MSK) == 0U)
01488   {
01489     (void)USB_EP0StartXfer(hpcd->Instance, ep);
01490   }
01491   else
01492   {
01493     (void)USB_EPStartXfer(hpcd->Instance, ep);
01494   }
01495
01496   return HAL_OK;
01497 }
01498
01499 /**
01500   * @brief  Set a STALL condition over an endpoint
01501   * @param  hpcd PCD handle
01502   * @param  ep_addr endpoint address
01503   * @retval HAL status
01504   */
01505 HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01506 {
01507   PCD_EPTypeDef *ep;
01508
01509   if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints)
01510   {
01511     return HAL_ERROR;
01512   }
01513
01514   if ((0x80U & ep_addr) == 0x80U)
01515   {
01516     ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
01517     ep->is_in = 1U;
01518   }
01519   else
01520   {
01521     ep = &hpcd->OUT_ep[ep_addr];
01522     ep->is_in = 0U;
01523   }
01524
01525   ep->is_stall = 1U;
01526   ep->num = ep_addr & EP_ADDR_MSK;
01527
01528   __HAL_LOCK(hpcd);
01529
01530   (void)USB_EPSetStall(hpcd->Instance, ep);
01531   if ((ep_addr & EP_ADDR_MSK) == 0U)
01532   {
01533     (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup);
01534   }
01535   __HAL_UNLOCK(hpcd);
01536
01537   return HAL_OK;
01538 }
01539
01540 /**
01541   * @brief  Clear a STALL condition over in an endpoint
01542   * @param  hpcd PCD handle
01543   * @param  ep_addr endpoint address
01544   * @retval HAL status
01545   */
01546 HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01547 {
01548   PCD_EPTypeDef *ep;
01549
01550   if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints)
01551   {
01552     return HAL_ERROR;
01553   }
01554
01555   if ((0x80U & ep_addr) == 0x80U)
01556   {
01557     ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
01558     ep->is_in = 1U;
01559   }
01560   else
01561   {
01562     ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
01563     ep->is_in = 0U;
01564   }
01565
01566   ep->is_stall = 0U;
01567   ep->num = ep_addr & EP_ADDR_MSK;
01568
01569   __HAL_LOCK(hpcd);
01570   (void)USB_EPClearStall(hpcd->Instance, ep);
01571   __HAL_UNLOCK(hpcd);
01572
01573   return HAL_OK;
01574 }
01575
01576 /**
01577   * @brief  Flush an endpoint
01578   * @param  hpcd PCD handle
01579   * @param  ep_addr endpoint address
01580   * @retval HAL status
01581   */
01582 HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01583 {
01584   /* Prevent unused argument(s) compilation warning */
01585   UNUSED(hpcd);
01586   UNUSED(ep_addr);
01587
01588   return HAL_OK;
01589 }
01590
01591 /**
01592   * @brief  Activate remote wakeup signalling
01593   * @param  hpcd PCD handle
01594   * @retval HAL status
01595   */
01596 HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
01597 {
01598   return (USB_ActivateRemoteWakeup(hpcd->Instance));
01599 }
01600
01601 /**
01602   * @brief  De-activate remote wakeup signalling.
01603   * @param  hpcd PCD handle
01604   * @retval HAL status
01605   */
01606 HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
01607 {
01608   return (USB_DeActivateRemoteWakeup(hpcd->Instance));
01609 }
01610
01611 /**
01612   * @}
01613   */
01614
01615 /** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
01616  *  @brief   Peripheral State functions
01617  *
01618 @verbatim
01619  ===============================================================================
01620                       ##### Peripheral State functions #####
01621  ===============================================================================
01622     [..]
01623     This subsection permits to get in run-time the status of the peripheral
01624     and the data flow.
01625
01626 @endverbatim
01627   * @{
01628   */
01629
01630 /**
01631   * @brief  Return the PCD handle state.
01632   * @param  hpcd PCD handle
01633   * @retval HAL state
01634   */
01635 PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
01636 {
01637   return hpcd->State;
01638 }
01639
01640 /**
01641   * @}
01642   */
01643
01644 /**
01645   * @}
01646   */
01647
01648 /* Private functions ---------------------------------------------------------*/
01649 /** @addtogroup PCD_Private_Functions
01650   * @{
01651   */
01652
01653
01654 /**
01655   * @brief  This function handles PCD Endpoint interrupt request.
01656   * @param  hpcd PCD handle
01657   * @retval HAL status
01658   */
01659 static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
01660 {
01661   PCD_EPTypeDef *ep;
01662   uint16_t count;
01663   uint16_t wIstr;
01664   uint16_t wEPVal;
01665   uint8_t epindex;
01666
01667   /* stay in loop while pending interrupts */
01668   while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U)
01669   {
01670     wIstr = hpcd->Instance->ISTR;
01671     /* extract highest priority endpoint number */
01672     epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
01673
01674     if (epindex == 0U)
01675     {
01676       /* Decode and service control endpoint interrupt */
01677
01678       /* DIR bit = origin of the interrupt */
01679       if ((wIstr & USB_ISTR_DIR) == 0U)
01680       {
01681         /* DIR = 0 */
01682
01683         /* DIR = 0      => IN  int */
01684         /* DIR = 0 implies that (EP_CTR_TX = 1) always  */
01685         PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0);
01686         ep = &hpcd->IN_ep[0];
01687
01688         ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
01689         ep->xfer_buff += ep->xfer_count;
01690
01691         /* TX COMPLETE */
01692 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01693         hpcd->DataInStageCallback(hpcd, 0U);
01694 #else
01695         HAL_PCD_DataInStageCallback(hpcd, 0U);
01696 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01697
01698         if ((hpcd->USB_Address > 0U) && (ep->xfer_len == 0U))
01699         {
01700           hpcd->Instance->DADDR = ((uint16_t)hpcd->USB_Address | USB_DADDR_EF);
01701           hpcd->USB_Address = 0U;
01702         }
01703       }
01704       else
01705       {
01706         /* DIR = 1 */
01707
01708         /* DIR = 1 & CTR_RX       => SETUP or OUT int */
01709         /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
01710         ep = &hpcd->OUT_ep[0];
01711         wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
01712
01713         if ((wEPVal & USB_EP_SETUP) != 0U)
01714         {
01715           /* Get SETUP Packet*/
01716           ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
01717
01718           USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup,
01719                       ep->pmaadress, (uint16_t)ep->xfer_count);
01720
01721           /* SETUP bit kept frozen while CTR_RX = 1*/
01722           PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
01723
01724           /* Process SETUP Packet*/
01725 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01726           hpcd->SetupStageCallback(hpcd);
01727 #else
01728           HAL_PCD_SetupStageCallback(hpcd);
01729 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01730         }
01731
01732         else if ((wEPVal & USB_EP_CTR_RX) != 0U)
01733         {
01734           PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
01735
01736           /* Get Control Data OUT Packet*/
01737           ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
01738
01739           if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U))
01740           {
01741             USB_ReadPMA(hpcd->Instance, ep->xfer_buff,
01742                         ep->pmaadress, (uint16_t)ep->xfer_count);
01743
01744             ep->xfer_buff += ep->xfer_count;
01745
01746             /* Process Control Data OUT Packet*/
01747 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01748             hpcd->DataOutStageCallback(hpcd, 0U);
01749 #else
01750             HAL_PCD_DataOutStageCallback(hpcd, 0U);
01751 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01752           }
01753
01754           PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
01755           PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
01756         }
01757       }
01758     }
01759     else
01760     {
01761       /* Decode and service non control endpoints interrupt  */
01762
01763       /* process related endpoint register */
01764       wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex);
01765       if ((wEPVal & USB_EP_CTR_RX) != 0U)
01766       {
01767         /* clear int flag */
01768         PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex);
01769         ep = &hpcd->OUT_ep[epindex];
01770
01771         /* OUT double Buffering*/
01772         if (ep->doublebuffer == 0U)
01773         {
01774           count = (uint16_t)PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
01775           if (count != 0U)
01776           {
01777             USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
01778           }
01779         }
01780         else
01781         {
01782           if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U)
01783           {
01784             /*read from endpoint BUF0Addr buffer*/
01785             count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
01786             if (count != 0U)
01787             {
01788               USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
01789             }
01790           }
01791           else
01792           {
01793             /*read from endpoint BUF1Addr buffer*/
01794             count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
01795             if (count != 0U)
01796             {
01797               USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
01798             }
01799           }
01800           /* free EP OUT Buffer */
01801           PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U);
01802         }
01803         /*multi-packet on the NON control OUT endpoint*/
01804         ep->xfer_count += count;
01805         ep->xfer_buff += count;
01806
01807         if ((ep->xfer_len == 0U) || (count < ep->maxpacket))
01808         {
01809           /* RX COMPLETE */
01810 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01811           hpcd->DataOutStageCallback(hpcd, ep->num);
01812 #else
01813           HAL_PCD_DataOutStageCallback(hpcd, ep->num);
01814 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01815         }
01816         else
01817         {
01818           (void)HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
01819         }
01820
01821       } /* if((wEPVal & EP_CTR_RX) */
01822
01823       if ((wEPVal & USB_EP_CTR_TX) != 0U)
01824       {
01825         ep = &hpcd->IN_ep[epindex];
01826
01827         /* clear int flag */
01828         PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex);
01829
01830         /*multi-packet on the NON control IN endpoint*/
01831         ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
01832         ep->xfer_buff += ep->xfer_count;
01833
01834         /* Zero Length Packet? */
01835         if (ep->xfer_len == 0U)
01836         {
01837           /* TX COMPLETE */
01838 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
01839           hpcd->DataInStageCallback(hpcd, ep->num);
01840 #else
01841           HAL_PCD_DataInStageCallback(hpcd, ep->num);
01842 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
01843         }
01844         else
01845         {
01846           (void)HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
01847         }
01848       }
01849     }
01850   }
01851   return HAL_OK;
01852 }
01853
01854
01855 /**
01856   * @}
01857   */
01858 #endif /* defined (USB) */
01859 #endif /* HAL_PCD_MODULE_ENABLED */
01860
01861 /**
01862   * @}
01863   */
01864
01865 /**
01866   * @}
01867   */
01868
01869 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_pcd.h Source File

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stm32wbxx_hal_pcd.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_pcd.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of PCD HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_PCD_H
00022 #define STM32WBxx_HAL_PCD_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_ll_usb.h"
00030
00031 #if defined (USB)
00032
00033 /** @addtogroup STM32WBxx_HAL_Driver
00034   * @{
00035   */
00036
00037 /** @addtogroup PCD
00038   * @{
00039   */
00040
00041 /* Exported types ------------------------------------------------------------*/
00042 /** @defgroup PCD_Exported_Types PCD Exported Types
00043   * @{
00044   */
00045
00046 /**
00047   * @brief  PCD State structure definition
00048   */
00049 typedef enum
00050 {
00051   HAL_PCD_STATE_RESET   = 0x00,
00052   HAL_PCD_STATE_READY   = 0x01,
00053   HAL_PCD_STATE_ERROR   = 0x02,
00054   HAL_PCD_STATE_BUSY    = 0x03,
00055   HAL_PCD_STATE_TIMEOUT = 0x04
00056 } PCD_StateTypeDef;
00057
00058 /* Device LPM suspend state */
00059 typedef enum
00060 {
00061   LPM_L0 = 0x00, /* on */
00062   LPM_L1 = 0x01, /* LPM L1 sleep */
00063   LPM_L2 = 0x02, /* suspend */
00064   LPM_L3 = 0x03, /* off */
00065 } PCD_LPM_StateTypeDef;
00066
00067 typedef enum
00068 {
00069   PCD_LPM_L0_ACTIVE = 0x00, /* on */
00070   PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
00071 } PCD_LPM_MsgTypeDef;
00072
00073 typedef enum
00074 {
00075   PCD_BCD_ERROR                     = 0xFF,
00076   PCD_BCD_CONTACT_DETECTION         = 0xFE,
00077   PCD_BCD_STD_DOWNSTREAM_PORT       = 0xFD,
00078   PCD_BCD_CHARGING_DOWNSTREAM_PORT  = 0xFC,
00079   PCD_BCD_DEDICATED_CHARGING_PORT   = 0xFB,
00080   PCD_BCD_DISCOVERY_COMPLETED       = 0x00,
00081
00082 } PCD_BCD_MsgTypeDef;
00083
00084
00085
00086
00087
00088 typedef USB_TypeDef        PCD_TypeDef;
00089 typedef USB_CfgTypeDef     PCD_InitTypeDef;
00090 typedef USB_EPTypeDef      PCD_EPTypeDef;
00091
00092
00093 /**
00094   * @brief  PCD Handle Structure definition
00095   */
00096 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00097 typedef struct __PCD_HandleTypeDef
00098 #else
00099 typedef struct
00100 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00101 {
00102   PCD_TypeDef             *Instance;   /*!< Register base address              */
00103   PCD_InitTypeDef         Init;        /*!< PCD required parameters            */
00104   __IO uint8_t            USB_Address; /*!< USB Address                        */
00105   PCD_EPTypeDef           IN_ep[8];   /*!< IN endpoint parameters             */
00106   PCD_EPTypeDef           OUT_ep[8];  /*!< OUT endpoint parameters            */
00107   HAL_LockTypeDef         Lock;        /*!< PCD peripheral status              */
00108   __IO PCD_StateTypeDef   State;       /*!< PCD communication state            */
00109   __IO  uint32_t          ErrorCode;   /*!< PCD Error code                     */
00110   uint32_t                Setup[12];   /*!< Setup packet buffer                */
00111   PCD_LPM_StateTypeDef    LPM_State;   /*!< LPM State                          */
00112   uint32_t                BESL;
00113
00114
00115   uint32_t lpm_active;                 /*!< Enable or disable the Link Power Management .
00116                                        This parameter can be set to ENABLE or DISABLE        */
00117
00118   uint32_t battery_charging_active;    /*!< Enable or disable Battery charging.
00119                                        This parameter can be set to ENABLE or DISABLE        */
00120   void                    *pData;      /*!< Pointer to upper stack Handler */
00121
00122 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00123   void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd);                              /*!< USB OTG PCD SOF callback                */
00124   void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd);                       /*!< USB OTG PCD Setup Stage callback        */
00125   void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd);                            /*!< USB OTG PCD Reset callback              */
00126   void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Suspend callback            */
00127   void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd);                           /*!< USB OTG PCD Resume callback             */
00128   void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Connect callback            */
00129   void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd);                       /*!< USB OTG PCD Disconnect callback         */
00130
00131   void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);      /*!< USB OTG PCD Data OUT Stage callback     */
00132   void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);       /*!< USB OTG PCD Data IN Stage callback      */
00133   void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);  /*!< USB OTG PCD ISO OUT Incomplete callback */
00134   void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);   /*!< USB OTG PCD ISO IN Incomplete callback  */
00135   void (* BCDCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);      /*!< USB OTG PCD BCD callback                */
00136   void (* LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);      /*!< USB OTG PCD LPM callback                */
00137
00138   void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Msp Init callback           */
00139   void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd);                        /*!< USB OTG PCD Msp DeInit callback         */
00140 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00141 } PCD_HandleTypeDef;
00142
00143 /**
00144   * @}
00145   */
00146
00147 /* Include PCD HAL Extended module */
00148 #include "stm32wbxx_hal_pcd_ex.h"
00149
00150 /* Exported constants --------------------------------------------------------*/
00151 /** @defgroup PCD_Exported_Constants PCD Exported Constants
00152   * @{
00153   */
00154
00155 /** @defgroup PCD_Speed PCD Speed
00156   * @{
00157   */
00158 #define PCD_SPEED_FULL               USBD_FS_SPEED
00159 /**
00160   * @}
00161   */
00162
00163 /** @defgroup PCD_PHY_Module PCD PHY Module
00164   * @{
00165   */
00166 #define PCD_PHY_ULPI                 1U
00167 #define PCD_PHY_EMBEDDED             2U
00168 #define PCD_PHY_UTMI                 3U
00169 /**
00170   * @}
00171   */
00172
00173 /** @defgroup PCD_Error_Code_definition PCD Error Code definition
00174   * @brief  PCD Error Code definition
00175   * @{
00176   */
00177 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00178 #define  HAL_PCD_ERROR_INVALID_CALLBACK                        (0x00000010U)    /*!< Invalid Callback error  */
00179 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00180
00181 /**
00182   * @}
00183   */
00184
00185 /**
00186   * @}
00187   */
00188
00189 /* Exported macros -----------------------------------------------------------*/
00190 /** @defgroup PCD_Exported_Macros PCD Exported Macros
00191  *  @brief macros to handle interrupts and specific clock configurations
00192  * @{
00193  */
00194
00195
00196 #define __HAL_PCD_ENABLE(__HANDLE__)                                  (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
00197 #define __HAL_PCD_DISABLE(__HANDLE__)                                 (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
00198 #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)                 ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
00199 #define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)               (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))
00200
00201 #define __HAL_USB_WAKEUP_EXTI_ENABLE_IT()                             EXTI->IMR1 |= USB_WAKEUP_EXTI_LINE
00202 #define __HAL_USB_WAKEUP_EXTI_DISABLE_IT()                            EXTI->IMR1 &= ~(USB_WAKEUP_EXTI_LINE)
00203
00204
00205 /**
00206   * @}
00207   */
00208
00209 /* Exported functions --------------------------------------------------------*/
00210 /** @addtogroup PCD_Exported_Functions PCD Exported Functions
00211   * @{
00212   */
00213
00214 /* Initialization/de-initialization functions  ********************************/
00215 /** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
00216   * @{
00217   */
00218 HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
00219 HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);
00220 void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
00221 void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
00222
00223 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00224 /** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition
00225   * @brief  HAL USB OTG PCD Callback ID enumeration definition
00226   * @{
00227   */
00228 typedef enum
00229 {
00230   HAL_PCD_SOF_CB_ID          = 0x01,      /*!< USB PCD SOF callback ID          */
00231   HAL_PCD_SETUPSTAGE_CB_ID   = 0x02,      /*!< USB PCD Setup Stage callback ID  */
00232   HAL_PCD_RESET_CB_ID        = 0x03,      /*!< USB PCD Reset callback ID        */
00233   HAL_PCD_SUSPEND_CB_ID      = 0x04,      /*!< USB PCD Suspend callback ID      */
00234   HAL_PCD_RESUME_CB_ID       = 0x05,      /*!< USB PCD Resume callback ID       */
00235   HAL_PCD_CONNECT_CB_ID      = 0x06,      /*!< USB PCD Connect callback ID      */
00236   HAL_PCD_DISCONNECT_CB_ID  = 0x07,      /*!< USB PCD Disconnect callback ID   */
00237
00238   HAL_PCD_MSPINIT_CB_ID      = 0x08,      /*!< USB PCD MspInit callback ID      */
00239   HAL_PCD_MSPDEINIT_CB_ID    = 0x09       /*!< USB PCD MspDeInit callback ID    */
00240
00241 } HAL_PCD_CallbackIDTypeDef;
00242 /**
00243   * @}
00244   */
00245
00246 /** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition
00247   * @brief  HAL USB OTG PCD Callback pointer definition
00248   * @{
00249   */
00250
00251 typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd);                                   /*!< pointer to a common USB OTG PCD callback function  */
00252 typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);        /*!< pointer to USB OTG PCD Data OUT Stage callback     */
00253 typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);         /*!< pointer to USB OTG PCD Data IN Stage callback      */
00254 typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);        /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */
00255 typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);         /*!< pointer to USB OTG PCD ISO IN Incomplete callback  */
00256 typedef void (*pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);        /*!< pointer to USB OTG PCD LPM callback                */
00257 typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);        /*!< pointer to USB OTG PCD BCD callback                */
00258
00259 /**
00260   * @}
00261   */
00262
00263 HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback);
00264 HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);
00265
00266 HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback);
00267 HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);
00268
00269 HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback);
00270 HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);
00271
00272 HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback);
00273 HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);
00274
00275 HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback);
00276 HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
00277
00278 HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback);
00279 HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd);
00280
00281 HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback);
00282 HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);
00283 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00284 /**
00285   * @}
00286   */
00287
00288 /* I/O operation functions  ***************************************************/
00289 /* Non-Blocking mode: Interrupt */
00290 /** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
00291   * @{
00292   */
00293 HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
00294 HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
00295 void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
00296
00297 void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
00298 void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
00299 void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
00300 void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
00301 void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
00302 void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
00303 void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
00304
00305 void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00306 void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00307 void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00308 void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00309 /**
00310   * @}
00311   */
00312
00313 /* Peripheral Control functions  **********************************************/
00314 /** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
00315   * @{
00316   */
00317 HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
00318 HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
00319 HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
00320 HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
00321 HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00322 HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
00323 HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
00324 uint32_t          HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00325 HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00326 HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00327 HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00328 HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
00329 HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
00330 /**
00331   * @}
00332   */
00333
00334 /* Peripheral State functions  ************************************************/
00335 /** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
00336   * @{
00337   */
00338 PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
00339 /**
00340   * @}
00341   */
00342
00343 /**
00344   * @}
00345   */
00346
00347 /* Private constants ---------------------------------------------------------*/
00348 /** @defgroup PCD_Private_Constants PCD Private Constants
00349   * @{
00350   */
00351 /** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
00352   * @{
00353   */
00354
00355
00356 #define  USB_WAKEUP_EXTI_LINE                                         (0x1U << 28)  /*!< USB FS EXTI Line WakeUp Interrupt */
00357
00358
00359 /**
00360   * @}
00361   */
00362
00363 /** @defgroup PCD_EP0_MPS PCD EP0 MPS
00364   * @{
00365   */
00366 #define PCD_EP0MPS_64                                                 DEP0CTL_MPS_64
00367 #define PCD_EP0MPS_32                                                 DEP0CTL_MPS_32
00368 #define PCD_EP0MPS_16                                                 DEP0CTL_MPS_16
00369 #define PCD_EP0MPS_08                                                 DEP0CTL_MPS_8
00370 /**
00371   * @}
00372   */
00373
00374 /** @defgroup PCD_ENDP PCD ENDP
00375   * @{
00376   */
00377 #define PCD_ENDP0                                                     0U
00378 #define PCD_ENDP1                                                     1U
00379 #define PCD_ENDP2                                                     2U
00380 #define PCD_ENDP3                                                     3U
00381 #define PCD_ENDP4                                                     4U
00382 #define PCD_ENDP5                                                     5U
00383 #define PCD_ENDP6                                                     6U
00384 #define PCD_ENDP7                                                     7U
00385 /**
00386   * @}
00387   */
00388
00389 /** @defgroup PCD_ENDP_Kind PCD Endpoint Kind
00390   * @{
00391   */
00392 #define PCD_SNG_BUF                                                   0U
00393 #define PCD_DBL_BUF                                                   1U
00394 /**
00395   * @}
00396   */
00397
00398 /**
00399   * @}
00400   */
00401
00402 /* Private macros ------------------------------------------------------------*/
00403 /** @defgroup PCD_Private_Macros PCD Private Macros
00404  * @{
00405  */
00406
00407 /********************  Bit definition for USB_COUNTn_RX register  *************/
00408 #define USB_CNTRX_NBLK_MSK                    (0x1FU << 10)
00409 #define USB_CNTRX_BLSIZE                      (0x1U << 15)
00410
00411 /* SetENDPOINT */
00412 #define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue)  (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue))
00413
00414 /* GetENDPOINT */
00415 #define PCD_GET_ENDPOINT(USBx, bEpNum)            (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))
00416
00417 /* ENDPOINT transfer */
00418 #define USB_EP0StartXfer                          USB_EPStartXfer
00419
00420 /**
00421   * @brief  sets the type in the endpoint register(bits EP_TYPE[1:0])
00422   * @param  USBx USB peripheral instance register address.
00423   * @param  bEpNum Endpoint Number.
00424   * @param  wType Endpoint Type.
00425   * @retval None
00426   */
00427 #define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
00428                                              ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))
00429
00430 /**
00431   * @brief  gets the type in the endpoint register(bits EP_TYPE[1:0])
00432   * @param  USBx USB peripheral instance register address.
00433   * @param  bEpNum Endpoint Number.
00434   * @retval Endpoint Type
00435   */
00436 #define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)
00437
00438 /**
00439   * @brief free buffer used from the application realizing it to the line
00440   *         toggles bit SW_BUF in the double buffered endpoint register
00441   * @param USBx USB device.
00442   * @param   bEpNum, bDir
00443   * @retval None
00444   */
00445 #define PCD_FreeUserBuffer(USBx, bEpNum, bDir) do { \
00446   if ((bDir) == 0U) \
00447   { \
00448     /* OUT double buffered endpoint */ \
00449     PCD_TX_DTOG((USBx), (bEpNum)); \
00450   } \
00451   else if ((bDir) == 1U) \
00452   { \
00453     /* IN double buffered endpoint */ \
00454     PCD_RX_DTOG((USBx), (bEpNum)); \
00455   } \
00456 } while(0)
00457
00458 /**
00459   * @brief  sets the status for tx transfer (bits STAT_TX[1:0]).
00460   * @param  USBx USB peripheral instance register address.
00461   * @param  bEpNum Endpoint Number.
00462   * @param  wState new state
00463   * @retval None
00464   */
00465 #define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) do { \
00466    register uint16_t _wRegVal; \
00467    \
00468     _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \
00469    /* toggle first bit ? */ \
00470    if ((USB_EPTX_DTOG1 & (wState))!= 0U) \
00471    { \
00472       _wRegVal ^= USB_EPTX_DTOG1; \
00473    } \
00474    /* toggle second bit ?  */ \
00475    if ((USB_EPTX_DTOG2 & (wState))!= 0U) \
00476    { \
00477       _wRegVal ^= USB_EPTX_DTOG2; \
00478    } \
00479    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
00480   } while(0) /* PCD_SET_EP_TX_STATUS */
00481
00482 /**
00483   * @brief  sets the status for rx transfer (bits STAT_TX[1:0])
00484   * @param  USBx USB peripheral instance register address.
00485   * @param  bEpNum Endpoint Number.
00486   * @param  wState new state
00487   * @retval None
00488   */
00489 #define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) do { \
00490     register uint16_t _wRegVal; \
00491     \
00492     _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \
00493     /* toggle first bit ? */ \
00494     if ((USB_EPRX_DTOG1 & (wState))!= 0U) \
00495     { \
00496        _wRegVal ^= USB_EPRX_DTOG1; \
00497     } \
00498     /* toggle second bit ? */ \
00499     if ((USB_EPRX_DTOG2 & (wState))!= 0U) \
00500     { \
00501        _wRegVal ^= USB_EPRX_DTOG2; \
00502     } \
00503     PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
00504   } while(0) /* PCD_SET_EP_RX_STATUS */
00505
00506 /**
00507   * @brief  sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
00508   * @param  USBx USB peripheral instance register address.
00509   * @param  bEpNum Endpoint Number.
00510   * @param  wStaterx new state.
00511   * @param  wStatetx new state.
00512   * @retval None
00513   */
00514 #define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) do { \
00515     register uint16_t _wRegVal; \
00516     \
00517     _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \
00518     /* toggle first bit ? */ \
00519     if ((USB_EPRX_DTOG1 & (wStaterx))!= 0U) \
00520     { \
00521       _wRegVal ^= USB_EPRX_DTOG1; \
00522     } \
00523     /* toggle second bit ? */ \
00524     if ((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \
00525     { \
00526       _wRegVal ^= USB_EPRX_DTOG2; \
00527     } \
00528     /* toggle first bit ? */ \
00529     if ((USB_EPTX_DTOG1 & (wStatetx))!= 0U) \
00530     { \
00531       _wRegVal ^= USB_EPTX_DTOG1; \
00532     } \
00533     /* toggle second bit ?  */ \
00534     if ((USB_EPTX_DTOG2 & (wStatetx))!= 0U) \
00535     { \
00536       _wRegVal ^= USB_EPTX_DTOG2; \
00537     } \
00538     \
00539     PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
00540   } while(0) /* PCD_SET_EP_TXRX_STATUS */
00541
00542 /**
00543   * @brief  gets the status for tx/rx transfer (bits STAT_TX[1:0]
00544   *         /STAT_RX[1:0])
00545   * @param  USBx USB peripheral instance register address.
00546   * @param  bEpNum Endpoint Number.
00547   * @retval status
00548   */
00549 #define PCD_GET_EP_TX_STATUS(USBx, bEpNum)     ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)
00550 #define PCD_GET_EP_RX_STATUS(USBx, bEpNum)     ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)
00551
00552 /**
00553   * @brief  sets directly the VALID tx/rx-status into the endpoint register
00554   * @param  USBx USB peripheral instance register address.
00555   * @param  bEpNum Endpoint Number.
00556   * @retval None
00557   */
00558 #define PCD_SET_EP_TX_VALID(USBx, bEpNum)      (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
00559 #define PCD_SET_EP_RX_VALID(USBx, bEpNum)      (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
00560
00561 /**
00562   * @brief  checks stall condition in an endpoint.
00563   * @param  USBx USB peripheral instance register address.
00564   * @param  bEpNum Endpoint Number.
00565   * @retval TRUE = endpoint in stall condition.
00566   */
00567 #define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \
00568                                    == USB_EP_TX_STALL)
00569 #define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \
00570                                    == USB_EP_RX_STALL)
00571
00572 /**
00573   * @brief  set & clear EP_KIND bit.
00574   * @param  USBx USB peripheral instance register address.
00575   * @param  bEpNum Endpoint Number.
00576   * @retval None
00577   */
00578 #define PCD_SET_EP_KIND(USBx, bEpNum) do { \
00579     register uint16_t _wRegVal; \
00580     \
00581     _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
00582     \
00583     PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_KIND)); \
00584   } while(0) /* PCD_SET_EP_KIND */
00585
00586 #define PCD_CLEAR_EP_KIND(USBx, bEpNum) do { \
00587     register uint16_t _wRegVal; \
00588     \
00589     _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \
00590     \
00591     PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
00592   } while(0) /* PCD_CLEAR_EP_KIND */
00593
00594 /**
00595   * @brief  Sets/clears directly STATUS_OUT bit in the endpoint register.
00596   * @param  USBx USB peripheral instance register address.
00597   * @param  bEpNum Endpoint Number.
00598   * @retval None
00599   */
00600 #define PCD_SET_OUT_STATUS(USBx, bEpNum)       PCD_SET_EP_KIND((USBx), (bEpNum))
00601 #define PCD_CLEAR_OUT_STATUS(USBx, bEpNum)     PCD_CLEAR_EP_KIND((USBx), (bEpNum))
00602
00603 /**
00604   * @brief  Sets/clears directly EP_KIND bit in the endpoint register.
00605   * @param  USBx USB peripheral instance register address.
00606   * @param  bEpNum Endpoint Number.
00607   * @retval None
00608   */
00609 #define PCD_SET_EP_DBUF(USBx, bEpNum)          PCD_SET_EP_KIND((USBx), (bEpNum))
00610 #define PCD_CLEAR_EP_DBUF(USBx, bEpNum)        PCD_CLEAR_EP_KIND((USBx), (bEpNum))
00611
00612 /**
00613   * @brief  Clears bit CTR_RX / CTR_TX in the endpoint register.
00614   * @param  USBx USB peripheral instance register address.
00615   * @param  bEpNum Endpoint Number.
00616   * @retval None
00617   */
00618 #define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) do { \
00619     register uint16_t _wRegVal; \
00620     \
00621     _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \
00622     \
00623     PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_TX)); \
00624   } while(0) /* PCD_CLEAR_RX_EP_CTR */
00625
00626 #define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) do { \
00627     register uint16_t _wRegVal; \
00628     \
00629     _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \
00630     \
00631     PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX)); \
00632   } while(0) /* PCD_CLEAR_TX_EP_CTR */
00633
00634 /**
00635   * @brief  Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
00636   * @param  USBx USB peripheral instance register address.
00637   * @param  bEpNum Endpoint Number.
00638   * @retval None
00639   */
00640 #define PCD_RX_DTOG(USBx, bEpNum) do { \
00641     register uint16_t _wEPVal; \
00642     \
00643     _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
00644     \
00645     PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_RX)); \
00646   } while(0) /* PCD_RX_DTOG */
00647
00648 #define PCD_TX_DTOG(USBx, bEpNum) do { \
00649     register uint16_t _wEPVal; \
00650     \
00651     _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
00652     \
00653     PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_TX)); \
00654   } while(0) /* PCD_TX_DTOG */
00655 /**
00656   * @brief  Clears DTOG_RX / DTOG_TX bit in the endpoint register.
00657   * @param  USBx USB peripheral instance register address.
00658   * @param  bEpNum Endpoint Number.
00659   * @retval None
00660   */
00661 #define PCD_CLEAR_RX_DTOG(USBx, bEpNum) do { \
00662     register uint16_t _wRegVal; \
00663     \
00664     _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
00665     \
00666     if ((_wRegVal & USB_EP_DTOG_RX) != 0U)\
00667     { \
00668       PCD_RX_DTOG((USBx), (bEpNum)); \
00669     } \
00670   } while(0) /* PCD_CLEAR_RX_DTOG */
00671
00672 #define PCD_CLEAR_TX_DTOG(USBx, bEpNum) do { \
00673     register uint16_t _wRegVal; \
00674     \
00675     _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
00676     \
00677     if ((_wRegVal & USB_EP_DTOG_TX) != 0U)\
00678     { \
00679       PCD_TX_DTOG((USBx), (bEpNum)); \
00680     } \
00681   } while(0) /* PCD_CLEAR_TX_DTOG */
00682
00683 /**
00684   * @brief  Sets address in an endpoint register.
00685   * @param  USBx USB peripheral instance register address.
00686   * @param  bEpNum Endpoint Number.
00687   * @param  bAddr Address.
00688   * @retval None
00689   */
00690 #define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) do { \
00691     register uint16_t _wRegVal; \
00692     \
00693     _wRegVal = (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \
00694     \
00695     PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
00696   } while(0) /* PCD_SET_EP_ADDRESS */
00697
00698 /**
00699   * @brief  Gets address in an endpoint register.
00700   * @param  USBx USB peripheral instance register address.
00701   * @param  bEpNum Endpoint Number.
00702   * @retval None
00703   */
00704 #define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
00705
00706 #define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
00707 #define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
00708
00709 /**
00710   * @brief  sets address of the tx/rx buffer.
00711   * @param  USBx USB peripheral instance register address.
00712   * @param  bEpNum Endpoint Number.
00713   * @param  wAddr address to be set (must be word aligned).
00714   * @retval None
00715   */
00716 #define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) do { \
00717   register uint16_t *_wRegVal; \
00718   register uint32_t _wRegBase = (uint32_t)USBx; \
00719   \
00720   _wRegBase += (uint32_t)(USBx)->BTABLE; \
00721   _wRegVal = (uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \
00722   *_wRegVal = ((wAddr) >> 1) << 1; \
00723 } while(0) /* PCD_SET_EP_TX_ADDRESS */
00724
00725 #define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) do { \
00726   register uint16_t *_wRegVal; \
00727   register uint32_t _wRegBase = (uint32_t)USBx; \
00728   \
00729   _wRegBase += (uint32_t)(USBx)->BTABLE; \
00730   _wRegVal = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \
00731   *_wRegVal = ((wAddr) >> 1) << 1; \
00732 } while(0) /* PCD_SET_EP_RX_ADDRESS */
00733
00734 /**
00735   * @brief  Gets address of the tx/rx buffer.
00736   * @param  USBx USB peripheral instance register address.
00737   * @param  bEpNum Endpoint Number.
00738   * @retval address of the buffer.
00739   */
00740 #define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
00741 #define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))
00742
00743 /**
00744   * @brief  Sets counter of rx buffer with no. of blocks.
00745   * @param  pdwReg Register pointer
00746   * @param  wCount Counter.
00747   * @param  wNBlocks no. of Blocks.
00748   * @retval None
00749   */
00750 #define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) do { \
00751     (wNBlocks) = (wCount) >> 5; \
00752     *(pdwReg) = (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \
00753   } while(0) /* PCD_CALC_BLK32 */
00754
00755 #define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) do { \
00756     (wNBlocks) = (wCount) >> 1; \
00757     if (((wCount) & 0x1U) != 0U) \
00758     { \
00759       (wNBlocks)++; \
00760     } \
00761     *(pdwReg) = (uint16_t)((wNBlocks) << 10); \
00762   } while(0) /* PCD_CALC_BLK2 */
00763
00764 #define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount)  do { \
00765     uint32_t wNBlocks; \
00766     if ((wCount) == 0U) \
00767     { \
00768       *(pdwReg) &= (uint16_t)~USB_CNTRX_NBLK_MSK; \
00769       *(pdwReg) |= USB_CNTRX_BLSIZE; \
00770     } \
00771     else if((wCount) < 62U) \
00772     { \
00773       PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
00774     } \
00775     else \
00776     { \
00777       PCD_CALC_BLK32((pdwReg),(wCount), wNBlocks); \
00778     } \
00779   } while(0) /* PCD_SET_EP_CNT_RX_REG */
00780
00781 #define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) do { \
00782      register uint32_t _wRegBase = (uint32_t)(USBx); \
00783      uint16_t *pdwReg; \
00784      \
00785     _wRegBase += (uint32_t)(USBx)->BTABLE; \
00786     pdwReg = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
00787     PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount)); \
00788   } while(0)
00789
00790 /**
00791   * @brief  sets counter for the tx/rx buffer.
00792   * @param  USBx USB peripheral instance register address.
00793   * @param  bEpNum Endpoint Number.
00794   * @param  wCount Counter value.
00795   * @retval None
00796   */
00797 #define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) do { \
00798     register uint32_t _wRegBase = (uint32_t)(USBx); \
00799     uint16_t *_wRegVal; \
00800     \
00801     _wRegBase += (uint32_t)(USBx)->BTABLE; \
00802     _wRegVal = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
00803     *_wRegVal = (uint16_t)(wCount); \
00804 } while(0)
00805
00806 #define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) do { \
00807     register uint32_t _wRegBase = (uint32_t)(USBx); \
00808     uint16_t *_wRegVal; \
00809     \
00810     _wRegBase += (uint32_t)(USBx)->BTABLE; \
00811     _wRegVal = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
00812     PCD_SET_EP_CNT_RX_REG(_wRegVal, (wCount)); \
00813 } while(0)
00814
00815 /**
00816   * @brief  gets counter of the tx buffer.
00817   * @param  USBx USB peripheral instance register address.
00818   * @param  bEpNum Endpoint Number.
00819   * @retval Counter value
00820   */
00821 #define PCD_GET_EP_TX_CNT(USBx, bEpNum)        ((uint32_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU)
00822 #define PCD_GET_EP_RX_CNT(USBx, bEpNum)        ((uint32_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU)
00823
00824 /**
00825   * @brief  Sets buffer 0/1 address in a double buffer endpoint.
00826   * @param  USBx USB peripheral instance register address.
00827   * @param  bEpNum Endpoint Number.
00828   * @param  wBuf0Addr buffer 0 address.
00829   * @retval Counter value
00830   */
00831 #define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) do { \
00832     PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)); \
00833   } while(0) /* PCD_SET_EP_DBUF0_ADDR */
00834 #define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) do { \
00835     PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)); \
00836   } while(0) /* PCD_SET_EP_DBUF1_ADDR */
00837
00838 /**
00839   * @brief  Sets addresses in a double buffer endpoint.
00840   * @param  USBx USB peripheral instance register address.
00841   * @param  bEpNum Endpoint Number.
00842   * @param  wBuf0Addr: buffer 0 address.
00843   * @param  wBuf1Addr = buffer 1 address.
00844   * @retval None
00845   */
00846 #define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) do { \
00847     PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr)); \
00848     PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr)); \
00849   } while(0) /* PCD_SET_EP_DBUF_ADDR */
00850
00851 /**
00852   * @brief  Gets buffer 0/1 address of a double buffer endpoint.
00853   * @param  USBx USB peripheral instance register address.
00854   * @param  bEpNum Endpoint Number.
00855   * @retval None
00856   */
00857 #define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum)    (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
00858 #define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum)    (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
00859
00860 /**
00861   * @brief  Gets buffer 0/1 address of a double buffer endpoint.
00862   * @param  USBx USB peripheral instance register address.
00863   * @param  bEpNum Endpoint Number.
00864   * @param  bDir endpoint dir  EP_DBUF_OUT = OUT
00865   *         EP_DBUF_IN  = IN
00866   * @param  wCount: Counter value
00867   * @retval None
00868   */
00869 #define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) do { \
00870     if ((bDir) == 0U) \
00871       /* OUT endpoint */ \
00872     { \
00873       PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum), (wCount)); \
00874     } \
00875     else \
00876     { \
00877       if ((bDir) == 1U) \
00878       { \
00879         /* IN endpoint */ \
00880         PCD_SET_EP_TX_CNT((USBx), (bEpNum), (wCount)); \
00881       } \
00882     } \
00883   } while(0) /* SetEPDblBuf0Count*/
00884
00885 #define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) do { \
00886     register uint32_t _wBase = (uint32_t)(USBx); \
00887     uint16_t *_wEPRegVal; \
00888     \
00889     if ((bDir) == 0U) \
00890     { \
00891       /* OUT endpoint */ \
00892       PCD_SET_EP_RX_CNT((USBx), (bEpNum), (wCount)); \
00893     } \
00894     else \
00895     { \
00896       if ((bDir) == 1U) \
00897       { \
00898         /* IN endpoint */ \
00899         _wBase += (uint32_t)(USBx)->BTABLE; \
00900         _wEPRegVal = (uint16_t *)(_wBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
00901         *_wEPRegVal = (uint16_t)(wCount); \
00902       } \
00903     } \
00904   } while(0) /* SetEPDblBuf1Count */
00905
00906 #define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) do { \
00907     PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
00908     PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
00909   } while(0) /* PCD_SET_EP_DBUF_CNT  */
00910
00911 /**
00912   * @brief  Gets buffer 0/1 rx/tx counter for double buffering.
00913   * @param  USBx USB peripheral instance register address.
00914   * @param  bEpNum Endpoint Number.
00915   * @retval None
00916   */
00917 #define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum)     (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
00918 #define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum)     (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))
00919
00920
00921
00922 /**
00923   * @}
00924   */
00925
00926 /**
00927   * @}
00928   */
00929
00930 /**
00931   * @}
00932   */
00933 #endif /* defined (USB) */
00934
00935 #ifdef __cplusplus
00936 }
00937 #endif
00938
00939 #endif /* STM32WBxx_HAL_PCD_H */
00940
00941 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_pcd_ex.c Source File

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stm32wbxx_hal_pcd_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_pcd_ex.c
00004   * @author  MCD Application Team
00005   * @brief   PCD Extended HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the USB Peripheral Controller:
00008   *           + Extended features functions
00009   *
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00014   * All rights reserved.</center></h2>
00015   *
00016   * This software component is licensed by ST under BSD 3-Clause license,
00017   * the "License"; You may not use this file except in compliance with the
00018   * License. You may obtain a copy of the License at:
00019   *                        opensource.org/licenses/BSD-3-Clause
00020   *
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32wbxx_hal.h"
00026
00027 /** @addtogroup STM32WBxx_HAL_Driver
00028   * @{
00029   */
00030
00031 /** @defgroup PCDEx PCDEx
00032   * @brief PCD Extended HAL module driver
00033   * @{
00034   */
00035
00036 #ifdef HAL_PCD_MODULE_ENABLED
00037
00038 #if defined (USB)
00039 /* Private types -------------------------------------------------------------*/
00040 /* Private variables ---------------------------------------------------------*/
00041 /* Private constants ---------------------------------------------------------*/
00042 /* Private macros ------------------------------------------------------------*/
00043 /* Private functions ---------------------------------------------------------*/
00044 /* Exported functions --------------------------------------------------------*/
00045
00046 /** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
00047   * @{
00048   */
00049
00050 /** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
00051   * @brief    PCDEx control functions
00052  *
00053 @verbatim
00054  ===============================================================================
00055                  ##### Extended features functions #####
00056  ===============================================================================
00057     [..]  This section provides functions allowing to:
00058       (+) Update FIFO configuration
00059
00060 @endverbatim
00061   * @{
00062   */
00063
00064 /**
00065   * @brief  Configure PMA for EP
00066   * @param  hpcd  Device instance
00067   * @param  ep_addr endpoint address
00068   * @param  ep_kind endpoint Kind
00069   *                  USB_SNG_BUF: Single Buffer used
00070   *                  USB_DBL_BUF: Double Buffer used
00071   * @param  pmaadress: EP address in The PMA: In case of single buffer endpoint
00072   *                   this parameter is 16-bit value providing the address
00073   *                   in PMA allocated to endpoint.
00074   *                   In case of double buffer endpoint this parameter
00075   *                   is a 32-bit value providing the endpoint buffer 0 address
00076   *                   in the LSB part of 32-bit value and endpoint buffer 1 address
00077   *                   in the MSB part of 32-bit value.
00078   * @retval HAL status
00079   */
00080
00081 HAL_StatusTypeDef  HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
00082                                        uint16_t ep_addr,
00083                                        uint16_t ep_kind,
00084                                        uint32_t pmaadress)
00085 {
00086   PCD_EPTypeDef *ep;
00087
00088   /* initialize ep structure*/
00089   if ((0x80U & ep_addr) == 0x80U)
00090   {
00091     ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
00092   }
00093   else
00094   {
00095     ep = &hpcd->OUT_ep[ep_addr];
00096   }
00097
00098   /* Here we check if the endpoint is single or double Buffer*/
00099   if (ep_kind == PCD_SNG_BUF)
00100   {
00101     /* Single Buffer */
00102     ep->doublebuffer = 0U;
00103     /* Configure the PMA */
00104     ep->pmaadress = (uint16_t)pmaadress;
00105   }
00106   else /* USB_DBL_BUF */
00107   {
00108     /* Double Buffer Endpoint */
00109     ep->doublebuffer = 1U;
00110     /* Configure the PMA */
00111     ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU);
00112     ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16);
00113   }
00114
00115   return HAL_OK;
00116 }
00117
00118 /**
00119   * @brief  Activate BatteryCharging feature.
00120   * @param  hpcd PCD handle
00121   * @retval HAL status
00122   */
00123 HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
00124 {
00125   USB_TypeDef *USBx = hpcd->Instance;
00126   hpcd->battery_charging_active = 1U;
00127
00128   /* Enable BCD feature */
00129   USBx->BCDR |= USB_BCDR_BCDEN;
00130
00131   /* Enable DCD : Data Contact Detect */
00132   USBx->BCDR &= ~(USB_BCDR_PDEN);
00133   USBx->BCDR &= ~(USB_BCDR_SDEN);
00134   USBx->BCDR |= USB_BCDR_DCDEN;
00135
00136   return HAL_OK;
00137 }
00138
00139 /**
00140   * @brief  Deactivate BatteryCharging feature.
00141   * @param  hpcd PCD handle
00142   * @retval HAL status
00143   */
00144 HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
00145 {
00146   USB_TypeDef *USBx = hpcd->Instance;
00147   hpcd->battery_charging_active = 0U;
00148
00149   /* Disable BCD feature */
00150   USBx->BCDR &= ~(USB_BCDR_BCDEN);
00151
00152   return HAL_OK;
00153 }
00154
00155 /**
00156   * @brief  Handle BatteryCharging Process.
00157   * @param  hpcd PCD handle
00158   * @retval HAL status
00159   */
00160 void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
00161 {
00162   USB_TypeDef *USBx = hpcd->Instance;
00163   uint32_t tickstart = HAL_GetTick();
00164
00165   /* Wait Detect flag or a timeout is happen*/
00166   while ((USBx->BCDR & USB_BCDR_DCDET) == 0U)
00167   {
00168     /* Check for the Timeout */
00169     if ((HAL_GetTick() - tickstart) > 1000U)
00170     {
00171 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00172       hpcd->BCDCallback(hpcd, PCD_BCD_ERROR);
00173 #else
00174       HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
00175 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00176
00177       return;
00178     }
00179   }
00180
00181   HAL_Delay(200U);
00182
00183   /* Data Pin Contact ? Check Detect flag */
00184   if ((USBx->BCDR & USB_BCDR_DCDET) == USB_BCDR_DCDET)
00185   {
00186 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00187     hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION);
00188 #else
00189     HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
00190 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00191   }
00192   /* Primary detection: checks if connected to Standard Downstream Port
00193   (without charging capability) */
00194   USBx->BCDR &= ~(USB_BCDR_DCDEN);
00195   HAL_Delay(50U);
00196   USBx->BCDR |= (USB_BCDR_PDEN);
00197   HAL_Delay(50U);
00198
00199   /* If Charger detect ? */
00200   if ((USBx->BCDR & USB_BCDR_PDET) == USB_BCDR_PDET)
00201   {
00202     /* Start secondary detection to check connection to Charging Downstream
00203     Port or Dedicated Charging Port */
00204     USBx->BCDR &= ~(USB_BCDR_PDEN);
00205     HAL_Delay(50U);
00206     USBx->BCDR |= (USB_BCDR_SDEN);
00207     HAL_Delay(50U);
00208
00209     /* If CDP ? */
00210     if ((USBx->BCDR & USB_BCDR_SDET) == USB_BCDR_SDET)
00211     {
00212       /* Dedicated Downstream Port DCP */
00213 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00214       hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
00215 #else
00216       HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
00217 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00218     }
00219     else
00220     {
00221       /* Charging Downstream Port CDP */
00222 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00223       hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
00224 #else
00225       HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
00226 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00227     }
00228   }
00229   else /* NO */
00230   {
00231     /* Standard Downstream Port */
00232 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00233     hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
00234 #else
00235     HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
00236 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00237   }
00238
00239   /* Battery Charging capability discovery finished Start Enumeration */
00240   (void)HAL_PCDEx_DeActivateBCD(hpcd);
00241 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
00242   hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
00243 #else
00244   HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
00245 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
00246 }
00247
00248
00249 /**
00250   * @brief  Activate LPM feature.
00251   * @param  hpcd PCD handle
00252   * @retval HAL status
00253   */
00254 HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
00255 {
00256
00257   USB_TypeDef *USBx = hpcd->Instance;
00258   hpcd->lpm_active = 1U;
00259   hpcd->LPM_State = LPM_L0;
00260
00261   USBx->LPMCSR |= USB_LPMCSR_LMPEN;
00262   USBx->LPMCSR |= USB_LPMCSR_LPMACK;
00263
00264   return HAL_OK;
00265 }
00266
00267 /**
00268   * @brief  Deactivate LPM feature.
00269   * @param  hpcd PCD handle
00270   * @retval HAL status
00271   */
00272 HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
00273 {
00274   USB_TypeDef *USBx = hpcd->Instance;
00275
00276   hpcd->lpm_active = 0U;
00277
00278   USBx->LPMCSR &= ~(USB_LPMCSR_LMPEN);
00279   USBx->LPMCSR &= ~(USB_LPMCSR_LPMACK);
00280
00281   return HAL_OK;
00282 }
00283
00284
00285
00286 /**
00287   * @brief  Send LPM message to user layer callback.
00288   * @param  hpcd PCD handle
00289   * @param  msg LPM message
00290   * @retval HAL status
00291   */
00292 __weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
00293 {
00294   /* Prevent unused argument(s) compilation warning */
00295   UNUSED(hpcd);
00296   UNUSED(msg);
00297
00298   /* NOTE : This function should not be modified, when the callback is needed,
00299             the HAL_PCDEx_LPM_Callback could be implemented in the user file
00300    */
00301 }
00302
00303 /**
00304   * @brief  Send BatteryCharging message to user layer callback.
00305   * @param  hpcd PCD handle
00306   * @param  msg LPM message
00307   * @retval HAL status
00308   */
00309 __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
00310 {
00311   /* Prevent unused argument(s) compilation warning */
00312   UNUSED(hpcd);
00313   UNUSED(msg);
00314
00315   /* NOTE : This function should not be modified, when the callback is needed,
00316             the HAL_PCDEx_BCD_Callback could be implemented in the user file
00317    */
00318 }
00319
00320 /**
00321   * @}
00322   */
00323
00324 /**
00325   * @}
00326   */
00327 #endif /* defined (USB) */
00328 #endif /* HAL_PCD_MODULE_ENABLED */
00329
00330 /**
00331   * @}
00332   */
00333
00334 /**
00335   * @}
00336   */
00337
00338 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_pcd_ex.h Source File

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stm32wbxx_hal_pcd_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_pcd_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of PCD HAL Extension module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_PCD_EX_H
00022 #define STM32WBxx_HAL_PCD_EX_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 #if defined (USB)
00032 /** @addtogroup STM32WBxx_HAL_Driver
00033   * @{
00034   */
00035
00036 /** @addtogroup PCDEx
00037   * @{
00038   */
00039 /* Exported types ------------------------------------------------------------*/
00040 /* Exported constants --------------------------------------------------------*/
00041 /* Exported macros -----------------------------------------------------------*/
00042 /* Exported functions --------------------------------------------------------*/
00043 /** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
00044   * @{
00045   */
00046 /** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
00047   * @{
00048   */
00049
00050
00051
00052 HAL_StatusTypeDef  HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
00053                                        uint16_t ep_addr,
00054                                        uint16_t ep_kind,
00055                                        uint32_t pmaadress);
00056
00057
00058 HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
00059 HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
00060
00061
00062 HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
00063 HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
00064 void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
00065
00066 void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
00067 void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
00068
00069 /**
00070   * @}
00071   */
00072
00073 /**
00074   * @}
00075   */
00076
00077 /**
00078   * @}
00079   */
00080
00081 /**
00082   * @}
00083   */
00084 #endif /* defined (USB) */
00085
00086 #ifdef __cplusplus
00087 }
00088 #endif
00089
00090
00091 #endif /* STM32WBxx_HAL_PCD_EX_H */
00092
00093 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_pka.c Source File

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stm32wbxx_hal_pka.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_pka.c
00004   * @author  MCD Application Team
00005   * @brief   PKA HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of public key accelerator(PKA):
00008   *           + Initialization and de-initialization functions
00009   *           + Start an operation
00010   *           + Retrieve the operation result
00011   *
00012   @verbatim
00013   ==============================================================================
00014                         ##### How to use this driver #####
00015   ==============================================================================
00016     [..]
00017     The PKA HAL driver can be used as follows:
00018
00019     (#) Declare a PKA_HandleTypeDef handle structure, for example: PKA_HandleTypeDef  hpka;
00020
00021     (#) Initialize the PKA low level resources by implementing the HAL_PKA_MspInit() API:
00022         (##) Enable the PKA interface clock
00023         (##) NVIC configuration if you need to use interrupt process
00024             (+++) Configure the PKA interrupt priority
00025             (+++) Enable the NVIC PKA IRQ Channel
00026
00027     (#) Initialize the PKA registers by calling the HAL_PKA_Init() API which trig
00028         HAL_PKA_MspInit().
00029
00030     (#) Fill entirely the input structure corresponding to your operation:
00031         For instance: PKA_ModExpInTypeDef for HAL_PKA_ModExp().
00032
00033     (#) Execute the operation (in polling or interrupt) and check the returned value.
00034
00035     (#) Retrieve the result of the operation (For instance, HAL_PKA_ModExp_GetResult for
00036         HAL_PKA_ModExp operation). The function to gather the result is different for each
00037         kind of operation. The correspondence can be found in the following section.
00038
00039     (#) Call the function HAL_PKA_DeInit() to restore the default configuration which trig
00040         HAL_PKA_MspDeInit().
00041
00042     *** High level operation ***
00043     =================================
00044     [..]
00045       (+) Input structure requires buffers as uint8_t array.
00046
00047       (+) Output structure requires buffers as uint8_t array.
00048
00049       (+) Modular exponentiation using:
00050       (++) HAL_PKA_ModExp().
00051       (++) HAL_PKA_ModExp_IT().
00052       (++) HAL_PKA_ModExpFastMode().
00053       (++) HAL_PKA_ModExpFastMode_IT().
00054       (++) HAL_PKA_ModExp_GetResult() to retrieve the result of the operation.
00055
00056       (+) RSA Chinese Remainder Theorem (CRT) using:
00057       (++) HAL_PKA_RSACRTExp().
00058       (++) HAL_PKA_RSACRTExp_IT().
00059       (++) HAL_PKA_RSACRTExp_GetResult() to retrieve the result of the operation.
00060
00061       (+) ECC Point Check using:
00062       (++) HAL_PKA_PointCheck().
00063       (++) HAL_PKA_PointCheck_IT().
00064       (++) HAL_PKA_PointCheck_IsOnCurve() to retrieve the result of the operation.
00065
00066       (+) ECDSA Sign
00067       (++) HAL_PKA_ECDSASign().
00068       (++) HAL_PKA_ECDSASign_IT().
00069       (++) HAL_PKA_ECDSASign_GetResult() to retrieve the result of the operation.
00070
00071       (+) ECDSA Verify
00072       (++) HAL_PKA_ECDSAVerif().
00073       (++) HAL_PKA_ECDSAVerif_IT().
00074       (++) HAL_PKA_ECDSAVerif_IsValidSignature() to retrieve the result of the operation.
00075
00076       (+) ECC Scalar Multiplication using:
00077       (++) HAL_PKA_ECCMul().
00078       (++) HAL_PKA_ECCMul_IT().
00079       (++) HAL_PKA_ECCMulFastMode().
00080       (++) HAL_PKA_ECCMulFastMode_IT().
00081       (++) HAL_PKA_ECCMul_GetResult() to retrieve the result of the operation.
00082
00083     *** Low level operation ***
00084     =================================
00085     [..]
00086       (+) Input structure requires buffers as uint32_t array.
00087
00088       (+) Output structure requires buffers as uint32_t array.
00089
00090       (+) Arithmetic addition using:
00091       (++) HAL_PKA_Add().
00092       (++) HAL_PKA_Add_IT().
00093       (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
00094             The resulting size can be the input parameter or the input parameter size + 1 (overflow).
00095
00096       (+) Arithmetic substraction using:
00097       (++) HAL_PKA_Sub().
00098       (++) HAL_PKA_Sub_IT().
00099       (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
00100
00101       (+) Arithmetic multiplication using:
00102       (++) HAL_PKA_Mul().
00103       (++) HAL_PKA_Mul_IT().
00104       (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
00105
00106       (+) Comparison using:
00107       (++) HAL_PKA_Cmp().
00108       (++) HAL_PKA_Cmp_IT().
00109       (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
00110
00111       (+) Modular addition using:
00112       (++) HAL_PKA_ModAdd().
00113       (++) HAL_PKA_ModAdd_IT().
00114       (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
00115
00116       (+) Modular substraction using:
00117       (++) HAL_PKA_ModSub().
00118       (++) HAL_PKA_ModSub_IT().
00119       (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
00120
00121       (+) Modular inversion using:
00122       (++) HAL_PKA_ModInv().
00123       (++) HAL_PKA_ModInv_IT().
00124       (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
00125
00126       (+) Modular reduction using:
00127       (++) HAL_PKA_ModRed().
00128       (++) HAL_PKA_ModRed_IT().
00129       (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
00130
00131       (+) Montgomery multiplication using:
00132       (++) HAL_PKA_MontgomeryMul().
00133       (++) HAL_PKA_MontgomeryMul_IT().
00134       (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
00135
00136     *** Montgomery parameter ***
00137     =================================
00138       (+) For some operation, the computation of the Montgomery parameter is a prerequisite.
00139       (+) Input structure requires buffers as uint8_t array.
00140       (+) Output structure requires buffers as uint32_t array.(Only used inside PKA).
00141       (+) You can compute the Montgomery parameter using:
00142       (++) HAL_PKA_MontgomeryParam().
00143       (++) HAL_PKA_MontgomeryParam_IT().
00144       (++) HAL_PKA_MontgomeryParam_GetResult() to retrieve the result of the operation.
00145       (+) You can save computation time by storing this parameter for a later usage.
00146           Use it again with HAL_PKA_MontgomeryParam_Set();
00147
00148     *** Polling mode operation ***
00149     ===================================
00150     [..]
00151       (+) When an operation is started in polling mode, the function returns when:
00152       (++) A timeout is encounter.
00153       (++) The operation is completed.
00154
00155     *** Interrupt mode operation ***
00156     ===================================
00157     [..]
00158       (+) Add HAL_PKA_IRQHandler to the IRQHandler of PKA.
00159       (+) Enable the IRQ using HAL_NVIC_EnableIRQ().
00160       (+) When an operation is started in interrupt mode, the function returns immediatly.
00161       (+) When the operation is completed, the callback HAL_PKA_OperationCpltCallback is called.
00162       (+) When an error is encountered, the callback HAL_PKA_ErrorCallback is called.
00163       (+) To stop any operation in interrupt mode, use HAL_PKA_Abort().
00164
00165     *** Utilities ***
00166     ===================================
00167     [..]
00168       (+) To clear the PKA RAM, use HAL_PKA_RAMReset().
00169       (+) To get current state, use HAL_PKA_GetState().
00170       (+) To get current error, use HAL_PKA_GetError().
00171
00172     *** Callback registration ***
00173     =============================================
00174     [..]
00175
00176      The compilation flag USE_HAL_PKA_REGISTER_CALLBACKS, when set to 1,
00177      allows the user to configure dynamically the driver callbacks.
00178      Use Functions @ref HAL_PKA_RegisterCallback()
00179      to register an interrupt callback.
00180     [..]
00181
00182      Function @ref HAL_PKA_RegisterCallback() allows to register following callbacks:
00183        (+) OperationCpltCallback : callback for End of operation.
00184        (+) ErrorCallback         : callback for error detection.
00185        (+) MspInitCallback       : callback for Msp Init.
00186        (+) MspDeInitCallback     : callback for Msp DeInit.
00187      This function takes as parameters the HAL peripheral handle, the Callback ID
00188      and a pointer to the user callback function.
00189     [..]
00190
00191      Use function @ref HAL_PKA_UnRegisterCallback to reset a callback to the default
00192      weak function.
00193     [..]
00194
00195      @ref HAL_PKA_UnRegisterCallback takes as parameters the HAL peripheral handle,
00196      and the Callback ID.
00197      This function allows to reset following callbacks:
00198        (+) OperationCpltCallback : callback for End of operation.
00199        (+) ErrorCallback         : callback for error detection.
00200        (+) MspInitCallback       : callback for Msp Init.
00201        (+) MspDeInitCallback     : callback for Msp DeInit.
00202      [..]
00203
00204      By default, after the @ref HAL_PKA_Init() and when the state is @ref HAL_PKA_STATE_RESET
00205      all callbacks are set to the corresponding weak functions:
00206      examples @ref HAL_PKA_OperationCpltCallback(), @ref HAL_PKA_ErrorCallback().
00207      Exception done for MspInit and MspDeInit functions that are
00208      reset to the legacy weak functions in the @ref HAL_PKA_Init()/ @ref HAL_PKA_DeInit() only when
00209      these callbacks are null (not registered beforehand).
00210     [..]
00211
00212      If MspInit or MspDeInit are not null, the @ref HAL_PKA_Init()/ @ref HAL_PKA_DeInit()
00213      keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
00214      [..]
00215
00216      Callbacks can be registered/unregistered in @ref HAL_PKA_STATE_READY state only.
00217      Exception done MspInit/MspDeInit functions that can be registered/unregistered
00218      in @ref HAL_PKA_STATE_READY or @ref HAL_PKA_STATE_RESET state,
00219      thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00220     [..]
00221
00222      Then, the user first registers the MspInit/MspDeInit user callbacks
00223      using @ref HAL_PKA_RegisterCallback() before calling @ref HAL_PKA_DeInit()
00224      or @ref HAL_PKA_Init() function.
00225      [..]
00226
00227      When the compilation flag USE_HAL_PKA_REGISTER_CALLBACKS is set to 0 or
00228      not defined, the callback registration feature is not available and all callbacks
00229      are set to the corresponding weak functions.
00230
00231   @endverbatim
00232   ******************************************************************************
00233   * @attention
00234   *
00235   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00236   * All rights reserved.</center></h2>
00237   *
00238   * This software component is licensed by ST under BSD 3-Clause license,
00239   * the "License"; You may not use this file except in compliance with the
00240   * License. You may obtain a copy of the License at:
00241   *                        opensource.org/licenses/BSD-3-Clause
00242   *
00243   ******************************************************************************
00244   */
00245
00246 /* Includes ------------------------------------------------------------------*/
00247 #include "stm32wbxx_hal.h"
00248
00249 /** @addtogroup STM32WBxx_HAL_Driver
00250   * @{
00251   */
00252
00253 #if defined(PKA) && defined(HAL_PKA_MODULE_ENABLED)
00254
00255 /** @defgroup PKA PKA
00256   * @brief PKA HAL module driver.
00257   * @{
00258   */
00259
00260 /* Private typedef -----------------------------------------------------------*/
00261 /* Private define ------------------------------------------------------------*/
00262 /** @defgroup PKA_Private_Define PKA Private Define
00263   * @{
00264   */
00265 #define PKA_RAM_SIZE 894U
00266 /**
00267   * @}
00268   */
00269
00270 /* Private macro -------------------------------------------------------------*/
00271 /* Private variables ---------------------------------------------------------*/
00272 /* Private function prototypes -----------------------------------------------*/
00273 /** @defgroup PKA_Private_Functions PKA Private Functions
00274   * @{
00275   */
00276 uint32_t PKA_GetMode(PKA_HandleTypeDef *hpka);
00277 HAL_StatusTypeDef PKA_PollEndOfOperation(PKA_HandleTypeDef *hpka, uint32_t Timeout, uint32_t Tickstart);
00278 uint32_t PKA_CheckError(PKA_HandleTypeDef *hpka, uint32_t mode);
00279 uint32_t PKA_GetBitSize_u8(uint32_t byteNumber);
00280 uint32_t PKA_GetOptBitSize_u8(uint32_t byteNumber, uint8_t msb);
00281 uint32_t PKA_GetBitSize_u32(uint32_t wordNumber);
00282 uint32_t PKA_GetArraySize_u8(uint32_t bitSize);
00283 void PKA_Memcpy_u32_to_u8(uint8_t dst[], __IO const uint32_t src[], size_t n);
00284 void PKA_Memcpy_u8_to_u32(__IO uint32_t dst[], const uint8_t src[], size_t n);
00285 void PKA_Memcpy_u32_to_u32(__IO uint32_t dst[], __IO const uint32_t src[], size_t n);
00286 HAL_StatusTypeDef PKA_Process(PKA_HandleTypeDef *hpka, uint32_t mode, uint32_t Timeout);
00287 HAL_StatusTypeDef PKA_Process_IT(PKA_HandleTypeDef *hpka, uint32_t mode);
00288 void PKA_ModExp_Set(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in);
00289 void PKA_ModExpFastMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in);
00290 void PKA_ECDSASign_Set(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in);
00291 void PKA_ECDSAVerif_Set(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in);
00292 void PKA_RSACRTExp_Set(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in);
00293 void PKA_PointCheck_Set(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in);
00294 void PKA_ECCMul_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in);
00295 void PKA_ECCMulFastMode_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulFastModeInTypeDef *in);
00296 void PKA_ModRed_Set(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in);
00297 void PKA_ModInv_Set(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in);
00298 void PKA_MontgomeryParam_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint8_t *pOp1);
00299 void PKA_ARI_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint32_t *pOp1, const uint32_t *pOp2, const uint8_t *pOp3);
00300 /**
00301   * @}
00302   */
00303
00304 /* Exported functions --------------------------------------------------------*/
00305
00306 /** @defgroup PKA_Exported_Functions PKA Exported Functions
00307   * @{
00308   */
00309
00310 /** @defgroup PKA_Exported_Functions_Group1 Initialization and de-initialization functions
00311  *  @brief   Initialization and de-initialization functions
00312  *
00313 @verbatim
00314  ===============================================================================
00315              ##### Initialization and de-initialization functions  #####
00316  ===============================================================================
00317     [..]  This subsection provides a set of functions allowing to initialize and
00318           deinitialize the PKAx peripheral:
00319
00320       (+) User must implement HAL_PKA_MspInit() function in which he configures
00321           all related peripherals resources (CLOCK, IT and NVIC ).
00322
00323       (+) Call the function HAL_PKA_Init() to configure the selected device with
00324           the selected configuration:
00325         (++) Security level
00326
00327       (+) Call the function HAL_PKA_DeInit() to restore the default configuration
00328           of the selected PKAx peripheral.
00329
00330 @endverbatim
00331   * @{
00332   */
00333
00334 /**
00335   * @brief  Initialize the PKA according to the specified
00336   *         parameters in the PKA_InitTypeDef and initialize the associated handle.
00337   * @param  hpka PKA handle
00338   * @retval HAL status
00339   */
00340 HAL_StatusTypeDef HAL_PKA_Init(PKA_HandleTypeDef *hpka)
00341 {
00342   HAL_StatusTypeDef err = HAL_OK;
00343
00344   /* Check the PKA handle allocation */
00345   if (hpka != NULL)
00346   {
00347     /* Check the parameters */
00348     assert_param(IS_PKA_ALL_INSTANCE(hpka->Instance));
00349
00350     if (hpka->State == HAL_PKA_STATE_RESET)
00351     {
00352
00353 #if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
00354       /* Init the PKA Callback settings */
00355       hpka->OperationCpltCallback = HAL_PKA_OperationCpltCallback; /* Legacy weak OperationCpltCallback */
00356       hpka->ErrorCallback         = HAL_PKA_ErrorCallback;         /* Legacy weak ErrorCallback         */
00357
00358       if (hpka->MspInitCallback == NULL)
00359       {
00360         hpka->MspInitCallback = HAL_PKA_MspInit; /* Legacy weak MspInit  */
00361       }
00362
00363       /* Init the low level hardware */
00364       hpka->MspInitCallback(hpka);
00365 #else
00366       /* Init the low level hardware */
00367       HAL_PKA_MspInit(hpka);
00368 #endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
00369     }
00370
00371     /* Set the state to busy */
00372     hpka->State = HAL_PKA_STATE_BUSY;
00373
00374     /* Reset the control register and enable the PKA */
00375     hpka->Instance->CR = PKA_CR_EN;
00376
00377     /* Reset any pending flag */
00378     SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC);
00379
00380     /* Initialize the error code */
00381     hpka->ErrorCode = HAL_PKA_ERROR_NONE;
00382
00383     /* Set the state to ready */
00384     hpka->State = HAL_PKA_STATE_READY;
00385   }
00386   else
00387   {
00388     err = HAL_ERROR;
00389   }
00390
00391   return err;
00392 }
00393
00394 /**
00395   * @brief  DeInitialize the PKA peripheral.
00396   * @param  hpka PKA handle
00397   * @retval HAL status
00398   */
00399 HAL_StatusTypeDef HAL_PKA_DeInit(PKA_HandleTypeDef *hpka)
00400 {
00401   HAL_StatusTypeDef err = HAL_OK;
00402
00403   /* Check the PKA handle allocation */
00404   if (hpka != NULL)
00405   {
00406     /* Check the parameters */
00407     assert_param(IS_PKA_ALL_INSTANCE(hpka->Instance));
00408
00409     /* Set the state to busy */
00410     hpka->State = HAL_PKA_STATE_BUSY;
00411
00412     /* Reset the control register */
00413     /* This abort any operation in progress (PKA RAM content is not guaranted in this case) */
00414     hpka->Instance->CR = 0;
00415
00416     /* Reset any pending flag */
00417     SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC);
00418
00419 #if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
00420     if (hpka->MspDeInitCallback == NULL)
00421     {
00422       hpka->MspDeInitCallback = HAL_PKA_MspDeInit; /* Legacy weak MspDeInit  */
00423     }
00424
00425     /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00426     hpka->MspDeInitCallback(hpka);
00427 #else
00428     /* DeInit the low level hardware: CLOCK, NVIC */
00429     HAL_PKA_MspDeInit(hpka);
00430 #endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
00431
00432     /* Reset the error code */
00433     hpka->ErrorCode = HAL_PKA_ERROR_NONE;
00434
00435     /* Reset the state */
00436     hpka->State = HAL_PKA_STATE_RESET;
00437   }
00438   else
00439   {
00440     err = HAL_ERROR;
00441   }
00442
00443   return err;
00444 }
00445
00446 /**
00447   * @brief  Initialize the PKA MSP.
00448   * @param  hpka PKA handle
00449   * @retval None
00450   */
00451 __weak void HAL_PKA_MspInit(PKA_HandleTypeDef *hpka)
00452 {
00453   /* Prevent unused argument(s) compilation warning */
00454   UNUSED(hpka);
00455
00456   /* NOTE : This function should not be modified, when the callback is needed,
00457             the HAL_PKA_MspInit can be implemented in the user file
00458    */
00459 }
00460
00461 /**
00462   * @brief  DeInitialize the PKA MSP.
00463   * @param  hpka PKA handle
00464   * @retval None
00465   */
00466 __weak void HAL_PKA_MspDeInit(PKA_HandleTypeDef *hpka)
00467 {
00468   /* Prevent unused argument(s) compilation warning */
00469   UNUSED(hpka);
00470
00471   /* NOTE : This function should not be modified, when the callback is needed,
00472             the HAL_PKA_MspDeInit can be implemented in the user file
00473    */
00474 }
00475
00476 #if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
00477 /**
00478   * @brief  Register a User PKA Callback
00479   *         To be used instead of the weak predefined callback
00480   * @param  hpka Pointer to a PKA_HandleTypeDef structure that contains
00481   *                the configuration information for the specified PKA.
00482   * @param  CallbackID ID of the callback to be registered
00483   *         This parameter can be one of the following values:
00484   *          @arg @ref HAL_PKA_OPERATION_COMPLETE_CB_ID End of operation callback ID
00485   *          @arg @ref HAL_PKA_ERROR_CB_ID Error callback ID
00486   *          @arg @ref HAL_PKA_MSPINIT_CB_ID MspInit callback ID
00487   *          @arg @ref HAL_PKA_MSPDEINIT_CB_ID MspDeInit callback ID
00488   * @param  pCallback pointer to the Callback function
00489   * @retval HAL status
00490   */
00491 HAL_StatusTypeDef HAL_PKA_RegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID, pPKA_CallbackTypeDef pCallback)
00492 {
00493   HAL_StatusTypeDef status = HAL_OK;
00494
00495   if (pCallback == NULL)
00496   {
00497     /* Update the error code */
00498     hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK;
00499
00500     return HAL_ERROR;
00501   }
00502
00503   if (HAL_PKA_STATE_READY == hpka->State)
00504   {
00505     switch (CallbackID)
00506     {
00507       case HAL_PKA_OPERATION_COMPLETE_CB_ID :
00508         hpka->OperationCpltCallback = pCallback;
00509         break;
00510
00511       case HAL_PKA_ERROR_CB_ID :
00512         hpka->ErrorCallback = pCallback;
00513         break;
00514
00515       case HAL_PKA_MSPINIT_CB_ID :
00516         hpka->MspInitCallback = pCallback;
00517         break;
00518
00519       case HAL_PKA_MSPDEINIT_CB_ID :
00520         hpka->MspDeInitCallback = pCallback;
00521         break;
00522
00523       default :
00524         /* Update the error code */
00525         hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK;
00526
00527         /* Return error status */
00528         status = HAL_ERROR;
00529         break;
00530     }
00531   }
00532   else if (HAL_PKA_STATE_RESET == hpka->State)
00533   {
00534     switch (CallbackID)
00535     {
00536       case HAL_PKA_MSPINIT_CB_ID :
00537         hpka->MspInitCallback = pCallback;
00538         break;
00539
00540       case HAL_PKA_MSPDEINIT_CB_ID :
00541         hpka->MspDeInitCallback = pCallback;
00542         break;
00543
00544       default :
00545         /* Update the error code */
00546         hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK;
00547
00548         /* Return error status */
00549         status = HAL_ERROR;
00550         break;
00551     }
00552   }
00553   else
00554   {
00555     /* Update the error code */
00556     hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK;
00557
00558     /* Return error status */
00559     status =  HAL_ERROR;
00560   }
00561
00562   return status;
00563 }
00564
00565 /**
00566   * @brief  Unregister a PKA Callback
00567   *         PKA callback is redirected to the weak predefined callback
00568   * @param  hpka Pointer to a PKA_HandleTypeDef structure that contains
00569   *                the configuration information for the specified PKA.
00570   * @param  CallbackID ID of the callback to be unregistered
00571   *         This parameter can be one of the following values:
00572   *          @arg @ref HAL_PKA_OPERATION_COMPLETE_CB_ID End of operation callback ID
00573   *          @arg @ref HAL_PKA_ERROR_CB_ID Error callback ID
00574   *          @arg @ref HAL_PKA_MSPINIT_CB_ID MspInit callback ID
00575   *          @arg @ref HAL_PKA_MSPDEINIT_CB_ID MspDeInit callback ID
00576   * @retval HAL status
00577   */
00578 HAL_StatusTypeDef HAL_PKA_UnRegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID)
00579 {
00580   HAL_StatusTypeDef status = HAL_OK;
00581
00582   if (HAL_PKA_STATE_READY == hpka->State)
00583   {
00584     switch (CallbackID)
00585     {
00586       case HAL_PKA_OPERATION_COMPLETE_CB_ID :
00587         hpka->OperationCpltCallback = HAL_PKA_OperationCpltCallback; /* Legacy weak OperationCpltCallback */
00588         break;
00589
00590       case HAL_PKA_ERROR_CB_ID :
00591         hpka->ErrorCallback = HAL_PKA_ErrorCallback;                 /* Legacy weak ErrorCallback        */
00592         break;
00593
00594       case HAL_PKA_MSPINIT_CB_ID :
00595         hpka->MspInitCallback = HAL_PKA_MspInit;                     /* Legacy weak MspInit              */
00596         break;
00597
00598       case HAL_PKA_MSPDEINIT_CB_ID :
00599         hpka->MspDeInitCallback = HAL_PKA_MspDeInit;                 /* Legacy weak MspDeInit            */
00600         break;
00601
00602       default :
00603         /* Update the error code */
00604         hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK;
00605
00606         /* Return error status */
00607         status =  HAL_ERROR;
00608         break;
00609     }
00610   }
00611   else if (HAL_PKA_STATE_RESET == hpka->State)
00612   {
00613     switch (CallbackID)
00614     {
00615       case HAL_PKA_MSPINIT_CB_ID :
00616         hpka->MspInitCallback = HAL_PKA_MspInit;                   /* Legacy weak MspInit              */
00617         break;
00618
00619       case HAL_PKA_MSPDEINIT_CB_ID :
00620         hpka->MspDeInitCallback = HAL_PKA_MspDeInit;               /* Legacy weak MspDeInit            */
00621         break;
00622
00623       default :
00624         /* Update the error code */
00625         hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK;
00626
00627         /* Return error status */
00628         status =  HAL_ERROR;
00629         break;
00630     }
00631   }
00632   else
00633   {
00634     /* Update the error code */
00635     hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK;
00636
00637     /* Return error status */
00638     status =  HAL_ERROR;
00639   }
00640
00641   return status;
00642 }
00643
00644 #endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
00645
00646 /**
00647   * @}
00648   */
00649
00650 /** @defgroup PKA_Exported_Functions_Group2 IO operation functions
00651  *  @brief   IO operation functions
00652  *
00653 @verbatim
00654  ===============================================================================
00655                       ##### IO operation functions #####
00656  ===============================================================================
00657     [..]
00658     This subsection provides a set of functions allowing to manage the PKA operations.
00659
00660     (#) There are two modes of operation:
00661
00662        (++) Blocking mode : The operation is performed in the polling mode.
00663             These functions return when data operation is completed.
00664        (++) No-Blocking mode : The operation is performed using Interrupts.
00665             These functions return immediatly.
00666             The end of the operation is indicated by HAL_PKA_ErrorCallback in case of error.
00667             The end of the operation is indicated by HAL_PKA_OperationCpltCallback in case of success.
00668             To stop any operation in interrupt mode, use HAL_PKA_Abort().
00669
00670     (#) Blocking mode functions are :
00671
00672         (++) HAL_PKA_ModExp()
00673         (++) HAL_PKA_ModExpFastMode()
00674         (++) HAL_PKA_ModExp_GetResult();
00675
00676         (++) HAL_PKA_ECDSASign()
00677         (++) HAL_PKA_ECDSASign_GetResult();
00678
00679         (++) HAL_PKA_ECDSAVerif()
00680         (++) HAL_PKA_ECDSAVerif_IsValidSignature();
00681
00682         (++) HAL_PKA_RSACRTExp()
00683         (++) HAL_PKA_RSACRTExp_GetResult();
00684
00685         (++) HAL_PKA_PointCheck()
00686         (++) HAL_PKA_PointCheck_IsOnCurve();
00687
00688         (++) HAL_PKA_ECCMul()
00689         (++) HAL_PKA_ECCMulFastMode()
00690         (++) HAL_PKA_ECCMul_GetResult();
00691
00692         (++) HAL_PKA_Add()
00693         (++) HAL_PKA_Sub()
00694         (++) HAL_PKA_Cmp()
00695         (++) HAL_PKA_Mul()
00696         (++) HAL_PKA_ModAdd()
00697         (++) HAL_PKA_ModSub()
00698         (++) HAL_PKA_ModInv()
00699         (++) HAL_PKA_ModRed()
00700         (++) HAL_PKA_MontgomeryMul()
00701         (++) HAL_PKA_Arithmetic_GetResult(P);
00702
00703         (++) HAL_PKA_MontgomeryParam()
00704         (++) HAL_PKA_MontgomeryParam_GetResult();
00705
00706     (#) No-Blocking mode functions with Interrupt are :
00707
00708         (++) HAL_PKA_ModExp_IT();
00709         (++) HAL_PKA_ModExpFastMode_IT();
00710         (++) HAL_PKA_ModExp_GetResult();
00711
00712         (++) HAL_PKA_ECDSASign_IT();
00713         (++) HAL_PKA_ECDSASign_GetResult();
00714
00715         (++) HAL_PKA_ECDSAVerif_IT();
00716         (++) HAL_PKA_ECDSAVerif_IsValidSignature();
00717
00718         (++) HAL_PKA_RSACRTExp_IT();
00719         (++) HAL_PKA_RSACRTExp_GetResult();
00720
00721         (++) HAL_PKA_PointCheck_IT();
00722         (++) HAL_PKA_PointCheck_IsOnCurve();
00723
00724         (++) HAL_PKA_ECCMul_IT();
00725         (++) HAL_PKA_ECCMulFastMode_IT();
00726         (++) HAL_PKA_ECCMul_GetResult();
00727
00728         (++) HAL_PKA_Add_IT();
00729         (++) HAL_PKA_Sub_IT();
00730         (++) HAL_PKA_Cmp_IT();
00731         (++) HAL_PKA_Mul_IT();
00732         (++) HAL_PKA_ModAdd_IT();
00733         (++) HAL_PKA_ModSub_IT();
00734         (++) HAL_PKA_ModInv_IT();
00735         (++) HAL_PKA_ModRed_IT();
00736         (++) HAL_PKA_MontgomeryMul_IT();
00737         (++) HAL_PKA_Arithmetic_GetResult();
00738
00739         (++) HAL_PKA_MontgomeryParam_IT();
00740         (++) HAL_PKA_MontgomeryParam_GetResult();
00741
00742         (++) HAL_PKA_Abort();
00743
00744 @endverbatim
00745   * @{
00746   */
00747
00748 /**
00749   * @brief  Modular exponentiation in blocking mode.
00750   * @param  hpka PKA handle
00751   * @param  in Input information
00752   * @param  Timeout Timeout duration
00753   * @retval HAL status
00754   */
00755 HAL_StatusTypeDef HAL_PKA_ModExp(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in, uint32_t Timeout)
00756 {
00757   /* Set input parameter in PKA RAM */
00758   PKA_ModExp_Set(hpka, in);
00759
00760   /* Start the operation */
00761   return PKA_Process(hpka, PKA_MODE_MODULAR_EXP, Timeout);
00762 }
00763
00764 /**
00765   * @brief  Modular exponentiation in non-blocking mode with Interrupt.
00766   * @param  hpka PKA handle
00767   * @param  in Input information
00768   * @retval HAL status
00769   */
00770 HAL_StatusTypeDef HAL_PKA_ModExp_IT(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in)
00771 {
00772   /* Set input parameter in PKA RAM */
00773   PKA_ModExp_Set(hpka, in);
00774
00775   /* Start the operation */
00776   return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP);
00777 }
00778
00779 /**
00780   * @brief  Modular exponentiation in blocking mode.
00781   * @param  hpka PKA handle
00782   * @param  in Input information
00783   * @param  Timeout Timeout duration
00784   * @retval HAL status
00785   */
00786 HAL_StatusTypeDef HAL_PKA_ModExpFastMode(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in, uint32_t Timeout)
00787 {
00788   /* Set input parameter in PKA RAM */
00789   PKA_ModExpFastMode_Set(hpka, in);
00790
00791   /* Start the operation */
00792   return PKA_Process(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE, Timeout);
00793 }
00794
00795 /**
00796   * @brief  Modular exponentiation in non-blocking mode with Interrupt.
00797   * @param  hpka PKA handle
00798   * @param  in Input information
00799   * @retval HAL status
00800   */
00801 HAL_StatusTypeDef HAL_PKA_ModExpFastMode_IT(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in)
00802 {
00803   /* Set input parameter in PKA RAM */
00804   PKA_ModExpFastMode_Set(hpka, in);
00805
00806   /* Start the operation */
00807   return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE);
00808 }
00809
00810 /**
00811   * @brief  Retrieve operation result.
00812   * @param  hpka PKA handle
00813   * @param  pRes Output buffer
00814   * @retval HAL status
00815   */
00816 void HAL_PKA_ModExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes)
00817 {
00818   uint32_t size;
00819
00820   /* Indicate to the user the final size */
00821   size = (hpka->Instance->RAM[PKA_MODULAR_EXP_IN_OP_NB_BITS] + 7UL) / 8UL;
00822
00823   /* Move the result to appropriate location (indicated in out parameter) */
00824   PKA_Memcpy_u32_to_u8(pRes, &hpka->Instance->RAM[PKA_MODULAR_EXP_OUT_SM_ALGO_ACC1], size);
00825 }
00826
00827 /**
00828   * @brief  Sign a message using elliptic curves over prime fields in blocking mode.
00829   * @param  hpka PKA handle
00830   * @param  in Input information
00831   * @param  Timeout Timeout duration
00832   * @retval HAL status
00833   */
00834 HAL_StatusTypeDef HAL_PKA_ECDSASign(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in, uint32_t Timeout)
00835 {
00836   /* Set input parameter in PKA RAM */
00837   PKA_ECDSASign_Set(hpka, in);
00838
00839   /* Start the operation */
00840   return PKA_Process(hpka, PKA_MODE_ECDSA_SIGNATURE, Timeout);
00841 }
00842
00843 /**
00844   * @brief  Sign a message using elliptic curves over prime fields in non-blocking mode with Interrupt.
00845   * @param  hpka PKA handle
00846   * @param  in Input information
00847   * @retval HAL status
00848   */
00849 HAL_StatusTypeDef HAL_PKA_ECDSASign_IT(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in)
00850 {
00851   /* Set input parameter in PKA RAM */
00852   PKA_ECDSASign_Set(hpka, in);
00853
00854   /* Start the operation */
00855   return PKA_Process_IT(hpka, PKA_MODE_ECDSA_SIGNATURE);
00856 }
00857
00858 /**
00859   * @brief  Retrieve operation result.
00860   * @param  hpka PKA handle
00861   * @param  out Output information
00862   * @param  outExt Additionnal Output information (facultative)
00863   */
00864 void HAL_PKA_ECDSASign_GetResult(PKA_HandleTypeDef *hpka, PKA_ECDSASignOutTypeDef *out, PKA_ECDSASignOutExtParamTypeDef *outExt)
00865 {
00866   uint32_t size;
00867
00868   size = (hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_MOD_NB_BITS] + 7UL) / 8UL;
00869
00870   if (out != NULL)
00871   {
00872     PKA_Memcpy_u32_to_u8(out->RSign, &hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_R], size);
00873     PKA_Memcpy_u32_to_u8(out->SSign, &hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_S], size);
00874   }
00875
00876   /* If user requires the additionnal information */
00877   if (outExt != NULL)
00878   {
00879     /* Move the result to appropriate location (indicated in outExt parameter) */
00880     PKA_Memcpy_u32_to_u8(outExt->ptX, &hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_FINAL_POINT_X], size);
00881     PKA_Memcpy_u32_to_u8(outExt->ptY, &hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y], size);
00882   }
00883 }
00884
00885 /**
00886   * @brief  Verify the validity of a signature using elliptic curves over prime fields in blocking mode.
00887   * @param  hpka PKA handle
00888   * @param  in Input information
00889   * @param  Timeout Timeout duration
00890   * @retval HAL status
00891   */
00892 HAL_StatusTypeDef HAL_PKA_ECDSAVerif(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in, uint32_t Timeout)
00893 {
00894   /* Set input parameter in PKA RAM */
00895   PKA_ECDSAVerif_Set(hpka, in);
00896
00897   /* Start the operation */
00898   return PKA_Process(hpka, PKA_MODE_ECDSA_VERIFICATION, Timeout);
00899 }
00900
00901 /**
00902   * @brief  Verify the validity of a signature using elliptic curves over prime fields in non-blocking mode with Interrupt.
00903   * @param  hpka PKA handle
00904   * @param  in Input information
00905   * @retval HAL status
00906   */
00907 HAL_StatusTypeDef HAL_PKA_ECDSAVerif_IT(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in)
00908 {
00909   /* Set input parameter in PKA RAM */
00910   PKA_ECDSAVerif_Set(hpka, in);
00911
00912   /* Start the operation */
00913   return PKA_Process_IT(hpka, PKA_MODE_ECDSA_VERIFICATION);
00914 }
00915
00916 /**
00917   * @brief  Return the result of the ECDSA verification operation.
00918   * @param  hpka PKA handle
00919   * @retval 1 if signature is verified, 0 in other case
00920   */
00921 uint32_t HAL_PKA_ECDSAVerif_IsValidSignature(PKA_HandleTypeDef const *const hpka)
00922 {
00923   /* Invert the state of the PKA RAM bit containing the result of the operation */
00924   return (hpka->Instance->RAM[PKA_ECDSA_VERIF_OUT_RESULT] == 0UL) ? 1UL : 0UL;
00925 }
00926
00927 /**
00928   * @brief  RSA CRT exponentiation in blocking mode.
00929   * @param  hpka PKA handle
00930   * @param  in Input information
00931   * @param  Timeout Timeout duration
00932   * @retval HAL status
00933   */
00934 HAL_StatusTypeDef HAL_PKA_RSACRTExp(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in, uint32_t Timeout)
00935 {
00936   /* Set input parameter in PKA RAM */
00937   PKA_RSACRTExp_Set(hpka, in);
00938
00939   /* Start the operation */
00940   return PKA_Process(hpka, PKA_MODE_RSA_CRT_EXP, Timeout);
00941 }
00942
00943 /**
00944   * @brief  RSA CRT exponentiation in non-blocking mode with Interrupt.
00945   * @param  hpka PKA handle
00946   * @param  in Input information
00947   * @retval HAL status
00948   */
00949 HAL_StatusTypeDef HAL_PKA_RSACRTExp_IT(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in)
00950 {
00951   /* Set input parameter in PKA RAM */
00952   PKA_RSACRTExp_Set(hpka, in);
00953
00954   /* Start the operation */
00955   return PKA_Process_IT(hpka, PKA_MODE_RSA_CRT_EXP);
00956 }
00957
00958 /**
00959   * @brief  Retrieve operation result.
00960   * @param  hpka PKA handle
00961   * @param  pRes Pointer to memory location to receive the result of the operation
00962   * @retval HAL status
00963   */
00964 void HAL_PKA_RSACRTExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes)
00965 {
00966   uint32_t size;
00967
00968   /* Move the result to appropriate location (indicated in out parameter) */
00969   size = (hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_MOD_NB_BITS] + 7UL) / 8UL;
00970
00971   PKA_Memcpy_u32_to_u8(pRes, &hpka->Instance->RAM[PKA_RSA_CRT_EXP_OUT_RESULT], size);
00972 }
00973
00974 /**
00975   * @brief  Point on elliptic curve check in blocking mode.
00976   * @param  hpka PKA handle
00977   * @param  in Input information
00978   * @param  Timeout Timeout duration
00979   * @retval HAL status
00980   */
00981 HAL_StatusTypeDef HAL_PKA_PointCheck(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in, uint32_t Timeout)
00982 {
00983   /* Set input parameter in PKA RAM */
00984   PKA_PointCheck_Set(hpka, in);
00985
00986   /* Start the operation */
00987   return PKA_Process(hpka, PKA_MODE_POINT_CHECK, Timeout);
00988 }
00989
00990 /**
00991   * @brief  Point on elliptic curve check in non-blocking mode with Interrupt.
00992   * @param  hpka PKA handle
00993   * @param  in Input information
00994   * @retval HAL status
00995   */
00996 HAL_StatusTypeDef HAL_PKA_PointCheck_IT(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in)
00997 {
00998   /* Set input parameter in PKA RAM */
00999   PKA_PointCheck_Set(hpka, in);
01000
01001   /* Start the operation */
01002   return PKA_Process_IT(hpka, PKA_MODE_POINT_CHECK);
01003 }
01004
01005 /**
01006   * @brief  Return the result of the point check operation.
01007   * @param  hpka PKA handle
01008   * @retval 1 if point is on curve, 0 in other case
01009   */
01010 uint32_t HAL_PKA_PointCheck_IsOnCurve(PKA_HandleTypeDef const *const hpka)
01011 {
01012   /* Invert the value of the PKA RAM containig the result of the operation */
01013   return (hpka->Instance->RAM[PKA_POINT_CHECK_OUT_ERROR] == 0UL) ? 1UL : 0UL;
01014 }
01015
01016 /**
01017   * @brief  ECC scalar multiplication in blocking mode.
01018   * @param  hpka PKA handle
01019   * @param  in Input information
01020   * @param  Timeout Timeout duration
01021   * @retval HAL status
01022   */
01023 HAL_StatusTypeDef HAL_PKA_ECCMul(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in, uint32_t Timeout)
01024 {
01025   /* Set input parameter in PKA RAM */
01026   PKA_ECCMul_Set(hpka, in);
01027
01028   /* Start the operation */
01029   return PKA_Process(hpka, PKA_MODE_ECC_MUL, Timeout);
01030 }
01031
01032 /**
01033   * @brief  ECC scalar multiplication in non-blocking mode with Interrupt.
01034   * @param  hpka PKA handle
01035   * @param  in Input information
01036   * @retval HAL status
01037   */
01038 HAL_StatusTypeDef HAL_PKA_ECCMul_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in)
01039 {
01040   /* Set input parameter in PKA RAM */
01041   PKA_ECCMul_Set(hpka, in);
01042
01043   /* Start the operation */
01044   return PKA_Process_IT(hpka, PKA_MODE_ECC_MUL);
01045 }
01046
01047 /**
01048   * @brief  ECC scalar multiplication in blocking mode.
01049   * @param  hpka PKA handle
01050   * @param  in Input information
01051   * @param  Timeout Timeout duration
01052   * @retval HAL status
01053   */
01054 HAL_StatusTypeDef HAL_PKA_ECCMulFastMode(PKA_HandleTypeDef *hpka, PKA_ECCMulFastModeInTypeDef *in, uint32_t Timeout)
01055 {
01056   /* Set input parameter in PKA RAM */
01057   PKA_ECCMulFastMode_Set(hpka, in);
01058
01059   /* Start the operation */
01060   return PKA_Process(hpka, PKA_MODE_ECC_MUL_FAST_MODE, Timeout);
01061 }
01062
01063 /**
01064   * @brief  ECC scalar multiplication in non-blocking mode with Interrupt.
01065   * @param  hpka PKA handle
01066   * @param  in Input information
01067   * @retval HAL status
01068   */
01069 HAL_StatusTypeDef HAL_PKA_ECCMulFastMode_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulFastModeInTypeDef *in)
01070 {
01071   /* Set input parameter in PKA RAM */
01072   PKA_ECCMulFastMode_Set(hpka, in);
01073
01074   /* Start the operation */
01075   return PKA_Process_IT(hpka, PKA_MODE_ECC_MUL_FAST_MODE);
01076 }
01077
01078 /**
01079   * @brief  Retrieve operation result.
01080   * @param  hpka PKA handle
01081   * @param  out Output information
01082   * @retval HAL status
01083   */
01084 void HAL_PKA_ECCMul_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCMulOutTypeDef *out)
01085 {
01086   uint32_t size;
01087
01088   /* Retrieve the size of the array from the PKA RAM */
01089   size = (hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS] + 7UL) / 8UL;
01090
01091   /* If a destination buffer is provided */
01092   if (out != NULL)
01093   {
01094     /* Move the result to appropriate location (indicated in out parameter) */
01095     PKA_Memcpy_u32_to_u8(out->ptX, &hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_X], size);
01096     PKA_Memcpy_u32_to_u8(out->ptY, &hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y], size);
01097   }
01098 }
01099
01100 /**
01101   * @brief  Arithmetic addition in blocking mode.
01102   * @param  hpka PKA handle
01103   * @param  in Input information
01104   * @param  Timeout Timeout duration
01105   * @retval HAL status
01106   */
01107 HAL_StatusTypeDef HAL_PKA_Add(PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in, uint32_t Timeout)
01108 {
01109   /* Set input parameter in PKA RAM */
01110   PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL);
01111
01112   /* Start the operation */
01113   return PKA_Process(hpka, PKA_MODE_ARITHMETIC_ADD, Timeout);
01114 }
01115
01116 /**
01117   * @brief  Arithmetic addition in non-blocking mode with Interrupt.
01118   * @param  hpka PKA handle
01119   * @param  in Input information
01120   * @retval HAL status
01121   */
01122 HAL_StatusTypeDef HAL_PKA_Add_IT(PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in)
01123 {
01124   /* Set input parameter in PKA RAM */
01125   PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL);
01126
01127   /* Start the operation */
01128   return PKA_Process_IT(hpka, PKA_MODE_ARITHMETIC_ADD);
01129 }
01130
01131 /**
01132   * @brief  Arithmetic substraction in blocking mode.
01133   * @param  hpka PKA handle
01134   * @param  in Input information
01135   * @param  Timeout Timeout duration
01136   * @retval HAL status
01137   */
01138 HAL_StatusTypeDef HAL_PKA_Sub(PKA_HandleTypeDef *hpka, PKA_SubInTypeDef *in, uint32_t Timeout)
01139 {
01140   /* Set input parameter in PKA RAM */
01141   PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL);
01142
01143   /* Start the operation */
01144   return PKA_Process(hpka, PKA_MODE_ARITHMETIC_SUB, Timeout);
01145 }
01146
01147 /**
01148   * @brief  Arithmetic substraction in non-blocking mode with Interrupt.
01149   * @param  hpka PKA handle
01150   * @param  in Input information
01151   * @retval HAL status
01152   */
01153 HAL_StatusTypeDef HAL_PKA_Sub_IT(PKA_HandleTypeDef *hpka, PKA_SubInTypeDef *in)
01154 {
01155   /* Set input parameter in PKA RAM */
01156   PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL);
01157
01158   /* Start the operation */
01159   return PKA_Process_IT(hpka, PKA_MODE_ARITHMETIC_SUB);
01160 }
01161
01162 /**
01163   * @brief  Arithmetic multiplication in blocking mode.
01164   * @param  hpka PKA handle
01165   * @param  in Input information
01166   * @param  Timeout Timeout duration
01167   * @retval HAL status
01168   */
01169 HAL_StatusTypeDef HAL_PKA_Mul(PKA_HandleTypeDef *hpka, PKA_MulInTypeDef *in, uint32_t Timeout)
01170 {
01171   /* Set input parameter in PKA RAM */
01172   PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL);
01173
01174   /* Start the operation */
01175   return PKA_Process(hpka, PKA_MODE_ARITHMETIC_MUL, Timeout);
01176 }
01177
01178 /**
01179   * @brief  Arithmetic multiplication in non-blocking mode with Interrupt.
01180   * @param  hpka PKA handle
01181   * @param  in Input information
01182   * @retval HAL status
01183   */
01184 HAL_StatusTypeDef HAL_PKA_Mul_IT(PKA_HandleTypeDef *hpka, PKA_MulInTypeDef *in)
01185 {
01186   /* Set input parameter in PKA RAM */
01187   PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL);
01188
01189   /* Start the operation */
01190   return PKA_Process_IT(hpka, PKA_MODE_ARITHMETIC_MUL);
01191 }
01192
01193 /**
01194   * @brief  Comparison in blocking mode.
01195   * @param  hpka PKA handle
01196   * @param  in Input information
01197   * @param  Timeout Timeout duration
01198   * @retval HAL status
01199   */
01200 HAL_StatusTypeDef HAL_PKA_Cmp(PKA_HandleTypeDef *hpka, PKA_CmpInTypeDef *in, uint32_t Timeout)
01201 {
01202   /* Set input parameter in PKA RAM */
01203   PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL);
01204
01205   /* Start the operation */
01206   return PKA_Process(hpka, PKA_MODE_COMPARISON, Timeout);
01207 }
01208
01209 /**
01210   * @brief  Comparison in non-blocking mode with Interrupt.
01211   * @param  hpka PKA handle
01212   * @param  in Input information
01213   * @retval HAL status
01214   */
01215 HAL_StatusTypeDef HAL_PKA_Cmp_IT(PKA_HandleTypeDef *hpka, PKA_CmpInTypeDef *in)
01216 {
01217   /* Set input parameter in PKA RAM */
01218   PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL);
01219
01220   /* Start the operation */
01221   return PKA_Process_IT(hpka, PKA_MODE_COMPARISON);
01222 }
01223
01224 /**
01225   * @brief  Modular addition in blocking mode.
01226   * @param  hpka PKA handle
01227   * @param  in Input information
01228   * @param  Timeout Timeout duration
01229   * @retval HAL status
01230   */
01231 HAL_StatusTypeDef HAL_PKA_ModAdd(PKA_HandleTypeDef *hpka, PKA_ModAddInTypeDef *in, uint32_t Timeout)
01232 {
01233   /* Set input parameter in PKA RAM */
01234   PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, in->pOp3);
01235
01236   /* Start the operation */
01237   return PKA_Process(hpka, PKA_MODE_MODULAR_ADD, Timeout);
01238 }
01239
01240 /**
01241   * @brief  Modular addition in non-blocking mode with Interrupt.
01242   * @param  hpka PKA handle
01243   * @param  in Input information
01244   * @retval HAL status
01245   */
01246 HAL_StatusTypeDef HAL_PKA_ModAdd_IT(PKA_HandleTypeDef *hpka, PKA_ModAddInTypeDef *in)
01247 {
01248   /* Set input parameter in PKA RAM */
01249   PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, in->pOp3);
01250
01251   /* Start the operation */
01252   return PKA_Process_IT(hpka, PKA_MODE_MODULAR_ADD);
01253 }
01254
01255 /**
01256   * @brief  Modular inversion in blocking mode.
01257   * @param  hpka PKA handle
01258   * @param  in Input information
01259   * @param  Timeout Timeout duration
01260   * @retval HAL status
01261   */
01262 HAL_StatusTypeDef HAL_PKA_ModInv(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in, uint32_t Timeout)
01263 {
01264   /* Set input parameter in PKA RAM */
01265   PKA_ModInv_Set(hpka, in);
01266
01267   /* Start the operation */
01268   return PKA_Process(hpka, PKA_MODE_MODULAR_INV, Timeout);
01269 }
01270
01271 /**
01272   * @brief  Modular inversion in non-blocking mode with Interrupt.
01273   * @param  hpka PKA handle
01274   * @param  in Input information
01275   * @retval HAL status
01276   */
01277 HAL_StatusTypeDef HAL_PKA_ModInv_IT(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in)
01278 {
01279   /* Set input parameter in PKA RAM */
01280   PKA_ModInv_Set(hpka, in);
01281
01282   /* Start the operation */
01283   return PKA_Process_IT(hpka, PKA_MODE_MODULAR_INV);
01284 }
01285
01286 /**
01287   * @brief  Modular substraction in blocking mode.
01288   * @param  hpka PKA handle
01289   * @param  in Input information
01290   * @param  Timeout Timeout duration
01291   * @retval HAL status
01292   */
01293 HAL_StatusTypeDef HAL_PKA_ModSub(PKA_HandleTypeDef *hpka, PKA_ModSubInTypeDef *in, uint32_t Timeout)
01294 {
01295   /* Set input parameter in PKA RAM */
01296   PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, in->pOp3);
01297
01298   /* Start the operation */
01299   return PKA_Process(hpka, PKA_MODE_MODULAR_SUB, Timeout);
01300 }
01301
01302 /**
01303   * @brief  Modular substraction in non-blocking mode with Interrupt.
01304   * @param  hpka PKA handle
01305   * @param  in Input information
01306   * @retval HAL status
01307   */
01308 HAL_StatusTypeDef HAL_PKA_ModSub_IT(PKA_HandleTypeDef *hpka, PKA_ModSubInTypeDef *in)
01309 {
01310   /* Set input parameter in PKA RAM */
01311   PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, in->pOp3);
01312
01313   /* Start the operation */
01314   return PKA_Process_IT(hpka, PKA_MODE_MODULAR_SUB);
01315 }
01316
01317 /**
01318   * @brief  Modular reduction in blocking mode.
01319   * @param  hpka PKA handle
01320   * @param  in Input information
01321   * @param  Timeout Timeout duration
01322   * @retval HAL status
01323   */
01324 HAL_StatusTypeDef HAL_PKA_ModRed(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in, uint32_t Timeout)
01325 {
01326   /* Set input parameter in PKA RAM */
01327   PKA_ModRed_Set(hpka, in);
01328
01329   /* Start the operation */
01330   return PKA_Process(hpka, PKA_MODE_MODULAR_RED, Timeout);
01331 }
01332
01333 /**
01334   * @brief  Modular reduction in non-blocking mode with Interrupt.
01335   * @param  hpka PKA handle
01336   * @param  in Input information
01337   * @retval HAL status
01338   */
01339 HAL_StatusTypeDef HAL_PKA_ModRed_IT(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in)
01340 {
01341   /* Set input parameter in PKA RAM */
01342   PKA_ModRed_Set(hpka, in);
01343
01344   /* Start the operation */
01345   return PKA_Process_IT(hpka, PKA_MODE_MODULAR_RED);
01346 }
01347
01348 /**
01349   * @brief  Montgomery multiplication in blocking mode.
01350   * @param  hpka PKA handle
01351   * @param  in Input information
01352   * @param  Timeout Timeout duration
01353   * @retval HAL status
01354   */
01355 HAL_StatusTypeDef HAL_PKA_MontgomeryMul(PKA_HandleTypeDef *hpka, PKA_MontgomeryMulInTypeDef *in, uint32_t Timeout)
01356 {
01357   /* Set input parameter in PKA RAM */
01358   PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, in->pOp3);
01359
01360   /* Start the operation */
01361   return PKA_Process(hpka, PKA_MODE_MONTGOMERY_MUL, Timeout);
01362 }
01363
01364 /**
01365   * @brief  Montgomery multiplication in non-blocking mode with Interrupt.
01366   * @param  hpka PKA handle
01367   * @param  in Input information
01368   * @retval HAL status
01369   */
01370 HAL_StatusTypeDef HAL_PKA_MontgomeryMul_IT(PKA_HandleTypeDef *hpka, PKA_MontgomeryMulInTypeDef *in)
01371 {
01372   /* Set input parameter in PKA RAM */
01373   PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, in->pOp3);
01374
01375   /* Start the operation */
01376   return PKA_Process_IT(hpka, PKA_MODE_MONTGOMERY_MUL);
01377 }
01378
01379 /**
01380   * @brief  Retrieve operation result.
01381   * @param  hpka PKA handle
01382   * @param  pRes Pointer to memory location to receive the result of the operation
01383   */
01384 void HAL_PKA_Arithmetic_GetResult(PKA_HandleTypeDef *hpka, uint32_t *pRes)
01385 {
01386   uint32_t mode = (hpka->Instance->CR & PKA_CR_MODE_Msk) >> PKA_CR_MODE_Pos;
01387   uint32_t size = 0;
01388
01389   /* Move the result to appropriate location (indicated in pRes parameter) */
01390   switch (mode)
01391   {
01392     case PKA_MODE_ARITHMETIC_SUB:
01393     case PKA_MODE_MODULAR_ADD:
01394     case PKA_MODE_MODULAR_RED:
01395     case PKA_MODE_MODULAR_INV:
01396     case PKA_MODE_MODULAR_SUB:
01397     case PKA_MODE_MONTGOMERY_MUL:
01398       size = hpka->Instance->RAM[1] / 32UL;
01399       break;
01400     case PKA_MODE_ARITHMETIC_ADD:
01401       size = hpka->Instance->RAM[1] / 32UL;
01402
01403       /* Manage the overflow of the addition */
01404       if (hpka->Instance->RAM[500U + size] != 0UL)
01405       {
01406         size += 1UL;
01407       }
01408
01409       break;
01410     case PKA_MODE_COMPARISON:
01411       size = 1;
01412       break;
01413     case PKA_MODE_ARITHMETIC_MUL:
01414       size = hpka->Instance->RAM[1] / 32UL * 2UL;
01415       break;
01416     default:
01417       break;
01418   }
01419
01420   if (pRes != NULL)
01421   {
01422     switch (mode)
01423     {
01424       case PKA_MODE_ARITHMETIC_SUB:
01425       case PKA_MODE_MODULAR_ADD:
01426       case PKA_MODE_MODULAR_RED:
01427       case PKA_MODE_MODULAR_INV:
01428       case PKA_MODE_MODULAR_SUB:
01429       case PKA_MODE_MONTGOMERY_MUL:
01430       case PKA_MODE_ARITHMETIC_ADD:
01431       case PKA_MODE_COMPARISON:
01432       case PKA_MODE_ARITHMETIC_MUL:
01433         PKA_Memcpy_u32_to_u32(pRes, &hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_OUT_RESULT], size);
01434         break;
01435       default:
01436         break;
01437     }
01438   }
01439 }
01440
01441 /**
01442   * @brief  Montgomery parameter computation in blocking mode.
01443   * @param  hpka PKA handle
01444   * @param  in Input information
01445   * @param  Timeout Timeout duration
01446   * @retval HAL status
01447   */
01448 HAL_StatusTypeDef HAL_PKA_MontgomeryParam(PKA_HandleTypeDef *hpka, PKA_MontgomeryParamInTypeDef *in, uint32_t Timeout)
01449 {
01450   /* Set input parameter in PKA RAM */
01451   PKA_MontgomeryParam_Set(hpka, in->size, in->pOp1);
01452
01453   /* Start the operation */
01454   return PKA_Process(hpka, PKA_MODE_MONTGOMERY_PARAM, Timeout);
01455 }
01456
01457 /**
01458   * @brief  Montgomery parameter computation in non-blocking mode with Interrupt.
01459   * @param  hpka PKA handle
01460   * @param  in Input information
01461   * @retval HAL status
01462   */
01463 HAL_StatusTypeDef HAL_PKA_MontgomeryParam_IT(PKA_HandleTypeDef *hpka, PKA_MontgomeryParamInTypeDef *in)
01464 {
01465   /* Set input parameter in PKA RAM */
01466   PKA_MontgomeryParam_Set(hpka, in->size, in->pOp1);
01467
01468   /* Start the operation */
01469   return PKA_Process_IT(hpka, PKA_MODE_MONTGOMERY_PARAM);
01470 }
01471
01472 /**
01473   * @brief  Retrieve operation result.
01474   * @param  hpka PKA handle
01475   * @param  pRes pointer to buffer where the result will be copied
01476   * @retval HAL status
01477   */
01478 void HAL_PKA_MontgomeryParam_GetResult(PKA_HandleTypeDef *hpka, uint32_t *pRes)
01479 {
01480   uint32_t size;
01481
01482   /* Retrieve the size of the buffer from the PKA RAM */
01483   size = (hpka->Instance->RAM[PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS] + 31UL) / 32UL;
01484
01485   /* Move the result to appropriate location (indicated in out parameter) */
01486   PKA_Memcpy_u32_to_u32(pRes, &hpka->Instance->RAM[PKA_MONTGOMERY_PARAM_OUT_PARAMETER], size);
01487 }
01488
01489 /**
01490   * @brief  Abort any ongoing operation.
01491   * @param  hpka PKA handle
01492   * @retval HAL status
01493   */
01494 HAL_StatusTypeDef HAL_PKA_Abort(PKA_HandleTypeDef *hpka)
01495 {
01496   HAL_StatusTypeDef err = HAL_OK;
01497
01498   /* Clear EN bit */
01499   /* This abort any operation in progress (PKA RAM content is not guaranted in this case) */
01500   CLEAR_BIT(hpka->Instance->CR, PKA_CR_EN);
01501   SET_BIT(hpka->Instance->CR, PKA_CR_EN);
01502
01503   /* Reset any pending flag */
01504   SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC);
01505
01506   /* Reset the error code */
01507   hpka->ErrorCode = HAL_PKA_ERROR_NONE;
01508
01509   /* Reset the state */
01510   hpka->State = HAL_PKA_STATE_READY;
01511
01512   return err;
01513 }
01514
01515 /**
01516   * @brief  Reset the PKA RAM.
01517   * @param  hpka PKA handle
01518   * @retval None
01519   */
01520 void HAL_PKA_RAMReset(PKA_HandleTypeDef *hpka)
01521 {
01522   uint32_t index;
01523
01524   /* For each element in the PKA RAM */
01525   for (index = 0; index < PKA_RAM_SIZE; index++)
01526   {
01527     /* Clear the content */
01528     hpka->Instance->RAM[index] = 0UL;
01529   }
01530 }
01531
01532 /**
01533   * @brief  This function handles PKA event interrupt request.
01534   * @param  hpka PKA handle
01535   * @retval None
01536   */
01537 void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka)
01538 {
01539   uint32_t mode = PKA_GetMode(hpka);
01540   FlagStatus addErrFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_ADDRERR);
01541   FlagStatus ramErrFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_RAMERR);
01542   FlagStatus procEndFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_PROCEND);
01543
01544   /* Address error interrupt occurred */
01545   if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_IT_ADDRERR) == SET) && (addErrFlag == SET))
01546   {
01547     hpka->ErrorCode |= HAL_PKA_ERROR_ADDRERR;
01548
01549     /* Clear ADDRERR flag */
01550     __HAL_PKA_CLEAR_FLAG(hpka, PKA_FLAG_ADDRERR);
01551   }
01552
01553   /* RAM access error interrupt occurred */
01554   if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_IT_RAMERR) == SET) && (ramErrFlag == SET))
01555   {
01556     hpka->ErrorCode |= HAL_PKA_ERROR_RAMERR;
01557
01558     /* Clear RAMERR flag */
01559     __HAL_PKA_CLEAR_FLAG(hpka, PKA_FLAG_RAMERR);
01560   }
01561
01562   /* Check the operation success in case of ECDSA signature */
01563   if (mode == PKA_MODE_ECDSA_SIGNATURE)
01564   {
01565     /* If error output result is different from 0, ecdsa sign operation need to be repeated */
01566     if (hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_ERROR] != 0UL)
01567     {
01568       hpka->ErrorCode |= HAL_PKA_ERROR_OPERATION;
01569     }
01570   }
01571
01572   /* Trigger the error callback if an error is present */
01573   if (hpka->ErrorCode != HAL_PKA_ERROR_NONE)
01574   {
01575 #if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
01576     hpka->ErrorCallback(hpka);
01577 #else
01578     HAL_PKA_ErrorCallback(hpka);
01579 #endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
01580   }
01581
01582   /* End Of Operation interrupt occurred */
01583   if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_IT_PROCEND) == SET) && (procEndFlag == SET))
01584   {
01585     /* Clear PROCEND flag */
01586     __HAL_PKA_CLEAR_FLAG(hpka, PKA_FLAG_PROCEND);
01587
01588     /* Set the state to ready */
01589     hpka->State = HAL_PKA_STATE_READY;
01590
01591 #if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
01592     hpka->OperationCpltCallback(hpka);
01593 #else
01594     HAL_PKA_OperationCpltCallback(hpka);
01595 #endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
01596   }
01597 }
01598
01599 /**
01600   * @brief  Process completed callback.
01601   * @param  hpka PKA handle
01602   * @retval None
01603   */
01604 __weak void HAL_PKA_OperationCpltCallback(PKA_HandleTypeDef *hpka)
01605 {
01606   /* Prevent unused argument(s) compilation warning */
01607   UNUSED(hpka);
01608
01609   /* NOTE : This function should not be modified, when the callback is needed,
01610             the HAL_PKA_OperationCpltCallback could be implemented in the user file
01611    */
01612 }
01613
01614 /**
01615   * @brief  Error callback.
01616   * @param  hpka PKA handle
01617   * @retval None
01618   */
01619 __weak void HAL_PKA_ErrorCallback(PKA_HandleTypeDef *hpka)
01620 {
01621   /* Prevent unused argument(s) compilation warning */
01622   UNUSED(hpka);
01623
01624   /* NOTE : This function should not be modified, when the callback is needed,
01625             the HAL_PKA_ErrorCallback could be implemented in the user file
01626    */
01627 }
01628
01629 /**
01630   * @}
01631   */
01632
01633 /** @defgroup PKA_Exported_Functions_Group3 Peripheral State and Error functions
01634  *  @brief   Peripheral State and Error functions
01635  *
01636   @verbatim
01637  ===============================================================================
01638             ##### Peripheral State and Error functions #####
01639  ===============================================================================
01640     [..]
01641     This subsection permit to get in run-time the status of the peripheral.
01642
01643 @endverbatim
01644   * @{
01645   */
01646
01647 /**
01648   * @brief  Return the PKA handle state.
01649   * @param  hpka PKA handle
01650   * @retval HAL status
01651   */
01652 HAL_PKA_StateTypeDef HAL_PKA_GetState(PKA_HandleTypeDef *hpka)
01653 {
01654   /* Return PKA handle state */
01655   return hpka->State;
01656 }
01657
01658 /**
01659   * @brief  Return the PKA error code.
01660   * @param  hpka PKA handle
01661   * @retval PKA error code
01662 */
01663 uint32_t HAL_PKA_GetError(PKA_HandleTypeDef *hpka)
01664 {
01665   /* Return PKA handle error code */
01666   return hpka->ErrorCode;
01667 }
01668
01669 /**
01670   * @}
01671   */
01672
01673 /**
01674   * @}
01675   */
01676
01677 /** @addtogroup PKA_Private_Functions
01678   * @{
01679   */
01680
01681 /**
01682   * @brief  Get PKA operating mode.
01683   * @param  hpka PKA handle
01684   * @retval Return the current mode
01685   */
01686 uint32_t PKA_GetMode(PKA_HandleTypeDef *hpka)
01687 {
01688   /* return the shifted PKA_CR_MODE value */
01689   return (uint32_t)(READ_BIT(hpka->Instance->CR, PKA_CR_MODE) >> PKA_CR_MODE_Pos);
01690 }
01691
01692 /**
01693   * @brief  Wait for operation completion or timeout.
01694   * @param  hpka PKA handle
01695   * @param  Timeout Timeout duration in millisecond.
01696   * @param  Tickstart Tick start value
01697   * @retval HAL status
01698   */
01699 HAL_StatusTypeDef PKA_PollEndOfOperation(PKA_HandleTypeDef *hpka, uint32_t Timeout, uint32_t Tickstart)
01700 {
01701   /* Wait for the end of operation or timeout */
01702   while ((hpka->Instance->SR & PKA_SR_PROCENDF) == 0UL)
01703   {
01704     /* Check if timeout is disabled (set to infinite wait) */
01705     if (Timeout != HAL_MAX_DELAY)
01706     {
01707       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0UL))
01708       {
01709         return HAL_TIMEOUT;
01710       }
01711     }
01712   }
01713   return HAL_OK;
01714 }
01715
01716 /**
01717   * @brief  Return a hal error code based on PKA error flags.
01718   * @param  hpka PKA handle
01719   * @param  mode PKA operating mode
01720   * @retval error code
01721   */
01722 uint32_t PKA_CheckError(PKA_HandleTypeDef *hpka, uint32_t mode)
01723 {
01724   uint32_t err = HAL_PKA_ERROR_NONE;
01725
01726   /* Check RAMERR error */
01727   if (__HAL_PKA_GET_FLAG(hpka, PKA_FLAG_RAMERR) == SET)
01728   {
01729     err |= HAL_PKA_ERROR_RAMERR;
01730   }
01731
01732   /* Check ADDRERR error */
01733   if (__HAL_PKA_GET_FLAG(hpka, PKA_FLAG_ADDRERR) == SET)
01734   {
01735     err |= HAL_PKA_ERROR_ADDRERR;
01736   }
01737
01738   /* Check the operation success in case of ECDSA signature */
01739   if (mode == PKA_MODE_ECDSA_SIGNATURE)
01740   {
01741     /* If error output result is different from 0, ecsa sign operation need to be repeated */
01742     if (hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_ERROR] != 0UL)
01743     {
01744       err |= HAL_PKA_ERROR_OPERATION;
01745     }
01746   }
01747
01748   return err;
01749 }
01750
01751 /**
01752   * @brief  Get number of bits inside an array of u8.
01753   * @param  byteNumber Number of u8 inside the array
01754   */
01755 uint32_t PKA_GetBitSize_u8(uint32_t byteNumber)
01756 {
01757   /* Convert from number of uint8_t in an array to the associated number of bits in this array */
01758   return byteNumber * 8UL;
01759 }
01760
01761 /**
01762   * @brief  Get optimal number of bits inside an array of u8.
01763   * @param  byteNumber Number of u8 inside the array
01764   * @param  msb Most significant uint8_t of the array
01765   */
01766 uint32_t PKA_GetOptBitSize_u8(uint32_t byteNumber, uint8_t msb)
01767 {
01768   uint32_t position;
01769
01770   position = 32UL - __CLZ(msb);
01771
01772   return (((byteNumber - 1UL) * 8UL) + position);
01773 }
01774
01775 /**
01776   * @brief  Get number of bits inside an array of u32.
01777   * @param  wordNumber Number of u32 inside the array
01778   */
01779 uint32_t PKA_GetBitSize_u32(uint32_t wordNumber)
01780 {
01781   /* Convert from number of uint32_t in an array to the associated number of bits in this array */
01782   return wordNumber * 32UL;
01783 }
01784
01785 /**
01786   * @brief  Get number of uint8_t element in an array of bitSize bits.
01787   * @param  bitSize Number of bits in an array
01788   */
01789 uint32_t PKA_GetArraySize_u8(uint32_t bitSize)
01790 {
01791   /* Manage the non aligned on uint8_t bitsize: */
01792   /*   512 bits requires 64 uint8_t             */
01793   /*   521 bits requires 66 uint8_t             */
01794   return ((bitSize + 7UL) / 8UL);
01795 }
01796
01797 /**
01798   * @brief  Copy uint32_t array to uint8_t array to fit PKA number representation.
01799   * @param  dst Pointer to destination
01800   * @param  src Pointer to source
01801   * @param  n Number of uint8_t to copy
01802   * @retval dst
01803   */
01804 void PKA_Memcpy_u32_to_u8(uint8_t dst[], __IO const uint32_t src[], size_t n)
01805 {
01806   if (dst != NULL)
01807   {
01808     if (src != NULL)
01809     {
01810       uint32_t index_uint32_t = 0UL; /* This index is used outside of the loop */
01811
01812       for (; index_uint32_t < (n / 4UL); index_uint32_t++)
01813       {
01814         /* Avoid casting from uint8_t* to uint32_t* by copying 4 uint8_t in a row */
01815         /* Apply __REV equivalent */
01816         uint32_t index_uint8_t = n - 4UL - (index_uint32_t * 4UL);
01817         dst[index_uint8_t + 3UL] = (uint8_t)((src[index_uint32_t] & 0x000000FFU));
01818         dst[index_uint8_t + 2UL] = (uint8_t)((src[index_uint32_t] & 0x0000FF00U) >> 8UL);
01819         dst[index_uint8_t + 1UL] = (uint8_t)((src[index_uint32_t] & 0x00FF0000U) >> 16UL);
01820         dst[index_uint8_t + 0UL] = (uint8_t)((src[index_uint32_t] & 0xFF000000U) >> 24UL);
01821       }
01822
01823       /* Manage the buffers not aligned on uint32_t */
01824       if ((n % 4UL) == 1UL)
01825       {
01826         dst[0UL] = (uint8_t)((src[index_uint32_t] & 0x000000FFU));
01827       }
01828       else if ((n % 4UL) == 2UL)
01829       {
01830         dst[1UL] = (uint8_t)((src[index_uint32_t] & 0x000000FFU));
01831         dst[0UL] = (uint8_t)((src[index_uint32_t] & 0x0000FF00U) >> 8UL);
01832       }
01833       else if ((n % 4UL) == 3UL)
01834       {
01835         dst[2UL] = (uint8_t)((src[index_uint32_t] & 0x000000FFU));
01836         dst[1UL] = (uint8_t)((src[index_uint32_t] & 0x0000FF00U) >> 8UL);
01837         dst[0UL] = (uint8_t)((src[index_uint32_t] & 0x00FF0000U) >> 16UL);
01838       }
01839       else
01840       {
01841         /* The last element is already handle in the loop */
01842       }
01843     }
01844   }
01845 }
01846
01847 /**
01848   * @brief  Copy uint8_t array to uint32_t array to fit PKA number representation.
01849   * @param  dst Pointer to destination
01850   * @param  src Pointer to source
01851   * @param  n Number of uint8_t to copy (must be multiple of 4)
01852   * @retval dst
01853   */
01854 void PKA_Memcpy_u8_to_u32(__IO uint32_t dst[], const uint8_t src[], size_t n)
01855 {
01856   if (dst != NULL)
01857   {
01858     if (src != NULL)
01859     {
01860       uint32_t index = 0UL; /* This index is used outside of the loop */
01861
01862       for (; index < (n / 4UL); index++)
01863       {
01864         /* Apply the equivalent of __REV from uint8_t to uint32_t */
01865         dst[index] = ((uint32_t)src[(n - (index * 4UL) - 1UL)]) \
01866                      | ((uint32_t)src[(n - (index * 4UL) - 2UL)] << 8UL) \
01867                      | ((uint32_t)src[(n - (index * 4UL) - 3UL)] << 16UL) \
01868                      | ((uint32_t)src[(n - (index * 4UL) - 4UL)] << 24UL);
01869       }
01870
01871       /* Manage the buffers not aligned on uint32_t */
01872       if ((n % 4UL) == 1UL)
01873       {
01874         dst[index] = (uint32_t)src[(n - (index * 4UL) - 1UL)];
01875       }
01876       else if ((n % 4UL) == 2UL)
01877       {
01878         dst[index] = ((uint32_t)src[(n - (index * 4UL) - 1UL)]) \
01879                      | ((uint32_t)src[(n - (index * 4UL) - 2UL)] << 8UL);
01880       }
01881       else if ((n % 4UL) == 3UL)
01882       {
01883         dst[index] = ((uint32_t)src[(n - (index * 4UL) - 1UL)]) \
01884                      | ((uint32_t)src[(n - (index * 4UL) - 2UL)] << 8UL) \
01885                      | ((uint32_t)src[(n - (index * 4UL) - 3UL)] << 16UL);
01886       }
01887       else
01888       {
01889         /* The last element is already handle in the loop */
01890       }
01891     }
01892   }
01893 }
01894
01895 /**
01896   * @brief  Copy uint32_t array to uint32_t array.
01897   * @param  dst Pointer to destination
01898   * @param  src Pointer to source
01899   * @param  n Number of u32 to be handled
01900   * @retval dst
01901   */
01902 void PKA_Memcpy_u32_to_u32(__IO uint32_t dst[], __IO const uint32_t src[], size_t n)
01903 {
01904   /* If a destination buffer is provided */
01905   if (dst != NULL)
01906   {
01907     /* If a source buffer is provided */
01908     if (src != NULL)
01909     {
01910       /* For each element in the array */
01911       for (uint32_t index = 0UL; index < n; index++)
01912       {
01913         /* Copy the content */
01914         dst[index] = src[index];
01915       }
01916     }
01917   }
01918 }
01919
01920 /**
01921   * @brief  Generic function to start a PKA operation in blocking mode.
01922   * @param  hpka PKA handle
01923   * @param  mode PKA operation
01924   * @param  Timeout Timeout duration
01925   * @retval HAL status
01926   */
01927 HAL_StatusTypeDef PKA_Process(PKA_HandleTypeDef *hpka, uint32_t mode, uint32_t Timeout)
01928 {
01929   HAL_StatusTypeDef err = HAL_OK;
01930   uint32_t tickstart;
01931
01932   if (hpka->State == HAL_PKA_STATE_READY)
01933   {
01934     /* Set the state to busy */
01935     hpka->State = HAL_PKA_STATE_BUSY;
01936
01937     /* Clear any pending error */
01938     hpka->ErrorCode = HAL_PKA_ERROR_NONE;
01939
01940     /* Init tickstart for timeout management*/
01941     tickstart = HAL_GetTick();
01942
01943     /* Set the mode and deactivate the interrupts */
01944     MODIFY_REG(hpka->Instance->CR, PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE, mode << PKA_CR_MODE_Pos);
01945
01946     /* Start the computation */
01947     hpka->Instance->CR |= PKA_CR_START;
01948
01949     /* Wait for the end of operation or timeout */
01950     if (PKA_PollEndOfOperation(hpka, Timeout, tickstart) != HAL_OK)
01951     {
01952       /* Abort any ongoing operation */
01953       CLEAR_BIT(hpka->Instance->CR, PKA_CR_EN);
01954
01955       hpka->ErrorCode |= HAL_PKA_ERROR_TIMEOUT;
01956
01957       /* Make ready for the next operation */
01958       SET_BIT(hpka->Instance->CR, PKA_CR_EN);
01959     }
01960
01961     /* Check error */
01962     hpka->ErrorCode |= PKA_CheckError(hpka, mode);
01963
01964     /* Clear all flags */
01965     hpka->Instance->CLRFR |= (PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC);
01966
01967     /* Set the state to ready */
01968     hpka->State = HAL_PKA_STATE_READY;
01969
01970     /* Manage the result based on encountered errors */
01971     if (hpka->ErrorCode != HAL_PKA_ERROR_NONE)
01972     {
01973       err = HAL_ERROR;
01974     }
01975   }
01976   else
01977   {
01978     err = HAL_ERROR;
01979   }
01980   return err;
01981 }
01982
01983 /**
01984   * @brief  Generic function to start a PKA operation in non-blocking mode with Interrupt.
01985   * @param  hpka PKA handle
01986   * @param  mode PKA operation
01987   * @retval HAL status
01988   */
01989 HAL_StatusTypeDef PKA_Process_IT(PKA_HandleTypeDef *hpka, uint32_t mode)
01990 {
01991   HAL_StatusTypeDef err = HAL_OK;
01992
01993   if (hpka->State == HAL_PKA_STATE_READY)
01994   {
01995     /* Set the state to busy */
01996     hpka->State = HAL_PKA_STATE_BUSY;
01997
01998     /* Clear any pending error */
01999     hpka->ErrorCode = HAL_PKA_ERROR_NONE;
02000
02001     /* Set the mode and activate interrupts */
02002     MODIFY_REG(hpka->Instance->CR, PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE, (mode << PKA_CR_MODE_Pos) | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE);
02003
02004     /* Start the computation */
02005     hpka->Instance->CR |= PKA_CR_START;
02006   }
02007   else
02008   {
02009     err = HAL_ERROR;
02010   }
02011   return err;
02012 }
02013
02014 /**
02015   * @brief  Set input parameters.
02016   * @param  hpka PKA handle
02017   * @param  in Input information
02018   */
02019 void PKA_ModExp_Set(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in)
02020 {
02021   /* Get the number of bit per operand */
02022   hpka->Instance->RAM[PKA_MODULAR_EXP_IN_OP_NB_BITS] = PKA_GetBitSize_u8(in->OpSize);
02023
02024   /* Get the number of bit of the exponent */
02025   hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXP_NB_BITS] = PKA_GetBitSize_u8(in->expSize);
02026
02027   /* Move the input parameters pOp1 to PKA RAM */
02028   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT_BASE], in->pOp1, in->OpSize);
02029   hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT_BASE + (in->OpSize / 4UL)] = 0UL;
02030
02031   /* Move the exponent to PKA RAM */
02032   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT], in->pExp, in->expSize);
02033   hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT + (in->expSize / 4UL)] = 0UL;
02034
02035   /* Move the modulus to PKA RAM */
02036   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MODULUS], in->pMod, in->OpSize);
02037   hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MODULUS + (in->OpSize / 4UL)] = 0UL;
02038 }
02039
02040 /**
02041   * @brief  Set input parameters.
02042   * @param  hpka PKA handle
02043   * @param  in Input information
02044   */
02045 void PKA_ModExpFastMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in)
02046 {
02047   /* Get the number of bit per operand */
02048   hpka->Instance->RAM[PKA_MODULAR_EXP_IN_OP_NB_BITS] = PKA_GetBitSize_u8(in->OpSize);
02049
02050   /* Get the number of bit of the exponent */
02051   hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXP_NB_BITS] = PKA_GetBitSize_u8(in->expSize);
02052
02053   /* Move the input parameters pOp1 to PKA RAM */
02054   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT_BASE], in->pOp1, in->OpSize);
02055   hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT_BASE + (in->OpSize / 4UL)] = 0UL;
02056
02057   /* Move the exponent to PKA RAM */
02058   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT], in->pExp, in->expSize);
02059   hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT + (in->expSize / 4UL)] = 0UL;
02060
02061   /* Move the modulus to PKA RAM */
02062   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MODULUS], in->pMod, in->OpSize);
02063   hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MODULUS + (in->OpSize / 4UL)] = 0UL;
02064
02065   /* Move the Montgomery parameter to PKA RAM */
02066   PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM], in->pMontgomeryParam, in->expSize / 4UL);
02067   hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM + (in->expSize / 4UL)] = 0UL;
02068 }
02069
02070 /**
02071   * @brief  Set input parameters.
02072   * @param  hpka PKA handle
02073   * @param  in Input information
02074   */
02075 void PKA_ECDSASign_Set(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in)
02076 {
02077   /* Get the prime order n length */
02078   hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_ORDER_NB_BITS] = PKA_GetOptBitSize_u8(in->primeOrderSize, *(in->primeOrder));
02079
02080   /* Get the modulus p length */
02081   hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_MOD_NB_BITS] = PKA_GetOptBitSize_u8(in->modulusSize, *(in->modulus));
02082
02083   /* Get the coefficient a sign */
02084   hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_A_COEFF_SIGN] = in->coefSign;
02085
02086   /* Move the input parameters coefficient |a| to PKA RAM */
02087   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_A_COEFF], in->coef, in->modulusSize);
02088   hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL)] = 0UL;
02089
02090   /* Move the input parameters modulus value p to PKA RAM */
02091   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_MOD_GF], in->modulus, in->modulusSize);
02092   hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL)] = 0UL;
02093
02094   /* Move the input parameters integer k to PKA RAM */
02095   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_K], in->integer, in->primeOrderSize);
02096   hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_K + ((in->primeOrderSize + 3UL) / 4UL)] = 0UL;
02097
02098   /* Move the input parameters base point G coordinate x to PKA RAM */
02099   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_INITIAL_POINT_X], in->basePointX, in->modulusSize);
02100   hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL)] = 0UL;
02101
02102   /* Move the input parameters base point G coordinate y to PKA RAM */
02103   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y], in->basePointY, in->modulusSize);
02104   hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL)] = 0UL;
02105
02106   /* Move the input parameters hash of message z to PKA RAM */
02107   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_HASH_E], in->hash, in->primeOrderSize);
02108   hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_HASH_E + ((in->primeOrderSize + 3UL) / 4UL)] = 0UL;
02109
02110   /* Move the input parameters private key d to PKA RAM */
02111   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D], in->privateKey, in->primeOrderSize);
02112   hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + ((in->primeOrderSize + 3UL) / 4UL)] = 0UL;
02113
02114   /* Move the input parameters prime order n to PKA RAM */
02115   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_ORDER_N], in->primeOrder, in->primeOrderSize);
02116   hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_ORDER_N + ((in->primeOrderSize + 3UL) / 4UL)] = 0UL;
02117 }
02118
02119 /**
02120   * @brief  Set input parameters.
02121   * @param  hpka PKA handle
02122   * @param  in Input information
02123   */
02124 void PKA_ECDSAVerif_Set(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in)
02125 {
02126   /* Get the prime order n length */
02127   hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_ORDER_NB_BITS] = PKA_GetOptBitSize_u8(in->primeOrderSize, *(in->primeOrder));
02128
02129   /* Get the modulus p length */
02130   hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_MOD_NB_BITS] = PKA_GetOptBitSize_u8(in->modulusSize, *(in->modulus));
02131
02132   /* Get the coefficient a sign */
02133   hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_A_COEFF_SIGN] = in->coefSign;
02134
02135   /* Move the input parameters coefficient |a| to PKA RAM */
02136   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_A_COEFF], in->coef, in->modulusSize);
02137   hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL)] = 0UL;
02138
02139   /* Move the input parameters modulus value p to PKA RAM */
02140   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_MOD_GF], in->modulus, in->modulusSize);
02141   hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL)] = 0UL;
02142
02143   /* Move the input parameters base point G coordinate x to PKA RAM */
02144   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_INITIAL_POINT_X], in->basePointX, in->modulusSize);
02145   hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL)] = 0UL;
02146
02147   /* Move the input parameters base point G coordinate y to PKA RAM */
02148   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y], in->basePointY, in->modulusSize);
02149   hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL)] = 0UL;
02150
02151   /* Move the input parameters public-key curve point Q coordinate xQ to PKA RAM */
02152   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X], in->pPubKeyCurvePtX, in->modulusSize);
02153   hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X + ((in->modulusSize + 3UL) / 4UL)] = 0UL;
02154
02155   /* Move the input parameters public-key curve point Q coordinate xQ to PKA RAM */
02156   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y], in->pPubKeyCurvePtY, in->modulusSize);
02157   hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y + ((in->modulusSize + 3UL) / 4UL)] = 0UL;
02158
02159   /* Move the input parameters signature part r to PKA RAM */
02160   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_SIGNATURE_R], in->RSign, in->primeOrderSize);
02161   hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_SIGNATURE_R + ((in->primeOrderSize + 3UL) / 4UL)] = 0UL;
02162
02163   /* Move the input parameters signature part s to PKA RAM */
02164   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_SIGNATURE_S], in->SSign, in->primeOrderSize);
02165   hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_SIGNATURE_S + ((in->primeOrderSize + 3UL) / 4UL)] = 0UL;
02166
02167   /* Move the input parameters hash of message z to PKA RAM */
02168   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_HASH_E], in->hash, in->primeOrderSize);
02169   hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_HASH_E + ((in->primeOrderSize + 3UL) / 4UL)] = 0UL;
02170
02171   /* Move the input parameters curve prime order n to PKA RAM */
02172   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_ORDER_N], in->primeOrder, in->primeOrderSize);
02173   hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_ORDER_N + ((in->primeOrderSize + 3UL) / 4UL)] = 0UL;
02174 }
02175
02176 /**
02177   * @brief  Set input parameters.
02178   * @param  hpka PKA handle
02179   * @param  in Input information
02180   */
02181 void PKA_RSACRTExp_Set(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in)
02182 {
02183   /* Get the operand length M */
02184   hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_MOD_NB_BITS] = PKA_GetBitSize_u8(in->size);
02185
02186   /* Move the input parameters operand dP to PKA RAM */
02187   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_DP_CRT], in->pOpDp, in->size / 2UL);
02188   hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_DP_CRT + (in->size / 8UL)] = 0UL;
02189
02190   /* Move the input parameters operand dQ to PKA RAM */
02191   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_DQ_CRT], in->pOpDq, in->size / 2UL);
02192   hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_DQ_CRT + (in->size / 8UL)] = 0UL;
02193
02194   /* Move the input parameters operand qinv to PKA RAM */
02195   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_QINV_CRT], in->pOpQinv, in->size / 2UL);
02196   hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_QINV_CRT + (in->size / 8UL)] = 0UL;
02197
02198   /* Move the input parameters prime p to PKA RAM */
02199   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_PRIME_P], in->pPrimeP, in->size / 2UL);
02200   hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_PRIME_P + (in->size / 8UL)] = 0UL;
02201
02202   /* Move the input parameters prime q to PKA RAM */
02203   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_PRIME_Q], in->pPrimeQ, in->size / 2UL);
02204   hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_PRIME_Q + (in->size / 8UL)] = 0UL;
02205
02206   /* Move the input parameters operand A to PKA RAM */
02207   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_EXPONENT_BASE], in->popA, in->size);
02208   hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_EXPONENT_BASE + (in->size / 4UL)] = 0UL;
02209 }
02210
02211 /**
02212   * @brief  Set input parameters.
02213   * @param  hpka PKA handle
02214   * @param  in Input information
02215   */
02216 void PKA_PointCheck_Set(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in)
02217 {
02218   /* Get the modulus length */
02219   hpka->Instance->RAM[PKA_POINT_CHECK_IN_MOD_NB_BITS] = PKA_GetOptBitSize_u8(in->modulusSize, *(in->modulus));
02220
02221   /* Get the coefficient a sign */
02222   hpka->Instance->RAM[PKA_POINT_CHECK_IN_A_COEFF_SIGN] = in->coefSign;
02223
02224   /* Move the input parameters coefficient |a| to PKA RAM */
02225   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_A_COEFF], in->coefA, in->modulusSize);
02226   hpka->Instance->RAM[PKA_POINT_CHECK_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL)] = 0UL;
02227
02228   /* Move the input parameters coefficient b to PKA RAM */
02229   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_B_COEFF], in->coefB, in->modulusSize);
02230   hpka->Instance->RAM[PKA_POINT_CHECK_IN_B_COEFF + ((in->modulusSize + 3UL) / 4UL)] = 0UL;
02231
02232   /* Move the input parameters modulus value p to PKA RAM */
02233   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_MOD_GF], in->modulus, in->modulusSize);
02234   hpka->Instance->RAM[PKA_POINT_CHECK_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL)] = 0UL;
02235
02236   /* Move the input parameters Point P coordinate x to PKA RAM */
02237   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_X], in->pointX, in->modulusSize);
02238   hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL)] = 0UL;
02239
02240   /* Move the input parameters Point P coordinate y to PKA RAM */
02241   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_Y], in->pointY, in->modulusSize);
02242   hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL)] = 0UL;
02243 }
02244
02245 /**
02246   * @brief  Set input parameters.
02247   * @param  hpka PKA handle
02248   * @param  in Input information
02249   */
02250 void PKA_ECCMul_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in)
02251 {
02252   /* Get the scalar multiplier k length */
02253   hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS] = PKA_GetOptBitSize_u8(in->scalarMulSize, *(in->scalarMul));
02254
02255   /* Get the modulus length */
02256   hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS] = PKA_GetOptBitSize_u8(in->modulusSize, *(in->modulus));
02257
02258   /* Get the coefficient a sign */
02259   hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN] = in->coefSign;
02260
02261   /* Move the input parameters coefficient |a| to PKA RAM */
02262   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF], in->coefA, in->modulusSize);
02263   hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL)] = 0UL;
02264
02265   /* Move the input parameters modulus value p to PKA RAM */
02266   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_MOD_GF], in->modulus, in->modulusSize);
02267   hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL)] = 0UL;
02268
02269   /* Move the input parameters scalar multiplier k to PKA RAM */
02270   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_K], in->scalarMul, in->scalarMulSize);
02271   hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_K + ((in->scalarMulSize + 3UL) / 4UL)] = 0UL;
02272
02273   /* Move the input parameters Point P coordinate x to PKA RAM */
02274   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_X], in->pointX, in->modulusSize);
02275   hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL)] = 0UL;
02276
02277   /* Move the input parameters Point P coordinate y to PKA RAM */
02278   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_Y], in->pointY, in->modulusSize);
02279   hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL)] = 0UL;
02280 }
02281
02282 /**
02283   * @brief  Set input parameters.
02284   * @param  hpka PKA handle
02285   * @param  in Input information
02286   */
02287 void PKA_ECCMulFastMode_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulFastModeInTypeDef *in)
02288 {
02289   /* Get the scalar multiplier k length */
02290   hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS] = PKA_GetOptBitSize_u8(in->scalarMulSize, *(in->scalarMul));
02291
02292   /* Get the modulus length */
02293   hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS] = PKA_GetOptBitSize_u8(in->modulusSize, *(in->modulus));
02294
02295   /* Get the coefficient a sign */
02296   hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN] = in->coefSign;
02297
02298   /* Move the input parameters coefficient |a| to PKA RAM */
02299   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF], in->coefA, in->modulusSize);
02300   hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL)] = 0UL;
02301
02302   /* Move the input parameters modulus value p to PKA RAM */
02303   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_MOD_GF], in->modulus, in->modulusSize);
02304   hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL)] = 0UL;
02305
02306   /* Move the input parameters scalar multiplier k to PKA RAM */
02307   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_K], in->scalarMul, in->scalarMulSize);
02308   hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_K + ((in->scalarMulSize + 3UL) / 4UL)] = 0UL;
02309
02310   /* Move the input parameters Point P coordinate x to PKA RAM */
02311   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_X], in->pointX, in->modulusSize);
02312   hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL)] = 0UL;
02313
02314   /* Move the input parameters Point P coordinate y to PKA RAM */
02315   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_Y], in->pointY, in->modulusSize);
02316   hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL)] = 0UL;
02317
02318   /* Move the Montgomery parameter to PKA RAM */
02319   PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_MONTGOMERY_PARAM], in->pMontgomeryParam, (in->modulusSize + 3UL) / 4UL);
02320   hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_MONTGOMERY_PARAM + ((in->modulusSize + 3UL) / 4UL)] = 0UL;
02321 }
02322
02323 /**
02324   * @brief  Set input parameters.
02325   * @param  hpka PKA handle
02326   * @param  in Input information
02327   */
02328 void PKA_ModInv_Set(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in)
02329 {
02330   /* Get the number of bit per operand */
02331   hpka->Instance->RAM[PKA_MODULAR_INV_NB_BITS] = PKA_GetBitSize_u32(in->size);
02332
02333   /* Move the input parameters operand A to PKA RAM */
02334   PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_MODULAR_INV_IN_OP1], in->pOp1, in->size);
02335   hpka->Instance->RAM[PKA_MODULAR_INV_IN_OP1 + in->size] = 0UL;
02336
02337   /* Move the input parameters modulus value n to PKA RAM */
02338   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_INV_IN_OP2_MOD], in->pMod, in->size * 4UL);
02339   hpka->Instance->RAM[PKA_MODULAR_INV_IN_OP2_MOD + in->size] = 0UL;
02340 }
02341
02342 /**
02343   * @brief  Set input parameters.
02344   * @param  hpka PKA handle
02345   * @param  in Input information
02346   */
02347 void PKA_ModRed_Set(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in)
02348 {
02349   /* Get the number of bit per operand */
02350   hpka->Instance->RAM[PKA_MODULAR_REDUC_IN_OP_LENGTH] = PKA_GetBitSize_u32(in->OpSize);
02351
02352   /* Get the number of bit per modulus */
02353   hpka->Instance->RAM[PKA_MODULAR_REDUC_IN_MOD_LENGTH] = PKA_GetBitSize_u8(in->modSize);
02354
02355   /* Move the input parameters operand A to PKA RAM */
02356   PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_MODULAR_REDUC_IN_OPERAND], in->pOp1, in->OpSize);
02357   hpka->Instance->RAM[PKA_MODULAR_REDUC_IN_OPERAND + in->OpSize] = 0UL;
02358
02359   /* Move the input parameters modulus value n to PKA RAM */
02360   PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_REDUC_IN_MODULUS], in->pMod, in->modSize);
02361   hpka->Instance->RAM[PKA_MODULAR_REDUC_IN_MODULUS + (in->modSize / 4UL)] = 0UL;
02362 }
02363
02364 /**
02365   * @brief  Set input parameters.
02366   * @param  hpka PKA handle
02367   * @param  size Size of the operand
02368   * @param  pOp1 Generic pointer to input data
02369   */
02370 void PKA_MontgomeryParam_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint8_t *pOp1)
02371 {
02372   if (pOp1 != NULL)
02373   {
02374     /* Get the number of bit per operand */
02375     hpka->Instance->RAM[PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS] = PKA_GetOptBitSize_u8(size, *pOp1);
02376
02377     /* Move the input parameters pOp1 to PKA RAM */
02378     PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MONTGOMERY_PARAM_IN_MODULUS], pOp1, size);
02379     hpka->Instance->RAM[PKA_MONTGOMERY_PARAM_IN_MODULUS + ((size + 3UL) / 4UL)] = 0UL;
02380   }
02381 }
02382
02383 /**
02384   * @brief  Generic function to set input parameters.
02385   * @param  hpka PKA handle
02386   * @param  size Size of the operand
02387   * @param  pOp1 Generic pointer to input data
02388   * @param  pOp2 Generic pointer to input data
02389   * @param  pOp3 Generic pointer to input data
02390   */
02391 void PKA_ARI_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint32_t *pOp1, const uint32_t *pOp2, const uint8_t *pOp3)
02392 {
02393   /* Get the number of bit per operand */
02394   hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_NB_BITS] = PKA_GetBitSize_u32(size);
02395
02396   if (pOp1 != NULL)
02397   {
02398     /* Move the input parameters pOp1 to PKA RAM */
02399     PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_IN_OP1], pOp1, size);
02400     hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_IN_OP1 + size] = 0UL;
02401   }
02402
02403   if (pOp2 != NULL)
02404   {
02405     /* Move the input parameters pOp2 to PKA RAM */
02406     PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_IN_OP2], pOp2, size);
02407     hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_IN_OP2 + size] = 0UL;
02408   }
02409
02410   if (pOp3 != NULL)
02411   {
02412     /* Move the input parameters pOp3 to PKA RAM */
02413     PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_IN_OP3], pOp3, size * 4UL);
02414     hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_IN_OP3 + size] = 0UL;
02415   }
02416 }
02417
02418 /**
02419   * @}
02420   */
02421
02422 /**
02423   * @}
02424   */
02425
02426 #endif /* defined(PKA) && defined(HAL_PKA_MODULE_ENABLED) */
02427
02428 /**
02429   * @}
02430   */
02431
02432 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_pka.h Source File

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stm32wbxx_hal_pka.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_pka.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of PKA HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_PKA_H
00022 #define STM32WBxx_HAL_PKA_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 /** @addtogroup STM32WBxx_HAL_Driver
00032  * @{
00033  */
00034
00035 #if defined(PKA) && defined(HAL_PKA_MODULE_ENABLED)
00036
00037 /** @addtogroup PKA
00038  * @{
00039  */
00040
00041 /* Exported types ------------------------------------------------------------*/
00042 /** @defgroup PKA_Exported_Types PKA Exported Types
00043  * @{
00044  */
00045
00046 /** @defgroup HAL_state_structure_definition HAL state structure definition
00047   * @brief  HAL State structures definition
00048   * @{
00049   */
00050 typedef enum
00051 {
00052   HAL_PKA_STATE_RESET   = 0x00U,  /*!< PKA not yet initialized or disabled  */
00053   HAL_PKA_STATE_READY   = 0x01U,  /*!< PKA initialized and ready for use    */
00054   HAL_PKA_STATE_BUSY    = 0x02U,  /*!< PKA internal processing is ongoing   */
00055   HAL_PKA_STATE_ERROR   = 0x03U,  /*!< PKA error state                      */
00056 }
00057 HAL_PKA_StateTypeDef;
00058
00059 /**
00060   * @}
00061   */
00062
00063 #if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
00064 /** @defgroup HAL_callback_id HAL callback ID enumeration
00065   * @{
00066   */
00067 typedef enum
00068 {
00069   HAL_PKA_OPERATION_COMPLETE_CB_ID      = 0x00U,    /*!< PKA End of operation callback ID  */
00070   HAL_PKA_ERROR_CB_ID                   = 0x01U,    /*!< PKA Error callback ID             */
00071   HAL_PKA_MSPINIT_CB_ID                 = 0x02U,    /*!< PKA Msp Init callback ID          */
00072   HAL_PKA_MSPDEINIT_CB_ID               = 0x03U     /*!< PKA Msp DeInit callback ID        */
00073 } HAL_PKA_CallbackIDTypeDef;
00074
00075 /**
00076   * @}
00077   */
00078
00079 #endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
00080
00081 /** @defgroup PKA_Error_Code_definition PKA Error Code definition
00082   * @brief  PKA Error Code definition
00083   * @{
00084   */
00085 #define HAL_PKA_ERROR_NONE      (0x00000000U)
00086 #define HAL_PKA_ERROR_ADDRERR   (0x00000001U)
00087 #define HAL_PKA_ERROR_RAMERR    (0x00000002U)
00088 #define HAL_PKA_ERROR_TIMEOUT   (0x00000004U)
00089 #define HAL_PKA_ERROR_OPERATION (0x00000008U)
00090 #if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
00091 #define HAL_PKA_ERROR_INVALID_CALLBACK  (0x00000010U)    /*!< Invalid Callback error */
00092 #endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
00093
00094 /**
00095   * @}
00096   */
00097
00098 /** @defgroup PKA_handle_Structure_definition PKA handle Structure definition
00099   * @brief  PKA handle Structure definition
00100   * @{
00101   */
00102 typedef struct __PKA_HandleTypeDef
00103 {
00104   PKA_TypeDef                   *Instance;              /*!< Register base address */
00105   __IO HAL_PKA_StateTypeDef     State;                  /*!< PKA state */
00106   __IO uint32_t                 ErrorCode;              /*!< PKA Error code */
00107 #if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
00108   void (* OperationCpltCallback)(struct __PKA_HandleTypeDef *hpka); /*!< PKA End of operation callback */
00109   void (* ErrorCallback)(struct __PKA_HandleTypeDef *hpka);         /*!< PKA Error callback            */
00110   void (* MspInitCallback)(struct __PKA_HandleTypeDef *hpka);       /*!< PKA Msp Init callback         */
00111   void (* MspDeInitCallback)(struct __PKA_HandleTypeDef *hpka);     /*!< PKA Msp DeInit callback       */
00112 #endif  /* USE_HAL_PKA_REGISTER_CALLBACKS */
00113 } PKA_HandleTypeDef;
00114 /**
00115   * @}
00116   */
00117
00118 #if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
00119 /** @defgroup PKA_Callback_definition PKA Callback pointer definition
00120   * @brief  PKA Callback pointer definition
00121   * @{
00122   */
00123 typedef  void (*pPKA_CallbackTypeDef)(PKA_HandleTypeDef *hpka); /*!< Pointer to a PKA callback function */
00124 /**
00125   * @}
00126   */
00127 #endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
00128 /** @defgroup PKA_Operation PKA operation structure definition
00129   * @brief  Input and output data definition
00130   * @{
00131   */
00132 typedef struct
00133 {
00134   uint32_t scalarMulSize;              /*!< Number of element in scalarMul array */
00135   uint32_t modulusSize;                /*!< Number of element in modulus, coefA, pointX and pointY arrays */
00136   uint32_t coefSign;                   /*!< Curve coefficient a sign */
00137   const uint8_t *coefA;                /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */
00138   const uint8_t *modulus;              /*!< Pointer to curve modulus value p (Array of modulusSize elements) */
00139   const uint8_t *pointX;               /*!< Pointer to point P coordinate xP (Array of modulusSize elements) */
00140   const uint8_t *pointY;               /*!< Pointer to point P coordinate yP (Array of modulusSize elements) */
00141   const uint8_t *scalarMul;            /*!< Pointer to scalar multiplier k   (Array of scalarMulSize elements) */
00142   const uint32_t *pMontgomeryParam;    /*!< Pointer to Montgomery parameter  (Array of modulusSize/4 elements) */
00143 } PKA_ECCMulFastModeInTypeDef;
00144
00145 typedef struct
00146 {
00147   uint32_t scalarMulSize;              /*!< Number of element in scalarMul array */
00148   uint32_t modulusSize;                /*!< Number of element in modulus, coefA, pointX and pointY arrays */
00149   uint32_t coefSign;                   /*!< Curve coefficient a sign */
00150   const uint8_t *coefA;                /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */
00151   const uint8_t *modulus;              /*!< Pointer to curve modulus value p (Array of modulusSize elements) */
00152   const uint8_t *pointX;               /*!< Pointer to point P coordinate xP (Array of modulusSize elements) */
00153   const uint8_t *pointY;               /*!< Pointer to point P coordinate yP (Array of modulusSize elements) */
00154   const uint8_t *scalarMul;            /*!< Pointer to scalar multiplier k   (Array of scalarMulSize elements) */
00155 } PKA_ECCMulInTypeDef;
00156
00157 typedef struct
00158 {
00159   uint32_t modulusSize;                /*!< Number of element in coefA, coefB, modulus, pointX and pointY arrays */
00160   uint32_t coefSign;                   /*!< Curve coefficient a sign */
00161   const uint8_t *coefA;                /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */
00162   const uint8_t *coefB;                /*!< Pointer to curve coefficient b   (Array of modulusSize elements) */
00163   const uint8_t *modulus;              /*!< Pointer to curve modulus value p (Array of modulusSize elements) */
00164   const uint8_t *pointX;               /*!< Pointer to point P coordinate xP (Array of modulusSize elements) */
00165   const uint8_t *pointY;               /*!< Pointer to point P coordinate yP (Array of modulusSize elements) */
00166 } PKA_PointCheckInTypeDef;
00167
00168 typedef struct
00169 {
00170   uint32_t size;                       /*!< Number of element in popA array */
00171   const uint8_t *pOpDp;                /*!< Pointer to operand dP   (Array of size/2 elements) */
00172   const uint8_t *pOpDq;                /*!< Pointer to operand dQ   (Array of size/2 elements) */
00173   const uint8_t *pOpQinv;              /*!< Pointer to operand qinv (Array of size/2 elements) */
00174   const uint8_t *pPrimeP;              /*!< Pointer to prime p      (Array of size/2 elements) */
00175   const uint8_t *pPrimeQ;              /*!< Pointer to prime Q      (Array of size/2 elements) */
00176   const uint8_t *popA;                 /*!< Pointer to operand A    (Array of size elements) */
00177 } PKA_RSACRTExpInTypeDef;
00178
00179 typedef struct
00180 {
00181   uint32_t primeOrderSize;             /*!< Number of element in primeOrder array */
00182   uint32_t modulusSize;                /*!< Number of element in modulus array */
00183   uint32_t coefSign;                   /*!< Curve coefficient a sign */
00184   const uint8_t *coef;                 /*!< Pointer to curve coefficient |a|     (Array of modulusSize elements) */
00185   const uint8_t *modulus;              /*!< Pointer to curve modulus value p     (Array of modulusSize elements) */
00186   const uint8_t *basePointX;           /*!< Pointer to curve base point xG       (Array of modulusSize elements) */
00187   const uint8_t *basePointY;           /*!< Pointer to curve base point yG       (Array of modulusSize elements) */
00188   const uint8_t *pPubKeyCurvePtX;      /*!< Pointer to public-key curve point xQ (Array of modulusSize elements) */
00189   const uint8_t *pPubKeyCurvePtY;      /*!< Pointer to public-key curve point yQ (Array of modulusSize elements) */
00190   const uint8_t *RSign;                /*!< Pointer to signature part r          (Array of primeOrderSize elements) */
00191   const uint8_t *SSign;                /*!< Pointer to signature part s          (Array of primeOrderSize elements) */
00192   const uint8_t *hash;                 /*!< Pointer to hash of the message e     (Array of primeOrderSize elements) */
00193   const uint8_t *primeOrder;           /*!< Pointer to order of the curve n      (Array of primeOrderSize elements) */
00194 } PKA_ECDSAVerifInTypeDef;
00195
00196 typedef struct
00197 {
00198   uint32_t primeOrderSize;             /*!< Number of element in primeOrder array */
00199   uint32_t modulusSize;                /*!< Number of element in modulus array */
00200   uint32_t coefSign;                   /*!< Curve coefficient a sign */
00201   const uint8_t *coef;                 /*!< Pointer to curve coefficient |a|     (Array of modulusSize elements) */
00202   const uint8_t *modulus;              /*!< Pointer to curve modulus value p     (Array of modulusSize elements) */
00203   const uint8_t *integer;              /*!< Pointer to random integer k          (Array of primeOrderSize elements) */
00204   const uint8_t *basePointX;           /*!< Pointer to curve base point xG       (Array of modulusSize elements) */
00205   const uint8_t *basePointY;           /*!< Pointer to curve base point yG       (Array of modulusSize elements) */
00206   const uint8_t *hash;                 /*!< Pointer to hash of the message       (Array of primeOrderSize elements) */
00207   const uint8_t *privateKey;           /*!< Pointer to private key d             (Array of primeOrderSize elements) */
00208   const uint8_t *primeOrder;           /*!< Pointer to order of the curve n      (Array of primeOrderSize elements) */
00209 } PKA_ECDSASignInTypeDef;
00210
00211 typedef struct
00212 {
00213   uint8_t *RSign;                      /*!< Pointer to signature part r          (Array of modulusSize elements) */
00214   uint8_t *SSign;                      /*!< Pointer to signature part s          (Array of modulusSize elements) */
00215 } PKA_ECDSASignOutTypeDef;
00216
00217 typedef struct
00218 {
00219   uint8_t *ptX;                        /*!< Pointer to point P coordinate xP     (Array of modulusSize elements) */
00220   uint8_t *ptY;                        /*!< Pointer to point P coordinate yP     (Array of modulusSize elements) */
00221 } PKA_ECDSASignOutExtParamTypeDef, PKA_ECCMulOutTypeDef;
00222
00223 typedef struct
00224 {
00225   uint32_t expSize;                    /*!< Number of element in pExp array */
00226   uint32_t OpSize;                     /*!< Number of element in pOp1 and pMod arrays */
00227   const uint8_t *pExp;                 /*!< Pointer to Exponent             (Array of expSize elements) */
00228   const uint8_t *pOp1;                 /*!< Pointer to Operand              (Array of OpSize elements) */
00229   const uint8_t *pMod;                 /*!< Pointer to modulus              (Array of OpSize elements) */
00230 } PKA_ModExpInTypeDef;
00231
00232 typedef struct
00233 {
00234   uint32_t expSize;                    /*!< Number of element in pExp and pMontgomeryParam arrays */
00235   uint32_t OpSize;                     /*!< Number of element in pOp1 and pMod arrays */
00236   const uint8_t *pExp;                 /*!< Pointer to Exponent             (Array of expSize elements) */
00237   const uint8_t *pOp1;                 /*!< Pointer to Operand              (Array of OpSize elements) */
00238   const uint8_t *pMod;                 /*!< Pointer to modulus              (Array of OpSize elements) */
00239   const uint32_t *pMontgomeryParam;    /*!< Pointer to Montgomery parameter (Array of expSize/4 elements) */
00240 } PKA_ModExpFastModeInTypeDef;
00241
00242 typedef struct
00243 {
00244   uint32_t size;                       /*!< Number of element in pOp1 array */
00245   const uint8_t *pOp1;                 /*!< Pointer to Operand (Array of size elements) */
00246 } PKA_MontgomeryParamInTypeDef;
00247
00248 typedef struct
00249 {
00250   uint32_t size;                       /*!< Number of element in pOp1 and pOp2 arrays */
00251   const uint32_t *pOp1;                /*!< Pointer to Operand 1 (Array of size elements) */
00252   const uint32_t *pOp2;                /*!< Pointer to Operand 2 (Array of size elements) */
00253 } PKA_AddInTypeDef, PKA_SubInTypeDef, PKA_MulInTypeDef, PKA_CmpInTypeDef;
00254
00255 typedef struct
00256 {
00257   uint32_t size;                       /*!< Number of element in pOp1 array */
00258   const uint32_t *pOp1;                /*!< Pointer to Operand 1       (Array of size elements) */
00259   const uint8_t *pMod;                 /*!< Pointer to modulus value n (Array of size*4 elements) */
00260 } PKA_ModInvInTypeDef;
00261
00262 typedef struct
00263 {
00264   uint32_t OpSize;                     /*!< Number of element in pOp1 array */
00265   uint32_t modSize;                    /*!< Number of element in pMod array */
00266   const uint32_t *pOp1;                /*!< Pointer to Operand 1       (Array of OpSize elements) */
00267   const uint8_t *pMod;                 /*!< Pointer to modulus value n (Array of modSize elements) */
00268 } PKA_ModRedInTypeDef;
00269
00270 typedef struct
00271 {
00272   uint32_t size;                       /*!< Number of element in pOp1 and pOp2 arrays */
00273   const uint32_t *pOp1;                /*!< Pointer to Operand 1 (Array of size elements) */
00274   const uint32_t *pOp2;                /*!< Pointer to Operand 2 (Array of size elements) */
00275   const uint8_t  *pOp3;                /*!< Pointer to Operand 3 (Array of size*4 elements) */
00276 } PKA_ModAddInTypeDef, PKA_ModSubInTypeDef, PKA_MontgomeryMulInTypeDef;
00277
00278 /**
00279   * @}
00280   */
00281
00282 /**
00283   * @}
00284   */
00285
00286 /* Exported constants --------------------------------------------------------*/
00287 /** @defgroup PKA_Exported_Constants PKA Exported Constants
00288   * @{
00289   */
00290
00291 /** @defgroup PKA_Mode PKA mode
00292   * @{
00293   */
00294 #define PKA_MODE_MONTGOMERY_PARAM                 (0x00000001U)
00295 #define PKA_MODE_MODULAR_EXP                      (0x00000000U)
00296 #define PKA_MODE_MODULAR_EXP_FAST_MODE            (0x00000002U)
00297 #define PKA_MODE_ECC_MUL                          (0x00000020U)
00298 #define PKA_MODE_ECC_MUL_FAST_MODE                (0x00000022U)
00299 #define PKA_MODE_ECDSA_SIGNATURE                  (0x00000024U)
00300 #define PKA_MODE_ECDSA_VERIFICATION               (0x00000026U)
00301 #define PKA_MODE_POINT_CHECK                      (0x00000028U)
00302 #define PKA_MODE_RSA_CRT_EXP                      (0x00000007U)
00303 #define PKA_MODE_MODULAR_INV                      (0x00000008U)
00304 #define PKA_MODE_ARITHMETIC_ADD                   (0x00000009U)
00305 #define PKA_MODE_ARITHMETIC_SUB                   (0x0000000AU)
00306 #define PKA_MODE_ARITHMETIC_MUL                   (0x0000000BU)
00307 #define PKA_MODE_COMPARISON                       (0x0000000CU)
00308 #define PKA_MODE_MODULAR_RED                      (0x0000000DU)
00309 #define PKA_MODE_MODULAR_ADD                      (0x0000000EU)
00310 #define PKA_MODE_MODULAR_SUB                      (0x0000000FU)
00311 #define PKA_MODE_MONTGOMERY_MUL                   (0x00000010U)
00312 /**
00313   * @}
00314   */
00315
00316 /** @defgroup PKA_Interrupt_configuration_definition PKA Interrupt configuration definition
00317   * @brief PKA Interrupt definition
00318   * @{
00319   */
00320 #define PKA_IT_PROCEND                            PKA_CR_PROCENDIE
00321 #define PKA_IT_ADDRERR                            PKA_CR_ADDRERRIE
00322 #define PKA_IT_RAMERR                             PKA_CR_RAMERRIE
00323 /**
00324   * @}
00325   */
00326
00327 /** @defgroup PKA_Flag_definition PKA Flag definition
00328   * @{
00329   */
00330 #define PKA_FLAG_PROCEND                          PKA_SR_PROCENDF
00331 #define PKA_FLAG_ADDRERR                          PKA_SR_ADDRERRF
00332 #define PKA_FLAG_RAMERR                           PKA_SR_RAMERRF
00333 /**
00334   * @}
00335   */
00336
00337 /**
00338   * @}
00339   */
00340
00341 /* Exported macros -----------------------------------------------------------*/
00342
00343 /** @defgroup PKA_Exported_Macros PKA Exported Macros
00344   * @{
00345   */
00346
00347 /** @brief  Reset PKA handle state.
00348   * @param  __HANDLE__ specifies the PKA Handle
00349   * @retval None
00350   */
00351 #if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
00352 #define __HAL_PKA_RESET_HANDLE_STATE(__HANDLE__)                do{                                                   \
00353                                                                     (__HANDLE__)->State = HAL_PKA_STATE_RESET;       \
00354                                                                     (__HANDLE__)->MspInitCallback = NULL;            \
00355                                                                     (__HANDLE__)->MspDeInitCallback = NULL;          \
00356                                                                   } while(0)
00357 #else
00358 #define __HAL_PKA_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_PKA_STATE_RESET)
00359 #endif
00360
00361 /** @brief  Enable the specified PKA interrupt.
00362   * @param  __HANDLE__ specifies the PKA Handle
00363   * @param  __INTERRUPT__ specifies the interrupt source to enable.
00364   *        This parameter can be one of the following values:
00365   *            @arg @ref PKA_IT_PROCEND End Of Operation interrupt enable
00366   *            @arg @ref PKA_IT_ADDRERR Address error interrupt enable
00367   *            @arg @ref PKA_IT_RAMERR RAM error interrupt enable
00368   * @retval None
00369   */
00370 #define __HAL_PKA_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
00371
00372 /** @brief  Disable the specified PKA interrupt.
00373   * @param  __HANDLE__ specifies the PKA Handle
00374   * @param  __INTERRUPT__ specifies the interrupt source to disable.
00375   *        This parameter can be one of the following values:
00376   *            @arg @ref PKA_IT_PROCEND End Of Operation interrupt enable
00377   *            @arg @ref PKA_IT_ADDRERR Address error interrupt enable
00378   *            @arg @ref PKA_IT_RAMERR RAM error interrupt enable
00379   * @retval None
00380   */
00381 #define __HAL_PKA_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR &= (~(__INTERRUPT__)))
00382
00383 /** @brief  Check whether the specified PKA interrupt source is enabled or not.
00384   * @param  __HANDLE__ specifies the PKA Handle
00385   * @param  __INTERRUPT__ specifies the PKA interrupt source to check.
00386   *        This parameter can be one of the following values:
00387   *            @arg @ref PKA_IT_PROCEND End Of Operation interrupt enable
00388   *            @arg @ref PKA_IT_ADDRERR Address error interrupt enable
00389   *            @arg @ref PKA_IT_RAMERR RAM error interrupt enable
00390   * @retval The new state of __INTERRUPT__ (SET or RESET)
00391   */
00392 #define __HAL_PKA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      ((((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00393
00394 /** @brief  Check whether the specified PKA flag is set or not.
00395   * @param  __HANDLE__ specifies the PKA Handle
00396   * @param  __FLAG__ specifies the flag to check.
00397   *        This parameter can be one of the following values:
00398   *            @arg @ref PKA_FLAG_PROCEND End Of Operation
00399   *            @arg @ref PKA_FLAG_ADDRERR Address error
00400   *            @arg @ref PKA_FLAG_RAMERR RAM error
00401   * @retval The new state of __FLAG__ (SET or RESET)
00402   */
00403 #define __HAL_PKA_GET_FLAG(__HANDLE__, __FLAG__)                (((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
00404
00405 /** @brief  Clear the PKA pending flags which are cleared by writing 1 in a specific bit.
00406   * @param  __HANDLE__ specifies the PKA Handle
00407   * @param  __FLAG__ specifies the flag to clear.
00408   *          This parameter can be any combination of the following values:
00409   *            @arg @ref PKA_FLAG_PROCEND End Of Operation
00410   *            @arg @ref PKA_FLAG_ADDRERR Address error
00411   *            @arg @ref PKA_FLAG_RAMERR RAM error
00412   * @retval None
00413   */
00414 #define __HAL_PKA_CLEAR_FLAG(__HANDLE__, __FLAG__)              ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
00415
00416 /** @brief  Enable the specified PKA peripheral.
00417   * @param  __HANDLE__ specifies the PKA Handle
00418   * @retval None
00419   */
00420 #define __HAL_PKA_ENABLE(__HANDLE__)                            (SET_BIT((__HANDLE__)->Instance->CR,  PKA_CR_EN))
00421
00422 /** @brief  Disable the specified PKA peripheral.
00423   * @param  __HANDLE__ specifies the PKA Handle
00424   * @retval None
00425   */
00426 #define __HAL_PKA_DISABLE(__HANDLE__)                           (CLEAR_BIT((__HANDLE__)->Instance->CR, PKA_CR_EN))
00427
00428 /** @brief  Start a PKA operation.
00429   * @param  __HANDLE__ specifies the PKA Handle
00430   * @retval None
00431   */
00432 #define __HAL_PKA_START(__HANDLE__)                             (SET_BIT((__HANDLE__)->Instance->CR,  PKA_CR_START))
00433 /**
00434   * @}
00435   */
00436
00437 /* Private macros --------------------------------------------------------*/
00438 /* Exported functions --------------------------------------------------------*/
00439 /** @addtogroup PKA_Exported_Functions
00440   * @{
00441   */
00442
00443 /** @addtogroup PKA_Exported_Functions_Group1
00444   * @{
00445   */
00446 /* Initialization and de-initialization functions *****************************/
00447 HAL_StatusTypeDef HAL_PKA_Init(PKA_HandleTypeDef *hpka);
00448 HAL_StatusTypeDef HAL_PKA_DeInit(PKA_HandleTypeDef *hpka);
00449 void              HAL_PKA_MspInit(PKA_HandleTypeDef *hpka);
00450 void              HAL_PKA_MspDeInit(PKA_HandleTypeDef *hpka);
00451
00452 #if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
00453 /* Callbacks Register/UnRegister functions  ***********************************/
00454 HAL_StatusTypeDef HAL_PKA_RegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID, pPKA_CallbackTypeDef pCallback);
00455 HAL_StatusTypeDef HAL_PKA_UnRegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID);
00456 #endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
00457
00458 /**
00459   * @}
00460   */
00461
00462 /** @addtogroup PKA_Exported_Functions_Group2
00463   * @{
00464   */
00465 /* IO operation functions *****************************************************/
00466 /* High Level Functions *******************************************************/
00467 HAL_StatusTypeDef HAL_PKA_ModExp(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in, uint32_t Timeout);
00468 HAL_StatusTypeDef HAL_PKA_ModExp_IT(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in);
00469 HAL_StatusTypeDef HAL_PKA_ModExpFastMode(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in, uint32_t Timeout);
00470 HAL_StatusTypeDef HAL_PKA_ModExpFastMode_IT(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in);
00471 void HAL_PKA_ModExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes);
00472
00473 HAL_StatusTypeDef HAL_PKA_ECDSASign(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in, uint32_t Timeout);
00474 HAL_StatusTypeDef HAL_PKA_ECDSASign_IT(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in);
00475 void HAL_PKA_ECDSASign_GetResult(PKA_HandleTypeDef *hpka, PKA_ECDSASignOutTypeDef *out, PKA_ECDSASignOutExtParamTypeDef *outExt);
00476
00477 HAL_StatusTypeDef HAL_PKA_ECDSAVerif(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in, uint32_t Timeout);
00478 HAL_StatusTypeDef HAL_PKA_ECDSAVerif_IT(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in);
00479 uint32_t HAL_PKA_ECDSAVerif_IsValidSignature(PKA_HandleTypeDef const *const hpka);
00480
00481 HAL_StatusTypeDef HAL_PKA_RSACRTExp(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in, uint32_t Timeout);
00482 HAL_StatusTypeDef HAL_PKA_RSACRTExp_IT(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in);
00483 void HAL_PKA_RSACRTExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes);
00484
00485 HAL_StatusTypeDef HAL_PKA_PointCheck(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in, uint32_t Timeout);
00486 HAL_StatusTypeDef HAL_PKA_PointCheck_IT(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in);
00487 uint32_t HAL_PKA_PointCheck_IsOnCurve(PKA_HandleTypeDef const *const hpka);
00488
00489 HAL_StatusTypeDef HAL_PKA_ECCMul(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in, uint32_t Timeout);
00490 HAL_StatusTypeDef HAL_PKA_ECCMul_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in);
00491 HAL_StatusTypeDef HAL_PKA_ECCMulFastMode(PKA_HandleTypeDef *hpka, PKA_ECCMulFastModeInTypeDef *in, uint32_t Timeout);
00492 HAL_StatusTypeDef HAL_PKA_ECCMulFastMode_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulFastModeInTypeDef *in);
00493 void HAL_PKA_ECCMul_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCMulOutTypeDef *out);
00494
00495 HAL_StatusTypeDef HAL_PKA_Add(PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in, uint32_t Timeout);
00496 HAL_StatusTypeDef HAL_PKA_Add_IT(PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in);
00497 HAL_StatusTypeDef HAL_PKA_Sub(PKA_HandleTypeDef *hpka, PKA_SubInTypeDef *in, uint32_t Timeout);
00498 HAL_StatusTypeDef HAL_PKA_Sub_IT(PKA_HandleTypeDef *hpka, PKA_SubInTypeDef *in);
00499 HAL_StatusTypeDef HAL_PKA_Cmp(PKA_HandleTypeDef *hpka, PKA_CmpInTypeDef *in, uint32_t Timeout);
00500 HAL_StatusTypeDef HAL_PKA_Cmp_IT(PKA_HandleTypeDef *hpka, PKA_CmpInTypeDef *in);
00501 HAL_StatusTypeDef HAL_PKA_Mul(PKA_HandleTypeDef *hpka, PKA_MulInTypeDef *in, uint32_t Timeout);
00502 HAL_StatusTypeDef HAL_PKA_Mul_IT(PKA_HandleTypeDef *hpka, PKA_MulInTypeDef *in);
00503 HAL_StatusTypeDef HAL_PKA_ModAdd(PKA_HandleTypeDef *hpka, PKA_ModAddInTypeDef *in, uint32_t Timeout);
00504 HAL_StatusTypeDef HAL_PKA_ModAdd_IT(PKA_HandleTypeDef *hpka, PKA_ModAddInTypeDef *in);
00505 HAL_StatusTypeDef HAL_PKA_ModSub(PKA_HandleTypeDef *hpka, PKA_ModSubInTypeDef *in, uint32_t Timeout);
00506 HAL_StatusTypeDef HAL_PKA_ModSub_IT(PKA_HandleTypeDef *hpka, PKA_ModSubInTypeDef *in);
00507 HAL_StatusTypeDef HAL_PKA_ModInv(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in, uint32_t Timeout);
00508 HAL_StatusTypeDef HAL_PKA_ModInv_IT(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in);
00509 HAL_StatusTypeDef HAL_PKA_ModRed(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in, uint32_t Timeout);
00510 HAL_StatusTypeDef HAL_PKA_ModRed_IT(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in);
00511 HAL_StatusTypeDef HAL_PKA_MontgomeryMul(PKA_HandleTypeDef *hpka, PKA_MontgomeryMulInTypeDef *in, uint32_t Timeout);
00512 HAL_StatusTypeDef HAL_PKA_MontgomeryMul_IT(PKA_HandleTypeDef *hpka, PKA_MontgomeryMulInTypeDef *in);
00513 void HAL_PKA_Arithmetic_GetResult(PKA_HandleTypeDef *hpka, uint32_t *pRes);
00514
00515 HAL_StatusTypeDef HAL_PKA_MontgomeryParam(PKA_HandleTypeDef *hpka, PKA_MontgomeryParamInTypeDef *in, uint32_t Timeout);
00516 HAL_StatusTypeDef HAL_PKA_MontgomeryParam_IT(PKA_HandleTypeDef *hpka, PKA_MontgomeryParamInTypeDef *in);
00517 void HAL_PKA_MontgomeryParam_GetResult(PKA_HandleTypeDef *hpka, uint32_t *pRes);
00518
00519 HAL_StatusTypeDef HAL_PKA_Abort(PKA_HandleTypeDef *hpka);
00520 void HAL_PKA_RAMReset(PKA_HandleTypeDef *hpka);
00521 void HAL_PKA_OperationCpltCallback(PKA_HandleTypeDef *hpka);
00522 void HAL_PKA_ErrorCallback(PKA_HandleTypeDef *hpka);
00523 void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka);
00524 /**
00525   * @}
00526   */
00527
00528 /** @addtogroup PKA_Exported_Functions_Group3
00529   * @{
00530   */
00531 /* Peripheral State and Error functions ***************************************/
00532 HAL_PKA_StateTypeDef HAL_PKA_GetState(PKA_HandleTypeDef *hpka);
00533 uint32_t             HAL_PKA_GetError(PKA_HandleTypeDef *hpka);
00534 /**
00535   * @}
00536   */
00537
00538 /**
00539   * @}
00540   */
00541
00542 /**
00543   * @}
00544   */
00545
00546 #endif /* defined(PKA) && defined(HAL_PKA_MODULE_ENABLED) */
00547
00548 /**
00549   * @}
00550   */
00551
00552 #ifdef __cplusplus
00553 }
00554 #endif
00555
00556 #endif /* STM32WBxx_HAL_PKA_H */
00557
00558 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_pwr.c Source File

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stm32wbxx_hal_pwr.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_pwr.c
00004   * @author  MCD Application Team
00005   * @brief   PWR HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Power Controller (PWR) peripheral:
00008   *           + Initialization/de-initialization functions
00009   *           + Peripheral Control functions
00010   *
00011   ******************************************************************************
00012   * @attention
00013   *
00014   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00015   * All rights reserved.</center></h2>
00016   *
00017   * This software component is licensed by ST under BSD 3-Clause license,
00018   * the "License"; You may not use this file except in compliance with the
00019   * License. You may obtain a copy of the License at:
00020   *                        opensource.org/licenses/BSD-3-Clause
00021   *
00022   ******************************************************************************
00023   */
00024
00025 /* Includes ------------------------------------------------------------------*/
00026 #include "stm32wbxx_hal.h"
00027
00028 /** @addtogroup STM32WBxx_HAL_Driver
00029   * @{
00030   */
00031
00032 /** @addtogroup PWR
00033   * @{
00034   */
00035
00036 #ifdef HAL_PWR_MODULE_ENABLED
00037
00038 /* Private typedef -----------------------------------------------------------*/
00039 /* Private define ------------------------------------------------------------*/
00040 /* Private macro -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /** @addtogroup PWR_Private_Defines
00044   * @{
00045   */
00046
00047 /** @defgroup PWR_Register_Reset_Values  PWR Register Reset Values
00048   * @{
00049   */
00050 /* Definitions of PWR registers reset value */
00051 #define PWR_CR1_RESET_VALUE   (0x00000200U)
00052 #define PWR_CR2_RESET_VALUE   (0x00000000U)
00053 #define PWR_CR3_RESET_VALUE   (0x00008000U)
00054 #define PWR_CR4_RESET_VALUE   (0x00000000U)
00055 #define PWR_CR5_RESET_VALUE   (0x00004204U)
00056 #define PWR_PUCRA_RESET_VALUE (0x00000000U)
00057 #define PWR_PDCRA_RESET_VALUE (0x00000000U)
00058 #define PWR_PUCRB_RESET_VALUE (0x00000000U)
00059 #define PWR_PDCRB_RESET_VALUE (0x00000000U)
00060 #define PWR_PUCRC_RESET_VALUE (0x00000000U)
00061 #define PWR_PDCRC_RESET_VALUE (0x00000000U)
00062 #define PWR_PUCRD_RESET_VALUE (0x00000000U)
00063 #define PWR_PDCRD_RESET_VALUE (0x00000000U)
00064 #define PWR_PUCRE_RESET_VALUE (0x00000000U)
00065 #define PWR_PDCRE_RESET_VALUE (0x00000000U)
00066 #define PWR_PUCRH_RESET_VALUE (0x00000000U)
00067 #define PWR_PDCRH_RESET_VALUE (0x00000000U)
00068 #define PWR_C2CR1_RESET_VALUE (0x00000000U)
00069 #define PWR_C2CR3_RESET_VALUE (0x00008000U)
00070 /**
00071   * @}
00072   */
00073
00074  /**
00075   * @}
00076   */
00077
00078 /* Private function prototypes -----------------------------------------------*/
00079 /* Exported functions --------------------------------------------------------*/
00080 /** @addtogroup PWR_Exported_Functions  PWR Exported Functions
00081   * @{
00082   */
00083
00084 /** @addtogroup PWR_Exported_Functions_Group1  Initialization and de-initialization functions
00085   * @brief  Initialization and de-initialization functions
00086   *
00087 @verbatim
00088  ===============================================================================
00089               ##### Initialization and de-initialization functions #####
00090  ===============================================================================
00091     [..]
00092
00093 @endverbatim
00094   * @{
00095   */
00096
00097 /**
00098   * @brief  Deinitialize the HAL PWR peripheral registers to their default reset values.
00099   * @retval None
00100   */
00101 void HAL_PWR_DeInit(void)
00102 {
00103   /* Apply reset values to all PWR registers */
00104   /* Note: Update of each register required since PWR global reset is not     */
00105   /*       available at RCC level on this STM32 serie.                        */
00106   LL_PWR_WriteReg(CR1, PWR_CR1_RESET_VALUE);
00107   LL_PWR_WriteReg(CR2, PWR_CR2_RESET_VALUE);
00108   LL_PWR_WriteReg(CR3, PWR_CR3_RESET_VALUE);
00109   LL_PWR_WriteReg(CR4, PWR_CR4_RESET_VALUE);
00110   LL_PWR_WriteReg(CR5, PWR_CR5_RESET_VALUE);
00111   LL_PWR_WriteReg(PUCRA, PWR_PUCRA_RESET_VALUE);
00112   LL_PWR_WriteReg(PDCRA, PWR_PDCRA_RESET_VALUE);
00113   LL_PWR_WriteReg(PUCRB, PWR_PUCRB_RESET_VALUE);
00114   LL_PWR_WriteReg(PDCRB, PWR_PDCRB_RESET_VALUE);
00115   LL_PWR_WriteReg(PUCRC, PWR_PUCRC_RESET_VALUE);
00116   LL_PWR_WriteReg(PDCRC, PWR_PDCRC_RESET_VALUE);
00117 #if defined(GPIOD)
00118   LL_PWR_WriteReg(PUCRD, PWR_PUCRD_RESET_VALUE);
00119   LL_PWR_WriteReg(PDCRD, PWR_PDCRD_RESET_VALUE);
00120 #endif
00121   LL_PWR_WriteReg(PUCRE, PWR_PUCRE_RESET_VALUE);
00122   LL_PWR_WriteReg(PDCRE, PWR_PDCRE_RESET_VALUE);
00123   LL_PWR_WriteReg(PUCRH, PWR_PUCRH_RESET_VALUE);
00124   LL_PWR_WriteReg(PDCRH, PWR_PDCRH_RESET_VALUE);
00125   LL_PWR_WriteReg(C2CR1, PWR_C2CR1_RESET_VALUE);
00126   LL_PWR_WriteReg(C2CR3, PWR_C2CR3_RESET_VALUE);
00127
00128   /* Clear all flags */
00129   LL_PWR_WriteReg(SCR,
00130                     LL_PWR_SCR_CC2HF
00131                   | LL_PWR_SCR_C802AF
00132                   | LL_PWR_SCR_CBLEAF
00133                   | LL_PWR_SCR_CCRPEF
00134                   | LL_PWR_SCR_C802WUF
00135                   | LL_PWR_SCR_CBLEWUF
00136 #if defined(PWR_CR5_SMPSEN)
00137                   | LL_PWR_SCR_CBORHF
00138                   | LL_PWR_SCR_CSMPSFBF
00139 #endif
00140                   | LL_PWR_SCR_CWUF
00141                  );
00142
00143   LL_PWR_WriteReg(EXTSCR,
00144                     LL_PWR_EXTSCR_CCRPF
00145                   | LL_PWR_EXTSCR_C2CSSF
00146                   | LL_PWR_EXTSCR_C1CSSF
00147                  );
00148 }
00149
00150
00151 /**
00152   * @brief  Enable access to the backup domain
00153   *         (RTC registers, RTC backup data registers).
00154   * @note   After reset, the backup domain is protected against
00155   *         possible unwanted write accesses.
00156   * @note   RTCSEL that sets the RTC clock source selection is in the RTC back-up domain.
00157   *         In order to set or modify the RTC clock, the backup domain access must be
00158   *         disabled.
00159   * @note   LSEON bit that switches on and off the LSE crystal belongs as well to the
00160   *         back-up domain.
00161   * @retval None
00162   */
00163 void HAL_PWR_EnableBkUpAccess(void)
00164 {
00165   SET_BIT(PWR->CR1, PWR_CR1_DBP);
00166 }
00167
00168 /**
00169   * @brief  Disable access to the backup domain
00170   *         (RTC registers, RTC backup data registers).
00171   * @retval None
00172   */
00173 void HAL_PWR_DisableBkUpAccess(void)
00174 {
00175   CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
00176 }
00177
00178 /**
00179   * @}
00180   */
00181
00182
00183 /** @addtogroup PWR_Exported_Functions_Group2  Peripheral Control functions
00184   *  @brief Low Power modes configuration functions
00185   *
00186 @verbatim
00187
00188  ===============================================================================
00189                  ##### Peripheral Control functions #####
00190  ===============================================================================
00191
00192     [..]
00193      *** PVD configuration ***
00194     =========================
00195     [..]
00196       (+) The PVD is used to monitor the VDD power supply by comparing it to a
00197           threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2 register).
00198       (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower
00199           than the PVD threshold. This event is internally connected to the EXTI
00200           line16 and can generate an interrupt if enabled. This is done through
00201           __HAL_PVD_EXTI_ENABLE_IT() macro.
00202       (+) The PVD is stopped in Standby mode.
00203
00204     *** WakeUp pin configuration ***
00205     ================================
00206     [..]
00207       (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode.
00208           The polarity of these pins can be set to configure event detection on high
00209           level (rising edge) or low level (falling edge).
00210
00211     *** Low Power modes configuration ***
00212     =====================================
00213     [..]
00214       The devices feature 8 low-power modes:
00215
00216       (+) Low-power Run mode: core and peripherals are running, main regulator off, low power regulator on.
00217
00218       (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and low power regulators on.
00219       (+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator off, low power regulator on.
00220
00221       (+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on.
00222       (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on.
00223       (+) Stop 2 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on, reduced set of waking up IPs compared to Stop 1 mode.
00224
00225       (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on.
00226       (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off.
00227
00228       (+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off.
00229
00230
00231    *** Low-power run mode ***
00232    ==========================
00233     [..]
00234       (+) Entry: (from main run mode)
00235           (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz.
00236       (+) Exit:
00237           (++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMode() API. Only
00238                then can the system clock frequency be increased above 2 MHz.
00239
00240    *** Sleep mode / Low-power sleep mode ***
00241    =========================================
00242     [..]
00243       (+) Entry:
00244           The Sleep mode / Low-power Sleep mode is entered thru HAL_PWR_EnterSLEEPMode() API
00245           in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered.
00246           (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
00247           (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).
00248           In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand.
00249           (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
00250           (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
00251
00252       (+) WFI Exit:
00253         (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
00254              controller (NVIC) or any wake-up event.
00255
00256       (+) WFE Exit:
00257         (++) Any wake-up event such as an EXTI line configured in event mode.
00258
00259     [..]  When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event,
00260           the MCU is in Low-power Run mode.
00261
00262    *** Stop 0, Stop 1 and Stop 2 modes ***
00263    ===============================
00264     [..]
00265       (+) Entry:
00266           The Stop 0, Stop 1 or Stop 2 modes are entered thru the following API's:
00267           (++) HAL_PWREx_EnterSTOP0Mode() for mode 0, HAL_PWREx_EnterSTOP1Mode() for mode 1, HAL_PWREx_EnterSTOP2Mode() for mode 2
00268                or for porting reasons HAL_PWR_EnterSTOPMode().
00269
00270       (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
00271           (++) PWR_MAINREGULATOR_ON: Regulator in main mode (STOP0 mode)
00272           (++) PWR_LOWPOWERREGULATOR_ON: Regulator in low-power mode (STOP1 mode)
00273       (+) Exit (interrupt or event-triggered, specified when entering STOP mode):
00274           (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
00275           (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction
00276       (+) WFI Exit:
00277           (++) Any EXTI Line (Internal or External) configured in Interrupt mode.
00278           (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts
00279                when programmed in wakeup mode.
00280       (+) WFE Exit:
00281           (++) Any EXTI Line (Internal or External) configured in Event mode.
00282
00283        [..]
00284           When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run mode
00285           depending on the LPR bit setting.
00286           When exiting Stop 2 mode, the MCU is in Run mode.
00287
00288    *** Standby mode ***
00289    ====================
00290     [..] The Standby mode offers two options:
00291       (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low power mode).
00292           SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers
00293           and Standby circuitry.
00294       (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disabled).
00295           SRAM and register contents are lost except for the RTC registers, RTC backup registers
00296           and Standby circuitry.
00297
00298       (++) Entry:
00299           (+++) The Standby mode is entered thru HAL_PWR_EnterSTANDBYMode() API.
00300                 SRAM1 and register contents are lost except for registers in the Backup domain and
00301                 Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
00302                 To enable this feature, the user can resort to HAL_PWREx_EnableBKRAMContentRetention() API
00303                 to set RRS bit.
00304       (++) Exit:
00305           (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
00306                 external reset in NRST pin, IWDG reset.
00307     [..] After waking up from Standby mode, program execution restarts in the same way as after a Reset.
00308
00309
00310     *** Shutdown mode ***
00311    ======================
00312     [..]
00313       In Shutdown mode,
00314         voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared.
00315         SRAM and registers contents are lost except for backup domain registers.
00316       (+) Entry:
00317           The Shutdown mode is entered thru HAL_PWREx_EnterSHUTDOWNMode() API.
00318       (+) Exit:
00319           (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
00320                external reset in NRST pin.
00321     [..] After waking up from Shutdown mode, program execution restarts in the same way as after a Reset.
00322
00323
00324    *** Auto-wakeup (AWU) from low-power mode ***
00325    =============================================
00326     [..]
00327       The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
00328       Wakeup event, a tamper event or a time-stamp event, without depending on
00329       an external interrupt (Auto-wakeup mode).
00330
00331       (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes
00332
00333
00334         (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
00335              configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
00336
00337         (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
00338              is necessary to configure the RTC to detect the tamper or time stamp event using the
00339              HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
00340
00341         (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
00342               configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
00343
00344 @endverbatim
00345   * @{
00346   */
00347
00348 /**
00349   * @brief  Configure the voltage threshold detected by the Power Voltage Detector (PVD).
00350   * @param sConfigPVD pointer to a PWR_PVDTypeDef structure that contains the PVD
00351   *         configuration information.
00352   * @note   Refer to the electrical characteristics of your device datasheet for
00353   *         more details about the voltage thresholds corresponding to each
00354   *         detection level.
00355   * @note   If "sConfigPVD->Mode" is set to PVD_MODE_IT,
00356   *         wake-up target is set by default to wake-up target CPU1.
00357   *         To select wake-up target to CPU2, additional configuration must be
00358   *         performed using macro "__HAL_PWR_PVD_EXTIC2_ENABLE_IT()"
00359   *         (and optionally, to select CPU2 only (not both CPU1 and CPU2):
00360   *         "__HAL_PWR_PVD_EXTI_DISABLE_IT()").
00361   * @retval None
00362   */
00363 HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
00364 {
00365   /* Check the parameters */
00366   assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
00367   assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
00368
00369   /* Set PLS bits according to PVDLevel value */
00370   MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel);
00371
00372   /* Clear any previous config. Keep it clear if no event or IT mode is selected */
00373
00374   /* Note: On STM32WB serie, power PVD event is not available on AIEC lines   */
00375   /*       (only interruption is available through AIEC line 16).             */
00376   __HAL_PWR_PVD_EXTI_DISABLE_IT();      /*CPU1*/
00377   __HAL_PWR_PVD_EXTIC2_DISABLE_IT();    /*CPU2*/
00378
00379   __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
00380   __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
00381
00382   /* Configure interrupt mode */
00383   if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
00384   {
00385     /* Set CPU1 as wakeup target */
00386     __HAL_PWR_PVD_EXTI_ENABLE_IT();
00387   }
00388
00389   /* Configure the edge */
00390   if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
00391   {
00392     __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
00393   }
00394
00395   if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
00396   {
00397     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
00398   }
00399
00400   return HAL_OK;
00401 }
00402
00403 /**
00404   * @brief Enables the Power Voltage Detector(PVD).
00405   * @retval None
00406   */
00407 void HAL_PWR_EnablePVD(void)
00408 {
00409   /* Enable the power voltage detector */
00410   SET_BIT(PWR->CR2, PWR_CR2_PVDE);
00411 }
00412
00413 /**
00414   * @brief Disables the Power Voltage Detector(PVD).
00415   * @retval None
00416   */
00417 void HAL_PWR_DisablePVD(void)
00418 {
00419   /* Disable the power voltage detector */
00420   CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
00421 }
00422
00423
00424 /**
00425   * @brief Enable the WakeUp PINx functionality.
00426   * @param WakeUpPinPolarity Specifies which Wake-Up pin to enable.
00427   *         This parameter can be one of the following legacy values which set the default polarity
00428   *         i.e. detection on high level (rising edge):
00429   *           @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
00430   *
00431   *         or one of the following value where the user can explicitly specify the enabled pin and
00432   *         the chosen polarity:
00433   *           @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
00434   *           @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
00435   *           @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
00436   *           @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
00437   *           @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
00438   * @note  PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
00439   * @retval None
00440   */
00441 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
00442 {
00443   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
00444
00445   /* Specifies the Wake-Up pin polarity for the event detection
00446     (rising or falling edge) */
00447   MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT));
00448
00449   /* Enable wake-up pin */
00450   SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity));
00451 }
00452
00453 /**
00454   * @brief  Disable the WakeUp PINx functionality.
00455   * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
00456   *         This parameter can be one of the following values:
00457   *           @arg PWR_WAKEUP_PIN1: An event on PA0   PIN wakes-up the system from Standby mode.
00458   *           @arg PWR_WAKEUP_PIN2: An event on PC13  PIN wakes-up the system from Standby mode.
00459   *           @arg PWR_WAKEUP_PIN3: An event on PC12  PIN wakes-up the system from Standby mode.
00460   *           @arg PWR_WAKEUP_PIN4: An event on PA2   PIN wakes-up the system from Standby mode.
00461   *           @arg PWR_WAKEUP_PIN5: An event on PC5   PIN wakes-up the system from Standby mode.
00462   * @retval None
00463   */
00464 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
00465 {
00466   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
00467
00468   CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx));
00469 }
00470
00471 /**
00472   * @brief Enter Sleep or Low-power Sleep mode.
00473   * @note  In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode.
00474   * @param Regulator Specifies the regulator state in Sleep/Low-power Sleep mode.
00475   *          This parameter can be one of the following values:
00476   *            @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)
00477   *            @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode)
00478   * @note  Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet
00479   *        in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set
00480   *        to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
00481   *        Flash in power-down mode in setting the SLEEP_PD bit in FLASH_ACR register.
00482   *        Additionally, the clock frequency must be reduced below 2 MHz.
00483   *        Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must
00484   *        be done before calling HAL_PWR_EnterSLEEPMode() API.
00485   * @note  When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in
00486   *        Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API.
00487   * @param SLEEPEntry Specifies if Sleep mode is entered with WFI or WFE instruction.
00488   *           This parameter can be one of the following values:
00489   *            @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction
00490   *            @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction
00491   * @note  When WFI entry is used, tick interrupt have to be disabled if not desired as
00492   *        the interrupt wake up source.
00493   * @retval None
00494   */
00495 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
00496 {
00497   /* Check the parameters */
00498   assert_param(IS_PWR_REGULATOR(Regulator));
00499   assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
00500
00501   /* Set Regulator parameter */
00502   if (Regulator == PWR_MAINREGULATOR_ON)
00503   {
00504     /* If in low-power run mode at this point, exit it */
00505     if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
00506     {
00507       if (HAL_PWREx_DisableLowPowerRunMode() != HAL_OK)
00508       {
00509         return ;
00510       }
00511     }
00512     /* Regulator now in main mode. */
00513   }
00514   else
00515   {
00516     /* If in run mode, first move to low-power run mode.
00517        The system clock frequency must be below 2 MHz at this point. */
00518     if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == RESET)
00519     {
00520       HAL_PWREx_EnableLowPowerRunMode();
00521     }
00522   }
00523
00524   /* Clear SLEEPDEEP bit of Cortex System Control Register */
00525   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00526
00527   /* Select SLEEP mode entry -------------------------------------------------*/
00528   if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
00529   {
00530     /* Request Wait For Interrupt */
00531     __WFI();
00532   }
00533   else
00534   {
00535     /* Request Wait For Event */
00536     __SEV();
00537     __WFE();
00538     __WFE();
00539   }
00540 }
00541
00542
00543 /**
00544   * @brief Enter Stop mode
00545   * @note  This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running
00546   *        on devices where only "Stop mode" is mentioned with main or low power regulator ON.
00547   * @note  In Stop mode, all I/O pins keep the same state as in Run mode.
00548   * @note  All clocks in the VCORE domain are stopped; the PLL, the MSI,
00549   *        the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
00550   *        (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
00551   *        after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
00552   *        only to the peripheral requesting it.
00553   *        SRAM1, SRAM2 and register contents are preserved.
00554   *        The BOR is available.
00555   *        The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1).
00556   * @note  When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event,
00557   *         the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
00558   *         is set; the MSI oscillator is selected if STOPWUCK is cleared.
00559   * @note  When the voltage regulator operates in low power mode (Stop 1), an additional
00560   *         startup delay is incurred when waking up.
00561   *         By keeping the internal regulator ON during Stop mode (Stop 0), the consumption
00562   *         is higher although the startup time is reduced.
00563   * @note  Case of Stop0 mode with SMPS: Before entering Stop 0 mode with SMPS Step Down converter enabled,
00564   *        the HSI16 must be kept on by enabling HSI kernel clock (set HSIKERON register bit).
00565   * @note  According to system power policy, system entering in Stop mode
00566   *        is depending on other CPU power mode.
00567   * @param Regulator Specifies the regulator state in Stop mode.
00568   *          This parameter can be one of the following values:
00569   *            @arg @ref PWR_MAINREGULATOR_ON  Stop 0 mode (main regulator ON)
00570   *            @arg @ref PWR_LOWPOWERREGULATOR_ON  Stop 1 mode (low power regulator ON)
00571   * @param STOPEntry Specifies Stop 0, Stop 1 or Stop 2 mode is entered with WFI or WFE instruction.
00572   *          This parameter can be one of the following values:
00573   *            @arg @ref PWR_STOPENTRY_WFI  Enter Stop 0 or Stop 1 mode with WFI instruction.
00574   *            @arg @ref PWR_STOPENTRY_WFE  Enter Stop 0 or Stop 1 mode with WFE instruction.
00575   * @retval None
00576   */
00577 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
00578 {
00579   /* Check the parameters */
00580   assert_param(IS_PWR_REGULATOR(Regulator));
00581
00582   if(Regulator == PWR_LOWPOWERREGULATOR_ON)
00583   {
00584     HAL_PWREx_EnterSTOP1Mode(STOPEntry);
00585   }
00586   else
00587   {
00588     HAL_PWREx_EnterSTOP0Mode(STOPEntry);
00589   }
00590 }
00591
00592
00593 /**
00594   * @brief Enter Standby mode.
00595   * @note  In Standby mode, the PLL, the HSI, the MSI and the HSE oscillators are switched
00596   *        off. The voltage regulator is disabled, except when BKRAM content is preserved
00597   *        in which case the regulator is in low-power mode.
00598   *        SRAM and register contents are lost except for registers in the Backup domain and
00599   *        Standby circuitry. BKRAM content can be preserved if the bit RRS is set in PWR_CR3 register.
00600   *        To enable this feature, the user can resort to HAL_PWREx_EnableBKRAMContentRetention() API
00601   *        to set RRS bit.
00602   *        The BOR is available.
00603   * @note  The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
00604   *        HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and
00605   *        Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the
00606   *        same.
00607   *        These states are effective in Standby mode only if APC bit is set through
00608   *        HAL_PWREx_EnablePullUpPullDownConfig() API.
00609   * @note  According to system power policy, system entering in Standby mode
00610   *        is depending on other CPU power mode.
00611   * @retval None
00612   */
00613 void HAL_PWR_EnterSTANDBYMode(void)
00614 {
00615   /* Set Stand-by mode */
00616   MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STANDBY);
00617
00618   /* Set SLEEPDEEP bit of Cortex System Control Register */
00619   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00620
00621 /* This option is used to ensure that store operations are completed */
00622 #if defined ( __CC_ARM)
00623   __force_stores();
00624 #endif
00625
00626   /* Request Wait For Interrupt */
00627   __WFI();
00628
00629   /* Following code is executed after wake up if system did not go to STANDBY
00630      mode according to system power policy */
00631
00632   /* Reset SLEEPDEEP bit of Cortex System Control Register */
00633   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00634 }
00635
00636 /**
00637   * @brief  Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.
00638   * @note   Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
00639   *         re-enters SLEEP mode when an interruption handling is over.
00640   *         Setting this bit is useful when the processor is expected to run only on
00641   *         interruptions handling.
00642   * @retval None
00643   */
00644 void HAL_PWR_EnableSleepOnExit(void)
00645 {
00646   /* Set SLEEPONEXIT bit of Cortex System Control Register */
00647   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
00648 }
00649
00650 /**
00651   * @brief  Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
00652   * @note   Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor
00653   *         re-enters SLEEP mode when an interruption handling is over.
00654   * @retval None
00655   */
00656 void HAL_PWR_DisableSleepOnExit(void)
00657 {
00658   /* Clear SLEEPONEXIT bit of Cortex System Control Register */
00659   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
00660 }
00661
00662
00663 /**
00664   * @brief Enable CORTEX M4 SEVONPEND bit.
00665   * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes
00666   *       WFE to wake up when an interrupt moves from inactive to pended.
00667   * @retval None
00668   */
00669 void HAL_PWR_EnableSEVOnPend(void)
00670 {
00671   /* Set SEVONPEND bit of Cortex System Control Register */
00672   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
00673 }
00674
00675
00676 /**
00677   * @brief Disable CORTEX M4 SEVONPEND bit.
00678   * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes
00679   *       WFE to wake up when an interrupt moves from inactive to pended.
00680   * @retval None
00681   */
00682 void HAL_PWR_DisableSEVOnPend(void)
00683 {
00684   /* Clear SEVONPEND bit of Cortex System Control Register */
00685   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
00686 }
00687
00688
00689 /**
00690   * @brief  PWR PVD interrupt callback
00691   * @retval None
00692   */
00693 __weak void HAL_PWR_PVDCallback(void)
00694 {
00695   /* NOTE : This function should not be modified; when the callback is needed,
00696             the HAL_PWR_PVDCallback can be implemented in the user file
00697   */
00698 }
00699
00700 /**
00701   * @}
00702   */
00703
00704 /**
00705   * @}
00706   */
00707
00708 #endif /* HAL_PWR_MODULE_ENABLED */
00709 /**
00710   * @}
00711   */
00712
00713 /**
00714   * @}
00715   */
00716
00717 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_pwr.h Source File

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stm32wbxx_hal_pwr.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_pwr.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of PWR HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_PWR_H
00022 #define STM32WBxx_HAL_PWR_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 /* Include low level driver */
00032 #include "stm32wbxx_ll_pwr.h"
00033 #include "stm32wbxx_ll_exti.h"
00034
00035 /** @addtogroup STM32WBxx_HAL_Driver
00036   * @{
00037   */
00038
00039 /** @defgroup PWR PWR
00040   * @brief PWR HAL module driver
00041   * @{
00042   */
00043
00044 /* Exported types ------------------------------------------------------------*/
00045 /** @defgroup PWR_Exported_Types PWR Exported Types
00046   * @{
00047   */
00048
00049 /**
00050   * @brief  PWR PVD configuration structure definition
00051   */
00052 typedef struct
00053 {
00054   uint32_t PVDLevel;       /*!< PVDLevel: Specifies the PVD detection level.
00055                                 This parameter can be a value of @ref PWR_PVD_detection_level. */
00056
00057   uint32_t Mode;           /*!< Mode: Specifies the operating mode for the selected pins.
00058                                 This parameter can be a value of @ref PWR_PVD_Mode. */
00059 }PWR_PVDTypeDef;
00060
00061 /**
00062   * @}
00063   */
00064
00065 /* Exported constants --------------------------------------------------------*/
00066 /** @defgroup PWR_Exported_Constants PWR Exported Constants
00067   * @{
00068   */
00069
00070 /** @defgroup PWR_PVD_detection_level  Power Voltage Detector Level selection
00071   * @note     Refer datasheet for selection voltage value
00072   * @{
00073   */
00074 #define PWR_PVDLEVEL_0                  (0x00000000U)                                    /*!< PVD threshold around 2.0 V */
00075 #define PWR_PVDLEVEL_1                  (                                PWR_CR2_PLS_0)  /*!< PVD threshold around 2.2 V */
00076 #define PWR_PVDLEVEL_2                  (                PWR_CR2_PLS_1                )  /*!< PVD threshold around 2.4 V */
00077 #define PWR_PVDLEVEL_3                  (                PWR_CR2_PLS_1 | PWR_CR2_PLS_0)  /*!< PVD threshold around 2.5 V */
00078 #define PWR_PVDLEVEL_4                  (PWR_CR2_PLS_2                                )  /*!< PVD threshold around 2.6 V */
00079 #define PWR_PVDLEVEL_5                  (PWR_CR2_PLS_2                 | PWR_CR2_PLS_0)  /*!< PVD threshold around 2.8 V */
00080 #define PWR_PVDLEVEL_6                  (PWR_CR2_PLS_2 | PWR_CR2_PLS_1                )  /*!< PVD threshold around 2.9 V */
00081 #define PWR_PVDLEVEL_7                  (PWR_CR2_PLS_2 | PWR_CR2_PLS_1 | PWR_CR2_PLS_0)  /*!< External input analog voltage (compared internally to VREFINT) */
00082 /**
00083   * @}
00084   */
00085
00086 /** @defgroup PWR_PVD_Mode  PWR PVD interrupt and event mode
00087   * @{
00088   */
00089 /* Note: On STM32WB serie, power PVD event is not available on AIEC lines     */
00090 /*       (only interruption is available through AIEC line 16).               */
00091 #define PWR_PVD_MODE_NORMAL                 (0x00000000U)                           /*!< Basic mode is used */
00092
00093 #define PWR_PVD_MODE_IT_RISING              (PVD_MODE_IT | PVD_RISING_EDGE)         /*!< External Interrupt Mode with Rising edge trigger detection */
00094 #define PWR_PVD_MODE_IT_FALLING             (PVD_MODE_IT | PVD_FALLING_EDGE)        /*!< External Interrupt Mode with Falling edge trigger detection */
00095 #define PWR_PVD_MODE_IT_RISING_FALLING      (PVD_MODE_IT | PVD_RISING_FALLING_EDGE) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
00096 /**
00097   * @}
00098   */
00099
00100 /* Note: On STM32WB serie, power PVD event is not available on AIEC lines     */
00101 /*       (only interruption is available through AIEC line 16).               */
00102
00103 /** @defgroup PWR_Low_Power_Mode_Selection  PWR Low Power Mode Selection
00104   * @{
00105   */
00106 #define PWR_LOWPOWERMODE_STOP0              (0x00000000u)                         /*!< Stop 0: stop mode with main regulator */
00107 #define PWR_LOWPOWERMODE_STOP1              (PWR_CR1_LPMS_0)                      /*!< Stop 1: stop mode with low power regulator */
00108 #define PWR_LOWPOWERMODE_STOP2              (PWR_CR1_LPMS_1)                      /*!< Stop 2: stop mode with low power regulator and VDD12I interruptible digital core domain supply OFF (less peripherals activated than low power mode stop 1 to reduce power consumption)*/
00109 #define PWR_LOWPOWERMODE_STANDBY            (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1)     /*!< Standby mode */
00110 #define PWR_LOWPOWERMODE_SHUTDOWN           (PWR_CR1_LPMS_2)                      /*!< Shutdown mode */
00111 /**
00112   * @}
00113   */
00114
00115 /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode  PWR regulator mode
00116   * @{
00117   */
00118 #define PWR_MAINREGULATOR_ON                (0x00000000U)               /*!< Regulator in main mode      */
00119 #define PWR_LOWPOWERREGULATOR_ON            (PWR_CR1_LPR)               /*!< Regulator in low-power mode */
00120 /**
00121   * @}
00122   */
00123
00124 /** @defgroup PWR_SLEEP_mode_entry  PWR SLEEP mode entry
00125   * @{
00126   */
00127 #define PWR_SLEEPENTRY_WFI                  ((uint8_t)0x01)         /*!< Wait For Interruption instruction to enter Sleep mode */
00128 #define PWR_SLEEPENTRY_WFE                  ((uint8_t)0x02)         /*!< Wait For Event instruction to enter Sleep mode        */
00129 /**
00130   * @}
00131   */
00132
00133 /** @defgroup PWR_STOP_mode_entry  PWR STOP mode entry
00134   * @{
00135   */
00136 #define PWR_STOPENTRY_WFI                   ((uint8_t)0x01)         /*!< Wait For Interruption instruction to enter Stop mode */
00137 #define PWR_STOPENTRY_WFE                   ((uint8_t)0x02)         /*!< Wait For Event instruction to enter Stop mode        */
00138 /**
00139   * @}
00140   */
00141
00142 /**
00143   * @}
00144   */
00145
00146 /* Private define ------------------------------------------------------------*/
00147 /** @defgroup PWR_Private_Defines PWR Private Defines
00148   * @{
00149   */
00150
00151 /** @defgroup PWR_PVD_EXTI_LINE  PWR PVD external interrupt line
00152   * @{
00153   */
00154 #define PWR_EXTI_LINE_PVD  (LL_EXTI_LINE_16)   /*!< External interrupt line 16 Connected to the PWR PVD */
00155 /**
00156   * @}
00157   */
00158
00159 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
00160   * @{
00161   */
00162 /* Note: On STM32WB serie, power PVD event is not available on AIEC lines     */
00163 /*       (only interruption is available through AIEC line 16).               */
00164 #define PVD_MODE_IT               (0x00010000U)  /*!< Mask for interruption yielded by PVD threshold crossing */
00165 #define PVD_RISING_EDGE           (0x00000001U)  /*!< Mask for rising edge set as PVD trigger                 */
00166 #define PVD_FALLING_EDGE          (0x00000002U)  /*!< Mask for falling edge set as PVD trigger                */
00167 #define PVD_RISING_FALLING_EDGE   (0x00000003U)  /*!< Mask for rising and falling edges set as PVD trigger    */
00168 /**
00169   * @}
00170   */
00171
00172 /**
00173   * @}
00174   */
00175
00176 /* Exported macros -----------------------------------------------------------*/
00177 /** @defgroup PWR_Exported_Macros  PWR Exported Macros
00178   * @{
00179   */
00180 /** @brief  Check whether or not a specific PWR flag is set.
00181   * @param __FLAG__ specifies the flag to check.
00182   *           This parameter can be one of the following values:
00183   *
00184   *            /--------------------------------SR1-------------------------------/
00185   *            @arg @ref PWR_FLAG_WUF1  Wake Up Flag 1. Indicates that a wakeup event
00186   *                                     was received from the WKUP pin 1.
00187   *            @arg @ref PWR_FLAG_WUF2  Wake Up Flag 2. Indicates that a wakeup event
00188   *                                     was received from the WKUP pin 2.
00189   *            @arg @ref PWR_FLAG_WUF3  Wake Up Flag 3. Indicates that a wakeup event
00190   *                                     was received from the WKUP pin 3.
00191   *            @arg @ref PWR_FLAG_WUF4  Wake Up Flag 4. Indicates that a wakeup event
00192   *                                     was received from the WKUP pin 4.
00193   *            @arg @ref PWR_FLAG_WUF5  Wake Up Flag 5. Indicates that a wakeup event
00194   *                                     was received from the WKUP pin 5.
00195   *
00196   *            @arg @ref PWR_FLAG_BHWF      BLE_Host WakeUp Flag
00197   *            @arg @ref PWR_FLAG_FRCBYPI   SMPS Forced in Bypass Interrupt Flag
00198   *            @arg @ref PWR_FLAG_RFPHASEI  Radio Phase Interrupt Flag
00199   *            @arg @ref PWR_FLAG_BLEACTI   BLE Activity Interrupt Flag
00200   *            @arg @ref PWR_FLAG_802ACTI   802.15.4 Activity Interrupt Flag
00201   *            @arg @ref PWR_FLAG_HOLDC2I   CPU2 on-Hold Interrupt Flag
00202   *            @arg @ref PWR_FLAG_WUFI      Wake-Up Flag Internal. Set when a wakeup is detected on
00203   *                                         the internal wakeup line.
00204   *
00205   *            @arg @ref PWR_FLAG_SMPSRDYF  SMPS Ready Flag
00206   *            @arg @ref PWR_FLAG_SMPSBYPF  SMPS Bypass Flag
00207   *
00208   *            /--------------------------------SR2-------------------------------/
00209   *            @arg @ref PWR_FLAG_REGLPS Low Power Regulator Started. Indicates whether or not the
00210   *                                      low-power regulator is ready.
00211   *            @arg @ref PWR_FLAG_REGLPF Low Power Regulator Flag. Indicates whether the
00212   *                                      regulator is ready in main mode or is in low-power mode.
00213   *
00214   *            @arg @ref PWR_FLAG_VOSF   Voltage Scaling Flag. Indicates whether the regulator is ready
00215   *                                      in the selected voltage range or is still changing to the required voltage level.
00216   *            @arg @ref PWR_FLAG_PVDO   Power Voltage Detector Output. Indicates whether VDD voltage is
00217   *                                      below or above the selected PVD threshold.
00218   *
00219   *            @arg @ref PWR_FLAG_PVMO1 Peripheral Voltage Monitoring Output 1. Indicates whether VDDUSB voltage is
00220   *                                     is below or above PVM1 threshold (applicable when USB feature is supported).
00221   *            @arg @ref PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3. Indicates whether VDDA voltage is
00222   *                                     is below or above PVM3 threshold.
00223   *
00224   *           /----------------------------EXTSCR--------------------------/
00225   *            @arg @ref PWR_FLAG_STOP              System Stop Flag for CPU1.
00226   *            @arg @ref PWR_FLAG_SB                System Standby Flag for CPU1.
00227   *
00228   *            @arg @ref PWR_FLAG_C2STOP            System Stop Flag for CPU2.
00229   *            @arg @ref PWR_FLAG_C2SB              System Standby Flag for CPU2.
00230   *
00231   *            @arg @ref PWR_FLAG_CRITICAL_RF_PHASE Critical radio system phase flag.
00232   *
00233   *            @arg @ref PWR_FLAG_C1DEEPSLEEP       CPU1 DeepSleep Flag.
00234   *            @arg @ref PWR_FLAG_C2DEEPSLEEP       CPU2 DeepSleep Flag.
00235   *
00236   * @retval The new state of __FLAG__ (TRUE or FALSE).
00237   */
00238 #define __HAL_PWR_GET_FLAG(__FLAG__)  ( ((((uint8_t)(__FLAG__)) >> 5U) == 1U)  ?\
00239                                       (PWR->SR1 & (1U << ((__FLAG__) & 31U))) :\
00240                                       ((((((uint8_t)(__FLAG__)) >> 5U) == 2U)) ?\
00241                                       (PWR->SR2 & (1U << ((__FLAG__) & 31U))) :\
00242                                       (PWR->EXTSCR & (1U << ((__FLAG__) & 31U))) ) )
00243
00244
00245 /** @brief  Clear a specific PWR flag.
00246   * @note   Clearing of flags {PWR_FLAG_STOP, PWR_FLAG_SB}
00247   *         and flags {PWR_FLAG_C2STOP, PWR_FLAG_C2SB} are grouped:
00248   *         clearing of one flag also clears the other one.
00249   * @param __FLAG__ specifies the flag to clear.
00250   *          This parameter can be one of the following values:
00251   *
00252   *            /--------------------------------SCR (SRR)------------------------------/
00253   *            @arg @ref PWR_FLAG_WUF1  Wake Up Flag 1. Indicates that a wakeup event
00254   *                                     was received from the WKUP pin 1.
00255   *            @arg @ref PWR_FLAG_WUF2  Wake Up Flag 2. Indicates that a wakeup event
00256   *                                     was received from the WKUP pin 2.
00257   *            @arg @ref PWR_FLAG_WUF3  Wake Up Flag 3. Indicates that a wakeup event
00258   *                                     was received from the WKUP pin 3.
00259   *            @arg @ref PWR_FLAG_WUF4  Wake Up Flag 4. Indicates that a wakeup event
00260   *                                     was received from the WKUP pin 4.
00261   *            @arg @ref PWR_FLAG_WUF5  Wake Up Flag 5. Indicates that a wakeup event
00262   *                                     was received from the WKUP pin 5.
00263   *            @arg @ref PWR_FLAG_WU    Encompasses all five Wake Up Flags.
00264   *
00265   *            @arg @ref PWR_FLAG_BHWF      Clear BLE_Host Wakeup Flag.
00266   *            @arg @ref PWR_FLAG_FRCBYPI   Clear SMPS Forced in Bypass Interrupt Flag.
00267   *            @arg @ref PWR_FLAG_RFPHASEI  RF Phase Interrupt Clear.
00268   *            @arg @ref PWR_FLAG_BLEACTI   BLE Activity Interrupt Clear.
00269   *            @arg @ref PWR_FLAG_802ACTI   802.15.4. Activity Interrupt Clear.
00270   *            @arg @ref PWR_FLAG_HOLDC2I   CPU2 on-Hold Interrupt Clear.
00271   *
00272   *           /----------------------------EXTSCR--------------------------/
00273   *            @arg @ref PWR_FLAG_STOP      System Stop Flag for CPU1.
00274   *            @arg @ref PWR_FLAG_SB        System Standby Flag for CPU1.
00275   *
00276   *            @arg @ref PWR_FLAG_C2STOP    System Stop Flag for CPU2.
00277   *            @arg @ref PWR_FLAG_C2SB      System Standby Flag for CPU2.
00278   *
00279   *            @arg @ref PWR_FLAG_CRITICAL_RF_PHASE  RF phase Flag.
00280   *
00281   * @retval None
00282   */
00283 #define __HAL_PWR_CLEAR_FLAG(__FLAG__)   ( ((((uint8_t)(__FLAG__)) >> 5U) == 1U) ?\
00284                                          ( (((uint8_t)(__FLAG__)) == PWR_FLAG_WU) ?\
00285                                          (PWR->SCR  = (__FLAG__)) : (PWR->SCR = (1U << ((__FLAG__) & 31U))) ) :\
00286                                          ( (((uint8_t)(__FLAG__)) == PWR_FLAG_CRITICAL_RF_PHASE) ?\
00287                                          SET_BIT (PWR->EXTSCR, PWR_EXTSCR_CCRPF) : ( ((((uint8_t)((__FLAG__)) & 31U) <= PWR_EXTSCR_C1STOPF_Pos) ?\
00288                                          SET_BIT (PWR->EXTSCR, PWR_EXTSCR_C1CSSF): SET_BIT (PWR->EXTSCR, PWR_EXTSCR_C2CSSF)) ) ))
00289
00290 /**
00291   * @brief Enable the PVD Extended Interrupt C1 Line.
00292   * @retval None
00293   */
00294 #define __HAL_PWR_PVD_EXTI_ENABLE_IT()   LL_EXTI_EnableIT_0_31(PWR_EXTI_LINE_PVD)
00295
00296 /**
00297   * @brief Enable the PVD Extended Interrupt C2 Line.
00298   * @retval None
00299   */
00300 #define __HAL_PWR_PVD_EXTIC2_ENABLE_IT()   LL_C2_EXTI_EnableIT_0_31(PWR_EXTI_LINE_PVD)
00301
00302
00303 /**
00304   * @brief Disable the PVD Extended Interrupt C1 Line.
00305   * @retval None
00306   */
00307 #define __HAL_PWR_PVD_EXTI_DISABLE_IT()  LL_EXTI_DisableIT_0_31(PWR_EXTI_LINE_PVD)
00308
00309 /**
00310   * @brief Disable the PVD Extended Interrupt C2 Line.
00311   * @retval None
00312   */
00313 #define __HAL_PWR_PVD_EXTIC2_DISABLE_IT()  LL_C2_EXTI_DisableIT_0_31(PWR_EXTI_LINE_PVD)
00314
00315 /* Note: On STM32WB serie, power PVD event is not available on AIEC lines     */
00316 /*       (only interruption is available through AIEC line 16).               */
00317
00318 /**
00319   * @brief Enable the PVD Extended Interrupt Rising Trigger.
00320   * @note  PVD flag polarity is inverted compared to EXTI line, therefore
00321   *        EXTI rising and falling logic edges are inverted versus PVD voltage edges.
00322   * @retval None
00323   */
00324 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()   LL_EXTI_EnableRisingTrig_0_31(PWR_EXTI_LINE_PVD)
00325
00326 /**
00327   * @brief Disable the PVD Extended Interrupt Rising Trigger.
00328   * @note  PVD flag polarity is inverted compared to EXTI line, therefore
00329   *        EXTI rising and falling logic edges are inverted versus PVD voltage edges.
00330   * @retval None
00331   */
00332 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE()  LL_EXTI_DisableFallingTrig_0_31(PWR_EXTI_LINE_PVD)
00333
00334 /**
00335   * @brief Enable the PVD Extended Interrupt Falling Trigger.
00336   * @note  PVD flag polarity is inverted compared to EXTI line, therefore
00337   *        EXTI rising and falling logic edges are inverted versus PVD voltage edges.
00338   * @retval None
00339   */
00340 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()   LL_EXTI_EnableFallingTrig_0_31(PWR_EXTI_LINE_PVD)
00341
00342
00343 /**
00344   * @brief Disable the PVD Extended Interrupt Falling Trigger.
00345   * @note  PVD flag polarity is inverted compared to EXTI line, therefore
00346   *        EXTI rising and falling logic edges are inverted versus PVD voltage edges.
00347   * @retval None
00348   */
00349 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()  LL_EXTI_DisableRisingTrig_0_31(PWR_EXTI_LINE_PVD)
00350
00351
00352 /**
00353   * @brief  Enable the PVD Extended Interrupt Rising & Falling Trigger.
00354   * @retval None
00355   */
00356 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()  \
00357   do {                                                   \
00358     __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();             \
00359     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();            \
00360   } while(0)
00361
00362 /**
00363   * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
00364   * @retval None
00365   */
00366 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()  \
00367   do {                                                    \
00368     __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();             \
00369     __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();            \
00370   } while(0)
00371
00372 /**
00373   * @brief  Generate a Software interrupt on selected EXTI line.
00374   * @retval None
00375   */
00376 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(PWR_EXTI_LINE_PVD)
00377
00378 /**
00379   * @brief Check whether or not the PVD EXTI interrupt flag is set.
00380   * @retval EXTI PVD Line Status.
00381   */
00382 #define __HAL_PWR_PVD_EXTI_GET_FLAG()  LL_EXTI_ReadFlag_0_31(PWR_EXTI_LINE_PVD)
00383
00384 /**
00385   * @brief Clear the PVD EXTI interrupt flag.
00386   * @retval None
00387   */
00388 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG()  LL_EXTI_ClearFlag_0_31(PWR_EXTI_LINE_PVD)
00389
00390 /**
00391   * @}
00392   */
00393
00394
00395 /* Private macros --------------------------------------------------------*/
00396 /** @defgroup PWR_Private_Macros  PWR Private Macros
00397   * @{
00398   */
00399
00400 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
00401                                  ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
00402                                  ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
00403                                  ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
00404
00405 #define IS_PWR_PVD_MODE(MODE)  (((MODE) == PWR_PVD_MODE_NORMAL)              ||\
00406                                 ((MODE) == PWR_PVD_MODE_IT_RISING)           ||\
00407                                 ((MODE) == PWR_PVD_MODE_IT_FALLING)          ||\
00408                                 ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING))
00409
00410
00411
00412 #define IS_PWR_REGULATOR(REGULATOR)               (((REGULATOR) == PWR_MAINREGULATOR_ON)    || \
00413                                                    ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
00414
00415
00416 #define IS_PWR_SLEEP_ENTRY(ENTRY)                 (((ENTRY) == PWR_SLEEPENTRY_WFI) || \
00417                                                    ((ENTRY) == PWR_SLEEPENTRY_WFE))
00418
00419 #define IS_PWR_STOP_ENTRY(ENTRY)                  (((ENTRY) == PWR_STOPENTRY_WFI) || \
00420                                                    ((ENTRY) == PWR_STOPENTRY_WFE))
00421 /**
00422   * @}
00423   */
00424
00425 /* Include PWR HAL Extended module */
00426 #include "stm32wbxx_hal_pwr_ex.h"
00427
00428 /* Exported functions --------------------------------------------------------*/
00429 /** @defgroup PWR_Exported_Functions  PWR Exported Functions
00430   * @{
00431   */
00432
00433 /** @defgroup PWR_Exported_Functions_Group1  Initialization and de-initialization functions
00434   * @{
00435   */
00436
00437 /* Initialization and de-initialization functions *******************************/
00438 void              HAL_PWR_DeInit(void);
00439
00440 void              HAL_PWR_EnableBkUpAccess(void);
00441 void              HAL_PWR_DisableBkUpAccess(void);
00442 /**
00443   * @}
00444   */
00445
00446 /** @defgroup PWR_Exported_Functions_Group2  Peripheral Control functions
00447   * @{
00448   */
00449 /* Peripheral Control functions  ************************************************/
00450 HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
00451 void              HAL_PWR_EnablePVD(void);
00452 void              HAL_PWR_DisablePVD(void);
00453
00454 /* WakeUp pins configuration functions ****************************************/
00455 void              HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
00456 void              HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
00457
00458 /* Low Power modes configuration functions ************************************/
00459 void              HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
00460 void              HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
00461 void              HAL_PWR_EnterSTANDBYMode(void);
00462
00463 void              HAL_PWR_PVDCallback(void);
00464 void              HAL_PWR_EnableSleepOnExit(void);
00465 void              HAL_PWR_DisableSleepOnExit(void);
00466
00467 void              HAL_PWR_EnableSEVOnPend(void);
00468 void              HAL_PWR_DisableSEVOnPend(void);
00469
00470
00471 /**
00472   * @}
00473   */
00474
00475 /**
00476   * @}
00477   */
00478
00479 /**
00480   * @}
00481   */
00482
00483 /**
00484   * @}
00485   */
00486
00487 /**
00488   * @}
00489   */
00490
00491 #ifdef __cplusplus
00492 }
00493 #endif
00494
00495
00496 #endif /* STM32WBxx_HAL_PWR_H */
00497
00498 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:34 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_pwr_ex.c Source File

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stm32wbxx_hal_pwr_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_pwr_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended PWR HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Power Controller (PWR) peripheral:
00008   *           + Extended Initialization and de-initialization functions
00009   *           + Extended Peripheral Control functions
00010   *
00011   ******************************************************************************
00012   * @attention
00013   *
00014   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00015   * All rights reserved.</center></h2>
00016   *
00017   * This software component is licensed by ST under BSD 3-Clause license,
00018   * the "License"; You may not use this file except in compliance with the
00019   * License. You may obtain a copy of the License at:
00020   *                        opensource.org/licenses/BSD-3-Clause
00021   *
00022   ******************************************************************************
00023   */
00024
00025 /* Includes ------------------------------------------------------------------*/
00026 #include "stm32wbxx_hal.h"
00027
00028 /** @addtogroup STM32WBxx_HAL_Driver
00029   * @{
00030   */
00031
00032 /** @addtogroup PWREx
00033   * @{
00034   */
00035
00036 #ifdef HAL_PWR_MODULE_ENABLED
00037
00038 /* Private typedef -----------------------------------------------------------*/
00039 /* Private define ------------------------------------------------------------*/
00040 /** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines
00041   * @{
00042   */
00043 #define PWR_PORTE_AVAILABLE_PINS   (PWR_GPIO_BIT_4 | PWR_GPIO_BIT_3 | PWR_GPIO_BIT_2 | PWR_GPIO_BIT_1 | PWR_GPIO_BIT_0)
00044 #define PWR_PORTH_AVAILABLE_PINS   (PWR_GPIO_BIT_3 | PWR_GPIO_BIT_1 | PWR_GPIO_BIT_0)
00045
00046 /** @defgroup PWREx_TimeOut_Value PWR Extended Flag Setting Time Out Value
00047   * @{
00048   */
00049 #define PWR_FLAG_SETTING_DELAY_US                      50U   /*!< Time out value for REGLPF and VOSF flags setting */
00050 /**
00051   * @}
00052   */
00053
00054 /**
00055   * @}
00056   */
00057
00058
00059
00060 /* Private macro -------------------------------------------------------------*/
00061 /* Private variables ---------------------------------------------------------*/
00062 /* Private function prototypes -----------------------------------------------*/
00063 /* Exported functions --------------------------------------------------------*/
00064 /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions
00065   * @{
00066   */
00067
00068 /** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
00069   *  @brief   Extended Peripheral Control functions
00070   *
00071 @verbatim
00072  ===============================================================================
00073               ##### Extended Peripheral Initialization and de-initialization functions #####
00074  ===============================================================================
00075     [..]
00076
00077 @endverbatim
00078   * @{
00079   */
00080
00081
00082 #if defined(PWR_CR1_VOS)
00083 /**
00084   * @brief Return Voltage Scaling Range.
00085   * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2)
00086   */
00087 uint32_t HAL_PWREx_GetVoltageRange(void)
00088 {
00089   return  (PWR->CR1 & PWR_CR1_VOS);
00090 }
00091
00092 /**
00093   * @brief Configure the main internal regulator output voltage.
00094   * @param VoltageScaling specifies the regulator output voltage to achieve
00095   *         a tradeoff between performance and power consumption.
00096   *          This parameter can be one of the following values:
00097   *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode,
00098   *                                                typical output voltage at 1.2 V,
00099   *                                                system frequency up to 64 MHz.
00100   *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode,
00101   *                                                typical output voltage at 1.0 V,
00102   *                                                system frequency up to 16 MHz.
00103   * @note  When moving from Range 1 to Range 2, the system frequency must be decreased to
00104   *        a value below 16 MHz before calling HAL_PWREx_ControlVoltageScaling() API.
00105   *        When moving from Range 2 to Range 1, the system frequency can be increased to
00106   *        a value up to 64 MHz after calling HAL_PWREx_ControlVoltageScaling() API.
00107   * @note  When moving from Range 2 to Range 1, the API waits for VOSF flag to be
00108   *        cleared before returning the status. If the flag is not cleared within
00109   *        50 microseconds, HAL_TIMEOUT status is reported.
00110   * @retval HAL Status
00111   */
00112 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
00113 {
00114   uint32_t wait_loop_index;
00115
00116   assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
00117
00118   /* If Set Range 1 */
00119   if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
00120   {
00121     if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1)
00122     {
00123       /* Set Range 1 */
00124       MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
00125
00126       /* Wait until VOSF is cleared */
00127       wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000U));
00128       while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
00129       {
00130         wait_loop_index--;
00131       }
00132       if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
00133       {
00134         return HAL_TIMEOUT;
00135       }
00136     }
00137   }
00138   else
00139   {
00140     if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2)
00141     {
00142       /* Set Range 2 */
00143       MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
00144       /* No need to wait for VOSF to be cleared for this transition */
00145     }
00146   }
00147
00148   return HAL_OK;
00149 }
00150 #endif
00151
00152 /****************************************************************************/
00153
00154 /**
00155   * @brief Enable battery charging.
00156   *        When VDD is present, charge the external battery on VBAT thru an internal resistor.
00157   * @param ResistorSelection specifies the resistor impedance.
00158   *          This parameter can be one of the following values:
00159   *            @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5     5 kOhms resistor
00160   *            @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor
00161   * @retval None
00162   */
00163 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection)
00164 {
00165   assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection));
00166
00167   /* Specify resistor selection */
00168   MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection);
00169
00170   /* Enable battery charging */
00171   SET_BIT(PWR->CR4, PWR_CR4_VBE);
00172 }
00173
00174 /**
00175   * @brief Disable battery charging.
00176   * @retval None
00177   */
00178 void HAL_PWREx_DisableBatteryCharging(void)
00179 {
00180   CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
00181 }
00182
00183 /****************************************************************************/
00184 #if defined(PWR_CR2_PVME1)
00185 /**
00186   * @brief Enable VDDUSB supply.
00187   * @note  Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present.
00188   * @retval None
00189   */
00190 void HAL_PWREx_EnableVddUSB(void)
00191 {
00192   SET_BIT(PWR->CR2, PWR_CR2_USV);
00193 }
00194
00195 /**
00196   * @brief Disable VDDUSB supply.
00197   * @retval None
00198   */
00199 void HAL_PWREx_DisableVddUSB(void)
00200 {
00201   CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
00202 }
00203 #endif
00204
00205 /****************************************************************************/
00206
00207 /**
00208   * @brief Enable Internal Wake-up Line.
00209   * @retval None
00210   */
00211 void HAL_PWREx_EnableInternalWakeUpLine(void)
00212 {
00213   SET_BIT(PWR->CR3, PWR_CR3_EIWUL);
00214 }
00215
00216 /**
00217   * @brief Disable Internal Wake-up Line.
00218   * @retval None
00219   */
00220 void HAL_PWREx_DisableInternalWakeUpLine(void)
00221 {
00222   CLEAR_BIT(PWR->CR3, PWR_CR3_EIWUL);
00223 }
00224
00225 #if defined(PWR_CR5_SMPSEN)
00226 /**
00227   * @brief Enable BORH and SMPS step down converter forced in bypass mode
00228   *        interrupt for CPU1
00229   * @retval None
00230   */
00231 void HAL_PWREx_EnableBORH_SMPSBypassIT(void)
00232 {
00233   SET_BIT(PWR->CR3, PWR_CR3_EBORHSMPSFB);
00234 }
00235
00236 /**
00237   * @brief Disable BORH and SMPS step down converter forced in bypass mode
00238   *        interrupt for CPU1
00239   * @retval None
00240   */
00241 void HAL_PWREx_DisableBORH_SMPSBypassIT(void)
00242 {
00243   CLEAR_BIT(PWR->CR3, PWR_CR3_EBORHSMPSFB);
00244 }
00245 #endif
00246
00247 /**
00248   * @brief Enable RF Phase interrupt.
00249   * @retval None
00250   */
00251 void HAL_PWREx_EnableRFPhaseIT(void)
00252 {
00253   SET_BIT(PWR->CR3, PWR_CR3_ECRPE_Msk);
00254 }
00255
00256 /**
00257   * @brief Disable RF Phase interrupt.
00258   * @retval None
00259   */
00260 void HAL_PWREx_DisableRFPhaseIT(void)
00261 {
00262   CLEAR_BIT(PWR->CR3, PWR_CR3_ECRPE_Msk);
00263 }
00264
00265
00266 /**
00267   * @brief Enable BLE Activity interrupt.
00268   * @retval None
00269   */
00270 void HAL_PWREx_EnableBLEActivityIT(void)
00271 {
00272   SET_BIT(PWR->CR3, PWR_CR3_EBLEA);
00273 }
00274
00275 /**
00276   * @brief Disable BLE Activity interrupt.
00277   * @retval None
00278   */
00279 void HAL_PWREx_DisableBLEActivityIT(void)
00280 {
00281   CLEAR_BIT(PWR->CR3, PWR_CR3_EBLEA);
00282 }
00283
00284
00285 /**
00286   * @brief Enable 802.15.4 Activity interrupt.
00287   * @retval None
00288   */
00289 void HAL_PWREx_Enable802ActivityIT(void)
00290 {
00291   SET_BIT(PWR->CR3, PWR_CR3_E802A);
00292 }
00293
00294 /**
00295   * @brief Disable 802.15.4 Activity interrupt.
00296   * @retval None
00297   */
00298 void HAL_PWREx_Disable802ActivityIT(void)
00299 {
00300   CLEAR_BIT(PWR->CR3, PWR_CR3_E802A);
00301 }
00302
00303 /**
00304   * @brief Enable CPU2 on-Hold interrupt.
00305   * @retval None
00306   */
00307 void HAL_PWREx_EnableHOLDC2IT(void)
00308 {
00309   SET_BIT(PWR->CR3, PWR_CR3_EC2H);
00310 }
00311
00312 /**
00313   * @brief Disable CPU2 on-Hold interrupt.
00314   * @retval None
00315   */
00316 void HAL_PWREx_DisableHOLDC2IT(void)
00317 {
00318   CLEAR_BIT(PWR->CR3, PWR_CR3_EC2H);
00319 }
00320
00321 /****************************************************************************/
00322
00323 /**
00324   * @brief Enable GPIO pull-up state in Standby and Shutdown modes.
00325   * @note  Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in
00326   *        pull-up state in Standby and Shutdown modes.
00327   * @note  This state is effective in Standby and Shutdown modes only if APC bit
00328   *        is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
00329   * @note  The configuration is lost when exiting the Shutdown mode due to the
00330   *        power-on reset, maintained when exiting the Standby mode.
00331   * @note  To avoid any conflict at Standby and Shutdown modes exits, the corresponding
00332   *        PDy bit of PWR_PDCRx register is cleared unless it is reserved.
00333   * @note  Even if a PUy bit to set is reserved, the other PUy bits entered as input
00334   *        parameter at the same time are set.
00335   * @param GPIO Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H
00336   *         to select the GPIO peripheral.
00337   * @param GPIONumber Specify the I/O pins numbers.
00338   *         This parameter can be one of the following values:
00339   *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less
00340   *         I/O pins are available) or the logical OR of several of them to set
00341   *         several bits for a given port in a single API call.
00342   * @retval HAL Status
00343   */
00344 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
00345 {
00346   HAL_StatusTypeDef status = HAL_OK;
00347
00348   assert_param(IS_PWR_GPIO(GPIO));
00349   assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
00350
00351   switch (GPIO)
00352   {
00353     case PWR_GPIO_A:
00354        SET_BIT(PWR->PUCRA, GPIONumber);
00355        CLEAR_BIT(PWR->PDCRA, GPIONumber);
00356        break;
00357     case PWR_GPIO_B:
00358        SET_BIT(PWR->PUCRB, GPIONumber);
00359        CLEAR_BIT(PWR->PDCRB, GPIONumber);
00360        break;
00361     case PWR_GPIO_C:
00362        SET_BIT(PWR->PUCRC, GPIONumber);
00363        CLEAR_BIT(PWR->PDCRC, GPIONumber);
00364        break;
00365 #if defined(GPIOD)
00366     case PWR_GPIO_D:
00367        SET_BIT(PWR->PUCRD, GPIONumber);
00368        CLEAR_BIT(PWR->PDCRD, GPIONumber);
00369        break;
00370 #endif
00371     case PWR_GPIO_E:
00372        SET_BIT(PWR->PUCRE, (GPIONumber & PWR_PORTE_AVAILABLE_PINS));
00373        CLEAR_BIT(PWR->PDCRE, (GPIONumber & PWR_PORTE_AVAILABLE_PINS));
00374        break;
00375     case PWR_GPIO_H:
00376        SET_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
00377        CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
00378        break;
00379     default:
00380       status = HAL_ERROR;
00381       break;
00382   }
00383
00384   return status;
00385 }
00386
00387 /**
00388   * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes.
00389   * @note  Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O
00390   *        in pull-up state in Standby and Shutdown modes.
00391   * @note  Even if a PUy bit to reset is reserved, the other PUy bits entered as input
00392   *        parameter at the same time are reset.
00393   * @param GPIO Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H
00394   *         to select the GPIO peripheral.
00395   * @param GPIONumber Specify the I/O pins numbers.
00396   *         This parameter can be one of the following values:
00397   *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less
00398   *         I/O pins are available) or the logical OR of several of them to reset
00399   *         several bits for a given port in a single API call.
00400   * @retval HAL Status
00401   */
00402 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
00403 {
00404   HAL_StatusTypeDef status = HAL_OK;
00405
00406   assert_param(IS_PWR_GPIO(GPIO));
00407   assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
00408
00409   switch (GPIO)
00410   {
00411     case PWR_GPIO_A:
00412        CLEAR_BIT(PWR->PUCRA, GPIONumber);
00413        break;
00414     case PWR_GPIO_B:
00415        CLEAR_BIT(PWR->PUCRB, GPIONumber);
00416        break;
00417     case PWR_GPIO_C:
00418        CLEAR_BIT(PWR->PUCRC, GPIONumber);
00419        break;
00420 #if defined(GPIOD)
00421     case PWR_GPIO_D:
00422        CLEAR_BIT(PWR->PUCRD, GPIONumber);
00423        break;
00424 #endif
00425     case PWR_GPIO_E:
00426        CLEAR_BIT(PWR->PUCRE, (GPIONumber & PWR_PORTE_AVAILABLE_PINS));
00427        break;
00428     case PWR_GPIO_H:
00429        CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
00430        break;
00431     default:
00432        status = HAL_ERROR;
00433        break;
00434   }
00435
00436   return status;
00437 }
00438
00439
00440
00441 /**
00442   * @brief Enable GPIO pull-down state in Standby and Shutdown modes.
00443   * @note  Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in
00444   *        pull-down state in Standby and Shutdown modes.
00445   * @note  This state is effective in Standby and Shutdown modes only if APC bit
00446   *        is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
00447   * @note  The configuration is lost when exiting the Shutdown mode due to the
00448   *        power-on reset, maintained when exiting the Standby mode.
00449   * @note  To avoid any conflict at Standby and Shutdown modes exits, the corresponding
00450   *        PUy bit of PWR_PUCRx register is cleared unless it is reserved.
00451   * @note  Even if a PDy bit to set is reserved, the other PDy bits entered as input
00452   *        parameter at the same time are set.
00453   * @param GPIO Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H
00454   *         to select the GPIO peripheral.
00455   * @param GPIONumber Specify the I/O pins numbers.
00456   *         This parameter can be one of the following values:
00457   *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less
00458   *         I/O pins are available) or the logical OR of several of them to set
00459   *         several bits for a given port in a single API call.
00460   * @retval HAL Status
00461   */
00462 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
00463 {
00464   HAL_StatusTypeDef status = HAL_OK;
00465
00466   assert_param(IS_PWR_GPIO(GPIO));
00467   assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
00468
00469   switch (GPIO)
00470   {
00471     case PWR_GPIO_A:
00472        SET_BIT(PWR->PDCRA, GPIONumber);
00473        CLEAR_BIT(PWR->PUCRA, GPIONumber);
00474        break;
00475     case PWR_GPIO_B:
00476        SET_BIT(PWR->PDCRB, GPIONumber);
00477        CLEAR_BIT(PWR->PUCRB, GPIONumber);
00478        break;
00479     case PWR_GPIO_C:
00480        SET_BIT(PWR->PDCRC, GPIONumber);
00481        CLEAR_BIT(PWR->PUCRC, GPIONumber);
00482        break;
00483 #if defined(GPIOD)
00484   case PWR_GPIO_D:
00485        SET_BIT(PWR->PDCRD, GPIONumber);
00486        CLEAR_BIT(PWR->PUCRD, GPIONumber);
00487        break;
00488 #endif
00489     case PWR_GPIO_E:
00490        SET_BIT(PWR->PDCRE, (GPIONumber & PWR_PORTE_AVAILABLE_PINS));
00491        CLEAR_BIT(PWR->PUCRE, (GPIONumber & PWR_PORTE_AVAILABLE_PINS));
00492        break;
00493     case PWR_GPIO_H:
00494        SET_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
00495        CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
00496        break;
00497     default:
00498       status = HAL_ERROR;
00499       break;
00500   }
00501
00502   return status;
00503 }
00504
00505 /**
00506   * @brief Disable GPIO pull-down state in Standby and Shutdown modes.
00507   * @note  Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O
00508   *        in pull-down state in Standby and Shutdown modes.
00509   * @note  Even if a PDy bit to reset is reserved, the other PDy bits entered as input
00510   *        parameter at the same time are reset.
00511   * @param GPIO Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H
00512   *         to select the GPIO peripheral.
00513   * @param GPIONumber Specify the I/O pins numbers.
00514   *         This parameter can be one of the following values:
00515   *         PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less
00516   *         I/O pins are available) or the logical OR of several of them to reset
00517   *         several bits for a given port in a single API call.
00518   * @retval HAL Status
00519   */
00520 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
00521 {
00522   HAL_StatusTypeDef status = HAL_OK;
00523
00524   assert_param(IS_PWR_GPIO(GPIO));
00525   assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
00526
00527   switch (GPIO)
00528   {
00529     case PWR_GPIO_A:
00530        CLEAR_BIT(PWR->PDCRA, GPIONumber);
00531        break;
00532     case PWR_GPIO_B:
00533        CLEAR_BIT(PWR->PDCRB, GPIONumber);
00534        break;
00535     case PWR_GPIO_C:
00536        CLEAR_BIT(PWR->PDCRC, GPIONumber);
00537        break;
00538 #if defined(GPIOD)
00539     case PWR_GPIO_D:
00540        CLEAR_BIT(PWR->PDCRD, GPIONumber);
00541        break;
00542 #endif
00543     case PWR_GPIO_E:
00544        CLEAR_BIT(PWR->PDCRE, (GPIONumber & PWR_PORTE_AVAILABLE_PINS));
00545        break;
00546     case PWR_GPIO_H:
00547       CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
00548        break;
00549     default:
00550       status = HAL_ERROR;
00551       break;
00552   }
00553
00554   return status;
00555 }
00556
00557 /**
00558   * @brief Enable pull-up and pull-down configuration.
00559   * @note  When APC bit is set, the I/O pull-up and pull-down configurations defined in
00560   *        PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes.
00561   * @note  Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding
00562   *        PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher).
00563   *        HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there
00564   *        is no conflict when setting PUy or PDy bit.
00565   * @retval None
00566   */
00567 void HAL_PWREx_EnablePullUpPullDownConfig(void)
00568 {
00569   SET_BIT(PWR->CR3, PWR_CR3_APC);
00570 }
00571
00572 /**
00573   * @brief Disable pull-up and pull-down configuration.
00574   * @note  When APC bit is cleared, the I/O pull-up and pull-down configurations defined in
00575   *        PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes.
00576   * @retval None
00577   */
00578 void HAL_PWREx_DisablePullUpPullDownConfig(void)
00579 {
00580   CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
00581 }
00582
00583 /****************************************************************************/
00584
00585 #if defined(PWR_CR5_SMPSEN)
00586 /**
00587   * @brief  Set BOR configuration
00588   * @param  BORConfiguration This parameter can be one of the following values:
00589   *         @arg @ref PWR_BOR_SYSTEM_RESET
00590   *         @arg @ref PWR_BOR_SMPS_FORCE_BYPASS
00591   */
00592 void HAL_PWREx_SetBORConfig(uint32_t BORConfiguration)
00593 {
00594   LL_PWR_SetBORConfig(BORConfiguration);
00595 }
00596
00597 /**
00598   * @brief  Get BOR configuration
00599   * @retval Returned value can be one of the following values:
00600   *         @arg @ref PWR_BOR_SYSTEM_RESET
00601   *         @arg @ref PWR_BOR_SMPS_FORCE_BYPASS
00602   */
00603 uint32_t HAL_PWREx_GetBORConfig(void)
00604 {
00605   return LL_PWR_GetBORConfig();
00606 }
00607 #endif
00608
00609 /****************************************************************************/
00610 /**
00611   * @brief  Hold the CPU and their allocated peripherals after reset or wakeup from stop or standby.
00612   * @param  CPU: Specifies the core to be held.
00613   *              This parameter can be one of the following values:
00614   *             @arg PWR_CORE_CPU2: Hold CPU2 and set CPU1 as master.
00615   * @note   Hold CPU2 with CPU1 as master by default.
00616   * @retval None
00617   */
00618 void HAL_PWREx_HoldCore(uint32_t CPU)
00619 {
00620   /* Check the parameters */
00621   assert_param(IS_PWR_CORE_HOLD_RELEASE(CPU));
00622
00623   LL_PWR_DisableBootC2();
00624 }
00625
00626 /**
00627   * @brief  Release Cortex CPU2 and allocated peripherals after reset or wakeup from stop or standby.
00628   * @param  CPU: Specifies the core to be released.
00629   *              This parameter can be one of the following values:
00630   *             @arg PWR_CORE_CPU2: Release the CPU2 from holding.
00631   * @retval None
00632   */
00633 void HAL_PWREx_ReleaseCore(uint32_t CPU)
00634 {
00635   /* Check the parameters */
00636   assert_param(IS_PWR_CORE_HOLD_RELEASE(CPU));
00637
00638   LL_PWR_EnableBootC2();
00639 }
00640
00641 /****************************************************************************/
00642 /**
00643   * @brief Enable BKRAM content retention in Standby mode.
00644   * @note  When RRS bit is set, SRAM is powered by the low-power regulator in
00645   *         Standby mode and its content is kept.
00646   * @retval None
00647   */
00648 void HAL_PWREx_EnableSRAMRetention(void)
00649 {
00650   LL_PWR_EnableSRAM2Retention();
00651 }
00652
00653 /**
00654   * @brief Disable BKRAM content retention in Standby mode.
00655   * @note  When RRS bit is reset, SRAM is powered off in Standby mode
00656   *        and its content is lost.
00657   * @retval None
00658   */
00659 void HAL_PWREx_DisableSRAMRetention(void)
00660 {
00661   LL_PWR_DisableSRAM2Retention();
00662 }
00663
00664 /****************************************************************************/
00665 /**
00666   * @brief  Enable Flash Power Down.
00667   * @note   This API allows to enable flash power down capabilities in low power
00668   *         run and low power sleep modes.
00669   * @param  PowerMode this can be a combination of following values:
00670   *           @arg @ref PWR_FLASHPD_LPRUN
00671   *           @arg @ref PWR_FLASHPD_LPSLEEP
00672   * @retval None
00673   */
00674 void HAL_PWREx_EnableFlashPowerDown(uint32_t PowerMode)
00675 {
00676   assert_param(IS_PWR_FLASH_POWERDOWN(PowerMode));
00677
00678   if((PowerMode & PWR_FLASHPD_LPRUN) != 0U)
00679   {
00680     /* Unlock bit FPDR */
00681     WRITE_REG(PWR->CR1, 0x0000C1B0U);
00682   }
00683
00684   /* Set flash power down mode */
00685   SET_BIT(PWR->CR1, PowerMode);
00686 }
00687
00688 /**
00689   * @brief  Disable Flash Power Down.
00690   * @note   This API allows to disable flash power down capabilities in low power
00691   *         run and low power sleep modes.
00692   * @param  PowerMode this can be a combination of following values:
00693   *           @arg @ref PWR_FLASHPD_LPRUN
00694   *           @arg @ref PWR_FLASHPD_LPSLEEP
00695   * @retval None
00696   */
00697 void HAL_PWREx_DisableFlashPowerDown(uint32_t PowerMode)
00698 {
00699   assert_param(IS_PWR_FLASH_POWERDOWN(PowerMode));
00700
00701   /* Set flash power down mode */
00702   CLEAR_BIT(PWR->CR1, PowerMode);
00703 }
00704
00705 /****************************************************************************/
00706 #if defined(PWR_CR2_PVME1)
00707 /**
00708   * @brief Enable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
00709   * @retval None
00710   */
00711 void HAL_PWREx_EnablePVM1(void)
00712 {
00713   SET_BIT(PWR->CR2, PWR_PVM_1);
00714 }
00715
00716 /**
00717   * @brief Disable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
00718   * @retval None
00719   */
00720 void HAL_PWREx_DisablePVM1(void)
00721 {
00722   CLEAR_BIT(PWR->CR2, PWR_PVM_1);
00723 }
00724 #endif
00725
00726 /**
00727   * @brief Enable the Power Voltage Monitoring 3: VDDA versus 1.62V.
00728   * @retval None
00729   */
00730 void HAL_PWREx_EnablePVM3(void)
00731 {
00732   SET_BIT(PWR->CR2, PWR_PVM_3);
00733 }
00734
00735 /**
00736   * @brief Disable the Power Voltage Monitoring 3: VDDA versus 1.62V.
00737   * @retval None
00738   */
00739 void HAL_PWREx_DisablePVM3(void)
00740 {
00741   CLEAR_BIT(PWR->CR2, PWR_PVM_3);
00742 }
00743
00744
00745
00746
00747 /**
00748   * @brief Configure the Peripheral Voltage Monitoring (PVM).
00749   * @param sConfigPVM pointer to a PWR_PVMTypeDef structure that contains the
00750   *        PVM configuration information.
00751   * @note The API configures a single PVM according to the information contained
00752   *       in the input structure. To configure several PVMs, the API must be singly
00753   *       called for each PVM used.
00754   * @note Refer to the electrical characteristics of your device datasheet for
00755   *         more details about the voltage thresholds corresponding to each
00756   *         detection level and to each monitored supply.
00757   * @retval HAL status
00758   */
00759 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)
00760 {
00761   HAL_StatusTypeDef status = HAL_OK;
00762
00763   /* Check the parameters */
00764   assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType));
00765   assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode));
00766
00767   /* Configure EXTI 31 and 33 interrupts if so required:
00768      scan thru PVMType to detect which PVMx is set and
00769      configure the corresponding EXTI line accordingly. */
00770   switch (sConfigPVM->PVMType)
00771   {
00772 #if defined(PWR_CR2_PVME1)
00773    case PWR_PVM_1:
00774       /* Clear any previous config. Keep it clear if no event or IT mode is selected */
00775       __HAL_PWR_PVM1_EXTI_DISABLE_EVENT();
00776       __HAL_PWR_PVM1_EXTI_DISABLE_IT();
00777       __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE();
00778       __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE();
00779
00780       /* Configure interrupt mode */
00781       if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
00782       {
00783         __HAL_PWR_PVM1_EXTI_ENABLE_IT();
00784       }
00785
00786       /* Configure event mode */
00787       if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
00788       {
00789         __HAL_PWR_PVM1_EXTI_ENABLE_EVENT();
00790       }
00791
00792       /* Configure the edge */
00793       if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
00794       {
00795         __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE();
00796       }
00797
00798       if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
00799       {
00800         __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();
00801       }
00802       break;
00803 #endif
00804
00805     case PWR_PVM_3:
00806       /* Clear any previous config. Keep it clear if no event or IT mode is selected */
00807       __HAL_PWR_PVM3_EXTI_DISABLE_EVENT();
00808       __HAL_PWR_PVM3_EXTI_DISABLE_IT();
00809       __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE();
00810       __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();
00811
00812       /* Configure interrupt mode */
00813       if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
00814       {
00815         __HAL_PWR_PVM3_EXTI_ENABLE_IT();
00816       }
00817
00818       /* Configure event mode */
00819       if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
00820       {
00821         __HAL_PWR_PVM3_EXTI_ENABLE_EVENT();
00822       }
00823
00824       /* Configure the edge */
00825       if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
00826       {
00827         __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();
00828       }
00829
00830       if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
00831       {
00832         __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();
00833       }
00834       break;
00835
00836     default:
00837       status = HAL_ERROR;
00838       break;
00839
00840   }
00841
00842   return status;
00843 }
00844
00845 #if defined(PWR_CR5_SMPSEN)
00846 /**
00847   * @brief Configure the SMPS step down converter.
00848   * @note   SMPS output voltage is calibrated in production,
00849   *         calibration parameters are applied to the voltage level parameter
00850   *         to reach the requested voltage value.
00851   * @param sConfigSMPS pointer to a PWR_SMPSTypeDef structure that contains the
00852   *        SMPS configuration information.
00853   * @note  To set and enable SMPS operating mode, refer to function
00854   *        "HAL_PWREx_SMPS_SetMode()".
00855   * @retval HAL status
00856   */
00857 HAL_StatusTypeDef HAL_PWREx_ConfigSMPS(PWR_SMPSTypeDef *sConfigSMPS)
00858 {
00859   HAL_StatusTypeDef status = HAL_OK;
00860
00861   /* Check the parameters */
00862   assert_param(IS_PWR_SMPS_STARTUP_CURRENT(sConfigSMPS->StartupCurrent));
00863   assert_param(IS_PWR_SMPS_OUTPUT_VOLTAGE(sConfigSMPS->OutputVoltage));
00864
00865   __IO const uint32_t OutputVoltageLevel_calibration = (((*SMPS_VOLTAGE_CAL_ADDR) & SMPS_VOLTAGE_CAL) >> SMPS_VOLTAGE_CAL_POS);  /* SMPS output voltage level calibrated in production */
00866   int32_t TrimmingSteps;                         /* Trimming steps between theorical output voltage and calibrated output voltage */
00867   int32_t OutputVoltageLevelTrimmed;             /* SMPS output voltage level after calibration: trimming value added to required level */
00868
00869   if(OutputVoltageLevel_calibration == 0UL)
00870   {
00871     /* Device with SMPS output voltage not calibrated in production: Apply output voltage value directly */
00872
00873     /* Update register */
00874     MODIFY_REG(PWR->CR5, PWR_CR5_SMPSVOS, (sConfigSMPS->StartupCurrent | sConfigSMPS->OutputVoltage));
00875   }
00876   else
00877   {
00878     /* Device with SMPS output voltage calibrated in production: Apply output voltage value after correction by calibration value */
00879
00880     TrimmingSteps = ((int32_t)OutputVoltageLevel_calibration - (int32_t)(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V50 >> PWR_CR5_SMPSVOS_Pos));
00881     OutputVoltageLevelTrimmed = ((int32_t)((uint32_t)(sConfigSMPS->OutputVoltage >> PWR_CR5_SMPSVOS_Pos)) + (int32_t)TrimmingSteps);
00882
00883     /* Clamp value to voltage trimming bitfield range */
00884     if(OutputVoltageLevelTrimmed < 0)
00885     {
00886       OutputVoltageLevelTrimmed = 0;
00887       status = HAL_ERROR;
00888     }
00889     else
00890     {
00891       if(OutputVoltageLevelTrimmed > (int32_t)PWR_CR5_SMPSVOS)
00892       {
00893         OutputVoltageLevelTrimmed = (int32_t)PWR_CR5_SMPSVOS;
00894         status = HAL_ERROR;
00895       }
00896     }
00897
00898     /* Update register */
00899     MODIFY_REG(PWR->CR5, (PWR_CR5_SMPSSC | PWR_CR5_SMPSVOS), (sConfigSMPS->StartupCurrent | ((uint32_t) OutputVoltageLevelTrimmed)));
00900   }
00901
00902   return status;
00903 }
00904
00905 /**
00906   * @brief Set SMPS operating mode.
00907   * @param  OperatingMode This parameter can be one of the following values:
00908   *         @arg @ref PWR_SMPS_BYPASS
00909   *         @arg @ref PWR_SMPS_STEP_DOWN (1)
00910   *
00911   *         (1) SMPS operating mode step down or open depends on system low-power mode:
00912   *              - step down mode if system low power mode is run, LP run or stop,
00913   *              - open mode if system low power mode is stop1, stop2, standby or shutdown
00914   * @retval None
00915   */
00916 void HAL_PWREx_SMPS_SetMode(uint32_t OperatingMode)
00917 {
00918   MODIFY_REG(PWR->CR5, PWR_CR5_SMPSEN, (OperatingMode & PWR_SR2_SMPSF) << (PWR_CR5_SMPSEN_Pos - PWR_SR2_SMPSF_Pos));
00919 }
00920
00921 /**
00922   * @brief  Get SMPS effective operating mode
00923   * @note   SMPS operating mode can be changed by hardware, therefore
00924   *         requested operating mode can differ from effective low power mode.
00925   *         - dependency on system low-power mode:
00926   *           - step down mode if system low power mode is run, LP run or stop,
00927   *           - open mode if system low power mode is stop1, stop2, standby or shutdown
00928   *         - dependency on BOR level:
00929   *           - bypass mode if supply voltage drops below BOR level
00930   * @note   This functions check flags of SMPS operating modes step down
00931   *         and bypass. If the SMPS is not among these 2 operating modes,
00932   *         then it can be in mode off or open.
00933   * @retval Returned value can be one of the following values:
00934   *         @arg @ref PWR_SMPS_BYPASS
00935   *         @arg @ref PWR_SMPS_STEP_DOWN (1)
00936   *
00937   *         (1) SMPS operating mode step down or open depends on system low-power mode:
00938   *              - step down mode if system low power mode is run, LP run or stop,
00939   *              - open mode if system low power mode is stop1, stop2, standby or shutdown
00940   */
00941 uint32_t HAL_PWREx_SMPS_GetEffectiveMode(void)
00942 {
00943   return (uint32_t)(READ_BIT(PWR->SR2, (PWR_SR2_SMPSF | PWR_SR2_SMPSBF)));
00944 }
00945 #endif
00946
00947 /****************************************************************************/
00948
00949 /**
00950   * @brief Enable the WakeUp PINx functionality.
00951   * @param WakeUpPinPolarity Specifies which Wake-Up pin to enable.
00952   *         This parameter can be one of the following legacy values which set the default polarity
00953   *         i.e. detection on high level (rising edge):
00954   *           @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
00955   *
00956   *         or one of the following value where the user can explicitly specify the enabled pin and
00957   *         the chosen polarity:
00958   *           @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
00959   *           @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
00960   *           @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
00961   *           @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
00962   *           @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
00963   * @param wakeupTarget Specifies the wake-up target
00964   *         @arg @ref PWR_CORE_CPU1
00965   *         @arg @ref PWR_CORE_CPU2
00966   * @note  PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
00967   * @retval None
00968   */
00969 void HAL_PWREx_EnableWakeUpPin(uint32_t WakeUpPinPolarity, uint32_t wakeupTarget)
00970 {
00971   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
00972
00973   /* Specifies the Wake-Up pin polarity for the event detection
00974     (rising or falling edge) */
00975   MODIFY_REG(PWR->CR4, (PWR_C2CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT));
00976
00977   /* Enable wake-up pin */
00978   if(PWR_CORE_CPU2 == wakeupTarget)
00979   {
00980     SET_BIT(PWR->C2CR3, (PWR_C2CR3_EWUP & WakeUpPinPolarity));
00981   }
00982   else
00983   {
00984     SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity));
00985   }
00986 }
00987
00988 /**
00989   * @brief  Get the Wake-Up pin flag.
00990   * @param WakeUpFlag specifies the Wake-Up PIN flag to check.
00991   *          This parameter can be one of the following values:
00992   *            @arg PWR_FLAG_WUF1: A wakeup event was received from PA0.
00993   *            @arg PWR_FLAG_WUF2: A wakeup event was received from PC13.
00994   *            @arg PWR_FLAG_WUF3: A wakeup event was received from PC12.
00995   *            @arg PWR_FLAG_WUF4: A wakeup event was received from PA2.
00996   *            @arg PWR_FLAG_WUF5: A wakeup event was received from PC5.
00997   * @retval The Wake-Up pin flag.
00998   */
00999 uint32_t  HAL_PWREx_GetWakeupFlag(uint32_t WakeUpFlag)
01000 {
01001   return (PWR->SR1 & (1UL << ((WakeUpFlag) & 31U)));
01002 }
01003
01004 /**
01005   * @brief  Clear the Wake-Up pin flag.
01006   * @param WakeUpFlag specifies the Wake-Up PIN flag to clear.
01007   *          This parameter can be one of the following values:
01008   *            @arg PWR_FLAG_WUF1: A wakeup event was received from PA0.
01009   *            @arg PWR_FLAG_WUF2: A wakeup event was received from PC13.
01010   *            @arg PWR_FLAG_WUF3: A wakeup event was received from PC12.
01011   *            @arg PWR_FLAG_WUF4: A wakeup event was received from PA2.
01012   *            @arg PWR_FLAG_WUF5: A wakeup event was received from PC5.
01013   * @retval HAL status.
01014   */
01015 HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag(uint32_t WakeUpFlag)
01016 {
01017   PWR->SCR = (1UL << ((WakeUpFlag) & 31U));
01018
01019   if((PWR->SR1 & (1UL << ((WakeUpFlag) & 31U))) != 0U)
01020   {
01021     return HAL_ERROR;
01022   }
01023   return HAL_OK;
01024 }
01025
01026 /****************************************************************************/
01027
01028 /**
01029   * @brief Enter Low-power Run mode
01030   * @note  In Low-power Run mode, all I/O pins keep the same state as in Run mode.
01031   * @note  When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
01032   *        Flash in power-down mode in setting the RUN_PD bit in FLASH_ACR register.
01033   *        Additionally, the clock frequency must be reduced below 2 MHz.
01034   *        Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must
01035   *        be done before calling HAL_PWREx_EnableLowPowerRunMode() API.
01036   * @retval None
01037   */
01038 void HAL_PWREx_EnableLowPowerRunMode(void)
01039 {
01040   /* Set Regulator parameter */
01041   SET_BIT(PWR->CR1, PWR_CR1_LPR);
01042 }
01043
01044
01045 /**
01046   * @brief Exit Low-power Run mode.
01047   * @note  Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that
01048   *        REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode
01049   *        returns HAL_TIMEOUT status). The system clock frequency can then be
01050   *        increased above 2 MHz.
01051   * @retval HAL Status
01052   */
01053 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void)
01054 {
01055   uint32_t wait_loop_index;
01056
01057   /* Clear LPR bit */
01058   CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
01059
01060   /* Wait until REGLPF is reset */
01061   wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000U));
01062   while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) && (wait_loop_index != 0U))
01063   {
01064     wait_loop_index--;
01065   }
01066   if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
01067   {
01068     return HAL_TIMEOUT;
01069   }
01070
01071   return HAL_OK;
01072 }
01073
01074 /****************************************************************************/
01075
01076 /**
01077   * @brief Enter Stop 0 mode.
01078   * @note  In Stop 0 mode, main and low voltage regulators are ON.
01079   * @note  In Stop 0 mode, all I/O pins keep the same state as in Run mode.
01080   * @note  All clocks in the VCORE domain are stopped; the PLL, the MSI,
01081   *        the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
01082   *        (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
01083   *        after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
01084   *        only to the peripheral requesting it.
01085   *        SRAM1, SRAM2 and register contents are preserved.
01086   *        The BOR is available.
01087   * @note  When exiting Stop 0 mode by issuing an interrupt or a wakeup event,
01088   *         the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
01089   *         is set; the MSI oscillator is selected if STOPWUCK is cleared.
01090   * @note  By keeping the internal regulator ON during Stop 0 mode, the consumption
01091   *         is higher although the startup time is reduced.
01092   * @note  Case of Stop0 mode with SMPS: Before entering Stop 0 mode with SMPS Step Down converter enabled,
01093   *        the HSI16 must be kept on by enabling HSI kernel clock (set HSIKERON register bit).
01094   * @note  According to system power policy, system entering in Stop mode
01095   *        is depending on other CPU power mode.
01096   * @param STOPEntry  specifies if Stop mode in entered with WFI or WFE instruction.
01097   *          This parameter can be one of the following values:
01098   *            @arg @ref PWR_STOPENTRY_WFI  Enter Stop mode with WFI instruction
01099   *            @arg @ref PWR_STOPENTRY_WFE  Enter Stop mode with WFE instruction
01100   * @retval None
01101   */
01102 void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry)
01103 {
01104   /* Check the parameters */
01105   assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
01106
01107   /* Stop 0 mode with Main Regulator */
01108   MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STOP0);
01109
01110
01111   /* Set SLEEPDEEP bit of Cortex System Control Register */
01112   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
01113
01114   /* Select Stop mode entry --------------------------------------------------*/
01115   if(STOPEntry == PWR_STOPENTRY_WFI)
01116   {
01117     /* Request Wait For Interrupt */
01118     __WFI();
01119   }
01120   else
01121   {
01122     /* Request Wait For Event */
01123     __SEV();
01124     __WFE();
01125     __WFE();
01126   }
01127
01128   /* Reset SLEEPDEEP bit of Cortex System Control Register */
01129   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
01130 }
01131
01132
01133 /**
01134   * @brief Enter Stop 1 mode.
01135   * @note  In Stop 1 mode, only low power voltage regulator is ON.
01136   * @note  In Stop 1 mode, all I/O pins keep the same state as in Run mode.
01137   * @note  All clocks in the VCORE domain are stopped; the PLL, the MSI,
01138   *        the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
01139   *        (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
01140   *        after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
01141   *        only to the peripheral requesting it.
01142   *        SRAM1, SRAM2 and register contents are preserved.
01143   *        The BOR is available.
01144   * @note  When exiting Stop 1 mode by issuing an interrupt or a wakeup event,
01145   *         the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
01146   *         is set; the MSI oscillator is selected if STOPWUCK is cleared.
01147   * @note  Due to low power mode, an additional startup delay is incurred when waking up from Stop 1 mode.
01148   * @note  According to system power policy, system entering in Stop mode
01149   *        is depending on other CPU power mode.
01150   * @param STOPEntry  specifies if Stop mode in entered with WFI or WFE instruction.
01151   *          This parameter can be one of the following values:
01152   *            @arg @ref PWR_STOPENTRY_WFI  Enter Stop mode with WFI instruction
01153   *            @arg @ref PWR_STOPENTRY_WFE  Enter Stop mode with WFE instruction
01154   * @retval None
01155   */
01156 void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)
01157 {
01158   /* Check the parameters */
01159   assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
01160
01161   /* Stop 1 mode with Low-Power Regulator */
01162   MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STOP1);
01163
01164   /* Set SLEEPDEEP bit of Cortex System Control Register */
01165   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
01166
01167   /* Select Stop mode entry --------------------------------------------------*/
01168   if(STOPEntry == PWR_STOPENTRY_WFI)
01169   {
01170     /* Request Wait For Interrupt */
01171     __WFI();
01172   }
01173   else
01174   {
01175     /* Request Wait For Event */
01176     __SEV();
01177     __WFE();
01178     __WFE();
01179   }
01180
01181   /* Reset SLEEPDEEP bit of Cortex System Control Register */
01182   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
01183 }
01184
01185
01186 /**
01187   * @brief Enter Stop 2 mode.
01188   * @note  In Stop 2 mode, only low power voltage regulator is ON.
01189   * @note  In Stop 2 mode, all I/O pins keep the same state as in Run mode.
01190   * @note  All clocks in the VCORE domain are stopped, the PLL, the MSI,
01191   *        the HSI and the HSE oscillators are disabled. Some peripherals with wakeup capability
01192   *        (LCD, LPTIM1, I2C3 and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after
01193   *        receiving the frame if it is not a wakeup frame. In this case the HSI clock is propagated only
01194   *        to the peripheral requesting it.
01195   *        SRAM1, SRAM2 and register contents are preserved.
01196   *        The BOR is available.
01197   *        The voltage regulator is set in low-power mode but LPR bit must be cleared to enter stop 2 mode.
01198   *        Otherwise, Stop 1 mode is entered.
01199   * @note  When exiting Stop 2 mode by issuing an interrupt or a wakeup event,
01200   *         the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
01201   *         is set; the MSI oscillator is selected if STOPWUCK is cleared.
01202   * @note  Case of Stop2 mode and debugger probe attached: a workaround should be applied.
01203   *        Issue specified in "ES0394 - STM32WB55Cx/Rx/Vx device errata":
01204   *        2.2.9 Incomplete Stop 2 mode entry after a wakeup from debug upon EXTI line 48 event
01205   *        "With the JTAG debugger enabled on GPIO pins and after a wakeup from debug triggered by an event on EXTI
01206   *        line 48 (CDBGPWRUPREQ), the device may enter in a state in which attempts to enter Stop 2 mode are not fully
01207   *        effective ..."
01208   *        Workaround implementation example using LL driver:
01209   *        LL_EXTI_DisableIT_32_63(LL_EXTI_LINE_48);
01210   *        LL_C2_EXTI_DisableIT_32_63(LL_EXTI_LINE_48);
01211   * @note  According to system power policy, system entering in Stop mode
01212   *        is depending on other CPU power mode.
01213   * @param STOPEntry  specifies if Stop mode in entered with WFI or WFE instruction.
01214   *          This parameter can be one of the following values:
01215   *            @arg @ref PWR_STOPENTRY_WFI  Enter Stop mode with WFI instruction
01216   *            @arg @ref PWR_STOPENTRY_WFE  Enter Stop mode with WFE instruction
01217   * @retval None
01218   */
01219 void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry)
01220 {
01221   /* Check the parameter */
01222   assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
01223
01224   /* Set Stop mode 2 */
01225   MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STOP2);
01226
01227   /* Set SLEEPDEEP bit of Cortex System Control Register */
01228   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
01229
01230   /* Select Stop mode entry --------------------------------------------------*/
01231   if(STOPEntry == PWR_STOPENTRY_WFI)
01232   {
01233     /* Request Wait For Interrupt */
01234     __WFI();
01235   }
01236   else
01237   {
01238     /* Request Wait For Event */
01239     __SEV();
01240     __WFE();
01241     __WFE();
01242   }
01243
01244   /* Reset SLEEPDEEP bit of Cortex System Control Register */
01245   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
01246 }
01247
01248
01249
01250
01251
01252 /**
01253   * @brief Enter Shutdown mode.
01254   * @note  In Shutdown mode, the PLL, the HSI, the MSI, the LSI and the HSE oscillators are switched
01255   *        off. The voltage regulator is disabled and Vcore domain is powered off.
01256   *        SRAM1, SRAM2, BKRAM and registers contents are lost except for registers in the Backup domain.
01257   *        The BOR is not available.
01258   * @note  The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
01259   * @note  According to system power policy, system entering in Shutdown mode
01260   *        is depending on other CPU power mode.
01261   * @retval None
01262   */
01263 void HAL_PWREx_EnterSHUTDOWNMode(void)
01264 {
01265   /* Set Shutdown mode */
01266   MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_SHUTDOWN);
01267
01268   /* Set SLEEPDEEP bit of Cortex System Control Register */
01269   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
01270
01271 /* This option is used to ensure that store operations are completed */
01272 #if defined ( __CC_ARM)
01273   __force_stores();
01274 #endif
01275
01276   /* Request Wait For Interrupt */
01277   __WFI();
01278
01279   /* Following code is executed after wake up if system didn't go to SHUTDOWN
01280    * or STANDBY mode according to power policy */
01281
01282   /* Reset SLEEPDEEP bit of Cortex System Control Register */
01283   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
01284 }
01285
01286
01287 /**
01288   * @brief This function handles the PWR PVD/PVMx interrupt request.
01289   * @note This API should be called under the PVD_PVM_IRQHandler().
01290   * @retval None
01291   */
01292 void HAL_PWREx_PVD_PVM_IRQHandler(void)
01293 {
01294   /* Check PWR exti flag */
01295   if(__HAL_PWR_PVD_EXTI_GET_FLAG() != 0U)
01296   {
01297     /* PWR PVD interrupt user callback */
01298     HAL_PWR_PVDCallback();
01299
01300     /* Clear PVD exti pending bit */
01301     __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
01302   }
01303
01304 #if defined(PWR_CR2_PVME1)
01305   /* Next, successively check PVMx exti flags */
01306   if(__HAL_PWR_PVM1_EXTI_GET_FLAG() != 0U)
01307   {
01308     /* PWR PVM1 interrupt user callback */
01309     HAL_PWREx_PVM1Callback();
01310
01311     /* Clear PVM1 exti pending bit */
01312     __HAL_PWR_PVM1_EXTI_CLEAR_FLAG();
01313   }
01314 #endif
01315
01316   if(__HAL_PWR_PVM3_EXTI_GET_FLAG() != 0U)
01317   {
01318     /* PWR PVM3 interrupt user callback */
01319     HAL_PWREx_PVM3Callback();
01320
01321     /* Clear PVM3 exti pending bit */
01322     __HAL_PWR_PVM3_EXTI_CLEAR_FLAG();
01323   }
01324 }
01325
01326 #if defined(PWR_CR2_PVME1)
01327 /**
01328   * @brief PWR PVM1 interrupt callback
01329   * @retval None
01330   */
01331 __weak void HAL_PWREx_PVM1Callback(void)
01332 {
01333   /* NOTE : This function should not be modified; when the callback is needed,
01334             HAL_PWREx_PVM1Callback() API can be implemented in the user file
01335    */
01336 }
01337 #endif
01338
01339 /**
01340   * @brief PWR PVM3 interrupt callback
01341   * @retval None
01342   */
01343 __weak void HAL_PWREx_PVM3Callback(void)
01344 {
01345   /* NOTE : This function should not be modified; when the callback is needed,
01346             HAL_PWREx_PVM3Callback() API can be implemented in the user file
01347    */
01348 }
01349
01350
01351 /**
01352   * @}
01353   */
01354
01355 /**
01356   * @}
01357   */
01358
01359 #endif /* HAL_PWR_MODULE_ENABLED */
01360 /**
01361   * @}
01362   */
01363
01364 /**
01365   * @}
01366   */
01367
01368 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:35 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_pwr_ex.h Source File

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stm32wbxx_hal_pwr_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_pwr_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of PWR HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_PWR_EX_H
00022 #define STM32WBxx_HAL_PWR_EX_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 /** @addtogroup STM32WBxx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @defgroup PWREx PWREx
00036   * @brief PWR Extended HAL module driver
00037   * @{
00038   */
00039
00040
00041 /* Exported types ------------------------------------------------------------*/
00042
00043 /** @defgroup PWREx_Exported_Types PWR Extended Exported Types
00044   * @{
00045   */
00046
00047 /**
00048   * @brief  PWR PVM configuration structure definition
00049   */
00050 typedef struct
00051 {
00052   uint32_t PVMType;   /*!< PVMType: Specifies which voltage is monitored and against which threshold.
00053                            This parameter can be a value of @ref PWREx_PVM_Type.
00054                            @arg @ref PWR_PVM_1 Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported).
00055                            @arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V.
00056                            */
00057
00058   uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.
00059                            This parameter can be a value of @ref PWREx_PVM_Mode. */
00060   uint32_t WakeupTarget;   /*!< Specifies the Wakeup Target
00061                            This parameter can be a value of @ref PWREx_WakeUpTarget_Definition */
00062 }PWR_PVMTypeDef;
00063
00064 #if defined(PWR_CR5_SMPSEN)
00065 /**
00066   * @brief  PWR SMPS step down configuration structure definition
00067   */
00068 typedef struct
00069 {
00070   uint32_t StartupCurrent; /*!< SMPS step down converter supply startup current selection.
00071                                 This parameter can be a value of @ref PWREx_SMPS_STARTUP_CURRENT. */
00072
00073   uint32_t OutputVoltage;  /*!< SMPS step down converter output voltage scaling voltage level.
00074                                 This parameter can be a value of @ref PWREx_SMPS_OUTPUT_VOLTAGE_LEVEL */
00075 }PWR_SMPSTypeDef;
00076 #endif
00077
00078 /**
00079   * @}
00080   */
00081
00082 /* Exported constants --------------------------------------------------------*/
00083
00084 /** @defgroup PWREx_Exported_Constants  PWR Extended Exported Constants
00085   * @{
00086   */
00087
00088 /** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants
00089   * @{
00090   */
00091 #define PWR_WUP_POLARITY_SHIFT                  0x05U   /*!< Internal constant used to retrieve wakeup pin polarity */
00092 /**
00093   * @}
00094   */
00095
00096
00097 /** @defgroup PWREx_WakeUp_Pins  PWR wake-up pins
00098   * @{
00099   */
00100 #define PWR_WAKEUP_PIN1_HIGH            PWR_CR3_EWUP1  /*!< Wakeup pin 1 (with high level polarity) */
00101 #if defined(PWR_CR3_EWUP2)
00102 #define PWR_WAKEUP_PIN2_HIGH            PWR_CR3_EWUP2  /*!< Wakeup pin 2 (with high level polarity) */
00103 #endif
00104 #if defined(PWR_CR3_EWUP3)
00105 #define PWR_WAKEUP_PIN3_HIGH            PWR_CR3_EWUP3  /*!< Wakeup pin 3 (with high level polarity) */
00106 #endif
00107 #define PWR_WAKEUP_PIN4_HIGH            PWR_CR3_EWUP4  /*!< Wakeup pin 4 (with high level polarity) */
00108 #if defined(PWR_CR3_EWUP5)
00109 #define PWR_WAKEUP_PIN5_HIGH            PWR_CR3_EWUP5  /*!< Wakeup pin 5 (with high level polarity) */
00110 #endif
00111
00112 #define PWR_WAKEUP_PIN1_LOW             ((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */
00113 #if defined(PWR_CR3_EWUP2)
00114 #define PWR_WAKEUP_PIN2_LOW             ((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */
00115 #endif
00116 #if defined(PWR_CR3_EWUP3)
00117 #define PWR_WAKEUP_PIN3_LOW             ((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */
00118 #endif
00119 #define PWR_WAKEUP_PIN4_LOW             ((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level polarity) */
00120 #if defined(PWR_CR3_EWUP5)
00121 #define PWR_WAKEUP_PIN5_LOW             ((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level polarity) */
00122 #endif
00123 /**
00124   * @}
00125   */
00126
00127 /* Literals kept for legacy purpose */
00128 #define PWR_WAKEUP_PIN1                 PWR_CR3_EWUP1  /*!< Wakeup pin 1 (with high level polarity) */
00129 #if defined(PWR_CR3_EWUP2)
00130 #define PWR_WAKEUP_PIN2                 PWR_CR3_EWUP2  /*!< Wakeup pin 2 (with high level polarity) */
00131 #endif
00132 #if defined(PWR_CR3_EWUP3)
00133 #define PWR_WAKEUP_PIN3                 PWR_CR3_EWUP3  /*!< Wakeup pin 3 (with high level polarity) */
00134 #endif
00135 #define PWR_WAKEUP_PIN4                 PWR_CR3_EWUP4  /*!< Wakeup pin 4 (with high level polarity) */
00136 #if defined(PWR_CR3_EWUP5)
00137 #define PWR_WAKEUP_PIN5                 PWR_CR3_EWUP5  /*!< Wakeup pin 5 (with high level polarity) */
00138 #endif
00139
00140 /** @defgroup PWREx_PIN_Polarity PWREx Pin Polarity configuration
00141   * @{
00142   */
00143 #define PWR_PIN_POLARITY_HIGH 0x00000000U
00144 #define PWR_PIN_POLARITY_LOW  0x00000001U
00145 /**
00146   * @}
00147   */
00148
00149 /** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type
00150   * @{
00151   */
00152 #if defined(PWR_CR2_PVME1)
00153 #define PWR_PVM_1                  PWR_CR2_PVME1  /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) */
00154 #endif
00155 #define PWR_PVM_3                  PWR_CR2_PVME3  /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */
00156 /**
00157   * @}
00158   */
00159
00160 /** @defgroup PWREx_PVM_Mode  PWR PVM interrupt and event mode
00161   * @{
00162   */
00163 #define PWR_PVM_MODE_NORMAL                 (0x00000000U) /*!< basic mode is used */
00164
00165 #define PWR_PVM_MODE_IT_RISING              (PVM_MODE_IT | PVM_RISING_EDGE)             /*!< External Interrupt Mode with Rising edge trigger detection */
00166 #define PWR_PVM_MODE_IT_FALLING             (PVM_MODE_IT | PVM_FALLING_EDGE)            /*!< External Interrupt Mode with Falling edge trigger detection */
00167 #define PWR_PVM_MODE_IT_RISING_FALLING      (PVM_MODE_IT | PVM_RISING_FALLING_EDGE)     /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
00168
00169 #define PWR_PVM_MODE_EVENT_RISING           (PVM_MODE_EVT | PVM_RISING_EDGE)          /*!< Event Mode with Rising edge trigger detection */
00170 #define PWR_PVM_MODE_EVENT_FALLING          (PVM_MODE_EVT | PVM_FALLING_EDGE)         /*!< Event Mode with Falling edge trigger detection */
00171 #define PWR_PVM_MODE_EVENT_RISING_FALLING   (PVM_MODE_EVT | PVM_RISING_FALLING_EDGE)  /*!< Event Mode with Rising/Falling edge trigger detection */
00172 /**
00173   * @}
00174   */
00175
00176 /** @defgroup PWREx_Flash_PowerDown  Flash Power Down modes
00177   * @{
00178   */
00179 #define PWR_FLASHPD_LPRUN                   PWR_CR1_FPDR     /*!< Enable Flash power down in low power run mode */
00180 #define PWR_FLASHPD_LPSLEEP                 PWR_CR1_FPDS     /*!< Enable Flash power down in low power sleep mode */
00181 /**
00182   * @}
00183   */
00184
00185 /** @defgroup PWREx_Regulator_Voltage_Scale  PWR Regulator voltage scale
00186   * @{
00187   */
00188 #if defined(PWR_CR1_VOS)
00189 #define PWR_REGULATOR_VOLTAGE_SCALE1       PWR_CR1_VOS_0     /*!< Regulator voltage output range 1 mode, typical output voltage at 1.2 V, system frequency up to 64 MHz */
00190 #define PWR_REGULATOR_VOLTAGE_SCALE2       PWR_CR1_VOS_1     /*!< Regulator voltage output range 2 mode, typical output voltage at 1.0 V, system frequency up to 16 MHz */
00191 #else
00192 #define PWR_REGULATOR_VOLTAGE_SCALE1       (0x00000200UL)    /*!< Regulator voltage output range 1 mode, typical output voltage at 1.2 V, system frequency up to 64 MHz */
00193 #endif
00194 /**
00195   * @}
00196   */
00197
00198
00199 /** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection
00200   * @{
00201   */
00202 #define PWR_BATTERY_CHARGING_RESISTOR_5          (0x00000000U) /*!< VBAT charging through a 5 kOhms resistor   */
00203 #define PWR_BATTERY_CHARGING_RESISTOR_1_5        PWR_CR4_VBRS           /*!< VBAT charging through a 1.5 kOhms resistor */
00204 /**
00205   * @}
00206   */
00207
00208 /** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging
00209   * @{
00210   */
00211 #define PWR_BATTERY_CHARGING_DISABLE        (0x00000000U)
00212 #define PWR_BATTERY_CHARGING_ENABLE         PWR_CR4_VBE
00213 /**
00214   * @}
00215   */
00216
00217 /** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode
00218   * @{
00219   */
00220 #define PWR_GPIO_BIT_0   PWR_PUCRA_PA0    /*!< GPIO port I/O pin 0  */
00221 #define PWR_GPIO_BIT_1   PWR_PUCRA_PA1    /*!< GPIO port I/O pin 1  */
00222 #define PWR_GPIO_BIT_2   PWR_PUCRA_PA2    /*!< GPIO port I/O pin 2  */
00223 #define PWR_GPIO_BIT_3   PWR_PUCRA_PA3    /*!< GPIO port I/O pin 3  */
00224 #define PWR_GPIO_BIT_4   PWR_PUCRA_PA4    /*!< GPIO port I/O pin 4  */
00225 #define PWR_GPIO_BIT_5   PWR_PUCRA_PA5    /*!< GPIO port I/O pin 5  */
00226 #define PWR_GPIO_BIT_6   PWR_PUCRA_PA6    /*!< GPIO port I/O pin 6  */
00227 #define PWR_GPIO_BIT_7   PWR_PUCRA_PA7    /*!< GPIO port I/O pin 7  */
00228 #define PWR_GPIO_BIT_8   PWR_PUCRA_PA8    /*!< GPIO port I/O pin 8  */
00229 #define PWR_GPIO_BIT_9   PWR_PUCRA_PA9    /*!< GPIO port I/O pin 9  */
00230 #define PWR_GPIO_BIT_10  PWR_PUCRA_PA10   /*!< GPIO port I/O pin 10 */
00231 #define PWR_GPIO_BIT_11  PWR_PUCRA_PA11   /*!< GPIO port I/O pin 11 */
00232 #define PWR_GPIO_BIT_12  PWR_PUCRA_PA12   /*!< GPIO port I/O pin 12 */
00233 #define PWR_GPIO_BIT_13  PWR_PUCRA_PA13   /*!< GPIO port I/O pin 14 */
00234 #define PWR_GPIO_BIT_14  PWR_PDCRC_PC14   /*!< GPIO port I/O pin 14 */
00235 #define PWR_GPIO_BIT_15  PWR_PUCRC_PC15   /*!< GPIO port I/O pin 15 */
00236 /**
00237   * @}
00238   */
00239
00240 /** @defgroup PWREx_GPIO GPIO port
00241   * @{
00242   */
00243 #define PWR_GPIO_A   0x00000000U      /*!< GPIO port A */
00244 #define PWR_GPIO_B   0x00000001U      /*!< GPIO port B */
00245 #define PWR_GPIO_C   0x00000002U      /*!< GPIO port C */
00246 #if defined(GPIOD)
00247 #define PWR_GPIO_D   0x00000003U      /*!< GPIO port D */
00248 #endif
00249 #define PWR_GPIO_E   0x00000004U      /*!< GPIO port E */
00250 #define PWR_GPIO_H   0x00000007U      /*!< GPIO port H */
00251 /**
00252   * @}
00253   */
00254
00255 #if defined(PWR_CR5_SMPSEN)
00256 /** @defgroup PWREx_BOR_CONFIGURATION BOR configuration
00257   * @{
00258   */
00259 #define PWR_BOR_SYSTEM_RESET            (LL_PWR_BOR_SYSTEM_RESET)      /*!< BOR will generate a system reset  */
00260 #define PWR_BOR_SMPS_FORCE_BYPASS       (LL_PWR_BOR_SMPS_FORCE_BYPASS) /*!< BOR will for SMPS step down converter in bypass mode */
00261 /**
00262   * @}
00263   */
00264
00265 /** @defgroup PWREx_SMPS_OPERATING_MODES SMPS step down converter operating modes
00266   * @{
00267   */
00268 /* Note: Literals values are defined from register SR2 bits SMPSF and SMPSBF  */
00269 /*       but they are also used as register CR5 bits SMPSEN and SMPSBEN,      */
00270 /*       as used by all SMPS operating mode functions targetting different    */
00271 /*       registers:                                                           */
00272 /*       "LL_PWR_SMPS_SetMode()", "LL_PWR_SMPS_GetMode()"                     */
00273 /*       and "LL_PWR_SMPS_GetEffectiveMode()".                                */
00274 #define PWR_SMPS_BYPASS                 (PWR_SR2_SMPSBF) /*!< SMPS step down in bypass mode  */
00275 #define PWR_SMPS_STEP_DOWN              (PWR_SR2_SMPSF)  /*!< SMPS step down in step down mode if system low power mode is run, LP run or stop0. If system low power mode is stop1, stop2, standby, shutdown, then SMPS is forced in mode open to preserve energy stored in decoupling capacitor as long as possible. */
00276 /**
00277   * @}
00278   */
00279
00280 /** @defgroup PWREx_SMPS_STARTUP_CURRENT SMPS step down converter supply startup current selection
00281   * @{
00282   */
00283 #define PWR_SMPS_STARTUP_CURRENT_80MA   (0x00000000U)                                            /*!< SMPS step down converter supply startup current 80mA */
00284 #define PWR_SMPS_STARTUP_CURRENT_100MA  (                                      PWR_CR5_SMPSSC_0) /*!< SMPS step down converter supply startup current 100mA */
00285 #define PWR_SMPS_STARTUP_CURRENT_120MA  (                   PWR_CR5_SMPSSC_1                   ) /*!< SMPS step down converter supply startup current 120mA */
00286 #define PWR_SMPS_STARTUP_CURRENT_140MA  (                   PWR_CR5_SMPSSC_1 | PWR_CR5_SMPSSC_0) /*!< SMPS step down converter supply startup current 140mA */
00287 #define PWR_SMPS_STARTUP_CURRENT_160MA  (PWR_CR5_SMPSSC_2                                      ) /*!< SMPS step down converter supply startup current 160mA */
00288 #define PWR_SMPS_STARTUP_CURRENT_180MA  (PWR_CR5_SMPSSC_2 |                    PWR_CR5_SMPSSC_0) /*!< SMPS step down converter supply startup current 180mA */
00289 #define PWR_SMPS_STARTUP_CURRENT_200MA  (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_1                   ) /*!< SMPS step down converter supply startup current 200mA */
00290 #define PWR_SMPS_STARTUP_CURRENT_220MA  (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_1 | PWR_CR5_SMPSSC_0) /*!< SMPS step down converter supply startup current 220mA */
00291 /**
00292   * @}
00293   */
00294
00295 /** @defgroup PWREx_SMPS_OUTPUT_VOLTAGE_LEVEL SMPS step down converter output voltage scaling voltage level
00296   * @{
00297   */
00298 /* Note: SMPS voltage is trimmed during device production to control
00299          the actual voltage level variation from device to device. */
00300 #define PWR_SMPS_OUTPUT_VOLTAGE_1V20  (0x00000000U)                                                                   /*!< SMPS step down converter supply output voltage 1.20V */
00301 #define PWR_SMPS_OUTPUT_VOLTAGE_1V25  (                                                            PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.25V */
00302 #define PWR_SMPS_OUTPUT_VOLTAGE_1V30  (                                        PWR_CR5_SMPSVOS_1                    ) /*!< SMPS step down converter supply output voltage 1.30V */
00303 #define PWR_SMPS_OUTPUT_VOLTAGE_1V35  (                                        PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.35V */
00304 #define PWR_SMPS_OUTPUT_VOLTAGE_1V40  (                    PWR_CR5_SMPSVOS_2                                        ) /*!< SMPS step down converter supply output voltage 1.40V */
00305 #define PWR_SMPS_OUTPUT_VOLTAGE_1V45  (                    PWR_CR5_SMPSVOS_2 |                     PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.45V */
00306 #define PWR_SMPS_OUTPUT_VOLTAGE_1V50  (                    PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1                    ) /*!< SMPS step down converter supply output voltage 1.50V */
00307 #define PWR_SMPS_OUTPUT_VOLTAGE_1V55  (                    PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.55V */
00308 #define PWR_SMPS_OUTPUT_VOLTAGE_1V60  (PWR_CR5_SMPSVOS_3                                                            ) /*!< SMPS step down converter supply output voltage 1.60V */
00309 #define PWR_SMPS_OUTPUT_VOLTAGE_1V65  (PWR_CR5_SMPSVOS_3 |                                         PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.65V */
00310 #define PWR_SMPS_OUTPUT_VOLTAGE_1V70  (PWR_CR5_SMPSVOS_3 |                     PWR_CR5_SMPSVOS_1                    ) /*!< SMPS step down converter supply output voltage 1.70V */
00311 #define PWR_SMPS_OUTPUT_VOLTAGE_1V75  (PWR_CR5_SMPSVOS_3 |                     PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.75V */
00312 #define PWR_SMPS_OUTPUT_VOLTAGE_1V80  (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2                                        ) /*!< SMPS step down converter supply output voltage 1.80V */
00313 #define PWR_SMPS_OUTPUT_VOLTAGE_1V85  (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 |                     PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.85V */
00314 #define PWR_SMPS_OUTPUT_VOLTAGE_1V90  (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1                    ) /*!< SMPS step down converter supply output voltage 1.90V */
00315 /**
00316   * @}
00317   */
00318 #endif
00319
00320 /** @defgroup PWREx_Flag  PWR Status Flags
00321   *        Elements values convention: 0000 0000 0XXY YYYYb
00322   *           - Y YYYY  : Flag position in the XX register (5 bits)
00323   *           - XX  : Status register (2 bits)
00324   *                 - 01: SR1 register
00325   *                 - 10: SR2 register
00326   *                 - 11: C2_SCR register
00327   *        The only exception is PWR_FLAG_WUF, encompassing all
00328   *        wake-up flags and set to PWR_SR1_WUF.
00329   * @{
00330   */
00331 /*--------------------------------SR1-------------------------------*/
00332 #define PWR_FLAG_WUF1                       (0x0020U)   /*!< Wakeup event on wakeup pin 1 */
00333 #if defined(PWR_CR3_EWUP2)
00334 #define PWR_FLAG_WUF2                       (0x0021U)   /*!< Wakeup event on wakeup pin 2 */
00335 #endif
00336 #if defined(PWR_CR3_EWUP3)
00337 #define PWR_FLAG_WUF3                       (0x0022U)   /*!< Wakeup event on wakeup pin 3 */
00338 #endif
00339 #define PWR_FLAG_WUF4                       (0x0023U)   /*!< Wakeup event on wakeup pin 4 */
00340 #if defined(PWR_CR3_EWUP5)
00341 #define PWR_FLAG_WUF5                       (0x0024U)   /*!< Wakeup event on wakeup pin 5 */
00342 #endif
00343 #define PWR_FLAG_WU                         PWR_SR1_WUF          /*!< Encompass wakeup event on all wakeup pins */
00344
00345 #if defined(PWR_CR5_SMPSEN)
00346 #define PWR_FLAG_FRCBYPI                    (0x0027U)   /*!< SMPS Forced in Bypass Interrupt Flag */
00347 #endif
00348 #define PWR_FLAG_BHWF                       (0x0029U)   /*!< BLE_Host WakeUp Flag */
00349 #define PWR_FLAG_RFPHASEI                   (0x002BU)   /*!< Radio Phase Interrupt Flag */
00350 #define PWR_FLAG_BLEACTI                    (0x002CU)   /*!< BLE Activity Interrupt Flag */
00351 #define PWR_FLAG_802ACTI                    (0x002DU)   /*!< 802.15.4 Activity Interrupt Flag */
00352 #define PWR_FLAG_HOLDC2I                    (0x002EU)   /*!< CPU2 on-Hold Interrupt Flag */
00353 #define PWR_FLAG_WUFI                       (0x002FU)   /*!< Wakeup on internal wakeup line */
00354
00355 /*--------------------------------SR2-------------------------------*/
00356 #if defined(PWR_CR5_SMPSEN)
00357 #define PWR_FLAG_SMPSRDYF                   (0x0040U)   /*!< SMPS Ready Flag */
00358 #define PWR_FLAG_SMPSBYPF                   (0x0041U)   /*!< SMPS Bypass Flag */
00359 #endif
00360
00361 #define PWR_FLAG_REGLPS                     (0x0048U)   /*!< Low-power regulator start flag */
00362 #define PWR_FLAG_REGLPF                     (0x0049U)   /*!< Low-power regulator flag */
00363
00364 #if defined(PWR_CR1_VOS)
00365 #define PWR_FLAG_VOSF                       (0x004AU)   /*!< Voltage scaling flag */
00366 #endif
00367 #define PWR_FLAG_PVDO                       (0x004BU)   /*!< Power Voltage Detector output flag */
00368
00369 #define PWR_FLAG_PVMO1                      (0x004CU)   /*!< Power Voltage Monitoring 1 output flag */
00370 #define PWR_FLAG_PVMO3                      (0x004EU)   /*!< Power Voltage Monitoring 3 output flag */
00371
00372 /*------------------------------EXTSCR---------------------------*/
00373 #define PWR_FLAG_SB                         (0x0068U)   /*!< System Standby flag for CPU1 */
00374 #define PWR_FLAG_STOP                       (0x0069U)   /*!< System Stop flag for CPU1 */
00375
00376 #define PWR_FLAG_C2SB                       (0x006AU)   /*!< System Standby flag for CPU2 */
00377 #define PWR_FLAG_C2STOP                     (0x006BU)   /*!< System Stop flag for CPU2 */
00378
00379 #define PWR_FLAG_CRITICAL_RF_PHASE          (0x006DU)   /*!< Critical radio system phase flag */
00380 #define PWR_FLAG_C1DEEPSLEEP                (0x006EU)   /*!< CPU1 DeepSleep Flag */
00381 #define PWR_FLAG_C2DEEPSLEEP                (0x006FU)   /*!< CPU2 DeepSleep Flag */
00382 /**
00383   * @}
00384   */
00385
00386 /** @defgroup PWREx_WakeUpTarget_Definition PWR Wakeup Target Definition
00387   * @{
00388   */
00389 #define PWR_WAKEUPTARGET_CPU1          (0x00000001U)
00390 #define PWR_WAKEUPTARGET_CPU2          (0x00000002U)
00391 #define PWR_WAKEUPTARGET_ALL_CPU       (PWR_WAKEUPTARGET_CPU1 | PWR_WAKEUPTARGET_CPU2)
00392 #define PWR_WAKEUPTARGET_RF            (0x00000004U)
00393 /**
00394   * @}
00395   */
00396
00397 /** @defgroup PWREx_Core_Select PWREx Core definition
00398   * @{
00399   */
00400 #define PWR_CORE_CPU1               (0x00000000U)
00401 #define PWR_CORE_CPU2               (0x00000001U)
00402 /**
00403   * @}
00404   */
00405
00406 /**
00407   * @}
00408   */
00409 /* Private define ------------------------------------------------------------*/
00410 /** @defgroup PWR_Private_Defines PWR Private Defines
00411   * @{
00412   */
00413
00414 /** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines
00415   * @{
00416   */
00417 #if defined(PWR_CR2_PVME1)
00418 #define PWR_EXTI_LINE_PVM1  (LL_EXTI_LINE_31)  /*!< External interrupt line 31 Connected to PVM1 */
00419 #endif
00420 #define PWR_EXTI_LINE_PVM3  (LL_EXTI_LINE_33)  /*!< External interrupt line 33 Connected to PVM3 */
00421 /**
00422   * @}
00423   */
00424
00425 /** @defgroup PWR_PVM_Mode_Mask PWR PVM Mode Mask
00426   * @{
00427   */
00428 /* Note: On STM32WB serie, power PVD event is not available on AIEC lines     */
00429 /*       (only interruption is available through AIEC line 16).               */
00430 #define PVM_MODE_IT               (0x00010000U)  /*!< Mask for interruption yielded by PVM threshold crossing */
00431 #define PVM_MODE_EVT              (0x00020000U)  /*!< Mask for event yielded by PVM threshold crossing */
00432 #define PVM_RISING_EDGE           (0x00000001U)  /*!< Mask for rising edge set as PVM trigger                 */
00433 #define PVM_FALLING_EDGE          (0x00000002U)  /*!< Mask for falling edge set as PVM trigger                */
00434 #define PVM_RISING_FALLING_EDGE   (0x00000003U)  /*!< Mask for rising and falling edges set as PVM trigger    */
00435 /**
00436   * @}
00437   */
00438
00439 /**
00440   * @}
00441   */
00442
00443 /* Exported macros -----------------------------------------------------------*/
00444 /** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros
00445  * @{
00446  */
00447
00448 #if defined(PWR_CR2_PVME1)
00449 /**
00450   * @brief Enable the PVM1 Extended Interrupt C1 Line.
00451   * @retval None
00452   */
00453 #define __HAL_PWR_PVM1_EXTI_ENABLE_IT()   LL_EXTI_EnableIT_0_31(PWR_EXTI_LINE_PVM1)
00454
00455 /**
00456   * @brief Enable the PVM1 Extended Interrupt C2 Line.
00457   * @retval None
00458   */
00459 #define __HAL_PWR_PVM1_EXTIC2_ENABLE_IT()   LL_C2_EXTI_EnableIT_0_31(PWR_EXTI_LINE_PVM1)
00460
00461 /**
00462   * @brief Disable the PVM1 Extended Interrupt C1 Line.
00463   * @retval None
00464   */
00465 #define __HAL_PWR_PVM1_EXTI_DISABLE_IT()  LL_EXTI_DisableIT_0_31(PWR_EXTI_LINE_PVM1)
00466
00467 /**
00468   * @brief Disable the PVM1 Extended Interrupt C2 Line.
00469   * @retval None
00470   */
00471 #define __HAL_PWR_PVM1_EXTIC2_DISABLE_IT()  LL_C2_EXTI_DisableIT_0_31(PWR_EXTI_LINE_PVM1)
00472
00473 /**
00474   * @brief Enable the PVM1 Event C1 Line.
00475   * @retval None
00476   */
00477 #define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT()   LL_EXTI_EnableEvent_0_31(PWR_EXTI_LINE_PVM1)
00478
00479 /**
00480   * @brief Enable the PVM1 Event C2 Line.
00481   * @retval None
00482   */
00483 #define __HAL_PWR_PVM1_EXTIC2_ENABLE_EVENT()   LL_C2_EXTI_EnableEvent_0_31(PWR_EXTI_LINE_PVM1)
00484
00485 /**
00486   * @brief Disable the PVM1 Event C1 Line.
00487   * @retval None
00488   */
00489 #define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT()  LL_EXTI_DisableEvent_0_31(PWR_EXTI_LINE_PVM1)
00490
00491 /**
00492   * @brief Disable the PVM1 Event C2 Line.
00493   * @retval None
00494   */
00495 #define __HAL_PWR_PVM1_EXTIC2_DISABLE_EVENT()  LL_C2_EXTI_DisableEvent_0_31(PWR_EXTI_LINE_PVM1)
00496
00497 /**
00498   * @brief Enable the PVM1 Extended Interrupt Rising Trigger.
00499   * @note  PVM1 flag polarity is inverted compared to EXTI line, therefore
00500   *        EXTI rising and falling logic edges are inverted versus PVM1 voltage edges.
00501   * @retval None
00502   */
00503 #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE()   LL_EXTI_EnableRisingTrig_0_31(PWR_EXTI_LINE_PVM1)
00504
00505 /**
00506   * @brief Disable the PVM1 Extended Interrupt Rising Trigger.
00507   * @note  PVM1 flag polarity is inverted compared to EXTI line, therefore
00508   *        EXTI rising and falling logic edges are inverted versus PVM1 voltage edges.
00509   * @retval None
00510   */
00511 #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE()  LL_EXTI_DisableRisingTrig_0_31(PWR_EXTI_LINE_PVM1)
00512
00513 /**
00514   * @brief Enable the PVM1 Extended Interrupt Falling Trigger.
00515   * @note  PVM1 flag polarity is inverted compared to EXTI line, therefore
00516   *        EXTI rising and falling logic edges are inverted versus PVM1 voltage edges.
00517   * @retval None
00518   */
00519 #define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE()   LL_EXTI_EnableFallingTrig_0_31(PWR_EXTI_LINE_PVM1)
00520
00521
00522 /**
00523   * @brief Disable the PVM1 Extended Interrupt Falling Trigger.
00524   * @note  PVM1 flag polarity is inverted compared to EXTI line, therefore
00525   *        EXTI rising and falling logic edges are inverted versus PVM1 voltage edges.
00526   * @retval None
00527   */
00528 #define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE()  LL_EXTI_DisableFallingTrig_0_31(PWR_EXTI_LINE_PVM1)
00529
00530 /**
00531   * @brief  PVM1 EXTI line configuration: set rising & falling edge trigger.
00532   * @retval None
00533   */
00534 #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE()  \
00535   do {                                                    \
00536     __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE();             \
00537     __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();            \
00538   } while(0)
00539
00540 /**
00541   * @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger.
00542   * @retval None
00543   */
00544 #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE()  \
00545   do {                                                     \
00546     __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE();             \
00547     __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE();            \
00548   } while(0)
00549
00550 /**
00551   * @brief  Generate a Software interrupt on selected EXTI line.
00552   * @retval None
00553   */
00554 #define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(PWR_EXTI_LINE_PVM1)
00555
00556 /**
00557   * @brief Check whether the specified PVM1 EXTI interrupt flag is set or not.
00558   * @retval EXTI PVM1 Line Status.
00559   */
00560 #define __HAL_PWR_PVM1_EXTI_GET_FLAG()  LL_EXTI_ReadFlag_0_31(PWR_EXTI_LINE_PVM1)
00561
00562 /**
00563   * @brief Clear the PVM1 EXTI flag.
00564   * @retval None
00565   */
00566 #define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG()  LL_EXTI_ClearFlag_0_31(PWR_EXTI_LINE_PVM1)
00567
00568 #endif
00569
00570 /**
00571   * @brief Enable the PVM3 Extended Interrupt C1 Line.
00572   * @retval None
00573   */
00574 #define __HAL_PWR_PVM3_EXTI_ENABLE_IT()   LL_EXTI_EnableIT_32_63(PWR_EXTI_LINE_PVM3)
00575
00576 /**
00577   * @brief Enable the PVM3 Extended Interrupt C2 Line.
00578   * @retval None
00579   */
00580 #define __HAL_PWR_PVM3_EXTIC2_ENABLE_IT()   LL_C2_EXTI_EnableIT_32_63(PWR_EXTI_LINE_PVM3)
00581
00582 /**
00583   * @brief Disable the PVM3 Extended Interrupt C1 Line.
00584   * @retval None
00585   */
00586 #define __HAL_PWR_PVM3_EXTI_DISABLE_IT()  LL_EXTI_DisableIT_32_63(PWR_EXTI_LINE_PVM3)
00587
00588 /**
00589   * @brief Disable the PVM3 Extended Interrupt C2 Line.
00590   * @retval None
00591   */
00592 #define __HAL_PWR_PVM3_EXTIC2_DISABLE_IT()  LL_C2_EXTI_DisableIT_32_63(PWR_EXTI_LINE_PVM3)
00593
00594 /**
00595   * @brief Enable the PVM3 Event C1 Line.
00596   * @retval None
00597   */
00598 #define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT()   LL_EXTI_EnableEvent_32_63(PWR_EXTI_LINE_PVM3)
00599
00600 /**
00601   * @brief Enable the PVM3 Event C2 Line.
00602   * @retval None
00603   */
00604 #define __HAL_PWR_PVM3_EXTIC2_ENABLE_EVENT()   LL_C2_EXTI_EnableEvent_32_63(PWR_EXTI_LINE_PVM3)
00605
00606 /**
00607   * @brief Disable the PVM3 Event C1 Line.
00608   * @retval None
00609   */
00610 #define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT()  LL_EXTI_DisableEvent_32_63(PWR_EXTI_LINE_PVM3)
00611
00612 /**
00613   * @brief Disable the PVM3 Event C2 Line.
00614   * @retval None
00615   */
00616 #define __HAL_PWR_PVM3_EXTIC2_DISABLE_EVENT()  LL_C2_EXTI_DisableEvent_32_63(PWR_EXTI_LINE_PVM3)
00617
00618 /**
00619   * @brief Enable the PVM3 Extended Interrupt Rising Trigger.
00620   * @note  PVM3 flag polarity is inverted compared to EXTI line, therefore
00621   *        EXTI rising and falling logic edges are inverted versus PVM3 voltage edges.
00622   * @retval None
00623   */
00624 #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE()   LL_EXTI_EnableRisingTrig_32_63(PWR_EXTI_LINE_PVM3)
00625
00626 /**
00627   * @brief Disable the PVM3 Extended Interrupt Rising Trigger.
00628   * @note  PVM3 flag polarity is inverted compared to EXTI line, therefore
00629   *        EXTI rising and falling logic edges are inverted versus PVM3 voltage edges.
00630   * @retval None
00631   */
00632 #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE()  LL_EXTI_DisableRisingTrig_32_63(PWR_EXTI_LINE_PVM3)
00633
00634 /**
00635   * @brief Enable the PVM3 Extended Interrupt Falling Trigger.
00636   * @note  PVM3 flag polarity is inverted compared to EXTI line, therefore
00637   *        EXTI rising and falling logic edges are inverted versus PVM3 voltage edges.
00638   * @retval None
00639   */
00640 #define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE()   LL_EXTI_EnableFallingTrig_32_63(PWR_EXTI_LINE_PVM3)
00641
00642
00643 /**
00644   * @brief Disable the PVM3 Extended Interrupt Falling Trigger.
00645   * @note  PVM3 flag polarity is inverted compared to EXTI line, therefore
00646   *        EXTI rising and falling logic edges are inverted versus PVM3 voltage edges.
00647   * @retval None
00648   */
00649 #define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE()  LL_EXTI_DisableFallingTrig_32_63(PWR_EXTI_LINE_PVM3)
00650
00651 /**
00652   * @brief  PVM3 EXTI line configuration: set rising & falling edge trigger.
00653   * @retval None
00654   */
00655 #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE()  \
00656   do {                                                    \
00657     __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();             \
00658     __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();            \
00659   } while(0)
00660
00661 /**
00662   * @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger.
00663   * @retval None
00664   */
00665 #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE()  \
00666   do {                                                     \
00667     __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();             \
00668     __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE();            \
00669   } while(0)
00670
00671 /**
00672   * @brief  Generate a Software interrupt on selected EXTI line.
00673   * @retval None
00674   */
00675 #define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_32_63(PWR_EXTI_LINE_PVM3)
00676
00677 /**
00678   * @brief Check whether the specified PVM3 EXTI interrupt flag is set or not.
00679   * @retval EXTI PVM3 Line Status.
00680   */
00681 #define __HAL_PWR_PVM3_EXTI_GET_FLAG()  LL_EXTI_ReadFlag_32_63(PWR_EXTI_LINE_PVM3)
00682
00683 /**
00684   * @brief Clear the PVM3 EXTI flag.
00685   * @retval None
00686   */
00687 #define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG()  LL_EXTI_ClearFlag_32_63(PWR_EXTI_LINE_PVM3)
00688
00689 #if defined(PWR_CR1_VOS)
00690 /**
00691   * @brief Configure the main internal regulator output voltage.
00692   * @param __REGULATOR__ specifies the regulator output voltage to achieve
00693   *         a tradeoff between performance and power consumption.
00694   *          This parameter can be one of the following values:
00695   *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1  Regulator voltage output range 1 mode,
00696   *                                                typical output voltage at 1.2 V,
00697   *                                                system frequency up to 64 MHz.
00698   *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2  Regulator voltage output range 2 mode,
00699   *                                                typical output voltage at 1.0 V,
00700   *                                                system frequency up to 16 MHz.
00701   * @note  This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check
00702   *        whether or not VOSF flag is cleared when moving from range 2 to range 1. User
00703   *        may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting.
00704   * @retval None
00705   */
00706 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do {                                                     \
00707                                                             __IO uint32_t tmpreg;                               \
00708                                                             MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \
00709                                                             /* Delay after an RCC peripheral clock enabling */  \
00710                                                             tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS);           \
00711                                                             UNUSED(tmpreg);                                     \
00712                                                           } while(0)
00713 #endif
00714
00715 /**
00716   * @brief  Wakeup BLE controller from its sleep mode
00717   * @note   This bit is automatically reset when 802.15.4 controller
00718   *         exit its sleep mode.
00719   * @retval None
00720   */
00721 #define __HAL_C2_PWR_WAKEUP_BLE() LL_C2_PWR_WakeUp_BLE()
00722
00723 /**
00724   * @brief  Wakeup 802.15.4 controller from its sleep mode
00725   * @note   This bit is automatically reset when 802.15.4 controller
00726   *         exit its sleep mode.
00727   * @retval None
00728   */
00729 #define __HAL_C2_PWR_WAKEUP_802_15_4() LL_C2_PWR_WakeUp_802_15_4()
00730
00731 /**
00732   * @}
00733   */
00734
00735 /* Private macros --------------------------------------------------------*/
00736 /** @addtogroup  PWREx_Private_Macros   PWR Extended Private Macros
00737   * @{
00738   */
00739 #if defined(PWR_CR3_EWUP2)
00740 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1_HIGH) || \
00741                                 ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \
00742                                 ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \
00743                                 ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \
00744                                 ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \
00745                                 ((PIN) == PWR_WAKEUP_PIN1_LOW) || \
00746                                 ((PIN) == PWR_WAKEUP_PIN2_LOW) || \
00747                                 ((PIN) == PWR_WAKEUP_PIN3_LOW) || \
00748                                 ((PIN) == PWR_WAKEUP_PIN4_LOW) || \
00749                                 ((PIN) == PWR_WAKEUP_PIN5_LOW))
00750 #else
00751 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1_HIGH) || \
00752                                 ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \
00753                                 ((PIN) == PWR_WAKEUP_PIN1_LOW) || \
00754                                 ((PIN) == PWR_WAKEUP_PIN4_LOW))
00755 #endif
00756
00757 #define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY)  (((POLARITY) == PWR_PIN_POLARITY_HIGH) || \
00758                                                ((POLARITY) == PWR_PIN_POLARITY_LOW))
00759
00760 #if defined(PWR_CR2_PVME1)
00761 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\
00762                                ((TYPE) == PWR_PVM_3))
00763 #else
00764 #define IS_PWR_PVM_TYPE(TYPE) ((TYPE) == PWR_PVM_3)
00765 #endif
00766
00767 #define IS_PWR_PVM_MODE(MODE)  (((MODE) == PWR_PVM_MODE_NORMAL)              ||\
00768                                 ((MODE) == PWR_PVM_MODE_IT_RISING)           ||\
00769                                 ((MODE) == PWR_PVM_MODE_IT_FALLING)          ||\
00770                                 ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING)   ||\
00771                                 ((MODE) == PWR_PVM_MODE_EVENT_RISING)        ||\
00772                                 ((MODE) == PWR_PVM_MODE_EVENT_FALLING)       ||\
00773                                 ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING))
00774
00775 #define IS_PWR_FLASH_POWERDOWN(__MODE__)    ((((__MODE__) & (PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP)) != 0x00u) && \
00776                                              (((__MODE__) & ~(PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP)) == 0x00u))
00777
00778 #if defined(PWR_CR1_VOS)
00779 #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
00780                                              ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
00781 #endif
00782
00783 #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
00784                                                   ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
00785
00786 #define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\
00787                                            ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE))
00788
00789
00790 #define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00)
00791
00792 #if defined(GPIOD)
00793 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
00794                            ((GPIO) == PWR_GPIO_B) ||\
00795                            ((GPIO) == PWR_GPIO_C) ||\
00796                            ((GPIO) == PWR_GPIO_D) ||\
00797                            ((GPIO) == PWR_GPIO_E) ||\
00798                            ((GPIO) == PWR_GPIO_H))
00799 #else
00800 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
00801                            ((GPIO) == PWR_GPIO_B) ||\
00802                            ((GPIO) == PWR_GPIO_C) ||\
00803                            ((GPIO) == PWR_GPIO_E) ||\
00804                            ((GPIO) == PWR_GPIO_H))
00805 #endif
00806
00807 #if defined(PWR_CR5_SMPSEN)
00808 #define IS_PWR_SMPS_MODE(SMPS_MODE) (((SMPS_MODE) == PWR_SMPS_BYPASS)    ||\
00809                                      ((SMPS_MODE) == PWR_SMPS_STEP_DOWN))
00810
00811 #define IS_PWR_SMPS_STARTUP_CURRENT(SMPS_STARTUP_CURRENT) (((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_80MA)  ||\
00812                                                            ((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_100MA) ||\
00813                                                            ((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_120MA) ||\
00814                                                            ((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_140MA) ||\
00815                                                            ((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_160MA) ||\
00816                                                            ((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_180MA) ||\
00817                                                            ((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_200MA) ||\
00818                                                            ((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_220MA))
00819
00820 #define IS_PWR_SMPS_OUTPUT_VOLTAGE(SMPS_OUTPUT_VOLTAGE) (((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V20) ||\
00821                                                          ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V25) ||\
00822                                                          ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V30) ||\
00823                                                          ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V35) ||\
00824                                                          ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V40) ||\
00825                                                          ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V45) ||\
00826                                                          ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V50) ||\
00827                                                          ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V55) ||\
00828                                                          ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V60) ||\
00829                                                          ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V65) ||\
00830                                                          ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V70) ||\
00831                                                          ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V75) ||\
00832                                                          ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V80) ||\
00833                                                          ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V85) ||\
00834                                                          ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V90))
00835 #endif
00836
00837 #define IS_PWR_CORE(CPU)  (((CPU) == PWR_CORE_CPU1) || ((CPU) == PWR_CORE_CPU2))
00838
00839 #define IS_PWR_CORE_HOLD_RELEASE(CPU)  ((CPU) == PWR_CORE_CPU2)
00840
00841 /**
00842   * @}
00843   */
00844
00845
00846 /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions
00847   * @{
00848   */
00849
00850 /** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
00851   * @{
00852   */
00853
00854 /* Peripheral Control functions  **********************************************/
00855 uint32_t          HAL_PWREx_GetVoltageRange(void);
00856 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
00857
00858 void              HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection);
00859 void              HAL_PWREx_DisableBatteryCharging(void);
00860
00861 void              HAL_PWREx_EnableVddUSB(void);
00862 void              HAL_PWREx_DisableVddUSB(void);
00863
00864 void              HAL_PWREx_EnableInternalWakeUpLine(void);
00865 void              HAL_PWREx_DisableInternalWakeUpLine(void);
00866
00867 #if defined(PWR_CR5_SMPSEN)
00868 void              HAL_PWREx_EnableBORH_SMPSBypassIT(void);
00869 void              HAL_PWREx_DisableBORH_SMPSBypassIT(void);
00870 #endif
00871 void              HAL_PWREx_EnableRFPhaseIT(void);
00872 void              HAL_PWREx_DisableRFPhaseIT(void);
00873 void              HAL_PWREx_EnableBLEActivityIT(void);
00874 void              HAL_PWREx_DisableBLEActivityIT(void);
00875 void              HAL_PWREx_Enable802ActivityIT(void);
00876 void              HAL_PWREx_Disable802ActivityIT(void);
00877 void              HAL_PWREx_EnableHOLDC2IT(void);
00878 void              HAL_PWREx_DisableHOLDC2IT(void);
00879
00880 void              HAL_PWREx_HoldCore(uint32_t CPU);
00881 void              HAL_PWREx_ReleaseCore(uint32_t CPU);
00882
00883 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
00884 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
00885 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
00886 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
00887 void              HAL_PWREx_EnablePullUpPullDownConfig(void);
00888 void              HAL_PWREx_DisablePullUpPullDownConfig(void);
00889
00890 #if defined(PWR_CR5_SMPSEN)
00891 void              HAL_PWREx_SetBORConfig(uint32_t BORConfiguration);
00892 uint32_t          HAL_PWREx_GetBORConfig(void);
00893 #endif
00894
00895 void              HAL_PWREx_EnableSRAMRetention(void);
00896 void              HAL_PWREx_DisableSRAMRetention(void);
00897
00898 void              HAL_PWREx_EnableFlashPowerDown(uint32_t PowerMode);
00899 void              HAL_PWREx_DisableFlashPowerDown(uint32_t PowerMode);
00900
00901 #if defined(PWR_CR2_PVME1)
00902 void              HAL_PWREx_EnablePVM1(void);
00903 void              HAL_PWREx_DisablePVM1(void);
00904 #endif
00905
00906 void              HAL_PWREx_EnablePVM3(void);
00907 void              HAL_PWREx_DisablePVM3(void);
00908
00909 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM);
00910
00911 #if defined(PWR_CR5_SMPSEN)
00912 HAL_StatusTypeDef HAL_PWREx_ConfigSMPS(PWR_SMPSTypeDef *sConfigSMPS);
00913 void              HAL_PWREx_SMPS_SetMode(uint32_t OperatingMode);
00914 uint32_t          HAL_PWREx_SMPS_GetEffectiveMode(void);
00915 #endif
00916
00917 /* WakeUp pins configuration functions ****************************************/
00918 void              HAL_PWREx_EnableWakeUpPin(uint32_t WakeUpPinPolarity, uint32_t wakeupTarget);
00919 uint32_t          HAL_PWREx_GetWakeupFlag(uint32_t WakeUpFlag);
00920 HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag(uint32_t WakeUpFlag);
00921
00922 /* Low Power modes configuration functions ************************************/
00923 void              HAL_PWREx_EnableLowPowerRunMode(void);
00924 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void);
00925
00926 void              HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry);
00927 void              HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry);
00928 void              HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry);
00929 void              HAL_PWREx_EnterSHUTDOWNMode(void);
00930
00931 void              HAL_PWREx_PVD_PVM_IRQHandler(void);
00932
00933 #if defined(PWR_CR2_PVME1)
00934 void              HAL_PWREx_PVM1Callback(void);
00935 #endif
00936 void              HAL_PWREx_PVM3Callback(void);
00937
00938 /**
00939   * @}
00940   */
00941
00942 /**
00943   * @}
00944   */
00945
00946 /**
00947   * @}
00948   */
00949
00950 /**
00951   * @}
00952   */
00953
00954 #ifdef __cplusplus
00955 }
00956 #endif
00957
00958
00959 #endif /* STM32WBxx_HAL_PWR_EX_H */
00960
00961 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:35 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_qspi.c Source File

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stm32wbxx_hal_qspi.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_qspi.c
00004   * @author  MCD Application Team
00005   * @brief   QSPI HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the QuadSPI interface (QSPI).
00008   *           + Initialization and de-initialization functions
00009   *           + Indirect functional mode management
00010   *           + Memory-mapped functional mode management
00011   *           + Auto-polling functional mode management
00012   *           + Interrupts and flags management
00013   *           + DMA channel configuration for indirect functional mode
00014   *           + Errors management and abort functionality
00015   *
00016   *
00017   @verbatim
00018  ===============================================================================
00019                         ##### How to use this driver #####
00020  ===============================================================================
00021   [..]
00022     *** Initialization ***
00023     ======================
00024     [..]
00025       (#) As prerequisite, fill in the HAL_QSPI_MspInit() :
00026         (++) Enable QuadSPI clock interface with __HAL_RCC_QUADSPI_CLK_ENABLE().
00027         (++) Reset QuadSPI Peripheral with __HAL_RCC_QUADSPI_FORCE_RESET() and __HAL_RCC_QUADSPI_RELEASE_RESET().
00028         (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
00029         (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
00030         (++) If interrupt mode is used, enable and configure QuadSPI global
00031             interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
00032         (++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
00033             with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
00034             link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
00035             DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
00036       (#) Configure the flash size, the clock prescaler, the fifo threshold, the
00037           clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.
00038
00039     *** Indirect functional mode ***
00040     ================================
00041     [..]
00042       (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
00043           functions :
00044          (++) Instruction phase : the mode used and if present the instruction opcode.
00045          (++) Address phase : the mode used and if present the size and the address value.
00046          (++) Alternate-bytes phase : the mode used and if present the size and the alternate
00047              bytes values.
00048          (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
00049          (++) Data phase : the mode used and if present the number of bytes.
00050          (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
00051              if activated.
00052          (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
00053       (#) If no data is required for the command, it is sent directly to the memory :
00054          (++) In polling mode, the output of the function is done when the transfer is complete.
00055          (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
00056       (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
00057           HAL_QSPI_Transmit_IT() after the command configuration :
00058          (++) In polling mode, the output of the function is done when the transfer is complete.
00059          (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
00060              is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
00061          (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
00062              HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
00063       (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
00064           HAL_QSPI_Receive_IT() after the command configuration :
00065          (++) In polling mode, the output of the function is done when the transfer is complete.
00066          (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
00067              is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
00068          (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
00069              HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
00070
00071     *** Auto-polling functional mode ***
00072     ====================================
00073     [..]
00074       (#) Configure the command sequence and the auto-polling functional mode using the
00075           HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
00076          (++) Instruction phase : the mode used and if present the instruction opcode.
00077          (++) Address phase : the mode used and if present the size and the address value.
00078          (++) Alternate-bytes phase : the mode used and if present the size and the alternate
00079              bytes values.
00080          (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
00081          (++) Data phase : the mode used.
00082          (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
00083              if activated.
00084          (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
00085          (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
00086              the polling interval and the automatic stop activation.
00087       (#) After the configuration :
00088          (++) In polling mode, the output of the function is done when the status match is reached. The
00089              automatic stop is activated to avoid an infinite loop.
00090          (++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
00091
00092     *** Memory-mapped functional mode ***
00093     =====================================
00094     [..]
00095       (#) Configure the command sequence and the memory-mapped functional mode using the
00096           HAL_QSPI_MemoryMapped() functions :
00097          (++) Instruction phase : the mode used and if present the instruction opcode.
00098          (++) Address phase : the mode used and the size.
00099          (++) Alternate-bytes phase : the mode used and if present the size and the alternate
00100              bytes values.
00101          (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
00102          (++) Data phase : the mode used.
00103          (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
00104              if activated.
00105          (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
00106          (++) The timeout activation and the timeout period.
00107       (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
00108           the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
00109
00110     *** Errors management and abort functionality ***
00111     =================================================
00112     [..]
00113       (#) HAL_QSPI_GetError() function gives the error raised during the last operation.
00114       (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and
00115           flushes the fifo :
00116          (++) In polling mode, the output of the function is done when the transfer
00117               complete bit is set and the busy bit cleared.
00118          (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when
00119               the transfer complete bit is set.
00120
00121     *** Control functions ***
00122     =========================
00123     [..]
00124       (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
00125       (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.
00126       (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.
00127       (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
00128
00129     *** Callback registration ***
00130     =============================================
00131     [..]
00132       The compilation define  USE_HAL_QSPI_REGISTER_CALLBACKS when set to 1
00133       allows the user to configure dynamically the driver callbacks.
00134
00135       Use Functions @ref HAL_QSPI_RegisterCallback() to register a user callback,
00136       it allows to register following callbacks:
00137         (+) ErrorCallback : callback when error occurs.
00138         (+) AbortCpltCallback : callback when abort is completed.
00139         (+) FifoThresholdCallback : callback when the fifo threshold is reached.
00140         (+) CmdCpltCallback : callback when a command without data is completed.
00141         (+) RxCpltCallback : callback when a reception transfer is completed.
00142         (+) TxCpltCallback : callback when a transmission transfer is completed.
00143         (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
00144         (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
00145         (+) StatusMatchCallback : callback when a status match occurs.
00146         (+) TimeOutCallback : callback when the timeout perioed expires.
00147         (+) MspInitCallback    : QSPI MspInit.
00148         (+) MspDeInitCallback  : QSPI MspDeInit.
00149       This function takes as parameters the HAL peripheral handle, the Callback ID
00150       and a pointer to the user callback function.
00151
00152       Use function @ref HAL_QSPI_UnRegisterCallback() to reset a callback to the default
00153       weak (surcharged) function. It allows to reset following callbacks:
00154         (+) ErrorCallback : callback when error occurs.
00155         (+) AbortCpltCallback : callback when abort is completed.
00156         (+) FifoThresholdCallback : callback when the fifo threshold is reached.
00157         (+) CmdCpltCallback : callback when a command without data is completed.
00158         (+) RxCpltCallback : callback when a reception transfer is completed.
00159         (+) TxCpltCallback : callback when a transmission transfer is completed.
00160         (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
00161         (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
00162         (+) StatusMatchCallback : callback when a status match occurs.
00163         (+) TimeOutCallback : callback when the timeout perioed expires.
00164         (+) MspInitCallback    : QSPI MspInit.
00165         (+) MspDeInitCallback  : QSPI MspDeInit.
00166       This function) takes as parameters the HAL peripheral handle and the Callback ID.
00167
00168       By default, after the @ref HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET
00169       all callbacks are reset to the corresponding legacy weak (surcharged) functions.
00170       Exception done for MspInit and MspDeInit callbacks that are respectively
00171       reset to the legacy weak (surcharged) functions in the @ref HAL_QSPI_Init
00172       and @ref  HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand).
00173       If not, MspInit or MspDeInit are not null, the @ref HAL_QSPI_Init and @ref HAL_QSPI_DeInit
00174       keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
00175
00176       Callbacks can be registered/unregistered in READY state only.
00177       Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
00178       in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
00179       during the Init/DeInit.
00180       In that case first register the MspInit/MspDeInit user callbacks
00181       using @ref HAL_QSPI_RegisterCallback before calling @ref HAL_QSPI_DeInit
00182       or @ref HAL_QSPI_Init function.
00183
00184       When The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS is set to 0 or
00185       not defined, the callback registering feature is not available
00186       and weak (surcharged) callbacks are used.
00187
00188     *** Workarounds linked to Silicon Limitation ***
00189     ====================================================
00190     [..]
00191       (#) Workarounds Implemented inside HAL Driver
00192          (++) Extra data written in the FIFO at the end of a read transfer
00193
00194   @endverbatim
00195   ******************************************************************************
00196   * @attention
00197   *
00198   * <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
00199   *
00200   * This software component is licensed by ST under BSD 3-Clause license,
00201   * the "License"; You may not use this file except in compliance with the
00202   * License. You may obtain a copy of the License at:
00203   *                       opensource.org/licenses/BSD-3-Clause
00204   *
00205   ******************************************************************************
00206   */
00207
00208 /* Includes ------------------------------------------------------------------*/
00209 #include "stm32wbxx_hal.h"
00210
00211 #if defined(QUADSPI)
00212
00213 /** @addtogroup STM32WBxx_HAL_Driver
00214   * @{
00215   */
00216
00217 /** @defgroup QSPI QSPI
00218   * @brief QSPI HAL module driver
00219   * @{
00220   */
00221 #ifdef HAL_QSPI_MODULE_ENABLED
00222
00223 /* Private typedef -----------------------------------------------------------*/
00224
00225 /* Private define ------------------------------------------------------------*/
00226 /** @defgroup QSPI_Private_Constants QSPI Private Constants
00227   * @{
00228   */
00229 #define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE 0x00000000U                     /*!<Indirect write mode*/
00230 #define QSPI_FUNCTIONAL_MODE_INDIRECT_READ  ((uint32_t)QUADSPI_CCR_FMODE_0) /*!<Indirect read mode*/
00231 #define QSPI_FUNCTIONAL_MODE_AUTO_POLLING   ((uint32_t)QUADSPI_CCR_FMODE_1) /*!<Automatic polling mode*/
00232 #define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED  ((uint32_t)QUADSPI_CCR_FMODE)   /*!<Memory-mapped mode*/
00233 /**
00234   * @}
00235   */
00236
00237 /* Private macro -------------------------------------------------------------*/
00238 /** @defgroup QSPI_Private_Macros QSPI Private Macros
00239   * @{
00240   */
00241 #define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \
00242                                        ((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ)  || \
00243                                        ((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING)   || \
00244                                        ((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
00245 /**
00246   * @}
00247   */
00248
00249 /* Private variables ---------------------------------------------------------*/
00250
00251 /* Private function prototypes -----------------------------------------------*/
00252 static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma);
00253 static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma);
00254 static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00255 static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00256 static void QSPI_DMAError(DMA_HandleTypeDef *hdma);
00257 static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma);
00258 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout);
00259 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode);
00260
00261 /* Exported functions --------------------------------------------------------*/
00262
00263 /** @defgroup QSPI_Exported_Functions QSPI Exported Functions
00264   * @{
00265   */
00266
00267 /** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions
00268   *  @brief    Initialization and Configuration functions
00269   *
00270 @verbatim
00271 ===============================================================================
00272             ##### Initialization and Configuration functions #####
00273  ===============================================================================
00274     [..]
00275     This subsection provides a set of functions allowing to :
00276       (+) Initialize the QuadSPI.
00277       (+) De-initialize the QuadSPI.
00278
00279 @endverbatim
00280   * @{
00281   */
00282
00283 /**
00284   * @brief Initialize the QSPI mode according to the specified parameters
00285   *        in the QSPI_InitTypeDef and initialize the associated handle.
00286   * @param hqspi : QSPI handle
00287   * @retval HAL status
00288   */
00289 HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
00290 {
00291   HAL_StatusTypeDef status;
00292   uint32_t tickstart = HAL_GetTick();
00293
00294   /* Check the QSPI handle allocation */
00295   if(hqspi == NULL)
00296   {
00297     return HAL_ERROR;
00298   }
00299
00300   /* Check the parameters */
00301   assert_param(IS_QUADSPI_ALL_INSTANCE(hqspi->Instance));
00302   assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));
00303   assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));
00304   assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));
00305   assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));
00306   assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));
00307   assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));
00308
00309   /* Process locked */
00310   __HAL_LOCK(hqspi);
00311
00312   if(hqspi->State == HAL_QSPI_STATE_RESET)
00313   {
00314     /* Allocate lock resource and initialize it */
00315     hqspi->Lock = HAL_UNLOCKED;
00316
00317 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00318     /* Reset Callback pointers in HAL_QSPI_STATE_RESET only */
00319     hqspi->ErrorCallback         = HAL_QSPI_ErrorCallback;
00320     hqspi->AbortCpltCallback     = HAL_QSPI_AbortCpltCallback;
00321     hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback;
00322     hqspi->CmdCpltCallback       = HAL_QSPI_CmdCpltCallback;
00323     hqspi->RxCpltCallback        = HAL_QSPI_RxCpltCallback;
00324     hqspi->TxCpltCallback        = HAL_QSPI_TxCpltCallback;
00325     hqspi->RxHalfCpltCallback    = HAL_QSPI_RxHalfCpltCallback;
00326     hqspi->TxHalfCpltCallback    = HAL_QSPI_TxHalfCpltCallback;
00327     hqspi->StatusMatchCallback   = HAL_QSPI_StatusMatchCallback;
00328     hqspi->TimeOutCallback       = HAL_QSPI_TimeOutCallback;
00329
00330     if(hqspi->MspInitCallback == NULL)
00331     {
00332       hqspi->MspInitCallback = HAL_QSPI_MspInit;
00333     }
00334
00335     /* Init the low level hardware */
00336     hqspi->MspInitCallback(hqspi);
00337 #else
00338     /* Init the low level hardware : GPIO, CLOCK */
00339     HAL_QSPI_MspInit(hqspi);
00340 #endif
00341
00342     /* Configure the default timeout for the QSPI memory access */
00343     HAL_QSPI_SetTimeout(hqspi, HAL_QSPI_TIMEOUT_DEFAULT_VALUE);
00344   }
00345
00346   /* Configure QSPI FIFO Threshold */
00347   MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
00348              ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos));
00349
00350   /* Wait till BUSY flag reset */
00351   status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
00352
00353   if(status == HAL_OK)
00354   {
00355     /* Configure QSPI Clock Prescaler and Sample Shift */
00356     MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT),
00357                ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) |
00358                 hqspi->Init.SampleShifting));
00359
00360     /* Configure QSPI Flash Size, CS High Time and Clock Mode */
00361     MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE),
00362                ((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) |
00363                 hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));
00364
00365     /* Enable the QSPI peripheral */
00366     __HAL_QSPI_ENABLE(hqspi);
00367
00368     /* Set QSPI error code to none */
00369     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00370
00371     /* Initialize the QSPI state */
00372     hqspi->State = HAL_QSPI_STATE_READY;
00373   }
00374
00375   /* Release Lock */
00376   __HAL_UNLOCK(hqspi);
00377
00378   /* Return function status */
00379   return status;
00380 }
00381
00382 /**
00383   * @brief De-Initialize the QSPI peripheral.
00384   * @param hqspi : QSPI handle
00385   * @retval HAL status
00386   */
00387 HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
00388 {
00389   /* Check the QSPI handle allocation */
00390   if(hqspi == NULL)
00391   {
00392     return HAL_ERROR;
00393   }
00394
00395   /* Process locked */
00396   __HAL_LOCK(hqspi);
00397
00398   /* Disable the QSPI Peripheral Clock */
00399   __HAL_QSPI_DISABLE(hqspi);
00400
00401 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00402   if(hqspi->MspDeInitCallback == NULL)
00403   {
00404     hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;
00405   }
00406
00407   /* DeInit the low level hardware */
00408   hqspi->MspDeInitCallback(hqspi);
00409 #else
00410   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
00411   HAL_QSPI_MspDeInit(hqspi);
00412 #endif
00413
00414   /* Set QSPI error code to none */
00415   hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00416
00417   /* Initialize the QSPI state */
00418   hqspi->State = HAL_QSPI_STATE_RESET;
00419
00420   /* Release Lock */
00421   __HAL_UNLOCK(hqspi);
00422
00423   return HAL_OK;
00424 }
00425
00426 /**
00427   * @brief Initialize the QSPI MSP.
00428   * @param hqspi : QSPI handle
00429   * @retval None
00430   */
00431 __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
00432 {
00433   /* Prevent unused argument(s) compilation warning */
00434   UNUSED(hqspi);
00435
00436   /* NOTE : This function should not be modified, when the callback is needed,
00437             the HAL_QSPI_MspInit can be implemented in the user file
00438    */
00439 }
00440
00441 /**
00442   * @brief DeInitialize the QSPI MSP.
00443   * @param hqspi : QSPI handle
00444   * @retval None
00445   */
00446 __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
00447 {
00448   /* Prevent unused argument(s) compilation warning */
00449   UNUSED(hqspi);
00450
00451   /* NOTE : This function should not be modified, when the callback is needed,
00452             the HAL_QSPI_MspDeInit can be implemented in the user file
00453    */
00454 }
00455
00456 /**
00457   * @}
00458   */
00459
00460 /** @defgroup QSPI_Exported_Functions_Group2 Input and Output operation functions
00461   *  @brief QSPI Transmit/Receive functions
00462   *
00463 @verbatim
00464  ===============================================================================
00465                       ##### IO operation functions #####
00466  ===============================================================================
00467     [..]
00468     This subsection provides a set of functions allowing to :
00469       (+) Handle the interrupts.
00470       (+) Handle the command sequence.
00471       (+) Transmit data in blocking, interrupt or DMA mode.
00472       (+) Receive data in blocking, interrupt or DMA mode.
00473       (+) Manage the auto-polling functional mode.
00474       (+) Manage the memory-mapped functional mode.
00475
00476 @endverbatim
00477   * @{
00478   */
00479
00480 /**
00481   * @brief Handle QSPI interrupt request.
00482   * @param hqspi : QSPI handle
00483   * @retval None
00484   */
00485 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
00486 {
00487   __IO uint32_t *data_reg;
00488   uint32_t flag = READ_REG(hqspi->Instance->SR);
00489   uint32_t itsource = READ_REG(hqspi->Instance->CR);
00490
00491   /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/
00492   if(((flag & QSPI_FLAG_FT) != 0U) && ((itsource & QSPI_IT_FT) != 0U))
00493   {
00494     data_reg = &hqspi->Instance->DR;
00495
00496     if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
00497     {
00498       /* Transmission process */
00499       while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET)
00500       {
00501         if (hqspi->TxXferCount > 0U)
00502         {
00503           /* Fill the FIFO until the threshold is reached */
00504           *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr;
00505           hqspi->pTxBuffPtr++;
00506           hqspi->TxXferCount--;
00507         }
00508         else
00509         {
00510           /* No more data available for the transfer */
00511           /* Disable the QSPI FIFO Threshold Interrupt */
00512           __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
00513           break;
00514         }
00515       }
00516     }
00517     else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
00518     {
00519       /* Receiving Process */
00520       while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET)
00521       {
00522         if (hqspi->RxXferCount > 0U)
00523         {
00524           /* Read the FIFO until the threshold is reached */
00525           *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
00526           hqspi->pRxBuffPtr++;
00527           hqspi->RxXferCount--;
00528         }
00529         else
00530         {
00531           /* All data have been received for the transfer */
00532           /* Disable the QSPI FIFO Threshold Interrupt */
00533           __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
00534           break;
00535         }
00536       }
00537     }
00538     else
00539     {
00540       /* Nothing to do */
00541     }
00542
00543     /* FIFO Threshold callback */
00544 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00545     hqspi->FifoThresholdCallback(hqspi);
00546 #else
00547     HAL_QSPI_FifoThresholdCallback(hqspi);
00548 #endif
00549   }
00550
00551   /* QSPI Transfer Complete interrupt occurred -------------------------------*/
00552   else if(((flag & QSPI_FLAG_TC) != 0U) && ((itsource & QSPI_IT_TC) != 0U))
00553   {
00554     /* Clear interrupt */
00555     WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC);
00556
00557     /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
00558     __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
00559
00560     /* Transfer complete callback */
00561     if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
00562     {
00563       if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
00564       {
00565         /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
00566         CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
00567
00568         /* Disable the DMA channel */
00569         __HAL_DMA_DISABLE(hqspi->hdma);
00570       }
00571
00572
00573       /* Change state of QSPI */
00574       hqspi->State = HAL_QSPI_STATE_READY;
00575
00576       /* TX Complete callback */
00577 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00578       hqspi->TxCpltCallback(hqspi);
00579 #else
00580       HAL_QSPI_TxCpltCallback(hqspi);
00581 #endif
00582     }
00583     else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
00584     {
00585       if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
00586       {
00587         /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
00588         CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
00589
00590         /* Disable the DMA channel */
00591         __HAL_DMA_DISABLE(hqspi->hdma);
00592       }
00593       else
00594       {
00595         data_reg = &hqspi->Instance->DR;
00596         while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0U)
00597         {
00598           if (hqspi->RxXferCount > 0U)
00599           {
00600             /* Read the last data received in the FIFO until it is empty */
00601             *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
00602             hqspi->pRxBuffPtr++;
00603             hqspi->RxXferCount--;
00604           }
00605           else
00606           {
00607             /* All data have been received for the transfer */
00608             break;
00609           }
00610         }
00611       }
00612
00613
00614       /* Change state of QSPI */
00615       hqspi->State = HAL_QSPI_STATE_READY;
00616
00617       /* RX Complete callback */
00618 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00619       hqspi->RxCpltCallback(hqspi);
00620 #else
00621       HAL_QSPI_RxCpltCallback(hqspi);
00622 #endif
00623     }
00624     else if(hqspi->State == HAL_QSPI_STATE_BUSY)
00625     {
00626       /* Change state of QSPI */
00627       hqspi->State = HAL_QSPI_STATE_READY;
00628
00629       /* Command Complete callback */
00630 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00631       hqspi->CmdCpltCallback(hqspi);
00632 #else
00633       HAL_QSPI_CmdCpltCallback(hqspi);
00634 #endif
00635     }
00636     else if(hqspi->State == HAL_QSPI_STATE_ABORT)
00637     {
00638       /* Reset functional mode configuration to indirect write mode by default */
00639       CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE);
00640
00641       /* Change state of QSPI */
00642       hqspi->State = HAL_QSPI_STATE_READY;
00643
00644       if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE)
00645       {
00646         /* Abort called by the user */
00647
00648         /* Abort Complete callback */
00649 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00650         hqspi->AbortCpltCallback(hqspi);
00651 #else
00652         HAL_QSPI_AbortCpltCallback(hqspi);
00653 #endif
00654       }
00655       else
00656       {
00657         /* Abort due to an error (eg :  DMA error) */
00658
00659         /* Error callback */
00660 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00661         hqspi->ErrorCallback(hqspi);
00662 #else
00663         HAL_QSPI_ErrorCallback(hqspi);
00664 #endif
00665       }
00666     }
00667     else
00668     {
00669      /* Nothing to do */
00670     }
00671   }
00672
00673   /* QSPI Status Match interrupt occurred ------------------------------------*/
00674   else if(((flag & QSPI_FLAG_SM) != 0U) && ((itsource & QSPI_IT_SM) != 0U))
00675   {
00676     /* Clear interrupt */
00677     WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM);
00678
00679     /* Check if the automatic poll mode stop is activated */
00680     if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0U)
00681     {
00682       /* Disable the QSPI Transfer Error and Status Match Interrupts */
00683       __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
00684
00685       /* Change state of QSPI */
00686       hqspi->State = HAL_QSPI_STATE_READY;
00687     }
00688
00689     /* Status match callback */
00690 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00691     hqspi->StatusMatchCallback(hqspi);
00692 #else
00693     HAL_QSPI_StatusMatchCallback(hqspi);
00694 #endif
00695   }
00696
00697   /* QSPI Transfer Error interrupt occurred ----------------------------------*/
00698   else if(((flag & QSPI_FLAG_TE) != 0U) && ((itsource & QSPI_IT_TE) != 0U))
00699   {
00700     /* Clear interrupt */
00701     WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE);
00702
00703     /* Disable all the QSPI Interrupts */
00704     __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
00705
00706     /* Set error code */
00707     hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;
00708
00709     if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
00710     {
00711       /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
00712       CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
00713
00714       /* Disable the DMA channel */
00715       hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
00716       if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK)
00717       {
00718         /* Set error code to DMA */
00719         hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
00720
00721         /* Change state of QSPI */
00722         hqspi->State = HAL_QSPI_STATE_READY;
00723
00724         /* Error callback */
00725 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00726         hqspi->ErrorCallback(hqspi);
00727 #else
00728         HAL_QSPI_ErrorCallback(hqspi);
00729 #endif
00730       }
00731     }
00732     else
00733     {
00734       /* Change state of QSPI */
00735       hqspi->State = HAL_QSPI_STATE_READY;
00736
00737       /* Error callback */
00738 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00739       hqspi->ErrorCallback(hqspi);
00740 #else
00741       HAL_QSPI_ErrorCallback(hqspi);
00742 #endif
00743     }
00744   }
00745
00746   /* QSPI Timeout interrupt occurred -----------------------------------------*/
00747   else if(((flag & QSPI_FLAG_TO) != 0U) && ((itsource & QSPI_IT_TO) != 0U))
00748   {
00749     /* Clear interrupt */
00750     WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);
00751
00752     /* Timeout callback */
00753 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00754     hqspi->TimeOutCallback(hqspi);
00755 #else
00756     HAL_QSPI_TimeOutCallback(hqspi);
00757 #endif
00758   }
00759
00760    else
00761   {
00762    /* Nothing to do */
00763   }
00764 }
00765
00766 /**
00767   * @brief Set the command configuration.
00768   * @param hqspi : QSPI handle
00769   * @param cmd : structure that contains the command configuration information
00770   * @param Timeout : Timeout duration
00771   * @note   This function is used only in Indirect Read or Write Modes
00772   * @retval HAL status
00773   */
00774 HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
00775 {
00776   HAL_StatusTypeDef status;
00777   uint32_t tickstart = HAL_GetTick();
00778
00779   /* Check the parameters */
00780   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
00781   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
00782   {
00783     assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
00784   }
00785
00786   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
00787   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
00788   {
00789     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
00790   }
00791
00792   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
00793   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
00794   {
00795     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
00796   }
00797
00798   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
00799   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
00800
00801   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
00802   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
00803
00804   /* Process locked */
00805   __HAL_LOCK(hqspi);
00806
00807   if(hqspi->State == HAL_QSPI_STATE_READY)
00808   {
00809     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00810
00811     /* Update QSPI state */
00812     hqspi->State = HAL_QSPI_STATE_BUSY;
00813
00814     /* Wait till BUSY flag reset */
00815     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
00816
00817     if (status == HAL_OK)
00818     {
00819       /* Call the configuration function */
00820       QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
00821
00822       if (cmd->DataMode == QSPI_DATA_NONE)
00823       {
00824         /* When there is no data phase, the transfer start as soon as the configuration is done
00825         so wait until TC flag is set to go back in idle state */
00826         status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
00827
00828         if (status == HAL_OK)
00829         {
00830           __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
00831
00832           /* Update QSPI state */
00833           hqspi->State = HAL_QSPI_STATE_READY;
00834         }
00835       }
00836       else
00837       {
00838         /* Update QSPI state */
00839         hqspi->State = HAL_QSPI_STATE_READY;
00840       }
00841     }
00842   }
00843   else
00844   {
00845     status = HAL_BUSY;
00846   }
00847
00848   /* Process unlocked */
00849   __HAL_UNLOCK(hqspi);
00850
00851   /* Return function status */
00852   return status;
00853 }
00854
00855 /**
00856   * @brief Set the command configuration in interrupt mode.
00857   * @param hqspi : QSPI handle
00858   * @param cmd : structure that contains the command configuration information
00859   * @note   This function is used only in Indirect Read or Write Modes
00860   * @retval HAL status
00861   */
00862 HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
00863 {
00864   HAL_StatusTypeDef status;
00865   uint32_t tickstart = HAL_GetTick();
00866
00867   /* Check the parameters */
00868   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
00869   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
00870   {
00871     assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
00872   }
00873
00874   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
00875   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
00876   {
00877     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
00878   }
00879
00880   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
00881   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
00882   {
00883     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
00884   }
00885
00886   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
00887   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
00888
00889   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
00890   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
00891
00892   /* Process locked */
00893   __HAL_LOCK(hqspi);
00894
00895   if(hqspi->State == HAL_QSPI_STATE_READY)
00896   {
00897     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00898
00899     /* Update QSPI state */
00900     hqspi->State = HAL_QSPI_STATE_BUSY;
00901
00902     /* Wait till BUSY flag reset */
00903     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
00904
00905     if (status == HAL_OK)
00906     {
00907       if (cmd->DataMode == QSPI_DATA_NONE)
00908       {
00909         /* Clear interrupt */
00910         __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
00911       }
00912
00913       /* Call the configuration function */
00914       QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
00915
00916       if (cmd->DataMode == QSPI_DATA_NONE)
00917       {
00918         /* When there is no data phase, the transfer start as soon as the configuration is done
00919         so activate TC and TE interrupts */
00920         /* Process unlocked */
00921         __HAL_UNLOCK(hqspi);
00922
00923         /* Enable the QSPI Transfer Error Interrupt */
00924         __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC);
00925       }
00926       else
00927       {
00928         /* Update QSPI state */
00929         hqspi->State = HAL_QSPI_STATE_READY;
00930
00931         /* Process unlocked */
00932         __HAL_UNLOCK(hqspi);
00933       }
00934     }
00935     else
00936     {
00937       /* Process unlocked */
00938       __HAL_UNLOCK(hqspi);
00939     }
00940   }
00941   else
00942   {
00943     status = HAL_BUSY;
00944
00945     /* Process unlocked */
00946     __HAL_UNLOCK(hqspi);
00947   }
00948
00949   /* Return function status */
00950   return status;
00951 }
00952
00953 /**
00954   * @brief Transmit an amount of data in blocking mode.
00955   * @param hqspi : QSPI handle
00956   * @param pData : pointer to data buffer
00957   * @param Timeout : Timeout duration
00958   * @note   This function is used only in Indirect Write Mode
00959   * @retval HAL status
00960   */
00961 HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
00962 {
00963   HAL_StatusTypeDef status = HAL_OK;
00964   uint32_t tickstart = HAL_GetTick();
00965   __IO uint32_t *data_reg = &hqspi->Instance->DR;
00966
00967   /* Process locked */
00968   __HAL_LOCK(hqspi);
00969
00970   if(hqspi->State == HAL_QSPI_STATE_READY)
00971   {
00972     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
00973
00974     if(pData != NULL )
00975     {
00976       /* Update state */
00977       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
00978
00979       /* Configure counters and size of the handle */
00980       hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
00981       hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
00982       hqspi->pTxBuffPtr = pData;
00983
00984       /* Configure QSPI: CCR register with functional as indirect write */
00985       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
00986
00987       while(hqspi->TxXferCount > 0U)
00988       {
00989         /* Wait until FT flag is set to send data */
00990         status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout);
00991
00992         if (status != HAL_OK)
00993         {
00994           break;
00995         }
00996
00997         *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr;
00998         hqspi->pTxBuffPtr++;
00999         hqspi->TxXferCount--;
01000       }
01001
01002       if (status == HAL_OK)
01003       {
01004         /* Wait until TC flag is set to go back in idle state */
01005         status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
01006
01007         if (status == HAL_OK)
01008         {
01009           /* Clear Transfer Complete bit */
01010           __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
01011
01012         }
01013       }
01014
01015       /* Update QSPI state */
01016       hqspi->State = HAL_QSPI_STATE_READY;
01017     }
01018     else
01019     {
01020       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
01021       status = HAL_ERROR;
01022     }
01023   }
01024   else
01025   {
01026     status = HAL_BUSY;
01027   }
01028
01029   /* Process unlocked */
01030   __HAL_UNLOCK(hqspi);
01031
01032   return status;
01033 }
01034
01035
01036 /**
01037   * @brief Receive an amount of data in blocking mode.
01038   * @param hqspi : QSPI handle
01039   * @param pData : pointer to data buffer
01040   * @param Timeout : Timeout duration
01041   * @note   This function is used only in Indirect Read Mode
01042   * @retval HAL status
01043   */
01044 HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
01045 {
01046   HAL_StatusTypeDef status = HAL_OK;
01047   uint32_t tickstart = HAL_GetTick();
01048   uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
01049   __IO uint32_t *data_reg = &hqspi->Instance->DR;
01050
01051   /* Process locked */
01052   __HAL_LOCK(hqspi);
01053
01054   if(hqspi->State == HAL_QSPI_STATE_READY)
01055   {
01056     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01057
01058     if(pData != NULL )
01059     {
01060       /* Update state */
01061       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
01062
01063       /* Configure counters and size of the handle */
01064       hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
01065       hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
01066       hqspi->pRxBuffPtr = pData;
01067
01068       /* Configure QSPI: CCR register with functional as indirect read */
01069       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
01070
01071       /* Start the transfer by re-writing the address in AR register */
01072       WRITE_REG(hqspi->Instance->AR, addr_reg);
01073
01074       while(hqspi->RxXferCount > 0U)
01075       {
01076         /* Wait until FT or TC flag is set to read received data */
01077         status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, Timeout);
01078
01079         if  (status != HAL_OK)
01080         {
01081           break;
01082         }
01083
01084         *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
01085         hqspi->pRxBuffPtr++;
01086         hqspi->RxXferCount--;
01087       }
01088
01089       if (status == HAL_OK)
01090       {
01091         /* Wait until TC flag is set to go back in idle state */
01092         status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
01093
01094         if  (status == HAL_OK)
01095         {
01096           /* Clear Transfer Complete bit */
01097           __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
01098
01099         }
01100       }
01101
01102       /* Update QSPI state */
01103       hqspi->State = HAL_QSPI_STATE_READY;
01104     }
01105     else
01106     {
01107       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
01108       status = HAL_ERROR;
01109     }
01110   }
01111   else
01112   {
01113     status = HAL_BUSY;
01114   }
01115
01116   /* Process unlocked */
01117   __HAL_UNLOCK(hqspi);
01118
01119   return status;
01120 }
01121
01122 /**
01123   * @brief  Send an amount of data in non-blocking mode with interrupt.
01124   * @param  hqspi : QSPI handle
01125   * @param  pData : pointer to data buffer
01126   * @note   This function is used only in Indirect Write Mode
01127   * @retval HAL status
01128   */
01129 HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
01130 {
01131   HAL_StatusTypeDef status = HAL_OK;
01132
01133   /* Process locked */
01134   __HAL_LOCK(hqspi);
01135
01136   if(hqspi->State == HAL_QSPI_STATE_READY)
01137   {
01138     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01139
01140     if(pData != NULL )
01141     {
01142       /* Update state */
01143       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
01144
01145       /* Configure counters and size of the handle */
01146       hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
01147       hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
01148       hqspi->pTxBuffPtr = pData;
01149
01150       /* Clear interrupt */
01151       __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
01152
01153       /* Configure QSPI: CCR register with functional as indirect write */
01154       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
01155
01156       /* Process unlocked */
01157       __HAL_UNLOCK(hqspi);
01158
01159       /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
01160       __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
01161     }
01162     else
01163     {
01164       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
01165       status = HAL_ERROR;
01166
01167       /* Process unlocked */
01168       __HAL_UNLOCK(hqspi);
01169     }
01170   }
01171   else
01172   {
01173     status = HAL_BUSY;
01174
01175     /* Process unlocked */
01176     __HAL_UNLOCK(hqspi);
01177   }
01178
01179   return status;
01180 }
01181
01182 /**
01183   * @brief  Receive an amount of data in non-blocking mode with interrupt.
01184   * @param  hqspi : QSPI handle
01185   * @param  pData : pointer to data buffer
01186   * @note   This function is used only in Indirect Read Mode
01187   * @retval HAL status
01188   */
01189 HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
01190 {
01191   HAL_StatusTypeDef status = HAL_OK;
01192   uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
01193
01194   /* Process locked */
01195   __HAL_LOCK(hqspi);
01196
01197   if(hqspi->State == HAL_QSPI_STATE_READY)
01198   {
01199     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01200
01201     if(pData != NULL )
01202     {
01203       /* Update state */
01204       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
01205
01206       /* Configure counters and size of the handle */
01207       hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
01208       hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
01209       hqspi->pRxBuffPtr = pData;
01210
01211       /* Clear interrupt */
01212       __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
01213
01214       /* Configure QSPI: CCR register with functional as indirect read */
01215       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
01216
01217       /* Start the transfer by re-writing the address in AR register */
01218       WRITE_REG(hqspi->Instance->AR, addr_reg);
01219
01220       /* Process unlocked */
01221       __HAL_UNLOCK(hqspi);
01222
01223       /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
01224       __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
01225     }
01226     else
01227     {
01228       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
01229       status = HAL_ERROR;
01230
01231       /* Process unlocked */
01232       __HAL_UNLOCK(hqspi);
01233     }
01234   }
01235   else
01236   {
01237     status = HAL_BUSY;
01238
01239     /* Process unlocked */
01240     __HAL_UNLOCK(hqspi);
01241   }
01242
01243   return status;
01244 }
01245
01246 /**
01247   * @brief  Send an amount of data in non-blocking mode with DMA.
01248   * @param  hqspi : QSPI handle
01249   * @param  pData : pointer to data buffer
01250   * @note   This function is used only in Indirect Write Mode
01251   * @note   If DMA peripheral access is configured as halfword, the number
01252   *         of data and the fifo threshold should be aligned on halfword
01253   * @note   If DMA peripheral access is configured as word, the number
01254   *         of data and the fifo threshold should be aligned on word
01255   * @retval HAL status
01256   */
01257 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
01258 {
01259   HAL_StatusTypeDef status = HAL_OK;
01260   uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);
01261
01262   /* Process locked */
01263   __HAL_LOCK(hqspi);
01264
01265   if(hqspi->State == HAL_QSPI_STATE_READY)
01266   {
01267     /* Clear the error code */
01268     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01269
01270     if(pData != NULL )
01271     {
01272       /* Configure counters of the handle */
01273       if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
01274       {
01275         hqspi->TxXferCount = data_size;
01276       }
01277       else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
01278       {
01279         if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U))
01280         {
01281           /* The number of data or the fifo threshold is not aligned on halfword
01282           => no transfer possible with DMA peripheral access configured as halfword */
01283           hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
01284           status = HAL_ERROR;
01285
01286           /* Process unlocked */
01287           __HAL_UNLOCK(hqspi);
01288         }
01289         else
01290         {
01291           hqspi->TxXferCount = (data_size >> 1U);
01292         }
01293       }
01294       else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
01295       {
01296         if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U))
01297         {
01298           /* The number of data or the fifo threshold is not aligned on word
01299           => no transfer possible with DMA peripheral access configured as word */
01300           hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
01301           status = HAL_ERROR;
01302
01303           /* Process unlocked */
01304           __HAL_UNLOCK(hqspi);
01305         }
01306         else
01307         {
01308           hqspi->TxXferCount = (data_size >> 2U);
01309         }
01310       }
01311       else
01312       {
01313         /* Nothing to do */
01314       }
01315
01316       if (status == HAL_OK)
01317       {
01318         /* Update state */
01319         hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
01320
01321         /* Clear interrupt */
01322         __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
01323
01324         /* Configure size and pointer of the handle */
01325         hqspi->TxXferSize = hqspi->TxXferCount;
01326         hqspi->pTxBuffPtr = pData;
01327
01328         /* Configure QSPI: CCR register with functional mode as indirect write */
01329         MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
01330
01331         /* Set the QSPI DMA transfer complete callback */
01332         hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;
01333
01334         /* Set the QSPI DMA Half transfer complete callback */
01335         hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;
01336
01337         /* Set the DMA error callback */
01338         hqspi->hdma->XferErrorCallback = QSPI_DMAError;
01339
01340         /* Clear the DMA abort callback */
01341         hqspi->hdma->XferAbortCallback = NULL;
01342
01343         /* Configure the direction of the DMA */
01344         hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
01345         MODIFY_REG(hqspi->hdma->Instance->CCR, DMA_CCR_DIR, hqspi->hdma->Init.Direction);
01346
01347         /* Enable the QSPI transmit DMA Channel */
01348         if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize) == HAL_OK)
01349         {
01350           /* Process unlocked */
01351           __HAL_UNLOCK(hqspi);
01352
01353           /* Enable the QSPI transfer error Interrupt */
01354           __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
01355
01356           /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
01357           SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
01358         }
01359         else
01360         {
01361           status = HAL_ERROR;
01362           hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
01363           hqspi->State = HAL_QSPI_STATE_READY;
01364
01365           /* Process unlocked */
01366           __HAL_UNLOCK(hqspi);
01367         }
01368      }
01369     }
01370     else
01371     {
01372       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
01373       status = HAL_ERROR;
01374
01375       /* Process unlocked */
01376       __HAL_UNLOCK(hqspi);
01377     }
01378   }
01379   else
01380   {
01381     status = HAL_BUSY;
01382
01383     /* Process unlocked */
01384     __HAL_UNLOCK(hqspi);
01385   }
01386
01387   return status;
01388 }
01389
01390 /**
01391   * @brief  Receive an amount of data in non-blocking mode with DMA.
01392   * @param  hqspi : QSPI handle
01393   * @param  pData : pointer to data buffer.
01394   * @note   This function is used only in Indirect Read Mode
01395   * @note   If DMA peripheral access is configured as halfword, the number
01396   *         of data and the fifo threshold should be aligned on halfword
01397   * @note   If DMA peripheral access is configured as word, the number
01398   *         of data and the fifo threshold should be aligned on word
01399   * @retval HAL status
01400   */
01401 HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
01402 {
01403   HAL_StatusTypeDef status = HAL_OK;
01404   uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
01405   uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);
01406
01407   /* Process locked */
01408   __HAL_LOCK(hqspi);
01409
01410   if(hqspi->State == HAL_QSPI_STATE_READY)
01411   {
01412     /* Clear the error code */
01413     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01414
01415     if(pData != NULL )
01416     {
01417       /* Configure counters of the handle */
01418       if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
01419       {
01420         hqspi->RxXferCount = data_size;
01421       }
01422       else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
01423       {
01424         if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U))
01425         {
01426           /* The number of data or the fifo threshold is not aligned on halfword
01427              => no transfer possible with DMA peripheral access configured as halfword */
01428           hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
01429           status = HAL_ERROR;
01430
01431           /* Process unlocked */
01432           __HAL_UNLOCK(hqspi);
01433         }
01434         else
01435         {
01436           hqspi->RxXferCount = (data_size >> 1U);
01437         }
01438       }
01439       else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
01440       {
01441         if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U))
01442         {
01443           /* The number of data or the fifo threshold is not aligned on word
01444              => no transfer possible with DMA peripheral access configured as word */
01445           hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
01446           status = HAL_ERROR;
01447
01448           /* Process unlocked */
01449           __HAL_UNLOCK(hqspi);
01450         }
01451         else
01452         {
01453           hqspi->RxXferCount = (data_size >> 2U);
01454         }
01455       }
01456       else
01457       {
01458         /* Nothing to do */
01459       }
01460
01461       if (status == HAL_OK)
01462       {
01463         /* Update state */
01464         hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
01465
01466         /* Clear interrupt */
01467         __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
01468
01469         /* Configure size and pointer of the handle */
01470         hqspi->RxXferSize = hqspi->RxXferCount;
01471         hqspi->pRxBuffPtr = pData;
01472
01473         /* Set the QSPI DMA transfer complete callback */
01474         hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;
01475
01476         /* Set the QSPI DMA Half transfer complete callback */
01477         hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;
01478
01479         /* Set the DMA error callback */
01480         hqspi->hdma->XferErrorCallback = QSPI_DMAError;
01481
01482         /* Clear the DMA abort callback */
01483         hqspi->hdma->XferAbortCallback = NULL;
01484
01485         /* Configure the direction of the DMA */
01486         hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
01487         MODIFY_REG(hqspi->hdma->Instance->CCR, DMA_CCR_DIR, hqspi->hdma->Init.Direction);
01488
01489         /* Enable the DMA Channel */
01490         if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize) == HAL_OK)
01491         {
01492           /* Configure QSPI: CCR register with functional as indirect read */
01493           MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
01494
01495           /* Start the transfer by re-writing the address in AR register */
01496           WRITE_REG(hqspi->Instance->AR, addr_reg);
01497
01498           /* Process unlocked */
01499           __HAL_UNLOCK(hqspi);
01500
01501           /* Enable the QSPI transfer error Interrupt */
01502           __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
01503
01504           /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
01505           SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
01506         }
01507         else
01508         {
01509           status = HAL_ERROR;
01510           hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
01511           hqspi->State = HAL_QSPI_STATE_READY;
01512
01513           /* Process unlocked */
01514           __HAL_UNLOCK(hqspi);
01515         }
01516       }
01517     }
01518     else
01519     {
01520       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
01521       status = HAL_ERROR;
01522
01523       /* Process unlocked */
01524       __HAL_UNLOCK(hqspi);
01525     }
01526   }
01527   else
01528   {
01529     status = HAL_BUSY;
01530
01531     /* Process unlocked */
01532     __HAL_UNLOCK(hqspi);
01533   }
01534
01535   return status;
01536 }
01537
01538 /**
01539   * @brief  Configure the QSPI Automatic Polling Mode in blocking mode.
01540   * @param  hqspi : QSPI handle
01541   * @param  cmd : structure that contains the command configuration information.
01542   * @param  cfg : structure that contains the polling configuration information.
01543   * @param  Timeout : Timeout duration
01544   * @note   This function is used only in Automatic Polling Mode
01545   * @retval HAL status
01546   */
01547 HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
01548 {
01549   HAL_StatusTypeDef status;
01550   uint32_t tickstart = HAL_GetTick();
01551
01552   /* Check the parameters */
01553   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
01554   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
01555   {
01556     assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
01557   }
01558
01559   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
01560   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
01561   {
01562     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
01563   }
01564
01565   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
01566   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
01567   {
01568     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
01569   }
01570
01571   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
01572   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
01573
01574   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
01575   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
01576
01577   assert_param(IS_QSPI_INTERVAL(cfg->Interval));
01578   assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
01579   assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
01580
01581   /* Process locked */
01582   __HAL_LOCK(hqspi);
01583
01584   if(hqspi->State == HAL_QSPI_STATE_READY)
01585   {
01586     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01587
01588     /* Update state */
01589     hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
01590
01591     /* Wait till BUSY flag reset */
01592     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
01593
01594     if (status == HAL_OK)
01595     {
01596       /* Configure QSPI: PSMAR register with the status match value */
01597       WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
01598
01599       /* Configure QSPI: PSMKR register with the status mask value */
01600       WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
01601
01602       /* Configure QSPI: PIR register with the interval value */
01603       WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
01604
01605       /* Configure QSPI: CR register with Match mode and Automatic stop enabled
01606       (otherwise there will be an infinite loop in blocking mode) */
01607       MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
01608                (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE));
01609
01610       /* Call the configuration function */
01611       cmd->NbData = cfg->StatusBytesSize;
01612       QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
01613
01614       /* Wait until SM flag is set to go back in idle state */
01615       status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout);
01616
01617       if (status == HAL_OK)
01618       {
01619         __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
01620
01621         /* Update state */
01622         hqspi->State = HAL_QSPI_STATE_READY;
01623       }
01624     }
01625   }
01626   else
01627   {
01628     status = HAL_BUSY;
01629   }
01630
01631   /* Process unlocked */
01632   __HAL_UNLOCK(hqspi);
01633
01634   /* Return function status */
01635   return status;
01636 }
01637
01638 /**
01639   * @brief  Configure the QSPI Automatic Polling Mode in non-blocking mode.
01640   * @param  hqspi : QSPI handle
01641   * @param  cmd : structure that contains the command configuration information.
01642   * @param  cfg : structure that contains the polling configuration information.
01643   * @note   This function is used only in Automatic Polling Mode
01644   * @retval HAL status
01645   */
01646 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
01647 {
01648   HAL_StatusTypeDef status;
01649   uint32_t tickstart = HAL_GetTick();
01650
01651   /* Check the parameters */
01652   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
01653   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
01654   {
01655     assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
01656   }
01657
01658   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
01659   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
01660   {
01661     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
01662   }
01663
01664   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
01665   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
01666   {
01667     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
01668   }
01669
01670   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
01671   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
01672
01673   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
01674   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
01675
01676   assert_param(IS_QSPI_INTERVAL(cfg->Interval));
01677   assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
01678   assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
01679   assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
01680
01681   /* Process locked */
01682   __HAL_LOCK(hqspi);
01683
01684   if(hqspi->State == HAL_QSPI_STATE_READY)
01685   {
01686     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01687
01688     /* Update state */
01689     hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
01690
01691     /* Wait till BUSY flag reset */
01692     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
01693
01694     if (status == HAL_OK)
01695     {
01696       /* Configure QSPI: PSMAR register with the status match value */
01697       WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
01698
01699       /* Configure QSPI: PSMKR register with the status mask value */
01700       WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
01701
01702       /* Configure QSPI: PIR register with the interval value */
01703       WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
01704
01705       /* Configure QSPI: CR register with Match mode and Automatic stop mode */
01706       MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
01707                (cfg->MatchMode | cfg->AutomaticStop));
01708
01709       /* Clear interrupt */
01710       __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM);
01711
01712       /* Call the configuration function */
01713       cmd->NbData = cfg->StatusBytesSize;
01714       QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
01715
01716       /* Process unlocked */
01717       __HAL_UNLOCK(hqspi);
01718
01719       /* Enable the QSPI Transfer Error and status match Interrupt */
01720       __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
01721
01722     }
01723     else
01724     {
01725       /* Process unlocked */
01726       __HAL_UNLOCK(hqspi);
01727     }
01728   }
01729   else
01730   {
01731     status = HAL_BUSY;
01732
01733     /* Process unlocked */
01734     __HAL_UNLOCK(hqspi);
01735   }
01736
01737   /* Return function status */
01738   return status;
01739 }
01740
01741 /**
01742   * @brief  Configure the Memory Mapped mode.
01743   * @param  hqspi : QSPI handle
01744   * @param  cmd : structure that contains the command configuration information.
01745   * @param  cfg : structure that contains the memory mapped configuration information.
01746   * @note   This function is used only in Memory mapped Mode
01747   * @retval HAL status
01748   */
01749 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
01750 {
01751   HAL_StatusTypeDef status;
01752   uint32_t tickstart = HAL_GetTick();
01753
01754   /* Check the parameters */
01755   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
01756   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
01757   {
01758   assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
01759   }
01760
01761   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
01762   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
01763   {
01764     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
01765   }
01766
01767   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
01768   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
01769   {
01770     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
01771   }
01772
01773   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
01774   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
01775
01776   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
01777   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
01778
01779   assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
01780
01781   /* Process locked */
01782   __HAL_LOCK(hqspi);
01783
01784   if(hqspi->State == HAL_QSPI_STATE_READY)
01785   {
01786     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
01787
01788     /* Update state */
01789     hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;
01790
01791     /* Wait till BUSY flag reset */
01792     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
01793
01794     if (status == HAL_OK)
01795     {
01796       /* Configure QSPI: CR register with timeout counter enable */
01797     MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
01798
01799     if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
01800       {
01801         assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
01802
01803         /* Configure QSPI: LPTR register with the low-power timeout value */
01804         WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
01805
01806         /* Clear interrupt */
01807         __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
01808
01809         /* Enable the QSPI TimeOut Interrupt */
01810         __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
01811       }
01812
01813       /* Call the configuration function */
01814       QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
01815     }
01816   }
01817   else
01818   {
01819     status = HAL_BUSY;
01820   }
01821
01822   /* Process unlocked */
01823   __HAL_UNLOCK(hqspi);
01824
01825   /* Return function status */
01826   return status;
01827 }
01828
01829 /**
01830   * @brief  Transfer Error callback.
01831   * @param  hqspi : QSPI handle
01832   * @retval None
01833   */
01834 __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
01835 {
01836   /* Prevent unused argument(s) compilation warning */
01837   UNUSED(hqspi);
01838
01839   /* NOTE : This function should not be modified, when the callback is needed,
01840             the HAL_QSPI_ErrorCallback could be implemented in the user file
01841    */
01842 }
01843
01844 /**
01845   * @brief  Abort completed callback.
01846   * @param  hqspi : QSPI handle
01847   * @retval None
01848   */
01849 __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
01850 {
01851   /* Prevent unused argument(s) compilation warning */
01852   UNUSED(hqspi);
01853
01854   /* NOTE: This function should not be modified, when the callback is needed,
01855            the HAL_QSPI_AbortCpltCallback could be implemented in the user file
01856    */
01857 }
01858
01859 /**
01860   * @brief  Command completed callback.
01861   * @param  hqspi : QSPI handle
01862   * @retval None
01863   */
01864 __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
01865 {
01866   /* Prevent unused argument(s) compilation warning */
01867   UNUSED(hqspi);
01868
01869   /* NOTE: This function should not be modified, when the callback is needed,
01870            the HAL_QSPI_CmdCpltCallback could be implemented in the user file
01871    */
01872 }
01873
01874 /**
01875   * @brief  Rx Transfer completed callback.
01876   * @param  hqspi : QSPI handle
01877   * @retval None
01878   */
01879 __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
01880 {
01881   /* Prevent unused argument(s) compilation warning */
01882   UNUSED(hqspi);
01883
01884   /* NOTE: This function should not be modified, when the callback is needed,
01885            the HAL_QSPI_RxCpltCallback could be implemented in the user file
01886    */
01887 }
01888
01889 /**
01890   * @brief  Tx Transfer completed callback.
01891   * @param  hqspi : QSPI handle
01892   * @retval None
01893   */
01894 __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
01895 {
01896   /* Prevent unused argument(s) compilation warning */
01897   UNUSED(hqspi);
01898
01899   /* NOTE: This function should not be modified, when the callback is needed,
01900            the HAL_QSPI_TxCpltCallback could be implemented in the user file
01901    */
01902 }
01903
01904 /**
01905   * @brief  Rx Half Transfer completed callback.
01906   * @param  hqspi : QSPI handle
01907   * @retval None
01908   */
01909 __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
01910 {
01911   /* Prevent unused argument(s) compilation warning */
01912   UNUSED(hqspi);
01913
01914   /* NOTE: This function should not be modified, when the callback is needed,
01915            the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file
01916    */
01917 }
01918
01919 /**
01920   * @brief  Tx Half Transfer completed callback.
01921   * @param  hqspi : QSPI handle
01922   * @retval None
01923   */
01924 __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
01925 {
01926   /* Prevent unused argument(s) compilation warning */
01927   UNUSED(hqspi);
01928
01929   /* NOTE: This function should not be modified, when the callback is needed,
01930            the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file
01931    */
01932 }
01933
01934 /**
01935   * @brief  FIFO Threshold callback.
01936   * @param  hqspi : QSPI handle
01937   * @retval None
01938   */
01939 __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
01940 {
01941   /* Prevent unused argument(s) compilation warning */
01942   UNUSED(hqspi);
01943
01944   /* NOTE : This function should not be modified, when the callback is needed,
01945             the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
01946    */
01947 }
01948
01949 /**
01950   * @brief  Status Match callback.
01951   * @param  hqspi : QSPI handle
01952   * @retval None
01953   */
01954 __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
01955 {
01956   /* Prevent unused argument(s) compilation warning */
01957   UNUSED(hqspi);
01958
01959   /* NOTE : This function should not be modified, when the callback is needed,
01960             the HAL_QSPI_StatusMatchCallback could be implemented in the user file
01961    */
01962 }
01963
01964 /**
01965   * @brief  Timeout callback.
01966   * @param  hqspi : QSPI handle
01967   * @retval None
01968   */
01969 __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
01970 {
01971   /* Prevent unused argument(s) compilation warning */
01972   UNUSED(hqspi);
01973
01974   /* NOTE : This function should not be modified, when the callback is needed,
01975             the HAL_QSPI_TimeOutCallback could be implemented in the user file
01976    */
01977 }
01978 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
01979 /**
01980   * @brief  Register a User QSPI Callback
01981   *         To be used instead of the weak (surcharged) predefined callback
01982   * @param hqspi : QSPI handle
01983   * @param CallbackId : ID of the callback to be registered
01984   *        This parameter can be one of the following values:
01985   *          @arg @ref HAL_QSPI_ERROR_CB_ID          QSPI Error Callback ID
01986   *          @arg @ref HAL_QSPI_ABORT_CB_ID          QSPI Abort Callback ID
01987   *          @arg @ref HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID
01988   *          @arg @ref HAL_QSPI_CMD_CPLT_CB_ID       QSPI Command Complete Callback ID
01989   *          @arg @ref HAL_QSPI_RX_CPLT_CB_ID        QSPI Rx Complete Callback ID
01990   *          @arg @ref HAL_QSPI_TX_CPLT_CB_ID        QSPI Tx Complete Callback ID
01991   *          @arg @ref HAL_QSPI_RX_HALF_CPLT_CB_ID   QSPI Rx Half Complete Callback ID
01992   *          @arg @ref HAL_QSPI_TX_HALF_CPLT_CB_ID   QSPI Tx Half Complete Callback ID
01993   *          @arg @ref HAL_QSPI_STATUS_MATCH_CB_ID   QSPI Status Match Callback ID
01994   *          @arg @ref HAL_QSPI_TIMEOUT_CB_ID        QSPI Timeout Callback ID
01995   *          @arg @ref HAL_QSPI_MSP_INIT_CB_ID       QSPI MspInit callback ID
01996   *          @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID     QSPI MspDeInit callback ID
01997   * @param pCallback : pointer to the Callback function
01998   * @retval status
01999   */
02000 HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback)
02001 {
02002   HAL_StatusTypeDef status = HAL_OK;
02003
02004   if(pCallback == NULL)
02005   {
02006     /* Update the error code */
02007     hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
02008     return HAL_ERROR;
02009   }
02010
02011   /* Process locked */
02012   __HAL_LOCK(hqspi);
02013
02014   if(hqspi->State == HAL_QSPI_STATE_READY)
02015   {
02016     switch (CallbackId)
02017     {
02018     case  HAL_QSPI_ERROR_CB_ID :
02019       hqspi->ErrorCallback = pCallback;
02020       break;
02021     case HAL_QSPI_ABORT_CB_ID :
02022       hqspi->AbortCpltCallback = pCallback;
02023       break;
02024     case HAL_QSPI_FIFO_THRESHOLD_CB_ID :
02025       hqspi->FifoThresholdCallback = pCallback;
02026       break;
02027     case HAL_QSPI_CMD_CPLT_CB_ID :
02028       hqspi->CmdCpltCallback = pCallback;
02029       break;
02030     case HAL_QSPI_RX_CPLT_CB_ID :
02031       hqspi->RxCpltCallback = pCallback;
02032       break;
02033     case HAL_QSPI_TX_CPLT_CB_ID :
02034       hqspi->TxCpltCallback = pCallback;
02035       break;
02036     case HAL_QSPI_RX_HALF_CPLT_CB_ID :
02037       hqspi->RxHalfCpltCallback = pCallback;
02038       break;
02039     case HAL_QSPI_TX_HALF_CPLT_CB_ID :
02040       hqspi->TxHalfCpltCallback = pCallback;
02041       break;
02042     case HAL_QSPI_STATUS_MATCH_CB_ID :
02043       hqspi->StatusMatchCallback = pCallback;
02044       break;
02045     case HAL_QSPI_TIMEOUT_CB_ID :
02046       hqspi->TimeOutCallback = pCallback;
02047       break;
02048     case HAL_QSPI_MSP_INIT_CB_ID :
02049       hqspi->MspInitCallback = pCallback;
02050       break;
02051     case HAL_QSPI_MSP_DEINIT_CB_ID :
02052       hqspi->MspDeInitCallback = pCallback;
02053       break;
02054     default :
02055       /* Update the error code */
02056       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
02057       /* update return status */
02058       status =  HAL_ERROR;
02059       break;
02060     }
02061   }
02062   else if (hqspi->State == HAL_QSPI_STATE_RESET)
02063   {
02064     switch (CallbackId)
02065     {
02066     case HAL_QSPI_MSP_INIT_CB_ID :
02067       hqspi->MspInitCallback = pCallback;
02068       break;
02069     case HAL_QSPI_MSP_DEINIT_CB_ID :
02070       hqspi->MspDeInitCallback = pCallback;
02071       break;
02072     default :
02073       /* Update the error code */
02074       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
02075       /* update return status */
02076       status =  HAL_ERROR;
02077       break;
02078     }
02079   }
02080   else
02081   {
02082     /* Update the error code */
02083     hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
02084     /* update return status */
02085     status =  HAL_ERROR;
02086   }
02087
02088   /* Release Lock */
02089   __HAL_UNLOCK(hqspi);
02090   return status;
02091 }
02092
02093 /**
02094   * @brief  Unregister a User QSPI Callback
02095   *         QSPI Callback is redirected to the weak (surcharged) predefined callback
02096   * @param hqspi : QSPI handle
02097   * @param CallbackId : ID of the callback to be unregistered
02098   *        This parameter can be one of the following values:
02099   *          @arg @ref HAL_QSPI_ERROR_CB_ID          QSPI Error Callback ID
02100   *          @arg @ref HAL_QSPI_ABORT_CB_ID          QSPI Abort Callback ID
02101   *          @arg @ref HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID
02102   *          @arg @ref HAL_QSPI_CMD_CPLT_CB_ID       QSPI Command Complete Callback ID
02103   *          @arg @ref HAL_QSPI_RX_CPLT_CB_ID        QSPI Rx Complete Callback ID
02104   *          @arg @ref HAL_QSPI_TX_CPLT_CB_ID        QSPI Tx Complete Callback ID
02105   *          @arg @ref HAL_QSPI_RX_HALF_CPLT_CB_ID   QSPI Rx Half Complete Callback ID
02106   *          @arg @ref HAL_QSPI_TX_HALF_CPLT_CB_ID   QSPI Tx Half Complete Callback ID
02107   *          @arg @ref HAL_QSPI_STATUS_MATCH_CB_ID   QSPI Status Match Callback ID
02108   *          @arg @ref HAL_QSPI_TIMEOUT_CB_ID        QSPI Timeout Callback ID
02109   *          @arg @ref HAL_QSPI_MSP_INIT_CB_ID       QSPI MspInit callback ID
02110   *          @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID     QSPI MspDeInit callback ID
02111   * @retval status
02112   */
02113 HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId)
02114 {
02115   HAL_StatusTypeDef status = HAL_OK;
02116
02117   /* Process locked */
02118   __HAL_LOCK(hqspi);
02119
02120   if(hqspi->State == HAL_QSPI_STATE_READY)
02121   {
02122     switch (CallbackId)
02123     {
02124     case  HAL_QSPI_ERROR_CB_ID :
02125       hqspi->ErrorCallback = HAL_QSPI_ErrorCallback;
02126       break;
02127     case HAL_QSPI_ABORT_CB_ID :
02128       hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback;
02129       break;
02130     case HAL_QSPI_FIFO_THRESHOLD_CB_ID :
02131       hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback;
02132       break;
02133     case HAL_QSPI_CMD_CPLT_CB_ID :
02134       hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback;
02135       break;
02136     case HAL_QSPI_RX_CPLT_CB_ID :
02137       hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback;
02138       break;
02139     case HAL_QSPI_TX_CPLT_CB_ID :
02140       hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback;
02141       break;
02142     case HAL_QSPI_RX_HALF_CPLT_CB_ID :
02143       hqspi->RxHalfCpltCallback = HAL_QSPI_RxHalfCpltCallback;
02144       break;
02145     case HAL_QSPI_TX_HALF_CPLT_CB_ID :
02146       hqspi->TxHalfCpltCallback = HAL_QSPI_TxHalfCpltCallback;
02147       break;
02148     case HAL_QSPI_STATUS_MATCH_CB_ID :
02149       hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback;
02150       break;
02151     case HAL_QSPI_TIMEOUT_CB_ID :
02152       hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback;
02153       break;
02154     case HAL_QSPI_MSP_INIT_CB_ID :
02155       hqspi->MspInitCallback = HAL_QSPI_MspInit;
02156       break;
02157     case HAL_QSPI_MSP_DEINIT_CB_ID :
02158       hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;
02159       break;
02160     default :
02161       /* Update the error code */
02162       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
02163       /* update return status */
02164       status =  HAL_ERROR;
02165       break;
02166     }
02167   }
02168   else if (hqspi->State == HAL_QSPI_STATE_RESET)
02169   {
02170     switch (CallbackId)
02171     {
02172     case HAL_QSPI_MSP_INIT_CB_ID :
02173       hqspi->MspInitCallback = HAL_QSPI_MspInit;
02174       break;
02175     case HAL_QSPI_MSP_DEINIT_CB_ID :
02176       hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;
02177       break;
02178     default :
02179       /* Update the error code */
02180       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
02181       /* update return status */
02182       status =  HAL_ERROR;
02183       break;
02184     }
02185   }
02186   else
02187   {
02188     /* Update the error code */
02189     hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
02190     /* update return status */
02191     status =  HAL_ERROR;
02192   }
02193
02194   /* Release Lock */
02195   __HAL_UNLOCK(hqspi);
02196   return status;
02197 }
02198 #endif
02199
02200 /**
02201   * @}
02202   */
02203
02204 /** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions
02205   *  @brief   QSPI control and State functions
02206   *
02207 @verbatim
02208  ===============================================================================
02209                   ##### Peripheral Control and State functions #####
02210  ===============================================================================
02211     [..]
02212     This subsection provides a set of functions allowing to :
02213       (+) Check in run-time the state of the driver.
02214       (+) Check the error code set during last operation.
02215       (+) Abort any operation.
02216
02217
02218 @endverbatim
02219   * @{
02220   */
02221
02222 /**
02223   * @brief  Return the QSPI handle state.
02224   * @param  hqspi : QSPI handle
02225   * @retval HAL state
02226   */
02227 HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
02228 {
02229   /* Return QSPI handle state */
02230   return hqspi->State;
02231 }
02232
02233 /**
02234 * @brief  Return the QSPI error code.
02235 * @param  hqspi : QSPI handle
02236 * @retval QSPI Error Code
02237 */
02238 uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
02239 {
02240   return hqspi->ErrorCode;
02241 }
02242
02243 /**
02244 * @brief  Abort the current transmission.
02245 * @param  hqspi : QSPI handle
02246 * @retval HAL status
02247 */
02248 HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
02249 {
02250   HAL_StatusTypeDef status = HAL_OK;
02251   uint32_t tickstart = HAL_GetTick();
02252
02253   /* Check if the state is in one of the busy states */
02254   if (((uint32_t)hqspi->State & 0x2U) != 0U)
02255   {
02256     /* Process unlocked */
02257     __HAL_UNLOCK(hqspi);
02258
02259     if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
02260     {
02261       /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
02262       CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
02263
02264       /* Abort DMA channel */
02265       status = HAL_DMA_Abort(hqspi->hdma);
02266       if(status != HAL_OK)
02267       {
02268         hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
02269       }
02270     }
02271
02272     /* Configure QSPI: CR register with Abort request */
02273     SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
02274
02275     /* Wait until TC flag is set to go back in idle state */
02276     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);
02277
02278     if (status == HAL_OK)
02279     {
02280       __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
02281
02282       /* Wait until BUSY flag is reset */
02283       status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
02284     }
02285
02286     if (status == HAL_OK)
02287     {
02288       /* Reset functional mode configuration to indirect write mode by default */
02289       CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE);
02290
02291       /* Update state */
02292       hqspi->State = HAL_QSPI_STATE_READY;
02293     }
02294   }
02295
02296   return status;
02297 }
02298
02299 /**
02300 * @brief  Abort the current transmission (non-blocking function)
02301 * @param  hqspi : QSPI handle
02302 * @retval HAL status
02303 */
02304 HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
02305 {
02306   HAL_StatusTypeDef status = HAL_OK;
02307
02308   /* Check if the state is in one of the busy states */
02309   if (((uint32_t)hqspi->State & 0x2U) != 0U)
02310   {
02311     /* Process unlocked */
02312     __HAL_UNLOCK(hqspi);
02313
02314     /* Update QSPI state */
02315     hqspi->State = HAL_QSPI_STATE_ABORT;
02316
02317     /* Disable all interrupts */
02318     __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE));
02319
02320     if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
02321     {
02322       /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
02323       CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
02324
02325       /* Abort DMA channel */
02326       hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
02327       if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK)
02328       {
02329         /* Change state of QSPI */
02330         hqspi->State = HAL_QSPI_STATE_READY;
02331
02332         /* Abort Complete callback */
02333 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
02334         hqspi->AbortCpltCallback(hqspi);
02335 #else
02336         HAL_QSPI_AbortCpltCallback(hqspi);
02337 #endif
02338       }
02339     }
02340     else
02341     {
02342       /* Clear interrupt */
02343       __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
02344
02345       /* Enable the QSPI Transfer Complete Interrupt */
02346       __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
02347
02348       /* Configure QSPI: CR register with Abort request */
02349       SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
02350     }
02351   }
02352   return status;
02353 }
02354
02355 /** @brief Set QSPI timeout.
02356   * @param  hqspi : QSPI handle.
02357   * @param  Timeout : Timeout for the QSPI memory access.
02358   * @retval None
02359   */
02360 void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
02361 {
02362   hqspi->Timeout = Timeout;
02363 }
02364
02365 /** @brief Set QSPI Fifo threshold.
02366   * @param  hqspi : QSPI handle.
02367   * @param  Threshold : Threshold of the Fifo (value between 1 and 16).
02368   * @retval HAL status
02369   */
02370 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
02371 {
02372   HAL_StatusTypeDef status = HAL_OK;
02373
02374   /* Process locked */
02375   __HAL_LOCK(hqspi);
02376
02377   if(hqspi->State == HAL_QSPI_STATE_READY)
02378   {
02379     /* Synchronize init structure with new FIFO threshold value */
02380     hqspi->Init.FifoThreshold = Threshold;
02381
02382     /* Configure QSPI FIFO Threshold */
02383     MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
02384                ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos));
02385   }
02386   else
02387   {
02388     status = HAL_BUSY;
02389   }
02390
02391   /* Process unlocked */
02392   __HAL_UNLOCK(hqspi);
02393
02394   /* Return function status */
02395   return status;
02396 }
02397
02398 /** @brief Get QSPI Fifo threshold.
02399   * @param  hqspi : QSPI handle.
02400   * @retval Fifo threshold (value between 1 and 16)
02401   */
02402 uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
02403 {
02404   return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U);
02405 }
02406
02407 /**
02408   * @}
02409   */
02410
02411 /**
02412   * @}
02413   */
02414
02415 /** @defgroup QSPI_Private_Functions QSPI Private Functions
02416   * @{
02417   */
02418
02419 /**
02420   * @brief  DMA QSPI receive process complete callback.
02421   * @param  hdma : DMA handle
02422   * @retval None
02423   */
02424 static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)
02425 {
02426   QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);
02427   hqspi->RxXferCount = 0U;
02428
02429   /* Enable the QSPI transfer complete Interrupt */
02430   __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
02431 }
02432
02433 /**
02434   * @brief  DMA QSPI transmit process complete callback.
02435   * @param  hdma : DMA handle
02436   * @retval None
02437   */
02438 static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)
02439 {
02440   QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);
02441   hqspi->TxXferCount = 0U;
02442
02443   /* Enable the QSPI transfer complete Interrupt */
02444   __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
02445 }
02446
02447 /**
02448   * @brief  DMA QSPI receive process half complete callback.
02449   * @param  hdma : DMA handle
02450   * @retval None
02451   */
02452 static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
02453 {
02454   QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);
02455
02456 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
02457   hqspi->RxHalfCpltCallback(hqspi);
02458 #else
02459   HAL_QSPI_RxHalfCpltCallback(hqspi);
02460 #endif
02461 }
02462
02463 /**
02464   * @brief  DMA QSPI transmit process half complete callback.
02465   * @param  hdma : DMA handle
02466   * @retval None
02467   */
02468 static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
02469 {
02470   QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);
02471
02472 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
02473   hqspi->TxHalfCpltCallback(hqspi);
02474 #else
02475   HAL_QSPI_TxHalfCpltCallback(hqspi);
02476 #endif
02477 }
02478
02479 /**
02480   * @brief  DMA QSPI communication error callback.
02481   * @param  hdma : DMA handle
02482   * @retval None
02483   */
02484 static void QSPI_DMAError(DMA_HandleTypeDef *hdma)
02485 {
02486   QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent);
02487
02488   hqspi->RxXferCount = 0U;
02489   hqspi->TxXferCount = 0U;
02490   hqspi->ErrorCode   |= HAL_QSPI_ERROR_DMA;
02491
02492   /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
02493   CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
02494
02495   /* Abort the QSPI */
02496   (void)HAL_QSPI_Abort_IT(hqspi);
02497
02498 }
02499
02500 /**
02501   * @brief  DMA QSPI abort complete callback.
02502   * @param  hdma : DMA handle
02503   * @retval None
02504   */
02505 static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma)
02506 {
02507   QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent);
02508
02509   hqspi->RxXferCount = 0U;
02510   hqspi->TxXferCount = 0U;
02511
02512   if(hqspi->State == HAL_QSPI_STATE_ABORT)
02513   {
02514     /* DMA Abort called by QSPI abort */
02515     /* Clear interrupt */
02516     __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
02517
02518     /* Enable the QSPI Transfer Complete Interrupt */
02519     __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
02520
02521     /* Configure QSPI: CR register with Abort request */
02522     SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
02523   }
02524   else
02525   {
02526     /* DMA Abort called due to a transfer error interrupt */
02527     /* Change state of QSPI */
02528     hqspi->State = HAL_QSPI_STATE_READY;
02529
02530     /* Error callback */
02531 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
02532     hqspi->ErrorCallback(hqspi);
02533 #else
02534     HAL_QSPI_ErrorCallback(hqspi);
02535 #endif
02536   }
02537 }
02538
02539 /**
02540   * @brief  Wait for a flag state until timeout.
02541   * @param  hqspi : QSPI handle
02542   * @param  Flag : Flag checked
02543   * @param  State : Value of the flag expected
02544   * @param  Tickstart : Tick start value
02545   * @param  Timeout : Duration of the timeout
02546   * @retval HAL status
02547   */
02548 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
02549                                                         FlagStatus State, uint32_t Tickstart, uint32_t Timeout)
02550 {
02551   /* Wait until flag is in expected state */
02552   while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
02553   {
02554     /* Check for the Timeout */
02555     if (Timeout != HAL_MAX_DELAY)
02556     {
02557       if(((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
02558       {
02559         hqspi->State     = HAL_QSPI_STATE_ERROR;
02560         hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
02561
02562         return HAL_ERROR;
02563       }
02564     }
02565   }
02566   return HAL_OK;
02567 }
02568
02569 /**
02570   * @brief  Configure the communication registers.
02571   * @param  hqspi : QSPI handle
02572   * @param  cmd : structure that contains the command configuration information
02573   * @param  FunctionalMode : functional mode to configured
02574   *           This parameter can be one of the following values:
02575   *            @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
02576   *            @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
02577   *            @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
02578   *            @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
02579   * @retval None
02580   */
02581 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)
02582 {
02583   assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));
02584
02585   if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
02586   {
02587     /* Configure QSPI: DLR register with the number of data to read or write */
02588     WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1U));
02589   }
02590
02591   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
02592   {
02593     if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
02594     {
02595       /* Configure QSPI: ABR register with alternate bytes value */
02596       WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
02597
02598       if (cmd->AddressMode != QSPI_ADDRESS_NONE)
02599       {
02600         /*---- Command with instruction, address and alternate bytes ----*/
02601         /* Configure QSPI: CCR register with all communications parameters */
02602         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->SIOOMode |
02603                                          cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
02604                                          cmd->AlternateBytesSize | cmd->AlternateByteMode |
02605                                          cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
02606                                          cmd->Instruction | FunctionalMode));
02607
02608         if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
02609         {
02610           /* Configure QSPI: AR register with address value */
02611           WRITE_REG(hqspi->Instance->AR, cmd->Address);
02612         }
02613       }
02614       else
02615       {
02616         /*---- Command with instruction and alternate bytes ----*/
02617         /* Configure QSPI: CCR register with all communications parameters */
02618         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->SIOOMode |
02619                                          cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
02620                                          cmd->AlternateBytesSize | cmd->AlternateByteMode |
02621                                          cmd->AddressMode | cmd->InstructionMode |
02622                                          cmd->Instruction | FunctionalMode));
02623       }
02624     }
02625     else
02626     {
02627       if (cmd->AddressMode != QSPI_ADDRESS_NONE)
02628       {
02629         /*---- Command with instruction and address ----*/
02630         /* Configure QSPI: CCR register with all communications parameters */
02631         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->SIOOMode |
02632                                          cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
02633                                          cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
02634                                          cmd->InstructionMode | cmd->Instruction | FunctionalMode));
02635
02636         if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
02637         {
02638           /* Configure QSPI: AR register with address value */
02639           WRITE_REG(hqspi->Instance->AR, cmd->Address);
02640         }
02641       }
02642       else
02643       {
02644         /*---- Command with only instruction ----*/
02645         /* Configure QSPI: CCR register with all communications parameters */
02646         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->SIOOMode |
02647                                          cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
02648                                          cmd->AlternateByteMode | cmd->AddressMode |
02649                                          cmd->InstructionMode | cmd->Instruction | FunctionalMode));
02650       }
02651     }
02652   }
02653   else
02654   {
02655     if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
02656     {
02657       /* Configure QSPI: ABR register with alternate bytes value */
02658       WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
02659
02660       if (cmd->AddressMode != QSPI_ADDRESS_NONE)
02661       {
02662         /*---- Command with address and alternate bytes ----*/
02663         /* Configure QSPI: CCR register with all communications parameters */
02664         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->SIOOMode |
02665                                          cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
02666                                          cmd->AlternateBytesSize | cmd->AlternateByteMode |
02667                                          cmd->AddressSize | cmd->AddressMode |
02668                                          cmd->InstructionMode | FunctionalMode));
02669
02670         if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
02671         {
02672           /* Configure QSPI: AR register with address value */
02673           WRITE_REG(hqspi->Instance->AR, cmd->Address);
02674         }
02675       }
02676       else
02677       {
02678         /*---- Command with only alternate bytes ----*/
02679         /* Configure QSPI: CCR register with all communications parameters */
02680         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->SIOOMode |
02681                                          cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
02682                                          cmd->AlternateBytesSize | cmd->AlternateByteMode |
02683                                          cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
02684       }
02685     }
02686     else
02687     {
02688       if (cmd->AddressMode != QSPI_ADDRESS_NONE)
02689       {
02690         /*---- Command with only address ----*/
02691         /* Configure QSPI: CCR register with all communications parameters */
02692         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->SIOOMode |
02693                                          cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
02694                                          cmd->AlternateByteMode | cmd->AddressSize |
02695                                          cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
02696
02697         if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
02698         {
02699           /* Configure QSPI: AR register with address value */
02700           WRITE_REG(hqspi->Instance->AR, cmd->Address);
02701         }
02702       }
02703       else
02704       {
02705         /*---- Command with only data phase ----*/
02706         if (cmd->DataMode != QSPI_DATA_NONE)
02707         {
02708           /* Configure QSPI: CCR register with all communications parameters */
02709           WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->SIOOMode |
02710                                            cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
02711                                            cmd->AlternateByteMode | cmd->AddressMode |
02712                                            cmd->InstructionMode | FunctionalMode));
02713         }
02714       }
02715     }
02716   }
02717 }
02718
02719 /**
02720   * @}
02721   */
02722
02723 /**
02724   * @}
02725   */
02726
02727 #endif /* HAL_QSPI_MODULE_ENABLED */
02728 /**
02729   * @}
02730   */
02731
02732 /**
02733   * @}
02734   */
02735
02736 #endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */
02737
02738 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:35 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_qspi.h Source File

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stm32wbxx_hal_qspi.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_qspi.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of QSPI HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
00010   *
00011   * This software component is licensed by ST under BSD 3-Clause license,
00012   * the "License"; You may not use this file except in compliance with the
00013   * License. You may obtain a copy of the License at:
00014   *                       opensource.org/licenses/BSD-3-Clause
00015   *
00016   ******************************************************************************
00017   */
00018
00019 /* Define to prevent recursive inclusion -------------------------------------*/
00020 #ifndef STM32WBxx_HAL_QSPI_H
00021 #define STM32WBxx_HAL_QSPI_H
00022
00023 #ifdef __cplusplus
00024  extern "C" {
00025 #endif
00026
00027 /* Includes ------------------------------------------------------------------*/
00028 #include "stm32wbxx_hal_def.h"
00029
00030 #if defined(QUADSPI)
00031
00032 /** @addtogroup STM32WBxx_HAL_Driver
00033   * @{
00034   */
00035
00036 /** @addtogroup QSPI
00037   * @{
00038   */
00039
00040 /* Exported types ------------------------------------------------------------*/
00041 /** @defgroup QSPI_Exported_Types QSPI Exported Types
00042   * @{
00043   */
00044
00045 /**
00046   * @brief  QSPI Init structure definition
00047   */
00048 typedef struct
00049 {
00050   uint32_t ClockPrescaler;     /* Specifies the prescaler factor for generating clock based on the AHB clock.
00051                                   This parameter can be a number between 0 and 255 */
00052   uint32_t FifoThreshold;      /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
00053                                   This parameter can be a value between 1 and 16 */
00054   uint32_t SampleShifting;     /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
00055                                   take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
00056                                   This parameter can be a value of @ref QSPI_SampleShifting */
00057   uint32_t FlashSize;          /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
00058                                   required to address the flash memory. The flash capacity can be up to 4GB
00059                                   (addressed using 32 bits) in indirect mode, but the addressable space in
00060                                   memory-mapped mode is limited to 256MB
00061                                   This parameter can be a number between 0 and 31 */
00062   uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
00063                                   of clock cycles which the chip select must remain high between commands.
00064                                   This parameter can be a value of @ref QSPI_ChipSelectHighTime */
00065   uint32_t ClockMode;          /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
00066                                   This parameter can be a value of @ref QSPI_ClockMode */
00067 }QSPI_InitTypeDef;
00068
00069 /**
00070   * @brief HAL QSPI State structures definition
00071   */
00072 typedef enum
00073 {
00074   HAL_QSPI_STATE_RESET             = 0x00U,    /*!< Peripheral not initialized                            */
00075   HAL_QSPI_STATE_READY             = 0x01U,    /*!< Peripheral initialized and ready for use              */
00076   HAL_QSPI_STATE_BUSY              = 0x02U,    /*!< Peripheral in indirect mode and busy                  */
00077   HAL_QSPI_STATE_BUSY_INDIRECT_TX  = 0x12U,    /*!< Peripheral in indirect mode with transmission ongoing */
00078   HAL_QSPI_STATE_BUSY_INDIRECT_RX  = 0x22U,    /*!< Peripheral in indirect mode with reception ongoing    */
00079   HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U,    /*!< Peripheral in auto polling mode ongoing               */
00080   HAL_QSPI_STATE_BUSY_MEM_MAPPED   = 0x82U,    /*!< Peripheral in memory mapped mode ongoing              */
00081   HAL_QSPI_STATE_ABORT             = 0x08U,    /*!< Peripheral with abort request ongoing                 */
00082   HAL_QSPI_STATE_ERROR             = 0x04U     /*!< Peripheral in error                                   */
00083 }HAL_QSPI_StateTypeDef;
00084
00085 /**
00086   * @brief  QSPI Handle Structure definition
00087   */
00088 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00089 typedef struct __QSPI_HandleTypeDef
00090 #else
00091 typedef struct
00092 #endif
00093 {
00094   QUADSPI_TypeDef            *Instance;        /* QSPI registers base address        */
00095   QSPI_InitTypeDef           Init;             /* QSPI communication parameters      */
00096   uint8_t                    *pTxBuffPtr;      /* Pointer to QSPI Tx transfer Buffer */
00097   __IO uint32_t              TxXferSize;       /* QSPI Tx Transfer size              */
00098   __IO uint32_t              TxXferCount;      /* QSPI Tx Transfer Counter           */
00099   uint8_t                    *pRxBuffPtr;      /* Pointer to QSPI Rx transfer Buffer */
00100   __IO uint32_t              RxXferSize;       /* QSPI Rx Transfer size              */
00101   __IO uint32_t              RxXferCount;      /* QSPI Rx Transfer Counter           */
00102   DMA_HandleTypeDef          *hdma;            /* QSPI Rx/Tx DMA Handle parameters   */
00103   __IO HAL_LockTypeDef       Lock;             /* Locking object                     */
00104   __IO HAL_QSPI_StateTypeDef State;            /* QSPI communication state           */
00105   __IO uint32_t              ErrorCode;        /* QSPI Error code                    */
00106   uint32_t                   Timeout;          /* Timeout for the QSPI memory access */
00107 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00108   void (* ErrorCallback)        (struct __QSPI_HandleTypeDef *hqspi);
00109   void (* AbortCpltCallback)    (struct __QSPI_HandleTypeDef *hqspi);
00110   void (* FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi);
00111   void (* CmdCpltCallback)      (struct __QSPI_HandleTypeDef *hqspi);
00112   void (* RxCpltCallback)       (struct __QSPI_HandleTypeDef *hqspi);
00113   void (* TxCpltCallback)       (struct __QSPI_HandleTypeDef *hqspi);
00114   void (* RxHalfCpltCallback)   (struct __QSPI_HandleTypeDef *hqspi);
00115   void (* TxHalfCpltCallback)   (struct __QSPI_HandleTypeDef *hqspi);
00116   void (* StatusMatchCallback)  (struct __QSPI_HandleTypeDef *hqspi);
00117   void (* TimeOutCallback)      (struct __QSPI_HandleTypeDef *hqspi);
00118
00119   void (* MspInitCallback)      (struct __QSPI_HandleTypeDef *hqspi);
00120   void (* MspDeInitCallback)    (struct __QSPI_HandleTypeDef *hqspi);
00121 #endif
00122 }QSPI_HandleTypeDef;
00123
00124 /**
00125   * @brief  QSPI Command structure definition
00126   */
00127 typedef struct
00128 {
00129   uint32_t Instruction;        /* Specifies the Instruction to be sent
00130                                   This parameter can be a value (8-bit) between 0x00 and 0xFF */
00131   uint32_t Address;            /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
00132                                   This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
00133   uint32_t AlternateBytes;     /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
00134                                   This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
00135   uint32_t AddressSize;        /* Specifies the Address Size
00136                                   This parameter can be a value of @ref QSPI_AddressSize */
00137   uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
00138                                   This parameter can be a value of @ref QSPI_AlternateBytesSize */
00139   uint32_t DummyCycles;        /* Specifies the Number of Dummy Cycles.
00140                                   This parameter can be a number between 0 and 31 */
00141   uint32_t InstructionMode;    /* Specifies the Instruction Mode
00142                                   This parameter can be a value of @ref QSPI_InstructionMode */
00143   uint32_t AddressMode;        /* Specifies the Address Mode
00144                                   This parameter can be a value of @ref QSPI_AddressMode */
00145   uint32_t AlternateByteMode;  /* Specifies the Alternate Bytes Mode
00146                                   This parameter can be a value of @ref QSPI_AlternateBytesMode */
00147   uint32_t DataMode;           /* Specifies the Data Mode (used for dummy cycles and data phases)
00148                                   This parameter can be a value of @ref QSPI_DataMode */
00149   uint32_t NbData;             /* Specifies the number of data to transfer. (This is the number of bytes)
00150                                   This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
00151                                   until end of memory)*/
00152   uint32_t DdrMode;            /* Specifies the double data rate mode for address, alternate byte and data phase
00153                                   This parameter can be a value of @ref QSPI_DdrMode */
00154   uint32_t SIOOMode;           /* Specifies the send instruction only once mode
00155                                   This parameter can be a value of @ref QSPI_SIOOMode */
00156 }QSPI_CommandTypeDef;
00157
00158 /**
00159   * @brief  QSPI Auto Polling mode configuration structure definition
00160   */
00161 typedef struct
00162 {
00163   uint32_t Match;              /* Specifies the value to be compared with the masked status register to get a match.
00164                                   This parameter can be any value between 0 and 0xFFFFFFFF */
00165   uint32_t Mask;               /* Specifies the mask to be applied to the status bytes received.
00166                                   This parameter can be any value between 0 and 0xFFFFFFFF */
00167   uint32_t Interval;           /* Specifies the number of clock cycles between two read during automatic polling phases.
00168                                   This parameter can be any value between 0 and 0xFFFF */
00169   uint32_t StatusBytesSize;    /* Specifies the size of the status bytes received.
00170                                   This parameter can be any value between 1 and 4 */
00171   uint32_t MatchMode;          /* Specifies the method used for determining a match.
00172                                   This parameter can be a value of @ref QSPI_MatchMode */
00173   uint32_t AutomaticStop;      /* Specifies if automatic polling is stopped after a match.
00174                                   This parameter can be a value of @ref QSPI_AutomaticStop */
00175 }QSPI_AutoPollingTypeDef;
00176
00177 /**
00178   * @brief  QSPI Memory Mapped mode configuration structure definition
00179   */
00180 typedef struct
00181 {
00182   uint32_t TimeOutPeriod;      /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
00183                                   This parameter can be any value between 0 and 0xFFFF */
00184   uint32_t TimeOutActivation;  /* Specifies if the timeout counter is enabled to release the chip select.
00185                                   This parameter can be a value of @ref QSPI_TimeOutActivation */
00186 }QSPI_MemoryMappedTypeDef;
00187
00188 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00189 /**
00190   * @brief  HAL QSPI Callback ID enumeration definition
00191   */
00192 typedef enum
00193 {
00194   HAL_QSPI_ERROR_CB_ID          = 0x00U,  /*!< QSPI Error Callback ID            */
00195   HAL_QSPI_ABORT_CB_ID          = 0x01U,  /*!< QSPI Abort Callback ID            */
00196   HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U,  /*!< QSPI FIFO Threshold Callback ID   */
00197   HAL_QSPI_CMD_CPLT_CB_ID       = 0x03U,  /*!< QSPI Command Complete Callback ID */
00198   HAL_QSPI_RX_CPLT_CB_ID        = 0x04U,  /*!< QSPI Rx Complete Callback ID      */
00199   HAL_QSPI_TX_CPLT_CB_ID        = 0x05U,  /*!< QSPI Tx Complete Callback ID      */
00200   HAL_QSPI_RX_HALF_CPLT_CB_ID   = 0x06U,  /*!< QSPI Rx Half Complete Callback ID */
00201   HAL_QSPI_TX_HALF_CPLT_CB_ID   = 0x07U,  /*!< QSPI Tx Half Complete Callback ID */
00202   HAL_QSPI_STATUS_MATCH_CB_ID   = 0x08U,  /*!< QSPI Status Match Callback ID     */
00203   HAL_QSPI_TIMEOUT_CB_ID        = 0x09U,  /*!< QSPI Timeout Callback ID          */
00204
00205   HAL_QSPI_MSP_INIT_CB_ID       = 0x0AU,  /*!< QSPI MspInit Callback ID          */
00206   HAL_QSPI_MSP_DEINIT_CB_ID     = 0x0B0   /*!< QSPI MspDeInit Callback ID        */
00207 }HAL_QSPI_CallbackIDTypeDef;
00208
00209 /**
00210   * @brief  HAL QSPI Callback pointer definition
00211   */
00212 typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
00213 #endif
00214 /**
00215   * @}
00216   */
00217
00218 /* Exported constants --------------------------------------------------------*/
00219 /** @defgroup QSPI_Exported_Constants QSPI Exported Constants
00220   * @{
00221   */
00222
00223 /** @defgroup QSPI_ErrorCode QSPI Error Code
00224   * @{
00225   */
00226 #define HAL_QSPI_ERROR_NONE             0x00000000U /*!< No error                 */
00227 #define HAL_QSPI_ERROR_TIMEOUT          0x00000001U /*!< Timeout error            */
00228 #define HAL_QSPI_ERROR_TRANSFER         0x00000002U /*!< Transfer error           */
00229 #define HAL_QSPI_ERROR_DMA              0x00000004U /*!< DMA transfer error       */
00230 #define HAL_QSPI_ERROR_INVALID_PARAM    0x00000008U /*!< Invalid parameters error */
00231 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00232 #define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error   */
00233 #endif
00234 /**
00235   * @}
00236   */
00237
00238 /** @defgroup QSPI_SampleShifting QSPI Sample Shifting
00239   * @{
00240   */
00241 #define QSPI_SAMPLE_SHIFTING_NONE      0x00000000U                   /*!<No clock cycle shift to sample data*/
00242 #define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
00243 /**
00244   * @}
00245   */
00246
00247 /** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time
00248   * @{
00249   */
00250 #define QSPI_CS_HIGH_TIME_1_CYCLE      0x00000000U                                         /*!<nCS stay high for at least 1 clock cycle between commands*/
00251 #define QSPI_CS_HIGH_TIME_2_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_0)                      /*!<nCS stay high for at least 2 clock cycles between commands*/
00252 #define QSPI_CS_HIGH_TIME_3_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_1)                      /*!<nCS stay high for at least 3 clock cycles between commands*/
00253 #define QSPI_CS_HIGH_TIME_4_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
00254 #define QSPI_CS_HIGH_TIME_5_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2)                      /*!<nCS stay high for at least 5 clock cycles between commands*/
00255 #define QSPI_CS_HIGH_TIME_6_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/
00256 #define QSPI_CS_HIGH_TIME_7_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/
00257 #define QSPI_CS_HIGH_TIME_8_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT)                        /*!<nCS stay high for at least 8 clock cycles between commands*/
00258 /**
00259   * @}
00260   */
00261
00262 /** @defgroup QSPI_ClockMode QSPI Clock Mode
00263   * @{
00264   */
00265 #define QSPI_CLOCK_MODE_0              0x00000000U                    /*!<Clk stays low while nCS is released*/
00266 #define QSPI_CLOCK_MODE_3              ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
00267 /**
00268   * @}
00269   */
00270
00271 /** @defgroup QSPI_AddressSize QSPI Address Size
00272   * @{
00273   */
00274 #define QSPI_ADDRESS_8_BITS            0x00000000U                      /*!<8-bit address*/
00275 #define QSPI_ADDRESS_16_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
00276 #define QSPI_ADDRESS_24_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
00277 #define QSPI_ADDRESS_32_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE)   /*!<32-bit address*/
00278 /**
00279   * @}
00280   */
00281
00282 /** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
00283   * @{
00284   */
00285 #define QSPI_ALTERNATE_BYTES_8_BITS    0x00000000U                      /*!<8-bit alternate bytes*/
00286 #define QSPI_ALTERNATE_BYTES_16_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
00287 #define QSPI_ALTERNATE_BYTES_24_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
00288 #define QSPI_ALTERNATE_BYTES_32_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE)   /*!<32-bit alternate bytes*/
00289 /**
00290   * @}
00291   */
00292
00293 /** @defgroup QSPI_InstructionMode QSPI Instruction Mode
00294 * @{
00295 */
00296 #define QSPI_INSTRUCTION_NONE          0x00000000U                     /*!<No instruction*/
00297 #define QSPI_INSTRUCTION_1_LINE        ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
00298 #define QSPI_INSTRUCTION_2_LINES       ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
00299 #define QSPI_INSTRUCTION_4_LINES       ((uint32_t)QUADSPI_CCR_IMODE)   /*!<Instruction on four lines*/
00300 /**
00301   * @}
00302   */
00303
00304 /** @defgroup QSPI_AddressMode QSPI Address Mode
00305 * @{
00306 */
00307 #define QSPI_ADDRESS_NONE              0x00000000U                      /*!<No address*/
00308 #define QSPI_ADDRESS_1_LINE            ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
00309 #define QSPI_ADDRESS_2_LINES           ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
00310 #define QSPI_ADDRESS_4_LINES           ((uint32_t)QUADSPI_CCR_ADMODE)   /*!<Address on four lines*/
00311 /**
00312   * @}
00313   */
00314
00315 /** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
00316 * @{
00317 */
00318 #define QSPI_ALTERNATE_BYTES_NONE      0x00000000U                      /*!<No alternate bytes*/
00319 #define QSPI_ALTERNATE_BYTES_1_LINE    ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
00320 #define QSPI_ALTERNATE_BYTES_2_LINES   ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
00321 #define QSPI_ALTERNATE_BYTES_4_LINES   ((uint32_t)QUADSPI_CCR_ABMODE)   /*!<Alternate bytes on four lines*/
00322 /**
00323   * @}
00324   */
00325
00326 /** @defgroup QSPI_DataMode QSPI Data Mode
00327   * @{
00328   */
00329 #define QSPI_DATA_NONE                 0x00000000U                     /*!<No data*/
00330 #define QSPI_DATA_1_LINE               ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
00331 #define QSPI_DATA_2_LINES              ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
00332 #define QSPI_DATA_4_LINES              ((uint32_t)QUADSPI_CCR_DMODE)   /*!<Data on four lines*/
00333 /**
00334   * @}
00335   */
00336
00337 /** @defgroup QSPI_DdrMode QSPI DDR Mode
00338   * @{
00339   */
00340 #define QSPI_DDR_MODE_DISABLE          0x00000000U                  /*!<Double data rate mode disabled*/
00341 #define QSPI_DDR_MODE_ENABLE           ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
00342 /**
00343   * @}
00344   */
00345
00346 /** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode
00347   * @{
00348   */
00349 #define QSPI_SIOO_INST_EVERY_CMD       0x00000000U                  /*!<Send instruction on every transaction*/
00350 #define QSPI_SIOO_INST_ONLY_FIRST_CMD  ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
00351 /**
00352   * @}
00353   */
00354
00355 /** @defgroup QSPI_MatchMode QSPI Match Mode
00356   * @{
00357   */
00358 #define QSPI_MATCH_MODE_AND            0x00000000U                /*!<AND match mode between unmasked bits*/
00359 #define QSPI_MATCH_MODE_OR             ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
00360 /**
00361   * @}
00362   */
00363
00364 /** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
00365   * @{
00366   */
00367 #define QSPI_AUTOMATIC_STOP_DISABLE    0x00000000U                 /*!<AutoPolling stops only with abort or QSPI disabling*/
00368 #define QSPI_AUTOMATIC_STOP_ENABLE     ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
00369 /**
00370   * @}
00371   */
00372
00373 /** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation
00374   * @{
00375   */
00376 #define QSPI_TIMEOUT_COUNTER_DISABLE   0x00000000U                 /*!<Timeout counter disabled, nCS remains active*/
00377 #define QSPI_TIMEOUT_COUNTER_ENABLE    ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
00378 /**
00379   * @}
00380   */
00381
00382 /** @defgroup QSPI_Flags QSPI Flags
00383   * @{
00384   */
00385 #define QSPI_FLAG_BUSY                 QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
00386 #define QSPI_FLAG_TO                   QUADSPI_SR_TOF  /*!<Timeout flag: timeout occurs in memory-mapped mode*/
00387 #define QSPI_FLAG_SM                   QUADSPI_SR_SMF  /*!<Status match flag: received data matches in autopolling mode*/
00388 #define QSPI_FLAG_FT                   QUADSPI_SR_FTF  /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/
00389 #define QSPI_FLAG_TC                   QUADSPI_SR_TCF  /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/
00390 #define QSPI_FLAG_TE                   QUADSPI_SR_TEF  /*!<Transfer error flag: invalid address is being accessed*/
00391 /**
00392   * @}
00393   */
00394
00395 /** @defgroup QSPI_Interrupts QSPI Interrupts
00396   * @{
00397   */
00398 #define QSPI_IT_TO                     QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
00399 #define QSPI_IT_SM                     QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
00400 #define QSPI_IT_FT                     QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
00401 #define QSPI_IT_TC                     QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
00402 #define QSPI_IT_TE                     QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
00403 /**
00404   * @}
00405   */
00406
00407 /** @defgroup QSPI_Timeout_definition QSPI Timeout definition
00408   * @brief QSPI Timeout definition
00409   * @{
00410   */
00411 #define HAL_QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */
00412 /**
00413   * @}
00414   */
00415
00416 /**
00417   * @}
00418   */
00419
00420 /* Exported macros -----------------------------------------------------------*/
00421 /** @defgroup QSPI_Exported_Macros QSPI Exported Macros
00422   * @{
00423   */
00424 /** @brief Reset QSPI handle state.
00425   * @param  __HANDLE__ : QSPI handle.
00426   * @retval None
00427   */
00428 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00429 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__)           do {                                              \
00430                                                                   (__HANDLE__)->State = HAL_QSPI_STATE_RESET; \
00431                                                                   (__HANDLE__)->MspInitCallback = NULL;       \
00432                                                                   (__HANDLE__)->MspDeInitCallback = NULL;     \
00433                                                                } while(0)
00434 #else
00435 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__)           ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
00436 #endif
00437
00438 /** @brief  Enable the QSPI peripheral.
00439   * @param  __HANDLE__ : specifies the QSPI Handle.
00440   * @retval None
00441   */
00442 #define __HAL_QSPI_ENABLE(__HANDLE__)                       SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
00443
00444 /** @brief  Disable the QSPI peripheral.
00445   * @param  __HANDLE__ : specifies the QSPI Handle.
00446   * @retval None
00447   */
00448 #define __HAL_QSPI_DISABLE(__HANDLE__)                      CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
00449
00450 /** @brief  Enable the specified QSPI interrupt.
00451   * @param  __HANDLE__ : specifies the QSPI Handle.
00452   * @param  __INTERRUPT__ : specifies the QSPI interrupt source to enable.
00453   *          This parameter can be one of the following values:
00454   *            @arg QSPI_IT_TO: QSPI Timeout interrupt
00455   *            @arg QSPI_IT_SM: QSPI Status match interrupt
00456   *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
00457   *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
00458   *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
00459   * @retval None
00460   */
00461 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)     SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
00462
00463
00464 /** @brief  Disable the specified QSPI interrupt.
00465   * @param  __HANDLE__ : specifies the QSPI Handle.
00466   * @param  __INTERRUPT__ : specifies the QSPI interrupt source to disable.
00467   *          This parameter can be one of the following values:
00468   *            @arg QSPI_IT_TO: QSPI Timeout interrupt
00469   *            @arg QSPI_IT_SM: QSPI Status match interrupt
00470   *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
00471   *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
00472   *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
00473   * @retval None
00474   */
00475 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)    CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
00476
00477 /** @brief  Check whether the specified QSPI interrupt source is enabled or not.
00478   * @param  __HANDLE__ : specifies the QSPI Handle.
00479   * @param  __INTERRUPT__ : specifies the QSPI interrupt source to check.
00480   *          This parameter can be one of the following values:
00481   *            @arg QSPI_IT_TO: QSPI Timeout interrupt
00482   *            @arg QSPI_IT_SM: QSPI Status match interrupt
00483   *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
00484   *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
00485   *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
00486   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
00487   */
00488 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
00489
00490 /**
00491   * @brief  Check whether the selected QSPI flag is set or not.
00492   * @param  __HANDLE__ : specifies the QSPI Handle.
00493   * @param  __FLAG__ : specifies the QSPI flag to check.
00494   *          This parameter can be one of the following values:
00495   *            @arg QSPI_FLAG_BUSY: QSPI Busy flag
00496   *            @arg QSPI_FLAG_TO:   QSPI Timeout flag
00497   *            @arg QSPI_FLAG_SM:   QSPI Status match flag
00498   *            @arg QSPI_FLAG_FT:   QSPI FIFO threshold flag
00499   *            @arg QSPI_FLAG_TC:   QSPI Transfer complete flag
00500   *            @arg QSPI_FLAG_TE:   QSPI Transfer error flag
00501   * @retval None
00502   */
00503 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__)           ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)
00504
00505 /** @brief  Clears the specified QSPI's flag status.
00506   * @param  __HANDLE__ : specifies the QSPI Handle.
00507   * @param  __FLAG__ : specifies the QSPI clear register flag that needs to be set
00508   *          This parameter can be one of the following values:
00509   *            @arg QSPI_FLAG_TO: QSPI Timeout flag
00510   *            @arg QSPI_FLAG_SM: QSPI Status match flag
00511   *            @arg QSPI_FLAG_TC: QSPI Transfer complete flag
00512   *            @arg QSPI_FLAG_TE: QSPI Transfer error flag
00513   * @retval None
00514   */
00515 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__)         WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
00516 /**
00517   * @}
00518   */
00519
00520 /* Exported functions --------------------------------------------------------*/
00521 /** @addtogroup QSPI_Exported_Functions
00522   * @{
00523   */
00524
00525 /** @addtogroup QSPI_Exported_Functions_Group1
00526   * @{
00527   */
00528 /* Initialization/de-initialization functions  ********************************/
00529 HAL_StatusTypeDef     HAL_QSPI_Init     (QSPI_HandleTypeDef *hqspi);
00530 HAL_StatusTypeDef     HAL_QSPI_DeInit   (QSPI_HandleTypeDef *hqspi);
00531 void                  HAL_QSPI_MspInit  (QSPI_HandleTypeDef *hqspi);
00532 void                  HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
00533 /**
00534   * @}
00535   */
00536
00537 /** @addtogroup QSPI_Exported_Functions_Group2
00538   * @{
00539   */
00540 /* IO operation functions *****************************************************/
00541 /* QSPI IRQ handler method */
00542 void                  HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
00543
00544 /* QSPI indirect mode */
00545 HAL_StatusTypeDef     HAL_QSPI_Command      (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);
00546 HAL_StatusTypeDef     HAL_QSPI_Transmit     (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
00547 HAL_StatusTypeDef     HAL_QSPI_Receive      (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
00548 HAL_StatusTypeDef     HAL_QSPI_Command_IT   (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);
00549 HAL_StatusTypeDef     HAL_QSPI_Transmit_IT  (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
00550 HAL_StatusTypeDef     HAL_QSPI_Receive_IT   (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
00551 HAL_StatusTypeDef     HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
00552 HAL_StatusTypeDef     HAL_QSPI_Receive_DMA  (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
00553
00554 /* QSPI status flag polling mode */
00555 HAL_StatusTypeDef     HAL_QSPI_AutoPolling   (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
00556 HAL_StatusTypeDef     HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);
00557
00558 /* QSPI memory-mapped mode */
00559 HAL_StatusTypeDef     HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
00560
00561 /* Callback functions in non-blocking modes ***********************************/
00562 void                  HAL_QSPI_ErrorCallback        (QSPI_HandleTypeDef *hqspi);
00563 void                  HAL_QSPI_AbortCpltCallback    (QSPI_HandleTypeDef *hqspi);
00564 void                  HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
00565
00566 /* QSPI indirect mode */
00567 void                  HAL_QSPI_CmdCpltCallback      (QSPI_HandleTypeDef *hqspi);
00568 void                  HAL_QSPI_RxCpltCallback       (QSPI_HandleTypeDef *hqspi);
00569 void                  HAL_QSPI_TxCpltCallback       (QSPI_HandleTypeDef *hqspi);
00570 void                  HAL_QSPI_RxHalfCpltCallback   (QSPI_HandleTypeDef *hqspi);
00571 void                  HAL_QSPI_TxHalfCpltCallback   (QSPI_HandleTypeDef *hqspi);
00572
00573 /* QSPI status flag polling mode */
00574 void                  HAL_QSPI_StatusMatchCallback  (QSPI_HandleTypeDef *hqspi);
00575
00576 /* QSPI memory-mapped mode */
00577 void                  HAL_QSPI_TimeOutCallback      (QSPI_HandleTypeDef *hqspi);
00578
00579 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
00580 /* QSPI callback registering/unregistering */
00581 HAL_StatusTypeDef     HAL_QSPI_RegisterCallback     (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback);
00582 HAL_StatusTypeDef     HAL_QSPI_UnRegisterCallback   (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId);
00583 #endif
00584 /**
00585   * @}
00586   */
00587
00588 /** @addtogroup QSPI_Exported_Functions_Group3
00589   * @{
00590   */
00591 /* Peripheral Control and State functions  ************************************/
00592 HAL_QSPI_StateTypeDef HAL_QSPI_GetState        (QSPI_HandleTypeDef *hqspi);
00593 uint32_t              HAL_QSPI_GetError        (QSPI_HandleTypeDef *hqspi);
00594 HAL_StatusTypeDef     HAL_QSPI_Abort           (QSPI_HandleTypeDef *hqspi);
00595 HAL_StatusTypeDef     HAL_QSPI_Abort_IT        (QSPI_HandleTypeDef *hqspi);
00596 void                  HAL_QSPI_SetTimeout      (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
00597 HAL_StatusTypeDef     HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
00598 uint32_t              HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
00599 /**
00600   * @}
00601   */
00602
00603 /**
00604   * @}
00605   */
00606 /* End of exported functions -------------------------------------------------*/
00607
00608 /* Private macros ------------------------------------------------------------*/
00609 /** @defgroup QSPI_Private_Macros QSPI Private Macros
00610   * @{
00611   */
00612 #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU)
00613
00614 #define IS_QSPI_FIFO_THRESHOLD(THR)        (((THR) > 0U) && ((THR) <= 16U))
00615
00616 #define IS_QSPI_SSHIFT(SSHIFT)             (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
00617                                             ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
00618
00619 #define IS_QSPI_FLASH_SIZE(FSIZE)          (((FSIZE) <= 31U))
00620
00621 #define IS_QSPI_CS_HIGH_TIME(CSHTIME)      (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
00622                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
00623                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
00624                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
00625                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
00626                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
00627                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
00628                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
00629
00630 #define IS_QSPI_CLOCK_MODE(CLKMODE)        (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
00631                                             ((CLKMODE) == QSPI_CLOCK_MODE_3))
00632
00633 #define IS_QSPI_INSTRUCTION(INSTRUCTION)   ((INSTRUCTION) <= 0xFFU)
00634
00635 #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE)    (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS)  || \
00636                                             ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
00637                                             ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
00638                                             ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
00639
00640 #define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS)  || \
00641                                             ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
00642                                             ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
00643                                             ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
00644
00645 #define IS_QSPI_DUMMY_CYCLES(DCY)          ((DCY) <= 31U)
00646
00647 #define IS_QSPI_INSTRUCTION_MODE(MODE)     (((MODE) == QSPI_INSTRUCTION_NONE)    || \
00648                                             ((MODE) == QSPI_INSTRUCTION_1_LINE)  || \
00649                                             ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
00650                                             ((MODE) == QSPI_INSTRUCTION_4_LINES))
00651
00652 #define IS_QSPI_ADDRESS_MODE(MODE)         (((MODE) == QSPI_ADDRESS_NONE)    || \
00653                                             ((MODE) == QSPI_ADDRESS_1_LINE)  || \
00654                                             ((MODE) == QSPI_ADDRESS_2_LINES) || \
00655                                             ((MODE) == QSPI_ADDRESS_4_LINES))
00656
00657 #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE)    || \
00658                                             ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE)  || \
00659                                             ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
00660                                             ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
00661
00662 #define IS_QSPI_DATA_MODE(MODE)            (((MODE) == QSPI_DATA_NONE)    || \
00663                                             ((MODE) == QSPI_DATA_1_LINE)  || \
00664                                             ((MODE) == QSPI_DATA_2_LINES) || \
00665                                             ((MODE) == QSPI_DATA_4_LINES))
00666
00667 #define IS_QSPI_DDR_MODE(DDR_MODE)         (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
00668                                             ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
00669
00670 #define IS_QSPI_SIOO_MODE(SIOO_MODE)       (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
00671                                             ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
00672
00673 #define IS_QSPI_INTERVAL(INTERVAL)         ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
00674
00675 #define IS_QSPI_STATUS_BYTES_SIZE(SIZE)    (((SIZE) >= 1U) && ((SIZE) <= 4U))
00676
00677 #define IS_QSPI_MATCH_MODE(MODE)           (((MODE) == QSPI_MATCH_MODE_AND) || \
00678                                             ((MODE) == QSPI_MATCH_MODE_OR))
00679
00680 #define IS_QSPI_AUTOMATIC_STOP(APMS)       (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
00681                                             ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
00682
00683 #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN)   (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
00684                                             ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
00685
00686 #define IS_QSPI_TIMEOUT_PERIOD(PERIOD)     ((PERIOD) <= 0xFFFFU)
00687 /**
00688 * @}
00689 */
00690 /* End of private macros -----------------------------------------------------*/
00691
00692 /**
00693   * @}
00694   */
00695
00696 /**
00697   * @}
00698   */
00699
00700 #endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */
00701
00702 #ifdef __cplusplus
00703 }
00704 #endif
00705
00706 #endif /* STM32WBxx_HAL_QSPI_H */
00707
00708 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:35 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_rcc.c Source File

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stm32wbxx_hal_rcc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_rcc.c
00004   * @author  MCD Application Team
00005   * @brief   RCC HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Reset and Clock Control (RCC) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + Peripheral Control functions
00010   *
00011   @verbatim
00012   ==============================================================================
00013
00014                       ##### RCC specific features #####
00015   ==============================================================================
00016     [..]
00017       After reset the device is running from Multiple Speed Internal oscillator
00018       (4 MHz) with Flash 0 wait state. Flash prefetch buffer, D-Cache
00019       and I-Cache are disabled, and all peripherals are off except internal
00020       SRAM, Flash and JTAG.
00021
00022       (+) There is no prescaler on High speed (AHBs) and Low speed (APBs) buses:
00023           all peripherals mapped on these buses are running at MSI speed.
00024       (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
00025       (+) All GPIOs are in analog mode, except the JTAG pins which
00026           are assigned to be used for debug purpose.
00027
00028     [..]
00029       Once the device started from reset, the user application has to:
00030       (+) Configure the clock source to be used to drive the System clock
00031           (if the application needs higher frequency/performance)
00032       (+) Configure the System clock frequency and Flash settings
00033       (+) Configure the AHB and APB buses prescalers
00034       (+) Enable the clock for the peripheral(s) to be used
00035       (+) Configure the clock source(s) for peripherals which clocks are not
00036           derived from the System clock (SAI1, RTC, ADC, USB/RNG, USART1, LPUART1, LPTIMx, I2Cx, SMPS)
00037
00038   @endverbatim
00039   ******************************************************************************
00040   * @attention
00041   *
00042   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00043   * All rights reserved.</center></h2>
00044   *
00045   * This software component is licensed by ST under BSD 3-Clause license,
00046   * the "License"; You may not use this file except in compliance with the
00047   * License. You may obtain a copy of the License at:
00048   *                        opensource.org/licenses/BSD-3-Clause
00049   *
00050   ******************************************************************************
00051   */
00052
00053 /* Includes ------------------------------------------------------------------*/
00054 #include "stm32wbxx_hal.h"
00055
00056 /** @addtogroup STM32WBxx_HAL_Driver
00057   * @{
00058   */
00059
00060 /** @defgroup RCC RCC
00061   * @brief RCC HAL module driver
00062   * @{
00063   */
00064
00065 #ifdef HAL_RCC_MODULE_ENABLED
00066
00067 /* Private typedef -----------------------------------------------------------*/
00068 /* Private define ------------------------------------------------------------*/
00069 /** @defgroup RCC_Private_Constants RCC Private Constants
00070  * @{
00071  */
00072 #define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
00073 #define HSI_TIMEOUT_VALUE          (2U)    /* 2 ms (minimum Tick + 1)   */
00074 #define MSI_TIMEOUT_VALUE          (2U)    /* 2 ms (minimum Tick + 1)   */
00075 #define LSI1_TIMEOUT_VALUE         (2U)    /* 2 ms (minimum Tick + 1)   */
00076 #define LSI2_TIMEOUT_VALUE         (3U)    /* to be adjusted with DS    */
00077 #define HSI48_TIMEOUT_VALUE        (2U)    /* 2 ms (minimum Tick + 1)   */
00078 #define PLL_TIMEOUT_VALUE          (2U)    /* 2 ms (minimum Tick + 1)   */
00079 #define PLLSAI1_TIMEOUT_VALUE      (2U)    /* 2 ms (minimum Tick + 1)   */
00080 #define PRESCALER_TIMEOUT_VALUE    (2U)    /* 2 ms (minimum Tick + 1)   */
00081 #define LATENCY_TIMEOUT_VALUE      (2U)    /* 2 ms (minimum Tick + 1)   */
00082 #define CLOCKSWITCH_TIMEOUT_VALUE  (5000U) /* 5 s                       */
00083
00084 #define PLLSOURCE_NONE             (0U)
00085 #define MEGA_HZ                     1000000U /* Division factor to convert Hz in Mhz */
00086 /**
00087   * @}
00088   */
00089
00090 /* Private macro -------------------------------------------------------------*/
00091 /** @defgroup RCC_Private_Macros RCC Private Macros
00092   * @{
00093   */
00094 #define __MCO1_CLK_ENABLE()   __HAL_RCC_GPIOA_CLK_ENABLE()
00095 #define MCO1_GPIO_PORT        GPIOA
00096 #define MCO1_PIN              GPIO_PIN_8
00097
00098 #define __MCO2_CLK_ENABLE()   __HAL_RCC_GPIOB_CLK_ENABLE()
00099 #define MCO2_GPIO_PORT        GPIOB
00100 #define MCO2_PIN              GPIO_PIN_6
00101
00102 #define __MCO3_CLK_ENABLE()   __HAL_RCC_GPIOA_CLK_ENABLE()
00103 #define MCO3_GPIO_PORT        GPIOA
00104 #define MCO3_PIN              GPIO_PIN_15
00105
00106 #define RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) \
00107             (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (uint32_t)(__HAL_RCC_PLLSOURCE__)))
00108
00109 #define __COUNTOF(_A_)   (sizeof(_A_) / sizeof(*(_A_)))
00110 /**
00111   * @}
00112   */
00113
00114 /* Private variables ---------------------------------------------------------*/
00115 /** @defgroup RCC_Private_Variables RCC Private Variables
00116   * @{
00117   */
00118
00119
00120 /**
00121   * @}
00122   */
00123
00124 /* Private function prototypes -----------------------------------------------*/
00125 /** @defgroup RCC_Private_Functions RCC Private Functions
00126   * @{
00127   */
00128 static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSI_Range);
00129 static HAL_StatusTypeDef RCC_SetFlashLatency(uint32_t Flash_ClkSrcFreq, uint32_t VCORE_Voltage);
00130 /**
00131   * @}
00132   */
00133
00134 /* Exported functions --------------------------------------------------------*/
00135
00136 /** @defgroup RCC_Exported_Functions RCC Exported Functions
00137   * @{
00138   */
00139
00140 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
00141   *  @brief    Initialization and Configuration functions
00142   *
00143   @verbatim
00144  ===============================================================================
00145            ##### Initialization and de-initialization functions #####
00146  ===============================================================================
00147     [..]
00148       This section provides functions allowing to configure the internal and external oscillators
00149       (HSE, HSI, LSE, MSI, LSI1, LSI2, PLL, CSS and MCO) and the System buses clocks (SYSCLK, HCLK1, HCLK2, HCLK4, PCLK1
00150        and PCLK2).
00151
00152     [..] Internal/external clock and PLL configuration
00153          (+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through
00154              the PLL as System clock source.
00155
00156          (+) MSI (Mutiple Speed Internal): Its frequency is software trimmable from 100KHZ to 48MHZ.
00157              It can be used to generate the clock for the USB FS (48 MHz).
00158              The number of flash wait states is automatically adjusted when MSI range is updated with
00159              @ref HAL_RCC_OscConfig() and the MSI is used as System clock source.
00160
00161          (+) LSI1/LSI2 (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC
00162              clock source.
00163
00164          (+) HSE (high-speed external): 32 MHz crystal oscillator used directly or
00165              through the PLL as System clock source. Can be used also optionally as RTC clock source.
00166
00167          (+) LSE (low-speed external): 32.768 KHz oscillator used optionally as RTC clock source
00168              or the RF system Auto-wakeup from Stop and Standby modes.
00169
00170          (+) PLL (clocked by HSI, HSE or MSI) providing up to three independent output clocks:
00171            (++) The first output is used to generate the high speed system clock (up to 64MHz).
00172            (++) The second output is used to generate the clock for the USB FS (48 MHz),
00173                 the random analog generator (<=48 MHz)
00174            (++) The third output is used to generate an accurate clock to achieve
00175                 high-quality audio performance on SAI interface.
00176
00177          (+) PLLSAI1 (clocked by HSI, HSE or MSI) providing up to three independent output clocks:
00178            (++) The first output is used to generate SAR ADC clock.
00179            (++) The second output is used to generate the clock for the USB FS (48 MHz),
00180                 the random analog generator (<=48 MHz).
00181            (++) The Third output is used to generate an accurate clock to achieve
00182                 high-quality audio performance on SAI interface.
00183
00184
00185          (+) CSS (Clock security system): once enabled, if a HSE clock failure occurs
00186             (HSE used directly or through PLL as System clock source), the System clock
00187              is automatically switched to MSI or the HSI oscillator (depending on the
00188              STOPWUCK configuration) and an interrupt is generated if enabled.
00189              The interrupt is linked to the CPU1 and CPU2 NMI (Non-Maskable Interrupt) exception vector.
00190
00191          (+) LSECSS: once enabled, if a LSE clock failure occurs, the LSE
00192              clock is no longer supplied to the RTC but no hardware action is made to the registers. If the
00193              MSI was in PLL-mode, this mode is disabled.
00194              In Standby mode a wakeup is generated. In other modes an interrupt can be sent to wakeup
00195              the software
00196
00197          (+) MCO (microcontroller clock output): used to output MSI, LSI1, LSI2, HSI, LSE, HSE (before and
00198              after stabilization), SYSCLK, HSI48 or main PLL clock (through a configurable prescaler) on PA8, PB6 & PA15 pins.
00199
00200     [..] System, AHB and APB buses clocks configuration
00201          (+) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI,
00202              HSE and main PLL.
00203              The AHB clock (HCLK1) is derived from System clock through configurable
00204              prescaler and used to clock the CPU, memory and peripherals mapped
00205              on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
00206              from AHB clock through configurable prescalers and used to clock
00207              the peripherals mapped on these buses. You can use
00208              "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
00209              The AHB4 clock (HCLK4) is derived from System clock through configurable
00210              prescaler and used to clock the FLASH
00211
00212          -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
00213
00214            (+@) SAI: the SAI clock can be derived either from a specific PLL (PLLSAI1) or (PLLSYS) or
00215                 from an external clock mapped on the SAI_CKIN pin.
00216                 You have to use @ref HAL_RCCEx_PeriphCLKConfig() function to configure this clock.
00217            (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
00218                 divided by 32.
00219                 You have to use @ref __HAL_RCC_RTC_ENABLE() and @ref HAL_RCCEx_PeriphCLKConfig() function
00220                 to configure this clock.
00221            (+@) USB FS and RNG: USB FS requires a frequency equal to 48 MHz
00222                 to work correctly, while RNG peripherals requires a frequency
00223                 equal or lower than to 48 MHz. This clock is derived of the main PLL or PLLSAI1
00224                 through PLLQ divider. You have to enable the peripheral clock and use
00225                 @ref HAL_RCCEx_PeriphCLKConfig() function to configure this clock.
00226            (+@) IWDG clock which is always the LSI clock.
00227
00228
00229          (+) The maximum frequency of the SYSCLK, HCLK1, HCLK4, PCLK1 and PCLK2 is 64 MHz.
00230              The maximum frequency of the HCLK2 is 32 MHz.
00231              The clock source frequency should be adapted depending on the device voltage range
00232              as listed in the Reference Manual "Clock source frequency versus voltage scaling" chapter.
00233
00234   @endverbatim
00235
00236            Table 1. HCLK4 clock frequency.
00237            +-------------------------------------------------------+
00238            | Latency         |    HCLK4 clock frequency (MHz)      |
00239            |                 |-------------------------------------|
00240            |                 | voltage range 1  | voltage range 2  |
00241            |                 |      1.2 V       |     1.0 V        |
00242            |-----------------|------------------|------------------|
00243            |0WS(1 CPU cycles)|   HCLK4 <= 18    |   HCLK4 <= 6     |
00244            |-----------------|------------------|------------------|
00245            |1WS(2 CPU cycles)|   HCLK4 <= 36    |   HCLK4 <= 12    |
00246            |-----------------|------------------|------------------|
00247            |2WS(3 CPU cycles)|   HCLK4 <= 54    |   HCLK4 <= 16    |
00248            |-----------------|------------------|------------------|
00249            |3WS(4 CPU cycles)|   HCLK4 <= 64    |   HCLK4 <= n.a.  |
00250            |-----------------|------------------|------------------|
00251
00252   * @{
00253   */
00254
00255 /**
00256   * @brief  Reset the RCC clock configuration to the default reset state.
00257   * @note   The default reset state of the clock configuration is given below:
00258   *            - MSI ON and used as system clock source
00259   *            - HSE, HSI, PLL, PLLSAI1
00260   *            - HCLK1, HCLK2, HCLK4, PCLK1 and PCLK2 prescalers set to 1.
00261   *            - CSS, MCO OFF
00262   *            - All interrupts disabled
00263   * @note   This function doesn't modify the configuration of the
00264   *            - Peripheral clocks
00265   *            - LSI, LSE and RTC clocks
00266   * @retval HAL status
00267   */
00268 HAL_StatusTypeDef HAL_RCC_DeInit(void)
00269 {
00270   uint32_t tickstart;
00271
00272   /* Get Start Tick*/
00273   tickstart = HAL_GetTick();
00274
00275   /* Set MSION bit */
00276   LL_RCC_MSI_Enable();
00277
00278   /* Wait till MSI is ready */
00279   while (LL_RCC_MSI_IsReady() == 0U)
00280   {
00281     if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
00282     {
00283       return HAL_TIMEOUT;
00284     }
00285   }
00286
00287   /* Set MSIRANGE default value */
00288   LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_6);
00289
00290   /* Set MSITRIM bits to the reset value*/
00291   LL_RCC_MSI_SetCalibTrimming(0);
00292
00293   /* Set HSITRIM bits to the reset value*/
00294   LL_RCC_HSI_SetCalibTrimming(0x40U);
00295
00296   /* Get Start Tick*/
00297   tickstart = HAL_GetTick();
00298
00299   /* Reset CFGR register (MSI is selected as system clock source) */
00300   CLEAR_REG(RCC->CFGR);
00301
00302   /* Wait till MSI is ready */
00303   while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != 0U)
00304   {
00305     if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
00306     {
00307       return HAL_TIMEOUT;
00308     }
00309   }
00310
00311   /* Reset HSION, HSIKERON, HSIASFS, HSEON, PLLON, PLLSAI11ON, HSEPRE bits */
00312 #if defined(SAI1)
00313   CLEAR_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSIKERON | RCC_CR_HSIASFS | RCC_CR_HSEON | RCC_CR_HSEPRE | RCC_CR_PLLON | RCC_CR_PLLSAI1ON);
00314 #else
00315   CLEAR_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSIKERON | RCC_CR_HSIASFS | RCC_CR_HSEON | RCC_CR_HSEPRE | RCC_CR_PLLON);
00316 #endif
00317
00318   /* Reset HSEBYP bit once HSE is OFF */
00319   LL_RCC_HSE_DisableBypass();
00320
00321   /* Get Start Tick*/
00322   tickstart = HAL_GetTick();
00323
00324   /* Wait till PLL is ready */
00325   while (LL_RCC_PLL_IsReady() != 0U)
00326   {
00327     if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
00328     {
00329       return HAL_TIMEOUT;
00330     }
00331   }
00332
00333   /* once PLL is OFF, reset PLLCFGR register to default value */
00334   WRITE_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLR_0 | RCC_PLLCFGR_PLLQ_0 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLN_0);
00335
00336 #if defined(SAI1)
00337   /* Get Start Tick*/
00338   tickstart = HAL_GetTick();
00339
00340   /* Wait till PLL is ready */
00341   while (LL_RCC_PLLSAI1_IsReady() != 0U)
00342   {
00343     if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
00344     {
00345       return HAL_TIMEOUT;
00346     }
00347   }
00348   /* once PLLSAI1 is OFF, reset PLLSAI1CFGR register to default value */
00349   WRITE_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLR_0 | RCC_PLLSAI1CFGR_PLLQ_0 | RCC_PLLSAI1CFGR_PLLP_1 | RCC_PLLSAI1CFGR_PLLN_0);
00350 #endif
00351
00352   /* Disable all interrupts */
00353   CLEAR_REG(RCC->CIER);
00354
00355   /* Clear all interrupt flags */
00356   WRITE_REG(RCC->CICR, 0xFFFFFFFFU);
00357
00358   /* EXTCFGR reset*/
00359   LL_RCC_WriteReg(EXTCFGR, 0x00030000U);
00360
00361   /* Update the SystemCoreClock global variable */
00362   SystemCoreClock = MSI_VALUE;
00363
00364   /* Adapt Systick interrupt period */
00365   if (HAL_InitTick(uwTickPrio) != HAL_OK)
00366   {
00367     return HAL_ERROR;
00368   }
00369   else
00370   {
00371     return HAL_OK;
00372   }
00373 }
00374
00375 /**
00376   * @brief  Initialize the RCC Oscillators according to the specified parameters in the
00377   *         @ref RCC_OscInitTypeDef.
00378   * @param  RCC_OscInitStruct  pointer to a @ref RCC_OscInitTypeDef structure that
00379   *         contains the configuration information for the RCC Oscillators.
00380   * @note   The PLL is not disabled when used as system clock.
00381   * @retval HAL status
00382   */
00383 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
00384 {
00385   uint32_t tickstart;
00386
00387   /* Check Null pointer */
00388   if (RCC_OscInitStruct == NULL)
00389   {
00390     return HAL_ERROR;
00391   }
00392
00393   /* Check the parameters */
00394   assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
00395
00396   /*----------------------------- MSI Configuration --------------------------*/
00397   if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
00398   {
00399     /* Check the parameters */
00400     assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
00401     assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
00402     assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
00403
00404     /* When the MSI is used as system clock it will not be disabled */
00405     const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
00406     const uint32_t temp_plloscsrc = __HAL_RCC_GET_PLL_OSCSOURCE();
00407     if ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_MSI) ||
00408         ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_plloscsrc == RCC_PLLSOURCE_MSI)))
00409     {
00410       if ((LL_RCC_MSI_IsReady() != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
00411       {
00412         return HAL_ERROR;
00413       }
00414       /* Otherwise, just the calibration and MSI range change are allowed */
00415       else
00416       {
00417         /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
00418            must be correctly programmed according to the frequency of the AHB4 clock
00419            and the supply voltage of the device. */
00420         if (RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
00421         {
00422           /* First increase number of wait states update if necessary */
00423           if (RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
00424           {
00425             return HAL_ERROR;
00426           }
00427
00428           /* Selects the Multiple Speed oscillator (MSI) clock range .*/
00429           __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
00430           /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
00431           __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
00432         }
00433         else
00434         {
00435           /* Else, keep current flash latency while decreasing applies */
00436           /* Selects the Multiple Speed oscillator (MSI) clock range .*/
00437           __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
00438           /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
00439           __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
00440
00441           /* Decrease number of wait states update if necessary */
00442           if (RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
00443           {
00444             return HAL_ERROR;
00445           }
00446         }
00447
00448         /* Update the SystemCoreClock global variable */
00449         SystemCoreClockUpdate();
00450         if (HAL_InitTick(uwTickPrio) != HAL_OK)
00451         {
00452           return HAL_ERROR;
00453         }
00454       }
00455     }
00456     else
00457     {
00458       /* Check the MSI State */
00459       if (RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
00460       {
00461         /* Enable the Internal High Speed oscillator (MSI). */
00462         __HAL_RCC_MSI_ENABLE();
00463
00464         /* Get timeout */
00465         tickstart = HAL_GetTick();
00466
00467         /* Wait till MSI is ready */
00468         while (LL_RCC_MSI_IsReady() == 0U)
00469         {
00470           if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
00471           {
00472             return HAL_TIMEOUT;
00473           }
00474         }
00475         /* Selects the Multiple Speed oscillator (MSI) clock range .*/
00476         __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
00477         /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
00478         __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
00479
00480       }
00481       else
00482       {
00483         /* Disable the Internal High Speed oscillator (MSI). */
00484         __HAL_RCC_MSI_DISABLE();
00485
00486         /* Get timeout */
00487         tickstart = HAL_GetTick();
00488
00489         /* Wait till MSI is disabled */
00490         while (LL_RCC_MSI_IsReady() != 0U)
00491         {
00492           if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
00493           {
00494             return HAL_TIMEOUT;
00495           }
00496         }
00497       }
00498     }
00499   }
00500   /*------------------------------- HSE Configuration ------------------------*/
00501   if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
00502   {
00503     /* Check the parameters */
00504     assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
00505
00506     /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
00507     const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
00508     const uint32_t temp_plloscsrc = __HAL_RCC_GET_PLL_OSCSOURCE();
00509     if ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE) ||
00510         ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_plloscsrc == RCC_PLLSOURCE_HSE)))
00511     {
00512       if ((LL_RCC_HSE_IsReady() != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
00513       {
00514         return HAL_ERROR;
00515       }
00516     }
00517     else
00518     {
00519       /* Set the new HSE configuration ---------------------------------------*/
00520       __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
00521
00522       /* Check the HSE State */
00523       if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
00524       {
00525         /* Get Start Tick*/
00526         tickstart = HAL_GetTick();
00527
00528         /* Wait till HSE is ready */
00529         while (LL_RCC_HSE_IsReady() == 0U)
00530         {
00531           if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
00532           {
00533             return HAL_TIMEOUT;
00534           }
00535         }
00536       }
00537       else
00538       {
00539         /* Get Start Tick*/
00540         tickstart = HAL_GetTick();
00541
00542         /* Wait till HSE is disabled */
00543         while (LL_RCC_HSE_IsReady() != 0U)
00544         {
00545           if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
00546           {
00547             return HAL_TIMEOUT;
00548           }
00549         }
00550       }
00551     }
00552   }
00553   /*----------------------------- HSI Configuration --------------------------*/
00554   if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
00555   {
00556     /* Check the parameters */
00557     assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
00558     assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
00559
00560     /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
00561     const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
00562     const uint32_t temp_plloscsrc = __HAL_RCC_GET_PLL_OSCSOURCE();
00563     if ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI) ||
00564         ((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_plloscsrc == RCC_PLLSOURCE_HSI)))
00565     {
00566       /* When HSI is used as system clock it will not be disabled */
00567       if ((LL_RCC_HSI_IsReady() != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
00568       {
00569         return HAL_ERROR;
00570       }
00571       /* Otherwise, just the calibration is allowed */
00572       else
00573       {
00574         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
00575         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
00576       }
00577     }
00578     else
00579     {
00580       /* Check the HSI State */
00581       if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
00582       {
00583         /* Enable the Internal High Speed oscillator (HSI). */
00584         __HAL_RCC_HSI_ENABLE();
00585
00586         /* Get Start Tick*/
00587         tickstart = HAL_GetTick();
00588
00589         /* Wait till HSI is ready */
00590         while (LL_RCC_HSI_IsReady() == 0U)
00591         {
00592           if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
00593           {
00594             return HAL_TIMEOUT;
00595           }
00596         }
00597
00598         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
00599         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
00600       }
00601       else
00602       {
00603         /* Disable the Internal High Speed oscillator (HSI). */
00604         __HAL_RCC_HSI_DISABLE();
00605
00606         /* Get Start Tick*/
00607         tickstart = HAL_GetTick();
00608
00609         /* Wait till HSI is disabled */
00610         while (LL_RCC_HSI_IsReady() != 0U)
00611         {
00612           if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
00613           {
00614             return HAL_TIMEOUT;
00615           }
00616         }
00617       }
00618     }
00619   }
00620   /*------------------------------ LSI Configuration (LSI1 or LSI2) -------------------------*/
00621
00622   if ((((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI1) == RCC_OSCILLATORTYPE_LSI1) || \
00623       (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI2) == RCC_OSCILLATORTYPE_LSI2))
00624   {
00625     /* Check the parameters */
00626     assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
00627
00628     /* Check the LSI State */
00629     if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
00630     {
00631       /*------------------------------ LSI2 selected by default (when Switch ON) -------------------------*/
00632       if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI2) == RCC_OSCILLATORTYPE_LSI2)
00633       {
00634         assert_param(IS_RCC_LSI2_CALIBRATION_VALUE(RCC_OscInitStruct->LSI2CalibrationValue));
00635
00636         /* 1. Check LSI1 state and enable if required */
00637         if (LL_RCC_LSI1_IsReady() == 0U)
00638         {
00639           /* This is required to enable LSI1 before enabling LSI2 */
00640           __HAL_RCC_LSI1_ENABLE();
00641
00642           /* Get Start Tick*/
00643           tickstart = HAL_GetTick();
00644
00645           /* Wait till LSI1 is ready */
00646           while (LL_RCC_LSI1_IsReady() == 0U)
00647           {
00648             if ((HAL_GetTick() - tickstart) > LSI1_TIMEOUT_VALUE)
00649             {
00650               return HAL_TIMEOUT;
00651             }
00652           }
00653         }
00654
00655         /* 2. Enable the Internal Low Speed oscillator (LSI2) and set trimming value */
00656         __HAL_RCC_LSI2_ENABLE();
00657
00658         /* Get Start Tick*/
00659         tickstart = HAL_GetTick();
00660
00661         /* Wait till LSI2 is ready */
00662         while (LL_RCC_LSI2_IsReady() == 0U)
00663         {
00664           if ((HAL_GetTick() - tickstart) > LSI2_TIMEOUT_VALUE)
00665           {
00666             return HAL_TIMEOUT;
00667           }
00668         }
00669         /* Adjusts the Internal Low Spee oscillator (LSI2) calibration value */
00670         __HAL_RCC_LSI2_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->LSI2CalibrationValue);
00671
00672         /* 3. Disable LSI1 */
00673
00674         /* LSI1 was initially not enable, require to disable it */
00675         __HAL_RCC_LSI1_DISABLE();
00676
00677         /* Get Start Tick*/
00678         tickstart = HAL_GetTick();
00679
00680         /* Wait till LSI1 is disabled */
00681         while (LL_RCC_LSI1_IsReady() != 0U)
00682         {
00683           if ((HAL_GetTick() - tickstart) > LSI1_TIMEOUT_VALUE)
00684           {
00685             return HAL_TIMEOUT;
00686           }
00687         }
00688       }
00689       else
00690       {
00691         /*------------------------------ LSI1 selected (only if LSI2 OFF)-------------------------*/
00692
00693         /* 1. Enable the Internal Low Speed oscillator (LSI1). */
00694         __HAL_RCC_LSI1_ENABLE();
00695
00696         /* Get Start Tick*/
00697         tickstart = HAL_GetTick();
00698
00699         /* Wait till LSI1 is ready */
00700         while (LL_RCC_LSI1_IsReady() == 0U)
00701         {
00702           if ((HAL_GetTick() - tickstart) > LSI1_TIMEOUT_VALUE)
00703           {
00704             return HAL_TIMEOUT;
00705           }
00706         }
00707         /*2. Switch OFF LSI2*/
00708
00709         /* Disable the Internal Low Speed oscillator (LSI2). */
00710         __HAL_RCC_LSI2_DISABLE();
00711
00712         /* Wait till LSI2 is disabled */
00713         while (LL_RCC_LSI2_IsReady() != 0U)
00714         {
00715           if ((HAL_GetTick() - tickstart) > LSI2_TIMEOUT_VALUE)
00716           {
00717             return HAL_TIMEOUT;
00718           }
00719         }
00720       }
00721     }
00722     else
00723     {
00724
00725       /* Disable the Internal Low Speed oscillator (LSI2). */
00726       __HAL_RCC_LSI2_DISABLE();
00727
00728       /* Get Start Tick*/
00729       tickstart = HAL_GetTick();
00730
00731       /* Wait till LSI2 is disabled */
00732       while (LL_RCC_LSI2_IsReady() != 0U)
00733       {
00734         if ((HAL_GetTick() - tickstart) > LSI2_TIMEOUT_VALUE)
00735         {
00736           return HAL_TIMEOUT;
00737         }
00738       }
00739
00740       /* Disable the Internal Low Speed oscillator (LSI1). */
00741       __HAL_RCC_LSI1_DISABLE();
00742
00743       /* Get Start Tick*/
00744       tickstart = HAL_GetTick();
00745
00746       /* Wait till LSI1 is disabled */
00747       while (LL_RCC_LSI1_IsReady() != 0U)
00748       {
00749         if ((HAL_GetTick() - tickstart) > LSI1_TIMEOUT_VALUE)
00750         {
00751           return HAL_TIMEOUT;
00752         }
00753       }
00754     }
00755   }
00756   /*------------------------------ LSE Configuration -------------------------*/
00757   if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
00758   {
00759
00760     /* Check the parameters */
00761     assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
00762
00763     /* Update LSE configuration in Backup Domain control register    */
00764     /* Requires to enable write access to Backup Domain of necessary */
00765
00766     if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
00767     {
00768       /* Enable write access to Backup domain */
00769       HAL_PWR_EnableBkUpAccess();
00770
00771       /* Wait for Backup domain Write protection disable */
00772       tickstart = HAL_GetTick();
00773
00774       while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
00775       {
00776         if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
00777         {
00778           return HAL_TIMEOUT;
00779         }
00780       }
00781     }
00782
00783     /* Set the new LSE configuration -----------------------------------------*/
00784     __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
00785
00786     /* Check the LSE State */
00787     if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
00788     {
00789       /* Get Start Tick*/
00790       tickstart = HAL_GetTick();
00791
00792       /* Wait till LSE is ready */
00793       while (LL_RCC_LSE_IsReady() == 0U)
00794       {
00795         if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
00796         {
00797           return HAL_TIMEOUT;
00798         }
00799       }
00800     }
00801     else
00802     {
00803       /* Get Start Tick*/
00804       tickstart = HAL_GetTick();
00805
00806       /* Wait till LSE is disabled */
00807       while (LL_RCC_LSE_IsReady() != 0U)
00808       {
00809         if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
00810         {
00811           return HAL_TIMEOUT;
00812         }
00813       }
00814     }
00815
00816   }
00817   /*------------------------------ HSI48 Configuration -----------------------*/
00818   if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
00819   {
00820     /* Check the parameters */
00821     assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
00822
00823     /* Check the LSI State */
00824     if (RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
00825     {
00826       /* Enable the Internal Low Speed oscillator (HSI48). */
00827       __HAL_RCC_HSI48_ENABLE();
00828
00829       /* Get Start Tick*/
00830       tickstart = HAL_GetTick();
00831
00832       /* Wait till HSI48 is ready */
00833       while (LL_RCC_HSI48_IsReady() == 0U)
00834       {
00835         if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
00836         {
00837           return HAL_TIMEOUT;
00838         }
00839       }
00840     }
00841     else
00842     {
00843       /* Disable the Internal Low Speed oscillator (HSI48). */
00844       __HAL_RCC_HSI48_DISABLE();
00845
00846       /* Get Start Tick*/
00847       tickstart = HAL_GetTick();
00848
00849       /* Wait till HSI48 is disabled */
00850       while (LL_RCC_HSI48_IsReady() != 0U)
00851       {
00852         if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
00853         {
00854           return HAL_TIMEOUT;
00855         }
00856       }
00857     }
00858   }
00859   /*-------------------------------- PLL Configuration -----------------------*/
00860   /* Check the parameters */
00861   assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
00862
00863   if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
00864   {
00865     /* Check if the PLL is used as system clock or not */
00866     if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
00867     {
00868       if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
00869       {
00870         /* Check the parameters */
00871         assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
00872         assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
00873         assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
00874         assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
00875         assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
00876         assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
00877
00878         /* Disable the main PLL. */
00879         __HAL_RCC_PLL_DISABLE();
00880
00881         /* Get Start Tick*/
00882         tickstart = HAL_GetTick();
00883
00884         /* Wait till PLL is ready */
00885         while (LL_RCC_PLL_IsReady() != 0U)
00886         {
00887           if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
00888           {
00889             return HAL_TIMEOUT;
00890           }
00891         }
00892
00893         /* Configure the main PLL clock source, multiplication and division factors. */
00894         __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
00895                              RCC_OscInitStruct->PLL.PLLM,
00896                              RCC_OscInitStruct->PLL.PLLN,
00897                              RCC_OscInitStruct->PLL.PLLP,
00898                              RCC_OscInitStruct->PLL.PLLQ,
00899                              RCC_OscInitStruct->PLL.PLLR);
00900
00901         /* Enable the main PLL. */
00902         __HAL_RCC_PLL_ENABLE();
00903
00904         /* Enable PLL System Clock output. */
00905         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
00906
00907         /* Get Start Tick*/
00908         tickstart = HAL_GetTick();
00909
00910         /* Wait till PLL is ready */
00911         while (LL_RCC_PLL_IsReady() == 0U)
00912         {
00913           if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
00914           {
00915             return HAL_TIMEOUT;
00916           }
00917         }
00918       }
00919       else
00920       {
00921         /* Disable the main PLL. */
00922         __HAL_RCC_PLL_DISABLE();
00923
00924         /* Disable all PLL outputs to save power */
00925         MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSOURCE_NONE);
00926
00927 #if defined(SAI1) && defined(USB)
00928         __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_USBCLK | RCC_PLL_SAI1CLK);
00929 #else
00930         __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK);
00931 #endif
00932
00933         /* Get Start Tick*/
00934         tickstart = HAL_GetTick();
00935
00936         /* Wait till PLL is disabled */
00937         while (LL_RCC_PLL_IsReady() != 0U)
00938         {
00939           if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
00940           {
00941             return HAL_TIMEOUT;
00942           }
00943         }
00944       }
00945     }
00946     else
00947     {
00948       /* Check if there is a request to disable the PLL used as System clock source */
00949       if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
00950       {
00951         return HAL_ERROR;
00952       }
00953       else
00954       {
00955         /* Do not return HAL_ERROR if request repeats the current configuration */
00956         uint32_t pllcfgr = RCC->PLLCFGR;
00957
00958         if ((READ_BIT(pllcfgr, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
00959             (READ_BIT(pllcfgr, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
00960             ((READ_BIT(pllcfgr, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) != RCC_OscInitStruct->PLL.PLLN) ||
00961             (READ_BIT(pllcfgr, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) ||
00962             (READ_BIT(pllcfgr, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) ||
00963             (READ_BIT(pllcfgr, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR))
00964         {
00965           return HAL_ERROR;
00966         }
00967       }
00968     }
00969   }
00970   return HAL_OK;
00971 }
00972
00973
00974 /**
00975   * @brief  Initialize the CPU, AHB and APB buses clocks according to the specified
00976   *         parameters in the RCC_ClkInitStruct.
00977   * @param  RCC_ClkInitStruct  pointer to a @ref RCC_ClkInitTypeDef structure that
00978   *         contains the configuration information for the RCC peripheral.
00979   * @param  FLatency  FLASH Latency
00980   *          This parameter can be one of the following values:
00981   *            @arg FLASH_LATENCY_0   FLASH 0 Latency cycle
00982   *            @arg FLASH_LATENCY_1   FLASH 1 Latency cycle
00983   *            @arg FLASH_LATENCY_2   FLASH 2 Latency cycle
00984   *            @arg FLASH_LATENCY_3   FLASH 3 Latency cycle
00985   *
00986   * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
00987   *         and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function
00988   *
00989   * @note   The MSI is used by default as system clock source after
00990   *         startup from Reset, wake-up from STANDBY mode. After restart from Reset,
00991   *         the MSI frequency is set to its default value 4 MHz.
00992   *
00993   * @note   The HSI can be selected as system clock source after
00994   *         from STOP modes or in case of failure of the HSE used directly or indirectly
00995   *         as system clock (if the Clock Security System CSS is enabled).
00996   *
00997   * @note   A switch from one clock source to another occurs only if the target
00998   *         clock source is ready (clock stable after startup delay or PLL locked).
00999   *         If a clock source which is not yet ready is selected, the switch will
01000   *         occur when the clock source is ready.
01001   *
01002   * @note   You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
01003   *         currently used as system clock source.
01004   *
01005   * @note   Depending on the device voltage range, the software has to set correctly
01006   *         HPRE[3:0] bits to ensure that HCLK1 not exceed the maximum allowed frequency
01007   *         (for more details refer to section above "Initialization/de-initialization functions")
01008   * @retval None
01009   */
01010 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
01011 {
01012   uint32_t tickstart;
01013
01014   /* Check Null pointer */
01015   if (RCC_ClkInitStruct == NULL)
01016   {
01017     return HAL_ERROR;
01018   }
01019
01020   /* Check the parameters */
01021   assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
01022   assert_param(IS_FLASH_LATENCY(FLatency));
01023
01024   /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
01025     must be correctly programmed according to the frequency of the FLASH clock
01026     (HCLK4) and the supply voltage of the device. */
01027
01028   /* Increasing the number of wait states because of higher CPU frequency */
01029   if (FLatency > __HAL_FLASH_GET_LATENCY())
01030   {
01031     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
01032     __HAL_FLASH_SET_LATENCY(FLatency);
01033
01034     /* Get Start Tick*/
01035     tickstart = HAL_GetTick();
01036
01037     /* Check that the new number of wait states is taken into account to access the Flash
01038        memory by reading the FLASH_ACR register */
01039     while (__HAL_FLASH_GET_LATENCY() != FLatency)
01040     {
01041       if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE)
01042       {
01043         return HAL_TIMEOUT;
01044       }
01045     }
01046   }
01047
01048   /*-------------------------- HCLK1 Configuration --------------------------*/
01049   if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
01050   {
01051     assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLKDivider));
01052     LL_RCC_SetAHBPrescaler(RCC_ClkInitStruct->AHBCLKDivider);
01053
01054     /* HCLK1 prescaler flag when value applied */
01055     tickstart = HAL_GetTick();
01056     while (LL_RCC_IsActiveFlag_HPRE() == 0U)
01057     {
01058       if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE)
01059       {
01060         return HAL_TIMEOUT;
01061       }
01062     }
01063   }
01064
01065   /*-------------------------- HCLK2 Configuration --------------------------*/
01066   if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK2) == RCC_CLOCKTYPE_HCLK2)
01067   {
01068     assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLK2Divider));
01069     LL_C2_RCC_SetAHBPrescaler(RCC_ClkInitStruct->AHBCLK2Divider);
01070
01071     /* HCLK2 prescaler flag when value applied */
01072     tickstart = HAL_GetTick();
01073     while (LL_RCC_IsActiveFlag_C2HPRE() == 0U)
01074     {
01075       if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE)
01076       {
01077         return HAL_TIMEOUT;
01078       }
01079     }
01080   }
01081   /*-------------------------- HCLK4 Configuration --------------------------*/
01082   if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK4) == RCC_CLOCKTYPE_HCLK4)
01083   {
01084     assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLK4Divider));
01085     LL_RCC_SetAHB4Prescaler(RCC_ClkInitStruct->AHBCLK4Divider);
01086
01087     /* AHB shared prescaler flag when value applied */
01088     tickstart = HAL_GetTick();
01089     while (LL_RCC_IsActiveFlag_SHDHPRE() == 0U)
01090     {
01091       if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE)
01092       {
01093         return HAL_TIMEOUT;
01094       }
01095     }
01096   }
01097
01098   /*-------------------------- PCLK1 Configuration ---------------------------*/
01099   if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
01100   {
01101     assert_param(IS_RCC_PCLKx(RCC_ClkInitStruct->APB1CLKDivider));
01102     LL_RCC_SetAPB1Prescaler(RCC_ClkInitStruct->APB1CLKDivider);
01103
01104     /* APB1 prescaler flag when value applied */
01105     tickstart = HAL_GetTick();
01106     while (LL_RCC_IsActiveFlag_PPRE1() == 0U)
01107     {
01108       if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE)
01109       {
01110         return HAL_TIMEOUT;
01111       }
01112     }
01113   }
01114
01115   /*-------------------------- PCLK2 Configuration ---------------------------*/
01116   if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
01117   {
01118     assert_param(IS_RCC_PCLKx(RCC_ClkInitStruct->APB2CLKDivider));
01119     LL_RCC_SetAPB2Prescaler((RCC_ClkInitStruct->APB2CLKDivider) << 3U);
01120
01121     /* APB2 prescaler flag when value applied */
01122     tickstart = HAL_GetTick();
01123     while (LL_RCC_IsActiveFlag_PPRE2() == 0U)
01124     {
01125       if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE)
01126       {
01127         return HAL_TIMEOUT;
01128       }
01129     }
01130   }
01131
01132   /*------------------------- SYSCLK Configuration ---------------------------*/
01133   if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
01134   {
01135     assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
01136
01137     /* HSE is selected as System Clock Source */
01138     if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
01139     {
01140       /* Check the HSE ready flag */
01141       if (LL_RCC_HSE_IsReady() == 0U)
01142       {
01143         return HAL_ERROR;
01144       }
01145     }
01146     /* PLL is selected as System Clock Source */
01147     else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
01148     {
01149       /* Check the PLL ready flag */
01150       if (LL_RCC_PLL_IsReady() == 0U)
01151       {
01152         return HAL_ERROR;
01153       }
01154     }
01155     /* MSI is selected as System Clock Source */
01156     else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
01157     {
01158       /* Check the MSI ready flag */
01159       if (LL_RCC_MSI_IsReady() == 0U)
01160       {
01161         return HAL_ERROR;
01162       }
01163     }
01164     /* HSI is selected as System Clock Source */
01165     else
01166     {
01167       /* Check the HSI ready flag */
01168       if (LL_RCC_HSI_IsReady() == 0U)
01169       {
01170         return HAL_ERROR;
01171       }
01172
01173     }
01174
01175     /* apply system clock switch */
01176     LL_RCC_SetSysClkSource(RCC_ClkInitStruct->SYSCLKSource);
01177
01178     /* Get Start Tick*/
01179     tickstart = HAL_GetTick();
01180
01181     /* check system clock source switch status */
01182     while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
01183     {
01184       if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
01185       {
01186         return HAL_TIMEOUT;
01187       }
01188     }
01189   }
01190
01191   /* Decreasing the number of wait states because of lower CPU frequency */
01192   if (FLatency < __HAL_FLASH_GET_LATENCY())
01193   {
01194     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
01195     __HAL_FLASH_SET_LATENCY(FLatency);
01196
01197     /* Get Start Tick*/
01198     tickstart = HAL_GetTick();
01199
01200     /* Check that the new number of wait states is taken into account to access the Flash
01201     memory by reading the FLASH_ACR register */
01202     while (__HAL_FLASH_GET_LATENCY() != FLatency)
01203     {
01204       if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE)
01205       {
01206         return HAL_TIMEOUT;
01207       }
01208     }
01209   }
01210
01211   /*---------------------------------------------------------------------------*/
01212
01213   /* Update the SystemCoreClock global variable */
01214   SystemCoreClockUpdate();
01215   /* Configure the source of time base considering new system clocks settings*/
01216   return HAL_InitTick(HAL_GetTickPrio());
01217 }
01218
01219 /**
01220   * @}
01221   */
01222
01223 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
01224  *  @brief   RCC clocks control functions
01225  *
01226 @verbatim
01227  ===============================================================================
01228                       ##### Peripheral Control functions #####
01229  ===============================================================================
01230     [..]
01231     This subsection provides a set of functions allowing to:
01232
01233     (+) Ouput clock to MCO pin.
01234     (+) Retrieve current clock frequencies.
01235     (+) Enable the Clock Security System.
01236
01237 @endverbatim
01238   * @{
01239   */
01240
01241 /**
01242   * @brief  Select the clock source to output on MCO1 pin(PA8) or MC02 pin (PB6) or MCO3 pin (PA15).
01243   * @note   PA8, PB6 or PA15 should be configured in alternate function mode.
01244   * @param  RCC_MCOx  specifies the output direction for the clock source.
01245   *            @arg @ref RCC_MCO1  Clock source to output on MCO1 pin(PA8)
01246   *            @arg @ref RCC_MCO2  Clock source to output on MCO2 pin(PB6)
01247   *            @arg @ref RCC_MCO3  Clock source to output on MCO3 pin(PA15)
01248   * @param  RCC_MCOSource  specifies the clock source to output.
01249   *          This parameter can be one of the following values:
01250   *            @arg @ref RCC_MCO1SOURCE_NOCLOCK  MCO output disabled, no clock on MCO
01251   *            @arg @ref RCC_MCO1SOURCE_SYSCLK  system  clock selected as MCO source
01252   *            @arg @ref RCC_MCO1SOURCE_MSI  MSI clock selected as MCO source
01253   *            @arg @ref RCC_MCO1SOURCE_HSI  HSI clock selected as MCO source
01254   *            @arg @ref RCC_MCO1SOURCE_HSE  HSE clock selected as MCO sourcee
01255   *            @arg @ref RCC_MCO1SOURCE_PLLCLK  main PLL clock selected as MCO source
01256   *            @arg @ref RCC_MCO1SOURCE_LSI1  LSI1 clock selected as MCO source
01257   *            @arg @ref RCC_MCO1SOURCE_LSI2  LSI2 clock selected as MCO source
01258   *            @arg @ref RCC_MCO1SOURCE_LSE  LSE clock selected as MCO source
01259   *            @arg @ref RCC_MCO1SOURCE_HSI48  HSI48 clock selected as MCO source for devices with HSI48
01260   *            @arg @ref RCC_MCO1SOURCE_HSE_BEFORE_STAB  HSE clock before stabilization selected as MCO source
01261   * @param  RCC_MCODiv  specifies the MCO prescaler.
01262   *          This parameter can be one of the following values:
01263   *            @arg @ref RCC_MCODIV_1  no division applied to MCO clock
01264   *            @arg @ref RCC_MCODIV_2  division by 2 applied to MCO clock
01265   *            @arg @ref RCC_MCODIV_4  division by 4 applied to MCO clock
01266   *            @arg @ref RCC_MCODIV_8  division by 8 applied to MCO clock
01267   *            @arg @ref RCC_MCODIV_16  division by 16 applied to MCO clock
01268   * @retval None
01269   */
01270 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
01271 {
01272   GPIO_InitTypeDef GPIO_InitStruct;
01273
01274   /* Check the parameters */
01275   assert_param(IS_RCC_MCO(RCC_MCOx));
01276   assert_param(IS_RCC_MCODIV(RCC_MCODiv));
01277   assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
01278
01279   /* Common GPIO init parameters */
01280   GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
01281   GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_VERY_HIGH;
01282   GPIO_InitStruct.Pull      = GPIO_NOPULL;
01283
01284   /* RCC_MCO1 */
01285   if (RCC_MCOx == RCC_MCO1)
01286   {
01287     /* MCO1 Clock Enable */
01288     __MCO1_CLK_ENABLE();
01289     /* Configue the MCO1 pin in alternate function mode */
01290     GPIO_InitStruct.Pin       = MCO1_PIN;
01291     GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
01292     HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
01293
01294   }
01295   else if (RCC_MCOx == RCC_MCO2)
01296   {
01297     /* MCO2 Clock Enable */
01298     __MCO2_CLK_ENABLE();
01299     /* Configue the MCO2 pin in alternate function mode */
01300     GPIO_InitStruct.Pin       = MCO2_PIN;
01301     GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
01302     HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
01303
01304   }
01305   else
01306   {
01307     /* MCO3 Clock Enable */
01308     __MCO3_CLK_ENABLE();
01309     /* Configue the MCO3 pin in alternate function mode */
01310     GPIO_InitStruct.Pin       = MCO3_PIN;
01311     GPIO_InitStruct.Alternate = GPIO_AF6_MCO;
01312     HAL_GPIO_Init(MCO3_GPIO_PORT, &GPIO_InitStruct);
01313   }
01314
01315   /* Mask MCOSEL[] and MCOPRE[] bits then set MCO clock source and prescaler */
01316   LL_RCC_ConfigMCO(RCC_MCOSource, RCC_MCODiv);
01317 }
01318
01319 /**
01320   * @brief  Return the SYSCLK frequency.
01321   *
01322   * @note   The system  computed by this function is not the real
01323   *         frequency in the chip. It is calculated based on the predefined
01324   *         constant and the selected clock source:
01325   * @note     If SYSCLK source is MSI, function returns values based on MSI range
01326   * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
01327   * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
01328   * @note     If SYSCLK source is PLL, function returns values based on HSE_VALUE(**),
01329   *           HSI_VALUE(*) or MSI Value multiplied/divided by the PLL factors.
01330   * @note     (*) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
01331   *               16 MHz) but the real value may vary depending on the variations
01332   *               in voltage and temperature.
01333   * @note     (**) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
01334   *                32 MHz), user has to ensure that HSE_VALUE is same as the real
01335   *                frequency of the crystal used. Otherwise, this function may
01336   *                have wrong result.
01337   *
01338   * @note   The result of this function could be not correct when using fractional
01339   *         value for HSE crystal.
01340   *
01341   * @note   This function can be used by the user application to compute the
01342   *         baudrate for the communication peripherals or configure other parameters.
01343   *
01344   * @note   Each time SYSCLK changes, this function must be called to update the
01345   *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
01346   *
01347   *
01348   * @retval SYSCLK frequency
01349   */
01350 uint32_t HAL_RCC_GetSysClockFreq(void)
01351 {
01352   uint32_t pllsource;
01353   uint32_t sysclockfreq, pllinputfreq;
01354   const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
01355
01356   if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_MSI)
01357   {
01358     /* Retrieve MSI frequency range in HZ*/
01359     /* MSI used as system clock source */
01360     sysclockfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
01361   }
01362   else if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI)
01363   {
01364     /* HSI used as system clock source */
01365     sysclockfreq = HSI_VALUE;
01366   }
01367   else if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE)
01368   {
01369     /* HSE used as system clock source */
01370     if (LL_RCC_HSE_IsEnabledDiv2() == 1U)
01371     {
01372       sysclockfreq = HSE_VALUE / 2U;
01373     }
01374     else
01375     {
01376       sysclockfreq = HSE_VALUE;
01377     }
01378   }
01379   else
01380   {
01381     /* PLL used as system clock  source */
01382     pllsource = LL_RCC_PLL_GetMainSource();
01383     switch (pllsource)
01384     {
01385       case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
01386         pllinputfreq = HSI_VALUE;
01387         break;
01388       case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
01389         if (LL_RCC_HSE_IsEnabledDiv2() == 1U)
01390         {
01391           pllinputfreq = HSE_VALUE / 2U;
01392         }
01393         else
01394         {
01395           pllinputfreq = HSE_VALUE;
01396         }
01397         break;
01398       case RCC_PLLSOURCE_MSI:  /* MSI used as PLL clock source */
01399       default:
01400         pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
01401         break;
01402     }
01403     sysclockfreq = __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
01404   }
01405
01406   return sysclockfreq;
01407 }
01408
01409 /**
01410   * @brief  Return the HCLK frequency.
01411   * @retval HCLK frequency in Hz
01412   */
01413 uint32_t HAL_RCC_GetHCLKFreq(void)
01414 {
01415   /* Get SysClock and Compute HCLK1 frequency ---------------------------*/
01416   return ((uint32_t)(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetAHBPrescaler())));
01417 }
01418
01419 /**
01420   * @brief  Return the HCLK2 frequency.
01421   * @retval HCLK2 frequency in Hz
01422   */
01423 uint32_t HAL_RCC_GetHCLK2Freq(void)
01424 {
01425   /* Get SysClock and Compute HCLK2 frequency ---------------------------*/
01426   return ((uint32_t)(__LL_RCC_CALC_HCLK2_FREQ(HAL_RCC_GetSysClockFreq(), LL_C2_RCC_GetAHBPrescaler())));
01427 }
01428
01429 /**
01430   * @brief  Return the HCLK4 frequency.
01431   * @retval HCLK4 frequency in Hz
01432   */
01433 uint32_t HAL_RCC_GetHCLK4Freq(void)
01434 {
01435   /* Get SysClock and Compute AHB4 frequency ---------------------------*/
01436   return ((uint32_t)(__LL_RCC_CALC_HCLK4_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetAHB4Prescaler())));
01437 }
01438
01439 /**
01440   * @brief  Return the PCLK1 frequency.
01441   * @note   Each time PCLK1 changes, this function must be called to update the
01442   *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
01443   * @retval PCLK1 frequency in Hz
01444   */
01445 uint32_t HAL_RCC_GetPCLK1Freq(void)
01446 {
01447   /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
01448   return ((uint32_t)(__LL_RCC_CALC_PCLK1_FREQ(HAL_RCC_GetHCLKFreq(), LL_RCC_GetAPB1Prescaler())));
01449 }
01450
01451 /**
01452   * @brief  Return the PCLK2 frequency.
01453   * @note   Each time PCLK2 changes, this function must be called to update the
01454   *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
01455   * @retval PCLK2 frequency in Hz
01456   */
01457 uint32_t HAL_RCC_GetPCLK2Freq(void)
01458 {
01459   /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
01460   return ((uint32_t)(__LL_RCC_CALC_PCLK2_FREQ(HAL_RCC_GetHCLKFreq(), LL_RCC_GetAPB2Prescaler())));
01461 }
01462
01463 /**
01464   * @brief  Configure the RCC_OscInitStruct according to the internal
01465   *         RCC configuration registers.
01466   * @param  RCC_OscInitStruct  pointer to an RCC_OscInitTypeDef structure that
01467   *         will be configured.
01468   * @retval None
01469   */
01470 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
01471 {
01472   /* Check the parameters */
01473   assert_param(RCC_OscInitStruct != (void *)NULL);
01474
01475   /* Set all possible values for the Oscillator type parameter ---------------*/
01476   RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \
01477                                       RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI1 | RCC_OSCILLATORTYPE_LSI2 | RCC_OSCILLATORTYPE_HSI48;
01478
01479
01480   /* Get the HSE configuration -----------------------------------------------*/
01481   if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
01482   {
01483     RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
01484   }
01485   else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
01486   {
01487     RCC_OscInitStruct->HSEState = RCC_HSE_ON;
01488   }
01489   else
01490   {
01491     RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
01492   }
01493
01494   /* Get the MSI configuration -----------------------------------------------*/
01495   if ((RCC->CR & RCC_CR_MSION) == RCC_CR_MSION)
01496   {
01497     RCC_OscInitStruct->MSIState = RCC_MSI_ON;
01498   }
01499   else
01500   {
01501     RCC_OscInitStruct->MSIState = RCC_MSI_OFF;
01502   }
01503   RCC_OscInitStruct->MSICalibrationValue  = LL_RCC_MSI_GetCalibTrimming();
01504   RCC_OscInitStruct->MSIClockRange        = LL_RCC_MSI_GetRange();
01505
01506   /* Get the HSI configuration -----------------------------------------------*/
01507   if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
01508   {
01509     RCC_OscInitStruct->HSIState = RCC_HSI_ON;
01510   }
01511   else
01512   {
01513     RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
01514   }
01515
01516   RCC_OscInitStruct->HSICalibrationValue = LL_RCC_HSI_GetCalibTrimming();
01517
01518   /* Get the LSE configuration -----------------------------------------------*/
01519   if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
01520   {
01521     RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
01522   }
01523   else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
01524   {
01525     RCC_OscInitStruct->LSEState = RCC_LSE_ON;
01526   }
01527   else
01528   {
01529     RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
01530   }
01531
01532   /* Get the LSI configuration -----------------------------------------------*/
01533   const uint32_t temp_lsi1on = (RCC->CSR & RCC_CSR_LSI1ON);
01534   const uint32_t temp_lsi2on = (RCC->CSR & RCC_CSR_LSI2ON);
01535   if ((temp_lsi1on == RCC_CSR_LSI1ON) || (temp_lsi2on == RCC_CSR_LSI2ON))
01536   {
01537     RCC_OscInitStruct->LSIState = RCC_LSI_ON;
01538   }
01539   else
01540   {
01541     RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
01542   }
01543
01544   /* Get the HSI48 configuration ---------------------------------------------*/
01545   if ((RCC->CRRCR & RCC_CRRCR_HSI48ON) == RCC_CRRCR_HSI48ON)
01546   {
01547     RCC_OscInitStruct->HSI48State = RCC_HSI48_ON;
01548   }
01549   else
01550   {
01551     RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;
01552   }
01553
01554
01555   /* Get the PLL configuration -----------------------------------------------*/
01556   if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON)
01557   {
01558     RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
01559   }
01560   else
01561   {
01562     RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
01563   }
01564   RCC_OscInitStruct->PLL.PLLSource = LL_RCC_PLL_GetMainSource();
01565   RCC_OscInitStruct->PLL.PLLM      = LL_RCC_PLL_GetDivider();
01566   RCC_OscInitStruct->PLL.PLLN      = LL_RCC_PLL_GetN();
01567   RCC_OscInitStruct->PLL.PLLP      = LL_RCC_PLL_GetP();
01568   RCC_OscInitStruct->PLL.PLLQ      = LL_RCC_PLL_GetQ();
01569   RCC_OscInitStruct->PLL.PLLR      = LL_RCC_PLL_GetR();
01570 }
01571
01572 /**
01573   * @brief  Configure the RCC_ClkInitStruct according to the internal
01574   *         RCC configuration registers.
01575   * @param  RCC_ClkInitStruct Pointer to a @ref RCC_ClkInitTypeDef structure that
01576   *                           will be configured.
01577   * @param  pFLatency         Pointer on the Flash Latency.
01578   * @retval None
01579   */
01580 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
01581 {
01582   /* Check the parameters */
01583   assert_param(RCC_ClkInitStruct != (void *)NULL);
01584   assert_param(pFLatency != (void *)NULL);
01585
01586   /* Set all possible values for the Clock type parameter --------------------*/
01587   RCC_ClkInitStruct->ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 |  \
01588                                   RCC_CLOCKTYPE_HCLK2 | RCC_CLOCKTYPE_HCLK4);
01589
01590   /* Get the SYSCLK configuration --------------------------------------------*/
01591   RCC_ClkInitStruct->SYSCLKSource = LL_RCC_GetSysClkSource();
01592
01593   /* Get the HCLK configuration ----------------------------------------------*/
01594   RCC_ClkInitStruct->AHBCLKDivider = LL_RCC_GetAHBPrescaler();
01595
01596   /* Get the APB1 configuration ----------------------------------------------*/
01597   RCC_ClkInitStruct->APB1CLKDivider = LL_RCC_GetAPB1Prescaler();
01598
01599   /* Get the APB2 configuration ----------------------------------------------*/
01600   RCC_ClkInitStruct->APB2CLKDivider = LL_RCC_GetAPB2Prescaler();
01601
01602   /* Get the AHBCLK2Divider configuration ------------------------------------*/
01603   RCC_ClkInitStruct->AHBCLK2Divider = LL_C2_RCC_GetAHBPrescaler();
01604
01605   /* Get the AHBCLK4Divider configuration ------------------------------------*/
01606   RCC_ClkInitStruct->AHBCLK4Divider = LL_RCC_GetAHB4Prescaler();
01607
01608   /* Get the Flash Wait State (Latency) configuration ------------------------*/
01609   *pFLatency = __HAL_FLASH_GET_LATENCY();
01610 }
01611
01612 /**
01613   * @brief  Enable the Clock Security System.
01614   * @note   If a failure is detected on the HSE oscillator clock, this oscillator
01615   *         is automatically disabled and an interrupt is generated to inform the
01616   *         software about the failure (Clock Security System Interrupt, CSSI),
01617   *         allowing the MCU to perform rescue operations. The CSSI is linked to
01618   *         CPU1 and CPU2 NMI (Non-Maskable Interrupt) exception vector.
01619   * @note   The Clock Security System can only be cleared by reset.
01620   * @retval None
01621   */
01622 void HAL_RCC_EnableCSS(void)
01623 {
01624   LL_RCC_HSE_EnableCSS();
01625 }
01626
01627 /**
01628   * @brief Handle the RCC HSE Clock Security System interrupt request.
01629   * @note  This API should be called under the NMI_Handler().
01630   * @retval None
01631   */
01632 void HAL_RCC_NMI_IRQHandler(void)
01633 {
01634   /* Check RCC CSSF interrupt flag  */
01635   if (__HAL_RCC_GET_IT(RCC_IT_HSECSS))
01636   {
01637     /* RCC Clock Security System interrupt user callback */
01638     HAL_RCC_CSSCallback();
01639
01640     /* Clear RCC CSS pending bit */
01641     __HAL_RCC_CLEAR_IT(RCC_IT_HSECSS);
01642   }
01643 }
01644
01645 /**
01646   * @brief Handle the RCC HSE Clock Security System interrupt callback.
01647   * @retval none
01648   */
01649 __weak void HAL_RCC_CSSCallback(void)
01650 {
01651   /* NOTE : This function should not be modified, when the callback is needed,
01652             the @ref HAL_RCC_CSSCallback should be implemented in the user file
01653    */
01654 }
01655
01656 /**
01657   * @}
01658   */
01659
01660 /**
01661   * @}
01662   */
01663
01664 /* Private function prototypes -----------------------------------------------*/
01665 /** @addtogroup RCC_Private_Functions
01666   * @{
01667   */
01668
01669
01670 /**
01671   * @brief  Update number of Flash wait states in line with MSI range and current
01672             voltage range.
01673   * @param  MSI_Range  MSI range value from @ref RCC_MSIRANGE_0 to @ref RCC_MSIRANGE_11
01674   * @retval HAL status
01675   */
01676 static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSI_Range)
01677 {
01678   uint32_t flash_clksrcfreq, msifreq;
01679
01680   /* Check the parameters */
01681   assert_param(IS_RCC_MSI_CLOCK_RANGE(MSI_Range));
01682
01683   /* MSI frequency range in Hz */
01684   if (MSI_Range > RCC_MSIRANGE_11)
01685   {
01686     msifreq = __LL_RCC_CALC_MSI_FREQ(RCC_MSIRANGE_11);
01687   }
01688   else
01689   {
01690     msifreq = __LL_RCC_CALC_MSI_FREQ(MSI_Range);
01691   }
01692
01693   flash_clksrcfreq = __LL_RCC_CALC_HCLK4_FREQ(msifreq, LL_RCC_GetAHB4Prescaler());
01694
01695 #if defined(PWR_CR1_VOS)
01696   return RCC_SetFlashLatency((flash_clksrcfreq / MEGA_HZ), HAL_PWREx_GetVoltageRange());
01697 #else
01698   return RCC_SetFlashLatency((flash_clksrcfreq / MEGA_HZ), PWR_REGULATOR_VOLTAGE_SCALE1);
01699 #endif
01700 }
01701
01702
01703 /**
01704   * @brief  Update number of Flash wait states.
01705   * @param  Flash_ClkSrcFreq  Flash Clock Source (in MHz)
01706   * @param  VCORE_Voltage     Current Vcore voltage (PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2)
01707   * @retval HAL status
01708   */
01709 static HAL_StatusTypeDef RCC_SetFlashLatency(uint32_t Flash_ClkSrcFreq, uint32_t VCORE_Voltage)
01710 {
01711   /* Flash Clock source (HCLK4) range in MHz with a VCORE is range1 */
01712   const uint32_t FLASH_CLK_SRC_RANGE_VOS1[] = {18UL, 36UL, 54UL, 64UL};
01713 #if defined(PWR_CR1_VOS)
01714   /* Flash Clock source (HCLK4) range in MHz with a VCORE is range2 */
01715   const uint32_t FLASH_CLK_SRC_RANGE_VOS2[] = {6UL, 12UL, 16UL};
01716 #endif
01717   /* Flash Latency range */
01718   const uint32_t FLASH_LATENCY_RANGE[] = {FLASH_LATENCY_0, FLASH_LATENCY_1, FLASH_LATENCY_2, FLASH_LATENCY_3};
01719   uint32_t latency   = FLASH_LATENCY_0;  /* default value 0WS */
01720   uint32_t tickstart;
01721
01722 #if defined(PWR_CR1_VOS)
01723   if (VCORE_Voltage == PWR_REGULATOR_VOLTAGE_SCALE1)
01724   {
01725     for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS1); index++)
01726     {
01727       if (Flash_ClkSrcFreq <= FLASH_CLK_SRC_RANGE_VOS1[index])
01728       {
01729         latency = FLASH_LATENCY_RANGE[index];
01730         break;
01731       }
01732     }
01733   }
01734   else  /* PWR_REGULATOR_VOLTAGE_SCALE2 */
01735   {
01736     for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS2); index++)
01737     {
01738       if (Flash_ClkSrcFreq <= FLASH_CLK_SRC_RANGE_VOS2[index])
01739       {
01740         latency = FLASH_LATENCY_RANGE[index];
01741         break;
01742       }
01743     }
01744   }
01745 #else
01746   for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS1); index++)
01747   {
01748     if (Flash_ClkSrcFreq <= FLASH_CLK_SRC_RANGE_VOS1[index])
01749     {
01750       latency = FLASH_LATENCY_RANGE[index];
01751       break;
01752     }
01753   }
01754 #endif
01755
01756   __HAL_FLASH_SET_LATENCY(latency);
01757
01758   /* Get Start Tick*/
01759   tickstart = HAL_GetTick();
01760
01761   /* Check that the new number of wait states is taken into account to access the Flash
01762      memory by reading the FLASH_ACR register */
01763   while (__HAL_FLASH_GET_LATENCY() != latency)
01764   {
01765     if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE)
01766     {
01767       return HAL_TIMEOUT;
01768     }
01769   }
01770   return HAL_OK;
01771 }
01772 /**
01773   * @}
01774   */
01775
01776 #endif /* HAL_RCC_MODULE_ENABLED */
01777 /**
01778   * @}
01779   */
01780
01781 /**
01782   * @}
01783   */
01784
01785 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:35 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_rcc.h Source File

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stm32wbxx_hal_rcc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_rcc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of RCC HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_RCC_H
00022 #define STM32WBxx_HAL_RCC_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030 #include "stm32wbxx_ll_rcc.h"
00031 #include "stm32wbxx_ll_bus.h"
00032
00033
00034 /** @addtogroup STM32WBxx_HAL_Driver
00035   * @{
00036   */
00037
00038 /** @addtogroup RCC
00039   * @{
00040   */
00041
00042 /* Private constants ---------------------------------------------------------*/
00043 /** @addtogroup RCC_Private_Constants
00044   * @{
00045   */
00046 /* Defines used for Flags */
00047 #define CR_REG_INDEX              1U
00048 #define BDCR_REG_INDEX            2U
00049 #define CSR_REG_INDEX             3U
00050 #define CRRCR_REG_INDEX           4U
00051
00052 #define RCC_FLAG_MASK             0x1FU
00053 /**
00054   * @}
00055   */
00056
00057 /* Private macros ------------------------------------------------------------*/
00058 /** @addtogroup RCC_Private_Macros
00059   * @{
00060   */
00061
00062 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE)                             || \
00063                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE)  == RCC_OSCILLATORTYPE_HSE)  || \
00064                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI)  == RCC_OSCILLATORTYPE_HSI)  || \
00065                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \
00066                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI)  == RCC_OSCILLATORTYPE_MSI)  || \
00067                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI1) == RCC_OSCILLATORTYPE_LSI1) || \
00068                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI2) == RCC_OSCILLATORTYPE_LSI2) || \
00069                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE)  == RCC_OSCILLATORTYPE_LSE))
00070
00071
00072 #define IS_RCC_HSE(__HSE__)  (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
00073                               ((__HSE__) == RCC_HSE_BYPASS))
00074
00075 #define IS_RCC_LSE(__LSE__)  (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
00076                               ((__LSE__) == RCC_LSE_BYPASS))
00077
00078 #define IS_RCC_HSI(__HSI__)  (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
00079
00080 #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)127U)
00081
00082 #define IS_RCC_LSI(__LSI__)  (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
00083
00084 #define IS_RCC_LSI2_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)15U)
00085
00086
00087 #define IS_RCC_MSI(__MSI__)  (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))
00088
00089
00090 #define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)255U)
00091
00092
00093 #define IS_RCC_HSI48(__HSI48__)  (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))
00094
00095
00096 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \
00097                              ((__PLL__) == RCC_PLL_ON))
00098
00099 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \
00100                                       ((__SOURCE__) == RCC_PLLSOURCE_MSI)  || \
00101                                       ((__SOURCE__) == RCC_PLLSOURCE_HSI)  || \
00102                                       ((__SOURCE__) == RCC_PLLSOURCE_HSE))
00103
00104 #define IS_RCC_PLLM_VALUE(__VALUE__) (((__VALUE__) == RCC_PLLM_DIV1)  || \
00105                                       ((__VALUE__) == RCC_PLLM_DIV2)  || \
00106                                       ((__VALUE__) == RCC_PLLM_DIV3)  || \
00107                                       ((__VALUE__) == RCC_PLLM_DIV4)  || \
00108                                       ((__VALUE__) == RCC_PLLM_DIV5)  || \
00109                                       ((__VALUE__) == RCC_PLLM_DIV6)  || \
00110                                       ((__VALUE__) == RCC_PLLM_DIV7)  || \
00111                                       ((__VALUE__) == RCC_PLLM_DIV8))
00112
00113 #define IS_RCC_PLLN_VALUE(__VALUE__) ((6U <= (__VALUE__)) && ((__VALUE__) <= 127U))
00114
00115 #define IS_RCC_PLLP_VALUE(__VALUE__) ((RCC_PLLP_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLP_DIV32))
00116
00117 #define IS_RCC_PLLQ_VALUE(__VALUE__) ((RCC_PLLQ_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLQ_DIV8))
00118
00119 #define IS_RCC_PLLR_VALUE(__VALUE__) ((RCC_PLLR_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLR_DIV8))
00120
00121 #if defined(SAI1)
00122 #define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_ADCCLK) == RCC_PLLSAI1_ADCCLK) || \
00123                                                 (((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK)  || \
00124                                                 (((__VALUE__) & RCC_PLLSAI1_USBCLK) == RCC_PLLSAI1_USBCLK)) && \
00125                                                 (((__VALUE__) & ~(RCC_PLLSAI1_ADCCLK|RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_USBCLK)) == 0U))
00126 #endif
00127 #define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0)  || \
00128                                            ((__RANGE__) == RCC_MSIRANGE_1)  || \
00129                                            ((__RANGE__) == RCC_MSIRANGE_2)  || \
00130                                            ((__RANGE__) == RCC_MSIRANGE_3)  || \
00131                                            ((__RANGE__) == RCC_MSIRANGE_4)  || \
00132                                            ((__RANGE__) == RCC_MSIRANGE_5)  || \
00133                                            ((__RANGE__) == RCC_MSIRANGE_6)  || \
00134                                            ((__RANGE__) == RCC_MSIRANGE_7)  || \
00135                                            ((__RANGE__) == RCC_MSIRANGE_8)  || \
00136                                            ((__RANGE__) == RCC_MSIRANGE_9)  || \
00137                                            ((__RANGE__) == RCC_MSIRANGE_10) || \
00138                                            ((__RANGE__) == RCC_MSIRANGE_11))
00139
00140 #define IS_RCC_CLOCKTYPE(__CLK__)  ((1U <= (__CLK__)) && ((__CLK__) <= (RCC_CLOCKTYPE_SYSCLK | \
00141                                                                          RCC_CLOCKTYPE_HCLK  | \
00142                                                                          RCC_CLOCKTYPE_PCLK1 | \
00143                                                                          RCC_CLOCKTYPE_PCLK2 | \
00144                                                                          RCC_CLOCKTYPE_HCLK2 | \
00145                                                                          RCC_CLOCKTYPE_HCLK4)))
00146
00147 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \
00148                                          ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
00149                                          ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
00150                                          ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
00151
00152 #define IS_RCC_HCLKx(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1)   || ((__HCLK__) == RCC_SYSCLK_DIV2)   || ((__HCLK__) == RCC_SYSCLK_DIV3)   || \
00153                                ((__HCLK__) == RCC_SYSCLK_DIV4)   || ((__HCLK__) == RCC_SYSCLK_DIV5)   || ((__HCLK__) == RCC_SYSCLK_DIV6)   || \
00154                                ((__HCLK__) == RCC_SYSCLK_DIV8)   || ((__HCLK__) == RCC_SYSCLK_DIV10)  || ((__HCLK__) == RCC_SYSCLK_DIV16)  || \
00155                                ((__HCLK__) == RCC_SYSCLK_DIV32)  || ((__HCLK__) == RCC_SYSCLK_DIV64)  || ((__HCLK__) == RCC_SYSCLK_DIV128) || \
00156                                ((__HCLK__) == RCC_SYSCLK_DIV256) || ((__HCLK__) == RCC_SYSCLK_DIV512))
00157
00158 #define IS_RCC_PCLKx(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
00159                                 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
00160                                 ((__PCLK__) == RCC_HCLK_DIV16))
00161
00162 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \
00163                                          ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
00164                                          ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
00165                                          ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
00166
00167 #define IS_RCC_MCO(__MCOX__) ( ((__MCOX__) == RCC_MCO1) || ((__MCOX__) == RCC_MCO2) || ((__MCOX__) == RCC_MCO3) )
00168
00169 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
00170                                        ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
00171                                        ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
00172                                        ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
00173                                        ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
00174                                        ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
00175                                        ((__SOURCE__) == RCC_MCO1SOURCE_LSI1) || \
00176                                        ((__SOURCE__) == RCC_MCO1SOURCE_LSI2) || \
00177                                        ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \
00178                                        ((__SOURCE__) == RCC_MCO1SOURCE_HSI48))
00179
00180 #define IS_RCC_MCO2SOURCE(__SOURCE__) IS_RCC_MCO1SOURCE((__SOURCE__))
00181 #define IS_RCC_MCO3SOURCE(__SOURCE__) IS_RCC_MCO1SOURCE((__SOURCE__))
00182
00183
00184 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \
00185                                 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \
00186                                 ((__DIV__) == RCC_MCODIV_16))
00187
00188
00189
00190
00191 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW)        || \
00192                                      ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW)  || \
00193                                      ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \
00194                                      ((__DRIVE__) == RCC_LSEDRIVE_HIGH))
00195
00196 #define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \
00197                                              ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI))
00198 /**
00199   * @}
00200   */
00201
00202 /* Exported types ------------------------------------------------------------*/
00203 /** @defgroup RCC_Exported_Types RCC Exported Types
00204   * @{
00205   */
00206
00207
00208 /**
00209   * @brief  RCC PLL configuration structure definition
00210   */
00211 typedef struct
00212 {
00213   uint32_t PLLState;   /*!< The new state of the PLL.
00214                             This parameter must be a value of @ref RCC_PLL_Config                                 */
00215
00216   uint32_t PLLSource;  /*!< RCC_PLLSource: PLL entry clock source.
00217                             This parameter must be a value of @ref RCC_PLL_Clock_Source               */
00218
00219   uint32_t PLLM;       /*!< PLLM: Division factor for PLL VCO input clock.
00220                             This parameter must be a value of @ref RCC_PLLM_Clock_Divider             */
00221
00222   uint32_t PLLN;       /*!< PLLN: Multiplication factor for PLL VCO output clock.
00223                             This parameter must be a number between Min_Data = 6 and Max_Data = 127    */
00224
00225   uint32_t PLLP;       /*!< PLLP: Division factor for SAI & ADC clock.
00226                             This parameter must be a value of @ref RCC_PLLP_Clock_Divider             */
00227
00228   uint32_t PLLQ;       /*!< PLLQ: Division factor for  RNG and USB clocks.
00229                             This parameter must be a value of @ref RCC_PLLQ_Clock_Divider             */
00230
00231   uint32_t PLLR;       /*!< PLLR: Division for the main system clock.
00232                             User have to set the PLLR parameter correctly to not exceed max frequency 64MHZ.
00233                             This parameter must be a value of @ref RCC_PLLR_Clock_Divider             */
00234
00235 } RCC_PLLInitTypeDef;
00236
00237 /**
00238   * @brief  RCC Internal/External Oscillator (HSE, HSI, HSI48, MSI, LSE and LSI) configuration structure definition
00239   */
00240 typedef struct
00241 {
00242   uint32_t OscillatorType;       /*!< The oscillators to be configured.
00243                                       This parameter can be a combination of @ref RCC_Oscillator_Type             */
00244
00245   uint32_t HSEState;             /*!< The new state of the HSE.
00246                                       This parameter can be a value of @ref RCC_HSE_Config                        */
00247
00248   uint32_t LSEState;             /*!< The new state of the LSE.
00249                                       This parameter can be a value of @ref RCC_LSE_Config                        */
00250
00251   uint32_t HSIState;             /*!< The new state of the HSI.
00252                                       This parameter can be a value of @ref RCC_HSI_Config                        */
00253
00254   uint32_t HSICalibrationValue;  /*!< The calibration trimming value (default is @ref RCC_HSICALIBRATION_DEFAULT).*/
00255
00256   uint32_t LSIState;             /*!< The new state of the LSI.
00257                                       This parameter can be a value of @ref RCC_LSI_Config                        */
00258
00259   uint32_t LSI2CalibrationValue;  /*!< The LSI2 calibration trimming value .
00260                                     This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xF     */
00261
00262   uint32_t MSIState;             /*!< The new state of the MSI.
00263                                       This parameter can be a value of @ref RCC_MSI_Config */
00264
00265   uint32_t MSICalibrationValue;  /*!< The calibration trimming value (default is @ref RCC_MSICALIBRATION_DEFAULT).
00266                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
00267
00268   uint32_t MSIClockRange;        /*!< The MSI frequency range.
00269                                       This parameter can be a value of @ref RCC_MSI_Clock_Range                   */
00270
00271   uint32_t HSI48State;           /*!< The new state of the HSI48 .
00272                                       This parameter can be a value of @ref RCC_HSI48_Config                      */
00273
00274   RCC_PLLInitTypeDef PLL;        /*!< Main PLL structure parameters                                               */
00275
00276 } RCC_OscInitTypeDef;
00277
00278 /**
00279   * @brief  RCC System, AHB and APB buses clock configuration structure definition
00280   */
00281 typedef struct
00282 {
00283   uint32_t ClockType;             /*!< The clock to be configured.
00284                                        This parameter can be a combination of @ref RCC_System_Clock_Type      */
00285
00286   uint32_t SYSCLKSource;          /*!< The clock source used as system clock (SYSCLK).
00287                                        This parameter can be a value of @ref RCC_System_Clock_Source    */
00288
00289   uint32_t AHBCLKDivider;         /*!< The AHBx clock (HCLK1) divider. This clock is derived from the system clock (SYSCLK).
00290                                        This parameter can be a value of @ref RCC_AHBx_Clock_Source       */
00291
00292   uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
00293                                        This parameter can be a value of @ref RCC_APBx_Clock_Source      */
00294
00295   uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
00296                                        This parameter can be a value of @ref RCC_APBx_Clock_Source      */
00297
00298   uint32_t AHBCLK2Divider;        /*!< The AHB clock (HCLK2) divider. This clock is derived from the system clock (SYSCLK).
00299                                        This parameter can be a value of @ref RCC_AHBx_Clock_Source      */
00300
00301   uint32_t AHBCLK4Divider;        /*!< The AHB shared clock (HCLK4) divider. This clock is derived from the system clock (SYSCLK).
00302                                        This parameter can be a value of @ref RCC_AHBx_Clock_Source       */
00303
00304 } RCC_ClkInitTypeDef;
00305
00306 /**
00307   * @}
00308   */
00309
00310 /* Exported constants --------------------------------------------------------*/
00311 /** @defgroup RCC_Exported_Constants RCC Exported Constants
00312   * @{
00313   */
00314
00315 /** @defgroup RCC_Timeout_Value Timeout Values
00316   * @{
00317   */
00318 #define RCC_DBP_TIMEOUT_VALUE          2U                   /* 2 ms (minimum Tick + 1)  */
00319 #define RCC_LSE_TIMEOUT_VALUE          LSE_STARTUP_TIMEOUT  /* LSE timeout in ms        */
00320 /**
00321   * @}
00322   */
00323
00324 /** @defgroup RCC_Oscillator_Type Oscillator Type
00325   * @{
00326   */
00327 #define RCC_OSCILLATORTYPE_NONE        0x00000000U   /*!< Oscillator configuration unchanged  */
00328 #define RCC_OSCILLATORTYPE_HSE         0x00000001U   /*!< HSE to configure                    */
00329 #define RCC_OSCILLATORTYPE_HSI         0x00000002U   /*!< HSI to configure                    */
00330 #define RCC_OSCILLATORTYPE_LSE         0x00000004U   /*!< LSE to configure                    */
00331 #define RCC_OSCILLATORTYPE_LSI1        0x00000008U   /*!< LSI1 to configure                   */
00332 #define RCC_OSCILLATORTYPE_LSI2        0x00000010U   /*!< LSI2 to configure                   */
00333 #define RCC_OSCILLATORTYPE_MSI         0x00000020U   /*!< MSI to configure                    */
00334 #define RCC_OSCILLATORTYPE_HSI48       0x00000040U   /*!< HSI48 to configure                  */
00335 /**
00336   * @}
00337   */
00338
00339 /** @defgroup RCC_HSE_Config HSE Config
00340   * @{
00341   */
00342 #define RCC_HSE_OFF                    0x00000000U                                /*!< HSE clock deactivation               */
00343 #define RCC_HSE_ON                     RCC_CR_HSEON                               /*!< HSE clock activation                 */
00344 #define RCC_HSE_BYPASS                 ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock  */
00345 /**
00346   * @}
00347   */
00348
00349 /** @defgroup RCC_LSE_Config LSE Config
00350   * @{
00351   */
00352 #define RCC_LSE_OFF                    0x00000000U                                    /*!< LSE clock deactivation */
00353 #define RCC_LSE_ON                     RCC_BDCR_LSEON                                 /*!< LSE clock activation */
00354 #define RCC_LSE_BYPASS                 ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */
00355 /**
00356   * @}
00357   */
00358
00359 /** @defgroup RCC_HSI_Config HSI Config
00360   * @{
00361   */
00362 #define RCC_HSI_OFF                    0x00000000U  /*!< HSI clock deactivation */
00363 #define RCC_HSI_ON                     RCC_CR_HSION /*!< HSI clock activation */
00364
00365 #define RCC_HSICALIBRATION_DEFAULT     64U          /*!< Default HSI calibration trimming value */
00366 /**
00367   * @}
00368   */
00369
00370 /** @defgroup RCC_LSI_Config LSI Config
00371   * @{
00372   */
00373 #define RCC_LSI_OFF                    0x00000000U                        /*!< LSI clock deactivation */
00374 #define RCC_LSI_ON                     (RCC_CSR_LSI1ON | RCC_CSR_LSI2ON)  /*!< LSI1 or LSI2 clock activation */
00375 /**
00376   * @}
00377   */
00378
00379 /** @defgroup RCC_MSI_Config MSI Config
00380   * @{
00381   */
00382 #define RCC_MSI_OFF                    0x00000000U  /*!< MSI clock deactivation */
00383 #define RCC_MSI_ON                     RCC_CR_MSION /*!< MSI clock activation */
00384
00385 #define RCC_MSICALIBRATION_DEFAULT     0U   /*!< Default MSI calibration trimming value */
00386 /**
00387   * @}
00388   */
00389
00390
00391 /** @defgroup RCC_HSI48_Config HSI48 Config
00392   * @{
00393   */
00394 #define RCC_HSI48_OFF                  0x00000000U        /*!< HSI48 clock deactivation */
00395 #define RCC_HSI48_ON                   RCC_CRRCR_HSI48ON  /*!< HSI48 clock activation */
00396 /**
00397   * @}
00398   */
00399
00400
00401 /** @defgroup RCC_PLL_Config PLL Config
00402   * @{
00403   */
00404 #define RCC_PLL_NONE                   0x00000000U /*!< PLL configuration unchanged */
00405 #define RCC_PLL_OFF                    0x00000001U /*!< PLL deactivation */
00406 #define RCC_PLL_ON                     0x00000002U /*!< PLL activation */
00407 /**
00408   * @}
00409   */
00410
00411 /** @defgroup RCC_PLLM_Clock_Divider PLLM Clock Divider
00412   * @{
00413   */
00414 #define RCC_PLLM_DIV1                  LL_RCC_PLLM_DIV_1 /*!< PLLM division factor = 1  */
00415 #define RCC_PLLM_DIV2                  LL_RCC_PLLM_DIV_2 /*!< PLLM division factor = 2  */
00416 #define RCC_PLLM_DIV3                  LL_RCC_PLLM_DIV_3 /*!< PLLM division factor = 3  */
00417 #define RCC_PLLM_DIV4                  LL_RCC_PLLM_DIV_4 /*!< PLLM division factor = 4  */
00418 #define RCC_PLLM_DIV5                  LL_RCC_PLLM_DIV_5 /*!< PLLM division factor = 5  */
00419 #define RCC_PLLM_DIV6                  LL_RCC_PLLM_DIV_6 /*!< PLLM division factor = 6  */
00420 #define RCC_PLLM_DIV7                  LL_RCC_PLLM_DIV_7 /*!< PLLM division factor = 7  */
00421 #define RCC_PLLM_DIV8                  LL_RCC_PLLM_DIV_8 /*!< PLLM division factor = 8  */
00422 /**
00423   * @}
00424   */
00425
00426 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
00427   * @{
00428   */
00429 #define RCC_PLLP_DIV2                  LL_RCC_PLLP_DIV_2  /*!< PLLP division factor = 2  */
00430 #define RCC_PLLP_DIV3                  LL_RCC_PLLP_DIV_3  /*!< PLLP division factor = 3  */
00431 #define RCC_PLLP_DIV4                  LL_RCC_PLLP_DIV_4  /*!< PLLP division factor = 4  */
00432 #define RCC_PLLP_DIV5                  LL_RCC_PLLP_DIV_5  /*!< PLLP division factor = 5  */
00433 #define RCC_PLLP_DIV6                  LL_RCC_PLLP_DIV_6  /*!< PLLP division factor = 6  */
00434 #define RCC_PLLP_DIV7                  LL_RCC_PLLP_DIV_7  /*!< PLLP division factor = 7  */
00435 #define RCC_PLLP_DIV8                  LL_RCC_PLLP_DIV_8  /*!< PLLP division factor = 8  */
00436 #define RCC_PLLP_DIV9                  LL_RCC_PLLP_DIV_9  /*!< PLLP division factor = 9  */
00437 #define RCC_PLLP_DIV10                 LL_RCC_PLLP_DIV_10 /*!< PLLP division factor = 10 */
00438 #define RCC_PLLP_DIV11                 LL_RCC_PLLP_DIV_11 /*!< PLLP division factor = 11 */
00439 #define RCC_PLLP_DIV12                 LL_RCC_PLLP_DIV_12 /*!< PLLP division factor = 12 */
00440 #define RCC_PLLP_DIV13                 LL_RCC_PLLP_DIV_13 /*!< PLLP division factor = 13 */
00441 #define RCC_PLLP_DIV14                 LL_RCC_PLLP_DIV_14 /*!< PLLP division factor = 14 */
00442 #define RCC_PLLP_DIV15                 LL_RCC_PLLP_DIV_15 /*!< PLLP division factor = 15 */
00443 #define RCC_PLLP_DIV16                 LL_RCC_PLLP_DIV_16 /*!< PLLP division factor = 16 */
00444 #define RCC_PLLP_DIV17                 LL_RCC_PLLP_DIV_17 /*!< PLLP division factor = 17 */
00445 #define RCC_PLLP_DIV18                 LL_RCC_PLLP_DIV_18 /*!< PLLP division factor = 18 */
00446 #define RCC_PLLP_DIV19                 LL_RCC_PLLP_DIV_19 /*!< PLLP division factor = 19 */
00447 #define RCC_PLLP_DIV20                 LL_RCC_PLLP_DIV_20 /*!< PLLP division factor = 20 */
00448 #define RCC_PLLP_DIV21                 LL_RCC_PLLP_DIV_21 /*!< PLLP division factor = 21 */
00449 #define RCC_PLLP_DIV22                 LL_RCC_PLLP_DIV_22 /*!< PLLP division factor = 22 */
00450 #define RCC_PLLP_DIV23                 LL_RCC_PLLP_DIV_23 /*!< PLLP division factor = 23 */
00451 #define RCC_PLLP_DIV24                 LL_RCC_PLLP_DIV_24 /*!< PLLP division factor = 24 */
00452 #define RCC_PLLP_DIV25                 LL_RCC_PLLP_DIV_25 /*!< PLLP division factor = 25 */
00453 #define RCC_PLLP_DIV26                 LL_RCC_PLLP_DIV_26 /*!< PLLP division factor = 26 */
00454 #define RCC_PLLP_DIV27                 LL_RCC_PLLP_DIV_27 /*!< PLLP division factor = 27 */
00455 #define RCC_PLLP_DIV28                 LL_RCC_PLLP_DIV_28 /*!< PLLP division factor = 28 */
00456 #define RCC_PLLP_DIV29                 LL_RCC_PLLP_DIV_29 /*!< PLLP division factor = 29 */
00457 #define RCC_PLLP_DIV30                 LL_RCC_PLLP_DIV_30 /*!< PLLP division factor = 30 */
00458 #define RCC_PLLP_DIV31                 LL_RCC_PLLP_DIV_31 /*!< PLLP division factor = 31 */
00459 #define RCC_PLLP_DIV32                 LL_RCC_PLLP_DIV_32 /*!< PLLP division factor = 32 */
00460 /**
00461   * @}
00462   */
00463
00464 /** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider
00465   * @{
00466   */
00467 #define RCC_PLLQ_DIV2                  LL_RCC_PLLQ_DIV_2  /*!< PLLQ division factor = 2 */
00468 #define RCC_PLLQ_DIV3                  LL_RCC_PLLQ_DIV_3  /*!< PLLQ division factor = 3 */
00469 #define RCC_PLLQ_DIV4                  LL_RCC_PLLQ_DIV_4  /*!< PLLQ division factor = 4 */
00470 #define RCC_PLLQ_DIV5                  LL_RCC_PLLQ_DIV_5  /*!< PLLQ division factor = 5 */
00471 #define RCC_PLLQ_DIV6                  LL_RCC_PLLQ_DIV_6  /*!< PLLQ division factor = 6 */
00472 #define RCC_PLLQ_DIV7                  LL_RCC_PLLQ_DIV_7  /*!< PLLQ division factor = 7 */
00473 #define RCC_PLLQ_DIV8                  LL_RCC_PLLQ_DIV_8  /*!< PLLQ division factor = 8 */
00474 /**
00475   * @}
00476   */
00477
00478 /** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider
00479   * @{
00480   */
00481 #define RCC_PLLR_DIV2                  LL_RCC_PLLR_DIV_2  /*!< PLLR division factor = 2 */
00482 #define RCC_PLLR_DIV3                  LL_RCC_PLLR_DIV_3  /*!< PLLR division factor = 3 */
00483 #define RCC_PLLR_DIV4                  LL_RCC_PLLR_DIV_4  /*!< PLLR division factor = 4 */
00484 #define RCC_PLLR_DIV5                  LL_RCC_PLLR_DIV_5  /*!< PLLR division factor = 5 */
00485 #define RCC_PLLR_DIV6                  LL_RCC_PLLR_DIV_6  /*!< PLLR division factor = 6 */
00486 #define RCC_PLLR_DIV7                  LL_RCC_PLLR_DIV_7  /*!< PLLR division factor = 7 */
00487 #define RCC_PLLR_DIV8                  LL_RCC_PLLR_DIV_8  /*!< PLLR division factor = 8 */
00488 /**
00489   * @}
00490   */
00491
00492 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
00493   * @{
00494   */
00495 #define RCC_PLLSOURCE_NONE             LL_RCC_PLLSOURCE_NONE /*!< No clock selected as PLL entry clock source  */
00496 #define RCC_PLLSOURCE_MSI              LL_RCC_PLLSOURCE_MSI  /*!< MSI clock selected as PLL entry clock source */
00497 #define RCC_PLLSOURCE_HSI              LL_RCC_PLLSOURCE_HSI  /*!< HSI clock selected as PLL entry clock source */
00498 #define RCC_PLLSOURCE_HSE              LL_RCC_PLLSOURCE_HSE  /*!< HSE clock selected as PLL entry clock source */
00499 /**
00500   * @}
00501   */
00502
00503 /** @defgroup RCC_PLL_Clock_Output PLL Clock Output
00504   * @{
00505   */
00506 #define RCC_PLL_SYSCLK                 RCC_PLLCFGR_PLLREN      /*!< PLLCLK selection from main PLL */
00507 #define RCC_PLL_USBCLK                 RCC_PLLCFGR_PLLQEN      /*!< PLLUSBCLK selection from main PLL */
00508 #define RCC_PLL_RNGCLK                 RCC_PLLCFGR_PLLQEN      /*!< PLLRNGCLK selection from main PLL */
00509 #if defined(SAI1)
00510 #define RCC_PLL_SAI1CLK                RCC_PLLCFGR_PLLPEN      /*!< PLLSAI1CLK selection from main PLL */
00511 #endif
00512 #define RCC_PLL_ADCCLK                 RCC_PLLCFGR_PLLPEN      /*!< PLLADCCLK selection from main PLL */
00513 /**
00514   * @}
00515   */
00516
00517 #if defined(SAI1)
00518 /** @defgroup RCC_PLLSAI1_Clock_Output PLLSAI1 Clock Output
00519   * @{
00520   */
00521 #define RCC_PLLSAI1_ADCCLK             RCC_PLLSAI1CFGR_PLLREN        /*!< PLLADCCLK selection from PLLSAI1 */
00522 #define RCC_PLLSAI1_USBCLK             RCC_PLLSAI1CFGR_PLLQEN        /*!< USBCLK selection from PLLSAI1 */
00523 #define RCC_PLLSAI1_SAI1CLK            RCC_PLLSAI1CFGR_PLLPEN       /*!< PLLSAI1CLK selection from PLLSAI1 */
00524 /**
00525   * @}
00526   */
00527 #endif
00528
00529 /** @defgroup RCC_MSI_Clock_Range MSI Clock Range
00530   * @{
00531   */
00532 #define RCC_MSIRANGE_0                 LL_RCC_MSIRANGE_0  /*!< MSI = 100 KHz  */
00533 #define RCC_MSIRANGE_1                 LL_RCC_MSIRANGE_1  /*!< MSI = 200 KHz  */
00534 #define RCC_MSIRANGE_2                 LL_RCC_MSIRANGE_2  /*!< MSI = 400 KHz  */
00535 #define RCC_MSIRANGE_3                 LL_RCC_MSIRANGE_3  /*!< MSI = 800 KHz  */
00536 #define RCC_MSIRANGE_4                 LL_RCC_MSIRANGE_4  /*!< MSI = 1 MHz    */
00537 #define RCC_MSIRANGE_5                 LL_RCC_MSIRANGE_5  /*!< MSI = 2 MHz    */
00538 #define RCC_MSIRANGE_6                 LL_RCC_MSIRANGE_6  /*!< MSI = 4 MHz    */
00539 #define RCC_MSIRANGE_7                 LL_RCC_MSIRANGE_7  /*!< MSI = 8 MHz    */
00540 #define RCC_MSIRANGE_8                 LL_RCC_MSIRANGE_8  /*!< MSI = 16 MHz   */
00541 #define RCC_MSIRANGE_9                 LL_RCC_MSIRANGE_9  /*!< MSI = 24 MHz   */
00542 #define RCC_MSIRANGE_10                LL_RCC_MSIRANGE_10 /*!< MSI = 32 MHz   */
00543 #define RCC_MSIRANGE_11                LL_RCC_MSIRANGE_11 /*!< MSI = 48 MHz   */
00544 /**
00545   * @}
00546   */
00547
00548 /** @defgroup RCC_System_Clock_Type System Clock Type
00549   * @{
00550   */
00551 #define RCC_CLOCKTYPE_SYSCLK           0x00000001U  /*!< SYSCLK to configure */
00552 #define RCC_CLOCKTYPE_HCLK             0x00000002U  /*!< HCLK to configure */
00553 #define RCC_CLOCKTYPE_PCLK1            0x00000004U  /*!< PCLK1 to configure */
00554 #define RCC_CLOCKTYPE_PCLK2            0x00000008U  /*!< PCLK2 to configure */
00555 #define RCC_CLOCKTYPE_HCLK2            0x00000020U  /*!< HCLK2 to configure */
00556 #define RCC_CLOCKTYPE_HCLK4            0x00000040U  /*!< HCLK4 to configure */
00557 /**
00558   * @}
00559   */
00560
00561 /** @defgroup RCC_System_Clock_Source System Clock Source
00562   * @{
00563   */
00564 #define RCC_SYSCLKSOURCE_MSI           LL_RCC_SYS_CLKSOURCE_MSI    /*!< MSI selection as system clock */
00565 #define RCC_SYSCLKSOURCE_HSI           LL_RCC_SYS_CLKSOURCE_HSI    /*!< HSI selection as system clock */
00566 #define RCC_SYSCLKSOURCE_HSE           LL_RCC_SYS_CLKSOURCE_HSE    /*!< HSE selection as system clock */
00567 #define RCC_SYSCLKSOURCE_PLLCLK        LL_RCC_SYS_CLKSOURCE_PLL    /*!< PLL selection as system clock */
00568 /**
00569   * @}
00570   */
00571
00572 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
00573   * @{
00574   */
00575 #define RCC_SYSCLKSOURCE_STATUS_MSI    LL_RCC_SYS_CLKSOURCE_STATUS_MSI   /*!< MSI used as system clock */
00576 #define RCC_SYSCLKSOURCE_STATUS_HSI    LL_RCC_SYS_CLKSOURCE_STATUS_HSI   /*!< HSI used as system clock */
00577 #define RCC_SYSCLKSOURCE_STATUS_HSE    LL_RCC_SYS_CLKSOURCE_STATUS_HSE   /*!< HSE used as system clock */
00578 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK LL_RCC_SYS_CLKSOURCE_STATUS_PLL   /*!< PLL used as system clock */
00579 /**
00580   * @}
00581   */
00582
00583 /** @defgroup RCC_AHBx_Clock_Source AHB Clock Source
00584   * @{
00585   */
00586 #define RCC_SYSCLK_DIV1                LL_RCC_SYSCLK_DIV_1     /*!< SYSCLK not divided */
00587 #define RCC_SYSCLK_DIV2                LL_RCC_SYSCLK_DIV_2     /*!< SYSCLK divided by 2 */
00588 #define RCC_SYSCLK_DIV3                LL_RCC_SYSCLK_DIV_3     /*!< SYSCLK divided by 3 */
00589 #define RCC_SYSCLK_DIV4                LL_RCC_SYSCLK_DIV_4     /*!< SYSCLK divided by 4 */
00590 #define RCC_SYSCLK_DIV5                LL_RCC_SYSCLK_DIV_5     /*!< SYSCLK divided by 5 */
00591 #define RCC_SYSCLK_DIV6                LL_RCC_SYSCLK_DIV_6     /*!< SYSCLK divided by 6 */
00592 #define RCC_SYSCLK_DIV8                LL_RCC_SYSCLK_DIV_8     /*!< SYSCLK divided by 8 */
00593 #define RCC_SYSCLK_DIV10               LL_RCC_SYSCLK_DIV_10    /*!< SYSCLK divided by 10 */
00594 #define RCC_SYSCLK_DIV16               LL_RCC_SYSCLK_DIV_16    /*!< SYSCLK divided by 16 */
00595 #define RCC_SYSCLK_DIV32               LL_RCC_SYSCLK_DIV_32    /*!< SYSCLK divided by 32 */
00596 #define RCC_SYSCLK_DIV64               LL_RCC_SYSCLK_DIV_64    /*!< SYSCLK divided by 64 */
00597 #define RCC_SYSCLK_DIV128              LL_RCC_SYSCLK_DIV_128   /*!< SYSCLK divided by 128 */
00598 #define RCC_SYSCLK_DIV256              LL_RCC_SYSCLK_DIV_256   /*!< SYSCLK divided by 256 */
00599 #define RCC_SYSCLK_DIV512              LL_RCC_SYSCLK_DIV_512   /*!< SYSCLK divided by 512 */
00600 /**
00601   * @}
00602   */
00603
00604 /** @defgroup RCC_APBx_Clock_Source APB1 Clock Source
00605 * @{
00606 */
00607 #define RCC_HCLK_DIV1                  LL_RCC_APB1_DIV_1    /*!< HCLK not divided */
00608 #define RCC_HCLK_DIV2                  LL_RCC_APB1_DIV_2    /*!< HCLK divided by 2 */
00609 #define RCC_HCLK_DIV4                  LL_RCC_APB1_DIV_4    /*!< HCLK divided by 4 */
00610 #define RCC_HCLK_DIV8                  LL_RCC_APB1_DIV_8    /*!< HCLK divided by 8 */
00611 #define RCC_HCLK_DIV16                 LL_RCC_APB1_DIV_16   /*!< HCLK divided by 16 */
00612 /**
00613   * @}
00614   */
00615
00616 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
00617   * @{
00618   */
00619 #define RCC_RTCCLKSOURCE_NONE           LL_RCC_RTC_CLKSOURCE_NONE       /*!< No clock used as RTC clock */
00620 #define RCC_RTCCLKSOURCE_LSE            LL_RCC_RTC_CLKSOURCE_LSE        /*!< LSE oscillator clock used as RTC clock */
00621 #define RCC_RTCCLKSOURCE_LSI            LL_RCC_RTC_CLKSOURCE_LSI        /*!< LSI oscillator clock used as RTC clock */
00622 #define RCC_RTCCLKSOURCE_HSE_DIV32      LL_RCC_RTC_CLKSOURCE_HSE_DIV32  /*!< HSE oscillator clock divided by 32 used as RTC clock */
00623 /**
00624   * @}
00625   */
00626
00627 /** @defgroup RCC_MCO_Index MCO Index
00628   * @{
00629   */
00630 #define RCC_MCO1                       0x00000000U          /*!< MCO1 index */
00631 #define RCC_MCO2                       0x00000001U          /*!< MCO2 index */
00632 #define RCC_MCO3                       0x00000002U          /*!< MCO3 index */
00633
00634 #define RCC_MCO                        RCC_MCO1             /*!< MCO1 to be compliant with other families with 1 MCO*/
00635 /**
00636   * @}
00637   */
00638
00639 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
00640   * @{
00641   */
00642 #define RCC_MCO1SOURCE_NOCLOCK         LL_RCC_MCO1SOURCE_NOCLOCK          /*!< MCO1 output disabled, no clock on MCO1 */
00643 #define RCC_MCO1SOURCE_SYSCLK          LL_RCC_MCO1SOURCE_SYSCLK           /*!< SYSCLK selection as MCO1 source */
00644 #define RCC_MCO1SOURCE_MSI             LL_RCC_MCO1SOURCE_MSI              /*!< MSI selection as MCO1 source */
00645 #define RCC_MCO1SOURCE_HSI             LL_RCC_MCO1SOURCE_HSI              /*!< HSI selection as MCO1 source */
00646 #define RCC_MCO1SOURCE_HSE             LL_RCC_MCO1SOURCE_HSE              /*!< HSE after stabilization selection as MCO1 source */
00647 #define RCC_MCO1SOURCE_PLLCLK          LL_RCC_MCO1SOURCE_PLLCLK           /*!< PLLCLK selection as MCO1 source */
00648 #define RCC_MCO1SOURCE_LSI1            LL_RCC_MCO1SOURCE_LSI1             /*!< LSI1 selection as MCO1 source */
00649 #define RCC_MCO1SOURCE_LSI2            LL_RCC_MCO1SOURCE_LSI2             /*!< LSI2 selection as MCO1 source */
00650 #define RCC_MCO1SOURCE_LSE             LL_RCC_MCO1SOURCE_LSE              /*!< LSE selection as MCO1 source */
00651 #define RCC_MCO1SOURCE_HSI48           LL_RCC_MCO1SOURCE_HSI48            /*!< HSI48 selection as MCO1 source */
00652 #define RCC_MCO1SOURCE_HSE_BEFORE_STAB LL_RCC_MCO1SOURCE_HSE_BEFORE_STAB  /*!< HSE before stabilization selection as MCO1 source */
00653
00654 /**
00655   * @}
00656   */
00657
00658 /** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler
00659   * @{
00660   */
00661 #define RCC_MCODIV_1                   LL_RCC_MCO1_DIV_1                  /*!< MCO not divided */
00662 #define RCC_MCODIV_2                   LL_RCC_MCO1_DIV_2                  /*!< MCO divided by 2 */
00663 #define RCC_MCODIV_4                   LL_RCC_MCO1_DIV_4                  /*!< MCO divided by 4 */
00664 #define RCC_MCODIV_8                   LL_RCC_MCO1_DIV_8                  /*!< MCO divided by 8 */
00665 #define RCC_MCODIV_16                  LL_RCC_MCO1_DIV_16                 /*!< MCO divided by 16 */
00666 /**
00667   * @}
00668   */
00669
00670 /** @defgroup RCC_HSEAMPTHRESHOLD HSE bias current factor
00671   * @{
00672   */
00673 #define RCC_HSEAMPTHRESHOLD_1_2       LL_RCC_HSEAMPTHRESHOLD_1_2           /*!< HSE bias current factor 1/2 */
00674 #define RCC_HSEAMPTHRESHOLD_3_4       LL_RCC_HSEAMPTHRESHOLD_3_4           /*!< HSE bias current factor 3/4 */
00675
00676 /**
00677   * @}
00678   */
00679
00680 /** @defgroup RCC_HSE_CURRENTMAX HSE current max limit
00681   * @{
00682   */
00683 #define RCC_HSE_CURRENTMAX_0           LL_RCC_HSE_CURRENTMAX_0             /*!< HSE current max limit 0.18 mA/V */
00684 #define RCC_HSE_CURRENTMAX_1           LL_RCC_HSE_CURRENTMAX_1             /*!< HSE current max limit 0.57 mA/V */
00685 #define RCC_HSE_CURRENTMAX_2           LL_RCC_HSE_CURRENTMAX_2             /*!< HSE current max limit 0.78 mA/V */
00686 #define RCC_HSE_CURRENTMAX_3           LL_RCC_HSE_CURRENTMAX_3             /*!< HSE current max limit 1.13 mA/V */
00687 #define RCC_HSE_CURRENTMAX_4           LL_RCC_HSE_CURRENTMAX_4             /*!< HSE current max limit 0.61 mA/V */
00688 #define RCC_HSE_CURRENTMAX_5           LL_RCC_HSE_CURRENTMAX_5             /*!< HSE current max limit 1.65 mA/V */
00689 #define RCC_HSE_CURRENTMAX_6           LL_RCC_HSE_CURRENTMAX_6             /*!< HSE current max limit 2.12 mA/V */
00690 #define RCC_HSE_CURRENTMAX_7           LL_RCC_HSE_CURRENTMAX_7             /*!< HSE current max limit 2.84 mA/V */
00691
00692 /**
00693   * @}
00694   */
00695
00696 /** @defgroup RCC_Interrupt Interrupts
00697   * @{
00698   */
00699 #define RCC_IT_LSI1RDY                 LL_RCC_CIFR_LSI1RDYF     /*!< LSI1 Ready Interrupt flag */
00700 #define RCC_IT_LSI2RDY                 LL_RCC_CIFR_LSI2RDYF     /*!< LSI2 Ready Interrupt flag */
00701 #define RCC_IT_LSERDY                  LL_RCC_CIFR_LSERDYF      /*!< LSE Ready Interrupt flag */
00702 #define RCC_IT_MSIRDY                  LL_RCC_CIFR_MSIRDYF      /*!< MSI Ready Interrupt flag */
00703 #define RCC_IT_HSIRDY                  LL_RCC_CIFR_HSIRDYF      /*!< HSI Ready Interrupt flag */
00704 #define RCC_IT_HSERDY                  LL_RCC_CIFR_HSERDYF      /*!< HSE Ready Interrupt flag */
00705 #define RCC_IT_PLLRDY                  LL_RCC_CIFR_PLLRDYF      /*!< PLL Ready Interrupt flag */
00706 #if defined(SAI1)
00707 #define RCC_IT_PLLSAI1RDY              LL_RCC_CIFR_PLLSAI1RDYF  /*!< PLLSAI1 Ready Interrupt flag */
00708 #endif
00709 #define RCC_IT_HSECSS                  LL_RCC_CIFR_CSSF         /*!< HSE Clock Security System Interrupt flag */
00710 #define RCC_IT_LSECSS                  LL_RCC_CIFR_LSECSSF      /*!< LSE Clock Security System Interrupt flag */
00711 #define RCC_IT_HSI48RDY                LL_RCC_CIFR_HSI48RDYF    /*!< HSI48 Ready Interrupt flag */
00712 /**
00713   * @}
00714   */
00715
00716
00717 /** @defgroup RCC_Flag Flags
00718   *        Elements values convention: XXXYYYYYb
00719   *           - YYYYY  : Flag position in the register
00720   *           - XXX  : Register index
00721   *                 - 001: CR register
00722   *                 - 010: BDCR register
00723   *                 - 011: CSR register
00724   *                 - 100: CRRCR register
00725   * @{
00726   */
00727 /* Flags in the CR register */
00728 #define RCC_FLAG_MSIRDY                ((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos)      /*!< MSI Ready flag */
00729 #define RCC_FLAG_HSIRDY                ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)      /*!< HSI Ready flag */
00730 #define RCC_FLAG_HSERDY                ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)      /*!< HSE Ready flag */
00731 #define RCC_FLAG_PLLRDY                ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)      /*!< PLL Ready flag */
00732 #define RCC_FLAG_PLLSAI1RDY            ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI1RDY_Pos)  /*!< PLLSAI1 Ready flag */
00733
00734 /* Flags in the BDCR register */
00735 #define RCC_FLAG_LSERDY                ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)  /*!< LSE Ready flag */
00736 #define RCC_FLAG_LSECSSD               ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System failure detection flag */
00737
00738 /* Flags in the CSR register */
00739 #define RCC_FLAG_LSI1RDY               ((CSR_REG_INDEX << 5U) | RCC_CSR_LSI1RDY_Pos)   /*!< LSI1 Ready flag */
00740 #define RCC_FLAG_LSI2RDY               ((CSR_REG_INDEX << 5U) | RCC_CSR_LSI2RDY_Pos)   /*!< LSI2 Ready flag */
00741 #define RCC_FLAG_OBLRST                ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos)   /*!< Option Byte Loader reset flag */
00742 #define RCC_FLAG_PINRST                ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)   /*!< Pin reset flag (NRST pin) */
00743 #define RCC_FLAG_BORRST                ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos)   /*!< BOR reset flag */
00744 #define RCC_FLAG_SFTRST                ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)   /*!< Software Reset flag */
00745 #define RCC_FLAG_IWDGRST               ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)  /*!< Watchdog reset flag */
00746 #define RCC_FLAG_WWDGRST               ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)  /*!< Window watchdog reset flag */
00747 #define RCC_FLAG_LPWRRST               ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)  /*!< Low-Power reset flag */
00748
00749 /* Flags in the CRRCR register */
00750 #define RCC_FLAG_HSI48RDY              ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos) /*!< HSI48 Ready flag */
00751
00752 /**
00753   * @}
00754   */
00755
00756 /** @defgroup RCC_LSEDrive_Config LSE Drive Configuration
00757   * @{
00758   */
00759 #define RCC_LSEDRIVE_LOW                 LL_RCC_LSEDRIVE_LOW            /*!< LSE low drive capability */
00760 #define RCC_LSEDRIVE_MEDIUMLOW           LL_RCC_LSEDRIVE_MEDIUMLOW      /*!< LSE medium low drive capability */
00761 #define RCC_LSEDRIVE_MEDIUMHIGH          LL_RCC_LSEDRIVE_MEDIUMHIGH     /*!< LSE medium high drive capability */
00762 #define RCC_LSEDRIVE_HIGH                LL_RCC_LSEDRIVE_HIGH           /*!< LSE high drive capability */
00763 /**
00764   * @}
00765   */
00766
00767 /** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock
00768   * @{
00769   */
00770 #define RCC_STOP_WAKEUPCLOCK_MSI       LL_RCC_STOP_WAKEUPCLOCK_MSI       /*!< MSI selection after wake-up from STOP */
00771 #define RCC_STOP_WAKEUPCLOCK_HSI       LL_RCC_STOP_WAKEUPCLOCK_HSI       /*!< HSI selection after wake-up from STOP */
00772 /**
00773   * @}
00774   */
00775
00776 /**
00777   * @}
00778   */
00779
00780 /* Exported macros -----------------------------------------------------------*/
00781
00782 /** @defgroup RCC_Exported_Macros RCC Exported Macros
00783   * @{
00784   */
00785
00786 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
00787   * @brief  Enable or disable the AHB1 peripheral clock.
00788   * @note   After reset, the peripheral clock (used for registers read/write access)
00789   *         is disabled and the application software has to enable this clock before
00790   *         using it.
00791   * @{
00792   */
00793
00794 #define __HAL_RCC_DMA1_CLK_ENABLE()            LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1)
00795 #if defined(DMA2)
00796 #define __HAL_RCC_DMA2_CLK_ENABLE()            LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA2)
00797 #endif
00798 #define __HAL_RCC_DMAMUX1_CLK_ENABLE()         LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMAMUX1)
00799 #define __HAL_RCC_CRC_CLK_ENABLE()             LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_CRC)
00800 #define __HAL_RCC_TSC_CLK_ENABLE()             LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_TSC)
00801
00802 #define __HAL_RCC_DMA1_CLK_DISABLE()           LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_DMA1)
00803 #if defined(DMA2)
00804 #define __HAL_RCC_DMA2_CLK_DISABLE()           LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_DMA2)
00805 #endif
00806 #define __HAL_RCC_DMAMUX1_CLK_DISABLE()        LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_DMAMUX1)
00807 #define __HAL_RCC_CRC_CLK_DISABLE()            LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_CRC)
00808 #define __HAL_RCC_TSC_CLK_DISABLE()            LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_TSC)
00809
00810 /**
00811   * @}
00812   */
00813
00814 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
00815   * @brief  Enable or disable the AHB2 peripheral clock.
00816   * @note   After reset, the peripheral clock (used for registers read/write access)
00817   *         is disabled and the application software has to enable this clock before
00818   *         using it.
00819   * @{
00820   */
00821
00822 #define __HAL_RCC_GPIOA_CLK_ENABLE()           LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA)
00823 #define __HAL_RCC_GPIOB_CLK_ENABLE()           LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB)
00824 #define __HAL_RCC_GPIOC_CLK_ENABLE()           LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOC)
00825
00826 #if defined(GPIOD)
00827 #define __HAL_RCC_GPIOD_CLK_ENABLE()           LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOD)
00828 #endif
00829 #define __HAL_RCC_GPIOE_CLK_ENABLE()           LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOE)
00830 #define __HAL_RCC_GPIOH_CLK_ENABLE()           LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOH)
00831
00832 #define __HAL_RCC_ADC_CLK_ENABLE()             LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_ADC)
00833 #if defined(AES1)
00834 #define __HAL_RCC_AES1_CLK_ENABLE()            LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_AES1)
00835 #endif
00836 #define __HAL_RCC_GPIOA_CLK_DISABLE()          LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOA)
00837 #define __HAL_RCC_GPIOB_CLK_DISABLE()          LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOB)
00838 #define __HAL_RCC_GPIOC_CLK_DISABLE()          LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOC)
00839 #if defined(GPIOD)
00840 #define __HAL_RCC_GPIOD_CLK_DISABLE()          LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOD)
00841 #endif
00842 #define __HAL_RCC_GPIOE_CLK_DISABLE()          LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOE)
00843 #define __HAL_RCC_GPIOH_CLK_DISABLE()          LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOH)
00844
00845 #define __HAL_RCC_ADC_CLK_DISABLE()            LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_ADC)
00846
00847 #if defined(AES1)
00848 #define __HAL_RCC_AES1_CLK_DISABLE()           LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_AES1)
00849 #endif
00850
00851 /**
00852   * @}
00853   */
00854
00855 /** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
00856   * @brief  Enable or disable the AHB3 peripheral clock.
00857   * @note   After reset, the peripheral clock (used for registers read/write access)
00858   *         is disabled and the application software has to enable this clock before
00859   *         using it.
00860   * @{
00861   */
00862
00863 #if defined(QUADSPI)
00864 #define __HAL_RCC_QUADSPI_CLK_ENABLE()         LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_QUADSPI)
00865 #endif
00866 #define __HAL_RCC_PKA_CLK_ENABLE()             LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PKA)
00867 #define __HAL_RCC_AES2_CLK_ENABLE()            LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_AES2)
00868 #define __HAL_RCC_RNG_CLK_ENABLE()             LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_RNG)
00869 #define __HAL_RCC_HSEM_CLK_ENABLE()            LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_HSEM)
00870 #define __HAL_RCC_IPCC_CLK_ENABLE()            LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_IPCC)
00871 #define __HAL_RCC_FLASH_CLK_ENABLE()           LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_FLASH)
00872
00873 #if defined(QUADSPI)
00874 #define __HAL_RCC_QUADSPI_CLK_DISABLE()        LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_QUADSPI)
00875 #endif
00876 #define __HAL_RCC_PKA_CLK_DISABLE()            LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_PKA)
00877 #define __HAL_RCC_AES2_CLK_DISABLE()           LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_AES2)
00878 #define __HAL_RCC_RNG_CLK_DISABLE()            LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_RNG)
00879 #define __HAL_RCC_HSEM_CLK_DISABLE()           LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_HSEM)
00880 #define __HAL_RCC_IPCC_CLK_DISABLE()           LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_IPCC)
00881 #define __HAL_RCC_FLASH_CLK_DISABLE()          LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_FLASH)
00882
00883 /**
00884   * @}
00885   */
00886
00887 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
00888   * @brief  Enable or disable the APB1 peripheral clock.
00889   * @note   After reset, the peripheral clock (used for registers read/write access)
00890   *         is disabled and the application software has to enable this clock before
00891   *         using it.
00892   * @{
00893   */
00894
00895 #define __HAL_RCC_RTCAPB_CLK_ENABLE()          LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_RTCAPB)
00896 #define __HAL_RCC_WWDG_CLK_ENABLE()            LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_WWDG)
00897 #define __HAL_RCC_TIM2_CLK_ENABLE()            LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2)
00898 #if defined(LCD)
00899 #define __HAL_RCC_LCD_CLK_ENABLE()             LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LCD)
00900 #endif
00901 #if defined(SPI2)
00902 #define __HAL_RCC_SPI2_CLK_ENABLE()            LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI2)
00903 #endif
00904 #define __HAL_RCC_I2C1_CLK_ENABLE()            LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C1)
00905 #if defined(I2C3)
00906 #define __HAL_RCC_I2C3_CLK_ENABLE()            LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C3)
00907 #endif
00908 #if defined(CRS)
00909 #define __HAL_RCC_CRS_CLK_ENABLE()             LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_CRS)
00910 #endif
00911 #if defined(USB)
00912 #define __HAL_RCC_USB_CLK_ENABLE()             LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USB)
00913 #endif
00914 #define __HAL_RCC_LPTIM1_CLK_ENABLE()          LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LPTIM1)
00915 #define __HAL_RCC_LPTIM2_CLK_ENABLE()          LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_LPTIM2)
00916 #if defined(LPUART1)
00917 #define __HAL_RCC_LPUART1_CLK_ENABLE()         LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_LPUART1)
00918 #endif
00919
00920 #define __HAL_RCC_RTCAPB_CLK_DISABLE()         LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_RTCAPB)
00921 #define __HAL_RCC_TIM2_CLK_DISABLE()           LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM2)
00922 #if defined(LCD)
00923 #define __HAL_RCC_LCD_CLK_DISABLE()            LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_LCD)
00924 #endif
00925 #if defined(SPI2)
00926 #define __HAL_RCC_SPI2_CLK_DISABLE()           LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_SPI2)
00927 #endif
00928 #define __HAL_RCC_I2C1_CLK_DISABLE()           LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C1)
00929 #if defined(I2C3)
00930 #define __HAL_RCC_I2C3_CLK_DISABLE()           LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C3)
00931 #endif
00932 #if defined(CRS)
00933 #define __HAL_RCC_CRS_CLK_DISABLE()            LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_CRS)
00934 #endif
00935 #if defined(USB)
00936 #define __HAL_RCC_USB_CLK_DISABLE()            LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_USB)
00937 #endif
00938 #define __HAL_RCC_LPTIM1_CLK_DISABLE()         LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_LPTIM1)
00939
00940 #define __HAL_RCC_LPTIM2_CLK_DISABLE()         LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_LPTIM2)
00941 #if defined(LPUART1)
00942 #define __HAL_RCC_LPUART1_CLK_DISABLE()        LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_LPUART1)
00943 #endif
00944
00945 /**
00946   * @}
00947   */
00948
00949 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
00950   * @brief  Enable or disable the APB2 peripheral clock.
00951   * @note   After reset, the peripheral clock (used for registers read/write access)
00952   *         is disabled and the application software has to enable this clock before
00953   *         using it.
00954   * @{
00955   */
00956
00957 #define __HAL_RCC_TIM1_CLK_ENABLE()            LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM1)
00958 #define __HAL_RCC_SPI1_CLK_ENABLE()            LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI1)
00959 #define __HAL_RCC_USART1_CLK_ENABLE()          LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1)
00960 #define __HAL_RCC_TIM16_CLK_ENABLE()           LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM16)
00961 #define __HAL_RCC_TIM17_CLK_ENABLE()           LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM17)
00962 #if defined(SAI1)
00963 #define __HAL_RCC_SAI1_CLK_ENABLE()            LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SAI1)
00964 #endif
00965
00966 #define __HAL_RCC_TIM1_CLK_DISABLE()           LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM1)
00967 #define __HAL_RCC_SPI1_CLK_DISABLE()           LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SPI1)
00968 #define __HAL_RCC_USART1_CLK_DISABLE()         LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_USART1)
00969 #define __HAL_RCC_TIM16_CLK_DISABLE()          LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM16)
00970 #define __HAL_RCC_TIM17_CLK_DISABLE()          LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM17)
00971 #if defined(SAI1)
00972 #define __HAL_RCC_SAI1_CLK_DISABLE()           LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SAI1)
00973 #endif
00974
00975 /**
00976   * @}
00977   */
00978
00979 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status
00980   * @brief  Check whether the AHB1 peripheral clock is enabled or not.
00981   * @note   After reset, the peripheral clock (used for registers read/write access)
00982   *         is disabled and the application software has to enable this clock before
00983   *         using it.
00984   * @{
00985   */
00986
00987 #define __HAL_RCC_DMA1_IS_CLK_ENABLED()        LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA1)
00988 #if defined(DMA2)
00989 #define __HAL_RCC_DMA2_IS_CLK_ENABLED()        LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA2)
00990 #endif
00991 #define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED()     LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMAMUX1)
00992 #define __HAL_RCC_CRC_IS_CLK_ENABLED()         LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_CRC)
00993 #define __HAL_RCC_TSC_IS_CLK_ENABLED()         LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_TSC)
00994
00995 #define __HAL_RCC_DMA1_IS_CLK_DISABLED()       !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA1))
00996 #if defined(DMA2)
00997 #define __HAL_RCC_DMA2_IS_CLK_DISABLED()       !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA2))
00998 #endif
00999 #define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED()    !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMAMUX1))
01000 #define __HAL_RCC_CRC_IS_CLK_DISABLED()        !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_CRC))
01001 #define __HAL_RCC_TSC_IS_CLK_DISABLED()        !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_TSC))
01002
01003 /**
01004   * @}
01005   */
01006
01007 /** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status
01008   * @brief  Check whether the AHB2 peripheral clock is enabled or not.
01009   * @note   After reset, the peripheral clock (used for registers read/write access)
01010   *         is disabled and the application software has to enable this clock before
01011   *         using it.
01012   * @{
01013   */
01014
01015 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED()       LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOA)
01016 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED()       LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOB)
01017 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED()       LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOC)
01018 #if defined(GPIOD)
01019 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED()       LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOD)
01020 #endif
01021 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED()       LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOE)
01022 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED()       LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOH)
01023 #define __HAL_RCC_ADC_IS_CLK_ENABLED()         LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_ADC)
01024 #if defined(AES1)
01025 #define __HAL_RCC_AES1_IS_CLK_ENABLED()        LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_AES1)
01026 #endif
01027
01028 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED()      !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOA))
01029 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED()      !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOB))
01030 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED()      !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOC))
01031 #if defined(GPIOD)
01032 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED()      !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOD))
01033 #endif
01034 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED()      !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOE))
01035 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED()      !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOH))
01036 #define __HAL_RCC_ADC_IS_CLK_DISABLED()        !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_ADC))
01037 #if defined(AES1)
01038 #define __HAL_RCC_AES1_IS_CLK_DISABLED()       !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_AES1))
01039 #endif
01040
01041 /**
01042   * @}
01043   */
01044
01045 /** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status
01046   * @brief  Check whether the AHB3 peripheral clock is enabled or not.
01047   * @note   After reset, the peripheral clock (used for registers read/write access)
01048   *         is disabled and the application software has to enable this clock before
01049   *         using it.
01050   * @{
01051   */
01052
01053 #if defined(QUADSPI)
01054 #define __HAL_RCC_QUADSPI_IS_CLK_ENABLED()      LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_QUADSPI)
01055 #endif
01056 #define __HAL_RCC_PKA_IS_CLK_ENABLED()          LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_PKA)
01057 #define __HAL_RCC_AES2_IS_CLK_ENABLED()         LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_AES2)
01058 #define __HAL_RCC_RNG_IS_CLK_ENABLED()          LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_RNG)
01059 #define __HAL_RCC_HSEM_IS_CLK_ENABLED()         LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_HSEM)
01060 #define __HAL_RCC_IPCC_IS_CLK_ENABLED()         LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_IPCC)
01061 #define __HAL_RCC_FLASH_IS_CLK_ENABLED()        LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_FLASH)
01062
01063 #if defined(QUADSPI)
01064 #define __HAL_RCC_QUADSPI_IS_CLK_DISABLED()     !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_QUADSPI))
01065 #endif
01066 #define __HAL_RCC_PKA_IS_CLK_DISABLED()         !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_PKA))
01067 #define __HAL_RCC_AES2_IS_CLK_DISABLED()        !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_AES2))
01068 #define __HAL_RCC_RNG_IS_CLK_DISABLED()         !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_RNG))
01069 #define __HAL_RCC_HSEM_IS_CLK_DISABLED()        !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_HSEM))
01070 #define __HAL_RCC_IPCC_IS_CLK_DISABLED()        !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_IPCC))
01071 #define __HAL_RCC_FLASH_IS_CLK_DISABLED()       !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_FLASH))
01072
01073 /**
01074   * @}
01075   */
01076
01077 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status
01078   * @brief  Check whether the APB1 peripheral clock is enabled or not.
01079   * @note   After reset, the peripheral clock (used for registers read/write access)
01080   *         is disabled and the application software has to enable this clock before
01081   *         using it.
01082   * @{
01083   */
01084
01085 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED()         LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_RTCAPB)
01086 #define __HAL_RCC_WWDG_IS_CLK_ENABLED()           LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_WWDG)
01087 #define __HAL_RCC_TIM2_IS_CLK_ENABLED()           LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM2)
01088 #if defined(LCD)
01089 #define __HAL_RCC_LCD_IS_CLK_ENABLED()            LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LCD)
01090 #endif
01091 #if defined(SPI2)
01092 #define __HAL_RCC_SPI2_IS_CLK_ENABLED()           LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_SPI2)
01093 #endif
01094 #define __HAL_RCC_I2C1_IS_CLK_ENABLED()           LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C1)
01095 #if defined(I2C3)
01096 #define __HAL_RCC_I2C3_IS_CLK_ENABLED()           LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C3)
01097 #endif
01098 #if defined(CRS)
01099 #define __HAL_RCC_CRS_IS_CLK_ENABLED()            LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_CRS)
01100 #endif
01101 #if defined(USB)
01102 #define __HAL_RCC_USB_IS_CLK_ENABLED()            LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_USB)
01103 #endif
01104 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED()         LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LPTIM1)
01105
01106 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED()         LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPTIM2)
01107 #if defined(LPUART1)
01108 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED()        LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPUART1)
01109 #endif
01110
01111 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED()        !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_RTCAPB))
01112 #define __HAL_RCC_WWDG_IS_CLK_DISABLED()          !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_WWDG))
01113 #define __HAL_RCC_TIM2_IS_CLK_DISABLED()          !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM2))
01114 #if defined(LCD)
01115 #define __HAL_RCC_LCD_IS_CLK_DISABLED()           !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LCD))
01116 #endif
01117 #if defined(SPI2)
01118 #define __HAL_RCC_SPI2_IS_CLK_DISABLED()          !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_SPI2))
01119 #endif
01120 #define __HAL_RCC_I2C1_IS_CLK_DISABLED()          !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C1))
01121 #if defined(I2C3)
01122 #define __HAL_RCC_I2C3_IS_CLK_DISABLED()          !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C3))
01123 #endif
01124 #if defined(CRS)
01125 #define __HAL_RCC_CRS_IS_CLK_DISABLED()           !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_CRS))
01126 #endif
01127 #if defined(USB)
01128 #define __HAL_RCC_USB_IS_CLK_DISABLED()           !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_USB))
01129 #endif
01130 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED()        !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LPTIM1))
01131
01132 #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED()        !(LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPTIM2))
01133 #if defined(LPUART1)
01134 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED()       !(LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPUART1))
01135 #endif
01136
01137 /**
01138   * @}
01139   */
01140
01141 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status
01142   * @brief  Check whether the APB2 peripheral clock is enabled or not.
01143   * @note   After reset, the peripheral clock (used for registers read/write access)
01144   *         is disabled and the application software has to enable this clock before
01145   *         using it.
01146   * @{
01147   */
01148
01149 #define __HAL_RCC_TIM1_IS_CLK_ENABLED()           LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM1)
01150 #define __HAL_RCC_SPI1_IS_CLK_ENABLED()           LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SPI1)
01151 #define __HAL_RCC_USART1_IS_CLK_ENABLED()         LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_USART1)
01152 #define __HAL_RCC_TIM16_IS_CLK_ENABLED()          LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM16)
01153 #define __HAL_RCC_TIM17_IS_CLK_ENABLED()          LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM17)
01154 #if defined(SAI1)
01155 #define __HAL_RCC_SAI1_IS_CLK_ENABLED()           LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SAI1)
01156 #endif
01157
01158
01159 #define __HAL_RCC_TIM1_IS_CLK_DISABLED()          !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM1))
01160 #define __HAL_RCC_SPI1_IS_CLK_DISABLED()          !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SPI1))
01161 #define __HAL_RCC_USART1_IS_CLK_DISABLED()        !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_USART1))
01162 #define __HAL_RCC_TIM16_IS_CLK_DISABLED()         !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM16))
01163 #define __HAL_RCC_TIM17_IS_CLK_DISABLED()         !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM17))
01164 #if defined(SAI1)
01165 #define __HAL_RCC_SAI1_IS_CLK_DISABLED()          !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SAI1))
01166 #endif
01167
01168 /**
01169   * @}
01170   */
01171
01172 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
01173   * @brief  Enable or disable the AHB1 peripheral clock.
01174   * @note   After reset, the peripheral clock (used for registers read/write access)
01175   *         is disabled and the application software has to enable this clock before
01176   *         using it.
01177   * @{
01178   */
01179
01180 #define __HAL_RCC_C2DMA1_CLK_ENABLE()            LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMA1)
01181 #if defined(DMA2)
01182 #define __HAL_RCC_C2DMA2_CLK_ENABLE()            LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMA2)
01183 #endif
01184 #define __HAL_RCC_C2DMAMUX1_CLK_ENABLE()         LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1)
01185 #define __HAL_RCC_C2SRAM1_CLK_ENABLE()           LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_SRAM1)
01186 #define __HAL_RCC_C2CRC_CLK_ENABLE()             LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_CRC)
01187 #define __HAL_RCC_C2TSC_CLK_ENABLE()             LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_TSC)
01188
01189 #define __HAL_RCC_C2DMA1_CLK_DISABLE()           LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_DMA1)
01190 #if defined(DMA2)
01191 #define __HAL_RCC_C2DMA2_CLK_DISABLE()           LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_DMA2)
01192 #endif
01193 #define __HAL_RCC_C2DMAMUX1_CLK_DISABLE()        LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1)
01194 #define __HAL_RCC_C2SRAM1_CLK_DISABLE()          LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_SRAM1)
01195 #define __HAL_RCC_C2CRC_CLK_DISABLE()            LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_CRC)
01196 #define __HAL_RCC_C2TSC_CLK_DISABLE()            LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_TSC)
01197
01198 /**
01199   * @}
01200   */
01201
01202 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
01203   * @brief  Enable or disable the AHB2 peripheral clock.
01204   * @note   After reset, the peripheral clock (used for registers read/write access)
01205   *         is disabled and the application software has to enable this clock before
01206   *         using it.
01207   * @{
01208   */
01209
01210 #define __HAL_RCC_C2GPIOA_CLK_ENABLE()           LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA)
01211 #define __HAL_RCC_C2GPIOB_CLK_ENABLE()           LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB)
01212 #define __HAL_RCC_C2GPIOC_CLK_ENABLE()           LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC)
01213 #if defined(GPIOD)
01214 #define __HAL_RCC_C2GPIOD_CLK_ENABLE()           LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOD)
01215 #endif
01216 #define __HAL_RCC_C2GPIOE_CLK_ENABLE()           LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE)
01217 #define __HAL_RCC_C2GPIOH_CLK_ENABLE()           LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH)
01218 #define __HAL_RCC_C2ADC_CLK_ENABLE()             LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_ADC)
01219 #if defined(GPIOD)
01220 #define __HAL_RCC_C2AES1_CLK_ENABLE()            LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_AES1)
01221 #endif
01222
01223 #define __HAL_RCC_C2GPIOA_CLK_DISABLE()          LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA)
01224 #define __HAL_RCC_C2GPIOB_CLK_DISABLE()          LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB)
01225 #define __HAL_RCC_C2GPIOC_CLK_DISABLE()          LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC)
01226 #if defined(GPIOD)
01227 #define __HAL_RCC_C2GPIOD_CLK_DISABLE()          LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOD)
01228 #endif
01229 #define __HAL_RCC_C2GPIOE_CLK_DISABLE()          LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE)
01230 #define __HAL_RCC_C2GPIOH_CLK_DISABLE()          LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH)
01231 #define __HAL_RCC_C2ADC_CLK_DISABLE()            LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_ADC)
01232 #if defined(AES1)
01233 #define __HAL_RCC_C2AES1_CLK_DISABLE()           LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_AES1)
01234 #endif
01235
01236 /**
01237   * @}
01238   */
01239
01240 /** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
01241   * @brief  Enable or disable the AHB3 peripheral clock.
01242   * @note   After reset, the peripheral clock (used for registers read/write access)
01243   *         is disabled and the application software has to enable this clock before
01244   *         using it.
01245   * @{
01246   */
01247
01248 #define __HAL_RCC_C2PKA_CLK_ENABLE()            LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_PKA)
01249 #define __HAL_RCC_C2AES2_CLK_ENABLE()           LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_AES2)
01250 #define __HAL_RCC_C2RNG_CLK_ENABLE()            LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_RNG)
01251 #define __HAL_RCC_C2HSEM_CLK_ENABLE()           LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_HSEM)
01252 #define __HAL_RCC_C2IPCC_CLK_ENABLE()           LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_IPCC)
01253 #define __HAL_RCC_C2FLASH_CLK_ENABLE()          LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_FLASH)
01254
01255 #define __HAL_RCC_C2PKA_CLK_DISABLE()           LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_PKA)
01256 #define __HAL_RCC_C2AES2_CLK_DISABLE()          LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_AES2)
01257 #define __HAL_RCC_C2RNG_CLK_DISABLE()           LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_RNG)
01258 #define __HAL_RCC_C2HSEM_CLK_DISABLE()          LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_HSEM)
01259 #define __HAL_RCC_C2IPCC_CLK_DISABLE()          LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_IPCC)
01260 #define __HAL_RCC_C2FLASH_CLK_DISABLE()         LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_FLASH)
01261
01262 /**
01263   * @}
01264   */
01265
01266 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
01267   * @brief  Enable or disable the APB1 peripheral clock.
01268   * @note   After reset, the peripheral clock (used for registers read/write access)
01269   *         is disabled and the application software has to enable this clock before
01270   *         using it.
01271   * @{
01272   */
01273
01274 #define __HAL_RCC_C2RTCAPB_CLK_ENABLE()          LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB)
01275 #define __HAL_RCC_C2TIM2_CLK_ENABLE()            LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_TIM2)
01276 #if defined(LCD)
01277 #define __HAL_RCC_C2LCD_CLK_ENABLE()             LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_LCD)
01278 #endif
01279 #if defined(SPI2)
01280 #define __HAL_RCC_C2SPI2_CLK_ENABLE()            LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_SPI2)
01281 #endif
01282 #define __HAL_RCC_C2I2C1_CLK_ENABLE()            LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_I2C1)
01283 #if defined(I2C3)
01284 #define __HAL_RCC_C2I2C3_CLK_ENABLE()            LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_I2C3)
01285 #endif
01286 #if defined(CRS)
01287 #define __HAL_RCC_C2CRS_CLK_ENABLE()             LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_CRS)
01288 #endif
01289 #if defined(USB)
01290 #define __HAL_RCC_C2USB_CLK_ENABLE()             LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_USB)
01291 #endif
01292 #define __HAL_RCC_C2LPTIM1_CLK_ENABLE()          LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1)
01293
01294 #define __HAL_RCC_C2LPTIM2_CLK_ENABLE()          LL_C2_APB1_GRP2_EnableClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2)
01295 #if defined(LPUART1)
01296 #define __HAL_RCC_C2LPUART1_CLK_ENABLE()         LL_C2_APB1_GRP2_EnableClock(LL_C2_APB1_GRP2_PERIPH_LPUART1)
01297 #endif
01298
01299 #define __HAL_RCC_C2RTCAPB_CLK_DISABLE()         LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB)
01300 #define __HAL_RCC_C2TIM2_CLK_DISABLE()           LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_TIM2)
01301 #if defined(LCD)
01302 #define __HAL_RCC_C2LCD_CLK_DISABLE()            LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_LCD)
01303 #endif
01304 #if defined(SPI2)
01305 #define __HAL_RCC_C2SPI2_CLK_DISABLE()           LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_SPI2)
01306 #endif
01307 #define __HAL_RCC_C2I2C1_CLK_DISABLE()           LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_I2C1)
01308 #if defined(I2C3)
01309 #define __HAL_RCC_C2I2C3_CLK_DISABLE()           LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_I2C3)
01310 #endif
01311 #if defined(CRS)
01312 #define __HAL_RCC_C2CRS_CLK_DISABLE()            LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_CRS)
01313 #endif
01314 #if defined(USB)
01315 #define __HAL_RCC_C2USB_CLK_DISABLE()            LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_USB)
01316 #endif
01317 #define __HAL_RCC_C2LPTIM1_CLK_DISABLE()         LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1)
01318
01319 #define __HAL_RCC_C2LPTIM2_CLK_DISABLE()         LL_C2_APB1_GRP2_DisableClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2)
01320 #if defined(LPUART1)
01321 #define __HAL_RCC_C2LPUART1_CLK_DISABLE()        LL_C2_APB1_GRP2_DisableClock(LL_C2_APB1_GRP2_PERIPH_LPUART1)
01322 #endif
01323
01324 /**
01325   * @}
01326   */
01327
01328 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
01329   * @brief  Enable or disable the APB2 peripheral clock.
01330   * @note   After reset, the peripheral clock (used for registers read/write access)
01331   *         is disabled and the application software has to enable this clock before
01332   *         using it.
01333   * @{
01334   */
01335
01336 #define __HAL_RCC_C2TIM1_CLK_ENABLE()            LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_TIM1)
01337 #define __HAL_RCC_C2SPI1_CLK_ENABLE()            LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_SPI1)
01338 #define __HAL_RCC_C2USART1_CLK_ENABLE()          LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_USART1)
01339 #define __HAL_RCC_C2TIM16_CLK_ENABLE()           LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_TIM16)
01340 #define __HAL_RCC_C2TIM17_CLK_ENABLE()           LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_TIM17)
01341 #if defined(SAI1)
01342 #define __HAL_RCC_C2SAI1_CLK_ENABLE()            LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_SAI1)
01343 #endif
01344
01345 #define __HAL_RCC_C2TIM1_CLK_DISABLE()           LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_TIM1)
01346 #define __HAL_RCC_C2SPI1_CLK_DISABLE()           LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_SPI1)
01347 #define __HAL_RCC_C2USART1_CLK_DISABLE()         LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_USART1)
01348 #define __HAL_RCC_C2TIM16_CLK_DISABLE()          LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_TIM16)
01349 #define __HAL_RCC_C2TIM17_CLK_DISABLE()          LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_TIM17)
01350 #if defined(SAI1)
01351 #define __HAL_RCC_C2SAI1_CLK_DISABLE()           LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_SAI1)
01352 #endif
01353
01354 /**
01355   * @}
01356   */
01357
01358 /** @defgroup RCC_APB3_Clock_Enable_Disable APB3 Peripheral Clock Enable Disable
01359   * @brief  Enable or disable the APB3 peripheral clock.
01360   * @note   After reset, the peripheral clock (used for registers read/write access)
01361   *         is disabled and the application software has to enable this clock before
01362   *         using it.
01363   * @{
01364   */
01365
01366 #define __HAL_RCC_C2BLE_CLK_ENABLE()           LL_C2_APB3_GRP1_EnableClock(LL_C2_APB3_GRP1_PERIPH_BLE)
01367 #define __HAL_RCC_C2802_CLK_ENABLE()           LL_C2_APB3_GRP1_EnableClock(LL_C2_APB3_GRP1_PERIPH_802)
01368
01369 #define __HAL_RCC_C2BLE_CLK_DISABLE()          LL_C2_APB3_GRP1_DisableClock(LL_C2_APB3_GRP1_PERIPH_BLE)
01370 #define __HAL_RCC_C2802_CLK_DISABLE()          LL_C2_APB3_GRP1_DisableClock(LL_C2_APB3_GRP1_PERIPH_802)
01371
01372
01373 /**
01374   * @}
01375   */
01376
01377 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status
01378   * @brief  Check whether the AHB1 peripheral clock is enabled or not.
01379   * @note   After reset, the peripheral clock (used for registers read/write access)
01380   *         is disabled and the application software has to enable this clock before
01381   *         using it.
01382   * @{
01383   */
01384
01385 #define __HAL_RCC_C2DMA1_IS_CLK_ENABLED()        LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMA1)
01386 #if defined(DMA2)
01387 #define __HAL_RCC_C2DMA2_IS_CLK_ENABLED()        LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMA2)
01388 #endif
01389 #define __HAL_RCC_C2DMAMUX1_IS_CLK_ENABLED()     LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1)
01390 #define __HAL_RCC_C2SRAM1_IS_CLK_ENABLED()       LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_SRAM1)
01391 #define __HAL_RCC_C2CRC_IS_CLK_ENABLED()         LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_CRC)
01392 #define __HAL_RCC_C2TSC_IS_CLK_ENABLED()         LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_TSC)
01393
01394 #define __HAL_RCC_C2DMA1_IS_CLK_DISABLED()       !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMA1))
01395 #if defined(DMA2)
01396 #define __HAL_RCC_C2DMA2_IS_CLK_DISABLED()       !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMA2))
01397 #endif
01398 #define __HAL_RCC_C2DMAMUX1_IS_CLK_DISABLED()    !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1))
01399 #define __HAL_RCC_C2SRAM1_IS_CLK_DISABLED()      !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_SRAM1))
01400 #define __HAL_RCC_C2CRC_IS_CLK_DISABLED()        !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_CRC))
01401 #define __HAL_RCC_C2TSC_IS_CLK_DISABLED()        !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_TSC))
01402
01403 /**
01404   * @}
01405   */
01406
01407 /** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status
01408   * @brief  Check whether the AHB2 peripheral clock is enabled or not.
01409   * @note   After reset, the peripheral clock (used for registers read/write access)
01410   *         is disabled and the application software has to enable this clock before
01411   *         using it.
01412   * @{
01413   */
01414
01415 #define __HAL_RCC_C2GPIOA_IS_CLK_ENABLED()       LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA)
01416 #define __HAL_RCC_C2GPIOB_IS_CLK_ENABLED()       LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB)
01417 #define __HAL_RCC_C2GPIOC_IS_CLK_ENABLED()       LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC)
01418 #if defined(GPIOD)
01419 #define __HAL_RCC_C2GPIOD_IS_CLK_ENABLED()       LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOD)
01420 #endif
01421 #define __HAL_RCC_C2GPIOE_IS_CLK_ENABLED()       LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE)
01422 #define __HAL_RCC_C2GPIOH_IS_CLK_ENABLED()       LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH)
01423 #define __HAL_RCC_C2ADC_IS_CLK_ENABLED()         LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_ADC)
01424 #if defined(AES1)
01425 #define __HAL_RCC_C2AES1_IS_CLK_ENABLED()        LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_AES1)
01426 #endif
01427
01428 #define __HAL_RCC_C2GPIOA_IS_CLK_DISABLED()      !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA))
01429 #define __HAL_RCC_C2GPIOB_IS_CLK_DISABLED()      !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB))
01430 #define __HAL_RCC_C2GPIOC_IS_CLK_DISABLED()      !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC))
01431 #if defined(GPIOD)
01432 #define __HAL_RCC_C2GPIOD_IS_CLK_DISABLED()      !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOD))
01433 #endif
01434 #define __HAL_RCC_C2GPIOE_IS_CLK_DISABLED()      !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE))
01435 #define __HAL_RCC_C2GPIOH_IS_CLK_DISABLED()      !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH))
01436 #define __HAL_RCC_C2ADC_IS_CLK_DISABLED()        !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_ADC))
01437 #if defined(AES1)
01438 #define __HAL_RCC_C2AES1_IS_CLK_DISABLED()       !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_AES1))
01439 #endif
01440
01441 /**
01442   * @}
01443   */
01444
01445 /** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status
01446   * @brief  Check whether the AHB3 peripheral clock is enabled or not.
01447   * @note   After reset, the peripheral clock (used for registers read/write access)
01448   *         is disabled and the application software has to enable this clock before
01449   *         using it.
01450   * @{
01451   */
01452
01453 #define __HAL_RCC_C2PKA_IS_CLK_ENABLED()          LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_PKA)
01454 #define __HAL_RCC_C2AES2_IS_CLK_ENABLED()         LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_AES2)
01455 #define __HAL_RCC_C2RNG_IS_CLK_ENABLED()          LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_RNG)
01456 #define __HAL_RCC_C2HSEM_IS_CLK_ENABLED()         LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_HSEM)
01457 #define __HAL_RCC_C2IPCC_IS_CLK_ENABLED()         LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_IPCC)
01458 #define __HAL_RCC_C2FLASH_IS_CLK_ENABLED()        LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_FLASH)
01459
01460 #define __HAL_RCC_C2PKA_IS_CLK_DISABLED()         !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_PKA))
01461 #define __HAL_RCC_C2AES2_IS_CLK_DISABLED()        !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_AES2))
01462 #define __HAL_RCC_C2RNG_IS_CLK_DISABLED()         !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_RNG))
01463 #define __HAL_RCC_C2HSEM_IS_CLK_DISABLED()        !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_HSEM))
01464 #define __HAL_RCC_C2IPCC_IS_CLK_DISABLED()        !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_IPCC))
01465 #define __HAL_RCC_C2FLASH_IS_CLK_DISABLED()       !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_FLASH))
01466
01467 /**
01468   * @}
01469   */
01470
01471 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status
01472   * @brief  Check whether the APB1 peripheral clock is enabled or not.
01473   * @note   After reset, the peripheral clock (used for registers read/write access)
01474   *         is disabled and the application software has to enable this clock before
01475   *         using it.
01476   * @{
01477   */
01478
01479 #define __HAL_RCC_C2RTCAPB_IS_CLK_ENABLED()         LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB)
01480 #define __HAL_RCC_C2TIM2_IS_CLK_ENABLED()           LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_TIM2)
01481 #if defined(LCD)
01482 #define __HAL_RCC_C2LCD_IS_CLK_ENABLED()            LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LCD)
01483 #endif
01484 #if defined(SPI2)
01485 #define __HAL_RCC_C2SPI2_IS_CLK_ENABLED()           LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_SPI2)
01486 #endif
01487 #define __HAL_RCC_C2I2C1_IS_CLK_ENABLED()           LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C1)
01488 #if defined(I2C3)
01489 #define __HAL_RCC_C2I2C3_IS_CLK_ENABLED()           LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C3)
01490 #endif
01491 #if defined(CRS)
01492 #define __HAL_RCC_C2CRS_IS_CLK_ENABLED()            LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_CRS)
01493 #endif
01494 #if defined(USB)
01495 #define __HAL_RCC_C2USB_IS_CLK_ENABLED()            LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_USB)
01496 #endif
01497 #define __HAL_RCC_C2LPTIM1_IS_CLK_ENABLED()         LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1)
01498
01499 #define __HAL_RCC_C2LPTIM2_IS_CLK_ENABLED()         LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2)
01500 #if defined(LPUART1)
01501 #define __HAL_RCC_C2LPUART1_IS_CLK_ENABLED()        LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP2_PERIPH_LPUART1)
01502 #endif
01503
01504 #define __HAL_RCC_C2RTCAPB_IS_CLK_DISABLED()       !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB))
01505 #define __HAL_RCC_C2TIM2_IS_CLK_DISABLED()         !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_TIM2))
01506 #if defined(LCD)
01507 #define __HAL_RCC_C2LCD_IS_CLK_DISABLED()          !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LCD))
01508 #endif
01509 #if defined(SPI2)
01510 #define __HAL_RCC_C2SPI2_IS_CLK_DISABLED()         !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_SPI2))
01511 #endif
01512 #define __HAL_RCC_C2I2C1_IS_CLK_DISABLED()         !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C1))
01513 #if defined(I2C3)
01514 #define __HAL_RCC_C2I2C3_IS_CLK_DISABLED()         !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C3))
01515 #endif
01516 #if defined(CRS)
01517 #define __HAL_RCC_C2CRS_IS_CLK_DISABLED()          !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_CRS))
01518 #endif
01519 #if defined(USB)
01520 #define __HAL_RCC_C2USB_IS_CLK_DISABLED()          !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_USB))
01521 #endif
01522 #define __HAL_RCC_C2LPTIM1_IS_CLK_DISABLED()       !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1))
01523
01524 #define __HAL_RCC_C2LPTIM2_IS_CLK_DISABLED()       !(LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2))
01525 #if defined(LPUART1)
01526 #define __HAL_RCC_C2LPUART1_IS_CLK_DISABLED()      !(LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1))
01527 #endif
01528
01529 /**
01530   * @}
01531   */
01532
01533 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status
01534   * @brief  Check whether the APB2 peripheral clock is enabled or not.
01535   * @note   After reset, the peripheral clock (used for registers read/write access)
01536   *         is disabled and the application software has to enable this clock before
01537   *         using it.
01538   * @{
01539   */
01540
01541 #define __HAL_RCC_C2TIM1_IS_CLK_ENABLED()           LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM1)
01542 #define __HAL_RCC_C2SPI1_IS_CLK_ENABLED()           LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SPI1)
01543 #define __HAL_RCC_C2USART1_IS_CLK_ENABLED()         LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_USART1)
01544 #define __HAL_RCC_C2TIM16_IS_CLK_ENABLED()          LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM16)
01545 #define __HAL_RCC_C2TIM17_IS_CLK_ENABLED()          LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM17)
01546 #if defined(SAI1)
01547 #define __HAL_RCC_C2SAI1_IS_CLK_ENABLED()           LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SAI1)
01548 #endif
01549
01550 #define __HAL_RCC_C2TIM1_IS_CLK_DISABLED()          !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM1))
01551 #define __HAL_RCC_C2SPI1_IS_CLK_DISABLED()          !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SPI1))
01552 #define __HAL_RCC_C2USART1_IS_CLK_DISABLED()        !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_USART1))
01553 #define __HAL_RCC_C2TIM16_IS_CLK_DISABLED()         !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM16))
01554 #define __HAL_RCC_C2TIM17_IS_CLK_DISABLED()         !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM17))
01555 #if defined(SAI1)
01556 #define __HAL_RCC_C2SAI1_IS_CLK_DISABLED()          !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SAI1))
01557 #endif
01558
01559 /**
01560   * @}
01561   */
01562
01563
01564 /** @defgroup RCC_APB3_Clock_Enable_Disable_Status APB3 Peripheral Clock Enabled or Disabled Status
01565   * @brief  Check whether the APB3 peripheral clock is enabled or not.
01566   * @note   After reset, the peripheral clock (used for registers read/write access)
01567   *         is disabled and the application software has to enable this clock before
01568   *         using it.
01569   * @{
01570   */
01571
01572 #define __HAL_RCC_C2BLE_IS_CLK_ENABLED()            LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_BLE)
01573 #define __HAL_RCC_C2802_IS_CLK_ENABLED()            LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_802)
01574
01575 #define __HAL_RCC_C2BLE_IS_CLK_DISABLED()          !(LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_BLE))
01576 #define __HAL_RCC_C2802_IS_CLK_DISABLED()          !(LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_802))
01577
01578 /**
01579   * @}
01580   */
01581
01582
01583 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset
01584   * @brief  Force or release AHB1 peripheral reset.
01585   * @{
01586   */
01587 #define __HAL_RCC_AHB1_FORCE_RESET()           LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_ALL)
01588 #define __HAL_RCC_DMA1_FORCE_RESET()           LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1)
01589 #if defined(DMA2)
01590 #define __HAL_RCC_DMA2_FORCE_RESET()           LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2)
01591 #endif
01592 #define __HAL_RCC_DMAMUX1_FORCE_RESET()        LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMAMUX1)
01593 #define __HAL_RCC_CRC_FORCE_RESET()            LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CRC)
01594 #define __HAL_RCC_TSC_FORCE_RESET()            LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_TSC)
01595
01596
01597 #define __HAL_RCC_AHB1_RELEASE_RESET()         LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ALL)
01598 #define __HAL_RCC_DMA1_RELEASE_RESET()         LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1)
01599 #if defined(DMA2)
01600 #define __HAL_RCC_DMA2_RELEASE_RESET()         LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2)
01601 #endif
01602 #define __HAL_RCC_DMAMUX1_RELEASE_RESET()      LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMAMUX1)
01603 #define __HAL_RCC_CRC_RELEASE_RESET()          LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC)
01604 #define __HAL_RCC_TSC_RELEASE_RESET()          LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_TSC)
01605
01606
01607 /**
01608   * @}
01609   */
01610
01611 /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset
01612   * @brief  Force or release AHB2 peripheral reset.
01613   * @{
01614   */
01615 #define __HAL_RCC_AHB2_FORCE_RESET()           LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ALL)
01616 #define __HAL_RCC_GPIOA_FORCE_RESET()          LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOA)
01617 #define __HAL_RCC_GPIOB_FORCE_RESET()          LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOB)
01618 #define __HAL_RCC_GPIOC_FORCE_RESET()          LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOC)
01619 #if defined(GPIOD)
01620 #define __HAL_RCC_GPIOD_FORCE_RESET()          LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOD)
01621 #endif
01622 #define __HAL_RCC_GPIOE_FORCE_RESET()          LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOE)
01623 #define __HAL_RCC_GPIOH_FORCE_RESET()          LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOH)
01624 #define __HAL_RCC_ADC_FORCE_RESET()            LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC)
01625 #if defined(AES1)
01626 #define __HAL_RCC_AES1_FORCE_RESET()           LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_AES1)
01627 #endif
01628
01629 #define __HAL_RCC_AHB2_RELEASE_RESET()         LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ALL)
01630 #define __HAL_RCC_GPIOA_RELEASE_RESET()        LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOA)
01631 #define __HAL_RCC_GPIOB_RELEASE_RESET()        LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOB)
01632 #define __HAL_RCC_GPIOC_RELEASE_RESET()        LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOC)
01633 #if defined(GPIOD)
01634 #define __HAL_RCC_GPIOD_RELEASE_RESET()        LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOD)
01635 #endif
01636 #define __HAL_RCC_GPIOE_RELEASE_RESET()        LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOE)
01637 #define __HAL_RCC_GPIOH_RELEASE_RESET()        LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOH)
01638 #define __HAL_RCC_ADC_RELEASE_RESET()          LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC)
01639 #if defined(AES1)
01640 #define __HAL_RCC_AES1_RELEASE_RESET()         LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_AES1)
01641 #endif
01642
01643 /**
01644   * @}
01645   */
01646
01647 /** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset
01648   * @brief  Force or release AHB3 peripheral reset.
01649   * @{
01650   */
01651 #define __HAL_RCC_AHB3_FORCE_RESET()           LL_AHB3_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ALL)
01652 #if defined(QUADSPI)
01653 #define __HAL_RCC_QUADSPI_FORCE_RESET()        LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_QUADSPI)
01654 #endif
01655 #define __HAL_RCC_PKA_FORCE_RESET()            LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_PKA)
01656 #define __HAL_RCC_AES2_FORCE_RESET()           LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_AES2)
01657 #define __HAL_RCC_RNG_FORCE_RESET()            LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_RNG)
01658 #define __HAL_RCC_HSEM_FORCE_RESET()           LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_HSEM)
01659 #define __HAL_RCC_IPCC_FORCE_RESET()           LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_IPCC)
01660 #define __HAL_RCC_FLASH_FORCE_RESET()          LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_FLASH)
01661
01662 #define __HAL_RCC_AHB3_RELEASE_RESET()         LL_AHB3_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ALL)
01663 #if defined(QUADSPI)
01664 #define __HAL_RCC_QUADSPI_RELEASE_RESET()      LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_QUADSPI)
01665 #endif
01666 #define __HAL_RCC_PKA_RELEASE_RESET()          LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_PKA)
01667 #define __HAL_RCC_AES2_RELEASE_RESET()         LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_AES2)
01668 #define __HAL_RCC_RNG_RELEASE_RESET()          LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_RNG)
01669 #define __HAL_RCC_HSEM_RELEASE_RESET()         LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_HSEM)
01670 #define __HAL_RCC_IPCC_RELEASE_RESET()         LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_IPCC)
01671 #define __HAL_RCC_FLASH_RELEASE_RESET()        LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_FLASH)
01672 /**
01673   * @}
01674   */
01675
01676 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
01677   * @brief  Force or release APB1 peripheral reset.
01678   * @{
01679   */
01680
01681 #define __HAL_RCC_APB1L_FORCE_RESET()          LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_ALL)
01682 #define __HAL_RCC_TIM2_FORCE_RESET()           LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2)
01683 #if defined(LCD)
01684 #define __HAL_RCC_LCD_FORCE_RESET()            LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LCD)
01685 #endif
01686 #if defined(SPI2)
01687 #define __HAL_RCC_SPI2_FORCE_RESET()           LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2)
01688 #endif
01689 #define __HAL_RCC_I2C1_FORCE_RESET()           LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1)
01690 #if defined(I2C3)
01691 #define __HAL_RCC_I2C3_FORCE_RESET()           LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3)
01692 #endif
01693 #if defined(CRS)
01694 #define __HAL_RCC_CRS_FORCE_RESET()            LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_CRS)
01695 #endif
01696 #if defined(USB)
01697 #define __HAL_RCC_USB_FORCE_RESET()            LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USB)
01698 #endif
01699 #define __HAL_RCC_LPTIM1_FORCE_RESET()         LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1)
01700
01701 #define __HAL_RCC_APB1H_FORCE_RESET()          LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_ALL)
01702 #if defined(LPUART1)
01703 #define __HAL_RCC_LPUART1_FORCE_RESET()        LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPUART1)
01704 #endif
01705 #define __HAL_RCC_LPTIM2_FORCE_RESET()         LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPTIM2)
01706
01707 #define __HAL_RCC_APB1_FORCE_RESET() do { \
01708                                            __HAL_RCC_APB1L_FORCE_RESET();\
01709                                            __HAL_RCC_APB1H_FORCE_RESET();\
01710                                         } while(0U)
01711
01712 #define __HAL_RCC_APB1L_RELEASE_RESET()        LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_ALL)
01713 #define __HAL_RCC_TIM2_RELEASE_RESET()         LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2)
01714 #if defined(LCD)
01715 #define __HAL_RCC_LCD_RELEASE_RESET()          LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LCD)
01716 #endif
01717 #if defined(SPI2)
01718 #define __HAL_RCC_SPI2_RELEASE_RESET()         LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2)
01719 #endif
01720 #define __HAL_RCC_I2C1_RELEASE_RESET()         LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1)
01721 #if defined(I2C3)
01722 #define __HAL_RCC_I2C3_RELEASE_RESET()         LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3)
01723 #endif
01724 #if defined(CRS)
01725 #define __HAL_RCC_CRS_RELEASE_RESET()          LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_CRS)
01726 #endif
01727 #if defined(USB)
01728 #define __HAL_RCC_USB_RELEASE_RESET()          LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USB)
01729 #endif
01730 #define __HAL_RCC_LPTIM1_RELEASE_RESET()       LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1)
01731
01732 #define __HAL_RCC_APB1H_RELEASE_RESET()        LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_ALL)
01733 #if defined(LPUART1)
01734 #define __HAL_RCC_LPUART1_RELEASE_RESET()      LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPUART1)
01735 #endif
01736 #define __HAL_RCC_LPTIM2_RELEASE_RESET()       LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPTIM2)
01737
01738 #define __HAL_RCC_APB1_RELEASE_RESET() do { \
01739                                            __HAL_RCC_APB1L_RELEASE_RESET();\
01740                                            __HAL_RCC_APB1H_RELEASE_RESET();\
01741                                         } while(0U)
01742 /**
01743   * @}
01744   */
01745
01746 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
01747   * @brief  Force or release APB2 peripheral reset.
01748   * @{
01749   */
01750 #define __HAL_RCC_APB2_FORCE_RESET()           LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ALL)
01751 #define __HAL_RCC_TIM1_FORCE_RESET()           LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1)
01752 #define __HAL_RCC_SPI1_FORCE_RESET()           LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1)
01753 #define __HAL_RCC_USART1_FORCE_RESET()         LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1)
01754 #define __HAL_RCC_TIM16_FORCE_RESET()          LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16)
01755 #define __HAL_RCC_TIM17_FORCE_RESET()          LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17)
01756 #if defined(SAI1)
01757 #define __HAL_RCC_SAI1_FORCE_RESET()           LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SAI1)
01758 #endif
01759
01760 #define __HAL_RCC_APB2_RELEASE_RESET()         LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ALL)
01761 #define __HAL_RCC_TIM1_RELEASE_RESET()         LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1)
01762 #define __HAL_RCC_SPI1_RELEASE_RESET()         LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1)
01763 #define __HAL_RCC_USART1_RELEASE_RESET()       LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1)
01764 #define __HAL_RCC_TIM16_RELEASE_RESET()        LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16)
01765 #define __HAL_RCC_TIM17_RELEASE_RESET()        LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17)
01766 #if defined(SAI1)
01767 #define __HAL_RCC_SAI1_RELEASE_RESET()         LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SAI1)
01768 #endif
01769 /**
01770   * @}
01771   */
01772
01773 /** @defgroup RCC_APB3_Force_Release_Reset APB3 Peripheral Force Release Reset
01774   * @brief  Force or release APB3 peripheral reset.
01775   * @{
01776   */
01777 #define __HAL_RCC_APB3_FORCE_RESET()           LL_APB3_GRP1_ForceReset(LL_APB3_GRP1_PERIPH_ALL)
01778 #define __HAL_RCC_RF_FORCE_RESET()             LL_APB3_GRP1_ForceReset(LL_APB3_GRP1_PERIPH_RF)
01779
01780 #define __HAL_RCC_APB3_RELEASE_RESET()         LL_APB3_GRP1_ReleaseReset(LL_APB3_GRP1_PERIPH_ALL)
01781 #define __HAL_RCC_RF_RELEASE_RESET()           LL_APB3_GRP1_ReleaseReset(LL_APB3_GRP1_PERIPH_RF)
01782
01783 /**
01784   * @}
01785   */
01786
01787 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable
01788   * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
01789   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
01790   *         power consumption.
01791   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
01792   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
01793   * @{
01794   */
01795 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE()       LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_DMA1)
01796 #if defined(DMA2)
01797 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE()       LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_DMA2)
01798 #endif
01799 #define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE()    LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_DMAMUX1)
01800 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()      LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_SRAM1)
01801 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()        LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_CRC)
01802 #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE()        LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_TSC)
01803
01804 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE()      LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_DMA1)
01805 #if defined(DMA2)
01806 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE()      LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_DMA2)
01807 #endif
01808 #define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE()   LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_DMAMUX1)
01809 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()     LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_SRAM1)
01810 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()       LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_CRC)
01811 #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE()       LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_TSC)
01812
01813 #define __HAL_RCC_C2DMA1_CLK_SLEEP_ENABLE()     LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA1)
01814 #if defined(DMA2)
01815 #define __HAL_RCC_C2DMA2_CLK_SLEEP_ENABLE()     LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA2)
01816 #endif
01817 #define __HAL_RCC_C2DMAMUX1_CLK_SLEEP_ENABLE()  LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1)
01818 #define __HAL_RCC_C2SRAM1_CLK_SLEEP_ENABLE()    LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_SRAM1)
01819 #define __HAL_RCC_C2CRC_CLK_SLEEP_ENABLE()      LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_CRC)
01820 #define __HAL_RCC_C2TSC_CLK_SLEEP_ENABLE()      LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_TSC)
01821
01822 #define __HAL_RCC_C2DMA1_CLK_SLEEP_DISABLE()    LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA1)
01823 #if defined(DMA2)
01824 #define __HAL_RCC_C2DMA2_CLK_SLEEP_DISABLE()    LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA2)
01825 #endif
01826 #define __HAL_RCC_C2DMAMUX1_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1)
01827 #define __HAL_RCC_C2SRAM1_CLK_SLEEP_DISABLE()   LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_SRAM1)
01828
01829 #define __HAL_RCC_C2CRC_CLK_SLEEP_DISABLE()     LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_CRC)
01830 #define __HAL_RCC_C2TSC_CLK_SLEEP_DISABLE()     LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_TSC)
01831
01832 /**
01833   * @}
01834   */
01835
01836 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable
01837   * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
01838   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
01839   *         power consumption.
01840   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
01841   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
01842   * @{
01843   */
01844 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE()     LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOA)
01845 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE()     LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOB)
01846 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE()     LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOC)
01847 #if defined(GPIOD)
01848 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()     LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOD)
01849 #endif
01850 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()     LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOE)
01851 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE()     LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOH)
01852 #define __HAL_RCC_ADC_CLK_SLEEP_ENABLE()       LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_ADC)
01853 #if defined(AES1)
01854 #define __HAL_RCC_AES1_CLK_SLEEP_ENABLE()      LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_AES1)
01855 #endif
01856
01857 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE()    LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOA)
01858 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE()    LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOB)
01859 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE()    LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOC)
01860 #if defined(GPIOD)
01861 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()    LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOD)
01862 #endif
01863 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()    LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOE)
01864 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE()    LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOH)
01865 #define __HAL_RCC_ADC_CLK_SLEEP_DISABLE()      LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_ADC)
01866 #if defined(AES1)
01867 #define __HAL_RCC_AES1_CLK_SLEEP_DISABLE()     LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_AES1)
01868 #endif
01869
01870 #define __HAL_RCC_C2GPIOA_CLK_SLEEP_ENABLE()   LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOA)
01871 #define __HAL_RCC_C2GPIOB_CLK_SLEEP_ENABLE()   LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOB)
01872 #define __HAL_RCC_C2GPIOC_CLK_SLEEP_ENABLE()   LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOC)
01873 #if defined(GPIOD)
01874 #define __HAL_RCC_C2GPIOD_CLK_SLEEP_ENABLE()   LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOD)
01875 #endif
01876 #define __HAL_RCC_C2GPIOE_CLK_SLEEP_ENABLE()   LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOE)
01877 #define __HAL_RCC_C2GPIOH_CLK_SLEEP_ENABLE()   LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOH)
01878 #define __HAL_RCC_C2ADC_CLK_SLEEP_ENABLE()     LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_ADC)
01879 #if defined(AES1)
01880 #define __HAL_RCC_C2AES1_CLK_SLEEP_ENABLE()    LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_AES1)
01881 #endif
01882
01883 #define __HAL_RCC_C2GPIOA_CLK_SLEEP_DISABLE()  LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOA)
01884 #define __HAL_RCC_C2GPIOB_CLK_SLEEP_DISABLE()  LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOB)
01885 #define __HAL_RCC_C2GPIOC_CLK_SLEEP_DISABLE()  LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOC)
01886 #if defined(GPIOD)
01887 #define __HAL_RCC_C2GPIOD_CLK_SLEEP_DISABLE()  LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOD)
01888 #endif
01889 #define __HAL_RCC_C2GPIOE_CLK_SLEEP_DISABLE()  LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOE)
01890 #define __HAL_RCC_C2GPIOH_CLK_SLEEP_DISABLE()  LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOH)
01891 #define __HAL_RCC_C2ADC_CLK_SLEEP_DISABLE()    LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_ADC)
01892 #if defined(AES1)
01893 #define __HAL_RCC_C2AES1_CLK_SLEEP_DISABLE()   LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_AES1)
01894 #endif
01895
01896 /**
01897   * @}
01898   */
01899
01900 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable
01901   * @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
01902   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
01903   *         power consumption.
01904   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
01905   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
01906   * @{
01907   */
01908 #if defined(QUADSPI)
01909 #define __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE()   LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_QUADSPI)
01910 #endif
01911 #define __HAL_RCC_PKA_CLK_SLEEP_ENABLE()       LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_PKA)
01912 #define __HAL_RCC_AES2_CLK_SLEEP_ENABLE()      LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_AES2)
01913 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()       LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_RNG)
01914 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE()     LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_SRAM2)
01915 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE()     LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_FLASH)
01916
01917 #if defined(QUADSPI)
01918 #define __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE()  LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_QUADSPI)
01919 #endif
01920 #define __HAL_RCC_PKA_CLK_SLEEP_DISABLE()      LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_PKA)
01921 #define __HAL_RCC_AES2_CLK_SLEEP_DISABLE()     LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_AES2)
01922 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()      LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_RNG)
01923 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE()    LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_SRAM2)
01924 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE()    LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_FLASH)
01925
01926 #define __HAL_RCC_C2PKA_CLK_SLEEP_ENABLE()     LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_PKA)
01927 #define __HAL_RCC_C2AES2_CLK_SLEEP_ENABLE()    LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_AES2)
01928 #define __HAL_RCC_C2RNG_CLK_SLEEP_ENABLE()     LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_RNG)
01929 #define __HAL_RCC_C2SRAM2_CLK_SLEEP_ENABLE()   LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_SRAM2)
01930 #define __HAL_RCC_C2FLASH_CLK_SLEEP_ENABLE()   LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_FLASH)
01931
01932 #define __HAL_RCC_C2PKA_CLK_SLEEP_DISABLE()    LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_PKA)
01933 #define __HAL_RCC_C2AES2_CLK_SLEEP_DISABLE()   LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_AES2)
01934 #define __HAL_RCC_C2RNG_CLK_SLEEP_DISABLE()    LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_RNG)
01935 #define __HAL_RCC_C2SRAM2_CLK_SLEEP_DISABLE()  LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_SRAM2)
01936 #define __HAL_RCC_C2FLASH_CLK_SLEEP_DISABLE()  LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_FLASH)
01937
01938 /**
01939   * @}
01940   */
01941
01942 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
01943   * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
01944   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
01945   *         power consumption.
01946   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
01947   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
01948   * @{
01949   */
01950 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()           LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_TIM2)
01951 #if defined(LCD)
01952 #define __HAL_RCC_LCD_CLK_SLEEP_ENABLE()            LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_LCD)
01953 #endif
01954 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE()         LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_RTCAPB)
01955 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE()           LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_WWDG)
01956 #if defined(SPI2)
01957 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()           LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_SPI2)
01958 #endif
01959 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()           LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_I2C1)
01960 #if defined(I2C3)
01961 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()           LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_I2C3)
01962 #endif
01963 #if defined(CRS)
01964 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE()            LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_CRS)
01965 #endif
01966 #if defined(USB)
01967 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE()            LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_USB)
01968 #endif
01969 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()         LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_LPTIM1)
01970 #if defined(LPUART1)
01971 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE()        LL_APB1_GRP2_EnableClockSleep(LL_APB1_GRP2_PERIPH_LPUART1)
01972 #endif
01973 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE()         LL_APB1_GRP2_EnableClockSleep(LL_APB1_GRP2_PERIPH_LPTIM2)
01974
01975 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()          LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_TIM2)
01976 #if defined(LCD)
01977 #define __HAL_RCC_LCD_CLK_SLEEP_DISABLE()           LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_LCD)
01978 #endif
01979 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE()        LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_RTCAPB)
01980 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE()          LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_WWDG)
01981 #if defined(SPI2)
01982 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()          LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_SPI2)
01983 #endif
01984 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()          LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_I2C1)
01985 #if defined(I2C3)
01986 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()          LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_I2C3)
01987 #endif
01988 #if defined(CRS)
01989 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE()           LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_CRS)
01990 #endif
01991 #if defined(USB)
01992 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE()           LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_USB)
01993 #endif
01994 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE()        LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_LPTIM1)
01995 #if defined(LPUART1)
01996 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE()       LL_APB1_GRP2_DisableClockSleep(LL_APB1_GRP2_PERIPH_LPUART1)
01997 #endif
01998 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE()        LL_APB1_GRP2_DisableClockSleep(LL_APB1_GRP2_PERIPH_LPTIM2)
01999
02000 #define __HAL_RCC_C2TIM2_CLK_SLEEP_ENABLE()         LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_TIM2)
02001 #if defined(LCD)
02002 #define __HAL_RCC_C2LCD_CLK_SLEEP_ENABLE()          LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_LCD)
02003 #endif
02004 #define __HAL_RCC_C2RTCAPB_CLK_SLEEP_ENABLE()       LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_RTCAPB)
02005 #if defined(SPI2)
02006 #define __HAL_RCC_C2SPI2_CLK_SLEEP_ENABLE()         LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_SPI2)
02007 #endif
02008 #define __HAL_RCC_C2I2C1_CLK_SLEEP_ENABLE()         LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C1)
02009 #if defined(I2C3)
02010 #define __HAL_RCC_C2I2C3_CLK_SLEEP_ENABLE()         LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C3)
02011 #endif
02012 #if defined(CRS)
02013 #define __HAL_RCC_C2CRS_CLK_SLEEP_ENABLE()          LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_CRS)
02014 #endif
02015 #if defined(USB)
02016 #define __HAL_RCC_C2USB_CLK_SLEEP_ENABLE()          LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_USB)
02017 #endif
02018 #define __HAL_RCC_C2LPTIM1_CLK_SLEEP_ENABLE()       LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_LPTIM1)
02019 #if defined(LPUART1)
02020 #define __HAL_RCC_C2LPUART1_CLK_SLEEP_ENABLE()      LL_C2_APB1_GRP2_EnableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPUART1)
02021 #endif
02022 #define __HAL_RCC_C2LPTIM2_CLK_SLEEP_ENABLE()       LL_C2_APB1_GRP2_EnableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPTIM2)
02023
02024 #define __HAL_RCC_C2TIM2_CLK_SLEEP_DISABLE()        LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_TIM2)
02025 #if defined(LCD)
02026 #define __HAL_RCC_C2LCD_CLK_SLEEP_DISABLE()         LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_LCD)
02027 #endif
02028 #define __HAL_RCC_C2RTCAPB_CLK_SLEEP_DISABLE()      LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_RTCAPB)
02029 #if defined(SPI2)
02030 #define __HAL_RCC_C2SPI2_CLK_SLEEP_DISABLE()        LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_SPI2)
02031 #endif
02032 #define __HAL_RCC_C2I2C1_CLK_SLEEP_DISABLE()        LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C1)
02033 #if defined(I2C3)
02034 #define __HAL_RCC_C2I2C3_CLK_SLEEP_DISABLE()        LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C3)
02035 #endif
02036 #if defined(CRS)
02037 #define __HAL_RCC_C2CRS_CLK_SLEEP_DISABLE()         LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_CRS)
02038 #endif
02039 #if defined(USB)
02040 #define __HAL_RCC_C2USB_CLK_SLEEP_DISABLE()         LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_USB)
02041 #endif
02042 #define __HAL_RCC_C2LPTIM1_CLK_SLEEP_DISABLE()      LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_LPTIM1)
02043 #if defined(LPUART1)
02044 #define __HAL_RCC_C2LPUART1_CLK_SLEEP_DISABLE()     LL_C2_APB1_GRP2_DisableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPUART1)
02045 #endif
02046 #define __HAL_RCC_C2LPTIM2_CLK_SLEEP_DISABLE()      LL_C2_APB1_GRP2_DisableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPTIM2)
02047
02048 /**
02049   * @}
02050   */
02051
02052 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
02053   * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
02054   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02055   *         power consumption.
02056   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02057   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02058   * @{
02059   */
02060 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE()           LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_TIM1)
02061 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE()           LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_SPI1)
02062 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE()         LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_USART1)
02063 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE()          LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_TIM16)
02064 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE()          LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_TIM17)
02065 #if defined(SAI1)
02066 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE()           LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_SAI1)
02067 #endif
02068
02069 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE()          LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_TIM1)
02070 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE()          LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_SPI1)
02071 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE()        LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_USART1)
02072 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE()         LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_TIM16)
02073 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE()         LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_TIM17)
02074 #if defined(SAI1)
02075 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE()          LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_SAI1)
02076 #endif
02077
02078 #define __HAL_RCC_C2TIM1_CLK_SLEEP_ENABLE()         LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM1)
02079 #define __HAL_RCC_C2SPI1_CLK_SLEEP_ENABLE()         LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_SPI1)
02080 #define __HAL_RCC_C2USART1_CLK_SLEEP_ENABLE()       LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_USART1)
02081 #define __HAL_RCC_C2TIM16_CLK_SLEEP_ENABLE()        LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM16)
02082 #define __HAL_RCC_C2TIM17_CLK_SLEEP_ENABLE()        LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM17)
02083 #if defined(SAI1)
02084 #define __HAL_RCC_C2SAI1_CLK_SLEEP_ENABLE()         LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_SAI1)
02085 #endif
02086
02087 #define __HAL_RCC_C2TIM1_CLK_SLEEP_DISABLE()        LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM1)
02088 #define __HAL_RCC_C2SPI1_CLK_SLEEP_DISABLE()        LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_SPI1)
02089 #define __HAL_RCC_C2USART1_CLK_SLEEP_DISABLE()      LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_USART1)
02090 #define __HAL_RCC_C2TIM16_CLK_SLEEP_DISABLE()       LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM16)
02091 #define __HAL_RCC_C2TIM17_CLK_SLEEP_DISABLE()       LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM17)
02092 #if defined(SAI1)
02093 #define __HAL_RCC_C2SAI1_CLK_SLEEP_DISABLE()        LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_SAI1)
02094 #endif
02095 /**
02096   * @}
02097   */
02098
02099 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status
02100   * @brief  Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
02101   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02102   *         power consumption.
02103   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02104   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02105   * @{
02106   */
02107 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED()       (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != RESET)
02108 #if defined(DMA2)
02109 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED()       (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != RESET)
02110 #endif
02111 #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != RESET)
02112 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != RESET)
02113 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED()        (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != RESET)
02114 #define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED()        (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != RESET)
02115
02116 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED()      (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == RESET)
02117 #if defined(DMA2)
02118 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED()      (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == RESET)
02119 #endif
02120 #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == RESET)
02121 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == RESET)
02122 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED()       (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == RESET)
02123 #define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED()       (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == RESET)
02124
02125 #define __HAL_RCC_C2DMA1_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMA1SMEN) != RESET)
02126 #if defined(DMA2)
02127 #define __HAL_RCC_C2DMA2_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMA2SMEN) != RESET)
02128 #endif
02129 #define __HAL_RCC_C2DMAMUX1_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMAMUX1SMEN) != RESET)
02130 #define __HAL_RCC_C2SRAM1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_SRAM1SMEN) != RESET)
02131 #define __HAL_RCC_C2CRC_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_CRCSMEN) != RESET)
02132 #define __HAL_RCC_C2TSC_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_TSCSMEN) != RESET)
02133
02134 #define __HAL_RCC_C2DMA1_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMA1SMEN) == RESET)
02135 #if defined(DMA2)
02136 #define __HAL_RCC_C2DMA2_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMA2SMEN) == RESET)
02137 #endif
02138 #define __HAL_RCC_C2DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMAMUX1SMEN) == RESET)
02139 #define __HAL_RCC_C2SRAM1_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_SRAM1SMEN) == RESET)
02140 #define __HAL_RCC_C2CRC_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_CRCSMEN) == RESET)
02141 #define __HAL_RCC_C2TSC_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_TSCSMEN) == RESET)
02142 /**
02143   * @}
02144   */
02145
02146 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status
02147   * @brief  Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
02148   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02149   *         power consumption.
02150   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02151   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02152   * @{
02153   */
02154 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != RESET)
02155 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != RESET)
02156 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != RESET)
02157 #if defined(GPIOD)
02158 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != RESET)
02159 #endif
02160 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != RESET)
02161 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != RESET)
02162 #define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED()       (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)   != RESET)
02163 #if defined(AES1)
02164 #define __HAL_RCC_AES1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AES1SMEN) != RESET)
02165 #endif
02166
02167 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == RESET)
02168 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == RESET)
02169 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == RESET)
02170 #if defined(GPIOD)
02171 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == RESET)
02172 #endif
02173 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == RESET)
02174 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == RESET)
02175 #define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED()       (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)   == RESET)
02176 #if defined(AES1)
02177 #define __HAL_RCC_AES1_IS_CLK_SLEEP_DISABLED()      (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AES1SMEN) == RESET)
02178 #endif
02179
02180 #define __HAL_RCC_C2GPIOA_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOASMEN) != RESET)
02181 #define __HAL_RCC_C2GPIOB_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOBSMEN) != RESET)
02182 #define __HAL_RCC_C2GPIOC_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOCSMEN) != RESET)
02183 #if defined(GPIOD)
02184 #define __HAL_RCC_C2GPIOD_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIODSMEN) != RESET)
02185 #endif
02186 #define __HAL_RCC_C2GPIOE_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOESMEN) != RESET)
02187 #define __HAL_RCC_C2GPIOH_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOHSMEN) != RESET)
02188 #define __HAL_RCC_C2ADC_IS_CLK_SLEEP_ENABLED()       (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_ADCSMEN)   != RESET)
02189 #if defined(AES1)
02190 #define __HAL_RCC_C2AES1_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_AES1SMEN) != RESET)
02191 #endif
02192
02193 #define __HAL_RCC_C2GPIOA_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOASMEN) == RESET)
02194 #define __HAL_RCC_C2GPIOB_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOBSMEN) == RESET)
02195 #define __HAL_RCC_C2GPIOC_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOCSMEN) == RESET)
02196 #if defined(GPIOD)
02197 #define __HAL_RCC_C2GPIOD_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIODSMEN) == RESET)
02198 #endif
02199 #define __HAL_RCC_C2GPIOE_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOESMEN) == RESET)
02200 #define __HAL_RCC_C2GPIOH_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOHSMEN) == RESET)
02201 #define __HAL_RCC_C2ADC_IS_CLK_SLEEP_DISABLED()      (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_ADCSMEN)   == RESET)
02202 #if defined(AES1)
02203 #define __HAL_RCC_C2AES1_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_AES1SMEN) == RESET)
02204 #endif
02205 /**
02206   * @}
02207   */
02208
02209 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status
02210   * @brief  Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not.
02211   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02212   *         power consumption.
02213   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02214   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02215   * @{
02216   */
02217 #if defined(QUADSPI)
02218 #define __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QUADSPISMEN) != RESET)
02219 #endif
02220 #define __HAL_RCC_PKA_IS_CLK_SLEEP_ENABLED()       (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_PKASMEN) != RESET)
02221 #define __HAL_RCC_AES2_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_AES2SMEN) != RESET)
02222 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED()       (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_RNGSMEN) != RESET)
02223 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_SRAM2SMEN) != RESET)
02224 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FLASHSMEN) != RESET)
02225
02226 #if defined(QUADSPI)
02227 #define __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QUADSPISMEN) == RESET)
02228 #endif
02229 #define __HAL_RCC_PKA_IS_CLK_SLEEP_DISABLED()      (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_PKASMEN) == RESET)
02230 #define __HAL_RCC_AES2_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_AES2SMEN) == RESET)
02231 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED()      (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_RNGSMEN) == RESET)
02232 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_SRAM2SMEN) == RESET)
02233 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FLASHSMEN) == RESET)
02234
02235 #define __HAL_RCC_C2PKA_IS_CLK_SLEEP_ENABLED()       (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_PKASMEN) != RESET)
02236 #define __HAL_RCC_C2AES2_IS_CLK_SLEEP_ENABLED()      (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_AES2SMEN) != RESET)
02237 #define __HAL_RCC_C2RNG_IS_CLK_SLEEP_ENABLED()       (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_RNGSMEN) != RESET)
02238 #define __HAL_RCC_C2SRAM2_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_SRAM2SMEN) != RESET)
02239 #define __HAL_RCC_C2FLASH_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_FLASHSMEN) != RESET)
02240
02241 #define __HAL_RCC_C2PKA_IS_CLK_SLEEP_DISABLED()      (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_PKASMEN) == RESET)
02242 #define __HAL_RCC_C2AES2_IS_CLK_SLEEP_DISABLED()     (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_AES2SMEN) == RESET)
02243 #define __HAL_RCC_C2RNG_IS_CLK_SLEEP_DISABLED()      (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_RNGSMEN) == RESET)
02244 #define __HAL_RCC_C2SRAM2_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_SRAM2SMEN) == RESET)
02245 #define __HAL_RCC_C2FLASH_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_FLASHSMEN) == RESET)
02246
02247 /**
02248   * @}
02249   */
02250
02251 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status
02252   * @brief  Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
02253   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02254   *         power consumption.
02255   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02256   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02257   * @{
02258   */
02259 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED()           (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != RESET)
02260 #if defined(LCD)
02261 #define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED()            (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)  != RESET)
02262 #endif
02263 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED()         (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)  != RESET)
02264 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED()           (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)  != RESET)
02265 #if defined(SPI2)
02266 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED()           (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != RESET)
02267 #endif
02268 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED()           (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != RESET)
02269 #if defined(I2C3)
02270 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED()           (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != RESET)
02271 #endif
02272 #if defined(CRS)
02273 #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED()            (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)  != RESET)
02274 #endif
02275 #if defined(USB)
02276 #define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED()            (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN)  != RESET)
02277 #endif
02278 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED()         (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != RESET)
02279 #if defined(LPUART1)
02280 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED()        (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != RESET)
02281 #endif
02282 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED()         (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != RESET)
02283
02284 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED()          (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == RESET)
02285 #if defined(LCD)
02286 #define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED()           (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)  == RESET)
02287 #endif
02288 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED()        (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)  == RESET)
02289 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED()          (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)  == RESET)
02290 #if defined(SPI2)
02291 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED()          (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == RESET)
02292 #endif
02293 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED()          (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == RESET)
02294 #if defined(I2C3)
02295 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED()          (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == RESET)
02296 #endif
02297 #if defined(CRS)
02298 #define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED()           (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)  == RESET)
02299 #endif
02300 #if defined(USB)
02301 #define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED()           (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN)  == RESET)
02302 #endif
02303 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED()        (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == RESET)
02304 #if defined(LPUART1)
02305 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED()       (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == RESET)
02306 #endif
02307 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED()        (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == RESET)
02308
02309 #define __HAL_RCC_C2TIM2_IS_CLK_SLEEP_ENABLED()           (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_TIM2SMEN) != RESET)
02310 #if defined(LCD)
02311 #define __HAL_RCC_C2LCD_IS_CLK_SLEEP_ENABLED()            (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_LCDSMEN)  != RESET)
02312 #endif
02313 #define __HAL_RCC_C2RTCAPB_IS_CLK_SLEEP_ENABLED()         (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_RTCAPBSMEN)  != RESET)
02314 #if defined(SPI2)
02315 #define __HAL_RCC_C2SPI2_IS_CLK_SLEEP_ENABLED()           (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_SPI2SMEN) != RESET)
02316 #endif
02317 #define __HAL_RCC_C2I2C1_IS_CLK_SLEEP_ENABLED()           (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_I2C1SMEN) != RESET)
02318 #if defined(I2C3)
02319 #define __HAL_RCC_C2I2C3_IS_CLK_SLEEP_ENABLED()           (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_I2C3SMEN) != RESET)
02320 #endif
02321 #if defined(CRS)
02322 #define __HAL_RCC_C2CRS_IS_CLK_SLEEP_ENABLED()            (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_CRSSMEN)  != RESET)
02323 #endif
02324 #if defined(USB)
02325 #define __HAL_RCC_C2USB_IS_CLK_SLEEP_ENABLED()            (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_USBSMEN)  != RESET)
02326 #endif
02327 #define __HAL_RCC_C2LPTIM1_IS_CLK_SLEEP_ENABLED()         (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_LPTIM1SMEN) != RESET)
02328 #if defined(LPUART1)
02329 #define __HAL_RCC_C2LPUART1_IS_CLK_SLEEP_ENABLED()        (READ_BIT(RCC->C2APB1SMENR2, RCC_C2APB1SMENR2_LPUART1SMEN) != RESET)
02330 #endif
02331 #define __HAL_RCC_C2LPTIM2_IS_CLK_SLEEP_ENABLED()         (READ_BIT(RCC->C2APB1SMENR2, RCC_C2APB1SMENR2_LPTIM2SMEN) != RESET)
02332
02333 #define __HAL_RCC_C2TIM2_IS_CLK_SLEEP_DISABLED()          (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_TIM2SMEN) == RESET)
02334 #if defined(LCD)
02335 #define __HAL_RCC_C2LCD_IS_CLK_SLEEP_DISABLED()           (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_LCDSMEN)  == RESET)
02336 #endif
02337 #define __HAL_RCC_C2RTCAPB_IS_CLK_SLEEP_DISABLED()        (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_RTCAPBSMEN)  == RESET)
02338 #if defined(SPI2)
02339 #define __HAL_RCC_C2SPI2_IS_CLK_SLEEP_DISABLED()          (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_SPI2SMEN) == RESET)
02340 #endif
02341 #define __HAL_RCC_C2I2C1_IS_CLK_SLEEP_DISABLED()          (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_I2C1SMEN) == RESET)
02342 #if defined(I2C3)
02343 #define __HAL_RCC_C2I2C3_IS_CLK_SLEEP_DISABLED()          (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_I2C3SMEN) == RESET)
02344 #endif
02345 #if defined(CRS)
02346 #define __HAL_RCC_C2CRS_IS_CLK_SLEEP_DISABLED()           (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_CRSSMEN)  == RESET)
02347 #endif
02348 #if defined(USB)
02349 #define __HAL_RCC_C2USB_IS_CLK_SLEEP_DISABLED()           (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_USBSMEN)  == RESET)
02350 #endif
02351 #define __HAL_RCC_C2LPTIM1_IS_CLK_SLEEP_DISABLED()        (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_LPTIM1SMEN) == RESET)
02352 #if defined(LPUART1)
02353 #define __HAL_RCC_C2LPUART1_IS_CLK_SLEEP_DISABLED()       (READ_BIT(RCC->C2APB1SMENR2, RCC_C2APB1SMENR2_LPUART1SMEN) == RESET)
02354 #endif
02355 #define __HAL_RCC_C2LPTIM2_IS_CLK_SLEEP_DISABLED()        (READ_BIT(RCC->C2APB1SMENR2, RCC_C2APB1SMENR2_LPTIM2SMEN) == RESET)
02356 /**
02357   * @}
02358   */
02359
02360 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status
02361   * @brief  Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
02362   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02363   *         power consumption.
02364   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02365   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02366   * @{
02367   */
02368 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED()           (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != RESET)
02369 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED()           (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != RESET)
02370 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED()         (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != RESET)
02371 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED()          (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != RESET)
02372 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED()          (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != RESET)
02373 #if defined(SAI1)
02374 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED()           (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != RESET)
02375 #endif
02376
02377 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED()           (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == RESET)
02378 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED()           (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == RESET)
02379 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED()         (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == RESET)
02380 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED()          (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == RESET)
02381 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED()          (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == RESET)
02382 #if defined(SAI1)
02383 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED()           (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == RESET)
02384 #endif
02385
02386 #define __HAL_RCC_C2TIM1_IS_CLK_SLEEP_ENABLED()           (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM1SMEN) != RESET)
02387 #define __HAL_RCC_C2SPI1_IS_CLK_SLEEP_ENABLED()           (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SPI1SMEN) != RESET)
02388 #define __HAL_RCC_C2USART1_IS_CLK_SLEEP_ENABLED()         (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_USART1SMEN) != RESET)
02389 #define __HAL_RCC_C2TIM16_IS_CLK_SLEEP_ENABLED()          (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM16SMEN) != RESET)
02390 #define __HAL_RCC_C2TIM17_IS_CLK_SLEEP_ENABLED()          (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM17SMEN) != RESET)
02391 #if defined(SAI1)
02392 #define __HAL_RCC_C2SAI1_IS_CLK_SLEEP_ENABLED()           (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SAI1SMEN) != RESET)
02393 #endif
02394
02395 #define __HAL_RCC_C2TIM1_IS_CLK_SLEEP_DISABLED()           (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM1SMEN) == RESET)
02396 #define __HAL_RCC_C2SPI1_IS_CLK_SLEEP_DISABLED()           (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SPI1SMEN) == RESET)
02397 #define __HAL_RCC_C2USART1_IS_CLK_SLEEP_DISABLED()         (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_USART1SMEN) == RESET)
02398 #define __HAL_RCC_C2TIM16_IS_CLK_SLEEP_DISABLED()          (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM16SMEN) == RESET)
02399 #define __HAL_RCC_C2TIM17_IS_CLK_SLEEP_DISABLED()          (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM17SMEN) == RESET)
02400 #if defined(SAI1)
02401 #define __HAL_RCC_C2SAI1_IS_CLK_SLEEP_DISABLED()           (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SAI1SMEN) == RESET)
02402 #endif
02403 /**
02404   * @}
02405   */
02406
02407 /** @defgroup RCC_C2APB3_Clock_Sleep_Enable_Disable APB3 Peripheral Clock Sleep Enable Disable
02408   * @brief  Enable or disable the APB3 peripheral clock during Low Power (Sleep) mode.
02409   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02410   *         power consumption.
02411   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02412   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02413   * @{
02414   */
02415 #define __HAL_RCC_C2BLE_CLK_SLEEP_ENABLE()          LL_C2_APB3_GRP1_EnableClockSleep(LL_C2_APB3_GRP1_PERIPH_BLE)
02416 #define __HAL_RCC_C2802_CLK_SLEEP_ENABLE()          LL_C2_APB3_GRP1_EnableClockSleep(LL_C2_APB3_GRP1_PERIPH_802)
02417
02418 #define __HAL_RCC_C2BLE_CLK_SLEEP_DISABLE()         LL_C2_APB3_GRP1_DisableClockSleep(LL_C2_APB3_GRP1_PERIPH_BLE)
02419 #define __HAL_RCC_C2802_CLK_SLEEP_DISABLE()         LL_C2_APB3_GRP1_DisableClockSleep(LL_C2_APB3_GRP1_PERIPH_802)
02420 /**
02421   * @}
02422   */
02423
02424 /** @defgroup RCC_C2APB3_Clock_Sleep_Enable_Disable_Status APB3 Peripheral Clock Sleep Enabled or Disabled Status
02425   * @brief  Check whether the APB3 peripheral clock during Low Power (Sleep) mode is enabled or not.
02426   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
02427   *         power consumption.
02428   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
02429   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
02430   * @{
02431   */
02432 #define __HAL_RCC_C2BLE_IS_CLK_SLEEP_ENABLED()           (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_BLESMEN) != RESET)
02433 #define __HAL_RCC_C2802_IS_CLK_SLEEP_ENABLED()           (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_802SMEN) != RESET)
02434
02435 #define __HAL_RCC_C2BLE_IS_CLK_SLEEP_DISABLED()           (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_BLESMEN) == RESET)
02436 #define __HAL_RCC_C2802_IS_CLK_SLEEP_DISABLED()           (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_802SMEN) == RESET)
02437 /**
02438   * @}
02439   */
02440
02441 /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset
02442   * @{
02443   */
02444
02445 /** @brief  Macros to force or release the Backup domain reset.
02446   * @note   This function resets the RTC peripheral (including the backup registers)
02447   *         and the RTC clock source selection in RCC_CSR register.
02448   * @note   The BKPSRAM is not affected by this reset.
02449   * @retval None
02450   */
02451 #define __HAL_RCC_BACKUPRESET_FORCE()   LL_RCC_ForceBackupDomainReset()
02452 #define __HAL_RCC_BACKUPRESET_RELEASE() LL_RCC_ReleaseBackupDomainReset()
02453
02454 /**
02455   * @}
02456   */
02457
02458 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
02459   * @{
02460   */
02461
02462 /** @brief  Macros to enable or disable the RTC clock.
02463   * @note   As the RTC is in the Backup domain and write access is denied to
02464   *         this domain after reset, you have to enable write access using
02465   *         HAL_PWR_EnableBkUpAccess() function before to configure the RTC
02466   *         (to be done once after reset).
02467   * @note   These macros must be used after the RTC clock source was selected.
02468   * @retval None
02469   */
02470 #define __HAL_RCC_RTC_ENABLE()         LL_RCC_EnableRTC()
02471 #define __HAL_RCC_RTC_DISABLE()        LL_RCC_DisableRTC()
02472
02473 /**
02474   * @}
02475   */
02476
02477 /** @brief  Macros to enable the Internal High Speed oscillator (HSI).
02478   * @note   The HSI is stopped by hardware when entering STOP, STANDBY or SHUTDOWN modes.
02479   *         It is enabled by hardware to force the HSI oscillator ON when STOPWUCK=1
02480   *         or HSIASFS = 1 when leaving Stop modes, or in case of failure of the HSE
02481   *         crystal oscillator and Security System CSS is enabled.
02482   * @note   After enabling the HSI, the application software should wait on HSIRDY
02483   *         flag to be set indicating that HSI clock is stable and can be used as
02484   *         system clock source.
02485   * @retval None
02486   */
02487 #define __HAL_RCC_HSI_ENABLE()  LL_RCC_HSI_Enable()
02488
02489 /** @brief  Macro to disable the Internal High Speed oscillator (HSI).
02490   * @note   HSI can not be stopped if it is used as system clock source. In this case,
02491   *         you have to select another source of the system clock then stop the HSI.
02492   * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
02493   *         clock cycles.
02494   * @retval None
02495   */
02496 #define __HAL_RCC_HSI_DISABLE() LL_RCC_HSI_Disable()
02497
02498 /** @brief  Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
02499   * @note   The calibration is used to compensate for the variations in voltage
02500   *         and temperature that influence the frequency of the internal HSI RC.
02501   * @param  __HSICALIBRATIONVALUE__ specifies the calibration trimming value
02502   *         (default is RCC_HSICALIBRATION_DEFAULT).
02503   *         This parameter must be a number between Min_data=0 and Max_Data=127.
02504   * @retval None
02505   */
02506 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__)  LL_RCC_HSI_SetCalibTrimming(__HSICALIBRATIONVALUE__)
02507
02508 /**
02509   * @brief    Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI)
02510   *           in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup.
02511   * @note     The enable of this function has not effect on the HSION bit.
02512   *           This parameter can be: ENABLE or DISABLE.
02513   * @retval None
02514   */
02515 #define __HAL_RCC_HSIAUTOMATIC_START_ENABLE()   LL_RCC_HSI_EnableAutoFromStop()
02516 #define __HAL_RCC_HSIAUTOMATIC_START_DISABLE()  LL_RCC_HSI_DisableAutoFromStop()
02517
02518 /**
02519   * @brief    Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
02520   *           in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
02521   * @note     Keeping the HSI ON in STOP mode allows to avoid slowing down the communication
02522   *           speed because of the HSI startup time.
02523   * @note     The enable of this function has not effect on the HSION bit.
02524   * @retval None
02525   */
02526 #define __HAL_RCC_HSISTOP_ENABLE()     LL_RCC_HSI_EnableInStopMode()
02527 #define __HAL_RCC_HSISTOP_DISABLE()    LL_RCC_HSI_DisableInStopMode()
02528
02529 /**
02530   * @brief  Macros to enable or disable the Internal Multi Speed oscillator (MSI).
02531   * @note   The MSI is stopped by hardware when entering STOP and STANDBY modes.
02532   *         It is used (enabled by hardware) as system clock source after
02533   *         startup from Reset, wakeup from STOP and STANDBY mode, or in case
02534   *         of failure of the HSE used directly or indirectly as system clock
02535   *         (if the Clock Security System CSS is enabled).
02536   * @note   MSI can not be stopped if it is used as system clock source.
02537   *         In this case, you have to select another source of the system
02538   *         clock then stop the MSI.
02539   * @note   After enabling the MSI, the application software should wait on
02540   *         MSIRDY flag to be set indicating that MSI clock is stable and can
02541   *         be used as system clock source.
02542   * @note   When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
02543   *         clock cycles.
02544   * @retval None
02545   */
02546 #define __HAL_RCC_MSI_ENABLE()  LL_RCC_MSI_Enable()
02547 #define __HAL_RCC_MSI_DISABLE() LL_RCC_MSI_Disable()
02548
02549 /** @brief  Macro to adjust the Internal Multi Speed oscillator (MSI) calibration value.
02550   * @note   The calibration is used to compensate for the variations in voltage
02551   *         and temperature that influence the frequency of the internal MSI RC.
02552   *         Refer to the Application Note AN3300 for more details on how to
02553   *         calibrate the MSI.
02554   * @param  __MSICALIBRATIONVALUE__  specifies the calibration trimming value
02555   *         (default is @ref RCC_MSICALIBRATION_DEFAULT).
02556   *         This parameter must be a number between 0 and 255.
02557   * @retval None
02558   */
02559 #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__)  LL_RCC_MSI_SetCalibTrimming(__MSICALIBRATIONVALUE__)
02560
02561 /**
02562   * @brief  Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode
02563   * @note     After restart from Reset , the MSI clock is around 4 MHz.
02564   *           After stop the startup clock can be MSI (at any of its possible
02565   *           frequencies, the one that was used before entering stop mode) or HSI.
02566   *          After Standby its frequency can be selected between 4 possible values
02567   *          (1, 2, 4 or 8 MHz).
02568   * @note     MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready
02569   *          (MSIRDY=1).
02570   * @note    The MSI clock range after reset can be modified on the fly.
02571   * @param  __MSIRANGEVALUE__  specifies the MSI clock range.
02572   *         This parameter must be one of the following values:
02573   *            @arg @ref RCC_MSIRANGE_0  MSI clock is around 100 KHz
02574   *            @arg @ref RCC_MSIRANGE_1  MSI clock is around 200 KHz
02575   *            @arg @ref RCC_MSIRANGE_2  MSI clock is around 400 KHz
02576   *            @arg @ref RCC_MSIRANGE_3  MSI clock is around 800 KHz
02577   *            @arg @ref RCC_MSIRANGE_4  MSI clock is around 1 MHz
02578   *            @arg @ref RCC_MSIRANGE_5  MSI clock is around 2MHz
02579   *            @arg @ref RCC_MSIRANGE_6  MSI clock is around 4MHz (default after Reset)
02580   *            @arg @ref RCC_MSIRANGE_7  MSI clock is around 8  MHz
02581   *            @arg @ref RCC_MSIRANGE_8  MSI clock is around 16 MHz
02582   *            @arg @ref RCC_MSIRANGE_9  MSI clock is around 24 MHz
02583   *            @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz
02584   *            @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz
02585   * @retval None
02586   */
02587 #define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__)  LL_RCC_MSI_SetRange(__MSIRANGEVALUE__)
02588
02589
02590 /** @brief  Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode
02591   * @retval MSI clock range.
02592   *         This parameter must be one of the following values:
02593   *            @arg @ref RCC_MSIRANGE_0   MSI clock is around 100 KHz
02594   *            @arg @ref RCC_MSIRANGE_1   MSI clock is around 200 KHz
02595   *            @arg @ref RCC_MSIRANGE_2   MSI clock is around 400 KHz
02596   *            @arg @ref RCC_MSIRANGE_3   MSI clock is around 800 KHz
02597   *            @arg @ref RCC_MSIRANGE_4   MSI clock is around 1 MHz
02598   *            @arg @ref RCC_MSIRANGE_5   MSI clock is around 2 MHz
02599   *            @arg @ref RCC_MSIRANGE_6   MSI clock is around 4 MHz   (default after Reset)
02600   *            @arg @ref RCC_MSIRANGE_7   MSI clock is around 8 MHz
02601   *            @arg @ref RCC_MSIRANGE_8   MSI clock is around 16 MHz
02602   *            @arg @ref RCC_MSIRANGE_9   MSI clock is around 24 MHz
02603   *            @arg @ref RCC_MSIRANGE_10  MSI clock is around 32 MHz
02604   *            @arg @ref RCC_MSIRANGE_11  MSI clock is around 48 MHz
02605   */
02606 #define __HAL_RCC_GET_MSI_RANGE()    LL_RCC_MSI_GetRange()
02607
02608
02609 /** @brief  Macros to enable or disable the Internal Low Speed oscillator (LSI1).
02610   * @note   After enabling the LSI1, the application software should wait on
02611   *         LSI1RDY flag to be set indicating that LSI1 clock is stable and can
02612   *         be used to clock the IWDG and/or the RTC.
02613   * @retval None
02614   */
02615 #define __HAL_RCC_LSI1_ENABLE()         LL_RCC_LSI1_Enable()
02616 #define __HAL_RCC_LSI1_DISABLE()        LL_RCC_LSI1_Disable()
02617
02618 /** @brief  Macros to enable or disable the Internal Low Speed oscillator (LSI2).
02619   * @note   After enabling the LSI2, the application software should wait on
02620   *         LSI2RDY flag to be set indicating that LSI2 clock is stable and can
02621   *         be used to clock the IWDG and/or the RTC.
02622   * @retval None
02623   */
02624 #define __HAL_RCC_LSI2_ENABLE()         LL_RCC_LSI2_Enable()
02625 #define __HAL_RCC_LSI2_DISABLE()        LL_RCC_LSI2_Disable()
02626
02627 /** @brief  Macro to adjust the Internal Low Speed oscillator (LSI2) calibration value.
02628   * @note   The calibration is used to compensate for the variations in voltage
02629   *         and temperature that influence the frequency of the internal HSI RC.
02630   * @param  __LSI2TRIMMINGVALUE__ specifies the calibration trimming value
02631   *         This parameter must be a number between Min_data=0 and Max_Data=15.
02632   * @retval None
02633   */
02634 #define __HAL_RCC_LSI2_CALIBRATIONVALUE_ADJUST(__LSI2TRIMMINGVALUE__)  LL_RCC_LSI2_SetTrimming(__LSI2TRIMMINGVALUE__)
02635
02636 /**
02637   * @brief  Macro to configure the External High Speed oscillator (HSE).
02638   * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
02639   *         supported by this macro. User should request a transition to HSE Off
02640   *         first and then HSE On or HSE Bypass.
02641   * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
02642   *         software should wait on HSERDY flag to be set indicating that HSE clock
02643   *         is stable and can be used to clock the PLL and/or system clock.
02644   * @note   HSE state can not be changed if it is used directly or through the
02645   *         PLL as system clock. In this case, you have to select another source
02646   *         of the system clock then change the HSE state (ex. disable it).
02647   * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
02648   * @note   This function reset the CSSON bit, so if the clock security system(CSS)
02649   *         was previously enabled you have to enable it again after calling this
02650   *         function.
02651   * @param  __STATE__  specifies the new state of the HSE.
02652   *         This parameter can be one of the following values:
02653   *            @arg @ref RCC_HSE_OFF  Turn OFF the HSE oscillator, HSERDY flag goes low after
02654   *                              6 HSE oscillator clock cycles.
02655   *            @arg @ref RCC_HSE_ON  Turn ON the HSE oscillator.
02656   *            @arg @ref RCC_HSE_BYPASS  HSE oscillator bypassed with external clock.
02657   * @retval None
02658   */
02659 #define __HAL_RCC_HSE_CONFIG(__STATE__)                      \
02660                     do {                                     \
02661                       if((__STATE__) == RCC_HSE_ON)          \
02662                       {                                      \
02663                        LL_RCC_HSE_Enable();                  \
02664                       }                                      \
02665                       else if((__STATE__) == RCC_HSE_BYPASS) \
02666                       {                                      \
02667                         LL_RCC_HSE_EnableBypass();           \
02668                         LL_RCC_HSE_Enable();                 \
02669                       }                                      \
02670                       else                                   \
02671                       {                                      \
02672                         LL_RCC_HSE_Disable();                \
02673                         LL_RCC_HSE_DisableBypass();          \
02674                       }                                      \
02675                     } while(0U)
02676
02677 /** @brief  Macros to enable or disable the HSE Prescaler
02678   * @note   HSE div2 could be used as Sysclk or PLL entry in Range2
02679   * @retval None
02680   */
02681 #define __HAL_RCC_HSE_DIV2_ENABLE()         LL_RCC_HSE_EnableDiv2()
02682 #define __HAL_RCC_HSE_DIV2_DISABLE()        LL_RCC_HSE_DisableDiv2()
02683
02684 /**
02685   * @brief  Macro to configure the External Low Speed oscillator (LSE).
02686   * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
02687   *         supported by this macro. User should request a transition to LSE Off
02688   *         first and then LSE On or LSE Bypass.
02689   * @note   As the LSE is in the Backup domain and write access is denied to
02690   *         this domain after reset, you have to enable write access using
02691   *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
02692   *         (to be done once after reset).
02693   * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
02694   *         software should wait on LSERDY flag to be set indicating that LSE clock
02695   *         is stable and can be used to clock the RTC.
02696   * @param  __STATE__  specifies the new state of the LSE.
02697   *         This parameter can be one of the following values:
02698   *            @arg @ref RCC_LSE_OFF  Turn OFF the LSE oscillator, LSERDY flag goes low after
02699   *                              6 LSE oscillator clock cycles.
02700   *            @arg @ref RCC_LSE_ON  Turn ON the LSE oscillator.
02701   *            @arg @ref RCC_LSE_BYPASS  LSE oscillator bypassed with external clock.
02702   * @retval None
02703   */
02704 #define __HAL_RCC_LSE_CONFIG(__STATE__)                        \
02705                     do {                                       \
02706                       if((__STATE__) == RCC_LSE_ON)            \
02707                       {                                        \
02708                         LL_RCC_LSE_Enable();                   \
02709                       }                                        \
02710                       else if((__STATE__) == RCC_LSE_BYPASS)   \
02711                       {                                        \
02712                         LL_RCC_LSE_EnableBypass();             \
02713                         LL_RCC_LSE_Enable();                   \
02714                       }                                        \
02715                       else                                     \
02716                       {                                        \
02717                         LL_RCC_LSE_Disable();                  \
02718                         LL_RCC_LSE_DisableBypass();            \
02719                       }                                        \
02720                     } while(0U)
02721
02722
02723 /** @brief  Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48).
02724   * @note   The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
02725   * @note   After enabling the HSI48, the application software should wait on HSI48RDY
02726   *         flag to be set indicating that HSI48 clock is stable.
02727   *         This parameter can be: ENABLE or DISABLE.
02728   * @retval None
02729   */
02730 #define __HAL_RCC_HSI48_ENABLE()  LL_RCC_HSI48_Enable()
02731 #define __HAL_RCC_HSI48_DISABLE() LL_RCC_HSI48_Disable()
02732
02733 /** @brief  Macros to configure HSE sense amplifier threshold.
02734   * @note   to configure HSE sense amplifier, first disable HSE
02735   *         using @ref __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF) macro.
02736   *
02737   * @param  __HSE_AMPTHRES__  specifies the HSE sense amplifier threshold.
02738   *         This parameter can be one of the following values:
02739   *            @arg @ref RCC_HSEAMPTHRESHOLD_1_2  HSE bias current factor 1/2.
02740   *            @arg @ref RCC_HSEAMPTHRESHOLD_3_4  HSE bias current factor 3/4.
02741   * @retval None
02742   */
02743 #define __HAL_RCC_HSE_AMPCONFIG(__HSE_AMPTHRES__)  LL_RCC_HSE_SetSenseAmplifier(__HSE_AMPTHRES__)
02744
02745 /** @brief  Macros to configure HSE current control.
02746   * @note   to configure HSE current control, first disable HSE
02747   *         using @ref __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF) macro.
02748   *
02749   * @param  __HSE_CURRENTMAX__  specifies the HSE current max limit.
02750   *         This parameter can be one of the following values:
02751   *            @arg @ref RCC_HSE_CURRENTMAX_0  HSE current max limit 0.18 mA/V.
02752   *            @arg @ref RCC_HSE_CURRENTMAX_1  HSE current max limit 0.57 mA/V.
02753   *            @arg @ref RCC_HSE_CURRENTMAX_2  HSE current max limit 0.78 mA/V.
02754   *            @arg @ref RCC_HSE_CURRENTMAX_3  HSE current max limit 1.13 mA/V.
02755   *            @arg @ref RCC_HSE_CURRENTMAX_4  HSE current max limit 0.61 mA/V.
02756   *            @arg @ref RCC_HSE_CURRENTMAX_5  HSE current max limit 1.65 mA/V.
02757   *            @arg @ref RCC_HSE_CURRENTMAX_6  HSE current max limit 2.12 mA/V.
02758   *            @arg @ref RCC_HSE_CURRENTMAX_7  HSE current max limit 2.84 mA/V.
02759   * @retval None
02760   */
02761 #define __HAL_RCC_HSE_CURRENTCONFIG(__HSE_CURRENTMAX__)  LL_RCC_HSE_SetCurrentControl(__HSE_CURRENTMAX__)
02762
02763 /** @brief  Macros to configure HSE capacitor tuning.
02764   * @note   to configure HSE current control, first disable HSE
02765   *         using __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF) macro.
02766   *
02767   * @param  __HSE_LOAD_CAPACITANCE__  specifies the HSE capacitor value.
02768   *         This Value Between Min_Data = 0 and Max_Data = 63
02769   * @retval None
02770   */
02771 #define __HAL_RCC_HSE_CAPACITORTUNING(__HSE_LOAD_CAPACITANCE__)  LL_RCC_HSE_SetCapacitorTuning(__HSE_LOAD_CAPACITANCE__)
02772
02773
02774 /** @brief  Macros to configure the RTC clock (RTCCLK).
02775   * @note   As the RTC clock configuration bits are in the Backup domain and write
02776   *         access is denied to this domain after reset, you have to enable write
02777   *         access using the Power Backup Access macro before to configure
02778   *         the RTC clock source (to be done once after reset).
02779   * @note   Once the RTC clock is configured it cannot be changed unless the
02780   *         Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
02781   *         a Power On Reset (POR).
02782   *
02783   * @param  __RTC_CLKSOURCE__  specifies the RTC clock source.
02784   *         This parameter can be one of the following values:*
02785   *            @arg @ref RCC_RTCCLKSOURCE_NONE  none clock selected as RTC clock.
02786   *            @arg @ref RCC_RTCCLKSOURCE_LSE  LSE selected as RTC clock.
02787   *            @arg @ref RCC_RTCCLKSOURCE_LSI  LSI selected as RTC clock.
02788   *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32  HSE clock divided by 32 selected
02789   *
02790   * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
02791   *         work in STOP and STANDBY modes, and can be used as wakeup source.
02792   *         However, when the HSE clock is used as RTC clock source, the RTC
02793   *         cannot be used in STOP and STANDBY modes.
02794   * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
02795   *         RTC clock source).
02796   * @retval None
02797   */
02798 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__)  LL_RCC_SetRTCClockSource(__RTC_CLKSOURCE__)
02799
02800
02801 /** @brief  Macro to get the RTC clock source.
02802   * @retval The returned value can be one of the following:
02803   *            @arg @ref RCC_RTCCLKSOURCE_NONE  none clock selected as RTC clock.
02804   *            @arg @ref RCC_RTCCLKSOURCE_LSE  LSE selected as RTC clock.
02805   *            @arg @ref RCC_RTCCLKSOURCE_LSI  LSI selected as RTC clock.
02806   *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32  HSE clock divided by 32 selected
02807   */
02808 #define  __HAL_RCC_GET_RTC_SOURCE() LL_RCC_GetRTCClockSource()
02809
02810 /** @brief  Macros to enable or disable the main PLL.
02811   * @note   After enabling the main PLL, the application software should wait on
02812   *         PLLRDY flag to be set indicating that PLL clock is stable and can
02813   *         be used as system clock source.
02814   * @note   The main PLL can not be disabled if it is used as system clock source
02815   * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
02816   * @retval None
02817   */
02818 #define __HAL_RCC_PLL_ENABLE()         LL_RCC_PLL_Enable()
02819 #define __HAL_RCC_PLL_DISABLE()        LL_RCC_PLL_Disable()
02820
02821 /** @brief  Macro to configure the PLL clock source.
02822   * @note   This function must be used only when the main PLL is disabled.
02823   * @param  __PLLSOURCE__  specifies the PLL entry clock source.
02824   *         This parameter can be one of the following values:
02825   *            @arg @ref RCC_PLLSOURCE_NONE  No clock selected as PLL clock entry
02826   *            @arg @ref RCC_PLLSOURCE_MSI  MSI oscillator clock selected as PLL clock entry
02827   *            @arg @ref RCC_PLLSOURCE_HSI  HSI oscillator clock selected as PLL clock entry
02828   *            @arg @ref RCC_PLLSOURCE_HSE  HSE oscillator clock selected as PLL clock entry
02829   * @note   This clock source is common for the main PLL and audio PLL (PLL and PLLSAI1).
02830   * @retval None
02831   *
02832   */
02833 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \
02834                   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
02835
02836 /** @brief  Macro to configure the PLL multiplication factor.
02837   * @note   This function must be used only when the main PLL is disabled.
02838   * @param  __PLLM__  specifies the division factor for PLL VCO input clock
02839   *         This parameter must be a value of @ref RCC_PLLM_Clock_Divider.
02840   * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
02841   *         frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
02842   *         of 16 MHz to limit PLL jitter.
02843   * @retval None
02844   *
02845   */
02846 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \
02847                   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
02848
02849 /**
02850   * @brief  Macro to configure the main PLL clock source, multiplication and division factors.
02851   * @note   This function must be used only when the main PLL is disabled.
02852   *
02853   * @param  __PLLSOURCE__  specifies the PLL entry clock source.
02854   *          This parameter can be one of the following values:
02855   *            @arg @ref RCC_PLLSOURCE_NONE  No clock selected as PLL clock entry
02856   *            @arg @ref RCC_PLLSOURCE_MSI  MSI oscillator clock selected as PLL clock entry
02857   *            @arg @ref RCC_PLLSOURCE_HSI  HSI oscillator clock selected as PLL clock entry
02858   *            @arg @ref RCC_PLLSOURCE_HSE  HSE oscillator clock selected as PLL clock entry
02859   * @note   This clock source is common for the main PLL and audio PLL (PLL and PLLSAI1).
02860   *
02861   * @param  __PLLM__  specifies the division factor for PLL VCO input clock.
02862   *         This parameter must be a value of @ref RCC_PLLM_Clock_Divider.
02863   * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
02864   *         frequency ranges from 2.66 to 16 MHz. It is recommended to select a frequency
02865   *         of 16 MHz to limit PLL jitter.
02866   *
02867   * @param  __PLLN__  specifies the multiplication factor for PLL VCO output clock.
02868   *         This parameter must be a number between 6 and 127.
02869   * @note   You have to set the PLLN parameter correctly to ensure that the VCO
02870   *         output frequency is between 96 and 344 MHz.
02871   *
02872   * @param  __PLLP__  specifies the division factor for ADC and SAI1 clock.
02873   *         This parameter must be a value of @ref RCC_PLLP_Clock_Divider.
02874   *
02875   * @param  __PLLQ__  specifies the division factor for USB and RNG clocks.
02876   *         This parameter must be a value of @ref RCC_PLLQ_Clock_Divider
02877   * @note   If the USB FS is used in your application, you have to set the
02878   *         PLLQ parameter correctly to have 48 MHz clock for the USB. However,
02879   *         the RNG need a frequency lower than or equal to 48 MHz to work
02880   *         correctly.
02881   *
02882   * @param  __PLLR__  specifies the division factor for the main system clock.
02883   *         This parameter must be a value of @ref RCC_PLLR_Clock_Divider
02884   * @note   You have to set the PLLR parameter correctly to not exceed 48 MHZ.
02885   * @retval None
02886   */
02887 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
02888                   MODIFY_REG( RCC->PLLCFGR,                                                   \
02889                              (RCC_PLLCFGR_PLLSRC                              |               \
02890                               RCC_PLLCFGR_PLLM                                |               \
02891                               RCC_PLLCFGR_PLLN                                |               \
02892                               RCC_PLLCFGR_PLLP                                |               \
02893                               RCC_PLLCFGR_PLLQ                                |               \
02894                               RCC_PLLCFGR_PLLR),                                              \
02895                              ((uint32_t) (__PLLSOURCE__)                      |               \
02896                               (uint32_t) (__PLLM__)                           |               \
02897                               (uint32_t) ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) |               \
02898                               (uint32_t) (__PLLP__)                           |               \
02899                               (uint32_t) (__PLLQ__)                           |               \
02900                               (uint32_t) (__PLLR__)))
02901
02902 /** @brief  Macro to get the oscillator used as PLL clock source.
02903   * @retval The oscillator used as PLL clock source. The returned value can be one
02904   *         of the following:
02905   *              @arg @ref RCC_PLLSOURCE_NONE No oscillator is used as PLL clock source.
02906   *              @arg @ref RCC_PLLSOURCE_MSI MSI oscillator is used as PLL clock source.
02907   *              @arg @ref RCC_PLLSOURCE_HSI HSI oscillator is used as PLL clock source.
02908   *              @arg @ref RCC_PLLSOURCE_HSE HSE oscillator is used as PLL clock source.
02909   */
02910 #define __HAL_RCC_GET_PLL_OSCSOURCE()  LL_RCC_PLL_GetMainSource()
02911
02912 /**
02913   * @brief  Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_USBCLK, RCC_PLL_SAI1CLK)
02914   * @note   Enabling/disabling clock outputs RCC_PLL_SAI1CLK and RCC_PLL_USBCLK can be done at anytime
02915   *         without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot
02916   *         be stopped if used as System Clock.
02917   * @param  __PLLCLOCKOUT__  specifies the PLL clock to be output.
02918   *          This parameter can be one or a combination of the following values:
02919   *            @arg @ref RCC_PLL_SAI1CLK  This clock is used to generate the clock for SAI
02920   *            @arg @ref RCC_PLL_ADCCLK  This clock is used to generate the clock for ADC
02921   *            @arg @ref RCC_PLL_USBCLK  This Clock is used to generate the clock for the USB FS (48 MHz)
02922   *            @arg @ref RCC_PLL_RNGCLK  This clock is used to generate the clock for RNG
02923   *            @arg @ref RCC_PLL_SYSCLK  This Clock is used to generate the high speed system clock (up to 64MHz)
02924   * @retval None
02925   */
02926 #define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__)   SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
02927
02928 #define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__)  CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
02929
02930 /**
02931   * @brief  Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_USBCLK, RCC_PLL_SAI1CLK)
02932   * @param  __PLLCLOCKOUT__  specifies the output PLL clock to be checked.
02933   *          This parameter can be one of the following values:
02934   *            @arg @ref RCC_PLL_SAI1CLK  This clock is used to generate an accurate clock to achieve high-quality audio performance on SAI interface
02935   *            @arg @ref RCC_PLL_ADCCLK  same
02936   *            @arg @ref RCC_PLL_USBCLK  This Clock is used to generate the clock for the USB FS (48 MHz)
02937   *            @arg @ref RCC_PLL_RNGCLK  same
02938   *            @arg @ref RCC_PLL_SYSCLK  This Clock is used to generate the high speed system clock (up to 64MHz)
02939   * @retval SET / RESET
02940   */
02941 #define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__)  READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
02942
02943 /**
02944   * @brief  Macro to configure the system clock source.
02945   * @param  __SYSCLKSOURCE__  specifies the system clock source.
02946   *          This parameter can be one of the following values:
02947   *              @arg @ref RCC_SYSCLKSOURCE_MSI MSI oscillator is used as system clock source.
02948   *              @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
02949   *              @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
02950   *              @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
02951   * @retval None
02952   */
02953 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__)  LL_RCC_SetSysClkSource(__SYSCLKSOURCE__)
02954
02955 /** @brief  Macro to get the clock source used as system clock.
02956   * @retval The clock source used as system clock. The returned value can be one
02957   *         of the following:
02958   *              @arg @ref RCC_SYSCLKSOURCE_STATUS_MSI MSI used as system clock.
02959   *              @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock.
02960   *              @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock.
02961   *              @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock.
02962   */
02963 #define __HAL_RCC_GET_SYSCLK_SOURCE()  LL_RCC_GetSysClkSource()
02964
02965 /**
02966   * @brief  Macro to configure the External Low Speed oscillator (LSE) drive capability.
02967   * @note   As the LSE is in the Backup domain and write access is denied to
02968   *         this domain after reset, you have to enable write access using
02969   *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
02970   *         (to be done once after reset).
02971   * @param  __LSEDRIVE__  specifies the new state of the LSE drive capability.
02972   *          This parameter can be one of the following values:
02973   *            @arg @ref RCC_LSEDRIVE_LOW  LSE oscillator low drive capability.
02974   *            @arg @ref RCC_LSEDRIVE_MEDIUMLOW  LSE oscillator medium low drive capability.
02975   *            @arg @ref RCC_LSEDRIVE_MEDIUMHIGH  LSE oscillator medium high drive capability.
02976   *            @arg @ref RCC_LSEDRIVE_HIGH  LSE oscillator high drive capability.
02977   * @retval None
02978   */
02979 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__)  LL_RCC_LSE_SetDriveCapability(__LSEDRIVE__)
02980
02981 /**
02982   * @brief  Macro to configure the wake up from stop clock.
02983   * @param  __STOPWUCLK__  specifies the clock source used after wake up from stop.
02984   *         This parameter can be one of the following values:
02985   *            @arg @ref RCC_STOP_WAKEUPCLOCK_MSI  MSI selected as system clock source
02986   *            @arg @ref RCC_STOP_WAKEUPCLOCK_HSI  HSI selected as system clock source
02987   * @retval None
02988   */
02989 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__)  LL_RCC_SetClkAfterWakeFromStop(__STOPWUCLK__)
02990
02991
02992 /** @brief  Macro to configure the MCO clock.
02993   * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
02994   *          This parameter can be one of the following values:
02995   *            @arg @ref RCC_MCO1SOURCE_NOCLOCK  MCO output disabled
02996   *            @arg @ref RCC_MCO1SOURCE_SYSCLK  System  clock selected as MCO source
02997   *            @arg @ref RCC_MCO1SOURCE_MSI     MSI clock selected as MCO source
02998   *            @arg @ref RCC_MCO1SOURCE_HSI     HSI clock selected as MCO source
02999   *            @arg @ref RCC_MCO1SOURCE_HSE     HSE clock selected as MCO sourcee
03000   *            @arg @ref RCC_MCO1SOURCE_PLLCLK  Main PLL clock selected as MCO source
03001   *            @arg @ref RCC_MCO1SOURCE_LSI1    LSI1 clock selected as MCO source
03002   *            @arg @ref RCC_MCO1SOURCE_LSI2    LSI2 clock selected as MCO source
03003   *            @arg @ref RCC_MCO1SOURCE_LSE     LSE clock selected as MCO source
03004   *            @arg @ref RCC_MCO1SOURCE_HSI48    HSI48 clock selected as MCO source
03005
03006   * @param  __MCODIV__ specifies the MCO clock prescaler.
03007   *          This parameter can be one of the following values:
03008   *            @arg @ref RCC_MCODIV_1   MCO clock source is divided by 1
03009   *            @arg @ref RCC_MCODIV_2   MCO clock source is divided by 2
03010   *            @arg @ref RCC_MCODIV_4   MCO clock source is divided by 4
03011   *            @arg @ref RCC_MCODIV_8   MCO clock source is divided by 8
03012   *            @arg @ref RCC_MCODIV_16  MCO clock source is divided by 16
03013   */
03014 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__)  LL_RCC_ConfigMCO((__MCOCLKSOURCE__), (__MCODIV__))
03015
03016
03017 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
03018   * @brief macros to manage the specified RCC Flags and interrupts.
03019   * @{
03020   */
03021
03022 /** @brief  Enable RCC interrupt.
03023   * @param  __INTERRUPT__  specifies the RCC interrupt sources to be enabled.
03024   *         This parameter can be any combination of the following values:
03025   *            @arg @ref RCC_IT_LSI1RDY     LSI1 ready interrupt enable
03026   *            @arg @ref RCC_IT_LSERDY      LSE ready interrupt enable
03027   *            @arg @ref RCC_IT_MSIRDY      HSI ready interrupt enable
03028   *            @arg @ref RCC_IT_HSIRDY      HSI ready interrupt enable
03029   *            @arg @ref RCC_IT_HSERDY      HSE ready interrupt enable
03030   *            @arg @ref RCC_IT_PLLRDY      Main PLL ready interrupt enable
03031   *            @arg @ref RCC_IT_PLLSAI1RDY  PLLSAI1 ready interrupt enable
03032   *            @arg @ref RCC_IT_LSECSS      LSE Clock security system interrupt enable
03033   *            @arg @ref RCC_IT_HSI48RDY PLLHSI48 ready interrupt enable
03034   *            @arg @ref RCC_IT_LSI2RDY     LSI2 ready interrupt enable
03035   * @retval None
03036   */
03037 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
03038
03039 /** @brief Disable RCC interrupt.
03040   * @param  __INTERRUPT__  specifies the RCC interrupt sources to be disabled.
03041     *         This parameter can be any combination of the following values:
03042   *            @arg @ref RCC_IT_LSI1RDY     LSI1 ready interrupt enable
03043   *            @arg @ref RCC_IT_LSERDY      LSE ready interrupt enable
03044   *            @arg @ref RCC_IT_MSIRDY      HSI ready interrupt enable
03045   *            @arg @ref RCC_IT_HSIRDY      HSI ready interrupt enable
03046   *            @arg @ref RCC_IT_HSERDY      HSE ready interrupt enable
03047   *            @arg @ref RCC_IT_PLLRDY      Main PLL ready interrupt enable
03048   *            @arg @ref RCC_IT_PLLSAI1RDY  PLLSAI1 ready interrupt enable
03049   *            @arg @ref RCC_IT_LSECSS      LSE Clock security system interrupt enable
03050   *            @arg @ref RCC_IT_HSI48RDY    PLLHSI48 ready interrupt enable
03051   *            @arg @ref RCC_IT_LSI2RDY     LSI2 ready interrupt enable
03052   * @retval None
03053   */
03054 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
03055
03056 /** @brief  Clear RCC interrupt pending bits (Perform Byte access to RCC_CICR[17:0]
03057   *         bits to clear the selected interrupt pending bits.
03058   * @param  __INTERRUPT__  specifies the interrupt pending bit to clear.
03059   *         This parameter can be any combination of the following values:
03060   *            @arg @ref RCC_IT_LSI1RDY  LSI1 ready interrupt clear
03061   *            @arg @ref RCC_IT_LSERDY   LSE ready interrupt clear
03062   *            @arg @ref RCC_IT_MSIRDY   HSI ready interrupt clear
03063   *            @arg @ref RCC_IT_HSIRDY   HSI ready interrupt clear
03064   *            @arg @ref RCC_IT_HSERDY   HSE ready interrupt clear
03065   *            @arg @ref RCC_IT_PLLRDY   Main PLL ready interrupt clear
03066   *            @arg @ref RCC_IT_PLLRDY   PLLSAI1 ready interrupt clear
03067   *            @arg @ref RCC_IT_HSECSS   HSE Clock security system interrupt clear
03068   *            @arg @ref RCC_IT_LSECSS   LSE Clock security system interrupt clear
03069   *            @arg @ref RCC_IT_HSI48RDY PLLHSI48 ready interrupt clear
03070   *            @arg @ref RCC_IT_LSI2RDY  LSI2 ready interrupt clear
03071   */
03072 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
03073
03074 /** @brief  Check whether the RCC interrupt has occurred or not.
03075   * @param  __INTERRUPT__  specifies the RCC interrupt source to check.
03076   *         This parameter can be one of the following values:
03077   *            @arg @ref RCC_IT_LSI1RDY  LSI1 ready interrupt flag
03078   *            @arg @ref RCC_IT_LSERDY   LSE ready interrupt flag
03079   *            @arg @ref RCC_IT_MSIRDY   HSI ready interrupt flag
03080   *            @arg @ref RCC_IT_HSIRDY   HSI ready interrupt flag
03081   *            @arg @ref RCC_IT_HSERDY   HSE ready interrupt flag
03082   *            @arg @ref RCC_IT_PLLRDY   Main PLL ready interrupt flag
03083   *            @arg @ref RCC_IT_PLLRDY   PLLSAI1 ready interrupt flag
03084   *            @arg @ref RCC_IT_HSECSS   HSE Clock security system interrupt flag
03085   *            @arg @ref RCC_IT_LSECSS   LSE Clock security system interrupt flag
03086   *            @arg @ref RCC_IT_HSI48RDY PLLHSI48 ready interrupt flag
03087   *            @arg @ref RCC_IT_LSI2RDY  LSI2 ready interrupt flag
03088   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
03089   */
03090 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
03091
03092 /** @brief Set RMVF bit to clear the reset flags.
03093   *        The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST,
03094   *        RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
03095   * @retval None
03096  */
03097 #define __HAL_RCC_CLEAR_RESET_FLAGS() LL_RCC_ClearResetFlags()
03098
03099 /** @brief  Check whether the selected RCC flag is set or not.
03100   * @param  __FLAG__  specifies the flag to check.
03101   *         This parameter can be one of the following values:
03102   *            @arg @ref RCC_FLAG_MSIRDY  MSI oscillator clock ready
03103   *            @arg @ref RCC_FLAG_HSIRDY  HSI oscillator clock ready
03104   *            @arg @ref RCC_FLAG_HSERDY  HSE oscillator clock ready
03105   *            @arg @ref RCC_FLAG_PLLRDY  Main PLL clock ready
03106   *            @arg @ref RCC_FLAG_PLLRDY  PLLSAI1 clock ready
03107   *            @arg @ref RCC_FLAG_HSI48RDY  HSI48 clock ready for devices with HSI48
03108   *            @arg @ref RCC_FLAG_LSERDY  LSE oscillator clock ready
03109   *            @arg @ref RCC_FLAG_LSECSSD  Clock security system failure on LSE oscillator detection
03110   *            @arg @ref RCC_FLAG_LSI1RDY  LSI1 oscillator clock ready
03111   *            @arg @ref RCC_FLAG_LSI2RDY  LSI2 oscillator clock ready
03112   *            @arg @ref RCC_FLAG_BORRST  BOR reset
03113   *            @arg @ref RCC_FLAG_OBLRST  OBLRST reset
03114   *            @arg @ref RCC_FLAG_PINRST  Pin reset
03115   *            @arg @ref RCC_FLAG_SFTRST  Software reset
03116   *            @arg @ref RCC_FLAG_IWDGRST  Independent Watchdog reset
03117   *            @arg @ref RCC_FLAG_WWDGRST  Window Watchdog reset
03118   *            @arg @ref RCC_FLAG_LPWRRST  Low Power reset
03119   * @retval The new state of __FLAG__ (TRUE or FALSE).
03120   */
03121 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR :                     \
03122                                         ((((__FLAG__) >> 5U) == CRRCR_REG_INDEX) ? RCC->CRRCR :                  \
03123                                         ((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR :                   \
03124                                         ((((__FLAG__) >> 5U) == CSR_REG_INDEX) ? RCC->CSR : RCC->CIFR)))) &    \
03125                                         (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) \
03126                                          ? 1U : 0U)
03127
03128 /**
03129   * @}
03130   */
03131
03132 /**
03133   * @}
03134   */
03135
03136 /* Include RCC HAL Extended module */
03137 #include "stm32wbxx_hal_rcc_ex.h"
03138
03139 /* Exported functions --------------------------------------------------------*/
03140 /** @addtogroup RCC_Exported_Functions
03141   * @{
03142   */
03143
03144
03145 /** @addtogroup RCC_Exported_Functions_Group1
03146   * @{
03147   */
03148
03149 /* Initialization and de-initialization functions  ******************************/
03150 HAL_StatusTypeDef HAL_RCC_DeInit(void);
03151 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
03152 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
03153
03154 /**
03155   * @}
03156   */
03157
03158 /** @addtogroup RCC_Exported_Functions_Group2
03159   * @{
03160   */
03161
03162 /* Peripheral Control functions  ************************************************/
03163 void              HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
03164 void              HAL_RCC_EnableCSS(void);
03165 uint32_t          HAL_RCC_GetSysClockFreq(void);
03166
03167 uint32_t          HAL_RCC_GetHCLKFreq(void);
03168 uint32_t          HAL_RCC_GetHCLK2Freq(void);
03169 uint32_t          HAL_RCC_GetHCLK4Freq(void);
03170
03171 uint32_t          HAL_RCC_GetPCLK1Freq(void);
03172 uint32_t          HAL_RCC_GetPCLK2Freq(void);
03173
03174 void              HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
03175 void              HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
03176 /* LSE & HSE CSS NMI IRQ handler */
03177 void              HAL_RCC_NMI_IRQHandler(void);
03178 /* User Callbacks in non blocking mode (IT mode) */
03179 void              HAL_RCC_CSSCallback(void);
03180
03181 /**
03182   * @}
03183   */
03184
03185 /**
03186   * @}
03187   */
03188
03189 /**
03190   * @}
03191   */
03192
03193 /**
03194   * @}
03195   */
03196
03197 #ifdef __cplusplus
03198 }
03199 #endif
03200
03201 #endif /* STM32WBxx_HAL_RCC_H */
03202
03203 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
03204
Generated on Fri Sep 6 2019 11:34:35 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_rcc_ex.c Source File

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stm32wbxx_hal_rcc_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_rcc_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended RCC HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities RCC extended peripheral:
00008   *           + Extended Peripheral Control functions
00009   *           + Extended Clock management functions
00010   *           + Extended Clock Recovery System Control functions
00011   *
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00016   * All rights reserved.</center></h2>
00017   *
00018   * This software component is licensed by ST under BSD 3-Clause license,
00019   * the "License"; You may not use this file except in compliance with the
00020   * License. You may obtain a copy of the License at:
00021   *                        opensource.org/licenses/BSD-3-Clause
00022   *
00023   ******************************************************************************
00024   */
00025
00026 /* Includes ------------------------------------------------------------------*/
00027 #include "stm32wbxx_hal.h"
00028
00029 /** @addtogroup STM32WBxx_HAL_Driver
00030   * @{
00031   */
00032
00033 /** @defgroup RCCEx RCCEx
00034   * @brief RCC Extended HAL module driver
00035   * @{
00036   */
00037
00038 #ifdef HAL_RCC_MODULE_ENABLED
00039
00040 /* Private typedef -----------------------------------------------------------*/
00041 /* Private defines -----------------------------------------------------------*/
00042 /** @defgroup RCCEx_Private_Constants RCCEx Private Constants
00043  * @{
00044  */
00045 #define PLLSAI1_TIMEOUT_VALUE    (2U)    /* 2 ms (minimum Tick + 1) */
00046 #define PLL_TIMEOUT_VALUE        (2U)    /* 2 ms (minimum Tick + 1) */
00047
00048 #define CLOCKSMPS_TIMEOUT_VALUE  (5000U) /* 5 s    */
00049
00050 #define __LSCO1_CLK_ENABLE()   __HAL_RCC_GPIOA_CLK_ENABLE()
00051 #define LSCO1_GPIO_PORT        GPIOA
00052 #define LSCO1_PIN              GPIO_PIN_2
00053
00054 #define __LSCO2_CLK_ENABLE()   __HAL_RCC_GPIOH_CLK_ENABLE()
00055 #define LSCO2_GPIO_PORT        GPIOH
00056 #define LSCO2_PIN              GPIO_PIN_3
00057
00058 #define __LSCO3_CLK_ENABLE()   __HAL_RCC_GPIOC_CLK_ENABLE()
00059 #define LSCO3_GPIO_PORT        GPIOC
00060 #define LSCO3_PIN              GPIO_PIN_12
00061
00062 #define LSI2_TIMEOUT_VALUE         (3U)    /* to be adjusted with DS    */
00063
00064 /**
00065   * @}
00066   */
00067
00068 /* Private macros ------------------------------------------------------------*/
00069 /* Private variables ---------------------------------------------------------*/
00070 /* Private function prototypes -----------------------------------------------*/
00071 /** @defgroup RCCEx_Private_Functions RCCEx Private Functions
00072  * @{
00073  */
00074 #if defined(SAI1)
00075 static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNP(RCC_PLLSAI1InitTypeDef *PLLSAI1);
00076 static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNQ(RCC_PLLSAI1InitTypeDef *PLLSAI1);
00077 static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNR(RCC_PLLSAI1InitTypeDef *PLLSAI1);
00078 #endif
00079
00080 static uint32_t          RCC_PLL_GetFreqDomain_P(void);
00081 static uint32_t          RCC_PLL_GetFreqDomain_Q(void);
00082
00083 #if defined(SAI1)
00084 static uint32_t          RCC_PLLSAI1_GetFreqDomain_R(void);
00085 static uint32_t          RCC_PLLSAI1_GetFreqDomain_P(void);
00086 static uint32_t          RCC_PLLSAI1_GetFreqDomain_Q(void);
00087 #endif
00088
00089 /**
00090   * @}
00091   */
00092
00093 /* Exported functions --------------------------------------------------------*/
00094
00095 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
00096   * @{
00097   */
00098
00099 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
00100  *  @brief  Extended Peripheral Control functions
00101  *
00102 @verbatim
00103  ===============================================================================
00104                 ##### Extended Peripheral Control functions  #####
00105  ===============================================================================
00106     [..]
00107     This subsection provides a set of functions allowing to control the RCC Clocks
00108     frequencies.
00109     [..]
00110     (@) Important note: Care must be taken when @ref HAL_RCCEx_PeriphCLKConfig() is used to
00111         select the RTC clock source; in this case the Backup domain will be reset in
00112         order to modify the RTC Clock source, as consequence RTC registers (including
00113         the backup registers) and RCC_BDCR register are set to their reset values.
00114
00115 @endverbatim
00116   * @{
00117   */
00118
00119 /**
00120   * @brief  Initialize the RCC extended peripherals clocks according to the specified
00121   *         parameters in the @ref RCC_PeriphCLKInitTypeDef.
00122   * @param  PeriphClkInit  pointer to a @ref RCC_PeriphCLKInitTypeDef structure that
00123   *         contains a field PeriphClockSelection which can be a combination of the following values:
00124   *
00125   *            @arg @ref RCC_PERIPHCLK_USART1   USART1 peripheral clock
00126   *            @arg @ref RCC_PERIPHCLK_LPUART1  LPUART1 peripheral clock
00127   *            @arg @ref RCC_PERIPHCLK_I2C1     I2C1 peripheral clock
00128   *            @arg @ref RCC_PERIPHCLK_I2C3     I2C3 peripheral clock
00129   *            @arg @ref RCC_PERIPHCLK_LPTIM1   LPTIM1 peripheral clock
00130   *            @arg @ref RCC_PERIPHCLK_LPTIM2   LPTIM2 peripheral clock
00131   *
00132   *            @arg @ref RCC_PERIPHCLK_SAI1     SAI1 peripheral clock
00133   *            @arg @ref RCC_PERIPHCLK_USB      USB peripheral clock
00134   *            @arg @ref RCC_PERIPHCLK_RNG      RNG peripheral clock
00135   *
00136   *            @arg @ref RCC_PERIPHCLK_ADC      ADC peripheral clock
00137   *            @arg @ref RCC_PERIPHCLK_RTC      RTC peripheral clock
00138   *
00139   *            @arg @ref RCC_PERIPHCLK_RFWAKEUP RFWKP peripheral clock
00140   *            @arg @ref RCC_PERIPHCLK_SMPS     SMPS peripheral clock
00141   *
00142   *
00143   * @note   Care must be taken when @ref HAL_RCCEx_PeriphCLKConfig() is used to select
00144   *         the RTC clock source: in this case the access to Backup domain is enabled.
00145   *
00146   * @retval HAL status
00147   */
00148 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
00149 {
00150   uint32_t tickstart;
00151   HAL_StatusTypeDef ret     = HAL_OK;      /* Intermediate status */
00152   HAL_StatusTypeDef status  = HAL_OK;   /* Final status */
00153
00154   /* Check the parameters */
00155   assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
00156
00157 #if defined(SAI1)
00158   /*-------------------------- SAI1 clock source configuration ---------------------*/
00159   if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1))
00160   {
00161     /* Check the parameters */
00162     assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection));
00163
00164     switch (PeriphClkInit->Sai1ClockSelection)
00165     {
00166       case RCC_SAI1CLKSOURCE_PLL:      /* PLL is used as clock source for SAI1 */
00167         /* Enable SAI1 Clock output generated form System PLL . */
00168         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI1CLK);
00169
00170         /* SAI1 clock source config set later after clock selection check */
00171         break;
00172
00173       case RCC_SAI1CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI1 */
00174         /* PLLSAI1 parameters N & P configuration and clock output (PLLSAI1ClockOut) */
00175         ret = RCCEx_PLLSAI1_ConfigNP(&(PeriphClkInit->PLLSAI1));
00176         /* SAI1 clock source config set later after clock selection check */
00177         break;
00178
00179
00180       case RCC_SAI1CLKSOURCE_PIN:      /* External clock is used as source of SAI1 clock*/
00181         /* SAI1 clock source config set later after clock selection check */
00182         break;
00183
00184       case RCC_SAI1CLKSOURCE_HSI:
00185
00186         break;
00187
00188       default:
00189         ret = HAL_ERROR;
00190         break;
00191     }
00192
00193     if (ret == HAL_OK)
00194     {
00195       /* Set the source of SAI1 clock*/
00196       __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
00197     }
00198     else
00199     {
00200       /* set overall return value */
00201       status = ret;
00202     }
00203   }
00204 #endif
00205
00206   /*-------------------------- RTC clock source configuration ----------------------*/
00207   if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
00208   {
00209     uint32_t rtcclocksource = LL_RCC_GetRTCClockSource();
00210
00211     /* Check for RTC Parameters used to output RTCCLK */
00212     assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
00213
00214     /* Configure the clock source only if a different source is expected */
00215     if (rtcclocksource != PeriphClkInit->RTCClockSelection)
00216     {
00217       /* Enable write access to Backup domain */
00218       HAL_PWR_EnableBkUpAccess();
00219
00220       /* If a clock source is not yet selected */
00221       if (rtcclocksource == RCC_RTCCLKSOURCE_NONE)
00222       {
00223         /* Directly set the configuration of the clock source selection */
00224         LL_RCC_SetRTCClockSource(PeriphClkInit->RTCClockSelection);
00225       }
00226       else /* A clock source is already selected */
00227       {
00228         /* Store the content of BDCR register before the reset of Backup Domain */
00229         uint32_t bdcr = LL_RCC_ReadReg(BDCR);
00230
00231         /* RTC Clock selection can be changed only if the Backup Domain is reset */
00232         LL_RCC_ForceBackupDomainReset();
00233         LL_RCC_ReleaseBackupDomainReset();
00234
00235         /* Set the value of the clock source selection */
00236         MODIFY_REG(bdcr, RCC_BDCR_RTCSEL, PeriphClkInit->RTCClockSelection);
00237
00238         /* Restore the content of BDCR register */
00239         LL_RCC_WriteReg(BDCR, bdcr);
00240
00241         /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
00242         if (LL_RCC_LSE_IsEnabled() == 1U)
00243         {
00244           /* Get Start Tick*/
00245           tickstart = HAL_GetTick();
00246
00247           /* Wait till LSE is ready */
00248           while (LL_RCC_LSE_IsReady() != 1U)
00249           {
00250             if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
00251             {
00252               ret = HAL_TIMEOUT;
00253               break;
00254             }
00255           }
00256         }
00257       }
00258
00259       /* set overall return value */
00260       status = ret;
00261     }
00262     else
00263     {
00264       /* set overall return value */
00265       status = ret;
00266     }
00267
00268   }
00269
00270   /*-------------------------- USART1 clock source configuration -------------------*/
00271   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
00272   {
00273     /* Check the parameters */
00274     assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
00275
00276     /* Configure the USART1 clock source */
00277     __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
00278   }
00279
00280 #if defined(LPUART1)
00281   /*-------------------------- LPUART1 clock source configuration ------------------*/
00282   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
00283   {
00284     /* Check the parameters */
00285     assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
00286
00287     /* Configure the LPUAR1 clock source */
00288     __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
00289   }
00290 #endif
00291
00292   /*-------------------------- LPTIM1 clock source configuration -------------------*/
00293   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
00294   {
00295     assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
00296     __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
00297   }
00298
00299   /*-------------------------- LPTIM2 clock source configuration -------------------*/
00300   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
00301   {
00302     assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection));
00303     __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
00304   }
00305
00306   /*-------------------------- I2C1 clock source configuration ---------------------*/
00307   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
00308   {
00309     /* Check the parameters */
00310     assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
00311
00312     /* Configure the I2C1 clock source */
00313     __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
00314   }
00315
00316 #if defined(I2C3)
00317   /*-------------------------- I2C3 clock source configuration ---------------------*/
00318   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
00319   {
00320     /* Check the parameters */
00321     assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
00322
00323     /* Configure the I2C3 clock source */
00324     __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
00325   }
00326 #endif
00327
00328   /*-------------------------- USB clock source configuration ----------------------*/
00329   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
00330   {
00331     assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
00332     __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
00333
00334     if (PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
00335     {
00336       /* Enable PLLQ output */
00337       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_USBCLK);
00338     }
00339
00340 #if defined(SAI1)
00341     if (PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1)
00342     {
00343       /* PLLSAI1 parameters N & Q configuration and clock output (PLLSAI1ClockOut) */
00344       ret = RCCEx_PLLSAI1_ConfigNQ(&(PeriphClkInit->PLLSAI1));
00345
00346       if (ret != HAL_OK)
00347       {
00348         /* set overall return value */
00349         status = ret;
00350       }
00351     }
00352 #endif
00353   }
00354
00355   /*-------------------------- RNG clock source configuration ----------------------*/
00356   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
00357   {
00358     /* Check the parameters */
00359     assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
00360
00361     /* Configure the RNG clock source */
00362     __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
00363
00364     if (PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
00365     {
00366       /* Enable PLLQ output */
00367       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_RNGCLK);
00368     }
00369   }
00370
00371   /*-------------------------- ADC clock source configuration ----------------------*/
00372   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
00373   {
00374     /* Check the parameters */
00375     assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
00376
00377     /* Configure the ADC interface clock source */
00378     __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
00379
00380     if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLL)
00381     {
00382       /* Enable RCC_PLL_RNGCLK output */
00383       __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK);
00384     }
00385
00386 #if defined(SAI1)
00387     if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1)
00388     {
00389       /* PLLSAI1 parameters N & R configuration and clock output (PLLSAI1ClockOut) */
00390       ret = RCCEx_PLLSAI1_ConfigNR(&(PeriphClkInit->PLLSAI1));
00391
00392       if (ret != HAL_OK)
00393       {
00394         /* set overall return value */
00395         status = ret;
00396       }
00397     }
00398 #endif
00399   }
00400
00401   /*-------------------------- RFWKP clock source configuration ----------------------*/
00402   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RFWAKEUP) == RCC_PERIPHCLK_RFWAKEUP)
00403   {
00404     /* Check the parameters */
00405     assert_param(IS_RCC_RFWKPCLKSOURCE(PeriphClkInit->RFWakeUpClockSelection));
00406
00407     /* Configure the RFWKP interface clock source */
00408     __HAL_RCC_RFWAKEUP_CONFIG(PeriphClkInit->RFWakeUpClockSelection);
00409
00410   }
00411
00412 #if defined(RCC_SMPS_SUPPORT)
00413   /*-------------------------- SMPS clock source configuration ----------------------*/
00414   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SMPS) == RCC_PERIPHCLK_SMPS)
00415   {
00416     /* Check the parameters */
00417     assert_param(IS_RCC_SMPSCLKDIV(PeriphClkInit->SmpsDivSelection));
00418     assert_param(IS_RCC_SMPSCLKSOURCE(PeriphClkInit->SmpsClockSelection));
00419
00420     /* Configure the SMPS interface clock division factor */
00421     __HAL_RCC_SMPS_DIV_CONFIG(PeriphClkInit->SmpsDivSelection);
00422
00423     /* Configure the SMPS interface clock source */
00424     __HAL_RCC_SMPS_CONFIG(PeriphClkInit->SmpsClockSelection);
00425   }
00426 #endif
00427
00428   return status;
00429 }
00430
00431
00432 /**
00433   * @brief  Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
00434   * @param  PeriphClkInit  pointer to an RCC_PeriphCLKInitTypeDef structure that
00435   *         returns the configuration information for the Extended Peripherals
00436   *         clocks(SAI1, LPTIM1, LPTIM2, I2C1, I2C3, LPUART1,
00437   *         USART1, RTC, ADCx, USB, RNG, RFWKP, SMPS).
00438   * @retval None
00439   */
00440 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
00441 {
00442   /* Set all possible values for the extended clock type parameter------------*/
00443
00444   PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1   | \
00445                                         RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \
00446                                         RCC_PERIPHCLK_RNG    | RCC_PERIPHCLK_ADC    | \
00447                                         RCC_PERIPHCLK_RTC    | RCC_PERIPHCLK_RFWAKEUP;
00448 #if defined(LPUART1)
00449   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LPUART1;
00450 #endif
00451
00452 #if defined(I2C3)
00453   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C3;
00454 #endif
00455
00456 #if defined(SAI1)
00457   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI1;
00458 #endif
00459
00460   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;
00461
00462 #if defined(RCC_SMPS_SUPPORT)
00463   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SMPS;
00464 #endif
00465
00466 #if defined(SAI1)
00467   /* Get the PLLSAI1 Clock configuration -----------------------------------------------*/
00468   PeriphClkInit->PLLSAI1.PLLN = LL_RCC_PLLSAI1_GetN();
00469   PeriphClkInit->PLLSAI1.PLLP = LL_RCC_PLLSAI1_GetP();
00470   PeriphClkInit->PLLSAI1.PLLR = LL_RCC_PLLSAI1_GetR();
00471   PeriphClkInit->PLLSAI1.PLLQ = LL_RCC_PLLSAI1_GetQ();
00472 #endif
00473
00474   /* Get the USART1 clock source ---------------------------------------------*/
00475   PeriphClkInit->Usart1ClockSelection   = __HAL_RCC_GET_USART1_SOURCE();
00476
00477 #if defined(LPUART1)
00478   /* Get the LPUART1 clock source --------------------------------------------*/
00479   PeriphClkInit->Lpuart1ClockSelection  = __HAL_RCC_GET_LPUART1_SOURCE();
00480 #endif
00481
00482   /* Get the I2C1 clock source -----------------------------------------------*/
00483   PeriphClkInit->I2c1ClockSelection     = __HAL_RCC_GET_I2C1_SOURCE();
00484
00485 #if defined(I2C3)
00486   /* Get the I2C3 clock source -----------------------------------------------*/
00487   PeriphClkInit->I2c3ClockSelection     = __HAL_RCC_GET_I2C3_SOURCE();
00488 #endif
00489
00490   /* Get the LPTIM1 clock source ---------------------------------------------*/
00491   PeriphClkInit->Lptim1ClockSelection   = __HAL_RCC_GET_LPTIM1_SOURCE();
00492
00493   /* Get the LPTIM2 clock source ---------------------------------------------*/
00494   PeriphClkInit->Lptim2ClockSelection   = __HAL_RCC_GET_LPTIM2_SOURCE();
00495
00496 #if defined(SAI1)
00497   /* Get the SAI1 clock source -----------------------------------------------*/
00498   PeriphClkInit->Sai1ClockSelection     = __HAL_RCC_GET_SAI1_SOURCE();
00499 #endif
00500
00501   /* Get the RTC clock source ------------------------------------------------*/
00502   PeriphClkInit->RTCClockSelection      = __HAL_RCC_GET_RTC_SOURCE();
00503
00504   /* Get the USB clock source ------------------------------------------------*/
00505   PeriphClkInit->UsbClockSelection      = __HAL_RCC_GET_USB_SOURCE();
00506
00507   /* Get the RNG clock source ------------------------------------------------*/
00508   PeriphClkInit->RngClockSelection      = HAL_RCCEx_GetRngCLKSource();
00509
00510   /* Get the ADC clock source ------------------------------------------------*/
00511   PeriphClkInit->AdcClockSelection      = __HAL_RCC_GET_ADC_SOURCE();
00512
00513   /* Get the RFWKP clock source ----------------------------------------------*/
00514   PeriphClkInit->RFWakeUpClockSelection = __HAL_RCC_GET_RFWAKEUP_SOURCE();
00515
00516 #if defined(RCC_SMPS_SUPPORT)
00517   /* Get the SMPS clock division factor --------------------------------------*/
00518   PeriphClkInit->SmpsDivSelection       = __HAL_RCC_GET_SMPS_DIV();
00519
00520   /* Get the SMPS clock source -----------------------------------------------*/
00521   PeriphClkInit->SmpsClockSelection     = __HAL_RCC_GET_SMPS_SOURCE();
00522 #endif
00523 }
00524
00525 /**
00526   * @brief  Return the peripheral clock frequency for peripherals with clock source
00527   * @note   Return 0 if peripheral clock identifier not managed by this API
00528   * @param  PeriphClk  Peripheral clock identifier
00529   *         This parameter can be one of the following values:
00530   *            @arg @ref RCC_PERIPHCLK_RTC  RTC peripheral clock
00531   *            @arg @ref RCC_PERIPHCLK_ADC  ADC peripheral clock
00532   *            @arg @ref RCC_PERIPHCLK_I2C1  I2C1 peripheral clock
00533   *            @arg @ref RCC_PERIPHCLK_I2C3  I2C3 peripheral clock
00534   *            @arg @ref RCC_PERIPHCLK_LPTIM1  LPTIM1 peripheral clock
00535   *            @arg @ref RCC_PERIPHCLK_LPTIM2  LPTIM2 peripheral clock
00536   *            @arg @ref RCC_PERIPHCLK_LPUART1  LPUART1 peripheral clock
00537   *            @arg @ref RCC_PERIPHCLK_RNG  RNG peripheral clock
00538   *            @arg @ref RCC_PERIPHCLK_SAI1  SAI1 peripheral clock
00539   *            @arg @ref RCC_PERIPHCLK_USART1  USART1 peripheral clock
00540   *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock
00541   *
00542   *            @arg @ref RCC_PERIPHCLK_RFWAKEUP  RFWKP peripheral clock
00543   *            @arg @ref RCC_PERIPHCLK_SMPS  SMPS peripheral clock
00544   * @retval Frequency in Hz
00545   */
00546 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
00547 {
00548   uint32_t frequency;
00549
00550 #if defined(RCC_SMPS_SUPPORT)
00551   uint32_t smps_prescaler_index = ((LL_RCC_GetSMPSPrescaler()) >> RCC_SMPSCR_SMPSDIV_Pos);
00552 #endif
00553
00554   /* Check the parameters */
00555   assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
00556
00557   if (PeriphClk == RCC_PERIPHCLK_RTC)
00558   {
00559     uint32_t rtcClockSource = LL_RCC_GetRTCClockSource();
00560
00561     if (rtcClockSource == LL_RCC_RTC_CLKSOURCE_LSE) /* LSE clock used as RTC clock source */
00562     {
00563       if (LL_RCC_LSE_IsReady() == 1U)
00564       {
00565         frequency = LSE_VALUE;
00566       }
00567       else
00568       {
00569         frequency = 0U;
00570       }
00571     }
00572     else if (rtcClockSource == LL_RCC_RTC_CLKSOURCE_LSI) /* LSI clock used as RTC clock source */
00573     {
00574       const uint32_t temp_lsi1ready = LL_RCC_LSI1_IsReady();
00575       const uint32_t temp_lsi2ready = LL_RCC_LSI2_IsReady();
00576       if ((temp_lsi1ready == 1U) || (temp_lsi2ready == 1U))
00577       {
00578         frequency = LSI_VALUE;
00579       }
00580       else
00581       {
00582         frequency = 0U;
00583       }
00584     }
00585     else if (rtcClockSource == LL_RCC_RTC_CLKSOURCE_HSE_DIV32) /* HSE clock used as RTC clock source */
00586     {
00587       frequency = HSE_VALUE / 32U;
00588     }
00589     else /* No clock used as RTC clock source */
00590     {
00591       frequency = 0;
00592     }
00593   }
00594 #if defined(SAI1)
00595   else if (PeriphClk == RCC_PERIPHCLK_SAI1)
00596   {
00597     switch (LL_RCC_GetSAIClockSource(LL_RCC_SAI1_CLKSOURCE))
00598     {
00599       case LL_RCC_SAI1_CLKSOURCE_HSI:        /* HSI clock used as SAI1 clock source */
00600         if (LL_RCC_HSI_IsReady() == 1U)
00601         {
00602           frequency = HSI_VALUE;
00603         }
00604         else
00605         {
00606           frequency = 0U;
00607         }
00608         break;
00609
00610       case LL_RCC_SAI1_CLKSOURCE_PLLSAI1:    /* PLLSAI1 clock used as SAI1 clock source */
00611         if (LL_RCC_PLLSAI1_IsReady() == 1U)
00612         {
00613           frequency = RCC_PLLSAI1_GetFreqDomain_P();
00614         }
00615         else
00616         {
00617           frequency = 0U;
00618         }
00619         break;
00620
00621       case LL_RCC_SAI1_CLKSOURCE_PLL:        /* PLL clock used as SAI1 clock source */
00622         if (LL_RCC_PLL_IsReady() == 1U)
00623         {
00624           frequency = RCC_PLL_GetFreqDomain_P();
00625         }
00626         else
00627         {
00628           frequency = 0U;
00629         }
00630         break;
00631
00632       default: /* External input clock used as SAI1 clock source */
00633         frequency = EXTERNAL_SAI1_CLOCK_VALUE;
00634         break;
00635     }
00636   }
00637 #endif
00638   else if (PeriphClk == RCC_PERIPHCLK_RNG)
00639   {
00640     uint32_t rngClockSource = HAL_RCCEx_GetRngCLKSource();
00641
00642     if (rngClockSource == RCC_RNGCLKSOURCE_LSI)             /* LSI clock used as RNG clock source */
00643     {
00644       const uint32_t temp_lsi1ready = LL_RCC_LSI1_IsReady();
00645       const uint32_t temp_lsi2ready = LL_RCC_LSI2_IsReady();
00646       if ((temp_lsi1ready == 1U) || (temp_lsi2ready == 1U))
00647       {
00648         frequency = LSI_VALUE;
00649       }
00650       else
00651       {
00652         frequency = 0U;
00653       }
00654     }
00655     else if (rngClockSource == RCC_RNGCLKSOURCE_LSE)        /* LSE clock used as RNG clock source */
00656     {
00657       if (LL_RCC_LSE_IsReady() == 1U)
00658       {
00659         frequency = LSE_VALUE;
00660       }
00661       else
00662       {
00663         frequency = 0U;
00664       }
00665     }
00666     else if (rngClockSource == RCC_RNGCLKSOURCE_PLL)        /* PLL clock divided by 3 used as RNG clock source */
00667     {
00668       if (LL_RCC_PLL_IsReady() == 1U)
00669       {
00670         frequency = (RCC_PLL_GetFreqDomain_Q() / 3U);
00671       }
00672       else
00673       {
00674         frequency = 0U;
00675       }
00676     }
00677     else if (rngClockSource == RCC_RNGCLKSOURCE_MSI)        /* MSI clock divided by 3 used as RNG clock source */
00678     {
00679       if (LL_RCC_MSI_IsReady() == 1U)
00680       {
00681         frequency = (__LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange()) / 3U);
00682       }
00683       else
00684       {
00685         frequency = 0U;
00686       }
00687     }
00688     else                                                    /* HSI48 clock divided by 3 used as RNG clock source */
00689     {
00690       if (LL_RCC_HSI48_IsReady() == 1U)
00691       {
00692         frequency = HSI48_VALUE / 3U;
00693       }
00694       else
00695       {
00696         frequency = 0U;
00697       }
00698     }
00699   }
00700   else if (PeriphClk == RCC_PERIPHCLK_USB)
00701   {
00702     switch (LL_RCC_GetUSBClockSource(LL_RCC_USB_CLKSOURCE))
00703     {
00704 #if defined(SAI1)
00705       case LL_RCC_USB_CLKSOURCE_PLLSAI1:       /* PLLSAI1 clock used as USB clock source */
00706         if (LL_RCC_PLLSAI1_IsReady() == 1U)
00707         {
00708           frequency = RCC_PLLSAI1_GetFreqDomain_Q();
00709         }
00710         else
00711         {
00712           frequency = 0U;
00713         }
00714         break;
00715 #endif
00716       case LL_RCC_USB_CLKSOURCE_PLL:           /* PLL clock used as USB clock source */
00717         if (LL_RCC_PLL_IsReady() == 1U)
00718         {
00719           frequency = RCC_PLL_GetFreqDomain_Q();
00720         }
00721         else
00722         {
00723           frequency = 0U;
00724         }
00725         break;
00726
00727       case LL_RCC_USB_CLKSOURCE_MSI:           /* MSI clock used as USB clock source */
00728         if (LL_RCC_MSI_IsReady() == 1U)
00729         {
00730           frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
00731         }
00732         else
00733         {
00734           frequency = 0U;
00735         }
00736         break;
00737
00738       default: /* HSI48 clock used as USB clock source */
00739         if (LL_RCC_HSI48_IsReady() == 1U)
00740         {
00741           frequency = HSI48_VALUE;
00742         }
00743         else
00744         {
00745           frequency = 0U;
00746         }
00747         break;
00748     }
00749   }
00750
00751   else if (PeriphClk == RCC_PERIPHCLK_USART1)
00752   {
00753     switch (LL_RCC_GetUSARTClockSource(LL_RCC_USART1_CLKSOURCE))
00754     {
00755       case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
00756         frequency = HAL_RCC_GetSysClockFreq();
00757         break;
00758
00759       case LL_RCC_USART1_CLKSOURCE_HSI:    /* USART1 Clock is HSI Osc. */
00760         if (LL_RCC_HSI_IsReady() == 1U)
00761         {
00762           frequency = HSI_VALUE;
00763         }
00764         else
00765         {
00766           frequency = 0U;
00767         }
00768         break;
00769
00770       case LL_RCC_USART1_CLKSOURCE_LSE:    /* USART1 Clock is LSE Osc. */
00771         if (LL_RCC_LSE_IsReady() == 1U)
00772         {
00773           frequency = LSE_VALUE;
00774         }
00775         else
00776         {
00777           frequency = 0U;
00778         }
00779         break;
00780
00781       default: /* USART1 Clock is PCLK2 */
00782         frequency = __LL_RCC_CALC_PCLK2_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \
00783                                              LL_RCC_GetAHBPrescaler()), LL_RCC_GetAPB2Prescaler());
00784         break;
00785     }
00786   }
00787 #if defined(LPUART1)
00788   else if (PeriphClk == RCC_PERIPHCLK_LPUART1)
00789   {
00790     switch (LL_RCC_GetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE))
00791     {
00792       case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */
00793         frequency = HAL_RCC_GetSysClockFreq();
00794         break;
00795
00796       case LL_RCC_LPUART1_CLKSOURCE_HSI:    /* LPUART1 Clock is HSI Osc. */
00797         if (LL_RCC_HSI_IsReady() == 1U)
00798         {
00799           frequency = HSI_VALUE;
00800         }
00801         else
00802         {
00803           frequency = 0U;
00804         }
00805         break;
00806
00807       case LL_RCC_LPUART1_CLKSOURCE_LSE:    /* LPUART1 Clock is LSE Osc. */
00808         if (LL_RCC_LSE_IsReady() == 1U)
00809         {
00810           frequency = LSE_VALUE;
00811         }
00812         else
00813         {
00814           frequency = 0U;
00815         }
00816         break;
00817
00818       default: /* LPUART1 Clock is PCLK1 */
00819         frequency = __LL_RCC_CALC_PCLK1_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \
00820                                              LL_RCC_GetAHBPrescaler()), LL_RCC_GetAPB1Prescaler());
00821         break;
00822     }
00823   }
00824 #endif
00825   else if (PeriphClk == RCC_PERIPHCLK_ADC)
00826   {
00827     switch (LL_RCC_GetADCClockSource(LL_RCC_ADC_CLKSOURCE))
00828     {
00829 #if defined(SAI1)
00830       case LL_RCC_ADC_CLKSOURCE_PLLSAI1:       /* PLLSAI1 clock used as ADC clock source */
00831         if (LL_RCC_PLLSAI1_IsReady() == 1U)
00832         {
00833           frequency = RCC_PLLSAI1_GetFreqDomain_R();
00834         }
00835         else
00836         {
00837           frequency = 0U;
00838         }
00839         break;
00840 #endif
00841       case LL_RCC_ADC_CLKSOURCE_SYSCLK:        /* SYSCLK clock used as ADC clock source */
00842         frequency = HAL_RCC_GetSysClockFreq();
00843         break;
00844
00845       case LL_RCC_ADC_CLKSOURCE_PLL:           /* PLL clock used as USB clock source */
00846         if (LL_RCC_PLL_IsReady() == 1U)
00847         {
00848           frequency = RCC_PLL_GetFreqDomain_P();
00849         }
00850         else
00851         {
00852           frequency = 0U;
00853         }
00854         break;
00855
00856       default: /* No clock used as ADC clock source */
00857         frequency = 0;
00858         break;
00859     }
00860   }
00861   else if (PeriphClk == RCC_PERIPHCLK_I2C1)
00862   {
00863     switch (LL_RCC_GetI2CClockSource(LL_RCC_I2C1_CLKSOURCE))
00864     {
00865       case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
00866         frequency = HAL_RCC_GetSysClockFreq();
00867         break;
00868
00869       case LL_RCC_I2C1_CLKSOURCE_HSI:    /* I2C1 Clock is HSI Osc. */
00870         if (LL_RCC_HSI_IsReady() == 1U)
00871         {
00872           frequency = HSI_VALUE;
00873         }
00874         else
00875         {
00876           frequency = 0U;
00877         }
00878         break;
00879
00880       default: /* I2C1 Clock is PCLK1 */
00881         frequency = __LL_RCC_CALC_PCLK1_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \
00882                                              LL_RCC_GetAHBPrescaler()), LL_RCC_GetAPB1Prescaler());
00883         break;
00884     }
00885   }
00886 #if defined(I2C3)
00887   else if (PeriphClk == RCC_PERIPHCLK_I2C3)
00888   {
00889     switch (LL_RCC_GetI2CClockSource(LL_RCC_I2C3_CLKSOURCE))
00890     {
00891       case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */
00892         frequency = HAL_RCC_GetSysClockFreq();
00893         break;
00894
00895       case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */
00896         if (LL_RCC_HSI_IsReady() == 1U)
00897         {
00898           frequency = HSI_VALUE;
00899         }
00900         else
00901         {
00902           frequency = 0U;
00903         }
00904         break;
00905
00906       default: /* I2C3 Clock is PCLK1 */
00907         frequency = __LL_RCC_CALC_PCLK1_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \
00908                                              LL_RCC_GetAHBPrescaler()), LL_RCC_GetAPB1Prescaler());
00909         break;
00910     }
00911   }
00912 #endif
00913   else if (PeriphClk == RCC_PERIPHCLK_LPTIM1)
00914   {
00915     uint32_t lptimClockSource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE);
00916
00917     if (lptimClockSource == LL_RCC_LPTIM1_CLKSOURCE_LSI) /* LPTIM1 Clock is LSI Osc. */
00918     {
00919       const uint32_t temp_lsi1ready = LL_RCC_LSI1_IsReady();
00920       const uint32_t temp_lsi2ready = LL_RCC_LSI2_IsReady();
00921       if ((temp_lsi1ready == 1U) || (temp_lsi2ready == 1U))
00922       {
00923         frequency = LSI_VALUE;
00924       }
00925       else
00926       {
00927         frequency = 0U;
00928       }
00929     }
00930     else if (lptimClockSource == LL_RCC_LPTIM1_CLKSOURCE_HSI) /* LPTIM1 Clock is HSI Osc. */
00931     {
00932       if (LL_RCC_HSI_IsReady() == 1U)
00933       {
00934         frequency = HSI_VALUE;
00935       }
00936       else
00937       {
00938         frequency = 0U;
00939       }
00940     }
00941     else if (lptimClockSource == LL_RCC_LPTIM1_CLKSOURCE_LSE) /* LPTIM1 Clock is LSE Osc. */
00942     {
00943       if (LL_RCC_LSE_IsReady() == 1U)
00944       {
00945         frequency = LSE_VALUE;
00946       }
00947       else
00948       {
00949         frequency = 0U;
00950       }
00951     }
00952     else /* LPTIM1 Clock is PCLK1 */
00953     {
00954       frequency = __LL_RCC_CALC_PCLK1_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetAHBPrescaler()), LL_RCC_GetAPB1Prescaler());
00955     }
00956   }
00957   else if (PeriphClk == RCC_PERIPHCLK_LPTIM2)
00958   {
00959     uint32_t lptimClockSource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE);
00960
00961     if (lptimClockSource == LL_RCC_LPTIM2_CLKSOURCE_LSI) /* LPTIM2 Clock is LSI Osc. */
00962     {
00963       const uint32_t temp_lsi1ready = LL_RCC_LSI1_IsReady();
00964       const uint32_t temp_lsi2ready = LL_RCC_LSI2_IsReady();
00965       if ((temp_lsi1ready == 1U) || (temp_lsi2ready == 1U))
00966       {
00967         frequency = LSI_VALUE;
00968       }
00969       else
00970       {
00971         frequency = 0U;
00972       }
00973     }
00974     else if (lptimClockSource == LL_RCC_LPTIM2_CLKSOURCE_HSI) /* LPTIM2 Clock is HSI Osc. */
00975     {
00976       if (LL_RCC_HSI_IsReady() == 1U)
00977       {
00978         frequency = HSI_VALUE;
00979       }
00980       else
00981       {
00982         frequency = 0U;
00983       }
00984     }
00985     else if (lptimClockSource == LL_RCC_LPTIM2_CLKSOURCE_LSE) /* LPTIM2 Clock is LSE Osc. */
00986     {
00987       if (LL_RCC_LSE_IsReady() == 1U)
00988       {
00989         frequency = LSE_VALUE;
00990       }
00991       else
00992       {
00993         frequency = 0U;
00994       }
00995     }
00996     else /* LPTIM2 Clock is PCLK1 */
00997     {
00998       frequency = __LL_RCC_CALC_PCLK1_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetAHBPrescaler()), LL_RCC_GetAPB1Prescaler());
00999     }
01000   }
01001   else if (PeriphClk == RCC_PERIPHCLK_RFWAKEUP)
01002   {
01003     uint32_t rfwkpClockSource = LL_RCC_GetRFWKPClockSource();
01004
01005     if (rfwkpClockSource == LL_RCC_RFWKP_CLKSOURCE_LSE) /* LSE clock used as RF Wakeup clock source */
01006     {
01007       if (LL_RCC_LSE_IsReady() == 1U)
01008       {
01009         frequency = LSE_VALUE;
01010       }
01011       else
01012       {
01013         frequency = 0U;
01014       }
01015     }
01016     else if (rfwkpClockSource == LL_RCC_RFWKP_CLKSOURCE_LSI) /* LSI clock used as RF Wakeup clock source */
01017     {
01018       const uint32_t temp_lsi1ready = LL_RCC_LSI1_IsReady();
01019       const uint32_t temp_lsi2ready = LL_RCC_LSI2_IsReady();
01020       if ((temp_lsi1ready == 1U) || (temp_lsi2ready == 1U))
01021       {
01022         frequency = LSI_VALUE;
01023       }
01024       else
01025       {
01026         frequency = 0U;
01027       }
01028     }
01029     else if (rfwkpClockSource == LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024) /* HSE clock used as RF Wakeup clock source */
01030     {
01031       frequency = HSE_VALUE / 1024U;
01032     }
01033     else /* No clock used as RF Wakeup clock source */
01034     {
01035       frequency = 0;
01036     }
01037   }
01038 #if defined(RCC_SMPS_SUPPORT)
01039   else if (PeriphClk == RCC_PERIPHCLK_SMPS)
01040   {
01041     uint32_t smpsClockSource = LL_RCC_GetSMPSClockSource();
01042
01043     if (smpsClockSource == LL_RCC_SMPS_CLKSOURCE_STATUS_HSI) /* SMPS Clock source is HSI Osc. */
01044     {
01045       if (LL_RCC_HSI_IsReady() == 1U)
01046       {
01047         frequency = HSI_VALUE / SmpsPrescalerTable[smps_prescaler_index][0];
01048         frequency = frequency >> 1U; /* Systematic Div by 2 */
01049       }
01050       else
01051       {
01052         frequency = 0U;
01053       }
01054     }
01055     else if (smpsClockSource == LL_RCC_SMPS_CLKSOURCE_STATUS_HSE) /* SMPS Clock source is HSE Osc. */
01056     {
01057       if (LL_RCC_HSE_IsReady() == 1U)
01058       {
01059         frequency = HSE_VALUE / SmpsPrescalerTable[smps_prescaler_index][5];
01060         frequency = frequency >> 1U; /* Systematic Div by 2 */
01061       }
01062       else
01063       {
01064         frequency = 0U;
01065       }
01066     }
01067     else if (smpsClockSource == LL_RCC_SMPS_CLKSOURCE_STATUS_MSI) /* SMPS Clock source is MSI Osc. */
01068     {
01069       switch (LL_RCC_MSI_GetRange())
01070       {
01071         case LL_RCC_MSIRANGE_8:
01072           frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGE_8) / SmpsPrescalerTable[smps_prescaler_index][4];
01073           break;
01074         case LL_RCC_MSIRANGE_9:
01075           frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGE_9) / SmpsPrescalerTable[smps_prescaler_index][3];
01076           break;
01077         case LL_RCC_MSIRANGE_10:
01078           frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGE_10) / SmpsPrescalerTable[smps_prescaler_index][2];
01079           break;
01080         case LL_RCC_MSIRANGE_11:
01081           frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGE_11) / SmpsPrescalerTable[smps_prescaler_index][1];
01082           break;
01083         default:
01084           frequency = 0U;
01085           break;
01086       }
01087       frequency = frequency >> 1U; /* Systematic Div by 2 */
01088     }
01089     else /* SMPS has no Clock */
01090     {
01091       frequency = 0U;
01092     }
01093   }
01094 #endif
01095   else
01096   {
01097     frequency = 0U;
01098   }
01099   return (frequency);
01100 }
01101
01102 /**
01103   * @brief  Return the RNG clock source
01104   * @retval The RNG clock source can be one of the following values:
01105   *            @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 clock divided by 3 selected as RNG clock
01106   *            @arg @ref RCC_RNGCLKSOURCE_PLL   PLL "Q" clock divided by 3  selected as RNG clock
01107   *            @arg @ref RCC_RNGCLKSOURCE_MSI   MSI clock divided by 3 selected as RNG clock
01108   *            @arg @ref RCC_RNGCLKSOURCE_LSI   LSI clock selected as RNG clock
01109   *            @arg @ref RCC_RNGCLKSOURCE_LSE   LSE clock selected as RNG clock
01110   */
01111 uint32_t HAL_RCCEx_GetRngCLKSource(void)
01112 {
01113   uint32_t rng_clock_source = LL_RCC_GetRNGClockSource(LL_RCC_RNG_CLKSOURCE);
01114   uint32_t clk48_clock_source;
01115
01116   /* RNG clock source originates from 48 MHz RC oscillator */
01117   if (rng_clock_source == RCC_RNGCLKSOURCE_CLK48)
01118   {
01119     clk48_clock_source = LL_RCC_GetCLK48ClockSource(LL_RCC_CLK48_CLKSOURCE);
01120     rng_clock_source = (CLK48_MASK | clk48_clock_source);
01121   }
01122
01123   return rng_clock_source;
01124 }
01125
01126 /**
01127   * @}
01128   */
01129
01130 /** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions
01131  *  @brief  Extended Clock management functions
01132  *
01133 @verbatim
01134  ===============================================================================
01135                 ##### Extended clock management functions  #####
01136  ===============================================================================
01137     [..]
01138     This subsection provides a set of functions allowing to control the
01139     activation or deactivation of MSI PLL-mode, PLLSAI1, PLLSAI12, LSE CSS,
01140     Low speed clock output and clock after wake-up from STOP mode.
01141 @endverbatim
01142   * @{
01143   */
01144
01145 #if defined(SAI1)
01146 /**
01147   * @brief  Enable PLLSAI1.
01148   * @param  PLLSAI1Init  pointer to an RCC_PLLSAI1InitTypeDef structure that
01149   *         contains the configuration information for the PLLSAI1
01150   * @retval HAL status
01151   */
01152 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef  *PLLSAI1Init)
01153 {
01154   uint32_t tickstart;
01155   HAL_StatusTypeDef status = HAL_OK;
01156
01157   /* check for PLLSAI1 Parameters used to output PLLSAI1CLK */
01158   assert_param(IS_RCC_PLLN_VALUE(PLLSAI1Init->PLLN));
01159   assert_param(IS_RCC_PLLP_VALUE(PLLSAI1Init->PLLP));
01160   assert_param(IS_RCC_PLLQ_VALUE(PLLSAI1Init->PLLQ));
01161   assert_param(IS_RCC_PLLR_VALUE(PLLSAI1Init->PLLR));
01162   assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PLLSAI1Init->PLLSAI1ClockOut));
01163
01164   /* Disable the PLLSAI1 */
01165   __HAL_RCC_PLLSAI1_DISABLE();
01166
01167   /* Get Start Tick*/
01168   tickstart = HAL_GetTick();
01169
01170   /* Wait till PLLSAI1 is ready to be updated */
01171   while (LL_RCC_PLLSAI1_IsReady() != 0U)
01172   {
01173     if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
01174     {
01175       status = HAL_TIMEOUT;
01176       break;
01177     }
01178   }
01179
01180   if (status == HAL_OK)
01181   {
01182     /* Configure the PLLSAI1 Multiplication factor N */
01183     /* Configure the PLLSAI1 Division factors P, Q and R */
01184     __HAL_RCC_PLLSAI1_CONFIG(PLLSAI1Init->PLLN, PLLSAI1Init->PLLP, PLLSAI1Init->PLLQ, PLLSAI1Init->PLLR);
01185     /* Configure the PLLSAI1 Clock output(s) */
01186     __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PLLSAI1Init->PLLSAI1ClockOut);
01187
01188     /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
01189     __HAL_RCC_PLLSAI1_ENABLE();
01190
01191     /* Get Start Tick*/
01192     tickstart = HAL_GetTick();
01193
01194     /* Wait till PLLSAI1 is ready */
01195     while (LL_RCC_PLLSAI1_IsReady() != 1U)
01196     {
01197       if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
01198       {
01199         status = HAL_TIMEOUT;
01200         break;
01201       }
01202     }
01203   }
01204
01205   return status;
01206 }
01207
01208 /**
01209   * @brief  Disable PLLSAI1.
01210   * @retval HAL status
01211   */
01212 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void)
01213 {
01214   uint32_t tickstart;
01215   HAL_StatusTypeDef status = HAL_OK;
01216
01217   /* Disable the PLLSAI1 */
01218   __HAL_RCC_PLLSAI1_DISABLE();
01219
01220   /* Get Start Tick*/
01221   tickstart = HAL_GetTick();
01222
01223   /* Wait till PLLSAI1 is ready */
01224   while (LL_RCC_PLLSAI1_IsReady() != 0U)
01225   {
01226     if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
01227     {
01228       status = HAL_TIMEOUT;
01229       break;
01230     }
01231   }
01232
01233   /* Disable the PLLSAI1 Clock outputs */
01234   __HAL_RCC_PLLSAI1CLKOUT_DISABLE(RCC_PLLSAI1_SAI1CLK | RCC_PLLSAI1_USBCLK | RCC_PLLSAI1_ADCCLK);
01235
01236   return status;
01237 }
01238 #endif
01239
01240 /***********************************************************************************************/
01241
01242 /**
01243   * @brief  Configure the oscillator clock source for wakeup from Stop and CSS backup clock.
01244   * @param  WakeUpClk  Wakeup clock
01245   *         This parameter can be one of the following values:
01246   *            @arg @ref RCC_STOP_WAKEUPCLOCK_MSI  MSI oscillator selection
01247   *            @arg @ref RCC_STOP_WAKEUPCLOCK_HSI  HSI oscillator selection
01248   * @note   This function shall not be called after the Clock Security System on HSE has been
01249   *         enabled.
01250   * @retval None
01251   */
01252 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)
01253 {
01254   assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk));
01255
01256   __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk);
01257 }
01258
01259 /**
01260   * @brief  Enable the LSE Clock Security System.
01261   * @note   Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled
01262   *         with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC
01263   *         clock with HAL_RCCEx_PeriphCLKConfig().
01264   * @retval None
01265   */
01266 void HAL_RCCEx_EnableLSECSS(void)
01267 {
01268   LL_RCC_LSE_EnableCSS();
01269 }
01270
01271 /**
01272   * @brief  Disable the LSE Clock Security System.
01273   * @note   LSE Clock Security System can only be disabled after a LSE failure detection.
01274   * @retval None
01275   */
01276 void HAL_RCCEx_DisableLSECSS(void)
01277 {
01278   LL_RCC_LSE_DisableCSS();
01279
01280   /* Disable LSE CSS IT if any */
01281   __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);
01282 }
01283
01284 /**
01285   * @brief  Enable the LSE Clock Security System Interrupt & corresponding EXTI line.
01286   * @note   LSE Clock Security System Interrupt is mapped on RTC EXTI line 18
01287   * @retval None
01288   */
01289 void HAL_RCCEx_EnableLSECSS_IT(void)
01290 {
01291   /* Enable LSE CSS */
01292   LL_RCC_LSE_EnableCSS();
01293
01294   /* Enable LSE CSS IT */
01295   __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS);
01296
01297   /* Enable IT on EXTI Line 18 */
01298   __HAL_RCC_LSECSS_EXTI_ENABLE_IT();
01299   __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();
01300
01301
01302 }
01303
01304 /**
01305   * @brief Handle the RCC LSE Clock Security System interrupt request.
01306   * @retval None
01307   */
01308 void HAL_RCCEx_LSECSS_IRQHandler(void)
01309 {
01310   /* Check RCC LSE CSSF flag  */
01311   if (__HAL_RCC_GET_IT(RCC_IT_LSECSS))
01312   {
01313     /* RCC LSE Clock Security System interrupt user callback */
01314     HAL_RCCEx_LSECSS_Callback();
01315
01316     /* Clear RCC LSE CSS pending bit */
01317     __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS);
01318   }
01319 }
01320
01321 /**
01322   * @brief  RCCEx LSE Clock Security System interrupt callback.
01323   * @retval none
01324   */
01325 __weak void HAL_RCCEx_LSECSS_Callback(void)
01326 {
01327   /* NOTE : This function should not be modified, when the callback is needed,
01328             the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
01329    */
01330 }
01331
01332 /**
01333   * @brief  Select the clock source to output on LSCO1 pin(PA2) or LSC02 pin (PH3) or LSCO3 pin (PC12).
01334   * @note   PA2, PH3 or PC12 should be configured in alternate function mode.
01335   * @param  RCC_LSCOx  specifies the output direction for the clock source.
01336   *            @arg @ref RCC_LSCO1  Clock source to output on LSCO1 pin(PA2)
01337   *            @arg @ref RCC_LSCO2  Clock source to output on LSCO2 pin(PH13)
01338   *            @arg @ref RCC_LSCO3  Clock source to output on LSCO3 pin(PC12)
01339   * @param  RCC_LSCOSource  specifies the clock source to output.
01340   *          This parameter can be one of the following values:
01341   *            @arg @ref RCC_LSCOSOURCE_LSI  LSI clock selected as LSCO source
01342   *            @arg @ref RCC_LSCOSOURCE_LSE  LSE clock selected as LSCO source
01343   * @retval None
01344   * @note   LSCO should be disable with @ref HAL_RCCEx_DisableLSCO
01345   */
01346 void HAL_RCCEx_LSCOConfig(uint32_t RCC_LSCOx, uint32_t RCC_LSCOSource)
01347 {
01348   GPIO_InitTypeDef GPIO_InitStruct;
01349   FlagStatus backupchanged;
01350
01351   /* Check the parameters */
01352   assert_param(IS_RCC_LSCO(RCC_LSCOx));
01353   assert_param(IS_RCC_LSCOSOURCE(RCC_LSCOSource));
01354
01355   /* Common GPIO init parameters */
01356   GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
01357   GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_VERY_HIGH;
01358   GPIO_InitStruct.Pull      = GPIO_NOPULL;
01359
01360   /* RCC_LSCO1 */
01361   if (RCC_LSCOx == RCC_LSCO1)
01362   {
01363     /* LSCO1 Clock Enable */
01364     __LSCO1_CLK_ENABLE();
01365     /* Configue the LSCO1 pin in alternate function mode */
01366     GPIO_InitStruct.Pin       = LSCO1_PIN;
01367     GPIO_InitStruct.Alternate = GPIO_AF0_LSCO;
01368     HAL_GPIO_Init(LSCO1_GPIO_PORT, &GPIO_InitStruct);
01369
01370   }
01371   else if (RCC_LSCOx == RCC_LSCO2)
01372   {
01373     /* LSCO2 Clock Enable */
01374     __LSCO2_CLK_ENABLE();
01375     /* Configue the LSCO2 pin in alternate function mode */
01376     GPIO_InitStruct.Pin       = LSCO2_PIN;
01377     GPIO_InitStruct.Alternate = GPIO_AF0_LSCO;
01378     HAL_GPIO_Init(LSCO2_GPIO_PORT, &GPIO_InitStruct);
01379
01380   }
01381   else
01382   {
01383     /* LSCO3 Clock Enable */
01384     __LSCO3_CLK_ENABLE();
01385     /* Configue the LSCO3 pin in alternate function mode */
01386     GPIO_InitStruct.Pin       = LSCO3_PIN;
01387     GPIO_InitStruct.Alternate = GPIO_AF6_LSCO;
01388     HAL_GPIO_Init(LSCO3_GPIO_PORT, &GPIO_InitStruct);
01389   }
01390
01391   /* Update LSCOSEL clock source in Backup Domain control register */
01392   if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
01393   {
01394     HAL_PWR_EnableBkUpAccess();
01395     backupchanged = SET;
01396   }
01397   else
01398   {
01399     backupchanged = RESET;
01400   }
01401
01402   MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, RCC_LSCOSource | RCC_BDCR_LSCOEN);
01403
01404   if (backupchanged == SET)
01405   {
01406     HAL_PWR_DisableBkUpAccess();
01407   }
01408
01409 }
01410
01411
01412
01413 /**
01414   * @brief  Select the Low Speed clock source to output on LSCO pin (PA2).
01415   * @param  LSCOSource  specifies the Low Speed clock source to output.
01416   *          This parameter can be one of the following values:
01417   *            @arg @ref RCC_LSCOSOURCE_LSI  LSI clock selected as LSCO source
01418   *            @arg @ref RCC_LSCOSOURCE_LSE  LSE clock selected as LSCO source
01419   * @retval None
01420   */
01421 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)
01422 {
01423   GPIO_InitTypeDef GPIO_InitStruct;
01424   FlagStatus backupchanged;
01425
01426   /* Check the parameters */
01427   assert_param(IS_RCC_LSCOSOURCE(LSCOSource));
01428
01429   /* LSCO Pin Clock Enable */
01430   __LSCO1_CLK_ENABLE();
01431
01432   /* Configure the LSCO pin in analog mode */
01433   GPIO_InitStruct.Pin   = LSCO1_PIN;
01434   GPIO_InitStruct.Mode  = GPIO_MODE_AF_PP;
01435   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
01436   GPIO_InitStruct.Pull  = GPIO_NOPULL;
01437   GPIO_InitStruct.Alternate = GPIO_AF0_LSCO;
01438   HAL_GPIO_Init(LSCO1_GPIO_PORT, &GPIO_InitStruct);
01439
01440   /* Update LSCOSEL clock source in Backup Domain control register */
01441   if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
01442   {
01443     HAL_PWR_EnableBkUpAccess();
01444     backupchanged = SET;
01445   }
01446   else
01447   {
01448     backupchanged = RESET;
01449   }
01450
01451   MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN);
01452
01453   if (backupchanged == SET)
01454   {
01455     HAL_PWR_DisableBkUpAccess();
01456   }
01457 }
01458
01459 /**
01460   * @brief  Disable the Low Speed clock output.
01461   * @retval None
01462   */
01463 void HAL_RCCEx_DisableLSCO(void)
01464 {
01465   FlagStatus backupchanged;
01466
01467   if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
01468   {
01469     /* Enable access to the backup domain */
01470     HAL_PWR_EnableBkUpAccess();
01471     backupchanged = SET;
01472   }
01473   else
01474   {
01475     backupchanged = RESET;
01476   }
01477
01478   LL_RCC_LSCO_Disable();
01479
01480   /* Restore previous configuration */
01481   if (backupchanged == SET)
01482   {
01483     /* Disable access to the backup domain */
01484     HAL_PWR_DisableBkUpAccess();
01485   }
01486 }
01487
01488 /**
01489   * @brief  Enable the PLL-mode of the MSI.
01490   * @note   Prior to enable the PLL-mode of the MSI for automatic hardware
01491   *         calibration LSE oscillator is to be enabled with @ref HAL_RCC_OscConfig().
01492   * @retval None
01493   */
01494 void HAL_RCCEx_EnableMSIPLLMode(void)
01495 {
01496   LL_RCC_MSI_EnablePLLMode() ;
01497 }
01498
01499 /**
01500   * @brief  Disable the PLL-mode of the MSI.
01501   * @note   PLL-mode of the MSI is automatically reset when LSE oscillator is disabled.
01502   * @retval None
01503   */
01504 void HAL_RCCEx_DisableMSIPLLMode(void)
01505 {
01506   LL_RCC_MSI_DisablePLLMode() ;
01507 }
01508
01509 /**
01510   * @brief Set trimming value
01511   * @param OscillatorType Specifies the oscillator to be trimmed
01512   *   This parameter can be one of the following values:
01513   *     @arg @ref RCC_OSCILLATORTYPE_LSI2 LSI2 oscillator selected.
01514   *       When disabling and re-enabling the LSI2 there is no need for re-trimming
01515   *       Trimming is only needed once after a NRST reset.
01516   *       Trimming values comes from factory trimmed flash location (0x1FFF7548).
01517   * @note The LSI2 oscillator must be disabled before calling this trimming function through @ref HAL_RCC_OscConfig
01518   * @retval HAL status
01519   */
01520 HAL_StatusTypeDef HAL_RCCEx_TrimOsc(uint32_t OscillatorType)
01521 {
01522 #define FTLSI2TRIM (0xFUL)
01523   HAL_StatusTypeDef status = HAL_OK;
01524
01525   assert_param(IS_RCC_TRIMOSC(OscillatorType));
01526
01527   if (OscillatorType == RCC_OSCILLATORTYPE_LSI2)
01528   {
01529     if (LL_RCC_LSI2_IsReady() == 1U)
01530     {
01531       status = HAL_ERROR;
01532     }
01533     else
01534     {
01535       /* Copy the LSI2 trimming information from the factory trimmed Flash location */
01536       uint32_t factoryTrimming = ((*(uint32_t *)(0x1FFF7548)) & FTLSI2TRIM);
01537       LL_RCC_LSI2_SetTrimming(factoryTrimming);
01538     }
01539   }
01540   else
01541   {
01542     status = HAL_ERROR;
01543   }
01544   return status;
01545 }
01546
01547
01548 /**
01549   * @}
01550   */
01551
01552 #if defined(CRS)
01553 /** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions
01554  *  @brief  Extended Clock Recovery System Control functions
01555  *
01556 @verbatim
01557  ===============================================================================
01558                 ##### Extended Clock Recovery System Control functions  #####
01559  ===============================================================================
01560     [..]
01561       For devices with Clock Recovery System feature (CRS), RCC Extention HAL driver can be used as follows:
01562
01563       (#) In System clock config, HSI48 needs to be enabled
01564
01565       (#) Enable CRS clock in IP MSP init which will use CRS functions
01566
01567       (#) Call CRS functions as follows:
01568           (##) Prepare synchronization configuration necessary for HSI48 calibration
01569               (+++) Default values can be set for frequency Error Measurement (reload and error limit)
01570                         and also HSI48 oscillator smooth trimming.
01571               (+++) Macro @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
01572                         directly reload value with target and sychronization frequencies values
01573           (##) Call function @ref HAL_RCCEx_CRSConfig which
01574               (+++) Resets CRS registers to their default values.
01575               (+++) Configures CRS registers with synchronization configuration
01576               (+++) Enables automatic calibration and frequency error counter feature
01577            Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
01578            periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
01579            provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
01580            precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
01581            should be used as SYNC signal.
01582
01583           (##) A polling function is provided to wait for complete synchronization
01584               (+++) Call function @ref HAL_RCCEx_CRSWaitSynchronization()
01585               (+++) According to CRS status, user can decide to adjust again the calibration or continue
01586                         application if synchronization is OK
01587
01588       (#) User can retrieve information related to synchronization in calling function
01589             @ref HAL_RCCEx_CRSGetSynchronizationInfo()
01590
01591       (#) Regarding synchronization status and synchronization information, user can try a new calibration
01592            in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
01593            Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value),
01594            it means that the actual frequency is lower than the target (and so, that the TRIM value should be
01595            incremented), while when it is detected during the upcounting phase it means that the actual frequency
01596            is higher (and that the TRIM value should be decremented).
01597
01598       (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go
01599           through CRS Handler (CRS_IRQn/CRS_IRQHandler)
01600               (++) Call function @ref HAL_RCCEx_CRSConfig()
01601               (++) Enable CRS_IRQn (thanks to NVIC functions)
01602               (++) Enable CRS interrupt (@ref __HAL_RCC_CRS_ENABLE_IT)
01603               (++) Implement CRS status management in the following user callbacks called from
01604                    HAL_RCCEx_CRS_IRQHandler():
01605                    (+++) @ref HAL_RCCEx_CRS_SyncOkCallback()
01606                    (+++) @ref HAL_RCCEx_CRS_SyncWarnCallback()
01607                    (+++) @ref HAL_RCCEx_CRS_ExpectedSyncCallback()
01608                    (+++) @ref HAL_RCCEx_CRS_ErrorCallback()
01609
01610       (#) To force a SYNC EVENT, user can use the function @ref HAL_RCCEx_CRSSoftwareSynchronizationGenerate().
01611           This function can be called before calling @ref HAL_RCCEx_CRSConfig (for instance in Systick handler)
01612
01613 @endverbatim
01614  * @{
01615  */
01616
01617 /**
01618   * @brief  Start automatic synchronization for polling mode
01619   * @param  pInit Pointer on RCC_CRSInitTypeDef structure
01620   * @retval None
01621   */
01622 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
01623 {
01624   uint32_t value;
01625
01626   /* Check the parameters */
01627   assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
01628   assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
01629   assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
01630   assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
01631   assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
01632   assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
01633
01634   /* CONFIGURATION */
01635
01636   /* Before configuration, reset CRS registers to their default values*/
01637   __HAL_RCC_CRS_FORCE_RESET();
01638   __HAL_RCC_CRS_RELEASE_RESET();
01639
01640   /* Set the SYNCDIV[2:0] bits according to Prescaler value */
01641   /* Set the SYNCSRC[1:0] bits according to Source value */
01642   /* Set the SYNCSPOL bit according to Polarity value */
01643   value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
01644   /* Set the RELOAD[15:0] bits according to ReloadValue value */
01645   value |= pInit->ReloadValue;
01646   /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
01647   value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos);
01648   WRITE_REG(CRS->CFGR, value);
01649
01650   /* Adjust HSI48 oscillator smooth trimming */
01651   /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */
01652   MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos));
01653
01654   /* START AUTOMATIC SYNCHRONIZATION*/
01655
01656   /* Enable Automatic trimming & Frequency error counter */
01657   SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
01658 }
01659
01660 /**
01661   * @brief  Generate the software synchronization event
01662   * @retval None
01663   */
01664 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
01665 {
01666   LL_CRS_GenerateEvent_SWSYNC();
01667 }
01668
01669 /**
01670   * @brief  Return synchronization info
01671   * @param  pSynchroInfo Pointer on @ref RCC_CRSSynchroInfoTypeDef structure
01672   * @retval None
01673   */
01674 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
01675 {
01676   /* Check the parameter */
01677   assert_param(pSynchroInfo != (void *)NULL);
01678
01679   /* Get the reload value */
01680   pSynchroInfo->ReloadValue = LL_CRS_GetReloadCounter();
01681
01682   /* Get HSI48 oscillator smooth trimming */
01683   pSynchroInfo->HSI48CalibrationValue = LL_CRS_GetHSI48SmoothTrimming();
01684
01685   /* Get Frequency error capture */
01686   pSynchroInfo->FreqErrorCapture = LL_CRS_GetFreqErrorCapture();
01687
01688   /* Get Frequency error direction */
01689   pSynchroInfo->FreqErrorDirection = LL_CRS_GetFreqErrorDirection();
01690 }
01691
01692 /**
01693 * @brief  Wait for CRS Synchronization status.
01694 * @param  Timeout  Duration of the timeout
01695 * @note   Timeout is based on the maximum time to receive a SYNC event based on synchronization
01696 *         frequency.
01697 * @note   If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
01698 * @retval Combination of Synchronization status
01699 *          This parameter can be a combination of the following values:
01700 *            @arg @ref RCC_CRS_TIMEOUT
01701 *            @arg @ref RCC_CRS_SYNCOK
01702 *            @arg @ref RCC_CRS_SYNCWARN
01703 *            @arg @ref RCC_CRS_SYNCERR
01704 *            @arg @ref RCC_CRS_SYNCMISS
01705 *            @arg @ref RCC_CRS_TRIMOVF
01706 */
01707 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
01708 {
01709   uint32_t crsstatus = RCC_CRS_NONE;
01710   uint32_t tickstart;
01711
01712   /* Get timeout */
01713   tickstart = HAL_GetTick();
01714
01715   /* Wait for CRS flag or timeout detection */
01716   do
01717   {
01718     if (Timeout != HAL_MAX_DELAY)
01719     {
01720       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
01721       {
01722         crsstatus = RCC_CRS_TIMEOUT;
01723       }
01724     }
01725     /* Check CRS SYNCOK flag  */
01726     if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
01727     {
01728       /* CRS SYNC event OK */
01729       crsstatus |= RCC_CRS_SYNCOK;
01730
01731       /* Clear CRS SYNC event OK bit */
01732       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
01733     }
01734
01735     /* Check CRS SYNCWARN flag  */
01736     if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
01737     {
01738       /* CRS SYNC warning */
01739       crsstatus |= RCC_CRS_SYNCWARN;
01740
01741       /* Clear CRS SYNCWARN bit */
01742       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
01743     }
01744
01745     /* Check CRS TRIM overflow flag  */
01746     if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
01747     {
01748       /* CRS SYNC Error */
01749       crsstatus |= RCC_CRS_TRIMOVF;
01750
01751       /* Clear CRS Error bit */
01752       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
01753     }
01754
01755     /* Check CRS Error flag  */
01756     if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
01757     {
01758       /* CRS SYNC Error */
01759       crsstatus |= RCC_CRS_SYNCERR;
01760
01761       /* Clear CRS Error bit */
01762       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
01763     }
01764
01765     /* Check CRS SYNC Missed flag  */
01766     if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
01767     {
01768       /* CRS SYNC Missed */
01769       crsstatus |= RCC_CRS_SYNCMISS;
01770
01771       /* Clear CRS SYNC Missed bit */
01772       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
01773     }
01774
01775     /* Check CRS Expected SYNC flag  */
01776     if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
01777     {
01778       /* frequency error counter reached a zero value */
01779       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
01780     }
01781   }
01782   while (RCC_CRS_NONE == crsstatus);
01783
01784   return crsstatus;
01785 }
01786
01787 /**
01788   * @brief Handle the Clock Recovery System interrupt request.
01789   * @retval None
01790   */
01791 void HAL_RCCEx_CRS_IRQHandler(void)
01792 {
01793   uint32_t crserror = RCC_CRS_NONE;
01794   /* Get current IT flags and IT sources values */
01795   uint32_t itflags = READ_REG(CRS->ISR);
01796   uint32_t itsources = READ_REG(CRS->CR);
01797
01798   /* Check CRS SYNCOK flag  */
01799   if (((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U))
01800   {
01801     /* Clear CRS SYNC event OK flag */
01802     LL_CRS_ClearFlag_SYNCOK();
01803
01804     /* user callback */
01805     HAL_RCCEx_CRS_SyncOkCallback();
01806   }
01807   /* Check CRS SYNCWARN flag  */
01808   else if (((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U))
01809   {
01810     /* Clear CRS SYNCWARN flag */
01811     LL_CRS_ClearFlag_SYNCWARN();
01812
01813     /* user callback */
01814     HAL_RCCEx_CRS_SyncWarnCallback();
01815   }
01816   /* Check CRS Expected SYNC flag  */
01817   else if (((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U))
01818   {
01819     /* frequency error counter reached a zero value */
01820     LL_CRS_ClearFlag_ESYNC();
01821
01822     /* user callback */
01823     HAL_RCCEx_CRS_ExpectedSyncCallback();
01824   }
01825   /* Check CRS Error flags  */
01826   else
01827   {
01828     if (((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U))
01829     {
01830       if ((itflags & RCC_CRS_FLAG_SYNCERR) != 0U)
01831       {
01832         crserror |= RCC_CRS_SYNCERR;
01833       }
01834       if ((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U)
01835       {
01836         crserror |= RCC_CRS_SYNCMISS;
01837       }
01838       if ((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U)
01839       {
01840         crserror |= RCC_CRS_TRIMOVF;
01841       }
01842
01843       /* Clear CRS Error flags */
01844       LL_CRS_ClearFlag_ERR();
01845
01846       /* user error callback */
01847       HAL_RCCEx_CRS_ErrorCallback(crserror);
01848     }
01849   }
01850 }
01851
01852 /**
01853   * @brief  RCCEx Clock Recovery System SYNCOK interrupt callback.
01854   * @retval none
01855   */
01856 __weak void HAL_RCCEx_CRS_SyncOkCallback(void)
01857 {
01858   /* NOTE : This function should not be modified, when the callback is needed,
01859             the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file
01860    */
01861 }
01862
01863 /**
01864   * @brief  RCCEx Clock Recovery System SYNCWARN interrupt callback.
01865   * @retval none
01866   */
01867 __weak void HAL_RCCEx_CRS_SyncWarnCallback(void)
01868 {
01869   /* NOTE : This function should not be modified, when the callback is needed,
01870             the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file
01871    */
01872 }
01873
01874 /**
01875   * @brief  RCCEx Clock Recovery System Expected SYNC interrupt callback.
01876   * @retval none
01877   */
01878 __weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
01879 {
01880   /* NOTE : This function should not be modified, when the callback is needed,
01881             the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file
01882    */
01883 }
01884
01885 /**
01886   * @brief  RCCEx Clock Recovery System Error interrupt callback.
01887   * @param  Error Combination of Error status.
01888   *         This parameter can be a combination of the following values:
01889   *           @arg @ref RCC_CRS_SYNCERR
01890   *           @arg @ref RCC_CRS_SYNCMISS
01891   *           @arg @ref RCC_CRS_TRIMOVF
01892   * @retval none
01893   */
01894 __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
01895 {
01896   /* Prevent unused argument(s) compilation warning */
01897   UNUSED(Error);
01898
01899   /* NOTE : This function should not be modified, when the callback is needed,
01900             the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file
01901    */
01902 }
01903
01904 /**
01905   * @}
01906   */
01907 #endif
01908
01909 /**
01910   * @}
01911   */
01912
01913 /** @addtogroup RCCEx_Private_Functions
01914  * @{
01915  */
01916
01917 #if defined(SAI1)
01918 /**
01919   * @brief  Configure the parameters N & P of PLLSAI1 and enable PLLSAI1 output clock(s).
01920   * @param  PLLSAI1  pointer to an RCC_PLLSAI1InitTypeDef structure that
01921   *         contains the configuration parameters N & P as well as PLLSAI1 output clock(s)
01922   *
01923   * @note   PLLSAI1 is temporary disable to apply new parameters
01924   *
01925   * @retval HAL status
01926   */
01927 static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNP(RCC_PLLSAI1InitTypeDef *PLLSAI1)
01928 {
01929   uint32_t tickstart;
01930   HAL_StatusTypeDef status = HAL_OK;
01931
01932   /* check for PLLSAI1 Parameters used to output PLLSAI1CLK */
01933   assert_param(IS_RCC_PLLN_VALUE(PLLSAI1->PLLN));
01934   assert_param(IS_RCC_PLLP_VALUE(PLLSAI1->PLLP));
01935   assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PLLSAI1->PLLSAI1ClockOut));
01936
01937   /* Disable the PLLSAI1 */
01938   __HAL_RCC_PLLSAI1_DISABLE();
01939
01940   /* Get Start Tick*/
01941   tickstart = HAL_GetTick();
01942
01943   /* Wait till PLLSAI1 is ready to be updated */
01944   while (LL_RCC_PLLSAI1_IsReady() != 0U)
01945   {
01946     if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
01947     {
01948       status = HAL_TIMEOUT;
01949       break;
01950     }
01951   }
01952
01953   if (status == HAL_OK)
01954   {
01955     /* Configure the PLLSAI1 Multiplication factor N */
01956     __HAL_RCC_PLLSAI1_MULN_CONFIG(PLLSAI1->PLLN);
01957
01958     /* Configure the PLLSAI1 Division factor P */
01959     __HAL_RCC_PLLSAI1_DIVP_CONFIG(PLLSAI1->PLLP);
01960
01961     /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
01962     __HAL_RCC_PLLSAI1_ENABLE();
01963
01964     /* Get Start Tick*/
01965     tickstart = HAL_GetTick();
01966
01967     /* Wait till PLLSAI1 is ready */
01968     while (LL_RCC_PLLSAI1_IsReady() != 1U)
01969     {
01970       if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
01971       {
01972         status = HAL_TIMEOUT;
01973         break;
01974       }
01975     }
01976
01977     if (status == HAL_OK)
01978     {
01979       /* Configure the PLLSAI1 Clock output(s) */
01980       __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PLLSAI1->PLLSAI1ClockOut);
01981     }
01982   }
01983
01984   return status;
01985 }
01986
01987 /**
01988   * @brief  Configure the parameters N & Q of PLLSAI1 and enable PLLSAI1 output clock(s).
01989   * @param  PLLSAI1  pointer to an RCC_PLLSAI1InitTypeDef structure that
01990   *         contains the configuration parameters N & Q as well as PLLSAI1 output clock(s)
01991   *
01992   * @note   PLLSAI1 is temporary disable to apply new parameters
01993   *
01994   * @retval HAL status
01995   */
01996 static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNQ(RCC_PLLSAI1InitTypeDef *PLLSAI1)
01997 {
01998   uint32_t tickstart;
01999   HAL_StatusTypeDef status = HAL_OK;
02000
02001   /* check for PLLSAI1 Parameters used to output PLLSAI1CLK */
02002   assert_param(IS_RCC_PLLN_VALUE(PLLSAI1->PLLN));
02003   assert_param(IS_RCC_PLLQ_VALUE(PLLSAI1->PLLQ));
02004   assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PLLSAI1->PLLSAI1ClockOut));
02005
02006   /* Disable the PLLSAI1 */
02007   __HAL_RCC_PLLSAI1_DISABLE();
02008
02009   /* Get Start Tick*/
02010   tickstart = HAL_GetTick();
02011
02012   /* Wait till PLLSAI1 is ready to be updated */
02013   while (LL_RCC_PLLSAI1_IsReady() != 0U)
02014   {
02015     if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
02016     {
02017       status = HAL_TIMEOUT;
02018       break;
02019     }
02020   }
02021
02022   if (status == HAL_OK)
02023   {
02024     /* Configure the PLLSAI1 Multiplication factor N */
02025     __HAL_RCC_PLLSAI1_MULN_CONFIG(PLLSAI1->PLLN);
02026     /* Configure the PLLSAI1 Division factor Q */
02027     __HAL_RCC_PLLSAI1_DIVQ_CONFIG(PLLSAI1->PLLQ);
02028
02029     /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
02030     __HAL_RCC_PLLSAI1_ENABLE();
02031
02032     /* Get Start Tick*/
02033     tickstart = HAL_GetTick();
02034
02035     /* Wait till PLLSAI1 is ready */
02036     while (LL_RCC_PLLSAI1_IsReady() != 1U)
02037     {
02038       if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
02039       {
02040         status = HAL_TIMEOUT;
02041         break;
02042       }
02043     }
02044
02045     if (status == HAL_OK)
02046     {
02047       /* Configure the PLLSAI1 Clock output(s) */
02048       __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PLLSAI1->PLLSAI1ClockOut);
02049     }
02050   }
02051
02052   return status;
02053 }
02054
02055 /**
02056   * @brief  Configure the parameters N & R of PLLSAI1 and enable PLLSAI1 output clock(s).
02057   * @param  PLLSAI1  pointer to an RCC_PLLSAI1InitTypeDef structure that
02058   *         contains the configuration parameters N & R as well as PLLSAI1 output clock(s)
02059   *
02060   * @note   PLLSAI1 is temporary disable to apply new parameters
02061   *
02062   * @retval HAL status
02063   */
02064 static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNR(RCC_PLLSAI1InitTypeDef *PLLSAI1)
02065 {
02066   uint32_t tickstart;
02067   HAL_StatusTypeDef status = HAL_OK;
02068
02069   /* check for PLLSAI1 Parameters used to output PLLSAI1CLK */
02070   assert_param(IS_RCC_PLLN_VALUE(PLLSAI1->PLLN));
02071   assert_param(IS_RCC_PLLR_VALUE(PLLSAI1->PLLR));
02072   assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PLLSAI1->PLLSAI1ClockOut));
02073
02074   /* Disable the PLLSAI1 */
02075   __HAL_RCC_PLLSAI1_DISABLE();
02076
02077   /* Get Start Tick*/
02078   tickstart = HAL_GetTick();
02079
02080   /* Wait till PLLSAI1 is ready to be updated */
02081   while (LL_RCC_PLLSAI1_IsReady() != 0U)
02082   {
02083     if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
02084     {
02085       status = HAL_TIMEOUT;
02086       break;
02087     }
02088   }
02089
02090   if (status == HAL_OK)
02091   {
02092     /* Configure the PLLSAI1 Multiplication factor N */
02093     __HAL_RCC_PLLSAI1_MULN_CONFIG(PLLSAI1->PLLN);
02094     /* Configure the PLLSAI1 Division factor R */
02095     __HAL_RCC_PLLSAI1_DIVR_CONFIG(PLLSAI1->PLLR);
02096
02097     /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
02098     __HAL_RCC_PLLSAI1_ENABLE();
02099
02100     /* Get Start Tick*/
02101     tickstart = HAL_GetTick();
02102
02103     /* Wait till PLLSAI1 is ready */
02104     while (LL_RCC_PLLSAI1_IsReady() != 1U)
02105     {
02106       if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
02107       {
02108         status = HAL_TIMEOUT;
02109         break;
02110       }
02111     }
02112
02113     if (status == HAL_OK)
02114     {
02115       /* Configure the PLLSAI1 Clock output(s) */
02116       __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PLLSAI1->PLLSAI1ClockOut);
02117     }
02118   }
02119
02120   return status;
02121 }
02122 #endif
02123
02124 /**
02125   * @brief  Return PLL clock (PLLPCLK) frequency used for SAI domain
02126   * @retval PLLPCLK clock frequency (in Hz)
02127   */
02128 static uint32_t RCC_PLL_GetFreqDomain_P(void)
02129 {
02130   uint32_t pllinputfreq, pllsource;
02131
02132   /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI Value / PLLM) * PLLN
02133      SAI Domain clock = PLL_VCO / PLLP
02134   */
02135   pllsource = LL_RCC_PLL_GetMainSource();
02136
02137   switch (pllsource)
02138   {
02139     case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLL clock source */
02140       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
02141       break;
02142
02143     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
02144       pllinputfreq = HSI_VALUE;
02145       break;
02146
02147     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
02148       if (LL_RCC_HSE_IsEnabledDiv2() == 1U)
02149       {
02150         pllinputfreq = HSE_VALUE / 2U;
02151       }
02152       else
02153       {
02154         pllinputfreq = HSE_VALUE;
02155       }
02156       break;
02157
02158     default:
02159       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
02160       break;
02161   }
02162   return __LL_RCC_CALC_PLLCLK_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
02163                                        LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
02164 }
02165
02166
02167 /**
02168   * @brief  Return PLL clock (PLLQCLK) frequency used for 48 MHz domain
02169   * @retval PLLQCLK clock frequency (in Hz)
02170   */
02171 static uint32_t RCC_PLL_GetFreqDomain_Q(void)
02172 {
02173   uint32_t pllinputfreq, pllsource;
02174
02175   /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI Value/ PLLM) * PLLN
02176      48M Domain clock = PLL_VCO / PLLQ
02177   */
02178   pllsource = LL_RCC_PLL_GetMainSource();
02179
02180   switch (pllsource)
02181   {
02182     case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLL clock source */
02183       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
02184       break;
02185
02186     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
02187       pllinputfreq = HSI_VALUE;
02188       break;
02189
02190     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
02191       if (LL_RCC_HSE_IsEnabledDiv2() == 1U)
02192       {
02193         pllinputfreq = HSE_VALUE / 2U;
02194       }
02195       else
02196       {
02197         pllinputfreq = HSE_VALUE;
02198       }
02199
02200       break;
02201
02202     default:
02203       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
02204       break;
02205   }
02206   return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
02207                                        LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
02208 }
02209
02210 #if defined(SAI1)
02211 /**
02212   * @brief  Return PLLSAI1 clock (PLLSAI1RCLK) frequency used for ADC domain
02213   * @retval PLLSAI1RCLK clock frequency (in Hz)
02214   */
02215 static uint32_t RCC_PLLSAI1_GetFreqDomain_R(void)
02216 {
02217   uint32_t pllinputfreq, pllsource;
02218
02219   /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI Value/ PLLM) * PLLSAI1N */
02220   /* 48M Domain clock  = PLLSAI1_VCO / PLLSAI1R */
02221   pllsource = LL_RCC_PLL_GetMainSource();
02222
02223   switch (pllsource)
02224   {
02225     case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLLSAI1 clock source */
02226       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
02227       break;
02228
02229     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI1 clock source */
02230       pllinputfreq = HSI_VALUE;
02231       break;
02232
02233     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI1 clock source */
02234       if (LL_RCC_HSE_IsEnabledDiv2() == 1U)
02235       {
02236         pllinputfreq = HSE_VALUE / 2U;
02237       }
02238       else
02239       {
02240         pllinputfreq = HSE_VALUE;
02241       }
02242       break;
02243
02244     default:
02245       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
02246       break;
02247   }
02248   return __LL_RCC_CALC_PLLSAI1_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
02249                                         LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetR());
02250 }
02251
02252 /**
02253   * @brief  Return PLLSAI1 clock (PLLSAI1PCLK) frequency used for SAI domain
02254   * @retval PLLSAI1PCLK clock frequency (in Hz)
02255   */
02256 static uint32_t RCC_PLLSAI1_GetFreqDomain_P(void)
02257 {
02258   uint32_t pllinputfreq, pllsource;
02259
02260   /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI Value/ PLLM) * PLLSAI1N */
02261   /* SAI Domain clock  = PLLSAI1_VCO / PLLSAI1P */
02262   pllsource = LL_RCC_PLL_GetMainSource();
02263
02264   switch (pllsource)
02265   {
02266     case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLLSAI1 clock source */
02267       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
02268       break;
02269
02270     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI1 clock source */
02271       pllinputfreq = HSI_VALUE;
02272       break;
02273
02274     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI1 clock source */
02275       if (LL_RCC_HSE_IsEnabledDiv2() == 1U)
02276       {
02277         pllinputfreq = HSE_VALUE / 2U;
02278       }
02279       else
02280       {
02281         pllinputfreq = HSE_VALUE;
02282       }
02283       break;
02284
02285     default:
02286       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
02287       break;
02288   }
02289   return __LL_RCC_CALC_PLLSAI1_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
02290                                         LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetP());
02291 }
02292
02293 /**
02294   * @brief  Return PLLSAI1 clock (PLLSAI1QCLK) frequency used for 48Mhz domain
02295   * @retval PLLSAI1QCLK clock frequency (in Hz)
02296   */
02297 static uint32_t RCC_PLLSAI1_GetFreqDomain_Q(void)
02298 {
02299   uint32_t pllinputfreq, pllsource;
02300
02301   /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI Value/ PLLM) * PLLSAI1N */
02302   /* 48M Domain clock  = PLLSAI1_VCO / PLLSAI1Q */
02303   pllsource = LL_RCC_PLL_GetMainSource();
02304
02305   switch (pllsource)
02306   {
02307     case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLLSAI1 clock source */
02308       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
02309       break;
02310
02311     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI1 clock source */
02312       pllinputfreq = HSI_VALUE;
02313       break;
02314
02315     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI1 clock source */
02316       if (LL_RCC_HSE_IsEnabledDiv2() == 1U)
02317       {
02318         pllinputfreq = HSE_VALUE / 2U;
02319       }
02320       else
02321       {
02322         pllinputfreq = HSE_VALUE;
02323       }
02324       break;
02325
02326     default:
02327       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
02328       break;
02329   }
02330   return __LL_RCC_CALC_PLLSAI1_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
02331                                         LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetQ());
02332 }
02333 #endif
02334 /**
02335   * @}
02336   */
02337
02338 #endif /* HAL_RCC_MODULE_ENABLED */
02339 /**
02340   * @}
02341   */
02342
02343 /**
02344   * @}
02345   */
02346
02347 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
02348
Generated on Fri Sep 6 2019 11:34:35 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_rcc_ex.h Source File

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stm32wbxx_hal_rcc_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_rcc_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of RCC HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_RCC_EX_H
00022 #define STM32WBxx_HAL_RCC_EX_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030 #include "stm32wbxx_ll_crs.h"
00031 #include "stm32wbxx_ll_exti.h"
00032 #include "stm32wbxx_ll_pwr.h"
00033
00034 /** @addtogroup STM32WBxx_HAL_Driver
00035   * @{
00036   */
00037
00038 /** @addtogroup RCCEx
00039   * @{
00040   */
00041 /* Private constants ---------------------------------------------------------*/
00042 /** @addtogroup RCC_Private_Constants
00043   * @{
00044   */
00045 /* CRS IT Error Mask */
00046 #define  RCC_CRS_IT_ERROR_MASK                 ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
00047
00048 /* CRS Flag Error Mask */
00049 #define RCC_CRS_FLAG_ERROR_MASK                ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
00050
00051 /* RNG closk selection CLK48 clock mask */
00052 #define CLK48_MASK   0x10000000U
00053 /**
00054   * @}
00055   */
00056
00057
00058 /* Private macros ------------------------------------------------------------*/
00059 /** @addtogroup RCCEx_Private_Macros
00060   * @{
00061   */
00062 #define IS_RCC_LSCO(__LSCOX__) ( ((__LSCOX__) == RCC_LSCO1) || ((__LSCOX__) == RCC_LSCO2) || ((__LSCOX__) == RCC_LSCO3) )
00063
00064 #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \
00065                                        ((__SOURCE__) == RCC_LSCOSOURCE_LSE))
00066
00067 #if defined(LPUART1) && defined(I2C3) && defined(SAI1) && defined(USB) && defined(RCC_SMPS_SUPPORT)
00068 #define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
00069                ((((__SELECTION__) & RCC_PERIPHCLK_USART1)   == RCC_PERIPHCLK_USART1)  || \
00070                 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)  || \
00071                 (((__SELECTION__) & RCC_PERIPHCLK_I2C1)      == RCC_PERIPHCLK_I2C1)   || \
00072                 (((__SELECTION__) & RCC_PERIPHCLK_I2C3)     == RCC_PERIPHCLK_I2C3)    || \
00073                 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)   == RCC_PERIPHCLK_LPTIM1)  || \
00074                 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)   == RCC_PERIPHCLK_LPTIM2)  || \
00075                 (((__SELECTION__) & RCC_PERIPHCLK_SAI1)     == RCC_PERIPHCLK_SAI1)    || \
00076                 (((__SELECTION__) & RCC_PERIPHCLK_USB)      == RCC_PERIPHCLK_USB)     || \
00077                 (((__SELECTION__) & RCC_PERIPHCLK_RNG)      == RCC_PERIPHCLK_RNG)     || \
00078                 (((__SELECTION__) & RCC_PERIPHCLK_ADC)      == RCC_PERIPHCLK_ADC)     || \
00079                 (((__SELECTION__) & RCC_PERIPHCLK_RTC)      == RCC_PERIPHCLK_RTC)     || \
00080                 (((__SELECTION__) & RCC_PERIPHCLK_RFWAKEUP) == RCC_PERIPHCLK_RFWAKEUP)|| \
00081                 (((__SELECTION__) & RCC_PERIPHCLK_SMPS)     == RCC_PERIPHCLK_SMPS))
00082 #else
00083 #define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
00084                ((((__SELECTION__) & RCC_PERIPHCLK_USART1)   == RCC_PERIPHCLK_USART1)  || \
00085                 (((__SELECTION__) & RCC_PERIPHCLK_I2C1)      == RCC_PERIPHCLK_I2C1)   || \
00086                 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)   == RCC_PERIPHCLK_LPTIM1)  || \
00087                 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)   == RCC_PERIPHCLK_LPTIM2)  || \
00088                 (((__SELECTION__) & RCC_PERIPHCLK_RNG)      == RCC_PERIPHCLK_RNG)     || \
00089                 (((__SELECTION__) & RCC_PERIPHCLK_ADC)      == RCC_PERIPHCLK_ADC)     || \
00090                 (((__SELECTION__) & RCC_PERIPHCLK_RTC)      == RCC_PERIPHCLK_RTC)     || \
00091                 (((__SELECTION__) & RCC_PERIPHCLK_RFWAKEUP) == RCC_PERIPHCLK_RFWAKEUP))
00092 #endif
00093
00094 #define IS_RCC_USART1CLKSOURCE(__SOURCE__)  \
00095                (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2)  || \
00096                 ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
00097                 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE)    || \
00098                 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
00099
00100 #if defined(LPUART1)
00101 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__)  \
00102                (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1)  || \
00103                 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
00104                 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE)    || \
00105                 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
00106 #endif
00107
00108 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__)   \
00109                (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
00110                 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
00111                 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
00112
00113 #if defined(I2C3)
00114 #define IS_RCC_I2C3CLKSOURCE(__SOURCE__)   \
00115                (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \
00116                 ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
00117                 ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
00118 #endif
00119
00120 #if defined(SAI1)
00121 #define IS_RCC_SAI1CLK(__SOURCE__)   \
00122                (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \
00123                 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \
00124                 ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI)     || \
00125                 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
00126 #endif
00127
00128 #define IS_RCC_LPTIM1CLK(__SOURCE__)  \
00129                (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \
00130                 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI)  || \
00131                 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI)  || \
00132                 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE))
00133
00134 #define IS_RCC_LPTIM2CLK(__SOURCE__)  \
00135                (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \
00136                 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI)  || \
00137                 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI)  || \
00138                 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE))
00139
00140 #define IS_RCC_RNGCLKSOURCE(__SOURCE__)  \
00141                (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48)   || \
00142                 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL)     || \
00143                 ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI)     || \
00144                 ((__SOURCE__) == RCC_RNGCLKSOURCE_CLK48)   || \
00145                 ((__SOURCE__) == RCC_RNGCLKSOURCE_LSI)     || \
00146                 ((__SOURCE__) == RCC_RNGCLKSOURCE_LSE))
00147
00148 #if defined(SAI1)
00149 #define IS_RCC_USBCLKSOURCE(__SOURCE__)  \
00150                (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48)   || \
00151                 ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \
00152                 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL)     || \
00153                 ((__SOURCE__) == RCC_USBCLKSOURCE_MSI))
00154 #else
00155 #define IS_RCC_USBCLKSOURCE(__SOURCE__)  \
00156                (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48)   || \
00157                 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL)     || \
00158                 ((__SOURCE__) == RCC_USBCLKSOURCE_MSI))
00159 #endif
00160
00161 #if defined(SAI1)
00162 #define IS_RCC_ADCCLKSOURCE(__SOURCE__)  \
00163                (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \
00164                 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLL) || \
00165                 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \
00166                 ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
00167 #else
00168 #define IS_RCC_ADCCLKSOURCE(__SOURCE__)  \
00169                (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \
00170                 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLL) || \
00171                 ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
00172 #endif
00173
00174 #define IS_RCC_RFWKPCLKSOURCE(__SOURCE__)  \
00175                (((__SOURCE__) == RCC_RFWKPCLKSOURCE_NONE) || \
00176                 ((__SOURCE__) == RCC_RFWKPCLKSOURCE_LSE) || \
00177                 ((__SOURCE__) == RCC_RFWKPCLKSOURCE_LSI) || \
00178                 ((__SOURCE__) == RCC_RFWKPCLKSOURCE_HSE_DIV1024))
00179
00180 #if defined(RCC_SMPS_SUPPORT)
00181 #define IS_RCC_SMPSCLKDIV(__DIV__)  \
00182                (((__DIV__) == RCC_SMPSCLKDIV_RANGE0) || \
00183                 ((__DIV__) == RCC_SMPSCLKDIV_RANGE1) || \
00184                 ((__DIV__) == RCC_SMPSCLKDIV_RANGE2) || \
00185                 ((__DIV__) == RCC_SMPSCLKDIV_RANGE3))
00186
00187 #define IS_RCC_SMPSCLKSOURCE(__SOURCE__)  \
00188                (((__SOURCE__) == RCC_SMPSCLKSOURCE_HSI)    || \
00189                 ((__SOURCE__) == RCC_SMPSCLKSOURCE_MSI)    || \
00190                 ((__SOURCE__) == RCC_SMPSCLKSOURCE_HSE))
00191 #endif
00192
00193 #if defined(SAI1)
00194 #define IS_RCC_PLLSAI1N_VALUE(__VALUE__)   ((6U <= (__VALUE__)) && ((__VALUE__) <= 127U))
00195
00196 #define IS_RCC_PLLSAI1P_VALUE(__VALUE__)   ((RCC_PLLP_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLP_DIV32))
00197
00198 #define IS_RCC_PLLSAI1Q_VALUE(__VALUE__)   ((RCC_PLLQ_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLQ_DIV8))
00199
00200 #define IS_RCC_PLLSAI1R_VALUE(__VALUE__)   ((RCC_PLLR_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLR_DIV8))
00201 #endif
00202
00203 #define IS_RCC_TRIMOSC(__VALUE__)          ((__VALUE__) == RCC_OSCILLATORTYPE_LSI2)
00204
00205 #if defined(CRS)
00206 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \
00207                                             ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE)  || \
00208                                             ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))
00209
00210 #define IS_RCC_CRS_SYNC_DIV(__DIV__)       (((__DIV__) == RCC_CRS_SYNC_DIV1)  || ((__DIV__) == RCC_CRS_SYNC_DIV2)  || \
00211                                             ((__DIV__) == RCC_CRS_SYNC_DIV4)  || ((__DIV__) == RCC_CRS_SYNC_DIV8)  || \
00212                                             ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
00213                                             ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
00214
00215 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
00216                                                 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
00217
00218 #define IS_RCC_CRS_RELOADVALUE(__VALUE__)  (((__VALUE__) <= 0xFFFFU))
00219
00220 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__)   (((__VALUE__) <= 0xFFU))
00221
00222 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
00223
00224 #define IS_RCC_CRS_FREQERRORDIR(__DIR__)   (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
00225                                             ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
00226 #endif
00227 /**
00228   * @}
00229   */
00230
00231 /* Exported types ------------------------------------------------------------*/
00232
00233 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
00234   * @{
00235   */
00236
00237 #if defined(SAI1)
00238 /**
00239   * @brief  PLLSAI1 Clock structure definition
00240   */
00241 typedef struct
00242 {
00243
00244   uint32_t PLLN;             /*!< PLLN: specifies the multiplication factor for PLLSAI1 VCO output clock.
00245                                   This parameter must be a number between Min_Data=6 and Max_Data=127. */
00246
00247   uint32_t PLLP;             /*!< PLLP: specifies the division factor for SAI clock.
00248                                   This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
00249
00250   uint32_t PLLQ;             /*!< PLLQ: specifies the division factor for USB/RNG clock.
00251                                   This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */
00252
00253   uint32_t PLLR;             /*!< PLLR: specifies the division factor for ADC clock.
00254                                   This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
00255
00256   uint32_t PLLSAI1ClockOut;  /*!< PLLSAI1ClockOut: specifies PLLSAI1 output clock to be enabled.
00257                                   This parameter must be a value of @ref RCC_PLLSAI1_Clock_Output */
00258 } RCC_PLLSAI1InitTypeDef;
00259 #endif
00260
00261 /**
00262   * @brief  RCC extended clocks structure definition
00263   */
00264 typedef struct
00265 {
00266   uint32_t PeriphClockSelection;   /*!< The Extended Clock to be configured.
00267                                         This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
00268
00269 #if defined(SAI1)
00270   RCC_PLLSAI1InitTypeDef PLLSAI1;  /*!< PLLSAI1 structure parameters.
00271                                         This parameter will be used only when PLLSAI1 is selected as Clock
00272                                         Source for SAI, USB/RNG or ADC */
00273 #endif
00274
00275   uint32_t Usart1ClockSelection;   /*!< Specifies USART1 clock source.
00276                                         This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
00277
00278 #if defined(LPUART1)
00279   uint32_t Lpuart1ClockSelection;  /*!< Specifies LPUART1 clock source.
00280                                         This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
00281 #endif
00282
00283   uint32_t I2c1ClockSelection;     /*!< Specifies I2C1 clock source.
00284                                         This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
00285
00286 #if defined(I2C3)
00287   uint32_t I2c3ClockSelection;     /*!< Specifies I2C3 clock source.
00288                                         This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
00289 #endif
00290
00291   uint32_t Lptim1ClockSelection;   /*!< Specifies LPTIM1 clock source.
00292                                         This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
00293
00294   uint32_t Lptim2ClockSelection;   /*!< Specifies LPTIM2 clock source.
00295                                         This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */
00296
00297 #if defined(SAI1)
00298   uint32_t Sai1ClockSelection;     /*!< Specifies SAI1 clock source.
00299                                         This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
00300 #endif
00301
00302   uint32_t UsbClockSelection;      /*!< Specifies USB clock source (warning: same source for RNG).
00303                                         This parameter can be a value of @ref RCCEx_USB_Clock_Source */
00304
00305   uint32_t RngClockSelection;      /*!< Specifies RNG clock source (warning: same source for USB).
00306                                         This parameter can be a value of @ref RCCEx_RNG_Clock_Source */
00307
00308
00309   uint32_t AdcClockSelection;      /*!< Specifies ADC interface clock source.
00310                                         This parameter can be a value of @ref RCCEx_ADC_Clock_Source */
00311
00312   uint32_t RTCClockSelection;      /*!< Specifies RTC clock source (also used for LCD).
00313                                         This parameter can be a value of @ref RCC_RTC_Clock_Source */
00314
00315   uint32_t RFWakeUpClockSelection; /*!< Specifies RF Wake-up clock source.
00316                                         This parameter can be a value of @ref RCCEx_RFWKP_Clock_Source */
00317
00318 #if defined(RCC_SMPS_SUPPORT)
00319   uint32_t SmpsClockSelection;     /*!< Specifies SMPS clock source.
00320                                         This parameter can be a value of @ref RCCEx_SMPS_Clock_Source */
00321
00322   uint32_t SmpsDivSelection;       /*!< Specifies SMPS clock division factor.
00323                                         This parameter can be a value of @ref RCCEx_SMPS_Clock_Divider */
00324 #endif
00325 } RCC_PeriphCLKInitTypeDef;
00326
00327
00328 #if defined(CRS)
00329 /**
00330   * @brief RCC_CRS Init structure definition
00331   */
00332 typedef struct
00333 {
00334   uint32_t Prescaler;             /*!< Specifies the division factor of the SYNC signal.
00335                                        This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
00336
00337   uint32_t Source;                /*!< Specifies the SYNC signal source.
00338                                        This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
00339
00340   uint32_t Polarity;              /*!< Specifies the input polarity for the SYNC signal source.
00341                                        This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
00342
00343   uint32_t ReloadValue;           /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
00344                                        It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)
00345                                        This parameter must be a number between Min_Data=0 and Max_Data=0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
00346
00347   uint32_t ErrorLimitValue;       /*!< Specifies the value to be used to evaluate the captured frequency error value.
00348                                        This parameter must be a number between Min_Data=0 and Max_Data=0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
00349
00350   uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
00351                                        This parameter must be a number between Min_Data=0 and Max_Data=0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
00352
00353 } RCC_CRSInitTypeDef;
00354
00355 /**
00356   * @brief RCC_CRS Synchronization structure definition
00357   */
00358 typedef struct
00359 {
00360   uint32_t ReloadValue;           /*!< Specifies the value loaded in the Counter reload value.
00361                                        This parameter must be a number between Min_Data=0 and Max_Data=0xFFFF */
00362
00363   uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
00364                                        This parameter must be a number between Min_Data=0 and Max_Data=0x3F */
00365
00366   uint32_t FreqErrorCapture;      /*!< Specifies the value loaded in the .FECAP, the frequency error counter
00367                                        value latched in the time of the last SYNC event.
00368                                        This parameter must be a number between Min_Data=0 and Max_Data=0xFFFF */
00369
00370   uint32_t FreqErrorDirection;    /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
00371                                        frequency error counter latched in the time of the last SYNC event.
00372                                        It shows whether the actual frequency is below or above the target.
00373                                        This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
00374
00375 } RCC_CRSSynchroInfoTypeDef;
00376 #endif
00377
00378 /**
00379   * @}
00380   */
00381
00382 /* Exported constants --------------------------------------------------------*/
00383 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
00384   * @{
00385   */
00386
00387 /** @defgroup RCC_LSCO_Index LSCO Index
00388   * @{
00389   */
00390 #define RCC_LSCO1                       0x00000000U          /*!< LSCO1 index */
00391 #define RCC_LSCO2                       0x00000001U          /*!< LSCO2 index */
00392 #define RCC_LSCO3                       0x00000002U          /*!< LSCO3 index */
00393 /**
00394   * @}
00395   */
00396
00397
00398 /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source
00399   * @{
00400   */
00401 #define RCC_LSCOSOURCE_LSI             LL_RCC_LSCO_CLKSOURCE_LSI      /*!< LSI selection for low speed clock output */
00402 #define RCC_LSCOSOURCE_LSE             LL_RCC_LSCO_CLKSOURCE_LSE      /*!< LSE selection for low speed clock output */
00403 /**
00404   * @}
00405   */
00406
00407 /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
00408   * @{
00409   */
00410 #define RCC_PERIPHCLK_USART1           0x00000001U                    /*!< USART1 Peripheral Clock Selection      */
00411 #if defined(LPUART1)
00412 #define RCC_PERIPHCLK_LPUART1          0x00000002U                    /*!< LPUART1 Peripheral Clock Selection     */
00413 #endif
00414 #define RCC_PERIPHCLK_I2C1             0x00000004U                    /*!< I2C1 Peripheral Clock Selection        */
00415 #if defined(I2C3)
00416 #define RCC_PERIPHCLK_I2C3             0x00000008U                    /*!< I2C3 Peripheral Clock Selection        */
00417 #endif
00418 #define RCC_PERIPHCLK_LPTIM1           0x00000010U                    /*!< LPTIM1 Peripheral Clock Selection      */
00419 #define RCC_PERIPHCLK_LPTIM2           0x00000020U                    /*!< LPTIM2 Peripheral Clock Selection      */
00420 #if defined(SAI1)
00421 #define RCC_PERIPHCLK_SAI1             0x00000040U                    /*!< SAI1 Peripheral Clock Selection        */
00422 #endif
00423 #define RCC_PERIPHCLK_CLK48SEL         0x00000100U                    /*!< 48 MHz clock source selection          */
00424 #define RCC_PERIPHCLK_USB              RCC_PERIPHCLK_CLK48SEL         /*!< USB Peripheral Clock Selection         */
00425 #define RCC_PERIPHCLK_RNG              0x00000200U                    /*!< RNG Peripheral Clock Selection         */
00426 #define RCC_PERIPHCLK_ADC              0x00000400U                    /*!< ADC Peripheral Clock Selection         */
00427 #define RCC_PERIPHCLK_RTC              0x00000800U                    /*!< RTC Peripheral Clock Selection         */
00428 #define RCC_PERIPHCLK_RFWAKEUP         0x00001000U                    /*!< RF Wakeup Peripheral Clock Selection   */
00429 #if defined(RCC_SMPS_SUPPORT)
00430 #define RCC_PERIPHCLK_SMPS             0x00002000U                    /*!< SMPS Peripheral Clock Selection         */
00431 #endif
00432 /**
00433   * @}
00434   */
00435
00436 /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source
00437   * @{
00438   */
00439 #define RCC_USART1CLKSOURCE_PCLK2      LL_RCC_USART1_CLKSOURCE_PCLK2  /*!< APB2 clock selected as USART 1 clock*/
00440 #define RCC_USART1CLKSOURCE_SYSCLK     LL_RCC_USART1_CLKSOURCE_SYSCLK /*!< SYSCLK clock selected as USART 1 clock*/
00441 #define RCC_USART1CLKSOURCE_HSI        LL_RCC_USART1_CLKSOURCE_HSI    /*!< HSI clock selected as USART 1 clock*/
00442 #define RCC_USART1CLKSOURCE_LSE        LL_RCC_USART1_CLKSOURCE_LSE    /*!< LSE clock selected as USART 1 clock*/
00443 /**
00444   * @}
00445   */
00446
00447 #if defined(LPUART1)
00448 /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source
00449   * @{
00450   */
00451 #define RCC_LPUART1CLKSOURCE_PCLK1     LL_RCC_LPUART1_CLKSOURCE_PCLK1  /*!< APB1 clock selected as LPUART 1 clock*/
00452 #define RCC_LPUART1CLKSOURCE_SYSCLK    LL_RCC_LPUART1_CLKSOURCE_SYSCLK /*!< SYSCLK clock selected as LPUART 1 clock*/
00453 #define RCC_LPUART1CLKSOURCE_HSI       LL_RCC_LPUART1_CLKSOURCE_HSI    /*!< HSI clock selected as LPUART 1 clock*/
00454 #define RCC_LPUART1CLKSOURCE_LSE       LL_RCC_LPUART1_CLKSOURCE_LSE    /*!< LSE clock selected as LPUART 1 clock*/
00455 /**
00456   * @}
00457   */
00458 #endif
00459
00460 /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source
00461   * @{
00462   */
00463 #define RCC_I2C1CLKSOURCE_PCLK1        LL_RCC_I2C1_CLKSOURCE_PCLK1    /*!< APB1 clock selected as I2C1 clock */
00464 #define RCC_I2C1CLKSOURCE_SYSCLK       LL_RCC_I2C1_CLKSOURCE_SYSCLK   /*!< SYSCLK clock selected as I2C1 clock */
00465 #define RCC_I2C1CLKSOURCE_HSI          LL_RCC_I2C1_CLKSOURCE_HSI      /*!< HSI clock selected as I2C1 clock */
00466 /**
00467   * @}
00468   */
00469
00470 #if defined(I2C3)
00471 /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source
00472   * @{
00473   */
00474 #define RCC_I2C3CLKSOURCE_PCLK1        LL_RCC_I2C3_CLKSOURCE_PCLK1   /*!< APB1 clock selected as I2C3 clock */
00475 #define RCC_I2C3CLKSOURCE_SYSCLK       LL_RCC_I2C3_CLKSOURCE_SYSCLK  /*!< SYSCLK clock selected as I2C3 clock */
00476 #define RCC_I2C3CLKSOURCE_HSI          LL_RCC_I2C3_CLKSOURCE_HSI     /*!< HSI clock selected as I2C3 clock */
00477 /**
00478   * @}
00479   */
00480 #endif
00481
00482 #if defined(SAI1)
00483 /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source
00484   * @{
00485   */
00486 #define RCC_SAI1CLKSOURCE_PLLSAI1      LL_RCC_SAI1_CLKSOURCE_PLLSAI1  /*!< PLLSAI "P" clock selected as SAI1 clock  */
00487 #define RCC_SAI1CLKSOURCE_PLL          LL_RCC_SAI1_CLKSOURCE_PLL      /*!< PLL "P" clock selected as SAI1 clock     */
00488 #define RCC_SAI1CLKSOURCE_HSI          LL_RCC_SAI1_CLKSOURCE_HSI      /*!< HSI clock selected as SAI1 clock         */
00489 #define RCC_SAI1CLKSOURCE_PIN          LL_RCC_SAI1_CLKSOURCE_PIN      /*!< External PIN clock selected as SAI1 clock */
00490 /**
00491   * @}
00492   */
00493 #endif
00494
00495 /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source
00496   * @{
00497   */
00498 #define RCC_LPTIM1CLKSOURCE_PCLK1      LL_RCC_LPTIM1_CLKSOURCE_PCLK1  /*!< APB1 clock selected as LPTIM1 clock */
00499 #define RCC_LPTIM1CLKSOURCE_LSI        LL_RCC_LPTIM1_CLKSOURCE_LSI    /*!< LSI clock selected as LPTIM1 clock  */
00500 #define RCC_LPTIM1CLKSOURCE_HSI        LL_RCC_LPTIM1_CLKSOURCE_HSI    /*!< HSI clock selected as LPTIM1 clock  */
00501 #define RCC_LPTIM1CLKSOURCE_LSE        LL_RCC_LPTIM1_CLKSOURCE_LSE    /*!< LSE clock selected as LPTIM1 clock  */
00502 /**
00503   * @}
00504   */
00505
00506 /** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source
00507   * @{
00508   */
00509 #define RCC_LPTIM2CLKSOURCE_PCLK1      LL_RCC_LPTIM2_CLKSOURCE_PCLK1  /*!< APB1 clock selected as LPTIM2 clock */
00510 #define RCC_LPTIM2CLKSOURCE_LSI        LL_RCC_LPTIM2_CLKSOURCE_LSI    /*!< LSI clock selected as LPTIM2 clock  */
00511 #define RCC_LPTIM2CLKSOURCE_HSI        LL_RCC_LPTIM2_CLKSOURCE_HSI    /*!< HSI clock selected as LPTIM2 clock  */
00512 #define RCC_LPTIM2CLKSOURCE_LSE        LL_RCC_LPTIM2_CLKSOURCE_LSE    /*!< LSE clock selected as LPTIM2 clock  */
00513 /**
00514   * @}
00515   */
00516
00517 /** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source
00518   * @{
00519   */
00520 #define RCC_RNGCLKSOURCE_HSI48         (CLK48_MASK | LL_RCC_CLK48_CLKSOURCE_HSI48)  /*!< HSI48 clock divided by 3 selected as RNG clock    */
00521 #define RCC_RNGCLKSOURCE_PLL           (CLK48_MASK | LL_RCC_CLK48_CLKSOURCE_PLL)    /*!< PLL "Q" clock divided by 3  selected as RNG clock */
00522 #define RCC_RNGCLKSOURCE_MSI           (CLK48_MASK | LL_RCC_CLK48_CLKSOURCE_MSI)    /*!< MSI clock divided by 3 selected as RNG clock      */
00523 #define RCC_RNGCLKSOURCE_CLK48         LL_RCC_RNG_CLKSOURCE_CLK48                   /*!< CLK48 divided by 3 selected as RNG Clock          */
00524 #define RCC_RNGCLKSOURCE_LSI           LL_RCC_RNG_CLKSOURCE_LSI                     /*!< LSI clock selected as RNG clock                   */
00525 #define RCC_RNGCLKSOURCE_LSE           LL_RCC_RNG_CLKSOURCE_LSE                     /*!< LSE clock selected as RNG clock                   */
00526 /**
00527   * @}
00528   */
00529
00530 /** @defgroup RCCEx_USB_Clock_Source USB Clock Source
00531   * @{
00532   */
00533 #define RCC_USBCLKSOURCE_HSI48         LL_RCC_USB_CLKSOURCE_HSI48     /*!< HSI48 clock selected as USB clock       */
00534 #define RCC_USBCLKSOURCE_PLLSAI1       LL_RCC_USB_CLKSOURCE_PLLSAI1   /*!< PLLSAI1 "Q" clock selected as USB clock */
00535 #define RCC_USBCLKSOURCE_PLL           LL_RCC_USB_CLKSOURCE_PLL       /*!< PLL "Q" clock selected as USB clock     */
00536 #define RCC_USBCLKSOURCE_MSI           LL_RCC_USB_CLKSOURCE_MSI       /*!< MSI clock selected as USB clock         */
00537 /**
00538   * @}
00539   */
00540
00541 /** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source
00542   * @{
00543   */
00544
00545 #define RCC_ADCCLKSOURCE_NONE          LL_RCC_ADC_CLKSOURCE_NONE      /*!< None clock selected as ADC clock        */
00546 #if defined(SAI1)
00547 #define RCC_ADCCLKSOURCE_PLLSAI1       LL_RCC_ADC_CLKSOURCE_PLLSAI1   /*!< PLLSAI1 "R" clock selected as ADC clock */
00548 #endif
00549 #define RCC_ADCCLKSOURCE_PLL           LL_RCC_ADC_CLKSOURCE_PLL       /*!< PLL "P" clock selected as ADC clock     */
00550 #define RCC_ADCCLKSOURCE_SYSCLK        LL_RCC_ADC_CLKSOURCE_SYSCLK    /*!< SYSCLK clock selected as ADC clock      */
00551
00552 /**
00553   * @}
00554   */
00555
00556 /** @defgroup RCCEx_HCLK5_Clock_Source HCLK RF Clock Source
00557   * @{
00558   */
00559
00560 #define RCC_HCLK5SOURCE_HSI            0x00000001U  /*!< HSI clock not divided selected as Radio Domain clock */
00561 #define RCC_HCLK5SOURCE_HSE            0x00000002U  /*!< HSE clock divided by 2 selected as Radio Domain clock */
00562
00563 /**
00564   * @}
00565   */
00566
00567 /** @defgroup RCCEx_RFWKP_Clock_Source RF WKP Clock Source
00568   * @{
00569   */
00570
00571 #define RCC_RFWKPCLKSOURCE_NONE          LL_RCC_RFWKP_CLKSOURCE_NONE  /*!< None clock selected as RF system wakeup clock                      */
00572 #define RCC_RFWKPCLKSOURCE_LSE           LL_RCC_RFWKP_CLKSOURCE_LSE   /*!< LSE clock selected as RF system wakeup clock                       */
00573 #define RCC_RFWKPCLKSOURCE_LSI           LL_RCC_RFWKP_CLKSOURCE_LSI   /*!< LSI clock selected as RF system wakeup clock                       */
00574 #define RCC_RFWKPCLKSOURCE_HSE_DIV1024   LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024 /*!< HSE clock divided by 1024 selected as RF system wakeup clock */
00575
00576 /**
00577   * @}
00578   */
00579
00580
00581 #if defined(RCC_SMPS_SUPPORT)
00582 /** @defgroup RCCEx_SMPS_Clock_Source SMPS Clock Source
00583   * @{
00584   */
00585 #define RCC_SMPSCLKSOURCE_HSI            LL_RCC_SMPS_CLKSOURCE_HSI     /*!< HSI selection as smps clock */
00586 #define RCC_SMPSCLKSOURCE_MSI            LL_RCC_SMPS_CLKSOURCE_MSI     /*!< MSI selection as smps clock */
00587 #define RCC_SMPSCLKSOURCE_HSE            LL_RCC_SMPS_CLKSOURCE_HSE     /*!< HSE selection as smps clock */
00588 /**
00589   * @}
00590   */
00591
00592 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
00593   * @{
00594   */
00595 #define RCC_SMPSCLKSOURCE_STATUS_HSI    LL_RCC_SMPS_CLKSOURCE_STATUS_HSI     /*!< HSI selection as smps clock */
00596 #define RCC_SMPSCLKSOURCE_STATUS_MSI    LL_RCC_SMPS_CLKSOURCE_STATUS_MSI     /*!< MSI selection as smps clock */
00597 #define RCC_SMPSCLKSOURCE_STATUS_HSE    LL_RCC_SMPS_CLKSOURCE_STATUS_HSE     /*!< HSE selection as smps clock */
00598 /**
00599   * @}
00600   */
00601
00602 /** @defgroup RCCEx_SMPS_Clock_Divider SMPS Clock Division Factor
00603   * @{
00604   */
00605 #define RCC_SMPSCLKDIV_RANGE0           LL_RCC_SMPS_DIV_0            /*!< PLLM division factor = 0 */
00606 #define RCC_SMPSCLKDIV_RANGE1           LL_RCC_SMPS_DIV_1            /*!< PLLM division factor = 1 */
00607 #define RCC_SMPSCLKDIV_RANGE2           LL_RCC_SMPS_DIV_2            /*!< PLLM division factor = 2 */
00608 #define RCC_SMPSCLKDIV_RANGE3           LL_RCC_SMPS_DIV_3            /*!< PLLM division factor = 3 */
00609 /**
00610   * @}
00611   */
00612 #endif
00613
00614 /** @defgroup RCCEx_EXTI_LINE_LSECSS  RCC LSE CSS external interrupt line
00615   * @{
00616   */
00617 #define  RCC_EXTI_LINE_LSECSS          EXTI_IMR1_IM18       /*!< External interrupt line 18 connected to the LSE CSS EXTI Line */
00618
00619 /**
00620   * @}
00621   */
00622
00623
00624 #if defined(CRS)
00625 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status
00626   * @{
00627   */
00628 #define RCC_CRS_NONE                   0x00000000U            /*!< CRS status none                           */
00629 #define RCC_CRS_TIMEOUT                0x00000001U            /*!< CRS status timeout                        */
00630 #define RCC_CRS_SYNCOK                 0x00000002U            /*!< CRS status synchronization success        */
00631 #define RCC_CRS_SYNCWARN               0x00000004U            /*!< CRS status synchronization warning        */
00632 #define RCC_CRS_SYNCERR                0x00000008U            /*!< CRS status synchronization error          */
00633 #define RCC_CRS_SYNCMISS               0x00000010U            /*!< CRS status synchronization missed         */
00634 #define RCC_CRS_TRIMOVF                0x00000020U            /*!< CRS status trimming overflow or underflow */
00635 /**
00636   * @}
00637   */
00638
00639 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
00640   * @{
00641   */
00642 #define RCC_CRS_SYNC_SOURCE_GPIO       LL_CRS_SYNC_SOURCE_GPIO             /*!< Synchro Signal source GPIO */
00643 #define RCC_CRS_SYNC_SOURCE_LSE        LL_CRS_SYNC_SOURCE_LSE              /*!< Synchro Signal source LSE */
00644 #define RCC_CRS_SYNC_SOURCE_USB        LL_CRS_SYNC_SOURCE_USB              /*!< Synchro Signal source USB SOF (default)*/
00645 /**
00646   * @}
00647   */
00648
00649 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
00650   * @{
00651   */
00652 #define RCC_CRS_SYNC_DIV1        LL_CRS_SYNC_DIV_1                        /*!< Synchro Signal not divided (default) */
00653 #define RCC_CRS_SYNC_DIV2        LL_CRS_SYNC_DIV_2                        /*!< Synchro Signal divided by 2 */
00654 #define RCC_CRS_SYNC_DIV4        LL_CRS_SYNC_DIV_4                        /*!< Synchro Signal divided by 4 */
00655 #define RCC_CRS_SYNC_DIV8        LL_CRS_SYNC_DIV_8                        /*!< Synchro Signal divided by 8 */
00656 #define RCC_CRS_SYNC_DIV16       LL_CRS_SYNC_DIV_16                       /*!< Synchro Signal divided by 16 */
00657 #define RCC_CRS_SYNC_DIV32       LL_CRS_SYNC_DIV_32                       /*!< Synchro Signal divided by 32 */
00658 #define RCC_CRS_SYNC_DIV64       LL_CRS_SYNC_DIV_64                       /*!< Synchro Signal divided by 64 */
00659 #define RCC_CRS_SYNC_DIV128      LL_CRS_SYNC_DIV_128                      /*!< Synchro Signal divided by 128 */
00660 /**
00661   * @}
00662   */
00663
00664 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
00665   * @{
00666   */
00667 #define RCC_CRS_SYNC_POLARITY_RISING   LL_CRS_SYNC_POLARITY_RISING        /*!< Synchro Active on rising edge (default) */
00668 #define RCC_CRS_SYNC_POLARITY_FALLING  LL_CRS_SYNC_POLARITY_FALLING       /*!< Synchro Active on falling edge */
00669 /**
00670   * @}
00671   */
00672
00673 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
00674   * @{
00675   */
00676 #define RCC_CRS_RELOADVALUE_DEFAULT    LL_CRS_RELOADVALUE_DEFAULT /*!< The reset value of the RELOAD field corresponds
00677                                                                        to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
00678 /**
00679   * @}
00680   */
00681
00682 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
00683   * @{
00684   */
00685 #define RCC_CRS_ERRORLIMIT_DEFAULT     LL_CRS_ERRORLIMIT_DEFAULT /*!< Default Frequency error limit */
00686 /**
00687   * @}
00688   */
00689
00690 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
00691   * @{
00692   */
00693 #define RCC_CRS_HSI48CALIBRATION_DEFAULT LL_CRS_HSI48CALIBRATION_DEFAULT /*!< The default value is 32, which corresponds to the middle of the trimming interval.
00694                                                                               The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
00695                                                                               corresponds to a higher output frequency */
00696 /**
00697   * @}
00698   */
00699
00700 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
00701   * @{
00702   */
00703 #define RCC_CRS_FREQERRORDIR_UP        LL_CRS_FREQ_ERROR_DIR_UP   /*!< Upcounting direction, the actual frequency is above the target */
00704 #define RCC_CRS_FREQERRORDIR_DOWN      LL_CRS_FREQ_ERROR_DIR_DOWN /*!< Downcounting direction, the actual frequency is below the target */
00705 /**
00706   * @}
00707   */
00708
00709 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
00710   * @{
00711   */
00712 #define RCC_CRS_IT_SYNCOK              LL_CRS_CR_SYNCOKIE       /*!< SYNC event OK */
00713 #define RCC_CRS_IT_SYNCWARN            LL_CRS_CR_SYNCWARNIE     /*!< SYNC warning */
00714 #define RCC_CRS_IT_ERR                 LL_CRS_CR_ERRIE          /*!< Error */
00715 #define RCC_CRS_IT_ESYNC               LL_CRS_CR_ESYNCIE        /*!< Expected SYNC */
00716 #define RCC_CRS_IT_SYNCERR             LL_CRS_CR_ERRIE          /*!< SYNC error */
00717 #define RCC_CRS_IT_SYNCMISS            LL_CRS_CR_ERRIE          /*!< SYNC missed */
00718 #define RCC_CRS_IT_TRIMOVF             LL_CRS_CR_ERRIE          /*!< Trimming overflow or underflow */
00719
00720 /**
00721   * @}
00722   */
00723
00724 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
00725   * @{
00726   */
00727 #define RCC_CRS_FLAG_SYNCOK            LL_CRS_ISR_SYNCOKF       /*!< SYNC event OK flag     */
00728 #define RCC_CRS_FLAG_SYNCWARN          LL_CRS_ISR_SYNCWARNF     /*!< SYNC warning flag      */
00729 #define RCC_CRS_FLAG_ERR               LL_CRS_ISR_ERRF          /*!< Error flag        */
00730 #define RCC_CRS_FLAG_ESYNC             LL_CRS_ISR_ESYNCF        /*!< Expected SYNC flag     */
00731 #define RCC_CRS_FLAG_SYNCERR           LL_CRS_ISR_SYNCERR       /*!< SYNC error */
00732 #define RCC_CRS_FLAG_SYNCMISS          LL_CRS_ISR_SYNCMISS      /*!< SYNC missed*/
00733 #define RCC_CRS_FLAG_TRIMOVF           LL_CRS_ISR_TRIMOVF       /*!< Trimming overflow or underflow */
00734
00735 /**
00736   * @}
00737   */
00738 #endif
00739
00740 /**
00741   * @}
00742   */
00743
00744 /* Exported macros -----------------------------------------------------------*/
00745 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
00746  * @{
00747  */
00748
00749 /*================================================================================================================*/
00750
00751 #if defined(SAI1)
00752 /**
00753   * @brief  Macro to configure the PLLSAI1 clock multiplication and division factors.
00754   *
00755   * @note   This function must be used only when the PLLSAI1 is disabled.
00756   * @note   PLLSAI1 clock source is common with the main PLL (configured through
00757   *         @ref __HAL_RCC_PLL_CONFIG() macro)
00758   *
00759   * @param  __PLLN__ specifies the multiplication factor for PLLSAI1 VCO output clock.
00760   *         This parameter must be a number between 6 and 127.
00761   * @note   You have to set the PLLN parameter correctly to ensure that the VCO
00762   *         output frequency is between 96 and 344 MHz.
00763   *         PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLN
00764   *
00765   * @param  __PLLP__ specifies the division factor for SAI clock.
00766   *         This parameter must be a number in the range (RCC_PLLP_DIV2 to RCC_PLLP_DIV32).
00767   *         SAI clock frequency = f(PLLSAI1) / PLLP
00768   *
00769   * @param  __PLLQ__ specifies the division factor for USB/RNG clock.
00770   *         This parameter must be in the range (RCC_PLLQ_DIV2 to RCC_PLLQ_DIV8).
00771   *         USB/RNG clock frequency = f(PLLSAI1) / PLLQ
00772   *
00773   * @param  __PLLR__ specifies the division factor for SAR ADC clock.
00774   *         This parameter must be in the range (RCC_PLLR_DIV2 to RCC_PLLR_DIV8).
00775   *         ADC clock frequency = f(PLLSAI1) / PLLR
00776   *
00777   * @retval None
00778   */
00779 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLN__, __PLLP__, __PLLQ__, __PLLR__) \
00780                   MODIFY_REG(RCC->PLLSAI1CFGR, \
00781                              (RCC_PLLSAI1CFGR_PLLN | RCC_PLLSAI1CFGR_PLLP | RCC_PLLSAI1CFGR_PLLQ | RCC_PLLSAI1CFGR_PLLR), \
00782                              (((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | (__PLLP__) | (__PLLQ__) | (__PLLR__)))
00783
00784 /**
00785   * @brief  Macro to configure the PLLSAI1 clock multiplication factor N.
00786   *
00787   * @note   This function must be used only when the PLLSAI1 is disabled.
00788   * @note   PLLSAI1 clock source is common with the main PLL (configured through
00789   *         @ref __HAL_RCC_PLL_CONFIG() macro)
00790   *
00791   * @param  __PLLN__ specifies the multiplication factor for PLLSAI1 VCO output clock.
00792   *          This parameter must be a number between Min_Data=6 and Max_Data=127.
00793   * @note   You have to set the PLLN parameter correctly to ensure that the VCO
00794   *         output frequency is between 96 and 344 MHz.
00795   *         Use to set PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLN
00796   *
00797   * @retval None
00798   */
00799 #define __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLN__) \
00800                   MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLN, (__PLLN__) << RCC_PLLSAI1CFGR_PLLN_Pos)
00801
00802
00803 /** @brief  Macro to configure the PLLSAI1 clock division factor P.
00804   *
00805   * @note   This function must be used only when the PLLSAI1 is disabled.
00806   * @note   PLLSAI1 clock source is common with the main PLL (configured through
00807   *         @ref __HAL_RCC_PLL_CONFIG() macro)
00808   *
00809   * @param  __PLLP__  specifies the division factor for SAI clock.
00810   *                   This parameter must be a number in range (RCC_PLLP_DIV2 to RCC_PLLP_DIV32).
00811   *                   Use to set SAI clock frequency = f(PLLSAI1) / PLLP
00812   *
00813   * @retval None
00814   */
00815 #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLP__) \
00816                   MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLP, (__PLLP__))
00817
00818
00819 /** @brief  Macro to configure the PLLSAI1 clock division factor Q.
00820   *
00821   * @note   This function must be used only when the PLLSAI1 is disabled.
00822   * @note   PLLSAI1 clock source is common with the main PLL (configured through
00823   *         @ref __HAL_RCC_PLL_CONFIG() macro)
00824   *
00825   * @param  __PLLQ__  specifies the division factor for USB clock.
00826   *                   This parameter must be in the range (RCC_PLLQ_DIV2 to RCC_PLLQ_DIV8).
00827   *                   Use to set USB clock frequency = f(PLLSAI1) / PLLQ
00828   *
00829   * @retval None
00830   */
00831 #define __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLQ__) \
00832                   MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLQ, (__PLLQ__))
00833
00834 /** @brief  Macro to configure the PLLSAI1 clock division factor R.
00835   *
00836   * @note   This function must be used only when the PLLSAI1 is disabled.
00837   * @note   PLLSAI1 clock source is common with the main PLL (configured through
00838   *         @ref __HAL_RCC_PLL_CONFIG() macro)
00839   *
00840   * @param  __PLLR__  specifies the division factor for ADC clock.
00841   *                   This parameter must be in the range (RCC_PLLR_DIV2 to RCC_PLLR_DIV8).
00842   *                   Use to set ADC clock frequency = f(PLLSAI1) / PLLR
00843   *
00844   * @retval None
00845   */
00846 #define __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLR__) \
00847                   MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLR, (__PLLR__))
00848
00849 /**
00850   * @brief  Macros to enable the PLLSAI1.
00851   * @note   The PLLSAI1 is disabled by hardware when entering STOP and STANDBY modes.
00852   * @retval None
00853   */
00854 #define __HAL_RCC_PLLSAI1_ENABLE()  LL_RCC_PLLSAI1_Enable()
00855
00856 /**
00857   * @brief  Macros to disable the PLLSAI1.
00858   * @note   The PLLSAI1 is disabled by hardware when entering STOP and STANDBY modes.
00859   * @retval None
00860   */
00861 #define __HAL_RCC_PLLSAI1_DISABLE() LL_RCC_PLLSAI1_Disable()
00862
00863 /**
00864   * @brief  Macros to enable each clock output (RCC_PLLSAI1_SAI1CLK, RCC_PLLSAI1_USBCLK and RCC_PLLSAI1_ADCCLK).
00865   * @note   Enabling and disabling those clocks can be done without the need to stop the PLL.
00866   *         This is mainly used to save Power.
00867   * @param  __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output.
00868   *         This parameter can be one or a combination of the following values:
00869   *            @arg @ref RCC_PLLSAI1_SAI1CLK  This clock is used to generate an accurate clock to achieve high-quality audio performance on SAI interface
00870   *            @arg @ref RCC_PLLSAI1_ADCCLK  Clock used to clock ADC peripheral
00871   *            @arg @ref RCC_PLLSAI1_USBCLK  This clock is used to generate the clock for the USB Device (48 MHz)
00872   *
00873   * @retval None
00874   */
00875 #define __HAL_RCC_PLLSAI1CLKOUT_ENABLE(__PLLSAI1_CLOCKOUT__)   SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
00876
00877 /**
00878   * @brief  Macros to disable each clock output (RCC_PLLSAI1_SAI1CLK, RCC_PLLSAI1_USBCLK and RCC_PLLSAI1_ADCCLK).
00879   * @note   Enabling and disabling those clocks can be done without the need to stop the PLL.
00880   *         This is mainly used to save Power.
00881   * @param  __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output.
00882   *         This parameter can be one or a combination of the following values:
00883   *            @arg @ref RCC_PLLSAI1_SAI1CLK  This clock is used to generate an accurate clock to achieve high-quality audio performance on SAI interface
00884   *            @arg @ref RCC_PLLSAI1_ADCCLK  Clock used to clock ADC peripheral
00885   *            @arg @ref RCC_PLLSAI1_USBCLK  This clock is used to generate the clock for the USB Device (48 MHz)
00886   *
00887   * @retval None
00888   */
00889 #define __HAL_RCC_PLLSAI1CLKOUT_DISABLE(__PLLSAI1_CLOCKOUT__)  CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
00890
00891 /**
00892   * @brief  Macro to get clock output enable status (RCC_PLLSAI1_SAI1CLK, RCC_PLLSAI1_USBCLK and RCC_PLLSAI1_ADCCLK).
00893   * @param  __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output.
00894   *         This parameter can be one or a combination of the following values:
00895   *            @arg @ref RCC_PLLSAI1_SAI1CLK  This clock is used to generate an accurate clock to achieve high-quality audio performance on SAI interface
00896   *            @arg @ref RCC_PLLSAI1_ADCCLK  Clock used to clock ADC peripheral
00897   *            @arg @ref RCC_PLLSAI1_USBCLK  This clock is used to generate the clock for the USB Device (48 MHz)
00898   * @retval SET / RESET
00899   */
00900 #define __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__)  READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
00901
00902
00903 /**
00904   * @brief  Macro to configure the SAI1 clock source.
00905   * @param  __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived
00906   *         from the PLLSAI1, system PLL, HSI or external clock (through a dedicated pin).
00907   *          This parameter can be one of the following values:
00908   *             @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1    SAI1 clock = PLLSAI1 "P" clock
00909   *             @arg @ref RCC_SAI1CLKSOURCE_PLL        SAI1 clock  = PLL "P" clock
00910   *             @arg @ref RCC_SAI1CLKSOURCE_HSI        SAI1 clock  = HSI clock
00911   *             @arg @ref RCC_SAI1CLKSOURCE_PIN        SAI1 clock = External Clock (SAI1_EXTCLK)
00912   *
00913   * @retval None
00914   */
00915 #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)  LL_RCC_SetSAIClockSource(__SAI1_CLKSOURCE__)
00916
00917
00918 /** @brief  Macro to get the SAI1 clock source.
00919   * @retval The clock source can be one of the following values:
00920   *             @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1     SAI1 clock = PLLSAI1 "P" clock
00921   *             @arg @ref RCC_SAI1CLKSOURCE_PLL         SAI1 clock  = PLL "P" clock
00922   *             @arg @ref RCC_SAI1CLKSOURCE_HSI         SAI1 clock  = HSI clock
00923   *             @arg @ref RCC_SAI1CLKSOURCE_PIN         SAI1 clock = External Clock (SAI1_EXTCLK)
00924   *
00925   * @retval None
00926   */
00927 #define __HAL_RCC_GET_SAI1_SOURCE()  LL_RCC_GetSAIClockSource(LL_RCC_SAI1_CLKSOURCE)
00928 #endif
00929
00930 /** @brief  Macro to configure the I2C1 clock (I2C1CLK).
00931   *
00932   * @param  __I2C1_CLKSOURCE__ specifies the I2C1 clock source.
00933   *          This parameter can be one of the following values:
00934   *            @arg @ref RCC_I2C1CLKSOURCE_PCLK1   PCLK1 selected as I2C1 clock
00935   *            @arg @ref RCC_I2C1CLKSOURCE_HSI     HSI selected as I2C1 clock
00936   *            @arg @ref RCC_I2C1CLKSOURCE_SYSCLK  System Clock selected as I2C1 clock
00937   * @retval None
00938   */
00939 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) LL_RCC_SetI2CClockSource(__I2C1_CLKSOURCE__)
00940
00941 /** @brief  Macro to get the I2C1 clock source.
00942   * @retval The clock source can be one of the following values:
00943   *            @arg @ref RCC_I2C1CLKSOURCE_PCLK1   PCLK1 selected as I2C1 clock
00944   *            @arg @ref RCC_I2C1CLKSOURCE_HSI     HSI selected as I2C1 clock
00945   *            @arg @ref RCC_I2C1CLKSOURCE_SYSCLK  System Clock selected as I2C1 clock
00946   */
00947 #define __HAL_RCC_GET_I2C1_SOURCE() LL_RCC_GetI2CClockSource(LL_RCC_I2C1_CLKSOURCE)
00948
00949 #if defined(I2C3)
00950 /** @brief  Macro to configure the I2C3 clock (I2C3CLK).
00951   *
00952   * @param  __I2C3_CLKSOURCE__ specifies the I2C3 clock source.
00953   *          This parameter can be one of the following values:
00954   *            @arg @ref RCC_I2C3CLKSOURCE_PCLK1   PCLK1 selected as I2C3 clock
00955   *            @arg @ref RCC_I2C3CLKSOURCE_HSI     HSI selected as I2C3 clock
00956   *            @arg @ref RCC_I2C3CLKSOURCE_SYSCLK  System Clock selected as I2C3 clock
00957   * @retval None
00958   */
00959 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) LL_RCC_SetI2CClockSource(__I2C3_CLKSOURCE__)
00960
00961 /** @brief  Macro to get the I2C3 clock source.
00962   * @retval The clock source can be one of the following values:
00963   *            @arg @ref RCC_I2C3CLKSOURCE_PCLK1   PCLK1 selected as I2C3 clock
00964   *            @arg @ref RCC_I2C3CLKSOURCE_HSI     HSI selected as I2C3 clock
00965   *            @arg @ref RCC_I2C3CLKSOURCE_SYSCLK  System Clock selected as I2C3 clock
00966   */
00967 #define __HAL_RCC_GET_I2C3_SOURCE() LL_RCC_GetI2CClockSource(LL_RCC_I2C3_CLKSOURCE)
00968 #endif
00969
00970 /** @brief  Macro to configure the USART1 clock (USART1CLK).
00971   *
00972   * @param  __USART1_CLKSOURCE__ specifies the USART1 clock source.
00973   *          This parameter can be one of the following values:
00974   *            @arg @ref RCC_USART1CLKSOURCE_PCLK2   PCLK2 selected as USART1 clock
00975   *            @arg @ref RCC_USART1CLKSOURCE_HSI     HSI selected as USART1 clock
00976   *            @arg @ref RCC_USART1CLKSOURCE_SYSCLK  System Clock selected as USART1 clock
00977   *            @arg @ref RCC_USART1CLKSOURCE_LSE     LSE selected as USART1 clock
00978   * @retval None
00979   */
00980 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) LL_RCC_SetUSARTClockSource(__USART1_CLKSOURCE__)
00981
00982 /** @brief  Macro to get the USART1 clock source.
00983   * @retval The clock source can be one of the following values:
00984   *            @arg @ref RCC_USART1CLKSOURCE_PCLK2   PCLK2 selected as USART1 clock
00985   *            @arg @ref RCC_USART1CLKSOURCE_HSI     HSI selected as USART1 clock
00986   *            @arg @ref RCC_USART1CLKSOURCE_SYSCLK  System Clock selected as USART1 clock
00987   *            @arg @ref RCC_USART1CLKSOURCE_LSE     LSE selected as USART1 clock
00988   */
00989 #define __HAL_RCC_GET_USART1_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_USART1_CLKSOURCE)
00990
00991 #if defined(LPUART1)
00992 /** @brief  Macro to configure the LPUART clock (LPUARTCLK).
00993   *
00994   * @param  __LPUART_CLKSOURCE__ specifies the LPUART clock source.
00995   *          This parameter can be one of the following values:
00996   *            @arg @ref RCC_LPUART1CLKSOURCE_PCLK1   PCLK1 selected as LPUART1 clock
00997   *            @arg @ref RCC_LPUART1CLKSOURCE_HSI     HSI selected as LPUART1 clock
00998   *            @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK  System Clock selected as LPUART1 clock
00999   *            @arg @ref RCC_LPUART1CLKSOURCE_LSE     LSE selected as LPUART1 clock
01000   * @retval None
01001   */
01002 #define __HAL_RCC_LPUART1_CONFIG(__LPUART_CLKSOURCE__) LL_RCC_SetLPUARTClockSource(__LPUART_CLKSOURCE__)
01003
01004 /** @brief  Macro to get the LPUART clock source.
01005   * @retval The clock source can be one of the following values:
01006   *            @arg @ref RCC_LPUART1CLKSOURCE_PCLK1   PCLK1 selected as LPUART1 clock
01007   *            @arg @ref RCC_LPUART1CLKSOURCE_HSI     HSI selected as LPUART1 clock
01008   *            @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK  System Clock selected as LPUART1 clock
01009   *            @arg @ref RCC_LPUART1CLKSOURCE_LSE     LSE selected as LPUART1 clock
01010   */
01011 #define __HAL_RCC_GET_LPUART1_SOURCE() LL_RCC_GetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE)
01012 #endif
01013
01014 /** @brief  Macro to configure the LPTIM1 clock (LPTIM1CLK).
01015   *
01016   * @param  __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source.
01017   *          This parameter can be one of the following values:
01018   *            @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1  PCLK selected as LPTIM1 clock
01019   *            @arg @ref RCC_LPTIM1CLKSOURCE_LSI   HSI selected as LPTIM1 clock
01020   *            @arg @ref RCC_LPTIM1CLKSOURCE_HSI   LSI selected as LPTIM1 clock
01021   *            @arg @ref RCC_LPTIM1CLKSOURCE_LSE   LSE selected as LPTIM1 clock
01022   * @retval None
01023   */
01024 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) LL_RCC_SetLPTIMClockSource(__LPTIM1_CLKSOURCE__)
01025
01026 /** @brief  Macro to get the LPTIM1 clock source.
01027   * @retval The clock source can be one of the following values:
01028   *            @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1  PCLK selected as LPTIM1 clock
01029   *            @arg @ref RCC_LPTIM1CLKSOURCE_LSI   HSI selected as LPTIM1 clock
01030   *            @arg @ref RCC_LPTIM1CLKSOURCE_HSI   System Clock selected as LPTIM1 clock
01031   *            @arg @ref RCC_LPTIM1CLKSOURCE_LSE   LSE selected as LPTIM1 clock
01032   */
01033 #define __HAL_RCC_GET_LPTIM1_SOURCE() LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE)
01034
01035 /** @brief  Macro to configure the LPTIM2 clock (LPTIM2CLK).
01036   *
01037   * @param  __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source.
01038   *          This parameter can be one of the following values:
01039   *            @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1  PCLK selected as LPTIM2 clock
01040   *            @arg @ref RCC_LPTIM2CLKSOURCE_LSI   HSI selected as LPTIM2 clock
01041   *            @arg @ref RCC_LPTIM2CLKSOURCE_HSI   LSI selected as LPTIM2 clock
01042   *            @arg @ref RCC_LPTIM2CLKSOURCE_LSE   LSE selected as LPTIM2 clock
01043   * @retval None
01044   */
01045 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) LL_RCC_SetLPTIMClockSource(__LPTIM2_CLKSOURCE__)
01046
01047 /** @brief  Macro to get the LPTIM2 clock source.
01048   * @retval The clock source can be one of the following values:
01049   *            @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1  PCLK selected as LPTIM2 clock
01050   *            @arg @ref RCC_LPTIM2CLKSOURCE_LSI   HSI selected as LPTIM2 clock
01051   *            @arg @ref RCC_LPTIM2CLKSOURCE_HSI   System Clock selected as LPTIM2 clock
01052   *            @arg @ref RCC_LPTIM2CLKSOURCE_LSE   LSE selected as LPTIM2 clock
01053   */
01054 #define __HAL_RCC_GET_LPTIM2_SOURCE() LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE)
01055
01056
01057 /** @brief  Macro to configure the RNG clock.
01058   *
01059   * @note  USB and RNG peripherals share the same 48MHz clock source.
01060   *
01061   * @param  __RNG_CLKSOURCE__ specifies the RNG clock source.
01062   *         This parameter can be one of the following values:
01063   *            @arg @ref RCC_RNGCLKSOURCE_HSI48         HSI48 clock divided by 3  selected as RNG clock
01064   *            @arg @ref RCC_RNGCLKSOURCE_PLL           PLL "Q" clock divided by 3  selected as RNG clock
01065   *            @arg @ref RCC_RNGCLKSOURCE_MSI           MSI clock divided by 3 selected as RNG clock
01066   *            @arg @ref RCC_RNGCLKSOURCE_CLK48         CLK48 divided by 3 selected as RNG Clock  (default HSI48)
01067   *            @arg @ref RCC_RNGCLKSOURCE_LSI           LSI clock selected as RNG clock
01068   *            @arg @ref RCC_RNGCLKSOURCE_LSE           LSE clock selected as RNG clock
01069   * @retval None
01070   */
01071 #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__)             \
01072   do {                                                      \
01073     if (((__RNG_CLKSOURCE__) == RCC_RNGCLKSOURCE_LSI)       \
01074      || ((__RNG_CLKSOURCE__) == RCC_RNGCLKSOURCE_LSE)       \
01075      || ((__RNG_CLKSOURCE__) == RCC_RNGCLKSOURCE_CLK48))    \
01076     {                                                       \
01077      LL_RCC_SetRNGClockSource((__RNG_CLKSOURCE__));         \
01078     }                                                       \
01079     else                                                    \
01080     {                                                       \
01081       uint32_t tmp = (__RNG_CLKSOURCE__) &(~CLK48_MASK);   \
01082       LL_RCC_SetRNGClockSource(RCC_RNGCLKSOURCE_CLK48);     \
01083       LL_RCC_SetCLK48ClockSource(tmp);                      \
01084     }                                                       \
01085   } while(0U)
01086
01087 /** @brief  Macro to get the direct RNG clock.
01088   * @note  @ref HAL_RCCEx_GetRngCLKSource can also be called to get direct
01089   *        of indirect (48 MHz clock source) RNG clock source.
01090   * @retval The RNG clock source can be one of the following values:
01091   *            @arg @ref RCC_RNGCLKSOURCE_CLK48    CLK48 divided by 3 selected as RNG Clock
01092   *            @arg @ref RCC_RNGCLKSOURCE_LSI      LSI selected as RNG clock
01093   *            @arg @ref RCC_RNGCLKSOURCE_LSE      LSE selected as RNG clock
01094   */
01095 #define __HAL_RCC_GET_RNG_SOURCE() LL_RCC_GetRNGClockSource(LL_RCC_RNG_CLKSOURCE)
01096
01097 /** @brief  Macro to configure the USB clock (USBCLK).
01098   *
01099   * @note  USB and RNG peripherals share the same 48MHz clock source.
01100   *
01101   * @param  __USB_CLKSOURCE__ specifies the USB clock source.
01102   *         This parameter can be one of the following values:
01103   *            @arg @ref RCC_USBCLKSOURCE_HSI48    HSI48 selected as 48MHz clock for devices with HSI48
01104   *            @arg @ref RCC_USBCLKSOURCE_MSI      MSI selected as USB clock
01105   *            @arg @ref RCC_USBCLKSOURCE_PLLSAI1  PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock
01106   *            @arg @ref RCC_USBCLKSOURCE_PLL      PLL "Q" clock (PLL48M1CLK) selected as USB clock
01107   * @retval None
01108   */
01109 #define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__)  LL_RCC_SetUSBClockSource(__USB_CLKSOURCE__)
01110
01111 /** @brief  Macro to get the USB clock source.
01112   * @retval The clock source can be one of the following values:
01113   *            @arg @ref RCC_USBCLKSOURCE_HSI48    HSI48 selected as 48MHz clock for devices with HSI48
01114   *            @arg @ref RCC_USBCLKSOURCE_MSI      MSI selected as USB clock
01115   *            @arg @ref RCC_USBCLKSOURCE_PLLSAI1  PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock
01116   *            @arg @ref RCC_USBCLKSOURCE_PLL      PLL "Q" clock (PLL48M1CLK) selected as USB clock
01117   */
01118 #define __HAL_RCC_GET_USB_SOURCE()  LL_RCC_GetUSBClockSource(LL_RCC_USB_CLKSOURCE)
01119
01120 /** @brief  Macro to configure the ADC interface clock.
01121   * @param  __ADC_CLKSOURCE__ specifies the ADC digital interface clock source.
01122   *         This parameter can be one of the following values:
01123   *            @arg @ref RCC_ADCCLKSOURCE_NONE    No clock selected as ADC clock
01124   *            @arg @ref RCC_ADCCLKSOURCE_PLLSAI1  PLLSAI1 Clock selected as ADC clock
01125   *            @arg @ref RCC_ADCCLKSOURCE_PLL  PLL Clock selected as ADC clock
01126   *            @arg @ref RCC_ADCCLKSOURCE_SYSCLK  System Clock selected as ADC clock
01127   * @retval None
01128   */
01129 #define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__)  LL_RCC_SetADCClockSource(__ADC_CLKSOURCE__)
01130
01131 /** @brief  Macro to get the ADC clock source.
01132   * @retval The clock source can be one of the following values:
01133   *            @arg @ref RCC_ADCCLKSOURCE_NONE    No clock selected as ADC clock
01134   *            @arg @ref RCC_ADCCLKSOURCE_PLLSAI1  PLLSAI1 Clock selected as ADC clock
01135   *            @arg @ref RCC_ADCCLKSOURCE_PLL  PLL Clock selected as ADC clock
01136   *            @arg @ref RCC_ADCCLKSOURCE_SYSCLK  System Clock selected as ADC clock
01137   */
01138 #define __HAL_RCC_GET_ADC_SOURCE() LL_RCC_GetADCClockSource(LL_RCC_ADC_CLKSOURCE)
01139
01140 /** @brief  Macro to configure the RFWKP interface clock.
01141   * @param  __RFWKP_CLKSOURCE__ specifies the RFWKP digital interface clock source.
01142   *         This parameter can be one of the following values:
01143   *            @arg @ref RCC_RFWKPCLKSOURCE_NONE         No clock selected as RFWKP clock
01144   *            @arg @ref RCC_RFWKPCLKSOURCE_LSE          LSE Clock selected as RFWKP clock
01145   *            @arg @ref RCC_RFWKPCLKSOURCE_LSI          LSI Clock selected as RFWKP clock
01146   *            @arg @ref RCC_RFWKPCLKSOURCE_HSE_DIV1024  HSE div1024 Clock selected as RFWKP clock
01147   * @retval None
01148   */
01149 #define __HAL_RCC_RFWAKEUP_CONFIG(__RFWKP_CLKSOURCE__)  LL_RCC_SetRFWKPClockSource(__RFWKP_CLKSOURCE__)
01150
01151 /** @brief  Macro to get the RFWKP clock source.
01152   *         This parameter can be one of the following values:
01153   *            @arg @ref RCC_RFWKPCLKSOURCE_NONE         No clock selected as RFWKP clock
01154   *            @arg @ref RCC_RFWKPCLKSOURCE_LSE          LSE Clock selected as RFWKP clock
01155   *            @arg @ref RCC_RFWKPCLKSOURCE_LSI          LSI Clock selected as RFWKP clock
01156   *            @arg @ref RCC_RFWKPCLKSOURCE_HSE_DIV1024  HSE div1024 Clock selected as RFWKP clock
01157   */
01158 #define __HAL_RCC_GET_RFWAKEUP_SOURCE()  LL_RCC_GetRFWKPClockSource()
01159
01160 #if defined(RCC_SMPS_SUPPORT)
01161 /** @brief  Macro to configure the SMPS clock division factor.
01162   *
01163   * @param  __SMPSCLKDIV__ specifies the division factor for SMPS clock.
01164   *         This parameter can be one of the following values:
01165   *            @arg @ref RCC_SMPSCLKDIV_RANGE0           1st divider factor value
01166   *            @arg @ref RCC_SMPSCLKDIV_RANGE1           2nd divider factor value
01167   *            @arg @ref RCC_SMPSCLKDIV_RANGE2           3th divider factor value
01168   *            @arg @ref RCC_SMPSCLKDIV_RANGE3           4th divider factor value
01169   *
01170   * @note divider value predefined by HW depending of SMPS clock source
01171   *
01172   * @retval None
01173   */
01174 #define __HAL_RCC_SMPS_DIV_CONFIG(__SMPSCLKDIV__) LL_RCC_SetSMPSPrescaler(__SMPSCLKDIV__)
01175
01176 /** @brief  Macro to get the SMPS clock division factor.
01177   *
01178   *         This parameter can be one of the following values:
01179   *            @arg @ref RCC_SMPSCLKDIV_RANGE0           1st divider factor value
01180   *            @arg @ref RCC_SMPSCLKDIV_RANGE1           2nd divider factor value
01181   *            @arg @ref RCC_SMPSCLKDIV_RANGE2           3th divider factor value
01182   *            @arg @ref RCC_SMPSCLKDIV_RANGE3           4th divider factor value
01183   *
01184   */
01185 #define __HAL_RCC_GET_SMPS_DIV() LL_RCC_GetSMPSPrescaler()
01186
01187 /** @brief  Macro to configure the SMPS interface clock.
01188   * @param  __SMPS_CLKSOURCE__ specifies the SMPS digital interface clock source.
01189   *         This parameter can be one of the following values:
01190   *            @arg @ref RCC_SMPSCLKSOURCE_HSI          HSI clock selected as SMPS clock
01191   *            @arg @ref RCC_SMPSCLKSOURCE_MSI          MSI Clock selected as SMPS clock
01192   *            @arg @ref RCC_SMPSCLKSOURCE_HSE          HSE Clock selected as SMPS clock
01193   * @retval None
01194   */
01195
01196 #define __HAL_RCC_SMPS_CONFIG(__SMPS_CLKSOURCE__) LL_RCC_SetSMPSClockSource(__SMPS_CLKSOURCE__)
01197
01198 /** @brief  Macro to get the SMPS clock source.
01199   *         This parameter can be one of the following values:
01200   *            @arg @ref RCC_SMPSCLKSOURCE_HSI          HSI clock selected as SMPS clock
01201   *            @arg @ref RCC_SMPSCLKSOURCE_MSI          MSI Clock selected as SMPS clock
01202   *            @arg @ref RCC_SMPSCLKSOURCE_HSE          HSE Clock selected as SMPS clock
01203   */
01204 #define __HAL_RCC_GET_SMPS_SOURCE() LL_RCC_GetSMPSClockSelection()
01205
01206 /** @brief  Macro to get the SMPS clock source.
01207   *         This parameter can be one of the following values:
01208   *            @arg @ref RCC_SMPSCLKSOURCE_STATUS_HSI   HSI clock selected as SMPS clock
01209   *            @arg @ref RCC_SMPSCLKSOURCE_STATUS_MSI   MSI Clock selected as SMPS clock
01210   *            @arg @ref RCC_SMPSCLKSOURCE_STATUS_HSE   HSE Clock selected as SMPS clock
01211   */
01212 #define __HAL_RCC_GET_SMPS_SOURCE_STATUS() LL_RCC_GetSMPSClockSource()
01213 #endif
01214
01215 /** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management
01216   * @brief macros to manage the specified RCC Flags and interrupts.
01217   * @{
01218   */
01219
01220 #if defined(SAI1)
01221 /** @brief Enable PLLSAI1RDY interrupt.
01222   * @retval None
01223   */
01224 #define __HAL_RCC_PLLSAI1_ENABLE_IT() LL_RCC_EnableIT_PLLSAI1RDY()
01225
01226 /** @brief Disable PLLSAI1RDY interrupt.
01227   * @retval None
01228   */
01229 #define __HAL_RCC_PLLSAI1_DISABLE_IT() LL_RCC_DisableIT_PLLSAI1RDY()
01230
01231 /** @brief Clear the PLLSAI1RDY interrupt pending bit.
01232   * @retval None
01233   */
01234 #define __HAL_RCC_PLLSAI1_CLEAR_IT() LL_RCC_ClearFlag_PLLSAI1RDY()
01235
01236 /** @brief Check whether PLLSAI1RDY interrupt has occurred or not.
01237   * @retval TRUE or FALSE.
01238   */
01239 #define __HAL_RCC_PLLSAI1_GET_IT_SOURCE() LL_RCC_IsActiveFlag_PLLSAI1RDY()
01240
01241 /** @brief  Check whether the PLLSAI1RDY flag is set or not.
01242   * @retval TRUE or FALSE.
01243   */
01244 #define __HAL_RCC_PLLSAI1_GET_FLAG()  LL_RCC_PLLSAI1_IsReady()
01245 #endif
01246
01247 /**
01248   * @brief Enable the RCC LSE CSS Extended Interrupt C1 Line.
01249   * @retval None
01250   */
01251 #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT()            LL_EXTI_EnableIT_0_31(RCC_EXTI_LINE_LSECSS)
01252
01253 /**
01254   * @brief Enable the RCC LSE CSS Extended Interrupt C2 Line.
01255   * @retval None
01256   */
01257 #define __HAL_C2_RCC_LSECSS_EXTI_ENABLE_IT()          LL_C2_EXTI_EnableIT_0_31(RCC_EXTI_LINE_LSECSS)
01258
01259 /**
01260   * @brief Disable the RCC LSE CSS Extended Interrupt C1 Line.
01261   * @retval None
01262   */
01263 #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT()           LL_EXTI_DisableIT_0_31(RCC_EXTI_LINE_LSECSS)
01264
01265 /**
01266   * @brief Disable the RCC LSE CSS Extended Interrupt C2 Line.
01267   * @retval None
01268   */
01269 #define __HAL_C2_RCC_LSECSS_EXTI_DISABLE_IT()        LL_C2_EXTI_DisableIT_0_31(RCC_EXTI_LINE_LSECSS)
01270
01271 /**
01272   * @brief Enable the RCC LSE CSS Event C1 Line.
01273   * @retval None.
01274   */
01275 #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT()         LL_EXTI_EnableEvent_0_31(RCC_EXTI_LINE_LSECSS)
01276
01277 /**
01278   * @brief Enable the RCC LSE CSS Event C2 Line.
01279   * @retval None.
01280   */
01281 #define __HAL_C2_RCC_LSECSS_EXTI_ENABLE_EVENT()      LL_C2_EXTI_EnableEvent_0_31(RCC_EXTI_LINE_LSECSS)
01282
01283 /**
01284   * @brief Disable the RCC LSE CSS Event C1 Line.
01285   * @retval None.
01286   */
01287 #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT()        LL_EXTI_DisableEvent_0_31(RCC_EXTI_LINE_LSECSS)
01288
01289 /**
01290   * @brief Disable the RCC LSE CSS Event C2 Line.
01291   * @retval None.
01292   */
01293 #define __HAL_C2_RCC_LSECSS_EXTI_DISABLE_EVENT()     LL_C2_EXTI_DisableEvent_0_31(RCC_EXTI_LINE_LSECSS)
01294
01295 /**
01296   * @brief  Enable the RCC LSE CSS Extended Interrupt Falling Trigger.
01297   * @retval None.
01298   */
01299 #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE()  LL_EXTI_EnableFallingTrig_0_31(RCC_EXTI_LINE_LSECSS)
01300
01301 /**
01302   * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
01303   * @retval None.
01304   */
01305 #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE()  LL_EXTI_DisableFallingTrig_0_31(RCC_EXTI_LINE_LSECSS)
01306
01307 /**
01308   * @brief  Enable the RCC LSE CSS Extended Interrupt Rising Trigger.
01309   * @retval None.
01310   */
01311 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE()   LL_EXTI_EnableRisingTrig_0_31(RCC_EXTI_LINE_LSECSS)
01312
01313 /**
01314   * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
01315   * @retval None.
01316   */
01317 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE()  LL_EXTI_DisableRisingTrig_0_31(RCC_EXTI_LINE_LSECSS)
01318
01319 /**
01320   * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
01321   * @retval None.
01322   */
01323 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE()  \
01324   do {                                                      \
01325     __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();             \
01326     __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE();            \
01327   } while(0)
01328
01329 /**
01330   * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
01331   * @retval None.
01332   */
01333 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE()  \
01334   do {                                                       \
01335     __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE();             \
01336     __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE();            \
01337   } while(0)
01338
01339 /**
01340   * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
01341   * @retval EXTI RCC LSE CSS Line Status.
01342   */
01343 #define __HAL_RCC_LSECSS_EXTI_GET_FLAG()       LL_EXTI_IsActiveFlag_0_31(RCC_EXTI_LINE_LSECSS)
01344
01345 /**
01346   * @brief Clear the RCC LSE CSS EXTI flag.
01347   * @retval None.
01348   */
01349 #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG()    LL_EXTI_ClearFlag_0_31(RCC_EXTI_LINE_LSECSS)
01350
01351 /**
01352   * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line.
01353   * @retval None.
01354   */
01355 #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT()  LL_EXTI_GenerateSWI_0_31(RCC_EXTI_LINE_LSECSS)
01356
01357 #if defined(CRS)
01358 /**
01359   * @brief  Enable the specified CRS interrupts.
01360   * @param  __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
01361   *          This parameter can be any combination of the following values:
01362   *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
01363   *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
01364   *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
01365   *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
01366   * @retval None
01367   */
01368 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__)   SET_BIT(CRS->CR, (__INTERRUPT__))
01369
01370 /**
01371   * @brief  Disable the specified CRS interrupts.
01372   * @param  __INTERRUPT__ specifies the CRS interrupt sources to be disabled.
01373   *          This parameter can be any combination of the following values:
01374   *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
01375   *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
01376   *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
01377   *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
01378   * @retval None
01379   */
01380 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__)  CLEAR_BIT(CRS->CR, (__INTERRUPT__))
01381
01382 /** @brief  Check whether the CRS interrupt has occurred or not.
01383   * @param  __INTERRUPT__ specifies the CRS interrupt source to check.
01384   *         This parameter can be one of the following values:
01385   *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
01386   *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
01387   *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
01388   *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
01389   * @retval The new state of __INTERRUPT__ (SET or RESET).
01390   */
01391 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__)  ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET)
01392
01393 /** @brief  Clear the CRS interrupt pending bits
01394   * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
01395   *         This parameter can be any combination of the following values:
01396   *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
01397   *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
01398   *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
01399   *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
01400   *              @arg @ref RCC_CRS_IT_TRIMOVF  Trimming overflow or underflow interrupt
01401   *              @arg @ref RCC_CRS_IT_SYNCERR  SYNC error interrupt
01402   *              @arg @ref RCC_CRS_IT_SYNCMISS  SYNC missed interrupt
01403   */
01404 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__)  do { \
01405                                                  if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \
01406                                                  { \
01407                                                    WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
01408                                                  } \
01409                                                  else \
01410                                                  { \
01411                                                    WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
01412                                                  } \
01413                                                } while(0)
01414
01415 /**
01416   * @brief  Check whether the specified CRS flag is set or not.
01417   * @param  __FLAG__ specifies the flag to check.
01418   *          This parameter can be one of the following values:
01419   *              @arg @ref RCC_CRS_FLAG_SYNCOK  SYNC event OK
01420   *              @arg @ref RCC_CRS_FLAG_SYNCWARN  SYNC warning
01421   *              @arg @ref RCC_CRS_FLAG_ERR  Error
01422   *              @arg @ref RCC_CRS_FLAG_ESYNC  Expected SYNC
01423   *              @arg @ref RCC_CRS_FLAG_TRIMOVF  Trimming overflow or underflow
01424   *              @arg @ref RCC_CRS_FLAG_SYNCERR  SYNC error
01425   *              @arg @ref RCC_CRS_FLAG_SYNCMISS  SYNC missed
01426   * @retval The new state of _FLAG_ (TRUE or FALSE).
01427   */
01428 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__)  (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
01429
01430 /**
01431   * @brief  Clear the CRS specified FLAG.
01432   * @param __FLAG__ specifies the flag to clear.
01433   *          This parameter can be one of the following values:
01434   *              @arg @ref RCC_CRS_FLAG_SYNCOK  SYNC event OK
01435   *              @arg @ref RCC_CRS_FLAG_SYNCWARN  SYNC warning
01436   *              @arg @ref RCC_CRS_FLAG_ERR  Error
01437   *              @arg @ref RCC_CRS_FLAG_ESYNC  Expected SYNC
01438   *              @arg @ref RCC_CRS_FLAG_TRIMOVF  Trimming overflow or underflow
01439   *              @arg @ref RCC_CRS_FLAG_SYNCERR  SYNC error
01440   *              @arg @ref RCC_CRS_FLAG_SYNCMISS  SYNC missed
01441   * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
01442   * @retval None
01443   */
01444 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__)     do { \
01445                                                  if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \
01446                                                  { \
01447                                                    WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
01448                                                  } \
01449                                                  else \
01450                                                  { \
01451                                                    WRITE_REG(CRS->ICR, (__FLAG__)); \
01452                                                  } \
01453                                                } while(0)
01454 #endif
01455 /**
01456   * @}
01457   */
01458
01459
01460 #if defined(CRS)
01461 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
01462   * @{
01463   */
01464 /**
01465   * @brief  Enable the oscillator clock for frequency error counter.
01466   * @note   when the CEN bit is set the CRS_CFGR register becomes write-protected.
01467   * @retval None
01468   */
01469 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE()  LL_CRS_EnableFreqErrorCounter()
01470
01471 /**
01472   * @brief  Disable the oscillator clock for frequency error counter.
01473   * @retval None
01474   */
01475 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() LL_CRS_DisableFreqErrorCounter()
01476
01477 /**
01478   * @brief  Enable the automatic hardware adjustement of TRIM bits.
01479   * @note   When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
01480   * @retval None
01481   */
01482 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE()     LL_CRS_EnableAutoTrimming()
01483
01484 /**
01485   * @brief  Enable or disable the automatic hardware adjustement of TRIM bits.
01486   * @retval None
01487   */
01488 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE()    LL_CRS_DisableAutoTrimming()
01489
01490 /**
01491   * @brief  Macro to calculate reload value to be set in CRS register according to target and sync frequencies
01492   * @note   The RELOAD value should be selected according to the ratio between the target frequency and the frequency
01493   *             of the synchronization source after prescaling. It is then decreased by one in order to
01494   *             reach the expected synchronization on the zero value. The formula is the following:
01495   *             RELOAD = (fTARGET / fSYNC) -1
01496   * @param  __FTARGET__ Target frequency (value in Hz)
01497   * @param  __FSYNC__ Synchronization signal frequency (value in Hz)
01498   * @retval None
01499   */
01500 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)  __LL_CRS_CALC_CALCULATE_RELOADVALUE((__FTARGET__),(__FSYNC__))
01501
01502 /**
01503   * @}
01504   */
01505 #endif
01506
01507 /**
01508   * @}
01509   */
01510
01511 /* Exported functions --------------------------------------------------------*/
01512 /** @addtogroup RCCEx_Exported_Functions
01513   * @{
01514   */
01515
01516 /** @addtogroup RCCEx_Exported_Functions_Group1
01517   * @{
01518   */
01519
01520 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
01521 void              HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
01522 uint32_t          HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
01523 uint32_t          HAL_RCCEx_GetRngCLKSource(void);
01524
01525 /**
01526   * @}
01527   */
01528
01529 /** @addtogroup RCCEx_Exported_Functions_Group2
01530   * @{
01531   */
01532
01533 #if defined(SAI1)
01534 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef  *PLLSAI1Init);
01535 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void);
01536 #endif
01537
01538 void              HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);
01539
01540 void              HAL_RCCEx_EnableLSECSS(void);
01541 void              HAL_RCCEx_DisableLSECSS(void);
01542 void              HAL_RCCEx_EnableLSECSS_IT(void);
01543 void              HAL_RCCEx_LSECSS_IRQHandler(void);
01544 void              HAL_RCCEx_LSECSS_Callback(void);
01545
01546 void              HAL_RCCEx_LSCOConfig(uint32_t RCC_LSCOx, uint32_t RCC_LSCOSource);
01547 void              HAL_RCCEx_EnableLSCO(uint32_t LSCOSource);
01548 void              HAL_RCCEx_DisableLSCO(void);
01549
01550 void              HAL_RCCEx_EnableMSIPLLMode(void);
01551 void              HAL_RCCEx_DisableMSIPLLMode(void);
01552
01553 HAL_StatusTypeDef   HAL_RCCEx_TrimOsc(uint32_t OscillatorType);
01554
01555 /**
01556   * @}
01557   */
01558
01559
01560 #if defined(CRS)
01561
01562 /** @addtogroup RCCEx_Exported_Functions_Group3
01563   * @{
01564   */
01565
01566 void              HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
01567 void              HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
01568 void              HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
01569 uint32_t          HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
01570 void              HAL_RCCEx_CRS_IRQHandler(void);
01571 void              HAL_RCCEx_CRS_SyncOkCallback(void);
01572 void              HAL_RCCEx_CRS_SyncWarnCallback(void);
01573 void              HAL_RCCEx_CRS_ExpectedSyncCallback(void);
01574 void              HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
01575
01576 /**
01577   * @}
01578   */
01579
01580 #endif
01581 /**
01582   * @}
01583   */
01584
01585 /**
01586   * @}
01587   */
01588
01589 /**
01590   * @}
01591   */
01592
01593 #ifdef __cplusplus
01594 }
01595 #endif
01596
01597 #endif /* STM32WBxx_HAL_RCC_EX_H */
01598
01599 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:35 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_rng.c Source File

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stm32wbxx_hal_rng.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_rng.c
00004   * @author  MCD Application Team
00005   * @brief   RNG HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Random Number Generator (RNG) peripheral:
00008   *           + Initialization and configuration functions
00009   *           + Peripheral Control functions
00010   *           + Peripheral State functions
00011   *
00012   @verbatim
00013   ==============================================================================
00014                      ##### How to use this driver #####
00015   ==============================================================================
00016   [..]
00017       The RNG HAL driver can be used as follows:
00018
00019       (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro
00020           in HAL_RNG_MspInit().
00021       (#) Activate the RNG peripheral using HAL_RNG_Init() function.
00022       (#) Wait until the 32 bit Random Number Generator contains a valid
00023           random data using (polling/interrupt) mode.
00024       (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.
00025
00026     ##### Callback registration #####
00027     ==================================
00028
00029     [..]
00030     The compilation define USE_HAL_RNG_REGISTER_CALLBACKS when set to 1
00031     allows the user to configure dynamically the driver callbacks.
00032
00033     [..]
00034     Use Function @ref HAL_RNG_RegisterCallback() to register a user callback.
00035     Function @ref HAL_RNG_RegisterCallback() allows to register following callbacks:
00036     (+) ErrorCallback             : RNG Error Callback.
00037     (+) MspInitCallback           : RNG MspInit.
00038     (+) MspDeInitCallback         : RNG MspDeInit.
00039     This function takes as parameters the HAL peripheral handle, the Callback ID
00040     and a pointer to the user callback function.
00041
00042     [..]
00043     Use function @ref HAL_RNG_UnRegisterCallback() to reset a callback to the default
00044     weak (surcharged) function.
00045     @ref HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00046     and the Callback ID.
00047     This function allows to reset following callbacks:
00048     (+) ErrorCallback             : RNG Error Callback.
00049     (+) MspInitCallback           : RNG MspInit.
00050     (+) MspDeInitCallback         : RNG MspDeInit.
00051
00052     [..]
00053     For specific callback ReadyDataCallback, use dedicated register callbacks:
00054     respectively @ref HAL_RNG_RegisterReadyDataCallback() , @ref HAL_RNG_UnRegisterReadyDataCallback().
00055
00056     [..]
00057     By default, after the @ref HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET
00058     all callbacks are set to the corresponding weak (surcharged) functions:
00059     example @ref HAL_RNG_ErrorCallback().
00060     Exception done for MspInit and MspDeInit functions that are respectively
00061     reset to the legacy weak (surcharged) functions in the @ref HAL_RNG_Init()
00062     and @ref HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand).
00063     If not, MspInit or MspDeInit are not null, the @ref HAL_RNG_Init() and @ref HAL_RNG_DeInit()
00064     keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
00065
00066     [..]
00067     Callbacks can be registered/unregistered in HAL_RNG_STATE_READY state only.
00068     Exception done MspInit/MspDeInit that can be registered/unregistered
00069     in HAL_RNG_STATE_READY or HAL_RNG_STATE_RESET state, thus registered (user)
00070     MspInit/DeInit callbacks can be used during the Init/DeInit.
00071     In that case first register the MspInit/MspDeInit user callbacks
00072     using @ref HAL_RNG_RegisterCallback() before calling @ref HAL_RNG_DeInit()
00073     or @ref HAL_RNG_Init() function.
00074
00075     [..]
00076     When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or
00077     not defined, the callback registration feature is not available
00078     and weak (surcharged) callbacks are used.
00079
00080   @endverbatim
00081   ******************************************************************************
00082   * @attention
00083   *
00084   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00085   * All rights reserved.</center></h2>
00086   *
00087   * This software component is licensed by ST under BSD 3-Clause license,
00088   * the "License"; You may not use this file except in compliance with the
00089   * License. You may obtain a copy of the License at:
00090   *                        opensource.org/licenses/BSD-3-Clause
00091   *
00092   ******************************************************************************
00093   */
00094
00095 /* Includes ------------------------------------------------------------------*/
00096 #include "stm32wbxx_hal.h"
00097
00098 /** @addtogroup STM32WBxx_HAL_Driver
00099   * @{
00100   */
00101
00102 #if defined (RNG)
00103
00104 /** @addtogroup RNG
00105   * @brief RNG HAL module driver.
00106   * @{
00107   */
00108
00109 #ifdef HAL_RNG_MODULE_ENABLED
00110
00111 /* Private types -------------------------------------------------------------*/
00112 /* Private defines -----------------------------------------------------------*/
00113 /* Private variables ---------------------------------------------------------*/
00114 /* Private constants ---------------------------------------------------------*/
00115 /** @defgroup RNG_Private_Constants RNG Private Constants
00116   * @{
00117   */
00118 #define RNG_TIMEOUT_VALUE     2U
00119 /**
00120   * @}
00121   */
00122 /* Private macros ------------------------------------------------------------*/
00123 /* Private functions prototypes ----------------------------------------------*/
00124 /* Private functions ---------------------------------------------------------*/
00125 /* Exported functions --------------------------------------------------------*/
00126
00127 /** @addtogroup RNG_Exported_Functions
00128   * @{
00129   */
00130
00131 /** @addtogroup RNG_Exported_Functions_Group1
00132  *  @brief   Initialization and configuration functions
00133  *
00134 @verbatim
00135  ===============================================================================
00136           ##### Initialization and configuration functions #####
00137  ===============================================================================
00138     [..]  This section provides functions allowing to:
00139       (+) Initialize the RNG according to the specified parameters
00140           in the RNG_InitTypeDef and create the associated handle
00141       (+) DeInitialize the RNG peripheral
00142       (+) Initialize the RNG MSP
00143       (+) DeInitialize RNG MSP
00144
00145 @endverbatim
00146   * @{
00147   */
00148
00149 /**
00150   * @brief  Initializes the RNG peripheral and creates the associated handle.
00151   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00152   *                the configuration information for RNG.
00153   * @retval HAL status
00154   */
00155 HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
00156 {
00157   /* Check the RNG handle allocation */
00158   if (hrng == NULL)
00159   {
00160     return HAL_ERROR;
00161   }
00162   /* Check the parameters */
00163   assert_param(IS_RNG_ALL_INSTANCE(hrng->Instance));
00164   assert_param(IS_RNG_CED(hrng->Init.ClockErrorDetection));
00165
00166 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00167   if (hrng->State == HAL_RNG_STATE_RESET)
00168   {
00169     /* Allocate lock resource and initialize it */
00170     hrng->Lock = HAL_UNLOCKED;
00171
00172     hrng->ReadyDataCallback  = HAL_RNG_ReadyDataCallback;  /* Legacy weak ReadyDataCallback  */
00173     hrng->ErrorCallback      = HAL_RNG_ErrorCallback;      /* Legacy weak ErrorCallback      */
00174
00175     if (hrng->MspInitCallback == NULL)
00176     {
00177       hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit  */
00178     }
00179
00180     /* Init the low level hardware */
00181     hrng->MspInitCallback(hrng);
00182   }
00183 #else
00184   if (hrng->State == HAL_RNG_STATE_RESET)
00185   {
00186     /* Allocate lock resource and initialize it */
00187     hrng->Lock = HAL_UNLOCKED;
00188
00189     /* Init the low level hardware */
00190     HAL_RNG_MspInit(hrng);
00191   }
00192 #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
00193
00194   /* Change RNG peripheral state */
00195   hrng->State = HAL_RNG_STATE_BUSY;
00196
00197   /* Clock Error Detection Configuration */
00198   MODIFY_REG(hrng->Instance->CR, RNG_CR_CED, hrng->Init.ClockErrorDetection);
00199
00200   /* Enable the RNG Peripheral */
00201   __HAL_RNG_ENABLE(hrng);
00202
00203   /* Initialize the RNG state */
00204   hrng->State = HAL_RNG_STATE_READY;
00205
00206   /* Initialise the error code */
00207   hrng->ErrorCode = HAL_RNG_ERROR_NONE;
00208
00209   /* Return function status */
00210   return HAL_OK;
00211 }
00212
00213 /**
00214   * @brief  DeInitializes the RNG peripheral.
00215   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00216   *                the configuration information for RNG.
00217   * @retval HAL status
00218   */
00219 HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
00220 {
00221   /* Check the RNG handle allocation */
00222   if (hrng == NULL)
00223   {
00224     return HAL_ERROR;
00225   }
00226
00227   /* Clear Clock Error Detection bit */
00228   CLEAR_BIT(hrng->Instance->CR, RNG_CR_CED);
00229   /* Disable the RNG Peripheral */
00230   CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN);
00231
00232   /* Clear RNG interrupt status flags */
00233   CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS);
00234
00235 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00236   if (hrng->MspDeInitCallback == NULL)
00237   {
00238     hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit  */
00239   }
00240
00241   /* DeInit the low level hardware */
00242   hrng->MspDeInitCallback(hrng);
00243 #else
00244   /* DeInit the low level hardware */
00245   HAL_RNG_MspDeInit(hrng);
00246 #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
00247
00248   /* Update the RNG state */
00249   hrng->State = HAL_RNG_STATE_RESET;
00250
00251   /* Initialise the error code */
00252   hrng->ErrorCode = HAL_RNG_ERROR_NONE;
00253
00254   /* Release Lock */
00255   __HAL_UNLOCK(hrng);
00256
00257   /* Return the function status */
00258   return HAL_OK;
00259 }
00260
00261 /**
00262   * @brief  Initializes the RNG MSP.
00263   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00264   *                the configuration information for RNG.
00265   * @retval None
00266   */
00267 __weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)
00268 {
00269   /* Prevent unused argument(s) compilation warning */
00270   UNUSED(hrng);
00271   /* NOTE : This function should not be modified. When the callback is needed,
00272             function HAL_RNG_MspInit must be implemented in the user file.
00273    */
00274 }
00275
00276 /**
00277   * @brief  DeInitializes the RNG MSP.
00278   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00279   *                the configuration information for RNG.
00280   * @retval None
00281   */
00282 __weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
00283 {
00284   /* Prevent unused argument(s) compilation warning */
00285   UNUSED(hrng);
00286   /* NOTE : This function should not be modified. When the callback is needed,
00287             function HAL_RNG_MspDeInit must be implemented in the user file.
00288    */
00289 }
00290
00291 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00292 /**
00293   * @brief  Register a User RNG Callback
00294   *         To be used instead of the weak predefined callback
00295   * @param  hrng RNG handle
00296   * @param  CallbackID ID of the callback to be registered
00297   *         This parameter can be one of the following values:
00298   *          @arg @ref HAL_RNG_ERROR_CB_ID Error callback ID
00299   *          @arg @ref HAL_RNG_MSPINIT_CB_ID MspInit callback ID
00300   *          @arg @ref HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID
00301   * @param  pCallback pointer to the Callback function
00302   * @retval HAL status
00303   */
00304 HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback)
00305 {
00306   HAL_StatusTypeDef status = HAL_OK;
00307
00308   if (pCallback == NULL)
00309   {
00310     /* Update the error code */
00311     hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00312     return HAL_ERROR;
00313   }
00314   /* Process locked */
00315   __HAL_LOCK(hrng);
00316
00317   if (HAL_RNG_STATE_READY == hrng->State)
00318   {
00319     switch (CallbackID)
00320     {
00321     case HAL_RNG_ERROR_CB_ID :
00322       hrng->ErrorCallback = pCallback;
00323       break;
00324
00325     case HAL_RNG_MSPINIT_CB_ID :
00326       hrng->MspInitCallback = pCallback;
00327       break;
00328
00329     case HAL_RNG_MSPDEINIT_CB_ID :
00330       hrng->MspDeInitCallback = pCallback;
00331       break;
00332
00333     default :
00334       /* Update the error code */
00335       hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00336      /* Return error status */
00337       status =  HAL_ERROR;
00338       break;
00339     }
00340   }
00341   else if (HAL_RNG_STATE_RESET == hrng->State)
00342   {
00343     switch (CallbackID)
00344     {
00345     case HAL_RNG_MSPINIT_CB_ID :
00346       hrng->MspInitCallback = pCallback;
00347       break;
00348
00349     case HAL_RNG_MSPDEINIT_CB_ID :
00350       hrng->MspDeInitCallback = pCallback;
00351       break;
00352
00353     default :
00354       /* Update the error code */
00355       hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00356      /* Return error status */
00357       status =  HAL_ERROR;
00358       break;
00359     }
00360   }
00361   else
00362   {
00363     /* Update the error code */
00364     hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00365     /* Return error status */
00366     status =  HAL_ERROR;
00367   }
00368
00369   /* Release Lock */
00370   __HAL_UNLOCK(hrng);
00371   return status;
00372 }
00373
00374 /**
00375   * @brief  Unregister an RNG Callback
00376   *         RNG callabck is redirected to the weak predefined callback
00377   * @param  hrng RNG handle
00378   * @param  CallbackID ID of the callback to be unregistered
00379   *         This parameter can be one of the following values:
00380   *          @arg @ref HAL_RNG_ERROR_CB_ID Error callback ID
00381   *          @arg @ref HAL_RNG_MSPINIT_CB_ID MspInit callback ID
00382   *          @arg @ref HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID
00383   * @retval HAL status
00384   */
00385 HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID)
00386 {
00387   HAL_StatusTypeDef status = HAL_OK;
00388
00389   /* Process locked */
00390   __HAL_LOCK(hrng);
00391
00392   if (HAL_RNG_STATE_READY == hrng->State)
00393   {
00394     switch (CallbackID)
00395     {
00396     case HAL_RNG_ERROR_CB_ID :
00397       hrng->ErrorCallback = HAL_RNG_ErrorCallback;          /* Legacy weak ErrorCallback  */
00398       break;
00399
00400     case HAL_RNG_MSPINIT_CB_ID :
00401       hrng->MspInitCallback = HAL_RNG_MspInit;              /* Legacy weak MspInit  */
00402       break;
00403
00404     case HAL_RNG_MSPDEINIT_CB_ID :
00405       hrng->MspDeInitCallback = HAL_RNG_MspDeInit;          /* Legacy weak MspDeInit  */
00406       break;
00407
00408     default :
00409       /* Update the error code */
00410       hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00411      /* Return error status */
00412       status =  HAL_ERROR;
00413       break;
00414     }
00415   }
00416   else if (HAL_RNG_STATE_RESET == hrng->State)
00417   {
00418     switch (CallbackID)
00419     {
00420     case HAL_RNG_MSPINIT_CB_ID :
00421       hrng->MspInitCallback = HAL_RNG_MspInit;              /* Legacy weak MspInit  */
00422       break;
00423
00424     case HAL_RNG_MSPDEINIT_CB_ID :
00425       hrng->MspDeInitCallback = HAL_RNG_MspDeInit;          /* Legacy weak MspInit  */
00426       break;
00427
00428     default :
00429       /* Update the error code */
00430       hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00431      /* Return error status */
00432       status =  HAL_ERROR;
00433       break;
00434     }
00435   }
00436   else
00437   {
00438     /* Update the error code */
00439     hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00440     /* Return error status */
00441     status =  HAL_ERROR;
00442   }
00443
00444   /* Release Lock */
00445   __HAL_UNLOCK(hrng);
00446   return status;
00447 }
00448
00449 /**
00450   * @brief  Register Data Ready RNG Callback
00451   *         To be used instead of the weak HAL_RNG_ReadyDataCallback() predefined callback
00452   * @param  hrng RNG handle
00453   * @param  pCallback pointer to the Data Ready Callback function
00454   * @retval HAL status
00455   */
00456 HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback)
00457 {
00458   HAL_StatusTypeDef status = HAL_OK;
00459
00460   if (pCallback == NULL)
00461   {
00462     /* Update the error code */
00463     hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00464     return HAL_ERROR;
00465   }
00466   /* Process locked */
00467   __HAL_LOCK(hrng);
00468
00469   if (HAL_RNG_STATE_READY == hrng->State)
00470   {
00471     hrng->ReadyDataCallback = pCallback;
00472   }
00473   else
00474   {
00475     /* Update the error code */
00476     hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00477     /* Return error status */
00478     status =  HAL_ERROR;
00479   }
00480
00481   /* Release Lock */
00482   __HAL_UNLOCK(hrng);
00483   return status;
00484 }
00485
00486 /**
00487   * @brief  UnRegister the Data Ready RNG Callback
00488   *         Data Ready RNG Callback is redirected to the weak HAL_RNG_ReadyDataCallback() predefined callback
00489   * @param  hrng RNG handle
00490   * @retval HAL status
00491   */
00492 HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng)
00493 {
00494   HAL_StatusTypeDef status = HAL_OK;
00495
00496   /* Process locked */
00497   __HAL_LOCK(hrng);
00498
00499   if (HAL_RNG_STATE_READY == hrng->State)
00500   {
00501     hrng->ReadyDataCallback = HAL_RNG_ReadyDataCallback; /* Legacy weak ReadyDataCallback  */
00502   }
00503   else
00504   {
00505     /* Update the error code */
00506     hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
00507     /* Return error status */
00508     status =  HAL_ERROR;
00509   }
00510
00511   /* Release Lock */
00512   __HAL_UNLOCK(hrng);
00513   return status;
00514 }
00515
00516 #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
00517
00518 /**
00519   * @}
00520   */
00521
00522 /** @addtogroup RNG_Exported_Functions_Group2
00523  *  @brief   Peripheral Control functions
00524  *
00525 @verbatim
00526  ===============================================================================
00527                       ##### Peripheral Control functions #####
00528  ===============================================================================
00529     [..]  This section provides functions allowing to:
00530       (+) Get the 32 bit Random number
00531       (+) Get the 32 bit Random number with interrupt enabled
00532       (+) Handle RNG interrupt request
00533
00534 @endverbatim
00535   * @{
00536   */
00537
00538 /**
00539   * @brief  Generates a 32-bit random number.
00540   * @note   This function checks value of RNG_FLAG_DRDY flag to know if valid
00541   *         random number is available in the DR register (RNG_FLAG_DRDY flag set
00542   *         whenever a random number is available through the RNG_DR register).
00543   *         After transitioning from 0 to 1 (random number available),
00544   *         RNG_FLAG_DRDY flag remains high until output buffer becomes empty after reading
00545   *         four words from the RNG_DR register, i.e. further function calls
00546   *         will immediately return a new u32 random number (additional words are
00547   *         available and can be read by the application, till RNG_FLAG_DRDY flag remains high).
00548   * @note   When no more random number data is available in DR register, RNG_FLAG_DRDY
00549   *         flag is automatically cleared.
00550   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00551   *                the configuration information for RNG.
00552   * @param  random32bit pointer to generated random number variable if successful.
00553   * @retval HAL status
00554   */
00555
00556 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit)
00557 {
00558   uint32_t tickstart;
00559   HAL_StatusTypeDef status = HAL_OK;
00560
00561   /* Process Locked */
00562   __HAL_LOCK(hrng);
00563
00564   /* Check RNG peripheral state */
00565   if (hrng->State == HAL_RNG_STATE_READY)
00566   {
00567     /* Change RNG peripheral state */
00568     hrng->State = HAL_RNG_STATE_BUSY;
00569
00570     /* Get tick */
00571     tickstart = HAL_GetTick();
00572
00573     /* Check if data register contains valid random data */
00574     while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
00575     {
00576       if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
00577       {
00578         hrng->State = HAL_RNG_STATE_READY;
00579         hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
00580         /* Process Unlocked */
00581         __HAL_UNLOCK(hrng);
00582         return HAL_ERROR;
00583       }
00584     }
00585
00586     /* Get a 32bit Random number */
00587     hrng->RandomNumber = hrng->Instance->DR;
00588     *random32bit = hrng->RandomNumber;
00589
00590     hrng->State = HAL_RNG_STATE_READY;
00591   }
00592   else
00593   {
00594     hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
00595     status = HAL_ERROR;
00596   }
00597
00598   /* Process Unlocked */
00599   __HAL_UNLOCK(hrng);
00600
00601   return status;
00602 }
00603
00604 /**
00605   * @brief  Generates a 32-bit random number in interrupt mode.
00606   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00607   *                the configuration information for RNG.
00608   * @retval HAL status
00609   */
00610 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)
00611 {
00612   HAL_StatusTypeDef status = HAL_OK;
00613
00614   /* Process Locked */
00615   __HAL_LOCK(hrng);
00616
00617   /* Check RNG peripheral state */
00618   if (hrng->State == HAL_RNG_STATE_READY)
00619   {
00620     /* Change RNG peripheral state */
00621     hrng->State = HAL_RNG_STATE_BUSY;
00622
00623     /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
00624     __HAL_RNG_ENABLE_IT(hrng);
00625   }
00626   else
00627   {
00628     /* Process Unlocked */
00629     __HAL_UNLOCK(hrng);
00630
00631     hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
00632     status = HAL_ERROR;
00633   }
00634
00635   return status;
00636 }
00637
00638 /**
00639   * @brief  Handles RNG interrupt request.
00640   * @note   In the case of a clock error, the RNG is no more able to generate
00641   *         random numbers because the PLL48CLK clock is not correct. User has
00642   *         to check that the clock controller is correctly configured to provide
00643   *         the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT().
00644   *         The clock error has no impact on the previously generated
00645   *         random numbers, and the RNG_DR register contents can be used.
00646   * @note   In the case of a seed error, the generation of random numbers is
00647   *         interrupted as long as the SECS bit is '1'. If a number is
00648   *         available in the RNG_DR register, it must not be used because it may
00649   *         not have enough entropy. In this case, it is recommended to clear the
00650   *         SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable
00651   *         the RNG peripheral to reinitialize and restart the RNG.
00652   * @note   User-written HAL_RNG_ErrorCallback() API is called once whether SEIS
00653   *         or CEIS are set.
00654   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00655   *                the configuration information for RNG.
00656   * @retval None
00657
00658   */
00659 void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
00660 {
00661   uint32_t rngclockerror = 0U;
00662
00663   /* RNG clock error interrupt occurred */
00664   if (__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET)
00665   {
00666     /* Update the error code */
00667     hrng->ErrorCode = HAL_RNG_ERROR_CLOCK;
00668     rngclockerror = 1U;
00669   }
00670   else if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
00671   {
00672     /* Update the error code */
00673     hrng->ErrorCode = HAL_RNG_ERROR_SEED;
00674     rngclockerror = 1U;
00675   }
00676   else
00677   {
00678     /* Nothing to do */
00679   }
00680
00681   if (rngclockerror == 1U)
00682   {
00683     /* Change RNG peripheral state */
00684     hrng->State = HAL_RNG_STATE_ERROR;
00685
00686 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00687     /* Call registered Error callback */
00688     hrng->ErrorCallback(hrng);
00689 #else
00690     /* Call legacy weak Error callback */
00691     HAL_RNG_ErrorCallback(hrng);
00692 #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
00693
00694     /* Clear the clock error flag */
00695     __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI | RNG_IT_SEI);
00696   }
00697
00698   /* Check RNG data ready interrupt occurred */
00699   if (__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)
00700   {
00701     /* Generate random number once, so disable the IT */
00702     __HAL_RNG_DISABLE_IT(hrng);
00703
00704     /* Get the 32bit Random number (DRDY flag automatically cleared) */
00705     hrng->RandomNumber = hrng->Instance->DR;
00706
00707     if (hrng->State != HAL_RNG_STATE_ERROR)
00708     {
00709       /* Change RNG peripheral state */
00710       hrng->State = HAL_RNG_STATE_READY;
00711       /* Process Unlocked */
00712       __HAL_UNLOCK(hrng);
00713
00714 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00715       /* Call registered Data Ready callback */
00716       hrng->ReadyDataCallback(hrng, hrng->RandomNumber);
00717 #else
00718       /* Call legacy weak Data Ready callback */
00719       HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber);
00720 #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
00721     }
00722   }
00723 }
00724
00725 /**
00726   * @brief  Read latest generated random number.
00727   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00728   *                the configuration information for RNG.
00729   * @retval random value
00730   */
00731 uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)
00732 {
00733   return (hrng->RandomNumber);
00734 }
00735
00736 /**
00737   * @brief  Data Ready callback in non-blocking mode.
00738   * @note   When RNG_FLAG_DRDY flag value is set, first random number has been read
00739   *         from DR register in IRQ Handler and is provided as callback parameter.
00740   *         Depending on valid data available in the conditioning output buffer,
00741   *         additional words can be read by the application from DR register till
00742   *         DRDY bit remains high.
00743   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00744   *                the configuration information for RNG.
00745   * @param  random32bit generated random number.
00746   * @retval None
00747   */
00748 __weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit)
00749 {
00750   /* Prevent unused argument(s) compilation warning */
00751   UNUSED(hrng);
00752   UNUSED(random32bit);
00753   /* NOTE : This function should not be modified. When the callback is needed,
00754             function HAL_RNG_ReadyDataCallback must be implemented in the user file.
00755    */
00756 }
00757
00758 /**
00759   * @brief  RNG error callbacks.
00760   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00761   *                the configuration information for RNG.
00762   * @retval None
00763   */
00764 __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
00765 {
00766   /* Prevent unused argument(s) compilation warning */
00767   UNUSED(hrng);
00768   /* NOTE : This function should not be modified. When the callback is needed,
00769             function HAL_RNG_ErrorCallback must be implemented in the user file.
00770    */
00771 }
00772 /**
00773   * @}
00774   */
00775
00776
00777 /** @addtogroup RNG_Exported_Functions_Group3
00778  *  @brief   Peripheral State functions
00779  *
00780 @verbatim
00781  ===============================================================================
00782                       ##### Peripheral State functions #####
00783  ===============================================================================
00784     [..]
00785     This subsection permits to get in run-time the status of the peripheral
00786     and the data flow.
00787
00788 @endverbatim
00789   * @{
00790   */
00791
00792 /**
00793   * @brief  Returns the RNG state.
00794   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
00795   *                the configuration information for RNG.
00796   * @retval HAL state
00797   */
00798 HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
00799 {
00800   return hrng->State;
00801 }
00802
00803 /**
00804   * @brief  Return the RNG handle error code.
00805   * @param  hrng: pointer to a RNG_HandleTypeDef structure.
00806   * @retval RNG Error Code
00807 */
00808 uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng)
00809 {
00810   /* Return RNG Error Code */
00811   return hrng->ErrorCode;
00812 }
00813 /**
00814   * @}
00815   */
00816
00817 /**
00818   * @}
00819   */
00820
00821
00822 #endif /* HAL_RNG_MODULE_ENABLED */
00823 /**
00824   * @}
00825   */
00826
00827 #endif /* RNG */
00828
00829 /**
00830   * @}
00831   */
00832
00833 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:35 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_rng.h Source File

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stm32wbxx_hal_rng.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_rng.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of RNG HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_RNG_H
00022 #define STM32WBxx_HAL_RNG_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 /** @addtogroup STM32WBxx_HAL_Driver
00032   * @{
00033   */
00034
00035 #if defined (RNG)
00036
00037 /** @defgroup RNG RNG
00038   * @brief RNG HAL module driver
00039   * @{
00040   */
00041
00042 /* Exported types ------------------------------------------------------------*/
00043
00044 /** @defgroup RNG_Exported_Types RNG Exported Types
00045   * @{
00046   */
00047
00048 /** @defgroup RNG_Exported_Types_Group1 RNG Init Structure definition
00049   * @{
00050   */
00051 typedef struct
00052 {
00053   uint32_t                    ClockErrorDetection; /*!< CED Clock error detection */
00054 } RNG_InitTypeDef;
00055
00056 /**
00057   * @}
00058   */
00059
00060 /** @defgroup RNG_Exported_Types_Group2 RNG State Structure definition
00061   * @{
00062   */
00063 typedef enum
00064 {
00065   HAL_RNG_STATE_RESET     = 0x00U,  /*!< RNG not yet initialized or disabled */
00066   HAL_RNG_STATE_READY     = 0x01U,  /*!< RNG initialized and ready for use   */
00067   HAL_RNG_STATE_BUSY      = 0x02U,  /*!< RNG internal process is ongoing     */
00068   HAL_RNG_STATE_TIMEOUT   = 0x03U,  /*!< RNG timeout state                   */
00069   HAL_RNG_STATE_ERROR     = 0x04U   /*!< RNG error state                     */
00070
00071 } HAL_RNG_StateTypeDef;
00072
00073 /**
00074   * @}
00075   */
00076
00077 /** @defgroup RNG_Exported_Types_Group3 RNG Handle Structure definition
00078   * @{
00079   */
00080 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00081 typedef struct  __RNG_HandleTypeDef
00082 #else
00083 typedef struct
00084 #endif /* (USE_HAL_RNG_REGISTER_CALLBACKS) */
00085 {
00086   RNG_TypeDef                 *Instance;    /*!< Register base address   */
00087
00088   RNG_InitTypeDef             Init;         /*!< RNG configuration parameters */
00089
00090   HAL_LockTypeDef             Lock;         /*!< RNG locking object      */
00091
00092   __IO HAL_RNG_StateTypeDef   State;        /*!< RNG communication state */
00093
00094   __IO  uint32_t              ErrorCode;     /*!< RNG Error code               */
00095
00096   uint32_t                    RandomNumber; /*!< Last Generated RNG Data */
00097
00098 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00099   void (* ReadyDataCallback)(struct __RNG_HandleTypeDef *hrng, uint32_t random32bit);  /*!< RNG Data Ready Callback    */
00100   void (* ErrorCallback)(struct __RNG_HandleTypeDef *hrng);                            /*!< RNG Error Callback         */
00101
00102   void (* MspInitCallback)(struct __RNG_HandleTypeDef *hrng);                          /*!< RNG Msp Init callback      */
00103   void (* MspDeInitCallback)(struct __RNG_HandleTypeDef *hrng);                        /*!< RNG Msp DeInit callback    */
00104 #endif  /* USE_HAL_RNG_REGISTER_CALLBACKS */
00105
00106 } RNG_HandleTypeDef;
00107
00108 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00109 /**
00110   * @brief  HAL RNG Callback ID enumeration definition
00111   */
00112 typedef enum
00113 {
00114   HAL_RNG_ERROR_CB_ID                   = 0x00U,     /*!< RNG Error Callback ID          */
00115
00116   HAL_RNG_MSPINIT_CB_ID                 = 0x01U,     /*!< RNG MspInit callback ID        */
00117   HAL_RNG_MSPDEINIT_CB_ID               = 0x02U      /*!< RNG MspDeInit callback ID      */
00118
00119 } HAL_RNG_CallbackIDTypeDef;
00120
00121 /**
00122   * @brief  HAL RNG Callback pointer definition
00123   */
00124 typedef  void (*pRNG_CallbackTypeDef)(RNG_HandleTypeDef *hrng);                                  /*!< pointer to a common RNG callback function */
00125 typedef  void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t random32bit);   /*!< pointer to an RNG Data Ready specific callback function */
00126
00127 #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
00128
00129 /**
00130   * @}
00131   */
00132
00133 /**
00134   * @}
00135   */
00136
00137 /* Exported constants --------------------------------------------------------*/
00138 /** @defgroup RNG_Exported_Constants RNG Exported Constants
00139   * @{
00140   */
00141
00142 /** @defgroup RNG_Exported_Constants_Group1 RNG Interrupt definition
00143   * @{
00144   */
00145 #define RNG_IT_DRDY  RNG_SR_DRDY  /*!< Data Ready interrupt  */
00146 #define RNG_IT_CEI   RNG_SR_CEIS  /*!< Clock error interrupt */
00147 #define RNG_IT_SEI   RNG_SR_SEIS  /*!< Seed error interrupt  */
00148 /**
00149   * @}
00150   */
00151
00152 /** @defgroup RNG_Exported_Constants_Group2 RNG Flag definition
00153   * @{
00154   */
00155 #define RNG_FLAG_DRDY   RNG_SR_DRDY  /*!< Data ready                 */
00156 #define RNG_FLAG_CECS   RNG_SR_CECS  /*!< Clock error current status */
00157 #define RNG_FLAG_SECS   RNG_SR_SECS  /*!< Seed error current status  */
00158 /**
00159   * @}
00160   */
00161
00162 /** @defgroup RNG_Exported_Constants_Group3 RNG Clock Error Detection
00163   * @{
00164   */
00165 #define RNG_CED_ENABLE          0x00000000U /*!< Clock error detection Enabled  */
00166 #define RNG_CED_DISABLE         RNG_CR_CED  /*!< Clock error detection Disabled */
00167 /**
00168   * @}
00169   */
00170
00171 /** @defgroup RNG_Error_Definition   RNG Error Definition
00172   * @{
00173   */
00174 #define  HAL_RNG_ERROR_NONE             0x00000000U    /*!< No error             */
00175 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00176 #define  HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U    /*!< Invalid Callback error  */
00177 #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
00178 #define  HAL_RNG_ERROR_TIMEOUT          0x00000002U    /*!< Timeout error        */
00179 #define  HAL_RNG_ERROR_BUSY             0x00000004U    /*!< Busy error        */
00180 #define  HAL_RNG_ERROR_SEED             0x00000008U    /*!< Seed error        */
00181 #define  HAL_RNG_ERROR_CLOCK            0x00000010U   /*!< Clock error        */
00182 /**
00183   * @}
00184   */
00185
00186 /**
00187   * @}
00188   */
00189
00190 /* Exported macros -----------------------------------------------------------*/
00191 /** @defgroup RNG_Exported_Macros RNG Exported Macros
00192   * @{
00193   */
00194
00195 /** @brief Reset RNG handle state
00196   * @param  __HANDLE__ RNG Handle
00197   * @retval None
00198   */
00199 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00200 #define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
00201                                                        (__HANDLE__)->State = HAL_RNG_STATE_RESET;       \
00202                                                        (__HANDLE__)->MspInitCallback = NULL;            \
00203                                                        (__HANDLE__)->MspDeInitCallback = NULL;          \
00204                                                     } while(0U)
00205 #else
00206 #define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
00207 #endif /*USE_HAL_RNG_REGISTER_CALLBACKS */
00208
00209 /**
00210   * @brief  Enables the RNG peripheral.
00211   * @param  __HANDLE__ RNG Handle
00212   * @retval None
00213   */
00214 #define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_RNGEN)
00215
00216 /**
00217   * @brief  Disables the RNG peripheral.
00218   * @param  __HANDLE__ RNG Handle
00219   * @retval None
00220   */
00221 #define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
00222
00223 /**
00224   * @brief  Check the selected RNG flag status.
00225   * @param  __HANDLE__ RNG Handle
00226   * @param  __FLAG__ RNG flag
00227   *          This parameter can be one of the following values:
00228   *            @arg RNG_FLAG_DRDY:  Data ready
00229   *            @arg RNG_FLAG_CECS:  Clock error current status
00230   *            @arg RNG_FLAG_SECS:  Seed error current status
00231   * @retval The new state of __FLAG__ (SET or RESET).
00232   */
00233 #define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
00234
00235 /**
00236   * @brief  Clears the selected RNG flag status.
00237   * @param  __HANDLE__ RNG handle
00238   * @param  __FLAG__ RNG flag to clear
00239   * @note   WARNING: This is a dummy macro for HAL code alignment,
00240   *         flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
00241   * @retval None
00242   */
00243 #define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__)                      /* dummy  macro */
00244
00245 /**
00246   * @brief  Enables the RNG interrupts.
00247   * @param  __HANDLE__ RNG Handle
00248   * @retval None
00249   */
00250 #define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_IE)
00251
00252 /**
00253   * @brief  Disables the RNG interrupts.
00254   * @param  __HANDLE__ RNG Handle
00255   * @retval None
00256   */
00257 #define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
00258
00259 /**
00260   * @brief  Checks whether the specified RNG interrupt has occurred or not.
00261   * @param  __HANDLE__ RNG Handle
00262   * @param  __INTERRUPT__ specifies the RNG interrupt status flag to check.
00263   *         This parameter can be one of the following values:
00264   *            @arg RNG_IT_DRDY: Data ready interrupt
00265   *            @arg RNG_IT_CEI: Clock error interrupt
00266   *            @arg RNG_IT_SEI: Seed error interrupt
00267   * @retval The new state of __INTERRUPT__ (SET or RESET).
00268   */
00269 #define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
00270
00271 /**
00272   * @brief  Clear the RNG interrupt status flags.
00273   * @param  __HANDLE__ RNG Handle
00274   * @param  __INTERRUPT__ specifies the RNG interrupt status flag to clear.
00275   *          This parameter can be one of the following values:
00276   *            @arg RNG_IT_CEI: Clock error interrupt
00277   *            @arg RNG_IT_SEI: Seed error interrupt
00278   * @note   RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.
00279   * @retval None
00280   */
00281 #define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
00282
00283 /**
00284   * @}
00285   */
00286
00287 /* Exported functions --------------------------------------------------------*/
00288 /** @defgroup RNG_Exported_Functions RNG Exported Functions
00289   * @{
00290   */
00291
00292 /** @defgroup RNG_Exported_Functions_Group1 Initialization and configuration functions
00293   * @{
00294   */
00295 HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
00296 HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng);
00297 void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
00298 void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
00299
00300 /* Callbacks Register/UnRegister functions  ***********************************/
00301 #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
00302 HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback);
00303 HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID);
00304
00305 HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback);
00306 HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng);
00307 #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
00308
00309 /**
00310   * @}
00311   */
00312
00313 /** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions
00314   * @{
00315   */
00316 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
00317 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
00318 uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
00319
00320 void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
00321 void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
00322 void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit);
00323
00324 /**
00325   * @}
00326   */
00327
00328 /** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
00329   * @{
00330   */
00331 HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
00332 uint32_t             HAL_RNG_GetError(RNG_HandleTypeDef *hrng);
00333 /**
00334   * @}
00335   */
00336
00337 /**
00338   * @}
00339   */
00340
00341 /* Private macros ------------------------------------------------------------*/
00342 /** @defgroup RNG_Private_Macros RNG Private Macros
00343   * @{
00344   */
00345 #define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \
00346                        ((IT) == RNG_IT_SEI))
00347
00348 #define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
00349                             ((FLAG) == RNG_FLAG_CECS) || \
00350                             ((FLAG) == RNG_FLAG_SECS))
00351
00352 /**
00353   * @brief Verify the RNG Clock Error Detection mode.
00354   * @param __MODE__ RNG Clock Error Detection mode
00355   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00356   */
00357 #define IS_RNG_CED(__MODE__)   (((__MODE__) == RNG_CED_ENABLE) || \
00358                                 ((__MODE__) == RNG_CED_DISABLE))
00359 /**
00360   * @}
00361   */
00362
00363 /**
00364   * @}
00365   */
00366
00367 #endif /* RNG */
00368
00369 /**
00370   * @}
00371   */
00372
00373 #ifdef __cplusplus
00374 }
00375 #endif
00376
00377
00378 #endif /* STM32WBxx_HAL_RNG_H */
00379
00380 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:35 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_rtc.c Source File

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stm32wbxx_hal_rtc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_rtc.c
00004   * @author  MCD Application Team
00005   * @brief   RTC HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Real-Time Clock (RTC) peripheral:
00008   *           + Initialization
00009   *           + Calendar (Time and Date) configuration
00010   *           + Alarms (Alarm A and Alarm B) configuration
00011   *           + WakeUp Timer configuration
00012   *           + TimeStamp configuration
00013   *           + Tampers configuration
00014   *           + Backup Data Registers configuration
00015   *           + RTC Tamper and TimeStamp Pins Selection
00016   *           + Interrupts and flags management
00017   *
00018   @verbatim
00019  ===============================================================================
00020                           ##### RTC Operating Condition #####
00021  ===============================================================================
00022   [..] The real-time clock (RTC) and the RTC backup registers can be powered
00023        from the VBAT voltage when the main VDD supply is powered off.
00024        To retain the content of the RTC backup registers and supply the RTC
00025        when VDD is turned off, VBAT pin can be connected to an optional
00026        standby voltage supplied by a battery or by another source.
00027
00028                    ##### Backup Domain Reset #####
00029  ===============================================================================
00030   [..] The backup domain reset sets all RTC registers and the RCC_BDCR register
00031        to their reset values.
00032        A backup domain reset is generated when one of the following events occurs:
00033     (+) Software reset, triggered by setting the BDRST bit in the
00034         RCC Backup domain control register (RCC_BDCR).
00035     (+) VDD or VBAT power on, if both supplies have previously been powered off.
00036     (+) Tamper detection event resets all data backup registers.
00037
00038                    ##### Backup Domain Access #####
00039  ===================================================================
00040   [..] After reset, the backup domain (RTC registers, RTC backup data
00041        registers and backup SRAM) is protected against possible unwanted write
00042        accesses.
00043
00044   [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
00045     (+) Call the function HAL_RCCEx_PeriphCLKConfig with RCC_PERIPHCLK_RTC for
00046         PeriphClockSelection and select RTCClockSelection (LSE, LSI or HSEdiv32)
00047     (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() macro.
00048
00049                   ##### How to use RTC Driver #####
00050  ===================================================================
00051   [..]
00052     (+) Enable the RTC domain access (see description in the section above).
00053     (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
00054         format using the HAL_RTC_Init() function.
00055
00056   *** Time and Date configuration ***
00057   ===================================
00058   [..]
00059     (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
00060         and HAL_RTC_SetDate() functions.
00061     (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.
00062
00063   *** Alarm configuration ***
00064   ===========================
00065   [..]
00066     (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
00067             You can also configure the RTC Alarm with interrupt mode using the
00068             HAL_RTC_SetAlarm_IT() function.
00069     (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
00070
00071                   ##### RTC and low power modes #####
00072   ==================================================================
00073   [..] The MCU can be woken up from a low power mode by an RTC alternate
00074        function.
00075   [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
00076        RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
00077        These RTC alternate functions can wake up the system from the Stop and
00078        Standby low power modes.
00079   [..] The system can also wake up from low power modes without depending
00080        on an external interrupt (Auto-wakeup mode), by using the RTC alarm
00081        or the RTC wakeup events.
00082   [..] The RTC provides a programmable time base for waking up from the
00083        Stop or Standby mode at regular intervals.
00084        Wakeup from STOP and STANDBY modes is possible only when the RTC clock source
00085        is LSE or LSI.
00086
00087   *** Callback registration ***
00088   =============================================
00089
00090   [..]
00091   The compilation define  USE_RTC_REGISTER_CALLBACKS when set to 1
00092   allows the user to configure dynamically the driver callbacks.
00093   Use Function @ref HAL_RTC_RegisterCallback() to register an interrupt callback.
00094
00095   [..]
00096   Function @ref HAL_RTC_RegisterCallback() allows to register following callbacks:
00097     (+) AlarmAEventCallback          : RTC Alarm A Event callback.
00098     (+) AlarmBEventCallback          : RTC Alarm B Event callback.
00099     (+) TimeStampEventCallback       : RTC TimeStamp Event callback.
00100     (+) WakeUpTimerEventCallback     : RTC WakeUpTimer Event callback.
00101     (+) Tamper1EventCallback         : RTC Tamper 1 Event callback.
00102     (+) Tamper2EventCallback         : RTC Tamper 2 Event callback.
00103     (+) Tamper3EventCallback         : RTC Tamper 3 Event callback.
00104     (+) MspInitCallback              : RTC MspInit callback.
00105     (+) MspDeInitCallback            : RTC MspDeInit callback.
00106   [..]
00107   This function takes as parameters the HAL peripheral handle, the Callback ID
00108   and a pointer to the user callback function.
00109
00110   [..]
00111   Use function @ref HAL_RTC_UnRegisterCallback() to reset a callback to the default
00112   weak function.
00113   @ref HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00114   and the Callback ID.
00115   This function allows to reset following callbacks:
00116     (+) AlarmAEventCallback          : RTC Alarm A Event callback.
00117     (+) AlarmBEventCallback          : RTC Alarm B Event callback.
00118     (+) TimeStampEventCallback       : RTC TimeStamp Event callback.
00119     (+) WakeUpTimerEventCallback     : RTC WakeUpTimer Event callback.
00120     (+) Tamper1EventCallback         : RTC Tamper 1 Event callback.
00121     (+) Tamper2EventCallback         : RTC Tamper 2 Event callback.
00122     (+) Tamper3EventCallback         : RTC Tamper 3 Event callback.
00123     (+) MspInitCallback              : RTC MspInit callback.
00124     (+) MspDeInitCallback            : RTC MspDeInit callback.
00125
00126   [..]
00127   By default, after the @ref HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET,
00128   all callbacks are set to the corresponding weak functions :
00129   examples @ref AlarmAEventCallback(), @ref WakeUpTimerEventCallback().
00130   Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function
00131   in the @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() only when these callbacks are null
00132   (not registered beforehand).
00133   If not, MspInit or MspDeInit are not null, @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit()
00134   keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
00135
00136   [..]
00137   Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only.
00138   Exception done MspInit/MspDeInit that can be registered/unregistered
00139   in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state,
00140   thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00141   In that case first register the MspInit/MspDeInit user callbacks
00142   using @ref HAL_RTC_RegisterCallback() before calling @ref HAL_RTC_DeInit()
00143   or @ref HAL_RTC_Init() function.
00144
00145   [..]
00146   When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or
00147   not defined, the callback registration feature is not available and all callbacks
00148   are set to the corresponding weak functions.
00149
00150    @endverbatim
00151
00152   ******************************************************************************
00153   * @attention
00154   *
00155   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00156   * All rights reserved.</center></h2>
00157   *
00158   * This software component is licensed by ST under BSD 3-Clause license,
00159   * the "License"; You may not use this file except in compliance with the
00160   * License. You may obtain a copy of the License at:
00161   *                        opensource.org/licenses/BSD-3-Clause
00162   *
00163   ******************************************************************************
00164   */
00165
00166 /* Includes ------------------------------------------------------------------*/
00167 #include "stm32wbxx_hal.h"
00168
00169 /** @addtogroup STM32WBxx_HAL_Driver
00170   * @{
00171   */
00172
00173
00174 /** @addtogroup RTC
00175   * @brief RTC HAL module driver
00176   * @{
00177   */
00178
00179 #ifdef HAL_RTC_MODULE_ENABLED
00180
00181 /* Private typedef -----------------------------------------------------------*/
00182 /* Private define ------------------------------------------------------------*/
00183 /* Private macro -------------------------------------------------------------*/
00184 /* Private variables ---------------------------------------------------------*/
00185 /* Private function prototypes -----------------------------------------------*/
00186 /* Exported functions --------------------------------------------------------*/
00187
00188 /** @addtogroup RTC_Exported_Functions
00189   * @{
00190   */
00191
00192 /** @addtogroup RTC_Exported_Functions_Group1
00193  *  @brief    Initialization and Configuration functions
00194  *
00195 @verbatim
00196  ===============================================================================
00197               ##### Initialization and de-initialization functions #####
00198  ===============================================================================
00199    [..] This section provides functions allowing to initialize and configure the
00200          RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
00201          RTC registers Write protection, enter and exit the RTC initialization mode,
00202          RTC registers synchronization check and reference clock detection enable.
00203          (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
00204              It is split into 2 programmable prescalers to minimize power consumption.
00205              (++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler.
00206              (++) When both prescalers are used, it is recommended to configure the
00207                  asynchronous prescaler to a high value to minimize power consumption.
00208          (#) All RTC registers are Write protected. Writing to the RTC registers
00209              is enabled by writing a key into the Write Protection register, RTC_WPR.
00210          (#) To configure the RTC Calendar, user application should enter
00211              initialization mode. In this mode, the calendar counter is stopped
00212              and its value can be updated. When the initialization sequence is
00213              complete, the calendar restarts counting after 4 RTCCLK cycles.
00214          (#) To read the calendar through the shadow registers after Calendar
00215              initialization, calendar update or after wakeup from low power modes
00216              the software must first clear the RSF flag. The software must then
00217              wait until it is set again before reading the calendar, which means
00218              that the calendar registers have been correctly copied into the
00219              RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function
00220              implements the above software sequence (RSF clear and RSF check).
00221
00222 @endverbatim
00223   * @{
00224   */
00225
00226 /**
00227   * @brief  Initialize the RTC peripheral
00228   * @param hrtc RTC handle
00229   * @retval HAL status
00230   */
00231 HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
00232 {
00233   /* Check the RTC peripheral state */
00234   if(hrtc == NULL)
00235   {
00236      return HAL_ERROR;
00237   }
00238
00239   /* Check the parameters */
00240   assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
00241   assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat));
00242   assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv));
00243   assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv));
00244   assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut));
00245   assert_param(IS_RTC_OUTPUT_REMAP(hrtc->Init.OutPutRemap));
00246   assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity));
00247   assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType));
00248
00249 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
00250   if(hrtc->State == HAL_RTC_STATE_RESET)
00251   {
00252     /* Allocate lock resource and initialize it */
00253     hrtc->Lock = HAL_UNLOCKED;
00254
00255     hrtc->AlarmAEventCallback          =  HAL_RTC_AlarmAEventCallback;        /* Legacy weak AlarmAEventCallback      */
00256     hrtc->AlarmBEventCallback          =  HAL_RTCEx_AlarmBEventCallback;      /* Legacy weak AlarmBEventCallback      */
00257     hrtc->TimeStampEventCallback       =  HAL_RTCEx_TimeStampEventCallback;   /* Legacy weak TimeStampEventCallback   */
00258     hrtc->WakeUpTimerEventCallback     =  HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */
00259 #if defined(RTC_TAMPER1_SUPPORT)
00260     hrtc->Tamper1EventCallback         =  HAL_RTCEx_Tamper1EventCallback;     /* Legacy weak Tamper1EventCallback     */
00261 #endif
00262     hrtc->Tamper2EventCallback         =  HAL_RTCEx_Tamper2EventCallback;     /* Legacy weak Tamper2EventCallback     */
00263 #if defined(RTC_TAMPER3_SUPPORT)
00264     hrtc->Tamper3EventCallback         =  HAL_RTCEx_Tamper3EventCallback;     /* Legacy weak Tamper3EventCallback     */
00265 #endif
00266
00267     if(hrtc->MspInitCallback == NULL)
00268     {
00269       hrtc->MspInitCallback = HAL_RTC_MspInit;
00270     }
00271     /* Init the low level hardware */
00272     hrtc->MspInitCallback(hrtc);
00273
00274     if(hrtc->MspDeInitCallback == NULL)
00275     {
00276       hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
00277     }
00278   }
00279 #else
00280   if(hrtc->State == HAL_RTC_STATE_RESET)
00281   {
00282     /* Allocate lock resource and initialize it */
00283     hrtc->Lock = HAL_UNLOCKED;
00284
00285     /* Initialize RTC MSP */
00286     HAL_RTC_MspInit(hrtc);
00287   }
00288 #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
00289
00290   /* Set RTC state */
00291   hrtc->State = HAL_RTC_STATE_BUSY;
00292
00293   /* Disable the write protection for RTC registers */
00294   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00295
00296   /* Set Initialization mode */
00297   if(RTC_EnterInitMode(hrtc) != HAL_OK)
00298   {
00299     /* Enable the write protection for RTC registers */
00300     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00301
00302     /* Set RTC state */
00303     hrtc->State = HAL_RTC_STATE_ERROR;
00304
00305     return HAL_ERROR;
00306   }
00307   else
00308   {
00309     /* Clear RTC_CR FMT, OSEL and POL Bits */
00310     hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
00311     /* Set RTC_CR register */
00312     hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
00313
00314     /* Configure the RTC PRER */
00315     hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
00316     hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16U);
00317
00318     /* Exit Initialization mode */
00319     hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
00320
00321     hrtc->Instance->OR &= (uint32_t)~(RTC_OR_ALARMOUTTYPE | RTC_OR_OUT_RMP);
00322     hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType | hrtc->Init.OutPutRemap);
00323
00324     /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
00325     if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == 0U)
00326     {
00327       if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
00328       {
00329         /* Enable the write protection for RTC registers */
00330         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00331
00332         hrtc->State = HAL_RTC_STATE_ERROR;
00333
00334         /* Process Unlocked */
00335         __HAL_UNLOCK(hrtc);
00336
00337         return HAL_ERROR;
00338       }
00339     }
00340
00341     /* Enable the write protection for RTC registers */
00342     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00343
00344     /* Set RTC state */
00345     hrtc->State = HAL_RTC_STATE_READY;
00346
00347     return HAL_OK;
00348   }
00349 }
00350
00351 /**
00352   * @brief  DeInitialize the RTC peripheral.
00353   * @param hrtc RTC handle
00354   * @note   This function doesn't reset the RTC Backup Data registers.
00355   * @retval HAL status
00356   */
00357 HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
00358 {
00359   uint32_t tickstart;
00360
00361   /* Check the parameters */
00362   assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
00363
00364   /* Set RTC state */
00365   hrtc->State = HAL_RTC_STATE_BUSY;
00366
00367   /* Disable the write protection for RTC registers */
00368   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00369
00370   /* Set Initialization mode */
00371   if(RTC_EnterInitMode(hrtc) != HAL_OK)
00372   {
00373     /* Enable the write protection for RTC registers */
00374     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00375
00376     /* Set RTC state */
00377     hrtc->State = HAL_RTC_STATE_ERROR;
00378
00379     return HAL_ERROR;
00380   }
00381   else
00382   {
00383     /* Reset TR, DR and CR registers */
00384     hrtc->Instance->TR = (uint32_t)0x00000000U;
00385     hrtc->Instance->DR = ((uint32_t)(RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
00386     /* Reset All CR bits except CR[2:0] */
00387     hrtc->Instance->CR &= RTC_CR_WUCKSEL;
00388
00389     tickstart = HAL_GetTick();
00390
00391     /* Wait till WUTWF flag is set and if Time out is reached exit */
00392     while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == 0U)
00393     {
00394       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
00395       {
00396         /* Enable the write protection for RTC registers */
00397         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00398
00399         /* Set RTC state */
00400         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00401
00402         return HAL_TIMEOUT;
00403       }
00404     }
00405
00406     /* Reset all RTC CR register bits */
00407     hrtc->Instance->CR &= (uint32_t)0x00000000U;
00408     hrtc->Instance->WUTR = RTC_WUTR_WUT;
00409     hrtc->Instance->PRER = ((uint32_t)(RTC_PRER_PREDIV_A | 0x000000FFU));
00410     hrtc->Instance->ALRMAR = (uint32_t)0x00000000U;
00411     hrtc->Instance->ALRMBR = (uint32_t)0x00000000U;
00412     hrtc->Instance->SHIFTR = (uint32_t)0x00000000U;
00413     hrtc->Instance->CALR = (uint32_t)0x00000000U;
00414     hrtc->Instance->ALRMASSR = (uint32_t)0x00000000U;
00415     hrtc->Instance->ALRMBSSR = (uint32_t)0x00000000U;
00416
00417     /* Reset ISR register and exit initialization mode */
00418     hrtc->Instance->ISR = (uint32_t)0x00000000U;
00419
00420     /* Reset Tamper configuration register */
00421     hrtc->Instance->TAMPCR = 0x00000000U;
00422
00423     /* Reset Option register */
00424     hrtc->Instance->OR = 0x00000000U;
00425
00426     /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
00427     if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == 0U)
00428     {
00429       if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
00430       {
00431         /* Enable the write protection for RTC registers */
00432         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00433
00434         hrtc->State = HAL_RTC_STATE_ERROR;
00435
00436         return HAL_ERROR;
00437       }
00438     }
00439   }
00440
00441   /* Enable the write protection for RTC registers */
00442   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00443
00444 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
00445     if(hrtc->MspDeInitCallback == NULL)
00446     {
00447       hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
00448     }
00449
00450     /* DeInit the low level hardware: CLOCK, NVIC.*/
00451     hrtc->MspDeInitCallback(hrtc);
00452
00453 #else
00454   /* De-Initialize RTC MSP */
00455   HAL_RTC_MspDeInit(hrtc);
00456 #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
00457
00458   hrtc->State = HAL_RTC_STATE_RESET;
00459
00460   /* Release Lock */
00461   __HAL_UNLOCK(hrtc);
00462
00463   return HAL_OK;
00464 }
00465
00466 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
00467 /**
00468   * @brief  Register a User RTC Callback
00469   *         To be used instead of the weak predefined callback
00470   * @param  hrtc RTC handle
00471   * @param  CallbackID ID of the callback to be registered
00472   *         This parameter can be one of the following values:
00473   *          @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID          Alarm A Event Callback ID
00474   *          @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID          Alarm B Event Callback ID
00475   *          @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID        TimeStamp Event Callback ID
00476   *          @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID      WakeUp Timer Event Callback ID
00477   *          @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID          Tamper 1 Callback ID (*)
00478   *          @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID          Tamper 2 Callback ID
00479   *          @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID          Tamper 3 Callback ID (*)
00480   *          @arg @ref HAL_RTC_MSPINIT_CB_ID                Msp Init callback ID
00481   *          @arg @ref HAL_RTC_MSPDEINIT_CB_ID              Msp DeInit callback ID
00482   *
00483   *         (*)  Value not defined in all devices. \n
00484   *
00485   * @param  pCallback pointer to the Callback function
00486   * @retval HAL status
00487   */
00488 HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback)
00489 {
00490   HAL_StatusTypeDef status = HAL_OK;
00491
00492   if(pCallback == NULL)
00493   {
00494     return HAL_ERROR;
00495   }
00496
00497   /* Process locked */
00498   __HAL_LOCK(hrtc);
00499
00500   if(HAL_RTC_STATE_READY == hrtc->State)
00501   {
00502     switch (CallbackID)
00503     {
00504     case HAL_RTC_ALARM_A_EVENT_CB_ID :
00505       hrtc->AlarmAEventCallback = pCallback;
00506       break;
00507
00508     case HAL_RTC_ALARM_B_EVENT_CB_ID :
00509       hrtc->AlarmBEventCallback = pCallback;
00510       break;
00511
00512     case HAL_RTC_TIMESTAMP_EVENT_CB_ID :
00513       hrtc->TimeStampEventCallback = pCallback;
00514       break;
00515
00516     case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID :
00517       hrtc->WakeUpTimerEventCallback = pCallback;
00518       break;
00519
00520 #if defined(RTC_TAMPER1_SUPPORT)
00521     case HAL_RTC_TAMPER1_EVENT_CB_ID :
00522       hrtc->Tamper1EventCallback = pCallback;
00523       break;
00524 #endif
00525
00526     case HAL_RTC_TAMPER2_EVENT_CB_ID :
00527       hrtc->Tamper2EventCallback = pCallback;
00528       break;
00529
00530 #if defined(RTC_TAMPER3_SUPPORT)
00531     case HAL_RTC_TAMPER3_EVENT_CB_ID :
00532       hrtc->Tamper3EventCallback = pCallback;
00533       break;
00534 #endif
00535
00536    case HAL_RTC_MSPINIT_CB_ID :
00537       hrtc->MspInitCallback = pCallback;
00538       break;
00539
00540    case HAL_RTC_MSPDEINIT_CB_ID :
00541       hrtc->MspDeInitCallback = pCallback;
00542       break;
00543
00544     default :
00545      /* Return error status */
00546       status =  HAL_ERROR;
00547       break;
00548     }
00549   }
00550   else if(HAL_RTC_STATE_RESET == hrtc->State)
00551   {
00552     switch (CallbackID)
00553     {
00554     case HAL_RTC_MSPINIT_CB_ID :
00555       hrtc->MspInitCallback = pCallback;
00556       break;
00557
00558    case HAL_RTC_MSPDEINIT_CB_ID :
00559       hrtc->MspDeInitCallback = pCallback;
00560       break;
00561
00562     default :
00563      /* Return error status */
00564       status =  HAL_ERROR;
00565       break;
00566     }
00567   }
00568   else
00569   {
00570     /* Return error status */
00571     status =  HAL_ERROR;
00572   }
00573
00574   /* Release Lock */
00575   __HAL_UNLOCK(hrtc);
00576
00577   return status;
00578 }
00579
00580 /**
00581   * @brief  Unregister an RTC Callback
00582   *         RTC callabck is redirected to the weak predefined callback
00583   * @param  hrtc RTC handle
00584   * @param  CallbackID ID of the callback to be unregistered
00585   *         This parameter can be one of the following values:
00586   *          @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID          Alarm A Event Callback ID
00587   *          @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID          Alarm B Event Callback ID
00588   *          @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID        TimeStamp Event Callback ID
00589   *          @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID      WakeUp Timer Event Callback ID
00590   *          @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID          Tamper 1 Callback ID (*)
00591   *          @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID          Tamper 2 Callback ID
00592   *          @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID          Tamper 3 Callback ID (*)
00593   *          @arg @ref HAL_RTC_MSPINIT_CB_ID                Msp Init callback ID
00594   *          @arg @ref HAL_RTC_MSPDEINIT_CB_ID              Msp DeInit callback ID
00595   *
00596   *         (*)  Value not defined in all devices. \n
00597   *
00598   * @retval HAL status
00599   */
00600 HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID)
00601 {
00602   HAL_StatusTypeDef status = HAL_OK;
00603
00604   /* Process locked */
00605   __HAL_LOCK(hrtc);
00606
00607   if(HAL_RTC_STATE_READY == hrtc->State)
00608   {
00609     switch (CallbackID)
00610     {
00611     case HAL_RTC_ALARM_A_EVENT_CB_ID :
00612       hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback;         /* Legacy weak AlarmAEventCallback    */
00613       break;
00614
00615     case HAL_RTC_ALARM_B_EVENT_CB_ID :
00616       hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback;          /* Legacy weak AlarmBEventCallback */
00617       break;
00618
00619     case HAL_RTC_TIMESTAMP_EVENT_CB_ID :
00620       hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback;    /* Legacy weak TimeStampEventCallback    */
00621       break;
00622
00623     case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID :
00624       hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */
00625       break;
00626
00627 #if defined(RTC_TAMPER1_SUPPORT)
00628     case HAL_RTC_TAMPER1_EVENT_CB_ID :
00629       hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback;         /* Legacy weak Tamper1EventCallback   */
00630       break;
00631 #endif
00632
00633     case HAL_RTC_TAMPER2_EVENT_CB_ID :
00634       hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback;         /* Legacy weak Tamper2EventCallback         */
00635       break;
00636
00637 #if defined(RTC_TAMPER3_SUPPORT)
00638     case HAL_RTC_TAMPER3_EVENT_CB_ID :
00639       hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback;         /* Legacy weak Tamper3EventCallback         */
00640       break;
00641 #endif
00642
00643     case HAL_RTC_MSPINIT_CB_ID :
00644       hrtc->MspInitCallback = HAL_RTC_MspInit;
00645       break;
00646
00647     case HAL_RTC_MSPDEINIT_CB_ID :
00648       hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
00649       break;
00650
00651     default :
00652      /* Return error status */
00653       status =  HAL_ERROR;
00654       break;
00655     }
00656   }
00657   else if(HAL_RTC_STATE_RESET == hrtc->State)
00658   {
00659     switch (CallbackID)
00660     {
00661     case HAL_RTC_MSPINIT_CB_ID :
00662       hrtc->MspInitCallback = HAL_RTC_MspInit;
00663       break;
00664
00665     case HAL_RTC_MSPDEINIT_CB_ID :
00666       hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
00667       break;
00668
00669     default :
00670      /* Return error status */
00671       status =  HAL_ERROR;
00672       break;
00673     }
00674   }
00675   else
00676   {
00677     /* Return error status */
00678     status =  HAL_ERROR;
00679   }
00680
00681   /* Release Lock */
00682   __HAL_UNLOCK(hrtc);
00683
00684   return status;
00685 }
00686 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
00687
00688 /**
00689   * @brief  Initialize the RTC MSP.
00690   * @param hrtc RTC handle
00691   * @retval None
00692   */
00693 __weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
00694 {
00695   /* Prevent unused argument(s) compilation warning */
00696   UNUSED(hrtc);
00697
00698   /* NOTE : This function should not be modified, when the callback is needed,
00699             the HAL_RTC_MspInit could be implemented in the user file
00700    */
00701 }
00702
00703 /**
00704   * @brief  DeInitialize the RTC MSP.
00705   * @param hrtc RTC handle
00706   * @retval None
00707   */
00708 __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
00709 {
00710   /* Prevent unused argument(s) compilation warning */
00711   UNUSED(hrtc);
00712
00713   /* NOTE : This function should not be modified, when the callback is needed,
00714             the HAL_RTC_MspDeInit could be implemented in the user file
00715    */
00716 }
00717
00718 /**
00719   * @}
00720   */
00721
00722 /** @addtogroup RTC_Exported_Functions_Group2
00723  *  @brief   RTC Time and Date functions
00724  *
00725 @verbatim
00726  ===============================================================================
00727                  ##### RTC Time and Date functions #####
00728  ===============================================================================
00729
00730  [..] This section provides functions allowing to configure Time and Date features
00731
00732 @endverbatim
00733   * @{
00734   */
00735
00736 /**
00737   * @brief  Set RTC current time.
00738   * @param hrtc RTC handle
00739   * @param sTime Pointer to Time structure
00740   * @param Format Specifies the format of the entered parameters.
00741   *          This parameter can be one of the following values:
00742   *            @arg RTC_FORMAT_BIN: Binary data format
00743   *            @arg RTC_FORMAT_BCD: BCD data format
00744   * @retval HAL status
00745   */
00746 HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
00747 {
00748   uint32_t tmpreg;
00749
00750  /* Check the parameters */
00751   assert_param(IS_RTC_FORMAT(Format));
00752   assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving));
00753   assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation));
00754
00755   /* Process Locked */
00756   __HAL_LOCK(hrtc);
00757
00758   hrtc->State = HAL_RTC_STATE_BUSY;
00759
00760   if(Format == RTC_FORMAT_BIN)
00761   {
00762     if((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
00763     {
00764       assert_param(IS_RTC_HOUR12(sTime->Hours));
00765       assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
00766     }
00767     else
00768     {
00769       sTime->TimeFormat = 0x00U;
00770       assert_param(IS_RTC_HOUR24(sTime->Hours));
00771     }
00772     assert_param(IS_RTC_MINUTES(sTime->Minutes));
00773     assert_param(IS_RTC_SECONDS(sTime->Seconds));
00774
00775     tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16U) | \
00776                         ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8U) | \
00777                         ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \
00778                         (((uint32_t)sTime->TimeFormat) << 16U));
00779   }
00780   else
00781   {
00782     if((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
00783     {
00784       assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sTime->Hours)));
00785       assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
00786     }
00787     else
00788     {
00789       sTime->TimeFormat = 0x00U;
00790       assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));
00791     }
00792     assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
00793     assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
00794     tmpreg = (((uint32_t)(sTime->Hours) << 16U) | \
00795               ((uint32_t)(sTime->Minutes) << 8U) | \
00796               ((uint32_t)sTime->Seconds) | \
00797               ((uint32_t)(sTime->TimeFormat) << 16U));
00798   }
00799   UNUSED(tmpreg);
00800   /* Disable the write protection for RTC registers */
00801   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00802
00803   /* Set Initialization mode */
00804   if(RTC_EnterInitMode(hrtc) != HAL_OK)
00805   {
00806     /* Enable the write protection for RTC registers */
00807     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00808
00809     /* Set RTC state */
00810     hrtc->State = HAL_RTC_STATE_ERROR;
00811
00812     /* Process Unlocked */
00813     __HAL_UNLOCK(hrtc);
00814
00815     return HAL_ERROR;
00816   }
00817   else
00818   {
00819     /* Set the RTC_TR register */
00820     hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
00821
00822     /* Clear the bits to be configured */
00823     hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BKP);
00824
00825     /* Configure the RTC_CR register */
00826     hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
00827
00828     /* Exit Initialization mode */
00829     hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
00830
00831     /* If  CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
00832     if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == 0U)
00833     {
00834       if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
00835       {
00836         /* Enable the write protection for RTC registers */
00837         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00838
00839         hrtc->State = HAL_RTC_STATE_ERROR;
00840
00841         /* Process Unlocked */
00842         __HAL_UNLOCK(hrtc);
00843
00844         return HAL_ERROR;
00845       }
00846     }
00847
00848     /* Enable the write protection for RTC registers */
00849     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00850
00851    hrtc->State = HAL_RTC_STATE_READY;
00852
00853    __HAL_UNLOCK(hrtc);
00854
00855    return HAL_OK;
00856   }
00857 }
00858
00859 /**
00860   * @brief  Get RTC current time.
00861   * @param hrtc RTC handle
00862   * @param sTime Pointer to Time structure with Hours, Minutes and Seconds fields returned
00863   *                with input format (BIN or BCD), also SubSeconds field returning the
00864   *                RTC_SSR register content and SecondFraction field the Synchronous pre-scaler
00865   *                factor to be used for second fraction ratio computation.
00866   * @param Format Specifies the format of the entered parameters.
00867   *          This parameter can be one of the following values:
00868   *            @arg RTC_FORMAT_BIN: Binary data format
00869   *            @arg RTC_FORMAT_BCD: BCD data format
00870   * @note  You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds
00871   *        value in second fraction ratio with time unit following generic formula:
00872   *        Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
00873   *        This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
00874   * @note  You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
00875   *        in the higher-order calendar shadow registers to ensure consistency between the time and date values.
00876   *        Reading RTC current time locks the values in calendar shadow registers until Current date is read
00877   *        to ensure consistency between the time and date values.
00878   * @retval HAL status
00879   */
00880 HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
00881 {
00882   uint32_t tmpreg;
00883
00884   /* Check the parameters */
00885   assert_param(IS_RTC_FORMAT(Format));
00886
00887   /* Get subseconds structure field from the corresponding register*/
00888   sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR);
00889
00890   /* Get SecondFraction structure field from the corresponding register field*/
00891   sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S);
00892
00893   /* Get the TR register */
00894   tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK);
00895
00896   /* Fill the structure fields with the read parameters */
00897   sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16U);
00898   sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8U);
00899   sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
00900   sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16U);
00901
00902   /* Check the input parameters format */
00903   if(Format == RTC_FORMAT_BIN)
00904   {
00905     /* Convert the time structure parameters to Binary format */
00906     sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours);
00907     sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes);
00908     sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds);
00909   }
00910
00911   return HAL_OK;
00912 }
00913
00914 /**
00915   * @brief  Set RTC current date.
00916   * @param hrtc RTC handle
00917   * @param sDate Pointer to date structure
00918   * @param Format specifies the format of the entered parameters.
00919   *          This parameter can be one of the following values:
00920   *            @arg RTC_FORMAT_BIN: Binary data format
00921   *            @arg RTC_FORMAT_BCD: BCD data format
00922   * @retval HAL status
00923   */
00924 HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
00925 {
00926   uint32_t datetmpreg;
00927
00928  /* Check the parameters */
00929   assert_param(IS_RTC_FORMAT(Format));
00930
00931  /* Process Locked */
00932  __HAL_LOCK(hrtc);
00933
00934   hrtc->State = HAL_RTC_STATE_BUSY;
00935
00936   if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U))
00937   {
00938     sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU);
00939   }
00940
00941   assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));
00942
00943   if(Format == RTC_FORMAT_BIN)
00944   {
00945     assert_param(IS_RTC_YEAR(sDate->Year));
00946     assert_param(IS_RTC_MONTH(sDate->Month));
00947     assert_param(IS_RTC_DATE(sDate->Date));
00948
00949    datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16U) | \
00950                  ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8U) | \
00951                  ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \
00952                  ((uint32_t)sDate->WeekDay << 13U));
00953   }
00954   else
00955   {
00956     assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
00957     assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month)));
00958     assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date)));
00959
00960     datetmpreg = ((((uint32_t)sDate->Year) << 16U) | \
00961                   (((uint32_t)sDate->Month) << 8U) | \
00962                   ((uint32_t)sDate->Date) | \
00963                   (((uint32_t)sDate->WeekDay) << 13U));
00964   }
00965
00966   /* Disable the write protection for RTC registers */
00967   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00968
00969   /* Set Initialization mode */
00970   if(RTC_EnterInitMode(hrtc) != HAL_OK)
00971   {
00972     /* Enable the write protection for RTC registers */
00973     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00974
00975     /* Set RTC state*/
00976     hrtc->State = HAL_RTC_STATE_ERROR;
00977
00978     /* Process Unlocked */
00979     __HAL_UNLOCK(hrtc);
00980
00981     return HAL_ERROR;
00982   }
00983   else
00984   {
00985     /* Set the RTC_DR register */
00986     hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK);
00987
00988     /* Exit Initialization mode */
00989     hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
00990
00991     /* If  CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
00992     if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == 0U)
00993     {
00994       if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
00995       {
00996         /* Enable the write protection for RTC registers */
00997         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00998
00999         hrtc->State = HAL_RTC_STATE_ERROR;
01000
01001         /* Process Unlocked */
01002         __HAL_UNLOCK(hrtc);
01003
01004         return HAL_ERROR;
01005       }
01006     }
01007
01008     /* Enable the write protection for RTC registers */
01009     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01010
01011     hrtc->State = HAL_RTC_STATE_READY ;
01012
01013     /* Process Unlocked */
01014     __HAL_UNLOCK(hrtc);
01015
01016     return HAL_OK;
01017   }
01018 }
01019
01020 /**
01021   * @brief  Get RTC current date.
01022   * @param hrtc RTC handle
01023   * @param sDate Pointer to Date structure
01024   * @param Format Specifies the format of the entered parameters.
01025   *          This parameter can be one of the following values:
01026   *            @arg RTC_FORMAT_BIN:  Binary data format
01027   *            @arg RTC_FORMAT_BCD:  BCD data format
01028   * @note  You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
01029   *        in the higher-order calendar shadow registers to ensure consistency between the time and date values.
01030   *        Reading RTC current time locks the values in calendar shadow registers until Current date is read.
01031   * @retval HAL status
01032   */
01033 HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
01034 {
01035   uint32_t datetmpreg;
01036
01037   /* Check the parameters */
01038   assert_param(IS_RTC_FORMAT(Format));
01039
01040   /* Get the DR register */
01041   datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK);
01042
01043   /* Fill the structure fields with the read parameters */
01044   sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16U);
01045   sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8U);
01046   sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU));
01047   sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13U);
01048
01049   /* Check the input parameters format */
01050   if(Format == RTC_FORMAT_BIN)
01051   {
01052     /* Convert the date structure parameters to Binary format */
01053     sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);
01054     sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month);
01055     sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date);
01056   }
01057   return HAL_OK;
01058 }
01059
01060 /**
01061   * @}
01062   */
01063
01064 /** @addtogroup RTC_Exported_Functions_Group3
01065  *  @brief   RTC Alarm functions
01066  *
01067 @verbatim
01068  ===============================================================================
01069                  ##### RTC Alarm functions #####
01070  ===============================================================================
01071
01072  [..] This section provides functions allowing to configure Alarm feature
01073
01074 @endverbatim
01075   * @{
01076   */
01077 /**
01078   * @brief  Set the specified RTC Alarm.
01079   * @param hrtc RTC handle
01080   * @param sAlarm Pointer to Alarm structure
01081   * @param Format Specifies the format of the entered parameters.
01082   *          This parameter can be one of the following values:
01083   *             @arg RTC_FORMAT_BIN: Binary data format
01084   *             @arg RTC_FORMAT_BCD: BCD data format
01085   * @retval HAL status
01086   */
01087 HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
01088 {
01089   uint32_t tickstart;
01090   uint32_t tmpreg, subsecondtmpreg;
01091
01092   /* Check the parameters */
01093   assert_param(IS_RTC_FORMAT(Format));
01094   assert_param(IS_RTC_ALARM(sAlarm->Alarm));
01095   assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
01096   assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
01097   assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
01098   assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
01099
01100   /* Process Locked */
01101   __HAL_LOCK(hrtc);
01102
01103   hrtc->State = HAL_RTC_STATE_BUSY;
01104
01105   if(Format == RTC_FORMAT_BIN)
01106   {
01107     if((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
01108     {
01109       assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
01110       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
01111     }
01112     else
01113     {
01114       sAlarm->AlarmTime.TimeFormat = 0x00U;
01115       assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
01116     }
01117     assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
01118     assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
01119
01120     if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
01121     {
01122       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
01123     }
01124     else
01125     {
01126       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
01127     }
01128
01129     tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \
01130               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \
01131               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
01132               ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
01133               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \
01134               ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
01135               ((uint32_t)sAlarm->AlarmMask));
01136   }
01137   else
01138   {
01139     if((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
01140     {
01141       assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
01142       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
01143     }
01144     else
01145     {
01146       sAlarm->AlarmTime.TimeFormat = 0x00U;
01147       assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
01148     }
01149
01150     assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
01151     assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
01152
01153     if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
01154     {
01155       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
01156     }
01157     else
01158     {
01159       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
01160     }
01161
01162     tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \
01163               ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \
01164               ((uint32_t) sAlarm->AlarmTime.Seconds) | \
01165               ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
01166               ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \
01167               ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
01168               ((uint32_t)sAlarm->AlarmMask));
01169   }
01170
01171   /* Configure the Alarm A or Alarm B Sub Second registers */
01172   subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
01173
01174   /* Disable the write protection for RTC registers */
01175   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01176
01177   /* Configure the Alarm register */
01178   if(sAlarm->Alarm == RTC_ALARM_A)
01179   {
01180     /* Disable the Alarm A interrupt */
01181     __HAL_RTC_ALARMA_DISABLE(hrtc);
01182
01183     /* In case of interrupt mode is used, the interrupt source must disabled */
01184     __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
01185
01186     tickstart = HAL_GetTick();
01187     /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
01188     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U)
01189     {
01190       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01191       {
01192         /* Enable the write protection for RTC registers */
01193         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01194
01195         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01196
01197         /* Process Unlocked */
01198         __HAL_UNLOCK(hrtc);
01199
01200         return HAL_TIMEOUT;
01201       }
01202     }
01203
01204     hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
01205     /* Configure the Alarm A Sub Second register */
01206     hrtc->Instance->ALRMASSR = subsecondtmpreg;
01207     /* Configure the Alarm state: Enable Alarm */
01208     __HAL_RTC_ALARMA_ENABLE(hrtc);
01209   }
01210   else
01211   {
01212     /* Disable the Alarm B interrupt */
01213     __HAL_RTC_ALARMB_DISABLE(hrtc);
01214
01215     /* In case of interrupt mode is used, the interrupt source must disabled */
01216     __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);
01217
01218     tickstart = HAL_GetTick();
01219     /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
01220     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U)
01221     {
01222       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01223       {
01224         /* Enable the write protection for RTC registers */
01225         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01226
01227         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01228
01229         /* Process Unlocked */
01230         __HAL_UNLOCK(hrtc);
01231
01232         return HAL_TIMEOUT;
01233       }
01234     }
01235
01236     hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
01237     /* Configure the Alarm B Sub Second register */
01238     hrtc->Instance->ALRMBSSR = subsecondtmpreg;
01239     /* Configure the Alarm state: Enable Alarm */
01240     __HAL_RTC_ALARMB_ENABLE(hrtc);
01241   }
01242
01243   /* Enable the write protection for RTC registers */
01244   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01245
01246   /* Change RTC state */
01247   hrtc->State = HAL_RTC_STATE_READY;
01248
01249   /* Process Unlocked */
01250   __HAL_UNLOCK(hrtc);
01251
01252   return HAL_OK;
01253 }
01254
01255 /**
01256   * @brief  Set the specified RTC Alarm with Interrupt.
01257   * @param hrtc RTC handle
01258   * @param sAlarm Pointer to Alarm structure
01259   * @param Format Specifies the format of the entered parameters.
01260   *          This parameter can be one of the following values:
01261   *             @arg RTC_FORMAT_BIN: Binary data format
01262   *             @arg RTC_FORMAT_BCD: BCD data format
01263   * @note   The Alarm register can only be written when the corresponding Alarm
01264   *         is disabled (Use the HAL_RTC_DeactivateAlarm()).
01265   * @note   The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
01266   * @retval HAL status
01267   */
01268 HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
01269 {
01270   uint32_t tickstart;
01271   uint32_t tmpreg, subsecondtmpreg;
01272
01273   /* Check the parameters */
01274   assert_param(IS_RTC_FORMAT(Format));
01275   assert_param(IS_RTC_ALARM(sAlarm->Alarm));
01276   assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
01277   assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
01278   assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
01279   assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
01280
01281   /* Process Locked */
01282   __HAL_LOCK(hrtc);
01283
01284   hrtc->State = HAL_RTC_STATE_BUSY;
01285
01286   if(Format == RTC_FORMAT_BIN)
01287   {
01288     if((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
01289     {
01290       assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
01291       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
01292     }
01293     else
01294     {
01295       sAlarm->AlarmTime.TimeFormat = 0x00U;
01296       assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
01297     }
01298     assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
01299     assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
01300
01301     if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
01302     {
01303       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
01304     }
01305     else
01306     {
01307       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
01308     }
01309     tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \
01310               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \
01311               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
01312               ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
01313               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \
01314               ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
01315               ((uint32_t)sAlarm->AlarmMask));
01316   }
01317   else
01318   {
01319     if((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
01320     {
01321       assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
01322       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
01323     }
01324     else
01325     {
01326       sAlarm->AlarmTime.TimeFormat = 0x00U;
01327       assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
01328     }
01329
01330     assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
01331     assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
01332
01333     if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
01334     {
01335       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
01336     }
01337     else
01338     {
01339       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
01340     }
01341     tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \
01342               ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \
01343               ((uint32_t) sAlarm->AlarmTime.Seconds) | \
01344               ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
01345               ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \
01346               ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
01347               ((uint32_t)sAlarm->AlarmMask));
01348   }
01349   /* Configure the Alarm A or Alarm B Sub Second registers */
01350   subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
01351
01352   /* Disable the write protection for RTC registers */
01353   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01354
01355   /* Configure the Alarm register */
01356   if(sAlarm->Alarm == RTC_ALARM_A)
01357   {
01358     /* Disable the Alarm A interrupt */
01359     __HAL_RTC_ALARMA_DISABLE(hrtc);
01360
01361     /* Clear flag alarm A */
01362     __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
01363
01364     tickstart = HAL_GetTick();
01365     /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
01366     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U)
01367     {
01368       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01369       {
01370         /* Enable the write protection for RTC registers */
01371         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01372
01373         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01374
01375         /* Process Unlocked */
01376         __HAL_UNLOCK(hrtc);
01377
01378         return HAL_TIMEOUT;
01379       }
01380     }
01381
01382     hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
01383     /* Configure the Alarm A Sub Second register */
01384     hrtc->Instance->ALRMASSR = subsecondtmpreg;
01385     /* Configure the Alarm state: Enable Alarm */
01386     __HAL_RTC_ALARMA_ENABLE(hrtc);
01387     /* Configure the Alarm interrupt */
01388     __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA);
01389   }
01390   else
01391   {
01392     /* Disable the Alarm B interrupt */
01393     __HAL_RTC_ALARMB_DISABLE(hrtc);
01394
01395     /* Clear flag alarm B */
01396     __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
01397
01398     tickstart = HAL_GetTick();
01399     /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
01400     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U)
01401     {
01402       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01403       {
01404         /* Enable the write protection for RTC registers */
01405         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01406
01407         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01408
01409         /* Process Unlocked */
01410         __HAL_UNLOCK(hrtc);
01411
01412         return HAL_TIMEOUT;
01413       }
01414     }
01415
01416     hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
01417     /* Configure the Alarm B Sub Second register */
01418     hrtc->Instance->ALRMBSSR = subsecondtmpreg;
01419     /* Configure the Alarm state: Enable Alarm */
01420     __HAL_RTC_ALARMB_ENABLE(hrtc);
01421     /* Configure the Alarm interrupt */
01422     __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB);
01423   }
01424
01425   /* RTC Alarm Interrupt Configuration: EXTI configuration */
01426   __HAL_RTC_ALARM_EXTI_ENABLE_IT();
01427
01428   __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
01429
01430   /* Enable the write protection for RTC registers */
01431   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01432
01433   hrtc->State = HAL_RTC_STATE_READY;
01434
01435   /* Process Unlocked */
01436   __HAL_UNLOCK(hrtc);
01437
01438   return HAL_OK;
01439 }
01440
01441 /**
01442   * @brief  Deactivate the specified RTC Alarm.
01443   * @param hrtc RTC handle
01444   * @param Alarm Specifies the Alarm.
01445   *          This parameter can be one of the following values:
01446   *            @arg RTC_ALARM_A:  AlarmA
01447   *            @arg RTC_ALARM_B:  AlarmB
01448   * @retval HAL status
01449   */
01450 HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
01451 {
01452   uint32_t tickstart;
01453
01454   /* Check the parameters */
01455   assert_param(IS_RTC_ALARM(Alarm));
01456
01457   /* Process Locked */
01458   __HAL_LOCK(hrtc);
01459
01460   hrtc->State = HAL_RTC_STATE_BUSY;
01461
01462   /* Disable the write protection for RTC registers */
01463   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01464
01465   if(Alarm == RTC_ALARM_A)
01466   {
01467     /* AlarmA */
01468     __HAL_RTC_ALARMA_DISABLE(hrtc);
01469
01470     /* In case of interrupt mode is used, the interrupt source must disabled */
01471     __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
01472
01473     tickstart = HAL_GetTick();
01474
01475     /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
01476     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U)
01477     {
01478       if( (HAL_GetTick()  - tickstart ) > RTC_TIMEOUT_VALUE)
01479       {
01480         /* Enable the write protection for RTC registers */
01481         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01482
01483         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01484
01485         /* Process Unlocked */
01486         __HAL_UNLOCK(hrtc);
01487
01488         return HAL_TIMEOUT;
01489       }
01490     }
01491   }
01492   else
01493   {
01494     /* AlarmB */
01495     __HAL_RTC_ALARMB_DISABLE(hrtc);
01496
01497     /* In case of interrupt mode is used, the interrupt source must disabled */
01498     __HAL_RTC_ALARM_DISABLE_IT(hrtc,RTC_IT_ALRB);
01499
01500     tickstart = HAL_GetTick();
01501
01502     /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
01503     while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U)
01504     {
01505       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01506       {
01507         /* Enable the write protection for RTC registers */
01508         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01509
01510         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01511
01512         /* Process Unlocked */
01513         __HAL_UNLOCK(hrtc);
01514
01515         return HAL_TIMEOUT;
01516       }
01517     }
01518   }
01519   /* Enable the write protection for RTC registers */
01520   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01521
01522   hrtc->State = HAL_RTC_STATE_READY;
01523
01524   /* Process Unlocked */
01525   __HAL_UNLOCK(hrtc);
01526
01527   return HAL_OK;
01528 }
01529
01530 /**
01531   * @brief  Get the RTC Alarm value and masks.
01532   * @param hrtc RTC handle
01533   * @param sAlarm Pointer to Date structure
01534   * @param Alarm Specifies the Alarm.
01535   *          This parameter can be one of the following values:
01536   *             @arg RTC_ALARM_A: AlarmA
01537   *             @arg RTC_ALARM_B: AlarmB
01538   * @param Format Specifies the format of the entered parameters.
01539   *          This parameter can be one of the following values:
01540   *             @arg RTC_FORMAT_BIN: Binary data format
01541   *             @arg RTC_FORMAT_BCD: BCD data format
01542   * @retval HAL status
01543   */
01544 HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
01545 {
01546   uint32_t tmpreg, subsecondtmpreg;
01547
01548   /* Check the parameters */
01549   assert_param(IS_RTC_FORMAT(Format));
01550   assert_param(IS_RTC_ALARM(Alarm));
01551
01552   if(Alarm == RTC_ALARM_A)
01553   {
01554     /* AlarmA */
01555     sAlarm->Alarm = RTC_ALARM_A;
01556
01557     tmpreg = (uint32_t)(hrtc->Instance->ALRMAR);
01558     subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS);
01559
01560 /* Fill the structure with the read parameters */
01561   sAlarm->AlarmTime.Hours = (uint8_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16U);
01562   sAlarm->AlarmTime.Minutes = (uint8_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8U);
01563   sAlarm->AlarmTime.Seconds = (uint8_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
01564   sAlarm->AlarmTime.TimeFormat = (uint8_t)((tmpreg & RTC_ALRMAR_PM) >> 16U);
01565   sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
01566   sAlarm->AlarmDateWeekDay = (uint8_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24U);
01567   sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
01568   sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
01569   }
01570   else
01571   {
01572     sAlarm->Alarm = RTC_ALARM_B;
01573
01574     tmpreg = (uint32_t)(hrtc->Instance->ALRMBR);
01575     subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS);
01576
01577   /* Fill the structure with the read parameters */
01578   sAlarm->AlarmTime.Hours = (uint8_t)((tmpreg & (RTC_ALRMBR_HT | RTC_ALRMBR_HU)) >> 16U);
01579   sAlarm->AlarmTime.Minutes = (uint8_t)((tmpreg & (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU)) >> 8U);
01580   sAlarm->AlarmTime.Seconds = (uint8_t)(tmpreg & (RTC_ALRMBR_ST | RTC_ALRMBR_SU));
01581   sAlarm->AlarmTime.TimeFormat = (uint8_t)((tmpreg & RTC_ALRMBR_PM) >> 16U);
01582   sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
01583   sAlarm->AlarmDateWeekDay = (uint8_t)((tmpreg & (RTC_ALRMBR_DT | RTC_ALRMBR_DU)) >> 24U);
01584   sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMBR_WDSEL);
01585   sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
01586  }
01587
01588   if(Format == RTC_FORMAT_BIN)
01589   {
01590     sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
01591     sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);
01592     sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds);
01593     sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
01594   }
01595
01596   return HAL_OK;
01597 }
01598
01599 /**
01600   * @brief  Handle Alarm interrupt request.
01601   * @param hrtc RTC handle
01602   * @retval None
01603   */
01604 void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
01605 {
01606   /* Get the AlarmA interrupt source enable status */
01607   if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != 0U)
01608   {
01609     /* Get the pending status of the AlarmA Interrupt */
01610     if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != 0U)
01611     {
01612       /* AlarmA callback */
01613 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01614       hrtc->AlarmAEventCallback(hrtc);
01615 #else
01616       HAL_RTC_AlarmAEventCallback(hrtc);
01617 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
01618
01619       /* Clear the AlarmA interrupt pending bit */
01620       __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
01621     }
01622   }
01623
01624   /* Get the AlarmB interrupt source enable status */
01625   if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != 0U)
01626   {
01627     /* Get the pending status of the AlarmB Interrupt */
01628     if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != 0U)
01629     {
01630       /* AlarmB callback */
01631 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01632       hrtc->AlarmBEventCallback(hrtc);
01633 #else
01634       HAL_RTCEx_AlarmBEventCallback(hrtc);
01635 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
01636
01637       /* Clear the AlarmB interrupt pending bit */
01638       __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
01639     }
01640   }
01641   /* Clear the EXTI's line Flag for RTC Alarm */
01642   __HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
01643
01644   /* Change RTC state */
01645   hrtc->State = HAL_RTC_STATE_READY;
01646 }
01647
01648 /**
01649   * @brief  Alarm A callback.
01650   * @param hrtc RTC handle
01651   * @retval None
01652   */
01653 __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
01654 {
01655   /* Prevent unused argument(s) compilation warning */
01656   UNUSED(hrtc);
01657
01658   /* NOTE : This function should not be modified, when the callback is needed,
01659             the HAL_RTC_AlarmAEventCallback could be implemented in the user file
01660    */
01661 }
01662
01663 /**
01664   * @brief  Handle AlarmA Polling request.
01665   * @param hrtc RTC handle
01666   * @param Timeout Timeout duration
01667   * @retval HAL status
01668   */
01669 HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
01670 {
01671
01672   uint32_t tickstart = HAL_GetTick();
01673
01674   while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == 0U)
01675   {
01676     if(Timeout != HAL_MAX_DELAY)
01677     {
01678       if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
01679       {
01680         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01681         return HAL_TIMEOUT;
01682       }
01683     }
01684   }
01685
01686   /* Clear the Alarm interrupt pending bit */
01687   __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
01688
01689   /* Change RTC state */
01690   hrtc->State = HAL_RTC_STATE_READY;
01691
01692   return HAL_OK;
01693 }
01694
01695 /**
01696   * @}
01697   */
01698
01699 /** @addtogroup RTC_Exported_Functions_Group4
01700  *  @brief   Peripheral Control functions
01701  *
01702 @verbatim
01703  ===============================================================================
01704                      ##### Peripheral Control functions #####
01705  ===============================================================================
01706     [..]
01707     This subsection provides functions allowing to
01708       (+) Wait for RTC Time and Date Synchronization
01709
01710 @endverbatim
01711   * @{
01712   */
01713
01714 /**
01715   * @brief  Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are
01716   *         synchronized with RTC APB clock.
01717   * @note   The RTC Resynchronization mode is write protected, use the
01718   *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
01719   * @note   To read the calendar through the shadow registers after Calendar
01720   *         initialization, calendar update or after wakeup from low power modes
01721   *         the software must first clear the RSF flag.
01722   *         The software must then wait until it is set again before reading
01723   *         the calendar, which means that the calendar registers have been
01724   *         correctly copied into the RTC_TR and RTC_DR shadow registers.
01725   * @param hrtc RTC handle
01726   * @retval HAL status
01727   */
01728 HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
01729 {
01730   uint32_t tickstart;
01731
01732   /* Clear RSF flag */
01733   hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;
01734
01735   tickstart = HAL_GetTick();
01736
01737   /* Wait the registers to be synchronised */
01738   while((hrtc->Instance->ISR & RTC_ISR_RSF) == 0U)
01739   {
01740     if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01741     {
01742       return HAL_TIMEOUT;
01743     }
01744   }
01745
01746   return HAL_OK;
01747 }
01748
01749 /**
01750   * @}
01751   */
01752
01753 /** @addtogroup RTC_Exported_Functions_Group5
01754  *  @brief   Peripheral State functions
01755  *
01756 @verbatim
01757  ===============================================================================
01758                      ##### Peripheral State functions #####
01759  ===============================================================================
01760     [..]
01761     This subsection provides functions allowing to
01762       (+) Get RTC state
01763
01764 @endverbatim
01765   * @{
01766   */
01767 /**
01768   * @brief  Return the RTC handle state.
01769   * @param hrtc RTC handle
01770   * @retval HAL state
01771   */
01772 HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
01773 {
01774   /* Return RTC handle state */
01775   return hrtc->State;
01776 }
01777
01778 /**
01779   * @}
01780   */
01781 /**
01782   * @}
01783   */
01784
01785 /** @addtogroup RTC_Private_Functions
01786   * @{
01787   */
01788 /**
01789   * @brief  Enter the RTC Initialization mode.
01790   * @note   The RTC Initialization mode is write protected, use the
01791   *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
01792   * @param hrtc RTC handle
01793   * @retval HAL status
01794   */
01795 HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
01796 {
01797   uint32_t tickstart;
01798
01799   /* Check if the Initialization mode is set */
01800   if((hrtc->Instance->ISR & RTC_ISR_INITF) == 0U)
01801   {
01802     /* Set the Initialization mode */
01803     hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
01804
01805     tickstart = HAL_GetTick();
01806     /* Wait till RTC is in INIT state and if Time out is reached exit */
01807     while((hrtc->Instance->ISR & RTC_ISR_INITF) == 0U)
01808     {
01809       if((HAL_GetTick()  - tickstart ) > RTC_TIMEOUT_VALUE)
01810       {
01811         return HAL_TIMEOUT;
01812       }
01813     }
01814   }
01815
01816   return HAL_OK;
01817 }
01818
01819
01820 /**
01821   * @brief  Convert a 2 digit decimal to BCD format.
01822   * @param Value Byte to be converted
01823   * @retval Converted byte
01824   */
01825 uint8_t RTC_ByteToBcd2(uint8_t Value)
01826 {
01827   uint32_t bcdhigh = 0U;
01828   uint8_t Param = Value;
01829
01830   while(Param >= 10U)
01831   {
01832     bcdhigh++;
01833     Param -= 10U;
01834   }
01835
01836   return  ((uint8_t)(bcdhigh << 4U) | Param);
01837 }
01838
01839 /**
01840   * @brief  Convert from 2 digit BCD to Binary.
01841   * @param Value BCD value to be converted
01842   * @retval Converted word
01843   */
01844 uint8_t RTC_Bcd2ToByte(uint8_t Value)
01845 {
01846   uint32_t tmp;
01847   tmp = (((uint32_t)Value & 0xF0U) >> 4U) * 10U;
01848   return (uint8_t)(tmp + ((uint32_t)Value & 0x0FU));
01849 }
01850
01851 /**
01852   * @}
01853   */
01854
01855 #endif /* HAL_RTC_MODULE_ENABLED */
01856 /**
01857   * @}
01858   */
01859
01860 /**
01861   * @}
01862   */
01863
01864 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:35 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_rtc.h Source File

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stm32wbxx_hal_rtc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_rtc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of RTC HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_RTC_H
00022 #define STM32WBxx_HAL_RTC_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 /* Include low level driver */
00032 #include "stm32wbxx_ll_exti.h"
00033
00034 /** @addtogroup STM32WBxx_HAL_Driver
00035   * @{
00036   */
00037
00038 /** @defgroup RTC RTC
00039   * @{
00040   */
00041
00042 /* Exported types ------------------------------------------------------------*/
00043 /** @defgroup RTC_Exported_Types RTC Exported Types
00044   * @{
00045   */
00046
00047 /**
00048   * @brief  HAL State structures definition
00049   */
00050 typedef enum
00051 {
00052   HAL_RTC_STATE_RESET             = 0x00U,  /*!< RTC not yet initialized or disabled */
00053   HAL_RTC_STATE_READY             = 0x01U,  /*!< RTC initialized and ready for use   */
00054   HAL_RTC_STATE_BUSY              = 0x02U,  /*!< RTC process is ongoing              */
00055   HAL_RTC_STATE_TIMEOUT           = 0x03U,  /*!< RTC timeout state                   */
00056   HAL_RTC_STATE_ERROR             = 0x04U   /*!< RTC error state                     */
00057
00058 }HAL_RTCStateTypeDef;
00059
00060 /**
00061   * @brief  RTC Configuration Structure definition
00062   */
00063 typedef struct
00064 {
00065   uint32_t HourFormat;      /*!< Specifies the RTC Hour Format.
00066                                  This parameter can be a value of @ref RTC_Hour_Formats */
00067
00068   uint32_t AsynchPrediv;    /*!< Specifies the RTC Asynchronous Predivider value.
00069                                  This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
00070
00071   uint32_t SynchPrediv;     /*!< Specifies the RTC Synchronous Predivider value.
00072                                  This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
00073
00074   uint32_t OutPut;          /*!< Specifies which signal will be routed to the RTC output.
00075                                  This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
00076
00077   uint32_t OutPutRemap;    /*!< Specifies the remap for RTC output.
00078                                  This parameter can be a value of @ref  RTC_Output_ALARM_OUT_Remap */
00079
00080   uint32_t OutPutPolarity;  /*!< Specifies the polarity of the output signal.
00081                                  This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
00082
00083   uint32_t OutPutType;      /*!< Specifies the RTC Output Pin mode.
00084                                  This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
00085 }RTC_InitTypeDef;
00086
00087 /**
00088   * @brief  RTC Time structure definition
00089   */
00090 typedef struct
00091 {
00092   uint8_t Hours;            /*!< Specifies the RTC Time Hour.
00093                                  This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
00094                                  This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
00095
00096   uint8_t Minutes;          /*!< Specifies the RTC Time Minutes.
00097                                  This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
00098
00099   uint8_t Seconds;          /*!< Specifies the RTC Time Seconds.
00100                                  This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
00101
00102   uint8_t TimeFormat;       /*!< Specifies the RTC AM/PM Time.
00103                                  This parameter can be a value of @ref RTC_AM_PM_Definitions */
00104
00105   uint32_t SubSeconds;     /*!< Specifies the RTC_SSR RTC Sub Second register content.
00106                                  This parameter corresponds to a time unit range between [0-1] Second
00107                                  with [1 Sec / SecondFraction +1] granularity */
00108
00109   uint32_t SecondFraction;  /*!< Specifies the range or granularity of Sub Second register content
00110                                  corresponding to Synchronous pre-scaler factor value (PREDIV_S)
00111                                  This parameter corresponds to a time unit range between [0-1] Second
00112                                  with [1 Sec / SecondFraction +1] granularity.
00113                                  This field will be used only by HAL_RTC_GetTime function */
00114
00115   uint32_t DayLightSaving;  /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment.
00116                                  This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
00117
00118   uint32_t StoreOperation;  /*!< Specifies RTC_StoreOperation value to be written in the BCK bit
00119                                  in CR register to store the operation.
00120                                  This parameter can be a value of @ref RTC_StoreOperation_Definitions */
00121 }RTC_TimeTypeDef;
00122
00123 /**
00124   * @brief  RTC Date structure definition
00125   */
00126 typedef struct
00127 {
00128   uint8_t WeekDay;  /*!< Specifies the RTC Date WeekDay.
00129                          This parameter can be a value of @ref RTC_WeekDay_Definitions */
00130
00131   uint8_t Month;    /*!< Specifies the RTC Date Month (in BCD format).
00132                          This parameter can be a value of @ref RTC_Month_Date_Definitions */
00133
00134   uint8_t Date;     /*!< Specifies the RTC Date.
00135                          This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
00136
00137   uint8_t Year;     /*!< Specifies the RTC Date Year.
00138                          This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
00139
00140 }RTC_DateTypeDef;
00141
00142 /**
00143   * @brief  RTC Alarm structure definition
00144   */
00145 typedef struct
00146 {
00147   RTC_TimeTypeDef AlarmTime;     /*!< Specifies the RTC Alarm Time members */
00148
00149   uint32_t AlarmMask;            /*!< Specifies the RTC Alarm Masks.
00150                                       This parameter can be a value of @ref RTC_AlarmMask_Definitions */
00151
00152   uint32_t AlarmSubSecondMask;   /*!< Specifies the RTC Alarm SubSeconds Masks.
00153                                       This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
00154
00155   uint32_t AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on Date or WeekDay.
00156                                      This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
00157
00158   uint8_t AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Date/WeekDay.
00159                                       If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
00160                                       If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
00161
00162   uint32_t Alarm;                /*!< Specifies the alarm .
00163                                       This parameter can be a value of @ref RTC_Alarms_Definitions */
00164 }RTC_AlarmTypeDef;
00165
00166 /**
00167   * @brief  RTC Handle Structure definition
00168   */
00169 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
00170 typedef struct __RTC_HandleTypeDef
00171 #else
00172 typedef struct
00173 #endif
00174 {
00175   RTC_TypeDef               *Instance;  /*!< Register base address    */
00176
00177   RTC_InitTypeDef           Init;       /*!< RTC required parameters  */
00178
00179   HAL_LockTypeDef           Lock;       /*!< RTC locking object       */
00180
00181   __IO HAL_RTCStateTypeDef  State;      /*!< Time communication state */
00182
00183 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
00184   void  (* AlarmAEventCallback)      ( struct __RTC_HandleTypeDef * hrtc);  /*!< RTC Alarm A Event callback         */
00185
00186   void  (* AlarmBEventCallback)      ( struct __RTC_HandleTypeDef * hrtc);  /*!< RTC Alarm B Event callback         */
00187
00188   void  (* TimeStampEventCallback)   ( struct __RTC_HandleTypeDef * hrtc);  /*!< RTC TimeStamp Event callback       */
00189
00190   void  (* WakeUpTimerEventCallback) ( struct __RTC_HandleTypeDef * hrtc);  /*!< RTC WakeUpTimer Event callback     */
00191
00192   void  (* Tamper1EventCallback)     ( struct __RTC_HandleTypeDef * hrtc);  /*!< RTC Tamper 1 Event callback        */
00193
00194   void  (* Tamper2EventCallback)     ( struct __RTC_HandleTypeDef * hrtc);  /*!< RTC Tamper 2 Event callback        */
00195
00196   void  (* Tamper3EventCallback)     ( struct __RTC_HandleTypeDef * hrtc);  /*!< RTC Tamper 3 Event callback        */
00197
00198   void  (* MspInitCallback)         ( struct __RTC_HandleTypeDef * hrtc);   /*!< RTC Msp Init callback              */
00199
00200   void  (* MspDeInitCallback)       ( struct __RTC_HandleTypeDef * hrtc);   /*!< RTC Msp DeInit callback            */
00201
00202 #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
00203
00204 }RTC_HandleTypeDef;
00205
00206 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
00207 /**
00208   * @brief  HAL LPTIM Callback ID enumeration definition
00209   */
00210 typedef enum
00211 {
00212   HAL_RTC_ALARM_A_EVENT_CB_ID           = 0x00U,    /*!< RTC Alarm A Event Callback ID      */
00213   HAL_RTC_ALARM_B_EVENT_CB_ID           = 0x01U,    /*!< RTC Alarm B Event Callback ID      */
00214   HAL_RTC_TIMESTAMP_EVENT_CB_ID         = 0x02U,    /*!< RTC TimeStamp Event Callback ID    */
00215   HAL_RTC_WAKEUPTIMER_EVENT_CB_ID       = 0x03U,    /*!< RTC WakeUp Timer Event Callback ID */
00216 #if defined(RTC_TAMPER1_SUPPORT)
00217   HAL_RTC_TAMPER1_EVENT_CB_ID           = 0x04U,    /*!< RTC Tamper 1 Callback ID           */
00218 #endif
00219   HAL_RTC_TAMPER2_EVENT_CB_ID           = 0x05U,    /*!< RTC Tamper 2 Callback ID           */
00220 #if defined(RTC_TAMPER3_SUPPORT)
00221   HAL_RTC_TAMPER3_EVENT_CB_ID           = 0x06U,    /*!< RTC Tamper 3 Callback ID           */
00222 #endif
00223   HAL_RTC_MSPINIT_CB_ID                 = 0x0EU,    /*!< RTC Msp Init callback ID           */
00224   HAL_RTC_MSPDEINIT_CB_ID               = 0x0FU     /*!< RTC Msp DeInit callback ID         */
00225 }HAL_RTC_CallbackIDTypeDef;
00226
00227 /**
00228   * @brief  HAL RTC Callback pointer definition
00229   */
00230 typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to an RTC callback function */
00231 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
00232
00233 /**
00234   * @}
00235   */
00236
00237 /* Exported constants --------------------------------------------------------*/
00238 /** @defgroup RTC_Exported_Constants RTC Exported Constants
00239   * @{
00240   */
00241
00242 /** @defgroup RTC_Hour_Formats RTC Hour Formats
00243   * @{
00244   */
00245 #define RTC_HOURFORMAT_24              ((uint32_t)0x00000000U)
00246 #define RTC_HOURFORMAT_12              ((uint32_t)RTC_CR_FMT)
00247
00248 /**
00249   * @}
00250   */
00251
00252
00253 /** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
00254   * @{
00255   */
00256 #define RTC_OUTPUT_POLARITY_HIGH       ((uint32_t)0x00000000U)
00257 #define RTC_OUTPUT_POLARITY_LOW        ((uint32_t)RTC_CR_POL)
00258
00259 /**
00260   * @}
00261   */
00262
00263 /** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
00264   * @{
00265   */
00266 #define RTC_OUTPUT_TYPE_OPENDRAIN      ((uint32_t)0x00000000U)
00267 #define RTC_OUTPUT_TYPE_PUSHPULL       ((uint32_t)RTC_OR_ALARMOUTTYPE)
00268
00269 /**
00270   * @}
00271   */
00272
00273 /** @defgroup RTC_Output_ALARM_OUT_Remap RTC Output ALARM OUT Remap
00274   * @{
00275   */
00276 #define RTC_OUTPUT_REMAP_NONE              ((uint32_t)0x00000000U)
00277 #define RTC_OUTPUT_REMAP_POS1              ((uint32_t)RTC_OR_OUT_RMP)
00278 /**
00279   * @}
00280   */
00281
00282 /** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
00283   * @{
00284   */
00285 #define RTC_HOURFORMAT12_AM            ((uint8_t)0x00U)
00286 #define RTC_HOURFORMAT12_PM            ((uint8_t)0x40U)
00287
00288 /**
00289   * @}
00290   */
00291
00292 /** @defgroup RTC_DayLightSaving_Definitions RTC DayLightSaving Definitions
00293   * @{
00294   */
00295 #define RTC_DAYLIGHTSAVING_SUB1H       ((uint32_t)RTC_CR_SUB1H)
00296 #define RTC_DAYLIGHTSAVING_ADD1H       ((uint32_t)RTC_CR_ADD1H)
00297 #define RTC_DAYLIGHTSAVING_NONE        ((uint32_t)0x00000000U)
00298
00299 /**
00300   * @}
00301   */
00302
00303 /** @defgroup RTC_StoreOperation_Definitions RTC StoreOperation Definitions
00304   * @{
00305   */
00306 #define RTC_STOREOPERATION_RESET        ((uint32_t)0x00000000U)
00307 #define RTC_STOREOPERATION_SET          ((uint32_t)RTC_CR_BKP)
00308
00309 /**
00310   * @}
00311   */
00312
00313 /** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
00314   * @{
00315   */
00316 #define RTC_FORMAT_BIN   ((uint32_t)0x000000000U)
00317 #define RTC_FORMAT_BCD   ((uint32_t)0x000000001U)
00318
00319 /**
00320   * @}
00321   */
00322
00323 /** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
00324   * @{
00325   */
00326
00327 /* Coded in BCD format */
00328 #define RTC_MONTH_JANUARY              ((uint8_t)0x01U)
00329 #define RTC_MONTH_FEBRUARY             ((uint8_t)0x02U)
00330 #define RTC_MONTH_MARCH                ((uint8_t)0x03U)
00331 #define RTC_MONTH_APRIL                ((uint8_t)0x04U)
00332 #define RTC_MONTH_MAY                  ((uint8_t)0x05U)
00333 #define RTC_MONTH_JUNE                 ((uint8_t)0x06U)
00334 #define RTC_MONTH_JULY                 ((uint8_t)0x07U)
00335 #define RTC_MONTH_AUGUST               ((uint8_t)0x08U)
00336 #define RTC_MONTH_SEPTEMBER            ((uint8_t)0x09U)
00337 #define RTC_MONTH_OCTOBER              ((uint8_t)0x10U)
00338 #define RTC_MONTH_NOVEMBER             ((uint8_t)0x11U)
00339 #define RTC_MONTH_DECEMBER             ((uint8_t)0x12U)
00340
00341 /**
00342   * @}
00343   */
00344
00345 /** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
00346   * @{
00347   */
00348 #define RTC_WEEKDAY_MONDAY             ((uint8_t)0x01U)
00349 #define RTC_WEEKDAY_TUESDAY            ((uint8_t)0x02U)
00350 #define RTC_WEEKDAY_WEDNESDAY          ((uint8_t)0x03U)
00351 #define RTC_WEEKDAY_THURSDAY           ((uint8_t)0x04U)
00352 #define RTC_WEEKDAY_FRIDAY             ((uint8_t)0x05U)
00353 #define RTC_WEEKDAY_SATURDAY           ((uint8_t)0x06U)
00354 #define RTC_WEEKDAY_SUNDAY             ((uint8_t)0x07U)
00355
00356 /**
00357   * @}
00358   */
00359
00360 /** @defgroup RTC_AlarmDateWeekDay_Definitions RTC AlarmDateWeekDay Definitions
00361   * @{
00362   */
00363 #define RTC_ALARMDATEWEEKDAYSEL_DATE      ((uint32_t)0x00000000U)
00364 #define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY   RTC_ALRMAR_WDSEL
00365
00366 /**
00367   * @}
00368   */
00369
00370 /** @defgroup RTC_AlarmMask_Definitions RTC AlarmMask Definitions
00371   * @{
00372   */
00373 #define RTC_ALARMMASK_NONE             ((uint32_t)0x00000000U)
00374 #define RTC_ALARMMASK_DATEWEEKDAY       RTC_ALRMAR_MSK4
00375 #define RTC_ALARMMASK_HOURS             RTC_ALRMAR_MSK3
00376 #define RTC_ALARMMASK_MINUTES           RTC_ALRMAR_MSK2
00377 #define RTC_ALARMMASK_SECONDS           RTC_ALRMAR_MSK1
00378 #define RTC_ALARMMASK_ALL               ((uint32_t) (RTC_ALARMMASK_NONE        | \
00379                                                      RTC_ALARMMASK_DATEWEEKDAY | \
00380                                                      RTC_ALARMMASK_HOURS       | \
00381                                                      RTC_ALARMMASK_MINUTES     | \
00382                                                      RTC_ALARMMASK_SECONDS))
00383
00384 /**
00385   * @}
00386   */
00387
00388 /** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
00389   * @{
00390   */
00391 #define RTC_ALARM_A                       RTC_CR_ALRAE
00392 #define RTC_ALARM_B                       RTC_CR_ALRBE
00393
00394 /**
00395   * @}
00396   */
00397
00398
00399   /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
00400   * @{
00401   */
00402 #define RTC_ALARMSUBSECONDMASK_ALL        ((uint32_t)0x00000000U)                                                                 /*!< All Alarm SS fields are masked.
00403                                                                                                                                     There is no comparison on sub seconds
00404                                                                                                                                     for Alarm */
00405 #define RTC_ALARMSUBSECONDMASK_SS14_1      RTC_ALRMASSR_MASKSS_0                                                                 /*!< SS[14:1] are don't care in Alarm
00406                                                                                                                                     comparison. Only SS[0] is compared.    */
00407 #define RTC_ALARMSUBSECONDMASK_SS14_2      RTC_ALRMASSR_MASKSS_1                                                                 /*!< SS[14:2] are don't care in Alarm
00408                                                                                                                                      comparison. Only SS[1:0] are compared  */
00409 #define RTC_ALARMSUBSECONDMASK_SS14_3      ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1))                          /*!< SS[14:3] are don't care in Alarm
00410                                                                                                                                      comparison. Only SS[2:0] are compared  */
00411 #define RTC_ALARMSUBSECONDMASK_SS14_4      RTC_ALRMASSR_MASKSS_2                                                                 /*!< SS[14:4] are don't care in Alarm
00412                                                                                                                                      comparison. Only SS[3:0] are compared  */
00413 #define RTC_ALARMSUBSECONDMASK_SS14_5      ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2))                          /*!< SS[14:5] are don't care in Alarm
00414                                                                                                                                       comparison. Only SS[4:0] are compared  */
00415 #define RTC_ALARMSUBSECONDMASK_SS14_6      ((uint32_t) (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2))                          /*!< SS[14:6] are don't care in Alarm
00416                                                                                                                                       comparison. Only SS[5:0] are compared  */
00417 #define RTC_ALARMSUBSECONDMASK_SS14_7      ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2))  /*!< SS[14:7] are don't care in Alarm
00418                                                                                                                                 `     comparison. Only SS[6:0] are compared  */
00419 #define RTC_ALARMSUBSECONDMASK_SS14_8      RTC_ALRMASSR_MASKSS_3                                                                 /*!< SS[14:8] are don't care in Alarm
00420                                                                                                                                       comparison. Only SS[7:0] are compared  */
00421 #define RTC_ALARMSUBSECONDMASK_SS14_9      ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3))                          /*!< SS[14:9] are don't care in Alarm
00422                                                                                                                                       comparison. Only SS[8:0] are compared  */
00423 #define RTC_ALARMSUBSECONDMASK_SS14_10     ((uint32_t) (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3))                          /*!< SS[14:10] are don't care in Alarm
00424                                                                                                                                       comparison. Only SS[9:0] are compared  */
00425 #define RTC_ALARMSUBSECONDMASK_SS14_11     ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3))  /*!< SS[14:11] are don't care in Alarm
00426                                                                                                                                       comparison. Only SS[10:0] are compared */
00427 #define RTC_ALARMSUBSECONDMASK_SS14_12     ((uint32_t) (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3))                          /*!< SS[14:12] are don't care in Alarm
00428                                                                                                                                       comparison.Only SS[11:0] are compared  */
00429 #define RTC_ALARMSUBSECONDMASK_SS14_13     ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3))  /*!< SS[14:13] are don't care in Alarm
00430                                                                                                                                       comparison. Only SS[12:0] are compared */
00431 #define RTC_ALARMSUBSECONDMASK_SS14        ((uint32_t) (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3))  /*!< SS[14] is don't care in Alarm
00432                                                                                                                                       comparison.Only SS[13:0] are compared  */
00433 #define RTC_ALARMSUBSECONDMASK_NONE        RTC_ALRMASSR_MASKSS                                                                   /*!< SS[14:0] are compared and must match
00434                                                                                                                                       to activate alarm. */
00435 /**
00436   * @}
00437   */
00438
00439 /** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
00440   * @{
00441   */
00442 #define RTC_IT_TS                         ((uint32_t)RTC_CR_TSIE)        /*!< Enable Timestamp Interrupt    */
00443 #define RTC_IT_WUT                        ((uint32_t)RTC_CR_WUTIE)       /*!< Enable Wakeup timer Interrupt */
00444 #define RTC_IT_ALRA                       ((uint32_t)RTC_CR_ALRAIE)      /*!< Enable Alarm A Interrupt      */
00445 #define RTC_IT_ALRB                       ((uint32_t)RTC_CR_ALRBIE)      /*!< Enable Alarm B Interrupt      */
00446 #define RTC_IT_TAMP                       ((uint32_t)RTC_TAMPCR_TAMPIE)  /*!< Enable all Tamper Interrupt   */
00447 #if defined(RTC_TAMPER1_SUPPORT)
00448 #define RTC_IT_TAMP1                      ((uint32_t)RTC_TAMPCR_TAMP1IE) /*!< Enable Tamper 1 Interrupt     */
00449 #endif
00450 #define RTC_IT_TAMP2                      ((uint32_t)RTC_TAMPCR_TAMP2IE) /*!< Enable Tamper 2 Interrupt     */
00451
00452 /**
00453   * @}
00454   */
00455
00456 /** @defgroup RTC_Flags_Definitions RTC Flags Definitions
00457   * @{
00458   */
00459 #define RTC_FLAG_RECALPF                  ((uint32_t)RTC_ISR_RECALPF)
00460 #define RTC_FLAG_TAMP2F                   ((uint32_t)RTC_ISR_TAMP2F)
00461 #if defined(RTC_TAMPER1_SUPPORT)
00462 #define RTC_FLAG_TAMP1F                   ((uint32_t)RTC_ISR_TAMP1F)
00463 #endif
00464 #define RTC_FLAG_TSOVF                    ((uint32_t)RTC_ISR_TSOVF)
00465 #define RTC_FLAG_TSF                      ((uint32_t)RTC_ISR_TSF)
00466 #if defined(RTC_ISR_ITSF)
00467 #define RTC_FLAG_ITSF                     ((uint32_t)RTC_ISR_ITSF)
00468 #endif
00469 #define RTC_FLAG_WUTF                     ((uint32_t)RTC_ISR_WUTF)
00470 #define RTC_FLAG_ALRBF                    ((uint32_t)RTC_ISR_ALRBF)
00471 #define RTC_FLAG_ALRAF                    ((uint32_t)RTC_ISR_ALRAF)
00472 #define RTC_FLAG_INITF                    ((uint32_t)RTC_ISR_INITF)
00473 #define RTC_FLAG_RSF                      ((uint32_t)RTC_ISR_RSF)
00474 #define RTC_FLAG_INITS                    ((uint32_t)RTC_ISR_INITS)
00475 #define RTC_FLAG_SHPF                     ((uint32_t)RTC_ISR_SHPF)
00476 #define RTC_FLAG_WUTWF                    ((uint32_t)RTC_ISR_WUTWF)
00477 #define RTC_FLAG_ALRBWF                   ((uint32_t)RTC_ISR_ALRBWF)
00478 #define RTC_FLAG_ALRAWF                   ((uint32_t)RTC_ISR_ALRAWF)
00479 /**
00480   * @}
00481   */
00482
00483 /**
00484   * @}
00485   */
00486
00487 /* Exported macros -----------------------------------------------------------*/
00488 /** @defgroup RTC_Exported_Macros RTC Exported Macros
00489   * @{
00490   */
00491
00492 /** @brief Reset RTC handle state
00493   * @param __HANDLE__ RTC handle.
00494   * @retval None
00495   */
00496 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
00497 #define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\
00498                                                       (__HANDLE__)->State = HAL_RTC_STATE_RESET;\
00499                                                       (__HANDLE__)->MspInitCallback = NULL;\
00500                                                       (__HANDLE__)->MspDeInitCallback = NULL;\
00501                                                      }while(0)
00502 #else
00503 #define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
00504 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
00505
00506 /**
00507   * @brief  Disable the write protection for RTC registers.
00508   * @param __HANDLE__ specifies the RTC handle.
00509   * @retval None
00510   */
00511 #define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)             \
00512                         do{                                       \
00513                             (__HANDLE__)->Instance->WPR = 0xCAU;   \
00514                             (__HANDLE__)->Instance->WPR = 0x53U;   \
00515                           } while(0U)
00516
00517 /**
00518   * @brief  Enable the write protection for RTC registers.
00519   * @param __HANDLE__ specifies the RTC handle.
00520   * @retval None
00521   */
00522 #define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)              \
00523                         do{                                       \
00524                             (__HANDLE__)->Instance->WPR = 0xFFU;   \
00525                           } while(0U)
00526
00527 /**
00528   * @brief  Enable the RTC ALARMA peripheral.
00529   * @param __HANDLE__ specifies the RTC handle.
00530   * @retval None
00531   */
00532 #define __HAL_RTC_ALARMA_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
00533
00534 /**
00535   * @brief  Disable the RTC ALARMA peripheral.
00536   * @param __HANDLE__ specifies the RTC handle.
00537   * @retval None
00538   */
00539 #define __HAL_RTC_ALARMA_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
00540
00541 /**
00542   * @brief  Enable the RTC ALARMB peripheral.
00543   * @param __HANDLE__ specifies the RTC handle.
00544   * @retval None
00545   */
00546 #define __HAL_RTC_ALARMB_ENABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
00547
00548 /**
00549   * @brief  Disable the RTC ALARMB peripheral.
00550   * @param __HANDLE__ specifies the RTC handle.
00551   * @retval None
00552   */
00553 #define __HAL_RTC_ALARMB_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
00554
00555 /**
00556   * @brief  Enable the RTC Alarm interrupt.
00557   * @param __HANDLE__ specifies the RTC handle.
00558   * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
00559   *          This parameter can be any combination of the following values:
00560   *             @arg RTC_IT_ALRA: Alarm A interrupt
00561   *             @arg RTC_IT_ALRB: Alarm B interrupt
00562   * @retval None
00563   */
00564 #define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
00565
00566 /**
00567   * @brief  Disable the RTC Alarm interrupt.
00568   * @param __HANDLE__ specifies the RTC handle.
00569   * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
00570   *         This parameter can be any combination of the following values:
00571   *            @arg RTC_IT_ALRA: Alarm A interrupt
00572   *            @arg RTC_IT_ALRB: Alarm B interrupt
00573   * @retval None
00574   */
00575 #define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
00576
00577 /**
00578   * @brief  Check whether the specified RTC Alarm interrupt has occurred or not.
00579   * @param __HANDLE__ specifies the RTC handle.
00580   * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
00581   *         This parameter can be:
00582   *            @arg RTC_IT_ALRA: Alarm A interrupt
00583   *            @arg RTC_IT_ALRB: Alarm B interrupt
00584   * @retval None
00585   */
00586 #define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__)  (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) != 0U)? 1U : 0U)
00587
00588 /**
00589   * @brief  Check whether the specified RTC Alarm interrupt has been enabled or not.
00590   * @param __HANDLE__ specifies the RTC handle.
00591   * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
00592   *         This parameter can be:
00593   *            @arg RTC_IT_ALRA: Alarm A interrupt
00594   *            @arg RTC_IT_ALRB: Alarm B interrupt
00595   * @retval None
00596   */
00597 #define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
00598
00599 /**
00600   * @brief  Get the selected RTC Alarm's flag status.
00601   * @param __HANDLE__ specifies the RTC handle.
00602   * @param __FLAG__ specifies the RTC Alarm Flag sources to check.
00603   *         This parameter can be:
00604   *            @arg RTC_FLAG_ALRAF
00605   *            @arg RTC_FLAG_ALRBF
00606   *            @arg RTC_FLAG_ALRAWF
00607   *            @arg RTC_FLAG_ALRBWF
00608   * @retval None
00609   */
00610 #define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)   (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U)
00611
00612 /**
00613   * @brief  Clear the RTC Alarm's pending flags.
00614   * @param __HANDLE__ specifies the RTC handle.
00615   * @param __FLAG__ specifies the RTC Alarm Flag sources to clear.
00616   *          This parameter can be:
00617   *             @arg RTC_FLAG_ALRAF
00618   *             @arg RTC_FLAG_ALRBF
00619   * @retval None
00620   */
00621 #define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)   ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT) | ((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
00622
00623 /**
00624   * @brief  Enable interrupt on the RTC Alarm associated Exti line by core 1.
00625   * @retval None
00626   */
00627 #define __HAL_RTC_ALARM_EXTI_ENABLE_IT()            (EXTI->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
00628
00629 /**
00630   * @brief  Enable interrupt on the RTC Alarm associated Exti line by core 2.
00631   * @retval None
00632   */
00633 #define __HAL_RTC_ALARM_EXTIC2_ENABLE_IT()          (EXTI->C2IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
00634
00635 /**
00636   * @brief  Disable interrupt on the RTC Alarm associated Exti line by core 1.
00637   * @retval None
00638   */
00639 #define __HAL_RTC_ALARM_EXTI_DISABLE_IT()           (EXTI->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00640
00641 /**
00642   * @brief  Disable interrupt on the RTC Alarm associated Exti line by core 2.
00643   * @retval None
00644   */
00645 #define __HAL_RTC_ALARM_EXTIC2_DISABLE_IT()         (EXTI->C2IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00646
00647
00648 /**
00649   * @brief  Enable event on the RTC Alarm associated Exti line by core 1.
00650   * @retval None.
00651   */
00652 #define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT()         (EXTI->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
00653
00654 /**
00655   * @brief  Enable event on the RTC Alarm associated Exti line by core 2.
00656   * @retval None.
00657   */
00658 #define __HAL_RTC_ALARM_EXTIC2_ENABLE_EVENT()        (EXTI->C2EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
00659
00660 /**
00661   * @brief  Disable event on the RTC Alarm associated Exti line by core 1.
00662   * @retval None.
00663   */
00664 #define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT()         (EXTI->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00665
00666 /**
00667   * @brief  Disable event on the RTC Alarm associated Exti line by core 2.
00668   * @retval None.
00669   */
00670 #define __HAL_RTC_ALARM_EXTIC2_DISABLE_EVENT()       (EXTI->C2EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00671
00672 /*----------------------------*/
00673 /**
00674   * @brief  Enable falling edge trigger on the RTC Alarm associated Exti line.
00675   * @retval None.
00676   */
00677 #define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
00678
00679 /**
00680   * @brief  Disable falling edge trigger on the RTC Alarm associated Exti line.
00681   * @retval None.
00682   */
00683 #define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00684
00685 /**
00686   * @brief  Enable rising edge trigger on the RTC Alarm associated Exti line.
00687   * @retval None.
00688   */
00689 #define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
00690
00691 /**
00692   * @brief  Disable rising edge trigger on the RTC Alarm associated Exti line.
00693   * @retval None.
00694   */
00695 #define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
00696
00697
00698
00699 /**
00700   * @brief  Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
00701   * @retval None.
00702   */
00703 #define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE()  do { \
00704                                                              __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();  \
00705                                                              __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \
00706                                                            } while(0U)
00707
00708 /**
00709   * @brief  Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
00710   * @retval None.
00711   */
00712 #define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
00713                                                              __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();  \
00714                                                              __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \
00715                                                            } while(0U)
00716
00717
00718 /**
00719   * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or notby core 1.
00720   * @retval Line Status.
00721   */
00722 #define __HAL_RTC_ALARM_EXTI_GET_FLAG()              (EXTI->PR1 & RTC_EXTI_LINE_ALARM_EVENT)
00723
00724 /**
00725   * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not by core 2.
00726   * @retval Line Status.
00727   */
00728 #define __HAL_RTC_ALARM_EXTIC2_GET_FLAG()            (EXTI->PR2 & RTC_EXTI_LINE_ALARM_EVENT)
00729
00730 /**
00731   * @brief Clear the RTC Alarm associated Exti line flag.
00732   * @retval None.
00733   */
00734 #define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()            (EXTI->PR1 = (RTC_EXTI_LINE_ALARM_EVENT))
00735
00736 /**
00737   * @brief Clear the RTC Alarm associated Exti line flag.
00738   * @retval None.
00739   */
00740 #define __HAL_RTC_ALARM_EXTIC2_CLEAR_FLAG()          (EXTI->PR2 = (RTC_EXTI_LINE_ALARM_EVENT))
00741
00742 /*----------------------------*/
00743 /**
00744   * @brief Generate a Software interrupt on RTC Alarm associated Exti line.
00745   * @retval None.
00746   */
00747 #define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()         (EXTI->SWIER1 |= RTC_EXTI_LINE_ALARM_EVENT)
00748 /*----------------------------*/
00749
00750
00751 /**
00752   * @}
00753   */
00754
00755 /* Include RTC HAL Extended module */
00756 #include "stm32wbxx_hal_rtc_ex.h"
00757
00758 /* Exported functions --------------------------------------------------------*/
00759 /** @defgroup RTC_Exported_Functions RTC Exported Functions
00760   * @{
00761   */
00762
00763 /** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
00764   * @{
00765   */
00766 /* Initialization and de-initialization functions  ****************************/
00767 HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
00768 HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
00769
00770 void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
00771 void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
00772
00773 /* Callbacks Register/UnRegister functions  ***********************************/
00774 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
00775 HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback);
00776 HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID);
00777 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
00778
00779 /**
00780   * @}
00781   */
00782
00783 /** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
00784   * @{
00785   */
00786 /* RTC Time and Date functions ************************************************/
00787 HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
00788 HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
00789 HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
00790 HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
00791 /**
00792   * @}
00793   */
00794
00795 /** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
00796   * @{
00797   */
00798 /* RTC Alarm functions ********************************************************/
00799 HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
00800 HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
00801 HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
00802 HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
00803 void              HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
00804 HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00805 void              HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
00806 /**
00807   * @}
00808   */
00809
00810 /** @defgroup  RTC_Exported_Functions_Group4 Peripheral Control functions
00811   * @{
00812   */
00813 /* Peripheral Control functions ***********************************************/
00814 HAL_StatusTypeDef   HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
00815 /**
00816   * @}
00817   */
00818
00819 /** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions
00820   * @{
00821   */
00822 /* Peripheral State functions *************************************************/
00823 HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
00824 /**
00825   * @}
00826   */
00827
00828 /**
00829   * @}
00830   */
00831
00832 /* Private types -------------------------------------------------------------*/
00833 /* Private variables ---------------------------------------------------------*/
00834 /* Private constants ---------------------------------------------------------*/
00835 /** @defgroup RTC_Private_Constants RTC Private Constants
00836   * @{
00837   */
00838 /* Masks Definition */
00839 #define RTC_TR_RESERVED_MASK  ((uint32_t) (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | \
00840                                            RTC_TR_MNT | RTC_TR_MNU| RTC_TR_ST | \
00841                                            RTC_TR_SU))
00842 #define RTC_DR_RESERVED_MASK  ((uint32_t) (RTC_DR_YT | RTC_DR_YU | RTC_DR_WDU | \
00843                                            RTC_DR_MT | RTC_DR_MU | RTC_DR_DT  | \
00844                                            RTC_DR_DU))
00845 #define RTC_INIT_MASK           ((uint32_t)0xFFFFFFFFU)
00846 #define RTC_RSF_MASK            ((uint32_t)~(RTC_ISR_INIT | RTC_ISR_RSF))
00847
00848 #define RTC_TIMEOUT_VALUE  1000U
00849
00850 #define RTC_EXTI_LINE_ALARM_EVENT             (LL_EXTI_LINE_17) /*!< External interrupt line connected to the RTC Alarm event */
00851
00852 /**
00853   * @}
00854   */
00855
00856 /* Private macros ------------------------------------------------------------*/
00857 /** @defgroup RTC_Private_Macros RTC Private Macros
00858   * @{
00859   */
00860
00861 /** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
00862   * @{
00863   */
00864
00865 #define IS_RTC_HOUR_FORMAT(FORMAT)     (((FORMAT) == RTC_HOURFORMAT_12) || \
00866                                         ((FORMAT) == RTC_HOURFORMAT_24))
00867
00868 #define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
00869                                 ((POL) == RTC_OUTPUT_POLARITY_LOW))
00870
00871 #define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
00872                                   ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
00873
00874 #define IS_RTC_OUTPUT_REMAP(REMAP)   (((REMAP) == RTC_OUTPUT_REMAP_NONE) || \
00875                                       ((REMAP) == RTC_OUTPUT_REMAP_POS1))
00876
00877 #define IS_RTC_HOURFORMAT12(PM)  (((PM) == RTC_HOURFORMAT12_AM) || \
00878                                   ((PM) == RTC_HOURFORMAT12_PM))
00879
00880 #define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
00881                                       ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
00882                                       ((SAVE) == RTC_DAYLIGHTSAVING_NONE))
00883
00884 #define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
00885                                            ((OPERATION) == RTC_STOREOPERATION_SET))
00886
00887 #define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
00888
00889 #define IS_RTC_YEAR(YEAR)              ((YEAR) <= (uint32_t)99U)
00890
00891 #define IS_RTC_MONTH(MONTH)            (((MONTH) >= (uint32_t)1U) && ((MONTH) <= (uint32_t)12U))
00892
00893 #define IS_RTC_DATE(DATE)              (((DATE) >= (uint32_t)1U) && ((DATE) <= (uint32_t)31U))
00894
00895 #define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
00896                                  ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
00897                                  ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
00898                                  ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
00899                                  ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
00900                                  ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
00901                                  ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
00902
00903 #define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t)0U) && ((DATE) <= (uint32_t)31U))
00904
00905 #define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
00906                                                     ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
00907                                                     ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
00908                                                     ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
00909                                                     ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
00910                                                     ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
00911                                                     ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
00912
00913 #define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
00914                                             ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
00915
00916 #define IS_RTC_ALARM_MASK(MASK)  (((MASK) & ~(RTC_ALARMMASK_ALL)) == 0U)
00917
00918 #define IS_RTC_ALARM(ALARM)      (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
00919
00920 #define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS)
00921
00922 #define IS_RTC_ALARM_SUB_SECOND_MASK(MASK)   (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
00923                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
00924                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
00925                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
00926                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
00927                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
00928                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
00929                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
00930                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
00931                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
00932                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
00933                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
00934                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
00935                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
00936                                               ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
00937                                               ((MASK) == RTC_ALARMSUBSECONDMASK_NONE))
00938
00939 #define IS_RTC_ASYNCH_PREDIV(PREDIV)   ((PREDIV) <= (uint32_t)0x7FU)
00940
00941 #define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= (uint32_t)0x7FFFU)
00942
00943 #define IS_RTC_HOUR12(HOUR)            (((HOUR) > (uint32_t)0U) && ((HOUR) <= (uint32_t)12U))
00944
00945 #define IS_RTC_HOUR24(HOUR)            ((HOUR) <= (uint32_t)23U)
00946
00947 #define IS_RTC_MINUTES(MINUTES)        ((MINUTES) <= (uint32_t)59U)
00948
00949 #define IS_RTC_SECONDS(SECONDS)        ((SECONDS) <= (uint32_t)59U)
00950
00951 /**
00952   * @}
00953   */
00954
00955 /**
00956   * @}
00957   */
00958
00959 /* Private functions -------------------------------------------------------------*/
00960 /** @defgroup RTC_Private_Functions RTC Private Functions
00961   * @{
00962   */
00963 HAL_StatusTypeDef  RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
00964 uint8_t            RTC_ByteToBcd2(uint8_t Value);
00965 uint8_t            RTC_Bcd2ToByte(uint8_t Value);
00966 /**
00967   * @}
00968   */
00969
00970
00971 /**
00972   * @}
00973   */
00974
00975 /**
00976   * @}
00977   */
00978
00979 #ifdef __cplusplus
00980 }
00981 #endif
00982
00983 #endif /* STM32WBxx_HAL_RTC_H */
00984
00985 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:35 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_rtc_ex.c Source File

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stm32wbxx_hal_rtc_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_rtc_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended RTC HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Real Time Clock (RTC) Extended peripheral:
00008   *           + RTC Time Stamp functions
00009   *           + RTC Tamper functions
00010   *           + RTC Wake-up functions
00011   *           + Extended Control functions
00012   *           + Extended RTC features functions
00013   *
00014   @verbatim
00015   ==============================================================================
00016                   ##### How to use this driver #####
00017   ==============================================================================
00018   [..]
00019     (+) Enable the RTC domain access.
00020     (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
00021         format using the HAL_RTC_Init() function.
00022
00023   *** RTC Wakeup configuration ***
00024   ================================
00025   [..]
00026     (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer()
00027         function. You can also configure the RTC Wakeup timer with interrupt mode
00028         using the HAL_RTCEx_SetWakeUpTimer_IT() function.
00029     (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer()
00030         function.
00031
00032   *** Outputs configuration ***
00033   =============================
00034   [..]  The RTC has 2 different outputs:
00035     (+) RTC_ALARM: this output is used to manage the RTC Alarm A, Alarm B
00036         and WaKeUp signals.
00037         To output the selected RTC signal, use the HAL_RTC_Init() function.
00038     (+) RTC_CALIB: this output is 512Hz signal or 1Hz.
00039         To enable the RTC_CALIB, use the HAL_RTCEx_SetCalibrationOutPut() function.
00040     (+) Two pins can be used as RTC_ALARM or RTC_CALIB (PC13, PB2) managed on
00041         the RTC_OR register.
00042     (+) When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is
00043         automatically configured in output alternate function.
00044
00045   *** Smooth digital Calibration configuration ***
00046   ================================================
00047   [..]
00048     (+) Configure the RTC Original Digital Calibration Value and the corresponding
00049         calibration cycle period (32s,16s and 8s) using the HAL_RTCEx_SetSmoothCalib()
00050         function.
00051
00052   *** TimeStamp configuration ***
00053   ===============================
00054   [..]
00055     (+) Enable the RTC TimeStamp using the HAL_RTCEx_SetTimeStamp() function.
00056         You can also configure the RTC TimeStamp with interrupt mode using the
00057         HAL_RTCEx_SetTimeStamp_IT() function.
00058     (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
00059         function.
00060
00061   *** Internal TimeStamp configuration ***
00062   ===============================
00063   [..]
00064     (+) Enable the RTC internal TimeStamp using the HAL_RTCEx_SetInternalTimeStamp() function.
00065         User has to check internal timestamp occurrence using __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG.
00066     (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
00067         function.
00068
00069   *** Tamper configuration ***
00070   ============================
00071   [..]
00072     (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge
00073         or Level according to the Tamper filter (if equal to 0 Edge else Level)
00074         value, sampling frequency, NoErase, MaskFlag,  precharge or discharge and
00075         Pull-UP using the HAL_RTCEx_SetTamper() function. You can configure RTC Tamper
00076         with interrupt mode using HAL_RTCEx_SetTamper_IT() function.
00077     (+) The default configuration of the Tamper erases the backup registers. To avoid
00078         erase, enable the NoErase field on the RTC_TAMPCR register.
00079
00080   *** Backup Data Registers configuration ***
00081   ===========================================
00082   [..]
00083     (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite()
00084         function.
00085     (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
00086         function.
00087
00088    @endverbatim
00089   ******************************************************************************
00090   * @attention
00091   *
00092   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00093   * All rights reserved.</center></h2>
00094   *
00095   * This software component is licensed by ST under BSD 3-Clause license,
00096   * the "License"; You may not use this file except in compliance with the
00097   * License. You may obtain a copy of the License at:
00098   *                        opensource.org/licenses/BSD-3-Clause
00099   *
00100   ******************************************************************************
00101   */
00102
00103 /* Includes ------------------------------------------------------------------*/
00104 #include "stm32wbxx_hal.h"
00105
00106 /** @addtogroup STM32WBxx_HAL_Driver
00107   * @{
00108   */
00109
00110 /** @addtogroup RTCEx
00111   * @brief RTC Extended HAL module driver
00112   * @{
00113   */
00114
00115 #ifdef HAL_RTC_MODULE_ENABLED
00116
00117 /* Private typedef -----------------------------------------------------------*/
00118 /* Private define ------------------------------------------------------------*/
00119
00120 /** @defgroup RTCEx_Private_Constants RTCEx Private Constants
00121   * @{
00122   */
00123 #if defined(RTC_TAMPER1_SUPPORT) && defined(RTC_TAMPER3_SUPPORT)
00124 #define RTC_TAMPCR_MASK               ((uint32_t)RTC_TAMPCR_TAMPTS    |\
00125                                        (uint32_t)RTC_TAMPCR_TAMPFREQ  | (uint32_t)RTC_TAMPCR_TAMPFLT      | (uint32_t)RTC_TAMPCR_TAMPPRCH |\
00126                                        (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE                                       |\
00127                                        (uint32_t)RTC_TAMPCR_TAMP1IE   | (uint32_t)RTC_TAMPCR_TAMP1NOERASE | (uint32_t)RTC_TAMPCR_TAMP1MF  |\
00128                                        (uint32_t)RTC_TAMPCR_TAMP2IE   | (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP2MF  |\
00129                                        (uint32_t)RTC_TAMPCR_TAMP3IE   | (uint32_t)RTC_TAMPCR_TAMP3NOERASE | (uint32_t)RTC_TAMPCR_TAMP3MF)
00130 #elif defined(RTC_TAMPER1_SUPPORT)
00131 #define RTC_TAMPCR_MASK               ((uint32_t)RTC_TAMPCR_TAMPTS    |\
00132                                        (uint32_t)RTC_TAMPCR_TAMPFREQ  | (uint32_t)RTC_TAMPCR_TAMPFLT      | (uint32_t)RTC_TAMPCR_TAMPPRCH |\
00133                                        (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE                                       |\
00134                                        (uint32_t)RTC_TAMPCR_TAMP1IE   | (uint32_t)RTC_TAMPCR_TAMP1NOERASE | (uint32_t)RTC_TAMPCR_TAMP1MF  |\
00135                                        (uint32_t)RTC_TAMPCR_TAMP2IE   | (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP2MF)
00136 #elif defined(RTC_TAMPER3_SUPPORT)
00137 #define RTC_TAMPCR_MASK               ((uint32_t)RTC_TAMPCR_TAMPTS    |\
00138                                        (uint32_t)RTC_TAMPCR_TAMPFREQ  | (uint32_t)RTC_TAMPCR_TAMPFLT      | (uint32_t)RTC_TAMPCR_TAMPPRCH |\
00139                                        (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE                                       |\
00140                                        (uint32_t)RTC_TAMPCR_TAMP2IE   | (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP2MF  |\
00141                                        (uint32_t)RTC_TAMPCR_TAMP3IE   | (uint32_t)RTC_TAMPCR_TAMP3NOERASE | (uint32_t)RTC_TAMPCR_TAMP3MF)
00142 #else
00143 #define RTC_TAMPCR_MASK               ((uint32_t)RTC_TAMPCR_TAMPTS    |\
00144                                        (uint32_t)RTC_TAMPCR_TAMPFREQ  | (uint32_t)RTC_TAMPCR_TAMPFLT      | (uint32_t)RTC_TAMPCR_TAMPPRCH |\
00145                                        (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE                                       |\
00146                                        (uint32_t)RTC_TAMPCR_TAMP2IE   | (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP2MF)
00147 #endif /* RTC_TAMPER1_SUPPORT && RTC_TAMPER3_SUPPORT */
00148 /**
00149   * @}
00150   */
00151
00152 /* Private macro -------------------------------------------------------------*/
00153 /* Private variables ---------------------------------------------------------*/
00154 /* Private function prototypes -----------------------------------------------*/
00155 /* Exported functions --------------------------------------------------------*/
00156
00157 /** @addtogroup RTCEx_Exported_Functions
00158   * @{
00159   */
00160
00161
00162 /** @addtogroup RTCEx_Exported_Functions_Group1
00163  *  @brief   RTC TimeStamp and Tamper functions
00164   *
00165 @verbatim
00166  ===============================================================================
00167                  ##### RTC TimeStamp and Tamper functions #####
00168  ===============================================================================
00169
00170  [..] This section provides functions allowing to configure TimeStamp feature
00171
00172 @endverbatim
00173   * @{
00174   */
00175
00176 /**
00177   * @brief  Set TimeStamp.
00178   * @note   This API must be called before enabling the TimeStamp feature.
00179   * @param hrtc RTC handle
00180   * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is
00181   *         activated.
00182   *          This parameter can be one of the following values:
00183   *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
00184   *                                        rising edge of the related pin.
00185   *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
00186   *                                         falling edge of the related pin.
00187   * @param RTC_TimeStampPin specifies the RTC TimeStamp Pin.
00188   *          This parameter can be one of the following values:
00189   *             @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
00190   *               The RTC TimeStamp Pin is per default PC13, but for reasons of
00191   *               compatibility, this parameter is required.
00192   * @retval HAL status
00193   */
00194 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
00195 {
00196   uint32_t tmpreg;
00197
00198   /* Check the parameters */
00199   assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
00200   assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
00201
00202   /* Process Locked */
00203   __HAL_LOCK(hrtc);
00204
00205   hrtc->State = HAL_RTC_STATE_BUSY;
00206
00207   /* Get the RTC_CR register and clear the bits to be configured */
00208   tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
00209
00210   tmpreg|= TimeStampEdge;
00211
00212   /* Disable the write protection for RTC registers */
00213   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00214
00215   /* Clear the Timestamp Flag */
00216   __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
00217
00218   /* Clear the Timestamp overrun Flag */
00219    __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
00220
00221   /* Configure the Time Stamp TSEDGE and Enable bits */
00222   hrtc->Instance->CR = (uint32_t)tmpreg;
00223
00224   __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
00225
00226   /* Enable the write protection for RTC registers */
00227   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00228
00229   /* Change RTC state */
00230   hrtc->State = HAL_RTC_STATE_READY;
00231
00232   /* Process Unlocked */
00233   __HAL_UNLOCK(hrtc);
00234
00235   return HAL_OK;
00236 }
00237
00238 /**
00239   * @brief  Set TimeStamp with Interrupt.
00240   * @param hrtc RTC handle
00241   * @note   This API must be called before enabling the TimeStamp feature.
00242   * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is
00243   *         activated.
00244   *          This parameter can be one of the following values:
00245   *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
00246   *                                        rising edge of the related pin.
00247   *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
00248   *                                         falling edge of the related pin.
00249   * @param RTC_TimeStampPin Specifies the RTC TimeStamp Pin.
00250   *          This parameter can be one of the following values:
00251   *             @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
00252   *               The RTC TimeStamp Pin is per default PC13, but for reasons of
00253   *               compatibility, this parameter is required.
00254   * @retval HAL status
00255   */
00256 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
00257 {
00258   uint32_t tmpreg;
00259
00260   /* Check the parameters */
00261   assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
00262   assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
00263
00264   /* Process Locked */
00265   __HAL_LOCK(hrtc);
00266
00267   hrtc->State = HAL_RTC_STATE_BUSY;
00268
00269   /* Get the RTC_CR register and clear the bits to be configured */
00270   tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
00271
00272   tmpreg |= TimeStampEdge;
00273
00274   /* Disable the write protection for RTC registers */
00275   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00276
00277   /* Clear the Timestamp Flag */
00278   __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
00279
00280   /* Clear the Timestamp overrun Flag */
00281    __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
00282
00283   /* Configure the Time Stamp TSEDGE and Enable bits */
00284   hrtc->Instance->CR = (uint32_t)tmpreg;
00285
00286   __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
00287
00288   /* Enable IT timestamp */
00289   __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS);
00290
00291   /* RTC timestamp Interrupt Configuration: EXTI configuration */
00292   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
00293
00294   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
00295
00296   /* Enable the write protection for RTC registers */
00297   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00298
00299   hrtc->State = HAL_RTC_STATE_READY;
00300
00301   /* Process Unlocked */
00302   __HAL_UNLOCK(hrtc);
00303
00304   return HAL_OK;
00305 }
00306
00307 /**
00308   * @brief  Deactivate TimeStamp.
00309   * @param hrtc RTC handle
00310   * @retval HAL status
00311   */
00312 HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
00313 {
00314   uint32_t tmpreg;
00315
00316   /* Process Locked */
00317   __HAL_LOCK(hrtc);
00318
00319   hrtc->State = HAL_RTC_STATE_BUSY;
00320
00321   /* Disable the write protection for RTC registers */
00322   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00323
00324   /* In case of interrupt mode is used, the interrupt source must disabled */
00325   __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS);
00326
00327   /* Get the RTC_CR register and clear the bits to be configured */
00328   tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
00329
00330   /* Configure the Time Stamp TSEDGE and Enable bits */
00331   hrtc->Instance->CR = (uint32_t)tmpreg;
00332
00333   /* Enable the write protection for RTC registers */
00334   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00335
00336   hrtc->State = HAL_RTC_STATE_READY;
00337
00338   /* Process Unlocked */
00339   __HAL_UNLOCK(hrtc);
00340
00341   return HAL_OK;
00342 }
00343
00344 #if defined(RTC_INTERNALTS_SUPPORT)
00345 /**
00346   * @brief  Set Internal TimeStamp.
00347   * @note   This API must be called before enabling the internal TimeStamp feature.
00348   * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
00349   *                the configuration information for RTC.
00350   * @retval HAL status
00351   */
00352 HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc)
00353 {
00354   /* Process Locked */
00355   __HAL_LOCK(hrtc);
00356
00357   hrtc->State = HAL_RTC_STATE_BUSY;
00358
00359   /* Disable the write protection for RTC registers */
00360   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00361
00362   /* Clear the TIMESTAMP Flags */
00363   __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_ITSF);
00364
00365   /* Configure the internal Time Stamp Enable bits */
00366   __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(hrtc);
00367
00368   /* Enable the write protection for RTC registers */
00369   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00370
00371   /* Change RTC state */
00372   hrtc->State = HAL_RTC_STATE_READY;
00373
00374   /* Process Unlocked */
00375   __HAL_UNLOCK(hrtc);
00376
00377   return HAL_OK;
00378 }
00379
00380 /**
00381   * @brief  Deactivate Internal TimeStamp.
00382   * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
00383   *                the configuration information for RTC.
00384   * @retval HAL status
00385   */
00386 HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc)
00387 {
00388   /* Process Locked */
00389   __HAL_LOCK(hrtc);
00390
00391   hrtc->State = HAL_RTC_STATE_BUSY;
00392
00393   /* Disable the write protection for RTC registers */
00394   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
00395
00396   /* Configure the internal Time Stamp Enable bits */
00397   __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(hrtc);
00398
00399   /* Enable the write protection for RTC registers */
00400   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
00401
00402   hrtc->State = HAL_RTC_STATE_READY;
00403
00404   /* Process Unlocked */
00405   __HAL_UNLOCK(hrtc);
00406
00407   return HAL_OK;
00408 }
00409 #endif
00410
00411 /**
00412   * @brief  Get the RTC TimeStamp value.
00413   * @param hrtc RTC handle
00414   * @param sTimeStamp Pointer to Time structure
00415   * @param sTimeStampDate Pointer to Date structure
00416   * @param Format specifies the format of the entered parameters.
00417   *          This parameter can be one of the following values:
00418   *             @arg RTC_FORMAT_BIN: Binary data format
00419   *             @arg RTC_FORMAT_BCD: BCD data format
00420   * @retval HAL status
00421   */
00422 HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format)
00423 {
00424   uint32_t tmptime, tmpdate;
00425
00426   /* Check the parameters */
00427   assert_param(IS_RTC_FORMAT(Format));
00428
00429   /* Get the TimeStamp time and date registers values */
00430   tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK);
00431   tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK);
00432
00433   /* Fill the Time structure fields with the read parameters */
00434   sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16U);
00435   sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8U);
00436   sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
00437   sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16U);
00438   sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR;
00439
00440   /* Fill the Date structure fields with the read parameters */
00441   sTimeStampDate->Year = 0U;
00442   sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8U);
00443   sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
00444   sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13U);
00445
00446   /* Check the input parameters format */
00447   if(Format == RTC_FORMAT_BIN)
00448   {
00449     /* Convert the TimeStamp structure parameters to Binary format */
00450     sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);
00451     sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes);
00452     sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds);
00453
00454     /* Convert the DateTimeStamp structure parameters to Binary format */
00455     sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month);
00456     sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date);
00457     sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay);
00458   }
00459
00460   /* Clear the TIMESTAMP Flags */
00461   #if defined(RTC_INTERNALTS_SUPPORT)
00462   __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_ITSF);
00463   #endif
00464
00465   __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
00466
00467   return HAL_OK;
00468 }
00469
00470 /**
00471   * @brief  Set Tamper
00472   * @note   By calling this API we disable the tamper interrupt for all tampers.
00473   * @param hrtc RTC handle
00474   * @param sTamper Pointer to Tamper Structure.
00475   * @retval HAL status
00476   */
00477 HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
00478 {
00479   uint32_t tmpreg;
00480
00481   /* Check the parameters */
00482   assert_param(IS_RTC_TAMPER(sTamper->Tamper));
00483   assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
00484   assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));
00485   assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));
00486   assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
00487   assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
00488   assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
00489   assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
00490   assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
00491
00492   /* Process Locked */
00493   __HAL_LOCK(hrtc);
00494
00495   hrtc->State = HAL_RTC_STATE_BUSY;
00496
00497   /* Configure the tamper trigger */
00498   if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
00499   {
00500     sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1U);
00501   }
00502
00503   if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
00504   {
00505     sTamper->NoErase = 0U;
00506 #if defined(RTC_TAMPER1_SUPPORT)
00507     if((sTamper->Tamper & RTC_TAMPER_1) != 0U)
00508     {
00509       sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE;
00510     }
00511 #endif /* RTC_TAMPER1_SUPPORT */
00512     if((sTamper->Tamper & RTC_TAMPER_2) != 0U)
00513     {
00514       sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE;
00515     }
00516 #if defined(RTC_TAMPER3_SUPPORT)
00517     if((sTamper->Tamper & RTC_TAMPER_3) != 0U)
00518     {
00519       sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE;
00520     }
00521 #endif /* RTC_TAMPER3_SUPPORT */
00522   }
00523
00524   if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
00525   {
00526     sTamper->MaskFlag = 0U;
00527 #if defined(RTC_TAMPER1_SUPPORT)
00528     if((sTamper->Tamper & RTC_TAMPER_1) != 0U)
00529     {
00530       sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF;
00531     }
00532 #endif /* RTC_TAMPER1_SUPPORT */
00533     if((sTamper->Tamper & RTC_TAMPER_2) != 0U)
00534     {
00535       sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF;
00536     }
00537 #if defined(RTC_TAMPER3_SUPPORT)
00538     if((sTamper->Tamper & RTC_TAMPER_3) != 0U)
00539     {
00540       sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF;
00541     }
00542 #endif /* RTC_TAMPER3_SUPPORT */
00543   }
00544
00545   /* Configure the RTC_TAMPCR register */
00546   tmpreg = (uint32_t)((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger  | (uint32_t)sTamper->NoErase |\
00547             (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\
00548             (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | (uint32_t)sTamper->TimeStampOnTamperDetection);
00549
00550   hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_MASK);
00551
00552   hrtc->Instance->TAMPCR |= tmpreg;
00553
00554   hrtc->State = HAL_RTC_STATE_READY;
00555
00556   /* Process Unlocked */
00557   __HAL_UNLOCK(hrtc);
00558
00559   return HAL_OK;
00560 }
00561
00562 /**
00563   * @brief  Set Tamper with interrupt.
00564   * @note   By calling this API we force the tamper interrupt for all tampers.
00565   * @param hrtc RTC handle
00566   * @param sTamper Pointer to RTC Tamper.
00567   * @retval HAL status
00568   */
00569 HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
00570 {
00571   uint32_t tmpreg;
00572
00573   /* Check the parameters */
00574   assert_param( IS_RTC_TAMPER(sTamper->Tamper));
00575   assert_param(IS_RTC_TAMPER_INTERRUPT(sTamper->Interrupt));
00576   assert_param( IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
00577   assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));
00578   assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));
00579   assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
00580   assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
00581   assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
00582   assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
00583   assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
00584
00585   /* Process Locked */
00586   __HAL_LOCK(hrtc);
00587
00588   hrtc->State = HAL_RTC_STATE_BUSY;
00589
00590   /* Configure the tamper trigger */
00591   if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
00592   {
00593     sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1U);
00594   }
00595
00596   if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
00597   {
00598     sTamper->NoErase = 0U;
00599 #if defined(RTC_TAMPER1_SUPPORT)
00600     if((sTamper->Tamper & RTC_TAMPER_1) != 0U)
00601     {
00602       sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE;
00603     }
00604 #endif /* RTC_TAMPER1_SUPPORT */
00605     if((sTamper->Tamper & RTC_TAMPER_2) != 0U)
00606     {
00607       sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE;
00608     }
00609 #if defined(RTC_TAMPER3_SUPPORT)
00610     if((sTamper->Tamper & RTC_TAMPER_3) != 0U)
00611     {
00612       sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE;
00613     }
00614 #endif /* RTC_TAMPER3_SUPPORT */
00615   }
00616
00617   if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
00618   {
00619     sTamper->MaskFlag = 0U;
00620 #if defined(RTC_TAMPER1_SUPPORT)
00621     if((sTamper->Tamper & RTC_TAMPER_1) != 0U)
00622     {
00623       sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF;
00624     }
00625 #endif /* RTC_TAMPER1_SUPPORT */
00626     if((sTamper->Tamper & RTC_TAMPER_2) != 0U)
00627     {
00628       sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF;
00629     }
00630 #if defined(RTC_TAMPER3_SUPPORT)
00631     if((sTamper->Tamper & RTC_TAMPER_3) != 0U)
00632     {
00633       sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF;
00634     }
00635 #endif /* RTC_TAMPER3_SUPPORT */
00636   }
00637
00638   /* Configure the RTC_TAMPCR register */
00639   tmpreg = (uint32_t)((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Interrupt | (uint32_t)sTamper->Trigger  | (uint32_t)sTamper->NoErase |\
00640             (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency                                |\
00641             (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | (uint32_t)sTamper->TimeStampOnTamperDetection);
00642
00643   hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_MASK);
00644
00645   hrtc->Instance->TAMPCR |= tmpreg;
00646
00647   /* RTC Tamper Interrupt Configuration: EXTI configuration */
00648   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
00649
00650   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
00651
00652   hrtc->State = HAL_RTC_STATE_READY;
00653
00654   /* Process Unlocked */
00655   __HAL_UNLOCK(hrtc);
00656
00657   return HAL_OK;
00658 }
00659
00660 /**
00661   * @brief  Deactivate Tamper.
00662   * @param hrtc RTC handle
00663   * @param Tamper Selected tamper pin.
00664   *          This parameter can be any combination of RTC_TAMPER_1, RTC_TAMPER_2 and RTC_TAMPER_3.
00665   * @retval HAL status
00666   */
00667 HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)
00668 {
00669   assert_param( IS_RTC_TAMPER(Tamper));
00670
00671   /* Process Locked */
00672   __HAL_LOCK(hrtc);
00673
00674   hrtc->State = HAL_RTC_STATE_BUSY;
00675
00676   /* Disable the selected Tamper pin */
00677   hrtc->Instance->TAMPCR &= ((uint32_t)~Tamper);
00678
00679 #if defined(RTC_TAMPER1_SUPPORT)
00680   if ((Tamper & RTC_TAMPER_1) != 0U)
00681   {
00682     /* Disable the Tamper1 interrupt */
00683     hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP1));
00684   }
00685 #endif /* RTC_TAMPER1_SUPPORT */
00686   if ((Tamper & RTC_TAMPER_2) != 0U)
00687   {
00688     /* Disable the Tamper2 interrupt */
00689     hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP2));
00690   }
00691 #if defined(RTC_TAMPER3_SUPPORT)
00692     if ((Tamper & RTC_TAMPER_3) != 0U)
00693   {
00694     /* Disable the Tamper3 interrupt */
00695     hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP3));
00696   }
00697
00698 #endif /* RTC_TAMPER3_SUPPORT */
00699
00700   hrtc->State = HAL_RTC_STATE_READY;
00701
00702   /* Process Unlocked */
00703   __HAL_UNLOCK(hrtc);
00704
00705   return HAL_OK;
00706 }
00707
00708 /**
00709   * @brief  Handle TimeStamp interrupt request.
00710   * @param hrtc RTC handle
00711   * @retval None
00712   */
00713 void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
00714 {
00715   /* Get the TimeStamp interrupt source enable status */
00716   if(__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != 0U)
00717   {
00718     /* Get the pending status of the TIMESTAMP Interrupt */
00719     if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != 0U)
00720     {
00721       /* TIMESTAMP callback */
00722 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
00723       hrtc->TimeStampEventCallback(hrtc);
00724 #else
00725       HAL_RTCEx_TimeStampEventCallback(hrtc);
00726 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
00727
00728       /* Clear the TIMESTAMP interrupt pending bit */
00729       __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
00730     }
00731   }
00732
00733 #if defined(RTC_TAMPER1_SUPPORT)
00734   /* Get the Tamper1 interrupts source enable status */
00735   if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP1) != 0U)
00736   {
00737     /* Get the pending status of the Tamper1 Interrupt */
00738     if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != 0U)
00739     {
00740       /* Tamper1 callback */
00741 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
00742       hrtc->Tamper1EventCallback(hrtc);
00743 #else
00744       HAL_RTCEx_Tamper1EventCallback(hrtc);
00745 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
00746
00747       /* Clear the Tamper1 interrupt pending bit */
00748       __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
00749     }
00750   }
00751 #endif /* RTC_TAMPER1_SUPPORT */
00752
00753
00754   /* Get the Tamper2 interrupts source enable status */
00755   if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP2) != 0U)
00756   {
00757     /* Get the pending status of the Tamper2 Interrupt */
00758     if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != 0U)
00759     {
00760       /* Tamper2 callback */
00761 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
00762       hrtc->Tamper2EventCallback(hrtc);
00763 #else
00764       HAL_RTCEx_Tamper2EventCallback(hrtc);
00765 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
00766
00767       /* Clear the Tamper2 interrupt pending bit */
00768       __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
00769     }
00770   }
00771
00772 #if defined(RTC_TAMPER3_SUPPORT)
00773   /* Get the Tamper3 interrupts source enable status */
00774   if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP3) != 0U)
00775   {
00776     /* Get the pending status of the Tamper3 Interrupt */
00777     if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != 0U)
00778     {
00779       /* Tamper3 callback */
00780 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
00781       hrtc->Tamper3EventCallback(hrtc);
00782 #else
00783       HAL_RTCEx_Tamper3EventCallback(hrtc);
00784 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
00785
00786       /* Clear the Tamper3 interrupt pending bit */
00787       __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);
00788     }
00789   }
00790 #endif /* RTC_TAMPER3_SUPPORT */
00791
00792   /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */
00793   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
00794
00795   /* Change RTC state */
00796   hrtc->State = HAL_RTC_STATE_READY;
00797 }
00798
00799 /**
00800   * @brief  TimeStamp callback.
00801   * @param hrtc RTC handle
00802   * @retval None
00803   */
00804 __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
00805 {
00806   /* Prevent unused argument(s) compilation warning */
00807   UNUSED(hrtc);
00808
00809   /* NOTE : This function should not be modified, when the callback is needed,
00810             the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file
00811   */
00812 }
00813
00814 #if defined(RTC_TAMPER1_SUPPORT)
00815 /**
00816   * @brief  Tamper 1 callback.
00817   * @param hrtc RTC handle
00818   * @retval None
00819   */
00820 __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
00821 {
00822   /* Prevent unused argument(s) compilation warning */
00823   UNUSED(hrtc);
00824
00825   /* NOTE : This function should not be modified, when the callback is needed,
00826             the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file
00827    */
00828 }
00829 #endif /* RTC_TAMPER1_SUPPORT */
00830
00831 /**
00832   * @brief  Tamper 2 callback.
00833   * @param hrtc RTC handle
00834   * @retval None
00835   */
00836 __weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
00837 {
00838   /* Prevent unused argument(s) compilation warning */
00839   UNUSED(hrtc);
00840
00841   /* NOTE : This function should not be modified, when the callback is needed,
00842             the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file
00843    */
00844 }
00845
00846 #if defined(RTC_TAMPER3_SUPPORT)
00847 /**
00848   * @brief  Tamper 3 callback.
00849   * @param hrtc RTC handle
00850   * @retval None
00851   */
00852 __weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc)
00853 {
00854   /* Prevent unused argument(s) compilation warning */
00855   UNUSED(hrtc);
00856
00857   /* NOTE : This function should not be modified, when the callback is needed,
00858             the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file
00859    */
00860 }
00861 #endif /* RTC_TAMPER3_SUPPORT */
00862
00863 /**
00864   * @brief  Handle TimeStamp polling request.
00865   * @param hrtc RTC handle
00866   * @param Timeout Timeout duration
00867   * @retval HAL status
00868   */
00869 HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
00870 {
00871   uint32_t tickstart = HAL_GetTick();
00872
00873   while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == 0U)
00874   {
00875     if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != 0U)
00876     {
00877       /* Clear the TIMESTAMP OverRun Flag */
00878       __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
00879
00880       /* Change TIMESTAMP state */
00881       hrtc->State = HAL_RTC_STATE_ERROR;
00882
00883       return HAL_ERROR;
00884     }
00885
00886     if(Timeout != HAL_MAX_DELAY)
00887     {
00888       if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
00889       {
00890         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00891         return HAL_TIMEOUT;
00892       }
00893     }
00894   }
00895
00896   /* Change RTC state */
00897   hrtc->State = HAL_RTC_STATE_READY;
00898
00899   return HAL_OK;
00900 }
00901
00902 #if defined(RTC_TAMPER1_SUPPORT)
00903 /**
00904   * @brief  Handle Tamper 1 Polling.
00905   * @param hrtc RTC handle
00906   * @param Timeout Timeout duration
00907   * @retval HAL status
00908   */
00909 HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
00910 {
00911   uint32_t tickstart = HAL_GetTick();
00912
00913   /* Get the status of the Interrupt */
00914   while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== 0U)
00915   {
00916     if(Timeout != HAL_MAX_DELAY)
00917     {
00918       if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
00919       {
00920         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00921         return HAL_TIMEOUT;
00922       }
00923     }
00924   }
00925
00926   /* Clear the Tamper Flag */
00927   __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
00928
00929   /* Change RTC state */
00930   hrtc->State = HAL_RTC_STATE_READY;
00931
00932   return HAL_OK;
00933 }
00934 #endif /* RTC_TAMPER1_SUPPORT */
00935
00936 /**
00937   * @brief  Handle Tamper 2 Polling.
00938   * @param hrtc RTC handle
00939   * @param Timeout Timeout duration
00940   * @retval HAL status
00941   */
00942 HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
00943 {
00944   uint32_t tickstart = HAL_GetTick();
00945
00946   /* Get the status of the Interrupt */
00947   while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == 0U)
00948   {
00949     if(Timeout != HAL_MAX_DELAY)
00950     {
00951       if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
00952       {
00953         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00954         return HAL_TIMEOUT;
00955       }
00956     }
00957   }
00958
00959   /* Clear the Tamper Flag */
00960   __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP2F);
00961
00962   /* Change RTC state */
00963   hrtc->State = HAL_RTC_STATE_READY;
00964
00965   return HAL_OK;
00966 }
00967
00968 #if defined(RTC_TAMPER3_SUPPORT)
00969 /**
00970   * @brief  Handle Tamper 3 Polling.
00971   * @param hrtc RTC handle
00972   * @param Timeout Timeout duration
00973   * @retval HAL status
00974   */
00975 HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
00976 {
00977   uint32_t tickstart = HAL_GetTick();
00978
00979   /* Get the status of the Interrupt */
00980   while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP3F) == 0U)
00981   {
00982     if(Timeout != HAL_MAX_DELAY)
00983     {
00984       if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
00985       {
00986         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00987         return HAL_TIMEOUT;
00988       }
00989     }
00990   }
00991
00992   /* Clear the Tamper Flag */
00993   __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP3F);
00994
00995   /* Change RTC state */
00996   hrtc->State = HAL_RTC_STATE_READY;
00997
00998   return HAL_OK;
00999 }
01000 #endif /* RTC_TAMPER3_SUPPORT */
01001
01002 /**
01003   * @}
01004   */
01005
01006 /** @addtogroup RTCEx_Exported_Functions_Group2
01007   * @brief    RTC Wake-up functions
01008   *
01009 @verbatim
01010  ===============================================================================
01011                         ##### RTC Wake-up functions #####
01012  ===============================================================================
01013
01014  [..] This section provides functions allowing to configure Wake-up feature
01015
01016 @endverbatim
01017   * @{
01018   */
01019
01020 /**
01021   * @brief  Set wake up timer.
01022   * @param hrtc RTC handle
01023   * @param WakeUpCounter Wake up counter
01024   * @param WakeUpClock Wake up clock
01025   * @retval HAL status
01026   */
01027 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
01028 {
01029   uint32_t tickstart;
01030
01031   /* Check the parameters */
01032   assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
01033   assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
01034
01035   /* Process Locked */
01036   __HAL_LOCK(hrtc);
01037
01038   hrtc->State = HAL_RTC_STATE_BUSY;
01039
01040   /* Disable the write protection for RTC registers */
01041   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01042
01043   /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
01044   if((hrtc->Instance->CR & RTC_CR_WUTE) != 0U){
01045     tickstart = HAL_GetTick();
01046
01047    /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
01048    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 1U)
01049    {
01050     if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01051       {
01052        /* Enable the write protection for RTC registers */
01053        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01054
01055        hrtc->State = HAL_RTC_STATE_TIMEOUT;
01056
01057        /* Process Unlocked */
01058        __HAL_UNLOCK(hrtc);
01059
01060        return HAL_TIMEOUT;
01061       }
01062     }
01063   }
01064
01065   __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
01066
01067   tickstart = HAL_GetTick();
01068
01069   /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
01070   while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U)
01071   {
01072     if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01073     {
01074       /* Enable the write protection for RTC registers */
01075       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01076
01077       hrtc->State = HAL_RTC_STATE_TIMEOUT;
01078
01079       /* Process Unlocked */
01080       __HAL_UNLOCK(hrtc);
01081
01082       return HAL_TIMEOUT;
01083     }
01084   }
01085
01086   /* Clear the Wakeup Timer clock source bits in CR register */
01087   hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
01088
01089   /* Configure the clock source */
01090   hrtc->Instance->CR |= (uint32_t)WakeUpClock;
01091
01092   /* Configure the Wakeup Timer counter */
01093   hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
01094
01095    /* Enable the Wakeup Timer */
01096   __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
01097
01098   /* Enable the write protection for RTC registers */
01099   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01100
01101   hrtc->State = HAL_RTC_STATE_READY;
01102
01103   /* Process Unlocked */
01104   __HAL_UNLOCK(hrtc);
01105
01106   return HAL_OK;
01107 }
01108
01109 /**
01110   * @brief  Set wake up timer with interrupt.
01111   * @param hrtc RTC handle
01112   * @param WakeUpCounter Wake up counter
01113   * @param WakeUpClock Wake up clock
01114   * @retval HAL status
01115   */
01116 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
01117 {
01118   uint32_t tickstart;
01119
01120   /* Check the parameters */
01121   assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
01122   assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
01123
01124   /* Process Locked */
01125   __HAL_LOCK(hrtc);
01126
01127   hrtc->State = HAL_RTC_STATE_BUSY;
01128
01129   /* Disable the write protection for RTC registers */
01130   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01131
01132   /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
01133   if((hrtc->Instance->CR & RTC_CR_WUTE) != 0U){
01134     tickstart = HAL_GetTick();
01135
01136    /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
01137    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 1U)
01138    {
01139     if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01140       {
01141        /* Enable the write protection for RTC registers */
01142        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01143
01144        hrtc->State = HAL_RTC_STATE_TIMEOUT;
01145
01146        /* Process Unlocked */
01147        __HAL_UNLOCK(hrtc);
01148
01149        return HAL_TIMEOUT;
01150       }
01151     }
01152   }
01153   /* Disable the Wake-Up timer */
01154   __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
01155
01156   /* Clear flag Wake-Up */
01157   __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
01158
01159   tickstart = HAL_GetTick();
01160
01161   /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
01162   while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U)
01163   {
01164     if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01165     {
01166       /* Enable the write protection for RTC registers */
01167       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01168
01169       hrtc->State = HAL_RTC_STATE_TIMEOUT;
01170
01171       /* Process Unlocked */
01172       __HAL_UNLOCK(hrtc);
01173
01174       return HAL_TIMEOUT;
01175     }
01176   }
01177
01178   /* Configure the Wakeup Timer counter */
01179   hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
01180
01181   /* Clear the Wakeup Timer clock source bits in CR register */
01182   hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
01183
01184   /* Configure the clock source */
01185   hrtc->Instance->CR |= (uint32_t)WakeUpClock;
01186
01187   /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
01188   __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
01189
01190   __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
01191
01192   /* Configure the Interrupt in the RTC_CR register */
01193   __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT);
01194
01195   /* Enable the Wakeup Timer */
01196   __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
01197
01198   /* Enable the write protection for RTC registers */
01199   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01200
01201   hrtc->State = HAL_RTC_STATE_READY;
01202
01203   /* Process Unlocked */
01204   __HAL_UNLOCK(hrtc);
01205
01206   return HAL_OK;
01207 }
01208
01209 /**
01210   * @brief  Deactivate wake up timer counter.
01211   * @param hrtc RTC handle
01212   * @retval HAL status
01213   */
01214 HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
01215 {
01216   uint32_t tickstart;
01217
01218   /* Process Locked */
01219   __HAL_LOCK(hrtc);
01220
01221   hrtc->State = HAL_RTC_STATE_BUSY;
01222
01223   /* Disable the write protection for RTC registers */
01224   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01225
01226   /* Disable the Wakeup Timer */
01227   __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
01228
01229   /* In case of interrupt mode is used, the interrupt source must disabled */
01230   __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT);
01231
01232   tickstart = HAL_GetTick();
01233   /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
01234   while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U)
01235   {
01236     if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01237     {
01238       /* Enable the write protection for RTC registers */
01239       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01240
01241       hrtc->State = HAL_RTC_STATE_TIMEOUT;
01242
01243       /* Process Unlocked */
01244       __HAL_UNLOCK(hrtc);
01245
01246       return HAL_TIMEOUT;
01247     }
01248   }
01249
01250   /* Enable the write protection for RTC registers */
01251   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01252
01253   hrtc->State = HAL_RTC_STATE_READY;
01254
01255   /* Process Unlocked */
01256   __HAL_UNLOCK(hrtc);
01257
01258   return HAL_OK;
01259 }
01260
01261 /**
01262   * @brief  Get wake up timer counter.
01263   * @param hrtc RTC handle
01264   * @retval Counter value
01265   */
01266 uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
01267 {
01268   /* Get the counter value */
01269   return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT));
01270 }
01271
01272 /**
01273   * @brief  Handle Wake Up Timer interrupt request.
01274   * @param hrtc RTC handle
01275   * @retval None
01276   */
01277 void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
01278 {
01279     /* Get the pending status of the WAKEUPTIMER Interrupt */
01280     if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != 0U)
01281     {
01282       /* WAKEUPTIMER callback */
01283 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
01284       hrtc->WakeUpTimerEventCallback(hrtc);
01285 #else
01286       HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
01287 #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
01288
01289       /* Clear the WAKEUPTIMER interrupt pending bit */
01290       __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
01291     }
01292
01293   /* Clear the EXTI's line Flag for RTC WakeUpTimer */
01294   __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
01295
01296   /* Change RTC state */
01297   hrtc->State = HAL_RTC_STATE_READY;
01298 }
01299
01300 /**
01301   * @brief  Wake Up Timer callback.
01302   * @param hrtc RTC handle
01303   * @retval None
01304   */
01305 __weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
01306 {
01307   /* Prevent unused argument(s) compilation warning */
01308   UNUSED(hrtc);
01309
01310   /* NOTE : This function should not be modified, when the callback is needed,
01311             the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file
01312    */
01313 }
01314
01315
01316 /**
01317   * @brief  Handle Wake Up Timer Polling.
01318   * @param hrtc RTC handle
01319   * @param Timeout Timeout duration
01320   * @retval HAL status
01321   */
01322 HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
01323 {
01324   uint32_t tickstart = HAL_GetTick();
01325
01326   while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == 0U)
01327   {
01328     if(Timeout != HAL_MAX_DELAY)
01329     {
01330       if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
01331       {
01332         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01333
01334         return HAL_TIMEOUT;
01335       }
01336     }
01337   }
01338
01339   /* Clear the WAKEUPTIMER Flag */
01340   __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
01341
01342   /* Change RTC state */
01343   hrtc->State = HAL_RTC_STATE_READY;
01344
01345   return HAL_OK;
01346 }
01347
01348 /**
01349   * @}
01350   */
01351
01352
01353 /** @addtogroup RTCEx_Exported_Functions_Group3
01354   * @brief    Extended Peripheral Control functions
01355   *
01356 @verbatim
01357  ===============================================================================
01358               ##### Extended Peripheral Control functions #####
01359  ===============================================================================
01360     [..]
01361     This subsection provides functions allowing to
01362       (+) Write a data in a specified RTC Backup data register
01363       (+) Read a data in a specified RTC Backup data register
01364       (+) Set the Coarse calibration parameters.
01365       (+) Deactivate the Coarse calibration parameters
01366       (+) Set the Smooth calibration parameters.
01367       (+) Configure the Synchronization Shift Control Settings.
01368       (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
01369       (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
01370       (+) Enable the RTC reference clock detection.
01371       (+) Disable the RTC reference clock detection.
01372       (+) Enable the Bypass Shadow feature.
01373       (+) Disable the Bypass Shadow feature.
01374
01375 @endverbatim
01376   * @{
01377   */
01378
01379 /**
01380   * @brief  Write a data in a specified RTC Backup data register.
01381   * @param hrtc RTC handle
01382   * @param BackupRegister RTC Backup data Register number.
01383   *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
01384   *                                 specify the register.
01385   * @param Data Data to be written in the specified RTC Backup data register.
01386   * @retval None
01387   */
01388 void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
01389 {
01390   uint32_t tmp;
01391
01392   /* Check the parameters */
01393   assert_param(IS_RTC_BKP(BackupRegister));
01394
01395   tmp = (uint32_t)&(hrtc->Instance->BKP0R);
01396   tmp += (BackupRegister * 4U);
01397
01398   /* Write the specified register */
01399   *(__IO uint32_t *)tmp = (uint32_t)Data;
01400 }
01401
01402 /**
01403   * @brief  Reads data from the specified RTC Backup data Register.
01404   * @param hrtc RTC handle
01405   * @param BackupRegister RTC Backup data Register number.
01406   *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
01407   *                                 specify the register.
01408   * @retval Read value
01409   */
01410 uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
01411 {
01412   uint32_t tmp;
01413
01414   /* Check the parameters */
01415   assert_param(IS_RTC_BKP(BackupRegister));
01416
01417   tmp = (uint32_t)&(hrtc->Instance->BKP0R);
01418   tmp += (BackupRegister * 4U);
01419
01420   /* Read the specified register */
01421   return (*(__IO uint32_t *)tmp);
01422 }
01423
01424 /**
01425   * @brief  Set the Smooth calibration parameters.
01426   * @param hrtc RTC handle
01427   * @param SmoothCalibPeriod Select the Smooth Calibration Period.
01428   *          This parameter can be can be one of the following values :
01429   *             @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
01430   *             @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
01431   *             @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
01432   * @param SmoothCalibPlusPulses Select to Set or reset the CALP bit.
01433   *          This parameter can be one of the following values:
01434   *             @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses.
01435   *             @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
01436   * @param SmoothCalibMinusPulsesValue Select the value of CALM[8:0] bits.
01437   *          This parameter can be one any value from 0 to 0x000001FF.
01438   * @note   To deactivate the smooth calibration, the field SmoothCalibPlusPulses
01439   *         must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field
01440   *         SmoothCalibMinusPulsesValue mut be equal to 0.
01441   * @retval HAL status
01442   */
01443 HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
01444 {
01445   uint32_t tickstart;
01446
01447   /* Check the parameters */
01448   assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod));
01449   assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses));
01450   assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmoothCalibMinusPulsesValue));
01451
01452   /* Process Locked */
01453   __HAL_LOCK(hrtc);
01454
01455   hrtc->State = HAL_RTC_STATE_BUSY;
01456
01457   /* Disable the write protection for RTC registers */
01458   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01459
01460   /* check if a calibration is pending*/
01461   if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != 0U)
01462   {
01463     tickstart = HAL_GetTick();
01464
01465     /* check if a calibration is pending*/
01466     while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != 0U)
01467     {
01468       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01469       {
01470         /* Enable the write protection for RTC registers */
01471         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01472
01473         /* Change RTC state */
01474         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01475
01476         /* Process Unlocked */
01477         __HAL_UNLOCK(hrtc);
01478
01479         return HAL_TIMEOUT;
01480       }
01481     }
01482   }
01483
01484   /* Configure the Smooth calibration settings */
01485   hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmoothCalibMinusPulsesValue);
01486
01487   /* Enable the write protection for RTC registers */
01488   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01489
01490   /* Change RTC state */
01491   hrtc->State = HAL_RTC_STATE_READY;
01492
01493   /* Process Unlocked */
01494   __HAL_UNLOCK(hrtc);
01495
01496   return HAL_OK;
01497 }
01498
01499 /**
01500   * @brief  Configure the Synchronization Shift Control Settings.
01501   * @note   When REFCKON is set, firmware must not write to Shift control register.
01502   * @param hrtc RTC handle
01503   * @param ShiftAdd1S Select to add or not 1 second to the time calendar.
01504   *          This parameter can be one of the following values :
01505   *             @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
01506   *             @arg RTC_SHIFTADD1S_RESET: No effect.
01507   * @param ShiftSubFS Select the number of Second Fractions to substitute.
01508   *          This parameter can be one any value from 0 to 0x7FFF.
01509   * @retval HAL status
01510   */
01511 HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
01512 {
01513   uint32_t tickstart;
01514
01515   /* Check the parameters */
01516   assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S));
01517   assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS));
01518
01519   /* Process Locked */
01520   __HAL_LOCK(hrtc);
01521
01522   hrtc->State = HAL_RTC_STATE_BUSY;
01523
01524   /* Disable the write protection for RTC registers */
01525   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01526
01527     tickstart = HAL_GetTick();
01528
01529     /* Wait until the shift is completed*/
01530     while((hrtc->Instance->ISR & RTC_ISR_SHPF) != 0U)
01531     {
01532       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
01533       {
01534         /* Enable the write protection for RTC registers */
01535         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01536
01537         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01538
01539         /* Process Unlocked */
01540         __HAL_UNLOCK(hrtc);
01541
01542         return HAL_TIMEOUT;
01543       }
01544     }
01545
01546     /* Check if the reference clock detection is disabled */
01547     if((hrtc->Instance->CR & RTC_CR_REFCKON) == 0U)
01548     {
01549       /* Configure the Shift settings */
01550       hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S);
01551
01552       /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
01553       if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == 0U)
01554       {
01555         if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
01556         {
01557           /* Enable the write protection for RTC registers */
01558           __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01559
01560           hrtc->State = HAL_RTC_STATE_ERROR;
01561
01562           /* Process Unlocked */
01563           __HAL_UNLOCK(hrtc);
01564
01565           return HAL_ERROR;
01566         }
01567       }
01568     }
01569     else
01570     {
01571       /* Enable the write protection for RTC registers */
01572       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01573
01574       /* Change RTC state */
01575       hrtc->State = HAL_RTC_STATE_ERROR;
01576
01577       /* Process Unlocked */
01578       __HAL_UNLOCK(hrtc);
01579
01580       return HAL_ERROR;
01581     }
01582
01583   /* Enable the write protection for RTC registers */
01584   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01585
01586   /* Change RTC state */
01587   hrtc->State = HAL_RTC_STATE_READY;
01588
01589   /* Process Unlocked */
01590   __HAL_UNLOCK(hrtc);
01591
01592   return HAL_OK;
01593 }
01594
01595 /**
01596   * @brief  Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
01597   * @param hrtc RTC handle
01598   * @param  CalibOutput : Select the Calibration output Selection .
01599   *          This parameter can be one of the following values:
01600   *             @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
01601   *             @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
01602   * @retval HAL status
01603   */
01604 HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput)
01605 {
01606   /* Check the parameters */
01607   assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput));
01608
01609   /* Process Locked */
01610   __HAL_LOCK(hrtc);
01611
01612   hrtc->State = HAL_RTC_STATE_BUSY;
01613
01614   /* Disable the write protection for RTC registers */
01615   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01616
01617   /* Clear flags before config */
01618   hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL;
01619
01620   /* Configure the RTC_CR register */
01621   hrtc->Instance->CR |= (uint32_t)CalibOutput;
01622
01623   __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc);
01624
01625   /* Enable the write protection for RTC registers */
01626   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01627
01628   /* Change RTC state */
01629   hrtc->State = HAL_RTC_STATE_READY;
01630
01631   /* Process Unlocked */
01632   __HAL_UNLOCK(hrtc);
01633
01634   return HAL_OK;
01635 }
01636
01637 /**
01638   * @brief  Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
01639   * @param hrtc RTC handle
01640   * @retval HAL status
01641   */
01642 HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc)
01643 {
01644   /* Process Locked */
01645   __HAL_LOCK(hrtc);
01646
01647   hrtc->State = HAL_RTC_STATE_BUSY;
01648
01649   /* Disable the write protection for RTC registers */
01650   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01651
01652   __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc);
01653
01654   /* Enable the write protection for RTC registers */
01655   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01656
01657   /* Change RTC state */
01658   hrtc->State = HAL_RTC_STATE_READY;
01659
01660   /* Process Unlocked */
01661   __HAL_UNLOCK(hrtc);
01662
01663   return HAL_OK;
01664 }
01665
01666 /**
01667   * @brief  Enable the RTC reference clock detection.
01668   * @param hrtc RTC handle
01669   * @retval HAL status
01670   */
01671 HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc)
01672 {
01673   /* Process Locked */
01674   __HAL_LOCK(hrtc);
01675
01676   hrtc->State = HAL_RTC_STATE_BUSY;
01677
01678   /* Disable the write protection for RTC registers */
01679   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01680
01681   /* Set Initialization mode */
01682   if(RTC_EnterInitMode(hrtc) != HAL_OK)
01683   {
01684     /* Enable the write protection for RTC registers */
01685     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01686
01687     /* Set RTC state*/
01688     hrtc->State = HAL_RTC_STATE_ERROR;
01689
01690     /* Process Unlocked */
01691     __HAL_UNLOCK(hrtc);
01692
01693     return HAL_ERROR;
01694   }
01695   else
01696   {
01697     __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc);
01698
01699     /* Exit Initialization mode */
01700     hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
01701   }
01702
01703   /* Enable the write protection for RTC registers */
01704   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01705
01706    /* Change RTC state */
01707   hrtc->State = HAL_RTC_STATE_READY;
01708
01709   /* Process Unlocked */
01710   __HAL_UNLOCK(hrtc);
01711
01712   return HAL_OK;
01713 }
01714
01715 /**
01716   * @brief  Disable the RTC reference clock detection.
01717   * @param hrtc RTC handle
01718   * @retval HAL status
01719   */
01720 HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc)
01721 {
01722   /* Process Locked */
01723   __HAL_LOCK(hrtc);
01724
01725   hrtc->State = HAL_RTC_STATE_BUSY;
01726
01727   /* Disable the write protection for RTC registers */
01728   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01729
01730   /* Set Initialization mode */
01731   if(RTC_EnterInitMode(hrtc) != HAL_OK)
01732   {
01733     /* Enable the write protection for RTC registers */
01734     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01735
01736     /* Set RTC state*/
01737     hrtc->State = HAL_RTC_STATE_ERROR;
01738
01739     /* Process Unlocked */
01740     __HAL_UNLOCK(hrtc);
01741
01742     return HAL_ERROR;
01743   }
01744   else
01745   {
01746     __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc);
01747
01748     /* Exit Initialization mode */
01749     hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
01750   }
01751
01752   /* Enable the write protection for RTC registers */
01753   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01754
01755   /* Change RTC state */
01756   hrtc->State = HAL_RTC_STATE_READY;
01757
01758   /* Process Unlocked */
01759   __HAL_UNLOCK(hrtc);
01760
01761   return HAL_OK;
01762 }
01763
01764 /**
01765   * @brief  Enable the Bypass Shadow feature.
01766   * @param hrtc RTC handle
01767   * @note   When the Bypass Shadow is enabled the calendar value are taken
01768   *         directly from the Calendar counter.
01769   * @retval HAL status
01770   */
01771 HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc)
01772 {
01773   /* Process Locked */
01774   __HAL_LOCK(hrtc);
01775
01776   hrtc->State = HAL_RTC_STATE_BUSY;
01777
01778   /* Disable the write protection for RTC registers */
01779   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01780
01781   /* Set the BYPSHAD bit */
01782   hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD;
01783
01784   /* Enable the write protection for RTC registers */
01785   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01786
01787   /* Change RTC state */
01788   hrtc->State = HAL_RTC_STATE_READY;
01789
01790   /* Process Unlocked */
01791   __HAL_UNLOCK(hrtc);
01792
01793   return HAL_OK;
01794 }
01795
01796 /**
01797   * @brief  Disable the Bypass Shadow feature.
01798   * @param hrtc RTC handle
01799   * @note   When the Bypass Shadow is enabled the calendar value are taken
01800   *         directly from the Calendar counter.
01801   * @retval HAL status
01802   */
01803 HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc)
01804 {
01805   /* Process Locked */
01806   __HAL_LOCK(hrtc);
01807
01808   hrtc->State = HAL_RTC_STATE_BUSY;
01809
01810   /* Disable the write protection for RTC registers */
01811   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01812
01813   /* Reset the BYPSHAD bit */
01814   hrtc->Instance->CR &= ((uint8_t)~RTC_CR_BYPSHAD);
01815
01816   /* Enable the write protection for RTC registers */
01817   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01818
01819   /* Change RTC state */
01820   hrtc->State = HAL_RTC_STATE_READY;
01821
01822   /* Process Unlocked */
01823   __HAL_UNLOCK(hrtc);
01824
01825   return HAL_OK;
01826 }
01827
01828 /**
01829   * @}
01830   */
01831
01832 /** @addtogroup RTCEx_Exported_Functions_Group4
01833   * @brief    Extended features functions
01834   *
01835 @verbatim
01836  ===============================================================================
01837                  ##### Extended features functions #####
01838  ===============================================================================
01839     [..]  This section provides functions allowing to:
01840       (+) RTC Alram B callback
01841       (+) RTC Poll for Alarm B request
01842
01843 @endverbatim
01844   * @{
01845   */
01846
01847 /**
01848   * @brief  Alarm B callback.
01849   * @param hrtc RTC handle
01850   * @retval None
01851   */
01852 __weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)
01853 {
01854   /* Prevent unused argument(s) compilation warning */
01855   UNUSED(hrtc);
01856
01857   /* NOTE : This function should not be modified, when the callback is needed,
01858             the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file
01859    */
01860 }
01861
01862 /**
01863   * @brief  Handle Alarm B Polling request.
01864   * @param hrtc RTC handle
01865   * @param Timeout Timeout duration
01866   * @retval HAL status
01867   */
01868 HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
01869 {
01870   uint32_t tickstart = HAL_GetTick();
01871
01872   while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == 0U)
01873   {
01874     if(Timeout != HAL_MAX_DELAY)
01875     {
01876       if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
01877       {
01878         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01879         return HAL_TIMEOUT;
01880       }
01881     }
01882   }
01883
01884   /* Clear the Alarm Flag */
01885   __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
01886
01887   /* Change RTC state */
01888   hrtc->State = HAL_RTC_STATE_READY;
01889
01890   return HAL_OK;
01891 }
01892
01893 /**
01894   * @}
01895   */
01896
01897 /**
01898   * @}
01899   */
01900
01901 #endif /* HAL_RTC_MODULE_ENABLED */
01902 /**
01903   * @}
01904   */
01905
01906
01907 /**
01908   * @}
01909   */
01910
01911 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
01912
Generated on Fri Sep 6 2019 11:34:35 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_rtc_ex.h Source File

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stm32wbxx_hal_rtc_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_rtc_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of RTC HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_RTC_EX_H
00022 #define STM32WBxx_HAL_RTC_EX_H
00023
00024 #ifdef __cplusplus
00025  extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 /** @addtogroup STM32WBxx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @defgroup RTCEx RTCEx
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040
00041 /** @defgroup RTCEx_Exported_Types RTCEx Exported Types
00042   * @{
00043   */
00044
00045 /**
00046   * @brief  RTC Tamper structure definition
00047   */
00048 typedef struct
00049 {
00050   uint32_t Tamper;                      /*!< Specifies the Tamper Pin.
00051                                              This parameter can be a value of @ref  RTCEx_Tamper_Pins_Definitions */
00052
00053   uint32_t Interrupt;                   /*!< Specifies the Tamper Interrupt.
00054                                              This parameter can be a value of @ref  RTCEx_Tamper_Interrupt_Definitions */
00055
00056   uint32_t Trigger;                     /*!< Specifies the Tamper Trigger.
00057                                              This parameter can be a value of @ref  RTCEx_Tamper_Trigger_Definitions */
00058
00059   uint32_t NoErase;                     /*!< Specifies the Tamper no erase mode.
00060                                              This parameter can be a value of @ref  RTCEx_Tamper_EraseBackUp_Definitions */
00061
00062   uint32_t MaskFlag;                     /*!< Specifies the Tamper Flag masking.
00063                                              This parameter can be a value of @ref RTCEx_Tamper_MaskFlag_Definitions   */
00064
00065   uint32_t Filter;                      /*!< Specifies the RTC Filter Tamper.
00066                                              This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */
00067
00068   uint32_t SamplingFrequency;           /*!< Specifies the sampling frequency.
00069                                              This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies_Definitions */
00070
00071   uint32_t PrechargeDuration;           /*!< Specifies the Precharge Duration .
00072                                              This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */
00073
00074   uint32_t TamperPullUp;                /*!< Specifies the Tamper PullUp .
00075                                              This parameter can be a value of @ref RTCEx_Tamper_Pull_UP_Definitions */
00076
00077   uint32_t TimeStampOnTamperDetection;  /*!< Specifies the TimeStampOnTamperDetection.
00078                                              This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */
00079 }RTC_TamperTypeDef;
00080 /**
00081   * @}
00082   */
00083
00084 /* Exported constants --------------------------------------------------------*/
00085 /** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants
00086   * @{
00087   */
00088
00089 /** @defgroup RTCEx_Output_selection_Definitions RTCEx Output Selection Definition
00090   * @{
00091   */
00092 #define RTC_OUTPUT_DISABLE             ((uint32_t)0x00000000U)
00093 #define RTC_OUTPUT_ALARMA              ((uint32_t)RTC_CR_OSEL_0)
00094 #define RTC_OUTPUT_ALARMB              ((uint32_t)RTC_CR_OSEL_1)
00095 #define RTC_OUTPUT_WAKEUP              ((uint32_t)RTC_CR_OSEL)
00096
00097 /**
00098   * @}
00099   */
00100
00101 /** @defgroup RTCEx_Backup_Registers_Definitions RTCEx Backup Registers Definition
00102   * @{
00103   */
00104 #define RTC_BKP_DR0                       ((uint32_t)0x00000000U)
00105 #define RTC_BKP_DR1                       ((uint32_t)0x00000001U)
00106 #define RTC_BKP_DR2                       ((uint32_t)0x00000002U)
00107 #define RTC_BKP_DR3                       ((uint32_t)0x00000003U)
00108 #define RTC_BKP_DR4                       ((uint32_t)0x00000004U)
00109 #define RTC_BKP_DR5                       ((uint32_t)0x00000005U)
00110 #define RTC_BKP_DR6                       ((uint32_t)0x00000006U)
00111 #define RTC_BKP_DR7                       ((uint32_t)0x00000007U)
00112 #define RTC_BKP_DR8                       ((uint32_t)0x00000008U)
00113 #define RTC_BKP_DR9                       ((uint32_t)0x00000009U)
00114 #define RTC_BKP_DR10                      ((uint32_t)0x0000000AU)
00115 #define RTC_BKP_DR11                      ((uint32_t)0x0000000BU)
00116 #define RTC_BKP_DR12                      ((uint32_t)0x0000000CU)
00117 #define RTC_BKP_DR13                      ((uint32_t)0x0000000DU)
00118 #define RTC_BKP_DR14                      ((uint32_t)0x0000000EU)
00119 #define RTC_BKP_DR15                      ((uint32_t)0x0000000FU)
00120 #define RTC_BKP_DR16                      ((uint32_t)0x00000010U)
00121 #define RTC_BKP_DR17                      ((uint32_t)0x00000011U)
00122 #define RTC_BKP_DR18                      ((uint32_t)0x00000012U)
00123 #define RTC_BKP_DR19                      ((uint32_t)0x00000013U)
00124
00125 /**
00126   * @}
00127   */
00128
00129
00130 /** @defgroup RTCEx_Time_Stamp_Edges_definitions RTCEx Time Stamp Edges definition
00131   * @{
00132   */
00133 #define RTC_TIMESTAMPEDGE_RISING        ((uint32_t)0x00000000U)
00134 #define RTC_TIMESTAMPEDGE_FALLING       RTC_CR_TSEDGE
00135
00136 /**
00137   * @}
00138   */
00139
00140 /** @defgroup RTCEx_TimeStamp_Pin_Selections RTCEx TimeStamp Pin Selection
00141   * @{
00142   */
00143 #define RTC_TIMESTAMPPIN_DEFAULT              ((uint32_t)0x00000000U)
00144
00145 /**
00146   * @}
00147   */
00148
00149
00150 /** @defgroup RTCEx_Tamper_Pins_Definitions RTCEx Tamper Pins Definition
00151   * @{
00152   */
00153 #if defined(RTC_TAMPER1_SUPPORT)
00154 #define RTC_TAMPER_1                       RTC_TAMPCR_TAMP1E
00155 #endif /* RTC_TAMPER1_SUPPORT */
00156
00157 #define RTC_TAMPER_2                       RTC_TAMPCR_TAMP2E
00158
00159 #if defined(RTC_TAMPER3_SUPPORT)
00160 #define RTC_TAMPER_3                       RTC_TAMPCR_TAMP3E
00161 #endif /* RTC_TAMPER3_SUPPORT */
00162 /**
00163   * @}
00164   */
00165
00166
00167 /** @defgroup RTCEx_Tamper_Interrupt_Definitions RTCEx Tamper Interrupt Definitions
00168   * @{
00169   */
00170 #if defined(RTC_TAMPER1_SUPPORT)
00171 #define RTC_TAMPER1_INTERRUPT              RTC_TAMPCR_TAMP1IE
00172 #endif /* RTC_TAMPER1_SUPPORT */
00173
00174
00175 #define RTC_TAMPER2_INTERRUPT              RTC_TAMPCR_TAMP2IE
00176
00177 #if defined(RTC_TAMPER3_SUPPORT)
00178 #define RTC_TAMPER3_INTERRUPT              RTC_TAMPCR_TAMP3IE
00179 #endif /* RTC_TAMPER3_SUPPORT */
00180 #define RTC_ALL_TAMPER_INTERRUPT             RTC_TAMPCR_TAMPIE
00181 /**
00182   * @}
00183   */
00184
00185 /** @defgroup RTCEx_Tamper_Trigger_Definitions RTCEx Tamper Trigger Definitions
00186   * @{
00187   */
00188 #define RTC_TAMPERTRIGGER_RISINGEDGE       ((uint32_t)0x00000000U)
00189 #define RTC_TAMPERTRIGGER_FALLINGEDGE      ((uint32_t)0x00000002U)
00190 #define RTC_TAMPERTRIGGER_LOWLEVEL         RTC_TAMPERTRIGGER_RISINGEDGE
00191 #define RTC_TAMPERTRIGGER_HIGHLEVEL        RTC_TAMPERTRIGGER_FALLINGEDGE
00192
00193 /**
00194   * @}
00195   */
00196
00197 /** @defgroup RTCEx_Tamper_EraseBackUp_Definitions RTCEx Tamper EraseBackUp Definitions
00198 * @{
00199 */
00200 #define RTC_TAMPER_ERASE_BACKUP_ENABLE               ((uint32_t)0x00000000U)
00201 #define RTC_TAMPER_ERASE_BACKUP_DISABLE              ((uint32_t)0x00020000U)
00202 /**
00203   * @}
00204   */
00205
00206 /** @defgroup RTCEx_Tamper_MaskFlag_Definitions RTCEx Tamper MaskFlag Definitions
00207 * @{
00208 */
00209 #define RTC_TAMPERMASK_FLAG_DISABLE               ((uint32_t)0x00000000U)
00210 #define RTC_TAMPERMASK_FLAG_ENABLE                ((uint32_t)0x00040000U)
00211
00212 /**
00213   * @}
00214   */
00215
00216 /** @defgroup RTCEx_Tamper_Filter_Definitions RTCEx Tamper Filter Definitions
00217   * @{
00218   */
00219 #define RTC_TAMPERFILTER_DISABLE   ((uint32_t)0x00000000U)  /*!< Tamper filter is disabled */
00220
00221 #define RTC_TAMPERFILTER_2SAMPLE   RTC_TAMPCR_TAMPFLT_0    /*!< Tamper is activated after 2
00222                                                                 consecutive samples at the active level */
00223 #define RTC_TAMPERFILTER_4SAMPLE   RTC_TAMPCR_TAMPFLT_1    /*!< Tamper is activated after 4
00224                                                                 consecutive samples at the active level */
00225 #define RTC_TAMPERFILTER_8SAMPLE   RTC_TAMPCR_TAMPFLT      /*!< Tamper is activated after 8
00226                                                                 consecutive samples at the active leve. */
00227
00228 /**
00229   * @}
00230   */
00231
00232 /** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTCEx Tamper Sampling Frequencies Definitions
00233   * @{
00234   */
00235 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768  ((uint32_t)0x00000000U)                                         /*!< Each of the tamper inputs are sampled
00236                                                                                                                     with a frequency =  RTCCLK / 32768 */
00237 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384  RTC_TAMPCR_TAMPFREQ_0                                          /*!< Each of the tamper inputs are sampled
00238                                                                                                                     with a frequency =  RTCCLK / 16384 */
00239 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192   RTC_TAMPCR_TAMPFREQ_1                                          /*!< Each of the tamper inputs are sampled
00240                                                                                                                     with a frequency =  RTCCLK / 8192  */
00241 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096   ((uint32_t) (RTC_TAMPCR_TAMPFREQ_0 | RTC_TAMPCR_TAMPFREQ_1))   /*!< Each of the tamper inputs are sampled
00242                                                                                                                     with a frequency =  RTCCLK / 4096  */
00243 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048   RTC_TAMPCR_TAMPFREQ_2                                          /*!< Each of the tamper inputs are sampled
00244                                                                                                                     with a frequency =  RTCCLK / 2048  */
00245 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024   ((uint32_t) (RTC_TAMPCR_TAMPFREQ_0 | RTC_TAMPCR_TAMPFREQ_2))   /*!< Each of the tamper inputs are sampled
00246                                                                                                                     with a frequency =  RTCCLK / 1024  */
00247 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512    ((uint32_t) (RTC_TAMPCR_TAMPFREQ_1 | RTC_TAMPCR_TAMPFREQ_2))   /*!< Each of the tamper inputs are sampled
00248                                                                                                                     with a frequency =  RTCCLK / 512   */
00249 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256    ((uint32_t) (RTC_TAMPCR_TAMPFREQ_0 | RTC_TAMPCR_TAMPFREQ_1 | \
00250                                                  RTC_TAMPCR_TAMPFREQ_2))                                       /*!< Each of the tamper inputs are sampled
00251                                                                                                                     with a frequency =  RTCCLK / 256   */
00252
00253 /**
00254   * @}
00255   */
00256
00257 /** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTCEx Tamper Pin Precharge Duration Definitions
00258   * @{
00259   */
00260 #define RTC_TAMPERPRECHARGEDURATION_1RTCCLK  ((uint32_t)0x00000000U)                                     /*!< Tamper pins are pre-charged before
00261                                                                                                             sampling during 1 RTCCLK cycle  */
00262 #define RTC_TAMPERPRECHARGEDURATION_2RTCCLK  RTC_TAMPCR_TAMPPRCH_0                                      /*!< Tamper pins are pre-charged before
00263                                                                                                              sampling during 2 RTCCLK cycles */
00264 #define RTC_TAMPERPRECHARGEDURATION_4RTCCLK  RTC_TAMPCR_TAMPPRCH_1                                      /*!< Tamper pins are pre-charged before
00265                                                                                                              sampling during 4 RTCCLK cycles */
00266 #define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)(RTC_TAMPCR_TAMPPRCH_0 | RTC_TAMPCR_TAMPPRCH_1)) /*!< Tamper pins are pre-charged before
00267                                                                                                              sampling during 8 RTCCLK cycles */
00268
00269 /**
00270   * @}
00271   */
00272
00273 /** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTCEx Tamper TimeStampOnTamperDetection Definitions
00274   * @{
00275   */
00276 #define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE  RTC_TAMPCR_TAMPTS       /*!< TimeStamp on Tamper Detection event saved        */
00277 #define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000U)  /*!< TimeStamp on Tamper Detection event is not saved */
00278
00279 /**
00280   * @}
00281   */
00282
00283 /** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTCEx Tamper Pull UP Definitions
00284   * @{
00285   */
00286 #define RTC_TAMPER_PULLUP_ENABLE  ((uint32_t)0x00000000U)  /*!< Tamper pins are pre-charged before sampling */
00287 #define RTC_TAMPER_PULLUP_DISABLE  RTC_TAMPCR_TAMPPUDIS   /*!< Tamper pins pre-charge is disabled          */
00288
00289 /**
00290   * @}
00291   */
00292
00293 /** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definitions
00294   * @{
00295   */
00296 #define RTC_WAKEUPCLOCK_RTCCLK_DIV16        ((uint32_t)0x00000000U)
00297 #define RTC_WAKEUPCLOCK_RTCCLK_DIV8         RTC_CR_WUCKSEL_0
00298 #define RTC_WAKEUPCLOCK_RTCCLK_DIV4         RTC_CR_WUCKSEL_1
00299 #define RTC_WAKEUPCLOCK_RTCCLK_DIV2         ((uint32_t) (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1))
00300 #define RTC_WAKEUPCLOCK_CK_SPRE_16BITS      RTC_CR_WUCKSEL_2
00301 #define RTC_WAKEUPCLOCK_CK_SPRE_17BITS      ((uint32_t) (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2))
00302 /**
00303   * @}
00304   */
00305
00306 /** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth calib period Definitions
00307   * @{
00308   */
00309 #define RTC_SMOOTHCALIB_PERIOD_32SEC   ((uint32_t)0x00000000U)   /*!< If RTCCLK = 32768 Hz, Smooth calibation
00310                                                                      period is 32s,  else 2exp20 RTCCLK pulses */
00311 #define RTC_SMOOTHCALIB_PERIOD_16SEC   RTC_CALR_CALW16          /*!< If RTCCLK = 32768 Hz, Smooth calibation
00312                                                                      period is 16s, else 2exp19 RTCCLK pulses */
00313 #define RTC_SMOOTHCALIB_PERIOD_8SEC    RTC_CALR_CALW8           /*!< If RTCCLK = 32768 Hz, Smooth calibation
00314                                                                      period is 8s, else 2exp18 RTCCLK pulses */
00315
00316 /**
00317   * @}
00318   */
00319
00320 /** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTCEx Smooth calib Plus pulses Definitions
00321   * @{
00322   */
00323 #define RTC_SMOOTHCALIB_PLUSPULSES_SET    RTC_CALR_CALP            /*!< The number of RTCCLK pulses added
00324                                                                         during a X -second window = Y - CALM[8:0]
00325                                                                         with Y = 512, 256, 128 when X = 32, 16, 8 */
00326 #define RTC_SMOOTHCALIB_PLUSPULSES_RESET  ((uint32_t)0x00000000U)   /*!< The number of RTCCLK pulses subbstited
00327                                                                         during a 32-second window = CALM[8:0] */
00328
00329 /**
00330   * @}
00331   */
00332  /** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definitions
00333   * @{
00334   */
00335 #define RTC_CALIBOUTPUT_512HZ            ((uint32_t)0x00000000U)
00336 #define RTC_CALIBOUTPUT_1HZ              RTC_CR_COSEL
00337
00338 /**
00339   * @}
00340   */
00341
00342
00343 /** @defgroup RTCEx_Add_1_Second_Parameter_Definition RTCEx Add 1 Second Parameter Definitions
00344   * @{
00345   */
00346 #define RTC_SHIFTADD1S_RESET      ((uint32_t)0x00000000U)
00347 #define RTC_SHIFTADD1S_SET        RTC_SHIFTR_ADD1S
00348 /**
00349   * @}
00350   */
00351   /** @defgroup RTCEx_Interrupts_Definitions RTCEx Interrupts Definitions
00352   * @{
00353   */
00354 #if defined(RTC_TAMPER3_SUPPORT)
00355 #define RTC_IT_TAMP3                      ((uint32_t)RTC_TAMPCR_TAMP3IE)  /*!< Enable Tamper 3 Interrupt     */
00356 #endif
00357 /**
00358   * @}
00359   */
00360
00361 /** @defgroup RTCEx_Flags_Definitions RTCEx Flags Definitions
00362   * @{
00363   */
00364 #if defined(RTC_TAMPER3_SUPPORT)
00365 #define RTC_FLAG_TAMP3F                   ((uint32_t)RTC_ISR_TAMP3F)
00366 #endif
00367 /**
00368   * @}
00369   */
00370
00371 /**
00372   * @}
00373   */
00374
00375 /* Exported macros -----------------------------------------------------------*/
00376 /** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros
00377   * @{
00378   */
00379
00380 /* ---------------------------------WAKEUPTIMER---------------------------------*/
00381 /** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer
00382   * @{
00383   */
00384 /**
00385   * @brief  Enable the RTC WakeUp Timer peripheral.
00386   * @param __HANDLE__ specifies the RTC handle.
00387   * @retval None
00388   */
00389 #define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
00390
00391 /**
00392   * @brief  Disable the RTC WakeUp Timer peripheral.
00393   * @param __HANDLE__ specifies the RTC handle.
00394   * @retval None
00395   */
00396 #define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__)                     ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
00397
00398 /**
00399   * @brief  Enable the RTC WakeUpTimer interrupt.
00400   * @param __HANDLE__ specifies the RTC handle.
00401   * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled.
00402   *         This parameter can be:
00403   *            @arg RTC_IT_WUT: WakeUpTimer interrupt
00404   * @retval None
00405   */
00406 #define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
00407
00408 /**
00409   * @brief  Disable the RTC WakeUpTimer interrupt.
00410   * @param __HANDLE__ specifies the RTC handle.
00411   * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be disabled.
00412   *         This parameter can be:
00413   *            @arg RTC_IT_WUT: WakeUpTimer interrupt
00414   * @retval None
00415   */
00416 #define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
00417
00418 /**
00419   * @brief  Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
00420   * @param __HANDLE__ specifies the RTC handle.
00421   * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt to check.
00422   *         This parameter can be:
00423   *            @arg RTC_IT_WUT:  WakeUpTimer interrupt
00424   * @retval None
00425   */
00426 #define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__)       (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != 0U) ? 1U : 0U)
00427
00428 /**
00429   * @brief  Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
00430   * @param __HANDLE__ specifies the RTC handle.
00431   * @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check.
00432   *         This parameter can be:
00433   *            @arg RTC_IT_WUT:  WakeUpTimer interrupt
00434   * @retval None
00435   */
00436 #define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)   (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
00437
00438 /**
00439   * @brief  Get the selected RTC WakeUpTimer's flag status.
00440   * @param __HANDLE__ specifies the RTC handle.
00441   * @param __FLAG__ specifies the RTC WakeUpTimer Flag is pending or not.
00442   *          This parameter can be:
00443   *             @arg RTC_FLAG_WUTF
00444   *             @arg RTC_FLAG_WUTWF
00445   * @retval None
00446   */
00447 #define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__)   (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)
00448
00449 /**
00450   * @brief  Clear the RTC Wake Up timer's pending flags.
00451   * @param __HANDLE__ specifies the RTC handle.
00452   * @param __FLAG__ specifies the RTC WakeUpTimer Flag to clear.
00453   *         This parameter can be:
00454   *            @arg RTC_FLAG_WUTF
00455   * @retval None
00456   */
00457 #define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
00458
00459 /**
00460   * @brief  Enable interrupt on the RTC WakeUp Timer associated Exti line of core 1.
00461   * @retval None
00462   */
00463 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT()       (EXTI->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00464
00465 /**
00466   * @brief  Disable interrupt on the RTC WakeUp Timer associated Exti line of core 1.
00467   * @retval None
00468   */
00469 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT()      (EXTI->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
00470
00471
00472 /**
00473   * @brief  Enable interrupt on the RTC WakeUp Timer associated Exti line of core 2.
00474   * @retval None
00475   */
00476 #define __HAL_RTC_WAKEUPTIMER_EXTIC2_ENABLE_IT()       (EXTI->C2IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00477
00478 /**
00479   * @brief  Disable interrupt on the RTC WakeUp Timer associated Exti line of core 2.
00480   * @retval None
00481   */
00482 #define __HAL_RTC_WAKEUPTIMER_EXTIC2_DISABLE_IT()      (EXTI->C2IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
00483
00484
00485 /**
00486   * @brief  Enable event on the RTC WakeUp Timer associated Exti line of core 1.
00487   * @retval None.
00488   */
00489 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT()    (EXTI->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00490
00491 /**
00492   * @brief  Enable event on the RTC WakeUp Timer associated Exti line of core 2.
00493   * @retval None.
00494   */
00495 #define __HAL_RTC_WAKEUPTIMER_EXTIC2_ENABLE_EVENT()    (EXTI->C2EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00496
00497
00498 /**
00499   * @brief  Disable event on the RTC WakeUp Timer associated Exti line of core 1.
00500   * @retval None.
00501   */
00502 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT()   (EXTI->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
00503
00504 /**
00505   * @brief  Disable event on the RTC WakeUp Timer associated Exti line of core 2.
00506   * @retval None.
00507   */
00508 #define __HAL_RTC_WAKEUPTIMER_EXTIC2_DISABLE_EVENT()   (EXTI->C2EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
00509
00510
00511 /*---------------*/
00512 /**
00513   * @brief  Enable falling edge trigger on the RTC WakeUp Timer associated Exti line.
00514   * @retval None.
00515   */
00516 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00517
00518 /**
00519   * @brief  Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.
00520   * @retval None.
00521   */
00522 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
00523
00524 /**
00525   * @brief  Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.
00526   * @retval None.
00527   */
00528 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00529
00530 /**
00531   * @brief  Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.
00532   * @retval None.
00533   */
00534 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
00535
00536
00537 /**
00538   * @brief  Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
00539   * @retval None
00540   */
00541 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE()  do { \
00542                                                                    __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();  \
00543                                                                    __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); \
00544                                                                  } while(0U)
00545
00546 /**
00547   * @brief  Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
00548   * This parameter can be:
00549   * @retval None
00550   */
00551 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE()  do { \
00552                                                                    __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();  \
00553                                                                    __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); \
00554                                                                   } while(0U)
00555
00556 /**
00557   * @brief Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not of core 1.
00558   * @retval Line Status.
00559   */
00560 #define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG()              (EXTI->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00561
00562 /**
00563   * @brief Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not of core 2.
00564   * @retval Line Status.
00565   */
00566 #define __HAL_RTC_WAKEUPTIMER_EXTIC2_GET_FLAG()            (EXTI->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00567
00568
00569
00570 /**
00571   * @brief Clear the RTC WakeUp Timer associated Exti line flag of core 1.
00572   * @retval None.
00573   */
00574 #define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG()            (EXTI->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00575
00576 /**
00577   * @brief Clear the RTC WakeUp Timer associated Exti line flag of core 2.
00578   * @retval None.
00579   */
00580 #define __HAL_RTC_WAKEUPTIMER_EXTIC2_CLEAR_FLAG()          (EXTI->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00581
00582
00583 /*---------------*/
00584 /**
00585   * @brief Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.
00586   * @retval None.
00587   */
00588 #define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT()         (EXTI->SWIER1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
00589 /*---------------*/
00590
00591 /**
00592   * @}
00593   */
00594
00595 /* ---------------------------------TIMESTAMP---------------------------------*/
00596 /** @defgroup RTCEx_Timestamp RTC Timestamp
00597   * @{
00598   */
00599 /**
00600   * @brief  Enable the RTC TimeStamp peripheral.
00601   * @param __HANDLE__ specifies the RTC handle.
00602   * @retval None
00603   */
00604 #define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__)                       ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
00605
00606 /**
00607   * @brief  Disable the RTC TimeStamp peripheral.
00608   * @param __HANDLE__ specifies the RTC handle.
00609   * @retval None
00610   */
00611 #define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
00612
00613 /**
00614   * @brief  Enable the RTC TimeStamp interrupt.
00615   * @param __HANDLE__ specifies the RTC handle.
00616   * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be enabled.
00617   *         This parameter can be:
00618   *            @arg RTC_IT_TS: TimeStamp interrupt
00619   * @retval None
00620   */
00621 #define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
00622
00623 /**
00624   * @brief  Disable the RTC TimeStamp interrupt.
00625   * @param __HANDLE__ specifies the RTC handle.
00626   * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be disabled.
00627   *         This parameter can be:
00628   *            @arg RTC_IT_TS: TimeStamp interrupt
00629   * @retval None
00630   */
00631 #define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
00632
00633 /**
00634   * @brief  Check whether the specified RTC TimeStamp interrupt has occurred or not.
00635   * @param __HANDLE__ specifies the RTC handle.
00636   * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt to check.
00637   *         This parameter can be:
00638   *            @arg RTC_IT_TS: TimeStamp interrupt
00639   * @retval None
00640   */
00641 #define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__)        (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != 0U) ? 1U : 0U)
00642
00643 /**
00644   * @brief  Check whether the specified RTC Time Stamp interrupt has been enabled or not.
00645   * @param __HANDLE__ specifies the RTC handle.
00646   * @param __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check.
00647   *         This parameter can be:
00648   *            @arg RTC_IT_TS: TimeStamp interrupt
00649   * @retval None
00650   */
00651 #define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
00652
00653 /**
00654   * @brief  Get the selected RTC TimeStamp's flag status.
00655   * @param __HANDLE__ specifies the RTC handle.
00656   * @param __FLAG__ specifies the RTC TimeStamp Flag is pending or not.
00657   *         This parameter can be:
00658   *            @arg RTC_FLAG_TSF
00659   *            @arg RTC_FLAG_TSOVF
00660   * @retval None
00661   */
00662 #define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)     (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)
00663
00664 /**
00665   * @brief  Clear the RTC Time Stamp's pending flags.
00666   * @param __HANDLE__ specifies the RTC handle.
00667   * @param __FLAG__ specifies the RTC TimeStamp Flag to clear.
00668   *          This parameter can be:
00669   *             @arg RTC_FLAG_TSF
00670   *             @arg RTC_FLAG_TSOVF
00671   * @retval None
00672   */
00673 #define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)   ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
00674
00675
00676 /**
00677   * @}
00678   */
00679
00680 /* ---------------------------------TAMPER------------------------------------*/
00681 /** @defgroup RTCEx_Tamper RTC Tamper
00682   * @{
00683   */
00684
00685 #if defined(RTC_TAMPER1_SUPPORT)
00686 /**
00687   * @brief  Enable the RTC Tamper1 input detection.
00688   * @param __HANDLE__ specifies the RTC handle.
00689   * @retval None
00690   */
00691 #define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E))
00692
00693 /**
00694   * @brief  Disable the RTC Tamper1 input detection.
00695   * @param __HANDLE__ specifies the RTC handle.
00696   * @retval None
00697   */
00698 #define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E))
00699 #endif /* RTC_TAMPER1_SUPPORT */
00700
00701 /**
00702   * @brief  Enable the RTC Tamper2 input detection.
00703   * @param __HANDLE__ specifies the RTC handle.
00704   * @retval None
00705   */
00706 #define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E))
00707
00708 /**
00709   * @brief  Disable the RTC Tamper2 input detection.
00710   * @param __HANDLE__ specifies the RTC handle.
00711   * @retval None
00712   */
00713 #define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E))
00714
00715 #if defined(RTC_TAMPER3_SUPPORT)
00716 /**
00717   * @brief  Enable the RTC Tamper3 input detection.
00718   * @param __HANDLE__ specifies the RTC handle.
00719   * @retval None
00720   */
00721 #define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E))
00722
00723 /**
00724   * @brief  Disable the RTC Tamper3 input detection.
00725   * @param __HANDLE__ specifies the RTC handle.
00726   * @retval None
00727   */
00728 #define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E))
00729 #endif /* RTC_TAMPER3_SUPPORT */
00730
00731
00732 /**************************************************************************************************/
00733
00734 /**
00735   * @brief  Enable the RTC Tamper interrupt.
00736   * @param __HANDLE__ specifies the RTC handle.
00737   * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled.
00738   *          This parameter can be any combination of the following values:
00739   *             @arg  RTC_IT_TAMP: All tampers interrupts
00740   *             @arg  RTC_IT_TAMP1: Tamper1 interrupt (*)
00741   *             @arg  RTC_IT_TAMP2: Tamper2 interrupt
00742   *             @arg  RTC_IT_TAMP3: Tamper3 interrupt (*)
00743   *
00744   *         (*)  Value not defined in all devices. \n
00745   *
00746   * @retval None
00747   */
00748 #define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__)        ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__))
00749
00750 /**
00751   * @brief  Disable the RTC Tamper interrupt.
00752   * @param __HANDLE__ specifies the RTC handle.
00753   * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled.
00754   *         This parameter can be any combination of the following values:
00755   *             @arg  RTC_IT_TAMP: All tampers interrupts
00756   *             @arg  RTC_IT_TAMP1: Tamper1 interrupt (*)
00757   *             @arg  RTC_IT_TAMP2: Tamper2 interrupt
00758   *             @arg  RTC_IT_TAMP3: Tamper3 interrupt (*)
00759   *
00760   *         (*)  Value not defined in all devices. \n
00761   *
00762   * @retval None
00763   */
00764 #define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__)       ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__))
00765
00766 /**************************************************************************************************/
00767
00768 /**
00769   * @brief  Check whether the specified RTC Tamper interrupt has occurred or not.
00770   * @param __HANDLE__ specifies the RTC handle.
00771   * @param __INTERRUPT__ specifies the RTC Tamper interrupt to check.
00772   *         This parameter can be:
00773   *             @arg  RTC_IT_TAMP1: Tamper1 interrupt (*)
00774   *             @arg  RTC_IT_TAMP2: Tamper2 interrupt
00775   *             @arg  RTC_IT_TAMP3: Tamper3 interrupt (*)
00776   *
00777   *         (*)  Value not defined in all devices. \n
00778   *
00779   * @retval None
00780   */
00781 #if defined(RTC_TAMPER1_SUPPORT) && defined(RTC_TAMPER3_SUPPORT)
00782 #define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)    (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3U)) != 0U) ? 1U : 0U) : \
00783                                                                ((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5U)) != 0U) ? 1U : 0U) : \
00784                                                                ((__INTERRUPT__) == RTC_IT_TAMP3) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7U)) != 0U) ? 1U : 0U))
00785 #else
00786 #define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)    (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3U)) != 0U) ? 1U : 0U))
00787 #endif
00788
00789 /**************************************************************************************************/
00790
00791 /**
00792   * @brief  Check whether the specified RTC Tamper interrupt has been enabled or not.
00793   * @param __HANDLE__ specifies the RTC handle.
00794   * @param __INTERRUPT__ specifies the RTC Tamper interrupt source to check.
00795   *         This parameter can be:
00796   *            @arg  RTC_IT_TAMP: All tampers interrupts
00797   *             @arg  RTC_IT_TAMP1: Tamper1 interrupt (*)
00798   *             @arg  RTC_IT_TAMP2: Tamper2 interrupt
00799   *             @arg  RTC_IT_TAMP3: Tamper3 interrupt (*)
00800   *
00801   *         (*)  Value not defined in all devices. \n
00802   *
00803   * @retval None
00804   */
00805 #define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)    (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
00806
00807
00808 /**
00809   * @brief  Get the selected RTC Tamper's flag status.
00810   * @param __HANDLE__ specifies the RTC handle.
00811   * @param __FLAG__ specifies the RTC Tamper Flag is pending or not.
00812   *          This parameter can be:
00813   *             @arg RTC_FLAG_TAMP1F: Tamper1 flag (*)
00814   *             @arg RTC_FLAG_TAMP2F: Tamper2 flag
00815   *             @arg RTC_FLAG_TAMP3F: Tamper3 flag (*)
00816   *
00817   *         (*)  Value not defined in all devices. \n
00818   *
00819   * @retval None
00820   */
00821 #define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__)        (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)
00822
00823 /**
00824   * @brief  Clear the RTC Tamper's pending flags.
00825   * @param __HANDLE__ specifies the RTC handle.
00826   * @param __FLAG__ specifies the RTC Tamper Flag to clear.
00827   *          This parameter can be:
00828   *             @arg RTC_FLAG_TAMP1F: Tamper1 flag (*)
00829   *             @arg RTC_FLAG_TAMP2F: Tamper2 flag
00830   *             @arg RTC_FLAG_TAMP3F: Tamper3 flag (*)
00831   *
00832   *         (*)  Value not defined in all devices. \n
00833   *
00834   * @retval None
00835   */
00836 #define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
00837
00838
00839 /**************************************************************************************************/
00840
00841
00842 #if defined(RTC_INTERNALTS_SUPPORT)
00843 /**
00844   * @brief  Enable the RTC internal TimeStamp peripheral.
00845   * @param __HANDLE__ specifies the RTC handle.
00846   * @retval None
00847   */
00848 #define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE))
00849
00850 /**
00851   * @brief  Disable the RTC internal TimeStamp peripheral.
00852   * @param __HANDLE__ specifies the RTC handle.
00853   * @retval None
00854   */
00855 #define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE))
00856
00857 /**
00858   * @brief  Get the selected RTC Internal Time Stamp's flag status.
00859   * @param __HANDLE__ specifies the RTC handle.
00860   * @param __FLAG__ specifies the RTC Internal Time Stamp Flag is pending or not.
00861   *         This parameter can be:
00862   *            @arg RTC_FLAG_ITSF
00863   * @retval None
00864   */
00865 #define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)    (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)
00866
00867 /**
00868   * @brief  Clear the RTC Internal Time Stamp's pending flags.
00869   * @param __HANDLE__ specifies the RTC handle.
00870   * @param __FLAG__ specifies the RTC Internal Time Stamp Flag source to clear.
00871   *          This parameter can be:
00872   *             @arg RTC_FLAG_ITSF
00873   * @retval None
00874   */
00875 #define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)  ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
00876 #endif
00877 /**************************************************************************************************/
00878
00879 /**
00880   * @}
00881   */
00882
00883 /* --------------------------TAMPER/TIMESTAMP---------------------------------*/
00884 /** @defgroup RTCEx_Tamper_Timestamp EXTI RTC Tamper Timestamp EXTI
00885   * @{
00886   */
00887
00888 /* TAMPER TIMESTAMP EXTI */
00889 /* --------------------- */
00890
00891 /**
00892   * @brief  Enable interrupt on the RTC Tamper and Timestamp associated Exti line of core 1.
00893   * @retval None
00894   */
00895 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()        (EXTI->IMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00896
00897 /**
00898   * @brief  Enable interrupt on the RTC Tamper and Timestamp associated Exti line of core 2.
00899   * @retval None
00900   */
00901 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_ENABLE_IT()      (EXTI->C2IMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00902
00903 /**
00904   * @brief  Disable interrupt on the RTC Tamper and Timestamp associated Exti line of core 1.
00905   * @retval None
00906   */
00907 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()       (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
00908
00909 /**
00910   * @brief  Disable interrupt on the RTC Tamper and Timestamp associated Exti line of core 2.
00911   * @retval None
00912   */
00913 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_DISABLE_IT()     (EXTI->C2IMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
00914
00915 /**
00916   * @brief  Enable event on the RTC Tamper and Timestamp associated Exti line of core 1.
00917   * @retval None.
00918   */
00919 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT()    (EXTI->EMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00920
00921 /**
00922   * @brief  Enable event on the RTC Tamper and Timestamp associated Exti line of core 2.
00923   * @retval None.
00924   */
00925 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_ENABLE_EVENT()  (EXTI->C2EMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00926
00927 /**
00928   * @brief  Disable event on the RTC Tamper and Timestamp associated Exti line of core 1.
00929   * @retval None.
00930   */
00931 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT()   (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
00932
00933 /**
00934   * @brief  Disable event on the RTC Tamper and Timestamp associated Exti line of core 2.
00935   * @retval None.
00936   */
00937 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_DISABLE_EVENT() (EXTI->C2EMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
00938
00939 /*-----------------*/
00940 /**
00941   * @brief  Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
00942   * @retval None.
00943   */
00944 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00945
00946 /**
00947   * @brief  Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
00948   * @retval None.
00949   */
00950 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
00951
00952 /**
00953   * @brief  Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
00954   * @retval None.
00955   */
00956 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00957
00958 /**
00959   * @brief  Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
00960   * @retval None.
00961   */
00962 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
00963
00964
00965 /**
00966   * @brief  Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
00967   * @retval None.
00968   */
00969 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE()  do { \
00970                                                                         __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();  \
00971                                                                         __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); \
00972                                                                       } while(0U)
00973
00974 /**
00975   * @brief  Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
00976   * This parameter can be:
00977   * @retval None.
00978   */
00979 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE()  do { \
00980                                                                         __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();  \
00981                                                                         __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE(); \
00982                                                                        } while(0U)
00983
00984 /**
00985   * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not of core 1.
00986   * @retval Line Status.
00987   */
00988 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()         (EXTI->PR1 & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00989
00990 /**
00991   * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not of core 2.
00992   * @retval Line Status.
00993   */
00994 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_GET_FLAG()       (EXTI->PR2 & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
00995
00996 /**
00997   * @brief Clear the RTC Tamper and Timestamp associated Exti line flag of core 1.
00998   * @retval None.
00999   */
01000 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()       (EXTI->PR1 = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
01001
01002 /**
01003   * @brief Clear the RTC Tamper and Timestamp associated Exti line flag of core 2.
01004   * @retval None.
01005   */
01006 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTIC2_CLEAR_FLAG()     (EXTI->PR1 = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
01007
01008 /**
01009   * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line
01010   * @retval None.
01011   */
01012 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()    (EXTI->SWIER1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
01013
01014
01015
01016 /**
01017   * @}
01018   */
01019
01020 /* ------------------------------Calibration----------------------------------*/
01021 /** @defgroup RTCEx_Calibration RTC Calibration
01022   * @{
01023   */
01024
01025 /**
01026   * @brief  Enable the RTC calibration output.
01027   * @param __HANDLE__ specifies the RTC handle.
01028   * @retval None
01029   */
01030 #define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
01031
01032 /**
01033   * @brief  Disable the calibration output.
01034   * @param __HANDLE__ specifies the RTC handle.
01035   * @retval None
01036   */
01037 #define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
01038
01039
01040 /**
01041   * @brief  Enable the clock reference detection.
01042   * @param __HANDLE__ specifies the RTC handle.
01043   * @retval None
01044   */
01045 #define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
01046
01047 /**
01048   * @brief  Disable the clock reference detection.
01049   * @param __HANDLE__ specifies the RTC handle.
01050   * @retval None
01051   */
01052 #define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
01053
01054
01055 /**
01056   * @brief  Get the selected RTC shift operation's flag status.
01057   * @param __HANDLE__ specifies the RTC handle.
01058   * @param __FLAG__ specifies the RTC shift operation Flag is pending or not.
01059   *          This parameter can be:
01060   *             @arg RTC_FLAG_SHPF
01061   * @retval None
01062   */
01063 #define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__)                (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U)
01064 /**
01065   * @}
01066   */
01067
01068 /**
01069   * @}
01070   */
01071
01072 /* Exported functions --------------------------------------------------------*/
01073 /** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
01074   * @{
01075   */
01076
01077 /* RTC TimeStamp and Tamper functions *****************************************/
01078 /** @defgroup RTCEx_Exported_Functions_Group1 Extended RTC TimeStamp and Tamper functions
01079  * @{
01080  */
01081
01082 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
01083 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
01084 HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
01085 #if defined(RTC_INTERNALTS_SUPPORT)
01086 HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc);
01087 HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc);
01088 #endif
01089 HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
01090
01091 HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
01092 HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
01093 HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
01094 void              HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
01095
01096 #if defined(RTC_TAMPER1_SUPPORT)
01097 void              HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
01098 #endif /* RTC_TAMPER1_SUPPORT */
01099 void              HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
01100 #if defined(RTC_TAMPER3_SUPPORT)
01101 void              HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc);
01102 #endif /* RTC_TAMPER3_SUPPORT */
01103 void              HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
01104 HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
01105 #if defined(RTC_TAMPER1_SUPPORT)
01106 HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
01107 #endif /* RTC_TAMPER1_SUPPORT */
01108 HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
01109 #if defined(RTC_TAMPER3_SUPPORT)
01110 HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
01111 #endif /* RTC_TAMPER3_SUPPORT */
01112 /**
01113   * @}
01114   */
01115
01116 /* RTC Wake-up functions ******************************************************/
01117 /** @defgroup RTCEx_Exported_Functions_Group2 Extended RTC Wake-up functions
01118  * @{
01119  */
01120
01121 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
01122 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
01123 HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
01124 uint32_t          HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
01125 void              HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
01126 void              HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
01127 HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
01128 /**
01129   * @}
01130   */
01131
01132 /* Extended Control functions ************************************************/
01133 /** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions
01134  * @{
01135  */
01136
01137 void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
01138 uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
01139
01140 HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue);
01141 HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS);
01142 HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput);
01143 HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);
01144 HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);
01145 HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
01146 HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);
01147 HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);
01148 /**
01149   * @}
01150   */
01151
01152 /* Extended RTC features functions *******************************************/
01153 /** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions
01154  * @{
01155  */
01156 void              HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
01157 HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
01158 /**
01159   * @}
01160   */
01161
01162 /**
01163   * @}
01164   */
01165
01166 /* Private types -------------------------------------------------------------*/
01167 /* Private variables ---------------------------------------------------------*/
01168 /* Private constants ---------------------------------------------------------*/
01169 /** @defgroup RTCEx_Private_Constants RTCEx Private Constants
01170   * @{
01171   */
01172
01173 /* Masks Definition */
01174
01175 #if defined(RTC_TAMPER1_SUPPORT) && defined(RTC_TAMPER3_SUPPORT)
01176
01177 #define RTC_FLAGS_MASK          ((uint32_t) (RTC_FLAG_RECALPF | RTC_FLAG_TAMP3F | RTC_FLAG_TAMP2F | \
01178                                              RTC_FLAG_TAMP1F| RTC_FLAG_TSOVF | RTC_FLAG_TSF       | \
01179                                              RTC_FLAG_WUTF | RTC_FLAG_ALRBF | RTC_FLAG_ALRAF      | \
01180                                              RTC_FLAG_INITF | RTC_FLAG_RSF                        | \
01181                                              RTC_FLAG_INITS | RTC_FLAG_SHPF | RTC_FLAG_WUTWF      | \
01182                                              RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF))
01183
01184 #define RTC_TAMPCR_TAMPXE     ((uint32_t) (RTC_TAMPCR_TAMP3E | RTC_TAMPCR_TAMP2E | RTC_TAMPCR_TAMP1E))
01185 #define RTC_TAMPCR_TAMPXIE    ((uint32_t) (RTC_TAMPER1_INTERRUPT | RTC_TAMPER2_INTERRUPT | \
01186                                            RTC_TAMPER3_INTERRUPT | RTC_ALL_TAMPER_INTERRUPT))
01187
01188 #else
01189
01190 #define RTC_FLAGS_MASK          ((uint32_t) (RTC_FLAG_RECALPF | RTC_FLAG_TAMP2F                  |  \
01191                                              RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF       | \
01192                                              RTC_FLAG_ALRBF | RTC_FLAG_ALRAF                     | \
01193                                              RTC_FLAG_INITF | RTC_FLAG_RSF | RTC_FLAG_INITS      | \
01194                                              RTC_FLAG_SHPF | RTC_FLAG_WUTWF |RTC_FLAG_ALRBWF     | \
01195                                              RTC_FLAG_ALRAWF))
01196
01197 #define RTC_TAMPCR_TAMPXE     ((uint32_t) (RTC_TAMPCR_TAMP2E))
01198 #define RTC_TAMPCR_TAMPXIE    ((uint32_t) (RTC_TAMPER2_INTERRUPT | RTC_ALL_TAMPER_INTERRUPT))
01199
01200 #endif
01201
01202 #define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT  (EXTI_IMR1_IM18)    /*!< External interrupt line 18 Connected to the RTC Tamper and Time Stamp events */
01203 #define RTC_EXTI_LINE_WAKEUPTIMER_EVENT       (EXTI_IMR1_IM19)    /*!< External interrupt line 19 Connected to the RTC Wakeup event */
01204
01205 /**
01206   * @}
01207   */
01208
01209 /* Private macros ------------------------------------------------------------*/
01210 /** @defgroup RTCEx_Private_Macros RTCEx Private Macros
01211   * @{
01212   */
01213
01214 /** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
01215   * @{
01216   */
01217
01218 #define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
01219                                ((OUTPUT) == RTC_OUTPUT_ALARMA)  || \
01220                                ((OUTPUT) == RTC_OUTPUT_ALARMB)  || \
01221                                ((OUTPUT) == RTC_OUTPUT_WAKEUP))
01222
01223 #define IS_RTC_BKP(BKP)                   ((BKP) < (uint32_t) RTC_BKP_NUMBER)
01224
01225 #define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
01226                                  ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
01227
01228 #define  IS_RTC_TAMPER(TAMPER)  ((((TAMPER) & ((uint32_t)(0xFFFFFFFFU ^ RTC_TAMPCR_TAMPXE))) == 0x00U) && ((TAMPER) != 0U))
01229
01230 #define IS_RTC_TAMPER_INTERRUPT(INTERRUPT) ((((INTERRUPT) & (uint32_t)(0xFFFFFFFFU ^ RTC_TAMPCR_TAMPXIE)) == 0x00U) && ((INTERRUPT) != 0U))
01231
01232 #define IS_RTC_TIMESTAMP_PIN(PIN)  (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
01233
01234 #define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
01235                                         ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
01236                                         ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
01237                                         ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))
01238
01239 #define IS_RTC_TAMPER_ERASE_MODE(MODE)             (((MODE) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \
01240                                                     ((MODE) == RTC_TAMPER_ERASE_BACKUP_DISABLE))
01241
01242 #define IS_RTC_TAMPER_MASKFLAG_STATE(STATE)        (((STATE) == RTC_TAMPERMASK_FLAG_ENABLE) || \
01243                                                     ((STATE) == RTC_TAMPERMASK_FLAG_DISABLE))
01244
01245 #define IS_RTC_TAMPER_FILTER(FILTER)  (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \
01246                                        ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \
01247                                        ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \
01248                                        ((FILTER) == RTC_TAMPERFILTER_8SAMPLE))
01249
01250 #define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
01251                                            ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
01252                                            ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
01253                                            ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
01254                                            ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
01255                                            ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
01256                                            ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512)  || \
01257                                           ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
01258
01259 #define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
01260                                                     ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
01261                                                     ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
01262                                                    ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
01263
01264 #define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
01265                                                               ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
01266
01267 #define IS_RTC_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \
01268                                            ((STATE) == RTC_TAMPER_PULLUP_DISABLE))
01269
01270 #define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16)   || \
01271                                     ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8)    || \
01272                                     ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4)    || \
01273                                     ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2)    || \
01274                                     ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
01275                                     ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
01276
01277 #define IS_RTC_WAKEUP_COUNTER(COUNTER)  ((COUNTER) <= RTC_WUTR_WUT)
01278
01279 #define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
01280                                             ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
01281                                             ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))
01282
01283 #define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
01284                                         ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
01285
01286
01287 /** @defgroup RTCEx_Smooth_calib_Minus_pulses_Definitions RTCEx Smooth calib Minus pulses Definitions
01288   * @{
01289   */
01290 #define  IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= RTC_CALR_CALM)
01291 /**
01292   * @}
01293   */
01294
01295
01296 #define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
01297                                  ((SEL) == RTC_SHIFTADD1S_SET))
01298
01299
01300
01301 /** @defgroup RTCEx_Substract_Fraction_Of_Second_Value RTCEx Substract Fraction Of Second Value
01302   * @{
01303   */
01304 #define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= RTC_SHIFTR_SUBFS)
01305 /**
01306   * @}
01307   */
01308 #define IS_RTC_CALIB_OUTPUT(OUTPUT)  (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
01309                                       ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
01310
01311 /**
01312   * @}
01313   */
01314
01315 /**
01316   * @}
01317   */
01318
01319
01320
01321 /**
01322   * @}
01323   */
01324
01325 /**
01326   * @}
01327   */
01328
01329 #ifdef __cplusplus
01330 }
01331 #endif
01332
01333 #endif /* STM32WBxx_HAL_RTC_EX_H */
01334
01335 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:35 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_sai.c Source File

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stm32wbxx_hal_sai.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_sai.c
00004   * @author  MCD Application Team
00005   * @brief   SAI HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Serial Audio Interface (SAI) peripheral:
00008   *           + Initialization/de-initialization functions
00009   *           + I/O operation functions
00010   *           + Peripheral Control functions
00011   *           + Peripheral State functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                   ##### How to use this driver #####
00016   ==============================================================================
00017
00018   [..]
00019     The SAI HAL driver can be used as follows:
00020
00021     (#) Declare a SAI_HandleTypeDef handle structure (eg. SAI_HandleTypeDef hsai).
00022     (#) Initialize the SAI low level resources by implementing the HAL_SAI_MspInit() API:
00023         (##) Enable the SAI interface clock.
00024         (##) SAI pins configuration:
00025             (+++) Enable the clock for the SAI GPIOs.
00026             (+++) Configure these SAI pins as alternate function pull-up.
00027         (##) NVIC configuration if you need to use interrupt process (HAL_SAI_Transmit_IT()
00028              and HAL_SAI_Receive_IT() APIs):
00029             (+++) Configure the SAI interrupt priority.
00030             (+++) Enable the NVIC SAI IRQ handle.
00031
00032         (##) DMA Configuration if you need to use DMA process (HAL_SAI_Transmit_DMA()
00033              and HAL_SAI_Receive_DMA() APIs):
00034             (+++) Declare a DMA handle structure for the Tx/Rx stream.
00035             (+++) Enable the DMAx interface clock.
00036             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00037             (+++) Configure the DMA Tx/Rx Stream.
00038             (+++) Associate the initialized DMA handle to the SAI DMA Tx/Rx handle.
00039             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
00040                 DMA Tx/Rx Stream.
00041
00042     (#) The initialization can be done by two ways
00043         (##) Expert mode : Initialize the structures Init, FrameInit and SlotInit and call HAL_SAI_Init().
00044         (##) Simplified mode : Initialize the high part of Init Structure and call HAL_SAI_InitProtocol().
00045
00046   [..]
00047     (@) The specific SAI interrupts (FIFO request and Overrun underrun interrupt)
00048         will be managed using the macros __HAL_SAI_ENABLE_IT() and __HAL_SAI_DISABLE_IT()
00049         inside the transmit and receive process.
00050   [..]
00051     (@) Make sure that either:
00052         (+@) PLLSAI1CLK output is configured or
00053         (+@) PLLSAI2CLK output is configured or
00054         (+@) PLLSAI3CLK output is configured or
00055         (+@) External clock source is configured after setting correctly
00056              the define constant EXTERNAL_SAI1_CLOCK_VALUE or EXTERNAL_SAI2_CLOCK_VALUE in the stm32wbxx_hal_conf.h file.
00057
00058   [..]
00059     (@) In master Tx mode: enabling the audio block immediately generates the bit clock
00060         for the external slaves even if there is no data in the FIFO, However FS signal
00061         generation is conditioned by the presence of data in the FIFO.
00062
00063   [..]
00064     (@) In master Rx mode: enabling the audio block immediately generates the bit clock
00065         and FS signal for the external slaves.
00066
00067   [..]
00068     (@) It is mandatory to respect the following conditions in order to avoid bad SAI behavior:
00069         (+@) First bit Offset <= (SLOT size - Data size)
00070         (+@) Data size <= SLOT size
00071         (+@) Number of SLOT x SLOT size = Frame length
00072         (+@) The number of slots should be even when SAI_FS_CHANNEL_IDENTIFICATION is selected.
00073
00074   [..]
00075     (@) PDM interface can be activated through HAL_SAI_Init function.
00076         Please note that PDM interface is only available for SAI1 sub-block A.
00077         PDM microphone delays can be tuned with HAL_SAIEx_ConfigPdmMicDelay function.
00078
00079   [..]
00080     Three operation modes are available within this driver :
00081
00082     *** Polling mode IO operation ***
00083     =================================
00084     [..]
00085       (+) Send an amount of data in blocking mode using HAL_SAI_Transmit()
00086       (+) Receive an amount of data in blocking mode using HAL_SAI_Receive()
00087
00088     *** Interrupt mode IO operation ***
00089     ===================================
00090     [..]
00091       (+) Send an amount of data in non-blocking mode using HAL_SAI_Transmit_IT()
00092       (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can
00093           add his own code by customization of function pointer HAL_SAI_TxCpltCallback()
00094       (+) Receive an amount of data in non-blocking mode using HAL_SAI_Receive_IT()
00095       (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can
00096           add his own code by customization of function pointer HAL_SAI_RxCpltCallback()
00097       (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can
00098           add his own code by customization of function pointer HAL_SAI_ErrorCallback()
00099
00100     *** DMA mode IO operation ***
00101     =============================
00102     [..]
00103       (+) Send an amount of data in non-blocking mode (DMA) using HAL_SAI_Transmit_DMA()
00104       (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can
00105           add his own code by customization of function pointer HAL_SAI_TxCpltCallback()
00106       (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SAI_Receive_DMA()
00107       (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can
00108           add his own code by customization of function pointer HAL_SAI_RxCpltCallback()
00109       (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can
00110           add his own code by customization of function pointer HAL_SAI_ErrorCallback()
00111       (+) Pause the DMA Transfer using HAL_SAI_DMAPause()
00112       (+) Resume the DMA Transfer using HAL_SAI_DMAResume()
00113       (+) Stop the DMA Transfer using HAL_SAI_DMAStop()
00114
00115     *** SAI HAL driver additional function list ***
00116     ===============================================
00117     [..]
00118       Below the list the others API available SAI HAL driver :
00119
00120       (+) HAL_SAI_EnableTxMuteMode(): Enable the mute in tx mode
00121       (+) HAL_SAI_DisableTxMuteMode(): Disable the mute in tx mode
00122       (+) HAL_SAI_EnableRxMuteMode(): Enable the mute in Rx mode
00123       (+) HAL_SAI_DisableRxMuteMode(): Disable the mute in Rx mode
00124       (+) HAL_SAI_FlushRxFifo(): Flush the rx fifo.
00125       (+) HAL_SAI_Abort(): Abort the current transfer
00126
00127     *** SAI HAL driver macros list ***
00128     ==================================
00129     [..]
00130       Below the list of most used macros in SAI HAL driver :
00131
00132       (+) __HAL_SAI_ENABLE(): Enable the SAI peripheral
00133       (+) __HAL_SAI_DISABLE(): Disable the SAI peripheral
00134       (+) __HAL_SAI_ENABLE_IT(): Enable the specified SAI interrupts
00135       (+) __HAL_SAI_DISABLE_IT(): Disable the specified SAI interrupts
00136       (+) __HAL_SAI_GET_IT_SOURCE(): Check if the specified SAI interrupt source is
00137           enabled or disabled
00138       (+) __HAL_SAI_GET_FLAG(): Check whether the specified SAI flag is set or not
00139
00140     *** Callback registration ***
00141     =============================
00142     [..]
00143     The compilation define USE_HAL_SAI_REGISTER_CALLBACKS when set to 1
00144     allows the user to configure dynamically the driver callbacks.
00145     Use functions HAL_SAI_RegisterCallback() to register a user callback.
00146
00147     [..]
00148     Function HAL_SAI_RegisterCallback() allows to register following callbacks:
00149       (+) RxCpltCallback     : SAI receive complete.
00150       (+) RxHalfCpltCallback : SAI receive half complete.
00151       (+) TxCpltCallback     : SAI transmit complete.
00152       (+) TxHalfCpltCallback : SAI transmit half complete.
00153       (+) ErrorCallback      : SAI error.
00154       (+) MspInitCallback    : SAI MspInit.
00155       (+) MspDeInitCallback  : SAI MspDeInit.
00156     [..]
00157     This function takes as parameters the HAL peripheral handle, the callback ID
00158     and a pointer to the user callback function.
00159
00160     [..]
00161     Use function HAL_SAI_UnRegisterCallback() to reset a callback to the default
00162     weak (surcharged) function.
00163     HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00164     and the callback ID.
00165     [..]
00166     This function allows to reset following callbacks:
00167       (+) RxCpltCallback     : SAI receive complete.
00168       (+) RxHalfCpltCallback : SAI receive half complete.
00169       (+) TxCpltCallback     : SAI transmit complete.
00170       (+) TxHalfCpltCallback : SAI transmit half complete.
00171       (+) ErrorCallback      : SAI error.
00172       (+) MspInitCallback    : SAI MspInit.
00173       (+) MspDeInitCallback  : SAI MspDeInit.
00174
00175     [..]
00176     By default, after the HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET
00177     all callbacks are reset to the corresponding legacy weak (surcharged) functions:
00178     examples HAL_SAI_RxCpltCallback(), HAL_SAI_ErrorCallback().
00179     Exception done for MspInit and MspDeInit callbacks that are respectively
00180     reset to the legacy weak (surcharged) functions in the HAL_SAI_Init
00181     and HAL_SAI_DeInit only when these callbacks are null (not registered beforehand).
00182     If not, MspInit or MspDeInit are not null, the HAL_SAI_Init and HAL_SAI_DeInit
00183     keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
00184
00185     [..]
00186     Callbacks can be registered/unregistered in READY state only.
00187     Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
00188     in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
00189     during the Init/DeInit.
00190     In that case first register the MspInit/MspDeInit user callbacks
00191     using HAL_SAI_RegisterCallback before calling HAL_SAI_DeInit
00192     or HAL_SAI_Init function.
00193
00194     [..]
00195     When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or
00196     not defined, the callback registering feature is not available
00197     and weak (surcharged) callbacks are used.
00198
00199   @endverbatim
00200   ******************************************************************************
00201   * @attention
00202   *
00203   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00204   * All rights reserved.</center></h2>
00205   *
00206   * This software component is licensed by ST under BSD 3-Clause license,
00207   * the "License"; You may not use this file except in compliance with the
00208   * License. You may obtain a copy of the License at:
00209   *                        opensource.org/licenses/BSD-3-Clause
00210   *
00211   ******************************************************************************
00212   */
00213
00214 /* Includes ------------------------------------------------------------------*/
00215 #include "stm32wbxx_hal.h"
00216
00217 /** @addtogroup STM32WBxx_HAL_Driver
00218   * @{
00219   */
00220
00221 #ifdef HAL_SAI_MODULE_ENABLED
00222
00223 #if defined (SAI1)
00224
00225 /** @defgroup SAI SAI
00226   * @brief SAI HAL module driver
00227   * @{
00228   */
00229
00230 /* Private typedef -----------------------------------------------------------*/
00231 /** @defgroup SAI_Private_Typedefs  SAI Private Typedefs
00232   * @{
00233   */
00234 typedef enum
00235 {
00236   SAI_MODE_DMA,
00237   SAI_MODE_IT
00238 } SAI_ModeTypedef;
00239 /**
00240   * @}
00241   */
00242
00243 /* Private define ------------------------------------------------------------*/
00244 /** @defgroup SAI_Private_Constants  SAI Private Constants
00245   * @{
00246   */
00247 #define SAI_DEFAULT_TIMEOUT      4U
00248 #define SAI_LONG_TIMEOUT         1000U
00249 /**
00250   * @}
00251   */
00252
00253 /* Private macro -------------------------------------------------------------*/
00254 /* Private variables ---------------------------------------------------------*/
00255 /* Private function prototypes -----------------------------------------------*/
00256 /** @defgroup SAI_Private_Functions  SAI Private Functions
00257   * @{
00258   */
00259 static void SAI_FillFifo(SAI_HandleTypeDef *hsai);
00260 static uint32_t SAI_InterruptFlag(const SAI_HandleTypeDef *hsai, SAI_ModeTypedef mode);
00261 static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
00262 static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
00263
00264 static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai);
00265 static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai);
00266 static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai);
00267 static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai);
00268 static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai);
00269 static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai);
00270 static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai);
00271
00272 static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma);
00273 static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00274 static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma);
00275 static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00276 static void SAI_DMAError(DMA_HandleTypeDef *hdma);
00277 static void SAI_DMAAbort(DMA_HandleTypeDef *hdma);
00278 /**
00279   * @}
00280   */
00281
00282 /* Exported functions ---------------------------------------------------------*/
00283 /** @defgroup SAI_Exported_Functions SAI Exported Functions
00284   * @{
00285   */
00286
00287 /** @defgroup SAI_Exported_Functions_Group1 Initialization and de-initialization functions
00288   * @brief    Initialization and Configuration functions
00289   *
00290 @verbatim
00291  ===============================================================================
00292              ##### Initialization and de-initialization functions #####
00293  ===============================================================================
00294   [..]  This subsection provides a set of functions allowing to initialize and
00295         de-initialize the SAIx peripheral:
00296
00297       (+) User must implement HAL_SAI_MspInit() function in which he configures
00298           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00299
00300       (+) Call the function HAL_SAI_Init() to configure the selected device with
00301           the selected configuration:
00302         (++) Mode (Master/slave TX/RX)
00303         (++) Protocol
00304         (++) Data Size
00305         (++) MCLK Output
00306         (++) Audio frequency
00307         (++) FIFO Threshold
00308         (++) Frame Config
00309         (++) Slot Config
00310         (++) PDM Config
00311
00312       (+) Call the function HAL_SAI_DeInit() to restore the default configuration
00313           of the selected SAI peripheral.
00314
00315 @endverbatim
00316   * @{
00317   */
00318
00319 /**
00320   * @brief  Initialize the structure FrameInit, SlotInit and the low part of
00321   *         Init according to the specified parameters and call the function
00322   *         HAL_SAI_Init to initialize the SAI block.
00323   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
00324   *              the configuration information for SAI module.
00325   * @param  protocol one of the supported protocol @ref SAI_Protocol
00326   * @param  datasize one of the supported datasize @ref SAI_Protocol_DataSize
00327   *                   the configuration information for SAI module.
00328   * @param  nbslot Number of slot.
00329   * @retval HAL status
00330   */
00331 HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
00332 {
00333   HAL_StatusTypeDef status;
00334
00335   /* Check the parameters */
00336   assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol));
00337   assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize));
00338
00339   switch (protocol)
00340   {
00341     case SAI_I2S_STANDARD :
00342     case SAI_I2S_MSBJUSTIFIED :
00343     case SAI_I2S_LSBJUSTIFIED :
00344       status = SAI_InitI2S(hsai, protocol, datasize, nbslot);
00345       break;
00346     case SAI_PCM_LONG :
00347     case SAI_PCM_SHORT :
00348       status = SAI_InitPCM(hsai, protocol, datasize, nbslot);
00349       break;
00350     default :
00351       status = HAL_ERROR;
00352       break;
00353   }
00354
00355   if (status == HAL_OK)
00356   {
00357     status = HAL_SAI_Init(hsai);
00358   }
00359
00360   return status;
00361 }
00362
00363 /**
00364   * @brief  Initialize the SAI according to the specified parameters.
00365   *         in the SAI_InitTypeDef structure and initialize the associated handle.
00366   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
00367   *              the configuration information for SAI module.
00368   * @retval HAL status
00369   */
00370 HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
00371 {
00372   uint32_t ckstr_bits;
00373   uint32_t syncen_bits;
00374
00375   /* Check the SAI handle allocation */
00376   if (hsai == NULL)
00377   {
00378     return HAL_ERROR;
00379   }
00380
00381   /* check the instance */
00382   assert_param(IS_SAI_ALL_INSTANCE(hsai->Instance));
00383
00384   /* Check the SAI Block parameters */
00385   assert_param(IS_SAI_AUDIO_FREQUENCY(hsai->Init.AudioFrequency));
00386   assert_param(IS_SAI_BLOCK_PROTOCOL(hsai->Init.Protocol));
00387   assert_param(IS_SAI_BLOCK_MODE(hsai->Init.AudioMode));
00388   assert_param(IS_SAI_BLOCK_DATASIZE(hsai->Init.DataSize));
00389   assert_param(IS_SAI_BLOCK_FIRST_BIT(hsai->Init.FirstBit));
00390   assert_param(IS_SAI_BLOCK_CLOCK_STROBING(hsai->Init.ClockStrobing));
00391   assert_param(IS_SAI_BLOCK_SYNCHRO(hsai->Init.Synchro));
00392   assert_param(IS_SAI_BLOCK_MCK_OUTPUT(hsai->Init.MckOutput));
00393   assert_param(IS_SAI_BLOCK_OUTPUT_DRIVE(hsai->Init.OutputDrive));
00394   assert_param(IS_SAI_BLOCK_NODIVIDER(hsai->Init.NoDivider));
00395   assert_param(IS_SAI_BLOCK_FIFO_THRESHOLD(hsai->Init.FIFOThreshold));
00396   assert_param(IS_SAI_MONO_STEREO_MODE(hsai->Init.MonoStereoMode));
00397   assert_param(IS_SAI_BLOCK_COMPANDING_MODE(hsai->Init.CompandingMode));
00398   assert_param(IS_SAI_BLOCK_TRISTATE_MANAGEMENT(hsai->Init.TriState));
00399   assert_param(IS_SAI_BLOCK_SYNCEXT(hsai->Init.SynchroExt));
00400   assert_param(IS_SAI_BLOCK_MCK_OVERSAMPLING(hsai->Init.MckOverSampling));
00401
00402   /* Check the SAI Block Frame parameters */
00403   assert_param(IS_SAI_BLOCK_FRAME_LENGTH(hsai->FrameInit.FrameLength));
00404   assert_param(IS_SAI_BLOCK_ACTIVE_FRAME(hsai->FrameInit.ActiveFrameLength));
00405   assert_param(IS_SAI_BLOCK_FS_DEFINITION(hsai->FrameInit.FSDefinition));
00406   assert_param(IS_SAI_BLOCK_FS_POLARITY(hsai->FrameInit.FSPolarity));
00407   assert_param(IS_SAI_BLOCK_FS_OFFSET(hsai->FrameInit.FSOffset));
00408
00409   /* Check the SAI Block Slot parameters */
00410   assert_param(IS_SAI_BLOCK_FIRSTBIT_OFFSET(hsai->SlotInit.FirstBitOffset));
00411   assert_param(IS_SAI_BLOCK_SLOT_SIZE(hsai->SlotInit.SlotSize));
00412   assert_param(IS_SAI_BLOCK_SLOT_NUMBER(hsai->SlotInit.SlotNumber));
00413   assert_param(IS_SAI_SLOT_ACTIVE(hsai->SlotInit.SlotActive));
00414
00415   /* Check the SAI PDM parameters */
00416   assert_param(IS_FUNCTIONAL_STATE(hsai->Init.PdmInit.Activation));
00417   if (hsai->Init.PdmInit.Activation == ENABLE)
00418   {
00419     assert_param(IS_SAI_PDM_MIC_PAIRS_NUMBER(hsai->Init.PdmInit.MicPairsNbr));
00420     assert_param(IS_SAI_PDM_CLOCK_ENABLE(hsai->Init.PdmInit.ClockEnable));
00421     /* Check that SAI sub-block is SAI1 sub-block A, in master RX mode with free protocol */
00422     if ((hsai->Instance != SAI1_Block_A) ||
00423         (hsai->Init.AudioMode != SAI_MODEMASTER_RX) ||
00424         (hsai->Init.Protocol != SAI_FREE_PROTOCOL))
00425     {
00426       return HAL_ERROR;
00427     }
00428   }
00429
00430   if (hsai->State == HAL_SAI_STATE_RESET)
00431   {
00432     /* Allocate lock resource and initialize it */
00433     hsai->Lock = HAL_UNLOCKED;
00434
00435 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
00436     /* Reset callback pointers to the weak predefined callbacks */
00437     hsai->RxCpltCallback     = HAL_SAI_RxCpltCallback;
00438     hsai->RxHalfCpltCallback = HAL_SAI_RxHalfCpltCallback;
00439     hsai->TxCpltCallback     = HAL_SAI_TxCpltCallback;
00440     hsai->TxHalfCpltCallback = HAL_SAI_TxHalfCpltCallback;
00441     hsai->ErrorCallback      = HAL_SAI_ErrorCallback;
00442
00443     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
00444     if (hsai->MspInitCallback == NULL)
00445     {
00446       hsai->MspInitCallback = HAL_SAI_MspInit;
00447     }
00448     hsai->MspInitCallback(hsai);
00449 #else
00450     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
00451     HAL_SAI_MspInit(hsai);
00452 #endif
00453   }
00454
00455   /* Disable the selected SAI peripheral */
00456   if (SAI_Disable(hsai) != HAL_OK)
00457   {
00458     return HAL_ERROR;
00459   }
00460
00461   hsai->State = HAL_SAI_STATE_BUSY;
00462
00463   /* SAI Block Synchro Configuration -----------------------------------------*/
00464   /* This setting must be done with both audio block (A & B) disabled         */
00465   switch (hsai->Init.Synchro)
00466   {
00467     case SAI_ASYNCHRONOUS :
00468       syncen_bits = 0;
00469       break;
00470     case SAI_SYNCHRONOUS :
00471       syncen_bits = SAI_xCR1_SYNCEN_0;
00472       break;
00473     default :
00474       syncen_bits = 0;
00475       break;
00476   }
00477
00478   SAI1->GCR = 0;
00479
00480   if (hsai->Init.AudioFrequency != SAI_AUDIO_FREQUENCY_MCKDIV)
00481   {
00482     uint32_t freq;
00483     uint32_t tmpval;
00484
00485     /* In this case, the MCKDIV value is calculated to get AudioFrequency */
00486     freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1);
00487
00488     /* Configure Master Clock Divider using the following formula :
00489        - If NODIV = 1 :
00490          MCKDIV[5:0] = SAI_CK_x / (FS * (FRL + 1))
00491        - If NODIV = 0 :
00492          MCKDIV[5:0] = SAI_CK_x / (FS * (OSR + 1) * 256) */
00493     if (hsai->Init.NoDivider == SAI_MASTERDIVIDER_DISABLE)
00494     {
00495       /* NODIV = 1 */
00496       uint32_t tmpframelength;
00497
00498       if (hsai->Init.Protocol == SAI_SPDIF_PROTOCOL)
00499       {
00500         /* For SPDIF protocol, frame length is set by hardware to 64 */
00501         tmpframelength = 64U;
00502       }
00503       else if (hsai->Init.Protocol == SAI_AC97_PROTOCOL)
00504       {
00505         /* For AC97 protocol, frame length is set by hardware to 256 */
00506         tmpframelength = 256U;
00507       }
00508       else
00509       {
00510         /* For free protocol, frame length is set by user */
00511         tmpframelength = hsai->FrameInit.FrameLength;
00512       }
00513
00514       /* (freq x 10) to keep Significant digits */
00515       tmpval = (freq * 10U) / (hsai->Init.AudioFrequency * tmpframelength);
00516     }
00517     else
00518     {
00519       /* NODIV = 0 */
00520       uint32_t tmposr;
00521       tmposr = (hsai->Init.MckOverSampling == SAI_MCK_OVERSAMPLING_ENABLE) ? 2U : 1U;
00522       /* (freq x 10) to keep Significant digits */
00523       tmpval = (freq * 10U) / (hsai->Init.AudioFrequency * tmposr * 256U);
00524     }
00525     hsai->Init.Mckdiv = tmpval / 10U;
00526
00527     /* Round result to the nearest integer */
00528     if ((tmpval % 10U) > 8U)
00529     {
00530       hsai->Init.Mckdiv += 1U;
00531     }
00532
00533     /* For SPDIF protocol, SAI shall provide a bit clock twice faster the symbol-rate */
00534     if (hsai->Init.Protocol == SAI_SPDIF_PROTOCOL)
00535     {
00536       hsai->Init.Mckdiv = hsai->Init.Mckdiv >> 1;
00537     }
00538   }
00539   /* Check the SAI Block master clock divider parameter */
00540   assert_param(IS_SAI_BLOCK_MASTER_DIVIDER(hsai->Init.Mckdiv));
00541
00542   /* Compute CKSTR bits of SAI CR1 according ClockStrobing and AudioMode */
00543   if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
00544   {
00545     /* Transmit */
00546     ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? 0U : SAI_xCR1_CKSTR;
00547   }
00548   else
00549   {
00550     /* Receive */
00551     ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? SAI_xCR1_CKSTR : 0U;
00552   }
00553
00554   /* SAI Block Configuration -------------------------------------------------*/
00555   /* SAI CR1 Configuration */
00556   hsai->Instance->CR1 &= ~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG |  SAI_xCR1_DS |      \
00557                            SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN | \
00558                            SAI_xCR1_MONO | SAI_xCR1_OUTDRIV  | SAI_xCR1_DMAEN |  \
00559                            SAI_xCR1_NODIV | SAI_xCR1_MCKDIV | SAI_xCR1_OSR |     \
00560                            SAI_xCR1_MCKEN);
00561
00562   hsai->Instance->CR1 |= (hsai->Init.AudioMode | hsai->Init.Protocol |           \
00563                           hsai->Init.DataSize | hsai->Init.FirstBit  |           \
00564                           ckstr_bits | syncen_bits |                             \
00565                           hsai->Init.MonoStereoMode | hsai->Init.OutputDrive |   \
00566                           hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20) |     \
00567                           hsai->Init.MckOverSampling | hsai->Init.MckOutput);
00568
00569   /* SAI CR2 Configuration */
00570   hsai->Instance->CR2 &= ~(SAI_xCR2_FTH | SAI_xCR2_FFLUSH | SAI_xCR2_COMP | SAI_xCR2_CPL);
00571   hsai->Instance->CR2 |= (hsai->Init.FIFOThreshold | hsai->Init.CompandingMode | hsai->Init.TriState);
00572
00573   /* SAI Frame Configuration -----------------------------------------*/
00574   hsai->Instance->FRCR &= (~(SAI_xFRCR_FRL | SAI_xFRCR_FSALL | SAI_xFRCR_FSDEF | \
00575                              SAI_xFRCR_FSPOL | SAI_xFRCR_FSOFF));
00576   hsai->Instance->FRCR |= ((hsai->FrameInit.FrameLength - 1U) |
00577                            hsai->FrameInit.FSOffset |
00578                            hsai->FrameInit.FSDefinition |
00579                            hsai->FrameInit.FSPolarity   |
00580                            ((hsai->FrameInit.ActiveFrameLength - 1U) << 8));
00581
00582   /* SAI Block_x SLOT Configuration ------------------------------------------*/
00583   /* This register has no meaning in AC 97 and SPDIF audio protocol */
00584   hsai->Instance->SLOTR &= (~(SAI_xSLOTR_FBOFF | SAI_xSLOTR_SLOTSZ |  \
00585                               SAI_xSLOTR_NBSLOT | SAI_xSLOTR_SLOTEN));
00586
00587   hsai->Instance->SLOTR |= hsai->SlotInit.FirstBitOffset | hsai->SlotInit.SlotSize | \
00588                            (hsai->SlotInit.SlotActive << 16) | ((hsai->SlotInit.SlotNumber - 1U) <<  8);
00589
00590   /* SAI PDM Configuration ---------------------------------------------------*/
00591   if (hsai->Instance == SAI1_Block_A)
00592   {
00593     /* Disable PDM interface */
00594     SAI1->PDMCR &= ~(SAI_PDMCR_PDMEN);
00595     if (hsai->Init.PdmInit.Activation == ENABLE)
00596     {
00597       /* Configure and enable PDM interface */
00598       SAI1->PDMCR = (hsai->Init.PdmInit.ClockEnable |
00599                      ((hsai->Init.PdmInit.MicPairsNbr - 1U) << SAI_PDMCR_MICNBR_Pos));
00600       SAI1->PDMCR |= SAI_PDMCR_PDMEN;
00601     }
00602   }
00603
00604   /* Initialize the error code */
00605   hsai->ErrorCode = HAL_SAI_ERROR_NONE;
00606
00607   /* Initialize the SAI state */
00608   hsai->State = HAL_SAI_STATE_READY;
00609
00610   /* Release Lock */
00611   __HAL_UNLOCK(hsai);
00612
00613   return HAL_OK;
00614 }
00615
00616 /**
00617   * @brief  DeInitialize the SAI peripheral.
00618   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
00619   *              the configuration information for SAI module.
00620   * @retval HAL status
00621   */
00622 HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai)
00623 {
00624   /* Check the SAI handle allocation */
00625   if (hsai == NULL)
00626   {
00627     return HAL_ERROR;
00628   }
00629
00630   hsai->State = HAL_SAI_STATE_BUSY;
00631
00632   /* Disabled All interrupt and clear all the flag */
00633   hsai->Instance->IMR = 0;
00634   hsai->Instance->CLRFR = 0xFFFFFFFFU;
00635
00636   /* Disable the SAI */
00637   if (SAI_Disable(hsai) != HAL_OK)
00638   {
00639     /* Reset SAI state to ready */
00640     hsai->State = HAL_SAI_STATE_READY;
00641
00642     /* Release Lock */
00643     __HAL_UNLOCK(hsai);
00644
00645     return HAL_ERROR;
00646   }
00647
00648   /* Flush the fifo */
00649   SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
00650
00651   /* Disable SAI PDM interface */
00652   if (hsai->Instance == SAI1_Block_A)
00653   {
00654     /* Reset PDM delays */
00655     SAI1->PDMDLY = 0U;
00656
00657     /* Disable PDM interface */
00658     SAI1->PDMCR &= ~(SAI_PDMCR_PDMEN);
00659   }
00660
00661   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
00662 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
00663   if (hsai->MspDeInitCallback == NULL)
00664   {
00665     hsai->MspDeInitCallback = HAL_SAI_MspDeInit;
00666   }
00667   hsai->MspDeInitCallback(hsai);
00668 #else
00669   HAL_SAI_MspDeInit(hsai);
00670 #endif
00671
00672   /* Initialize the error code */
00673   hsai->ErrorCode = HAL_SAI_ERROR_NONE;
00674
00675   /* Initialize the SAI state */
00676   hsai->State = HAL_SAI_STATE_RESET;
00677
00678   /* Release Lock */
00679   __HAL_UNLOCK(hsai);
00680
00681   return HAL_OK;
00682 }
00683
00684 /**
00685   * @brief Initialize the SAI MSP.
00686   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
00687   *              the configuration information for SAI module.
00688   * @retval None
00689   */
00690 __weak void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai)
00691 {
00692   /* Prevent unused argument(s) compilation warning */
00693   UNUSED(hsai);
00694
00695   /* NOTE : This function should not be modified, when the callback is needed,
00696             the HAL_SAI_MspInit could be implemented in the user file
00697    */
00698 }
00699
00700 /**
00701   * @brief DeInitialize the SAI MSP.
00702   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
00703   *              the configuration information for SAI module.
00704   * @retval None
00705   */
00706 __weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai)
00707 {
00708   /* Prevent unused argument(s) compilation warning */
00709   UNUSED(hsai);
00710
00711   /* NOTE : This function should not be modified, when the callback is needed,
00712             the HAL_SAI_MspDeInit could be implemented in the user file
00713    */
00714 }
00715
00716 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
00717 /**
00718   * @brief  Register a user SAI callback
00719   *         to be used instead of the weak predefined callback.
00720   * @param  hsai SAI handle.
00721   * @param  CallbackID ID of the callback to be registered.
00722   *         This parameter can be one of the following values:
00723   *           @arg @ref HAL_SAI_RX_COMPLETE_CB_ID receive complete callback ID.
00724   *           @arg @ref HAL_SAI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID.
00725   *           @arg @ref HAL_SAI_TX_COMPLETE_CB_ID transmit complete callback ID.
00726   *           @arg @ref HAL_SAI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID.
00727   *           @arg @ref HAL_SAI_ERROR_CB_ID error callback ID.
00728   *           @arg @ref HAL_SAI_MSPINIT_CB_ID MSP init callback ID.
00729   *           @arg @ref HAL_SAI_MSPDEINIT_CB_ID MSP de-init callback ID.
00730   * @param  pCallback pointer to the callback function.
00731   * @retval HAL status.
00732   */
00733 HAL_StatusTypeDef HAL_SAI_RegisterCallback(SAI_HandleTypeDef        *hsai,
00734                                            HAL_SAI_CallbackIDTypeDef CallbackID,
00735                                            pSAI_CallbackTypeDef      pCallback)
00736 {
00737   HAL_StatusTypeDef status = HAL_OK;
00738
00739   if (pCallback == NULL)
00740   {
00741     /* update the error code */
00742     hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
00743     /* update return status */
00744     status = HAL_ERROR;
00745   }
00746   else
00747   {
00748     if (HAL_SAI_STATE_READY == hsai->State)
00749     {
00750       switch (CallbackID)
00751       {
00752         case HAL_SAI_RX_COMPLETE_CB_ID :
00753           hsai->RxCpltCallback = pCallback;
00754           break;
00755         case HAL_SAI_RX_HALFCOMPLETE_CB_ID :
00756           hsai->RxHalfCpltCallback = pCallback;
00757           break;
00758         case HAL_SAI_TX_COMPLETE_CB_ID :
00759           hsai->TxCpltCallback = pCallback;
00760           break;
00761         case HAL_SAI_TX_HALFCOMPLETE_CB_ID :
00762           hsai->TxHalfCpltCallback = pCallback;
00763           break;
00764         case HAL_SAI_ERROR_CB_ID :
00765           hsai->ErrorCallback = pCallback;
00766           break;
00767         case HAL_SAI_MSPINIT_CB_ID :
00768           hsai->MspInitCallback = pCallback;
00769           break;
00770         case HAL_SAI_MSPDEINIT_CB_ID :
00771           hsai->MspDeInitCallback = pCallback;
00772           break;
00773         default :
00774           /* update the error code */
00775           hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
00776           /* update return status */
00777           status = HAL_ERROR;
00778           break;
00779       }
00780     }
00781     else if (HAL_SAI_STATE_RESET == hsai->State)
00782     {
00783       switch (CallbackID)
00784       {
00785         case HAL_SAI_MSPINIT_CB_ID :
00786           hsai->MspInitCallback = pCallback;
00787           break;
00788         case HAL_SAI_MSPDEINIT_CB_ID :
00789           hsai->MspDeInitCallback = pCallback;
00790           break;
00791         default :
00792           /* update the error code */
00793           hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
00794           /* update return status */
00795           status = HAL_ERROR;
00796           break;
00797       }
00798     }
00799     else
00800     {
00801       /* update the error code */
00802       hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
00803       /* update return status */
00804       status = HAL_ERROR;
00805     }
00806   }
00807   return status;
00808 }
00809
00810 /**
00811   * @brief  Unregister a user SAI callback.
00812   *         SAI callback is redirected to the weak predefined callback.
00813   * @param  hsai SAI handle.
00814   * @param  CallbackID ID of the callback to be unregistered.
00815   *         This parameter can be one of the following values:
00816   *           @arg @ref HAL_SAI_RX_COMPLETE_CB_ID receive complete callback ID.
00817   *           @arg @ref HAL_SAI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID.
00818   *           @arg @ref HAL_SAI_TX_COMPLETE_CB_ID transmit complete callback ID.
00819   *           @arg @ref HAL_SAI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID.
00820   *           @arg @ref HAL_SAI_ERROR_CB_ID error callback ID.
00821   *           @arg @ref HAL_SAI_MSPINIT_CB_ID MSP init callback ID.
00822   *           @arg @ref HAL_SAI_MSPDEINIT_CB_ID MSP de-init callback ID.
00823   * @retval HAL status.
00824   */
00825 HAL_StatusTypeDef HAL_SAI_UnRegisterCallback(SAI_HandleTypeDef        *hsai,
00826                                              HAL_SAI_CallbackIDTypeDef CallbackID)
00827 {
00828   HAL_StatusTypeDef status = HAL_OK;
00829
00830   if (HAL_SAI_STATE_READY == hsai->State)
00831   {
00832     switch (CallbackID)
00833     {
00834       case HAL_SAI_RX_COMPLETE_CB_ID :
00835         hsai->RxCpltCallback = HAL_SAI_RxCpltCallback;
00836         break;
00837       case HAL_SAI_RX_HALFCOMPLETE_CB_ID :
00838         hsai->RxHalfCpltCallback = HAL_SAI_RxHalfCpltCallback;
00839         break;
00840       case HAL_SAI_TX_COMPLETE_CB_ID :
00841         hsai->TxCpltCallback = HAL_SAI_TxCpltCallback;
00842         break;
00843       case HAL_SAI_TX_HALFCOMPLETE_CB_ID :
00844         hsai->TxHalfCpltCallback = HAL_SAI_TxHalfCpltCallback;
00845         break;
00846       case HAL_SAI_ERROR_CB_ID :
00847         hsai->ErrorCallback = HAL_SAI_ErrorCallback;
00848         break;
00849       case HAL_SAI_MSPINIT_CB_ID :
00850         hsai->MspInitCallback = HAL_SAI_MspInit;
00851         break;
00852       case HAL_SAI_MSPDEINIT_CB_ID :
00853         hsai->MspDeInitCallback = HAL_SAI_MspDeInit;
00854         break;
00855       default :
00856         /* update the error code */
00857         hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
00858         /* update return status */
00859         status = HAL_ERROR;
00860         break;
00861     }
00862   }
00863   else if (HAL_SAI_STATE_RESET == hsai->State)
00864   {
00865     switch (CallbackID)
00866     {
00867       case HAL_SAI_MSPINIT_CB_ID :
00868         hsai->MspInitCallback = HAL_SAI_MspInit;
00869         break;
00870       case HAL_SAI_MSPDEINIT_CB_ID :
00871         hsai->MspDeInitCallback = HAL_SAI_MspDeInit;
00872         break;
00873       default :
00874         /* update the error code */
00875         hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
00876         /* update return status */
00877         status = HAL_ERROR;
00878         break;
00879     }
00880   }
00881   else
00882   {
00883     /* update the error code */
00884     hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
00885     /* update return status */
00886     status = HAL_ERROR;
00887   }
00888   return status;
00889 }
00890 #endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
00891
00892 /**
00893   * @}
00894   */
00895
00896 /** @defgroup SAI_Exported_Functions_Group2 IO operation functions
00897   * @brief    Data transfers functions
00898   *
00899 @verbatim
00900   ==============================================================================
00901                       ##### IO operation functions #####
00902   ==============================================================================
00903   [..]
00904     This subsection provides a set of functions allowing to manage the SAI data
00905     transfers.
00906
00907     (+) There are two modes of transfer:
00908       (++) Blocking mode : The communication is performed in the polling mode.
00909            The status of all data processing is returned by the same function
00910            after finishing transfer.
00911       (++) No-Blocking mode : The communication is performed using Interrupts
00912            or DMA. These functions return the status of the transfer startup.
00913            The end of the data processing will be indicated through the
00914            dedicated SAI IRQ when using Interrupt mode or the DMA IRQ when
00915            using DMA mode.
00916
00917     (+) Blocking mode functions are :
00918       (++) HAL_SAI_Transmit()
00919       (++) HAL_SAI_Receive()
00920
00921     (+) Non Blocking mode functions with Interrupt are :
00922       (++) HAL_SAI_Transmit_IT()
00923       (++) HAL_SAI_Receive_IT()
00924
00925     (+) Non Blocking mode functions with DMA are :
00926       (++) HAL_SAI_Transmit_DMA()
00927       (++) HAL_SAI_Receive_DMA()
00928
00929     (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
00930       (++) HAL_SAI_TxCpltCallback()
00931       (++) HAL_SAI_RxCpltCallback()
00932       (++) HAL_SAI_ErrorCallback()
00933
00934 @endverbatim
00935   * @{
00936   */
00937
00938 /**
00939   * @brief  Transmit an amount of data in blocking mode.
00940   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
00941   *              the configuration information for SAI module.
00942   * @param  pData Pointer to data buffer
00943   * @param  Size Amount of data to be sent
00944   * @param  Timeout Timeout duration
00945   * @retval HAL status
00946   */
00947 HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00948 {
00949   uint32_t tickstart = HAL_GetTick();
00950   uint32_t temp;
00951
00952   if ((pData == NULL) || (Size == 0U))
00953   {
00954     return  HAL_ERROR;
00955   }
00956
00957   if (hsai->State == HAL_SAI_STATE_READY)
00958   {
00959     /* Process Locked */
00960     __HAL_LOCK(hsai);
00961
00962     hsai->XferSize = Size;
00963     hsai->XferCount = Size;
00964     hsai->pBuffPtr = pData;
00965     hsai->State = HAL_SAI_STATE_BUSY_TX;
00966     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
00967
00968     /* Check if the SAI is already enabled */
00969     if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
00970     {
00971       /* fill the fifo with data before to enabled the SAI */
00972       SAI_FillFifo(hsai);
00973       /* Enable SAI peripheral */
00974       __HAL_SAI_ENABLE(hsai);
00975     }
00976
00977     while (hsai->XferCount > 0U)
00978     {
00979       /* Write data if the FIFO is not full */
00980       if ((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL)
00981       {
00982         if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
00983         {
00984           hsai->Instance->DR = *hsai->pBuffPtr;
00985           hsai->pBuffPtr++;
00986         }
00987         else if (hsai->Init.DataSize <= SAI_DATASIZE_16)
00988         {
00989           temp = (uint32_t)(*hsai->pBuffPtr);
00990           hsai->pBuffPtr++;
00991           temp |= ((uint32_t)(*hsai->pBuffPtr) << 8);
00992           hsai->pBuffPtr++;
00993           hsai->Instance->DR = temp;
00994         }
00995         else
00996         {
00997           temp = (uint32_t)(*hsai->pBuffPtr);
00998           hsai->pBuffPtr++;
00999           temp |= ((uint32_t)(*hsai->pBuffPtr) << 8);
01000           hsai->pBuffPtr++;
01001           temp |= ((uint32_t)(*hsai->pBuffPtr) << 16);
01002           hsai->pBuffPtr++;
01003           temp |= ((uint32_t)(*hsai->pBuffPtr) << 24);
01004           hsai->pBuffPtr++;
01005           hsai->Instance->DR = temp;
01006         }
01007         hsai->XferCount--;
01008       }
01009       else
01010       {
01011         /* Check for the Timeout */
01012         if ((((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) && (Timeout != HAL_MAX_DELAY))
01013         {
01014           /* Update error code */
01015           hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
01016
01017           /* Clear all the flags */
01018           hsai->Instance->CLRFR = 0xFFFFFFFFU;
01019
01020           /* Disable SAI peripheral */
01021           /* No need to check return value because state update, unlock and error return will be performed later */
01022           (void) SAI_Disable(hsai);
01023
01024           /* Flush the fifo */
01025           SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
01026
01027           /* Change the SAI state */
01028           hsai->State = HAL_SAI_STATE_READY;
01029
01030           /* Process Unlocked */
01031           __HAL_UNLOCK(hsai);
01032
01033           return HAL_ERROR;
01034         }
01035       }
01036     }
01037
01038     hsai->State = HAL_SAI_STATE_READY;
01039
01040     /* Process Unlocked */
01041     __HAL_UNLOCK(hsai);
01042
01043     return HAL_OK;
01044   }
01045   else
01046   {
01047     return HAL_BUSY;
01048   }
01049 }
01050
01051 /**
01052   * @brief  Receive an amount of data in blocking mode.
01053   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01054   *              the configuration information for SAI module.
01055   * @param  pData Pointer to data buffer
01056   * @param  Size Amount of data to be received
01057   * @param  Timeout Timeout duration
01058   * @retval HAL status
01059   */
01060 HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
01061 {
01062   uint32_t tickstart = HAL_GetTick();
01063   uint32_t temp;
01064
01065   if ((pData == NULL) || (Size == 0U))
01066   {
01067     return  HAL_ERROR;
01068   }
01069
01070   if (hsai->State == HAL_SAI_STATE_READY)
01071   {
01072     /* Process Locked */
01073     __HAL_LOCK(hsai);
01074
01075     hsai->pBuffPtr = pData;
01076     hsai->XferSize = Size;
01077     hsai->XferCount = Size;
01078     hsai->State = HAL_SAI_STATE_BUSY_RX;
01079     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
01080
01081     /* Check if the SAI is already enabled */
01082     if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
01083     {
01084       /* Enable SAI peripheral */
01085       __HAL_SAI_ENABLE(hsai);
01086     }
01087
01088     /* Receive data */
01089     while (hsai->XferCount > 0U)
01090     {
01091       if ((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_EMPTY)
01092       {
01093         if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
01094         {
01095           *hsai->pBuffPtr = (uint8_t)hsai->Instance->DR;
01096           hsai->pBuffPtr++;
01097         }
01098         else if (hsai->Init.DataSize <= SAI_DATASIZE_16)
01099         {
01100           temp = hsai->Instance->DR;
01101           *hsai->pBuffPtr = (uint8_t)temp;
01102           hsai->pBuffPtr++;
01103           *hsai->pBuffPtr = (uint8_t)(temp >> 8);
01104           hsai->pBuffPtr++;
01105         }
01106         else
01107         {
01108           temp = hsai->Instance->DR;
01109           *hsai->pBuffPtr = (uint8_t)temp;
01110           hsai->pBuffPtr++;
01111           *hsai->pBuffPtr = (uint8_t)(temp >> 8);
01112           hsai->pBuffPtr++;
01113           *hsai->pBuffPtr = (uint8_t)(temp >> 16);
01114           hsai->pBuffPtr++;
01115           *hsai->pBuffPtr = (uint8_t)(temp >> 24);
01116           hsai->pBuffPtr++;
01117         }
01118         hsai->XferCount--;
01119       }
01120       else
01121       {
01122         /* Check for the Timeout */
01123         if ((((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) && (Timeout != HAL_MAX_DELAY))
01124         {
01125           /* Update error code */
01126           hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
01127
01128           /* Clear all the flags */
01129           hsai->Instance->CLRFR = 0xFFFFFFFFU;
01130
01131           /* Disable SAI peripheral */
01132           /* No need to check return value because state update, unlock and error return will be performed later */
01133           (void) SAI_Disable(hsai);
01134
01135           /* Flush the fifo */
01136           SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
01137
01138           /* Change the SAI state */
01139           hsai->State = HAL_SAI_STATE_READY;
01140
01141           /* Process Unlocked */
01142           __HAL_UNLOCK(hsai);
01143
01144           return HAL_ERROR;
01145         }
01146       }
01147     }
01148
01149     hsai->State = HAL_SAI_STATE_READY;
01150
01151     /* Process Unlocked */
01152     __HAL_UNLOCK(hsai);
01153
01154     return HAL_OK;
01155   }
01156   else
01157   {
01158     return HAL_BUSY;
01159   }
01160 }
01161
01162 /**
01163   * @brief  Transmit an amount of data in non-blocking mode with Interrupt.
01164   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01165   *              the configuration information for SAI module.
01166   * @param  pData Pointer to data buffer
01167   * @param  Size Amount of data to be sent
01168   * @retval HAL status
01169   */
01170 HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
01171 {
01172   if ((pData == NULL) || (Size == 0U))
01173   {
01174     return  HAL_ERROR;
01175   }
01176
01177   if (hsai->State == HAL_SAI_STATE_READY)
01178   {
01179     /* Process Locked */
01180     __HAL_LOCK(hsai);
01181
01182     hsai->pBuffPtr = pData;
01183     hsai->XferSize = Size;
01184     hsai->XferCount = Size;
01185     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
01186     hsai->State = HAL_SAI_STATE_BUSY_TX;
01187
01188     if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
01189     {
01190       hsai->InterruptServiceRoutine = SAI_Transmit_IT8Bit;
01191     }
01192     else if (hsai->Init.DataSize <= SAI_DATASIZE_16)
01193     {
01194       hsai->InterruptServiceRoutine = SAI_Transmit_IT16Bit;
01195     }
01196     else
01197     {
01198       hsai->InterruptServiceRoutine = SAI_Transmit_IT32Bit;
01199     }
01200
01201     /* Fill the fifo before starting the communication */
01202     SAI_FillFifo(hsai);
01203
01204     /* Enable FRQ and OVRUDR interrupts */
01205     __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
01206
01207     /* Check if the SAI is already enabled */
01208     if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
01209     {
01210       /* Enable SAI peripheral */
01211       __HAL_SAI_ENABLE(hsai);
01212     }
01213     /* Process Unlocked */
01214     __HAL_UNLOCK(hsai);
01215
01216     return HAL_OK;
01217   }
01218   else
01219   {
01220     return HAL_BUSY;
01221   }
01222 }
01223
01224 /**
01225   * @brief  Receive an amount of data in non-blocking mode with Interrupt.
01226   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01227   *              the configuration information for SAI module.
01228   * @param  pData Pointer to data buffer
01229   * @param  Size Amount of data to be received
01230   * @retval HAL status
01231   */
01232 HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
01233 {
01234   if ((pData == NULL) || (Size == 0U))
01235   {
01236     return  HAL_ERROR;
01237   }
01238
01239   if (hsai->State == HAL_SAI_STATE_READY)
01240   {
01241     /* Process Locked */
01242     __HAL_LOCK(hsai);
01243
01244     hsai->pBuffPtr = pData;
01245     hsai->XferSize = Size;
01246     hsai->XferCount = Size;
01247     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
01248     hsai->State = HAL_SAI_STATE_BUSY_RX;
01249
01250     if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
01251     {
01252       hsai->InterruptServiceRoutine = SAI_Receive_IT8Bit;
01253     }
01254     else if (hsai->Init.DataSize <= SAI_DATASIZE_16)
01255     {
01256       hsai->InterruptServiceRoutine = SAI_Receive_IT16Bit;
01257     }
01258     else
01259     {
01260       hsai->InterruptServiceRoutine = SAI_Receive_IT32Bit;
01261     }
01262
01263     /* Enable TXE and OVRUDR interrupts */
01264     __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
01265
01266     /* Check if the SAI is already enabled */
01267     if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
01268     {
01269       /* Enable SAI peripheral */
01270       __HAL_SAI_ENABLE(hsai);
01271     }
01272
01273     /* Process Unlocked */
01274     __HAL_UNLOCK(hsai);
01275
01276     return HAL_OK;
01277   }
01278   else
01279   {
01280     return HAL_BUSY;
01281   }
01282 }
01283
01284 /**
01285   * @brief Pause the audio stream playing from the Media.
01286   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01287   *              the configuration information for SAI module.
01288   * @retval HAL status
01289   */
01290 HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai)
01291 {
01292   /* Process Locked */
01293   __HAL_LOCK(hsai);
01294
01295   /* Pause the audio file playing by disabling the SAI DMA requests */
01296   hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
01297
01298   /* Process Unlocked */
01299   __HAL_UNLOCK(hsai);
01300
01301   return HAL_OK;
01302 }
01303
01304 /**
01305   * @brief Resume the audio stream playing from the Media.
01306   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01307   *              the configuration information for SAI module.
01308   * @retval HAL status
01309   */
01310 HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai)
01311 {
01312   /* Process Locked */
01313   __HAL_LOCK(hsai);
01314
01315   /* Enable the SAI DMA requests */
01316   hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
01317
01318   /* If the SAI peripheral is still not enabled, enable it */
01319   if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
01320   {
01321     /* Enable SAI peripheral */
01322     __HAL_SAI_ENABLE(hsai);
01323   }
01324
01325   /* Process Unlocked */
01326   __HAL_UNLOCK(hsai);
01327
01328   return HAL_OK;
01329 }
01330
01331 /**
01332   * @brief Stop the audio stream playing from the Media.
01333   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01334   *              the configuration information for SAI module.
01335   * @retval HAL status
01336   */
01337 HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai)
01338 {
01339   HAL_StatusTypeDef status = HAL_OK;
01340
01341   /* Process Locked */
01342   __HAL_LOCK(hsai);
01343
01344   /* Disable the SAI DMA request */
01345   hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
01346
01347   /* Abort the SAI Tx DMA Stream */
01348   if ((hsai->State == HAL_SAI_STATE_BUSY_TX) && (hsai->hdmatx != NULL))
01349   {
01350     /* No need to check the returned value of HAL_DMA_Abort. */
01351     /* Only HAL_DMA_ERROR_NO_XFER can be returned in case of error and it's not an error for SAI. */
01352     (void) HAL_DMA_Abort(hsai->hdmatx);
01353   }
01354
01355   /* Abort the SAI Rx DMA Stream */
01356   if ((hsai->State == HAL_SAI_STATE_BUSY_RX) && (hsai->hdmarx != NULL))
01357   {
01358     /* No need to check the returned value of HAL_DMA_Abort. */
01359     /* Only HAL_DMA_ERROR_NO_XFER can be returned in case of error and it's not an error for SAI. */
01360     (void) HAL_DMA_Abort(hsai->hdmarx);
01361   }
01362
01363   /* Disable SAI peripheral */
01364   if (SAI_Disable(hsai) != HAL_OK)
01365   {
01366     status = HAL_ERROR;
01367   }
01368
01369   /* Flush the fifo */
01370   SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
01371
01372   /* Set hsai state to ready */
01373   hsai->State = HAL_SAI_STATE_READY;
01374
01375   /* Process Unlocked */
01376   __HAL_UNLOCK(hsai);
01377
01378   return status;
01379 }
01380
01381 /**
01382   * @brief Abort the current transfer and disable the SAI.
01383   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01384   *              the configuration information for SAI module.
01385   * @retval HAL status
01386   */
01387 HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai)
01388 {
01389   HAL_StatusTypeDef status = HAL_OK;
01390
01391   /* Process Locked */
01392   __HAL_LOCK(hsai);
01393
01394   /* Check SAI DMA is enabled or not */
01395   if ((hsai->Instance->CR1 & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
01396   {
01397     /* Disable the SAI DMA request */
01398     hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
01399
01400     /* Abort the SAI Tx DMA Stream */
01401     if ((hsai->State == HAL_SAI_STATE_BUSY_TX) && (hsai->hdmatx != NULL))
01402     {
01403       /* No need to check the returned value of HAL_DMA_Abort. */
01404       /* Only HAL_DMA_ERROR_NO_XFER can be returned in case of error and it's not an error for SAI. */
01405       (void) HAL_DMA_Abort(hsai->hdmatx);
01406     }
01407
01408     /* Abort the SAI Rx DMA Stream */
01409     if ((hsai->State == HAL_SAI_STATE_BUSY_RX) && (hsai->hdmarx != NULL))
01410     {
01411       /* No need to check the returned value of HAL_DMA_Abort. */
01412       /* Only HAL_DMA_ERROR_NO_XFER can be returned in case of error and it's not an error for SAI. */
01413       (void) HAL_DMA_Abort(hsai->hdmarx);
01414     }
01415   }
01416
01417   /* Disabled All interrupt and clear all the flag */
01418   hsai->Instance->IMR = 0;
01419   hsai->Instance->CLRFR = 0xFFFFFFFFU;
01420
01421   /* Disable SAI peripheral */
01422   if (SAI_Disable(hsai) != HAL_OK)
01423   {
01424     status = HAL_ERROR;
01425   }
01426
01427   /* Flush the fifo */
01428   SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
01429
01430   /* Set hsai state to ready */
01431   hsai->State = HAL_SAI_STATE_READY;
01432
01433   /* Process Unlocked */
01434   __HAL_UNLOCK(hsai);
01435
01436   return status;
01437 }
01438
01439 /**
01440   * @brief  Transmit an amount of data in non-blocking mode with DMA.
01441   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01442   *              the configuration information for SAI module.
01443   * @param  pData Pointer to data buffer
01444   * @param  Size Amount of data to be sent
01445   * @retval HAL status
01446   */
01447 HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
01448 {
01449   uint32_t tickstart = HAL_GetTick();
01450
01451   if ((pData == NULL) || (Size == 0U))
01452   {
01453     return  HAL_ERROR;
01454   }
01455
01456   if (hsai->State == HAL_SAI_STATE_READY)
01457   {
01458     /* Process Locked */
01459     __HAL_LOCK(hsai);
01460
01461     hsai->pBuffPtr = pData;
01462     hsai->XferSize = Size;
01463     hsai->XferCount = Size;
01464     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
01465     hsai->State = HAL_SAI_STATE_BUSY_TX;
01466
01467     /* Set the SAI Tx DMA Half transfer complete callback */
01468     hsai->hdmatx->XferHalfCpltCallback = SAI_DMATxHalfCplt;
01469
01470     /* Set the SAI TxDMA transfer complete callback */
01471     hsai->hdmatx->XferCpltCallback = SAI_DMATxCplt;
01472
01473     /* Set the DMA error callback */
01474     hsai->hdmatx->XferErrorCallback = SAI_DMAError;
01475
01476     /* Set the DMA Tx abort callback */
01477     hsai->hdmatx->XferAbortCallback = NULL;
01478
01479     /* Enable the Tx DMA Stream */
01480     if (HAL_DMA_Start_IT(hsai->hdmatx, (uint32_t)hsai->pBuffPtr, (uint32_t)&hsai->Instance->DR, hsai->XferSize) != HAL_OK)
01481     {
01482       __HAL_UNLOCK(hsai);
01483       return  HAL_ERROR;
01484     }
01485
01486     /* Enable the interrupts for error handling */
01487     __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
01488
01489     /* Enable SAI Tx DMA Request */
01490     hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
01491
01492     /* Wait untill FIFO is not empty */
01493     while ((hsai->Instance->SR & SAI_xSR_FLVL) == SAI_FIFOSTATUS_EMPTY)
01494     {
01495       /* Check for the Timeout */
01496       if ((HAL_GetTick() - tickstart) > SAI_LONG_TIMEOUT)
01497       {
01498         /* Update error code */
01499         hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
01500
01501         /* Process Unlocked */
01502         __HAL_UNLOCK(hsai);
01503
01504         return HAL_TIMEOUT;
01505       }
01506     }
01507
01508     /* Check if the SAI is already enabled */
01509     if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
01510     {
01511       /* Enable SAI peripheral */
01512       __HAL_SAI_ENABLE(hsai);
01513     }
01514
01515     /* Process Unlocked */
01516     __HAL_UNLOCK(hsai);
01517
01518     return HAL_OK;
01519   }
01520   else
01521   {
01522     return HAL_BUSY;
01523   }
01524 }
01525
01526 /**
01527   * @brief  Receive an amount of data in non-blocking mode with DMA.
01528   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01529   *              the configuration information for SAI module.
01530   * @param  pData Pointer to data buffer
01531   * @param  Size Amount of data to be received
01532   * @retval HAL status
01533   */
01534 HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
01535 {
01536
01537   if ((pData == NULL) || (Size == 0U))
01538   {
01539     return  HAL_ERROR;
01540   }
01541
01542   if (hsai->State == HAL_SAI_STATE_READY)
01543   {
01544     /* Process Locked */
01545     __HAL_LOCK(hsai);
01546
01547     hsai->pBuffPtr = pData;
01548     hsai->XferSize = Size;
01549     hsai->XferCount = Size;
01550     hsai->ErrorCode = HAL_SAI_ERROR_NONE;
01551     hsai->State = HAL_SAI_STATE_BUSY_RX;
01552
01553     /* Set the SAI Rx DMA Half transfer complete callback */
01554     hsai->hdmarx->XferHalfCpltCallback = SAI_DMARxHalfCplt;
01555
01556     /* Set the SAI Rx DMA transfer complete callback */
01557     hsai->hdmarx->XferCpltCallback = SAI_DMARxCplt;
01558
01559     /* Set the DMA error callback */
01560     hsai->hdmarx->XferErrorCallback = SAI_DMAError;
01561
01562     /* Set the DMA Rx abort callback */
01563     hsai->hdmarx->XferAbortCallback = NULL;
01564
01565     /* Enable the Rx DMA Stream */
01566     if (HAL_DMA_Start_IT(hsai->hdmarx, (uint32_t)&hsai->Instance->DR, (uint32_t)hsai->pBuffPtr, hsai->XferSize) != HAL_OK)
01567     {
01568       __HAL_UNLOCK(hsai);
01569       return  HAL_ERROR;
01570     }
01571
01572     /* Enable the interrupts for error handling */
01573     __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
01574
01575     /* Enable SAI Rx DMA Request */
01576     hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
01577
01578     /* Check if the SAI is already enabled */
01579     if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
01580     {
01581       /* Enable SAI peripheral */
01582       __HAL_SAI_ENABLE(hsai);
01583     }
01584
01585     /* Process Unlocked */
01586     __HAL_UNLOCK(hsai);
01587
01588     return HAL_OK;
01589   }
01590   else
01591   {
01592     return HAL_BUSY;
01593   }
01594 }
01595
01596 /**
01597   * @brief  Enable the Tx mute mode.
01598   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01599   *              the configuration information for SAI module.
01600   * @param  val  value sent during the mute @ref SAI_Block_Mute_Value
01601   * @retval HAL status
01602   */
01603 HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val)
01604 {
01605   assert_param(IS_SAI_BLOCK_MUTE_VALUE(val));
01606
01607   if (hsai->State != HAL_SAI_STATE_RESET)
01608   {
01609     CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE);
01610     SET_BIT(hsai->Instance->CR2, SAI_xCR2_MUTE | (uint32_t)val);
01611     return HAL_OK;
01612   }
01613   return HAL_ERROR;
01614 }
01615
01616 /**
01617   * @brief  Disable the Tx mute mode.
01618   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01619   *              the configuration information for SAI module.
01620   * @retval HAL status
01621   */
01622 HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai)
01623 {
01624   if (hsai->State != HAL_SAI_STATE_RESET)
01625   {
01626     CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE);
01627     return HAL_OK;
01628   }
01629   return HAL_ERROR;
01630 }
01631
01632 /**
01633   * @brief  Enable the Rx mute detection.
01634   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01635   *              the configuration information for SAI module.
01636   * @param  callback function called when the mute is detected.
01637   * @param  counter number a data before mute detection max 63.
01638   * @retval HAL status
01639   */
01640 HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter)
01641 {
01642   assert_param(IS_SAI_BLOCK_MUTE_COUNTER(counter));
01643
01644   if (hsai->State != HAL_SAI_STATE_RESET)
01645   {
01646     /* set the mute counter */
01647     CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTECNT);
01648     SET_BIT(hsai->Instance->CR2, (uint32_t)((uint32_t)counter << SAI_xCR2_MUTECNT_Pos));
01649     hsai->mutecallback = callback;
01650     /* enable the IT interrupt */
01651     __HAL_SAI_ENABLE_IT(hsai, SAI_IT_MUTEDET);
01652     return HAL_OK;
01653   }
01654   return HAL_ERROR;
01655 }
01656
01657 /**
01658   * @brief  Disable the Rx mute detection.
01659   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01660   *              the configuration information for SAI module.
01661   * @retval HAL status
01662   */
01663 HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai)
01664 {
01665   if (hsai->State != HAL_SAI_STATE_RESET)
01666   {
01667     /* set the mutecallback to NULL */
01668     hsai->mutecallback = NULL;
01669     /* enable the IT interrupt */
01670     __HAL_SAI_DISABLE_IT(hsai, SAI_IT_MUTEDET);
01671     return HAL_OK;
01672   }
01673   return HAL_ERROR;
01674 }
01675
01676 /**
01677   * @brief  Handle SAI interrupt request.
01678   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01679   *              the configuration information for SAI module.
01680   * @retval None
01681   */
01682 void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
01683 {
01684   if (hsai->State != HAL_SAI_STATE_RESET)
01685   {
01686     uint32_t itflags = hsai->Instance->SR;
01687     uint32_t itsources = hsai->Instance->IMR;
01688     uint32_t cr1config = hsai->Instance->CR1;
01689     uint32_t tmperror;
01690
01691     /* SAI Fifo request interrupt occurred -----------------------------------*/
01692     if (((itflags & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((itsources & SAI_IT_FREQ) == SAI_IT_FREQ))
01693     {
01694       hsai->InterruptServiceRoutine(hsai);
01695     }
01696     /* SAI Overrun error interrupt occurred ----------------------------------*/
01697     else if (((itflags & SAI_FLAG_OVRUDR) == SAI_FLAG_OVRUDR) && ((itsources & SAI_IT_OVRUDR) == SAI_IT_OVRUDR))
01698     {
01699       /* Clear the SAI Overrun flag */
01700       __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
01701       /* Get the SAI error code */
01702       tmperror = ((hsai->State == HAL_SAI_STATE_BUSY_RX) ? HAL_SAI_ERROR_OVR : HAL_SAI_ERROR_UDR);
01703       /* Change the SAI error code */
01704       hsai->ErrorCode |= tmperror;
01705       /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */
01706 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
01707       hsai->ErrorCallback(hsai);
01708 #else
01709       HAL_SAI_ErrorCallback(hsai);
01710 #endif
01711     }
01712     /* SAI mutedet interrupt occurred ----------------------------------*/
01713     else if (((itflags & SAI_FLAG_MUTEDET) == SAI_FLAG_MUTEDET) && ((itsources & SAI_IT_MUTEDET) == SAI_IT_MUTEDET))
01714     {
01715       /* Clear the SAI mutedet flag */
01716       __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_MUTEDET);
01717       /* call the call back function */
01718       if (hsai->mutecallback != NULL)
01719       {
01720         /* inform the user that an RX mute event has been detected */
01721         hsai->mutecallback();
01722       }
01723     }
01724     /* SAI AFSDET interrupt occurred ----------------------------------*/
01725     else if (((itflags & SAI_FLAG_AFSDET) == SAI_FLAG_AFSDET) && ((itsources & SAI_IT_AFSDET) == SAI_IT_AFSDET))
01726     {
01727       /* Clear the SAI AFSDET flag */
01728       __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_AFSDET);
01729
01730       /* Change the SAI error code */
01731       hsai->ErrorCode |= HAL_SAI_ERROR_AFSDET;
01732
01733       /* Check SAI DMA is enabled or not */
01734       if ((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
01735       {
01736         /* Abort the SAI DMA Streams */
01737         if (hsai->hdmatx != NULL)
01738         {
01739           /* Set the DMA Tx abort callback */
01740           hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
01741
01742           /* Abort DMA in IT mode */
01743           if (HAL_DMA_Abort_IT(hsai->hdmatx) != HAL_OK)
01744           {
01745             /* Update SAI error code */
01746             hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
01747
01748             /* Call SAI error callback */
01749 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
01750             hsai->ErrorCallback(hsai);
01751 #else
01752             HAL_SAI_ErrorCallback(hsai);
01753 #endif
01754           }
01755         }
01756         if (hsai->hdmarx != NULL)
01757         {
01758           /* Set the DMA Rx abort callback */
01759           hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
01760
01761           /* Abort DMA in IT mode */
01762           if (HAL_DMA_Abort_IT(hsai->hdmarx) != HAL_OK)
01763           {
01764             /* Update SAI error code */
01765             hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
01766
01767             /* Call SAI error callback */
01768 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
01769             hsai->ErrorCallback(hsai);
01770 #else
01771             HAL_SAI_ErrorCallback(hsai);
01772 #endif
01773           }
01774         }
01775       }
01776       else
01777       {
01778         /* Abort SAI */
01779         /* No need to check return value because HAL_SAI_ErrorCallback will be called later */
01780         (void) HAL_SAI_Abort(hsai);
01781
01782         /* Set error callback */
01783 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
01784         hsai->ErrorCallback(hsai);
01785 #else
01786         HAL_SAI_ErrorCallback(hsai);
01787 #endif
01788       }
01789     }
01790     /* SAI LFSDET interrupt occurred ----------------------------------*/
01791     else if (((itflags & SAI_FLAG_LFSDET) == SAI_FLAG_LFSDET) && ((itsources & SAI_IT_LFSDET) == SAI_IT_LFSDET))
01792     {
01793       /* Clear the SAI LFSDET flag */
01794       __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_LFSDET);
01795
01796       /* Change the SAI error code */
01797       hsai->ErrorCode |= HAL_SAI_ERROR_LFSDET;
01798
01799       /* Check SAI DMA is enabled or not */
01800       if ((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
01801       {
01802         /* Abort the SAI DMA Streams */
01803         if (hsai->hdmatx != NULL)
01804         {
01805           /* Set the DMA Tx abort callback */
01806           hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
01807
01808           /* Abort DMA in IT mode */
01809           if (HAL_DMA_Abort_IT(hsai->hdmatx) != HAL_OK)
01810           {
01811             /* Update SAI error code */
01812             hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
01813
01814             /* Call SAI error callback */
01815 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
01816             hsai->ErrorCallback(hsai);
01817 #else
01818             HAL_SAI_ErrorCallback(hsai);
01819 #endif
01820           }
01821         }
01822         if (hsai->hdmarx != NULL)
01823         {
01824           /* Set the DMA Rx abort callback */
01825           hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
01826
01827           /* Abort DMA in IT mode */
01828           if (HAL_DMA_Abort_IT(hsai->hdmarx) != HAL_OK)
01829           {
01830             /* Update SAI error code */
01831             hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
01832
01833             /* Call SAI error callback */
01834 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
01835             hsai->ErrorCallback(hsai);
01836 #else
01837             HAL_SAI_ErrorCallback(hsai);
01838 #endif
01839           }
01840         }
01841       }
01842       else
01843       {
01844         /* Abort SAI */
01845         /* No need to check return value because HAL_SAI_ErrorCallback will be called later */
01846         (void) HAL_SAI_Abort(hsai);
01847
01848         /* Set error callback */
01849 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
01850         hsai->ErrorCallback(hsai);
01851 #else
01852         HAL_SAI_ErrorCallback(hsai);
01853 #endif
01854       }
01855     }
01856     /* SAI WCKCFG interrupt occurred ----------------------------------*/
01857     else if (((itflags & SAI_FLAG_WCKCFG) == SAI_FLAG_WCKCFG) && ((itsources & SAI_IT_WCKCFG) == SAI_IT_WCKCFG))
01858     {
01859       /* Clear the SAI WCKCFG flag */
01860       __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_WCKCFG);
01861
01862       /* Change the SAI error code */
01863       hsai->ErrorCode |= HAL_SAI_ERROR_WCKCFG;
01864
01865       /* Check SAI DMA is enabled or not */
01866       if ((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
01867       {
01868         /* Abort the SAI DMA Streams */
01869         if (hsai->hdmatx != NULL)
01870         {
01871           /* Set the DMA Tx abort callback */
01872           hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
01873
01874           /* Abort DMA in IT mode */
01875           if (HAL_DMA_Abort_IT(hsai->hdmatx) != HAL_OK)
01876           {
01877             /* Update SAI error code */
01878             hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
01879
01880             /* Call SAI error callback */
01881 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
01882             hsai->ErrorCallback(hsai);
01883 #else
01884             HAL_SAI_ErrorCallback(hsai);
01885 #endif
01886           }
01887         }
01888         if (hsai->hdmarx != NULL)
01889         {
01890           /* Set the DMA Rx abort callback */
01891           hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
01892
01893           /* Abort DMA in IT mode */
01894           if (HAL_DMA_Abort_IT(hsai->hdmarx) != HAL_OK)
01895           {
01896             /* Update SAI error code */
01897             hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
01898
01899             /* Call SAI error callback */
01900 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
01901             hsai->ErrorCallback(hsai);
01902 #else
01903             HAL_SAI_ErrorCallback(hsai);
01904 #endif
01905           }
01906         }
01907       }
01908       else
01909       {
01910         /* If WCKCFG occurs, SAI audio block is automatically disabled */
01911         /* Disable all interrupts and clear all flags */
01912         hsai->Instance->IMR = 0U;
01913         hsai->Instance->CLRFR = 0xFFFFFFFFU;
01914         /* Set the SAI state to ready to be able to start again the process */
01915         hsai->State = HAL_SAI_STATE_READY;
01916
01917         /* Initialize XferCount */
01918         hsai->XferCount = 0U;
01919
01920         /* SAI error Callback */
01921 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
01922         hsai->ErrorCallback(hsai);
01923 #else
01924         HAL_SAI_ErrorCallback(hsai);
01925 #endif
01926       }
01927     }
01928     /* SAI CNRDY interrupt occurred ----------------------------------*/
01929     else if (((itflags & SAI_FLAG_CNRDY) == SAI_FLAG_CNRDY) && ((itsources & SAI_IT_CNRDY) == SAI_IT_CNRDY))
01930     {
01931       /* Clear the SAI CNRDY flag */
01932       __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_CNRDY);
01933       /* Change the SAI error code */
01934       hsai->ErrorCode |= HAL_SAI_ERROR_CNREADY;
01935       /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */
01936 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
01937       hsai->ErrorCallback(hsai);
01938 #else
01939       HAL_SAI_ErrorCallback(hsai);
01940 #endif
01941     }
01942     else
01943     {
01944       /* Nothing to do */
01945     }
01946   }
01947 }
01948
01949 /**
01950   * @brief Tx Transfer completed callback.
01951   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01952   *              the configuration information for SAI module.
01953   * @retval None
01954   */
01955 __weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai)
01956 {
01957   /* Prevent unused argument(s) compilation warning */
01958   UNUSED(hsai);
01959
01960   /* NOTE : This function should not be modified, when the callback is needed,
01961             the HAL_SAI_TxCpltCallback could be implemented in the user file
01962    */
01963 }
01964
01965 /**
01966   * @brief Tx Transfer Half completed callback.
01967   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01968   *              the configuration information for SAI module.
01969   * @retval None
01970   */
01971 __weak void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai)
01972 {
01973   /* Prevent unused argument(s) compilation warning */
01974   UNUSED(hsai);
01975
01976   /* NOTE : This function should not be modified, when the callback is needed,
01977             the HAL_SAI_TxHalfCpltCallback could be implemented in the user file
01978    */
01979 }
01980
01981 /**
01982   * @brief Rx Transfer completed callback.
01983   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
01984   *              the configuration information for SAI module.
01985   * @retval None
01986   */
01987 __weak void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai)
01988 {
01989   /* Prevent unused argument(s) compilation warning */
01990   UNUSED(hsai);
01991
01992   /* NOTE : This function should not be modified, when the callback is needed,
01993             the HAL_SAI_RxCpltCallback could be implemented in the user file
01994    */
01995 }
01996
01997 /**
01998   * @brief Rx Transfer half completed callback.
01999   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02000   *              the configuration information for SAI module.
02001   * @retval None
02002   */
02003 __weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai)
02004 {
02005   /* Prevent unused argument(s) compilation warning */
02006   UNUSED(hsai);
02007
02008   /* NOTE : This function should not be modified, when the callback is needed,
02009             the HAL_SAI_RxHalfCpltCallback could be implemented in the user file
02010    */
02011 }
02012
02013 /**
02014   * @brief SAI error callback.
02015   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02016   *              the configuration information for SAI module.
02017   * @retval None
02018   */
02019 __weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai)
02020 {
02021   /* Prevent unused argument(s) compilation warning */
02022   UNUSED(hsai);
02023
02024   /* NOTE : This function should not be modified, when the callback is needed,
02025             the HAL_SAI_ErrorCallback could be implemented in the user file
02026    */
02027 }
02028
02029 /**
02030   * @}
02031   */
02032
02033 /** @defgroup SAI_Exported_Functions_Group3 Peripheral State functions
02034   * @brief    Peripheral State functions
02035   *
02036 @verbatim
02037   ===============================================================================
02038                 ##### Peripheral State and Errors functions #####
02039   ===============================================================================
02040   [..]
02041     This subsection permits to get in run-time the status of the peripheral
02042     and the data flow.
02043
02044 @endverbatim
02045   * @{
02046   */
02047
02048 /**
02049   * @brief  Return the SAI handle state.
02050   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02051   *              the configuration information for SAI module.
02052   * @retval HAL state
02053   */
02054 HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai)
02055 {
02056   return hsai->State;
02057 }
02058
02059 /**
02060   * @brief  Return the SAI error code.
02061   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02062   *              the configuration information for the specified SAI Block.
02063   * @retval SAI Error Code
02064   */
02065 uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai)
02066 {
02067   return hsai->ErrorCode;
02068 }
02069
02070 /**
02071   * @}
02072   */
02073
02074 /**
02075   * @}
02076   */
02077
02078 /** @addtogroup SAI_Private_Functions
02079   * @brief      Private functions
02080   * @{
02081   */
02082
02083 /**
02084   * @brief  Initialize the SAI I2S protocol according to the specified parameters
02085   *         in the SAI_InitTypeDef and create the associated handle.
02086   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02087   *              the configuration information for SAI module.
02088   * @param  protocol one of the supported protocol.
02089   * @param  datasize one of the supported datasize @ref SAI_Protocol_DataSize.
02090   * @param  nbslot number of slot minimum value is 2 and max is 16.
02091   *         the value must be a multiple of 2.
02092   * @retval HAL status
02093   */
02094 static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
02095 {
02096   HAL_StatusTypeDef status = HAL_OK;
02097
02098   hsai->Init.Protocol            = SAI_FREE_PROTOCOL;
02099   hsai->Init.FirstBit            = SAI_FIRSTBIT_MSB;
02100   /* Compute ClockStrobing according AudioMode */
02101   if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
02102   {
02103     /* Transmit */
02104     hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_FALLINGEDGE;
02105   }
02106   else
02107   {
02108     /* Receive */
02109     hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_RISINGEDGE;
02110   }
02111   hsai->FrameInit.FSDefinition   = SAI_FS_CHANNEL_IDENTIFICATION;
02112   hsai->SlotInit.SlotActive      = SAI_SLOTACTIVE_ALL;
02113   hsai->SlotInit.FirstBitOffset  = 0;
02114   hsai->SlotInit.SlotNumber      = nbslot;
02115
02116   /* in IS2 the number of slot must be even */
02117   if ((nbslot & 0x1U) != 0U)
02118   {
02119     return HAL_ERROR;
02120   }
02121
02122   if (protocol == SAI_I2S_STANDARD)
02123   {
02124     hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW;
02125     hsai->FrameInit.FSOffset   = SAI_FS_BEFOREFIRSTBIT;
02126   }
02127   else
02128   {
02129      /* SAI_I2S_MSBJUSTIFIED or SAI_I2S_LSBJUSTIFIED */
02130     hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH;
02131     hsai->FrameInit.FSOffset   = SAI_FS_FIRSTBIT;
02132   }
02133
02134   /* Frame definition */
02135   switch (datasize)
02136   {
02137     case SAI_PROTOCOL_DATASIZE_16BIT:
02138       hsai->Init.DataSize = SAI_DATASIZE_16;
02139       hsai->FrameInit.FrameLength = 32U * (nbslot / 2U);
02140       hsai->FrameInit.ActiveFrameLength = 16U * (nbslot / 2U);
02141       hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;
02142       break;
02143     case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :
02144       hsai->Init.DataSize = SAI_DATASIZE_16;
02145       hsai->FrameInit.FrameLength = 64U * (nbslot / 2U);
02146       hsai->FrameInit.ActiveFrameLength = 32U * (nbslot / 2U);
02147       hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
02148       break;
02149     case SAI_PROTOCOL_DATASIZE_24BIT:
02150       hsai->Init.DataSize = SAI_DATASIZE_24;
02151       hsai->FrameInit.FrameLength = 64U * (nbslot / 2U);
02152       hsai->FrameInit.ActiveFrameLength = 32U * (nbslot / 2U);
02153       hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
02154       break;
02155     case SAI_PROTOCOL_DATASIZE_32BIT:
02156       hsai->Init.DataSize = SAI_DATASIZE_32;
02157       hsai->FrameInit.FrameLength = 64U * (nbslot / 2U);
02158       hsai->FrameInit.ActiveFrameLength = 32U * (nbslot / 2U);
02159       hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
02160       break;
02161     default :
02162       status = HAL_ERROR;
02163       break;
02164   }
02165   if (protocol == SAI_I2S_LSBJUSTIFIED)
02166   {
02167     if (datasize == SAI_PROTOCOL_DATASIZE_16BITEXTENDED)
02168     {
02169       hsai->SlotInit.FirstBitOffset = 16;
02170     }
02171     if (datasize == SAI_PROTOCOL_DATASIZE_24BIT)
02172     {
02173       hsai->SlotInit.FirstBitOffset = 8;
02174     }
02175   }
02176   return status;
02177 }
02178
02179 /**
02180   * @brief  Initialize the SAI PCM protocol according to the specified parameters
02181   *         in the SAI_InitTypeDef and create the associated handle.
02182   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02183   *              the configuration information for SAI module.
02184   * @param  protocol one of the supported protocol
02185   * @param  datasize one of the supported datasize @ref SAI_Protocol_DataSize
02186   * @param  nbslot number of slot minimum value is 1 and the max is 16.
02187   * @retval HAL status
02188   */
02189 static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
02190 {
02191   HAL_StatusTypeDef status = HAL_OK;
02192
02193   hsai->Init.Protocol            = SAI_FREE_PROTOCOL;
02194   hsai->Init.FirstBit            = SAI_FIRSTBIT_MSB;
02195   /* Compute ClockStrobing according AudioMode */
02196   if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
02197   {
02198     /* Transmit */
02199     hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_RISINGEDGE;
02200   }
02201   else
02202   {
02203     /* Receive */
02204     hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_FALLINGEDGE;
02205   }
02206   hsai->FrameInit.FSDefinition   = SAI_FS_STARTFRAME;
02207   hsai->FrameInit.FSPolarity     = SAI_FS_ACTIVE_HIGH;
02208   hsai->FrameInit.FSOffset       = SAI_FS_BEFOREFIRSTBIT;
02209   hsai->SlotInit.FirstBitOffset  = 0;
02210   hsai->SlotInit.SlotNumber      = nbslot;
02211   hsai->SlotInit.SlotActive      = SAI_SLOTACTIVE_ALL;
02212
02213   if (protocol == SAI_PCM_SHORT)
02214   {
02215     hsai->FrameInit.ActiveFrameLength = 1;
02216   }
02217   else
02218   {
02219     /* SAI_PCM_LONG */
02220     hsai->FrameInit.ActiveFrameLength = 13;
02221   }
02222
02223   switch (datasize)
02224   {
02225     case SAI_PROTOCOL_DATASIZE_16BIT:
02226       hsai->Init.DataSize = SAI_DATASIZE_16;
02227       hsai->FrameInit.FrameLength = 16U * nbslot;
02228       hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;
02229       break;
02230     case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :
02231       hsai->Init.DataSize = SAI_DATASIZE_16;
02232       hsai->FrameInit.FrameLength = 32U * nbslot;
02233       hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
02234       break;
02235     case SAI_PROTOCOL_DATASIZE_24BIT :
02236       hsai->Init.DataSize = SAI_DATASIZE_24;
02237       hsai->FrameInit.FrameLength = 32U * nbslot;
02238       hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
02239       break;
02240     case SAI_PROTOCOL_DATASIZE_32BIT:
02241       hsai->Init.DataSize = SAI_DATASIZE_32;
02242       hsai->FrameInit.FrameLength = 32U * nbslot;
02243       hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
02244       break;
02245     default :
02246       status = HAL_ERROR;
02247       break;
02248   }
02249
02250   return status;
02251 }
02252
02253 /**
02254   * @brief  Fill the fifo.
02255   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02256   *              the configuration information for SAI module.
02257   * @retval None
02258   */
02259 static void SAI_FillFifo(SAI_HandleTypeDef *hsai)
02260 {
02261   uint32_t temp;
02262
02263   /* fill the fifo with data before to enabled the SAI */
02264   while (((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) && (hsai->XferCount > 0U))
02265   {
02266     if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
02267     {
02268       hsai->Instance->DR = *hsai->pBuffPtr;
02269       hsai->pBuffPtr++;
02270     }
02271     else if (hsai->Init.DataSize <= SAI_DATASIZE_16)
02272     {
02273       temp = (uint32_t)(*hsai->pBuffPtr);
02274       hsai->pBuffPtr++;
02275       temp |= ((uint32_t)(*hsai->pBuffPtr) << 8);
02276       hsai->pBuffPtr++;
02277       hsai->Instance->DR = temp;
02278     }
02279     else
02280     {
02281       temp = (uint32_t)(*hsai->pBuffPtr);
02282       hsai->pBuffPtr++;
02283       temp |= ((uint32_t)(*hsai->pBuffPtr) << 8);
02284       hsai->pBuffPtr++;
02285       temp |= ((uint32_t)(*hsai->pBuffPtr) << 16);
02286       hsai->pBuffPtr++;
02287       temp |= ((uint32_t)(*hsai->pBuffPtr) << 24);
02288       hsai->pBuffPtr++;
02289       hsai->Instance->DR = temp;
02290     }
02291     hsai->XferCount--;
02292   }
02293 }
02294
02295 /**
02296   * @brief  Return the interrupt flag to set according the SAI setup.
02297   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02298   *              the configuration information for SAI module.
02299   * @param  mode SAI_MODE_DMA or SAI_MODE_IT
02300   * @retval the list of the IT flag to enable
02301   */
02302 static uint32_t SAI_InterruptFlag(const SAI_HandleTypeDef *hsai, SAI_ModeTypedef mode)
02303 {
02304   uint32_t tmpIT = SAI_IT_OVRUDR;
02305
02306   if (mode == SAI_MODE_IT)
02307   {
02308     tmpIT |= SAI_IT_FREQ;
02309   }
02310
02311   if ((hsai->Init.Protocol == SAI_AC97_PROTOCOL) &&
02312       ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODEMASTER_RX)))
02313   {
02314     tmpIT |= SAI_IT_CNRDY;
02315   }
02316
02317   if ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
02318   {
02319     tmpIT |= SAI_IT_AFSDET | SAI_IT_LFSDET;
02320   }
02321   else
02322   {
02323     /* hsai has been configured in master mode */
02324     tmpIT |= SAI_IT_WCKCFG;
02325   }
02326   return tmpIT;
02327 }
02328
02329 /**
02330   * @brief  Disable the SAI and wait for the disabling.
02331   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02332   *              the configuration information for SAI module.
02333   * @retval None
02334   */
02335 static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai)
02336 {
02337   register uint32_t count = SAI_DEFAULT_TIMEOUT * (SystemCoreClock / 7U / 1000U);
02338   HAL_StatusTypeDef status = HAL_OK;
02339
02340   /* Disable the SAI instance */
02341   __HAL_SAI_DISABLE(hsai);
02342
02343   do
02344   {
02345     /* Check for the Timeout */
02346     if (count == 0U)
02347     {
02348       /* Update error code */
02349       hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
02350       status = HAL_TIMEOUT;
02351       break;
02352     }
02353     count--;
02354   }
02355   while ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != 0U);
02356
02357   return status;
02358 }
02359
02360 /**
02361   * @brief  Tx Handler for Transmit in Interrupt mode 8-Bit transfer.
02362   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02363   *              the configuration information for SAI module.
02364   * @retval None
02365   */
02366 static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai)
02367 {
02368   if (hsai->XferCount == 0U)
02369   {
02370     /* Handle the end of the transmission */
02371     /* Disable FREQ and OVRUDR interrupts */
02372     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
02373     hsai->State = HAL_SAI_STATE_READY;
02374 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02375     hsai->TxCpltCallback(hsai);
02376 #else
02377     HAL_SAI_TxCpltCallback(hsai);
02378 #endif
02379   }
02380   else
02381   {
02382     /* Write data on DR register */
02383     hsai->Instance->DR = *hsai->pBuffPtr;
02384     hsai->pBuffPtr++;
02385     hsai->XferCount--;
02386   }
02387 }
02388
02389 /**
02390   * @brief  Tx Handler for Transmit in Interrupt mode for 16-Bit transfer.
02391   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02392   *              the configuration information for SAI module.
02393   * @retval None
02394   */
02395 static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai)
02396 {
02397   if (hsai->XferCount == 0U)
02398   {
02399     /* Handle the end of the transmission */
02400     /* Disable FREQ and OVRUDR interrupts */
02401     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
02402     hsai->State = HAL_SAI_STATE_READY;
02403 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02404     hsai->TxCpltCallback(hsai);
02405 #else
02406     HAL_SAI_TxCpltCallback(hsai);
02407 #endif
02408   }
02409   else
02410   {
02411     /* Write data on DR register */
02412     uint32_t temp;
02413     temp = (uint32_t)(*hsai->pBuffPtr);
02414     hsai->pBuffPtr++;
02415     temp |= ((uint32_t)(*hsai->pBuffPtr) << 8);
02416     hsai->pBuffPtr++;
02417     hsai->Instance->DR = temp;
02418     hsai->XferCount--;
02419   }
02420 }
02421
02422 /**
02423   * @brief  Tx Handler for Transmit in Interrupt mode for 32-Bit transfer.
02424   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02425   *              the configuration information for SAI module.
02426   * @retval None
02427   */
02428 static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai)
02429 {
02430   if (hsai->XferCount == 0U)
02431   {
02432     /* Handle the end of the transmission */
02433     /* Disable FREQ and OVRUDR interrupts */
02434     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
02435     hsai->State = HAL_SAI_STATE_READY;
02436 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02437     hsai->TxCpltCallback(hsai);
02438 #else
02439     HAL_SAI_TxCpltCallback(hsai);
02440 #endif
02441   }
02442   else
02443   {
02444     /* Write data on DR register */
02445     uint32_t temp;
02446     temp = (uint32_t)(*hsai->pBuffPtr);
02447     hsai->pBuffPtr++;
02448     temp |= ((uint32_t)(*hsai->pBuffPtr) << 8);
02449     hsai->pBuffPtr++;
02450     temp |= ((uint32_t)(*hsai->pBuffPtr) << 16);
02451     hsai->pBuffPtr++;
02452     temp |= ((uint32_t)(*hsai->pBuffPtr) << 24);
02453     hsai->pBuffPtr++;
02454     hsai->Instance->DR = temp;
02455     hsai->XferCount--;
02456   }
02457 }
02458
02459 /**
02460   * @brief  Rx Handler for Receive in Interrupt mode 8-Bit transfer.
02461   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02462   *              the configuration information for SAI module.
02463   * @retval None
02464   */
02465 static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai)
02466 {
02467   /* Receive data */
02468   *hsai->pBuffPtr = (uint8_t)hsai->Instance->DR;
02469   hsai->pBuffPtr++;
02470   hsai->XferCount--;
02471
02472   /* Check end of the transfer */
02473   if (hsai->XferCount == 0U)
02474   {
02475     /* Disable TXE and OVRUDR interrupts */
02476     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
02477
02478     /* Clear the SAI Overrun flag */
02479     __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
02480
02481     hsai->State = HAL_SAI_STATE_READY;
02482 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02483     hsai->RxCpltCallback(hsai);
02484 #else
02485     HAL_SAI_RxCpltCallback(hsai);
02486 #endif
02487   }
02488 }
02489
02490 /**
02491   * @brief  Rx Handler for Receive in Interrupt mode for 16-Bit transfer.
02492   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02493   *              the configuration information for SAI module.
02494   * @retval None
02495   */
02496 static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai)
02497 {
02498   uint32_t temp;
02499
02500   /* Receive data */
02501   temp = hsai->Instance->DR;
02502   *hsai->pBuffPtr = (uint8_t)temp;
02503   hsai->pBuffPtr++;
02504   *hsai->pBuffPtr = (uint8_t)(temp >> 8);
02505   hsai->pBuffPtr++;
02506   hsai->XferCount--;
02507
02508   /* Check end of the transfer */
02509   if (hsai->XferCount == 0U)
02510   {
02511     /* Disable TXE and OVRUDR interrupts */
02512     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
02513
02514     /* Clear the SAI Overrun flag */
02515     __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
02516
02517     hsai->State = HAL_SAI_STATE_READY;
02518 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02519     hsai->RxCpltCallback(hsai);
02520 #else
02521     HAL_SAI_RxCpltCallback(hsai);
02522 #endif
02523   }
02524 }
02525
02526 /**
02527   * @brief  Rx Handler for Receive in Interrupt mode for 32-Bit transfer.
02528   * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
02529   *              the configuration information for SAI module.
02530   * @retval None
02531   */
02532 static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai)
02533 {
02534   uint32_t temp;
02535
02536   /* Receive data */
02537   temp = hsai->Instance->DR;
02538   *hsai->pBuffPtr = (uint8_t)temp;
02539   hsai->pBuffPtr++;
02540   *hsai->pBuffPtr = (uint8_t)(temp >> 8);
02541   hsai->pBuffPtr++;
02542   *hsai->pBuffPtr = (uint8_t)(temp >> 16);
02543   hsai->pBuffPtr++;
02544   *hsai->pBuffPtr = (uint8_t)(temp >> 24);
02545   hsai->pBuffPtr++;
02546   hsai->XferCount--;
02547
02548   /* Check end of the transfer */
02549   if (hsai->XferCount == 0U)
02550   {
02551     /* Disable TXE and OVRUDR interrupts */
02552     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
02553
02554     /* Clear the SAI Overrun flag */
02555     __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
02556
02557     hsai->State = HAL_SAI_STATE_READY;
02558 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02559     hsai->RxCpltCallback(hsai);
02560 #else
02561     HAL_SAI_RxCpltCallback(hsai);
02562 #endif
02563   }
02564 }
02565
02566 /**
02567   * @brief  DMA SAI transmit process complete callback.
02568   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
02569   *              the configuration information for the specified DMA module.
02570   * @retval None
02571   */
02572 static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma)
02573 {
02574   SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02575
02576   if (hdma->Init.Mode != DMA_CIRCULAR)
02577   {
02578     hsai->XferCount = 0;
02579
02580     /* Disable SAI Tx DMA Request */
02581     hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
02582
02583     /* Stop the interrupts error handling */
02584     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
02585
02586     hsai->State = HAL_SAI_STATE_READY;
02587   }
02588 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02589   hsai->TxCpltCallback(hsai);
02590 #else
02591   HAL_SAI_TxCpltCallback(hsai);
02592 #endif
02593 }
02594
02595 /**
02596   * @brief  DMA SAI transmit process half complete callback.
02597   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
02598   *              the configuration information for the specified DMA module.
02599   * @retval None
02600   */
02601 static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
02602 {
02603   SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02604
02605 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02606   hsai->TxHalfCpltCallback(hsai);
02607 #else
02608   HAL_SAI_TxHalfCpltCallback(hsai);
02609 #endif
02610 }
02611
02612 /**
02613   * @brief  DMA SAI receive process complete callback.
02614   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
02615   *              the configuration information for the specified DMA module.
02616   * @retval None
02617   */
02618 static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma)
02619 {
02620   SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02621
02622   if (hdma->Init.Mode != DMA_CIRCULAR)
02623   {
02624     /* Disable Rx DMA Request */
02625     hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
02626     hsai->XferCount = 0;
02627
02628     /* Stop the interrupts error handling */
02629     __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
02630
02631     hsai->State = HAL_SAI_STATE_READY;
02632   }
02633 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02634   hsai->RxCpltCallback(hsai);
02635 #else
02636   HAL_SAI_RxCpltCallback(hsai);
02637 #endif
02638 }
02639
02640 /**
02641   * @brief  DMA SAI receive process half complete callback
02642   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
02643   *              the configuration information for the specified DMA module.
02644   * @retval None
02645   */
02646 static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
02647 {
02648   SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02649
02650 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02651   hsai->RxHalfCpltCallback(hsai);
02652 #else
02653   HAL_SAI_RxHalfCpltCallback(hsai);
02654 #endif
02655 }
02656
02657 /**
02658   * @brief  DMA SAI communication error callback.
02659   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
02660   *              the configuration information for the specified DMA module.
02661   * @retval None
02662   */
02663 static void SAI_DMAError(DMA_HandleTypeDef *hdma)
02664 {
02665   SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02666
02667   /* Set SAI error code */
02668   hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
02669
02670   /* Disable the SAI DMA request */
02671   hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
02672
02673   /* Disable SAI peripheral */
02674   /* No need to check return value because state will be updated and HAL_SAI_ErrorCallback will be called later */
02675   (void) SAI_Disable(hsai);
02676
02677   /* Set the SAI state ready to be able to start again the process */
02678   hsai->State = HAL_SAI_STATE_READY;
02679
02680   /* Initialize XferCount */
02681   hsai->XferCount = 0U;
02682
02683   /* SAI error Callback */
02684 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02685   hsai->ErrorCallback(hsai);
02686 #else
02687   HAL_SAI_ErrorCallback(hsai);
02688 #endif
02689 }
02690
02691 /**
02692   * @brief  DMA SAI Abort callback.
02693   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
02694   *              the configuration information for the specified DMA module.
02695   * @retval None
02696   */
02697 static void SAI_DMAAbort(DMA_HandleTypeDef *hdma)
02698 {
02699   SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02700
02701   /* Disable DMA request */
02702   hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
02703
02704   /* Disable all interrupts and clear all flags */
02705   hsai->Instance->IMR = 0U;
02706   hsai->Instance->CLRFR = 0xFFFFFFFFU;
02707
02708   if (hsai->ErrorCode != HAL_SAI_ERROR_WCKCFG)
02709   {
02710     /* Disable SAI peripheral */
02711     /* No need to check return value because state will be updated and HAL_SAI_ErrorCallback will be called later */
02712     (void) SAI_Disable(hsai);
02713
02714     /* Flush the fifo */
02715     SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
02716   }
02717   /* Set the SAI state to ready to be able to start again the process */
02718   hsai->State = HAL_SAI_STATE_READY;
02719
02720   /* Initialize XferCount */
02721   hsai->XferCount = 0U;
02722
02723   /* SAI error Callback */
02724 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
02725   hsai->ErrorCallback(hsai);
02726 #else
02727   HAL_SAI_ErrorCallback(hsai);
02728 #endif
02729 }
02730
02731 /**
02732   * @}
02733   */
02734
02735 /**
02736   * @}
02737   */
02738
02739 #endif /* SAI1 */
02740
02741 #endif /* HAL_SAI_MODULE_ENABLED */
02742 /**
02743   * @}
02744   */
02745
02746 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:35 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_sai.h Source File

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stm32wbxx_hal_sai.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_sai.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SAI HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_SAI_H
00022 #define STM32WBxx_HAL_SAI_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 /** @addtogroup STM32WBxx_HAL_Driver
00032   * @{
00033   */
00034
00035 #if defined (SAI1)
00036
00037 /** @addtogroup SAI
00038   * @{
00039   */
00040
00041 /* Exported types ------------------------------------------------------------*/
00042 /** @defgroup SAI_Exported_Types SAI Exported Types
00043   * @{
00044   */
00045
00046 /**
00047   * @brief  HAL State structures definition
00048   */
00049 typedef enum
00050 {
00051   HAL_SAI_STATE_RESET   = 0x00U, /*!< SAI not yet initialized or disabled  */
00052   HAL_SAI_STATE_READY   = 0x01U, /*!< SAI initialized and ready for use    */
00053   HAL_SAI_STATE_BUSY    = 0x02U, /*!< SAI internal process is ongoing      */
00054   HAL_SAI_STATE_BUSY_TX = 0x12U, /*!< Data transmission process is ongoing */
00055   HAL_SAI_STATE_BUSY_RX = 0x22U, /*!< Data reception process is ongoing    */
00056 } HAL_SAI_StateTypeDef;
00057
00058 /**
00059   * @brief  SAI Callback prototype
00060   */
00061 typedef void (*SAIcallback)(void);
00062
00063 /** @defgroup SAI_PDM_Structure_definition SAI PDM Structure definition
00064   * @brief  SAI PDM Init structure definition
00065   * @{
00066   */
00067 typedef struct
00068 {
00069   FunctionalState  Activation;  /*!< Enable/disable PDM interface */
00070   uint32_t         MicPairsNbr; /*!< Specifies the number of microphone pairs used.
00071                                      This parameter must be a number between Min_Data = 1 and Max_Data = 3. */
00072   uint32_t         ClockEnable; /*!< Specifies which clock must be enabled.
00073                                      This parameter can be a values combination of @ref SAI_PDM_ClockEnable */
00074 } SAI_PdmInitTypeDef;
00075 /**
00076   * @}
00077   */
00078
00079 /** @defgroup SAI_Init_Structure_definition SAI Init Structure definition
00080   * @brief  SAI Init Structure definition
00081   * @{
00082   */
00083 typedef struct
00084 {
00085   uint32_t AudioMode;           /*!< Specifies the SAI Block audio Mode.
00086                                      This parameter can be a value of @ref SAI_Block_Mode */
00087
00088   uint32_t Synchro;             /*!< Specifies SAI Block synchronization
00089                                      This parameter can be a value of @ref SAI_Block_Synchronization */
00090
00091   uint32_t SynchroExt;          /*!< Specifies SAI external output synchronization, this setup is common
00092                                      for BlockA and BlockB
00093                                      This parameter can be a value of @ref SAI_Block_SyncExt
00094                                      @note If both audio blocks of same SAI are used, this parameter has
00095                                            to be set to the same value for each audio block */
00096
00097   uint32_t MckOutput;           /*!< Specifies whether master clock output will be generated or not.
00098                                      This parameter can be a value of @ref SAI_Block_MckOutput */
00099
00100   uint32_t OutputDrive;         /*!< Specifies when SAI Block outputs are driven.
00101                                      This parameter can be a value of @ref SAI_Block_Output_Drive
00102                                      @note This value has to be set before enabling the audio block
00103                                            but after the audio block configuration. */
00104
00105   uint32_t NoDivider;           /*!< Specifies whether master clock will be divided or not.
00106                                      This parameter can be a value of @ref SAI_Block_NoDivider
00107                                      @note If bit NODIV in the SAI_xCR1 register is cleared, the frame length
00108                                            should be aligned to a number equal to a power of 2, from 8 to 256.
00109                                            If bit NODIV in the SAI_xCR1 register is set, the frame length can
00110                                            take any of the values from 8 to 256. */
00111
00112   uint32_t FIFOThreshold;       /*!< Specifies SAI Block FIFO threshold.
00113                                      This parameter can be a value of @ref SAI_Block_Fifo_Threshold */
00114
00115   uint32_t AudioFrequency;      /*!< Specifies the audio frequency sampling.
00116                                      This parameter can be a value of @ref SAI_Audio_Frequency */
00117
00118   uint32_t Mckdiv;              /*!< Specifies the master clock divider.
00119                                      This parameter must be a number between Min_Data = 0 and Max_Data = 63.
00120                                      @note This parameter is used only if AudioFrequency is set to
00121                                            SAI_AUDIO_FREQUENCY_MCKDIV otherwise it is internally computed. */
00122
00123   uint32_t MckOverSampling;     /*!< Specifies the master clock oversampling.
00124                                      This parameter can be a value of @ref SAI_Block_Mck_OverSampling */
00125
00126   uint32_t MonoStereoMode;      /*!< Specifies if the mono or stereo mode is selected.
00127                                      This parameter can be a value of @ref SAI_Mono_Stereo_Mode */
00128
00129   uint32_t CompandingMode;      /*!< Specifies the companding mode type.
00130                                      This parameter can be a value of @ref SAI_Block_Companding_Mode */
00131
00132   uint32_t TriState;            /*!< Specifies the companding mode type.
00133                                      This parameter can be a value of @ref SAI_TRIState_Management */
00134
00135   SAI_PdmInitTypeDef PdmInit;   /*!< Specifies the PDM configuration. */
00136
00137   /* This part of the structure is automatically filled if your are using the high level initialisation
00138      function HAL_SAI_InitProtocol */
00139
00140   uint32_t Protocol;        /*!< Specifies the SAI Block protocol.
00141                                  This parameter can be a value of @ref SAI_Block_Protocol */
00142
00143   uint32_t DataSize;        /*!< Specifies the SAI Block data size.
00144                                  This parameter can be a value of @ref SAI_Block_Data_Size */
00145
00146   uint32_t FirstBit;        /*!< Specifies whether data transfers start from MSB or LSB bit.
00147                                  This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission */
00148
00149   uint32_t ClockStrobing;   /*!< Specifies the SAI Block clock strobing edge sensitivity.
00150                                  This parameter can be a value of @ref SAI_Block_Clock_Strobing */
00151 } SAI_InitTypeDef;
00152 /**
00153   * @}
00154   */
00155
00156 /** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition
00157   * @brief  SAI Frame Init structure definition
00158   * @note   For SPDIF and AC97 protocol, these parameters are not used (set by hardware).
00159   * @{
00160   */
00161 typedef struct
00162 {
00163
00164   uint32_t FrameLength;        /*!< Specifies the Frame length, the number of SCK clocks for each audio frame.
00165                                     This parameter must be a number between Min_Data = 8 and Max_Data = 256.
00166                                     @note If master clock MCLK_x pin is declared as an output, the frame length
00167                                           should be aligned to a number equal to power of 2 in order to keep
00168                                           in an audio frame, an integer number of MCLK pulses by bit Clock. */
00169
00170   uint32_t ActiveFrameLength;  /*!< Specifies the Frame synchronization active level length.
00171                                     This Parameter specifies the length in number of bit clock (SCK + 1)
00172                                     of the active level of FS signal in audio frame.
00173                                     This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
00174
00175   uint32_t FSDefinition;       /*!< Specifies the Frame synchronization definition.
00176                                     This parameter can be a value of @ref SAI_Block_FS_Definition */
00177
00178   uint32_t FSPolarity;         /*!< Specifies the Frame synchronization Polarity.
00179                                     This parameter can be a value of @ref SAI_Block_FS_Polarity */
00180
00181   uint32_t FSOffset;           /*!< Specifies the Frame synchronization Offset.
00182                                     This parameter can be a value of @ref SAI_Block_FS_Offset */
00183
00184 } SAI_FrameInitTypeDef;
00185 /**
00186   * @}
00187   */
00188
00189 /** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition
00190   * @brief   SAI Block Slot Init Structure definition
00191   * @note    For SPDIF protocol, these parameters are not used (set by hardware).
00192   * @note    For AC97 protocol, only SlotActive parameter is used (the others are set by hardware).
00193   * @{
00194   */
00195 typedef struct
00196 {
00197   uint32_t FirstBitOffset;  /*!< Specifies the position of first data transfer bit in the slot.
00198                                  This parameter must be a number between Min_Data = 0 and Max_Data = 24 */
00199
00200   uint32_t SlotSize;        /*!< Specifies the Slot Size.
00201                                  This parameter can be a value of @ref SAI_Block_Slot_Size */
00202
00203   uint32_t SlotNumber;      /*!< Specifies the number of slot in the audio frame.
00204                                  This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
00205
00206   uint32_t SlotActive;      /*!< Specifies the slots in audio frame that will be activated.
00207                                  This parameter can be a value of @ref SAI_Block_Slot_Active */
00208 } SAI_SlotInitTypeDef;
00209 /**
00210   * @}
00211   */
00212
00213 /** @defgroup SAI_Handle_Structure_definition SAI Handle Structure definition
00214   * @brief  SAI handle Structure definition
00215   * @{
00216   */
00217 typedef struct __SAI_HandleTypeDef
00218 {
00219   SAI_Block_TypeDef         *Instance;    /*!< SAI Blockx registers base address */
00220
00221   SAI_InitTypeDef           Init;         /*!< SAI communication parameters */
00222
00223   SAI_FrameInitTypeDef      FrameInit;    /*!< SAI Frame configuration parameters */
00224
00225   SAI_SlotInitTypeDef       SlotInit;     /*!< SAI Slot configuration parameters */
00226
00227   uint8_t                  *pBuffPtr;     /*!< Pointer to SAI transfer Buffer */
00228
00229   uint16_t                  XferSize;     /*!< SAI transfer size */
00230
00231   uint16_t                  XferCount;    /*!< SAI transfer counter */
00232
00233   DMA_HandleTypeDef         *hdmatx;      /*!< SAI Tx DMA handle parameters */
00234
00235   DMA_HandleTypeDef         *hdmarx;      /*!< SAI Rx DMA handle parameters */
00236
00237   SAIcallback               mutecallback; /*!< SAI mute callback */
00238
00239   void (*InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai); /* function pointer for IRQ handler */
00240
00241   HAL_LockTypeDef           Lock;         /*!< SAI locking object */
00242
00243   __IO HAL_SAI_StateTypeDef State;        /*!< SAI communication state */
00244
00245   __IO uint32_t             ErrorCode;    /*!< SAI Error code */
00246
00247 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
00248   void (*RxCpltCallback)(struct __SAI_HandleTypeDef *hsai);      /*!< SAI receive complete callback */
00249   void (*RxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai);  /*!< SAI receive half complete callback */
00250   void (*TxCpltCallback)(struct __SAI_HandleTypeDef *hsai);      /*!< SAI transmit complete callback */
00251   void (*TxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai);  /*!< SAI transmit half complete callback */
00252   void (*ErrorCallback)(struct __SAI_HandleTypeDef *hsai);       /*!< SAI error callback */
00253   void (*MspInitCallback)(struct __SAI_HandleTypeDef *hsai);     /*!< SAI MSP init callback */
00254   void (*MspDeInitCallback)(struct __SAI_HandleTypeDef *hsai);   /*!< SAI MSP de-init callback */
00255 #endif
00256 } SAI_HandleTypeDef;
00257 /**
00258   * @}
00259   */
00260
00261 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
00262 /**
00263   * @brief  SAI callback ID enumeration definition
00264   */
00265 typedef enum
00266 {
00267   HAL_SAI_RX_COMPLETE_CB_ID     = 0x00U, /*!< SAI receive complete callback ID */
00268   HAL_SAI_RX_HALFCOMPLETE_CB_ID = 0x01U, /*!< SAI receive half complete callback ID */
00269   HAL_SAI_TX_COMPLETE_CB_ID     = 0x02U, /*!< SAI transmit complete callback ID */
00270   HAL_SAI_TX_HALFCOMPLETE_CB_ID = 0x03U, /*!< SAI transmit half complete callback ID */
00271   HAL_SAI_ERROR_CB_ID           = 0x04U, /*!< SAI error callback ID */
00272   HAL_SAI_MSPINIT_CB_ID         = 0x05U, /*!< SAI MSP init callback ID */
00273   HAL_SAI_MSPDEINIT_CB_ID       = 0x06U  /*!< SAI MSP de-init callback ID */
00274 } HAL_SAI_CallbackIDTypeDef;
00275
00276 /**
00277   * @brief  SAI callback pointer definition
00278   */
00279 typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
00280 #endif
00281
00282 /**
00283   * @}
00284   */
00285
00286 /* Exported constants --------------------------------------------------------*/
00287 /** @defgroup SAI_Exported_Constants SAI Exported Constants
00288   * @{
00289   */
00290
00291 /** @defgroup SAI_Error_Code SAI Error Code
00292   * @{
00293   */
00294 #define HAL_SAI_ERROR_NONE             0x00000000U  /*!< No error */
00295 #define HAL_SAI_ERROR_OVR              0x00000001U  /*!< Overrun Error */
00296 #define HAL_SAI_ERROR_UDR              0x00000002U  /*!< Underrun error */
00297 #define HAL_SAI_ERROR_AFSDET           0x00000004U  /*!< Anticipated Frame synchronisation detection */
00298 #define HAL_SAI_ERROR_LFSDET           0x00000008U  /*!< Late Frame synchronisation detection */
00299 #define HAL_SAI_ERROR_CNREADY          0x00000010U  /*!< codec not ready */
00300 #define HAL_SAI_ERROR_WCKCFG           0x00000020U  /*!< Wrong clock configuration */
00301 #define HAL_SAI_ERROR_TIMEOUT          0x00000040U  /*!< Timeout error */
00302 #define HAL_SAI_ERROR_DMA              0x00000080U  /*!< DMA error */
00303 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
00304 #define HAL_SAI_ERROR_INVALID_CALLBACK 0x00000100U  /*!< Invalid callback error */
00305 #endif
00306 /**
00307   * @}
00308   */
00309
00310 /** @defgroup SAI_Block_SyncExt SAI External synchronisation
00311   * @{
00312   */
00313 #define SAI_SYNCEXT_DISABLE          0U
00314 #define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1U
00315 #define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2U
00316 /**
00317   * @}
00318   */
00319
00320 /** @defgroup SAI_Block_MckOutput SAI Block Master Clock Output
00321   * @{
00322   */
00323 #define SAI_MCK_OUTPUT_DISABLE      0x00000000U
00324 #define SAI_MCK_OUTPUT_ENABLE       SAI_xCR1_MCKEN
00325 /**
00326   * @}
00327   */
00328
00329 /** @defgroup SAI_Protocol SAI Supported protocol
00330   * @{
00331   */
00332 #define SAI_I2S_STANDARD      0U
00333 #define SAI_I2S_MSBJUSTIFIED  1U
00334 #define SAI_I2S_LSBJUSTIFIED  2U
00335 #define SAI_PCM_LONG          3U
00336 #define SAI_PCM_SHORT         4U
00337 /**
00338   * @}
00339   */
00340
00341 /** @defgroup SAI_Protocol_DataSize SAI protocol data size
00342   * @{
00343   */
00344 #define SAI_PROTOCOL_DATASIZE_16BIT         0U
00345 #define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1U
00346 #define SAI_PROTOCOL_DATASIZE_24BIT         2U
00347 #define SAI_PROTOCOL_DATASIZE_32BIT         3U
00348 /**
00349   * @}
00350   */
00351
00352 /** @defgroup SAI_Audio_Frequency SAI Audio Frequency
00353   * @{
00354   */
00355 #define SAI_AUDIO_FREQUENCY_192K          192000U
00356 #define SAI_AUDIO_FREQUENCY_96K           96000U
00357 #define SAI_AUDIO_FREQUENCY_48K           48000U
00358 #define SAI_AUDIO_FREQUENCY_44K           44100U
00359 #define SAI_AUDIO_FREQUENCY_32K           32000U
00360 #define SAI_AUDIO_FREQUENCY_22K           22050U
00361 #define SAI_AUDIO_FREQUENCY_16K           16000U
00362 #define SAI_AUDIO_FREQUENCY_11K           11025U
00363 #define SAI_AUDIO_FREQUENCY_8K            8000U
00364 #define SAI_AUDIO_FREQUENCY_MCKDIV        0U
00365 /**
00366   * @}
00367   */
00368
00369 /** @defgroup SAI_Block_Mck_OverSampling SAI Block Master Clock OverSampling
00370   * @{
00371   */
00372 #define SAI_MCK_OVERSAMPLING_DISABLE      0x00000000U
00373 #define SAI_MCK_OVERSAMPLING_ENABLE       SAI_xCR1_OSR
00374 /**
00375   * @}
00376   */
00377
00378 /** @defgroup SAI_PDM_ClockEnable SAI PDM Clock Enable
00379   * @{
00380   */
00381 #define SAI_PDM_CLOCK1_ENABLE     SAI_PDMCR_CKEN1
00382 #define SAI_PDM_CLOCK2_ENABLE     SAI_PDMCR_CKEN2
00383 /**
00384   * @}
00385   */
00386
00387 /** @defgroup SAI_Block_Mode SAI Block Mode
00388   * @{
00389   */
00390 #define SAI_MODEMASTER_TX         0x00000000U
00391 #define SAI_MODEMASTER_RX         SAI_xCR1_MODE_0
00392 #define SAI_MODESLAVE_TX          SAI_xCR1_MODE_1
00393 #define SAI_MODESLAVE_RX          (SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0)
00394
00395 /**
00396   * @}
00397   */
00398
00399 /** @defgroup SAI_Block_Protocol SAI Block Protocol
00400   * @{
00401   */
00402 #define SAI_FREE_PROTOCOL                 0x00000000U
00403 #define SAI_SPDIF_PROTOCOL                SAI_xCR1_PRTCFG_0
00404 #define SAI_AC97_PROTOCOL                 SAI_xCR1_PRTCFG_1
00405 /**
00406   * @}
00407   */
00408
00409 /** @defgroup SAI_Block_Data_Size SAI Block Data Size
00410   * @{
00411   */
00412 #define SAI_DATASIZE_8     SAI_xCR1_DS_1
00413 #define SAI_DATASIZE_10    (SAI_xCR1_DS_1 | SAI_xCR1_DS_0)
00414 #define SAI_DATASIZE_16    SAI_xCR1_DS_2
00415 #define SAI_DATASIZE_20    (SAI_xCR1_DS_2 | SAI_xCR1_DS_0)
00416 #define SAI_DATASIZE_24    (SAI_xCR1_DS_2 | SAI_xCR1_DS_1)
00417 #define SAI_DATASIZE_32    (SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0)
00418 /**
00419   * @}
00420   */
00421
00422 /** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission
00423   * @{
00424   */
00425 #define SAI_FIRSTBIT_MSB                  0x00000000U
00426 #define SAI_FIRSTBIT_LSB                  SAI_xCR1_LSBFIRST
00427 /**
00428   * @}
00429   */
00430
00431 /** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing
00432   * @{
00433   */
00434 #define SAI_CLOCKSTROBING_FALLINGEDGE     0U
00435 #define SAI_CLOCKSTROBING_RISINGEDGE      1U
00436 /**
00437   * @}
00438   */
00439
00440 /** @defgroup SAI_Block_Synchronization SAI Block Synchronization
00441   * @{
00442   */
00443 #define SAI_ASYNCHRONOUS                  0U /*!< Asynchronous */
00444 #define SAI_SYNCHRONOUS                   1U /*!< Synchronous with other block of same SAI */
00445 #define SAI_SYNCHRONOUS_EXT_SAI1          2U /*!< Synchronous with other SAI, SAI1 */
00446 #define SAI_SYNCHRONOUS_EXT_SAI2          3U /*!< Synchronous with other SAI, SAI2 */
00447 /**
00448   * @}
00449   */
00450
00451 /** @defgroup SAI_Block_Output_Drive SAI Block Output Drive
00452   * @{
00453   */
00454 #define SAI_OUTPUTDRIVE_DISABLE          0x00000000U
00455 #define SAI_OUTPUTDRIVE_ENABLE           SAI_xCR1_OUTDRIV
00456 /**
00457   * @}
00458   */
00459
00460 /** @defgroup SAI_Block_NoDivider SAI Block NoDivider
00461   * @{
00462   */
00463 #define SAI_MASTERDIVIDER_ENABLE         0x00000000U
00464 #define SAI_MASTERDIVIDER_DISABLE        SAI_xCR1_NODIV
00465 /**
00466   * @}
00467   */
00468
00469 /** @defgroup SAI_Block_FS_Definition SAI Block FS Definition
00470   * @{
00471   */
00472 #define SAI_FS_STARTFRAME                 0x00000000U
00473 #define SAI_FS_CHANNEL_IDENTIFICATION     SAI_xFRCR_FSDEF
00474 /**
00475   * @}
00476   */
00477
00478 /** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity
00479   * @{
00480   */
00481 #define SAI_FS_ACTIVE_LOW                  0x00000000U
00482 #define SAI_FS_ACTIVE_HIGH                 SAI_xFRCR_FSPOL
00483 /**
00484   * @}
00485   */
00486
00487 /** @defgroup SAI_Block_FS_Offset SAI Block FS Offset
00488   * @{
00489   */
00490 #define SAI_FS_FIRSTBIT                   0x00000000U
00491 #define SAI_FS_BEFOREFIRSTBIT             SAI_xFRCR_FSOFF
00492 /**
00493   * @}
00494   */
00495
00496 /** @defgroup SAI_Block_Slot_Size SAI Block Slot Size
00497   * @{
00498   */
00499 #define SAI_SLOTSIZE_DATASIZE             0x00000000U
00500 #define SAI_SLOTSIZE_16B                  SAI_xSLOTR_SLOTSZ_0
00501 #define SAI_SLOTSIZE_32B                  SAI_xSLOTR_SLOTSZ_1
00502 /**
00503   * @}
00504   */
00505
00506 /** @defgroup SAI_Block_Slot_Active SAI Block Slot Active
00507   * @{
00508   */
00509 #define SAI_SLOT_NOTACTIVE           0x00000000U
00510 #define SAI_SLOTACTIVE_0             0x00000001U
00511 #define SAI_SLOTACTIVE_1             0x00000002U
00512 #define SAI_SLOTACTIVE_2             0x00000004U
00513 #define SAI_SLOTACTIVE_3             0x00000008U
00514 #define SAI_SLOTACTIVE_4             0x00000010U
00515 #define SAI_SLOTACTIVE_5             0x00000020U
00516 #define SAI_SLOTACTIVE_6             0x00000040U
00517 #define SAI_SLOTACTIVE_7             0x00000080U
00518 #define SAI_SLOTACTIVE_8             0x00000100U
00519 #define SAI_SLOTACTIVE_9             0x00000200U
00520 #define SAI_SLOTACTIVE_10            0x00000400U
00521 #define SAI_SLOTACTIVE_11            0x00000800U
00522 #define SAI_SLOTACTIVE_12            0x00001000U
00523 #define SAI_SLOTACTIVE_13            0x00002000U
00524 #define SAI_SLOTACTIVE_14            0x00004000U
00525 #define SAI_SLOTACTIVE_15            0x00008000U
00526 #define SAI_SLOTACTIVE_ALL           0x0000FFFFU
00527 /**
00528   * @}
00529   */
00530
00531 /** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode
00532   * @{
00533   */
00534 #define SAI_STEREOMODE               0x00000000U
00535 #define SAI_MONOMODE                 SAI_xCR1_MONO
00536 /**
00537   * @}
00538   */
00539
00540 /** @defgroup SAI_TRIState_Management SAI TRIState Management
00541   * @{
00542   */
00543 #define SAI_OUTPUT_NOTRELEASED    0x00000000U
00544 #define SAI_OUTPUT_RELEASED       SAI_xCR2_TRIS
00545 /**
00546   * @}
00547   */
00548
00549 /** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold
00550   * @{
00551   */
00552 #define SAI_FIFOTHRESHOLD_EMPTY  0x00000000U
00553 #define SAI_FIFOTHRESHOLD_1QF    SAI_xCR2_FTH_0
00554 #define SAI_FIFOTHRESHOLD_HF     SAI_xCR2_FTH_1
00555 #define SAI_FIFOTHRESHOLD_3QF    (SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0)
00556 #define SAI_FIFOTHRESHOLD_FULL   SAI_xCR2_FTH_2
00557 /**
00558   * @}
00559   */
00560
00561 /** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode
00562   * @{
00563   */
00564 #define SAI_NOCOMPANDING                 0x00000000U
00565 #define SAI_ULAW_1CPL_COMPANDING         SAI_xCR2_COMP_1
00566 #define SAI_ALAW_1CPL_COMPANDING         (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0)
00567 #define SAI_ULAW_2CPL_COMPANDING         (SAI_xCR2_COMP_1 | SAI_xCR2_CPL)
00568 #define SAI_ALAW_2CPL_COMPANDING         (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL)
00569 /**
00570   * @}
00571   */
00572
00573 /** @defgroup SAI_Block_Mute_Value SAI Block Mute Value
00574   * @{
00575   */
00576 #define SAI_ZERO_VALUE                     0x00000000U
00577 #define SAI_LAST_SENT_VALUE                SAI_xCR2_MUTEVAL
00578 /**
00579   * @}
00580   */
00581
00582 /** @defgroup SAI_Block_Interrupts_Definition SAI Block Interrupts Definition
00583   * @{
00584   */
00585 #define SAI_IT_OVRUDR                     SAI_xIMR_OVRUDRIE
00586 #define SAI_IT_MUTEDET                    SAI_xIMR_MUTEDETIE
00587 #define SAI_IT_WCKCFG                     SAI_xIMR_WCKCFGIE
00588 #define SAI_IT_FREQ                       SAI_xIMR_FREQIE
00589 #define SAI_IT_CNRDY                      SAI_xIMR_CNRDYIE
00590 #define SAI_IT_AFSDET                     SAI_xIMR_AFSDETIE
00591 #define SAI_IT_LFSDET                     SAI_xIMR_LFSDETIE
00592 /**
00593   * @}
00594   */
00595
00596 /** @defgroup SAI_Block_Flags_Definition  SAI Block Flags Definition
00597   * @{
00598   */
00599 #define SAI_FLAG_OVRUDR                   SAI_xSR_OVRUDR
00600 #define SAI_FLAG_MUTEDET                  SAI_xSR_MUTEDET
00601 #define SAI_FLAG_WCKCFG                   SAI_xSR_WCKCFG
00602 #define SAI_FLAG_FREQ                     SAI_xSR_FREQ
00603 #define SAI_FLAG_CNRDY                    SAI_xSR_CNRDY
00604 #define SAI_FLAG_AFSDET                   SAI_xSR_AFSDET
00605 #define SAI_FLAG_LFSDET                   SAI_xSR_LFSDET
00606 /**
00607   * @}
00608   */
00609
00610 /** @defgroup SAI_Block_Fifo_Status_Level   SAI Block Fifo Status Level
00611   * @{
00612   */
00613 #define SAI_FIFOSTATUS_EMPTY              0x00000000U
00614 #define SAI_FIFOSTATUS_LESS1QUARTERFULL   0x00010000U
00615 #define SAI_FIFOSTATUS_1QUARTERFULL       0x00020000U
00616 #define SAI_FIFOSTATUS_HALFFULL           0x00030000U
00617 #define SAI_FIFOSTATUS_3QUARTERFULL       0x00040000U
00618 #define SAI_FIFOSTATUS_FULL               0x00050000U
00619 /**
00620   * @}
00621   */
00622
00623 /**
00624   * @}
00625   */
00626
00627 /* Exported macro ------------------------------------------------------------*/
00628 /** @defgroup SAI_Exported_Macros SAI Exported Macros
00629   * @brief macros to handle interrupts and specific configurations
00630   * @{
00631   */
00632
00633 /** @brief Reset SAI handle state.
00634   * @param  __HANDLE__ specifies the SAI Handle.
00635   * @retval None
00636   */
00637 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
00638 #define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) do{                                            \
00639                                                      (__HANDLE__)->State = HAL_SAI_STATE_RESET; \
00640                                                      (__HANDLE__)->MspInitCallback = NULL;      \
00641                                                      (__HANDLE__)->MspDeInitCallback = NULL;    \
00642                                                    } while(0)
00643 #else
00644 #define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)
00645 #endif
00646
00647 /** @brief  Enable the specified SAI interrupts.
00648   * @param  __HANDLE__ specifies the SAI Handle.
00649   * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
00650   *         This parameter can be one of the following values:
00651   *            @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
00652   *            @arg SAI_IT_MUTEDET: Mute detection interrupt enable
00653   *            @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
00654   *            @arg SAI_IT_FREQ: FIFO request interrupt enable
00655   *            @arg SAI_IT_CNRDY: Codec not ready interrupt enable
00656   *            @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
00657   *            @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
00658   * @retval None
00659   */
00660 #define __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
00661
00662 /** @brief  Disable the specified SAI interrupts.
00663   * @param  __HANDLE__ specifies the SAI Handle.
00664   * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
00665   *         This parameter can be one of the following values:
00666   *            @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
00667   *            @arg SAI_IT_MUTEDET: Mute detection interrupt enable
00668   *            @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
00669   *            @arg SAI_IT_FREQ: FIFO request interrupt enable
00670   *            @arg SAI_IT_CNRDY: Codec not ready interrupt enable
00671   *            @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
00672   *            @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
00673   * @retval None
00674   */
00675 #define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))
00676
00677 /** @brief  Check whether the specified SAI interrupt source is enabled or not.
00678   * @param  __HANDLE__ specifies the SAI Handle.
00679   * @param  __INTERRUPT__ specifies the SAI interrupt source to check.
00680   *         This parameter can be one of the following values:
00681   *            @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
00682   *            @arg SAI_IT_MUTEDET: Mute detection interrupt enable
00683   *            @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
00684   *            @arg SAI_IT_FREQ: FIFO request interrupt enable
00685   *            @arg SAI_IT_CNRDY: Codec not ready interrupt enable
00686   *            @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
00687   *            @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
00688   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
00689   */
00690 #define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00691
00692 /** @brief  Check whether the specified SAI flag is set or not.
00693   * @param  __HANDLE__ specifies the SAI Handle.
00694   * @param  __FLAG__ specifies the flag to check.
00695   *         This parameter can be one of the following values:
00696   *            @arg SAI_FLAG_OVRUDR: Overrun underrun flag.
00697   *            @arg SAI_FLAG_MUTEDET: Mute detection flag.
00698   *            @arg SAI_FLAG_WCKCFG: Wrong Clock Configuration flag.
00699   *            @arg SAI_FLAG_FREQ: FIFO request flag.
00700   *            @arg SAI_FLAG_CNRDY: Codec not ready flag.
00701   *            @arg SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag.
00702   *            @arg SAI_FLAG_LFSDET: Late frame synchronization detection flag.
00703   * @retval The new state of __FLAG__ (TRUE or FALSE).
00704   */
00705 #define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00706
00707 /** @brief  Clear the specified SAI pending flag.
00708   * @param  __HANDLE__ specifies the SAI Handle.
00709   * @param  __FLAG__ specifies the flag to check.
00710   *          This parameter can be any combination of the following values:
00711   *            @arg SAI_FLAG_OVRUDR: Clear Overrun underrun
00712   *            @arg SAI_FLAG_MUTEDET: Clear Mute detection
00713   *            @arg SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration
00714   *            @arg SAI_FLAG_FREQ: Clear FIFO request
00715   *            @arg SAI_FLAG_CNRDY: Clear Codec not ready
00716   *            @arg SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection
00717   *            @arg SAI_FLAG_LFSDET: Clear Late frame synchronization detection
00718   *
00719   * @retval None
00720   */
00721 #define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
00722
00723 /** @brief  Enable SAI.
00724   * @param  __HANDLE__ specifies the SAI Handle.
00725   * @retval None
00726   */
00727 #define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |=  SAI_xCR1_SAIEN)
00728
00729 /** @brief  Disable SAI.
00730   * @param  __HANDLE__ specifies the SAI Handle.
00731   * @retval None
00732   */
00733 #define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &=  ~SAI_xCR1_SAIEN)
00734
00735 /**
00736   * @}
00737   */
00738
00739 /* Include SAI HAL Extension module */
00740 #include "stm32wbxx_hal_sai_ex.h"
00741
00742 /* Exported functions --------------------------------------------------------*/
00743 /** @addtogroup SAI_Exported_Functions
00744   * @{
00745   */
00746
00747 /* Initialization/de-initialization functions  ********************************/
00748 /** @addtogroup SAI_Exported_Functions_Group1
00749   * @{
00750   */
00751 HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
00752 HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai);
00753 HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai);
00754 void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai);
00755 void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai);
00756
00757 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
00758 /* SAI callbacks register/unregister functions ********************************/
00759 HAL_StatusTypeDef HAL_SAI_RegisterCallback(SAI_HandleTypeDef        *hsai,
00760                                            HAL_SAI_CallbackIDTypeDef CallbackID,
00761                                            pSAI_CallbackTypeDef      pCallback);
00762 HAL_StatusTypeDef HAL_SAI_UnRegisterCallback(SAI_HandleTypeDef        *hsai,
00763                                              HAL_SAI_CallbackIDTypeDef CallbackID);
00764 #endif
00765 /**
00766   * @}
00767   */
00768
00769 /* I/O operation functions  ***************************************************/
00770 /** @addtogroup SAI_Exported_Functions_Group2
00771   * @{
00772   */
00773 /* Blocking mode: Polling */
00774 HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00775 HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00776
00777 /* Non-Blocking mode: Interrupt */
00778 HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
00779 HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
00780
00781 /* Non-Blocking mode: DMA */
00782 HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
00783 HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
00784 HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai);
00785 HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai);
00786 HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai);
00787
00788 /* Abort function */
00789 HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai);
00790
00791 /* Mute management */
00792 HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val);
00793 HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai);
00794 HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter);
00795 HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai);
00796
00797 /* SAI IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
00798 void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai);
00799 void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai);
00800 void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai);
00801 void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai);
00802 void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai);
00803 void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai);
00804 /**
00805   * @}
00806   */
00807
00808 /** @addtogroup SAI_Exported_Functions_Group3
00809   * @{
00810   */
00811 /* Peripheral State functions  ************************************************/
00812 HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai);
00813 uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
00814 /**
00815   * @}
00816   */
00817
00818 /**
00819   * @}
00820   */
00821
00822 /* Private macros ------------------------------------------------------------*/
00823 /** @defgroup SAI_Private_Macros SAI Private Macros
00824   * @{
00825   */
00826 #define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE) ||\
00827                                      ((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE) ||\
00828                                      ((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE))
00829
00830 #define IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL)   (((PROTOCOL) == SAI_I2S_STANDARD)     ||\
00831                                                ((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\
00832                                                ((PROTOCOL) == SAI_I2S_LSBJUSTIFIED) ||\
00833                                                ((PROTOCOL) == SAI_PCM_LONG)         ||\
00834                                                ((PROTOCOL) == SAI_PCM_SHORT))
00835
00836 #define IS_SAI_PROTOCOL_DATASIZE(DATASIZE)   (((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BIT)         ||\
00837                                               ((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) ||\
00838                                               ((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT)         ||\
00839                                               ((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT))
00840
00841 #define IS_SAI_AUDIO_FREQUENCY(AUDIO) (((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \
00842                                        ((AUDIO) == SAI_AUDIO_FREQUENCY_48K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \
00843                                        ((AUDIO) == SAI_AUDIO_FREQUENCY_32K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \
00844                                        ((AUDIO) == SAI_AUDIO_FREQUENCY_16K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \
00845                                        ((AUDIO) == SAI_AUDIO_FREQUENCY_8K)   || ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV))
00846
00847 #define IS_SAI_BLOCK_MCK_OVERSAMPLING(VALUE) (((VALUE) == SAI_MCK_OVERSAMPLING_DISABLE) || \
00848                                               ((VALUE) == SAI_MCK_OVERSAMPLING_ENABLE))
00849
00850 #define IS_SAI_PDM_MIC_PAIRS_NUMBER(VALUE)   ((1U <= (VALUE)) && ((VALUE) <= 3U))
00851
00852 #define IS_SAI_PDM_CLOCK_ENABLE(CLOCK) (((CLOCK) != 0U) && \
00853                                        (((CLOCK) & ~(SAI_PDM_CLOCK1_ENABLE | SAI_PDM_CLOCK2_ENABLE)) == 0U))
00854
00855 #define IS_SAI_BLOCK_MODE(MODE)  (((MODE) == SAI_MODEMASTER_TX) || \
00856                                   ((MODE) == SAI_MODEMASTER_RX) || \
00857                                   ((MODE) == SAI_MODESLAVE_TX)  || \
00858                                   ((MODE) == SAI_MODESLAVE_RX))
00859
00860 #define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL)  || \
00861                                          ((PROTOCOL) == SAI_AC97_PROTOCOL)  || \
00862                                          ((PROTOCOL) == SAI_SPDIF_PROTOCOL))
00863
00864 #define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DATASIZE_8)  || \
00865                                          ((DATASIZE) == SAI_DATASIZE_10) || \
00866                                          ((DATASIZE) == SAI_DATASIZE_16) || \
00867                                          ((DATASIZE) == SAI_DATASIZE_20) || \
00868                                          ((DATASIZE) == SAI_DATASIZE_24) || \
00869                                          ((DATASIZE) == SAI_DATASIZE_32))
00870
00871 #define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FIRSTBIT_MSB) || \
00872                                      ((BIT) == SAI_FIRSTBIT_LSB))
00873
00874 #define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \
00875                                             ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))
00876
00877 #define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS)         || \
00878                                        ((SYNCHRO) == SAI_SYNCHRONOUS)          || \
00879                                        ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) || \
00880                                        ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2))
00881
00882 #define IS_SAI_BLOCK_MCK_OUTPUT(VALUE) (((VALUE) == SAI_MCK_OUTPUT_ENABLE) || \
00883                                         ((VALUE) == SAI_MCK_OUTPUT_DISABLE))
00884
00885 #define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \
00886                                           ((DRIVE) == SAI_OUTPUTDRIVE_ENABLE))
00887
00888 #define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \
00889                                            ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE))
00890
00891 #define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63U)
00892
00893 #define IS_SAI_BLOCK_MUTE_VALUE(VALUE)    (((VALUE) == SAI_ZERO_VALUE)     || \
00894                                            ((VALUE) == SAI_LAST_SENT_VALUE))
00895
00896 #define IS_SAI_BLOCK_COMPANDING_MODE(MODE)    (((MODE) == SAI_NOCOMPANDING)         || \
00897                                                ((MODE) == SAI_ULAW_1CPL_COMPANDING) || \
00898                                                ((MODE) == SAI_ALAW_1CPL_COMPANDING) || \
00899                                                ((MODE) == SAI_ULAW_2CPL_COMPANDING) || \
00900                                                ((MODE) == SAI_ALAW_2CPL_COMPANDING))
00901
00902 #define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY)   || \
00903                                                 ((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF)     || \
00904                                                 ((THRESHOLD) == SAI_FIFOTHRESHOLD_HF)      || \
00905                                                 ((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF)     || \
00906                                                 ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL))
00907
00908 #define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\
00909                                                  ((STATE) == SAI_OUTPUT_RELEASED))
00910
00911 #define IS_SAI_MONO_STEREO_MODE(MODE) (((MODE) == SAI_MONOMODE) ||\
00912                                        ((MODE) == SAI_STEREOMODE))
00913
00914 #define IS_SAI_SLOT_ACTIVE(ACTIVE)  ((ACTIVE) <= SAI_SLOTACTIVE_ALL)
00915
00916 #define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1U <= (NUMBER)) && ((NUMBER) <= 16U))
00917
00918 #define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \
00919                                       ((SIZE) == SAI_SLOTSIZE_16B)      || \
00920                                       ((SIZE) == SAI_SLOTSIZE_32B))
00921
00922 #define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24U)
00923
00924 #define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \
00925                                         ((OFFSET) == SAI_FS_BEFOREFIRSTBIT))
00926
00927 #define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ACTIVE_LOW) || \
00928                                             ((POLARITY) == SAI_FS_ACTIVE_HIGH))
00929
00930 #define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \
00931                                                 ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION))
00932
00933 #define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 63U)
00934
00935 #define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8U <= (LENGTH)) && ((LENGTH) <= 256U))
00936
00937 #define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1U <= (LENGTH)) && ((LENGTH) <= 128U))
00938
00939 /**
00940   * @}
00941   */
00942
00943 /* Private functions ---------------------------------------------------------*/
00944 /** @defgroup SAI_Private_Functions SAI Private Functions
00945   * @{
00946   */
00947
00948 /**
00949   * @}
00950   */
00951
00952 /**
00953   * @}
00954   */
00955
00956 #endif /* SAI1 */
00957
00958 /**
00959   * @}
00960   */
00961
00962 #ifdef __cplusplus
00963 }
00964 #endif
00965
00966 #endif /* STM32WBxx_HAL_SAI_H */
00967
00968 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:35 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_sai_ex.c Source File

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stm32wbxx_hal_sai_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_sai_ex.c
00004   * @author  MCD Application Team
00005   * @brief   SAI Extended HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionality of the SAI Peripheral Controller:
00008   *           + Modify PDM microphone delays.
00009   *
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00014   * All rights reserved.</center></h2>
00015   *
00016   * This software component is licensed by ST under BSD 3-Clause license,
00017   * the "License"; You may not use this file except in compliance with the
00018   * License. You may obtain a copy of the License at:
00019   *                        opensource.org/licenses/BSD-3-Clause
00020   *
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32wbxx_hal.h"
00026
00027 /** @addtogroup STM32WBxx_HAL_Driver
00028   * @{
00029   */
00030 #ifdef HAL_SAI_MODULE_ENABLED
00031
00032 #if defined (SAI1)
00033
00034 /** @defgroup SAIEx SAIEx
00035   * @brief SAI Extended HAL module driver
00036   * @{
00037   */
00038
00039 /* Private types -------------------------------------------------------------*/
00040 /* Private variables ---------------------------------------------------------*/
00041 /* Private constants ---------------------------------------------------------*/
00042 /** @defgroup SAIEx_Private_Defines SAIEx Extended Private Defines
00043   * @{
00044   */
00045 #define SAI_PDM_DELAY_MASK          0x77U
00046 #define SAI_PDM_DELAY_OFFSET        8U
00047 #define SAI_PDM_RIGHT_DELAY_OFFSET  4U
00048 /**
00049   * @}
00050   */
00051
00052 /* Private macros ------------------------------------------------------------*/
00053 /* Private functions ---------------------------------------------------------*/
00054 /* Exported functions --------------------------------------------------------*/
00055 /** @defgroup SAIEx_Exported_Functions SAIEx Extended Exported Functions
00056   * @{
00057   */
00058
00059 /** @defgroup SAIEx_Exported_Functions_Group1 Peripheral Control functions
00060   * @brief    SAIEx control functions
00061   *
00062 @verbatim
00063  ===============================================================================
00064                  ##### Extended features functions #####
00065  ===============================================================================
00066     [..]  This section provides functions allowing to:
00067       (+) Modify PDM microphone delays
00068
00069 @endverbatim
00070   * @{
00071   */
00072
00073 /**
00074   * @brief  Configure PDM microphone delays.
00075   * @param  hsai SAI handle.
00076   * @param  pdmMicDelay Microphone delays configuration.
00077   * @retval HAL status
00078   */
00079 HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay)
00080 {
00081   HAL_StatusTypeDef status = HAL_OK;
00082   uint32_t offset;
00083
00084   /* Check that SAI sub-block is SAI1 sub-block A */
00085   if (hsai->Instance != SAI1_Block_A)
00086   {
00087     status = HAL_ERROR;
00088   }
00089   else
00090   {
00091     /* Check microphone delay parameters */
00092     assert_param(IS_SAI_PDM_MIC_PAIRS_NUMBER(pdmMicDelay->MicPair));
00093     assert_param(IS_SAI_PDM_MIC_DELAY(pdmMicDelay->LeftDelay));
00094     assert_param(IS_SAI_PDM_MIC_DELAY(pdmMicDelay->RightDelay));
00095
00096     /* Compute offset on PDMDLY register according mic pair number */
00097     offset = SAI_PDM_DELAY_OFFSET * (pdmMicDelay->MicPair - 1U);
00098
00099     /* Check SAI state and offset */
00100     if ((hsai->State != HAL_SAI_STATE_RESET) && (offset <= 24U))
00101     {
00102       /* Reset current delays for specified microphone */
00103       SAI1->PDMDLY &= ~(SAI_PDM_DELAY_MASK << offset);
00104
00105       /* Apply new microphone delays */
00106       SAI1->PDMDLY |= (((pdmMicDelay->RightDelay << SAI_PDM_RIGHT_DELAY_OFFSET) | pdmMicDelay->LeftDelay) << offset);
00107     }
00108     else
00109     {
00110       status = HAL_ERROR;
00111     }
00112   }
00113   return status;
00114 }
00115
00116 /**
00117   * @}
00118   */
00119
00120 /**
00121   * @}
00122   */
00123
00124 /**
00125   * @}
00126   */
00127
00128 #endif /* SAI1 */
00129
00130 #endif /* HAL_SAI_MODULE_ENABLED */
00131 /**
00132   * @}
00133   */
00134
00135 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:35 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_sai_ex.h Source File

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stm32wbxx_hal_sai_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_sai_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SAI HAL extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_SAI_EX_H
00022 #define STM32WBxx_HAL_SAI_EX_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 /** @addtogroup STM32WBxx_HAL_Driver
00032   * @{
00033   */
00034
00035 #if defined (SAI1)
00036
00037 /** @addtogroup SAIEx
00038   * @{
00039   */
00040
00041 /* Exported types ------------------------------------------------------------*/
00042 /** @defgroup SAIEx_Exported_Types SAIEx Exported Types
00043   * @{
00044   */
00045
00046 /**
00047   * @brief  PDM microphone delay structure definition
00048   */
00049 typedef struct
00050 {
00051   uint32_t MicPair;     /*!< Specifies which pair of microphones is selected.
00052                              This parameter must be a number between Min_Data = 1 and Max_Data = 3. */
00053
00054   uint32_t LeftDelay;   /*!< Specifies the delay in PDM clock unit to apply on left microphone.
00055                              This parameter must be a number between Min_Data = 0 and Max_Data = 7. */
00056
00057   uint32_t RightDelay;  /*!< Specifies the delay in PDM clock unit to apply on right microphone.
00058                              This parameter must be a number between Min_Data = 0 and Max_Data = 7. */
00059 } SAIEx_PdmMicDelayParamTypeDef;
00060
00061 /**
00062   * @}
00063   */
00064
00065 /* Exported constants --------------------------------------------------------*/
00066 /* Exported macros -----------------------------------------------------------*/
00067 /* Exported functions --------------------------------------------------------*/
00068 /** @addtogroup SAIEx_Exported_Functions SAIEx Extended Exported Functions
00069   * @{
00070   */
00071
00072 /** @addtogroup SAIEx_Exported_Functions_Group1 Peripheral Control functions
00073   * @{
00074   */
00075 HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay);
00076 /**
00077   * @}
00078   */
00079
00080 /**
00081   * @}
00082   */
00083
00084 /* Private macros ------------------------------------------------------------*/
00085 /** @addtogroup SAIEx_Private_Macros SAIEx Extended Private Macros
00086   * @{
00087   */
00088 #define IS_SAI_PDM_MIC_DELAY(VALUE)   ((VALUE) <= 7U)
00089 /**
00090   * @}
00091   */
00092
00093 /**
00094   * @}
00095   */
00096
00097 #endif /* SAI1 */
00098
00099 /**
00100   * @}
00101   */
00102 #ifdef __cplusplus
00103 }
00104 #endif
00105
00106 #endif /* STM32WBxx_HAL_SAI_EX_H */
00107
00108 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:35 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_smartcard.c Source File

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stm32wbxx_hal_smartcard.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_smartcard.c
00004   * @author  MCD Application Team
00005   * @brief   SMARTCARD HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the SMARTCARD peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral Control functions
00011   *           + Peripheral State and Error functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                         ##### How to use this driver #####
00016   ==============================================================================
00017   [..]
00018     The SMARTCARD HAL driver can be used as follows:
00019
00020     (#) Declare a SMARTCARD_HandleTypeDef handle structure (eg. SMARTCARD_HandleTypeDef hsmartcard).
00021     (#) Associate a USART to the SMARTCARD handle hsmartcard.
00022     (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
00023         (++) Enable the USARTx interface clock.
00024         (++) USART pins configuration:
00025              (+++) Enable the clock for the USART GPIOs.
00026              (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
00027         (++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
00028              and HAL_SMARTCARD_Receive_IT() APIs):
00029              (+++) Configure the USARTx interrupt priority.
00030              (+++) Enable the NVIC USART IRQ handle.
00031         (++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
00032              and HAL_SMARTCARD_Receive_DMA() APIs):
00033              (+++) Declare a DMA handle structure for the Tx/Rx channel.
00034              (+++) Enable the DMAx interface clock.
00035              (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00036              (+++) Configure the DMA Tx/Rx channel.
00037              (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
00038              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
00039
00040     (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
00041         the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
00042         error enabling or disabling in the hsmartcard handle Init structure.
00043
00044     (#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...)
00045         in the hsmartcard handle AdvancedInit structure.
00046
00047     (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
00048         (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00049              by calling the customized HAL_SMARTCARD_MspInit() API.
00050         [..]
00051         (@) The specific SMARTCARD interrupts (Transmission complete interrupt,
00052              RXNE interrupt and Error Interrupts) will be managed using the macros
00053              __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
00054
00055     [..]
00056     [..] Three operation modes are available within this driver :
00057
00058      *** Polling mode IO operation ***
00059      =================================
00060      [..]
00061        (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
00062        (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()
00063
00064      *** Interrupt mode IO operation ***
00065      ===================================
00066      [..]
00067        (+) Send an amount of data in non-blocking mode using HAL_SMARTCARD_Transmit_IT()
00068        (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
00069             add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
00070        (+) Receive an amount of data in non-blocking mode using HAL_SMARTCARD_Receive_IT()
00071        (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
00072             add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
00073        (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
00074             add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
00075
00076      *** DMA mode IO operation ***
00077      ==============================
00078      [..]
00079        (+) Send an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
00080        (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
00081             add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
00082        (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
00083        (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
00084             add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
00085        (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
00086             add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
00087
00088      *** SMARTCARD HAL driver macros list ***
00089      ========================================
00090      [..]
00091        Below the list of most used macros in SMARTCARD HAL driver.
00092
00093        (+) __HAL_SMARTCARD_GET_FLAG : Check whether or not the specified SMARTCARD flag is set
00094        (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
00095        (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
00096        (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
00097        (+) __HAL_SMARTCARD_GET_IT_SOURCE: Check whether or not the specified SMARTCARD interrupt is enabled
00098
00099      [..]
00100        (@) You can refer to the SMARTCARD HAL driver header file for more useful macros
00101
00102     ##### Callback registration #####
00103     ==================================
00104
00105     [..]
00106     The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS when set to 1
00107     allows the user to configure dynamically the driver callbacks.
00108
00109     [..]
00110     Use Function @ref HAL_SMARTCARD_RegisterCallback() to register a user callback.
00111     Function @ref HAL_SMARTCARD_RegisterCallback() allows to register following callbacks:
00112     (+) TxCpltCallback            : Tx Complete Callback.
00113     (+) RxCpltCallback            : Rx Complete Callback.
00114     (+) ErrorCallback             : Error Callback.
00115     (+) AbortCpltCallback         : Abort Complete Callback.
00116     (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
00117     (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
00118     (+) RxFifoFullCallback        : Rx Fifo Full Callback.
00119     (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
00120     (+) MspInitCallback           : SMARTCARD MspInit.
00121     (+) MspDeInitCallback         : SMARTCARD MspDeInit.
00122     This function takes as parameters the HAL peripheral handle, the Callback ID
00123     and a pointer to the user callback function.
00124
00125     [..]
00126     Use function @ref HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default
00127     weak (surcharged) function.
00128     @ref HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00129     and the Callback ID.
00130     This function allows to reset following callbacks:
00131     (+) TxCpltCallback            : Tx Complete Callback.
00132     (+) RxCpltCallback            : Rx Complete Callback.
00133     (+) ErrorCallback             : Error Callback.
00134     (+) AbortCpltCallback         : Abort Complete Callback.
00135     (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
00136     (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
00137     (+) RxFifoFullCallback        : Rx Fifo Full Callback.
00138     (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
00139     (+) MspInitCallback           : SMARTCARD MspInit.
00140     (+) MspDeInitCallback         : SMARTCARD MspDeInit.
00141
00142     [..]
00143     By default, after the @ref HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET
00144     all callbacks are set to the corresponding weak (surcharged) functions:
00145     examples @ref HAL_SMARTCARD_TxCpltCallback(), @ref HAL_SMARTCARD_RxCpltCallback().
00146     Exception done for MspInit and MspDeInit functions that are respectively
00147     reset to the legacy weak (surcharged) functions in the @ref HAL_SMARTCARD_Init()
00148     and @ref HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand).
00149     If not, MspInit or MspDeInit are not null, the @ref HAL_SMARTCARD_Init() and @ref HAL_SMARTCARD_DeInit()
00150     keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
00151
00152     [..]
00153     Callbacks can be registered/unregistered in HAL_SMARTCARD_STATE_READY state only.
00154     Exception done MspInit/MspDeInit that can be registered/unregistered
00155     in HAL_SMARTCARD_STATE_READY or HAL_SMARTCARD_STATE_RESET state, thus registered (user)
00156     MspInit/DeInit callbacks can be used during the Init/DeInit.
00157     In that case first register the MspInit/MspDeInit user callbacks
00158     using @ref HAL_SMARTCARD_RegisterCallback() before calling @ref HAL_SMARTCARD_DeInit()
00159     or @ref HAL_SMARTCARD_Init() function.
00160
00161     [..]
00162     When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or
00163     not defined, the callback registration feature is not available
00164     and weak (surcharged) callbacks are used.
00165
00166
00167   @endverbatim
00168   ******************************************************************************
00169   * @attention
00170   *
00171   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00172   * All rights reserved.</center></h2>
00173   *
00174   * This software component is licensed by ST under BSD 3-Clause license,
00175   * the "License"; You may not use this file except in compliance with the
00176   * License. You may obtain a copy of the License at:
00177   *                        opensource.org/licenses/BSD-3-Clause
00178   *
00179   ******************************************************************************
00180   */
00181
00182 /* Includes ------------------------------------------------------------------*/
00183 #include "stm32wbxx_hal.h"
00184
00185 /** @addtogroup STM32WBxx_HAL_Driver
00186   * @{
00187   */
00188
00189 /** @defgroup SMARTCARD SMARTCARD
00190   * @brief HAL SMARTCARD module driver
00191   * @{
00192   */
00193
00194 #ifdef HAL_SMARTCARD_MODULE_ENABLED
00195
00196 /* Private typedef -----------------------------------------------------------*/
00197 /* Private define ------------------------------------------------------------*/
00198 /** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
00199  * @{
00200  */
00201 #define SMARTCARD_TEACK_REACK_TIMEOUT               1000U      /*!< SMARTCARD TX or RX enable acknowledge time-out value  */
00202
00203 #define USART_CR1_FIELDS      ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS   | \
00204                                           USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \
00205                                           USART_CR1_FIFOEN ))                                         /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
00206
00207 #define USART_CR2_CLK_FIELDS  ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | \
00208                                           USART_CR2_LBCL))                                            /*!< SMARTCARD clock-related USART CR2 fields of parameters */
00209
00210 #define USART_CR2_FIELDS      ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | USART_CR2_STOP))   /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */
00211
00212 #define USART_CR3_FIELDS      ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT | \
00213                                           USART_CR3_TXFTCFG | USART_CR3_RXFTCFG ))                    /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */
00214
00215 #define USART_BRR_MIN    0x10U        /*!< USART BRR minimum authorized value */
00216
00217 #define USART_BRR_MAX    0x0000FFFFU  /*!< USART BRR maximum authorized value */
00218 /**
00219   * @}
00220   */
00221
00222 /* Private macros ------------------------------------------------------------*/
00223 /* Private variables ---------------------------------------------------------*/
00224 /* Private function prototypes -----------------------------------------------*/
00225 /** @addtogroup SMARTCARD_Private_Functions
00226   * @{
00227   */
00228 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
00229 void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard);
00230 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
00231 static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard);
00232 static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard);
00233 static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard);
00234 static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
00235 static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
00236 static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
00237 static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00238 static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00239 static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
00240 static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma);
00241 static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
00242 static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
00243 static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00244 static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00245 static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard);
00246 static void SMARTCARD_TxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard);
00247 static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
00248 static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard);
00249 static void SMARTCARD_RxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard);
00250 /**
00251   * @}
00252   */
00253
00254 /* Exported functions --------------------------------------------------------*/
00255
00256 /** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
00257   * @{
00258   */
00259
00260 /** @defgroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions
00261   * @brief    Initialization and Configuration functions
00262   *
00263 @verbatim
00264   ==============================================================================
00265               ##### Initialization and Configuration functions #####
00266   ==============================================================================
00267   [..]
00268   This subsection provides a set of functions allowing to initialize the USARTx
00269   associated to the SmartCard.
00270   (+) These parameters can be configured:
00271       (++) Baud Rate
00272       (++) Parity: parity should be enabled, frame Length is fixed to 8 bits plus parity
00273       (++) Receiver/transmitter modes
00274       (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)
00275       (++) Prescaler value
00276       (++) Guard bit time
00277       (++) NACK enabling or disabling on transmission error
00278
00279   (+) The following advanced features can be configured as well:
00280       (++) TX and/or RX pin level inversion
00281       (++) data logical level inversion
00282       (++) RX and TX pins swap
00283       (++) RX overrun detection disabling
00284       (++) DMA disabling on RX error
00285       (++) MSB first on communication line
00286       (++) Time out enabling (and if activated, timeout value)
00287       (++) Block length
00288       (++) Auto-retry counter
00289   [..]
00290   The HAL_SMARTCARD_Init() API follows the USART synchronous configuration procedures
00291   (details for the procedures are available in reference manual).
00292
00293 @endverbatim
00294
00295   The USART frame format is given in the following table:
00296
00297     Table 1. USART frame format.
00298     +---------------------------------------------------------------+
00299     | M1M0 bits |  PCE bit  |            USART frame                |
00300     |-----------------------|---------------------------------------|
00301     |     01    |    1      |    | SB | 8 bit data | PB | STB |     |
00302     +---------------------------------------------------------------+
00303
00304
00305   * @{
00306   */
00307
00308 /**
00309   * @brief  Initialize the SMARTCARD mode according to the specified
00310   *         parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
00311   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00312   *                    the configuration information for the specified SMARTCARD module.
00313   * @retval HAL status
00314   */
00315 HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard)
00316 {
00317   /* Check the SMARTCARD handle allocation */
00318   if (hsmartcard == NULL)
00319   {
00320     return HAL_ERROR;
00321   }
00322
00323   /* Check the USART associated to the SMARTCARD handle */
00324   assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
00325
00326   if (hsmartcard->gState == HAL_SMARTCARD_STATE_RESET)
00327   {
00328     /* Allocate lock resource and initialize it */
00329     hsmartcard->Lock = HAL_UNLOCKED;
00330
00331 #if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
00332     SMARTCARD_InitCallbacksToDefault(hsmartcard);
00333
00334     if (hsmartcard->MspInitCallback == NULL)
00335     {
00336       hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit;
00337     }
00338
00339     /* Init the low level hardware */
00340     hsmartcard->MspInitCallback(hsmartcard);
00341 #else
00342     /* Init the low level hardware : GPIO, CLOCK */
00343     HAL_SMARTCARD_MspInit(hsmartcard);
00344 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
00345   }
00346
00347   hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00348
00349   /* Disable the Peripheral to set smartcard mode */
00350   CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00351
00352   /* In SmartCard mode, the following bits must be kept cleared:
00353   - LINEN in the USART_CR2 register,
00354   - HDSEL and IREN  bits in the USART_CR3 register.*/
00355   CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_LINEN);
00356   CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN));
00357
00358   /* set the USART in SMARTCARD mode */
00359   SET_BIT(hsmartcard->Instance->CR3, USART_CR3_SCEN);
00360
00361   /* Set the SMARTCARD Communication parameters */
00362   if (SMARTCARD_SetConfig(hsmartcard) == HAL_ERROR)
00363   {
00364     return HAL_ERROR;
00365   }
00366
00367   /* Set the SMARTCARD transmission completion indication */
00368   SMARTCARD_TRANSMISSION_COMPLETION_SETTING(hsmartcard);
00369
00370   if (hsmartcard->AdvancedInit.AdvFeatureInit != SMARTCARD_ADVFEATURE_NO_INIT)
00371   {
00372     SMARTCARD_AdvFeatureConfig(hsmartcard);
00373   }
00374
00375   /* Enable the Peripheral */
00376   SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00377
00378   /* TEACK and/or REACK to check before moving hsmartcard->gState and hsmartcard->RxState to Ready */
00379   return (SMARTCARD_CheckIdleState(hsmartcard));
00380 }
00381
00382 /**
00383   * @brief  DeInitialize the SMARTCARD peripheral.
00384   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00385   *                    the configuration information for the specified SMARTCARD module.
00386   * @retval HAL status
00387   */
00388 HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard)
00389 {
00390   /* Check the SMARTCARD handle allocation */
00391   if (hsmartcard == NULL)
00392   {
00393     return HAL_ERROR;
00394   }
00395
00396   /* Check the USART/UART associated to the SMARTCARD handle */
00397   assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
00398
00399   hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00400
00401   /* Disable the Peripheral */
00402   CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00403
00404   WRITE_REG(hsmartcard->Instance->CR1, 0x0U);
00405   WRITE_REG(hsmartcard->Instance->CR2, 0x0U);
00406   WRITE_REG(hsmartcard->Instance->CR3, 0x0U);
00407   WRITE_REG(hsmartcard->Instance->RTOR, 0x0U);
00408   WRITE_REG(hsmartcard->Instance->GTPR, 0x0U);
00409
00410   /* DeInit the low level hardware */
00411 #if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
00412   if (hsmartcard->MspDeInitCallback == NULL)
00413   {
00414     hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit;
00415   }
00416   /* DeInit the low level hardware */
00417   hsmartcard->MspDeInitCallback(hsmartcard);
00418 #else
00419   HAL_SMARTCARD_MspDeInit(hsmartcard);
00420 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
00421
00422   hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00423   hsmartcard->gState    = HAL_SMARTCARD_STATE_RESET;
00424   hsmartcard->RxState   = HAL_SMARTCARD_STATE_RESET;
00425
00426   /* Process Unlock */
00427   __HAL_UNLOCK(hsmartcard);
00428
00429   return HAL_OK;
00430 }
00431
00432 /**
00433   * @brief  Initialize the SMARTCARD MSP.
00434   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00435   *                    the configuration information for the specified SMARTCARD module.
00436   * @retval None
00437   */
00438 __weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard)
00439 {
00440   /* Prevent unused argument(s) compilation warning */
00441   UNUSED(hsmartcard);
00442
00443   /* NOTE : This function should not be modified, when the callback is needed,
00444             the HAL_SMARTCARD_MspInit can be implemented in the user file
00445    */
00446 }
00447
00448 /**
00449   * @brief  DeInitialize the SMARTCARD MSP.
00450   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00451   *                    the configuration information for the specified SMARTCARD module.
00452   * @retval None
00453   */
00454 __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard)
00455 {
00456   /* Prevent unused argument(s) compilation warning */
00457   UNUSED(hsmartcard);
00458
00459   /* NOTE : This function should not be modified, when the callback is needed,
00460             the HAL_SMARTCARD_MspDeInit can be implemented in the user file
00461    */
00462 }
00463
00464 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
00465 /**
00466   * @brief  Register a User SMARTCARD Callback
00467   *         To be used instead of the weak predefined callback
00468   * @param  hsmartcard smartcard handle
00469   * @param  CallbackID ID of the callback to be registered
00470   *         This parameter can be one of the following values:
00471   *           @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID
00472   *           @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID
00473   *           @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID
00474   *           @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
00475   *           @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
00476   *           @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
00477   *           @arg @ref HAL_SMARTCARD_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
00478   *           @arg @ref HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
00479   *           @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID
00480   *           @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
00481   * @param  pCallback pointer to the Callback function
00482   * @retval HAL status
00483   */
00484 HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback)
00485 {
00486   HAL_StatusTypeDef status = HAL_OK;
00487
00488   if (pCallback == NULL)
00489   {
00490     /* Update the error code */
00491     hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
00492
00493     return HAL_ERROR;
00494   }
00495   /* Process locked */
00496   __HAL_LOCK(hsmartcard);
00497
00498   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
00499   {
00500     switch (CallbackID)
00501     {
00502
00503       case HAL_SMARTCARD_TX_COMPLETE_CB_ID :
00504         hsmartcard->TxCpltCallback = pCallback;
00505         break;
00506
00507       case HAL_SMARTCARD_RX_COMPLETE_CB_ID :
00508         hsmartcard->RxCpltCallback = pCallback;
00509         break;
00510
00511       case HAL_SMARTCARD_ERROR_CB_ID :
00512         hsmartcard->ErrorCallback = pCallback;
00513         break;
00514
00515       case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID :
00516         hsmartcard->AbortCpltCallback = pCallback;
00517         break;
00518
00519       case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID :
00520         hsmartcard->AbortTransmitCpltCallback = pCallback;
00521         break;
00522
00523       case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID :
00524         hsmartcard->AbortReceiveCpltCallback = pCallback;
00525         break;
00526
00527       case HAL_SMARTCARD_RX_FIFO_FULL_CB_ID :
00528         hsmartcard->RxFifoFullCallback = pCallback;
00529         break;
00530
00531       case HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID :
00532         hsmartcard->TxFifoEmptyCallback = pCallback;
00533         break;
00534
00535       case HAL_SMARTCARD_MSPINIT_CB_ID :
00536         hsmartcard->MspInitCallback = pCallback;
00537         break;
00538
00539       case HAL_SMARTCARD_MSPDEINIT_CB_ID :
00540         hsmartcard->MspDeInitCallback = pCallback;
00541         break;
00542
00543       default :
00544         /* Update the error code */
00545         hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
00546
00547         /* Return error status */
00548         status =  HAL_ERROR;
00549         break;
00550     }
00551   }
00552   else if (hsmartcard->gState == HAL_SMARTCARD_STATE_RESET)
00553   {
00554     switch (CallbackID)
00555     {
00556       case HAL_SMARTCARD_MSPINIT_CB_ID :
00557         hsmartcard->MspInitCallback = pCallback;
00558         break;
00559
00560       case HAL_SMARTCARD_MSPDEINIT_CB_ID :
00561         hsmartcard->MspDeInitCallback = pCallback;
00562         break;
00563
00564       default :
00565         /* Update the error code */
00566         hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
00567
00568         /* Return error status */
00569         status =  HAL_ERROR;
00570         break;
00571     }
00572   }
00573   else
00574   {
00575     /* Update the error code */
00576     hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
00577
00578     /* Return error status */
00579     status =  HAL_ERROR;
00580   }
00581
00582   /* Release Lock */
00583   __HAL_UNLOCK(hsmartcard);
00584
00585   return status;
00586 }
00587
00588 /**
00589   * @brief  Unregister an SMARTCARD callback
00590   *         SMARTCARD callback is redirected to the weak predefined callback
00591   * @param  hsmartcard smartcard handle
00592   * @param  CallbackID ID of the callback to be unregistered
00593   *         This parameter can be one of the following values:
00594   *           @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID
00595   *           @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID
00596   *           @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID
00597   *           @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
00598   *           @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
00599   *           @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
00600   *           @arg @ref HAL_SMARTCARD_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
00601   *           @arg @ref HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
00602   *           @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID
00603   *           @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
00604   * @retval HAL status
00605   */
00606 HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID)
00607 {
00608   HAL_StatusTypeDef status = HAL_OK;
00609
00610   /* Process locked */
00611   __HAL_LOCK(hsmartcard);
00612
00613   if (HAL_SMARTCARD_STATE_READY == hsmartcard->gState)
00614   {
00615     switch (CallbackID)
00616     {
00617       case HAL_SMARTCARD_TX_COMPLETE_CB_ID :
00618         hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback;                       /* Legacy weak TxCpltCallback            */
00619         break;
00620
00621       case HAL_SMARTCARD_RX_COMPLETE_CB_ID :
00622         hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback;                       /* Legacy weak RxCpltCallback            */
00623         break;
00624
00625       case HAL_SMARTCARD_ERROR_CB_ID :
00626         hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback;                         /* Legacy weak ErrorCallback             */
00627         break;
00628
00629       case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID :
00630         hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback;                 /* Legacy weak AbortCpltCallback         */
00631         break;
00632
00633       case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID :
00634         hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
00635         break;
00636
00637       case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID :
00638         hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback;   /* Legacy weak AbortReceiveCpltCallback  */
00639         break;
00640
00641       case HAL_SMARTCARD_RX_FIFO_FULL_CB_ID :
00642         hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback;             /* Legacy weak RxFifoFullCallback        */
00643         break;
00644
00645       case HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID :
00646         hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback;           /* Legacy weak TxFifoEmptyCallback       */
00647         break;
00648
00649       case HAL_SMARTCARD_MSPINIT_CB_ID :
00650         hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit;                             /* Legacy weak MspInitCallback           */
00651         break;
00652
00653       case HAL_SMARTCARD_MSPDEINIT_CB_ID :
00654         hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit;                         /* Legacy weak MspDeInitCallback         */
00655         break;
00656
00657       default :
00658         /* Update the error code */
00659         hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
00660
00661         /* Return error status */
00662         status =  HAL_ERROR;
00663         break;
00664     }
00665   }
00666   else if (HAL_SMARTCARD_STATE_RESET == hsmartcard->gState)
00667   {
00668     switch (CallbackID)
00669     {
00670       case HAL_SMARTCARD_MSPINIT_CB_ID :
00671         hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit;
00672         break;
00673
00674       case HAL_SMARTCARD_MSPDEINIT_CB_ID :
00675         hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit;
00676         break;
00677
00678       default :
00679         /* Update the error code */
00680         hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
00681
00682         /* Return error status */
00683         status =  HAL_ERROR;
00684         break;
00685     }
00686   }
00687   else
00688   {
00689     /* Update the error code */
00690     hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
00691
00692     /* Return error status */
00693     status =  HAL_ERROR;
00694   }
00695
00696   /* Release Lock */
00697   __HAL_UNLOCK(hsmartcard);
00698
00699   return status;
00700 }
00701 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
00702
00703 /**
00704   * @}
00705   */
00706
00707 /** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions
00708   * @brief    SMARTCARD Transmit and Receive functions
00709   *
00710 @verbatim
00711   ==============================================================================
00712                          ##### IO operation functions #####
00713   ==============================================================================
00714   [..]
00715     This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
00716
00717   [..]
00718     Smartcard is a single wire half duplex communication protocol.
00719     The Smartcard interface is designed to support asynchronous protocol Smartcards as
00720     defined in the ISO 7816-3 standard. The USART should be configured as:
00721     (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
00722     (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
00723
00724   [..]
00725     (+) There are two modes of transfer:
00726         (++) Blocking mode: The communication is performed in polling mode.
00727              The HAL status of all data processing is returned by the same function
00728              after finishing transfer.
00729         (++) Non-Blocking mode: The communication is performed using Interrupts
00730              or DMA, the relevant API's return the HAL status.
00731              The end of the data processing will be indicated through the
00732              dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
00733              using DMA mode.
00734         (++) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
00735              will be executed respectively at the end of the Transmit or Receive process
00736              The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
00737              error is detected.
00738
00739     (+) Blocking mode APIs are :
00740         (++) HAL_SMARTCARD_Transmit()
00741         (++) HAL_SMARTCARD_Receive()
00742
00743     (+) Non Blocking mode APIs with Interrupt are :
00744         (++) HAL_SMARTCARD_Transmit_IT()
00745         (++) HAL_SMARTCARD_Receive_IT()
00746         (++) HAL_SMARTCARD_IRQHandler()
00747
00748     (+) Non Blocking mode functions with DMA are :
00749         (++) HAL_SMARTCARD_Transmit_DMA()
00750         (++) HAL_SMARTCARD_Receive_DMA()
00751
00752     (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
00753         (++) HAL_SMARTCARD_TxCpltCallback()
00754         (++) HAL_SMARTCARD_RxCpltCallback()
00755         (++) HAL_SMARTCARD_ErrorCallback()
00756
00757     (#) Non-Blocking mode transfers could be aborted using Abort API's :
00758         (+) HAL_SMARTCARD_Abort()
00759         (+) HAL_SMARTCARD_AbortTransmit()
00760         (+) HAL_SMARTCARD_AbortReceive()
00761         (+) HAL_SMARTCARD_Abort_IT()
00762         (+) HAL_SMARTCARD_AbortTransmit_IT()
00763         (+) HAL_SMARTCARD_AbortReceive_IT()
00764
00765     (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
00766         (+) HAL_SMARTCARD_AbortCpltCallback()
00767         (+) HAL_SMARTCARD_AbortTransmitCpltCallback()
00768         (+) HAL_SMARTCARD_AbortReceiveCpltCallback()
00769
00770     (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
00771         Errors are handled as follows :
00772        (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
00773            to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
00774            Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
00775            and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
00776            If user wants to abort it, Abort services should be called by user.
00777        (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
00778            This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
00779            Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.
00780
00781 @endverbatim
00782   * @{
00783   */
00784
00785 /**
00786   * @brief  Send an amount of data in blocking mode.
00787   * @note   When FIFO mode is enabled, writing a data in the TDR register adds one
00788   *         data to the TXFIFO. Write operations to the TDR register are performed
00789   *         when TXFNF flag is set. From hardware perspective, TXFNF flag and
00790   *         TXE are mapped on the same bit-field.
00791   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00792   *                    the configuration information for the specified SMARTCARD module.
00793   * @param  pData pointer to data buffer.
00794   * @param  Size amount of data to be sent.
00795   * @param  Timeout  Timeout duration.
00796   * @retval HAL status
00797   */
00798 HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00799 {
00800   uint32_t tickstart;
00801   uint8_t  *ptmpdata = pData;
00802
00803   /* Check that a Tx process is not already ongoing */
00804   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
00805   {
00806     if ((ptmpdata == NULL) || (Size == 0U))
00807     {
00808       return  HAL_ERROR;
00809     }
00810
00811     /* Process Locked */
00812     __HAL_LOCK(hsmartcard);
00813
00814     hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
00815
00816     /* Init tickstart for timeout management */
00817     tickstart = HAL_GetTick();
00818
00819     /* Disable the Peripheral first to update mode for TX master */
00820     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00821
00822     /* Disable Rx, enable Tx */
00823     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
00824     SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
00825     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
00826
00827     /* Enable the Peripheral */
00828     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00829
00830     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00831     hsmartcard->TxXferSize = Size;
00832     hsmartcard->TxXferCount = Size;
00833
00834     while (hsmartcard->TxXferCount > 0U)
00835     {
00836       hsmartcard->TxXferCount--;
00837       if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
00838       {
00839         return HAL_TIMEOUT;
00840       }
00841       hsmartcard->Instance->TDR = (uint8_t)(*ptmpdata & 0xFFU);
00842       ptmpdata++;
00843     }
00844     if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart, Timeout) != HAL_OK)
00845     {
00846       return HAL_TIMEOUT;
00847     }
00848     /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */
00849     if (hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
00850     {
00851       /* Disable the Peripheral first to update modes */
00852       CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00853       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
00854       /* Enable the Peripheral */
00855       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00856     }
00857
00858     /* At end of Tx process, restore hsmartcard->gState to Ready */
00859     hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00860
00861     /* Process Unlocked */
00862     __HAL_UNLOCK(hsmartcard);
00863
00864     return HAL_OK;
00865   }
00866   else
00867   {
00868     return HAL_BUSY;
00869   }
00870 }
00871
00872 /**
00873   * @brief  Receive an amount of data in blocking mode.
00874   * @note   When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
00875   *         is not empty. Read operations from the RDR register are performed when
00876   *         RXFNE flag is set. From hardware perspective, RXFNE flag and
00877   *         RXNE are mapped on the same bit-field.
00878   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00879   *                    the configuration information for the specified SMARTCARD module.
00880   * @param  pData pointer to data buffer.
00881   * @param  Size amount of data to be received.
00882   * @param  Timeout Timeout duration.
00883   * @retval HAL status
00884   */
00885 HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00886 {
00887   uint32_t tickstart;
00888   uint8_t  *ptmpdata = pData;
00889
00890   /* Check that a Rx process is not already ongoing */
00891   if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
00892   {
00893     if ((ptmpdata == NULL) || (Size == 0U))
00894     {
00895       return  HAL_ERROR;
00896     }
00897
00898     /* Process Locked */
00899     __HAL_LOCK(hsmartcard);
00900
00901     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00902     hsmartcard->RxState   = HAL_SMARTCARD_STATE_BUSY_RX;
00903
00904     /* Init tickstart for timeout management */
00905     tickstart = HAL_GetTick();
00906
00907     hsmartcard->RxXferSize = Size;
00908     hsmartcard->RxXferCount = Size;
00909
00910     /* Check the remain data to be received */
00911     while (hsmartcard->RxXferCount > 0U)
00912     {
00913       hsmartcard->RxXferCount--;
00914
00915       if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
00916       {
00917         return HAL_TIMEOUT;
00918       }
00919       *ptmpdata = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF);
00920       ptmpdata++;
00921     }
00922
00923     /* At end of Rx process, restore hsmartcard->RxState to Ready */
00924     hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
00925
00926     /* Process Unlocked */
00927     __HAL_UNLOCK(hsmartcard);
00928
00929     return HAL_OK;
00930   }
00931   else
00932   {
00933     return HAL_BUSY;
00934   }
00935 }
00936
00937 /**
00938   * @brief  Send an amount of data in interrupt mode.
00939   * @note   When FIFO mode is disabled, USART interrupt is generated whenever
00940   *         USART_TDR register is empty, i.e one interrupt per data to transmit.
00941   * @note   When FIFO mode is enabled, USART interrupt is generated whenever
00942   *         TXFIFO threshold reached. In that case the interrupt rate depends on
00943   *         TXFIFO threshold configuration.
00944   * @note   This function sets the hsmartcard->TxIsr function pointer according to
00945   *         the FIFO mode (data transmission processing depends on FIFO mode).
00946   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00947   *                    the configuration information for the specified SMARTCARD module.
00948   * @param  pData pointer to data buffer.
00949   * @param  Size amount of data to be sent.
00950   * @retval HAL status
00951   */
00952 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
00953 {
00954   /* Check that a Tx process is not already ongoing */
00955   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
00956   {
00957     if ((pData == NULL) || (Size == 0U))
00958     {
00959       return HAL_ERROR;
00960     }
00961
00962     /* Process Locked */
00963     __HAL_LOCK(hsmartcard);
00964
00965     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00966     hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
00967
00968     hsmartcard->pTxBuffPtr  = pData;
00969     hsmartcard->TxXferSize  = Size;
00970     hsmartcard->TxXferCount = Size;
00971     hsmartcard->TxISR       = NULL;
00972
00973     /* Disable the Peripheral first to update mode for TX master */
00974     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00975
00976     /* Disable Rx, enable Tx */
00977     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
00978     SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
00979     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
00980
00981     /* Enable the Peripheral */
00982     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
00983
00984     /* Configure Tx interrupt processing */
00985     if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_ENABLE)
00986     {
00987       /* Set the Tx ISR function pointer */
00988       hsmartcard->TxISR = SMARTCARD_TxISR_FIFOEN;
00989
00990       /* Process Unlocked */
00991       __HAL_UNLOCK(hsmartcard);
00992
00993       /* Enable the SMARTCARD Error Interrupt: (Frame error) */
00994       SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
00995
00996       /* Enable the TX FIFO threshold interrupt */
00997       SET_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE);
00998     }
00999     else
01000     {
01001       /* Set the Tx ISR function pointer */
01002       hsmartcard->TxISR = SMARTCARD_TxISR;
01003
01004       /* Process Unlocked */
01005       __HAL_UNLOCK(hsmartcard);
01006
01007       /* Enable the SMARTCARD Error Interrupt: (Frame error) */
01008       SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01009
01010       /* Enable the SMARTCARD Transmit Data Register Empty Interrupt */
01011       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
01012     }
01013
01014     return HAL_OK;
01015   }
01016   else
01017   {
01018     return HAL_BUSY;
01019   }
01020 }
01021
01022 /**
01023   * @brief  Receive an amount of data in interrupt mode.
01024   * @note   When FIFO mode is disabled, USART interrupt is generated whenever
01025   *         USART_RDR register can be read, i.e one interrupt per data to receive.
01026   * @note   When FIFO mode is enabled, USART interrupt is generated whenever
01027   *         RXFIFO threshold reached. In that case the interrupt rate depends on
01028   *         RXFIFO threshold configuration.
01029   * @note   This function sets the hsmartcard->RxIsr function pointer according to
01030   *         the FIFO mode (data reception processing depends on FIFO mode).
01031   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01032   *                    the configuration information for the specified SMARTCARD module.
01033   * @param  pData pointer to data buffer.
01034   * @param  Size amount of data to be received.
01035   * @retval HAL status
01036   */
01037 HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
01038 {
01039   /* Check that a Rx process is not already ongoing */
01040   if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
01041   {
01042     if ((pData == NULL) || (Size == 0U))
01043     {
01044       return HAL_ERROR;
01045     }
01046
01047     /* Process Locked */
01048     __HAL_LOCK(hsmartcard);
01049
01050     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
01051     hsmartcard->RxState   = HAL_SMARTCARD_STATE_BUSY_RX;
01052
01053     hsmartcard->pRxBuffPtr = pData;
01054     hsmartcard->RxXferSize = Size;
01055     hsmartcard->RxXferCount = Size;
01056
01057     /* Configure Rx interrupt processing */
01058     if ((hsmartcard->FifoMode == SMARTCARD_FIFOMODE_ENABLE) && (Size >= hsmartcard->NbRxDataToProcess))
01059     {
01060       /* Set the Rx ISR function pointer */
01061       hsmartcard->RxISR = SMARTCARD_RxISR_FIFOEN;
01062
01063       /* Process Unlocked */
01064       __HAL_UNLOCK(hsmartcard);
01065
01066       /* Enable the SMARTCART Parity Error interrupt and RX FIFO Threshold interrupt */
01067       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
01068       SET_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTIE);
01069     }
01070     else
01071     {
01072       /* Set the Rx ISR function pointer */
01073       hsmartcard->RxISR = SMARTCARD_RxISR;
01074
01075       /* Process Unlocked */
01076       __HAL_UNLOCK(hsmartcard);
01077
01078       /* Enable the SMARTCARD Parity Error and Data Register not empty Interrupts */
01079       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
01080     }
01081
01082     /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
01083     SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01084
01085     return HAL_OK;
01086   }
01087   else
01088   {
01089     return HAL_BUSY;
01090   }
01091 }
01092
01093 /**
01094   * @brief  Send an amount of data in DMA mode.
01095   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01096   *                    the configuration information for the specified SMARTCARD module.
01097   * @param  pData pointer to data buffer.
01098   * @param  Size amount of data to be sent.
01099   * @retval HAL status
01100   */
01101 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
01102 {
01103   HAL_StatusTypeDef status;
01104
01105   /* Check that a Tx process is not already ongoing */
01106   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
01107   {
01108     if ((pData == NULL) || (Size == 0U))
01109     {
01110       return HAL_ERROR;
01111     }
01112
01113     /* Process Locked */
01114     __HAL_LOCK(hsmartcard);
01115
01116     hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
01117
01118     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
01119     hsmartcard->pTxBuffPtr = pData;
01120     hsmartcard->TxXferSize = Size;
01121     hsmartcard->TxXferCount = Size;
01122
01123     /* Disable the Peripheral first to update mode for TX master */
01124     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
01125
01126     /* Disable Rx, enable Tx */
01127     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
01128     SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
01129     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
01130
01131     /* Enable the Peripheral */
01132     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
01133
01134     /* Set the SMARTCARD DMA transfer complete callback */
01135     hsmartcard->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
01136
01137     /* Set the SMARTCARD error callback */
01138     hsmartcard->hdmatx->XferErrorCallback = SMARTCARD_DMAError;
01139
01140     /* Set the DMA abort callback */
01141     hsmartcard->hdmatx->XferAbortCallback = NULL;
01142
01143     /* Enable the SMARTCARD transmit DMA channel */
01144     status = HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR, Size);
01145
01146     if(status == HAL_OK)
01147     {
01148       /* Clear the TC flag in the ICR register */
01149       CLEAR_BIT(hsmartcard->Instance->ICR, USART_ICR_TCCF);
01150
01151       /* Process Unlocked */
01152       __HAL_UNLOCK(hsmartcard);
01153
01154       /* Enable the UART Error Interrupt: (Frame error) */
01155       SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01156
01157       /* Enable the DMA transfer for transmit request by setting the DMAT bit
01158          in the SMARTCARD associated USART CR3 register */
01159       SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
01160
01161       return HAL_OK;
01162     }
01163     else
01164     {
01165       /* Set error code to DMA */
01166       hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
01167
01168       /* Process Unlocked */
01169       __HAL_UNLOCK(hsmartcard);
01170
01171       /* Restore hsmartcard->State to ready */
01172       hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
01173
01174       return HAL_ERROR;
01175     }
01176   }
01177   else
01178   {
01179     return HAL_BUSY;
01180   }
01181 }
01182
01183 /**
01184   * @brief  Receive an amount of data in DMA mode.
01185   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01186   *                    the configuration information for the specified SMARTCARD module.
01187   * @param  pData pointer to data buffer.
01188   * @param  Size amount of data to be received.
01189   * @note   The SMARTCARD-associated USART parity is enabled (PCE = 1),
01190   *         the received data contain the parity bit (MSB position).
01191   * @retval HAL status
01192   */
01193 HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
01194 {
01195   HAL_StatusTypeDef status;
01196
01197   /* Check that a Rx process is not already ongoing */
01198   if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
01199   {
01200     if ((pData == NULL) || (Size == 0U))
01201     {
01202       return HAL_ERROR;
01203     }
01204
01205     /* Process Locked */
01206     __HAL_LOCK(hsmartcard);
01207
01208     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
01209     hsmartcard->RxState   = HAL_SMARTCARD_STATE_BUSY_RX;
01210
01211     hsmartcard->pRxBuffPtr = pData;
01212     hsmartcard->RxXferSize = Size;
01213
01214     /* Set the SMARTCARD DMA transfer complete callback */
01215     hsmartcard->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
01216
01217     /* Set the SMARTCARD DMA error callback */
01218     hsmartcard->hdmarx->XferErrorCallback = SMARTCARD_DMAError;
01219
01220     /* Set the DMA abort callback */
01221     hsmartcard->hdmarx->XferAbortCallback = NULL;
01222
01223     /* Enable the DMA channel */
01224     status = HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr, Size);
01225
01226     if(status == HAL_OK)
01227     {
01228       /* Process Unlocked */
01229       __HAL_UNLOCK(hsmartcard);
01230
01231       /* Enable the SMARTCARD Parity Error Interrupt */
01232       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
01233
01234       /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
01235       SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01236
01237       /* Enable the DMA transfer for the receiver request by setting the DMAR bit
01238          in the SMARTCARD associated USART CR3 register */
01239       SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
01240
01241       return HAL_OK;
01242     }
01243     else
01244     {
01245       /* Set error code to DMA */
01246       hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
01247
01248       /* Process Unlocked */
01249       __HAL_UNLOCK(hsmartcard);
01250
01251       /* Restore hsmartcard->State to ready */
01252       hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01253
01254       return HAL_ERROR;
01255     }
01256   }
01257   else
01258   {
01259     return HAL_BUSY;
01260   }
01261 }
01262
01263 /**
01264   * @brief  Abort ongoing transfers (blocking mode).
01265   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01266   *                    the configuration information for the specified SMARTCARD module.
01267   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01268   *         This procedure performs following operations :
01269   *           - Disable SMARTCARD Interrupts (Tx and Rx)
01270   *           - Disable the DMA transfer in the peripheral register (if enabled)
01271   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01272   *           - Set handle State to READY
01273   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01274   * @retval HAL status
01275   */
01276 HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard)
01277 {
01278   /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and  ERR (Frame error, noise error, overrun error) interrupts */
01279   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
01280   CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
01281
01282   /* Disable the SMARTCARD DMA Tx request if enabled */
01283   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
01284   {
01285     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
01286
01287     /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
01288     if (hsmartcard->hdmatx != NULL)
01289     {
01290       /* Set the SMARTCARD DMA Abort callback to Null.
01291          No call back execution at end of DMA abort procedure */
01292       hsmartcard->hdmatx->XferAbortCallback = NULL;
01293
01294       if (HAL_DMA_Abort(hsmartcard->hdmatx) != HAL_OK)
01295       {
01296         if (HAL_DMA_GetError(hsmartcard->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
01297         {
01298           /* Set error code to DMA */
01299           hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
01300
01301           /* Process Unlocked */
01302           __HAL_UNLOCK(hsmartcard);
01303
01304           return HAL_TIMEOUT;
01305         }
01306       }
01307     }
01308   }
01309
01310   /* Disable the SMARTCARD DMA Rx request if enabled */
01311   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
01312   {
01313     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
01314
01315     /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
01316     if (hsmartcard->hdmarx != NULL)
01317     {
01318       /* Set the SMARTCARD DMA Abort callback to Null.
01319          No call back execution at end of DMA abort procedure */
01320       hsmartcard->hdmarx->XferAbortCallback = NULL;
01321
01322       if (HAL_DMA_Abort(hsmartcard->hdmarx) != HAL_OK)
01323       {
01324         if (HAL_DMA_GetError(hsmartcard->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
01325         {
01326           /* Set error code to DMA */
01327           hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
01328
01329           /* Process Unlocked */
01330           __HAL_UNLOCK(hsmartcard);
01331
01332           return HAL_TIMEOUT;
01333         }
01334       }
01335     }
01336   }
01337
01338   /* Reset Tx and Rx transfer counters */
01339   hsmartcard->TxXferCount = 0U;
01340   hsmartcard->RxXferCount = 0U;
01341
01342   /* Clear the Error flags in the ICR register */
01343   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
01344
01345   /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
01346   hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
01347   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01348
01349   /* Reset Handle ErrorCode to No Error */
01350   hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
01351
01352   return HAL_OK;
01353 }
01354
01355 /**
01356   * @brief  Abort ongoing Transmit transfer (blocking mode).
01357   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01358   *                    the configuration information for the specified SMARTCARD module.
01359   * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
01360   *         This procedure performs following operations :
01361   *           - Disable SMARTCARD Interrupts (Tx)
01362   *           - Disable the DMA transfer in the peripheral register (if enabled)
01363   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01364   *           - Set handle State to READY
01365   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01366   * @retval HAL status
01367   */
01368 HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard)
01369 {
01370   /* Disable TCIE, TXEIE and TXFTIE interrupts */
01371   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
01372   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE);
01373
01374   /* Check if a receive process is ongoing or not. If not disable ERR IT */
01375   if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
01376   {
01377     /* Disable the SMARTCARD Error Interrupt: (Frame error) */
01378     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01379   }
01380
01381   /* Disable the SMARTCARD DMA Tx request if enabled */
01382   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
01383   {
01384     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
01385
01386     /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
01387     if (hsmartcard->hdmatx != NULL)
01388     {
01389       /* Set the SMARTCARD DMA Abort callback to Null.
01390          No call back execution at end of DMA abort procedure */
01391       hsmartcard->hdmatx->XferAbortCallback = NULL;
01392
01393       if (HAL_DMA_Abort(hsmartcard->hdmatx) != HAL_OK)
01394       {
01395         if (HAL_DMA_GetError(hsmartcard->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
01396         {
01397           /* Set error code to DMA */
01398           hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
01399
01400           /* Process Unlocked */
01401           __HAL_UNLOCK(hsmartcard);
01402
01403           return HAL_TIMEOUT;
01404         }
01405       }
01406     }
01407   }
01408
01409   /* Reset Tx transfer counter */
01410   hsmartcard->TxXferCount = 0U;
01411
01412   /* Clear the Error flags in the ICR register */
01413   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
01414
01415   /* Restore hsmartcard->gState to Ready */
01416   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
01417
01418   return HAL_OK;
01419 }
01420
01421 /**
01422   * @brief  Abort ongoing Receive transfer (blocking mode).
01423   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01424   *                    the configuration information for the specified SMARTCARD module.
01425   * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
01426   *         This procedure performs following operations :
01427   *           - Disable SMARTCARD Interrupts (Rx)
01428   *           - Disable the DMA transfer in the peripheral register (if enabled)
01429   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01430   *           - Set handle State to READY
01431   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01432   * @retval HAL status
01433   */
01434 HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard)
01435 {
01436   /* Disable RTOIE, EOBIE, RXNE, PE, RXFT, TXFT and  ERR (Frame error, noise error, overrun error) interrupts */
01437   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
01438   CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
01439
01440   /* Check if a Transmit process is ongoing or not. If not disable ERR IT */
01441   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
01442   {
01443     /* Disable the SMARTCARD Error Interrupt: (Frame error) */
01444     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01445   }
01446
01447   /* Disable the SMARTCARD DMA Rx request if enabled */
01448   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
01449   {
01450     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
01451
01452     /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
01453     if (hsmartcard->hdmarx != NULL)
01454     {
01455       /* Set the SMARTCARD DMA Abort callback to Null.
01456          No call back execution at end of DMA abort procedure */
01457       hsmartcard->hdmarx->XferAbortCallback = NULL;
01458
01459       if (HAL_DMA_Abort(hsmartcard->hdmarx) != HAL_OK)
01460       {
01461         if (HAL_DMA_GetError(hsmartcard->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
01462         {
01463           /* Set error code to DMA */
01464           hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
01465
01466           /* Process Unlocked */
01467           __HAL_UNLOCK(hsmartcard);
01468
01469           return HAL_TIMEOUT;
01470         }
01471       }
01472     }
01473   }
01474
01475   /* Reset Rx transfer counter */
01476   hsmartcard->RxXferCount = 0U;
01477
01478   /* Clear the Error flags in the ICR register */
01479   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
01480
01481   /* Restore hsmartcard->RxState to Ready */
01482   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01483
01484   return HAL_OK;
01485 }
01486
01487 /**
01488   * @brief  Abort ongoing transfers (Interrupt mode).
01489   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01490   *                    the configuration information for the specified SMARTCARD module.
01491   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01492   *         This procedure performs following operations :
01493   *           - Disable SMARTCARD Interrupts (Tx and Rx)
01494   *           - Disable the DMA transfer in the peripheral register (if enabled)
01495   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01496   *           - Set handle State to READY
01497   *           - At abort completion, call user abort complete callback
01498   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01499   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01500   * @retval HAL status
01501   */
01502 HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard)
01503 {
01504   uint32_t abortcplt = 1U;
01505
01506   /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and  ERR (Frame error, noise error, overrun error) interrupts */
01507   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
01508   CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
01509
01510   /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised
01511      before any call to DMA Abort functions */
01512   /* DMA Tx Handle is valid */
01513   if (hsmartcard->hdmatx != NULL)
01514   {
01515     /* Set DMA Abort Complete callback if SMARTCARD DMA Tx request if enabled.
01516        Otherwise, set it to NULL */
01517     if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
01518     {
01519       hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxAbortCallback;
01520     }
01521     else
01522     {
01523       hsmartcard->hdmatx->XferAbortCallback = NULL;
01524     }
01525   }
01526   /* DMA Rx Handle is valid */
01527   if (hsmartcard->hdmarx != NULL)
01528   {
01529     /* Set DMA Abort Complete callback if SMARTCARD DMA Rx request if enabled.
01530        Otherwise, set it to NULL */
01531     if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
01532     {
01533       hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxAbortCallback;
01534     }
01535     else
01536     {
01537       hsmartcard->hdmarx->XferAbortCallback = NULL;
01538     }
01539   }
01540
01541   /* Disable the SMARTCARD DMA Tx request if enabled */
01542   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
01543   {
01544     /* Disable DMA Tx at UART level */
01545     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
01546
01547     /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
01548     if (hsmartcard->hdmatx != NULL)
01549     {
01550       /* SMARTCARD Tx DMA Abort callback has already been initialised :
01551          will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
01552
01553       /* Abort DMA TX */
01554       if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
01555       {
01556         hsmartcard->hdmatx->XferAbortCallback = NULL;
01557       }
01558       else
01559       {
01560         abortcplt = 0U;
01561       }
01562     }
01563   }
01564
01565   /* Disable the SMARTCARD DMA Rx request if enabled */
01566   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
01567   {
01568     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
01569
01570     /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
01571     if (hsmartcard->hdmarx != NULL)
01572     {
01573       /* SMARTCARD Rx DMA Abort callback has already been initialised :
01574          will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
01575
01576       /* Abort DMA RX */
01577       if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
01578       {
01579         hsmartcard->hdmarx->XferAbortCallback = NULL;
01580         abortcplt = 1U;
01581       }
01582       else
01583       {
01584         abortcplt = 0U;
01585       }
01586     }
01587   }
01588
01589   /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
01590   if (abortcplt == 1U)
01591   {
01592     /* Reset Tx and Rx transfer counters */
01593     hsmartcard->TxXferCount = 0U;
01594     hsmartcard->RxXferCount = 0U;
01595
01596     /* Clear ISR function pointers */
01597     hsmartcard->RxISR = NULL;
01598     hsmartcard->TxISR = NULL;
01599
01600     /* Reset errorCode */
01601     hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
01602
01603     /* Clear the Error flags in the ICR register */
01604     __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
01605
01606     /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
01607     hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
01608     hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01609
01610     /* As no DMA to be aborted, call directly user Abort complete callback */
01611 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
01612     /* Call registered Abort complete callback */
01613     hsmartcard->AbortCpltCallback(hsmartcard);
01614 #else
01615     /* Call legacy weak Abort complete callback */
01616     HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
01617 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
01618   }
01619
01620   return HAL_OK;
01621 }
01622
01623 /**
01624   * @brief  Abort ongoing Transmit transfer (Interrupt mode).
01625   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01626   *                    the configuration information for the specified SMARTCARD module.
01627   * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
01628   *         This procedure performs following operations :
01629   *           - Disable SMARTCARD Interrupts (Tx)
01630   *           - Disable the DMA transfer in the peripheral register (if enabled)
01631   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01632   *           - Set handle State to READY
01633   *           - At abort completion, call user abort complete callback
01634   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01635   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01636   * @retval HAL status
01637   */
01638 HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
01639 {
01640   /* Disable TCIE, TXEIE and TXFTIE interrupts */
01641   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
01642   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE);
01643
01644   /* Check if a receive process is ongoing or not. If not disable ERR IT */
01645   if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
01646   {
01647     /* Disable the SMARTCARD Error Interrupt: (Frame error) */
01648     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01649   }
01650
01651   /* Disable the SMARTCARD DMA Tx request if enabled */
01652   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
01653   {
01654     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
01655
01656     /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
01657     if (hsmartcard->hdmatx != NULL)
01658     {
01659       /* Set the SMARTCARD DMA Abort callback :
01660          will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
01661       hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxOnlyAbortCallback;
01662
01663       /* Abort DMA TX */
01664       if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
01665       {
01666         /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
01667         hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
01668       }
01669     }
01670     else
01671     {
01672       /* Reset Tx transfer counter */
01673       hsmartcard->TxXferCount = 0U;
01674
01675       /* Clear TxISR function pointers */
01676       hsmartcard->TxISR = NULL;
01677
01678       /* Restore hsmartcard->gState to Ready */
01679       hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
01680
01681       /* As no DMA to be aborted, call directly user Abort complete callback */
01682 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
01683       /* Call registered Abort Transmit Complete Callback */
01684       hsmartcard->AbortTransmitCpltCallback(hsmartcard);
01685 #else
01686       /* Call legacy weak Abort Transmit Complete Callback */
01687       HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
01688 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
01689     }
01690   }
01691   else
01692   {
01693     /* Reset Tx transfer counter */
01694     hsmartcard->TxXferCount = 0U;
01695
01696     /* Clear TxISR function pointers */
01697     hsmartcard->TxISR = NULL;
01698
01699     /* Clear the Error flags in the ICR register */
01700     __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
01701
01702     /* Restore hsmartcard->gState to Ready */
01703     hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
01704
01705     /* As no DMA to be aborted, call directly user Abort complete callback */
01706 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
01707     /* Call registered Abort Transmit Complete Callback */
01708     hsmartcard->AbortTransmitCpltCallback(hsmartcard);
01709 #else
01710     /* Call legacy weak Abort Transmit Complete Callback */
01711     HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
01712 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
01713   }
01714
01715   return HAL_OK;
01716 }
01717
01718 /**
01719   * @brief  Abort ongoing Receive transfer (Interrupt mode).
01720   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01721   *                    the configuration information for the specified SMARTCARD module.
01722   * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
01723   *         This procedure performs following operations :
01724   *           - Disable SMARTCARD Interrupts (Rx)
01725   *           - Disable the DMA transfer in the peripheral register (if enabled)
01726   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01727   *           - Set handle State to READY
01728   *           - At abort completion, call user abort complete callback
01729   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01730   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01731   * @retval HAL status
01732 */
01733 HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
01734 {
01735   /* Disable RTOIE, EOBIE, RXNE, PE, RXFT and  ERR (Frame error, noise error, overrun error) interrupts */
01736   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
01737   CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
01738
01739   /* Check if a Transmit process is ongoing or not. If not disable ERR IT */
01740   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
01741   {
01742     /* Disable the SMARTCARD Error Interrupt: (Frame error) */
01743     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01744   }
01745
01746   /* Disable the SMARTCARD DMA Rx request if enabled */
01747   if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
01748   {
01749     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
01750
01751     /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
01752     if (hsmartcard->hdmarx != NULL)
01753     {
01754       /* Set the SMARTCARD DMA Abort callback :
01755          will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
01756       hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxOnlyAbortCallback;
01757
01758       /* Abort DMA RX */
01759       if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
01760       {
01761         /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
01762         hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
01763       }
01764     }
01765     else
01766     {
01767       /* Reset Rx transfer counter */
01768       hsmartcard->RxXferCount = 0U;
01769
01770       /* Clear RxISR function pointer */
01771       hsmartcard->RxISR = NULL;
01772
01773       /* Clear the Error flags in the ICR register */
01774       __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
01775
01776       /* Restore hsmartcard->RxState to Ready */
01777       hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01778
01779       /* As no DMA to be aborted, call directly user Abort complete callback */
01780 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
01781       /* Call registered Abort Receive Complete Callback */
01782       hsmartcard->AbortReceiveCpltCallback(hsmartcard);
01783 #else
01784       /* Call legacy weak Abort Receive Complete Callback */
01785       HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
01786 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
01787     }
01788   }
01789   else
01790   {
01791     /* Reset Rx transfer counter */
01792     hsmartcard->RxXferCount = 0U;
01793
01794     /* Clear RxISR function pointer */
01795     hsmartcard->RxISR = NULL;
01796
01797     /* Clear the Error flags in the ICR register */
01798     __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
01799
01800     /* Restore hsmartcard->RxState to Ready */
01801     hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
01802
01803     /* As no DMA to be aborted, call directly user Abort complete callback */
01804 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
01805     /* Call registered Abort Receive Complete Callback */
01806     hsmartcard->AbortReceiveCpltCallback(hsmartcard);
01807 #else
01808     /* Call legacy weak Abort Receive Complete Callback */
01809     HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
01810 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
01811   }
01812
01813   return HAL_OK;
01814 }
01815
01816 /**
01817   * @brief  Handle SMARTCARD interrupt requests.
01818   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
01819   *                    the configuration information for the specified SMARTCARD module.
01820   * @retval None
01821   */
01822 void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
01823 {
01824   uint32_t isrflags   = READ_REG(hsmartcard->Instance->ISR);
01825   uint32_t cr1its     = READ_REG(hsmartcard->Instance->CR1);
01826   uint32_t cr3its     = READ_REG(hsmartcard->Instance->CR3);
01827   uint32_t errorflags;
01828
01829   /* If no error occurs */
01830   errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
01831   if (errorflags == 0U)
01832   {
01833     /* SMARTCARD in mode Receiver ---------------------------------------------------*/
01834     if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
01835         && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
01836             || ((cr3its & USART_CR3_RXFTIE) != 0U)))
01837     {
01838       if (hsmartcard->RxISR != NULL)
01839       {
01840         hsmartcard->RxISR(hsmartcard);
01841       }
01842       return;
01843     }
01844   }
01845
01846   /* If some errors occur */
01847   if ((errorflags != 0U)
01848       && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
01849            || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U))))
01850   {
01851     /* SMARTCARD parity error interrupt occurred -------------------------------------*/
01852     if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
01853     {
01854       __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF);
01855
01856       hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
01857     }
01858
01859     /* SMARTCARD frame error interrupt occurred --------------------------------------*/
01860     if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
01861     {
01862       __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF);
01863
01864       hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
01865     }
01866
01867     /* SMARTCARD noise error interrupt occurred --------------------------------------*/
01868     if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
01869     {
01870       __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF);
01871
01872       hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
01873     }
01874
01875     /* SMARTCARD Over-Run interrupt occurred -----------------------------------------*/
01876     if (((isrflags & USART_ISR_ORE) != 0U)
01877         && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
01878             || ((cr3its & USART_CR3_RXFTIE) != 0U)
01879             || ((cr3its & USART_CR3_EIE) != 0U)))
01880     {
01881       __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF);
01882
01883       hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
01884     }
01885
01886     /* SMARTCARD receiver timeout interrupt occurred -----------------------------------------*/
01887     if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
01888     {
01889       __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF);
01890
01891       hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_RTO;
01892     }
01893
01894     /* Call SMARTCARD Error Call back function if need be --------------------------*/
01895     if (hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
01896     {
01897       /* SMARTCARD in mode Receiver ---------------------------------------------------*/
01898       if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
01899           && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
01900               || ((cr3its & USART_CR3_RXFTIE) != 0U)))
01901       {
01902         if (hsmartcard->RxISR != NULL)
01903         {
01904           hsmartcard->RxISR(hsmartcard);
01905         }
01906       }
01907
01908       /* If Error is to be considered as blocking :
01909       - Receiver Timeout error in Reception
01910       - Overrun error in Reception
01911       - any error occurs in DMA mode reception
01912       */
01913       if ((HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
01914           || ((hsmartcard->ErrorCode & (HAL_SMARTCARD_ERROR_RTO | HAL_SMARTCARD_ERROR_ORE)) != 0U))
01915       {
01916         /* Blocking error : transfer is aborted
01917         Set the SMARTCARD state ready to be able to start again the process,
01918         Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
01919         SMARTCARD_EndRxTransfer(hsmartcard);
01920
01921         /* Disable the SMARTCARD DMA Rx request if enabled */
01922         if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
01923         {
01924           CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
01925
01926           /* Abort the SMARTCARD DMA Rx channel */
01927           if (hsmartcard->hdmarx != NULL)
01928           {
01929             /* Set the SMARTCARD DMA Abort callback :
01930                will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
01931             hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
01932
01933             /* Abort DMA RX */
01934             if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
01935             {
01936               /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
01937               hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
01938             }
01939           }
01940           else
01941           {
01942 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
01943             /* Call registered user error callback */
01944             hsmartcard->ErrorCallback(hsmartcard);
01945 #else
01946             /* Call legacy weak user error callback */
01947             HAL_SMARTCARD_ErrorCallback(hsmartcard);
01948 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
01949           }
01950         }
01951         else
01952         {
01953 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
01954           /* Call registered user error callback */
01955           hsmartcard->ErrorCallback(hsmartcard);
01956 #else
01957           /* Call legacy weak user error callback */
01958           HAL_SMARTCARD_ErrorCallback(hsmartcard);
01959 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
01960         }
01961       }
01962       /* other error type to be considered as blocking :
01963       - Frame error in Transmission
01964       */
01965       else if ((hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
01966                && ((hsmartcard->ErrorCode & HAL_SMARTCARD_ERROR_FE) != 0U))
01967       {
01968         /* Blocking error : transfer is aborted
01969         Set the SMARTCARD state ready to be able to start again the process,
01970         Disable Tx Interrupts, and disable Tx DMA request, if ongoing */
01971         SMARTCARD_EndTxTransfer(hsmartcard);
01972
01973         /* Disable the SMARTCARD DMA Tx request if enabled */
01974         if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
01975         {
01976           CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
01977
01978           /* Abort the SMARTCARD DMA Tx channel */
01979           if (hsmartcard->hdmatx != NULL)
01980           {
01981             /* Set the SMARTCARD DMA Abort callback :
01982                will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
01983             hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
01984
01985             /* Abort DMA TX */
01986             if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
01987             {
01988               /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
01989               hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
01990             }
01991           }
01992           else
01993           {
01994 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
01995             /* Call registered user error callback */
01996             hsmartcard->ErrorCallback(hsmartcard);
01997 #else
01998             /* Call legacy weak user error callback */
01999             HAL_SMARTCARD_ErrorCallback(hsmartcard);
02000 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02001           }
02002         }
02003         else
02004         {
02005 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02006           /* Call registered user error callback */
02007           hsmartcard->ErrorCallback(hsmartcard);
02008 #else
02009           /* Call legacy weak user error callback */
02010           HAL_SMARTCARD_ErrorCallback(hsmartcard);
02011 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02012         }
02013       }
02014       else
02015       {
02016         /* Non Blocking error : transfer could go on.
02017            Error is notified to user through user error callback */
02018 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02019         /* Call registered user error callback */
02020         hsmartcard->ErrorCallback(hsmartcard);
02021 #else
02022         /* Call legacy weak user error callback */
02023         HAL_SMARTCARD_ErrorCallback(hsmartcard);
02024 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02025         hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
02026       }
02027     }
02028     return;
02029
02030   } /* End if some error occurs */
02031
02032   /* SMARTCARD in mode Receiver, end of block interruption ------------------------*/
02033   if (((isrflags & USART_ISR_EOBF) != 0U) && ((cr1its & USART_CR1_EOBIE) != 0U))
02034   {
02035     hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02036     __HAL_UNLOCK(hsmartcard);
02037 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02038     /* Call registered Rx complete callback */
02039     hsmartcard->RxCpltCallback(hsmartcard);
02040 #else
02041     /* Call legacy weak Rx complete callback */
02042     HAL_SMARTCARD_RxCpltCallback(hsmartcard);
02043 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02044     /* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information
02045     * to be available during HAL_SMARTCARD_RxCpltCallback() processing */
02046     __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_EOBF);
02047     return;
02048   }
02049
02050   /* SMARTCARD in mode Transmitter ------------------------------------------------*/
02051   if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
02052       && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
02053           || ((cr3its & USART_CR3_TXFTIE) != 0U)))
02054   {
02055     if (hsmartcard->TxISR != NULL)
02056     {
02057       hsmartcard->TxISR(hsmartcard);
02058     }
02059     return;
02060   }
02061
02062   /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
02063   if (__HAL_SMARTCARD_GET_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET)
02064   {
02065     if(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET)
02066     {
02067       SMARTCARD_EndTransmit_IT(hsmartcard);
02068       return;
02069     }
02070   }
02071
02072   /* SMARTCARD TX Fifo Empty occurred ----------------------------------------------*/
02073   if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
02074   {
02075 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02076     /* Call registered Tx Fifo Empty Callback */
02077     hsmartcard->TxFifoEmptyCallback(hsmartcard);
02078 #else
02079     /* Call legacy weak Tx Fifo Empty Callback */
02080     HAL_SMARTCARDEx_TxFifoEmptyCallback(hsmartcard);
02081 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02082     return;
02083   }
02084
02085   /* SMARTCARD RX Fifo Full occurred ----------------------------------------------*/
02086   if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
02087   {
02088 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02089     /* Call registered Rx Fifo Full Callback */
02090     hsmartcard->RxFifoFullCallback(hsmartcard);
02091 #else
02092     /* Call legacy weak Rx Fifo Full Callback */
02093     HAL_SMARTCARDEx_RxFifoFullCallback(hsmartcard);
02094 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02095     return;
02096   }
02097 }
02098
02099 /**
02100   * @brief  Tx Transfer completed callback.
02101   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02102   *                    the configuration information for the specified SMARTCARD module.
02103   * @retval None
02104   */
02105 __weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
02106 {
02107   /* Prevent unused argument(s) compilation warning */
02108   UNUSED(hsmartcard);
02109
02110   /* NOTE : This function should not be modified, when the callback is needed,
02111             the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file.
02112    */
02113 }
02114
02115 /**
02116   * @brief  Rx Transfer completed callback.
02117   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02118   *                    the configuration information for the specified SMARTCARD module.
02119   * @retval None
02120   */
02121 __weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
02122 {
02123   /* Prevent unused argument(s) compilation warning */
02124   UNUSED(hsmartcard);
02125
02126   /* NOTE : This function should not be modified, when the callback is needed,
02127             the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file.
02128    */
02129 }
02130
02131 /**
02132   * @brief  SMARTCARD error callback.
02133   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02134   *                    the configuration information for the specified SMARTCARD module.
02135   * @retval None
02136   */
02137 __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard)
02138 {
02139   /* Prevent unused argument(s) compilation warning */
02140   UNUSED(hsmartcard);
02141
02142   /* NOTE : This function should not be modified, when the callback is needed,
02143             the HAL_SMARTCARD_ErrorCallback can be implemented in the user file.
02144    */
02145 }
02146
02147 /**
02148   * @brief  SMARTCARD Abort Complete callback.
02149   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02150   *                    the configuration information for the specified SMARTCARD module.
02151   * @retval None
02152   */
02153 __weak void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
02154 {
02155   /* Prevent unused argument(s) compilation warning */
02156   UNUSED(hsmartcard);
02157
02158   /* NOTE : This function should not be modified, when the callback is needed,
02159             the HAL_SMARTCARD_AbortCpltCallback can be implemented in the user file.
02160    */
02161 }
02162
02163 /**
02164   * @brief  SMARTCARD Abort Complete callback.
02165   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02166   *                    the configuration information for the specified SMARTCARD module.
02167   * @retval None
02168   */
02169 __weak void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
02170 {
02171   /* Prevent unused argument(s) compilation warning */
02172   UNUSED(hsmartcard);
02173
02174   /* NOTE : This function should not be modified, when the callback is needed,
02175             the HAL_SMARTCARD_AbortTransmitCpltCallback can be implemented in the user file.
02176    */
02177 }
02178
02179 /**
02180   * @brief  SMARTCARD Abort Receive Complete callback.
02181   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02182   *                    the configuration information for the specified SMARTCARD module.
02183   * @retval None
02184   */
02185 __weak void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
02186 {
02187   /* Prevent unused argument(s) compilation warning */
02188   UNUSED(hsmartcard);
02189
02190   /* NOTE : This function should not be modified, when the callback is needed,
02191             the HAL_SMARTCARD_AbortReceiveCpltCallback can be implemented in the user file.
02192    */
02193 }
02194
02195 /**
02196   * @}
02197   */
02198
02199 /** @defgroup SMARTCARD_Exported_Functions_Group4 Peripheral State and Errors functions
02200   * @brief    SMARTCARD State and Errors functions
02201   *
02202 @verbatim
02203   ==============================================================================
02204                   ##### Peripheral State and Errors functions #####
02205   ==============================================================================
02206   [..]
02207     This subsection provides a set of functions allowing to return the State of SmartCard
02208     handle and also return Peripheral Errors occurred during communication process
02209      (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state
02210          of the SMARTCARD peripheral.
02211      (+) HAL_SMARTCARD_GetError() checks in run-time errors that could occur during
02212          communication.
02213
02214 @endverbatim
02215   * @{
02216   */
02217
02218 /**
02219   * @brief  Return the SMARTCARD handle state.
02220   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02221   *                    the configuration information for the specified SMARTCARD module.
02222   * @retval SMARTCARD handle state
02223   */
02224 HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard)
02225 {
02226   /* Return SMARTCARD handle state */
02227   uint32_t temp1, temp2;
02228   temp1 = (uint32_t)hsmartcard->gState;
02229   temp2 = (uint32_t)hsmartcard->RxState;
02230
02231   return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2);
02232 }
02233
02234 /**
02235   * @brief  Return the SMARTCARD handle error code.
02236   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02237   *                    the configuration information for the specified SMARTCARD module.
02238   * @retval SMARTCARD handle Error Code
02239   */
02240 uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard)
02241 {
02242   return hsmartcard->ErrorCode;
02243 }
02244
02245 /**
02246   * @}
02247   */
02248
02249 /**
02250   * @}
02251   */
02252
02253 /** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
02254   * @{
02255   */
02256
02257 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02258 /**
02259   * @brief  Initialize the callbacks to their default values.
02260   * @param  hsmartcard SMARTCARD handle.
02261   * @retval none
02262   */
02263 void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard)
02264 {
02265   /* Init the SMARTCARD Callback settings */
02266   hsmartcard->TxCpltCallback            = HAL_SMARTCARD_TxCpltCallback;            /* Legacy weak TxCpltCallback            */
02267   hsmartcard->RxCpltCallback            = HAL_SMARTCARD_RxCpltCallback;            /* Legacy weak RxCpltCallback            */
02268   hsmartcard->ErrorCallback             = HAL_SMARTCARD_ErrorCallback;             /* Legacy weak ErrorCallback             */
02269   hsmartcard->AbortCpltCallback         = HAL_SMARTCARD_AbortCpltCallback;         /* Legacy weak AbortCpltCallback         */
02270   hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
02271   hsmartcard->AbortReceiveCpltCallback  = HAL_SMARTCARD_AbortReceiveCpltCallback;  /* Legacy weak AbortReceiveCpltCallback  */
02272   hsmartcard->RxFifoFullCallback        = HAL_SMARTCARDEx_RxFifoFullCallback;      /* Legacy weak RxFifoFullCallback        */
02273   hsmartcard->TxFifoEmptyCallback       = HAL_SMARTCARDEx_TxFifoEmptyCallback;     /* Legacy weak TxFifoEmptyCallback       */
02274
02275 }
02276 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
02277
02278 /**
02279   * @brief  Configure the SMARTCARD associated USART peripheral.
02280   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02281   *                    the configuration information for the specified SMARTCARD module.
02282   * @retval HAL status
02283   */
02284 static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard)
02285 {
02286   uint32_t tmpreg;
02287   SMARTCARD_ClockSourceTypeDef clocksource;
02288   HAL_StatusTypeDef ret                    = HAL_OK;
02289   const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
02290   uint32_t pclk;
02291
02292   /* Check the parameters */
02293   assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
02294   assert_param(IS_SMARTCARD_BAUDRATE(hsmartcard->Init.BaudRate));
02295   assert_param(IS_SMARTCARD_WORD_LENGTH(hsmartcard->Init.WordLength));
02296   assert_param(IS_SMARTCARD_STOPBITS(hsmartcard->Init.StopBits));
02297   assert_param(IS_SMARTCARD_PARITY(hsmartcard->Init.Parity));
02298   assert_param(IS_SMARTCARD_MODE(hsmartcard->Init.Mode));
02299   assert_param(IS_SMARTCARD_POLARITY(hsmartcard->Init.CLKPolarity));
02300   assert_param(IS_SMARTCARD_PHASE(hsmartcard->Init.CLKPhase));
02301   assert_param(IS_SMARTCARD_LASTBIT(hsmartcard->Init.CLKLastBit));
02302   assert_param(IS_SMARTCARD_ONE_BIT_SAMPLE(hsmartcard->Init.OneBitSampling));
02303   assert_param(IS_SMARTCARD_NACK(hsmartcard->Init.NACKEnable));
02304   assert_param(IS_SMARTCARD_TIMEOUT(hsmartcard->Init.TimeOutEnable));
02305   assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsmartcard->Init.AutoRetryCount));
02306   assert_param(IS_SMARTCARD_CLOCKPRESCALER(hsmartcard->Init.ClockPrescaler));
02307
02308   /*-------------------------- USART CR1 Configuration -----------------------*/
02309   /* In SmartCard mode, M and PCE are forced to 1 (8 bits + parity).
02310    * Oversampling is forced to 16 (OVER8 = 0).
02311    * Configure the Parity and Mode:
02312    *  set PS bit according to hsmartcard->Init.Parity value
02313    *  set TE and RE bits according to hsmartcard->Init.Mode value */
02314   tmpreg = (uint32_t) hsmartcard->Init.Parity | hsmartcard->Init.Mode;
02315   tmpreg |= (uint32_t) hsmartcard->Init.WordLength | hsmartcard->FifoMode;
02316   MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg);
02317
02318   /*-------------------------- USART CR2 Configuration -----------------------*/
02319   tmpreg = hsmartcard->Init.StopBits;
02320   /* Synchronous mode is activated by default */
02321   tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity;
02322   tmpreg |= (uint32_t) hsmartcard->Init.CLKPhase | hsmartcard->Init.CLKLastBit;
02323   tmpreg |= (uint32_t) hsmartcard->Init.TimeOutEnable;
02324   MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg);
02325
02326   /*-------------------------- USART CR3 Configuration -----------------------*/
02327   /* Configure
02328    * - one-bit sampling method versus three samples' majority rule
02329    *   according to hsmartcard->Init.OneBitSampling
02330    * - NACK transmission in case of parity error according
02331    *   to hsmartcard->Init.NACKEnable
02332    * - autoretry counter according to hsmartcard->Init.AutoRetryCount */
02333
02334   tmpreg = (uint32_t) hsmartcard->Init.OneBitSampling | hsmartcard->Init.NACKEnable;
02335   tmpreg |= ((uint32_t)hsmartcard->Init.AutoRetryCount << USART_CR3_SCARCNT_Pos);
02336   MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_FIELDS, tmpreg);
02337
02338   /*--------------------- SMARTCARD clock PRESC Configuration ----------------*/
02339   /* Configure
02340   * - SMARTCARD Clock Prescaler: set PRESCALER according to hsmartcard->Init.ClockPrescaler value */
02341   MODIFY_REG(hsmartcard->Instance->PRESC, USART_PRESC_PRESCALER, hsmartcard->Init.ClockPrescaler);
02342
02343   /*-------------------------- USART GTPR Configuration ----------------------*/
02344   tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << USART_GTPR_GT_Pos));
02345   MODIFY_REG(hsmartcard->Instance->GTPR, (uint16_t)(USART_GTPR_GT | USART_GTPR_PSC), (uint16_t)tmpreg);
02346
02347   /*-------------------------- USART RTOR Configuration ----------------------*/
02348   tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << USART_RTOR_BLEN_Pos);
02349   if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE)
02350   {
02351     assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
02352     tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue;
02353   }
02354   MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO | USART_RTOR_BLEN), tmpreg);
02355
02356   /*-------------------------- USART BRR Configuration -----------------------*/
02357   SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource);
02358   tmpreg =   0U;
02359   switch (clocksource)
02360   {
02361     case SMARTCARD_CLOCKSOURCE_PCLK2:
02362       pclk = HAL_RCC_GetPCLK2Freq();
02363       tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
02364       break;
02365     case SMARTCARD_CLOCKSOURCE_HSI:
02366       tmpreg = (uint16_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
02367       break;
02368     case SMARTCARD_CLOCKSOURCE_SYSCLK:
02369       pclk = HAL_RCC_GetSysClockFreq();
02370       tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
02371       break;
02372     case SMARTCARD_CLOCKSOURCE_LSE:
02373       tmpreg = (uint16_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
02374       break;
02375     default:
02376       ret = HAL_ERROR;
02377       break;
02378   }
02379
02380   /* USARTDIV must be greater than or equal to 0d16 */
02381   if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX))
02382   {
02383     hsmartcard->Instance->BRR = tmpreg;
02384   }
02385   else
02386   {
02387     ret = HAL_ERROR;
02388   }
02389
02390   /* Initialize the number of data to process during RX/TX ISR execution */
02391   hsmartcard->NbTxDataToProcess = 1U;
02392   hsmartcard->NbRxDataToProcess = 1U;
02393
02394   /* Clear ISR function pointers */
02395   hsmartcard->RxISR   = NULL;
02396   hsmartcard->TxISR   = NULL;
02397
02398   return ret;
02399 }
02400
02401
02402 /**
02403   * @brief Configure the SMARTCARD associated USART peripheral advanced features.
02404   * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02405   *                   the configuration information for the specified SMARTCARD module.
02406   * @retval None
02407   */
02408 static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard)
02409 {
02410   /* Check whether the set of advanced features to configure is properly set */
02411   assert_param(IS_SMARTCARD_ADVFEATURE_INIT(hsmartcard->AdvancedInit.AdvFeatureInit));
02412
02413   /* if required, configure TX pin active level inversion */
02414   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXINVERT_INIT))
02415   {
02416     assert_param(IS_SMARTCARD_ADVFEATURE_TXINV(hsmartcard->AdvancedInit.TxPinLevelInvert));
02417     MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_TXINV, hsmartcard->AdvancedInit.TxPinLevelInvert);
02418   }
02419
02420   /* if required, configure RX pin active level inversion */
02421   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXINVERT_INIT))
02422   {
02423     assert_param(IS_SMARTCARD_ADVFEATURE_RXINV(hsmartcard->AdvancedInit.RxPinLevelInvert));
02424     MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_RXINV, hsmartcard->AdvancedInit.RxPinLevelInvert);
02425   }
02426
02427   /* if required, configure data inversion */
02428   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DATAINVERT_INIT))
02429   {
02430     assert_param(IS_SMARTCARD_ADVFEATURE_DATAINV(hsmartcard->AdvancedInit.DataInvert));
02431     MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_DATAINV, hsmartcard->AdvancedInit.DataInvert);
02432   }
02433
02434   /* if required, configure RX/TX pins swap */
02435   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_SWAP_INIT))
02436   {
02437     assert_param(IS_SMARTCARD_ADVFEATURE_SWAP(hsmartcard->AdvancedInit.Swap));
02438     MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_SWAP, hsmartcard->AdvancedInit.Swap);
02439   }
02440
02441   /* if required, configure RX overrun detection disabling */
02442   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT))
02443   {
02444     assert_param(IS_SMARTCARD_OVERRUN(hsmartcard->AdvancedInit.OverrunDisable));
02445     MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_OVRDIS, hsmartcard->AdvancedInit.OverrunDisable);
02446   }
02447
02448   /* if required, configure DMA disabling on reception error */
02449   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT))
02450   {
02451     assert_param(IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(hsmartcard->AdvancedInit.DMADisableonRxError));
02452     MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_DDRE, hsmartcard->AdvancedInit.DMADisableonRxError);
02453   }
02454
02455   /* if required, configure MSB first on communication line */
02456   if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
02457   {
02458     assert_param(IS_SMARTCARD_ADVFEATURE_MSBFIRST(hsmartcard->AdvancedInit.MSBFirst));
02459     MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_MSBFIRST, hsmartcard->AdvancedInit.MSBFirst);
02460   }
02461
02462 }
02463
02464 /**
02465   * @brief Check the SMARTCARD Idle State.
02466   * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02467   *                   the configuration information for the specified SMARTCARD module.
02468   * @retval HAL status
02469   */
02470 static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard)
02471 {
02472   uint32_t tickstart;
02473
02474   /* Initialize the SMARTCARD ErrorCode */
02475   hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
02476
02477   /* Init tickstart for timeout management */
02478   tickstart = HAL_GetTick();
02479
02480   /* Check if the Transmitter is enabled */
02481   if ((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
02482   {
02483     /* Wait until TEACK flag is set */
02484     if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
02485     {
02486       /* Timeout occurred */
02487       return HAL_TIMEOUT;
02488     }
02489   }
02490   /* Check if the Receiver is enabled */
02491   if ((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
02492   {
02493     /* Wait until REACK flag is set */
02494     if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
02495     {
02496       /* Timeout occurred */
02497       return HAL_TIMEOUT;
02498     }
02499   }
02500
02501   /* Initialize the SMARTCARD states */
02502   hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
02503   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02504
02505   /* Process Unlocked */
02506   __HAL_UNLOCK(hsmartcard);
02507
02508   return HAL_OK;
02509 }
02510
02511 /**
02512   * @brief  Handle SMARTCARD Communication Timeout.
02513   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02514   *                   the configuration information for the specified SMARTCARD module.
02515   * @param  Flag Specifies the SMARTCARD flag to check.
02516   * @param  Status The new Flag status (SET or RESET).
02517   * @param  Tickstart Tick start value
02518   * @param  Timeout Timeout duration.
02519   * @retval HAL status
02520   */
02521 static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
02522 {
02523   /* Wait until flag is set */
02524   while ((__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) ? SET : RESET) == Status)
02525   {
02526     /* Check for the Timeout */
02527     if (Timeout != HAL_MAX_DELAY)
02528     {
02529       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
02530       {
02531         /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
02532         CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
02533         CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
02534
02535         hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
02536         hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02537
02538         /* Process Unlocked */
02539         __HAL_UNLOCK(hsmartcard);
02540         return HAL_TIMEOUT;
02541       }
02542     }
02543   }
02544   return HAL_OK;
02545 }
02546
02547
02548 /**
02549   * @brief  End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
02550   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02551   *                    the configuration information for the specified SMARTCARD module.
02552   * @retval None
02553   */
02554 static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
02555 {
02556   /* Disable TXEIE, TCIE and ERR (Frame error, noise error, overrun error) interrupts */
02557   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
02558   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
02559
02560   /* At end of Tx process, restore hsmartcard->gState to Ready */
02561   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
02562 }
02563
02564
02565 /**
02566   * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
02567   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02568   *                    the configuration information for the specified SMARTCARD module.
02569   * @retval None
02570   */
02571 static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
02572 {
02573   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
02574   CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
02575   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
02576
02577   /* At end of Rx process, restore hsmartcard->RxState to Ready */
02578   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02579 }
02580
02581
02582 /**
02583   * @brief  DMA SMARTCARD transmit process complete callback.
02584   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
02585   *              the configuration information for the specified DMA module.
02586   * @retval None
02587   */
02588 static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
02589 {
02590   SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
02591   hsmartcard->TxXferCount = 0U;
02592
02593   /* Disable the DMA transfer for transmit request by resetting the DMAT bit
02594   in the SMARTCARD associated USART CR3 register */
02595   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
02596
02597   /* Enable the SMARTCARD Transmit Complete Interrupt */
02598   __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
02599 }
02600
02601 /**
02602   * @brief  DMA SMARTCARD receive process complete callback.
02603   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
02604   *              the configuration information for the specified DMA module.
02605   * @retval None
02606   */
02607 static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
02608 {
02609   SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
02610   hsmartcard->RxXferCount = 0U;
02611
02612   /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
02613   CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
02614   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
02615
02616   /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
02617      in the SMARTCARD associated USART CR3 register */
02618   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
02619
02620   /* At end of Rx process, restore hsmartcard->RxState to Ready */
02621   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02622
02623 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02624   /* Call registered Rx complete callback */
02625   hsmartcard->RxCpltCallback(hsmartcard);
02626 #else
02627   /* Call legacy weak Rx complete callback */
02628   HAL_SMARTCARD_RxCpltCallback(hsmartcard);
02629 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02630 }
02631
02632 /**
02633   * @brief  DMA SMARTCARD communication error callback.
02634   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
02635   *              the configuration information for the specified DMA module.
02636   * @retval None
02637   */
02638 static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
02639 {
02640   SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
02641
02642   /* Stop SMARTCARD DMA Tx request if ongoing */
02643   if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
02644   {
02645     if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
02646     {
02647       hsmartcard->TxXferCount = 0U;
02648       SMARTCARD_EndTxTransfer(hsmartcard);
02649     }
02650   }
02651
02652   /* Stop SMARTCARD DMA Rx request if ongoing */
02653   if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
02654   {
02655     if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
02656     {
02657       hsmartcard->RxXferCount = 0U;
02658       SMARTCARD_EndRxTransfer(hsmartcard);
02659     }
02660   }
02661
02662   hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_DMA;
02663 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02664   /* Call registered user error callback */
02665   hsmartcard->ErrorCallback(hsmartcard);
02666 #else
02667   /* Call legacy weak user error callback */
02668   HAL_SMARTCARD_ErrorCallback(hsmartcard);
02669 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02670 }
02671
02672 /**
02673   * @brief  DMA SMARTCARD communication abort callback, when initiated by HAL services on Error
02674   *         (To be called at end of DMA Abort procedure following error occurrence).
02675   * @param  hdma DMA handle.
02676   * @retval None
02677   */
02678 static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma)
02679 {
02680   SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
02681   hsmartcard->RxXferCount = 0U;
02682   hsmartcard->TxXferCount = 0U;
02683
02684 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02685   /* Call registered user error callback */
02686   hsmartcard->ErrorCallback(hsmartcard);
02687 #else
02688   /* Call legacy weak user error callback */
02689   HAL_SMARTCARD_ErrorCallback(hsmartcard);
02690 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02691 }
02692
02693 /**
02694   * @brief  DMA SMARTCARD Tx communication abort callback, when initiated by user
02695   *         (To be called at end of DMA Tx Abort procedure following user abort request).
02696   * @note   When this callback is executed, User Abort complete call back is called only if no
02697   *         Abort still ongoing for Rx DMA Handle.
02698   * @param  hdma DMA handle.
02699   * @retval None
02700   */
02701 static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
02702 {
02703   SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
02704
02705   hsmartcard->hdmatx->XferAbortCallback = NULL;
02706
02707   /* Check if an Abort process is still ongoing */
02708   if (hsmartcard->hdmarx != NULL)
02709   {
02710     if (hsmartcard->hdmarx->XferAbortCallback != NULL)
02711     {
02712       return;
02713     }
02714   }
02715
02716   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02717   hsmartcard->TxXferCount = 0U;
02718   hsmartcard->RxXferCount = 0U;
02719
02720   /* Reset errorCode */
02721   hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
02722
02723   /* Clear the Error flags in the ICR register */
02724   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
02725
02726   /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
02727   hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
02728   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02729
02730 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02731   /* Call registered Abort complete callback */
02732   hsmartcard->AbortCpltCallback(hsmartcard);
02733 #else
02734   /* Call legacy weak Abort complete callback */
02735   HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
02736 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02737 }
02738
02739
02740 /**
02741   * @brief  DMA SMARTCARD Rx communication abort callback, when initiated by user
02742   *         (To be called at end of DMA Rx Abort procedure following user abort request).
02743   * @note   When this callback is executed, User Abort complete call back is called only if no
02744   *         Abort still ongoing for Tx DMA Handle.
02745   * @param  hdma DMA handle.
02746   * @retval None
02747   */
02748 static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
02749 {
02750   SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
02751
02752   hsmartcard->hdmarx->XferAbortCallback = NULL;
02753
02754   /* Check if an Abort process is still ongoing */
02755   if (hsmartcard->hdmatx != NULL)
02756   {
02757     if (hsmartcard->hdmatx->XferAbortCallback != NULL)
02758     {
02759       return;
02760     }
02761   }
02762
02763   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02764   hsmartcard->TxXferCount = 0U;
02765   hsmartcard->RxXferCount = 0U;
02766
02767   /* Reset errorCode */
02768   hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
02769
02770   /* Clear the Error flags in the ICR register */
02771   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
02772
02773   /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
02774   hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
02775   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02776
02777 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02778   /* Call registered Abort complete callback */
02779   hsmartcard->AbortCpltCallback(hsmartcard);
02780 #else
02781   /* Call legacy weak Abort complete callback */
02782   HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
02783 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02784 }
02785
02786
02787 /**
02788   * @brief  DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to
02789   *         HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer)
02790   *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
02791   *         and leads to user Tx Abort Complete callback execution).
02792   * @param  hdma DMA handle.
02793   * @retval None
02794   */
02795 static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
02796 {
02797   SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
02798
02799   hsmartcard->TxXferCount = 0U;
02800
02801   /* Clear the Error flags in the ICR register */
02802   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
02803
02804   /* Restore hsmartcard->gState to Ready */
02805   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
02806
02807 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02808   /* Call registered Abort Transmit Complete Callback */
02809   hsmartcard->AbortTransmitCpltCallback(hsmartcard);
02810 #else
02811   /* Call legacy weak Abort Transmit Complete Callback */
02812   HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
02813 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02814 }
02815
02816 /**
02817   * @brief  DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to
02818   *         HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer)
02819   *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
02820   *         and leads to user Rx Abort Complete callback execution).
02821   * @param  hdma DMA handle.
02822   * @retval None
02823   */
02824 static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
02825 {
02826   SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
02827
02828   hsmartcard->RxXferCount = 0U;
02829
02830   /* Clear the Error flags in the ICR register */
02831   __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
02832
02833   /* Restore hsmartcard->RxState to Ready */
02834   hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02835
02836 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02837   /* Call registered Abort Receive Complete Callback */
02838   hsmartcard->AbortReceiveCpltCallback(hsmartcard);
02839 #else
02840   /* Call legacy weak Abort Receive Complete Callback */
02841   HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
02842 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02843 }
02844
02845 /**
02846   * @brief  Send an amount of data in non-blocking mode.
02847   * @note   Function called under interruption only, once
02848   *         interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
02849   *         and when the FIFO mode is disabled.
02850   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02851   *                    the configuration information for the specified SMARTCARD module.
02852   * @retval None
02853   */
02854 static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard)
02855 {
02856   /* Check that a Tx process is ongoing */
02857   if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
02858   {
02859     if (hsmartcard->TxXferCount == 0U)
02860     {
02861       /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */
02862       CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
02863
02864       /* Enable the SMARTCARD Transmit Complete Interrupt */
02865       __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
02866     }
02867     else
02868     {
02869       hsmartcard->Instance->TDR = (uint8_t)(*hsmartcard->pTxBuffPtr & 0xFFU);
02870       hsmartcard->pTxBuffPtr++;
02871       hsmartcard->TxXferCount--;
02872     }
02873   }
02874 }
02875
02876 /**
02877   * @brief  Send an amount of data in non-blocking mode.
02878   * @note   Function called under interruption only, once
02879   *         interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
02880   *         and when the FIFO mode is enabled.
02881   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02882   *                    the configuration information for the specified SMARTCARD module.
02883   * @retval None
02884   */
02885 static void SMARTCARD_TxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard)
02886 {
02887   uint16_t   nb_tx_data;
02888
02889   /* Check that a Tx process is ongoing */
02890   if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
02891   {
02892     for (nb_tx_data = hsmartcard->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
02893     {
02894       if (hsmartcard->TxXferCount == 0U)
02895       {
02896         /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */
02897         CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
02898
02899         /* Enable the SMARTCARD Transmit Complete Interrupt */
02900         __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
02901       }
02902       else if (READ_BIT(hsmartcard->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
02903       {
02904         hsmartcard->Instance->TDR = (uint8_t)(*hsmartcard->pTxBuffPtr & 0xFFU);
02905         hsmartcard->pTxBuffPtr++;
02906         hsmartcard->TxXferCount--;
02907       }
02908       else
02909       {
02910         /* Nothing to do */
02911       }
02912     }
02913   }
02914 }
02915
02916 /**
02917   * @brief  Wrap up transmission in non-blocking mode.
02918   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02919   *                    the configuration information for the specified SMARTCARD module.
02920   * @retval None
02921   */
02922 static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
02923 {
02924   /* Disable the SMARTCARD Transmit Complete Interrupt */
02925   __HAL_SMARTCARD_DISABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
02926
02927   /* Check if a receive process is ongoing or not. If not disable ERR IT */
02928   if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
02929   {
02930     /* Disable the SMARTCARD Error Interrupt: (Frame error) */
02931     CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
02932   }
02933
02934   /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */
02935   if (hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
02936   {
02937     /* Disable the Peripheral first to update modes */
02938     CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
02939     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
02940     /* Enable the Peripheral */
02941     SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
02942   }
02943
02944   /* Tx process is ended, restore hsmartcard->gState to Ready */
02945   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
02946
02947   /* Clear TxISR function pointer */
02948   hsmartcard->TxISR = NULL;
02949
02950 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02951   /* Call registered Tx complete callback */
02952   hsmartcard->TxCpltCallback(hsmartcard);
02953 #else
02954   /* Call legacy weak Tx complete callback */
02955   HAL_SMARTCARD_TxCpltCallback(hsmartcard);
02956 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
02957 }
02958
02959 /**
02960   * @brief  Receive an amount of data in non-blocking mode.
02961   * @note   Function called under interruption only, once
02962   *         interruptions have been enabled by HAL_SMARTCARD_Receive_IT()
02963   *         and when the FIFO mode is disabled.
02964   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
02965   *                    the configuration information for the specified SMARTCARD module.
02966   * @retval None
02967   */
02968 static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard)
02969 {
02970   /* Check that a Rx process is ongoing */
02971   if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
02972   {
02973     *hsmartcard->pRxBuffPtr = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF);
02974     hsmartcard->pRxBuffPtr++;
02975
02976     hsmartcard->RxXferCount--;
02977     if (hsmartcard->RxXferCount == 0U)
02978     {
02979       CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
02980
02981       /* Check if a transmit process is ongoing or not. If not disable ERR IT */
02982       if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
02983       {
02984         /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
02985         CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
02986       }
02987
02988       /* Disable the SMARTCARD Parity Error Interrupt */
02989       CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
02990
02991       hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
02992
02993       /* Clear RxISR function pointer */
02994       hsmartcard->RxISR = NULL;
02995
02996 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
02997       /* Call registered Rx complete callback */
02998       hsmartcard->RxCpltCallback(hsmartcard);
02999 #else
03000       /* Call legacy weak Rx complete callback */
03001       HAL_SMARTCARD_RxCpltCallback(hsmartcard);
03002 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
03003     }
03004   }
03005   else
03006   {
03007     /* Clear RXNE interrupt flag */
03008     __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST);
03009   }
03010 }
03011
03012 /**
03013   * @brief  Receive an amount of data in non-blocking mode.
03014   * @note   Function called under interruption only, once
03015   *         interruptions have been enabled by HAL_SMARTCARD_Receive_IT()
03016   *         and when the FIFO mode is enabled.
03017   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
03018   *                    the configuration information for the specified SMARTCARD module.
03019   * @retval None
03020   */
03021 static void SMARTCARD_RxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard)
03022 {
03023   uint16_t   nb_rx_data;
03024   uint16_t rxdatacount;
03025
03026   /* Check that a Rx process is ongoing */
03027   if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
03028   {
03029     for (nb_rx_data = hsmartcard->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)
03030     {
03031       *hsmartcard->pRxBuffPtr = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF);
03032       hsmartcard->pRxBuffPtr++;
03033
03034       hsmartcard->RxXferCount--;
03035       if (hsmartcard->RxXferCount == 0U)
03036       {
03037         CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
03038
03039         /* Check if a transmit process is ongoing or not. If not disable ERR IT */
03040         if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
03041         {
03042           /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
03043           CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
03044         }
03045
03046         /* Disable the SMARTCARD Parity Error Interrupt */
03047         CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
03048
03049         hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
03050
03051         /* Clear RxISR function pointer */
03052         hsmartcard->RxISR = NULL;
03053
03054 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
03055         /* Call registered Rx complete callback */
03056         hsmartcard->RxCpltCallback(hsmartcard);
03057 #else
03058         /* Call legacy weak Rx complete callback */
03059         HAL_SMARTCARD_RxCpltCallback(hsmartcard);
03060 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
03061       }
03062     }
03063
03064     /* When remaining number of bytes to receive is less than the RX FIFO
03065     threshold, next incoming frames are processed as if FIFO mode was
03066     disabled (i.e. one interrupt per received frame).
03067     */
03068     rxdatacount = hsmartcard->RxXferCount;
03069     if (((rxdatacount != 0U)) && (rxdatacount < hsmartcard->NbRxDataToProcess))
03070     {
03071       /* Disable the UART RXFT interrupt*/
03072       CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTIE);
03073
03074       /* Update the RxISR function pointer */
03075       hsmartcard->RxISR = SMARTCARD_RxISR;
03076
03077       /* Enable the UART Data Register Not Empty interrupt */
03078       SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
03079     }
03080   }
03081   else
03082   {
03083     /* Clear RXNE interrupt flag */
03084     __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST);
03085   }
03086 }
03087
03088 /**
03089   * @}
03090   */
03091
03092 #endif /* HAL_SMARTCARD_MODULE_ENABLED */
03093 /**
03094   * @}
03095   */
03096
03097 /**
03098   * @}
03099   */
03100
03101 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:35 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_smartcard.h Source File

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stm32wbxx_hal_smartcard.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_smartcard.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SMARTCARD HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_SMARTCARD_H
00022 #define STM32WBxx_HAL_SMARTCARD_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 /** @addtogroup STM32WBxx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup SMARTCARD
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief SMARTCARD Init Structure definition
00046   */
00047 typedef struct
00048 {
00049   uint32_t BaudRate;                  /*!< Configures the SmartCard communication baud rate.
00050                                            The baud rate register is computed using the following formula:
00051                                               Baud Rate Register = ((usart_ker_ckpres) / ((hsmartcard->Init.BaudRate)))
00052                                            where usart_ker_ckpres is the USART input clock divided by a prescaler */
00053
00054   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
00055                                            This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */
00056
00057   uint32_t StopBits;                  /*!< Specifies the number of stop bits.
00058                                            This parameter can be a value of @ref SMARTCARD_Stop_Bits. */
00059
00060   uint16_t Parity;                    /*!< Specifies the parity mode.
00061                                            This parameter can be a value of @ref SMARTCARD_Parity
00062                                            @note The parity is enabled by default (PCE is forced to 1).
00063                                                  Since the WordLength is forced to 8 bits + parity, M is
00064                                                  forced to 1 and the parity bit is the 9th bit. */
00065
00066   uint16_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
00067                                            This parameter can be a value of @ref SMARTCARD_Mode */
00068
00069   uint16_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.
00070                                            This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
00071
00072   uint16_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.
00073                                            This parameter can be a value of @ref SMARTCARD_Clock_Phase */
00074
00075   uint16_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
00076                                            data bit (MSB) has to be output on the SCLK pin in synchronous mode.
00077                                            This parameter can be a value of @ref SMARTCARD_Last_Bit */
00078
00079   uint16_t OneBitSampling;            /*!< Specifies whether a single sample or three samples' majority vote is selected.
00080                                            Selecting the single sample method increases the receiver tolerance to clock
00081                                            deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */
00082
00083   uint8_t  Prescaler;                 /*!< Specifies the SmartCard Prescaler.
00084                                            This parameter can be any value from 0x01 to 0x1F. Prescaler value is multiplied
00085                                            by 2 to give the division factor of the source clock frequency */
00086
00087   uint8_t  GuardTime;                 /*!< Specifies the SmartCard Guard Time applied after stop bits. */
00088
00089   uint16_t NACKEnable;                /*!< Specifies whether the SmartCard NACK transmission is enabled
00090                                            in case of parity error.
00091                                            This parameter can be a value of @ref SMARTCARD_NACK_Enable */
00092
00093   uint32_t TimeOutEnable;             /*!< Specifies whether the receiver timeout is enabled.
00094                                             This parameter can be a value of @ref SMARTCARD_Timeout_Enable*/
00095
00096   uint32_t TimeOutValue;              /*!< Specifies the receiver time out value in number of baud blocks:
00097                                            it is used to implement the Character Wait Time (CWT) and
00098                                            Block Wait Time (BWT). It is coded over 24 bits. */
00099
00100   uint8_t BlockLength;                /*!< Specifies the SmartCard Block Length in T=1 Reception mode.
00101                                            This parameter can be any value from 0x0 to 0xFF */
00102
00103   uint8_t AutoRetryCount;             /*!< Specifies the SmartCard auto-retry count (number of retries in
00104                                             receive and transmit mode). When set to 0, retransmission is
00105                                             disabled. Otherwise, its maximum value is 7 (before signalling
00106                                             an error) */
00107
00108   uint32_t ClockPrescaler;            /*!< Specifies the prescaler value used to divide the USART clock source.
00109                                            This parameter can be a value of @ref SMARTCARD_ClockPrescaler. */
00110
00111 } SMARTCARD_InitTypeDef;
00112
00113 /**
00114   * @brief  SMARTCARD advanced features initalization structure definition
00115   */
00116 typedef struct
00117 {
00118   uint32_t AdvFeatureInit;            /*!< Specifies which advanced SMARTCARD features is initialized. Several
00119                                            advanced features may be initialized at the same time. This parameter
00120                                            can be a value of @ref SMARTCARDEx_Advanced_Features_Initialization_Type */
00121
00122   uint32_t TxPinLevelInvert;          /*!< Specifies whether the TX pin active level is inverted.
00123                                            This parameter can be a value of @ref SMARTCARD_Tx_Inv  */
00124
00125   uint32_t RxPinLevelInvert;          /*!< Specifies whether the RX pin active level is inverted.
00126                                            This parameter can be a value of @ref SMARTCARD_Rx_Inv  */
00127
00128   uint32_t DataInvert;                /*!< Specifies whether data are inverted (positive/direct logic
00129                                            vs negative/inverted logic).
00130                                            This parameter can be a value of @ref SMARTCARD_Data_Inv */
00131
00132   uint32_t Swap;                      /*!< Specifies whether TX and RX pins are swapped.
00133                                            This parameter can be a value of @ref SMARTCARD_Rx_Tx_Swap */
00134
00135   uint32_t OverrunDisable;            /*!< Specifies whether the reception overrun detection is disabled.
00136                                            This parameter can be a value of @ref SMARTCARD_Overrun_Disable */
00137
00138   uint32_t DMADisableonRxError;       /*!< Specifies whether the DMA is disabled in case of reception error.
00139                                            This parameter can be a value of @ref SMARTCARD_DMA_Disable_on_Rx_Error */
00140
00141   uint32_t MSBFirst;                  /*!< Specifies whether MSB is sent first on UART line.
00142                                            This parameter can be a value of @ref SMARTCARD_MSB_First */
00143
00144   uint16_t TxCompletionIndication;     /*!< Specifies which transmission completion indication is used: before (when
00145                                             relevant flag is available) or once guard time period has elapsed.
00146                                            This parameter can be a value of @ref SMARTCARDEx_Transmission_Completion_Indication. */
00147 } SMARTCARD_AdvFeatureInitTypeDef;
00148
00149 /**
00150   * @brief HAL SMARTCARD State definition
00151   * @note  HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState (see @ref SMARTCARD_State_Definition).
00152   *        - gState contains SMARTCARD state information related to global Handle management
00153   *          and also information related to Tx operations.
00154   *          gState value coding follow below described bitmap :
00155   *          b7-b6  Error information
00156   *             00 : No Error
00157   *             01 : (Not Used)
00158   *             10 : Timeout
00159   *             11 : Error
00160   *          b5     IP initilisation status
00161   *             0  : Reset (IP not initialized)
00162   *             1  : Init done (IP not initialized. HAL SMARTCARD Init function already called)
00163   *          b4-b3  (not used)
00164   *             xx : Should be set to 00
00165   *          b2     Intrinsic process state
00166   *             0  : Ready
00167   *             1  : Busy (IP busy with some configuration or internal operations)
00168   *          b1     (not used)
00169   *             x  : Should be set to 0
00170   *          b0     Tx state
00171   *             0  : Ready (no Tx operation ongoing)
00172   *             1  : Busy (Tx operation ongoing)
00173   *        - RxState contains information related to Rx operations.
00174   *          RxState value coding follow below described bitmap :
00175   *          b7-b6  (not used)
00176   *             xx : Should be set to 00
00177   *          b5     IP initilisation status
00178   *             0  : Reset (IP not initialized)
00179   *             1  : Init done (IP not initialized)
00180   *          b4-b2  (not used)
00181   *            xxx : Should be set to 000
00182   *          b1     Rx state
00183   *             0  : Ready (no Rx operation ongoing)
00184   *             1  : Busy (Rx operation ongoing)
00185   *          b0     (not used)
00186   *             x  : Should be set to 0.
00187   */
00188 typedef uint32_t HAL_SMARTCARD_StateTypeDef;
00189
00190 /**
00191   * @brief  SMARTCARD handle Structure definition
00192   */
00193 typedef struct __SMARTCARD_HandleTypeDef
00194 {
00195   USART_TypeDef                     *Instance;             /*!< USART registers base address                          */
00196
00197   SMARTCARD_InitTypeDef             Init;                  /*!< SmartCard communication parameters                    */
00198
00199   SMARTCARD_AdvFeatureInitTypeDef   AdvancedInit;          /*!< SmartCard advanced features initialization parameters */
00200
00201   uint8_t                           *pTxBuffPtr;           /*!< Pointer to SmartCard Tx transfer Buffer               */
00202
00203   uint16_t                          TxXferSize;            /*!< SmartCard Tx Transfer size                            */
00204
00205   __IO uint16_t                     TxXferCount;           /*!< SmartCard Tx Transfer Counter                         */
00206
00207   uint8_t                           *pRxBuffPtr;           /*!< Pointer to SmartCard Rx transfer Buffer               */
00208
00209   uint16_t                          RxXferSize;            /*!< SmartCard Rx Transfer size                            */
00210
00211   __IO uint16_t                     RxXferCount;           /*!< SmartCard Rx Transfer Counter                         */
00212
00213   uint16_t                          NbRxDataToProcess;     /*!< Number of data to process during RX ISR execution     */
00214
00215   uint16_t                          NbTxDataToProcess;     /*!< Number of data to process during TX ISR execution     */
00216
00217   uint32_t                          FifoMode;              /*!< Specifies if the FIFO mode will be used.
00218                                                                 This parameter can be a value of @ref SMARTCARDEx_FIFO_mode. */
00219
00220   void (*RxISR)(struct __SMARTCARD_HandleTypeDef *huart);  /*!< Function pointer on Rx IRQ handler                    */
00221
00222   void (*TxISR)(struct __SMARTCARD_HandleTypeDef *huart);  /*!< Function pointer on Tx IRQ handler                    */
00223
00224   DMA_HandleTypeDef                 *hdmatx;               /*!< SmartCard Tx DMA Handle parameters                    */
00225
00226   DMA_HandleTypeDef                 *hdmarx;               /*!< SmartCard Rx DMA Handle parameters                    */
00227
00228   HAL_LockTypeDef                   Lock;                  /*!< Locking object                                        */
00229
00230   __IO HAL_SMARTCARD_StateTypeDef   gState;                /*!< SmartCard state information related to global Handle management
00231                                                                 and also related to Tx operations.
00232                                                                 This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
00233
00234   __IO HAL_SMARTCARD_StateTypeDef   RxState;               /*!< SmartCard state information related to Rx operations.
00235                                                                 This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
00236
00237   uint32_t                          ErrorCode;             /*!< SmartCard Error code                                  */
00238
00239 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
00240   void (* TxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);            /*!< SMARTCARD Tx Complete Callback             */
00241
00242   void (* RxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);            /*!< SMARTCARD Rx Complete Callback             */
00243
00244   void (* ErrorCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);             /*!< SMARTCARD Error Callback                   */
00245
00246   void (* AbortCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);         /*!< SMARTCARD Abort Complete Callback          */
00247
00248   void (* AbortTransmitCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Transmit Complete Callback */
00249
00250   void (* AbortReceiveCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);  /*!< SMARTCARD Abort Receive Complete Callback  */
00251
00252   void (* RxFifoFullCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);        /*!< SMARTCARD Rx Fifo Full Callback            */
00253
00254   void (* TxFifoEmptyCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);       /*!< SMARTCARD Tx Fifo Empty Callback           */
00255
00256
00257   void (* MspInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);           /*!< SMARTCARD Msp Init callback                */
00258
00259   void (* MspDeInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);         /*!< SMARTCARD Msp DeInit callback              */
00260 #endif  /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
00261
00262 } SMARTCARD_HandleTypeDef;
00263
00264 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
00265 /**
00266   * @brief  HAL SMARTCARD Callback ID enumeration definition
00267   */
00268 typedef enum
00269 {
00270   HAL_SMARTCARD_TX_COMPLETE_CB_ID             = 0x00U,    /*!< SMARTCARD Tx Complete Callback ID             */
00271   HAL_SMARTCARD_RX_COMPLETE_CB_ID             = 0x01U,    /*!< SMARTCARD Rx Complete Callback ID             */
00272   HAL_SMARTCARD_ERROR_CB_ID                   = 0x02U,    /*!< SMARTCARD Error Callback ID                   */
00273   HAL_SMARTCARD_ABORT_COMPLETE_CB_ID          = 0x03U,    /*!< SMARTCARD Abort Complete Callback ID          */
00274   HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x04U,    /*!< SMARTCARD Abort Transmit Complete Callback ID */
00275   HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x05U,    /*!< SMARTCARD Abort Receive Complete Callback ID  */
00276   HAL_SMARTCARD_RX_FIFO_FULL_CB_ID            = 0x06U,    /*!< SMARTCARD Rx Fifo Full Callback ID            */
00277   HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID           = 0x07U,    /*!< SMARTCARD Tx Fifo Empty Callback ID           */
00278
00279   HAL_SMARTCARD_MSPINIT_CB_ID                 = 0x08U,    /*!< SMARTCARD MspInit callback ID                 */
00280   HAL_SMARTCARD_MSPDEINIT_CB_ID               = 0x09U     /*!< SMARTCARD MspDeInit callback ID               */
00281
00282 } HAL_SMARTCARD_CallbackIDTypeDef;
00283
00284 /**
00285   * @brief  HAL SMARTCARD Callback pointer definition
00286   */
00287 typedef  void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsmartcard);  /*!< pointer to an SMARTCARD callback function */
00288
00289 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
00290
00291 /**
00292   * @brief  SMARTCARD clock sources
00293   */
00294 typedef enum
00295 {
00296   SMARTCARD_CLOCKSOURCE_PCLK2     = 0x01, /*!< PCLK2 clock source         */
00297   SMARTCARD_CLOCKSOURCE_HSI       = 0x02, /*!< HSI clock source           */
00298   SMARTCARD_CLOCKSOURCE_SYSCLK    = 0x04, /*!< SYSCLK clock source        */
00299   SMARTCARD_CLOCKSOURCE_LSE       = 0x08, /*!< LSE clock source           */
00300   SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10  /*!< undefined clock source     */
00301 } SMARTCARD_ClockSourceTypeDef;
00302
00303 /**
00304   * @}
00305   */
00306
00307 /* Exported constants --------------------------------------------------------*/
00308 /** @defgroup SMARTCARD_Exported_Constants  SMARTCARD Exported Constants
00309   * @{
00310   */
00311
00312 /** @defgroup SMARTCARD_State_Definition SMARTCARD State Code Definition
00313   * @{
00314   */
00315 #define HAL_SMARTCARD_STATE_RESET            0x00000000U                     /*!< Peripheral is not initialized
00316                                                                                   Value is allowed for gState and RxState */
00317 #define HAL_SMARTCARD_STATE_READY            0x00000020U                     /*!< Peripheral Initialized and ready for use
00318                                                                                   Value is allowed for gState and RxState */
00319 #define HAL_SMARTCARD_STATE_BUSY             0x00000024U                     /*!< an internal process is ongoing
00320                                                                                   Value is allowed for gState only */
00321 #define HAL_SMARTCARD_STATE_BUSY_TX          0x00000021U                     /*!< Data Transmission process is ongoing
00322                                                                                   Value is allowed for gState only */
00323 #define HAL_SMARTCARD_STATE_BUSY_RX          0x00000022U                     /*!< Data Reception process is ongoing
00324                                                                                   Value is allowed for RxState only */
00325 #define HAL_SMARTCARD_STATE_BUSY_TX_RX       0x00000023U                     /*!< Data Transmission and Reception process is ongoing
00326                                                                                   Not to be used for neither gState nor RxState.
00327                                                                                   Value is result of combination (Or) between gState and RxState values */
00328 #define HAL_SMARTCARD_STATE_TIMEOUT          0x000000A0U                     /*!< Timeout state
00329                                                                                   Value is allowed for gState only */
00330 #define HAL_SMARTCARD_STATE_ERROR            0x000000E0U                     /*!< Error
00331                                                                                   Value is allowed for gState only */
00332 /**
00333   * @}
00334   */
00335
00336 /** @defgroup SMARTCARD_Error_Definition SMARTCARD Error Code Definition
00337   * @{
00338   */
00339 #define HAL_SMARTCARD_ERROR_NONE             ((uint32_t)0x00000000U)         /*!< No error                */
00340 #define HAL_SMARTCARD_ERROR_PE               ((uint32_t)0x00000001U)         /*!< Parity error            */
00341 #define HAL_SMARTCARD_ERROR_NE               ((uint32_t)0x00000002U)         /*!< Noise error             */
00342 #define HAL_SMARTCARD_ERROR_FE               ((uint32_t)0x00000004U)         /*!< frame error             */
00343 #define HAL_SMARTCARD_ERROR_ORE              ((uint32_t)0x00000008U)         /*!< Overrun error           */
00344 #define HAL_SMARTCARD_ERROR_DMA              ((uint32_t)0x00000010U)         /*!< DMA transfer error      */
00345 #define HAL_SMARTCARD_ERROR_RTO              ((uint32_t)0x00000020U)         /*!< Receiver TimeOut error  */
00346 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
00347 #define HAL_SMARTCARD_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U)         /*!< Invalid Callback error  */
00348 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
00349 /**
00350   * @}
00351   */
00352
00353 /** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
00354   * @{
00355   */
00356 #define SMARTCARD_WORDLENGTH_9B             USART_CR1_M0                    /*!< SMARTCARD frame length */
00357 /**
00358   * @}
00359   */
00360
00361 /** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
00362   * @{
00363   */
00364 #define SMARTCARD_STOPBITS_0_5              USART_CR2_STOP_0                /*!< SMARTCARD frame with 0.5 stop bit  */
00365 #define SMARTCARD_STOPBITS_1_5              USART_CR2_STOP                  /*!< SMARTCARD frame with 1.5 stop bits */
00366 /**
00367   * @}
00368   */
00369
00370 /** @defgroup SMARTCARD_Parity SMARTCARD Parity
00371   * @{
00372   */
00373 #define SMARTCARD_PARITY_EVEN               USART_CR1_PCE                   /*!< SMARTCARD frame even parity */
00374 #define SMARTCARD_PARITY_ODD                (USART_CR1_PCE | USART_CR1_PS)  /*!< SMARTCARD frame odd parity  */
00375 /**
00376   * @}
00377   */
00378
00379 /** @defgroup SMARTCARD_Mode SMARTCARD Transfer Mode
00380   * @{
00381   */
00382 #define SMARTCARD_MODE_RX                   USART_CR1_RE                    /*!< SMARTCARD RX mode        */
00383 #define SMARTCARD_MODE_TX                   USART_CR1_TE                    /*!< SMARTCARD TX mode        */
00384 #define SMARTCARD_MODE_TX_RX                (USART_CR1_TE |USART_CR1_RE)    /*!< SMARTCARD RX and TX mode */
00385 /**
00386   * @}
00387   */
00388
00389 /** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
00390   * @{
00391   */
00392 #define SMARTCARD_POLARITY_LOW              0x00000000U                     /*!< SMARTCARD frame low polarity  */
00393 #define SMARTCARD_POLARITY_HIGH             USART_CR2_CPOL                  /*!< SMARTCARD frame high polarity */
00394 /**
00395   * @}
00396   */
00397
00398 /** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
00399   * @{
00400   */
00401 #define SMARTCARD_PHASE_1EDGE               0x00000000U                     /*!< SMARTCARD frame phase on first clock transition  */
00402 #define SMARTCARD_PHASE_2EDGE               USART_CR2_CPHA                  /*!< SMARTCARD frame phase on second clock transition */
00403 /**
00404   * @}
00405   */
00406
00407 /** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
00408   * @{
00409   */
00410 #define SMARTCARD_LASTBIT_DISABLE           0x00000000U                     /*!< SMARTCARD frame last data bit clock pulse not output to SCLK pin */
00411 #define SMARTCARD_LASTBIT_ENABLE            USART_CR2_LBCL                  /*!< SMARTCARD frame last data bit clock pulse output to SCLK pin     */
00412 /**
00413   * @}
00414   */
00415
00416 /** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD One Bit Sampling Method
00417   * @{
00418   */
00419 #define SMARTCARD_ONE_BIT_SAMPLE_DISABLE    0x00000000U                     /*!< SMARTCARD frame one-bit sample disabled */
00420 #define SMARTCARD_ONE_BIT_SAMPLE_ENABLE     USART_CR3_ONEBIT                /*!< SMARTCARD frame one-bit sample enabled  */
00421 /**
00422   * @}
00423   */
00424
00425
00426 /** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable
00427   * @{
00428   */
00429 #define SMARTCARD_NACK_DISABLE              0x00000000U                     /*!< SMARTCARD NACK transmission disabled  */
00430 #define SMARTCARD_NACK_ENABLE               USART_CR3_NACK                  /*!< SMARTCARD NACK transmission enabled */
00431 /**
00432   * @}
00433   */
00434
00435 /** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable
00436   * @{
00437   */
00438 #define SMARTCARD_TIMEOUT_DISABLE           0x00000000U                     /*!< SMARTCARD receiver timeout disabled */
00439 #define SMARTCARD_TIMEOUT_ENABLE            USART_CR2_RTOEN                 /*!< SMARTCARD receiver timeout enabled  */
00440 /**
00441   * @}
00442   */
00443
00444 /** @defgroup SMARTCARD_ClockPrescaler  Clock Prescaler
00445   * @{
00446   */
00447 #define SMARTCARD_PRESCALER_DIV1    0x00000000U  /*!< fclk_pres = fclk     */
00448 #define SMARTCARD_PRESCALER_DIV2    0x00000001U  /*!< fclk_pres = fclk/2   */
00449 #define SMARTCARD_PRESCALER_DIV4    0x00000002U  /*!< fclk_pres = fclk/4   */
00450 #define SMARTCARD_PRESCALER_DIV6    0x00000003U  /*!< fclk_pres = fclk/6   */
00451 #define SMARTCARD_PRESCALER_DIV8    0x00000004U  /*!< fclk_pres = fclk/8   */
00452 #define SMARTCARD_PRESCALER_DIV10   0x00000005U  /*!< fclk_pres = fclk/10  */
00453 #define SMARTCARD_PRESCALER_DIV12   0x00000006U  /*!< fclk_pres = fclk/12  */
00454 #define SMARTCARD_PRESCALER_DIV16   0x00000007U  /*!< fclk_pres = fclk/16  */
00455 #define SMARTCARD_PRESCALER_DIV32   0x00000008U  /*!< fclk_pres = fclk/32  */
00456 #define SMARTCARD_PRESCALER_DIV64   0x00000009U  /*!< fclk_pres = fclk/64  */
00457 #define SMARTCARD_PRESCALER_DIV128  0x0000000AU  /*!< fclk_pres = fclk/128 */
00458 #define SMARTCARD_PRESCALER_DIV256  0x0000000BU  /*!< fclk_pres = fclk/256 */
00459
00460 /**
00461   * @}
00462   */
00463
00464 /** @defgroup SMARTCARD_Tx_Inv SMARTCARD advanced feature TX pin active level inversion
00465   * @{
00466   */
00467 #define SMARTCARD_ADVFEATURE_TXINV_DISABLE  0x00000000U                  /*!< TX pin active level inversion disable */
00468 #define SMARTCARD_ADVFEATURE_TXINV_ENABLE   USART_CR2_TXINV              /*!< TX pin active level inversion enable  */
00469 /**
00470   * @}
00471   */
00472
00473 /** @defgroup SMARTCARD_Rx_Inv SMARTCARD advanced feature RX pin active level inversion
00474   * @{
00475   */
00476 #define SMARTCARD_ADVFEATURE_RXINV_DISABLE  0x00000000U                  /*!< RX pin active level inversion disable */
00477 #define SMARTCARD_ADVFEATURE_RXINV_ENABLE   USART_CR2_RXINV              /*!< RX pin active level inversion enable  */
00478 /**
00479   * @}
00480   */
00481
00482 /** @defgroup SMARTCARD_Data_Inv SMARTCARD advanced feature Binary Data inversion
00483   * @{
00484   */
00485 #define SMARTCARD_ADVFEATURE_DATAINV_DISABLE  0x00000000U                /*!< Binary data inversion disable */
00486 #define SMARTCARD_ADVFEATURE_DATAINV_ENABLE   USART_CR2_DATAINV          /*!< Binary data inversion enable  */
00487 /**
00488   * @}
00489   */
00490
00491 /** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD advanced feature RX TX pins swap
00492   * @{
00493   */
00494 #define SMARTCARD_ADVFEATURE_SWAP_DISABLE   0x00000000U                  /*!< TX/RX pins swap disable */
00495 #define SMARTCARD_ADVFEATURE_SWAP_ENABLE    USART_CR2_SWAP               /*!< TX/RX pins swap enable  */
00496 /**
00497   * @}
00498   */
00499
00500 /** @defgroup SMARTCARD_Overrun_Disable SMARTCARD advanced feature Overrun Disable
00501   * @{
00502   */
00503 #define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE   0x00000000U                /*!< RX overrun enable  */
00504 #define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE  USART_CR3_OVRDIS           /*!< RX overrun disable */
00505 /**
00506   * @}
00507   */
00508
00509 /** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD advanced feature DMA Disable on Rx Error
00510   * @{
00511   */
00512 #define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR   0x00000000U           /*!< DMA enable on Reception Error  */
00513 #define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR  USART_CR3_DDRE        /*!< DMA disable on Reception Error */
00514 /**
00515   * @}
00516   */
00517
00518 /** @defgroup SMARTCARD_MSB_First   SMARTCARD advanced feature MSB first
00519   * @{
00520   */
00521 #define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE      0x00000000U           /*!< Most significant bit sent/received first disable */
00522 #define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE       USART_CR2_MSBFIRST    /*!< Most significant bit sent/received first enable  */
00523 /**
00524   * @}
00525   */
00526
00527 /** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters
00528   * @{
00529   */
00530 #define SMARTCARD_RXDATA_FLUSH_REQUEST      USART_RQR_RXFRQ              /*!< Receive data flush request */
00531 #define SMARTCARD_TXDATA_FLUSH_REQUEST      USART_RQR_TXFRQ              /*!< Transmit data flush request */
00532 /**
00533   * @}
00534   */
00535
00536 /** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flags mask
00537   * @{
00538   */
00539 #define SMARTCARD_IT_MASK                   0x001FU   /*!< SMARTCARD interruptions flags mask  */
00540 #define SMARTCARD_CR_MASK                   0x00E0U   /*!< SMARTCARD control register mask     */
00541 #define SMARTCARD_CR_POS                    5U        /*!< SMARTCARD control register position */
00542 #define SMARTCARD_ISR_MASK                  0x1F00U   /*!< SMARTCARD ISR register mask         */
00543 #define SMARTCARD_ISR_POS                   8U        /*!< SMARTCARD ISR register position     */
00544 /**
00545   * @}
00546   */
00547
00548 /**
00549   * @}
00550   */
00551
00552 /* Exported macros -----------------------------------------------------------*/
00553 /** @defgroup SMARTCARD_Exported_Macros  SMARTCARD Exported Macros
00554   * @{
00555   */
00556
00557 /** @brief  Reset SMARTCARD handle states.
00558   * @param  __HANDLE__ SMARTCARD handle.
00559   * @retval None
00560   */
00561 #if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
00562 #define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)  do{                                                       \
00563                                                            (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;      \
00564                                                            (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;     \
00565                                                            (__HANDLE__)->MspInitCallback = NULL;                  \
00566                                                            (__HANDLE__)->MspDeInitCallback = NULL;                \
00567                                                           } while(0U)
00568 #else
00569 #define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)  do{                                                       \
00570                                                            (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;      \
00571                                                            (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;     \
00572                                                           } while(0U)
00573 #endif /*USE_HAL_SMARTCARD_REGISTER_CALLBACKS  */
00574
00575 /** @brief  Flush the Smartcard Data registers.
00576   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00577   * @retval None
00578   */
00579 #define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__)                                 \
00580     do{                                                                              \
00581       SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
00582       SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
00583       } while(0U)
00584
00585 /** @brief  Clear the specified SMARTCARD pending flag.
00586   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00587   * @param  __FLAG__ specifies the flag to check.
00588   *          This parameter can be any combination of the following values:
00589   *            @arg @ref SMARTCARD_CLEAR_PEF    Parity error clear flag
00590   *            @arg @ref SMARTCARD_CLEAR_FEF    Framing error clear flag
00591   *            @arg @ref SMARTCARD_CLEAR_NEF    Noise detected clear flag
00592   *            @arg @ref SMARTCARD_CLEAR_OREF   OverRun error clear flag
00593   *            @arg @ref SMARTCARD_CLEAR_IDLEF  Idle line detected clear flag
00594   *            @arg @ref SMARTCARD_CLEAR_TCF    Transmission complete clear flag
00595   *            @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag
00596   *            @arg @ref SMARTCARD_CLEAR_RTOF   Receiver timeout clear flag
00597   *            @arg @ref SMARTCARD_CLEAR_EOBF   End of block clear flag
00598   *            @arg @ref SMARTCARD_CLEAR_TXFECF TXFIFO empty Clear flag
00599   * @retval None
00600   */
00601 #define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00602
00603 /** @brief  Clear the SMARTCARD PE pending flag.
00604   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00605   * @retval None
00606   */
00607 #define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
00608
00609
00610 /** @brief  Clear the SMARTCARD FE pending flag.
00611   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00612   * @retval None
00613   */
00614 #define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)
00615
00616 /** @brief  Clear the SMARTCARD NE pending flag.
00617   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00618   * @retval None
00619   */
00620 #define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)
00621
00622 /** @brief  Clear the SMARTCARD ORE pending flag.
00623   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00624   * @retval None
00625   */
00626 #define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)
00627
00628 /** @brief  Clear the SMARTCARD IDLE pending flag.
00629   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00630   * @retval None
00631   */
00632 #define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
00633
00634 /** @brief  Check whether the specified Smartcard flag is set or not.
00635   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00636   * @param  __FLAG__ specifies the flag to check.
00637   *        This parameter can be one of the following values:
00638   *            @arg @ref SMARTCARD_FLAG_TCBGT Transmission complete before guard time flag (when flag available)
00639   *            @arg @ref SMARTCARD_FLAG_REACK Receive enable acknowledge flag
00640   *            @arg @ref SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag
00641   *            @arg @ref SMARTCARD_FLAG_BUSY  Busy flag
00642   *            @arg @ref SMARTCARD_FLAG_EOBF  End of block flag
00643   *            @arg @ref SMARTCARD_FLAG_RTOF  Receiver timeout flag
00644   *            @arg @ref SMARTCARD_FLAG_TXE   Transmit data register empty flag
00645   *            @arg @ref SMARTCARD_FLAG_TXFNF TXFIFO not full flag
00646   *            @arg @ref SMARTCARD_FLAG_TC    Transmission complete flag
00647   *            @arg @ref SMARTCARD_FLAG_RXNE  Receive data register not empty flag
00648   *            @arg @ref SMARTCARD_FLAG_RXFNE RXFIFO not empty flag
00649   *            @arg @ref SMARTCARD_FLAG_IDLE  Idle line detection flag
00650   *            @arg @ref SMARTCARD_FLAG_ORE   Overrun error flag
00651   *            @arg @ref SMARTCARD_FLAG_NE    Noise error flag
00652   *            @arg @ref SMARTCARD_FLAG_FE    Framing error flag
00653   *            @arg @ref SMARTCARD_FLAG_PE    Parity error flag
00654   *            @arg @ref SMARTCARD_FLAG_TXFE  TXFIFO Empty flag
00655   *            @arg @ref SMARTCARD_FLAG_RXFF  RXFIFO Full flag
00656   *            @arg @ref SMARTCARD_FLAG_RXFT  SMARTCARD RXFIFO threshold flag
00657   *            @arg @ref SMARTCARD_FLAG_TXFT  SMARTCARD TXFIFO threshold flag
00658   * @retval The new state of __FLAG__ (TRUE or FALSE).
00659   */
00660 #define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
00661
00662 /** @brief  Enable the specified SmartCard interrupt.
00663   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00664   * @param  __INTERRUPT__ specifies the SMARTCARD interrupt to enable.
00665   *          This parameter can be one of the following values:
00666   *            @arg @ref SMARTCARD_IT_EOB    End of block interrupt
00667   *            @arg @ref SMARTCARD_IT_RTO    Receive timeout interrupt
00668   *            @arg @ref SMARTCARD_IT_TXE    Transmit data register empty interrupt
00669   *            @arg @ref SMARTCARD_IT_TXFNF  TX FIFO not full interruption
00670   *            @arg @ref SMARTCARD_IT_TC     Transmission complete interrupt
00671   *            @arg @ref SMARTCARD_IT_TCBGT  Transmission complete before guard time interrupt (when interruption available)
00672   *            @arg @ref SMARTCARD_IT_RXNE   Receive data register not empty interrupt
00673   *            @arg @ref SMARTCARD_IT_RXFNE  RXFIFO not empty interruption
00674   *            @arg @ref SMARTCARD_IT_IDLE   Idle line detection interrupt
00675   *            @arg @ref SMARTCARD_IT_PE     Parity error interrupt
00676   *            @arg @ref SMARTCARD_IT_ERR    Error interrupt(frame error, noise error, overrun error)
00677   *            @arg @ref SMARTCARD_IT_RXFF   RXFIFO full interruption
00678   *            @arg @ref SMARTCARD_IT_TXFE   TXFIFO empty interruption
00679   *            @arg @ref SMARTCARD_IT_RXFT   RXFIFO threshold reached interruption
00680   *            @arg @ref SMARTCARD_IT_TXFT   TXFIFO threshold reached interruption
00681   * @retval None
00682   */
00683 #define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
00684                                                                 ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
00685                                                                 ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
00686
00687 /** @brief  Disable the specified SmartCard interrupt.
00688   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00689   * @param  __INTERRUPT__ specifies the SMARTCARD interrupt to disable.
00690   *          This parameter can be one of the following values:
00691   *            @arg @ref SMARTCARD_IT_EOB    End of block interrupt
00692   *            @arg @ref SMARTCARD_IT_RTO    Receive timeout interrupt
00693   *            @arg @ref SMARTCARD_IT_TXE    Transmit data register empty interrupt
00694   *            @arg @ref SMARTCARD_IT_TXFNF  TX FIFO not full interruption
00695   *            @arg @ref SMARTCARD_IT_TC     Transmission complete interrupt
00696   *            @arg @ref SMARTCARD_IT_TCBGT  Transmission complete before guard time interrupt (when interruption available)
00697   *            @arg @ref SMARTCARD_IT_RXNE   Receive data register not empty interrupt
00698   *            @arg @ref SMARTCARD_IT_RXFNE  RXFIFO not empty interruption
00699   *            @arg @ref SMARTCARD_IT_IDLE   Idle line detection interrupt
00700   *            @arg @ref SMARTCARD_IT_PE     Parity error interrupt
00701   *            @arg @ref SMARTCARD_IT_ERR    Error interrupt(frame error, noise error, overrun error)
00702   *            @arg @ref SMARTCARD_IT_RXFF   RXFIFO full interruption
00703   *            @arg @ref SMARTCARD_IT_TXFE   TXFIFO empty interruption
00704   *            @arg @ref SMARTCARD_IT_RXFT   RXFIFO threshold reached interruption
00705   *            @arg @ref SMARTCARD_IT_TXFT   TXFIFO threshold reached interruption
00706   * @retval None
00707   */
00708 #define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
00709                                                                 ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
00710                                                                 ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
00711
00712
00713 /** @brief  Check whether the specified SmartCard interrupt has occurred or not.
00714   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00715   * @param  __INTERRUPT__ specifies the SMARTCARD interrupt to check.
00716   *          This parameter can be one of the following values:
00717   *            @arg @ref SMARTCARD_IT_EOB    End of block interrupt
00718   *            @arg @ref SMARTCARD_IT_RTO    Receive timeout interrupt
00719   *            @arg @ref SMARTCARD_IT_TXE    Transmit data register empty interrupt
00720   *            @arg @ref SMARTCARD_IT_TXFNF  TX FIFO not full interruption
00721   *            @arg @ref SMARTCARD_IT_TC     Transmission complete interrupt
00722   *            @arg @ref SMARTCARD_IT_TCBGT  Transmission complete before guard time interrupt (when interruption available)
00723   *            @arg @ref SMARTCARD_IT_RXNE   Receive data register not empty interrupt
00724   *            @arg @ref SMARTCARD_IT_RXFNE  RXFIFO not empty interruption
00725   *            @arg @ref SMARTCARD_IT_IDLE   Idle line detection interrupt
00726   *            @arg @ref SMARTCARD_IT_PE     Parity error interrupt
00727   *            @arg @ref SMARTCARD_IT_ERR    Error interrupt(frame error, noise error, overrun error)
00728   *            @arg @ref SMARTCARD_IT_RXFF   RXFIFO full interruption
00729   *            @arg @ref SMARTCARD_IT_TXFE   TXFIFO empty interruption
00730   *            @arg @ref SMARTCARD_IT_RXFT   RXFIFO threshold reached interruption
00731   *            @arg @ref SMARTCARD_IT_TXFT   TXFIFO threshold reached interruption
00732   * @retval The new state of __INTERRUPT__ (SET or RESET).
00733   */
00734 #define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET)
00735
00736 /** @brief  Check whether the specified SmartCard interrupt source is enabled or not.
00737   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00738   * @param  __INTERRUPT__ specifies the SMARTCARD interrupt source to check.
00739   *          This parameter can be one of the following values:
00740   *            @arg @ref SMARTCARD_IT_EOB    End of block interrupt
00741   *            @arg @ref SMARTCARD_IT_RTO    Receive timeout interrupt
00742   *            @arg @ref SMARTCARD_IT_TXE    Transmit data register empty interrupt
00743   *            @arg @ref SMARTCARD_IT_TXFNF  TX FIFO not full interruption
00744   *            @arg @ref SMARTCARD_IT_TC     Transmission complete interrupt
00745   *            @arg @ref SMARTCARD_IT_TCBGT  Transmission complete before guard time interrupt (when interruption available)
00746   *            @arg @ref SMARTCARD_IT_RXNE   Receive data register not empty interrupt
00747   *            @arg @ref SMARTCARD_IT_RXFNE  RXFIFO not empty interruption
00748   *            @arg @ref SMARTCARD_IT_IDLE   Idle line detection interrupt
00749   *            @arg @ref SMARTCARD_IT_PE     Parity error interrupt
00750   *            @arg @ref SMARTCARD_IT_ERR    Error interrupt(frame error, noise error, overrun error)
00751   *            @arg @ref SMARTCARD_IT_RXFF   RXFIFO full interruption
00752   *            @arg @ref SMARTCARD_IT_TXFE   TXFIFO empty interruption
00753   *            @arg @ref SMARTCARD_IT_RXFT   RXFIFO threshold reached interruption
00754   *            @arg @ref SMARTCARD_IT_TXFT   TXFIFO threshold reached interruption
00755   * @retval The new state of __INTERRUPT__ (SET or RESET).
00756   */
00757 #define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \
00758                                                                     (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
00759                                                                     (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK)))  != 0U) ? SET : RESET)
00760
00761
00762 /** @brief  Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
00763   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00764   * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
00765   *                       to clear the corresponding interrupt.
00766   *          This parameter can be one of the following values:
00767   *            @arg @ref SMARTCARD_CLEAR_PEF    Parity error clear flag
00768   *            @arg @ref SMARTCARD_CLEAR_FEF    Framing error clear flag
00769   *            @arg @ref SMARTCARD_CLEAR_NEF    Noise detected clear flag
00770   *            @arg @ref SMARTCARD_CLEAR_OREF   OverRun error clear flag
00771   *            @arg @ref SMARTCARD_CLEAR_IDLEF  Idle line detection clear flag
00772   *            @arg @ref SMARTCARD_CLEAR_TXFECF TXFIFO empty Clear Flag
00773   *            @arg @ref SMARTCARD_CLEAR_TCF    Transmission complete clear flag
00774   *            @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available)
00775   *            @arg @ref SMARTCARD_CLEAR_RTOF   Receiver timeout clear flag
00776   *            @arg @ref SMARTCARD_CLEAR_EOBF   End of block clear flag
00777   * @retval None
00778   */
00779 #define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))
00780
00781 /** @brief  Set a specific SMARTCARD request flag.
00782   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00783   * @param  __REQ__ specifies the request flag to set
00784   *          This parameter can be one of the following values:
00785   *            @arg @ref SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request
00786   *            @arg @ref SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request
00787   *
00788   * @retval None
00789   */
00790 #define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
00791
00792 /** @brief  Enable the SMARTCARD one bit sample method.
00793   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00794   * @retval None
00795   */
00796 #define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
00797
00798 /** @brief  Disable the SMARTCARD one bit sample method.
00799   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00800   * @retval None
00801   */
00802 #define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
00803
00804 /** @brief  Enable the USART associated to the SMARTCARD Handle.
00805   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00806   * @retval None
00807   */
00808 #define __HAL_SMARTCARD_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
00809
00810 /** @brief  Disable the USART associated to the SMARTCARD Handle
00811   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00812   * @retval None
00813   */
00814 #define __HAL_SMARTCARD_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
00815
00816 /**
00817   * @}
00818   */
00819
00820 /* Private macros -------------------------------------------------------------*/
00821 /** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
00822   * @{
00823   */
00824
00825 /** @brief  Report the SMARTCARD clock source.
00826   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00827   * @param  __CLOCKSOURCE__ output variable.
00828   * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
00829   */
00830 #define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)   \
00831   do {                                                         \
00832     if((__HANDLE__)->Instance == USART1)                       \
00833     {                                                          \
00834        switch(__HAL_RCC_GET_USART1_SOURCE())                   \
00835        {                                                       \
00836         case RCC_USART1CLKSOURCE_PCLK2:                        \
00837           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2;     \
00838           break;                                               \
00839         case RCC_USART1CLKSOURCE_HSI:                          \
00840           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
00841           break;                                               \
00842         case RCC_USART1CLKSOURCE_SYSCLK:                       \
00843           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;    \
00844           break;                                               \
00845         case RCC_USART1CLKSOURCE_LSE:                          \
00846           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
00847           break;                                               \
00848         default:                                               \
00849           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
00850           break;                                               \
00851        }                                                       \
00852     }                                                          \
00853     else                                                       \
00854     {                                                          \
00855       (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED;     \
00856     }                                                          \
00857   } while(0U)
00858
00859 /** @brief  Check the Baud rate range.
00860   * @note   The maximum Baud Rate is derived from the maximum clock on WB (64 MHz)
00861   *         divided by the oversampling used on the SMARTCARD (i.e. 16).
00862   * @param  __BAUDRATE__ Baud rate set by the configuration function.
00863   * @retval Test result (TRUE or FALSE)
00864   */
00865 #define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4000001U)
00866
00867 /** @brief  Check the block length range.
00868   * @note   The maximum SMARTCARD block length is 0xFF.
00869   * @param  __LENGTH__ block length.
00870   * @retval Test result (TRUE or FALSE)
00871   */
00872 #define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU)
00873
00874 /** @brief  Check the receiver timeout value.
00875   * @note   The maximum SMARTCARD receiver timeout value is 0xFFFFFF.
00876   * @param  __TIMEOUTVALUE__ receiver timeout value.
00877   * @retval Test result (TRUE or FALSE)
00878   */
00879 #define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__)    ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
00880
00881 /** @brief  Check the SMARTCARD autoretry counter value.
00882   * @note   The maximum number of retransmissions is 0x7.
00883   * @param  __COUNT__ number of retransmissions.
00884   * @retval Test result (TRUE or FALSE)
00885   */
00886 #define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__)         ((__COUNT__) <= 0x7U)
00887
00888 /**
00889   * @brief Ensure that SMARTCARD frame length is valid.
00890   * @param __LENGTH__ SMARTCARD frame length.
00891   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
00892   */
00893 #define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
00894
00895 /**
00896   * @brief Ensure that SMARTCARD frame number of stop bits is valid.
00897   * @param __STOPBITS__ SMARTCARD frame number of stop bits.
00898   * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
00899   */
00900 #define IS_SMARTCARD_STOPBITS(__STOPBITS__) (((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\
00901                                              ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5))
00902
00903 /**
00904   * @brief Ensure that SMARTCARD frame parity is valid.
00905   * @param __PARITY__ SMARTCARD frame parity.
00906   * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
00907   */
00908 #define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \
00909                                          ((__PARITY__) == SMARTCARD_PARITY_ODD))
00910
00911 /**
00912   * @brief Ensure that SMARTCARD communication mode is valid.
00913   * @param __MODE__ SMARTCARD communication mode.
00914   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00915   */
00916 #define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & 0xFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
00917
00918 /**
00919   * @brief Ensure that SMARTCARD frame polarity is valid.
00920   * @param __CPOL__ SMARTCARD frame polarity.
00921   * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
00922   */
00923 #define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
00924
00925 /**
00926   * @brief Ensure that SMARTCARD frame phase is valid.
00927   * @param __CPHA__ SMARTCARD frame phase.
00928   * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
00929   */
00930 #define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
00931
00932 /**
00933   * @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid.
00934   * @param __LASTBIT__ SMARTCARD frame last bit clock pulse setting.
00935   * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
00936   */
00937 #define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \
00938                                            ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE))
00939
00940 /**
00941   * @brief Ensure that SMARTCARD frame sampling is valid.
00942   * @param __ONEBIT__ SMARTCARD frame sampling.
00943   * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
00944   */
00945 #define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \
00946                                                  ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE))
00947
00948 /**
00949   * @brief Ensure that SMARTCARD NACK transmission setting is valid.
00950   * @param __NACK__ SMARTCARD NACK transmission setting.
00951   * @retval SET (__NACK__ is valid) or RESET (__NACK__ is invalid)
00952   */
00953 #define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \
00954                                      ((__NACK__) == SMARTCARD_NACK_DISABLE))
00955
00956 /**
00957   * @brief Ensure that SMARTCARD receiver timeout setting is valid.
00958   * @param __TIMEOUT__ SMARTCARD receiver timeout setting.
00959   * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
00960   */
00961 #define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \
00962                                            ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE))
00963
00964 /**
00965   * @brief Ensure that SMARTCARD clock Prescaler is valid.
00966   * @param __CLOCKPRESCALER__ SMARTCARD clock Prescaler value.
00967   * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
00968   */
00969 #define IS_SMARTCARD_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV1) || \
00970               ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV2)   || \
00971               ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV4)   || \
00972               ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV6)   || \
00973               ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV8)   || \
00974               ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV10)  || \
00975               ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV12)  || \
00976               ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV16)  || \
00977               ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV32)  || \
00978               ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV64)  || \
00979               ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV128) || \
00980               ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV256))
00981
00982 /**
00983   * @brief Ensure that SMARTCARD advanced features initialization is valid.
00984   * @param __INIT__ SMARTCARD advanced features initialization.
00985   * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
00986   */
00987 #define IS_SMARTCARD_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT                | \
00988                                                                SMARTCARD_ADVFEATURE_TXINVERT_INIT          | \
00989                                                                SMARTCARD_ADVFEATURE_RXINVERT_INIT          | \
00990                                                                SMARTCARD_ADVFEATURE_DATAINVERT_INIT        | \
00991                                                                SMARTCARD_ADVFEATURE_SWAP_INIT              | \
00992                                                                SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
00993                                                                SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \
00994                                                                SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
00995
00996 /**
00997   * @brief Ensure that SMARTCARD frame TX inversion setting is valid.
00998   * @param __TXINV__ SMARTCARD frame TX inversion setting.
00999   * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
01000   */
01001 #define IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \
01002                                                   ((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))
01003
01004 /**
01005   * @brief Ensure that SMARTCARD frame RX inversion setting is valid.
01006   * @param __RXINV__ SMARTCARD frame RX inversion setting.
01007   * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
01008   */
01009 #define IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \
01010                                                   ((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))
01011
01012 /**
01013   * @brief Ensure that SMARTCARD frame data inversion setting is valid.
01014   * @param __DATAINV__ SMARTCARD frame data inversion setting.
01015   * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
01016   */
01017 #define IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \
01018                                                       ((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))
01019
01020 /**
01021   * @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid.
01022   * @param __SWAP__ SMARTCARD frame RX/TX pins swap setting.
01023   * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
01024   */
01025 #define IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \
01026                                                 ((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))
01027
01028 /**
01029   * @brief Ensure that SMARTCARD frame overrun setting is valid.
01030   * @param __OVERRUN__ SMARTCARD frame overrun setting.
01031   * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
01032   */
01033 #define IS_SMARTCARD_OVERRUN(__OVERRUN__) (((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \
01034                                            ((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))
01035
01036 /**
01037   * @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.
01038   * @param __DMA__ SMARTCARD DMA enabling or disabling on error setting.
01039   * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
01040   */
01041 #define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \
01042                                                        ((__DMA__) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))
01043
01044 /**
01045   * @brief Ensure that SMARTCARD frame MSB first setting is valid.
01046   * @param __MSBFIRST__ SMARTCARD frame MSB first setting.
01047   * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
01048   */
01049 #define IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \
01050                                                         ((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))
01051
01052 /**
01053   * @brief Ensure that SMARTCARD request parameter is valid.
01054   * @param __PARAM__ SMARTCARD request parameter.
01055   * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
01056   */
01057 #define IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \
01058                                                    ((__PARAM__) == SMARTCARD_TXDATA_FLUSH_REQUEST))
01059
01060 /**
01061   * @}
01062   */
01063
01064 /* Include SMARTCARD HAL Extended module */
01065 #include "stm32wbxx_hal_smartcard_ex.h"
01066
01067
01068 /* Exported functions --------------------------------------------------------*/
01069 /** @addtogroup SMARTCARD_Exported_Functions
01070   * @{
01071   */
01072
01073 /* Initialization and de-initialization functions  ****************************/
01074 /** @addtogroup SMARTCARD_Exported_Functions_Group1
01075   * @{
01076   */
01077
01078 HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard);
01079 HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard);
01080 void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard);
01081 void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard);
01082
01083 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
01084 /* Callbacks Register/UnRegister functions  ***********************************/
01085 HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback);
01086 HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID);
01087 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
01088
01089 /**
01090   * @}
01091   */
01092
01093 /* IO operation functions *****************************************************/
01094 /** @addtogroup SMARTCARD_Exported_Functions_Group2
01095   * @{
01096   */
01097
01098 HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
01099 HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
01100 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
01101 HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
01102 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
01103 HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
01104 /* Transfer Abort functions */
01105 HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard);
01106 HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard);
01107 HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard);
01108 HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard);
01109 HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
01110 HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard);
01111
01112 void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard);
01113 void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
01114 void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
01115 void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard);
01116 void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
01117 void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
01118 void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
01119
01120 /**
01121   * @}
01122   */
01123
01124 /* Peripheral State and Error functions ***************************************/
01125 /** @addtogroup SMARTCARD_Exported_Functions_Group4
01126   * @{
01127   */
01128
01129 HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard);
01130 uint32_t                   HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard);
01131
01132 /**
01133   * @}
01134   */
01135
01136 /**
01137   * @}
01138   */
01139
01140 /**
01141   * @}
01142   */
01143
01144 /**
01145   * @}
01146   */
01147
01148 #ifdef __cplusplus
01149 }
01150 #endif
01151
01152 #endif /* STM32WBxx_HAL_SMARTCARD_H */
01153
01154 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:35 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_smartcard_ex.c Source File

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stm32wbxx_hal_smartcard_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_smartcard_ex.c
00004   * @author  MCD Application Team
00005   * @brief   SMARTCARD HAL module driver.
00006   *          This file provides extended firmware functions to manage the following
00007   *          functionalities of the SmartCard.
00008   *           + Initialization and de-initialization functions
00009   *           + Peripheral Control functions
00010   *
00011   *
00012   @verbatim
00013   =============================================================================
00014                ##### SMARTCARD peripheral extended features  #####
00015   =============================================================================
00016   [..]
00017   The Extended SMARTCARD HAL driver can be used as follows:
00018
00019     (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(),
00020         then program SMARTCARD advanced features if required (TX/RX pins swap, TimeOut,
00021         auto-retry counter,...) in the hsmartcard AdvancedInit structure.
00022
00023     (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
00024
00025         -@- When SMARTCARD operates in FIFO mode, FIFO mode must be enabled prior
00026             starting RX/TX transfers. Also RX/TX FIFO thresholds must be
00027             configured prior starting RX/TX transfers.
00028
00029   @endverbatim
00030   ******************************************************************************
00031   * @attention
00032   *
00033   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00034   * All rights reserved.</center></h2>
00035   *
00036   * This software component is licensed by ST under BSD 3-Clause license,
00037   * the "License"; You may not use this file except in compliance with the
00038   * License. You may obtain a copy of the License at:
00039   *                        opensource.org/licenses/BSD-3-Clause
00040   *
00041   ******************************************************************************
00042   */
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32wbxx_hal.h"
00046
00047 /** @addtogroup STM32WBxx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @defgroup SMARTCARDEx SMARTCARDEx
00052   * @brief SMARTCARD Extended HAL module driver
00053   * @{
00054   */
00055 #ifdef HAL_SMARTCARD_MODULE_ENABLED
00056
00057 /* Private typedef -----------------------------------------------------------*/
00058 /* Private define ------------------------------------------------------------*/
00059 /* UART RX FIFO depth */
00060 #define RX_FIFO_DEPTH 8U
00061
00062 /* UART TX FIFO depth */
00063 #define TX_FIFO_DEPTH 8U
00064
00065 /* Private macros ------------------------------------------------------------*/
00066 /* Private variables ---------------------------------------------------------*/
00067 /* Private function prototypes -----------------------------------------------*/
00068 static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard);
00069
00070 /* Exported functions --------------------------------------------------------*/
00071 /** @defgroup SMARTCARDEx_Exported_Functions  SMARTCARD Extended Exported Functions
00072   * @{
00073   */
00074
00075 /** @defgroup SMARTCARDEx_Exported_Functions_Group1 Extended Peripheral Control functions
00076   * @brief    Extended control functions
00077   *
00078 @verbatim
00079   ===============================================================================
00080                       ##### Peripheral Control functions #####
00081   ===============================================================================
00082   [..]
00083   This subsection provides a set of functions allowing to initialize the SMARTCARD.
00084      (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly
00085      (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly
00086      (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature
00087      (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature
00088
00089 @endverbatim
00090   * @{
00091   */
00092
00093 /**
00094   * @brief Update on the fly the SMARTCARD block length in RTOR register.
00095   * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00096   *                    the configuration information for the specified SMARTCARD module.
00097   * @param BlockLength SMARTCARD block length (8-bit long at most)
00098   * @retval None
00099   */
00100 void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
00101 {
00102   MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << USART_RTOR_BLEN_Pos));
00103 }
00104
00105 /**
00106   * @brief Update on the fly the receiver timeout value in RTOR register.
00107   * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00108   *                    the configuration information for the specified SMARTCARD module.
00109   * @param TimeOutValue receiver timeout value in number of baud blocks. The timeout
00110   *                     value must be less or equal to 0x0FFFFFFFF.
00111   * @retval None
00112   */
00113 void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
00114 {
00115   assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
00116   MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_RTO, TimeOutValue);
00117 }
00118
00119 /**
00120   * @brief Enable the SMARTCARD receiver timeout feature.
00121   * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00122   *                    the configuration information for the specified SMARTCARD module.
00123   * @retval HAL status
00124   */
00125 HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
00126 {
00127
00128   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
00129   {
00130     /* Process Locked */
00131     __HAL_LOCK(hsmartcard);
00132
00133     hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00134
00135     /* Set the USART RTOEN bit */
00136     SET_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
00137
00138     hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00139
00140     /* Process Unlocked */
00141     __HAL_UNLOCK(hsmartcard);
00142
00143     return HAL_OK;
00144   }
00145   else
00146   {
00147     return HAL_BUSY;
00148   }
00149 }
00150
00151 /**
00152   * @brief Disable the SMARTCARD receiver timeout feature.
00153   * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00154   *                    the configuration information for the specified SMARTCARD module.
00155   * @retval HAL status
00156   */
00157 HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
00158 {
00159
00160   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
00161   {
00162     /* Process Locked */
00163     __HAL_LOCK(hsmartcard);
00164
00165     hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00166
00167     /* Clear the USART RTOEN bit */
00168     CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
00169
00170     hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00171
00172     /* Process Unlocked */
00173     __HAL_UNLOCK(hsmartcard);
00174
00175     return HAL_OK;
00176   }
00177   else
00178   {
00179     return HAL_BUSY;
00180   }
00181 }
00182
00183 /**
00184   * @}
00185   */
00186
00187 /** @defgroup SMARTCARDEx_Exported_Functions_Group2 Extended Peripheral IO operation functions
00188   * @brief   SMARTCARD Transmit and Receive functions
00189   *
00190 @verbatim
00191  ===============================================================================
00192                       ##### IO operation functions #####
00193  ===============================================================================
00194     This subsection provides a set of FIFO mode related callback functions.
00195
00196     (#) TX/RX Fifos Callbacks:
00197         (+) HAL_SMARTCARDEx_RxFifoFullCallback()
00198         (+) HAL_SMARTCARDEx_TxFifoEmptyCallback()
00199
00200
00201 @endverbatim
00202   * @{
00203   */
00204
00205 /**
00206   * @brief  SMARTCARD RX Fifo full callback.
00207   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00208   *                   the configuration information for the specified SMARTCARD module.
00209   * @retval None
00210   */
00211 __weak void HAL_SMARTCARDEx_RxFifoFullCallback(SMARTCARD_HandleTypeDef *hsmartcard)
00212 {
00213   /* Prevent unused argument(s) compilation warning */
00214   UNUSED(hsmartcard);
00215
00216   /* NOTE : This function should not be modified, when the callback is needed,
00217             the HAL_SMARTCARDEx_RxFifoFullCallback can be implemented in the user file.
00218    */
00219 }
00220
00221 /**
00222   * @brief  SMARTCARD TX Fifo empty callback.
00223   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
00224   *                   the configuration information for the specified SMARTCARD module.
00225   * @retval None
00226   */
00227 __weak void HAL_SMARTCARDEx_TxFifoEmptyCallback(SMARTCARD_HandleTypeDef *hsmartcard)
00228 {
00229   /* Prevent unused argument(s) compilation warning */
00230   UNUSED(hsmartcard);
00231
00232   /* NOTE : This function should not be modified, when the callback is needed,
00233             the HAL_SMARTCARDEx_TxFifoEmptyCallback can be implemented in the user file.
00234    */
00235 }
00236
00237 /**
00238   * @}
00239   */
00240
00241 /** @defgroup SMARTCARD_Exported_Functions_Group3 Extended Peripheral Peripheral Control functions
00242   *  @brief   SMARTCARD control functions
00243   *
00244 @verbatim
00245  ===============================================================================
00246                       ##### Peripheral Control functions #####
00247  ===============================================================================
00248     [..]
00249     This subsection provides a set of functions allowing to control the SMARTCARD.
00250      (+) HAL_SMARTCARDEx_EnableFifoMode() API enables the FIFO mode
00251      (+) HAL_SMARTCARDEx_DisableFifoMode() API disables the FIFO mode
00252      (+) HAL_SMARTCARDEx_SetTxFifoThreshold() API sets the TX FIFO threshold
00253      (+) HAL_SMARTCARDEx_SetRxFifoThreshold() API sets the RX FIFO threshold
00254 @endverbatim
00255   * @{
00256   */
00257
00258 /**
00259   * @brief  Enable the FIFO mode.
00260   * @param hsmartcard SMARTCARD handle.
00261   * @retval HAL status
00262   */
00263 HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard)
00264 {
00265   uint32_t tmpcr1;
00266
00267   /* Check parameters */
00268   assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
00269
00270   /* Process Locked */
00271   __HAL_LOCK(hsmartcard);
00272
00273   hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00274
00275   /* Save actual SMARTCARD configuration */
00276   tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
00277
00278   /* Disable SMARTCARD */
00279   __HAL_SMARTCARD_DISABLE(hsmartcard);
00280
00281   /* Enable FIFO mode */
00282   SET_BIT(tmpcr1, USART_CR1_FIFOEN);
00283   hsmartcard->FifoMode = SMARTCARD_FIFOMODE_ENABLE;
00284
00285   /* Restore SMARTCARD configuration */
00286   WRITE_REG(hsmartcard->Instance->CR1, tmpcr1);
00287
00288   /* Determine the number of data to process during RX/TX ISR execution */
00289   SMARTCARDEx_SetNbDataToProcess(hsmartcard);
00290
00291   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00292
00293   /* Process Unlocked */
00294   __HAL_UNLOCK(hsmartcard);
00295
00296   return HAL_OK;
00297 }
00298
00299 /**
00300   * @brief  Disable the FIFO mode.
00301   * @param hsmartcard SMARTCARD handle.
00302   * @retval HAL status
00303   */
00304 HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard)
00305 {
00306   uint32_t tmpcr1;
00307
00308   /* Check parameters */
00309   assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
00310
00311   /* Process Locked */
00312   __HAL_LOCK(hsmartcard);
00313
00314   hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00315
00316   /* Save actual SMARTCARD configuration */
00317   tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
00318
00319   /* Disable SMARTCARD */
00320   __HAL_SMARTCARD_DISABLE(hsmartcard);
00321
00322   /* Enable FIFO mode */
00323   CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
00324   hsmartcard->FifoMode = SMARTCARD_FIFOMODE_DISABLE;
00325
00326   /* Restore SMARTCARD configuration */
00327   WRITE_REG(hsmartcard->Instance->CR1, tmpcr1);
00328
00329   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00330
00331   /* Process Unlocked */
00332   __HAL_UNLOCK(hsmartcard);
00333
00334   return HAL_OK;
00335 }
00336
00337 /**
00338   * @brief  Set the TXFIFO threshold.
00339   * @param hsmartcard      SMARTCARD handle.
00340   * @param Threshold  TX FIFO threshold value
00341   *          This parameter can be one of the following values:
00342   *            @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_8
00343   *            @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_4
00344   *            @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_2
00345   *            @arg @ref SMARTCARD_TXFIFO_THRESHOLD_3_4
00346   *            @arg @ref SMARTCARD_TXFIFO_THRESHOLD_7_8
00347   *            @arg @ref SMARTCARD_TXFIFO_THRESHOLD_8_8
00348   * @retval HAL status
00349   */
00350 HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
00351 {
00352   uint32_t tmpcr1;
00353
00354   /* Check parameters */
00355   assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
00356   assert_param(IS_SMARTCARD_TXFIFO_THRESHOLD(Threshold));
00357
00358   /* Process Locked */
00359   __HAL_LOCK(hsmartcard);
00360
00361   hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00362
00363   /* Save actual SMARTCARD configuration */
00364   tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
00365
00366   /* Disable SMARTCARD */
00367   __HAL_SMARTCARD_DISABLE(hsmartcard);
00368
00369   /* Update TX threshold configuration */
00370   MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
00371
00372   /* Determine the number of data to process during RX/TX ISR execution */
00373   SMARTCARDEx_SetNbDataToProcess(hsmartcard);
00374
00375   /* Restore SMARTCARD configuration */
00376   MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_UE, tmpcr1);
00377
00378   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00379
00380   /* Process Unlocked */
00381   __HAL_UNLOCK(hsmartcard);
00382
00383   return HAL_OK;
00384 }
00385
00386 /**
00387   * @brief  Set the RXFIFO threshold.
00388   * @param hsmartcard      SMARTCARD handle.
00389   * @param Threshold  RX FIFO threshold value
00390   *          This parameter can be one of the following values:
00391   *            @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_8
00392   *            @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_4
00393   *            @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_2
00394   *            @arg @ref SMARTCARD_RXFIFO_THRESHOLD_3_4
00395   *            @arg @ref SMARTCARD_RXFIFO_THRESHOLD_7_8
00396   *            @arg @ref SMARTCARD_RXFIFO_THRESHOLD_8_8
00397   * @retval HAL status
00398   */
00399 HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
00400 {
00401   uint32_t tmpcr1;
00402
00403   /* Check parameters */
00404   assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
00405   assert_param(IS_SMARTCARD_RXFIFO_THRESHOLD(Threshold));
00406
00407   /* Process Locked */
00408   __HAL_LOCK(hsmartcard);
00409
00410   hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
00411
00412   /* Save actual SMARTCARD configuration */
00413   tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
00414
00415   /* Disable SMARTCARD */
00416   __HAL_SMARTCARD_DISABLE(hsmartcard);
00417
00418   /* Update RX threshold configuration */
00419   MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
00420
00421   /* Determine the number of data to process during RX/TX ISR execution */
00422   SMARTCARDEx_SetNbDataToProcess(hsmartcard);
00423
00424   /* Restore SMARTCARD configuration */
00425   MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_UE, tmpcr1);
00426
00427   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
00428
00429   /* Process Unlocked */
00430   __HAL_UNLOCK(hsmartcard);
00431
00432   return HAL_OK;
00433 }
00434
00435 /**
00436   * @}
00437   */
00438
00439 /**
00440   * @}
00441   */
00442
00443 /** @defgroup SMARTCARDEx_Private_Functions  SMARTCARD Extended private Functions
00444   * @{
00445   */
00446
00447 /**
00448   * @brief Calculate the number of data to process in RX/TX ISR.
00449   * @note The RX FIFO depth and the TX FIFO depth is extracted from
00450   *       the USART configuration registers.
00451   * @param hsmartcard SMARTCARD handle.
00452   * @retval None
00453   */
00454 static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard)
00455 {
00456   uint8_t rx_fifo_depth;
00457   uint8_t tx_fifo_depth;
00458   uint8_t rx_fifo_threshold;
00459   uint8_t tx_fifo_threshold;
00460   /* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */
00461   uint8_t numerator[]   = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
00462   uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
00463
00464   if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_DISABLE)
00465   {
00466     hsmartcard->NbTxDataToProcess = 1U;
00467     hsmartcard->NbRxDataToProcess = 1U;
00468   }
00469   else
00470   {
00471     rx_fifo_depth = RX_FIFO_DEPTH;
00472     tx_fifo_depth = TX_FIFO_DEPTH;
00473     rx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
00474     tx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
00475     hsmartcard->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold];
00476     hsmartcard->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold];
00477   }
00478 }
00479
00480 /**
00481   * @}
00482   */
00483
00484 #endif /* HAL_SMARTCARD_MODULE_ENABLED */
00485
00486 /**
00487   * @}
00488   */
00489
00490 /**
00491   * @}
00492   */
00493
00494 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:35 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_smartcard_ex.h Source File

  • File List
  • Globals
  • Firmware
  • Drivers
  • STM32WBxx_HAL_Driver
  • Inc
stm32wbxx_hal_smartcard_ex.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_smartcard_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SMARTCARD HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_SMARTCARD_EX_H
00022 #define STM32WBxx_HAL_SMARTCARD_EX_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 /** @addtogroup STM32WBxx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup SMARTCARDEx
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /* Exported constants --------------------------------------------------------*/
00041
00042 /** @addtogroup SMARTCARDEx_Exported_Constants  SMARTCARD Extended Exported Constants
00043   * @{
00044   */
00045
00046 /** @defgroup SMARTCARDEx_Transmission_Completion_Indication SMARTCARD Transmission Completion Indication
00047   * @{
00048   */
00049 #define SMARTCARD_TCBGT      SMARTCARD_IT_TCBGT /*!< SMARTCARD transmission complete before guard time */
00050 #define SMARTCARD_TC         SMARTCARD_IT_TC    /*!< SMARTCARD transmission complete (flag raised when guard time has elapsed) */
00051 /**
00052   * @}
00053   */
00054
00055 /** @defgroup SMARTCARDEx_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type
00056   * @{
00057   */
00058 #define SMARTCARD_ADVFEATURE_NO_INIT                 0x00000000U    /*!< No advanced feature initialization                  */
00059 #define SMARTCARD_ADVFEATURE_TXINVERT_INIT           0x00000001U    /*!< TX pin active level inversion                       */
00060 #define SMARTCARD_ADVFEATURE_RXINVERT_INIT           0x00000002U    /*!< RX pin active level inversion                       */
00061 #define SMARTCARD_ADVFEATURE_DATAINVERT_INIT         0x00000004U    /*!< Binary data inversion                               */
00062 #define SMARTCARD_ADVFEATURE_SWAP_INIT               0x00000008U    /*!< TX/RX pins swap                                     */
00063 #define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT   0x00000010U    /*!< RX overrun disable                                  */
00064 #define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT  0x00000020U    /*!< DMA disable on Reception Error                      */
00065 #define SMARTCARD_ADVFEATURE_MSBFIRST_INIT           0x00000080U    /*!< Most significant bit sent/received first            */
00066 #define SMARTCARD_ADVFEATURE_TXCOMPLETION            0x00000100U    /*!< TX completion indication before of after guard time */
00067 /**
00068   * @}
00069   */
00070
00071 /** @defgroup SMARTCARDEx_FIFO_mode SMARTCARDEx FIFO mode
00072   * @brief    SMARTCARD FIFO mode
00073   * @{
00074   */
00075 #define SMARTCARD_FIFOMODE_DISABLE        0x00000000U                   /*!< FIFO mode disable */
00076 #define SMARTCARD_FIFOMODE_ENABLE         USART_CR1_FIFOEN              /*!< FIFO mode enable  */
00077 /**
00078   * @}
00079   */
00080
00081 /** @defgroup SMARTCARDEx_TXFIFO_threshold_level SMARTCARDEx TXFIFO threshold level
00082   * @brief    SMARTCARD TXFIFO level
00083   * @{
00084   */
00085 #define SMARTCARD_TXFIFO_THRESHOLD_1_8    0x00000000U                               /*!< TXFIFO reaches 1/8 of its depth */
00086 #define SMARTCARD_TXFIFO_THRESHOLD_1_4   USART_CR3_TXFTCFG_0                        /*!< TXFIFO reaches 1/4 of its depth */
00087 #define SMARTCARD_TXFIFO_THRESHOLD_1_2   USART_CR3_TXFTCFG_1                        /*!< TXFIFO reaches 1/2 of its depth */
00088 #define SMARTCARD_TXFIFO_THRESHOLD_3_4   (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)  /*!< TXFIFO reaches 3/4 of its depth */
00089 #define SMARTCARD_TXFIFO_THRESHOLD_7_8   USART_CR3_TXFTCFG_2                        /*!< TXFIFO reaches 7/8 of its depth */
00090 #define SMARTCARD_TXFIFO_THRESHOLD_8_8   (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)  /*!< TXFIFO becomes empty            */
00091 /**
00092   * @}
00093   */
00094
00095 /** @defgroup SMARTCARDEx_RXFIFO_threshold_level SMARTCARDEx RXFIFO threshold level
00096   * @brief    SMARTCARD RXFIFO level
00097   * @{
00098   */
00099 #define SMARTCARD_RXFIFO_THRESHOLD_1_8   0x00000000U                                /*!< RXFIFO FIFO reaches 1/8 of its depth */
00100 #define SMARTCARD_RXFIFO_THRESHOLD_1_4   USART_CR3_RXFTCFG_0                        /*!< RXFIFO FIFO reaches 1/4 of its depth */
00101 #define SMARTCARD_RXFIFO_THRESHOLD_1_2   USART_CR3_RXFTCFG_1                        /*!< RXFIFO FIFO reaches 1/2 of its depth */
00102 #define SMARTCARD_RXFIFO_THRESHOLD_3_4   (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)  /*!< RXFIFO FIFO reaches 3/4 of its depth */
00103 #define SMARTCARD_RXFIFO_THRESHOLD_7_8   USART_CR3_RXFTCFG_2                        /*!< RXFIFO FIFO reaches 7/8 of its depth */
00104 #define SMARTCARD_RXFIFO_THRESHOLD_8_8   (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)  /*!< RXFIFO FIFO becomes full             */
00105 /**
00106   * @}
00107   */
00108
00109 /** @defgroup SMARTCARDEx_Flags SMARTCARD Flags
00110   *        Elements values convention: 0xXXXX
00111   *           - 0xXXXX  : Flag mask in the ISR register
00112   * @{
00113   */
00114 #define SMARTCARD_FLAG_TCBGT          USART_ISR_TCBGT         /*!< SMARTCARD transmission complete before guard time completion */
00115 #define SMARTCARD_FLAG_REACK          USART_ISR_REACK         /*!< SMARTCARD receive enable acknowledge flag  */
00116 #define SMARTCARD_FLAG_TEACK          USART_ISR_TEACK         /*!< SMARTCARD transmit enable acknowledge flag */
00117 #define SMARTCARD_FLAG_BUSY           USART_ISR_BUSY          /*!< SMARTCARD busy flag                        */
00118 #define SMARTCARD_FLAG_EOBF           USART_ISR_EOBF          /*!< SMARTCARD end of block flag                */
00119 #define SMARTCARD_FLAG_RTOF           USART_ISR_RTOF          /*!< SMARTCARD receiver timeout flag            */
00120 #define SMARTCARD_FLAG_TXE            USART_ISR_TXE_TXFNF     /*!< SMARTCARD transmit data register empty     */
00121 #define SMARTCARD_FLAG_TXFNF          USART_ISR_TXE_TXFNF     /*!< SMARTCARD TXFIFO not full                  */
00122 #define SMARTCARD_FLAG_TC             USART_ISR_TC            /*!< SMARTCARD transmission complete            */
00123 #define SMARTCARD_FLAG_RXNE           USART_ISR_RXNE_RXFNE    /*!< SMARTCARD read data register not empty     */
00124 #define SMARTCARD_FLAG_RXFNE          USART_ISR_RXNE_RXFNE    /*!< SMARTCARD RXFIFO not empty                 */
00125 #define SMARTCARD_FLAG_IDLE           USART_ISR_IDLE          /*!< SMARTCARD idle line detection              */
00126 #define SMARTCARD_FLAG_ORE            USART_ISR_ORE           /*!< SMARTCARD overrun error                    */
00127 #define SMARTCARD_FLAG_NE             USART_ISR_NE            /*!< SMARTCARD noise error                      */
00128 #define SMARTCARD_FLAG_FE             USART_ISR_FE            /*!< SMARTCARD frame error                      */
00129 #define SMARTCARD_FLAG_PE             USART_ISR_PE            /*!< SMARTCARD parity error                     */
00130 #define SMARTCARD_FLAG_TXFE           USART_ISR_TXFE          /*!< SMARTCARD TXFIFO Empty flag                */
00131 #define SMARTCARD_FLAG_RXFF           USART_ISR_RXFF          /*!< SMARTCARD RXFIFO Full flag                 */
00132 #define SMARTCARD_FLAG_RXFT           USART_ISR_RXFT          /*!< SMARTCARD RXFIFO threshold flag            */
00133 #define SMARTCARD_FLAG_TXFT           USART_ISR_TXFT          /*!< SMARTCARD TXFIFO threshold flag            */
00134 /**
00135   * @}
00136   */
00137
00138 /** @defgroup SMARTCARDEx_Interrupt_definition SMARTCARD Interrupts Definition
00139   *        Elements values convention: 000ZZZZZ0XXYYYYYb
00140   *           - YYYYY  : Interrupt source position in the XX register (5 bits)
00141   *           - XX  : Interrupt source register (2 bits)
00142   *                 - 01: CR1 register
00143   *                 - 10: CR2 register
00144   *                 - 11: CR3 register
00145   *           - ZZZZZ  : Flag position in the ISR register(5 bits)
00146   * @{
00147   */
00148 #define SMARTCARD_IT_PE                     0x0028U           /*!< SMARTCARD parity error interruption                 */
00149 #define SMARTCARD_IT_TXE                    0x0727U           /*!< SMARTCARD transmit data register empty interruption */
00150 #define SMARTCARD_IT_TXFNF                  0x0727U           /*!< SMARTCARD TX FIFO not full interruption             */
00151 #define SMARTCARD_IT_TC                     0x0626U           /*!< SMARTCARD transmission complete interruption        */
00152 #define SMARTCARD_IT_RXNE                   0x0525U           /*!< SMARTCARD read data register not empty interruption */
00153 #define SMARTCARD_IT_RXFNE                  0x0525U           /*!< SMARTCARD RXFIFO not empty interruption             */
00154 #define SMARTCARD_IT_IDLE                   0x0424U           /*!< SMARTCARD idle line detection interruption          */
00155
00156 #define SMARTCARD_IT_ERR                    0x0060U           /*!< SMARTCARD error interruption         */
00157 #define SMARTCARD_IT_ORE                    0x0300U           /*!< SMARTCARD overrun error interruption */
00158 #define SMARTCARD_IT_NE                     0x0200U           /*!< SMARTCARD noise error interruption   */
00159 #define SMARTCARD_IT_FE                     0x0100U           /*!< SMARTCARD frame error interruption   */
00160
00161 #define SMARTCARD_IT_EOB                    0x0C3BU           /*!< SMARTCARD end of block interruption     */
00162 #define SMARTCARD_IT_RTO                    0x0B3AU           /*!< SMARTCARD receiver timeout interruption */
00163 #define SMARTCARD_IT_TCBGT                  0x1978U           /*!< SMARTCARD transmission complete before guard time completion interruption */
00164
00165 #define SMARTCARD_IT_RXFF                    0x183FU          /*!< SMARTCARD RXFIFO full interruption                  */
00166 #define SMARTCARD_IT_TXFE                    0x173EU          /*!< SMARTCARD TXFIFO empty interruption                 */
00167 #define SMARTCARD_IT_RXFT                    0x1A7CU          /*!< SMARTCARD RXFIFO threshold reached interruption     */
00168 #define SMARTCARD_IT_TXFT                    0x1B77U          /*!< SMARTCARD TXFIFO threshold reached interruption     */
00169 /**
00170   * @}
00171   */
00172
00173 /** @defgroup SMARTCARDEx_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags
00174   * @{
00175   */
00176 #define SMARTCARD_CLEAR_PEF                 USART_ICR_PECF    /*!< SMARTCARD parity error clear flag          */
00177 #define SMARTCARD_CLEAR_FEF                 USART_ICR_FECF    /*!< SMARTCARD framing error clear flag         */
00178 #define SMARTCARD_CLEAR_NEF                 USART_ICR_NECF    /*!< SMARTCARD noise error detected clear flag  */
00179 #define SMARTCARD_CLEAR_OREF                USART_ICR_ORECF   /*!< SMARTCARD overrun error clear flag         */
00180 #define SMARTCARD_CLEAR_IDLEF               USART_ICR_IDLECF  /*!< SMARTCARD idle line detected clear flag    */
00181 #define SMARTCARD_CLEAR_TXFECF              USART_ICR_TXFECF  /*!< TXFIFO empty Clear Flag                    */
00182 #define SMARTCARD_CLEAR_TCF                 USART_ICR_TCCF    /*!< SMARTCARD transmission complete clear flag */
00183 #define SMARTCARD_CLEAR_TCBGTF              USART_ICR_TCBGTCF /*!< SMARTCARD transmission complete before guard time completion clear flag */
00184 #define SMARTCARD_CLEAR_RTOF                USART_ICR_RTOCF   /*!< SMARTCARD receiver time out clear flag     */
00185 #define SMARTCARD_CLEAR_EOBF                USART_ICR_EOBCF   /*!< SMARTCARD end of block clear flag          */
00186 /**
00187   * @}
00188   */
00189
00190 /**
00191   * @}
00192   */
00193 /* Exported macros -----------------------------------------------------------*/
00194 /* Private macros ------------------------------------------------------------*/
00195 /** @defgroup SMARTCARDEx_Private_Macros SMARTCARD Extended Private Macros
00196   * @{
00197   */
00198
00199 /** @brief  Set the Transmission Completion flag
00200   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00201   * @note  If TCBGT (Transmission Complete Before Guard Time) flag is not available or if
00202   *        AdvancedInit.TxCompletionIndication is not already filled, the latter is forced
00203   *        to SMARTCARD_TC (transmission completion indication when guard time has elapsed).
00204   * @retval None
00205   */
00206 #define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__)                                                \
00207   do {                                                                                                       \
00208     if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION))        \
00209     {                                                                                                        \
00210      (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC;                                       \
00211     }                                                                                                        \
00212     else                                                                                                     \
00213     {                                                                                                        \
00214       assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \
00215     }                                                                                                        \
00216   } while(0U)
00217
00218 /** @brief  Return the transmission completion flag.
00219   * @param  __HANDLE__ specifies the SMARTCARD Handle.
00220   * @note  Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag.
00221   *        When TCBGT flag (Transmission Complete Before Guard Time) is not available, TC flag is
00222   *        reported.
00223   * @retval Transmission completion flag
00224   */
00225 #define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__)                                                         \
00226   (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) :  (SMARTCARD_FLAG_TCBGT))
00227
00228
00229 /**
00230   * @brief Ensure that SMARTCARD frame transmission completion used flag is valid.
00231   * @param __TXCOMPLETE__ SMARTCARD frame transmission completion used flag.
00232   * @retval SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid)
00233   */
00234 #define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) (((__TXCOMPLETE__) == SMARTCARD_TCBGT) ||\
00235                                                               ((__TXCOMPLETE__) == SMARTCARD_TC))
00236
00237 /**
00238   * @brief Ensure that SMARTCARD FIFO mode is valid.
00239   * @param __STATE__ SMARTCARD FIFO mode.
00240   * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
00241   */
00242 #define IS_SMARTCARD_FIFOMODE_STATE(__STATE__) (((__STATE__) == SMARTCARD_FIFOMODE_DISABLE ) || \
00243                                          ((__STATE__) == SMARTCARD_FIFOMODE_ENABLE))
00244
00245 /**
00246   * @brief Ensure that SMARTCARD TXFIFO threshold level is valid.
00247   * @param __THRESHOLD__ SMARTCARD TXFIFO threshold level.
00248   * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
00249   */
00250 #define IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_8) || \
00251                                           ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4)             || \
00252                                           ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2)             || \
00253                                           ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4)             || \
00254                                           ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8)             || \
00255                                           ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8))
00256
00257 /**
00258   * @brief Ensure that SMARTCARD RXFIFO threshold level is valid.
00259   * @param __THRESHOLD__ SMARTCARD RXFIFO threshold level.
00260   * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
00261   */
00262 #define IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_8) || \
00263                                           ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4)             || \
00264                                           ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2)             || \
00265                                           ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4)             || \
00266                                           ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8)             || \
00267                                           ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8))
00268
00269 /**
00270   * @}
00271   */
00272
00273 /* Exported functions --------------------------------------------------------*/
00274 /** @addtogroup SMARTCARDEx_Exported_Functions
00275   * @{
00276   */
00277
00278 /* Initialization and de-initialization functions  ****************************/
00279 /* IO operation methods *******************************************************/
00280
00281 /** @addtogroup SMARTCARDEx_Exported_Functions_Group1
00282   * @{
00283   */
00284
00285 /* Peripheral Control functions ***********************************************/
00286 void              HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength);
00287 void              HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue);
00288 HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
00289 HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
00290
00291 /**
00292   * @}
00293   */
00294
00295 /* Exported functions --------------------------------------------------------*/
00296 /** @addtogroup SMARTCARDEx_Exported_Functions_Group2
00297   * @{
00298   */
00299
00300 /* IO operation functions *****************************************************/
00301 void HAL_SMARTCARDEx_RxFifoFullCallback(SMARTCARD_HandleTypeDef *hsmartcard);
00302 void HAL_SMARTCARDEx_TxFifoEmptyCallback(SMARTCARD_HandleTypeDef *hsmartcard);
00303
00304 /**
00305   * @}
00306   */
00307
00308 /** @addtogroup SMARTCARDEx_Exported_Functions_Group3
00309   * @{
00310   */
00311
00312 /* Peripheral Control functions ***********************************************/
00313 HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard);
00314 HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard);
00315 HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold);
00316 HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold);
00317
00318 /**
00319   * @}
00320   */
00321
00322 /**
00323   * @}
00324   */
00325
00326
00327 /* Private functions ---------------------------------------------------------*/
00328
00329 /**
00330   * @}
00331   */
00332
00333 /**
00334   * @}
00335   */
00336
00337 #ifdef __cplusplus
00338 }
00339 #endif
00340
00341 #endif /* STM32WBxx_HAL_SMARTCARD_EX_H */
00342
00343 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:35 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_smbus.c Source File

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stm32wbxx_hal_smbus.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_smbus.c
00004   * @author  MCD Application Team
00005   * @brief   SMBUS HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the System Management Bus (SMBus) peripheral,
00008   *          based on I2C principles of operation :
00009   *           + Initialization and de-initialization functions
00010   *           + IO operation functions
00011   *           + Peripheral State and Errors functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                         ##### How to use this driver #####
00016   ==============================================================================
00017     [..]
00018     The SMBUS HAL driver can be used as follows:
00019
00020     (#) Declare a SMBUS_HandleTypeDef handle structure, for example:
00021         SMBUS_HandleTypeDef  hsmbus;
00022
00023     (#)Initialize the SMBUS low level resources by implementing the @ref HAL_SMBUS_MspInit() API:
00024         (##) Enable the SMBUSx interface clock
00025         (##) SMBUS pins configuration
00026             (+++) Enable the clock for the SMBUS GPIOs
00027             (+++) Configure SMBUS pins as alternate function open-drain
00028         (##) NVIC configuration if you need to use interrupt process
00029             (+++) Configure the SMBUSx interrupt priority
00030             (+++) Enable the NVIC SMBUS IRQ Channel
00031
00032     (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing mode,
00033         Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode,
00034         Peripheral mode and Packet Error Check mode in the hsmbus Init structure.
00035
00036     (#) Initialize the SMBUS registers by calling the @ref HAL_SMBUS_Init() API:
00037         (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00038              by calling the customized @ref HAL_SMBUS_MspInit(&hsmbus) API.
00039
00040     (#) To check if target device is ready for communication, use the function @ref HAL_SMBUS_IsDeviceReady()
00041
00042     (#) For SMBUS IO operations, only one mode of operations is available within this driver
00043
00044     *** Interrupt mode IO operation ***
00045     ===================================
00046     [..]
00047       (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Master_Transmit_IT()
00048       (++) At transmission end of transfer @ref HAL_SMBUS_MasterTxCpltCallback() is executed and user can
00049            add his own code by customization of function pointer @ref HAL_SMBUS_MasterTxCpltCallback()
00050       (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Master_Receive_IT()
00051       (++) At reception end of transfer @ref HAL_SMBUS_MasterRxCpltCallback() is executed and user can
00052            add his own code by customization of function pointer @ref HAL_SMBUS_MasterRxCpltCallback()
00053       (+) Abort a master/host SMBUS process communication with Interrupt using @ref HAL_SMBUS_Master_Abort_IT()
00054       (++) The associated previous transfer callback is called at the end of abort process
00055       (++) mean @ref HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
00056       (++) mean @ref HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
00057       (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode
00058            using @ref HAL_SMBUS_EnableListen_IT() @ref HAL_SMBUS_DisableListen_IT()
00059       (++) When address slave/device SMBUS match, @ref HAL_SMBUS_AddrCallback() is executed and user can
00060            add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read).
00061       (++) At Listen mode end @ref HAL_SMBUS_ListenCpltCallback() is executed and user can
00062            add his own code by customization of function pointer @ref HAL_SMBUS_ListenCpltCallback()
00063       (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Slave_Transmit_IT()
00064       (++) At transmission end of transfer @ref HAL_SMBUS_SlaveTxCpltCallback() is executed and user can
00065            add his own code by customization of function pointer @ref HAL_SMBUS_SlaveTxCpltCallback()
00066       (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Slave_Receive_IT()
00067       (++) At reception end of transfer @ref HAL_SMBUS_SlaveRxCpltCallback() is executed and user can
00068            add his own code by customization of function pointer @ref HAL_SMBUS_SlaveRxCpltCallback()
00069       (+) Enable/Disable the SMBUS alert mode using @ref HAL_SMBUS_EnableAlert_IT() @ref HAL_SMBUS_DisableAlert_IT()
00070       (++) When SMBUS Alert is generated @ref HAL_SMBUS_ErrorCallback() is executed and user can
00071            add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback()
00072            to check the Alert Error Code using function @ref HAL_SMBUS_GetError()
00073       (+) Get HAL state machine or error values using @ref HAL_SMBUS_GetState() or @ref HAL_SMBUS_GetError()
00074       (+) In case of transfer Error, @ref HAL_SMBUS_ErrorCallback() function is executed and user can
00075            add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback()
00076            to check the Error Code using function @ref HAL_SMBUS_GetError()
00077
00078      *** SMBUS HAL driver macros list ***
00079      ==================================
00080      [..]
00081        Below the list of most used macros in SMBUS HAL driver.
00082
00083       (+) @ref __HAL_SMBUS_ENABLE:      Enable the SMBUS peripheral
00084       (+) @ref __HAL_SMBUS_DISABLE:     Disable the SMBUS peripheral
00085       (+) @ref __HAL_SMBUS_GET_FLAG:    Check whether the specified SMBUS flag is set or not
00086       (+) @ref __HAL_SMBUS_CLEAR_FLAG:  Clear the specified SMBUS pending flag
00087       (+) @ref __HAL_SMBUS_ENABLE_IT:   Enable the specified SMBUS interrupt
00088       (+) @ref __HAL_SMBUS_DISABLE_IT:  Disable the specified SMBUS interrupt
00089
00090      *** Callback registration ***
00091      =============================================
00092     [..]
00093      The compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS when set to 1
00094      allows the user to configure dynamically the driver callbacks.
00095      Use Functions @ref HAL_SMBUS_RegisterCallback() or @ref HAL_SMBUS_RegisterAddrCallback()
00096      to register an interrupt callback.
00097     [..]
00098      Function @ref HAL_SMBUS_RegisterCallback() allows to register following callbacks:
00099        (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
00100        (+) MasterRxCpltCallback : callback for Master reception end of transfer.
00101        (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
00102        (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
00103        (+) ListenCpltCallback   : callback for end of listen mode.
00104        (+) ErrorCallback        : callback for error detection.
00105        (+) MspInitCallback      : callback for Msp Init.
00106        (+) MspDeInitCallback    : callback for Msp DeInit.
00107      This function takes as parameters the HAL peripheral handle, the Callback ID
00108      and a pointer to the user callback function.
00109     [..]
00110      For specific callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_RegisterAddrCallback.
00111     [..]
00112      Use function @ref HAL_SMBUS_UnRegisterCallback to reset a callback to the default
00113      weak function.
00114      @ref HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle,
00115      and the Callback ID.
00116      This function allows to reset following callbacks:
00117        (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
00118        (+) MasterRxCpltCallback : callback for Master reception end of transfer.
00119        (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
00120        (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
00121        (+) ListenCpltCallback   : callback for end of listen mode.
00122        (+) ErrorCallback        : callback for error detection.
00123        (+) MspInitCallback      : callback for Msp Init.
00124        (+) MspDeInitCallback    : callback for Msp DeInit.
00125     [..]
00126      For callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_UnRegisterAddrCallback.
00127     [..]
00128      By default, after the @ref HAL_SMBUS_Init() and when the state is @ref HAL_I2C_STATE_RESET
00129      all callbacks are set to the corresponding weak functions:
00130      examples @ref HAL_SMBUS_MasterTxCpltCallback(), @ref HAL_SMBUS_MasterRxCpltCallback().
00131      Exception done for MspInit and MspDeInit functions that are
00132      reset to the legacy weak functions in the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit() only when
00133      these callbacks are null (not registered beforehand).
00134      If MspInit or MspDeInit are not null, the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit()
00135      keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
00136     [..]
00137      Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
00138      Exception done MspInit/MspDeInit functions that can be registered/unregistered
00139      in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
00140      thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00141      Then, the user first registers the MspInit/MspDeInit user callbacks
00142      using @ref HAL_SMBUS_RegisterCallback() before calling @ref HAL_SMBUS_DeInit()
00143      or @ref HAL_SMBUS_Init() function.
00144     [..]
00145      When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or
00146      not defined, the callback registration feature is not available and all callbacks
00147      are set to the corresponding weak functions.
00148
00149      [..]
00150        (@) You can refer to the SMBUS HAL driver header file for more useful macros
00151
00152   @endverbatim
00153   ******************************************************************************
00154   * @attention
00155   *
00156   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00157   * All rights reserved.</center></h2>
00158   *
00159   * This software component is licensed by ST under BSD 3-Clause license,
00160   * the "License"; You may not use this file except in compliance with the
00161   * License. You may obtain a copy of the License at:
00162   *                        opensource.org/licenses/BSD-3-Clause
00163   *
00164   ******************************************************************************
00165   */
00166
00167 /* Includes ------------------------------------------------------------------*/
00168 #include "stm32wbxx_hal.h"
00169
00170 /** @addtogroup STM32WBxx_HAL_Driver
00171   * @{
00172   */
00173
00174 /** @defgroup SMBUS SMBUS
00175   * @brief SMBUS HAL module driver
00176   * @{
00177   */
00178
00179 #ifdef HAL_SMBUS_MODULE_ENABLED
00180
00181 /* Private typedef -----------------------------------------------------------*/
00182 /* Private constants ---------------------------------------------------------*/
00183 /** @defgroup SMBUS_Private_Define SMBUS Private Constants
00184   * @{
00185   */
00186 #define TIMING_CLEAR_MASK   (0xF0FFFFFFUL)     /*!< SMBUS TIMING clear register Mask */
00187 #define HAL_TIMEOUT_ADDR    (10000U)           /*!< 10 s  */
00188 #define HAL_TIMEOUT_BUSY    (25U)              /*!< 25 ms */
00189 #define HAL_TIMEOUT_DIR     (25U)              /*!< 25 ms */
00190 #define HAL_TIMEOUT_RXNE    (25U)              /*!< 25 ms */
00191 #define HAL_TIMEOUT_STOPF   (25U)              /*!< 25 ms */
00192 #define HAL_TIMEOUT_TC      (25U)              /*!< 25 ms */
00193 #define HAL_TIMEOUT_TCR     (25U)              /*!< 25 ms */
00194 #define HAL_TIMEOUT_TXIS    (25U)              /*!< 25 ms */
00195 #define MAX_NBYTE_SIZE      255U
00196 /**
00197   * @}
00198   */
00199
00200 /* Private macro -------------------------------------------------------------*/
00201 /* Private variables ---------------------------------------------------------*/
00202 /* Private function prototypes -----------------------------------------------*/
00203 /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
00204   * @{
00205   */
00206 static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
00207
00208 static void SMBUS_Enable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
00209 static void SMBUS_Disable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
00210 static HAL_StatusTypeDef SMBUS_Master_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
00211 static HAL_StatusTypeDef SMBUS_Slave_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
00212
00213 static void SMBUS_ConvertOtherXferOptions(struct __SMBUS_HandleTypeDef *hsmbus);
00214
00215 static void SMBUS_ITErrorHandler(struct __SMBUS_HandleTypeDef *hsmbus);
00216
00217 static void SMBUS_TransferConfig(struct __SMBUS_HandleTypeDef *hsmbus,  uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
00218 /**
00219   * @}
00220   */
00221
00222 /* Exported functions --------------------------------------------------------*/
00223
00224 /** @defgroup SMBUS_Exported_Functions SMBUS Exported Functions
00225   * @{
00226   */
00227
00228 /** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
00229  *  @brief    Initialization and Configuration functions
00230  *
00231 @verbatim
00232  ===============================================================================
00233               ##### Initialization and de-initialization functions #####
00234  ===============================================================================
00235     [..]  This subsection provides a set of functions allowing to initialize and
00236           deinitialize the SMBUSx peripheral:
00237
00238       (+) User must Implement HAL_SMBUS_MspInit() function in which he configures
00239           all related peripherals resources (CLOCK, GPIO, IT and NVIC ).
00240
00241       (+) Call the function HAL_SMBUS_Init() to configure the selected device with
00242           the selected configuration:
00243         (++) Clock Timing
00244         (++) Bus Timeout
00245         (++) Analog Filer mode
00246         (++) Own Address 1
00247         (++) Addressing mode (Master, Slave)
00248         (++) Dual Addressing mode
00249         (++) Own Address 2
00250         (++) Own Address 2 Mask
00251         (++) General call mode
00252         (++) Nostretch mode
00253         (++) Packet Error Check mode
00254         (++) Peripheral mode
00255
00256
00257       (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration
00258           of the selected SMBUSx peripheral.
00259
00260       (+) Enable/Disable Analog/Digital filters with HAL_SMBUS_ConfigAnalogFilter() and
00261           HAL_SMBUS_ConfigDigitalFilter().
00262
00263 @endverbatim
00264   * @{
00265   */
00266
00267 /**
00268   * @brief  Initialize the SMBUS according to the specified parameters
00269   *         in the SMBUS_InitTypeDef and initialize the associated handle.
00270   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00271   *                the configuration information for the specified SMBUS.
00272   * @retval HAL status
00273   */
00274 HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
00275 {
00276   /* Check the SMBUS handle allocation */
00277   if (hsmbus == NULL)
00278   {
00279     return HAL_ERROR;
00280   }
00281
00282   /* Check the parameters */
00283   assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
00284   assert_param(IS_SMBUS_ANALOG_FILTER(hsmbus->Init.AnalogFilter));
00285   assert_param(IS_SMBUS_OWN_ADDRESS1(hsmbus->Init.OwnAddress1));
00286   assert_param(IS_SMBUS_ADDRESSING_MODE(hsmbus->Init.AddressingMode));
00287   assert_param(IS_SMBUS_DUAL_ADDRESS(hsmbus->Init.DualAddressMode));
00288   assert_param(IS_SMBUS_OWN_ADDRESS2(hsmbus->Init.OwnAddress2));
00289   assert_param(IS_SMBUS_OWN_ADDRESS2_MASK(hsmbus->Init.OwnAddress2Masks));
00290   assert_param(IS_SMBUS_GENERAL_CALL(hsmbus->Init.GeneralCallMode));
00291   assert_param(IS_SMBUS_NO_STRETCH(hsmbus->Init.NoStretchMode));
00292   assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode));
00293   assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode));
00294
00295   if (hsmbus->State == HAL_SMBUS_STATE_RESET)
00296   {
00297     /* Allocate lock resource and initialize it */
00298     hsmbus->Lock = HAL_UNLOCKED;
00299
00300 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
00301     hsmbus->MasterTxCpltCallback = HAL_SMBUS_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
00302     hsmbus->MasterRxCpltCallback = HAL_SMBUS_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
00303     hsmbus->SlaveTxCpltCallback  = HAL_SMBUS_SlaveTxCpltCallback;  /* Legacy weak SlaveTxCpltCallback  */
00304     hsmbus->SlaveRxCpltCallback  = HAL_SMBUS_SlaveRxCpltCallback;  /* Legacy weak SlaveRxCpltCallback  */
00305     hsmbus->ListenCpltCallback   = HAL_SMBUS_ListenCpltCallback;   /* Legacy weak ListenCpltCallback   */
00306     hsmbus->ErrorCallback        = HAL_SMBUS_ErrorCallback;        /* Legacy weak ErrorCallback        */
00307     hsmbus->AddrCallback         = HAL_SMBUS_AddrCallback;         /* Legacy weak AddrCallback         */
00308
00309     if (hsmbus->MspInitCallback == NULL)
00310     {
00311       hsmbus->MspInitCallback = HAL_SMBUS_MspInit; /* Legacy weak MspInit  */
00312     }
00313
00314     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00315     hsmbus->MspInitCallback(hsmbus);
00316 #else
00317     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00318     HAL_SMBUS_MspInit(hsmbus);
00319 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
00320   }
00321
00322   hsmbus->State = HAL_SMBUS_STATE_BUSY;
00323
00324   /* Disable the selected SMBUS peripheral */
00325   __HAL_SMBUS_DISABLE(hsmbus);
00326
00327   /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/
00328   /* Configure SMBUSx: Frequency range */
00329   hsmbus->Instance->TIMINGR = hsmbus->Init.Timing & TIMING_CLEAR_MASK;
00330
00331   /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/
00332   /* Configure SMBUSx: Bus Timeout  */
00333   hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TIMOUTEN;
00334   hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TEXTEN;
00335   hsmbus->Instance->TIMEOUTR = hsmbus->Init.SMBusTimeout;
00336
00337   /*---------------------------- SMBUSx OAR1 Configuration -----------------------*/
00338   /* Configure SMBUSx: Own Address1 and ack own address1 mode */
00339   hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
00340
00341   if (hsmbus->Init.OwnAddress1 != 0UL)
00342   {
00343     if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT)
00344     {
00345       hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1);
00346     }
00347     else /* SMBUS_ADDRESSINGMODE_10BIT */
00348     {
00349       hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hsmbus->Init.OwnAddress1);
00350     }
00351   }
00352
00353   /*---------------------------- SMBUSx CR2 Configuration ------------------------*/
00354   /* Configure SMBUSx: Addressing Master mode */
00355   if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT)
00356   {
00357     hsmbus->Instance->CR2 = (I2C_CR2_ADD10);
00358   }
00359   /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */
00360   /* AUTOEND and NACK bit will be manage during Transfer process */
00361   hsmbus->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
00362
00363   /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/
00364   /* Configure SMBUSx: Dual mode and Own Address2 */
00365   hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | (hsmbus->Init.OwnAddress2Masks << 8U));
00366
00367   /*---------------------------- SMBUSx CR1 Configuration ------------------------*/
00368   /* Configure SMBUSx: Generalcall and NoStretch mode */
00369   hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter);
00370
00371   /* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */
00372   if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE)
00373       && ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)))
00374   {
00375     hsmbus->Instance->CR1 |= I2C_CR1_SBC;
00376   }
00377
00378   /* Enable the selected SMBUS peripheral */
00379   __HAL_SMBUS_ENABLE(hsmbus);
00380
00381   hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
00382   hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
00383   hsmbus->State = HAL_SMBUS_STATE_READY;
00384
00385   return HAL_OK;
00386 }
00387
00388 /**
00389   * @brief  DeInitialize the SMBUS peripheral.
00390   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00391   *                the configuration information for the specified SMBUS.
00392   * @retval HAL status
00393   */
00394 HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus)
00395 {
00396   /* Check the SMBUS handle allocation */
00397   if (hsmbus == NULL)
00398   {
00399     return HAL_ERROR;
00400   }
00401
00402   /* Check the parameters */
00403   assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
00404
00405   hsmbus->State = HAL_SMBUS_STATE_BUSY;
00406
00407   /* Disable the SMBUS Peripheral Clock */
00408   __HAL_SMBUS_DISABLE(hsmbus);
00409
00410 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
00411   if (hsmbus->MspDeInitCallback == NULL)
00412   {
00413     hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit; /* Legacy weak MspDeInit  */
00414   }
00415
00416   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00417   hsmbus->MspDeInitCallback(hsmbus);
00418 #else
00419   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00420   HAL_SMBUS_MspDeInit(hsmbus);
00421 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
00422
00423   hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
00424   hsmbus->PreviousState =  HAL_SMBUS_STATE_RESET;
00425   hsmbus->State = HAL_SMBUS_STATE_RESET;
00426
00427   /* Release Lock */
00428   __HAL_UNLOCK(hsmbus);
00429
00430   return HAL_OK;
00431 }
00432
00433 /**
00434   * @brief Initialize the SMBUS MSP.
00435   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00436   *                the configuration information for the specified SMBUS.
00437   * @retval None
00438   */
00439 __weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus)
00440 {
00441   /* Prevent unused argument(s) compilation warning */
00442   UNUSED(hsmbus);
00443
00444   /* NOTE : This function should not be modified, when the callback is needed,
00445             the HAL_SMBUS_MspInit could be implemented in the user file
00446    */
00447 }
00448
00449 /**
00450   * @brief DeInitialize the SMBUS MSP.
00451   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00452   *                the configuration information for the specified SMBUS.
00453   * @retval None
00454   */
00455 __weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus)
00456 {
00457   /* Prevent unused argument(s) compilation warning */
00458   UNUSED(hsmbus);
00459
00460   /* NOTE : This function should not be modified, when the callback is needed,
00461             the HAL_SMBUS_MspDeInit could be implemented in the user file
00462    */
00463 }
00464
00465 /**
00466   * @brief  Configure Analog noise filter.
00467   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00468   *                the configuration information for the specified SMBUS.
00469   * @param  AnalogFilter This parameter can be one of the following values:
00470   *         @arg @ref SMBUS_ANALOGFILTER_ENABLE
00471   *         @arg @ref SMBUS_ANALOGFILTER_DISABLE
00472   * @retval HAL status
00473   */
00474 HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter)
00475 {
00476   /* Check the parameters */
00477   assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
00478   assert_param(IS_SMBUS_ANALOG_FILTER(AnalogFilter));
00479
00480   if (hsmbus->State == HAL_SMBUS_STATE_READY)
00481   {
00482     /* Process Locked */
00483     __HAL_LOCK(hsmbus);
00484
00485     hsmbus->State = HAL_SMBUS_STATE_BUSY;
00486
00487     /* Disable the selected SMBUS peripheral */
00488     __HAL_SMBUS_DISABLE(hsmbus);
00489
00490     /* Reset ANOFF bit */
00491     hsmbus->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
00492
00493     /* Set analog filter bit*/
00494     hsmbus->Instance->CR1 |= AnalogFilter;
00495
00496     __HAL_SMBUS_ENABLE(hsmbus);
00497
00498     hsmbus->State = HAL_SMBUS_STATE_READY;
00499
00500     /* Process Unlocked */
00501     __HAL_UNLOCK(hsmbus);
00502
00503     return HAL_OK;
00504   }
00505   else
00506   {
00507     return HAL_BUSY;
00508   }
00509 }
00510
00511 /**
00512   * @brief  Configure Digital noise filter.
00513   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00514   *                the configuration information for the specified SMBUS.
00515   * @param  DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
00516   * @retval HAL status
00517   */
00518 HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter)
00519 {
00520   uint32_t tmpreg;
00521
00522   /* Check the parameters */
00523   assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
00524   assert_param(IS_SMBUS_DIGITAL_FILTER(DigitalFilter));
00525
00526   if (hsmbus->State == HAL_SMBUS_STATE_READY)
00527   {
00528     /* Process Locked */
00529     __HAL_LOCK(hsmbus);
00530
00531     hsmbus->State = HAL_SMBUS_STATE_BUSY;
00532
00533     /* Disable the selected SMBUS peripheral */
00534     __HAL_SMBUS_DISABLE(hsmbus);
00535
00536     /* Get the old register value */
00537     tmpreg = hsmbus->Instance->CR1;
00538
00539     /* Reset I2C DNF bits [11:8] */
00540     tmpreg &= ~(I2C_CR1_DNF);
00541
00542     /* Set I2Cx DNF coefficient */
00543     tmpreg |= DigitalFilter << I2C_CR1_DNF_Pos;
00544
00545     /* Store the new register value */
00546     hsmbus->Instance->CR1 = tmpreg;
00547
00548     __HAL_SMBUS_ENABLE(hsmbus);
00549
00550     hsmbus->State = HAL_SMBUS_STATE_READY;
00551
00552     /* Process Unlocked */
00553     __HAL_UNLOCK(hsmbus);
00554
00555     return HAL_OK;
00556   }
00557   else
00558   {
00559     return HAL_BUSY;
00560   }
00561 }
00562
00563 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
00564 /**
00565   * @brief  Register a User SMBUS Callback
00566   *         To be used instead of the weak predefined callback
00567   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00568   *                the configuration information for the specified SMBUS.
00569   * @param  CallbackID ID of the callback to be registered
00570   *         This parameter can be one of the following values:
00571   *          @arg @ref HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
00572   *          @arg @ref HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
00573   *          @arg @ref HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
00574   *          @arg @ref HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
00575   *          @arg @ref HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
00576   *          @arg @ref HAL_SMBUS_ERROR_CB_ID Error callback ID
00577   *          @arg @ref HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID
00578   *          @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID
00579   * @param  pCallback pointer to the Callback function
00580   * @retval HAL status
00581   */
00582 HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback)
00583 {
00584   HAL_StatusTypeDef status = HAL_OK;
00585
00586   if (pCallback == NULL)
00587   {
00588     /* Update the error code */
00589     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00590
00591     return HAL_ERROR;
00592   }
00593
00594   /* Process locked */
00595   __HAL_LOCK(hsmbus);
00596
00597   if (HAL_SMBUS_STATE_READY == hsmbus->State)
00598   {
00599     switch (CallbackID)
00600     {
00601       case HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID :
00602         hsmbus->MasterTxCpltCallback = pCallback;
00603         break;
00604
00605       case HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID :
00606         hsmbus->MasterRxCpltCallback = pCallback;
00607         break;
00608
00609       case HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID :
00610         hsmbus->SlaveTxCpltCallback = pCallback;
00611         break;
00612
00613       case HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID :
00614         hsmbus->SlaveRxCpltCallback = pCallback;
00615         break;
00616
00617       case HAL_SMBUS_LISTEN_COMPLETE_CB_ID :
00618         hsmbus->ListenCpltCallback = pCallback;
00619         break;
00620
00621       case HAL_SMBUS_ERROR_CB_ID :
00622         hsmbus->ErrorCallback = pCallback;
00623         break;
00624
00625       case HAL_SMBUS_MSPINIT_CB_ID :
00626         hsmbus->MspInitCallback = pCallback;
00627         break;
00628
00629       case HAL_SMBUS_MSPDEINIT_CB_ID :
00630         hsmbus->MspDeInitCallback = pCallback;
00631         break;
00632
00633       default :
00634         /* Update the error code */
00635         hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00636
00637         /* Return error status */
00638         status =  HAL_ERROR;
00639         break;
00640     }
00641   }
00642   else if (HAL_SMBUS_STATE_RESET == hsmbus->State)
00643   {
00644     switch (CallbackID)
00645     {
00646       case HAL_SMBUS_MSPINIT_CB_ID :
00647         hsmbus->MspInitCallback = pCallback;
00648         break;
00649
00650       case HAL_SMBUS_MSPDEINIT_CB_ID :
00651         hsmbus->MspDeInitCallback = pCallback;
00652         break;
00653
00654       default :
00655         /* Update the error code */
00656         hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00657
00658         /* Return error status */
00659         status =  HAL_ERROR;
00660         break;
00661     }
00662   }
00663   else
00664   {
00665     /* Update the error code */
00666     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00667
00668     /* Return error status */
00669     status =  HAL_ERROR;
00670   }
00671
00672   /* Release Lock */
00673   __HAL_UNLOCK(hsmbus);
00674   return status;
00675 }
00676
00677 /**
00678   * @brief  Unregister an SMBUS Callback
00679   *         SMBUS callback is redirected to the weak predefined callback
00680   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00681   *                the configuration information for the specified SMBUS.
00682   * @param  CallbackID ID of the callback to be unregistered
00683   *         This parameter can be one of the following values:
00684   *         This parameter can be one of the following values:
00685   *          @arg @ref HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
00686   *          @arg @ref HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
00687   *          @arg @ref HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
00688   *          @arg @ref HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
00689   *          @arg @ref HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
00690   *          @arg @ref HAL_SMBUS_ERROR_CB_ID Error callback ID
00691   *          @arg @ref HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID
00692   *          @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID
00693   * @retval HAL status
00694   */
00695 HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID)
00696 {
00697   HAL_StatusTypeDef status = HAL_OK;
00698
00699   /* Process locked */
00700   __HAL_LOCK(hsmbus);
00701
00702   if (HAL_SMBUS_STATE_READY == hsmbus->State)
00703   {
00704     switch (CallbackID)
00705     {
00706       case HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID :
00707         hsmbus->MasterTxCpltCallback = HAL_SMBUS_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
00708         break;
00709
00710       case HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID :
00711         hsmbus->MasterRxCpltCallback = HAL_SMBUS_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
00712         break;
00713
00714       case HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID :
00715         hsmbus->SlaveTxCpltCallback = HAL_SMBUS_SlaveTxCpltCallback;   /* Legacy weak SlaveTxCpltCallback  */
00716         break;
00717
00718       case HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID :
00719         hsmbus->SlaveRxCpltCallback = HAL_SMBUS_SlaveRxCpltCallback;   /* Legacy weak SlaveRxCpltCallback  */
00720         break;
00721
00722       case HAL_SMBUS_LISTEN_COMPLETE_CB_ID :
00723         hsmbus->ListenCpltCallback = HAL_SMBUS_ListenCpltCallback;     /* Legacy weak ListenCpltCallback   */
00724         break;
00725
00726       case HAL_SMBUS_ERROR_CB_ID :
00727         hsmbus->ErrorCallback = HAL_SMBUS_ErrorCallback;               /* Legacy weak ErrorCallback        */
00728         break;
00729
00730       case HAL_SMBUS_MSPINIT_CB_ID :
00731         hsmbus->MspInitCallback = HAL_SMBUS_MspInit;                   /* Legacy weak MspInit              */
00732         break;
00733
00734       case HAL_SMBUS_MSPDEINIT_CB_ID :
00735         hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit;               /* Legacy weak MspDeInit            */
00736         break;
00737
00738       default :
00739         /* Update the error code */
00740         hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00741
00742         /* Return error status */
00743         status =  HAL_ERROR;
00744         break;
00745     }
00746   }
00747   else if (HAL_SMBUS_STATE_RESET == hsmbus->State)
00748   {
00749     switch (CallbackID)
00750     {
00751       case HAL_SMBUS_MSPINIT_CB_ID :
00752         hsmbus->MspInitCallback = HAL_SMBUS_MspInit;                   /* Legacy weak MspInit              */
00753         break;
00754
00755       case HAL_SMBUS_MSPDEINIT_CB_ID :
00756         hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit;               /* Legacy weak MspDeInit            */
00757         break;
00758
00759       default :
00760         /* Update the error code */
00761         hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00762
00763         /* Return error status */
00764         status =  HAL_ERROR;
00765         break;
00766     }
00767   }
00768   else
00769   {
00770     /* Update the error code */
00771     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00772
00773     /* Return error status */
00774     status =  HAL_ERROR;
00775   }
00776
00777   /* Release Lock */
00778   __HAL_UNLOCK(hsmbus);
00779   return status;
00780 }
00781
00782 /**
00783   * @brief  Register the Slave Address Match SMBUS Callback
00784   *         To be used instead of the weak HAL_SMBUS_AddrCallback() predefined callback
00785   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00786   *                the configuration information for the specified SMBUS.
00787   * @param  pCallback pointer to the Address Match Callback function
00788   * @retval HAL status
00789   */
00790 HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback)
00791 {
00792   HAL_StatusTypeDef status = HAL_OK;
00793
00794   if (pCallback == NULL)
00795   {
00796     /* Update the error code */
00797     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00798
00799     return HAL_ERROR;
00800   }
00801   /* Process locked */
00802   __HAL_LOCK(hsmbus);
00803
00804   if (HAL_SMBUS_STATE_READY == hsmbus->State)
00805   {
00806     hsmbus->AddrCallback = pCallback;
00807   }
00808   else
00809   {
00810     /* Update the error code */
00811     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00812
00813     /* Return error status */
00814     status =  HAL_ERROR;
00815   }
00816
00817   /* Release Lock */
00818   __HAL_UNLOCK(hsmbus);
00819   return status;
00820 }
00821
00822 /**
00823   * @brief  UnRegister the Slave Address Match SMBUS Callback
00824   *         Info Ready SMBUS Callback is redirected to the weak HAL_SMBUS_AddrCallback() predefined callback
00825   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00826   *                the configuration information for the specified SMBUS.
00827   * @retval HAL status
00828   */
00829 HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus)
00830 {
00831   HAL_StatusTypeDef status = HAL_OK;
00832
00833   /* Process locked */
00834   __HAL_LOCK(hsmbus);
00835
00836   if (HAL_SMBUS_STATE_READY == hsmbus->State)
00837   {
00838     hsmbus->AddrCallback = HAL_SMBUS_AddrCallback; /* Legacy weak AddrCallback  */
00839   }
00840   else
00841   {
00842     /* Update the error code */
00843     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
00844
00845     /* Return error status */
00846     status =  HAL_ERROR;
00847   }
00848
00849   /* Release Lock */
00850   __HAL_UNLOCK(hsmbus);
00851   return status;
00852 }
00853
00854 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
00855
00856 /**
00857   * @}
00858   */
00859
00860 /** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
00861  *  @brief   Data transfers functions
00862  *
00863 @verbatim
00864  ===============================================================================
00865                       ##### IO operation functions #####
00866  ===============================================================================
00867     [..]
00868     This subsection provides a set of functions allowing to manage the SMBUS data
00869     transfers.
00870
00871     (#) Blocking mode function to check if device is ready for usage is :
00872         (++) HAL_SMBUS_IsDeviceReady()
00873
00874     (#) There is only one mode of transfer:
00875        (++) Non-Blocking mode : The communication is performed using Interrupts.
00876             These functions return the status of the transfer startup.
00877             The end of the data processing will be indicated through the
00878             dedicated SMBUS IRQ when using Interrupt mode.
00879
00880     (#) Non-Blocking mode functions with Interrupt are :
00881         (++) HAL_SMBUS_Master_Transmit_IT()
00882         (++) HAL_SMBUS_Master_Receive_IT()
00883         (++) HAL_SMBUS_Slave_Transmit_IT()
00884         (++) HAL_SMBUS_Slave_Receive_IT()
00885         (++) HAL_SMBUS_EnableListen_IT() or alias HAL_SMBUS_EnableListen_IT()
00886         (++) HAL_SMBUS_DisableListen_IT()
00887         (++) HAL_SMBUS_EnableAlert_IT()
00888         (++) HAL_SMBUS_DisableAlert_IT()
00889
00890     (#) A set of Transfer Complete Callbacks are provided in non-Blocking mode:
00891         (++) HAL_SMBUS_MasterTxCpltCallback()
00892         (++) HAL_SMBUS_MasterRxCpltCallback()
00893         (++) HAL_SMBUS_SlaveTxCpltCallback()
00894         (++) HAL_SMBUS_SlaveRxCpltCallback()
00895         (++) HAL_SMBUS_AddrCallback()
00896         (++) HAL_SMBUS_ListenCpltCallback()
00897         (++) HAL_SMBUS_ErrorCallback()
00898
00899 @endverbatim
00900   * @{
00901   */
00902
00903 /**
00904   * @brief  Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
00905   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
00906   *                the configuration information for the specified SMBUS.
00907   * @param  DevAddress Target device address: The device 7 bits address value
00908   *         in datasheet must be shifted to the left before calling the interface
00909   * @param  pData Pointer to data buffer
00910   * @param  Size Amount of data to be sent
00911   * @param  XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
00912   * @retval HAL status
00913   */
00914 HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
00915 {
00916   uint32_t tmp;
00917
00918   /* Check the parameters */
00919   assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
00920
00921   if (hsmbus->State == HAL_SMBUS_STATE_READY)
00922   {
00923     /* Process Locked */
00924     __HAL_LOCK(hsmbus);
00925
00926     hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
00927     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
00928     /* Prepare transfer parameters */
00929     hsmbus->pBuffPtr = pData;
00930     hsmbus->XferCount = Size;
00931     hsmbus->XferOptions = XferOptions;
00932
00933     /* In case of Quick command, remove autoend mode */
00934     /* Manage the stop generation by software */
00935     if (hsmbus->pBuffPtr == NULL)
00936     {
00937       hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
00938     }
00939
00940     if (Size > MAX_NBYTE_SIZE)
00941     {
00942       hsmbus->XferSize = MAX_NBYTE_SIZE;
00943     }
00944     else
00945     {
00946       hsmbus->XferSize = Size;
00947     }
00948
00949     /* Send Slave Address */
00950     /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
00951     if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
00952     {
00953       SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE);
00954     }
00955     else
00956     {
00957       /* If transfer direction not change, do not generate Restart Condition */
00958       /* Mean Previous state is same as current state */
00959
00960       /* Store current volatile XferOptions, misra rule */
00961       tmp = hsmbus->XferOptions;
00962
00963       if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
00964       {
00965         SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
00966       }
00967       /* Else transfer direction change, so generate Restart with new transfer direction */
00968       else
00969       {
00970         /* Convert OTHER_xxx XferOptions if any */
00971         SMBUS_ConvertOtherXferOptions(hsmbus);
00972
00973         /* Handle Transfer */
00974         SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE);
00975       }
00976
00977       /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */
00978       /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
00979       if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
00980       {
00981         hsmbus->XferSize--;
00982         hsmbus->XferCount--;
00983       }
00984     }
00985
00986     /* Process Unlocked */
00987     __HAL_UNLOCK(hsmbus);
00988
00989     /* Note : The SMBUS interrupts must be enabled after unlocking current process
00990               to avoid the risk of SMBUS interrupt handle execution before current
00991               process unlock */
00992     SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
00993
00994     return HAL_OK;
00995   }
00996   else
00997   {
00998     return HAL_BUSY;
00999   }
01000 }
01001
01002 /**
01003   * @brief  Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
01004   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01005   *                the configuration information for the specified SMBUS.
01006   * @param  DevAddress Target device address: The device 7 bits address value
01007   *         in datasheet must be shifted to the left before calling the interface
01008   * @param  pData Pointer to data buffer
01009   * @param  Size Amount of data to be sent
01010   * @param  XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
01011   * @retval HAL status
01012   */
01013 HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
01014 {
01015   uint32_t tmp;
01016
01017   /* Check the parameters */
01018   assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
01019
01020   if (hsmbus->State == HAL_SMBUS_STATE_READY)
01021   {
01022     /* Process Locked */
01023     __HAL_LOCK(hsmbus);
01024
01025     hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
01026     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
01027
01028     /* Prepare transfer parameters */
01029     hsmbus->pBuffPtr = pData;
01030     hsmbus->XferCount = Size;
01031     hsmbus->XferOptions = XferOptions;
01032
01033     /* In case of Quick command, remove autoend mode */
01034     /* Manage the stop generation by software */
01035     if (hsmbus->pBuffPtr == NULL)
01036     {
01037       hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
01038     }
01039
01040     if (Size > MAX_NBYTE_SIZE)
01041     {
01042       hsmbus->XferSize = MAX_NBYTE_SIZE;
01043     }
01044     else
01045     {
01046       hsmbus->XferSize = Size;
01047     }
01048
01049     /* Send Slave Address */
01050     /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
01051     if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
01052     {
01053       SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE  | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ);
01054     }
01055     else
01056     {
01057       /* If transfer direction not change, do not generate Restart Condition */
01058       /* Mean Previous state is same as current state */
01059
01060       /* Store current volatile XferOptions, Misra rule */
01061       tmp = hsmbus->XferOptions;
01062
01063       if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
01064       {
01065         SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
01066       }
01067       /* Else transfer direction change, so generate Restart with new transfer direction */
01068       else
01069       {
01070         /* Convert OTHER_xxx XferOptions if any */
01071         SMBUS_ConvertOtherXferOptions(hsmbus);
01072
01073         /* Handle Transfer */
01074         SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ);
01075       }
01076     }
01077
01078     /* Process Unlocked */
01079     __HAL_UNLOCK(hsmbus);
01080
01081     /* Note : The SMBUS interrupts must be enabled after unlocking current process
01082               to avoid the risk of SMBUS interrupt handle execution before current
01083               process unlock */
01084     SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
01085
01086     return HAL_OK;
01087   }
01088   else
01089   {
01090     return HAL_BUSY;
01091   }
01092 }
01093
01094 /**
01095   * @brief  Abort a master/host SMBUS process communication with Interrupt.
01096   * @note   This abort can be called only if state is ready
01097   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01098   *                the configuration information for the specified SMBUS.
01099   * @param  DevAddress Target device address: The device 7 bits address value
01100   *         in datasheet must be shifted to the left before calling the interface
01101   * @retval HAL status
01102   */
01103 HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
01104 {
01105   if (hsmbus->State == HAL_SMBUS_STATE_READY)
01106   {
01107     /* Process Locked */
01108     __HAL_LOCK(hsmbus);
01109
01110     /* Keep the same state as previous */
01111     /* to perform as well the call of the corresponding end of transfer callback */
01112     if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
01113     {
01114       hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
01115     }
01116     else if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
01117     {
01118       hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
01119     }
01120     else
01121     {
01122       /* Wrong usage of abort function */
01123       /* This function should be used only in case of abort monitored by master device */
01124       return HAL_ERROR;
01125     }
01126     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
01127
01128     /* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */
01129     /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
01130     SMBUS_TransferConfig(hsmbus, DevAddress, 1, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP);
01131
01132     /* Process Unlocked */
01133     __HAL_UNLOCK(hsmbus);
01134
01135     /* Note : The SMBUS interrupts must be enabled after unlocking current process
01136               to avoid the risk of SMBUS interrupt handle execution before current
01137               process unlock */
01138     if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
01139     {
01140       SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
01141     }
01142     else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
01143     {
01144       SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
01145     }
01146     else
01147     {
01148       /* Nothing to do */
01149     }
01150
01151     return HAL_OK;
01152   }
01153   else
01154   {
01155     return HAL_BUSY;
01156   }
01157 }
01158
01159 /**
01160   * @brief  Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
01161   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01162   *                the configuration information for the specified SMBUS.
01163   * @param  pData Pointer to data buffer
01164   * @param  Size Amount of data to be sent
01165   * @param  XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
01166   * @retval HAL status
01167   */
01168 HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
01169 {
01170   /* Check the parameters */
01171   assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
01172
01173   if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
01174   {
01175     if ((pData == NULL) || (Size == 0UL))
01176     {
01177       hsmbus->ErrorCode = HAL_SMBUS_ERROR_INVALID_PARAM;
01178       return HAL_ERROR;
01179     }
01180
01181     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
01182     SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_TX);
01183
01184     /* Process Locked */
01185     __HAL_LOCK(hsmbus);
01186
01187     hsmbus->State = (HAL_SMBUS_STATE_SLAVE_BUSY_TX | HAL_SMBUS_STATE_LISTEN);
01188     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
01189
01190     /* Set SBC bit to manage Acknowledge at each bit */
01191     hsmbus->Instance->CR1 |= I2C_CR1_SBC;
01192
01193     /* Enable Address Acknowledge */
01194     hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
01195
01196     /* Prepare transfer parameters */
01197     hsmbus->pBuffPtr = pData;
01198     hsmbus->XferCount = Size;
01199     hsmbus->XferOptions = XferOptions;
01200
01201     /* Convert OTHER_xxx XferOptions if any */
01202     SMBUS_ConvertOtherXferOptions(hsmbus);
01203
01204     if (Size > MAX_NBYTE_SIZE)
01205     {
01206       hsmbus->XferSize = MAX_NBYTE_SIZE;
01207     }
01208     else
01209     {
01210       hsmbus->XferSize = Size;
01211     }
01212
01213     /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
01214     if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
01215     {
01216       SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
01217     }
01218     else
01219     {
01220       /* Set NBYTE to transmit */
01221       SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
01222
01223       /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
01224       /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
01225       if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
01226       {
01227         hsmbus->XferSize--;
01228         hsmbus->XferCount--;
01229       }
01230     }
01231
01232     /* Clear ADDR flag after prepare the transfer parameters */
01233     /* This action will generate an acknowledge to the HOST */
01234     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
01235
01236     /* Process Unlocked */
01237     __HAL_UNLOCK(hsmbus);
01238
01239     /* Note : The SMBUS interrupts must be enabled after unlocking current process
01240               to avoid the risk of SMBUS interrupt handle execution before current
01241               process unlock */
01242     /* REnable ADDR interrupt */
01243     SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX | SMBUS_IT_ADDR);
01244
01245     return HAL_OK;
01246   }
01247   else
01248   {
01249     return HAL_BUSY;
01250   }
01251 }
01252
01253 /**
01254   * @brief  Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
01255   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01256   *                the configuration information for the specified SMBUS.
01257   * @param  pData Pointer to data buffer
01258   * @param  Size Amount of data to be sent
01259   * @param  XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
01260   * @retval HAL status
01261   */
01262 HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
01263 {
01264   /* Check the parameters */
01265   assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
01266
01267   if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
01268   {
01269     if ((pData == NULL) || (Size == 0UL))
01270     {
01271       hsmbus->ErrorCode = HAL_SMBUS_ERROR_INVALID_PARAM;
01272       return HAL_ERROR;
01273     }
01274
01275     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
01276     SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_RX);
01277
01278     /* Process Locked */
01279     __HAL_LOCK(hsmbus);
01280
01281     hsmbus->State = (HAL_SMBUS_STATE_SLAVE_BUSY_RX | HAL_SMBUS_STATE_LISTEN);
01282     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
01283
01284     /* Set SBC bit to manage Acknowledge at each bit */
01285     hsmbus->Instance->CR1 |= I2C_CR1_SBC;
01286
01287     /* Enable Address Acknowledge */
01288     hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
01289
01290     /* Prepare transfer parameters */
01291     hsmbus->pBuffPtr = pData;
01292     hsmbus->XferSize = Size;
01293     hsmbus->XferCount = Size;
01294     hsmbus->XferOptions = XferOptions;
01295
01296     /* Convert OTHER_xxx XferOptions if any */
01297     SMBUS_ConvertOtherXferOptions(hsmbus);
01298
01299     /* Set NBYTE to receive */
01300     /* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */
01301     /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */
01302     /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */
01303     /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */
01304     if (((SMBUS_GET_PEC_MODE(hsmbus) != 0UL) && (hsmbus->XferSize == 2U)) || (hsmbus->XferSize == 1U))
01305     {
01306       SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
01307     }
01308     else
01309     {
01310       SMBUS_TransferConfig(hsmbus, 0, 1, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP);
01311     }
01312
01313     /* Clear ADDR flag after prepare the transfer parameters */
01314     /* This action will generate an acknowledge to the HOST */
01315     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
01316
01317     /* Process Unlocked */
01318     __HAL_UNLOCK(hsmbus);
01319
01320     /* Note : The SMBUS interrupts must be enabled after unlocking current process
01321               to avoid the risk of SMBUS interrupt handle execution before current
01322               process unlock */
01323     /* REnable ADDR interrupt */
01324     SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_ADDR);
01325
01326     return HAL_OK;
01327   }
01328   else
01329   {
01330     return HAL_BUSY;
01331   }
01332 }
01333
01334 /**
01335   * @brief  Enable the Address listen mode with Interrupt.
01336   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01337   *                the configuration information for the specified SMBUS.
01338   * @retval HAL status
01339   */
01340 HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus)
01341 {
01342   hsmbus->State = HAL_SMBUS_STATE_LISTEN;
01343
01344   /* Enable the Address Match interrupt */
01345   SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ADDR);
01346
01347   return HAL_OK;
01348 }
01349
01350 /**
01351   * @brief  Disable the Address listen mode with Interrupt.
01352   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01353   *                the configuration information for the specified SMBUS.
01354   * @retval HAL status
01355   */
01356 HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus)
01357 {
01358   /* Disable Address listen mode only if a transfer is not ongoing */
01359   if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
01360   {
01361     hsmbus->State = HAL_SMBUS_STATE_READY;
01362
01363     /* Disable the Address Match interrupt */
01364     SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
01365
01366     return HAL_OK;
01367   }
01368   else
01369   {
01370     return HAL_BUSY;
01371   }
01372 }
01373
01374 /**
01375   * @brief  Enable the SMBUS alert mode with Interrupt.
01376   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01377   *                the configuration information for the specified SMBUSx peripheral.
01378   * @retval HAL status
01379   */
01380 HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
01381 {
01382   /* Enable SMBus alert */
01383   hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN;
01384
01385   /* Clear ALERT flag */
01386   __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
01387
01388   /* Enable Alert Interrupt */
01389   SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ALERT);
01390
01391   return HAL_OK;
01392 }
01393 /**
01394   * @brief  Disable the SMBUS alert mode with Interrupt.
01395   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01396   *                the configuration information for the specified SMBUSx peripheral.
01397   * @retval HAL status
01398   */
01399 HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
01400 {
01401   /* Enable SMBus alert */
01402   hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN;
01403
01404   /* Disable Alert Interrupt */
01405   SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ALERT);
01406
01407   return HAL_OK;
01408 }
01409
01410 /**
01411   * @brief  Check if target device is ready for communication.
01412   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01413   *                the configuration information for the specified SMBUS.
01414   * @param  DevAddress Target device address: The device 7 bits address value
01415   *         in datasheet must be shifted to the left before calling the interface
01416   * @param  Trials Number of trials
01417   * @param  Timeout Timeout duration
01418   * @retval HAL status
01419   */
01420 HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
01421 {
01422   uint32_t tickstart;
01423
01424   __IO uint32_t SMBUS_Trials = 0UL;
01425
01426   FlagStatus tmp1;
01427   FlagStatus tmp2;
01428
01429   if (hsmbus->State == HAL_SMBUS_STATE_READY)
01430   {
01431     if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET)
01432     {
01433       return HAL_BUSY;
01434     }
01435
01436     /* Process Locked */
01437     __HAL_LOCK(hsmbus);
01438
01439     hsmbus->State = HAL_SMBUS_STATE_BUSY;
01440     hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
01441
01442     do
01443     {
01444       /* Generate Start */
01445       hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode, DevAddress);
01446
01447       /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
01448       /* Wait until STOPF flag is set or a NACK flag is set*/
01449       tickstart = HAL_GetTick();
01450
01451       tmp1 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01452       tmp2 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF);
01453
01454       while ((tmp1 == RESET) && (tmp2 == RESET))
01455       {
01456         if (Timeout != HAL_MAX_DELAY)
01457         {
01458           if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
01459           {
01460             /* Device is ready */
01461             hsmbus->State = HAL_SMBUS_STATE_READY;
01462
01463             /* Update SMBUS error code */
01464             hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT;
01465
01466             /* Process Unlocked */
01467             __HAL_UNLOCK(hsmbus);
01468             return HAL_ERROR;
01469           }
01470         }
01471
01472         tmp1 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01473         tmp2 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF);
01474       }
01475
01476       /* Check if the NACKF flag has not been set */
01477       if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET)
01478       {
01479         /* Wait until STOPF flag is reset */
01480         if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
01481         {
01482           return HAL_ERROR;
01483         }
01484
01485         /* Clear STOP Flag */
01486         __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01487
01488         /* Device is ready */
01489         hsmbus->State = HAL_SMBUS_STATE_READY;
01490
01491         /* Process Unlocked */
01492         __HAL_UNLOCK(hsmbus);
01493
01494         return HAL_OK;
01495       }
01496       else
01497       {
01498         /* Wait until STOPF flag is reset */
01499         if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
01500         {
01501           return HAL_ERROR;
01502         }
01503
01504         /* Clear NACK Flag */
01505         __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
01506
01507         /* Clear STOP Flag, auto generated with autoend*/
01508         __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01509       }
01510
01511       /* Check if the maximum allowed number of trials has been reached */
01512       if (SMBUS_Trials == Trials)
01513       {
01514         /* Generate Stop */
01515         hsmbus->Instance->CR2 |= I2C_CR2_STOP;
01516
01517         /* Wait until STOPF flag is reset */
01518         if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
01519         {
01520           return HAL_ERROR;
01521         }
01522
01523         /* Clear STOP Flag */
01524         __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01525       }
01526
01527       /* Increment Trials */
01528       SMBUS_Trials++;
01529     }
01530     while (SMBUS_Trials < Trials);
01531
01532     hsmbus->State = HAL_SMBUS_STATE_READY;
01533
01534     /* Update SMBUS error code */
01535     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT;
01536
01537     /* Process Unlocked */
01538     __HAL_UNLOCK(hsmbus);
01539
01540     return HAL_ERROR;
01541   }
01542   else
01543   {
01544     return HAL_BUSY;
01545   }
01546 }
01547 /**
01548   * @}
01549   */
01550
01551 /** @defgroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
01552  * @{
01553  */
01554
01555 /**
01556   * @brief  Handle SMBUS event interrupt request.
01557   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01558   *                the configuration information for the specified SMBUS.
01559   * @retval None
01560   */
01561 void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
01562 {
01563   /* Use a local variable to store the current ISR flags */
01564   /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */
01565   uint32_t tmpisrvalue = READ_REG(hsmbus->Instance->ISR);
01566   uint32_t tmpcr1value = READ_REG(hsmbus->Instance->CR1);
01567
01568   /* SMBUS in mode Transmitter ---------------------------------------------------*/
01569   if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
01570   {
01571     /* Slave mode selected */
01572     if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
01573     {
01574       (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue);
01575     }
01576     /* Master mode selected */
01577     else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX)
01578     {
01579       (void)SMBUS_Master_ISR(hsmbus, tmpisrvalue);
01580     }
01581     else
01582     {
01583       /* Nothing to do */
01584     }
01585   }
01586
01587   /* SMBUS in mode Receiver ----------------------------------------------------*/
01588   if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
01589   {
01590     /* Slave mode selected */
01591     if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
01592     {
01593       (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue);
01594     }
01595     /* Master mode selected */
01596     else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX)
01597     {
01598       (void)SMBUS_Master_ISR(hsmbus, tmpisrvalue);
01599     }
01600     else
01601     {
01602       /* Nothing to do */
01603     }
01604   }
01605
01606   /* SMBUS in mode Listener Only --------------------------------------------------*/
01607   if (((SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_ADDRI) != RESET) || (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_STOPI) != RESET) || (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_NACKI) != RESET)) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
01608   {
01609     if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
01610     {
01611       (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue);
01612     }
01613   }
01614 }
01615
01616 /**
01617   * @brief  Handle SMBUS error interrupt request.
01618   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01619   *                the configuration information for the specified SMBUS.
01620   * @retval None
01621   */
01622 void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
01623 {
01624   SMBUS_ITErrorHandler(hsmbus);
01625 }
01626
01627 /**
01628   * @brief  Master Tx Transfer completed callback.
01629   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01630   *                the configuration information for the specified SMBUS.
01631   * @retval None
01632   */
01633 __weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
01634 {
01635   /* Prevent unused argument(s) compilation warning */
01636   UNUSED(hsmbus);
01637
01638   /* NOTE : This function should not be modified, when the callback is needed,
01639             the HAL_SMBUS_MasterTxCpltCallback() could be implemented in the user file
01640    */
01641 }
01642
01643 /**
01644   * @brief  Master Rx Transfer completed callback.
01645   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01646   *                the configuration information for the specified SMBUS.
01647   * @retval None
01648   */
01649 __weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
01650 {
01651   /* Prevent unused argument(s) compilation warning */
01652   UNUSED(hsmbus);
01653
01654   /* NOTE : This function should not be modified, when the callback is needed,
01655             the HAL_SMBUS_MasterRxCpltCallback() could be implemented in the user file
01656    */
01657 }
01658
01659 /** @brief  Slave Tx Transfer completed callback.
01660   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01661   *                the configuration information for the specified SMBUS.
01662   * @retval None
01663   */
01664 __weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
01665 {
01666   /* Prevent unused argument(s) compilation warning */
01667   UNUSED(hsmbus);
01668
01669   /* NOTE : This function should not be modified, when the callback is needed,
01670             the HAL_SMBUS_SlaveTxCpltCallback() could be implemented in the user file
01671    */
01672 }
01673
01674 /**
01675   * @brief  Slave Rx Transfer completed callback.
01676   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01677   *                the configuration information for the specified SMBUS.
01678   * @retval None
01679   */
01680 __weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
01681 {
01682   /* Prevent unused argument(s) compilation warning */
01683   UNUSED(hsmbus);
01684
01685   /* NOTE : This function should not be modified, when the callback is needed,
01686             the HAL_SMBUS_SlaveRxCpltCallback() could be implemented in the user file
01687    */
01688 }
01689
01690 /**
01691   * @brief  Slave Address Match callback.
01692   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01693   *                the configuration information for the specified SMBUS.
01694   * @param  TransferDirection Master request Transfer Direction (Write/Read)
01695   * @param  AddrMatchCode Address Match Code
01696   * @retval None
01697   */
01698 __weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
01699 {
01700   /* Prevent unused argument(s) compilation warning */
01701   UNUSED(hsmbus);
01702   UNUSED(TransferDirection);
01703   UNUSED(AddrMatchCode);
01704
01705   /* NOTE : This function should not be modified, when the callback is needed,
01706             the HAL_SMBUS_AddrCallback() could be implemented in the user file
01707    */
01708 }
01709
01710 /**
01711   * @brief  Listen Complete callback.
01712   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01713   *                the configuration information for the specified SMBUS.
01714   * @retval None
01715   */
01716 __weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus)
01717 {
01718   /* Prevent unused argument(s) compilation warning */
01719   UNUSED(hsmbus);
01720
01721   /* NOTE : This function should not be modified, when the callback is needed,
01722             the HAL_SMBUS_ListenCpltCallback() could be implemented in the user file
01723    */
01724 }
01725
01726 /**
01727   * @brief  SMBUS error callback.
01728   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01729   *                the configuration information for the specified SMBUS.
01730   * @retval None
01731   */
01732 __weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus)
01733 {
01734   /* Prevent unused argument(s) compilation warning */
01735   UNUSED(hsmbus);
01736
01737   /* NOTE : This function should not be modified, when the callback is needed,
01738             the HAL_SMBUS_ErrorCallback() could be implemented in the user file
01739    */
01740 }
01741
01742 /**
01743   * @}
01744   */
01745
01746 /** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
01747  *  @brief   Peripheral State and Errors functions
01748  *
01749 @verbatim
01750  ===============================================================================
01751             ##### Peripheral State and Errors functions #####
01752  ===============================================================================
01753     [..]
01754     This subsection permits to get in run-time the status of the peripheral
01755     and the data flow.
01756
01757 @endverbatim
01758   * @{
01759   */
01760
01761 /**
01762   * @brief  Return the SMBUS handle state.
01763   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01764   *                the configuration information for the specified SMBUS.
01765   * @retval HAL state
01766   */
01767 uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus)
01768 {
01769   /* Return SMBUS handle state */
01770   return hsmbus->State;
01771 }
01772
01773 /**
01774 * @brief  Return the SMBUS error code.
01775   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01776   *              the configuration information for the specified SMBUS.
01777 * @retval SMBUS Error Code
01778 */
01779 uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus)
01780 {
01781   return hsmbus->ErrorCode;
01782 }
01783
01784 /**
01785   * @}
01786   */
01787
01788 /**
01789   * @}
01790   */
01791
01792 /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
01793  *  @brief   Data transfers Private functions
01794   * @{
01795   */
01796
01797 /**
01798   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
01799   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
01800   *                the configuration information for the specified SMBUS.
01801   * @param  StatusFlags Value of Interrupt Flags.
01802   * @retval HAL status
01803   */
01804 static HAL_StatusTypeDef SMBUS_Master_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
01805 {
01806   uint16_t DevAddress;
01807
01808   /* Process Locked */
01809   __HAL_LOCK(hsmbus);
01810
01811   if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_AF) != RESET)
01812   {
01813     /* Clear NACK Flag */
01814     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
01815
01816     /* Set corresponding Error Code */
01817     /* No need to generate STOP, it is automatically done */
01818     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
01819
01820     /* Process Unlocked */
01821     __HAL_UNLOCK(hsmbus);
01822
01823     /* Call the Error callback to inform upper layer */
01824 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
01825     hsmbus->ErrorCallback(hsmbus);
01826 #else
01827     HAL_SMBUS_ErrorCallback(hsmbus);
01828 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
01829   }
01830   else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_STOPF) != RESET)
01831   {
01832     /* Check and treat errors if errors occurs during STOP process */
01833     SMBUS_ITErrorHandler(hsmbus);
01834
01835     /* Call the corresponding callback to inform upper layer of End of Transfer */
01836     if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
01837     {
01838       /* Disable Interrupt */
01839       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
01840
01841       /* Clear STOP Flag */
01842       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01843
01844       /* Clear Configuration Register 2 */
01845       SMBUS_RESET_CR2(hsmbus);
01846
01847       /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */
01848       /* Disable the selected SMBUS peripheral */
01849       __HAL_SMBUS_DISABLE(hsmbus);
01850
01851       hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
01852       hsmbus->State = HAL_SMBUS_STATE_READY;
01853
01854       /* Process Unlocked */
01855       __HAL_UNLOCK(hsmbus);
01856
01857       /* REenable the selected SMBUS peripheral */
01858       __HAL_SMBUS_ENABLE(hsmbus);
01859
01860       /* Call the corresponding callback to inform upper layer of End of Transfer */
01861 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
01862       hsmbus->MasterTxCpltCallback(hsmbus);
01863 #else
01864       HAL_SMBUS_MasterTxCpltCallback(hsmbus);
01865 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
01866     }
01867     else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
01868     {
01869       /* Store Last receive data if any */
01870       if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET)
01871       {
01872         /* Read data from RXDR */
01873         *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
01874
01875         /* Increment Buffer pointer */
01876         hsmbus->pBuffPtr++;
01877
01878         if ((hsmbus->XferSize > 0U))
01879         {
01880           hsmbus->XferSize--;
01881           hsmbus->XferCount--;
01882         }
01883       }
01884
01885       /* Disable Interrupt */
01886       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
01887
01888       /* Clear STOP Flag */
01889       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
01890
01891       /* Clear Configuration Register 2 */
01892       SMBUS_RESET_CR2(hsmbus);
01893
01894       hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
01895       hsmbus->State = HAL_SMBUS_STATE_READY;
01896
01897       /* Process Unlocked */
01898       __HAL_UNLOCK(hsmbus);
01899
01900       /* Call the corresponding callback to inform upper layer of End of Transfer */
01901 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
01902       hsmbus->MasterRxCpltCallback(hsmbus);
01903 #else
01904       HAL_SMBUS_MasterRxCpltCallback(hsmbus);
01905 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
01906     }
01907     else
01908     {
01909       /* Nothing to do */
01910     }
01911   }
01912   else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET)
01913   {
01914     /* Read data from RXDR */
01915     *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
01916
01917     /* Increment Buffer pointer */
01918     hsmbus->pBuffPtr++;
01919
01920     /* Increment Size counter */
01921     hsmbus->XferSize--;
01922     hsmbus->XferCount--;
01923   }
01924   else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TXIS) != RESET)
01925   {
01926     /* Write data to TXDR */
01927     hsmbus->Instance->TXDR = *hsmbus->pBuffPtr;
01928
01929     /* Increment Buffer pointer */
01930     hsmbus->pBuffPtr++;
01931
01932     /* Increment Size counter */
01933     hsmbus->XferSize--;
01934     hsmbus->XferCount--;
01935   }
01936   else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET)
01937   {
01938     if ((hsmbus->XferCount != 0U) && (hsmbus->XferSize == 0U))
01939     {
01940       DevAddress = (uint16_t)(hsmbus->Instance->CR2 & I2C_CR2_SADD);
01941
01942       if (hsmbus->XferCount > MAX_NBYTE_SIZE)
01943       {
01944         SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
01945         hsmbus->XferSize = MAX_NBYTE_SIZE;
01946       }
01947       else
01948       {
01949         hsmbus->XferSize = hsmbus->XferCount;
01950         SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
01951         /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
01952         /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
01953         if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
01954         {
01955           hsmbus->XferSize--;
01956           hsmbus->XferCount--;
01957         }
01958       }
01959     }
01960     else if ((hsmbus->XferCount == 0U) && (hsmbus->XferSize == 0U))
01961     {
01962       /* Call TxCpltCallback() if no stop mode is set */
01963       if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
01964       {
01965         /* Call the corresponding callback to inform upper layer of End of Transfer */
01966         if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
01967         {
01968           /* Disable Interrupt */
01969           SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
01970           hsmbus->PreviousState = hsmbus->State;
01971           hsmbus->State = HAL_SMBUS_STATE_READY;
01972
01973           /* Process Unlocked */
01974           __HAL_UNLOCK(hsmbus);
01975
01976           /* Call the corresponding callback to inform upper layer of End of Transfer */
01977 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
01978           hsmbus->MasterTxCpltCallback(hsmbus);
01979 #else
01980           HAL_SMBUS_MasterTxCpltCallback(hsmbus);
01981 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
01982         }
01983         else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
01984         {
01985           SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
01986           hsmbus->PreviousState = hsmbus->State;
01987           hsmbus->State = HAL_SMBUS_STATE_READY;
01988
01989           /* Process Unlocked */
01990           __HAL_UNLOCK(hsmbus);
01991
01992           /* Call the corresponding callback to inform upper layer of End of Transfer */
01993 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
01994           hsmbus->MasterRxCpltCallback(hsmbus);
01995 #else
01996           HAL_SMBUS_MasterRxCpltCallback(hsmbus);
01997 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
01998         }
01999         else
02000         {
02001           /* Nothing to do */
02002         }
02003       }
02004     }
02005     else
02006     {
02007       /* Nothing to do */
02008     }
02009   }
02010   else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TC) != RESET)
02011   {
02012     if (hsmbus->XferCount == 0U)
02013     {
02014       /* Specific use case for Quick command */
02015       if (hsmbus->pBuffPtr == NULL)
02016       {
02017         /* Generate a Stop command */
02018         hsmbus->Instance->CR2 |= I2C_CR2_STOP;
02019       }
02020       /* Call TxCpltCallback() if no stop mode is set */
02021       else if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
02022       {
02023         /* No Generate Stop, to permit restart mode */
02024         /* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */
02025
02026         /* Call the corresponding callback to inform upper layer of End of Transfer */
02027         if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
02028         {
02029           /* Disable Interrupt */
02030           SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
02031           hsmbus->PreviousState = hsmbus->State;
02032           hsmbus->State = HAL_SMBUS_STATE_READY;
02033
02034           /* Process Unlocked */
02035           __HAL_UNLOCK(hsmbus);
02036
02037           /* Call the corresponding callback to inform upper layer of End of Transfer */
02038 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
02039           hsmbus->MasterTxCpltCallback(hsmbus);
02040 #else
02041           HAL_SMBUS_MasterTxCpltCallback(hsmbus);
02042 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
02043         }
02044         else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
02045         {
02046           SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
02047           hsmbus->PreviousState = hsmbus->State;
02048           hsmbus->State = HAL_SMBUS_STATE_READY;
02049
02050           /* Process Unlocked */
02051           __HAL_UNLOCK(hsmbus);
02052
02053           /* Call the corresponding callback to inform upper layer of End of Transfer */
02054 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
02055           hsmbus->MasterRxCpltCallback(hsmbus);
02056 #else
02057           HAL_SMBUS_MasterRxCpltCallback(hsmbus);
02058 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
02059         }
02060         else
02061         {
02062           /* Nothing to do */
02063         }
02064       }
02065       else
02066       {
02067         /* Nothing to do */
02068       }
02069     }
02070   }
02071   else
02072   {
02073     /* Nothing to do */
02074   }
02075
02076   /* Process Unlocked */
02077   __HAL_UNLOCK(hsmbus);
02078
02079   return HAL_OK;
02080 }
02081 /**
02082   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
02083   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
02084   *                the configuration information for the specified SMBUS.
02085   * @param  StatusFlags Value of Interrupt Flags.
02086   * @retval HAL status
02087   */
02088 static HAL_StatusTypeDef SMBUS_Slave_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
02089 {
02090   uint8_t TransferDirection;
02091   uint16_t SlaveAddrCode;
02092
02093   /* Process Locked */
02094   __HAL_LOCK(hsmbus);
02095
02096   if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_AF) != RESET)
02097   {
02098     /* Check that SMBUS transfer finished */
02099     /* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */
02100     /* Mean XferCount == 0*/
02101     /* So clear Flag NACKF only */
02102     if (hsmbus->XferCount == 0U)
02103     {
02104       /* Clear NACK Flag */
02105       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
02106
02107       /* Process Unlocked */
02108       __HAL_UNLOCK(hsmbus);
02109     }
02110     else
02111     {
02112       /* if no, error usecase, a Non-Acknowledge of last Data is generated by the HOST*/
02113       /* Clear NACK Flag */
02114       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
02115
02116       /* Set HAL State to "Idle" State, mean to LISTEN state */
02117       /* So reset Slave Busy state */
02118       hsmbus->PreviousState = hsmbus->State;
02119       hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
02120       hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
02121
02122       /* Disable RX/TX Interrupts, keep only ADDR Interrupt */
02123       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
02124
02125       /* Set ErrorCode corresponding to a Non-Acknowledge */
02126       hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
02127
02128       /* Process Unlocked */
02129       __HAL_UNLOCK(hsmbus);
02130
02131       /* Call the Error callback to inform upper layer */
02132 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
02133       hsmbus->ErrorCallback(hsmbus);
02134 #else
02135       HAL_SMBUS_ErrorCallback(hsmbus);
02136 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
02137     }
02138   }
02139   else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_ADDR) != RESET)
02140   {
02141     TransferDirection = (uint8_t)(SMBUS_GET_DIR(hsmbus));
02142     SlaveAddrCode = (uint16_t)(SMBUS_GET_ADDR_MATCH(hsmbus));
02143
02144     /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/
02145     /* Other ADDRInterrupt will be treat in next Listen usecase */
02146     __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_ADDRI);
02147
02148     /* Process Unlocked */
02149     __HAL_UNLOCK(hsmbus);
02150
02151     /* Call Slave Addr callback */
02152 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
02153     hsmbus->AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
02154 #else
02155     HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
02156 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
02157   }
02158   else if ((SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET))
02159   {
02160     if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
02161     {
02162       /* Read data from RXDR */
02163       *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
02164
02165       /* Increment Buffer pointer */
02166       hsmbus->pBuffPtr++;
02167
02168       hsmbus->XferSize--;
02169       hsmbus->XferCount--;
02170
02171       if (hsmbus->XferCount == 1U)
02172       {
02173         /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */
02174         /* or only the last Byte of Transfer */
02175         /* So reset the RELOAD bit mode */
02176         hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE;
02177         SMBUS_TransferConfig(hsmbus, 0, 1, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
02178       }
02179       else if (hsmbus->XferCount == 0U)
02180       {
02181         /* Last Byte is received, disable Interrupt */
02182         SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
02183
02184         /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */
02185         hsmbus->PreviousState = hsmbus->State;
02186         hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
02187
02188         /* Process Unlocked */
02189         __HAL_UNLOCK(hsmbus);
02190
02191         /* Call the corresponding callback to inform upper layer of End of Transfer */
02192 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
02193         hsmbus->SlaveRxCpltCallback(hsmbus);
02194 #else
02195         HAL_SMBUS_SlaveRxCpltCallback(hsmbus);
02196 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
02197       }
02198       else
02199       {
02200         /* Set Reload for next Bytes */
02201         SMBUS_TransferConfig(hsmbus, 0, 1, SMBUS_RELOAD_MODE  | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
02202
02203         /* Ack last Byte Read */
02204         hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
02205       }
02206     }
02207     else if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
02208     {
02209       if ((hsmbus->XferCount != 0U) && (hsmbus->XferSize == 0U))
02210       {
02211         if (hsmbus->XferCount > MAX_NBYTE_SIZE)
02212         {
02213           SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
02214           hsmbus->XferSize = MAX_NBYTE_SIZE;
02215         }
02216         else
02217         {
02218           hsmbus->XferSize = hsmbus->XferCount;
02219           SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
02220           /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
02221           /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
02222           if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
02223           {
02224             hsmbus->XferSize--;
02225             hsmbus->XferCount--;
02226           }
02227         }
02228       }
02229     }
02230     else
02231     {
02232       /* Nothing to do */
02233     }
02234   }
02235   else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TXIS) != RESET)
02236   {
02237     /* Write data to TXDR only if XferCount not reach "0" */
02238     /* A TXIS flag can be set, during STOP treatment      */
02239     /* Check if all Data have already been sent */
02240     /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
02241     if (hsmbus->XferCount > 0U)
02242     {
02243       /* Write data to TXDR */
02244       hsmbus->Instance->TXDR = *hsmbus->pBuffPtr;
02245
02246       /* Increment Buffer pointer */
02247       hsmbus->pBuffPtr++;
02248
02249       hsmbus->XferCount--;
02250       hsmbus->XferSize--;
02251     }
02252
02253     if (hsmbus->XferCount == 0U)
02254     {
02255       /* Last Byte is Transmitted */
02256       /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */
02257       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
02258       hsmbus->PreviousState = hsmbus->State;
02259       hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
02260
02261       /* Process Unlocked */
02262       __HAL_UNLOCK(hsmbus);
02263
02264       /* Call the corresponding callback to inform upper layer of End of Transfer */
02265 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
02266       hsmbus->SlaveTxCpltCallback(hsmbus);
02267 #else
02268       HAL_SMBUS_SlaveTxCpltCallback(hsmbus);
02269 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
02270     }
02271   }
02272   else
02273   {
02274     /* Nothing to do */
02275   }
02276
02277   /* Check if STOPF is set */
02278   if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_STOPF) != RESET)
02279   {
02280     if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
02281     {
02282       /* Store Last receive data if any */
02283       if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
02284       {
02285         /* Read data from RXDR */
02286         *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
02287
02288         /* Increment Buffer pointer */
02289         hsmbus->pBuffPtr++;
02290
02291         if ((hsmbus->XferSize > 0U))
02292         {
02293           hsmbus->XferSize--;
02294           hsmbus->XferCount--;
02295         }
02296       }
02297
02298       /* Disable RX and TX Interrupts */
02299       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
02300
02301       /* Disable ADDR Interrupt */
02302       SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
02303
02304       /* Disable Address Acknowledge */
02305       hsmbus->Instance->CR2 |= I2C_CR2_NACK;
02306
02307       /* Clear Configuration Register 2 */
02308       SMBUS_RESET_CR2(hsmbus);
02309
02310       /* Clear STOP Flag */
02311       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
02312
02313       /* Clear ADDR flag */
02314       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
02315
02316       hsmbus->XferOptions = 0;
02317       hsmbus->PreviousState = hsmbus->State;
02318       hsmbus->State = HAL_SMBUS_STATE_READY;
02319
02320       /* Process Unlocked */
02321       __HAL_UNLOCK(hsmbus);
02322
02323       /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
02324 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
02325       hsmbus->ListenCpltCallback(hsmbus);
02326 #else
02327       HAL_SMBUS_ListenCpltCallback(hsmbus);
02328 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
02329     }
02330   }
02331
02332   /* Process Unlocked */
02333   __HAL_UNLOCK(hsmbus);
02334
02335   return HAL_OK;
02336 }
02337 /**
02338   * @brief  Manage the enabling of Interrupts.
02339   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
02340   *                the configuration information for the specified SMBUS.
02341   * @param  InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
02342   * @retval HAL status
02343   */
02344 static void SMBUS_Enable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
02345 {
02346   uint32_t tmpisr = 0UL;
02347
02348   if ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)
02349   {
02350     /* Enable ERR interrupt */
02351     tmpisr |= SMBUS_IT_ERRI;
02352   }
02353
02354   if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
02355   {
02356     /* Enable ADDR, STOP interrupt */
02357     tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_ERRI;
02358   }
02359
02360   if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
02361   {
02362     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
02363     tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI;
02364   }
02365
02366   if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
02367   {
02368     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
02369     tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI;
02370   }
02371
02372   /* Enable interrupts only at the end */
02373   /* to avoid the risk of SMBUS interrupt handle execution before */
02374   /* all interrupts requested done */
02375   __HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr);
02376 }
02377 /**
02378   * @brief  Manage the disabling of Interrupts.
02379   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
02380   *                the configuration information for the specified SMBUS.
02381   * @param  InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
02382   * @retval HAL status
02383   */
02384 static void SMBUS_Disable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
02385 {
02386   uint32_t tmpisr = 0UL;
02387   uint32_t tmpstate = hsmbus->State;
02388
02389   if ((tmpstate == HAL_SMBUS_STATE_READY) && ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT))
02390   {
02391     /* Disable ERR interrupt */
02392     tmpisr |= SMBUS_IT_ERRI;
02393   }
02394
02395   if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
02396   {
02397     /* Disable TC, STOP, NACK and TXI interrupt */
02398     tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI;
02399
02400     if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL)
02401         && ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
02402     {
02403       /* Disable ERR interrupt */
02404       tmpisr |= SMBUS_IT_ERRI;
02405     }
02406
02407     if ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
02408     {
02409       /* Disable STOP and NACK interrupt */
02410       tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
02411     }
02412   }
02413
02414   if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
02415   {
02416     /* Disable TC, STOP, NACK and RXI interrupt */
02417     tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI;
02418
02419     if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL)
02420         && ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
02421     {
02422       /* Disable ERR interrupt */
02423       tmpisr |= SMBUS_IT_ERRI;
02424     }
02425
02426     if ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
02427     {
02428       /* Disable STOP and NACK interrupt */
02429       tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
02430     }
02431   }
02432
02433   if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
02434   {
02435     /* Disable ADDR, STOP and NACK interrupt */
02436     tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI;
02437
02438     if (SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL)
02439     {
02440       /* Disable ERR interrupt */
02441       tmpisr |= SMBUS_IT_ERRI;
02442     }
02443   }
02444
02445   /* Disable interrupts only at the end */
02446   /* to avoid a breaking situation like at "t" time */
02447   /* all disable interrupts request are not done */
02448   __HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr);
02449 }
02450
02451 /**
02452   * @brief  SMBUS interrupts error handler.
02453   * @param  hsmbus SMBUS handle.
02454   * @retval None
02455   */
02456 static void SMBUS_ITErrorHandler(struct __SMBUS_HandleTypeDef *hsmbus)
02457 {
02458   uint32_t itflags   = READ_REG(hsmbus->Instance->ISR);
02459   uint32_t itsources = READ_REG(hsmbus->Instance->CR1);
02460   uint32_t tmpstate;
02461   uint32_t tmperror;
02462
02463   /* SMBUS Bus error interrupt occurred ------------------------------------*/
02464   if (((itflags & SMBUS_FLAG_BERR) == SMBUS_FLAG_BERR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
02465   {
02466     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR;
02467
02468     /* Clear BERR flag */
02469     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR);
02470   }
02471
02472   /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/
02473   if (((itflags & SMBUS_FLAG_OVR) == SMBUS_FLAG_OVR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
02474   {
02475     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR;
02476
02477     /* Clear OVR flag */
02478     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR);
02479   }
02480
02481   /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/
02482   if (((itflags & SMBUS_FLAG_ARLO) == SMBUS_FLAG_ARLO) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
02483   {
02484     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO;
02485
02486     /* Clear ARLO flag */
02487     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO);
02488   }
02489
02490   /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/
02491   if (((itflags & SMBUS_FLAG_TIMEOUT) == SMBUS_FLAG_TIMEOUT) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
02492   {
02493     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT;
02494
02495     /* Clear TIMEOUT flag */
02496     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT);
02497   }
02498
02499   /* SMBUS Alert error interrupt occurred -----------------------------------------------*/
02500   if (((itflags & SMBUS_FLAG_ALERT) == SMBUS_FLAG_ALERT) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
02501   {
02502     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT;
02503
02504     /* Clear ALERT flag */
02505     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
02506   }
02507
02508   /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/
02509   if (((itflags & SMBUS_FLAG_PECERR) == SMBUS_FLAG_PECERR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
02510   {
02511     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR;
02512
02513     /* Clear PEC error flag */
02514     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
02515   }
02516
02517   /* Store current volatile hsmbus->State, misra rule */
02518   tmperror = hsmbus->ErrorCode;
02519
02520   /* Call the Error Callback in case of Error detected */
02521   if ((tmperror != HAL_SMBUS_ERROR_NONE) && (tmperror != HAL_SMBUS_ERROR_ACKF))
02522   {
02523     /* Do not Reset the HAL state in case of ALERT error */
02524     if ((tmperror & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT)
02525     {
02526       /* Store current volatile hsmbus->State, misra rule */
02527       tmpstate = hsmbus->State;
02528
02529       if (((tmpstate & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
02530           || ((tmpstate & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX))
02531       {
02532         /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */
02533         /* keep HAL_SMBUS_STATE_LISTEN if set */
02534         hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
02535         hsmbus->State = HAL_SMBUS_STATE_LISTEN;
02536       }
02537     }
02538
02539     /* Call the Error callback to inform upper layer */
02540 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
02541     hsmbus->ErrorCallback(hsmbus);
02542 #else
02543     HAL_SMBUS_ErrorCallback(hsmbus);
02544 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
02545   }
02546 }
02547
02548 /**
02549   * @brief  Handle SMBUS Communication Timeout.
02550   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
02551   *                the configuration information for the specified SMBUS.
02552   * @param  Flag Specifies the SMBUS flag to check.
02553   * @param  Status The new Flag status (SET or RESET).
02554   * @param  Timeout Timeout duration
02555   * @retval HAL status
02556   */
02557 static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
02558 {
02559   uint32_t tickstart = HAL_GetTick();
02560
02561   /* Wait until flag is set */
02562   while ((FlagStatus)(__HAL_SMBUS_GET_FLAG(hsmbus, Flag)) == Status)
02563   {
02564     /* Check for the Timeout */
02565     if (Timeout != HAL_MAX_DELAY)
02566     {
02567       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
02568       {
02569         hsmbus->PreviousState = hsmbus->State;
02570         hsmbus->State = HAL_SMBUS_STATE_READY;
02571
02572         /* Update SMBUS error code */
02573         hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT;
02574
02575         /* Process Unlocked */
02576         __HAL_UNLOCK(hsmbus);
02577
02578         return HAL_ERROR;
02579       }
02580     }
02581   }
02582
02583   return HAL_OK;
02584 }
02585
02586 /**
02587   * @brief  Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
02588   * @param  hsmbus SMBUS handle.
02589   * @param  DevAddress specifies the slave address to be programmed.
02590   * @param  Size specifies the number of bytes to be programmed.
02591   *   This parameter must be a value between 0 and 255.
02592   * @param  Mode New state of the SMBUS START condition generation.
02593   *   This parameter can be one or a combination  of the following values:
02594   *     @arg @ref SMBUS_RELOAD_MODE Enable Reload mode.
02595   *     @arg @ref SMBUS_AUTOEND_MODE Enable Automatic end mode.
02596   *     @arg @ref SMBUS_SOFTEND_MODE Enable Software end mode and Reload mode.
02597   *     @arg @ref SMBUS_SENDPEC_MODE Enable Packet Error Calculation mode.
02598   * @param  Request New state of the SMBUS START condition generation.
02599   *   This parameter can be one of the following values:
02600   *     @arg @ref SMBUS_NO_STARTSTOP Don't Generate stop and start condition.
02601   *     @arg @ref SMBUS_GENERATE_STOP Generate stop condition (Size should be set to 0).
02602   *     @arg @ref SMBUS_GENERATE_START_READ Generate Restart for read request.
02603   *     @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request.
02604   * @retval None
02605   */
02606 static void SMBUS_TransferConfig(struct __SMBUS_HandleTypeDef *hsmbus,  uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
02607 {
02608   /* Check the parameters */
02609   assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
02610   assert_param(IS_SMBUS_TRANSFER_MODE(Mode));
02611   assert_param(IS_SMBUS_TRANSFER_REQUEST(Request));
02612
02613   /* update CR2 register */
02614   MODIFY_REG(hsmbus->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP  | I2C_CR2_PECBYTE)), \
02615              (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
02616 }
02617
02618 /**
02619   * @brief  Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions.
02620   * @param  hsmbus SMBUS handle.
02621   * @retval None
02622   */
02623 static void SMBUS_ConvertOtherXferOptions(struct __SMBUS_HandleTypeDef *hsmbus)
02624 {
02625   /* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC   */
02626   /* it request implicitly to generate a restart condition */
02627   /* set XferOptions to SMBUS_FIRST_FRAME                  */
02628   if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_NO_PEC)
02629   {
02630     hsmbus->XferOptions = SMBUS_FIRST_FRAME;
02631   }
02632   /* else if user set XferOptions to SMBUS_OTHER_FRAME_WITH_PEC */
02633   /* it request implicitly to generate a restart condition      */
02634   /* set XferOptions to SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE  */
02635   else if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_WITH_PEC)
02636   {
02637     hsmbus->XferOptions = SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE;
02638   }
02639   /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_NO_PEC */
02640   /* it request implicitly to generate a restart condition             */
02641   /* then generate a stop condition at the end of transfer             */
02642   /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_NO_PEC              */
02643   else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)
02644   {
02645     hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_NO_PEC;
02646   }
02647   /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC */
02648   /* it request implicitly to generate a restart condition               */
02649   /* then generate a stop condition at the end of transfer               */
02650   /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC              */
02651   else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)
02652   {
02653     hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC;
02654   }
02655   else
02656   {
02657     /* Nothing to do */
02658   }
02659 }
02660 /**
02661   * @}
02662   */
02663
02664 #endif /* HAL_SMBUS_MODULE_ENABLED */
02665 /**
02666   * @}
02667   */
02668
02669 /**
02670   * @}
02671   */
02672
02673 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:35 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_smbus.h Source File

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stm32wbxx_hal_smbus.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_smbus.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SMBUS HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_SMBUS_H
00022 #define STM32WBxx_HAL_SMBUS_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 /** @addtogroup STM32WBxx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup SMBUS
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup SMBUS_Exported_Types SMBUS Exported Types
00041   * @{
00042   */
00043
00044 /** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition
00045   * @brief  SMBUS Configuration Structure definition
00046   * @{
00047   */
00048 typedef struct
00049 {
00050   uint32_t Timing;                 /*!< Specifies the SMBUS_TIMINGR_register value.
00051                                      This parameter calculated by referring to SMBUS initialization
00052                                             section in Reference manual */
00053   uint32_t AnalogFilter;           /*!< Specifies if Analog Filter is enable or not.
00054                                      This parameter can be a value of @ref SMBUS_Analog_Filter */
00055
00056   uint32_t OwnAddress1;            /*!< Specifies the first device own address.
00057                                      This parameter can be a 7-bit or 10-bit address. */
00058
00059   uint32_t AddressingMode;         /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
00060                                      This parameter can be a value of @ref SMBUS_addressing_mode */
00061
00062   uint32_t DualAddressMode;        /*!< Specifies if dual addressing mode is selected.
00063                                      This parameter can be a value of @ref SMBUS_dual_addressing_mode */
00064
00065   uint32_t OwnAddress2;            /*!< Specifies the second device own address if dual addressing mode is selected
00066                                      This parameter can be a 7-bit address. */
00067
00068   uint32_t OwnAddress2Masks;       /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
00069                                      This parameter can be a value of @ref SMBUS_own_address2_masks. */
00070
00071   uint32_t GeneralCallMode;        /*!< Specifies if general call mode is selected.
00072                                      This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
00073
00074   uint32_t NoStretchMode;          /*!< Specifies if nostretch mode is selected.
00075                                      This parameter can be a value of @ref SMBUS_nostretch_mode */
00076
00077   uint32_t PacketErrorCheckMode;   /*!< Specifies if Packet Error Check mode is selected.
00078                                      This parameter can be a value of @ref SMBUS_packet_error_check_mode */
00079
00080   uint32_t PeripheralMode;         /*!< Specifies which mode of Periphal is selected.
00081                                      This parameter can be a value of @ref SMBUS_peripheral_mode */
00082
00083   uint32_t SMBusTimeout;           /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
00084                                       (Enable bits and different timeout values)
00085                                      This parameter calculated by referring to SMBUS initialization
00086                                          section in Reference manual */
00087 } SMBUS_InitTypeDef;
00088 /**
00089   * @}
00090   */
00091
00092 /** @defgroup HAL_state_definition HAL state definition
00093   * @brief  HAL State definition
00094   * @{
00095   */
00096 #define HAL_SMBUS_STATE_RESET           (0x00000000U)  /*!< SMBUS not yet initialized or disabled         */
00097 #define HAL_SMBUS_STATE_READY           (0x00000001U)  /*!< SMBUS initialized and ready for use           */
00098 #define HAL_SMBUS_STATE_BUSY            (0x00000002U)  /*!< SMBUS internal process is ongoing             */
00099 #define HAL_SMBUS_STATE_MASTER_BUSY_TX  (0x00000012U)  /*!< Master Data Transmission process is ongoing   */
00100 #define HAL_SMBUS_STATE_MASTER_BUSY_RX  (0x00000022U)  /*!< Master Data Reception process is ongoing      */
00101 #define HAL_SMBUS_STATE_SLAVE_BUSY_TX   (0x00000032U)  /*!< Slave Data Transmission process is ongoing    */
00102 #define HAL_SMBUS_STATE_SLAVE_BUSY_RX   (0x00000042U)  /*!< Slave Data Reception process is ongoing       */
00103 #define HAL_SMBUS_STATE_TIMEOUT         (0x00000003U)  /*!< Timeout state                                 */
00104 #define HAL_SMBUS_STATE_ERROR           (0x00000004U)  /*!< Reception process is ongoing                  */
00105 #define HAL_SMBUS_STATE_LISTEN          (0x00000008U)   /*!< Address Listen Mode is ongoing                */
00106 /**
00107   * @}
00108   */
00109
00110 /** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition
00111   * @brief  SMBUS Error Code definition
00112   * @{
00113   */
00114 #define HAL_SMBUS_ERROR_NONE            (0x00000000U)    /*!< No error             */
00115 #define HAL_SMBUS_ERROR_BERR            (0x00000001U)    /*!< BERR error           */
00116 #define HAL_SMBUS_ERROR_ARLO            (0x00000002U)    /*!< ARLO error           */
00117 #define HAL_SMBUS_ERROR_ACKF            (0x00000004U)    /*!< ACKF error           */
00118 #define HAL_SMBUS_ERROR_OVR             (0x00000008U)    /*!< OVR error            */
00119 #define HAL_SMBUS_ERROR_HALTIMEOUT      (0x00000010U)    /*!< Timeout error        */
00120 #define HAL_SMBUS_ERROR_BUSTIMEOUT      (0x00000020U)    /*!< Bus Timeout error    */
00121 #define HAL_SMBUS_ERROR_ALERT           (0x00000040U)    /*!< Alert error          */
00122 #define HAL_SMBUS_ERROR_PECERR          (0x00000080U)    /*!< PEC error            */
00123 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
00124 #define HAL_SMBUS_ERROR_INVALID_CALLBACK  (0x00000100U)    /*!< Invalid Callback error */
00125 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
00126 #define HAL_SMBUS_ERROR_INVALID_PARAM    (0x00000200U)   /*!< Invalid Parameters error */
00127 /**
00128   * @}
00129   */
00130
00131 /** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition
00132   * @brief  SMBUS handle Structure definition
00133   * @{
00134   */
00135 typedef struct __SMBUS_HandleTypeDef
00136 {
00137   I2C_TypeDef                  *Instance;       /*!< SMBUS registers base address       */
00138
00139   SMBUS_InitTypeDef            Init;            /*!< SMBUS communication parameters     */
00140
00141   uint8_t                      *pBuffPtr;       /*!< Pointer to SMBUS transfer buffer   */
00142
00143   uint16_t                     XferSize;        /*!< SMBUS transfer size                */
00144
00145   __IO uint16_t                XferCount;       /*!< SMBUS transfer counter             */
00146
00147   __IO uint32_t                XferOptions;     /*!< SMBUS transfer options             */
00148
00149   __IO uint32_t                PreviousState;   /*!< SMBUS communication Previous state */
00150
00151   HAL_LockTypeDef              Lock;            /*!< SMBUS locking object               */
00152
00153   __IO uint32_t                State;           /*!< SMBUS communication state          */
00154
00155   __IO uint32_t                ErrorCode;       /*!< SMBUS Error code                   */
00156
00157 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
00158   void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);           /*!< SMBUS Master Tx Transfer completed callback */
00159   void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);           /*!< SMBUS Master Rx Transfer completed callback */
00160   void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);            /*!< SMBUS Slave Tx Transfer completed callback  */
00161   void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);            /*!< SMBUS Slave Rx Transfer completed callback  */
00162   void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);             /*!< SMBUS Listen Complete callback              */
00163   void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus);                  /*!< SMBUS Error callback                        */
00164
00165   void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);  /*!< SMBUS Slave Address Match callback */
00166
00167   void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);                /*!< SMBUS Msp Init callback                     */
00168   void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);              /*!< SMBUS Msp DeInit callback                   */
00169
00170 #endif  /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
00171 } SMBUS_HandleTypeDef;
00172
00173 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
00174 /**
00175   * @brief  HAL SMBUS Callback ID enumeration definition
00176   */
00177 typedef enum
00178 {
00179   HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID      = 0x00U,    /*!< SMBUS Master Tx Transfer completed callback ID  */
00180   HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID      = 0x01U,    /*!< SMBUS Master Rx Transfer completed callback ID  */
00181   HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID       = 0x02U,    /*!< SMBUS Slave Tx Transfer completed callback ID   */
00182   HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID       = 0x03U,    /*!< SMBUS Slave Rx Transfer completed callback ID   */
00183   HAL_SMBUS_LISTEN_COMPLETE_CB_ID         = 0x04U,    /*!< SMBUS Listen Complete callback ID               */
00184   HAL_SMBUS_ERROR_CB_ID                   = 0x05U,    /*!< SMBUS Error callback ID                         */
00185
00186   HAL_SMBUS_MSPINIT_CB_ID                 = 0x06U,    /*!< SMBUS Msp Init callback ID                      */
00187   HAL_SMBUS_MSPDEINIT_CB_ID               = 0x07U     /*!< SMBUS Msp DeInit callback ID                    */
00188
00189 } HAL_SMBUS_CallbackIDTypeDef;
00190
00191 /**
00192   * @brief  HAL SMBUS Callback pointer definition
00193   */
00194 typedef  void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus); /*!< pointer to an SMBUS callback function */
00195 typedef  void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an SMBUS Address Match callback function */
00196
00197 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
00198 /**
00199   * @}
00200   */
00201
00202 /**
00203   * @}
00204   */
00205 /* Exported constants --------------------------------------------------------*/
00206
00207 /** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
00208   * @{
00209   */
00210
00211 /** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
00212   * @{
00213   */
00214 #define SMBUS_ANALOGFILTER_ENABLE               (0x00000000U)
00215 #define SMBUS_ANALOGFILTER_DISABLE              I2C_CR1_ANFOFF
00216 /**
00217   * @}
00218   */
00219
00220 /** @defgroup SMBUS_addressing_mode SMBUS addressing mode
00221   * @{
00222   */
00223 #define SMBUS_ADDRESSINGMODE_7BIT               (0x00000001U)
00224 #define SMBUS_ADDRESSINGMODE_10BIT              (0x00000002U)
00225 /**
00226   * @}
00227   */
00228
00229 /** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode
00230   * @{
00231   */
00232
00233 #define SMBUS_DUALADDRESS_DISABLE               (0x00000000U)
00234 #define SMBUS_DUALADDRESS_ENABLE                I2C_OAR2_OA2EN
00235 /**
00236   * @}
00237   */
00238
00239 /** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks
00240   * @{
00241   */
00242
00243 #define SMBUS_OA2_NOMASK                        ((uint8_t)0x00U)
00244 #define SMBUS_OA2_MASK01                        ((uint8_t)0x01U)
00245 #define SMBUS_OA2_MASK02                        ((uint8_t)0x02U)
00246 #define SMBUS_OA2_MASK03                        ((uint8_t)0x03U)
00247 #define SMBUS_OA2_MASK04                        ((uint8_t)0x04U)
00248 #define SMBUS_OA2_MASK05                        ((uint8_t)0x05U)
00249 #define SMBUS_OA2_MASK06                        ((uint8_t)0x06U)
00250 #define SMBUS_OA2_MASK07                        ((uint8_t)0x07U)
00251 /**
00252   * @}
00253   */
00254
00255
00256 /** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
00257   * @{
00258   */
00259 #define SMBUS_GENERALCALL_DISABLE               (0x00000000U)
00260 #define SMBUS_GENERALCALL_ENABLE                I2C_CR1_GCEN
00261 /**
00262   * @}
00263   */
00264
00265 /** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode
00266   * @{
00267   */
00268 #define SMBUS_NOSTRETCH_DISABLE                 (0x00000000U)
00269 #define SMBUS_NOSTRETCH_ENABLE                  I2C_CR1_NOSTRETCH
00270 /**
00271   * @}
00272   */
00273
00274 /** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
00275   * @{
00276   */
00277 #define SMBUS_PEC_DISABLE                       (0x00000000U)
00278 #define SMBUS_PEC_ENABLE                        I2C_CR1_PECEN
00279 /**
00280   * @}
00281   */
00282
00283 /** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode
00284   * @{
00285   */
00286 #define SMBUS_PERIPHERAL_MODE_SMBUS_HOST        I2C_CR1_SMBHEN
00287 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE       (0x00000000U)
00288 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP   I2C_CR1_SMBDEN
00289 /**
00290   * @}
00291   */
00292
00293 /** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition
00294   * @{
00295   */
00296
00297 #define  SMBUS_SOFTEND_MODE                     (0x00000000U)
00298 #define  SMBUS_RELOAD_MODE                      I2C_CR2_RELOAD
00299 #define  SMBUS_AUTOEND_MODE                     I2C_CR2_AUTOEND
00300 #define  SMBUS_SENDPEC_MODE                     I2C_CR2_PECBYTE
00301 /**
00302   * @}
00303   */
00304
00305 /** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition
00306   * @{
00307   */
00308
00309 #define  SMBUS_NO_STARTSTOP                     (0x00000000U)
00310 #define  SMBUS_GENERATE_STOP                    (uint32_t)(0x80000000U | I2C_CR2_STOP)
00311 #define  SMBUS_GENERATE_START_READ              (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
00312 #define  SMBUS_GENERATE_START_WRITE             (uint32_t)(0x80000000U | I2C_CR2_START)
00313 /**
00314   * @}
00315   */
00316
00317 /** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition
00318   * @{
00319   */
00320
00321 /* List of XferOptions in usage of :
00322  * 1- Restart condition when direction change
00323  * 2- No Restart condition in other use cases
00324  */
00325 #define  SMBUS_FIRST_FRAME                      SMBUS_SOFTEND_MODE
00326 #define  SMBUS_NEXT_FRAME                       ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
00327 #define  SMBUS_FIRST_AND_LAST_FRAME_NO_PEC      SMBUS_AUTOEND_MODE
00328 #define  SMBUS_LAST_FRAME_NO_PEC                SMBUS_AUTOEND_MODE
00329 #define  SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC    ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
00330 #define  SMBUS_LAST_FRAME_WITH_PEC              ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
00331
00332 /* List of XferOptions in usage of :
00333  * 1- Restart condition in all use cases (direction change or not)
00334  */
00335 #define  SMBUS_OTHER_FRAME_NO_PEC               (0x000000AAU)
00336 #define  SMBUS_OTHER_FRAME_WITH_PEC             (0x0000AA00U)
00337 #define  SMBUS_OTHER_AND_LAST_FRAME_NO_PEC      (0x00AA0000U)
00338 #define  SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC    (0xAA000000U)
00339 /**
00340   * @}
00341   */
00342
00343 /** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition
00344   * @brief SMBUS Interrupt definition
00345   *        Elements values convention: 0xXXXXXXXX
00346   *           - XXXXXXXX  : Interrupt control mask
00347   * @{
00348   */
00349 #define SMBUS_IT_ERRI                           I2C_CR1_ERRIE
00350 #define SMBUS_IT_TCI                            I2C_CR1_TCIE
00351 #define SMBUS_IT_STOPI                          I2C_CR1_STOPIE
00352 #define SMBUS_IT_NACKI                          I2C_CR1_NACKIE
00353 #define SMBUS_IT_ADDRI                          I2C_CR1_ADDRIE
00354 #define SMBUS_IT_RXI                            I2C_CR1_RXIE
00355 #define SMBUS_IT_TXI                            I2C_CR1_TXIE
00356 #define SMBUS_IT_TX                             (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
00357 #define SMBUS_IT_RX                             (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
00358 #define SMBUS_IT_ALERT                          (SMBUS_IT_ERRI)
00359 #define SMBUS_IT_ADDR                           (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
00360 /**
00361   * @}
00362   */
00363
00364 /** @defgroup SMBUS_Flag_definition SMBUS Flag definition
00365   * @brief Flag definition
00366   *        Elements values convention: 0xXXXXYYYY
00367   *           - XXXXXXXX  : Flag mask
00368   * @{
00369   */
00370
00371 #define  SMBUS_FLAG_TXE                         I2C_ISR_TXE
00372 #define  SMBUS_FLAG_TXIS                        I2C_ISR_TXIS
00373 #define  SMBUS_FLAG_RXNE                        I2C_ISR_RXNE
00374 #define  SMBUS_FLAG_ADDR                        I2C_ISR_ADDR
00375 #define  SMBUS_FLAG_AF                          I2C_ISR_NACKF
00376 #define  SMBUS_FLAG_STOPF                       I2C_ISR_STOPF
00377 #define  SMBUS_FLAG_TC                          I2C_ISR_TC
00378 #define  SMBUS_FLAG_TCR                         I2C_ISR_TCR
00379 #define  SMBUS_FLAG_BERR                        I2C_ISR_BERR
00380 #define  SMBUS_FLAG_ARLO                        I2C_ISR_ARLO
00381 #define  SMBUS_FLAG_OVR                         I2C_ISR_OVR
00382 #define  SMBUS_FLAG_PECERR                      I2C_ISR_PECERR
00383 #define  SMBUS_FLAG_TIMEOUT                     I2C_ISR_TIMEOUT
00384 #define  SMBUS_FLAG_ALERT                       I2C_ISR_ALERT
00385 #define  SMBUS_FLAG_BUSY                        I2C_ISR_BUSY
00386 #define  SMBUS_FLAG_DIR                         I2C_ISR_DIR
00387 /**
00388   * @}
00389   */
00390
00391 /**
00392   * @}
00393   */
00394
00395 /* Exported macros ------------------------------------------------------------*/
00396 /** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
00397   * @{
00398   */
00399
00400 /** @brief  Reset SMBUS handle state.
00401   * @param  __HANDLE__ specifies the SMBUS Handle.
00402   * @retval None
00403   */
00404 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
00405 #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__)           do{                                                   \
00406                                                                 (__HANDLE__)->State = HAL_SMBUS_STATE_RESET;       \
00407                                                                 (__HANDLE__)->MspInitCallback = NULL;            \
00408                                                                 (__HANDLE__)->MspDeInitCallback = NULL;          \
00409                                                              } while(0)
00410 #else
00411 #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__)         ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
00412 #endif
00413
00414 /** @brief  Enable the specified SMBUS interrupts.
00415   * @param  __HANDLE__ specifies the SMBUS Handle.
00416   * @param  __INTERRUPT__ specifies the interrupt source to enable.
00417   *        This parameter can be one of the following values:
00418   *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable
00419   *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable
00420   *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
00421   *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
00422   *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
00423   *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
00424   *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
00425   *
00426   * @retval None
00427   */
00428 #define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
00429
00430 /** @brief  Disable the specified SMBUS interrupts.
00431   * @param  __HANDLE__ specifies the SMBUS Handle.
00432   * @param  __INTERRUPT__ specifies the interrupt source to disable.
00433   *        This parameter can be one of the following values:
00434   *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable
00435   *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable
00436   *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
00437   *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
00438   *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
00439   *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
00440   *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
00441   *
00442   * @retval None
00443   */
00444 #define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
00445
00446 /** @brief  Check whether the specified SMBUS interrupt source is enabled or not.
00447   * @param  __HANDLE__ specifies the SMBUS Handle.
00448   * @param  __INTERRUPT__ specifies the SMBUS interrupt source to check.
00449   *          This parameter can be one of the following values:
00450   *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable
00451   *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable
00452   *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
00453   *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
00454   *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
00455   *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
00456   *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
00457   *
00458   * @retval The new state of __IT__ (SET or RESET).
00459   */
00460 #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00461
00462 /** @brief  Check whether the specified SMBUS flag is set or not.
00463   * @param  __HANDLE__ specifies the SMBUS Handle.
00464   * @param  __FLAG__ specifies the flag to check.
00465   *        This parameter can be one of the following values:
00466   *            @arg @ref SMBUS_FLAG_TXE     Transmit data register empty
00467   *            @arg @ref SMBUS_FLAG_TXIS    Transmit interrupt status
00468   *            @arg @ref SMBUS_FLAG_RXNE    Receive data register not empty
00469   *            @arg @ref SMBUS_FLAG_ADDR    Address matched (slave mode)
00470   *            @arg @ref SMBUS_FLAG_AF      NACK received flag
00471   *            @arg @ref SMBUS_FLAG_STOPF   STOP detection flag
00472   *            @arg @ref SMBUS_FLAG_TC      Transfer complete (master mode)
00473   *            @arg @ref SMBUS_FLAG_TCR     Transfer complete reload
00474   *            @arg @ref SMBUS_FLAG_BERR    Bus error
00475   *            @arg @ref SMBUS_FLAG_ARLO    Arbitration lost
00476   *            @arg @ref SMBUS_FLAG_OVR     Overrun/Underrun
00477   *            @arg @ref SMBUS_FLAG_PECERR  PEC error in reception
00478   *            @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
00479   *            @arg @ref SMBUS_FLAG_ALERT   SMBus alert
00480   *            @arg @ref SMBUS_FLAG_BUSY    Bus busy
00481   *            @arg @ref SMBUS_FLAG_DIR     Transfer direction (slave mode)
00482   *
00483   * @retval The new state of __FLAG__ (SET or RESET).
00484   */
00485 #define SMBUS_FLAG_MASK  (0x0001FFFFU)
00486 #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
00487
00488 /** @brief  Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
00489   * @param  __HANDLE__ specifies the SMBUS Handle.
00490   * @param  __FLAG__ specifies the flag to clear.
00491   *          This parameter can be any combination of the following values:
00492   *            @arg @ref SMBUS_FLAG_ADDR    Address matched (slave mode)
00493   *            @arg @ref SMBUS_FLAG_AF      NACK received flag
00494   *            @arg @ref SMBUS_FLAG_STOPF   STOP detection flag
00495   *            @arg @ref SMBUS_FLAG_BERR    Bus error
00496   *            @arg @ref SMBUS_FLAG_ARLO    Arbitration lost
00497   *            @arg @ref SMBUS_FLAG_OVR     Overrun/Underrun
00498   *            @arg @ref SMBUS_FLAG_PECERR  PEC error in reception
00499   *            @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
00500   *            @arg @ref SMBUS_FLAG_ALERT   SMBus alert
00501   *
00502   * @retval None
00503   */
00504 #define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00505
00506 /** @brief  Enable the specified SMBUS peripheral.
00507   * @param  __HANDLE__ specifies the SMBUS Handle.
00508   * @retval None
00509   */
00510 #define __HAL_SMBUS_ENABLE(__HANDLE__)                  (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
00511
00512 /** @brief  Disable the specified SMBUS peripheral.
00513   * @param  __HANDLE__ specifies the SMBUS Handle.
00514   * @retval None
00515   */
00516 #define __HAL_SMBUS_DISABLE(__HANDLE__)                 (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
00517
00518 /** @brief  Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
00519   * @param  __HANDLE__ specifies the SMBUS Handle.
00520   * @retval None
00521   */
00522 #define __HAL_SMBUS_GENERATE_NACK(__HANDLE__)           (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
00523
00524 /**
00525   * @}
00526   */
00527
00528
00529 /* Private constants ---------------------------------------------------------*/
00530
00531 /* Private macros ------------------------------------------------------------*/
00532 /** @defgroup SMBUS_Private_Macro SMBUS Private Macros
00533   * @{
00534   */
00535
00536 #define IS_SMBUS_ANALOG_FILTER(FILTER)                  (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
00537                                                           ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
00538
00539 #define IS_SMBUS_DIGITAL_FILTER(FILTER)                 ((FILTER) <= 0x0000000FU)
00540
00541 #define IS_SMBUS_ADDRESSING_MODE(MODE)                  (((MODE) == SMBUS_ADDRESSINGMODE_7BIT)  || \
00542                                                           ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
00543
00544 #define IS_SMBUS_DUAL_ADDRESS(ADDRESS)                  (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
00545                                                           ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
00546
00547 #define IS_SMBUS_OWN_ADDRESS2_MASK(MASK)                (((MASK) == SMBUS_OA2_NOMASK)    || \
00548                                                          ((MASK) == SMBUS_OA2_MASK01)    || \
00549                                                          ((MASK) == SMBUS_OA2_MASK02)    || \
00550                                                          ((MASK) == SMBUS_OA2_MASK03)    || \
00551                                                          ((MASK) == SMBUS_OA2_MASK04)    || \
00552                                                          ((MASK) == SMBUS_OA2_MASK05)    || \
00553                                                          ((MASK) == SMBUS_OA2_MASK06)    || \
00554                                                          ((MASK) == SMBUS_OA2_MASK07))
00555
00556 #define IS_SMBUS_GENERAL_CALL(CALL)                     (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
00557                                                          ((CALL) == SMBUS_GENERALCALL_ENABLE))
00558
00559 #define IS_SMBUS_NO_STRETCH(STRETCH)                    (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
00560                                                          ((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
00561
00562 #define IS_SMBUS_PEC(PEC)                               (((PEC) == SMBUS_PEC_DISABLE) || \
00563                                                           ((PEC) == SMBUS_PEC_ENABLE))
00564
00565 #define IS_SMBUS_PERIPHERAL_MODE(MODE)                  (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST)    || \
00566                                                           ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE)  || \
00567                                                           ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
00568
00569 #define IS_SMBUS_TRANSFER_MODE(MODE)                    (((MODE) == SMBUS_RELOAD_MODE)                           || \
00570                                                           ((MODE) == SMBUS_AUTOEND_MODE)                         || \
00571                                                           ((MODE) == SMBUS_SOFTEND_MODE)                         || \
00572                                                           ((MODE) == SMBUS_SENDPEC_MODE)                         || \
00573                                                           ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE))   || \
00574                                                           ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))  || \
00575                                                           ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE))   || \
00576                                                           ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
00577
00578
00579 #define IS_SMBUS_TRANSFER_REQUEST(REQUEST)              (((REQUEST) == SMBUS_GENERATE_STOP)              || \
00580                                                           ((REQUEST) == SMBUS_GENERATE_START_READ)       || \
00581                                                           ((REQUEST) == SMBUS_GENERATE_START_WRITE)      || \
00582                                                           ((REQUEST) == SMBUS_NO_STARTSTOP))
00583
00584
00585 #define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST)      (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)       || \
00586                                                           ((REQUEST) == SMBUS_FIRST_FRAME)                       || \
00587                                                           ((REQUEST) == SMBUS_NEXT_FRAME)                        || \
00588                                                           ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC)       || \
00589                                                           ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC)                 || \
00590                                                           ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)     || \
00591                                                           ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
00592
00593 #define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC)                || \
00594                                                           ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)       || \
00595                                                           ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC)              || \
00596                                                           ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
00597
00598 #define SMBUS_RESET_CR1(__HANDLE__)                       ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
00599 #define SMBUS_RESET_CR2(__HANDLE__)                       ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
00600
00601 #define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__)     (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
00602                                                                   (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
00603
00604 #define SMBUS_GET_ADDR_MATCH(__HANDLE__)                  (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
00605 #define SMBUS_GET_DIR(__HANDLE__)                         (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
00606 #define SMBUS_GET_STOP_MODE(__HANDLE__)                   ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
00607 #define SMBUS_GET_PEC_MODE(__HANDLE__)                    ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
00608 #define SMBUS_GET_ALERT_ENABLED(__HANDLE__)                ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
00609
00610 #define SMBUS_CHECK_FLAG(__ISR__, __FLAG__)             ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
00611 #define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__)          ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
00612
00613 #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1)                         ((ADDRESS1) <= 0x000003FFU)
00614 #define IS_SMBUS_OWN_ADDRESS2(ADDRESS2)                         ((ADDRESS2) <= (uint16_t)0x00FFU)
00615
00616 /**
00617   * @}
00618   */
00619
00620 /* Exported functions --------------------------------------------------------*/
00621 /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
00622   * @{
00623   */
00624
00625 /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
00626  * @{
00627  */
00628
00629 /* Initialization and de-initialization functions  ****************************/
00630 HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
00631 HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus);
00632 void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
00633 void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
00634 HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter);
00635 HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter);
00636
00637 /* Callbacks Register/UnRegister functions  ***********************************/
00638 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
00639 HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback);
00640 HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID);
00641
00642 HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback);
00643 HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus);
00644 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
00645 /**
00646   * @}
00647   */
00648
00649 /** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
00650  * @{
00651  */
00652
00653 /* IO operation functions  *****************************************************/
00654 /** @addtogroup Blocking_mode_Polling Blocking mode Polling
00655  * @{
00656  */
00657 /******* Blocking mode: Polling */
00658 HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
00659 /**
00660   * @}
00661   */
00662
00663 /** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
00664  * @{
00665  */
00666 /******* Non-Blocking mode: Interrupt */
00667 HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00668 HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00669 HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
00670 HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00671 HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00672
00673 HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
00674 HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
00675 HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
00676 HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
00677 /**
00678   * @}
00679   */
00680
00681 /** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
00682  * @{
00683  */
00684 /******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
00685 void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
00686 void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
00687 void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
00688 void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
00689 void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
00690 void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
00691 void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
00692 void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
00693 void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
00694
00695 /**
00696   * @}
00697   */
00698
00699 /** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
00700  *  @{
00701  */
00702
00703 /* Peripheral State and Errors functions  **************************************************/
00704 uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
00705 uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
00706
00707 /**
00708   * @}
00709   */
00710
00711 /**
00712   * @}
00713   */
00714
00715 /* Private Functions ---------------------------------------------------------*/
00716 /** @defgroup SMBUS_Private_Functions SMBUS Private Functions
00717   * @{
00718   */
00719 /* Private functions are defined in stm32wbxx_hal_smbus.c file */
00720 /**
00721   * @}
00722   */
00723
00724 /**
00725   * @}
00726   */
00727
00728 /**
00729   * @}
00730   */
00731
00732 /**
00733   * @}
00734   */
00735
00736 #ifdef __cplusplus
00737 }
00738 #endif
00739
00740
00741 #endif /* STM32WBxx_HAL_SMBUS_H */
00742
00743 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:35 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_spi.c Source File

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stm32wbxx_hal_spi.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_spi.c
00004   * @author  MCD Application Team
00005   * @brief   SPI HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Serial Peripheral Interface (SPI) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral Control functions
00011   *           + Peripheral State functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                         ##### How to use this driver #####
00016   ==============================================================================
00017     [..]
00018       The SPI HAL driver can be used as follows:
00019
00020       (#) Declare a SPI_HandleTypeDef handle structure, for example:
00021           SPI_HandleTypeDef  hspi;
00022
00023       (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
00024           (##) Enable the SPIx interface clock
00025           (##) SPI pins configuration
00026               (+++) Enable the clock for the SPI GPIOs
00027               (+++) Configure these SPI pins as alternate function push-pull
00028           (##) NVIC configuration if you need to use interrupt process
00029               (+++) Configure the SPIx interrupt priority
00030               (+++) Enable the NVIC SPI IRQ handle
00031           (##) DMA Configuration if you need to use DMA process
00032               (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
00033               (+++) Enable the DMAx clock
00034               (+++) Configure the DMA handle parameters
00035               (+++) Configure the DMA Tx or Rx Stream/Channel
00036               (+++) Associate the initialized hdma_tx(or _rx)  handle to the hspi DMA Tx or Rx handle
00037               (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
00038
00039       (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
00040           management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
00041
00042       (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
00043           (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00044               by calling the customized HAL_SPI_MspInit() API.
00045      [..]
00046        Circular mode restriction:
00047       (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
00048           (##) Master 2Lines RxOnly
00049           (##) Master 1Line Rx
00050       (#) The CRC feature is not managed when the DMA circular mode is enabled
00051       (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
00052           the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
00053      [..]
00054        Master Receive mode restriction:
00055       (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or
00056           bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
00057           does not initiate a new transfer the following procedure has to be respected:
00058           (##) HAL_SPI_DeInit()
00059           (##) HAL_SPI_Init()
00060      [..]
00061        Callback registration:
00062
00063       (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
00064           allows the user to configure dynamically the driver callbacks.
00065           Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
00066
00067           Function HAL_SPI_RegisterCallback() allows to register following callbacks:
00068             (++) TxCpltCallback        : SPI Tx Completed callback
00069             (++) RxCpltCallback        : SPI Rx Completed callback
00070             (++) TxRxCpltCallback      : SPI TxRx Completed callback
00071             (++) TxHalfCpltCallback    : SPI Tx Half Completed callback
00072             (++) RxHalfCpltCallback    : SPI Rx Half Completed callback
00073             (++) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback
00074             (++) ErrorCallback         : SPI Error callback
00075             (++) AbortCpltCallback     : SPI Abort callback
00076             (++) MspInitCallback       : SPI Msp Init callback
00077             (++) MspDeInitCallback     : SPI Msp DeInit callback
00078           This function takes as parameters the HAL peripheral handle, the Callback ID
00079           and a pointer to the user callback function.
00080
00081
00082       (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
00083           weak function.
00084           HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
00085           and the Callback ID.
00086           This function allows to reset following callbacks:
00087             (++) TxCpltCallback        : SPI Tx Completed callback
00088             (++) RxCpltCallback        : SPI Rx Completed callback
00089             (++) TxRxCpltCallback      : SPI TxRx Completed callback
00090             (++) TxHalfCpltCallback    : SPI Tx Half Completed callback
00091             (++) RxHalfCpltCallback    : SPI Rx Half Completed callback
00092             (++) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback
00093             (++) ErrorCallback         : SPI Error callback
00094             (++) AbortCpltCallback     : SPI Abort callback
00095             (++) MspInitCallback       : SPI Msp Init callback
00096             (++) MspDeInitCallback     : SPI Msp DeInit callback
00097
00098        [..]
00099        By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
00100        all callbacks are set to the corresponding weak functions:
00101        examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
00102        Exception done for MspInit and MspDeInit functions that are
00103        reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
00104        these callbacks are null (not registered beforehand).
00105        If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
00106        keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
00107
00108        [..]
00109        Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
00110        Exception done MspInit/MspDeInit functions that can be registered/unregistered
00111        in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
00112        thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00113        Then, the user first registers the MspInit/MspDeInit user callbacks
00114        using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
00115        or HAL_SPI_Init() function.
00116
00117        [..]
00118        When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
00119        not defined, the callback registering feature is not available
00120        and weak (surcharged) callbacks are used.
00121
00122      [..]
00123        Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,
00124        the following table resume the max SPI frequency reached with data size 8bits/16bits,
00125          according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.
00126
00127   @endverbatim
00128
00129   Additional table :
00130
00131        DataSize = SPI_DATASIZE_8BIT:
00132        +----------------------------------------------------------------------------------------------+
00133        |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |
00134        | Process | Tranfert mode  |---------------------|----------------------|----------------------|
00135        |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |
00136        |==============================================================================================|
00137        |    T    |     Polling    | Fpclk/4  | Fpclk/8  |    NA     |    NA    |    NA     |   NA     |
00138        |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
00139        |    /    |     Interrupt  | Fpclk/4  | Fpclk/16 |    NA     |    NA    |    NA     |   NA     |
00140        |    R    |----------------|----------|----------|-----------|----------|-----------|----------|
00141        |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
00142        |=========|================|==========|==========|===========|==========|===========|==========|
00143        |         |     Polling    | Fpclk/4  | Fpclk/8  | Fpclk/16  | Fpclk/8  | Fpclk/8   | Fpclk/8  |
00144        |         |----------------|----------|----------|-----------|----------|-----------|----------|
00145        |    R    |     Interrupt  | Fpclk/8  | Fpclk/16 | Fpclk/8   | Fpclk/8  | Fpclk/8   | Fpclk/4  |
00146        |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
00147        |         |       DMA      | Fpclk/4  | Fpclk/2  | Fpclk/2   | Fpclk/16 | Fpclk/2   | Fpclk/16 |
00148        |=========|================|==========|==========|===========|==========|===========|==========|
00149        |         |     Polling    | Fpclk/8  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/8  |
00150        |         |----------------|----------|----------|-----------|----------|-----------|----------|
00151        |    T    |     Interrupt  | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/16  | Fpclk/8  |
00152        |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
00153        |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/16 |
00154        +----------------------------------------------------------------------------------------------+
00155
00156        DataSize = SPI_DATASIZE_16BIT:
00157        +----------------------------------------------------------------------------------------------+
00158        |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |
00159        | Process | Tranfert mode  |---------------------|----------------------|----------------------|
00160        |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |
00161        |==============================================================================================|
00162        |    T    |     Polling    | Fpclk/4  | Fpclk/8  |    NA     |    NA    |    NA     |   NA     |
00163        |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
00164        |    /    |     Interrupt  | Fpclk/4  | Fpclk/16 |    NA     |    NA    |    NA     |   NA     |
00165        |    R    |----------------|----------|----------|-----------|----------|-----------|----------|
00166        |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
00167        |=========|================|==========|==========|===========|==========|===========|==========|
00168        |         |     Polling    | Fpclk/4  | Fpclk/8  | Fpclk/16  | Fpclk/8  | Fpclk/8   | Fpclk/8  |
00169        |         |----------------|----------|----------|-----------|----------|-----------|----------|
00170        |    R    |     Interrupt  | Fpclk/8  | Fpclk/16 | Fpclk/8   | Fpclk/8  | Fpclk/8   | Fpclk/4  |
00171        |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
00172        |         |       DMA      | Fpclk/4  | Fpclk/2  | Fpclk/2   | Fpclk/16 | Fpclk/2   | Fpclk/16 |
00173        |=========|================|==========|==========|===========|==========|===========|==========|
00174        |         |     Polling    | Fpclk/8  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/8  |
00175        |         |----------------|----------|----------|-----------|----------|-----------|----------|
00176        |    T    |     Interrupt  | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/16  | Fpclk/8  |
00177        |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
00178        |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/16 |
00179        +----------------------------------------------------------------------------------------------+
00180        @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
00181              SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
00182        @note
00183             (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
00184             (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
00185             (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
00186
00187   ******************************************************************************
00188   * @attention
00189   *
00190   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00191   * All rights reserved.</center></h2>
00192   *
00193   * This software component is licensed by ST under BSD 3-Clause license,
00194   * the "License"; You may not use this file except in compliance with the
00195   * License. You may obtain a copy of the License at:
00196   *                        opensource.org/licenses/BSD-3-Clause
00197   *
00198   ******************************************************************************
00199   */
00200
00201 /* Includes ------------------------------------------------------------------*/
00202 #include "stm32wbxx_hal.h"
00203
00204 /** @addtogroup STM32WBxx_HAL_Driver
00205   * @{
00206   */
00207
00208 /** @defgroup SPI SPI
00209   * @brief SPI HAL module driver
00210   * @{
00211   */
00212 #ifdef HAL_SPI_MODULE_ENABLED
00213
00214 /* Private typedef -----------------------------------------------------------*/
00215 /* Private defines -----------------------------------------------------------*/
00216 /** @defgroup SPI_Private_Constants SPI Private Constants
00217   * @{
00218   */
00219 #define SPI_DEFAULT_TIMEOUT 100U
00220 /**
00221   * @}
00222   */
00223
00224 /* Private macros ------------------------------------------------------------*/
00225 /* Private variables ---------------------------------------------------------*/
00226 /* Private function prototypes -----------------------------------------------*/
00227 /** @defgroup SPI_Private_Functions SPI Private Functions
00228   * @{
00229   */
00230 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00231 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00232 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
00233 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
00234 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
00235 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
00236 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
00237 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
00238 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
00239 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
00240 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
00241                                                        uint32_t Timeout, uint32_t Tickstart);
00242 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
00243                                                        uint32_t Timeout, uint32_t Tickstart);
00244 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
00245 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
00246 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
00247 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
00248 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
00249 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
00250 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
00251 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
00252 #if (USE_SPI_CRC != 0U)
00253 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
00254 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
00255 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
00256 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
00257 #endif /* USE_SPI_CRC */
00258 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
00259 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
00260 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
00261 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
00262 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
00263 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
00264 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
00265 /**
00266   * @}
00267   */
00268
00269 /* Exported functions --------------------------------------------------------*/
00270 /** @defgroup SPI_Exported_Functions SPI Exported Functions
00271   * @{
00272   */
00273
00274 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
00275   *  @brief    Initialization and Configuration functions
00276   *
00277 @verbatim
00278  ===============================================================================
00279               ##### Initialization and de-initialization functions #####
00280  ===============================================================================
00281     [..]  This subsection provides a set of functions allowing to initialize and
00282           de-initialize the SPIx peripheral:
00283
00284       (+) User must implement HAL_SPI_MspInit() function in which he configures
00285           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00286
00287       (+) Call the function HAL_SPI_Init() to configure the selected device with
00288           the selected configuration:
00289         (++) Mode
00290         (++) Direction
00291         (++) Data Size
00292         (++) Clock Polarity and Phase
00293         (++) NSS Management
00294         (++) BaudRate Prescaler
00295         (++) FirstBit
00296         (++) TIMode
00297         (++) CRC Calculation
00298         (++) CRC Polynomial if CRC enabled
00299         (++) CRC Length, used only with Data8 and Data16
00300         (++) FIFO reception threshold
00301
00302       (+) Call the function HAL_SPI_DeInit() to restore the default configuration
00303           of the selected SPIx peripheral.
00304
00305 @endverbatim
00306   * @{
00307   */
00308
00309 /**
00310   * @brief  Initialize the SPI according to the specified parameters
00311   *         in the SPI_InitTypeDef and initialize the associated handle.
00312   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
00313   *               the configuration information for SPI module.
00314   * @retval HAL status
00315   */
00316 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
00317 {
00318   uint32_t frxth;
00319
00320   /* Check the SPI handle allocation */
00321   if (hspi == NULL)
00322   {
00323     return HAL_ERROR;
00324   }
00325
00326   /* Check the parameters */
00327   assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
00328   assert_param(IS_SPI_MODE(hspi->Init.Mode));
00329   assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
00330   assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
00331   assert_param(IS_SPI_NSS(hspi->Init.NSS));
00332   assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
00333   assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
00334   assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
00335   assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
00336   if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
00337   {
00338     assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
00339     assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
00340   }
00341 #if (USE_SPI_CRC != 0U)
00342   assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
00343   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00344   {
00345     assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
00346     assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
00347   }
00348 #else
00349   hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
00350 #endif /* USE_SPI_CRC */
00351
00352   if (hspi->State == HAL_SPI_STATE_RESET)
00353   {
00354     /* Allocate lock resource and initialize it */
00355     hspi->Lock = HAL_UNLOCKED;
00356
00357 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
00358     /* Init the SPI Callback settings */
00359     hspi->TxCpltCallback       = HAL_SPI_TxCpltCallback;       /* Legacy weak TxCpltCallback       */
00360     hspi->RxCpltCallback       = HAL_SPI_RxCpltCallback;       /* Legacy weak RxCpltCallback       */
00361     hspi->TxRxCpltCallback     = HAL_SPI_TxRxCpltCallback;     /* Legacy weak TxRxCpltCallback     */
00362     hspi->TxHalfCpltCallback   = HAL_SPI_TxHalfCpltCallback;   /* Legacy weak TxHalfCpltCallback   */
00363     hspi->RxHalfCpltCallback   = HAL_SPI_RxHalfCpltCallback;   /* Legacy weak RxHalfCpltCallback   */
00364     hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
00365     hspi->ErrorCallback        = HAL_SPI_ErrorCallback;        /* Legacy weak ErrorCallback        */
00366     hspi->AbortCpltCallback    = HAL_SPI_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    */
00367
00368     if (hspi->MspInitCallback == NULL)
00369     {
00370       hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit  */
00371     }
00372
00373     /* Init the low level hardware : GPIO, CLOCK, NVIC... */
00374     hspi->MspInitCallback(hspi);
00375 #else
00376     /* Init the low level hardware : GPIO, CLOCK, NVIC... */
00377     HAL_SPI_MspInit(hspi);
00378 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
00379   }
00380
00381   hspi->State = HAL_SPI_STATE_BUSY;
00382
00383   /* Disable the selected SPI peripheral */
00384   __HAL_SPI_DISABLE(hspi);
00385
00386   /* Align by default the rs fifo threshold on the data size */
00387   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
00388   {
00389     frxth = SPI_RXFIFO_THRESHOLD_HF;
00390   }
00391   else
00392   {
00393     frxth = SPI_RXFIFO_THRESHOLD_QF;
00394   }
00395
00396   /* CRC calculation is valid only for 16Bit and 8 Bit */
00397   if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
00398   {
00399     /* CRC must be disabled */
00400     hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
00401   }
00402
00403   /* Align the CRC Length on the data size */
00404   if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
00405   {
00406     /* CRC Length aligned on the data size : value set by default */
00407     if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
00408     {
00409       hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
00410     }
00411     else
00412     {
00413       hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
00414     }
00415   }
00416
00417   /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
00418   /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
00419   Communication speed, First bit and CRC calculation state */
00420   WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction |
00421                                   hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
00422                                   hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit  | hspi->Init.CRCCalculation));
00423 #if (USE_SPI_CRC != 0U)
00424   /* Configure : CRC Length */
00425   if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
00426   {
00427     hspi->Instance->CR1 |= SPI_CR1_CRCL;
00428   }
00429 #endif /* USE_SPI_CRC */
00430
00431   /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
00432   WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode |
00433                                   hspi->Init.NSSPMode | hspi->Init.DataSize) | frxth);
00434
00435 #if (USE_SPI_CRC != 0U)
00436   /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
00437   /* Configure : CRC Polynomial */
00438   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00439   {
00440     WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
00441   }
00442 #endif /* USE_SPI_CRC */
00443
00444 #if defined(SPI_I2SCFGR_I2SMOD)
00445   /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
00446   CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
00447 #endif /* SPI_I2SCFGR_I2SMOD */
00448
00449   hspi->ErrorCode = HAL_SPI_ERROR_NONE;
00450   hspi->State     = HAL_SPI_STATE_READY;
00451
00452   return HAL_OK;
00453 }
00454
00455 /**
00456   * @brief  De-Initialize the SPI peripheral.
00457   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
00458   *               the configuration information for SPI module.
00459   * @retval HAL status
00460   */
00461 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
00462 {
00463   /* Check the SPI handle allocation */
00464   if (hspi == NULL)
00465   {
00466     return HAL_ERROR;
00467   }
00468
00469   /* Check SPI Instance parameter */
00470   assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
00471
00472   hspi->State = HAL_SPI_STATE_BUSY;
00473
00474   /* Disable the SPI Peripheral Clock */
00475   __HAL_SPI_DISABLE(hspi);
00476
00477 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
00478   if (hspi->MspDeInitCallback == NULL)
00479   {
00480     hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit  */
00481   }
00482
00483   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
00484   hspi->MspDeInitCallback(hspi);
00485 #else
00486   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
00487   HAL_SPI_MspDeInit(hspi);
00488 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
00489
00490   hspi->ErrorCode = HAL_SPI_ERROR_NONE;
00491   hspi->State = HAL_SPI_STATE_RESET;
00492
00493   /* Release Lock */
00494   __HAL_UNLOCK(hspi);
00495
00496   return HAL_OK;
00497 }
00498
00499 /**
00500   * @brief  Initialize the SPI MSP.
00501   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
00502   *               the configuration information for SPI module.
00503   * @retval None
00504   */
00505 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
00506 {
00507   /* Prevent unused argument(s) compilation warning */
00508   UNUSED(hspi);
00509
00510   /* NOTE : This function should not be modified, when the callback is needed,
00511             the HAL_SPI_MspInit should be implemented in the user file
00512    */
00513 }
00514
00515 /**
00516   * @brief  De-Initialize the SPI MSP.
00517   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
00518   *               the configuration information for SPI module.
00519   * @retval None
00520   */
00521 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
00522 {
00523   /* Prevent unused argument(s) compilation warning */
00524   UNUSED(hspi);
00525
00526   /* NOTE : This function should not be modified, when the callback is needed,
00527             the HAL_SPI_MspDeInit should be implemented in the user file
00528    */
00529 }
00530
00531 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
00532 /**
00533   * @brief  Register a User SPI Callback
00534   *         To be used instead of the weak predefined callback
00535   * @param  hspi Pointer to a SPI_HandleTypeDef structure that contains
00536   *                the configuration information for the specified SPI.
00537   * @param  CallbackID ID of the callback to be registered
00538   * @param  pCallback pointer to the Callback function
00539   * @retval HAL status
00540   */
00541 HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
00542                                            pSPI_CallbackTypeDef pCallback)
00543 {
00544   HAL_StatusTypeDef status = HAL_OK;
00545
00546   if (pCallback == NULL)
00547   {
00548     /* Update the error code */
00549     hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;
00550
00551     return HAL_ERROR;
00552   }
00553   /* Process locked */
00554   __HAL_LOCK(hspi);
00555
00556   if (HAL_SPI_STATE_READY == hspi->State)
00557   {
00558     switch (CallbackID)
00559     {
00560       case HAL_SPI_TX_COMPLETE_CB_ID :
00561         hspi->TxCpltCallback = pCallback;
00562         break;
00563
00564       case HAL_SPI_RX_COMPLETE_CB_ID :
00565         hspi->RxCpltCallback = pCallback;
00566         break;
00567
00568       case HAL_SPI_TX_RX_COMPLETE_CB_ID :
00569         hspi->TxRxCpltCallback = pCallback;
00570         break;
00571
00572       case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
00573         hspi->TxHalfCpltCallback = pCallback;
00574         break;
00575
00576       case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
00577         hspi->RxHalfCpltCallback = pCallback;
00578         break;
00579
00580       case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
00581         hspi->TxRxHalfCpltCallback = pCallback;
00582         break;
00583
00584       case HAL_SPI_ERROR_CB_ID :
00585         hspi->ErrorCallback = pCallback;
00586         break;
00587
00588       case HAL_SPI_ABORT_CB_ID :
00589         hspi->AbortCpltCallback = pCallback;
00590         break;
00591
00592       case HAL_SPI_MSPINIT_CB_ID :
00593         hspi->MspInitCallback = pCallback;
00594         break;
00595
00596       case HAL_SPI_MSPDEINIT_CB_ID :
00597         hspi->MspDeInitCallback = pCallback;
00598         break;
00599
00600       default :
00601         /* Update the error code */
00602         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
00603
00604         /* Return error status */
00605         status =  HAL_ERROR;
00606         break;
00607     }
00608   }
00609   else if (HAL_SPI_STATE_RESET == hspi->State)
00610   {
00611     switch (CallbackID)
00612     {
00613       case HAL_SPI_MSPINIT_CB_ID :
00614         hspi->MspInitCallback = pCallback;
00615         break;
00616
00617       case HAL_SPI_MSPDEINIT_CB_ID :
00618         hspi->MspDeInitCallback = pCallback;
00619         break;
00620
00621       default :
00622         /* Update the error code */
00623         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
00624
00625         /* Return error status */
00626         status =  HAL_ERROR;
00627         break;
00628     }
00629   }
00630   else
00631   {
00632     /* Update the error code */
00633     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
00634
00635     /* Return error status */
00636     status =  HAL_ERROR;
00637   }
00638
00639   /* Release Lock */
00640   __HAL_UNLOCK(hspi);
00641   return status;
00642 }
00643
00644 /**
00645   * @brief  Unregister an SPI Callback
00646   *         SPI callback is redirected to the weak predefined callback
00647   * @param  hspi Pointer to a SPI_HandleTypeDef structure that contains
00648   *                the configuration information for the specified SPI.
00649   * @param  CallbackID ID of the callback to be unregistered
00650   * @retval HAL status
00651   */
00652 HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
00653 {
00654   HAL_StatusTypeDef status = HAL_OK;
00655
00656   /* Process locked */
00657   __HAL_LOCK(hspi);
00658
00659   if (HAL_SPI_STATE_READY == hspi->State)
00660   {
00661     switch (CallbackID)
00662     {
00663       case HAL_SPI_TX_COMPLETE_CB_ID :
00664         hspi->TxCpltCallback = HAL_SPI_TxCpltCallback;             /* Legacy weak TxCpltCallback       */
00665         break;
00666
00667       case HAL_SPI_RX_COMPLETE_CB_ID :
00668         hspi->RxCpltCallback = HAL_SPI_RxCpltCallback;             /* Legacy weak RxCpltCallback       */
00669         break;
00670
00671       case HAL_SPI_TX_RX_COMPLETE_CB_ID :
00672         hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback;         /* Legacy weak TxRxCpltCallback     */
00673         break;
00674
00675       case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
00676         hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback;     /* Legacy weak TxHalfCpltCallback   */
00677         break;
00678
00679       case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
00680         hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback;     /* Legacy weak RxHalfCpltCallback   */
00681         break;
00682
00683       case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
00684         hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
00685         break;
00686
00687       case HAL_SPI_ERROR_CB_ID :
00688         hspi->ErrorCallback = HAL_SPI_ErrorCallback;               /* Legacy weak ErrorCallback        */
00689         break;
00690
00691       case HAL_SPI_ABORT_CB_ID :
00692         hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback;       /* Legacy weak AbortCpltCallback    */
00693         break;
00694
00695       case HAL_SPI_MSPINIT_CB_ID :
00696         hspi->MspInitCallback = HAL_SPI_MspInit;                   /* Legacy weak MspInit              */
00697         break;
00698
00699       case HAL_SPI_MSPDEINIT_CB_ID :
00700         hspi->MspDeInitCallback = HAL_SPI_MspDeInit;               /* Legacy weak MspDeInit            */
00701         break;
00702
00703       default :
00704         /* Update the error code */
00705         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
00706
00707         /* Return error status */
00708         status =  HAL_ERROR;
00709         break;
00710     }
00711   }
00712   else if (HAL_SPI_STATE_RESET == hspi->State)
00713   {
00714     switch (CallbackID)
00715     {
00716       case HAL_SPI_MSPINIT_CB_ID :
00717         hspi->MspInitCallback = HAL_SPI_MspInit;                   /* Legacy weak MspInit              */
00718         break;
00719
00720       case HAL_SPI_MSPDEINIT_CB_ID :
00721         hspi->MspDeInitCallback = HAL_SPI_MspDeInit;               /* Legacy weak MspDeInit            */
00722         break;
00723
00724       default :
00725         /* Update the error code */
00726         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
00727
00728         /* Return error status */
00729         status =  HAL_ERROR;
00730         break;
00731     }
00732   }
00733   else
00734   {
00735     /* Update the error code */
00736     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
00737
00738     /* Return error status */
00739     status =  HAL_ERROR;
00740   }
00741
00742   /* Release Lock */
00743   __HAL_UNLOCK(hspi);
00744   return status;
00745 }
00746 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
00747 /**
00748   * @}
00749   */
00750
00751 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
00752   *  @brief   Data transfers functions
00753   *
00754 @verbatim
00755   ==============================================================================
00756                       ##### IO operation functions #####
00757  ===============================================================================
00758  [..]
00759     This subsection provides a set of functions allowing to manage the SPI
00760     data transfers.
00761
00762     [..] The SPI supports master and slave mode :
00763
00764     (#) There are two modes of transfer:
00765        (++) Blocking mode: The communication is performed in polling mode.
00766             The HAL status of all data processing is returned by the same function
00767             after finishing transfer.
00768        (++) No-Blocking mode: The communication is performed using Interrupts
00769             or DMA, These APIs return the HAL status.
00770             The end of the data processing will be indicated through the
00771             dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
00772             using DMA mode.
00773             The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
00774             will be executed respectively at the end of the transmit or Receive process
00775             The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
00776
00777     (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
00778         exist for 1Line (simplex) and 2Lines (full duplex) modes.
00779
00780 @endverbatim
00781   * @{
00782   */
00783
00784 /**
00785   * @brief  Transmit an amount of data in blocking mode.
00786   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
00787   *               the configuration information for SPI module.
00788   * @param  pData pointer to data buffer
00789   * @param  Size amount of data to be sent
00790   * @param  Timeout Timeout duration
00791   * @retval HAL status
00792   */
00793 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00794 {
00795   uint32_t tickstart;
00796   HAL_StatusTypeDef errorcode = HAL_OK;
00797   uint16_t initial_TxXferCount;
00798
00799   /* Check Direction parameter */
00800   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
00801
00802   /* Process Locked */
00803   __HAL_LOCK(hspi);
00804
00805   /* Init tickstart for timeout management*/
00806   tickstart = HAL_GetTick();
00807   initial_TxXferCount = Size;
00808
00809   if (hspi->State != HAL_SPI_STATE_READY)
00810   {
00811     errorcode = HAL_BUSY;
00812     goto error;
00813   }
00814
00815   if ((pData == NULL) || (Size == 0U))
00816   {
00817     errorcode = HAL_ERROR;
00818     goto error;
00819   }
00820
00821   /* Set the transaction information */
00822   hspi->State       = HAL_SPI_STATE_BUSY_TX;
00823   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
00824   hspi->pTxBuffPtr  = (uint8_t *)pData;
00825   hspi->TxXferSize  = Size;
00826   hspi->TxXferCount = Size;
00827
00828   /*Init field not used in handle to zero */
00829   hspi->pRxBuffPtr  = (uint8_t *)NULL;
00830   hspi->RxXferSize  = 0U;
00831   hspi->RxXferCount = 0U;
00832   hspi->TxISR       = NULL;
00833   hspi->RxISR       = NULL;
00834
00835   /* Configure communication direction : 1Line */
00836   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
00837   {
00838     SPI_1LINE_TX(hspi);
00839   }
00840
00841 #if (USE_SPI_CRC != 0U)
00842   /* Reset CRC Calculation */
00843   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00844   {
00845     SPI_RESET_CRC(hspi);
00846   }
00847 #endif /* USE_SPI_CRC */
00848
00849   /* Check if the SPI is already enabled */
00850   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
00851   {
00852     /* Enable SPI peripheral */
00853     __HAL_SPI_ENABLE(hspi);
00854   }
00855
00856   /* Transmit data in 16 Bit mode */
00857   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
00858   {
00859     if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
00860     {
00861       hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
00862       hspi->pTxBuffPtr += sizeof(uint16_t);
00863       hspi->TxXferCount--;
00864     }
00865     /* Transmit data in 16 Bit mode */
00866     while (hspi->TxXferCount > 0U)
00867     {
00868       /* Wait until TXE flag is set to send data */
00869       if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
00870       {
00871         hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
00872         hspi->pTxBuffPtr += sizeof(uint16_t);
00873         hspi->TxXferCount--;
00874       }
00875       else
00876       {
00877         /* Timeout management */
00878         if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
00879         {
00880           errorcode = HAL_TIMEOUT;
00881           goto error;
00882         }
00883       }
00884     }
00885   }
00886   /* Transmit data in 8 Bit mode */
00887   else
00888   {
00889     if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
00890     {
00891       if (hspi->TxXferCount > 1U)
00892       {
00893         /* write on the data register in packing mode */
00894         hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
00895         hspi->pTxBuffPtr += sizeof(uint16_t);
00896         hspi->TxXferCount -= 2U;
00897       }
00898       else
00899       {
00900         *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
00901         hspi->pTxBuffPtr ++;
00902         hspi->TxXferCount--;
00903       }
00904     }
00905     while (hspi->TxXferCount > 0U)
00906     {
00907       /* Wait until TXE flag is set to send data */
00908       if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
00909       {
00910         if (hspi->TxXferCount > 1U)
00911         {
00912           /* write on the data register in packing mode */
00913           hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
00914           hspi->pTxBuffPtr += sizeof(uint16_t);
00915           hspi->TxXferCount -= 2U;
00916         }
00917         else
00918         {
00919           *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
00920           hspi->pTxBuffPtr++;
00921           hspi->TxXferCount--;
00922         }
00923       }
00924       else
00925       {
00926         /* Timeout management */
00927         if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
00928         {
00929           errorcode = HAL_TIMEOUT;
00930           goto error;
00931         }
00932       }
00933     }
00934   }
00935 #if (USE_SPI_CRC != 0U)
00936   /* Enable CRC Transmission */
00937   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00938   {
00939     SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
00940   }
00941 #endif /* USE_SPI_CRC */
00942
00943   /* Check the end of the transaction */
00944   if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
00945   {
00946     hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
00947   }
00948
00949   /* Clear overrun flag in 2 Lines communication mode because received is not read */
00950   if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
00951   {
00952     __HAL_SPI_CLEAR_OVRFLAG(hspi);
00953   }
00954
00955   if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
00956   {
00957     errorcode = HAL_ERROR;
00958   }
00959
00960 error:
00961   hspi->State = HAL_SPI_STATE_READY;
00962   /* Process Unlocked */
00963   __HAL_UNLOCK(hspi);
00964   return errorcode;
00965 }
00966
00967 /**
00968   * @brief  Receive an amount of data in blocking mode.
00969   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
00970   *               the configuration information for SPI module.
00971   * @param  pData pointer to data buffer
00972   * @param  Size amount of data to be received
00973   * @param  Timeout Timeout duration
00974   * @retval HAL status
00975   */
00976 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00977 {
00978   uint32_t tickstart;
00979   HAL_StatusTypeDef errorcode = HAL_OK;
00980
00981   if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
00982   {
00983     hspi->State = HAL_SPI_STATE_BUSY_RX;
00984     /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
00985     return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
00986   }
00987
00988   /* Process Locked */
00989   __HAL_LOCK(hspi);
00990
00991   /* Init tickstart for timeout management*/
00992   tickstart = HAL_GetTick();
00993
00994   if (hspi->State != HAL_SPI_STATE_READY)
00995   {
00996     errorcode = HAL_BUSY;
00997     goto error;
00998   }
00999
01000   if ((pData == NULL) || (Size == 0U))
01001   {
01002     errorcode = HAL_ERROR;
01003     goto error;
01004   }
01005
01006   /* Set the transaction information */
01007   hspi->State       = HAL_SPI_STATE_BUSY_RX;
01008   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01009   hspi->pRxBuffPtr  = (uint8_t *)pData;
01010   hspi->RxXferSize  = Size;
01011   hspi->RxXferCount = Size;
01012
01013   /*Init field not used in handle to zero */
01014   hspi->pTxBuffPtr  = (uint8_t *)NULL;
01015   hspi->TxXferSize  = 0U;
01016   hspi->TxXferCount = 0U;
01017   hspi->RxISR       = NULL;
01018   hspi->TxISR       = NULL;
01019
01020 #if (USE_SPI_CRC != 0U)
01021   /* Reset CRC Calculation */
01022   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01023   {
01024     SPI_RESET_CRC(hspi);
01025     /* this is done to handle the CRCNEXT before the latest data */
01026     hspi->RxXferCount--;
01027   }
01028 #endif /* USE_SPI_CRC */
01029
01030   /* Set the Rx Fifo threshold */
01031   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01032   {
01033     /* Set RX Fifo threshold according the reception data length: 16bit */
01034     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01035   }
01036   else
01037   {
01038     /* Set RX Fifo threshold according the reception data length: 8bit */
01039     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01040   }
01041
01042   /* Configure communication direction: 1Line */
01043   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
01044   {
01045     SPI_1LINE_RX(hspi);
01046   }
01047
01048   /* Check if the SPI is already enabled */
01049   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01050   {
01051     /* Enable SPI peripheral */
01052     __HAL_SPI_ENABLE(hspi);
01053   }
01054
01055   /* Receive data in 8 Bit mode */
01056   if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
01057   {
01058     /* Transfer loop */
01059     while (hspi->RxXferCount > 0U)
01060     {
01061       /* Check the RXNE flag */
01062       if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
01063       {
01064         /* read the received data */
01065         (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
01066         hspi->pRxBuffPtr += sizeof(uint8_t);
01067         hspi->RxXferCount--;
01068       }
01069       else
01070       {
01071         /* Timeout management */
01072         if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
01073         {
01074           errorcode = HAL_TIMEOUT;
01075           goto error;
01076         }
01077       }
01078     }
01079   }
01080   else
01081   {
01082     /* Transfer loop */
01083     while (hspi->RxXferCount > 0U)
01084     {
01085       /* Check the RXNE flag */
01086       if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
01087       {
01088         *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
01089         hspi->pRxBuffPtr += sizeof(uint16_t);
01090         hspi->RxXferCount--;
01091       }
01092       else
01093       {
01094         /* Timeout management */
01095         if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
01096         {
01097           errorcode = HAL_TIMEOUT;
01098           goto error;
01099         }
01100       }
01101     }
01102   }
01103
01104 #if (USE_SPI_CRC != 0U)
01105   /* Handle the CRC Transmission */
01106   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01107   {
01108     /* freeze the CRC before the latest data */
01109     SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
01110
01111     /* Read the latest data */
01112     if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
01113     {
01114       /* the latest data has not been received */
01115       errorcode = HAL_TIMEOUT;
01116       goto error;
01117     }
01118
01119     /* Receive last data in 16 Bit mode */
01120     if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01121     {
01122       *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
01123     }
01124     /* Receive last data in 8 Bit mode */
01125     else
01126     {
01127       (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
01128     }
01129
01130     /* Wait the CRC data */
01131     if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
01132     {
01133       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
01134       errorcode = HAL_TIMEOUT;
01135       goto error;
01136     }
01137
01138     /* Read CRC to Flush DR and RXNE flag */
01139     if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
01140     {
01141       /* Read 16bit CRC */
01142       READ_REG(hspi->Instance->DR);
01143     }
01144     else
01145     {
01146       /* Read 8bit CRC */
01147       READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
01148
01149       if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
01150       {
01151         if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
01152         {
01153           /* Error on the CRC reception */
01154           SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
01155           errorcode = HAL_TIMEOUT;
01156           goto error;
01157         }
01158         /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
01159         READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
01160       }
01161     }
01162   }
01163 #endif /* USE_SPI_CRC */
01164
01165   /* Check the end of the transaction */
01166   if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
01167   {
01168     hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
01169   }
01170
01171 #if (USE_SPI_CRC != 0U)
01172   /* Check if CRC error occurred */
01173   if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
01174   {
01175     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
01176     __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
01177   }
01178 #endif /* USE_SPI_CRC */
01179
01180   if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
01181   {
01182     errorcode = HAL_ERROR;
01183   }
01184
01185 error :
01186   hspi->State = HAL_SPI_STATE_READY;
01187   __HAL_UNLOCK(hspi);
01188   return errorcode;
01189 }
01190
01191 /**
01192   * @brief  Transmit and Receive an amount of data in blocking mode.
01193   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
01194   *               the configuration information for SPI module.
01195   * @param  pTxData pointer to transmission data buffer
01196   * @param  pRxData pointer to reception data buffer
01197   * @param  Size amount of data to be sent and received
01198   * @param  Timeout Timeout duration
01199   * @retval HAL status
01200   */
01201 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
01202                                           uint32_t Timeout)
01203 {
01204   uint16_t             initial_TxXferCount;
01205   uint16_t             initial_RxXferCount;
01206   uint32_t             tmp_mode;
01207   HAL_SPI_StateTypeDef tmp_state;
01208   uint32_t             tickstart;
01209 #if (USE_SPI_CRC != 0U)
01210   uint32_t             spi_cr1;
01211   uint32_t             spi_cr2;
01212 #endif /* USE_SPI_CRC */
01213
01214   /* Variable used to alternate Rx and Tx during transfer */
01215   uint32_t             txallowed = 1U;
01216   HAL_StatusTypeDef    errorcode = HAL_OK;
01217
01218   /* Check Direction parameter */
01219   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
01220
01221   /* Process Locked */
01222   __HAL_LOCK(hspi);
01223
01224   /* Init tickstart for timeout management*/
01225   tickstart = HAL_GetTick();
01226
01227   /* Init temporary variables */
01228   tmp_state           = hspi->State;
01229   tmp_mode            = hspi->Init.Mode;
01230   initial_TxXferCount = Size;
01231   initial_RxXferCount = Size;
01232 #if (USE_SPI_CRC != 0U)
01233   spi_cr1             = READ_REG(hspi->Instance->CR1);
01234   spi_cr2             = READ_REG(hspi->Instance->CR2);
01235 #endif /* USE_SPI_CRC */
01236
01237   if (!((tmp_state == HAL_SPI_STATE_READY) || \
01238         ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
01239   {
01240     errorcode = HAL_BUSY;
01241     goto error;
01242   }
01243
01244   if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
01245   {
01246     errorcode = HAL_ERROR;
01247     goto error;
01248   }
01249
01250   /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
01251   if (hspi->State != HAL_SPI_STATE_BUSY_RX)
01252   {
01253     hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
01254   }
01255
01256   /* Set the transaction information */
01257   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01258   hspi->pRxBuffPtr  = (uint8_t *)pRxData;
01259   hspi->RxXferCount = Size;
01260   hspi->RxXferSize  = Size;
01261   hspi->pTxBuffPtr  = (uint8_t *)pTxData;
01262   hspi->TxXferCount = Size;
01263   hspi->TxXferSize  = Size;
01264
01265   /*Init field not used in handle to zero */
01266   hspi->RxISR       = NULL;
01267   hspi->TxISR       = NULL;
01268
01269 #if (USE_SPI_CRC != 0U)
01270   /* Reset CRC Calculation */
01271   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01272   {
01273     SPI_RESET_CRC(hspi);
01274   }
01275 #endif /* USE_SPI_CRC */
01276
01277   /* Set the Rx Fifo threshold */
01278   if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U))
01279   {
01280     /* Set fiforxthreshold according the reception data length: 16bit */
01281     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01282   }
01283   else
01284   {
01285     /* Set fiforxthreshold according the reception data length: 8bit */
01286     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01287   }
01288
01289   /* Check if the SPI is already enabled */
01290   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01291   {
01292     /* Enable SPI peripheral */
01293     __HAL_SPI_ENABLE(hspi);
01294   }
01295
01296   /* Transmit and Receive data in 16 Bit mode */
01297   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01298   {
01299     if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
01300     {
01301       hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
01302       hspi->pTxBuffPtr += sizeof(uint16_t);
01303       hspi->TxXferCount--;
01304     }
01305     while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
01306     {
01307       /* Check TXE flag */
01308       if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
01309       {
01310         hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
01311         hspi->pTxBuffPtr += sizeof(uint16_t);
01312         hspi->TxXferCount--;
01313         /* Next Data is a reception (Rx). Tx not allowed */
01314         txallowed = 0U;
01315
01316 #if (USE_SPI_CRC != 0U)
01317         /* Enable CRC Transmission */
01318         if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
01319         {
01320           /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
01321           if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
01322           {
01323             SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
01324           }
01325           SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
01326         }
01327 #endif /* USE_SPI_CRC */
01328       }
01329
01330       /* Check RXNE flag */
01331       if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
01332       {
01333         *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
01334         hspi->pRxBuffPtr += sizeof(uint16_t);
01335         hspi->RxXferCount--;
01336         /* Next Data is a Transmission (Tx). Tx is allowed */
01337         txallowed = 1U;
01338       }
01339       if (((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY))
01340       {
01341         errorcode = HAL_TIMEOUT;
01342         goto error;
01343       }
01344     }
01345   }
01346   /* Transmit and Receive data in 8 Bit mode */
01347   else
01348   {
01349     if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
01350     {
01351       if (hspi->TxXferCount > 1U)
01352       {
01353         hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
01354         hspi->pTxBuffPtr += sizeof(uint16_t);
01355         hspi->TxXferCount -= 2U;
01356       }
01357       else
01358       {
01359         *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
01360         hspi->pTxBuffPtr++;
01361         hspi->TxXferCount--;
01362       }
01363     }
01364     while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
01365     {
01366       /* Check TXE flag */
01367       if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
01368       {
01369         if (hspi->TxXferCount > 1U)
01370         {
01371           hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
01372           hspi->pTxBuffPtr += sizeof(uint16_t);
01373           hspi->TxXferCount -= 2U;
01374         }
01375         else
01376         {
01377           *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
01378           hspi->pTxBuffPtr++;
01379           hspi->TxXferCount--;
01380         }
01381         /* Next Data is a reception (Rx). Tx not allowed */
01382         txallowed = 0U;
01383
01384 #if (USE_SPI_CRC != 0U)
01385         /* Enable CRC Transmission */
01386         if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
01387         {
01388           /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
01389           if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
01390           {
01391             SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
01392           }
01393           SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
01394         }
01395 #endif /* USE_SPI_CRC */
01396       }
01397
01398       /* Wait until RXNE flag is reset */
01399       if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
01400       {
01401         if (hspi->RxXferCount > 1U)
01402         {
01403           *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
01404           hspi->pRxBuffPtr += sizeof(uint16_t);
01405           hspi->RxXferCount -= 2U;
01406           if (hspi->RxXferCount <= 1U)
01407           {
01408             /* Set RX Fifo threshold before to switch on 8 bit data size */
01409             SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01410           }
01411         }
01412         else
01413         {
01414           (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
01415           hspi->pRxBuffPtr++;
01416           hspi->RxXferCount--;
01417         }
01418         /* Next Data is a Transmission (Tx). Tx is allowed */
01419         txallowed = 1U;
01420       }
01421       if ((((HAL_GetTick() - tickstart) >=  Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
01422       {
01423         errorcode = HAL_TIMEOUT;
01424         goto error;
01425       }
01426     }
01427   }
01428
01429 #if (USE_SPI_CRC != 0U)
01430   /* Read CRC from DR to close CRC calculation process */
01431   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01432   {
01433     /* Wait until TXE flag */
01434     if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
01435     {
01436       /* Error on the CRC reception */
01437       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
01438       errorcode = HAL_TIMEOUT;
01439       goto error;
01440     }
01441     /* Read CRC */
01442     if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
01443     {
01444       /* Read 16bit CRC */
01445       READ_REG(hspi->Instance->DR);
01446     }
01447     else
01448     {
01449       /* Read 8bit CRC */
01450       READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
01451
01452       if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
01453       {
01454         if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
01455         {
01456           /* Error on the CRC reception */
01457           SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
01458           errorcode = HAL_TIMEOUT;
01459           goto error;
01460         }
01461         /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
01462         READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
01463       }
01464     }
01465   }
01466
01467   /* Check if CRC error occurred */
01468   if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
01469   {
01470     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
01471     /* Clear CRC Flag */
01472     __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
01473
01474     errorcode = HAL_ERROR;
01475   }
01476 #endif /* USE_SPI_CRC */
01477
01478   /* Check the end of the transaction */
01479   if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
01480   {
01481     errorcode = HAL_ERROR;
01482     hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
01483   }
01484
01485 error :
01486   hspi->State = HAL_SPI_STATE_READY;
01487   __HAL_UNLOCK(hspi);
01488   return errorcode;
01489 }
01490
01491 /**
01492   * @brief  Transmit an amount of data in non-blocking mode with Interrupt.
01493   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
01494   *               the configuration information for SPI module.
01495   * @param  pData pointer to data buffer
01496   * @param  Size amount of data to be sent
01497   * @retval HAL status
01498   */
01499 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
01500 {
01501   HAL_StatusTypeDef errorcode = HAL_OK;
01502
01503   /* Check Direction parameter */
01504   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
01505
01506   /* Process Locked */
01507   __HAL_LOCK(hspi);
01508
01509   if ((pData == NULL) || (Size == 0U))
01510   {
01511     errorcode = HAL_ERROR;
01512     goto error;
01513   }
01514
01515   if (hspi->State != HAL_SPI_STATE_READY)
01516   {
01517     errorcode = HAL_BUSY;
01518     goto error;
01519   }
01520
01521   /* Set the transaction information */
01522   hspi->State       = HAL_SPI_STATE_BUSY_TX;
01523   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01524   hspi->pTxBuffPtr  = (uint8_t *)pData;
01525   hspi->TxXferSize  = Size;
01526   hspi->TxXferCount = Size;
01527
01528   /* Init field not used in handle to zero */
01529   hspi->pRxBuffPtr  = (uint8_t *)NULL;
01530   hspi->RxXferSize  = 0U;
01531   hspi->RxXferCount = 0U;
01532   hspi->RxISR       = NULL;
01533
01534   /* Set the function for IT treatment */
01535   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01536   {
01537     hspi->TxISR = SPI_TxISR_16BIT;
01538   }
01539   else
01540   {
01541     hspi->TxISR = SPI_TxISR_8BIT;
01542   }
01543
01544   /* Configure communication direction : 1Line */
01545   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
01546   {
01547     SPI_1LINE_TX(hspi);
01548   }
01549
01550 #if (USE_SPI_CRC != 0U)
01551   /* Reset CRC Calculation */
01552   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01553   {
01554     SPI_RESET_CRC(hspi);
01555   }
01556 #endif /* USE_SPI_CRC */
01557
01558   /* Enable TXE and ERR interrupt */
01559   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
01560
01561
01562   /* Check if the SPI is already enabled */
01563   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01564   {
01565     /* Enable SPI peripheral */
01566     __HAL_SPI_ENABLE(hspi);
01567   }
01568
01569 error :
01570   __HAL_UNLOCK(hspi);
01571   return errorcode;
01572 }
01573
01574 /**
01575   * @brief  Receive an amount of data in non-blocking mode with Interrupt.
01576   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
01577   *               the configuration information for SPI module.
01578   * @param  pData pointer to data buffer
01579   * @param  Size amount of data to be sent
01580   * @retval HAL status
01581   */
01582 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
01583 {
01584   HAL_StatusTypeDef errorcode = HAL_OK;
01585
01586   if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
01587   {
01588     hspi->State = HAL_SPI_STATE_BUSY_RX;
01589     /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
01590     return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
01591   }
01592
01593   /* Process Locked */
01594   __HAL_LOCK(hspi);
01595
01596   if (hspi->State != HAL_SPI_STATE_READY)
01597   {
01598     errorcode = HAL_BUSY;
01599     goto error;
01600   }
01601
01602   if ((pData == NULL) || (Size == 0U))
01603   {
01604     errorcode = HAL_ERROR;
01605     goto error;
01606   }
01607
01608   /* Set the transaction information */
01609   hspi->State       = HAL_SPI_STATE_BUSY_RX;
01610   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01611   hspi->pRxBuffPtr  = (uint8_t *)pData;
01612   hspi->RxXferSize  = Size;
01613   hspi->RxXferCount = Size;
01614
01615   /* Init field not used in handle to zero */
01616   hspi->pTxBuffPtr  = (uint8_t *)NULL;
01617   hspi->TxXferSize  = 0U;
01618   hspi->TxXferCount = 0U;
01619   hspi->TxISR       = NULL;
01620
01621   /* Check the data size to adapt Rx threshold and the set the function for IT treatment */
01622   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01623   {
01624     /* Set RX Fifo threshold according the reception data length: 16 bit */
01625     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01626     hspi->RxISR = SPI_RxISR_16BIT;
01627   }
01628   else
01629   {
01630     /* Set RX Fifo threshold according the reception data length: 8 bit */
01631     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01632     hspi->RxISR = SPI_RxISR_8BIT;
01633   }
01634
01635   /* Configure communication direction : 1Line */
01636   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
01637   {
01638     SPI_1LINE_RX(hspi);
01639   }
01640
01641 #if (USE_SPI_CRC != 0U)
01642   /* Reset CRC Calculation */
01643   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01644   {
01645     hspi->CRCSize = 1U;
01646     if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
01647     {
01648       hspi->CRCSize = 2U;
01649     }
01650     SPI_RESET_CRC(hspi);
01651   }
01652   else
01653   {
01654     hspi->CRCSize = 0U;
01655   }
01656 #endif /* USE_SPI_CRC */
01657
01658   /* Enable TXE and ERR interrupt */
01659   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
01660
01661   /* Note : The SPI must be enabled after unlocking current process
01662             to avoid the risk of SPI interrupt handle execution before current
01663             process unlock */
01664
01665   /* Check if the SPI is already enabled */
01666   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01667   {
01668     /* Enable SPI peripheral */
01669     __HAL_SPI_ENABLE(hspi);
01670   }
01671
01672 error :
01673   /* Process Unlocked */
01674   __HAL_UNLOCK(hspi);
01675   return errorcode;
01676 }
01677
01678 /**
01679   * @brief  Transmit and Receive an amount of data in non-blocking mode with Interrupt.
01680   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
01681   *               the configuration information for SPI module.
01682   * @param  pTxData pointer to transmission data buffer
01683   * @param  pRxData pointer to reception data buffer
01684   * @param  Size amount of data to be sent and received
01685   * @retval HAL status
01686   */
01687 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
01688 {
01689   uint32_t             tmp_mode;
01690   HAL_SPI_StateTypeDef tmp_state;
01691   HAL_StatusTypeDef    errorcode = HAL_OK;
01692
01693   /* Check Direction parameter */
01694   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
01695
01696   /* Process locked */
01697   __HAL_LOCK(hspi);
01698
01699   /* Init temporary variables */
01700   tmp_state           = hspi->State;
01701   tmp_mode            = hspi->Init.Mode;
01702
01703   if (!((tmp_state == HAL_SPI_STATE_READY) || \
01704         ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
01705   {
01706     errorcode = HAL_BUSY;
01707     goto error;
01708   }
01709
01710   if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
01711   {
01712     errorcode = HAL_ERROR;
01713     goto error;
01714   }
01715
01716   /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
01717   if (hspi->State != HAL_SPI_STATE_BUSY_RX)
01718   {
01719     hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
01720   }
01721
01722   /* Set the transaction information */
01723   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01724   hspi->pTxBuffPtr  = (uint8_t *)pTxData;
01725   hspi->TxXferSize  = Size;
01726   hspi->TxXferCount = Size;
01727   hspi->pRxBuffPtr  = (uint8_t *)pRxData;
01728   hspi->RxXferSize  = Size;
01729   hspi->RxXferCount = Size;
01730
01731   /* Set the function for IT treatment */
01732   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01733   {
01734     hspi->RxISR     = SPI_2linesRxISR_16BIT;
01735     hspi->TxISR     = SPI_2linesTxISR_16BIT;
01736   }
01737   else
01738   {
01739     hspi->RxISR     = SPI_2linesRxISR_8BIT;
01740     hspi->TxISR     = SPI_2linesTxISR_8BIT;
01741   }
01742
01743 #if (USE_SPI_CRC != 0U)
01744   /* Reset CRC Calculation */
01745   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01746   {
01747     hspi->CRCSize = 1U;
01748     if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
01749     {
01750       hspi->CRCSize = 2U;
01751     }
01752     SPI_RESET_CRC(hspi);
01753   }
01754   else
01755   {
01756     hspi->CRCSize = 0U;
01757   }
01758 #endif /* USE_SPI_CRC */
01759
01760   /* Check if packing mode is enabled and if there is more than 2 data to receive */
01761   if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size >= 2U))
01762   {
01763     /* Set RX Fifo threshold according the reception data length: 16 bit */
01764     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01765   }
01766   else
01767   {
01768     /* Set RX Fifo threshold according the reception data length: 8 bit */
01769     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01770   }
01771
01772   /* Enable TXE, RXNE and ERR interrupt */
01773   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
01774
01775   /* Check if the SPI is already enabled */
01776   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01777   {
01778     /* Enable SPI peripheral */
01779     __HAL_SPI_ENABLE(hspi);
01780   }
01781
01782 error :
01783   /* Process Unlocked */
01784   __HAL_UNLOCK(hspi);
01785   return errorcode;
01786 }
01787
01788 /**
01789   * @brief  Transmit an amount of data in non-blocking mode with DMA.
01790   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
01791   *               the configuration information for SPI module.
01792   * @param  pData pointer to data buffer
01793   * @param  Size amount of data to be sent
01794   * @retval HAL status
01795   */
01796 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
01797 {
01798   HAL_StatusTypeDef errorcode = HAL_OK;
01799
01800   /* Check tx dma handle */
01801   assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
01802
01803   /* Check Direction parameter */
01804   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
01805
01806   /* Process Locked */
01807   __HAL_LOCK(hspi);
01808
01809   if (hspi->State != HAL_SPI_STATE_READY)
01810   {
01811     errorcode = HAL_BUSY;
01812     goto error;
01813   }
01814
01815   if ((pData == NULL) || (Size == 0U))
01816   {
01817     errorcode = HAL_ERROR;
01818     goto error;
01819   }
01820
01821   /* Set the transaction information */
01822   hspi->State       = HAL_SPI_STATE_BUSY_TX;
01823   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01824   hspi->pTxBuffPtr  = (uint8_t *)pData;
01825   hspi->TxXferSize  = Size;
01826   hspi->TxXferCount = Size;
01827
01828   /* Init field not used in handle to zero */
01829   hspi->pRxBuffPtr  = (uint8_t *)NULL;
01830   hspi->TxISR       = NULL;
01831   hspi->RxISR       = NULL;
01832   hspi->RxXferSize  = 0U;
01833   hspi->RxXferCount = 0U;
01834
01835   /* Configure communication direction : 1Line */
01836   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
01837   {
01838     SPI_1LINE_TX(hspi);
01839   }
01840
01841 #if (USE_SPI_CRC != 0U)
01842   /* Reset CRC Calculation */
01843   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01844   {
01845     SPI_RESET_CRC(hspi);
01846   }
01847 #endif /* USE_SPI_CRC */
01848
01849   /* Set the SPI TxDMA Half transfer complete callback */
01850   hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
01851
01852   /* Set the SPI TxDMA transfer complete callback */
01853   hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
01854
01855   /* Set the DMA error callback */
01856   hspi->hdmatx->XferErrorCallback = SPI_DMAError;
01857
01858   /* Set the DMA AbortCpltCallback */
01859   hspi->hdmatx->XferAbortCallback = NULL;
01860
01861   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
01862   /* Packing mode is enabled only if the DMA setting is HALWORD */
01863   if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
01864   {
01865     /* Check the even/odd of the data size + crc if enabled */
01866     if ((hspi->TxXferCount & 0x1U) == 0U)
01867     {
01868       CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
01869       hspi->TxXferCount = (hspi->TxXferCount >> 1U);
01870     }
01871     else
01872     {
01873       SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
01874       hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
01875     }
01876   }
01877
01878   /* Enable the Tx DMA Stream/Channel */
01879   if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
01880                                  hspi->TxXferCount))
01881   {
01882     /* Update SPI error code */
01883     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
01884     errorcode = HAL_ERROR;
01885
01886     hspi->State = HAL_SPI_STATE_READY;
01887     goto error;
01888   }
01889
01890   /* Check if the SPI is already enabled */
01891   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
01892   {
01893     /* Enable SPI peripheral */
01894     __HAL_SPI_ENABLE(hspi);
01895   }
01896
01897   /* Enable the SPI Error Interrupt Bit */
01898   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
01899
01900   /* Enable Tx DMA Request */
01901   SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
01902
01903 error :
01904   /* Process Unlocked */
01905   __HAL_UNLOCK(hspi);
01906   return errorcode;
01907 }
01908
01909 /**
01910   * @brief  Receive an amount of data in non-blocking mode with DMA.
01911   * @note   In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
01912   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
01913   *               the configuration information for SPI module.
01914   * @param  pData pointer to data buffer
01915   * @note   When the CRC feature is enabled the pData Length must be Size + 1.
01916   * @param  Size amount of data to be sent
01917   * @retval HAL status
01918   */
01919 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
01920 {
01921   HAL_StatusTypeDef errorcode = HAL_OK;
01922
01923   /* Check rx dma handle */
01924   assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
01925
01926   if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
01927   {
01928     hspi->State = HAL_SPI_STATE_BUSY_RX;
01929
01930     /* Check tx dma handle */
01931     assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
01932
01933     /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
01934     return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
01935   }
01936
01937   /* Process Locked */
01938   __HAL_LOCK(hspi);
01939
01940   if (hspi->State != HAL_SPI_STATE_READY)
01941   {
01942     errorcode = HAL_BUSY;
01943     goto error;
01944   }
01945
01946   if ((pData == NULL) || (Size == 0U))
01947   {
01948     errorcode = HAL_ERROR;
01949     goto error;
01950   }
01951
01952   /* Set the transaction information */
01953   hspi->State       = HAL_SPI_STATE_BUSY_RX;
01954   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01955   hspi->pRxBuffPtr  = (uint8_t *)pData;
01956   hspi->RxXferSize  = Size;
01957   hspi->RxXferCount = Size;
01958
01959   /*Init field not used in handle to zero */
01960   hspi->RxISR       = NULL;
01961   hspi->TxISR       = NULL;
01962   hspi->TxXferSize  = 0U;
01963   hspi->TxXferCount = 0U;
01964
01965   /* Configure communication direction : 1Line */
01966   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
01967   {
01968     SPI_1LINE_RX(hspi);
01969   }
01970
01971 #if (USE_SPI_CRC != 0U)
01972   /* Reset CRC Calculation */
01973   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01974   {
01975     SPI_RESET_CRC(hspi);
01976   }
01977 #endif /* USE_SPI_CRC */
01978
01979
01980   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
01981   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
01982   {
01983     /* Set RX Fifo threshold according the reception data length: 16bit */
01984     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01985   }
01986   else
01987   {
01988     /* Set RX Fifo threshold according the reception data length: 8bit */
01989     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01990
01991     if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
01992     {
01993       /* Set RX Fifo threshold according the reception data length: 16bit */
01994       CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
01995
01996       if ((hspi->RxXferCount & 0x1U) == 0x0U)
01997       {
01998         CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
01999         hspi->RxXferCount = hspi->RxXferCount >> 1U;
02000       }
02001       else
02002       {
02003         SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
02004         hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
02005       }
02006     }
02007   }
02008
02009   /* Set the SPI RxDMA Half transfer complete callback */
02010   hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
02011
02012   /* Set the SPI Rx DMA transfer complete callback */
02013   hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
02014
02015   /* Set the DMA error callback */
02016   hspi->hdmarx->XferErrorCallback = SPI_DMAError;
02017
02018   /* Set the DMA AbortCpltCallback */
02019   hspi->hdmarx->XferAbortCallback = NULL;
02020
02021   /* Enable the Rx DMA Stream/Channel  */
02022   if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
02023                                  hspi->RxXferCount))
02024   {
02025     /* Update SPI error code */
02026     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
02027     errorcode = HAL_ERROR;
02028
02029     hspi->State = HAL_SPI_STATE_READY;
02030     goto error;
02031   }
02032
02033   /* Check if the SPI is already enabled */
02034   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
02035   {
02036     /* Enable SPI peripheral */
02037     __HAL_SPI_ENABLE(hspi);
02038   }
02039
02040   /* Enable the SPI Error Interrupt Bit */
02041   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
02042
02043   /* Enable Rx DMA Request */
02044   SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
02045
02046 error:
02047   /* Process Unlocked */
02048   __HAL_UNLOCK(hspi);
02049   return errorcode;
02050 }
02051
02052 /**
02053   * @brief  Transmit and Receive an amount of data in non-blocking mode with DMA.
02054   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02055   *               the configuration information for SPI module.
02056   * @param  pTxData pointer to transmission data buffer
02057   * @param  pRxData pointer to reception data buffer
02058   * @note   When the CRC feature is enabled the pRxData Length must be Size + 1
02059   * @param  Size amount of data to be sent
02060   * @retval HAL status
02061   */
02062 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
02063                                               uint16_t Size)
02064 {
02065   uint32_t             tmp_mode;
02066   HAL_SPI_StateTypeDef tmp_state;
02067   HAL_StatusTypeDef errorcode = HAL_OK;
02068
02069   /* Check rx & tx dma handles */
02070   assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
02071   assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
02072
02073   /* Check Direction parameter */
02074   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
02075
02076   /* Process locked */
02077   __HAL_LOCK(hspi);
02078
02079   /* Init temporary variables */
02080   tmp_state           = hspi->State;
02081   tmp_mode            = hspi->Init.Mode;
02082
02083   if (!((tmp_state == HAL_SPI_STATE_READY) ||
02084         ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
02085   {
02086     errorcode = HAL_BUSY;
02087     goto error;
02088   }
02089
02090   if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
02091   {
02092     errorcode = HAL_ERROR;
02093     goto error;
02094   }
02095
02096   /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
02097   if (hspi->State != HAL_SPI_STATE_BUSY_RX)
02098   {
02099     hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
02100   }
02101
02102   /* Set the transaction information */
02103   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
02104   hspi->pTxBuffPtr  = (uint8_t *)pTxData;
02105   hspi->TxXferSize  = Size;
02106   hspi->TxXferCount = Size;
02107   hspi->pRxBuffPtr  = (uint8_t *)pRxData;
02108   hspi->RxXferSize  = Size;
02109   hspi->RxXferCount = Size;
02110
02111   /* Init field not used in handle to zero */
02112   hspi->RxISR       = NULL;
02113   hspi->TxISR       = NULL;
02114
02115 #if (USE_SPI_CRC != 0U)
02116   /* Reset CRC Calculation */
02117   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02118   {
02119     SPI_RESET_CRC(hspi);
02120   }
02121 #endif /* USE_SPI_CRC */
02122
02123   /* Reset the threshold bit */
02124   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
02125
02126   /* The packing mode management is enabled by the DMA settings according the spi data size */
02127   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
02128   {
02129     /* Set fiforxthreshold according the reception data length: 16bit */
02130     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
02131   }
02132   else
02133   {
02134     /* Set RX Fifo threshold according the reception data length: 8bit */
02135     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
02136
02137     if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
02138     {
02139       if ((hspi->TxXferSize & 0x1U) == 0x0U)
02140       {
02141         CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
02142         hspi->TxXferCount = hspi->TxXferCount >> 1U;
02143       }
02144       else
02145       {
02146         SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
02147         hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
02148       }
02149     }
02150
02151     if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
02152     {
02153       /* Set RX Fifo threshold according the reception data length: 16bit */
02154       CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
02155
02156       if ((hspi->RxXferCount & 0x1U) == 0x0U)
02157       {
02158         CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
02159         hspi->RxXferCount = hspi->RxXferCount >> 1U;
02160       }
02161       else
02162       {
02163         SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
02164         hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
02165       }
02166     }
02167   }
02168
02169   /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
02170   if (hspi->State == HAL_SPI_STATE_BUSY_RX)
02171   {
02172     /* Set the SPI Rx DMA Half transfer complete callback */
02173     hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
02174     hspi->hdmarx->XferCpltCallback     = SPI_DMAReceiveCplt;
02175   }
02176   else
02177   {
02178     /* Set the SPI Tx/Rx DMA Half transfer complete callback */
02179     hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
02180     hspi->hdmarx->XferCpltCallback     = SPI_DMATransmitReceiveCplt;
02181   }
02182
02183   /* Set the DMA error callback */
02184   hspi->hdmarx->XferErrorCallback = SPI_DMAError;
02185
02186   /* Set the DMA AbortCpltCallback */
02187   hspi->hdmarx->XferAbortCallback = NULL;
02188
02189   /* Enable the Rx DMA Stream/Channel  */
02190   if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
02191                                  hspi->RxXferCount))
02192   {
02193     /* Update SPI error code */
02194     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
02195     errorcode = HAL_ERROR;
02196
02197     hspi->State = HAL_SPI_STATE_READY;
02198     goto error;
02199   }
02200
02201   /* Enable Rx DMA Request */
02202   SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
02203
02204   /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
02205   is performed in DMA reception complete callback  */
02206   hspi->hdmatx->XferHalfCpltCallback = NULL;
02207   hspi->hdmatx->XferCpltCallback     = NULL;
02208   hspi->hdmatx->XferErrorCallback    = NULL;
02209   hspi->hdmatx->XferAbortCallback    = NULL;
02210
02211   /* Enable the Tx DMA Stream/Channel  */
02212   if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
02213                                  hspi->TxXferCount))
02214   {
02215     /* Update SPI error code */
02216     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
02217     errorcode = HAL_ERROR;
02218
02219     hspi->State = HAL_SPI_STATE_READY;
02220     goto error;
02221   }
02222
02223   /* Check if the SPI is already enabled */
02224   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
02225   {
02226     /* Enable SPI peripheral */
02227     __HAL_SPI_ENABLE(hspi);
02228   }
02229   /* Enable the SPI Error Interrupt Bit */
02230   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
02231
02232   /* Enable Tx DMA Request */
02233   SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
02234
02235 error :
02236   /* Process Unlocked */
02237   __HAL_UNLOCK(hspi);
02238   return errorcode;
02239 }
02240
02241 /**
02242   * @brief  Abort ongoing transfer (blocking mode).
02243   * @param  hspi SPI handle.
02244   * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),
02245   *         started in Interrupt or DMA mode.
02246   *         This procedure performs following operations :
02247   *           - Disable SPI Interrupts (depending of transfer direction)
02248   *           - Disable the DMA transfer in the peripheral register (if enabled)
02249   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
02250   *           - Set handle State to READY
02251   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
02252   * @retval HAL status
02253   */
02254 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
02255 {
02256   HAL_StatusTypeDef errorcode;
02257   __IO uint32_t count;
02258   __IO uint32_t resetcount;
02259
02260   /* Initialized local variable  */
02261   errorcode = HAL_OK;
02262   resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
02263   count = resetcount;
02264
02265   /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
02266   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
02267
02268   /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
02269   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
02270   {
02271     hspi->TxISR = SPI_AbortTx_ISR;
02272     /* Wait HAL_SPI_STATE_ABORT state */
02273     do
02274     {
02275       if (count == 0U)
02276       {
02277         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
02278         break;
02279       }
02280       count--;
02281     } while (hspi->State != HAL_SPI_STATE_ABORT);
02282     /* Reset Timeout Counter */
02283     count = resetcount;
02284   }
02285
02286   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
02287   {
02288     hspi->RxISR = SPI_AbortRx_ISR;
02289     /* Wait HAL_SPI_STATE_ABORT state */
02290     do
02291     {
02292       if (count == 0U)
02293       {
02294         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
02295         break;
02296       }
02297       count--;
02298     } while (hspi->State != HAL_SPI_STATE_ABORT);
02299     /* Reset Timeout Counter */
02300     count = resetcount;
02301   }
02302
02303   /* Disable the SPI DMA Tx request if enabled */
02304   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
02305   {
02306     /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
02307     if (hspi->hdmatx != NULL)
02308     {
02309       /* Set the SPI DMA Abort callback :
02310       will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
02311       hspi->hdmatx->XferAbortCallback = NULL;
02312
02313       /* Abort DMA Tx Handle linked to SPI Peripheral */
02314       if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
02315       {
02316         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02317       }
02318
02319       /* Disable Tx DMA Request */
02320       CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
02321
02322       if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
02323       {
02324         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02325       }
02326
02327       /* Disable SPI Peripheral */
02328       __HAL_SPI_DISABLE(hspi);
02329
02330       /* Empty the FRLVL fifo */
02331       if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
02332       {
02333         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02334       }
02335     }
02336   }
02337
02338   /* Disable the SPI DMA Rx request if enabled */
02339   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
02340   {
02341     /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
02342     if (hspi->hdmarx != NULL)
02343     {
02344       /* Set the SPI DMA Abort callback :
02345       will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
02346       hspi->hdmarx->XferAbortCallback = NULL;
02347
02348       /* Abort DMA Rx Handle linked to SPI Peripheral */
02349       if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
02350       {
02351         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02352       }
02353
02354       /* Disable peripheral */
02355       __HAL_SPI_DISABLE(hspi);
02356
02357       /* Control the BSY flag */
02358       if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
02359       {
02360         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02361       }
02362
02363       /* Empty the FRLVL fifo */
02364       if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
02365       {
02366         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02367       }
02368
02369       /* Disable Rx DMA Request */
02370       CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
02371     }
02372   }
02373   /* Reset Tx and Rx transfer counters */
02374   hspi->RxXferCount = 0U;
02375   hspi->TxXferCount = 0U;
02376
02377   /* Check error during Abort procedure */
02378   if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
02379   {
02380     /* return HAL_Error in case of error during Abort procedure */
02381     errorcode = HAL_ERROR;
02382   }
02383   else
02384   {
02385     /* Reset errorCode */
02386     hspi->ErrorCode = HAL_SPI_ERROR_NONE;
02387   }
02388
02389   /* Clear the Error flags in the SR register */
02390   __HAL_SPI_CLEAR_OVRFLAG(hspi);
02391   __HAL_SPI_CLEAR_FREFLAG(hspi);
02392
02393   /* Restore hspi->state to ready */
02394   hspi->State = HAL_SPI_STATE_READY;
02395
02396   return errorcode;
02397 }
02398
02399 /**
02400   * @brief  Abort ongoing transfer (Interrupt mode).
02401   * @param  hspi SPI handle.
02402   * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),
02403   *         started in Interrupt or DMA mode.
02404   *         This procedure performs following operations :
02405   *           - Disable SPI Interrupts (depending of transfer direction)
02406   *           - Disable the DMA transfer in the peripheral register (if enabled)
02407   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
02408   *           - Set handle State to READY
02409   *           - At abort completion, call user abort complete callback
02410   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
02411   *         considered as completed only when user abort complete callback is executed (not when exiting function).
02412   * @retval HAL status
02413   */
02414 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
02415 {
02416   HAL_StatusTypeDef errorcode;
02417   uint32_t abortcplt ;
02418   __IO uint32_t count;
02419   __IO uint32_t resetcount;
02420
02421   /* Initialized local variable  */
02422   errorcode = HAL_OK;
02423   abortcplt = 1U;
02424   resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
02425   count = resetcount;
02426
02427   /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
02428   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
02429
02430   /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
02431   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
02432   {
02433     hspi->TxISR = SPI_AbortTx_ISR;
02434     /* Wait HAL_SPI_STATE_ABORT state */
02435     do
02436     {
02437       if (count == 0U)
02438       {
02439         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
02440         break;
02441       }
02442       count--;
02443     } while (hspi->State != HAL_SPI_STATE_ABORT);
02444     /* Reset Timeout Counter */
02445     count = resetcount;
02446   }
02447
02448   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
02449   {
02450     hspi->RxISR = SPI_AbortRx_ISR;
02451     /* Wait HAL_SPI_STATE_ABORT state */
02452     do
02453     {
02454       if (count == 0U)
02455       {
02456         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
02457         break;
02458       }
02459       count--;
02460     } while (hspi->State != HAL_SPI_STATE_ABORT);
02461     /* Reset Timeout Counter */
02462     count = resetcount;
02463   }
02464
02465   /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
02466      before any call to DMA Abort functions */
02467   /* DMA Tx Handle is valid */
02468   if (hspi->hdmatx != NULL)
02469   {
02470     /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
02471        Otherwise, set it to NULL */
02472     if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
02473     {
02474       hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
02475     }
02476     else
02477     {
02478       hspi->hdmatx->XferAbortCallback = NULL;
02479     }
02480   }
02481   /* DMA Rx Handle is valid */
02482   if (hspi->hdmarx != NULL)
02483   {
02484     /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
02485        Otherwise, set it to NULL */
02486     if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
02487     {
02488       hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
02489     }
02490     else
02491     {
02492       hspi->hdmarx->XferAbortCallback = NULL;
02493     }
02494   }
02495
02496   /* Disable the SPI DMA Tx request if enabled */
02497   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
02498   {
02499     /* Abort the SPI DMA Tx Stream/Channel */
02500     if (hspi->hdmatx != NULL)
02501     {
02502       /* Abort DMA Tx Handle linked to SPI Peripheral */
02503       if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
02504       {
02505         hspi->hdmatx->XferAbortCallback = NULL;
02506         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02507       }
02508       else
02509       {
02510         abortcplt = 0U;
02511       }
02512     }
02513   }
02514   /* Disable the SPI DMA Rx request if enabled */
02515   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
02516   {
02517     /* Abort the SPI DMA Rx Stream/Channel */
02518     if (hspi->hdmarx != NULL)
02519     {
02520       /* Abort DMA Rx Handle linked to SPI Peripheral */
02521       if (HAL_DMA_Abort_IT(hspi->hdmarx) !=  HAL_OK)
02522       {
02523         hspi->hdmarx->XferAbortCallback = NULL;
02524         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
02525       }
02526       else
02527       {
02528         abortcplt = 0U;
02529       }
02530     }
02531   }
02532
02533   if (abortcplt == 1U)
02534   {
02535     /* Reset Tx and Rx transfer counters */
02536     hspi->RxXferCount = 0U;
02537     hspi->TxXferCount = 0U;
02538
02539     /* Check error during Abort procedure */
02540     if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
02541     {
02542       /* return HAL_Error in case of error during Abort procedure */
02543       errorcode = HAL_ERROR;
02544     }
02545     else
02546     {
02547       /* Reset errorCode */
02548       hspi->ErrorCode = HAL_SPI_ERROR_NONE;
02549     }
02550
02551     /* Clear the Error flags in the SR register */
02552     __HAL_SPI_CLEAR_OVRFLAG(hspi);
02553     __HAL_SPI_CLEAR_FREFLAG(hspi);
02554
02555     /* Restore hspi->State to Ready */
02556     hspi->State = HAL_SPI_STATE_READY;
02557
02558     /* As no DMA to be aborted, call directly user Abort complete callback */
02559 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
02560     hspi->AbortCpltCallback(hspi);
02561 #else
02562     HAL_SPI_AbortCpltCallback(hspi);
02563 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
02564   }
02565
02566   return errorcode;
02567 }
02568
02569 /**
02570   * @brief  Pause the DMA Transfer.
02571   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02572   *               the configuration information for the specified SPI module.
02573   * @retval HAL status
02574   */
02575 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
02576 {
02577   /* Process Locked */
02578   __HAL_LOCK(hspi);
02579
02580   /* Disable the SPI DMA Tx & Rx requests */
02581   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
02582
02583   /* Process Unlocked */
02584   __HAL_UNLOCK(hspi);
02585
02586   return HAL_OK;
02587 }
02588
02589 /**
02590   * @brief  Resume the DMA Transfer.
02591   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02592   *               the configuration information for the specified SPI module.
02593   * @retval HAL status
02594   */
02595 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
02596 {
02597   /* Process Locked */
02598   __HAL_LOCK(hspi);
02599
02600   /* Enable the SPI DMA Tx & Rx requests */
02601   SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
02602
02603   /* Process Unlocked */
02604   __HAL_UNLOCK(hspi);
02605
02606   return HAL_OK;
02607 }
02608
02609 /**
02610   * @brief  Stop the DMA Transfer.
02611   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02612   *               the configuration information for the specified SPI module.
02613   * @retval HAL status
02614   */
02615 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
02616 {
02617   HAL_StatusTypeDef errorcode = HAL_OK;
02618   /* The Lock is not implemented on this API to allow the user application
02619      to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
02620      when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
02621      and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
02622      */
02623
02624   /* Abort the SPI DMA tx Stream/Channel  */
02625   if (hspi->hdmatx != NULL)
02626   {
02627     if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx))
02628     {
02629       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
02630       errorcode = HAL_ERROR;
02631     }
02632   }
02633   /* Abort the SPI DMA rx Stream/Channel  */
02634   if (hspi->hdmarx != NULL)
02635   {
02636     if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx))
02637     {
02638       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
02639       errorcode = HAL_ERROR;
02640     }
02641   }
02642
02643   /* Disable the SPI DMA Tx & Rx requests */
02644   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
02645   hspi->State = HAL_SPI_STATE_READY;
02646   return errorcode;
02647 }
02648
02649 /**
02650   * @brief  Handle SPI interrupt request.
02651   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02652   *               the configuration information for the specified SPI module.
02653   * @retval None
02654   */
02655 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
02656 {
02657   uint32_t itsource = hspi->Instance->CR2;
02658   uint32_t itflag   = hspi->Instance->SR;
02659
02660   /* SPI in mode Receiver ----------------------------------------------------*/
02661   if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
02662       (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
02663   {
02664     hspi->RxISR(hspi);
02665     return;
02666   }
02667
02668   /* SPI in mode Transmitter -------------------------------------------------*/
02669   if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))
02670   {
02671     hspi->TxISR(hspi);
02672     return;
02673   }
02674
02675   /* SPI in Error Treatment --------------------------------------------------*/
02676   if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
02677        || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
02678   {
02679     /* SPI Overrun error interrupt occurred ----------------------------------*/
02680     if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
02681     {
02682       if (hspi->State != HAL_SPI_STATE_BUSY_TX)
02683       {
02684         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
02685         __HAL_SPI_CLEAR_OVRFLAG(hspi);
02686       }
02687       else
02688       {
02689         __HAL_SPI_CLEAR_OVRFLAG(hspi);
02690         return;
02691       }
02692     }
02693
02694     /* SPI Mode Fault error interrupt occurred -------------------------------*/
02695     if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)
02696     {
02697       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
02698       __HAL_SPI_CLEAR_MODFFLAG(hspi);
02699     }
02700
02701     /* SPI Frame error interrupt occurred ------------------------------------*/
02702     if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)
02703     {
02704       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
02705       __HAL_SPI_CLEAR_FREFLAG(hspi);
02706     }
02707
02708     if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
02709     {
02710       /* Disable all interrupts */
02711       __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
02712
02713       hspi->State = HAL_SPI_STATE_READY;
02714       /* Disable the SPI DMA requests if enabled */
02715       if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
02716       {
02717         CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
02718
02719         /* Abort the SPI DMA Rx channel */
02720         if (hspi->hdmarx != NULL)
02721         {
02722           /* Set the SPI DMA Abort callback :
02723           will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
02724           hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
02725           if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
02726           {
02727             SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
02728           }
02729         }
02730         /* Abort the SPI DMA Tx channel */
02731         if (hspi->hdmatx != NULL)
02732         {
02733           /* Set the SPI DMA Abort callback :
02734           will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
02735           hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
02736           if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
02737           {
02738             SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
02739           }
02740         }
02741       }
02742       else
02743       {
02744         /* Call user error callback */
02745 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
02746         hspi->ErrorCallback(hspi);
02747 #else
02748         HAL_SPI_ErrorCallback(hspi);
02749 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
02750       }
02751     }
02752     return;
02753   }
02754 }
02755
02756 /**
02757   * @brief  Tx Transfer completed callback.
02758   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02759   *               the configuration information for SPI module.
02760   * @retval None
02761   */
02762 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
02763 {
02764   /* Prevent unused argument(s) compilation warning */
02765   UNUSED(hspi);
02766
02767   /* NOTE : This function should not be modified, when the callback is needed,
02768             the HAL_SPI_TxCpltCallback should be implemented in the user file
02769    */
02770 }
02771
02772 /**
02773   * @brief  Rx Transfer completed callback.
02774   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02775   *               the configuration information for SPI module.
02776   * @retval None
02777   */
02778 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
02779 {
02780   /* Prevent unused argument(s) compilation warning */
02781   UNUSED(hspi);
02782
02783   /* NOTE : This function should not be modified, when the callback is needed,
02784             the HAL_SPI_RxCpltCallback should be implemented in the user file
02785    */
02786 }
02787
02788 /**
02789   * @brief  Tx and Rx Transfer completed callback.
02790   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02791   *               the configuration information for SPI module.
02792   * @retval None
02793   */
02794 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
02795 {
02796   /* Prevent unused argument(s) compilation warning */
02797   UNUSED(hspi);
02798
02799   /* NOTE : This function should not be modified, when the callback is needed,
02800             the HAL_SPI_TxRxCpltCallback should be implemented in the user file
02801    */
02802 }
02803
02804 /**
02805   * @brief  Tx Half Transfer completed callback.
02806   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02807   *               the configuration information for SPI module.
02808   * @retval None
02809   */
02810 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
02811 {
02812   /* Prevent unused argument(s) compilation warning */
02813   UNUSED(hspi);
02814
02815   /* NOTE : This function should not be modified, when the callback is needed,
02816             the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
02817    */
02818 }
02819
02820 /**
02821   * @brief  Rx Half Transfer completed callback.
02822   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02823   *               the configuration information for SPI module.
02824   * @retval None
02825   */
02826 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
02827 {
02828   /* Prevent unused argument(s) compilation warning */
02829   UNUSED(hspi);
02830
02831   /* NOTE : This function should not be modified, when the callback is needed,
02832             the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
02833    */
02834 }
02835
02836 /**
02837   * @brief  Tx and Rx Half Transfer callback.
02838   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02839   *               the configuration information for SPI module.
02840   * @retval None
02841   */
02842 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
02843 {
02844   /* Prevent unused argument(s) compilation warning */
02845   UNUSED(hspi);
02846
02847   /* NOTE : This function should not be modified, when the callback is needed,
02848             the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
02849    */
02850 }
02851
02852 /**
02853   * @brief  SPI error callback.
02854   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02855   *               the configuration information for SPI module.
02856   * @retval None
02857   */
02858 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
02859 {
02860   /* Prevent unused argument(s) compilation warning */
02861   UNUSED(hspi);
02862
02863   /* NOTE : This function should not be modified, when the callback is needed,
02864             the HAL_SPI_ErrorCallback should be implemented in the user file
02865    */
02866   /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
02867             and user can use HAL_SPI_GetError() API to check the latest error occurred
02868    */
02869 }
02870
02871 /**
02872   * @brief  SPI Abort Complete callback.
02873   * @param  hspi SPI handle.
02874   * @retval None
02875   */
02876 __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
02877 {
02878   /* Prevent unused argument(s) compilation warning */
02879   UNUSED(hspi);
02880
02881   /* NOTE : This function should not be modified, when the callback is needed,
02882             the HAL_SPI_AbortCpltCallback can be implemented in the user file.
02883    */
02884 }
02885
02886 /**
02887   * @}
02888   */
02889
02890 /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
02891   * @brief   SPI control functions
02892   *
02893 @verbatim
02894  ===============================================================================
02895                       ##### Peripheral State and Errors functions #####
02896  ===============================================================================
02897     [..]
02898     This subsection provides a set of functions allowing to control the SPI.
02899      (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
02900      (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
02901 @endverbatim
02902   * @{
02903   */
02904
02905 /**
02906   * @brief  Return the SPI handle state.
02907   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02908   *               the configuration information for SPI module.
02909   * @retval SPI state
02910   */
02911 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
02912 {
02913   /* Return SPI handle state */
02914   return hspi->State;
02915 }
02916
02917 /**
02918   * @brief  Return the SPI error code.
02919   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
02920   *               the configuration information for SPI module.
02921   * @retval SPI error code in bitmap format
02922   */
02923 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
02924 {
02925   /* Return SPI ErrorCode */
02926   return hspi->ErrorCode;
02927 }
02928
02929 /**
02930   * @}
02931   */
02932
02933 /**
02934   * @}
02935   */
02936
02937 /** @addtogroup SPI_Private_Functions
02938   * @brief   Private functions
02939   * @{
02940   */
02941
02942 /**
02943   * @brief  DMA SPI transmit process complete callback.
02944   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
02945   *               the configuration information for the specified DMA module.
02946   * @retval None
02947   */
02948 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
02949 {
02950   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
02951   uint32_t tickstart;
02952
02953   /* Init tickstart for timeout management*/
02954   tickstart = HAL_GetTick();
02955
02956   /* DMA Normal Mode */
02957   if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
02958   {
02959     /* Disable ERR interrupt */
02960     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
02961
02962     /* Disable Tx DMA Request */
02963     CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
02964
02965     /* Check the end of the transaction */
02966     if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
02967     {
02968       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
02969     }
02970
02971     /* Clear overrun flag in 2 Lines communication mode because received data is not read */
02972     if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
02973     {
02974       __HAL_SPI_CLEAR_OVRFLAG(hspi);
02975     }
02976
02977     hspi->TxXferCount = 0U;
02978     hspi->State = HAL_SPI_STATE_READY;
02979
02980     if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
02981     {
02982       /* Call user error callback */
02983 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
02984       hspi->ErrorCallback(hspi);
02985 #else
02986       HAL_SPI_ErrorCallback(hspi);
02987 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
02988       return;
02989     }
02990   }
02991   /* Call user Tx complete callback */
02992 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
02993   hspi->TxCpltCallback(hspi);
02994 #else
02995   HAL_SPI_TxCpltCallback(hspi);
02996 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
02997 }
02998
02999 /**
03000   * @brief  DMA SPI receive process complete callback.
03001   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
03002   *               the configuration information for the specified DMA module.
03003   * @retval None
03004   */
03005 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
03006 {
03007   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
03008   uint32_t tickstart;
03009
03010   /* Init tickstart for timeout management*/
03011   tickstart = HAL_GetTick();
03012
03013   /* DMA Normal Mode */
03014   if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
03015   {
03016     /* Disable ERR interrupt */
03017     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
03018
03019 #if (USE_SPI_CRC != 0U)
03020     /* CRC handling */
03021     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03022     {
03023       /* Wait until RXNE flag */
03024       if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
03025       {
03026         /* Error on the CRC reception */
03027         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
03028       }
03029       /* Read CRC */
03030       if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
03031       {
03032         /* Read 16bit CRC */
03033         READ_REG(hspi->Instance->DR);
03034       }
03035       else
03036       {
03037         /* Read 8bit CRC */
03038         READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
03039
03040         if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
03041         {
03042           if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
03043           {
03044             /* Error on the CRC reception */
03045             SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
03046           }
03047           /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
03048           READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
03049         }
03050       }
03051     }
03052 #endif /* USE_SPI_CRC */
03053
03054     /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
03055     CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
03056
03057     /* Check the end of the transaction */
03058     if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
03059     {
03060       hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
03061     }
03062
03063     hspi->RxXferCount = 0U;
03064     hspi->State = HAL_SPI_STATE_READY;
03065
03066 #if (USE_SPI_CRC != 0U)
03067     /* Check if CRC error occurred */
03068     if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
03069     {
03070       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
03071       __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
03072     }
03073 #endif /* USE_SPI_CRC */
03074
03075     if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
03076     {
03077       /* Call user error callback */
03078 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
03079       hspi->ErrorCallback(hspi);
03080 #else
03081       HAL_SPI_ErrorCallback(hspi);
03082 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03083       return;
03084     }
03085   }
03086   /* Call user Rx complete callback */
03087 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
03088   hspi->RxCpltCallback(hspi);
03089 #else
03090   HAL_SPI_RxCpltCallback(hspi);
03091 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03092 }
03093
03094 /**
03095   * @brief  DMA SPI transmit receive process complete callback.
03096   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
03097   *               the configuration information for the specified DMA module.
03098   * @retval None
03099   */
03100 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
03101 {
03102   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
03103   uint32_t tickstart;
03104
03105   /* Init tickstart for timeout management*/
03106   tickstart = HAL_GetTick();
03107
03108   /* DMA Normal Mode */
03109   if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
03110   {
03111     /* Disable ERR interrupt */
03112     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
03113
03114 #if (USE_SPI_CRC != 0U)
03115     /* CRC handling */
03116     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03117     {
03118       if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
03119       {
03120         if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT,
03121                                           tickstart) != HAL_OK)
03122         {
03123           /* Error on the CRC reception */
03124           SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
03125         }
03126         /* Read CRC to Flush DR and RXNE flag */
03127         READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
03128       }
03129       else
03130       {
03131         if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
03132         {
03133           /* Error on the CRC reception */
03134           SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
03135         }
03136         /* Read CRC to Flush DR and RXNE flag */
03137         READ_REG(hspi->Instance->DR);
03138       }
03139     }
03140 #endif /* USE_SPI_CRC */
03141
03142     /* Check the end of the transaction */
03143     if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
03144     {
03145       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
03146     }
03147
03148     /* Disable Rx/Tx DMA Request */
03149     CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
03150
03151     hspi->TxXferCount = 0U;
03152     hspi->RxXferCount = 0U;
03153     hspi->State = HAL_SPI_STATE_READY;
03154
03155 #if (USE_SPI_CRC != 0U)
03156     /* Check if CRC error occurred */
03157     if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
03158     {
03159       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
03160       __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
03161     }
03162 #endif /* USE_SPI_CRC */
03163
03164     if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
03165     {
03166       /* Call user error callback */
03167 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
03168       hspi->ErrorCallback(hspi);
03169 #else
03170       HAL_SPI_ErrorCallback(hspi);
03171 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03172       return;
03173     }
03174   }
03175   /* Call user TxRx complete callback */
03176 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
03177   hspi->TxRxCpltCallback(hspi);
03178 #else
03179   HAL_SPI_TxRxCpltCallback(hspi);
03180 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03181 }
03182
03183 /**
03184   * @brief  DMA SPI half transmit process complete callback.
03185   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
03186   *               the configuration information for the specified DMA module.
03187   * @retval None
03188   */
03189 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
03190 {
03191   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
03192
03193   /* Call user Tx half complete callback */
03194 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
03195   hspi->TxHalfCpltCallback(hspi);
03196 #else
03197   HAL_SPI_TxHalfCpltCallback(hspi);
03198 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03199 }
03200
03201 /**
03202   * @brief  DMA SPI half receive process complete callback
03203   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
03204   *               the configuration information for the specified DMA module.
03205   * @retval None
03206   */
03207 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
03208 {
03209   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
03210
03211   /* Call user Rx half complete callback */
03212 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
03213   hspi->RxHalfCpltCallback(hspi);
03214 #else
03215   HAL_SPI_RxHalfCpltCallback(hspi);
03216 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03217 }
03218
03219 /**
03220   * @brief  DMA SPI half transmit receive process complete callback.
03221   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
03222   *               the configuration information for the specified DMA module.
03223   * @retval None
03224   */
03225 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
03226 {
03227   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
03228
03229   /* Call user TxRx half complete callback */
03230 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
03231   hspi->TxRxHalfCpltCallback(hspi);
03232 #else
03233   HAL_SPI_TxRxHalfCpltCallback(hspi);
03234 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03235 }
03236
03237 /**
03238   * @brief  DMA SPI communication error callback.
03239   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
03240   *               the configuration information for the specified DMA module.
03241   * @retval None
03242   */
03243 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
03244 {
03245   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
03246
03247   /* Stop the disable DMA transfer on SPI side */
03248   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
03249
03250   SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
03251   hspi->State = HAL_SPI_STATE_READY;
03252   /* Call user error callback */
03253 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
03254   hspi->ErrorCallback(hspi);
03255 #else
03256   HAL_SPI_ErrorCallback(hspi);
03257 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03258 }
03259
03260 /**
03261   * @brief  DMA SPI communication abort callback, when initiated by HAL services on Error
03262   *         (To be called at end of DMA Abort procedure following error occurrence).
03263   * @param  hdma DMA handle.
03264   * @retval None
03265   */
03266 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
03267 {
03268   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
03269   hspi->RxXferCount = 0U;
03270   hspi->TxXferCount = 0U;
03271
03272   /* Call user error callback */
03273 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
03274   hspi->ErrorCallback(hspi);
03275 #else
03276   HAL_SPI_ErrorCallback(hspi);
03277 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03278 }
03279
03280 /**
03281   * @brief  DMA SPI Tx communication abort callback, when initiated by user
03282   *         (To be called at end of DMA Tx Abort procedure following user abort request).
03283   * @note   When this callback is executed, User Abort complete call back is called only if no
03284   *         Abort still ongoing for Rx DMA Handle.
03285   * @param  hdma DMA handle.
03286   * @retval None
03287   */
03288 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
03289 {
03290   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
03291
03292   hspi->hdmatx->XferAbortCallback = NULL;
03293
03294   /* Disable Tx DMA Request */
03295   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
03296
03297   if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
03298   {
03299     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
03300   }
03301
03302   /* Disable SPI Peripheral */
03303   __HAL_SPI_DISABLE(hspi);
03304
03305   /* Empty the FRLVL fifo */
03306   if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
03307   {
03308     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
03309   }
03310
03311   /* Check if an Abort process is still ongoing */
03312   if (hspi->hdmarx != NULL)
03313   {
03314     if (hspi->hdmarx->XferAbortCallback != NULL)
03315     {
03316       return;
03317     }
03318   }
03319
03320   /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
03321   hspi->RxXferCount = 0U;
03322   hspi->TxXferCount = 0U;
03323
03324   /* Check no error during Abort procedure */
03325   if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
03326   {
03327     /* Reset errorCode */
03328     hspi->ErrorCode = HAL_SPI_ERROR_NONE;
03329   }
03330
03331   /* Clear the Error flags in the SR register */
03332   __HAL_SPI_CLEAR_OVRFLAG(hspi);
03333   __HAL_SPI_CLEAR_FREFLAG(hspi);
03334
03335   /* Restore hspi->State to Ready */
03336   hspi->State  = HAL_SPI_STATE_READY;
03337
03338   /* Call user Abort complete callback */
03339 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
03340   hspi->AbortCpltCallback(hspi);
03341 #else
03342   HAL_SPI_AbortCpltCallback(hspi);
03343 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03344 }
03345
03346 /**
03347   * @brief  DMA SPI Rx communication abort callback, when initiated by user
03348   *         (To be called at end of DMA Rx Abort procedure following user abort request).
03349   * @note   When this callback is executed, User Abort complete call back is called only if no
03350   *         Abort still ongoing for Tx DMA Handle.
03351   * @param  hdma DMA handle.
03352   * @retval None
03353   */
03354 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
03355 {
03356   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
03357
03358   /* Disable SPI Peripheral */
03359   __HAL_SPI_DISABLE(hspi);
03360
03361   hspi->hdmarx->XferAbortCallback = NULL;
03362
03363   /* Disable Rx DMA Request */
03364   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
03365
03366   /* Control the BSY flag */
03367   if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
03368   {
03369     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
03370   }
03371
03372   /* Empty the FRLVL fifo */
03373   if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
03374   {
03375     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
03376   }
03377
03378   /* Check if an Abort process is still ongoing */
03379   if (hspi->hdmatx != NULL)
03380   {
03381     if (hspi->hdmatx->XferAbortCallback != NULL)
03382     {
03383       return;
03384     }
03385   }
03386
03387   /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
03388   hspi->RxXferCount = 0U;
03389   hspi->TxXferCount = 0U;
03390
03391   /* Check no error during Abort procedure */
03392   if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
03393   {
03394     /* Reset errorCode */
03395     hspi->ErrorCode = HAL_SPI_ERROR_NONE;
03396   }
03397
03398   /* Clear the Error flags in the SR register */
03399   __HAL_SPI_CLEAR_OVRFLAG(hspi);
03400   __HAL_SPI_CLEAR_FREFLAG(hspi);
03401
03402   /* Restore hspi->State to Ready */
03403   hspi->State  = HAL_SPI_STATE_READY;
03404
03405   /* Call user Abort complete callback */
03406 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
03407   hspi->AbortCpltCallback(hspi);
03408 #else
03409   HAL_SPI_AbortCpltCallback(hspi);
03410 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03411 }
03412
03413 /**
03414   * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
03415   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03416   *               the configuration information for SPI module.
03417   * @retval None
03418   */
03419 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
03420 {
03421   /* Receive data in packing mode */
03422   if (hspi->RxXferCount > 1U)
03423   {
03424     *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
03425     hspi->pRxBuffPtr += sizeof(uint16_t);
03426     hspi->RxXferCount -= 2U;
03427     if (hspi->RxXferCount == 1U)
03428     {
03429       /* Set RX Fifo threshold according the reception data length: 8bit */
03430       SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
03431     }
03432   }
03433   /* Receive data in 8 Bit mode */
03434   else
03435   {
03436     *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR);
03437     hspi->pRxBuffPtr++;
03438     hspi->RxXferCount--;
03439   }
03440
03441   /* Check end of the reception */
03442   if (hspi->RxXferCount == 0U)
03443   {
03444 #if (USE_SPI_CRC != 0U)
03445     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03446     {
03447       SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
03448       hspi->RxISR =  SPI_2linesRxISR_8BITCRC;
03449       return;
03450     }
03451 #endif /* USE_SPI_CRC */
03452
03453     /* Disable RXNE  and ERR interrupt */
03454     __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
03455
03456     if (hspi->TxXferCount == 0U)
03457     {
03458       SPI_CloseRxTx_ISR(hspi);
03459     }
03460   }
03461 }
03462
03463 #if (USE_SPI_CRC != 0U)
03464 /**
03465   * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
03466   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03467   *               the configuration information for SPI module.
03468   * @retval None
03469   */
03470 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
03471 {
03472   /* Read 8bit CRC to flush Data Regsiter */
03473   READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
03474
03475   hspi->CRCSize--;
03476
03477   /* Check end of the reception */
03478   if (hspi->CRCSize == 0U)
03479   {
03480     /* Disable RXNE and ERR interrupt */
03481     __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
03482
03483     if (hspi->TxXferCount == 0U)
03484     {
03485       SPI_CloseRxTx_ISR(hspi);
03486     }
03487   }
03488 }
03489 #endif /* USE_SPI_CRC */
03490
03491 /**
03492   * @brief  Tx 8-bit handler for Transmit and Receive in Interrupt mode.
03493   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03494   *               the configuration information for SPI module.
03495   * @retval None
03496   */
03497 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
03498 {
03499   /* Transmit data in packing Bit mode */
03500   if (hspi->TxXferCount >= 2U)
03501   {
03502     hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
03503     hspi->pTxBuffPtr += sizeof(uint16_t);
03504     hspi->TxXferCount -= 2U;
03505   }
03506   /* Transmit data in 8 Bit mode */
03507   else
03508   {
03509     *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
03510     hspi->pTxBuffPtr++;
03511     hspi->TxXferCount--;
03512   }
03513
03514   /* Check the end of the transmission */
03515   if (hspi->TxXferCount == 0U)
03516   {
03517 #if (USE_SPI_CRC != 0U)
03518     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03519     {
03520       /* Set CRC Next Bit to send CRC */
03521       SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
03522       /* Disable TXE interrupt */
03523       __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
03524       return;
03525     }
03526 #endif /* USE_SPI_CRC */
03527
03528     /* Disable TXE interrupt */
03529     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
03530
03531     if (hspi->RxXferCount == 0U)
03532     {
03533       SPI_CloseRxTx_ISR(hspi);
03534     }
03535   }
03536 }
03537
03538 /**
03539   * @brief  Rx 16-bit handler for Transmit and Receive in Interrupt mode.
03540   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03541   *               the configuration information for SPI module.
03542   * @retval None
03543   */
03544 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
03545 {
03546   /* Receive data in 16 Bit mode */
03547   *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
03548   hspi->pRxBuffPtr += sizeof(uint16_t);
03549   hspi->RxXferCount--;
03550
03551   if (hspi->RxXferCount == 0U)
03552   {
03553 #if (USE_SPI_CRC != 0U)
03554     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03555     {
03556       hspi->RxISR =  SPI_2linesRxISR_16BITCRC;
03557       return;
03558     }
03559 #endif /* USE_SPI_CRC */
03560
03561     /* Disable RXNE interrupt */
03562     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
03563
03564     if (hspi->TxXferCount == 0U)
03565     {
03566       SPI_CloseRxTx_ISR(hspi);
03567     }
03568   }
03569 }
03570
03571 #if (USE_SPI_CRC != 0U)
03572 /**
03573   * @brief  Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
03574   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03575   *               the configuration information for SPI module.
03576   * @retval None
03577   */
03578 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
03579 {
03580   /* Read 16bit CRC to flush Data Regsiter */
03581   READ_REG(hspi->Instance->DR);
03582
03583   /* Disable RXNE interrupt */
03584   __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
03585
03586   SPI_CloseRxTx_ISR(hspi);
03587 }
03588 #endif /* USE_SPI_CRC */
03589
03590 /**
03591   * @brief  Tx 16-bit handler for Transmit and Receive in Interrupt mode.
03592   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03593   *               the configuration information for SPI module.
03594   * @retval None
03595   */
03596 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
03597 {
03598   /* Transmit data in 16 Bit mode */
03599   hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
03600   hspi->pTxBuffPtr += sizeof(uint16_t);
03601   hspi->TxXferCount--;
03602
03603   /* Enable CRC Transmission */
03604   if (hspi->TxXferCount == 0U)
03605   {
03606 #if (USE_SPI_CRC != 0U)
03607     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03608     {
03609       /* Set CRC Next Bit to send CRC */
03610       SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
03611       /* Disable TXE interrupt */
03612       __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
03613       return;
03614     }
03615 #endif /* USE_SPI_CRC */
03616
03617     /* Disable TXE interrupt */
03618     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
03619
03620     if (hspi->RxXferCount == 0U)
03621     {
03622       SPI_CloseRxTx_ISR(hspi);
03623     }
03624   }
03625 }
03626
03627 #if (USE_SPI_CRC != 0U)
03628 /**
03629   * @brief  Manage the CRC 8-bit receive in Interrupt context.
03630   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03631   *               the configuration information for SPI module.
03632   * @retval None
03633   */
03634 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
03635 {
03636   /* Read 8bit CRC to flush Data Register */
03637   READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
03638
03639   hspi->CRCSize--;
03640
03641   if (hspi->CRCSize == 0U)
03642   {
03643     SPI_CloseRx_ISR(hspi);
03644   }
03645 }
03646 #endif /* USE_SPI_CRC */
03647
03648 /**
03649   * @brief  Manage the receive 8-bit in Interrupt context.
03650   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03651   *               the configuration information for SPI module.
03652   * @retval None
03653   */
03654 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
03655 {
03656   *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR);
03657   hspi->pRxBuffPtr++;
03658   hspi->RxXferCount--;
03659
03660 #if (USE_SPI_CRC != 0U)
03661   /* Enable CRC Transmission */
03662   if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
03663   {
03664     SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
03665   }
03666 #endif /* USE_SPI_CRC */
03667
03668   if (hspi->RxXferCount == 0U)
03669   {
03670 #if (USE_SPI_CRC != 0U)
03671     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03672     {
03673       hspi->RxISR =  SPI_RxISR_8BITCRC;
03674       return;
03675     }
03676 #endif /* USE_SPI_CRC */
03677     SPI_CloseRx_ISR(hspi);
03678   }
03679 }
03680
03681 #if (USE_SPI_CRC != 0U)
03682 /**
03683   * @brief  Manage the CRC 16-bit receive in Interrupt context.
03684   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03685   *               the configuration information for SPI module.
03686   * @retval None
03687   */
03688 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
03689 {
03690   /* Read 16bit CRC to flush Data Register */
03691   READ_REG(hspi->Instance->DR);
03692
03693   /* Disable RXNE and ERR interrupt */
03694   __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
03695
03696   SPI_CloseRx_ISR(hspi);
03697 }
03698 #endif /* USE_SPI_CRC */
03699
03700 /**
03701   * @brief  Manage the 16-bit receive in Interrupt context.
03702   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03703   *               the configuration information for SPI module.
03704   * @retval None
03705   */
03706 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
03707 {
03708   *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
03709   hspi->pRxBuffPtr += sizeof(uint16_t);
03710   hspi->RxXferCount--;
03711
03712 #if (USE_SPI_CRC != 0U)
03713   /* Enable CRC Transmission */
03714   if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
03715   {
03716     SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
03717   }
03718 #endif /* USE_SPI_CRC */
03719
03720   if (hspi->RxXferCount == 0U)
03721   {
03722 #if (USE_SPI_CRC != 0U)
03723     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03724     {
03725       hspi->RxISR = SPI_RxISR_16BITCRC;
03726       return;
03727     }
03728 #endif /* USE_SPI_CRC */
03729     SPI_CloseRx_ISR(hspi);
03730   }
03731 }
03732
03733 /**
03734   * @brief  Handle the data 8-bit transmit in Interrupt mode.
03735   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03736   *               the configuration information for SPI module.
03737   * @retval None
03738   */
03739 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
03740 {
03741   *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
03742   hspi->pTxBuffPtr++;
03743   hspi->TxXferCount--;
03744
03745   if (hspi->TxXferCount == 0U)
03746   {
03747 #if (USE_SPI_CRC != 0U)
03748     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03749     {
03750       /* Enable CRC Transmission */
03751       SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
03752     }
03753 #endif /* USE_SPI_CRC */
03754     SPI_CloseTx_ISR(hspi);
03755   }
03756 }
03757
03758 /**
03759   * @brief  Handle the data 16-bit transmit in Interrupt mode.
03760   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03761   *               the configuration information for SPI module.
03762   * @retval None
03763   */
03764 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
03765 {
03766   /* Transmit data in 16 Bit mode */
03767   hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
03768   hspi->pTxBuffPtr += sizeof(uint16_t);
03769   hspi->TxXferCount--;
03770
03771   if (hspi->TxXferCount == 0U)
03772   {
03773 #if (USE_SPI_CRC != 0U)
03774     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03775     {
03776       /* Enable CRC Transmission */
03777       SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
03778     }
03779 #endif /* USE_SPI_CRC */
03780     SPI_CloseTx_ISR(hspi);
03781   }
03782 }
03783
03784 /**
03785   * @brief  Handle SPI Communication Timeout.
03786   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03787   *              the configuration information for SPI module.
03788   * @param  Flag SPI flag to check
03789   * @param  State flag state to check
03790   * @param  Timeout Timeout duration
03791   * @param  Tickstart tick start value
03792   * @retval HAL status
03793   */
03794 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
03795                                                        uint32_t Timeout, uint32_t Tickstart)
03796 {
03797   while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
03798   {
03799     if (Timeout != HAL_MAX_DELAY)
03800     {
03801       if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U))
03802       {
03803         /* Disable the SPI and reset the CRC: the CRC value should be cleared
03804         on both master and slave sides in order to resynchronize the master
03805         and slave for their respective CRC calculation */
03806
03807         /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
03808         __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
03809
03810         if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
03811                                                      || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
03812         {
03813           /* Disable SPI peripheral */
03814           __HAL_SPI_DISABLE(hspi);
03815         }
03816
03817         /* Reset CRC Calculation */
03818         if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03819         {
03820           SPI_RESET_CRC(hspi);
03821         }
03822
03823         hspi->State = HAL_SPI_STATE_READY;
03824
03825         /* Process Unlocked */
03826         __HAL_UNLOCK(hspi);
03827
03828         return HAL_TIMEOUT;
03829       }
03830     }
03831   }
03832
03833   return HAL_OK;
03834 }
03835
03836 /**
03837   * @brief  Handle SPI FIFO Communication Timeout.
03838   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03839   *              the configuration information for SPI module.
03840   * @param  Fifo Fifo to check
03841   * @param  State Fifo state to check
03842   * @param  Timeout Timeout duration
03843   * @param  Tickstart tick start value
03844   * @retval HAL status
03845   */
03846 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
03847                                                        uint32_t Timeout, uint32_t Tickstart)
03848 {
03849   while ((hspi->Instance->SR & Fifo) != State)
03850   {
03851     if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
03852     {
03853       /* Read 8bit CRC to flush Data Register */
03854       READ_REG(*((__IO uint8_t *)&hspi->Instance->DR));
03855     }
03856
03857     if (Timeout != HAL_MAX_DELAY)
03858     {
03859       if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U))
03860       {
03861         /* Disable the SPI and reset the CRC: the CRC value should be cleared
03862            on both master and slave sides in order to resynchronize the master
03863            and slave for their respective CRC calculation */
03864
03865         /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
03866         __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
03867
03868         if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
03869                                                      || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
03870         {
03871           /* Disable SPI peripheral */
03872           __HAL_SPI_DISABLE(hspi);
03873         }
03874
03875         /* Reset CRC Calculation */
03876         if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
03877         {
03878           SPI_RESET_CRC(hspi);
03879         }
03880
03881         hspi->State = HAL_SPI_STATE_READY;
03882
03883         /* Process Unlocked */
03884         __HAL_UNLOCK(hspi);
03885
03886         return HAL_TIMEOUT;
03887       }
03888     }
03889   }
03890
03891   return HAL_OK;
03892 }
03893
03894 /**
03895   * @brief  Handle the check of the RX transaction complete.
03896   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03897   *               the configuration information for SPI module.
03898   * @param  Timeout Timeout duration
03899   * @param  Tickstart tick start value
03900   * @retval HAL status
03901   */
03902 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi,  uint32_t Timeout, uint32_t Tickstart)
03903 {
03904   if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
03905                                                || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
03906   {
03907     /* Disable SPI peripheral */
03908     __HAL_SPI_DISABLE(hspi);
03909   }
03910
03911   /* Control the BSY flag */
03912   if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
03913   {
03914     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
03915     return HAL_TIMEOUT;
03916   }
03917
03918   if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
03919                                                || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
03920   {
03921     /* Empty the FRLVL fifo */
03922     if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
03923     {
03924       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
03925       return HAL_TIMEOUT;
03926     }
03927   }
03928   return HAL_OK;
03929 }
03930
03931 /**
03932   * @brief  Handle the check of the RXTX or TX transaction complete.
03933   * @param  hspi SPI handle
03934   * @param  Timeout Timeout duration
03935   * @param  Tickstart tick start value
03936   * @retval HAL status
03937   */
03938 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
03939 {
03940   /* Control if the TX fifo is empty */
03941   if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
03942   {
03943     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
03944     return HAL_TIMEOUT;
03945   }
03946
03947   /* Control the BSY flag */
03948   if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
03949   {
03950     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
03951     return HAL_TIMEOUT;
03952   }
03953
03954   /* Control if the RX fifo is empty */
03955   if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
03956   {
03957     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
03958     return HAL_TIMEOUT;
03959   }
03960
03961   return HAL_OK;
03962 }
03963
03964 /**
03965   * @brief  Handle the end of the RXTX transaction.
03966   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
03967   *               the configuration information for SPI module.
03968   * @retval None
03969   */
03970 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
03971 {
03972   uint32_t tickstart;
03973
03974   /* Init tickstart for timeout managment*/
03975   tickstart = HAL_GetTick();
03976
03977   /* Disable ERR interrupt */
03978   __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
03979
03980   /* Check the end of the transaction */
03981   if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
03982   {
03983     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
03984   }
03985
03986 #if (USE_SPI_CRC != 0U)
03987   /* Check if CRC error occurred */
03988   if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
03989   {
03990     hspi->State = HAL_SPI_STATE_READY;
03991     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
03992     __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
03993     /* Call user error callback */
03994 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
03995     hspi->ErrorCallback(hspi);
03996 #else
03997     HAL_SPI_ErrorCallback(hspi);
03998 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
03999   }
04000   else
04001   {
04002 #endif /* USE_SPI_CRC */
04003     if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
04004     {
04005       if (hspi->State == HAL_SPI_STATE_BUSY_RX)
04006       {
04007         hspi->State = HAL_SPI_STATE_READY;
04008         /* Call user Rx complete callback */
04009 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
04010         hspi->RxCpltCallback(hspi);
04011 #else
04012         HAL_SPI_RxCpltCallback(hspi);
04013 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
04014       }
04015       else
04016       {
04017         hspi->State = HAL_SPI_STATE_READY;
04018         /* Call user TxRx complete callback */
04019 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
04020         hspi->TxRxCpltCallback(hspi);
04021 #else
04022         HAL_SPI_TxRxCpltCallback(hspi);
04023 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
04024       }
04025     }
04026     else
04027     {
04028       hspi->State = HAL_SPI_STATE_READY;
04029       /* Call user error callback */
04030 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
04031       hspi->ErrorCallback(hspi);
04032 #else
04033       HAL_SPI_ErrorCallback(hspi);
04034 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
04035     }
04036 #if (USE_SPI_CRC != 0U)
04037   }
04038 #endif /* USE_SPI_CRC */
04039 }
04040
04041 /**
04042   * @brief  Handle the end of the RX transaction.
04043   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
04044   *               the configuration information for SPI module.
04045   * @retval None
04046   */
04047 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
04048 {
04049   /* Disable RXNE and ERR interrupt */
04050   __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
04051
04052   /* Check the end of the transaction */
04053   if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
04054   {
04055     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
04056   }
04057   hspi->State = HAL_SPI_STATE_READY;
04058
04059 #if (USE_SPI_CRC != 0U)
04060   /* Check if CRC error occurred */
04061   if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
04062   {
04063     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
04064     __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
04065     /* Call user error callback */
04066 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
04067     hspi->ErrorCallback(hspi);
04068 #else
04069     HAL_SPI_ErrorCallback(hspi);
04070 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
04071   }
04072   else
04073   {
04074 #endif /* USE_SPI_CRC */
04075     if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
04076     {
04077       /* Call user Rx complete callback */
04078 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
04079       hspi->RxCpltCallback(hspi);
04080 #else
04081       HAL_SPI_RxCpltCallback(hspi);
04082 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
04083     }
04084     else
04085     {
04086       /* Call user error callback */
04087 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
04088       hspi->ErrorCallback(hspi);
04089 #else
04090       HAL_SPI_ErrorCallback(hspi);
04091 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
04092     }
04093 #if (USE_SPI_CRC != 0U)
04094   }
04095 #endif /* USE_SPI_CRC */
04096 }
04097
04098 /**
04099   * @brief  Handle the end of the TX transaction.
04100   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
04101   *               the configuration information for SPI module.
04102   * @retval None
04103   */
04104 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
04105 {
04106   uint32_t tickstart;
04107
04108   /* Init tickstart for timeout management*/
04109   tickstart = HAL_GetTick();
04110
04111   /* Disable TXE and ERR interrupt */
04112   __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
04113
04114   /* Check the end of the transaction */
04115   if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
04116   {
04117     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
04118   }
04119
04120   /* Clear overrun flag in 2 Lines communication mode because received is not read */
04121   if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
04122   {
04123     __HAL_SPI_CLEAR_OVRFLAG(hspi);
04124   }
04125
04126   hspi->State = HAL_SPI_STATE_READY;
04127   if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
04128   {
04129     /* Call user error callback */
04130 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
04131     hspi->ErrorCallback(hspi);
04132 #else
04133     HAL_SPI_ErrorCallback(hspi);
04134 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
04135   }
04136   else
04137   {
04138     /* Call user Rx complete callback */
04139 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
04140     hspi->TxCpltCallback(hspi);
04141 #else
04142     HAL_SPI_TxCpltCallback(hspi);
04143 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
04144   }
04145 }
04146
04147 /**
04148   * @brief  Handle abort a Rx transaction.
04149   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
04150   *               the configuration information for SPI module.
04151   * @retval None
04152   */
04153 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
04154 {
04155   __IO uint32_t count;
04156
04157   /* Disable SPI Peripheral */
04158   __HAL_SPI_DISABLE(hspi);
04159
04160   count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
04161
04162   /* Disable RXNEIE interrupt */
04163   CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
04164
04165   /* Check RXNEIE is disabled */
04166   do
04167   {
04168     if (count == 0U)
04169     {
04170       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
04171       break;
04172     }
04173     count--;
04174   } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
04175
04176   /* Control the BSY flag */
04177   if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
04178   {
04179     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
04180   }
04181
04182   /* Empty the FRLVL fifo */
04183   if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
04184   {
04185     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
04186   }
04187
04188   hspi->State = HAL_SPI_STATE_ABORT;
04189 }
04190
04191 /**
04192   * @brief  Handle abort a Tx or Rx/Tx transaction.
04193   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
04194   *               the configuration information for SPI module.
04195   * @retval None
04196   */
04197 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
04198 {
04199   __IO uint32_t count;
04200
04201   count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
04202
04203   /* Disable TXEIE interrupt */
04204   CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));
04205
04206   /* Check TXEIE is disabled */
04207   do
04208   {
04209     if (count == 0U)
04210     {
04211       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
04212       break;
04213     }
04214     count--;
04215   } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
04216
04217   if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
04218   {
04219     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
04220   }
04221
04222   /* Disable SPI Peripheral */
04223   __HAL_SPI_DISABLE(hspi);
04224
04225   /* Empty the FRLVL fifo */
04226   if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
04227   {
04228     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
04229   }
04230
04231   /* Check case of Full-Duplex Mode and disable directly RXNEIE interrupt */
04232   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
04233   {
04234     /* Disable RXNEIE interrupt */
04235     CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
04236
04237     /* Check RXNEIE is disabled */
04238     do
04239     {
04240       if (count == 0U)
04241       {
04242         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
04243         break;
04244       }
04245       count--;
04246     } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
04247
04248     /* Control the BSY flag */
04249     if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
04250     {
04251       hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
04252     }
04253
04254     /* Empty the FRLVL fifo */
04255     if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
04256     {
04257       hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
04258     }
04259   }
04260   hspi->State = HAL_SPI_STATE_ABORT;
04261 }
04262
04263 /**
04264   * @}
04265   */
04266
04267 #endif /* HAL_SPI_MODULE_ENABLED */
04268
04269 /**
04270   * @}
04271   */
04272
04273 /**
04274   * @}
04275   */
04276
04277 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:35 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_spi.h Source File

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stm32wbxx_hal_spi.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_spi.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SPI HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_SPI_H
00022 #define STM32WBxx_HAL_SPI_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 /** @addtogroup STM32WBxx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup SPI
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup SPI_Exported_Types SPI Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief  SPI Configuration Structure definition
00046   */
00047 typedef struct
00048 {
00049   uint32_t Mode;                /*!< Specifies the SPI operating mode.
00050                                      This parameter can be a value of @ref SPI_Mode */
00051
00052   uint32_t Direction;           /*!< Specifies the SPI bidirectional mode state.
00053                                      This parameter can be a value of @ref SPI_Direction */
00054
00055   uint32_t DataSize;            /*!< Specifies the SPI data size.
00056                                      This parameter can be a value of @ref SPI_Data_Size */
00057
00058   uint32_t CLKPolarity;         /*!< Specifies the serial clock steady state.
00059                                      This parameter can be a value of @ref SPI_Clock_Polarity */
00060
00061   uint32_t CLKPhase;            /*!< Specifies the clock active edge for the bit capture.
00062                                      This parameter can be a value of @ref SPI_Clock_Phase */
00063
00064   uint32_t NSS;                 /*!< Specifies whether the NSS signal is managed by
00065                                      hardware (NSS pin) or by software using the SSI bit.
00066                                      This parameter can be a value of @ref SPI_Slave_Select_management */
00067
00068   uint32_t BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be
00069                                      used to configure the transmit and receive SCK clock.
00070                                      This parameter can be a value of @ref SPI_BaudRate_Prescaler
00071                                      @note The communication clock is derived from the master
00072                                      clock. The slave clock does not need to be set. */
00073
00074   uint32_t FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.
00075                                      This parameter can be a value of @ref SPI_MSB_LSB_transmission */
00076
00077   uint32_t TIMode;              /*!< Specifies if the TI mode is enabled or not.
00078                                      This parameter can be a value of @ref SPI_TI_mode */
00079
00080   uint32_t CRCCalculation;      /*!< Specifies if the CRC calculation is enabled or not.
00081                                      This parameter can be a value of @ref SPI_CRC_Calculation */
00082
00083   uint32_t CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation.
00084                                      This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */
00085
00086   uint32_t CRCLength;           /*!< Specifies the CRC Length used for the CRC calculation.
00087                                      CRC Length is only used with Data8 and Data16, not other data size
00088                                      This parameter can be a value of @ref SPI_CRC_length */
00089
00090   uint32_t NSSPMode;            /*!< Specifies whether the NSSP signal is enabled or not .
00091                                      This parameter can be a value of @ref SPI_NSSP_Mode
00092                                      This mode is activated by the NSSP bit in the SPIx_CR2 register and
00093                                      it takes effect only if the SPI interface is configured as Motorola SPI
00094                                      master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
00095                                      CPOL setting is ignored).. */
00096 } SPI_InitTypeDef;
00097
00098 /**
00099   * @brief  HAL SPI State structure definition
00100   */
00101 typedef enum
00102 {
00103   HAL_SPI_STATE_RESET      = 0x00U,    /*!< Peripheral not Initialized                         */
00104   HAL_SPI_STATE_READY      = 0x01U,    /*!< Peripheral Initialized and ready for use           */
00105   HAL_SPI_STATE_BUSY       = 0x02U,    /*!< an internal process is ongoing                     */
00106   HAL_SPI_STATE_BUSY_TX    = 0x03U,    /*!< Data Transmission process is ongoing               */
00107   HAL_SPI_STATE_BUSY_RX    = 0x04U,    /*!< Data Reception process is ongoing                  */
00108   HAL_SPI_STATE_BUSY_TX_RX = 0x05U,    /*!< Data Transmission and Reception process is ongoing */
00109   HAL_SPI_STATE_ERROR      = 0x06U,    /*!< SPI error state                                    */
00110   HAL_SPI_STATE_ABORT      = 0x07U     /*!< SPI abort is ongoing                               */
00111 } HAL_SPI_StateTypeDef;
00112
00113 /**
00114   * @brief  SPI handle Structure definition
00115   */
00116 typedef struct __SPI_HandleTypeDef
00117 {
00118   SPI_TypeDef                *Instance;      /*!< SPI registers base address               */
00119
00120   SPI_InitTypeDef            Init;           /*!< SPI communication parameters             */
00121
00122   uint8_t                    *pTxBuffPtr;    /*!< Pointer to SPI Tx transfer Buffer        */
00123
00124   uint16_t                   TxXferSize;     /*!< SPI Tx Transfer size                     */
00125
00126   __IO uint16_t              TxXferCount;    /*!< SPI Tx Transfer Counter                  */
00127
00128   uint8_t                    *pRxBuffPtr;    /*!< Pointer to SPI Rx transfer Buffer        */
00129
00130   uint16_t                   RxXferSize;     /*!< SPI Rx Transfer size                     */
00131
00132   __IO uint16_t              RxXferCount;    /*!< SPI Rx Transfer Counter                  */
00133
00134   uint32_t                   CRCSize;        /*!< SPI CRC size used for the transfer       */
00135
00136   void (*RxISR)(struct __SPI_HandleTypeDef *hspi);   /*!< function pointer on Rx ISR       */
00137
00138   void (*TxISR)(struct __SPI_HandleTypeDef *hspi);   /*!< function pointer on Tx ISR       */
00139
00140   DMA_HandleTypeDef          *hdmatx;        /*!< SPI Tx DMA Handle parameters             */
00141
00142   DMA_HandleTypeDef          *hdmarx;        /*!< SPI Rx DMA Handle parameters             */
00143
00144   HAL_LockTypeDef            Lock;           /*!< Locking object                           */
00145
00146   __IO HAL_SPI_StateTypeDef  State;          /*!< SPI communication state                  */
00147
00148   __IO uint32_t              ErrorCode;      /*!< SPI Error code                           */
00149
00150 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
00151   void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi);             /*!< SPI Tx Completed callback          */
00152   void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi);             /*!< SPI Rx Completed callback          */
00153   void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi);           /*!< SPI TxRx Completed callback        */
00154   void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);         /*!< SPI Tx Half Completed callback     */
00155   void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);         /*!< SPI Rx Half Completed callback     */
00156   void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);       /*!< SPI TxRx Half Completed callback   */
00157   void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi);              /*!< SPI Error callback                 */
00158   void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi);          /*!< SPI Abort callback                 */
00159   void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi);            /*!< SPI Msp Init callback              */
00160   void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi);          /*!< SPI Msp DeInit callback            */
00161
00162 #endif  /* USE_HAL_SPI_REGISTER_CALLBACKS */
00163 } SPI_HandleTypeDef;
00164
00165 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
00166 /**
00167   * @brief  HAL SPI Callback ID enumeration definition
00168   */
00169 typedef enum
00170 {
00171   HAL_SPI_TX_COMPLETE_CB_ID             = 0x00U,    /*!< SPI Tx Completed callback ID         */
00172   HAL_SPI_RX_COMPLETE_CB_ID             = 0x01U,    /*!< SPI Rx Completed callback ID         */
00173   HAL_SPI_TX_RX_COMPLETE_CB_ID          = 0x02U,    /*!< SPI TxRx Completed callback ID       */
00174   HAL_SPI_TX_HALF_COMPLETE_CB_ID        = 0x03U,    /*!< SPI Tx Half Completed callback ID    */
00175   HAL_SPI_RX_HALF_COMPLETE_CB_ID        = 0x04U,    /*!< SPI Rx Half Completed callback ID    */
00176   HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID     = 0x05U,    /*!< SPI TxRx Half Completed callback ID  */
00177   HAL_SPI_ERROR_CB_ID                   = 0x06U,    /*!< SPI Error callback ID                */
00178   HAL_SPI_ABORT_CB_ID                   = 0x07U,    /*!< SPI Abort callback ID                */
00179   HAL_SPI_MSPINIT_CB_ID                 = 0x08U,    /*!< SPI Msp Init callback ID             */
00180   HAL_SPI_MSPDEINIT_CB_ID               = 0x09U     /*!< SPI Msp DeInit callback ID           */
00181
00182 } HAL_SPI_CallbackIDTypeDef;
00183
00184 /**
00185   * @brief  HAL SPI Callback pointer definition
00186   */
00187 typedef  void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */
00188
00189 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
00190 /**
00191   * @}
00192   */
00193
00194 /* Exported constants --------------------------------------------------------*/
00195 /** @defgroup SPI_Exported_Constants SPI Exported Constants
00196   * @{
00197   */
00198
00199 /** @defgroup SPI_Error_Code SPI Error Code
00200   * @{
00201   */
00202 #define HAL_SPI_ERROR_NONE              (0x00000000U)   /*!< No error                               */
00203 #define HAL_SPI_ERROR_MODF              (0x00000001U)   /*!< MODF error                             */
00204 #define HAL_SPI_ERROR_CRC               (0x00000002U)   /*!< CRC error                              */
00205 #define HAL_SPI_ERROR_OVR               (0x00000004U)   /*!< OVR error                              */
00206 #define HAL_SPI_ERROR_FRE               (0x00000008U)   /*!< FRE error                              */
00207 #define HAL_SPI_ERROR_DMA               (0x00000010U)   /*!< DMA transfer error                     */
00208 #define HAL_SPI_ERROR_FLAG              (0x00000020U)   /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */
00209 #define HAL_SPI_ERROR_ABORT             (0x00000040U)   /*!< Error during SPI Abort procedure       */
00210 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
00211 #define HAL_SPI_ERROR_INVALID_CALLBACK  (0x00000080U)   /*!< Invalid Callback error                 */
00212 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
00213 /**
00214   * @}
00215   */
00216
00217 /** @defgroup SPI_Mode SPI Mode
00218   * @{
00219   */
00220 #define SPI_MODE_SLAVE                  (0x00000000U)
00221 #define SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)
00222 /**
00223   * @}
00224   */
00225
00226 /** @defgroup SPI_Direction SPI Direction Mode
00227   * @{
00228   */
00229 #define SPI_DIRECTION_2LINES            (0x00000000U)
00230 #define SPI_DIRECTION_2LINES_RXONLY     SPI_CR1_RXONLY
00231 #define SPI_DIRECTION_1LINE             SPI_CR1_BIDIMODE
00232 /**
00233   * @}
00234   */
00235
00236 /** @defgroup SPI_Data_Size SPI Data Size
00237   * @{
00238   */
00239 #define SPI_DATASIZE_4BIT               (0x00000300U)
00240 #define SPI_DATASIZE_5BIT               (0x00000400U)
00241 #define SPI_DATASIZE_6BIT               (0x00000500U)
00242 #define SPI_DATASIZE_7BIT               (0x00000600U)
00243 #define SPI_DATASIZE_8BIT               (0x00000700U)
00244 #define SPI_DATASIZE_9BIT               (0x00000800U)
00245 #define SPI_DATASIZE_10BIT              (0x00000900U)
00246 #define SPI_DATASIZE_11BIT              (0x00000A00U)
00247 #define SPI_DATASIZE_12BIT              (0x00000B00U)
00248 #define SPI_DATASIZE_13BIT              (0x00000C00U)
00249 #define SPI_DATASIZE_14BIT              (0x00000D00U)
00250 #define SPI_DATASIZE_15BIT              (0x00000E00U)
00251 #define SPI_DATASIZE_16BIT              (0x00000F00U)
00252 /**
00253   * @}
00254   */
00255
00256 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity
00257   * @{
00258   */
00259 #define SPI_POLARITY_LOW                (0x00000000U)
00260 #define SPI_POLARITY_HIGH               SPI_CR1_CPOL
00261 /**
00262   * @}
00263   */
00264
00265 /** @defgroup SPI_Clock_Phase SPI Clock Phase
00266   * @{
00267   */
00268 #define SPI_PHASE_1EDGE                 (0x00000000U)
00269 #define SPI_PHASE_2EDGE                 SPI_CR1_CPHA
00270 /**
00271   * @}
00272   */
00273
00274 /** @defgroup SPI_Slave_Select_management SPI Slave Select Management
00275   * @{
00276   */
00277 #define SPI_NSS_SOFT                    SPI_CR1_SSM
00278 #define SPI_NSS_HARD_INPUT              (0x00000000U)
00279 #define SPI_NSS_HARD_OUTPUT             (SPI_CR2_SSOE << 16U)
00280 /**
00281   * @}
00282   */
00283
00284 /** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
00285   * @{
00286   */
00287 #define SPI_NSS_PULSE_ENABLE            SPI_CR2_NSSP
00288 #define SPI_NSS_PULSE_DISABLE           (0x00000000U)
00289 /**
00290   * @}
00291   */
00292
00293 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
00294   * @{
00295   */
00296 #define SPI_BAUDRATEPRESCALER_2         (0x00000000U)
00297 #define SPI_BAUDRATEPRESCALER_4         (SPI_CR1_BR_0)
00298 #define SPI_BAUDRATEPRESCALER_8         (SPI_CR1_BR_1)
00299 #define SPI_BAUDRATEPRESCALER_16        (SPI_CR1_BR_1 | SPI_CR1_BR_0)
00300 #define SPI_BAUDRATEPRESCALER_32        (SPI_CR1_BR_2)
00301 #define SPI_BAUDRATEPRESCALER_64        (SPI_CR1_BR_2 | SPI_CR1_BR_0)
00302 #define SPI_BAUDRATEPRESCALER_128       (SPI_CR1_BR_2 | SPI_CR1_BR_1)
00303 #define SPI_BAUDRATEPRESCALER_256       (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
00304 /**
00305   * @}
00306   */
00307
00308 /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
00309   * @{
00310   */
00311 #define SPI_FIRSTBIT_MSB                (0x00000000U)
00312 #define SPI_FIRSTBIT_LSB                SPI_CR1_LSBFIRST
00313 /**
00314   * @}
00315   */
00316
00317 /** @defgroup SPI_TI_mode SPI TI Mode
00318   * @{
00319   */
00320 #define SPI_TIMODE_DISABLE              (0x00000000U)
00321 #define SPI_TIMODE_ENABLE               SPI_CR2_FRF
00322 /**
00323   * @}
00324   */
00325
00326 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation
00327   * @{
00328   */
00329 #define SPI_CRCCALCULATION_DISABLE      (0x00000000U)
00330 #define SPI_CRCCALCULATION_ENABLE       SPI_CR1_CRCEN
00331 /**
00332   * @}
00333   */
00334
00335 /** @defgroup SPI_CRC_length SPI CRC Length
00336   * @{
00337   * This parameter can be one of the following values:
00338   *     SPI_CRC_LENGTH_DATASIZE: aligned with the data size
00339   *     SPI_CRC_LENGTH_8BIT    : CRC 8bit
00340   *     SPI_CRC_LENGTH_16BIT   : CRC 16bit
00341   */
00342 #define SPI_CRC_LENGTH_DATASIZE         (0x00000000U)
00343 #define SPI_CRC_LENGTH_8BIT             (0x00000001U)
00344 #define SPI_CRC_LENGTH_16BIT            (0x00000002U)
00345 /**
00346   * @}
00347   */
00348
00349 /** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold
00350   * @{
00351   * This parameter can be one of the following values:
00352   *     SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :
00353   *          RXNE event is generated if the FIFO
00354   *          level is greater or equal to 1/4(8-bits).
00355   *     SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
00356   *          level is greater or equal to 1/2(16 bits). */
00357 #define SPI_RXFIFO_THRESHOLD            SPI_CR2_FRXTH
00358 #define SPI_RXFIFO_THRESHOLD_QF         SPI_CR2_FRXTH
00359 #define SPI_RXFIFO_THRESHOLD_HF         (0x00000000U)
00360 /**
00361   * @}
00362   */
00363
00364 /** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
00365   * @{
00366   */
00367 #define SPI_IT_TXE                      SPI_CR2_TXEIE
00368 #define SPI_IT_RXNE                     SPI_CR2_RXNEIE
00369 #define SPI_IT_ERR                      SPI_CR2_ERRIE
00370 /**
00371   * @}
00372   */
00373
00374 /** @defgroup SPI_Flags_definition SPI Flags Definition
00375   * @{
00376   */
00377 #define SPI_FLAG_RXNE                   SPI_SR_RXNE   /* SPI status flag: Rx buffer not empty flag       */
00378 #define SPI_FLAG_TXE                    SPI_SR_TXE    /* SPI status flag: Tx buffer empty flag           */
00379 #define SPI_FLAG_BSY                    SPI_SR_BSY    /* SPI status flag: Busy flag                      */
00380 #define SPI_FLAG_CRCERR                 SPI_SR_CRCERR /* SPI Error flag: CRC error flag                  */
00381 #define SPI_FLAG_MODF                   SPI_SR_MODF   /* SPI Error flag: Mode fault flag                 */
00382 #define SPI_FLAG_OVR                    SPI_SR_OVR    /* SPI Error flag: Overrun flag                    */
00383 #define SPI_FLAG_FRE                    SPI_SR_FRE    /* SPI Error flag: TI mode frame format error flag */
00384 #define SPI_FLAG_FTLVL                  SPI_SR_FTLVL  /* SPI fifo transmission level                     */
00385 #define SPI_FLAG_FRLVL                  SPI_SR_FRLVL  /* SPI fifo reception level                        */
00386 #define SPI_FLAG_MASK                   (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR\
00387                                          | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_FTLVL | SPI_SR_FRLVL)
00388 /**
00389   * @}
00390   */
00391
00392 /** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level
00393   * @{
00394   */
00395 #define SPI_FTLVL_EMPTY                 (0x00000000U)
00396 #define SPI_FTLVL_QUARTER_FULL          (0x00000800U)
00397 #define SPI_FTLVL_HALF_FULL             (0x00001000U)
00398 #define SPI_FTLVL_FULL                  (0x00001800U)
00399
00400 /**
00401   * @}
00402   */
00403
00404 /** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
00405   * @{
00406   */
00407 #define SPI_FRLVL_EMPTY                 (0x00000000U)
00408 #define SPI_FRLVL_QUARTER_FULL          (0x00000200U)
00409 #define SPI_FRLVL_HALF_FULL             (0x00000400U)
00410 #define SPI_FRLVL_FULL                  (0x00000600U)
00411 /**
00412   * @}
00413   */
00414
00415 /**
00416   * @}
00417   */
00418
00419 /* Exported macros -----------------------------------------------------------*/
00420 /** @defgroup SPI_Exported_Macros SPI Exported Macros
00421   * @{
00422   */
00423
00424 /** @brief  Reset SPI handle state.
00425   * @param  __HANDLE__ specifies the SPI Handle.
00426   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00427   * @retval None
00428   */
00429 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
00430 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__)                do{                                                  \
00431                                                                     (__HANDLE__)->State = HAL_SPI_STATE_RESET;       \
00432                                                                     (__HANDLE__)->MspInitCallback = NULL;            \
00433                                                                     (__HANDLE__)->MspDeInitCallback = NULL;          \
00434                                                                   } while(0)
00435 #else
00436 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
00437 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
00438
00439 /** @brief  Enable the specified SPI interrupts.
00440   * @param  __HANDLE__ specifies the SPI Handle.
00441   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00442   * @param  __INTERRUPT__ specifies the interrupt source to enable.
00443   *         This parameter can be one of the following values:
00444   *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
00445   *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
00446   *            @arg SPI_IT_ERR: Error interrupt enable
00447   * @retval None
00448   */
00449 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
00450
00451 /** @brief  Disable the specified SPI interrupts.
00452   * @param  __HANDLE__ specifies the SPI handle.
00453   *         This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
00454   * @param  __INTERRUPT__ specifies the interrupt source to disable.
00455   *         This parameter can be one of the following values:
00456   *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
00457   *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
00458   *            @arg SPI_IT_ERR: Error interrupt enable
00459   * @retval None
00460   */
00461 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
00462
00463 /** @brief  Check whether the specified SPI interrupt source is enabled or not.
00464   * @param  __HANDLE__ specifies the SPI Handle.
00465   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00466   * @param  __INTERRUPT__ specifies the SPI interrupt source to check.
00467   *          This parameter can be one of the following values:
00468   *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
00469   *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
00470   *            @arg SPI_IT_ERR: Error interrupt enable
00471   * @retval The new state of __IT__ (TRUE or FALSE).
00472   */
00473 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
00474                                                               & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00475
00476 /** @brief  Check whether the specified SPI flag is set or not.
00477   * @param  __HANDLE__ specifies the SPI Handle.
00478   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00479   * @param  __FLAG__ specifies the flag to check.
00480   *         This parameter can be one of the following values:
00481   *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag
00482   *            @arg SPI_FLAG_TXE: Transmit buffer empty flag
00483   *            @arg SPI_FLAG_CRCERR: CRC error flag
00484   *            @arg SPI_FLAG_MODF: Mode fault flag
00485   *            @arg SPI_FLAG_OVR: Overrun flag
00486   *            @arg SPI_FLAG_BSY: Busy flag
00487   *            @arg SPI_FLAG_FRE: Frame format error flag
00488   *            @arg SPI_FLAG_FTLVL: SPI fifo transmission level
00489   *            @arg SPI_FLAG_FRLVL: SPI fifo reception level
00490   * @retval The new state of __FLAG__ (TRUE or FALSE).
00491   */
00492 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00493
00494 /** @brief  Clear the SPI CRCERR pending flag.
00495   * @param  __HANDLE__ specifies the SPI Handle.
00496   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00497   * @retval None
00498   */
00499 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
00500
00501 /** @brief  Clear the SPI MODF pending flag.
00502   * @param  __HANDLE__ specifies the SPI Handle.
00503   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00504   * @retval None
00505   */
00506 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)             \
00507   do{                                                    \
00508     __IO uint32_t tmpreg_modf = 0x00U;                   \
00509     tmpreg_modf = (__HANDLE__)->Instance->SR;            \
00510     CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
00511     UNUSED(tmpreg_modf);                                 \
00512   } while(0U)
00513
00514 /** @brief  Clear the SPI OVR pending flag.
00515   * @param  __HANDLE__ specifies the SPI Handle.
00516   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00517   * @retval None
00518   */
00519 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)        \
00520   do{                                              \
00521     __IO uint32_t tmpreg_ovr = 0x00U;              \
00522     tmpreg_ovr = (__HANDLE__)->Instance->DR;       \
00523     tmpreg_ovr = (__HANDLE__)->Instance->SR;       \
00524     UNUSED(tmpreg_ovr);                            \
00525   } while(0U)
00526
00527 /** @brief  Clear the SPI FRE pending flag.
00528   * @param  __HANDLE__ specifies the SPI Handle.
00529   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00530   * @retval None
00531   */
00532 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)        \
00533   do{                                              \
00534     __IO uint32_t tmpreg_fre = 0x00U;              \
00535     tmpreg_fre = (__HANDLE__)->Instance->SR;       \
00536     UNUSED(tmpreg_fre);                            \
00537   }while(0U)
00538
00539 /** @brief  Enable the SPI peripheral.
00540   * @param  __HANDLE__ specifies the SPI Handle.
00541   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00542   * @retval None
00543   */
00544 #define __HAL_SPI_ENABLE(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
00545
00546 /** @brief  Disable the SPI peripheral.
00547   * @param  __HANDLE__ specifies the SPI Handle.
00548   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00549   * @retval None
00550   */
00551 #define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
00552
00553 /**
00554   * @}
00555   */
00556
00557 /* Private macros ------------------------------------------------------------*/
00558 /** @defgroup SPI_Private_Macros SPI Private Macros
00559   * @{
00560   */
00561
00562 /** @brief  Set the SPI transmit-only mode.
00563   * @param  __HANDLE__ specifies the SPI Handle.
00564   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00565   * @retval None
00566   */
00567 #define SPI_1LINE_TX(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
00568
00569 /** @brief  Set the SPI receive-only mode.
00570   * @param  __HANDLE__ specifies the SPI Handle.
00571   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00572   * @retval None
00573   */
00574 #define SPI_1LINE_RX(__HANDLE__)  CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
00575
00576 /** @brief  Reset the CRC calculation of the SPI.
00577   * @param  __HANDLE__ specifies the SPI Handle.
00578   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00579   * @retval None
00580   */
00581 #define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
00582                                        SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
00583
00584 /** @brief  Check whether the specified SPI flag is set or not.
00585   * @param  __SR__  copy of SPI SR regsiter.
00586   * @param  __FLAG__ specifies the flag to check.
00587   *         This parameter can be one of the following values:
00588   *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag
00589   *            @arg SPI_FLAG_TXE: Transmit buffer empty flag
00590   *            @arg SPI_FLAG_CRCERR: CRC error flag
00591   *            @arg SPI_FLAG_MODF: Mode fault flag
00592   *            @arg SPI_FLAG_OVR: Overrun flag
00593   *            @arg SPI_FLAG_BSY: Busy flag
00594   *            @arg SPI_FLAG_FRE: Frame format error flag
00595   *            @arg SPI_FLAG_FTLVL: SPI fifo transmission level
00596   *            @arg SPI_FLAG_FRLVL: SPI fifo reception level
00597   * @retval SET or RESET.
00598   */
00599 #define SPI_CHECK_FLAG(__SR__, __FLAG__)         ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
00600
00601 /** @brief  Check whether the specified SPI Interrupt is set or not.
00602   * @param  __CR2__  copy of SPI CR2 regsiter.
00603   * @param  __INTERRUPT__ specifies the SPI interrupt source to check.
00604   *         This parameter can be one of the following values:
00605   *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
00606   *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
00607   *            @arg SPI_IT_ERR: Error interrupt enable
00608   * @retval SET or RESET.
00609   */
00610 #define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__)      ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00611
00612 /** @brief  Checks if SPI Mode parameter is in allowed range.
00613   * @param  __MODE__ specifies the SPI Mode.
00614   *         This parameter can be a value of @ref SPI_Mode
00615   * @retval None
00616   */
00617 #define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \
00618                                ((__MODE__) == SPI_MODE_MASTER))
00619
00620 /** @brief  Checks if SPI Direction Mode parameter is in allowed range.
00621   * @param  __MODE__ specifies the SPI Direction Mode.
00622   *         This parameter can be a value of @ref SPI_Direction
00623   * @retval None
00624   */
00625 #define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES)        || \
00626                                     ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \
00627                                     ((__MODE__) == SPI_DIRECTION_1LINE))
00628
00629 /** @brief  Checks if SPI Direction Mode parameter is 2 lines.
00630   * @param  __MODE__ specifies the SPI Direction Mode.
00631   * @retval None
00632   */
00633 #define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)
00634
00635 /** @brief  Checks if SPI Direction Mode parameter is 1 or 2 lines.
00636   * @param  __MODE__ specifies the SPI Direction Mode.
00637   * @retval None
00638   */
00639 #define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
00640                                                     ((__MODE__) == SPI_DIRECTION_1LINE))
00641
00642 /** @brief  Checks if SPI Data Size parameter is in allowed range.
00643   * @param  __DATASIZE__ specifies the SPI Data Size.
00644   *         This parameter can be a value of @ref SPI_Data_Size
00645   * @retval None
00646   */
00647 #define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \
00648                                        ((__DATASIZE__) == SPI_DATASIZE_15BIT) || \
00649                                        ((__DATASIZE__) == SPI_DATASIZE_14BIT) || \
00650                                        ((__DATASIZE__) == SPI_DATASIZE_13BIT) || \
00651                                        ((__DATASIZE__) == SPI_DATASIZE_12BIT) || \
00652                                        ((__DATASIZE__) == SPI_DATASIZE_11BIT) || \
00653                                        ((__DATASIZE__) == SPI_DATASIZE_10BIT) || \
00654                                        ((__DATASIZE__) == SPI_DATASIZE_9BIT)  || \
00655                                        ((__DATASIZE__) == SPI_DATASIZE_8BIT)  || \
00656                                        ((__DATASIZE__) == SPI_DATASIZE_7BIT)  || \
00657                                        ((__DATASIZE__) == SPI_DATASIZE_6BIT)  || \
00658                                        ((__DATASIZE__) == SPI_DATASIZE_5BIT)  || \
00659                                        ((__DATASIZE__) == SPI_DATASIZE_4BIT))
00660
00661 /** @brief  Checks if SPI Serial clock steady state parameter is in allowed range.
00662   * @param  __CPOL__ specifies the SPI serial clock steady state.
00663   *         This parameter can be a value of @ref SPI_Clock_Polarity
00664   * @retval None
00665   */
00666 #define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \
00667                                ((__CPOL__) == SPI_POLARITY_HIGH))
00668
00669 /** @brief  Checks if SPI Clock Phase parameter is in allowed range.
00670   * @param  __CPHA__ specifies the SPI Clock Phase.
00671   *         This parameter can be a value of @ref SPI_Clock_Phase
00672   * @retval None
00673   */
00674 #define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \
00675                                ((__CPHA__) == SPI_PHASE_2EDGE))
00676
00677 /** @brief  Checks if SPI Slave Select parameter is in allowed range.
00678   * @param  __NSS__ specifies the SPI Slave Select management parameter.
00679   *         This parameter can be a value of @ref SPI_Slave_Select_management
00680   * @retval None
00681   */
00682 #define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT)       || \
00683                              ((__NSS__) == SPI_NSS_HARD_INPUT) || \
00684                              ((__NSS__) == SPI_NSS_HARD_OUTPUT))
00685
00686 /** @brief  Checks if SPI NSS Pulse parameter is in allowed range.
00687   * @param  __NSSP__ specifies the SPI NSS Pulse Mode parameter.
00688   *         This parameter can be a value of @ref SPI_NSSP_Mode
00689   * @retval None
00690   */
00691 #define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \
00692                                ((__NSSP__) == SPI_NSS_PULSE_DISABLE))
00693
00694 /** @brief  Checks if SPI Baudrate prescaler parameter is in allowed range.
00695   * @param  __PRESCALER__ specifies the SPI Baudrate prescaler.
00696   *         This parameter can be a value of @ref SPI_BaudRate_Prescaler
00697   * @retval None
00698   */
00699 #define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2)   || \
00700                                                   ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4)   || \
00701                                                   ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8)   || \
00702                                                   ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16)  || \
00703                                                   ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32)  || \
00704                                                   ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64)  || \
00705                                                   ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \
00706                                                   ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))
00707
00708 /** @brief  Checks if SPI MSB LSB transmission parameter is in allowed range.
00709   * @param  __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit).
00710   *         This parameter can be a value of @ref SPI_MSB_LSB_transmission
00711   * @retval None
00712   */
00713 #define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \
00714                                    ((__BIT__) == SPI_FIRSTBIT_LSB))
00715
00716 /** @brief  Checks if SPI TI mode parameter is in allowed range.
00717   * @param  __MODE__ specifies the SPI TI mode.
00718   *         This parameter can be a value of @ref SPI_TI_mode
00719   * @retval None
00720   */
00721 #define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \
00722                                  ((__MODE__) == SPI_TIMODE_ENABLE))
00723
00724 /** @brief  Checks if SPI CRC calculation enabled state is in allowed range.
00725   * @param  __CALCULATION__ specifies the SPI CRC calculation enable state.
00726   *         This parameter can be a value of @ref SPI_CRC_Calculation
00727   * @retval None
00728   */
00729 #define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \
00730                                                  ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))
00731
00732 /** @brief  Checks if SPI CRC length is in allowed range.
00733   * @param  __LENGTH__ specifies the SPI CRC length.
00734   *         This parameter can be a value of @ref SPI_CRC_length
00735   * @retval None
00736   */
00737 #define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) ||\
00738                                        ((__LENGTH__) == SPI_CRC_LENGTH_8BIT)  ||   \
00739                                        ((__LENGTH__) == SPI_CRC_LENGTH_16BIT))
00740
00741 /** @brief  Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
00742   * @param  __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation.
00743   *         This parameter must be a number between Min_Data = 0 and Max_Data = 65535
00744   * @retval None
00745   */
00746 #define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU) && (((__POLYNOMIAL__)&0x1U) != 0U))
00747
00748 /** @brief  Checks if DMA handle is valid.
00749   * @param  __HANDLE__ specifies a DMA Handle.
00750   * @retval None
00751   */
00752 #define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL)
00753
00754 /**
00755   * @}
00756   */
00757
00758 /* Include SPI HAL Extended module */
00759 #include "stm32wbxx_hal_spi_ex.h"
00760
00761 /* Exported functions --------------------------------------------------------*/
00762 /** @addtogroup SPI_Exported_Functions
00763   * @{
00764   */
00765
00766 /** @addtogroup SPI_Exported_Functions_Group1
00767   * @{
00768   */
00769 /* Initialization/de-initialization functions  ********************************/
00770 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
00771 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
00772 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
00773 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
00774
00775 /* Callbacks Register/UnRegister functions  ***********************************/
00776 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
00777 HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback);
00778 HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
00779 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
00780 /**
00781   * @}
00782   */
00783
00784 /** @addtogroup SPI_Exported_Functions_Group2
00785   * @{
00786   */
00787 /* I/O operation functions  ***************************************************/
00788 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00789 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00790 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
00791                                           uint32_t Timeout);
00792 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00793 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00794 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
00795                                              uint16_t Size);
00796 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00797 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00798 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
00799                                               uint16_t Size);
00800 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
00801 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
00802 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
00803 /* Transfer Abort functions */
00804 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
00805 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
00806
00807 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
00808 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
00809 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
00810 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
00811 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
00812 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
00813 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
00814 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
00815 void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
00816 /**
00817   * @}
00818   */
00819
00820 /** @addtogroup SPI_Exported_Functions_Group3
00821   * @{
00822   */
00823 /* Peripheral State and Error functions ***************************************/
00824 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
00825 uint32_t             HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
00826 /**
00827   * @}
00828   */
00829
00830 /**
00831   * @}
00832   */
00833
00834 /**
00835   * @}
00836   */
00837
00838 /**
00839   * @}
00840   */
00841
00842 #ifdef __cplusplus
00843 }
00844 #endif
00845
00846 #endif /* STM32WBxx_HAL_SPI_H */
00847
00848 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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STM32WB55xx HAL User Manual: stm32wbxx_hal_spi_ex.c Source File

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stm32wbxx_hal_spi_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_spi_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended SPI HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          SPI peripheral extended functionalities :
00008   *           + IO operation functions
00009   *
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00014   * All rights reserved.</center></h2>
00015   *
00016   * This software component is licensed by ST under BSD 3-Clause license,
00017   * the "License"; You may not use this file except in compliance with the
00018   * License. You may obtain a copy of the License at:
00019   *                        opensource.org/licenses/BSD-3-Clause
00020   *
00021   ******************************************************************************
00022   */
00023
00024 /* Includes ------------------------------------------------------------------*/
00025 #include "stm32wbxx_hal.h"
00026
00027 /** @addtogroup STM32WBxx_HAL_Driver
00028   * @{
00029   */
00030
00031 /** @defgroup SPIEx SPIEx
00032   * @brief SPI Extended HAL module driver
00033   * @{
00034   */
00035 #ifdef HAL_SPI_MODULE_ENABLED
00036
00037 /* Private typedef -----------------------------------------------------------*/
00038 /* Private defines -----------------------------------------------------------*/
00039 /** @defgroup SPIEx_Private_Constants SPIEx Private Constants
00040   * @{
00041   */
00042 #define SPI_FIFO_SIZE       4UL
00043 /**
00044   * @}
00045   */
00046
00047 /* Private macros ------------------------------------------------------------*/
00048 /* Private variables ---------------------------------------------------------*/
00049 /* Private function prototypes -----------------------------------------------*/
00050 /* Exported functions --------------------------------------------------------*/
00051
00052 /** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions
00053   * @{
00054   */
00055
00056 /** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions
00057   *  @brief   Data transfers functions
00058   *
00059 @verbatim
00060   ==============================================================================
00061                       ##### IO operation functions #####
00062  ===============================================================================
00063  [..]
00064     This subsection provides a set of extended functions to manage the SPI
00065     data transfers.
00066
00067     (#) Rx data flush function:
00068         (++) HAL_SPIEx_FlushRxFifo()
00069
00070 @endverbatim
00071   * @{
00072   */
00073
00074 /**
00075   * @brief  Flush the RX fifo.
00076   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
00077   *               the configuration information for the specified SPI module.
00078   * @retval HAL status
00079   */
00080 HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi)
00081 {
00082   __IO uint32_t tmpreg;
00083   uint8_t  count = 0U;
00084   while ((hspi->Instance->SR & SPI_FLAG_FRLVL) !=  SPI_FRLVL_EMPTY)
00085   {
00086     count++;
00087     tmpreg = hspi->Instance->DR;
00088     UNUSED(tmpreg); /* To avoid GCC warning */
00089     if (count == SPI_FIFO_SIZE)
00090     {
00091       return HAL_TIMEOUT;
00092     }
00093   }
00094   return HAL_OK;
00095 }
00096
00097 /**
00098   * @}
00099   */
00100
00101 /**
00102   * @}
00103   */
00104
00105 #endif /* HAL_SPI_MODULE_ENABLED */
00106
00107 /**
00108   * @}
00109   */
00110
00111 /**
00112   * @}
00113   */
00114
00115 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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STM32WB55xx HAL User Manual: stm32wbxx_hal_spi_ex.h Source File

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stm32wbxx_hal_spi_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_spi_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SPI HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_SPI_EX_H
00022 #define STM32WBxx_HAL_SPI_EX_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 /** @addtogroup STM32WBxx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup SPIEx
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /* Exported constants --------------------------------------------------------*/
00041 /* Exported macros -----------------------------------------------------------*/
00042 /* Exported functions --------------------------------------------------------*/
00043 /** @addtogroup SPIEx_Exported_Functions
00044   * @{
00045   */
00046
00047 /* Initialization and de-initialization functions  ****************************/
00048 /* IO operation functions *****************************************************/
00049 /** @addtogroup SPIEx_Exported_Functions_Group1
00050   * @{
00051   */
00052 HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);
00053 /**
00054   * @}
00055   */
00056
00057 /**
00058   * @}
00059   */
00060
00061 /**
00062   * @}
00063   */
00064
00065 /**
00066   * @}
00067   */
00068
00069 #ifdef __cplusplus
00070 }
00071 #endif
00072
00073 #endif /* STM32WBxx_HAL_SPI_EX_H */
00074
00075 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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STM32WB55xx HAL User Manual: stm32wbxx_hal_tim.c Source File

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stm32wbxx_hal_tim.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_tim.c
00004   * @author  MCD Application Team
00005   * @brief   TIM HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Timer (TIM) peripheral:
00008   *           + TIM Time Base Initialization
00009   *           + TIM Time Base Start
00010   *           + TIM Time Base Start Interruption
00011   *           + TIM Time Base Start DMA
00012   *           + TIM Output Compare/PWM Initialization
00013   *           + TIM Output Compare/PWM Channel Configuration
00014   *           + TIM Output Compare/PWM  Start
00015   *           + TIM Output Compare/PWM  Start Interruption
00016   *           + TIM Output Compare/PWM Start DMA
00017   *           + TIM Input Capture Initialization
00018   *           + TIM Input Capture Channel Configuration
00019   *           + TIM Input Capture Start
00020   *           + TIM Input Capture Start Interruption
00021   *           + TIM Input Capture Start DMA
00022   *           + TIM One Pulse Initialization
00023   *           + TIM One Pulse Channel Configuration
00024   *           + TIM One Pulse Start
00025   *           + TIM Encoder Interface Initialization
00026   *           + TIM Encoder Interface Start
00027   *           + TIM Encoder Interface Start Interruption
00028   *           + TIM Encoder Interface Start DMA
00029   *           + Commutation Event configuration with Interruption and DMA
00030   *           + TIM OCRef clear configuration
00031   *           + TIM External Clock configuration
00032   @verbatim
00033   ==============================================================================
00034                       ##### TIMER Generic features #####
00035   ==============================================================================
00036   [..] The Timer features include:
00037        (#) 16-bit up, down, up/down auto-reload counter.
00038        (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
00039            counter clock frequency either by any factor between 1 and 65536.
00040        (#) Up to 4 independent channels for:
00041            (++) Input Capture
00042            (++) Output Compare
00043            (++) PWM generation (Edge and Center-aligned Mode)
00044            (++) One-pulse mode output
00045        (#) Synchronization circuit to control the timer with external signals and to interconnect
00046             several timers together.
00047        (#) Supports incremental encoder for positioning purposes
00048
00049             ##### How to use this driver #####
00050   ==============================================================================
00051     [..]
00052      (#) Initialize the TIM low level resources by implementing the following functions
00053          depending on the selected feature:
00054            (++) Time Base : HAL_TIM_Base_MspInit()
00055            (++) Input Capture : HAL_TIM_IC_MspInit()
00056            (++) Output Compare : HAL_TIM_OC_MspInit()
00057            (++) PWM generation : HAL_TIM_PWM_MspInit()
00058            (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
00059            (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
00060
00061      (#) Initialize the TIM low level resources :
00062         (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
00063         (##) TIM pins configuration
00064             (+++) Enable the clock for the TIM GPIOs using the following function:
00065              __HAL_RCC_GPIOx_CLK_ENABLE();
00066             (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
00067
00068      (#) The external Clock can be configured, if needed (the default clock is the
00069          internal clock from the APBx), using the following function:
00070          HAL_TIM_ConfigClockSource, the clock configuration should be done before
00071          any start function.
00072
00073      (#) Configure the TIM in the desired functioning mode using one of the
00074        Initialization function of this driver:
00075        (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
00076        (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
00077             Output Compare signal.
00078        (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
00079             PWM signal.
00080        (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
00081             external signal.
00082        (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
00083             in One Pulse Mode.
00084        (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
00085
00086      (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
00087            (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
00088            (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
00089            (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
00090            (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
00091            (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
00092            (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
00093
00094      (#) The DMA Burst is managed with the two following functions:
00095          HAL_TIM_DMABurst_WriteStart()
00096          HAL_TIM_DMABurst_ReadStart()
00097
00098     *** Callback registration ***
00099   =============================================
00100
00101   [..]
00102   The compilation define  USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
00103   allows the user to configure dynamically the driver callbacks.
00104
00105   [..]
00106   Use Function @ref HAL_TIM_RegisterCallback() to register a callback.
00107   @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
00108   the Callback ID and a pointer to the user callback function.
00109
00110   [..]
00111   Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default
00112   weak function.
00113   @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
00114   and the Callback ID.
00115
00116   [..]
00117   These functions allow to register/unregister following callbacks:
00118     (+) Base_MspInitCallback              : TIM Base Msp Init Callback.
00119     (+) Base_MspDeInitCallback            : TIM Base Msp DeInit Callback.
00120     (+) IC_MspInitCallback                : TIM IC Msp Init Callback.
00121     (+) IC_MspDeInitCallback              : TIM IC Msp DeInit Callback.
00122     (+) OC_MspInitCallback                : TIM OC Msp Init Callback.
00123     (+) OC_MspDeInitCallback              : TIM OC Msp DeInit Callback.
00124     (+) PWM_MspInitCallback               : TIM PWM Msp Init Callback.
00125     (+) PWM_MspDeInitCallback             : TIM PWM Msp DeInit Callback.
00126     (+) OnePulse_MspInitCallback          : TIM One Pulse Msp Init Callback.
00127     (+) OnePulse_MspDeInitCallback        : TIM One Pulse Msp DeInit Callback.
00128     (+) Encoder_MspInitCallback           : TIM Encoder Msp Init Callback.
00129     (+) Encoder_MspDeInitCallback         : TIM Encoder Msp DeInit Callback.
00130     (+) HallSensor_MspInitCallback        : TIM Hall Sensor Msp Init Callback.
00131     (+) HallSensor_MspDeInitCallback      : TIM Hall Sensor Msp DeInit Callback.
00132     (+) PeriodElapsedCallback             : TIM Period Elapsed Callback.
00133     (+) PeriodElapsedHalfCpltCallback     : TIM Period Elapsed half complete Callback.
00134     (+) TriggerCallback                   : TIM Trigger Callback.
00135     (+) TriggerHalfCpltCallback           : TIM Trigger half complete Callback.
00136     (+) IC_CaptureCallback                : TIM Input Capture Callback.
00137     (+) IC_CaptureHalfCpltCallback        : TIM Input Capture half complete Callback.
00138     (+) OC_DelayElapsedCallback           : TIM Output Compare Delay Elapsed Callback.
00139     (+) PWM_PulseFinishedCallback         : TIM PWM Pulse Finished Callback.
00140     (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
00141     (+) ErrorCallback                     : TIM Error Callback.
00142     (+) CommutationCallback               : TIM Commutation Callback.
00143     (+) CommutationHalfCpltCallback       : TIM Commutation half complete Callback.
00144     (+) BreakCallback                     : TIM Break Callback.
00145     (+) Break2Callback                    : TIM Break2 Callback.
00146
00147   [..]
00148 By default, after the Init and when the state is HAL_TIM_STATE_RESET
00149 all interrupt callbacks are set to the corresponding weak functions:
00150   examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().
00151
00152   [..]
00153   Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
00154   functionalities in the Init / DeInit only when these callbacks are null
00155   (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
00156     keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
00157
00158   [..]
00159     Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
00160     Exception done MspInit / MspDeInit that can be registered / unregistered
00161     in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
00162     thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
00163   In that case first register the MspInit/MspDeInit user callbacks
00164       using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.
00165
00166   [..]
00167       When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
00168       not defined, the callback registration feature is not available and all callbacks
00169       are set to the corresponding weak functions.
00170
00171   @endverbatim
00172   ******************************************************************************
00173   * @attention
00174   *
00175   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00176   * All rights reserved.</center></h2>
00177   *
00178   * This software component is licensed by ST under BSD 3-Clause license,
00179   * the "License"; You may not use this file except in compliance with the
00180   * License. You may obtain a copy of the License at:
00181   *                        opensource.org/licenses/BSD-3-Clause
00182   *
00183   ******************************************************************************
00184   */
00185
00186 /* Includes ------------------------------------------------------------------*/
00187 #include "stm32wbxx_hal.h"
00188
00189 /** @addtogroup STM32WBxx_HAL_Driver
00190   * @{
00191   */
00192
00193 /** @defgroup TIM TIM
00194   * @brief TIM HAL module driver
00195   * @{
00196   */
00197
00198 #ifdef HAL_TIM_MODULE_ENABLED
00199
00200 /* Private typedef -----------------------------------------------------------*/
00201 /* Private define ------------------------------------------------------------*/
00202 /** @addtogroup TIM_Private_Constants
00203   * @{
00204   */
00205 #define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL
00206 /**
00207   * @}
00208   */
00209
00210 /* Private macro -------------------------------------------------------------*/
00211 /* Private variables ---------------------------------------------------------*/
00212 /* Private function prototypes -----------------------------------------------*/
00213 /** @addtogroup TIM_Private_Functions
00214   * @{
00215   */
00216 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
00217 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
00218 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
00219 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
00220 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
00221 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
00222 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
00223                               uint32_t TIM_ICFilter);
00224 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
00225 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
00226                               uint32_t TIM_ICFilter);
00227 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
00228                               uint32_t TIM_ICFilter);
00229 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
00230 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
00231 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
00232 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
00233 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
00234 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
00235                                                   TIM_SlaveConfigTypeDef *sSlaveConfig);
00236 /**
00237   * @}
00238   */
00239 /* Exported functions --------------------------------------------------------*/
00240
00241 /** @defgroup TIM_Exported_Functions TIM Exported Functions
00242   * @{
00243   */
00244
00245 /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
00246   *  @brief    Time Base functions
00247   *
00248 @verbatim
00249   ==============================================================================
00250               ##### Time Base functions #####
00251   ==============================================================================
00252   [..]
00253     This section provides functions allowing to:
00254     (+) Initialize and configure the TIM base.
00255     (+) De-initialize the TIM base.
00256     (+) Start the Time Base.
00257     (+) Stop the Time Base.
00258     (+) Start the Time Base and enable interrupt.
00259     (+) Stop the Time Base and disable interrupt.
00260     (+) Start the Time Base and enable DMA transfer.
00261     (+) Stop the Time Base and disable DMA transfer.
00262
00263 @endverbatim
00264   * @{
00265   */
00266 /**
00267   * @brief  Initializes the TIM Time base Unit according to the specified
00268   *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
00269   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
00270   *         requires a timer reset to avoid unexpected direction
00271   *         due to DIR bit readonly in center aligned mode.
00272   *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
00273   * @param  htim TIM Base handle
00274   * @retval HAL status
00275   */
00276 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
00277 {
00278   /* Check the TIM handle allocation */
00279   if (htim == NULL)
00280   {
00281     return HAL_ERROR;
00282   }
00283
00284   /* Check the parameters */
00285   assert_param(IS_TIM_INSTANCE(htim->Instance));
00286   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
00287   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
00288   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
00289
00290   if (htim->State == HAL_TIM_STATE_RESET)
00291   {
00292     /* Allocate lock resource and initialize it */
00293     htim->Lock = HAL_UNLOCKED;
00294
00295 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
00296     /* Reset interrupt callbacks to legacy weak callbacks */
00297     TIM_ResetCallback(htim);
00298
00299     if (htim->Base_MspInitCallback == NULL)
00300     {
00301       htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
00302     }
00303     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00304     htim->Base_MspInitCallback(htim);
00305 #else
00306     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00307     HAL_TIM_Base_MspInit(htim);
00308 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
00309   }
00310
00311   /* Set the TIM state */
00312   htim->State = HAL_TIM_STATE_BUSY;
00313
00314   /* Set the Time Base configuration */
00315   TIM_Base_SetConfig(htim->Instance, &htim->Init);
00316
00317   /* Initialize the TIM state*/
00318   htim->State = HAL_TIM_STATE_READY;
00319
00320   return HAL_OK;
00321 }
00322
00323 /**
00324   * @brief  DeInitializes the TIM Base peripheral
00325   * @param  htim TIM Base handle
00326   * @retval HAL status
00327   */
00328 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
00329 {
00330   /* Check the parameters */
00331   assert_param(IS_TIM_INSTANCE(htim->Instance));
00332
00333   htim->State = HAL_TIM_STATE_BUSY;
00334
00335   /* Disable the TIM Peripheral Clock */
00336   __HAL_TIM_DISABLE(htim);
00337
00338 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
00339   if (htim->Base_MspDeInitCallback == NULL)
00340   {
00341     htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
00342   }
00343   /* DeInit the low level hardware */
00344   htim->Base_MspDeInitCallback(htim);
00345 #else
00346   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00347   HAL_TIM_Base_MspDeInit(htim);
00348 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
00349
00350   /* Change TIM state */
00351   htim->State = HAL_TIM_STATE_RESET;
00352
00353   /* Release Lock */
00354   __HAL_UNLOCK(htim);
00355
00356   return HAL_OK;
00357 }
00358
00359 /**
00360   * @brief  Initializes the TIM Base MSP.
00361   * @param  htim TIM Base handle
00362   * @retval None
00363   */
00364 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
00365 {
00366   /* Prevent unused argument(s) compilation warning */
00367   UNUSED(htim);
00368
00369   /* NOTE : This function should not be modified, when the callback is needed,
00370             the HAL_TIM_Base_MspInit could be implemented in the user file
00371    */
00372 }
00373
00374 /**
00375   * @brief  DeInitializes TIM Base MSP.
00376   * @param  htim TIM Base handle
00377   * @retval None
00378   */
00379 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
00380 {
00381   /* Prevent unused argument(s) compilation warning */
00382   UNUSED(htim);
00383
00384   /* NOTE : This function should not be modified, when the callback is needed,
00385             the HAL_TIM_Base_MspDeInit could be implemented in the user file
00386    */
00387 }
00388
00389
00390 /**
00391   * @brief  Starts the TIM Base generation.
00392   * @param  htim TIM Base handle
00393   * @retval HAL status
00394   */
00395 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
00396 {
00397   uint32_t tmpsmcr;
00398
00399   /* Check the parameters */
00400   assert_param(IS_TIM_INSTANCE(htim->Instance));
00401
00402   /* Set the TIM state */
00403   htim->State = HAL_TIM_STATE_BUSY;
00404
00405   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00406   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00407   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00408   {
00409     __HAL_TIM_ENABLE(htim);
00410   }
00411
00412   /* Change the TIM state*/
00413   htim->State = HAL_TIM_STATE_READY;
00414
00415   /* Return function status */
00416   return HAL_OK;
00417 }
00418
00419 /**
00420   * @brief  Stops the TIM Base generation.
00421   * @param  htim TIM Base handle
00422   * @retval HAL status
00423   */
00424 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
00425 {
00426   /* Check the parameters */
00427   assert_param(IS_TIM_INSTANCE(htim->Instance));
00428
00429   /* Set the TIM state */
00430   htim->State = HAL_TIM_STATE_BUSY;
00431
00432   /* Disable the Peripheral */
00433   __HAL_TIM_DISABLE(htim);
00434
00435   /* Change the TIM state*/
00436   htim->State = HAL_TIM_STATE_READY;
00437
00438   /* Return function status */
00439   return HAL_OK;
00440 }
00441
00442 /**
00443   * @brief  Starts the TIM Base generation in interrupt mode.
00444   * @param  htim TIM Base handle
00445   * @retval HAL status
00446   */
00447 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
00448 {
00449   uint32_t tmpsmcr;
00450
00451   /* Check the parameters */
00452   assert_param(IS_TIM_INSTANCE(htim->Instance));
00453
00454   /* Enable the TIM Update interrupt */
00455   __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
00456
00457   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00458   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00459   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00460   {
00461     __HAL_TIM_ENABLE(htim);
00462   }
00463
00464   /* Return function status */
00465   return HAL_OK;
00466 }
00467
00468 /**
00469   * @brief  Stops the TIM Base generation in interrupt mode.
00470   * @param  htim TIM Base handle
00471   * @retval HAL status
00472   */
00473 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
00474 {
00475   /* Check the parameters */
00476   assert_param(IS_TIM_INSTANCE(htim->Instance));
00477   /* Disable the TIM Update interrupt */
00478   __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
00479
00480   /* Disable the Peripheral */
00481   __HAL_TIM_DISABLE(htim);
00482
00483   /* Return function status */
00484   return HAL_OK;
00485 }
00486
00487 /**
00488   * @brief  Starts the TIM Base generation in DMA mode.
00489   * @param  htim TIM Base handle
00490   * @param  pData The source Buffer address.
00491   * @param  Length The length of data to be transferred from memory to peripheral.
00492   * @retval HAL status
00493   */
00494 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
00495 {
00496   uint32_t tmpsmcr;
00497
00498   /* Check the parameters */
00499   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
00500
00501   if (htim->State == HAL_TIM_STATE_BUSY)
00502   {
00503     return HAL_BUSY;
00504   }
00505   else if (htim->State == HAL_TIM_STATE_READY)
00506   {
00507     if ((pData == NULL) && (Length > 0U))
00508     {
00509       return HAL_ERROR;
00510     }
00511     else
00512     {
00513       htim->State = HAL_TIM_STATE_BUSY;
00514     }
00515   }
00516   else
00517   {
00518     /* nothing to do */
00519   }
00520
00521   /* Set the DMA Period elapsed callbacks */
00522   htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
00523   htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
00524
00525   /* Set the DMA error callback */
00526   htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
00527
00528   /* Enable the DMA channel */
00529   if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)
00530   {
00531     return HAL_ERROR;
00532   }
00533
00534   /* Enable the TIM Update DMA request */
00535   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
00536
00537   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00538   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00539   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00540   {
00541     __HAL_TIM_ENABLE(htim);
00542   }
00543
00544   /* Return function status */
00545   return HAL_OK;
00546 }
00547
00548 /**
00549   * @brief  Stops the TIM Base generation in DMA mode.
00550   * @param  htim TIM Base handle
00551   * @retval HAL status
00552   */
00553 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
00554 {
00555   /* Check the parameters */
00556   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
00557
00558   /* Disable the TIM Update DMA request */
00559   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
00560
00561   (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
00562
00563   /* Disable the Peripheral */
00564   __HAL_TIM_DISABLE(htim);
00565
00566   /* Change the htim state */
00567   htim->State = HAL_TIM_STATE_READY;
00568
00569   /* Return function status */
00570   return HAL_OK;
00571 }
00572
00573 /**
00574   * @}
00575   */
00576
00577 /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
00578   *  @brief    TIM Output Compare functions
00579   *
00580 @verbatim
00581   ==============================================================================
00582                   ##### TIM Output Compare functions #####
00583   ==============================================================================
00584   [..]
00585     This section provides functions allowing to:
00586     (+) Initialize and configure the TIM Output Compare.
00587     (+) De-initialize the TIM Output Compare.
00588     (+) Start the TIM Output Compare.
00589     (+) Stop the TIM Output Compare.
00590     (+) Start the TIM Output Compare and enable interrupt.
00591     (+) Stop the TIM Output Compare and disable interrupt.
00592     (+) Start the TIM Output Compare and enable DMA transfer.
00593     (+) Stop the TIM Output Compare and disable DMA transfer.
00594
00595 @endverbatim
00596   * @{
00597   */
00598 /**
00599   * @brief  Initializes the TIM Output Compare according to the specified
00600   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
00601   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
00602   *         requires a timer reset to avoid unexpected direction
00603   *         due to DIR bit readonly in center aligned mode.
00604   *         Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
00605   * @param  htim TIM Output Compare handle
00606   * @retval HAL status
00607   */
00608 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
00609 {
00610   /* Check the TIM handle allocation */
00611   if (htim == NULL)
00612   {
00613     return HAL_ERROR;
00614   }
00615
00616   /* Check the parameters */
00617   assert_param(IS_TIM_INSTANCE(htim->Instance));
00618   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
00619   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
00620   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
00621
00622   if (htim->State == HAL_TIM_STATE_RESET)
00623   {
00624     /* Allocate lock resource and initialize it */
00625     htim->Lock = HAL_UNLOCKED;
00626
00627 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
00628     /* Reset interrupt callbacks to legacy weak callbacks */
00629     TIM_ResetCallback(htim);
00630
00631     if (htim->OC_MspInitCallback == NULL)
00632     {
00633       htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
00634     }
00635     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00636     htim->OC_MspInitCallback(htim);
00637 #else
00638     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
00639     HAL_TIM_OC_MspInit(htim);
00640 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
00641   }
00642
00643   /* Set the TIM state */
00644   htim->State = HAL_TIM_STATE_BUSY;
00645
00646   /* Init the base time for the Output Compare */
00647   TIM_Base_SetConfig(htim->Instance,  &htim->Init);
00648
00649   /* Initialize the TIM state*/
00650   htim->State = HAL_TIM_STATE_READY;
00651
00652   return HAL_OK;
00653 }
00654
00655 /**
00656   * @brief  DeInitializes the TIM peripheral
00657   * @param  htim TIM Output Compare handle
00658   * @retval HAL status
00659   */
00660 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
00661 {
00662   /* Check the parameters */
00663   assert_param(IS_TIM_INSTANCE(htim->Instance));
00664
00665   htim->State = HAL_TIM_STATE_BUSY;
00666
00667   /* Disable the TIM Peripheral Clock */
00668   __HAL_TIM_DISABLE(htim);
00669
00670 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
00671   if (htim->OC_MspDeInitCallback == NULL)
00672   {
00673     htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
00674   }
00675   /* DeInit the low level hardware */
00676   htim->OC_MspDeInitCallback(htim);
00677 #else
00678   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
00679   HAL_TIM_OC_MspDeInit(htim);
00680 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
00681
00682   /* Change TIM state */
00683   htim->State = HAL_TIM_STATE_RESET;
00684
00685   /* Release Lock */
00686   __HAL_UNLOCK(htim);
00687
00688   return HAL_OK;
00689 }
00690
00691 /**
00692   * @brief  Initializes the TIM Output Compare MSP.
00693   * @param  htim TIM Output Compare handle
00694   * @retval None
00695   */
00696 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
00697 {
00698   /* Prevent unused argument(s) compilation warning */
00699   UNUSED(htim);
00700
00701   /* NOTE : This function should not be modified, when the callback is needed,
00702             the HAL_TIM_OC_MspInit could be implemented in the user file
00703    */
00704 }
00705
00706 /**
00707   * @brief  DeInitializes TIM Output Compare MSP.
00708   * @param  htim TIM Output Compare handle
00709   * @retval None
00710   */
00711 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
00712 {
00713   /* Prevent unused argument(s) compilation warning */
00714   UNUSED(htim);
00715
00716   /* NOTE : This function should not be modified, when the callback is needed,
00717             the HAL_TIM_OC_MspDeInit could be implemented in the user file
00718    */
00719 }
00720
00721 /**
00722   * @brief  Starts the TIM Output Compare signal generation.
00723   * @param  htim TIM Output Compare handle
00724   * @param  Channel TIM Channel to be enabled
00725   *          This parameter can be one of the following values:
00726   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00727   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00728   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00729   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00730   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
00731   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
00732   * @retval HAL status
00733   */
00734 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
00735 {
00736   uint32_t tmpsmcr;
00737
00738   /* Check the parameters */
00739   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00740
00741   /* Enable the Output compare channel */
00742   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
00743
00744   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00745   {
00746     /* Enable the main output */
00747     __HAL_TIM_MOE_ENABLE(htim);
00748   }
00749
00750   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00751   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00752   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00753   {
00754     __HAL_TIM_ENABLE(htim);
00755   }
00756
00757   /* Return function status */
00758   return HAL_OK;
00759 }
00760
00761 /**
00762   * @brief  Stops the TIM Output Compare signal generation.
00763   * @param  htim TIM Output Compare handle
00764   * @param  Channel TIM Channel to be disabled
00765   *          This parameter can be one of the following values:
00766   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00767   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00768   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00769   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00770   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
00771   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
00772   * @retval HAL status
00773   */
00774 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
00775 {
00776   /* Check the parameters */
00777   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00778
00779   /* Disable the Output compare channel */
00780   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
00781
00782   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00783   {
00784     /* Disable the Main Output */
00785     __HAL_TIM_MOE_DISABLE(htim);
00786   }
00787
00788   /* Disable the Peripheral */
00789   __HAL_TIM_DISABLE(htim);
00790
00791   /* Return function status */
00792   return HAL_OK;
00793 }
00794
00795 /**
00796   * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
00797   * @param  htim TIM Output Compare handle
00798   * @param  Channel TIM Channel to be enabled
00799   *          This parameter can be one of the following values:
00800   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00801   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00802   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00803   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00804   * @retval HAL status
00805   */
00806 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00807 {
00808   uint32_t tmpsmcr;
00809
00810   /* Check the parameters */
00811   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00812
00813   switch (Channel)
00814   {
00815     case TIM_CHANNEL_1:
00816     {
00817       /* Enable the TIM Capture/Compare 1 interrupt */
00818       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00819       break;
00820     }
00821
00822     case TIM_CHANNEL_2:
00823     {
00824       /* Enable the TIM Capture/Compare 2 interrupt */
00825       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
00826       break;
00827     }
00828
00829     case TIM_CHANNEL_3:
00830     {
00831       /* Enable the TIM Capture/Compare 3 interrupt */
00832       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
00833       break;
00834     }
00835
00836     case TIM_CHANNEL_4:
00837     {
00838       /* Enable the TIM Capture/Compare 4 interrupt */
00839       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
00840       break;
00841     }
00842
00843     default:
00844       break;
00845   }
00846
00847   /* Enable the Output compare channel */
00848   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
00849
00850   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00851   {
00852     /* Enable the main output */
00853     __HAL_TIM_MOE_ENABLE(htim);
00854   }
00855
00856   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00857   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00858   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00859   {
00860     __HAL_TIM_ENABLE(htim);
00861   }
00862
00863   /* Return function status */
00864   return HAL_OK;
00865 }
00866
00867 /**
00868   * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
00869   * @param  htim TIM Output Compare handle
00870   * @param  Channel TIM Channel to be disabled
00871   *          This parameter can be one of the following values:
00872   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00873   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00874   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00875   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00876   * @retval HAL status
00877   */
00878 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00879 {
00880   /* Check the parameters */
00881   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00882
00883   switch (Channel)
00884   {
00885     case TIM_CHANNEL_1:
00886     {
00887       /* Disable the TIM Capture/Compare 1 interrupt */
00888       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
00889       break;
00890     }
00891
00892     case TIM_CHANNEL_2:
00893     {
00894       /* Disable the TIM Capture/Compare 2 interrupt */
00895       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
00896       break;
00897     }
00898
00899     case TIM_CHANNEL_3:
00900     {
00901       /* Disable the TIM Capture/Compare 3 interrupt */
00902       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
00903       break;
00904     }
00905
00906     case TIM_CHANNEL_4:
00907     {
00908       /* Disable the TIM Capture/Compare 4 interrupt */
00909       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
00910       break;
00911     }
00912
00913     default:
00914       break;
00915   }
00916
00917   /* Disable the Output compare channel */
00918   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
00919
00920   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00921   {
00922     /* Disable the Main Output */
00923     __HAL_TIM_MOE_DISABLE(htim);
00924   }
00925
00926   /* Disable the Peripheral */
00927   __HAL_TIM_DISABLE(htim);
00928
00929   /* Return function status */
00930   return HAL_OK;
00931 }
00932
00933 /**
00934   * @brief  Starts the TIM Output Compare signal generation in DMA mode.
00935   * @param  htim TIM Output Compare handle
00936   * @param  Channel TIM Channel to be enabled
00937   *          This parameter can be one of the following values:
00938   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00939   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00940   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00941   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00942   * @param  pData The source Buffer address.
00943   * @param  Length The length of data to be transferred from memory to TIM peripheral
00944   * @retval HAL status
00945   */
00946 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
00947 {
00948   uint32_t tmpsmcr;
00949
00950   /* Check the parameters */
00951   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00952
00953   if (htim->State == HAL_TIM_STATE_BUSY)
00954   {
00955     return HAL_BUSY;
00956   }
00957   else if (htim->State == HAL_TIM_STATE_READY)
00958   {
00959     if ((pData == NULL) && (Length > 0U))
00960     {
00961       return HAL_ERROR;
00962     }
00963     else
00964     {
00965       htim->State = HAL_TIM_STATE_BUSY;
00966     }
00967   }
00968   else
00969   {
00970     /* nothing to do */
00971   }
00972
00973   switch (Channel)
00974   {
00975     case TIM_CHANNEL_1:
00976     {
00977       /* Set the DMA compare callbacks */
00978       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
00979       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
00980
00981       /* Set the DMA error callback */
00982       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
00983
00984       /* Enable the DMA channel */
00985       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
00986       {
00987         return HAL_ERROR;
00988       }
00989
00990       /* Enable the TIM Capture/Compare 1 DMA request */
00991       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
00992       break;
00993     }
00994
00995     case TIM_CHANNEL_2:
00996     {
00997       /* Set the DMA compare callbacks */
00998       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
00999       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01000
01001       /* Set the DMA error callback */
01002       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
01003
01004       /* Enable the DMA channel */
01005       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
01006       {
01007         return HAL_ERROR;
01008       }
01009
01010       /* Enable the TIM Capture/Compare 2 DMA request */
01011       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
01012       break;
01013     }
01014
01015     case TIM_CHANNEL_3:
01016     {
01017       /* Set the DMA compare callbacks */
01018       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
01019       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01020
01021       /* Set the DMA error callback */
01022       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
01023
01024       /* Enable the DMA channel */
01025       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
01026       {
01027         return HAL_ERROR;
01028       }
01029       /* Enable the TIM Capture/Compare 3 DMA request */
01030       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
01031       break;
01032     }
01033
01034     case TIM_CHANNEL_4:
01035     {
01036       /* Set the DMA compare callbacks */
01037       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
01038       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01039
01040       /* Set the DMA error callback */
01041       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
01042
01043       /* Enable the DMA channel */
01044       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
01045       {
01046         return HAL_ERROR;
01047       }
01048       /* Enable the TIM Capture/Compare 4 DMA request */
01049       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
01050       break;
01051     }
01052
01053     default:
01054       break;
01055   }
01056
01057   /* Enable the Output compare channel */
01058   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01059
01060   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01061   {
01062     /* Enable the main output */
01063     __HAL_TIM_MOE_ENABLE(htim);
01064   }
01065
01066   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
01067   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
01068   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
01069   {
01070     __HAL_TIM_ENABLE(htim);
01071   }
01072
01073   /* Return function status */
01074   return HAL_OK;
01075 }
01076
01077 /**
01078   * @brief  Stops the TIM Output Compare signal generation in DMA mode.
01079   * @param  htim TIM Output Compare handle
01080   * @param  Channel TIM Channel to be disabled
01081   *          This parameter can be one of the following values:
01082   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01083   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01084   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01085   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01086   * @retval HAL status
01087   */
01088 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
01089 {
01090   /* Check the parameters */
01091   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01092
01093   switch (Channel)
01094   {
01095     case TIM_CHANNEL_1:
01096     {
01097       /* Disable the TIM Capture/Compare 1 DMA request */
01098       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
01099       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
01100       break;
01101     }
01102
01103     case TIM_CHANNEL_2:
01104     {
01105       /* Disable the TIM Capture/Compare 2 DMA request */
01106       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
01107       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
01108       break;
01109     }
01110
01111     case TIM_CHANNEL_3:
01112     {
01113       /* Disable the TIM Capture/Compare 3 DMA request */
01114       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
01115       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
01116       break;
01117     }
01118
01119     case TIM_CHANNEL_4:
01120     {
01121       /* Disable the TIM Capture/Compare 4 interrupt */
01122       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
01123       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
01124       break;
01125     }
01126
01127     default:
01128       break;
01129   }
01130
01131   /* Disable the Output compare channel */
01132   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01133
01134   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01135   {
01136     /* Disable the Main Output */
01137     __HAL_TIM_MOE_DISABLE(htim);
01138   }
01139
01140   /* Disable the Peripheral */
01141   __HAL_TIM_DISABLE(htim);
01142
01143   /* Change the htim state */
01144   htim->State = HAL_TIM_STATE_READY;
01145
01146   /* Return function status */
01147   return HAL_OK;
01148 }
01149
01150 /**
01151   * @}
01152   */
01153
01154 /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
01155   *  @brief    TIM PWM functions
01156   *
01157 @verbatim
01158   ==============================================================================
01159                           ##### TIM PWM functions #####
01160   ==============================================================================
01161   [..]
01162     This section provides functions allowing to:
01163     (+) Initialize and configure the TIM PWM.
01164     (+) De-initialize the TIM PWM.
01165     (+) Start the TIM PWM.
01166     (+) Stop the TIM PWM.
01167     (+) Start the TIM PWM and enable interrupt.
01168     (+) Stop the TIM PWM and disable interrupt.
01169     (+) Start the TIM PWM and enable DMA transfer.
01170     (+) Stop the TIM PWM and disable DMA transfer.
01171
01172 @endverbatim
01173   * @{
01174   */
01175 /**
01176   * @brief  Initializes the TIM PWM Time Base according to the specified
01177   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
01178   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
01179   *         requires a timer reset to avoid unexpected direction
01180   *         due to DIR bit readonly in center aligned mode.
01181   *         Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
01182   * @param  htim TIM PWM handle
01183   * @retval HAL status
01184   */
01185 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
01186 {
01187   /* Check the TIM handle allocation */
01188   if (htim == NULL)
01189   {
01190     return HAL_ERROR;
01191   }
01192
01193   /* Check the parameters */
01194   assert_param(IS_TIM_INSTANCE(htim->Instance));
01195   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
01196   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
01197   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
01198
01199   if (htim->State == HAL_TIM_STATE_RESET)
01200   {
01201     /* Allocate lock resource and initialize it */
01202     htim->Lock = HAL_UNLOCKED;
01203
01204 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
01205     /* Reset interrupt callbacks to legacy weak callbacks */
01206     TIM_ResetCallback(htim);
01207
01208     if (htim->PWM_MspInitCallback == NULL)
01209     {
01210       htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
01211     }
01212     /* Init the low level hardware : GPIO, CLOCK, NVIC */
01213     htim->PWM_MspInitCallback(htim);
01214 #else
01215     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
01216     HAL_TIM_PWM_MspInit(htim);
01217 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
01218   }
01219
01220   /* Set the TIM state */
01221   htim->State = HAL_TIM_STATE_BUSY;
01222
01223   /* Init the base time for the PWM */
01224   TIM_Base_SetConfig(htim->Instance, &htim->Init);
01225
01226   /* Initialize the TIM state*/
01227   htim->State = HAL_TIM_STATE_READY;
01228
01229   return HAL_OK;
01230 }
01231
01232 /**
01233   * @brief  DeInitializes the TIM peripheral
01234   * @param  htim TIM PWM handle
01235   * @retval HAL status
01236   */
01237 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
01238 {
01239   /* Check the parameters */
01240   assert_param(IS_TIM_INSTANCE(htim->Instance));
01241
01242   htim->State = HAL_TIM_STATE_BUSY;
01243
01244   /* Disable the TIM Peripheral Clock */
01245   __HAL_TIM_DISABLE(htim);
01246
01247 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
01248   if (htim->PWM_MspDeInitCallback == NULL)
01249   {
01250     htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
01251   }
01252   /* DeInit the low level hardware */
01253   htim->PWM_MspDeInitCallback(htim);
01254 #else
01255   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
01256   HAL_TIM_PWM_MspDeInit(htim);
01257 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
01258
01259   /* Change TIM state */
01260   htim->State = HAL_TIM_STATE_RESET;
01261
01262   /* Release Lock */
01263   __HAL_UNLOCK(htim);
01264
01265   return HAL_OK;
01266 }
01267
01268 /**
01269   * @brief  Initializes the TIM PWM MSP.
01270   * @param  htim TIM PWM handle
01271   * @retval None
01272   */
01273 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
01274 {
01275   /* Prevent unused argument(s) compilation warning */
01276   UNUSED(htim);
01277
01278   /* NOTE : This function should not be modified, when the callback is needed,
01279             the HAL_TIM_PWM_MspInit could be implemented in the user file
01280    */
01281 }
01282
01283 /**
01284   * @brief  DeInitializes TIM PWM MSP.
01285   * @param  htim TIM PWM handle
01286   * @retval None
01287   */
01288 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
01289 {
01290   /* Prevent unused argument(s) compilation warning */
01291   UNUSED(htim);
01292
01293   /* NOTE : This function should not be modified, when the callback is needed,
01294             the HAL_TIM_PWM_MspDeInit could be implemented in the user file
01295    */
01296 }
01297
01298 /**
01299   * @brief  Starts the PWM signal generation.
01300   * @param  htim TIM handle
01301   * @param  Channel TIM Channels to be enabled
01302   *          This parameter can be one of the following values:
01303   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01304   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01305   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01306   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01307   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
01308   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
01309   * @retval HAL status
01310   */
01311 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
01312 {
01313   uint32_t tmpsmcr;
01314
01315   /* Check the parameters */
01316   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01317
01318   /* Enable the Capture compare channel */
01319   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01320
01321   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01322   {
01323     /* Enable the main output */
01324     __HAL_TIM_MOE_ENABLE(htim);
01325   }
01326
01327   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
01328   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
01329   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
01330   {
01331     __HAL_TIM_ENABLE(htim);
01332   }
01333
01334   /* Return function status */
01335   return HAL_OK;
01336 }
01337
01338 /**
01339   * @brief  Stops the PWM signal generation.
01340   * @param  htim TIM PWM handle
01341   * @param  Channel TIM Channels to be disabled
01342   *          This parameter can be one of the following values:
01343   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01344   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01345   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01346   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01347   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
01348   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
01349   * @retval HAL status
01350   */
01351 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
01352 {
01353   /* Check the parameters */
01354   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01355
01356   /* Disable the Capture compare channel */
01357   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01358
01359   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01360   {
01361     /* Disable the Main Output */
01362     __HAL_TIM_MOE_DISABLE(htim);
01363   }
01364
01365   /* Disable the Peripheral */
01366   __HAL_TIM_DISABLE(htim);
01367
01368   /* Change the htim state */
01369   htim->State = HAL_TIM_STATE_READY;
01370
01371   /* Return function status */
01372   return HAL_OK;
01373 }
01374
01375 /**
01376   * @brief  Starts the PWM signal generation in interrupt mode.
01377   * @param  htim TIM PWM handle
01378   * @param  Channel TIM Channel to be enabled
01379   *          This parameter can be one of the following values:
01380   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01381   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01382   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01383   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01384   * @retval HAL status
01385   */
01386 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
01387 {
01388   uint32_t tmpsmcr;
01389   /* Check the parameters */
01390   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01391
01392   switch (Channel)
01393   {
01394     case TIM_CHANNEL_1:
01395     {
01396       /* Enable the TIM Capture/Compare 1 interrupt */
01397       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
01398       break;
01399     }
01400
01401     case TIM_CHANNEL_2:
01402     {
01403       /* Enable the TIM Capture/Compare 2 interrupt */
01404       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
01405       break;
01406     }
01407
01408     case TIM_CHANNEL_3:
01409     {
01410       /* Enable the TIM Capture/Compare 3 interrupt */
01411       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
01412       break;
01413     }
01414
01415     case TIM_CHANNEL_4:
01416     {
01417       /* Enable the TIM Capture/Compare 4 interrupt */
01418       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
01419       break;
01420     }
01421
01422     default:
01423       break;
01424   }
01425
01426   /* Enable the Capture compare channel */
01427   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01428
01429   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01430   {
01431     /* Enable the main output */
01432     __HAL_TIM_MOE_ENABLE(htim);
01433   }
01434
01435   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
01436   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
01437   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
01438   {
01439     __HAL_TIM_ENABLE(htim);
01440   }
01441
01442   /* Return function status */
01443   return HAL_OK;
01444 }
01445
01446 /**
01447   * @brief  Stops the PWM signal generation in interrupt mode.
01448   * @param  htim TIM PWM handle
01449   * @param  Channel TIM Channels to be disabled
01450   *          This parameter can be one of the following values:
01451   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01452   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01453   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01454   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01455   * @retval HAL status
01456   */
01457 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
01458 {
01459   /* Check the parameters */
01460   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01461
01462   switch (Channel)
01463   {
01464     case TIM_CHANNEL_1:
01465     {
01466       /* Disable the TIM Capture/Compare 1 interrupt */
01467       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01468       break;
01469     }
01470
01471     case TIM_CHANNEL_2:
01472     {
01473       /* Disable the TIM Capture/Compare 2 interrupt */
01474       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01475       break;
01476     }
01477
01478     case TIM_CHANNEL_3:
01479     {
01480       /* Disable the TIM Capture/Compare 3 interrupt */
01481       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
01482       break;
01483     }
01484
01485     case TIM_CHANNEL_4:
01486     {
01487       /* Disable the TIM Capture/Compare 4 interrupt */
01488       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
01489       break;
01490     }
01491
01492     default:
01493       break;
01494   }
01495
01496   /* Disable the Capture compare channel */
01497   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01498
01499   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01500   {
01501     /* Disable the Main Output */
01502     __HAL_TIM_MOE_DISABLE(htim);
01503   }
01504
01505   /* Disable the Peripheral */
01506   __HAL_TIM_DISABLE(htim);
01507
01508   /* Return function status */
01509   return HAL_OK;
01510 }
01511
01512 /**
01513   * @brief  Starts the TIM PWM signal generation in DMA mode.
01514   * @param  htim TIM PWM handle
01515   * @param  Channel TIM Channels to be enabled
01516   *          This parameter can be one of the following values:
01517   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01518   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01519   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01520   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01521   * @param  pData The source Buffer address.
01522   * @param  Length The length of data to be transferred from memory to TIM peripheral
01523   * @retval HAL status
01524   */
01525 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
01526 {
01527   uint32_t tmpsmcr;
01528
01529   /* Check the parameters */
01530   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01531
01532   if (htim->State == HAL_TIM_STATE_BUSY)
01533   {
01534     return HAL_BUSY;
01535   }
01536   else if (htim->State == HAL_TIM_STATE_READY)
01537   {
01538     if ((pData == NULL) && (Length > 0U))
01539     {
01540       return HAL_ERROR;
01541     }
01542     else
01543     {
01544       htim->State = HAL_TIM_STATE_BUSY;
01545     }
01546   }
01547   else
01548   {
01549     /* nothing to do */
01550   }
01551
01552   switch (Channel)
01553   {
01554     case TIM_CHANNEL_1:
01555     {
01556       /* Set the DMA compare callbacks */
01557       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
01558       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01559
01560       /* Set the DMA error callback */
01561       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
01562
01563       /* Enable the DMA channel */
01564       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
01565       {
01566         return HAL_ERROR;
01567       }
01568
01569       /* Enable the TIM Capture/Compare 1 DMA request */
01570       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
01571       break;
01572     }
01573
01574     case TIM_CHANNEL_2:
01575     {
01576       /* Set the DMA compare callbacks */
01577       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
01578       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01579
01580       /* Set the DMA error callback */
01581       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
01582
01583       /* Enable the DMA channel */
01584       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
01585       {
01586         return HAL_ERROR;
01587       }
01588       /* Enable the TIM Capture/Compare 2 DMA request */
01589       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
01590       break;
01591     }
01592
01593     case TIM_CHANNEL_3:
01594     {
01595       /* Set the DMA compare callbacks */
01596       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
01597       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01598
01599       /* Set the DMA error callback */
01600       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
01601
01602       /* Enable the DMA channel */
01603       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
01604       {
01605         return HAL_ERROR;
01606       }
01607       /* Enable the TIM Output Capture/Compare 3 request */
01608       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
01609       break;
01610     }
01611
01612     case TIM_CHANNEL_4:
01613     {
01614       /* Set the DMA compare callbacks */
01615       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
01616       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01617
01618       /* Set the DMA error callback */
01619       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
01620
01621       /* Enable the DMA channel */
01622       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
01623       {
01624         return HAL_ERROR;
01625       }
01626       /* Enable the TIM Capture/Compare 4 DMA request */
01627       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
01628       break;
01629     }
01630
01631     default:
01632       break;
01633   }
01634
01635   /* Enable the Capture compare channel */
01636   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01637
01638   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01639   {
01640     /* Enable the main output */
01641     __HAL_TIM_MOE_ENABLE(htim);
01642   }
01643
01644   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
01645   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
01646   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
01647   {
01648     __HAL_TIM_ENABLE(htim);
01649   }
01650
01651   /* Return function status */
01652   return HAL_OK;
01653 }
01654
01655 /**
01656   * @brief  Stops the TIM PWM signal generation in DMA mode.
01657   * @param  htim TIM PWM handle
01658   * @param  Channel TIM Channels to be disabled
01659   *          This parameter can be one of the following values:
01660   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01661   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01662   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01663   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01664   * @retval HAL status
01665   */
01666 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
01667 {
01668   /* Check the parameters */
01669   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01670
01671   switch (Channel)
01672   {
01673     case TIM_CHANNEL_1:
01674     {
01675       /* Disable the TIM Capture/Compare 1 DMA request */
01676       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
01677       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
01678       break;
01679     }
01680
01681     case TIM_CHANNEL_2:
01682     {
01683       /* Disable the TIM Capture/Compare 2 DMA request */
01684       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
01685       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
01686       break;
01687     }
01688
01689     case TIM_CHANNEL_3:
01690     {
01691       /* Disable the TIM Capture/Compare 3 DMA request */
01692       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
01693       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
01694       break;
01695     }
01696
01697     case TIM_CHANNEL_4:
01698     {
01699       /* Disable the TIM Capture/Compare 4 interrupt */
01700       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
01701       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
01702       break;
01703     }
01704
01705     default:
01706       break;
01707   }
01708
01709   /* Disable the Capture compare channel */
01710   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01711
01712   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01713   {
01714     /* Disable the Main Output */
01715     __HAL_TIM_MOE_DISABLE(htim);
01716   }
01717
01718   /* Disable the Peripheral */
01719   __HAL_TIM_DISABLE(htim);
01720
01721   /* Change the htim state */
01722   htim->State = HAL_TIM_STATE_READY;
01723
01724   /* Return function status */
01725   return HAL_OK;
01726 }
01727
01728 /**
01729   * @}
01730   */
01731
01732 /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
01733   *  @brief    TIM Input Capture functions
01734   *
01735 @verbatim
01736   ==============================================================================
01737               ##### TIM Input Capture functions #####
01738   ==============================================================================
01739  [..]
01740    This section provides functions allowing to:
01741    (+) Initialize and configure the TIM Input Capture.
01742    (+) De-initialize the TIM Input Capture.
01743    (+) Start the TIM Input Capture.
01744    (+) Stop the TIM Input Capture.
01745    (+) Start the TIM Input Capture and enable interrupt.
01746    (+) Stop the TIM Input Capture and disable interrupt.
01747    (+) Start the TIM Input Capture and enable DMA transfer.
01748    (+) Stop the TIM Input Capture and disable DMA transfer.
01749
01750 @endverbatim
01751   * @{
01752   */
01753 /**
01754   * @brief  Initializes the TIM Input Capture Time base according to the specified
01755   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
01756   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
01757   *         requires a timer reset to avoid unexpected direction
01758   *         due to DIR bit readonly in center aligned mode.
01759   *         Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
01760   * @param  htim TIM Input Capture handle
01761   * @retval HAL status
01762   */
01763 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
01764 {
01765   /* Check the TIM handle allocation */
01766   if (htim == NULL)
01767   {
01768     return HAL_ERROR;
01769   }
01770
01771   /* Check the parameters */
01772   assert_param(IS_TIM_INSTANCE(htim->Instance));
01773   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
01774   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
01775   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
01776
01777   if (htim->State == HAL_TIM_STATE_RESET)
01778   {
01779     /* Allocate lock resource and initialize it */
01780     htim->Lock = HAL_UNLOCKED;
01781
01782 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
01783     /* Reset interrupt callbacks to legacy weak callbacks */
01784     TIM_ResetCallback(htim);
01785
01786     if (htim->IC_MspInitCallback == NULL)
01787     {
01788       htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
01789     }
01790     /* Init the low level hardware : GPIO, CLOCK, NVIC */
01791     htim->IC_MspInitCallback(htim);
01792 #else
01793     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
01794     HAL_TIM_IC_MspInit(htim);
01795 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
01796   }
01797
01798   /* Set the TIM state */
01799   htim->State = HAL_TIM_STATE_BUSY;
01800
01801   /* Init the base time for the input capture */
01802   TIM_Base_SetConfig(htim->Instance, &htim->Init);
01803
01804   /* Initialize the TIM state*/
01805   htim->State = HAL_TIM_STATE_READY;
01806
01807   return HAL_OK;
01808 }
01809
01810 /**
01811   * @brief  DeInitializes the TIM peripheral
01812   * @param  htim TIM Input Capture handle
01813   * @retval HAL status
01814   */
01815 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
01816 {
01817   /* Check the parameters */
01818   assert_param(IS_TIM_INSTANCE(htim->Instance));
01819
01820   htim->State = HAL_TIM_STATE_BUSY;
01821
01822   /* Disable the TIM Peripheral Clock */
01823   __HAL_TIM_DISABLE(htim);
01824
01825 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
01826   if (htim->IC_MspDeInitCallback == NULL)
01827   {
01828     htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
01829   }
01830   /* DeInit the low level hardware */
01831   htim->IC_MspDeInitCallback(htim);
01832 #else
01833   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
01834   HAL_TIM_IC_MspDeInit(htim);
01835 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
01836
01837   /* Change TIM state */
01838   htim->State = HAL_TIM_STATE_RESET;
01839
01840   /* Release Lock */
01841   __HAL_UNLOCK(htim);
01842
01843   return HAL_OK;
01844 }
01845
01846 /**
01847   * @brief  Initializes the TIM Input Capture MSP.
01848   * @param  htim TIM Input Capture handle
01849   * @retval None
01850   */
01851 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
01852 {
01853   /* Prevent unused argument(s) compilation warning */
01854   UNUSED(htim);
01855
01856   /* NOTE : This function should not be modified, when the callback is needed,
01857             the HAL_TIM_IC_MspInit could be implemented in the user file
01858    */
01859 }
01860
01861 /**
01862   * @brief  DeInitializes TIM Input Capture MSP.
01863   * @param  htim TIM handle
01864   * @retval None
01865   */
01866 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
01867 {
01868   /* Prevent unused argument(s) compilation warning */
01869   UNUSED(htim);
01870
01871   /* NOTE : This function should not be modified, when the callback is needed,
01872             the HAL_TIM_IC_MspDeInit could be implemented in the user file
01873    */
01874 }
01875
01876 /**
01877   * @brief  Starts the TIM Input Capture measurement.
01878   * @param  htim TIM Input Capture handle
01879   * @param  Channel TIM Channels to be enabled
01880   *          This parameter can be one of the following values:
01881   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01882   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01883   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01884   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01885   * @retval HAL status
01886   */
01887 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
01888 {
01889   uint32_t tmpsmcr;
01890
01891   /* Check the parameters */
01892   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01893
01894   /* Enable the Input Capture channel */
01895   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01896
01897   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
01898   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
01899   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
01900   {
01901     __HAL_TIM_ENABLE(htim);
01902   }
01903
01904   /* Return function status */
01905   return HAL_OK;
01906 }
01907
01908 /**
01909   * @brief  Stops the TIM Input Capture measurement.
01910   * @param  htim TIM Input Capture handle
01911   * @param  Channel TIM Channels to be disabled
01912   *          This parameter can be one of the following values:
01913   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01914   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01915   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01916   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01917   * @retval HAL status
01918   */
01919 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
01920 {
01921   /* Check the parameters */
01922   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01923
01924   /* Disable the Input Capture channel */
01925   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01926
01927   /* Disable the Peripheral */
01928   __HAL_TIM_DISABLE(htim);
01929
01930   /* Return function status */
01931   return HAL_OK;
01932 }
01933
01934 /**
01935   * @brief  Starts the TIM Input Capture measurement in interrupt mode.
01936   * @param  htim TIM Input Capture handle
01937   * @param  Channel TIM Channels to be enabled
01938   *          This parameter can be one of the following values:
01939   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01940   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01941   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01942   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01943   * @retval HAL status
01944   */
01945 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
01946 {
01947   uint32_t tmpsmcr;
01948
01949   /* Check the parameters */
01950   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01951
01952   switch (Channel)
01953   {
01954     case TIM_CHANNEL_1:
01955     {
01956       /* Enable the TIM Capture/Compare 1 interrupt */
01957       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
01958       break;
01959     }
01960
01961     case TIM_CHANNEL_2:
01962     {
01963       /* Enable the TIM Capture/Compare 2 interrupt */
01964       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
01965       break;
01966     }
01967
01968     case TIM_CHANNEL_3:
01969     {
01970       /* Enable the TIM Capture/Compare 3 interrupt */
01971       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
01972       break;
01973     }
01974
01975     case TIM_CHANNEL_4:
01976     {
01977       /* Enable the TIM Capture/Compare 4 interrupt */
01978       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
01979       break;
01980     }
01981
01982     default:
01983       break;
01984   }
01985   /* Enable the Input Capture channel */
01986   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01987
01988   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
01989   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
01990   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
01991   {
01992     __HAL_TIM_ENABLE(htim);
01993   }
01994
01995   /* Return function status */
01996   return HAL_OK;
01997 }
01998
01999 /**
02000   * @brief  Stops the TIM Input Capture measurement in interrupt mode.
02001   * @param  htim TIM Input Capture handle
02002   * @param  Channel TIM Channels to be disabled
02003   *          This parameter can be one of the following values:
02004   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02005   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02006   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
02007   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
02008   * @retval HAL status
02009   */
02010 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
02011 {
02012   /* Check the parameters */
02013   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
02014
02015   switch (Channel)
02016   {
02017     case TIM_CHANNEL_1:
02018     {
02019       /* Disable the TIM Capture/Compare 1 interrupt */
02020       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
02021       break;
02022     }
02023
02024     case TIM_CHANNEL_2:
02025     {
02026       /* Disable the TIM Capture/Compare 2 interrupt */
02027       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
02028       break;
02029     }
02030
02031     case TIM_CHANNEL_3:
02032     {
02033       /* Disable the TIM Capture/Compare 3 interrupt */
02034       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
02035       break;
02036     }
02037
02038     case TIM_CHANNEL_4:
02039     {
02040       /* Disable the TIM Capture/Compare 4 interrupt */
02041       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
02042       break;
02043     }
02044
02045     default:
02046       break;
02047   }
02048
02049   /* Disable the Input Capture channel */
02050   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
02051
02052   /* Disable the Peripheral */
02053   __HAL_TIM_DISABLE(htim);
02054
02055   /* Return function status */
02056   return HAL_OK;
02057 }
02058
02059 /**
02060   * @brief  Starts the TIM Input Capture measurement in DMA mode.
02061   * @param  htim TIM Input Capture handle
02062   * @param  Channel TIM Channels to be enabled
02063   *          This parameter can be one of the following values:
02064   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02065   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02066   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
02067   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
02068   * @param  pData The destination Buffer address.
02069   * @param  Length The length of data to be transferred from TIM peripheral to memory.
02070   * @retval HAL status
02071   */
02072 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
02073 {
02074   uint32_t tmpsmcr;
02075
02076   /* Check the parameters */
02077   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
02078   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
02079
02080   if (htim->State == HAL_TIM_STATE_BUSY)
02081   {
02082     return HAL_BUSY;
02083   }
02084   else if (htim->State == HAL_TIM_STATE_READY)
02085   {
02086     if ((pData == NULL) && (Length > 0U))
02087     {
02088       return HAL_ERROR;
02089     }
02090     else
02091     {
02092       htim->State = HAL_TIM_STATE_BUSY;
02093     }
02094   }
02095   else
02096   {
02097     /* nothing to do */
02098   }
02099
02100   switch (Channel)
02101   {
02102     case TIM_CHANNEL_1:
02103     {
02104       /* Set the DMA capture callbacks */
02105       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
02106       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
02107
02108       /* Set the DMA error callback */
02109       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
02110
02111       /* Enable the DMA channel */
02112       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
02113       {
02114         return HAL_ERROR;
02115       }
02116       /* Enable the TIM Capture/Compare 1 DMA request */
02117       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
02118       break;
02119     }
02120
02121     case TIM_CHANNEL_2:
02122     {
02123       /* Set the DMA capture callbacks */
02124       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
02125       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
02126
02127       /* Set the DMA error callback */
02128       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
02129
02130       /* Enable the DMA channel */
02131       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
02132       {
02133         return HAL_ERROR;
02134       }
02135       /* Enable the TIM Capture/Compare 2  DMA request */
02136       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
02137       break;
02138     }
02139
02140     case TIM_CHANNEL_3:
02141     {
02142       /* Set the DMA capture callbacks */
02143       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
02144       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
02145
02146       /* Set the DMA error callback */
02147       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
02148
02149       /* Enable the DMA channel */
02150       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)
02151       {
02152         return HAL_ERROR;
02153       }
02154       /* Enable the TIM Capture/Compare 3  DMA request */
02155       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
02156       break;
02157     }
02158
02159     case TIM_CHANNEL_4:
02160     {
02161       /* Set the DMA capture callbacks */
02162       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
02163       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
02164
02165       /* Set the DMA error callback */
02166       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
02167
02168       /* Enable the DMA channel */
02169       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)
02170       {
02171         return HAL_ERROR;
02172       }
02173       /* Enable the TIM Capture/Compare 4  DMA request */
02174       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
02175       break;
02176     }
02177
02178     default:
02179       break;
02180   }
02181
02182   /* Enable the Input Capture channel */
02183   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
02184
02185   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
02186   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
02187   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
02188   {
02189     __HAL_TIM_ENABLE(htim);
02190   }
02191
02192   /* Return function status */
02193   return HAL_OK;
02194 }
02195
02196 /**
02197   * @brief  Stops the TIM Input Capture measurement in DMA mode.
02198   * @param  htim TIM Input Capture handle
02199   * @param  Channel TIM Channels to be disabled
02200   *          This parameter can be one of the following values:
02201   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02202   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02203   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
02204   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
02205   * @retval HAL status
02206   */
02207 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
02208 {
02209   /* Check the parameters */
02210   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
02211   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
02212
02213   switch (Channel)
02214   {
02215     case TIM_CHANNEL_1:
02216     {
02217       /* Disable the TIM Capture/Compare 1 DMA request */
02218       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
02219       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
02220       break;
02221     }
02222
02223     case TIM_CHANNEL_2:
02224     {
02225       /* Disable the TIM Capture/Compare 2 DMA request */
02226       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
02227       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
02228       break;
02229     }
02230
02231     case TIM_CHANNEL_3:
02232     {
02233       /* Disable the TIM Capture/Compare 3  DMA request */
02234       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
02235       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
02236       break;
02237     }
02238
02239     case TIM_CHANNEL_4:
02240     {
02241       /* Disable the TIM Capture/Compare 4  DMA request */
02242       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
02243       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
02244       break;
02245     }
02246
02247     default:
02248       break;
02249   }
02250
02251   /* Disable the Input Capture channel */
02252   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
02253
02254   /* Disable the Peripheral */
02255   __HAL_TIM_DISABLE(htim);
02256
02257   /* Change the htim state */
02258   htim->State = HAL_TIM_STATE_READY;
02259
02260   /* Return function status */
02261   return HAL_OK;
02262 }
02263 /**
02264   * @}
02265   */
02266
02267 /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
02268   *  @brief    TIM One Pulse functions
02269   *
02270 @verbatim
02271   ==============================================================================
02272                         ##### TIM One Pulse functions #####
02273   ==============================================================================
02274   [..]
02275     This section provides functions allowing to:
02276     (+) Initialize and configure the TIM One Pulse.
02277     (+) De-initialize the TIM One Pulse.
02278     (+) Start the TIM One Pulse.
02279     (+) Stop the TIM One Pulse.
02280     (+) Start the TIM One Pulse and enable interrupt.
02281     (+) Stop the TIM One Pulse and disable interrupt.
02282     (+) Start the TIM One Pulse and enable DMA transfer.
02283     (+) Stop the TIM One Pulse and disable DMA transfer.
02284
02285 @endverbatim
02286   * @{
02287   */
02288 /**
02289   * @brief  Initializes the TIM One Pulse Time Base according to the specified
02290   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
02291   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
02292   *         requires a timer reset to avoid unexpected direction
02293   *         due to DIR bit readonly in center aligned mode.
02294   *         Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
02295   * @param  htim TIM One Pulse handle
02296   * @param  OnePulseMode Select the One pulse mode.
02297   *         This parameter can be one of the following values:
02298   *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
02299   *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
02300   * @retval HAL status
02301   */
02302 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
02303 {
02304   /* Check the TIM handle allocation */
02305   if (htim == NULL)
02306   {
02307     return HAL_ERROR;
02308   }
02309
02310   /* Check the parameters */
02311   assert_param(IS_TIM_INSTANCE(htim->Instance));
02312   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
02313   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
02314   assert_param(IS_TIM_OPM_MODE(OnePulseMode));
02315   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
02316
02317   if (htim->State == HAL_TIM_STATE_RESET)
02318   {
02319     /* Allocate lock resource and initialize it */
02320     htim->Lock = HAL_UNLOCKED;
02321
02322 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
02323     /* Reset interrupt callbacks to legacy weak callbacks */
02324     TIM_ResetCallback(htim);
02325
02326     if (htim->OnePulse_MspInitCallback == NULL)
02327     {
02328       htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
02329     }
02330     /* Init the low level hardware : GPIO, CLOCK, NVIC */
02331     htim->OnePulse_MspInitCallback(htim);
02332 #else
02333     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
02334     HAL_TIM_OnePulse_MspInit(htim);
02335 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
02336   }
02337
02338   /* Set the TIM state */
02339   htim->State = HAL_TIM_STATE_BUSY;
02340
02341   /* Configure the Time base in the One Pulse Mode */
02342   TIM_Base_SetConfig(htim->Instance, &htim->Init);
02343
02344   /* Reset the OPM Bit */
02345   htim->Instance->CR1 &= ~TIM_CR1_OPM;
02346
02347   /* Configure the OPM Mode */
02348   htim->Instance->CR1 |= OnePulseMode;
02349
02350   /* Initialize the TIM state*/
02351   htim->State = HAL_TIM_STATE_READY;
02352
02353   return HAL_OK;
02354 }
02355
02356 /**
02357   * @brief  DeInitializes the TIM One Pulse
02358   * @param  htim TIM One Pulse handle
02359   * @retval HAL status
02360   */
02361 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
02362 {
02363   /* Check the parameters */
02364   assert_param(IS_TIM_INSTANCE(htim->Instance));
02365
02366   htim->State = HAL_TIM_STATE_BUSY;
02367
02368   /* Disable the TIM Peripheral Clock */
02369   __HAL_TIM_DISABLE(htim);
02370
02371 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
02372   if (htim->OnePulse_MspDeInitCallback == NULL)
02373   {
02374     htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
02375   }
02376   /* DeInit the low level hardware */
02377   htim->OnePulse_MspDeInitCallback(htim);
02378 #else
02379   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
02380   HAL_TIM_OnePulse_MspDeInit(htim);
02381 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
02382
02383   /* Change TIM state */
02384   htim->State = HAL_TIM_STATE_RESET;
02385
02386   /* Release Lock */
02387   __HAL_UNLOCK(htim);
02388
02389   return HAL_OK;
02390 }
02391
02392 /**
02393   * @brief  Initializes the TIM One Pulse MSP.
02394   * @param  htim TIM One Pulse handle
02395   * @retval None
02396   */
02397 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
02398 {
02399   /* Prevent unused argument(s) compilation warning */
02400   UNUSED(htim);
02401
02402   /* NOTE : This function should not be modified, when the callback is needed,
02403             the HAL_TIM_OnePulse_MspInit could be implemented in the user file
02404    */
02405 }
02406
02407 /**
02408   * @brief  DeInitializes TIM One Pulse MSP.
02409   * @param  htim TIM One Pulse handle
02410   * @retval None
02411   */
02412 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
02413 {
02414   /* Prevent unused argument(s) compilation warning */
02415   UNUSED(htim);
02416
02417   /* NOTE : This function should not be modified, when the callback is needed,
02418             the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
02419    */
02420 }
02421
02422 /**
02423   * @brief  Starts the TIM One Pulse signal generation.
02424   * @param  htim TIM One Pulse handle
02425   * @param  OutputChannel TIM Channels to be enabled
02426   *          This parameter can be one of the following values:
02427   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02428   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02429   * @retval HAL status
02430   */
02431 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02432 {
02433   /* Prevent unused argument(s) compilation warning */
02434   UNUSED(OutputChannel);
02435
02436   /* Enable the Capture compare and the Input Capture channels
02437     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02438     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02439     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02440     in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
02441
02442     No need to enable the counter, it's enabled automatically by hardware
02443     (the counter starts in response to a stimulus and generate a pulse */
02444
02445   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02446   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02447
02448   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
02449   {
02450     /* Enable the main output */
02451     __HAL_TIM_MOE_ENABLE(htim);
02452   }
02453
02454   /* Return function status */
02455   return HAL_OK;
02456 }
02457
02458 /**
02459   * @brief  Stops the TIM One Pulse signal generation.
02460   * @param  htim TIM One Pulse handle
02461   * @param  OutputChannel TIM Channels to be disable
02462   *          This parameter can be one of the following values:
02463   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02464   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02465   * @retval HAL status
02466   */
02467 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02468 {
02469   /* Prevent unused argument(s) compilation warning */
02470   UNUSED(OutputChannel);
02471
02472   /* Disable the Capture compare and the Input Capture channels
02473   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02474   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02475   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02476   in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
02477
02478   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02479   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02480
02481   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
02482   {
02483     /* Disable the Main Output */
02484     __HAL_TIM_MOE_DISABLE(htim);
02485   }
02486
02487   /* Disable the Peripheral */
02488   __HAL_TIM_DISABLE(htim);
02489
02490   /* Return function status */
02491   return HAL_OK;
02492 }
02493
02494 /**
02495   * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
02496   * @param  htim TIM One Pulse handle
02497   * @param  OutputChannel TIM Channels to be enabled
02498   *          This parameter can be one of the following values:
02499   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02500   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02501   * @retval HAL status
02502   */
02503 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02504 {
02505   /* Prevent unused argument(s) compilation warning */
02506   UNUSED(OutputChannel);
02507
02508   /* Enable the Capture compare and the Input Capture channels
02509     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02510     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02511     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02512     in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
02513
02514     No need to enable the counter, it's enabled automatically by hardware
02515     (the counter starts in response to a stimulus and generate a pulse */
02516
02517   /* Enable the TIM Capture/Compare 1 interrupt */
02518   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
02519
02520   /* Enable the TIM Capture/Compare 2 interrupt */
02521   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
02522
02523   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02524   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02525
02526   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
02527   {
02528     /* Enable the main output */
02529     __HAL_TIM_MOE_ENABLE(htim);
02530   }
02531
02532   /* Return function status */
02533   return HAL_OK;
02534 }
02535
02536 /**
02537   * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
02538   * @param  htim TIM One Pulse handle
02539   * @param  OutputChannel TIM Channels to be enabled
02540   *          This parameter can be one of the following values:
02541   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02542   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02543   * @retval HAL status
02544   */
02545 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02546 {
02547   /* Prevent unused argument(s) compilation warning */
02548   UNUSED(OutputChannel);
02549
02550   /* Disable the TIM Capture/Compare 1 interrupt */
02551   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
02552
02553   /* Disable the TIM Capture/Compare 2 interrupt */
02554   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
02555
02556   /* Disable the Capture compare and the Input Capture channels
02557   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02558   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02559   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02560   in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
02561   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02562   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02563
02564   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
02565   {
02566     /* Disable the Main Output */
02567     __HAL_TIM_MOE_DISABLE(htim);
02568   }
02569
02570   /* Disable the Peripheral */
02571   __HAL_TIM_DISABLE(htim);
02572
02573   /* Return function status */
02574   return HAL_OK;
02575 }
02576
02577 /**
02578   * @}
02579   */
02580
02581 /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
02582   *  @brief    TIM Encoder functions
02583   *
02584 @verbatim
02585   ==============================================================================
02586                           ##### TIM Encoder functions #####
02587   ==============================================================================
02588   [..]
02589     This section provides functions allowing to:
02590     (+) Initialize and configure the TIM Encoder.
02591     (+) De-initialize the TIM Encoder.
02592     (+) Start the TIM Encoder.
02593     (+) Stop the TIM Encoder.
02594     (+) Start the TIM Encoder and enable interrupt.
02595     (+) Stop the TIM Encoder and disable interrupt.
02596     (+) Start the TIM Encoder and enable DMA transfer.
02597     (+) Stop the TIM Encoder and disable DMA transfer.
02598
02599 @endverbatim
02600   * @{
02601   */
02602 /**
02603   * @brief  Initializes the TIM Encoder Interface and initialize the associated handle.
02604   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
02605   *         requires a timer reset to avoid unexpected direction
02606   *         due to DIR bit readonly in center aligned mode.
02607   *         Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
02608   * @note   Encoder mode and External clock mode 2 are not compatible and must not be selected together
02609   *         Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
02610   *         using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
02611   * @param  htim TIM Encoder Interface handle
02612   * @param  sConfig TIM Encoder Interface configuration structure
02613   * @retval HAL status
02614   */
02615 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig)
02616 {
02617   uint32_t tmpsmcr;
02618   uint32_t tmpccmr1;
02619   uint32_t tmpccer;
02620
02621   /* Check the TIM handle allocation */
02622   if (htim == NULL)
02623   {
02624     return HAL_ERROR;
02625   }
02626
02627   /* Check the parameters */
02628   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
02629   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
02630   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
02631   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02632   assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
02633   assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
02634   assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
02635   assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
02636   assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
02637   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
02638   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
02639   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
02640   assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
02641
02642   if (htim->State == HAL_TIM_STATE_RESET)
02643   {
02644     /* Allocate lock resource and initialize it */
02645     htim->Lock = HAL_UNLOCKED;
02646
02647 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
02648     /* Reset interrupt callbacks to legacy weak callbacks */
02649     TIM_ResetCallback(htim);
02650
02651     if (htim->Encoder_MspInitCallback == NULL)
02652     {
02653       htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
02654     }
02655     /* Init the low level hardware : GPIO, CLOCK, NVIC */
02656     htim->Encoder_MspInitCallback(htim);
02657 #else
02658     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
02659     HAL_TIM_Encoder_MspInit(htim);
02660 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
02661   }
02662
02663   /* Set the TIM state */
02664   htim->State = HAL_TIM_STATE_BUSY;
02665
02666   /* Reset the SMS and ECE bits */
02667   htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
02668
02669   /* Configure the Time base in the Encoder Mode */
02670   TIM_Base_SetConfig(htim->Instance, &htim->Init);
02671
02672   /* Get the TIMx SMCR register value */
02673   tmpsmcr = htim->Instance->SMCR;
02674
02675   /* Get the TIMx CCMR1 register value */
02676   tmpccmr1 = htim->Instance->CCMR1;
02677
02678   /* Get the TIMx CCER register value */
02679   tmpccer = htim->Instance->CCER;
02680
02681   /* Set the encoder Mode */
02682   tmpsmcr |= sConfig->EncoderMode;
02683
02684   /* Select the Capture Compare 1 and the Capture Compare 2 as input */
02685   tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
02686   tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
02687
02688   /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
02689   tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
02690   tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
02691   tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
02692   tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
02693
02694   /* Set the TI1 and the TI2 Polarities */
02695   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
02696   tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
02697   tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
02698
02699   /* Write to TIMx SMCR */
02700   htim->Instance->SMCR = tmpsmcr;
02701
02702   /* Write to TIMx CCMR1 */
02703   htim->Instance->CCMR1 = tmpccmr1;
02704
02705   /* Write to TIMx CCER */
02706   htim->Instance->CCER = tmpccer;
02707
02708   /* Initialize the TIM state*/
02709   htim->State = HAL_TIM_STATE_READY;
02710
02711   return HAL_OK;
02712 }
02713
02714
02715 /**
02716   * @brief  DeInitializes the TIM Encoder interface
02717   * @param  htim TIM Encoder Interface handle
02718   * @retval HAL status
02719   */
02720 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
02721 {
02722   /* Check the parameters */
02723   assert_param(IS_TIM_INSTANCE(htim->Instance));
02724
02725   htim->State = HAL_TIM_STATE_BUSY;
02726
02727   /* Disable the TIM Peripheral Clock */
02728   __HAL_TIM_DISABLE(htim);
02729
02730 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
02731   if (htim->Encoder_MspDeInitCallback == NULL)
02732   {
02733     htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
02734   }
02735   /* DeInit the low level hardware */
02736   htim->Encoder_MspDeInitCallback(htim);
02737 #else
02738   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
02739   HAL_TIM_Encoder_MspDeInit(htim);
02740 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
02741
02742   /* Change TIM state */
02743   htim->State = HAL_TIM_STATE_RESET;
02744
02745   /* Release Lock */
02746   __HAL_UNLOCK(htim);
02747
02748   return HAL_OK;
02749 }
02750
02751 /**
02752   * @brief  Initializes the TIM Encoder Interface MSP.
02753   * @param  htim TIM Encoder Interface handle
02754   * @retval None
02755   */
02756 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
02757 {
02758   /* Prevent unused argument(s) compilation warning */
02759   UNUSED(htim);
02760
02761   /* NOTE : This function should not be modified, when the callback is needed,
02762             the HAL_TIM_Encoder_MspInit could be implemented in the user file
02763    */
02764 }
02765
02766 /**
02767   * @brief  DeInitializes TIM Encoder Interface MSP.
02768   * @param  htim TIM Encoder Interface handle
02769   * @retval None
02770   */
02771 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
02772 {
02773   /* Prevent unused argument(s) compilation warning */
02774   UNUSED(htim);
02775
02776   /* NOTE : This function should not be modified, when the callback is needed,
02777             the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
02778    */
02779 }
02780
02781 /**
02782   * @brief  Starts the TIM Encoder Interface.
02783   * @param  htim TIM Encoder Interface handle
02784   * @param  Channel TIM Channels to be enabled
02785   *          This parameter can be one of the following values:
02786   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02787   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02788   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02789   * @retval HAL status
02790   */
02791 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
02792 {
02793   /* Check the parameters */
02794   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02795
02796   /* Enable the encoder interface channels */
02797   switch (Channel)
02798   {
02799     case TIM_CHANNEL_1:
02800     {
02801       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02802       break;
02803     }
02804
02805     case TIM_CHANNEL_2:
02806     {
02807       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02808       break;
02809     }
02810
02811     default :
02812     {
02813       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02814       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02815       break;
02816     }
02817   }
02818   /* Enable the Peripheral */
02819   __HAL_TIM_ENABLE(htim);
02820
02821   /* Return function status */
02822   return HAL_OK;
02823 }
02824
02825 /**
02826   * @brief  Stops the TIM Encoder Interface.
02827   * @param  htim TIM Encoder Interface handle
02828   * @param  Channel TIM Channels to be disabled
02829   *          This parameter can be one of the following values:
02830   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02831   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02832   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02833   * @retval HAL status
02834   */
02835 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
02836 {
02837   /* Check the parameters */
02838   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02839
02840   /* Disable the Input Capture channels 1 and 2
02841     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
02842   switch (Channel)
02843   {
02844     case TIM_CHANNEL_1:
02845     {
02846       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02847       break;
02848     }
02849
02850     case TIM_CHANNEL_2:
02851     {
02852       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02853       break;
02854     }
02855
02856     default :
02857     {
02858       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02859       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02860       break;
02861     }
02862   }
02863
02864   /* Disable the Peripheral */
02865   __HAL_TIM_DISABLE(htim);
02866
02867   /* Return function status */
02868   return HAL_OK;
02869 }
02870
02871 /**
02872   * @brief  Starts the TIM Encoder Interface in interrupt mode.
02873   * @param  htim TIM Encoder Interface handle
02874   * @param  Channel TIM Channels to be enabled
02875   *          This parameter can be one of the following values:
02876   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02877   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02878   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02879   * @retval HAL status
02880   */
02881 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
02882 {
02883   /* Check the parameters */
02884   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02885
02886   /* Enable the encoder interface channels */
02887   /* Enable the capture compare Interrupts 1 and/or 2 */
02888   switch (Channel)
02889   {
02890     case TIM_CHANNEL_1:
02891     {
02892       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02893       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
02894       break;
02895     }
02896
02897     case TIM_CHANNEL_2:
02898     {
02899       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02900       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
02901       break;
02902     }
02903
02904     default :
02905     {
02906       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02907       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02908       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
02909       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
02910       break;
02911     }
02912   }
02913
02914   /* Enable the Peripheral */
02915   __HAL_TIM_ENABLE(htim);
02916
02917   /* Return function status */
02918   return HAL_OK;
02919 }
02920
02921 /**
02922   * @brief  Stops the TIM Encoder Interface in interrupt mode.
02923   * @param  htim TIM Encoder Interface handle
02924   * @param  Channel TIM Channels to be disabled
02925   *          This parameter can be one of the following values:
02926   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02927   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02928   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02929   * @retval HAL status
02930   */
02931 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
02932 {
02933   /* Check the parameters */
02934   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02935
02936   /* Disable the Input Capture channels 1 and 2
02937     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
02938   if (Channel == TIM_CHANNEL_1)
02939   {
02940     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02941
02942     /* Disable the capture compare Interrupts 1 */
02943     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
02944   }
02945   else if (Channel == TIM_CHANNEL_2)
02946   {
02947     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02948
02949     /* Disable the capture compare Interrupts 2 */
02950     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
02951   }
02952   else
02953   {
02954     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02955     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02956
02957     /* Disable the capture compare Interrupts 1 and 2 */
02958     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
02959     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
02960   }
02961
02962   /* Disable the Peripheral */
02963   __HAL_TIM_DISABLE(htim);
02964
02965   /* Change the htim state */
02966   htim->State = HAL_TIM_STATE_READY;
02967
02968   /* Return function status */
02969   return HAL_OK;
02970 }
02971
02972 /**
02973   * @brief  Starts the TIM Encoder Interface in DMA mode.
02974   * @param  htim TIM Encoder Interface handle
02975   * @param  Channel TIM Channels to be enabled
02976   *          This parameter can be one of the following values:
02977   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02978   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02979   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02980   * @param  pData1 The destination Buffer address for IC1.
02981   * @param  pData2 The destination Buffer address for IC2.
02982   * @param  Length The length of data to be transferred from TIM peripheral to memory.
02983   * @retval HAL status
02984   */
02985 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
02986                                             uint32_t *pData2, uint16_t Length)
02987 {
02988   /* Check the parameters */
02989   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
02990
02991   if (htim->State == HAL_TIM_STATE_BUSY)
02992   {
02993     return HAL_BUSY;
02994   }
02995   else if (htim->State == HAL_TIM_STATE_READY)
02996   {
02997     if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
02998     {
02999       return HAL_ERROR;
03000     }
03001     else
03002     {
03003       htim->State = HAL_TIM_STATE_BUSY;
03004     }
03005   }
03006   else
03007   {
03008     /* nothing to do */
03009   }
03010
03011   switch (Channel)
03012   {
03013     case TIM_CHANNEL_1:
03014     {
03015       /* Set the DMA capture callbacks */
03016       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
03017       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
03018
03019       /* Set the DMA error callback */
03020       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
03021
03022       /* Enable the DMA channel */
03023       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
03024       {
03025         return HAL_ERROR;
03026       }
03027       /* Enable the TIM Input Capture DMA request */
03028       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
03029
03030       /* Enable the Peripheral */
03031       __HAL_TIM_ENABLE(htim);
03032
03033       /* Enable the Capture compare channel */
03034       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
03035       break;
03036     }
03037
03038     case TIM_CHANNEL_2:
03039     {
03040       /* Set the DMA capture callbacks */
03041       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
03042       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
03043
03044       /* Set the DMA error callback */
03045       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
03046       /* Enable the DMA channel */
03047       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
03048       {
03049         return HAL_ERROR;
03050       }
03051       /* Enable the TIM Input Capture  DMA request */
03052       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
03053
03054       /* Enable the Peripheral */
03055       __HAL_TIM_ENABLE(htim);
03056
03057       /* Enable the Capture compare channel */
03058       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
03059       break;
03060     }
03061
03062     case TIM_CHANNEL_ALL:
03063     {
03064       /* Set the DMA capture callbacks */
03065       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
03066       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
03067
03068       /* Set the DMA error callback */
03069       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
03070
03071       /* Enable the DMA channel */
03072       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
03073       {
03074         return HAL_ERROR;
03075       }
03076
03077       /* Set the DMA capture callbacks */
03078       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
03079       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
03080
03081       /* Set the DMA error callback */
03082       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
03083
03084       /* Enable the DMA channel */
03085       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
03086       {
03087         return HAL_ERROR;
03088       }
03089       /* Enable the Peripheral */
03090       __HAL_TIM_ENABLE(htim);
03091
03092       /* Enable the Capture compare channel */
03093       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
03094       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
03095
03096       /* Enable the TIM Input Capture  DMA request */
03097       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
03098       /* Enable the TIM Input Capture  DMA request */
03099       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
03100       break;
03101     }
03102
03103     default:
03104       break;
03105   }
03106   /* Return function status */
03107   return HAL_OK;
03108 }
03109
03110 /**
03111   * @brief  Stops the TIM Encoder Interface in DMA mode.
03112   * @param  htim TIM Encoder Interface handle
03113   * @param  Channel TIM Channels to be enabled
03114   *          This parameter can be one of the following values:
03115   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03116   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03117   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
03118   * @retval HAL status
03119   */
03120 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
03121 {
03122   /* Check the parameters */
03123   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
03124
03125   /* Disable the Input Capture channels 1 and 2
03126     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
03127   if (Channel == TIM_CHANNEL_1)
03128   {
03129     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
03130
03131     /* Disable the capture compare DMA Request 1 */
03132     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
03133     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
03134   }
03135   else if (Channel == TIM_CHANNEL_2)
03136   {
03137     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
03138
03139     /* Disable the capture compare DMA Request 2 */
03140     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
03141     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
03142   }
03143   else
03144   {
03145     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
03146     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
03147
03148     /* Disable the capture compare DMA Request 1 and 2 */
03149     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
03150     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
03151     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
03152     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
03153   }
03154
03155   /* Disable the Peripheral */
03156   __HAL_TIM_DISABLE(htim);
03157
03158   /* Change the htim state */
03159   htim->State = HAL_TIM_STATE_READY;
03160
03161   /* Return function status */
03162   return HAL_OK;
03163 }
03164
03165 /**
03166   * @}
03167   */
03168 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
03169   *  @brief    TIM IRQ handler management
03170   *
03171 @verbatim
03172   ==============================================================================
03173                         ##### IRQ handler management #####
03174   ==============================================================================
03175   [..]
03176     This section provides Timer IRQ handler function.
03177
03178 @endverbatim
03179   * @{
03180   */
03181 /**
03182   * @brief  This function handles TIM interrupts requests.
03183   * @param  htim TIM  handle
03184   * @retval None
03185   */
03186 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
03187 {
03188   /* Capture compare 1 event */
03189   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
03190   {
03191     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
03192     {
03193       {
03194         __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
03195         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
03196
03197         /* Input capture event */
03198         if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
03199         {
03200 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03201           htim->IC_CaptureCallback(htim);
03202 #else
03203           HAL_TIM_IC_CaptureCallback(htim);
03204 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03205         }
03206         /* Output compare event */
03207         else
03208         {
03209 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03210           htim->OC_DelayElapsedCallback(htim);
03211           htim->PWM_PulseFinishedCallback(htim);
03212 #else
03213           HAL_TIM_OC_DelayElapsedCallback(htim);
03214           HAL_TIM_PWM_PulseFinishedCallback(htim);
03215 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03216         }
03217         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
03218       }
03219     }
03220   }
03221   /* Capture compare 2 event */
03222   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
03223   {
03224     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
03225     {
03226       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
03227       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
03228       /* Input capture event */
03229       if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
03230       {
03231 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03232         htim->IC_CaptureCallback(htim);
03233 #else
03234         HAL_TIM_IC_CaptureCallback(htim);
03235 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03236       }
03237       /* Output compare event */
03238       else
03239       {
03240 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03241         htim->OC_DelayElapsedCallback(htim);
03242         htim->PWM_PulseFinishedCallback(htim);
03243 #else
03244         HAL_TIM_OC_DelayElapsedCallback(htim);
03245         HAL_TIM_PWM_PulseFinishedCallback(htim);
03246 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03247       }
03248       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
03249     }
03250   }
03251   /* Capture compare 3 event */
03252   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
03253   {
03254     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
03255     {
03256       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
03257       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
03258       /* Input capture event */
03259       if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
03260       {
03261 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03262         htim->IC_CaptureCallback(htim);
03263 #else
03264         HAL_TIM_IC_CaptureCallback(htim);
03265 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03266       }
03267       /* Output compare event */
03268       else
03269       {
03270 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03271         htim->OC_DelayElapsedCallback(htim);
03272         htim->PWM_PulseFinishedCallback(htim);
03273 #else
03274         HAL_TIM_OC_DelayElapsedCallback(htim);
03275         HAL_TIM_PWM_PulseFinishedCallback(htim);
03276 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03277       }
03278       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
03279     }
03280   }
03281   /* Capture compare 4 event */
03282   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
03283   {
03284     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
03285     {
03286       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
03287       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
03288       /* Input capture event */
03289       if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
03290       {
03291 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03292         htim->IC_CaptureCallback(htim);
03293 #else
03294         HAL_TIM_IC_CaptureCallback(htim);
03295 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03296       }
03297       /* Output compare event */
03298       else
03299       {
03300 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03301         htim->OC_DelayElapsedCallback(htim);
03302         htim->PWM_PulseFinishedCallback(htim);
03303 #else
03304         HAL_TIM_OC_DelayElapsedCallback(htim);
03305         HAL_TIM_PWM_PulseFinishedCallback(htim);
03306 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03307       }
03308       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
03309     }
03310   }
03311   /* TIM Update event */
03312   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
03313   {
03314     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
03315     {
03316       __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
03317 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03318       htim->PeriodElapsedCallback(htim);
03319 #else
03320       HAL_TIM_PeriodElapsedCallback(htim);
03321 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03322     }
03323   }
03324   /* TIM Break input event */
03325   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
03326   {
03327     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
03328     {
03329       __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
03330 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03331       htim->BreakCallback(htim);
03332 #else
03333       HAL_TIMEx_BreakCallback(htim);
03334 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03335     }
03336   }
03337   /* TIM Break2 input event */
03338   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
03339   {
03340     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
03341     {
03342       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
03343 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03344       htim->Break2Callback(htim);
03345 #else
03346       HAL_TIMEx_Break2Callback(htim);
03347 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03348     }
03349   }
03350   /* TIM Trigger detection event */
03351   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
03352   {
03353     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
03354     {
03355       __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
03356 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03357       htim->TriggerCallback(htim);
03358 #else
03359       HAL_TIM_TriggerCallback(htim);
03360 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03361     }
03362   }
03363   /* TIM commutation event */
03364   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
03365   {
03366     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
03367     {
03368       __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
03369 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
03370       htim->CommutationCallback(htim);
03371 #else
03372       HAL_TIMEx_CommutCallback(htim);
03373 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
03374     }
03375   }
03376 }
03377
03378 /**
03379   * @}
03380   */
03381
03382 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
03383   *  @brief    TIM Peripheral Control functions
03384   *
03385 @verbatim
03386   ==============================================================================
03387                    ##### Peripheral Control functions #####
03388   ==============================================================================
03389  [..]
03390    This section provides functions allowing to:
03391       (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
03392       (+) Configure External Clock source.
03393       (+) Configure Complementary channels, break features and dead time.
03394       (+) Configure Master and the Slave synchronization.
03395       (+) Configure the DMA Burst Mode.
03396
03397 @endverbatim
03398   * @{
03399   */
03400
03401 /**
03402   * @brief  Initializes the TIM Output Compare Channels according to the specified
03403   *         parameters in the TIM_OC_InitTypeDef.
03404   * @param  htim TIM Output Compare handle
03405   * @param  sConfig TIM Output Compare configuration structure
03406   * @param  Channel TIM Channels to configure
03407   *          This parameter can be one of the following values:
03408   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03409   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03410   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
03411   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
03412   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
03413   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
03414   * @retval HAL status
03415   */
03416 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
03417                                            TIM_OC_InitTypeDef *sConfig,
03418                                            uint32_t Channel)
03419 {
03420   /* Check the parameters */
03421   assert_param(IS_TIM_CHANNELS(Channel));
03422   assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
03423   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
03424
03425   /* Process Locked */
03426   __HAL_LOCK(htim);
03427
03428   htim->State = HAL_TIM_STATE_BUSY;
03429
03430   switch (Channel)
03431   {
03432     case TIM_CHANNEL_1:
03433     {
03434       /* Check the parameters */
03435       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03436
03437       /* Configure the TIM Channel 1 in Output Compare */
03438       TIM_OC1_SetConfig(htim->Instance, sConfig);
03439       break;
03440     }
03441
03442     case TIM_CHANNEL_2:
03443     {
03444       /* Check the parameters */
03445       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03446
03447       /* Configure the TIM Channel 2 in Output Compare */
03448       TIM_OC2_SetConfig(htim->Instance, sConfig);
03449       break;
03450     }
03451
03452     case TIM_CHANNEL_3:
03453     {
03454       /* Check the parameters */
03455       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
03456
03457       /* Configure the TIM Channel 3 in Output Compare */
03458       TIM_OC3_SetConfig(htim->Instance, sConfig);
03459       break;
03460     }
03461
03462     case TIM_CHANNEL_4:
03463     {
03464       /* Check the parameters */
03465       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
03466
03467       /* Configure the TIM Channel 4 in Output Compare */
03468       TIM_OC4_SetConfig(htim->Instance, sConfig);
03469       break;
03470     }
03471
03472     case TIM_CHANNEL_5:
03473     {
03474       /* Check the parameters */
03475       assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
03476
03477       /* Configure the TIM Channel 5 in Output Compare */
03478       TIM_OC5_SetConfig(htim->Instance, sConfig);
03479       break;
03480     }
03481
03482     case TIM_CHANNEL_6:
03483     {
03484       /* Check the parameters */
03485       assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
03486
03487       /* Configure the TIM Channel 6 in Output Compare */
03488       TIM_OC6_SetConfig(htim->Instance, sConfig);
03489       break;
03490     }
03491
03492     default:
03493       break;
03494   }
03495
03496   htim->State = HAL_TIM_STATE_READY;
03497
03498   __HAL_UNLOCK(htim);
03499
03500   return HAL_OK;
03501 }
03502
03503 /**
03504   * @brief  Initializes the TIM Input Capture Channels according to the specified
03505   *         parameters in the TIM_IC_InitTypeDef.
03506   * @param  htim TIM IC handle
03507   * @param  sConfig TIM Input Capture configuration structure
03508   * @param  Channel TIM Channel to configure
03509   *          This parameter can be one of the following values:
03510   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03511   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03512   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
03513   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
03514   * @retval HAL status
03515   */
03516 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
03517 {
03518   /* Check the parameters */
03519   assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03520   assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
03521   assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
03522   assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
03523   assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
03524
03525   /* Process Locked */
03526   __HAL_LOCK(htim);
03527
03528   htim->State = HAL_TIM_STATE_BUSY;
03529
03530   if (Channel == TIM_CHANNEL_1)
03531   {
03532     /* TI1 Configuration */
03533     TIM_TI1_SetConfig(htim->Instance,
03534                       sConfig->ICPolarity,
03535                       sConfig->ICSelection,
03536                       sConfig->ICFilter);
03537
03538     /* Reset the IC1PSC Bits */
03539     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
03540
03541     /* Set the IC1PSC value */
03542     htim->Instance->CCMR1 |= sConfig->ICPrescaler;
03543   }
03544   else if (Channel == TIM_CHANNEL_2)
03545   {
03546     /* TI2 Configuration */
03547     assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03548
03549     TIM_TI2_SetConfig(htim->Instance,
03550                       sConfig->ICPolarity,
03551                       sConfig->ICSelection,
03552                       sConfig->ICFilter);
03553
03554     /* Reset the IC2PSC Bits */
03555     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
03556
03557     /* Set the IC2PSC value */
03558     htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
03559   }
03560   else if (Channel == TIM_CHANNEL_3)
03561   {
03562     /* TI3 Configuration */
03563     assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
03564
03565     TIM_TI3_SetConfig(htim->Instance,
03566                       sConfig->ICPolarity,
03567                       sConfig->ICSelection,
03568                       sConfig->ICFilter);
03569
03570     /* Reset the IC3PSC Bits */
03571     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
03572
03573     /* Set the IC3PSC value */
03574     htim->Instance->CCMR2 |= sConfig->ICPrescaler;
03575   }
03576   else
03577   {
03578     /* TI4 Configuration */
03579     assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
03580
03581     TIM_TI4_SetConfig(htim->Instance,
03582                       sConfig->ICPolarity,
03583                       sConfig->ICSelection,
03584                       sConfig->ICFilter);
03585
03586     /* Reset the IC4PSC Bits */
03587     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
03588
03589     /* Set the IC4PSC value */
03590     htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
03591   }
03592
03593   htim->State = HAL_TIM_STATE_READY;
03594
03595   __HAL_UNLOCK(htim);
03596
03597   return HAL_OK;
03598 }
03599
03600 /**
03601   * @brief  Initializes the TIM PWM  channels according to the specified
03602   *         parameters in the TIM_OC_InitTypeDef.
03603   * @param  htim TIM PWM handle
03604   * @param  sConfig TIM PWM configuration structure
03605   * @param  Channel TIM Channels to be configured
03606   *          This parameter can be one of the following values:
03607   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03608   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03609   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
03610   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
03611   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
03612   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
03613   * @retval HAL status
03614   */
03615 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
03616                                             TIM_OC_InitTypeDef *sConfig,
03617                                             uint32_t Channel)
03618 {
03619   /* Check the parameters */
03620   assert_param(IS_TIM_CHANNELS(Channel));
03621   assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
03622   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
03623   assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
03624
03625   /* Process Locked */
03626   __HAL_LOCK(htim);
03627
03628   htim->State = HAL_TIM_STATE_BUSY;
03629
03630   switch (Channel)
03631   {
03632     case TIM_CHANNEL_1:
03633     {
03634       /* Check the parameters */
03635       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03636
03637       /* Configure the Channel 1 in PWM mode */
03638       TIM_OC1_SetConfig(htim->Instance, sConfig);
03639
03640       /* Set the Preload enable bit for channel1 */
03641       htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
03642
03643       /* Configure the Output Fast mode */
03644       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
03645       htim->Instance->CCMR1 |= sConfig->OCFastMode;
03646       break;
03647     }
03648
03649     case TIM_CHANNEL_2:
03650     {
03651       /* Check the parameters */
03652       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03653
03654       /* Configure the Channel 2 in PWM mode */
03655       TIM_OC2_SetConfig(htim->Instance, sConfig);
03656
03657       /* Set the Preload enable bit for channel2 */
03658       htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
03659
03660       /* Configure the Output Fast mode */
03661       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
03662       htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
03663       break;
03664     }
03665
03666     case TIM_CHANNEL_3:
03667     {
03668       /* Check the parameters */
03669       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
03670
03671       /* Configure the Channel 3 in PWM mode */
03672       TIM_OC3_SetConfig(htim->Instance, sConfig);
03673
03674       /* Set the Preload enable bit for channel3 */
03675       htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
03676
03677       /* Configure the Output Fast mode */
03678       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
03679       htim->Instance->CCMR2 |= sConfig->OCFastMode;
03680       break;
03681     }
03682
03683     case TIM_CHANNEL_4:
03684     {
03685       /* Check the parameters */
03686       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
03687
03688       /* Configure the Channel 4 in PWM mode */
03689       TIM_OC4_SetConfig(htim->Instance, sConfig);
03690
03691       /* Set the Preload enable bit for channel4 */
03692       htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
03693
03694       /* Configure the Output Fast mode */
03695       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
03696       htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
03697       break;
03698     }
03699
03700     case TIM_CHANNEL_5:
03701     {
03702       /* Check the parameters */
03703       assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
03704
03705       /* Configure the Channel 5 in PWM mode */
03706       TIM_OC5_SetConfig(htim->Instance, sConfig);
03707
03708       /* Set the Preload enable bit for channel5*/
03709       htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
03710
03711       /* Configure the Output Fast mode */
03712       htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
03713       htim->Instance->CCMR3 |= sConfig->OCFastMode;
03714       break;
03715     }
03716
03717     case TIM_CHANNEL_6:
03718     {
03719       /* Check the parameters */
03720       assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
03721
03722       /* Configure the Channel 6 in PWM mode */
03723       TIM_OC6_SetConfig(htim->Instance, sConfig);
03724
03725       /* Set the Preload enable bit for channel6 */
03726       htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
03727
03728       /* Configure the Output Fast mode */
03729       htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
03730       htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
03731       break;
03732     }
03733
03734     default:
03735       break;
03736   }
03737
03738   htim->State = HAL_TIM_STATE_READY;
03739
03740   __HAL_UNLOCK(htim);
03741
03742   return HAL_OK;
03743 }
03744
03745 /**
03746   * @brief  Initializes the TIM One Pulse Channels according to the specified
03747   *         parameters in the TIM_OnePulse_InitTypeDef.
03748   * @param  htim TIM One Pulse handle
03749   * @param  sConfig TIM One Pulse configuration structure
03750   * @param  OutputChannel TIM output channel to configure
03751   *          This parameter can be one of the following values:
03752   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03753   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03754   * @param  InputChannel TIM input Channel to configure
03755   *          This parameter can be one of the following values:
03756   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03757   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03758   * @note  To output a waveform with a minimum delay user can enable the fast
03759   *        mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
03760   *        output is forced in response to the edge detection on TIx input,
03761   *        without taking in account the comparison.
03762   * @retval HAL status
03763   */
03764 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef *sConfig,
03765                                                  uint32_t OutputChannel,  uint32_t InputChannel)
03766 {
03767   TIM_OC_InitTypeDef temp1;
03768
03769   /* Check the parameters */
03770   assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
03771   assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
03772
03773   if (OutputChannel != InputChannel)
03774   {
03775     /* Process Locked */
03776     __HAL_LOCK(htim);
03777
03778     htim->State = HAL_TIM_STATE_BUSY;
03779
03780     /* Extract the Output compare configuration from sConfig structure */
03781     temp1.OCMode = sConfig->OCMode;
03782     temp1.Pulse = sConfig->Pulse;
03783     temp1.OCPolarity = sConfig->OCPolarity;
03784     temp1.OCNPolarity = sConfig->OCNPolarity;
03785     temp1.OCIdleState = sConfig->OCIdleState;
03786     temp1.OCNIdleState = sConfig->OCNIdleState;
03787
03788     switch (OutputChannel)
03789     {
03790       case TIM_CHANNEL_1:
03791       {
03792         assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03793
03794         TIM_OC1_SetConfig(htim->Instance, &temp1);
03795         break;
03796       }
03797       case TIM_CHANNEL_2:
03798       {
03799         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03800
03801         TIM_OC2_SetConfig(htim->Instance, &temp1);
03802         break;
03803       }
03804       default:
03805         break;
03806     }
03807
03808     switch (InputChannel)
03809     {
03810       case TIM_CHANNEL_1:
03811       {
03812         assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03813
03814         TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
03815                           sConfig->ICSelection, sConfig->ICFilter);
03816
03817         /* Reset the IC1PSC Bits */
03818         htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
03819
03820         /* Select the Trigger source */
03821         htim->Instance->SMCR &= ~TIM_SMCR_TS;
03822         htim->Instance->SMCR |= TIM_TS_TI1FP1;
03823
03824         /* Select the Slave Mode */
03825         htim->Instance->SMCR &= ~TIM_SMCR_SMS;
03826         htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
03827         break;
03828       }
03829       case TIM_CHANNEL_2:
03830       {
03831         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03832
03833         TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
03834                           sConfig->ICSelection, sConfig->ICFilter);
03835
03836         /* Reset the IC2PSC Bits */
03837         htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
03838
03839         /* Select the Trigger source */
03840         htim->Instance->SMCR &= ~TIM_SMCR_TS;
03841         htim->Instance->SMCR |= TIM_TS_TI2FP2;
03842
03843         /* Select the Slave Mode */
03844         htim->Instance->SMCR &= ~TIM_SMCR_SMS;
03845         htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
03846         break;
03847       }
03848
03849       default:
03850         break;
03851     }
03852
03853     htim->State = HAL_TIM_STATE_READY;
03854
03855     __HAL_UNLOCK(htim);
03856
03857     return HAL_OK;
03858   }
03859   else
03860   {
03861     return HAL_ERROR;
03862   }
03863 }
03864
03865 /**
03866   * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
03867   * @param  htim TIM handle
03868   * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data write
03869   *         This parameter can be one of the following values:
03870   *            @arg TIM_DMABASE_CR1
03871   *            @arg TIM_DMABASE_CR2
03872   *            @arg TIM_DMABASE_SMCR
03873   *            @arg TIM_DMABASE_DIER
03874   *            @arg TIM_DMABASE_SR
03875   *            @arg TIM_DMABASE_EGR
03876   *            @arg TIM_DMABASE_CCMR1
03877   *            @arg TIM_DMABASE_CCMR2
03878   *            @arg TIM_DMABASE_CCER
03879   *            @arg TIM_DMABASE_CNT
03880   *            @arg TIM_DMABASE_PSC
03881   *            @arg TIM_DMABASE_ARR
03882   *            @arg TIM_DMABASE_RCR
03883   *            @arg TIM_DMABASE_CCR1
03884   *            @arg TIM_DMABASE_CCR2
03885   *            @arg TIM_DMABASE_CCR3
03886   *            @arg TIM_DMABASE_CCR4
03887   *            @arg TIM_DMABASE_BDTR
03888   *            @arg TIM_DMABASE_OR
03889   *            @arg TIM_DMABASE_CCMR3
03890   *            @arg TIM_DMABASE_CCR5
03891   *            @arg TIM_DMABASE_CCR6
03892   *            @arg TIM_DMABASE_AF1
03893   *            @arg TIM_DMABASE_AF2
03894   * @param  BurstRequestSrc TIM DMA Request sources
03895   *         This parameter can be one of the following values:
03896   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
03897   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
03898   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
03899   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
03900   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
03901   *            @arg TIM_DMA_COM: TIM Commutation DMA source
03902   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
03903   * @param  BurstBuffer The Buffer address.
03904   * @param  BurstLength DMA Burst length. This parameter can be one value
03905   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
03906   * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
03907   * @retval HAL status
03908   */
03909 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
03910                                               uint32_t *BurstBuffer, uint32_t  BurstLength)
03911 {
03912   /* Check the parameters */
03913   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
03914   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
03915   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
03916   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
03917
03918   if (htim->State == HAL_TIM_STATE_BUSY)
03919   {
03920     return HAL_BUSY;
03921   }
03922   else if (htim->State == HAL_TIM_STATE_READY)
03923   {
03924     if ((BurstBuffer == NULL) && (BurstLength > 0U))
03925     {
03926       return HAL_ERROR;
03927     }
03928     else
03929     {
03930       htim->State = HAL_TIM_STATE_BUSY;
03931     }
03932   }
03933   else
03934   {
03935     /* nothing to do */
03936   }
03937   switch (BurstRequestSrc)
03938   {
03939     case TIM_DMA_UPDATE:
03940     {
03941       /* Set the DMA Period elapsed callbacks */
03942       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
03943       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
03944
03945       /* Set the DMA error callback */
03946       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
03947
03948       /* Enable the DMA channel */
03949       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
03950       {
03951         return HAL_ERROR;
03952       }
03953       break;
03954     }
03955     case TIM_DMA_CC1:
03956     {
03957       /* Set the DMA compare callbacks */
03958       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
03959       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
03960
03961       /* Set the DMA error callback */
03962       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
03963
03964       /* Enable the DMA channel */
03965       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
03966                            (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
03967       {
03968         return HAL_ERROR;
03969       }
03970       break;
03971     }
03972     case TIM_DMA_CC2:
03973     {
03974       /* Set the DMA compare callbacks */
03975       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
03976       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
03977
03978       /* Set the DMA error callback */
03979       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
03980
03981       /* Enable the DMA channel */
03982       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
03983                            (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
03984       {
03985         return HAL_ERROR;
03986       }
03987       break;
03988     }
03989     case TIM_DMA_CC3:
03990     {
03991       /* Set the DMA compare callbacks */
03992       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
03993       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
03994
03995       /* Set the DMA error callback */
03996       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
03997
03998       /* Enable the DMA channel */
03999       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
04000                            (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
04001       {
04002         return HAL_ERROR;
04003       }
04004       break;
04005     }
04006     case TIM_DMA_CC4:
04007     {
04008       /* Set the DMA compare callbacks */
04009       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
04010       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
04011
04012       /* Set the DMA error callback */
04013       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
04014
04015       /* Enable the DMA channel */
04016       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
04017                            (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
04018       {
04019         return HAL_ERROR;
04020       }
04021       break;
04022     }
04023     case TIM_DMA_COM:
04024     {
04025       /* Set the DMA commutation callbacks */
04026       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
04027       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
04028
04029       /* Set the DMA error callback */
04030       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
04031
04032       /* Enable the DMA channel */
04033       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
04034                            (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
04035       {
04036         return HAL_ERROR;
04037       }
04038       break;
04039     }
04040     case TIM_DMA_TRIGGER:
04041     {
04042       /* Set the DMA trigger callbacks */
04043       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
04044       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
04045
04046       /* Set the DMA error callback */
04047       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
04048
04049       /* Enable the DMA channel */
04050       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
04051                            (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
04052       {
04053         return HAL_ERROR;
04054       }
04055       break;
04056     }
04057     default:
04058       break;
04059   }
04060   /* configure the DMA Burst Mode */
04061   htim->Instance->DCR = (BurstBaseAddress | BurstLength);
04062
04063   /* Enable the TIM DMA Request */
04064   __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
04065
04066   htim->State = HAL_TIM_STATE_READY;
04067
04068   /* Return function status */
04069   return HAL_OK;
04070 }
04071
04072 /**
04073   * @brief  Stops the TIM DMA Burst mode
04074   * @param  htim TIM handle
04075   * @param  BurstRequestSrc TIM DMA Request sources to disable
04076   * @retval HAL status
04077   */
04078 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
04079 {
04080   HAL_StatusTypeDef status = HAL_OK;
04081   /* Check the parameters */
04082   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
04083
04084   /* Abort the DMA transfer (at least disable the DMA channel) */
04085   switch (BurstRequestSrc)
04086   {
04087     case TIM_DMA_UPDATE:
04088     {
04089       status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
04090       break;
04091     }
04092     case TIM_DMA_CC1:
04093     {
04094       status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
04095       break;
04096     }
04097     case TIM_DMA_CC2:
04098     {
04099       status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
04100       break;
04101     }
04102     case TIM_DMA_CC3:
04103     {
04104       status =  HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
04105       break;
04106     }
04107     case TIM_DMA_CC4:
04108     {
04109       status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
04110       break;
04111     }
04112     case TIM_DMA_COM:
04113     {
04114       status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
04115       break;
04116     }
04117     case TIM_DMA_TRIGGER:
04118     {
04119       status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
04120       break;
04121     }
04122     default:
04123       break;
04124   }
04125
04126   if (HAL_OK == status)
04127   {
04128     /* Disable the TIM Update DMA request */
04129     __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
04130   }
04131
04132   /* Return function status */
04133   return status;
04134 }
04135
04136 /**
04137   * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
04138   * @param  htim TIM handle
04139   * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
04140   *         This parameter can be one of the following values:
04141   *            @arg TIM_DMABASE_CR1
04142   *            @arg TIM_DMABASE_CR2
04143   *            @arg TIM_DMABASE_SMCR
04144   *            @arg TIM_DMABASE_DIER
04145   *            @arg TIM_DMABASE_SR
04146   *            @arg TIM_DMABASE_EGR
04147   *            @arg TIM_DMABASE_CCMR1
04148   *            @arg TIM_DMABASE_CCMR2
04149   *            @arg TIM_DMABASE_CCER
04150   *            @arg TIM_DMABASE_CNT
04151   *            @arg TIM_DMABASE_PSC
04152   *            @arg TIM_DMABASE_ARR
04153   *            @arg TIM_DMABASE_RCR
04154   *            @arg TIM_DMABASE_CCR1
04155   *            @arg TIM_DMABASE_CCR2
04156   *            @arg TIM_DMABASE_CCR3
04157   *            @arg TIM_DMABASE_CCR4
04158   *            @arg TIM_DMABASE_BDTR
04159   *            @arg TIM_DMABASE_OR
04160   *            @arg TIM_DMABASE_CCMR3
04161   *            @arg TIM_DMABASE_CCR5
04162   *            @arg TIM_DMABASE_CCR6
04163   *            @arg TIM_DMABASE_AF1
04164   *            @arg TIM_DMABASE_AF2
04165   * @param  BurstRequestSrc TIM DMA Request sources
04166   *         This parameter can be one of the following values:
04167   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
04168   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
04169   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
04170   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
04171   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
04172   *            @arg TIM_DMA_COM: TIM Commutation DMA source
04173   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
04174   * @param  BurstBuffer The Buffer address.
04175   * @param  BurstLength DMA Burst length. This parameter can be one value
04176   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
04177   * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
04178   * @retval HAL status
04179   */
04180 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
04181                                              uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength)
04182 {
04183   /* Check the parameters */
04184   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
04185   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
04186   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
04187   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
04188
04189   if (htim->State == HAL_TIM_STATE_BUSY)
04190   {
04191     return HAL_BUSY;
04192   }
04193   else if (htim->State == HAL_TIM_STATE_READY)
04194   {
04195     if ((BurstBuffer == NULL) && (BurstLength > 0U))
04196     {
04197       return HAL_ERROR;
04198     }
04199     else
04200     {
04201       htim->State = HAL_TIM_STATE_BUSY;
04202     }
04203   }
04204   else
04205   {
04206     /* nothing to do */
04207   }
04208   switch (BurstRequestSrc)
04209   {
04210     case TIM_DMA_UPDATE:
04211     {
04212       /* Set the DMA Period elapsed callbacks */
04213       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
04214       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
04215
04216       /* Set the DMA error callback */
04217       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
04218
04219       /* Enable the DMA channel */
04220       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
04221       {
04222         return HAL_ERROR;
04223       }
04224       break;
04225     }
04226     case TIM_DMA_CC1:
04227     {
04228       /* Set the DMA capture callbacks */
04229       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
04230       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
04231
04232       /* Set the DMA error callback */
04233       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
04234
04235       /* Enable the DMA channel */
04236       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
04237       {
04238         return HAL_ERROR;
04239       }
04240       break;
04241     }
04242     case TIM_DMA_CC2:
04243     {
04244       /* Set the DMA capture/compare callbacks */
04245       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
04246       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
04247
04248       /* Set the DMA error callback */
04249       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
04250
04251       /* Enable the DMA channel */
04252       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
04253       {
04254         return HAL_ERROR;
04255       }
04256       break;
04257     }
04258     case TIM_DMA_CC3:
04259     {
04260       /* Set the DMA capture callbacks */
04261       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
04262       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
04263
04264       /* Set the DMA error callback */
04265       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
04266
04267       /* Enable the DMA channel */
04268       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
04269       {
04270         return HAL_ERROR;
04271       }
04272       break;
04273     }
04274     case TIM_DMA_CC4:
04275     {
04276       /* Set the DMA capture callbacks */
04277       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
04278       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
04279
04280       /* Set the DMA error callback */
04281       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
04282
04283       /* Enable the DMA channel */
04284       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
04285       {
04286         return HAL_ERROR;
04287       }
04288       break;
04289     }
04290     case TIM_DMA_COM:
04291     {
04292       /* Set the DMA commutation callbacks */
04293       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
04294       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
04295
04296       /* Set the DMA error callback */
04297       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
04298
04299       /* Enable the DMA channel */
04300       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
04301       {
04302         return HAL_ERROR;
04303       }
04304       break;
04305     }
04306     case TIM_DMA_TRIGGER:
04307     {
04308       /* Set the DMA trigger callbacks */
04309       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
04310       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
04311
04312       /* Set the DMA error callback */
04313       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
04314
04315       /* Enable the DMA channel */
04316       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
04317       {
04318         return HAL_ERROR;
04319       }
04320       break;
04321     }
04322     default:
04323       break;
04324   }
04325
04326   /* configure the DMA Burst Mode */
04327   htim->Instance->DCR = (BurstBaseAddress | BurstLength);
04328
04329   /* Enable the TIM DMA Request */
04330   __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
04331
04332   htim->State = HAL_TIM_STATE_READY;
04333
04334   /* Return function status */
04335   return HAL_OK;
04336 }
04337
04338 /**
04339   * @brief  Stop the DMA burst reading
04340   * @param  htim TIM handle
04341   * @param  BurstRequestSrc TIM DMA Request sources to disable.
04342   * @retval HAL status
04343   */
04344 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
04345 {
04346   HAL_StatusTypeDef status = HAL_OK;
04347   /* Check the parameters */
04348   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
04349
04350   /* Abort the DMA transfer (at least disable the DMA channel) */
04351   switch (BurstRequestSrc)
04352   {
04353     case TIM_DMA_UPDATE:
04354     {
04355       status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
04356       break;
04357     }
04358     case TIM_DMA_CC1:
04359     {
04360       status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
04361       break;
04362     }
04363     case TIM_DMA_CC2:
04364     {
04365       status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
04366       break;
04367     }
04368     case TIM_DMA_CC3:
04369     {
04370       status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
04371       break;
04372     }
04373     case TIM_DMA_CC4:
04374     {
04375       status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
04376       break;
04377     }
04378     case TIM_DMA_COM:
04379     {
04380       status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
04381       break;
04382     }
04383     case TIM_DMA_TRIGGER:
04384     {
04385       status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
04386       break;
04387     }
04388     default:
04389       break;
04390   }
04391
04392   if (HAL_OK == status)
04393   {
04394     /* Disable the TIM Update DMA request */
04395     __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
04396   }
04397
04398   /* Return function status */
04399   return status;
04400 }
04401
04402 /**
04403   * @brief  Generate a software event
04404   * @param  htim TIM handle
04405   * @param  EventSource specifies the event source.
04406   *          This parameter can be one of the following values:
04407   *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
04408   *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
04409   *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
04410   *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
04411   *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
04412   *            @arg TIM_EVENTSOURCE_COM: Timer COM event source
04413   *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
04414   *            @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
04415   *            @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
04416   * @note   Basic timers can only generate an update event.
04417   * @note   TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
04418   * @note   TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant
04419   *         only for timer instances supporting break input(s).
04420   * @retval HAL status
04421   */
04422
04423 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
04424 {
04425   /* Check the parameters */
04426   assert_param(IS_TIM_INSTANCE(htim->Instance));
04427   assert_param(IS_TIM_EVENT_SOURCE(EventSource));
04428
04429   /* Process Locked */
04430   __HAL_LOCK(htim);
04431
04432   /* Change the TIM state */
04433   htim->State = HAL_TIM_STATE_BUSY;
04434
04435   /* Set the event sources */
04436   htim->Instance->EGR = EventSource;
04437
04438   /* Change the TIM state */
04439   htim->State = HAL_TIM_STATE_READY;
04440
04441   __HAL_UNLOCK(htim);
04442
04443   /* Return function status */
04444   return HAL_OK;
04445 }
04446
04447 /**
04448   * @brief  Configures the OCRef clear feature
04449   * @param  htim TIM handle
04450   * @param  sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
04451   *         contains the OCREF clear feature and parameters for the TIM peripheral.
04452   * @param  Channel specifies the TIM Channel
04453   *          This parameter can be one of the following values:
04454   *            @arg TIM_CHANNEL_1: TIM Channel 1
04455   *            @arg TIM_CHANNEL_2: TIM Channel 2
04456   *            @arg TIM_CHANNEL_3: TIM Channel 3
04457   *            @arg TIM_CHANNEL_4: TIM Channel 4
04458   *            @arg TIM_CHANNEL_5: TIM Channel 5
04459   *            @arg TIM_CHANNEL_6: TIM Channel 6
04460   * @retval HAL status
04461   */
04462 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
04463                                            TIM_ClearInputConfigTypeDef *sClearInputConfig,
04464                                            uint32_t Channel)
04465 {
04466   /* Check the parameters */
04467   assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
04468   assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
04469
04470   /* Process Locked */
04471   __HAL_LOCK(htim);
04472
04473   htim->State = HAL_TIM_STATE_BUSY;
04474
04475   switch (sClearInputConfig->ClearInputSource)
04476   {
04477     case TIM_CLEARINPUTSOURCE_NONE:
04478     {
04479       /* Clear the OCREF clear selection bit and the the ETR Bits */
04480       CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
04481
04482       /* Clear TIMx_AF1_OCREF_CLR (reset value) */
04483       CLEAR_BIT(htim->Instance->AF1, TIM1_AF1_ETRSEL);
04484       break;
04485     }
04486     case TIM_CLEARINPUTSOURCE_COMP1:
04487     case TIM_CLEARINPUTSOURCE_COMP2:
04488     {
04489       /* Clear the OCREF clear selection bit */
04490       CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
04491
04492       /* OCREF_CLR_INT is connected to COMPx output */
04493       MODIFY_REG(htim->Instance->AF1, TIM1_AF1_ETRSEL, sClearInputConfig->ClearInputSource);
04494       break;
04495     }
04496
04497     case TIM_CLEARINPUTSOURCE_ETR:
04498     {
04499       /* Check the parameters */
04500       assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
04501       assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
04502       assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
04503
04504       /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
04505       if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
04506       {
04507         htim->State = HAL_TIM_STATE_READY;
04508         __HAL_UNLOCK(htim);
04509         return HAL_ERROR;
04510       }
04511
04512       TIM_ETR_SetConfig(htim->Instance,
04513                         sClearInputConfig->ClearInputPrescaler,
04514                         sClearInputConfig->ClearInputPolarity,
04515                         sClearInputConfig->ClearInputFilter);
04516
04517       /* Set the OCREF clear selection bit */
04518       SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
04519
04520       /* Clear TIMx_AF1_OCREF_CLR (reset value) */
04521       CLEAR_BIT(htim->Instance->AF1, TIM1_AF1_ETRSEL);
04522       break;
04523     }
04524
04525     default:
04526       break;
04527   }
04528
04529   switch (Channel)
04530   {
04531     case TIM_CHANNEL_1:
04532     {
04533       if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
04534       {
04535         /* Enable the OCREF clear feature for Channel 1 */
04536         SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
04537       }
04538       else
04539       {
04540         /* Disable the OCREF clear feature for Channel 1 */
04541         CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
04542       }
04543       break;
04544     }
04545     case TIM_CHANNEL_2:
04546     {
04547       if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
04548       {
04549         /* Enable the OCREF clear feature for Channel 2 */
04550         SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
04551       }
04552       else
04553       {
04554         /* Disable the OCREF clear feature for Channel 2 */
04555         CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
04556       }
04557       break;
04558     }
04559     case TIM_CHANNEL_3:
04560     {
04561       if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
04562       {
04563         /* Enable the OCREF clear feature for Channel 3 */
04564         SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
04565       }
04566       else
04567       {
04568         /* Disable the OCREF clear feature for Channel 3 */
04569         CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
04570       }
04571       break;
04572     }
04573     case TIM_CHANNEL_4:
04574     {
04575       if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
04576       {
04577         /* Enable the OCREF clear feature for Channel 4 */
04578         SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
04579       }
04580       else
04581       {
04582         /* Disable the OCREF clear feature for Channel 4 */
04583         CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
04584       }
04585       break;
04586     }
04587     case TIM_CHANNEL_5:
04588     {
04589       if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
04590       {
04591         /* Enable the OCREF clear feature for Channel 5 */
04592         SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
04593       }
04594       else
04595       {
04596         /* Disable the OCREF clear feature for Channel 5 */
04597         CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
04598       }
04599       break;
04600     }
04601     case TIM_CHANNEL_6:
04602     {
04603       if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
04604       {
04605         /* Enable the OCREF clear feature for Channel 6 */
04606         SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
04607       }
04608       else
04609       {
04610         /* Disable the OCREF clear feature for Channel 6 */
04611         CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
04612       }
04613       break;
04614     }
04615     default:
04616       break;
04617   }
04618
04619   htim->State = HAL_TIM_STATE_READY;
04620
04621   __HAL_UNLOCK(htim);
04622
04623   return HAL_OK;
04624 }
04625
04626 /**
04627   * @brief   Configures the clock source to be used
04628   * @param  htim TIM handle
04629   * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
04630   *         contains the clock source information for the TIM peripheral.
04631   * @retval HAL status
04632   */
04633 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
04634 {
04635   uint32_t tmpsmcr;
04636
04637   /* Process Locked */
04638   __HAL_LOCK(htim);
04639
04640   htim->State = HAL_TIM_STATE_BUSY;
04641
04642   /* Check the parameters */
04643   assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
04644
04645   /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
04646   tmpsmcr = htim->Instance->SMCR;
04647   tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
04648   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
04649   htim->Instance->SMCR = tmpsmcr;
04650
04651   switch (sClockSourceConfig->ClockSource)
04652   {
04653     case TIM_CLOCKSOURCE_INTERNAL:
04654     {
04655       assert_param(IS_TIM_INSTANCE(htim->Instance));
04656       break;
04657     }
04658
04659     case TIM_CLOCKSOURCE_ETRMODE1:
04660     {
04661       /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
04662       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
04663
04664       /* Check ETR input conditioning related parameters */
04665       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
04666       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
04667       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
04668
04669       /* Configure the ETR Clock source */
04670       TIM_ETR_SetConfig(htim->Instance,
04671                         sClockSourceConfig->ClockPrescaler,
04672                         sClockSourceConfig->ClockPolarity,
04673                         sClockSourceConfig->ClockFilter);
04674
04675       /* Select the External clock mode1 and the ETRF trigger */
04676       tmpsmcr = htim->Instance->SMCR;
04677       tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
04678       /* Write to TIMx SMCR */
04679       htim->Instance->SMCR = tmpsmcr;
04680       break;
04681     }
04682
04683     case TIM_CLOCKSOURCE_ETRMODE2:
04684     {
04685       /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
04686       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
04687
04688       /* Check ETR input conditioning related parameters */
04689       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
04690       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
04691       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
04692
04693       /* Configure the ETR Clock source */
04694       TIM_ETR_SetConfig(htim->Instance,
04695                         sClockSourceConfig->ClockPrescaler,
04696                         sClockSourceConfig->ClockPolarity,
04697                         sClockSourceConfig->ClockFilter);
04698       /* Enable the External clock mode2 */
04699       htim->Instance->SMCR |= TIM_SMCR_ECE;
04700       break;
04701     }
04702
04703     case TIM_CLOCKSOURCE_TI1:
04704     {
04705       /* Check whether or not the timer instance supports external clock mode 1 */
04706       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
04707
04708       /* Check TI1 input conditioning related parameters */
04709       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
04710       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
04711
04712       TIM_TI1_ConfigInputStage(htim->Instance,
04713                                sClockSourceConfig->ClockPolarity,
04714                                sClockSourceConfig->ClockFilter);
04715       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
04716       break;
04717     }
04718
04719     case TIM_CLOCKSOURCE_TI2:
04720     {
04721       /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
04722       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
04723
04724       /* Check TI2 input conditioning related parameters */
04725       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
04726       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
04727
04728       TIM_TI2_ConfigInputStage(htim->Instance,
04729                                sClockSourceConfig->ClockPolarity,
04730                                sClockSourceConfig->ClockFilter);
04731       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
04732       break;
04733     }
04734
04735     case TIM_CLOCKSOURCE_TI1ED:
04736     {
04737       /* Check whether or not the timer instance supports external clock mode 1 */
04738       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
04739
04740       /* Check TI1 input conditioning related parameters */
04741       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
04742       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
04743
04744       TIM_TI1_ConfigInputStage(htim->Instance,
04745                                sClockSourceConfig->ClockPolarity,
04746                                sClockSourceConfig->ClockFilter);
04747       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
04748       break;
04749     }
04750
04751     case TIM_CLOCKSOURCE_ITR0:
04752     case TIM_CLOCKSOURCE_ITR1:
04753     case TIM_CLOCKSOURCE_ITR2:
04754     case TIM_CLOCKSOURCE_ITR3:
04755     {
04756       /* Check whether or not the timer instance supports internal trigger input */
04757       assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
04758
04759       TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
04760       break;
04761     }
04762
04763     default:
04764       break;
04765   }
04766   htim->State = HAL_TIM_STATE_READY;
04767
04768   __HAL_UNLOCK(htim);
04769
04770   return HAL_OK;
04771 }
04772
04773 /**
04774   * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
04775   *         or a XOR combination between CH1_input, CH2_input & CH3_input
04776   * @param  htim TIM handle.
04777   * @param  TI1_Selection Indicate whether or not channel 1 is connected to the
04778   *         output of a XOR gate.
04779   *          This parameter can be one of the following values:
04780   *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
04781   *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
04782   *            pins are connected to the TI1 input (XOR combination)
04783   * @retval HAL status
04784   */
04785 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
04786 {
04787   uint32_t tmpcr2;
04788
04789   /* Check the parameters */
04790   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
04791   assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
04792
04793   /* Get the TIMx CR2 register value */
04794   tmpcr2 = htim->Instance->CR2;
04795
04796   /* Reset the TI1 selection */
04797   tmpcr2 &= ~TIM_CR2_TI1S;
04798
04799   /* Set the TI1 selection */
04800   tmpcr2 |= TI1_Selection;
04801
04802   /* Write to TIMxCR2 */
04803   htim->Instance->CR2 = tmpcr2;
04804
04805   return HAL_OK;
04806 }
04807
04808 /**
04809   * @brief  Configures the TIM in Slave mode
04810   * @param  htim TIM handle.
04811   * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
04812   *         contains the selected trigger (internal trigger input, filtered
04813   *         timer input or external trigger input) and the Slave mode
04814   *         (Disable, Reset, Gated, Trigger, External clock mode 1).
04815   * @retval HAL status
04816   */
04817 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
04818 {
04819   /* Check the parameters */
04820   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
04821   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
04822   assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
04823
04824   __HAL_LOCK(htim);
04825
04826   htim->State = HAL_TIM_STATE_BUSY;
04827
04828   if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
04829   {
04830     htim->State = HAL_TIM_STATE_READY;
04831     __HAL_UNLOCK(htim);
04832     return HAL_ERROR;
04833   }
04834
04835   /* Disable Trigger Interrupt */
04836   __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
04837
04838   /* Disable Trigger DMA request */
04839   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
04840
04841   htim->State = HAL_TIM_STATE_READY;
04842
04843   __HAL_UNLOCK(htim);
04844
04845   return HAL_OK;
04846 }
04847
04848 /**
04849   * @brief  Configures the TIM in Slave mode in interrupt mode
04850   * @param  htim TIM handle.
04851   * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
04852   *         contains the selected trigger (internal trigger input, filtered
04853   *         timer input or external trigger input) and the Slave mode
04854   *         (Disable, Reset, Gated, Trigger, External clock mode 1).
04855   * @retval HAL status
04856   */
04857 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
04858                                                 TIM_SlaveConfigTypeDef *sSlaveConfig)
04859 {
04860   /* Check the parameters */
04861   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
04862   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
04863   assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
04864
04865   __HAL_LOCK(htim);
04866
04867   htim->State = HAL_TIM_STATE_BUSY;
04868
04869   if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
04870   {
04871     htim->State = HAL_TIM_STATE_READY;
04872     __HAL_UNLOCK(htim);
04873     return HAL_ERROR;
04874   }
04875
04876   /* Enable Trigger Interrupt */
04877   __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
04878
04879   /* Disable Trigger DMA request */
04880   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
04881
04882   htim->State = HAL_TIM_STATE_READY;
04883
04884   __HAL_UNLOCK(htim);
04885
04886   return HAL_OK;
04887 }
04888
04889 /**
04890   * @brief  Read the captured value from Capture Compare unit
04891   * @param  htim TIM handle.
04892   * @param  Channel TIM Channels to be enabled
04893   *          This parameter can be one of the following values:
04894   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
04895   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
04896   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
04897   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
04898   * @retval Captured value
04899   */
04900 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
04901 {
04902   uint32_t tmpreg = 0U;
04903
04904   switch (Channel)
04905   {
04906     case TIM_CHANNEL_1:
04907     {
04908       /* Check the parameters */
04909       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
04910
04911       /* Return the capture 1 value */
04912       tmpreg =  htim->Instance->CCR1;
04913
04914       break;
04915     }
04916     case TIM_CHANNEL_2:
04917     {
04918       /* Check the parameters */
04919       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
04920
04921       /* Return the capture 2 value */
04922       tmpreg =   htim->Instance->CCR2;
04923
04924       break;
04925     }
04926
04927     case TIM_CHANNEL_3:
04928     {
04929       /* Check the parameters */
04930       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
04931
04932       /* Return the capture 3 value */
04933       tmpreg =   htim->Instance->CCR3;
04934
04935       break;
04936     }
04937
04938     case TIM_CHANNEL_4:
04939     {
04940       /* Check the parameters */
04941       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
04942
04943       /* Return the capture 4 value */
04944       tmpreg =   htim->Instance->CCR4;
04945
04946       break;
04947     }
04948
04949     default:
04950       break;
04951   }
04952
04953   return tmpreg;
04954 }
04955
04956 /**
04957   * @}
04958   */
04959
04960 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
04961   *  @brief    TIM Callbacks functions
04962   *
04963 @verbatim
04964   ==============================================================================
04965                         ##### TIM Callbacks functions #####
04966   ==============================================================================
04967  [..]
04968    This section provides TIM callback functions:
04969    (+) TIM Period elapsed callback
04970    (+) TIM Output Compare callback
04971    (+) TIM Input capture callback
04972    (+) TIM Trigger callback
04973    (+) TIM Error callback
04974
04975 @endverbatim
04976   * @{
04977   */
04978
04979 /**
04980   * @brief  Period elapsed callback in non-blocking mode
04981   * @param  htim TIM handle
04982   * @retval None
04983   */
04984 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
04985 {
04986   /* Prevent unused argument(s) compilation warning */
04987   UNUSED(htim);
04988
04989   /* NOTE : This function should not be modified, when the callback is needed,
04990             the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
04991    */
04992 }
04993
04994 /**
04995   * @brief  Period elapsed half complete callback in non-blocking mode
04996   * @param  htim TIM handle
04997   * @retval None
04998   */
04999 __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
05000 {
05001   /* Prevent unused argument(s) compilation warning */
05002   UNUSED(htim);
05003
05004   /* NOTE : This function should not be modified, when the callback is needed,
05005             the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
05006    */
05007 }
05008
05009 /**
05010   * @brief  Output Compare callback in non-blocking mode
05011   * @param  htim TIM OC handle
05012   * @retval None
05013   */
05014 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
05015 {
05016   /* Prevent unused argument(s) compilation warning */
05017   UNUSED(htim);
05018
05019   /* NOTE : This function should not be modified, when the callback is needed,
05020             the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
05021    */
05022 }
05023
05024 /**
05025   * @brief  Input Capture callback in non-blocking mode
05026   * @param  htim TIM IC handle
05027   * @retval None
05028   */
05029 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
05030 {
05031   /* Prevent unused argument(s) compilation warning */
05032   UNUSED(htim);
05033
05034   /* NOTE : This function should not be modified, when the callback is needed,
05035             the HAL_TIM_IC_CaptureCallback could be implemented in the user file
05036    */
05037 }
05038
05039 /**
05040   * @brief  Input Capture half complete callback in non-blocking mode
05041   * @param  htim TIM IC handle
05042   * @retval None
05043   */
05044 __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
05045 {
05046   /* Prevent unused argument(s) compilation warning */
05047   UNUSED(htim);
05048
05049   /* NOTE : This function should not be modified, when the callback is needed,
05050             the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
05051    */
05052 }
05053
05054 /**
05055   * @brief  PWM Pulse finished callback in non-blocking mode
05056   * @param  htim TIM handle
05057   * @retval None
05058   */
05059 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
05060 {
05061   /* Prevent unused argument(s) compilation warning */
05062   UNUSED(htim);
05063
05064   /* NOTE : This function should not be modified, when the callback is needed,
05065             the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
05066    */
05067 }
05068
05069 /**
05070   * @brief  PWM Pulse finished half complete callback in non-blocking mode
05071   * @param  htim TIM handle
05072   * @retval None
05073   */
05074 __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
05075 {
05076   /* Prevent unused argument(s) compilation warning */
05077   UNUSED(htim);
05078
05079   /* NOTE : This function should not be modified, when the callback is needed,
05080             the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
05081    */
05082 }
05083
05084 /**
05085   * @brief  Hall Trigger detection callback in non-blocking mode
05086   * @param  htim TIM handle
05087   * @retval None
05088   */
05089 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
05090 {
05091   /* Prevent unused argument(s) compilation warning */
05092   UNUSED(htim);
05093
05094   /* NOTE : This function should not be modified, when the callback is needed,
05095             the HAL_TIM_TriggerCallback could be implemented in the user file
05096    */
05097 }
05098
05099 /**
05100   * @brief  Hall Trigger detection half complete callback in non-blocking mode
05101   * @param  htim TIM handle
05102   * @retval None
05103   */
05104 __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
05105 {
05106   /* Prevent unused argument(s) compilation warning */
05107   UNUSED(htim);
05108
05109   /* NOTE : This function should not be modified, when the callback is needed,
05110             the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
05111    */
05112 }
05113
05114 /**
05115   * @brief  Timer error callback in non-blocking mode
05116   * @param  htim TIM handle
05117   * @retval None
05118   */
05119 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
05120 {
05121   /* Prevent unused argument(s) compilation warning */
05122   UNUSED(htim);
05123
05124   /* NOTE : This function should not be modified, when the callback is needed,
05125             the HAL_TIM_ErrorCallback could be implemented in the user file
05126    */
05127 }
05128
05129 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
05130 /**
05131   * @brief  Register a User TIM callback to be used instead of the weak predefined callback
05132   * @param htim tim handle
05133   * @param CallbackID ID of the callback to be registered
05134   *        This parameter can be one of the following values:
05135   *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
05136   *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
05137   *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
05138   *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
05139   *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
05140   *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
05141   *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
05142   *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
05143   *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
05144   *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
05145   *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
05146   *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
05147   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
05148   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
05149   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
05150   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
05151   *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
05152   *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
05153   *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
05154   *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
05155   *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
05156   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
05157   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
05158   *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
05159   *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
05160   *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
05161   *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
05162   *          @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
05163   *          @param pCallback pointer to the callback function
05164   *          @retval status
05165   */
05166 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
05167                                            pTIM_CallbackTypeDef pCallback)
05168 {
05169   HAL_StatusTypeDef status = HAL_OK;
05170
05171   if (pCallback == NULL)
05172   {
05173     return HAL_ERROR;
05174   }
05175   /* Process locked */
05176   __HAL_LOCK(htim);
05177
05178   if (htim->State == HAL_TIM_STATE_READY)
05179   {
05180     switch (CallbackID)
05181     {
05182       case HAL_TIM_BASE_MSPINIT_CB_ID :
05183         htim->Base_MspInitCallback                 = pCallback;
05184         break;
05185
05186       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
05187         htim->Base_MspDeInitCallback               = pCallback;
05188         break;
05189
05190       case HAL_TIM_IC_MSPINIT_CB_ID :
05191         htim->IC_MspInitCallback                   = pCallback;
05192         break;
05193
05194       case HAL_TIM_IC_MSPDEINIT_CB_ID :
05195         htim->IC_MspDeInitCallback                 = pCallback;
05196         break;
05197
05198       case HAL_TIM_OC_MSPINIT_CB_ID :
05199         htim->OC_MspInitCallback                   = pCallback;
05200         break;
05201
05202       case HAL_TIM_OC_MSPDEINIT_CB_ID :
05203         htim->OC_MspDeInitCallback                 = pCallback;
05204         break;
05205
05206       case HAL_TIM_PWM_MSPINIT_CB_ID :
05207         htim->PWM_MspInitCallback                  = pCallback;
05208         break;
05209
05210       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
05211         htim->PWM_MspDeInitCallback                = pCallback;
05212         break;
05213
05214       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
05215         htim->OnePulse_MspInitCallback             = pCallback;
05216         break;
05217
05218       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
05219         htim->OnePulse_MspDeInitCallback           = pCallback;
05220         break;
05221
05222       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
05223         htim->Encoder_MspInitCallback              = pCallback;
05224         break;
05225
05226       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
05227         htim->Encoder_MspDeInitCallback            = pCallback;
05228         break;
05229
05230       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
05231         htim->HallSensor_MspInitCallback           = pCallback;
05232         break;
05233
05234       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
05235         htim->HallSensor_MspDeInitCallback         = pCallback;
05236         break;
05237
05238       case HAL_TIM_PERIOD_ELAPSED_CB_ID :
05239         htim->PeriodElapsedCallback                = pCallback;
05240         break;
05241
05242       case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
05243         htim->PeriodElapsedHalfCpltCallback        = pCallback;
05244         break;
05245
05246       case HAL_TIM_TRIGGER_CB_ID :
05247         htim->TriggerCallback                      = pCallback;
05248         break;
05249
05250       case HAL_TIM_TRIGGER_HALF_CB_ID :
05251         htim->TriggerHalfCpltCallback              = pCallback;
05252         break;
05253
05254       case HAL_TIM_IC_CAPTURE_CB_ID :
05255         htim->IC_CaptureCallback                   = pCallback;
05256         break;
05257
05258       case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
05259         htim->IC_CaptureHalfCpltCallback           = pCallback;
05260         break;
05261
05262       case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
05263         htim->OC_DelayElapsedCallback              = pCallback;
05264         break;
05265
05266       case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
05267         htim->PWM_PulseFinishedCallback            = pCallback;
05268         break;
05269
05270       case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
05271         htim->PWM_PulseFinishedHalfCpltCallback    = pCallback;
05272         break;
05273
05274       case HAL_TIM_ERROR_CB_ID :
05275         htim->ErrorCallback                        = pCallback;
05276         break;
05277
05278       case HAL_TIM_COMMUTATION_CB_ID :
05279         htim->CommutationCallback                  = pCallback;
05280         break;
05281
05282       case HAL_TIM_COMMUTATION_HALF_CB_ID :
05283         htim->CommutationHalfCpltCallback          = pCallback;
05284         break;
05285
05286       case HAL_TIM_BREAK_CB_ID :
05287         htim->BreakCallback                        = pCallback;
05288         break;
05289
05290       case HAL_TIM_BREAK2_CB_ID :
05291         htim->Break2Callback                       = pCallback;
05292         break;
05293
05294       default :
05295         /* Return error status */
05296         status =  HAL_ERROR;
05297         break;
05298     }
05299   }
05300   else if (htim->State == HAL_TIM_STATE_RESET)
05301   {
05302     switch (CallbackID)
05303     {
05304       case HAL_TIM_BASE_MSPINIT_CB_ID :
05305         htim->Base_MspInitCallback         = pCallback;
05306         break;
05307
05308       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
05309         htim->Base_MspDeInitCallback       = pCallback;
05310         break;
05311
05312       case HAL_TIM_IC_MSPINIT_CB_ID :
05313         htim->IC_MspInitCallback           = pCallback;
05314         break;
05315
05316       case HAL_TIM_IC_MSPDEINIT_CB_ID :
05317         htim->IC_MspDeInitCallback         = pCallback;
05318         break;
05319
05320       case HAL_TIM_OC_MSPINIT_CB_ID :
05321         htim->OC_MspInitCallback           = pCallback;
05322         break;
05323
05324       case HAL_TIM_OC_MSPDEINIT_CB_ID :
05325         htim->OC_MspDeInitCallback         = pCallback;
05326         break;
05327
05328       case HAL_TIM_PWM_MSPINIT_CB_ID :
05329         htim->PWM_MspInitCallback          = pCallback;
05330         break;
05331
05332       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
05333         htim->PWM_MspDeInitCallback        = pCallback;
05334         break;
05335
05336       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
05337         htim->OnePulse_MspInitCallback     = pCallback;
05338         break;
05339
05340       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
05341         htim->OnePulse_MspDeInitCallback   = pCallback;
05342         break;
05343
05344       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
05345         htim->Encoder_MspInitCallback      = pCallback;
05346         break;
05347
05348       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
05349         htim->Encoder_MspDeInitCallback    = pCallback;
05350         break;
05351
05352       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
05353         htim->HallSensor_MspInitCallback   = pCallback;
05354         break;
05355
05356       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
05357         htim->HallSensor_MspDeInitCallback = pCallback;
05358         break;
05359
05360       default :
05361         /* Return error status */
05362         status =  HAL_ERROR;
05363         break;
05364     }
05365   }
05366   else
05367   {
05368     /* Return error status */
05369     status =  HAL_ERROR;
05370   }
05371
05372   /* Release Lock */
05373   __HAL_UNLOCK(htim);
05374
05375   return status;
05376 }
05377
05378 /**
05379   * @brief  Unregister a TIM callback
05380   *         TIM callback is redirected to the weak predefined callback
05381   * @param htim tim handle
05382   * @param CallbackID ID of the callback to be unregistered
05383   *        This parameter can be one of the following values:
05384   *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
05385   *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
05386   *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
05387   *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
05388   *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
05389   *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
05390   *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
05391   *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
05392   *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
05393   *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
05394   *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
05395   *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
05396   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
05397   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
05398   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
05399   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
05400   *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
05401   *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
05402   *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
05403   *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
05404   *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
05405   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
05406   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
05407   *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
05408   *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
05409   *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
05410   *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
05411   *          @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
05412   *          @retval status
05413   */
05414 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
05415 {
05416   HAL_StatusTypeDef status = HAL_OK;
05417
05418   /* Process locked */
05419   __HAL_LOCK(htim);
05420
05421   if (htim->State == HAL_TIM_STATE_READY)
05422   {
05423     switch (CallbackID)
05424     {
05425       case HAL_TIM_BASE_MSPINIT_CB_ID :
05426         htim->Base_MspInitCallback              = HAL_TIM_Base_MspInit;                      /* Legacy weak Base MspInit Callback */
05427         break;
05428
05429       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
05430         htim->Base_MspDeInitCallback            = HAL_TIM_Base_MspDeInit;                    /* Legacy weak Base Msp DeInit Callback */
05431         break;
05432
05433       case HAL_TIM_IC_MSPINIT_CB_ID :
05434         htim->IC_MspInitCallback                = HAL_TIM_IC_MspInit;                        /* Legacy weak IC Msp Init Callback */
05435         break;
05436
05437       case HAL_TIM_IC_MSPDEINIT_CB_ID :
05438         htim->IC_MspDeInitCallback              = HAL_TIM_IC_MspDeInit;                      /* Legacy weak IC Msp DeInit Callback */
05439         break;
05440
05441       case HAL_TIM_OC_MSPINIT_CB_ID :
05442         htim->OC_MspInitCallback                = HAL_TIM_OC_MspInit;                        /* Legacy weak OC Msp Init Callback */
05443         break;
05444
05445       case HAL_TIM_OC_MSPDEINIT_CB_ID :
05446         htim->OC_MspDeInitCallback              = HAL_TIM_OC_MspDeInit;                      /* Legacy weak OC Msp DeInit Callback */
05447         break;
05448
05449       case HAL_TIM_PWM_MSPINIT_CB_ID :
05450         htim->PWM_MspInitCallback               = HAL_TIM_PWM_MspInit;                       /* Legacy weak PWM Msp Init Callback */
05451         break;
05452
05453       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
05454         htim->PWM_MspDeInitCallback             = HAL_TIM_PWM_MspDeInit;                     /* Legacy weak PWM Msp DeInit Callback */
05455         break;
05456
05457       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
05458         htim->OnePulse_MspInitCallback          = HAL_TIM_OnePulse_MspInit;                  /* Legacy weak One Pulse Msp Init Callback */
05459         break;
05460
05461       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
05462         htim->OnePulse_MspDeInitCallback        = HAL_TIM_OnePulse_MspDeInit;                /* Legacy weak One Pulse Msp DeInit Callback */
05463         break;
05464
05465       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
05466         htim->Encoder_MspInitCallback           = HAL_TIM_Encoder_MspInit;                   /* Legacy weak Encoder Msp Init Callback */
05467         break;
05468
05469       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
05470         htim->Encoder_MspDeInitCallback         = HAL_TIM_Encoder_MspDeInit;                 /* Legacy weak Encoder Msp DeInit Callback */
05471         break;
05472
05473       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
05474         htim->HallSensor_MspInitCallback        = HAL_TIMEx_HallSensor_MspInit;              /* Legacy weak Hall Sensor Msp Init Callback */
05475         break;
05476
05477       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
05478         htim->HallSensor_MspDeInitCallback      = HAL_TIMEx_HallSensor_MspDeInit;            /* Legacy weak Hall Sensor Msp DeInit Callback */
05479         break;
05480
05481       case HAL_TIM_PERIOD_ELAPSED_CB_ID :
05482         htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;             /* Legacy weak Period Elapsed Callback */
05483         break;
05484
05485       case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
05486         htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;     /* Legacy weak Period Elapsed half complete Callback */
05487         break;
05488
05489       case HAL_TIM_TRIGGER_CB_ID :
05490         htim->TriggerCallback                   = HAL_TIM_TriggerCallback;                   /* Legacy weak Trigger Callback */
05491         break;
05492
05493       case HAL_TIM_TRIGGER_HALF_CB_ID :
05494         htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;           /* Legacy weak Trigger half complete Callback */
05495         break;
05496
05497       case HAL_TIM_IC_CAPTURE_CB_ID :
05498         htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;                /* Legacy weak IC Capture Callback */
05499         break;
05500
05501       case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
05502         htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;        /* Legacy weak IC Capture half complete Callback */
05503         break;
05504
05505       case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
05506         htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;           /* Legacy weak OC Delay Elapsed Callback */
05507         break;
05508
05509       case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
05510         htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;         /* Legacy weak PWM Pulse Finished Callback */
05511         break;
05512
05513       case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
05514         htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */
05515         break;
05516
05517       case HAL_TIM_ERROR_CB_ID :
05518         htim->ErrorCallback                     = HAL_TIM_ErrorCallback;                     /* Legacy weak Error Callback */
05519         break;
05520
05521       case HAL_TIM_COMMUTATION_CB_ID :
05522         htim->CommutationCallback               = HAL_TIMEx_CommutCallback;                  /* Legacy weak Commutation Callback */
05523         break;
05524
05525       case HAL_TIM_COMMUTATION_HALF_CB_ID :
05526         htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;          /* Legacy weak Commutation half complete Callback */
05527         break;
05528
05529       case HAL_TIM_BREAK_CB_ID :
05530         htim->BreakCallback                     = HAL_TIMEx_BreakCallback;                   /* Legacy weak Break Callback */
05531         break;
05532
05533       case HAL_TIM_BREAK2_CB_ID :
05534         htim->Break2Callback                    = HAL_TIMEx_Break2Callback;                  /* Legacy weak Break2 Callback */
05535         break;
05536
05537       default :
05538         /* Return error status */
05539         status =  HAL_ERROR;
05540         break;
05541     }
05542   }
05543   else if (htim->State == HAL_TIM_STATE_RESET)
05544   {
05545     switch (CallbackID)
05546     {
05547       case HAL_TIM_BASE_MSPINIT_CB_ID :
05548         htim->Base_MspInitCallback         = HAL_TIM_Base_MspInit;              /* Legacy weak Base MspInit Callback */
05549         break;
05550
05551       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
05552         htim->Base_MspDeInitCallback       = HAL_TIM_Base_MspDeInit;            /* Legacy weak Base Msp DeInit Callback */
05553         break;
05554
05555       case HAL_TIM_IC_MSPINIT_CB_ID :
05556         htim->IC_MspInitCallback           = HAL_TIM_IC_MspInit;                /* Legacy weak IC Msp Init Callback */
05557         break;
05558
05559       case HAL_TIM_IC_MSPDEINIT_CB_ID :
05560         htim->IC_MspDeInitCallback         = HAL_TIM_IC_MspDeInit;              /* Legacy weak IC Msp DeInit Callback */
05561         break;
05562
05563       case HAL_TIM_OC_MSPINIT_CB_ID :
05564         htim->OC_MspInitCallback           = HAL_TIM_OC_MspInit;                /* Legacy weak OC Msp Init Callback */
05565         break;
05566
05567       case HAL_TIM_OC_MSPDEINIT_CB_ID :
05568         htim->OC_MspDeInitCallback         = HAL_TIM_OC_MspDeInit;              /* Legacy weak OC Msp DeInit Callback */
05569         break;
05570
05571       case HAL_TIM_PWM_MSPINIT_CB_ID :
05572         htim->PWM_MspInitCallback          = HAL_TIM_PWM_MspInit;               /* Legacy weak PWM Msp Init Callback */
05573         break;
05574
05575       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
05576         htim->PWM_MspDeInitCallback        = HAL_TIM_PWM_MspDeInit;             /* Legacy weak PWM Msp DeInit Callback */
05577         break;
05578
05579       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
05580         htim->OnePulse_MspInitCallback     = HAL_TIM_OnePulse_MspInit;          /* Legacy weak One Pulse Msp Init Callback */
05581         break;
05582
05583       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
05584         htim->OnePulse_MspDeInitCallback   = HAL_TIM_OnePulse_MspDeInit;        /* Legacy weak One Pulse Msp DeInit Callback */
05585         break;
05586
05587       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
05588         htim->Encoder_MspInitCallback      = HAL_TIM_Encoder_MspInit;           /* Legacy weak Encoder Msp Init Callback */
05589         break;
05590
05591       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
05592         htim->Encoder_MspDeInitCallback    = HAL_TIM_Encoder_MspDeInit;         /* Legacy weak Encoder Msp DeInit Callback */
05593         break;
05594
05595       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
05596         htim->HallSensor_MspInitCallback   = HAL_TIMEx_HallSensor_MspInit;      /* Legacy weak Hall Sensor Msp Init Callback */
05597         break;
05598
05599       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
05600         htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;    /* Legacy weak Hall Sensor Msp DeInit Callback */
05601         break;
05602
05603       default :
05604         /* Return error status */
05605         status =  HAL_ERROR;
05606         break;
05607     }
05608   }
05609   else
05610   {
05611     /* Return error status */
05612     status =  HAL_ERROR;
05613   }
05614
05615   /* Release Lock */
05616   __HAL_UNLOCK(htim);
05617
05618   return status;
05619 }
05620 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
05621
05622 /**
05623   * @}
05624   */
05625
05626 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
05627   *  @brief   TIM Peripheral State functions
05628   *
05629 @verbatim
05630   ==============================================================================
05631                         ##### Peripheral State functions #####
05632   ==============================================================================
05633     [..]
05634     This subsection permits to get in run-time the status of the peripheral
05635     and the data flow.
05636
05637 @endverbatim
05638   * @{
05639   */
05640
05641 /**
05642   * @brief  Return the TIM Base handle state.
05643   * @param  htim TIM Base handle
05644   * @retval HAL state
05645   */
05646 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
05647 {
05648   return htim->State;
05649 }
05650
05651 /**
05652   * @brief  Return the TIM OC handle state.
05653   * @param  htim TIM Output Compare handle
05654   * @retval HAL state
05655   */
05656 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
05657 {
05658   return htim->State;
05659 }
05660
05661 /**
05662   * @brief  Return the TIM PWM handle state.
05663   * @param  htim TIM handle
05664   * @retval HAL state
05665   */
05666 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
05667 {
05668   return htim->State;
05669 }
05670
05671 /**
05672   * @brief  Return the TIM Input Capture handle state.
05673   * @param  htim TIM IC handle
05674   * @retval HAL state
05675   */
05676 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
05677 {
05678   return htim->State;
05679 }
05680
05681 /**
05682   * @brief  Return the TIM One Pulse Mode handle state.
05683   * @param  htim TIM OPM handle
05684   * @retval HAL state
05685   */
05686 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
05687 {
05688   return htim->State;
05689 }
05690
05691 /**
05692   * @brief  Return the TIM Encoder Mode handle state.
05693   * @param  htim TIM Encoder Interface handle
05694   * @retval HAL state
05695   */
05696 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
05697 {
05698   return htim->State;
05699 }
05700
05701 /**
05702   * @}
05703   */
05704
05705 /**
05706   * @}
05707   */
05708
05709 /** @defgroup TIM_Private_Functions TIM Private Functions
05710   * @{
05711   */
05712
05713 /**
05714   * @brief  TIM DMA error callback
05715   * @param  hdma pointer to DMA handle.
05716   * @retval None
05717   */
05718 void TIM_DMAError(DMA_HandleTypeDef *hdma)
05719 {
05720   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
05721
05722   htim->State = HAL_TIM_STATE_READY;
05723
05724 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
05725   htim->ErrorCallback(htim);
05726 #else
05727   HAL_TIM_ErrorCallback(htim);
05728 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
05729 }
05730
05731 /**
05732   * @brief  TIM DMA Delay Pulse complete callback.
05733   * @param  hdma pointer to DMA handle.
05734   * @retval None
05735   */
05736 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
05737 {
05738   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
05739
05740   htim->State = HAL_TIM_STATE_READY;
05741
05742   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
05743   {
05744     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
05745   }
05746   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
05747   {
05748     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
05749   }
05750   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
05751   {
05752     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
05753   }
05754   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
05755   {
05756     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
05757   }
05758   else
05759   {
05760     /* nothing to do */
05761   }
05762
05763 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
05764   htim->PWM_PulseFinishedCallback(htim);
05765 #else
05766   HAL_TIM_PWM_PulseFinishedCallback(htim);
05767 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
05768
05769   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
05770 }
05771
05772 /**
05773   * @brief  TIM DMA Delay Pulse half complete callback.
05774   * @param  hdma pointer to DMA handle.
05775   * @retval None
05776   */
05777 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
05778 {
05779   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
05780
05781   htim->State = HAL_TIM_STATE_READY;
05782
05783   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
05784   {
05785     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
05786   }
05787   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
05788   {
05789     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
05790   }
05791   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
05792   {
05793     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
05794   }
05795   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
05796   {
05797     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
05798   }
05799   else
05800   {
05801     /* nothing to do */
05802   }
05803
05804 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
05805   htim->PWM_PulseFinishedHalfCpltCallback(htim);
05806 #else
05807   HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
05808 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
05809
05810   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
05811 }
05812
05813 /**
05814   * @brief  TIM DMA Capture complete callback.
05815   * @param  hdma pointer to DMA handle.
05816   * @retval None
05817   */
05818 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
05819 {
05820   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
05821
05822   htim->State = HAL_TIM_STATE_READY;
05823
05824   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
05825   {
05826     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
05827   }
05828   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
05829   {
05830     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
05831   }
05832   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
05833   {
05834     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
05835   }
05836   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
05837   {
05838     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
05839   }
05840   else
05841   {
05842     /* nothing to do */
05843   }
05844
05845 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
05846   htim->IC_CaptureCallback(htim);
05847 #else
05848   HAL_TIM_IC_CaptureCallback(htim);
05849 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
05850
05851   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
05852 }
05853
05854 /**
05855   * @brief  TIM DMA Capture half complete callback.
05856   * @param  hdma pointer to DMA handle.
05857   * @retval None
05858   */
05859 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
05860 {
05861   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
05862
05863   htim->State = HAL_TIM_STATE_READY;
05864
05865   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
05866   {
05867     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
05868   }
05869   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
05870   {
05871     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
05872   }
05873   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
05874   {
05875     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
05876   }
05877   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
05878   {
05879     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
05880   }
05881   else
05882   {
05883     /* nothing to do */
05884   }
05885
05886 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
05887   htim->IC_CaptureHalfCpltCallback(htim);
05888 #else
05889   HAL_TIM_IC_CaptureHalfCpltCallback(htim);
05890 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
05891
05892   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
05893 }
05894
05895 /**
05896   * @brief  TIM DMA Period Elapse complete callback.
05897   * @param  hdma pointer to DMA handle.
05898   * @retval None
05899   */
05900 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
05901 {
05902   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
05903
05904   htim->State = HAL_TIM_STATE_READY;
05905
05906 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
05907   htim->PeriodElapsedCallback(htim);
05908 #else
05909   HAL_TIM_PeriodElapsedCallback(htim);
05910 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
05911 }
05912
05913 /**
05914   * @brief  TIM DMA Period Elapse half complete callback.
05915   * @param  hdma pointer to DMA handle.
05916   * @retval None
05917   */
05918 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
05919 {
05920   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
05921
05922   htim->State = HAL_TIM_STATE_READY;
05923
05924 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
05925   htim->PeriodElapsedHalfCpltCallback(htim);
05926 #else
05927   HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
05928 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
05929 }
05930
05931 /**
05932   * @brief  TIM DMA Trigger callback.
05933   * @param  hdma pointer to DMA handle.
05934   * @retval None
05935   */
05936 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
05937 {
05938   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
05939
05940   htim->State = HAL_TIM_STATE_READY;
05941
05942 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
05943   htim->TriggerCallback(htim);
05944 #else
05945   HAL_TIM_TriggerCallback(htim);
05946 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
05947 }
05948
05949 /**
05950   * @brief  TIM DMA Trigger half complete callback.
05951   * @param  hdma pointer to DMA handle.
05952   * @retval None
05953   */
05954 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
05955 {
05956   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
05957
05958   htim->State = HAL_TIM_STATE_READY;
05959
05960 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
05961   htim->TriggerHalfCpltCallback(htim);
05962 #else
05963   HAL_TIM_TriggerHalfCpltCallback(htim);
05964 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
05965 }
05966
05967 /**
05968   * @brief  Time Base configuration
05969   * @param  TIMx TIM peripheral
05970   * @param  Structure TIM Base configuration structure
05971   * @retval None
05972   */
05973 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
05974 {
05975   uint32_t tmpcr1;
05976   tmpcr1 = TIMx->CR1;
05977
05978   /* Set TIM Time Base Unit parameters ---------------------------------------*/
05979   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
05980   {
05981     /* Select the Counter Mode */
05982     tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
05983     tmpcr1 |= Structure->CounterMode;
05984   }
05985
05986   if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
05987   {
05988     /* Set the clock division */
05989     tmpcr1 &= ~TIM_CR1_CKD;
05990     tmpcr1 |= (uint32_t)Structure->ClockDivision;
05991   }
05992
05993   /* Set the auto-reload preload */
05994   MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
05995
05996   TIMx->CR1 = tmpcr1;
05997
05998   /* Set the Autoreload value */
05999   TIMx->ARR = (uint32_t)Structure->Period ;
06000
06001   /* Set the Prescaler value */
06002   TIMx->PSC = Structure->Prescaler;
06003
06004   if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
06005   {
06006     /* Set the Repetition Counter value */
06007     TIMx->RCR = Structure->RepetitionCounter;
06008   }
06009
06010   /* Generate an update event to reload the Prescaler
06011      and the repetition counter (only for advanced timer) value immediately */
06012   TIMx->EGR = TIM_EGR_UG;
06013 }
06014
06015 /**
06016   * @brief  Timer Output Compare 1 configuration
06017   * @param  TIMx to select the TIM peripheral
06018   * @param  OC_Config The ouput configuration structure
06019   * @retval None
06020   */
06021 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
06022 {
06023   uint32_t tmpccmrx;
06024   uint32_t tmpccer;
06025   uint32_t tmpcr2;
06026
06027   /* Disable the Channel 1: Reset the CC1E Bit */
06028   TIMx->CCER &= ~TIM_CCER_CC1E;
06029
06030   /* Get the TIMx CCER register value */
06031   tmpccer = TIMx->CCER;
06032   /* Get the TIMx CR2 register value */
06033   tmpcr2 =  TIMx->CR2;
06034
06035   /* Get the TIMx CCMR1 register value */
06036   tmpccmrx = TIMx->CCMR1;
06037
06038   /* Reset the Output Compare Mode Bits */
06039   tmpccmrx &= ~TIM_CCMR1_OC1M;
06040   tmpccmrx &= ~TIM_CCMR1_CC1S;
06041   /* Select the Output Compare Mode */
06042   tmpccmrx |= OC_Config->OCMode;
06043
06044   /* Reset the Output Polarity level */
06045   tmpccer &= ~TIM_CCER_CC1P;
06046   /* Set the Output Compare Polarity */
06047   tmpccer |= OC_Config->OCPolarity;
06048
06049   if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
06050   {
06051     /* Check parameters */
06052     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
06053
06054     /* Reset the Output N Polarity level */
06055     tmpccer &= ~TIM_CCER_CC1NP;
06056     /* Set the Output N Polarity */
06057     tmpccer |= OC_Config->OCNPolarity;
06058     /* Reset the Output N State */
06059     tmpccer &= ~TIM_CCER_CC1NE;
06060   }
06061
06062   if (IS_TIM_BREAK_INSTANCE(TIMx))
06063   {
06064     /* Check parameters */
06065     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
06066     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
06067
06068     /* Reset the Output Compare and Output Compare N IDLE State */
06069     tmpcr2 &= ~TIM_CR2_OIS1;
06070     tmpcr2 &= ~TIM_CR2_OIS1N;
06071     /* Set the Output Idle state */
06072     tmpcr2 |= OC_Config->OCIdleState;
06073     /* Set the Output N Idle state */
06074     tmpcr2 |= OC_Config->OCNIdleState;
06075   }
06076
06077   /* Write to TIMx CR2 */
06078   TIMx->CR2 = tmpcr2;
06079
06080   /* Write to TIMx CCMR1 */
06081   TIMx->CCMR1 = tmpccmrx;
06082
06083   /* Set the Capture Compare Register value */
06084   TIMx->CCR1 = OC_Config->Pulse;
06085
06086   /* Write to TIMx CCER */
06087   TIMx->CCER = tmpccer;
06088 }
06089
06090 /**
06091   * @brief  Timer Output Compare 2 configuration
06092   * @param  TIMx to select the TIM peripheral
06093   * @param  OC_Config The ouput configuration structure
06094   * @retval None
06095   */
06096 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
06097 {
06098   uint32_t tmpccmrx;
06099   uint32_t tmpccer;
06100   uint32_t tmpcr2;
06101
06102   /* Disable the Channel 2: Reset the CC2E Bit */
06103   TIMx->CCER &= ~TIM_CCER_CC2E;
06104
06105   /* Get the TIMx CCER register value */
06106   tmpccer = TIMx->CCER;
06107   /* Get the TIMx CR2 register value */
06108   tmpcr2 =  TIMx->CR2;
06109
06110   /* Get the TIMx CCMR1 register value */
06111   tmpccmrx = TIMx->CCMR1;
06112
06113   /* Reset the Output Compare mode and Capture/Compare selection Bits */
06114   tmpccmrx &= ~TIM_CCMR1_OC2M;
06115   tmpccmrx &= ~TIM_CCMR1_CC2S;
06116
06117   /* Select the Output Compare Mode */
06118   tmpccmrx |= (OC_Config->OCMode << 8U);
06119
06120   /* Reset the Output Polarity level */
06121   tmpccer &= ~TIM_CCER_CC2P;
06122   /* Set the Output Compare Polarity */
06123   tmpccer |= (OC_Config->OCPolarity << 4U);
06124
06125   if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
06126   {
06127     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
06128
06129     /* Reset the Output N Polarity level */
06130     tmpccer &= ~TIM_CCER_CC2NP;
06131     /* Set the Output N Polarity */
06132     tmpccer |= (OC_Config->OCNPolarity << 4U);
06133     /* Reset the Output N State */
06134     tmpccer &= ~TIM_CCER_CC2NE;
06135
06136   }
06137
06138   if (IS_TIM_BREAK_INSTANCE(TIMx))
06139   {
06140     /* Check parameters */
06141     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
06142     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
06143
06144     /* Reset the Output Compare and Output Compare N IDLE State */
06145     tmpcr2 &= ~TIM_CR2_OIS2;
06146     tmpcr2 &= ~TIM_CR2_OIS2N;
06147     /* Set the Output Idle state */
06148     tmpcr2 |= (OC_Config->OCIdleState << 2U);
06149     /* Set the Output N Idle state */
06150     tmpcr2 |= (OC_Config->OCNIdleState << 2U);
06151   }
06152
06153   /* Write to TIMx CR2 */
06154   TIMx->CR2 = tmpcr2;
06155
06156   /* Write to TIMx CCMR1 */
06157   TIMx->CCMR1 = tmpccmrx;
06158
06159   /* Set the Capture Compare Register value */
06160   TIMx->CCR2 = OC_Config->Pulse;
06161
06162   /* Write to TIMx CCER */
06163   TIMx->CCER = tmpccer;
06164 }
06165
06166 /**
06167   * @brief  Timer Output Compare 3 configuration
06168   * @param  TIMx to select the TIM peripheral
06169   * @param  OC_Config The ouput configuration structure
06170   * @retval None
06171   */
06172 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
06173 {
06174   uint32_t tmpccmrx;
06175   uint32_t tmpccer;
06176   uint32_t tmpcr2;
06177
06178   /* Disable the Channel 3: Reset the CC2E Bit */
06179   TIMx->CCER &= ~TIM_CCER_CC3E;
06180
06181   /* Get the TIMx CCER register value */
06182   tmpccer = TIMx->CCER;
06183   /* Get the TIMx CR2 register value */
06184   tmpcr2 =  TIMx->CR2;
06185
06186   /* Get the TIMx CCMR2 register value */
06187   tmpccmrx = TIMx->CCMR2;
06188
06189   /* Reset the Output Compare mode and Capture/Compare selection Bits */
06190   tmpccmrx &= ~TIM_CCMR2_OC3M;
06191   tmpccmrx &= ~TIM_CCMR2_CC3S;
06192   /* Select the Output Compare Mode */
06193   tmpccmrx |= OC_Config->OCMode;
06194
06195   /* Reset the Output Polarity level */
06196   tmpccer &= ~TIM_CCER_CC3P;
06197   /* Set the Output Compare Polarity */
06198   tmpccer |= (OC_Config->OCPolarity << 8U);
06199
06200   if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
06201   {
06202     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
06203
06204     /* Reset the Output N Polarity level */
06205     tmpccer &= ~TIM_CCER_CC3NP;
06206     /* Set the Output N Polarity */
06207     tmpccer |= (OC_Config->OCNPolarity << 8U);
06208     /* Reset the Output N State */
06209     tmpccer &= ~TIM_CCER_CC3NE;
06210   }
06211
06212   if (IS_TIM_BREAK_INSTANCE(TIMx))
06213   {
06214     /* Check parameters */
06215     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
06216     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
06217
06218     /* Reset the Output Compare and Output Compare N IDLE State */
06219     tmpcr2 &= ~TIM_CR2_OIS3;
06220     tmpcr2 &= ~TIM_CR2_OIS3N;
06221     /* Set the Output Idle state */
06222     tmpcr2 |= (OC_Config->OCIdleState << 4U);
06223     /* Set the Output N Idle state */
06224     tmpcr2 |= (OC_Config->OCNIdleState << 4U);
06225   }
06226
06227   /* Write to TIMx CR2 */
06228   TIMx->CR2 = tmpcr2;
06229
06230   /* Write to TIMx CCMR2 */
06231   TIMx->CCMR2 = tmpccmrx;
06232
06233   /* Set the Capture Compare Register value */
06234   TIMx->CCR3 = OC_Config->Pulse;
06235
06236   /* Write to TIMx CCER */
06237   TIMx->CCER = tmpccer;
06238 }
06239
06240 /**
06241   * @brief  Timer Output Compare 4 configuration
06242   * @param  TIMx to select the TIM peripheral
06243   * @param  OC_Config The ouput configuration structure
06244   * @retval None
06245   */
06246 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
06247 {
06248   uint32_t tmpccmrx;
06249   uint32_t tmpccer;
06250   uint32_t tmpcr2;
06251
06252   /* Disable the Channel 4: Reset the CC4E Bit */
06253   TIMx->CCER &= ~TIM_CCER_CC4E;
06254
06255   /* Get the TIMx CCER register value */
06256   tmpccer = TIMx->CCER;
06257   /* Get the TIMx CR2 register value */
06258   tmpcr2 =  TIMx->CR2;
06259
06260   /* Get the TIMx CCMR2 register value */
06261   tmpccmrx = TIMx->CCMR2;
06262
06263   /* Reset the Output Compare mode and Capture/Compare selection Bits */
06264   tmpccmrx &= ~TIM_CCMR2_OC4M;
06265   tmpccmrx &= ~TIM_CCMR2_CC4S;
06266
06267   /* Select the Output Compare Mode */
06268   tmpccmrx |= (OC_Config->OCMode << 8U);
06269
06270   /* Reset the Output Polarity level */
06271   tmpccer &= ~TIM_CCER_CC4P;
06272   /* Set the Output Compare Polarity */
06273   tmpccer |= (OC_Config->OCPolarity << 12U);
06274
06275   if (IS_TIM_BREAK_INSTANCE(TIMx))
06276   {
06277     /* Check parameters */
06278     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
06279
06280     /* Reset the Output Compare IDLE State */
06281     tmpcr2 &= ~TIM_CR2_OIS4;
06282
06283     /* Set the Output Idle state */
06284     tmpcr2 |= (OC_Config->OCIdleState << 6U);
06285   }
06286
06287   /* Write to TIMx CR2 */
06288   TIMx->CR2 = tmpcr2;
06289
06290   /* Write to TIMx CCMR2 */
06291   TIMx->CCMR2 = tmpccmrx;
06292
06293   /* Set the Capture Compare Register value */
06294   TIMx->CCR4 = OC_Config->Pulse;
06295
06296   /* Write to TIMx CCER */
06297   TIMx->CCER = tmpccer;
06298 }
06299
06300 /**
06301   * @brief  Timer Output Compare 5 configuration
06302   * @param  TIMx to select the TIM peripheral
06303   * @param  OC_Config The ouput configuration structure
06304   * @retval None
06305   */
06306 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
06307                               TIM_OC_InitTypeDef *OC_Config)
06308 {
06309   uint32_t tmpccmrx;
06310   uint32_t tmpccer;
06311   uint32_t tmpcr2;
06312
06313   /* Disable the output: Reset the CCxE Bit */
06314   TIMx->CCER &= ~TIM_CCER_CC5E;
06315
06316   /* Get the TIMx CCER register value */
06317   tmpccer = TIMx->CCER;
06318   /* Get the TIMx CR2 register value */
06319   tmpcr2 =  TIMx->CR2;
06320   /* Get the TIMx CCMR1 register value */
06321   tmpccmrx = TIMx->CCMR3;
06322
06323   /* Reset the Output Compare Mode Bits */
06324   tmpccmrx &= ~(TIM_CCMR3_OC5M);
06325   /* Select the Output Compare Mode */
06326   tmpccmrx |= OC_Config->OCMode;
06327
06328   /* Reset the Output Polarity level */
06329   tmpccer &= ~TIM_CCER_CC5P;
06330   /* Set the Output Compare Polarity */
06331   tmpccer |= (OC_Config->OCPolarity << 16U);
06332
06333   if (IS_TIM_BREAK_INSTANCE(TIMx))
06334   {
06335     /* Reset the Output Compare IDLE State */
06336     tmpcr2 &= ~TIM_CR2_OIS5;
06337     /* Set the Output Idle state */
06338     tmpcr2 |= (OC_Config->OCIdleState << 8U);
06339   }
06340   /* Write to TIMx CR2 */
06341   TIMx->CR2 = tmpcr2;
06342
06343   /* Write to TIMx CCMR3 */
06344   TIMx->CCMR3 = tmpccmrx;
06345
06346   /* Set the Capture Compare Register value */
06347   TIMx->CCR5 = OC_Config->Pulse;
06348
06349   /* Write to TIMx CCER */
06350   TIMx->CCER = tmpccer;
06351 }
06352
06353 /**
06354   * @brief  Timer Output Compare 6 configuration
06355   * @param  TIMx to select the TIM peripheral
06356   * @param  OC_Config The ouput configuration structure
06357   * @retval None
06358   */
06359 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
06360                               TIM_OC_InitTypeDef *OC_Config)
06361 {
06362   uint32_t tmpccmrx;
06363   uint32_t tmpccer;
06364   uint32_t tmpcr2;
06365
06366   /* Disable the output: Reset the CCxE Bit */
06367   TIMx->CCER &= ~TIM_CCER_CC6E;
06368
06369   /* Get the TIMx CCER register value */
06370   tmpccer = TIMx->CCER;
06371   /* Get the TIMx CR2 register value */
06372   tmpcr2 =  TIMx->CR2;
06373   /* Get the TIMx CCMR1 register value */
06374   tmpccmrx = TIMx->CCMR3;
06375
06376   /* Reset the Output Compare Mode Bits */
06377   tmpccmrx &= ~(TIM_CCMR3_OC6M);
06378   /* Select the Output Compare Mode */
06379   tmpccmrx |= (OC_Config->OCMode << 8U);
06380
06381   /* Reset the Output Polarity level */
06382   tmpccer &= (uint32_t)~TIM_CCER_CC6P;
06383   /* Set the Output Compare Polarity */
06384   tmpccer |= (OC_Config->OCPolarity << 20U);
06385
06386   if (IS_TIM_BREAK_INSTANCE(TIMx))
06387   {
06388     /* Reset the Output Compare IDLE State */
06389     tmpcr2 &= ~TIM_CR2_OIS6;
06390     /* Set the Output Idle state */
06391     tmpcr2 |= (OC_Config->OCIdleState << 10U);
06392   }
06393
06394   /* Write to TIMx CR2 */
06395   TIMx->CR2 = tmpcr2;
06396
06397   /* Write to TIMx CCMR3 */
06398   TIMx->CCMR3 = tmpccmrx;
06399
06400   /* Set the Capture Compare Register value */
06401   TIMx->CCR6 = OC_Config->Pulse;
06402
06403   /* Write to TIMx CCER */
06404   TIMx->CCER = tmpccer;
06405 }
06406
06407 /**
06408   * @brief  Slave Timer configuration function
06409   * @param  htim TIM handle
06410   * @param  sSlaveConfig Slave timer configuration
06411   * @retval None
06412   */
06413 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
06414                                                   TIM_SlaveConfigTypeDef *sSlaveConfig)
06415 {
06416   uint32_t tmpsmcr;
06417   uint32_t tmpccmr1;
06418   uint32_t tmpccer;
06419
06420   /* Get the TIMx SMCR register value */
06421   tmpsmcr = htim->Instance->SMCR;
06422
06423   /* Reset the Trigger Selection Bits */
06424   tmpsmcr &= ~TIM_SMCR_TS;
06425   /* Set the Input Trigger source */
06426   tmpsmcr |= sSlaveConfig->InputTrigger;
06427
06428   /* Reset the slave mode Bits */
06429   tmpsmcr &= ~TIM_SMCR_SMS;
06430   /* Set the slave mode */
06431   tmpsmcr |= sSlaveConfig->SlaveMode;
06432
06433   /* Write to TIMx SMCR */
06434   htim->Instance->SMCR = tmpsmcr;
06435
06436   /* Configure the trigger prescaler, filter, and polarity */
06437   switch (sSlaveConfig->InputTrigger)
06438   {
06439     case TIM_TS_ETRF:
06440     {
06441       /* Check the parameters */
06442       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
06443       assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
06444       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
06445       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
06446       /* Configure the ETR Trigger source */
06447       TIM_ETR_SetConfig(htim->Instance,
06448                         sSlaveConfig->TriggerPrescaler,
06449                         sSlaveConfig->TriggerPolarity,
06450                         sSlaveConfig->TriggerFilter);
06451       break;
06452     }
06453
06454     case TIM_TS_TI1F_ED:
06455     {
06456       /* Check the parameters */
06457       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
06458       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
06459
06460       if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
06461       {
06462         return HAL_ERROR;
06463       }
06464
06465       /* Disable the Channel 1: Reset the CC1E Bit */
06466       tmpccer = htim->Instance->CCER;
06467       htim->Instance->CCER &= ~TIM_CCER_CC1E;
06468       tmpccmr1 = htim->Instance->CCMR1;
06469
06470       /* Set the filter */
06471       tmpccmr1 &= ~TIM_CCMR1_IC1F;
06472       tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
06473
06474       /* Write to TIMx CCMR1 and CCER registers */
06475       htim->Instance->CCMR1 = tmpccmr1;
06476       htim->Instance->CCER = tmpccer;
06477       break;
06478     }
06479
06480     case TIM_TS_TI1FP1:
06481     {
06482       /* Check the parameters */
06483       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
06484       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
06485       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
06486
06487       /* Configure TI1 Filter and Polarity */
06488       TIM_TI1_ConfigInputStage(htim->Instance,
06489                                sSlaveConfig->TriggerPolarity,
06490                                sSlaveConfig->TriggerFilter);
06491       break;
06492     }
06493
06494     case TIM_TS_TI2FP2:
06495     {
06496       /* Check the parameters */
06497       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
06498       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
06499       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
06500
06501       /* Configure TI2 Filter and Polarity */
06502       TIM_TI2_ConfigInputStage(htim->Instance,
06503                                sSlaveConfig->TriggerPolarity,
06504                                sSlaveConfig->TriggerFilter);
06505       break;
06506     }
06507
06508     case TIM_TS_ITR0:
06509     case TIM_TS_ITR1:
06510     case TIM_TS_ITR2:
06511     case TIM_TS_ITR3:
06512     {
06513       /* Check the parameter */
06514       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
06515       break;
06516     }
06517
06518     default:
06519       break;
06520   }
06521   return HAL_OK;
06522 }
06523
06524 /**
06525   * @brief  Configure the TI1 as Input.
06526   * @param  TIMx to select the TIM peripheral.
06527   * @param  TIM_ICPolarity The Input Polarity.
06528   *          This parameter can be one of the following values:
06529   *            @arg TIM_ICPOLARITY_RISING
06530   *            @arg TIM_ICPOLARITY_FALLING
06531   *            @arg TIM_ICPOLARITY_BOTHEDGE
06532   * @param  TIM_ICSelection specifies the input to be used.
06533   *          This parameter can be one of the following values:
06534   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
06535   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
06536   *            @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
06537   * @param  TIM_ICFilter Specifies the Input Capture Filter.
06538   *          This parameter must be a value between 0x00 and 0x0F.
06539   * @retval None
06540   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
06541   *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be
06542   *        protected against un-initialized filter and polarity values.
06543   */
06544 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
06545                        uint32_t TIM_ICFilter)
06546 {
06547   uint32_t tmpccmr1;
06548   uint32_t tmpccer;
06549
06550   /* Disable the Channel 1: Reset the CC1E Bit */
06551   TIMx->CCER &= ~TIM_CCER_CC1E;
06552   tmpccmr1 = TIMx->CCMR1;
06553   tmpccer = TIMx->CCER;
06554
06555   /* Select the Input */
06556   if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
06557   {
06558     tmpccmr1 &= ~TIM_CCMR1_CC1S;
06559     tmpccmr1 |= TIM_ICSelection;
06560   }
06561   else
06562   {
06563     tmpccmr1 |= TIM_CCMR1_CC1S_0;
06564   }
06565
06566   /* Set the filter */
06567   tmpccmr1 &= ~TIM_CCMR1_IC1F;
06568   tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
06569
06570   /* Select the Polarity and set the CC1E Bit */
06571   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
06572   tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
06573
06574   /* Write to TIMx CCMR1 and CCER registers */
06575   TIMx->CCMR1 = tmpccmr1;
06576   TIMx->CCER = tmpccer;
06577 }
06578
06579 /**
06580   * @brief  Configure the Polarity and Filter for TI1.
06581   * @param  TIMx to select the TIM peripheral.
06582   * @param  TIM_ICPolarity The Input Polarity.
06583   *          This parameter can be one of the following values:
06584   *            @arg TIM_ICPOLARITY_RISING
06585   *            @arg TIM_ICPOLARITY_FALLING
06586   *            @arg TIM_ICPOLARITY_BOTHEDGE
06587   * @param  TIM_ICFilter Specifies the Input Capture Filter.
06588   *          This parameter must be a value between 0x00 and 0x0F.
06589   * @retval None
06590   */
06591 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
06592 {
06593   uint32_t tmpccmr1;
06594   uint32_t tmpccer;
06595
06596   /* Disable the Channel 1: Reset the CC1E Bit */
06597   tmpccer = TIMx->CCER;
06598   TIMx->CCER &= ~TIM_CCER_CC1E;
06599   tmpccmr1 = TIMx->CCMR1;
06600
06601   /* Set the filter */
06602   tmpccmr1 &= ~TIM_CCMR1_IC1F;
06603   tmpccmr1 |= (TIM_ICFilter << 4U);
06604
06605   /* Select the Polarity and set the CC1E Bit */
06606   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
06607   tmpccer |= TIM_ICPolarity;
06608
06609   /* Write to TIMx CCMR1 and CCER registers */
06610   TIMx->CCMR1 = tmpccmr1;
06611   TIMx->CCER = tmpccer;
06612 }
06613
06614 /**
06615   * @brief  Configure the TI2 as Input.
06616   * @param  TIMx to select the TIM peripheral
06617   * @param  TIM_ICPolarity The Input Polarity.
06618   *          This parameter can be one of the following values:
06619   *            @arg TIM_ICPOLARITY_RISING
06620   *            @arg TIM_ICPOLARITY_FALLING
06621   *            @arg TIM_ICPOLARITY_BOTHEDGE
06622   * @param  TIM_ICSelection specifies the input to be used.
06623   *          This parameter can be one of the following values:
06624   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
06625   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
06626   *            @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
06627   * @param  TIM_ICFilter Specifies the Input Capture Filter.
06628   *          This parameter must be a value between 0x00 and 0x0F.
06629   * @retval None
06630   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
06631   *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be
06632   *        protected against un-initialized filter and polarity values.
06633   */
06634 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
06635                               uint32_t TIM_ICFilter)
06636 {
06637   uint32_t tmpccmr1;
06638   uint32_t tmpccer;
06639
06640   /* Disable the Channel 2: Reset the CC2E Bit */
06641   TIMx->CCER &= ~TIM_CCER_CC2E;
06642   tmpccmr1 = TIMx->CCMR1;
06643   tmpccer = TIMx->CCER;
06644
06645   /* Select the Input */
06646   tmpccmr1 &= ~TIM_CCMR1_CC2S;
06647   tmpccmr1 |= (TIM_ICSelection << 8U);
06648
06649   /* Set the filter */
06650   tmpccmr1 &= ~TIM_CCMR1_IC2F;
06651   tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
06652
06653   /* Select the Polarity and set the CC2E Bit */
06654   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
06655   tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
06656
06657   /* Write to TIMx CCMR1 and CCER registers */
06658   TIMx->CCMR1 = tmpccmr1 ;
06659   TIMx->CCER = tmpccer;
06660 }
06661
06662 /**
06663   * @brief  Configure the Polarity and Filter for TI2.
06664   * @param  TIMx to select the TIM peripheral.
06665   * @param  TIM_ICPolarity The Input Polarity.
06666   *          This parameter can be one of the following values:
06667   *            @arg TIM_ICPOLARITY_RISING
06668   *            @arg TIM_ICPOLARITY_FALLING
06669   *            @arg TIM_ICPOLARITY_BOTHEDGE
06670   * @param  TIM_ICFilter Specifies the Input Capture Filter.
06671   *          This parameter must be a value between 0x00 and 0x0F.
06672   * @retval None
06673   */
06674 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
06675 {
06676   uint32_t tmpccmr1;
06677   uint32_t tmpccer;
06678
06679   /* Disable the Channel 2: Reset the CC2E Bit */
06680   TIMx->CCER &= ~TIM_CCER_CC2E;
06681   tmpccmr1 = TIMx->CCMR1;
06682   tmpccer = TIMx->CCER;
06683
06684   /* Set the filter */
06685   tmpccmr1 &= ~TIM_CCMR1_IC2F;
06686   tmpccmr1 |= (TIM_ICFilter << 12U);
06687
06688   /* Select the Polarity and set the CC2E Bit */
06689   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
06690   tmpccer |= (TIM_ICPolarity << 4U);
06691
06692   /* Write to TIMx CCMR1 and CCER registers */
06693   TIMx->CCMR1 = tmpccmr1 ;
06694   TIMx->CCER = tmpccer;
06695 }
06696
06697 /**
06698   * @brief  Configure the TI3 as Input.
06699   * @param  TIMx to select the TIM peripheral
06700   * @param  TIM_ICPolarity The Input Polarity.
06701   *          This parameter can be one of the following values:
06702   *            @arg TIM_ICPOLARITY_RISING
06703   *            @arg TIM_ICPOLARITY_FALLING
06704   *            @arg TIM_ICPOLARITY_BOTHEDGE
06705   * @param  TIM_ICSelection specifies the input to be used.
06706   *          This parameter can be one of the following values:
06707   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
06708   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
06709   *            @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
06710   * @param  TIM_ICFilter Specifies the Input Capture Filter.
06711   *          This parameter must be a value between 0x00 and 0x0F.
06712   * @retval None
06713   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
06714   *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
06715   *        protected against un-initialized filter and polarity values.
06716   */
06717 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
06718                               uint32_t TIM_ICFilter)
06719 {
06720   uint32_t tmpccmr2;
06721   uint32_t tmpccer;
06722
06723   /* Disable the Channel 3: Reset the CC3E Bit */
06724   TIMx->CCER &= ~TIM_CCER_CC3E;
06725   tmpccmr2 = TIMx->CCMR2;
06726   tmpccer = TIMx->CCER;
06727
06728   /* Select the Input */
06729   tmpccmr2 &= ~TIM_CCMR2_CC3S;
06730   tmpccmr2 |= TIM_ICSelection;
06731
06732   /* Set the filter */
06733   tmpccmr2 &= ~TIM_CCMR2_IC3F;
06734   tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
06735
06736   /* Select the Polarity and set the CC3E Bit */
06737   tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
06738   tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
06739
06740   /* Write to TIMx CCMR2 and CCER registers */
06741   TIMx->CCMR2 = tmpccmr2;
06742   TIMx->CCER = tmpccer;
06743 }
06744
06745 /**
06746   * @brief  Configure the TI4 as Input.
06747   * @param  TIMx to select the TIM peripheral
06748   * @param  TIM_ICPolarity The Input Polarity.
06749   *          This parameter can be one of the following values:
06750   *            @arg TIM_ICPOLARITY_RISING
06751   *            @arg TIM_ICPOLARITY_FALLING
06752   *            @arg TIM_ICPOLARITY_BOTHEDGE
06753   * @param  TIM_ICSelection specifies the input to be used.
06754   *          This parameter can be one of the following values:
06755   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
06756   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
06757   *            @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
06758   * @param  TIM_ICFilter Specifies the Input Capture Filter.
06759   *          This parameter must be a value between 0x00 and 0x0F.
06760   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
06761   *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
06762   *        protected against un-initialized filter and polarity values.
06763   * @retval None
06764   */
06765 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
06766                               uint32_t TIM_ICFilter)
06767 {
06768   uint32_t tmpccmr2;
06769   uint32_t tmpccer;
06770
06771   /* Disable the Channel 4: Reset the CC4E Bit */
06772   TIMx->CCER &= ~TIM_CCER_CC4E;
06773   tmpccmr2 = TIMx->CCMR2;
06774   tmpccer = TIMx->CCER;
06775
06776   /* Select the Input */
06777   tmpccmr2 &= ~TIM_CCMR2_CC4S;
06778   tmpccmr2 |= (TIM_ICSelection << 8U);
06779
06780   /* Set the filter */
06781   tmpccmr2 &= ~TIM_CCMR2_IC4F;
06782   tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
06783
06784   /* Select the Polarity and set the CC4E Bit */
06785   tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
06786   tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
06787
06788   /* Write to TIMx CCMR2 and CCER registers */
06789   TIMx->CCMR2 = tmpccmr2;
06790   TIMx->CCER = tmpccer ;
06791 }
06792
06793 /**
06794   * @brief  Selects the Input Trigger source
06795   * @param  TIMx to select the TIM peripheral
06796   * @param  InputTriggerSource The Input Trigger source.
06797   *          This parameter can be one of the following values:
06798   *            @arg TIM_TS_ITR0: Internal Trigger 0
06799   *            @arg TIM_TS_ITR1: Internal Trigger 1
06800   *            @arg TIM_TS_ITR2: Internal Trigger 2
06801   *            @arg TIM_TS_ITR3: Internal Trigger 3
06802   *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
06803   *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
06804   *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
06805   *            @arg TIM_TS_ETRF: External Trigger input
06806   * @retval None
06807   */
06808 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
06809 {
06810   uint32_t tmpsmcr;
06811
06812   /* Get the TIMx SMCR register value */
06813   tmpsmcr = TIMx->SMCR;
06814   /* Reset the TS Bits */
06815   tmpsmcr &= ~TIM_SMCR_TS;
06816   /* Set the Input Trigger source and the slave mode*/
06817   tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
06818   /* Write to TIMx SMCR */
06819   TIMx->SMCR = tmpsmcr;
06820 }
06821 /**
06822   * @brief  Configures the TIMx External Trigger (ETR).
06823   * @param  TIMx to select the TIM peripheral
06824   * @param  TIM_ExtTRGPrescaler The external Trigger Prescaler.
06825   *          This parameter can be one of the following values:
06826   *            @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
06827   *            @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
06828   *            @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
06829   *            @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
06830   * @param  TIM_ExtTRGPolarity The external Trigger Polarity.
06831   *          This parameter can be one of the following values:
06832   *            @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
06833   *            @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
06834   * @param  ExtTRGFilter External Trigger Filter.
06835   *          This parameter must be a value between 0x00 and 0x0F
06836   * @retval None
06837   */
06838 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
06839                        uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
06840 {
06841   uint32_t tmpsmcr;
06842
06843   tmpsmcr = TIMx->SMCR;
06844
06845   /* Reset the ETR Bits */
06846   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
06847
06848   /* Set the Prescaler, the Filter value and the Polarity */
06849   tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
06850
06851   /* Write to TIMx SMCR */
06852   TIMx->SMCR = tmpsmcr;
06853 }
06854
06855 /**
06856   * @brief  Enables or disables the TIM Capture Compare Channel x.
06857   * @param  TIMx to select the TIM peripheral
06858   * @param  Channel specifies the TIM Channel
06859   *          This parameter can be one of the following values:
06860   *            @arg TIM_CHANNEL_1: TIM Channel 1
06861   *            @arg TIM_CHANNEL_2: TIM Channel 2
06862   *            @arg TIM_CHANNEL_3: TIM Channel 3
06863   *            @arg TIM_CHANNEL_4: TIM Channel 4
06864   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
06865   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
06866   * @param  ChannelState specifies the TIM Channel CCxE bit new state.
06867   *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
06868   * @retval None
06869   */
06870 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
06871 {
06872   uint32_t tmp;
06873
06874   /* Check the parameters */
06875   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
06876   assert_param(IS_TIM_CHANNELS(Channel));
06877
06878   tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
06879
06880   /* Reset the CCxE Bit */
06881   TIMx->CCER &= ~tmp;
06882
06883   /* Set or reset the CCxE Bit */
06884   TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
06885 }
06886
06887 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
06888 /**
06889   * @brief  Reset interrupt callbacks to the legacy weak callbacks.
06890   * @param  htim pointer to a TIM_HandleTypeDef structure that contains
06891   *                the configuration information for TIM module.
06892   * @retval None
06893   */
06894 void TIM_ResetCallback(TIM_HandleTypeDef *htim)
06895 {
06896   /* Reset the TIM callback to the legacy weak callbacks */
06897   htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;             /* Legacy weak PeriodElapsedCallback             */
06898   htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;     /* Legacy weak PeriodElapsedHalfCpltCallback     */
06899   htim->TriggerCallback                   = HAL_TIM_TriggerCallback;                   /* Legacy weak TriggerCallback                   */
06900   htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;           /* Legacy weak TriggerHalfCpltCallback           */
06901   htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;                /* Legacy weak IC_CaptureCallback                */
06902   htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;        /* Legacy weak IC_CaptureHalfCpltCallback        */
06903   htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;           /* Legacy weak OC_DelayElapsedCallback           */
06904   htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;         /* Legacy weak PWM_PulseFinishedCallback         */
06905   htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */
06906   htim->ErrorCallback                     = HAL_TIM_ErrorCallback;                     /* Legacy weak ErrorCallback                     */
06907   htim->CommutationCallback               = HAL_TIMEx_CommutCallback;                  /* Legacy weak CommutationCallback               */
06908   htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;          /* Legacy weak CommutationHalfCpltCallback       */
06909   htim->BreakCallback                     = HAL_TIMEx_BreakCallback;                   /* Legacy weak BreakCallback                     */
06910   htim->Break2Callback                    = HAL_TIMEx_Break2Callback;                  /* Legacy weak Break2Callback                    */
06911 }
06912 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
06913
06914 /**
06915   * @}
06916   */
06917
06918 #endif /* HAL_TIM_MODULE_ENABLED */
06919 /**
06920   * @}
06921   */
06922
06923 /**
06924   * @}
06925   */
06926 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:35 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_tim.h Source File

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stm32wbxx_hal_tim.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_tim.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of TIM HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_TIM_H
00022 #define STM32WBxx_HAL_TIM_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 /** @addtogroup STM32WBxx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup TIM
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup TIM_Exported_Types TIM Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief  TIM Time base Configuration Structure definition
00046   */
00047 typedef struct
00048 {
00049   uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
00050                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00051
00052   uint32_t CounterMode;       /*!< Specifies the counter mode.
00053                                    This parameter can be a value of @ref TIM_Counter_Mode */
00054
00055   uint32_t Period;            /*!< Specifies the period value to be loaded into the active
00056                                    Auto-Reload Register at the next update event.
00057                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.  */
00058
00059   uint32_t ClockDivision;     /*!< Specifies the clock division.
00060                                    This parameter can be a value of @ref TIM_ClockDivision */
00061
00062   uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
00063                                     reaches zero, an update event is generated and counting restarts
00064                                     from the RCR value (N).
00065                                     This means in PWM mode that (N+1) corresponds to:
00066                                         - the number of PWM periods in edge-aligned mode
00067                                         - the number of half PWM period in center-aligned mode
00068                                      GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
00069                                      Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
00070
00071   uint32_t AutoReloadPreload;  /*!< Specifies the auto-reload preload.
00072                                    This parameter can be a value of @ref TIM_AutoReloadPreload */
00073 } TIM_Base_InitTypeDef;
00074
00075 /**
00076   * @brief  TIM Output Compare Configuration Structure definition
00077   */
00078 typedef struct
00079 {
00080   uint32_t OCMode;        /*!< Specifies the TIM mode.
00081                                This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
00082
00083   uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
00084                                This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00085
00086   uint32_t OCPolarity;    /*!< Specifies the output polarity.
00087                                This parameter can be a value of @ref TIM_Output_Compare_Polarity */
00088
00089   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
00090                                This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
00091                                @note This parameter is valid only for timer instances supporting break feature. */
00092
00093   uint32_t OCFastMode;    /*!< Specifies the Fast mode state.
00094                                This parameter can be a value of @ref TIM_Output_Fast_State
00095                                @note This parameter is valid only in PWM1 and PWM2 mode. */
00096
00097
00098   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
00099                                This parameter can be a value of @ref TIM_Output_Compare_Idle_State
00100                                @note This parameter is valid only for timer instances supporting break feature. */
00101
00102   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
00103                                This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
00104                                @note This parameter is valid only for timer instances supporting break feature. */
00105 } TIM_OC_InitTypeDef;
00106
00107 /**
00108   * @brief  TIM One Pulse Mode Configuration Structure definition
00109   */
00110 typedef struct
00111 {
00112   uint32_t OCMode;        /*!< Specifies the TIM mode.
00113                                This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
00114
00115   uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
00116                                This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00117
00118   uint32_t OCPolarity;    /*!< Specifies the output polarity.
00119                                This parameter can be a value of @ref TIM_Output_Compare_Polarity */
00120
00121   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
00122                                This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
00123                                @note This parameter is valid only for timer instances supporting break feature. */
00124
00125   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
00126                                This parameter can be a value of @ref TIM_Output_Compare_Idle_State
00127                                @note This parameter is valid only for timer instances supporting break feature. */
00128
00129   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
00130                                This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
00131                                @note This parameter is valid only for timer instances supporting break feature. */
00132
00133   uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
00134                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00135
00136   uint32_t ICSelection;   /*!< Specifies the input.
00137                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
00138
00139   uint32_t ICFilter;      /*!< Specifies the input capture filter.
00140                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00141 } TIM_OnePulse_InitTypeDef;
00142
00143 /**
00144   * @brief  TIM Input Capture Configuration Structure definition
00145   */
00146 typedef struct
00147 {
00148   uint32_t  ICPolarity;  /*!< Specifies the active edge of the input signal.
00149                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00150
00151   uint32_t ICSelection;  /*!< Specifies the input.
00152                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
00153
00154   uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
00155                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00156
00157   uint32_t ICFilter;     /*!< Specifies the input capture filter.
00158                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00159 } TIM_IC_InitTypeDef;
00160
00161 /**
00162   * @brief  TIM Encoder Configuration Structure definition
00163   */
00164 typedef struct
00165 {
00166   uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.
00167                                This parameter can be a value of @ref TIM_Encoder_Mode */
00168
00169   uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.
00170                                This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
00171
00172   uint32_t IC1Selection;  /*!< Specifies the input.
00173                                This parameter can be a value of @ref TIM_Input_Capture_Selection */
00174
00175   uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.
00176                                This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00177
00178   uint32_t IC1Filter;     /*!< Specifies the input capture filter.
00179                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00180
00181   uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.
00182                                This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
00183
00184   uint32_t IC2Selection;  /*!< Specifies the input.
00185                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
00186
00187   uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.
00188                                This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00189
00190   uint32_t IC2Filter;     /*!< Specifies the input capture filter.
00191                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00192 } TIM_Encoder_InitTypeDef;
00193
00194 /**
00195   * @brief  Clock Configuration Handle Structure definition
00196   */
00197 typedef struct
00198 {
00199   uint32_t ClockSource;     /*!< TIM clock sources
00200                                  This parameter can be a value of @ref TIM_Clock_Source */
00201   uint32_t ClockPolarity;   /*!< TIM clock polarity
00202                                  This parameter can be a value of @ref TIM_Clock_Polarity */
00203   uint32_t ClockPrescaler;  /*!< TIM clock prescaler
00204                                  This parameter can be a value of @ref TIM_Clock_Prescaler */
00205   uint32_t ClockFilter;     /*!< TIM clock filter
00206                                  This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00207 } TIM_ClockConfigTypeDef;
00208
00209 /**
00210   * @brief  TIM Clear Input Configuration Handle Structure definition
00211   */
00212 typedef struct
00213 {
00214   uint32_t ClearInputState;      /*!< TIM clear Input state
00215                                       This parameter can be ENABLE or DISABLE */
00216   uint32_t ClearInputSource;     /*!< TIM clear Input sources
00217                                       This parameter can be a value of @ref TIM_ClearInput_Source */
00218   uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity
00219                                       This parameter can be a value of @ref TIM_ClearInput_Polarity */
00220   uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler
00221                                       This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */
00222   uint32_t ClearInputFilter;     /*!< TIM Clear Input filter
00223                                       This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00224 } TIM_ClearInputConfigTypeDef;
00225
00226 /**
00227   * @brief  TIM Master configuration Structure definition
00228   * @note   Advanced timers provide TRGO2 internal line which is redirected
00229   *         to the ADC
00230   */
00231 typedef struct
00232 {
00233   uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection
00234                                         This parameter can be a value of @ref TIM_Master_Mode_Selection */
00235   uint32_t  MasterOutputTrigger2;  /*!< Trigger output2 (TRGO2) selection
00236                                         This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
00237   uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection
00238                                         This parameter can be a value of @ref TIM_Master_Slave_Mode
00239                                         @note When the Master/slave mode is enabled, the effect of
00240                                         an event on the trigger input (TRGI) is delayed to allow a
00241                                         perfect synchronization between the current timer and its
00242                                         slaves (through TRGO). It is not mandatory in case of timer
00243                                         synchronization mode. */
00244 } TIM_MasterConfigTypeDef;
00245
00246 /**
00247   * @brief  TIM Slave configuration Structure definition
00248   */
00249 typedef struct
00250 {
00251   uint32_t  SlaveMode;         /*!< Slave mode selection
00252                                     This parameter can be a value of @ref TIM_Slave_Mode */
00253   uint32_t  InputTrigger;      /*!< Input Trigger source
00254                                     This parameter can be a value of @ref TIM_Trigger_Selection */
00255   uint32_t  TriggerPolarity;   /*!< Input Trigger polarity
00256                                     This parameter can be a value of @ref TIM_Trigger_Polarity */
00257   uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler
00258                                     This parameter can be a value of @ref TIM_Trigger_Prescaler */
00259   uint32_t  TriggerFilter;     /*!< Input trigger filter
00260                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF  */
00261
00262 } TIM_SlaveConfigTypeDef;
00263
00264 /**
00265   * @brief  TIM Break input(s) and Dead time configuration Structure definition
00266   * @note   2 break inputs can be configured (BKIN and BKIN2) with configurable
00267   *        filter and polarity.
00268   */
00269 typedef struct
00270 {
00271   uint32_t OffStateRunMode;      /*!< TIM off state in run mode
00272                                       This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
00273   uint32_t OffStateIDLEMode;     /*!< TIM off state in IDLE mode
00274                                       This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
00275   uint32_t LockLevel;            /*!< TIM Lock level
00276                                       This parameter can be a value of @ref TIM_Lock_level */
00277   uint32_t DeadTime;             /*!< TIM dead Time
00278                                       This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
00279   uint32_t BreakState;           /*!< TIM Break State
00280                                       This parameter can be a value of @ref TIM_Break_Input_enable_disable */
00281   uint32_t BreakPolarity;        /*!< TIM Break input polarity
00282                                       This parameter can be a value of @ref TIM_Break_Polarity */
00283   uint32_t BreakFilter;          /*!< Specifies the break input filter.
00284                                       This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00285   uint32_t Break2State;          /*!< TIM Break2 State
00286                                       This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
00287   uint32_t Break2Polarity;       /*!< TIM Break2 input polarity
00288                                       This parameter can be a value of @ref TIM_Break2_Polarity */
00289   uint32_t Break2Filter;         /*!< TIM break2 input filter.
00290                                       This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00291   uint32_t AutomaticOutput;      /*!< TIM Automatic Output Enable state
00292                                       This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
00293 } TIM_BreakDeadTimeConfigTypeDef;
00294
00295 /**
00296   * @brief  HAL State structures definition
00297   */
00298 typedef enum
00299 {
00300   HAL_TIM_STATE_RESET             = 0x00U,    /*!< Peripheral not yet initialized or disabled  */
00301   HAL_TIM_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */
00302   HAL_TIM_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */
00303   HAL_TIM_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */
00304   HAL_TIM_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                */
00305 } HAL_TIM_StateTypeDef;
00306
00307 /**
00308   * @brief  HAL Active channel structures definition
00309   */
00310 typedef enum
00311 {
00312   HAL_TIM_ACTIVE_CHANNEL_1        = 0x01U,    /*!< The active channel is 1     */
00313   HAL_TIM_ACTIVE_CHANNEL_2        = 0x02U,    /*!< The active channel is 2     */
00314   HAL_TIM_ACTIVE_CHANNEL_3        = 0x04U,    /*!< The active channel is 3     */
00315   HAL_TIM_ACTIVE_CHANNEL_4        = 0x08U,    /*!< The active channel is 4     */
00316   HAL_TIM_ACTIVE_CHANNEL_5        = 0x10U,    /*!< The active channel is 5     */
00317   HAL_TIM_ACTIVE_CHANNEL_6        = 0x20U,    /*!< The active channel is 6     */
00318   HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00U     /*!< All active channels cleared */
00319 } HAL_TIM_ActiveChannel;
00320
00321 /**
00322   * @brief  TIM Time Base Handle Structure definition
00323   */
00324 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
00325 typedef struct __TIM_HandleTypeDef
00326 #else
00327 typedef struct
00328 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
00329 {
00330   TIM_TypeDef                 *Instance;     /*!< Register base address             */
00331   TIM_Base_InitTypeDef        Init;          /*!< TIM Time Base required parameters */
00332   HAL_TIM_ActiveChannel       Channel;       /*!< Active channel                    */
00333   DMA_HandleTypeDef           *hdma[7];      /*!< DMA Handlers array
00334                                                   This array is accessed by a @ref DMA_Handle_index */
00335   HAL_LockTypeDef             Lock;          /*!< Locking object                    */
00336   __IO HAL_TIM_StateTypeDef   State;         /*!< TIM operation state               */
00337
00338 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
00339   void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM Base Msp Init Callback                              */
00340   void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);            /*!< TIM Base Msp DeInit Callback                            */
00341   void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM IC Msp Init Callback                                */
00342   void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM IC Msp DeInit Callback                              */
00343   void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM OC Msp Init Callback                                */
00344   void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM OC Msp DeInit Callback                              */
00345   void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM PWM Msp Init Callback                               */
00346   void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM PWM Msp DeInit Callback                             */
00347   void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim);          /*!< TIM One Pulse Msp Init Callback                         */
00348   void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM One Pulse Msp DeInit Callback                       */
00349   void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Encoder Msp Init Callback                           */
00350   void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM Encoder Msp DeInit Callback                         */
00351   void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Hall Sensor Msp Init Callback                       */
00352   void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);      /*!< TIM Hall Sensor Msp DeInit Callback                     */
00353   void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM Period Elapsed Callback                             */
00354   void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);     /*!< TIM Period Elapsed half complete Callback               */
00355   void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim);                   /*!< TIM Trigger Callback                                    */
00356   void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Trigger half complete Callback                      */
00357   void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM Input Capture Callback                              */
00358   void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Input Capture half complete Callback                */
00359   void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Output Compare Delay Elapsed Callback               */
00360   void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM PWM Pulse Finished Callback                         */
00361   void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback           */
00362   void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Error Callback                                      */
00363   void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM Commutation Callback                                */
00364   void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);       /*!< TIM Commutation half complete Callback                  */
00365   void (* BreakCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Break Callback                                      */
00366   void (* Break2Callback)(struct __TIM_HandleTypeDef *htim);                    /*!< TIM Break2 Callback                                     */
00367 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
00368 } TIM_HandleTypeDef;
00369
00370 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
00371 /**
00372   * @brief  HAL TIM Callback ID enumeration definition
00373   */
00374 typedef enum
00375 {
00376    HAL_TIM_BASE_MSPINIT_CB_ID            = 0x00U    /*!< TIM Base MspInit Callback ID                              */
00377   ,HAL_TIM_BASE_MSPDEINIT_CB_ID          = 0x01U    /*!< TIM Base MspDeInit Callback ID                            */
00378   ,HAL_TIM_IC_MSPINIT_CB_ID              = 0x02U    /*!< TIM IC MspInit Callback ID                                */
00379   ,HAL_TIM_IC_MSPDEINIT_CB_ID            = 0x03U    /*!< TIM IC MspDeInit Callback ID                              */
00380   ,HAL_TIM_OC_MSPINIT_CB_ID              = 0x04U    /*!< TIM OC MspInit Callback ID                                */
00381   ,HAL_TIM_OC_MSPDEINIT_CB_ID            = 0x05U    /*!< TIM OC MspDeInit Callback ID                              */
00382   ,HAL_TIM_PWM_MSPINIT_CB_ID             = 0x06U    /*!< TIM PWM MspInit Callback ID                               */
00383   ,HAL_TIM_PWM_MSPDEINIT_CB_ID           = 0x07U    /*!< TIM PWM MspDeInit Callback ID                             */
00384   ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID       = 0x08U    /*!< TIM One Pulse MspInit Callback ID                         */
00385   ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID     = 0x09U    /*!< TIM One Pulse MspDeInit Callback ID                       */
00386   ,HAL_TIM_ENCODER_MSPINIT_CB_ID         = 0x0AU    /*!< TIM Encoder MspInit Callback ID                           */
00387   ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID       = 0x0BU    /*!< TIM Encoder MspDeInit Callback ID                         */
00388   ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID     = 0x0CU    /*!< TIM Hall Sensor MspDeInit Callback ID                     */
00389   ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID   = 0x0DU    /*!< TIM Hall Sensor MspDeInit Callback ID                     */
00390   ,HAL_TIM_PERIOD_ELAPSED_CB_ID          = 0x0EU    /*!< TIM Period Elapsed Callback ID                             */
00391   ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID     = 0x0FU    /*!< TIM Period Elapsed half complete Callback ID               */
00392   ,HAL_TIM_TRIGGER_CB_ID                 = 0x10U    /*!< TIM Trigger Callback ID                                    */
00393   ,HAL_TIM_TRIGGER_HALF_CB_ID            = 0x11U    /*!< TIM Trigger half complete Callback ID                      */
00394
00395   ,HAL_TIM_IC_CAPTURE_CB_ID              = 0x12U    /*!< TIM Input Capture Callback ID                              */
00396   ,HAL_TIM_IC_CAPTURE_HALF_CB_ID         = 0x13U    /*!< TIM Input Capture half complete Callback ID                */
00397   ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID        = 0x14U    /*!< TIM Output Compare Delay Elapsed Callback ID               */
00398   ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID      = 0x15U    /*!< TIM PWM Pulse Finished Callback ID           */
00399   ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U    /*!< TIM PWM Pulse Finished half complete Callback ID           */
00400   ,HAL_TIM_ERROR_CB_ID                   = 0x17U    /*!< TIM Error Callback ID                                      */
00401   ,HAL_TIM_COMMUTATION_CB_ID             = 0x18U    /*!< TIM Commutation Callback ID                                */
00402   ,HAL_TIM_COMMUTATION_HALF_CB_ID        = 0x19U    /*!< TIM Commutation half complete Callback ID                  */
00403   ,HAL_TIM_BREAK_CB_ID                   = 0x1AU    /*!< TIM Break Callback ID                                      */
00404   ,HAL_TIM_BREAK2_CB_ID                  = 0x1BU    /*!< TIM Break2 Callback ID                                     */
00405 } HAL_TIM_CallbackIDTypeDef;
00406
00407 /**
00408   * @brief  HAL TIM Callback pointer definition
00409   */
00410 typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to the TIM callback function */
00411
00412 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
00413
00414 /**
00415   * @}
00416   */
00417 /* End of exported types -----------------------------------------------------*/
00418
00419 /* Exported constants --------------------------------------------------------*/
00420 /** @defgroup TIM_Exported_Constants TIM Exported Constants
00421   * @{
00422   */
00423
00424 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source
00425   * @{
00426   */
00427 #define TIM_CLEARINPUTSOURCE_NONE           0x00000000U         /*!< OCREF_CLR is disabled */
00428 #define TIM_CLEARINPUTSOURCE_ETR            0x00000001U         /*!< OCREF_CLR is connected to ETRF input */
00429 #define TIM_CLEARINPUTSOURCE_COMP1          TIM1_AF1_ETRSEL_0   /*!< OCREF_CLR_INT is connected to COMP1 output */
00430 #define TIM_CLEARINPUTSOURCE_COMP2          TIM1_AF1_ETRSEL_1   /*!< OCREF_CLR_INT is connected to COMP2 output */
00431 /**
00432   * @}
00433   */
00434
00435 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address
00436   * @{
00437   */
00438 #define TIM_DMABASE_CR1                    0x00000000U
00439 #define TIM_DMABASE_CR2                    0x00000001U
00440 #define TIM_DMABASE_SMCR                   0x00000002U
00441 #define TIM_DMABASE_DIER                   0x00000003U
00442 #define TIM_DMABASE_SR                     0x00000004U
00443 #define TIM_DMABASE_EGR                    0x00000005U
00444 #define TIM_DMABASE_CCMR1                  0x00000006U
00445 #define TIM_DMABASE_CCMR2                  0x00000007U
00446 #define TIM_DMABASE_CCER                   0x00000008U
00447 #define TIM_DMABASE_CNT                    0x00000009U
00448 #define TIM_DMABASE_PSC                    0x0000000AU
00449 #define TIM_DMABASE_ARR                    0x0000000BU
00450 #define TIM_DMABASE_RCR                    0x0000000CU
00451 #define TIM_DMABASE_CCR1                   0x0000000DU
00452 #define TIM_DMABASE_CCR2                   0x0000000EU
00453 #define TIM_DMABASE_CCR3                   0x0000000FU
00454 #define TIM_DMABASE_CCR4                   0x00000010U
00455 #define TIM_DMABASE_BDTR                   0x00000011U
00456 #define TIM_DMABASE_DCR                    0x00000012U
00457 #define TIM_DMABASE_DMAR                   0x00000013U
00458 #define TIM_DMABASE_OR                     0x00000014U
00459 #define TIM_DMABASE_CCMR3                  0x00000015U
00460 #define TIM_DMABASE_CCR5                   0x00000016U
00461 #define TIM_DMABASE_CCR6                   0x00000017U
00462 #define TIM_DMABASE_AF1                    0x00000018U
00463 #define TIM_DMABASE_AF2                    0x00000019U
00464 /**
00465   * @}
00466   */
00467
00468 /** @defgroup TIM_Event_Source TIM Event Source
00469   * @{
00470   */
00471 #define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG     /*!< Reinitialize the counter and generates an update of the registers */
00472 #define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G   /*!< A capture/compare event is generated on channel 1 */
00473 #define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G   /*!< A capture/compare event is generated on channel 2 */
00474 #define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G   /*!< A capture/compare event is generated on channel 3 */
00475 #define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G   /*!< A capture/compare event is generated on channel 4 */
00476 #define TIM_EVENTSOURCE_COM                 TIM_EGR_COMG   /*!< A commutation event is generated */
00477 #define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG     /*!< A trigger event is generated */
00478 #define TIM_EVENTSOURCE_BREAK               TIM_EGR_BG     /*!< A break event is generated */
00479 #define TIM_EVENTSOURCE_BREAK2              TIM_EGR_B2G    /*!< A break 2 event is generated */
00480 /**
00481   * @}
00482   */
00483
00484 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
00485   * @{
00486   */
00487 #define  TIM_INPUTCHANNELPOLARITY_RISING      0x00000000U                       /*!< Polarity for TIx source */
00488 #define  TIM_INPUTCHANNELPOLARITY_FALLING     TIM_CCER_CC1P                     /*!< Polarity for TIx source */
00489 #define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */
00490 /**
00491   * @}
00492   */
00493
00494 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
00495   * @{
00496   */
00497 #define TIM_ETRPOLARITY_INVERTED              TIM_SMCR_ETP                      /*!< Polarity for ETR source */
00498 #define TIM_ETRPOLARITY_NONINVERTED           0x00000000U                       /*!< Polarity for ETR source */
00499 /**
00500   * @}
00501   */
00502
00503 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
00504   * @{
00505   */
00506 #define TIM_ETRPRESCALER_DIV1                 0x00000000U                       /*!< No prescaler is used */
00507 #define TIM_ETRPRESCALER_DIV2                 TIM_SMCR_ETPS_0                   /*!< ETR input source is divided by 2 */
00508 #define TIM_ETRPRESCALER_DIV4                 TIM_SMCR_ETPS_1                   /*!< ETR input source is divided by 4 */
00509 #define TIM_ETRPRESCALER_DIV8                 TIM_SMCR_ETPS                     /*!< ETR input source is divided by 8 */
00510 /**
00511   * @}
00512   */
00513
00514 /** @defgroup TIM_Counter_Mode TIM Counter Mode
00515   * @{
00516   */
00517 #define TIM_COUNTERMODE_UP                 0x00000000U                          /*!< Counter used as up-counter   */
00518 #define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR                          /*!< Counter used as down-counter */
00519 #define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0                        /*!< Center-aligned mode 1        */
00520 #define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1                        /*!< Center-aligned mode 2        */
00521 #define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS                          /*!< Center-aligned mode 3        */
00522 /**
00523   * @}
00524   */
00525
00526 /** @defgroup TIM_ClockDivision TIM Clock Division
00527   * @{
00528   */
00529 #define TIM_CLOCKDIVISION_DIV1             0x00000000U                          /*!< Clock division: tDTS=tCK_INT   */
00530 #define TIM_CLOCKDIVISION_DIV2             TIM_CR1_CKD_0                        /*!< Clock division: tDTS=2*tCK_INT */
00531 #define TIM_CLOCKDIVISION_DIV4             TIM_CR1_CKD_1                        /*!< Clock division: tDTS=4*tCK_INT */
00532 /**
00533   * @}
00534   */
00535
00536 /** @defgroup TIM_Output_Compare_State TIM Output Compare State
00537   * @{
00538   */
00539 #define TIM_OUTPUTSTATE_DISABLE            0x00000000U                          /*!< Capture/Compare 1 output disabled */
00540 #define TIM_OUTPUTSTATE_ENABLE             TIM_CCER_CC1E                        /*!< Capture/Compare 1 output enabled */
00541 /**
00542   * @}
00543   */
00544
00545 /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
00546   * @{
00547   */
00548 #define TIM_AUTORELOAD_PRELOAD_DISABLE                0x00000000U               /*!< TIMx_ARR register is not buffered */
00549 #define TIM_AUTORELOAD_PRELOAD_ENABLE                 TIM_CR1_ARPE              /*!< TIMx_ARR register is buffered */
00550
00551 /**
00552   * @}
00553   */
00554
00555 /** @defgroup TIM_Output_Fast_State TIM Output Fast State
00556   * @{
00557   */
00558 #define TIM_OCFAST_DISABLE                 0x00000000U                          /*!< Output Compare fast disable */
00559 #define TIM_OCFAST_ENABLE                  TIM_CCMR1_OC1FE                      /*!< Output Compare fast enable  */
00560 /**
00561   * @}
00562   */
00563
00564 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
00565   * @{
00566   */
00567 #define TIM_OUTPUTNSTATE_DISABLE           0x00000000U                          /*!< OCxN is disabled  */
00568 #define TIM_OUTPUTNSTATE_ENABLE            TIM_CCER_CC1NE                       /*!< OCxN is enabled   */
00569 /**
00570   * @}
00571   */
00572
00573 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
00574   * @{
00575   */
00576 #define TIM_OCPOLARITY_HIGH                0x00000000U                          /*!< Capture/Compare output polarity  */
00577 #define TIM_OCPOLARITY_LOW                 TIM_CCER_CC1P                        /*!< Capture/Compare output polarity  */
00578 /**
00579   * @}
00580   */
00581
00582 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
00583   * @{
00584   */
00585 #define TIM_OCNPOLARITY_HIGH               0x00000000U                          /*!< Capture/Compare complementary output polarity */
00586 #define TIM_OCNPOLARITY_LOW                TIM_CCER_CC1NP                       /*!< Capture/Compare complementary output polarity */
00587 /**
00588   * @}
00589   */
00590
00591 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
00592   * @{
00593   */
00594 #define TIM_OCIDLESTATE_SET                TIM_CR2_OIS1                         /*!< Output Idle state: OCx=1 when MOE=0 */
00595 #define TIM_OCIDLESTATE_RESET              0x00000000U                          /*!< Output Idle state: OCx=0 when MOE=0 */
00596 /**
00597   * @}
00598   */
00599
00600 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
00601   * @{
00602   */
00603 #define TIM_OCNIDLESTATE_SET               TIM_CR2_OIS1N                        /*!< Complementary output Idle state: OCxN=1 when MOE=0 */
00604 #define TIM_OCNIDLESTATE_RESET             0x00000000U                          /*!< Complementary output Idle state: OCxN=0 when MOE=0 */
00605 /**
00606   * @}
00607   */
00608
00609 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
00610   * @{
00611   */
00612 #define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING      /*!< Capture triggered by rising edge on timer input                  */
00613 #define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Capture triggered by falling edge on timer input                 */
00614 #define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE    /*!< Capture triggered by both rising and falling edges on timer input*/
00615 /**
00616   * @}
00617   */
00618
00619 /** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
00620   * @{
00621   */
00622 #define  TIM_ENCODERINPUTPOLARITY_RISING   TIM_INPUTCHANNELPOLARITY_RISING      /*!< Encoder input with rising edge polarity  */
00623 #define  TIM_ENCODERINPUTPOLARITY_FALLING  TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Encoder input with falling edge polarity */
00624 /**
00625   * @}
00626   */
00627
00628 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
00629   * @{
00630   */
00631 #define TIM_ICSELECTION_DIRECTTI           TIM_CCMR1_CC1S_0                     /*!< TIM Input 1, 2, 3 or 4 is selected to be
00632                                                                                      connected to IC1, IC2, IC3 or IC4, respectively */
00633 #define TIM_ICSELECTION_INDIRECTTI         TIM_CCMR1_CC1S_1                     /*!< TIM Input 1, 2, 3 or 4 is selected to be
00634                                                                                      connected to IC2, IC1, IC4 or IC3, respectively */
00635 #define TIM_ICSELECTION_TRC                TIM_CCMR1_CC1S                       /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
00636 /**
00637   * @}
00638   */
00639
00640 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
00641   * @{
00642   */
00643 #define TIM_ICPSC_DIV1                     0x00000000U                          /*!< Capture performed each time an edge is detected on the capture input */
00644 #define TIM_ICPSC_DIV2                     TIM_CCMR1_IC1PSC_0                   /*!< Capture performed once every 2 events                                */
00645 #define TIM_ICPSC_DIV4                     TIM_CCMR1_IC1PSC_1                   /*!< Capture performed once every 4 events                                */
00646 #define TIM_ICPSC_DIV8                     TIM_CCMR1_IC1PSC                     /*!< Capture performed once every 8 events                                */
00647 /**
00648   * @}
00649   */
00650
00651 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
00652   * @{
00653   */
00654 #define TIM_OPMODE_SINGLE                  TIM_CR1_OPM                          /*!< Counter stops counting at the next update event */
00655 #define TIM_OPMODE_REPETITIVE              0x00000000U                          /*!< Counter is not stopped at update event          */
00656 /**
00657   * @}
00658   */
00659
00660 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
00661   * @{
00662   */
00663 #define TIM_ENCODERMODE_TI1                      TIM_SMCR_SMS_0                                                      /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level  */
00664 #define TIM_ENCODERMODE_TI2                      TIM_SMCR_SMS_1                                                      /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
00665 #define TIM_ENCODERMODE_TI12                     (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
00666 /**
00667   * @}
00668   */
00669
00670 /** @defgroup TIM_Interrupt_definition TIM interrupt Definition
00671   * @{
00672   */
00673 #define TIM_IT_UPDATE                      TIM_DIER_UIE                         /*!< Update interrupt            */
00674 #define TIM_IT_CC1                         TIM_DIER_CC1IE                       /*!< Capture/Compare 1 interrupt */
00675 #define TIM_IT_CC2                         TIM_DIER_CC2IE                       /*!< Capture/Compare 2 interrupt */
00676 #define TIM_IT_CC3                         TIM_DIER_CC3IE                       /*!< Capture/Compare 3 interrupt */
00677 #define TIM_IT_CC4                         TIM_DIER_CC4IE                       /*!< Capture/Compare 4 interrupt */
00678 #define TIM_IT_COM                         TIM_DIER_COMIE                       /*!< Commutation interrupt       */
00679 #define TIM_IT_TRIGGER                     TIM_DIER_TIE                         /*!< Trigger interrupt           */
00680 #define TIM_IT_BREAK                       TIM_DIER_BIE                         /*!< Break interrupt             */
00681 /**
00682   * @}
00683   */
00684
00685 /** @defgroup TIM_Commutation_Source  TIM Commutation Source
00686   * @{
00687   */
00688 #define TIM_COMMUTATION_TRGI              TIM_CR2_CCUS                          /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */
00689 #define TIM_COMMUTATION_SOFTWARE          0x00000000U                           /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */
00690 /**
00691   * @}
00692   */
00693
00694 /** @defgroup TIM_DMA_sources TIM DMA Sources
00695   * @{
00696   */
00697 #define TIM_DMA_UPDATE                     TIM_DIER_UDE                         /*!< DMA request is triggered by the update event */
00698 #define TIM_DMA_CC1                        TIM_DIER_CC1DE                       /*!< DMA request is triggered by the capture/compare macth 1 event */
00699 #define TIM_DMA_CC2                        TIM_DIER_CC2DE                       /*!< DMA request is triggered by the capture/compare macth 2 event event */
00700 #define TIM_DMA_CC3                        TIM_DIER_CC3DE                       /*!< DMA request is triggered by the capture/compare macth 3 event event */
00701 #define TIM_DMA_CC4                        TIM_DIER_CC4DE                       /*!< DMA request is triggered by the capture/compare macth 4 event event */
00702 #define TIM_DMA_COM                        TIM_DIER_COMDE                       /*!< DMA request is triggered by the commutation event */
00703 #define TIM_DMA_TRIGGER                    TIM_DIER_TDE                         /*!< DMA request is triggered by the trigger event */
00704 /**
00705   * @}
00706   */
00707
00708 /** @defgroup TIM_Flag_definition TIM Flag Definition
00709   * @{
00710   */
00711 #define TIM_FLAG_UPDATE                    TIM_SR_UIF                           /*!< Update interrupt flag         */
00712 #define TIM_FLAG_CC1                       TIM_SR_CC1IF                         /*!< Capture/Compare 1 interrupt flag */
00713 #define TIM_FLAG_CC2                       TIM_SR_CC2IF                         /*!< Capture/Compare 2 interrupt flag */
00714 #define TIM_FLAG_CC3                       TIM_SR_CC3IF                         /*!< Capture/Compare 3 interrupt flag */
00715 #define TIM_FLAG_CC4                       TIM_SR_CC4IF                         /*!< Capture/Compare 4 interrupt flag */
00716 #define TIM_FLAG_CC5                       TIM_SR_CC5IF                         /*!< Capture/Compare 5 interrupt flag */
00717 #define TIM_FLAG_CC6                       TIM_SR_CC6IF                         /*!< Capture/Compare 6 interrupt flag */
00718 #define TIM_FLAG_COM                       TIM_SR_COMIF                         /*!< Commutation interrupt flag    */
00719 #define TIM_FLAG_TRIGGER                   TIM_SR_TIF                           /*!< Trigger interrupt flag        */
00720 #define TIM_FLAG_BREAK                     TIM_SR_BIF                           /*!< Break interrupt flag          */
00721 #define TIM_FLAG_BREAK2                    TIM_SR_B2IF                          /*!< Break 2 interrupt flag        */
00722 #define TIM_FLAG_SYSTEM_BREAK              TIM_SR_SBIF                          /*!< System Break interrupt flag   */
00723 #define TIM_FLAG_CC1OF                     TIM_SR_CC1OF                         /*!< Capture 1 overcapture flag    */
00724 #define TIM_FLAG_CC2OF                     TIM_SR_CC2OF                         /*!< Capture 2 overcapture flag    */
00725 #define TIM_FLAG_CC3OF                     TIM_SR_CC3OF                         /*!< Capture 3 overcapture flag    */
00726 #define TIM_FLAG_CC4OF                     TIM_SR_CC4OF                         /*!< Capture 4 overcapture flag    */
00727 /**
00728   * @}
00729   */
00730
00731 /** @defgroup TIM_Channel TIM Channel
00732   * @{
00733   */
00734 #define TIM_CHANNEL_1                      0x00000000U                          /*!< Capture/compare channel 1 identifier      */
00735 #define TIM_CHANNEL_2                      0x00000004U                          /*!< Capture/compare channel 2 identifier      */
00736 #define TIM_CHANNEL_3                      0x00000008U                          /*!< Capture/compare channel 3 identifier      */
00737 #define TIM_CHANNEL_4                      0x0000000CU                          /*!< Capture/compare channel 4 identifier      */
00738 #define TIM_CHANNEL_5                      0x00000010U                          /*!< Compare channel 5 identifier              */
00739 #define TIM_CHANNEL_6                      0x00000014U                          /*!< Compare channel 6 identifier              */
00740 #define TIM_CHANNEL_ALL                    0x0000003CU                          /*!< Global Capture/compare channel identifier  */
00741 /**
00742   * @}
00743   */
00744
00745 /** @defgroup TIM_Clock_Source TIM Clock Source
00746   * @{
00747   */
00748 #define TIM_CLOCKSOURCE_ETRMODE2    TIM_SMCR_ETPS_1      /*!< External clock source mode 2                          */
00749 #define TIM_CLOCKSOURCE_INTERNAL    TIM_SMCR_ETPS_0      /*!< Internal clock source                                 */
00750 #define TIM_CLOCKSOURCE_ITR0        TIM_TS_ITR0          /*!< External clock source mode 1 (ITR0)                   */
00751 #define TIM_CLOCKSOURCE_ITR1        TIM_TS_ITR1          /*!< External clock source mode 1 (ITR1)                   */
00752 #define TIM_CLOCKSOURCE_ITR2        TIM_TS_ITR2          /*!< External clock source mode 1 (ITR2)                   */
00753 #define TIM_CLOCKSOURCE_ITR3        TIM_TS_ITR3          /*!< External clock source mode 1 (ITR3)                   */
00754 #define TIM_CLOCKSOURCE_TI1ED       TIM_TS_TI1F_ED       /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
00755 #define TIM_CLOCKSOURCE_TI1         TIM_TS_TI1FP1        /*!< External clock source mode 1 (TTI1FP1)                */
00756 #define TIM_CLOCKSOURCE_TI2         TIM_TS_TI2FP2        /*!< External clock source mode 1 (TTI2FP2)                */
00757 #define TIM_CLOCKSOURCE_ETRMODE1    TIM_TS_ETRF          /*!< External clock source mode 1 (ETRF)                   */
00758 /**
00759   * @}
00760   */
00761
00762 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
00763   * @{
00764   */
00765 #define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED           /*!< Polarity for ETRx clock sources */
00766 #define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED        /*!< Polarity for ETRx clock sources */
00767 #define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING    /*!< Polarity for TIx clock sources */
00768 #define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */
00769 #define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */
00770 /**
00771   * @}
00772   */
00773
00774 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
00775   * @{
00776   */
00777 #define TIM_CLOCKPRESCALER_DIV1                 TIM_ETRPRESCALER_DIV1           /*!< No prescaler is used                                                     */
00778 #define TIM_CLOCKPRESCALER_DIV2                 TIM_ETRPRESCALER_DIV2           /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
00779 #define TIM_CLOCKPRESCALER_DIV4                 TIM_ETRPRESCALER_DIV4           /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
00780 #define TIM_CLOCKPRESCALER_DIV8                 TIM_ETRPRESCALER_DIV8           /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
00781 /**
00782   * @}
00783   */
00784
00785 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
00786   * @{
00787   */
00788 #define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx pin */
00789 #define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx pin */
00790 /**
00791   * @}
00792   */
00793
00794 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
00795   * @{
00796   */
00797 #define TIM_CLEARINPUTPRESCALER_DIV1              TIM_ETRPRESCALER_DIV1         /*!< No prescaler is used                                                   */
00798 #define TIM_CLEARINPUTPRESCALER_DIV2              TIM_ETRPRESCALER_DIV2         /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
00799 #define TIM_CLEARINPUTPRESCALER_DIV4              TIM_ETRPRESCALER_DIV4         /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
00800 #define TIM_CLEARINPUTPRESCALER_DIV8              TIM_ETRPRESCALER_DIV8         /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
00801 /**
00802   * @}
00803   */
00804
00805 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
00806   * @{
00807   */
00808 #define TIM_OSSR_ENABLE                          TIM_BDTR_OSSR                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */
00809 #define TIM_OSSR_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
00810 /**
00811   * @}
00812   */
00813
00814 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
00815   * @{
00816   */
00817 #define TIM_OSSI_ENABLE                          TIM_BDTR_OSSI                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */
00818 #define TIM_OSSI_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
00819 /**
00820   * @}
00821   */
00822 /** @defgroup TIM_Lock_level  TIM Lock level
00823   * @{
00824   */
00825 #define TIM_LOCKLEVEL_OFF                  0x00000000U                          /*!< LOCK OFF     */
00826 #define TIM_LOCKLEVEL_1                    TIM_BDTR_LOCK_0                      /*!< LOCK Level 1 */
00827 #define TIM_LOCKLEVEL_2                    TIM_BDTR_LOCK_1                      /*!< LOCK Level 2 */
00828 #define TIM_LOCKLEVEL_3                    TIM_BDTR_LOCK                        /*!< LOCK Level 3 */
00829 /**
00830   * @}
00831   */
00832
00833 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
00834   * @{
00835   */
00836 #define TIM_BREAK_ENABLE                   TIM_BDTR_BKE                         /*!< Break input BRK is enabled  */
00837 #define TIM_BREAK_DISABLE                  0x00000000U                          /*!< Break input BRK is disabled */
00838 /**
00839   * @}
00840   */
00841
00842 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity
00843   * @{
00844   */
00845 #define TIM_BREAKPOLARITY_LOW              0x00000000U                          /*!< Break input BRK is active low  */
00846 #define TIM_BREAKPOLARITY_HIGH             TIM_BDTR_BKP                         /*!< Break input BRK is active high */
00847 /**
00848   * @}
00849   */
00850
00851 /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable
00852   * @{
00853   */
00854 #define TIM_BREAK2_DISABLE                 0x00000000U                          /*!< Break input BRK2 is disabled  */
00855 #define TIM_BREAK2_ENABLE                  TIM_BDTR_BK2E                        /*!< Break input BRK2 is enabled  */
00856 /**
00857   * @}
00858   */
00859
00860 /** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity
00861   * @{
00862   */
00863 #define TIM_BREAK2POLARITY_LOW             0x00000000U                          /*!< Break input BRK2 is active low   */
00864 #define TIM_BREAK2POLARITY_HIGH            TIM_BDTR_BK2P                        /*!< Break input BRK2 is active high  */
00865 /**
00866   * @}
00867   */
00868
00869 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
00870   * @{
00871   */
00872 #define TIM_AUTOMATICOUTPUT_DISABLE        0x00000000U                          /*!< MOE can be set only by software */
00873 #define TIM_AUTOMATICOUTPUT_ENABLE         TIM_BDTR_AOE                         /*!< MOE can be set by software or automatically at the next update event
00874                                                                                     (if none of the break inputs BRK and BRK2 is active) */
00875 /**
00876   * @}
00877   */
00878
00879 /** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3
00880   * @{
00881   */
00882 #define TIM_GROUPCH5_NONE                  0x00000000U                          /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
00883 #define TIM_GROUPCH5_OC1REFC               TIM_CCR5_GC5C1                       /* !< OC1REFC is the logical AND of OC1REFC and OC5REF    */
00884 #define TIM_GROUPCH5_OC2REFC               TIM_CCR5_GC5C2                       /* !< OC2REFC is the logical AND of OC2REFC and OC5REF    */
00885 #define TIM_GROUPCH5_OC3REFC               TIM_CCR5_GC5C3                       /* !< OC3REFC is the logical AND of OC3REFC and OC5REF    */
00886 /**
00887   * @}
00888   */
00889
00890 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
00891   * @{
00892   */
00893 #define TIM_TRGO_RESET            0x00000000U                                      /*!< TIMx_EGR.UG bit is used as trigger output (TRGO)              */
00894 #define TIM_TRGO_ENABLE           TIM_CR2_MMS_0                                    /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO)             */
00895 #define TIM_TRGO_UPDATE           TIM_CR2_MMS_1                                    /*!< Update event is used as trigger output (TRGO)                 */
00896 #define TIM_TRGO_OC1              (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                  /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
00897 #define TIM_TRGO_OC1REF           TIM_CR2_MMS_2                                    /*!< OC1REF signal is used as trigger output (TRGO)                */
00898 #define TIM_TRGO_OC2REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                  /*!< OC2REF signal is used as trigger output(TRGO)                 */
00899 #define TIM_TRGO_OC3REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                  /*!< OC3REF signal is used as trigger output(TRGO)                 */
00900 #define TIM_TRGO_OC4REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)  /*!< OC4REF signal is used as trigger output(TRGO)                 */
00901 /**
00902   * @}
00903   */
00904
00905 /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)
00906   * @{
00907   */
00908 #define TIM_TRGO2_RESET                          0x00000000U                                                         /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2)              */
00909 #define TIM_TRGO2_ENABLE                         TIM_CR2_MMS2_0                                                      /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2)             */
00910 #define TIM_TRGO2_UPDATE                         TIM_CR2_MMS2_1                                                      /*!< Update event is used as trigger output (TRGO2)                 */
00911 #define TIM_TRGO2_OC1                            (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                                   /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */
00912 #define TIM_TRGO2_OC1REF                         TIM_CR2_MMS2_2                                                      /*!< OC1REF signal is used as trigger output (TRGO2)                */
00913 #define TIM_TRGO2_OC2REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                                   /*!< OC2REF signal is used as trigger output (TRGO2)                */
00914 #define TIM_TRGO2_OC3REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)                                   /*!< OC3REF signal is used as trigger output (TRGO2)                */
00915 #define TIM_TRGO2_OC4REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC4REF signal is used as trigger output (TRGO2)                */
00916 #define TIM_TRGO2_OC5REF                         TIM_CR2_MMS2_3                                                      /*!< OC5REF signal is used as trigger output (TRGO2)                */
00917 #define TIM_TRGO2_OC6REF                         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)                                   /*!< OC6REF signal is used as trigger output (TRGO2)                */
00918 #define TIM_TRGO2_OC4REF_RISINGFALLING           (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)                                   /*!< OC4REF rising or falling edges generate pulses on TRGO2        */
00919 #define TIM_TRGO2_OC6REF_RISINGFALLING           (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC6REF rising or falling edges generate pulses on TRGO2        */
00920 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)                                   /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2         */
00921 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING   (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                  /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */
00922 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)                   /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2         */
00923 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING   (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2         */
00924 /**
00925   * @}
00926   */
00927
00928 /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
00929   * @{
00930   */
00931 #define TIM_MASTERSLAVEMODE_ENABLE         TIM_SMCR_MSM                         /*!< No action */
00932 #define TIM_MASTERSLAVEMODE_DISABLE        0x00000000U                          /*!< Master/slave mode is selected */
00933 /**
00934   * @}
00935   */
00936
00937 /** @defgroup TIM_Slave_Mode TIM Slave mode
00938   * @{
00939   */
00940 #define TIM_SLAVEMODE_DISABLE                0x00000000U                                        /*!< Slave mode disabled           */
00941 #define TIM_SLAVEMODE_RESET                  TIM_SMCR_SMS_2                                     /*!< Reset Mode                    */
00942 #define TIM_SLAVEMODE_GATED                  (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)                  /*!< Gated Mode                    */
00943 #define TIM_SLAVEMODE_TRIGGER                (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)                  /*!< Trigger Mode                  */
00944 #define TIM_SLAVEMODE_EXTERNAL1              (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1         */
00945 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER  TIM_SMCR_SMS_3                                     /*!< Combined reset + trigger mode */
00946 /**
00947   * @}
00948   */
00949
00950 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
00951   * @{
00952   */
00953 #define TIM_OCMODE_TIMING                   0x00000000U                                              /*!< Frozen                                 */
00954 #define TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!< Set channel to active level on match   */
00955 #define TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!< Set channel to inactive level on match */
00956 #define TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!< Toggle                                 */
00957 #define TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!< PWM mode 1                             */
00958 #define TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2                             */
00959 #define TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!< Force active level                     */
00960 #define TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!< Force inactive level                   */
00961 #define TIM_OCMODE_RETRIGERRABLE_OPM1      TIM_CCMR1_OC1M_3                                          /*!< Retrigerrable OPM mode 1               */
00962 #define TIM_OCMODE_RETRIGERRABLE_OPM2      (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)                     /*!< Retrigerrable OPM mode 2               */
00963 #define TIM_OCMODE_COMBINED_PWM1           (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)                     /*!< Combined PWM mode 1                    */
00964 #define TIM_OCMODE_COMBINED_PWM2           (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)  /*!< Combined PWM mode 2                    */
00965 #define TIM_OCMODE_ASSYMETRIC_PWM1         (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)  /*!< Asymmetric PWM mode 1                  */
00966 #define TIM_OCMODE_ASSYMETRIC_PWM2         TIM_CCMR1_OC1M                                            /*!< Asymmetric PWM mode 2                  */
00967 /**
00968   * @}
00969   */
00970
00971 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
00972   * @{
00973   */
00974 #define TIM_TS_ITR0          0x00000000U                                                       /*!< Internal Trigger 0 (ITR0)              */
00975 #define TIM_TS_ITR1          TIM_SMCR_TS_0                                                     /*!< Internal Trigger 1 (ITR1)              */
00976 #define TIM_TS_ITR2          TIM_SMCR_TS_1                                                     /*!< Internal Trigger 2 (ITR2)              */
00977 #define TIM_TS_ITR3          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                   /*!< Internal Trigger 3 (ITR3)              */
00978 #define TIM_TS_TI1F_ED       TIM_SMCR_TS_2                                                     /*!< TI1 Edge Detector (TI1F_ED)            */
00979 #define TIM_TS_TI1FP1        (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 1 (TI1FP1)        */
00980 #define TIM_TS_TI2FP2        (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 2 (TI2FP2)        */
00981 #define TIM_TS_ETRF          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                   /*!< Filtered External Trigger input (ETRF) */
00982 #define TIM_TS_NONE          0x0000FFFFU                                                       /*!< No trigger selected                    */
00983 /**
00984   * @}
00985   */
00986
00987 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
00988   * @{
00989   */
00990 #define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED               /*!< Polarity for ETRx trigger sources             */
00991 #define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED            /*!< Polarity for ETRx trigger sources             */
00992 #define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */
00993 #define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */
00994 #define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */
00995 /**
00996   * @}
00997   */
00998
00999 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
01000   * @{
01001   */
01002 #define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1             /*!< No prescaler is used                                                       */
01003 #define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2             /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
01004 #define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4             /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
01005 #define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8             /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
01006 /**
01007   * @}
01008   */
01009
01010 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
01011   * @{
01012   */
01013 #define TIM_TI1SELECTION_CH1               0x00000000U                          /*!< The TIMx_CH1 pin is connected to TI1 input */
01014 #define TIM_TI1SELECTION_XORCOMBINATION    TIM_CR2_TI1S                         /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
01015 /**
01016   * @}
01017   */
01018
01019 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
01020   * @{
01021   */
01022 #define TIM_DMABURSTLENGTH_1TRANSFER       0x00000000U                          /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA   */
01023 #define TIM_DMABURSTLENGTH_2TRANSFERS      0x00000100U                          /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
01024 #define TIM_DMABURSTLENGTH_3TRANSFERS      0x00000200U                          /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
01025 #define TIM_DMABURSTLENGTH_4TRANSFERS      0x00000300U                          /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
01026 #define TIM_DMABURSTLENGTH_5TRANSFERS      0x00000400U                          /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
01027 #define TIM_DMABURSTLENGTH_6TRANSFERS      0x00000500U                          /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
01028 #define TIM_DMABURSTLENGTH_7TRANSFERS      0x00000600U                          /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
01029 #define TIM_DMABURSTLENGTH_8TRANSFERS      0x00000700U                          /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
01030 #define TIM_DMABURSTLENGTH_9TRANSFERS      0x00000800U                          /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
01031 #define TIM_DMABURSTLENGTH_10TRANSFERS     0x00000900U                          /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
01032 #define TIM_DMABURSTLENGTH_11TRANSFERS     0x00000A00U                          /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
01033 #define TIM_DMABURSTLENGTH_12TRANSFERS     0x00000B00U                          /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
01034 #define TIM_DMABURSTLENGTH_13TRANSFERS     0x00000C00U                          /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
01035 #define TIM_DMABURSTLENGTH_14TRANSFERS     0x00000D00U                          /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
01036 #define TIM_DMABURSTLENGTH_15TRANSFERS     0x00000E00U                          /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
01037 #define TIM_DMABURSTLENGTH_16TRANSFERS     0x00000F00U                          /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
01038 #define TIM_DMABURSTLENGTH_17TRANSFERS     0x00001000U                          /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
01039 #define TIM_DMABURSTLENGTH_18TRANSFERS     0x00001100U                          /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
01040 /**
01041   * @}
01042   */
01043
01044 /** @defgroup DMA_Handle_index TIM DMA Handle Index
01045   * @{
01046   */
01047 #define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0000)       /*!< Index of the DMA handle used for Update DMA requests */
01048 #define TIM_DMA_ID_CC1                   ((uint16_t) 0x0001)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
01049 #define TIM_DMA_ID_CC2                   ((uint16_t) 0x0002)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
01050 #define TIM_DMA_ID_CC3                   ((uint16_t) 0x0003)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
01051 #define TIM_DMA_ID_CC4                   ((uint16_t) 0x0004)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
01052 #define TIM_DMA_ID_COMMUTATION           ((uint16_t) 0x0005)       /*!< Index of the DMA handle used for Commutation DMA requests */
01053 #define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x0006)       /*!< Index of the DMA handle used for Trigger DMA requests */
01054 /**
01055   * @}
01056   */
01057
01058 /** @defgroup Channel_CC_State TIM Capture/Compare Channel State
01059   * @{
01060   */
01061 #define TIM_CCx_ENABLE                   0x00000001U                            /*!< Input or output channel is enabled */
01062 #define TIM_CCx_DISABLE                  0x00000000U                            /*!< Input or output channel is disabled */
01063 #define TIM_CCxN_ENABLE                  0x00000004U                            /*!< Complementary output channel is enabled */
01064 #define TIM_CCxN_DISABLE                 0x00000000U                            /*!< Complementary output channel is enabled */
01065 /**
01066   * @}
01067   */
01068
01069 /** @defgroup TIM_Break_System TIM Break System
01070   * @{
01071   */
01072 #define TIM_BREAK_SYSTEM_ECC                 SYSCFG_CFGR2_ECCL   /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */
01073 #define TIM_BREAK_SYSTEM_PVD                 SYSCFG_CFGR2_PVDL   /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */
01074 #define TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR  SYSCFG_CFGR2_SPL    /*!< Enables and locks the SRAM2_PARITY error signal with Break Input of TIM1/8/15/16/17 */
01075 #define TIM_BREAK_SYSTEM_LOCKUP              SYSCFG_CFGR2_CLL    /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */
01076 /**
01077   * @}
01078   */
01079
01080 /**
01081   * @}
01082   */
01083 /* End of exported constants -------------------------------------------------*/
01084
01085 /* Exported macros -----------------------------------------------------------*/
01086 /** @defgroup TIM_Exported_Macros TIM Exported Macros
01087   * @{
01088   */
01089
01090 /** @brief  Reset TIM handle state.
01091   * @param  __HANDLE__ TIM handle.
01092   * @retval None
01093   */
01094 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
01095 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                        \
01096                                                       (__HANDLE__)->State             = HAL_TIM_STATE_RESET; \
01097                                                       (__HANDLE__)->Base_MspInitCallback         = NULL;     \
01098                                                       (__HANDLE__)->Base_MspDeInitCallback       = NULL;     \
01099                                                       (__HANDLE__)->IC_MspInitCallback           = NULL;     \
01100                                                       (__HANDLE__)->IC_MspDeInitCallback         = NULL;     \
01101                                                       (__HANDLE__)->OC_MspInitCallback           = NULL;     \
01102                                                       (__HANDLE__)->OC_MspDeInitCallback         = NULL;     \
01103                                                       (__HANDLE__)->PWM_MspInitCallback          = NULL;     \
01104                                                       (__HANDLE__)->PWM_MspDeInitCallback        = NULL;     \
01105                                                       (__HANDLE__)->OnePulse_MspInitCallback     = NULL;     \
01106                                                       (__HANDLE__)->OnePulse_MspDeInitCallback   = NULL;     \
01107                                                       (__HANDLE__)->Encoder_MspInitCallback      = NULL;     \
01108                                                       (__HANDLE__)->Encoder_MspDeInitCallback    = NULL;     \
01109                                                       (__HANDLE__)->HallSensor_MspInitCallback   = NULL;     \
01110                                                       (__HANDLE__)->HallSensor_MspDeInitCallback = NULL;     \
01111                                                      } while(0)
01112 #else
01113 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
01114 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
01115
01116 /**
01117   * @brief  Enable the TIM peripheral.
01118   * @param  __HANDLE__ TIM handle
01119   * @retval None
01120   */
01121 #define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
01122
01123 /**
01124   * @brief  Enable the TIM main Output.
01125   * @param  __HANDLE__ TIM handle
01126   * @retval None
01127   */
01128 #define __HAL_TIM_MOE_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
01129
01130 /**
01131   * @brief  Disable the TIM peripheral.
01132   * @param  __HANDLE__ TIM handle
01133   * @retval None
01134   */
01135 #define __HAL_TIM_DISABLE(__HANDLE__) \
01136   do { \
01137     if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
01138     { \
01139       if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
01140       { \
01141         (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
01142       } \
01143     } \
01144   } while(0)
01145
01146 /**
01147   * @brief  Disable the TIM main Output.
01148   * @param  __HANDLE__ TIM handle
01149   * @retval None
01150   * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
01151   */
01152 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
01153   do { \
01154     if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
01155     { \
01156       if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
01157       { \
01158         (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
01159       } \
01160     } \
01161   } while(0)
01162
01163 /**
01164   * @brief  Disable the TIM main Output.
01165   * @param  __HANDLE__ TIM handle
01166   * @retval None
01167   * @note The Main Output Enable of a timer instance is disabled unconditionally
01168   */
01169 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__)  (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
01170
01171 /** @brief  Enable the specified TIM interrupt.
01172   * @param  __HANDLE__ specifies the TIM Handle.
01173   * @param  __INTERRUPT__ specifies the TIM interrupt source to enable.
01174   *          This parameter can be one of the following values:
01175   *            @arg TIM_IT_UPDATE: Update interrupt
01176   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
01177   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
01178   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
01179   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
01180   *            @arg TIM_IT_COM:   Commutation interrupt
01181   *            @arg TIM_IT_TRIGGER: Trigger interrupt
01182   *            @arg TIM_IT_BREAK: Break interrupt
01183   * @retval None
01184   */
01185 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
01186
01187 /** @brief  Disable the specified TIM interrupt.
01188   * @param  __HANDLE__ specifies the TIM Handle.
01189   * @param  __INTERRUPT__ specifies the TIM interrupt source to disable.
01190   *          This parameter can be one of the following values:
01191   *            @arg TIM_IT_UPDATE: Update interrupt
01192   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
01193   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
01194   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
01195   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
01196   *            @arg TIM_IT_COM:   Commutation interrupt
01197   *            @arg TIM_IT_TRIGGER: Trigger interrupt
01198   *            @arg TIM_IT_BREAK: Break interrupt
01199   * @retval None
01200   */
01201 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
01202
01203 /** @brief  Enable the specified DMA request.
01204   * @param  __HANDLE__ specifies the TIM Handle.
01205   * @param  __DMA__ specifies the TIM DMA request to enable.
01206   *          This parameter can be one of the following values:
01207   *            @arg TIM_DMA_UPDATE: Update DMA request
01208   *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
01209   *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
01210   *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
01211   *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
01212   *            @arg TIM_DMA_COM:   Commutation DMA request
01213   *            @arg TIM_DMA_TRIGGER: Trigger DMA request
01214   * @retval None
01215   */
01216 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))
01217
01218 /** @brief  Disable the specified DMA request.
01219   * @param  __HANDLE__ specifies the TIM Handle.
01220   * @param  __DMA__ specifies the TIM DMA request to disable.
01221   *          This parameter can be one of the following values:
01222   *            @arg TIM_DMA_UPDATE: Update DMA request
01223   *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
01224   *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
01225   *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
01226   *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
01227   *            @arg TIM_DMA_COM:   Commutation DMA request
01228   *            @arg TIM_DMA_TRIGGER: Trigger DMA request
01229   * @retval None
01230   */
01231 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
01232
01233 /** @brief  Check whether the specified TIM interrupt flag is set or not.
01234   * @param  __HANDLE__ specifies the TIM Handle.
01235   * @param  __FLAG__ specifies the TIM interrupt flag to check.
01236   *        This parameter can be one of the following values:
01237   *            @arg TIM_FLAG_UPDATE: Update interrupt flag
01238   *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
01239   *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
01240   *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
01241   *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
01242   *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag
01243   *            @arg TIM_FLAG_CC6: Compare 6 interrupt flag
01244   *            @arg TIM_FLAG_COM:  Commutation interrupt flag
01245   *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
01246   *            @arg TIM_FLAG_BREAK: Break interrupt flag
01247   *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
01248   *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
01249   *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
01250   *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
01251   *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
01252   *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
01253   * @retval The new state of __FLAG__ (TRUE or FALSE).
01254   */
01255 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
01256
01257 /** @brief  Clear the specified TIM interrupt flag.
01258   * @param  __HANDLE__ specifies the TIM Handle.
01259   * @param  __FLAG__ specifies the TIM interrupt flag to clear.
01260   *        This parameter can be one of the following values:
01261   *            @arg TIM_FLAG_UPDATE: Update interrupt flag
01262   *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
01263   *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
01264   *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
01265   *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
01266   *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag
01267   *            @arg TIM_FLAG_CC6: Compare 6 interrupt flag
01268   *            @arg TIM_FLAG_COM:  Commutation interrupt flag
01269   *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
01270   *            @arg TIM_FLAG_BREAK: Break interrupt flag
01271   *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
01272   *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
01273   *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
01274   *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
01275   *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
01276   *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
01277   * @retval The new state of __FLAG__ (TRUE or FALSE).
01278   */
01279 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR = ~(__FLAG__))
01280
01281 /**
01282   * @brief  Check whether the specified TIM interrupt source is enabled or not.
01283   * @param  __HANDLE__ TIM handle
01284   * @param  __INTERRUPT__ specifies the TIM interrupt source to check.
01285   *          This parameter can be one of the following values:
01286   *            @arg TIM_IT_UPDATE: Update interrupt
01287   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
01288   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
01289   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
01290   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
01291   *            @arg TIM_IT_COM:   Commutation interrupt
01292   *            @arg TIM_IT_TRIGGER: Trigger interrupt
01293   *            @arg TIM_IT_BREAK: Break interrupt
01294   * @retval The state of TIM_IT (SET or RESET).
01295   */
01296 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
01297                                                              == (__INTERRUPT__)) ? SET : RESET)
01298
01299 /** @brief Clear the TIM interrupt pending bits.
01300   * @param  __HANDLE__ TIM handle
01301   * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
01302   *          This parameter can be one of the following values:
01303   *            @arg TIM_IT_UPDATE: Update interrupt
01304   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
01305   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
01306   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
01307   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
01308   *            @arg TIM_IT_COM:   Commutation interrupt
01309   *            @arg TIM_IT_TRIGGER: Trigger interrupt
01310   *            @arg TIM_IT_BREAK: Break interrupt
01311   * @retval None
01312   */
01313 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
01314
01315 /**
01316   * @brief  Indicates whether or not the TIM Counter is used as downcounter.
01317   * @param  __HANDLE__ TIM handle.
01318   * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
01319   * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
01320 mode.
01321   */
01322 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
01323
01324 /**
01325   * @brief  Set the TIM Prescaler on runtime.
01326   * @param  __HANDLE__ TIM handle.
01327   * @param  __PRESC__ specifies the Prescaler new value.
01328   * @retval None
01329   */
01330 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))
01331
01332 /**
01333   * @brief  Set the TIM Counter Register value on runtime.
01334   * @param  __HANDLE__ TIM handle.
01335   * @param  __COUNTER__ specifies the Counter register new value.
01336   * @retval None
01337   */
01338 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__)  ((__HANDLE__)->Instance->CNT = (__COUNTER__))
01339
01340 /**
01341   * @brief  Get the TIM Counter Register value on runtime.
01342   * @param  __HANDLE__ TIM handle.
01343   * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
01344   */
01345 #define __HAL_TIM_GET_COUNTER(__HANDLE__)  ((__HANDLE__)->Instance->CNT)
01346
01347 /**
01348   * @brief  Set the TIM Autoreload Register value on runtime without calling another time any Init function.
01349   * @param  __HANDLE__ TIM handle.
01350   * @param  __AUTORELOAD__ specifies the Counter register new value.
01351   * @retval None
01352   */
01353 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
01354   do{                                                    \
01355     (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
01356     (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
01357   } while(0)
01358
01359 /**
01360   * @brief  Get the TIM Autoreload Register value on runtime.
01361   * @param  __HANDLE__ TIM handle.
01362   * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
01363   */
01364 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__)  ((__HANDLE__)->Instance->ARR)
01365
01366 /**
01367   * @brief  Set the TIM Clock Division value on runtime without calling another time any Init function.
01368   * @param  __HANDLE__ TIM handle.
01369   * @param  __CKD__ specifies the clock division value.
01370   *          This parameter can be one of the following value:
01371   *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
01372   *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
01373   *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
01374   * @retval None
01375   */
01376 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
01377   do{                                                   \
01378     (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD);  \
01379     (__HANDLE__)->Instance->CR1 |= (__CKD__);       \
01380     (__HANDLE__)->Init.ClockDivision = (__CKD__);   \
01381   } while(0)
01382
01383 /**
01384   * @brief  Get the TIM Clock Division value on runtime.
01385   * @param  __HANDLE__ TIM handle.
01386   * @retval The clock division can be one of the following values:
01387   *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
01388   *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
01389   *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
01390   */
01391 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__)  ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
01392
01393 /**
01394   * @brief  Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
01395   * @param  __HANDLE__ TIM handle.
01396   * @param  __CHANNEL__ TIM Channels to be configured.
01397   *          This parameter can be one of the following values:
01398   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01399   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01400   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01401   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01402   * @param  __ICPSC__ specifies the Input Capture4 prescaler new value.
01403   *          This parameter can be one of the following values:
01404   *            @arg TIM_ICPSC_DIV1: no prescaler
01405   *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
01406   *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
01407   *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
01408   * @retval None
01409   */
01410 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
01411   do{                                                    \
01412     TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
01413     TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
01414   } while(0)
01415
01416 /**
01417   * @brief  Get the TIM Input Capture prescaler on runtime.
01418   * @param  __HANDLE__ TIM handle.
01419   * @param  __CHANNEL__ TIM Channels to be configured.
01420   *          This parameter can be one of the following values:
01421   *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value
01422   *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value
01423   *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value
01424   *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value
01425   * @retval The input capture prescaler can be one of the following values:
01426   *            @arg TIM_ICPSC_DIV1: no prescaler
01427   *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
01428   *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
01429   *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
01430   */
01431 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \
01432   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
01433    ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
01434    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
01435    (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
01436
01437 /**
01438   * @brief  Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
01439   * @param  __HANDLE__ TIM handle.
01440   * @param  __CHANNEL__ TIM Channels to be configured.
01441   *          This parameter can be one of the following values:
01442   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01443   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01444   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01445   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01446   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
01447   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
01448   * @param  __COMPARE__ specifies the Capture Compare register new value.
01449   * @retval None
01450   */
01451 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
01452   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
01453    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
01454    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
01455    ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
01456    ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
01457    ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
01458
01459 /**
01460   * @brief  Get the TIM Capture Compare Register value on runtime.
01461   * @param  __HANDLE__ TIM handle.
01462   * @param  __CHANNEL__ TIM Channel associated with the capture compare register
01463   *          This parameter can be one of the following values:
01464   *            @arg TIM_CHANNEL_1: get capture/compare 1 register value
01465   *            @arg TIM_CHANNEL_2: get capture/compare 2 register value
01466   *            @arg TIM_CHANNEL_3: get capture/compare 3 register value
01467   *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
01468   *            @arg TIM_CHANNEL_5: get capture/compare 5 register value
01469   *            @arg TIM_CHANNEL_6: get capture/compare 6 register value
01470   * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
01471   */
01472 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
01473   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
01474    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
01475    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
01476    ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
01477    ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
01478    ((__HANDLE__)->Instance->CCR6))
01479
01480 /**
01481   * @brief  Set the TIM Output compare preload.
01482   * @param  __HANDLE__ TIM handle.
01483   * @param  __CHANNEL__ TIM Channels to be configured.
01484   *          This parameter can be one of the following values:
01485   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01486   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01487   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01488   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01489   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
01490   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
01491   * @retval None
01492   */
01493 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
01494   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
01495    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
01496    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
01497    ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
01498    ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
01499    ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
01500
01501 /**
01502   * @brief  Reset the TIM Output compare preload.
01503   * @param  __HANDLE__ TIM handle.
01504   * @param  __CHANNEL__ TIM Channels to be configured.
01505   *          This parameter can be one of the following values:
01506   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01507   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01508   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01509   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01510   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
01511   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
01512   * @retval None
01513   */
01514 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
01515   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
01516    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
01517    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
01518    ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\
01519    ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\
01520    ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE))
01521
01522 /**
01523   * @brief  Enable fast mode for a given channel.
01524   * @param  __HANDLE__ TIM handle.
01525   * @param  __CHANNEL__ TIM Channels to be configured.
01526   *          This parameter can be one of the following values:
01527   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01528   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01529   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01530   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01531   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
01532   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
01533   * @note  When fast mode is enabled an active edge on the trigger input acts
01534   *        like a compare match on CCx output. Delay to sample the trigger
01535   *        input and to activate CCx output is reduced to 3 clock cycles.
01536   * @note  Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
01537   * @retval None
01538   */
01539 #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
01540   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
01541    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
01542    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
01543    ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\
01544    ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\
01545    ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE))
01546
01547 /**
01548   * @brief  Disable fast mode for a given channel.
01549   * @param  __HANDLE__ TIM handle.
01550   * @param  __CHANNEL__ TIM Channels to be configured.
01551   *          This parameter can be one of the following values:
01552   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01553   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01554   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01555   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01556   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
01557   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
01558   * @note  When fast mode is disabled CCx output behaves normally depending
01559   *        on counter and CCRx values even when the trigger is ON. The minimum
01560   *        delay to activate CCx output when an active edge occurs on the
01561   *        trigger input is 5 clock cycles.
01562   * @retval None
01563   */
01564 #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
01565   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
01566    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
01567    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
01568    ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\
01569    ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\
01570    ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE))
01571
01572 /**
01573   * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register.
01574   * @param  __HANDLE__ TIM handle.
01575   * @note  When the URS bit of the TIMx_CR1 register is set, only counter
01576   *        overflow/underflow generates an update interrupt or DMA request (if
01577   *        enabled)
01578   * @retval None
01579   */
01580 #define __HAL_TIM_URS_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
01581
01582 /**
01583   * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
01584   * @param  __HANDLE__ TIM handle.
01585   * @note  When the URS bit of the TIMx_CR1 register is reset, any of the
01586   *        following events generate an update interrupt or DMA request (if
01587   *        enabled):
01588   *           _ Counter overflow underflow
01589   *           _ Setting the UG bit
01590   *           _ Update generation through the slave mode controller
01591   * @retval None
01592   */
01593 #define __HAL_TIM_URS_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
01594
01595 /**
01596   * @brief  Set the TIM Capture x input polarity on runtime.
01597   * @param  __HANDLE__ TIM handle.
01598   * @param  __CHANNEL__ TIM Channels to be configured.
01599   *          This parameter can be one of the following values:
01600   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01601   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01602   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01603   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01604   * @param  __POLARITY__ Polarity for TIx source
01605   *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
01606   *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
01607   *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
01608   * @retval None
01609   */
01610 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)    \
01611   do{                                                                     \
01612     TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
01613     TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
01614   }while(0)
01615
01616 /**
01617   * @}
01618   */
01619 /* End of exported macros ----------------------------------------------------*/
01620
01621 /* Private constants ---------------------------------------------------------*/
01622 /** @defgroup TIM_Private_Constants TIM Private Constants
01623   * @{
01624   */
01625 /* The counter of a timer instance is disabled only if all the CCx and CCxN
01626    channels have been disabled */
01627 #define TIM_CCER_CCxE_MASK  ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
01628 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
01629 /**
01630   * @}
01631   */
01632 /* End of private constants --------------------------------------------------*/
01633
01634 /* Private macros ------------------------------------------------------------*/
01635 /** @defgroup TIM_Private_Macros TIM Private Macros
01636   * @{
01637   */
01638 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__)  (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)      || \
01639                                              ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1)    || \
01640                                              ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2)    || \
01641                                              ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))
01642
01643 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1)   || \
01644                                    ((__BASE__) == TIM_DMABASE_CR2)   || \
01645                                    ((__BASE__) == TIM_DMABASE_SMCR)  || \
01646                                    ((__BASE__) == TIM_DMABASE_DIER)  || \
01647                                    ((__BASE__) == TIM_DMABASE_SR)    || \
01648                                    ((__BASE__) == TIM_DMABASE_EGR)   || \
01649                                    ((__BASE__) == TIM_DMABASE_CCMR1) || \
01650                                    ((__BASE__) == TIM_DMABASE_CCMR2) || \
01651                                    ((__BASE__) == TIM_DMABASE_CCER)  || \
01652                                    ((__BASE__) == TIM_DMABASE_CNT)   || \
01653                                    ((__BASE__) == TIM_DMABASE_PSC)   || \
01654                                    ((__BASE__) == TIM_DMABASE_ARR)   || \
01655                                    ((__BASE__) == TIM_DMABASE_RCR)   || \
01656                                    ((__BASE__) == TIM_DMABASE_CCR1)  || \
01657                                    ((__BASE__) == TIM_DMABASE_CCR2)  || \
01658                                    ((__BASE__) == TIM_DMABASE_CCR3)  || \
01659                                    ((__BASE__) == TIM_DMABASE_CCR4)  || \
01660                                    ((__BASE__) == TIM_DMABASE_BDTR)  || \
01661                                    ((__BASE__) == TIM_DMABASE_OR)    || \
01662                                    ((__BASE__) == TIM_DMABASE_CCMR3) || \
01663                                    ((__BASE__) == TIM_DMABASE_CCR5)  || \
01664                                    ((__BASE__) == TIM_DMABASE_CCR6)  || \
01665                                    ((__BASE__) == TIM_DMABASE_AF1)   || \
01666                                    ((__BASE__) == TIM_DMABASE_AF2))
01667
01668 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
01669
01670 #define IS_TIM_COUNTER_MODE(__MODE__)      (((__MODE__) == TIM_COUNTERMODE_UP)              || \
01671                                             ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \
01672                                             ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
01673                                             ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
01674                                             ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
01675
01676 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__)  (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
01677                                             ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
01678                                             ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
01679
01680 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
01681                                             ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
01682
01683 #define IS_TIM_FAST_STATE(__STATE__)       (((__STATE__) == TIM_OCFAST_DISABLE) || \
01684                                             ((__STATE__) == TIM_OCFAST_ENABLE))
01685
01686 #define IS_TIM_OC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
01687                                             ((__POLARITY__) == TIM_OCPOLARITY_LOW))
01688
01689 #define IS_TIM_OCN_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
01690                                             ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
01691
01692 #define IS_TIM_OCIDLE_STATE(__STATE__)     (((__STATE__) == TIM_OCIDLESTATE_SET) || \
01693                                             ((__STATE__) == TIM_OCIDLESTATE_RESET))
01694
01695 #define IS_TIM_OCNIDLE_STATE(__STATE__)    (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
01696                                             ((__STATE__) == TIM_OCNIDLESTATE_RESET))
01697
01698 #define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING)   || \
01699                                                       ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
01700
01701 #define IS_TIM_IC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \
01702                                             ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \
01703                                             ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
01704
01705 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
01706                                             ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
01707                                             ((__SELECTION__) == TIM_ICSELECTION_TRC))
01708
01709 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
01710                                             ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
01711                                             ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
01712                                             ((__PRESCALER__) == TIM_ICPSC_DIV8))
01713
01714 #define IS_TIM_OPM_MODE(__MODE__)          (((__MODE__) == TIM_OPMODE_SINGLE) || \
01715                                             ((__MODE__) == TIM_OPMODE_REPETITIVE))
01716
01717 #define IS_TIM_ENCODER_MODE(__MODE__)      (((__MODE__) == TIM_ENCODERMODE_TI1) || \
01718                                             ((__MODE__) == TIM_ENCODERMODE_TI2) || \
01719                                             ((__MODE__) == TIM_ENCODERMODE_TI12))
01720
01721 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
01722
01723 #define IS_TIM_CHANNELS(__CHANNEL__)       (((__CHANNEL__) == TIM_CHANNEL_1) || \
01724                                             ((__CHANNEL__) == TIM_CHANNEL_2) || \
01725                                             ((__CHANNEL__) == TIM_CHANNEL_3) || \
01726                                             ((__CHANNEL__) == TIM_CHANNEL_4) || \
01727                                             ((__CHANNEL__) == TIM_CHANNEL_5) || \
01728                                             ((__CHANNEL__) == TIM_CHANNEL_6) || \
01729                                             ((__CHANNEL__) == TIM_CHANNEL_ALL))
01730
01731 #define IS_TIM_OPM_CHANNELS(__CHANNEL__)   (((__CHANNEL__) == TIM_CHANNEL_1) || \
01732                                             ((__CHANNEL__) == TIM_CHANNEL_2))
01733
01734 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
01735                                                     ((__CHANNEL__) == TIM_CHANNEL_2) || \
01736                                                     ((__CHANNEL__) == TIM_CHANNEL_3))
01737
01738 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
01739                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
01740                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
01741                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
01742                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
01743                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \
01744                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
01745                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
01746                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
01747                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
01748
01749 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \
01750                                             ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
01751                                             ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \
01752                                             ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \
01753                                             ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
01754
01755 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
01756                                               ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
01757                                               ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
01758                                               ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
01759
01760 #define IS_TIM_CLOCKFILTER(__ICFILTER__)      ((__ICFILTER__) <= 0xFU)
01761
01762 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
01763                                                   ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
01764
01765 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
01766                                                     ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
01767                                                     ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
01768                                                     ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
01769
01770 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
01771
01772 #define IS_TIM_OSSR_STATE(__STATE__)       (((__STATE__) == TIM_OSSR_ENABLE) || \
01773                                             ((__STATE__) == TIM_OSSR_DISABLE))
01774
01775 #define IS_TIM_OSSI_STATE(__STATE__)       (((__STATE__) == TIM_OSSI_ENABLE) || \
01776                                             ((__STATE__) == TIM_OSSI_DISABLE))
01777
01778 #define IS_TIM_LOCK_LEVEL(__LEVEL__)       (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
01779                                             ((__LEVEL__) == TIM_LOCKLEVEL_1)   || \
01780                                             ((__LEVEL__) == TIM_LOCKLEVEL_2)   || \
01781                                             ((__LEVEL__) == TIM_LOCKLEVEL_3))
01782
01783 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
01784
01785
01786 #define IS_TIM_BREAK_STATE(__STATE__)      (((__STATE__) == TIM_BREAK_ENABLE) || \
01787                                             ((__STATE__) == TIM_BREAK_DISABLE))
01788
01789 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
01790                                              ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
01791
01792 #define IS_TIM_BREAK2_STATE(__STATE__)     (((__STATE__) == TIM_BREAK2_ENABLE) || \
01793                                             ((__STATE__) == TIM_BREAK2_DISABLE))
01794
01795 #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
01796                                               ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
01797
01798 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
01799                                                   ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
01800
01801 #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
01802
01803 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET)  || \
01804                                         ((__SOURCE__) == TIM_TRGO_ENABLE) || \
01805                                         ((__SOURCE__) == TIM_TRGO_UPDATE) || \
01806                                         ((__SOURCE__) == TIM_TRGO_OC1)    || \
01807                                         ((__SOURCE__) == TIM_TRGO_OC1REF) || \
01808                                         ((__SOURCE__) == TIM_TRGO_OC2REF) || \
01809                                         ((__SOURCE__) == TIM_TRGO_OC3REF) || \
01810                                         ((__SOURCE__) == TIM_TRGO_OC4REF))
01811
01812 #define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET)                        || \
01813                                          ((__SOURCE__) == TIM_TRGO2_ENABLE)                       || \
01814                                          ((__SOURCE__) == TIM_TRGO2_UPDATE)                       || \
01815                                          ((__SOURCE__) == TIM_TRGO2_OC1)                          || \
01816                                          ((__SOURCE__) == TIM_TRGO2_OC1REF)                       || \
01817                                          ((__SOURCE__) == TIM_TRGO2_OC2REF)                       || \
01818                                          ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
01819                                          ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
01820                                          ((__SOURCE__) == TIM_TRGO2_OC4REF)                       || \
01821                                          ((__SOURCE__) == TIM_TRGO2_OC5REF)                       || \
01822                                          ((__SOURCE__) == TIM_TRGO2_OC6REF)                       || \
01823                                          ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING)         || \
01824                                          ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING)         || \
01825                                          ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING)  || \
01826                                          ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
01827                                          ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING)  || \
01828                                          ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
01829
01830 #define IS_TIM_MSM_STATE(__STATE__)      (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
01831                                           ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
01832
01833 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE)   || \
01834                                      ((__MODE__) == TIM_SLAVEMODE_RESET)     || \
01835                                      ((__MODE__) == TIM_SLAVEMODE_GATED)     || \
01836                                      ((__MODE__) == TIM_SLAVEMODE_TRIGGER)   || \
01837                                      ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
01838                                      ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
01839
01840 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1)               || \
01841                                    ((__MODE__) == TIM_OCMODE_PWM2)               || \
01842                                    ((__MODE__) == TIM_OCMODE_COMBINED_PWM1)      || \
01843                                    ((__MODE__) == TIM_OCMODE_COMBINED_PWM2)      || \
01844                                    ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1)    || \
01845                                    ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
01846
01847 #define IS_TIM_OC_MODE(__MODE__)  (((__MODE__) == TIM_OCMODE_TIMING)             || \
01848                                    ((__MODE__) == TIM_OCMODE_ACTIVE)             || \
01849                                    ((__MODE__) == TIM_OCMODE_INACTIVE)           || \
01850                                    ((__MODE__) == TIM_OCMODE_TOGGLE)             || \
01851                                    ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE)      || \
01852                                    ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)    || \
01853                                    ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
01854                                    ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))
01855
01856 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
01857                                                  ((__SELECTION__) == TIM_TS_ITR1) || \
01858                                                  ((__SELECTION__) == TIM_TS_ITR2) || \
01859                                                  ((__SELECTION__) == TIM_TS_ITR3) || \
01860                                                  ((__SELECTION__) == TIM_TS_TI1F_ED) || \
01861                                                  ((__SELECTION__) == TIM_TS_TI1FP1) || \
01862                                                  ((__SELECTION__) == TIM_TS_TI2FP2) || \
01863                                                  ((__SELECTION__) == TIM_TS_ETRF))
01864
01865 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
01866                                                                ((__SELECTION__) == TIM_TS_ITR1) || \
01867                                                                ((__SELECTION__) == TIM_TS_ITR2) || \
01868                                                                ((__SELECTION__) == TIM_TS_ITR3) || \
01869                                                                ((__SELECTION__) == TIM_TS_NONE))
01870
01871 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__)   (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
01872                                                 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
01873                                                 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \
01874                                                 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \
01875                                                 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))
01876
01877 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
01878                                                 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
01879                                                 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
01880                                                 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
01881
01882 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
01883
01884 #define IS_TIM_TI1SELECTION(__TI1SELECTION__)  (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
01885                                                 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
01886
01887 #define IS_TIM_DMA_LENGTH(__LENGTH__)      (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
01888                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
01889                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
01890                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
01891                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
01892                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
01893                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
01894                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
01895                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
01896                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
01897                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
01898                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
01899                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
01900                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
01901                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
01902                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
01903                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
01904                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
01905
01906 #define IS_TIM_IC_FILTER(__ICFILTER__)   ((__ICFILTER__) <= 0xFU)
01907
01908 #define IS_TIM_DEADTIME(__DEADTIME__)    ((__DEADTIME__) <= 0xFFU)
01909
01910 #define IS_TIM_BREAK_SYSTEM(__CONFIG__)    (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC)                  || \
01911                                             ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD)                  || \
01912                                             ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR)   || \
01913                                             ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
01914
01915 #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \
01916                                                        ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
01917
01918 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
01919   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
01920    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
01921    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
01922    ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
01923
01924 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
01925   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
01926    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
01927    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
01928    ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
01929
01930 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
01931   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
01932    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
01933    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
01934    ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
01935
01936 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
01937   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
01938    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
01939    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
01940    ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
01941
01942 /**
01943   * @}
01944   */
01945 /* End of private macros -----------------------------------------------------*/
01946
01947 /* Include TIM HAL Extended module */
01948 #include "stm32wbxx_hal_tim_ex.h"
01949
01950 /* Exported functions --------------------------------------------------------*/
01951 /** @addtogroup TIM_Exported_Functions TIM Exported Functions
01952   * @{
01953   */
01954
01955 /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
01956   *  @brief   Time Base functions
01957   * @{
01958   */
01959 /* Time Base functions ********************************************************/
01960 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
01961 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
01962 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
01963 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
01964 /* Blocking mode: Polling */
01965 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
01966 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
01967 /* Non-Blocking mode: Interrupt */
01968 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
01969 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
01970 /* Non-Blocking mode: DMA */
01971 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
01972 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
01973 /**
01974   * @}
01975   */
01976
01977 /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
01978   *  @brief   TIM Output Compare functions
01979   * @{
01980   */
01981 /* Timer Output Compare functions *********************************************/
01982 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
01983 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
01984 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
01985 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
01986 /* Blocking mode: Polling */
01987 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
01988 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
01989 /* Non-Blocking mode: Interrupt */
01990 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01991 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01992 /* Non-Blocking mode: DMA */
01993 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
01994 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
01995 /**
01996   * @}
01997   */
01998
01999 /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
02000   *  @brief   TIM PWM functions
02001   * @{
02002   */
02003 /* Timer PWM functions ********************************************************/
02004 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
02005 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
02006 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
02007 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
02008 /* Blocking mode: Polling */
02009 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
02010 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
02011 /* Non-Blocking mode: Interrupt */
02012 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
02013 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
02014 /* Non-Blocking mode: DMA */
02015 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
02016 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
02017 /**
02018   * @}
02019   */
02020
02021 /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
02022   *  @brief   TIM Input Capture functions
02023   * @{
02024   */
02025 /* Timer Input Capture functions **********************************************/
02026 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
02027 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
02028 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
02029 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
02030 /* Blocking mode: Polling */
02031 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
02032 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
02033 /* Non-Blocking mode: Interrupt */
02034 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
02035 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
02036 /* Non-Blocking mode: DMA */
02037 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
02038 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
02039 /**
02040   * @}
02041   */
02042
02043 /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
02044   *  @brief   TIM One Pulse functions
02045   * @{
02046   */
02047 /* Timer One Pulse functions **************************************************/
02048 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
02049 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
02050 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
02051 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
02052 /* Blocking mode: Polling */
02053 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
02054 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
02055 /* Non-Blocking mode: Interrupt */
02056 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
02057 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
02058 /**
02059   * @}
02060   */
02061
02062 /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
02063   *  @brief   TIM Encoder functions
02064   * @{
02065   */
02066 /* Timer Encoder functions ****************************************************/
02067 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig);
02068 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
02069 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
02070 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
02071 /* Blocking mode: Polling */
02072 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
02073 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
02074 /* Non-Blocking mode: Interrupt */
02075 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
02076 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
02077 /* Non-Blocking mode: DMA */
02078 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
02079                                             uint32_t *pData2, uint16_t Length);
02080 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
02081 /**
02082   * @}
02083   */
02084
02085 /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
02086   *  @brief   IRQ handler management
02087   * @{
02088   */
02089 /* Interrupt Handler functions  ***********************************************/
02090 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
02091 /**
02092   * @}
02093   */
02094
02095 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
02096   *  @brief   Peripheral Control functions
02097   * @{
02098   */
02099 /* Control functions  *********************************************************/
02100 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
02101 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
02102 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
02103 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
02104                                                  uint32_t OutputChannel,  uint32_t InputChannel);
02105 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
02106                                            uint32_t Channel);
02107 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
02108 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
02109 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
02110 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
02111 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
02112                                               uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);
02113 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
02114 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
02115                                              uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);
02116 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
02117 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
02118 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
02119 /**
02120   * @}
02121   */
02122
02123 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
02124   *  @brief   TIM Callbacks functions
02125   * @{
02126   */
02127 /* Callback in non blocking modes (Interrupt and DMA) *************************/
02128 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
02129 void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
02130 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
02131 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
02132 void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
02133 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
02134 void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
02135 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
02136 void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
02137 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
02138
02139 /* Callbacks Register/UnRegister functions  ***********************************/
02140 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
02141 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
02142                                            pTIM_CallbackTypeDef pCallback);
02143 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
02144 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
02145
02146 /**
02147   * @}
02148   */
02149
02150 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
02151   *  @brief  Peripheral State functions
02152   * @{
02153   */
02154 /* Peripheral State functions  ************************************************/
02155 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
02156 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
02157 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
02158 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
02159 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
02160 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
02161 /**
02162   * @}
02163   */
02164
02165 /**
02166   * @}
02167   */
02168 /* End of exported functions -------------------------------------------------*/
02169
02170 /* Private functions----------------------------------------------------------*/
02171 /** @defgroup TIM_Private_Functions TIM Private Functions
02172   * @{
02173   */
02174 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
02175 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
02176 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
02177 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
02178                        uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
02179
02180 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
02181 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
02182 void TIM_DMAError(DMA_HandleTypeDef *hdma);
02183 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
02184 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
02185 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
02186
02187 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
02188 void TIM_ResetCallback(TIM_HandleTypeDef *htim);
02189 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
02190
02191 /**
02192   * @}
02193   */
02194 /* End of private functions --------------------------------------------------*/
02195
02196 /**
02197   * @}
02198   */
02199
02200 /**
02201   * @}
02202   */
02203
02204 #ifdef __cplusplus
02205 }
02206 #endif
02207
02208 #endif /* STM32WBxx_HAL_TIM_H */
02209
02210 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:35 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_tim_ex.c Source File

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stm32wbxx_hal_tim_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_tim_ex.c
00004   * @author  MCD Application Team
00005   * @brief   TIM HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Timer Extended peripheral:
00008   *           + Time Hall Sensor Interface Initialization
00009   *           + Time Hall Sensor Interface Start
00010   *           + Time Complementary signal break and dead time configuration
00011   *           + Time Master and Slave synchronization configuration
00012   *           + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
00013   *           + Time OCRef clear configuration
00014   *           + Timer remapping capabilities configuration
00015   @verbatim
00016   ==============================================================================
00017                       ##### TIMER Extended features #####
00018   ==============================================================================
00019   [..]
00020     The Timer Extended features include:
00021     (#) Complementary outputs with programmable dead-time for :
00022         (++) Output Compare
00023         (++) PWM generation (Edge and Center-aligned Mode)
00024         (++) One-pulse mode output
00025     (#) Synchronization circuit to control the timer with external signals and to
00026         interconnect several timers together.
00027     (#) Break input to put the timer output signals in reset state or in a known state.
00028     (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
00029         positioning purposes
00030
00031             ##### How to use this driver #####
00032   ==============================================================================
00033     [..]
00034      (#) Initialize the TIM low level resources by implementing the following functions
00035          depending on the selected feature:
00036            (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
00037
00038      (#) Initialize the TIM low level resources :
00039         (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
00040         (##) TIM pins configuration
00041             (+++) Enable the clock for the TIM GPIOs using the following function:
00042               __HAL_RCC_GPIOx_CLK_ENABLE();
00043             (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
00044
00045      (#) The external Clock can be configured, if needed (the default clock is the
00046          internal clock from the APBx), using the following function:
00047          HAL_TIM_ConfigClockSource, the clock configuration should be done before
00048          any start function.
00049
00050      (#) Configure the TIM in the desired functioning mode using one of the
00051          initialization function of this driver:
00052           (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
00053                Timer Hall Sensor Interface and the commutation event with the corresponding
00054                Interrupt and DMA request if needed (Note that One Timer is used to interface
00055                with the Hall sensor Interface and another Timer should be used to use
00056                the commutation event).
00057
00058      (#) Activate the TIM peripheral using one of the start functions:
00059            (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
00060            (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
00061            (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
00062            (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
00063
00064   @endverbatim
00065   ******************************************************************************
00066   * @attention
00067   *
00068   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00069   * All rights reserved.</center></h2>
00070   *
00071   * This software component is licensed by ST under BSD 3-Clause license,
00072   * the "License"; You may not use this file except in compliance with the
00073   * License. You may obtain a copy of the License at:
00074   *                        opensource.org/licenses/BSD-3-Clause
00075   *
00076   ******************************************************************************
00077   */
00078
00079 /* Includes ------------------------------------------------------------------*/
00080 #include "stm32wbxx_hal.h"
00081
00082 /** @addtogroup STM32WBxx_HAL_Driver
00083   * @{
00084   */
00085
00086 /** @defgroup TIMEx TIMEx
00087   * @brief TIM Extended HAL module driver
00088   * @{
00089   */
00090
00091 #ifdef HAL_TIM_MODULE_ENABLED
00092
00093 /* Private typedef -----------------------------------------------------------*/
00094 /* Private define ------------------------------------------------------------*/
00095 /* Private macro -------------------------------------------------------------*/
00096 /** @addtogroup TIMEx_Private_Macros
00097   * @{
00098   */
00099 #define TIM_GET_OR_MASK(__INSTANCE__)                                                  \
00100   (((__INSTANCE__) == TIM1) ? (TIM1_OR_ETR_ADC1_RMP | TIM1_OR_TI1_RMP) :               \
00101    ((__INSTANCE__) == TIM2) ? (TIM2_OR_TI4_RMP | TIM2_OR_ETR_RMP | TIM2_OR_ITR1_RMP) : \
00102    ((__INSTANCE__) == TIM16) ? TIM16_OR_TI1_RMP : TIM17_OR_TI1_RMP)
00103 /**
00104   * @}
00105   */
00106
00107 /* Private variables ---------------------------------------------------------*/
00108 /* Private function prototypes -----------------------------------------------*/
00109 static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
00110
00111 /* Exported functions --------------------------------------------------------*/
00112 /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
00113   * @{
00114   */
00115
00116 /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
00117   * @brief    Timer Hall Sensor functions
00118   *
00119 @verbatim
00120   ==============================================================================
00121                       ##### Timer Hall Sensor functions #####
00122   ==============================================================================
00123   [..]
00124     This section provides functions allowing to:
00125     (+) Initialize and configure TIM HAL Sensor.
00126     (+) De-initialize TIM HAL Sensor.
00127     (+) Start the Hall Sensor Interface.
00128     (+) Stop the Hall Sensor Interface.
00129     (+) Start the Hall Sensor Interface and enable interrupts.
00130     (+) Stop the Hall Sensor Interface and disable interrupts.
00131     (+) Start the Hall Sensor Interface and enable DMA transfers.
00132     (+) Stop the Hall Sensor Interface and disable DMA transfers.
00133
00134 @endverbatim
00135   * @{
00136   */
00137 /**
00138   * @brief  Initializes the TIM Hall Sensor Interface and initialize the associated handle.
00139   * @param  htim TIM Hall Sensor Interface handle
00140   * @param  sConfig TIM Hall Sensor configuration structure
00141   * @retval HAL status
00142   */
00143 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
00144 {
00145   TIM_OC_InitTypeDef OC_Config;
00146
00147   /* Check the TIM handle allocation */
00148   if (htim == NULL)
00149   {
00150     return HAL_ERROR;
00151   }
00152
00153   /* Check the parameters */
00154   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
00155   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
00156   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
00157   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
00158   assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
00159   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
00160   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
00161
00162   if (htim->State == HAL_TIM_STATE_RESET)
00163   {
00164     /* Allocate lock resource and initialize it */
00165     htim->Lock = HAL_UNLOCKED;
00166
00167 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
00168     /* Reset interrupt callbacks to legacy week callbacks */
00169     TIM_ResetCallback(htim);
00170
00171     if (htim->HallSensor_MspInitCallback == NULL)
00172     {
00173       htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
00174     }
00175     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00176     htim->HallSensor_MspInitCallback(htim);
00177 #else
00178     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
00179     HAL_TIMEx_HallSensor_MspInit(htim);
00180 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
00181   }
00182
00183   /* Set the TIM state */
00184   htim->State = HAL_TIM_STATE_BUSY;
00185
00186   /* Configure the Time base in the Encoder Mode */
00187   TIM_Base_SetConfig(htim->Instance, &htim->Init);
00188
00189   /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the  Hall sensor */
00190   TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
00191
00192   /* Reset the IC1PSC Bits */
00193   htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
00194   /* Set the IC1PSC value */
00195   htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
00196
00197   /* Enable the Hall sensor interface (XOR function of the three inputs) */
00198   htim->Instance->CR2 |= TIM_CR2_TI1S;
00199
00200   /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
00201   htim->Instance->SMCR &= ~TIM_SMCR_TS;
00202   htim->Instance->SMCR |= TIM_TS_TI1F_ED;
00203
00204   /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
00205   htim->Instance->SMCR &= ~TIM_SMCR_SMS;
00206   htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
00207
00208   /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
00209   OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
00210   OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
00211   OC_Config.OCMode = TIM_OCMODE_PWM2;
00212   OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
00213   OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
00214   OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
00215   OC_Config.Pulse = sConfig->Commutation_Delay;
00216
00217   TIM_OC2_SetConfig(htim->Instance, &OC_Config);
00218
00219   /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
00220     register to 101 */
00221   htim->Instance->CR2 &= ~TIM_CR2_MMS;
00222   htim->Instance->CR2 |= TIM_TRGO_OC2REF;
00223
00224   /* Initialize the TIM state*/
00225   htim->State = HAL_TIM_STATE_READY;
00226
00227   return HAL_OK;
00228 }
00229
00230 /**
00231   * @brief  DeInitializes the TIM Hall Sensor interface
00232   * @param  htim TIM Hall Sensor Interface handle
00233   * @retval HAL status
00234   */
00235 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
00236 {
00237   /* Check the parameters */
00238   assert_param(IS_TIM_INSTANCE(htim->Instance));
00239
00240   htim->State = HAL_TIM_STATE_BUSY;
00241
00242   /* Disable the TIM Peripheral Clock */
00243   __HAL_TIM_DISABLE(htim);
00244
00245 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
00246   if (htim->HallSensor_MspDeInitCallback == NULL)
00247   {
00248     htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
00249   }
00250   /* DeInit the low level hardware */
00251   htim->HallSensor_MspDeInitCallback(htim);
00252 #else
00253   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00254   HAL_TIMEx_HallSensor_MspDeInit(htim);
00255 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
00256
00257   /* Change TIM state */
00258   htim->State = HAL_TIM_STATE_RESET;
00259
00260   /* Release Lock */
00261   __HAL_UNLOCK(htim);
00262
00263   return HAL_OK;
00264 }
00265
00266 /**
00267   * @brief  Initializes the TIM Hall Sensor MSP.
00268   * @param  htim TIM Hall Sensor Interface handle
00269   * @retval None
00270   */
00271 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
00272 {
00273   /* Prevent unused argument(s) compilation warning */
00274   UNUSED(htim);
00275
00276   /* NOTE : This function should not be modified, when the callback is needed,
00277             the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
00278    */
00279 }
00280
00281 /**
00282   * @brief  DeInitializes TIM Hall Sensor MSP.
00283   * @param  htim TIM Hall Sensor Interface handle
00284   * @retval None
00285   */
00286 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
00287 {
00288   /* Prevent unused argument(s) compilation warning */
00289   UNUSED(htim);
00290
00291   /* NOTE : This function should not be modified, when the callback is needed,
00292             the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
00293    */
00294 }
00295
00296 /**
00297   * @brief  Starts the TIM Hall Sensor Interface.
00298   * @param  htim TIM Hall Sensor Interface handle
00299   * @retval HAL status
00300   */
00301 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
00302 {
00303   uint32_t tmpsmcr;
00304
00305   /* Check the parameters */
00306   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
00307
00308   /* Enable the Input Capture channel 1
00309     (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00310   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
00311
00312   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00313   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00314   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00315   {
00316     __HAL_TIM_ENABLE(htim);
00317   }
00318
00319   /* Return function status */
00320   return HAL_OK;
00321 }
00322
00323 /**
00324   * @brief  Stops the TIM Hall sensor Interface.
00325   * @param  htim TIM Hall Sensor Interface handle
00326   * @retval HAL status
00327   */
00328 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
00329 {
00330   /* Check the parameters */
00331   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
00332
00333   /* Disable the Input Capture channels 1, 2 and 3
00334     (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00335   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
00336
00337   /* Disable the Peripheral */
00338   __HAL_TIM_DISABLE(htim);
00339
00340   /* Return function status */
00341   return HAL_OK;
00342 }
00343
00344 /**
00345   * @brief  Starts the TIM Hall Sensor Interface in interrupt mode.
00346   * @param  htim TIM Hall Sensor Interface handle
00347   * @retval HAL status
00348   */
00349 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
00350 {
00351   uint32_t tmpsmcr;
00352
00353   /* Check the parameters */
00354   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
00355
00356   /* Enable the capture compare Interrupts 1 event */
00357   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00358
00359   /* Enable the Input Capture channel 1
00360     (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00361   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
00362
00363   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00364   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00365   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00366   {
00367     __HAL_TIM_ENABLE(htim);
00368   }
00369
00370   /* Return function status */
00371   return HAL_OK;
00372 }
00373
00374 /**
00375   * @brief  Stops the TIM Hall Sensor Interface in interrupt mode.
00376   * @param  htim TIM Hall Sensor Interface handle
00377   * @retval HAL status
00378   */
00379 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
00380 {
00381   /* Check the parameters */
00382   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
00383
00384   /* Disable the Input Capture channel 1
00385     (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00386   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
00387
00388   /* Disable the capture compare Interrupts event */
00389   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
00390
00391   /* Disable the Peripheral */
00392   __HAL_TIM_DISABLE(htim);
00393
00394   /* Return function status */
00395   return HAL_OK;
00396 }
00397
00398 /**
00399   * @brief  Starts the TIM Hall Sensor Interface in DMA mode.
00400   * @param  htim TIM Hall Sensor Interface handle
00401   * @param  pData The destination Buffer address.
00402   * @param  Length The length of data to be transferred from TIM peripheral to memory.
00403   * @retval HAL status
00404   */
00405 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
00406 {
00407   uint32_t tmpsmcr;
00408
00409   /* Check the parameters */
00410   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
00411
00412   if (htim->State == HAL_TIM_STATE_BUSY)
00413   {
00414     return HAL_BUSY;
00415   }
00416   else if (htim->State == HAL_TIM_STATE_READY)
00417   {
00418     if (((uint32_t)pData == 0U) && (Length > 0U))
00419     {
00420       return HAL_ERROR;
00421     }
00422     else
00423     {
00424       htim->State = HAL_TIM_STATE_BUSY;
00425     }
00426   }
00427   else
00428   {
00429     /* nothing to do */
00430   }
00431   /* Enable the Input Capture channel 1
00432     (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00433   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
00434
00435   /* Set the DMA Input Capture 1 Callbacks */
00436   htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
00437   htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
00438   /* Set the DMA error callback */
00439   htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
00440
00441   /* Enable the DMA channel for Capture 1*/
00442   if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
00443   {
00444     return HAL_ERROR;
00445   }
00446   /* Enable the capture compare 1 Interrupt */
00447   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
00448
00449   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00450   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00451   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00452   {
00453     __HAL_TIM_ENABLE(htim);
00454   }
00455
00456   /* Return function status */
00457   return HAL_OK;
00458 }
00459
00460 /**
00461   * @brief  Stops the TIM Hall Sensor Interface in DMA mode.
00462   * @param  htim TIM Hall Sensor Interface handle
00463   * @retval HAL status
00464   */
00465 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
00466 {
00467   /* Check the parameters */
00468   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
00469
00470   /* Disable the Input Capture channel 1
00471     (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00472   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
00473
00474
00475   /* Disable the capture compare Interrupts 1 event */
00476   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
00477
00478   (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
00479   /* Disable the Peripheral */
00480   __HAL_TIM_DISABLE(htim);
00481
00482   /* Return function status */
00483   return HAL_OK;
00484 }
00485
00486 /**
00487   * @}
00488   */
00489
00490 /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
00491   *  @brief   Timer Complementary Output Compare functions
00492   *
00493 @verbatim
00494   ==============================================================================
00495               ##### Timer Complementary Output Compare functions #####
00496   ==============================================================================
00497   [..]
00498     This section provides functions allowing to:
00499     (+) Start the Complementary Output Compare/PWM.
00500     (+) Stop the Complementary Output Compare/PWM.
00501     (+) Start the Complementary Output Compare/PWM and enable interrupts.
00502     (+) Stop the Complementary Output Compare/PWM and disable interrupts.
00503     (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
00504     (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
00505
00506 @endverbatim
00507   * @{
00508   */
00509
00510 /**
00511   * @brief  Starts the TIM Output Compare signal generation on the complementary
00512   *         output.
00513   * @param  htim TIM Output Compare handle
00514   * @param  Channel TIM Channel to be enabled
00515   *          This parameter can be one of the following values:
00516   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00517   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00518   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00519   * @retval HAL status
00520   */
00521 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
00522 {
00523   uint32_t tmpsmcr;
00524
00525   /* Check the parameters */
00526   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00527
00528   /* Enable the Capture compare channel N */
00529   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00530
00531   /* Enable the Main Output */
00532   __HAL_TIM_MOE_ENABLE(htim);
00533
00534   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00535   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00536   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00537   {
00538     __HAL_TIM_ENABLE(htim);
00539   }
00540
00541   /* Return function status */
00542   return HAL_OK;
00543 }
00544
00545 /**
00546   * @brief  Stops the TIM Output Compare signal generation on the complementary
00547   *         output.
00548   * @param  htim TIM handle
00549   * @param  Channel TIM Channel to be disabled
00550   *          This parameter can be one of the following values:
00551   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00552   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00553   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00554   * @retval HAL status
00555   */
00556 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
00557 {
00558   /* Check the parameters */
00559   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00560
00561   /* Disable the Capture compare channel N */
00562   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00563
00564   /* Disable the Main Output */
00565   __HAL_TIM_MOE_DISABLE(htim);
00566
00567   /* Disable the Peripheral */
00568   __HAL_TIM_DISABLE(htim);
00569
00570   /* Return function status */
00571   return HAL_OK;
00572 }
00573
00574 /**
00575   * @brief  Starts the TIM Output Compare signal generation in interrupt mode
00576   *         on the complementary output.
00577   * @param  htim TIM OC handle
00578   * @param  Channel TIM Channel to be enabled
00579   *          This parameter can be one of the following values:
00580   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00581   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00582   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00583   * @retval HAL status
00584   */
00585 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00586 {
00587   uint32_t tmpsmcr;
00588
00589   /* Check the parameters */
00590   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00591
00592   switch (Channel)
00593   {
00594     case TIM_CHANNEL_1:
00595     {
00596       /* Enable the TIM Output Compare interrupt */
00597       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00598       break;
00599     }
00600
00601     case TIM_CHANNEL_2:
00602     {
00603       /* Enable the TIM Output Compare interrupt */
00604       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
00605       break;
00606     }
00607
00608     case TIM_CHANNEL_3:
00609     {
00610       /* Enable the TIM Output Compare interrupt */
00611       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
00612       break;
00613     }
00614
00615
00616     default:
00617       break;
00618   }
00619
00620   /* Enable the TIM Break interrupt */
00621   __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
00622
00623   /* Enable the Capture compare channel N */
00624   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00625
00626   /* Enable the Main Output */
00627   __HAL_TIM_MOE_ENABLE(htim);
00628
00629   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00630   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00631   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00632   {
00633     __HAL_TIM_ENABLE(htim);
00634   }
00635
00636   /* Return function status */
00637   return HAL_OK;
00638 }
00639
00640 /**
00641   * @brief  Stops the TIM Output Compare signal generation in interrupt mode
00642   *         on the complementary output.
00643   * @param  htim TIM Output Compare handle
00644   * @param  Channel TIM Channel to be disabled
00645   *          This parameter can be one of the following values:
00646   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00647   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00648   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00649   * @retval HAL status
00650   */
00651 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00652 {
00653   uint32_t tmpccer;
00654   /* Check the parameters */
00655   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00656
00657   switch (Channel)
00658   {
00659     case TIM_CHANNEL_1:
00660     {
00661       /* Disable the TIM Output Compare interrupt */
00662       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
00663       break;
00664     }
00665
00666     case TIM_CHANNEL_2:
00667     {
00668       /* Disable the TIM Output Compare interrupt */
00669       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
00670       break;
00671     }
00672
00673     case TIM_CHANNEL_3:
00674     {
00675       /* Disable the TIM Output Compare interrupt */
00676       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
00677       break;
00678     }
00679
00680     default:
00681       break;
00682   }
00683
00684   /* Disable the Capture compare channel N */
00685   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00686
00687   /* Disable the TIM Break interrupt (only if no more channel is active) */
00688   tmpccer = htim->Instance->CCER;
00689   if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
00690   {
00691     __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
00692   }
00693
00694   /* Disable the Main Output */
00695   __HAL_TIM_MOE_DISABLE(htim);
00696
00697   /* Disable the Peripheral */
00698   __HAL_TIM_DISABLE(htim);
00699
00700   /* Return function status */
00701   return HAL_OK;
00702 }
00703
00704 /**
00705   * @brief  Starts the TIM Output Compare signal generation in DMA mode
00706   *         on the complementary output.
00707   * @param  htim TIM Output Compare handle
00708   * @param  Channel TIM Channel to be enabled
00709   *          This parameter can be one of the following values:
00710   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00711   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00712   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00713   * @param  pData The source Buffer address.
00714   * @param  Length The length of data to be transferred from memory to TIM peripheral
00715   * @retval HAL status
00716   */
00717 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
00718 {
00719   uint32_t tmpsmcr;
00720
00721   /* Check the parameters */
00722   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00723
00724   if (htim->State == HAL_TIM_STATE_BUSY)
00725   {
00726     return HAL_BUSY;
00727   }
00728   else if (htim->State == HAL_TIM_STATE_READY)
00729   {
00730     if (((uint32_t)pData == 0U) && (Length > 0U))
00731     {
00732       return HAL_ERROR;
00733     }
00734     else
00735     {
00736       htim->State = HAL_TIM_STATE_BUSY;
00737     }
00738   }
00739   else
00740   {
00741     /* nothing to do  */
00742   }
00743
00744   switch (Channel)
00745   {
00746     case TIM_CHANNEL_1:
00747     {
00748       /* Set the DMA compare callbacks */
00749       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
00750       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
00751
00752       /* Set the DMA error callback */
00753       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
00754
00755       /* Enable the DMA channel */
00756       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
00757       {
00758         return HAL_ERROR;
00759       }
00760       /* Enable the TIM Output Compare DMA request */
00761       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
00762       break;
00763     }
00764
00765     case TIM_CHANNEL_2:
00766     {
00767       /* Set the DMA compare callbacks */
00768       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
00769       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
00770
00771       /* Set the DMA error callback */
00772       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
00773
00774       /* Enable the DMA channel */
00775       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
00776       {
00777         return HAL_ERROR;
00778       }
00779       /* Enable the TIM Output Compare DMA request */
00780       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
00781       break;
00782     }
00783
00784     case TIM_CHANNEL_3:
00785     {
00786       /* Set the DMA compare callbacks */
00787       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
00788       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
00789
00790       /* Set the DMA error callback */
00791       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
00792
00793       /* Enable the DMA channel */
00794       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
00795       {
00796         return HAL_ERROR;
00797       }
00798       /* Enable the TIM Output Compare DMA request */
00799       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
00800       break;
00801     }
00802
00803     default:
00804       break;
00805   }
00806
00807   /* Enable the Capture compare channel N */
00808   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00809
00810   /* Enable the Main Output */
00811   __HAL_TIM_MOE_ENABLE(htim);
00812
00813   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00814   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00815   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00816   {
00817     __HAL_TIM_ENABLE(htim);
00818   }
00819
00820   /* Return function status */
00821   return HAL_OK;
00822 }
00823
00824 /**
00825   * @brief  Stops the TIM Output Compare signal generation in DMA mode
00826   *         on the complementary output.
00827   * @param  htim TIM Output Compare handle
00828   * @param  Channel TIM Channel to be disabled
00829   *          This parameter can be one of the following values:
00830   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00831   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00832   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00833   * @retval HAL status
00834   */
00835 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
00836 {
00837   /* Check the parameters */
00838   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00839
00840   switch (Channel)
00841   {
00842     case TIM_CHANNEL_1:
00843     {
00844       /* Disable the TIM Output Compare DMA request */
00845       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
00846       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
00847       break;
00848     }
00849
00850     case TIM_CHANNEL_2:
00851     {
00852       /* Disable the TIM Output Compare DMA request */
00853       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
00854       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
00855       break;
00856     }
00857
00858     case TIM_CHANNEL_3:
00859     {
00860       /* Disable the TIM Output Compare DMA request */
00861       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
00862       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
00863       break;
00864     }
00865
00866     default:
00867       break;
00868   }
00869
00870   /* Disable the Capture compare channel N */
00871   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00872
00873   /* Disable the Main Output */
00874   __HAL_TIM_MOE_DISABLE(htim);
00875
00876   /* Disable the Peripheral */
00877   __HAL_TIM_DISABLE(htim);
00878
00879   /* Change the htim state */
00880   htim->State = HAL_TIM_STATE_READY;
00881
00882   /* Return function status */
00883   return HAL_OK;
00884 }
00885
00886 /**
00887   * @}
00888   */
00889
00890 /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
00891   * @brief    Timer Complementary PWM functions
00892   *
00893 @verbatim
00894   ==============================================================================
00895                  ##### Timer Complementary PWM functions #####
00896   ==============================================================================
00897   [..]
00898     This section provides functions allowing to:
00899     (+) Start the Complementary PWM.
00900     (+) Stop the Complementary PWM.
00901     (+) Start the Complementary PWM and enable interrupts.
00902     (+) Stop the Complementary PWM and disable interrupts.
00903     (+) Start the Complementary PWM and enable DMA transfers.
00904     (+) Stop the Complementary PWM and disable DMA transfers.
00905     (+) Start the Complementary Input Capture measurement.
00906     (+) Stop the Complementary Input Capture.
00907     (+) Start the Complementary Input Capture and enable interrupts.
00908     (+) Stop the Complementary Input Capture and disable interrupts.
00909     (+) Start the Complementary Input Capture and enable DMA transfers.
00910     (+) Stop the Complementary Input Capture and disable DMA transfers.
00911     (+) Start the Complementary One Pulse generation.
00912     (+) Stop the Complementary One Pulse.
00913     (+) Start the Complementary One Pulse and enable interrupts.
00914     (+) Stop the Complementary One Pulse and disable interrupts.
00915
00916 @endverbatim
00917   * @{
00918   */
00919
00920 /**
00921   * @brief  Starts the PWM signal generation on the complementary output.
00922   * @param  htim TIM handle
00923   * @param  Channel TIM Channel to be enabled
00924   *          This parameter can be one of the following values:
00925   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00926   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00927   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00928   * @retval HAL status
00929   */
00930 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
00931 {
00932   uint32_t tmpsmcr;
00933
00934   /* Check the parameters */
00935   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00936
00937   /* Enable the complementary PWM output  */
00938   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00939
00940   /* Enable the Main Output */
00941   __HAL_TIM_MOE_ENABLE(htim);
00942
00943   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
00944   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
00945   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
00946   {
00947     __HAL_TIM_ENABLE(htim);
00948   }
00949
00950   /* Return function status */
00951   return HAL_OK;
00952 }
00953
00954 /**
00955   * @brief  Stops the PWM signal generation on the complementary output.
00956   * @param  htim TIM handle
00957   * @param  Channel TIM Channel to be disabled
00958   *          This parameter can be one of the following values:
00959   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00960   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00961   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00962   * @retval HAL status
00963   */
00964 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
00965 {
00966   /* Check the parameters */
00967   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00968
00969   /* Disable the complementary PWM output  */
00970   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00971
00972   /* Disable the Main Output */
00973   __HAL_TIM_MOE_DISABLE(htim);
00974
00975   /* Disable the Peripheral */
00976   __HAL_TIM_DISABLE(htim);
00977
00978   /* Return function status */
00979   return HAL_OK;
00980 }
00981
00982 /**
00983   * @brief  Starts the PWM signal generation in interrupt mode on the
00984   *         complementary output.
00985   * @param  htim TIM handle
00986   * @param  Channel TIM Channel to be disabled
00987   *          This parameter can be one of the following values:
00988   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00989   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00990   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00991   * @retval HAL status
00992   */
00993 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00994 {
00995   uint32_t tmpsmcr;
00996
00997   /* Check the parameters */
00998   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00999
01000   switch (Channel)
01001   {
01002     case TIM_CHANNEL_1:
01003     {
01004       /* Enable the TIM Capture/Compare 1 interrupt */
01005       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
01006       break;
01007     }
01008
01009     case TIM_CHANNEL_2:
01010     {
01011       /* Enable the TIM Capture/Compare 2 interrupt */
01012       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
01013       break;
01014     }
01015
01016     case TIM_CHANNEL_3:
01017     {
01018       /* Enable the TIM Capture/Compare 3 interrupt */
01019       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
01020       break;
01021     }
01022
01023     default:
01024       break;
01025   }
01026
01027   /* Enable the TIM Break interrupt */
01028   __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
01029
01030   /* Enable the complementary PWM output  */
01031   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
01032
01033   /* Enable the Main Output */
01034   __HAL_TIM_MOE_ENABLE(htim);
01035
01036   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
01037   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
01038   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
01039   {
01040     __HAL_TIM_ENABLE(htim);
01041   }
01042
01043   /* Return function status */
01044   return HAL_OK;
01045 }
01046
01047 /**
01048   * @brief  Stops the PWM signal generation in interrupt mode on the
01049   *         complementary output.
01050   * @param  htim TIM handle
01051   * @param  Channel TIM Channel to be disabled
01052   *          This parameter can be one of the following values:
01053   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01054   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01055   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01056   * @retval HAL status
01057   */
01058 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
01059 {
01060   uint32_t tmpccer;
01061
01062   /* Check the parameters */
01063   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01064
01065   switch (Channel)
01066   {
01067     case TIM_CHANNEL_1:
01068     {
01069       /* Disable the TIM Capture/Compare 1 interrupt */
01070       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01071       break;
01072     }
01073
01074     case TIM_CHANNEL_2:
01075     {
01076       /* Disable the TIM Capture/Compare 2 interrupt */
01077       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01078       break;
01079     }
01080
01081     case TIM_CHANNEL_3:
01082     {
01083       /* Disable the TIM Capture/Compare 3 interrupt */
01084       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
01085       break;
01086     }
01087
01088     default:
01089       break;
01090   }
01091
01092   /* Disable the complementary PWM output  */
01093   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
01094
01095   /* Disable the TIM Break interrupt (only if no more channel is active) */
01096   tmpccer = htim->Instance->CCER;
01097   if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
01098   {
01099     __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
01100   }
01101
01102   /* Disable the Main Output */
01103   __HAL_TIM_MOE_DISABLE(htim);
01104
01105   /* Disable the Peripheral */
01106   __HAL_TIM_DISABLE(htim);
01107
01108   /* Return function status */
01109   return HAL_OK;
01110 }
01111
01112 /**
01113   * @brief  Starts the TIM PWM signal generation in DMA mode on the
01114   *         complementary output
01115   * @param  htim TIM handle
01116   * @param  Channel TIM Channel to be enabled
01117   *          This parameter can be one of the following values:
01118   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01119   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01120   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01121   * @param  pData The source Buffer address.
01122   * @param  Length The length of data to be transferred from memory to TIM peripheral
01123   * @retval HAL status
01124   */
01125 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
01126 {
01127   uint32_t tmpsmcr;
01128
01129   /* Check the parameters */
01130   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01131
01132   if (htim->State == HAL_TIM_STATE_BUSY)
01133   {
01134     return HAL_BUSY;
01135   }
01136   else if (htim->State == HAL_TIM_STATE_READY)
01137   {
01138     if (((uint32_t)pData == 0U) && (Length > 0U))
01139     {
01140       return HAL_ERROR;
01141     }
01142     else
01143     {
01144       htim->State = HAL_TIM_STATE_BUSY;
01145     }
01146   }
01147   else
01148   {
01149     /* nothing to do */
01150   }
01151   switch (Channel)
01152   {
01153     case TIM_CHANNEL_1:
01154     {
01155       /* Set the DMA compare callbacks */
01156       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
01157       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01158
01159       /* Set the DMA error callback */
01160       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
01161
01162       /* Enable the DMA channel */
01163       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
01164       {
01165         return HAL_ERROR;
01166       }
01167       /* Enable the TIM Capture/Compare 1 DMA request */
01168       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
01169       break;
01170     }
01171
01172     case TIM_CHANNEL_2:
01173     {
01174       /* Set the DMA compare callbacks */
01175       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
01176       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01177
01178       /* Set the DMA error callback */
01179       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
01180
01181       /* Enable the DMA channel */
01182       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
01183       {
01184         return HAL_ERROR;
01185       }
01186       /* Enable the TIM Capture/Compare 2 DMA request */
01187       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
01188       break;
01189     }
01190
01191     case TIM_CHANNEL_3:
01192     {
01193       /* Set the DMA compare callbacks */
01194       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
01195       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
01196
01197       /* Set the DMA error callback */
01198       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
01199
01200       /* Enable the DMA channel */
01201       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
01202       {
01203         return HAL_ERROR;
01204       }
01205       /* Enable the TIM Capture/Compare 3 DMA request */
01206       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
01207       break;
01208     }
01209
01210     default:
01211       break;
01212   }
01213
01214   /* Enable the complementary PWM output  */
01215   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
01216
01217   /* Enable the Main Output */
01218   __HAL_TIM_MOE_ENABLE(htim);
01219
01220   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
01221   tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
01222   if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
01223   {
01224     __HAL_TIM_ENABLE(htim);
01225   }
01226
01227   /* Return function status */
01228   return HAL_OK;
01229 }
01230
01231 /**
01232   * @brief  Stops the TIM PWM signal generation in DMA mode on the complementary
01233   *         output
01234   * @param  htim TIM handle
01235   * @param  Channel TIM Channel to be disabled
01236   *          This parameter can be one of the following values:
01237   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01238   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01239   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01240   * @retval HAL status
01241   */
01242 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
01243 {
01244   /* Check the parameters */
01245   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01246
01247   switch (Channel)
01248   {
01249     case TIM_CHANNEL_1:
01250     {
01251       /* Disable the TIM Capture/Compare 1 DMA request */
01252       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
01253       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
01254       break;
01255     }
01256
01257     case TIM_CHANNEL_2:
01258     {
01259       /* Disable the TIM Capture/Compare 2 DMA request */
01260       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
01261       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
01262       break;
01263     }
01264
01265     case TIM_CHANNEL_3:
01266     {
01267       /* Disable the TIM Capture/Compare 3 DMA request */
01268       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
01269       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
01270       break;
01271     }
01272
01273     default:
01274       break;
01275   }
01276
01277   /* Disable the complementary PWM output */
01278   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
01279
01280   /* Disable the Main Output */
01281   __HAL_TIM_MOE_DISABLE(htim);
01282
01283   /* Disable the Peripheral */
01284   __HAL_TIM_DISABLE(htim);
01285
01286   /* Change the htim state */
01287   htim->State = HAL_TIM_STATE_READY;
01288
01289   /* Return function status */
01290   return HAL_OK;
01291 }
01292
01293 /**
01294   * @}
01295   */
01296
01297 /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
01298   * @brief    Timer Complementary One Pulse functions
01299   *
01300 @verbatim
01301   ==============================================================================
01302                 ##### Timer Complementary One Pulse functions #####
01303   ==============================================================================
01304   [..]
01305     This section provides functions allowing to:
01306     (+) Start the Complementary One Pulse generation.
01307     (+) Stop the Complementary One Pulse.
01308     (+) Start the Complementary One Pulse and enable interrupts.
01309     (+) Stop the Complementary One Pulse and disable interrupts.
01310
01311 @endverbatim
01312   * @{
01313   */
01314
01315 /**
01316   * @brief  Starts the TIM One Pulse signal generation on the complementary
01317   *         output.
01318   * @param  htim TIM One Pulse handle
01319   * @param  OutputChannel TIM Channel to be enabled
01320   *          This parameter can be one of the following values:
01321   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01322   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01323   * @retval HAL status
01324   */
01325 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01326 {
01327   /* Check the parameters */
01328   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01329
01330   /* Enable the complementary One Pulse output */
01331   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
01332
01333   /* Enable the Main Output */
01334   __HAL_TIM_MOE_ENABLE(htim);
01335
01336   /* Return function status */
01337   return HAL_OK;
01338 }
01339
01340 /**
01341   * @brief  Stops the TIM One Pulse signal generation on the complementary
01342   *         output.
01343   * @param  htim TIM One Pulse handle
01344   * @param  OutputChannel TIM Channel to be disabled
01345   *          This parameter can be one of the following values:
01346   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01347   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01348   * @retval HAL status
01349   */
01350 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01351 {
01352
01353   /* Check the parameters */
01354   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01355
01356   /* Disable the complementary One Pulse output */
01357   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
01358
01359   /* Disable the Main Output */
01360   __HAL_TIM_MOE_DISABLE(htim);
01361
01362   /* Disable the Peripheral */
01363   __HAL_TIM_DISABLE(htim);
01364
01365   /* Return function status */
01366   return HAL_OK;
01367 }
01368
01369 /**
01370   * @brief  Starts the TIM One Pulse signal generation in interrupt mode on the
01371   *         complementary channel.
01372   * @param  htim TIM One Pulse handle
01373   * @param  OutputChannel TIM Channel to be enabled
01374   *          This parameter can be one of the following values:
01375   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01376   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01377   * @retval HAL status
01378   */
01379 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01380 {
01381   /* Check the parameters */
01382   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01383
01384   /* Enable the TIM Capture/Compare 1 interrupt */
01385   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
01386
01387   /* Enable the TIM Capture/Compare 2 interrupt */
01388   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
01389
01390   /* Enable the complementary One Pulse output */
01391   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
01392
01393   /* Enable the Main Output */
01394   __HAL_TIM_MOE_ENABLE(htim);
01395
01396   /* Return function status */
01397   return HAL_OK;
01398 }
01399
01400 /**
01401   * @brief  Stops the TIM One Pulse signal generation in interrupt mode on the
01402   *         complementary channel.
01403   * @param  htim TIM One Pulse handle
01404   * @param  OutputChannel TIM Channel to be disabled
01405   *          This parameter can be one of the following values:
01406   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01407   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01408   * @retval HAL status
01409   */
01410 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01411 {
01412   /* Check the parameters */
01413   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01414
01415   /* Disable the TIM Capture/Compare 1 interrupt */
01416   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01417
01418   /* Disable the TIM Capture/Compare 2 interrupt */
01419   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01420
01421   /* Disable the complementary One Pulse output */
01422   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
01423
01424   /* Disable the Main Output */
01425   __HAL_TIM_MOE_DISABLE(htim);
01426
01427   /* Disable the Peripheral */
01428   __HAL_TIM_DISABLE(htim);
01429
01430   /* Return function status */
01431   return HAL_OK;
01432 }
01433
01434 /**
01435   * @}
01436   */
01437
01438 /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
01439   * @brief    Peripheral Control functions
01440   *
01441 @verbatim
01442   ==============================================================================
01443                     ##### Peripheral Control functions #####
01444   ==============================================================================
01445   [..]
01446     This section provides functions allowing to:
01447       (+) Configure the commutation event in case of use of the Hall sensor interface.
01448       (+) Configure Output channels for OC and PWM mode.
01449
01450       (+) Configure Complementary channels, break features and dead time.
01451       (+) Configure Master synchronization.
01452       (+) Configure timer remapping capabilities.
01453       (+) Enable or disable channel grouping.
01454
01455 @endverbatim
01456   * @{
01457   */
01458
01459 /**
01460   * @brief  Configure the TIM commutation event sequence.
01461   * @note  This function is mandatory to use the commutation event in order to
01462   *        update the configuration at each commutation detection on the TRGI input of the Timer,
01463   *        the typical use of this feature is with the use of another Timer(interface Timer)
01464   *        configured in Hall sensor interface, this interface Timer will generate the
01465   *        commutation at its TRGO output (connected to Timer used in this function) each time
01466   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
01467   * @param  htim TIM handle
01468   * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
01469   *          This parameter can be one of the following values:
01470   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
01471   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
01472   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
01473   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
01474   *            @arg TIM_TS_NONE: No trigger is needed
01475   * @param  CommutationSource the Commutation Event source
01476   *          This parameter can be one of the following values:
01477   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
01478   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
01479   * @retval HAL status
01480   */
01481 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
01482                                               uint32_t  CommutationSource)
01483 {
01484   /* Check the parameters */
01485   assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
01486   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
01487
01488   __HAL_LOCK(htim);
01489
01490   if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
01491       (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
01492   {
01493     /* Select the Input trigger */
01494     htim->Instance->SMCR &= ~TIM_SMCR_TS;
01495     htim->Instance->SMCR |= InputTrigger;
01496   }
01497
01498   /* Select the Capture Compare preload feature */
01499   htim->Instance->CR2 |= TIM_CR2_CCPC;
01500   /* Select the Commutation event source */
01501   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
01502   htim->Instance->CR2 |= CommutationSource;
01503
01504   /* Disable Commutation Interrupt */
01505   __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
01506
01507   /* Disable Commutation DMA request */
01508   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
01509
01510   __HAL_UNLOCK(htim);
01511
01512   return HAL_OK;
01513 }
01514
01515 /**
01516   * @brief  Configure the TIM commutation event sequence with interrupt.
01517   * @note  This function is mandatory to use the commutation event in order to
01518   *        update the configuration at each commutation detection on the TRGI input of the Timer,
01519   *        the typical use of this feature is with the use of another Timer(interface Timer)
01520   *        configured in Hall sensor interface, this interface Timer will generate the
01521   *        commutation at its TRGO output (connected to Timer used in this function) each time
01522   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
01523   * @param  htim TIM handle
01524   * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
01525   *          This parameter can be one of the following values:
01526   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
01527   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
01528   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
01529   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
01530   *            @arg TIM_TS_NONE: No trigger is needed
01531   * @param  CommutationSource the Commutation Event source
01532   *          This parameter can be one of the following values:
01533   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
01534   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
01535   * @retval HAL status
01536   */
01537 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
01538                                                  uint32_t  CommutationSource)
01539 {
01540   /* Check the parameters */
01541   assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
01542   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
01543
01544   __HAL_LOCK(htim);
01545
01546   if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
01547       (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
01548   {
01549     /* Select the Input trigger */
01550     htim->Instance->SMCR &= ~TIM_SMCR_TS;
01551     htim->Instance->SMCR |= InputTrigger;
01552   }
01553
01554   /* Select the Capture Compare preload feature */
01555   htim->Instance->CR2 |= TIM_CR2_CCPC;
01556   /* Select the Commutation event source */
01557   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
01558   htim->Instance->CR2 |= CommutationSource;
01559
01560   /* Disable Commutation DMA request */
01561   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
01562
01563   /* Enable the Commutation Interrupt */
01564   __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
01565
01566   __HAL_UNLOCK(htim);
01567
01568   return HAL_OK;
01569 }
01570
01571 /**
01572   * @brief  Configure the TIM commutation event sequence with DMA.
01573   * @note  This function is mandatory to use the commutation event in order to
01574   *        update the configuration at each commutation detection on the TRGI input of the Timer,
01575   *        the typical use of this feature is with the use of another Timer(interface Timer)
01576   *        configured in Hall sensor interface, this interface Timer will generate the
01577   *        commutation at its TRGO output (connected to Timer used in this function) each time
01578   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
01579   * @note  The user should configure the DMA in his own software, in This function only the COMDE bit is set
01580   * @param  htim TIM handle
01581   * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
01582   *          This parameter can be one of the following values:
01583   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
01584   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
01585   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
01586   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
01587   *            @arg TIM_TS_NONE: No trigger is needed
01588   * @param  CommutationSource the Commutation Event source
01589   *          This parameter can be one of the following values:
01590   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
01591   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
01592   * @retval HAL status
01593   */
01594 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
01595                                                   uint32_t  CommutationSource)
01596 {
01597   /* Check the parameters */
01598   assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
01599   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
01600
01601   __HAL_LOCK(htim);
01602
01603   if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
01604       (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
01605   {
01606     /* Select the Input trigger */
01607     htim->Instance->SMCR &= ~TIM_SMCR_TS;
01608     htim->Instance->SMCR |= InputTrigger;
01609   }
01610
01611   /* Select the Capture Compare preload feature */
01612   htim->Instance->CR2 |= TIM_CR2_CCPC;
01613   /* Select the Commutation event source */
01614   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
01615   htim->Instance->CR2 |= CommutationSource;
01616
01617   /* Enable the Commutation DMA Request */
01618   /* Set the DMA Commutation Callback */
01619   htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
01620   htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
01621   /* Set the DMA error callback */
01622   htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
01623
01624   /* Disable Commutation Interrupt */
01625   __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
01626
01627   /* Enable the Commutation DMA Request */
01628   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
01629
01630   __HAL_UNLOCK(htim);
01631
01632   return HAL_OK;
01633 }
01634
01635 /**
01636   * @brief  Configures the TIM in master mode.
01637   * @param  htim TIM handle.
01638   * @param  sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
01639   *         contains the selected trigger output (TRGO) and the Master/Slave
01640   *         mode.
01641   * @retval HAL status
01642   */
01643 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
01644                                                         TIM_MasterConfigTypeDef *sMasterConfig)
01645 {
01646   uint32_t tmpcr2;
01647   uint32_t tmpsmcr;
01648
01649   /* Check the parameters */
01650   assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
01651   assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
01652   assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
01653
01654   /* Check input state */
01655   __HAL_LOCK(htim);
01656
01657   /* Change the handler state */
01658   htim->State = HAL_TIM_STATE_BUSY;
01659
01660   /* Get the TIMx CR2 register value */
01661   tmpcr2 = htim->Instance->CR2;
01662
01663   /* Get the TIMx SMCR register value */
01664   tmpsmcr = htim->Instance->SMCR;
01665
01666   /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
01667   if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
01668   {
01669     /* Check the parameters */
01670     assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
01671
01672     /* Clear the MMS2 bits */
01673     tmpcr2 &= ~TIM_CR2_MMS2;
01674     /* Select the TRGO2 source*/
01675     tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
01676   }
01677
01678   /* Reset the MMS Bits */
01679   tmpcr2 &= ~TIM_CR2_MMS;
01680   /* Select the TRGO source */
01681   tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
01682
01683   /* Update TIMx CR2 */
01684   htim->Instance->CR2 = tmpcr2;
01685
01686   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
01687   {
01688     /* Reset the MSM Bit */
01689     tmpsmcr &= ~TIM_SMCR_MSM;
01690     /* Set master mode */
01691     tmpsmcr |= sMasterConfig->MasterSlaveMode;
01692
01693     /* Update TIMx SMCR */
01694     htim->Instance->SMCR = tmpsmcr;
01695   }
01696
01697   /* Change the htim state */
01698   htim->State = HAL_TIM_STATE_READY;
01699
01700   __HAL_UNLOCK(htim);
01701
01702   return HAL_OK;
01703 }
01704
01705 /**
01706   * @brief  Configures the Break feature, dead time, Lock level, OSSI/OSSR State
01707   *         and the AOE(automatic output enable).
01708   * @param  htim TIM handle
01709   * @param  sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
01710   *         contains the BDTR Register configuration  information for the TIM peripheral.
01711   * @note   Interrupts can be generated when an active level is detected on the
01712   *         break input, the break 2 input or the system break input. Break
01713   *         interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
01714   * @retval HAL status
01715   */
01716 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
01717                                                 TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
01718 {
01719   /* Keep this variable initialized to 0 as it is used to configure BDTR register */
01720   uint32_t tmpbdtr = 0U;
01721
01722   /* Check the parameters */
01723   assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
01724   assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
01725   assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
01726   assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
01727   assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
01728   assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
01729   assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
01730   assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
01731   assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
01732
01733   /* Check input state */
01734   __HAL_LOCK(htim);
01735
01736   /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
01737      the OSSI State, the dead time value and the Automatic Output Enable Bit */
01738
01739   /* Set the BDTR bits */
01740   MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
01741   MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
01742   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
01743   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
01744   MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
01745   MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
01746   MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
01747   MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
01748
01749   if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
01750   {
01751     /* Check the parameters */
01752     assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
01753     assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
01754     assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
01755
01756     /* Set the BREAK2 input related BDTR bits */
01757     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
01758     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
01759     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
01760   }
01761
01762   /* Set TIMx_BDTR */
01763   htim->Instance->BDTR = tmpbdtr;
01764
01765   __HAL_UNLOCK(htim);
01766
01767   return HAL_OK;
01768 }
01769
01770 /**
01771   * @brief  Configures the break input source.
01772   * @param  htim TIM handle.
01773   * @param  BreakInput Break input to configure
01774   *          This parameter can be one of the following values:
01775   *            @arg TIM_BREAKINPUT_BRK: Timer break input
01776   *            @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
01777   * @param  sBreakInputConfig Break input source configuration
01778   * @retval HAL status
01779   */
01780 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
01781                                              uint32_t BreakInput,
01782                                              TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
01783
01784 {
01785   uint32_t tmporx;
01786   uint32_t bkin_enable_mask;
01787   uint32_t bkin_polarity_mask;
01788   uint32_t bkin_enable_bitpos;
01789   uint32_t bkin_polarity_bitpos;
01790
01791   /* Check the parameters */
01792   assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
01793   assert_param(IS_TIM_BREAKINPUT(BreakInput));
01794   assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
01795   assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
01796   assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
01797
01798   /* Check input state */
01799   __HAL_LOCK(htim);
01800
01801   switch (sBreakInputConfig->Source)
01802   {
01803     case TIM_BREAKINPUTSOURCE_BKIN:
01804     {
01805       bkin_enable_mask = TIM1_AF1_BKINE;
01806       bkin_enable_bitpos = TIM1_AF1_BKINE_Pos;
01807       bkin_polarity_mask = TIM1_AF1_BKINP;
01808       bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos;
01809       break;
01810     }
01811 #if defined(COMP1) && defined(COMP2)
01812     case TIM_BREAKINPUTSOURCE_COMP1:
01813     {
01814       bkin_enable_mask = TIM1_AF1_BKCMP1E;
01815       bkin_enable_bitpos = TIM1_AF1_BKCMP1E_Pos;
01816       bkin_polarity_mask = TIM1_AF1_BKCMP1P;
01817       bkin_polarity_bitpos = TIM1_AF1_BKCMP1P_Pos;
01818       break;
01819     }
01820     case TIM_BREAKINPUTSOURCE_COMP2:
01821     {
01822       bkin_enable_mask = TIM1_AF1_BKCMP2E;
01823       bkin_enable_bitpos = TIM1_AF1_BKCMP2E_Pos;
01824       bkin_polarity_mask = TIM1_AF1_BKCMP2P;
01825       bkin_polarity_bitpos = TIM1_AF1_BKCMP2P_Pos;
01826       break;
01827     }
01828 #endif /* COMP1 && COMP2 */
01829
01830     default:
01831     {
01832       bkin_enable_mask = 0U;
01833       bkin_polarity_mask = 0U;
01834       bkin_enable_bitpos = 0U;
01835       bkin_polarity_bitpos = 0U;
01836       break;
01837     }
01838   }
01839
01840   switch (BreakInput)
01841   {
01842     case TIM_BREAKINPUT_BRK:
01843     {
01844       /* Get the TIMx_AF1 register value */
01845       tmporx = htim->Instance->AF1;
01846
01847       /* Enable the break input */
01848       tmporx &= ~bkin_enable_mask;
01849       tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
01850
01851       /* Set the break input polarity */
01852       tmporx &= ~bkin_polarity_mask;
01853       tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
01854
01855       /* Set TIMx_AF1 */
01856       htim->Instance->AF1 = tmporx;
01857       break;
01858     }
01859     case TIM_BREAKINPUT_BRK2:
01860     {
01861       /* Get the TIMx_AF2 register value */
01862       tmporx = htim->Instance->AF2;
01863
01864       /* Enable the break input */
01865       tmporx &= ~bkin_enable_mask;
01866       tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
01867
01868       /* Set the break input polarity */
01869       tmporx &= ~bkin_polarity_mask;
01870       tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
01871
01872       /* Set TIMx_AF2 */
01873       htim->Instance->AF2 = tmporx;
01874       break;
01875     }
01876     default:
01877       break;
01878   }
01879
01880   __HAL_UNLOCK(htim);
01881
01882   return HAL_OK;
01883 }
01884
01885 /**
01886   * @brief  Configures the TIMx Remapping input capabilities.
01887   * @param  htim TIM handle.
01888   * @param  Remap specifies the TIM remapping source.
01889   *     For TIM1, the parameter is a combination of 2 fields (field1 | field2):
01890   *
01891   *       field1 can have the following values:
01892   *            @arg TIM_TIM1_ETR_ADC1_GPIO:           TIM1_ETR is connected to I/O
01893   *            @arg TIM_TIM1_ETR_ADC1_AWD1:           TIM1_ETR is connected to ADC1 AWD1
01894   *            @arg TIM_TIM1_ETR_ADC1_AWD2:           TIM1_ETR is connected to ADC1 AWD2
01895   *            @arg TIM_TIM1_ETR_ADC1_AWD3:           TIM1_ETR is connected to ADC1 AWD3
01896   *            @arg TIM_TIM1_ETR_COMP1:               TIM1_ETR is connected to COMP1 output (*)
01897   *            @arg TIM_TIM1_ETR_COMP2:               TIM1_ETR is connected to COMP2 output (*)
01898   *       field2 can have the following values:
01899   *            @arg TIM_TIM1_TI1_GPIO:                TIM1 TI1 is connected to I/O
01900   *            @arg TIM_TIM1_TI1_COMP1:               TIM1 TI1 is connected to COMP1 output (*)
01901   *
01902   *        For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3):
01903   *
01904   *       field1 can have the following values:
01905   *            @arg TIM_TIM2_ITR1_NONE:               No internal trigger on TIM2_ITR1
01906   *            @arg TIM_TIM2_ITR1_USB:                TIM2_ITR1 is connected to USB SOF (*)
01907   *
01908   *       field2 can have the following values:
01909   *            @arg TIM_TIM2_ETR_GPIO:                TIM2_ETR is connected to I/O
01910   *            @arg TIM_TIM2_ETR_LSE:                 TIM2_ETR is connected to LSE
01911   *            @arg TIM_TIM2_ETR_COMP1:               TIM2_ETR is connected to COMP1 output (*)
01912   *            @arg TIM_TIM2_ETR_COMP2:               TIM2_ETR is connected to COMP2 output (*)
01913   *
01914   *       field3 can have the following values:
01915   *            @arg TIM_TIM2_TI4_GPIO:                TIM2 TI4 is connected to I/O
01916   *            @arg TIM_TIM2_TI4_COMP1:               TIM2 TI4 is connected to COMP1 output (*)
01917   *            @arg TIM_TIM2_TI4_COMP2:               TIM2 TI4 is connected to COMP2 output (*)
01918   *            @arg TIM_TIM2_TI4_COMP1_COMP2:         TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output (*)
01919   *
01920   *     For TIM16, the parameter can have the following values:
01921   *            @arg TIM_TIM16_TI1_GPIO:              TIM16 TI1 is connected to I/O
01922   *            @arg TIM_TIM16_TI1_LSI:               TIM16 TI1 is connected to LSI
01923   *            @arg TIM_TIM16_TI1_LSE:               TIM16 TI1 is connected to LSE
01924   *            @arg TIM_TIM16_TI1_RTC:               TIM16 TI1 is connected to RTC wakeup interrupt
01925   *
01926   *     For TIM17, the parameter can have the following values:
01927   *            @arg TIM_TIM17_TI1_GPIO:              TIM17 TI1 is connected to I/O
01928   *            @arg TIM_TIM17_TI1_MSI:               TIM17 TI1 is connected to MSI  (constraint: MSI clock < 1/4 TIM APB clock)
01929   *            @arg TIM_TIM17_TI1_HSE:               TIM17 TI1 is connected to HSE div 32
01930   *            @arg TIM_TIM17_TI1_MCO:               TIM17 TI1 is connected to MCO
01931   *
01932   *         (*)  Value not defined in all devices.
01933   *
01934   * @retval HAL status
01935   */
01936 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
01937 {
01938   uint32_t tmpor;
01939   uint32_t tmpaf1;
01940
01941   /* Check parameters */
01942   assert_param(IS_TIM_REMAP(htim->Instance, Remap));
01943
01944   __HAL_LOCK(htim);
01945
01946   /* Read TIMx_OR */
01947   tmpor = READ_REG(htim->Instance->OR);
01948
01949   /* Read TIMx_AF1 */
01950   tmpaf1 = READ_REG(htim->Instance->AF1);
01951
01952   /* Set ETR_SEL bit field (if required) */
01953   if (IS_TIM_ETRSEL_INSTANCE(htim->Instance))
01954   {
01955     if ((Remap & TIM1_AF1_ETRSEL) != (uint32_t)RESET)
01956     {
01957       /* COMP1 output or COMP2 output connected to ETR input */
01958       MODIFY_REG(tmpaf1, TIM1_AF1_ETRSEL, (Remap & TIM1_AF1_ETRSEL));
01959     }
01960     else
01961     {
01962       /* ETR legacy mode */
01963       MODIFY_REG(tmpaf1, TIM1_AF1_ETRSEL, 0U);
01964     }
01965
01966     /* Set TIMx_AF1 */
01967     WRITE_REG(htim->Instance->AF1, tmpaf1);
01968   }
01969
01970   /* Set other remapping capabilities */
01971   MODIFY_REG(tmpor, TIM_GET_OR_MASK(htim->Instance), (Remap & (~TIM1_AF1_ETRSEL)));
01972
01973   /* Set TIMx_OR */
01974   WRITE_REG(htim->Instance->OR, tmpor);
01975
01976   __HAL_UNLOCK(htim);
01977
01978   return HAL_OK;
01979 }
01980
01981 /**
01982   * @brief  Group channel 5 and channel 1, 2 or 3
01983   * @param  htim TIM handle.
01984   * @param  Channels specifies the reference signal(s) the OC5REF is combined with.
01985   *         This parameter can be any combination of the following values:
01986   *         TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
01987   *         TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
01988   *         TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
01989   *         TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
01990   * @retval HAL status
01991   */
01992 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
01993 {
01994   /* Check parameters */
01995   assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
01996   assert_param(IS_TIM_GROUPCH5(Channels));
01997
01998   /* Process Locked */
01999   __HAL_LOCK(htim);
02000
02001   htim->State = HAL_TIM_STATE_BUSY;
02002
02003   /* Clear GC5Cx bit fields */
02004   htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1);
02005
02006   /* Set GC5Cx bit fields */
02007   htim->Instance->CCR5 |= Channels;
02008
02009   /* Change the htim state */
02010   htim->State = HAL_TIM_STATE_READY;
02011
02012   __HAL_UNLOCK(htim);
02013
02014   return HAL_OK;
02015 }
02016
02017 /**
02018   * @}
02019   */
02020
02021 /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
02022   * @brief    Extended Callbacks functions
02023   *
02024 @verbatim
02025   ==============================================================================
02026                     ##### Extended Callbacks functions #####
02027   ==============================================================================
02028   [..]
02029     This section provides Extended TIM callback functions:
02030     (+) Timer Commutation callback
02031     (+) Timer Break callback
02032
02033 @endverbatim
02034   * @{
02035   */
02036
02037 /**
02038   * @brief  Hall commutation changed callback in non-blocking mode
02039   * @param  htim TIM handle
02040   * @retval None
02041   */
02042 __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
02043 {
02044   /* Prevent unused argument(s) compilation warning */
02045   UNUSED(htim);
02046
02047   /* NOTE : This function should not be modified, when the callback is needed,
02048             the HAL_TIMEx_CommutCallback could be implemented in the user file
02049    */
02050 }
02051 /**
02052   * @brief  Hall commutation changed half complete callback in non-blocking mode
02053   * @param  htim TIM handle
02054   * @retval None
02055   */
02056 __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
02057 {
02058   /* Prevent unused argument(s) compilation warning */
02059   UNUSED(htim);
02060
02061   /* NOTE : This function should not be modified, when the callback is needed,
02062             the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file
02063    */
02064 }
02065
02066 /**
02067   * @brief  Hall Break detection callback in non-blocking mode
02068   * @param  htim TIM handle
02069   * @retval None
02070   */
02071 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
02072 {
02073   /* Prevent unused argument(s) compilation warning */
02074   UNUSED(htim);
02075
02076   /* NOTE : This function should not be modified, when the callback is needed,
02077             the HAL_TIMEx_BreakCallback could be implemented in the user file
02078    */
02079 }
02080
02081 /**
02082   * @brief  Hall Break2 detection callback in non blocking mode
02083   * @param  htim: TIM handle
02084   * @retval None
02085   */
02086 __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
02087 {
02088   /* Prevent unused argument(s) compilation warning */
02089   UNUSED(htim);
02090
02091   /* NOTE : This function Should not be modified, when the callback is needed,
02092             the HAL_TIMEx_Break2Callback could be implemented in the user file
02093    */
02094 }
02095 /**
02096   * @}
02097   */
02098
02099 /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
02100   * @brief    Extended Peripheral State functions
02101   *
02102 @verbatim
02103   ==============================================================================
02104                 ##### Extended Peripheral State functions #####
02105   ==============================================================================
02106   [..]
02107     This subsection permits to get in run-time the status of the peripheral
02108     and the data flow.
02109
02110 @endverbatim
02111   * @{
02112   */
02113
02114 /**
02115   * @brief  Return the TIM Hall Sensor interface handle state.
02116   * @param  htim TIM Hall Sensor handle
02117   * @retval HAL state
02118   */
02119 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
02120 {
02121   return htim->State;
02122 }
02123
02124 /**
02125   * @}
02126   */
02127
02128 /**
02129   * @}
02130   */
02131
02132 /* Private functions ---------------------------------------------------------*/
02133 /** @defgroup TIMEx_Private_Functions TIMEx Private Functions
02134   * @{
02135   */
02136
02137 /**
02138   * @brief  TIM DMA Commutation callback.
02139   * @param  hdma pointer to DMA handle.
02140   * @retval None
02141   */
02142 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
02143 {
02144   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02145
02146   /* Change the htim state */
02147   htim->State = HAL_TIM_STATE_READY;
02148
02149 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
02150   htim->CommutationCallback(htim);
02151 #else
02152   HAL_TIMEx_CommutCallback(htim);
02153 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
02154 }
02155
02156 /**
02157   * @brief  TIM DMA Commutation half complete callback.
02158   * @param  hdma pointer to DMA handle.
02159   * @retval None
02160   */
02161 void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
02162 {
02163   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
02164
02165   /* Change the htim state */
02166   htim->State = HAL_TIM_STATE_READY;
02167
02168 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
02169   htim->CommutationHalfCpltCallback(htim);
02170 #else
02171   HAL_TIMEx_CommutHalfCpltCallback(htim);
02172 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
02173 }
02174
02175
02176 /**
02177   * @brief  Enables or disables the TIM Capture Compare Channel xN.
02178   * @param  TIMx to select the TIM peripheral
02179   * @param  Channel specifies the TIM Channel
02180   *          This parameter can be one of the following values:
02181   *            @arg TIM_CHANNEL_1: TIM Channel 1
02182   *            @arg TIM_CHANNEL_2: TIM Channel 2
02183   *            @arg TIM_CHANNEL_3: TIM Channel 3
02184   * @param  ChannelNState specifies the TIM Channel CCxNE bit new state.
02185   *          This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
02186   * @retval None
02187   */
02188 static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
02189 {
02190   uint32_t tmp;
02191
02192   tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
02193
02194   /* Reset the CCxNE Bit */
02195   TIMx->CCER &=  ~tmp;
02196
02197   /* Set or reset the CCxNE Bit */
02198   TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
02199 }
02200 /**
02201   * @}
02202   */
02203
02204 #endif /* HAL_TIM_MODULE_ENABLED */
02205 /**
02206   * @}
02207   */
02208
02209 /**
02210   * @}
02211   */
02212
02213 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:35 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_tim_ex.h Source File

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stm32wbxx_hal_tim_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_tim_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of TIM HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_TIM_EX_H
00022 #define STM32WBxx_HAL_TIM_EX_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 /** @addtogroup STM32WBxx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup TIMEx
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief  TIM Hall sensor Configuration Structure definition
00046   */
00047
00048 typedef struct
00049 {
00050   uint32_t IC1Polarity;         /*!< Specifies the active edge of the input signal.
00051                                      This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00052
00053   uint32_t IC1Prescaler;        /*!< Specifies the Input Capture Prescaler.
00054                                      This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00055
00056   uint32_t IC1Filter;           /*!< Specifies the input capture filter.
00057                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00058
00059   uint32_t Commutation_Delay;   /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
00060                                      This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00061 } TIM_HallSensor_InitTypeDef;
00062
00063 /**
00064   * @brief  TIM Break/Break2 input configuration
00065   */
00066 typedef struct
00067 {
00068   uint32_t Source;         /*!< Specifies the source of the timer break input.
00069                                 This parameter can be a value of @ref TIMEx_Break_Input_Source */
00070   uint32_t Enable;         /*!< Specifies whether or not the break input source is enabled.
00071                                 This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
00072   uint32_t Polarity;       /*!< Specifies the break input source polarity.
00073                                 This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity */
00074 }
00075 TIMEx_BreakInputConfigTypeDef;
00076
00077 /**
00078   * @}
00079   */
00080 /* End of exported types -----------------------------------------------------*/
00081
00082 /* Exported constants --------------------------------------------------------*/
00083 /** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
00084   * @{
00085   */
00086
00087 /** @defgroup TIMEx_Remap TIM Extended Remapping
00088   * @{
00089   */
00090 #define TIM_TIM1_ETR_GPIO           0x00000000U                                           /* !< TIM1_ETR is not connected to I/O      */
00091 #define TIM_TIM1_ETR_ADC1_AWD1      TIM1_OR_ETR_ADC1_RMP_0                                /* !< TIM1_ETR is connected to ADC1 AWD1    */
00092 #define TIM_TIM1_ETR_ADC1_AWD2      TIM1_OR_ETR_ADC1_RMP_1                                /* !< TIM1_ETR is connected to ADC1 AWD2    */
00093 #define TIM_TIM1_ETR_ADC1_AWD3      (TIM1_OR_ETR_ADC1_RMP_0 | TIM1_OR_ETR_ADC1_RMP_1)     /* !< TIM1_ETR is connected to ADC1 AWD3    */
00094 #if defined(COMP1)
00095 #define TIM_TIM1_ETR_COMP1          TIM1_AF1_ETRSEL_0                                     /* !< TIM1_ETR is connected to COMP1 output */
00096 #endif /* COMP1 */
00097 #if defined(COMP2)
00098 #define TIM_TIM1_ETR_COMP2          TIM1_AF1_ETRSEL_1                                     /* !< TIM1_ETR is connected to COMP2 output */
00099 #endif /* COMP2 */
00100
00101 #define TIM_TIM1_TI1_GPIO           0x00000000U                                           /* !< TIM1 Input capture 1 is connected to I/0      */
00102 #define TIM_TIM1_TI1_COMP1         TIM1_OR_TI1_RMP                                        /* !< TIM1 Input capture 1is connected to COMP1 OUT */
00103
00104 #define TIM_TIM2_ITR_NC             0x00000000U                                           /* !< TIM2 Internal trigger ITR is not connected          */
00105 #if defined(USB)
00106 #define TIM_TIM2_ITR_USB            TIM2_OR_ITR1_RMP                                      /* !< TIM2 Internal trigger ITR is connected to USBFS SOF */
00107 #endif /* USB */
00108
00109 #define TIM_TIM2_ETR_GPIO           0x00000000U                                           /* !< TIM2 External trigger ETR is connected to I/O */
00110 #define TIM_TIM2_ETR_LSE            TIM2_OR_ETR_RMP                                       /* !< TIM2 External trigger ETR is connected to LSE */
00111 #if defined(COMP1)
00112 #define TIM_TIM2_ETR_COMP1          TIM2_AF1_ETRSEL_0                                     /* !< TIM2_ETR is connected to COMP1 output         */
00113 #endif /* COMP1 */
00114 #if defined(COMP2)
00115 #define TIM_TIM2_ETR_COMP2          TIM2_AF1_ETRSEL_1                                     /* !< TIM2_ETR is connected to COMP2 output         */
00116 #endif /* COMP2 */
00117
00118 #define TIM_TIM2_TI4_GPIO           0x00000000U                                           /* !< TIM2_TI4 is connected to I/O                 */
00119 #if defined(COMP1)
00120 #define TIM_TIM2_TI4_COMP1          TIM2_OR_TI4_RMP_0                                     /* !< TIM2_TI4 is connected to COMP1 OUT           */
00121 #endif /* COMP1 */
00122 #if defined(COMP2)
00123 #define TIM_TIM2_TI4_COMP2          TIM2_OR_TI4_RMP_1                                     /* !< TIM2_TI4 is connected to COMP1 OUT           */
00124 #endif /* COMP2 */
00125 #if defined(COMP1) && defined(COMP2)
00126 #define TIM_TIM2_TI4_COMP1_COMP2    (TIM2_OR_TI4_RMP_0 | TIM2_OR_TI4_RMP_1)               /* !< TIM2_TI4 is connected to COMP1 and COMP2 OUT */
00127 #endif /* COMP1 && COMP2 */
00128
00129 #define TIM_TIM16_TI1_GPIO          0x00000000U                                           /* !< TIM16_TI1 is connected to I/O       */
00130 #define TIM_TIM16_TI1_LSI           TIM16_OR_TI1_RMP_0                                    /* !< TIM16_TI1 is connected to LSI Clock */
00131 #define TIM_TIM16_TI1_LSE           TIM16_OR_TI1_RMP_1                                    /* !< TIM16_TI1 is connected to LSE Clock */
00132 #define TIM_TIM16_TI1_RTC           (TIM16_OR_TI1_RMP_0 | TIM16_OR_TI1_RMP_1)             /* !< TIM16_TI1 is connected to RTC       */
00133
00134 #define TIM_TIM17_TI1_GPIO          0x00000000U                                           /* !< TIM17_TI1 is connected to I/O       */
00135 #define TIM_TIM17_TI1_MSI           TIM17_OR_TI1_RMP_0                                    /* !< TIM17_TI1 is connected to MSI       */
00136 #define TIM_TIM17_TI1_HSE           TIM17_OR_TI1_RMP_1                                    /* !< TIM17_TI1 is connected to HSE/32    */
00137 #define TIM_TIM17_TI1_MCO           (TIM17_OR_TI1_RMP_0 | TIM17_OR_TI1_RMP_1)             /* !< TIM17_TI1 is connected to MCO       */
00138 /**
00139   * @}
00140   */
00141
00142 /** @defgroup TIMEx_Break_Input TIM Extended Break input
00143   * @{
00144   */
00145 #define TIM_BREAKINPUT_BRK     0x00000001U                                      /* !< Timer break input  */
00146 #define TIM_BREAKINPUT_BRK2    0x00000002U                                      /* !< Timer break2 input */
00147 /**
00148   * @}
00149   */
00150
00151 /** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
00152   * @{
00153   */
00154 #define TIM_BREAKINPUTSOURCE_BKIN     0x00000001U                               /* !< An external source (GPIO) is connected to the BKIN pin  */
00155 #if defined(COMP1)
00156 #define TIM_BREAKINPUTSOURCE_COMP1    0x00000002U                               /* !< The COMP1 output is connected to the break input */
00157 #endif /* COMP1 */
00158 #if defined(COMP2)
00159 #define TIM_BREAKINPUTSOURCE_COMP2    0x00000004U                               /* !< The COMP2 output is connected to the break input */
00160 #endif /* COMP2 */
00161 /**
00162   * @}
00163   */
00164
00165 /** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
00166   * @{
00167   */
00168 #define TIM_BREAKINPUTSOURCE_DISABLE     0x00000000U                            /* !< Break input source is disabled */
00169 #define TIM_BREAKINPUTSOURCE_ENABLE      0x00000001U                            /* !< Break input source is enabled */
00170 /**
00171   * @}
00172   */
00173
00174 /** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity
00175   * @{
00176   */
00177 #define TIM_BREAKINPUTSOURCE_POLARITY_LOW     0x00000001U                       /* !< Break input source is active low */
00178 #define TIM_BREAKINPUTSOURCE_POLARITY_HIGH    0x00000000U                       /* !< Break input source is active_high */
00179 /**
00180   * @}
00181   */
00182
00183 /**
00184   * @}
00185   */
00186 /* End of exported constants -------------------------------------------------*/
00187
00188 /* Exported macro ------------------------------------------------------------*/
00189 /** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
00190   * @{
00191   */
00192
00193 /**
00194   * @}
00195   */
00196 /* End of exported macro -----------------------------------------------------*/
00197
00198 /* Private macro -------------------------------------------------------------*/
00199 /** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
00200   * @{
00201   */
00202 #define IS_TIM_REMAP(__INSTANCE__, __REMAP__)                                             \
00203           ((((__INSTANCE__) == TIM1)  && ((((__REMAP__) & 0xFFFE3FECU) == 0x00000000U)))  \
00204         || (((__INSTANCE__) == TIM2)  && ((((__REMAP__) & 0xFFFE3FF0U) == 0x00000000U)))  \
00205         || (((__INSTANCE__) == TIM16) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U)))  \
00206         || (((__INSTANCE__) == TIM17) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))))
00207
00208 #define IS_TIM_BREAKINPUT(__BREAKINPUT__)               \
00209           (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK)  || \
00210            ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
00211
00212 #if defined(COMP1) && defined(COMP2)
00213 #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__)                \
00214           (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \
00215            ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
00216            ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2))
00217 #else
00218 #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__)                \
00219           (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN))
00220 #endif
00221
00222 #define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__)             \
00223           (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE)  || \
00224            ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
00225
00226 #define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__)                 \
00227             (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW)  || \
00228              ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
00229
00230 /**
00231   * @}
00232   */
00233 /* End of private macro ------------------------------------------------------*/
00234
00235 /* Exported functions --------------------------------------------------------*/
00236 /** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
00237   * @{
00238   */
00239
00240 /** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
00241   *  @brief    Timer Hall Sensor functions
00242   * @{
00243   */
00244 /*  Timer Hall Sensor functions  **********************************************/
00245 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
00246 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
00247
00248 void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
00249 void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
00250
00251 /* Blocking mode: Polling */
00252 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
00253 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
00254 /* Non-Blocking mode: Interrupt */
00255 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
00256 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
00257 /* Non-Blocking mode: DMA */
00258 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
00259 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
00260 /**
00261   * @}
00262   */
00263
00264 /** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
00265   *  @brief   Timer Complementary Output Compare functions
00266   * @{
00267   */
00268 /*  Timer Complementary Output Compare functions  *****************************/
00269 /* Blocking mode: Polling */
00270 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
00271 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
00272
00273 /* Non-Blocking mode: Interrupt */
00274 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
00275 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
00276
00277 /* Non-Blocking mode: DMA */
00278 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
00279 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
00280 /**
00281   * @}
00282   */
00283
00284 /** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
00285   *  @brief    Timer Complementary PWM functions
00286   * @{
00287   */
00288 /*  Timer Complementary PWM functions  ****************************************/
00289 /* Blocking mode: Polling */
00290 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
00291 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
00292
00293 /* Non-Blocking mode: Interrupt */
00294 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
00295 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
00296 /* Non-Blocking mode: DMA */
00297 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
00298 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
00299 /**
00300   * @}
00301   */
00302
00303 /** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
00304   *  @brief    Timer Complementary One Pulse functions
00305   * @{
00306   */
00307 /*  Timer Complementary One Pulse functions  **********************************/
00308 /* Blocking mode: Polling */
00309 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
00310 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
00311
00312 /* Non-Blocking mode: Interrupt */
00313 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
00314 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
00315 /**
00316   * @}
00317   */
00318
00319 /** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
00320   *  @brief    Peripheral Control functions
00321   * @{
00322   */
00323 /* Extended Control functions  ************************************************/
00324 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
00325                                               uint32_t  CommutationSource);
00326 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
00327                                                  uint32_t  CommutationSource);
00328 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
00329                                                   uint32_t  CommutationSource);
00330 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
00331                                                         TIM_MasterConfigTypeDef *sMasterConfig);
00332 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
00333                                                 TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
00334 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput,
00335                                              TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
00336 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
00337 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
00338 /**
00339   * @}
00340   */
00341
00342 /** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
00343   * @brief    Extended Callbacks functions
00344   * @{
00345   */
00346 /* Extended Callback **********************************************************/
00347 void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
00348 void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
00349 void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
00350 void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);
00351 /**
00352   * @}
00353   */
00354
00355 /** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
00356   * @brief    Extended Peripheral State functions
00357   * @{
00358   */
00359 /* Extended Peripheral State functions  ***************************************/
00360 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
00361 /**
00362   * @}
00363   */
00364
00365 /**
00366   * @}
00367   */
00368 /* End of exported functions -------------------------------------------------*/
00369
00370 /* Private functions----------------------------------------------------------*/
00371 /** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
00372   * @{
00373   */
00374 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
00375 void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
00376 /**
00377   * @}
00378   */
00379 /* End of private functions --------------------------------------------------*/
00380
00381 /**
00382   * @}
00383   */
00384
00385 /**
00386   * @}
00387   */
00388
00389 #ifdef __cplusplus
00390 }
00391 #endif
00392
00393
00394 #endif /* STM32WBxx_HAL_TIM_EX_H */
00395
00396 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:35 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_tsc.c Source File

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stm32wbxx_hal_tsc.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_tsc.c
00004   * @author  MCD Application Team
00005   * @brief   This file provides firmware functions to manage the following
00006   *          functionalities of the Touch Sensing Controller (TSC) peripheral:
00007   *           + Initialization and De-initialization
00008   *           + Channel IOs, Shield IOs and Sampling IOs configuration
00009   *           + Start and Stop an acquisition
00010   *           + Read acquisition result
00011   *           + Interrupts and flags management
00012   *
00013   @verbatim
00014 ================================================================================
00015                        ##### TSC specific features #####
00016 ================================================================================
00017   [..]
00018   (#) Proven and robust surface charge transfer acquisition principle
00019
00020   (#) Supports up to 3 capacitive sensing channels per group
00021
00022   (#) Capacitive sensing channels can be acquired in parallel offering a very good
00023       response time
00024
00025   (#) Spread spectrum feature to improve system robustness in noisy environments
00026
00027   (#) Full hardware management of the charge transfer acquisition sequence
00028
00029   (#) Programmable charge transfer frequency
00030
00031   (#) Programmable sampling capacitor I/O pin
00032
00033   (#) Programmable channel I/O pin
00034
00035   (#) Programmable max count value to avoid long acquisition when a channel is faulty
00036
00037   (#) Dedicated end of acquisition and max count error flags with interrupt capability
00038
00039   (#) One sampling capacitor for up to 3 capacitive sensing channels to reduce the system
00040       components
00041
00042   (#) Compatible with proximity, touchkey, linear and rotary touch sensor implementation
00043
00044                           ##### How to use this driver #####
00045 ================================================================================
00046   [..]
00047     (#) Enable the TSC interface clock using __HAL_RCC_TSC_CLK_ENABLE() macro.
00048
00049     (#) GPIO pins configuration
00050       (++) Enable the clock for the TSC GPIOs using __HAL_RCC_GPIOx_CLK_ENABLE() macro.
00051       (++) Configure the TSC pins used as sampling IOs in alternate function output Open-Drain mode,
00052            and TSC pins used as channel/shield IOs in alternate function output Push-Pull mode
00053            using HAL_GPIO_Init() function.
00054
00055     (#) Interrupts configuration
00056       (++) Configure the NVIC (if the interrupt model is used) using HAL_NVIC_SetPriority()
00057            and HAL_NVIC_EnableIRQ() and function.
00058
00059     (#) TSC configuration
00060       (++) Configure all TSC parameters and used TSC IOs using HAL_TSC_Init() function.
00061
00062  [..]   TSC peripheral alternate functions are mapped on AF9.
00063
00064   *** Acquisition sequence ***
00065   ===================================
00066   [..]
00067     (+) Discharge all IOs using HAL_TSC_IODischarge() function.
00068     (+) Wait a certain time allowing a good discharge of all capacitors. This delay depends
00069         of the sampling capacitor and electrodes design.
00070     (+) Select the channel IOs to be acquired using HAL_TSC_IOConfig() function.
00071     (+) Launch the acquisition using either HAL_TSC_Start() or HAL_TSC_Start_IT() function.
00072         If the synchronized mode is selected, the acquisition will start as soon as the signal
00073         is received on the synchro pin.
00074     (+) Wait the end of acquisition using either HAL_TSC_PollForAcquisition() or
00075         HAL_TSC_GetState() function or using WFI instruction for example.
00076     (+) Check the group acquisition status using HAL_TSC_GroupGetStatus() function.
00077     (+) Read the acquisition value using HAL_TSC_GroupGetValue() function.
00078
00079      *** Callback registration ***
00080      =============================================
00081
00082   [..]
00083      The compilation flag USE_HAL_TSC_REGISTER_CALLBACKS when set to 1
00084      allows the user to configure dynamically the driver callbacks.
00085      Use Functions @ref HAL_TSC_RegisterCallback() to register an interrupt callback.
00086
00087   [..]
00088      Function @ref HAL_TSC_RegisterCallback() allows to register following callbacks:
00089        (+) ConvCpltCallback   : callback for conversion complete process.
00090        (+) ErrorCallback      : callback for error detection.
00091        (+) MspInitCallback    : callback for Msp Init.
00092        (+) MspDeInitCallback  : callback for Msp DeInit.
00093   [..]
00094      This function takes as parameters the HAL peripheral handle, the Callback ID
00095      and a pointer to the user callback function.
00096
00097   [..]
00098      Use function @ref HAL_TSC_UnRegisterCallback to reset a callback to the default
00099      weak function.
00100      @ref HAL_TSC_UnRegisterCallback takes as parameters the HAL peripheral handle,
00101      and the Callback ID.
00102   [..]
00103      This function allows to reset following callbacks:
00104        (+) ConvCpltCallback   : callback for conversion complete process.
00105        (+) ErrorCallback      : callback for error detection.
00106        (+) MspInitCallback    : callback for Msp Init.
00107        (+) MspDeInitCallback  : callback for Msp DeInit.
00108
00109   [..]
00110      By default, after the @ref HAL_TSC_Init() and when the state is @ref HAL_TSC_STATE_RESET
00111      all callbacks are set to the corresponding weak functions:
00112      examples @ref HAL_TSC_ConvCpltCallback(), @ref HAL_TSC_ErrorCallback().
00113      Exception done for MspInit and MspDeInit functions that are
00114      reset to the legacy weak functions in the @ref HAL_TSC_Init()/ @ref HAL_TSC_DeInit() only when
00115      these callbacks are null (not registered beforehand).
00116      If MspInit or MspDeInit are not null, the @ref HAL_TSC_Init()/ @ref HAL_TSC_DeInit()
00117      keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
00118
00119   [..]
00120      Callbacks can be registered/unregistered in @ref HAL_TSC_STATE_READY state only.
00121      Exception done MspInit/MspDeInit functions that can be registered/unregistered
00122      in @ref HAL_TSC_STATE_READY or @ref HAL_TSC_STATE_RESET state,
00123      thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
00124      Then, the user first registers the MspInit/MspDeInit user callbacks
00125      using @ref HAL_TSC_RegisterCallback() before calling @ref HAL_TSC_DeInit()
00126      or @ref HAL_TSC_Init() function.
00127
00128   [..]
00129      When the compilation flag USE_HAL_TSC_REGISTER_CALLBACKS is set to 0 or
00130      not defined, the callback registration feature is not available and all callbacks
00131      are set to the corresponding weak functions.
00132
00133   @endverbatim
00134   ******************************************************************************
00135
00136     Table 1. IOs for the STM32WBxx devices
00137     +--------------------------------+
00138     |       IOs    |   TSC functions |
00139     |--------------|-----------------|
00140     |   PB12 (AF)  |   TSC_G1_IO1    |
00141     |   PB13 (AF)  |   TSC_G1_IO2    |
00142     |   PB14 (AF)  |   TSC_G1_IO3    |
00143     |   PB15 (AF)  |   TSC_G1_IO4    |
00144     |--------------|-----------------|
00145     |   PB4 (AF)   |   TSC_G2_IO1    |
00146     |   PB5 (AF)   |   TSC_G2_IO2    |
00147     |   PB6 (AF)   |   TSC_G2_IO3    |
00148     |   PB7 (AF)   |   TSC_G2_IO4    |
00149     |--------------|-----------------|
00150     |   PA15 (AF)  |   TSC_G3_IO1    |
00151     |   PC10 (AF)  |   TSC_G3_IO2    |
00152     |   PC11 (AF)  |   TSC_G3_IO3    |
00153     |   PC12 (AF)  |   TSC_G3_IO4    |
00154     |--------------|-----------------|
00155     |   PC6  (AF)  |   TSC_G4_IO1    |
00156     |   PC7  (AF)  |   TSC_G4_IO2    |
00157     |   PC8  (AF)  |   TSC_G4_IO3    |
00158     |   PC9  (AF)  |   TSC_G4_IO4    |
00159     |--------------|-----------------|
00160     |   PD4  (AF)  |   TSC_G5_IO1    |
00161     |   PD5  (AF)  |   TSC_G5_IO2    |
00162     |   PD6  (AF)  |   TSC_G5_IO3    |
00163     |   PD7  (AF)  |   TSC_G5_IO4    |
00164     |--------------|-----------------|
00165     |   PD10 (AF)  |   TSC_G6_IO1    |
00166     |   PD11 (AF)  |   TSC_G6_IO2    |
00167     |   PD12 (AF)  |   TSC_G6_IO3    |
00168     |   PD13 (AF)  |   TSC_G6_IO4    |
00169     |--------------|-----------------|
00170     |   PE2  (AF)  |   TSC_G7_IO1    |
00171     |   PE1  (AF)  |   TSC_G7_IO2    |
00172     |   PE0  (AF)  |   TSC_G7_IO3    |
00173     |   PB9  (AF)  |   TSC_G7_IO4    |
00174     |--------------|-----------------|
00175     |   PB10 (AF)  |   TSC_SYNC      |
00176     |   PD2  (AF)  |                 |
00177     +--------------------------------+
00178
00179   ******************************************************************************
00180   * @attention
00181   *
00182   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00183   * All rights reserved.</center></h2>
00184   *
00185   * This software component is licensed by ST under BSD 3-Clause license,
00186   * the "License"; You may not use this file except in compliance with the
00187   * License. You may obtain a copy of the License at:
00188   *                        opensource.org/licenses/BSD-3-Clause
00189   *
00190   ******************************************************************************
00191   */
00192
00193 /* Includes ------------------------------------------------------------------*/
00194 #include "stm32wbxx_hal.h"
00195
00196 #if defined(TSC)
00197 /** @addtogroup STM32WBxx_HAL_Driver
00198   * @{
00199   */
00200
00201 /** @defgroup TSC TSC
00202   * @brief HAL TSC module driver
00203   * @{
00204   */
00205
00206 #ifdef HAL_TSC_MODULE_ENABLED
00207
00208 /* Private typedef -----------------------------------------------------------*/
00209 /* Private define ------------------------------------------------------------*/
00210 /* Private macro -------------------------------------------------------------*/
00211 /* Private variables ---------------------------------------------------------*/
00212 /* Private function prototypes -----------------------------------------------*/
00213 static uint32_t TSC_extract_groups(uint32_t iomask);
00214
00215 /* Exported functions --------------------------------------------------------*/
00216
00217 /** @defgroup TSC_Exported_Functions TSC Exported Functions
00218   * @{
00219   */
00220
00221 /** @defgroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions
00222  *  @brief    Initialization and Configuration functions
00223  *
00224 @verbatim
00225  ===============================================================================
00226               ##### Initialization and de-initialization functions #####
00227  ===============================================================================
00228     [..]  This section provides functions allowing to:
00229       (+) Initialize and configure the TSC.
00230       (+) De-initialize the TSC.
00231 @endverbatim
00232   * @{
00233   */
00234
00235 /**
00236   * @brief  Initialize the TSC peripheral according to the specified parameters
00237   *         in the TSC_InitTypeDef structure and initialize the associated handle.
00238   * @param  htsc TSC handle
00239   * @retval HAL status
00240   */
00241 HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef *htsc)
00242 {
00243   /* Check TSC handle allocation */
00244   if (htsc == NULL)
00245   {
00246     return HAL_ERROR;
00247   }
00248
00249   /* Check the parameters */
00250   assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
00251   assert_param(IS_TSC_CTPH(htsc->Init.CTPulseHighLength));
00252   assert_param(IS_TSC_CTPL(htsc->Init.CTPulseLowLength));
00253   assert_param(IS_TSC_SS(htsc->Init.SpreadSpectrum));
00254   assert_param(IS_TSC_SSD(htsc->Init.SpreadSpectrumDeviation));
00255   assert_param(IS_TSC_SS_PRESC(htsc->Init.SpreadSpectrumPrescaler));
00256   assert_param(IS_TSC_PG_PRESC(htsc->Init.PulseGeneratorPrescaler));
00257   assert_param(IS_TSC_MCV(htsc->Init.MaxCountValue));
00258   assert_param(IS_TSC_IODEF(htsc->Init.IODefaultMode));
00259   assert_param(IS_TSC_SYNC_POL(htsc->Init.SynchroPinPolarity));
00260   assert_param(IS_TSC_ACQ_MODE(htsc->Init.AcquisitionMode));
00261   assert_param(IS_TSC_MCE_IT(htsc->Init.MaxCountInterrupt));
00262   assert_param(IS_TSC_GROUP(htsc->Init.ChannelIOs));
00263   assert_param(IS_TSC_GROUP(htsc->Init.ShieldIOs));
00264   assert_param(IS_TSC_GROUP(htsc->Init.SamplingIOs));
00265
00266   if (htsc->State == HAL_TSC_STATE_RESET)
00267   {
00268     /* Allocate lock resource and initialize it */
00269     htsc->Lock = HAL_UNLOCKED;
00270
00271 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
00272     /* Init the TSC Callback settings */
00273     htsc->ConvCpltCallback  = HAL_TSC_ConvCpltCallback; /* Legacy weak ConvCpltCallback     */
00274     htsc->ErrorCallback     = HAL_TSC_ErrorCallback;    /* Legacy weak ErrorCallback        */
00275
00276     if (htsc->MspInitCallback == NULL)
00277     {
00278       htsc->MspInitCallback = HAL_TSC_MspInit; /* Legacy weak MspInit  */
00279     }
00280
00281     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00282     htsc->MspInitCallback(htsc);
00283 #else
00284     /* Init the low level hardware : GPIO, CLOCK, CORTEX */
00285     HAL_TSC_MspInit(htsc);
00286 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
00287   }
00288
00289   /* Initialize the TSC state */
00290   htsc->State = HAL_TSC_STATE_BUSY;
00291
00292   /*--------------------------------------------------------------------------*/
00293   /* Set TSC parameters */
00294
00295   /* Enable TSC */
00296   htsc->Instance->CR = TSC_CR_TSCE;
00297
00298   /* Set all functions */
00299   htsc->Instance->CR |= (htsc->Init.CTPulseHighLength |
00300                          htsc->Init.CTPulseLowLength |
00301                          (htsc->Init.SpreadSpectrumDeviation << TSC_CR_SSD_Pos) |
00302                          htsc->Init.SpreadSpectrumPrescaler |
00303                          htsc->Init.PulseGeneratorPrescaler |
00304                          htsc->Init.MaxCountValue |
00305                          htsc->Init.SynchroPinPolarity |
00306                          htsc->Init.AcquisitionMode);
00307
00308   /* Spread spectrum */
00309   if (htsc->Init.SpreadSpectrum == ENABLE)
00310   {
00311     htsc->Instance->CR |= TSC_CR_SSE;
00312   }
00313
00314   /* Disable Schmitt trigger hysteresis on all used TSC IOs */
00315   htsc->Instance->IOHCR = (~(htsc->Init.ChannelIOs | htsc->Init.ShieldIOs | htsc->Init.SamplingIOs));
00316
00317   /* Set channel and shield IOs */
00318   htsc->Instance->IOCCR = (htsc->Init.ChannelIOs | htsc->Init.ShieldIOs);
00319
00320   /* Set sampling IOs */
00321   htsc->Instance->IOSCR = htsc->Init.SamplingIOs;
00322
00323   /* Set the groups to be acquired */
00324   htsc->Instance->IOGCSR = TSC_extract_groups(htsc->Init.ChannelIOs);
00325
00326   /* Disable interrupts */
00327   htsc->Instance->IER &= (~(TSC_IT_EOA | TSC_IT_MCE));
00328
00329   /* Clear flags */
00330   htsc->Instance->ICR = (TSC_FLAG_EOA | TSC_FLAG_MCE);
00331
00332   /*--------------------------------------------------------------------------*/
00333
00334   /* Initialize the TSC state */
00335   htsc->State = HAL_TSC_STATE_READY;
00336
00337   /* Return function status */
00338   return HAL_OK;
00339 }
00340
00341 /**
00342   * @brief  Deinitialize the TSC peripheral registers to their default reset values.
00343   * @param  htsc TSC handle
00344   * @retval HAL status
00345   */
00346 HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc)
00347 {
00348   /* Check TSC handle allocation */
00349   if (htsc == NULL)
00350   {
00351     return HAL_ERROR;
00352   }
00353
00354   /* Check the parameters */
00355   assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
00356
00357   /* Change TSC state */
00358   htsc->State = HAL_TSC_STATE_BUSY;
00359
00360 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
00361   if (htsc->MspDeInitCallback == NULL)
00362   {
00363     htsc->MspDeInitCallback = HAL_TSC_MspDeInit; /* Legacy weak MspDeInit  */
00364   }
00365
00366   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00367   htsc->MspDeInitCallback(htsc);
00368 #else
00369   /* DeInit the low level hardware */
00370   HAL_TSC_MspDeInit(htsc);
00371 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
00372
00373   /* Change TSC state */
00374   htsc->State = HAL_TSC_STATE_RESET;
00375
00376   /* Process unlocked */
00377   __HAL_UNLOCK(htsc);
00378
00379   /* Return function status */
00380   return HAL_OK;
00381 }
00382
00383 /**
00384   * @brief  Initialize the TSC MSP.
00385   * @param  htsc Pointer to a TSC_HandleTypeDef structure that contains
00386   *         the configuration information for the specified TSC.
00387   * @retval None
00388   */
00389 __weak void HAL_TSC_MspInit(TSC_HandleTypeDef *htsc)
00390 {
00391   /* Prevent unused argument(s) compilation warning */
00392   UNUSED(htsc);
00393
00394   /* NOTE : This function should not be modified, when the callback is needed,
00395             the HAL_TSC_MspInit could be implemented in the user file.
00396    */
00397 }
00398
00399 /**
00400   * @brief  DeInitialize the TSC MSP.
00401   * @param  htsc Pointer to a TSC_HandleTypeDef structure that contains
00402   *         the configuration information for the specified TSC.
00403   * @retval None
00404   */
00405 __weak void HAL_TSC_MspDeInit(TSC_HandleTypeDef *htsc)
00406 {
00407   /* Prevent unused argument(s) compilation warning */
00408   UNUSED(htsc);
00409
00410   /* NOTE : This function should not be modified, when the callback is needed,
00411             the HAL_TSC_MspDeInit could be implemented in the user file.
00412    */
00413 }
00414
00415 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
00416 /**
00417   * @brief  Register a User TSC Callback
00418   *         To be used instead of the weak predefined callback
00419   * @param  htsc Pointer to a TSC_HandleTypeDef structure that contains
00420   *                the configuration information for the specified TSC.
00421   * @param  CallbackID ID of the callback to be registered
00422   *         This parameter can be one of the following values:
00423   *          @arg @ref HAL_TSC_CONV_COMPLETE_CB_ID Conversion completed callback ID
00424   *          @arg @ref HAL_TSC_ERROR_CB_ID Error callback ID
00425   *          @arg @ref HAL_TSC_MSPINIT_CB_ID MspInit callback ID
00426   *          @arg @ref HAL_TSC_MSPDEINIT_CB_ID MspDeInit callback ID
00427   * @param  pCallback pointer to the Callback function
00428   * @retval HAL status
00429   */
00430 HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID, pTSC_CallbackTypeDef pCallback)
00431 {
00432   HAL_StatusTypeDef status = HAL_OK;
00433
00434   if (pCallback == NULL)
00435   {
00436     /* Update the error code */
00437     htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK;
00438
00439     return HAL_ERROR;
00440   }
00441   /* Process locked */
00442   __HAL_LOCK(htsc);
00443
00444   if (HAL_TSC_STATE_READY == htsc->State)
00445   {
00446     switch (CallbackID)
00447     {
00448       case HAL_TSC_CONV_COMPLETE_CB_ID :
00449         htsc->ConvCpltCallback = pCallback;
00450         break;
00451
00452       case HAL_TSC_ERROR_CB_ID :
00453         htsc->ErrorCallback = pCallback;
00454         break;
00455
00456       case HAL_TSC_MSPINIT_CB_ID :
00457         htsc->MspInitCallback = pCallback;
00458         break;
00459
00460       case HAL_TSC_MSPDEINIT_CB_ID :
00461         htsc->MspDeInitCallback = pCallback;
00462         break;
00463
00464       default :
00465         /* Update the error code */
00466         htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK;
00467
00468         /* Return error status */
00469         status =  HAL_ERROR;
00470         break;
00471     }
00472   }
00473   else if (HAL_TSC_STATE_RESET == htsc->State)
00474   {
00475     switch (CallbackID)
00476     {
00477       case HAL_TSC_MSPINIT_CB_ID :
00478         htsc->MspInitCallback = pCallback;
00479         break;
00480
00481       case HAL_TSC_MSPDEINIT_CB_ID :
00482         htsc->MspDeInitCallback = pCallback;
00483         break;
00484
00485       default :
00486         /* Update the error code */
00487         htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK;
00488
00489         /* Return error status */
00490         status =  HAL_ERROR;
00491         break;
00492     }
00493   }
00494   else
00495   {
00496     /* Update the error code */
00497     htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK;
00498
00499     /* Return error status */
00500     status =  HAL_ERROR;
00501   }
00502
00503   /* Release Lock */
00504   __HAL_UNLOCK(htsc);
00505   return status;
00506 }
00507
00508 /**
00509   * @brief  Unregister an TSC Callback
00510   *         TSC callback is redirected to the weak predefined callback
00511   * @param  htsc Pointer to a TSC_HandleTypeDef structure that contains
00512   *                the configuration information for the specified TSC.
00513   * @param  CallbackID ID of the callback to be unregistered
00514   *         This parameter can be one of the following values:
00515   *         This parameter can be one of the following values:
00516   *          @arg @ref HAL_TSC_CONV_COMPLETE_CB_ID Conversion completed callback ID
00517   *          @arg @ref HAL_TSC_ERROR_CB_ID Error callback ID
00518   *          @arg @ref HAL_TSC_MSPINIT_CB_ID MspInit callback ID
00519   *          @arg @ref HAL_TSC_MSPDEINIT_CB_ID MspDeInit callback ID
00520   * @retval HAL status
00521   */
00522 HAL_StatusTypeDef HAL_TSC_UnRegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID)
00523 {
00524   HAL_StatusTypeDef status = HAL_OK;
00525
00526   /* Process locked */
00527   __HAL_LOCK(htsc);
00528
00529   if (HAL_TSC_STATE_READY == htsc->State)
00530   {
00531     switch (CallbackID)
00532     {
00533       case HAL_TSC_CONV_COMPLETE_CB_ID :
00534         htsc->ConvCpltCallback = HAL_TSC_ConvCpltCallback;       /* Legacy weak ConvCpltCallback      */
00535         break;
00536
00537       case HAL_TSC_ERROR_CB_ID :
00538         htsc->ErrorCallback = HAL_TSC_ErrorCallback;               /* Legacy weak ErrorCallback        */
00539         break;
00540
00541       case HAL_TSC_MSPINIT_CB_ID :
00542         htsc->MspInitCallback = HAL_TSC_MspInit;                   /* Legacy weak MspInit              */
00543         break;
00544
00545       case HAL_TSC_MSPDEINIT_CB_ID :
00546         htsc->MspDeInitCallback = HAL_TSC_MspDeInit;               /* Legacy weak MspDeInit            */
00547         break;
00548
00549       default :
00550         /* Update the error code */
00551         htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK;
00552
00553         /* Return error status */
00554         status =  HAL_ERROR;
00555         break;
00556     }
00557   }
00558   else if (HAL_TSC_STATE_RESET == htsc->State)
00559   {
00560     switch (CallbackID)
00561     {
00562       case HAL_TSC_MSPINIT_CB_ID :
00563         htsc->MspInitCallback = HAL_TSC_MspInit;                   /* Legacy weak MspInit              */
00564         break;
00565
00566       case HAL_TSC_MSPDEINIT_CB_ID :
00567         htsc->MspDeInitCallback = HAL_TSC_MspDeInit;               /* Legacy weak MspDeInit            */
00568         break;
00569
00570       default :
00571         /* Update the error code */
00572         htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK;
00573
00574         /* Return error status */
00575         status =  HAL_ERROR;
00576         break;
00577     }
00578   }
00579   else
00580   {
00581     /* Update the error code */
00582     htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK;
00583
00584     /* Return error status */
00585     status =  HAL_ERROR;
00586   }
00587
00588   /* Release Lock */
00589   __HAL_UNLOCK(htsc);
00590   return status;
00591 }
00592
00593 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
00594
00595 /**
00596   * @}
00597   */
00598
00599 /** @defgroup TSC_Exported_Functions_Group2 Input and Output operation functions
00600  *  @brief    Input and Output operation functions
00601  *
00602 @verbatim
00603  ===============================================================================
00604              ##### IO Operation functions #####
00605  ===============================================================================
00606     [..]  This section provides functions allowing to:
00607       (+) Start acquisition in polling mode.
00608       (+) Start acquisition in interrupt mode.
00609       (+) Stop conversion in polling mode.
00610       (+) Stop conversion in interrupt mode.
00611       (+) Poll for acquisition completed.
00612       (+) Get group acquisition status.
00613       (+) Get group acquisition value.
00614 @endverbatim
00615   * @{
00616   */
00617
00618 /**
00619   * @brief  Start the acquisition.
00620   * @param  htsc Pointer to a TSC_HandleTypeDef structure that contains
00621   *         the configuration information for the specified TSC.
00622   * @retval HAL status
00623   */
00624 HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef *htsc)
00625 {
00626   /* Check the parameters */
00627   assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
00628
00629   /* Process locked */
00630   __HAL_LOCK(htsc);
00631
00632   /* Change TSC state */
00633   htsc->State = HAL_TSC_STATE_BUSY;
00634
00635   /* Clear interrupts */
00636   __HAL_TSC_DISABLE_IT(htsc, (TSC_IT_EOA | TSC_IT_MCE));
00637
00638   /* Clear flags */
00639   __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
00640
00641   /* Set touch sensing IOs not acquired to the specified IODefaultMode */
00642   if (htsc->Init.IODefaultMode == TSC_IODEF_OUT_PP_LOW)
00643   {
00644     __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
00645   }
00646   else
00647   {
00648     __HAL_TSC_SET_IODEF_INFLOAT(htsc);
00649   }
00650
00651   /* Launch the acquisition */
00652   __HAL_TSC_START_ACQ(htsc);
00653
00654   /* Process unlocked */
00655   __HAL_UNLOCK(htsc);
00656
00657   /* Return function status */
00658   return HAL_OK;
00659 }
00660
00661 /**
00662   * @brief  Start the acquisition in interrupt mode.
00663   * @param  htsc Pointer to a TSC_HandleTypeDef structure that contains
00664   *         the configuration information for the specified TSC.
00665   * @retval HAL status.
00666   */
00667 HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef *htsc)
00668 {
00669   /* Check the parameters */
00670   assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
00671   assert_param(IS_TSC_MCE_IT(htsc->Init.MaxCountInterrupt));
00672
00673   /* Process locked */
00674   __HAL_LOCK(htsc);
00675
00676   /* Change TSC state */
00677   htsc->State = HAL_TSC_STATE_BUSY;
00678
00679   /* Enable end of acquisition interrupt */
00680   __HAL_TSC_ENABLE_IT(htsc, TSC_IT_EOA);
00681
00682   /* Enable max count error interrupt (optional) */
00683   if (htsc->Init.MaxCountInterrupt == ENABLE)
00684   {
00685     __HAL_TSC_ENABLE_IT(htsc, TSC_IT_MCE);
00686   }
00687   else
00688   {
00689     __HAL_TSC_DISABLE_IT(htsc, TSC_IT_MCE);
00690   }
00691
00692   /* Clear flags */
00693   __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
00694
00695   /* Set touch sensing IOs not acquired to the specified IODefaultMode */
00696   if (htsc->Init.IODefaultMode == TSC_IODEF_OUT_PP_LOW)
00697   {
00698     __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
00699   }
00700   else
00701   {
00702     __HAL_TSC_SET_IODEF_INFLOAT(htsc);
00703   }
00704
00705   /* Launch the acquisition */
00706   __HAL_TSC_START_ACQ(htsc);
00707
00708   /* Process unlocked */
00709   __HAL_UNLOCK(htsc);
00710
00711   /* Return function status */
00712   return HAL_OK;
00713 }
00714
00715 /**
00716   * @brief  Stop the acquisition previously launched in polling mode.
00717   * @param  htsc Pointer to a TSC_HandleTypeDef structure that contains
00718   *         the configuration information for the specified TSC.
00719   * @retval HAL status
00720   */
00721 HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef *htsc)
00722 {
00723   /* Check the parameters */
00724   assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
00725
00726   /* Process locked */
00727   __HAL_LOCK(htsc);
00728
00729   /* Stop the acquisition */
00730   __HAL_TSC_STOP_ACQ(htsc);
00731
00732   /* Set touch sensing IOs in low power mode (output push-pull) */
00733   __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
00734
00735   /* Clear flags */
00736   __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
00737
00738   /* Change TSC state */
00739   htsc->State = HAL_TSC_STATE_READY;
00740
00741   /* Process unlocked */
00742   __HAL_UNLOCK(htsc);
00743
00744   /* Return function status */
00745   return HAL_OK;
00746 }
00747
00748 /**
00749   * @brief  Stop the acquisition previously launched in interrupt mode.
00750   * @param  htsc Pointer to a TSC_HandleTypeDef structure that contains
00751   *         the configuration information for the specified TSC.
00752   * @retval HAL status
00753   */
00754 HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef *htsc)
00755 {
00756   /* Check the parameters */
00757   assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
00758
00759   /* Process locked */
00760   __HAL_LOCK(htsc);
00761
00762   /* Stop the acquisition */
00763   __HAL_TSC_STOP_ACQ(htsc);
00764
00765   /* Set touch sensing IOs in low power mode (output push-pull) */
00766   __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
00767
00768   /* Disable interrupts */
00769   __HAL_TSC_DISABLE_IT(htsc, (TSC_IT_EOA | TSC_IT_MCE));
00770
00771   /* Clear flags */
00772   __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
00773
00774   /* Change TSC state */
00775   htsc->State = HAL_TSC_STATE_READY;
00776
00777   /* Process unlocked */
00778   __HAL_UNLOCK(htsc);
00779
00780   /* Return function status */
00781   return HAL_OK;
00782 }
00783
00784 /**
00785   * @brief  Start acquisition and wait until completion.
00786   * @note   There is no need of a timeout parameter as the max count error is already
00787   *         managed by the TSC peripheral.
00788   * @param  htsc Pointer to a TSC_HandleTypeDef structure that contains
00789   *         the configuration information for the specified TSC.
00790   * @retval HAL state
00791   */
00792 HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef *htsc)
00793 {
00794   /* Check the parameters */
00795   assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
00796
00797   /* Process locked */
00798   __HAL_LOCK(htsc);
00799
00800   /* Check end of acquisition */
00801   while (HAL_TSC_GetState(htsc) == HAL_TSC_STATE_BUSY)
00802   {
00803     /* The timeout (max count error) is managed by the TSC peripheral itself. */
00804   }
00805
00806   /* Process unlocked */
00807   __HAL_UNLOCK(htsc);
00808
00809   return HAL_OK;
00810 }
00811
00812 /**
00813   * @brief  Get the acquisition status for a group.
00814   * @param  htsc Pointer to a TSC_HandleTypeDef structure that contains
00815   *         the configuration information for the specified TSC.
00816   * @param  gx_index Index of the group
00817   * @retval Group status
00818   */
00819 TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef *htsc, uint32_t gx_index)
00820 {
00821   /* Check the parameters */
00822   assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
00823   assert_param(IS_TSC_GROUP_INDEX(gx_index));
00824
00825   /* Return the group status */
00826   return (__HAL_TSC_GET_GROUP_STATUS(htsc, gx_index));
00827 }
00828
00829 /**
00830   * @brief  Get the acquisition measure for a group.
00831   * @param  htsc Pointer to a TSC_HandleTypeDef structure that contains
00832   *         the configuration information for the specified TSC.
00833   * @param  gx_index Index of the group
00834   * @retval Acquisition measure
00835   */
00836 uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef *htsc, uint32_t gx_index)
00837 {
00838   /* Check the parameters */
00839   assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
00840   assert_param(IS_TSC_GROUP_INDEX(gx_index));
00841
00842   /* Return the group acquisition counter */
00843   return htsc->Instance->IOGXCR[gx_index];
00844 }
00845
00846 /**
00847   * @}
00848   */
00849
00850 /** @defgroup TSC_Exported_Functions_Group3 Peripheral Control functions
00851  *  @brief    Peripheral Control functions
00852  *
00853 @verbatim
00854  ===============================================================================
00855              ##### Peripheral Control functions #####
00856  ===============================================================================
00857     [..]  This section provides functions allowing to:
00858       (+) Configure TSC IOs
00859       (+) Discharge TSC IOs
00860 @endverbatim
00861   * @{
00862   */
00863
00864 /**
00865   * @brief  Configure TSC IOs.
00866   * @param  htsc Pointer to a TSC_HandleTypeDef structure that contains
00867   *         the configuration information for the specified TSC.
00868   * @param  config Pointer to the configuration structure.
00869   * @retval HAL status
00870   */
00871 HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, TSC_IOConfigTypeDef *config)
00872 {
00873   /* Check the parameters */
00874   assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
00875   assert_param(IS_TSC_GROUP(config->ChannelIOs));
00876   assert_param(IS_TSC_GROUP(config->ShieldIOs));
00877   assert_param(IS_TSC_GROUP(config->SamplingIOs));
00878
00879   /* Process locked */
00880   __HAL_LOCK(htsc);
00881
00882   /* Stop acquisition */
00883   __HAL_TSC_STOP_ACQ(htsc);
00884
00885   /* Disable Schmitt trigger hysteresis on all used TSC IOs */
00886   htsc->Instance->IOHCR = (~(config->ChannelIOs | config->ShieldIOs | config->SamplingIOs));
00887
00888   /* Set channel and shield IOs */
00889   htsc->Instance->IOCCR = (config->ChannelIOs | config->ShieldIOs);
00890
00891   /* Set sampling IOs */
00892   htsc->Instance->IOSCR = config->SamplingIOs;
00893
00894   /* Set groups to be acquired */
00895   htsc->Instance->IOGCSR = TSC_extract_groups(config->ChannelIOs);
00896
00897   /* Process unlocked */
00898   __HAL_UNLOCK(htsc);
00899
00900   /* Return function status */
00901   return HAL_OK;
00902 }
00903
00904 /**
00905   * @brief  Discharge TSC IOs.
00906   * @param  htsc Pointer to a TSC_HandleTypeDef structure that contains
00907   *         the configuration information for the specified TSC.
00908   * @param  choice This parameter can be set to ENABLE or DISABLE.
00909   * @retval HAL status
00910   */
00911 HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef *htsc, FunctionalState choice)
00912 {
00913   /* Check the parameters */
00914   assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
00915
00916   /* Process locked */
00917   __HAL_LOCK(htsc);
00918
00919   if (choice == ENABLE)
00920   {
00921     __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
00922   }
00923   else
00924   {
00925     __HAL_TSC_SET_IODEF_INFLOAT(htsc);
00926   }
00927
00928   /* Process unlocked */
00929   __HAL_UNLOCK(htsc);
00930
00931   /* Return the group acquisition counter */
00932   return HAL_OK;
00933 }
00934
00935 /**
00936   * @}
00937   */
00938
00939 /** @defgroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions
00940  *  @brief   Peripheral State and Errors functions
00941  *
00942 @verbatim
00943  ===============================================================================
00944             ##### State and Errors functions #####
00945  ===============================================================================
00946     [..]
00947     This subsection provides functions allowing to
00948       (+) Get TSC state.
00949
00950 @endverbatim
00951   * @{
00952   */
00953
00954 /**
00955   * @brief  Return the TSC handle state.
00956   * @param  htsc Pointer to a TSC_HandleTypeDef structure that contains
00957   *         the configuration information for the specified TSC.
00958   * @retval HAL state
00959   */
00960 HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef *htsc)
00961 {
00962   /* Check the parameters */
00963   assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
00964
00965   if (htsc->State == HAL_TSC_STATE_BUSY)
00966   {
00967     /* Check end of acquisition flag */
00968     if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_EOA) != RESET)
00969     {
00970       /* Check max count error flag */
00971       if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_MCE) != RESET)
00972       {
00973         /* Change TSC state */
00974         htsc->State = HAL_TSC_STATE_ERROR;
00975       }
00976       else
00977       {
00978         /* Change TSC state */
00979         htsc->State = HAL_TSC_STATE_READY;
00980       }
00981     }
00982   }
00983
00984   /* Return TSC state */
00985   return htsc->State;
00986 }
00987
00988 /**
00989   * @}
00990   */
00991
00992 /** @defgroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
00993  * @{
00994  */
00995
00996 /**
00997   * @brief  Handle TSC interrupt request.
00998   * @param  htsc Pointer to a TSC_HandleTypeDef structure that contains
00999   *         the configuration information for the specified TSC.
01000   * @retval None
01001   */
01002 void HAL_TSC_IRQHandler(TSC_HandleTypeDef *htsc)
01003 {
01004   /* Check the parameters */
01005   assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
01006
01007   /* Check if the end of acquisition occurred */
01008   if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_EOA) != RESET)
01009   {
01010     /* Clear EOA flag */
01011     __HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_EOA);
01012   }
01013
01014   /* Check if max count error occurred */
01015   if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_MCE) != RESET)
01016   {
01017     /* Clear MCE flag */
01018     __HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_MCE);
01019     /* Change TSC state */
01020     htsc->State = HAL_TSC_STATE_ERROR;
01021 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
01022     htsc->ErrorCallback(htsc);
01023 #else
01024     /* Conversion completed callback */
01025     HAL_TSC_ErrorCallback(htsc);
01026 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
01027   }
01028   else
01029   {
01030     /* Change TSC state */
01031     htsc->State = HAL_TSC_STATE_READY;
01032 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
01033     htsc->ConvCpltCallback(htsc);
01034 #else
01035     /* Conversion completed callback */
01036     HAL_TSC_ConvCpltCallback(htsc);
01037 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
01038   }
01039 }
01040
01041 /**
01042   * @brief  Acquisition completed callback in non-blocking mode.
01043   * @param  htsc Pointer to a TSC_HandleTypeDef structure that contains
01044   *         the configuration information for the specified TSC.
01045   * @retval None
01046   */
01047 __weak void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef *htsc)
01048 {
01049   /* Prevent unused argument(s) compilation warning */
01050   UNUSED(htsc);
01051
01052   /* NOTE : This function should not be modified, when the callback is needed,
01053             the HAL_TSC_ConvCpltCallback could be implemented in the user file.
01054    */
01055 }
01056
01057 /**
01058   * @brief  Error callback in non-blocking mode.
01059   * @param  htsc Pointer to a TSC_HandleTypeDef structure that contains
01060   *         the configuration information for the specified TSC.
01061   * @retval None
01062   */
01063 __weak void HAL_TSC_ErrorCallback(TSC_HandleTypeDef *htsc)
01064 {
01065   /* Prevent unused argument(s) compilation warning */
01066   UNUSED(htsc);
01067
01068   /* NOTE : This function should not be modified, when the callback is needed,
01069             the HAL_TSC_ErrorCallback could be implemented in the user file.
01070    */
01071 }
01072
01073 /**
01074   * @}
01075   */
01076
01077 /**
01078   * @}
01079   */
01080
01081 /* Private functions ---------------------------------------------------------*/
01082 /** @defgroup TSC_Private_Functions TSC Private Functions
01083   * @{
01084   */
01085
01086 /**
01087   * @brief  Utility function used to set the acquired groups mask.
01088   * @param  iomask Channels IOs mask
01089   * @retval Acquired groups mask
01090   */
01091 static uint32_t TSC_extract_groups(uint32_t iomask)
01092 {
01093   uint32_t groups = 0UL;
01094   uint32_t idx;
01095
01096   for (idx = 0UL; idx < (uint32_t)TSC_NB_OF_GROUPS; idx++)
01097   {
01098     if ((iomask & (0x0FUL << (idx * 4UL))) != 0UL )
01099     {
01100       groups |= (1UL << idx);
01101     }
01102   }
01103
01104   return groups;
01105 }
01106
01107 /**
01108   * @}
01109   */
01110
01111 #endif /* HAL_TSC_MODULE_ENABLED */
01112
01113 /**
01114   * @}
01115   */
01116
01117 /**
01118   * @}
01119   */
01120
01121 #endif /* TSC */
01122 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:35 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_tsc.h Source File

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stm32wbxx_hal_tsc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_tsc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of TSC HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_TSC_H
00022 #define STM32WBxx_HAL_TSC_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 #if defined(TSC)
00032
00033 /** @addtogroup STM32WBxx_HAL_Driver
00034   * @{
00035   */
00036
00037 /** @addtogroup TSC
00038   * @{
00039   */
00040
00041 /* Exported types ------------------------------------------------------------*/
00042 /** @defgroup TSC_Exported_Types TSC Exported Types
00043   * @{
00044   */
00045
00046 /**
00047   * @brief TSC state structure definition
00048   */
00049 typedef enum
00050 {
00051   HAL_TSC_STATE_RESET  = 0x00UL, /*!< TSC registers have their reset value */
00052   HAL_TSC_STATE_READY  = 0x01UL, /*!< TSC registers are initialized or acquisition is completed with success */
00053   HAL_TSC_STATE_BUSY   = 0x02UL, /*!< TSC initialization or acquisition is on-going */
00054   HAL_TSC_STATE_ERROR  = 0x03UL  /*!< Acquisition is completed with max count error */
00055 } HAL_TSC_StateTypeDef;
00056
00057 /**
00058   * @brief TSC group status structure definition
00059   */
00060 typedef enum
00061 {
00062   TSC_GROUP_ONGOING   = 0x00UL, /*!< Acquisition on group is on-going or not started */
00063   TSC_GROUP_COMPLETED = 0x01UL /*!< Acquisition on group is completed with success (no max count error) */
00064 } TSC_GroupStatusTypeDef;
00065
00066 /**
00067   * @brief TSC init structure definition
00068   */
00069 typedef struct
00070 {
00071   uint32_t CTPulseHighLength;       /*!< Charge-transfer high pulse length
00072                                          This parameter can be a value of @ref TSC_CTPulseHL_Config  */
00073   uint32_t CTPulseLowLength;        /*!< Charge-transfer low pulse length
00074                                          This parameter can be a value of @ref TSC_CTPulseLL_Config  */
00075   FunctionalState SpreadSpectrum;   /*!< Spread spectrum activation
00076                                          This parameter can be set to ENABLE or DISABLE. */
00077   uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation
00078                                          This parameter must be a number between Min_Data = 0 and Max_Data = 127 */
00079   uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler
00080                                          This parameter can be a value of @ref TSC_SpreadSpec_Prescaler */
00081   uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler
00082                                          This parameter can be a value of @ref TSC_PulseGenerator_Prescaler */
00083   uint32_t MaxCountValue;           /*!< Max count value
00084                                          This parameter can be a value of @ref TSC_MaxCount_Value  */
00085   uint32_t IODefaultMode;           /*!< IO default mode
00086                                          This parameter can be a value of @ref TSC_IO_Default_Mode  */
00087   uint32_t SynchroPinPolarity;      /*!< Synchro pin polarity
00088                                          This parameter can be a value of @ref TSC_Synchro_Pin_Polarity */
00089   uint32_t AcquisitionMode;         /*!< Acquisition mode
00090                                          This parameter can be a value of @ref TSC_Acquisition_Mode  */
00091   FunctionalState MaxCountInterrupt;/*!< Max count interrupt activation
00092                                          This parameter can be set to ENABLE or DISABLE. */
00093   uint32_t ChannelIOs;              /*!< Channel IOs mask */
00094   uint32_t ShieldIOs;               /*!< Shield IOs mask */
00095   uint32_t SamplingIOs;             /*!< Sampling IOs mask */
00096 } TSC_InitTypeDef;
00097
00098 /**
00099   * @brief TSC IOs configuration structure definition
00100   */
00101 typedef struct
00102 {
00103   uint32_t ChannelIOs;  /*!< Channel IOs mask */
00104   uint32_t ShieldIOs;   /*!< Shield IOs mask */
00105   uint32_t SamplingIOs; /*!< Sampling IOs mask */
00106 } TSC_IOConfigTypeDef;
00107
00108 /**
00109   * @brief  TSC handle Structure definition
00110   */
00111 typedef struct __TSC_HandleTypeDef
00112 {
00113   TSC_TypeDef               *Instance;  /*!< Register base address      */
00114   TSC_InitTypeDef           Init;       /*!< Initialization parameters  */
00115   __IO HAL_TSC_StateTypeDef State;      /*!< Peripheral state           */
00116   HAL_LockTypeDef           Lock;       /*!< Lock feature               */
00117   __IO uint32_t             ErrorCode;  /*!< I2C Error code             */
00118
00119 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
00120   void (* ConvCpltCallback)(struct __TSC_HandleTypeDef *htsc);   /*!< TSC Conversion complete callback  */
00121   void (* ErrorCallback)(struct __TSC_HandleTypeDef *htsc);      /*!< TSC Error callback                */
00122
00123   void (* MspInitCallback)(struct __TSC_HandleTypeDef *htsc);    /*!< TSC Msp Init callback             */
00124   void (* MspDeInitCallback)(struct __TSC_HandleTypeDef *htsc);  /*!< TSC Msp DeInit callback           */
00125
00126 #endif  /* USE_HAL_TSC_REGISTER_CALLBACKS */
00127 } TSC_HandleTypeDef;
00128
00129 enum
00130 {
00131   TSC_GROUP1_IDX = 0x00UL,
00132   TSC_GROUP2_IDX,
00133   TSC_GROUP3_IDX,
00134   TSC_GROUP4_IDX,
00135   TSC_GROUP5_IDX,
00136   TSC_GROUP6_IDX,
00137   TSC_GROUP7_IDX,
00138   TSC_NB_OF_GROUPS
00139 };
00140
00141 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
00142 /**
00143   * @brief  HAL TSC Callback ID enumeration definition
00144   */
00145 typedef enum
00146 {
00147   HAL_TSC_CONV_COMPLETE_CB_ID           = 0x00UL,  /*!< TSC Conversion completed callback ID  */
00148   HAL_TSC_ERROR_CB_ID                   = 0x01UL,  /*!< TSC Error callback ID                 */
00149
00150   HAL_TSC_MSPINIT_CB_ID                 = 0x02UL,  /*!< TSC Msp Init callback ID              */
00151   HAL_TSC_MSPDEINIT_CB_ID               = 0x03UL   /*!< TSC Msp DeInit callback ID            */
00152
00153 } HAL_TSC_CallbackIDTypeDef;
00154
00155 /**
00156   * @brief  HAL TSC Callback pointer definition
00157   */
00158 typedef  void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to an TSC callback function */
00159
00160 #endif  /* USE_HAL_TSC_REGISTER_CALLBACKS */
00161
00162 /**
00163   * @}
00164   */
00165
00166 /* Exported constants --------------------------------------------------------*/
00167 /** @defgroup TSC_Exported_Constants TSC Exported Constants
00168   * @{
00169   */
00170
00171 /** @defgroup TSC_Error_Code_definition TSC Error Code definition
00172   * @brief  TSC Error Code definition
00173   * @{
00174   */
00175 #define HAL_TSC_ERROR_NONE      0x00000000UL    /*!< No error              */
00176 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
00177 #define HAL_TSC_ERROR_INVALID_CALLBACK  0x00000001UL    /*!< Invalid Callback error */
00178 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
00179 /**
00180   * @}
00181   */
00182
00183 /** @defgroup TSC_CTPulseHL_Config CTPulse High Length
00184   * @{
00185   */
00186 #define TSC_CTPH_1CYCLE         0x00000000UL                                                    /*!< Charge transfer pulse high during 1 cycle (PGCLK)   */
00187 #define TSC_CTPH_2CYCLES        TSC_CR_CTPH_0                                                   /*!< Charge transfer pulse high during 2 cycles (PGCLK)  */
00188 #define TSC_CTPH_3CYCLES        TSC_CR_CTPH_1                                                   /*!< Charge transfer pulse high during 3 cycles (PGCLK)  */
00189 #define TSC_CTPH_4CYCLES        (TSC_CR_CTPH_1 | TSC_CR_CTPH_0)                                 /*!< Charge transfer pulse high during 4 cycles (PGCLK)  */
00190 #define TSC_CTPH_5CYCLES        TSC_CR_CTPH_2                                                   /*!< Charge transfer pulse high during 5 cycles (PGCLK)  */
00191 #define TSC_CTPH_6CYCLES        (TSC_CR_CTPH_2 | TSC_CR_CTPH_0)                                 /*!< Charge transfer pulse high during 6 cycles (PGCLK)  */
00192 #define TSC_CTPH_7CYCLES        (TSC_CR_CTPH_2 | TSC_CR_CTPH_1)                                 /*!< Charge transfer pulse high during 7 cycles (PGCLK)  */
00193 #define TSC_CTPH_8CYCLES        (TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0)                 /*!< Charge transfer pulse high during 8 cycles (PGCLK)  */
00194 #define TSC_CTPH_9CYCLES        TSC_CR_CTPH_3                                                   /*!< Charge transfer pulse high during 9 cycles (PGCLK)  */
00195 #define TSC_CTPH_10CYCLES       (TSC_CR_CTPH_3 | TSC_CR_CTPH_0)                                 /*!< Charge transfer pulse high during 10 cycles (PGCLK) */
00196 #define TSC_CTPH_11CYCLES       (TSC_CR_CTPH_3 | TSC_CR_CTPH_1)                                 /*!< Charge transfer pulse high during 11 cycles (PGCLK) */
00197 #define TSC_CTPH_12CYCLES       (TSC_CR_CTPH_3 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0)                 /*!< Charge transfer pulse high during 12 cycles (PGCLK) */
00198 #define TSC_CTPH_13CYCLES       (TSC_CR_CTPH_3 | TSC_CR_CTPH_2)                                 /*!< Charge transfer pulse high during 13 cycles (PGCLK) */
00199 #define TSC_CTPH_14CYCLES       (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_0)                 /*!< Charge transfer pulse high during 14 cycles (PGCLK) */
00200 #define TSC_CTPH_15CYCLES       (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1)                 /*!< Charge transfer pulse high during 15 cycles (PGCLK) */
00201 #define TSC_CTPH_16CYCLES       (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 16 cycles (PGCLK) */
00202 /**
00203   * @}
00204   */
00205
00206 /** @defgroup TSC_CTPulseLL_Config CTPulse Low Length
00207   * @{
00208   */
00209 #define TSC_CTPL_1CYCLE         0x00000000UL                                                     /*!< Charge transfer pulse low during 1 cycle (PGCLK)   */
00210 #define TSC_CTPL_2CYCLES        TSC_CR_CTPL_0                                                    /*!< Charge transfer pulse low during 2 cycles (PGCLK)  */
00211 #define TSC_CTPL_3CYCLES        TSC_CR_CTPL_1                                                    /*!< Charge transfer pulse low during 3 cycles (PGCLK)  */
00212 #define TSC_CTPL_4CYCLES        (TSC_CR_CTPL_1 | TSC_CR_CTPL_0)                                  /*!< Charge transfer pulse low during 4 cycles (PGCLK)  */
00213 #define TSC_CTPL_5CYCLES        TSC_CR_CTPL_2                                                    /*!< Charge transfer pulse low during 5 cycles (PGCLK)  */
00214 #define TSC_CTPL_6CYCLES        (TSC_CR_CTPL_2 | TSC_CR_CTPL_0)                                  /*!< Charge transfer pulse low during 6 cycles (PGCLK)  */
00215 #define TSC_CTPL_7CYCLES        (TSC_CR_CTPL_2 | TSC_CR_CTPL_1)                                  /*!< Charge transfer pulse low during 7 cycles (PGCLK)  */
00216 #define TSC_CTPL_8CYCLES        (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0)                  /*!< Charge transfer pulse low during 8 cycles (PGCLK)  */
00217 #define TSC_CTPL_9CYCLES        TSC_CR_CTPL_3                                                    /*!< Charge transfer pulse low during 9 cycles (PGCLK)  */
00218 #define TSC_CTPL_10CYCLES       (TSC_CR_CTPL_3 | TSC_CR_CTPL_0)                                  /*!< Charge transfer pulse low during 10 cycles (PGCLK) */
00219 #define TSC_CTPL_11CYCLES       (TSC_CR_CTPL_3 | TSC_CR_CTPL_1)                                  /*!< Charge transfer pulse low during 11 cycles (PGCLK) */
00220 #define TSC_CTPL_12CYCLES       (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0)                  /*!< Charge transfer pulse low during 12 cycles (PGCLK) */
00221 #define TSC_CTPL_13CYCLES       (TSC_CR_CTPL_3 | TSC_CR_CTPL_2)                                  /*!< Charge transfer pulse low during 13 cycles (PGCLK) */
00222 #define TSC_CTPL_14CYCLES       (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0)                  /*!< Charge transfer pulse low during 14 cycles (PGCLK) */
00223 #define TSC_CTPL_15CYCLES       (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1)                  /*!< Charge transfer pulse low during 15 cycles (PGCLK) */
00224 #define TSC_CTPL_16CYCLES       (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0)  /*!< Charge transfer pulse low during 16 cycles (PGCLK) */
00225 /**
00226   * @}
00227   */
00228
00229 /** @defgroup TSC_SpreadSpec_Prescaler Spread Spectrum Prescaler
00230   * @{
00231   */
00232 #define TSC_SS_PRESC_DIV1       0x00000000UL  /*!< Spread Spectrum Prescaler Div1 */
00233 #define TSC_SS_PRESC_DIV2       TSC_CR_SSPSC  /*!< Spread Spectrum Prescaler Div2 */
00234 /**
00235   * @}
00236   */
00237
00238 /** @defgroup TSC_PulseGenerator_Prescaler Pulse Generator Prescaler
00239   * @{
00240   */
00241 #define TSC_PG_PRESC_DIV1       0x00000000UL                                        /*!< Pulse Generator HCLK Div1   */
00242 #define TSC_PG_PRESC_DIV2       TSC_CR_PGPSC_0                                      /*!< Pulse Generator HCLK Div2   */
00243 #define TSC_PG_PRESC_DIV4       TSC_CR_PGPSC_1                                      /*!< Pulse Generator HCLK Div4   */
00244 #define TSC_PG_PRESC_DIV8       (TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0)                   /*!< Pulse Generator HCLK Div8   */
00245 #define TSC_PG_PRESC_DIV16      TSC_CR_PGPSC_2                                      /*!< Pulse Generator HCLK Div16  */
00246 #define TSC_PG_PRESC_DIV32      (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_0)                   /*!< Pulse Generator HCLK Div32  */
00247 #define TSC_PG_PRESC_DIV64      (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1)                   /*!< Pulse Generator HCLK Div64  */
00248 #define TSC_PG_PRESC_DIV128     (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0)  /*!< Pulse Generator HCLK Div128 */
00249 /**
00250   * @}
00251   */
00252
00253 /** @defgroup TSC_MaxCount_Value Max Count Value
00254   * @{
00255   */
00256 #define TSC_MCV_255             0x00000000UL                   /*!< 255 maximum number of charge transfer pulses   */
00257 #define TSC_MCV_511             TSC_CR_MCV_0                   /*!< 511 maximum number of charge transfer pulses   */
00258 #define TSC_MCV_1023            TSC_CR_MCV_1                   /*!< 1023 maximum number of charge transfer pulses  */
00259 #define TSC_MCV_2047            (TSC_CR_MCV_1 | TSC_CR_MCV_0)  /*!< 2047 maximum number of charge transfer pulses  */
00260 #define TSC_MCV_4095            TSC_CR_MCV_2                   /*!< 4095 maximum number of charge transfer pulses  */
00261 #define TSC_MCV_8191            (TSC_CR_MCV_2 | TSC_CR_MCV_0)  /*!< 8191 maximum number of charge transfer pulses  */
00262 #define TSC_MCV_16383           (TSC_CR_MCV_2 | TSC_CR_MCV_1)  /*!< 16383 maximum number of charge transfer pulses */
00263 /**
00264   * @}
00265   */
00266
00267 /** @defgroup TSC_IO_Default_Mode IO Default Mode
00268   * @{
00269   */
00270 #define TSC_IODEF_OUT_PP_LOW    0x00000000UL /*!< I/Os are forced to output push-pull low */
00271 #define TSC_IODEF_IN_FLOAT      TSC_CR_IODEF /*!< I/Os are in input floating              */
00272 /**
00273   * @}
00274   */
00275
00276 /** @defgroup TSC_Synchro_Pin_Polarity Synchro Pin Polarity
00277   * @{
00278   */
00279 #define TSC_SYNC_POLARITY_FALLING  0x00000000UL   /*!< Falling edge only           */
00280 #define TSC_SYNC_POLARITY_RISING   TSC_CR_SYNCPOL /*!< Rising edge and high level  */
00281 /**
00282   * @}
00283   */
00284
00285 /** @defgroup TSC_Acquisition_Mode Acquisition Mode
00286   * @{
00287   */
00288 #define TSC_ACQ_MODE_NORMAL     0x00000000UL  /*!< Normal acquisition mode (acquisition starts as soon as START bit is set)                                                              */
00289 #define TSC_ACQ_MODE_SYNCHRO    TSC_CR_AM     /*!< Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin) */
00290 /**
00291   * @}
00292   */
00293
00294 /** @defgroup TSC_interrupts_definition Interrupts definition
00295   * @{
00296   */
00297 #define TSC_IT_EOA              TSC_IER_EOAIE /*!< End of acquisition interrupt enable */
00298 #define TSC_IT_MCE              TSC_IER_MCEIE /*!< Max count error interrupt enable    */
00299 /**
00300   * @}
00301   */
00302
00303 /** @defgroup TSC_flags_definition Flags definition
00304   * @{
00305   */
00306 #define TSC_FLAG_EOA            TSC_ISR_EOAF /*!< End of acquisition flag */
00307 #define TSC_FLAG_MCE            TSC_ISR_MCEF /*!< Max count error flag    */
00308 /**
00309   * @}
00310   */
00311
00312 /** @defgroup TSC_Group_definition Group definition
00313   * @{
00314   */
00315 #define TSC_GROUP1              (0x1UL << TSC_GROUP1_IDX)
00316 #define TSC_GROUP2              (0x1UL << TSC_GROUP2_IDX)
00317 #define TSC_GROUP3              (0x1UL << TSC_GROUP3_IDX)
00318 #define TSC_GROUP4              (0x1UL << TSC_GROUP4_IDX)
00319 #define TSC_GROUP5              (0x1UL << TSC_GROUP5_IDX)
00320 #define TSC_GROUP6              (0x1UL << TSC_GROUP6_IDX)
00321 #define TSC_GROUP7              (0x1UL << TSC_GROUP7_IDX)
00322
00323 #define TSC_GROUP1_IO1          TSC_IOCCR_G1_IO1 /*!< TSC Group1 IO1 */
00324 #define TSC_GROUP1_IO2          TSC_IOCCR_G1_IO2 /*!< TSC Group1 IO2 */
00325 #define TSC_GROUP1_IO3          TSC_IOCCR_G1_IO3 /*!< TSC Group1 IO3 */
00326 #define TSC_GROUP1_IO4          TSC_IOCCR_G1_IO4 /*!< TSC Group1 IO4 */
00327
00328 #define TSC_GROUP2_IO1          TSC_IOCCR_G2_IO1 /*!< TSC Group2 IO1 */
00329 #define TSC_GROUP2_IO2          TSC_IOCCR_G2_IO2 /*!< TSC Group2 IO2 */
00330 #define TSC_GROUP2_IO3          TSC_IOCCR_G2_IO3 /*!< TSC Group2 IO3 */
00331 #define TSC_GROUP2_IO4          TSC_IOCCR_G2_IO4 /*!< TSC Group2 IO4 */
00332
00333 #define TSC_GROUP3_IO1          TSC_IOCCR_G3_IO1 /*!< TSC Group3 IO1 */
00334 #define TSC_GROUP3_IO2          TSC_IOCCR_G3_IO2 /*!< TSC Group3 IO2 */
00335 #define TSC_GROUP3_IO3          TSC_IOCCR_G3_IO3 /*!< TSC Group3 IO3 */
00336 #define TSC_GROUP3_IO4          TSC_IOCCR_G3_IO4 /*!< TSC Group3 IO4 */
00337
00338 #define TSC_GROUP4_IO1          TSC_IOCCR_G4_IO1 /*!< TSC Group4 IO1 */
00339 #define TSC_GROUP4_IO2          TSC_IOCCR_G4_IO2 /*!< TSC Group4 IO2 */
00340 #define TSC_GROUP4_IO3          TSC_IOCCR_G4_IO3 /*!< TSC Group4 IO3 */
00341 #define TSC_GROUP4_IO4          TSC_IOCCR_G4_IO4 /*!< TSC Group4 IO4 */
00342
00343 #define TSC_GROUP5_IO1          TSC_IOCCR_G5_IO1 /*!< TSC Group5 IO1 */
00344 #define TSC_GROUP5_IO2          TSC_IOCCR_G5_IO2 /*!< TSC Group5 IO2 */
00345 #define TSC_GROUP5_IO3          TSC_IOCCR_G5_IO3 /*!< TSC Group5 IO3 */
00346 #define TSC_GROUP5_IO4          TSC_IOCCR_G5_IO4 /*!< TSC Group5 IO4 */
00347
00348 #define TSC_GROUP6_IO1          TSC_IOCCR_G6_IO1 /*!< TSC Group6 IO1 */
00349 #define TSC_GROUP6_IO2          TSC_IOCCR_G6_IO2 /*!< TSC Group6 IO2 */
00350 #define TSC_GROUP6_IO3          TSC_IOCCR_G6_IO3 /*!< TSC Group6 IO3 */
00351 #define TSC_GROUP6_IO4          TSC_IOCCR_G6_IO4 /*!< TSC Group6 IO4 */
00352
00353 #define TSC_GROUP7_IO1          TSC_IOCCR_G7_IO1 /*!< TSC Group7 IO1 */
00354 #define TSC_GROUP7_IO2          TSC_IOCCR_G7_IO2 /*!< TSC Group7 IO2 */
00355 #define TSC_GROUP7_IO3          TSC_IOCCR_G7_IO3 /*!< TSC Group7 IO3 */
00356 #define TSC_GROUP7_IO4          TSC_IOCCR_G7_IO4 /*!< TSC Group7 IO4 */
00357 /**
00358   * @}
00359   */
00360
00361 /**
00362   * @}
00363   */
00364
00365 /* Exported macros -----------------------------------------------------------*/
00366
00367 /** @defgroup TSC_Exported_Macros TSC Exported Macros
00368   * @{
00369   */
00370
00371 /** @brief Reset TSC handle state.
00372   * @param  __HANDLE__ TSC handle
00373   * @retval None
00374   */
00375 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
00376 #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__)                   do{                                                   \
00377                                                                        (__HANDLE__)->State = HAL_TSC_STATE_RESET;       \
00378                                                                        (__HANDLE__)->MspInitCallback = NULL;            \
00379                                                                        (__HANDLE__)->MspDeInitCallback = NULL;          \
00380                                                                      } while(0)
00381 #else
00382 #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__)                   ((__HANDLE__)->State = HAL_TSC_STATE_RESET)
00383 #endif
00384
00385 /**
00386   * @brief Enable the TSC peripheral.
00387   * @param  __HANDLE__ TSC handle
00388   * @retval None
00389   */
00390 #define __HAL_TSC_ENABLE(__HANDLE__)                               ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE)
00391
00392 /**
00393   * @brief Disable the TSC peripheral.
00394   * @param  __HANDLE__ TSC handle
00395   * @retval None
00396   */
00397 #define __HAL_TSC_DISABLE(__HANDLE__)                              ((__HANDLE__)->Instance->CR &= (~TSC_CR_TSCE))
00398
00399 /**
00400   * @brief Start acquisition.
00401   * @param  __HANDLE__ TSC handle
00402   * @retval None
00403   */
00404 #define __HAL_TSC_START_ACQ(__HANDLE__)                            ((__HANDLE__)->Instance->CR |= TSC_CR_START)
00405
00406 /**
00407   * @brief Stop acquisition.
00408   * @param  __HANDLE__ TSC handle
00409   * @retval None
00410   */
00411 #define __HAL_TSC_STOP_ACQ(__HANDLE__)                             ((__HANDLE__)->Instance->CR &= (~TSC_CR_START))
00412
00413 /**
00414   * @brief Set IO default mode to output push-pull low.
00415   * @param  __HANDLE__ TSC handle
00416   * @retval None
00417   */
00418 #define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__)                   ((__HANDLE__)->Instance->CR &= (~TSC_CR_IODEF))
00419
00420 /**
00421   * @brief Set IO default mode to input floating.
00422   * @param  __HANDLE__ TSC handle
00423   * @retval None
00424   */
00425 #define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__)                    ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF)
00426
00427 /**
00428   * @brief Set synchronization polarity to falling edge.
00429   * @param  __HANDLE__ TSC handle
00430   * @retval None
00431   */
00432 #define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__)                    ((__HANDLE__)->Instance->CR &= (~TSC_CR_SYNCPOL))
00433
00434 /**
00435   * @brief Set synchronization polarity to rising edge and high level.
00436   * @param  __HANDLE__ TSC handle
00437   * @retval None
00438   */
00439 #define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__)               ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL)
00440
00441 /**
00442   * @brief Enable TSC interrupt.
00443   * @param  __HANDLE__ TSC handle
00444   * @param  __INTERRUPT__ TSC interrupt
00445   * @retval None
00446   */
00447 #define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__)             ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
00448
00449 /**
00450   * @brief Disable TSC interrupt.
00451   * @param  __HANDLE__ TSC handle
00452   * @param  __INTERRUPT__ TSC interrupt
00453   * @retval None
00454   */
00455 #define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__)            ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
00456
00457 /** @brief Check whether the specified TSC interrupt source is enabled or not.
00458   * @param  __HANDLE__ TSC Handle
00459   * @param  __INTERRUPT__ TSC interrupt
00460   * @retval SET or RESET
00461   */
00462 #define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)         ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00463
00464 /**
00465   * @brief Check whether the specified TSC flag is set or not.
00466   * @param  __HANDLE__ TSC handle
00467   * @param  __FLAG__ TSC flag
00468   * @retval SET or RESET
00469   */
00470 #define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__)                   ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
00471
00472 /**
00473   * @brief Clear the TSC's pending flag.
00474   * @param  __HANDLE__ TSC handle
00475   * @param  __FLAG__ TSC flag
00476   * @retval None
00477   */
00478 #define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__)                 ((__HANDLE__)->Instance->ICR = (__FLAG__))
00479
00480 /**
00481   * @brief Enable schmitt trigger hysteresis on a group of IOs.
00482   * @param  __HANDLE__ TSC handle
00483   * @param  __GX_IOY_MASK__ IOs mask
00484   * @retval None
00485   */
00486 #define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__)   ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__))
00487
00488 /**
00489   * @brief Disable schmitt trigger hysteresis on a group of IOs.
00490   * @param  __HANDLE__ TSC handle
00491   * @param  __GX_IOY_MASK__ IOs mask
00492   * @retval None
00493   */
00494 #define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__)  ((__HANDLE__)->Instance->IOHCR &= (~(__GX_IOY_MASK__)))
00495
00496 /**
00497   * @brief Open analog switch on a group of IOs.
00498   * @param  __HANDLE__ TSC handle
00499   * @param  __GX_IOY_MASK__ IOs mask
00500   * @retval None
00501   */
00502 #define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__)  ((__HANDLE__)->Instance->IOASCR &= (~(__GX_IOY_MASK__)))
00503
00504 /**
00505   * @brief Close analog switch on a group of IOs.
00506   * @param  __HANDLE__ TSC handle
00507   * @param  __GX_IOY_MASK__ IOs mask
00508   * @retval None
00509   */
00510 #define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__))
00511
00512 /**
00513   * @brief Enable a group of IOs in channel mode.
00514   * @param  __HANDLE__ TSC handle
00515   * @param  __GX_IOY_MASK__ IOs mask
00516   * @retval None
00517   */
00518 #define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__)      ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__))
00519
00520 /**
00521   * @brief Disable a group of channel IOs.
00522   * @param  __HANDLE__ TSC handle
00523   * @param  __GX_IOY_MASK__ IOs mask
00524   * @retval None
00525   */
00526 #define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__)     ((__HANDLE__)->Instance->IOCCR &= (~(__GX_IOY_MASK__)))
00527
00528 /**
00529   * @brief Enable a group of IOs in sampling mode.
00530   * @param  __HANDLE__ TSC handle
00531   * @param  __GX_IOY_MASK__ IOs mask
00532   * @retval None
00533   */
00534 #define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__)     ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__))
00535
00536 /**
00537   * @brief Disable a group of sampling IOs.
00538   * @param  __HANDLE__ TSC handle
00539   * @param  __GX_IOY_MASK__ IOs mask
00540   * @retval None
00541   */
00542 #define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (~(__GX_IOY_MASK__)))
00543
00544 /**
00545   * @brief Enable acquisition groups.
00546   * @param  __HANDLE__ TSC handle
00547   * @param  __GX_MASK__ Groups mask
00548   * @retval None
00549   */
00550 #define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__))
00551
00552 /**
00553   * @brief Disable acquisition groups.
00554   * @param  __HANDLE__ TSC handle
00555   * @param  __GX_MASK__ Groups mask
00556   * @retval None
00557   */
00558 #define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (~(__GX_MASK__)))
00559
00560 /** @brief Gets acquisition group status.
00561   * @param  __HANDLE__ TSC Handle
00562   * @param  __GX_INDEX__ Group index
00563   * @retval SET or RESET
00564   */
00565 #define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \
00566 ((((__HANDLE__)->Instance->IOGCSR & (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) == (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING)
00567
00568 /**
00569   * @}
00570   */
00571
00572 /* Private macros ------------------------------------------------------------*/
00573
00574 /** @defgroup TSC_Private_Macros TSC Private Macros
00575   * @{
00576   */
00577
00578 #define IS_TSC_CTPH(__VALUE__)          (((__VALUE__) == TSC_CTPH_1CYCLE)   || \
00579                                          ((__VALUE__) == TSC_CTPH_2CYCLES)  || \
00580                                          ((__VALUE__) == TSC_CTPH_3CYCLES)  || \
00581                                          ((__VALUE__) == TSC_CTPH_4CYCLES)  || \
00582                                          ((__VALUE__) == TSC_CTPH_5CYCLES)  || \
00583                                          ((__VALUE__) == TSC_CTPH_6CYCLES)  || \
00584                                          ((__VALUE__) == TSC_CTPH_7CYCLES)  || \
00585                                          ((__VALUE__) == TSC_CTPH_8CYCLES)  || \
00586                                          ((__VALUE__) == TSC_CTPH_9CYCLES)  || \
00587                                          ((__VALUE__) == TSC_CTPH_10CYCLES) || \
00588                                          ((__VALUE__) == TSC_CTPH_11CYCLES) || \
00589                                          ((__VALUE__) == TSC_CTPH_12CYCLES) || \
00590                                          ((__VALUE__) == TSC_CTPH_13CYCLES) || \
00591                                          ((__VALUE__) == TSC_CTPH_14CYCLES) || \
00592                                          ((__VALUE__) == TSC_CTPH_15CYCLES) || \
00593                                          ((__VALUE__) == TSC_CTPH_16CYCLES))
00594
00595 #define IS_TSC_CTPL(__VALUE__)          (((__VALUE__) == TSC_CTPL_1CYCLE)   || \
00596                                          ((__VALUE__) == TSC_CTPL_2CYCLES)  || \
00597                                          ((__VALUE__) == TSC_CTPL_3CYCLES)  || \
00598                                          ((__VALUE__) == TSC_CTPL_4CYCLES)  || \
00599                                          ((__VALUE__) == TSC_CTPL_5CYCLES)  || \
00600                                          ((__VALUE__) == TSC_CTPL_6CYCLES)  || \
00601                                          ((__VALUE__) == TSC_CTPL_7CYCLES)  || \
00602                                          ((__VALUE__) == TSC_CTPL_8CYCLES)  || \
00603                                          ((__VALUE__) == TSC_CTPL_9CYCLES)  || \
00604                                          ((__VALUE__) == TSC_CTPL_10CYCLES) || \
00605                                          ((__VALUE__) == TSC_CTPL_11CYCLES) || \
00606                                          ((__VALUE__) == TSC_CTPL_12CYCLES) || \
00607                                          ((__VALUE__) == TSC_CTPL_13CYCLES) || \
00608                                          ((__VALUE__) == TSC_CTPL_14CYCLES) || \
00609                                          ((__VALUE__) == TSC_CTPL_15CYCLES) || \
00610                                          ((__VALUE__) == TSC_CTPL_16CYCLES))
00611
00612 #define IS_TSC_SS(__VALUE__)            (((FunctionalState)(__VALUE__) == DISABLE) || ((FunctionalState)(__VALUE__) == ENABLE))
00613
00614 #define IS_TSC_SSD(__VALUE__)           (((__VALUE__) == 0UL) || (((__VALUE__) > 0UL) && ((__VALUE__) < 128UL)))
00615
00616 #define IS_TSC_SS_PRESC(__VALUE__)      (((__VALUE__) == TSC_SS_PRESC_DIV1) || ((__VALUE__) == TSC_SS_PRESC_DIV2))
00617
00618 #define IS_TSC_PG_PRESC(__VALUE__)      (((__VALUE__) == TSC_PG_PRESC_DIV1)  || \
00619                                          ((__VALUE__) == TSC_PG_PRESC_DIV2)  || \
00620                                          ((__VALUE__) == TSC_PG_PRESC_DIV4)  || \
00621                                          ((__VALUE__) == TSC_PG_PRESC_DIV8)  || \
00622                                          ((__VALUE__) == TSC_PG_PRESC_DIV16) || \
00623                                          ((__VALUE__) == TSC_PG_PRESC_DIV32) || \
00624                                          ((__VALUE__) == TSC_PG_PRESC_DIV64) || \
00625                                          ((__VALUE__) == TSC_PG_PRESC_DIV128))
00626
00627 #define IS_TSC_MCV(__VALUE__)           (((__VALUE__) == TSC_MCV_255)  || \
00628                                          ((__VALUE__) == TSC_MCV_511)  || \
00629                                          ((__VALUE__) == TSC_MCV_1023) || \
00630                                          ((__VALUE__) == TSC_MCV_2047) || \
00631                                          ((__VALUE__) == TSC_MCV_4095) || \
00632                                          ((__VALUE__) == TSC_MCV_8191) || \
00633                                           ((__VALUE__) == TSC_MCV_16383))
00634
00635 #define IS_TSC_IODEF(__VALUE__)         (((__VALUE__) == TSC_IODEF_OUT_PP_LOW) || ((__VALUE__) == TSC_IODEF_IN_FLOAT))
00636
00637 #define IS_TSC_SYNC_POL(__VALUE__)      (((__VALUE__) == TSC_SYNC_POLARITY_FALLING) || ((__VALUE__) == TSC_SYNC_POLARITY_RISING))
00638
00639 #define IS_TSC_ACQ_MODE(__VALUE__)      (((__VALUE__) == TSC_ACQ_MODE_NORMAL) || ((__VALUE__) == TSC_ACQ_MODE_SYNCHRO))
00640
00641 #define IS_TSC_MCE_IT(__VALUE__)        (((FunctionalState)(__VALUE__) == DISABLE) || ((FunctionalState)(__VALUE__) == ENABLE))
00642
00643 #define IS_TSC_GROUP_INDEX(__VALUE__)   (((__VALUE__) == 0UL) || (((__VALUE__) > 0UL) && ((__VALUE__) < (uint32_t)TSC_NB_OF_GROUPS)))
00644
00645 #define IS_TSC_GROUP(__VALUE__)         (((__VALUE__) == 0UL)                               ||\
00646                                          (((__VALUE__) & TSC_GROUP1_IO1) == TSC_GROUP1_IO1) ||\
00647                                          (((__VALUE__) & TSC_GROUP1_IO2) == TSC_GROUP1_IO2) ||\
00648                                          (((__VALUE__) & TSC_GROUP1_IO3) == TSC_GROUP1_IO3) ||\
00649                                          (((__VALUE__) & TSC_GROUP1_IO4) == TSC_GROUP1_IO4) ||\
00650                                          (((__VALUE__) & TSC_GROUP2_IO1) == TSC_GROUP2_IO1) ||\
00651                                          (((__VALUE__) & TSC_GROUP2_IO2) == TSC_GROUP2_IO2) ||\
00652                                          (((__VALUE__) & TSC_GROUP2_IO3) == TSC_GROUP2_IO3) ||\
00653                                          (((__VALUE__) & TSC_GROUP2_IO4) == TSC_GROUP2_IO4) ||\
00654                                          (((__VALUE__) & TSC_GROUP3_IO1) == TSC_GROUP3_IO1) ||\
00655                                          (((__VALUE__) & TSC_GROUP3_IO2) == TSC_GROUP3_IO2) ||\
00656                                          (((__VALUE__) & TSC_GROUP3_IO3) == TSC_GROUP3_IO3) ||\
00657                                          (((__VALUE__) & TSC_GROUP3_IO4) == TSC_GROUP3_IO4) ||\
00658                                          (((__VALUE__) & TSC_GROUP4_IO1) == TSC_GROUP4_IO1) ||\
00659                                          (((__VALUE__) & TSC_GROUP4_IO2) == TSC_GROUP4_IO2) ||\
00660                                          (((__VALUE__) & TSC_GROUP4_IO3) == TSC_GROUP4_IO3) ||\
00661                                          (((__VALUE__) & TSC_GROUP4_IO4) == TSC_GROUP4_IO4) ||\
00662                                          (((__VALUE__) & TSC_GROUP5_IO1) == TSC_GROUP5_IO1) ||\
00663                                          (((__VALUE__) & TSC_GROUP5_IO2) == TSC_GROUP5_IO2) ||\
00664                                          (((__VALUE__) & TSC_GROUP5_IO3) == TSC_GROUP5_IO3) ||\
00665                                          (((__VALUE__) & TSC_GROUP5_IO4) == TSC_GROUP5_IO4) ||\
00666                                          (((__VALUE__) & TSC_GROUP6_IO1) == TSC_GROUP6_IO1) ||\
00667                                          (((__VALUE__) & TSC_GROUP6_IO2) == TSC_GROUP6_IO2) ||\
00668                                          (((__VALUE__) & TSC_GROUP6_IO3) == TSC_GROUP6_IO3) ||\
00669                                          (((__VALUE__) & TSC_GROUP6_IO4) == TSC_GROUP6_IO4) ||\
00670                                          (((__VALUE__) & TSC_GROUP7_IO1) == TSC_GROUP7_IO1) ||\
00671                                          (((__VALUE__) & TSC_GROUP7_IO2) == TSC_GROUP7_IO2) ||\
00672                                          (((__VALUE__) & TSC_GROUP7_IO3) == TSC_GROUP7_IO3) ||\
00673                                          (((__VALUE__) & TSC_GROUP7_IO4) == TSC_GROUP7_IO4))
00674 /**
00675   * @}
00676   */
00677
00678 /* Exported functions --------------------------------------------------------*/
00679 /** @addtogroup TSC_Exported_Functions
00680   * @{
00681   */
00682
00683 /** @addtogroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions
00684   * @{
00685   */
00686 /* Initialization and de-initialization functions *****************************/
00687 HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef *htsc);
00688 HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc);
00689 void HAL_TSC_MspInit(TSC_HandleTypeDef *htsc);
00690 void HAL_TSC_MspDeInit(TSC_HandleTypeDef *htsc);
00691
00692 /* Callbacks Register/UnRegister functions  ***********************************/
00693 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
00694 HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID, pTSC_CallbackTypeDef pCallback);
00695 HAL_StatusTypeDef HAL_TSC_UnRegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID);
00696 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
00697 /**
00698   * @}
00699   */
00700
00701 /** @addtogroup TSC_Exported_Functions_Group2 Input and Output operation functions
00702   * @{
00703   */
00704 /* IO operation functions *****************************************************/
00705 HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef *htsc);
00706 HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef *htsc);
00707 HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef *htsc);
00708 HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef *htsc);
00709 HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef *htsc);
00710 TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef *htsc, uint32_t gx_index);
00711 uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef *htsc, uint32_t gx_index);
00712 /**
00713   * @}
00714   */
00715
00716 /** @addtogroup TSC_Exported_Functions_Group3 Peripheral Control functions
00717   * @{
00718   */
00719 /* Peripheral Control functions ***********************************************/
00720 HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, TSC_IOConfigTypeDef *config);
00721 HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef *htsc, FunctionalState choice);
00722 /**
00723   * @}
00724   */
00725
00726 /** @addtogroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions
00727   * @{
00728   */
00729 /* Peripheral State and Error functions ***************************************/
00730 HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef *htsc);
00731 /**
00732   * @}
00733   */
00734
00735 /** @addtogroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
00736  * @{
00737  */
00738 /******* TSC IRQHandler and Callbacks used in Interrupt mode */
00739 void HAL_TSC_IRQHandler(TSC_HandleTypeDef *htsc);
00740 void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef *htsc);
00741 void HAL_TSC_ErrorCallback(TSC_HandleTypeDef *htsc);
00742 /**
00743   * @}
00744   */
00745
00746 /**
00747   * @}
00748   */
00749
00750 /**
00751   * @}
00752   */
00753
00754 /**
00755   * @}
00756   */
00757 #endif /* TSC */
00758
00759 #ifdef __cplusplus
00760 }
00761 #endif
00762
00763 #endif /* STM32WBxx_HAL_TSC_H */
00764
00765 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:35 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_uart.c Source File

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stm32wbxx_hal_uart.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_uart.c
00004   * @author  MCD Application Team
00005   * @brief   UART HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral Control functions
00011   *
00012   *
00013   @verbatim
00014  ===============================================================================
00015                         ##### How to use this driver #####
00016  ===============================================================================
00017   [..]
00018     The UART HAL driver can be used as follows:
00019
00020     (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
00021     (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
00022         (++) Enable the USARTx interface clock.
00023         (++) UART pins configuration:
00024             (+++) Enable the clock for the UART GPIOs.
00025             (+++) Configure these UART pins as alternate function pull-up.
00026         (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
00027              and HAL_UART_Receive_IT() APIs):
00028             (+++) Configure the USARTx interrupt priority.
00029             (+++) Enable the NVIC USART IRQ handle.
00030         (++) UART interrupts handling:
00031               -@@-  The specific UART interrupts (Transmission complete interrupt,
00032                 RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts)
00033                 are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT()
00034                 inside the transmit and receive processes.
00035         (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
00036              and HAL_UART_Receive_DMA() APIs):
00037             (+++) Declare a DMA handle structure for the Tx/Rx channel.
00038             (+++) Enable the DMAx interface clock.
00039             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00040             (+++) Configure the DMA Tx/Rx channel.
00041             (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
00042             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
00043
00044     (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value , Hardware
00045         flow control and Mode (Receiver/Transmitter) in the huart handle Init structure.
00046
00047     (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...)
00048         in the huart handle AdvancedInit structure.
00049
00050     (#) For the UART asynchronous mode, initialize the UART registers by calling
00051         the HAL_UART_Init() API.
00052
00053     (#) For the UART Half duplex mode, initialize the UART registers by calling
00054         the HAL_HalfDuplex_Init() API.
00055
00056     (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers
00057         by calling the HAL_LIN_Init() API.
00058
00059     (#) For the UART Multiprocessor mode, initialize the UART registers
00060         by calling the HAL_MultiProcessor_Init() API.
00061
00062     (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
00063         by calling the HAL_RS485Ex_Init() API.
00064
00065     [..]
00066     (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(),
00067         also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by
00068         calling the customized HAL_UART_MspInit() API.
00069
00070     ##### Callback registration #####
00071     ==================================
00072
00073     [..]
00074     The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1
00075     allows the user to configure dynamically the driver callbacks.
00076
00077     [..]
00078     Use Function @ref HAL_UART_RegisterCallback() to register a user callback.
00079     Function @ref HAL_UART_RegisterCallback() allows to register following callbacks:
00080     (+) TxHalfCpltCallback        : Tx Half Complete Callback.
00081     (+) TxCpltCallback            : Tx Complete Callback.
00082     (+) RxHalfCpltCallback        : Rx Half Complete Callback.
00083     (+) RxCpltCallback            : Rx Complete Callback.
00084     (+) ErrorCallback             : Error Callback.
00085     (+) AbortCpltCallback         : Abort Complete Callback.
00086     (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
00087     (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
00088     (+) WakeupCallback            : Wakeup Callback.
00089     (+) RxFifoFullCallback        : Rx Fifo Full Callback.
00090     (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
00091     (+) MspInitCallback           : UART MspInit.
00092     (+) MspDeInitCallback         : UART MspDeInit.
00093     This function takes as parameters the HAL peripheral handle, the Callback ID
00094     and a pointer to the user callback function.
00095
00096     [..]
00097     Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default
00098     weak (surcharged) function.
00099     @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00100     and the Callback ID.
00101     This function allows to reset following callbacks:
00102     (+) TxHalfCpltCallback        : Tx Half Complete Callback.
00103     (+) TxCpltCallback            : Tx Complete Callback.
00104     (+) RxHalfCpltCallback        : Rx Half Complete Callback.
00105     (+) RxCpltCallback            : Rx Complete Callback.
00106     (+) ErrorCallback             : Error Callback.
00107     (+) AbortCpltCallback         : Abort Complete Callback.
00108     (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
00109     (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
00110     (+) WakeupCallback            : Wakeup Callback.
00111     (+) RxFifoFullCallback        : Rx Fifo Full Callback.
00112     (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
00113     (+) MspInitCallback           : UART MspInit.
00114     (+) MspDeInitCallback         : UART MspDeInit.
00115
00116     [..]
00117     By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
00118     all callbacks are set to the corresponding weak (surcharged) functions:
00119     examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback().
00120     Exception done for MspInit and MspDeInit functions that are respectively
00121     reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init()
00122     and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
00123     If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit()
00124     keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
00125
00126     [..]
00127     Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only.
00128     Exception done MspInit/MspDeInit that can be registered/unregistered
00129     in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user)
00130     MspInit/DeInit callbacks can be used during the Init/DeInit.
00131     In that case first register the MspInit/MspDeInit user callbacks
00132     using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit()
00133     or @ref HAL_UART_Init() function.
00134
00135     [..]
00136     When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
00137     not defined, the callback registration feature is not available
00138     and weak (surcharged) callbacks are used.
00139
00140
00141   @endverbatim
00142   ******************************************************************************
00143   * @attention
00144   *
00145   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00146   * All rights reserved.</center></h2>
00147   *
00148   * This software component is licensed by ST under BSD 3-Clause license,
00149   * the "License"; You may not use this file except in compliance with the
00150   * License. You may obtain a copy of the License at:
00151   *                        opensource.org/licenses/BSD-3-Clause
00152   *
00153   ******************************************************************************
00154   */
00155
00156 /* Includes ------------------------------------------------------------------*/
00157 #include "stm32wbxx_hal.h"
00158
00159 /** @addtogroup STM32WBxx_HAL_Driver
00160   * @{
00161   */
00162
00163 /** @defgroup UART UART
00164   * @brief HAL UART module driver
00165   * @{
00166   */
00167
00168 #ifdef HAL_UART_MODULE_ENABLED
00169
00170 /* Private typedef -----------------------------------------------------------*/
00171 /* Private define ------------------------------------------------------------*/
00172 /** @defgroup UART_Private_Constants UART Private Constants
00173   * @{
00174   */
00175 #define USART_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
00176                                       USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \
00177                                       USART_CR1_FIFOEN ))                      /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
00178
00179 #define USART_CR3_FIELDS  ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT| \
00180                                       USART_CR3_TXFTCFG | USART_CR3_RXFTCFG ))  /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */
00181
00182 #if defined(LPUART1)
00183 #define LPUART_BRR_MIN  0x00000300U  /* LPUART BRR minimum authorized value */
00184 #define LPUART_BRR_MAX  0x000FFFFFU  /* LPUART BRR maximum authorized value */
00185 #endif
00186
00187 #define UART_BRR_MIN    0x10U        /* UART BRR minimum authorized value */
00188 #define UART_BRR_MAX    0x0000FFFFU  /* UART BRR maximum authorized value */
00189
00190 /**
00191   * @}
00192   */
00193
00194 /* Private macros ------------------------------------------------------------*/
00195 /* Private variables ---------------------------------------------------------*/
00196 /* Private function prototypes -----------------------------------------------*/
00197 /** @addtogroup UART_Private_Functions
00198   * @{
00199   */
00200 static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
00201 static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
00202 static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00203 static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00204 static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00205 static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00206 static void UART_DMAError(DMA_HandleTypeDef *hdma);
00207 static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
00208 static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
00209 static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
00210 static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00211 static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00212 static void UART_TxISR_8BIT(UART_HandleTypeDef *huart);
00213 static void UART_TxISR_16BIT(UART_HandleTypeDef *huart);
00214 static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart);
00215 static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);
00216 static void UART_EndTransmit_IT(UART_HandleTypeDef *huart);
00217 static void UART_RxISR_8BIT(UART_HandleTypeDef *huart);
00218 static void UART_RxISR_16BIT(UART_HandleTypeDef *huart);
00219 static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart);
00220 static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);
00221 /**
00222   * @}
00223   */
00224
00225 /* Exported functions --------------------------------------------------------*/
00226
00227 /** @defgroup UART_Exported_Functions UART Exported Functions
00228   * @{
00229   */
00230
00231 /** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
00232   *  @brief    Initialization and Configuration functions
00233   *
00234 @verbatim
00235 ===============================================================================
00236             ##### Initialization and Configuration functions #####
00237  ===============================================================================
00238     [..]
00239     This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
00240     in asynchronous mode.
00241       (+) For the asynchronous mode the parameters below can be configured:
00242         (++) Baud Rate
00243         (++) Word Length
00244         (++) Stop Bit
00245         (++) Parity: If the parity is enabled, then the MSB bit of the data written
00246              in the data register is transmitted but is changed by the parity bit.
00247         (++) Hardware flow control
00248         (++) Receiver/transmitter modes
00249         (++) Over Sampling Method
00250         (++) One-Bit Sampling Method
00251       (+) For the asynchronous mode, the following advanced features can be configured as well:
00252         (++) TX and/or RX pin level inversion
00253         (++) data logical level inversion
00254         (++) RX and TX pins swap
00255         (++) RX overrun detection disabling
00256         (++) DMA disabling on RX error
00257         (++) MSB first on communication line
00258         (++) auto Baud rate detection
00259     [..]
00260     The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API
00261     follow respectively the UART asynchronous, UART Half duplex, UART LIN mode
00262     and UART multiprocessor mode configuration procedures (details for the procedures
00263     are available in reference manual).
00264
00265 @endverbatim
00266
00267   Depending on the frame length defined by the M1 and M0 bits (7-bit,
00268   8-bit or 9-bit), the possible UART formats are listed in the
00269   following table.
00270
00271   Table 1. UART frame format.
00272     +-----------------------------------------------------------------------+
00273     |  M1 bit |  M0 bit |  PCE bit  |             UART frame                |
00274     |---------|---------|-----------|---------------------------------------|
00275     |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
00276     |---------|---------|-----------|---------------------------------------|
00277     |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
00278     |---------|---------|-----------|---------------------------------------|
00279     |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
00280     |---------|---------|-----------|---------------------------------------|
00281     |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
00282     |---------|---------|-----------|---------------------------------------|
00283     |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
00284     |---------|---------|-----------|---------------------------------------|
00285     |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
00286     +-----------------------------------------------------------------------+
00287
00288   * @{
00289   */
00290
00291 /**
00292   * @brief Initialize the UART mode according to the specified
00293   *        parameters in the UART_InitTypeDef and initialize the associated handle.
00294   * @param huart UART handle.
00295   * @retval HAL status
00296   */
00297 HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
00298 {
00299   /* Check the UART handle allocation */
00300   if (huart == NULL)
00301   {
00302     return HAL_ERROR;
00303   }
00304
00305   if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
00306   {
00307     /* Check the parameters */
00308     assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
00309   }
00310   else
00311   {
00312     /* Check the parameters */
00313 #if defined(LPUART1)
00314     assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
00315 #else
00316     assert_param(IS_UART_INSTANCE(huart->Instance));
00317 #endif
00318   }
00319
00320   if (huart->gState == HAL_UART_STATE_RESET)
00321   {
00322     /* Allocate lock resource and initialize it */
00323     huart->Lock = HAL_UNLOCKED;
00324
00325 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00326     UART_InitCallbacksToDefault(huart);
00327
00328     if (huart->MspInitCallback == NULL)
00329     {
00330       huart->MspInitCallback = HAL_UART_MspInit;
00331     }
00332
00333     /* Init the low level hardware */
00334     huart->MspInitCallback(huart);
00335 #else
00336     /* Init the low level hardware : GPIO, CLOCK */
00337     HAL_UART_MspInit(huart);
00338 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
00339   }
00340
00341   huart->gState = HAL_UART_STATE_BUSY;
00342
00343   __HAL_UART_DISABLE(huart);
00344
00345   /* Set the UART Communication parameters */
00346   if (UART_SetConfig(huart) == HAL_ERROR)
00347   {
00348     return HAL_ERROR;
00349   }
00350
00351   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
00352   {
00353     UART_AdvFeatureConfig(huart);
00354   }
00355
00356   /* In asynchronous mode, the following bits must be kept cleared:
00357   - LINEN and CLKEN bits in the USART_CR2 register,
00358   - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
00359   CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
00360   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
00361
00362   __HAL_UART_ENABLE(huart);
00363
00364   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
00365   return (UART_CheckIdleState(huart));
00366 }
00367
00368 /**
00369   * @brief Initialize the half-duplex mode according to the specified
00370   *        parameters in the UART_InitTypeDef and creates the associated handle.
00371   * @param huart UART handle.
00372   * @retval HAL status
00373   */
00374 HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
00375 {
00376   /* Check the UART handle allocation */
00377   if (huart == NULL)
00378   {
00379     return HAL_ERROR;
00380   }
00381
00382   /* Check UART instance */
00383   assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
00384
00385   if (huart->gState == HAL_UART_STATE_RESET)
00386   {
00387     /* Allocate lock resource and initialize it */
00388     huart->Lock = HAL_UNLOCKED;
00389
00390 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00391     UART_InitCallbacksToDefault(huart);
00392
00393     if (huart->MspInitCallback == NULL)
00394     {
00395       huart->MspInitCallback = HAL_UART_MspInit;
00396     }
00397
00398     /* Init the low level hardware */
00399     huart->MspInitCallback(huart);
00400 #else
00401     /* Init the low level hardware : GPIO, CLOCK */
00402     HAL_UART_MspInit(huart);
00403 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
00404   }
00405
00406   huart->gState = HAL_UART_STATE_BUSY;
00407
00408   __HAL_UART_DISABLE(huart);
00409
00410   /* Set the UART Communication parameters */
00411   if (UART_SetConfig(huart) == HAL_ERROR)
00412   {
00413     return HAL_ERROR;
00414   }
00415
00416   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
00417   {
00418     UART_AdvFeatureConfig(huart);
00419   }
00420
00421   /* In half-duplex mode, the following bits must be kept cleared:
00422   - LINEN and CLKEN bits in the USART_CR2 register,
00423   - SCEN and IREN bits in the USART_CR3 register.*/
00424   CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
00425   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
00426
00427   /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
00428   SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
00429
00430   __HAL_UART_ENABLE(huart);
00431
00432   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
00433   return (UART_CheckIdleState(huart));
00434 }
00435
00436
00437 /**
00438   * @brief Initialize the LIN mode according to the specified
00439   *        parameters in the UART_InitTypeDef and creates the associated handle.
00440   * @param huart             UART handle.
00441   * @param BreakDetectLength Specifies the LIN break detection length.
00442   *        This parameter can be one of the following values:
00443   *          @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection
00444   *          @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection
00445   * @retval HAL status
00446   */
00447 HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
00448 {
00449   /* Check the UART handle allocation */
00450   if (huart == NULL)
00451   {
00452     return HAL_ERROR;
00453   }
00454
00455   /* Check the LIN UART instance */
00456   assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
00457   /* Check the Break detection length parameter */
00458   assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
00459
00460   /* LIN mode limited to 16-bit oversampling only */
00461   if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
00462   {
00463     return HAL_ERROR;
00464   }
00465   /* LIN mode limited to 8-bit data length */
00466   if (huart->Init.WordLength != UART_WORDLENGTH_8B)
00467   {
00468     return HAL_ERROR;
00469   }
00470
00471   if (huart->gState == HAL_UART_STATE_RESET)
00472   {
00473     /* Allocate lock resource and initialize it */
00474     huart->Lock = HAL_UNLOCKED;
00475
00476 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00477     UART_InitCallbacksToDefault(huart);
00478
00479     if (huart->MspInitCallback == NULL)
00480     {
00481       huart->MspInitCallback = HAL_UART_MspInit;
00482     }
00483
00484     /* Init the low level hardware */
00485     huart->MspInitCallback(huart);
00486 #else
00487     /* Init the low level hardware : GPIO, CLOCK */
00488     HAL_UART_MspInit(huart);
00489 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
00490   }
00491
00492   huart->gState = HAL_UART_STATE_BUSY;
00493
00494   __HAL_UART_DISABLE(huart);
00495
00496   /* Set the UART Communication parameters */
00497   if (UART_SetConfig(huart) == HAL_ERROR)
00498   {
00499     return HAL_ERROR;
00500   }
00501
00502   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
00503   {
00504     UART_AdvFeatureConfig(huart);
00505   }
00506
00507   /* In LIN mode, the following bits must be kept cleared:
00508   - LINEN and CLKEN bits in the USART_CR2 register,
00509   - SCEN and IREN bits in the USART_CR3 register.*/
00510   CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
00511   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
00512
00513   /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
00514   SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
00515
00516   /* Set the USART LIN Break detection length. */
00517   MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
00518
00519   __HAL_UART_ENABLE(huart);
00520
00521   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
00522   return (UART_CheckIdleState(huart));
00523 }
00524
00525
00526 /**
00527   * @brief Initialize the multiprocessor mode according to the specified
00528   *        parameters in the UART_InitTypeDef and initialize the associated handle.
00529   * @param huart        UART handle.
00530   * @param Address      UART node address (4-, 6-, 7- or 8-bit long).
00531   * @param WakeUpMethod Specifies the UART wakeup method.
00532   *        This parameter can be one of the following values:
00533   *          @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection
00534   *          @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark
00535   * @note  If the user resorts to idle line detection wake up, the Address parameter
00536   *        is useless and ignored by the initialization function.
00537   * @note  If the user resorts to address mark wake up, the address length detection
00538   *        is configured by default to 4 bits only. For the UART to be able to
00539   *        manage 6-, 7- or 8-bit long addresses detection, the API
00540   *        HAL_MultiProcessorEx_AddressLength_Set() must be called after
00541   *        HAL_MultiProcessor_Init().
00542   * @retval HAL status
00543   */
00544 HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
00545 {
00546   /* Check the UART handle allocation */
00547   if (huart == NULL)
00548   {
00549     return HAL_ERROR;
00550   }
00551
00552   /* Check the wake up method parameter */
00553   assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
00554
00555   if (huart->gState == HAL_UART_STATE_RESET)
00556   {
00557     /* Allocate lock resource and initialize it */
00558     huart->Lock = HAL_UNLOCKED;
00559
00560 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00561     UART_InitCallbacksToDefault(huart);
00562
00563     if (huart->MspInitCallback == NULL)
00564     {
00565       huart->MspInitCallback = HAL_UART_MspInit;
00566     }
00567
00568     /* Init the low level hardware */
00569     huart->MspInitCallback(huart);
00570 #else
00571     /* Init the low level hardware : GPIO, CLOCK */
00572     HAL_UART_MspInit(huart);
00573 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
00574   }
00575
00576   huart->gState = HAL_UART_STATE_BUSY;
00577
00578   __HAL_UART_DISABLE(huart);
00579
00580   /* Set the UART Communication parameters */
00581   if (UART_SetConfig(huart) == HAL_ERROR)
00582   {
00583     return HAL_ERROR;
00584   }
00585
00586   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
00587   {
00588     UART_AdvFeatureConfig(huart);
00589   }
00590
00591   /* In multiprocessor mode, the following bits must be kept cleared:
00592   - LINEN and CLKEN bits in the USART_CR2 register,
00593   - SCEN, HDSEL and IREN  bits in the USART_CR3 register. */
00594   CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
00595   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
00596
00597   if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)
00598   {
00599     /* If address mark wake up method is chosen, set the USART address node */
00600     MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS));
00601   }
00602
00603   /* Set the wake up method by setting the WAKE bit in the CR1 register */
00604   MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
00605
00606   __HAL_UART_ENABLE(huart);
00607
00608   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
00609   return (UART_CheckIdleState(huart));
00610 }
00611
00612
00613 /**
00614   * @brief DeInitialize the UART peripheral.
00615   * @param huart UART handle.
00616   * @retval HAL status
00617   */
00618 HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
00619 {
00620   /* Check the UART handle allocation */
00621   if (huart == NULL)
00622   {
00623     return HAL_ERROR;
00624   }
00625
00626   /* Check the parameters */
00627 #if defined(LPUART1)
00628   assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
00629 #else
00630   assert_param(IS_UART_INSTANCE(huart->Instance));
00631 #endif
00632
00633   huart->gState = HAL_UART_STATE_BUSY;
00634
00635   __HAL_UART_DISABLE(huart);
00636
00637   huart->Instance->CR1 = 0x0U;
00638   huart->Instance->CR2 = 0x0U;
00639   huart->Instance->CR3 = 0x0U;
00640
00641 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00642   if (huart->MspDeInitCallback == NULL)
00643   {
00644     huart->MspDeInitCallback = HAL_UART_MspDeInit;
00645   }
00646   /* DeInit the low level hardware */
00647   huart->MspDeInitCallback(huart);
00648 #else
00649   /* DeInit the low level hardware */
00650   HAL_UART_MspDeInit(huart);
00651 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
00652
00653   huart->ErrorCode = HAL_UART_ERROR_NONE;
00654   huart->gState = HAL_UART_STATE_RESET;
00655   huart->RxState = HAL_UART_STATE_RESET;
00656
00657   __HAL_UNLOCK(huart);
00658
00659   return HAL_OK;
00660 }
00661
00662 /**
00663   * @brief Initialize the UART MSP.
00664   * @param huart UART handle.
00665   * @retval None
00666   */
00667 __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
00668 {
00669   /* Prevent unused argument(s) compilation warning */
00670   UNUSED(huart);
00671
00672   /* NOTE : This function should not be modified, when the callback is needed,
00673             the HAL_UART_MspInit can be implemented in the user file
00674    */
00675 }
00676
00677 /**
00678   * @brief DeInitialize the UART MSP.
00679   * @param huart UART handle.
00680   * @retval None
00681   */
00682 __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
00683 {
00684   /* Prevent unused argument(s) compilation warning */
00685   UNUSED(huart);
00686
00687   /* NOTE : This function should not be modified, when the callback is needed,
00688             the HAL_UART_MspDeInit can be implemented in the user file
00689    */
00690 }
00691
00692 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00693 /**
00694   * @brief  Register a User UART Callback
00695   *         To be used instead of the weak predefined callback
00696   * @param  huart uart handle
00697   * @param  CallbackID ID of the callback to be registered
00698   *         This parameter can be one of the following values:
00699   *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
00700   *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
00701   *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
00702   *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
00703   *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
00704   *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
00705   *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
00706   *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
00707   *           @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
00708   *           @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
00709   *           @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
00710   *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
00711   *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
00712   * @param  pCallback pointer to the Callback function
00713   * @retval HAL status
00714   */
00715 HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
00716                                             pUART_CallbackTypeDef pCallback)
00717 {
00718   HAL_StatusTypeDef status = HAL_OK;
00719
00720   if (pCallback == NULL)
00721   {
00722     huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
00723
00724     return HAL_ERROR;
00725   }
00726
00727   __HAL_LOCK(huart);
00728
00729   if (huart->gState == HAL_UART_STATE_READY)
00730   {
00731     switch (CallbackID)
00732     {
00733       case HAL_UART_TX_HALFCOMPLETE_CB_ID :
00734         huart->TxHalfCpltCallback = pCallback;
00735         break;
00736
00737       case HAL_UART_TX_COMPLETE_CB_ID :
00738         huart->TxCpltCallback = pCallback;
00739         break;
00740
00741       case HAL_UART_RX_HALFCOMPLETE_CB_ID :
00742         huart->RxHalfCpltCallback = pCallback;
00743         break;
00744
00745       case HAL_UART_RX_COMPLETE_CB_ID :
00746         huart->RxCpltCallback = pCallback;
00747         break;
00748
00749       case HAL_UART_ERROR_CB_ID :
00750         huart->ErrorCallback = pCallback;
00751         break;
00752
00753       case HAL_UART_ABORT_COMPLETE_CB_ID :
00754         huart->AbortCpltCallback = pCallback;
00755         break;
00756
00757       case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
00758         huart->AbortTransmitCpltCallback = pCallback;
00759         break;
00760
00761       case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
00762         huart->AbortReceiveCpltCallback = pCallback;
00763         break;
00764
00765       case HAL_UART_WAKEUP_CB_ID :
00766         huart->WakeupCallback = pCallback;
00767         break;
00768
00769       case HAL_UART_RX_FIFO_FULL_CB_ID :
00770         huart->RxFifoFullCallback = pCallback;
00771         break;
00772
00773       case HAL_UART_TX_FIFO_EMPTY_CB_ID :
00774         huart->TxFifoEmptyCallback = pCallback;
00775         break;
00776
00777       case HAL_UART_MSPINIT_CB_ID :
00778         huart->MspInitCallback = pCallback;
00779         break;
00780
00781       case HAL_UART_MSPDEINIT_CB_ID :
00782         huart->MspDeInitCallback = pCallback;
00783         break;
00784
00785       default :
00786         huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
00787
00788         status =  HAL_ERROR;
00789         break;
00790     }
00791   }
00792   else if (huart->gState == HAL_UART_STATE_RESET)
00793   {
00794     switch (CallbackID)
00795     {
00796       case HAL_UART_MSPINIT_CB_ID :
00797         huart->MspInitCallback = pCallback;
00798         break;
00799
00800       case HAL_UART_MSPDEINIT_CB_ID :
00801         huart->MspDeInitCallback = pCallback;
00802         break;
00803
00804       default :
00805         huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
00806
00807         status =  HAL_ERROR;
00808         break;
00809     }
00810   }
00811   else
00812   {
00813     huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
00814
00815     status =  HAL_ERROR;
00816   }
00817
00818   __HAL_UNLOCK(huart);
00819
00820   return status;
00821 }
00822
00823 /**
00824   * @brief  Unregister an UART Callback
00825   *         UART callaback is redirected to the weak predefined callback
00826   * @param  huart uart handle
00827   * @param  CallbackID ID of the callback to be unregistered
00828   *         This parameter can be one of the following values:
00829   *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
00830   *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
00831   *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
00832   *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
00833   *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
00834   *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
00835   *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
00836   *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
00837   *           @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
00838   *           @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
00839   *           @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
00840   *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
00841   *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
00842   * @retval HAL status
00843   */
00844 HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID)
00845 {
00846   HAL_StatusTypeDef status = HAL_OK;
00847
00848   __HAL_LOCK(huart);
00849
00850   if (HAL_UART_STATE_READY == huart->gState)
00851   {
00852     switch (CallbackID)
00853     {
00854       case HAL_UART_TX_HALFCOMPLETE_CB_ID :
00855         huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback;               /* Legacy weak  TxHalfCpltCallback       */
00856         break;
00857
00858       case HAL_UART_TX_COMPLETE_CB_ID :
00859         huart->TxCpltCallback = HAL_UART_TxCpltCallback;                       /* Legacy weak TxCpltCallback            */
00860         break;
00861
00862       case HAL_UART_RX_HALFCOMPLETE_CB_ID :
00863         huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback;               /* Legacy weak RxHalfCpltCallback        */
00864         break;
00865
00866       case HAL_UART_RX_COMPLETE_CB_ID :
00867         huart->RxCpltCallback = HAL_UART_RxCpltCallback;                       /* Legacy weak RxCpltCallback            */
00868         break;
00869
00870       case HAL_UART_ERROR_CB_ID :
00871         huart->ErrorCallback = HAL_UART_ErrorCallback;                         /* Legacy weak ErrorCallback             */
00872         break;
00873
00874       case HAL_UART_ABORT_COMPLETE_CB_ID :
00875         huart->AbortCpltCallback = HAL_UART_AbortCpltCallback;                 /* Legacy weak AbortCpltCallback         */
00876         break;
00877
00878       case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
00879         huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
00880         break;
00881
00882       case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
00883         huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback;   /* Legacy weak AbortReceiveCpltCallback  */
00884         break;
00885
00886       case HAL_UART_WAKEUP_CB_ID :
00887         huart->WakeupCallback = HAL_UARTEx_WakeupCallback;                     /* Legacy weak WakeupCallback            */
00888         break;
00889
00890       case HAL_UART_RX_FIFO_FULL_CB_ID :
00891         huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback;             /* Legacy weak RxFifoFullCallback        */
00892         break;
00893
00894       case HAL_UART_TX_FIFO_EMPTY_CB_ID :
00895         huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback;           /* Legacy weak TxFifoEmptyCallback       */
00896         break;
00897
00898       case HAL_UART_MSPINIT_CB_ID :
00899         huart->MspInitCallback = HAL_UART_MspInit;                             /* Legacy weak MspInitCallback           */
00900         break;
00901
00902       case HAL_UART_MSPDEINIT_CB_ID :
00903         huart->MspDeInitCallback = HAL_UART_MspDeInit;                         /* Legacy weak MspDeInitCallback         */
00904         break;
00905
00906       default :
00907         huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
00908
00909         status =  HAL_ERROR;
00910         break;
00911     }
00912   }
00913   else if (HAL_UART_STATE_RESET == huart->gState)
00914   {
00915     switch (CallbackID)
00916     {
00917       case HAL_UART_MSPINIT_CB_ID :
00918         huart->MspInitCallback = HAL_UART_MspInit;
00919         break;
00920
00921       case HAL_UART_MSPDEINIT_CB_ID :
00922         huart->MspDeInitCallback = HAL_UART_MspDeInit;
00923         break;
00924
00925       default :
00926         huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
00927
00928         status =  HAL_ERROR;
00929         break;
00930     }
00931   }
00932   else
00933   {
00934     huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
00935
00936     status =  HAL_ERROR;
00937   }
00938
00939   __HAL_UNLOCK(huart);
00940
00941   return status;
00942 }
00943 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
00944
00945 /**
00946   * @}
00947   */
00948
00949 /** @defgroup UART_Exported_Functions_Group2 IO operation functions
00950   * @brief UART Transmit/Receive functions
00951   *
00952 @verbatim
00953  ===============================================================================
00954                       ##### IO operation functions #####
00955  ===============================================================================
00956     This subsection provides a set of functions allowing to manage the UART asynchronous
00957     and Half duplex data transfers.
00958
00959     (#) There are two mode of transfer:
00960        (+) Blocking mode: The communication is performed in polling mode.
00961            The HAL status of all data processing is returned by the same function
00962            after finishing transfer.
00963        (+) Non-Blocking mode: The communication is performed using Interrupts
00964            or DMA, These API's return the HAL status.
00965            The end of the data processing will be indicated through the
00966            dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
00967            using DMA mode.
00968            The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
00969            will be executed respectively at the end of the transmit or Receive process
00970            The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected
00971
00972     (#) Blocking mode API's are :
00973         (+) HAL_UART_Transmit()
00974         (+) HAL_UART_Receive()
00975
00976     (#) Non-Blocking mode API's with Interrupt are :
00977         (+) HAL_UART_Transmit_IT()
00978         (+) HAL_UART_Receive_IT()
00979         (+) HAL_UART_IRQHandler()
00980
00981     (#) Non-Blocking mode API's with DMA are :
00982         (+) HAL_UART_Transmit_DMA()
00983         (+) HAL_UART_Receive_DMA()
00984         (+) HAL_UART_DMAPause()
00985         (+) HAL_UART_DMAResume()
00986         (+) HAL_UART_DMAStop()
00987
00988     (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
00989         (+) HAL_UART_TxHalfCpltCallback()
00990         (+) HAL_UART_TxCpltCallback()
00991         (+) HAL_UART_RxHalfCpltCallback()
00992         (+) HAL_UART_RxCpltCallback()
00993         (+) HAL_UART_ErrorCallback()
00994
00995     (#) Non-Blocking mode transfers could be aborted using Abort API's :
00996         (+) HAL_UART_Abort()
00997         (+) HAL_UART_AbortTransmit()
00998         (+) HAL_UART_AbortReceive()
00999         (+) HAL_UART_Abort_IT()
01000         (+) HAL_UART_AbortTransmit_IT()
01001         (+) HAL_UART_AbortReceive_IT()
01002
01003     (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
01004         (+) HAL_UART_AbortCpltCallback()
01005         (+) HAL_UART_AbortTransmitCpltCallback()
01006         (+) HAL_UART_AbortReceiveCpltCallback()
01007
01008     (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
01009         Errors are handled as follows :
01010        (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
01011            to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
01012            Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
01013            and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side.
01014            If user wants to abort it, Abort services should be called by user.
01015        (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
01016            This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
01017            Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
01018
01019     -@- In the Half duplex communication, it is forbidden to run the transmit
01020         and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
01021
01022 @endverbatim
01023   * @{
01024   */
01025
01026 /**
01027   * @brief Send an amount of data in blocking mode.
01028   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01029   *         the sent data is handled as a set of u16. In this case, Size must indicate the number
01030   *         of u16 provided through pData.
01031   * @note When FIFO mode is enabled, writing a data in the TDR register adds one
01032   *       data to the TXFIFO. Write operations to the TDR register are performed
01033   *       when TXFNF flag is set. From hardware perspective, TXFNF flag and
01034   *       TXE are mapped on the same bit-field.
01035   * @param huart   UART handle.
01036   * @param pData   Pointer to data buffer (u8 or u16 data elements).
01037   * @param Size    Amount of data elements (u8 or u16) to be sent.
01038   * @param Timeout Timeout duration.
01039   * @retval HAL status
01040   */
01041 HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
01042 {
01043   uint8_t  *pdata8bits;
01044   uint16_t *pdata16bits;
01045   uint32_t tickstart;
01046
01047   /* Check that a Tx process is not already ongoing */
01048   if (huart->gState == HAL_UART_STATE_READY)
01049   {
01050     if ((pData == NULL) || (Size == 0U))
01051     {
01052       return  HAL_ERROR;
01053     }
01054
01055     __HAL_LOCK(huart);
01056
01057     huart->ErrorCode = HAL_UART_ERROR_NONE;
01058     huart->gState = HAL_UART_STATE_BUSY_TX;
01059
01060     /* Init tickstart for timeout managment*/
01061     tickstart = HAL_GetTick();
01062
01063     huart->TxXferSize  = Size;
01064     huart->TxXferCount = Size;
01065
01066     /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
01067     if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
01068     {
01069       pdata8bits  = NULL;
01070       pdata16bits = (uint16_t *) pData;
01071     }
01072     else
01073     {
01074       pdata8bits  = pData;
01075       pdata16bits = NULL;
01076     }
01077
01078     __HAL_UNLOCK(huart);
01079
01080     while (huart->TxXferCount > 0U)
01081     {
01082       if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
01083       {
01084         return HAL_TIMEOUT;
01085       }
01086       if (pdata8bits == NULL)
01087       {
01088         huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
01089         pdata16bits++;
01090       }
01091       else
01092       {
01093         huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
01094         pdata8bits++;
01095       }
01096       huart->TxXferCount--;
01097     }
01098
01099     if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
01100     {
01101       return HAL_TIMEOUT;
01102     }
01103
01104     /* At end of Tx process, restore huart->gState to Ready */
01105     huart->gState = HAL_UART_STATE_READY;
01106
01107     return HAL_OK;
01108   }
01109   else
01110   {
01111     return HAL_BUSY;
01112   }
01113 }
01114
01115 /**
01116   * @brief Receive an amount of data in blocking mode.
01117   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01118   *         the received data is handled as a set of u16. In this case, Size must indicate the number
01119   *         of u16 available through pData.
01120   * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
01121   *       is not empty. Read operations from the RDR register are performed when
01122   *       RXFNE flag is set. From hardware perspective, RXFNE flag and
01123   *       RXNE are mapped on the same bit-field.
01124   * @param huart   UART handle.
01125   * @param pData   Pointer to data buffer (u8 or u16 data elements).
01126   * @param Size    Amount of data elements (u8 or u16) to be received.
01127   * @param Timeout Timeout duration.
01128   * @retval HAL status
01129   */
01130 HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
01131 {
01132   uint8_t  *pdata8bits;
01133   uint16_t *pdata16bits;
01134   uint16_t uhMask;
01135   uint32_t tickstart;
01136
01137   /* Check that a Rx process is not already ongoing */
01138   if (huart->RxState == HAL_UART_STATE_READY)
01139   {
01140     if ((pData == NULL) || (Size == 0U))
01141     {
01142       return  HAL_ERROR;
01143     }
01144
01145     __HAL_LOCK(huart);
01146
01147     huart->ErrorCode = HAL_UART_ERROR_NONE;
01148     huart->RxState = HAL_UART_STATE_BUSY_RX;
01149
01150     /* Init tickstart for timeout managment*/
01151     tickstart = HAL_GetTick();
01152
01153     huart->RxXferSize  = Size;
01154     huart->RxXferCount = Size;
01155
01156     /* Computation of UART mask to apply to RDR register */
01157     UART_MASK_COMPUTATION(huart);
01158     uhMask = huart->Mask;
01159
01160     /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
01161     if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
01162     {
01163       pdata8bits  = NULL;
01164       pdata16bits = (uint16_t *) pData;
01165     }
01166     else
01167     {
01168       pdata8bits  = pData;
01169       pdata16bits = NULL;
01170     }
01171
01172     __HAL_UNLOCK(huart);
01173
01174     /* as long as data have to be received */
01175     while (huart->RxXferCount > 0U)
01176     {
01177       if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
01178       {
01179         return HAL_TIMEOUT;
01180       }
01181       if (pdata8bits == NULL)
01182       {
01183         *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
01184         pdata16bits++;
01185       }
01186       else
01187       {
01188         *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
01189         pdata8bits++;
01190       }
01191       huart->RxXferCount--;
01192     }
01193
01194     /* At end of Rx process, restore huart->RxState to Ready */
01195     huart->RxState = HAL_UART_STATE_READY;
01196
01197     return HAL_OK;
01198   }
01199   else
01200   {
01201     return HAL_BUSY;
01202   }
01203 }
01204
01205 /**
01206   * @brief Send an amount of data in interrupt mode.
01207   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01208   *         the sent data is handled as a set of u16. In this case, Size must indicate the number
01209   *         of u16 provided through pData.
01210   * @param huart UART handle.
01211   * @param pData Pointer to data buffer (u8 or u16 data elements).
01212   * @param Size  Amount of data elements (u8 or u16) to be sent.
01213   * @retval HAL status
01214   */
01215 HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
01216 {
01217   /* Check that a Tx process is not already ongoing */
01218   if (huart->gState == HAL_UART_STATE_READY)
01219   {
01220     if ((pData == NULL) || (Size == 0U))
01221     {
01222       return HAL_ERROR;
01223     }
01224
01225     __HAL_LOCK(huart);
01226
01227     huart->pTxBuffPtr  = pData;
01228     huart->TxXferSize  = Size;
01229     huart->TxXferCount = Size;
01230     huart->TxISR       = NULL;
01231
01232     huart->ErrorCode = HAL_UART_ERROR_NONE;
01233     huart->gState = HAL_UART_STATE_BUSY_TX;
01234
01235     /* Configure Tx interrupt processing */
01236     if (huart->FifoMode == UART_FIFOMODE_ENABLE)
01237     {
01238       /* Set the Tx ISR function pointer according to the data word length */
01239       if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
01240       {
01241         huart->TxISR = UART_TxISR_16BIT_FIFOEN;
01242       }
01243       else
01244       {
01245         huart->TxISR = UART_TxISR_8BIT_FIFOEN;
01246       }
01247
01248       __HAL_UNLOCK(huart);
01249
01250       /* Enable the TX FIFO threshold interrupt */
01251       SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
01252     }
01253     else
01254     {
01255       /* Set the Tx ISR function pointer according to the data word length */
01256       if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
01257       {
01258         huart->TxISR = UART_TxISR_16BIT;
01259       }
01260       else
01261       {
01262         huart->TxISR = UART_TxISR_8BIT;
01263       }
01264
01265       __HAL_UNLOCK(huart);
01266
01267       /* Enable the Transmit Data Register Empty interrupt */
01268       SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
01269     }
01270
01271     return HAL_OK;
01272   }
01273   else
01274   {
01275     return HAL_BUSY;
01276   }
01277 }
01278
01279 /**
01280   * @brief Receive an amount of data in interrupt mode.
01281   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01282   *         the received data is handled as a set of u16. In this case, Size must indicate the number
01283   *         of u16 available through pData.
01284   * @param huart UART handle.
01285   * @param pData Pointer to data buffer (u8 or u16 data elements).
01286   * @param Size  Amount of data elements (u8 or u16) to be received.
01287   * @retval HAL status
01288   */
01289 HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
01290 {
01291   /* Check that a Rx process is not already ongoing */
01292   if (huart->RxState == HAL_UART_STATE_READY)
01293   {
01294     if ((pData == NULL) || (Size == 0U))
01295     {
01296       return HAL_ERROR;
01297     }
01298
01299     __HAL_LOCK(huart);
01300
01301     huart->pRxBuffPtr  = pData;
01302     huart->RxXferSize  = Size;
01303     huart->RxXferCount = Size;
01304     huart->RxISR       = NULL;
01305
01306     /* Computation of UART mask to apply to RDR register */
01307     UART_MASK_COMPUTATION(huart);
01308
01309     huart->ErrorCode = HAL_UART_ERROR_NONE;
01310     huart->RxState = HAL_UART_STATE_BUSY_RX;
01311
01312     /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
01313     SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
01314
01315     /* Configure Rx interrupt processing*/
01316     if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))
01317     {
01318       /* Set the Rx ISR function pointer according to the data word length */
01319       if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
01320       {
01321         huart->RxISR = UART_RxISR_16BIT_FIFOEN;
01322       }
01323       else
01324       {
01325         huart->RxISR = UART_RxISR_8BIT_FIFOEN;
01326       }
01327
01328       __HAL_UNLOCK(huart);
01329
01330       /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
01331       SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
01332       SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
01333     }
01334     else
01335     {
01336       /* Set the Rx ISR function pointer according to the data word length */
01337       if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
01338       {
01339         huart->RxISR = UART_RxISR_16BIT;
01340       }
01341       else
01342       {
01343         huart->RxISR = UART_RxISR_8BIT;
01344       }
01345
01346       __HAL_UNLOCK(huart);
01347
01348       /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
01349       SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
01350     }
01351
01352     return HAL_OK;
01353   }
01354   else
01355   {
01356     return HAL_BUSY;
01357   }
01358 }
01359
01360 /**
01361   * @brief Send an amount of data in DMA mode.
01362   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01363   *         the sent data is handled as a set of u16. In this case, Size must indicate the number
01364   *         of u16 provided through pData.
01365   * @param huart UART handle.
01366   * @param pData Pointer to data buffer (u8 or u16 data elements).
01367   * @param Size  Amount of data elements (u8 or u16) to be sent.
01368   * @retval HAL status
01369   */
01370 HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
01371 {
01372   /* Check that a Tx process is not already ongoing */
01373   if (huart->gState == HAL_UART_STATE_READY)
01374   {
01375     if ((pData == NULL) || (Size == 0U))
01376     {
01377       return HAL_ERROR;
01378     }
01379
01380     __HAL_LOCK(huart);
01381
01382     huart->pTxBuffPtr  = pData;
01383     huart->TxXferSize  = Size;
01384     huart->TxXferCount = Size;
01385
01386     huart->ErrorCode = HAL_UART_ERROR_NONE;
01387     huart->gState = HAL_UART_STATE_BUSY_TX;
01388
01389     if (huart->hdmatx != NULL)
01390     {
01391       /* Set the UART DMA transfer complete callback */
01392       huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
01393
01394       /* Set the UART DMA Half transfer complete callback */
01395       huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
01396
01397       /* Set the DMA error callback */
01398       huart->hdmatx->XferErrorCallback = UART_DMAError;
01399
01400       /* Set the DMA abort callback */
01401       huart->hdmatx->XferAbortCallback = NULL;
01402
01403       /* Enable the UART transmit DMA channel */
01404       if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size) != HAL_OK)
01405       {
01406         /* Set error code to DMA */
01407         huart->ErrorCode = HAL_UART_ERROR_DMA;
01408
01409         __HAL_UNLOCK(huart);
01410
01411         /* Restore huart->gState to ready */
01412         huart->gState = HAL_UART_STATE_READY;
01413
01414         return HAL_ERROR;
01415       }
01416     }
01417     /* Clear the TC flag in the ICR register */
01418     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
01419
01420     __HAL_UNLOCK(huart);
01421
01422     /* Enable the DMA transfer for transmit request by setting the DMAT bit
01423     in the UART CR3 register */
01424     SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01425
01426     return HAL_OK;
01427   }
01428   else
01429   {
01430     return HAL_BUSY;
01431   }
01432 }
01433
01434 /**
01435   * @brief Receive an amount of data in DMA mode.
01436   * @note   When the UART parity is enabled (PCE = 1), the received data contain
01437   *         the parity bit (MSB position).
01438   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01439   *         the received data is handled as a set of u16. In this case, Size must indicate the number
01440   *         of u16 available through pData.
01441   * @param huart UART handle.
01442   * @param pData Pointer to data buffer (u8 or u16 data elements).
01443   * @param Size  Amount of data elements (u8 or u16) to be received.
01444   * @retval HAL status
01445   */
01446 HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
01447 {
01448   /* Check that a Rx process is not already ongoing */
01449   if (huart->RxState == HAL_UART_STATE_READY)
01450   {
01451     if ((pData == NULL) || (Size == 0U))
01452     {
01453       return HAL_ERROR;
01454     }
01455
01456     __HAL_LOCK(huart);
01457
01458     huart->pRxBuffPtr = pData;
01459     huart->RxXferSize = Size;
01460
01461     huart->ErrorCode = HAL_UART_ERROR_NONE;
01462     huart->RxState = HAL_UART_STATE_BUSY_RX;
01463
01464     if (huart->hdmarx != NULL)
01465     {
01466       /* Set the UART DMA transfer complete callback */
01467       huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
01468
01469       /* Set the UART DMA Half transfer complete callback */
01470       huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
01471
01472       /* Set the DMA error callback */
01473       huart->hdmarx->XferErrorCallback = UART_DMAError;
01474
01475       /* Set the DMA abort callback */
01476       huart->hdmarx->XferAbortCallback = NULL;
01477
01478       /* Enable the DMA channel */
01479       if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK)
01480       {
01481         /* Set error code to DMA */
01482         huart->ErrorCode = HAL_UART_ERROR_DMA;
01483
01484         __HAL_UNLOCK(huart);
01485
01486         /* Restore huart->gState to ready */
01487         huart->gState = HAL_UART_STATE_READY;
01488
01489         return HAL_ERROR;
01490       }
01491     }
01492     __HAL_UNLOCK(huart);
01493
01494     /* Enable the UART Parity Error Interrupt */
01495     SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
01496
01497     /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
01498     SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
01499
01500     /* Enable the DMA transfer for the receiver request by setting the DMAR bit
01501     in the UART CR3 register */
01502     SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01503
01504     return HAL_OK;
01505   }
01506   else
01507   {
01508     return HAL_BUSY;
01509   }
01510 }
01511
01512 /**
01513   * @brief Pause the DMA Transfer.
01514   * @param huart UART handle.
01515   * @retval HAL status
01516   */
01517 HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
01518 {
01519   const HAL_UART_StateTypeDef gstate = huart->gState;
01520   const HAL_UART_StateTypeDef rxstate = huart->RxState;
01521
01522   __HAL_LOCK(huart);
01523
01524   if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
01525       (gstate == HAL_UART_STATE_BUSY_TX))
01526   {
01527     /* Disable the UART DMA Tx request */
01528     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01529   }
01530   if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
01531       (rxstate == HAL_UART_STATE_BUSY_RX))
01532   {
01533     /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
01534     CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
01535     CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
01536
01537     /* Disable the UART DMA Rx request */
01538     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01539   }
01540
01541   __HAL_UNLOCK(huart);
01542
01543   return HAL_OK;
01544 }
01545
01546 /**
01547   * @brief Resume the DMA Transfer.
01548   * @param huart UART handle.
01549   * @retval HAL status
01550   */
01551 HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
01552 {
01553   __HAL_LOCK(huart);
01554
01555   if (huart->gState == HAL_UART_STATE_BUSY_TX)
01556   {
01557     /* Enable the UART DMA Tx request */
01558     SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01559   }
01560   if (huart->RxState == HAL_UART_STATE_BUSY_RX)
01561   {
01562     /* Clear the Overrun flag before resuming the Rx transfer */
01563     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
01564
01565     /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
01566     SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
01567     SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
01568
01569     /* Enable the UART DMA Rx request */
01570     SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01571   }
01572
01573   __HAL_UNLOCK(huart);
01574
01575   return HAL_OK;
01576 }
01577
01578 /**
01579   * @brief Stop the DMA Transfer.
01580   * @param huart UART handle.
01581   * @retval HAL status
01582   */
01583 HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
01584 {
01585   /* The Lock is not implemented on this API to allow the user application
01586      to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() /
01587      HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback:
01588      indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
01589      interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
01590      the stream and the corresponding call back is executed. */
01591
01592   const HAL_UART_StateTypeDef gstate = huart->gState;
01593   const HAL_UART_StateTypeDef rxstate = huart->RxState;
01594
01595   /* Stop UART DMA Tx request if ongoing */
01596   if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
01597       (gstate == HAL_UART_STATE_BUSY_TX))
01598   {
01599     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01600
01601     /* Abort the UART DMA Tx channel */
01602     if (huart->hdmatx != NULL)
01603     {
01604       if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
01605       {
01606         if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
01607         {
01608           /* Set error code to DMA */
01609           huart->ErrorCode = HAL_UART_ERROR_DMA;
01610
01611           return HAL_TIMEOUT;
01612         }
01613       }
01614     }
01615
01616     UART_EndTxTransfer(huart);
01617   }
01618
01619   /* Stop UART DMA Rx request if ongoing */
01620   if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
01621       (rxstate == HAL_UART_STATE_BUSY_RX))
01622   {
01623     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01624
01625     /* Abort the UART DMA Rx channel */
01626     if (huart->hdmarx != NULL)
01627     {
01628       if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
01629       {
01630         if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
01631         {
01632           /* Set error code to DMA */
01633           huart->ErrorCode = HAL_UART_ERROR_DMA;
01634
01635           return HAL_TIMEOUT;
01636         }
01637       }
01638     }
01639
01640     UART_EndRxTransfer(huart);
01641   }
01642
01643   return HAL_OK;
01644 }
01645
01646 /**
01647   * @brief  Abort ongoing transfers (blocking mode).
01648   * @param  huart UART handle.
01649   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01650   *         This procedure performs following operations :
01651   *           - Disable UART Interrupts (Tx and Rx)
01652   *           - Disable the DMA transfer in the peripheral register (if enabled)
01653   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01654   *           - Set handle State to READY
01655   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01656   * @retval HAL status
01657   */
01658 HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
01659 {
01660   /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
01661   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
01662   CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);
01663
01664   /* Disable the UART DMA Tx request if enabled */
01665   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
01666   {
01667     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01668
01669     /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
01670     if (huart->hdmatx != NULL)
01671     {
01672       /* Set the UART DMA Abort callback to Null.
01673          No call back execution at end of DMA abort procedure */
01674       huart->hdmatx->XferAbortCallback = NULL;
01675
01676       if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
01677       {
01678         if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
01679         {
01680           /* Set error code to DMA */
01681           huart->ErrorCode = HAL_UART_ERROR_DMA;
01682
01683           return HAL_TIMEOUT;
01684         }
01685       }
01686     }
01687   }
01688
01689   /* Disable the UART DMA Rx request if enabled */
01690   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
01691   {
01692     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01693
01694     /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
01695     if (huart->hdmarx != NULL)
01696     {
01697       /* Set the UART DMA Abort callback to Null.
01698          No call back execution at end of DMA abort procedure */
01699       huart->hdmarx->XferAbortCallback = NULL;
01700
01701       if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
01702       {
01703         if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
01704         {
01705           /* Set error code to DMA */
01706           huart->ErrorCode = HAL_UART_ERROR_DMA;
01707
01708           return HAL_TIMEOUT;
01709         }
01710       }
01711     }
01712   }
01713
01714   /* Reset Tx and Rx transfer counters */
01715   huart->TxXferCount = 0U;
01716   huart->RxXferCount = 0U;
01717
01718   /* Clear the Error flags in the ICR register */
01719   __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
01720
01721   /* Flush the whole TX FIFO (if needed) */
01722   if (huart->FifoMode == UART_FIFOMODE_ENABLE)
01723   {
01724     __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
01725   }
01726
01727   /* Discard the received data */
01728   __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
01729
01730   /* Restore huart->gState and huart->RxState to Ready */
01731   huart->gState  = HAL_UART_STATE_READY;
01732   huart->RxState = HAL_UART_STATE_READY;
01733
01734   huart->ErrorCode = HAL_UART_ERROR_NONE;
01735
01736   return HAL_OK;
01737 }
01738
01739 /**
01740   * @brief  Abort ongoing Transmit transfer (blocking mode).
01741   * @param  huart UART handle.
01742   * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
01743   *         This procedure performs following operations :
01744   *           - Disable UART Interrupts (Tx)
01745   *           - Disable the DMA transfer in the peripheral register (if enabled)
01746   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01747   *           - Set handle State to READY
01748   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01749   * @retval HAL status
01750   */
01751 HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
01752 {
01753   /* Disable TCIE, TXEIE and TXFTIE interrupts */
01754   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
01755   CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
01756
01757   /* Disable the UART DMA Tx request if enabled */
01758   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
01759   {
01760     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01761
01762     /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
01763     if (huart->hdmatx != NULL)
01764     {
01765       /* Set the UART DMA Abort callback to Null.
01766          No call back execution at end of DMA abort procedure */
01767       huart->hdmatx->XferAbortCallback = NULL;
01768
01769       if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
01770       {
01771         if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
01772         {
01773           /* Set error code to DMA */
01774           huart->ErrorCode = HAL_UART_ERROR_DMA;
01775
01776           return HAL_TIMEOUT;
01777         }
01778       }
01779     }
01780   }
01781
01782   /* Reset Tx transfer counter */
01783   huart->TxXferCount = 0U;
01784
01785   /* Flush the whole TX FIFO (if needed) */
01786   if (huart->FifoMode == UART_FIFOMODE_ENABLE)
01787   {
01788     __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
01789   }
01790
01791   /* Restore huart->gState to Ready */
01792   huart->gState = HAL_UART_STATE_READY;
01793
01794   return HAL_OK;
01795 }
01796
01797 /**
01798   * @brief  Abort ongoing Receive transfer (blocking mode).
01799   * @param  huart UART handle.
01800   * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
01801   *         This procedure performs following operations :
01802   *           - Disable UART Interrupts (Rx)
01803   *           - Disable the DMA transfer in the peripheral register (if enabled)
01804   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01805   *           - Set handle State to READY
01806   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01807   * @retval HAL status
01808   */
01809 HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
01810 {
01811   /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */
01812   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
01813   CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
01814
01815   /* Disable the UART DMA Rx request if enabled */
01816   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
01817   {
01818     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01819
01820     /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
01821     if (huart->hdmarx != NULL)
01822     {
01823       /* Set the UART DMA Abort callback to Null.
01824          No call back execution at end of DMA abort procedure */
01825       huart->hdmarx->XferAbortCallback = NULL;
01826
01827       if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
01828       {
01829         if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
01830         {
01831           /* Set error code to DMA */
01832           huart->ErrorCode = HAL_UART_ERROR_DMA;
01833
01834           return HAL_TIMEOUT;
01835         }
01836       }
01837     }
01838   }
01839
01840   /* Reset Rx transfer counter */
01841   huart->RxXferCount = 0U;
01842
01843   /* Clear the Error flags in the ICR register */
01844   __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
01845
01846   /* Discard the received data */
01847   __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
01848
01849   /* Restore huart->RxState to Ready */
01850   huart->RxState = HAL_UART_STATE_READY;
01851
01852   return HAL_OK;
01853 }
01854
01855 /**
01856   * @brief  Abort ongoing transfers (Interrupt mode).
01857   * @param  huart UART handle.
01858   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01859   *         This procedure performs following operations :
01860   *           - Disable UART Interrupts (Tx and Rx)
01861   *           - Disable the DMA transfer in the peripheral register (if enabled)
01862   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01863   *           - Set handle State to READY
01864   *           - At abort completion, call user abort complete callback
01865   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01866   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01867   * @retval HAL status
01868   */
01869 HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
01870 {
01871   uint32_t abortcplt = 1U;
01872
01873   /* Disable interrupts */
01874   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE | USART_CR1_TXEIE_TXFNFIE));
01875   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
01876
01877   /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
01878      before any call to DMA Abort functions */
01879   /* DMA Tx Handle is valid */
01880   if (huart->hdmatx != NULL)
01881   {
01882     /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
01883        Otherwise, set it to NULL */
01884     if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
01885     {
01886       huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
01887     }
01888     else
01889     {
01890       huart->hdmatx->XferAbortCallback = NULL;
01891     }
01892   }
01893   /* DMA Rx Handle is valid */
01894   if (huart->hdmarx != NULL)
01895   {
01896     /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
01897        Otherwise, set it to NULL */
01898     if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
01899     {
01900       huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
01901     }
01902     else
01903     {
01904       huart->hdmarx->XferAbortCallback = NULL;
01905     }
01906   }
01907
01908   /* Disable the UART DMA Tx request if enabled */
01909   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
01910   {
01911     /* Disable DMA Tx at UART level */
01912     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01913
01914     /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
01915     if (huart->hdmatx != NULL)
01916     {
01917       /* UART Tx DMA Abort callback has already been initialised :
01918          will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
01919
01920       /* Abort DMA TX */
01921       if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
01922       {
01923         huart->hdmatx->XferAbortCallback = NULL;
01924       }
01925       else
01926       {
01927         abortcplt = 0U;
01928       }
01929     }
01930   }
01931
01932   /* Disable the UART DMA Rx request if enabled */
01933   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
01934   {
01935     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01936
01937     /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
01938     if (huart->hdmarx != NULL)
01939     {
01940       /* UART Rx DMA Abort callback has already been initialised :
01941          will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
01942
01943       /* Abort DMA RX */
01944       if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
01945       {
01946         huart->hdmarx->XferAbortCallback = NULL;
01947         abortcplt = 1U;
01948       }
01949       else
01950       {
01951         abortcplt = 0U;
01952       }
01953     }
01954   }
01955
01956   /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
01957   if (abortcplt == 1U)
01958   {
01959     /* Reset Tx and Rx transfer counters */
01960     huart->TxXferCount = 0U;
01961     huart->RxXferCount = 0U;
01962
01963     /* Clear ISR function pointers */
01964     huart->RxISR = NULL;
01965     huart->TxISR = NULL;
01966
01967     /* Reset errorCode */
01968     huart->ErrorCode = HAL_UART_ERROR_NONE;
01969
01970     /* Clear the Error flags in the ICR register */
01971     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
01972
01973     /* Flush the whole TX FIFO (if needed) */
01974     if (huart->FifoMode == UART_FIFOMODE_ENABLE)
01975     {
01976       __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
01977     }
01978
01979     /* Discard the received data */
01980     __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
01981
01982     /* Restore huart->gState and huart->RxState to Ready */
01983     huart->gState  = HAL_UART_STATE_READY;
01984     huart->RxState = HAL_UART_STATE_READY;
01985
01986     /* As no DMA to be aborted, call directly user Abort complete callback */
01987 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
01988     /* Call registered Abort complete callback */
01989     huart->AbortCpltCallback(huart);
01990 #else
01991     /* Call legacy weak Abort complete callback */
01992     HAL_UART_AbortCpltCallback(huart);
01993 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
01994   }
01995
01996   return HAL_OK;
01997 }
01998
01999 /**
02000   * @brief  Abort ongoing Transmit transfer (Interrupt mode).
02001   * @param  huart UART handle.
02002   * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
02003   *         This procedure performs following operations :
02004   *           - Disable UART Interrupts (Tx)
02005   *           - Disable the DMA transfer in the peripheral register (if enabled)
02006   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
02007   *           - Set handle State to READY
02008   *           - At abort completion, call user abort complete callback
02009   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
02010   *         considered as completed only when user abort complete callback is executed (not when exiting function).
02011   * @retval HAL status
02012   */
02013 HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
02014 {
02015   /* Disable interrupts */
02016   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
02017   CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
02018
02019   /* Disable the UART DMA Tx request if enabled */
02020   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
02021   {
02022     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
02023
02024     /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
02025     if (huart->hdmatx != NULL)
02026     {
02027       /* Set the UART DMA Abort callback :
02028          will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
02029       huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
02030
02031       /* Abort DMA TX */
02032       if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
02033       {
02034         /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */
02035         huart->hdmatx->XferAbortCallback(huart->hdmatx);
02036       }
02037     }
02038     else
02039     {
02040       /* Reset Tx transfer counter */
02041       huart->TxXferCount = 0U;
02042
02043       /* Clear TxISR function pointers */
02044       huart->TxISR = NULL;
02045
02046       /* Restore huart->gState to Ready */
02047       huart->gState = HAL_UART_STATE_READY;
02048
02049       /* As no DMA to be aborted, call directly user Abort complete callback */
02050 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02051       /* Call registered Abort Transmit Complete Callback */
02052       huart->AbortTransmitCpltCallback(huart);
02053 #else
02054       /* Call legacy weak Abort Transmit Complete Callback */
02055       HAL_UART_AbortTransmitCpltCallback(huart);
02056 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02057     }
02058   }
02059   else
02060   {
02061     /* Reset Tx transfer counter */
02062     huart->TxXferCount = 0U;
02063
02064     /* Clear TxISR function pointers */
02065     huart->TxISR = NULL;
02066
02067     /* Flush the whole TX FIFO (if needed) */
02068     if (huart->FifoMode == UART_FIFOMODE_ENABLE)
02069     {
02070       __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
02071     }
02072
02073     /* Restore huart->gState to Ready */
02074     huart->gState = HAL_UART_STATE_READY;
02075
02076     /* As no DMA to be aborted, call directly user Abort complete callback */
02077 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02078     /* Call registered Abort Transmit Complete Callback */
02079     huart->AbortTransmitCpltCallback(huart);
02080 #else
02081     /* Call legacy weak Abort Transmit Complete Callback */
02082     HAL_UART_AbortTransmitCpltCallback(huart);
02083 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02084   }
02085
02086   return HAL_OK;
02087 }
02088
02089 /**
02090   * @brief  Abort ongoing Receive transfer (Interrupt mode).
02091   * @param  huart UART handle.
02092   * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
02093   *         This procedure performs following operations :
02094   *           - Disable UART Interrupts (Rx)
02095   *           - Disable the DMA transfer in the peripheral register (if enabled)
02096   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
02097   *           - Set handle State to READY
02098   *           - At abort completion, call user abort complete callback
02099   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
02100   *         considered as completed only when user abort complete callback is executed (not when exiting function).
02101   * @retval HAL status
02102   */
02103 HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
02104 {
02105   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
02106   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
02107   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
02108
02109   /* Disable the UART DMA Rx request if enabled */
02110   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
02111   {
02112     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
02113
02114     /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
02115     if (huart->hdmarx != NULL)
02116     {
02117       /* Set the UART DMA Abort callback :
02118          will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
02119       huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
02120
02121       /* Abort DMA RX */
02122       if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
02123       {
02124         /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
02125         huart->hdmarx->XferAbortCallback(huart->hdmarx);
02126       }
02127     }
02128     else
02129     {
02130       /* Reset Rx transfer counter */
02131       huart->RxXferCount = 0U;
02132
02133       /* Clear RxISR function pointer */
02134       huart->pRxBuffPtr = NULL;
02135
02136       /* Clear the Error flags in the ICR register */
02137       __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
02138
02139       /* Discard the received data */
02140       __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
02141
02142       /* Restore huart->RxState to Ready */
02143       huart->RxState = HAL_UART_STATE_READY;
02144
02145       /* As no DMA to be aborted, call directly user Abort complete callback */
02146 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02147       /* Call registered Abort Receive Complete Callback */
02148       huart->AbortReceiveCpltCallback(huart);
02149 #else
02150       /* Call legacy weak Abort Receive Complete Callback */
02151       HAL_UART_AbortReceiveCpltCallback(huart);
02152 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02153     }
02154   }
02155   else
02156   {
02157     /* Reset Rx transfer counter */
02158     huart->RxXferCount = 0U;
02159
02160     /* Clear RxISR function pointer */
02161     huart->pRxBuffPtr = NULL;
02162
02163     /* Clear the Error flags in the ICR register */
02164     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
02165
02166     /* Restore huart->RxState to Ready */
02167     huart->RxState = HAL_UART_STATE_READY;
02168
02169     /* As no DMA to be aborted, call directly user Abort complete callback */
02170 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02171     /* Call registered Abort Receive Complete Callback */
02172     huart->AbortReceiveCpltCallback(huart);
02173 #else
02174     /* Call legacy weak Abort Receive Complete Callback */
02175     HAL_UART_AbortReceiveCpltCallback(huart);
02176 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02177   }
02178
02179   return HAL_OK;
02180 }
02181
02182 /**
02183   * @brief Handle UART interrupt request.
02184   * @param huart UART handle.
02185   * @retval None
02186   */
02187 void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
02188 {
02189   uint32_t isrflags   = READ_REG(huart->Instance->ISR);
02190   uint32_t cr1its     = READ_REG(huart->Instance->CR1);
02191   uint32_t cr3its     = READ_REG(huart->Instance->CR3);
02192
02193   uint32_t errorflags;
02194   uint32_t errorcode;
02195
02196   /* If no error occurs */
02197   errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
02198   if (errorflags == 0U)
02199   {
02200     /* UART in mode Receiver ---------------------------------------------------*/
02201     if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
02202         && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
02203             || ((cr3its & USART_CR3_RXFTIE) != 0U)))
02204     {
02205       if (huart->RxISR != NULL)
02206       {
02207         huart->RxISR(huart);
02208       }
02209       return;
02210     }
02211   }
02212
02213   /* If some errors occur */
02214   if ((errorflags != 0U)
02215       && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
02216            || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))))
02217   {
02218     /* UART parity error interrupt occurred -------------------------------------*/
02219     if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
02220     {
02221       __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
02222
02223       huart->ErrorCode |= HAL_UART_ERROR_PE;
02224     }
02225
02226     /* UART frame error interrupt occurred --------------------------------------*/
02227     if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
02228     {
02229       __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
02230
02231       huart->ErrorCode |= HAL_UART_ERROR_FE;
02232     }
02233
02234     /* UART noise error interrupt occurred --------------------------------------*/
02235     if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
02236     {
02237       __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
02238
02239       huart->ErrorCode |= HAL_UART_ERROR_NE;
02240     }
02241
02242     /* UART Over-Run interrupt occurred -----------------------------------------*/
02243     if (((isrflags & USART_ISR_ORE) != 0U)
02244         && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
02245             ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
02246     {
02247       __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
02248
02249       huart->ErrorCode |= HAL_UART_ERROR_ORE;
02250     }
02251
02252     /* UART Receiver Timeout interrupt occurred ---------------------------------*/
02253     if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
02254     {
02255       __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
02256
02257       huart->ErrorCode |= HAL_UART_ERROR_RTO;
02258     }
02259
02260     /* Call UART Error Call back function if need be ----------------------------*/
02261     if (huart->ErrorCode != HAL_UART_ERROR_NONE)
02262     {
02263       /* UART in mode Receiver --------------------------------------------------*/
02264       if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
02265           && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
02266               || ((cr3its & USART_CR3_RXFTIE) != 0U)))
02267       {
02268         if (huart->RxISR != NULL)
02269         {
02270           huart->RxISR(huart);
02271         }
02272       }
02273
02274       /* If Error is to be considered as blocking :
02275           - Receiver Timeout error in Reception
02276           - Overrun error in Reception
02277           - any error occurs in DMA mode reception
02278       */
02279       errorcode = huart->ErrorCode;
02280       if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
02281           ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
02282       {
02283         /* Blocking error : transfer is aborted
02284            Set the UART state ready to be able to start again the process,
02285            Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
02286         UART_EndRxTransfer(huart);
02287
02288         /* Disable the UART DMA Rx request if enabled */
02289         if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
02290         {
02291           CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
02292
02293           /* Abort the UART DMA Rx channel */
02294           if (huart->hdmarx != NULL)
02295           {
02296             /* Set the UART DMA Abort callback :
02297                will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
02298             huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
02299
02300             /* Abort DMA RX */
02301             if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
02302             {
02303               /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
02304               huart->hdmarx->XferAbortCallback(huart->hdmarx);
02305             }
02306           }
02307           else
02308           {
02309             /* Call user error callback */
02310 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02311             /*Call registered error callback*/
02312             huart->ErrorCallback(huart);
02313 #else
02314             /*Call legacy weak error callback*/
02315             HAL_UART_ErrorCallback(huart);
02316 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02317
02318           }
02319         }
02320         else
02321         {
02322           /* Call user error callback */
02323 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02324           /*Call registered error callback*/
02325           huart->ErrorCallback(huart);
02326 #else
02327           /*Call legacy weak error callback*/
02328           HAL_UART_ErrorCallback(huart);
02329 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02330         }
02331       }
02332       else
02333       {
02334         /* Non Blocking error : transfer could go on.
02335            Error is notified to user through user error callback */
02336 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02337         /*Call registered error callback*/
02338         huart->ErrorCallback(huart);
02339 #else
02340         /*Call legacy weak error callback*/
02341         HAL_UART_ErrorCallback(huart);
02342 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02343         huart->ErrorCode = HAL_UART_ERROR_NONE;
02344       }
02345     }
02346     return;
02347
02348   } /* End if some error occurs */
02349
02350   /* UART wakeup from Stop mode interrupt occurred ---------------------------*/
02351   if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
02352   {
02353     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
02354
02355     /* UART Rx state is not reset as a reception process might be ongoing.
02356        If UART handle state fields need to be reset to READY, this could be done in Wakeup callback */
02357
02358 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02359     /* Call registered Wakeup Callback */
02360     huart->WakeupCallback(huart);
02361 #else
02362     /* Call legacy weak Wakeup Callback */
02363     HAL_UARTEx_WakeupCallback(huart);
02364 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02365     return;
02366   }
02367
02368   /* UART in mode Transmitter ------------------------------------------------*/
02369   if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
02370       && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
02371           || ((cr3its & USART_CR3_TXFTIE) != 0U)))
02372   {
02373     if (huart->TxISR != NULL)
02374     {
02375       huart->TxISR(huart);
02376     }
02377     return;
02378   }
02379
02380   /* UART in mode Transmitter (transmission end) -----------------------------*/
02381   if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
02382   {
02383     UART_EndTransmit_IT(huart);
02384     return;
02385   }
02386
02387   /* UART TX Fifo Empty occurred ----------------------------------------------*/
02388   if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
02389   {
02390 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02391     /* Call registered Tx Fifo Empty Callback */
02392     huart->TxFifoEmptyCallback(huart);
02393 #else
02394     /* Call legacy weak Tx Fifo Empty Callback */
02395     HAL_UARTEx_TxFifoEmptyCallback(huart);
02396 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02397     return;
02398   }
02399
02400   /* UART RX Fifo Full occurred ----------------------------------------------*/
02401   if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
02402   {
02403 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02404     /* Call registered Rx Fifo Full Callback */
02405     huart->RxFifoFullCallback(huart);
02406 #else
02407     /* Call legacy weak Rx Fifo Full Callback */
02408     HAL_UARTEx_RxFifoFullCallback(huart);
02409 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02410     return;
02411   }
02412 }
02413
02414 /**
02415   * @brief Tx Transfer completed callback.
02416   * @param huart UART handle.
02417   * @retval None
02418   */
02419 __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
02420 {
02421   /* Prevent unused argument(s) compilation warning */
02422   UNUSED(huart);
02423
02424   /* NOTE : This function should not be modified, when the callback is needed,
02425             the HAL_UART_TxCpltCallback can be implemented in the user file.
02426    */
02427 }
02428
02429 /**
02430   * @brief  Tx Half Transfer completed callback.
02431   * @param  huart UART handle.
02432   * @retval None
02433   */
02434 __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
02435 {
02436   /* Prevent unused argument(s) compilation warning */
02437   UNUSED(huart);
02438
02439   /* NOTE: This function should not be modified, when the callback is needed,
02440            the HAL_UART_TxHalfCpltCallback can be implemented in the user file.
02441    */
02442 }
02443
02444 /**
02445   * @brief  Rx Transfer completed callback.
02446   * @param  huart UART handle.
02447   * @retval None
02448   */
02449 __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
02450 {
02451   /* Prevent unused argument(s) compilation warning */
02452   UNUSED(huart);
02453
02454   /* NOTE : This function should not be modified, when the callback is needed,
02455             the HAL_UART_RxCpltCallback can be implemented in the user file.
02456    */
02457 }
02458
02459 /**
02460   * @brief  Rx Half Transfer completed callback.
02461   * @param  huart UART handle.
02462   * @retval None
02463   */
02464 __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
02465 {
02466   /* Prevent unused argument(s) compilation warning */
02467   UNUSED(huart);
02468
02469   /* NOTE: This function should not be modified, when the callback is needed,
02470            the HAL_UART_RxHalfCpltCallback can be implemented in the user file.
02471    */
02472 }
02473
02474 /**
02475   * @brief  UART error callback.
02476   * @param  huart UART handle.
02477   * @retval None
02478   */
02479 __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
02480 {
02481   /* Prevent unused argument(s) compilation warning */
02482   UNUSED(huart);
02483
02484   /* NOTE : This function should not be modified, when the callback is needed,
02485             the HAL_UART_ErrorCallback can be implemented in the user file.
02486    */
02487 }
02488
02489 /**
02490   * @brief  UART Abort Complete callback.
02491   * @param  huart UART handle.
02492   * @retval None
02493   */
02494 __weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart)
02495 {
02496   /* Prevent unused argument(s) compilation warning */
02497   UNUSED(huart);
02498
02499   /* NOTE : This function should not be modified, when the callback is needed,
02500             the HAL_UART_AbortCpltCallback can be implemented in the user file.
02501    */
02502 }
02503
02504 /**
02505   * @brief  UART Abort Complete callback.
02506   * @param  huart UART handle.
02507   * @retval None
02508   */
02509 __weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart)
02510 {
02511   /* Prevent unused argument(s) compilation warning */
02512   UNUSED(huart);
02513
02514   /* NOTE : This function should not be modified, when the callback is needed,
02515             the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.
02516    */
02517 }
02518
02519 /**
02520   * @brief  UART Abort Receive Complete callback.
02521   * @param  huart UART handle.
02522   * @retval None
02523   */
02524 __weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart)
02525 {
02526   /* Prevent unused argument(s) compilation warning */
02527   UNUSED(huart);
02528
02529   /* NOTE : This function should not be modified, when the callback is needed,
02530             the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.
02531    */
02532 }
02533
02534 /**
02535   * @}
02536   */
02537
02538 /** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
02539   *  @brief   UART control functions
02540   *
02541 @verbatim
02542  ===============================================================================
02543                       ##### Peripheral Control functions #####
02544  ===============================================================================
02545     [..]
02546     This subsection provides a set of functions allowing to control the UART.
02547      (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly
02548      (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature
02549      (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature
02550      (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
02551      (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
02552      (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
02553      (+) UART_SetConfig() API configures the UART peripheral
02554      (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features
02555      (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization
02556      (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
02557      (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
02558      (+) HAL_LIN_SendBreak() API transmits the break characters
02559 @endverbatim
02560   * @{
02561   */
02562
02563 /**
02564   * @brief  Update on the fly the receiver timeout value in RTOR register.
02565   * @param  huart Pointer to a UART_HandleTypeDef structure that contains
02566   *                    the configuration information for the specified UART module.
02567   * @param  TimeoutValue receiver timeout value in number of baud blocks. The timeout
02568   *                     value must be less or equal to 0x0FFFFFFFF.
02569   * @retval None
02570   */
02571 void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue)
02572 {
02573   if (!(IS_LPUART_INSTANCE(huart->Instance)))
02574   {
02575     assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue));
02576     MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue);
02577   }
02578 }
02579
02580 /**
02581   * @brief  Enable the UART receiver timeout feature.
02582   * @param  huart Pointer to a UART_HandleTypeDef structure that contains
02583   *                    the configuration information for the specified UART module.
02584   * @retval HAL status
02585   */
02586 HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart)
02587 {
02588   if (!(IS_LPUART_INSTANCE(huart->Instance)))
02589   {
02590     if (huart->gState == HAL_UART_STATE_READY)
02591     {
02592       /* Process Locked */
02593       __HAL_LOCK(huart);
02594
02595       huart->gState = HAL_UART_STATE_BUSY;
02596
02597       /* Set the USART RTOEN bit */
02598       SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
02599
02600       huart->gState = HAL_UART_STATE_READY;
02601
02602       /* Process Unlocked */
02603       __HAL_UNLOCK(huart);
02604
02605       return HAL_OK;
02606     }
02607     else
02608     {
02609       return HAL_BUSY;
02610     }
02611   }
02612   else
02613   {
02614     return HAL_ERROR;
02615   }
02616 }
02617
02618 /**
02619   * @brief  Disable the UART receiver timeout feature.
02620   * @param  huart Pointer to a UART_HandleTypeDef structure that contains
02621   *                    the configuration information for the specified UART module.
02622   * @retval HAL status
02623   */
02624 HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart)
02625 {
02626   if (!(IS_LPUART_INSTANCE(huart->Instance)))
02627   {
02628     if (huart->gState == HAL_UART_STATE_READY)
02629     {
02630       /* Process Locked */
02631       __HAL_LOCK(huart);
02632
02633       huart->gState = HAL_UART_STATE_BUSY;
02634
02635       /* Clear the USART RTOEN bit */
02636       CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
02637
02638       huart->gState = HAL_UART_STATE_READY;
02639
02640       /* Process Unlocked */
02641       __HAL_UNLOCK(huart);
02642
02643       return HAL_OK;
02644     }
02645     else
02646     {
02647       return HAL_BUSY;
02648     }
02649   }
02650   else
02651   {
02652     return HAL_ERROR;
02653   }
02654 }
02655
02656 /**
02657   * @brief  Enable UART in mute mode (does not mean UART enters mute mode;
02658   *         to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
02659   * @param  huart UART handle.
02660   * @retval HAL status
02661   */
02662 HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
02663 {
02664   __HAL_LOCK(huart);
02665
02666   huart->gState = HAL_UART_STATE_BUSY;
02667
02668   /* Enable USART mute mode by setting the MME bit in the CR1 register */
02669   SET_BIT(huart->Instance->CR1, USART_CR1_MME);
02670
02671   huart->gState = HAL_UART_STATE_READY;
02672
02673   return (UART_CheckIdleState(huart));
02674 }
02675
02676 /**
02677   * @brief  Disable UART mute mode (does not mean the UART actually exits mute mode
02678   *         as it may not have been in mute mode at this very moment).
02679   * @param  huart UART handle.
02680   * @retval HAL status
02681   */
02682 HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
02683 {
02684   __HAL_LOCK(huart);
02685
02686   huart->gState = HAL_UART_STATE_BUSY;
02687
02688   /* Disable USART mute mode by clearing the MME bit in the CR1 register */
02689   CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
02690
02691   huart->gState = HAL_UART_STATE_READY;
02692
02693   return (UART_CheckIdleState(huart));
02694 }
02695
02696 /**
02697   * @brief Enter UART mute mode (means UART actually enters mute mode).
02698   * @note  To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
02699   * @param huart UART handle.
02700   * @retval None
02701   */
02702 void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
02703 {
02704   __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);
02705 }
02706
02707 /**
02708   * @brief  Enable the UART transmitter and disable the UART receiver.
02709   * @param  huart UART handle.
02710   * @retval HAL status
02711   */
02712 HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
02713 {
02714   __HAL_LOCK(huart);
02715   huart->gState = HAL_UART_STATE_BUSY;
02716
02717   /* Clear TE and RE bits */
02718   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
02719
02720   /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
02721   SET_BIT(huart->Instance->CR1, USART_CR1_TE);
02722
02723   huart->gState = HAL_UART_STATE_READY;
02724
02725   __HAL_UNLOCK(huart);
02726
02727   return HAL_OK;
02728 }
02729
02730 /**
02731   * @brief  Enable the UART receiver and disable the UART transmitter.
02732   * @param  huart UART handle.
02733   * @retval HAL status.
02734   */
02735 HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
02736 {
02737   __HAL_LOCK(huart);
02738   huart->gState = HAL_UART_STATE_BUSY;
02739
02740   /* Clear TE and RE bits */
02741   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
02742
02743   /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
02744   SET_BIT(huart->Instance->CR1, USART_CR1_RE);
02745
02746   huart->gState = HAL_UART_STATE_READY;
02747
02748   __HAL_UNLOCK(huart);
02749
02750   return HAL_OK;
02751 }
02752
02753
02754 /**
02755   * @brief  Transmit break characters.
02756   * @param  huart UART handle.
02757   * @retval HAL status
02758   */
02759 HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
02760 {
02761   /* Check the parameters */
02762   assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
02763
02764   __HAL_LOCK(huart);
02765
02766   huart->gState = HAL_UART_STATE_BUSY;
02767
02768   /* Send break characters */
02769   __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST);
02770
02771   huart->gState = HAL_UART_STATE_READY;
02772
02773   __HAL_UNLOCK(huart);
02774
02775   return HAL_OK;
02776 }
02777
02778 /**
02779   * @}
02780   */
02781
02782 /** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions
02783   *  @brief   UART Peripheral State functions
02784   *
02785 @verbatim
02786   ==============================================================================
02787             ##### Peripheral State and Error functions #####
02788   ==============================================================================
02789     [..]
02790     This subsection provides functions allowing to :
02791       (+) Return the UART handle state.
02792       (+) Return the UART handle error code
02793
02794 @endverbatim
02795   * @{
02796   */
02797
02798 /**
02799   * @brief Return the UART handle state.
02800   * @param  huart Pointer to a UART_HandleTypeDef structure that contains
02801   *               the configuration information for the specified UART.
02802   * @retval HAL state
02803   */
02804 HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
02805 {
02806   uint32_t temp1;
02807   uint32_t temp2;
02808   temp1 = huart->gState;
02809   temp2 = huart->RxState;
02810
02811   return (HAL_UART_StateTypeDef)(temp1 | temp2);
02812 }
02813
02814 /**
02815   * @brief  Return the UART handle error code.
02816   * @param  huart Pointer to a UART_HandleTypeDef structure that contains
02817   *               the configuration information for the specified UART.
02818   * @retval UART Error Code
02819   */
02820 uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
02821 {
02822   return huart->ErrorCode;
02823 }
02824 /**
02825   * @}
02826   */
02827
02828 /**
02829   * @}
02830   */
02831
02832 /** @defgroup UART_Private_Functions UART Private Functions
02833   * @{
02834   */
02835
02836 /**
02837   * @brief  Initialize the callbacks to their default values.
02838   * @param  huart UART handle.
02839   * @retval none
02840   */
02841 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
02842 void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart)
02843 {
02844   /* Init the UART Callback settings */
02845   huart->TxHalfCpltCallback        = HAL_UART_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback        */
02846   huart->TxCpltCallback            = HAL_UART_TxCpltCallback;            /* Legacy weak TxCpltCallback            */
02847   huart->RxHalfCpltCallback        = HAL_UART_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback        */
02848   huart->RxCpltCallback            = HAL_UART_RxCpltCallback;            /* Legacy weak RxCpltCallback            */
02849   huart->ErrorCallback             = HAL_UART_ErrorCallback;             /* Legacy weak ErrorCallback             */
02850   huart->AbortCpltCallback         = HAL_UART_AbortCpltCallback;         /* Legacy weak AbortCpltCallback         */
02851   huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
02852   huart->AbortReceiveCpltCallback  = HAL_UART_AbortReceiveCpltCallback;  /* Legacy weak AbortReceiveCpltCallback  */
02853   huart->WakeupCallback            = HAL_UARTEx_WakeupCallback;          /* Legacy weak WakeupCallback            */
02854   huart->RxFifoFullCallback        = HAL_UARTEx_RxFifoFullCallback;      /* Legacy weak RxFifoFullCallback        */
02855   huart->TxFifoEmptyCallback       = HAL_UARTEx_TxFifoEmptyCallback;     /* Legacy weak TxFifoEmptyCallback       */
02856
02857 }
02858 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
02859
02860 /**
02861   * @brief Configure the UART peripheral.
02862   * @param huart UART handle.
02863   * @retval HAL status
02864   */
02865 HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
02866 {
02867   uint32_t tmpreg;
02868   uint16_t brrtemp;
02869   UART_ClockSourceTypeDef clocksource;
02870   uint32_t usartdiv                   = 0x00000000U;
02871   HAL_StatusTypeDef ret               = HAL_OK;
02872 #if defined(LPUART1)
02873   uint32_t lpuart_ker_ck_pres         = 0x00000000U;
02874 #endif
02875   uint32_t pclk;
02876
02877   /* Check the parameters */
02878   assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
02879   assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
02880 #if defined(LPUART1)
02881   if (UART_INSTANCE_LOWPOWER(huart))
02882   {
02883     assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits));
02884   }
02885   else
02886   {
02887     assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
02888     assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
02889   }
02890 #else
02891   assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
02892   assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
02893 #endif
02894
02895   assert_param(IS_UART_PARITY(huart->Init.Parity));
02896   assert_param(IS_UART_MODE(huart->Init.Mode));
02897   assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
02898   assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
02899   assert_param(IS_UART_PRESCALER(huart->Init.ClockPrescaler));
02900
02901   /*-------------------------- USART CR1 Configuration -----------------------*/
02902   /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
02903   *  the UART Word Length, Parity, Mode and oversampling:
02904   *  set the M bits according to huart->Init.WordLength value
02905   *  set PCE and PS bits according to huart->Init.Parity value
02906   *  set TE and RE bits according to huart->Init.Mode value
02907   *  set OVER8 bit according to huart->Init.OverSampling value */
02908   tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
02909   tmpreg |= (uint32_t)huart->FifoMode;
02910   MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
02911
02912   /*-------------------------- USART CR2 Configuration -----------------------*/
02913   /* Configure the UART Stop Bits: Set STOP[13:12] bits according
02914   * to huart->Init.StopBits value */
02915   MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
02916
02917   /*-------------------------- USART CR3 Configuration -----------------------*/
02918   /* Configure
02919   * - UART HardWare Flow Control: set CTSE and RTSE bits according
02920   *   to huart->Init.HwFlowCtl value
02921   * - one-bit sampling method versus three samples' majority rule according
02922   *   to huart->Init.OneBitSampling (not applicable to LPUART) */
02923   tmpreg = (uint32_t)huart->Init.HwFlowCtl;
02924
02925 #if defined(LPUART1)
02926   if (!(UART_INSTANCE_LOWPOWER(huart)))
02927   {
02928     tmpreg |= huart->Init.OneBitSampling;
02929   }
02930 #else
02931   tmpreg |= huart->Init.OneBitSampling;
02932 #endif
02933   MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
02934
02935   /*-------------------------- USART PRESC Configuration -----------------------*/
02936   /* Configure
02937   * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
02938   MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
02939
02940   /*-------------------------- USART BRR Configuration -----------------------*/
02941   UART_GETCLOCKSOURCE(huart, clocksource);
02942
02943 #if defined(LPUART1)
02944   /* Check LPUART instance */
02945   if (UART_INSTANCE_LOWPOWER(huart))
02946   {
02947     /* Retrieve frequency clock */
02948     switch (clocksource)
02949     {
02950       case UART_CLOCKSOURCE_PCLK1:
02951         lpuart_ker_ck_pres = (HAL_RCC_GetPCLK1Freq() / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
02952         break;
02953       case UART_CLOCKSOURCE_HSI:
02954         lpuart_ker_ck_pres = ((uint32_t)HSI_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
02955         break;
02956       case UART_CLOCKSOURCE_SYSCLK:
02957         lpuart_ker_ck_pres = (HAL_RCC_GetSysClockFreq() / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
02958         break;
02959       case UART_CLOCKSOURCE_LSE:
02960         lpuart_ker_ck_pres = ((uint32_t)LSE_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
02961         break;
02962       default:
02963         ret = HAL_ERROR;
02964         break;
02965     }
02966
02967     /* if proper clock source reported */
02968     if (lpuart_ker_ck_pres != 0U)
02969     {
02970       /* ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
02971       if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
02972           (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate)))
02973       {
02974         ret = HAL_ERROR;
02975       }
02976       else
02977       {
02978         switch (clocksource)
02979         {
02980           case UART_CLOCKSOURCE_PCLK1:
02981             pclk = HAL_RCC_GetPCLK1Freq();
02982             usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
02983             break;
02984           case UART_CLOCKSOURCE_HSI:
02985             usartdiv = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
02986             break;
02987           case UART_CLOCKSOURCE_SYSCLK:
02988             pclk = HAL_RCC_GetSysClockFreq();
02989             usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
02990             break;
02991           case UART_CLOCKSOURCE_LSE:
02992             usartdiv = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
02993             break;
02994           default:
02995             ret = HAL_ERROR;
02996             break;
02997         }
02998
02999         /* It is forbidden to write values lower than 0x300 in the LPUART_BRR register */
03000         if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
03001         {
03002           huart->Instance->BRR = usartdiv;
03003         }
03004         else
03005         {
03006           ret = HAL_ERROR;
03007         }
03008       } /*   if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
03009     } /* if (lpuart_ker_ck_pres != 0) */
03010   }
03011   /* Check UART Over Sampling to set Baud Rate Register */
03012   else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
03013 #else
03014   if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
03015 #endif /* LPUART1 */
03016   {
03017     switch (clocksource)
03018     {
03019       case UART_CLOCKSOURCE_PCLK2:
03020         pclk = HAL_RCC_GetPCLK2Freq();
03021         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
03022         break;
03023       case UART_CLOCKSOURCE_HSI:
03024         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
03025         break;
03026       case UART_CLOCKSOURCE_SYSCLK:
03027         pclk = HAL_RCC_GetSysClockFreq();
03028         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
03029         break;
03030       case UART_CLOCKSOURCE_LSE:
03031         usartdiv = (uint16_t)(UART_DIV_SAMPLING8((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
03032         break;
03033       default:
03034         ret = HAL_ERROR;
03035         break;
03036     }
03037
03038     /* USARTDIV must be greater than or equal to 0d16 */
03039     if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
03040     {
03041       brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
03042       brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
03043       huart->Instance->BRR = brrtemp;
03044     }
03045     else
03046     {
03047       ret = HAL_ERROR;
03048     }
03049   }
03050   else
03051   {
03052     switch (clocksource)
03053     {
03054       case UART_CLOCKSOURCE_PCLK2:
03055         pclk = HAL_RCC_GetPCLK2Freq();
03056         usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
03057         break;
03058       case UART_CLOCKSOURCE_HSI:
03059         usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
03060         break;
03061       case UART_CLOCKSOURCE_SYSCLK:
03062         pclk = HAL_RCC_GetSysClockFreq();
03063         usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
03064         break;
03065       case UART_CLOCKSOURCE_LSE:
03066         usartdiv = (uint16_t)(UART_DIV_SAMPLING16((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
03067         break;
03068       default:
03069         ret = HAL_ERROR;
03070         break;
03071     }
03072
03073     /* USARTDIV must be greater than or equal to 0d16 */
03074     if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
03075     {
03076       huart->Instance->BRR = usartdiv;
03077     }
03078     else
03079     {
03080       ret = HAL_ERROR;
03081     }
03082   }
03083
03084   /* Initialize the number of data to process during RX/TX ISR execution */
03085   huart->NbTxDataToProcess = 1;
03086   huart->NbRxDataToProcess = 1;
03087
03088   /* Clear ISR function pointers */
03089   huart->RxISR = NULL;
03090   huart->TxISR = NULL;
03091
03092   return ret;
03093 }
03094
03095 /**
03096   * @brief Configure the UART peripheral advanced features.
03097   * @param huart UART handle.
03098   * @retval None
03099   */
03100 void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
03101 {
03102   /* Check whether the set of advanced features to configure is properly set */
03103   assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
03104
03105   /* if required, configure TX pin active level inversion */
03106   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
03107   {
03108     assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
03109     MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
03110   }
03111
03112   /* if required, configure RX pin active level inversion */
03113   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
03114   {
03115     assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
03116     MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
03117   }
03118
03119   /* if required, configure data inversion */
03120   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
03121   {
03122     assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
03123     MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
03124   }
03125
03126   /* if required, configure RX/TX pins swap */
03127   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
03128   {
03129     assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
03130     MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
03131   }
03132
03133   /* if required, configure RX overrun detection disabling */
03134   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
03135   {
03136     assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
03137     MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
03138   }
03139
03140   /* if required, configure DMA disabling on reception error */
03141   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
03142   {
03143     assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
03144     MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
03145   }
03146
03147   /* if required, configure auto Baud rate detection scheme */
03148   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
03149   {
03150     assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
03151     assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
03152     MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
03153     /* set auto Baudrate detection parameters if detection is enabled */
03154     if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
03155     {
03156       assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
03157       MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
03158     }
03159   }
03160
03161   /* if required, configure MSB first on communication line */
03162   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
03163   {
03164     assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
03165     MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
03166   }
03167 }
03168
03169 /**
03170   * @brief Check the UART Idle State.
03171   * @param huart UART handle.
03172   * @retval HAL status
03173   */
03174 HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
03175 {
03176   uint32_t tickstart;
03177
03178   /* Initialize the UART ErrorCode */
03179   huart->ErrorCode = HAL_UART_ERROR_NONE;
03180
03181   /* Init tickstart for timeout managment*/
03182   tickstart = HAL_GetTick();
03183
03184   /* Check if the Transmitter is enabled */
03185   if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
03186   {
03187     /* Wait until TEACK flag is set */
03188     if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
03189     {
03190       /* Timeout occurred */
03191       return HAL_TIMEOUT;
03192     }
03193   }
03194
03195   /* Check if the Receiver is enabled */
03196   if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
03197   {
03198     /* Wait until REACK flag is set */
03199     if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
03200     {
03201       /* Timeout occurred */
03202       return HAL_TIMEOUT;
03203     }
03204   }
03205
03206   /* Initialize the UART State */
03207   huart->gState = HAL_UART_STATE_READY;
03208   huart->RxState = HAL_UART_STATE_READY;
03209
03210   __HAL_UNLOCK(huart);
03211
03212   return HAL_OK;
03213 }
03214
03215 /**
03216   * @brief  Handle UART Communication Timeout.
03217   * @param huart     UART handle.
03218   * @param Flag      Specifies the UART flag to check
03219   * @param Status    Flag status (SET or RESET)
03220   * @param Tickstart Tick start value
03221   * @param Timeout   Timeout duration
03222   * @retval HAL status
03223   */
03224 HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
03225                                               uint32_t Tickstart, uint32_t Timeout)
03226 {
03227   /* Wait until flag is set */
03228   while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
03229   {
03230     /* Check for the Timeout */
03231     if (Timeout != HAL_MAX_DELAY)
03232     {
03233       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
03234       {
03235         /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
03236         CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
03237         CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
03238
03239         huart->gState = HAL_UART_STATE_READY;
03240         huart->RxState = HAL_UART_STATE_READY;
03241
03242         __HAL_UNLOCK(huart);
03243
03244         return HAL_TIMEOUT;
03245       }
03246
03247       if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
03248       {
03249         if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
03250         {
03251           /* Clear Receiver Timeout flag*/
03252           __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
03253
03254           /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
03255           CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
03256           CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
03257
03258           huart->gState = HAL_UART_STATE_READY;
03259           huart->RxState = HAL_UART_STATE_READY;
03260           huart->ErrorCode = HAL_UART_ERROR_RTO;
03261
03262           /* Process Unlocked */
03263           __HAL_UNLOCK(huart);
03264
03265           return HAL_TIMEOUT;
03266         }
03267       }
03268     }
03269   }
03270   return HAL_OK;
03271 }
03272
03273
03274 /**
03275   * @brief  End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
03276   * @param  huart UART handle.
03277   * @retval None
03278   */
03279 static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
03280 {
03281   /* Disable TXEIE, TCIE, TXFT interrupts */
03282   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
03283   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE));
03284
03285   /* At end of Tx process, restore huart->gState to Ready */
03286   huart->gState = HAL_UART_STATE_READY;
03287 }
03288
03289
03290 /**
03291   * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
03292   * @param  huart UART handle.
03293   * @retval None
03294   */
03295 static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
03296 {
03297   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
03298   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
03299   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
03300
03301   /* At end of Rx process, restore huart->RxState to Ready */
03302   huart->RxState = HAL_UART_STATE_READY;
03303
03304   /* Reset RxIsr function pointer */
03305   huart->RxISR = NULL;
03306 }
03307
03308
03309 /**
03310   * @brief DMA UART transmit process complete callback.
03311   * @param hdma DMA handle.
03312   * @retval None
03313   */
03314 static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
03315 {
03316   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
03317
03318   /* DMA Normal mode */
03319   if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
03320   {
03321     huart->TxXferCount = 0U;
03322
03323     /* Disable the DMA transfer for transmit request by resetting the DMAT bit
03324        in the UART CR3 register */
03325     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
03326
03327     /* Enable the UART Transmit Complete Interrupt */
03328     SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
03329   }
03330   /* DMA Circular mode */
03331   else
03332   {
03333 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03334     /*Call registered Tx complete callback*/
03335     huart->TxCpltCallback(huart);
03336 #else
03337     /*Call legacy weak Tx complete callback*/
03338     HAL_UART_TxCpltCallback(huart);
03339 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03340   }
03341 }
03342
03343 /**
03344   * @brief DMA UART transmit process half complete callback.
03345   * @param hdma DMA handle.
03346   * @retval None
03347   */
03348 static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
03349 {
03350   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
03351
03352 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03353   /*Call registered Tx Half complete callback*/
03354   huart->TxHalfCpltCallback(huart);
03355 #else
03356   /*Call legacy weak Tx Half complete callback*/
03357   HAL_UART_TxHalfCpltCallback(huart);
03358 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03359 }
03360
03361 /**
03362   * @brief DMA UART receive process complete callback.
03363   * @param hdma DMA handle.
03364   * @retval None
03365   */
03366 static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
03367 {
03368   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
03369
03370   /* DMA Normal mode */
03371   if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
03372   {
03373     huart->RxXferCount = 0U;
03374
03375     /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
03376     CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
03377     CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
03378
03379     /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
03380        in the UART CR3 register */
03381     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
03382
03383     /* At end of Rx process, restore huart->RxState to Ready */
03384     huart->RxState = HAL_UART_STATE_READY;
03385   }
03386
03387 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03388   /*Call registered Rx complete callback*/
03389   huart->RxCpltCallback(huart);
03390 #else
03391   /*Call legacy weak Rx complete callback*/
03392   HAL_UART_RxCpltCallback(huart);
03393 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03394 }
03395
03396 /**
03397   * @brief DMA UART receive process half complete callback.
03398   * @param hdma DMA handle.
03399   * @retval None
03400   */
03401 static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
03402 {
03403   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
03404
03405 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03406   /*Call registered Rx Half complete callback*/
03407   huart->RxHalfCpltCallback(huart);
03408 #else
03409   /*Call legacy weak Rx Half complete callback*/
03410   HAL_UART_RxHalfCpltCallback(huart);
03411 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03412 }
03413
03414 /**
03415   * @brief DMA UART communication error callback.
03416   * @param hdma DMA handle.
03417   * @retval None
03418   */
03419 static void UART_DMAError(DMA_HandleTypeDef *hdma)
03420 {
03421   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
03422
03423   const HAL_UART_StateTypeDef gstate = huart->gState;
03424   const HAL_UART_StateTypeDef rxstate = huart->RxState;
03425
03426   /* Stop UART DMA Tx request if ongoing */
03427   if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
03428       (gstate == HAL_UART_STATE_BUSY_TX))
03429   {
03430     huart->TxXferCount = 0U;
03431     UART_EndTxTransfer(huart);
03432   }
03433
03434   /* Stop UART DMA Rx request if ongoing */
03435   if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
03436       (rxstate == HAL_UART_STATE_BUSY_RX))
03437   {
03438     huart->RxXferCount = 0U;
03439     UART_EndRxTransfer(huart);
03440   }
03441
03442   huart->ErrorCode |= HAL_UART_ERROR_DMA;
03443
03444 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03445   /*Call registered error callback*/
03446   huart->ErrorCallback(huart);
03447 #else
03448   /*Call legacy weak error callback*/
03449   HAL_UART_ErrorCallback(huart);
03450 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03451 }
03452
03453 /**
03454   * @brief  DMA UART communication abort callback, when initiated by HAL services on Error
03455   *         (To be called at end of DMA Abort procedure following error occurrence).
03456   * @param  hdma DMA handle.
03457   * @retval None
03458   */
03459 static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
03460 {
03461   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
03462   huart->RxXferCount = 0U;
03463   huart->TxXferCount = 0U;
03464
03465 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03466   /*Call registered error callback*/
03467   huart->ErrorCallback(huart);
03468 #else
03469   /*Call legacy weak error callback*/
03470   HAL_UART_ErrorCallback(huart);
03471 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03472 }
03473
03474 /**
03475   * @brief  DMA UART Tx communication abort callback, when initiated by user
03476   *         (To be called at end of DMA Tx Abort procedure following user abort request).
03477   * @note   When this callback is executed, User Abort complete call back is called only if no
03478   *         Abort still ongoing for Rx DMA Handle.
03479   * @param  hdma DMA handle.
03480   * @retval None
03481   */
03482 static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
03483 {
03484   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
03485
03486   huart->hdmatx->XferAbortCallback = NULL;
03487
03488   /* Check if an Abort process is still ongoing */
03489   if (huart->hdmarx != NULL)
03490   {
03491     if (huart->hdmarx->XferAbortCallback != NULL)
03492     {
03493       return;
03494     }
03495   }
03496
03497   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
03498   huart->TxXferCount = 0U;
03499   huart->RxXferCount = 0U;
03500
03501   /* Reset errorCode */
03502   huart->ErrorCode = HAL_UART_ERROR_NONE;
03503
03504   /* Clear the Error flags in the ICR register */
03505   __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
03506
03507   /* Flush the whole TX FIFO (if needed) */
03508   if (huart->FifoMode == UART_FIFOMODE_ENABLE)
03509   {
03510     __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
03511   }
03512
03513   /* Restore huart->gState and huart->RxState to Ready */
03514   huart->gState  = HAL_UART_STATE_READY;
03515   huart->RxState = HAL_UART_STATE_READY;
03516
03517   /* Call user Abort complete callback */
03518 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03519   /* Call registered Abort complete callback */
03520   huart->AbortCpltCallback(huart);
03521 #else
03522   /* Call legacy weak Abort complete callback */
03523   HAL_UART_AbortCpltCallback(huart);
03524 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03525 }
03526
03527
03528 /**
03529   * @brief  DMA UART Rx communication abort callback, when initiated by user
03530   *         (To be called at end of DMA Rx Abort procedure following user abort request).
03531   * @note   When this callback is executed, User Abort complete call back is called only if no
03532   *         Abort still ongoing for Tx DMA Handle.
03533   * @param  hdma DMA handle.
03534   * @retval None
03535   */
03536 static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
03537 {
03538   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
03539
03540   huart->hdmarx->XferAbortCallback = NULL;
03541
03542   /* Check if an Abort process is still ongoing */
03543   if (huart->hdmatx != NULL)
03544   {
03545     if (huart->hdmatx->XferAbortCallback != NULL)
03546     {
03547       return;
03548     }
03549   }
03550
03551   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
03552   huart->TxXferCount = 0U;
03553   huart->RxXferCount = 0U;
03554
03555   /* Reset errorCode */
03556   huart->ErrorCode = HAL_UART_ERROR_NONE;
03557
03558   /* Clear the Error flags in the ICR register */
03559   __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
03560
03561   /* Discard the received data */
03562   __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
03563
03564   /* Restore huart->gState and huart->RxState to Ready */
03565   huart->gState  = HAL_UART_STATE_READY;
03566   huart->RxState = HAL_UART_STATE_READY;
03567
03568   /* Call user Abort complete callback */
03569 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03570   /* Call registered Abort complete callback */
03571   huart->AbortCpltCallback(huart);
03572 #else
03573   /* Call legacy weak Abort complete callback */
03574   HAL_UART_AbortCpltCallback(huart);
03575 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03576 }
03577
03578
03579 /**
03580   * @brief  DMA UART Tx communication abort callback, when initiated by user by a call to
03581   *         HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)
03582   *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
03583   *         and leads to user Tx Abort Complete callback execution).
03584   * @param  hdma DMA handle.
03585   * @retval None
03586   */
03587 static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
03588 {
03589   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
03590
03591   huart->TxXferCount = 0U;
03592
03593   /* Flush the whole TX FIFO (if needed) */
03594   if (huart->FifoMode == UART_FIFOMODE_ENABLE)
03595   {
03596     __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
03597   }
03598
03599   /* Restore huart->gState to Ready */
03600   huart->gState = HAL_UART_STATE_READY;
03601
03602   /* Call user Abort complete callback */
03603 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03604   /* Call registered Abort Transmit Complete Callback */
03605   huart->AbortTransmitCpltCallback(huart);
03606 #else
03607   /* Call legacy weak Abort Transmit Complete Callback */
03608   HAL_UART_AbortTransmitCpltCallback(huart);
03609 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03610 }
03611
03612 /**
03613   * @brief  DMA UART Rx communication abort callback, when initiated by user by a call to
03614   *         HAL_UART_AbortReceive_IT API (Abort only Rx transfer)
03615   *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
03616   *         and leads to user Rx Abort Complete callback execution).
03617   * @param  hdma DMA handle.
03618   * @retval None
03619   */
03620 static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
03621 {
03622   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
03623
03624   huart->RxXferCount = 0U;
03625
03626   /* Clear the Error flags in the ICR register */
03627   __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
03628
03629   /* Discard the received data */
03630   __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
03631
03632   /* Restore huart->RxState to Ready */
03633   huart->RxState = HAL_UART_STATE_READY;
03634
03635   /* Call user Abort complete callback */
03636 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03637   /* Call registered Abort Receive Complete Callback */
03638   huart->AbortReceiveCpltCallback(huart);
03639 #else
03640   /* Call legacy weak Abort Receive Complete Callback */
03641   HAL_UART_AbortReceiveCpltCallback(huart);
03642 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03643 }
03644
03645 /**
03646   * @brief TX interrrupt handler for 7 or 8 bits data word length .
03647   * @note   Function is called under interruption only, once
03648   *         interruptions have been enabled by HAL_UART_Transmit_IT().
03649   * @param huart UART handle.
03650   * @retval None
03651   */
03652 static void UART_TxISR_8BIT(UART_HandleTypeDef *huart)
03653 {
03654   /* Check that a Tx process is ongoing */
03655   if (huart->gState == HAL_UART_STATE_BUSY_TX)
03656   {
03657     if (huart->TxXferCount == 0U)
03658     {
03659       /* Disable the UART Transmit Data Register Empty Interrupt */
03660       CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
03661
03662       /* Enable the UART Transmit Complete Interrupt */
03663       SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
03664     }
03665     else
03666     {
03667       huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
03668       huart->pTxBuffPtr++;
03669       huart->TxXferCount--;
03670     }
03671   }
03672 }
03673
03674 /**
03675   * @brief TX interrrupt handler for 9 bits data word length.
03676   * @note   Function is called under interruption only, once
03677   *         interruptions have been enabled by HAL_UART_Transmit_IT().
03678   * @param huart UART handle.
03679   * @retval None
03680   */
03681 static void UART_TxISR_16BIT(UART_HandleTypeDef *huart)
03682 {
03683   uint16_t *tmp;
03684
03685   /* Check that a Tx process is ongoing */
03686   if (huart->gState == HAL_UART_STATE_BUSY_TX)
03687   {
03688     if (huart->TxXferCount == 0U)
03689     {
03690       /* Disable the UART Transmit Data Register Empty Interrupt */
03691       CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
03692
03693       /* Enable the UART Transmit Complete Interrupt */
03694       SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
03695     }
03696     else
03697     {
03698       tmp = (uint16_t *) huart->pTxBuffPtr;
03699       huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
03700       huart->pTxBuffPtr += 2U;
03701       huart->TxXferCount--;
03702     }
03703   }
03704 }
03705
03706 /**
03707   * @brief TX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
03708   * @note   Function is called under interruption only, once
03709   *         interruptions have been enabled by HAL_UART_Transmit_IT().
03710   * @param huart UART handle.
03711   * @retval None
03712   */
03713 static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
03714 {
03715   uint16_t  nb_tx_data;
03716
03717   /* Check that a Tx process is ongoing */
03718   if (huart->gState == HAL_UART_STATE_BUSY_TX)
03719   {
03720     for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
03721     {
03722       if (huart->TxXferCount == 0U)
03723       {
03724         /* Disable the TX FIFO threshold interrupt */
03725         CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
03726
03727         /* Enable the UART Transmit Complete Interrupt */
03728         SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
03729
03730         break; /* force exit loop */
03731       }
03732       else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
03733       {
03734         huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
03735         huart->pTxBuffPtr++;
03736         huart->TxXferCount--;
03737       }
03738       else
03739       {
03740         /* Nothing to do */
03741       }
03742     }
03743   }
03744 }
03745
03746 /**
03747   * @brief TX interrrupt handler for 9 bits data word length and FIFO mode is enabled.
03748   * @note   Function is called under interruption only, once
03749   *         interruptions have been enabled by HAL_UART_Transmit_IT().
03750   * @param huart UART handle.
03751   * @retval None
03752   */
03753 static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
03754 {
03755   uint16_t *tmp;
03756   uint16_t  nb_tx_data;
03757
03758   /* Check that a Tx process is ongoing */
03759   if (huart->gState == HAL_UART_STATE_BUSY_TX)
03760   {
03761     for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
03762     {
03763       if (huart->TxXferCount == 0U)
03764       {
03765         /* Disable the TX FIFO threshold interrupt */
03766         CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
03767
03768         /* Enable the UART Transmit Complete Interrupt */
03769         SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
03770
03771         break; /* force exit loop */
03772       }
03773       else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
03774       {
03775         tmp = (uint16_t *) huart->pTxBuffPtr;
03776         huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
03777         huart->pTxBuffPtr += 2U;
03778         huart->TxXferCount--;
03779       }
03780       else
03781       {
03782         /* Nothing to do */
03783       }
03784     }
03785   }
03786 }
03787
03788 /**
03789   * @brief  Wrap up transmission in non-blocking mode.
03790   * @param  huart pointer to a UART_HandleTypeDef structure that contains
03791   *                the configuration information for the specified UART module.
03792   * @retval None
03793   */
03794 static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
03795 {
03796   /* Disable the UART Transmit Complete Interrupt */
03797   CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
03798
03799   /* Tx process is ended, restore huart->gState to Ready */
03800   huart->gState = HAL_UART_STATE_READY;
03801
03802   /* Cleat TxISR function pointer */
03803   huart->TxISR = NULL;
03804
03805 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03806   /*Call registered Tx complete callback*/
03807   huart->TxCpltCallback(huart);
03808 #else
03809   /*Call legacy weak Tx complete callback*/
03810   HAL_UART_TxCpltCallback(huart);
03811 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03812 }
03813
03814 /**
03815   * @brief RX interrrupt handler for 7 or 8 bits data word length .
03816   * @param huart UART handle.
03817   * @retval None
03818   */
03819 static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
03820 {
03821   uint16_t uhMask = huart->Mask;
03822   uint16_t  uhdata;
03823
03824   /* Check that a Rx process is ongoing */
03825   if (huart->RxState == HAL_UART_STATE_BUSY_RX)
03826   {
03827     uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
03828     *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
03829     huart->pRxBuffPtr++;
03830     huart->RxXferCount--;
03831
03832     if (huart->RxXferCount == 0U)
03833     {
03834       /* Disable the UART Parity Error Interrupt and RXNE interrupts */
03835       CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
03836
03837       /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
03838       CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
03839
03840       /* Rx process is completed, restore huart->RxState to Ready */
03841       huart->RxState = HAL_UART_STATE_READY;
03842
03843       /* Clear RxISR function pointer */
03844       huart->RxISR = NULL;
03845
03846 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03847       /*Call registered Rx complete callback*/
03848       huart->RxCpltCallback(huart);
03849 #else
03850       /*Call legacy weak Rx complete callback*/
03851       HAL_UART_RxCpltCallback(huart);
03852 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03853     }
03854   }
03855   else
03856   {
03857     /* Clear RXNE interrupt flag */
03858     __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
03859   }
03860 }
03861
03862 /**
03863   * @brief RX interrrupt handler for 9 bits data word length .
03864   * @note   Function is called under interruption only, once
03865   *         interruptions have been enabled by HAL_UART_Receive_IT()
03866   * @param huart UART handle.
03867   * @retval None
03868   */
03869 static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
03870 {
03871   uint16_t *tmp;
03872   uint16_t uhMask = huart->Mask;
03873   uint16_t  uhdata;
03874
03875   /* Check that a Rx process is ongoing */
03876   if (huart->RxState == HAL_UART_STATE_BUSY_RX)
03877   {
03878     uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
03879     tmp = (uint16_t *) huart->pRxBuffPtr ;
03880     *tmp = (uint16_t)(uhdata & uhMask);
03881     huart->pRxBuffPtr += 2U;
03882     huart->RxXferCount--;
03883
03884     if (huart->RxXferCount == 0U)
03885     {
03886       /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
03887       CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
03888
03889       /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
03890       CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
03891
03892       /* Rx process is completed, restore huart->RxState to Ready */
03893       huart->RxState = HAL_UART_STATE_READY;
03894
03895       /* Clear RxISR function pointer */
03896       huart->RxISR = NULL;
03897
03898 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03899       /*Call registered Rx complete callback*/
03900       huart->RxCpltCallback(huart);
03901 #else
03902       /*Call legacy weak Rx complete callback*/
03903       HAL_UART_RxCpltCallback(huart);
03904 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03905     }
03906   }
03907   else
03908   {
03909     /* Clear RXNE interrupt flag */
03910     __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
03911   }
03912 }
03913
03914 /**
03915   * @brief RX interrrupt handler for 7 or 8  bits data word length and FIFO mode is enabled.
03916   * @note   Function is called under interruption only, once
03917   *         interruptions have been enabled by HAL_UART_Receive_IT()
03918   * @param huart UART handle.
03919   * @retval None
03920   */
03921 static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
03922 {
03923   uint16_t  uhMask = huart->Mask;
03924   uint16_t  uhdata;
03925   uint16_t   nb_rx_data;
03926   uint16_t  rxdatacount;
03927
03928   /* Check that a Rx process is ongoing */
03929   if (huart->RxState == HAL_UART_STATE_BUSY_RX)
03930   {
03931     for (nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)
03932     {
03933       uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
03934       *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
03935       huart->pRxBuffPtr++;
03936       huart->RxXferCount--;
03937
03938       if (huart->RxXferCount == 0U)
03939       {
03940         /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
03941         CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
03942
03943         /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
03944         CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
03945
03946         /* Rx process is completed, restore huart->RxState to Ready */
03947         huart->RxState = HAL_UART_STATE_READY;
03948
03949         /* Clear RxISR function pointer */
03950         huart->RxISR = NULL;
03951
03952 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
03953         /*Call registered Rx complete callback*/
03954         huart->RxCpltCallback(huart);
03955 #else
03956         /*Call legacy weak Rx complete callback*/
03957         HAL_UART_RxCpltCallback(huart);
03958 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
03959       }
03960     }
03961
03962     /* When remaining number of bytes to receive is less than the RX FIFO
03963     threshold, next incoming frames are processed as if FIFO mode was
03964     disabled (i.e. one interrupt per received frame).
03965     */
03966     rxdatacount = huart->RxXferCount;
03967     if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
03968     {
03969       /* Disable the UART RXFT interrupt*/
03970       CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
03971
03972       /* Update the RxISR function pointer */
03973       huart->RxISR = UART_RxISR_8BIT;
03974
03975       /* Enable the UART Data Register Not Empty interrupt */
03976       SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
03977     }
03978   }
03979   else
03980   {
03981     /* Clear RXNE interrupt flag */
03982     __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
03983   }
03984 }
03985
03986 /**
03987   * @brief RX interrrupt handler for 9 bits data word length and FIFO mode is enabled.
03988   * @note   Function is called under interruption only, once
03989   *         interruptions have been enabled by HAL_UART_Receive_IT()
03990   * @param huart UART handle.
03991   * @retval None
03992   */
03993 static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
03994 {
03995   uint16_t *tmp;
03996   uint16_t  uhMask = huart->Mask;
03997   uint16_t  uhdata;
03998   uint16_t   nb_rx_data;
03999   uint16_t  rxdatacount;
04000
04001   /* Check that a Rx process is ongoing */
04002   if (huart->RxState == HAL_UART_STATE_BUSY_RX)
04003   {
04004     for (nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)
04005     {
04006       uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
04007       tmp = (uint16_t *) huart->pRxBuffPtr ;
04008       *tmp = (uint16_t)(uhdata & uhMask);
04009       huart->pRxBuffPtr += 2U;
04010       huart->RxXferCount--;
04011
04012       if (huart->RxXferCount == 0U)
04013       {
04014         /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
04015         CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
04016
04017         /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
04018         CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
04019
04020         /* Rx process is completed, restore huart->RxState to Ready */
04021         huart->RxState = HAL_UART_STATE_READY;
04022
04023         /* Clear RxISR function pointer */
04024         huart->RxISR = NULL;
04025
04026 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
04027         /*Call registered Rx complete callback*/
04028         huart->RxCpltCallback(huart);
04029 #else
04030         /*Call legacy weak Rx complete callback*/
04031         HAL_UART_RxCpltCallback(huart);
04032 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
04033       }
04034     }
04035
04036     /* When remaining number of bytes to receive is less than the RX FIFO
04037     threshold, next incoming frames are processed as if FIFO mode was
04038     disabled (i.e. one interrupt per received frame).
04039     */
04040     rxdatacount = huart->RxXferCount;
04041     if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
04042     {
04043       /* Disable the UART RXFT interrupt*/
04044       CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
04045
04046       /* Update the RxISR function pointer */
04047       huart->RxISR = UART_RxISR_16BIT;
04048
04049       /* Enable the UART Data Register Not Empty interrupt */
04050       SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
04051     }
04052   }
04053   else
04054   {
04055     /* Clear RXNE interrupt flag */
04056     __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
04057   }
04058 }
04059
04060 /**
04061   * @}
04062   */
04063
04064 #endif /* HAL_UART_MODULE_ENABLED */
04065 /**
04066   * @}
04067   */
04068
04069 /**
04070   * @}
04071   */
04072
04073 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_uart.h Source File

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stm32wbxx_hal_uart.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_uart.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of UART HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_UART_H
00022 #define STM32WBxx_HAL_UART_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 /** @addtogroup STM32WBxx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup UART
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup UART_Exported_Types UART Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief UART Init Structure definition
00046   */
00047 typedef struct
00048 {
00049   uint32_t BaudRate;                  /*!< This member configures the UART communication baud rate.
00050                                            The baud rate register is computed using the following formula:
00051 #if defined(LPUART1)
00052                                            LPUART:
00053                                            =======
00054                                               Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate)))
00055                                            where lpuart_ker_ck_pres is the UART input clock divided by a prescaler
00056                                            UART:
00057                                            =====
00058 #endif
00059                                            - If oversampling is 16 or in LIN mode,
00060                                               Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate)))
00061                                            - If oversampling is 8,
00062                                               Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[15:4]
00063                                               Baud Rate Register[3] =  0
00064                                               Baud Rate Register[2:0] =  (((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[3:0]) >> 1
00065                                            where uart_ker_ck_pres is the UART input clock divided by a prescaler */
00066
00067   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
00068                                            This parameter can be a value of @ref UARTEx_Word_Length. */
00069
00070   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
00071                                            This parameter can be a value of @ref UART_Stop_Bits. */
00072
00073   uint32_t Parity;                    /*!< Specifies the parity mode.
00074                                            This parameter can be a value of @ref UART_Parity
00075                                            @note When parity is enabled, the computed parity is inserted
00076                                                  at the MSB position of the transmitted data (9th bit when
00077                                                  the word length is set to 9 data bits; 8th bit when the
00078                                                  word length is set to 8 data bits). */
00079
00080   uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
00081                                            This parameter can be a value of @ref UART_Mode. */
00082
00083   uint32_t HwFlowCtl;                 /*!< Specifies whether the hardware flow control mode is enabled
00084                                            or disabled.
00085                                            This parameter can be a value of @ref UART_Hardware_Flow_Control. */
00086
00087   uint32_t OverSampling;              /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8).
00088                                            This parameter can be a value of @ref UART_Over_Sampling. */
00089
00090   uint32_t OneBitSampling;            /*!< Specifies whether a single sample or three samples' majority vote is selected.
00091                                            Selecting the single sample method increases the receiver tolerance to clock
00092                                            deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
00093
00094   uint32_t ClockPrescaler;            /*!< Specifies the prescaler value used to divide the UART clock source.
00095                                            This parameter can be a value of @ref UART_ClockPrescaler. */
00096
00097 } UART_InitTypeDef;
00098
00099 /**
00100   * @brief  UART Advanced Features initialization structure definition
00101   */
00102 typedef struct
00103 {
00104   uint32_t AdvFeatureInit;        /*!< Specifies which advanced UART features is initialized. Several
00105                                        Advanced Features may be initialized at the same time .
00106                                        This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */
00107
00108   uint32_t TxPinLevelInvert;      /*!< Specifies whether the TX pin active level is inverted.
00109                                        This parameter can be a value of @ref UART_Tx_Inv. */
00110
00111   uint32_t RxPinLevelInvert;      /*!< Specifies whether the RX pin active level is inverted.
00112                                        This parameter can be a value of @ref UART_Rx_Inv. */
00113
00114   uint32_t DataInvert;            /*!< Specifies whether data are inverted (positive/direct logic
00115                                        vs negative/inverted logic).
00116                                        This parameter can be a value of @ref UART_Data_Inv. */
00117
00118   uint32_t Swap;                  /*!< Specifies whether TX and RX pins are swapped.
00119                                        This parameter can be a value of @ref UART_Rx_Tx_Swap. */
00120
00121   uint32_t OverrunDisable;        /*!< Specifies whether the reception overrun detection is disabled.
00122                                        This parameter can be a value of @ref UART_Overrun_Disable. */
00123
00124   uint32_t DMADisableonRxError;   /*!< Specifies whether the DMA is disabled in case of reception error.
00125                                        This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */
00126
00127   uint32_t AutoBaudRateEnable;    /*!< Specifies whether auto Baud rate detection is enabled.
00128                                        This parameter can be a value of @ref UART_AutoBaudRate_Enable. */
00129
00130   uint32_t AutoBaudRateMode;      /*!< If auto Baud rate detection is enabled, specifies how the rate
00131                                        detection is carried out.
00132                                        This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */
00133
00134   uint32_t MSBFirst;              /*!< Specifies whether MSB is sent first on UART line.
00135                                        This parameter can be a value of @ref UART_MSB_First. */
00136 } UART_AdvFeatureInitTypeDef;
00137
00138 /**
00139   * @brief HAL UART State definition
00140   * @note  HAL UART State value is a combination of 2 different substates: gState and RxState (see @ref UART_State_Definition).
00141   *        - gState contains UART state information related to global Handle management
00142   *          and also information related to Tx operations.
00143   *          gState value coding follow below described bitmap :
00144   *          b7-b6  Error information
00145   *             00 : No Error
00146   *             01 : (Not Used)
00147   *             10 : Timeout
00148   *             11 : Error
00149   *          b5     Peripheral initialization status
00150   *             0  : Reset (Peripheral not initialized)
00151   *             1  : Init done (Peripheral not initialized. HAL UART Init function already called)
00152   *          b4-b3  (not used)
00153   *             xx : Should be set to 00
00154   *          b2     Intrinsic process state
00155   *             0  : Ready
00156   *             1  : Busy (Peripheral busy with some configuration or internal operations)
00157   *          b1     (not used)
00158   *             x  : Should be set to 0
00159   *          b0     Tx state
00160   *             0  : Ready (no Tx operation ongoing)
00161   *             1  : Busy (Tx operation ongoing)
00162   *        - RxState contains information related to Rx operations.
00163   *          RxState value coding follow below described bitmap :
00164   *          b7-b6  (not used)
00165   *             xx : Should be set to 00
00166   *          b5     Peripheral initialization status
00167   *             0  : Reset (Peripheral not initialized)
00168   *             1  : Init done (Peripheral not initialized)
00169   *          b4-b2  (not used)
00170   *            xxx : Should be set to 000
00171   *          b1     Rx state
00172   *             0  : Ready (no Rx operation ongoing)
00173   *             1  : Busy (Rx operation ongoing)
00174   *          b0     (not used)
00175   *             x  : Should be set to 0.
00176   */
00177 typedef uint32_t HAL_UART_StateTypeDef;
00178
00179 /**
00180   * @brief UART clock sources definition
00181   */
00182 typedef enum
00183 {
00184   UART_CLOCKSOURCE_PCLK1      = 0x00U,    /*!< PCLK1 clock source  */
00185   UART_CLOCKSOURCE_PCLK2      = 0x01U,    /*!< PCLK2 clock source  */
00186   UART_CLOCKSOURCE_HSI        = 0x02U,    /*!< HSI clock source    */
00187   UART_CLOCKSOURCE_SYSCLK     = 0x04U,    /*!< SYSCLK clock source */
00188   UART_CLOCKSOURCE_LSE        = 0x08U,    /*!< LSE clock source       */
00189   UART_CLOCKSOURCE_UNDEFINED  = 0x10U     /*!< Undefined clock source */
00190 } UART_ClockSourceTypeDef;
00191
00192 /**
00193   * @brief  UART handle Structure definition
00194   */
00195 typedef struct __UART_HandleTypeDef
00196 {
00197   USART_TypeDef            *Instance;                /*!< UART registers base address        */
00198
00199   UART_InitTypeDef         Init;                     /*!< UART communication parameters      */
00200
00201   UART_AdvFeatureInitTypeDef AdvancedInit;           /*!< UART Advanced Features initialization parameters */
00202
00203   uint8_t                  *pTxBuffPtr;              /*!< Pointer to UART Tx transfer Buffer */
00204
00205   uint16_t                 TxXferSize;               /*!< UART Tx Transfer size              */
00206
00207   __IO uint16_t            TxXferCount;              /*!< UART Tx Transfer Counter           */
00208
00209   uint8_t                  *pRxBuffPtr;              /*!< Pointer to UART Rx transfer Buffer */
00210
00211   uint16_t                 RxXferSize;               /*!< UART Rx Transfer size              */
00212
00213   __IO uint16_t            RxXferCount;              /*!< UART Rx Transfer Counter           */
00214
00215   uint16_t                 Mask;                     /*!< UART Rx RDR register mask          */
00216
00217   uint32_t                 FifoMode;                 /*!< Specifies if the FIFO mode is being used.
00218                                                           This parameter can be a value of @ref UARTEx_FIFO_mode. */
00219
00220   uint16_t                 NbRxDataToProcess;        /*!< Number of data to process during RX ISR execution */
00221
00222   uint16_t                 NbTxDataToProcess;        /*!< Number of data to process during TX ISR execution */
00223
00224   void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
00225
00226   void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
00227
00228   DMA_HandleTypeDef        *hdmatx;                  /*!< UART Tx DMA Handle parameters      */
00229
00230   DMA_HandleTypeDef        *hdmarx;                  /*!< UART Rx DMA Handle parameters      */
00231
00232   HAL_LockTypeDef           Lock;                    /*!< Locking object                     */
00233
00234   __IO HAL_UART_StateTypeDef    gState;              /*!< UART state information related to global Handle management
00235                                                           and also related to Tx operations.
00236                                                           This parameter can be a value of @ref HAL_UART_StateTypeDef */
00237
00238   __IO HAL_UART_StateTypeDef    RxState;             /*!< UART state information related to Rx operations.
00239                                                           This parameter can be a value of @ref HAL_UART_StateTypeDef */
00240
00241   __IO uint32_t                 ErrorCode;           /*!< UART Error code                    */
00242
00243 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00244   void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Tx Half Complete Callback        */
00245   void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Tx Complete Callback             */
00246   void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Rx Half Complete Callback        */
00247   void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Rx Complete Callback             */
00248   void (* ErrorCallback)(struct __UART_HandleTypeDef *huart);             /*!< UART Error Callback                   */
00249   void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Abort Complete Callback          */
00250   void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */
00251   void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart);  /*!< UART Abort Receive Complete Callback  */
00252   void (* WakeupCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Wakeup Callback                  */
00253   void (* RxFifoFullCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Rx Fifo Full Callback            */
00254   void (* TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart);       /*!< UART Tx Fifo Empty Callback           */
00255
00256   void (* MspInitCallback)(struct __UART_HandleTypeDef *huart);           /*!< UART Msp Init callback                */
00257   void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Msp DeInit callback              */
00258 #endif  /* USE_HAL_UART_REGISTER_CALLBACKS */
00259
00260 } UART_HandleTypeDef;
00261
00262 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00263 /**
00264   * @brief  HAL UART Callback ID enumeration definition
00265   */
00266 typedef enum
00267 {
00268   HAL_UART_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< UART Tx Half Complete Callback ID        */
00269   HAL_UART_TX_COMPLETE_CB_ID             = 0x01U,    /*!< UART Tx Complete Callback ID             */
00270   HAL_UART_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< UART Rx Half Complete Callback ID        */
00271   HAL_UART_RX_COMPLETE_CB_ID             = 0x03U,    /*!< UART Rx Complete Callback ID             */
00272   HAL_UART_ERROR_CB_ID                   = 0x04U,    /*!< UART Error Callback ID                   */
00273   HAL_UART_ABORT_COMPLETE_CB_ID          = 0x05U,    /*!< UART Abort Complete Callback ID          */
00274   HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U,    /*!< UART Abort Transmit Complete Callback ID */
00275   HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x07U,    /*!< UART Abort Receive Complete Callback ID  */
00276   HAL_UART_WAKEUP_CB_ID                  = 0x08U,    /*!< UART Wakeup Callback ID                  */
00277   HAL_UART_RX_FIFO_FULL_CB_ID            = 0x09U,    /*!< UART Rx Fifo Full Callback ID            */
00278   HAL_UART_TX_FIFO_EMPTY_CB_ID           = 0x0AU,    /*!< UART Tx Fifo Empty Callback ID           */
00279
00280   HAL_UART_MSPINIT_CB_ID                 = 0x0BU,    /*!< UART MspInit callback ID                 */
00281   HAL_UART_MSPDEINIT_CB_ID               = 0x0CU     /*!< UART MspDeInit callback ID               */
00282
00283 } HAL_UART_CallbackIDTypeDef;
00284
00285 /**
00286   * @brief  HAL UART Callback pointer definition
00287   */
00288 typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer to an UART callback function */
00289
00290 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
00291
00292 /**
00293   * @}
00294   */
00295
00296 /* Exported constants --------------------------------------------------------*/
00297 /** @defgroup UART_Exported_Constants UART Exported Constants
00298   * @{
00299   */
00300
00301 /** @defgroup UART_State_Definition UART State Code Definition
00302   * @{
00303   */
00304 #define  HAL_UART_STATE_RESET         0x00000000U    /*!< Peripheral is not initialized
00305                                                           Value is allowed for gState and RxState */
00306 #define  HAL_UART_STATE_READY         0x00000020U    /*!< Peripheral Initialized and ready for use
00307                                                           Value is allowed for gState and RxState */
00308 #define  HAL_UART_STATE_BUSY          0x00000024U    /*!< an internal process is ongoing
00309                                                           Value is allowed for gState only */
00310 #define  HAL_UART_STATE_BUSY_TX       0x00000021U    /*!< Data Transmission process is ongoing
00311                                                           Value is allowed for gState only */
00312 #define  HAL_UART_STATE_BUSY_RX       0x00000022U    /*!< Data Reception process is ongoing
00313                                                           Value is allowed for RxState only */
00314 #define  HAL_UART_STATE_BUSY_TX_RX    0x00000023U    /*!< Data Transmission and Reception process is ongoing
00315                                                           Not to be used for neither gState nor RxState.
00316                                                           Value is result of combination (Or) between gState and RxState values */
00317 #define  HAL_UART_STATE_TIMEOUT       0x000000A0U    /*!< Timeout state
00318                                                           Value is allowed for gState only */
00319 #define  HAL_UART_STATE_ERROR         0x000000E0U    /*!< Error
00320                                                           Value is allowed for gState only */
00321 /**
00322   * @}
00323   */
00324
00325 /** @defgroup UART_Error_Definition   UART Error Definition
00326   * @{
00327   */
00328 #define  HAL_UART_ERROR_NONE             ((uint32_t)0x00000000U)    /*!< No error                */
00329 #define  HAL_UART_ERROR_PE               ((uint32_t)0x00000001U)    /*!< Parity error            */
00330 #define  HAL_UART_ERROR_NE               ((uint32_t)0x00000002U)    /*!< Noise error             */
00331 #define  HAL_UART_ERROR_FE               ((uint32_t)0x00000004U)    /*!< Frame error             */
00332 #define  HAL_UART_ERROR_ORE              ((uint32_t)0x00000008U)    /*!< Overrun error           */
00333 #define  HAL_UART_ERROR_DMA              ((uint32_t)0x00000010U)    /*!< DMA transfer error      */
00334 #define  HAL_UART_ERROR_RTO              ((uint32_t)0x00000020U)    /*!< Receiver Timeout error  */
00335
00336 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00337 #define  HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U)    /*!< Invalid Callback error  */
00338 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
00339 /**
00340   * @}
00341   */
00342
00343 /** @defgroup UART_Stop_Bits   UART Number of Stop Bits
00344   * @{
00345   */
00346 #define UART_STOPBITS_0_5                    USART_CR2_STOP_0                     /*!< UART frame with 0.5 stop bit  */
00347 #define UART_STOPBITS_1                     0x00000000U                           /*!< UART frame with 1 stop bit    */
00348 #define UART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */
00349 #define UART_STOPBITS_2                      USART_CR2_STOP_1                     /*!< UART frame with 2 stop bits   */
00350 /**
00351   * @}
00352   */
00353
00354 /** @defgroup UART_Parity  UART Parity
00355   * @{
00356   */
00357 #define UART_PARITY_NONE                    0x00000000U                        /*!< No parity   */
00358 #define UART_PARITY_EVEN                    USART_CR1_PCE                      /*!< Even parity */
00359 #define UART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)     /*!< Odd parity  */
00360 /**
00361   * @}
00362   */
00363
00364 /** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
00365   * @{
00366   */
00367 #define UART_HWCONTROL_NONE                  0x00000000U                          /*!< No hardware control       */
00368 #define UART_HWCONTROL_RTS                   USART_CR3_RTSE                       /*!< Request To Send           */
00369 #define UART_HWCONTROL_CTS                   USART_CR3_CTSE                       /*!< Clear To Send             */
00370 #define UART_HWCONTROL_RTS_CTS               (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< Request and Clear To Send */
00371 /**
00372   * @}
00373   */
00374
00375 /** @defgroup UART_Mode UART Transfer Mode
00376   * @{
00377   */
00378 #define UART_MODE_RX                        USART_CR1_RE                    /*!< RX mode        */
00379 #define UART_MODE_TX                        USART_CR1_TE                    /*!< TX mode        */
00380 #define UART_MODE_TX_RX                     (USART_CR1_TE |USART_CR1_RE)    /*!< RX and TX mode */
00381 /**
00382   * @}
00383   */
00384
00385 /** @defgroup UART_State  UART State
00386   * @{
00387   */
00388 #define UART_STATE_DISABLE                  0x00000000U         /*!< UART disabled  */
00389 #define UART_STATE_ENABLE                   USART_CR1_UE        /*!< UART enabled   */
00390 /**
00391   * @}
00392   */
00393
00394 /** @defgroup UART_Over_Sampling UART Over Sampling
00395   * @{
00396   */
00397 #define UART_OVERSAMPLING_16                0x00000000U         /*!< Oversampling by 16 */
00398 #define UART_OVERSAMPLING_8                 USART_CR1_OVER8     /*!< Oversampling by 8  */
00399 /**
00400   * @}
00401   */
00402
00403 /** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method
00404   * @{
00405   */
00406 #define UART_ONE_BIT_SAMPLE_DISABLE         0x00000000U         /*!< One-bit sampling disable */
00407 #define UART_ONE_BIT_SAMPLE_ENABLE          USART_CR3_ONEBIT    /*!< One-bit sampling enable  */
00408 /**
00409   * @}
00410   */
00411
00412 /** @defgroup UART_ClockPrescaler  UART Clock Prescaler
00413   * @{
00414   */
00415 #define UART_PRESCALER_DIV1    0x00000000U  /*!< fclk_pres = fclk     */
00416 #define UART_PRESCALER_DIV2    0x00000001U  /*!< fclk_pres = fclk/2   */
00417 #define UART_PRESCALER_DIV4    0x00000002U  /*!< fclk_pres = fclk/4   */
00418 #define UART_PRESCALER_DIV6    0x00000003U  /*!< fclk_pres = fclk/6   */
00419 #define UART_PRESCALER_DIV8    0x00000004U  /*!< fclk_pres = fclk/8   */
00420 #define UART_PRESCALER_DIV10   0x00000005U  /*!< fclk_pres = fclk/10  */
00421 #define UART_PRESCALER_DIV12   0x00000006U  /*!< fclk_pres = fclk/12  */
00422 #define UART_PRESCALER_DIV16   0x00000007U  /*!< fclk_pres = fclk/16  */
00423 #define UART_PRESCALER_DIV32   0x00000008U  /*!< fclk_pres = fclk/32  */
00424 #define UART_PRESCALER_DIV64   0x00000009U  /*!< fclk_pres = fclk/64  */
00425 #define UART_PRESCALER_DIV128  0x0000000AU  /*!< fclk_pres = fclk/128 */
00426 #define UART_PRESCALER_DIV256  0x0000000BU  /*!< fclk_pres = fclk/256 */
00427 /**
00428   * @}
00429   */
00430
00431 /** @defgroup UART_AutoBaud_Rate_Mode    UART Advanced Feature AutoBaud Rate Mode
00432   * @{
00433   */
00434 #define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT    0x00000000U           /*!< Auto Baud rate detection on start bit            */
00435 #define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0   /*!< Auto Baud rate detection on falling edge         */
00436 #define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME   USART_CR2_ABRMODE_1   /*!< Auto Baud rate detection on 0x7F frame detection */
00437 #define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME   USART_CR2_ABRMODE     /*!< Auto Baud rate detection on 0x55 frame detection */
00438 /**
00439   * @}
00440   */
00441
00442 /** @defgroup UART_Receiver_Timeout UART Receiver Timeout
00443   * @{
00444   */
00445 #define UART_RECEIVER_TIMEOUT_DISABLE       0x00000000U                /*!< UART Receiver Timeout disable */
00446 #define UART_RECEIVER_TIMEOUT_ENABLE        USART_CR2_RTOEN            /*!< UART Receiver Timeout enable  */
00447 /**
00448   * @}
00449   */
00450
00451 /** @defgroup UART_LIN    UART Local Interconnection Network mode
00452   * @{
00453   */
00454 #define UART_LIN_DISABLE                    0x00000000U                /*!< Local Interconnect Network disable */
00455 #define UART_LIN_ENABLE                     USART_CR2_LINEN            /*!< Local Interconnect Network enable  */
00456 /**
00457   * @}
00458   */
00459
00460 /** @defgroup UART_LIN_Break_Detection  UART LIN Break Detection
00461   * @{
00462   */
00463 #define UART_LINBREAKDETECTLENGTH_10B       0x00000000U                /*!< LIN 10-bit break detection length */
00464 #define UART_LINBREAKDETECTLENGTH_11B       USART_CR2_LBDL             /*!< LIN 11-bit break detection length  */
00465 /**
00466   * @}
00467   */
00468
00469 /** @defgroup UART_DMA_Tx    UART DMA Tx
00470   * @{
00471   */
00472 #define UART_DMA_TX_DISABLE                 0x00000000U                /*!< UART DMA TX disabled */
00473 #define UART_DMA_TX_ENABLE                  USART_CR3_DMAT             /*!< UART DMA TX enabled  */
00474 /**
00475   * @}
00476   */
00477
00478 /** @defgroup UART_DMA_Rx   UART DMA Rx
00479   * @{
00480   */
00481 #define UART_DMA_RX_DISABLE                 0x00000000U                 /*!< UART DMA RX disabled */
00482 #define UART_DMA_RX_ENABLE                  USART_CR3_DMAR              /*!< UART DMA RX enabled  */
00483 /**
00484   * @}
00485   */
00486
00487 /** @defgroup UART_Half_Duplex_Selection  UART Half Duplex Selection
00488   * @{
00489   */
00490 #define UART_HALF_DUPLEX_DISABLE            0x00000000U                 /*!< UART half-duplex disabled */
00491 #define UART_HALF_DUPLEX_ENABLE             USART_CR3_HDSEL             /*!< UART half-duplex enabled  */
00492 /**
00493   * @}
00494   */
00495
00496 /** @defgroup UART_WakeUp_Methods   UART WakeUp Methods
00497   * @{
00498   */
00499 #define UART_WAKEUPMETHOD_IDLELINE          0x00000000U                 /*!< UART wake-up on idle line    */
00500 #define UART_WAKEUPMETHOD_ADDRESSMARK       USART_CR1_WAKE              /*!< UART wake-up on address mark */
00501 /**
00502   * @}
00503   */
00504
00505 /** @defgroup UART_Request_Parameters UART Request Parameters
00506   * @{
00507   */
00508 #define UART_AUTOBAUD_REQUEST               USART_RQR_ABRRQ        /*!< Auto-Baud Rate Request      */
00509 #define UART_SENDBREAK_REQUEST              USART_RQR_SBKRQ        /*!< Send Break Request          */
00510 #define UART_MUTE_MODE_REQUEST              USART_RQR_MMRQ         /*!< Mute Mode Request           */
00511 #define UART_RXDATA_FLUSH_REQUEST           USART_RQR_RXFRQ        /*!< Receive Data flush Request  */
00512 #define UART_TXDATA_FLUSH_REQUEST           USART_RQR_TXFRQ        /*!< Transmit data flush Request */
00513 /**
00514   * @}
00515   */
00516
00517 /** @defgroup UART_Advanced_Features_Initialization_Type  UART Advanced Feature Initialization Type
00518   * @{
00519   */
00520 #define UART_ADVFEATURE_NO_INIT                 0x00000000U          /*!< No advanced feature initialization       */
00521 #define UART_ADVFEATURE_TXINVERT_INIT           0x00000001U          /*!< TX pin active level inversion            */
00522 #define UART_ADVFEATURE_RXINVERT_INIT           0x00000002U          /*!< RX pin active level inversion            */
00523 #define UART_ADVFEATURE_DATAINVERT_INIT         0x00000004U          /*!< Binary data inversion                    */
00524 #define UART_ADVFEATURE_SWAP_INIT               0x00000008U          /*!< TX/RX pins swap                          */
00525 #define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT   0x00000010U          /*!< RX overrun disable                       */
00526 #define UART_ADVFEATURE_DMADISABLEONERROR_INIT  0x00000020U          /*!< DMA disable on Reception Error           */
00527 #define UART_ADVFEATURE_AUTOBAUDRATE_INIT       0x00000040U          /*!< Auto Baud rate detection initialization  */
00528 #define UART_ADVFEATURE_MSBFIRST_INIT           0x00000080U          /*!< Most significant bit sent/received first */
00529 /**
00530   * @}
00531   */
00532
00533 /** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion
00534   * @{
00535   */
00536 #define UART_ADVFEATURE_TXINV_DISABLE       0x00000000U             /*!< TX pin active level inversion disable */
00537 #define UART_ADVFEATURE_TXINV_ENABLE        USART_CR2_TXINV         /*!< TX pin active level inversion enable  */
00538 /**
00539   * @}
00540   */
00541
00542 /** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion
00543   * @{
00544   */
00545 #define UART_ADVFEATURE_RXINV_DISABLE       0x00000000U             /*!< RX pin active level inversion disable */
00546 #define UART_ADVFEATURE_RXINV_ENABLE        USART_CR2_RXINV         /*!< RX pin active level inversion enable  */
00547 /**
00548   * @}
00549   */
00550
00551 /** @defgroup UART_Data_Inv  UART Advanced Feature Binary Data Inversion
00552   * @{
00553   */
00554 #define UART_ADVFEATURE_DATAINV_DISABLE     0x00000000U             /*!< Binary data inversion disable */
00555 #define UART_ADVFEATURE_DATAINV_ENABLE      USART_CR2_DATAINV       /*!< Binary data inversion enable  */
00556 /**
00557   * @}
00558   */
00559
00560 /** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap
00561   * @{
00562   */
00563 #define UART_ADVFEATURE_SWAP_DISABLE        0x00000000U             /*!< TX/RX pins swap disable */
00564 #define UART_ADVFEATURE_SWAP_ENABLE         USART_CR2_SWAP          /*!< TX/RX pins swap enable  */
00565 /**
00566   * @}
00567   */
00568
00569 /** @defgroup UART_Overrun_Disable  UART Advanced Feature Overrun Disable
00570   * @{
00571   */
00572 #define UART_ADVFEATURE_OVERRUN_ENABLE      0x00000000U             /*!< RX overrun enable  */
00573 #define UART_ADVFEATURE_OVERRUN_DISABLE     USART_CR3_OVRDIS        /*!< RX overrun disable */
00574 /**
00575   * @}
00576   */
00577
00578 /** @defgroup UART_AutoBaudRate_Enable  UART Advanced Feature Auto BaudRate Enable
00579   * @{
00580   */
00581 #define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE   0x00000000U          /*!< RX Auto Baud rate detection enable  */
00582 #define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE    USART_CR2_ABREN      /*!< RX Auto Baud rate detection disable */
00583 /**
00584   * @}
00585   */
00586
00587 /** @defgroup UART_DMA_Disable_on_Rx_Error   UART Advanced Feature DMA Disable On Rx Error
00588   * @{
00589   */
00590 #define UART_ADVFEATURE_DMA_ENABLEONRXERROR    0x00000000U          /*!< DMA enable on Reception Error  */
00591 #define UART_ADVFEATURE_DMA_DISABLEONRXERROR   USART_CR3_DDRE       /*!< DMA disable on Reception Error */
00592 /**
00593   * @}
00594   */
00595
00596 /** @defgroup UART_MSB_First   UART Advanced Feature MSB First
00597   * @{
00598   */
00599 #define UART_ADVFEATURE_MSBFIRST_DISABLE    0x00000000U             /*!< Most significant bit sent/received first disable */
00600 #define UART_ADVFEATURE_MSBFIRST_ENABLE     USART_CR2_MSBFIRST      /*!< Most significant bit sent/received first enable  */
00601 /**
00602   * @}
00603   */
00604
00605 /** @defgroup UART_Stop_Mode_Enable   UART Advanced Feature Stop Mode Enable
00606   * @{
00607   */
00608 #define UART_ADVFEATURE_STOPMODE_DISABLE    0x00000000U             /*!< UART stop mode disable */
00609 #define UART_ADVFEATURE_STOPMODE_ENABLE     USART_CR1_UESM          /*!< UART stop mode enable  */
00610 /**
00611   * @}
00612   */
00613
00614 /** @defgroup UART_Mute_Mode   UART Advanced Feature Mute Mode Enable
00615   * @{
00616   */
00617 #define UART_ADVFEATURE_MUTEMODE_DISABLE    0x00000000U             /*!< UART mute mode disable */
00618 #define UART_ADVFEATURE_MUTEMODE_ENABLE     USART_CR1_MME           /*!< UART mute mode enable  */
00619 /**
00620   * @}
00621   */
00622
00623 /** @defgroup UART_CR2_ADDRESS_LSB_POS    UART Address-matching LSB Position In CR2 Register
00624   * @{
00625   */
00626 #define UART_CR2_ADDRESS_LSB_POS             24U                                /*!< UART address-matching LSB position in CR2 register */
00627 /**
00628   * @}
00629   */
00630
00631 /** @defgroup UART_WakeUp_from_Stop_Selection   UART WakeUp From Stop Selection
00632   * @{
00633   */
00634 #define UART_WAKEUP_ON_ADDRESS              0x00000000U             /*!< UART wake-up on address                         */
00635 #define UART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1         /*!< UART wake-up on start bit                       */
00636 #define UART_WAKEUP_ON_READDATA_NONEMPTY    USART_CR3_WUS           /*!< UART wake-up on receive data register not empty or RXFIFO is not empty */
00637 /**
00638   * @}
00639   */
00640
00641 /** @defgroup UART_DriverEnable_Polarity      UART DriverEnable Polarity
00642   * @{
00643   */
00644 #define UART_DE_POLARITY_HIGH               0x00000000U             /*!< Driver enable signal is active high */
00645 #define UART_DE_POLARITY_LOW                USART_CR3_DEP           /*!< Driver enable signal is active low  */
00646 /**
00647   * @}
00648   */
00649
00650 /** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS    UART Driver Enable Assertion Time LSB Position In CR1 Register
00651   * @{
00652   */
00653 #define UART_CR1_DEAT_ADDRESS_LSB_POS       21U      /*!< UART Driver Enable assertion time LSB position in CR1 register */
00654 /**
00655   * @}
00656   */
00657
00658 /** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS    UART Driver Enable DeAssertion Time LSB Position In CR1 Register
00659   * @{
00660   */
00661 #define UART_CR1_DEDT_ADDRESS_LSB_POS       16U      /*!< UART Driver Enable de-assertion time LSB position in CR1 register */
00662 /**
00663   * @}
00664   */
00665
00666 /** @defgroup UART_Interruption_Mask    UART Interruptions Flag Mask
00667   * @{
00668   */
00669 #define UART_IT_MASK                        0x001FU  /*!< UART interruptions flags mask */
00670 /**
00671   * @}
00672   */
00673
00674 /** @defgroup UART_TimeOut_Value    UART polling-based communications time-out value
00675   * @{
00676   */
00677 #define HAL_UART_TIMEOUT_VALUE              0x1FFFFFFU  /*!< UART polling-based communications time-out value */
00678 /**
00679   * @}
00680   */
00681
00682 /** @defgroup UART_Flags     UART Status Flags
00683   *        Elements values convention: 0xXXXX
00684   *           - 0xXXXX  : Flag mask in the ISR register
00685   * @{
00686   */
00687 #define UART_FLAG_TXFT                      USART_ISR_TXFT          /*!< UART TXFIFO threshold flag                */
00688 #define UART_FLAG_RXFT                      USART_ISR_RXFT          /*!< UART RXFIFO threshold flag                */
00689 #define UART_FLAG_RXFF                      USART_ISR_RXFF          /*!< UART RXFIFO Full flag                     */
00690 #define UART_FLAG_TXFE                      USART_ISR_TXFE          /*!< UART TXFIFO Empty flag                    */
00691 #define UART_FLAG_REACK                     USART_ISR_REACK         /*!< UART receive enable acknowledge flag      */
00692 #define UART_FLAG_TEACK                     USART_ISR_TEACK         /*!< UART transmit enable acknowledge flag     */
00693 #define UART_FLAG_WUF                       USART_ISR_WUF           /*!< UART wake-up from stop mode flag          */
00694 #define UART_FLAG_RWU                       USART_ISR_RWU           /*!< UART receiver wake-up from mute mode flag */
00695 #define UART_FLAG_SBKF                      USART_ISR_SBKF          /*!< UART send break flag                      */
00696 #define UART_FLAG_CMF                       USART_ISR_CMF           /*!< UART character match flag                 */
00697 #define UART_FLAG_BUSY                      USART_ISR_BUSY          /*!< UART busy flag                            */
00698 #define UART_FLAG_ABRF                      USART_ISR_ABRF          /*!< UART auto Baud rate flag                  */
00699 #define UART_FLAG_ABRE                      USART_ISR_ABRE          /*!< UART auto Baud rate error                 */
00700 #define UART_FLAG_RTOF                      USART_ISR_RTOF          /*!< UART receiver timeout flag                */
00701 #define UART_FLAG_CTS                       USART_ISR_CTS           /*!< UART clear to send flag                   */
00702 #define UART_FLAG_CTSIF                     USART_ISR_CTSIF         /*!< UART clear to send interrupt flag         */
00703 #define UART_FLAG_LBDF                      USART_ISR_LBDF          /*!< UART LIN break detection flag             */
00704 #define UART_FLAG_TXE                       USART_ISR_TXE_TXFNF     /*!< UART transmit data register empty         */
00705 #define UART_FLAG_TXFNF                     USART_ISR_TXE_TXFNF     /*!< UART TXFIFO not full                      */
00706 #define UART_FLAG_TC                        USART_ISR_TC            /*!< UART transmission complete                */
00707 #define UART_FLAG_RXNE                      USART_ISR_RXNE_RXFNE    /*!< UART read data register not empty         */
00708 #define UART_FLAG_RXFNE                     USART_ISR_RXNE_RXFNE    /*!< UART RXFIFO not empty                     */
00709 #define UART_FLAG_IDLE                      USART_ISR_IDLE          /*!< UART idle flag                            */
00710 #define UART_FLAG_ORE                       USART_ISR_ORE           /*!< UART overrun error                        */
00711 #define UART_FLAG_NE                        USART_ISR_NE            /*!< UART noise error                          */
00712 #define UART_FLAG_FE                        USART_ISR_FE            /*!< UART frame error                          */
00713 #define UART_FLAG_PE                        USART_ISR_PE            /*!< UART parity error                         */
00714 /**
00715   * @}
00716   */
00717
00718 /** @defgroup UART_Interrupt_definition   UART Interrupts Definition
00719   *        Elements values convention: 000ZZZZZ0XXYYYYYb
00720   *           - YYYYY  : Interrupt source position in the XX register (5bits)
00721   *           - XX  : Interrupt source register (2bits)
00722   *                 - 01: CR1 register
00723   *                 - 10: CR2 register
00724   *                 - 11: CR3 register
00725   *           - ZZZZZ  : Flag position in the ISR register(5bits)
00726   *        Elements values convention: 000000000XXYYYYYb
00727   *           - YYYYY  : Interrupt source position in the XX register (5bits)
00728   *           - XX  : Interrupt source register (2bits)
00729   *                 - 01: CR1 register
00730   *                 - 10: CR2 register
00731   *                 - 11: CR3 register
00732   *        Elements values convention: 0000ZZZZ00000000b
00733   *           - ZZZZ  : Flag position in the ISR register(4bits)
00734   * @{
00735   */
00736 #define UART_IT_PE                          0x0028U                  /*!< UART parity error interruption                 */
00737 #define UART_IT_TXE                         0x0727U                  /*!< UART transmit data register empty interruption */
00738 #define UART_IT_TXFNF                       0x0727U                  /*!< UART TX FIFO not full interruption             */
00739 #define UART_IT_TC                          0x0626U                  /*!< UART transmission complete interruption        */
00740 #define UART_IT_RXNE                        0x0525U                  /*!< UART read data register not empty interruption */
00741 #define UART_IT_RXFNE                       0x0525U                  /*!< UART RXFIFO not empty interruption             */
00742 #define UART_IT_IDLE                        0x0424U                  /*!< UART idle interruption                         */
00743 #define UART_IT_LBD                         0x0846U                  /*!< UART LIN break detection interruption          */
00744 #define UART_IT_CTS                         0x096AU                  /*!< UART CTS interruption                          */
00745 #define UART_IT_CM                          0x112EU                  /*!< UART character match interruption              */
00746 #define UART_IT_WUF                         0x1476U                  /*!< UART wake-up from stop mode interruption       */
00747 #define UART_IT_RXFF                        0x183FU                  /*!< UART RXFIFO full interruption                  */
00748 #define UART_IT_TXFE                        0x173EU                  /*!< UART TXFIFO empty interruption                 */
00749 #define UART_IT_RXFT                        0x1A7CU                  /*!< UART RXFIFO threshold reached interruption     */
00750 #define UART_IT_TXFT                        0x1B77U                  /*!< UART TXFIFO threshold reached interruption     */
00751 #define UART_IT_RTO                         0x0B3AU                  /*!< UART receiver timeout interruption             */
00752
00753 #define UART_IT_ERR                         0x0060U                  /*!< UART error interruption         */
00754
00755 #define UART_IT_ORE                         0x0300U                  /*!< UART overrun error interruption */
00756 #define UART_IT_NE                          0x0200U                  /*!< UART noise error interruption   */
00757 #define UART_IT_FE                          0x0100U                  /*!< UART frame error interruption   */
00758 /**
00759   * @}
00760   */
00761
00762 /** @defgroup UART_IT_CLEAR_Flags  UART Interruption Clear Flags
00763   * @{
00764   */
00765 #define UART_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag           */
00766 #define UART_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag          */
00767 #define UART_CLEAR_NEF                       USART_ICR_NECF            /*!< Noise Error detected Clear Flag   */
00768 #define UART_CLEAR_OREF                      USART_ICR_ORECF           /*!< Overrun Error Clear Flag          */
00769 #define UART_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag     */
00770 #define UART_CLEAR_TXFECF                    USART_ICR_TXFECF          /*!< TXFIFO empty clear flag           */
00771 #define UART_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag  */
00772 #define UART_CLEAR_LBDF                      USART_ICR_LBDCF           /*!< LIN Break Detection Clear Flag    */
00773 #define UART_CLEAR_CTSF                      USART_ICR_CTSCF           /*!< CTS Interrupt Clear Flag          */
00774 #define UART_CLEAR_CMF                       USART_ICR_CMCF            /*!< Character Match Clear Flag        */
00775 #define UART_CLEAR_WUF                       USART_ICR_WUCF            /*!< Wake Up from stop mode Clear Flag */
00776 #define UART_CLEAR_RTOF                      USART_ICR_RTOCF           /*!< UART receiver timeout clear flag  */
00777 /**
00778   * @}
00779   */
00780
00781
00782 /**
00783   * @}
00784   */
00785
00786 /* Exported macros -----------------------------------------------------------*/
00787 /** @defgroup UART_Exported_Macros UART Exported Macros
00788   * @{
00789   */
00790
00791 /** @brief  Reset UART handle states.
00792   * @param  __HANDLE__ UART handle.
00793   * @retval None
00794   */
00795 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00796 #define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
00797                                                        (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
00798                                                        (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
00799                                                        (__HANDLE__)->MspInitCallback = NULL;             \
00800                                                        (__HANDLE__)->MspDeInitCallback = NULL;           \
00801                                                      } while(0U)
00802 #else
00803 #define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
00804                                                        (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
00805                                                        (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
00806                                                      } while(0U)
00807 #endif /*USE_HAL_UART_REGISTER_CALLBACKS */
00808
00809 /** @brief  Flush the UART Data registers.
00810   * @param  __HANDLE__ specifies the UART Handle.
00811   * @retval None
00812   */
00813 #define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)  \
00814   do{                \
00815     SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
00816     SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
00817   }  while(0U)
00818
00819 /** @brief  Clear the specified UART pending flag.
00820   * @param  __HANDLE__ specifies the UART Handle.
00821   * @param  __FLAG__ specifies the flag to check.
00822   *          This parameter can be any combination of the following values:
00823   *            @arg @ref UART_CLEAR_PEF      Parity Error Clear Flag
00824   *            @arg @ref UART_CLEAR_FEF      Framing Error Clear Flag
00825   *            @arg @ref UART_CLEAR_NEF      Noise detected Clear Flag
00826   *            @arg @ref UART_CLEAR_OREF     Overrun Error Clear Flag
00827   *            @arg @ref UART_CLEAR_IDLEF    IDLE line detected Clear Flag
00828   *            @arg @ref UART_CLEAR_TXFECF   TXFIFO empty clear Flag
00829   *            @arg @ref UART_CLEAR_TCF      Transmission Complete Clear Flag
00830   *            @arg @ref UART_CLEAR_RTOF     Receiver Timeout clear flag
00831   *            @arg @ref UART_CLEAR_LBDF     LIN Break Detection Clear Flag
00832   *            @arg @ref UART_CLEAR_CTSF     CTS Interrupt Clear Flag
00833   *            @arg @ref UART_CLEAR_CMF      Character Match Clear Flag
00834   *            @arg @ref UART_CLEAR_WUF      Wake Up from stop mode Clear Flag
00835   * @retval None
00836   */
00837 #define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00838
00839 /** @brief  Clear the UART PE pending flag.
00840   * @param  __HANDLE__ specifies the UART Handle.
00841   * @retval None
00842   */
00843 #define __HAL_UART_CLEAR_PEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
00844
00845 /** @brief  Clear the UART FE pending flag.
00846   * @param  __HANDLE__ specifies the UART Handle.
00847   * @retval None
00848   */
00849 #define __HAL_UART_CLEAR_FEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
00850
00851 /** @brief  Clear the UART NE pending flag.
00852   * @param  __HANDLE__ specifies the UART Handle.
00853   * @retval None
00854   */
00855 #define __HAL_UART_CLEAR_NEFLAG(__HANDLE__)  __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
00856
00857 /** @brief  Clear the UART ORE pending flag.
00858   * @param  __HANDLE__ specifies the UART Handle.
00859   * @retval None
00860   */
00861 #define __HAL_UART_CLEAR_OREFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
00862
00863 /** @brief  Clear the UART IDLE pending flag.
00864   * @param  __HANDLE__ specifies the UART Handle.
00865   * @retval None
00866   */
00867 #define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
00868
00869 /** @brief  Clear the UART TX FIFO empty clear flag.
00870   * @param  __HANDLE__ specifies the UART Handle.
00871   * @retval None
00872   */
00873 #define __HAL_UART_CLEAR_TXFECF(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF)
00874
00875 /** @brief  Check whether the specified UART flag is set or not.
00876   * @param  __HANDLE__ specifies the UART Handle.
00877   * @param  __FLAG__ specifies the flag to check.
00878   *        This parameter can be one of the following values:
00879   *            @arg @ref UART_FLAG_TXFT  TXFIFO threshold flag
00880   *            @arg @ref UART_FLAG_RXFT  RXFIFO threshold flag
00881   *            @arg @ref UART_FLAG_RXFF  RXFIFO Full flag
00882   *            @arg @ref UART_FLAG_TXFE  TXFIFO Empty flag
00883   *            @arg @ref UART_FLAG_REACK Receive enable acknowledge flag
00884   *            @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag
00885   *            @arg @ref UART_FLAG_WUF   Wake up from stop mode flag
00886   *            @arg @ref UART_FLAG_RWU   Receiver wake up flag (if the UART in mute mode)
00887   *            @arg @ref UART_FLAG_SBKF  Send Break flag
00888   *            @arg @ref UART_FLAG_CMF   Character match flag
00889   *            @arg @ref UART_FLAG_BUSY  Busy flag
00890   *            @arg @ref UART_FLAG_ABRF  Auto Baud rate detection flag
00891   *            @arg @ref UART_FLAG_ABRE  Auto Baud rate detection error flag
00892   *            @arg @ref UART_FLAG_CTS   CTS Change flag
00893   *            @arg @ref UART_FLAG_LBDF  LIN Break detection flag
00894   *            @arg @ref UART_FLAG_TXE   Transmit data register empty flag
00895   *            @arg @ref UART_FLAG_TXFNF UART TXFIFO not full flag
00896   *            @arg @ref UART_FLAG_TC    Transmission Complete flag
00897   *            @arg @ref UART_FLAG_RXNE  Receive data register not empty flag
00898   *            @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag
00899   *            @arg @ref UART_FLAG_RTOF  Receiver Timeout flag
00900   *            @arg @ref UART_FLAG_IDLE  Idle Line detection flag
00901   *            @arg @ref UART_FLAG_ORE   Overrun Error flag
00902   *            @arg @ref UART_FLAG_NE    Noise Error flag
00903   *            @arg @ref UART_FLAG_FE    Framing Error flag
00904   *            @arg @ref UART_FLAG_PE    Parity Error flag
00905   * @retval The new state of __FLAG__ (TRUE or FALSE).
00906   */
00907 #define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
00908
00909 /** @brief  Enable the specified UART interrupt.
00910   * @param  __HANDLE__ specifies the UART Handle.
00911   * @param  __INTERRUPT__ specifies the UART interrupt source to enable.
00912   *          This parameter can be one of the following values:
00913   *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
00914   *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
00915   *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
00916   *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
00917   *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
00918   *            @arg @ref UART_IT_CM    Character match interrupt
00919   *            @arg @ref UART_IT_CTS   CTS change interrupt
00920   *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
00921   *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
00922   *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
00923   *            @arg @ref UART_IT_TC    Transmission complete interrupt
00924   *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
00925   *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
00926   *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
00927   *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
00928   *            @arg @ref UART_IT_PE    Parity Error interrupt
00929   *            @arg @ref UART_IT_ERR   Error interrupt (frame error, noise error, overrun error)
00930   * @retval None
00931   */
00932 #define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
00933                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
00934                                                            ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))
00935
00936
00937 /** @brief  Disable the specified UART interrupt.
00938   * @param  __HANDLE__ specifies the UART Handle.
00939   * @param  __INTERRUPT__ specifies the UART interrupt source to disable.
00940   *          This parameter can be one of the following values:
00941   *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
00942   *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
00943   *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
00944   *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
00945   *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
00946   *            @arg @ref UART_IT_CM    Character match interrupt
00947   *            @arg @ref UART_IT_CTS   CTS change interrupt
00948   *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
00949   *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
00950   *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
00951   *            @arg @ref UART_IT_TC    Transmission complete interrupt
00952   *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
00953   *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
00954   *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
00955   *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
00956   *            @arg @ref UART_IT_PE    Parity Error interrupt
00957   *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)
00958   * @retval None
00959   */
00960 #define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
00961                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
00962                                                            ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))
00963
00964 /** @brief  Check whether the specified UART interrupt has occurred or not.
00965   * @param  __HANDLE__ specifies the UART Handle.
00966   * @param  __INTERRUPT__ specifies the UART interrupt to check.
00967   *          This parameter can be one of the following values:
00968   *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
00969   *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
00970   *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
00971   *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
00972   *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
00973   *            @arg @ref UART_IT_CM    Character match interrupt
00974   *            @arg @ref UART_IT_CTS   CTS change interrupt
00975   *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
00976   *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
00977   *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
00978   *            @arg @ref UART_IT_TC    Transmission complete interrupt
00979   *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
00980   *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
00981   *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
00982   *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
00983   *            @arg @ref UART_IT_PE    Parity Error interrupt
00984   *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)
00985   * @retval The new state of __INTERRUPT__ (SET or RESET).
00986   */
00987 #define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
00988                                                         & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET)
00989
00990 /** @brief  Check whether the specified UART interrupt source is enabled or not.
00991   * @param  __HANDLE__ specifies the UART Handle.
00992   * @param  __INTERRUPT__ specifies the UART interrupt source to check.
00993   *          This parameter can be one of the following values:
00994   *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
00995   *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
00996   *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
00997   *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
00998   *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
00999   *            @arg @ref UART_IT_CM    Character match interrupt
01000   *            @arg @ref UART_IT_CTS   CTS change interrupt
01001   *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
01002   *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
01003   *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
01004   *            @arg @ref UART_IT_TC    Transmission complete interrupt
01005   *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
01006   *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
01007   *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
01008   *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
01009   *            @arg @ref UART_IT_PE    Parity Error interrupt
01010   *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)
01011   * @retval The new state of __INTERRUPT__ (SET or RESET).
01012   */
01013 #define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : \
01014                                                                 (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \
01015                                                                  (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK)))  != RESET) ? SET : RESET)
01016
01017 /** @brief  Clear the specified UART ISR flag, in setting the proper ICR register flag.
01018   * @param  __HANDLE__ specifies the UART Handle.
01019   * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
01020   *                       to clear the corresponding interrupt
01021   *          This parameter can be one of the following values:
01022   *            @arg @ref UART_CLEAR_PEF    Parity Error Clear Flag
01023   *            @arg @ref UART_CLEAR_FEF    Framing Error Clear Flag
01024   *            @arg @ref UART_CLEAR_NEF    Noise detected Clear Flag
01025   *            @arg @ref UART_CLEAR_OREF   Overrun Error Clear Flag
01026   *            @arg @ref UART_CLEAR_IDLEF  IDLE line detected Clear Flag
01027   *            @arg @ref UART_CLEAR_RTOF   Receiver timeout clear flag
01028   *            @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag
01029   *            @arg @ref UART_CLEAR_TCF    Transmission Complete Clear Flag
01030   *            @arg @ref UART_CLEAR_LBDF   LIN Break Detection Clear Flag
01031   *            @arg @ref UART_CLEAR_CTSF   CTS Interrupt Clear Flag
01032   *            @arg @ref UART_CLEAR_CMF    Character Match Clear Flag
01033   *            @arg @ref UART_CLEAR_WUF    Wake Up from stop mode Clear Flag
01034   * @retval None
01035   */
01036 #define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
01037
01038 /** @brief  Set a specific UART request flag.
01039   * @param  __HANDLE__ specifies the UART Handle.
01040   * @param  __REQ__ specifies the request flag to set
01041   *          This parameter can be one of the following values:
01042   *            @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request
01043   *            @arg @ref UART_SENDBREAK_REQUEST Send Break Request
01044   *            @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request
01045   *            @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request
01046   *            @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request
01047   * @retval None
01048   */
01049 #define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
01050
01051 /** @brief  Enable the UART one bit sample method.
01052   * @param  __HANDLE__ specifies the UART Handle.
01053   * @retval None
01054   */
01055 #define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
01056
01057 /** @brief  Disable the UART one bit sample method.
01058   * @param  __HANDLE__ specifies the UART Handle.
01059   * @retval None
01060   */
01061 #define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
01062
01063 /** @brief  Enable UART.
01064   * @param  __HANDLE__ specifies the UART Handle.
01065   * @retval None
01066   */
01067 #define __HAL_UART_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
01068
01069 /** @brief  Disable UART.
01070   * @param  __HANDLE__ specifies the UART Handle.
01071   * @retval None
01072   */
01073 #define __HAL_UART_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
01074
01075 /** @brief  Enable CTS flow control.
01076   * @note   This macro allows to enable CTS hardware flow control for a given UART instance,
01077   *         without need to call HAL_UART_Init() function.
01078   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
01079   * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
01080   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
01081   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
01082   *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
01083   *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
01084   * @param  __HANDLE__ specifies the UART Handle.
01085   * @retval None
01086   */
01087 #define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)        \
01088   do{                                                      \
01089     SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
01090     (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;        \
01091   } while(0U)
01092
01093 /** @brief  Disable CTS flow control.
01094   * @note   This macro allows to disable CTS hardware flow control for a given UART instance,
01095   *         without need to call HAL_UART_Init() function.
01096   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
01097   * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
01098   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
01099   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
01100   *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
01101   *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
01102   * @param  __HANDLE__ specifies the UART Handle.
01103   * @retval None
01104   */
01105 #define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)        \
01106   do{                                                       \
01107     CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
01108     (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);      \
01109   } while(0U)
01110
01111 /** @brief  Enable RTS flow control.
01112   * @note   This macro allows to enable RTS hardware flow control for a given UART instance,
01113   *         without need to call HAL_UART_Init() function.
01114   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
01115   * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
01116   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
01117   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
01118   *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
01119   *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
01120   * @param  __HANDLE__ specifies the UART Handle.
01121   * @retval None
01122   */
01123 #define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)       \
01124   do{                                                     \
01125     SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
01126     (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;       \
01127   } while(0U)
01128
01129 /** @brief  Disable RTS flow control.
01130   * @note   This macro allows to disable RTS hardware flow control for a given UART instance,
01131   *         without need to call HAL_UART_Init() function.
01132   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
01133   * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
01134   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
01135   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
01136   *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
01137   *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
01138   * @param  __HANDLE__ specifies the UART Handle.
01139   * @retval None
01140   */
01141 #define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)       \
01142   do{                                                      \
01143     CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
01144     (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);     \
01145   } while(0U)
01146 /**
01147   * @}
01148   */
01149
01150 /* Private macros --------------------------------------------------------*/
01151 /** @defgroup UART_Private_Macros   UART Private Macros
01152   * @{
01153   */
01154 /** @brief  Get UART clok division factor from clock prescaler value.
01155   * @param  __CLOCKPRESCALER__ UART prescaler value.
01156   * @retval UART clock division factor
01157   */
01158 #define UART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \
01159   (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1)   ? 1U :       \
01160    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2)   ? 2U :       \
01161    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4)   ? 4U :       \
01162    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6)   ? 6U :       \
01163    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8)   ? 8U :       \
01164    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10)  ? 10U :      \
01165    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12)  ? 12U :      \
01166    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16)  ? 16U :      \
01167    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32)  ? 32U :      \
01168    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64)  ? 64U :      \
01169    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U :     \
01170    ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U)
01171
01172 #if defined(LPUART1)
01173 /** @brief  BRR division operation to set BRR register with LPUART.
01174   * @param  __PCLK__ LPUART clock.
01175   * @param  __BAUD__ Baud rate set by the user.
01176   * @param  __CLOCKPRESCALER__ UART prescaler value.
01177   * @retval Division result
01178   */
01179 #define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__)      ((uint32_t)(((((uint64_t)(__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*256U)\
01180                                                                       + (uint32_t)((__BAUD__)/2U)) / (__BAUD__)))
01181 #endif
01182
01183 /** @brief  BRR division operation to set BRR register in 8-bit oversampling mode.
01184   * @param  __PCLK__ UART clock.
01185   * @param  __BAUD__ Baud rate set by the user.
01186   * @param  __CLOCKPRESCALER__ UART prescaler value.
01187   * @retval Division result
01188   */
01189 #define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)   (((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*2U)\
01190                                                                        + ((__BAUD__)/2U)) / (__BAUD__))
01191
01192 /** @brief  BRR division operation to set BRR register in 16-bit oversampling mode.
01193   * @param  __PCLK__ UART clock.
01194   * @param  __BAUD__ Baud rate set by the user.
01195   * @param  __CLOCKPRESCALER__ UART prescaler value.
01196   * @retval Division result
01197   */
01198 #define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__)  ((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))\
01199                                                                        + ((__BAUD__)/2U)) / (__BAUD__))
01200
01201 #if defined(LPUART1)
01202 /** @brief  Check whether or not UART instance is Low Power UART.
01203   * @param  __HANDLE__ specifies the UART Handle.
01204   * @retval SET (instance is LPUART) or RESET (instance isn't LPUART)
01205   */
01206 #define UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance))
01207 #endif
01208
01209 /** @brief  Check UART Baud rate.
01210   * @param  __BAUDRATE__ Baudrate specified by the user.
01211   *         The maximum Baud Rate is derived from the maximum clock on WB (i.e. 64 MHz)
01212   *         divided by the smallest oversampling used on the USART (i.e. 8)
01213   * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)
01214   */
01215 #define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 8000001U)
01216
01217 /** @brief  Check UART assertion time.
01218   * @param  __TIME__ 5-bit value assertion time.
01219   * @retval Test result (TRUE or FALSE).
01220   */
01221 #define IS_UART_ASSERTIONTIME(__TIME__)    ((__TIME__) <= 0x1FU)
01222
01223 /** @brief  Check UART deassertion time.
01224   * @param  __TIME__ 5-bit value deassertion time.
01225   * @retval Test result (TRUE or FALSE).
01226   */
01227 #define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
01228
01229 /**
01230   * @brief Ensure that UART frame number of stop bits is valid.
01231   * @param __STOPBITS__ UART frame number of stop bits.
01232   * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
01233   */
01234 #define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \
01235                                         ((__STOPBITS__) == UART_STOPBITS_1)   || \
01236                                         ((__STOPBITS__) == UART_STOPBITS_1_5) || \
01237                                         ((__STOPBITS__) == UART_STOPBITS_2))
01238
01239 #if defined(LPUART1)
01240 /**
01241   * @brief Ensure that LPUART frame number of stop bits is valid.
01242   * @param __STOPBITS__ LPUART frame number of stop bits.
01243   * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
01244   */
01245 #define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \
01246                                           ((__STOPBITS__) == UART_STOPBITS_2))
01247 #endif
01248
01249 /**
01250   * @brief Ensure that UART frame parity is valid.
01251   * @param __PARITY__ UART frame parity.
01252   * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
01253   */
01254 #define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \
01255                                     ((__PARITY__) == UART_PARITY_EVEN) || \
01256                                     ((__PARITY__) == UART_PARITY_ODD))
01257
01258 /**
01259   * @brief Ensure that UART hardware flow control is valid.
01260   * @param __CONTROL__ UART hardware flow control.
01261   * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)
01262   */
01263 #define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\
01264   (((__CONTROL__) == UART_HWCONTROL_NONE) || \
01265    ((__CONTROL__) == UART_HWCONTROL_RTS)  || \
01266    ((__CONTROL__) == UART_HWCONTROL_CTS)  || \
01267    ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
01268
01269 /**
01270   * @brief Ensure that UART communication mode is valid.
01271   * @param __MODE__ UART communication mode.
01272   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
01273   */
01274 #define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
01275
01276 /**
01277   * @brief Ensure that UART state is valid.
01278   * @param __STATE__ UART state.
01279   * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
01280   */
01281 #define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \
01282                                   ((__STATE__) == UART_STATE_ENABLE))
01283
01284 /**
01285   * @brief Ensure that UART oversampling is valid.
01286   * @param __SAMPLING__ UART oversampling.
01287   * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
01288   */
01289 #define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \
01290                                             ((__SAMPLING__) == UART_OVERSAMPLING_8))
01291
01292 /**
01293   * @brief Ensure that UART frame sampling is valid.
01294   * @param __ONEBIT__ UART frame sampling.
01295   * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
01296   */
01297 #define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \
01298                                             ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))
01299
01300 /**
01301   * @brief Ensure that UART auto Baud rate detection mode is valid.
01302   * @param __MODE__ UART auto Baud rate detection mode.
01303   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
01304   */
01305 #define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__)  (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT)    || \
01306                                                         ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
01307                                                         ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME)   || \
01308                                                         ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
01309
01310 /**
01311   * @brief Ensure that UART receiver timeout setting is valid.
01312   * @param __TIMEOUT__ UART receiver timeout setting.
01313   * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
01314   */
01315 #define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__)  (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
01316                                                 ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
01317
01318 /** @brief  Check the receiver timeout value.
01319   * @note   The maximum UART receiver timeout value is 0xFFFFFF.
01320   * @param  __TIMEOUTVALUE__ receiver timeout value.
01321   * @retval Test result (TRUE or FALSE)
01322   */
01323 #define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__)  ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
01324
01325 /**
01326   * @brief Ensure that UART LIN state is valid.
01327   * @param __LIN__ UART LIN state.
01328   * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid)
01329   */
01330 #define IS_UART_LIN(__LIN__)        (((__LIN__) == UART_LIN_DISABLE) || \
01331                                      ((__LIN__) == UART_LIN_ENABLE))
01332
01333 /**
01334   * @brief Ensure that UART LIN break detection length is valid.
01335   * @param __LENGTH__ UART LIN break detection length.
01336   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
01337   */
01338 #define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
01339                                                      ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))
01340
01341 /**
01342   * @brief Ensure that UART DMA TX state is valid.
01343   * @param __DMATX__ UART DMA TX state.
01344   * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
01345   */
01346 #define IS_UART_DMA_TX(__DMATX__)     (((__DMATX__) == UART_DMA_TX_DISABLE) || \
01347                                        ((__DMATX__) == UART_DMA_TX_ENABLE))
01348
01349 /**
01350   * @brief Ensure that UART DMA RX state is valid.
01351   * @param __DMARX__ UART DMA RX state.
01352   * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
01353   */
01354 #define IS_UART_DMA_RX(__DMARX__)     (((__DMARX__) == UART_DMA_RX_DISABLE) || \
01355                                        ((__DMARX__) == UART_DMA_RX_ENABLE))
01356
01357 /**
01358   * @brief Ensure that UART half-duplex state is valid.
01359   * @param __HDSEL__ UART half-duplex state.
01360   * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)
01361   */
01362 #define IS_UART_HALF_DUPLEX(__HDSEL__)     (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \
01363                                             ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))
01364
01365 /**
01366   * @brief Ensure that UART wake-up method is valid.
01367   * @param __WAKEUP__ UART wake-up method .
01368   * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)
01369   */
01370 #define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \
01371                                           ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))
01372
01373 /**
01374   * @brief Ensure that UART request parameter is valid.
01375   * @param __PARAM__ UART request parameter.
01376   * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
01377   */
01378 #define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST)     || \
01379                                               ((__PARAM__) == UART_SENDBREAK_REQUEST)    || \
01380                                               ((__PARAM__) == UART_MUTE_MODE_REQUEST)    || \
01381                                               ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \
01382                                               ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))
01383
01384 /**
01385   * @brief Ensure that UART advanced features initialization is valid.
01386   * @param __INIT__ UART advanced features initialization.
01387   * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
01388   */
01389 #define IS_UART_ADVFEATURE_INIT(__INIT__)   ((__INIT__) <= (UART_ADVFEATURE_NO_INIT                | \
01390                                                             UART_ADVFEATURE_TXINVERT_INIT          | \
01391                                                             UART_ADVFEATURE_RXINVERT_INIT          | \
01392                                                             UART_ADVFEATURE_DATAINVERT_INIT        | \
01393                                                             UART_ADVFEATURE_SWAP_INIT              | \
01394                                                             UART_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
01395                                                             UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
01396                                                             UART_ADVFEATURE_AUTOBAUDRATE_INIT      | \
01397                                                             UART_ADVFEATURE_MSBFIRST_INIT))
01398
01399 /**
01400   * @brief Ensure that UART frame TX inversion setting is valid.
01401   * @param __TXINV__ UART frame TX inversion setting.
01402   * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
01403   */
01404 #define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \
01405                                              ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))
01406
01407 /**
01408   * @brief Ensure that UART frame RX inversion setting is valid.
01409   * @param __RXINV__ UART frame RX inversion setting.
01410   * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
01411   */
01412 #define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \
01413                                              ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))
01414
01415 /**
01416   * @brief Ensure that UART frame data inversion setting is valid.
01417   * @param __DATAINV__ UART frame data inversion setting.
01418   * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
01419   */
01420 #define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \
01421                                                  ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))
01422
01423 /**
01424   * @brief Ensure that UART frame RX/TX pins swap setting is valid.
01425   * @param __SWAP__ UART frame RX/TX pins swap setting.
01426   * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
01427   */
01428 #define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \
01429                                            ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))
01430
01431 /**
01432   * @brief Ensure that UART frame overrun setting is valid.
01433   * @param __OVERRUN__ UART frame overrun setting.
01434   * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
01435   */
01436 #define IS_UART_OVERRUN(__OVERRUN__)     (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
01437                                           ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))
01438
01439 /**
01440   * @brief Ensure that UART auto Baud rate state is valid.
01441   * @param __AUTOBAUDRATE__ UART auto Baud rate state.
01442   * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)
01443   */
01444 #define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__)  (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
01445                                                             ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
01446
01447 /**
01448   * @brief Ensure that UART DMA enabling or disabling on error setting is valid.
01449   * @param __DMA__ UART DMA enabling or disabling on error setting.
01450   * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
01451   */
01452 #define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__)  (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
01453                                                    ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))
01454
01455 /**
01456   * @brief Ensure that UART frame MSB first setting is valid.
01457   * @param __MSBFIRST__ UART frame MSB first setting.
01458   * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
01459   */
01460 #define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
01461                                                    ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))
01462
01463 /**
01464   * @brief Ensure that UART stop mode state is valid.
01465   * @param __STOPMODE__ UART stop mode state.
01466   * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)
01467   */
01468 #define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
01469                                                    ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))
01470
01471 /**
01472   * @brief Ensure that UART mute mode state is valid.
01473   * @param __MUTE__ UART mute mode state.
01474   * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)
01475   */
01476 #define IS_UART_MUTE_MODE(__MUTE__)       (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
01477                                            ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))
01478
01479 /**
01480   * @brief Ensure that UART wake-up selection is valid.
01481   * @param __WAKE__ UART wake-up selection.
01482   * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)
01483   */
01484 #define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS)           || \
01485                                             ((__WAKE__) == UART_WAKEUP_ON_STARTBIT)          || \
01486                                             ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))
01487
01488 /**
01489   * @brief Ensure that UART driver enable polarity is valid.
01490   * @param __POLARITY__ UART driver enable polarity.
01491   * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)
01492   */
01493 #define IS_UART_DE_POLARITY(__POLARITY__)    (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \
01494                                               ((__POLARITY__) == UART_DE_POLARITY_LOW))
01495
01496 /**
01497   * @brief Ensure that UART Prescaler is valid.
01498   * @param __CLOCKPRESCALER__ UART Prescaler value.
01499   * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
01500   */
01501 #define IS_UART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1)   || \
01502                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2)   || \
01503                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4)   || \
01504                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6)   || \
01505                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8)   || \
01506                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10)  || \
01507                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12)  || \
01508                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16)  || \
01509                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32)  || \
01510                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64)  || \
01511                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) || \
01512                                                ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256))
01513
01514 /**
01515   * @}
01516   */
01517
01518 /* Include UART HAL Extended module */
01519 #include "stm32wbxx_hal_uart_ex.h"
01520
01521
01522 /* Exported functions --------------------------------------------------------*/
01523 /** @addtogroup UART_Exported_Functions UART Exported Functions
01524   * @{
01525   */
01526
01527 /** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
01528   * @{
01529   */
01530
01531 /* Initialization and de-initialization functions  ****************************/
01532 HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
01533 HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
01534 HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
01535 HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
01536 HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart);
01537 void HAL_UART_MspInit(UART_HandleTypeDef *huart);
01538 void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
01539
01540 /* Callbacks Register/UnRegister functions  ***********************************/
01541 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
01542 HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
01543                                             pUART_CallbackTypeDef pCallback);
01544 HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
01545 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
01546
01547 /**
01548   * @}
01549   */
01550
01551 /** @addtogroup UART_Exported_Functions_Group2 IO operation functions
01552   * @{
01553   */
01554
01555 /* IO operation functions *****************************************************/
01556 HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
01557 HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
01558 HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
01559 HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
01560 HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
01561 HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
01562 HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
01563 HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
01564 HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
01565 /* Transfer Abort functions */
01566 HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
01567 HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
01568 HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
01569 HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
01570 HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
01571 HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
01572
01573 void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
01574 void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
01575 void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
01576 void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
01577 void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
01578 void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
01579 void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);
01580 void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);
01581 void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
01582
01583 /**
01584   * @}
01585   */
01586
01587 /** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions
01588   * @{
01589   */
01590
01591 /* Peripheral Control functions  ************************************************/
01592 void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue);
01593 HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart);
01594 HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart);
01595
01596 HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
01597 HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
01598 HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
01599 void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
01600 HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
01601 HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
01602
01603 /**
01604   * @}
01605   */
01606
01607 /** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions
01608   * @{
01609   */
01610
01611 /* Peripheral State and Errors functions  **************************************************/
01612 HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
01613 uint32_t              HAL_UART_GetError(UART_HandleTypeDef *huart);
01614
01615 /**
01616   * @}
01617   */
01618
01619 /**
01620   * @}
01621   */
01622
01623 /* Private functions -----------------------------------------------------------*/
01624 /** @addtogroup UART_Private_Functions UART Private Functions
01625   * @{
01626   */
01627 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
01628 void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
01629 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
01630 HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
01631 HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
01632 HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
01633                                               uint32_t Tickstart, uint32_t Timeout);
01634 void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
01635
01636 /**
01637   * @}
01638   */
01639
01640 /**
01641   * @}
01642   */
01643
01644 /**
01645   * @}
01646   */
01647
01648 #ifdef __cplusplus
01649 }
01650 #endif
01651
01652 #endif /* STM32WBxx_HAL_UART_H */
01653
01654 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_uart_ex.c Source File

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stm32wbxx_hal_uart_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_uart_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended UART HAL module driver.
00006   *          This file provides firmware functions to manage the following extended
00007   *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
00008   *           + Initialization and de-initialization functions
00009   *           + Peripheral Control functions
00010   *
00011   *
00012   @verbatim
00013   ==============================================================================
00014                ##### UART peripheral extended features  #####
00015   ==============================================================================
00016
00017     (#) Declare a UART_HandleTypeDef handle structure.
00018
00019     (#) For the UART RS485 Driver Enable mode, initialize the UART registers
00020         by calling the HAL_RS485Ex_Init() API.
00021
00022     (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
00023
00024         -@- When UART operates in FIFO mode, FIFO mode must be enabled prior
00025             starting RX/TX transfers. Also RX/TX FIFO thresholds must be
00026             configured prior starting RX/TX transfers.
00027
00028   @endverbatim
00029   ******************************************************************************
00030   * @attention
00031   *
00032   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00033   * All rights reserved.</center></h2>
00034   *
00035   * This software component is licensed by ST under BSD 3-Clause license,
00036   * the "License"; You may not use this file except in compliance with the
00037   * License. You may obtain a copy of the License at:
00038   *                        opensource.org/licenses/BSD-3-Clause
00039   *
00040   ******************************************************************************
00041   */
00042
00043 /* Includes ------------------------------------------------------------------*/
00044 #include "stm32wbxx_hal.h"
00045
00046 /** @addtogroup STM32WBxx_HAL_Driver
00047   * @{
00048   */
00049
00050 /** @defgroup UARTEx UARTEx
00051   * @brief UART Extended HAL module driver
00052   * @{
00053   */
00054
00055 #ifdef HAL_UART_MODULE_ENABLED
00056
00057 /* Private typedef -----------------------------------------------------------*/
00058 /* Private define ------------------------------------------------------------*/
00059 /** @defgroup UARTEX_Private_Constants UARTEx Private Constants
00060   * @{
00061   */
00062 /* UART RX FIFO depth */
00063 #define RX_FIFO_DEPTH 8U
00064
00065 /* UART TX FIFO depth */
00066 #define TX_FIFO_DEPTH 8U
00067 /**
00068   * @}
00069   */
00070
00071 /* Private macros ------------------------------------------------------------*/
00072 /* Private variables ---------------------------------------------------------*/
00073 /* Private function prototypes -----------------------------------------------*/
00074 /** @defgroup UARTEx_Private_Functions UARTEx Private Functions
00075   * @{
00076   */
00077 static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
00078 static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart);
00079 /**
00080   * @}
00081   */
00082
00083 /* Exported functions --------------------------------------------------------*/
00084
00085 /** @defgroup UARTEx_Exported_Functions  UARTEx Exported Functions
00086   * @{
00087   */
00088
00089 /** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions
00090   * @brief    Extended Initialization and Configuration Functions
00091   *
00092 @verbatim
00093 ===============================================================================
00094             ##### Initialization and Configuration functions #####
00095  ===============================================================================
00096     [..]
00097     This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
00098     in asynchronous mode.
00099       (+) For the asynchronous mode the parameters below can be configured:
00100         (++) Baud Rate
00101         (++) Word Length
00102         (++) Stop Bit
00103         (++) Parity: If the parity is enabled, then the MSB bit of the data written
00104              in the data register is transmitted but is changed by the parity bit.
00105         (++) Hardware flow control
00106         (++) Receiver/transmitter modes
00107         (++) Over Sampling Method
00108         (++) One-Bit Sampling Method
00109       (+) For the asynchronous mode, the following advanced features can be configured as well:
00110         (++) TX and/or RX pin level inversion
00111         (++) data logical level inversion
00112         (++) RX and TX pins swap
00113         (++) RX overrun detection disabling
00114         (++) DMA disabling on RX error
00115         (++) MSB first on communication line
00116         (++) auto Baud rate detection
00117     [..]
00118     The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration
00119      procedures (details for the procedures are available in reference manual).
00120
00121 @endverbatim
00122
00123   Depending on the frame length defined by the M1 and M0 bits (7-bit,
00124   8-bit or 9-bit), the possible UART formats are listed in the
00125   following table.
00126
00127     Table 1. UART frame format.
00128     +-----------------------------------------------------------------------+
00129     |  M1 bit |  M0 bit |  PCE bit  |             UART frame                |
00130     |---------|---------|-----------|---------------------------------------|
00131     |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
00132     |---------|---------|-----------|---------------------------------------|
00133     |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
00134     |---------|---------|-----------|---------------------------------------|
00135     |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
00136     |---------|---------|-----------|---------------------------------------|
00137     |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
00138     |---------|---------|-----------|---------------------------------------|
00139     |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
00140     |---------|---------|-----------|---------------------------------------|
00141     |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
00142     +-----------------------------------------------------------------------+
00143
00144   * @{
00145   */
00146
00147 /**
00148   * @brief Initialize the RS485 Driver enable feature according to the specified
00149   *         parameters in the UART_InitTypeDef and creates the associated handle.
00150   * @param huart            UART handle.
00151   * @param Polarity         Select the driver enable polarity.
00152   *          This parameter can be one of the following values:
00153   *          @arg @ref UART_DE_POLARITY_HIGH DE signal is active high
00154   *          @arg @ref UART_DE_POLARITY_LOW  DE signal is active low
00155   * @param AssertionTime    Driver Enable assertion time:
00156   *       5-bit value defining the time between the activation of the DE (Driver Enable)
00157   *       signal and the beginning of the start bit. It is expressed in sample time
00158   *       units (1/8 or 1/16 bit time, depending on the oversampling rate)
00159   * @param DeassertionTime  Driver Enable deassertion time:
00160   *       5-bit value defining the time between the end of the last stop bit, in a
00161   *       transmitted message, and the de-activation of the DE (Driver Enable) signal.
00162   *       It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
00163   *       oversampling rate).
00164   * @retval HAL status
00165   */
00166 HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
00167                                    uint32_t DeassertionTime)
00168 {
00169   uint32_t temp;
00170
00171   /* Check the UART handle allocation */
00172   if (huart == NULL)
00173   {
00174     return HAL_ERROR;
00175   }
00176   /* Check the Driver Enable UART instance */
00177   assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
00178
00179   /* Check the Driver Enable polarity */
00180   assert_param(IS_UART_DE_POLARITY(Polarity));
00181
00182   /* Check the Driver Enable assertion time */
00183   assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
00184
00185   /* Check the Driver Enable deassertion time */
00186   assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
00187
00188   if (huart->gState == HAL_UART_STATE_RESET)
00189   {
00190     /* Allocate lock resource and initialize it */
00191     huart->Lock = HAL_UNLOCKED;
00192
00193 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
00194     UART_InitCallbacksToDefault(huart);
00195
00196     if (huart->MspInitCallback == NULL)
00197     {
00198       huart->MspInitCallback = HAL_UART_MspInit;
00199     }
00200
00201     /* Init the low level hardware */
00202     huart->MspInitCallback(huart);
00203 #else
00204     /* Init the low level hardware : GPIO, CLOCK, CORTEX */
00205     HAL_UART_MspInit(huart);
00206 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
00207   }
00208
00209   huart->gState = HAL_UART_STATE_BUSY;
00210
00211   /* Disable the Peripheral */
00212   __HAL_UART_DISABLE(huart);
00213
00214   /* Set the UART Communication parameters */
00215   if (UART_SetConfig(huart) == HAL_ERROR)
00216   {
00217     return HAL_ERROR;
00218   }
00219
00220   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
00221   {
00222     UART_AdvFeatureConfig(huart);
00223   }
00224
00225   /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
00226   SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
00227
00228   /* Set the Driver Enable polarity */
00229   MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
00230
00231   /* Set the Driver Enable assertion and deassertion times */
00232   temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
00233   temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
00234   MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);
00235
00236   /* Enable the Peripheral */
00237   __HAL_UART_ENABLE(huart);
00238
00239   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
00240   return (UART_CheckIdleState(huart));
00241 }
00242
00243 /**
00244   * @}
00245   */
00246
00247 /** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions
00248   *  @brief Extended functions
00249   *
00250 @verbatim
00251  ===============================================================================
00252                       ##### IO operation functions #####
00253  ===============================================================================
00254     This subsection provides a set of Wakeup and FIFO mode related callback functions.
00255
00256     (#) Wakeup from Stop mode Callback:
00257         (+) HAL_UARTEx_WakeupCallback()
00258
00259     (#) TX/RX Fifos Callbacks:
00260         (+) HAL_UARTEx_RxFifoFullCallback()
00261         (+) HAL_UARTEx_TxFifoEmptyCallback()
00262
00263 @endverbatim
00264   * @{
00265   */
00266
00267 /**
00268   * @brief UART wakeup from Stop mode callback.
00269   * @param huart UART handle.
00270   * @retval None
00271   */
00272 __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
00273 {
00274   /* Prevent unused argument(s) compilation warning */
00275   UNUSED(huart);
00276
00277   /* NOTE : This function should not be modified, when the callback is needed,
00278             the HAL_UARTEx_WakeupCallback can be implemented in the user file.
00279    */
00280 }
00281
00282 /**
00283   * @brief  UART RX Fifo full callback.
00284   * @param  huart UART handle.
00285   * @retval None
00286   */
00287 __weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart)
00288 {
00289   /* Prevent unused argument(s) compilation warning */
00290   UNUSED(huart);
00291
00292   /* NOTE : This function should not be modified, when the callback is needed,
00293             the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file.
00294    */
00295 }
00296
00297 /**
00298   * @brief  UART TX Fifo empty callback.
00299   * @param  huart UART handle.
00300   * @retval None
00301   */
00302 __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart)
00303 {
00304   /* Prevent unused argument(s) compilation warning */
00305   UNUSED(huart);
00306
00307   /* NOTE : This function should not be modified, when the callback is needed,
00308             the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file.
00309    */
00310 }
00311
00312 /**
00313   * @}
00314   */
00315
00316 /** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions
00317   * @brief    Extended Peripheral Control functions
00318   *
00319 @verbatim
00320  ===============================================================================
00321                       ##### Peripheral Control functions #####
00322  ===============================================================================
00323     [..] This section provides the following functions:
00324      (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
00325          detection length to more than 4 bits for multiprocessor address mark wake up.
00326      (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode
00327          trigger: address match, Start Bit detection or RXNE bit status.
00328      (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode
00329      (+) HAL_UARTEx_DisableStopMode() API disables the above functionality
00330      (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode
00331      (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode
00332      (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
00333      (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold
00334
00335 @endverbatim
00336   * @{
00337   */
00338
00339 /**
00340   * @brief By default in multiprocessor mode, when the wake up method is set
00341   *        to address mark, the UART handles only 4-bit long addresses detection;
00342   *        this API allows to enable longer addresses detection (6-, 7- or 8-bit
00343   *        long).
00344   * @note  Addresses detection lengths are: 6-bit address detection in 7-bit data mode,
00345   *        7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
00346   * @param huart         UART handle.
00347   * @param AddressLength This parameter can be one of the following values:
00348   *          @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
00349   *          @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
00350   * @retval HAL status
00351   */
00352 HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
00353 {
00354   /* Check the UART handle allocation */
00355   if (huart == NULL)
00356   {
00357     return HAL_ERROR;
00358   }
00359
00360   /* Check the address length parameter */
00361   assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
00362
00363   huart->gState = HAL_UART_STATE_BUSY;
00364
00365   /* Disable the Peripheral */
00366   __HAL_UART_DISABLE(huart);
00367
00368   /* Set the address length */
00369   MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
00370
00371   /* Enable the Peripheral */
00372   __HAL_UART_ENABLE(huart);
00373
00374   /* TEACK and/or REACK to check before moving huart->gState to Ready */
00375   return (UART_CheckIdleState(huart));
00376 }
00377
00378 /**
00379   * @brief Set Wakeup from Stop mode interrupt flag selection.
00380   * @note It is the application responsibility to enable the interrupt used as
00381   *       usart_wkup interrupt source before entering low-power mode.
00382   * @param huart           UART handle.
00383   * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status.
00384   *          This parameter can be one of the following values:
00385   *          @arg @ref UART_WAKEUP_ON_ADDRESS
00386   *          @arg @ref UART_WAKEUP_ON_STARTBIT
00387   *          @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY
00388   * @retval HAL status
00389   */
00390 HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
00391 {
00392   HAL_StatusTypeDef status = HAL_OK;
00393   uint32_t tickstart;
00394
00395   /* check the wake-up from stop mode UART instance */
00396   assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
00397   /* check the wake-up selection parameter */
00398   assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));
00399
00400   /* Process Locked */
00401   __HAL_LOCK(huart);
00402
00403   huart->gState = HAL_UART_STATE_BUSY;
00404
00405   /* Disable the Peripheral */
00406   __HAL_UART_DISABLE(huart);
00407
00408   /* Set the wake-up selection scheme */
00409   MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);
00410
00411   if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)
00412   {
00413     UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection);
00414   }
00415
00416   /* Enable the Peripheral */
00417   __HAL_UART_ENABLE(huart);
00418
00419   /* Init tickstart for timeout managment*/
00420   tickstart = HAL_GetTick();
00421
00422   /* Wait until REACK flag is set */
00423   if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
00424   {
00425     status = HAL_TIMEOUT;
00426   }
00427   else
00428   {
00429     /* Initialize the UART State */
00430     huart->gState = HAL_UART_STATE_READY;
00431   }
00432
00433   /* Process Unlocked */
00434   __HAL_UNLOCK(huart);
00435
00436   return status;
00437 }
00438
00439 /**
00440   * @brief Enable UART Stop Mode.
00441   * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.
00442   * @param huart UART handle.
00443   * @retval HAL status
00444   */
00445 HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
00446 {
00447   /* Process Locked */
00448   __HAL_LOCK(huart);
00449
00450   /* Set UESM bit */
00451   SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
00452
00453   /* Process Unlocked */
00454   __HAL_UNLOCK(huart);
00455
00456   return HAL_OK;
00457 }
00458
00459 /**
00460   * @brief Disable UART Stop Mode.
00461   * @param huart UART handle.
00462   * @retval HAL status
00463   */
00464 HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
00465 {
00466   /* Process Locked */
00467   __HAL_LOCK(huart);
00468
00469   /* Clear UESM bit */
00470   CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
00471
00472   /* Process Unlocked */
00473   __HAL_UNLOCK(huart);
00474
00475   return HAL_OK;
00476 }
00477
00478 /**
00479   * @brief  Enable the FIFO mode.
00480   * @param huart      UART handle.
00481   * @retval HAL status
00482   */
00483 HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart)
00484 {
00485   uint32_t tmpcr1;
00486
00487   /* Check parameters */
00488   assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
00489
00490   /* Process Locked */
00491   __HAL_LOCK(huart);
00492
00493   huart->gState = HAL_UART_STATE_BUSY;
00494
00495   /* Save actual UART configuration */
00496   tmpcr1 = READ_REG(huart->Instance->CR1);
00497
00498   /* Disable UART */
00499   __HAL_UART_DISABLE(huart);
00500
00501   /* Enable FIFO mode */
00502   SET_BIT(tmpcr1, USART_CR1_FIFOEN);
00503   huart->FifoMode = UART_FIFOMODE_ENABLE;
00504
00505   /* Restore UART configuration */
00506   WRITE_REG(huart->Instance->CR1, tmpcr1);
00507
00508   /* Determine the number of data to process during RX/TX ISR execution */
00509   UARTEx_SetNbDataToProcess(huart);
00510
00511   huart->gState = HAL_UART_STATE_READY;
00512
00513   /* Process Unlocked */
00514   __HAL_UNLOCK(huart);
00515
00516   return HAL_OK;
00517 }
00518
00519 /**
00520   * @brief  Disable the FIFO mode.
00521   * @param huart      UART handle.
00522   * @retval HAL status
00523   */
00524 HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart)
00525 {
00526   uint32_t tmpcr1;
00527
00528   /* Check parameters */
00529   assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
00530
00531   /* Process Locked */
00532   __HAL_LOCK(huart);
00533
00534   huart->gState = HAL_UART_STATE_BUSY;
00535
00536   /* Save actual UART configuration */
00537   tmpcr1 = READ_REG(huart->Instance->CR1);
00538
00539   /* Disable UART */
00540   __HAL_UART_DISABLE(huart);
00541
00542   /* Enable FIFO mode */
00543   CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
00544   huart->FifoMode = UART_FIFOMODE_DISABLE;
00545
00546   /* Restore UART configuration */
00547   WRITE_REG(huart->Instance->CR1, tmpcr1);
00548
00549   huart->gState = HAL_UART_STATE_READY;
00550
00551   /* Process Unlocked */
00552   __HAL_UNLOCK(huart);
00553
00554   return HAL_OK;
00555 }
00556
00557 /**
00558   * @brief  Set the TXFIFO threshold.
00559   * @param huart      UART handle.
00560   * @param Threshold  TX FIFO threshold value
00561   *          This parameter can be one of the following values:
00562   *            @arg @ref UART_TXFIFO_THRESHOLD_1_8
00563   *            @arg @ref UART_TXFIFO_THRESHOLD_1_4
00564   *            @arg @ref UART_TXFIFO_THRESHOLD_1_2
00565   *            @arg @ref UART_TXFIFO_THRESHOLD_3_4
00566   *            @arg @ref UART_TXFIFO_THRESHOLD_7_8
00567   *            @arg @ref UART_TXFIFO_THRESHOLD_8_8
00568   * @retval HAL status
00569   */
00570 HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
00571 {
00572   uint32_t tmpcr1;
00573
00574   /* Check parameters */
00575   assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
00576   assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));
00577
00578   /* Process Locked */
00579   __HAL_LOCK(huart);
00580
00581   huart->gState = HAL_UART_STATE_BUSY;
00582
00583   /* Save actual UART configuration */
00584   tmpcr1 = READ_REG(huart->Instance->CR1);
00585
00586   /* Disable UART */
00587   __HAL_UART_DISABLE(huart);
00588
00589   /* Update TX threshold configuration */
00590   MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
00591
00592   /* Determine the number of data to process during RX/TX ISR execution */
00593   UARTEx_SetNbDataToProcess(huart);
00594
00595   /* Restore UART configuration */
00596   WRITE_REG(huart->Instance->CR1, tmpcr1);
00597
00598   huart->gState = HAL_UART_STATE_READY;
00599
00600   /* Process Unlocked */
00601   __HAL_UNLOCK(huart);
00602
00603   return HAL_OK;
00604 }
00605
00606 /**
00607   * @brief  Set the RXFIFO threshold.
00608   * @param huart      UART handle.
00609   * @param Threshold  RX FIFO threshold value
00610   *          This parameter can be one of the following values:
00611   *            @arg @ref UART_RXFIFO_THRESHOLD_1_8
00612   *            @arg @ref UART_RXFIFO_THRESHOLD_1_4
00613   *            @arg @ref UART_RXFIFO_THRESHOLD_1_2
00614   *            @arg @ref UART_RXFIFO_THRESHOLD_3_4
00615   *            @arg @ref UART_RXFIFO_THRESHOLD_7_8
00616   *            @arg @ref UART_RXFIFO_THRESHOLD_8_8
00617   * @retval HAL status
00618   */
00619 HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
00620 {
00621   uint32_t tmpcr1;
00622
00623   /* Check the parameters */
00624   assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
00625   assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold));
00626
00627   /* Process Locked */
00628   __HAL_LOCK(huart);
00629
00630   huart->gState = HAL_UART_STATE_BUSY;
00631
00632   /* Save actual UART configuration */
00633   tmpcr1 = READ_REG(huart->Instance->CR1);
00634
00635   /* Disable UART */
00636   __HAL_UART_DISABLE(huart);
00637
00638   /* Update RX threshold configuration */
00639   MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
00640
00641   /* Determine the number of data to process during RX/TX ISR execution */
00642   UARTEx_SetNbDataToProcess(huart);
00643
00644   /* Restore UART configuration */
00645   WRITE_REG(huart->Instance->CR1, tmpcr1);
00646
00647   huart->gState = HAL_UART_STATE_READY;
00648
00649   /* Process Unlocked */
00650   __HAL_UNLOCK(huart);
00651
00652   return HAL_OK;
00653 }
00654
00655 /**
00656   * @}
00657   */
00658
00659 /**
00660   * @}
00661   */
00662
00663 /** @addtogroup UARTEx_Private_Functions
00664   * @{
00665   */
00666
00667 /**
00668   * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection.
00669   * @param huart           UART handle.
00670   * @param WakeUpSelection UART wake up from stop mode parameters.
00671   * @retval None
00672   */
00673 static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
00674 {
00675   assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
00676
00677   /* Set the USART address length */
00678   MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);
00679
00680   /* Set the USART address node */
00681   MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
00682 }
00683
00684 /**
00685   * @brief Calculate the number of data to process in RX/TX ISR.
00686   * @note The RX FIFO depth and the TX FIFO depth is extracted from
00687   *       the UART configuration registers.
00688   * @param huart UART handle.
00689   * @retval None
00690   */
00691 static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)
00692 {
00693   uint8_t rx_fifo_depth;
00694   uint8_t tx_fifo_depth;
00695   uint8_t rx_fifo_threshold;
00696   uint8_t tx_fifo_threshold;
00697   uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
00698   uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
00699
00700   if (huart->FifoMode == UART_FIFOMODE_DISABLE)
00701   {
00702     huart->NbTxDataToProcess = 1U;
00703     huart->NbRxDataToProcess = 1U;
00704   }
00705   else
00706   {
00707     rx_fifo_depth = RX_FIFO_DEPTH;
00708     tx_fifo_depth = TX_FIFO_DEPTH;
00709     rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
00710     tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
00711     huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold];
00712     huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold];
00713   }
00714 }
00715 /**
00716   * @}
00717   */
00718
00719 #endif /* HAL_UART_MODULE_ENABLED */
00720
00721 /**
00722   * @}
00723   */
00724
00725 /**
00726   * @}
00727   */
00728
00729 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_uart_ex.h Source File

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stm32wbxx_hal_uart_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_uart_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of UART HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_UART_EX_H
00022 #define STM32WBxx_HAL_UART_EX_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 /** @addtogroup STM32WBxx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup UARTEx
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup UARTEx_Exported_Types UARTEx Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief  UART wake up from stop mode parameters
00046   */
00047 typedef struct
00048 {
00049   uint32_t WakeUpEvent;        /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF).
00050                                     This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
00051                                     If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
00052                                     be filled up. */
00053
00054   uint16_t AddressLength;      /*!< Specifies whether the address is 4 or 7-bit long.
00055                                     This parameter can be a value of @ref UARTEx_WakeUp_Address_Length.  */
00056
00057   uint8_t Address;             /*!< UART/USART node address (7-bit long max). */
00058 } UART_WakeUpTypeDef;
00059
00060 /**
00061   * @}
00062   */
00063
00064 /* Exported constants --------------------------------------------------------*/
00065 /** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
00066   * @{
00067   */
00068
00069 /** @defgroup UARTEx_Word_Length UARTEx Word Length
00070   * @{
00071   */
00072 #define UART_WORDLENGTH_7B          USART_CR1_M1   /*!< 7-bit long UART frame */
00073 #define UART_WORDLENGTH_8B          0x00000000U    /*!< 8-bit long UART frame */
00074 #define UART_WORDLENGTH_9B          USART_CR1_M0   /*!< 9-bit long UART frame */
00075 /**
00076   * @}
00077   */
00078
00079 /** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length
00080   * @{
00081   */
00082 #define UART_ADDRESS_DETECT_4B      0x00000000U      /*!< 4-bit long wake-up address */
00083 #define UART_ADDRESS_DETECT_7B      USART_CR2_ADDM7  /*!< 7-bit long wake-up address */
00084 /**
00085   * @}
00086   */
00087
00088 /** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode
00089   * @brief    UART FIFO mode
00090   * @{
00091   */
00092 #define UART_FIFOMODE_DISABLE       0x00000000U       /*!< FIFO mode disable */
00093 #define UART_FIFOMODE_ENABLE        USART_CR1_FIFOEN  /*!< FIFO mode enable  */
00094 /**
00095   * @}
00096   */
00097
00098 /** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level
00099   * @brief    UART TXFIFO threshold level
00100   * @{
00101   */
00102 #define UART_TXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< TXFIFO reaches 1/8 of its depth */
00103 #define UART_TXFIFO_THRESHOLD_1_4   USART_CR3_TXFTCFG_0                       /*!< TXFIFO reaches 1/4 of its depth */
00104 #define UART_TXFIFO_THRESHOLD_1_2   USART_CR3_TXFTCFG_1                       /*!< TXFIFO reaches 1/2 of its depth */
00105 #define UART_TXFIFO_THRESHOLD_3_4   (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */
00106 #define UART_TXFIFO_THRESHOLD_7_8   USART_CR3_TXFTCFG_2                       /*!< TXFIFO reaches 7/8 of its depth */
00107 #define UART_TXFIFO_THRESHOLD_8_8   (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty            */
00108 /**
00109   * @}
00110   */
00111
00112 /** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level
00113   * @brief    UART RXFIFO threshold level
00114   * @{
00115   */
00116 #define UART_RXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< RXFIFO FIFO reaches 1/8 of its depth */
00117 #define UART_RXFIFO_THRESHOLD_1_4   USART_CR3_RXFTCFG_0                       /*!< RXFIFO FIFO reaches 1/4 of its depth */
00118 #define UART_RXFIFO_THRESHOLD_1_2   USART_CR3_RXFTCFG_1                       /*!< RXFIFO FIFO reaches 1/2 of its depth */
00119 #define UART_RXFIFO_THRESHOLD_3_4   (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */
00120 #define UART_RXFIFO_THRESHOLD_7_8   USART_CR3_RXFTCFG_2                       /*!< RXFIFO FIFO reaches 7/8 of its depth */
00121 #define UART_RXFIFO_THRESHOLD_8_8   (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full             */
00122 /**
00123   * @}
00124   */
00125
00126 /**
00127   * @}
00128   */
00129
00130 /* Exported macros -----------------------------------------------------------*/
00131 /* Exported functions --------------------------------------------------------*/
00132 /** @addtogroup UARTEx_Exported_Functions
00133   * @{
00134   */
00135
00136 /** @addtogroup UARTEx_Exported_Functions_Group1
00137   * @{
00138   */
00139
00140 /* Initialization and de-initialization functions  ****************************/
00141 HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
00142                                    uint32_t DeassertionTime);
00143
00144 /**
00145   * @}
00146   */
00147
00148 /** @addtogroup UARTEx_Exported_Functions_Group2
00149   * @{
00150   */
00151
00152 void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
00153
00154 void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart);
00155 void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart);
00156
00157 /**
00158   * @}
00159   */
00160
00161 /** @addtogroup UARTEx_Exported_Functions_Group3
00162   * @{
00163   */
00164
00165 /* Peripheral Control functions  **********************************************/
00166 HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
00167 HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
00168 HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
00169
00170 HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
00171
00172 HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart);
00173 HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart);
00174 HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
00175 HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
00176
00177 /**
00178   * @}
00179   */
00180
00181 /**
00182   * @}
00183   */
00184
00185 /* Private macros ------------------------------------------------------------*/
00186 /** @defgroup UARTEx_Private_Macros UARTEx Private Macros
00187   * @{
00188   */
00189
00190 /** @brief  Report the UART clock source.
00191   * @param  __HANDLE__ specifies the UART Handle.
00192   * @param  __CLOCKSOURCE__ output variable.
00193   * @retval UART clocking source, written in __CLOCKSOURCE__.
00194   */
00195 #if defined (LPUART1)
00196 #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00197   do {                                                        \
00198     if((__HANDLE__)->Instance == USART1)                      \
00199     {                                                         \
00200       switch(__HAL_RCC_GET_USART1_SOURCE())                   \
00201       {                                                       \
00202         case RCC_USART1CLKSOURCE_PCLK2:                       \
00203           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \
00204           break;                                              \
00205         case RCC_USART1CLKSOURCE_HSI:                         \
00206           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00207           break;                                              \
00208         case RCC_USART1CLKSOURCE_SYSCLK:                      \
00209           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00210           break;                                              \
00211         case RCC_USART1CLKSOURCE_LSE:                         \
00212           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00213           break;                                              \
00214         default:                                              \
00215           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00216           break;                                              \
00217       }                                                       \
00218     }                                                         \
00219     else if((__HANDLE__)->Instance == LPUART1)                \
00220     {                                                         \
00221       switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \
00222       {                                                       \
00223         case RCC_LPUART1CLKSOURCE_PCLK1:                      \
00224           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
00225           break;                                              \
00226         case RCC_LPUART1CLKSOURCE_HSI:                        \
00227           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00228           break;                                              \
00229         case RCC_LPUART1CLKSOURCE_SYSCLK:                     \
00230           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00231           break;                                              \
00232         case RCC_LPUART1CLKSOURCE_LSE:                        \
00233           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00234           break;                                              \
00235         default:                                              \
00236           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00237           break;                                              \
00238       }                                                       \
00239     }                                                         \
00240     else                                                      \
00241     {                                                         \
00242       (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
00243     }                                                         \
00244   } while(0U)
00245 #else
00246 #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00247   do {                                                        \
00248     if((__HANDLE__)->Instance == USART1)                      \
00249     {                                                         \
00250       switch(__HAL_RCC_GET_USART1_SOURCE())                   \
00251       {                                                       \
00252         case RCC_USART1CLKSOURCE_PCLK2:                       \
00253           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \
00254           break;                                              \
00255         case RCC_USART1CLKSOURCE_HSI:                         \
00256           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
00257           break;                                              \
00258         case RCC_USART1CLKSOURCE_SYSCLK:                      \
00259           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
00260           break;                                              \
00261         case RCC_USART1CLKSOURCE_LSE:                         \
00262           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
00263           break;                                              \
00264         default:                                              \
00265           (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
00266           break;                                              \
00267       }                                                       \
00268     }                                                         \
00269     else                                                      \
00270     {                                                         \
00271       (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
00272     }                                                         \
00273   } while(0U)
00274 #endif /* LPUART1 */
00275
00276 /** @brief  Report the UART mask to apply to retrieve the received data
00277   *         according to the word length and to the parity bits activation.
00278   * @note   If PCE = 1, the parity bit is not included in the data extracted
00279   *         by the reception API().
00280   *         This masking operation is not carried out in the case of
00281   *         DMA transfers.
00282   * @param  __HANDLE__ specifies the UART Handle.
00283   * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
00284   */
00285 #define UART_MASK_COMPUTATION(__HANDLE__)                             \
00286   do {                                                                \
00287     if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B)          \
00288     {                                                                 \
00289       if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \
00290       {                                                               \
00291         (__HANDLE__)->Mask = 0x01FFU ;                                \
00292       }                                                               \
00293       else                                                            \
00294       {                                                               \
00295         (__HANDLE__)->Mask = 0x00FFU ;                                \
00296       }                                                               \
00297     }                                                                 \
00298     else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B)     \
00299     {                                                                 \
00300       if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \
00301       {                                                               \
00302         (__HANDLE__)->Mask = 0x00FFU ;                                \
00303       }                                                               \
00304       else                                                            \
00305       {                                                               \
00306         (__HANDLE__)->Mask = 0x007FU ;                                \
00307       }                                                               \
00308     }                                                                 \
00309     else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B)     \
00310     {                                                                 \
00311       if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \
00312       {                                                               \
00313         (__HANDLE__)->Mask = 0x007FU ;                                \
00314       }                                                               \
00315       else                                                            \
00316       {                                                               \
00317         (__HANDLE__)->Mask = 0x003FU ;                                \
00318       }                                                               \
00319     }                                                                 \
00320     else                                                              \
00321     {                                                                 \
00322       (__HANDLE__)->Mask = 0x0000U;                                   \
00323     }                                                                 \
00324   } while(0U)
00325
00326 /**
00327   * @brief Ensure that UART frame length is valid.
00328   * @param __LENGTH__ UART frame length.
00329   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
00330   */
00331 #define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
00332                                          ((__LENGTH__) == UART_WORDLENGTH_8B) || \
00333                                          ((__LENGTH__) == UART_WORDLENGTH_9B))
00334
00335 /**
00336   * @brief Ensure that UART wake-up address length is valid.
00337   * @param __ADDRESS__ UART wake-up address length.
00338   * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
00339   */
00340 #define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
00341                                                    ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
00342
00343 /**
00344   * @brief Ensure that UART TXFIFO threshold level is valid.
00345   * @param __THRESHOLD__ UART TXFIFO threshold level.
00346   * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
00347   */
00348 #define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \
00349                                                  ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \
00350                                                  ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \
00351                                                  ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \
00352                                                  ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \
00353                                                  ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8))
00354
00355 /**
00356   * @brief Ensure that UART RXFIFO threshold level is valid.
00357   * @param __THRESHOLD__ UART RXFIFO threshold level.
00358   * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
00359   */
00360 #define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \
00361                                                  ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \
00362                                                  ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \
00363                                                  ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \
00364                                                  ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \
00365                                                  ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8))
00366
00367 /**
00368   * @}
00369   */
00370
00371 /* Private functions ---------------------------------------------------------*/
00372
00373 /**
00374   * @}
00375   */
00376
00377 /**
00378   * @}
00379   */
00380
00381 #ifdef __cplusplus
00382 }
00383 #endif
00384
00385 #endif /* STM32WBxx_HAL_UART_EX_H */
00386
00387 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_usart.c Source File

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stm32wbxx_hal_usart.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_usart.c
00004   * @author  MCD Application Team
00005   * @brief   USART HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter
00008   *          Peripheral (USART).
00009   *           + Initialization and de-initialization functions
00010   *           + IO operation functions
00011   *           + Peripheral Control functions
00012   *           + Peripheral State and Error functions
00013   *
00014   @verbatim
00015  ===============================================================================
00016                         ##### How to use this driver #####
00017  ===============================================================================
00018     [..]
00019       The USART HAL driver can be used as follows:
00020
00021       (#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart).
00022       (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API:
00023           (++) Enable the USARTx interface clock.
00024           (++) USART pins configuration:
00025             (+++) Enable the clock for the USART GPIOs.
00026             (+++) Configure these USART pins as alternate function pull-up.
00027           (++) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
00028                 HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
00029             (+++) Configure the USARTx interrupt priority.
00030             (+++) Enable the NVIC USART IRQ handle.
00031             (++) USART interrupts handling:
00032               -@@-   The specific USART interrupts (Transmission complete interrupt,
00033                   RXNE interrupt and Error Interrupts) will be managed using the macros
00034                   __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
00035           (++) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
00036                HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):
00037             (+++) Declare a DMA handle structure for the Tx/Rx channel.
00038             (+++) Enable the DMAx interface clock.
00039             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00040             (+++) Configure the DMA Tx/Rx channel.
00041             (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
00042             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
00043
00044       (#) Program the Baud Rate, Word Length, Stop Bit, Parity, and Mode
00045           (Receiver/Transmitter) in the husart handle Init structure.
00046
00047       (#) Initialize the USART registers by calling the HAL_USART_Init() API:
00048           (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00049                by calling the customized HAL_USART_MspInit(&husart) API.
00050
00051     [..]
00052      (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's
00053         HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and
00054         HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef.
00055
00056     ##### Callback registration #####
00057     ==================================
00058
00059     [..]
00060     The compilation define USE_HAL_USART_REGISTER_CALLBACKS when set to 1
00061     allows the user to configure dynamically the driver callbacks.
00062
00063     [..]
00064     Use Function @ref HAL_USART_RegisterCallback() to register a user callback.
00065     Function @ref HAL_USART_RegisterCallback() allows to register following callbacks:
00066     (+) TxHalfCpltCallback        : Tx Half Complete Callback.
00067     (+) TxCpltCallback            : Tx Complete Callback.
00068     (+) RxHalfCpltCallback        : Rx Half Complete Callback.
00069     (+) RxCpltCallback            : Rx Complete Callback.
00070     (+) TxRxCpltCallback          : Tx Rx Complete Callback.
00071     (+) ErrorCallback             : Error Callback.
00072     (+) AbortCpltCallback         : Abort Complete Callback.
00073     (+) RxFifoFullCallback        : Rx Fifo Full Callback.
00074     (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
00075     (+) MspInitCallback           : USART MspInit.
00076     (+) MspDeInitCallback         : USART MspDeInit.
00077     This function takes as parameters the HAL peripheral handle, the Callback ID
00078     and a pointer to the user callback function.
00079
00080     [..]
00081     Use function @ref HAL_USART_UnRegisterCallback() to reset a callback to the default
00082     weak (surcharged) function.
00083     @ref HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00084     and the Callback ID.
00085     This function allows to reset following callbacks:
00086     (+) TxHalfCpltCallback        : Tx Half Complete Callback.
00087     (+) TxCpltCallback            : Tx Complete Callback.
00088     (+) RxHalfCpltCallback        : Rx Half Complete Callback.
00089     (+) RxCpltCallback            : Rx Complete Callback.
00090     (+) TxRxCpltCallback          : Tx Rx Complete Callback.
00091     (+) ErrorCallback             : Error Callback.
00092     (+) AbortCpltCallback         : Abort Complete Callback.
00093     (+) RxFifoFullCallback        : Rx Fifo Full Callback.
00094     (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
00095     (+) MspInitCallback           : USART MspInit.
00096     (+) MspDeInitCallback         : USART MspDeInit.
00097
00098     [..]
00099     By default, after the @ref HAL_USART_Init() and when the state is HAL_USART_STATE_RESET
00100     all callbacks are set to the corresponding weak (surcharged) functions:
00101     examples @ref HAL_USART_TxCpltCallback(), @ref HAL_USART_RxHalfCpltCallback().
00102     Exception done for MspInit and MspDeInit functions that are respectively
00103     reset to the legacy weak (surcharged) functions in the @ref HAL_USART_Init()
00104     and @ref HAL_USART_DeInit() only when these callbacks are null (not registered beforehand).
00105     If not, MspInit or MspDeInit are not null, the @ref HAL_USART_Init() and @ref HAL_USART_DeInit()
00106     keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
00107
00108     [..]
00109     Callbacks can be registered/unregistered in HAL_USART_STATE_READY state only.
00110     Exception done MspInit/MspDeInit that can be registered/unregistered
00111     in HAL_USART_STATE_READY or HAL_USART_STATE_RESET state, thus registered (user)
00112     MspInit/DeInit callbacks can be used during the Init/DeInit.
00113     In that case first register the MspInit/MspDeInit user callbacks
00114     using @ref HAL_USART_RegisterCallback() before calling @ref HAL_USART_DeInit()
00115     or @ref HAL_USART_Init() function.
00116
00117     [..]
00118     When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or
00119     not defined, the callback registration feature is not available
00120     and weak (surcharged) callbacks are used.
00121
00122
00123   @endverbatim
00124   ******************************************************************************
00125   * @attention
00126   *
00127   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00128   * All rights reserved.</center></h2>
00129   *
00130   * This software component is licensed by ST under BSD 3-Clause license,
00131   * the "License"; You may not use this file except in compliance with the
00132   * License. You may obtain a copy of the License at:
00133   *                        opensource.org/licenses/BSD-3-Clause
00134   *
00135   ******************************************************************************
00136   */
00137
00138 /* Includes ------------------------------------------------------------------*/
00139 #include "stm32wbxx_hal.h"
00140
00141 /** @addtogroup STM32WBxx_HAL_Driver
00142   * @{
00143   */
00144
00145 /** @defgroup USART USART
00146   * @brief HAL USART Synchronous module driver
00147   * @{
00148   */
00149
00150 #ifdef HAL_USART_MODULE_ENABLED
00151
00152 /* Private typedef -----------------------------------------------------------*/
00153 /* Private define ------------------------------------------------------------*/
00154 /** @defgroup USART_Private_Constants USART Private Constants
00155   * @{
00156   */
00157 #define USART_DUMMY_DATA          ((uint16_t) 0xFFFF)           /*!< USART transmitted dummy data                     */
00158 #define USART_TEACK_REACK_TIMEOUT             1000U             /*!< USART TX or RX enable acknowledge time-out value */
00159 #define USART_CR1_FIELDS          ((uint32_t)(USART_CR1_M |  USART_CR1_PCE | USART_CR1_PS    | \
00160                                               USART_CR1_TE | USART_CR1_RE  | USART_CR1_OVER8 | \
00161                                               USART_CR1_FIFOEN ))                                  /*!< USART CR1 fields of parameters set by USART_SetConfig API */
00162
00163 #define USART_CR2_FIELDS          ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | \
00164                                               USART_CR2_LBCL | USART_CR2_STOP | USART_CR2_SLVEN | \
00165                                               USART_CR2_DIS_NSS))                                  /*!< USART CR2 fields of parameters set by USART_SetConfig API */
00166
00167 #define USART_CR3_FIELDS          ((uint32_t)(USART_CR3_TXFTCFG | USART_CR3_RXFTCFG ))             /*!< USART or USART CR3 fields of parameters set by USART_SetConfig API */
00168
00169 #define USART_BRR_MIN    0x10U        /* USART BRR minimum authorized value */
00170 #define USART_BRR_MAX    0xFFFFU      /* USART BRR maximum authorized value */
00171 /**
00172   * @}
00173   */
00174
00175 /* Private macros ------------------------------------------------------------*/
00176 /* Private variables ---------------------------------------------------------*/
00177 /* Private function prototypes -----------------------------------------------*/
00178 /** @addtogroup USART_Private_Functions
00179   * @{
00180   */
00181 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
00182 void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart);
00183 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
00184 static void USART_EndTransfer(USART_HandleTypeDef *husart);
00185 static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00186 static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00187 static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00188 static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00189 static void USART_DMAError(DMA_HandleTypeDef *hdma);
00190 static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
00191 static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
00192 static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
00193 static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
00194 static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart);
00195 static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart);
00196 static void USART_TxISR_8BIT(USART_HandleTypeDef *husart);
00197 static void USART_TxISR_16BIT(USART_HandleTypeDef *husart);
00198 static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart);
00199 static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart);
00200 static void USART_EndTransmit_IT(USART_HandleTypeDef *husart);
00201 static void USART_RxISR_8BIT(USART_HandleTypeDef *husart);
00202 static void USART_RxISR_16BIT(USART_HandleTypeDef *husart);
00203 static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart);
00204 static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart);
00205
00206
00207 /**
00208   * @}
00209   */
00210
00211 /* Exported functions --------------------------------------------------------*/
00212
00213 /** @defgroup USART_Exported_Functions USART Exported Functions
00214   * @{
00215   */
00216
00217 /** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
00218   * @brief    Initialization and Configuration functions
00219   *
00220 @verbatim
00221  ===============================================================================
00222             ##### Initialization and Configuration functions #####
00223  ===============================================================================
00224     [..]
00225     This subsection provides a set of functions allowing to initialize the USART
00226     in asynchronous and in synchronous modes.
00227       (+) For the asynchronous mode only these parameters can be configured:
00228         (++) Baud Rate
00229         (++) Word Length
00230         (++) Stop Bit
00231         (++) Parity: If the parity is enabled, then the MSB bit of the data written
00232              in the data register is transmitted but is changed by the parity bit.
00233         (++) USART polarity
00234         (++) USART phase
00235         (++) USART LastBit
00236         (++) Receiver/transmitter modes
00237
00238     [..]
00239     The HAL_USART_Init() function follows the USART  synchronous configuration
00240     procedure (details for the procedure are available in reference manual).
00241
00242 @endverbatim
00243
00244   Depending on the frame length defined by the M1 and M0 bits (7-bit,
00245   8-bit or 9-bit), the possible USART formats are listed in the
00246   following table.
00247
00248     Table 1. USART frame format.
00249     +-----------------------------------------------------------------------+
00250     |  M1 bit |  M0 bit |  PCE bit  |            USART frame                |
00251     |---------|---------|-----------|---------------------------------------|
00252     |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
00253     |---------|---------|-----------|---------------------------------------|
00254     |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
00255     |---------|---------|-----------|---------------------------------------|
00256     |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
00257     |---------|---------|-----------|---------------------------------------|
00258     |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
00259     |---------|---------|-----------|---------------------------------------|
00260     |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
00261     |---------|---------|-----------|---------------------------------------|
00262     |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
00263     +-----------------------------------------------------------------------+
00264
00265   * @{
00266   */
00267
00268 /**
00269   * @brief  Initialize the USART mode according to the specified
00270   *         parameters in the USART_InitTypeDef and initialize the associated handle.
00271   * @param  husart USART handle.
00272   * @retval HAL status
00273   */
00274 HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
00275 {
00276   /* Check the USART handle allocation */
00277   if (husart == NULL)
00278   {
00279     return HAL_ERROR;
00280   }
00281
00282   /* Check the parameters */
00283   assert_param(IS_USART_INSTANCE(husart->Instance));
00284
00285   if (husart->State == HAL_USART_STATE_RESET)
00286   {
00287     /* Allocate lock resource and initialize it */
00288     husart->Lock = HAL_UNLOCKED;
00289
00290 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
00291     USART_InitCallbacksToDefault(husart);
00292
00293     if (husart->MspInitCallback == NULL)
00294     {
00295       husart->MspInitCallback = HAL_USART_MspInit;
00296     }
00297
00298     /* Init the low level hardware */
00299     husart->MspInitCallback(husart);
00300 #else
00301     /* Init the low level hardware : GPIO, CLOCK */
00302     HAL_USART_MspInit(husart);
00303 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
00304   }
00305
00306   husart->State = HAL_USART_STATE_BUSY;
00307
00308   /* Disable the Peripheral */
00309   __HAL_USART_DISABLE(husart);
00310
00311   /* Set the Usart Communication parameters */
00312   if (USART_SetConfig(husart) == HAL_ERROR)
00313   {
00314     return HAL_ERROR;
00315   }
00316
00317   /* In Synchronous mode, the following bits must be kept cleared:
00318   - LINEN bit in the USART_CR2 register
00319   - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/
00320   husart->Instance->CR2 &= ~USART_CR2_LINEN;
00321   husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
00322
00323   /* Enable the Peripheral */
00324   __HAL_USART_ENABLE(husart);
00325
00326   /* TEACK and/or REACK to check before moving husart->State to Ready */
00327   return (USART_CheckIdleState(husart));
00328 }
00329
00330 /**
00331   * @brief DeInitialize the USART peripheral.
00332   * @param  husart USART handle.
00333   * @retval HAL status
00334   */
00335 HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
00336 {
00337   /* Check the USART handle allocation */
00338   if (husart == NULL)
00339   {
00340     return HAL_ERROR;
00341   }
00342
00343   /* Check the parameters */
00344   assert_param(IS_USART_INSTANCE(husart->Instance));
00345
00346   husart->State = HAL_USART_STATE_BUSY;
00347
00348   husart->Instance->CR1 = 0x0U;
00349   husart->Instance->CR2 = 0x0U;
00350   husart->Instance->CR3 = 0x0U;
00351
00352 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
00353   if (husart->MspDeInitCallback == NULL)
00354   {
00355     husart->MspDeInitCallback = HAL_USART_MspDeInit;
00356   }
00357   /* DeInit the low level hardware */
00358   husart->MspDeInitCallback(husart);
00359 #else
00360   /* DeInit the low level hardware */
00361   HAL_USART_MspDeInit(husart);
00362 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
00363
00364   husart->ErrorCode = HAL_USART_ERROR_NONE;
00365   husart->State = HAL_USART_STATE_RESET;
00366
00367   /* Process Unlock */
00368   __HAL_UNLOCK(husart);
00369
00370   return HAL_OK;
00371 }
00372
00373 /**
00374   * @brief Initialize the USART MSP.
00375   * @param husart USART handle.
00376   * @retval None
00377   */
00378 __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
00379 {
00380   /* Prevent unused argument(s) compilation warning */
00381   UNUSED(husart);
00382
00383   /* NOTE : This function should not be modified, when the callback is needed,
00384             the HAL_USART_MspInit can be implemented in the user file
00385    */
00386 }
00387
00388 /**
00389   * @brief DeInitialize the USART MSP.
00390   * @param husart USART handle.
00391   * @retval None
00392   */
00393 __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
00394 {
00395   /* Prevent unused argument(s) compilation warning */
00396   UNUSED(husart);
00397
00398   /* NOTE : This function should not be modified, when the callback is needed,
00399             the HAL_USART_MspDeInit can be implemented in the user file
00400    */
00401 }
00402
00403 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
00404 /**
00405   * @brief  Register a User USART Callback
00406   *         To be used instead of the weak predefined callback
00407   * @param  husart usart handle
00408   * @param  CallbackID ID of the callback to be registered
00409   *         This parameter can be one of the following values:
00410   *           @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
00411   *           @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID
00412   *           @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
00413   *           @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID
00414   *           @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID
00415   *           @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID
00416   *           @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
00417   *           @arg @ref HAL_USART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
00418   *           @arg @ref HAL_USART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
00419   *           @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID
00420   *           @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID
00421   * @param  pCallback pointer to the Callback function
00422   * @retval HAL status
00423 +  */
00424 HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback)
00425 {
00426   HAL_StatusTypeDef status = HAL_OK;
00427
00428   if (pCallback == NULL)
00429   {
00430     /* Update the error code */
00431     husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
00432
00433     return HAL_ERROR;
00434   }
00435   /* Process locked */
00436   __HAL_LOCK(husart);
00437
00438   if (husart->State == HAL_USART_STATE_READY)
00439   {
00440     switch (CallbackID)
00441     {
00442       case HAL_USART_TX_HALFCOMPLETE_CB_ID :
00443         husart->TxHalfCpltCallback = pCallback;
00444         break;
00445
00446       case HAL_USART_TX_COMPLETE_CB_ID :
00447         husart->TxCpltCallback = pCallback;
00448         break;
00449
00450       case HAL_USART_RX_HALFCOMPLETE_CB_ID :
00451         husart->RxHalfCpltCallback = pCallback;
00452         break;
00453
00454       case HAL_USART_RX_COMPLETE_CB_ID :
00455         husart->RxCpltCallback = pCallback;
00456         break;
00457
00458       case HAL_USART_TX_RX_COMPLETE_CB_ID :
00459         husart->TxRxCpltCallback = pCallback;
00460         break;
00461
00462       case HAL_USART_ERROR_CB_ID :
00463         husart->ErrorCallback = pCallback;
00464         break;
00465
00466       case HAL_USART_ABORT_COMPLETE_CB_ID :
00467         husart->AbortCpltCallback = pCallback;
00468         break;
00469
00470       case HAL_USART_RX_FIFO_FULL_CB_ID :
00471         husart->RxFifoFullCallback = pCallback;
00472         break;
00473
00474       case HAL_USART_TX_FIFO_EMPTY_CB_ID :
00475         husart->TxFifoEmptyCallback = pCallback;
00476         break;
00477
00478       case HAL_USART_MSPINIT_CB_ID :
00479         husart->MspInitCallback = pCallback;
00480         break;
00481
00482       case HAL_USART_MSPDEINIT_CB_ID :
00483         husart->MspDeInitCallback = pCallback;
00484         break;
00485
00486       default :
00487         /* Update the error code */
00488         husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
00489
00490         /* Return error status */
00491         status =  HAL_ERROR;
00492         break;
00493     }
00494   }
00495   else if (husart->State == HAL_USART_STATE_RESET)
00496   {
00497     switch (CallbackID)
00498     {
00499       case HAL_USART_MSPINIT_CB_ID :
00500         husart->MspInitCallback = pCallback;
00501         break;
00502
00503       case HAL_USART_MSPDEINIT_CB_ID :
00504         husart->MspDeInitCallback = pCallback;
00505         break;
00506
00507       default :
00508         /* Update the error code */
00509         husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
00510
00511         /* Return error status */
00512         status =  HAL_ERROR;
00513         break;
00514     }
00515   }
00516   else
00517   {
00518     /* Update the error code */
00519     husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
00520
00521     /* Return error status */
00522     status =  HAL_ERROR;
00523   }
00524
00525   /* Release Lock */
00526   __HAL_UNLOCK(husart);
00527
00528   return status;
00529 }
00530
00531 /**
00532   * @brief  Unregister an UART Callback
00533   *         UART callaback is redirected to the weak predefined callback
00534   * @param  husart uart handle
00535   * @param  CallbackID ID of the callback to be unregistered
00536   *         This parameter can be one of the following values:
00537   *           @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
00538   *           @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID
00539   *           @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
00540   *           @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID
00541   *           @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID
00542   *           @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID
00543   *           @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
00544   *           @arg @ref HAL_USART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
00545   *           @arg @ref HAL_USART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
00546   *           @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID
00547   *           @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID
00548   * @retval HAL status
00549   */
00550 HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID)
00551 {
00552   HAL_StatusTypeDef status = HAL_OK;
00553
00554   /* Process locked */
00555   __HAL_LOCK(husart);
00556
00557   if (HAL_USART_STATE_READY == husart->State)
00558   {
00559     switch (CallbackID)
00560     {
00561       case HAL_USART_TX_HALFCOMPLETE_CB_ID :
00562         husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback;               /* Legacy weak  TxHalfCpltCallback       */
00563         break;
00564
00565       case HAL_USART_TX_COMPLETE_CB_ID :
00566         husart->TxCpltCallback = HAL_USART_TxCpltCallback;                       /* Legacy weak TxCpltCallback            */
00567         break;
00568
00569       case HAL_USART_RX_HALFCOMPLETE_CB_ID :
00570         husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback;               /* Legacy weak RxHalfCpltCallback        */
00571         break;
00572
00573       case HAL_USART_RX_COMPLETE_CB_ID :
00574         husart->RxCpltCallback = HAL_USART_RxCpltCallback;                       /* Legacy weak RxCpltCallback            */
00575         break;
00576
00577       case HAL_USART_TX_RX_COMPLETE_CB_ID :
00578         husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback;                   /* Legacy weak TxRxCpltCallback            */
00579         break;
00580
00581       case HAL_USART_ERROR_CB_ID :
00582         husart->ErrorCallback = HAL_USART_ErrorCallback;                         /* Legacy weak ErrorCallback             */
00583         break;
00584
00585       case HAL_USART_ABORT_COMPLETE_CB_ID :
00586         husart->AbortCpltCallback = HAL_USART_AbortCpltCallback;                 /* Legacy weak AbortCpltCallback         */
00587         break;
00588
00589       case HAL_USART_RX_FIFO_FULL_CB_ID :
00590         husart->RxFifoFullCallback = HAL_USARTEx_RxFifoFullCallback;             /* Legacy weak RxFifoFullCallback        */
00591         break;
00592
00593       case HAL_USART_TX_FIFO_EMPTY_CB_ID :
00594         husart->TxFifoEmptyCallback = HAL_USARTEx_TxFifoEmptyCallback;           /* Legacy weak TxFifoEmptyCallback       */
00595         break;
00596
00597       case HAL_USART_MSPINIT_CB_ID :
00598         husart->MspInitCallback = HAL_USART_MspInit;                             /* Legacy weak MspInitCallback           */
00599         break;
00600
00601       case HAL_USART_MSPDEINIT_CB_ID :
00602         husart->MspDeInitCallback = HAL_USART_MspDeInit;                         /* Legacy weak MspDeInitCallback         */
00603         break;
00604
00605       default :
00606         /* Update the error code */
00607         husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
00608
00609         /* Return error status */
00610         status =  HAL_ERROR;
00611         break;
00612     }
00613   }
00614   else if (HAL_USART_STATE_RESET == husart->State)
00615   {
00616     switch (CallbackID)
00617     {
00618       case HAL_USART_MSPINIT_CB_ID :
00619         husart->MspInitCallback = HAL_USART_MspInit;
00620         break;
00621
00622       case HAL_USART_MSPDEINIT_CB_ID :
00623         husart->MspDeInitCallback = HAL_USART_MspDeInit;
00624         break;
00625
00626       default :
00627         /* Update the error code */
00628         husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
00629
00630         /* Return error status */
00631         status =  HAL_ERROR;
00632         break;
00633     }
00634   }
00635   else
00636   {
00637     /* Update the error code */
00638     husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
00639
00640     /* Return error status */
00641     status =  HAL_ERROR;
00642   }
00643
00644   /* Release Lock */
00645   __HAL_UNLOCK(husart);
00646
00647   return status;
00648 }
00649 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
00650
00651
00652 /**
00653   * @}
00654   */
00655
00656 /** @defgroup USART_Exported_Functions_Group2 IO operation functions
00657   * @brief   USART Transmit and Receive functions
00658   *
00659 @verbatim
00660  ===============================================================================
00661                       ##### IO operation functions #####
00662  ===============================================================================
00663     [..] This subsection provides a set of functions allowing to manage the USART synchronous
00664     data transfers.
00665
00666     [..] The USART supports master mode only: it cannot receive or send data related to an input
00667          clock (SCLK is always an output).
00668
00669     [..]
00670
00671     (#) There are two modes of transfer:
00672         (++) Blocking mode: The communication is performed in polling mode.
00673              The HAL status of all data processing is returned by the same function
00674              after finishing transfer.
00675         (++) No-Blocking mode: The communication is performed using Interrupts
00676              or DMA, These API's return the HAL status.
00677              The end of the data processing will be indicated through the
00678              dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
00679              using DMA mode.
00680              The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks
00681              will be executed respectively at the end of the transmit or Receive process
00682              The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected
00683
00684     (#) Blocking mode API's are :
00685         (++) HAL_USART_Transmit() in simplex mode
00686         (++) HAL_USART_Receive() in full duplex receive only
00687         (++) HAL_USART_TransmitReceive() in full duplex mode
00688
00689     (#) Non-Blocking mode API's with Interrupt are :
00690         (++) HAL_USART_Transmit_IT() in simplex mode
00691         (++) HAL_USART_Receive_IT() in full duplex receive only
00692         (++) HAL_USART_TransmitReceive_IT() in full duplex mode
00693         (++) HAL_USART_IRQHandler()
00694
00695     (#) No-Blocking mode API's  with DMA are :
00696         (++) HAL_USART_Transmit_DMA() in simplex mode
00697         (++) HAL_USART_Receive_DMA() in full duplex receive only
00698         (++) HAL_USART_TransmitReceive_DMA() in full duplex mode
00699         (++) HAL_USART_DMAPause()
00700         (++) HAL_USART_DMAResume()
00701         (++) HAL_USART_DMAStop()
00702
00703     (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
00704         (++) HAL_USART_TxCpltCallback()
00705         (++) HAL_USART_RxCpltCallback()
00706         (++) HAL_USART_TxHalfCpltCallback()
00707         (++) HAL_USART_RxHalfCpltCallback()
00708         (++) HAL_USART_ErrorCallback()
00709         (++) HAL_USART_TxRxCpltCallback()
00710
00711     (#) Non-Blocking mode transfers could be aborted using Abort API's :
00712         (++) HAL_USART_Abort()
00713         (++) HAL_USART_Abort_IT()
00714
00715     (#) For Abort services based on interrupts (HAL_USART_Abort_IT), a Abort Complete Callbacks is provided:
00716         (++) HAL_USART_AbortCpltCallback()
00717
00718     (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
00719         Errors are handled as follows :
00720         (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
00721              to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
00722              Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
00723              and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side.
00724              If user wants to abort it, Abort services should be called by user.
00725         (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
00726              This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
00727              Error code is set to allow user to identify error type, and HAL_USART_ErrorCallback() user callback is executed.
00728
00729 @endverbatim
00730   * @{
00731   */
00732
00733 /**
00734   * @brief  Simplex send an amount of data in blocking mode.
00735   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
00736   *         the sent data is handled as a set of u16. In this case, Size must indicate the number
00737   *         of u16 provided through pTxData.
00738   * @param  husart USART handle.
00739   * @param  pTxData Pointer to data buffer (u8 or u16 data elements).
00740   * @param  Size Amount of data elements (u8 or u16) to be sent.
00741   * @param  Timeout Timeout duration.
00742   * @retval HAL status
00743   */
00744 HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
00745 {
00746   uint8_t  *ptxdata8bits;
00747   uint16_t *ptxdata16bits;
00748   uint32_t tickstart;
00749
00750
00751   if (husart->State == HAL_USART_STATE_READY)
00752   {
00753     if ((pTxData == NULL) || (Size == 0U))
00754     {
00755       return  HAL_ERROR;
00756     }
00757
00758     /* Process Locked */
00759     __HAL_LOCK(husart);
00760
00761     husart->ErrorCode = HAL_USART_ERROR_NONE;
00762     husart->State = HAL_USART_STATE_BUSY_TX;
00763
00764     /* Init tickstart for timeout managment*/
00765     tickstart = HAL_GetTick();
00766
00767     husart->TxXferSize = Size;
00768     husart->TxXferCount = Size;
00769
00770     /* In case of 9bits/No Parity transfer, pTxData needs to be handled as a uint16_t pointer */
00771     if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
00772     {
00773       ptxdata8bits  = NULL;
00774       ptxdata16bits = (uint16_t *) pTxData;
00775     }
00776     else
00777     {
00778       ptxdata8bits  = pTxData;
00779       ptxdata16bits = NULL;
00780     }
00781
00782     /* Check the remaining data to be sent */
00783     while (husart->TxXferCount > 0U)
00784     {
00785       if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
00786       {
00787         return HAL_TIMEOUT;
00788       }
00789       if (ptxdata8bits == NULL)
00790       {
00791         husart->Instance->TDR = (uint16_t)(*ptxdata16bits & 0x01FFU);
00792         ptxdata16bits++;
00793       }
00794       else
00795       {
00796         husart->Instance->TDR = (uint8_t)(*ptxdata8bits & 0xFFU);
00797         ptxdata8bits++;
00798       }
00799
00800       husart->TxXferCount--;
00801     }
00802
00803     if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
00804     {
00805       return HAL_TIMEOUT;
00806     }
00807
00808     /* Clear Transmission Complete Flag */
00809     __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
00810
00811     /* Clear overrun flag and discard the received data */
00812     __HAL_USART_CLEAR_OREFLAG(husart);
00813     __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
00814     __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
00815
00816     /* At end of Tx process, restore husart->State to Ready */
00817     husart->State = HAL_USART_STATE_READY;
00818
00819     /* Process Unlocked */
00820     __HAL_UNLOCK(husart);
00821
00822     return HAL_OK;
00823   }
00824   else
00825   {
00826     return HAL_BUSY;
00827   }
00828 }
00829
00830 /**
00831   * @brief Receive an amount of data in blocking mode.
00832   * @note   To receive synchronous data, dummy data are simultaneously transmitted.
00833   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
00834   *         the received data is handled as a set of u16. In this case, Size must indicate the number
00835   *         of u16 available through pRxData.
00836   * @param husart USART handle.
00837   * @param pRxData Pointer to data buffer (u8 or u16 data elements).
00838   * @param Size Amount of data elements (u8 or u16) to be received.
00839   * @param Timeout Timeout duration.
00840   * @retval HAL status
00841   */
00842 HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
00843 {
00844   uint8_t  *prxdata8bits;
00845   uint16_t *prxdata16bits;
00846   uint16_t uhMask;
00847   uint32_t tickstart;
00848
00849
00850   if (husart->State == HAL_USART_STATE_READY)
00851   {
00852     if ((pRxData == NULL) || (Size == 0U))
00853     {
00854       return  HAL_ERROR;
00855     }
00856
00857     /* Process Locked */
00858     __HAL_LOCK(husart);
00859
00860     husart->ErrorCode = HAL_USART_ERROR_NONE;
00861     husart->State = HAL_USART_STATE_BUSY_RX;
00862
00863     /* Init tickstart for timeout managment*/
00864     tickstart = HAL_GetTick();
00865
00866     husart->RxXferSize = Size;
00867     husart->RxXferCount = Size;
00868
00869     /* Computation of USART mask to apply to RDR register */
00870     USART_MASK_COMPUTATION(husart);
00871     uhMask = husart->Mask;
00872
00873     /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
00874     if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
00875     {
00876       prxdata8bits  = NULL;
00877       prxdata16bits = (uint16_t *) pRxData;
00878     }
00879     else
00880     {
00881       prxdata8bits  = pRxData;
00882       prxdata16bits = NULL;
00883     }
00884
00885     /* as long as data have to be received */
00886     while (husart->RxXferCount > 0U)
00887     {
00888       if (husart->SlaveMode == USART_SLAVEMODE_DISABLE)
00889       {
00890         /* Wait until TXE flag is set to send dummy byte in order to generate the
00891         * clock for the slave to send data.
00892         * Whatever the frame length (7, 8 or 9-bit long), the same dummy value
00893         * can be written for all the cases. */
00894         if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
00895         {
00896           return HAL_TIMEOUT;
00897         }
00898         husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FF);
00899       }
00900
00901       /* Wait for RXNE Flag */
00902       if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
00903       {
00904         return HAL_TIMEOUT;
00905       }
00906
00907       if (prxdata8bits == NULL)
00908       {
00909         *prxdata16bits = (uint16_t)(husart->Instance->RDR & uhMask);
00910         prxdata16bits++;
00911       }
00912       else
00913       {
00914         *prxdata8bits = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU));
00915         prxdata8bits++;
00916       }
00917
00918       husart->RxXferCount--;
00919
00920     }
00921
00922     /* Clear SPI slave underrun flag and discard transmit data */
00923     if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)
00924     {
00925       __HAL_USART_CLEAR_UDRFLAG(husart);
00926       __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
00927     }
00928
00929     /* At end of Rx process, restore husart->State to Ready */
00930     husart->State = HAL_USART_STATE_READY;
00931
00932     /* Process Unlocked */
00933     __HAL_UNLOCK(husart);
00934
00935     return HAL_OK;
00936   }
00937   else
00938   {
00939     return HAL_BUSY;
00940   }
00941 }
00942
00943 /**
00944   * @brief Full-Duplex Send and Receive an amount of data in blocking mode.
00945   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
00946   *         the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
00947   *         of u16 available through pTxData and through pRxData.
00948   * @param  husart USART handle.
00949   * @param  pTxData pointer to TX data buffer (u8 or u16 data elements).
00950   * @param  pRxData pointer to RX data buffer (u8 or u16 data elements).
00951   * @param  Size amount of data elements (u8 or u16) to be sent (same amount to be received).
00952   * @param  Timeout Timeout duration.
00953   * @retval HAL status
00954   */
00955 HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
00956 {
00957   uint8_t  *prxdata8bits;
00958   uint16_t *prxdata16bits;
00959   uint8_t  *ptxdata8bits;
00960   uint16_t *ptxdata16bits;
00961   uint16_t uhMask;
00962   uint16_t rxdatacount;
00963   uint32_t tickstart;
00964
00965
00966   if (husart->State == HAL_USART_STATE_READY)
00967   {
00968     if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
00969     {
00970       return  HAL_ERROR;
00971     }
00972
00973     /* Process Locked */
00974     __HAL_LOCK(husart);
00975
00976     husart->ErrorCode = HAL_USART_ERROR_NONE;
00977     husart->State = HAL_USART_STATE_BUSY_RX;
00978
00979     /* Init tickstart for timeout managment*/
00980     tickstart = HAL_GetTick();
00981
00982     husart->RxXferSize = Size;
00983     husart->TxXferSize = Size;
00984     husart->TxXferCount = Size;
00985     husart->RxXferCount = Size;
00986
00987     /* Computation of USART mask to apply to RDR register */
00988     USART_MASK_COMPUTATION(husart);
00989     uhMask = husart->Mask;
00990
00991     /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
00992     if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
00993     {
00994       prxdata8bits  = NULL;
00995       ptxdata8bits  = NULL;
00996       ptxdata16bits = (uint16_t *) pTxData;
00997       prxdata16bits = (uint16_t *) pRxData;
00998     }
00999     else
01000     {
01001       prxdata8bits  = pRxData;
01002       ptxdata8bits  = pTxData;
01003       ptxdata16bits = NULL;
01004       prxdata16bits = NULL;
01005     }
01006
01007     if ((husart->TxXferCount == 0x01U) || (husart->SlaveMode == USART_SLAVEMODE_ENABLE))
01008     {
01009       /* Wait until TXE flag is set to send data */
01010       if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
01011       {
01012         return HAL_TIMEOUT;
01013       }
01014       if (ptxdata8bits == NULL)
01015       {
01016         husart->Instance->TDR = (uint16_t)(*ptxdata16bits & uhMask);
01017         ptxdata16bits++;
01018       }
01019       else
01020       {
01021         husart->Instance->TDR = (uint8_t)(*ptxdata8bits & (uint8_t)(uhMask & 0xFFU));
01022         ptxdata8bits++;
01023       }
01024
01025       husart->TxXferCount--;
01026     }
01027
01028     /* Check the remain data to be sent */
01029     /* rxdatacount is a temporary variable for MISRAC2012-Rule-13.5 */
01030     rxdatacount = husart->RxXferCount;
01031     while ((husart->TxXferCount > 0U) || (rxdatacount > 0U))
01032     {
01033       if (husart->TxXferCount > 0U)
01034       {
01035         /* Wait until TXE flag is set to send data */
01036         if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
01037         {
01038           return HAL_TIMEOUT;
01039         }
01040         if (ptxdata8bits == NULL)
01041         {
01042           husart->Instance->TDR = (uint16_t)(*ptxdata16bits & uhMask);
01043           ptxdata16bits++;
01044         }
01045         else
01046         {
01047           husart->Instance->TDR = (uint8_t)(*ptxdata8bits & (uint8_t)(uhMask & 0xFFU));
01048           ptxdata8bits++;
01049         }
01050
01051         husart->TxXferCount--;
01052       }
01053
01054       if (husart->RxXferCount > 0U)
01055       {
01056         /* Wait for RXNE Flag */
01057         if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
01058         {
01059           return HAL_TIMEOUT;
01060         }
01061
01062         if (prxdata8bits == NULL)
01063         {
01064           *prxdata16bits = (uint16_t)(husart->Instance->RDR & uhMask);
01065           prxdata16bits++;
01066         }
01067         else
01068         {
01069           *prxdata8bits = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU));
01070           prxdata8bits++;
01071         }
01072
01073         husart->RxXferCount--;
01074       }
01075       rxdatacount = husart->RxXferCount;
01076     }
01077
01078     /* At end of TxRx process, restore husart->State to Ready */
01079     husart->State = HAL_USART_STATE_READY;
01080
01081     /* Process Unlocked */
01082     __HAL_UNLOCK(husart);
01083
01084     return HAL_OK;
01085   }
01086   else
01087   {
01088     return HAL_BUSY;
01089   }
01090 }
01091
01092 /**
01093   * @brief  Send an amount of data in interrupt mode.
01094   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01095   *         the sent data is handled as a set of u16. In this case, Size must indicate the number
01096   *         of u16 provided through pTxData.
01097   * @param  husart USART handle.
01098   * @param  pTxData pointer to data buffer (u8 or u16 data elements).
01099   * @param  Size amount of data elements (u8 or u16) to be sent.
01100   * @retval HAL status
01101   */
01102 HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
01103 {
01104
01105   if (husart->State == HAL_USART_STATE_READY)
01106   {
01107     if ((pTxData == NULL) || (Size == 0U))
01108     {
01109       return HAL_ERROR;
01110     }
01111
01112     /* Process Locked */
01113     __HAL_LOCK(husart);
01114
01115     husart->pTxBuffPtr  = pTxData;
01116     husart->TxXferSize  = Size;
01117     husart->TxXferCount = Size;
01118     husart->TxISR       = NULL;
01119
01120     husart->ErrorCode = HAL_USART_ERROR_NONE;
01121     husart->State     = HAL_USART_STATE_BUSY_TX;
01122
01123     /* The USART Error Interrupts: (Frame error, noise error, overrun error)
01124     are not managed by the USART Transmit Process to avoid the overrun interrupt
01125     when the usart mode is configured for transmit and receive "USART_MODE_TX_RX"
01126     to benefit for the frame error and noise interrupts the usart mode should be
01127     configured only for transmit "USART_MODE_TX" */
01128
01129     /* Configure Tx interrupt processing */
01130     if (husart->FifoMode == USART_FIFOMODE_ENABLE)
01131     {
01132       /* Set the Tx ISR function pointer according to the data word length */
01133       if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01134       {
01135         husart->TxISR = USART_TxISR_16BIT_FIFOEN;
01136       }
01137       else
01138       {
01139         husart->TxISR = USART_TxISR_8BIT_FIFOEN;
01140       }
01141
01142       /* Process Unlocked */
01143       __HAL_UNLOCK(husart);
01144
01145       /* Enable the TX FIFO threshold interrupt */
01146       __HAL_USART_ENABLE_IT(husart, USART_IT_TXFT);
01147     }
01148     else
01149     {
01150       /* Set the Tx ISR function pointer according to the data word length */
01151       if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01152       {
01153         husart->TxISR = USART_TxISR_16BIT;
01154       }
01155       else
01156       {
01157         husart->TxISR = USART_TxISR_8BIT;
01158       }
01159
01160       /* Process Unlocked */
01161       __HAL_UNLOCK(husart);
01162
01163       /* Enable the USART Transmit Data Register Empty Interrupt */
01164       __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
01165     }
01166
01167     return HAL_OK;
01168   }
01169   else
01170   {
01171     return HAL_BUSY;
01172   }
01173 }
01174
01175 /**
01176   * @brief Receive an amount of data in interrupt mode.
01177   * @note   To receive synchronous data, dummy data are simultaneously transmitted.
01178   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01179   *         the received data is handled as a set of u16. In this case, Size must indicate the number
01180   *         of u16 available through pRxData.
01181   * @param  husart USART handle.
01182   * @param  pRxData pointer to data buffer (u8 or u16 data elements).
01183   * @param  Size amount of data elements (u8 or u16) to be received.
01184   * @retval HAL status
01185   */
01186 HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
01187 {
01188   uint16_t nb_dummy_data;
01189
01190
01191   if (husart->State == HAL_USART_STATE_READY)
01192   {
01193     if ((pRxData == NULL) || (Size == 0U))
01194     {
01195       return HAL_ERROR;
01196     }
01197
01198     /* Process Locked */
01199     __HAL_LOCK(husart);
01200
01201     husart->pRxBuffPtr  = pRxData;
01202     husart->RxXferSize  = Size;
01203     husart->RxXferCount = Size;
01204     husart->RxISR       = NULL;
01205
01206     USART_MASK_COMPUTATION(husart);
01207
01208     husart->ErrorCode = HAL_USART_ERROR_NONE;
01209     husart->State = HAL_USART_STATE_BUSY_RX;
01210
01211     /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
01212     SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
01213
01214     /* Configure Rx interrupt processing */
01215     if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess))
01216     {
01217       /* Set the Rx ISR function pointer according to the data word length */
01218       if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01219       {
01220         husart->RxISR = USART_RxISR_16BIT_FIFOEN;
01221       }
01222       else
01223       {
01224         husart->RxISR = USART_RxISR_8BIT_FIFOEN;
01225       }
01226
01227       /* Process Unlocked */
01228       __HAL_UNLOCK(husart);
01229
01230       /* Enable the USART Parity Error interrupt and RX FIFO Threshold interrupt */
01231       SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
01232       SET_BIT(husart->Instance->CR3, USART_CR3_RXFTIE);
01233     }
01234     else
01235     {
01236       /* Set the Rx ISR function pointer according to the data word length */
01237       if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01238       {
01239         husart->RxISR = USART_RxISR_16BIT;
01240       }
01241       else
01242       {
01243         husart->RxISR = USART_RxISR_8BIT;
01244       }
01245
01246       /* Process Unlocked */
01247       __HAL_UNLOCK(husart);
01248
01249       /* Enable the USART Parity Error and Data Register not empty Interrupts */
01250       SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
01251     }
01252
01253     if (husart->SlaveMode == USART_SLAVEMODE_DISABLE)
01254     {
01255       /* Send dummy data in order to generate the clock for the Slave to send the next data.
01256          When FIFO mode is disabled only one data must be transferred.
01257          When FIFO mode is enabled data must be transmitted until the RX FIFO reaches its threshold.
01258       */
01259       if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess))
01260       {
01261         for (nb_dummy_data = husart->NbRxDataToProcess ; nb_dummy_data > 0U ; nb_dummy_data--)
01262         {
01263           husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
01264         }
01265       }
01266       else
01267       {
01268         husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
01269       }
01270     }
01271
01272     return HAL_OK;
01273   }
01274   else
01275   {
01276     return HAL_BUSY;
01277   }
01278 }
01279
01280 /**
01281   * @brief Full-Duplex Send and Receive an amount of data in interrupt mode.
01282   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01283   *         the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
01284   *         of u16 available through pTxData and through pRxData.
01285   * @param  husart USART handle.
01286   * @param  pTxData pointer to TX data buffer (u8 or u16 data elements).
01287   * @param  pRxData pointer to RX data buffer (u8 or u16 data elements).
01288   * @param  Size amount of data elements (u8 or u16) to be sent (same amount to be received).
01289   * @retval HAL status
01290   */
01291 HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,  uint16_t Size)
01292 {
01293
01294   if (husart->State == HAL_USART_STATE_READY)
01295   {
01296     if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
01297     {
01298       return HAL_ERROR;
01299     }
01300
01301     /* Process Locked */
01302     __HAL_LOCK(husart);
01303
01304     husart->pRxBuffPtr = pRxData;
01305     husart->RxXferSize = Size;
01306     husart->RxXferCount = Size;
01307     husart->pTxBuffPtr = pTxData;
01308     husart->TxXferSize = Size;
01309     husart->TxXferCount = Size;
01310
01311     /* Computation of USART mask to apply to RDR register */
01312     USART_MASK_COMPUTATION(husart);
01313
01314     husart->ErrorCode = HAL_USART_ERROR_NONE;
01315     husart->State = HAL_USART_STATE_BUSY_TX_RX;
01316
01317     /* Configure TxRx interrupt processing */
01318     if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess))
01319     {
01320       /* Set the Rx ISR function pointer according to the data word length */
01321       if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01322       {
01323         husart->TxISR = USART_TxISR_16BIT_FIFOEN;
01324         husart->RxISR = USART_RxISR_16BIT_FIFOEN;
01325       }
01326       else
01327       {
01328         husart->TxISR = USART_TxISR_8BIT_FIFOEN;
01329         husart->RxISR = USART_RxISR_8BIT_FIFOEN;
01330       }
01331
01332       /* Process Locked */
01333       __HAL_UNLOCK(husart);
01334
01335       /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
01336       SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
01337
01338       /* Enable the USART Parity Error interrupt  */
01339       SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
01340
01341       /* Enable the TX and  RX FIFO Threshold interrupts */
01342       SET_BIT(husart->Instance->CR3, (USART_CR3_TXFTIE | USART_CR3_RXFTIE));
01343     }
01344     else
01345     {
01346       if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
01347       {
01348         husart->TxISR = USART_TxISR_16BIT;
01349         husart->RxISR = USART_RxISR_16BIT;
01350       }
01351       else
01352       {
01353         husart->TxISR = USART_TxISR_8BIT;
01354         husart->RxISR = USART_RxISR_8BIT;
01355       }
01356
01357       /* Process Locked */
01358       __HAL_UNLOCK(husart);
01359
01360       /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
01361       SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
01362
01363       /* Enable the USART Parity Error and USART Data Register not empty Interrupts */
01364       SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
01365
01366       /* Enable the USART Transmit Data Register Empty Interrupt */
01367       SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
01368     }
01369
01370     return HAL_OK;
01371   }
01372   else
01373   {
01374     return HAL_BUSY;
01375   }
01376 }
01377
01378 /**
01379   * @brief Send an amount of data in DMA mode.
01380   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01381   *         the sent data is handled as a set of u16. In this case, Size must indicate the number
01382   *         of u16 provided through pTxData.
01383   * @param  husart USART handle.
01384   * @param  pTxData pointer to data buffer (u8 or u16 data elements).
01385   * @param  Size amount of data elements (u8 or u16) to be sent.
01386   * @retval HAL status
01387   */
01388 HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
01389 {
01390   HAL_StatusTypeDef status = HAL_OK;
01391   uint32_t *tmp;
01392
01393
01394   if (husart->State == HAL_USART_STATE_READY)
01395   {
01396     if ((pTxData == NULL) || (Size == 0U))
01397     {
01398       return HAL_ERROR;
01399     }
01400
01401     /* Process Locked */
01402     __HAL_LOCK(husart);
01403
01404     husart->pTxBuffPtr = pTxData;
01405     husart->TxXferSize = Size;
01406     husart->TxXferCount = Size;
01407
01408     husart->ErrorCode = HAL_USART_ERROR_NONE;
01409     husart->State = HAL_USART_STATE_BUSY_TX;
01410
01411     if (husart->hdmatx != NULL)
01412     {
01413       /* Set the USART DMA transfer complete callback */
01414       husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
01415
01416       /* Set the USART DMA Half transfer complete callback */
01417       husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
01418
01419       /* Set the DMA error callback */
01420       husart->hdmatx->XferErrorCallback = USART_DMAError;
01421
01422       /* Enable the USART transmit DMA channel */
01423       tmp = (uint32_t *)&pTxData;
01424       status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size);
01425     }
01426
01427     if(status == HAL_OK)
01428     {
01429       /* Clear the TC flag in the ICR register */
01430       __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
01431
01432       /* Process Unlocked */
01433       __HAL_UNLOCK(husart);
01434
01435       /* Enable the DMA transfer for transmit request by setting the DMAT bit
01436          in the USART CR3 register */
01437       SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01438
01439       return HAL_OK;
01440     }
01441     else
01442     {
01443       /* Set error code to DMA */
01444       husart->ErrorCode = HAL_USART_ERROR_DMA;
01445
01446       /* Process Unlocked */
01447       __HAL_UNLOCK(husart);
01448
01449       /* Restore husart->State to ready */
01450       husart->State = HAL_USART_STATE_READY;
01451
01452       return HAL_ERROR;
01453     }
01454   }
01455   else
01456   {
01457     return HAL_BUSY;
01458   }
01459 }
01460
01461 /**
01462   * @brief Receive an amount of data in DMA mode.
01463   * @note   When the USART parity is enabled (PCE = 1), the received data contain
01464   *         the parity bit (MSB position).
01465   * @note   The USART DMA transmit channel must be configured in order to generate the clock for the slave.
01466   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01467   *         the received data is handled as a set of u16. In this case, Size must indicate the number
01468   *         of u16 available through pRxData.
01469   * @param  husart USART handle.
01470   * @param  pRxData pointer to data buffer (u8 or u16 data elements).
01471   * @param  Size amount of data elements (u8 or u16) to be received.
01472   * @retval HAL status
01473   */
01474 HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
01475 {
01476   HAL_StatusTypeDef status = HAL_OK;
01477   uint32_t *tmp = (uint32_t *)&pRxData;
01478
01479
01480   /* Check that a Rx process is not already ongoing */
01481   if (husart->State == HAL_USART_STATE_READY)
01482   {
01483     if ((pRxData == NULL) || (Size == 0U))
01484     {
01485       return HAL_ERROR;
01486     }
01487
01488     /* Process Locked */
01489     __HAL_LOCK(husart);
01490
01491     husart->pRxBuffPtr = pRxData;
01492     husart->RxXferSize = Size;
01493     husart->pTxBuffPtr = pRxData;
01494     husart->TxXferSize = Size;
01495
01496     husart->ErrorCode = HAL_USART_ERROR_NONE;
01497     husart->State = HAL_USART_STATE_BUSY_RX;
01498
01499     if (husart->hdmarx != NULL)
01500     {
01501       /* Set the USART DMA Rx transfer complete callback */
01502       husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
01503
01504       /* Set the USART DMA Half transfer complete callback */
01505       husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
01506
01507       /* Set the USART DMA Rx transfer error callback */
01508       husart->hdmarx->XferErrorCallback = USART_DMAError;
01509
01510       /* Enable the USART receive DMA channel */
01511       status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t *)tmp, Size);
01512     }
01513
01514     if ((status == HAL_OK) &&
01515         (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
01516     {
01517       /* Enable the USART transmit DMA channel: the transmit channel is used in order
01518          to generate in the non-blocking mode the clock to the slave device,
01519          this mode isn't a simplex receive mode but a full-duplex receive mode */
01520
01521       /* Set the USART DMA Tx Complete and Error callback to Null */
01522       if (husart->hdmatx != NULL)
01523       {
01524         husart->hdmatx->XferErrorCallback = NULL;
01525         husart->hdmatx->XferHalfCpltCallback = NULL;
01526         husart->hdmatx->XferCpltCallback = NULL;
01527         status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size);
01528       }
01529     }
01530
01531     if(status == HAL_OK)
01532     {
01533       /* Process Unlocked */
01534       __HAL_UNLOCK(husart);
01535
01536       /* Enable the USART Parity Error Interrupt */
01537       SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
01538
01539       /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
01540       SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
01541
01542       /* Enable the DMA transfer for the receiver request by setting the DMAR bit
01543          in the USART CR3 register */
01544       SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01545
01546       /* Enable the DMA transfer for transmit request by setting the DMAT bit
01547          in the USART CR3 register */
01548       SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01549
01550       return HAL_OK;
01551     }
01552     else
01553     {
01554       if(husart->hdmarx != NULL)
01555       {
01556         status = HAL_DMA_Abort(husart->hdmarx);
01557       }
01558
01559       /* No need to check on error code */
01560       UNUSED(status);
01561
01562       /* Set error code to DMA */
01563       husart->ErrorCode = HAL_USART_ERROR_DMA;
01564
01565       /* Process Unlocked */
01566       __HAL_UNLOCK(husart);
01567
01568       /* Restore husart->State to ready */
01569       husart->State = HAL_USART_STATE_READY;
01570
01571       return HAL_ERROR;
01572     }
01573   }
01574   else
01575   {
01576     return HAL_BUSY;
01577   }
01578 }
01579
01580 /**
01581   * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
01582   * @note   When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
01583   * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
01584   *         the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
01585   *         of u16 available through pTxData and through pRxData.
01586   * @param  husart USART handle.
01587   * @param  pTxData pointer to TX data buffer (u8 or u16 data elements).
01588   * @param  pRxData pointer to RX data buffer (u8 or u16 data elements).
01589   * @param  Size amount of data elements (u8 or u16) to be received/sent.
01590   * @retval HAL status
01591   */
01592 HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
01593 {
01594   HAL_StatusTypeDef status;
01595   uint32_t *tmp;
01596
01597
01598   if (husart->State == HAL_USART_STATE_READY)
01599   {
01600     if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
01601     {
01602       return HAL_ERROR;
01603     }
01604
01605     /* Process Locked */
01606     __HAL_LOCK(husart);
01607
01608     husart->pRxBuffPtr = pRxData;
01609     husart->RxXferSize = Size;
01610     husart->pTxBuffPtr = pTxData;
01611     husart->TxXferSize = Size;
01612
01613     husart->ErrorCode = HAL_USART_ERROR_NONE;
01614     husart->State = HAL_USART_STATE_BUSY_TX_RX;
01615
01616     if ((husart->hdmarx != NULL) && (husart->hdmatx != NULL))
01617     {
01618       /* Set the USART DMA Rx transfer complete callback */
01619       husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
01620
01621       /* Set the USART DMA Half transfer complete callback */
01622       husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
01623
01624       /* Set the USART DMA Tx transfer complete callback */
01625       husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
01626
01627       /* Set the USART DMA Half transfer complete callback */
01628       husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
01629
01630       /* Set the USART DMA Tx transfer error callback */
01631       husart->hdmatx->XferErrorCallback = USART_DMAError;
01632
01633       /* Set the USART DMA Rx transfer error callback */
01634       husart->hdmarx->XferErrorCallback = USART_DMAError;
01635
01636       /* Enable the USART receive DMA channel */
01637       tmp = (uint32_t *)&pRxData;
01638       status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t *)tmp, Size);
01639
01640       /* Enable the USART transmit DMA channel */
01641       if(status == HAL_OK)
01642       {
01643         tmp = (uint32_t *)&pTxData;
01644         status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size);
01645       }
01646     }
01647     else
01648     {
01649       status = HAL_ERROR;
01650     }
01651
01652     if(status == HAL_OK)
01653     {
01654       /* Process Unlocked */
01655       __HAL_UNLOCK(husart);
01656
01657       /* Enable the USART Parity Error Interrupt */
01658       SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
01659
01660       /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
01661       SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
01662
01663       /* Clear the TC flag in the ICR register */
01664       __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
01665
01666       /* Enable the DMA transfer for the receiver request by setting the DMAR bit
01667          in the USART CR3 register */
01668       SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01669
01670       /* Enable the DMA transfer for transmit request by setting the DMAT bit
01671          in the USART CR3 register */
01672       SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01673
01674       return HAL_OK;
01675     }
01676     else
01677     {
01678       if(husart->hdmarx != NULL)
01679       {
01680         status = HAL_DMA_Abort(husart->hdmarx);
01681       }
01682
01683       /* No need to check on error code */
01684       UNUSED(status);
01685
01686       /* Set error code to DMA */
01687       husart->ErrorCode = HAL_USART_ERROR_DMA;
01688
01689       /* Process Unlocked */
01690       __HAL_UNLOCK(husart);
01691
01692       /* Restore husart->State to ready */
01693       husart->State = HAL_USART_STATE_READY;
01694
01695       return HAL_ERROR;
01696     }
01697   }
01698   else
01699   {
01700     return HAL_BUSY;
01701   }
01702 }
01703
01704 /**
01705   * @brief Pause the DMA Transfer.
01706   * @param  husart USART handle.
01707   * @retval HAL status
01708   */
01709 HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
01710 {
01711   const HAL_USART_StateTypeDef state = husart->State;
01712
01713   /* Process Locked */
01714   __HAL_LOCK(husart);
01715
01716   if ((HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) &&
01717       (state == HAL_USART_STATE_BUSY_TX))
01718   {
01719     /* Disable the USART DMA Tx request */
01720     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01721   }
01722   else if ((state == HAL_USART_STATE_BUSY_RX) ||
01723            (state == HAL_USART_STATE_BUSY_TX_RX))
01724   {
01725     if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
01726     {
01727       /* Disable the USART DMA Tx request */
01728       CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01729     }
01730     if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
01731     {
01732       /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
01733       CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
01734       CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
01735
01736       /* Disable the USART DMA Rx request */
01737       CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01738     }
01739   }
01740   else
01741   {
01742     /* Nothing to do */
01743   }
01744
01745   /* Process Unlocked */
01746   __HAL_UNLOCK(husart);
01747
01748   return HAL_OK;
01749 }
01750
01751 /**
01752   * @brief Resume the DMA Transfer.
01753   * @param  husart USART handle.
01754   * @retval HAL status
01755   */
01756 HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
01757 {
01758   const HAL_USART_StateTypeDef state = husart->State;
01759
01760   /* Process Locked */
01761   __HAL_LOCK(husart);
01762
01763   if (state == HAL_USART_STATE_BUSY_TX)
01764   {
01765     /* Enable the USART DMA Tx request */
01766     SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01767   }
01768   else if ((state == HAL_USART_STATE_BUSY_RX) ||
01769            (state == HAL_USART_STATE_BUSY_TX_RX))
01770   {
01771     /* Clear the Overrun flag before resuming the Rx transfer*/
01772     __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF);
01773
01774     /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
01775     SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
01776     SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
01777
01778     /* Enable the USART DMA Rx request  before the DMA Tx request */
01779     SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01780
01781     /* Enable the USART DMA Tx request */
01782     SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01783   }
01784   else
01785   {
01786     /* Nothing to do */
01787   }
01788
01789   /* Process Unlocked */
01790   __HAL_UNLOCK(husart);
01791
01792   return HAL_OK;
01793 }
01794
01795 /**
01796   * @brief Stop the DMA Transfer.
01797   * @param  husart USART handle.
01798   * @retval HAL status
01799   */
01800 HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
01801 {
01802   /* The Lock is not implemented on this API to allow the user application
01803      to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() /
01804      HAL_USART_TxHalfCpltCallback / HAL_USART_RxHalfCpltCallback:
01805      indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
01806      interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
01807      the stream and the corresponding call back is executed. */
01808
01809   /* Disable the USART Tx/Rx DMA requests */
01810   CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01811   CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01812
01813   /* Abort the USART DMA tx channel */
01814   if (husart->hdmatx != NULL)
01815   {
01816     if (HAL_DMA_Abort(husart->hdmatx) != HAL_OK)
01817     {
01818       if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
01819       {
01820         /* Set error code to DMA */
01821         husart->ErrorCode = HAL_USART_ERROR_DMA;
01822
01823         /* Process Unlocked */
01824         __HAL_UNLOCK(husart);
01825
01826         return HAL_TIMEOUT;
01827       }
01828     }
01829   }
01830   /* Abort the USART DMA rx channel */
01831   if (husart->hdmarx != NULL)
01832   {
01833     if (HAL_DMA_Abort(husart->hdmarx) != HAL_OK)
01834     {
01835       if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
01836       {
01837         /* Set error code to DMA */
01838         husart->ErrorCode = HAL_USART_ERROR_DMA;
01839
01840         /* Process Unlocked */
01841         __HAL_UNLOCK(husart);
01842
01843         return HAL_TIMEOUT;
01844       }
01845     }
01846   }
01847
01848   USART_EndTransfer(husart);
01849   husart->State = HAL_USART_STATE_READY;
01850
01851   return HAL_OK;
01852 }
01853
01854 /**
01855   * @brief  Abort ongoing transfers (blocking mode).
01856   * @param  husart USART handle.
01857   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01858   *         This procedure performs following operations :
01859   *           - Disable USART Interrupts (Tx and Rx)
01860   *           - Disable the DMA transfer in the peripheral register (if enabled)
01861   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01862   *           - Set handle State to READY
01863   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01864   * @retval HAL status
01865 */
01866 HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart)
01867 {
01868   /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */
01869   CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
01870   CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
01871
01872   /* Disable the USART DMA Tx request if enabled */
01873   if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
01874   {
01875     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01876
01877     /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */
01878     if (husart->hdmatx != NULL)
01879     {
01880       /* Set the USART DMA Abort callback to Null.
01881          No call back execution at end of DMA abort procedure */
01882       husart->hdmatx->XferAbortCallback = NULL;
01883
01884       if (HAL_DMA_Abort(husart->hdmatx) != HAL_OK)
01885       {
01886         if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
01887         {
01888           /* Set error code to DMA */
01889           husart->ErrorCode = HAL_USART_ERROR_DMA;
01890
01891           /* Process Unlocked */
01892           __HAL_UNLOCK(husart);
01893
01894           return HAL_TIMEOUT;
01895         }
01896       }
01897     }
01898   }
01899
01900   /* Disable the USART DMA Rx request if enabled */
01901   if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
01902   {
01903     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01904
01905     /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */
01906     if (husart->hdmarx != NULL)
01907     {
01908       /* Set the USART DMA Abort callback to Null.
01909          No call back execution at end of DMA abort procedure */
01910       husart->hdmarx->XferAbortCallback = NULL;
01911
01912       if (HAL_DMA_Abort(husart->hdmarx) != HAL_OK)
01913       {
01914         if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
01915         {
01916           /* Set error code to DMA */
01917           husart->ErrorCode = HAL_USART_ERROR_DMA;
01918
01919           /* Process Unlocked */
01920           __HAL_UNLOCK(husart);
01921
01922           return HAL_TIMEOUT;
01923         }
01924       }
01925     }
01926   }
01927
01928   /* Reset Tx and Rx transfer counters */
01929   husart->TxXferCount = 0U;
01930   husart->RxXferCount = 0U;
01931
01932   /* Clear the Error flags in the ICR register */
01933   __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
01934
01935   /* Flush the whole TX FIFO (if needed) */
01936   if (husart->FifoMode == USART_FIFOMODE_ENABLE)
01937   {
01938     __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
01939   }
01940
01941   /* Discard the received data */
01942   __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
01943
01944   /* Restore husart->State to Ready */
01945   husart->State  = HAL_USART_STATE_READY;
01946
01947   /* Reset Handle ErrorCode to No Error */
01948   husart->ErrorCode = HAL_USART_ERROR_NONE;
01949
01950   return HAL_OK;
01951 }
01952
01953 /**
01954   * @brief  Abort ongoing transfers (Interrupt mode).
01955   * @param  husart USART handle.
01956   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01957   *         This procedure performs following operations :
01958   *           - Disable USART Interrupts (Tx and Rx)
01959   *           - Disable the DMA transfer in the peripheral register (if enabled)
01960   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01961   *           - Set handle State to READY
01962   *           - At abort completion, call user abort complete callback
01963   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01964   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01965   * @retval HAL status
01966 */
01967 HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
01968 {
01969   uint32_t abortcplt = 1U;
01970
01971   /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */
01972   CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
01973   CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
01974
01975   /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised
01976      before any call to DMA Abort functions */
01977   /* DMA Tx Handle is valid */
01978   if (husart->hdmatx != NULL)
01979   {
01980     /* Set DMA Abort Complete callback if USART DMA Tx request if enabled.
01981        Otherwise, set it to NULL */
01982     if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
01983     {
01984       husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback;
01985     }
01986     else
01987     {
01988       husart->hdmatx->XferAbortCallback = NULL;
01989     }
01990   }
01991   /* DMA Rx Handle is valid */
01992   if (husart->hdmarx != NULL)
01993   {
01994     /* Set DMA Abort Complete callback if USART DMA Rx request if enabled.
01995        Otherwise, set it to NULL */
01996     if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
01997     {
01998       husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback;
01999     }
02000     else
02001     {
02002       husart->hdmarx->XferAbortCallback = NULL;
02003     }
02004   }
02005
02006   /* Disable the USART DMA Tx request if enabled */
02007   if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
02008   {
02009     /* Disable DMA Tx at USART level */
02010     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
02011
02012     /* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */
02013     if (husart->hdmatx != NULL)
02014     {
02015       /* USART Tx DMA Abort callback has already been initialised :
02016          will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
02017
02018       /* Abort DMA TX */
02019       if (HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK)
02020       {
02021         husart->hdmatx->XferAbortCallback = NULL;
02022       }
02023       else
02024       {
02025         abortcplt = 0U;
02026       }
02027     }
02028   }
02029
02030   /* Disable the USART DMA Rx request if enabled */
02031   if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
02032   {
02033     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
02034
02035     /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */
02036     if (husart->hdmarx != NULL)
02037     {
02038       /* USART Rx DMA Abort callback has already been initialised :
02039          will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
02040
02041       /* Abort DMA RX */
02042       if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
02043       {
02044         husart->hdmarx->XferAbortCallback = NULL;
02045         abortcplt = 1U;
02046       }
02047       else
02048       {
02049         abortcplt = 0U;
02050       }
02051     }
02052   }
02053
02054   /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
02055   if (abortcplt == 1U)
02056   {
02057     /* Reset Tx and Rx transfer counters */
02058     husart->TxXferCount = 0U;
02059     husart->RxXferCount = 0U;
02060
02061     /* Reset errorCode */
02062     husart->ErrorCode = HAL_USART_ERROR_NONE;
02063
02064     /* Clear the Error flags in the ICR register */
02065     __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
02066
02067     /* Flush the whole TX FIFO (if needed) */
02068     if (husart->FifoMode == USART_FIFOMODE_ENABLE)
02069     {
02070       __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
02071     }
02072
02073     /* Discard the received data */
02074     __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
02075
02076     /* Restore husart->State to Ready */
02077     husart->State  = HAL_USART_STATE_READY;
02078
02079     /* As no DMA to be aborted, call directly user Abort complete callback */
02080 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02081     /* Call registered Abort Complete Callback */
02082     husart->AbortCpltCallback(husart);
02083 #else
02084     /* Call legacy weak Abort Complete Callback */
02085     HAL_USART_AbortCpltCallback(husart);
02086 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02087   }
02088
02089   return HAL_OK;
02090 }
02091
02092 /**
02093   * @brief  Handle USART interrupt request.
02094   * @param  husart USART handle.
02095   * @retval None
02096   */
02097 void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
02098 {
02099   uint32_t isrflags   = READ_REG(husart->Instance->ISR);
02100   uint32_t cr1its     = READ_REG(husart->Instance->CR1);
02101   uint32_t cr3its     = READ_REG(husart->Instance->CR3);
02102
02103   uint32_t errorflags;
02104   uint32_t errorcode;
02105
02106   /* If no error occurs */
02107   errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_UDR));
02108   if (errorflags == 0U)
02109   {
02110     /* USART in mode Receiver ---------------------------------------------------*/
02111     if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
02112         && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
02113             || ((cr3its & USART_CR3_RXFTIE) != 0U)))
02114     {
02115       if (husart->RxISR != NULL)
02116       {
02117         husart->RxISR(husart);
02118       }
02119       return;
02120     }
02121   }
02122
02123   /* If some errors occur */
02124   if ((errorflags != 0U)
02125       && (((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
02126           || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U)))
02127   {
02128     /* USART parity error interrupt occurred -------------------------------------*/
02129     if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
02130     {
02131       __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF);
02132
02133       husart->ErrorCode |= HAL_USART_ERROR_PE;
02134     }
02135
02136     /* USART frame error interrupt occurred --------------------------------------*/
02137     if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
02138     {
02139       __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF);
02140
02141       husart->ErrorCode |= HAL_USART_ERROR_FE;
02142     }
02143
02144     /* USART noise error interrupt occurred --------------------------------------*/
02145     if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
02146     {
02147       __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF);
02148
02149       husart->ErrorCode |= HAL_USART_ERROR_NE;
02150     }
02151
02152     /* USART Over-Run interrupt occurred -----------------------------------------*/
02153     if (((isrflags & USART_ISR_ORE) != 0U)
02154         && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
02155             ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
02156     {
02157       __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);
02158
02159       husart->ErrorCode |= HAL_USART_ERROR_ORE;
02160     }
02161
02162     /* USART SPI slave underrun error interrupt occurred -------------------------*/
02163     if (((isrflags & USART_ISR_UDR) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
02164     {
02165       /* Ignore SPI slave underrun errors when reception is going on */
02166       if (husart->State == HAL_USART_STATE_BUSY_RX)
02167       {
02168         __HAL_USART_CLEAR_UDRFLAG(husart);
02169         return;
02170       }
02171       else
02172       {
02173         __HAL_USART_CLEAR_UDRFLAG(husart);
02174         husart->ErrorCode |= HAL_USART_ERROR_UDR;
02175       }
02176     }
02177
02178     /* Call USART Error Call back function if need be --------------------------*/
02179     if (husart->ErrorCode != HAL_USART_ERROR_NONE)
02180     {
02181       /* USART in mode Receiver ---------------------------------------------------*/
02182       if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
02183           && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
02184               || ((cr3its & USART_CR3_RXFTIE) != 0U)))
02185       {
02186         if (husart->RxISR != NULL)
02187         {
02188           husart->RxISR(husart);
02189         }
02190       }
02191
02192       /* If Overrun error occurs, or if any error occurs in DMA mode reception,
02193          consider error as blocking */
02194       errorcode = husart->ErrorCode & HAL_USART_ERROR_ORE;
02195       if ((HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) ||
02196           (errorcode != 0U))
02197       {
02198         /* Blocking error : transfer is aborted
02199            Set the USART state ready to be able to start again the process,
02200            Disable Interrupts, and disable DMA requests, if ongoing */
02201         USART_EndTransfer(husart);
02202
02203         /* Disable the USART DMA Rx request if enabled */
02204         if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
02205         {
02206           CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR);
02207
02208           /* Abort the USART DMA Tx channel */
02209           if (husart->hdmatx != NULL)
02210           {
02211             /* Set the USART Tx DMA Abort callback to NULL : no callback
02212                executed at end of DMA abort procedure */
02213             husart->hdmatx->XferAbortCallback = NULL;
02214
02215             /* Abort DMA TX */
02216             (void)HAL_DMA_Abort_IT(husart->hdmatx);
02217           }
02218
02219           /* Abort the USART DMA Rx channel */
02220           if (husart->hdmarx != NULL)
02221           {
02222             /* Set the USART Rx DMA Abort callback :
02223                will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */
02224             husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError;
02225
02226             /* Abort DMA RX */
02227             if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
02228             {
02229               /* Call Directly husart->hdmarx->XferAbortCallback function in case of error */
02230               husart->hdmarx->XferAbortCallback(husart->hdmarx);
02231             }
02232           }
02233           else
02234           {
02235             /* Call user error callback */
02236 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02237             /* Call registered Error Callback */
02238             husart->ErrorCallback(husart);
02239 #else
02240             /* Call legacy weak Error Callback */
02241             HAL_USART_ErrorCallback(husart);
02242 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02243           }
02244         }
02245         else
02246         {
02247           /* Call user error callback */
02248 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02249           /* Call registered Error Callback */
02250           husart->ErrorCallback(husart);
02251 #else
02252           /* Call legacy weak Error Callback */
02253           HAL_USART_ErrorCallback(husart);
02254 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02255         }
02256       }
02257       else
02258       {
02259         /* Non Blocking error : transfer could go on.
02260            Error is notified to user through user error callback */
02261 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02262         /* Call registered Error Callback */
02263         husart->ErrorCallback(husart);
02264 #else
02265         /* Call legacy weak Error Callback */
02266         HAL_USART_ErrorCallback(husart);
02267 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02268         husart->ErrorCode = HAL_USART_ERROR_NONE;
02269       }
02270     }
02271     return;
02272
02273   } /* End if some error occurs */
02274
02275
02276   /* USART in mode Transmitter ------------------------------------------------*/
02277   if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
02278       && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
02279           || ((cr3its & USART_CR3_TXFTIE) != 0U)))
02280   {
02281     if (husart->TxISR != NULL)
02282     {
02283       husart->TxISR(husart);
02284     }
02285     return;
02286   }
02287
02288   /* USART in mode Transmitter (transmission end) -----------------------------*/
02289   if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
02290   {
02291     USART_EndTransmit_IT(husart);
02292     return;
02293   }
02294
02295   /* USART TX Fifo Empty occurred ----------------------------------------------*/
02296   if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
02297   {
02298 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02299     /* Call registered Tx Fifo Empty Callback */
02300     husart->TxFifoEmptyCallback(husart);
02301 #else
02302     /* Call legacy weak Tx Fifo Empty Callback */
02303     HAL_USARTEx_TxFifoEmptyCallback(husart);
02304 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02305     return;
02306   }
02307
02308   /* USART RX Fifo Full occurred ----------------------------------------------*/
02309   if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
02310   {
02311 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02312     /* Call registered Rx Fifo Full Callback */
02313     husart->RxFifoFullCallback(husart);
02314 #else
02315     /* Call legacy weak Rx Fifo Full Callback */
02316     HAL_USARTEx_RxFifoFullCallback(husart);
02317 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02318     return;
02319   }
02320 }
02321
02322 /**
02323   * @brief Tx Transfer completed callback.
02324   * @param husart USART handle.
02325   * @retval None
02326   */
02327 __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
02328 {
02329   /* Prevent unused argument(s) compilation warning */
02330   UNUSED(husart);
02331
02332   /* NOTE : This function should not be modified, when the callback is needed,
02333             the HAL_USART_TxCpltCallback can be implemented in the user file.
02334    */
02335 }
02336
02337 /**
02338   * @brief  Tx Half Transfer completed callback.
02339   * @param husart USART handle.
02340   * @retval None
02341   */
02342 __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
02343 {
02344   /* Prevent unused argument(s) compilation warning */
02345   UNUSED(husart);
02346
02347   /* NOTE: This function should not be modified, when the callback is needed,
02348            the HAL_USART_TxHalfCpltCallback can be implemented in the user file.
02349    */
02350 }
02351
02352 /**
02353   * @brief  Rx Transfer completed callback.
02354   * @param husart USART handle.
02355   * @retval None
02356   */
02357 __weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
02358 {
02359   /* Prevent unused argument(s) compilation warning */
02360   UNUSED(husart);
02361
02362   /* NOTE: This function should not be modified, when the callback is needed,
02363            the HAL_USART_RxCpltCallback can be implemented in the user file.
02364    */
02365 }
02366
02367 /**
02368   * @brief Rx Half Transfer completed callback.
02369   * @param husart USART handle.
02370   * @retval None
02371   */
02372 __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
02373 {
02374   /* Prevent unused argument(s) compilation warning */
02375   UNUSED(husart);
02376
02377   /* NOTE : This function should not be modified, when the callback is needed,
02378             the HAL_USART_RxHalfCpltCallback can be implemented in the user file
02379    */
02380 }
02381
02382 /**
02383   * @brief Tx/Rx Transfers completed callback for the non-blocking process.
02384   * @param husart USART handle.
02385   * @retval None
02386   */
02387 __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
02388 {
02389   /* Prevent unused argument(s) compilation warning */
02390   UNUSED(husart);
02391
02392   /* NOTE : This function should not be modified, when the callback is needed,
02393             the HAL_USART_TxRxCpltCallback can be implemented in the user file
02394    */
02395 }
02396
02397 /**
02398   * @brief USART error callback.
02399   * @param husart USART handle.
02400   * @retval None
02401   */
02402 __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
02403 {
02404   /* Prevent unused argument(s) compilation warning */
02405   UNUSED(husart);
02406
02407   /* NOTE : This function should not be modified, when the callback is needed,
02408             the HAL_USART_ErrorCallback can be implemented in the user file.
02409    */
02410 }
02411
02412 /**
02413   * @brief  USART Abort Complete callback.
02414   * @param  husart USART handle.
02415   * @retval None
02416   */
02417 __weak void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart)
02418 {
02419   /* Prevent unused argument(s) compilation warning */
02420   UNUSED(husart);
02421
02422   /* NOTE : This function should not be modified, when the callback is needed,
02423             the HAL_USART_AbortCpltCallback can be implemented in the user file.
02424    */
02425 }
02426
02427 /**
02428   * @}
02429   */
02430
02431 /** @defgroup USART_Exported_Functions_Group4 Peripheral State and Error functions
02432  *  @brief   USART Peripheral State and Error functions
02433  *
02434 @verbatim
02435   ==============================================================================
02436             ##### Peripheral State and Error functions #####
02437   ==============================================================================
02438     [..]
02439     This subsection provides functions allowing to :
02440       (+) Return the USART handle state
02441       (+) Return the USART handle error code
02442
02443 @endverbatim
02444   * @{
02445   */
02446
02447
02448 /**
02449   * @brief Return the USART handle state.
02450   * @param husart pointer to a USART_HandleTypeDef structure that contains
02451   *              the configuration information for the specified USART.
02452   * @retval USART handle state
02453   */
02454 HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
02455 {
02456   return husart->State;
02457 }
02458
02459 /**
02460   * @brief Return the USART error code.
02461   * @param husart pointer to a USART_HandleTypeDef structure that contains
02462   *              the configuration information for the specified USART.
02463   * @retval USART handle Error Code
02464   */
02465 uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
02466 {
02467   return husart->ErrorCode;
02468 }
02469
02470 /**
02471   * @}
02472   */
02473
02474 /**
02475   * @}
02476   */
02477
02478 /** @defgroup USART_Private_Functions USART Private Functions
02479  * @{
02480  */
02481
02482 /**
02483   * @brief  Initialize the callbacks to their default values.
02484   * @param  husart USART handle.
02485   * @retval none
02486   */
02487 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02488 void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart)
02489 {
02490   /* Init the USART Callback settings */
02491   husart->TxHalfCpltCallback        = HAL_USART_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback        */
02492   husart->TxCpltCallback            = HAL_USART_TxCpltCallback;            /* Legacy weak TxCpltCallback            */
02493   husart->RxHalfCpltCallback        = HAL_USART_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback        */
02494   husart->RxCpltCallback            = HAL_USART_RxCpltCallback;            /* Legacy weak RxCpltCallback            */
02495   husart->TxRxCpltCallback          = HAL_USART_TxRxCpltCallback;          /* Legacy weak TxRxCpltCallback          */
02496   husart->ErrorCallback             = HAL_USART_ErrorCallback;             /* Legacy weak ErrorCallback             */
02497   husart->AbortCpltCallback         = HAL_USART_AbortCpltCallback;         /* Legacy weak AbortCpltCallback         */
02498   husart->RxFifoFullCallback        = HAL_USARTEx_RxFifoFullCallback;      /* Legacy weak RxFifoFullCallback        */
02499   husart->TxFifoEmptyCallback       = HAL_USARTEx_TxFifoEmptyCallback;     /* Legacy weak TxFifoEmptyCallback       */
02500 }
02501 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02502
02503 /**
02504   * @brief  End ongoing transfer on USART peripheral (following error detection or Transfer completion).
02505   * @param  husart USART handle.
02506   * @retval None
02507   */
02508 static void USART_EndTransfer(USART_HandleTypeDef *husart)
02509 {
02510   /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */
02511   CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
02512   CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
02513
02514   /* At end of process, restore husart->State to Ready */
02515   husart->State = HAL_USART_STATE_READY;
02516 }
02517
02518 /**
02519   * @brief DMA USART transmit process complete callback.
02520   * @param  hdma DMA handle.
02521   * @retval None
02522   */
02523 static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
02524 {
02525   USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
02526
02527   /* DMA Normal mode */
02528   if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
02529   {
02530     husart->TxXferCount = 0U;
02531
02532     if (husart->State == HAL_USART_STATE_BUSY_TX)
02533     {
02534       /* Disable the DMA transfer for transmit request by resetting the DMAT bit
02535          in the USART CR3 register */
02536       CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
02537
02538       /* Enable the USART Transmit Complete Interrupt */
02539       __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
02540     }
02541   }
02542   /* DMA Circular mode */
02543   else
02544   {
02545     if (husart->State == HAL_USART_STATE_BUSY_TX)
02546     {
02547 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02548       /* Call registered Tx Complete Callback */
02549       husart->TxCpltCallback(husart);
02550 #else
02551       /* Call legacy weak Tx Complete Callback */
02552       HAL_USART_TxCpltCallback(husart);
02553 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02554     }
02555   }
02556 }
02557
02558 /**
02559   * @brief DMA USART transmit process half complete callback.
02560   * @param  hdma DMA handle.
02561   * @retval None
02562   */
02563 static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
02564 {
02565   USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
02566
02567 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02568   /* Call registered Tx Half Complete Callback */
02569   husart->TxHalfCpltCallback(husart);
02570 #else
02571   /* Call legacy weak Tx Half Complete Callback */
02572   HAL_USART_TxHalfCpltCallback(husart);
02573 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02574 }
02575
02576 /**
02577   * @brief DMA USART receive process complete callback.
02578   * @param  hdma DMA handle.
02579   * @retval None
02580   */
02581 static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
02582 {
02583   USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
02584
02585   /* DMA Normal mode */
02586   if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
02587   {
02588     husart->RxXferCount = 0U;
02589
02590     /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
02591     CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
02592     CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
02593
02594     /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit
02595        in USART CR3 register */
02596     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
02597     /* similarly, disable the DMA TX transfer that was started to provide the
02598        clock to the slave device */
02599     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
02600
02601     if (husart->State == HAL_USART_STATE_BUSY_RX)
02602     {
02603 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02604       /* Call registered Rx Complete Callback */
02605       husart->RxCpltCallback(husart);
02606 #else
02607       /* Call legacy weak Rx Complete Callback */
02608       HAL_USART_RxCpltCallback(husart);
02609 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02610     }
02611     /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
02612     else
02613     {
02614 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02615       /* Call registered Tx Rx Complete Callback */
02616       husart->TxRxCpltCallback(husart);
02617 #else
02618       /* Call legacy weak Tx Rx Complete Callback */
02619       HAL_USART_TxRxCpltCallback(husart);
02620 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02621     }
02622     husart->State = HAL_USART_STATE_READY;
02623   }
02624   /* DMA circular mode */
02625   else
02626   {
02627     if (husart->State == HAL_USART_STATE_BUSY_RX)
02628     {
02629 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02630       /* Call registered Rx Complete Callback */
02631       husart->RxCpltCallback(husart);
02632 #else
02633       /* Call legacy weak Rx Complete Callback */
02634       HAL_USART_RxCpltCallback(husart);
02635 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02636     }
02637     /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
02638     else
02639     {
02640 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02641       /* Call registered Tx Rx Complete Callback */
02642       husart->TxRxCpltCallback(husart);
02643 #else
02644       /* Call legacy weak Tx Rx Complete Callback */
02645       HAL_USART_TxRxCpltCallback(husart);
02646 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02647     }
02648   }
02649 }
02650
02651 /**
02652   * @brief DMA USART receive process half complete callback.
02653   * @param  hdma DMA handle.
02654   * @retval None
02655   */
02656 static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
02657 {
02658   USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
02659
02660 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02661   /* Call registered Rx Half Complete Callback */
02662   husart->RxHalfCpltCallback(husart);
02663 #else
02664   /* Call legacy weak Rx Half Complete Callback */
02665   HAL_USART_RxHalfCpltCallback(husart);
02666 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02667 }
02668
02669 /**
02670   * @brief DMA USART communication error callback.
02671   * @param  hdma DMA handle.
02672   * @retval None
02673   */
02674 static void USART_DMAError(DMA_HandleTypeDef *hdma)
02675 {
02676   USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
02677
02678   husart->RxXferCount = 0U;
02679   husart->TxXferCount = 0U;
02680   USART_EndTransfer(husart);
02681
02682   husart->ErrorCode |= HAL_USART_ERROR_DMA;
02683   husart->State = HAL_USART_STATE_READY;
02684
02685 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02686   /* Call registered Error Callback */
02687   husart->ErrorCallback(husart);
02688 #else
02689   /* Call legacy weak Error Callback */
02690   HAL_USART_ErrorCallback(husart);
02691 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02692 }
02693
02694 /**
02695   * @brief  DMA USART communication abort callback, when initiated by HAL services on Error
02696   *         (To be called at end of DMA Abort procedure following error occurrence).
02697   * @param  hdma DMA handle.
02698   * @retval None
02699   */
02700 static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
02701 {
02702   USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
02703   husart->RxXferCount = 0U;
02704   husart->TxXferCount = 0U;
02705
02706 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02707   /* Call registered Error Callback */
02708   husart->ErrorCallback(husart);
02709 #else
02710   /* Call legacy weak Error Callback */
02711   HAL_USART_ErrorCallback(husart);
02712 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02713 }
02714
02715 /**
02716   * @brief  DMA USART Tx communication abort callback, when initiated by user
02717   *         (To be called at end of DMA Tx Abort procedure following user abort request).
02718   * @note   When this callback is executed, User Abort complete call back is called only if no
02719   *         Abort still ongoing for Rx DMA Handle.
02720   * @param  hdma DMA handle.
02721   * @retval None
02722   */
02723 static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
02724 {
02725   USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
02726
02727   husart->hdmatx->XferAbortCallback = NULL;
02728
02729   /* Check if an Abort process is still ongoing */
02730   if (husart->hdmarx != NULL)
02731   {
02732     if (husart->hdmarx->XferAbortCallback != NULL)
02733     {
02734       return;
02735     }
02736   }
02737
02738   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02739   husart->TxXferCount = 0U;
02740   husart->RxXferCount = 0U;
02741
02742   /* Reset errorCode */
02743   husart->ErrorCode = HAL_USART_ERROR_NONE;
02744
02745   /* Clear the Error flags in the ICR register */
02746   __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
02747
02748   /* Restore husart->State to Ready */
02749   husart->State = HAL_USART_STATE_READY;
02750
02751   /* Call user Abort complete callback */
02752 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02753   /* Call registered Abort Complete Callback */
02754   husart->AbortCpltCallback(husart);
02755 #else
02756   /* Call legacy weak Abort Complete Callback */
02757   HAL_USART_AbortCpltCallback(husart);
02758 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02759
02760 }
02761
02762
02763 /**
02764   * @brief  DMA USART Rx communication abort callback, when initiated by user
02765   *         (To be called at end of DMA Rx Abort procedure following user abort request).
02766   * @note   When this callback is executed, User Abort complete call back is called only if no
02767   *         Abort still ongoing for Tx DMA Handle.
02768   * @param  hdma DMA handle.
02769   * @retval None
02770   */
02771 static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
02772 {
02773   USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
02774
02775   husart->hdmarx->XferAbortCallback = NULL;
02776
02777   /* Check if an Abort process is still ongoing */
02778   if (husart->hdmatx != NULL)
02779   {
02780     if (husart->hdmatx->XferAbortCallback != NULL)
02781     {
02782       return;
02783     }
02784   }
02785
02786   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02787   husart->TxXferCount = 0U;
02788   husart->RxXferCount = 0U;
02789
02790   /* Reset errorCode */
02791   husart->ErrorCode = HAL_USART_ERROR_NONE;
02792
02793   /* Clear the Error flags in the ICR register */
02794   __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
02795
02796   /* Restore husart->State to Ready */
02797   husart->State  = HAL_USART_STATE_READY;
02798
02799   /* Call user Abort complete callback */
02800 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
02801   /* Call registered Abort Complete Callback */
02802   husart->AbortCpltCallback(husart);
02803 #else
02804   /* Call legacy weak Abort Complete Callback */
02805   HAL_USART_AbortCpltCallback(husart);
02806 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
02807 }
02808
02809
02810 /**
02811   * @brief  Handle USART Communication Timeout.
02812   * @param  husart USART handle.
02813   * @param  Flag Specifies the USART flag to check.
02814   * @param  Status the Flag status (SET or RESET).
02815   * @param  Tickstart Tick start value
02816   * @param  Timeout timeout duration.
02817   * @retval HAL status
02818   */
02819 static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
02820 {
02821   /* Wait until flag is set */
02822   while ((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)
02823   {
02824     /* Check for the Timeout */
02825     if (Timeout != HAL_MAX_DELAY)
02826     {
02827       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
02828       {
02829         husart->State = HAL_USART_STATE_READY;
02830
02831         /* Process Unlocked */
02832         __HAL_UNLOCK(husart);
02833
02834         return HAL_TIMEOUT;
02835       }
02836     }
02837   }
02838   return HAL_OK;
02839 }
02840
02841 /**
02842   * @brief Configure the USART peripheral.
02843   * @param husart USART handle.
02844   * @retval HAL status
02845   */
02846 static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
02847 {
02848   uint32_t tmpreg;
02849   USART_ClockSourceTypeDef clocksource;
02850   HAL_StatusTypeDef ret                = HAL_OK;
02851   uint16_t brrtemp;
02852   uint32_t usartdiv                    = 0x00000000;
02853   uint32_t pclk;
02854
02855   /* Check the parameters */
02856   assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
02857   assert_param(IS_USART_PHASE(husart->Init.CLKPhase));
02858   assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));
02859   assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));
02860   assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));
02861   assert_param(IS_USART_STOPBITS(husart->Init.StopBits));
02862   assert_param(IS_USART_PARITY(husart->Init.Parity));
02863   assert_param(IS_USART_MODE(husart->Init.Mode));
02864   assert_param(IS_USART_PRESCALER(husart->Init.ClockPrescaler));
02865
02866   /*-------------------------- USART CR1 Configuration -----------------------*/
02867   /* Clear M, PCE, PS, TE and RE bits and configure
02868   *  the USART Word Length, Parity and Mode:
02869   *  set the M bits according to husart->Init.WordLength value
02870   *  set PCE and PS bits according to husart->Init.Parity value
02871   *  set TE and RE bits according to husart->Init.Mode value
02872   *  force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */
02873   tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8;
02874   MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
02875
02876   /*---------------------------- USART CR2 Configuration ---------------------*/
02877   /* Clear and configure the USART Clock, CPOL, CPHA, LBCL STOP and SLVEN bits:
02878    * set CPOL bit according to husart->Init.CLKPolarity value
02879    * set CPHA bit according to husart->Init.CLKPhase value
02880    * set LBCL bit according to husart->Init.CLKLastBit value (used in SPI master mode only)
02881    * set STOP[13:12] bits according to husart->Init.StopBits value */
02882   tmpreg = (uint32_t)(USART_CLOCK_ENABLE);
02883   tmpreg |= (uint32_t)husart->Init.CLKLastBit;
02884   tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase);
02885   tmpreg |= (uint32_t)husart->Init.StopBits;
02886   MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg);
02887
02888   /*-------------------------- USART PRESC Configuration -----------------------*/
02889   /* Configure
02890    * - USART Clock Prescaler : set PRESCALER according to husart->Init.ClockPrescaler value */
02891   MODIFY_REG(husart->Instance->PRESC, USART_PRESC_PRESCALER, husart->Init.ClockPrescaler);
02892
02893   /*-------------------------- USART BRR Configuration -----------------------*/
02894   /* BRR is filled-up according to OVER8 bit setting which is forced to 1     */
02895   USART_GETCLOCKSOURCE(husart, clocksource);
02896
02897   switch (clocksource)
02898   {
02899     case USART_CLOCKSOURCE_PCLK2:
02900       pclk = HAL_RCC_GetPCLK2Freq();
02901       usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler));
02902       break;
02903     case USART_CLOCKSOURCE_HSI:
02904       usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HSI_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler));
02905       break;
02906     case USART_CLOCKSOURCE_SYSCLK:
02907       pclk = HAL_RCC_GetSysClockFreq();
02908       usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler));
02909       break;
02910     case USART_CLOCKSOURCE_LSE:
02911       usartdiv = (uint32_t)(USART_DIV_SAMPLING8(LSE_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler));
02912       break;
02913     default:
02914       ret = HAL_ERROR;
02915       break;
02916   }
02917
02918   /* USARTDIV must be greater than or equal to 0d16 and smaller than or equal to ffff */
02919   if ((usartdiv >= USART_BRR_MIN) && (usartdiv <= USART_BRR_MAX))
02920   {
02921     brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
02922     brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
02923     husart->Instance->BRR = brrtemp;
02924   }
02925   else
02926   {
02927     ret = HAL_ERROR;
02928   }
02929
02930   /* Initialize the number of data to process during RX/TX ISR execution */
02931   husart->NbTxDataToProcess = 1U;
02932   husart->NbRxDataToProcess = 1U;
02933
02934   /* Clear ISR function pointers */
02935   husart->RxISR   = NULL;
02936   husart->TxISR   = NULL;
02937
02938   return ret;
02939 }
02940
02941 /**
02942   * @brief Check the USART Idle State.
02943   * @param husart USART handle.
02944   * @retval HAL status
02945   */
02946 static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart)
02947 {
02948   uint32_t tickstart;
02949
02950   /* Initialize the USART ErrorCode */
02951   husart->ErrorCode = HAL_USART_ERROR_NONE;
02952
02953   /* Init tickstart for timeout managment*/
02954   tickstart = HAL_GetTick();
02955
02956   /* Check if the Transmitter is enabled */
02957   if ((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
02958   {
02959     /* Wait until TEACK flag is set */
02960     if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
02961     {
02962       /* Timeout occurred */
02963       return HAL_TIMEOUT;
02964     }
02965   }
02966   /* Check if the Receiver is enabled */
02967   if ((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
02968   {
02969     /* Wait until REACK flag is set */
02970     if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
02971     {
02972       /* Timeout occurred */
02973       return HAL_TIMEOUT;
02974     }
02975   }
02976
02977   /* Initialize the USART state*/
02978   husart->State = HAL_USART_STATE_READY;
02979
02980   /* Process Unlocked */
02981   __HAL_UNLOCK(husart);
02982
02983   return HAL_OK;
02984 }
02985
02986 /**
02987   * @brief  Simplex send an amount of data in non-blocking mode.
02988   * @note   Function called under interruption only, once
02989   *         interruptions have been enabled by HAL_USART_Transmit_IT().
02990   * @note   The USART errors are not managed to avoid the overrun error.
02991   * @note   ISR function executed when FIFO mode is disabled and when the
02992   *         data word length is less than 9 bits long.
02993   * @param  husart USART handle.
02994   * @retval None
02995   */
02996 static void USART_TxISR_8BIT(USART_HandleTypeDef *husart)
02997 {
02998   const HAL_USART_StateTypeDef state = husart->State;
02999
03000   /* Check that a Tx process is ongoing */
03001   if ((state == HAL_USART_STATE_BUSY_TX) ||
03002       (state == HAL_USART_STATE_BUSY_TX_RX))
03003   {
03004     if (husart->TxXferCount == 0U)
03005     {
03006       /* Disable the USART Transmit data register empty interrupt */
03007       __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
03008
03009       /* Enable the USART Transmit Complete Interrupt */
03010       __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
03011     }
03012     else
03013     {
03014       husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr & (uint8_t)0xFF);
03015       husart->pTxBuffPtr++;
03016       husart->TxXferCount--;
03017     }
03018   }
03019 }
03020
03021 /**
03022   * @brief  Simplex send an amount of data in non-blocking mode.
03023   * @note   Function called under interruption only, once
03024   *         interruptions have been enabled by HAL_USART_Transmit_IT().
03025   * @note   The USART errors are not managed to avoid the overrun error.
03026   * @note   ISR function executed when FIFO mode is disabled and when the
03027   *         data word length is 9 bits long.
03028   * @param  husart USART handle.
03029   * @retval None
03030   */
03031 static void USART_TxISR_16BIT(USART_HandleTypeDef *husart)
03032 {
03033   const HAL_USART_StateTypeDef state = husart->State;
03034   uint16_t *tmp;
03035
03036   if ((state == HAL_USART_STATE_BUSY_TX) ||
03037       (state == HAL_USART_STATE_BUSY_TX_RX))
03038   {
03039     if (husart->TxXferCount == 0U)
03040     {
03041       /* Disable the USART Transmit data register empty interrupt */
03042       __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
03043
03044       /* Enable the USART Transmit Complete Interrupt */
03045       __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
03046     }
03047     else
03048     {
03049       tmp = (uint16_t *) husart->pTxBuffPtr;
03050       husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);
03051       husart->pTxBuffPtr += 2U;
03052       husart->TxXferCount--;
03053     }
03054   }
03055 }
03056
03057 /**
03058   * @brief  Simplex send an amount of data in non-blocking mode.
03059   * @note   Function called under interruption only, once
03060   *         interruptions have been enabled by HAL_USART_Transmit_IT().
03061   * @note   The USART errors are not managed to avoid the overrun error.
03062   * @note   ISR function executed when FIFO mode is enabled and when the
03063   *         data word length is less than 9 bits long.
03064   * @param  husart USART handle.
03065   * @retval None
03066   */
03067 static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart)
03068 {
03069   const HAL_USART_StateTypeDef state = husart->State;
03070   uint16_t  nb_tx_data;
03071
03072   /* Check that a Tx process is ongoing */
03073   if ((state == HAL_USART_STATE_BUSY_TX) ||
03074       (state == HAL_USART_STATE_BUSY_TX_RX))
03075   {
03076     for (nb_tx_data = husart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
03077     {
03078       if (husart->TxXferCount == 0U)
03079       {
03080         /* Disable the TX FIFO threshold interrupt */
03081         __HAL_USART_DISABLE_IT(husart, USART_IT_TXFT);
03082
03083         /* Enable the USART Transmit Complete Interrupt */
03084         __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
03085
03086         break; /* force exit loop */
03087       }
03088       else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET)
03089       {
03090         husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr & (uint8_t)0xFF);
03091         husart->pTxBuffPtr++;
03092         husart->TxXferCount--;
03093       }
03094       else
03095       {
03096         /* Nothing to do */
03097       }
03098     }
03099   }
03100 }
03101
03102 /**
03103   * @brief  Simplex send an amount of data in non-blocking mode.
03104   * @note   Function called under interruption only, once
03105   *         interruptions have been enabled by HAL_USART_Transmit_IT().
03106   * @note   The USART errors are not managed to avoid the overrun error.
03107   * @note   ISR function executed when FIFO mode is enabled and when the
03108   *         data word length is 9 bits long.
03109   * @param  husart USART handle.
03110   * @retval None
03111   */
03112 static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart)
03113 {
03114   const HAL_USART_StateTypeDef state = husart->State;
03115   uint16_t *tmp;
03116   uint16_t  nb_tx_data;
03117
03118   /* Check that a Tx process is ongoing */
03119   if ((state == HAL_USART_STATE_BUSY_TX) ||
03120       (state == HAL_USART_STATE_BUSY_TX_RX))
03121   {
03122     for (nb_tx_data = husart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
03123     {
03124       if (husart->TxXferCount == 0U)
03125       {
03126         /* Disable the TX FIFO threshold interrupt */
03127         __HAL_USART_DISABLE_IT(husart, USART_IT_TXFT);
03128
03129         /* Enable the USART Transmit Complete Interrupt */
03130         __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
03131
03132         break; /* force exit loop */
03133       }
03134       else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET)
03135       {
03136         tmp = (uint16_t *) husart->pTxBuffPtr;
03137         husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);
03138         husart->pTxBuffPtr += 2U;
03139         husart->TxXferCount--;
03140       }
03141       else
03142       {
03143         /* Nothing to do */
03144       }
03145     }
03146   }
03147 }
03148
03149 /**
03150   * @brief  Wraps up transmission in non-blocking mode.
03151   * @param  husart Pointer to a USART_HandleTypeDef structure that contains
03152   *                the configuration information for the specified USART module.
03153   * @retval None
03154   */
03155 static void USART_EndTransmit_IT(USART_HandleTypeDef *husart)
03156 {
03157   /* Disable the USART Transmit Complete Interrupt */
03158   __HAL_USART_DISABLE_IT(husart, USART_IT_TC);
03159
03160   /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
03161   __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
03162
03163   /* Clear TxISR function pointer */
03164   husart->TxISR = NULL;
03165
03166   if (husart->State == HAL_USART_STATE_BUSY_TX)
03167   {
03168     /* Clear overrun flag and discard the received data */
03169     __HAL_USART_CLEAR_OREFLAG(husart);
03170     __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
03171
03172     /* Tx process is completed, restore husart->State to Ready */
03173     husart->State = HAL_USART_STATE_READY;
03174
03175 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03176     /* Call registered Tx Complete Callback */
03177     husart->TxCpltCallback(husart);
03178 #else
03179     /* Call legacy weak Tx Complete Callback */
03180     HAL_USART_TxCpltCallback(husart);
03181 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03182   }
03183   else if (husart->RxXferCount == 0U)
03184   {
03185     /* TxRx process is completed, restore husart->State to Ready */
03186     husart->State = HAL_USART_STATE_READY;
03187
03188 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03189     /* Call registered Tx Rx Complete Callback */
03190     husart->TxRxCpltCallback(husart);
03191 #else
03192     /* Call legacy weak Tx Rx Complete Callback */
03193     HAL_USART_TxRxCpltCallback(husart);
03194 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03195   }
03196   else
03197   {
03198     /* Nothing to do */
03199   }
03200 }
03201
03202
03203 /**
03204   * @brief  Simplex receive an amount of data in non-blocking mode.
03205   * @note   Function called under interruption only, once
03206   *         interruptions have been enabled by HAL_USART_Receive_IT().
03207   * @note   ISR function executed when FIFO mode is disabled and when the
03208   *         data word length is less than 9 bits long.
03209   * @param  husart USART handle
03210   * @retval None
03211   */
03212 static void USART_RxISR_8BIT(USART_HandleTypeDef *husart)
03213 {
03214   const HAL_USART_StateTypeDef state = husart->State;
03215   uint16_t txdatacount;
03216   uint16_t uhMask = husart->Mask;
03217
03218   if ((state == HAL_USART_STATE_BUSY_RX) ||
03219       (state == HAL_USART_STATE_BUSY_TX_RX))
03220   {
03221     *husart->pRxBuffPtr = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
03222     husart->pRxBuffPtr++;
03223     husart->RxXferCount--;
03224
03225     if (husart->RxXferCount == 0U)
03226     {
03227       /* Disable the USART Parity Error Interrupt and RXNE interrupt*/
03228       CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
03229
03230       /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
03231       CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
03232
03233       /* Clear RxISR function pointer */
03234       husart->RxISR = NULL;
03235
03236       /* txdatacount is a temporary variable for MISRAC2012-Rule-13.5 */
03237       txdatacount = husart->TxXferCount;
03238
03239       if (state == HAL_USART_STATE_BUSY_RX)
03240       {
03241         /* Clear SPI slave underrun flag and discard transmit data */
03242         if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)
03243         {
03244           __HAL_USART_CLEAR_UDRFLAG(husart);
03245           __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
03246         }
03247
03248         /* Rx process is completed, restore husart->State to Ready */
03249         husart->State = HAL_USART_STATE_READY;
03250
03251 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03252         /* Call registered Rx Complete Callback */
03253         husart->RxCpltCallback(husart);
03254 #else
03255         /* Call legacy weak Rx Complete Callback */
03256         HAL_USART_RxCpltCallback(husart);
03257 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03258       }
03259       else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) &&
03260                (txdatacount == 0U))
03261       {
03262         /* TxRx process is completed, restore husart->State to Ready */
03263         husart->State = HAL_USART_STATE_READY;
03264
03265 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03266         /* Call registered Tx Rx Complete Callback */
03267         husart->TxRxCpltCallback(husart);
03268 #else
03269         /* Call legacy weak Tx Rx Complete Callback */
03270         HAL_USART_TxRxCpltCallback(husart);
03271 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03272       }
03273       else
03274       {
03275         /* Nothing to do */
03276       }
03277     }
03278     else if ((state == HAL_USART_STATE_BUSY_RX) &&
03279              (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
03280     {
03281       /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
03282       husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
03283     }
03284     else
03285     {
03286       /* Nothing to do */
03287     }
03288   }
03289 }
03290
03291 /**
03292   * @brief  Simplex receive an amount of data in non-blocking mode.
03293   * @note   Function called under interruption only, once
03294   *         interruptions have been enabled by HAL_USART_Receive_IT().
03295   * @note   ISR function executed when FIFO mode is disabled and when the
03296   *         data word length is 9 bits long.
03297   * @param  husart USART handle
03298   * @retval None
03299   */
03300 static void USART_RxISR_16BIT(USART_HandleTypeDef *husart)
03301 {
03302   const HAL_USART_StateTypeDef state = husart->State;
03303   uint16_t txdatacount;
03304   uint16_t *tmp;
03305   uint16_t uhMask = husart->Mask;
03306
03307   if ((state == HAL_USART_STATE_BUSY_RX) ||
03308       (state == HAL_USART_STATE_BUSY_TX_RX))
03309   {
03310     tmp = (uint16_t *) husart->pRxBuffPtr;
03311     *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
03312     husart->pRxBuffPtr += 2U;
03313     husart->RxXferCount--;
03314
03315     if (husart->RxXferCount == 0U)
03316     {
03317       /* Disable the USART Parity Error Interrupt and RXNE interrupt*/
03318       CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
03319
03320       /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
03321       CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
03322
03323       /* Clear RxISR function pointer */
03324       husart->RxISR = NULL;
03325
03326       /* txdatacount is a temporary variable for MISRAC2012-Rule-13.5 */
03327       txdatacount = husart->TxXferCount;
03328
03329       if (state == HAL_USART_STATE_BUSY_RX)
03330       {
03331         /* Clear SPI slave underrun flag and discard transmit data */
03332         if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)
03333         {
03334           __HAL_USART_CLEAR_UDRFLAG(husart);
03335           __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
03336         }
03337
03338         /* Rx process is completed, restore husart->State to Ready */
03339         husart->State = HAL_USART_STATE_READY;
03340
03341 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03342         /* Call registered Rx Complete Callback */
03343         husart->RxCpltCallback(husart);
03344 #else
03345         /* Call legacy weak Rx Complete Callback */
03346         HAL_USART_RxCpltCallback(husart);
03347 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03348       }
03349       else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) &&
03350                (txdatacount == 0U))
03351       {
03352         /* TxRx process is completed, restore husart->State to Ready */
03353         husart->State = HAL_USART_STATE_READY;
03354
03355 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03356         /* Call registered Tx Rx Complete Callback */
03357         husart->TxRxCpltCallback(husart);
03358 #else
03359         /* Call legacy weak Tx Rx Complete Callback */
03360         HAL_USART_TxRxCpltCallback(husart);
03361 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03362       }
03363       else
03364       {
03365         /* Nothing to do */
03366       }
03367     }
03368     else if ((state == HAL_USART_STATE_BUSY_RX) &&
03369              (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
03370     {
03371       /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
03372       husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
03373     }
03374     else
03375     {
03376       /* Nothing to do */
03377     }
03378   }
03379 }
03380
03381 /**
03382   * @brief  Simplex receive an amount of data in non-blocking mode.
03383   * @note   Function called under interruption only, once
03384   *         interruptions have been enabled by HAL_USART_Receive_IT().
03385   * @note   ISR function executed when FIFO mode is enabled and when the
03386   *         data word length is less than 9 bits long.
03387   * @param  husart USART handle
03388   * @retval None
03389   */
03390 static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart)
03391 {
03392   HAL_USART_StateTypeDef state = husart->State;
03393   uint16_t txdatacount;
03394   uint16_t rxdatacount;
03395   uint16_t uhMask = husart->Mask;
03396   uint16_t nb_rx_data;
03397
03398   /* Check that a Rx process is ongoing */
03399   if ((state == HAL_USART_STATE_BUSY_RX) ||
03400       (state == HAL_USART_STATE_BUSY_TX_RX))
03401   {
03402     for (nb_rx_data = husart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)
03403     {
03404       if (__HAL_USART_GET_FLAG(husart, USART_FLAG_RXFNE) == SET)
03405       {
03406         *husart->pRxBuffPtr = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU));
03407         husart->pRxBuffPtr++;
03408         husart->RxXferCount--;
03409
03410         if (husart->RxXferCount == 0U)
03411         {
03412           /* Disable the USART Parity Error Interrupt */
03413           CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
03414
03415           /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
03416           CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
03417
03418           /* Clear RxISR function pointer */
03419           husart->RxISR = NULL;
03420
03421           /* txdatacount is a temporary variable for MISRAC2012-Rule-13.5 */
03422           txdatacount = husart->TxXferCount;
03423
03424           if (state == HAL_USART_STATE_BUSY_RX)
03425           {
03426             /* Clear SPI slave underrun flag and discard transmit data */
03427             if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)
03428             {
03429               __HAL_USART_CLEAR_UDRFLAG(husart);
03430               __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
03431             }
03432
03433             /* Rx process is completed, restore husart->State to Ready */
03434             husart->State = HAL_USART_STATE_READY;
03435             state = HAL_USART_STATE_READY;
03436
03437 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03438             /* Call registered Rx Complete Callback */
03439             husart->RxCpltCallback(husart);
03440 #else
03441             /* Call legacy weak Rx Complete Callback */
03442             HAL_USART_RxCpltCallback(husart);
03443 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03444           }
03445           else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) &&
03446                    (txdatacount == 0U))
03447           {
03448             /* TxRx process is completed, restore husart->State to Ready */
03449             husart->State = HAL_USART_STATE_READY;
03450             state = HAL_USART_STATE_READY;
03451
03452 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03453             /* Call registered Tx Rx Complete Callback */
03454             husart->TxRxCpltCallback(husart);
03455 #else
03456             /* Call legacy weak Tx Rx Complete Callback */
03457             HAL_USART_TxRxCpltCallback(husart);
03458 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03459           }
03460           else
03461           {
03462             /* Nothing to do */
03463           }
03464         }
03465         else if ((state == HAL_USART_STATE_BUSY_RX) &&
03466                  (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
03467         {
03468           /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
03469           husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
03470         }
03471         else
03472         {
03473           /* Nothing to do */
03474         }
03475       }
03476     }
03477
03478     /* When remaining number of bytes to receive is less than the RX FIFO
03479     threshold, next incoming frames are processed as if FIFO mode was
03480     disabled (i.e. one interrupt per received frame).
03481     */
03482     rxdatacount = husart->RxXferCount;
03483     if (((rxdatacount != 0U)) && (rxdatacount < husart->NbRxDataToProcess))
03484     {
03485       /* Disable the USART RXFT interrupt*/
03486       CLEAR_BIT(husart->Instance->CR3, USART_CR3_RXFTIE);
03487
03488       /* Update the RxISR function pointer */
03489       husart->RxISR = USART_RxISR_8BIT;
03490
03491       /* Enable the USART Data Register Not Empty interrupt */
03492       SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
03493
03494       if ((husart->TxXferCount == 0U) &&
03495           (state == HAL_USART_STATE_BUSY_TX_RX) &&
03496           (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
03497       {
03498         /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
03499         husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
03500       }
03501     }
03502   }
03503   else
03504   {
03505     /* Clear RXNE interrupt flag */
03506     __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
03507   }
03508 }
03509
03510 /**
03511   * @brief  Simplex receive an amount of data in non-blocking mode.
03512   * @note   Function called under interruption only, once
03513   *         interruptions have been enabled by HAL_USART_Receive_IT().
03514   * @note   ISR function executed when FIFO mode is enabled and when the
03515   *         data word length is 9 bits long.
03516   * @param  husart USART handle
03517   * @retval None
03518   */
03519 static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart)
03520 {
03521   HAL_USART_StateTypeDef state = husart->State;
03522   uint16_t txdatacount;
03523   uint16_t rxdatacount;
03524   uint16_t *tmp;
03525   uint16_t uhMask = husart->Mask;
03526   uint16_t nb_rx_data;
03527
03528   /* Check that a Tx process is ongoing */
03529   if ((state == HAL_USART_STATE_BUSY_RX) ||
03530       (state == HAL_USART_STATE_BUSY_TX_RX))
03531   {
03532     for (nb_rx_data = husart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)
03533     {
03534       if (__HAL_USART_GET_FLAG(husart, USART_FLAG_RXFNE) == SET)
03535       {
03536         tmp = (uint16_t *) husart->pRxBuffPtr;
03537         *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
03538         husart->pRxBuffPtr += 2U;
03539         husart->RxXferCount--;
03540
03541         if (husart->RxXferCount == 0U)
03542         {
03543           /* Disable the USART Parity Error Interrupt */
03544           CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
03545
03546           /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
03547           CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
03548
03549           /* Clear RxISR function pointer */
03550           husart->RxISR = NULL;
03551
03552           /* txdatacount is a temporary variable for MISRAC2012-Rule-13.5 */
03553           txdatacount = husart->TxXferCount;
03554
03555           if (state == HAL_USART_STATE_BUSY_RX)
03556           {
03557             /* Clear SPI slave underrun flag and discard transmit data */
03558             if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)
03559             {
03560               __HAL_USART_CLEAR_UDRFLAG(husart);
03561               __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
03562             }
03563
03564             /* Rx process is completed, restore husart->State to Ready */
03565             husart->State = HAL_USART_STATE_READY;
03566             state = HAL_USART_STATE_READY;
03567
03568 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03569             /* Call registered Rx Complete Callback */
03570             husart->RxCpltCallback(husart);
03571 #else
03572             /* Call legacy weak Rx Complete Callback */
03573             HAL_USART_RxCpltCallback(husart);
03574 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03575           }
03576           else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) &&
03577                    (txdatacount == 0U))
03578           {
03579             /* TxRx process is completed, restore husart->State to Ready */
03580             husart->State = HAL_USART_STATE_READY;
03581             state = HAL_USART_STATE_READY;
03582
03583 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
03584             /* Call registered Tx Rx Complete Callback */
03585             husart->TxRxCpltCallback(husart);
03586 #else
03587             /* Call legacy weak Tx Rx Complete Callback */
03588             HAL_USART_TxRxCpltCallback(husart);
03589 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
03590           }
03591           else
03592           {
03593             /* Nothing to do */
03594           }
03595         }
03596         else if ((state == HAL_USART_STATE_BUSY_RX) &&
03597                  (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
03598         {
03599           /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
03600           husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
03601         }
03602         else
03603         {
03604           /* Nothing to do */
03605         }
03606       }
03607     }
03608
03609     /* When remaining number of bytes to receive is less than the RX FIFO
03610     threshold, next incoming frames are processed as if FIFO mode was
03611     disabled (i.e. one interrupt per received frame).
03612     */
03613     rxdatacount = husart->RxXferCount;
03614     if (((rxdatacount != 0U)) && (rxdatacount < husart->NbRxDataToProcess))
03615     {
03616       /* Disable the USART RXFT interrupt*/
03617       CLEAR_BIT(husart->Instance->CR3, USART_CR3_RXFTIE);
03618
03619       /* Update the RxISR function pointer */
03620       husart->RxISR = USART_RxISR_16BIT;
03621
03622       /* Enable the USART Data Register Not Empty interrupt */
03623       SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
03624
03625       if ((husart->TxXferCount == 0U) &&
03626           (state == HAL_USART_STATE_BUSY_TX_RX) &&
03627           (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
03628       {
03629         /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
03630         husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
03631       }
03632     }
03633   }
03634   else
03635   {
03636     /* Clear RXNE interrupt flag */
03637     __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
03638   }
03639 }
03640
03641 /**
03642   * @}
03643   */
03644
03645 #endif /* HAL_USART_MODULE_ENABLED */
03646 /**
03647   * @}
03648   */
03649
03650 /**
03651   * @}
03652   */
03653
03654 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_usart.h Source File

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stm32wbxx_hal_usart.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_usart.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of USART HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_USART_H
00022 #define STM32WBxx_HAL_USART_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 /** @addtogroup STM32WBxx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup USART
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /** @defgroup USART_Exported_Types USART Exported Types
00041   * @{
00042   */
00043
00044 /**
00045   * @brief USART Init Structure definition
00046   */
00047 typedef struct
00048 {
00049   uint32_t BaudRate;                  /*!< This member configures the Usart communication baud rate.
00050                                            The baud rate is computed using the following formula:
00051                                               Baud Rate Register[15:4] = ((2 * fclk_pres) / ((huart->Init.BaudRate)))[15:4]
00052                                               Baud Rate Register[3]    = 0
00053                                               Baud Rate Register[2:0]  =  (((2 * fclk_pres) / ((huart->Init.BaudRate)))[3:0]) >> 1
00054                                               where fclk_pres is the USART input clock frequency (fclk) divided by a prescaler.
00055                                            @note  Oversampling by 8 is systematically applied to achieve high baud rates. */
00056
00057   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
00058                                            This parameter can be a value of @ref USARTEx_Word_Length. */
00059
00060   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
00061                                            This parameter can be a value of @ref USART_Stop_Bits. */
00062
00063   uint32_t Parity;                   /*!< Specifies the parity mode.
00064                                            This parameter can be a value of @ref USART_Parity
00065                                            @note When parity is enabled, the computed parity is inserted
00066                                                  at the MSB position of the transmitted data (9th bit when
00067                                                  the word length is set to 9 data bits; 8th bit when the
00068                                                  word length is set to 8 data bits). */
00069
00070   uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
00071                                            This parameter can be a value of @ref USART_Mode. */
00072
00073   uint32_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.
00074                                            This parameter can be a value of @ref USART_Clock_Polarity. */
00075
00076   uint32_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.
00077                                            This parameter can be a value of @ref USART_Clock_Phase. */
00078
00079   uint32_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
00080                                            data bit (MSB) has to be output on the SCLK pin in synchronous mode.
00081                                            This parameter can be a value of @ref USART_Last_Bit. */
00082
00083   uint32_t ClockPrescaler;            /*!< Specifies the prescaler value used to divide the USART clock source.
00084                                            This parameter can be a value of @ref USART_ClockPrescaler. */
00085 } USART_InitTypeDef;
00086
00087 /**
00088   * @brief HAL USART State structures definition
00089   */
00090 typedef enum
00091 {
00092   HAL_USART_STATE_RESET             = 0x00U,    /*!< Peripheral is not initialized                  */
00093   HAL_USART_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use       */
00094   HAL_USART_STATE_BUSY              = 0x02U,    /*!< an internal process is ongoing                 */
00095   HAL_USART_STATE_BUSY_TX           = 0x12U,    /*!< Data Transmission process is ongoing           */
00096   HAL_USART_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing              */
00097   HAL_USART_STATE_BUSY_TX_RX        = 0x32U,    /*!< Data Transmission Reception process is ongoing */
00098   HAL_USART_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                                  */
00099   HAL_USART_STATE_ERROR             = 0x04U     /*!< Error                                          */
00100 } HAL_USART_StateTypeDef;
00101
00102 /**
00103   * @brief  USART clock sources definitions
00104   */
00105 typedef enum
00106 {
00107   USART_CLOCKSOURCE_PCLK2      = 0x01U,    /*!< PCLK2 clock source     */
00108   USART_CLOCKSOURCE_HSI        = 0x02U,    /*!< HSI clock source       */
00109   USART_CLOCKSOURCE_SYSCLK     = 0x04U,    /*!< SYSCLK clock source    */
00110   USART_CLOCKSOURCE_LSE        = 0x08U,    /*!< LSE clock source       */
00111   USART_CLOCKSOURCE_UNDEFINED  = 0x10U     /*!< Undefined clock source */
00112 } USART_ClockSourceTypeDef;
00113
00114 /**
00115   * @brief  USART handle Structure definition
00116   */
00117 typedef struct __USART_HandleTypeDef
00118 {
00119   USART_TypeDef                 *Instance;               /*!< USART registers base address        */
00120
00121   USART_InitTypeDef             Init;                    /*!< USART communication parameters      */
00122
00123   uint8_t                       *pTxBuffPtr;             /*!< Pointer to USART Tx transfer Buffer */
00124
00125   uint16_t                      TxXferSize;              /*!< USART Tx Transfer size              */
00126
00127   __IO uint16_t                 TxXferCount;             /*!< USART Tx Transfer Counter           */
00128
00129   uint8_t                       *pRxBuffPtr;             /*!< Pointer to USART Rx transfer Buffer */
00130
00131   uint16_t                      RxXferSize;              /*!< USART Rx Transfer size              */
00132
00133   __IO uint16_t                 RxXferCount;             /*!< USART Rx Transfer Counter           */
00134
00135   uint16_t                      Mask;                    /*!< USART Rx RDR register mask          */
00136
00137   uint16_t                      NbRxDataToProcess;       /*!< Number of data to process during RX ISR execution */
00138
00139   uint16_t                      NbTxDataToProcess;       /*!< Number of data to process during TX ISR execution */
00140
00141   uint32_t                      SlaveMode;               /*!< Enable/Disable UART SPI Slave Mode. This parameter can be a value
00142                                                               of @ref USARTEx_Slave_Mode */
00143
00144   uint32_t                      FifoMode;                /*!< Specifies if the FIFO mode will be used. This parameter can be a value
00145                                                               of @ref USARTEx_FIFO_mode. */
00146
00147   void (*RxISR)(struct __USART_HandleTypeDef *husart);   /*!< Function pointer on Rx IRQ handler  */
00148
00149   void (*TxISR)(struct __USART_HandleTypeDef *husart);   /*!< Function pointer on Tx IRQ handler  */
00150
00151   DMA_HandleTypeDef             *hdmatx;                 /*!< USART Tx DMA Handle parameters      */
00152
00153   DMA_HandleTypeDef             *hdmarx;                 /*!< USART Rx DMA Handle parameters      */
00154
00155   HAL_LockTypeDef               Lock;                    /*!< Locking object                      */
00156
00157   __IO HAL_USART_StateTypeDef   State;                   /*!< USART communication state           */
00158
00159   __IO uint32_t                 ErrorCode;               /*!< USART Error code                    */
00160
00161 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
00162   void (* TxHalfCpltCallback)(struct __USART_HandleTypeDef *husart);        /*!< USART Tx Half Complete Callback        */
00163   void (* TxCpltCallback)(struct __USART_HandleTypeDef *husart);            /*!< USART Tx Complete Callback             */
00164   void (* RxHalfCpltCallback)(struct __USART_HandleTypeDef *husart);        /*!< USART Rx Half Complete Callback        */
00165   void (* RxCpltCallback)(struct __USART_HandleTypeDef *husart);            /*!< USART Rx Complete Callback             */
00166   void (* TxRxCpltCallback)(struct __USART_HandleTypeDef *husart);          /*!< USART Tx Rx Complete Callback          */
00167   void (* ErrorCallback)(struct __USART_HandleTypeDef *husart);             /*!< USART Error Callback                   */
00168   void (* AbortCpltCallback)(struct __USART_HandleTypeDef *husart);         /*!< USART Abort Complete Callback          */
00169   void (* RxFifoFullCallback)(struct __USART_HandleTypeDef *husart);        /*!< USART Rx Fifo Full Callback            */
00170   void (* TxFifoEmptyCallback)(struct __USART_HandleTypeDef *husart);       /*!< USART Tx Fifo Empty Callback           */
00171
00172   void (* MspInitCallback)(struct __USART_HandleTypeDef *husart);           /*!< USART Msp Init callback                */
00173   void (* MspDeInitCallback)(struct __USART_HandleTypeDef *husart);         /*!< USART Msp DeInit callback              */
00174 #endif  /* USE_HAL_USART_REGISTER_CALLBACKS */
00175
00176 } USART_HandleTypeDef;
00177
00178 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
00179 /**
00180   * @brief  HAL USART Callback ID enumeration definition
00181   */
00182 typedef enum
00183 {
00184   HAL_USART_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< USART Tx Half Complete Callback ID        */
00185   HAL_USART_TX_COMPLETE_CB_ID             = 0x01U,    /*!< USART Tx Complete Callback ID             */
00186   HAL_USART_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< USART Rx Half Complete Callback ID        */
00187   HAL_USART_RX_COMPLETE_CB_ID             = 0x03U,    /*!< USART Rx Complete Callback ID             */
00188   HAL_USART_TX_RX_COMPLETE_CB_ID          = 0x04U,    /*!< USART Tx Rx Complete Callback ID          */
00189   HAL_USART_ERROR_CB_ID                   = 0x05U,    /*!< USART Error Callback ID                   */
00190   HAL_USART_ABORT_COMPLETE_CB_ID          = 0x06U,    /*!< USART Abort Complete Callback ID          */
00191   HAL_USART_RX_FIFO_FULL_CB_ID            = 0x07U,    /*!< USART Rx Fifo Full Callback ID            */
00192   HAL_USART_TX_FIFO_EMPTY_CB_ID           = 0x08U,    /*!< USART Tx Fifo Empty Callback ID           */
00193
00194   HAL_USART_MSPINIT_CB_ID                 = 0x09U,    /*!< USART MspInit callback ID                 */
00195   HAL_USART_MSPDEINIT_CB_ID               = 0x0AU     /*!< USART MspDeInit callback ID               */
00196
00197 } HAL_USART_CallbackIDTypeDef;
00198
00199 /**
00200   * @brief  HAL USART Callback pointer definition
00201   */
00202 typedef  void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart);  /*!< pointer to an USART callback function */
00203
00204 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
00205
00206 /**
00207   * @}
00208   */
00209
00210 /* Exported constants --------------------------------------------------------*/
00211 /** @defgroup USART_Exported_Constants USART Exported Constants
00212   * @{
00213   */
00214
00215 /** @defgroup USART_Error_Definition   USART Error Definition
00216   * @{
00217   */
00218 #define HAL_USART_ERROR_NONE             ((uint32_t)0x00000000U)    /*!< No error                  */
00219 #define HAL_USART_ERROR_PE               ((uint32_t)0x00000001U)    /*!< Parity error              */
00220 #define HAL_USART_ERROR_NE               ((uint32_t)0x00000002U)    /*!< Noise error               */
00221 #define HAL_USART_ERROR_FE               ((uint32_t)0x00000004U)    /*!< frame error               */
00222 #define HAL_USART_ERROR_ORE              ((uint32_t)0x00000008U)    /*!< Overrun error             */
00223 #define HAL_USART_ERROR_DMA              ((uint32_t)0x00000010U)    /*!< DMA transfer error        */
00224 #define HAL_USART_ERROR_UDR              ((uint32_t)0x00000020U)    /*!< SPI slave underrun error  */
00225 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
00226 #define HAL_USART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U)    /*!< Invalid Callback error    */
00227 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
00228 /**
00229   * @}
00230   */
00231
00232 /** @defgroup USART_Stop_Bits  USART Number of Stop Bits
00233   * @{
00234   */
00235 #define USART_STOPBITS_0_5                   USART_CR2_STOP_0                     /*!< USART frame with 0.5 stop bit  */
00236 #define USART_STOPBITS_1                     0x00000000U                          /*!< USART frame with 1 stop bit    */
00237 #define USART_STOPBITS_1_5                  (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< USART frame with 1.5 stop bits */
00238 #define USART_STOPBITS_2                     USART_CR2_STOP_1                     /*!< USART frame with 2 stop bits   */
00239 /**
00240   * @}
00241   */
00242
00243 /** @defgroup USART_Parity    USART Parity
00244   * @{
00245   */
00246 #define USART_PARITY_NONE                   0x00000000U                      /*!< No parity   */
00247 #define USART_PARITY_EVEN                   USART_CR1_PCE                    /*!< Even parity */
00248 #define USART_PARITY_ODD                    (USART_CR1_PCE | USART_CR1_PS)   /*!< Odd parity  */
00249 /**
00250   * @}
00251   */
00252
00253 /** @defgroup USART_Mode   USART Mode
00254   * @{
00255   */
00256 #define USART_MODE_RX                       USART_CR1_RE                    /*!< RX mode        */
00257 #define USART_MODE_TX                       USART_CR1_TE                    /*!< TX mode        */
00258 #define USART_MODE_TX_RX                    (USART_CR1_TE |USART_CR1_RE)    /*!< RX and TX mode */
00259 /**
00260   * @}
00261   */
00262
00263 /** @defgroup USART_Over_Sampling USART Over Sampling
00264   * @{
00265   */
00266 #define USART_OVERSAMPLING_16               0x00000000U         /*!< Oversampling by 16 */
00267 #define USART_OVERSAMPLING_8                USART_CR1_OVER8     /*!< Oversampling by 8  */
00268 /**
00269   * @}
00270   */
00271
00272 /** @defgroup USART_Clock  USART Clock
00273   * @{
00274   */
00275 #define USART_CLOCK_DISABLE                 0x00000000U       /*!< USART clock disable */
00276 #define USART_CLOCK_ENABLE                  USART_CR2_CLKEN   /*!< USART clock enable  */
00277 /**
00278   * @}
00279   */
00280
00281 /** @defgroup USART_Clock_Polarity  USART Clock Polarity
00282   * @{
00283   */
00284 #define USART_POLARITY_LOW                  0x00000000U      /*!< Driver enable signal is active high */
00285 #define USART_POLARITY_HIGH                 USART_CR2_CPOL   /*!< Driver enable signal is active low  */
00286 /**
00287   * @}
00288   */
00289
00290 /** @defgroup USART_Clock_Phase   USART Clock Phase
00291   * @{
00292   */
00293 #define USART_PHASE_1EDGE                   0x00000000U      /*!< USART frame phase on first clock transition  */
00294 #define USART_PHASE_2EDGE                   USART_CR2_CPHA   /*!< USART frame phase on second clock transition */
00295 /**
00296   * @}
00297   */
00298
00299 /** @defgroup USART_Last_Bit  USART Last Bit
00300   * @{
00301   */
00302 #define USART_LASTBIT_DISABLE               0x00000000U      /*!< USART frame last data bit clock pulse not output to SCLK pin */
00303 #define USART_LASTBIT_ENABLE                USART_CR2_LBCL   /*!< USART frame last data bit clock pulse output to SCLK pin     */
00304 /**
00305   * @}
00306   */
00307
00308 /** @defgroup USART_ClockPrescaler  USART Clock Prescaler
00309   * @{
00310   */
00311 #define USART_PRESCALER_DIV1    0x00000000U  /*!< fclk_pres = fclk     */
00312 #define USART_PRESCALER_DIV2    0x00000001U  /*!< fclk_pres = fclk/2   */
00313 #define USART_PRESCALER_DIV4    0x00000002U  /*!< fclk_pres = fclk/4   */
00314 #define USART_PRESCALER_DIV6    0x00000003U  /*!< fclk_pres = fclk/6   */
00315 #define USART_PRESCALER_DIV8    0x00000004U  /*!< fclk_pres = fclk/8   */
00316 #define USART_PRESCALER_DIV10   0x00000005U  /*!< fclk_pres = fclk/10  */
00317 #define USART_PRESCALER_DIV12   0x00000006U  /*!< fclk_pres = fclk/12  */
00318 #define USART_PRESCALER_DIV16   0x00000007U  /*!< fclk_pres = fclk/16  */
00319 #define USART_PRESCALER_DIV32   0x00000008U  /*!< fclk_pres = fclk/32  */
00320 #define USART_PRESCALER_DIV64   0x00000009U  /*!< fclk_pres = fclk/64  */
00321 #define USART_PRESCALER_DIV128  0x0000000AU  /*!< fclk_pres = fclk/128 */
00322 #define USART_PRESCALER_DIV256  0x0000000BU  /*!< fclk_pres = fclk/256 */
00323
00324 /**
00325   * @}
00326   */
00327
00328 /** @defgroup USART_Request_Parameters  USART Request Parameters
00329   * @{
00330   */
00331 #define USART_RXDATA_FLUSH_REQUEST        USART_RQR_RXFRQ        /*!< Receive Data flush Request  */
00332 #define USART_TXDATA_FLUSH_REQUEST        USART_RQR_TXFRQ        /*!< Transmit data flush Request */
00333 /**
00334   * @}
00335   */
00336
00337 /** @defgroup USART_Flags      USART Flags
00338   *        Elements values convention: 0xXXXX
00339   *           - 0xXXXX  : Flag mask in the ISR register
00340   * @{
00341   */
00342 #define USART_FLAG_TXFT                     USART_ISR_TXFT          /*!< USART TXFIFO threshold flag                */
00343 #define USART_FLAG_RXFT                     USART_ISR_RXFT          /*!< USART RXFIFO threshold flag                */
00344 #define USART_FLAG_RXFF                     USART_ISR_RXFF          /*!< USART RXFIFO Full flag                     */
00345 #define USART_FLAG_TXFE                     USART_ISR_TXFE          /*!< USART TXFIFO Empty flag                    */
00346 #define USART_FLAG_REACK                    USART_ISR_REACK         /*!< USART receive enable acknowledge flag      */
00347 #define USART_FLAG_TEACK                    USART_ISR_TEACK         /*!< USART transmit enable acknowledge flag     */
00348 #define USART_FLAG_BUSY                     USART_ISR_BUSY          /*!< USART busy flag                            */
00349 #define USART_FLAG_UDR                      USART_ISR_UDR           /*!< SPI slave underrun error flag              */
00350 #define USART_FLAG_TXE                      USART_ISR_TXE_TXFNF     /*!< USART transmit data register empty         */
00351 #define USART_FLAG_TXFNF                    USART_ISR_TXE_TXFNF     /*!< USART TXFIFO not full                      */
00352 #define USART_FLAG_TC                       USART_ISR_TC            /*!< USART transmission complete                */
00353 #define USART_FLAG_RXNE                     USART_ISR_RXNE_RXFNE    /*!< USART read data register not empty         */
00354 #define USART_FLAG_RXFNE                    USART_ISR_RXNE_RXFNE    /*!< USART RXFIFO not empty                     */
00355 #define USART_FLAG_IDLE                     USART_ISR_IDLE          /*!< USART idle flag                            */
00356 #define USART_FLAG_ORE                      USART_ISR_ORE           /*!< USART overrun error                        */
00357 #define USART_FLAG_NE                       USART_ISR_NE            /*!< USART noise error                          */
00358 #define USART_FLAG_FE                       USART_ISR_FE            /*!< USART frame error                          */
00359 #define USART_FLAG_PE                       USART_ISR_PE            /*!< USART parity error                         */
00360 /**
00361   * @}
00362   */
00363
00364 /** @defgroup USART_Interrupt_definition USART Interrupts Definition
00365   *        Elements values convention: 0000ZZZZ0XXYYYYYb
00366   *           - YYYYY  : Interrupt source position in the XX register (5bits)
00367   *           - XX  : Interrupt source register (2bits)
00368   *                 - 01: CR1 register
00369   *                 - 10: CR2 register
00370   *                 - 11: CR3 register
00371   *           - ZZZZ  : Flag position in the ISR register(4bits)
00372   * @{
00373   */
00374
00375 #define USART_IT_PE                          0x0028U     /*!< USART parity error interruption                 */
00376 #define USART_IT_TXE                         0x0727U     /*!< USART transmit data register empty interruption */
00377 #define USART_IT_TXFNF                       0x0727U     /*!< USART TX FIFO not full interruption             */
00378 #define USART_IT_TC                          0x0626U     /*!< USART transmission complete interruption        */
00379 #define USART_IT_RXNE                        0x0525U     /*!< USART read data register not empty interruption */
00380 #define USART_IT_RXFNE                       0x0525U     /*!< USART RXFIFO not empty interruption             */
00381 #define USART_IT_IDLE                        0x0424U     /*!< USART idle interruption                         */
00382 #define USART_IT_ERR                         0x0060U     /*!< USART error interruption                        */
00383 #define USART_IT_ORE                         0x0300U     /*!< USART overrun error interruption                */
00384 #define USART_IT_NE                          0x0200U     /*!< USART noise error interruption                  */
00385 #define USART_IT_FE                          0x0100U     /*!< USART frame error interruption                  */
00386 #define USART_IT_RXFF                        0x183FU     /*!< USART RXFIFO full interruption                  */
00387 #define USART_IT_TXFE                        0x173EU     /*!< USART TXFIFO empty interruption                 */
00388 #define USART_IT_RXFT                        0x1A7CU     /*!< USART RXFIFO threshold reached interruption     */
00389 #define USART_IT_TXFT                        0x1B77U     /*!< USART TXFIFO threshold reached interruption     */
00390
00391 /**
00392   * @}
00393   */
00394
00395 /** @defgroup USART_IT_CLEAR_Flags    USART Interruption Clear Flags
00396   * @{
00397   */
00398 #define USART_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag             */
00399 #define USART_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag            */
00400 #define USART_CLEAR_NEF                       USART_ICR_NECF            /*!< Noise Error detected Clear Flag     */
00401 #define USART_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag            */
00402 #define USART_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag       */
00403 #define USART_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag    */
00404 #define USART_CLEAR_UDRF                      USART_ICR_UDRCF           /*!< SPI slave underrun error Clear Flag */
00405 #define USART_CLEAR_TXFECF                    USART_ICR_TXFECF          /*!< TXFIFO Empty Clear Flag             */
00406 /**
00407   * @}
00408   */
00409
00410 /** @defgroup USART_Interruption_Mask    USART Interruption Flags Mask
00411   * @{
00412   */
00413 #define USART_IT_MASK                             0x001FU     /*!< USART interruptions flags mask */
00414 #define USART_CR_MASK                             0x00E0U     /*!< USART control register mask */
00415 #define USART_CR_POS                              5U          /*!< USART control register position */
00416 /**
00417   * @}
00418   */
00419
00420 /**
00421   * @}
00422   */
00423
00424 /* Exported macros -----------------------------------------------------------*/
00425 /** @defgroup USART_Exported_Macros USART Exported Macros
00426   * @{
00427   */
00428
00429 /** @brief Reset USART handle state.
00430   * @param  __HANDLE__ USART handle.
00431   * @retval None
00432   */
00433 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
00434 #define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)  do{                                            \
00435                                                       (__HANDLE__)->State = HAL_USART_STATE_RESET; \
00436                                                       (__HANDLE__)->MspInitCallback = NULL;        \
00437                                                       (__HANDLE__)->MspDeInitCallback = NULL;      \
00438                                                     } while(0U)
00439 #else
00440 #define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)  ((__HANDLE__)->State = HAL_USART_STATE_RESET)
00441 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
00442
00443 /** @brief  Check whether the specified USART flag is set or not.
00444   * @param  __HANDLE__ specifies the USART Handle
00445   * @param  __FLAG__ specifies the flag to check.
00446   *        This parameter can be one of the following values:
00447   *            @arg @ref USART_FLAG_TXFT  TXFIFO threshold flag
00448   *            @arg @ref USART_FLAG_RXFT  RXFIFO threshold flag
00449   *            @arg @ref USART_FLAG_RXFF  RXFIFO Full flag
00450   *            @arg @ref USART_FLAG_TXFE  TXFIFO Empty flag
00451   *            @arg @ref USART_FLAG_REACK Receive enable acknowledge flag
00452   *            @arg @ref USART_FLAG_TEACK Transmit enable acknowledge flag
00453   *            @arg @ref USART_FLAG_BUSY  Busy flag
00454   *            @arg @ref USART_FLAG_UDR   SPI slave underrun error flag
00455   *            @arg @ref USART_FLAG_TXE   Transmit data register empty flag
00456   *            @arg @ref USART_FLAG_TXFNF TXFIFO not full flag
00457   *            @arg @ref USART_FLAG_TC    Transmission Complete flag
00458   *            @arg @ref USART_FLAG_RXNE  Receive data register not empty flag
00459   *            @arg @ref USART_FLAG_RXFNE RXFIFO not empty flag
00460   *            @arg @ref USART_FLAG_IDLE  Idle Line detection flag
00461   *            @arg @ref USART_FLAG_ORE   OverRun Error flag
00462   *            @arg @ref USART_FLAG_NE    Noise Error flag
00463   *            @arg @ref USART_FLAG_FE    Framing Error flag
00464   *            @arg @ref USART_FLAG_PE    Parity Error flag
00465   * @retval The new state of __FLAG__ (TRUE or FALSE).
00466   */
00467 #define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
00468
00469 /** @brief  Clear the specified USART pending flag.
00470   * @param  __HANDLE__ specifies the USART Handle.
00471   * @param  __FLAG__ specifies the flag to check.
00472   *          This parameter can be any combination of the following values:
00473   *            @arg @ref USART_CLEAR_PEF      Parity Error Clear Flag
00474   *            @arg @ref USART_CLEAR_FEF      Framing Error Clear Flag
00475   *            @arg @ref USART_CLEAR_NEF      Noise detected Clear Flag
00476   *            @arg @ref USART_CLEAR_OREF     Overrun Error Clear Flag
00477   *            @arg @ref USART_CLEAR_IDLEF    IDLE line detected Clear Flag
00478   *            @arg @ref USART_CLEAR_TXFECF   TXFIFO empty clear Flag
00479   *            @arg @ref USART_CLEAR_TCF      Transmission Complete Clear Flag
00480   *            @arg @ref USART_CLEAR_UDRF     SPI slave underrun error Clear Flag
00481   * @retval None
00482   */
00483 #define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
00484
00485 /** @brief  Clear the USART PE pending flag.
00486   * @param  __HANDLE__ specifies the USART Handle.
00487   * @retval None
00488   */
00489 #define __HAL_USART_CLEAR_PEFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)
00490
00491 /** @brief  Clear the USART FE pending flag.
00492   * @param  __HANDLE__ specifies the USART Handle.
00493   * @retval None
00494   */
00495 #define __HAL_USART_CLEAR_FEFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)
00496
00497 /** @brief  Clear the USART NE pending flag.
00498   * @param  __HANDLE__ specifies the USART Handle.
00499   * @retval None
00500   */
00501 #define __HAL_USART_CLEAR_NEFLAG(__HANDLE__)  __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)
00502
00503 /** @brief  Clear the USART ORE pending flag.
00504   * @param  __HANDLE__ specifies the USART Handle.
00505   * @retval None
00506   */
00507 #define __HAL_USART_CLEAR_OREFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)
00508
00509 /** @brief  Clear the USART IDLE pending flag.
00510   * @param  __HANDLE__ specifies the USART Handle.
00511   * @retval None
00512   */
00513 #define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)
00514
00515 /** @brief  Clear the USART TX FIFO empty clear flag.
00516   * @param  __HANDLE__ specifies the USART Handle.
00517   * @retval None
00518   */
00519 #define __HAL_USART_CLEAR_TXFECF(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_TXFECF)
00520
00521 /** @brief  Clear SPI slave underrun error flag.
00522   * @param  __HANDLE__ specifies the USART Handle.
00523   * @retval None
00524   */
00525 #define __HAL_USART_CLEAR_UDRFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_UDRF)
00526
00527 /** @brief  Enable the specified USART interrupt.
00528   * @param  __HANDLE__ specifies the USART Handle.
00529   * @param  __INTERRUPT__ specifies the USART interrupt source to enable.
00530   *          This parameter can be one of the following values:
00531   *            @arg @ref USART_IT_RXFF  RXFIFO Full interrupt
00532   *            @arg @ref USART_IT_TXFE  TXFIFO Empty interrupt
00533   *            @arg @ref USART_IT_RXFT  RXFIFO threshold interrupt
00534   *            @arg @ref USART_IT_TXFT  TXFIFO threshold interrupt
00535   *            @arg @ref USART_IT_TXE   Transmit Data Register empty interrupt
00536   *            @arg @ref USART_IT_TXFNF TX FIFO not full interrupt
00537   *            @arg @ref USART_IT_TC    Transmission complete interrupt
00538   *            @arg @ref USART_IT_RXNE  Receive Data register not empty interrupt
00539   *            @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt
00540   *            @arg @ref USART_IT_IDLE  Idle line detection interrupt
00541   *            @arg @ref USART_IT_PE    Parity Error interrupt
00542   *            @arg @ref USART_IT_ERR   Error interrupt(Frame error, noise error, overrun error)
00543   * @retval None
00544   */
00545 #define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
00546                                                             ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
00547                                                             ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))
00548
00549 /** @brief  Disable the specified USART interrupt.
00550   * @param  __HANDLE__ specifies the USART Handle.
00551   * @param  __INTERRUPT__ specifies the USART interrupt source to disable.
00552   *          This parameter can be one of the following values:
00553   *            @arg @ref USART_IT_RXFF  RXFIFO Full interrupt
00554   *            @arg @ref USART_IT_TXFE  TXFIFO Empty interrupt
00555   *            @arg @ref USART_IT_RXFT  RXFIFO threshold interrupt
00556   *            @arg @ref USART_IT_TXFT  TXFIFO threshold interrupt
00557   *            @arg @ref USART_IT_TXE   Transmit Data Register empty interrupt
00558   *            @arg @ref USART_IT_TXFNF TX FIFO not full interrupt
00559   *            @arg @ref USART_IT_TC    Transmission complete interrupt
00560   *            @arg @ref USART_IT_RXNE  Receive Data register not empty interrupt
00561   *            @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt
00562   *            @arg @ref USART_IT_IDLE  Idle line detection interrupt
00563   *            @arg @ref USART_IT_PE    Parity Error interrupt
00564   *            @arg @ref USART_IT_ERR   Error interrupt(Frame error, noise error, overrun error)
00565   * @retval None
00566   */
00567 #define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
00568                                                             ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
00569                                                             ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))
00570
00571
00572 /** @brief  Check whether the specified USART interrupt has occurred or not.
00573   * @param  __HANDLE__ specifies the USART Handle.
00574   * @param  __INTERRUPT__ specifies the USART interrupt source to check.
00575   *          This parameter can be one of the following values:
00576   *            @arg @ref USART_IT_RXFF  RXFIFO Full interrupt
00577   *            @arg @ref USART_IT_TXFE  TXFIFO Empty interrupt
00578   *            @arg @ref USART_IT_RXFT  RXFIFO threshold interrupt
00579   *            @arg @ref USART_IT_TXFT  TXFIFO threshold interrupt
00580   *            @arg @ref USART_IT_TXE   Transmit Data Register empty interrupt
00581   *            @arg @ref USART_IT_TXFNF TX FIFO not full interrupt
00582   *            @arg @ref USART_IT_TC    Transmission complete interrupt
00583   *            @arg @ref USART_IT_RXNE  Receive Data register not empty interrupt
00584   *            @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt
00585   *            @arg @ref USART_IT_IDLE  Idle line detection interrupt
00586   *            @arg @ref USART_IT_ORE   OverRun Error interrupt
00587   *            @arg @ref USART_IT_NE    Noise Error interrupt
00588   *            @arg @ref USART_IT_FE    Framing Error interrupt
00589   *            @arg @ref USART_IT_PE    Parity Error interrupt
00590   * @retval The new state of __INTERRUPT__ (SET or RESET).
00591   */
00592 #define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__INTERRUPT__)>> 0x08))) != RESET) ? SET : RESET)
00593
00594 /** @brief  Check whether the specified USART interrupt source is enabled or not.
00595   * @param  __HANDLE__ specifies the USART Handle.
00596   * @param  __INTERRUPT__ specifies the USART interrupt source to check.
00597   *          This parameter can be one of the following values:
00598   *            @arg @ref USART_IT_RXFF  RXFIFO Full interrupt
00599   *            @arg @ref USART_IT_TXFE  TXFIFO Empty interrupt
00600   *            @arg @ref USART_IT_RXFT  RXFIFO threshold interrupt
00601   *            @arg @ref USART_IT_TXFT  TXFIFO threshold interrupt
00602   *            @arg @ref USART_IT_TXE   Transmit Data Register empty interrupt
00603   *            @arg @ref USART_IT_TXFNF TX FIFO not full interrupt
00604   *            @arg @ref USART_IT_TC    Transmission complete interrupt
00605   *            @arg @ref USART_IT_RXNE  Receive Data register not empty interrupt
00606   *            @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt
00607   *            @arg @ref USART_IT_IDLE  Idle line detection interrupt
00608   *            @arg @ref USART_IT_ORE   OverRun Error interrupt
00609   *            @arg @ref USART_IT_NE    Noise Error interrupt
00610   *            @arg @ref USART_IT_FE    Framing Error interrupt
00611   *            @arg @ref USART_IT_PE    Parity Error interrupt
00612   * @retval The new state of __INTERRUPT__ (SET or RESET).
00613   */
00614 #define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ? (__HANDLE__)->Instance->CR1 : \
00615                                                                 (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \
00616                                                                 (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK)))  != RESET) ? SET : RESET)
00617
00618
00619 /** @brief  Clear the specified USART ISR flag, in setting the proper ICR register flag.
00620   * @param  __HANDLE__ specifies the USART Handle.
00621   * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
00622   *                       to clear the corresponding interrupt.
00623   *          This parameter can be one of the following values:
00624   *            @arg @ref USART_CLEAR_PEF      Parity Error Clear Flag
00625   *            @arg @ref USART_CLEAR_FEF      Framing Error Clear Flag
00626   *            @arg @ref USART_CLEAR_NEF      Noise detected Clear Flag
00627   *            @arg @ref USART_CLEAR_OREF     Overrun Error Clear Flag
00628   *            @arg @ref USART_CLEAR_IDLEF    IDLE line detected Clear Flag
00629   *            @arg @ref USART_CLEAR_TXFECF   TXFIFO empty clear Flag
00630   *            @arg @ref USART_CLEAR_TCF      Transmission Complete Clear Flag
00631   * @retval None
00632   */
00633 #define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
00634
00635 /** @brief  Set a specific USART request flag.
00636   * @param  __HANDLE__ specifies the USART Handle.
00637   * @param  __REQ__ specifies the request flag to set.
00638   *          This parameter can be one of the following values:
00639   *            @arg @ref USART_RXDATA_FLUSH_REQUEST Receive Data flush Request
00640   *            @arg @ref USART_TXDATA_FLUSH_REQUEST Transmit data flush Request
00641   *
00642   * @retval None
00643   */
00644 #define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__)      ((__HANDLE__)->Instance->RQR |= (__REQ__))
00645
00646 /** @brief  Enable the USART one bit sample method.
00647   * @param  __HANDLE__ specifies the USART Handle.
00648   * @retval None
00649   */
00650 #define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
00651
00652 /** @brief  Disable the USART one bit sample method.
00653   * @param  __HANDLE__ specifies the USART Handle.
00654   * @retval None
00655   */
00656 #define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
00657
00658 /** @brief  Enable USART.
00659   * @param  __HANDLE__ specifies the USART Handle.
00660   * @retval None
00661   */
00662 #define __HAL_USART_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
00663
00664 /** @brief  Disable USART.
00665   * @param  __HANDLE__ specifies the USART Handle.
00666   * @retval None
00667   */
00668 #define __HAL_USART_DISABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
00669
00670 /**
00671   * @}
00672   */
00673
00674 /* Private macros --------------------------------------------------------*/
00675 /** @defgroup USART_Private_Macros   USART Private Macros
00676   * @{
00677   */
00678
00679 /** @brief  Get USART clock division factor from clock prescaler value.
00680   * @param  __CLOCKPRESCALER__ USART prescaler value.
00681   * @retval USART clock division factor
00682   */
00683 #define USART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \
00684   (((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1)   ? 1U :       \
00685    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2)   ? 2U :       \
00686    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4)   ? 4U :       \
00687    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6)   ? 6U :       \
00688    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8)   ? 8U :       \
00689    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10)  ? 10U :      \
00690    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12)  ? 12U :      \
00691    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16)  ? 16U :      \
00692    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32)  ? 32U :      \
00693    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64)  ? 64U :      \
00694    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U :     \
00695    ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256) ? 256U : 1U)
00696
00697 /** @brief  BRR division operation to set BRR register in 8-bit oversampling mode.
00698   * @param  __PCLK__ USART clock.
00699   * @param  __BAUD__ Baud rate set by the user.
00700   * @param  __CLOCKPRESCALER__ UART prescaler value.
00701   * @retval Division result
00702   */
00703 #define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)   (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U) + ((__BAUD__)/2U)) / (__BAUD__))
00704
00705 /** @brief  Report the USART clock source.
00706   * @param  __HANDLE__ specifies the USART Handle.
00707   * @param  __CLOCKSOURCE__ output variable.
00708   * @retval the USART clocking source, written in __CLOCKSOURCE__.
00709   */
00710 #define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
00711   do {                                                         \
00712     if((__HANDLE__)->Instance == USART1)                       \
00713     {                                                          \
00714        switch(__HAL_RCC_GET_USART1_SOURCE())                   \
00715        {                                                       \
00716         case RCC_USART1CLKSOURCE_PCLK2:                        \
00717           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2;         \
00718           break;                                               \
00719         case RCC_USART1CLKSOURCE_HSI:                          \
00720           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
00721           break;                                               \
00722         case RCC_USART1CLKSOURCE_SYSCLK:                       \
00723           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
00724           break;                                               \
00725         case RCC_USART1CLKSOURCE_LSE:                          \
00726           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
00727           break;                                               \
00728         default:                                               \
00729           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
00730           break;                                               \
00731        }                                                       \
00732     }                                                       \
00733     else                                                       \
00734     {                                                          \
00735       (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;         \
00736     }                                                          \
00737   } while(0U)
00738
00739 /** @brief  Check USART Baud rate.
00740   * @param  __BAUDRATE__ Baudrate specified by the user.
00741   *         The maximum Baud Rate is derived from the maximum clock on WB (i.e. 64 MHz)
00742   *         divided by the smallest oversampling used on the USART (i.e. 8)
00743   * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)  */
00744 #define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 8000000U)
00745
00746 /**
00747   * @brief Ensure that USART frame number of stop bits is valid.
00748   * @param __STOPBITS__ USART frame number of stop bits.
00749   * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
00750   */
00751 #define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_0_5) || \
00752                                          ((__STOPBITS__) == USART_STOPBITS_1)   || \
00753                                          ((__STOPBITS__) == USART_STOPBITS_1_5) || \
00754                                          ((__STOPBITS__) == USART_STOPBITS_2))
00755
00756 /**
00757   * @brief Ensure that USART frame parity is valid.
00758   * @param __PARITY__ USART frame parity.
00759   * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
00760   */
00761 #define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \
00762                                      ((__PARITY__) == USART_PARITY_EVEN) || \
00763                                      ((__PARITY__) == USART_PARITY_ODD))
00764
00765 /**
00766   * @brief Ensure that USART communication mode is valid.
00767   * @param __MODE__ USART communication mode.
00768   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
00769   */
00770 #define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
00771
00772 /**
00773   * @brief Ensure that USART oversampling is valid.
00774   * @param __SAMPLING__ USART oversampling.
00775   * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
00776   */
00777 #define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
00778                                              ((__SAMPLING__) == USART_OVERSAMPLING_8))
00779
00780 /**
00781   * @brief Ensure that USART clock state is valid.
00782   * @param __CLOCK__ USART clock state.
00783   * @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)
00784   */
00785 #define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \
00786                                    ((__CLOCK__) == USART_CLOCK_ENABLE))
00787
00788 /**
00789   * @brief Ensure that USART frame polarity is valid.
00790   * @param __CPOL__ USART frame polarity.
00791   * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
00792   */
00793 #define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
00794
00795 /**
00796   * @brief Ensure that USART frame phase is valid.
00797   * @param __CPHA__ USART frame phase.
00798   * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
00799   */
00800 #define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
00801
00802 /**
00803   * @brief Ensure that USART frame last bit clock pulse setting is valid.
00804   * @param __LASTBIT__ USART frame last bit clock pulse setting.
00805   * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
00806   */
00807 #define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \
00808                                        ((__LASTBIT__) == USART_LASTBIT_ENABLE))
00809
00810 /**
00811   * @brief Ensure that USART request parameter is valid.
00812   * @param __PARAM__ USART request parameter.
00813   * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
00814   */
00815 #define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \
00816                                                ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))
00817
00818 /**
00819   * @brief Ensure that USART Prescaler is valid.
00820   * @param __CLOCKPRESCALER__ USART Prescaler value.
00821   * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
00822   */
00823 #define IS_USART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1) || \
00824                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2) || \
00825                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4) || \
00826                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6) || \
00827                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8) || \
00828                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10) || \
00829                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12) || \
00830                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) || \
00831                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) || \
00832                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) || \
00833                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) || \
00834                                                 ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256))
00835
00836 /**
00837   * @}
00838   */
00839
00840 /* Include USART HAL Extended module */
00841 #include "stm32wbxx_hal_usart_ex.h"
00842
00843 /* Exported functions --------------------------------------------------------*/
00844 /** @addtogroup USART_Exported_Functions USART Exported Functions
00845   * @{
00846   */
00847
00848 /** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
00849   * @{
00850   */
00851
00852 /* Initialization and de-initialization functions  ****************************/
00853 HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
00854 HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
00855 void HAL_USART_MspInit(USART_HandleTypeDef *husart);
00856 void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
00857
00858 /* Callbacks Register/UnRegister functions  ***********************************/
00859 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
00860 HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback);
00861 HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID);
00862 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
00863
00864 /**
00865   * @}
00866   */
00867
00868 /** @addtogroup USART_Exported_Functions_Group2 IO operation functions
00869   * @{
00870   */
00871
00872 /* IO operation functions *****************************************************/
00873 HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
00874 HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
00875 HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
00876 HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
00877 HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
00878 HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,  uint16_t Size);
00879 HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
00880 HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
00881 HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
00882 HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
00883 HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
00884 HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
00885 /* Transfer Abort functions */
00886 HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart);
00887 HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart);
00888
00889 void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
00890 void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
00891 void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
00892 void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
00893 void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
00894 void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
00895 void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
00896 void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart);
00897
00898 /**
00899   * @}
00900   */
00901
00902 /** @addtogroup USART_Exported_Functions_Group4 Peripheral State and Error functions
00903   * @{
00904   */
00905
00906 /* Peripheral State and Error functions ***************************************/
00907 HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
00908 uint32_t               HAL_USART_GetError(USART_HandleTypeDef *husart);
00909
00910 /**
00911   * @}
00912   */
00913
00914 /**
00915   * @}
00916   */
00917
00918 /**
00919   * @}
00920   */
00921
00922 /**
00923   * @}
00924   */
00925
00926 #ifdef __cplusplus
00927 }
00928 #endif
00929
00930 #endif /* STM32WBxx_HAL_USART_H */
00931
00932 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_usart_ex.c Source File

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stm32wbxx_hal_usart_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_usart_ex.c
00004   * @author  MCD Application Team
00005   * @brief   Extended USART HAL module driver.
00006   *          This file provides firmware functions to manage the following extended
00007   *          functionalities of the Universal Synchronous Receiver Transmitter Peripheral (USART).
00008   *           + Peripheral Control functions
00009   *
00010   *
00011   @verbatim
00012   ==============================================================================
00013                ##### USART peripheral extended features  #####
00014   ==============================================================================
00015
00016     (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
00017
00018         -@- When USART operates in FIFO mode, FIFO mode must be enabled prior
00019             starting RX/TX transfers. Also RX/TX FIFO thresholds must be
00020             configured prior starting RX/TX transfers.
00021
00022     (#) Slave mode enabling/disabling and NSS pin configuration.
00023
00024         -@- When USART operates in Slave mode, Slave mode must be enabled prior
00025             starting RX/TX transfers.
00026
00027   @endverbatim
00028   ******************************************************************************
00029   * @attention
00030   *
00031   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00032   * All rights reserved.</center></h2>
00033   *
00034   * This software component is licensed by ST under BSD 3-Clause license,
00035   * the "License"; You may not use this file except in compliance with the
00036   * License. You may obtain a copy of the License at:
00037   *                        opensource.org/licenses/BSD-3-Clause
00038   *
00039   ******************************************************************************
00040   */
00041
00042 /* Includes ------------------------------------------------------------------*/
00043 #include "stm32wbxx_hal.h"
00044
00045 /** @addtogroup STM32WBxx_HAL_Driver
00046   * @{
00047   */
00048
00049 /** @defgroup USARTEx USARTEx
00050   * @brief USART Extended HAL module driver
00051   * @{
00052   */
00053
00054 #ifdef HAL_USART_MODULE_ENABLED
00055
00056 /* Private typedef -----------------------------------------------------------*/
00057 /* UART RX FIFO depth */
00058 #define RX_FIFO_DEPTH 8U
00059
00060 /* UART TX FIFO depth */
00061 #define TX_FIFO_DEPTH 8U
00062
00063 /* Private define ------------------------------------------------------------*/
00064 /* Private macros ------------------------------------------------------------*/
00065 /* Private variables ---------------------------------------------------------*/
00066 /* Private function prototypes -----------------------------------------------*/
00067 /** @defgroup USARTEx_Private_Functions USARTEx Private Functions
00068   * @{
00069   */
00070 static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart);
00071 /**
00072   * @}
00073   */
00074
00075 /* Exported functions --------------------------------------------------------*/
00076
00077 /** @defgroup USARTEx_Exported_Functions  USARTEx Exported Functions
00078   * @{
00079   */
00080
00081 /** @defgroup USARTEx_Exported_Functions_Group1 IO operation functions
00082   * @brief Extended USART Transmit/Receive functions
00083   *
00084 @verbatim
00085  ===============================================================================
00086                       ##### IO operation functions #####
00087  ===============================================================================
00088     This subsection provides a set of FIFO mode related callback functions.
00089
00090     (#) TX/RX Fifos Callbacks:
00091         (+) HAL_USARTEx_RxFifoFullCallback()
00092         (+) HAL_USARTEx_TxFifoEmptyCallback()
00093
00094 @endverbatim
00095   * @{
00096   */
00097
00098 /**
00099   * @brief  USART RX Fifo full callback.
00100   * @param  husart USART handle.
00101   * @retval None
00102   */
00103 __weak void HAL_USARTEx_RxFifoFullCallback(USART_HandleTypeDef *husart)
00104 {
00105   /* Prevent unused argument(s) compilation warning */
00106   UNUSED(husart);
00107
00108   /* NOTE : This function should not be modified, when the callback is needed,
00109             the HAL_USARTEx_RxFifoFullCallback can be implemented in the user file.
00110    */
00111 }
00112
00113 /**
00114   * @brief  USART TX Fifo empty callback.
00115   * @param  husart USART handle.
00116   * @retval None
00117   */
00118 __weak void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart)
00119 {
00120   /* Prevent unused argument(s) compilation warning */
00121   UNUSED(husart);
00122
00123   /* NOTE : This function should not be modified, when the callback is needed,
00124             the HAL_USARTEx_TxFifoEmptyCallback can be implemented in the user file.
00125    */
00126 }
00127
00128 /**
00129   * @}
00130   */
00131
00132 /** @defgroup USARTEx_Exported_Functions_Group2 Peripheral Control functions
00133   * @brief    Extended Peripheral Control functions
00134   *
00135 @verbatim
00136  ===============================================================================
00137                       ##### Peripheral Control functions #####
00138  ===============================================================================
00139     [..] This section provides the following functions:
00140      (+) HAL_USARTEx_EnableSPISlaveMode() API enables the SPI slave mode
00141      (+) HAL_USARTEx_DisableSPISlaveMode() API disables the SPI slave mode
00142      (+) HAL_USARTEx_ConfigNSS API configures the Slave Select input pin (NSS)
00143      (+) HAL_USARTEx_EnableFifoMode() API enables the FIFO mode
00144      (+) HAL_USARTEx_DisableFifoMode() API disables the FIFO mode
00145      (+) HAL_USARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
00146      (+) HAL_USARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold
00147
00148
00149 @endverbatim
00150   * @{
00151   */
00152
00153 /**
00154   * @brief  Enable the SPI slave mode.
00155   * @note When the USART operates in SPI slave mode, it handles data flow using
00156   *       the serial interface clock derived from the external SCLK signal
00157   *       provided by the external master SPI device.
00158   * @note In SPI slave mode, the USART must be enabled before starting the master
00159   *       communications (or between frames while the clock is stable). Otherwise,
00160   *       if the USART slave is enabled while the master is in the middle of a
00161   *       frame, it will become desynchronized with the master.
00162   * @note The data register of the slave needs to be ready before the first edge
00163   *       of the communication clock or before the end of the ongoing communication,
00164   *       otherwise the SPI slave will transmit zeros.
00165   * @param husart      USART handle.
00166   * @retval HAL status
00167   */
00168 HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart)
00169 {
00170   uint32_t tmpcr1;
00171
00172   /* Check parameters */
00173   assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance));
00174
00175   /* Process Locked */
00176   __HAL_LOCK(husart);
00177
00178   husart->State = HAL_USART_STATE_BUSY;
00179
00180   /* Save actual USART configuration */
00181   tmpcr1 = READ_REG(husart->Instance->CR1);
00182
00183   /* Disable USART */
00184   __HAL_USART_DISABLE(husart);
00185
00186   /* In SPI slave mode mode, the following bits must be kept cleared:
00187   - LINEN and CLKEN bit in the USART_CR2 register
00188   - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/
00189   CLEAR_BIT(husart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
00190   CLEAR_BIT(husart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
00191
00192   /* Enable SPI slave mode */
00193   SET_BIT(husart->Instance->CR2, USART_CR2_SLVEN);
00194
00195   /* Restore USART configuration */
00196   WRITE_REG(husart->Instance->CR1, tmpcr1);
00197
00198   husart->SlaveMode = USART_SLAVEMODE_ENABLE;
00199
00200   husart->State = HAL_USART_STATE_READY;
00201
00202   /* Enable USART */
00203   __HAL_USART_ENABLE(husart);
00204
00205   /* Process Unlocked */
00206   __HAL_UNLOCK(husart);
00207
00208   return HAL_OK;
00209 }
00210
00211 /**
00212   * @brief  Disable the SPI slave mode.
00213   * @param husart      USART handle.
00214   * @retval HAL status
00215   */
00216 HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart)
00217 {
00218   uint32_t tmpcr1;
00219
00220   /* Check parameters */
00221   assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance));
00222
00223   /* Process Locked */
00224   __HAL_LOCK(husart);
00225
00226   husart->State = HAL_USART_STATE_BUSY;
00227
00228   /* Save actual USART configuration */
00229   tmpcr1 = READ_REG(husart->Instance->CR1);
00230
00231   /* Disable USART */
00232   __HAL_USART_DISABLE(husart);
00233
00234   /* Disable SPI slave mode */
00235   CLEAR_BIT(husart->Instance->CR2, USART_CR2_SLVEN);
00236
00237   /* Restore USART configuration */
00238   WRITE_REG(husart->Instance->CR1, tmpcr1);
00239
00240   husart->SlaveMode = USART_SLAVEMODE_ENABLE;
00241
00242   husart->State = HAL_USART_STATE_READY;
00243
00244   /* Process Unlocked */
00245   __HAL_UNLOCK(husart);
00246
00247   return HAL_OK;
00248 }
00249
00250 /**
00251   * @brief  Configure the Slave Select input pin (NSS).
00252   * @note Software NSS management: SPI slave will always be selected and NSS
00253   *       input pin will be ignored.
00254   * @note Hardware NSS management: the SPI slave selection depends on NSS
00255   *       input pin. The slave is selected when NSS is low and deselected when
00256   *       NSS is high.
00257   * @param husart      USART handle.
00258   * @param NSSConfig   NSS configuration.
00259   *          This parameter can be one of the following values:
00260   *            @arg @ref USART_NSS_HARD
00261   *            @arg @ref USART_NSS_SOFT
00262   * @retval HAL status
00263   */
00264 HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig)
00265 {
00266   uint32_t tmpcr1;
00267
00268   /* Check parameters */
00269   assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance));
00270   assert_param(IS_USART_NSS(NSSConfig));
00271
00272   /* Process Locked */
00273   __HAL_LOCK(husart);
00274
00275   husart->State = HAL_USART_STATE_BUSY;
00276
00277   /* Save actual USART configuration */
00278   tmpcr1 = READ_REG(husart->Instance->CR1);
00279
00280   /* Disable USART */
00281   __HAL_USART_DISABLE(husart);
00282
00283   /* Program DIS_NSS bit in the USART_CR2 register */
00284   MODIFY_REG(husart->Instance->CR2, USART_CR2_DIS_NSS, NSSConfig);
00285
00286   /* Restore USART configuration */
00287   WRITE_REG(husart->Instance->CR1, tmpcr1);
00288
00289   husart->State = HAL_USART_STATE_READY;
00290
00291   /* Process Unlocked */
00292   __HAL_UNLOCK(husart);
00293
00294   return HAL_OK;
00295 }
00296
00297 /**
00298   * @brief  Enable the FIFO mode.
00299   * @param husart      USART handle.
00300   * @retval HAL status
00301   */
00302 HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart)
00303 {
00304   uint32_t tmpcr1;
00305
00306   /* Check parameters */
00307   assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
00308
00309   /* Process Locked */
00310   __HAL_LOCK(husart);
00311
00312   husart->State = HAL_USART_STATE_BUSY;
00313
00314   /* Save actual USART configuration */
00315   tmpcr1 = READ_REG(husart->Instance->CR1);
00316
00317   /* Disable USART */
00318   __HAL_USART_DISABLE(husart);
00319
00320   /* Enable FIFO mode */
00321   SET_BIT(tmpcr1, USART_CR1_FIFOEN);
00322   husart->FifoMode = USART_FIFOMODE_ENABLE;
00323
00324   /* Restore USART configuration */
00325   WRITE_REG(husart->Instance->CR1, tmpcr1);
00326
00327   /* Determine the number of data to process during RX/TX ISR execution */
00328   USARTEx_SetNbDataToProcess(husart);
00329
00330   husart->State = HAL_USART_STATE_READY;
00331
00332   /* Process Unlocked */
00333   __HAL_UNLOCK(husart);
00334
00335   return HAL_OK;
00336 }
00337
00338 /**
00339   * @brief  Disable the FIFO mode.
00340   * @param husart      USART handle.
00341   * @retval HAL status
00342   */
00343 HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart)
00344 {
00345   uint32_t tmpcr1;
00346
00347   /* Check parameters */
00348   assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
00349
00350   /* Process Locked */
00351   __HAL_LOCK(husart);
00352
00353   husart->State = HAL_USART_STATE_BUSY;
00354
00355   /* Save actual USART configuration */
00356   tmpcr1 = READ_REG(husart->Instance->CR1);
00357
00358   /* Disable USART */
00359   __HAL_USART_DISABLE(husart);
00360
00361   /* Enable FIFO mode */
00362   CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
00363   husart->FifoMode = USART_FIFOMODE_DISABLE;
00364
00365   /* Restore USART configuration */
00366   WRITE_REG(husart->Instance->CR1, tmpcr1);
00367
00368   husart->State = HAL_USART_STATE_READY;
00369
00370   /* Process Unlocked */
00371   __HAL_UNLOCK(husart);
00372
00373   return HAL_OK;
00374 }
00375
00376 /**
00377   * @brief  Set the TXFIFO threshold.
00378   * @param husart      USART handle.
00379   * @param Threshold  TX FIFO threshold value
00380   *          This parameter can be one of the following values:
00381   *            @arg @ref USART_TXFIFO_THRESHOLD_1_8
00382   *            @arg @ref USART_TXFIFO_THRESHOLD_1_4
00383   *            @arg @ref USART_TXFIFO_THRESHOLD_1_2
00384   *            @arg @ref USART_TXFIFO_THRESHOLD_3_4
00385   *            @arg @ref USART_TXFIFO_THRESHOLD_7_8
00386   *            @arg @ref USART_TXFIFO_THRESHOLD_8_8
00387   * @retval HAL status
00388   */
00389 HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold)
00390 {
00391   uint32_t tmpcr1;
00392
00393   /* Check parameters */
00394   assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
00395   assert_param(IS_USART_TXFIFO_THRESHOLD(Threshold));
00396
00397   /* Process Locked */
00398   __HAL_LOCK(husart);
00399
00400   husart->State = HAL_USART_STATE_BUSY;
00401
00402   /* Save actual USART configuration */
00403   tmpcr1 = READ_REG(husart->Instance->CR1);
00404
00405   /* Disable USART */
00406   __HAL_USART_DISABLE(husart);
00407
00408   /* Update TX threshold configuration */
00409   MODIFY_REG(husart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
00410
00411   /* Determine the number of data to process during RX/TX ISR execution */
00412   USARTEx_SetNbDataToProcess(husart);
00413
00414   /* Restore USART configuration */
00415   WRITE_REG(husart->Instance->CR1, tmpcr1);
00416
00417   husart->State = HAL_USART_STATE_READY;
00418
00419   /* Process Unlocked */
00420   __HAL_UNLOCK(husart);
00421
00422   return HAL_OK;
00423 }
00424
00425 /**
00426   * @brief  Set the RXFIFO threshold.
00427   * @param husart      USART handle.
00428   * @param Threshold  RX FIFO threshold value
00429   *          This parameter can be one of the following values:
00430   *            @arg @ref USART_RXFIFO_THRESHOLD_1_8
00431   *            @arg @ref USART_RXFIFO_THRESHOLD_1_4
00432   *            @arg @ref USART_RXFIFO_THRESHOLD_1_2
00433   *            @arg @ref USART_RXFIFO_THRESHOLD_3_4
00434   *            @arg @ref USART_RXFIFO_THRESHOLD_7_8
00435   *            @arg @ref USART_RXFIFO_THRESHOLD_8_8
00436   * @retval HAL status
00437   */
00438 HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold)
00439 {
00440   uint32_t tmpcr1;
00441
00442   /* Check the parameters */
00443   assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
00444   assert_param(IS_USART_RXFIFO_THRESHOLD(Threshold));
00445
00446   /* Process Locked */
00447   __HAL_LOCK(husart);
00448
00449   husart->State = HAL_USART_STATE_BUSY;
00450
00451   /* Save actual USART configuration */
00452   tmpcr1 = READ_REG(husart->Instance->CR1);
00453
00454   /* Disable USART */
00455   __HAL_USART_DISABLE(husart);
00456
00457   /* Update RX threshold configuration */
00458   MODIFY_REG(husart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
00459
00460   /* Determine the number of data to process during RX/TX ISR execution */
00461   USARTEx_SetNbDataToProcess(husart);
00462
00463   /* Restore USART configuration */
00464   WRITE_REG(husart->Instance->CR1, tmpcr1);
00465
00466   husart->State = HAL_USART_STATE_READY;
00467
00468   /* Process Unlocked */
00469   __HAL_UNLOCK(husart);
00470
00471   return HAL_OK;
00472 }
00473
00474 /**
00475   * @}
00476   */
00477
00478 /**
00479   * @}
00480   */
00481
00482 /** @addtogroup USARTEx_Private_Functions
00483   * @{
00484   */
00485
00486 /**
00487   * @brief Calculate the number of data to process in RX/TX ISR.
00488   * @note The RX FIFO depth and the TX FIFO depth is extracted from
00489   *       the USART configuration registers.
00490   * @param husart USART handle.
00491   * @retval None
00492   */
00493 static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart)
00494 {
00495   uint8_t rx_fifo_depth;
00496   uint8_t tx_fifo_depth;
00497   uint8_t rx_fifo_threshold;
00498   uint8_t tx_fifo_threshold;
00499   /* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */
00500   uint8_t numerator[]   = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
00501   uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
00502
00503   if (husart->FifoMode == USART_FIFOMODE_DISABLE)
00504   {
00505     husart->NbTxDataToProcess = 1U;
00506     husart->NbRxDataToProcess = 1U;
00507   }
00508   else
00509   {
00510     rx_fifo_depth = RX_FIFO_DEPTH;
00511     tx_fifo_depth = TX_FIFO_DEPTH;
00512     rx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos) & 0xFFU);
00513     tx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos) & 0xFFU);
00514     husart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold];
00515     husart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold];
00516   }
00517 }
00518 /**
00519   * @}
00520   */
00521
00522 #endif /* HAL_USART_MODULE_ENABLED */
00523
00524 /**
00525   * @}
00526   */
00527
00528 /**
00529   * @}
00530   */
00531
00532 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_usart_ex.h Source File

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stm32wbxx_hal_usart_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_usart_ex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of USART HAL Extended module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_USART_EX_H
00022 #define STM32WBxx_HAL_USART_EX_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 /** @addtogroup STM32WBxx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup USARTEx
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040 /* Exported constants --------------------------------------------------------*/
00041 /** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants
00042   * @{
00043   */
00044
00045 /** @defgroup USARTEx_Word_Length USARTEx Word Length
00046   * @{
00047   */
00048 #define USART_WORDLENGTH_7B                  ((uint32_t)USART_CR1_M1)   /*!< 7-bit long USART frame */
00049 #define USART_WORDLENGTH_8B                  0x00000000U                /*!< 8-bit long USART frame */
00050 #define USART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M0)   /*!< 9-bit long USART frame */
00051 /**
00052   * @}
00053   */
00054
00055 /** @defgroup USARTEx_Slave_Select_management USARTEx Slave Select Management
00056   * @{
00057   */
00058 #define USART_NSS_HARD                        0x00000000U          /*!< SPI slave selection depends on NSS input pin              */
00059 #define USART_NSS_SOFT                        USART_CR2_DIS_NSS    /*!< SPI slave is always selected and NSS input pin is ignored */
00060 /**
00061   * @}
00062   */
00063
00064
00065 /** @defgroup USARTEx_Slave_Mode USARTEx Synchronous Slave mode enable
00066   * @brief    USART SLAVE mode
00067   * @{
00068   */
00069 #define USART_SLAVEMODE_DISABLE   0x00000000U     /*!< USART SPI Slave Mode Enable  */
00070 #define USART_SLAVEMODE_ENABLE    USART_CR2_SLVEN /*!< USART SPI Slave Mode Disable */
00071 /**
00072   * @}
00073   */
00074
00075 /** @defgroup USARTEx_FIFO_mode USARTEx FIFO  mode
00076   * @brief    USART FIFO  mode
00077   * @{
00078   */
00079 #define USART_FIFOMODE_DISABLE        0x00000000U                   /*!< FIFO mode disable */
00080 #define USART_FIFOMODE_ENABLE         USART_CR1_FIFOEN              /*!< FIFO mode enable  */
00081 /**
00082   * @}
00083   */
00084
00085 /** @defgroup USARTEx_TXFIFO_threshold_level USARTEx TXFIFO threshold level
00086   * @brief    USART TXFIFO level
00087   * @{
00088   */
00089 #define USART_TXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< TXFIFO reaches 1/8 of its depth */
00090 #define USART_TXFIFO_THRESHOLD_1_4   USART_CR3_TXFTCFG_0                       /*!< TXFIFO reaches 1/4 of its depth */
00091 #define USART_TXFIFO_THRESHOLD_1_2   USART_CR3_TXFTCFG_1                       /*!< TXFIFO reaches 1/2 of its depth */
00092 #define USART_TXFIFO_THRESHOLD_3_4   (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */
00093 #define USART_TXFIFO_THRESHOLD_7_8   USART_CR3_TXFTCFG_2                       /*!< TXFIFO reaches 7/8 of its depth */
00094 #define USART_TXFIFO_THRESHOLD_8_8   (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty            */
00095 /**
00096   * @}
00097   */
00098
00099 /** @defgroup USARTEx_RXFIFO_threshold_level USARTEx RXFIFO threshold level
00100   * @brief    USART RXFIFO level
00101   * @{
00102   */
00103 #define USART_RXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< RXFIFO FIFO reaches 1/8 of its depth */
00104 #define USART_RXFIFO_THRESHOLD_1_4   USART_CR3_RXFTCFG_0                       /*!< RXFIFO FIFO reaches 1/4 of its depth */
00105 #define USART_RXFIFO_THRESHOLD_1_2   USART_CR3_RXFTCFG_1                       /*!< RXFIFO FIFO reaches 1/2 of its depth */
00106 #define USART_RXFIFO_THRESHOLD_3_4   (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */
00107 #define USART_RXFIFO_THRESHOLD_7_8   USART_CR3_RXFTCFG_2                       /*!< RXFIFO FIFO reaches 7/8 of its depth */
00108 #define USART_RXFIFO_THRESHOLD_8_8   (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full             */
00109 /**
00110   * @}
00111   */
00112
00113 /**
00114   * @}
00115   */
00116
00117 /* Private macros ------------------------------------------------------------*/
00118 /** @defgroup USARTEx_Private_Macros USARTEx Private Macros
00119   * @{
00120   */
00121
00122 /** @brief  Compute the USART mask to apply to retrieve the received data
00123   *         according to the word length and to the parity bits activation.
00124   * @note   If PCE = 1, the parity bit is not included in the data extracted
00125   *         by the reception API().
00126   *         This masking operation is not carried out in the case of
00127   *         DMA transfers.
00128   * @param  __HANDLE__ specifies the USART Handle.
00129   * @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field.
00130   */
00131 #define USART_MASK_COMPUTATION(__HANDLE__)                            \
00132   do {                                                                \
00133   if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B)           \
00134   {                                                                   \
00135      if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)              \
00136      {                                                                \
00137         (__HANDLE__)->Mask = 0x01FFU;                                 \
00138      }                                                                \
00139      else                                                             \
00140      {                                                                \
00141         (__HANDLE__)->Mask = 0x00FFU;                                 \
00142      }                                                                \
00143   }                                                                   \
00144   else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B)      \
00145   {                                                                   \
00146      if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)              \
00147      {                                                                \
00148         (__HANDLE__)->Mask = 0x00FFU;                                 \
00149      }                                                                \
00150      else                                                             \
00151      {                                                                \
00152         (__HANDLE__)->Mask = 0x007FU;                                 \
00153      }                                                                \
00154   }                                                                   \
00155   else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B)      \
00156   {                                                                   \
00157      if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)              \
00158      {                                                                \
00159         (__HANDLE__)->Mask = 0x007FU;                                 \
00160      }                                                                \
00161      else                                                             \
00162      {                                                                \
00163         (__HANDLE__)->Mask = 0x003FU;                                 \
00164      }                                                                \
00165   }                                                                   \
00166   else                                                                \
00167   {                                                                   \
00168     (__HANDLE__)->Mask = 0x0000U;                                     \
00169   }                                                                   \
00170 } while(0U)
00171
00172
00173 /**
00174   * @brief Ensure that USART frame length is valid.
00175   * @param __LENGTH__ USART frame length.
00176   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
00177   */
00178 #define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \
00179                                           ((__LENGTH__) == USART_WORDLENGTH_8B) || \
00180                                           ((__LENGTH__) == USART_WORDLENGTH_9B))
00181
00182 /**
00183   * @brief Ensure that USART Negative Slave Select (NSS) pin management is valid.
00184   * @param __NSS__ USART Negative Slave Select pin management.
00185   * @retval SET (__NSS__ is valid) or RESET (__NSS__ is invalid)
00186   */
00187 #define IS_USART_NSS(__NSS__) (((__NSS__) == USART_NSS_HARD) || \
00188                                ((__NSS__) == USART_NSS_SOFT))
00189
00190 /**
00191   * @brief Ensure that USART Slave Mode is valid.
00192   * @param __STATE__ USART Slave Mode.
00193   * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
00194   */
00195 #define IS_USART_SLAVEMODE(__STATE__)   (((__STATE__) == USART_SLAVEMODE_DISABLE ) || \
00196                                          ((__STATE__) == USART_SLAVEMODE_ENABLE))
00197
00198 /**
00199   * @brief Ensure that USART FIFO mode is valid.
00200   * @param __STATE__ USART FIFO mode.
00201   * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
00202   */
00203 #define IS_USART_FIFO_MODE_STATE(__STATE__) (((__STATE__) == USART_FIFOMODE_DISABLE ) || \
00204                                              ((__STATE__) == USART_FIFOMODE_ENABLE))
00205
00206 /**
00207   * @brief Ensure that USART TXFIFO threshold level is valid.
00208   * @param __THRESHOLD__ USART TXFIFO threshold level.
00209   * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
00210   */
00211 #define IS_USART_TXFIFO_THRESHOLD(__THRESHOLD__)  (((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_8)  || \
00212                                                    ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_4)  || \
00213                                                    ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_2)  || \
00214                                                    ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_3_4)  || \
00215                                                    ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_7_8)  || \
00216                                                    ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_8_8))
00217
00218 /**
00219   * @brief Ensure that USART RXFIFO threshold level is valid.
00220   * @param __THRESHOLD__ USART RXFIFO threshold level.
00221   * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
00222   */
00223 #define IS_USART_RXFIFO_THRESHOLD(__THRESHOLD__)  (((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_8)  || \
00224                                                    ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_4)  || \
00225                                                    ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_2)  || \
00226                                                    ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_3_4)  || \
00227                                                    ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_7_8)  || \
00228                                                    ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_8_8))
00229 /**
00230   * @}
00231   */
00232
00233 /* Exported functions --------------------------------------------------------*/
00234 /** @addtogroup USARTEx_Exported_Functions
00235   * @{
00236   */
00237
00238 /** @addtogroup USARTEx_Exported_Functions_Group1
00239   * @{
00240   */
00241
00242 /* IO operation functions *****************************************************/
00243 void HAL_USARTEx_RxFifoFullCallback(USART_HandleTypeDef *husart);
00244 void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart);
00245
00246 /**
00247   * @}
00248   */
00249
00250 /** @addtogroup USARTEx_Exported_Functions_Group2
00251   * @{
00252   */
00253
00254 /* Peripheral Control functions ***********************************************/
00255 HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart);
00256 HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart);
00257 HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig);
00258 HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart);
00259 HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart);
00260 HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold);
00261 HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold);
00262
00263 /**
00264   * @}
00265   */
00266
00267 /**
00268   * @}
00269   */
00270
00271 /**
00272   * @}
00273   */
00274
00275 /**
00276   * @}
00277   */
00278
00279 #ifdef __cplusplus
00280 }
00281 #endif
00282
00283 #endif /* STM32WBxx_HAL_USART_EX_H */
00284
00285 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_wwdg.c Source File

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stm32wbxx_hal_wwdg.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_wwdg.c
00004   * @author  MCD Application Team
00005   * @brief   WWDG HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Window Watchdog (WWDG) peripheral:
00008   *           + Initialization and Configuration functions
00009   *           + IO operation functions
00010   @verbatim
00011   ==============================================================================
00012                       ##### WWDG Specific features #####
00013   ==============================================================================
00014   [..]
00015     Once enabled the WWDG generates a system reset on expiry of a programmed
00016     time period, unless the program refreshes the counter (T[6;0] downcounter)
00017     before reaching 0x3F value (i.e. a reset is generated when the counter
00018     value rolls down from 0x40 to 0x3F).
00019
00020     (+) An MCU reset is also generated if the counter value is refreshed
00021         before the counter has reached the refresh window value. This
00022         implies that the counter must be refreshed in a limited window.
00023     (+) Once enabled the WWDG cannot be disabled except by a system reset.
00024     (+) WWDGRST flag in RCC CSR register can be used to inform when a WWDG
00025         reset occurs.
00026     (+) The WWDG counter input clock is derived from the APB clock divided
00027         by a programmable prescaler.
00028     (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler)
00029     (+) WWDG timeout (mS) = 1000 * (T[5;0] + 1) / WWDG clock (Hz)
00030         where T[5;0] are the lowest 6 bits of Counter.
00031     (+) WWDG Counter refresh is allowed between the following limits :
00032         (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock
00033         (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
00034     (+) Typical values:
00035         (++) Counter min (T[5;0] = 0x00) @64 MHz (PCLK1) with zero prescaler:
00036              max timeout before reset: approximately 64µs
00037         (++) Counter max (T[5;0] = 0x3F) @64 MHz (PCLK1) with prescaler dividing by 128:
00038              max timeout before reset: approximately 524.28ms
00039
00040   ==============================================================================
00041                      ##### How to use this driver #####
00042   ==============================================================================
00043
00044     *** Common driver usage ***
00045     ===========================
00046
00047   [..]
00048     (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
00049     (+) Set the WWDG prescaler, refresh window and counter value
00050         using HAL_WWDG_Init() function.
00051     (+) Start the WWDG using HAL_WWDG_Start() function.
00052         When the WWDG is enabled the counter value should be configured to
00053         a value greater than 0x40 to prevent generating an immediate reset.
00054     (+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is
00055         generated when the counter reaches 0x40, and then start the WWDG using
00056         HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can
00057         add his own code by customization of callback HAL_WWDG_WakeupCallback.
00058         Once enabled, EWI interrupt cannot be disabled except by a system reset.
00059     (+) Then the application program must refresh the WWDG counter at regular
00060         intervals during normal operation to prevent an MCU reset, using
00061         HAL_WWDG_Refresh() function. This operation must occur only when
00062         the counter is lower than the refresh window value already programmed.
00063
00064     *** Callback registration ***
00065     =============================
00066
00067   [..]
00068     The compilation define  USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows
00069     the user to configure dynamically the driver callbacks. Use Functions
00070     @ref HAL_WWDG_RegisterCallback() to register a user callback.
00071
00072     (+) Function @ref HAL_WWDG_RegisterCallback() allows to register following
00073         callbacks:
00074         (++) EwiCallback : callback for Early WakeUp Interrupt.
00075         (++) MspInitCallback : WWDG MspInit.
00076     This function takes as parameters the HAL peripheral handle, the Callback ID
00077     and a pointer to the user callback function.
00078
00079     (+) Use function @ref HAL_WWDG_UnRegisterCallback() to reset a callback to
00080     the default weak (surcharged) function. @ref HAL_WWDG_UnRegisterCallback()
00081     takes as parameters the HAL peripheral handle and the Callback ID.
00082     This function allows to reset following callbacks:
00083         (++) EwiCallback : callback for  Early WakeUp Interrupt.
00084         (++) MspInitCallback : WWDG MspInit.
00085
00086     [..]
00087     When calling @ref HAL_WWDG_Init function, callbacks are reset to the
00088     corresponding legacy weak (surcharged) functions:
00089     @ref HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have
00090     not been registered before.
00091
00092     [..]
00093     When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or
00094     not defined, the callback registering feature is not available
00095     and weak (surcharged) callbacks are used.
00096
00097     *** WWDG HAL driver macros list ***
00098     ===================================
00099     [..]
00100       Below the list of most used macros in WWDG HAL driver.
00101       (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
00102       (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
00103       (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
00104       (+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt
00105
00106   @endverbatim
00107   ******************************************************************************
00108   * @attention
00109   *
00110   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00111   * All rights reserved.</center></h2>
00112   *
00113   * This software component is licensed by ST under BSD 3-Clause license,
00114   * the "License"; You may not use this file except in compliance with the
00115   * License. You may obtain a copy of the License at:
00116   *                        opensource.org/licenses/BSD-3-Clause
00117   *
00118   ******************************************************************************
00119   */
00120
00121 /* Includes ------------------------------------------------------------------*/
00122 #include "stm32wbxx_hal.h"
00123
00124 /** @addtogroup STM32WBxx_HAL_Driver
00125   * @{
00126   */
00127
00128 #ifdef HAL_WWDG_MODULE_ENABLED
00129 /** @defgroup WWDG WWDG
00130   * @brief WWDG HAL module driver.
00131   * @{
00132   */
00133
00134 /* Private typedef -----------------------------------------------------------*/
00135 /* Private define ------------------------------------------------------------*/
00136 /* Private macro -------------------------------------------------------------*/
00137 /* Private variables ---------------------------------------------------------*/
00138 /* Private function prototypes -----------------------------------------------*/
00139 /* Exported functions --------------------------------------------------------*/
00140
00141 /** @defgroup WWDG_Exported_Functions WWDG Exported Functions
00142   * @{
00143   */
00144
00145 /** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions
00146   *  @brief    Initialization and Configuration functions.
00147   *
00148 @verbatim
00149   ==============================================================================
00150           ##### Initialization and Configuration functions #####
00151   ==============================================================================
00152   [..]
00153     This section provides functions allowing to:
00154       (+) Initialize and start the WWDG according to the specified parameters
00155           in the WWDG_InitTypeDef of associated handle.
00156       (+) Initialize the WWDG MSP.
00157
00158 @endverbatim
00159   * @{
00160   */
00161
00162 /**
00163   * @brief  Initialize the WWDG according to the specified.
00164   *         parameters in the WWDG_InitTypeDef of  associated handle.
00165   * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
00166   *                the configuration information for the specified WWDG module.
00167   * @retval HAL status
00168   */
00169 HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
00170 {
00171   /* Check the WWDG handle allocation */
00172   if (hwwdg == NULL)
00173   {
00174     return HAL_ERROR;
00175   }
00176
00177   /* Check the parameters */
00178   assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
00179   assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
00180   assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));
00181   assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
00182   assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode));
00183
00184 #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
00185   /* Reset Callback pointers */
00186   if (hwwdg->EwiCallback == NULL)
00187   {
00188     hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
00189   }
00190
00191   if (hwwdg->MspInitCallback == NULL)
00192   {
00193     hwwdg->MspInitCallback = HAL_WWDG_MspInit;
00194   }
00195
00196   /* Init the low level hardware */
00197   hwwdg->MspInitCallback(hwwdg);
00198 #else
00199   /* Init the low level hardware */
00200   HAL_WWDG_MspInit(hwwdg);
00201 #endif
00202
00203   /* Set WWDG Counter */
00204   WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));
00205
00206   /* Set WWDG Prescaler and Window */
00207   WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window));
00208
00209   /* Return function status */
00210   return HAL_OK;
00211 }
00212
00213
00214 /**
00215   * @brief  Initialize the WWDG MSP.
00216   * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
00217   *                the configuration information for the specified WWDG module.
00218   * @note   When rewriting this function in user file, mechanism may be added
00219   *         to avoid multiple initialize when HAL_WWDG_Init function is called
00220   *         again to change parameters.
00221   * @retval None
00222   */
00223 __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
00224 {
00225   /* Prevent unused argument(s) compilation warning */
00226   UNUSED(hwwdg);
00227
00228   /* NOTE: This function should not be modified, when the callback is needed,
00229            the HAL_WWDG_MspInit could be implemented in the user file
00230    */
00231 }
00232
00233
00234 #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
00235 /**
00236   * @brief  Register a User WWDG Callback
00237   *         To be used instead of the weak (surcharged) predefined callback
00238   * @param  hwwdg WWDG handle
00239   * @param  CallbackID ID of the callback to be registered
00240   *         This parameter can be one of the following values:
00241   *           @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
00242   *           @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
00243   * @param  pCallback pointer to the Callback function
00244   * @retval status
00245   */
00246 HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback)
00247 {
00248   HAL_StatusTypeDef status = HAL_OK;
00249
00250   if (pCallback == NULL)
00251   {
00252     status = HAL_ERROR;
00253   }
00254   else
00255   {
00256     switch (CallbackID)
00257     {
00258       case HAL_WWDG_EWI_CB_ID:
00259         hwwdg->EwiCallback = pCallback;
00260         break;
00261
00262       case HAL_WWDG_MSPINIT_CB_ID:
00263         hwwdg->MspInitCallback = pCallback;
00264         break;
00265
00266       default:
00267         status = HAL_ERROR;
00268         break;
00269     }
00270   }
00271
00272   return status;
00273 }
00274
00275
00276 /**
00277   * @brief  Unregister a WWDG Callback
00278   *         WWDG Callback is redirected to the weak (surcharged) predefined callback
00279   * @param  hwwdg WWDG handle
00280   * @param  CallbackID ID of the callback to be registered
00281   *         This parameter can be one of the following values:
00282   *           @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
00283   *           @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
00284   * @retval status
00285   */
00286 HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID)
00287 {
00288   HAL_StatusTypeDef status = HAL_OK;
00289
00290   switch (CallbackID)
00291   {
00292     case HAL_WWDG_EWI_CB_ID:
00293       hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
00294       break;
00295
00296     case HAL_WWDG_MSPINIT_CB_ID:
00297       hwwdg->MspInitCallback = HAL_WWDG_MspInit;
00298       break;
00299
00300     default:
00301       status = HAL_ERROR;
00302       break;
00303   }
00304
00305   return status;
00306 }
00307 #endif
00308
00309 /**
00310   * @}
00311   */
00312
00313 /** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
00314   *  @brief    IO operation functions
00315   *
00316 @verbatim
00317   ==============================================================================
00318                       ##### IO operation functions #####
00319   ==============================================================================
00320   [..]
00321     This section provides functions allowing to:
00322     (+) Refresh the WWDG.
00323     (+) Handle WWDG interrupt request and associated function callback.
00324
00325 @endverbatim
00326   * @{
00327   */
00328
00329 /**
00330   * @brief  Refresh the WWDG.
00331   * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
00332   *                the configuration information for the specified WWDG module.
00333   * @retval HAL status
00334   */
00335 HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg)
00336 {
00337   /* Write to WWDG CR the WWDG Counter value to refresh with */
00338   WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter));
00339
00340   /* Return function status */
00341   return HAL_OK;
00342 }
00343
00344 /**
00345   * @brief  Handle WWDG interrupt request.
00346   * @note   The Early Wakeup Interrupt (EWI) can be used if specific safety operations
00347   *         or data logging must be performed before the actual reset is generated.
00348   *         The EWI interrupt is enabled by calling HAL_WWDG_Init function with
00349   *         EWIMode set to WWDG_EWI_ENABLE.
00350   *         When the downcounter reaches the value 0x40, and EWI interrupt is
00351   *         generated and the corresponding Interrupt Service Routine (ISR) can
00352   *         be used to trigger specific actions (such as communications or data
00353   *         logging), before resetting the device.
00354   * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
00355   *                the configuration information for the specified WWDG module.
00356   * @retval None
00357   */
00358 void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
00359 {
00360   /* Check if Early Wakeup Interrupt is enable */
00361   if (__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
00362   {
00363     /* Check if WWDG Early Wakeup Interrupt occurred */
00364     if (__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
00365     {
00366       /* Clear the WWDG Early Wakeup flag */
00367       __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
00368
00369 #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
00370       /* Early Wakeup registered callback */
00371       hwwdg->EwiCallback(hwwdg);
00372 #else
00373       /* Early Wakeup callback */
00374       HAL_WWDG_EarlyWakeupCallback(hwwdg);
00375 #endif
00376     }
00377   }
00378 }
00379
00380
00381 /**
00382   * @brief  WWDG Early Wakeup callback.
00383   * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
00384   *                the configuration information for the specified WWDG module.
00385   * @retval None
00386   */
00387 __weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg)
00388 {
00389   /* Prevent unused argument(s) compilation warning */
00390   UNUSED(hwwdg);
00391
00392   /* NOTE: This function should not be modified, when the callback is needed,
00393            the HAL_WWDG_EarlyWakeupCallback could be implemented in the user file
00394    */
00395 }
00396
00397 /**
00398   * @}
00399   */
00400
00401 /**
00402   * @}
00403   */
00404
00405 #endif /* HAL_WWDG_MODULE_ENABLED */
00406 /**
00407   * @}
00408   */
00409
00410 /**
00411   * @}
00412   */
00413
00414 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_hal_wwdg.h Source File

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stm32wbxx_hal_wwdg.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_hal_wwdg.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of WWDG HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_HAL_WWDG_H
00022 #define STM32WBxx_HAL_WWDG_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx_hal_def.h"
00030
00031 /** @addtogroup STM32WBxx_HAL_Driver
00032   * @{
00033   */
00034
00035 /** @addtogroup WWDG
00036   * @{
00037   */
00038
00039 /* Exported types ------------------------------------------------------------*/
00040
00041 /** @defgroup WWDG_Exported_Types WWDG Exported Types
00042   * @{
00043   */
00044
00045 /**
00046   * @brief  WWDG Init structure definition
00047   */
00048 typedef struct
00049 {
00050   uint32_t Prescaler;     /*!< Specifies the prescaler value of the WWDG.
00051                                This parameter can be a value of @ref WWDG_Prescaler */
00052
00053   uint32_t Window;        /*!< Specifies the WWDG window value to be compared to the downcounter.
00054                                This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */
00055
00056   uint32_t Counter;       /*!< Specifies the WWDG free-running downcounter  value.
00057                                This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
00058
00059   uint32_t EWIMode ;      /*!< Specifies if WWDG Early Wakeup Interupt is enable or not.
00060                                This parameter can be a value of @ref WWDG_EWI_Mode */
00061
00062 } WWDG_InitTypeDef;
00063
00064 /**
00065   * @brief  WWDG handle Structure definition
00066   */
00067 #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
00068 typedef struct __WWDG_HandleTypeDef
00069 #else
00070 typedef struct
00071 #endif
00072 {
00073   WWDG_TypeDef      *Instance;  /*!< Register base address */
00074
00075   WWDG_InitTypeDef  Init;       /*!< WWDG required parameters */
00076
00077 #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
00078   void              (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg);     /*!< WWDG Early WakeUp Interrupt callback */
00079
00080   void              (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */
00081 #endif
00082 } WWDG_HandleTypeDef;
00083
00084 #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
00085 /**
00086   * @brief  HAL WWDG common Callback ID enumeration definition
00087   */
00088 typedef enum
00089 {
00090   HAL_WWDG_EWI_CB_ID          = 0x00u,    /*!< WWDG EWI callback ID */
00091   HAL_WWDG_MSPINIT_CB_ID      = 0x01u,    /*!< WWDG MspInit callback ID */
00092 } HAL_WWDG_CallbackIDTypeDef;
00093
00094 /**
00095   * @brief  HAL WWDG Callback pointer definition
00096   */
00097 typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp);  /*!< pointer to a WWDG common callback functions */
00098
00099 #endif
00100 /**
00101   * @}
00102   */
00103
00104 /* Exported constants --------------------------------------------------------*/
00105
00106 /** @defgroup WWDG_Exported_Constants WWDG Exported Constants
00107   * @{
00108   */
00109
00110 /** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
00111   * @{
00112   */
00113 #define WWDG_IT_EWI                         WWDG_CFR_EWI  /*!< Early wakeup interrupt */
00114 /**
00115   * @}
00116   */
00117
00118 /** @defgroup WWDG_Flag_definition WWDG Flag definition
00119   * @brief WWDG Flag definition
00120   * @{
00121   */
00122 #define WWDG_FLAG_EWIF                      WWDG_SR_EWIF  /*!< Early wakeup interrupt flag */
00123 /**
00124   * @}
00125   */
00126
00127 /** @defgroup WWDG_Prescaler WWDG Prescaler
00128   * @{
00129   */
00130 #define WWDG_PRESCALER_1                    0x00000000u                              /*!< WWDG counter clock = (PCLK1/4096)/1 */
00131 #define WWDG_PRESCALER_2                    WWDG_CFR_WDGTB_0                         /*!< WWDG counter clock = (PCLK1/4096)/2 */
00132 #define WWDG_PRESCALER_4                    WWDG_CFR_WDGTB_1                         /*!< WWDG counter clock = (PCLK1/4096)/4 */
00133 #define WWDG_PRESCALER_8                    (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)    /*!< WWDG counter clock = (PCLK1/4096)/8 */
00134 #define WWDG_PRESCALER_16                   WWDG_CFR_WDGTB_2                         /*!< WWDG counter clock = (PCLK1/4096)/16 */
00135 #define WWDG_PRESCALER_32                   (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0)    /*!< WWDG counter clock = (PCLK1/4096)/32 */
00136 #define WWDG_PRESCALER_64                   (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1)    /*!< WWDG counter clock = (PCLK1/4096)/64 */
00137 #define WWDG_PRESCALER_128                  WWDG_CFR_WDGTB                           /*!< WWDG counter clock = (PCLK1/4096)/128 */
00138 /**
00139   * @}
00140   */
00141
00142 /** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode
00143   * @{
00144   */
00145 #define WWDG_EWI_DISABLE                    0x00000000u       /*!< EWI Disable */
00146 #define WWDG_EWI_ENABLE                     WWDG_CFR_EWI      /*!< EWI Enable */
00147 /**
00148   * @}
00149   */
00150
00151 /**
00152   * @}
00153   */
00154
00155 /* Private macros ------------------------------------------------------------*/
00156
00157 /** @defgroup WWDG_Private_Macros WWDG Private Macros
00158   * @{
00159   */
00160 #define IS_WWDG_PRESCALER(__PRESCALER__)    (((__PRESCALER__) == WWDG_PRESCALER_1)  || \
00161                                              ((__PRESCALER__) == WWDG_PRESCALER_2)  || \
00162                                              ((__PRESCALER__) == WWDG_PRESCALER_4)  || \
00163                                              ((__PRESCALER__) == WWDG_PRESCALER_8)  || \
00164                                              ((__PRESCALER__) == WWDG_PRESCALER_16) || \
00165                                              ((__PRESCALER__) == WWDG_PRESCALER_32) || \
00166                                              ((__PRESCALER__) == WWDG_PRESCALER_64) || \
00167                                              ((__PRESCALER__) == WWDG_PRESCALER_128))
00168
00169 #define IS_WWDG_WINDOW(__WINDOW__)          (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
00170
00171 #define IS_WWDG_COUNTER(__COUNTER__)        (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
00172
00173 #define IS_WWDG_EWI_MODE(__MODE__)          (((__MODE__) == WWDG_EWI_ENABLE) || \
00174                                              ((__MODE__) == WWDG_EWI_DISABLE))
00175 /**
00176   * @}
00177   */
00178
00179
00180 /* Exported macros ------------------------------------------------------------*/
00181
00182 /** @defgroup WWDG_Exported_Macros WWDG Exported Macros
00183   * @{
00184   */
00185
00186 /**
00187   * @brief  Enable the WWDG peripheral.
00188   * @param  __HANDLE__  WWDG handle
00189   * @retval None
00190   */
00191 #define __HAL_WWDG_ENABLE(__HANDLE__)                         SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
00192
00193 /**
00194   * @brief  Enable the WWDG early wakeup interrupt.
00195   * @param  __HANDLE__: WWDG handle
00196   * @param  __INTERRUPT__  specifies the interrupt to enable.
00197   *         This parameter can be one of the following values:
00198   *            @arg WWDG_IT_EWI: Early wakeup interrupt
00199   * @note   Once enabled this interrupt cannot be disabled except by a system reset.
00200   * @retval None
00201   */
00202 #define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__)       SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
00203
00204 /**
00205   * @brief  Check whether the selected WWDG interrupt has occurred or not.
00206   * @param  __HANDLE__  WWDG handle
00207   * @param  __INTERRUPT__  specifies the it to check.
00208   *        This parameter can be one of the following values:
00209   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
00210   * @retval The new state of WWDG_FLAG (SET or RESET).
00211   */
00212 #define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__)        __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
00213
00214 /** @brief  Clear the WWDG interrupt pending bits.
00215   *         bits to clear the selected interrupt pending bits.
00216   * @param  __HANDLE__  WWDG handle
00217   * @param  __INTERRUPT__  specifies the interrupt pending bit to clear.
00218   *         This parameter can be one of the following values:
00219   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
00220   */
00221 #define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__)      __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
00222
00223 /**
00224   * @brief  Check whether the specified WWDG flag is set or not.
00225   * @param  __HANDLE__  WWDG handle
00226   * @param  __FLAG__  specifies the flag to check.
00227   *         This parameter can be one of the following values:
00228   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
00229   * @retval The new state of WWDG_FLAG (SET or RESET).
00230   */
00231 #define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__)           (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
00232
00233 /**
00234   * @brief  Clear the WWDG's pending flags.
00235   * @param  __HANDLE__  WWDG handle
00236   * @param  __FLAG__  specifies the flag to clear.
00237   *         This parameter can be one of the following values:
00238   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
00239   * @retval None
00240   */
00241 #define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->SR = ~(__FLAG__))
00242
00243 /** @brief  Check whether the specified WWDG interrupt source is enabled or not.
00244   * @param  __HANDLE__  WWDG Handle.
00245   * @param  __INTERRUPT__  specifies the WWDG interrupt source to check.
00246   *         This parameter can be one of the following values:
00247   *            @arg WWDG_IT_EWI: Early Wakeup Interrupt
00248   * @retval state of __INTERRUPT__ (TRUE or FALSE).
00249   */
00250 #define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR\
00251                                                               & (__INTERRUPT__)) == (__INTERRUPT__))
00252
00253 /**
00254   * @}
00255   */
00256
00257 /* Exported functions --------------------------------------------------------*/
00258
00259 /** @addtogroup WWDG_Exported_Functions
00260   * @{
00261   */
00262
00263 /** @addtogroup WWDG_Exported_Functions_Group1
00264   * @{
00265   */
00266 /* Initialization/de-initialization functions  **********************************/
00267 HAL_StatusTypeDef     HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
00268 void                  HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
00269 /* Callbacks Register/UnRegister functions  ***********************************/
00270 #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
00271 HAL_StatusTypeDef     HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback);
00272 HAL_StatusTypeDef     HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID);
00273 #endif
00274
00275 /**
00276   * @}
00277   */
00278
00279 /** @addtogroup WWDG_Exported_Functions_Group2
00280   * @{
00281   */
00282 /* I/O operation functions ******************************************************/
00283 HAL_StatusTypeDef     HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);
00284 void                  HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
00285 void                  HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg);
00286 /**
00287   * @}
00288   */
00289
00290 /**
00291   * @}
00292   */
00293
00294 /**
00295   * @}
00296   */
00297
00298 /**
00299   * @}
00300   */
00301
00302 #ifdef __cplusplus
00303 }
00304 #endif
00305
00306 #endif /* STM32WBxx_HAL_WWDG_H */
00307
00308 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_adc.c Source File

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stm32wbxx_ll_adc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_adc.c
00004   * @author  MCD Application Team
00005   * @brief   ADC LL module driver
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32wbxx_ll_adc.h"
00023 #include "stm32wbxx_ll_bus.h"
00024
00025 #ifdef  USE_FULL_ASSERT
00026 #include "stm32_assert.h"
00027 #else
00028 #define assert_param(expr) ((void)0U)
00029 #endif
00030
00031 /** @addtogroup STM32WBxx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (ADC1)
00036
00037 /** @addtogroup ADC_LL ADC
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /** @addtogroup ADC_LL_Private_Constants
00045   * @{
00046   */
00047
00048 /* Definitions of ADC hardware constraints delays */
00049 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver,   */
00050 /*       not timeout values:                                                  */
00051 /*       Timeout values for ADC operations are dependent to device clock      */
00052 /*       configuration (system clock versus ADC clock),                       */
00053 /*       and therefore must be defined in user application.                   */
00054 /*       Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout     */
00055 /*       values definition.                                                   */
00056 /* Note: ADC timeout values are defined here in CPU cycles to be independent  */
00057 /*       of device clock setting.                                             */
00058 /*       In user application, ADC timeout values should be defined with       */
00059 /*       temporal values, in function of device clock settings.               */
00060 /*       Highest ratio CPU clock frequency vs ADC clock frequency:            */
00061 /*        - ADC clock from synchronous clock with AHB prescaler 512,          */
00062 /*          APB prescaler 16, ADC prescaler 4.                                */
00063 /*        - ADC clock from asynchronous clock (PLLSAI) with prescaler 1,      */
00064 /*          with highest ratio CPU clock frequency vs HSI clock frequency:    */
00065 /*          CPU clock frequency max 72MHz, PLLSAI freq min 26MHz: ratio 4.    */
00066 /* Unit: CPU cycles.                                                          */
00067 #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST          (512UL * 16UL * 4UL)
00068 #define ADC_TIMEOUT_DISABLE_CPU_CYCLES          (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
00069 #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES  (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
00070
00071 /**
00072   * @}
00073   */
00074
00075 /* Private macros ------------------------------------------------------------*/
00076
00077 /** @addtogroup ADC_LL_Private_Macros
00078   * @{
00079   */
00080
00081 /* Check of parameters for configuration of ADC hierarchical scope:           */
00082 /* common to several ADC instances.                                           */
00083 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__)                                      \
00084   (   ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1)                             \
00085    || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2)                             \
00086    || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4)                             \
00087    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1)                                 \
00088    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2)                                 \
00089    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4)                                 \
00090    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6)                                 \
00091    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8)                                 \
00092    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10)                                \
00093    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12)                                \
00094    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16)                                \
00095    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32)                                \
00096    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64)                                \
00097    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128)                               \
00098    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256)                               \
00099   )
00100
00101 /* Check of parameters for configuration of ADC hierarchical scope:           */
00102 /* ADC instance.                                                              */
00103 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__)                                   \
00104   (   ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B)                              \
00105    || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B)                              \
00106    || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B)                               \
00107    || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B)                               \
00108   )
00109
00110 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__)                                   \
00111   (   ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT)                            \
00112    || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT)                             \
00113   )
00114
00115 #define IS_LL_ADC_LOW_POWER(__LOW_POWER__)                                     \
00116   (   ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE)                                 \
00117    || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT)                                  \
00118   )
00119
00120 /* Check of parameters for configuration of ADC hierarchical scope:           */
00121 /* ADC group regular                                                          */
00122 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__)                         \
00123   (   ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                      \
00124    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO)                 \
00125    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)                \
00126    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1)                  \
00127    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2)                  \
00128    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3)                  \
00129    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO)                 \
00130    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)                  \
00131    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)               \
00132   )
00133
00134 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__)                 \
00135   (   ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE)                    \
00136    || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS)                \
00137   )
00138
00139 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__)                       \
00140   (   ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE)                 \
00141    || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED)              \
00142    || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED)            \
00143   )
00144
00145 #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__)             \
00146   (   ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED)           \
00147    || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN)         \
00148   )
00149
00150 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__)                 \
00151   (   ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE)               \
00152    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS)         \
00153    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS)         \
00154    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS)         \
00155    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS)         \
00156    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS)         \
00157    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS)         \
00158    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS)         \
00159    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS)         \
00160    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS)        \
00161    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS)        \
00162    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS)        \
00163    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS)        \
00164    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS)        \
00165    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS)        \
00166    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS)        \
00167   )
00168
00169 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__)          \
00170   (   ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE)           \
00171    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK)             \
00172    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS)            \
00173    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS)            \
00174    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS)            \
00175    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS)            \
00176    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS)            \
00177    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS)            \
00178    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS)            \
00179   )
00180
00181 /* Check of parameters for configuration of ADC hierarchical scope:           */
00182 /* ADC group injected                                                         */
00183 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__)                         \
00184   (   ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                      \
00185    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)                 \
00186    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)                \
00187    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)                  \
00188    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)                 \
00189    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1)                  \
00190    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)               \
00191   )
00192
00193 #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__)                     \
00194   (   ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING)                  \
00195    || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING)                 \
00196    || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING)           \
00197   )
00198
00199 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__)                             \
00200   (   ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT)                     \
00201    || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR)                \
00202   )
00203
00204 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__)                 \
00205   (   ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE)               \
00206    || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS)         \
00207    || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS)         \
00208    || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS)         \
00209   )
00210
00211 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__)          \
00212   (   ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE)           \
00213    || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK)             \
00214   )
00215
00216 /**
00217   * @}
00218   */
00219
00220
00221 /* Private function prototypes -----------------------------------------------*/
00222
00223 /* Exported functions --------------------------------------------------------*/
00224 /** @addtogroup ADC_LL_Exported_Functions
00225   * @{
00226   */
00227
00228 /** @addtogroup ADC_LL_EF_Init
00229   * @{
00230   */
00231
00232 /**
00233   * @brief  De-initialize registers of all ADC instances belonging to
00234   *         the same ADC common instance to their default reset values.
00235   * @note   This function is performing a hard reset, using high level
00236   *         clock source RCC ADC reset.
00237   * @param  ADCxy_COMMON ADC common instance
00238   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
00239   * @retval An ErrorStatus enumeration value:
00240   *          - SUCCESS: ADC common registers are de-initialized
00241   *          - ERROR: not applicable
00242   */
00243 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
00244 {
00245   /* Check the parameters */
00246   assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
00247
00248   /* Force reset of ADC clock (core clock) */
00249   LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC);
00250
00251   /* Release reset of ADC clock (core clock) */
00252   LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC);
00253
00254   return SUCCESS;
00255 }
00256
00257 /**
00258   * @brief  Initialize some features of ADC common parameters
00259   *         (all ADC instances belonging to the same ADC common instance)
00260   *         and multimode (for devices with several ADC instances available).
00261   * @note   The setting of ADC common parameters is conditioned to
00262   *         ADC instances state:
00263   *         All ADC instances belonging to the same ADC common instance
00264   *         must be disabled.
00265   * @param  ADCxy_COMMON ADC common instance
00266   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
00267   * @param  ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
00268   * @retval An ErrorStatus enumeration value:
00269   *          - SUCCESS: ADC common registers are initialized
00270   *          - ERROR: ADC common registers are not initialized
00271   */
00272 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
00273 {
00274   ErrorStatus status = SUCCESS;
00275
00276   /* Check the parameters */
00277   assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
00278   assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
00279
00280   /* Note: Hardware constraint (refer to description of functions             */
00281   /*       "LL_ADC_SetCommonXXX()":                                           */
00282   /*       On this STM32 serie, setting of these features is conditioned to   */
00283   /*       ADC state:                                                         */
00284   /*       All ADC instances of the ADC common group must be disabled.        */
00285   if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL)
00286   {
00287     /* Configuration of ADC hierarchical scope:                               */
00288     /*  - common to several ADC                                               */
00289     /*    (all ADC instances belonging to the same ADC common instance)       */
00290     /*    - Set ADC clock (conversion clock)                                  */
00291 #if defined(ADC_MULTIMODE_SUPPORT)
00292     if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
00293     {
00294       MODIFY_REG(ADCxy_COMMON->CCR,
00295                  ADC_CCR_CKMODE
00296                  | ADC_CCR_PRESC
00297                  | ADC_CCR_DUAL
00298                  | ADC_CCR_MDMA
00299                  | ADC_CCR_DELAY
00300                  ,
00301                  ADC_CommonInitStruct->CommonClock
00302                  | ADC_CommonInitStruct->Multimode
00303                  | ADC_CommonInitStruct->MultiDMATransfer
00304                  | ADC_CommonInitStruct->MultiTwoSamplingDelay
00305                 );
00306     }
00307     else
00308     {
00309       MODIFY_REG(ADCxy_COMMON->CCR,
00310                  ADC_CCR_CKMODE
00311                  | ADC_CCR_PRESC
00312                  | ADC_CCR_DUAL
00313                  | ADC_CCR_MDMA
00314                  | ADC_CCR_DELAY
00315                  ,
00316                  ADC_CommonInitStruct->CommonClock
00317                  | LL_ADC_MULTI_INDEPENDENT
00318                 );
00319     }
00320 #else
00321     LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock);
00322 #endif
00323   }
00324   else
00325   {
00326     /* Initialization error: One or several ADC instances belonging to        */
00327     /* the same ADC common instance are not disabled.                         */
00328     status = ERROR;
00329   }
00330
00331   return status;
00332 }
00333
00334 /**
00335   * @brief  Set each @ref LL_ADC_CommonInitTypeDef field to default value.
00336   * @param  ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
00337   *                              whose fields will be set to default values.
00338   * @retval None
00339   */
00340 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
00341 {
00342   /* Set ADC_CommonInitStruct fields to default values */
00343   /* Set fields of ADC common */
00344   /* (all ADC instances belonging to the same ADC common instance) */
00345   ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
00346
00347 }
00348
00349 /**
00350   * @brief  De-initialize registers of the selected ADC instance
00351   *         to their default reset values.
00352   * @note   To reset all ADC instances quickly (perform a hard reset),
00353   *         use function @ref LL_ADC_CommonDeInit().
00354   * @note   If this functions returns error status, it means that ADC instance
00355   *         is in an unknown state.
00356   *         In this case, perform a hard reset using high level
00357   *         clock source RCC ADC reset.
00358   *         Refer to function @ref LL_ADC_CommonDeInit().
00359   * @param  ADCx ADC instance
00360   * @retval An ErrorStatus enumeration value:
00361   *          - SUCCESS: ADC registers are de-initialized
00362   *          - ERROR: ADC registers are not de-initialized
00363   */
00364 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
00365 {
00366   ErrorStatus status = SUCCESS;
00367
00368   __IO uint32_t timeout_cpu_cycles = 0UL;
00369
00370   /* Check the parameters */
00371   assert_param(IS_ADC_ALL_INSTANCE(ADCx));
00372
00373   /* Disable ADC instance if not already disabled.                            */
00374   if (LL_ADC_IsEnabled(ADCx) == 1UL)
00375   {
00376     /* Set ADC group regular trigger source to SW start to ensure to not      */
00377     /* have an external trigger event occurring during the conversion stop    */
00378     /* ADC disable process.                                                   */
00379     LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
00380
00381     /* Stop potential ADC conversion on going on ADC group regular.           */
00382     if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL)
00383     {
00384       if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL)
00385       {
00386         LL_ADC_REG_StopConversion(ADCx);
00387       }
00388     }
00389
00390     /* Set ADC group injected trigger source to SW start to ensure to not     */
00391     /* have an external trigger event occurring during the conversion stop    */
00392     /* ADC disable process.                                                   */
00393     LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
00394
00395     /* Stop potential ADC conversion on going on ADC group injected.          */
00396     if (LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL)
00397     {
00398       if (LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0UL)
00399       {
00400         LL_ADC_INJ_StopConversion(ADCx);
00401       }
00402     }
00403
00404     /* Wait for ADC conversions are effectively stopped                       */
00405     timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
00406     while ((LL_ADC_REG_IsStopConversionOngoing(ADCx)
00407             | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1UL)
00408     {
00409       timeout_cpu_cycles--;
00410       if (timeout_cpu_cycles == 0UL)
00411       {
00412         /* Time-out error */
00413         status = ERROR;
00414         break;
00415       }
00416     }
00417
00418     /* Flush group injected contexts queue (register JSQR):                   */
00419     /* Note: Bit JQM must be set to empty the contexts queue (otherwise       */
00420     /*       contexts queue is maintained with the last active context).      */
00421     LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY);
00422
00423     /* Disable the ADC instance */
00424     LL_ADC_Disable(ADCx);
00425
00426     /* Wait for ADC instance is effectively disabled */
00427     timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
00428     while (LL_ADC_IsDisableOngoing(ADCx) == 1UL)
00429     {
00430       timeout_cpu_cycles--;
00431       if (timeout_cpu_cycles == 0UL)
00432       {
00433         /* Time-out error */
00434         status = ERROR;
00435         break;
00436       }
00437     }
00438   }
00439
00440   /* Check whether ADC state is compliant with expected state */
00441   if (READ_BIT(ADCx->CR,
00442                (ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
00443                 | ADC_CR_ADDIS | ADC_CR_ADEN)
00444               )
00445       == 0UL)
00446   {
00447     /* ========== Reset ADC registers ========== */
00448     /* Reset register IER */
00449     CLEAR_BIT(ADCx->IER,
00450               (LL_ADC_IT_ADRDY
00451                | LL_ADC_IT_EOC
00452                | LL_ADC_IT_EOS
00453                | LL_ADC_IT_OVR
00454                | LL_ADC_IT_EOSMP
00455                | LL_ADC_IT_JEOC
00456                | LL_ADC_IT_JEOS
00457                | LL_ADC_IT_JQOVF
00458                | LL_ADC_IT_AWD1
00459                | LL_ADC_IT_AWD2
00460                | LL_ADC_IT_AWD3
00461               )
00462              );
00463
00464     /* Reset register ISR */
00465     SET_BIT(ADCx->ISR,
00466             (LL_ADC_FLAG_ADRDY
00467              | LL_ADC_FLAG_EOC
00468              | LL_ADC_FLAG_EOS
00469              | LL_ADC_FLAG_OVR
00470              | LL_ADC_FLAG_EOSMP
00471              | LL_ADC_FLAG_JEOC
00472              | LL_ADC_FLAG_JEOS
00473              | LL_ADC_FLAG_JQOVF
00474              | LL_ADC_FLAG_AWD1
00475              | LL_ADC_FLAG_AWD2
00476              | LL_ADC_FLAG_AWD3
00477             )
00478            );
00479
00480     /* Reset register CR */
00481     /*  - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART,  */
00482     /*    ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in                      */
00483     /*    access mode "read-set": no direct reset applicable.                 */
00484     /*  - Reset Calibration mode to default setting (single ended).           */
00485     /*  - Disable ADC internal voltage regulator.                             */
00486     /*  - Enable ADC deep power down.                                         */
00487     /*    Note: ADC internal voltage regulator disable and ADC deep power     */
00488     /*          down enable are conditioned to ADC state disabled:            */
00489     /*          already done above.                                           */
00490     CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
00491     SET_BIT(ADCx->CR, ADC_CR_DEEPPWD);
00492
00493     /* Reset register CFGR */
00494     MODIFY_REG(ADCx->CFGR,
00495                (ADC_CFGR_AWD1CH  | ADC_CFGR_JAUTO   | ADC_CFGR_JAWD1EN
00496                 | ADC_CFGR_AWD1EN  | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM
00497                 | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN
00498                 | ADC_CFGR_AUTDLY  | ADC_CFGR_CONT    | ADC_CFGR_OVRMOD
00499                 | ADC_CFGR_EXTEN   | ADC_CFGR_EXTSEL  | ADC_CFGR_ALIGN
00500                 | ADC_CFGR_RES     | ADC_CFGR_DMACFG  | ADC_CFGR_DMAEN),
00501                ADC_CFGR_JQDIS
00502               );
00503
00504     /* Reset register CFGR2 */
00505     CLEAR_BIT(ADCx->CFGR2,
00506               (ADC_CFGR2_ROVSM  | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS
00507                | ADC_CFGR2_OVSR   | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)
00508              );
00509
00510     /* Reset register SMPR1 */
00511     CLEAR_BIT(ADCx->SMPR1,
00512               (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7
00513                | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4
00514                | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1)
00515              );
00516
00517     /* Reset register SMPR2 */
00518     CLEAR_BIT(ADCx->SMPR2,
00519               (ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16
00520                | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13
00521                | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10)
00522              );
00523
00524     /* Reset register TR1 */
00525     MODIFY_REG(ADCx->TR1, ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1);
00526
00527     /* Reset register TR2 */
00528     MODIFY_REG(ADCx->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, ADC_TR2_HT2);
00529
00530     /* Reset register TR3 */
00531     MODIFY_REG(ADCx->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, ADC_TR3_HT3);
00532
00533     /* Reset register SQR1 */
00534     CLEAR_BIT(ADCx->SQR1,
00535               (ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2
00536                | ADC_SQR1_SQ1 | ADC_SQR1_L)
00537              );
00538
00539     /* Reset register SQR2 */
00540     CLEAR_BIT(ADCx->SQR2,
00541               (ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7
00542                | ADC_SQR2_SQ6 | ADC_SQR2_SQ5)
00543              );
00544
00545     /* Reset register SQR3 */
00546     CLEAR_BIT(ADCx->SQR3,
00547               (ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12
00548                | ADC_SQR3_SQ11 | ADC_SQR3_SQ10)
00549              );
00550
00551     /* Reset register SQR4 */
00552     CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
00553
00554     /* Reset register JSQR */
00555     CLEAR_BIT(ADCx->JSQR,
00556               (ADC_JSQR_JL
00557                | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN
00558                | ADC_JSQR_JSQ4    | ADC_JSQR_JSQ3
00559                | ADC_JSQR_JSQ2    | ADC_JSQR_JSQ1)
00560              );
00561
00562     /* Reset register DR */
00563     /* Note: bits in access mode read only, no direct reset applicable */
00564
00565     /* Reset register OFR1 */
00566     CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
00567     /* Reset register OFR2 */
00568     CLEAR_BIT(ADCx->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
00569     /* Reset register OFR3 */
00570     CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
00571     /* Reset register OFR4 */
00572     CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
00573
00574     /* Reset registers JDR1, JDR2, JDR3, JDR4 */
00575     /* Note: bits in access mode read only, no direct reset applicable */
00576
00577     /* Reset register AWD2CR */
00578     CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH);
00579
00580     /* Reset register AWD3CR */
00581     CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH);
00582
00583     /* Reset register DIFSEL */
00584     CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL);
00585
00586     /* Reset register CALFACT */
00587     CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
00588   }
00589   else
00590   {
00591     /* ADC instance is in an unknown state */
00592     /* Need to performing a hard reset of ADC instance, using high level      */
00593     /* clock source RCC ADC reset.                                            */
00594     /* Caution: On this STM32 serie, if several ADC instances are available   */
00595     /*          on the selected device, RCC ADC reset will reset              */
00596     /*          all ADC instances belonging to the common ADC instance.       */
00597     status = ERROR;
00598   }
00599
00600   return status;
00601 }
00602
00603 /**
00604   * @brief  Initialize some features of ADC instance.
00605   * @note   These parameters have an impact on ADC scope: ADC instance.
00606   *         Affects both group regular and group injected (availability
00607   *         of ADC group injected depends on STM32 families).
00608   *         Refer to corresponding unitary functions into
00609   *         @ref ADC_LL_EF_Configuration_ADC_Instance .
00610   * @note   The setting of these parameters by function @ref LL_ADC_Init()
00611   *         is conditioned to ADC state:
00612   *         ADC instance must be disabled.
00613   *         This condition is applied to all ADC features, for efficiency
00614   *         and compatibility over all STM32 families. However, the different
00615   *         features can be set under different ADC state conditions
00616   *         (setting possible with ADC enabled without conversion on going,
00617   *         ADC enabled with conversion on going, ...)
00618   *         Each feature can be updated afterwards with a unitary function
00619   *         and potentially with ADC in a different state than disabled,
00620   *         refer to description of each function for setting
00621   *         conditioned to ADC state.
00622   * @note   After using this function, some other features must be configured
00623   *         using LL unitary functions.
00624   *         The minimum configuration remaining to be done is:
00625   *          - Set ADC group regular or group injected sequencer:
00626   *            map channel on the selected sequencer rank.
00627   *            Refer to function @ref LL_ADC_REG_SetSequencerRanks().
00628   *          - Set ADC channel sampling time
00629   *            Refer to function LL_ADC_SetChannelSamplingTime();
00630   * @param  ADCx ADC instance
00631   * @param  ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
00632   * @retval An ErrorStatus enumeration value:
00633   *          - SUCCESS: ADC registers are initialized
00634   *          - ERROR: ADC registers are not initialized
00635   */
00636 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
00637 {
00638   ErrorStatus status = SUCCESS;
00639
00640   /* Check the parameters */
00641   assert_param(IS_ADC_ALL_INSTANCE(ADCx));
00642
00643   assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
00644   assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
00645   assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
00646
00647   /* Note: Hardware constraint (refer to description of this function):       */
00648   /*       ADC instance must be disabled.                                     */
00649   if (LL_ADC_IsEnabled(ADCx) == 0UL)
00650   {
00651     /* Configuration of ADC hierarchical scope:                               */
00652     /*  - ADC instance                                                        */
00653     /*    - Set ADC data resolution                                           */
00654     /*    - Set ADC conversion data alignment                                 */
00655     /*    - Set ADC low power mode                                            */
00656     MODIFY_REG(ADCx->CFGR,
00657                ADC_CFGR_RES
00658                | ADC_CFGR_ALIGN
00659                | ADC_CFGR_AUTDLY
00660                ,
00661                ADC_InitStruct->Resolution
00662                | ADC_InitStruct->DataAlignment
00663                | ADC_InitStruct->LowPowerMode
00664               );
00665
00666   }
00667   else
00668   {
00669     /* Initialization error: ADC instance is not disabled. */
00670     status = ERROR;
00671   }
00672   return status;
00673 }
00674
00675 /**
00676   * @brief  Set each @ref LL_ADC_InitTypeDef field to default value.
00677   * @param  ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
00678   *                        whose fields will be set to default values.
00679   * @retval None
00680   */
00681 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
00682 {
00683   /* Set ADC_InitStruct fields to default values */
00684   /* Set fields of ADC instance */
00685   ADC_InitStruct->Resolution    = LL_ADC_RESOLUTION_12B;
00686   ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
00687   ADC_InitStruct->LowPowerMode  = LL_ADC_LP_MODE_NONE;
00688
00689 }
00690
00691 /**
00692   * @brief  Initialize some features of ADC group regular.
00693   * @note   These parameters have an impact on ADC scope: ADC group regular.
00694   *         Refer to corresponding unitary functions into
00695   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
00696   *         (functions with prefix "REG").
00697   * @note   The setting of these parameters by function @ref LL_ADC_Init()
00698   *         is conditioned to ADC state:
00699   *         ADC instance must be disabled.
00700   *         This condition is applied to all ADC features, for efficiency
00701   *         and compatibility over all STM32 families. However, the different
00702   *         features can be set under different ADC state conditions
00703   *         (setting possible with ADC enabled without conversion on going,
00704   *         ADC enabled with conversion on going, ...)
00705   *         Each feature can be updated afterwards with a unitary function
00706   *         and potentially with ADC in a different state than disabled,
00707   *         refer to description of each function for setting
00708   *         conditioned to ADC state.
00709   * @note   After using this function, other features must be configured
00710   *         using LL unitary functions.
00711   *         The minimum configuration remaining to be done is:
00712   *          - Set ADC group regular or group injected sequencer:
00713   *            map channel on the selected sequencer rank.
00714   *            Refer to function @ref LL_ADC_REG_SetSequencerRanks().
00715   *          - Set ADC channel sampling time
00716   *            Refer to function LL_ADC_SetChannelSamplingTime();
00717   * @param  ADCx ADC instance
00718   * @param  ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
00719   * @retval An ErrorStatus enumeration value:
00720   *          - SUCCESS: ADC registers are initialized
00721   *          - ERROR: ADC registers are not initialized
00722   */
00723 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
00724 {
00725   ErrorStatus status = SUCCESS;
00726
00727   /* Check the parameters */
00728   assert_param(IS_ADC_ALL_INSTANCE(ADCx));
00729   assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
00730   assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
00731   if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
00732   {
00733     assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
00734   }
00735   assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
00736   assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
00737   assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
00738
00739   /* Note: Hardware constraint (refer to description of this function):       */
00740   /*       ADC instance must be disabled.                                     */
00741   if (LL_ADC_IsEnabled(ADCx) == 0UL)
00742   {
00743     /* Configuration of ADC hierarchical scope:                               */
00744     /*  - ADC group regular                                                   */
00745     /*    - Set ADC group regular trigger source                              */
00746     /*    - Set ADC group regular sequencer length                            */
00747     /*    - Set ADC group regular sequencer discontinuous mode                */
00748     /*    - Set ADC group regular continuous mode                             */
00749     /*    - Set ADC group regular conversion data transfer: no transfer or    */
00750     /*      transfer by DMA, and DMA requests mode                            */
00751     /*    - Set ADC group regular overrun behavior                            */
00752     /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by     */
00753     /*       setting of trigger source to SW start.                           */
00754     if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
00755     {
00756       MODIFY_REG(ADCx->CFGR,
00757                  ADC_CFGR_EXTSEL
00758                  | ADC_CFGR_EXTEN
00759                  | ADC_CFGR_DISCEN
00760                  | ADC_CFGR_DISCNUM
00761                  | ADC_CFGR_CONT
00762                  | ADC_CFGR_DMAEN
00763                  | ADC_CFGR_DMACFG
00764                  | ADC_CFGR_OVRMOD
00765                  ,
00766                  ADC_REG_InitStruct->TriggerSource
00767                  | ADC_REG_InitStruct->SequencerDiscont
00768                  | ADC_REG_InitStruct->ContinuousMode
00769                  | ADC_REG_InitStruct->DMATransfer
00770                  | ADC_REG_InitStruct->Overrun
00771                 );
00772     }
00773     else
00774     {
00775       MODIFY_REG(ADCx->CFGR,
00776                  ADC_CFGR_EXTSEL
00777                  | ADC_CFGR_EXTEN
00778                  | ADC_CFGR_DISCEN
00779                  | ADC_CFGR_DISCNUM
00780                  | ADC_CFGR_CONT
00781                  | ADC_CFGR_DMAEN
00782                  | ADC_CFGR_DMACFG
00783                  | ADC_CFGR_OVRMOD
00784                  ,
00785                  ADC_REG_InitStruct->TriggerSource
00786                  | LL_ADC_REG_SEQ_DISCONT_DISABLE
00787                  | ADC_REG_InitStruct->ContinuousMode
00788                  | ADC_REG_InitStruct->DMATransfer
00789                  | ADC_REG_InitStruct->Overrun
00790                 );
00791     }
00792
00793     /* Set ADC group regular sequencer length and scan direction */
00794     LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
00795   }
00796   else
00797   {
00798     /* Initialization error: ADC instance is not disabled. */
00799     status = ERROR;
00800   }
00801   return status;
00802 }
00803
00804 /**
00805   * @brief  Set each @ref LL_ADC_REG_InitTypeDef field to default value.
00806   * @param  ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
00807   *                            whose fields will be set to default values.
00808   * @retval None
00809   */
00810 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
00811 {
00812   /* Set ADC_REG_InitStruct fields to default values */
00813   /* Set fields of ADC group regular */
00814   /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by       */
00815   /*       setting of trigger source to SW start.                             */
00816   ADC_REG_InitStruct->TriggerSource    = LL_ADC_REG_TRIG_SOFTWARE;
00817   ADC_REG_InitStruct->SequencerLength  = LL_ADC_REG_SEQ_SCAN_DISABLE;
00818   ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
00819   ADC_REG_InitStruct->ContinuousMode   = LL_ADC_REG_CONV_SINGLE;
00820   ADC_REG_InitStruct->DMATransfer      = LL_ADC_REG_DMA_TRANSFER_NONE;
00821   ADC_REG_InitStruct->Overrun          = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
00822 }
00823
00824 /**
00825   * @brief  Initialize some features of ADC group injected.
00826   * @note   These parameters have an impact on ADC scope: ADC group injected.
00827   *         Refer to corresponding unitary functions into
00828   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
00829   *         (functions with prefix "INJ").
00830   * @note   The setting of these parameters by function @ref LL_ADC_Init()
00831   *         is conditioned to ADC state:
00832   *         ADC instance must be disabled.
00833   *         This condition is applied to all ADC features, for efficiency
00834   *         and compatibility over all STM32 families. However, the different
00835   *         features can be set under different ADC state conditions
00836   *         (setting possible with ADC enabled without conversion on going,
00837   *         ADC enabled with conversion on going, ...)
00838   *         Each feature can be updated afterwards with a unitary function
00839   *         and potentially with ADC in a different state than disabled,
00840   *         refer to description of each function for setting
00841   *         conditioned to ADC state.
00842   * @note   After using this function, other features must be configured
00843   *         using LL unitary functions.
00844   *         The minimum configuration remaining to be done is:
00845   *          - Set ADC group injected sequencer:
00846   *            map channel on the selected sequencer rank.
00847   *            Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
00848   *          - Set ADC channel sampling time
00849   *            Refer to function LL_ADC_SetChannelSamplingTime();
00850   * @param  ADCx ADC instance
00851   * @param  ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
00852   * @retval An ErrorStatus enumeration value:
00853   *          - SUCCESS: ADC registers are initialized
00854   *          - ERROR: ADC registers are not initialized
00855   */
00856 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
00857 {
00858   ErrorStatus status = SUCCESS;
00859
00860   /* Check the parameters */
00861   assert_param(IS_ADC_ALL_INSTANCE(ADCx));
00862   assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
00863   assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
00864   if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
00865   {
00866     assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
00867   }
00868   assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
00869
00870   /* Note: Hardware constraint (refer to description of this function):       */
00871   /*       ADC instance must be disabled.                                     */
00872   if (LL_ADC_IsEnabled(ADCx) == 0UL)
00873   {
00874     /* Configuration of ADC hierarchical scope:                               */
00875     /*  - ADC group injected                                                  */
00876     /*    - Set ADC group injected trigger source                             */
00877     /*    - Set ADC group injected sequencer length                           */
00878     /*    - Set ADC group injected sequencer discontinuous mode               */
00879     /*    - Set ADC group injected conversion trigger: independent or         */
00880     /*      from ADC group regular                                            */
00881     /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by     */
00882     /*       setting of trigger source to SW start.                           */
00883     if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
00884     {
00885       MODIFY_REG(ADCx->CFGR,
00886                  ADC_CFGR_JDISCEN
00887                  | ADC_CFGR_JAUTO
00888                  ,
00889                  ADC_INJ_InitStruct->SequencerDiscont
00890                  | ADC_INJ_InitStruct->TrigAuto
00891                 );
00892     }
00893     else
00894     {
00895       MODIFY_REG(ADCx->CFGR,
00896                  ADC_CFGR_JDISCEN
00897                  | ADC_CFGR_JAUTO
00898                  ,
00899                  LL_ADC_REG_SEQ_DISCONT_DISABLE
00900                  | ADC_INJ_InitStruct->TrigAuto
00901                 );
00902     }
00903
00904     MODIFY_REG(ADCx->JSQR,
00905                ADC_JSQR_JEXTSEL
00906                | ADC_JSQR_JEXTEN
00907                | ADC_JSQR_JL
00908                ,
00909                ADC_INJ_InitStruct->TriggerSource
00910                | ADC_INJ_InitStruct->SequencerLength
00911               );
00912   }
00913   else
00914   {
00915     /* Initialization error: ADC instance is not disabled. */
00916     status = ERROR;
00917   }
00918   return status;
00919 }
00920
00921 /**
00922   * @brief  Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
00923   * @param  ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
00924   *                            whose fields will be set to default values.
00925   * @retval None
00926   */
00927 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
00928 {
00929   /* Set ADC_INJ_InitStruct fields to default values */
00930   /* Set fields of ADC group injected */
00931   ADC_INJ_InitStruct->TriggerSource    = LL_ADC_INJ_TRIG_SOFTWARE;
00932   ADC_INJ_InitStruct->SequencerLength  = LL_ADC_INJ_SEQ_SCAN_DISABLE;
00933   ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
00934   ADC_INJ_InitStruct->TrigAuto         = LL_ADC_INJ_TRIG_INDEPENDENT;
00935 }
00936
00937 /**
00938   * @}
00939   */
00940
00941 /**
00942   * @}
00943   */
00944
00945 /**
00946   * @}
00947   */
00948
00949 #endif /* ADC1 */
00950
00951 /**
00952   * @}
00953   */
00954
00955 #endif /* USE_FULL_LL_DRIVER */
00956
00957 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_adc.h Source File

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stm32wbxx_ll_adc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_adc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of ADC LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_LL_ADC_H
00022 #define STM32WBxx_LL_ADC_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx.h"
00030
00031 /** @addtogroup STM32WBxx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (ADC1)
00036
00037 /** @defgroup ADC_LL ADC
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043
00044 /* Private constants ---------------------------------------------------------*/
00045 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
00046   * @{
00047   */
00048
00049 /* Internal mask for ADC group regular sequencer:                             */
00050 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for:            */
00051 /* - sequencer register offset                                                */
00052 /* - sequencer rank bits position into the selected register                  */
00053
00054 /* Internal register offset for ADC group regular sequencer configuration */
00055 /* (offset placed into a spare area of literal definition) */
00056 #define ADC_SQR1_REGOFFSET                 (0x00000000UL)
00057 #define ADC_SQR2_REGOFFSET                 (0x00000100UL)
00058 #define ADC_SQR3_REGOFFSET                 (0x00000200UL)
00059 #define ADC_SQR4_REGOFFSET                 (0x00000300UL)
00060
00061 #define ADC_REG_SQRX_REGOFFSET_MASK        (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
00062 #define ADC_SQRX_REGOFFSET_POS             (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */
00063 #define ADC_REG_RANK_ID_SQRX_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
00064
00065 /* Definition of ADC group regular sequencer bits information to be inserted  */
00066 /* into ADC group regular sequencer ranks literals definition.                */
00067 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS  ( 6UL) /* Value equivalent to bitfield "ADC_SQR1_SQ1" position in register */
00068 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS  (12UL) /* Value equivalent to bitfield "ADC_SQR1_SQ2" position in register */
00069 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS  (18UL) /* Value equivalent to bitfield "ADC_SQR1_SQ3" position in register */
00070 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS  (24UL) /* Value equivalent to bitfield "ADC_SQR1_SQ4" position in register */
00071 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS  ( 0UL) /* Value equivalent to bitfield "ADC_SQR2_SQ5" position in register */
00072 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS  ( 6UL) /* Value equivalent to bitfield "ADC_SQR2_SQ6" position in register */
00073 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS  (12UL) /* Value equivalent to bitfield "ADC_SQR2_SQ7" position in register */
00074 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS  (18UL) /* Value equivalent to bitfield "ADC_SQR2_SQ8" position in register */
00075 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS  (24UL) /* Value equivalent to bitfield "ADC_SQR2_SQ9" position in register */
00076 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR3_SQ10" position in register */
00077 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR3_SQ11" position in register */
00078 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR3_SQ12" position in register */
00079 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR3_SQ13" position in register */
00080 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR3_SQ14" position in register */
00081 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR4_SQ15" position in register */
00082 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR4_SQ16" position in register */
00083
00084
00085
00086 /* Internal mask for ADC group injected sequencer:                            */
00087 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for:            */
00088 /* - data register offset                                                     */
00089 /* - sequencer rank bits position into the selected register                  */
00090
00091 /* Internal register offset for ADC group injected data register */
00092 /* (offset placed into a spare area of literal definition) */
00093 #define ADC_JDR1_REGOFFSET                 (0x00000000UL)
00094 #define ADC_JDR2_REGOFFSET                 (0x00000100UL)
00095 #define ADC_JDR3_REGOFFSET                 (0x00000200UL)
00096 #define ADC_JDR4_REGOFFSET                 (0x00000300UL)
00097
00098 #define ADC_INJ_JDRX_REGOFFSET_MASK        (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
00099 #define ADC_INJ_RANK_ID_JSQR_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
00100 #define ADC_JDRX_REGOFFSET_POS             (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */
00101
00102 /* Definition of ADC group injected sequencer bits information to be inserted */
00103 /* into ADC group injected sequencer ranks literals definition.               */
00104 #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS  ( 8UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ1" position in register */
00105 #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS  (14UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ2" position in register */
00106 #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS  (20UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ3" position in register */
00107 #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS  (26UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ4" position in register */
00108
00109
00110
00111 /* Internal mask for ADC group regular trigger:                               */
00112 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for:            */
00113 /* - regular trigger source                                                   */
00114 /* - regular trigger edge                                                     */
00115 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT       (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
00116
00117 /* Mask containing trigger source masks for each of possible                  */
00118 /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
00119 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
00120 #define ADC_REG_TRIG_SOURCE_MASK            (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \
00121                                              ((ADC_CFGR_EXTSEL)                            << (4U * 1UL)) | \
00122                                              ((ADC_CFGR_EXTSEL)                            << (4U * 2UL)) | \
00123                                              ((ADC_CFGR_EXTSEL)                            << (4U * 3UL))  )
00124
00125 /* Mask containing trigger edge masks for each of possible                    */
00126 /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
00127 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
00128 #define ADC_REG_TRIG_EDGE_MASK              (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \
00129                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 1UL)) | \
00130                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 2UL)) | \
00131                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 3UL))  )
00132
00133 /* Definition of ADC group regular trigger bits information.                  */
00134 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS  ( 6UL) /* Value equivalent to bitfield "ADC_CFGR_EXTSEL" position in register */
00135 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS   (10UL) /* Value equivalent to bitfield "ADC_CFGR_EXTEN" position in register */
00136
00137
00138
00139 /* Internal mask for ADC group injected trigger:                              */
00140 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for:            */
00141 /* - injected trigger source                                                  */
00142 /* - injected trigger edge                                                    */
00143 #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT      (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
00144
00145 /* Mask containing trigger source masks for each of possible                  */
00146 /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
00147 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
00148 #define ADC_INJ_TRIG_SOURCE_MASK            (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL)  << (4U * 0UL)) | \
00149                                              ((ADC_JSQR_JEXTSEL)                             << (4U * 1UL)) | \
00150                                              ((ADC_JSQR_JEXTSEL)                             << (4U * 2UL)) | \
00151                                              ((ADC_JSQR_JEXTSEL)                             << (4U * 3UL))  )
00152
00153 /* Mask containing trigger edge masks for each of possible                    */
00154 /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
00155 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
00156 #define ADC_INJ_TRIG_EDGE_MASK              (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \
00157                                              ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 1UL)) | \
00158                                              ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 2UL)) | \
00159                                              ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 3UL))  )
00160
00161 /* Definition of ADC group injected trigger bits information.                 */
00162 #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS  ( 2UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTSEL" position in register */
00163 #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS   ( 6UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTEN" position in register */
00164
00165
00166
00167
00168
00169
00170 /* Internal mask for ADC channel:                                             */
00171 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for:             */
00172 /* - channel identifier defined by number                                     */
00173 /* - channel identifier defined by bitfield                                   */
00174 /* - channel differentiation between external channels (connected to          */
00175 /*   GPIO pins) and internal channels (connected to internal paths)           */
00176 /* - channel sampling time defined by SMPRx register offset                   */
00177 /*   and SMPx bits positions into SMPRx register                              */
00178 #define ADC_CHANNEL_ID_NUMBER_MASK         (ADC_CFGR_AWD1CH)
00179 #define ADC_CHANNEL_ID_BITFIELD_MASK       (ADC_AWD2CR_AWD2CH)
00180 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */
00181 #define ADC_CHANNEL_ID_MASK                (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
00182 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
00183 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
00184
00185 /* Channel differentiation between external and internal channels */
00186 #define ADC_CHANNEL_ID_INTERNAL_CH         (0x80000000UL) /* Marker of internal channel */
00187 #define ADC_CHANNEL_ID_INTERNAL_CH_2       (0x00080000UL) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
00188 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK    (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
00189
00190 /* Internal register offset for ADC channel sampling time configuration */
00191 /* (offset placed into a spare area of literal definition) */
00192 #define ADC_SMPR1_REGOFFSET                (0x00000000UL)
00193 #define ADC_SMPR2_REGOFFSET                (0x02000000UL)
00194 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK   (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
00195 #define ADC_SMPRX_REGOFFSET_POS            (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
00196
00197 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK    (0x01F00000UL)
00198 #define ADC_CHANNEL_SMPx_BITOFFSET_POS     (20UL)           /* Value equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */
00199
00200 /* Definition of channels ID number information to be inserted into           */
00201 /* channels literals definition.                                              */
00202 #define ADC_CHANNEL_0_NUMBER               (0x00000000UL)
00203 #define ADC_CHANNEL_1_NUMBER               (                                                                                ADC_CFGR_AWD1CH_0)
00204 #define ADC_CHANNEL_2_NUMBER               (                                                            ADC_CFGR_AWD1CH_1                    )
00205 #define ADC_CHANNEL_3_NUMBER               (                                                            ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
00206 #define ADC_CHANNEL_4_NUMBER               (                                        ADC_CFGR_AWD1CH_2                                        )
00207 #define ADC_CHANNEL_5_NUMBER               (                                        ADC_CFGR_AWD1CH_2                     | ADC_CFGR_AWD1CH_0)
00208 #define ADC_CHANNEL_6_NUMBER               (                                        ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1                    )
00209 #define ADC_CHANNEL_7_NUMBER               (                                        ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
00210 #define ADC_CHANNEL_8_NUMBER               (                    ADC_CFGR_AWD1CH_3                                                            )
00211 #define ADC_CHANNEL_9_NUMBER               (                    ADC_CFGR_AWD1CH_3                                         | ADC_CFGR_AWD1CH_0)
00212 #define ADC_CHANNEL_10_NUMBER              (                    ADC_CFGR_AWD1CH_3                     | ADC_CFGR_AWD1CH_1                    )
00213 #define ADC_CHANNEL_11_NUMBER              (                    ADC_CFGR_AWD1CH_3                     | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
00214 #define ADC_CHANNEL_12_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2                                        )
00215 #define ADC_CHANNEL_13_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2                     | ADC_CFGR_AWD1CH_0)
00216 #define ADC_CHANNEL_14_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1                    )
00217 #define ADC_CHANNEL_15_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
00218 #define ADC_CHANNEL_16_NUMBER              (ADC_CFGR_AWD1CH_4                                                                                )
00219 #define ADC_CHANNEL_17_NUMBER              (ADC_CFGR_AWD1CH_4                                                             | ADC_CFGR_AWD1CH_0)
00220 #define ADC_CHANNEL_18_NUMBER              (ADC_CFGR_AWD1CH_4                                         | ADC_CFGR_AWD1CH_1                    )
00221
00222 /* Definition of channels ID bitfield information to be inserted into         */
00223 /* channels literals definition.                                              */
00224 #define ADC_CHANNEL_0_BITFIELD             (ADC_AWD2CR_AWD2CH_0)
00225 #define ADC_CHANNEL_1_BITFIELD             (ADC_AWD2CR_AWD2CH_1)
00226 #define ADC_CHANNEL_2_BITFIELD             (ADC_AWD2CR_AWD2CH_2)
00227 #define ADC_CHANNEL_3_BITFIELD             (ADC_AWD2CR_AWD2CH_3)
00228 #define ADC_CHANNEL_4_BITFIELD             (ADC_AWD2CR_AWD2CH_4)
00229 #define ADC_CHANNEL_5_BITFIELD             (ADC_AWD2CR_AWD2CH_5)
00230 #define ADC_CHANNEL_6_BITFIELD             (ADC_AWD2CR_AWD2CH_6)
00231 #define ADC_CHANNEL_7_BITFIELD             (ADC_AWD2CR_AWD2CH_7)
00232 #define ADC_CHANNEL_8_BITFIELD             (ADC_AWD2CR_AWD2CH_8)
00233 #define ADC_CHANNEL_9_BITFIELD             (ADC_AWD2CR_AWD2CH_9)
00234 #define ADC_CHANNEL_10_BITFIELD            (ADC_AWD2CR_AWD2CH_10)
00235 #define ADC_CHANNEL_11_BITFIELD            (ADC_AWD2CR_AWD2CH_11)
00236 #define ADC_CHANNEL_12_BITFIELD            (ADC_AWD2CR_AWD2CH_12)
00237 #define ADC_CHANNEL_13_BITFIELD            (ADC_AWD2CR_AWD2CH_13)
00238 #define ADC_CHANNEL_14_BITFIELD            (ADC_AWD2CR_AWD2CH_14)
00239 #define ADC_CHANNEL_15_BITFIELD            (ADC_AWD2CR_AWD2CH_15)
00240 #define ADC_CHANNEL_16_BITFIELD            (ADC_AWD2CR_AWD2CH_16)
00241 #define ADC_CHANNEL_17_BITFIELD            (ADC_AWD2CR_AWD2CH_17)
00242 #define ADC_CHANNEL_18_BITFIELD            (ADC_AWD2CR_AWD2CH_18)
00243
00244 /* Definition of channels sampling time information to be inserted into       */
00245 /* channels literals definition.                                              */
00246 #define ADC_CHANNEL_0_SMP                  (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP0" position in register */
00247 #define ADC_CHANNEL_1_SMP                  (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP1" position in register */
00248 #define ADC_CHANNEL_2_SMP                  (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP2" position in register */
00249 #define ADC_CHANNEL_3_SMP                  (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP3" position in register */
00250 #define ADC_CHANNEL_4_SMP                  (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP4" position in register */
00251 #define ADC_CHANNEL_5_SMP                  (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP5" position in register */
00252 #define ADC_CHANNEL_6_SMP                  (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP6" position in register */
00253 #define ADC_CHANNEL_7_SMP                  (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP7" position in register */
00254 #define ADC_CHANNEL_8_SMP                  (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP8" position in register */
00255 #define ADC_CHANNEL_9_SMP                  (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP9" position in register */
00256 #define ADC_CHANNEL_10_SMP                 (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP10" position in register */
00257 #define ADC_CHANNEL_11_SMP                 (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP11" position in register */
00258 #define ADC_CHANNEL_12_SMP                 (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP12" position in register */
00259 #define ADC_CHANNEL_13_SMP                 (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP13" position in register */
00260 #define ADC_CHANNEL_14_SMP                 (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP14" position in register */
00261 #define ADC_CHANNEL_15_SMP                 (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP15" position in register */
00262 #define ADC_CHANNEL_16_SMP                 (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP16" position in register */
00263 #define ADC_CHANNEL_17_SMP                 (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP17" position in register */
00264 #define ADC_CHANNEL_18_SMP                 (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP18" position in register */
00265
00266
00267 /* Internal mask for ADC mode single or differential ended:                   */
00268 /* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL  */
00269 /* the relevant bits for:                                                     */
00270 /* (concatenation of multiple bits used in different registers)               */
00271 /* - ADC calibration: calibration start, calibration factor get or set        */
00272 /* - ADC channels: set each ADC channel ending mode                           */
00273 #define ADC_SINGLEDIFF_CALIB_START_MASK    (ADC_CR_ADCALDIF)
00274 #define ADC_SINGLEDIFF_CALIB_FACTOR_MASK   (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
00275 #define ADC_SINGLEDIFF_CHANNEL_MASK        (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
00276 #define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK  (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen to perform of shift when single mode is selected, shift value out of channels bits range. */
00277 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK   (0x00010000UL)                           /* Selection of 1 bit to discriminate differential mode: mask of bit */
00278 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS    (16UL)                                   /* Selection of 1 bit to discriminate differential mode: position of bit */
00279 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a shift of 4 ranks */
00280
00281 /* Internal mask for ADC analog watchdog:                                     */
00282 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for:     */
00283 /* (concatenation of multiple bits used in different analog watchdogs,        */
00284 /* (feature of several watchdogs not available on all STM32 families)).       */
00285 /* - analog watchdog 1: monitored channel defined by number,                  */
00286 /*   selection of ADC group (ADC groups regular and-or injected).             */
00287 /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no       */
00288 /*   selection on groups.                                                     */
00289
00290 /* Internal register offset for ADC analog watchdog channel configuration */
00291 #define ADC_AWD_CR1_REGOFFSET              (0x00000000UL)
00292 #define ADC_AWD_CR2_REGOFFSET              (0x00100000UL)
00293 #define ADC_AWD_CR3_REGOFFSET              (0x00200000UL)
00294
00295 /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
00296 /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
00297 #define ADC_AWD_CR12_REGOFFSETGAP_MASK     (ADC_AWD2CR_AWD2CH_0)
00298 #define ADC_AWD_CR12_REGOFFSETGAP_VAL      (0x00000024UL)
00299
00300 #define ADC_AWD_CRX_REGOFFSET_MASK         (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
00301
00302 #define ADC_AWD_CR1_CHANNEL_MASK           (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
00303 #define ADC_AWD_CR23_CHANNEL_MASK          (ADC_AWD2CR_AWD2CH)
00304 #define ADC_AWD_CR_ALL_CHANNEL_MASK        (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
00305
00306 #define ADC_AWD_CRX_REGOFFSET_POS          (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */
00307
00308 /* Internal register offset for ADC analog watchdog threshold configuration */
00309 #define ADC_AWD_TR1_REGOFFSET              (ADC_AWD_CR1_REGOFFSET)
00310 #define ADC_AWD_TR2_REGOFFSET              (ADC_AWD_CR2_REGOFFSET)
00311 #define ADC_AWD_TR3_REGOFFSET              (ADC_AWD_CR3_REGOFFSET)
00312 #define ADC_AWD_TRX_REGOFFSET_MASK         (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
00313 #define ADC_AWD_TRX_REGOFFSET_POS          (ADC_AWD_CRX_REGOFFSET_POS)     /* Position of bits ADC_SQRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */
00314 #define ADC_AWD_TRX_BIT_HIGH_MASK          (0x00010000UL)                   /* Selection of 1 bit to discriminate threshold high: mask of bit */
00315 #define ADC_AWD_TRX_BIT_HIGH_POS           (16UL)                           /* Selection of 1 bit to discriminate threshold high: position of bit */
00316 #define ADC_AWD_TRX_BIT_HIGH_SHIFT4        (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */
00317
00318 /* Internal mask for ADC offset:                                              */
00319 /* Internal register offset for ADC offset number configuration */
00320 #define ADC_OFR1_REGOFFSET                 (0x00000000UL)
00321 #define ADC_OFR2_REGOFFSET                 (0x00000001UL)
00322 #define ADC_OFR3_REGOFFSET                 (0x00000002UL)
00323 #define ADC_OFR4_REGOFFSET                 (0x00000003UL)
00324 #define ADC_OFRx_REGOFFSET_MASK            (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
00325
00326
00327 /* ADC registers bits positions */
00328 #define ADC_CFGR_RES_BITOFFSET_POS         ( 3UL) /* Value equivalent to bitfield "ADC_CFGR_RES" position in register */
00329 #define ADC_CFGR_AWD1SGL_BITOFFSET_POS     (22UL) /* Value equivalent to bitfield "ADC_CFGR_AWD1SGL" position in register */
00330 #define ADC_CFGR_AWD1EN_BITOFFSET_POS      (23UL) /* Value equivalent to bitfield "ADC_CFGR_AWD1EN" position in register */
00331 #define ADC_CFGR_JAWD1EN_BITOFFSET_POS     (24UL) /* Value equivalent to bitfield "ADC_CFGR_JAWD1EN" position in register */
00332 #define ADC_TR1_HT1_BITOFFSET_POS          (16UL) /* Value equivalent to bitfield "ADC_TR1_HT1" position in register */
00333
00334
00335 /* ADC registers bits groups */
00336 #define ADC_CR_BITS_PROPERTY_RS            (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
00337
00338
00339 /* ADC internal channels related definitions */
00340 /* Internal voltage reference VrefInt */
00341 #define VREFINT_CAL_ADDR                   ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, address of parameter VREFINT: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.6 V (tolerance: +-10 mV). */
00342 #define VREFINT_CAL_VREF                   (3600UL)                     /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
00343 /* Temperature sensor */
00344 #define TEMPSENSOR_CAL1_ADDR               ((uint16_t*) (0x1FFF75A8UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32WB, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
00345 #define TEMPSENSOR_CAL2_ADDR               ((uint16_t*) (0x1FFF75CAUL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32WB, temperature sensor ADC raw data acquired at temperature 130 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
00346 #define TEMPSENSOR_CAL1_TEMP               (30L)                        /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
00347 #define TEMPSENSOR_CAL2_TEMP               (130L)                       /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
00348 #define TEMPSENSOR_CAL_VREFANALOG          (3000UL)                     /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
00349
00350
00351 /**
00352   * @}
00353   */
00354
00355
00356 /* Private macros ------------------------------------------------------------*/
00357 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
00358   * @{
00359   */
00360
00361 /**
00362   * @brief  Driver macro reserved for internal use: set a pointer to
00363   *         a register from a register basis from which an offset
00364   *         is applied.
00365   * @param  __REG__ Register basis from which the offset is applied.
00366   * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).
00367   * @retval Pointer to register address
00368   */
00369 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \
00370   ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
00371
00372 /**
00373   * @}
00374   */
00375
00376
00377 /* Exported types ------------------------------------------------------------*/
00378 #if defined(USE_FULL_LL_DRIVER)
00379 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
00380   * @{
00381   */
00382
00383 /**
00384   * @brief  Structure definition of some features of ADC common parameters
00385   *         and multimode
00386   *         (all ADC instances belonging to the same ADC common instance).
00387   * @note   The setting of these parameters by function @ref LL_ADC_CommonInit()
00388   *         is conditioned to ADC instances state (all ADC instances
00389   *         sharing the same ADC common instance):
00390   *         All ADC instances sharing the same ADC common instance must be
00391   *         disabled.
00392   */
00393 typedef struct
00394 {
00395   uint32_t CommonClock;                 /*!< Set parameter common to several ADC: Clock source and prescaler.
00396                                              This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
00397                                              @note On this STM32 serie, if ADC group injected is used, some
00398                                                    clock ratio constraints between ADC clock and AHB clock
00399                                                    must be respected. Refer to reference manual.
00400
00401                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
00402
00403 } LL_ADC_CommonInitTypeDef;
00404
00405 /**
00406   * @brief  Structure definition of some features of ADC instance.
00407   * @note   These parameters have an impact on ADC scope: ADC instance.
00408   *         Affects both group regular and group injected (availability
00409   *         of ADC group injected depends on STM32 families).
00410   *         Refer to corresponding unitary functions into
00411   *         @ref ADC_LL_EF_Configuration_ADC_Instance .
00412   * @note   The setting of these parameters by function @ref LL_ADC_Init()
00413   *         is conditioned to ADC state:
00414   *         ADC instance must be disabled.
00415   *         This condition is applied to all ADC features, for efficiency
00416   *         and compatibility over all STM32 families. However, the different
00417   *         features can be set under different ADC state conditions
00418   *         (setting possible with ADC enabled without conversion on going,
00419   *         ADC enabled with conversion on going, ...)
00420   *         Each feature can be updated afterwards with a unitary function
00421   *         and potentially with ADC in a different state than disabled,
00422   *         refer to description of each function for setting
00423   *         conditioned to ADC state.
00424   */
00425 typedef struct
00426 {
00427   uint32_t Resolution;                  /*!< Set ADC resolution.
00428                                              This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
00429
00430                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
00431
00432   uint32_t DataAlignment;               /*!< Set ADC conversion data alignment.
00433                                              This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
00434
00435                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
00436
00437   uint32_t LowPowerMode;                /*!< Set ADC low power mode.
00438                                              This parameter can be a value of @ref ADC_LL_EC_LP_MODE
00439
00440                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */
00441
00442 } LL_ADC_InitTypeDef;
00443
00444 /**
00445   * @brief  Structure definition of some features of ADC group regular.
00446   * @note   These parameters have an impact on ADC scope: ADC group regular.
00447   *         Refer to corresponding unitary functions into
00448   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
00449   *         (functions with prefix "REG").
00450   * @note   The setting of these parameters by function @ref LL_ADC_REG_Init()
00451   *         is conditioned to ADC state:
00452   *         ADC instance must be disabled.
00453   *         This condition is applied to all ADC features, for efficiency
00454   *         and compatibility over all STM32 families. However, the different
00455   *         features can be set under different ADC state conditions
00456   *         (setting possible with ADC enabled without conversion on going,
00457   *         ADC enabled with conversion on going, ...)
00458   *         Each feature can be updated afterwards with a unitary function
00459   *         and potentially with ADC in a different state than disabled,
00460   *         refer to description of each function for setting
00461   *         conditioned to ADC state.
00462   */
00463 typedef struct
00464 {
00465   uint32_t TriggerSource;               /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
00466                                              This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
00467                                              @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
00468                                                    (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
00469                                                    In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
00470
00471                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
00472
00473   uint32_t SequencerLength;             /*!< Set ADC group regular sequencer length.
00474                                              This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
00475
00476                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
00477
00478   uint32_t SequencerDiscont;            /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
00479                                              This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
00480                                              @note This parameter has an effect only if group regular sequencer is enabled
00481                                                    (scan length of 2 ranks or more).
00482
00483                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
00484
00485   uint32_t ContinuousMode;              /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
00486                                              This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
00487                                              Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
00488
00489                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
00490
00491   uint32_t DMATransfer;                 /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
00492                                              This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
00493
00494                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
00495
00496   uint32_t Overrun;                     /*!< Set ADC group regular behavior in case of overrun:
00497                                              data preserved or overwritten.
00498                                              This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
00499
00500                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */
00501
00502 } LL_ADC_REG_InitTypeDef;
00503
00504 /**
00505   * @brief  Structure definition of some features of ADC group injected.
00506   * @note   These parameters have an impact on ADC scope: ADC group injected.
00507   *         Refer to corresponding unitary functions into
00508   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
00509   *         (functions with prefix "INJ").
00510   * @note   The setting of these parameters by function @ref LL_ADC_INJ_Init()
00511   *         is conditioned to ADC state:
00512   *         ADC instance must be disabled.
00513   *         This condition is applied to all ADC features, for efficiency
00514   *         and compatibility over all STM32 families. However, the different
00515   *         features can be set under different ADC state conditions
00516   *         (setting possible with ADC enabled without conversion on going,
00517   *         ADC enabled with conversion on going, ...)
00518   *         Each feature can be updated afterwards with a unitary function
00519   *         and potentially with ADC in a different state than disabled,
00520   *         refer to description of each function for setting
00521   *         conditioned to ADC state.
00522   */
00523 typedef struct
00524 {
00525   uint32_t TriggerSource;               /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
00526                                              This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
00527                                              @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
00528                                                    (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
00529                                                    In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge().
00530
00531                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
00532
00533   uint32_t SequencerLength;             /*!< Set ADC group injected sequencer length.
00534                                              This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
00535
00536                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
00537
00538   uint32_t SequencerDiscont;            /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
00539                                              This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
00540                                              @note This parameter has an effect only if group injected sequencer is enabled
00541                                                    (scan length of 2 ranks or more).
00542
00543                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
00544
00545   uint32_t TrigAuto;                    /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
00546                                              This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
00547                                              Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
00548
00549                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
00550
00551 } LL_ADC_INJ_InitTypeDef;
00552
00553 /**
00554   * @}
00555   */
00556 #endif /* USE_FULL_LL_DRIVER */
00557
00558 /* Exported constants --------------------------------------------------------*/
00559 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
00560   * @{
00561   */
00562
00563 /** @defgroup ADC_LL_EC_FLAG ADC flags
00564   * @brief    Flags defines which can be used with LL_ADC_ReadReg function
00565   * @{
00566   */
00567 #define LL_ADC_FLAG_ADRDY                  ADC_ISR_ADRDY      /*!< ADC flag ADC instance ready */
00568 #define LL_ADC_FLAG_EOC                    ADC_ISR_EOC        /*!< ADC flag ADC group regular end of unitary conversion */
00569 #define LL_ADC_FLAG_EOS                    ADC_ISR_EOS        /*!< ADC flag ADC group regular end of sequence conversions */
00570 #define LL_ADC_FLAG_OVR                    ADC_ISR_OVR        /*!< ADC flag ADC group regular overrun */
00571 #define LL_ADC_FLAG_EOSMP                  ADC_ISR_EOSMP      /*!< ADC flag ADC group regular end of sampling phase */
00572 #define LL_ADC_FLAG_JEOC                   ADC_ISR_JEOC       /*!< ADC flag ADC group injected end of unitary conversion */
00573 #define LL_ADC_FLAG_JEOS                   ADC_ISR_JEOS       /*!< ADC flag ADC group injected end of sequence conversions */
00574 #define LL_ADC_FLAG_JQOVF                  ADC_ISR_JQOVF      /*!< ADC flag ADC group injected contexts queue overflow */
00575 #define LL_ADC_FLAG_AWD1                   ADC_ISR_AWD1       /*!< ADC flag ADC analog watchdog 1 */
00576 #define LL_ADC_FLAG_AWD2                   ADC_ISR_AWD2       /*!< ADC flag ADC analog watchdog 2 */
00577 #define LL_ADC_FLAG_AWD3                   ADC_ISR_AWD3       /*!< ADC flag ADC analog watchdog 3 */
00578 /**
00579   * @}
00580   */
00581
00582 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
00583   * @brief    IT defines which can be used with LL_ADC_ReadReg and  LL_ADC_WriteReg functions
00584   * @{
00585   */
00586 #define LL_ADC_IT_ADRDY                    ADC_IER_ADRDYIE    /*!< ADC interruption ADC instance ready */
00587 #define LL_ADC_IT_EOC                      ADC_IER_EOCIE      /*!< ADC interruption ADC group regular end of unitary conversion */
00588 #define LL_ADC_IT_EOS                      ADC_IER_EOSIE      /*!< ADC interruption ADC group regular end of sequence conversions */
00589 #define LL_ADC_IT_OVR                      ADC_IER_OVRIE      /*!< ADC interruption ADC group regular overrun */
00590 #define LL_ADC_IT_EOSMP                    ADC_IER_EOSMPIE    /*!< ADC interruption ADC group regular end of sampling phase */
00591 #define LL_ADC_IT_JEOC                     ADC_IER_JEOCIE     /*!< ADC interruption ADC group injected end of unitary conversion */
00592 #define LL_ADC_IT_JEOS                     ADC_IER_JEOSIE     /*!< ADC interruption ADC group injected end of sequence conversions */
00593 #define LL_ADC_IT_JQOVF                    ADC_IER_JQOVFIE    /*!< ADC interruption ADC group injected contexts queue overflow */
00594 #define LL_ADC_IT_AWD1                     ADC_IER_AWD1IE     /*!< ADC interruption ADC analog watchdog 1 */
00595 #define LL_ADC_IT_AWD2                     ADC_IER_AWD2IE     /*!< ADC interruption ADC analog watchdog 2 */
00596 #define LL_ADC_IT_AWD3                     ADC_IER_AWD3IE     /*!< ADC interruption ADC analog watchdog 3 */
00597 /**
00598   * @}
00599   */
00600
00601 /** @defgroup ADC_LL_EC_REGISTERS  ADC registers compliant with specific purpose
00602   * @{
00603   */
00604 /* List of ADC registers intended to be used (most commonly) with             */
00605 /* DMA transfer.                                                              */
00606 /* Refer to function @ref LL_ADC_DMA_GetRegAddr().                            */
00607 #define LL_ADC_DMA_REG_REGULAR_DATA          (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
00608 /**
00609   * @}
00610   */
00611
00612 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE  ADC common - Clock source
00613   * @{
00614   */
00615 #define LL_ADC_CLOCK_SYNC_PCLK_DIV1        (ADC_CCR_CKMODE_0)                                    /*!< ADC synchronous clock derived from AHB clock without prescaler */
00616 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2        (ADC_CCR_CKMODE_1                   )                 /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
00617 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4        (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0)                 /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
00618 #define LL_ADC_CLOCK_ASYNC_DIV1            (0x00000000UL)                                        /*!< ADC asynchronous clock without prescaler */
00619 #define LL_ADC_CLOCK_ASYNC_DIV2            (ADC_CCR_PRESC_0)                                     /*!< ADC asynchronous clock with prescaler division by 2   */
00620 #define LL_ADC_CLOCK_ASYNC_DIV4            (ADC_CCR_PRESC_1                  )                   /*!< ADC asynchronous clock with prescaler division by 4   */
00621 #define LL_ADC_CLOCK_ASYNC_DIV6            (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)                   /*!< ADC asynchronous clock with prescaler division by 6   */
00622 #define LL_ADC_CLOCK_ASYNC_DIV8            (ADC_CCR_PRESC_2                                    ) /*!< ADC asynchronous clock with prescaler division by 8   */
00623 #define LL_ADC_CLOCK_ASYNC_DIV10           (ADC_CCR_PRESC_2                   | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 10  */
00624 #define LL_ADC_CLOCK_ASYNC_DIV12           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1                  ) /*!< ADC asynchronous clock with prescaler division by 12  */
00625 #define LL_ADC_CLOCK_ASYNC_DIV16           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16  */
00626 #define LL_ADC_CLOCK_ASYNC_DIV32           (ADC_CCR_PRESC_3)                                     /*!< ADC asynchronous clock with prescaler division by 32  */
00627 #define LL_ADC_CLOCK_ASYNC_DIV64           (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0)                   /*!< ADC asynchronous clock with prescaler division by 64  */
00628 #define LL_ADC_CLOCK_ASYNC_DIV128          (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1)                   /*!< ADC asynchronous clock with prescaler division by 128 */
00629 #define LL_ADC_CLOCK_ASYNC_DIV256          (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256 */
00630 /**
00631   * @}
00632   */
00633
00634 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL  ADC common - Measurement path to internal channels
00635   * @{
00636   */
00637 /* Note: Other measurement paths to internal channels may be available        */
00638 /*       (connections to other peripherals).                                  */
00639 /*       If they are not listed below, they do not require any specific       */
00640 /*       path enable. In this case, Access to measurement path is done        */
00641 /*       only by selecting the corresponding ADC internal channel.            */
00642 #define LL_ADC_PATH_INTERNAL_NONE          (0x00000000UL)         /*!< ADC measurement pathes all disabled */
00643 #define LL_ADC_PATH_INTERNAL_VREFINT       (ADC_CCR_VREFEN)       /*!< ADC measurement path to internal channel VrefInt */
00644 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR    (ADC_CCR_TSEN)         /*!< ADC measurement path to internal channel temperature sensor */
00645 #define LL_ADC_PATH_INTERNAL_VBAT          (ADC_CCR_VBATEN)       /*!< ADC measurement path to internal channel Vbat */
00646 /**
00647   * @}
00648   */
00649
00650 /** @defgroup ADC_LL_EC_RESOLUTION  ADC instance - Resolution
00651   * @{
00652   */
00653 #define LL_ADC_RESOLUTION_12B              (0x00000000UL)                      /*!< ADC resolution 12 bits */
00654 #define LL_ADC_RESOLUTION_10B              (                 ADC_CFGR_RES_0)   /*!< ADC resolution 10 bits */
00655 #define LL_ADC_RESOLUTION_8B               (ADC_CFGR_RES_1                 )   /*!< ADC resolution  8 bits */
00656 #define LL_ADC_RESOLUTION_6B               (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)   /*!< ADC resolution  6 bits */
00657 /**
00658   * @}
00659   */
00660
00661 /** @defgroup ADC_LL_EC_DATA_ALIGN  ADC instance - Data alignment
00662   * @{
00663   */
00664 #define LL_ADC_DATA_ALIGN_RIGHT            (0x00000000UL)         /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
00665 #define LL_ADC_DATA_ALIGN_LEFT             (ADC_CFGR_ALIGN)       /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
00666 /**
00667   * @}
00668   */
00669
00670 /** @defgroup ADC_LL_EC_LP_MODE  ADC instance - Low power mode
00671   * @{
00672   */
00673 #define LL_ADC_LP_MODE_NONE                (0x00000000UL)                      /*!< No ADC low power mode activated */
00674 #define LL_ADC_LP_AUTOWAIT                 (ADC_CFGR_AUTDLY)                   /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
00675 /**
00676   * @}
00677   */
00678
00679 /** @defgroup ADC_LL_EC_OFFSET_NB  ADC instance - Offset number
00680   * @{
00681   */
00682 #define LL_ADC_OFFSET_1                    ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
00683 #define LL_ADC_OFFSET_2                    ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
00684 #define LL_ADC_OFFSET_3                    ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
00685 #define LL_ADC_OFFSET_4                    ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
00686 /**
00687   * @}
00688   */
00689
00690 /** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state
00691   * @{
00692   */
00693 #define LL_ADC_OFFSET_DISABLE              (0x00000000UL)         /*!< ADC offset disabled (among ADC selected offset number 1, 2, 3 or 4) */
00694 #define LL_ADC_OFFSET_ENABLE               (ADC_OFR1_OFFSET1_EN)  /*!< ADC offset enabled (among ADC selected offset number 1, 2, 3 or 4) */
00695 /**
00696   * @}
00697   */
00698
00699 /** @defgroup ADC_LL_EC_GROUPS  ADC instance - Groups
00700   * @{
00701   */
00702 #define LL_ADC_GROUP_REGULAR               (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */
00703 #define LL_ADC_GROUP_INJECTED              (0x00000002UL) /*!< ADC group injected (not available on all STM32 devices)*/
00704 #define LL_ADC_GROUP_REGULAR_INJECTED      (0x00000003UL) /*!< ADC both groups regular and injected */
00705 /**
00706   * @}
00707   */
00708
00709 /** @defgroup ADC_LL_EC_CHANNEL  ADC instance - Channel number
00710   * @{
00711   */
00712 #define LL_ADC_CHANNEL_0                   (ADC_CHANNEL_0_NUMBER  | ADC_CHANNEL_0_SMP  | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0  */
00713 #define LL_ADC_CHANNEL_1                   (ADC_CHANNEL_1_NUMBER  | ADC_CHANNEL_1_SMP  | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1  */
00714 #define LL_ADC_CHANNEL_2                   (ADC_CHANNEL_2_NUMBER  | ADC_CHANNEL_2_SMP  | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2  */
00715 #define LL_ADC_CHANNEL_3                   (ADC_CHANNEL_3_NUMBER  | ADC_CHANNEL_3_SMP  | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3  */
00716 #define LL_ADC_CHANNEL_4                   (ADC_CHANNEL_4_NUMBER  | ADC_CHANNEL_4_SMP  | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4  */
00717 #define LL_ADC_CHANNEL_5                   (ADC_CHANNEL_5_NUMBER  | ADC_CHANNEL_5_SMP  | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5  */
00718 #define LL_ADC_CHANNEL_6                   (ADC_CHANNEL_6_NUMBER  | ADC_CHANNEL_6_SMP  | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6  */
00719 #define LL_ADC_CHANNEL_7                   (ADC_CHANNEL_7_NUMBER  | ADC_CHANNEL_7_SMP  | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7  */
00720 #define LL_ADC_CHANNEL_8                   (ADC_CHANNEL_8_NUMBER  | ADC_CHANNEL_8_SMP  | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8  */
00721 #define LL_ADC_CHANNEL_9                   (ADC_CHANNEL_9_NUMBER  | ADC_CHANNEL_9_SMP  | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9  */
00722 #define LL_ADC_CHANNEL_10                  (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
00723 #define LL_ADC_CHANNEL_11                  (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
00724 #define LL_ADC_CHANNEL_12                  (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
00725 #define LL_ADC_CHANNEL_13                  (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
00726 #define LL_ADC_CHANNEL_14                  (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
00727 #define LL_ADC_CHANNEL_15                  (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
00728 #define LL_ADC_CHANNEL_16                  (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
00729 #define LL_ADC_CHANNEL_17                  (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
00730 #define LL_ADC_CHANNEL_18                  (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
00731 #define LL_ADC_CHANNEL_VREFINT             (LL_ADC_CHANNEL_0  | ADC_CHANNEL_ID_INTERNAL_CH)  /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */
00732 #define LL_ADC_CHANNEL_TEMPSENSOR          (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH)  /*!< ADC internal channel connected to Temperature sensor. */
00733 #define LL_ADC_CHANNEL_VBAT                (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH)  /*!< ADC internal channel connected to Vbat/2: Vbat voltage through a divider ladder of factor 1/2 to have Vbat always below Vdda. */
00734 /**
00735   * @}
00736   */
00737
00738 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE  ADC group regular - Trigger source
00739   * @{
00740   */
00741 #define LL_ADC_REG_TRIG_SOFTWARE           (0x00000000UL)                                                                                                  /*!< ADC group regular conversion trigger internal: SW start. */
00742 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
00743 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2     (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
00744 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1       (ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                                                 /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00745 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2       (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00746 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3       (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00747 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                     /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
00748 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2       (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00749 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11    (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */
00750 /**
00751   * @}
00752   */
00753
00754 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE  ADC group regular - Trigger edge
00755   * @{
00756   */
00757 #define LL_ADC_REG_TRIG_EXT_RISING         (                   ADC_CFGR_EXTEN_0)   /*!< ADC group regular conversion trigger polarity set to rising edge */
00758 #define LL_ADC_REG_TRIG_EXT_FALLING        (ADC_CFGR_EXTEN_1                   )   /*!< ADC group regular conversion trigger polarity set to falling edge */
00759 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING  (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0)   /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
00760 /**
00761   * @}
00762   */
00763
00764 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE  ADC group regular - Continuous mode
00765   * @{
00766   */
00767 #define LL_ADC_REG_CONV_SINGLE             (0x00000000UL)          /*!< ADC conversions are performed in single mode: one conversion per trigger */
00768 #define LL_ADC_REG_CONV_CONTINUOUS         (ADC_CFGR_CONT)         /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
00769 /**
00770   * @}
00771   */
00772
00773 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER  ADC group regular - DMA transfer of ADC conversion data
00774   * @{
00775   */
00776 #define LL_ADC_REG_DMA_TRANSFER_NONE       (0x00000000UL)                        /*!< ADC conversions are not transferred by DMA */
00777 #define LL_ADC_REG_DMA_TRANSFER_LIMITED    (                  ADC_CFGR_DMAEN)    /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
00778 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED  (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN)    /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
00779 /**
00780   * @}
00781   */
00782
00783
00784
00785 /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR  ADC group regular - Overrun behavior on conversion data
00786   * @{
00787   */
00788 #define LL_ADC_REG_OVR_DATA_PRESERVED      (0x00000000UL)         /*!< ADC group regular behavior in case of overrun: data preserved */
00789 #define LL_ADC_REG_OVR_DATA_OVERWRITTEN    (ADC_CFGR_OVRMOD)      /*!< ADC group regular behavior in case of overrun: data overwritten */
00790 /**
00791   * @}
00792   */
00793
00794 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH  ADC group regular - Sequencer scan length
00795   * @{
00796   */
00797 #define LL_ADC_REG_SEQ_SCAN_DISABLE        (0x00000000UL)                                              /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
00798 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS  (                                             ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
00799 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS  (                              ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
00800 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS  (                              ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
00801 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS  (               ADC_SQR1_L_2                              ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
00802 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS  (               ADC_SQR1_L_2                | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
00803 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
00804 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
00805 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS  (ADC_SQR1_L_3                                             ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
00806 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3                               | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
00807 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
00808 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
00809 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                              ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
00810 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
00811 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
00812 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
00813 /**
00814   * @}
00815   */
00816
00817 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE  ADC group regular - Sequencer discontinuous mode
00818   * @{
00819   */
00820 #define LL_ADC_REG_SEQ_DISCONT_DISABLE     (0x00000000UL)                                                               /*!< ADC group regular sequencer discontinuous mode disable */
00821 #define LL_ADC_REG_SEQ_DISCONT_1RANK       (                                                               ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
00822 #define LL_ADC_REG_SEQ_DISCONT_2RANKS      (                                          ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
00823 #define LL_ADC_REG_SEQ_DISCONT_3RANKS      (                     ADC_CFGR_DISCNUM_1                      | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
00824 #define LL_ADC_REG_SEQ_DISCONT_4RANKS      (                     ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
00825 #define LL_ADC_REG_SEQ_DISCONT_5RANKS      (ADC_CFGR_DISCNUM_2                                           | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
00826 #define LL_ADC_REG_SEQ_DISCONT_6RANKS      (ADC_CFGR_DISCNUM_2                      | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
00827 #define LL_ADC_REG_SEQ_DISCONT_7RANKS      (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1                      | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
00828 #define LL_ADC_REG_SEQ_DISCONT_8RANKS      (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
00829 /**
00830   * @}
00831   */
00832
00833 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS  ADC group regular - Sequencer ranks
00834   * @{
00835   */
00836 #define LL_ADC_REG_RANK_1                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 1 */
00837 #define LL_ADC_REG_RANK_2                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 2 */
00838 #define LL_ADC_REG_RANK_3                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 3 */
00839 #define LL_ADC_REG_RANK_4                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 4 */
00840 #define LL_ADC_REG_RANK_5                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 5 */
00841 #define LL_ADC_REG_RANK_6                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 6 */
00842 #define LL_ADC_REG_RANK_7                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 7 */
00843 #define LL_ADC_REG_RANK_8                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 8 */
00844 #define LL_ADC_REG_RANK_9                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 9 */
00845 #define LL_ADC_REG_RANK_10                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
00846 #define LL_ADC_REG_RANK_11                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
00847 #define LL_ADC_REG_RANK_12                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
00848 #define LL_ADC_REG_RANK_13                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
00849 #define LL_ADC_REG_RANK_14                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
00850 #define LL_ADC_REG_RANK_15                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
00851 #define LL_ADC_REG_RANK_16                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
00852 /**
00853   * @}
00854   */
00855
00856 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE  ADC group injected - Trigger source
00857   * @{
00858   */
00859 #define LL_ADC_INJ_TRIG_SOFTWARE           (0x00000000UL)                                                                                                      /*!< ADC group injected conversion trigger internal: SW start.. Trigger edge set to rising edge (default setting). */
00860 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO      (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                                     /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
00861 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2     (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
00862 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4       (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00863 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO      (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
00864 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1       (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00865 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15    (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */
00866 /**
00867   * @}
00868   */
00869
00870 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE  ADC group injected - Trigger edge
00871   * @{
00872   */
00873 #define LL_ADC_INJ_TRIG_EXT_RISING         (                    ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */
00874 #define LL_ADC_INJ_TRIG_EXT_FALLING        (ADC_JSQR_JEXTEN_1                    ) /*!< ADC group injected conversion trigger polarity set to falling edge */
00875 #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING  (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
00876 /**
00877   * @}
00878   */
00879
00880 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO  ADC group injected - Automatic trigger mode
00881   * @{
00882   */
00883 #define LL_ADC_INJ_TRIG_INDEPENDENT        (0x00000000UL)         /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
00884 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR   (ADC_CFGR_JAUTO)       /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on  ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
00885 /**
00886   * @}
00887   */
00888
00889 /** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE  ADC group injected - Context queue mode
00890   * @{
00891   */
00892 #define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL)         /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */
00893 #define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY   (ADC_CFGR_JQM)         /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */
00894 #define LL_ADC_INJ_QUEUE_DISABLE               (ADC_CFGR_JQDIS)       /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */
00895 /**
00896   * @}
00897   */
00898
00899 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH  ADC group injected - Sequencer scan length
00900   * @{
00901   */
00902 #define LL_ADC_INJ_SEQ_SCAN_DISABLE        (0x00000000UL)                  /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
00903 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS  (                ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
00904 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS  (ADC_JSQR_JL_1                ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
00905 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS  (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
00906 /**
00907   * @}
00908   */
00909
00910 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE  ADC group injected - Sequencer discontinuous mode
00911   * @{
00912   */
00913 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE     (0x00000000UL)         /*!< ADC group injected sequencer discontinuous mode disable */
00914 #define LL_ADC_INJ_SEQ_DISCONT_1RANK       (ADC_CFGR_JDISCEN)     /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
00915 /**
00916   * @}
00917   */
00918
00919 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS  ADC group injected - Sequencer ranks
00920   * @{
00921   */
00922 #define LL_ADC_INJ_RANK_1                  (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */
00923 #define LL_ADC_INJ_RANK_2                  (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */
00924 #define LL_ADC_INJ_RANK_3                  (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */
00925 #define LL_ADC_INJ_RANK_4                  (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */
00926 /**
00927   * @}
00928   */
00929
00930 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME  Channel - Sampling time
00931   * @{
00932   */
00933 #define LL_ADC_SAMPLINGTIME_2CYCLES_5      (0x00000000UL)                                              /*!< Sampling time 2.5 ADC clock cycles */
00934 #define LL_ADC_SAMPLINGTIME_6CYCLES_5      (                                        ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles */
00935 #define LL_ADC_SAMPLINGTIME_12CYCLES_5     (                    ADC_SMPR2_SMP10_1                    ) /*!< Sampling time 12.5 ADC clock cycles */
00936 #define LL_ADC_SAMPLINGTIME_24CYCLES_5     (                    ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 24.5 ADC clock cycles */
00937 #define LL_ADC_SAMPLINGTIME_47CYCLES_5     (ADC_SMPR2_SMP10_2                                        ) /*!< Sampling time 47.5 ADC clock cycles */
00938 #define LL_ADC_SAMPLINGTIME_92CYCLES_5     (ADC_SMPR2_SMP10_2                     | ADC_SMPR2_SMP10_0) /*!< Sampling time 92.5 ADC clock cycles */
00939 #define LL_ADC_SAMPLINGTIME_247CYCLES_5    (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1                    ) /*!< Sampling time 247.5 ADC clock cycles */
00940 #define LL_ADC_SAMPLINGTIME_640CYCLES_5    (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 640.5 ADC clock cycles */
00941 /**
00942   * @}
00943   */
00944
00945 /** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING  Channel - Single or differential ending
00946   * @{
00947   */
00948 #define LL_ADC_SINGLE_ENDED                (                  ADC_CALFACT_CALFACT_S)         /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
00949 #define LL_ADC_DIFFERENTIAL_ENDED          (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D)         /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
00950 #define LL_ADC_BOTH_SINGLE_DIFF_ENDED      (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */
00951 /**
00952   * @}
00953   */
00954
00955 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
00956   * @{
00957   */
00958 #define LL_ADC_AWD1                        (ADC_AWD_CR1_CHANNEL_MASK  | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
00959 #define LL_ADC_AWD2                        (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
00960 #define LL_ADC_AWD3                        (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
00961 /**
00962   * @}
00963   */
00964
00965 /** @defgroup ADC_LL_EC_AWD_CHANNELS  Analog watchdog - Monitored channels
00966   * @{
00967   */
00968 #define LL_ADC_AWD_DISABLE                 (0x00000000UL)                                                                                      /*!< ADC analog watchdog monitoring disabled */
00969 #define LL_ADC_AWD_ALL_CHANNELS_REG        (ADC_AWD_CR23_CHANNEL_MASK                                    | ADC_CFGR_AWD1EN                   ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
00970 #define LL_ADC_AWD_ALL_CHANNELS_INJ        (ADC_AWD_CR23_CHANNEL_MASK                 | ADC_CFGR_JAWD1EN                                     ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
00971 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ    (ADC_AWD_CR23_CHANNEL_MASK                 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN                   ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
00972 #define LL_ADC_AWD_CHANNEL_0_REG           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
00973 #define LL_ADC_AWD_CHANNEL_0_INJ           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
00974 #define LL_ADC_AWD_CHANNEL_0_REG_INJ       ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
00975 #define LL_ADC_AWD_CHANNEL_1_REG           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
00976 #define LL_ADC_AWD_CHANNEL_1_INJ           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
00977 #define LL_ADC_AWD_CHANNEL_1_REG_INJ       ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
00978 #define LL_ADC_AWD_CHANNEL_2_REG           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
00979 #define LL_ADC_AWD_CHANNEL_2_INJ           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
00980 #define LL_ADC_AWD_CHANNEL_2_REG_INJ       ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
00981 #define LL_ADC_AWD_CHANNEL_3_REG           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
00982 #define LL_ADC_AWD_CHANNEL_3_INJ           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
00983 #define LL_ADC_AWD_CHANNEL_3_REG_INJ       ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
00984 #define LL_ADC_AWD_CHANNEL_4_REG           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
00985 #define LL_ADC_AWD_CHANNEL_4_INJ           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
00986 #define LL_ADC_AWD_CHANNEL_4_REG_INJ       ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
00987 #define LL_ADC_AWD_CHANNEL_5_REG           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
00988 #define LL_ADC_AWD_CHANNEL_5_INJ           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
00989 #define LL_ADC_AWD_CHANNEL_5_REG_INJ       ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
00990 #define LL_ADC_AWD_CHANNEL_6_REG           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
00991 #define LL_ADC_AWD_CHANNEL_6_INJ           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
00992 #define LL_ADC_AWD_CHANNEL_6_REG_INJ       ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
00993 #define LL_ADC_AWD_CHANNEL_7_REG           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
00994 #define LL_ADC_AWD_CHANNEL_7_INJ           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
00995 #define LL_ADC_AWD_CHANNEL_7_REG_INJ       ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
00996 #define LL_ADC_AWD_CHANNEL_8_REG           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
00997 #define LL_ADC_AWD_CHANNEL_8_INJ           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
00998 #define LL_ADC_AWD_CHANNEL_8_REG_INJ       ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
00999 #define LL_ADC_AWD_CHANNEL_9_REG           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
01000 #define LL_ADC_AWD_CHANNEL_9_INJ           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
01001 #define LL_ADC_AWD_CHANNEL_9_REG_INJ       ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
01002 #define LL_ADC_AWD_CHANNEL_10_REG          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
01003 #define LL_ADC_AWD_CHANNEL_10_INJ          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
01004 #define LL_ADC_AWD_CHANNEL_10_REG_INJ      ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
01005 #define LL_ADC_AWD_CHANNEL_11_REG          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
01006 #define LL_ADC_AWD_CHANNEL_11_INJ          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
01007 #define LL_ADC_AWD_CHANNEL_11_REG_INJ      ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
01008 #define LL_ADC_AWD_CHANNEL_12_REG          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
01009 #define LL_ADC_AWD_CHANNEL_12_INJ          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
01010 #define LL_ADC_AWD_CHANNEL_12_REG_INJ      ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
01011 #define LL_ADC_AWD_CHANNEL_13_REG          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
01012 #define LL_ADC_AWD_CHANNEL_13_INJ          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
01013 #define LL_ADC_AWD_CHANNEL_13_REG_INJ      ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
01014 #define LL_ADC_AWD_CHANNEL_14_REG          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
01015 #define LL_ADC_AWD_CHANNEL_14_INJ          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
01016 #define LL_ADC_AWD_CHANNEL_14_REG_INJ      ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
01017 #define LL_ADC_AWD_CHANNEL_15_REG          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
01018 #define LL_ADC_AWD_CHANNEL_15_INJ          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
01019 #define LL_ADC_AWD_CHANNEL_15_REG_INJ      ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
01020 #define LL_ADC_AWD_CHANNEL_16_REG          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
01021 #define LL_ADC_AWD_CHANNEL_16_INJ          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
01022 #define LL_ADC_AWD_CHANNEL_16_REG_INJ      ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
01023 #define LL_ADC_AWD_CHANNEL_17_REG          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
01024 #define LL_ADC_AWD_CHANNEL_17_INJ          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
01025 #define LL_ADC_AWD_CHANNEL_17_REG_INJ      ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
01026 #define LL_ADC_AWD_CHANNEL_18_REG          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
01027 #define LL_ADC_AWD_CHANNEL_18_INJ          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
01028 #define LL_ADC_AWD_CHANNEL_18_REG_INJ      ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
01029 #define LL_ADC_AWD_CH_VREFINT_REG          ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
01030 #define LL_ADC_AWD_CH_VREFINT_INJ          ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
01031 #define LL_ADC_AWD_CH_VREFINT_REG_INJ      ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
01032 #define LL_ADC_AWD_CH_TEMPSENSOR_REG       ((LL_ADC_CHANNEL_TEMPSENSOR    & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
01033 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ       ((LL_ADC_CHANNEL_TEMPSENSOR    & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
01034 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ   ((LL_ADC_CHANNEL_TEMPSENSOR    & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
01035 #define LL_ADC_AWD_CH_VBAT_REG             ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
01036 #define LL_ADC_AWD_CH_VBAT_INJ             ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */
01037 #define LL_ADC_AWD_CH_VBAT_REG_INJ         ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */
01038 /**
01039   * @}
01040   */
01041
01042 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS  Analog watchdog - Thresholds
01043   * @{
01044   */
01045 #define LL_ADC_AWD_THRESHOLD_HIGH          (ADC_TR1_HT1              ) /*!< ADC analog watchdog threshold high */
01046 #define LL_ADC_AWD_THRESHOLD_LOW           (              ADC_TR1_LT1) /*!< ADC analog watchdog threshold low */
01047 #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW     (ADC_TR1_HT1 | ADC_TR1_LT1) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */
01048 /**
01049   * @}
01050   */
01051
01052 /** @defgroup ADC_LL_EC_OVS_SCOPE  Oversampling - Oversampling scope
01053   * @{
01054   */
01055 #define LL_ADC_OVS_DISABLE                 (0x00000000UL)                                        /*!< ADC oversampling disabled. */
01056 #define LL_ADC_OVS_GRP_REGULAR_CONTINUED   (                                    ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. */
01057 #define LL_ADC_OVS_GRP_REGULAR_RESUMED     (ADC_CFGR2_ROVSM |                   ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
01058 #define LL_ADC_OVS_GRP_INJECTED            (                  ADC_CFGR2_JOVSE                  ) /*!< ADC oversampling on conversions of ADC group injected. */
01059 #define LL_ADC_OVS_GRP_INJ_REG_RESUMED     (                  ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
01060 /**
01061   * @}
01062   */
01063
01064 /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE  Oversampling - Discontinuous mode
01065   * @{
01066   */
01067 #define LL_ADC_OVS_REG_CONT                (0x00000000UL)         /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
01068 #define LL_ADC_OVS_REG_DISCONT             (ADC_CFGR2_TROVS)      /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
01069 /**
01070   * @}
01071   */
01072
01073 /** @defgroup ADC_LL_EC_OVS_RATIO  Oversampling - Ratio
01074   * @{
01075   */
01076 #define LL_ADC_OVS_RATIO_2                 (0x00000000UL)                                           /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
01077 #define LL_ADC_OVS_RATIO_4                 (                                      ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
01078 #define LL_ADC_OVS_RATIO_8                 (                   ADC_CFGR2_OVSR_1                   ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
01079 #define LL_ADC_OVS_RATIO_16                (                   ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
01080 #define LL_ADC_OVS_RATIO_32                (ADC_CFGR2_OVSR_2                                      ) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
01081 #define LL_ADC_OVS_RATIO_64                (ADC_CFGR2_OVSR_2                    | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
01082 #define LL_ADC_OVS_RATIO_128               (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1                   ) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
01083 #define LL_ADC_OVS_RATIO_256               (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
01084 /**
01085   * @}
01086   */
01087
01088 /** @defgroup ADC_LL_EC_OVS_SHIFT  Oversampling - Data shift
01089   * @{
01090   */
01091 #define LL_ADC_OVS_SHIFT_NONE              (0x00000000UL)                                                              /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
01092 #define LL_ADC_OVS_SHIFT_RIGHT_1           (                                                         ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
01093 #define LL_ADC_OVS_SHIFT_RIGHT_2           (                                      ADC_CFGR2_OVSS_1                   ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
01094 #define LL_ADC_OVS_SHIFT_RIGHT_3           (                                      ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
01095 #define LL_ADC_OVS_SHIFT_RIGHT_4           (                   ADC_CFGR2_OVSS_2                                      ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
01096 #define LL_ADC_OVS_SHIFT_RIGHT_5           (                   ADC_CFGR2_OVSS_2                    | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
01097 #define LL_ADC_OVS_SHIFT_RIGHT_6           (                   ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1                   ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
01098 #define LL_ADC_OVS_SHIFT_RIGHT_7           (                   ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
01099 #define LL_ADC_OVS_SHIFT_RIGHT_8           (ADC_CFGR2_OVSS_3                                                         ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
01100 /**
01101   * @}
01102   */
01103
01104
01105 /** @defgroup ADC_LL_EC_HW_DELAYS  Definitions of ADC hardware constraints delays
01106   * @note   Only ADC peripheral HW delays are defined in ADC LL driver driver,
01107   *         not timeout values.
01108   *         For details on delays values, refer to descriptions in source code
01109   *         above each literal definition.
01110   * @{
01111   */
01112
01113 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver,   */
01114 /*       not timeout values.                                                  */
01115 /*       Timeout values for ADC operations are dependent to device clock      */
01116 /*       configuration (system clock versus ADC clock),                       */
01117 /*       and therefore must be defined in user application.                   */
01118 /*       Indications for estimation of ADC timeout delays, for this           */
01119 /*       STM32 serie:                                                         */
01120 /*       - ADC calibration time: maximum delay is 112/fADC.                   */
01121 /*         (refer to device datasheet, parameter "tCAL")                      */
01122 /*       - ADC enable time: maximum delay is 1 conversion cycle.              */
01123 /*         (refer to device datasheet, parameter "tSTAB")                     */
01124 /*       - ADC disable time: maximum delay should be a few ADC clock cycles   */
01125 /*       - ADC stop conversion time: maximum delay should be a few ADC clock  */
01126 /*         cycles                                                             */
01127 /*       - ADC conversion time: duration depending on ADC clock and ADC       */
01128 /*         configuration.                                                     */
01129 /*         (refer to device reference manual, section "Timing")               */
01130
01131 /* Delay for ADC stabilization time (ADC voltage regulator start-up time)     */
01132 /* Delay set to maximum value (refer to device datasheet,                     */
01133 /* parameter "tADCVREG_STUP").                                                */
01134 /* Unit: us                                                                   */
01135 #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 10UL)  /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */
01136
01137 /* Delay for internal voltage reference stabilization time.                   */
01138 /* Delay set to maximum value (refer to device datasheet,                     */
01139 /* parameter "tstart_vrefint").                                               */
01140 /* Unit: us                                                                   */
01141 #define LL_ADC_DELAY_VREFINT_STAB_US       ( 12UL)  /*!< Delay for internal voltage reference stabilization time */
01142
01143 /* Delay for temperature sensor stabilization time.                           */
01144 /* Literal set to maximum value (refer to device datasheet,                   */
01145 /* parameter "tSTART").                                                       */
01146 /* Unit: us                                                                   */
01147 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US    (120UL)  /*!< Delay for temperature sensor stabilization time */
01148
01149 /* Delay required between ADC end of calibration and ADC enable.              */
01150 /* Note: On this STM32 serie, a minimum number of ADC clock cycles            */
01151 /*       are required between ADC end of calibration and ADC enable.          */
01152 /*       Wait time can be computed in user application by waiting for the     */
01153 /*       equivalent number of CPU cycles, by taking into account              */
01154 /*       ratio of CPU clock versus ADC clock prescalers.                      */
01155 /* Unit: ADC clock cycles.                                                    */
01156 #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES (  4UL)  /*!< Delay required between ADC end of calibration and ADC enable */
01157
01158 /**
01159   * @}
01160   */
01161
01162 /**
01163   * @}
01164   */
01165
01166
01167 /* Exported macro ------------------------------------------------------------*/
01168 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
01169   * @{
01170   */
01171
01172 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
01173   * @{
01174   */
01175
01176 /**
01177   * @brief  Write a value in ADC register
01178   * @param  __INSTANCE__ ADC Instance
01179   * @param  __REG__ Register to be written
01180   * @param  __VALUE__ Value to be written in the register
01181   * @retval None
01182   */
01183 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
01184
01185 /**
01186   * @brief  Read a value in ADC register
01187   * @param  __INSTANCE__ ADC Instance
01188   * @param  __REG__ Register to be read
01189   * @retval Register value
01190   */
01191 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
01192 /**
01193   * @}
01194   */
01195
01196 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
01197   * @{
01198   */
01199
01200 /**
01201   * @brief  Helper macro to get ADC channel number in decimal format
01202   *         from literals LL_ADC_CHANNEL_x.
01203   * @note   Example:
01204   *           __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
01205   *           will return decimal number "4".
01206   * @note   The input can be a value from functions where a channel
01207   *         number is returned, either defined with number
01208   *         or with bitfield (only one bit must be set).
01209   * @param  __CHANNEL__ This parameter can be one of the following values:
01210   *         @arg @ref LL_ADC_CHANNEL_0
01211   *         @arg @ref LL_ADC_CHANNEL_1            (7)
01212   *         @arg @ref LL_ADC_CHANNEL_2            (7)
01213   *         @arg @ref LL_ADC_CHANNEL_3            (7)
01214   *         @arg @ref LL_ADC_CHANNEL_4            (7)
01215   *         @arg @ref LL_ADC_CHANNEL_5            (7)
01216   *         @arg @ref LL_ADC_CHANNEL_6
01217   *         @arg @ref LL_ADC_CHANNEL_7
01218   *         @arg @ref LL_ADC_CHANNEL_8
01219   *         @arg @ref LL_ADC_CHANNEL_9
01220   *         @arg @ref LL_ADC_CHANNEL_10
01221   *         @arg @ref LL_ADC_CHANNEL_11
01222   *         @arg @ref LL_ADC_CHANNEL_12
01223   *         @arg @ref LL_ADC_CHANNEL_13
01224   *         @arg @ref LL_ADC_CHANNEL_14
01225   *         @arg @ref LL_ADC_CHANNEL_15
01226   *         @arg @ref LL_ADC_CHANNEL_16
01227   *         @arg @ref LL_ADC_CHANNEL_17
01228   *         @arg @ref LL_ADC_CHANNEL_18
01229   *         @arg @ref LL_ADC_CHANNEL_VREFINT
01230   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
01231   *         @arg @ref LL_ADC_CHANNEL_VBAT
01232   *
01233   *         (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
01234   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
01235   * @retval Value between Min_Data=0 and Max_Data=18
01236   */
01237 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                                        \
01238   ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL)                                 \
01239    ? (                                                                                     \
01240        ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
01241      )                                                                                     \
01242    :                                                                                       \
01243    (                                                                                       \
01244        (uint32_t)POSITION_VAL((__CHANNEL__))                                               \
01245    )                                                                                       \
01246   )
01247
01248 /**
01249   * @brief  Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
01250   *         from number in decimal format.
01251   * @note   Example:
01252   *           __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
01253   *           will return a data equivalent to "LL_ADC_CHANNEL_4".
01254   * @param  __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
01255   * @retval Returned value can be one of the following values:
01256   *         @arg @ref LL_ADC_CHANNEL_0
01257   *         @arg @ref LL_ADC_CHANNEL_1            (7)
01258   *         @arg @ref LL_ADC_CHANNEL_2            (7)
01259   *         @arg @ref LL_ADC_CHANNEL_3            (7)
01260   *         @arg @ref LL_ADC_CHANNEL_4            (7)
01261   *         @arg @ref LL_ADC_CHANNEL_5            (7)
01262   *         @arg @ref LL_ADC_CHANNEL_6
01263   *         @arg @ref LL_ADC_CHANNEL_7
01264   *         @arg @ref LL_ADC_CHANNEL_8
01265   *         @arg @ref LL_ADC_CHANNEL_9
01266   *         @arg @ref LL_ADC_CHANNEL_10
01267   *         @arg @ref LL_ADC_CHANNEL_11
01268   *         @arg @ref LL_ADC_CHANNEL_12
01269   *         @arg @ref LL_ADC_CHANNEL_13
01270   *         @arg @ref LL_ADC_CHANNEL_14
01271   *         @arg @ref LL_ADC_CHANNEL_15
01272   *         @arg @ref LL_ADC_CHANNEL_16
01273   *         @arg @ref LL_ADC_CHANNEL_17
01274   *         @arg @ref LL_ADC_CHANNEL_18
01275   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
01276   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
01277   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
01278   *
01279   *         (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
01280   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
01281   *         (4) For ADC channel read back from ADC register,
01282   *             comparison with internal channel parameter to be done
01283   *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
01284   */
01285 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                                                  \
01286   (((__DECIMAL_NB__) <= 9UL)                                                                            \
01287    ? (                                                                                                  \
01288        ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                             |          \
01289        (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                             |          \
01290        (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))           \
01291      )                                                                                                  \
01292    :                                                                                                    \
01293    (                                                                                                    \
01294        ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                      | \
01295        (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                                      | \
01296        (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))  \
01297    )                                                                                                    \
01298   )
01299
01300 /**
01301   * @brief  Helper macro to determine whether the selected channel
01302   *         corresponds to literal definitions of driver.
01303   * @note   The different literal definitions of ADC channels are:
01304   *         - ADC internal channel:
01305   *           LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
01306   *         - ADC external channel (channel connected to a GPIO pin):
01307   *           LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
01308   * @note   The channel parameter must be a value defined from literal
01309   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
01310   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
01311   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
01312   *         must not be a value from functions where a channel number is
01313   *         returned from ADC registers,
01314   *         because internal and external channels share the same channel
01315   *         number in ADC registers. The differentiation is made only with
01316   *         parameters definitions of driver.
01317   * @param  __CHANNEL__ This parameter can be one of the following values:
01318   *         @arg @ref LL_ADC_CHANNEL_0
01319   *         @arg @ref LL_ADC_CHANNEL_1            (7)
01320   *         @arg @ref LL_ADC_CHANNEL_2            (7)
01321   *         @arg @ref LL_ADC_CHANNEL_3            (7)
01322   *         @arg @ref LL_ADC_CHANNEL_4            (7)
01323   *         @arg @ref LL_ADC_CHANNEL_5            (7)
01324   *         @arg @ref LL_ADC_CHANNEL_6
01325   *         @arg @ref LL_ADC_CHANNEL_7
01326   *         @arg @ref LL_ADC_CHANNEL_8
01327   *         @arg @ref LL_ADC_CHANNEL_9
01328   *         @arg @ref LL_ADC_CHANNEL_10
01329   *         @arg @ref LL_ADC_CHANNEL_11
01330   *         @arg @ref LL_ADC_CHANNEL_12
01331   *         @arg @ref LL_ADC_CHANNEL_13
01332   *         @arg @ref LL_ADC_CHANNEL_14
01333   *         @arg @ref LL_ADC_CHANNEL_15
01334   *         @arg @ref LL_ADC_CHANNEL_16
01335   *         @arg @ref LL_ADC_CHANNEL_17
01336   *         @arg @ref LL_ADC_CHANNEL_18
01337   *         @arg @ref LL_ADC_CHANNEL_VREFINT
01338   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
01339   *         @arg @ref LL_ADC_CHANNEL_VBAT
01340   *
01341   *         (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
01342   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
01343   * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
01344   *         Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
01345   */
01346 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                              \
01347   (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
01348
01349 /**
01350   * @brief  Helper macro to convert a channel defined from parameter
01351   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
01352   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
01353   *         to its equivalent parameter definition of a ADC external channel
01354   *         (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
01355   * @note   The channel parameter can be, additionally to a value
01356   *         defined from parameter definition of a ADC internal channel
01357   *         (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
01358   *         a value defined from parameter definition of
01359   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
01360   *         or a value from functions where a channel number is returned
01361   *         from ADC registers.
01362   * @param  __CHANNEL__ This parameter can be one of the following values:
01363   *         @arg @ref LL_ADC_CHANNEL_0
01364   *         @arg @ref LL_ADC_CHANNEL_1            (7)
01365   *         @arg @ref LL_ADC_CHANNEL_2            (7)
01366   *         @arg @ref LL_ADC_CHANNEL_3            (7)
01367   *         @arg @ref LL_ADC_CHANNEL_4            (7)
01368   *         @arg @ref LL_ADC_CHANNEL_5            (7)
01369   *         @arg @ref LL_ADC_CHANNEL_6
01370   *         @arg @ref LL_ADC_CHANNEL_7
01371   *         @arg @ref LL_ADC_CHANNEL_8
01372   *         @arg @ref LL_ADC_CHANNEL_9
01373   *         @arg @ref LL_ADC_CHANNEL_10
01374   *         @arg @ref LL_ADC_CHANNEL_11
01375   *         @arg @ref LL_ADC_CHANNEL_12
01376   *         @arg @ref LL_ADC_CHANNEL_13
01377   *         @arg @ref LL_ADC_CHANNEL_14
01378   *         @arg @ref LL_ADC_CHANNEL_15
01379   *         @arg @ref LL_ADC_CHANNEL_16
01380   *         @arg @ref LL_ADC_CHANNEL_17
01381   *         @arg @ref LL_ADC_CHANNEL_18
01382   *         @arg @ref LL_ADC_CHANNEL_VREFINT
01383   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
01384   *         @arg @ref LL_ADC_CHANNEL_VBAT
01385   *
01386   *         (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
01387   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
01388   * @retval Returned value can be one of the following values:
01389   *         @arg @ref LL_ADC_CHANNEL_0
01390   *         @arg @ref LL_ADC_CHANNEL_1
01391   *         @arg @ref LL_ADC_CHANNEL_2
01392   *         @arg @ref LL_ADC_CHANNEL_3
01393   *         @arg @ref LL_ADC_CHANNEL_4
01394   *         @arg @ref LL_ADC_CHANNEL_5
01395   *         @arg @ref LL_ADC_CHANNEL_6
01396   *         @arg @ref LL_ADC_CHANNEL_7
01397   *         @arg @ref LL_ADC_CHANNEL_8
01398   *         @arg @ref LL_ADC_CHANNEL_9
01399   *         @arg @ref LL_ADC_CHANNEL_10
01400   *         @arg @ref LL_ADC_CHANNEL_11
01401   *         @arg @ref LL_ADC_CHANNEL_12
01402   *         @arg @ref LL_ADC_CHANNEL_13
01403   *         @arg @ref LL_ADC_CHANNEL_14
01404   *         @arg @ref LL_ADC_CHANNEL_15
01405   *         @arg @ref LL_ADC_CHANNEL_16
01406   *         @arg @ref LL_ADC_CHANNEL_17
01407   *         @arg @ref LL_ADC_CHANNEL_18
01408   */
01409 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)                     \
01410   ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
01411
01412 /**
01413   * @brief  Helper macro to determine whether the internal channel
01414   *         selected is available on the ADC instance selected.
01415   * @note   The channel parameter must be a value defined from parameter
01416   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
01417   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
01418   *         must not be a value defined from parameter definition of
01419   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
01420   *         or a value from functions where a channel number is
01421   *         returned from ADC registers,
01422   *         because internal and external channels share the same channel
01423   *         number in ADC registers. The differentiation is made only with
01424   *         parameters definitions of driver.
01425   * @param  __ADC_INSTANCE__ ADC instance
01426   * @param  __CHANNEL__ This parameter can be one of the following values:
01427   *         @arg @ref LL_ADC_CHANNEL_VREFINT
01428   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
01429   *         @arg @ref LL_ADC_CHANNEL_VBAT
01430   * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
01431   *         Value "1" if the internal channel selected is available on the ADC instance selected.
01432   */
01433 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
01434   (                                                                            \
01435     ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                            \
01436     ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) ||                            \
01437     ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)                                     \
01438   )
01439
01440 /**
01441   * @brief  Helper macro to define ADC analog watchdog parameter:
01442   *         define a single channel to monitor with analog watchdog
01443   *         from sequencer channel and groups definition.
01444   * @note   To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
01445   *         Example:
01446   *           LL_ADC_SetAnalogWDMonitChannels(
01447   *             ADC1, LL_ADC_AWD1,
01448   *             __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
01449   * @param  __CHANNEL__ This parameter can be one of the following values:
01450   *         @arg @ref LL_ADC_CHANNEL_0
01451   *         @arg @ref LL_ADC_CHANNEL_1            (7)
01452   *         @arg @ref LL_ADC_CHANNEL_2            (7)
01453   *         @arg @ref LL_ADC_CHANNEL_3            (7)
01454   *         @arg @ref LL_ADC_CHANNEL_4            (7)
01455   *         @arg @ref LL_ADC_CHANNEL_5            (7)
01456   *         @arg @ref LL_ADC_CHANNEL_6
01457   *         @arg @ref LL_ADC_CHANNEL_7
01458   *         @arg @ref LL_ADC_CHANNEL_8
01459   *         @arg @ref LL_ADC_CHANNEL_9
01460   *         @arg @ref LL_ADC_CHANNEL_10
01461   *         @arg @ref LL_ADC_CHANNEL_11
01462   *         @arg @ref LL_ADC_CHANNEL_12
01463   *         @arg @ref LL_ADC_CHANNEL_13
01464   *         @arg @ref LL_ADC_CHANNEL_14
01465   *         @arg @ref LL_ADC_CHANNEL_15
01466   *         @arg @ref LL_ADC_CHANNEL_16
01467   *         @arg @ref LL_ADC_CHANNEL_17
01468   *         @arg @ref LL_ADC_CHANNEL_18
01469   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
01470   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
01471   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
01472   *
01473   *         (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
01474   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
01475   *         (4) For ADC channel read back from ADC register,
01476   *             comparison with internal channel parameter to be done
01477   *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
01478   * @param  __GROUP__ This parameter can be one of the following values:
01479   *         @arg @ref LL_ADC_GROUP_REGULAR
01480   *         @arg @ref LL_ADC_GROUP_INJECTED
01481   *         @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
01482   * @retval Returned value can be one of the following values:
01483   *         @arg @ref LL_ADC_AWD_DISABLE
01484   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)
01485   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)
01486   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
01487   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)
01488   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)
01489   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
01490   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)
01491   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)
01492   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
01493   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)
01494   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)
01495   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
01496   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)
01497   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)
01498   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
01499   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)
01500   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)
01501   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
01502   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)
01503   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)
01504   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
01505   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)
01506   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)
01507   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
01508   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)
01509   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)
01510   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
01511   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)
01512   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)
01513   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
01514   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)
01515   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)
01516   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
01517   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)
01518   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)
01519   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
01520   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)
01521   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)
01522   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
01523   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)
01524   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)
01525   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
01526   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)
01527   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)
01528   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
01529   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)
01530   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)
01531   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
01532   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)
01533   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)
01534   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
01535   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)
01536   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)
01537   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
01538   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)
01539   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)
01540   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
01541   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)
01542   *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)
01543   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
01544   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (0)
01545   *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (0)
01546   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ
01547   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG       (0)
01548   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ       (0)
01549   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ
01550   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (0)
01551   *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (0)
01552   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ
01553   *
01554   *         (0) On STM32WB, parameter available only on analog watchdog number: AWD1.
01555   */
01556 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)                                           \
01557   (((__GROUP__) == LL_ADC_GROUP_REGULAR)                                                                  \
01558    ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)                         \
01559    :                                                                                                      \
01560    ((__GROUP__) == LL_ADC_GROUP_INJECTED)                                                                 \
01561    ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)                        \
01562    :                                                                                                      \
01563    (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)        \
01564   )
01565
01566 /**
01567   * @brief  Helper macro to set the value of ADC analog watchdog threshold high
01568   *         or low in function of ADC resolution, when ADC resolution is
01569   *         different of 12 bits.
01570   * @note   To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
01571   *         or @ref LL_ADC_SetAnalogWDThresholds().
01572   *         Example, with a ADC resolution of 8 bits, to set the value of
01573   *         analog watchdog threshold high (on 8 bits):
01574   *           LL_ADC_SetAnalogWDThresholds
01575   *            (< ADCx param >,
01576   *             __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
01577   *            );
01578   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
01579   *         @arg @ref LL_ADC_RESOLUTION_12B
01580   *         @arg @ref LL_ADC_RESOLUTION_10B
01581   *         @arg @ref LL_ADC_RESOLUTION_8B
01582   *         @arg @ref LL_ADC_RESOLUTION_6B
01583   * @param  __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
01584   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
01585   */
01586 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
01587   ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
01588
01589 /**
01590   * @brief  Helper macro to get the value of ADC analog watchdog threshold high
01591   *         or low in function of ADC resolution, when ADC resolution is
01592   *         different of 12 bits.
01593   * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().
01594   *         Example, with a ADC resolution of 8 bits, to get the value of
01595   *         analog watchdog threshold high (on 8 bits):
01596   *           < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
01597   *            (LL_ADC_RESOLUTION_8B,
01598   *             LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
01599   *            );
01600   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
01601   *         @arg @ref LL_ADC_RESOLUTION_12B
01602   *         @arg @ref LL_ADC_RESOLUTION_10B
01603   *         @arg @ref LL_ADC_RESOLUTION_8B
01604   *         @arg @ref LL_ADC_RESOLUTION_6B
01605   * @param  __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
01606   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
01607   */
01608 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
01609   ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
01610
01611 /**
01612   * @brief  Helper macro to get the ADC analog watchdog threshold high
01613   *         or low from raw value containing both thresholds concatenated.
01614   * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().
01615   *         Example, to get analog watchdog threshold high from the register raw value:
01616   *           __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
01617   * @param  __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
01618   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
01619   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
01620   * @param  __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
01621   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
01622   */
01623 #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__)       \
01624   (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) & LL_ADC_AWD_THRESHOLD_LOW)
01625
01626 /**
01627   * @brief  Helper macro to set the ADC calibration value with both single ended
01628   *         and differential modes calibration factors concatenated.
01629   * @note   To be used with function @ref LL_ADC_SetCalibrationFactor().
01630   *         Example, to set calibration factors single ended to 0x55
01631   *         and differential ended to 0x2A:
01632   *           LL_ADC_SetCalibrationFactor(
01633   *             ADC1,
01634   *             __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
01635   * @param  __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F
01636   * @param  __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F
01637   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
01638   */
01639 #define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__)        \
01640   (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))
01641
01642 /**
01643   * @brief  Helper macro to select the ADC common instance
01644   *         to which is belonging the selected ADC instance.
01645   * @note   ADC common register instance can be used for:
01646   *         - Set parameters common to several ADC instances
01647   *         - Multimode (for devices with several ADC instances)
01648   *         Refer to functions having argument "ADCxy_COMMON" as parameter.
01649   * @param  __ADCx__ ADC instance
01650   * @retval ADC common register instance
01651   */
01652 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
01653 #define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \
01654   (ADC123_COMMON)
01655 #elif defined(ADC1) && defined(ADC2)
01656 #define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \
01657   (ADC12_COMMON)
01658 #else
01659 #define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \
01660   (ADC1_COMMON)
01661 #endif
01662
01663 /**
01664   * @brief  Helper macro to check if all ADC instances sharing the same
01665   *         ADC common instance are disabled.
01666   * @note   This check is required by functions with setting conditioned to
01667   *         ADC state:
01668   *         All ADC instances of the ADC common group must be disabled.
01669   *         Refer to functions having argument "ADCxy_COMMON" as parameter.
01670   * @note   On devices with only 1 ADC common instance, parameter of this macro
01671   *         is useless and can be ignored (parameter kept for compatibility
01672   *         with devices featuring several ADC common instances).
01673   * @param  __ADCXY_COMMON__ ADC common instance
01674   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
01675   * @retval Value "0" if all ADC instances sharing the same ADC common instance
01676   *         are disabled.
01677   *         Value "1" if at least one ADC instance sharing the same ADC common instance
01678   *         is enabled.
01679   */
01680 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
01681 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
01682   (LL_ADC_IsEnabled(ADC1) |                                                    \
01683    LL_ADC_IsEnabled(ADC2) |                                                    \
01684    LL_ADC_IsEnabled(ADC3)  )
01685 #elif defined(ADC1) && defined(ADC2)
01686 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
01687   (LL_ADC_IsEnabled(ADC1) |                                                    \
01688    LL_ADC_IsEnabled(ADC2)  )
01689 #else
01690 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
01691   (LL_ADC_IsEnabled(ADC1))
01692 #endif
01693
01694 /**
01695   * @brief  Helper macro to define the ADC conversion data full-scale digital
01696   *         value corresponding to the selected ADC resolution.
01697   * @note   ADC conversion data full-scale corresponds to voltage range
01698   *         determined by analog voltage references Vref+ and Vref-
01699   *         (refer to reference manual).
01700   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
01701   *         @arg @ref LL_ADC_RESOLUTION_12B
01702   *         @arg @ref LL_ADC_RESOLUTION_10B
01703   *         @arg @ref LL_ADC_RESOLUTION_8B
01704   *         @arg @ref LL_ADC_RESOLUTION_6B
01705   * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)
01706   */
01707 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \
01708   (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))
01709
01710 /**
01711   * @brief  Helper macro to convert the ADC conversion data from
01712   *         a resolution to another resolution.
01713   * @param  __DATA__ ADC conversion data to be converted
01714   * @param  __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
01715   *         This parameter can be one of the following values:
01716   *         @arg @ref LL_ADC_RESOLUTION_12B
01717   *         @arg @ref LL_ADC_RESOLUTION_10B
01718   *         @arg @ref LL_ADC_RESOLUTION_8B
01719   *         @arg @ref LL_ADC_RESOLUTION_6B
01720   * @param  __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
01721   *         This parameter can be one of the following values:
01722   *         @arg @ref LL_ADC_RESOLUTION_12B
01723   *         @arg @ref LL_ADC_RESOLUTION_10B
01724   *         @arg @ref LL_ADC_RESOLUTION_8B
01725   *         @arg @ref LL_ADC_RESOLUTION_6B
01726   * @retval ADC conversion data to the requested resolution
01727   */
01728 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
01729                                          __ADC_RESOLUTION_CURRENT__,\
01730                                          __ADC_RESOLUTION_TARGET__)            \
01731   (((__DATA__)                                                                 \
01732     << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))   \
01733    >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))      \
01734   )
01735
01736 /**
01737   * @brief  Helper macro to calculate the voltage (unit: mVolt)
01738   *         corresponding to a ADC conversion data (unit: digital value).
01739   * @note   Analog reference voltage (Vref+) must be either known from
01740   *         user board environment or can be calculated using ADC measurement
01741   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
01742   * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
01743   * @param  __ADC_DATA__ ADC conversion data (resolution 12 bits)
01744   *                       (unit: digital value).
01745   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
01746   *         @arg @ref LL_ADC_RESOLUTION_12B
01747   *         @arg @ref LL_ADC_RESOLUTION_10B
01748   *         @arg @ref LL_ADC_RESOLUTION_8B
01749   *         @arg @ref LL_ADC_RESOLUTION_6B
01750   * @retval ADC conversion data equivalent voltage value (unit: mVolt)
01751   */
01752 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
01753                                       __ADC_DATA__,\
01754                                       __ADC_RESOLUTION__)                      \
01755   ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__)                                   \
01756    / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                                \
01757   )
01758
01759 /**
01760   * @brief  Helper macro to calculate analog reference voltage (Vref+)
01761   *         (unit: mVolt) from ADC conversion data of internal voltage
01762   *         reference VrefInt.
01763   * @note   Computation is using VrefInt calibration value
01764   *         stored in system memory for each device during production.
01765   * @note   This voltage depends on user board environment: voltage level
01766   *         connected to pin Vref+.
01767   *         On devices with small package, the pin Vref+ is not present
01768   *         and internally bonded to pin Vdda.
01769   * @note   On this STM32 serie, calibration data of internal voltage reference
01770   *         VrefInt corresponds to a resolution of 12 bits,
01771   *         this is the recommended ADC resolution to convert voltage of
01772   *         internal voltage reference VrefInt.
01773   *         Otherwise, this macro performs the processing to scale
01774   *         ADC conversion data to 12 bits.
01775   * @param  __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
01776   *         of internal voltage reference VrefInt (unit: digital value).
01777   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
01778   *         @arg @ref LL_ADC_RESOLUTION_12B
01779   *         @arg @ref LL_ADC_RESOLUTION_10B
01780   *         @arg @ref LL_ADC_RESOLUTION_8B
01781   *         @arg @ref LL_ADC_RESOLUTION_6B
01782   * @retval Analog reference voltage (unit: mV)
01783   */
01784 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
01785                                          __ADC_RESOLUTION__)                   \
01786   (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF)                          \
01787    / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__),                  \
01788                                       (__ADC_RESOLUTION__),                    \
01789                                       LL_ADC_RESOLUTION_12B))
01790
01791 /**
01792   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
01793   *         from ADC conversion data of internal temperature sensor.
01794   * @note   Computation is using temperature sensor calibration values
01795   *         stored in system memory for each device during production.
01796   * @note   Calculation formula:
01797   *           Temperature = ((TS_ADC_DATA - TS_CAL1)
01798   *                           * (TS_CAL2_TEMP - TS_CAL1_TEMP))
01799   *                         / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
01800   *           with TS_ADC_DATA = temperature sensor raw data measured by ADC
01801   *                Avg_Slope = (TS_CAL2 - TS_CAL1)
01802   *                            / (TS_CAL2_TEMP - TS_CAL1_TEMP)
01803   *                TS_CAL1   = equivalent TS_ADC_DATA at temperature
01804   *                            TEMP_DEGC_CAL1 (calibrated in factory)
01805   *                TS_CAL2   = equivalent TS_ADC_DATA at temperature
01806   *                            TEMP_DEGC_CAL2 (calibrated in factory)
01807   *         Caution: Calculation relevancy under reserve that calibration
01808   *                  parameters are correct (address and data).
01809   *                  To calculate temperature using temperature sensor
01810   *                  datasheet typical values (generic values less, therefore
01811   *                  less accurate than calibrated values),
01812   *                  use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
01813   * @note   As calculation input, the analog reference voltage (Vref+) must be
01814   *         defined as it impacts the ADC LSB equivalent voltage.
01815   * @note   Analog reference voltage (Vref+) must be either known from
01816   *         user board environment or can be calculated using ADC measurement
01817   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
01818   * @note   On this STM32 serie, calibration data of temperature sensor
01819   *         corresponds to a resolution of 12 bits,
01820   *         this is the recommended ADC resolution to convert voltage of
01821   *         temperature sensor.
01822   *         Otherwise, this macro performs the processing to scale
01823   *         ADC conversion data to 12 bits.
01824   * @param  __VREFANALOG_VOLTAGE__  Analog reference voltage (unit: mV)
01825   * @param  __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
01826   *                                 temperature sensor (unit: digital value).
01827   * @param  __ADC_RESOLUTION__      ADC resolution at which internal temperature
01828   *                                 sensor voltage has been measured.
01829   *         This parameter can be one of the following values:
01830   *         @arg @ref LL_ADC_RESOLUTION_12B
01831   *         @arg @ref LL_ADC_RESOLUTION_10B
01832   *         @arg @ref LL_ADC_RESOLUTION_8B
01833   *         @arg @ref LL_ADC_RESOLUTION_6B
01834   * @retval Temperature (unit: degree Celsius)
01835   */
01836 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
01837                                   __TEMPSENSOR_ADC_DATA__,\
01838                                   __ADC_RESOLUTION__)                              \
01839   (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__),     \
01840                                                     (__ADC_RESOLUTION__),          \
01841                                                     LL_ADC_RESOLUTION_12B)         \
01842                    * (__VREFANALOG_VOLTAGE__))                                     \
01843                   / TEMPSENSOR_CAL_VREFANALOG)                                     \
01844         - (int32_t) *TEMPSENSOR_CAL1_ADDR)                                         \
01845      ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP)                    \
01846     ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
01847    ) + TEMPSENSOR_CAL1_TEMP                                                        \
01848   )
01849
01850 /**
01851   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
01852   *         from ADC conversion data of internal temperature sensor.
01853   * @note   Computation is using temperature sensor typical values
01854   *         (refer to device datasheet).
01855   * @note   Calculation formula:
01856   *           Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
01857   *                         / Avg_Slope + CALx_TEMP
01858   *           with TS_ADC_DATA      = temperature sensor raw data measured by ADC
01859   *                                   (unit: digital value)
01860   *                Avg_Slope        = temperature sensor slope
01861   *                                   (unit: uV/Degree Celsius)
01862   *                TS_TYP_CALx_VOLT = temperature sensor digital value at
01863   *                                   temperature CALx_TEMP (unit: mV)
01864   *         Caution: Calculation relevancy under reserve the temperature sensor
01865   *                  of the current device has characteristics in line with
01866   *                  datasheet typical values.
01867   *                  If temperature sensor calibration values are available on
01868   *                  on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
01869   *                  temperature calculation will be more accurate using
01870   *                  helper macro @ref __LL_ADC_CALC_TEMPERATURE().
01871   * @note   As calculation input, the analog reference voltage (Vref+) must be
01872   *         defined as it impacts the ADC LSB equivalent voltage.
01873   * @note   Analog reference voltage (Vref+) must be either known from
01874   *         user board environment or can be calculated using ADC measurement
01875   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
01876   * @note   ADC measurement data must correspond to a resolution of 12 bits
01877   *         (full scale digital value 4095). If not the case, the data must be
01878   *         preliminarily rescaled to an equivalent resolution of 12 bits.
01879   * @param  __TEMPSENSOR_TYP_AVGSLOPE__   Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
01880   *                                       On STM32WB, refer to device datasheet parameter "Avg_Slope".
01881   * @param  __TEMPSENSOR_TYP_CALX_V__     Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
01882   *                                       On STM32WB, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
01883   * @param  __TEMPSENSOR_CALX_TEMP__      Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
01884   * @param  __VREFANALOG_VOLTAGE__        Analog voltage reference (Vref+) voltage (unit: mV)
01885   * @param  __TEMPSENSOR_ADC_DATA__       ADC conversion data of internal temperature sensor (unit: digital value).
01886   * @param  __ADC_RESOLUTION__            ADC resolution at which internal temperature sensor voltage has been measured.
01887   *         This parameter can be one of the following values:
01888   *         @arg @ref LL_ADC_RESOLUTION_12B
01889   *         @arg @ref LL_ADC_RESOLUTION_10B
01890   *         @arg @ref LL_ADC_RESOLUTION_8B
01891   *         @arg @ref LL_ADC_RESOLUTION_6B
01892   * @retval Temperature (unit: degree Celsius)
01893   */
01894 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
01895                                              __TEMPSENSOR_TYP_CALX_V__,\
01896                                              __TEMPSENSOR_CALX_TEMP__,\
01897                                              __VREFANALOG_VOLTAGE__,\
01898                                              __TEMPSENSOR_ADC_DATA__,\
01899                                              __ADC_RESOLUTION__)               \
01900   ((( (                                                                        \
01901        (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__))       \
01902                   / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))                \
01903                  * 1000UL)                                                     \
01904        -                                                                       \
01905        (int32_t)(((__TEMPSENSOR_TYP_CALX_V__))                                 \
01906                  * 1000UL)                                                     \
01907       )                                                                        \
01908     ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__)                                 \
01909    ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__)                                     \
01910   )
01911
01912 /**
01913   * @}
01914   */
01915
01916 /**
01917   * @}
01918   */
01919
01920
01921 /* Exported functions --------------------------------------------------------*/
01922 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
01923   * @{
01924   */
01925
01926 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
01927   * @{
01928   */
01929 /* Note: LL ADC functions to set DMA transfer are located into sections of    */
01930 /*       configuration of ADC instance, groups and multimode (if available):  */
01931 /*       @ref LL_ADC_REG_SetDMATransfer(), ...                                */
01932
01933 /**
01934   * @brief  Function to help to configure DMA transfer from ADC: retrieve the
01935   *         ADC register address from ADC instance and a list of ADC registers
01936   *         intended to be used (most commonly) with DMA transfer.
01937   * @note   These ADC registers are data registers:
01938   *         when ADC conversion data is available in ADC data registers,
01939   *         ADC generates a DMA transfer request.
01940   * @note   This macro is intended to be used with LL DMA driver, refer to
01941   *         function "LL_DMA_ConfigAddresses()".
01942   *         Example:
01943   *           LL_DMA_ConfigAddresses(DMA1,
01944   *                                  LL_DMA_CHANNEL_1,
01945   *                                  LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
01946   *                                  (uint32_t)&< array or variable >,
01947   *                                  LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
01948   * @note   For devices with several ADC: in multimode, some devices
01949   *         use a different data register outside of ADC instance scope
01950   *         (common data register). This macro manages this register difference,
01951   *         only ADC instance has to be set as parameter.
01952   * @rmtoll DR       DATA           LL_ADC_DMA_GetRegAddr
01953   * @param  ADCx ADC instance
01954   * @param  Register This parameter can be one of the following values:
01955   *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
01956   * @retval ADC register address
01957   */
01958 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
01959 {
01960   /* Prevent unused argument(s) compilation warning */
01961   (void)(Register);
01962
01963   /* Retrieve address of register DR */
01964   return (uint32_t)&(ADCx->DR);
01965 }
01966
01967 /**
01968   * @}
01969   */
01970
01971 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
01972   * @{
01973   */
01974
01975 /**
01976   * @brief  Set parameter common to several ADC: Clock source and prescaler.
01977   * @note   ADC clock source and prescaler must be selected in function of system clock to not exceed ADC maximum frequency, depending on devices.
01978   *         Example: STM32WB55xx ADC maximum frequency is 64MHz (corresponding to 4.27Msmp/s maximum)
01979   *         Example: STM32WB50xx ADC maximum frequency is 32MHz (corresponding to 2.13Msmp/s maximum)
01980   *         For ADC maximum frequency, refer to datasheet of the selected device.
01981   * @note   On this STM32 serie, if ADC group injected is used, some
01982   *         clock ratio constraints between ADC clock and AHB clock
01983   *         must be respected.
01984   *         Refer to reference manual.
01985   * @note   On this STM32 serie, setting of this feature is conditioned to
01986   *         ADC state:
01987   *         All ADC instances of the ADC common group must be disabled.
01988   *         This check can be done with function @ref LL_ADC_IsEnabled() for each
01989   *         ADC instance or by using helper macro helper macro
01990   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
01991   * @rmtoll CCR      CKMODE         LL_ADC_SetCommonClock\n
01992   *         CCR      PRESC          LL_ADC_SetCommonClock
01993   * @param  ADCxy_COMMON ADC common instance
01994   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
01995   * @param  CommonClock This parameter can be one of the following values:
01996   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
01997   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
01998   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
01999   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
02000   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
02001   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
02002   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
02003   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
02004   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
02005   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
02006   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
02007   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
02008   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
02009   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
02010   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
02011   * @retval None
02012   */
02013 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
02014 {
02015   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
02016 }
02017
02018 /**
02019   * @brief  Get parameter common to several ADC: Clock source and prescaler.
02020   * @rmtoll CCR      CKMODE         LL_ADC_GetCommonClock\n
02021   *         CCR      PRESC          LL_ADC_GetCommonClock
02022   * @param  ADCxy_COMMON ADC common instance
02023   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
02024   * @retval Returned value can be one of the following values:
02025   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
02026   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
02027   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
02028   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
02029   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
02030   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
02031   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
02032   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
02033   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
02034   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
02035   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
02036   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
02037   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
02038   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
02039   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
02040   */
02041 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
02042 {
02043   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));
02044 }
02045
02046 /**
02047   * @brief  Set parameter common to several ADC: measurement path to internal
02048   *         channels (VrefInt, temperature sensor, ...).
02049   * @note   One or several values can be selected.
02050   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
02051   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
02052   * @note   Stabilization time of measurement path to internal channel:
02053   *         After enabling internal paths, before starting ADC conversion,
02054   *         a delay is required for internal voltage reference and
02055   *         temperature sensor stabilization time.
02056   *         Refer to device datasheet.
02057   *         Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
02058   *         Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
02059   * @note   ADC internal channel sampling time constraint:
02060   *         For ADC conversion of internal channels,
02061   *         a sampling time minimum value is required.
02062   *         Refer to device datasheet.
02063   * @note   On this STM32 serie, setting of this feature is conditioned to
02064   *         ADC state:
02065   *         All ADC instances of the ADC common group must be disabled.
02066   *         This check can be done with function @ref LL_ADC_IsEnabled() for each
02067   *         ADC instance or by using helper macro helper macro
02068   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
02069   * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalCh\n
02070   *         CCR      TSEN           LL_ADC_SetCommonPathInternalCh\n
02071   *         CCR      VBATEN         LL_ADC_SetCommonPathInternalCh
02072   * @param  ADCxy_COMMON ADC common instance
02073   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
02074   * @param  PathInternal This parameter can be a combination of the following values:
02075   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
02076   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
02077   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
02078   *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
02079   * @retval None
02080   */
02081 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
02082 {
02083   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
02084 }
02085
02086 /**
02087   * @brief  Get parameter common to several ADC: measurement path to internal
02088   *         channels (VrefInt, temperature sensor, ...).
02089   * @note   One or several values can be selected.
02090   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
02091   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
02092   * @rmtoll CCR      VREFEN         LL_ADC_GetCommonPathInternalCh\n
02093   *         CCR      TSEN           LL_ADC_GetCommonPathInternalCh\n
02094   *         CCR      VBATEN         LL_ADC_GetCommonPathInternalCh
02095   * @param  ADCxy_COMMON ADC common instance
02096   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
02097   * @retval Returned value can be a combination of the following values:
02098   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
02099   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
02100   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
02101   *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
02102   */
02103 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
02104 {
02105   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
02106 }
02107
02108 /**
02109   * @}
02110   */
02111
02112 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
02113   * @{
02114   */
02115
02116 /**
02117   * @brief  Set ADC calibration factor in the mode single-ended
02118   *         or differential (for devices with differential mode available).
02119   * @note   This function is intended to set calibration parameters
02120   *         without having to perform a new calibration using
02121   *         @ref LL_ADC_StartCalibration().
02122   * @note   For devices with differential mode available:
02123   *         Calibration of offset is specific to each of
02124   *         single-ended and differential modes
02125   *         (calibration factor must be specified for each of these
02126   *         differential modes, if used afterwards and if the application
02127   *         requires their calibration).
02128   * @note   In case of setting calibration factors of both modes single ended
02129   *         and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
02130   *         both calibration factors must be concatenated.
02131   *         To perform this processing, use helper macro
02132   *         @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
02133   * @note   On this STM32 serie, setting of this feature is conditioned to
02134   *         ADC state:
02135   *         ADC must be enabled, without calibration on going, without conversion
02136   *         on going on group regular.
02137   * @rmtoll CALFACT  CALFACT_S      LL_ADC_SetCalibrationFactor\n
02138   *         CALFACT  CALFACT_D      LL_ADC_SetCalibrationFactor
02139   * @param  ADCx ADC instance
02140   * @param  SingleDiff This parameter can be one of the following values:
02141   *         @arg @ref LL_ADC_SINGLE_ENDED
02142   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
02143   *         @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
02144   * @param  CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
02145   * @retval None
02146   */
02147 __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
02148 {
02149   MODIFY_REG(ADCx->CALFACT,
02150              SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
02151              CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S)));
02152 }
02153
02154 /**
02155   * @brief  Get ADC calibration factor in the mode single-ended
02156   *         or differential (for devices with differential mode available).
02157   * @note   Calibration factors are set by hardware after performing
02158   *         a calibration run using function @ref LL_ADC_StartCalibration().
02159   * @note   For devices with differential mode available:
02160   *         Calibration of offset is specific to each of
02161   *         single-ended and differential modes
02162   * @rmtoll CALFACT  CALFACT_S      LL_ADC_GetCalibrationFactor\n
02163   *         CALFACT  CALFACT_D      LL_ADC_GetCalibrationFactor
02164   * @param  ADCx ADC instance
02165   * @param  SingleDiff This parameter can be one of the following values:
02166   *         @arg @ref LL_ADC_SINGLE_ENDED
02167   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
02168   * @retval Value between Min_Data=0x00 and Max_Data=0x7F
02169   */
02170 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)
02171 {
02172   /* Retrieve bits with position in register depending on parameter           */
02173   /* "SingleDiff".                                                            */
02174   /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because      */
02175   /* containing other bits reserved for other purpose.                        */
02176   return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
02177 }
02178
02179 /**
02180   * @brief  Set ADC resolution.
02181   *         Refer to reference manual for alignments formats
02182   *         dependencies to ADC resolutions.
02183   * @note   On this STM32 serie, setting of this feature is conditioned to
02184   *         ADC state:
02185   *         ADC must be disabled or enabled without conversion on going
02186   *         on either groups regular or injected.
02187   * @rmtoll CFGR     RES            LL_ADC_SetResolution
02188   * @param  ADCx ADC instance
02189   * @param  Resolution This parameter can be one of the following values:
02190   *         @arg @ref LL_ADC_RESOLUTION_12B
02191   *         @arg @ref LL_ADC_RESOLUTION_10B
02192   *         @arg @ref LL_ADC_RESOLUTION_8B
02193   *         @arg @ref LL_ADC_RESOLUTION_6B
02194   * @retval None
02195   */
02196 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
02197 {
02198   MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
02199 }
02200
02201 /**
02202   * @brief  Get ADC resolution.
02203   *         Refer to reference manual for alignments formats
02204   *         dependencies to ADC resolutions.
02205   * @rmtoll CFGR     RES            LL_ADC_GetResolution
02206   * @param  ADCx ADC instance
02207   * @retval Returned value can be one of the following values:
02208   *         @arg @ref LL_ADC_RESOLUTION_12B
02209   *         @arg @ref LL_ADC_RESOLUTION_10B
02210   *         @arg @ref LL_ADC_RESOLUTION_8B
02211   *         @arg @ref LL_ADC_RESOLUTION_6B
02212   */
02213 __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
02214 {
02215   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
02216 }
02217
02218 /**
02219   * @brief  Set ADC conversion data alignment.
02220   * @note   Refer to reference manual for alignments formats
02221   *         dependencies to ADC resolutions.
02222   * @note   On this STM32 serie, setting of this feature is conditioned to
02223   *         ADC state:
02224   *         ADC must be disabled or enabled without conversion on going
02225   *         on either groups regular or injected.
02226   * @rmtoll CFGR     ALIGN          LL_ADC_SetDataAlignment
02227   * @param  ADCx ADC instance
02228   * @param  DataAlignment This parameter can be one of the following values:
02229   *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT
02230   *         @arg @ref LL_ADC_DATA_ALIGN_LEFT
02231   * @retval None
02232   */
02233 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
02234 {
02235   MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment);
02236 }
02237
02238 /**
02239   * @brief  Get ADC conversion data alignment.
02240   * @note   Refer to reference manual for alignments formats
02241   *         dependencies to ADC resolutions.
02242   * @rmtoll CFGR     ALIGN          LL_ADC_GetDataAlignment
02243   * @param  ADCx ADC instance
02244   * @retval Returned value can be one of the following values:
02245   *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT
02246   *         @arg @ref LL_ADC_DATA_ALIGN_LEFT
02247   */
02248 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
02249 {
02250   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN));
02251 }
02252
02253 /**
02254   * @brief  Set ADC low power mode.
02255   * @note   Description of ADC low power modes:
02256   *         - ADC low power mode "auto wait": Dynamic low power mode,
02257   *           ADC conversions occurrences are limited to the minimum necessary
02258   *           in order to reduce power consumption.
02259   *           New ADC conversion starts only when the previous
02260   *           unitary conversion data (for ADC group regular)
02261   *           or previous sequence conversions data (for ADC group injected)
02262   *           has been retrieved by user software.
02263   *           In the meantime, ADC remains idle: does not performs any
02264   *           other conversion.
02265   *           This mode allows to automatically adapt the ADC conversions
02266   *           triggers to the speed of the software that reads the data.
02267   *           Moreover, this avoids risk of overrun for low frequency
02268   *           applications.
02269   *           How to use this low power mode:
02270   *           - Do not use with interruption or DMA since these modes
02271   *             have to clear immediately the EOC flag to free the
02272   *             IRQ vector sequencer.
02273   *           - Do use with polling: 1. Start conversion,
02274   *             2. Later on, when conversion data is needed: poll for end of
02275   *             conversion  to ensure that conversion is completed and
02276   *             retrieve ADC conversion data. This will trig another
02277   *             ADC conversion start.
02278   *         - ADC low power mode "auto power-off" (feature available on
02279   *           this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
02280   *           the ADC automatically powers-off after a conversion and
02281   *           automatically wakes up when a new conversion is triggered
02282   *           (with startup time between trigger and start of sampling).
02283   *           This feature can be combined with low power mode "auto wait".
02284   * @note   With ADC low power mode "auto wait", the ADC conversion data read
02285   *         is corresponding to previous ADC conversion start, independently
02286   *         of delay during which ADC was idle.
02287   *         Therefore, the ADC conversion data may be outdated: does not
02288   *         correspond to the current voltage level on the selected
02289   *         ADC channel.
02290   * @note   On this STM32 serie, setting of this feature is conditioned to
02291   *         ADC state:
02292   *         ADC must be disabled or enabled without conversion on going
02293   *         on either groups regular or injected.
02294   * @rmtoll CFGR     AUTDLY         LL_ADC_SetLowPowerMode
02295   * @param  ADCx ADC instance
02296   * @param  LowPowerMode This parameter can be one of the following values:
02297   *         @arg @ref LL_ADC_LP_MODE_NONE
02298   *         @arg @ref LL_ADC_LP_AUTOWAIT
02299   * @retval None
02300   */
02301 __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
02302 {
02303   MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
02304 }
02305
02306 /**
02307   * @brief  Get ADC low power mode:
02308   * @note   Description of ADC low power modes:
02309   *         - ADC low power mode "auto wait": Dynamic low power mode,
02310   *           ADC conversions occurrences are limited to the minimum necessary
02311   *           in order to reduce power consumption.
02312   *           New ADC conversion starts only when the previous
02313   *           unitary conversion data (for ADC group regular)
02314   *           or previous sequence conversions data (for ADC group injected)
02315   *           has been retrieved by user software.
02316   *           In the meantime, ADC remains idle: does not performs any
02317   *           other conversion.
02318   *           This mode allows to automatically adapt the ADC conversions
02319   *           triggers to the speed of the software that reads the data.
02320   *           Moreover, this avoids risk of overrun for low frequency
02321   *           applications.
02322   *           How to use this low power mode:
02323   *           - Do not use with interruption or DMA since these modes
02324   *             have to clear immediately the EOC flag to free the
02325   *             IRQ vector sequencer.
02326   *           - Do use with polling: 1. Start conversion,
02327   *             2. Later on, when conversion data is needed: poll for end of
02328   *             conversion  to ensure that conversion is completed and
02329   *             retrieve ADC conversion data. This will trig another
02330   *             ADC conversion start.
02331   *         - ADC low power mode "auto power-off" (feature available on
02332   *           this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
02333   *           the ADC automatically powers-off after a conversion and
02334   *           automatically wakes up when a new conversion is triggered
02335   *           (with startup time between trigger and start of sampling).
02336   *           This feature can be combined with low power mode "auto wait".
02337   * @note   With ADC low power mode "auto wait", the ADC conversion data read
02338   *         is corresponding to previous ADC conversion start, independently
02339   *         of delay during which ADC was idle.
02340   *         Therefore, the ADC conversion data may be outdated: does not
02341   *         correspond to the current voltage level on the selected
02342   *         ADC channel.
02343   * @rmtoll CFGR     AUTDLY         LL_ADC_GetLowPowerMode
02344   * @param  ADCx ADC instance
02345   * @retval Returned value can be one of the following values:
02346   *         @arg @ref LL_ADC_LP_MODE_NONE
02347   *         @arg @ref LL_ADC_LP_AUTOWAIT
02348   */
02349 __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
02350 {
02351   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
02352 }
02353
02354 /**
02355   * @brief  Set ADC selected offset number 1, 2, 3 or 4.
02356   * @note   This function set the 2 items of offset configuration:
02357   *         - ADC channel to which the offset programmed will be applied
02358   *           (independently of channel mapped on ADC group regular
02359   *           or group injected)
02360   *         - Offset level (offset to be subtracted from the raw
02361   *           converted data).
02362   * @note   Caution: Offset format is dependent to ADC resolution:
02363   *         offset has to be left-aligned on bit 11, the LSB (right bits)
02364   *         are set to 0.
02365   * @note   This function enables the offset, by default. It can be forced
02366   *         to disable state using function LL_ADC_SetOffsetState().
02367   * @note   If a channel is mapped on several offsets numbers, only the offset
02368   *         with the lowest value is considered for the subtraction.
02369   * @note   On this STM32 serie, setting of this feature is conditioned to
02370   *         ADC state:
02371   *         ADC must be disabled or enabled without conversion on going
02372   *         on either groups regular or injected.
02373   * @note   On STM32WB, some fast channels are available: fast analog inputs
02374   *         coming from GPIO pads (ADC_IN1..5).
02375   * @rmtoll OFR1     OFFSET1_CH     LL_ADC_SetOffset\n
02376   *         OFR1     OFFSET1        LL_ADC_SetOffset\n
02377   *         OFR1     OFFSET1_EN     LL_ADC_SetOffset\n
02378   *         OFR2     OFFSET2_CH     LL_ADC_SetOffset\n
02379   *         OFR2     OFFSET2        LL_ADC_SetOffset\n
02380   *         OFR2     OFFSET2_EN     LL_ADC_SetOffset\n
02381   *         OFR3     OFFSET3_CH     LL_ADC_SetOffset\n
02382   *         OFR3     OFFSET3        LL_ADC_SetOffset\n
02383   *         OFR3     OFFSET3_EN     LL_ADC_SetOffset\n
02384   *         OFR4     OFFSET4_CH     LL_ADC_SetOffset\n
02385   *         OFR4     OFFSET4        LL_ADC_SetOffset\n
02386   *         OFR4     OFFSET4_EN     LL_ADC_SetOffset
02387   * @param  ADCx ADC instance
02388   * @param  Offsety This parameter can be one of the following values:
02389   *         @arg @ref LL_ADC_OFFSET_1
02390   *         @arg @ref LL_ADC_OFFSET_2
02391   *         @arg @ref LL_ADC_OFFSET_3
02392   *         @arg @ref LL_ADC_OFFSET_4
02393   * @param  Channel This parameter can be one of the following values:
02394   *         @arg @ref LL_ADC_CHANNEL_0
02395   *         @arg @ref LL_ADC_CHANNEL_1            (7)
02396   *         @arg @ref LL_ADC_CHANNEL_2            (7)
02397   *         @arg @ref LL_ADC_CHANNEL_3            (7)
02398   *         @arg @ref LL_ADC_CHANNEL_4            (7)
02399   *         @arg @ref LL_ADC_CHANNEL_5            (7)
02400   *         @arg @ref LL_ADC_CHANNEL_6
02401   *         @arg @ref LL_ADC_CHANNEL_7
02402   *         @arg @ref LL_ADC_CHANNEL_8
02403   *         @arg @ref LL_ADC_CHANNEL_9
02404   *         @arg @ref LL_ADC_CHANNEL_10
02405   *         @arg @ref LL_ADC_CHANNEL_11
02406   *         @arg @ref LL_ADC_CHANNEL_12
02407   *         @arg @ref LL_ADC_CHANNEL_13
02408   *         @arg @ref LL_ADC_CHANNEL_14
02409   *         @arg @ref LL_ADC_CHANNEL_15
02410   *         @arg @ref LL_ADC_CHANNEL_16
02411   *         @arg @ref LL_ADC_CHANNEL_17
02412   *         @arg @ref LL_ADC_CHANNEL_18
02413   *         @arg @ref LL_ADC_CHANNEL_VREFINT
02414   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
02415   *         @arg @ref LL_ADC_CHANNEL_VBAT
02416   *
02417   *         (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
02418   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
02419   * @param  OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
02420   * @retval None
02421   */
02422 __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
02423 {
02424   register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
02425
02426   MODIFY_REG(*preg,
02427              ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
02428              ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
02429 }
02430
02431 /**
02432   * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:
02433   *         Channel to which the offset programmed will be applied
02434   *         (independently of channel mapped on ADC group regular
02435   *         or group injected)
02436   * @note   Usage of the returned channel number:
02437   *         - To reinject this channel into another function LL_ADC_xxx:
02438   *           the returned channel number is only partly formatted on definition
02439   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
02440   *           with parts of literals LL_ADC_CHANNEL_x or using
02441   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
02442   *           Then the selected literal LL_ADC_CHANNEL_x can be used
02443   *           as parameter for another function.
02444   *         - To get the channel number in decimal format:
02445   *           process the returned value with the helper macro
02446   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
02447   * @note   On STM32WB, some fast channels are available: fast analog inputs
02448   *         coming from GPIO pads (ADC_IN1..5).
02449   * @rmtoll OFR1     OFFSET1_CH     LL_ADC_GetOffsetChannel\n
02450   *         OFR2     OFFSET2_CH     LL_ADC_GetOffsetChannel\n
02451   *         OFR3     OFFSET3_CH     LL_ADC_GetOffsetChannel\n
02452   *         OFR4     OFFSET4_CH     LL_ADC_GetOffsetChannel
02453   * @param  ADCx ADC instance
02454   * @param  Offsety This parameter can be one of the following values:
02455   *         @arg @ref LL_ADC_OFFSET_1
02456   *         @arg @ref LL_ADC_OFFSET_2
02457   *         @arg @ref LL_ADC_OFFSET_3
02458   *         @arg @ref LL_ADC_OFFSET_4
02459   * @retval Returned value can be one of the following values:
02460   *         @arg @ref LL_ADC_CHANNEL_0
02461   *         @arg @ref LL_ADC_CHANNEL_1            (7)
02462   *         @arg @ref LL_ADC_CHANNEL_2            (7)
02463   *         @arg @ref LL_ADC_CHANNEL_3            (7)
02464   *         @arg @ref LL_ADC_CHANNEL_4            (7)
02465   *         @arg @ref LL_ADC_CHANNEL_5            (7)
02466   *         @arg @ref LL_ADC_CHANNEL_6
02467   *         @arg @ref LL_ADC_CHANNEL_7
02468   *         @arg @ref LL_ADC_CHANNEL_8
02469   *         @arg @ref LL_ADC_CHANNEL_9
02470   *         @arg @ref LL_ADC_CHANNEL_10
02471   *         @arg @ref LL_ADC_CHANNEL_11
02472   *         @arg @ref LL_ADC_CHANNEL_12
02473   *         @arg @ref LL_ADC_CHANNEL_13
02474   *         @arg @ref LL_ADC_CHANNEL_14
02475   *         @arg @ref LL_ADC_CHANNEL_15
02476   *         @arg @ref LL_ADC_CHANNEL_16
02477   *         @arg @ref LL_ADC_CHANNEL_17
02478   *         @arg @ref LL_ADC_CHANNEL_18
02479   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
02480   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
02481   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
02482   *
02483   *         (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
02484   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
02485   *         (4) For ADC channel read back from ADC register,
02486   *             comparison with internal channel parameter to be done
02487   *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
02488   */
02489 __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)
02490 {
02491   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
02492
02493   return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
02494 }
02495
02496 /**
02497   * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:
02498   *         Offset level (offset to be subtracted from the raw
02499   *         converted data).
02500   * @note   Caution: Offset format is dependent to ADC resolution:
02501   *         offset has to be left-aligned on bit 11, the LSB (right bits)
02502   *         are set to 0.
02503   * @rmtoll OFR1     OFFSET1        LL_ADC_GetOffsetLevel\n
02504   *         OFR2     OFFSET2        LL_ADC_GetOffsetLevel\n
02505   *         OFR3     OFFSET3        LL_ADC_GetOffsetLevel\n
02506   *         OFR4     OFFSET4        LL_ADC_GetOffsetLevel
02507   * @param  ADCx ADC instance
02508   * @param  Offsety This parameter can be one of the following values:
02509   *         @arg @ref LL_ADC_OFFSET_1
02510   *         @arg @ref LL_ADC_OFFSET_2
02511   *         @arg @ref LL_ADC_OFFSET_3
02512   *         @arg @ref LL_ADC_OFFSET_4
02513   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
02514   */
02515 __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)
02516 {
02517   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
02518
02519   return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
02520 }
02521
02522 /**
02523   * @brief  Set for the ADC selected offset number 1, 2, 3 or 4:
02524   *         force offset state disable or enable
02525   *         without modifying offset channel or offset value.
02526   * @note   This function should be needed only in case of offset to be
02527   *         enabled-disabled dynamically, and should not be needed in other cases:
02528   *         function LL_ADC_SetOffset() automatically enables the offset.
02529   * @note   On this STM32 serie, setting of this feature is conditioned to
02530   *         ADC state:
02531   *         ADC must be disabled or enabled without conversion on going
02532   *         on either groups regular or injected.
02533   * @rmtoll OFR1     OFFSET1_EN     LL_ADC_SetOffsetState\n
02534   *         OFR2     OFFSET2_EN     LL_ADC_SetOffsetState\n
02535   *         OFR3     OFFSET3_EN     LL_ADC_SetOffsetState\n
02536   *         OFR4     OFFSET4_EN     LL_ADC_SetOffsetState
02537   * @param  ADCx ADC instance
02538   * @param  Offsety This parameter can be one of the following values:
02539   *         @arg @ref LL_ADC_OFFSET_1
02540   *         @arg @ref LL_ADC_OFFSET_2
02541   *         @arg @ref LL_ADC_OFFSET_3
02542   *         @arg @ref LL_ADC_OFFSET_4
02543   * @param  OffsetState This parameter can be one of the following values:
02544   *         @arg @ref LL_ADC_OFFSET_DISABLE
02545   *         @arg @ref LL_ADC_OFFSET_ENABLE
02546   * @retval None
02547   */
02548 __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
02549 {
02550   register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
02551
02552   MODIFY_REG(*preg,
02553              ADC_OFR1_OFFSET1_EN,
02554              OffsetState);
02555 }
02556
02557 /**
02558   * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:
02559   *         offset state disabled or enabled.
02560   * @rmtoll OFR1     OFFSET1_EN     LL_ADC_GetOffsetState\n
02561   *         OFR2     OFFSET2_EN     LL_ADC_GetOffsetState\n
02562   *         OFR3     OFFSET3_EN     LL_ADC_GetOffsetState\n
02563   *         OFR4     OFFSET4_EN     LL_ADC_GetOffsetState
02564   * @param  ADCx ADC instance
02565   * @param  Offsety This parameter can be one of the following values:
02566   *         @arg @ref LL_ADC_OFFSET_1
02567   *         @arg @ref LL_ADC_OFFSET_2
02568   *         @arg @ref LL_ADC_OFFSET_3
02569   *         @arg @ref LL_ADC_OFFSET_4
02570   * @retval Returned value can be one of the following values:
02571   *         @arg @ref LL_ADC_OFFSET_DISABLE
02572   *         @arg @ref LL_ADC_OFFSET_ENABLE
02573   */
02574 __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety)
02575 {
02576   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
02577
02578   return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN);
02579 }
02580
02581
02582 /**
02583   * @}
02584   */
02585
02586 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
02587   * @{
02588   */
02589
02590 /**
02591   * @brief  Set ADC group regular conversion trigger source:
02592   *         internal (SW start) or from external peripheral (timer event,
02593   *         external interrupt line).
02594   * @note   On this STM32 serie, setting trigger source to external trigger
02595   *         also set trigger polarity to rising edge
02596   *         (default setting for compatibility with some ADC on other
02597   *         STM32 families having this setting set by HW default value).
02598   *         In case of need to modify trigger edge, use
02599   *         function @ref LL_ADC_REG_SetTriggerEdge().
02600   * @note   Availability of parameters of trigger sources from timer
02601   *         depends on timers availability on the selected device.
02602   * @note   On this STM32 serie, setting of this feature is conditioned to
02603   *         ADC state:
02604   *         ADC must be disabled or enabled without conversion on going
02605   *         on group regular.
02606   * @rmtoll CFGR     EXTSEL         LL_ADC_REG_SetTriggerSource\n
02607   *         CFGR     EXTEN          LL_ADC_REG_SetTriggerSource
02608   * @param  ADCx ADC instance
02609   * @param  TriggerSource This parameter can be one of the following values:
02610   *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE
02611   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
02612   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
02613   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
02614   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
02615   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
02616   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
02617   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
02618   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
02619   * @retval None
02620   */
02621 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
02622 {
02623   MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
02624 }
02625
02626 /**
02627   * @brief  Get ADC group regular conversion trigger source:
02628   *         internal (SW start) or from external peripheral (timer event,
02629   *         external interrupt line).
02630   * @note   To determine whether group regular trigger source is
02631   *         internal (SW start) or external, without detail
02632   *         of which peripheral is selected as external trigger,
02633   *         (equivalent to
02634   *         "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
02635   *         use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
02636   * @note   Availability of parameters of trigger sources from timer
02637   *         depends on timers availability on the selected device.
02638   * @rmtoll CFGR     EXTSEL         LL_ADC_REG_GetTriggerSource\n
02639   *         CFGR     EXTEN          LL_ADC_REG_GetTriggerSource
02640   * @param  ADCx ADC instance
02641   * @retval Returned value can be one of the following values:
02642   *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE
02643   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
02644   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
02645   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
02646   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
02647   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
02648   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
02649   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
02650   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
02651   */
02652 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
02653 {
02654   register __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
02655
02656   /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */
02657   /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}.                            */
02658   register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
02659
02660   /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL         */
02661   /* to match with triggers literals definition.                              */
02662   return ((TriggerSource
02663            & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL)
02664           | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN)
02665          );
02666 }
02667
02668 /**
02669   * @brief  Get ADC group regular conversion trigger source internal (SW start)
02670   *         or external.
02671   * @note   In case of group regular trigger source set to external trigger,
02672   *         to determine which peripheral is selected as external trigger,
02673   *         use function @ref LL_ADC_REG_GetTriggerSource().
02674   * @rmtoll CFGR     EXTEN          LL_ADC_REG_IsTriggerSourceSWStart
02675   * @param  ADCx ADC instance
02676   * @retval Value "0" if trigger source external trigger
02677   *         Value "1" if trigger source SW start.
02678   */
02679 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
02680 {
02681   return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
02682 }
02683
02684 /**
02685   * @brief  Set ADC group regular conversion trigger polarity.
02686   * @note   Applicable only for trigger source set to external trigger.
02687   * @note   On this STM32 serie, setting of this feature is conditioned to
02688   *         ADC state:
02689   *         ADC must be disabled or enabled without conversion on going
02690   *         on group regular.
02691   * @rmtoll CFGR     EXTEN          LL_ADC_REG_SetTriggerEdge
02692   * @param  ADCx ADC instance
02693   * @param  ExternalTriggerEdge This parameter can be one of the following values:
02694   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING
02695   *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
02696   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
02697   * @retval None
02698   */
02699 __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
02700 {
02701   MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
02702 }
02703
02704 /**
02705   * @brief  Get ADC group regular conversion trigger polarity.
02706   * @note   Applicable only for trigger source set to external trigger.
02707   * @rmtoll CFGR     EXTEN          LL_ADC_REG_GetTriggerEdge
02708   * @param  ADCx ADC instance
02709   * @retval Returned value can be one of the following values:
02710   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING
02711   *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
02712   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
02713   */
02714 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
02715 {
02716   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
02717 }
02718
02719 /**
02720   * @brief  Set ADC group regular sequencer length and scan direction.
02721   * @note   Description of ADC group regular sequencer features:
02722   *         - For devices with sequencer fully configurable
02723   *           (function "LL_ADC_REG_SetSequencerRanks()" available):
02724   *           sequencer length and each rank affectation to a channel
02725   *           are configurable.
02726   *           This function performs configuration of:
02727   *           - Sequence length: Number of ranks in the scan sequence.
02728   *           - Sequence direction: Unless specified in parameters, sequencer
02729   *             scan direction is forward (from rank 1 to rank n).
02730   *           Sequencer ranks are selected using
02731   *           function "LL_ADC_REG_SetSequencerRanks()".
02732   *         - For devices with sequencer not fully configurable
02733   *           (function "LL_ADC_REG_SetSequencerChannels()" available):
02734   *           sequencer length and each rank affectation to a channel
02735   *           are defined by channel number.
02736   *           This function performs configuration of:
02737   *           - Sequence length: Number of ranks in the scan sequence is
02738   *             defined by number of channels set in the sequence,
02739   *             rank of each channel is fixed by channel HW number.
02740   *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
02741   *           - Sequence direction: Unless specified in parameters, sequencer
02742   *             scan direction is forward (from lowest channel number to
02743   *             highest channel number).
02744   *           Sequencer ranks are selected using
02745   *           function "LL_ADC_REG_SetSequencerChannels()".
02746   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
02747   *         ADC conversion on only 1 channel.
02748   * @note   On this STM32 serie, setting of this feature is conditioned to
02749   *         ADC state:
02750   *         ADC must be disabled or enabled without conversion on going
02751   *         on group regular.
02752   * @rmtoll SQR1     L              LL_ADC_REG_SetSequencerLength
02753   * @param  ADCx ADC instance
02754   * @param  SequencerNbRanks This parameter can be one of the following values:
02755   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
02756   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
02757   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
02758   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
02759   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
02760   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
02761   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
02762   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
02763   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
02764   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
02765   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
02766   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
02767   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
02768   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
02769   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
02770   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
02771   * @retval None
02772   */
02773 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
02774 {
02775   MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
02776 }
02777
02778 /**
02779   * @brief  Get ADC group regular sequencer length and scan direction.
02780   * @note   Description of ADC group regular sequencer features:
02781   *         - For devices with sequencer fully configurable
02782   *           (function "LL_ADC_REG_SetSequencerRanks()" available):
02783   *           sequencer length and each rank affectation to a channel
02784   *           are configurable.
02785   *           This function retrieves:
02786   *           - Sequence length: Number of ranks in the scan sequence.
02787   *           - Sequence direction: Unless specified in parameters, sequencer
02788   *             scan direction is forward (from rank 1 to rank n).
02789   *           Sequencer ranks are selected using
02790   *           function "LL_ADC_REG_SetSequencerRanks()".
02791   *         - For devices with sequencer not fully configurable
02792   *           (function "LL_ADC_REG_SetSequencerChannels()" available):
02793   *           sequencer length and each rank affectation to a channel
02794   *           are defined by channel number.
02795   *           This function retrieves:
02796   *           - Sequence length: Number of ranks in the scan sequence is
02797   *             defined by number of channels set in the sequence,
02798   *             rank of each channel is fixed by channel HW number.
02799   *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
02800   *           - Sequence direction: Unless specified in parameters, sequencer
02801   *             scan direction is forward (from lowest channel number to
02802   *             highest channel number).
02803   *           Sequencer ranks are selected using
02804   *           function "LL_ADC_REG_SetSequencerChannels()".
02805   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
02806   *         ADC conversion on only 1 channel.
02807   * @rmtoll SQR1     L              LL_ADC_REG_GetSequencerLength
02808   * @param  ADCx ADC instance
02809   * @retval Returned value can be one of the following values:
02810   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
02811   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
02812   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
02813   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
02814   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
02815   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
02816   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
02817   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
02818   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
02819   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
02820   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
02821   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
02822   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
02823   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
02824   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
02825   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
02826   */
02827 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
02828 {
02829   return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
02830 }
02831
02832 /**
02833   * @brief  Set ADC group regular sequencer discontinuous mode:
02834   *         sequence subdivided and scan conversions interrupted every selected
02835   *         number of ranks.
02836   * @note   It is not possible to enable both ADC group regular
02837   *         continuous mode and sequencer discontinuous mode.
02838   * @note   It is not possible to enable both ADC auto-injected mode
02839   *         and ADC group regular sequencer discontinuous mode.
02840   * @note   On this STM32 serie, setting of this feature is conditioned to
02841   *         ADC state:
02842   *         ADC must be disabled or enabled without conversion on going
02843   *         on group regular.
02844   * @rmtoll CFGR     DISCEN         LL_ADC_REG_SetSequencerDiscont\n
02845   *         CFGR     DISCNUM        LL_ADC_REG_SetSequencerDiscont
02846   * @param  ADCx ADC instance
02847   * @param  SeqDiscont This parameter can be one of the following values:
02848   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
02849   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
02850   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
02851   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
02852   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
02853   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
02854   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
02855   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
02856   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
02857   * @retval None
02858   */
02859 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
02860 {
02861   MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
02862 }
02863
02864 /**
02865   * @brief  Get ADC group regular sequencer discontinuous mode:
02866   *         sequence subdivided and scan conversions interrupted every selected
02867   *         number of ranks.
02868   * @rmtoll CFGR     DISCEN         LL_ADC_REG_GetSequencerDiscont\n
02869   *         CFGR     DISCNUM        LL_ADC_REG_GetSequencerDiscont
02870   * @param  ADCx ADC instance
02871   * @retval Returned value can be one of the following values:
02872   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
02873   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
02874   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
02875   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
02876   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
02877   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
02878   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
02879   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
02880   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
02881   */
02882 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
02883 {
02884   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
02885 }
02886
02887 /**
02888   * @brief  Set ADC group regular sequence: channel on the selected
02889   *         scan sequence rank.
02890   * @note   This function performs configuration of:
02891   *         - Channels ordering into each rank of scan sequence:
02892   *           whatever channel can be placed into whatever rank.
02893   * @note   On this STM32 serie, ADC group regular sequencer is
02894   *         fully configurable: sequencer length and each rank
02895   *         affectation to a channel are configurable.
02896   *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
02897   * @note   Depending on devices and packages, some channels may not be available.
02898   *         Refer to device datasheet for channels availability.
02899   * @note   On this STM32 serie, to measure internal channels (VrefInt,
02900   *         TempSensor, ...), measurement paths to internal channels must be
02901   *         enabled separately.
02902   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
02903   * @note   On this STM32 serie, setting of this feature is conditioned to
02904   *         ADC state:
02905   *         ADC must be disabled or enabled without conversion on going
02906   *         on group regular.
02907   * @rmtoll SQR1     SQ1            LL_ADC_REG_SetSequencerRanks\n
02908   *         SQR1     SQ2            LL_ADC_REG_SetSequencerRanks\n
02909   *         SQR1     SQ3            LL_ADC_REG_SetSequencerRanks\n
02910   *         SQR1     SQ4            LL_ADC_REG_SetSequencerRanks\n
02911   *         SQR2     SQ5            LL_ADC_REG_SetSequencerRanks\n
02912   *         SQR2     SQ6            LL_ADC_REG_SetSequencerRanks\n
02913   *         SQR2     SQ7            LL_ADC_REG_SetSequencerRanks\n
02914   *         SQR2     SQ8            LL_ADC_REG_SetSequencerRanks\n
02915   *         SQR2     SQ9            LL_ADC_REG_SetSequencerRanks\n
02916   *         SQR3     SQ10           LL_ADC_REG_SetSequencerRanks\n
02917   *         SQR3     SQ11           LL_ADC_REG_SetSequencerRanks\n
02918   *         SQR3     SQ12           LL_ADC_REG_SetSequencerRanks\n
02919   *         SQR3     SQ13           LL_ADC_REG_SetSequencerRanks\n
02920   *         SQR3     SQ14           LL_ADC_REG_SetSequencerRanks\n
02921   *         SQR4     SQ15           LL_ADC_REG_SetSequencerRanks\n
02922   *         SQR4     SQ16           LL_ADC_REG_SetSequencerRanks
02923   * @param  ADCx ADC instance
02924   * @param  Rank This parameter can be one of the following values:
02925   *         @arg @ref LL_ADC_REG_RANK_1
02926   *         @arg @ref LL_ADC_REG_RANK_2
02927   *         @arg @ref LL_ADC_REG_RANK_3
02928   *         @arg @ref LL_ADC_REG_RANK_4
02929   *         @arg @ref LL_ADC_REG_RANK_5
02930   *         @arg @ref LL_ADC_REG_RANK_6
02931   *         @arg @ref LL_ADC_REG_RANK_7
02932   *         @arg @ref LL_ADC_REG_RANK_8
02933   *         @arg @ref LL_ADC_REG_RANK_9
02934   *         @arg @ref LL_ADC_REG_RANK_10
02935   *         @arg @ref LL_ADC_REG_RANK_11
02936   *         @arg @ref LL_ADC_REG_RANK_12
02937   *         @arg @ref LL_ADC_REG_RANK_13
02938   *         @arg @ref LL_ADC_REG_RANK_14
02939   *         @arg @ref LL_ADC_REG_RANK_15
02940   *         @arg @ref LL_ADC_REG_RANK_16
02941   * @param  Channel This parameter can be one of the following values:
02942   *         @arg @ref LL_ADC_CHANNEL_0
02943   *         @arg @ref LL_ADC_CHANNEL_1            (7)
02944   *         @arg @ref LL_ADC_CHANNEL_2            (7)
02945   *         @arg @ref LL_ADC_CHANNEL_3            (7)
02946   *         @arg @ref LL_ADC_CHANNEL_4            (7)
02947   *         @arg @ref LL_ADC_CHANNEL_5            (7)
02948   *         @arg @ref LL_ADC_CHANNEL_6
02949   *         @arg @ref LL_ADC_CHANNEL_7
02950   *         @arg @ref LL_ADC_CHANNEL_8
02951   *         @arg @ref LL_ADC_CHANNEL_9
02952   *         @arg @ref LL_ADC_CHANNEL_10
02953   *         @arg @ref LL_ADC_CHANNEL_11
02954   *         @arg @ref LL_ADC_CHANNEL_12
02955   *         @arg @ref LL_ADC_CHANNEL_13
02956   *         @arg @ref LL_ADC_CHANNEL_14
02957   *         @arg @ref LL_ADC_CHANNEL_15
02958   *         @arg @ref LL_ADC_CHANNEL_16
02959   *         @arg @ref LL_ADC_CHANNEL_17
02960   *         @arg @ref LL_ADC_CHANNEL_18
02961   *         @arg @ref LL_ADC_CHANNEL_VREFINT
02962   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
02963   *         @arg @ref LL_ADC_CHANNEL_VBAT
02964   *
02965   *         (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
02966   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
02967   * @retval None
02968   */
02969 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
02970 {
02971   /* Set bits with content of parameter "Channel" with bits position          */
02972   /* in register and register position depending on parameter "Rank".         */
02973   /* Parameters "Rank" and "Channel" are used with masks because containing   */
02974   /* other bits reserved for other purpose.                                   */
02975   register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
02976
02977   MODIFY_REG(*preg,
02978              ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
02979              ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
02980 }
02981
02982 /**
02983   * @brief  Get ADC group regular sequence: channel on the selected
02984   *         scan sequence rank.
02985   * @note   On this STM32 serie, ADC group regular sequencer is
02986   *         fully configurable: sequencer length and each rank
02987   *         affectation to a channel are configurable.
02988   *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
02989   * @note   Depending on devices and packages, some channels may not be available.
02990   *         Refer to device datasheet for channels availability.
02991   * @note   Usage of the returned channel number:
02992   *         - To reinject this channel into another function LL_ADC_xxx:
02993   *           the returned channel number is only partly formatted on definition
02994   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
02995   *           with parts of literals LL_ADC_CHANNEL_x or using
02996   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
02997   *           Then the selected literal LL_ADC_CHANNEL_x can be used
02998   *           as parameter for another function.
02999   *         - To get the channel number in decimal format:
03000   *           process the returned value with the helper macro
03001   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
03002   * @rmtoll SQR1     SQ1            LL_ADC_REG_GetSequencerRanks\n
03003   *         SQR1     SQ2            LL_ADC_REG_GetSequencerRanks\n
03004   *         SQR1     SQ3            LL_ADC_REG_GetSequencerRanks\n
03005   *         SQR1     SQ4            LL_ADC_REG_GetSequencerRanks\n
03006   *         SQR2     SQ5            LL_ADC_REG_GetSequencerRanks\n
03007   *         SQR2     SQ6            LL_ADC_REG_GetSequencerRanks\n
03008   *         SQR2     SQ7            LL_ADC_REG_GetSequencerRanks\n
03009   *         SQR2     SQ8            LL_ADC_REG_GetSequencerRanks\n
03010   *         SQR2     SQ9            LL_ADC_REG_GetSequencerRanks\n
03011   *         SQR3     SQ10           LL_ADC_REG_GetSequencerRanks\n
03012   *         SQR3     SQ11           LL_ADC_REG_GetSequencerRanks\n
03013   *         SQR3     SQ12           LL_ADC_REG_GetSequencerRanks\n
03014   *         SQR3     SQ13           LL_ADC_REG_GetSequencerRanks\n
03015   *         SQR3     SQ14           LL_ADC_REG_GetSequencerRanks\n
03016   *         SQR4     SQ15           LL_ADC_REG_GetSequencerRanks\n
03017   *         SQR4     SQ16           LL_ADC_REG_GetSequencerRanks
03018   * @param  ADCx ADC instance
03019   * @param  Rank This parameter can be one of the following values:
03020   *         @arg @ref LL_ADC_REG_RANK_1
03021   *         @arg @ref LL_ADC_REG_RANK_2
03022   *         @arg @ref LL_ADC_REG_RANK_3
03023   *         @arg @ref LL_ADC_REG_RANK_4
03024   *         @arg @ref LL_ADC_REG_RANK_5
03025   *         @arg @ref LL_ADC_REG_RANK_6
03026   *         @arg @ref LL_ADC_REG_RANK_7
03027   *         @arg @ref LL_ADC_REG_RANK_8
03028   *         @arg @ref LL_ADC_REG_RANK_9
03029   *         @arg @ref LL_ADC_REG_RANK_10
03030   *         @arg @ref LL_ADC_REG_RANK_11
03031   *         @arg @ref LL_ADC_REG_RANK_12
03032   *         @arg @ref LL_ADC_REG_RANK_13
03033   *         @arg @ref LL_ADC_REG_RANK_14
03034   *         @arg @ref LL_ADC_REG_RANK_15
03035   *         @arg @ref LL_ADC_REG_RANK_16
03036   * @retval Returned value can be one of the following values:
03037   *         @arg @ref LL_ADC_CHANNEL_0
03038   *         @arg @ref LL_ADC_CHANNEL_1            (7)
03039   *         @arg @ref LL_ADC_CHANNEL_2            (7)
03040   *         @arg @ref LL_ADC_CHANNEL_3            (7)
03041   *         @arg @ref LL_ADC_CHANNEL_4            (7)
03042   *         @arg @ref LL_ADC_CHANNEL_5            (7)
03043   *         @arg @ref LL_ADC_CHANNEL_6
03044   *         @arg @ref LL_ADC_CHANNEL_7
03045   *         @arg @ref LL_ADC_CHANNEL_8
03046   *         @arg @ref LL_ADC_CHANNEL_9
03047   *         @arg @ref LL_ADC_CHANNEL_10
03048   *         @arg @ref LL_ADC_CHANNEL_11
03049   *         @arg @ref LL_ADC_CHANNEL_12
03050   *         @arg @ref LL_ADC_CHANNEL_13
03051   *         @arg @ref LL_ADC_CHANNEL_14
03052   *         @arg @ref LL_ADC_CHANNEL_15
03053   *         @arg @ref LL_ADC_CHANNEL_16
03054   *         @arg @ref LL_ADC_CHANNEL_17
03055   *         @arg @ref LL_ADC_CHANNEL_18
03056   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
03057   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
03058   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
03059   *
03060   *         (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
03061   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
03062   *         (4) For ADC channel read back from ADC register,
03063   *             comparison with internal channel parameter to be done
03064   *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
03065   */
03066 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
03067 {
03068   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
03069
03070   return (uint32_t)((READ_BIT(*preg,
03071                               ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
03072                      >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
03073                    );
03074 }
03075
03076 /**
03077   * @brief  Set ADC continuous conversion mode on ADC group regular.
03078   * @note   Description of ADC continuous conversion mode:
03079   *         - single mode: one conversion per trigger
03080   *         - continuous mode: after the first trigger, following
03081   *           conversions launched successively automatically.
03082   * @note   It is not possible to enable both ADC group regular
03083   *         continuous mode and sequencer discontinuous mode.
03084   * @note   On this STM32 serie, setting of this feature is conditioned to
03085   *         ADC state:
03086   *         ADC must be disabled or enabled without conversion on going
03087   *         on group regular.
03088   * @rmtoll CFGR     CONT           LL_ADC_REG_SetContinuousMode
03089   * @param  ADCx ADC instance
03090   * @param  Continuous This parameter can be one of the following values:
03091   *         @arg @ref LL_ADC_REG_CONV_SINGLE
03092   *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
03093   * @retval None
03094   */
03095 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
03096 {
03097   MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
03098 }
03099
03100 /**
03101   * @brief  Get ADC continuous conversion mode on ADC group regular.
03102   * @note   Description of ADC continuous conversion mode:
03103   *         - single mode: one conversion per trigger
03104   *         - continuous mode: after the first trigger, following
03105   *           conversions launched successively automatically.
03106   * @rmtoll CFGR     CONT           LL_ADC_REG_GetContinuousMode
03107   * @param  ADCx ADC instance
03108   * @retval Returned value can be one of the following values:
03109   *         @arg @ref LL_ADC_REG_CONV_SINGLE
03110   *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
03111   */
03112 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
03113 {
03114   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
03115 }
03116
03117 /**
03118   * @brief  Set ADC group regular conversion data transfer: no transfer or
03119   *         transfer by DMA, and DMA requests mode.
03120   * @note   If transfer by DMA selected, specifies the DMA requests
03121   *         mode:
03122   *         - Limited mode (One shot mode): DMA transfer requests are stopped
03123   *           when number of DMA data transfers (number of
03124   *           ADC conversions) is reached.
03125   *           This ADC mode is intended to be used with DMA mode non-circular.
03126   *         - Unlimited mode: DMA transfer requests are unlimited,
03127   *           whatever number of DMA data transfers (number of
03128   *           ADC conversions).
03129   *           This ADC mode is intended to be used with DMA mode circular.
03130   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
03131   *         mode non-circular:
03132   *         when DMA transfers size will be reached, DMA will stop transfers of
03133   *         ADC conversions data ADC will raise an overrun error
03134   *        (overrun flag and interruption if enabled).
03135   * @note   To configure DMA source address (peripheral address),
03136   *         use function @ref LL_ADC_DMA_GetRegAddr().
03137   * @note   On this STM32 serie, setting of this feature is conditioned to
03138   *         ADC state:
03139   *         ADC must be disabled or enabled without conversion on going
03140   *         on either groups regular or injected.
03141   * @rmtoll CFGR     DMAEN          LL_ADC_REG_SetDMATransfer\n
03142   *         CFGR     DMACFG         LL_ADC_REG_SetDMATransfer
03143   * @param  ADCx ADC instance
03144   * @param  DMATransfer This parameter can be one of the following values:
03145   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
03146   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
03147   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
03148   * @retval None
03149   */
03150 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
03151 {
03152   MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer);
03153 }
03154
03155 /**
03156   * @brief  Get ADC group regular conversion data transfer: no transfer or
03157   *         transfer by DMA, and DMA requests mode.
03158   * @note   If transfer by DMA selected, specifies the DMA requests
03159   *         mode:
03160   *         - Limited mode (One shot mode): DMA transfer requests are stopped
03161   *           when number of DMA data transfers (number of
03162   *           ADC conversions) is reached.
03163   *           This ADC mode is intended to be used with DMA mode non-circular.
03164   *         - Unlimited mode: DMA transfer requests are unlimited,
03165   *           whatever number of DMA data transfers (number of
03166   *           ADC conversions).
03167   *           This ADC mode is intended to be used with DMA mode circular.
03168   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
03169   *         mode non-circular:
03170   *         when DMA transfers size will be reached, DMA will stop transfers of
03171   *         ADC conversions data ADC will raise an overrun error
03172   *         (overrun flag and interruption if enabled).
03173   * @note   To configure DMA source address (peripheral address),
03174   *         use function @ref LL_ADC_DMA_GetRegAddr().
03175   * @rmtoll CFGR     DMAEN          LL_ADC_REG_GetDMATransfer\n
03176   *         CFGR     DMACFG         LL_ADC_REG_GetDMATransfer
03177   * @param  ADCx ADC instance
03178   * @retval Returned value can be one of the following values:
03179   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
03180   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
03181   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
03182   */
03183 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
03184 {
03185   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG));
03186 }
03187
03188
03189 /**
03190   * @brief  Set ADC group regular behavior in case of overrun:
03191   *         data preserved or overwritten.
03192   * @note   Compatibility with devices without feature overrun:
03193   *         other devices without this feature have a behavior
03194   *         equivalent to data overwritten.
03195   *         The default setting of overrun is data preserved.
03196   *         Therefore, for compatibility with all devices, parameter
03197   *         overrun should be set to data overwritten.
03198   * @note   On this STM32 serie, setting of this feature is conditioned to
03199   *         ADC state:
03200   *         ADC must be disabled or enabled without conversion on going
03201   *         on group regular.
03202   * @rmtoll CFGR     OVRMOD         LL_ADC_REG_SetOverrun
03203   * @param  ADCx ADC instance
03204   * @param  Overrun This parameter can be one of the following values:
03205   *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
03206   *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
03207   * @retval None
03208   */
03209 __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
03210 {
03211   MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
03212 }
03213
03214 /**
03215   * @brief  Get ADC group regular behavior in case of overrun:
03216   *         data preserved or overwritten.
03217   * @rmtoll CFGR     OVRMOD         LL_ADC_REG_GetOverrun
03218   * @param  ADCx ADC instance
03219   * @retval Returned value can be one of the following values:
03220   *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
03221   *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
03222   */
03223 __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
03224 {
03225   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
03226 }
03227
03228 /**
03229   * @}
03230   */
03231
03232 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
03233   * @{
03234   */
03235
03236 /**
03237   * @brief  Set ADC group injected conversion trigger source:
03238   *         internal (SW start) or from external peripheral (timer event,
03239   *         external interrupt line).
03240   * @note   On this STM32 serie, setting trigger source to external trigger
03241   *         also set trigger polarity to rising edge
03242   *         (default setting for compatibility with some ADC on other
03243   *         STM32 families having this setting set by HW default value).
03244   *         In case of need to modify trigger edge, use
03245   *         function @ref LL_ADC_INJ_SetTriggerEdge().
03246   * @note   Availability of parameters of trigger sources from timer
03247   *         depends on timers availability on the selected device.
03248   * @note   On this STM32 serie, setting of this feature is conditioned to
03249   *         ADC state:
03250   *         ADC must not be disabled. Can be enabled with or without conversion
03251   *         on going on either groups regular or injected.
03252   * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_SetTriggerSource\n
03253   *         JSQR     JEXTEN         LL_ADC_INJ_SetTriggerSource
03254   * @param  ADCx ADC instance
03255   * @param  TriggerSource This parameter can be one of the following values:
03256   *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
03257   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
03258   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
03259   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
03260   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
03261   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
03262   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
03263   * @retval None
03264   */
03265 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
03266 {
03267   MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
03268 }
03269
03270 /**
03271   * @brief  Get ADC group injected conversion trigger source:
03272   *         internal (SW start) or from external peripheral (timer event,
03273   *         external interrupt line).
03274   * @note   To determine whether group injected trigger source is
03275   *         internal (SW start) or external, without detail
03276   *         of which peripheral is selected as external trigger,
03277   *         (equivalent to
03278   *         "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
03279   *         use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
03280   * @note   Availability of parameters of trigger sources from timer
03281   *         depends on timers availability on the selected device.
03282   * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_GetTriggerSource\n
03283   *         JSQR     JEXTEN         LL_ADC_INJ_GetTriggerSource
03284   * @param  ADCx ADC instance
03285   * @retval Returned value can be one of the following values:
03286   *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
03287   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
03288   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
03289   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
03290   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
03291   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
03292   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
03293   */
03294 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
03295 {
03296   register __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
03297
03298   /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */
03299   /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}.                           */
03300   register uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
03301
03302   /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL       */
03303   /* to match with triggers literals definition.                              */
03304   return ((TriggerSource
03305            & (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL)
03306           | ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN)
03307          );
03308 }
03309
03310 /**
03311   * @brief  Get ADC group injected conversion trigger source internal (SW start)
03312             or external
03313   * @note   In case of group injected trigger source set to external trigger,
03314   *         to determine which peripheral is selected as external trigger,
03315   *         use function @ref LL_ADC_INJ_GetTriggerSource.
03316   * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_IsTriggerSourceSWStart
03317   * @param  ADCx ADC instance
03318   * @retval Value "0" if trigger source external trigger
03319   *         Value "1" if trigger source SW start.
03320   */
03321 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
03322 {
03323   return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);
03324 }
03325
03326 /**
03327   * @brief  Set ADC group injected conversion trigger polarity.
03328   *         Applicable only for trigger source set to external trigger.
03329   * @note   On this STM32 serie, setting of this feature is conditioned to
03330   *         ADC state:
03331   *         ADC must not be disabled. Can be enabled with or without conversion
03332   *         on going on either groups regular or injected.
03333   * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_SetTriggerEdge
03334   * @param  ADCx ADC instance
03335   * @param  ExternalTriggerEdge This parameter can be one of the following values:
03336   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
03337   *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
03338   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
03339   * @retval None
03340   */
03341 __STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
03342 {
03343   MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
03344 }
03345
03346 /**
03347   * @brief  Get ADC group injected conversion trigger polarity.
03348   *         Applicable only for trigger source set to external trigger.
03349   * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_GetTriggerEdge
03350   * @param  ADCx ADC instance
03351   * @retval Returned value can be one of the following values:
03352   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
03353   *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
03354   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
03355   */
03356 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
03357 {
03358   return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
03359 }
03360
03361 /**
03362   * @brief  Set ADC group injected sequencer length and scan direction.
03363   * @note   This function performs configuration of:
03364   *         - Sequence length: Number of ranks in the scan sequence.
03365   *         - Sequence direction: Unless specified in parameters, sequencer
03366   *           scan direction is forward (from rank 1 to rank n).
03367   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
03368   *         ADC conversion on only 1 channel.
03369   * @note   On this STM32 serie, setting of this feature is conditioned to
03370   *         ADC state:
03371   *         ADC must not be disabled. Can be enabled with or without conversion
03372   *         on going on either groups regular or injected.
03373   * @rmtoll JSQR     JL             LL_ADC_INJ_SetSequencerLength
03374   * @param  ADCx ADC instance
03375   * @param  SequencerNbRanks This parameter can be one of the following values:
03376   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
03377   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
03378   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
03379   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
03380   * @retval None
03381   */
03382 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
03383 {
03384   MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
03385 }
03386
03387 /**
03388   * @brief  Get ADC group injected sequencer length and scan direction.
03389   * @note   This function retrieves:
03390   *         - Sequence length: Number of ranks in the scan sequence.
03391   *         - Sequence direction: Unless specified in parameters, sequencer
03392   *           scan direction is forward (from rank 1 to rank n).
03393   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
03394   *         ADC conversion on only 1 channel.
03395   * @rmtoll JSQR     JL             LL_ADC_INJ_GetSequencerLength
03396   * @param  ADCx ADC instance
03397   * @retval Returned value can be one of the following values:
03398   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
03399   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
03400   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
03401   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
03402   */
03403 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
03404 {
03405   return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
03406 }
03407
03408 /**
03409   * @brief  Set ADC group injected sequencer discontinuous mode:
03410   *         sequence subdivided and scan conversions interrupted every selected
03411   *         number of ranks.
03412   * @note   It is not possible to enable both ADC group injected
03413   *         auto-injected mode and sequencer discontinuous mode.
03414   * @rmtoll CFGR     JDISCEN        LL_ADC_INJ_SetSequencerDiscont
03415   * @param  ADCx ADC instance
03416   * @param  SeqDiscont This parameter can be one of the following values:
03417   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
03418   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
03419   * @retval None
03420   */
03421 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
03422 {
03423   MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
03424 }
03425
03426 /**
03427   * @brief  Get ADC group injected sequencer discontinuous mode:
03428   *         sequence subdivided and scan conversions interrupted every selected
03429   *         number of ranks.
03430   * @rmtoll CFGR     JDISCEN        LL_ADC_INJ_GetSequencerDiscont
03431   * @param  ADCx ADC instance
03432   * @retval Returned value can be one of the following values:
03433   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
03434   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
03435   */
03436 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
03437 {
03438   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
03439 }
03440
03441 /**
03442   * @brief  Set ADC group injected sequence: channel on the selected
03443   *         sequence rank.
03444   * @note   Depending on devices and packages, some channels may not be available.
03445   *         Refer to device datasheet for channels availability.
03446   * @note   On this STM32 serie, to measure internal channels (VrefInt,
03447   *         TempSensor, ...), measurement paths to internal channels must be
03448   *         enabled separately.
03449   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
03450   * @note   On STM32WB, some fast channels are available: fast analog inputs
03451   *         coming from GPIO pads (ADC_IN1..5).
03452   * @note   On this STM32 serie, setting of this feature is conditioned to
03453   *         ADC state:
03454   *         ADC must not be disabled. Can be enabled with or without conversion
03455   *         on going on either groups regular or injected.
03456   * @rmtoll JSQR     JSQ1           LL_ADC_INJ_SetSequencerRanks\n
03457   *         JSQR     JSQ2           LL_ADC_INJ_SetSequencerRanks\n
03458   *         JSQR     JSQ3           LL_ADC_INJ_SetSequencerRanks\n
03459   *         JSQR     JSQ4           LL_ADC_INJ_SetSequencerRanks
03460   * @param  ADCx ADC instance
03461   * @param  Rank This parameter can be one of the following values:
03462   *         @arg @ref LL_ADC_INJ_RANK_1
03463   *         @arg @ref LL_ADC_INJ_RANK_2
03464   *         @arg @ref LL_ADC_INJ_RANK_3
03465   *         @arg @ref LL_ADC_INJ_RANK_4
03466   * @param  Channel This parameter can be one of the following values:
03467   *         @arg @ref LL_ADC_CHANNEL_0
03468   *         @arg @ref LL_ADC_CHANNEL_1            (7)
03469   *         @arg @ref LL_ADC_CHANNEL_2            (7)
03470   *         @arg @ref LL_ADC_CHANNEL_3            (7)
03471   *         @arg @ref LL_ADC_CHANNEL_4            (7)
03472   *         @arg @ref LL_ADC_CHANNEL_5            (7)
03473   *         @arg @ref LL_ADC_CHANNEL_6
03474   *         @arg @ref LL_ADC_CHANNEL_7
03475   *         @arg @ref LL_ADC_CHANNEL_8
03476   *         @arg @ref LL_ADC_CHANNEL_9
03477   *         @arg @ref LL_ADC_CHANNEL_10
03478   *         @arg @ref LL_ADC_CHANNEL_11
03479   *         @arg @ref LL_ADC_CHANNEL_12
03480   *         @arg @ref LL_ADC_CHANNEL_13
03481   *         @arg @ref LL_ADC_CHANNEL_14
03482   *         @arg @ref LL_ADC_CHANNEL_15
03483   *         @arg @ref LL_ADC_CHANNEL_16
03484   *         @arg @ref LL_ADC_CHANNEL_17
03485   *         @arg @ref LL_ADC_CHANNEL_18
03486   *         @arg @ref LL_ADC_CHANNEL_VREFINT
03487   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
03488   *         @arg @ref LL_ADC_CHANNEL_VBAT
03489   *
03490   *         (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
03491   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
03492   * @retval None
03493   */
03494 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
03495 {
03496   /* Set bits with content of parameter "Channel" with bits position          */
03497   /* in register depending on parameter "Rank".                               */
03498   /* Parameters "Rank" and "Channel" are used with masks because containing   */
03499   /* other bits reserved for other purpose.                                   */
03500   MODIFY_REG(ADCx->JSQR,
03501              (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
03502              ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
03503 }
03504
03505 /**
03506   * @brief  Get ADC group injected sequence: channel on the selected
03507   *         sequence rank.
03508   * @note   Depending on devices and packages, some channels may not be available.
03509   *         Refer to device datasheet for channels availability.
03510   * @note   Usage of the returned channel number:
03511   *         - To reinject this channel into another function LL_ADC_xxx:
03512   *           the returned channel number is only partly formatted on definition
03513   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
03514   *           with parts of literals LL_ADC_CHANNEL_x or using
03515   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
03516   *           Then the selected literal LL_ADC_CHANNEL_x can be used
03517   *           as parameter for another function.
03518   *         - To get the channel number in decimal format:
03519   *           process the returned value with the helper macro
03520   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
03521   * @rmtoll JSQR     JSQ1           LL_ADC_INJ_GetSequencerRanks\n
03522   *         JSQR     JSQ2           LL_ADC_INJ_GetSequencerRanks\n
03523   *         JSQR     JSQ3           LL_ADC_INJ_GetSequencerRanks\n
03524   *         JSQR     JSQ4           LL_ADC_INJ_GetSequencerRanks
03525   * @param  ADCx ADC instance
03526   * @param  Rank This parameter can be one of the following values:
03527   *         @arg @ref LL_ADC_INJ_RANK_1
03528   *         @arg @ref LL_ADC_INJ_RANK_2
03529   *         @arg @ref LL_ADC_INJ_RANK_3
03530   *         @arg @ref LL_ADC_INJ_RANK_4
03531   * @retval Returned value can be one of the following values:
03532   *         @arg @ref LL_ADC_CHANNEL_0
03533   *         @arg @ref LL_ADC_CHANNEL_1            (7)
03534   *         @arg @ref LL_ADC_CHANNEL_2            (7)
03535   *         @arg @ref LL_ADC_CHANNEL_3            (7)
03536   *         @arg @ref LL_ADC_CHANNEL_4            (7)
03537   *         @arg @ref LL_ADC_CHANNEL_5            (7)
03538   *         @arg @ref LL_ADC_CHANNEL_6
03539   *         @arg @ref LL_ADC_CHANNEL_7
03540   *         @arg @ref LL_ADC_CHANNEL_8
03541   *         @arg @ref LL_ADC_CHANNEL_9
03542   *         @arg @ref LL_ADC_CHANNEL_10
03543   *         @arg @ref LL_ADC_CHANNEL_11
03544   *         @arg @ref LL_ADC_CHANNEL_12
03545   *         @arg @ref LL_ADC_CHANNEL_13
03546   *         @arg @ref LL_ADC_CHANNEL_14
03547   *         @arg @ref LL_ADC_CHANNEL_15
03548   *         @arg @ref LL_ADC_CHANNEL_16
03549   *         @arg @ref LL_ADC_CHANNEL_17
03550   *         @arg @ref LL_ADC_CHANNEL_18
03551   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
03552   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
03553   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
03554   *
03555   *         (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
03556   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
03557   *         (4) For ADC channel read back from ADC register,
03558   *             comparison with internal channel parameter to be done
03559   *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
03560   */
03561 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
03562 {
03563   return (uint32_t)((READ_BIT(ADCx->JSQR,
03564                               (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
03565                      >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
03566                    );
03567 }
03568
03569 /**
03570   * @brief  Set ADC group injected conversion trigger:
03571   *         independent or from ADC group regular.
03572   * @note   This mode can be used to extend number of data registers
03573   *         updated after one ADC conversion trigger and with data
03574   *         permanently kept (not erased by successive conversions of scan of
03575   *         ADC sequencer ranks), up to 5 data registers:
03576   *         1 data register on ADC group regular, 4 data registers
03577   *         on ADC group injected.
03578   * @note   If ADC group injected injected trigger source is set to an
03579   *         external trigger, this feature must be must be set to
03580   *         independent trigger.
03581   *         ADC group injected automatic trigger is compliant only with
03582   *         group injected trigger source set to SW start, without any
03583   *         further action on  ADC group injected conversion start or stop:
03584   *         in this case, ADC group injected is controlled only
03585   *         from ADC group regular.
03586   * @note   It is not possible to enable both ADC group injected
03587   *         auto-injected mode and sequencer discontinuous mode.
03588   * @note   On this STM32 serie, setting of this feature is conditioned to
03589   *         ADC state:
03590   *         ADC must be disabled or enabled without conversion on going
03591   *         on either groups regular or injected.
03592   * @rmtoll CFGR     JAUTO          LL_ADC_INJ_SetTrigAuto
03593   * @param  ADCx ADC instance
03594   * @param  TrigAuto This parameter can be one of the following values:
03595   *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
03596   *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
03597   * @retval None
03598   */
03599 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
03600 {
03601   MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);
03602 }
03603
03604 /**
03605   * @brief  Get ADC group injected conversion trigger:
03606   *         independent or from ADC group regular.
03607   * @rmtoll CFGR     JAUTO          LL_ADC_INJ_GetTrigAuto
03608   * @param  ADCx ADC instance
03609   * @retval Returned value can be one of the following values:
03610   *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
03611   *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
03612   */
03613 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
03614 {
03615   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
03616 }
03617
03618 /**
03619   * @brief  Set ADC group injected contexts queue mode.
03620   * @note   A context is a setting of group injected sequencer:
03621   *         - group injected trigger
03622   *         - sequencer length
03623   *         - sequencer ranks
03624   *         If contexts queue is disabled:
03625   *         - only 1 sequence can be configured
03626   *           and is active perpetually.
03627   *         If contexts queue is enabled:
03628   *         - up to 2 contexts can be queued
03629   *           and are checked in and out as a FIFO stack (first-in, first-out).
03630   *         - If a new context is set when queues is full, error is triggered
03631   *           by interruption "Injected Queue Overflow".
03632   *         - Two behaviors are possible when all contexts have been processed:
03633   *           the contexts queue can maintain the last context active perpetually
03634   *           or can be empty and injected group triggers are disabled.
03635   *         - Triggers can be only external (not internal SW start)
03636   *         - Caution: The sequence must be fully configured in one time
03637   *           (one write of register JSQR makes a check-in of a new context
03638   *           into the queue).
03639   *           Therefore functions to set separately injected trigger and
03640   *           sequencer channels cannot be used, register JSQR must be set
03641   *           using function @ref LL_ADC_INJ_ConfigQueueContext().
03642   * @note   This parameter can be modified only when no conversion is on going
03643   *         on either groups regular or injected.
03644   * @note   A modification of the context mode (bit JQDIS) causes the contexts
03645   *         queue to be flushed and the register JSQR is cleared.
03646   * @note   On this STM32 serie, setting of this feature is conditioned to
03647   *         ADC state:
03648   *         ADC must be disabled or enabled without conversion on going
03649   *         on either groups regular or injected.
03650   * @rmtoll CFGR     JQM            LL_ADC_INJ_SetQueueMode\n
03651   *         CFGR     JQDIS          LL_ADC_INJ_SetQueueMode
03652   * @param  ADCx ADC instance
03653   * @param  QueueMode This parameter can be one of the following values:
03654   *         @arg @ref LL_ADC_INJ_QUEUE_DISABLE
03655   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
03656   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
03657   * @retval None
03658   */
03659 __STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)
03660 {
03661   MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode);
03662 }
03663
03664 /**
03665   * @brief  Get ADC group injected context queue mode.
03666   * @rmtoll CFGR     JQM            LL_ADC_INJ_GetQueueMode\n
03667   *         CFGR     JQDIS          LL_ADC_INJ_GetQueueMode
03668   * @param  ADCx ADC instance
03669   * @retval Returned value can be one of the following values:
03670   *         @arg @ref LL_ADC_INJ_QUEUE_DISABLE
03671   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
03672   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
03673   */
03674 __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)
03675 {
03676   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));
03677 }
03678
03679 /**
03680   * @brief  Set one context on ADC group injected that will be checked in
03681   *         contexts queue.
03682   * @note   A context is a setting of group injected sequencer:
03683   *         - group injected trigger
03684   *         - sequencer length
03685   *         - sequencer ranks
03686   *         This function is intended to be used when contexts queue is enabled,
03687   *         because the sequence must be fully configured in one time
03688   *         (functions to set separately injected trigger and sequencer channels
03689   *         cannot be used):
03690   *         Refer to function @ref LL_ADC_INJ_SetQueueMode().
03691   * @note   In the contexts queue, only the active context can be read.
03692   *         The parameters of this function can be read using functions:
03693   *         @arg @ref LL_ADC_INJ_GetTriggerSource()
03694   *         @arg @ref LL_ADC_INJ_GetTriggerEdge()
03695   *         @arg @ref LL_ADC_INJ_GetSequencerRanks()
03696   * @note   On this STM32 serie, to measure internal channels (VrefInt,
03697   *         TempSensor, ...), measurement paths to internal channels must be
03698   *         enabled separately.
03699   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
03700   * @note   On STM32WB, some fast channels are available: fast analog inputs
03701   *         coming from GPIO pads (ADC_IN1..5).
03702   * @note   On this STM32 serie, setting of this feature is conditioned to
03703   *         ADC state:
03704   *         ADC must not be disabled. Can be enabled with or without conversion
03705   *         on going on either groups regular or injected.
03706   * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_ConfigQueueContext\n
03707   *         JSQR     JEXTEN         LL_ADC_INJ_ConfigQueueContext\n
03708   *         JSQR     JL             LL_ADC_INJ_ConfigQueueContext\n
03709   *         JSQR     JSQ1           LL_ADC_INJ_ConfigQueueContext\n
03710   *         JSQR     JSQ2           LL_ADC_INJ_ConfigQueueContext\n
03711   *         JSQR     JSQ3           LL_ADC_INJ_ConfigQueueContext\n
03712   *         JSQR     JSQ4           LL_ADC_INJ_ConfigQueueContext
03713   * @param  ADCx ADC instance
03714   * @param  TriggerSource This parameter can be one of the following values:
03715   *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
03716   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
03717   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
03718   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
03719   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
03720   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
03721   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
03722   * @param  ExternalTriggerEdge This parameter can be one of the following values:
03723   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
03724   *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
03725   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
03726   *
03727   *         Note: This parameter is discarded in case of SW start:
03728   *               parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
03729   * @param  SequencerNbRanks This parameter can be one of the following values:
03730   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
03731   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
03732   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
03733   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
03734   * @param  Rank1_Channel This parameter can be one of the following values:
03735   *         @arg @ref LL_ADC_CHANNEL_0
03736   *         @arg @ref LL_ADC_CHANNEL_1            (7)
03737   *         @arg @ref LL_ADC_CHANNEL_2            (7)
03738   *         @arg @ref LL_ADC_CHANNEL_3            (7)
03739   *         @arg @ref LL_ADC_CHANNEL_4            (7)
03740   *         @arg @ref LL_ADC_CHANNEL_5            (7)
03741   *         @arg @ref LL_ADC_CHANNEL_6
03742   *         @arg @ref LL_ADC_CHANNEL_7
03743   *         @arg @ref LL_ADC_CHANNEL_8
03744   *         @arg @ref LL_ADC_CHANNEL_9
03745   *         @arg @ref LL_ADC_CHANNEL_10
03746   *         @arg @ref LL_ADC_CHANNEL_11
03747   *         @arg @ref LL_ADC_CHANNEL_12
03748   *         @arg @ref LL_ADC_CHANNEL_13
03749   *         @arg @ref LL_ADC_CHANNEL_14
03750   *         @arg @ref LL_ADC_CHANNEL_15
03751   *         @arg @ref LL_ADC_CHANNEL_16
03752   *         @arg @ref LL_ADC_CHANNEL_17
03753   *         @arg @ref LL_ADC_CHANNEL_18
03754   *         @arg @ref LL_ADC_CHANNEL_VREFINT
03755   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
03756   *         @arg @ref LL_ADC_CHANNEL_VBAT
03757   *
03758   *         (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
03759   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
03760   * @param  Rank2_Channel This parameter can be one of the following values:
03761   *         @arg @ref LL_ADC_CHANNEL_0
03762   *         @arg @ref LL_ADC_CHANNEL_1            (7)
03763   *         @arg @ref LL_ADC_CHANNEL_2            (7)
03764   *         @arg @ref LL_ADC_CHANNEL_3            (7)
03765   *         @arg @ref LL_ADC_CHANNEL_4            (7)
03766   *         @arg @ref LL_ADC_CHANNEL_5            (7)
03767   *         @arg @ref LL_ADC_CHANNEL_6
03768   *         @arg @ref LL_ADC_CHANNEL_7
03769   *         @arg @ref LL_ADC_CHANNEL_8
03770   *         @arg @ref LL_ADC_CHANNEL_9
03771   *         @arg @ref LL_ADC_CHANNEL_10
03772   *         @arg @ref LL_ADC_CHANNEL_11
03773   *         @arg @ref LL_ADC_CHANNEL_12
03774   *         @arg @ref LL_ADC_CHANNEL_13
03775   *         @arg @ref LL_ADC_CHANNEL_14
03776   *         @arg @ref LL_ADC_CHANNEL_15
03777   *         @arg @ref LL_ADC_CHANNEL_16
03778   *         @arg @ref LL_ADC_CHANNEL_17
03779   *         @arg @ref LL_ADC_CHANNEL_18
03780   *         @arg @ref LL_ADC_CHANNEL_VREFINT
03781   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
03782   *         @arg @ref LL_ADC_CHANNEL_VBAT
03783   *
03784   *         (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
03785   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
03786   * @param  Rank3_Channel This parameter can be one of the following values:
03787   *         @arg @ref LL_ADC_CHANNEL_0
03788   *         @arg @ref LL_ADC_CHANNEL_1            (7)
03789   *         @arg @ref LL_ADC_CHANNEL_2            (7)
03790   *         @arg @ref LL_ADC_CHANNEL_3            (7)
03791   *         @arg @ref LL_ADC_CHANNEL_4            (7)
03792   *         @arg @ref LL_ADC_CHANNEL_5            (7)
03793   *         @arg @ref LL_ADC_CHANNEL_6
03794   *         @arg @ref LL_ADC_CHANNEL_7
03795   *         @arg @ref LL_ADC_CHANNEL_8
03796   *         @arg @ref LL_ADC_CHANNEL_9
03797   *         @arg @ref LL_ADC_CHANNEL_10
03798   *         @arg @ref LL_ADC_CHANNEL_11
03799   *         @arg @ref LL_ADC_CHANNEL_12
03800   *         @arg @ref LL_ADC_CHANNEL_13
03801   *         @arg @ref LL_ADC_CHANNEL_14
03802   *         @arg @ref LL_ADC_CHANNEL_15
03803   *         @arg @ref LL_ADC_CHANNEL_16
03804   *         @arg @ref LL_ADC_CHANNEL_17
03805   *         @arg @ref LL_ADC_CHANNEL_18
03806   *         @arg @ref LL_ADC_CHANNEL_VREFINT
03807   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
03808   *         @arg @ref LL_ADC_CHANNEL_VBAT
03809   *
03810   *         (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
03811   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
03812   * @param  Rank4_Channel This parameter can be one of the following values:
03813   *         @arg @ref LL_ADC_CHANNEL_0
03814   *         @arg @ref LL_ADC_CHANNEL_1            (7)
03815   *         @arg @ref LL_ADC_CHANNEL_2            (7)
03816   *         @arg @ref LL_ADC_CHANNEL_3            (7)
03817   *         @arg @ref LL_ADC_CHANNEL_4            (7)
03818   *         @arg @ref LL_ADC_CHANNEL_5            (7)
03819   *         @arg @ref LL_ADC_CHANNEL_6
03820   *         @arg @ref LL_ADC_CHANNEL_7
03821   *         @arg @ref LL_ADC_CHANNEL_8
03822   *         @arg @ref LL_ADC_CHANNEL_9
03823   *         @arg @ref LL_ADC_CHANNEL_10
03824   *         @arg @ref LL_ADC_CHANNEL_11
03825   *         @arg @ref LL_ADC_CHANNEL_12
03826   *         @arg @ref LL_ADC_CHANNEL_13
03827   *         @arg @ref LL_ADC_CHANNEL_14
03828   *         @arg @ref LL_ADC_CHANNEL_15
03829   *         @arg @ref LL_ADC_CHANNEL_16
03830   *         @arg @ref LL_ADC_CHANNEL_17
03831   *         @arg @ref LL_ADC_CHANNEL_18
03832   *         @arg @ref LL_ADC_CHANNEL_VREFINT
03833   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
03834   *         @arg @ref LL_ADC_CHANNEL_VBAT
03835   *
03836   *         (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
03837   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
03838   * @retval None
03839   */
03840 __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
03841                                                    uint32_t TriggerSource,
03842                                                    uint32_t ExternalTriggerEdge,
03843                                                    uint32_t SequencerNbRanks,
03844                                                    uint32_t Rank1_Channel,
03845                                                    uint32_t Rank2_Channel,
03846                                                    uint32_t Rank3_Channel,
03847                                                    uint32_t Rank4_Channel)
03848 {
03849   /* Set bits with content of parameter "Rankx_Channel" with bits position    */
03850   /* in register depending on literal "LL_ADC_INJ_RANK_x".                    */
03851   /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks   */
03852   /* because containing other bits reserved for other purpose.                */
03853   /* If parameter "TriggerSource" is set to SW start, then parameter          */
03854   /* "ExternalTriggerEdge" is discarded.                                      */
03855   register uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
03856   MODIFY_REG(ADCx->JSQR,
03857              ADC_JSQR_JEXTSEL |
03858              ADC_JSQR_JEXTEN  |
03859              ADC_JSQR_JSQ4    |
03860              ADC_JSQR_JSQ3    |
03861              ADC_JSQR_JSQ2    |
03862              ADC_JSQR_JSQ1    |
03863              ADC_JSQR_JL,
03864              (TriggerSource & ADC_JSQR_JEXTSEL)          |
03865              (ExternalTriggerEdge * (is_trigger_not_sw)) |
03866              (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |
03867              (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |
03868              (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) |
03869              (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) |
03870              SequencerNbRanks
03871             );
03872 }
03873
03874 /**
03875   * @}
03876   */
03877
03878 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
03879   * @{
03880   */
03881
03882 /**
03883   * @brief  Set sampling time of the selected ADC channel
03884   *         Unit: ADC clock cycles.
03885   * @note   On this device, sampling time is on channel scope: independently
03886   *         of channel mapped on ADC group regular or injected.
03887   * @note   In case of internal channel (VrefInt, TempSensor, ...) to be
03888   *         converted:
03889   *         sampling time constraints must be respected (sampling time can be
03890   *         adjusted in function of ADC clock frequency and sampling time
03891   *         setting).
03892   *         Refer to device datasheet for timings values (parameters TS_vrefint,
03893   *         TS_temp, ...).
03894   * @note   Conversion time is the addition of sampling time and processing time.
03895   *         On this STM32 serie, ADC processing time is:
03896   *         - 12.5 ADC clock cycles at ADC resolution 12 bits
03897   *         - 10.5 ADC clock cycles at ADC resolution 10 bits
03898   *         - 8.5 ADC clock cycles at ADC resolution 8 bits
03899   *         - 6.5 ADC clock cycles at ADC resolution 6 bits
03900   * @note   In case of ADC conversion of internal channel (VrefInt,
03901   *         temperature sensor, ...), a sampling time minimum value
03902   *         is required.
03903   *         Refer to device datasheet.
03904   * @note   On this STM32 serie, setting of this feature is conditioned to
03905   *         ADC state:
03906   *         ADC must be disabled or enabled without conversion on going
03907   *         on either groups regular or injected.
03908   * @rmtoll SMPR1    SMP0           LL_ADC_SetChannelSamplingTime\n
03909   *         SMPR1    SMP1           LL_ADC_SetChannelSamplingTime\n
03910   *         SMPR1    SMP2           LL_ADC_SetChannelSamplingTime\n
03911   *         SMPR1    SMP3           LL_ADC_SetChannelSamplingTime\n
03912   *         SMPR1    SMP4           LL_ADC_SetChannelSamplingTime\n
03913   *         SMPR1    SMP5           LL_ADC_SetChannelSamplingTime\n
03914   *         SMPR1    SMP6           LL_ADC_SetChannelSamplingTime\n
03915   *         SMPR1    SMP7           LL_ADC_SetChannelSamplingTime\n
03916   *         SMPR1    SMP8           LL_ADC_SetChannelSamplingTime\n
03917   *         SMPR1    SMP9           LL_ADC_SetChannelSamplingTime\n
03918   *         SMPR2    SMP10          LL_ADC_SetChannelSamplingTime\n
03919   *         SMPR2    SMP11          LL_ADC_SetChannelSamplingTime\n
03920   *         SMPR2    SMP12          LL_ADC_SetChannelSamplingTime\n
03921   *         SMPR2    SMP13          LL_ADC_SetChannelSamplingTime\n
03922   *         SMPR2    SMP14          LL_ADC_SetChannelSamplingTime\n
03923   *         SMPR2    SMP15          LL_ADC_SetChannelSamplingTime\n
03924   *         SMPR2    SMP16          LL_ADC_SetChannelSamplingTime\n
03925   *         SMPR2    SMP17          LL_ADC_SetChannelSamplingTime\n
03926   *         SMPR2    SMP18          LL_ADC_SetChannelSamplingTime
03927   * @param  ADCx ADC instance
03928   * @param  Channel This parameter can be one of the following values:
03929   *         @arg @ref LL_ADC_CHANNEL_0
03930   *         @arg @ref LL_ADC_CHANNEL_1            (7)
03931   *         @arg @ref LL_ADC_CHANNEL_2            (7)
03932   *         @arg @ref LL_ADC_CHANNEL_3            (7)
03933   *         @arg @ref LL_ADC_CHANNEL_4            (7)
03934   *         @arg @ref LL_ADC_CHANNEL_5            (7)
03935   *         @arg @ref LL_ADC_CHANNEL_6
03936   *         @arg @ref LL_ADC_CHANNEL_7
03937   *         @arg @ref LL_ADC_CHANNEL_8
03938   *         @arg @ref LL_ADC_CHANNEL_9
03939   *         @arg @ref LL_ADC_CHANNEL_10
03940   *         @arg @ref LL_ADC_CHANNEL_11
03941   *         @arg @ref LL_ADC_CHANNEL_12
03942   *         @arg @ref LL_ADC_CHANNEL_13
03943   *         @arg @ref LL_ADC_CHANNEL_14
03944   *         @arg @ref LL_ADC_CHANNEL_15
03945   *         @arg @ref LL_ADC_CHANNEL_16
03946   *         @arg @ref LL_ADC_CHANNEL_17
03947   *         @arg @ref LL_ADC_CHANNEL_18
03948   *         @arg @ref LL_ADC_CHANNEL_VREFINT
03949   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
03950   *         @arg @ref LL_ADC_CHANNEL_VBAT
03951   *
03952   *         (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
03953   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
03954   * @param  SamplingTime This parameter can be one of the following values:
03955   *         @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5
03956   *         @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
03957   *         @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
03958   *         @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
03959   *         @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
03960   *         @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
03961   *         @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
03962   *         @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
03963   * @retval None
03964   */
03965 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
03966 {
03967   /* Set bits with content of parameter "SamplingTime" with bits position     */
03968   /* in register and register position depending on parameter "Channel".      */
03969   /* Parameter "Channel" is used with masks because containing                */
03970   /* other bits reserved for other purpose.                                   */
03971   register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
03972
03973   MODIFY_REG(*preg,
03974              ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
03975              SamplingTime   << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
03976 }
03977
03978 /**
03979   * @brief  Get sampling time of the selected ADC channel
03980   *         Unit: ADC clock cycles.
03981   * @note   On this device, sampling time is on channel scope: independently
03982   *         of channel mapped on ADC group regular or injected.
03983   * @note   Conversion time is the addition of sampling time and processing time.
03984   *         On this STM32 serie, ADC processing time is:
03985   *         - 12.5 ADC clock cycles at ADC resolution 12 bits
03986   *         - 10.5 ADC clock cycles at ADC resolution 10 bits
03987   *         - 8.5 ADC clock cycles at ADC resolution 8 bits
03988   *         - 6.5 ADC clock cycles at ADC resolution 6 bits
03989   * @rmtoll SMPR1    SMP0           LL_ADC_GetChannelSamplingTime\n
03990   *         SMPR1    SMP1           LL_ADC_GetChannelSamplingTime\n
03991   *         SMPR1    SMP2           LL_ADC_GetChannelSamplingTime\n
03992   *         SMPR1    SMP3           LL_ADC_GetChannelSamplingTime\n
03993   *         SMPR1    SMP4           LL_ADC_GetChannelSamplingTime\n
03994   *         SMPR1    SMP5           LL_ADC_GetChannelSamplingTime\n
03995   *         SMPR1    SMP6           LL_ADC_GetChannelSamplingTime\n
03996   *         SMPR1    SMP7           LL_ADC_GetChannelSamplingTime\n
03997   *         SMPR1    SMP8           LL_ADC_GetChannelSamplingTime\n
03998   *         SMPR1    SMP9           LL_ADC_GetChannelSamplingTime\n
03999   *         SMPR2    SMP10          LL_ADC_GetChannelSamplingTime\n
04000   *         SMPR2    SMP11          LL_ADC_GetChannelSamplingTime\n
04001   *         SMPR2    SMP12          LL_ADC_GetChannelSamplingTime\n
04002   *         SMPR2    SMP13          LL_ADC_GetChannelSamplingTime\n
04003   *         SMPR2    SMP14          LL_ADC_GetChannelSamplingTime\n
04004   *         SMPR2    SMP15          LL_ADC_GetChannelSamplingTime\n
04005   *         SMPR2    SMP16          LL_ADC_GetChannelSamplingTime\n
04006   *         SMPR2    SMP17          LL_ADC_GetChannelSamplingTime\n
04007   *         SMPR2    SMP18          LL_ADC_GetChannelSamplingTime
04008   * @param  ADCx ADC instance
04009   * @param  Channel This parameter can be one of the following values:
04010   *         @arg @ref LL_ADC_CHANNEL_0
04011   *         @arg @ref LL_ADC_CHANNEL_1            (7)
04012   *         @arg @ref LL_ADC_CHANNEL_2            (7)
04013   *         @arg @ref LL_ADC_CHANNEL_3            (7)
04014   *         @arg @ref LL_ADC_CHANNEL_4            (7)
04015   *         @arg @ref LL_ADC_CHANNEL_5            (7)
04016   *         @arg @ref LL_ADC_CHANNEL_6
04017   *         @arg @ref LL_ADC_CHANNEL_7
04018   *         @arg @ref LL_ADC_CHANNEL_8
04019   *         @arg @ref LL_ADC_CHANNEL_9
04020   *         @arg @ref LL_ADC_CHANNEL_10
04021   *         @arg @ref LL_ADC_CHANNEL_11
04022   *         @arg @ref LL_ADC_CHANNEL_12
04023   *         @arg @ref LL_ADC_CHANNEL_13
04024   *         @arg @ref LL_ADC_CHANNEL_14
04025   *         @arg @ref LL_ADC_CHANNEL_15
04026   *         @arg @ref LL_ADC_CHANNEL_16
04027   *         @arg @ref LL_ADC_CHANNEL_17
04028   *         @arg @ref LL_ADC_CHANNEL_18
04029   *         @arg @ref LL_ADC_CHANNEL_VREFINT
04030   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
04031   *         @arg @ref LL_ADC_CHANNEL_VBAT
04032   *
04033   *         (7) On STM32WB, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
04034   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
04035   * @retval Returned value can be one of the following values:
04036   *         @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5
04037   *         @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
04038   *         @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
04039   *         @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
04040   *         @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
04041   *         @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
04042   *         @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
04043   *         @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
04044   */
04045 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
04046 {
04047   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
04048
04049   return (uint32_t)(READ_BIT(*preg,
04050                              ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS))
04051                     >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)
04052                    );
04053 }
04054
04055 /**
04056   * @brief  Set mode single-ended or differential input of the selected
04057   *         ADC channel.
04058   * @note   Channel ending is on channel scope: independently of channel mapped
04059   *         on ADC group regular or injected.
04060   *         In differential mode: Differential measurement is carried out
04061   *         between the selected channel 'i' (positive input) and
04062   *         channel 'i+1' (negative input). Only channel 'i' has to be
04063   *         configured, channel 'i+1' is configured automatically.
04064   * @note   Refer to Reference Manual to ensure the selected channel is
04065   *         available in differential mode.
04066   *         For example, internal channels (VrefInt, TempSensor, ...) are
04067   *         not available in differential mode.
04068   * @note   When configuring a channel 'i' in differential mode,
04069   *         the channel 'i+1' is not usable separately.
04070   * @note   On STM32WB, channels 16, 17, 18 of ADC1
04071   *         are internally fixed to single-ended inputs configuration.
04072   * @note   For ADC channels configured in differential mode, both inputs
04073   *         should be biased at (Vref+)/2 +/-200mV.
04074   *         (Vref+ is the analog voltage reference)
04075   * @note   On this STM32 serie, setting of this feature is conditioned to
04076   *         ADC state:
04077   *         ADC must be ADC disabled.
04078   * @note   One or several values can be selected.
04079   *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
04080   * @rmtoll DIFSEL   DIFSEL         LL_ADC_SetChannelSingleDiff
04081   * @param  ADCx ADC instance
04082   * @param  Channel This parameter can be one of the following values:
04083   *         @arg @ref LL_ADC_CHANNEL_1
04084   *         @arg @ref LL_ADC_CHANNEL_2
04085   *         @arg @ref LL_ADC_CHANNEL_3
04086   *         @arg @ref LL_ADC_CHANNEL_4
04087   *         @arg @ref LL_ADC_CHANNEL_5
04088   *         @arg @ref LL_ADC_CHANNEL_6
04089   *         @arg @ref LL_ADC_CHANNEL_7
04090   *         @arg @ref LL_ADC_CHANNEL_8
04091   *         @arg @ref LL_ADC_CHANNEL_9
04092   *         @arg @ref LL_ADC_CHANNEL_10
04093   *         @arg @ref LL_ADC_CHANNEL_11
04094   *         @arg @ref LL_ADC_CHANNEL_12
04095   *         @arg @ref LL_ADC_CHANNEL_13
04096   *         @arg @ref LL_ADC_CHANNEL_14
04097   *         @arg @ref LL_ADC_CHANNEL_15
04098   * @param  SingleDiff This parameter can be a combination of the following values:
04099   *         @arg @ref LL_ADC_SINGLE_ENDED
04100   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
04101   * @retval None
04102   */
04103 __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
04104 {
04105   /* Bits of channels in single or differential mode are set only for         */
04106   /* differential mode (for single mode, mask of bits allowed to be set is    */
04107   /* shifted out of range of bits of channels in single or differential mode. */
04108   MODIFY_REG(ADCx->DIFSEL,
04109              Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
04110              (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
04111 }
04112
04113 /**
04114   * @brief  Get mode single-ended or differential input of the selected
04115   *         ADC channel.
04116   * @note   When configuring a channel 'i' in differential mode,
04117   *         the channel 'i+1' is not usable separately.
04118   *         Therefore, to ensure a channel is configured in single-ended mode,
04119   *         the configuration of channel itself and the channel 'i-1' must be
04120   *         read back (to ensure that the selected channel channel has not been
04121   *         configured in differential mode by the previous channel).
04122   * @note   Refer to Reference Manual to ensure the selected channel is
04123   *         available in differential mode.
04124   *         For example, internal channels (VrefInt, TempSensor, ...) are
04125   *         not available in differential mode.
04126   * @note   When configuring a channel 'i' in differential mode,
04127   *         the channel 'i+1' is not usable separately.
04128   * @note   On STM32WB, channels 16, 17, 18 of ADC1
04129   *         are internally fixed to single-ended inputs configuration.
04130   * @note   One or several values can be selected. In this case, the value
04131   *         returned is null if all channels are in single ended-mode.
04132   *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
04133   * @rmtoll DIFSEL   DIFSEL         LL_ADC_GetChannelSingleDiff
04134   * @param  ADCx ADC instance
04135   * @param  Channel This parameter can be a combination of the following values:
04136   *         @arg @ref LL_ADC_CHANNEL_1
04137   *         @arg @ref LL_ADC_CHANNEL_2
04138   *         @arg @ref LL_ADC_CHANNEL_3
04139   *         @arg @ref LL_ADC_CHANNEL_4
04140   *         @arg @ref LL_ADC_CHANNEL_5
04141   *         @arg @ref LL_ADC_CHANNEL_6
04142   *         @arg @ref LL_ADC_CHANNEL_7
04143   *         @arg @ref LL_ADC_CHANNEL_8
04144   *         @arg @ref LL_ADC_CHANNEL_9
04145   *         @arg @ref LL_ADC_CHANNEL_10
04146   *         @arg @ref LL_ADC_CHANNEL_11
04147   *         @arg @ref LL_ADC_CHANNEL_12
04148   *         @arg @ref LL_ADC_CHANNEL_13
04149   *         @arg @ref LL_ADC_CHANNEL_14
04150   *         @arg @ref LL_ADC_CHANNEL_15
04151   * @retval 0: channel in single-ended mode, else: channel in differential mode
04152   */
04153 __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel)
04154 {
04155   return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
04156 }
04157
04158 /**
04159   * @}
04160   */
04161
04162 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
04163   * @{
04164   */
04165
04166 /**
04167   * @brief  Set ADC analog watchdog monitored channels:
04168   *         a single channel, multiple channels or all channels,
04169   *         on ADC groups regular and-or injected.
04170   * @note   Once monitored channels are selected, analog watchdog
04171   *         is enabled.
04172   * @note   In case of need to define a single channel to monitor
04173   *         with analog watchdog from sequencer channel definition,
04174   *         use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
04175   * @note   On this STM32 serie, there are 2 kinds of analog watchdog
04176   *         instance:
04177   *         - AWD standard (instance AWD1):
04178   *           - channels monitored: can monitor 1 channel or all channels.
04179   *           - groups monitored: ADC groups regular and-or injected.
04180   *           - resolution: resolution is not limited (corresponds to
04181   *             ADC resolution configured).
04182   *         - AWD flexible (instances AWD2, AWD3):
04183   *           - channels monitored: flexible on channels monitored, selection is
04184   *             channel wise, from from 1 to all channels.
04185   *             Specificity of this analog watchdog: Multiple channels can
04186   *             be selected. For example:
04187   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
04188   *           - groups monitored: not selection possible (monitoring on both
04189   *             groups regular and injected).
04190   *             Channels selected are monitored on groups regular and injected:
04191   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
04192   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
04193   *           - resolution: resolution is limited to 8 bits: if ADC resolution is
04194   *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
04195   *             the 2 LSB are ignored.
04196   * @note   On this STM32 serie, setting of this feature is conditioned to
04197   *         ADC state:
04198   *         ADC must be disabled or enabled without conversion on going
04199   *         on either groups regular or injected.
04200   * @rmtoll CFGR     AWD1CH         LL_ADC_SetAnalogWDMonitChannels\n
04201   *         CFGR     AWD1SGL        LL_ADC_SetAnalogWDMonitChannels\n
04202   *         CFGR     AWD1EN         LL_ADC_SetAnalogWDMonitChannels\n
04203   *         CFGR     JAWD1EN        LL_ADC_SetAnalogWDMonitChannels\n
04204   *         AWD2CR   AWD2CH         LL_ADC_SetAnalogWDMonitChannels\n
04205   *         AWD3CR   AWD3CH         LL_ADC_SetAnalogWDMonitChannels
04206   * @param  ADCx ADC instance
04207   * @param  AWDy This parameter can be one of the following values:
04208   *         @arg @ref LL_ADC_AWD1
04209   *         @arg @ref LL_ADC_AWD2
04210   *         @arg @ref LL_ADC_AWD3
04211   * @param  AWDChannelGroup This parameter can be one of the following values:
04212   *         @arg @ref LL_ADC_AWD_DISABLE
04213   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)
04214   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)
04215   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
04216   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)
04217   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)
04218   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
04219   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)
04220   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)
04221   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
04222   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)
04223   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)
04224   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
04225   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)
04226   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)
04227   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
04228   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)
04229   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)
04230   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
04231   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)
04232   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)
04233   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
04234   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)
04235   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)
04236   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
04237   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)
04238   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)
04239   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
04240   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)
04241   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)
04242   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
04243   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)
04244   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)
04245   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
04246   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)
04247   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)
04248   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
04249   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)
04250   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)
04251   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
04252   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)
04253   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)
04254   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
04255   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)
04256   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)
04257   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
04258   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)
04259   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)
04260   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
04261   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)
04262   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)
04263   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
04264   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)
04265   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)
04266   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
04267   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)
04268   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)
04269   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
04270   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)
04271   *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)
04272   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
04273   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (0)
04274   *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (0)
04275   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ
04276   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG       (0)
04277   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ       (0)
04278   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ
04279   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (0)
04280   *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (0)
04281   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ
04282   *
04283   *         (0) On STM32WB, parameter available only on analog watchdog number: AWD1.
04284   * @retval None
04285   */
04286 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
04287 {
04288   /* Set bits with content of parameter "AWDChannelGroup" with bits position  */
04289   /* in register and register position depending on parameter "AWDy".         */
04290   /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because      */
04291   /* containing other bits reserved for other purpose.                        */
04292   register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
04293                                                       + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
04294
04295   MODIFY_REG(*preg,
04296              (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
04297              AWDChannelGroup & AWDy);
04298 }
04299
04300 /**
04301   * @brief  Get ADC analog watchdog monitored channel.
04302   * @note   Usage of the returned channel number:
04303   *         - To reinject this channel into another function LL_ADC_xxx:
04304   *           the returned channel number is only partly formatted on definition
04305   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
04306   *           with parts of literals LL_ADC_CHANNEL_x or using
04307   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
04308   *           Then the selected literal LL_ADC_CHANNEL_x can be used
04309   *           as parameter for another function.
04310   *         - To get the channel number in decimal format:
04311   *           process the returned value with the helper macro
04312   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
04313   *           Applicable only when the analog watchdog is set to monitor
04314   *           one channel.
04315   * @note   On this STM32 serie, there are 2 kinds of analog watchdog
04316   *         instance:
04317   *         - AWD standard (instance AWD1):
04318   *           - channels monitored: can monitor 1 channel or all channels.
04319   *           - groups monitored: ADC groups regular and-or injected.
04320   *           - resolution: resolution is not limited (corresponds to
04321   *             ADC resolution configured).
04322   *         - AWD flexible (instances AWD2, AWD3):
04323   *           - channels monitored: flexible on channels monitored, selection is
04324   *             channel wise, from from 1 to all channels.
04325   *             Specificity of this analog watchdog: Multiple channels can
04326   *             be selected. For example:
04327   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
04328   *           - groups monitored: not selection possible (monitoring on both
04329   *             groups regular and injected).
04330   *             Channels selected are monitored on groups regular and injected:
04331   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
04332   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
04333   *           - resolution: resolution is limited to 8 bits: if ADC resolution is
04334   *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
04335   *             the 2 LSB are ignored.
04336   * @note   On this STM32 serie, setting of this feature is conditioned to
04337   *         ADC state:
04338   *         ADC must be disabled or enabled without conversion on going
04339   *         on either groups regular or injected.
04340   * @rmtoll CFGR     AWD1CH         LL_ADC_GetAnalogWDMonitChannels\n
04341   *         CFGR     AWD1SGL        LL_ADC_GetAnalogWDMonitChannels\n
04342   *         CFGR     AWD1EN         LL_ADC_GetAnalogWDMonitChannels\n
04343   *         CFGR     JAWD1EN        LL_ADC_GetAnalogWDMonitChannels\n
04344   *         AWD2CR   AWD2CH         LL_ADC_GetAnalogWDMonitChannels\n
04345   *         AWD3CR   AWD3CH         LL_ADC_GetAnalogWDMonitChannels
04346   * @param  ADCx ADC instance
04347   * @param  AWDy This parameter can be one of the following values:
04348   *         @arg @ref LL_ADC_AWD1
04349   *         @arg @ref LL_ADC_AWD2 (1)
04350   *         @arg @ref LL_ADC_AWD3 (1)
04351   *
04352   *         (1) On this AWD number, monitored channel can be retrieved
04353   *             if only 1 channel is programmed (or none or all channels).
04354   *             This function cannot retrieve monitored channel if
04355   *             multiple channels are programmed simultaneously
04356   *             by bitfield.
04357   * @retval Returned value can be one of the following values:
04358   *         @arg @ref LL_ADC_AWD_DISABLE
04359   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)
04360   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)
04361   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
04362   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)
04363   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)
04364   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
04365   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)
04366   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)
04367   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
04368   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)
04369   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)
04370   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
04371   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)
04372   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)
04373   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
04374   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)
04375   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)
04376   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
04377   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)
04378   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)
04379   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
04380   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)
04381   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)
04382   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
04383   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)
04384   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)
04385   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
04386   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)
04387   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)
04388   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
04389   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)
04390   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)
04391   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
04392   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)
04393   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)
04394   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
04395   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)
04396   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)
04397   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
04398   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)
04399   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)
04400   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
04401   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)
04402   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)
04403   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
04404   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)
04405   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)
04406   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
04407   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)
04408   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)
04409   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
04410   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)
04411   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)
04412   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
04413   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)
04414   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)
04415   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
04416   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)
04417   *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)
04418   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
04419   *
04420   *         (0) On STM32WB, parameter available only on analog watchdog number: AWD1.
04421   */
04422 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
04423 {
04424   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
04425                                                             + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
04426
04427   register uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
04428
04429   /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled       */
04430   /* (parameter value LL_ADC_AWD_DISABLE).                                    */
04431   /* Else, the selected AWD is enabled and is monitoring a group of channels  */
04432   /* or a single channel.                                                     */
04433   if (AnalogWDMonitChannels != 0UL)
04434   {
04435     if (AWDy == LL_ADC_AWD1)
04436     {
04437       if ((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0UL)
04438       {
04439         /* AWD monitoring a group of channels */
04440         AnalogWDMonitChannels = ((AnalogWDMonitChannels
04441                                   | (ADC_AWD_CR23_CHANNEL_MASK)
04442                                  )
04443                                  & (~(ADC_CFGR_AWD1CH))
04444                                 );
04445       }
04446       else
04447       {
04448         /* AWD monitoring a single channel */
04449         AnalogWDMonitChannels = (AnalogWDMonitChannels
04450                                  | (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR_AWD1CH_Pos))
04451                                 );
04452       }
04453     }
04454     else
04455     {
04456       if ((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
04457       {
04458         /* AWD monitoring a group of channels */
04459         AnalogWDMonitChannels = (ADC_AWD_CR23_CHANNEL_MASK
04460                                  | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN))
04461                                 );
04462       }
04463       else
04464       {
04465         /* AWD monitoring a single channel */
04466         /* AWD monitoring a group of channels */
04467         AnalogWDMonitChannels = (AnalogWDMonitChannels
04468                                  | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
04469                                  | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR_AWD1CH_Pos)
04470                                 );
04471       }
04472     }
04473   }
04474
04475   return AnalogWDMonitChannels;
04476 }
04477
04478 /**
04479   * @brief  Set ADC analog watchdog thresholds value of both thresholds
04480   *         high and low.
04481   * @note   If value of only one threshold high or low must be set,
04482   *         use function @ref LL_ADC_SetAnalogWDThresholds().
04483   * @note   In case of ADC resolution different of 12 bits,
04484   *         analog watchdog thresholds data require a specific shift.
04485   *         Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
04486   * @note   On this STM32 serie, there are 2 kinds of analog watchdog
04487   *         instance:
04488   *         - AWD standard (instance AWD1):
04489   *           - channels monitored: can monitor 1 channel or all channels.
04490   *           - groups monitored: ADC groups regular and-or injected.
04491   *           - resolution: resolution is not limited (corresponds to
04492   *             ADC resolution configured).
04493   *         - AWD flexible (instances AWD2, AWD3):
04494   *           - channels monitored: flexible on channels monitored, selection is
04495   *             channel wise, from from 1 to all channels.
04496   *             Specificity of this analog watchdog: Multiple channels can
04497   *             be selected. For example:
04498   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
04499   *           - groups monitored: not selection possible (monitoring on both
04500   *             groups regular and injected).
04501   *             Channels selected are monitored on groups regular and injected:
04502   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
04503   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
04504   *           - resolution: resolution is limited to 8 bits: if ADC resolution is
04505   *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
04506   *             the 2 LSB are ignored.
04507   * @note   If ADC oversampling is enabled, ADC analog watchdog thresholds are
04508   *         impacted: the comparison of analog watchdog thresholds is done on
04509   *         oversampling final computation (after ratio and shift application):
04510   *         ADC data register bitfield [15:4] (12 most significant bits).
04511   * @note   On this STM32 serie, setting of this feature is conditioned to
04512   *         ADC state:
04513   *         ADC must be disabled or enabled without conversion on going
04514   *         on either groups regular or injected.
04515   * @rmtoll TR1      HT1            LL_ADC_ConfigAnalogWDThresholds\n
04516   *         TR2      HT2            LL_ADC_ConfigAnalogWDThresholds\n
04517   *         TR3      HT3            LL_ADC_ConfigAnalogWDThresholds\n
04518   *         TR1      LT1            LL_ADC_ConfigAnalogWDThresholds\n
04519   *         TR2      LT2            LL_ADC_ConfigAnalogWDThresholds\n
04520   *         TR3      LT3            LL_ADC_ConfigAnalogWDThresholds
04521   * @param  ADCx ADC instance
04522   * @param  AWDy This parameter can be one of the following values:
04523   *         @arg @ref LL_ADC_AWD1
04524   *         @arg @ref LL_ADC_AWD2
04525   *         @arg @ref LL_ADC_AWD3
04526   * @param  AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
04527   * @param  AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
04528   * @retval None
04529   */
04530 __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue,
04531                                                      uint32_t AWDThresholdLowValue)
04532 {
04533   /* Set bits with content of parameter "AWDThresholdxxxValue" with bits      */
04534   /* position in register and register position depending on parameter        */
04535   /* "AWDy".                                                                  */
04536   /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
04537   /* containing other bits reserved for other purpose.                        */
04538   register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
04539
04540   MODIFY_REG(*preg,
04541              ADC_TR1_HT1 | ADC_TR1_LT1,
04542              (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
04543 }
04544
04545 /**
04546   * @brief  Set ADC analog watchdog threshold value of threshold
04547   *         high or low.
04548   * @note   If values of both thresholds high or low must be set,
04549   *         use function @ref LL_ADC_ConfigAnalogWDThresholds().
04550   * @note   In case of ADC resolution different of 12 bits,
04551   *         analog watchdog thresholds data require a specific shift.
04552   *         Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
04553   * @note   On this STM32 serie, there are 2 kinds of analog watchdog
04554   *         instance:
04555   *         - AWD standard (instance AWD1):
04556   *           - channels monitored: can monitor 1 channel or all channels.
04557   *           - groups monitored: ADC groups regular and-or injected.
04558   *           - resolution: resolution is not limited (corresponds to
04559   *             ADC resolution configured).
04560   *         - AWD flexible (instances AWD2, AWD3):
04561   *           - channels monitored: flexible on channels monitored, selection is
04562   *             channel wise, from from 1 to all channels.
04563   *             Specificity of this analog watchdog: Multiple channels can
04564   *             be selected. For example:
04565   *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
04566   *           - groups monitored: not selection possible (monitoring on both
04567   *             groups regular and injected).
04568   *             Channels selected are monitored on groups regular and injected:
04569   *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
04570   *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
04571   *           - resolution: resolution is limited to 8 bits: if ADC resolution is
04572   *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
04573   *             the 2 LSB are ignored.
04574   * @note   If ADC oversampling is enabled, ADC analog watchdog thresholds are
04575   *         impacted: the comparison of analog watchdog thresholds is done on
04576   *         oversampling final computation (after ratio and shift application):
04577   *         ADC data register bitfield [15:4] (12 most significant bits).
04578   * @note   On this STM32 serie, setting of this feature is conditioned to
04579   *         ADC state:
04580   *         ADC must be disabled or enabled without conversion on going
04581   *         on either ADC groups regular or injected.
04582   * @rmtoll TR1      HT1            LL_ADC_SetAnalogWDThresholds\n
04583   *         TR2      HT2            LL_ADC_SetAnalogWDThresholds\n
04584   *         TR3      HT3            LL_ADC_SetAnalogWDThresholds\n
04585   *         TR1      LT1            LL_ADC_SetAnalogWDThresholds\n
04586   *         TR2      LT2            LL_ADC_SetAnalogWDThresholds\n
04587   *         TR3      LT3            LL_ADC_SetAnalogWDThresholds
04588   * @param  ADCx ADC instance
04589   * @param  AWDy This parameter can be one of the following values:
04590   *         @arg @ref LL_ADC_AWD1
04591   *         @arg @ref LL_ADC_AWD2
04592   *         @arg @ref LL_ADC_AWD3
04593   * @param  AWDThresholdsHighLow This parameter can be one of the following values:
04594   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
04595   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
04596   * @param  AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
04597   * @retval None
04598   */
04599 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,
04600                                                   uint32_t AWDThresholdValue)
04601 {
04602   /* Set bits with content of parameter "AWDThresholdValue" with bits         */
04603   /* position in register and register position depending on parameters       */
04604   /* "AWDThresholdsHighLow" and "AWDy".                                       */
04605   /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because    */
04606   /* containing other bits reserved for other purpose.                        */
04607   register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
04608
04609   MODIFY_REG(*preg,
04610              AWDThresholdsHighLow,
04611              AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
04612 }
04613
04614 /**
04615   * @brief  Get ADC analog watchdog threshold value of threshold high,
04616   *         threshold low or raw data with ADC thresholds high and low
04617   *         concatenated.
04618   * @note   If raw data with ADC thresholds high and low is retrieved,
04619   *         the data of each threshold high or low can be isolated
04620   *         using helper macro:
04621   *         @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
04622   * @note   In case of ADC resolution different of 12 bits,
04623   *         analog watchdog thresholds data require a specific shift.
04624   *         Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
04625   * @rmtoll TR1      HT1            LL_ADC_GetAnalogWDThresholds\n
04626   *         TR2      HT2            LL_ADC_GetAnalogWDThresholds\n
04627   *         TR3      HT3            LL_ADC_GetAnalogWDThresholds\n
04628   *         TR1      LT1            LL_ADC_GetAnalogWDThresholds\n
04629   *         TR2      LT2            LL_ADC_GetAnalogWDThresholds\n
04630   *         TR3      LT3            LL_ADC_GetAnalogWDThresholds
04631   * @param  ADCx ADC instance
04632   * @param  AWDy This parameter can be one of the following values:
04633   *         @arg @ref LL_ADC_AWD1
04634   *         @arg @ref LL_ADC_AWD2
04635   *         @arg @ref LL_ADC_AWD3
04636   * @param  AWDThresholdsHighLow This parameter can be one of the following values:
04637   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
04638   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
04639   *         @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
04640   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
04641   */
04642 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
04643 {
04644   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
04645
04646   return (uint32_t)(READ_BIT(*preg,
04647                              (AWDThresholdsHighLow | ADC_TR1_LT1))
04648                     >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) & ~(AWDThresholdsHighLow & ADC_TR1_LT1))
04649                    );
04650 }
04651
04652 /**
04653   * @}
04654   */
04655
04656 /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
04657   * @{
04658   */
04659
04660 /**
04661   * @brief  Set ADC oversampling scope: ADC groups regular and-or injected
04662   *         (availability of ADC group injected depends on STM32 families).
04663   * @note   If both groups regular and injected are selected,
04664   *         specify behavior of ADC group injected interrupting
04665   *         group regular: when ADC group injected is triggered,
04666   *         the oversampling on ADC group regular is either
04667   *         temporary stopped and continued, or resumed from start
04668   *         (oversampler buffer reset).
04669   * @note   On this STM32 serie, setting of this feature is conditioned to
04670   *         ADC state:
04671   *         ADC must be disabled or enabled without conversion on going
04672   *         on either groups regular or injected.
04673   * @rmtoll CFGR2    ROVSE          LL_ADC_SetOverSamplingScope\n
04674   *         CFGR2    JOVSE          LL_ADC_SetOverSamplingScope\n
04675   *         CFGR2    ROVSM          LL_ADC_SetOverSamplingScope
04676   * @param  ADCx ADC instance
04677   * @param  OvsScope This parameter can be one of the following values:
04678   *         @arg @ref LL_ADC_OVS_DISABLE
04679   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
04680   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
04681   *         @arg @ref LL_ADC_OVS_GRP_INJECTED
04682   *         @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
04683   * @retval None
04684   */
04685 __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
04686 {
04687   MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);
04688 }
04689
04690 /**
04691   * @brief  Get ADC oversampling scope: ADC groups regular and-or injected
04692   *         (availability of ADC group injected depends on STM32 families).
04693   * @note   If both groups regular and injected are selected,
04694   *         specify behavior of ADC group injected interrupting
04695   *         group regular: when ADC group injected is triggered,
04696   *         the oversampling on ADC group regular is either
04697   *         temporary stopped and continued, or resumed from start
04698   *         (oversampler buffer reset).
04699   * @rmtoll CFGR2    ROVSE          LL_ADC_GetOverSamplingScope\n
04700   *         CFGR2    JOVSE          LL_ADC_GetOverSamplingScope\n
04701   *         CFGR2    ROVSM          LL_ADC_GetOverSamplingScope
04702   * @param  ADCx ADC instance
04703   * @retval Returned value can be one of the following values:
04704   *         @arg @ref LL_ADC_OVS_DISABLE
04705   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
04706   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
04707   *         @arg @ref LL_ADC_OVS_GRP_INJECTED
04708   *         @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
04709   */
04710 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)
04711 {
04712   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
04713 }
04714
04715 /**
04716   * @brief  Set ADC oversampling discontinuous mode (triggered mode)
04717   *         on the selected ADC group.
04718   * @note   Number of oversampled conversions are done either in:
04719   *         - continuous mode (all conversions of oversampling ratio
04720   *           are done from 1 trigger)
04721   *         - discontinuous mode (each conversion of oversampling ratio
04722   *           needs a trigger)
04723   * @note   On this STM32 serie, setting of this feature is conditioned to
04724   *         ADC state:
04725   *         ADC must be disabled or enabled without conversion on going
04726   *         on group regular.
04727   * @note   On this STM32 serie, oversampling discontinuous mode
04728   *         (triggered mode) can be used only when oversampling is
04729   *         set on group regular only and in resumed mode.
04730   * @rmtoll CFGR2    TROVS          LL_ADC_SetOverSamplingDiscont
04731   * @param  ADCx ADC instance
04732   * @param  OverSamplingDiscont This parameter can be one of the following values:
04733   *         @arg @ref LL_ADC_OVS_REG_CONT
04734   *         @arg @ref LL_ADC_OVS_REG_DISCONT
04735   * @retval None
04736   */
04737 __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
04738 {
04739   MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
04740 }
04741
04742 /**
04743   * @brief  Get ADC oversampling discontinuous mode (triggered mode)
04744   *         on the selected ADC group.
04745   * @note   Number of oversampled conversions are done either in:
04746   *         - continuous mode (all conversions of oversampling ratio
04747   *           are done from 1 trigger)
04748   *         - discontinuous mode (each conversion of oversampling ratio
04749   *           needs a trigger)
04750   * @rmtoll CFGR2    TROVS          LL_ADC_GetOverSamplingDiscont
04751   * @param  ADCx ADC instance
04752   * @retval Returned value can be one of the following values:
04753   *         @arg @ref LL_ADC_OVS_REG_CONT
04754   *         @arg @ref LL_ADC_OVS_REG_DISCONT
04755   */
04756 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)
04757 {
04758   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
04759 }
04760
04761 /**
04762   * @brief  Set ADC oversampling
04763   *         (impacting both ADC groups regular and injected)
04764   * @note   This function set the 2 items of oversampling configuration:
04765   *         - ratio
04766   *         - shift
04767   * @note   On this STM32 serie, setting of this feature is conditioned to
04768   *         ADC state:
04769   *         ADC must be disabled or enabled without conversion on going
04770   *         on either groups regular or injected.
04771   * @rmtoll CFGR2    OVSS           LL_ADC_ConfigOverSamplingRatioShift\n
04772   *         CFGR2    OVSR           LL_ADC_ConfigOverSamplingRatioShift
04773   * @param  ADCx ADC instance
04774   * @param  Ratio This parameter can be one of the following values:
04775   *         @arg @ref LL_ADC_OVS_RATIO_2
04776   *         @arg @ref LL_ADC_OVS_RATIO_4
04777   *         @arg @ref LL_ADC_OVS_RATIO_8
04778   *         @arg @ref LL_ADC_OVS_RATIO_16
04779   *         @arg @ref LL_ADC_OVS_RATIO_32
04780   *         @arg @ref LL_ADC_OVS_RATIO_64
04781   *         @arg @ref LL_ADC_OVS_RATIO_128
04782   *         @arg @ref LL_ADC_OVS_RATIO_256
04783   * @param  Shift This parameter can be one of the following values:
04784   *         @arg @ref LL_ADC_OVS_SHIFT_NONE
04785   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
04786   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
04787   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
04788   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
04789   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
04790   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
04791   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
04792   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
04793   * @retval None
04794   */
04795 __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
04796 {
04797   MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio));
04798 }
04799
04800 /**
04801   * @brief  Get ADC oversampling ratio
04802   *        (impacting both ADC groups regular and injected)
04803   * @rmtoll CFGR2    OVSR           LL_ADC_GetOverSamplingRatio
04804   * @param  ADCx ADC instance
04805   * @retval Ratio This parameter can be one of the following values:
04806   *         @arg @ref LL_ADC_OVS_RATIO_2
04807   *         @arg @ref LL_ADC_OVS_RATIO_4
04808   *         @arg @ref LL_ADC_OVS_RATIO_8
04809   *         @arg @ref LL_ADC_OVS_RATIO_16
04810   *         @arg @ref LL_ADC_OVS_RATIO_32
04811   *         @arg @ref LL_ADC_OVS_RATIO_64
04812   *         @arg @ref LL_ADC_OVS_RATIO_128
04813   *         @arg @ref LL_ADC_OVS_RATIO_256
04814   */
04815 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)
04816 {
04817   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
04818 }
04819
04820 /**
04821   * @brief  Get ADC oversampling shift
04822   *        (impacting both ADC groups regular and injected)
04823   * @rmtoll CFGR2    OVSS           LL_ADC_GetOverSamplingShift
04824   * @param  ADCx ADC instance
04825   * @retval Shift This parameter can be one of the following values:
04826   *         @arg @ref LL_ADC_OVS_SHIFT_NONE
04827   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
04828   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
04829   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
04830   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
04831   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
04832   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
04833   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
04834   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
04835   */
04836 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)
04837 {
04838   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
04839 }
04840
04841 /**
04842   * @}
04843   */
04844
04845 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
04846   * @{
04847   */
04848
04849 /**
04850   * @brief  Put ADC instance in deep power down state.
04851   * @note   In case of ADC calibration necessary: When ADC is in deep-power-down
04852   *         state, the internal analog calibration is lost. After exiting from
04853   *         deep power down, calibration must be relaunched or calibration factor
04854   *         (preliminarily saved) must be set back into calibration register.
04855   * @note   On this STM32 serie, setting of this feature is conditioned to
04856   *         ADC state:
04857   *         ADC must be ADC disabled.
04858   * @rmtoll CR       DEEPPWD        LL_ADC_EnableDeepPowerDown
04859   * @param  ADCx ADC instance
04860   * @retval None
04861   */
04862 __STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)
04863 {
04864   /* Note: Write register with some additional bits forced to state reset     */
04865   /*       instead of modifying only the selected bit for this function,      */
04866   /*       to not interfere with bits with HW property "rs".                  */
04867   MODIFY_REG(ADCx->CR,
04868              ADC_CR_BITS_PROPERTY_RS,
04869              ADC_CR_DEEPPWD);
04870 }
04871
04872 /**
04873   * @brief  Disable ADC deep power down mode.
04874   * @note   In case of ADC calibration necessary: When ADC is in deep-power-down
04875   *         state, the internal analog calibration is lost. After exiting from
04876   *         deep power down, calibration must be relaunched or calibration factor
04877   *         (preliminarily saved) must be set back into calibration register.
04878   * @note   On this STM32 serie, setting of this feature is conditioned to
04879   *         ADC state:
04880   *         ADC must be ADC disabled.
04881   * @rmtoll CR       DEEPPWD        LL_ADC_DisableDeepPowerDown
04882   * @param  ADCx ADC instance
04883   * @retval None
04884   */
04885 __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
04886 {
04887   /* Note: Write register with some additional bits forced to state reset     */
04888   /*       instead of modifying only the selected bit for this function,      */
04889   /*       to not interfere with bits with HW property "rs".                  */
04890   CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
04891 }
04892
04893 /**
04894   * @brief  Get the selected ADC instance deep power down state.
04895   * @rmtoll CR       DEEPPWD        LL_ADC_IsDeepPowerDownEnabled
04896   * @param  ADCx ADC instance
04897   * @retval 0: deep power down is disabled, 1: deep power down is enabled.
04898   */
04899 __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx)
04900 {
04901   return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
04902 }
04903
04904 /**
04905   * @brief  Enable ADC instance internal voltage regulator.
04906   * @note   On this STM32 serie, after ADC internal voltage regulator enable,
04907   *         a delay for ADC internal voltage regulator stabilization
04908   *         is required before performing a ADC calibration or ADC enable.
04909   *         Refer to device datasheet, parameter tADCVREG_STUP.
04910   *         Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
04911   * @note   On this STM32 serie, setting of this feature is conditioned to
04912   *         ADC state:
04913   *         ADC must be ADC disabled.
04914   * @rmtoll CR       ADVREGEN       LL_ADC_EnableInternalRegulator
04915   * @param  ADCx ADC instance
04916   * @retval None
04917   */
04918 __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
04919 {
04920   /* Note: Write register with some additional bits forced to state reset     */
04921   /*       instead of modifying only the selected bit for this function,      */
04922   /*       to not interfere with bits with HW property "rs".                  */
04923   MODIFY_REG(ADCx->CR,
04924              ADC_CR_BITS_PROPERTY_RS,
04925              ADC_CR_ADVREGEN);
04926 }
04927
04928 /**
04929   * @brief  Disable ADC internal voltage regulator.
04930   * @note   On this STM32 serie, setting of this feature is conditioned to
04931   *         ADC state:
04932   *         ADC must be ADC disabled.
04933   * @rmtoll CR       ADVREGEN       LL_ADC_DisableInternalRegulator
04934   * @param  ADCx ADC instance
04935   * @retval None
04936   */
04937 __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
04938 {
04939   CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
04940 }
04941
04942 /**
04943   * @brief  Get the selected ADC instance internal voltage regulator state.
04944   * @rmtoll CR       ADVREGEN       LL_ADC_IsInternalRegulatorEnabled
04945   * @param  ADCx ADC instance
04946   * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
04947   */
04948 __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
04949 {
04950   return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
04951 }
04952
04953 /**
04954   * @brief  Enable the selected ADC instance.
04955   * @note   On this STM32 serie, after ADC enable, a delay for
04956   *         ADC internal analog stabilization is required before performing a
04957   *         ADC conversion start.
04958   *         Refer to device datasheet, parameter tSTAB.
04959   * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
04960   *         is enabled and when conversion clock is active.
04961   *         (not only core clock: this ADC has a dual clock domain)
04962   * @note   On this STM32 serie, setting of this feature is conditioned to
04963   *         ADC state:
04964   *         ADC must be ADC disabled and ADC internal voltage regulator enabled.
04965   * @rmtoll CR       ADEN           LL_ADC_Enable
04966   * @param  ADCx ADC instance
04967   * @retval None
04968   */
04969 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
04970 {
04971   /* Note: Write register with some additional bits forced to state reset     */
04972   /*       instead of modifying only the selected bit for this function,      */
04973   /*       to not interfere with bits with HW property "rs".                  */
04974   MODIFY_REG(ADCx->CR,
04975              ADC_CR_BITS_PROPERTY_RS,
04976              ADC_CR_ADEN);
04977 }
04978
04979 /**
04980   * @brief  Disable the selected ADC instance.
04981   * @note   On this STM32 serie, setting of this feature is conditioned to
04982   *         ADC state:
04983   *         ADC must be not disabled. Must be enabled without conversion on going
04984   *         on either groups regular or injected.
04985   * @rmtoll CR       ADDIS          LL_ADC_Disable
04986   * @param  ADCx ADC instance
04987   * @retval None
04988   */
04989 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
04990 {
04991   /* Note: Write register with some additional bits forced to state reset     */
04992   /*       instead of modifying only the selected bit for this function,      */
04993   /*       to not interfere with bits with HW property "rs".                  */
04994   MODIFY_REG(ADCx->CR,
04995              ADC_CR_BITS_PROPERTY_RS,
04996              ADC_CR_ADDIS);
04997 }
04998
04999 /**
05000   * @brief  Get the selected ADC instance enable state.
05001   * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
05002   *         is enabled and when conversion clock is active.
05003   *         (not only core clock: this ADC has a dual clock domain)
05004   * @rmtoll CR       ADEN           LL_ADC_IsEnabled
05005   * @param  ADCx ADC instance
05006   * @retval 0: ADC is disabled, 1: ADC is enabled.
05007   */
05008 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
05009 {
05010   return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
05011 }
05012
05013 /**
05014   * @brief  Get the selected ADC instance disable state.
05015   * @rmtoll CR       ADDIS          LL_ADC_IsDisableOngoing
05016   * @param  ADCx ADC instance
05017   * @retval 0: no ADC disable command on going.
05018   */
05019 __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
05020 {
05021   return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
05022 }
05023
05024 /**
05025   * @brief  Start ADC calibration in the mode single-ended
05026   *         or differential (for devices with differential mode available).
05027   * @note   On this STM32 serie, a minimum number of ADC clock cycles
05028   *         are required between ADC end of calibration and ADC enable.
05029   *         Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
05030   * @note   For devices with differential mode available:
05031   *         Calibration of offset is specific to each of
05032   *         single-ended and differential modes
05033   *         (calibration run must be performed for each of these
05034   *         differential modes, if used afterwards and if the application
05035   *         requires their calibration).
05036   * @note   On this STM32 serie, setting of this feature is conditioned to
05037   *         ADC state:
05038   *         ADC must be ADC disabled.
05039   * @rmtoll CR       ADCAL          LL_ADC_StartCalibration\n
05040   *         CR       ADCALDIF       LL_ADC_StartCalibration
05041   * @param  ADCx ADC instance
05042   * @param  SingleDiff This parameter can be one of the following values:
05043   *         @arg @ref LL_ADC_SINGLE_ENDED
05044   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
05045   * @retval None
05046   */
05047 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff)
05048 {
05049   /* Note: Write register with some additional bits forced to state reset     */
05050   /*       instead of modifying only the selected bit for this function,      */
05051   /*       to not interfere with bits with HW property "rs".                  */
05052   MODIFY_REG(ADCx->CR,
05053              ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,
05054              ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
05055 }
05056
05057 /**
05058   * @brief  Get ADC calibration state.
05059   * @rmtoll CR       ADCAL          LL_ADC_IsCalibrationOnGoing
05060   * @param  ADCx ADC instance
05061   * @retval 0: calibration complete, 1: calibration in progress.
05062   */
05063 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
05064 {
05065   return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
05066 }
05067
05068 /**
05069   * @}
05070   */
05071
05072 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
05073   * @{
05074   */
05075
05076 /**
05077   * @brief  Start ADC group regular conversion.
05078   * @note   On this STM32 serie, this function is relevant for both
05079   *         internal trigger (SW start) and external trigger:
05080   *         - If ADC trigger has been set to software start, ADC conversion
05081   *           starts immediately.
05082   *         - If ADC trigger has been set to external trigger, ADC conversion
05083   *           will start at next trigger event (on the selected trigger edge)
05084   *           following the ADC start conversion command.
05085   * @note   On this STM32 serie, setting of this feature is conditioned to
05086   *         ADC state:
05087   *         ADC must be enabled without conversion on going on group regular,
05088   *         without conversion stop command on going on group regular,
05089   *         without ADC disable command on going.
05090   * @rmtoll CR       ADSTART        LL_ADC_REG_StartConversion
05091   * @param  ADCx ADC instance
05092   * @retval None
05093   */
05094 __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
05095 {
05096   /* Note: Write register with some additional bits forced to state reset     */
05097   /*       instead of modifying only the selected bit for this function,      */
05098   /*       to not interfere with bits with HW property "rs".                  */
05099   MODIFY_REG(ADCx->CR,
05100              ADC_CR_BITS_PROPERTY_RS,
05101              ADC_CR_ADSTART);
05102 }
05103
05104 /**
05105   * @brief  Stop ADC group regular conversion.
05106   * @note   On this STM32 serie, setting of this feature is conditioned to
05107   *         ADC state:
05108   *         ADC must be enabled with conversion on going on group regular,
05109   *         without ADC disable command on going.
05110   * @rmtoll CR       ADSTP          LL_ADC_REG_StopConversion
05111   * @param  ADCx ADC instance
05112   * @retval None
05113   */
05114 __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
05115 {
05116   /* Note: Write register with some additional bits forced to state reset     */
05117   /*       instead of modifying only the selected bit for this function,      */
05118   /*       to not interfere with bits with HW property "rs".                  */
05119   MODIFY_REG(ADCx->CR,
05120              ADC_CR_BITS_PROPERTY_RS,
05121              ADC_CR_ADSTP);
05122 }
05123
05124 /**
05125   * @brief  Get ADC group regular conversion state.
05126   * @rmtoll CR       ADSTART        LL_ADC_REG_IsConversionOngoing
05127   * @param  ADCx ADC instance
05128   * @retval 0: no conversion is on going on ADC group regular.
05129   */
05130 __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
05131 {
05132   return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
05133 }
05134
05135 /**
05136   * @brief  Get ADC group regular command of conversion stop state
05137   * @rmtoll CR       ADSTP          LL_ADC_REG_IsStopConversionOngoing
05138   * @param  ADCx ADC instance
05139   * @retval 0: no command of conversion stop is on going on ADC group regular.
05140   */
05141 __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
05142 {
05143   return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
05144 }
05145
05146 /**
05147   * @brief  Get ADC group regular conversion data, range fit for
05148   *         all ADC configurations: all ADC resolutions and
05149   *         all oversampling increased data width (for devices
05150   *         with feature oversampling).
05151   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData32
05152   * @param  ADCx ADC instance
05153   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
05154   */
05155 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
05156 {
05157   return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
05158 }
05159
05160 /**
05161   * @brief  Get ADC group regular conversion data, range fit for
05162   *         ADC resolution 12 bits.
05163   * @note   For devices with feature oversampling: Oversampling
05164   *         can increase data width, function for extended range
05165   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
05166   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData12
05167   * @param  ADCx ADC instance
05168   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
05169   */
05170 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
05171 {
05172   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
05173 }
05174
05175 /**
05176   * @brief  Get ADC group regular conversion data, range fit for
05177   *         ADC resolution 10 bits.
05178   * @note   For devices with feature oversampling: Oversampling
05179   *         can increase data width, function for extended range
05180   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
05181   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData10
05182   * @param  ADCx ADC instance
05183   * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
05184   */
05185 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
05186 {
05187   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
05188 }
05189
05190 /**
05191   * @brief  Get ADC group regular conversion data, range fit for
05192   *         ADC resolution 8 bits.
05193   * @note   For devices with feature oversampling: Oversampling
05194   *         can increase data width, function for extended range
05195   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
05196   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData8
05197   * @param  ADCx ADC instance
05198   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
05199   */
05200 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
05201 {
05202   return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
05203 }
05204
05205 /**
05206   * @brief  Get ADC group regular conversion data, range fit for
05207   *         ADC resolution 6 bits.
05208   * @note   For devices with feature oversampling: Oversampling
05209   *         can increase data width, function for extended range
05210   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
05211   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData6
05212   * @param  ADCx ADC instance
05213   * @retval Value between Min_Data=0x00 and Max_Data=0x3F
05214   */
05215 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
05216 {
05217   return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
05218 }
05219
05220 /**
05221   * @}
05222   */
05223
05224 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
05225   * @{
05226   */
05227
05228 /**
05229   * @brief  Start ADC group injected conversion.
05230   * @note   On this STM32 serie, this function is relevant for both
05231   *         internal trigger (SW start) and external trigger:
05232   *         - If ADC trigger has been set to software start, ADC conversion
05233   *           starts immediately.
05234   *         - If ADC trigger has been set to external trigger, ADC conversion
05235   *           will start at next trigger event (on the selected trigger edge)
05236   *           following the ADC start conversion command.
05237   * @note   On this STM32 serie, setting of this feature is conditioned to
05238   *         ADC state:
05239   *         ADC must be enabled without conversion on going on group injected,
05240   *         without conversion stop command on going on group injected,
05241   *         without ADC disable command on going.
05242   * @rmtoll CR       JADSTART       LL_ADC_INJ_StartConversion
05243   * @param  ADCx ADC instance
05244   * @retval None
05245   */
05246 __STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
05247 {
05248   /* Note: Write register with some additional bits forced to state reset     */
05249   /*       instead of modifying only the selected bit for this function,      */
05250   /*       to not interfere with bits with HW property "rs".                  */
05251   MODIFY_REG(ADCx->CR,
05252              ADC_CR_BITS_PROPERTY_RS,
05253              ADC_CR_JADSTART);
05254 }
05255
05256 /**
05257   * @brief  Stop ADC group injected conversion.
05258   * @note   On this STM32 serie, setting of this feature is conditioned to
05259   *         ADC state:
05260   *         ADC must be enabled with conversion on going on group injected,
05261   *         without ADC disable command on going.
05262   * @rmtoll CR       JADSTP         LL_ADC_INJ_StopConversion
05263   * @param  ADCx ADC instance
05264   * @retval None
05265   */
05266 __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
05267 {
05268   /* Note: Write register with some additional bits forced to state reset     */
05269   /*       instead of modifying only the selected bit for this function,      */
05270   /*       to not interfere with bits with HW property "rs".                  */
05271   MODIFY_REG(ADCx->CR,
05272              ADC_CR_BITS_PROPERTY_RS,
05273              ADC_CR_JADSTP);
05274 }
05275
05276 /**
05277   * @brief  Get ADC group injected conversion state.
05278   * @rmtoll CR       JADSTART       LL_ADC_INJ_IsConversionOngoing
05279   * @param  ADCx ADC instance
05280   * @retval 0: no conversion is on going on ADC group injected.
05281   */
05282 __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)
05283 {
05284   return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
05285 }
05286
05287 /**
05288   * @brief  Get ADC group injected command of conversion stop state
05289   * @rmtoll CR       JADSTP         LL_ADC_INJ_IsStopConversionOngoing
05290   * @param  ADCx ADC instance
05291   * @retval 0: no command of conversion stop is on going on ADC group injected.
05292   */
05293 __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx)
05294 {
05295   return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);
05296 }
05297
05298 /**
05299   * @brief  Get ADC group injected conversion data, range fit for
05300   *         all ADC configurations: all ADC resolutions and
05301   *         all oversampling increased data width (for devices
05302   *         with feature oversampling).
05303   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData32\n
05304   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData32\n
05305   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData32\n
05306   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData32
05307   * @param  ADCx ADC instance
05308   * @param  Rank This parameter can be one of the following values:
05309   *         @arg @ref LL_ADC_INJ_RANK_1
05310   *         @arg @ref LL_ADC_INJ_RANK_2
05311   *         @arg @ref LL_ADC_INJ_RANK_3
05312   *         @arg @ref LL_ADC_INJ_RANK_4
05313   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
05314   */
05315 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
05316 {
05317   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
05318
05319   return (uint32_t)(READ_BIT(*preg,
05320                              ADC_JDR1_JDATA)
05321                    );
05322 }
05323
05324 /**
05325   * @brief  Get ADC group injected conversion data, range fit for
05326   *         ADC resolution 12 bits.
05327   * @note   For devices with feature oversampling: Oversampling
05328   *         can increase data width, function for extended range
05329   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
05330   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData12\n
05331   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData12\n
05332   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData12\n
05333   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData12
05334   * @param  ADCx ADC instance
05335   * @param  Rank This parameter can be one of the following values:
05336   *         @arg @ref LL_ADC_INJ_RANK_1
05337   *         @arg @ref LL_ADC_INJ_RANK_2
05338   *         @arg @ref LL_ADC_INJ_RANK_3
05339   *         @arg @ref LL_ADC_INJ_RANK_4
05340   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
05341   */
05342 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
05343 {
05344   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
05345
05346   return (uint16_t)(READ_BIT(*preg,
05347                              ADC_JDR1_JDATA)
05348                    );
05349 }
05350
05351 /**
05352   * @brief  Get ADC group injected conversion data, range fit for
05353   *         ADC resolution 10 bits.
05354   * @note   For devices with feature oversampling: Oversampling
05355   *         can increase data width, function for extended range
05356   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
05357   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData10\n
05358   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData10\n
05359   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData10\n
05360   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData10
05361   * @param  ADCx ADC instance
05362   * @param  Rank This parameter can be one of the following values:
05363   *         @arg @ref LL_ADC_INJ_RANK_1
05364   *         @arg @ref LL_ADC_INJ_RANK_2
05365   *         @arg @ref LL_ADC_INJ_RANK_3
05366   *         @arg @ref LL_ADC_INJ_RANK_4
05367   * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
05368   */
05369 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
05370 {
05371   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
05372
05373   return (uint16_t)(READ_BIT(*preg,
05374                              ADC_JDR1_JDATA)
05375                    );
05376 }
05377
05378 /**
05379   * @brief  Get ADC group injected conversion data, range fit for
05380   *         ADC resolution 8 bits.
05381   * @note   For devices with feature oversampling: Oversampling
05382   *         can increase data width, function for extended range
05383   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
05384   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData8\n
05385   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData8\n
05386   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData8\n
05387   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData8
05388   * @param  ADCx ADC instance
05389   * @param  Rank This parameter can be one of the following values:
05390   *         @arg @ref LL_ADC_INJ_RANK_1
05391   *         @arg @ref LL_ADC_INJ_RANK_2
05392   *         @arg @ref LL_ADC_INJ_RANK_3
05393   *         @arg @ref LL_ADC_INJ_RANK_4
05394   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
05395   */
05396 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
05397 {
05398   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
05399
05400   return (uint8_t)(READ_BIT(*preg,
05401                             ADC_JDR1_JDATA)
05402                   );
05403 }
05404
05405 /**
05406   * @brief  Get ADC group injected conversion data, range fit for
05407   *         ADC resolution 6 bits.
05408   * @note   For devices with feature oversampling: Oversampling
05409   *         can increase data width, function for extended range
05410   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
05411   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData6\n
05412   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData6\n
05413   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData6\n
05414   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData6
05415   * @param  ADCx ADC instance
05416   * @param  Rank This parameter can be one of the following values:
05417   *         @arg @ref LL_ADC_INJ_RANK_1
05418   *         @arg @ref LL_ADC_INJ_RANK_2
05419   *         @arg @ref LL_ADC_INJ_RANK_3
05420   *         @arg @ref LL_ADC_INJ_RANK_4
05421   * @retval Value between Min_Data=0x00 and Max_Data=0x3F
05422   */
05423 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
05424 {
05425   register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
05426
05427   return (uint8_t)(READ_BIT(*preg,
05428                             ADC_JDR1_JDATA)
05429                   );
05430 }
05431
05432 /**
05433   * @}
05434   */
05435
05436 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
05437   * @{
05438   */
05439
05440 /**
05441   * @brief  Get flag ADC ready.
05442   * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
05443   *         is enabled and when conversion clock is active.
05444   *         (not only core clock: this ADC has a dual clock domain)
05445   * @rmtoll ISR      ADRDY          LL_ADC_IsActiveFlag_ADRDY
05446   * @param  ADCx ADC instance
05447   * @retval State of bit (1 or 0).
05448   */
05449 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
05450 {
05451   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
05452 }
05453
05454 /**
05455   * @brief  Get flag ADC group regular end of unitary conversion.
05456   * @rmtoll ISR      EOC            LL_ADC_IsActiveFlag_EOC
05457   * @param  ADCx ADC instance
05458   * @retval State of bit (1 or 0).
05459   */
05460 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
05461 {
05462   return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
05463 }
05464
05465 /**
05466   * @brief  Get flag ADC group regular end of sequence conversions.
05467   * @rmtoll ISR      EOS            LL_ADC_IsActiveFlag_EOS
05468   * @param  ADCx ADC instance
05469   * @retval State of bit (1 or 0).
05470   */
05471 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
05472 {
05473   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
05474 }
05475
05476 /**
05477   * @brief  Get flag ADC group regular overrun.
05478   * @rmtoll ISR      OVR            LL_ADC_IsActiveFlag_OVR
05479   * @param  ADCx ADC instance
05480   * @retval State of bit (1 or 0).
05481   */
05482 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
05483 {
05484   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
05485 }
05486
05487 /**
05488   * @brief  Get flag ADC group regular end of sampling phase.
05489   * @rmtoll ISR      EOSMP          LL_ADC_IsActiveFlag_EOSMP
05490   * @param  ADCx ADC instance
05491   * @retval State of bit (1 or 0).
05492   */
05493 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
05494 {
05495   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
05496 }
05497
05498 /**
05499   * @brief  Get flag ADC group injected end of unitary conversion.
05500   * @rmtoll ISR      JEOC           LL_ADC_IsActiveFlag_JEOC
05501   * @param  ADCx ADC instance
05502   * @retval State of bit (1 or 0).
05503   */
05504 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx)
05505 {
05506   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL);
05507 }
05508
05509 /**
05510   * @brief  Get flag ADC group injected end of sequence conversions.
05511   * @rmtoll ISR      JEOS           LL_ADC_IsActiveFlag_JEOS
05512   * @param  ADCx ADC instance
05513   * @retval State of bit (1 or 0).
05514   */
05515 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
05516 {
05517   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL);
05518 }
05519
05520 /**
05521   * @brief  Get flag ADC group injected contexts queue overflow.
05522   * @rmtoll ISR      JQOVF          LL_ADC_IsActiveFlag_JQOVF
05523   * @param  ADCx ADC instance
05524   * @retval State of bit (1 or 0).
05525   */
05526 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx)
05527 {
05528   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL);
05529 }
05530
05531 /**
05532   * @brief  Get flag ADC analog watchdog 1 flag
05533   * @rmtoll ISR      AWD1           LL_ADC_IsActiveFlag_AWD1
05534   * @param  ADCx ADC instance
05535   * @retval State of bit (1 or 0).
05536   */
05537 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
05538 {
05539   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
05540 }
05541
05542 /**
05543   * @brief  Get flag ADC analog watchdog 2.
05544   * @rmtoll ISR      AWD2           LL_ADC_IsActiveFlag_AWD2
05545   * @param  ADCx ADC instance
05546   * @retval State of bit (1 or 0).
05547   */
05548 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)
05549 {
05550   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
05551 }
05552
05553 /**
05554   * @brief  Get flag ADC analog watchdog 3.
05555   * @rmtoll ISR      AWD3           LL_ADC_IsActiveFlag_AWD3
05556   * @param  ADCx ADC instance
05557   * @retval State of bit (1 or 0).
05558   */
05559 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)
05560 {
05561   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
05562 }
05563
05564 /**
05565   * @brief  Clear flag ADC ready.
05566   * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
05567   *         is enabled and when conversion clock is active.
05568   *         (not only core clock: this ADC has a dual clock domain)
05569   * @rmtoll ISR      ADRDY          LL_ADC_ClearFlag_ADRDY
05570   * @param  ADCx ADC instance
05571   * @retval None
05572   */
05573 __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
05574 {
05575   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
05576 }
05577
05578 /**
05579   * @brief  Clear flag ADC group regular end of unitary conversion.
05580   * @rmtoll ISR      EOC            LL_ADC_ClearFlag_EOC
05581   * @param  ADCx ADC instance
05582   * @retval None
05583   */
05584 __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
05585 {
05586   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
05587 }
05588
05589 /**
05590   * @brief  Clear flag ADC group regular end of sequence conversions.
05591   * @rmtoll ISR      EOS            LL_ADC_ClearFlag_EOS
05592   * @param  ADCx ADC instance
05593   * @retval None
05594   */
05595 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
05596 {
05597   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
05598 }
05599
05600 /**
05601   * @brief  Clear flag ADC group regular overrun.
05602   * @rmtoll ISR      OVR            LL_ADC_ClearFlag_OVR
05603   * @param  ADCx ADC instance
05604   * @retval None
05605   */
05606 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
05607 {
05608   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
05609 }
05610
05611 /**
05612   * @brief  Clear flag ADC group regular end of sampling phase.
05613   * @rmtoll ISR      EOSMP          LL_ADC_ClearFlag_EOSMP
05614   * @param  ADCx ADC instance
05615   * @retval None
05616   */
05617 __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
05618 {
05619   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
05620 }
05621
05622 /**
05623   * @brief  Clear flag ADC group injected end of unitary conversion.
05624   * @rmtoll ISR      JEOC           LL_ADC_ClearFlag_JEOC
05625   * @param  ADCx ADC instance
05626   * @retval None
05627   */
05628 __STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
05629 {
05630   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
05631 }
05632
05633 /**
05634   * @brief  Clear flag ADC group injected end of sequence conversions.
05635   * @rmtoll ISR      JEOS           LL_ADC_ClearFlag_JEOS
05636   * @param  ADCx ADC instance
05637   * @retval None
05638   */
05639 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
05640 {
05641   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
05642 }
05643
05644 /**
05645   * @brief  Clear flag ADC group injected contexts queue overflow.
05646   * @rmtoll ISR      JQOVF          LL_ADC_ClearFlag_JQOVF
05647   * @param  ADCx ADC instance
05648   * @retval None
05649   */
05650 __STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)
05651 {
05652   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);
05653 }
05654
05655 /**
05656   * @brief  Clear flag ADC analog watchdog 1.
05657   * @rmtoll ISR      AWD1           LL_ADC_ClearFlag_AWD1
05658   * @param  ADCx ADC instance
05659   * @retval None
05660   */
05661 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
05662 {
05663   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
05664 }
05665
05666 /**
05667   * @brief  Clear flag ADC analog watchdog 2.
05668   * @rmtoll ISR      AWD2           LL_ADC_ClearFlag_AWD2
05669   * @param  ADCx ADC instance
05670   * @retval None
05671   */
05672 __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
05673 {
05674   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
05675 }
05676
05677 /**
05678   * @brief  Clear flag ADC analog watchdog 3.
05679   * @rmtoll ISR      AWD3           LL_ADC_ClearFlag_AWD3
05680   * @param  ADCx ADC instance
05681   * @retval None
05682   */
05683 __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
05684 {
05685   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
05686 }
05687
05688 /**
05689   * @}
05690   */
05691
05692 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
05693   * @{
05694   */
05695
05696 /**
05697   * @brief  Enable ADC ready.
05698   * @rmtoll IER      ADRDYIE        LL_ADC_EnableIT_ADRDY
05699   * @param  ADCx ADC instance
05700   * @retval None
05701   */
05702 __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
05703 {
05704   SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
05705 }
05706
05707 /**
05708   * @brief  Enable interruption ADC group regular end of unitary conversion.
05709   * @rmtoll IER      EOCIE          LL_ADC_EnableIT_EOC
05710   * @param  ADCx ADC instance
05711   * @retval None
05712   */
05713 __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
05714 {
05715   SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
05716 }
05717
05718 /**
05719   * @brief  Enable interruption ADC group regular end of sequence conversions.
05720   * @rmtoll IER      EOSIE          LL_ADC_EnableIT_EOS
05721   * @param  ADCx ADC instance
05722   * @retval None
05723   */
05724 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
05725 {
05726   SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
05727 }
05728
05729 /**
05730   * @brief  Enable ADC group regular interruption overrun.
05731   * @rmtoll IER      OVRIE          LL_ADC_EnableIT_OVR
05732   * @param  ADCx ADC instance
05733   * @retval None
05734   */
05735 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
05736 {
05737   SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
05738 }
05739
05740 /**
05741   * @brief  Enable interruption ADC group regular end of sampling.
05742   * @rmtoll IER      EOSMPIE        LL_ADC_EnableIT_EOSMP
05743   * @param  ADCx ADC instance
05744   * @retval None
05745   */
05746 __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
05747 {
05748   SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
05749 }
05750
05751 /**
05752   * @brief  Enable interruption ADC group injected end of unitary conversion.
05753   * @rmtoll IER      JEOCIE         LL_ADC_EnableIT_JEOC
05754   * @param  ADCx ADC instance
05755   * @retval None
05756   */
05757 __STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
05758 {
05759   SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
05760 }
05761
05762 /**
05763   * @brief  Enable interruption ADC group injected end of sequence conversions.
05764   * @rmtoll IER      JEOSIE         LL_ADC_EnableIT_JEOS
05765   * @param  ADCx ADC instance
05766   * @retval None
05767   */
05768 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
05769 {
05770   SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
05771 }
05772
05773 /**
05774   * @brief  Enable interruption ADC group injected context queue overflow.
05775   * @rmtoll IER      JQOVFIE        LL_ADC_EnableIT_JQOVF
05776   * @param  ADCx ADC instance
05777   * @retval None
05778   */
05779 __STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)
05780 {
05781   SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
05782 }
05783
05784 /**
05785   * @brief  Enable interruption ADC analog watchdog 1.
05786   * @rmtoll IER      AWD1IE         LL_ADC_EnableIT_AWD1
05787   * @param  ADCx ADC instance
05788   * @retval None
05789   */
05790 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
05791 {
05792   SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
05793 }
05794
05795 /**
05796   * @brief  Enable interruption ADC analog watchdog 2.
05797   * @rmtoll IER      AWD2IE         LL_ADC_EnableIT_AWD2
05798   * @param  ADCx ADC instance
05799   * @retval None
05800   */
05801 __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
05802 {
05803   SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
05804 }
05805
05806 /**
05807   * @brief  Enable interruption ADC analog watchdog 3.
05808   * @rmtoll IER      AWD3IE         LL_ADC_EnableIT_AWD3
05809   * @param  ADCx ADC instance
05810   * @retval None
05811   */
05812 __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
05813 {
05814   SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
05815 }
05816
05817 /**
05818   * @brief  Disable interruption ADC ready.
05819   * @rmtoll IER      ADRDYIE        LL_ADC_DisableIT_ADRDY
05820   * @param  ADCx ADC instance
05821   * @retval None
05822   */
05823 __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
05824 {
05825   CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
05826 }
05827
05828 /**
05829   * @brief  Disable interruption ADC group regular end of unitary conversion.
05830   * @rmtoll IER      EOCIE          LL_ADC_DisableIT_EOC
05831   * @param  ADCx ADC instance
05832   * @retval None
05833   */
05834 __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
05835 {
05836   CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
05837 }
05838
05839 /**
05840   * @brief  Disable interruption ADC group regular end of sequence conversions.
05841   * @rmtoll IER      EOSIE          LL_ADC_DisableIT_EOS
05842   * @param  ADCx ADC instance
05843   * @retval None
05844   */
05845 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
05846 {
05847   CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
05848 }
05849
05850 /**
05851   * @brief  Disable interruption ADC group regular overrun.
05852   * @rmtoll IER      OVRIE          LL_ADC_DisableIT_OVR
05853   * @param  ADCx ADC instance
05854   * @retval None
05855   */
05856 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
05857 {
05858   CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
05859 }
05860
05861 /**
05862   * @brief  Disable interruption ADC group regular end of sampling.
05863   * @rmtoll IER      EOSMPIE        LL_ADC_DisableIT_EOSMP
05864   * @param  ADCx ADC instance
05865   * @retval None
05866   */
05867 __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
05868 {
05869   CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
05870 }
05871
05872 /**
05873   * @brief  Disable interruption ADC group regular end of unitary conversion.
05874   * @rmtoll IER      JEOCIE         LL_ADC_DisableIT_JEOC
05875   * @param  ADCx ADC instance
05876   * @retval None
05877   */
05878 __STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
05879 {
05880   CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
05881 }
05882
05883 /**
05884   * @brief  Disable interruption ADC group injected end of sequence conversions.
05885   * @rmtoll IER      JEOSIE         LL_ADC_DisableIT_JEOS
05886   * @param  ADCx ADC instance
05887   * @retval None
05888   */
05889 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
05890 {
05891   CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
05892 }
05893
05894 /**
05895   * @brief  Disable interruption ADC group injected context queue overflow.
05896   * @rmtoll IER      JQOVFIE        LL_ADC_DisableIT_JQOVF
05897   * @param  ADCx ADC instance
05898   * @retval None
05899   */
05900 __STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)
05901 {
05902   CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
05903 }
05904
05905 /**
05906   * @brief  Disable interruption ADC analog watchdog 1.
05907   * @rmtoll IER      AWD1IE         LL_ADC_DisableIT_AWD1
05908   * @param  ADCx ADC instance
05909   * @retval None
05910   */
05911 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
05912 {
05913   CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
05914 }
05915
05916 /**
05917   * @brief  Disable interruption ADC analog watchdog 2.
05918   * @rmtoll IER      AWD2IE         LL_ADC_DisableIT_AWD2
05919   * @param  ADCx ADC instance
05920   * @retval None
05921   */
05922 __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
05923 {
05924   CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
05925 }
05926
05927 /**
05928   * @brief  Disable interruption ADC analog watchdog 3.
05929   * @rmtoll IER      AWD3IE         LL_ADC_DisableIT_AWD3
05930   * @param  ADCx ADC instance
05931   * @retval None
05932   */
05933 __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
05934 {
05935   CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
05936 }
05937
05938 /**
05939   * @brief  Get state of interruption ADC ready
05940   *         (0: interrupt disabled, 1: interrupt enabled).
05941   * @rmtoll IER      ADRDYIE        LL_ADC_IsEnabledIT_ADRDY
05942   * @param  ADCx ADC instance
05943   * @retval State of bit (1 or 0).
05944   */
05945 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
05946 {
05947   return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
05948 }
05949
05950 /**
05951   * @brief  Get state of interruption ADC group regular end of unitary conversion
05952   *         (0: interrupt disabled, 1: interrupt enabled).
05953   * @rmtoll IER      EOCIE          LL_ADC_IsEnabledIT_EOC
05954   * @param  ADCx ADC instance
05955   * @retval State of bit (1 or 0).
05956   */
05957 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
05958 {
05959   return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
05960 }
05961
05962 /**
05963   * @brief  Get state of interruption ADC group regular end of sequence conversions
05964   *         (0: interrupt disabled, 1: interrupt enabled).
05965   * @rmtoll IER      EOSIE          LL_ADC_IsEnabledIT_EOS
05966   * @param  ADCx ADC instance
05967   * @retval State of bit (1 or 0).
05968   */
05969 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
05970 {
05971   return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
05972 }
05973
05974 /**
05975   * @brief  Get state of interruption ADC group regular overrun
05976   *         (0: interrupt disabled, 1: interrupt enabled).
05977   * @rmtoll IER      OVRIE          LL_ADC_IsEnabledIT_OVR
05978   * @param  ADCx ADC instance
05979   * @retval State of bit (1 or 0).
05980   */
05981 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
05982 {
05983   return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
05984 }
05985
05986 /**
05987   * @brief  Get state of interruption ADC group regular end of sampling
05988   *         (0: interrupt disabled, 1: interrupt enabled).
05989   * @rmtoll IER      EOSMPIE        LL_ADC_IsEnabledIT_EOSMP
05990   * @param  ADCx ADC instance
05991   * @retval State of bit (1 or 0).
05992   */
05993 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
05994 {
05995   return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
05996 }
05997
05998 /**
05999   * @brief  Get state of interruption ADC group injected end of unitary conversion
06000   *         (0: interrupt disabled, 1: interrupt enabled).
06001   * @rmtoll IER      JEOCIE         LL_ADC_IsEnabledIT_JEOC
06002   * @param  ADCx ADC instance
06003   * @retval State of bit (1 or 0).
06004   */
06005 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx)
06006 {
06007   return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL);
06008 }
06009
06010 /**
06011   * @brief  Get state of interruption ADC group injected end of sequence conversions
06012   *         (0: interrupt disabled, 1: interrupt enabled).
06013   * @rmtoll IER      JEOSIE         LL_ADC_IsEnabledIT_JEOS
06014   * @param  ADCx ADC instance
06015   * @retval State of bit (1 or 0).
06016   */
06017 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
06018 {
06019   return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL);
06020 }
06021
06022 /**
06023   * @brief  Get state of interruption ADC group injected context queue overflow interrupt state
06024   *         (0: interrupt disabled, 1: interrupt enabled).
06025   * @rmtoll IER      JQOVFIE        LL_ADC_IsEnabledIT_JQOVF
06026   * @param  ADCx ADC instance
06027   * @retval State of bit (1 or 0).
06028   */
06029 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx)
06030 {
06031   return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL);
06032 }
06033
06034 /**
06035   * @brief  Get state of interruption ADC analog watchdog 1
06036   *         (0: interrupt disabled, 1: interrupt enabled).
06037   * @rmtoll IER      AWD1IE         LL_ADC_IsEnabledIT_AWD1
06038   * @param  ADCx ADC instance
06039   * @retval State of bit (1 or 0).
06040   */
06041 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
06042 {
06043   return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
06044 }
06045
06046 /**
06047   * @brief  Get state of interruption Get ADC analog watchdog 2
06048   *         (0: interrupt disabled, 1: interrupt enabled).
06049   * @rmtoll IER      AWD2IE         LL_ADC_IsEnabledIT_AWD2
06050   * @param  ADCx ADC instance
06051   * @retval State of bit (1 or 0).
06052   */
06053 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)
06054 {
06055   return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
06056 }
06057
06058 /**
06059   * @brief  Get state of interruption Get ADC analog watchdog 3
06060   *         (0: interrupt disabled, 1: interrupt enabled).
06061   * @rmtoll IER      AWD3IE         LL_ADC_IsEnabledIT_AWD3
06062   * @param  ADCx ADC instance
06063   * @retval State of bit (1 or 0).
06064   */
06065 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx)
06066 {
06067   return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
06068 }
06069
06070 /**
06071   * @}
06072   */
06073
06074 #if defined(USE_FULL_LL_DRIVER)
06075 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
06076   * @{
06077   */
06078
06079 /* Initialization of some features of ADC common parameters and multimode */
06080 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
06081 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
06082 void        LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
06083
06084 /* De-initialization of ADC instance, ADC group regular and ADC group injected */
06085 /* (availability of ADC group injected depends on STM32 families) */
06086 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
06087
06088 /* Initialization of some features of ADC instance */
06089 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
06090 void        LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
06091
06092 /* Initialization of some features of ADC instance and ADC group regular */
06093 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
06094 void        LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
06095
06096 /* Initialization of some features of ADC instance and ADC group injected */
06097 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
06098 void        LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
06099
06100 /**
06101   * @}
06102   */
06103 #endif /* USE_FULL_LL_DRIVER */
06104
06105 /**
06106   * @}
06107   */
06108
06109 /**
06110   * @}
06111   */
06112
06113 #endif /* ADC1 */
06114
06115 /**
06116   * @}
06117   */
06118
06119 #ifdef __cplusplus
06120 }
06121 #endif
06122
06123 #endif /* STM32WBxx_LL_ADC_H */
06124
06125 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_bus.h Source File

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stm32wbxx_ll_bus.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_bus.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of BUS LL module.
00006
00007   @verbatim
00008                       ##### RCC Limitations #####
00009   ==============================================================================
00010     [..]
00011       A delay between an RCC peripheral clock enable and the effective peripheral
00012       enabling should be taken into account in order to manage the peripheral read/write
00013       from/to registers.
00014       (+) This delay depends on the peripheral mapping.
00015         (++) AHB & APB peripherals, 1 dummy read is necessary
00016
00017     [..]
00018       Workarounds:
00019       (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
00020           inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
00021
00022   @endverbatim
00023   ******************************************************************************
00024   * @attention
00025   *
00026   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00027   * All rights reserved.</center></h2>
00028   *
00029   * This software component is licensed by ST under BSD 3-Clause license,
00030   * the "License"; You may not use this file except in compliance with the
00031   * License. You may obtain a copy of the License at:
00032   *                        opensource.org/licenses/BSD-3-Clause
00033   *
00034   ******************************************************************************
00035   */
00036
00037 /* Define to prevent recursive inclusion -------------------------------------*/
00038 #ifndef STM32WBxx_LL_BUS_H
00039 #define STM32WBxx_LL_BUS_H
00040
00041 #ifdef __cplusplus
00042 extern "C" {
00043 #endif
00044
00045 /* Includes ------------------------------------------------------------------*/
00046 #include "stm32wbxx.h"
00047
00048 /** @addtogroup STM32WBxx_LL_Driver
00049   * @{
00050   */
00051
00052 #if defined(RCC)
00053
00054 /** @defgroup BUS_LL BUS
00055   * @{
00056   */
00057
00058 /* Private types -------------------------------------------------------------*/
00059 /* Private variables ---------------------------------------------------------*/
00060
00061 /* Private constants ---------------------------------------------------------*/
00062
00063 /* Private macros ------------------------------------------------------------*/
00064
00065 /* Exported types ------------------------------------------------------------*/
00066
00067 /* Exported constants --------------------------------------------------------*/
00068 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
00069   * @{
00070   */
00071
00072 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH  AHB1 GRP1 PERIPH
00073   * @{
00074   */
00075 #define LL_AHB1_GRP1_PERIPH_ALL            (0xFFFFFFFFU)
00076
00077 #define LL_AHB1_GRP1_PERIPH_DMA1           RCC_AHB1ENR_DMA1EN
00078 #if defined(DMA2)
00079 #define LL_AHB1_GRP1_PERIPH_DMA2           RCC_AHB1ENR_DMA2EN
00080 #endif
00081 #define LL_AHB1_GRP1_PERIPH_DMAMUX1        RCC_AHB1ENR_DMAMUX1EN
00082 #define LL_AHB1_GRP1_PERIPH_SRAM1          RCC_AHB1SMENR_SRAM1SMEN
00083 #define LL_AHB1_GRP1_PERIPH_CRC            RCC_AHB1ENR_CRCEN
00084 #define LL_AHB1_GRP1_PERIPH_TSC            RCC_AHB1ENR_TSCEN
00085 /**
00086   * @}
00087   */
00088
00089 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH  AHB2 GRP1 PERIPH
00090   * @{
00091   */
00092 #define LL_AHB2_GRP1_PERIPH_ALL            (0xFFFFFFFFU)
00093
00094 #define LL_AHB2_GRP1_PERIPH_GPIOA          RCC_AHB2ENR_GPIOAEN
00095 #define LL_AHB2_GRP1_PERIPH_GPIOB          RCC_AHB2ENR_GPIOBEN
00096 #define LL_AHB2_GRP1_PERIPH_GPIOC          RCC_AHB2ENR_GPIOCEN
00097 #if defined(GPIOD)
00098 #define LL_AHB2_GRP1_PERIPH_GPIOD          RCC_AHB2ENR_GPIODEN
00099 #endif
00100 #define LL_AHB2_GRP1_PERIPH_GPIOE          RCC_AHB2ENR_GPIOEEN
00101 #define LL_AHB2_GRP1_PERIPH_GPIOH          RCC_AHB2ENR_GPIOHEN
00102 #define LL_AHB2_GRP1_PERIPH_ADC            RCC_AHB2ENR_ADCEN
00103 #if defined(AES1)
00104 #define LL_AHB2_GRP1_PERIPH_AES1           RCC_AHB2ENR_AES1EN
00105 #endif
00106 /**
00107   * @}
00108   */
00109
00110 /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH  AHB3 GRP1 PERIPH
00111   * @{
00112   */
00113 #define LL_AHB3_GRP1_PERIPH_ALL            (0xFFFFFFFFU)
00114 #if defined(QUADSPI)
00115 #define LL_AHB3_GRP1_PERIPH_QUADSPI        RCC_AHB3ENR_QUADSPIEN
00116 #endif
00117 #define LL_AHB3_GRP1_PERIPH_PKA            RCC_AHB3ENR_PKAEN
00118 #define LL_AHB3_GRP1_PERIPH_AES2           RCC_AHB3ENR_AES2EN
00119 #define LL_AHB3_GRP1_PERIPH_RNG            RCC_AHB3ENR_RNGEN
00120 #define LL_AHB3_GRP1_PERIPH_HSEM           RCC_AHB3ENR_HSEMEN
00121 #define LL_AHB3_GRP1_PERIPH_IPCC           RCC_AHB3ENR_IPCCEN
00122 #define LL_AHB3_GRP1_PERIPH_SRAM2          RCC_AHB3SMENR_SRAM2SMEN
00123 #define LL_AHB3_GRP1_PERIPH_FLASH          RCC_AHB3ENR_FLASHEN
00124 /**
00125   * @}
00126   */
00127
00128 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH  APB1 GRP1 PERIPH
00129   * @{
00130   */
00131 #define LL_APB1_GRP1_PERIPH_ALL            (0xFFFFFFFFU)
00132 #define LL_APB1_GRP1_PERIPH_TIM2           RCC_APB1ENR1_TIM2EN
00133 #if defined(LCD)
00134 #define LL_APB1_GRP1_PERIPH_LCD            RCC_APB1ENR1_LCDEN
00135 #endif
00136 #define LL_APB1_GRP1_PERIPH_RTCAPB         RCC_APB1ENR1_RTCAPBEN
00137 #define LL_APB1_GRP1_PERIPH_WWDG           RCC_APB1ENR1_WWDGEN
00138 #if defined(SPI2)
00139 #define LL_APB1_GRP1_PERIPH_SPI2           RCC_APB1ENR1_SPI2EN
00140 #endif
00141 #define LL_APB1_GRP1_PERIPH_I2C1           RCC_APB1ENR1_I2C1EN
00142 #if defined(I2C3)
00143 #define LL_APB1_GRP1_PERIPH_I2C3           RCC_APB1ENR1_I2C3EN
00144 #endif
00145 #if defined(CRS)
00146 #define LL_APB1_GRP1_PERIPH_CRS            RCC_APB1ENR1_CRSEN
00147 #endif
00148 #if defined(USB)
00149 #define LL_APB1_GRP1_PERIPH_USB            RCC_APB1ENR1_USBEN
00150 #endif
00151 #define LL_APB1_GRP1_PERIPH_LPTIM1         RCC_APB1ENR1_LPTIM1EN
00152 /**
00153   * @}
00154   */
00155
00156
00157 /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH  APB1 GRP2 PERIPH
00158   * @{
00159   */
00160 #define LL_APB1_GRP2_PERIPH_ALL            (0xFFFFFFFFU)
00161
00162 #if defined(LPUART1)
00163 #define LL_APB1_GRP2_PERIPH_LPUART1        RCC_APB1ENR2_LPUART1EN
00164 #endif
00165 #define LL_APB1_GRP2_PERIPH_LPTIM2         RCC_APB1ENR2_LPTIM2EN
00166 /**
00167   * @}
00168   */
00169
00170 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH  APB2 GRP1 PERIPH
00171   * @{
00172   */
00173 #define LL_APB2_GRP1_PERIPH_ALL            (0xFFFFFFFFU)
00174
00175 #define LL_APB2_GRP1_PERIPH_TIM1           RCC_APB2ENR_TIM1EN
00176 #define LL_APB2_GRP1_PERIPH_SPI1           RCC_APB2ENR_SPI1EN
00177 #define LL_APB2_GRP1_PERIPH_USART1         RCC_APB2ENR_USART1EN
00178 #define LL_APB2_GRP1_PERIPH_TIM16          RCC_APB2ENR_TIM16EN
00179 #define LL_APB2_GRP1_PERIPH_TIM17          RCC_APB2ENR_TIM17EN
00180 #if defined(SAI1)
00181 #define LL_APB2_GRP1_PERIPH_SAI1           RCC_APB2ENR_SAI1EN
00182 #endif
00183 /**
00184   * @}
00185   */
00186
00187 /** @defgroup BUS_LL_EC_APB3_GRP1_PERIPH  APB3 GRP1 PERIPH
00188   * @{
00189   */
00190 #define LL_APB3_GRP1_PERIPH_ALL            (0xFFFFFFFFU)
00191 #define LL_APB3_GRP1_PERIPH_RF             RCC_APB3RSTR_RFRST
00192 /**
00193   * @}
00194   */
00195
00196
00197 /** @defgroup BUS_LL_EC_C2_AHB1_GRP1_PERIPH  C2 AHB1 GRP1 PERIPH
00198   * @{
00199   */
00200 #define LL_C2_AHB1_GRP1_PERIPH_DMA1         RCC_C2AHB1ENR_DMA1EN
00201 #if defined(DMA2)
00202 #define LL_C2_AHB1_GRP1_PERIPH_DMA2         RCC_C2AHB1ENR_DMA2EN
00203 #endif
00204 #define LL_C2_AHB1_GRP1_PERIPH_DMAMUX1      RCC_C2AHB1ENR_DMAMUX1EN
00205 #define LL_C2_AHB1_GRP1_PERIPH_SRAM1        RCC_C2AHB1ENR_SRAM1EN
00206 #define LL_C2_AHB1_GRP1_PERIPH_CRC          RCC_C2AHB1ENR_CRCEN
00207 #define LL_C2_AHB1_GRP1_PERIPH_TSC          RCC_C2AHB1ENR_TSCEN
00208 /**
00209   * @}
00210   */
00211
00212
00213 /** @defgroup BUS_LL_EC_C2_AHB2_GRP1_PERIPH  C2 AHB2 GRP1 PERIPH
00214   * @{
00215   */
00216 #define LL_C2_AHB2_GRP1_PERIPH_GPIOA        RCC_C2AHB2ENR_GPIOAEN
00217 #define LL_C2_AHB2_GRP1_PERIPH_GPIOB        RCC_C2AHB2ENR_GPIOBEN
00218 #define LL_C2_AHB2_GRP1_PERIPH_GPIOC        RCC_C2AHB2ENR_GPIOCEN
00219 #if defined(GPIOD)
00220 #define LL_C2_AHB2_GRP1_PERIPH_GPIOD        RCC_C2AHB2ENR_GPIODEN
00221 #endif
00222 #define LL_C2_AHB2_GRP1_PERIPH_GPIOE        RCC_C2AHB2ENR_GPIOEEN
00223 #define LL_C2_AHB2_GRP1_PERIPH_GPIOH        RCC_C2AHB2ENR_GPIOHEN
00224 #define LL_C2_AHB2_GRP1_PERIPH_ADC          RCC_C2AHB2ENR_ADCEN
00225 #if defined(AES1)
00226 #define LL_C2_AHB2_GRP1_PERIPH_AES1         RCC_C2AHB2ENR_AES1EN
00227 #endif
00228 /**
00229   * @}
00230   */
00231
00232
00233 /** @defgroup BUS_LL_EC_C2_AHB3_GRP1_PERIPH  C2 AHB3 GRP1 PERIPH
00234   * @{
00235   */
00236 #define LL_C2_AHB3_GRP1_PERIPH_PKA          RCC_C2AHB3ENR_PKAEN
00237 #define LL_C2_AHB3_GRP1_PERIPH_AES2         RCC_C2AHB3ENR_AES2EN
00238 #define LL_C2_AHB3_GRP1_PERIPH_RNG          RCC_C2AHB3ENR_RNGEN
00239 #define LL_C2_AHB3_GRP1_PERIPH_HSEM         RCC_C2AHB3ENR_HSEMEN
00240 #define LL_C2_AHB3_GRP1_PERIPH_IPCC         RCC_C2AHB3ENR_IPCCEN
00241 #define LL_C2_AHB3_GRP1_PERIPH_FLASH        RCC_C2AHB3ENR_FLASHEN
00242 #define LL_C2_AHB3_GRP1_PERIPH_SRAM2        RCC_C2AHB3SMENR_SRAM2SMEN
00243 /**
00244   * @}
00245   */
00246
00247
00248 /** @defgroup BUS_LL_EC_C2_APB1_GRP1_PERIPH  C2 APB1 GRP1 PERIPH
00249   * @{
00250   */
00251 #define LL_C2_APB1_GRP1_PERIPH_TIM2         RCC_C2APB1ENR1_TIM2EN
00252 #if defined(LCD)
00253 #define LL_C2_APB1_GRP1_PERIPH_LCD          RCC_C2APB1ENR1_LCDEN
00254 #endif
00255 #define LL_C2_APB1_GRP1_PERIPH_RTCAPB       RCC_C2APB1ENR1_RTCAPBEN
00256 #if defined(SPI2)
00257 #define LL_C2_APB1_GRP1_PERIPH_SPI2         RCC_C2APB1ENR1_SPI2EN
00258 #endif
00259 #define LL_C2_APB1_GRP1_PERIPH_I2C1         RCC_C2APB1ENR1_I2C1EN
00260 #if defined(I2C3)
00261 #define LL_C2_APB1_GRP1_PERIPH_I2C3         RCC_C2APB1ENR1_I2C3EN
00262 #define LL_C2_APB1_GRP1_PERIPH_CRS          RCC_C2APB1ENR1_CRSEN
00263 #define LL_C2_APB1_GRP1_PERIPH_USB          RCC_C2APB1ENR1_USBEN
00264 #endif
00265 #define LL_C2_APB1_GRP1_PERIPH_LPTIM1       RCC_C2APB1ENR1_LPTIM1EN
00266 /**
00267   * @}
00268   */
00269
00270
00271 /** @defgroup BUS_LL_EC_C2_APB1_GRP2_PERIPH  C2 APB1 GRP2 PERIPH
00272   * @{
00273   */
00274 #if defined(LPUART1)
00275 #define LL_C2_APB1_GRP2_PERIPH_LPUART1      RCC_C2APB1ENR2_LPUART1EN
00276 #endif
00277 #define LL_C2_APB1_GRP2_PERIPH_LPTIM2       RCC_C2APB1ENR2_LPTIM2EN
00278 /**
00279   * @}
00280   */
00281
00282
00283 /** @defgroup BUS_LL_EC_C2_APB2_GRP1_PERIPH  C2 APB2 GRP1 PERIPH
00284   * @{
00285   */
00286 #define LL_C2_APB2_GRP1_PERIPH_TIM1         RCC_C2APB2ENR_TIM1EN
00287 #define LL_C2_APB2_GRP1_PERIPH_SPI1         RCC_C2APB2ENR_SPI1EN
00288 #define LL_C2_APB2_GRP1_PERIPH_USART1       RCC_C2APB2ENR_USART1EN
00289 #define LL_C2_APB2_GRP1_PERIPH_TIM16        RCC_C2APB2ENR_TIM16EN
00290 #define LL_C2_APB2_GRP1_PERIPH_TIM17        RCC_C2APB2ENR_TIM17EN
00291 #if defined(SAI1)
00292 #define LL_C2_APB2_GRP1_PERIPH_SAI1         RCC_C2APB2ENR_SAI1EN
00293 #endif
00294 /**
00295   * @}
00296   */
00297
00298
00299 /** @defgroup BUS_LL_EC_C2_APB3_GRP1_PERIPH  C2 APB3 GRP1 PERIPH
00300   * @{
00301   */
00302 #define LL_C2_APB3_GRP1_PERIPH_BLE          RCC_C2APB3ENR_BLEEN
00303 #define LL_C2_APB3_GRP1_PERIPH_802          RCC_C2APB3ENR_802EN
00304 /**
00305   * @}
00306   */
00307
00308
00309 /**
00310   * @}
00311   */
00312
00313 /* Exported macro ------------------------------------------------------------*/
00314
00315 /* Exported functions --------------------------------------------------------*/
00316
00317 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
00318   * @{
00319   */
00320
00321 /** @defgroup BUS_LL_EF_AHB1 AHB1
00322   * @{
00323   */
00324
00325 /**
00326   * @brief  Enable AHB1 peripherals clock.
00327   * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_EnableClock\n
00328   *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_EnableClock\n
00329   *         AHB1ENR      DMAMUX1EN      LL_AHB1_GRP1_EnableClock\n
00330   *         AHB1ENR      CRCEN         LL_AHB1_GRP1_EnableClock\n
00331   *         AHB1ENR      TSCEN         LL_AHB1_GRP1_EnableClock
00332   * @param  Periphs This parameter can be a combination of the following values:
00333   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00334   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
00335   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
00336   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
00337   *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC
00338   * @retval None
00339 */
00340 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
00341 {
00342   __IO uint32_t tmpreg;
00343   SET_BIT(RCC->AHB1ENR, Periphs);
00344   /* Delay after an RCC peripheral clock enabling */
00345   tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
00346   (void)tmpreg;
00347 }
00348
00349 /**
00350   * @brief  Check if AHB1 peripheral clock is enabled or not
00351   * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_IsEnabledClock\n
00352   *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_IsEnabledClock\n
00353   *         AHB1ENR      DMAMUX1EN      LL_AHB1_GRP1_IsEnabledClock\n
00354   *         AHB1ENR      CRCEN         LL_AHB1_GRP1_IsEnabledClock\n
00355   *         AHB1ENR      TSCEN         LL_AHB1_GRP1_IsEnabledClock
00356   * @param  Periphs This parameter can be a combination of the following values:
00357   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00358   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
00359   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
00360   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
00361   *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC
00362   * @retval uint32_t
00363 */
00364 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
00365 {
00366   return ((READ_BIT(RCC->AHB1ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
00367 }
00368
00369 /**
00370   * @brief  Disable AHB1 peripherals clock.
00371   * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_DisableClock\n
00372   *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_DisableClock\n
00373   *         AHB1ENR      DMAMUX1EN      LL_AHB1_GRP1_DisableClock\n
00374   *         AHB1ENR      CRCEN         LL_AHB1_GRP1_DisableClock\n
00375   *         AHB1ENR      TSCEN         LL_AHB1_GRP1_DisableClock
00376   * @param  Periphs This parameter can be a combination of the following values:
00377   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00378   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
00379   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
00380   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
00381   *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC
00382   * @retval None
00383 */
00384 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
00385 {
00386   CLEAR_BIT(RCC->AHB1ENR, Periphs);
00387 }
00388
00389 /**
00390   * @brief  Force AHB1 peripherals reset.
00391   * @rmtoll AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ForceReset\n
00392   *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ForceReset\n
00393   *         AHB1RSTR     DMAMUX1RST     LL_AHB1_GRP1_ForceReset\n
00394   *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ForceReset\n
00395   *         AHB1RSTR     TSCRST        LL_AHB1_GRP1_ForceReset
00396   * @param  Periphs This parameter can be a combination of the following values:
00397   *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
00398   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00399   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
00400   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
00401   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
00402   *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC
00403   * @retval None
00404 */
00405 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
00406 {
00407   SET_BIT(RCC->AHB1RSTR, Periphs);
00408 }
00409
00410 /**
00411   * @brief  Release AHB1 peripherals reset.
00412   * @rmtoll AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ReleaseReset\n
00413   *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ReleaseReset\n
00414   *         AHB1RSTR     DMAMUX1RST     LL_AHB1_GRP1_ReleaseReset\n
00415   *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ReleaseReset\n
00416   *         AHB1RSTR     TSCRST        LL_AHB1_GRP1_ReleaseReset
00417   * @param  Periphs This parameter can be a combination of the following values:
00418   *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
00419   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00420   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
00421   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
00422   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
00423   *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC
00424   * @retval None
00425 */
00426 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
00427 {
00428   CLEAR_BIT(RCC->AHB1RSTR, Periphs);
00429 }
00430
00431 /**
00432   * @brief  Enable AHB1 peripherals clock during Low Power (Sleep) mode.
00433   * @rmtoll AHB1SMENR    DMA1SMEN      LL_AHB1_GRP1_EnableClockSleep\n
00434   *         AHB1SMENR    DMA2SMEN      LL_AHB1_GRP1_EnableClockSleep\n
00435   *         AHB1SMENR    DMAMUX1SMEN    LL_AHB1_GRP1_EnableClockSleep\n
00436   *         AHB1SMENR    SRAM1SMEN     LL_AHB1_GRP1_EnableClockSleep\n
00437   *         AHB1SMENR    CRCSMEN       LL_AHB1_GRP1_EnableClockSleep\n
00438   *         AHB1SMENR    TSCSMEN       LL_AHB1_GRP1_EnableClockSleep
00439   * @param  Periphs This parameter can be a combination of the following values:
00440   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00441   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
00442   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
00443   *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
00444   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
00445   *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC
00446   * @retval None
00447 */
00448 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
00449 {
00450   __IO uint32_t tmpreg;
00451   SET_BIT(RCC->AHB1SMENR, Periphs);
00452   /* Delay after an RCC peripheral clock enabling */
00453   tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs);
00454   (void)tmpreg;
00455 }
00456
00457 /**
00458   * @brief  Disable AHB1 peripherals clock during Low Power (Sleep) mode.
00459   * @rmtoll AHB1SMENR    DMA1SMEN      LL_AHB1_GRP1_DisableClockSleep\n
00460   *         AHB1SMENR    DMA2SMEN      LL_AHB1_GRP1_DisableClockSleep\n
00461   *         AHB1SMENR    DMAMUX1SMEN    LL_AHB1_GRP1_DisableClockSleep\n
00462   *         AHB1SMENR    SRAM1SMEN     LL_AHB1_GRP1_DisableClockSleep\n
00463   *         AHB1SMENR    CRCSMEN       LL_AHB1_GRP1_DisableClockSleep\n
00464   *         AHB1SMENR    TSCSMEN       LL_AHB1_GRP1_DisableClockSleep
00465   * @param  Periphs This parameter can be a combination of the following values:
00466   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00467   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
00468   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
00469   *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
00470   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
00471   *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC
00472   * @retval None
00473 */
00474 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
00475 {
00476   CLEAR_BIT(RCC->AHB1SMENR, Periphs);
00477 }
00478
00479 /**
00480   * @}
00481   */
00482
00483 /** @defgroup BUS_LL_EF_AHB2 AHB2
00484   * @{
00485   */
00486
00487 /**
00488   * @brief  Enable AHB2 peripherals clock.
00489   * @rmtoll AHB2ENR      GPIOAEN       LL_AHB2_GRP1_EnableClock\n
00490   *         AHB2ENR      GPIOBEN       LL_AHB2_GRP1_EnableClock\n
00491   *         AHB2ENR      GPIOCEN       LL_AHB2_GRP1_EnableClock\n
00492   *         AHB2ENR      GPIODEN       LL_AHB2_GRP1_EnableClock\n
00493   *         AHB2ENR      GPIOEEN       LL_AHB2_GRP1_EnableClock\n
00494   *         AHB2ENR      GPIOHEN       LL_AHB2_GRP1_EnableClock\n
00495   *         AHB2ENR      ADCEN         LL_AHB2_GRP1_EnableClock\n
00496   *         AHB2ENR      AES1EN        LL_AHB2_GRP1_EnableClock
00497   * @param  Periphs This parameter can be a combination of the following values:
00498   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
00499   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
00500   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
00501   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
00502   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
00503   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
00504   *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC
00505   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES1
00506   * @retval None
00507 */
00508 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
00509 {
00510   __IO uint32_t tmpreg;
00511   SET_BIT(RCC->AHB2ENR, Periphs);
00512   /* Delay after an RCC peripheral clock enabling */
00513   tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
00514   (void)tmpreg;
00515 }
00516
00517 /**
00518   * @brief  Check if AHB2 peripheral clock is enabled or not
00519   * @rmtoll AHB2ENR      GPIOAEN       LL_AHB2_GRP1_IsEnabledClock\n
00520   *         AHB2ENR      GPIOBEN       LL_AHB2_GRP1_IsEnabledClock\n
00521   *         AHB2ENR      GPIOCEN       LL_AHB2_GRP1_IsEnabledClock\n
00522   *         AHB2ENR      GPIODEN       LL_AHB2_GRP1_IsEnabledClock\n
00523   *         AHB2ENR      GPIOEEN       LL_AHB2_GRP1_IsEnabledClock\n
00524   *         AHB2ENR      GPIOHEN       LL_AHB2_GRP1_IsEnabledClock\n
00525   *         AHB2ENR      ADCEN         LL_AHB2_GRP1_IsEnabledClock\n
00526   *         AHB2ENR      AES1EN        LL_AHB2_GRP1_IsEnabledClock
00527   * @param  Periphs This parameter can be a combination of the following values:
00528   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
00529   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
00530   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
00531   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
00532   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
00533   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
00534   *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC
00535   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES1
00536   * @retval uint32_t
00537 */
00538 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
00539 {
00540   return ((READ_BIT(RCC->AHB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
00541 }
00542
00543 /**
00544   * @brief  Disable AHB2 peripherals clock.
00545   * @rmtoll AHB2ENR      GPIOAEN       LL_AHB2_GRP1_DisableClock\n
00546   *         AHB2ENR      GPIOBEN       LL_AHB2_GRP1_DisableClock\n
00547   *         AHB2ENR      GPIOCEN       LL_AHB2_GRP1_DisableClock\n
00548   *         AHB2ENR      GPIODEN       LL_AHB2_GRP1_DisableClock\n
00549   *         AHB2ENR      GPIOEEN       LL_AHB2_GRP1_DisableClock\n
00550   *         AHB2ENR      GPIOHEN       LL_AHB2_GRP1_DisableClock\n
00551   *         AHB2ENR      ADCEN         LL_AHB2_GRP1_DisableClock\n
00552   *         AHB2ENR      AES1EN        LL_AHB2_GRP1_DisableClock
00553   * @param  Periphs This parameter can be a combination of the following values:
00554   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
00555   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
00556   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
00557   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
00558   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
00559   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
00560   *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC
00561   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES1
00562   * @retval None
00563 */
00564 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
00565 {
00566   CLEAR_BIT(RCC->AHB2ENR, Periphs);
00567 }
00568
00569 /**
00570   * @brief  Force AHB2 peripherals reset.
00571   * @rmtoll AHB2RSTR     GPIOARST      LL_AHB2_GRP1_ForceReset\n
00572   *         AHB2RSTR     GPIOBRST      LL_AHB2_GRP1_ForceReset\n
00573   *         AHB2RSTR     GPIOCRST      LL_AHB2_GRP1_ForceReset\n
00574   *         AHB2RSTR     GPIODRST      LL_AHB2_GRP1_ForceReset\n
00575   *         AHB2RSTR     GPIOERST      LL_AHB2_GRP1_ForceReset\n
00576   *         AHB2RSTR     GPIOHRST      LL_AHB2_GRP1_ForceReset\n
00577   *         AHB2RSTR     ADCRST        LL_AHB2_GRP1_ForceReset\n
00578   *         AHB2RSTR     AES1RST       LL_AHB2_GRP1_ForceReset
00579   * @param  Periphs This parameter can be a combination of the following values:
00580   *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL
00581   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
00582   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
00583   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
00584   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
00585   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
00586   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
00587   *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC
00588   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES1
00589   * @retval None
00590 */
00591 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
00592 {
00593   SET_BIT(RCC->AHB2RSTR, Periphs);
00594 }
00595
00596 /**
00597   * @brief  Release AHB2 peripherals reset.
00598   * @rmtoll AHB2RSTR     GPIOARST      LL_AHB2_GRP1_ReleaseReset\n
00599   *         AHB2RSTR     GPIOBRST      LL_AHB2_GRP1_ReleaseReset\n
00600   *         AHB2RSTR     GPIOCRST      LL_AHB2_GRP1_ReleaseReset\n
00601   *         AHB2RSTR     GPIODRST      LL_AHB2_GRP1_ReleaseReset\n
00602   *         AHB2RSTR     GPIOERST      LL_AHB2_GRP1_ReleaseReset\n
00603   *         AHB2RSTR     GPIOHRST      LL_AHB2_GRP1_ReleaseReset\n
00604   *         AHB2RSTR     ADCRST        LL_AHB2_GRP1_ReleaseReset\n
00605   *         AHB2RSTR     AES1RST       LL_AHB2_GRP1_ReleaseReset
00606   * @param  Periphs This parameter can be a combination of the following values:
00607   *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL
00608   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
00609   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
00610   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
00611   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
00612   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
00613   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
00614   *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC
00615   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES1
00616   * @retval None
00617 */
00618 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
00619 {
00620   CLEAR_BIT(RCC->AHB2RSTR, Periphs);
00621 }
00622
00623 /**
00624   * @brief  Enable AHB2 peripherals clock during Low Power (Sleep) mode.
00625   * @rmtoll AHB2SMENR    GPIOASMEN     LL_AHB2_GRP1_EnableClockSleep\n
00626   *         AHB2SMENR    GPIOBSMEN     LL_AHB2_GRP1_EnableClockSleep\n
00627   *         AHB2SMENR    GPIOCSMEN     LL_AHB2_GRP1_EnableClockSleep\n
00628   *         AHB2SMENR    GPIODSMEN     LL_AHB2_GRP1_EnableClockSleep\n
00629   *         AHB2SMENR    GPIOESMEN     LL_AHB2_GRP1_EnableClockSleep\n
00630   *         AHB2SMENR    GPIOHSMEN     LL_AHB2_GRP1_EnableClockSleep\n
00631   *         AHB2SMENR    ADCSMEN       LL_AHB2_GRP1_EnableClockSleep\n
00632   *         AHB2SMENR    AES1SMEN      LL_AHB2_GRP1_EnableClockSleep
00633   * @param  Periphs This parameter can be a combination of the following values:
00634   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
00635   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
00636   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
00637   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
00638   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
00639   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
00640   *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC
00641   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES1
00642   * @retval None
00643 */
00644 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)
00645 {
00646   __IO uint32_t tmpreg;
00647   SET_BIT(RCC->AHB2SMENR, Periphs);
00648   /* Delay after an RCC peripheral clock enabling */
00649   tmpreg = READ_BIT(RCC->AHB2SMENR, Periphs);
00650   (void)tmpreg;
00651 }
00652
00653 /**
00654   * @brief  Disable AHB2 peripherals clock during Low Power (Sleep) mode.
00655   * @rmtoll AHB2SMENR    GPIOASMEN     LL_AHB2_GRP1_DisableClockSleep\n
00656   *         AHB2SMENR    GPIOBSMEN     LL_AHB2_GRP1_DisableClockSleep\n
00657   *         AHB2SMENR    GPIOCSMEN     LL_AHB2_GRP1_DisableClockSleep\n
00658   *         AHB2SMENR    GPIODSMEN     LL_AHB2_GRP1_DisableClockSleep\n
00659   *         AHB2SMENR    GPIOESMEN     LL_AHB2_GRP1_DisableClockSleep\n
00660   *         AHB2SMENR    GPIOHSMEN     LL_AHB2_GRP1_DisableClockSleep\n
00661   *         AHB2SMENR    ADCSMEN       LL_AHB2_GRP1_DisableClockSleep\n
00662   *         AHB2SMENR    AES1SMEN      LL_AHB2_GRP1_DisableClockSleep
00663   * @param  Periphs This parameter can be a combination of the following values:
00664   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
00665   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
00666   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
00667   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
00668   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
00669   *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
00670   *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC
00671   *         @arg @ref LL_AHB2_GRP1_PERIPH_AES1
00672   * @retval None
00673 */
00674 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)
00675 {
00676   CLEAR_BIT(RCC->AHB2SMENR, Periphs);
00677 }
00678
00679 /**
00680   * @}
00681   */
00682
00683 /** @defgroup BUS_LL_EF_AHB3 AHB3
00684   * @{
00685   */
00686
00687 /**
00688   * @brief  Enable AHB3 peripherals clock.
00689   * @rmtoll AHB3ENR      QUADSPIEN     LL_AHB3_GRP1_EnableClock\n
00690   *         AHB3ENR      PKAEN         LL_AHB3_GRP1_EnableClock\n
00691   *         AHB3ENR      AES2EN        LL_AHB3_GRP1_EnableClock\n
00692   *         AHB3ENR      RNGEN         LL_AHB3_GRP1_EnableClock\n
00693   *         AHB3ENR      HSEMEN        LL_AHB3_GRP1_EnableClock\n
00694   *         AHB3ENR      IPCCEN        LL_AHB3_GRP1_EnableClock\n
00695   *         AHB3ENR      FLASHEN       LL_AHB3_GRP1_EnableClock
00696   * @param  Periphs This parameter can be a combination of the following values:
00697   *         @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI
00698   *         @arg @ref LL_AHB3_GRP1_PERIPH_PKA
00699   *         @arg @ref LL_AHB3_GRP1_PERIPH_AES2
00700   *         @arg @ref LL_AHB3_GRP1_PERIPH_RNG
00701   *         @arg @ref LL_AHB3_GRP1_PERIPH_HSEM
00702   *         @arg @ref LL_AHB3_GRP1_PERIPH_IPCC
00703   *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
00704   * @retval None
00705 */
00706 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
00707 {
00708   __IO uint32_t tmpreg;
00709   SET_BIT(RCC->AHB3ENR, Periphs);
00710   /* Delay after an RCC peripheral clock enabling */
00711   tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
00712   (void)tmpreg;
00713 }
00714
00715 /**
00716   * @brief  Check if AHB3 peripheral clock is enabled or not
00717   * @rmtoll AHB3ENR      QUADSPIEN     LL_AHB3_GRP1_IsEnabledClock\n
00718   *         AHB3ENR      PKAEN         LL_AHB3_GRP1_IsEnabledClock\n
00719   *         AHB3ENR      AES2EN        LL_AHB3_GRP1_IsEnabledClock\n
00720   *         AHB3ENR      RNGEN         LL_AHB3_GRP1_IsEnabledClock\n
00721   *         AHB3ENR      HSEMEN        LL_AHB3_GRP1_IsEnabledClock\n
00722   *         AHB3ENR      IPCCEN        LL_AHB3_GRP1_IsEnabledClock\n
00723   *         AHB3ENR      FLASHEN       LL_AHB3_GRP1_IsEnabledClock
00724   * @param  Periphs This parameter can be a combination of the following values:
00725   *         @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI
00726   *         @arg @ref LL_AHB3_GRP1_PERIPH_PKA
00727   *         @arg @ref LL_AHB3_GRP1_PERIPH_AES2
00728   *         @arg @ref LL_AHB3_GRP1_PERIPH_RNG
00729   *         @arg @ref LL_AHB3_GRP1_PERIPH_HSEM
00730   *         @arg @ref LL_AHB3_GRP1_PERIPH_IPCC
00731   *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
00732   * @retval uint32_t
00733 */
00734 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
00735 {
00736   return ((READ_BIT(RCC->AHB3ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
00737 }
00738
00739 /**
00740   * @brief  Disable AHB3 peripherals clock.
00741   * @rmtoll AHB3ENR      QUADSPIEN     LL_AHB3_GRP1_DisableClock\n
00742   *         AHB3ENR      PKAEN         LL_AHB3_GRP1_DisableClock\n
00743   *         AHB3ENR      AES2EN        LL_AHB3_GRP1_DisableClock\n
00744   *         AHB3ENR      RNGEN         LL_AHB3_GRP1_DisableClock\n
00745   *         AHB3ENR      HSEMEN        LL_AHB3_GRP1_DisableClock\n
00746   *         AHB3ENR      IPCCEN        LL_AHB3_GRP1_DisableClock\n
00747   *         AHB3ENR      FLASHEN       LL_AHB3_GRP1_DisableClock
00748   * @param  Periphs This parameter can be a combination of the following values:
00749   *         @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI
00750   *         @arg @ref LL_AHB3_GRP1_PERIPH_PKA
00751   *         @arg @ref LL_AHB3_GRP1_PERIPH_AES2
00752   *         @arg @ref LL_AHB3_GRP1_PERIPH_RNG
00753   *         @arg @ref LL_AHB3_GRP1_PERIPH_HSEM
00754   *         @arg @ref LL_AHB3_GRP1_PERIPH_IPCC
00755   *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
00756   * @retval None
00757 */
00758 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
00759 {
00760   CLEAR_BIT(RCC->AHB3ENR, Periphs);
00761 }
00762
00763 /**
00764   * @brief  Force AHB3 peripherals reset.
00765   * @rmtoll AHB3RSTR     QUADSPIRST       LL_AHB3_GRP1_ForceReset\n
00766   *         AHB3RSTR     PKARST        LL_AHB3_GRP1_ForceReset\n
00767   *         AHB3RSTR     AES2RST       LL_AHB3_GRP1_ForceReset\n
00768   *         AHB3RSTR     RNGRST        LL_AHB3_GRP1_ForceReset\n
00769   *         AHB3RSTR     HSEMRST       LL_AHB3_GRP1_ForceReset\n
00770   *         AHB3RSTR     IPCCRST       LL_AHB3_GRP1_ForceReset\n
00771   *         AHB3RSTR     FLASHRST      LL_AHB3_GRP1_ForceReset
00772   * @param  Periphs This parameter can be a combination of the following values:
00773   *         @arg @ref LL_AHB3_GRP1_PERIPH_ALL
00774   *         @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI
00775   *         @arg @ref LL_AHB3_GRP1_PERIPH_PKA
00776   *         @arg @ref LL_AHB3_GRP1_PERIPH_AES2
00777   *         @arg @ref LL_AHB3_GRP1_PERIPH_RNG
00778   *         @arg @ref LL_AHB3_GRP1_PERIPH_HSEM
00779   *         @arg @ref LL_AHB3_GRP1_PERIPH_IPCC
00780   *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
00781   * @retval None
00782 */
00783 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
00784 {
00785   SET_BIT(RCC->AHB3RSTR, Periphs);
00786 }
00787
00788 /**
00789   * @brief  Release AHB3 peripherals reset.
00790   * @rmtoll AHB3RSTR     QUADSPIRST    LL_AHB3_GRP1_ReleaseReset\n
00791   *         AHB3RSTR     PKARST        LL_AHB3_GRP1_ReleaseReset\n
00792   *         AHB3RSTR     AES2RST       LL_AHB3_GRP1_ReleaseReset\n
00793   *         AHB3RSTR     RNGRST        LL_AHB3_GRP1_ReleaseReset\n
00794   *         AHB3RSTR     HSEMRST       LL_AHB3_GRP1_ReleaseReset\n
00795   *         AHB3RSTR     IPCCRST       LL_AHB3_GRP1_ReleaseReset\n
00796   *         AHB3RSTR     FLASHRST      LL_AHB3_GRP1_ReleaseReset
00797   * @param  Periphs This parameter can be a combination of the following values:
00798   *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL
00799   *         @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI
00800   *         @arg @ref LL_AHB3_GRP1_PERIPH_PKA
00801   *         @arg @ref LL_AHB3_GRP1_PERIPH_AES2
00802   *         @arg @ref LL_AHB3_GRP1_PERIPH_RNG
00803   *         @arg @ref LL_AHB3_GRP1_PERIPH_HSEM
00804   *         @arg @ref LL_AHB3_GRP1_PERIPH_IPCC
00805   *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
00806   * @retval None
00807 */
00808 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
00809 {
00810   CLEAR_BIT(RCC->AHB3RSTR, Periphs);
00811 }
00812
00813 /**
00814   * @brief  Enable AHB3 peripherals clock during Low Power (Sleep) mode.
00815   * @rmtoll AHB3SMENR    QUADSPISMEN   LL_AHB3_GRP1_EnableClockSleep\n
00816   *         AHB3SMENR    PKASMEN       LL_AHB3_GRP1_EnableClockSleep\n
00817   *         AHB3SMENR    AES2SMEN      LL_AHB3_GRP1_EnableClockSleep\n
00818   *         AHB3SMENR    RNGSMEN       LL_AHB3_GRP1_EnableClockSleep\n
00819   *         AHB3SMENR    SRAM2SMEN     LL_AHB3_GRP1_EnableClockSleep\n
00820   *         AHB3SMENR    FLASHSMEN     LL_AHB3_GRP1_EnableClockSleep
00821   * @param  Periphs This parameter can be a combination of the following values:
00822   *         @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI
00823   *         @arg @ref LL_AHB3_GRP1_PERIPH_PKA
00824   *         @arg @ref LL_AHB3_GRP1_PERIPH_AES2
00825   *         @arg @ref LL_AHB3_GRP1_PERIPH_RNG
00826   *         @arg @ref LL_AHB3_GRP1_PERIPH_SRAM2
00827   *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
00828   * @retval None
00829 */
00830 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)
00831 {
00832   __IO uint32_t tmpreg;
00833   SET_BIT(RCC->AHB3SMENR, Periphs);
00834   /* Delay after an RCC peripheral clock enabling */
00835   tmpreg = READ_BIT(RCC->AHB3SMENR, Periphs);
00836   (void)tmpreg;
00837 }
00838
00839 /**
00840   * @brief  Disable AHB3 peripherals clock during Low Power (Sleep) mode.
00841   * @rmtoll AHB3SMENR    QUADSPISMEN   LL_AHB3_GRP1_DisableClockSleep\n
00842   *         AHB3SMENR    PKASMEN       LL_AHB3_GRP1_DisableClockSleep\n
00843   *         AHB3SMENR    AES2SMEN      LL_AHB3_GRP1_DisableClockSleep\n
00844   *         AHB3SMENR    RNGSMEN       LL_AHB3_GRP1_DisableClockSleep\n
00845   *         AHB3SMENR    SRAM2SMEN     LL_AHB3_GRP1_DisableClockSleep\n
00846   *         AHB3SMENR    FLASHSMEN     LL_AHB3_GRP1_DisableClockSleep
00847   * @param  Periphs This parameter can be a combination of the following values:
00848   *         @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI
00849   *         @arg @ref LL_AHB3_GRP1_PERIPH_PKA
00850   *         @arg @ref LL_AHB3_GRP1_PERIPH_AES2
00851   *         @arg @ref LL_AHB3_GRP1_PERIPH_RNG
00852   *         @arg @ref LL_AHB3_GRP1_PERIPH_SRAM2
00853   *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
00854   * @retval None
00855 */
00856 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
00857 {
00858   CLEAR_BIT(RCC->AHB3SMENR, Periphs);
00859 }
00860
00861 /**
00862   * @}
00863   */
00864
00865 /** @defgroup BUS_LL_EF_APB1 APB1
00866   * @{
00867   */
00868
00869 /**
00870   * @brief  Enable APB1 peripherals clock.
00871   * @rmtoll APB1ENR1     TIM2EN        LL_APB1_GRP1_EnableClock\n
00872   *         APB1ENR1     LCDEN         LL_APB1_GRP1_EnableClock\n
00873   *         APB1ENR1     RTCAPBEN      LL_APB1_GRP1_EnableClock\n
00874   *         APB1ENR1     WWDGEN        LL_APB1_GRP1_EnableClock\n
00875   *         APB1ENR1     SPI2EN        LL_APB1_GRP1_EnableClock\n
00876   *         APB1ENR1     I2C1EN        LL_APB1_GRP1_EnableClock\n
00877   *         APB1ENR1     I2C3EN        LL_APB1_GRP1_EnableClock\n
00878   *         APB1ENR1     CRSEN         LL_APB1_GRP1_EnableClock\n
00879   *         APB1ENR1     USBEN         LL_APB1_GRP1_EnableClock\n
00880   *         APB1ENR1     LPTIM1EN      LL_APB1_GRP1_EnableClock
00881   * @param  Periphs This parameter can be a combination of the following values:
00882   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
00883   *         @arg @ref LL_APB1_GRP1_PERIPH_LCD
00884   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
00885   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
00886   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
00887   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
00888   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
00889   *         @arg @ref LL_APB1_GRP1_PERIPH_CRS
00890   *         @arg @ref LL_APB1_GRP1_PERIPH_USB
00891   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
00892   * @retval None
00893 */
00894 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
00895 {
00896   __IO uint32_t tmpreg;
00897   SET_BIT(RCC->APB1ENR1, Periphs);
00898   /* Delay after an RCC peripheral clock enabling */
00899   tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);
00900   (void)tmpreg;
00901 }
00902
00903 /**
00904   * @brief  Enable APB1 peripherals clock.
00905   * @rmtoll APB1ENR2     LPUART1EN     LL_APB1_GRP2_EnableClock\n
00906   *         APB1ENR2     LPTIM2EN      LL_APB1_GRP2_EnableClock
00907   * @param  Periphs This parameter can be a combination of the following values:
00908   *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
00909   *         @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
00910   * @retval None
00911 */
00912 __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
00913 {
00914   __IO uint32_t tmpreg;
00915   SET_BIT(RCC->APB1ENR2, Periphs);
00916   /* Delay after an RCC peripheral clock enabling */
00917   tmpreg = READ_BIT(RCC->APB1ENR2, Periphs);
00918   (void)tmpreg;
00919 }
00920
00921 /**
00922   * @brief  Check if APB1 peripheral clock is enabled or not
00923   * @rmtoll APB1ENR1     TIM2EN        LL_APB1_GRP1_IsEnabledClock\n
00924   *         APB1ENR1     LCDEN         LL_APB1_GRP1_IsEnabledClock\n
00925   *         APB1ENR1     RTCAPBEN      LL_APB1_GRP1_IsEnabledClock\n
00926   *         APB1ENR1     WWDGEN        LL_APB1_GRP1_IsEnabledClock\n
00927   *         APB1ENR1     SPI2EN        LL_APB1_GRP1_IsEnabledClock\n
00928   *         APB1ENR1     I2C1EN        LL_APB1_GRP1_IsEnabledClock\n
00929   *         APB1ENR1     I2C3EN        LL_APB1_GRP1_IsEnabledClock\n
00930   *         APB1ENR1     CRSEN         LL_APB1_GRP1_IsEnabledClock\n
00931   *         APB1ENR1     USBEN         LL_APB1_GRP1_IsEnabledClock\n
00932   *         APB1ENR1     LPTIM1EN      LL_APB1_GRP1_IsEnabledClock
00933   * @param  Periphs This parameter can be a combination of the following values:
00934   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
00935   *         @arg @ref LL_APB1_GRP1_PERIPH_LCD
00936   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
00937   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
00938   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
00939   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
00940   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
00941   *         @arg @ref LL_APB1_GRP1_PERIPH_CRS
00942   *         @arg @ref LL_APB1_GRP1_PERIPH_USB
00943   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
00944   * @retval uint32_t
00945 */
00946 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
00947 {
00948   return ((READ_BIT(RCC->APB1ENR1, Periphs) == (Periphs)) ? 1UL : 0UL);
00949 }
00950
00951 /**
00952   * @brief  Check if APB1 peripheral clock is enabled or not
00953   * @rmtoll APB1ENR2     LPUART1EN     LL_APB1_GRP2_IsEnabledClock\n
00954   *         APB1ENR2     LPTIM2EN      LL_APB1_GRP2_IsEnabledClock
00955   * @param  Periphs This parameter can be a combination of the following values:
00956   *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
00957   *         @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
00958   * @retval uint32_t
00959 */
00960 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
00961 {
00962   return ((READ_BIT(RCC->APB1ENR2, Periphs) == (Periphs)) ? 1UL : 0UL);
00963 }
00964
00965 /**
00966   * @brief  Disable APB1 peripherals clock.
00967   * @rmtoll APB1ENR1     TIM2EN        LL_APB1_GRP1_DisableClock\n
00968   *         APB1ENR1     LCDEN         LL_APB1_GRP1_DisableClock\n
00969   *         APB1ENR1     RTCAPBEN      LL_APB1_GRP1_DisableClock\n
00970   *         APB1ENR1     SPI2EN        LL_APB1_GRP1_DisableClock\n
00971   *         APB1ENR1     I2C1EN        LL_APB1_GRP1_DisableClock\n
00972   *         APB1ENR1     I2C3EN        LL_APB1_GRP1_DisableClock\n
00973   *         APB1ENR1     CRSEN         LL_APB1_GRP1_DisableClock\n
00974   *         APB1ENR1     USBEN         LL_APB1_GRP1_DisableClock\n
00975   *         APB1ENR1     LPTIM1EN      LL_APB1_GRP1_DisableClock
00976   * @param  Periphs This parameter can be a combination of the following values:
00977   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
00978   *         @arg @ref LL_APB1_GRP1_PERIPH_LCD
00979   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
00980   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
00981   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
00982   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
00983   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
00984   *         @arg @ref LL_APB1_GRP1_PERIPH_CRS
00985   *         @arg @ref LL_APB1_GRP1_PERIPH_USB
00986   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
00987   * @retval None
00988 */
00989 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
00990 {
00991   CLEAR_BIT(RCC->APB1ENR1, Periphs);
00992 }
00993
00994 /**
00995   * @brief  Disable APB1 peripherals clock.
00996   * @rmtoll APB1ENR2     LPUART1EN     LL_APB1_GRP2_DisableClock\n
00997   *         APB1ENR2     LPTIM2EN      LL_APB1_GRP2_DisableClock
00998   * @param  Periphs This parameter can be a combination of the following values:
00999   *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
01000   *         @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
01001   * @retval None
01002 */
01003 __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
01004 {
01005   CLEAR_BIT(RCC->APB1ENR2, Periphs);
01006 }
01007
01008 /**
01009   * @brief  Force APB1 peripherals reset.
01010   * @rmtoll APB1RSTR1    TIM2RST       LL_APB1_GRP1_ForceReset\n
01011   *         APB1RSTR1    LCDRST        LL_APB1_GRP1_ForceReset\n
01012   *         APB1RSTR1    SPI2RST       LL_APB1_GRP1_ForceReset\n
01013   *         APB1RSTR1    I2C1RST       LL_APB1_GRP1_ForceReset\n
01014   *         APB1RSTR1    I2C3RST       LL_APB1_GRP1_ForceReset\n
01015   *         APB1RSTR1    CRSRST        LL_APB1_GRP1_ForceReset\n
01016   *         APB1RSTR1    USBRST        LL_APB1_GRP1_ForceReset\n
01017   *         APB1RSTR1    LPTIM1RST     LL_APB1_GRP1_ForceReset
01018   * @param  Periphs This parameter can be a combination of the following values:
01019   *         @arg @ref LL_APB1_GRP1_PERIPH_ALL
01020   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
01021   *         @arg @ref LL_APB1_GRP1_PERIPH_LCD
01022   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
01023   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
01024   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
01025   *         @arg @ref LL_APB1_GRP1_PERIPH_CRS
01026   *         @arg @ref LL_APB1_GRP1_PERIPH_USB
01027   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
01028   * @retval None
01029 */
01030 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
01031 {
01032   SET_BIT(RCC->APB1RSTR1, Periphs);
01033 }
01034
01035 /**
01036   * @brief  Force APB1 peripherals reset.
01037   * @rmtoll APB1RSTR2    LPUART1RST    LL_APB1_GRP2_ForceReset\n
01038   *         APB1RSTR2    LPTIM2RST     LL_APB1_GRP2_ForceReset
01039   * @param  Periphs This parameter can be a combination of the following values:
01040   *         @arg @ref LL_APB1_GRP2_PERIPH_ALL
01041   *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
01042   *         @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
01043   * @retval None
01044 */
01045 __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
01046 {
01047   SET_BIT(RCC->APB1RSTR2, Periphs);
01048 }
01049
01050 /**
01051   * @brief  Release APB1 peripherals reset.
01052   * @rmtoll APB1RSTR1    TIM2RST       LL_APB1_GRP1_ReleaseReset\n
01053   *         APB1RSTR1    LCDRST        LL_APB1_GRP1_ReleaseReset\n
01054   *         APB1RSTR1    SPI2RST       LL_APB1_GRP1_ReleaseReset\n
01055   *         APB1RSTR1    I2C1RST       LL_APB1_GRP1_ReleaseReset\n
01056   *         APB1RSTR1    I2C3RST       LL_APB1_GRP1_ReleaseReset\n
01057   *         APB1RSTR1    CRSRST        LL_APB1_GRP1_ReleaseReset\n
01058   *         APB1RSTR1    USBRST        LL_APB1_GRP1_ReleaseReset\n
01059   *         APB1RSTR1    LPTIM1RST     LL_APB1_GRP1_ReleaseReset
01060   * @param  Periphs This parameter can be a combination of the following values:
01061   *         @arg @ref LL_APB1_GRP1_PERIPH_ALL
01062   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
01063   *         @arg @ref LL_APB1_GRP1_PERIPH_LCD
01064   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
01065   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
01066   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
01067   *         @arg @ref LL_APB1_GRP1_PERIPH_CRS
01068   *         @arg @ref LL_APB1_GRP1_PERIPH_USB
01069   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
01070   * @retval None
01071 */
01072 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
01073 {
01074   CLEAR_BIT(RCC->APB1RSTR1, Periphs);
01075 }
01076
01077 /**
01078   * @brief  Release APB1 peripherals reset.
01079   * @rmtoll APB1RSTR2    LPUART1RST    LL_APB1_GRP2_ReleaseReset\n
01080   *         APB1RSTR2    LPTIM2RST     LL_APB1_GRP2_ReleaseReset
01081   * @param  Periphs This parameter can be a combination of the following values:
01082   *         @arg @ref LL_APB1_GRP2_PERIPH_ALL
01083   *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
01084   *         @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
01085   * @retval None
01086 */
01087 __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
01088 {
01089   CLEAR_BIT(RCC->APB1RSTR2, Periphs);
01090 }
01091
01092 /**
01093   * @brief  Enable APB1 peripherals clock during Low Power (Sleep) mode.
01094   * @rmtoll APB1SMENR1   TIM2SMEN      LL_APB1_GRP1_EnableClockSleep\n
01095   *         APB1SMENR1   LCDSMEN       LL_APB1_GRP1_EnableClockSleep\n
01096   *         APB1SMENR1   RTCAPBSMEN    LL_APB1_GRP1_EnableClockSleep\n
01097   *         APB1SMENR1   WWDGSMEN      LL_APB1_GRP1_EnableClockSleep\n
01098   *         APB1SMENR1   SPI2SMEN      LL_APB1_GRP1_EnableClockSleep\n
01099   *         APB1SMENR1   I2C1SMEN      LL_APB1_GRP1_EnableClockSleep\n
01100   *         APB1SMENR1   I2C3SMEN      LL_APB1_GRP1_EnableClockSleep\n
01101   *         APB1SMENR1   CRSSMEN       LL_APB1_GRP1_EnableClockSleep\n
01102   *         APB1SMENR1   USBSMEN       LL_APB1_GRP1_EnableClockSleep\n
01103   *         APB1SMENR1   LPTIM1SMEN    LL_APB1_GRP1_EnableClockSleep
01104   * @param  Periphs This parameter can be a combination of the following values:
01105   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
01106   *         @arg @ref LL_APB1_GRP1_PERIPH_LCD
01107   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
01108   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
01109   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
01110   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
01111   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
01112   *         @arg @ref LL_APB1_GRP1_PERIPH_CRS
01113   *         @arg @ref LL_APB1_GRP1_PERIPH_USB
01114   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
01115   * @retval None
01116 */
01117 __STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
01118 {
01119   __IO uint32_t tmpreg;
01120   SET_BIT(RCC->APB1SMENR1, Periphs);
01121   /* Delay after an RCC peripheral clock enabling */
01122   tmpreg = READ_BIT(RCC->APB1SMENR1, Periphs);
01123   (void)tmpreg;
01124 }
01125
01126 /**
01127   * @brief  Enable APB1 peripherals clock during Low Power (Sleep) mode.
01128   * @rmtoll APB1SMENR2   LPUART1SMEN   LL_APB1_GRP2_EnableClockSleep\n
01129   *         APB1SMENR2   LPTIM2SMEN    LL_APB1_GRP2_EnableClockSleep
01130   * @param  Periphs This parameter can be a combination of the following values:
01131   *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
01132   *         @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
01133   * @retval None
01134 */
01135 __STATIC_INLINE void LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
01136 {
01137   __IO uint32_t tmpreg;
01138   SET_BIT(RCC->APB1SMENR2, Periphs);
01139   /* Delay after an RCC peripheral clock enabling */
01140   tmpreg = READ_BIT(RCC->APB1SMENR2, Periphs);
01141   (void)tmpreg;
01142 }
01143
01144 /**
01145   * @brief  Disable APB1 peripherals clock during Low Power (Sleep) mode.
01146   * @rmtoll APB1SMENR1   TIM2SMEN      LL_APB1_GRP1_DisableClockSleep\n
01147   *         APB1SMENR1   LCDSMEN       LL_APB1_GRP1_DisableClockSleep\n
01148   *         APB1SMENR1   RTCAPBSMEN    LL_APB1_GRP1_DisableClockSleep\n
01149   *         APB1SMENR1   WWDGSMEN      LL_APB1_GRP1_DisableClockSleep\n
01150   *         APB1SMENR1   SPI2SMEN      LL_APB1_GRP1_DisableClockSleep\n
01151   *         APB1SMENR1   I2C1SMEN      LL_APB1_GRP1_DisableClockSleep\n
01152   *         APB1SMENR1   I2C3SMEN      LL_APB1_GRP1_DisableClockSleep\n
01153   *         APB1SMENR1   CRSSMEN       LL_APB1_GRP1_DisableClockSleep\n
01154   *         APB1SMENR1   USBSMEN       LL_APB1_GRP1_DisableClockSleep\n
01155   *         APB1SMENR1   LPTIM1SMEN    LL_APB1_GRP1_DisableClockSleep
01156   * @param  Periphs This parameter can be a combination of the following values:
01157   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
01158   *         @arg @ref LL_APB1_GRP1_PERIPH_LCD
01159   *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
01160   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
01161   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
01162   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
01163   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
01164   *         @arg @ref LL_APB1_GRP1_PERIPH_CRS
01165   *         @arg @ref LL_APB1_GRP1_PERIPH_USB
01166   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
01167   * @retval None
01168 */
01169 __STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
01170 {
01171   CLEAR_BIT(RCC->APB1SMENR1, Periphs);
01172 }
01173
01174 /**
01175   * @brief  Disable APB1 peripherals clock during Low Power (Sleep) mode.
01176   * @rmtoll APB1SMENR2   LPUART1SMEN   LL_APB1_GRP2_DisableClockSleep\n
01177   *         APB1SMENR2   LPTIM2SMEN    LL_APB1_GRP2_DisableClockSleep
01178   * @param  Periphs This parameter can be a combination of the following values:
01179   *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
01180   *         @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
01181   * @retval None
01182 */
01183 __STATIC_INLINE void LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
01184 {
01185   CLEAR_BIT(RCC->APB1SMENR2, Periphs);
01186 }
01187
01188 /**
01189   * @}
01190   */
01191
01192 /** @defgroup BUS_LL_EF_APB2 APB2
01193   * @{
01194   */
01195
01196 /**
01197   * @brief  Enable APB2 peripherals clock.
01198   * @rmtoll APB2ENR      TIM1EN        LL_APB2_GRP1_EnableClock\n
01199   *         APB2ENR      SPI1EN        LL_APB2_GRP1_EnableClock\n
01200   *         APB2ENR      USART1EN      LL_APB2_GRP1_EnableClock\n
01201   *         APB2ENR      TIM16EN       LL_APB2_GRP1_EnableClock\n
01202   *         APB2ENR      TIM17EN       LL_APB2_GRP1_EnableClock\n
01203   *         APB2ENR      SAI1EN        LL_APB2_GRP1_EnableClock
01204   * @param  Periphs This parameter can be a combination of the following values:
01205   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
01206   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
01207   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
01208   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
01209   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
01210   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
01211   * @retval None
01212 */
01213 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
01214 {
01215   __IO uint32_t tmpreg;
01216   SET_BIT(RCC->APB2ENR, Periphs);
01217   /* Delay after an RCC peripheral clock enabling */
01218   tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
01219   (void)tmpreg;
01220 }
01221
01222 /**
01223   * @brief  Check if APB2 peripheral clock is enabled or not
01224   * @rmtoll APB2ENR      TIM1EN        LL_APB2_GRP1_IsEnabledClock\n
01225   *         APB2ENR      SPI1EN        LL_APB2_GRP1_IsEnabledClock\n
01226   *         APB2ENR      USART1EN      LL_APB2_GRP1_IsEnabledClock\n
01227   *         APB2ENR      TIM16EN       LL_APB2_GRP1_IsEnabledClock\n
01228   *         APB2ENR      TIM17EN       LL_APB2_GRP1_IsEnabledClock\n
01229   *         APB2ENR      SAI1EN        LL_APB2_GRP1_IsEnabledClock
01230   * @param  Periphs This parameter can be a combination of the following values:
01231   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
01232   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
01233   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
01234   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
01235   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
01236   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
01237   * @retval uint32_t
01238 */
01239 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
01240 {
01241   return ((READ_BIT(RCC->APB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
01242 }
01243
01244 /**
01245   * @brief  Disable APB2 peripherals clock.
01246   * @rmtoll APB2ENR      TIM1EN        LL_APB2_GRP1_DisableClock\n
01247   *         APB2ENR      SPI1EN        LL_APB2_GRP1_DisableClock\n
01248   *         APB2ENR      USART1EN      LL_APB2_GRP1_DisableClock\n
01249   *         APB2ENR      TIM16EN       LL_APB2_GRP1_DisableClock\n
01250   *         APB2ENR      TIM17EN       LL_APB2_GRP1_DisableClock\n
01251   *         APB2ENR      SAI1EN        LL_APB2_GRP1_DisableClock
01252   * @param  Periphs This parameter can be a combination of the following values:
01253   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
01254   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
01255   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
01256   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
01257   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
01258   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
01259   * @retval None
01260 */
01261 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
01262 {
01263   CLEAR_BIT(RCC->APB2ENR, Periphs);
01264 }
01265
01266 /**
01267   * @brief  Force APB2 peripherals reset.
01268   * @rmtoll APB2RSTR     TIM1RST       LL_APB2_GRP1_ForceReset\n
01269   *         APB2RSTR     SPI1RST       LL_APB2_GRP1_ForceReset\n
01270   *         APB2RSTR     USART1RST     LL_APB2_GRP1_ForceReset\n
01271   *         APB2RSTR     TIM16RST      LL_APB2_GRP1_ForceReset\n
01272   *         APB2RSTR     TIM17RST      LL_APB2_GRP1_ForceReset\n
01273   *         APB2RSTR     SAI1RST       LL_APB2_GRP1_ForceReset
01274   * @param  Periphs This parameter can be a combination of the following values:
01275   *         @arg @ref LL_APB2_GRP1_PERIPH_ALL
01276   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
01277   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
01278   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
01279   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
01280   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
01281   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
01282   * @retval None
01283 */
01284 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
01285 {
01286   SET_BIT(RCC->APB2RSTR, Periphs);
01287 }
01288
01289 /**
01290   * @brief  Release APB2 peripherals reset.
01291   * @rmtoll APB2RSTR     TIM1RST       LL_APB2_GRP1_ReleaseReset\n
01292   *         APB2RSTR     SPI1RST       LL_APB2_GRP1_ReleaseReset\n
01293   *         APB2RSTR     USART1RST     LL_APB2_GRP1_ReleaseReset\n
01294   *         APB2RSTR     TIM16RST      LL_APB2_GRP1_ReleaseReset\n
01295   *         APB2RSTR     TIM17RST      LL_APB2_GRP1_ReleaseReset\n
01296   *         APB2RSTR     SAI1RST       LL_APB2_GRP1_ReleaseReset
01297   * @param  Periphs This parameter can be a combination of the following values:
01298   *         @arg @ref LL_APB2_GRP1_PERIPH_ALL
01299   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
01300   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
01301   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
01302   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
01303   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
01304   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
01305   * @retval None
01306 */
01307 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
01308 {
01309   CLEAR_BIT(RCC->APB2RSTR, Periphs);
01310 }
01311
01312 /**
01313   * @brief  Enable APB2 peripherals clock during Low Power (Sleep) mode.
01314   * @rmtoll APB2SMENR    TIM1SMEN      LL_APB2_GRP1_EnableClockSleep\n
01315   *         APB2SMENR    SPI1SMEN      LL_APB2_GRP1_EnableClockSleep\n
01316   *         APB2SMENR    USART1SMEN    LL_APB2_GRP1_EnableClockSleep\n
01317   *         APB2SMENR    TIM16SMEN     LL_APB2_GRP1_EnableClockSleep\n
01318   *         APB2SMENR    TIM17SMEN     LL_APB2_GRP1_EnableClockSleep\n
01319   *         APB2SMENR    SAI1SMEN      LL_APB2_GRP1_EnableClockSleep
01320   * @param  Periphs This parameter can be a combination of the following values:
01321   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
01322   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
01323   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
01324   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
01325   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
01326   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
01327   * @retval None
01328 */
01329 __STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
01330 {
01331   __IO uint32_t tmpreg;
01332   SET_BIT(RCC->APB2SMENR, Periphs);
01333   /* Delay after an RCC peripheral clock enabling */
01334   tmpreg = READ_BIT(RCC->APB2SMENR, Periphs);
01335   (void)tmpreg;
01336 }
01337
01338 /**
01339   * @brief  Disable APB2 peripherals clock during Low Power (Sleep) mode.
01340   * @rmtoll APB2SMENR    TIM1SMEN      LL_APB2_GRP1_DisableClockSleep\n
01341   *         APB2SMENR    SPI1SMEN      LL_APB2_GRP1_DisableClockSleep\n
01342   *         APB2SMENR    USART1SMEN    LL_APB2_GRP1_DisableClockSleep\n
01343   *         APB2SMENR    TIM16SMEN     LL_APB2_GRP1_DisableClockSleep\n
01344   *         APB2SMENR    TIM17SMEN     LL_APB2_GRP1_DisableClockSleep\n
01345   *         APB2SMENR    SAI1SMEN      LL_APB2_GRP1_DisableClockSleep
01346   * @param  Periphs This parameter can be a combination of the following values:
01347   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
01348   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
01349   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
01350   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
01351   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
01352   *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
01353   * @retval None
01354 */
01355 __STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
01356 {
01357   CLEAR_BIT(RCC->APB2SMENR, Periphs);
01358 }
01359
01360 /**
01361   * @}
01362   */
01363
01364 /** @defgroup BUS_LL_EF_APB3 APB3
01365   * @{
01366   */
01367
01368 /**
01369   * @brief  Force APB3 peripherals reset.
01370   * @rmtoll APB3RSTR     RFRST        LL_APB3_GRP1_ForceReset
01371   * @param  Periphs This parameter can be a combination of the following values:
01372   *         @arg @ref LL_APB3_GRP1_PERIPH_RF
01373   * @retval None
01374 */
01375 __STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t Periphs)
01376 {
01377   SET_BIT(RCC->APB3RSTR, Periphs);
01378 }
01379
01380 /**
01381   * @brief  Release APB3 peripherals reset.
01382   * @rmtoll APB3RSTR     RFRST        LL_APB3_GRP1_ReleaseReset
01383   * @param  Periphs This parameter can be a combination of the following values:
01384   *         @arg @ref LL_APB3_GRP1_PERIPH_RF
01385   * @retval None
01386 */
01387 __STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t Periphs)
01388 {
01389   CLEAR_BIT(RCC->APB3RSTR, Periphs);
01390 }
01391
01392 /**
01393   * @}
01394   */
01395
01396 /** @defgroup BUS_LL_EF_C2_AHB1 C2 AHB1
01397   * @{
01398   */
01399 /**
01400   * @brief  Enable C2AHB1 peripherals clock.
01401   * @rmtoll C2AHB1ENR    DMA1EN        LL_C2_AHB1_GRP1_EnableClock\n
01402   *         C2AHB1ENR    DMA2EN        LL_C2_AHB1_GRP1_EnableClock\n
01403   *         C2AHB1ENR    DMAMUX1EN     LL_C2_AHB1_GRP1_EnableClock\n
01404   *         C2AHB1ENR    SRAM1EN       LL_C2_AHB1_GRP1_EnableClock\n
01405   *         C2AHB1ENR    CRCEN         LL_C2_AHB1_GRP1_EnableClock\n
01406   *         C2AHB1ENR    TSCEN         LL_C2_AHB1_GRP1_EnableClock
01407   * @param  Periphs This parameter can be a combination of the following values:
01408   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1
01409   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2
01410   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1
01411   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_SRAM1
01412   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC
01413   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_TSC
01414   * @retval None
01415 */
01416
01417 __STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClock(uint32_t Periphs)
01418 {
01419   __IO uint32_t tmpreg;
01420   SET_BIT(RCC->C2AHB1ENR, Periphs);
01421   /* Delay after an RCC peripheral clock enabling */
01422   tmpreg = READ_BIT(RCC->C2AHB1ENR, Periphs);
01423   (void)tmpreg;
01424 }
01425
01426 /**
01427   * @brief  Check if C2AHB1 peripheral clock is enabled or not
01428   * @rmtoll C2AHB1ENR    DMA1EN        LL_C2_AHB1_GRP1_IsEnabledClock\n
01429   *         C2AHB1ENR    DMA2EN        LL_C2_AHB1_GRP1_IsEnabledClock\n
01430   *         C2AHB1ENR    DMAMUX1EN     LL_C2_AHB1_GRP1_IsEnabledClock\n
01431   *         C2AHB1ENR    SRAM1EN       LL_C2_AHB1_GRP1_IsEnabledClock\n
01432   *         C2AHB1ENR    CRCEN         LL_C2_AHB1_GRP1_IsEnabledClock\n
01433   *         C2AHB1ENR    TSCEN         LL_C2_AHB1_GRP1_IsEnabledClock
01434   * @param  Periphs This parameter can be a combination of the following values:
01435   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1
01436   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2
01437   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1
01438   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_SRAM1
01439   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC
01440   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_TSC
01441   * @retval uint32_t
01442 */
01443
01444 __STATIC_INLINE uint32_t LL_C2_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
01445 {
01446   return ((READ_BIT(RCC->C2AHB1ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
01447 }
01448
01449 /**
01450   * @brief  Disable C2AHB1 peripherals clock.
01451   * @rmtoll C2AHB1ENR    DMA1EN        LL_C2_AHB1_GRP1_DisableClock\n
01452   *         C2AHB1ENR    DMA2EN        LL_C2_AHB1_GRP1_DisableClock\n
01453   *         C2AHB1ENR    DMAMUX1EN     LL_C2_AHB1_GRP1_DisableClock\n
01454   *         C2AHB1ENR    SRAM1EN       LL_C2_AHB1_GRP1_DisableClock\n
01455   *         C2AHB1ENR    CRCEN         LL_C2_AHB1_GRP1_DisableClock\n
01456   *         C2AHB1ENR    TSCEN         LL_C2_AHB1_GRP1_DisableClock
01457   * @param  Periphs This parameter can be a combination of the following values:
01458   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1
01459   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2
01460   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1
01461   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_SRAM1
01462   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC
01463   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_TSC
01464   * @retval None
01465 */
01466
01467 __STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClock(uint32_t Periphs)
01468 {
01469   CLEAR_BIT(RCC->C2AHB1ENR, Periphs);
01470 }
01471
01472 /**
01473   * @brief  Enable C2AHB1 peripherals clock during Low Power (Sleep) mode.
01474   * @rmtoll C2AHB1SMENR  DMA1SMEN      LL_C2_AHB1_GRP1_EnableClockSleep\n
01475   *         C2AHB1SMENR  DMA2SMEN      LL_C2_AHB1_GRP1_EnableClockSleep\n
01476   *         C2AHB1SMENR  DMAMUX1SMEN   LL_C2_AHB1_GRP1_EnableClockSleep\n
01477   *         C2AHB1ENR    SRAM1SMEN     LL_C2_AHB1_GRP1_EnableClockSleep\n
01478   *         C2AHB1SMENR  CRCSMEN       LL_C2_AHB1_GRP1_EnableClockSleep\n
01479   *         C2AHB1SMENR  TSCSMEN       LL_C2_AHB1_GRP1_EnableClockSleep
01480   * @param  Periphs This parameter can be a combination of the following values:
01481   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1
01482   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2
01483   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1
01484   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_SRAM1
01485   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC
01486   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_TSC
01487   * @retval None
01488 */
01489
01490 __STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
01491 {
01492   __IO uint32_t tmpreg;
01493   SET_BIT(RCC->C2AHB1SMENR, Periphs);
01494   /* Delay after an RCC peripheral clock enabling */
01495   tmpreg = READ_BIT(RCC->C2AHB1SMENR, Periphs);
01496   (void)tmpreg;
01497 }
01498
01499 /**
01500   * @brief  Disable C2AHB1 peripherals clock during Low Power (Sleep) mode.
01501   * @rmtoll C2AHB1SMENR  DMA1SMEN      LL_C2_AHB1_GRP1_DisableClockSleep\n
01502   *         C2AHB1SMENR  DMA2SMEN      LL_C2_AHB1_GRP1_DisableClockSleep\n
01503   *         C2AHB1SMENR  DMAMUX1SMEN    LL_C2_AHB1_GRP1_DisableClockSleep\n
01504   *         C2AHB1ENR    SRAM1SMEN     LL_C2_AHB1_GRP1_DisableClockSleep\n
01505   *         C2AHB1SMENR  CRCSMEN       LL_C2_AHB1_GRP1_DisableClockSleep\n
01506   *         C2AHB1SMENR  TSCSMEN       LL_C2_AHB1_GRP1_DisableClockSleep
01507   * @param  Periphs This parameter can be a combination of the following values:
01508   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1
01509   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2
01510   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1
01511   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_SRAM1
01512   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC
01513   *         @arg @ref LL_C2_AHB1_GRP1_PERIPH_TSC
01514   * @retval None
01515 */
01516
01517 __STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
01518 {
01519   CLEAR_BIT(RCC->C2AHB1SMENR, Periphs);
01520 }
01521
01522 /**
01523   * @}
01524   */
01525
01526 /** @defgroup BUS_LL_EF_C2_AHB2 C2 AHB2
01527   * @{
01528   */
01529
01530 /**
01531   * @brief  Enable C2AHB2 peripherals clock.
01532   * @rmtoll C2AHB2ENR    GPIOAEN       LL_C2_AHB2_GRP1_EnableClock\n
01533   *         C2AHB2ENR    GPIOBEN       LL_C2_AHB2_GRP1_EnableClock\n
01534   *         C2AHB2ENR    GPIOCEN       LL_C2_AHB2_GRP1_EnableClock\n
01535   *         C2AHB2ENR    GPIODEN       LL_C2_AHB2_GRP1_EnableClock\n
01536   *         C2AHB2ENR    GPIOEEN       LL_C2_AHB2_GRP1_EnableClock\n
01537   *         C2AHB2ENR    GPIOHEN       LL_C2_AHB2_GRP1_EnableClock\n
01538   *         C2AHB2ENR    ADCEN         LL_C2_AHB2_GRP1_EnableClock\n
01539   *         C2AHB2ENR    AES1EN        LL_C2_AHB2_GRP1_EnableClock
01540   * @param  Periphs This parameter can be a combination of the following values:
01541   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA
01542   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB
01543   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC
01544   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD
01545   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOE
01546   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH
01547   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC
01548   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1
01549   * @retval None
01550 */
01551 __STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClock(uint32_t Periphs)
01552 {
01553   __IO uint32_t tmpreg;
01554   SET_BIT(RCC->C2AHB2ENR, Periphs);
01555   /* Delay after an RCC peripheral clock enabling */
01556   tmpreg = READ_BIT(RCC->C2AHB2ENR, Periphs);
01557   (void)tmpreg;
01558 }
01559
01560 /**
01561   * @brief  Check if C2AHB2 peripheral clock is enabled or not
01562   * @rmtoll C2AHB2ENR    GPIOAEN       LL_C2_AHB2_GRP1_IsEnabledClock\n
01563   *         C2AHB2ENR    GPIOBEN       LL_C2_AHB2_GRP1_IsEnabledClock\n
01564   *         C2AHB2ENR    GPIOCEN       LL_C2_AHB2_GRP1_IsEnabledClock\n
01565   *         C2AHB2ENR    GPIODEN       LL_C2_AHB2_GRP1_IsEnabledClock\n
01566   *         C2AHB2ENR    GPIOEEN       LL_C2_AHB2_GRP1_IsEnabledClock\n
01567   *         C2AHB2ENR    GPIOHEN       LL_C2_AHB2_GRP1_IsEnabledClock\n
01568   *         C2AHB2ENR    ADCEN         LL_C2_AHB2_GRP1_IsEnabledClock\n
01569   *         C2AHB2ENR    AES1EN        LL_C2_AHB2_GRP1_IsEnabledClock
01570   * @param  Periphs This parameter can be a combination of the following values:
01571   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA
01572   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB
01573   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC
01574   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD
01575   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOE
01576   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH
01577   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC
01578   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1
01579   * @retval uint32_t
01580 */
01581 __STATIC_INLINE uint32_t LL_C2_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
01582 {
01583   return ((READ_BIT(RCC->C2AHB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
01584 }
01585
01586 /**
01587   * @brief  Disable C2AHB2 peripherals clock.
01588   * @rmtoll C2AHB2ENR    GPIOAEN       LL_C2_AHB2_GRP1_DisableClock\n
01589   *         C2AHB2ENR    GPIOBEN       LL_C2_AHB2_GRP1_DisableClock\n
01590   *         C2AHB2ENR    GPIOCEN       LL_C2_AHB2_GRP1_DisableClock\n
01591   *         C2AHB2ENR    GPIODEN       LL_C2_AHB2_GRP1_DisableClock\n
01592   *         C2AHB2ENR    GPIOEEN       LL_C2_AHB2_GRP1_DisableClock\n
01593   *         C2AHB2ENR    GPIOHEN       LL_C2_AHB2_GRP1_DisableClock\n
01594   *         C2AHB2ENR    ADCEN         LL_C2_AHB2_GRP1_DisableClock\n
01595   *         C2AHB2ENR    AES1EN        LL_C2_AHB2_GRP1_DisableClock
01596   * @param  Periphs This parameter can be a combination of the following values:
01597   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA
01598   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB
01599   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC
01600   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD
01601   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOE
01602   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH
01603   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC
01604   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1
01605   * @retval None
01606 */
01607 __STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClock(uint32_t Periphs)
01608 {
01609   CLEAR_BIT(RCC->C2AHB2ENR, Periphs);
01610 }
01611
01612 /**
01613   * @brief  Enable C2AHB2 peripherals clock during Low Power (Sleep) mode.
01614   * @rmtoll C2AHB2SMENR  GPIOASMEN     LL_C2_AHB2_GRP1_EnableClockSleep\n
01615   *         C2AHB2SMENR  GPIOBSMEN     LL_C2_AHB2_GRP1_EnableClockSleep\n
01616   *         C2AHB2SMENR  GPIOCSMEN     LL_C2_AHB2_GRP1_EnableClockSleep\n
01617   *         C2AHB2SMENR  GPIODSMEN     LL_C2_AHB2_GRP1_EnableClockSleep\n
01618   *         C2AHB2SMENR  GPIOESMEN     LL_C2_AHB2_GRP1_EnableClockSleep\n
01619   *         C2AHB2SMENR  GPIOHSMEN     LL_C2_AHB2_GRP1_EnableClockSleep\n
01620   *         C2AHB2SMENR  ADCSMEN       LL_C2_AHB2_GRP1_EnableClockSleep\n
01621   *         C2AHB2SMENR  AES1SMEN      LL_C2_AHB2_GRP1_EnableClockSleep
01622   * @param  Periphs This parameter can be a combination of the following values:
01623   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA
01624   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB
01625   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC
01626   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD
01627   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOE
01628   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH
01629   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC
01630   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1
01631   * @retval None
01632 */
01633 __STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)
01634 {
01635   __IO uint32_t tmpreg;
01636   SET_BIT(RCC->C2AHB2SMENR, Periphs);
01637   /* Delay after an RCC peripheral clock enabling */
01638   tmpreg = READ_BIT(RCC->C2AHB2SMENR, Periphs);
01639   (void)tmpreg;
01640 }
01641
01642 /**
01643   * @brief  Disable C2AHB2 peripherals clock during Low Power (Sleep) mode.
01644   * @rmtoll C2AHB2SMENR  GPIOASMEN     LL_C2_AHB2_GRP1_DisableClockSleep\n
01645   *         C2AHB2SMENR  GPIOBSMEN     LL_C2_AHB2_GRP1_DisableClockSleep\n
01646   *         C2AHB2SMENR  GPIOCSMEN     LL_C2_AHB2_GRP1_DisableClockSleep\n
01647   *         C2AHB2SMENR  GPIODSMEN     LL_C2_AHB2_GRP1_DisableClockSleep\n
01648   *         C2AHB2SMENR  GPIOESMEN     LL_C2_AHB2_GRP1_DisableClockSleep\n
01649   *         C2AHB2SMENR  GPIOHSMEN     LL_C2_AHB2_GRP1_DisableClockSleep\n
01650   *         C2AHB2SMENR  ADCSMEN       LL_C2_AHB2_GRP1_DisableClockSleep\n
01651   *         C2AHB2SMENR  AES1SMEN      LL_C2_AHB2_GRP1_DisableClockSleep
01652   * @param  Periphs This parameter can be a combination of the following values:
01653   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA
01654   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB
01655   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC
01656   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD
01657   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOE
01658   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH
01659   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC
01660   *         @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1
01661   * @retval None
01662 */
01663 __STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)
01664 {
01665   CLEAR_BIT(RCC->C2AHB2SMENR, Periphs);
01666 }
01667
01668 /**
01669   * @}
01670   */
01671
01672 /** @defgroup BUS_LL_EF_C2_AHB3 C2 AHB3
01673   * @{
01674   */
01675
01676 /**
01677   * @brief  Enable C2AHB3 peripherals clock.
01678   * @rmtoll C2AHB3ENR    PKAEN         LL_C2_AHB3_GRP1_EnableClock\n
01679   *         C2AHB3ENR    AES2EN        LL_C2_AHB3_GRP1_EnableClock\n
01680   *         C2AHB3ENR    RNGEN         LL_C2_AHB3_GRP1_EnableClock\n
01681   *         C2AHB3ENR    HSEMEN        LL_C2_AHB3_GRP1_EnableClock\n
01682   *         C2AHB3ENR    IPCCEN        LL_C2_AHB3_GRP1_EnableClock\n
01683   *         C2AHB3ENR    FLASHEN       LL_C2_AHB3_GRP1_EnableClock
01684   * @param  Periphs This parameter can be a combination of the following values:
01685   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_PKA
01686   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_AES2
01687   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_RNG
01688   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_HSEM
01689   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_IPCC
01690   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH
01691   * @retval None
01692 */
01693 __STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClock(uint32_t Periphs)
01694 {
01695   __IO uint32_t tmpreg;
01696   SET_BIT(RCC->C2AHB3ENR, Periphs);
01697   /* Delay after an RCC peripheral clock enabling */
01698   tmpreg = READ_BIT(RCC->C2AHB3ENR, Periphs);
01699   (void)tmpreg;
01700 }
01701
01702 /**
01703   * @brief  Check if C2AHB3 peripheral clock is enabled or not
01704   * @rmtoll C2AHB3ENR    PKAEN         LL_C2_AHB3_GRP1_IsEnabledClock\n
01705   *         C2AHB3ENR    AES2EN        LL_C2_AHB3_GRP1_IsEnabledClock\n
01706   *         C2AHB3ENR    RNGEN         LL_C2_AHB3_GRP1_IsEnabledClock\n
01707   *         C2AHB3ENR    HSEMEN        LL_C2_AHB3_GRP1_IsEnabledClock\n
01708   *         C2AHB3ENR    IPCCEN        LL_C2_AHB3_GRP1_IsEnabledClock\n
01709   *         C2AHB3ENR    FLASHEN       LL_C2_AHB3_GRP1_IsEnabledClock
01710   * @param  Periphs This parameter can be a combination of the following values:
01711   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_PKA
01712   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_AES2
01713   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_RNG
01714   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_HSEM
01715   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_IPCC
01716   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH
01717   * @retval uint32_t
01718 */
01719 __STATIC_INLINE uint32_t LL_C2_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
01720 {
01721   return ((READ_BIT(RCC->C2AHB3ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
01722 }
01723
01724 /**
01725   * @brief  Disable C2AHB3 peripherals clock.
01726   * @rmtoll C2AHB3ENR    PKAEN         LL_C2_AHB3_GRP1_DisableClock\n
01727   *         C2AHB3ENR    AES2EN        LL_C2_AHB3_GRP1_DisableClock\n
01728   *         C2AHB3ENR    RNGEN         LL_C2_AHB3_GRP1_DisableClock\n
01729   *         C2AHB3ENR    HSEMEN        LL_C2_AHB3_GRP1_DisableClock\n
01730   *         C2AHB3ENR    IPCCEN        LL_C2_AHB3_GRP1_DisableClock\n
01731   *         C2AHB3ENR    FLASHEN       LL_C2_AHB3_GRP1_DisableClock
01732   * @param  Periphs This parameter can be a combination of the following values:
01733   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_PKA
01734   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_AES2
01735   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_RNG
01736   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_HSEM
01737   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_IPCC
01738   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH
01739   * @retval None
01740 */
01741 __STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClock(uint32_t Periphs)
01742 {
01743   CLEAR_BIT(RCC->C2AHB3ENR, Periphs);
01744 }
01745
01746 /**
01747   * @brief  Enable C2AHB3 peripherals clock during Low Power (Sleep) mode.
01748   * @rmtoll C2AHB3SMENR  PKASMEN       LL_C2_AHB3_GRP1_EnableClockSleep\n
01749   *         C2AHB3SMENR  AES2SMEN      LL_C2_AHB3_GRP1_EnableClockSleep\n
01750   *         C2AHB3SMENR  RNGSMEN       LL_C2_AHB3_GRP1_EnableClockSleep\n
01751   *         C2AHB3SMENR  SRAM2SMEN     LL_C2_AHB3_GRP1_EnableClockSleep\n
01752   *         C2AHB3SMENR  FLASHSMEN     LL_C2_AHB3_GRP1_EnableClockSleep
01753   * @param  Periphs This parameter can be a combination of the following values:
01754   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_PKA
01755   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_AES2
01756   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_RNG
01757   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_SRAM2
01758   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH
01759   * @retval None
01760 */
01761 __STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)
01762 {
01763   __IO uint32_t tmpreg;
01764   SET_BIT(RCC->C2AHB3SMENR, Periphs);
01765   /* Delay after an RCC peripheral clock enabling */
01766   tmpreg = READ_BIT(RCC->C2AHB3SMENR, Periphs);
01767   (void)tmpreg;
01768 }
01769
01770 /**
01771   * @brief  Disable C2AHB3 peripherals clock during Low Power (Sleep) mode.
01772   * @rmtoll C2AHB3SMENR  PKASMEN       LL_C2_AHB3_GRP1_DisableClockSleep\n
01773   *         C2AHB3SMENR  AES2SMEN      LL_C2_AHB3_GRP1_DisableClockSleep\n
01774   *         C2AHB3SMENR  RNGSMEN       LL_C2_AHB3_GRP1_DisableClockSleep\n
01775   *         C2AHB3SMENR  SRAM2SMEN     LL_C2_AHB3_GRP1_DisableClockSleep\n
01776   *         C2AHB3SMENR  FLASHSMEN     LL_C2_AHB3_GRP1_DisableClockSleep
01777   * @param  Periphs This parameter can be a combination of the following values:
01778   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_PKA
01779   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_AES2
01780   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_RNG
01781   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_SRAM2
01782   *         @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH
01783   * @retval None
01784 */
01785 __STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
01786 {
01787   CLEAR_BIT(RCC->C2AHB3SMENR, Periphs);
01788 }
01789
01790 /**
01791   * @}
01792   */
01793
01794 /** @defgroup BUS_LL_EF_C2_APB1 C2 APB1
01795   * @{
01796   */
01797
01798 /**
01799   * @brief  Enable C2APB1 peripherals clock.
01800   * @rmtoll C2APB1ENR1   TIM2EN        LL_C2_APB1_GRP1_EnableClock\n
01801   *         C2APB1ENR1   LCDEN         LL_C2_APB1_GRP1_EnableClock\n
01802   *         C2APB1ENR1   RTCAPBEN      LL_C2_APB1_GRP1_EnableClock\n
01803   *         C2APB1ENR1   SPI2EN        LL_C2_APB1_GRP1_EnableClock\n
01804   *         C2APB1ENR1   I2C1EN        LL_C2_APB1_GRP1_EnableClock\n
01805   *         C2APB1ENR1   I2C3EN        LL_C2_APB1_GRP1_EnableClock\n
01806   *         C2APB1ENR1   CRSEN         LL_C2_APB1_GRP1_EnableClock\n
01807   *         C2APB1ENR1   USBEN         LL_C2_APB1_GRP1_EnableClock\n
01808   *         C2APB1ENR1   LPTIM1EN      LL_C2_APB1_GRP1_EnableClock
01809   * @param  Periphs This parameter can be a combination of the following values:
01810   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2
01811   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD
01812   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB
01813   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2
01814   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1
01815   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3
01816   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS
01817   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_USB
01818   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1
01819   * @retval None
01820 */
01821 __STATIC_INLINE void LL_C2_APB1_GRP1_EnableClock(uint32_t Periphs)
01822 {
01823   __IO uint32_t tmpreg;
01824   SET_BIT(RCC->C2APB1ENR1, Periphs);
01825   /* Delay after an RCC peripheral clock enabling */
01826   tmpreg = READ_BIT(RCC->C2APB1ENR1, Periphs);
01827   (void)tmpreg;
01828 }
01829
01830 /**
01831   * @brief  Enable C2APB1 peripherals clock.
01832   * @rmtoll C2APB1ENR2   LPUART1EN     LL_C2_APB1_GRP2_EnableClock\n
01833   *         C2APB1ENR2   LPTIM2EN      LL_C2_APB1_GRP2_EnableClock
01834   * @param  Periphs This parameter can be a combination of the following values:
01835   *         @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1
01836   *         @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2
01837   * @retval None
01838 */
01839 __STATIC_INLINE void LL_C2_APB1_GRP2_EnableClock(uint32_t Periphs)
01840 {
01841   __IO uint32_t tmpreg;
01842   SET_BIT(RCC->C2APB1ENR2, Periphs);
01843   /* Delay after an RCC peripheral clock enabling */
01844   tmpreg = READ_BIT(RCC->C2APB1ENR2, Periphs);
01845   (void)tmpreg;
01846 }
01847
01848 /**
01849   * @brief  Check if C2APB1 peripheral clock is enabled or not
01850   * @rmtoll C2APB1ENR1   TIM2EN        LL_C2_APB1_GRP1_IsEnabledClock\n
01851   *         C2APB1ENR1   LCDEN         LL_C2_APB1_GRP1_IsEnabledClock\n
01852   *         C2APB1ENR1   RTCAPBEN      LL_C2_APB1_GRP1_IsEnabledClock\n
01853   *         C2APB1ENR1   SPI2EN        LL_C2_APB1_GRP1_IsEnabledClock\n
01854   *         C2APB1ENR1   I2C1EN        LL_C2_APB1_GRP1_IsEnabledClock\n
01855   *         C2APB1ENR1   I2C3EN        LL_C2_APB1_GRP1_IsEnabledClock\n
01856   *         C2APB1ENR1   CRSEN         LL_C2_APB1_GRP1_IsEnabledClock\n
01857   *         C2APB1ENR1   USBEN         LL_C2_APB1_GRP1_IsEnabledClock\n
01858   *         C2APB1ENR1   LPTIM1EN      LL_C2_APB1_GRP1_IsEnabledClock
01859   * @param  Periphs This parameter can be a combination of the following values:
01860   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2
01861   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD
01862   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB
01863   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2
01864   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1
01865   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3
01866   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS
01867   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_USB
01868   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1
01869   * @retval uint32_t
01870 */
01871 __STATIC_INLINE uint32_t LL_C2_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
01872 {
01873   return ((READ_BIT(RCC->C2APB1ENR1, Periphs) == (Periphs)) ? 1UL : 0UL);
01874 }
01875
01876 /**
01877   * @brief  Check if C2APB1 peripheral clock is enabled or not
01878   * @rmtoll C2APB1ENR2   LPUART1EN     LL_C2_APB1_GRP2_IsEnabledClock\n
01879   *         C2APB1ENR2   LPTIM2EN      LL_C2_APB1_GRP2_IsEnabledClock
01880   * @param  Periphs This parameter can be a combination of the following values:
01881   *         @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1
01882   *         @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2
01883   * @retval uint32_t
01884 */
01885 __STATIC_INLINE uint32_t LL_C2_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
01886 {
01887   return ((READ_BIT(RCC->C2APB1ENR2, Periphs) == (Periphs)) ? 1UL : 0UL);
01888 }
01889
01890 /**
01891   * @brief  Disable C2APB1 peripherals clock.
01892   * @rmtoll C2APB1ENR1   TIM2EN        LL_C2_APB1_GRP1_DisableClock\n
01893   *         C2APB1ENR1   LCDEN         LL_C2_APB1_GRP1_DisableClock\n
01894   *         C2APB1ENR1   RTCAPBEN      LL_C2_APB1_GRP1_DisableClock\n
01895   *         C2APB1ENR1   SPI2EN        LL_C2_APB1_GRP1_DisableClock\n
01896   *         C2APB1ENR1   I2C1EN        LL_C2_APB1_GRP1_DisableClock\n
01897   *         C2APB1ENR1   I2C3EN        LL_C2_APB1_GRP1_DisableClock\n
01898   *         C2APB1ENR1   CRSEN         LL_C2_APB1_GRP1_DisableClock\n
01899   *         C2APB1ENR1   USBEN         LL_C2_APB1_GRP1_DisableClock\n
01900   *         C2APB1ENR1   LPTIM1EN      LL_C2_APB1_GRP1_DisableClock
01901   * @param  Periphs This parameter can be a combination of the following values:
01902   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2
01903   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD
01904   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB
01905   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2
01906   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1
01907   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3
01908   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS
01909   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_USB
01910   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1
01911   * @retval None
01912 */
01913 __STATIC_INLINE void LL_C2_APB1_GRP1_DisableClock(uint32_t Periphs)
01914 {
01915   CLEAR_BIT(RCC->C2APB1ENR1, Periphs);
01916 }
01917
01918 /**
01919   * @brief  Disable C2APB1 peripherals clock.
01920   * @rmtoll C2APB1ENR2   LPUART1EN     LL_C2_APB1_GRP2_DisableClock\n
01921   *         C2APB1ENR2   LPTIM2EN      LL_C2_APB1_GRP2_DisableClock
01922   * @param  Periphs This parameter can be a combination of the following values:
01923   *         @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1
01924   *         @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2
01925   * @retval None
01926 */
01927 __STATIC_INLINE void LL_C2_APB1_GRP2_DisableClock(uint32_t Periphs)
01928 {
01929   CLEAR_BIT(RCC->C2APB1ENR2, Periphs);
01930 }
01931
01932 /**
01933   * @brief  Enable C2APB1 peripherals clock during Low Power (Sleep) mode.
01934   * @rmtoll C2APB1SMENR1 TIM2SMEN      LL_C2_APB1_GRP1_EnableClockSleep\n
01935   *         C2APB1SMENR1 LCDSMEN       LL_C2_APB1_GRP1_EnableClockSleep\n
01936   *         C2APB1SMENR1 RTCAPBSMEN    LL_C2_APB1_GRP1_EnableClockSleep\n
01937   *         C2APB1SMENR1 SPI2SMEN      LL_C2_APB1_GRP1_EnableClockSleep\n
01938   *         C2APB1SMENR1 I2C1SMEN      LL_C2_APB1_GRP1_EnableClockSleep\n
01939   *         C2APB1SMENR1 I2C3SMEN      LL_C2_APB1_GRP1_EnableClockSleep\n
01940   *         C2APB1SMENR1 CRSSMEN       LL_C2_APB1_GRP1_EnableClockSleep\n
01941   *         C2APB1SMENR1 USBSMEN       LL_C2_APB1_GRP1_EnableClockSleep\n
01942   *         C2APB1SMENR1 LPTIM1SMEN    LL_C2_APB1_GRP1_EnableClockSleep
01943   * @param  Periphs This parameter can be a combination of the following values:
01944   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2
01945   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD
01946   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB
01947   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2
01948   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1
01949   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3
01950   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS
01951   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_USB
01952   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1
01953   * @retval None
01954 */
01955 __STATIC_INLINE void LL_C2_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
01956 {
01957   __IO uint32_t tmpreg;
01958   SET_BIT(RCC->C2APB1SMENR1, Periphs);
01959   /* Delay after an RCC peripheral clock enabling */
01960   tmpreg = READ_BIT(RCC->C2APB1SMENR1, Periphs);
01961   (void)tmpreg;
01962 }
01963
01964 /**
01965   * @brief  Enable C2APB1 peripherals clock during Low Power (Sleep) mode.
01966   * @rmtoll C2APB1SMENR2 LPUART1SMEN   LL_C2_APB1_GRP2_EnableClockSleep\n
01967   *         C2APB1SMENR2 LPTIM2SMEN    LL_C2_APB1_GRP2_EnableClockSleep
01968   * @param  Periphs This parameter can be a combination of the following values:
01969   *         @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1
01970   *         @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2
01971   * @retval None
01972 */
01973 __STATIC_INLINE void LL_C2_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
01974 {
01975   __IO uint32_t tmpreg;
01976   SET_BIT(RCC->C2APB1SMENR2, Periphs);
01977   /* Delay after an RCC peripheral clock enabling */
01978   tmpreg = READ_BIT(RCC->C2APB1SMENR2, Periphs);
01979   (void)tmpreg;
01980 }
01981
01982 /**
01983   * @brief  Disable C2APB1 peripherals clock during Low Power (Sleep) mode.
01984   * @rmtoll C2APB1SMENR1 TIM2SMEN      LL_C2_APB1_GRP1_DisableClockSleep\n
01985   *         C2APB1SMENR1 LCDSMEN       LL_C2_APB1_GRP1_DisableClockSleep\n
01986   *         C2APB1SMENR1 RTCAPBSMEN    LL_C2_APB1_GRP1_DisableClockSleep\n
01987   *         C2APB1SMENR1 SPI2SMEN      LL_C2_APB1_GRP1_DisableClockSleep\n
01988   *         C2APB1SMENR1 I2C1SMEN      LL_C2_APB1_GRP1_DisableClockSleep\n
01989   *         C2APB1SMENR1 I2C3SMEN      LL_C2_APB1_GRP1_DisableClockSleep\n
01990   *         C2APB1SMENR1 CRSSMEN       LL_C2_APB1_GRP1_DisableClockSleep\n
01991   *         C2APB1SMENR1 USBSMEN       LL_C2_APB1_GRP1_DisableClockSleep\n
01992   *         C2APB1SMENR1 LPTIM1SMEN    LL_C2_APB1_GRP1_DisableClockSleep
01993   * @param  Periphs This parameter can be a combination of the following values:
01994   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2
01995   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD
01996   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB
01997   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2
01998   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1
01999   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3
02000   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS
02001   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_USB
02002   *         @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1
02003   * @retval None
02004 */
02005 __STATIC_INLINE void LL_C2_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
02006 {
02007   CLEAR_BIT(RCC->C2APB1SMENR1, Periphs);
02008 }
02009
02010 /**
02011   * @brief  Disable C2APB1 peripherals clock during Low Power (Sleep) mode.
02012   * @rmtoll C2APB1SMENR2 LPUART1SMEN   LL_C2_APB1_GRP2_DisableClockSleep\n
02013   *         C2APB1SMENR2 LPTIM2SMEN    LL_C2_APB1_GRP2_DisableClockSleep
02014   * @param  Periphs This parameter can be a combination of the following values:
02015   *         @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1
02016   *         @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2
02017   * @retval None
02018 */
02019 __STATIC_INLINE void LL_C2_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
02020 {
02021   CLEAR_BIT(RCC->C2APB1SMENR2, Periphs);
02022 }
02023
02024 /**
02025   * @}
02026   */
02027
02028 /** @defgroup BUS_LL_EF_C2_APB2 C2 APB2
02029   * @{
02030   */
02031
02032 /**
02033   * @brief  Enable C2APB2 peripherals clock.
02034   * @rmtoll C2APB2ENR    TIM1EN        LL_C2_APB2_GRP1_EnableClock\n
02035   *         C2APB2ENR    SPI1EN        LL_C2_APB2_GRP1_EnableClock\n
02036   *         C2APB2ENR    USART1EN      LL_C2_APB2_GRP1_EnableClock\n
02037   *         C2APB2ENR    TIM16EN       LL_C2_APB2_GRP1_EnableClock\n
02038   *         C2APB2ENR    TIM17EN       LL_C2_APB2_GRP1_EnableClock\n
02039   *         C2APB2ENR    SAI1EN        LL_C2_APB2_GRP1_EnableClock
02040   * @param  Periphs This parameter can be a combination of the following values:
02041   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1
02042   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1
02043   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1
02044   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16
02045   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17
02046   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1
02047   * @retval None
02048 */
02049 __STATIC_INLINE void LL_C2_APB2_GRP1_EnableClock(uint32_t Periphs)
02050 {
02051   __IO uint32_t tmpreg;
02052   SET_BIT(RCC->C2APB2ENR, Periphs);
02053   /* Delay after an RCC peripheral clock enabling */
02054   tmpreg = READ_BIT(RCC->C2APB2ENR, Periphs);
02055   (void)tmpreg;
02056 }
02057
02058 /**
02059   * @brief  Check if C2APB2 peripheral clock is enabled or not
02060   * @rmtoll C2APB2ENR    TIM1EN        LL_C2_APB2_GRP1_IsEnabledClock\n
02061   *         C2APB2ENR    SPI1EN        LL_C2_APB2_GRP1_IsEnabledClock\n
02062   *         C2APB2ENR    USART1EN      LL_C2_APB2_GRP1_IsEnabledClock\n
02063   *         C2APB2ENR    TIM16EN       LL_C2_APB2_GRP1_IsEnabledClock\n
02064   *         C2APB2ENR    TIM17EN       LL_C2_APB2_GRP1_IsEnabledClock\n
02065   *         C2APB2ENR    SAI1EN        LL_C2_APB2_GRP1_IsEnabledClock
02066   * @param  Periphs This parameter can be a combination of the following values:
02067   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1
02068   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1
02069   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1
02070   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16
02071   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17
02072   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1
02073   * @retval uint32_t
02074 */
02075 __STATIC_INLINE uint32_t LL_C2_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
02076 {
02077   return ((READ_BIT(RCC->C2APB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
02078 }
02079
02080 /**
02081   * @brief  Disable C2APB2 peripherals clock.
02082   * @rmtoll C2APB2ENR    TIM1EN        LL_C2_APB2_GRP1_DisableClock\n
02083   *         C2APB2ENR    SPI1EN        LL_C2_APB2_GRP1_DisableClock\n
02084   *         C2APB2ENR    USART1EN      LL_C2_APB2_GRP1_DisableClock\n
02085   *         C2APB2ENR    TIM16EN       LL_C2_APB2_GRP1_DisableClock\n
02086   *         C2APB2ENR    TIM17EN       LL_C2_APB2_GRP1_DisableClock\n
02087   *         C2APB2ENR    SAI1EN        LL_C2_APB2_GRP1_DisableClock
02088   * @param  Periphs This parameter can be a combination of the following values:
02089   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1
02090   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1
02091   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1
02092   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16
02093   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17
02094   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1
02095   * @retval None
02096 */
02097 __STATIC_INLINE void LL_C2_APB2_GRP1_DisableClock(uint32_t Periphs)
02098 {
02099   CLEAR_BIT(RCC->C2APB2ENR, Periphs);
02100 }
02101
02102 /**
02103   * @brief  Enable C2APB2 peripherals clock during Low Power (Sleep) mode.
02104   * @rmtoll C2APB2SMENR  TIM1SMEN      LL_C2_APB2_GRP1_EnableClockSleep\n
02105   *         C2APB2SMENR  SPI1SMEN      LL_C2_APB2_GRP1_EnableClockSleep\n
02106   *         C2APB2SMENR  USART1SMEN    LL_C2_APB2_GRP1_EnableClockSleep\n
02107   *         C2APB2SMENR  TIM16SMEN     LL_C2_APB2_GRP1_EnableClockSleep\n
02108   *         C2APB2SMENR  TIM17SMEN     LL_C2_APB2_GRP1_EnableClockSleep\n
02109   *         C2APB2SMENR  SAI1SMEN      LL_C2_APB2_GRP1_EnableClockSleep
02110   * @param  Periphs This parameter can be a combination of the following values:
02111   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1
02112   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1
02113   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1
02114   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16
02115   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17
02116   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1
02117   * @retval None
02118 */
02119 __STATIC_INLINE void LL_C2_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
02120 {
02121   __IO uint32_t tmpreg;
02122   SET_BIT(RCC->C2APB2SMENR, Periphs);
02123   /* Delay after an RCC peripheral clock enabling */
02124   tmpreg = READ_BIT(RCC->C2APB2SMENR, Periphs);
02125   (void)tmpreg;
02126 }
02127
02128 /**
02129   * @brief  Disable C2APB2 peripherals clock during Low Power (Sleep) mode.
02130   * @rmtoll C2APB2SMENR  TIM1SMEN      LL_C2_APB2_GRP1_DisableClockSleep\n
02131   *         C2APB2SMENR  SPI1SMEN      LL_C2_APB2_GRP1_DisableClockSleep\n
02132   *         C2APB2SMENR  USART1SMEN    LL_C2_APB2_GRP1_DisableClockSleep\n
02133   *         C2APB2SMENR  TIM16SMEN     LL_C2_APB2_GRP1_DisableClockSleep\n
02134   *         C2APB2SMENR  TIM17SMEN     LL_C2_APB2_GRP1_DisableClockSleep\n
02135   *         C2APB2SMENR  SAI1SMEN      LL_C2_APB2_GRP1_DisableClockSleep
02136   * @param  Periphs This parameter can be a combination of the following values:
02137   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1
02138   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1
02139   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1
02140   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16
02141   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17
02142   *         @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1
02143   * @retval None
02144 */
02145 __STATIC_INLINE void LL_C2_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
02146 {
02147   CLEAR_BIT(RCC->C2APB2SMENR, Periphs);
02148 }
02149
02150 /**
02151   * @}
02152   */
02153
02154 /** @defgroup BUS_LL_EF_C2_APB3 C2 APB3
02155   * @{
02156   */
02157
02158 /**
02159   * @brief  Enable C2APB3 peripherals clock.
02160   * @rmtoll C2APB3ENR    BLEEN         LL_C2_APB3_GRP1_EnableClock\n
02161   *         C2APB3ENR    802EN         LL_C2_APB3_GRP1_EnableClock
02162   * @param  Periphs This parameter can be a combination of the following values:
02163   *         @arg @ref LL_C2_APB3_GRP1_PERIPH_BLE
02164   *         @arg @ref LL_C2_APB3_GRP1_PERIPH_802
02165   * @retval None
02166 */
02167 __STATIC_INLINE void LL_C2_APB3_GRP1_EnableClock(uint32_t Periphs)
02168 {
02169   __IO uint32_t tmpreg;
02170   SET_BIT(RCC->C2APB3ENR, Periphs);
02171   /* Delay after an RCC peripheral clock enabling */
02172   tmpreg = READ_BIT(RCC->C2APB3ENR, Periphs);
02173   (void)tmpreg;
02174 }
02175
02176 /**
02177   * @brief  Check if C2APB3 peripheral clock is enabled or not
02178   * @rmtoll C2APB3ENR    BLEEN         LL_C2_APB3_GRP1_IsEnabledClock\n
02179   *         C2APB3ENR    802EN         LL_C2_APB3_GRP1_IsEnabledClock
02180   * @param  Periphs This parameter can be a combination of the following values:
02181   *         @arg @ref LL_C2_APB3_GRP1_PERIPH_BLE
02182   *         @arg @ref LL_C2_APB3_GRP1_PERIPH_802
02183   * @retval uint32_t
02184 */
02185 __STATIC_INLINE uint32_t LL_C2_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
02186 {
02187   return ((READ_BIT(RCC->C2APB3ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
02188 }
02189
02190 /**
02191   * @brief  Disable C2APB3 peripherals clock.
02192   * @rmtoll C2APB3ENR    BLEEN         LL_C2_APB3_GRP1_DisableClock\n
02193   *         C2APB3ENR    802EN         LL_C2_APB3_GRP1_DisableClock
02194   * @param  Periphs This parameter can be a combination of the following values:
02195   *         @arg @ref LL_C2_APB3_GRP1_PERIPH_BLE
02196   *         @arg @ref LL_C2_APB3_GRP1_PERIPH_802
02197   * @retval None
02198 */
02199 __STATIC_INLINE void LL_C2_APB3_GRP1_DisableClock(uint32_t Periphs)
02200 {
02201   CLEAR_BIT(RCC->C2APB3ENR, Periphs);
02202 }
02203
02204 /**
02205   * @brief  Enable C2APB3 peripherals clock during Low Power (Sleep) mode.
02206   * @rmtoll C2APB3SMENR  BLESMEN       LL_C2_APB3_GRP1_EnableClockSleep\n
02207   *         C2APB3SMENR  802SMEN       LL_C2_APB3_GRP1_EnableClockSleep
02208   * @param  Periphs This parameter can be a combination of the following values:
02209   *         @arg @ref LL_C2_APB3_GRP1_PERIPH_BLE
02210   *         @arg @ref LL_C2_APB3_GRP1_PERIPH_802
02211   * @retval None
02212 */
02213 __STATIC_INLINE void LL_C2_APB3_GRP1_EnableClockSleep(uint32_t Periphs)
02214 {
02215   __IO uint32_t tmpreg;
02216   SET_BIT(RCC->C2APB3SMENR, Periphs);
02217   /* Delay after an RCC peripheral clock enabling */
02218   tmpreg = READ_BIT(RCC->C2APB3SMENR, Periphs);
02219   (void)tmpreg;
02220 }
02221
02222 /**
02223   * @brief  Disable C2APB3 peripherals clock during Low Power (Sleep) mode.
02224   * @rmtoll C2APB3SMENR  BLESMEN       LL_C2_APB3_GRP1_DisableClockSleep\n
02225   *         C2APB3SMENR  802SMEN       LL_C2_APB3_GRP1_DisableClockSleep
02226   * @param  Periphs This parameter can be a combination of the following values:
02227   *         @arg @ref LL_C2_APB3_GRP1_PERIPH_BLE
02228   *         @arg @ref LL_C2_APB3_GRP1_PERIPH_802
02229   * @retval None
02230 */
02231 __STATIC_INLINE void LL_C2_APB3_GRP1_DisableClockSleep(uint32_t Periphs)
02232 {
02233   CLEAR_BIT(RCC->C2APB3SMENR, Periphs);
02234 }
02235
02236 /**
02237   * @}
02238   */
02239
02240 /**
02241   * @}
02242   */
02243
02244 /**
02245   * @}
02246   */
02247
02248 #endif /* defined(RCC) */
02249
02250 /**
02251   * @}
02252   */
02253
02254 #ifdef __cplusplus
02255 }
02256 #endif
02257
02258 #endif /* STM32WBxx_LL_BUS_H */
02259
02260 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_comp.c Source File

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stm32wbxx_ll_comp.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_comp.c
00004   * @author  MCD Application Team
00005   * @brief   COMP LL module driver
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32wbxx_ll_comp.h"
00023
00024 #ifdef  USE_FULL_ASSERT
00025 #include "stm32_assert.h"
00026 #else
00027 #define assert_param(expr) ((void)0U)
00028 #endif
00029
00030 /** @addtogroup STM32WBxx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (COMP1) || defined (COMP2)
00035
00036 /** @addtogroup COMP_LL COMP
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /* Private macros ------------------------------------------------------------*/
00044
00045 /** @addtogroup COMP_LL_Private_Macros
00046   * @{
00047   */
00048
00049 /* Check of parameters for configuration of COMP hierarchical scope:          */
00050 /* COMP instance.                                                             */
00051
00052 #define IS_LL_COMP_POWER_MODE(__POWER_MODE__)                                  \
00053   (   ((__POWER_MODE__) == LL_COMP_POWERMODE_HIGHSPEED)                        \
00054    || ((__POWER_MODE__) == LL_COMP_POWERMODE_MEDIUMSPEED)                      \
00055    || ((__POWER_MODE__) == LL_COMP_POWERMODE_ULTRALOWPOWER)                    \
00056   )
00057
00058 /* Note: On this STM32 serie, comparator input plus parameters are            */
00059 /*       the same on all COMP instances.                                      */
00060 /*       However, comparator instance kept as macro parameter for             */
00061 /*       compatibility with other STM32 families.                             */
00062 #define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)               \
00063   (   ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1)                             \
00064    || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2)                             \
00065    || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO3)                             \
00066   )
00067
00068 /* Note: On this STM32 serie, comparator input minus parameters are           */
00069 /*       the same on all COMP instances.                                      */
00070 /*       However, comparator instance kept as macro parameter for             */
00071 /*       compatibility with other STM32 families.                             */
00072 #define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)             \
00073   (   ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT)                    \
00074    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT)                    \
00075    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT)                    \
00076    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT)                       \
00077    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1)                           \
00078    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2)                           \
00079    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO3)                           \
00080    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO4)                           \
00081    || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO5)                           \
00082   )
00083
00084 #define IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__)                      \
00085   (   ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_NONE)                      \
00086    || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_LOW)                       \
00087    || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_MEDIUM)                    \
00088    || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_HIGH)                      \
00089   )
00090
00091 #define IS_LL_COMP_OUTPUT_POLARITY(__POLARITY__)                               \
00092   (   ((__POLARITY__) == LL_COMP_OUTPUTPOL_NONINVERTED)                        \
00093    || ((__POLARITY__) == LL_COMP_OUTPUTPOL_INVERTED)                           \
00094   )
00095
00096 #define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__OUTPUT_BLANKING_SOURCE__)          \
00097   (   ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE)               \
00098    || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5)           \
00099    || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3)           \
00100   )
00101
00102 /**
00103   * @}
00104   */
00105
00106
00107 /* Private function prototypes -----------------------------------------------*/
00108
00109 /* Exported functions --------------------------------------------------------*/
00110 /** @addtogroup COMP_LL_Exported_Functions
00111   * @{
00112   */
00113
00114 /** @addtogroup COMP_LL_EF_Init
00115   * @{
00116   */
00117
00118 /**
00119   * @brief  De-initialize registers of the selected COMP instance
00120   *         to their default reset values.
00121   * @note   If comparator is locked, de-initialization by software is
00122   *         not possible.
00123   *         The only way to unlock the comparator is a device hardware reset.
00124   * @param  COMPx COMP instance
00125   * @retval An ErrorStatus enumeration value:
00126   *          - SUCCESS: COMP registers are de-initialized
00127   *          - ERROR: COMP registers are not de-initialized
00128   */
00129 ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx)
00130 {
00131   ErrorStatus status = SUCCESS;
00132
00133   /* Check the parameters */
00134   assert_param(IS_COMP_ALL_INSTANCE(COMPx));
00135
00136   /* Note: Hardware constraint (refer to description of this function):       */
00137   /*       COMP instance must not be locked.                                  */
00138   if (LL_COMP_IsLocked(COMPx) == 0UL)
00139   {
00140     LL_COMP_WriteReg(COMPx, CSR, 0x00000000UL);
00141
00142   }
00143   else
00144   {
00145     /* Comparator instance is locked: de-initialization by software is         */
00146     /* not possible.                                                           */
00147     /* The only way to unlock the comparator is a device hardware reset.       */
00148     status = ERROR;
00149   }
00150
00151   return status;
00152 }
00153
00154 /**
00155   * @brief  Initialize some features of COMP instance.
00156   * @note   This function configures features of the selected COMP instance.
00157   *         Some features are also available at scope COMP common instance
00158   *         (common to several COMP instances).
00159   *         Refer to functions having argument "COMPxy_COMMON" as parameter.
00160   * @param  COMPx COMP instance
00161   * @param  COMP_InitStruct Pointer to a @ref LL_COMP_InitTypeDef structure
00162   * @retval An ErrorStatus enumeration value:
00163   *          - SUCCESS: COMP registers are initialized
00164   *          - ERROR: COMP registers are not initialized
00165   */
00166 ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct)
00167 {
00168   ErrorStatus status = SUCCESS;
00169
00170   /* Check the parameters */
00171   assert_param(IS_COMP_ALL_INSTANCE(COMPx));
00172   assert_param(IS_LL_COMP_POWER_MODE(COMP_InitStruct->PowerMode));
00173   assert_param(IS_LL_COMP_INPUT_PLUS(COMPx, COMP_InitStruct->InputPlus));
00174   assert_param(IS_LL_COMP_INPUT_MINUS(COMPx, COMP_InitStruct->InputMinus));
00175   assert_param(IS_LL_COMP_INPUT_HYSTERESIS(COMP_InitStruct->InputHysteresis));
00176   assert_param(IS_LL_COMP_OUTPUT_POLARITY(COMP_InitStruct->OutputPolarity));
00177   assert_param(IS_LL_COMP_OUTPUT_BLANKING_SOURCE(COMP_InitStruct->OutputBlankingSource));
00178
00179   /* Note: Hardware constraint (refer to description of this function)        */
00180   /*       COMP instance must not be locked.                                  */
00181   if (LL_COMP_IsLocked(COMPx) == 0UL)
00182   {
00183     /* Configuration of comparator instance :                                 */
00184     /*  - PowerMode                                                           */
00185     /*  - InputPlus                                                           */
00186     /*  - InputMinus                                                          */
00187     /*  - InputHysteresis                                                     */
00188     /*  - OutputPolarity                                                      */
00189     /*  - OutputBlankingSource                                                */
00190     MODIFY_REG(COMPx->CSR,
00191                COMP_CSR_PWRMODE
00192                | COMP_CSR_INPSEL
00193                | COMP_CSR_SCALEN
00194                | COMP_CSR_BRGEN
00195                | COMP_CSR_INMESEL
00196                | COMP_CSR_INMSEL
00197                | COMP_CSR_HYST
00198                | COMP_CSR_POLARITY
00199                | COMP_CSR_BLANKING
00200                ,
00201                COMP_InitStruct->PowerMode
00202                | COMP_InitStruct->InputPlus
00203                | COMP_InitStruct->InputMinus
00204                | COMP_InitStruct->InputHysteresis
00205                | COMP_InitStruct->OutputPolarity
00206                | COMP_InitStruct->OutputBlankingSource
00207               );
00208
00209   }
00210   else
00211   {
00212     /* Initialization error: COMP instance is locked.                         */
00213     status = ERROR;
00214   }
00215
00216   return status;
00217 }
00218
00219 /**
00220   * @brief Set each @ref LL_COMP_InitTypeDef field to default value.
00221   * @param COMP_InitStruct Pointer to a @ref LL_COMP_InitTypeDef structure
00222   *                        whose fields will be set to default values.
00223   * @retval None
00224   */
00225 void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct)
00226 {
00227   /* Set COMP_InitStruct fields to default values */
00228   COMP_InitStruct->PowerMode            = LL_COMP_POWERMODE_ULTRALOWPOWER;
00229   COMP_InitStruct->InputPlus            = LL_COMP_INPUT_PLUS_IO1;
00230   COMP_InitStruct->InputMinus           = LL_COMP_INPUT_MINUS_VREFINT;
00231   COMP_InitStruct->InputHysteresis      = LL_COMP_HYSTERESIS_NONE;
00232   COMP_InitStruct->OutputPolarity       = LL_COMP_OUTPUTPOL_NONINVERTED;
00233   COMP_InitStruct->OutputBlankingSource = LL_COMP_BLANKINGSRC_NONE;
00234 }
00235
00236 /**
00237   * @}
00238   */
00239
00240 /**
00241   * @}
00242   */
00243
00244 /**
00245   * @}
00246   */
00247
00248 #endif /* COMP1 || COMP2 */
00249
00250 /**
00251   * @}
00252   */
00253
00254 #endif /* USE_FULL_LL_DRIVER */
00255
00256 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_comp.h Source File

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stm32wbxx_ll_comp.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_comp.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of COMP LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_LL_COMP_H
00022 #define STM32WBxx_LL_COMP_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx.h"
00030
00031 /** @addtogroup STM32WBxx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (COMP1) || defined (COMP2)
00036
00037 /** @defgroup COMP_LL COMP
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /** @defgroup COMP_LL_Private_Constants COMP Private Constants
00045   * @{
00046   */
00047
00048 /* COMP registers bits positions */
00049 #define LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS (30UL) /* Value equivalent to POSITION_VAL(COMP_CSR_VALUE) */
00050
00051 /**
00052   * @}
00053   */
00054
00055 /* Private macros ------------------------------------------------------------*/
00056 /* Exported types ------------------------------------------------------------*/
00057 #if defined(USE_FULL_LL_DRIVER)
00058 /** @defgroup COMP_LL_ES_INIT COMP Exported Init structure
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  Structure definition of some features of COMP instance.
00064   */
00065 typedef struct
00066 {
00067   uint32_t PowerMode;                   /*!< Set comparator operating mode to adjust power and speed.
00068                                              This parameter can be a value of @ref COMP_LL_EC_POWERMODE
00069
00070                                              This feature can be modified afterwards using unitary function @ref LL_COMP_SetPowerMode(). */
00071
00072   uint32_t InputPlus;                   /*!< Set comparator input plus (non-inverting input).
00073                                              This parameter can be a value of @ref COMP_LL_EC_INPUT_PLUS
00074
00075                                              This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputPlus(). */
00076
00077   uint32_t InputMinus;                  /*!< Set comparator input minus (inverting input).
00078                                              This parameter can be a value of @ref COMP_LL_EC_INPUT_MINUS
00079
00080                                              This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputMinus(). */
00081
00082   uint32_t InputHysteresis;             /*!< Set comparator hysteresis mode of the input minus.
00083                                              This parameter can be a value of @ref COMP_LL_EC_INPUT_HYSTERESIS
00084
00085                                              This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputHysteresis(). */
00086
00087   uint32_t OutputPolarity;              /*!< Set comparator output polarity.
00088                                              This parameter can be a value of @ref COMP_LL_EC_OUTPUT_POLARITY
00089
00090                                              This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputPolarity(). */
00091
00092   uint32_t OutputBlankingSource;        /*!< Set comparator blanking source.
00093                                              This parameter can be a value of @ref COMP_LL_EC_OUTPUT_BLANKING_SOURCE
00094
00095                                              This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputBlankingSource(). */
00096
00097 } LL_COMP_InitTypeDef;
00098
00099 /**
00100   * @}
00101   */
00102 #endif /* USE_FULL_LL_DRIVER */
00103
00104 /* Exported constants --------------------------------------------------------*/
00105 /** @defgroup COMP_LL_Exported_Constants COMP Exported Constants
00106   * @{
00107   */
00108
00109 /** @defgroup COMP_LL_EC_COMMON_WINDOWMODE Comparator common modes - Window mode
00110   * @{
00111   */
00112 #define LL_COMP_WINDOWMODE_DISABLE                 (0x00000000UL)          /*!< Window mode disable: Comparators 1 and 2 are independent */
00113 #define LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE)      /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */
00114 /**
00115   * @}
00116   */
00117
00118 /** @defgroup COMP_LL_EC_POWERMODE Comparator modes - Power mode
00119   * @{
00120   */
00121 #define LL_COMP_POWERMODE_HIGHSPEED     (0x00000000UL)                            /*!< COMP power mode to high speed */
00122 #define LL_COMP_POWERMODE_MEDIUMSPEED   (COMP_CSR_PWRMODE_0)                      /*!< COMP power mode to medium speed */
00123 #define LL_COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_PWRMODE_1 | COMP_CSR_PWRMODE_0) /*!< COMP power mode to ultra-low power */
00124 /**
00125   * @}
00126   */
00127
00128 /** @defgroup COMP_LL_EC_INPUT_PLUS Comparator inputs - Input plus (input non-inverting) selection
00129   * @{
00130   */
00131 #define LL_COMP_INPUT_PLUS_IO1          (0x00000000UL)                          /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2) */
00132 #define LL_COMP_INPUT_PLUS_IO2          (COMP_CSR_INPSEL_0)                     /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2) */
00133 #define LL_COMP_INPUT_PLUS_IO3          (COMP_CSR_INPSEL_1)                     /*!< Comparator input plus connected to IO3 (pin PA1 for COMP1, pin PA3 for COMP2) */
00134 /**
00135   * @}
00136   */
00137
00138 /** @defgroup COMP_LL_EC_INPUT_MINUS Comparator inputs - Input minus (input inverting) selection
00139   * @{
00140   */
00141 #define LL_COMP_INPUT_MINUS_1_4VREFINT  (                                                            COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 1/4 VrefInt  */
00142 #define LL_COMP_INPUT_MINUS_1_2VREFINT  (                                        COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 1/2 VrefInt  */
00143 #define LL_COMP_INPUT_MINUS_3_4VREFINT  (                    COMP_CSR_INMSEL_1                     | COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 3/4 VrefInt  */
00144 #define LL_COMP_INPUT_MINUS_VREFINT     (                    COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN                 )        /*!< Comparator input minus connected to VrefInt */
00145 #define LL_COMP_INPUT_MINUS_IO1         (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1                    )                                           /*!< Comparator input minus connected to IO1 (pin PA9 for COMP1, pin PB3 for COMP2) */
00146 #define LL_COMP_INPUT_MINUS_IO2         (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)                                           /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PB7 for COMP2) */
00147 #define LL_COMP_INPUT_MINUS_IO3         (                     COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO3 (pin PA0 for COMP1, pin PA2 for COMP2) */
00148 #define LL_COMP_INPUT_MINUS_IO4         (COMP_CSR_INMESEL_1                      | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO4 (pin PA4 for COMP1, pin PA4 for COMP2) */
00149 #define LL_COMP_INPUT_MINUS_IO5         (COMP_CSR_INMESEL_1 | COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO5 (pin PA5 for COMP1, pin PA5 for COMP2) */
00150 /**
00151   * @}
00152   */
00153
00154 /** @defgroup COMP_LL_EC_INPUT_HYSTERESIS Comparator input - Hysteresis
00155   * @{
00156   */
00157 #define LL_COMP_HYSTERESIS_NONE         (0x00000000UL)                      /*!< No hysteresis */
00158 #define LL_COMP_HYSTERESIS_LOW          (                  COMP_CSR_HYST_0) /*!< Hysteresis level low */
00159 #define LL_COMP_HYSTERESIS_MEDIUM       (COMP_CSR_HYST_1                  ) /*!< Hysteresis level medium */
00160 #define LL_COMP_HYSTERESIS_HIGH         (COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level high */
00161 /**
00162   * @}
00163   */
00164
00165 /** @defgroup COMP_LL_EC_OUTPUT_POLARITY Comparator output - Output polarity
00166   * @{
00167   */
00168 #define LL_COMP_OUTPUTPOL_NONINVERTED   (0x00000000UL)          /*!< COMP output polarity is not inverted: comparator output is high when the plus (non-inverting) input is at a higher voltage than the minus (inverting) input */
00169 #define LL_COMP_OUTPUTPOL_INVERTED      (COMP_CSR_POLARITY)     /*!< COMP output polarity is inverted: comparator output is low when the plus (non-inverting) input is at a lower voltage than the minus (inverting) input */
00170 /**
00171   * @}
00172   */
00173
00174 /** @defgroup COMP_LL_EC_OUTPUT_BLANKING_SOURCE Comparator output - Blanking source
00175   * @{
00176   */
00177 #define LL_COMP_BLANKINGSRC_NONE            (0x00000000UL)          /*!<Comparator output without blanking */
00178 /* Note: Output blanking source common to all COMP instances */
00179 #define LL_COMP_BLANKINGSRC_TIM1_OC5        (COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM1 OC5 (common to all COMP instances: COMP1, COMP2) */
00180 #define LL_COMP_BLANKINGSRC_TIM2_OC3        (COMP_CSR_BLANKING_1)   /*!< Comparator output blanking source TIM2 OC3 (common to all COMP instances: COMP1, COMP2) */
00181 /**
00182   * @}
00183   */
00184
00185 /** @defgroup COMP_LL_EC_OUTPUT_LEVEL Comparator output - Output level
00186   * @{
00187   */
00188 #define LL_COMP_OUTPUT_LEVEL_LOW        (0x00000000UL)          /*!< Comparator output level low (if the polarity is not inverted, otherwise to be complemented) */
00189 #define LL_COMP_OUTPUT_LEVEL_HIGH       (0x00000001UL)          /*!< Comparator output level high (if the polarity is not inverted, otherwise to be complemented) */
00190 /**
00191   * @}
00192   */
00193
00194 /** @defgroup COMP_LL_EC_HW_DELAYS  Definitions of COMP hardware constraints delays
00195   * @note   Only COMP peripheral HW delays are defined in COMP LL driver driver,
00196   *         not timeout values.
00197   *         For details on delays values, refer to descriptions in source code
00198   *         above each literal definition.
00199   * @{
00200   */
00201
00202 /* Delay for comparator startup time.                                         */
00203 /* Note: Delay required to reach propagation delay specification.             */
00204 /* Literal set to maximum value (refer to device datasheet,                   */
00205 /* parameter "tSTART").                                                       */
00206 /* Unit: us                                                                   */
00207 #define LL_COMP_DELAY_STARTUP_US          ( 80UL) /*!< Delay for COMP startup time */
00208
00209 /* Delay for comparator voltage scaler stabilization time.                    */
00210 /* Note: Voltage scaler is used when selecting comparator input               */
00211 /*       based on VrefInt: VrefInt or subdivision of VrefInt.                 */
00212 /* Literal set to maximum value (refer to device datasheet,                   */
00213 /* parameter "tSTART_SCALER").                                                */
00214 /* Unit: us                                                                   */
00215 #define LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US ( 200UL) /*!< Delay for COMP voltage scaler stabilization time */
00216
00217 /**
00218   * @}
00219   */
00220
00221 /**
00222   * @}
00223   */
00224
00225 /* Exported macro ------------------------------------------------------------*/
00226 /** @defgroup COMP_LL_Exported_Macros COMP Exported Macros
00227   * @{
00228   */
00229 /** @defgroup COMP_LL_EM_WRITE_READ Common write and read registers macro
00230   * @{
00231   */
00232
00233 /**
00234   * @brief  Write a value in COMP register
00235   * @param  __INSTANCE__ comparator instance
00236   * @param  __REG__ Register to be written
00237   * @param  __VALUE__ Value to be written in the register
00238   * @retval None
00239   */
00240 #define LL_COMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
00241
00242 /**
00243   * @brief  Read a value in COMP register
00244   * @param  __INSTANCE__ comparator instance
00245   * @param  __REG__ Register to be read
00246   * @retval Register value
00247   */
00248 #define LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
00249 /**
00250   * @}
00251   */
00252
00253 /** @defgroup COMP_LL_EM_HELPER_MACRO COMP helper macro
00254   * @{
00255   */
00256
00257 /**
00258   * @brief  Helper macro to select the COMP common instance
00259   *         to which is belonging the selected COMP instance.
00260   * @note   COMP common register instance can be used to
00261   *         set parameters common to several COMP instances.
00262   *         Refer to functions having argument "COMPxy_COMMON" as parameter.
00263   * @param  __COMPx__ COMP instance
00264   * @retval COMP common instance or value "0" if there is no COMP common instance.
00265   */
00266 #define __LL_COMP_COMMON_INSTANCE(__COMPx__)                                   \
00267   (COMP12_COMMON)
00268
00269 /**
00270   * @}
00271   */
00272
00273 /**
00274   * @}
00275   */
00276
00277 /* Exported functions --------------------------------------------------------*/
00278 /** @defgroup COMP_LL_Exported_Functions COMP Exported Functions
00279   * @{
00280   */
00281
00282 /** @defgroup COMP_LL_EF_Configuration_comparator_common Configuration of COMP hierarchical scope: common to several COMP instances
00283   * @{
00284   */
00285
00286 /**
00287   * @brief  Set window mode of a pair of comparators instances
00288   *         (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
00289   * @rmtoll CSR      WINMODE        LL_COMP_SetCommonWindowMode
00290   * @param  COMPxy_COMMON Comparator common instance
00291   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
00292   * @param  WindowMode This parameter can be one of the following values:
00293   *         @arg @ref LL_COMP_WINDOWMODE_DISABLE
00294   *         @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
00295   * @retval None
00296   */
00297 __STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode)
00298 {
00299   /* Note: On this STM32 serie, window mode can be set only                   */
00300   /*       from COMP instance: COMP2.                                         */
00301   MODIFY_REG(COMPxy_COMMON->CSR, COMP_CSR_WINMODE, WindowMode);
00302 }
00303
00304 /**
00305   * @brief  Get window mode of a pair of comparators instances
00306   *         (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
00307   * @rmtoll CSR      WINMODE        LL_COMP_GetCommonWindowMode
00308   * @param  COMPxy_COMMON Comparator common instance
00309   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
00310   * @retval Returned value can be one of the following values:
00311   *         @arg @ref LL_COMP_WINDOWMODE_DISABLE
00312   *         @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
00313   */
00314 __STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON)
00315 {
00316   return (uint32_t)(READ_BIT(COMPxy_COMMON->CSR, COMP_CSR_WINMODE));
00317 }
00318
00319 /**
00320   * @}
00321   */
00322
00323 /** @defgroup COMP_LL_EF_Configuration_comparator_modes Configuration of comparator modes
00324   * @{
00325   */
00326
00327 /**
00328   * @brief  Set comparator instance operating mode to adjust power and speed.
00329   * @rmtoll CSR      PWRMODE        LL_COMP_SetPowerMode
00330   * @param  COMPx Comparator instance
00331   * @param  PowerMode This parameter can be one of the following values:
00332   *         @arg @ref LL_COMP_POWERMODE_HIGHSPEED
00333   *         @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED
00334   *         @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER
00335   * @retval None
00336   */
00337 __STATIC_INLINE void LL_COMP_SetPowerMode(COMP_TypeDef *COMPx, uint32_t PowerMode)
00338 {
00339   MODIFY_REG(COMPx->CSR, COMP_CSR_PWRMODE, PowerMode);
00340 }
00341
00342 /**
00343   * @brief  Get comparator instance operating mode to adjust power and speed.
00344   * @rmtoll CSR      PWRMODE        LL_COMP_GetPowerMode
00345   * @param  COMPx Comparator instance
00346   * @retval Returned value can be one of the following values:
00347   *         @arg @ref LL_COMP_POWERMODE_HIGHSPEED
00348   *         @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED
00349   *         @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER
00350   */
00351 __STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx)
00352 {
00353   return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_PWRMODE));
00354 }
00355
00356 /**
00357   * @}
00358   */
00359
00360 /** @defgroup COMP_LL_EF_Configuration_comparator_inputs Configuration of comparator inputs
00361   * @{
00362   */
00363
00364 /**
00365   * @brief  Set comparator inputs minus (inverting) and plus (non-inverting).
00366   * @note   In case of comparator input selected to be connected to IO:
00367   *         GPIO pins are specific to each comparator instance.
00368   *         Refer to description of parameters or to reference manual.
00369   * @note   On this STM32 serie, scaler bridge is configurable:
00370   *         to optimize power consumption, this function enables the
00371   *         voltage scaler bridge only when required
00372   *         (when selecting comparator input based on VrefInt: VrefInt or
00373   *         subdivision of VrefInt).
00374   *         - For scaler bridge power consumption values,
00375   *           refer to device datasheet, parameter "IDDA(SCALER)".
00376   *         - Voltage scaler requires a delay for voltage stabilization.
00377   *           Refer to device datasheet, parameter "tSTART_SCALER".
00378   *         - Scaler bridge is common for all comparator instances,
00379   *           therefore if at least one of the comparator instance
00380   *           is requiring the scaler bridge, it remains enabled.
00381   * @rmtoll CSR      INMSEL         LL_COMP_ConfigInputs\n
00382   *         CSR      INPSEL         LL_COMP_ConfigInputs\n
00383   *         CSR      BRGEN          LL_COMP_ConfigInputs\n
00384   *         CSR      SCALEN         LL_COMP_ConfigInputs
00385   * @param  COMPx Comparator instance
00386   * @param  InputMinus This parameter can be one of the following values:
00387   *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
00388   *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
00389   *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
00390   *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT
00391   *         @arg @ref LL_COMP_INPUT_MINUS_IO1
00392   *         @arg @ref LL_COMP_INPUT_MINUS_IO2
00393   *         @arg @ref LL_COMP_INPUT_MINUS_IO3
00394   *         @arg @ref LL_COMP_INPUT_MINUS_IO4
00395   *         @arg @ref LL_COMP_INPUT_MINUS_IO5
00396   * @param  InputPlus This parameter can be one of the following values:
00397   *         @arg @ref LL_COMP_INPUT_PLUS_IO1
00398   *         @arg @ref LL_COMP_INPUT_PLUS_IO2
00399   *         @arg @ref LL_COMP_INPUT_PLUS_IO3 (*)
00400   *
00401   *         (*) Parameter not available on all devices.
00402   * @retval None
00403   */
00404 __STATIC_INLINE void LL_COMP_ConfigInputs(COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputPlus)
00405 {
00406   MODIFY_REG(COMPx->CSR,
00407              COMP_CSR_INMESEL | COMP_CSR_INMSEL | COMP_CSR_INPSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN,
00408              InputMinus | InputPlus);
00409 }
00410
00411 /**
00412   * @brief  Set comparator input plus (non-inverting).
00413   * @note   In case of comparator input selected to be connected to IO:
00414   *         GPIO pins are specific to each comparator instance.
00415   *         Refer to description of parameters or to reference manual.
00416   * @rmtoll CSR      INPSEL         LL_COMP_SetInputPlus
00417   * @param  COMPx Comparator instance
00418   * @param  InputPlus This parameter can be one of the following values:
00419   *         @arg @ref LL_COMP_INPUT_PLUS_IO1
00420   *         @arg @ref LL_COMP_INPUT_PLUS_IO2
00421   *         @arg @ref LL_COMP_INPUT_PLUS_IO3 (*)
00422   *
00423   *         (*) Parameter not available on all devices.
00424   * @retval None
00425   */
00426 __STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlus)
00427 {
00428   MODIFY_REG(COMPx->CSR, COMP_CSR_INPSEL, InputPlus);
00429 }
00430
00431 /**
00432   * @brief  Get comparator input plus (non-inverting).
00433   * @note   In case of comparator input selected to be connected to IO:
00434   *         GPIO pins are specific to each comparator instance.
00435   *         Refer to description of parameters or to reference manual.
00436   * @rmtoll CSR      INPSEL         LL_COMP_GetInputPlus
00437   * @param  COMPx Comparator instance
00438   * @retval Returned value can be one of the following values:
00439   *         @arg @ref LL_COMP_INPUT_PLUS_IO1
00440   *         @arg @ref LL_COMP_INPUT_PLUS_IO2
00441   *         @arg @ref LL_COMP_INPUT_PLUS_IO3 (*)
00442   *
00443   *         (*) Parameter not available on all devices.
00444   */
00445 __STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx)
00446 {
00447   return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INPSEL));
00448 }
00449
00450 /**
00451   * @brief  Set comparator input minus (inverting).
00452   * @note   In case of comparator input selected to be connected to IO:
00453   *         GPIO pins are specific to each comparator instance.
00454   *         Refer to description of parameters or to reference manual.
00455   * @note   On this STM32 serie, scaler bridge is configurable:
00456   *         to optimize power consumption, this function enables the
00457   *         voltage scaler bridge only when required
00458   *         (when selecting comparator input based on VrefInt: VrefInt or
00459   *         subdivision of VrefInt).
00460   *         - For scaler bridge power consumption values,
00461   *           refer to device datasheet, parameter "IDDA(SCALER)".
00462   *         - Voltage scaler requires a delay for voltage stabilization.
00463   *           Refer to device datasheet, parameter "tSTART_SCALER".
00464   *         - Scaler bridge is common for all comparator instances,
00465   *           therefore if at least one of the comparator instance
00466   *           is requiring the scaler bridge, it remains enabled.
00467   * @rmtoll CSR      INMSEL         LL_COMP_SetInputMinus\n
00468   *         CSR      BRGEN          LL_COMP_SetInputMinus\n
00469   *         CSR      SCALEN         LL_COMP_SetInputMinus
00470   * @param  COMPx Comparator instance
00471   * @param  InputMinus This parameter can be one of the following values:
00472   *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
00473   *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
00474   *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
00475   *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT
00476   *         @arg @ref LL_COMP_INPUT_MINUS_IO1
00477   *         @arg @ref LL_COMP_INPUT_MINUS_IO2
00478   *         @arg @ref LL_COMP_INPUT_MINUS_IO3
00479   *         @arg @ref LL_COMP_INPUT_MINUS_IO4
00480   *         @arg @ref LL_COMP_INPUT_MINUS_IO5
00481   * @retval None
00482   */
00483 __STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMinus)
00484 {
00485   MODIFY_REG(COMPx->CSR, COMP_CSR_INMESEL | COMP_CSR_INMSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN, InputMinus);
00486 }
00487
00488 /**
00489   * @brief  Get comparator input minus (inverting).
00490   * @note   In case of comparator input selected to be connected to IO:
00491   *         GPIO pins are specific to each comparator instance.
00492   *         Refer to description of parameters or to reference manual.
00493   * @rmtoll CSR      INMSEL         LL_COMP_GetInputMinus\n
00494   *         CSR      BRGEN          LL_COMP_GetInputMinus\n
00495   *         CSR      SCALEN         LL_COMP_GetInputMinus
00496   * @param  COMPx Comparator instance
00497   * @retval Returned value can be one of the following values:
00498   *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
00499   *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
00500   *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
00501   *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT
00502   *         @arg @ref LL_COMP_INPUT_MINUS_IO1
00503   *         @arg @ref LL_COMP_INPUT_MINUS_IO2
00504   *         @arg @ref LL_COMP_INPUT_MINUS_IO3
00505   *         @arg @ref LL_COMP_INPUT_MINUS_IO4
00506   *         @arg @ref LL_COMP_INPUT_MINUS_IO5
00507   */
00508 __STATIC_INLINE uint32_t LL_COMP_GetInputMinus(COMP_TypeDef *COMPx)
00509 {
00510   return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INMESEL | COMP_CSR_INMSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN));
00511 }
00512
00513 /**
00514   * @brief  Set comparator instance hysteresis mode of the input minus (inverting input).
00515   * @rmtoll CSR      HYST           LL_COMP_SetInputHysteresis
00516   * @param  COMPx Comparator instance
00517   * @param  InputHysteresis This parameter can be one of the following values:
00518   *         @arg @ref LL_COMP_HYSTERESIS_NONE
00519   *         @arg @ref LL_COMP_HYSTERESIS_LOW
00520   *         @arg @ref LL_COMP_HYSTERESIS_MEDIUM
00521   *         @arg @ref LL_COMP_HYSTERESIS_HIGH
00522   * @retval None
00523   */
00524 __STATIC_INLINE void LL_COMP_SetInputHysteresis(COMP_TypeDef *COMPx, uint32_t InputHysteresis)
00525 {
00526   MODIFY_REG(COMPx->CSR, COMP_CSR_HYST, InputHysteresis);
00527 }
00528
00529 /**
00530   * @brief  Get comparator instance hysteresis mode of the minus (inverting) input.
00531   * @rmtoll CSR      HYST           LL_COMP_GetInputHysteresis
00532   * @param  COMPx Comparator instance
00533   * @retval Returned value can be one of the following values:
00534   *         @arg @ref LL_COMP_HYSTERESIS_NONE
00535   *         @arg @ref LL_COMP_HYSTERESIS_LOW
00536   *         @arg @ref LL_COMP_HYSTERESIS_MEDIUM
00537   *         @arg @ref LL_COMP_HYSTERESIS_HIGH
00538   */
00539 __STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(COMP_TypeDef *COMPx)
00540 {
00541   return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_HYST));
00542 }
00543
00544 /**
00545   * @}
00546   */
00547
00548 /** @defgroup COMP_LL_EF_Configuration_comparator_output Configuration of comparator output
00549   * @{
00550   */
00551
00552 /**
00553   * @brief  Set comparator instance output polarity.
00554   * @rmtoll CSR      POLARITY       LL_COMP_SetOutputPolarity
00555   * @param  COMPx Comparator instance
00556   * @param  OutputPolarity This parameter can be one of the following values:
00557   *         @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
00558   *         @arg @ref LL_COMP_OUTPUTPOL_INVERTED
00559   * @retval None
00560   */
00561 __STATIC_INLINE void LL_COMP_SetOutputPolarity(COMP_TypeDef *COMPx, uint32_t OutputPolarity)
00562 {
00563   MODIFY_REG(COMPx->CSR, COMP_CSR_POLARITY, OutputPolarity);
00564 }
00565
00566 /**
00567   * @brief  Get comparator instance output polarity.
00568   * @rmtoll CSR      POLARITY       LL_COMP_GetOutputPolarity
00569   * @param  COMPx Comparator instance
00570   * @retval Returned value can be one of the following values:
00571   *         @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
00572   *         @arg @ref LL_COMP_OUTPUTPOL_INVERTED
00573   */
00574 __STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(COMP_TypeDef *COMPx)
00575 {
00576   return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_POLARITY));
00577 }
00578
00579 /**
00580   * @brief  Set comparator instance blanking source.
00581   * @note   Blanking source may be specific to each comparator instance.
00582   *         Refer to description of parameters or to reference manual.
00583   * @note   Availability of parameters of blanking source from timer
00584   *         depends on timers availability on the selected device.
00585   * @rmtoll CSR      BLANKING       LL_COMP_SetOutputBlankingSource
00586   * @param  COMPx Comparator instance
00587   * @param  BlankingSource This parameter can be one of the following values:
00588   *         @arg @ref LL_COMP_BLANKINGSRC_NONE
00589   *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5  (1)
00590   *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3  (1)
00591   *
00592   *         (1) Parameter availability depending on timer availability
00593   *             on the selected device.
00594   * @retval None
00595   */
00596 __STATIC_INLINE void LL_COMP_SetOutputBlankingSource(COMP_TypeDef *COMPx, uint32_t BlankingSource)
00597 {
00598   MODIFY_REG(COMPx->CSR, COMP_CSR_BLANKING, BlankingSource);
00599 }
00600
00601 /**
00602   * @brief  Get comparator instance blanking source.
00603   * @note   Availability of parameters of blanking source from timer
00604   *         depends on timers availability on the selected device.
00605   * @note   Blanking source may be specific to each comparator instance.
00606   *         Refer to description of parameters or to reference manual.
00607   * @rmtoll CSR      BLANKING       LL_COMP_GetOutputBlankingSource
00608   * @param  COMPx Comparator instance
00609   * @retval Returned value can be one of the following values:
00610   *         @arg @ref LL_COMP_BLANKINGSRC_NONE
00611   *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5  (1)
00612   *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3  (1)
00613   *
00614   *         (1) Parameter availability depending on timer availability
00615   *             on the selected device.
00616   */
00617 __STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(COMP_TypeDef *COMPx)
00618 {
00619   return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_BLANKING));
00620 }
00621
00622 /**
00623   * @}
00624   */
00625
00626 /** @defgroup COMP_LL_EF_Operation Operation on comparator instance
00627   * @{
00628   */
00629
00630 /**
00631   * @brief  Enable comparator instance.
00632   * @note   After enable from off state, comparator requires a delay
00633   *         to reach reach propagation delay specification.
00634   *         Refer to device datasheet, parameter "tSTART".
00635   * @rmtoll CSR      EN             LL_COMP_Enable
00636   * @param  COMPx Comparator instance
00637   * @retval None
00638   */
00639 __STATIC_INLINE void LL_COMP_Enable(COMP_TypeDef *COMPx)
00640 {
00641   SET_BIT(COMPx->CSR, COMP_CSR_EN);
00642 }
00643
00644 /**
00645   * @brief  Disable comparator instance.
00646   * @rmtoll CSR      EN             LL_COMP_Disable
00647   * @param  COMPx Comparator instance
00648   * @retval None
00649   */
00650 __STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *COMPx)
00651 {
00652   CLEAR_BIT(COMPx->CSR, COMP_CSR_EN);
00653 }
00654
00655 /**
00656   * @brief  Get comparator enable state
00657   *         (0: COMP is disabled, 1: COMP is enabled)
00658   * @rmtoll CSR      EN             LL_COMP_IsEnabled
00659   * @param  COMPx Comparator instance
00660   * @retval State of bit (1 or 0).
00661   */
00662 __STATIC_INLINE uint32_t LL_COMP_IsEnabled(COMP_TypeDef *COMPx)
00663 {
00664   return ((READ_BIT(COMPx->CSR, COMP_CSR_EN) == (COMP_CSR_EN)) ? 1UL : 0UL);
00665 }
00666
00667 /**
00668   * @brief  Lock comparator instance.
00669   * @note   Once locked, comparator configuration can be accessed in read-only.
00670   * @note   The only way to unlock the comparator is a device hardware reset.
00671   * @rmtoll CSR      LOCK           LL_COMP_Lock
00672   * @param  COMPx Comparator instance
00673   * @retval None
00674   */
00675 __STATIC_INLINE void LL_COMP_Lock(COMP_TypeDef *COMPx)
00676 {
00677   SET_BIT(COMPx->CSR, COMP_CSR_LOCK);
00678 }
00679
00680 /**
00681   * @brief  Get comparator lock state
00682   *         (0: COMP is unlocked, 1: COMP is locked).
00683   * @note   Once locked, comparator configuration can be accessed in read-only.
00684   * @note   The only way to unlock the comparator is a device hardware reset.
00685   * @rmtoll CSR      LOCK           LL_COMP_IsLocked
00686   * @param  COMPx Comparator instance
00687   * @retval State of bit (1 or 0).
00688   */
00689 __STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx)
00690 {
00691   return ((READ_BIT(COMPx->CSR, COMP_CSR_LOCK) == (COMP_CSR_LOCK)) ? 1UL : 0UL);
00692 }
00693
00694 /**
00695   * @brief  Read comparator instance output level.
00696   * @note   The comparator output level depends on the selected polarity
00697   *         (Refer to function @ref LL_COMP_SetOutputPolarity()).
00698   *         If the comparator polarity is not inverted:
00699   *          - Comparator output is low when the input plus
00700   *            is at a lower voltage than the input minus
00701   *          - Comparator output is high when the input plus
00702   *            is at a higher voltage than the input minus
00703   *         If the comparator polarity is inverted:
00704   *          - Comparator output is high when the input plus
00705   *            is at a lower voltage than the input minus
00706   *          - Comparator output is low when the input plus
00707   *            is at a higher voltage than the input minus
00708   * @rmtoll CSR      VALUE          LL_COMP_ReadOutputLevel
00709   * @param  COMPx Comparator instance
00710   * @retval Returned value can be one of the following values:
00711   *         @arg @ref LL_COMP_OUTPUT_LEVEL_LOW
00712   *         @arg @ref LL_COMP_OUTPUT_LEVEL_HIGH
00713   */
00714 __STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx)
00715 {
00716   return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_VALUE)
00717                     >> LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS);
00718 }
00719
00720 /**
00721   * @}
00722   */
00723
00724 #if defined(USE_FULL_LL_DRIVER)
00725 /** @defgroup COMP_LL_EF_Init Initialization and de-initialization functions
00726   * @{
00727   */
00728
00729 ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx);
00730 ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct);
00731 void        LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct);
00732
00733 /**
00734   * @}
00735   */
00736 #endif /* USE_FULL_LL_DRIVER */
00737
00738 /**
00739   * @}
00740   */
00741
00742 /**
00743   * @}
00744   */
00745
00746 /**
00747   * @}
00748   */
00749
00750 #endif /* COMP1 || COMP2 */
00751
00752 /**
00753   * @}
00754   */
00755
00756 #ifdef __cplusplus
00757 }
00758 #endif
00759
00760 #endif /* STM32WBxx_LL_COMP_H */
00761
00762 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_cortex.h Source File

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stm32wbxx_ll_cortex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_cortex.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CORTEX LL module.
00006   @verbatim
00007   ==============================================================================
00008                      ##### How to use this driver #####
00009   ==============================================================================
00010     [..]
00011     The LL CORTEX driver contains a set of generic APIs that can be
00012     used by user:
00013       (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
00014           functions
00015       (+) Low power mode configuration (SCB register of Cortex-MCU)
00016       (+) MPU API to configure and enable regions
00017       (+) API to access to MCU info (CPUID register)
00018       (+) API to enable fault handler (SHCSR accesses)
00019
00020   @endverbatim
00021   ******************************************************************************
00022   * @attention
00023   *
00024   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00025   * All rights reserved.</center></h2>
00026   *
00027   * This software component is licensed by ST under BSD 3-Clause license,
00028   * the "License"; You may not use this file except in compliance with the
00029   * License. You may obtain a copy of the License at:
00030   *                        opensource.org/licenses/BSD-3-Clause
00031   *
00032   ******************************************************************************
00033   */
00034
00035 /* Define to prevent recursive inclusion -------------------------------------*/
00036 #ifndef STM32WBxx_LL_CORTEX_H
00037 #define STM32WBxx_LL_CORTEX_H
00038
00039 #ifdef __cplusplus
00040 extern "C" {
00041 #endif
00042
00043 /* Includes ------------------------------------------------------------------*/
00044 #include "stm32wbxx.h"
00045
00046 /** @addtogroup STM32WBxx_LL_Driver
00047   * @{
00048   */
00049
00050 /** @defgroup CORTEX_LL CORTEX
00051   * @{
00052   */
00053
00054 /* Private types -------------------------------------------------------------*/
00055 /* Private variables ---------------------------------------------------------*/
00056
00057 /* Private constants ---------------------------------------------------------*/
00058
00059 /* Private macros ------------------------------------------------------------*/
00060
00061 /* Exported types ------------------------------------------------------------*/
00062 /* Exported constants --------------------------------------------------------*/
00063 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
00064   * @{
00065   */
00066
00067 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
00068   * @{
00069   */
00070 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8     0x00000000U                 /*!< AHB clock divided by 8 selected as SysTick clock source.*/
00071 #define LL_SYSTICK_CLKSOURCE_HCLK          SysTick_CTRL_CLKSOURCE_Msk  /*!< AHB clock selected as SysTick clock source. */
00072 /**
00073   * @}
00074   */
00075
00076 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
00077   * @{
00078   */
00079 #define LL_HANDLER_FAULT_USG               SCB_SHCSR_USGFAULTENA_Msk              /*!< Usage fault */
00080 #define LL_HANDLER_FAULT_BUS               SCB_SHCSR_BUSFAULTENA_Msk              /*!< Bus fault */
00081 #define LL_HANDLER_FAULT_MEM               SCB_SHCSR_MEMFAULTENA_Msk              /*!< Memory management fault */
00082 /**
00083   * @}
00084   */
00085
00086 #if __MPU_PRESENT
00087
00088 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
00089   * @{
00090   */
00091 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE     0x00000000U                                       /*!< Disable NMI and privileged SW access */
00092 #define LL_MPU_CTRL_HARDFAULT_NMI          MPU_CTRL_HFNMIENA_Msk                             /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
00093 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT     MPU_CTRL_PRIVDEFENA_Msk                           /*!< Enable privileged software access to default memory map */
00094 #define LL_MPU_CTRL_HFNMI_PRIVDEF          (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
00095 /**
00096   * @}
00097   */
00098
00099 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number
00100   * @{
00101   */
00102 #define LL_MPU_REGION_NUMBER0              0x00U /*!< REGION Number 0 */
00103 #define LL_MPU_REGION_NUMBER1              0x01U /*!< REGION Number 1 */
00104 #define LL_MPU_REGION_NUMBER2              0x02U /*!< REGION Number 2 */
00105 #define LL_MPU_REGION_NUMBER3              0x03U /*!< REGION Number 3 */
00106 #define LL_MPU_REGION_NUMBER4              0x04U /*!< REGION Number 4 */
00107 #define LL_MPU_REGION_NUMBER5              0x05U /*!< REGION Number 5 */
00108 #define LL_MPU_REGION_NUMBER6              0x06U /*!< REGION Number 6 */
00109 #define LL_MPU_REGION_NUMBER7              0x07U /*!< REGION Number 7 */
00110 /**
00111   * @}
00112   */
00113
00114 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
00115   * @{
00116   */
00117 #define LL_MPU_REGION_SIZE_32B             (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
00118 #define LL_MPU_REGION_SIZE_64B             (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
00119 #define LL_MPU_REGION_SIZE_128B            (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
00120 #define LL_MPU_REGION_SIZE_256B            (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
00121 #define LL_MPU_REGION_SIZE_512B            (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
00122 #define LL_MPU_REGION_SIZE_1KB             (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
00123 #define LL_MPU_REGION_SIZE_2KB             (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
00124 #define LL_MPU_REGION_SIZE_4KB             (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
00125 #define LL_MPU_REGION_SIZE_8KB             (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
00126 #define LL_MPU_REGION_SIZE_16KB            (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
00127 #define LL_MPU_REGION_SIZE_32KB            (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
00128 #define LL_MPU_REGION_SIZE_64KB            (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
00129 #define LL_MPU_REGION_SIZE_128KB           (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
00130 #define LL_MPU_REGION_SIZE_256KB           (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
00131 #define LL_MPU_REGION_SIZE_512KB           (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
00132 #define LL_MPU_REGION_SIZE_1MB             (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
00133 #define LL_MPU_REGION_SIZE_2MB             (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
00134 #define LL_MPU_REGION_SIZE_4MB             (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
00135 #define LL_MPU_REGION_SIZE_8MB             (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
00136 #define LL_MPU_REGION_SIZE_16MB            (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
00137 #define LL_MPU_REGION_SIZE_32MB            (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
00138 #define LL_MPU_REGION_SIZE_64MB            (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
00139 #define LL_MPU_REGION_SIZE_128MB           (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
00140 #define LL_MPU_REGION_SIZE_256MB           (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
00141 #define LL_MPU_REGION_SIZE_512MB           (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
00142 #define LL_MPU_REGION_SIZE_1GB             (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
00143 #define LL_MPU_REGION_SIZE_2GB             (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
00144 #define LL_MPU_REGION_SIZE_4GB             (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
00145 /**
00146   * @}
00147   */
00148
00149 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
00150   * @{
00151   */
00152 #define LL_MPU_REGION_NO_ACCESS            (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
00153 #define LL_MPU_REGION_PRIV_RW              (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
00154 #define LL_MPU_REGION_PRIV_RW_URO          (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
00155 #define LL_MPU_REGION_FULL_ACCESS          (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
00156 #define LL_MPU_REGION_PRIV_RO              (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
00157 #define LL_MPU_REGION_PRIV_RO_URO          (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
00158 /**
00159   * @}
00160   */
00161
00162 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
00163   * @{
00164   */
00165 #define LL_MPU_TEX_LEVEL0                  (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
00166 #define LL_MPU_TEX_LEVEL1                  (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
00167 #define LL_MPU_TEX_LEVEL2                  (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
00168 #define LL_MPU_TEX_LEVEL4                  (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
00169 /**
00170   * @}
00171   */
00172
00173 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
00174   * @{
00175   */
00176 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE   0x00U            /*!< Instruction fetches enabled */
00177 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE  MPU_RASR_XN_Msk  /*!< Instruction fetches disabled*/
00178 /**
00179   * @}
00180   */
00181
00182 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
00183   * @{
00184   */
00185 #define LL_MPU_ACCESS_SHAREABLE            MPU_RASR_S_Msk   /*!< Shareable memory attribute */
00186 #define LL_MPU_ACCESS_NOT_SHAREABLE        0x00U            /*!< Not Shareable memory attribute */
00187 /**
00188   * @}
00189   */
00190
00191 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
00192   * @{
00193   */
00194 #define LL_MPU_ACCESS_CACHEABLE            MPU_RASR_C_Msk   /*!< Cacheable memory attribute */
00195 #define LL_MPU_ACCESS_NOT_CACHEABLE        0x00U            /*!< Not Cacheable memory attribute */
00196 /**
00197   * @}
00198   */
00199
00200 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
00201   * @{
00202   */
00203 #define LL_MPU_ACCESS_BUFFERABLE           MPU_RASR_B_Msk   /*!< Bufferable memory attribute */
00204 #define LL_MPU_ACCESS_NOT_BUFFERABLE       0x00U            /*!< Not Bufferable memory attribute */
00205 /**
00206   * @}
00207   */
00208 #endif /* __MPU_PRESENT */
00209 /**
00210   * @}
00211   */
00212
00213 /* Exported macro ------------------------------------------------------------*/
00214
00215 /* Exported functions --------------------------------------------------------*/
00216 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
00217   * @{
00218   */
00219
00220 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
00221   * @{
00222   */
00223
00224 /**
00225   * @brief  This function checks if the Systick counter flag is active or not.
00226   * @note   It can be used in timeout function on application side.
00227   * @rmtoll STK_CTRL     COUNTFLAG     LL_SYSTICK_IsActiveCounterFlag
00228   * @retval State of bit (1 or 0).
00229   */
00230 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
00231 {
00232   return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL);
00233 }
00234
00235 /**
00236   * @brief  Configures the SysTick clock source
00237   * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_SetClkSource
00238   * @param  Source This parameter can be one of the following values:
00239   *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
00240   *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
00241   * @retval None
00242   */
00243 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
00244 {
00245   if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
00246   {
00247     SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
00248   }
00249   else
00250   {
00251     CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
00252   }
00253 }
00254
00255 /**
00256   * @brief  Get the SysTick clock source
00257   * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_GetClkSource
00258   * @retval Returned value can be one of the following values:
00259   *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
00260   *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
00261   */
00262 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
00263 {
00264   return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
00265 }
00266
00267 /**
00268   * @brief  Enable SysTick exception request
00269   * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_EnableIT
00270   * @retval None
00271   */
00272 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
00273 {
00274   SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
00275 }
00276
00277 /**
00278   * @brief  Disable SysTick exception request
00279   * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_DisableIT
00280   * @retval None
00281   */
00282 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
00283 {
00284   CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
00285 }
00286
00287 /**
00288   * @brief  Checks if the SYSTICK interrupt is enabled or disabled.
00289   * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_IsEnabledIT
00290   * @retval State of bit (1 or 0).
00291   */
00292 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
00293 {
00294   return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL);
00295 }
00296
00297 /**
00298   * @}
00299   */
00300
00301 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
00302   * @{
00303   */
00304
00305 /**
00306   * @brief  Processor uses sleep as its low power mode
00307   * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableSleep
00308   * @retval None
00309   */
00310 __STATIC_INLINE void LL_LPM_EnableSleep(void)
00311 {
00312   /* Clear SLEEPDEEP bit of Cortex System Control Register */
00313   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00314 }
00315
00316 /**
00317   * @brief  Processor uses deep sleep as its low power mode
00318   * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableDeepSleep
00319   * @retval None
00320   */
00321 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
00322 {
00323   /* Set SLEEPDEEP bit of Cortex System Control Register */
00324   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00325 }
00326
00327 /**
00328   * @brief  Configures sleep-on-exit when returning from Handler mode to Thread mode.
00329   * @note   Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
00330   *         empty main application.
00331   * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_EnableSleepOnExit
00332   * @retval None
00333   */
00334 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
00335 {
00336   /* Set SLEEPONEXIT bit of Cortex System Control Register */
00337   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
00338 }
00339
00340 /**
00341   * @brief  Do not sleep when returning to Thread mode.
00342   * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_DisableSleepOnExit
00343   * @retval None
00344   */
00345 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
00346 {
00347   /* Clear SLEEPONEXIT bit of Cortex System Control Register */
00348   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
00349 }
00350
00351 /**
00352   * @brief  Enabled events and all interrupts, including disabled interrupts, can wakeup the
00353   *         processor.
00354   * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_EnableEventOnPend
00355   * @retval None
00356   */
00357 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
00358 {
00359   /* Set SEVEONPEND bit of Cortex System Control Register */
00360   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
00361 }
00362
00363 /**
00364   * @brief  Only enabled interrupts or events can wakeup the processor, disabled interrupts are
00365   *         excluded
00366   * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_DisableEventOnPend
00367   * @retval None
00368   */
00369 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
00370 {
00371   /* Clear SEVEONPEND bit of Cortex System Control Register */
00372   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
00373 }
00374
00375 /**
00376   * @}
00377   */
00378
00379 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER
00380   * @{
00381   */
00382
00383 /**
00384   * @brief  Enable a fault in System handler control register (SHCSR)
00385   * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_EnableFault
00386   * @param  Fault This parameter can be a combination of the following values:
00387   *         @arg @ref LL_HANDLER_FAULT_USG
00388   *         @arg @ref LL_HANDLER_FAULT_BUS
00389   *         @arg @ref LL_HANDLER_FAULT_MEM
00390   * @retval None
00391   */
00392 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
00393 {
00394   /* Enable the system handler fault */
00395   SET_BIT(SCB->SHCSR, Fault);
00396 }
00397
00398 /**
00399   * @brief  Disable a fault in System handler control register (SHCSR)
00400   * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_DisableFault
00401   * @param  Fault This parameter can be a combination of the following values:
00402   *         @arg @ref LL_HANDLER_FAULT_USG
00403   *         @arg @ref LL_HANDLER_FAULT_BUS
00404   *         @arg @ref LL_HANDLER_FAULT_MEM
00405   * @retval None
00406   */
00407 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
00408 {
00409   /* Disable the system handler fault */
00410   CLEAR_BIT(SCB->SHCSR, Fault);
00411 }
00412
00413 /**
00414   * @}
00415   */
00416
00417 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
00418   * @{
00419   */
00420
00421 /**
00422   * @brief  Get Implementer code
00423   * @rmtoll SCB_CPUID    IMPLEMENTER   LL_CPUID_GetImplementer
00424   * @retval Value should be equal to 0x41 for ARM
00425   */
00426 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
00427 {
00428   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
00429 }
00430
00431 /**
00432   * @brief  Get Variant number (The r value in the rnpn product revision identifier)
00433   * @rmtoll SCB_CPUID    VARIANT       LL_CPUID_GetVariant
00434   * @retval Value between 0 and 255 (0x0: revision 0)
00435   */
00436 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
00437 {
00438   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
00439 }
00440
00441 /**
00442   * @brief  Get Constant number
00443   * @rmtoll SCB_CPUID    ARCHITECTURE  LL_CPUID_GetConstant
00444   * @retval Value should be equal to 0xF for Cortex-M4 devices
00445   */
00446 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
00447 {
00448   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
00449 }
00450
00451 /**
00452   * @brief  Get Part number
00453   * @rmtoll SCB_CPUID    PARTNO        LL_CPUID_GetParNo
00454   * @retval Value should be equal to 0xC24 for Cortex-M4
00455   */
00456 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
00457 {
00458   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
00459 }
00460
00461 /**
00462   * @brief  Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
00463   * @rmtoll SCB_CPUID    REVISION      LL_CPUID_GetRevision
00464   * @retval Value between 0 and 255 (0x1: patch 1)
00465   */
00466 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
00467 {
00468   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
00469 }
00470
00471 /**
00472   * @}
00473   */
00474
00475 #if __MPU_PRESENT
00476 /** @defgroup CORTEX_LL_EF_MPU MPU
00477   * @{
00478   */
00479
00480 /**
00481   * @brief  Enable MPU with input options
00482   * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Enable
00483   * @param  Options This parameter can be one of the following values:
00484   *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
00485   *         @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
00486   *         @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
00487   *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
00488   * @retval None
00489   */
00490 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
00491 {
00492   /* Enable the MPU*/
00493   WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
00494   /* Ensure MPU settings take effects */
00495   __DSB();
00496   /* Sequence instruction fetches using update settings */
00497   __ISB();
00498 }
00499
00500 /**
00501   * @brief  Disable MPU
00502   * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Disable
00503   * @retval None
00504   */
00505 __STATIC_INLINE void LL_MPU_Disable(void)
00506 {
00507   /* Make sure outstanding transfers are done */
00508   __DMB();
00509   /* Disable MPU*/
00510   WRITE_REG(MPU->CTRL, 0U);
00511 }
00512
00513 /**
00514   * @brief  Check if MPU is enabled or not
00515   * @rmtoll MPU_CTRL     ENABLE        LL_MPU_IsEnabled
00516   * @retval State of bit (1 or 0).
00517   */
00518 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
00519 {
00520   return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
00521 }
00522
00523 /**
00524   * @brief  Enable a MPU region
00525   * @rmtoll MPU_RASR     ENABLE        LL_MPU_EnableRegion
00526   * @param  Region This parameter can be one of the following values:
00527   *         @arg @ref LL_MPU_REGION_NUMBER0
00528   *         @arg @ref LL_MPU_REGION_NUMBER1
00529   *         @arg @ref LL_MPU_REGION_NUMBER2
00530   *         @arg @ref LL_MPU_REGION_NUMBER3
00531   *         @arg @ref LL_MPU_REGION_NUMBER4
00532   *         @arg @ref LL_MPU_REGION_NUMBER5
00533   *         @arg @ref LL_MPU_REGION_NUMBER6
00534   *         @arg @ref LL_MPU_REGION_NUMBER7
00535   * @retval None
00536   */
00537 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
00538 {
00539   /* Set Region number */
00540   WRITE_REG(MPU->RNR, Region);
00541   /* Enable the MPU region */
00542   SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
00543 }
00544
00545 /**
00546   * @brief  Configure and enable a region
00547   * @rmtoll MPU_RNR      REGION        LL_MPU_ConfigRegion\n
00548   *         MPU_RBAR     REGION        LL_MPU_ConfigRegion\n
00549   *         MPU_RBAR     ADDR          LL_MPU_ConfigRegion\n
00550   *         MPU_RASR     XN            LL_MPU_ConfigRegion\n
00551   *         MPU_RASR     AP            LL_MPU_ConfigRegion\n
00552   *         MPU_RASR     S             LL_MPU_ConfigRegion\n
00553   *         MPU_RASR     C             LL_MPU_ConfigRegion\n
00554   *         MPU_RASR     B             LL_MPU_ConfigRegion\n
00555   *         MPU_RASR     SIZE          LL_MPU_ConfigRegion
00556   * @param  Region This parameter can be one of the following values:
00557   *         @arg @ref LL_MPU_REGION_NUMBER0
00558   *         @arg @ref LL_MPU_REGION_NUMBER1
00559   *         @arg @ref LL_MPU_REGION_NUMBER2
00560   *         @arg @ref LL_MPU_REGION_NUMBER3
00561   *         @arg @ref LL_MPU_REGION_NUMBER4
00562   *         @arg @ref LL_MPU_REGION_NUMBER5
00563   *         @arg @ref LL_MPU_REGION_NUMBER6
00564   *         @arg @ref LL_MPU_REGION_NUMBER7
00565   * @param  Address Value of region base address
00566   * @param  SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
00567   * @param  Attributes This parameter can be a combination of the following values:
00568   *         @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
00569   *           or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
00570   *           or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
00571   *           or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
00572   *           or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
00573   *           or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
00574   *         @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
00575   *           or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
00576   *         @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
00577   *         @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or  @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
00578   *         @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
00579   *         @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
00580   *         @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
00581   * @retval None
00582   */
00583 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
00584 {
00585   /* Set Region number */
00586   WRITE_REG(MPU->RNR, Region);
00587   /* Set base address */
00588   WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
00589   /* Configure MPU */
00590   WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos)));
00591 }
00592
00593 /**
00594   * @brief  Disable a region
00595   * @rmtoll MPU_RNR      REGION        LL_MPU_DisableRegion\n
00596   *         MPU_RASR     ENABLE        LL_MPU_DisableRegion
00597   * @param  Region This parameter can be one of the following values:
00598   *         @arg @ref LL_MPU_REGION_NUMBER0
00599   *         @arg @ref LL_MPU_REGION_NUMBER1
00600   *         @arg @ref LL_MPU_REGION_NUMBER2
00601   *         @arg @ref LL_MPU_REGION_NUMBER3
00602   *         @arg @ref LL_MPU_REGION_NUMBER4
00603   *         @arg @ref LL_MPU_REGION_NUMBER5
00604   *         @arg @ref LL_MPU_REGION_NUMBER6
00605   *         @arg @ref LL_MPU_REGION_NUMBER7
00606   * @retval None
00607   */
00608 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
00609 {
00610   /* Set Region number */
00611   WRITE_REG(MPU->RNR, Region);
00612   /* Disable the MPU region */
00613   CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
00614 }
00615
00616 /**
00617   * @}
00618   */
00619
00620 #endif /* __MPU_PRESENT */
00621 /**
00622   * @}
00623   */
00624
00625 /**
00626   * @}
00627   */
00628
00629 /**
00630   * @}
00631   */
00632
00633 #ifdef __cplusplus
00634 }
00635 #endif
00636
00637 #endif /* STM32WBxx_LL_CORTEX_H */
00638
00639 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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STM32WB55xx HAL User Manual: stm32wbxx_ll_crc.c Source File

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stm32wbxx_ll_crc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_crc.c
00004   * @author  MCD Application Team
00005   * @brief   CRC LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32wbxx_ll_crc.h"
00023 #include "stm32wbxx_ll_bus.h"
00024
00025 #ifdef  USE_FULL_ASSERT
00026 #include "stm32_assert.h"
00027 #else
00028 #define assert_param(expr) ((void)0U)
00029 #endif
00030
00031 /** @addtogroup STM32WBxx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (CRC)
00036
00037 /** @addtogroup CRC_LL
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /* Private macros ------------------------------------------------------------*/
00045 /* Private function prototypes -----------------------------------------------*/
00046
00047 /* Exported functions --------------------------------------------------------*/
00048 /** @addtogroup CRC_LL_Exported_Functions
00049   * @{
00050   */
00051
00052 /** @addtogroup CRC_LL_EF_Init
00053   * @{
00054   */
00055
00056 /**
00057   * @brief  De-initialize CRC registers (Registers restored to their default values).
00058   * @param  CRCx CRC Instance
00059   * @retval An ErrorStatus enumeration value:
00060   *          - SUCCESS: CRC registers are de-initialized
00061   *          - ERROR: CRC registers are not de-initialized
00062   */
00063 ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx)
00064 {
00065   ErrorStatus status = SUCCESS;
00066
00067   /* Check the parameters */
00068   assert_param(IS_CRC_ALL_INSTANCE(CRCx));
00069
00070   if (CRCx == CRC)
00071   {
00072     /* Force CRC reset */
00073     LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CRC);
00074
00075     /* Release CRC reset */
00076     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC);
00077   }
00078   else
00079   {
00080     status = ERROR;
00081   }
00082
00083   return (status);
00084 }
00085
00086 /**
00087   * @}
00088   */
00089
00090 /**
00091   * @}
00092   */
00093
00094 /**
00095   * @}
00096   */
00097
00098 #endif /* defined (CRC) */
00099
00100 /**
00101   * @}
00102   */
00103
00104 #endif /* USE_FULL_LL_DRIVER */
00105
00106 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00107
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_crc.h Source File

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stm32wbxx_ll_crc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_crc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CRC LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_LL_CRC_H
00022 #define STM32WBxx_LL_CRC_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx.h"
00030
00031 /** @addtogroup STM32WBxx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined(CRC)
00036
00037 /** @defgroup CRC_LL CRC
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /* Private macros ------------------------------------------------------------*/
00045
00046 /* Exported types ------------------------------------------------------------*/
00047 /* Exported constants --------------------------------------------------------*/
00048 /** @defgroup CRC_LL_Exported_Constants CRC Exported Constants
00049   * @{
00050   */
00051
00052 /** @defgroup CRC_LL_EC_POLYLENGTH Polynomial length
00053   * @{
00054   */
00055 #define LL_CRC_POLYLENGTH_32B              0x00000000U                              /*!< 32 bits Polynomial size */
00056 #define LL_CRC_POLYLENGTH_16B              CRC_CR_POLYSIZE_0                        /*!< 16 bits Polynomial size */
00057 #define LL_CRC_POLYLENGTH_8B               CRC_CR_POLYSIZE_1                        /*!< 8 bits Polynomial size */
00058 #define LL_CRC_POLYLENGTH_7B               (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0)  /*!< 7 bits Polynomial size */
00059 /**
00060   * @}
00061   */
00062
00063 /** @defgroup CRC_LL_EC_INDATA_REVERSE Input Data Reverse
00064   * @{
00065   */
00066 #define LL_CRC_INDATA_REVERSE_NONE         0x00000000U                              /*!< Input Data bit order not affected */
00067 #define LL_CRC_INDATA_REVERSE_BYTE         CRC_CR_REV_IN_0                          /*!< Input Data bit reversal done by byte */
00068 #define LL_CRC_INDATA_REVERSE_HALFWORD     CRC_CR_REV_IN_1                          /*!< Input Data bit reversal done by half-word */
00069 #define LL_CRC_INDATA_REVERSE_WORD         (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0)      /*!< Input Data bit reversal done by word */
00070 /**
00071   * @}
00072   */
00073
00074 /** @defgroup CRC_LL_EC_OUTDATA_REVERSE Output Data Reverse
00075   * @{
00076   */
00077 #define LL_CRC_OUTDATA_REVERSE_NONE        0x00000000U                               /*!< Output Data bit order not affected */
00078 #define LL_CRC_OUTDATA_REVERSE_BIT         CRC_CR_REV_OUT                            /*!< Output Data bit reversal done by bit */
00079 /**
00080   * @}
00081   */
00082
00083 /** @defgroup CRC_LL_EC_Default_Polynomial_Value    Default CRC generating polynomial value
00084   * @brief    Normal representation of this polynomial value is
00085   *           X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 .
00086   * @{
00087   */
00088 #define LL_CRC_DEFAULT_CRC32_POLY          0x04C11DB7U                               /*!< Default CRC generating polynomial value */
00089 /**
00090   * @}
00091   */
00092
00093 /** @defgroup CRC_LL_EC_Default_InitValue    Default CRC computation initialization value
00094   * @{
00095   */
00096 #define LL_CRC_DEFAULT_CRC_INITVALUE       0xFFFFFFFFU                               /*!< Default CRC computation initialization value */
00097 /**
00098   * @}
00099   */
00100
00101 /**
00102   * @}
00103   */
00104
00105 /* Exported macro ------------------------------------------------------------*/
00106 /** @defgroup CRC_LL_Exported_Macros CRC Exported Macros
00107   * @{
00108   */
00109
00110 /** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros
00111   * @{
00112   */
00113
00114 /**
00115   * @brief  Write a value in CRC register
00116   * @param  __INSTANCE__ CRC Instance
00117   * @param  __REG__ Register to be written
00118   * @param  __VALUE__ Value to be written in the register
00119   * @retval None
00120   */
00121 #define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__)
00122
00123 /**
00124   * @brief  Read a value in CRC register
00125   * @param  __INSTANCE__ CRC Instance
00126   * @param  __REG__ Register to be read
00127   * @retval Register value
00128   */
00129 #define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00130 /**
00131   * @}
00132   */
00133
00134 /**
00135   * @}
00136   */
00137
00138
00139 /* Exported functions --------------------------------------------------------*/
00140 /** @defgroup CRC_LL_Exported_Functions CRC Exported Functions
00141   * @{
00142   */
00143
00144 /** @defgroup CRC_LL_EF_Configuration CRC Configuration functions
00145   * @{
00146   */
00147
00148 /**
00149   * @brief  Reset the CRC calculation unit.
00150   * @note   If Programmable Initial CRC value feature
00151   *         is available, also set the Data Register to the value stored in the
00152   *         CRC_INIT register, otherwise, reset Data Register to its default value.
00153   * @rmtoll CR           RESET         LL_CRC_ResetCRCCalculationUnit
00154   * @param  CRCx CRC Instance
00155   * @retval None
00156   */
00157 __STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx)
00158 {
00159   SET_BIT(CRCx->CR, CRC_CR_RESET);
00160 }
00161
00162 /**
00163   * @brief  Configure size of the polynomial.
00164   * @rmtoll CR           POLYSIZE      LL_CRC_SetPolynomialSize
00165   * @param  CRCx CRC Instance
00166   * @param  PolySize This parameter can be one of the following values:
00167   *         @arg @ref LL_CRC_POLYLENGTH_32B
00168   *         @arg @ref LL_CRC_POLYLENGTH_16B
00169   *         @arg @ref LL_CRC_POLYLENGTH_8B
00170   *         @arg @ref LL_CRC_POLYLENGTH_7B
00171   * @retval None
00172   */
00173 __STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *CRCx, uint32_t PolySize)
00174 {
00175   MODIFY_REG(CRCx->CR, CRC_CR_POLYSIZE, PolySize);
00176 }
00177
00178 /**
00179   * @brief  Return size of the polynomial.
00180   * @rmtoll CR           POLYSIZE      LL_CRC_GetPolynomialSize
00181   * @param  CRCx CRC Instance
00182   * @retval Returned value can be one of the following values:
00183   *         @arg @ref LL_CRC_POLYLENGTH_32B
00184   *         @arg @ref LL_CRC_POLYLENGTH_16B
00185   *         @arg @ref LL_CRC_POLYLENGTH_8B
00186   *         @arg @ref LL_CRC_POLYLENGTH_7B
00187   */
00188 __STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(CRC_TypeDef *CRCx)
00189 {
00190   return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE));
00191 }
00192
00193 /**
00194   * @brief  Configure the reversal of the bit order of the input data
00195   * @rmtoll CR           REV_IN        LL_CRC_SetInputDataReverseMode
00196   * @param  CRCx CRC Instance
00197   * @param  ReverseMode This parameter can be one of the following values:
00198   *         @arg @ref LL_CRC_INDATA_REVERSE_NONE
00199   *         @arg @ref LL_CRC_INDATA_REVERSE_BYTE
00200   *         @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
00201   *         @arg @ref LL_CRC_INDATA_REVERSE_WORD
00202   * @retval None
00203   */
00204 __STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
00205 {
00206   MODIFY_REG(CRCx->CR, CRC_CR_REV_IN, ReverseMode);
00207 }
00208
00209 /**
00210   * @brief  Return type of reversal for input data bit order
00211   * @rmtoll CR           REV_IN        LL_CRC_GetInputDataReverseMode
00212   * @param  CRCx CRC Instance
00213   * @retval Returned value can be one of the following values:
00214   *         @arg @ref LL_CRC_INDATA_REVERSE_NONE
00215   *         @arg @ref LL_CRC_INDATA_REVERSE_BYTE
00216   *         @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
00217   *         @arg @ref LL_CRC_INDATA_REVERSE_WORD
00218   */
00219 __STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(CRC_TypeDef *CRCx)
00220 {
00221   return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN));
00222 }
00223
00224 /**
00225   * @brief  Configure the reversal of the bit order of the Output data
00226   * @rmtoll CR           REV_OUT       LL_CRC_SetOutputDataReverseMode
00227   * @param  CRCx CRC Instance
00228   * @param  ReverseMode This parameter can be one of the following values:
00229   *         @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
00230   *         @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
00231   * @retval None
00232   */
00233 __STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
00234 {
00235   MODIFY_REG(CRCx->CR, CRC_CR_REV_OUT, ReverseMode);
00236 }
00237
00238 /**
00239   * @brief  Configure the reversal of the bit order of the Output data
00240   * @rmtoll CR           REV_OUT       LL_CRC_GetOutputDataReverseMode
00241   * @param  CRCx CRC Instance
00242   * @retval Returned value can be one of the following values:
00243   *         @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
00244   *         @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
00245   */
00246 __STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(CRC_TypeDef *CRCx)
00247 {
00248   return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT));
00249 }
00250
00251 /**
00252   * @brief  Initialize the Programmable initial CRC value.
00253   * @note   If the CRC size is less than 32 bits, the least significant bits
00254   *         are used to write the correct value
00255   * @note   LL_CRC_DEFAULT_CRC_INITVALUE could be used as value for InitCrc parameter.
00256   * @rmtoll INIT         INIT          LL_CRC_SetInitialData
00257   * @param  CRCx CRC Instance
00258   * @param  InitCrc Value to be programmed in Programmable initial CRC value register
00259   * @retval None
00260   */
00261 __STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *CRCx, uint32_t InitCrc)
00262 {
00263   WRITE_REG(CRCx->INIT, InitCrc);
00264 }
00265
00266 /**
00267   * @brief  Return current Initial CRC value.
00268   * @note   If the CRC size is less than 32 bits, the least significant bits
00269   *         are used to read the correct value
00270   * @rmtoll INIT         INIT          LL_CRC_GetInitialData
00271   * @param  CRCx CRC Instance
00272   * @retval Value programmed in Programmable initial CRC value register
00273   */
00274 __STATIC_INLINE uint32_t LL_CRC_GetInitialData(CRC_TypeDef *CRCx)
00275 {
00276   return (uint32_t)(READ_REG(CRCx->INIT));
00277 }
00278
00279 /**
00280   * @brief  Initialize the Programmable polynomial value
00281   *         (coefficients of the polynomial to be used for CRC calculation).
00282   * @note   LL_CRC_DEFAULT_CRC32_POLY could be used as value for PolynomCoef parameter.
00283   * @note   Please check Reference Manual and existing Errata Sheets,
00284   *         regarding possible limitations for Polynomial values usage.
00285   *         For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
00286   * @rmtoll POL          POL           LL_CRC_SetPolynomialCoef
00287   * @param  CRCx CRC Instance
00288   * @param  PolynomCoef Value to be programmed in Programmable Polynomial value register
00289   * @retval None
00290   */
00291 __STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *CRCx, uint32_t PolynomCoef)
00292 {
00293   WRITE_REG(CRCx->POL, PolynomCoef);
00294 }
00295
00296 /**
00297   * @brief  Return current Programmable polynomial value
00298   * @note   Please check Reference Manual and existing Errata Sheets,
00299   *         regarding possible limitations for Polynomial values usage.
00300   *         For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
00301   * @rmtoll POL          POL           LL_CRC_GetPolynomialCoef
00302   * @param  CRCx CRC Instance
00303   * @retval Value programmed in Programmable Polynomial value register
00304   */
00305 __STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(CRC_TypeDef *CRCx)
00306 {
00307   return (uint32_t)(READ_REG(CRCx->POL));
00308 }
00309
00310 /**
00311   * @}
00312   */
00313
00314 /** @defgroup CRC_LL_EF_Data_Management Data_Management
00315   * @{
00316   */
00317
00318 /**
00319   * @brief  Write given 32-bit data to the CRC calculator
00320   * @rmtoll DR           DR            LL_CRC_FeedData32
00321   * @param  CRCx CRC Instance
00322   * @param  InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
00323   * @retval None
00324   */
00325 __STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData)
00326 {
00327   WRITE_REG(CRCx->DR, InData);
00328 }
00329
00330 /**
00331   * @brief  Write given 16-bit data to the CRC calculator
00332   * @rmtoll DR           DR            LL_CRC_FeedData16
00333   * @param  CRCx CRC Instance
00334   * @param  InData 16 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFF
00335   * @retval None
00336   */
00337 __STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData)
00338 {
00339   __IO uint16_t *pReg;
00340
00341   pReg = (__IO uint16_t *)(__IO void *)(&CRCx->DR);                             /* Derogation MisraC2012 R.11.5 */
00342   *pReg = InData;
00343 }
00344
00345 /**
00346   * @brief  Write given 8-bit data to the CRC calculator
00347   * @rmtoll DR           DR            LL_CRC_FeedData8
00348   * @param  CRCx CRC Instance
00349   * @param  InData 8 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFF
00350   * @retval None
00351   */
00352 __STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *CRCx, uint8_t InData)
00353 {
00354   *(uint8_t __IO *)(&CRCx->DR) = (uint8_t) InData;
00355 }
00356
00357 /**
00358   * @brief  Return current CRC calculation result. 32 bits value is returned.
00359   * @rmtoll DR           DR            LL_CRC_ReadData32
00360   * @param  CRCx CRC Instance
00361   * @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
00362   */
00363 __STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
00364 {
00365   return (uint32_t)(READ_REG(CRCx->DR));
00366 }
00367
00368 /**
00369   * @brief  Return current CRC calculation result. 16 bits value is returned.
00370   * @note   This function is expected to be used in a 16 bits CRC polynomial size context.
00371   * @rmtoll DR           DR            LL_CRC_ReadData16
00372   * @param  CRCx CRC Instance
00373   * @retval Current CRC calculation result as stored in CRC_DR register (16 bits).
00374   */
00375 __STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx)
00376 {
00377   return (uint16_t)READ_REG(CRCx->DR);
00378 }
00379
00380 /**
00381   * @brief  Return current CRC calculation result. 8 bits value is returned.
00382   * @note   This function is expected to be used in a 8 bits CRC polynomial size context.
00383   * @rmtoll DR           DR            LL_CRC_ReadData8
00384   * @param  CRCx CRC Instance
00385   * @retval Current CRC calculation result as stored in CRC_DR register (8 bits).
00386   */
00387 __STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx)
00388 {
00389   return (uint8_t)READ_REG(CRCx->DR);
00390 }
00391
00392 /**
00393   * @brief  Return current CRC calculation result. 7 bits value is returned.
00394   * @note   This function is expected to be used in a 7 bits CRC polynomial size context.
00395   * @rmtoll DR           DR            LL_CRC_ReadData7
00396   * @param  CRCx CRC Instance
00397   * @retval Current CRC calculation result as stored in CRC_DR register (7 bits).
00398   */
00399 __STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx)
00400 {
00401   return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU);
00402 }
00403
00404 /**
00405   * @brief  Return data stored in the Independent Data(IDR) register.
00406   * @note   This register can be used as a temporary storage location for one 32-bit long data.
00407   * @rmtoll IDR          IDR           LL_CRC_Read_IDR
00408   * @param  CRCx CRC Instance
00409   * @retval Value stored in CRC_IDR register (General-purpose 32-bit data register).
00410   */
00411 __STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
00412 {
00413   return (uint32_t)(READ_REG(CRCx->IDR));
00414 }
00415
00416 /**
00417   * @brief  Store data in the Independent Data(IDR) register.
00418   * @note   This register can be used as a temporary storage location for one 32-bit long data.
00419   * @rmtoll IDR          IDR           LL_CRC_Write_IDR
00420   * @param  CRCx CRC Instance
00421   * @param  InData value to be stored in CRC_IDR register (32-bit) between Min_Data=0 and Max_Data=0xFFFFFFFF
00422   * @retval None
00423   */
00424 __STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
00425 {
00426   *((uint32_t __IO *)(&CRCx->IDR)) = (uint32_t) InData;
00427 }
00428 /**
00429   * @}
00430   */
00431
00432 #if defined(USE_FULL_LL_DRIVER)
00433 /** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions
00434   * @{
00435   */
00436
00437 ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
00438
00439 /**
00440   * @}
00441   */
00442 #endif /* USE_FULL_LL_DRIVER */
00443
00444 /**
00445   * @}
00446   */
00447
00448 /**
00449   * @}
00450   */
00451
00452 #endif /* defined(CRC) */
00453
00454 /**
00455   * @}
00456   */
00457
00458 #ifdef __cplusplus
00459 }
00460 #endif
00461
00462 #endif /* STM32WBxx_LL_CRC_H */
00463
00464 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_crs.c Source File

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stm32wbxx_ll_crs.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_crs.h
00004   * @author  MCD Application Team
00005   * @brief   CRS LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32wbxx_ll_crs.h"
00023 #include "stm32wbxx_ll_bus.h"
00024
00025 /** @addtogroup STM32WBxx_LL_Driver
00026   * @{
00027   */
00028
00029 #if defined(CRS)
00030
00031 /** @defgroup CRS_LL CRS
00032   * @{
00033   */
00034
00035 /* Private types -------------------------------------------------------------*/
00036 /* Private variables ---------------------------------------------------------*/
00037 /* Private constants ---------------------------------------------------------*/
00038 /* Private macros ------------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040
00041 /* Exported functions --------------------------------------------------------*/
00042 /** @addtogroup CRS_LL_Exported_Functions
00043   * @{
00044   */
00045
00046 /** @addtogroup CRS_LL_EF_Init
00047   * @{
00048   */
00049
00050 /**
00051   * @brief  De-Initializes CRS peripheral registers to their default reset values.
00052   * @retval An ErrorStatus enumeration value:
00053   *          - SUCCESS: CRS registers are de-initialized
00054   *          - ERROR: not applicable
00055   */
00056 ErrorStatus LL_CRS_DeInit(void)
00057 {
00058   LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_CRS);
00059   LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_CRS);
00060
00061   return  SUCCESS;
00062 }
00063
00064
00065
00066 /**
00067   * @}
00068   */
00069
00070 /**
00071   * @}
00072   */
00073
00074 /**
00075   * @}
00076   */
00077
00078 #endif /* defined(CRS) */
00079
00080 /**
00081   * @}
00082   */
00083
00084 #endif /* USE_FULL_LL_DRIVER */
00085
00086 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_crs.h Source File

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stm32wbxx_ll_crs.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_crs.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of CRS LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_LL_CRS_H
00022 #define STM32WBxx_LL_CRS_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx.h"
00030
00031 /** @addtogroup STM32WBxx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined(CRS)
00036
00037 /** @defgroup CRS_LL CRS
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043
00044 /* Private constants ---------------------------------------------------------*/
00045 /** @defgroup CRS_LL_Private_Constants CRS Private Constants
00046   * @{
00047   */
00048
00049 /* Defines used for the bit position in the register and perform offsets*/
00050 #define CRS_POSITION_TRIM        (CRS_CR_TRIM_Pos)     /* bit position in CR reg */
00051 #define CRS_POSITION_FECAP       (CRS_ISR_FECAP_Pos)   /* bit position in ISR reg */
00052 #define CRS_POSITION_FELIM       (CRS_CFGR_FELIM_Pos)  /* bit position in CFGR reg */
00053
00054
00055 /**
00056   * @}
00057   */
00058
00059 /* Private macros ------------------------------------------------------------*/
00060
00061 /* Exported types ------------------------------------------------------------*/
00062 /* Exported constants --------------------------------------------------------*/
00063 /** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
00064   * @{
00065   */
00066
00067 /** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
00068   * @brief    Flags defines which can be used with LL_CRS_ReadReg function
00069   * @{
00070   */
00071 #define LL_CRS_ISR_SYNCOKF                 CRS_ISR_SYNCOKF
00072 #define LL_CRS_ISR_SYNCWARNF               CRS_ISR_SYNCWARNF
00073 #define LL_CRS_ISR_ERRF                    CRS_ISR_ERRF
00074 #define LL_CRS_ISR_ESYNCF                  CRS_ISR_ESYNCF
00075 #define LL_CRS_ISR_SYNCERR                 CRS_ISR_SYNCERR
00076 #define LL_CRS_ISR_SYNCMISS                CRS_ISR_SYNCMISS
00077 #define LL_CRS_ISR_TRIMOVF                 CRS_ISR_TRIMOVF
00078 /**
00079   * @}
00080   */
00081
00082 /** @defgroup CRS_LL_EC_IT IT Defines
00083   * @brief    IT defines which can be used with LL_CRS_ReadReg and  LL_CRS_WriteReg functions
00084   * @{
00085   */
00086 #define LL_CRS_CR_SYNCOKIE                 CRS_CR_SYNCOKIE
00087 #define LL_CRS_CR_SYNCWARNIE               CRS_CR_SYNCWARNIE
00088 #define LL_CRS_CR_ERRIE                    CRS_CR_ERRIE
00089 #define LL_CRS_CR_ESYNCIE                  CRS_CR_ESYNCIE
00090 /**
00091   * @}
00092   */
00093
00094 /** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
00095   * @{
00096   */
00097 #define LL_CRS_SYNC_DIV_1                  0x00000000U                               /*!< Synchro Signal not divided (default) */
00098 #define LL_CRS_SYNC_DIV_2                  CRS_CFGR_SYNCDIV_0                        /*!< Synchro Signal divided by 2 */
00099 #define LL_CRS_SYNC_DIV_4                  CRS_CFGR_SYNCDIV_1                        /*!< Synchro Signal divided by 4 */
00100 #define LL_CRS_SYNC_DIV_8                  (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
00101 #define LL_CRS_SYNC_DIV_16                 CRS_CFGR_SYNCDIV_2                        /*!< Synchro Signal divided by 16 */
00102 #define LL_CRS_SYNC_DIV_32                 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
00103 #define LL_CRS_SYNC_DIV_64                 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
00104 #define LL_CRS_SYNC_DIV_128                CRS_CFGR_SYNCDIV                          /*!< Synchro Signal divided by 128 */
00105 /**
00106   * @}
00107   */
00108
00109 /** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
00110   * @{
00111   */
00112 #define LL_CRS_SYNC_SOURCE_GPIO            0x00000000U             /*!< Synchro Signal soucre GPIO */
00113 #define LL_CRS_SYNC_SOURCE_LSE             CRS_CFGR_SYNCSRC_0      /*!< Synchro Signal source LSE */
00114 #define LL_CRS_SYNC_SOURCE_USB             CRS_CFGR_SYNCSRC_1      /*!< Synchro Signal source USB SOF (default)*/
00115 /**
00116   * @}
00117   */
00118
00119 /** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
00120   * @{
00121   */
00122 #define LL_CRS_SYNC_POLARITY_RISING        0x00000000U           /*!< Synchro Active on rising edge (default) */
00123 #define LL_CRS_SYNC_POLARITY_FALLING       CRS_CFGR_SYNCPOL      /*!< Synchro Active on falling edge */
00124 /**
00125   * @}
00126   */
00127
00128 /** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
00129   * @{
00130   */
00131 #define LL_CRS_FREQ_ERROR_DIR_UP             0x00000000U        /*!< Upcounting direction, the actual frequency is above the target */
00132 #define LL_CRS_FREQ_ERROR_DIR_DOWN           CRS_ISR_FEDIR      /*!< Downcounting direction, the actual frequency is below the target */
00133 /**
00134   * @}
00135   */
00136
00137 /** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
00138   * @{
00139   */
00140 /**
00141   * @brief Reset value of the RELOAD field
00142   * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
00143   *       and a synchronization signal frequency of 1 kHz (SOF signal from USB)
00144   */
00145 #define LL_CRS_RELOADVALUE_DEFAULT         0x0000BB7FU
00146
00147 /**
00148   * @brief Reset value of Frequency error limit.
00149   */
00150 #define LL_CRS_ERRORLIMIT_DEFAULT          0x00000022U
00151
00152 /**
00153   * @brief Reset value of the HSI48 Calibration field
00154   * @note The default value is 32, which corresponds to the middle of the trimming interval.
00155   *       The trimming step is around 67 kHz between two consecutive TRIM steps.
00156   *       A higher TRIM value corresponds to a higher output frequency
00157   */
00158 #define LL_CRS_HSI48CALIBRATION_DEFAULT    0x00000020U
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /* Exported macro ------------------------------------------------------------*/
00168 /** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
00169   * @{
00170   */
00171
00172 /** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
00173   * @{
00174   */
00175
00176 /**
00177   * @brief  Write a value in CRS register
00178   * @param  __INSTANCE__ CRS Instance
00179   * @param  __REG__ Register to be written
00180   * @param  __VALUE__ Value to be written in the register
00181   * @retval None
00182   */
00183 #define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00184
00185 /**
00186   * @brief  Read a value in CRS register
00187   * @param  __INSTANCE__ CRS Instance
00188   * @param  __REG__ Register to be read
00189   * @retval Register value
00190   */
00191 #define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00192 /**
00193   * @}
00194   */
00195
00196 /** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
00197   * @{
00198   */
00199
00200 /**
00201   * @brief  Macro to calculate reload value to be set in CRS register according to target and sync frequencies
00202   * @note   The RELOAD value should be selected according to the ratio between
00203   *         the target frequency and the frequency of the synchronization source after
00204   *         prescaling. It is then decreased by one in order to reach the expected
00205   *         synchronization on the zero value. The formula is the following:
00206   *              RELOAD = (fTARGET / fSYNC) -1
00207   * @param  __FTARGET__ Target frequency (value in Hz)
00208   * @param  __FSYNC__ Synchronization signal frequency (value in Hz)
00209   * @retval Reload value (in Hz)
00210   */
00211 #define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
00212
00213 /**
00214   * @}
00215   */
00216
00217 /**
00218   * @}
00219   */
00220
00221 /* Exported functions --------------------------------------------------------*/
00222 /** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
00223   * @{
00224   */
00225
00226 /** @defgroup CRS_LL_EF_Configuration Configuration
00227   * @{
00228   */
00229
00230 /**
00231   * @brief  Enable Frequency error counter
00232   * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
00233   * @rmtoll CR           CEN           LL_CRS_EnableFreqErrorCounter
00234   * @retval None
00235   */
00236 __STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
00237 {
00238   SET_BIT(CRS->CR, CRS_CR_CEN);
00239 }
00240
00241 /**
00242   * @brief  Disable Frequency error counter
00243   * @rmtoll CR           CEN           LL_CRS_DisableFreqErrorCounter
00244   * @retval None
00245   */
00246 __STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
00247 {
00248   CLEAR_BIT(CRS->CR, CRS_CR_CEN);
00249 }
00250
00251 /**
00252   * @brief  Check if Frequency error counter is enabled or not
00253   * @rmtoll CR           CEN           LL_CRS_IsEnabledFreqErrorCounter
00254   * @retval State of bit (1 or 0).
00255   */
00256 __STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
00257 {
00258   return ((READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)) ? 1UL : 0UL);
00259 }
00260
00261 /**
00262   * @brief  Enable Automatic trimming counter
00263   * @rmtoll CR           AUTOTRIMEN    LL_CRS_EnableAutoTrimming
00264   * @retval None
00265   */
00266 __STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
00267 {
00268   SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
00269 }
00270
00271 /**
00272   * @brief  Disable Automatic trimming counter
00273   * @rmtoll CR           AUTOTRIMEN    LL_CRS_DisableAutoTrimming
00274   * @retval None
00275   */
00276 __STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
00277 {
00278   CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
00279 }
00280
00281 /**
00282   * @brief  Check if Automatic trimming is enabled or not
00283   * @rmtoll CR           AUTOTRIMEN    LL_CRS_IsEnabledAutoTrimming
00284   * @retval State of bit (1 or 0).
00285   */
00286 __STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
00287 {
00288   return ((READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)) ? 1UL : 0UL);
00289 }
00290
00291 /**
00292   * @brief  Set HSI48 oscillator smooth trimming
00293   * @note   When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
00294   * @rmtoll CR           TRIM          LL_CRS_SetHSI48SmoothTrimming
00295   * @param  Value a number between Min_Data = 0 and Max_Data = 63
00296   * @note   Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
00297   * @retval None
00298   */
00299 __STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
00300 {
00301   MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_POSITION_TRIM);
00302 }
00303
00304 /**
00305   * @brief  Get HSI48 oscillator smooth trimming
00306   * @rmtoll CR           TRIM          LL_CRS_GetHSI48SmoothTrimming
00307   * @retval a number between Min_Data = 0 and Max_Data = 63
00308   */
00309 __STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
00310 {
00311   return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_POSITION_TRIM);
00312 }
00313
00314 /**
00315   * @brief  Set counter reload value
00316   * @rmtoll CFGR         RELOAD        LL_CRS_SetReloadCounter
00317   * @param  Value a number between Min_Data = 0 and Max_Data = 0xFFFF
00318   * @note   Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
00319   *         Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
00320   * @retval None
00321   */
00322 __STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
00323 {
00324   MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
00325 }
00326
00327 /**
00328   * @brief  Get counter reload value
00329   * @rmtoll CFGR         RELOAD        LL_CRS_GetReloadCounter
00330   * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
00331   */
00332 __STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
00333 {
00334   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
00335 }
00336
00337 /**
00338   * @brief  Set frequency error limit
00339   * @rmtoll CFGR         FELIM         LL_CRS_SetFreqErrorLimit
00340   * @param  Value a number between Min_Data = 0 and Max_Data = 255
00341   * @note   Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
00342   * @retval None
00343   */
00344 __STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
00345 {
00346   MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_POSITION_FELIM);
00347 }
00348
00349 /**
00350   * @brief  Get frequency error limit
00351   * @rmtoll CFGR         FELIM         LL_CRS_GetFreqErrorLimit
00352   * @retval A number between Min_Data = 0 and Max_Data = 255
00353   */
00354 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
00355 {
00356   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_POSITION_FELIM);
00357 }
00358
00359 /**
00360   * @brief  Set division factor for SYNC signal
00361   * @rmtoll CFGR         SYNCDIV       LL_CRS_SetSyncDivider
00362   * @param  Divider This parameter can be one of the following values:
00363   *         @arg @ref LL_CRS_SYNC_DIV_1
00364   *         @arg @ref LL_CRS_SYNC_DIV_2
00365   *         @arg @ref LL_CRS_SYNC_DIV_4
00366   *         @arg @ref LL_CRS_SYNC_DIV_8
00367   *         @arg @ref LL_CRS_SYNC_DIV_16
00368   *         @arg @ref LL_CRS_SYNC_DIV_32
00369   *         @arg @ref LL_CRS_SYNC_DIV_64
00370   *         @arg @ref LL_CRS_SYNC_DIV_128
00371   * @retval None
00372   */
00373 __STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
00374 {
00375   MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
00376 }
00377
00378 /**
00379   * @brief  Get division factor for SYNC signal
00380   * @rmtoll CFGR         SYNCDIV       LL_CRS_GetSyncDivider
00381   * @retval Returned value can be one of the following values:
00382   *         @arg @ref LL_CRS_SYNC_DIV_1
00383   *         @arg @ref LL_CRS_SYNC_DIV_2
00384   *         @arg @ref LL_CRS_SYNC_DIV_4
00385   *         @arg @ref LL_CRS_SYNC_DIV_8
00386   *         @arg @ref LL_CRS_SYNC_DIV_16
00387   *         @arg @ref LL_CRS_SYNC_DIV_32
00388   *         @arg @ref LL_CRS_SYNC_DIV_64
00389   *         @arg @ref LL_CRS_SYNC_DIV_128
00390   */
00391 __STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
00392 {
00393   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
00394 }
00395
00396 /**
00397   * @brief  Set SYNC signal source
00398   * @rmtoll CFGR         SYNCSRC       LL_CRS_SetSyncSignalSource
00399   * @param  Source This parameter can be one of the following values:
00400   *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO
00401   *         @arg @ref LL_CRS_SYNC_SOURCE_LSE
00402   *         @arg @ref LL_CRS_SYNC_SOURCE_USB
00403   * @retval None
00404   */
00405 __STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
00406 {
00407   MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
00408 }
00409
00410 /**
00411   * @brief  Get SYNC signal source
00412   * @rmtoll CFGR         SYNCSRC       LL_CRS_GetSyncSignalSource
00413   * @retval Returned value can be one of the following values:
00414   *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO
00415   *         @arg @ref LL_CRS_SYNC_SOURCE_LSE
00416   *         @arg @ref LL_CRS_SYNC_SOURCE_USB
00417   */
00418 __STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
00419 {
00420   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
00421 }
00422
00423 /**
00424   * @brief  Set input polarity for the SYNC signal source
00425   * @rmtoll CFGR         SYNCPOL       LL_CRS_SetSyncPolarity
00426   * @param  Polarity This parameter can be one of the following values:
00427   *         @arg @ref LL_CRS_SYNC_POLARITY_RISING
00428   *         @arg @ref LL_CRS_SYNC_POLARITY_FALLING
00429   * @retval None
00430   */
00431 __STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
00432 {
00433   MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
00434 }
00435
00436 /**
00437   * @brief  Get input polarity for the SYNC signal source
00438   * @rmtoll CFGR         SYNCPOL       LL_CRS_GetSyncPolarity
00439   * @retval Returned value can be one of the following values:
00440   *         @arg @ref LL_CRS_SYNC_POLARITY_RISING
00441   *         @arg @ref LL_CRS_SYNC_POLARITY_FALLING
00442   */
00443 __STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
00444 {
00445   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
00446 }
00447
00448 /**
00449   * @brief  Configure CRS for the synchronization
00450   * @rmtoll CR           TRIM          LL_CRS_ConfigSynchronization\n
00451   *         CFGR         RELOAD        LL_CRS_ConfigSynchronization\n
00452   *         CFGR         FELIM         LL_CRS_ConfigSynchronization\n
00453   *         CFGR         SYNCDIV       LL_CRS_ConfigSynchronization\n
00454   *         CFGR         SYNCSRC       LL_CRS_ConfigSynchronization\n
00455   *         CFGR         SYNCPOL       LL_CRS_ConfigSynchronization
00456   * @param  HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
00457   * @param  ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
00458   * @param  ReloadValue a number between Min_Data = 0 and Max_Data = 255
00459   * @param  Settings This parameter can be a combination of the following values:
00460   *         @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
00461   *              or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
00462   *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
00463   *         @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
00464   * @retval None
00465   */
00466 __STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
00467 {
00468   MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue);
00469   MODIFY_REG(CRS->CFGR,
00470              CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
00471              ReloadValue | (ErrorLimitValue << CRS_POSITION_FELIM) | Settings);
00472 }
00473
00474 /**
00475   * @}
00476   */
00477
00478 /** @defgroup CRS_LL_EF_CRS_Management CRS_Management
00479   * @{
00480   */
00481
00482 /**
00483   * @brief  Generate software SYNC event
00484   * @rmtoll CR           SWSYNC        LL_CRS_GenerateEvent_SWSYNC
00485   * @retval None
00486   */
00487 __STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
00488 {
00489   SET_BIT(CRS->CR, CRS_CR_SWSYNC);
00490 }
00491
00492 /**
00493   * @brief  Get the frequency error direction latched in the time of the last
00494   * SYNC event
00495   * @rmtoll ISR          FEDIR         LL_CRS_GetFreqErrorDirection
00496   * @retval Returned value can be one of the following values:
00497   *         @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
00498   *         @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
00499   */
00500 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
00501 {
00502   return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
00503 }
00504
00505 /**
00506   * @brief  Get the frequency error counter value latched in the time of the last SYNC event
00507   * @rmtoll ISR          FECAP         LL_CRS_GetFreqErrorCapture
00508   * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
00509   */
00510 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
00511 {
00512   return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_POSITION_FECAP);
00513 }
00514
00515 /**
00516   * @}
00517   */
00518
00519 /** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
00520   * @{
00521   */
00522
00523 /**
00524   * @brief  Check if SYNC event OK signal occurred or not
00525   * @rmtoll ISR          SYNCOKF       LL_CRS_IsActiveFlag_SYNCOK
00526   * @retval State of bit (1 or 0).
00527   */
00528 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
00529 {
00530   return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)) ? 1UL : 0UL);
00531 }
00532
00533 /**
00534   * @brief  Check if SYNC warning signal occurred or not
00535   * @rmtoll ISR          SYNCWARNF     LL_CRS_IsActiveFlag_SYNCWARN
00536   * @retval State of bit (1 or 0).
00537   */
00538 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
00539 {
00540   return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)) ? 1UL : 0UL);
00541 }
00542
00543 /**
00544   * @brief  Check if Synchronization or trimming error signal occurred or not
00545   * @rmtoll ISR          ERRF          LL_CRS_IsActiveFlag_ERR
00546   * @retval State of bit (1 or 0).
00547   */
00548 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
00549 {
00550   return ((READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)) ? 1UL : 0UL);
00551 }
00552
00553 /**
00554   * @brief  Check if Expected SYNC signal occurred or not
00555   * @rmtoll ISR          ESYNCF        LL_CRS_IsActiveFlag_ESYNC
00556   * @retval State of bit (1 or 0).
00557   */
00558 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
00559 {
00560   return ((READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)) ? 1UL : 0UL);
00561 }
00562
00563 /**
00564   * @brief  Check if SYNC error signal occurred or not
00565   * @rmtoll ISR          SYNCERR       LL_CRS_IsActiveFlag_SYNCERR
00566   * @retval State of bit (1 or 0).
00567   */
00568 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
00569 {
00570   return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)) ? 1UL : 0UL);
00571 }
00572
00573 /**
00574   * @brief  Check if SYNC missed error signal occurred or not
00575   * @rmtoll ISR          SYNCMISS      LL_CRS_IsActiveFlag_SYNCMISS
00576   * @retval State of bit (1 or 0).
00577   */
00578 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
00579 {
00580   return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)) ? 1UL : 0UL);
00581 }
00582
00583 /**
00584   * @brief  Check if Trimming overflow or underflow occurred or not
00585   * @rmtoll ISR          TRIMOVF       LL_CRS_IsActiveFlag_TRIMOVF
00586   * @retval State of bit (1 or 0).
00587   */
00588 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
00589 {
00590   return ((READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)) ? 1UL : 0UL);
00591 }
00592
00593 /**
00594   * @brief  Clear the SYNC event OK flag
00595   * @rmtoll ICR          SYNCOKC       LL_CRS_ClearFlag_SYNCOK
00596   * @retval None
00597   */
00598 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
00599 {
00600   WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
00601 }
00602
00603 /**
00604   * @brief  Clear the  SYNC warning flag
00605   * @rmtoll ICR          SYNCWARNC     LL_CRS_ClearFlag_SYNCWARN
00606   * @retval None
00607   */
00608 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
00609 {
00610   WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
00611 }
00612
00613 /**
00614   * @brief  Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
00615   * the ERR flag
00616   * @rmtoll ICR          ERRC          LL_CRS_ClearFlag_ERR
00617   * @retval None
00618   */
00619 __STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
00620 {
00621   WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
00622 }
00623
00624 /**
00625   * @brief  Clear Expected SYNC flag
00626   * @rmtoll ICR          ESYNCC        LL_CRS_ClearFlag_ESYNC
00627   * @retval None
00628   */
00629 __STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
00630 {
00631   WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
00632 }
00633
00634 /**
00635   * @}
00636   */
00637
00638 /** @defgroup CRS_LL_EF_IT_Management IT_Management
00639   * @{
00640   */
00641
00642 /**
00643   * @brief  Enable SYNC event OK interrupt
00644   * @rmtoll CR           SYNCOKIE      LL_CRS_EnableIT_SYNCOK
00645   * @retval None
00646   */
00647 __STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
00648 {
00649   SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
00650 }
00651
00652 /**
00653   * @brief  Disable SYNC event OK interrupt
00654   * @rmtoll CR           SYNCOKIE      LL_CRS_DisableIT_SYNCOK
00655   * @retval None
00656   */
00657 __STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
00658 {
00659   CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
00660 }
00661
00662 /**
00663   * @brief  Check if SYNC event OK interrupt is enabled or not
00664   * @rmtoll CR           SYNCOKIE      LL_CRS_IsEnabledIT_SYNCOK
00665   * @retval State of bit (1 or 0).
00666   */
00667 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
00668 {
00669   return ((READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)) ? 1UL : 0UL);
00670 }
00671
00672 /**
00673   * @brief  Enable SYNC warning interrupt
00674   * @rmtoll CR           SYNCWARNIE    LL_CRS_EnableIT_SYNCWARN
00675   * @retval None
00676   */
00677 __STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
00678 {
00679   SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
00680 }
00681
00682 /**
00683   * @brief  Disable SYNC warning interrupt
00684   * @rmtoll CR           SYNCWARNIE    LL_CRS_DisableIT_SYNCWARN
00685   * @retval None
00686   */
00687 __STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
00688 {
00689   CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
00690 }
00691
00692 /**
00693   * @brief  Check if SYNC warning interrupt is enabled or not
00694   * @rmtoll CR           SYNCWARNIE    LL_CRS_IsEnabledIT_SYNCWARN
00695   * @retval State of bit (1 or 0).
00696   */
00697 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
00698 {
00699   return ((READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)) ? 1UL : 0UL);
00700 }
00701
00702 /**
00703   * @brief  Enable Synchronization or trimming error interrupt
00704   * @rmtoll CR           ERRIE         LL_CRS_EnableIT_ERR
00705   * @retval None
00706   */
00707 __STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
00708 {
00709   SET_BIT(CRS->CR, CRS_CR_ERRIE);
00710 }
00711
00712 /**
00713   * @brief  Disable Synchronization or trimming error interrupt
00714   * @rmtoll CR           ERRIE         LL_CRS_DisableIT_ERR
00715   * @retval None
00716   */
00717 __STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
00718 {
00719   CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
00720 }
00721
00722 /**
00723   * @brief  Check if Synchronization or trimming error interrupt is enabled or not
00724   * @rmtoll CR           ERRIE         LL_CRS_IsEnabledIT_ERR
00725   * @retval State of bit (1 or 0).
00726   */
00727 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
00728 {
00729   return ((READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)) ? 1UL : 0UL);
00730 }
00731
00732 /**
00733   * @brief  Enable Expected SYNC interrupt
00734   * @rmtoll CR           ESYNCIE       LL_CRS_EnableIT_ESYNC
00735   * @retval None
00736   */
00737 __STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
00738 {
00739   SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
00740 }
00741
00742 /**
00743   * @brief  Disable Expected SYNC interrupt
00744   * @rmtoll CR           ESYNCIE       LL_CRS_DisableIT_ESYNC
00745   * @retval None
00746   */
00747 __STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
00748 {
00749   CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
00750 }
00751
00752 /**
00753   * @brief  Check if Expected SYNC interrupt is enabled or not
00754   * @rmtoll CR           ESYNCIE       LL_CRS_IsEnabledIT_ESYNC
00755   * @retval State of bit (1 or 0).
00756   */
00757 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
00758 {
00759   return ((READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)) ? 1UL : 0UL);
00760 }
00761
00762 /**
00763   * @}
00764   */
00765
00766 #if defined(USE_FULL_LL_DRIVER)
00767 /** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
00768   * @{
00769   */
00770
00771 ErrorStatus LL_CRS_DeInit(void);
00772
00773 /**
00774   * @}
00775   */
00776 #endif /* USE_FULL_LL_DRIVER */
00777
00778 /**
00779   * @}
00780   */
00781
00782 /**
00783   * @}
00784   */
00785
00786 #endif /* defined(CRS) */
00787
00788 /**
00789   * @}
00790   */
00791
00792 #ifdef __cplusplus
00793 }
00794 #endif
00795
00796 #endif /* STM32WBxx_LL_CRS_H */
00797
00798 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_dma.c Source File

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stm32wbxx_ll_dma.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_dma.c
00004   * @author  MCD Application Team
00005   * @brief   DMA LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32wbxx_ll_dma.h"
00023 #include "stm32wbxx_ll_bus.h"
00024 #ifdef  USE_FULL_ASSERT
00025 #include "stm32_assert.h"
00026 #else
00027 #define assert_param(expr) ((void)0U)
00028 #endif
00029
00030 /** @addtogroup STM32WBxx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (DMA1) || defined (DMA2)
00035
00036 /** @defgroup DMA_LL DMA
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /* Private macros ------------------------------------------------------------*/
00044 /** @addtogroup DMA_LL_Private_Macros
00045   * @{
00046   */
00047 #define IS_LL_DMA_DIRECTION(__VALUE__)          (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
00048                                                  ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
00049                                                  ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
00050
00051 #define IS_LL_DMA_MODE(__VALUE__)               (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
00052                                                  ((__VALUE__) == LL_DMA_MODE_CIRCULAR))
00053
00054 #define IS_LL_DMA_PERIPHINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
00055                                                  ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
00056
00057 #define IS_LL_DMA_MEMORYINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
00058                                                  ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
00059
00060 #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE)      || \
00061                                                  ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD)  || \
00062                                                  ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
00063
00064 #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE)      || \
00065                                                  ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD)  || \
00066                                                  ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
00067
00068 #define IS_LL_DMA_NBDATA(__VALUE__)             ((__VALUE__)  <= 0x0000FFFFU)
00069
00070 #define IS_LL_DMA_PERIPHREQUEST(__VALUE__)      ((__VALUE__) <= 40U)
00071
00072 #define IS_LL_DMA_PRIORITY(__VALUE__)           (((__VALUE__) == LL_DMA_PRIORITY_LOW)    || \
00073                                                  ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
00074                                                  ((__VALUE__) == LL_DMA_PRIORITY_HIGH)   || \
00075                                                  ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
00076
00077 #if defined (DMA2)
00078 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
00079 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
00080                                                          (((CHANNEL) == LL_DMA_CHANNEL_1) || \
00081                                                           ((CHANNEL) == LL_DMA_CHANNEL_2) || \
00082                                                           ((CHANNEL) == LL_DMA_CHANNEL_3) || \
00083                                                           ((CHANNEL) == LL_DMA_CHANNEL_4) || \
00084                                                           ((CHANNEL) == LL_DMA_CHANNEL_5) || \
00085                                                           ((CHANNEL) == LL_DMA_CHANNEL_6) || \
00086                                                           ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
00087                                                          (((INSTANCE) == DMA2) && \
00088                                                          (((CHANNEL) == LL_DMA_CHANNEL_1) || \
00089                                                           ((CHANNEL) == LL_DMA_CHANNEL_2) || \
00090                                                           ((CHANNEL) == LL_DMA_CHANNEL_3) || \
00091                                                           ((CHANNEL) == LL_DMA_CHANNEL_4) || \
00092                                                           ((CHANNEL) == LL_DMA_CHANNEL_5) || \
00093                                                           ((CHANNEL) == LL_DMA_CHANNEL_6) || \
00094                                                           ((CHANNEL) == LL_DMA_CHANNEL_7))))
00095 #else
00096 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
00097                                                          (((CHANNEL) == LL_DMA_CHANNEL_1) || \
00098                                                           ((CHANNEL) == LL_DMA_CHANNEL_2) || \
00099                                                           ((CHANNEL) == LL_DMA_CHANNEL_3) || \
00100                                                           ((CHANNEL) == LL_DMA_CHANNEL_4) || \
00101                                                           ((CHANNEL) == LL_DMA_CHANNEL_5) || \
00102                                                           ((CHANNEL) == LL_DMA_CHANNEL_6) || \
00103                                                           ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
00104                                                          (((INSTANCE) == DMA2) && \
00105                                                          (((CHANNEL) == LL_DMA_CHANNEL_1) || \
00106                                                           ((CHANNEL) == LL_DMA_CHANNEL_2) || \
00107                                                           ((CHANNEL) == LL_DMA_CHANNEL_3) || \
00108                                                           ((CHANNEL) == LL_DMA_CHANNEL_4) || \
00109                                                           ((CHANNEL) == LL_DMA_CHANNEL_5))))
00110 #endif
00111 #else
00112 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
00113                                                             (((CHANNEL) == LL_DMA_CHANNEL_1)|| \
00114                                                             ((CHANNEL) == LL_DMA_CHANNEL_2) || \
00115                                                             ((CHANNEL) == LL_DMA_CHANNEL_3) || \
00116                                                             ((CHANNEL) == LL_DMA_CHANNEL_4) || \
00117                                                             ((CHANNEL) == LL_DMA_CHANNEL_5) || \
00118                                                             ((CHANNEL) == LL_DMA_CHANNEL_6) || \
00119                                                             ((CHANNEL) == LL_DMA_CHANNEL_7))))
00120 #endif
00121 /**
00122   * @}
00123   */
00124
00125 /* Private function prototypes -----------------------------------------------*/
00126
00127 /* Exported functions --------------------------------------------------------*/
00128 /** @addtogroup DMA_LL_Exported_Functions
00129   * @{
00130   */
00131
00132 /** @addtogroup DMA_LL_EF_Init
00133   * @{
00134   */
00135
00136 /**
00137   * @brief  De-initialize the DMA registers to their default reset values.
00138   * @param  DMAx DMAx Instance
00139   * @param  Channel This parameter can be one of the following values:
00140   *         @arg @ref LL_DMA_CHANNEL_1
00141   *         @arg @ref LL_DMA_CHANNEL_2
00142   *         @arg @ref LL_DMA_CHANNEL_3
00143   *         @arg @ref LL_DMA_CHANNEL_4
00144   *         @arg @ref LL_DMA_CHANNEL_5
00145   *         @arg @ref LL_DMA_CHANNEL_6
00146   *         @arg @ref LL_DMA_CHANNEL_7
00147   *         @arg @ref LL_DMA_CHANNEL_ALL
00148   * @retval An ErrorStatus enumeration value:
00149   *          - SUCCESS: DMA registers are de-initialized
00150   *          - ERROR: DMA registers are not de-initialized
00151   */
00152 ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
00153 {
00154   DMA_Channel_TypeDef *tmp;
00155   ErrorStatus status = SUCCESS;
00156
00157   /* Check the DMA Instance DMAx and Channel parameters*/
00158   assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel) || (Channel == LL_DMA_CHANNEL_ALL));
00159
00160   if (Channel == LL_DMA_CHANNEL_ALL)
00161   {
00162     if (DMAx == DMA1)
00163     {
00164       /* Force reset of DMA clock */
00165       LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
00166
00167       /* Release reset of DMA clock */
00168       LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
00169     }
00170 #if defined(DMA2)
00171     else if (DMAx == DMA2)
00172     {
00173       /* Force reset of DMA clock */
00174       LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
00175
00176       /* Release reset of DMA clock */
00177       LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
00178     }
00179 #endif
00180     else
00181     {
00182       status = ERROR;
00183     }
00184   }
00185   else
00186   {
00187     tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
00188
00189     /* Reset DMAx_Channely control register */
00190     WRITE_REG(tmp->CCR, 0U);
00191
00192     /* Reset DMAx_Channely remaining bytes register */
00193     WRITE_REG(tmp->CNDTR, 0U);
00194
00195     /* Reset DMAx_Channely peripheral address register */
00196     WRITE_REG(tmp->CPAR, 0U);
00197
00198     /* Reset DMAx_Channely memory address register */
00199     WRITE_REG(tmp->CMAR, 0U);
00200
00201     /* Reset Request register field for DMAx Channel */
00202     LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMAMUX_REQ_MEM2MEM);
00203
00204     if (Channel == LL_DMA_CHANNEL_1)
00205     {
00206       /* Reset interrupt pending bits for DMAx Channel1 */
00207       LL_DMA_ClearFlag_GI1(DMAx);
00208     }
00209     else if (Channel == LL_DMA_CHANNEL_2)
00210     {
00211       /* Reset interrupt pending bits for DMAx Channel2 */
00212       LL_DMA_ClearFlag_GI2(DMAx);
00213     }
00214     else if (Channel == LL_DMA_CHANNEL_3)
00215     {
00216       /* Reset interrupt pending bits for DMAx Channel3 */
00217       LL_DMA_ClearFlag_GI3(DMAx);
00218     }
00219     else if (Channel == LL_DMA_CHANNEL_4)
00220     {
00221       /* Reset interrupt pending bits for DMAx Channel4 */
00222       LL_DMA_ClearFlag_GI4(DMAx);
00223     }
00224     else if (Channel == LL_DMA_CHANNEL_5)
00225     {
00226       /* Reset interrupt pending bits for DMAx Channel5 */
00227       LL_DMA_ClearFlag_GI5(DMAx);
00228     }
00229
00230     else if (Channel == LL_DMA_CHANNEL_6)
00231     {
00232       /* Reset interrupt pending bits for DMAx Channel6 */
00233       LL_DMA_ClearFlag_GI6(DMAx);
00234     }
00235     else if (Channel == LL_DMA_CHANNEL_7)
00236     {
00237       /* Reset interrupt pending bits for DMAx Channel7 */
00238       LL_DMA_ClearFlag_GI7(DMAx);
00239     }
00240     else
00241     {
00242       status = ERROR;
00243     }
00244   }
00245
00246   return status;
00247 }
00248
00249 /**
00250   * @brief  Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
00251   * @note   To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
00252   *         @arg @ref __LL_DMA_GET_INSTANCE
00253   *         @arg @ref __LL_DMA_GET_CHANNEL
00254   * @param  DMAx DMAx Instance
00255   * @param  Channel This parameter can be one of the following values:
00256   *         @arg @ref LL_DMA_CHANNEL_1
00257   *         @arg @ref LL_DMA_CHANNEL_2
00258   *         @arg @ref LL_DMA_CHANNEL_3
00259   *         @arg @ref LL_DMA_CHANNEL_4
00260   *         @arg @ref LL_DMA_CHANNEL_5
00261   *         @arg @ref LL_DMA_CHANNEL_6
00262   *         @arg @ref LL_DMA_CHANNEL_7
00263   * @param  DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
00264   * @retval An ErrorStatus enumeration value:
00265   *          - SUCCESS: DMA registers are initialized
00266   *          - ERROR: Not applicable
00267   */
00268 ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
00269 {
00270   /* Check the DMA Instance DMAx and Channel parameters*/
00271   assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
00272
00273   /* Check the DMA parameters from DMA_InitStruct */
00274   assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
00275   assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
00276   assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
00277   assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
00278   assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
00279   assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
00280   assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
00281   assert_param(IS_LL_DMA_PERIPHREQUEST(DMA_InitStruct->PeriphRequest));
00282   assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
00283
00284   /*---------------------------- DMAx CCR Configuration ------------------------
00285    * Configure DMAx_Channely: data transfer direction, data transfer mode,
00286    *                          peripheral and memory increment mode,
00287    *                          data size alignment and  priority level with parameters :
00288    * - Direction:      DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
00289    * - Mode:           DMA_CCR_CIRC bit
00290    * - PeriphOrM2MSrcIncMode:  DMA_CCR_PINC bit
00291    * - MemoryOrM2MDstIncMode:  DMA_CCR_MINC bit
00292    * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
00293    * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
00294    * - Priority:               DMA_CCR_PL[1:0] bits
00295    */
00296   LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction              | \
00297                         DMA_InitStruct->Mode                   | \
00298                         DMA_InitStruct->PeriphOrM2MSrcIncMode  | \
00299                         DMA_InitStruct->MemoryOrM2MDstIncMode  | \
00300                         DMA_InitStruct->PeriphOrM2MSrcDataSize | \
00301                         DMA_InitStruct->MemoryOrM2MDstDataSize | \
00302                         DMA_InitStruct->Priority);
00303
00304   /*-------------------------- DMAx CMAR Configuration -------------------------
00305    * Configure the memory or destination base address with parameter :
00306    * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
00307    */
00308   LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
00309
00310   /*-------------------------- DMAx CPAR Configuration -------------------------
00311    * Configure the peripheral or source base address with parameter :
00312    * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
00313    */
00314   LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
00315
00316   /*--------------------------- DMAx CNDTR Configuration -----------------------
00317    * Configure the peripheral base address with parameter :
00318    * - NbData: DMA_CNDTR_NDT[15:0] bits
00319    */
00320   LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
00321
00322   /*--------------------------- DMAMUXx CCR Configuration ----------------------
00323    * Configure the DMA request for DMA Channels on DMAMUX Channel x with parameter :
00324    * - PeriphRequest: DMA_CxCR[7:0] bits
00325    */
00326   LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest);
00327
00328   return SUCCESS;
00329 }
00330
00331 /**
00332   * @brief  Set each @ref LL_DMA_InitTypeDef field to default value.
00333   * @param  DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
00334   * @retval None
00335   */
00336 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
00337 {
00338   /* Set DMA_InitStruct fields to default values */
00339   DMA_InitStruct->PeriphOrM2MSrcAddress  = 0x00000000U;
00340   DMA_InitStruct->MemoryOrM2MDstAddress  = 0x00000000U;
00341   DMA_InitStruct->Direction              = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
00342   DMA_InitStruct->Mode                   = LL_DMA_MODE_NORMAL;
00343   DMA_InitStruct->PeriphOrM2MSrcIncMode  = LL_DMA_PERIPH_NOINCREMENT;
00344   DMA_InitStruct->MemoryOrM2MDstIncMode  = LL_DMA_MEMORY_NOINCREMENT;
00345   DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
00346   DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
00347   DMA_InitStruct->NbData                 = 0x00000000U;
00348   DMA_InitStruct->PeriphRequest          = LL_DMAMUX_REQ_MEM2MEM;
00349   DMA_InitStruct->Priority               = LL_DMA_PRIORITY_LOW;
00350 }
00351
00352 /**
00353   * @}
00354   */
00355
00356 /**
00357   * @}
00358   */
00359
00360 /**
00361   * @}
00362   */
00363
00364 #endif /* DMA1 || DMA2 */
00365
00366 /**
00367   * @}
00368   */
00369
00370 #endif /* USE_FULL_LL_DRIVER */
00371
00372 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_dma.h Source File

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stm32wbxx_ll_dma.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_dma.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DMA LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_LL_DMA_H
00022 #define STM32WBxx_LL_DMA_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx.h"
00030 #include "stm32wbxx_ll_dmamux.h"
00031
00032 /** @addtogroup STM32WBxx_LL_Driver
00033   * @{
00034   */
00035
00036 #if defined (DMA1) || defined (DMA2)
00037
00038 /** @defgroup DMA_LL DMA
00039   * @{
00040   */
00041
00042 /* Private types -------------------------------------------------------------*/
00043 /* Private variables ---------------------------------------------------------*/
00044 /* Private constants ---------------------------------------------------------*/
00045 /* Private macros ------------------------------------------------------------*/
00046 /** @defgroup DMA_LL_Private_Macros DMA Private Macros
00047   * @{
00048   */
00049
00050 /**
00051   * @brief  Helper macro to convert DMA Instance and index into DMA channel
00052   * @param  __DMA_INSTANCE__ DMAx
00053   * @param  __CHANNEL_INDEX__ 0 to 6 to map DMAx_Channel1 to DMAx_Channel7
00054   * @retval Pointer to the DMA channel
00055   */
00056 #if defined (DMA2)
00057 #define __LL_DMA_INSTANCE_TO_CHANNEL(__DMA_INSTANCE__, __CHANNEL_INDEX__)   \
00058 (((__DMA_INSTANCE__) == DMA1) ? (DMA1_Channel1 + (__CHANNEL_INDEX__)) : (DMA2_Channel1 + (__CHANNEL_INDEX__)))
00059 #else
00060 #define __LL_DMA_INSTANCE_TO_CHANNEL(__DMA_INSTANCE__, __CHANNEL_INDEX__)   \
00061 (DMA1_Channel1 + (__CHANNEL_INDEX__))
00062 #endif
00063
00064 /**
00065   * @brief  Helper macro to convert DMA Instance and index into DMAMUX channel
00066   * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
00067 #if defined (DMA2)
00068   *         DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7.
00069 #endif
00070   * @param  __DMA_INSTANCE__ DMAx
00071   * @param  __CHANNEL_INDEX__ 0 to 6 to map DMAx_Channel1 to DMAx_Channel7
00072   * @retval Pointer to the DMA channel
00073   */
00074 #if defined (DMA2)
00075 #define __LL_DMA_INSTANCE_TO_DMAMUX_CCR(__DMA_INSTANCE__, __CHANNEL_INDEX__)\
00076 (((__DMA_INSTANCE__) == DMA1) ? (DMAMUX1_Channel0 + (__CHANNEL_INDEX__)) : (DMAMUX1_Channel7 + (__CHANNEL_INDEX__)))
00077 #else
00078 #define __LL_DMA_INSTANCE_TO_DMAMUX_CCR(__DMA_INSTANCE__, __CHANNEL_INDEX__)\
00079 (DMAMUX1_Channel0 + (__CHANNEL_INDEX__))
00080 #endif
00081 /**
00082   * @}
00083   */
00084
00085 /* Exported types ------------------------------------------------------------*/
00086 #if defined(USE_FULL_LL_DRIVER)
00087 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
00088   * @{
00089   */
00090 typedef struct
00091 {
00092   uint32_t PeriphOrM2MSrcAddress;  /*!< Specifies the peripheral base address for DMA transfer
00093                                         or as Source base address in case of memory to memory transfer direction.
00094
00095                                         This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
00096
00097   uint32_t MemoryOrM2MDstAddress;  /*!< Specifies the memory base address for DMA transfer
00098                                         or as Destination base address in case of memory to memory transfer direction.
00099
00100                                         This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
00101
00102   uint32_t Direction;              /*!< Specifies if the data will be transferred from memory to peripheral,
00103                                         from memory to memory or from peripheral to memory.
00104                                         This parameter can be a value of @ref DMA_LL_EC_DIRECTION
00105
00106                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
00107
00108   uint32_t Mode;                   /*!< Specifies the normal or circular operation mode.
00109                                         This parameter can be a value of @ref DMA_LL_EC_MODE
00110                                         @note: The circular buffer mode cannot be used if the memory to memory
00111                                                data transfer direction is configured on the selected Channel
00112
00113                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
00114
00115   uint32_t PeriphOrM2MSrcIncMode;  /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
00116                                         is incremented or not.
00117                                         This parameter can be a value of @ref DMA_LL_EC_PERIPH
00118
00119                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
00120
00121   uint32_t MemoryOrM2MDstIncMode;  /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
00122                                         is incremented or not.
00123                                         This parameter can be a value of @ref DMA_LL_EC_MEMORY
00124
00125                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
00126
00127   uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
00128                                         in case of memory to memory transfer direction.
00129                                         This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
00130
00131                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
00132
00133   uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
00134                                         in case of memory to memory transfer direction.
00135                                         This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
00136
00137                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
00138
00139   uint32_t NbData;                 /*!< Specifies the number of data to transfer, in data unit.
00140                                         The data unit is equal to the source buffer configuration set in PeripheralSize
00141                                         or MemorySize parameters depending in the transfer direction.
00142                                         This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
00143
00144                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
00145
00146   uint32_t PeriphRequest;          /*!< Specifies the peripheral request.
00147                                         This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST
00148
00149                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
00150
00151   uint32_t Priority;               /*!< Specifies the channel priority level.
00152                                         This parameter can be a value of @ref DMA_LL_EC_PRIORITY
00153
00154                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
00155
00156 } LL_DMA_InitTypeDef;
00157 /**
00158   * @}
00159   */
00160 #endif /*USE_FULL_LL_DRIVER*/
00161
00162 /* Exported constants --------------------------------------------------------*/
00163 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
00164   * @{
00165   */
00166 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
00167   * @brief    Flags defines which can be used with LL_DMA_WriteReg function
00168   * @{
00169   */
00170 #define LL_DMA_IFCR_CGIF1                 DMA_IFCR_CGIF1        /*!< Channel 1 global flag            */
00171 #define LL_DMA_IFCR_CTCIF1                DMA_IFCR_CTCIF1       /*!< Channel 1 transfer complete flag */
00172 #define LL_DMA_IFCR_CHTIF1                DMA_IFCR_CHTIF1       /*!< Channel 1 half transfer flag     */
00173 #define LL_DMA_IFCR_CTEIF1                DMA_IFCR_CTEIF1       /*!< Channel 1 transfer error flag    */
00174 #define LL_DMA_IFCR_CGIF2                 DMA_IFCR_CGIF2        /*!< Channel 2 global flag            */
00175 #define LL_DMA_IFCR_CTCIF2                DMA_IFCR_CTCIF2       /*!< Channel 2 transfer complete flag */
00176 #define LL_DMA_IFCR_CHTIF2                DMA_IFCR_CHTIF2       /*!< Channel 2 half transfer flag     */
00177 #define LL_DMA_IFCR_CTEIF2                DMA_IFCR_CTEIF2       /*!< Channel 2 transfer error flag    */
00178 #define LL_DMA_IFCR_CGIF3                 DMA_IFCR_CGIF3        /*!< Channel 3 global flag            */
00179 #define LL_DMA_IFCR_CTCIF3                DMA_IFCR_CTCIF3       /*!< Channel 3 transfer complete flag */
00180 #define LL_DMA_IFCR_CHTIF3                DMA_IFCR_CHTIF3       /*!< Channel 3 half transfer flag     */
00181 #define LL_DMA_IFCR_CTEIF3                DMA_IFCR_CTEIF3       /*!< Channel 3 transfer error flag    */
00182 #define LL_DMA_IFCR_CGIF4                 DMA_IFCR_CGIF4        /*!< Channel 4 global flag            */
00183 #define LL_DMA_IFCR_CTCIF4                DMA_IFCR_CTCIF4       /*!< Channel 4 transfer complete flag */
00184 #define LL_DMA_IFCR_CHTIF4                DMA_IFCR_CHTIF4       /*!< Channel 4 half transfer flag     */
00185 #define LL_DMA_IFCR_CTEIF4                DMA_IFCR_CTEIF4       /*!< Channel 4 transfer error flag    */
00186 #define LL_DMA_IFCR_CGIF5                 DMA_IFCR_CGIF5        /*!< Channel 5 global flag            */
00187 #define LL_DMA_IFCR_CTCIF5                DMA_IFCR_CTCIF5       /*!< Channel 5 transfer complete flag */
00188 #define LL_DMA_IFCR_CHTIF5                DMA_IFCR_CHTIF5       /*!< Channel 5 half transfer flag     */
00189 #define LL_DMA_IFCR_CTEIF5                DMA_IFCR_CTEIF5       /*!< Channel 5 transfer error flag    */
00190 #define LL_DMA_IFCR_CGIF6                 DMA_IFCR_CGIF6        /*!< Channel 6 global flag            */
00191 #define LL_DMA_IFCR_CTCIF6                DMA_IFCR_CTCIF6       /*!< Channel 6 transfer complete flag */
00192 #define LL_DMA_IFCR_CHTIF6                DMA_IFCR_CHTIF6       /*!< Channel 6 half transfer flag     */
00193 #define LL_DMA_IFCR_CTEIF6                DMA_IFCR_CTEIF6       /*!< Channel 6 transfer error flag    */
00194 #define LL_DMA_IFCR_CGIF7                 DMA_IFCR_CGIF7        /*!< Channel 7 global flag            */
00195 #define LL_DMA_IFCR_CTCIF7                DMA_IFCR_CTCIF7       /*!< Channel 7 transfer complete flag */
00196 #define LL_DMA_IFCR_CHTIF7                DMA_IFCR_CHTIF7       /*!< Channel 7 half transfer flag     */
00197 #define LL_DMA_IFCR_CTEIF7                DMA_IFCR_CTEIF7       /*!< Channel 7 transfer error flag    */
00198 /**
00199   * @}
00200   */
00201
00202 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
00203   * @brief    Flags defines which can be used with LL_DMA_ReadReg function
00204   * @{
00205   */
00206 #define LL_DMA_ISR_GIF1                   DMA_ISR_GIF1          /*!< Channel 1 global flag            */
00207 #define LL_DMA_ISR_TCIF1                  DMA_ISR_TCIF1         /*!< Channel 1 transfer complete flag */
00208 #define LL_DMA_ISR_HTIF1                  DMA_ISR_HTIF1         /*!< Channel 1 half transfer flag     */
00209 #define LL_DMA_ISR_TEIF1                  DMA_ISR_TEIF1         /*!< Channel 1 transfer error flag    */
00210 #define LL_DMA_ISR_GIF2                   DMA_ISR_GIF2          /*!< Channel 2 global flag            */
00211 #define LL_DMA_ISR_TCIF2                  DMA_ISR_TCIF2         /*!< Channel 2 transfer complete flag */
00212 #define LL_DMA_ISR_HTIF2                  DMA_ISR_HTIF2         /*!< Channel 2 half transfer flag     */
00213 #define LL_DMA_ISR_TEIF2                  DMA_ISR_TEIF2         /*!< Channel 2 transfer error flag    */
00214 #define LL_DMA_ISR_GIF3                   DMA_ISR_GIF3          /*!< Channel 3 global flag            */
00215 #define LL_DMA_ISR_TCIF3                  DMA_ISR_TCIF3         /*!< Channel 3 transfer complete flag */
00216 #define LL_DMA_ISR_HTIF3                  DMA_ISR_HTIF3         /*!< Channel 3 half transfer flag     */
00217 #define LL_DMA_ISR_TEIF3                  DMA_ISR_TEIF3         /*!< Channel 3 transfer error flag    */
00218 #define LL_DMA_ISR_GIF4                   DMA_ISR_GIF4          /*!< Channel 4 global flag            */
00219 #define LL_DMA_ISR_TCIF4                  DMA_ISR_TCIF4         /*!< Channel 4 transfer complete flag */
00220 #define LL_DMA_ISR_HTIF4                  DMA_ISR_HTIF4         /*!< Channel 4 half transfer flag     */
00221 #define LL_DMA_ISR_TEIF4                  DMA_ISR_TEIF4         /*!< Channel 4 transfer error flag    */
00222 #define LL_DMA_ISR_GIF5                   DMA_ISR_GIF5          /*!< Channel 5 global flag            */
00223 #define LL_DMA_ISR_TCIF5                  DMA_ISR_TCIF5         /*!< Channel 5 transfer complete flag */
00224 #define LL_DMA_ISR_HTIF5                  DMA_ISR_HTIF5         /*!< Channel 5 half transfer flag     */
00225 #define LL_DMA_ISR_TEIF5                  DMA_ISR_TEIF5         /*!< Channel 5 transfer error flag    */
00226 #define LL_DMA_ISR_GIF6                   DMA_ISR_GIF6          /*!< Channel 6 global flag            */
00227 #define LL_DMA_ISR_TCIF6                  DMA_ISR_TCIF6         /*!< Channel 6 transfer complete flag */
00228 #define LL_DMA_ISR_HTIF6                  DMA_ISR_HTIF6         /*!< Channel 6 half transfer flag     */
00229 #define LL_DMA_ISR_TEIF6                  DMA_ISR_TEIF6         /*!< Channel 6 transfer error flag    */
00230 #define LL_DMA_ISR_GIF7                   DMA_ISR_GIF7          /*!< Channel 7 global flag            */
00231 #define LL_DMA_ISR_TCIF7                  DMA_ISR_TCIF7         /*!< Channel 7 transfer complete flag */
00232 #define LL_DMA_ISR_HTIF7                  DMA_ISR_HTIF7         /*!< Channel 7 half transfer flag     */
00233 #define LL_DMA_ISR_TEIF7                  DMA_ISR_TEIF7         /*!< Channel 7 transfer error flag    */
00234 /**
00235   * @}
00236   */
00237
00238 /** @defgroup DMA_LL_EC_IT IT Defines
00239   * @brief    IT defines which can be used with LL_DMA_ReadReg and  LL_DMA_WriteReg functions
00240   * @{
00241   */
00242 #define LL_DMA_CCR_TCIE                   DMA_CCR_TCIE          /*!< Transfer complete interrupt */
00243 #define LL_DMA_CCR_HTIE                   DMA_CCR_HTIE          /*!< Half Transfer interrupt     */
00244 #define LL_DMA_CCR_TEIE                   DMA_CCR_TEIE          /*!< Transfer error interrupt    */
00245 /**
00246   * @}
00247   */
00248
00249 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
00250   * @{
00251   */
00252 #define LL_DMA_CHANNEL_1                  0x00000001U /*!< DMA Channel 1 */
00253 #define LL_DMA_CHANNEL_2                  0x00000002U /*!< DMA Channel 2 */
00254 #define LL_DMA_CHANNEL_3                  0x00000003U /*!< DMA Channel 3 */
00255 #define LL_DMA_CHANNEL_4                  0x00000004U /*!< DMA Channel 4 */
00256 #define LL_DMA_CHANNEL_5                  0x00000005U /*!< DMA Channel 5 */
00257 #define LL_DMA_CHANNEL_6                  0x00000006U /*!< DMA Channel 6 */
00258 #define LL_DMA_CHANNEL_7                  0x00000007U /*!< DMA Channel 7 */
00259 #if defined(USE_FULL_LL_DRIVER)
00260 #define LL_DMA_CHANNEL_ALL                0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
00261 #endif /*USE_FULL_LL_DRIVER*/
00262 /**
00263   * @}
00264   */
00265
00266 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
00267   * @{
00268   */
00269 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U             /*!< Peripheral to memory direction */
00270 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR             /*!< Memory to peripheral direction */
00271 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM         /*!< Memory to memory direction     */
00272 /**
00273   * @}
00274   */
00275
00276 /** @defgroup DMA_LL_EC_MODE Transfer mode
00277   * @{
00278   */
00279 #define LL_DMA_MODE_NORMAL                0x00000000U             /*!< Normal Mode                  */
00280 #define LL_DMA_MODE_CIRCULAR              DMA_CCR_CIRC            /*!< Circular Mode                */
00281 /**
00282   * @}
00283   */
00284
00285 /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
00286   * @{
00287   */
00288 #define LL_DMA_PERIPH_INCREMENT           DMA_CCR_PINC            /*!< Peripheral increment mode Enable */
00289 #define LL_DMA_PERIPH_NOINCREMENT         0x00000000U             /*!< Peripheral increment mode Disable */
00290 /**
00291   * @}
00292   */
00293
00294 /** @defgroup DMA_LL_EC_MEMORY Memory increment mode
00295   * @{
00296   */
00297 #define LL_DMA_MEMORY_INCREMENT           DMA_CCR_MINC            /*!< Memory increment mode Enable  */
00298 #define LL_DMA_MEMORY_NOINCREMENT         0x00000000U             /*!< Memory increment mode Disable */
00299 /**
00300   * @}
00301   */
00302
00303 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
00304   * @{
00305   */
00306 #define LL_DMA_PDATAALIGN_BYTE            0x00000000U             /*!< Peripheral data alignment : Byte     */
00307 #define LL_DMA_PDATAALIGN_HALFWORD        DMA_CCR_PSIZE_0         /*!< Peripheral data alignment : HalfWord */
00308 #define LL_DMA_PDATAALIGN_WORD            DMA_CCR_PSIZE_1         /*!< Peripheral data alignment : Word     */
00309 /**
00310   * @}
00311   */
00312
00313 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
00314   * @{
00315   */
00316 #define LL_DMA_MDATAALIGN_BYTE            0x00000000U             /*!< Memory data alignment : Byte     */
00317 #define LL_DMA_MDATAALIGN_HALFWORD        DMA_CCR_MSIZE_0         /*!< Memory data alignment : HalfWord */
00318 #define LL_DMA_MDATAALIGN_WORD            DMA_CCR_MSIZE_1         /*!< Memory data alignment : Word     */
00319 /**
00320   * @}
00321   */
00322
00323 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
00324   * @{
00325   */
00326 #define LL_DMA_PRIORITY_LOW               0x00000000U             /*!< Priority level : Low       */
00327 #define LL_DMA_PRIORITY_MEDIUM            DMA_CCR_PL_0            /*!< Priority level : Medium    */
00328 #define LL_DMA_PRIORITY_HIGH              DMA_CCR_PL_1            /*!< Priority level : High      */
00329 #define LL_DMA_PRIORITY_VERYHIGH          DMA_CCR_PL              /*!< Priority level : Very_High */
00330 /**
00331   * @}
00332   */
00333
00334 /**
00335   * @}
00336   */
00337
00338 /* Exported macro ------------------------------------------------------------*/
00339 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
00340   * @{
00341   */
00342
00343 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
00344   * @{
00345   */
00346 /**
00347   * @brief  Write a value in DMA register
00348   * @param  __INSTANCE__ DMA Instance
00349   * @param  __REG__ Register to be written
00350   * @param  __VALUE__ Value to be written in the register
00351   * @retval None
00352   */
00353 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00354
00355 /**
00356   * @brief  Read a value in DMA register
00357   * @param  __INSTANCE__ DMA Instance
00358   * @param  __REG__ Register to be read
00359   * @retval Register value
00360   */
00361 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00362 /**
00363   * @}
00364   */
00365
00366 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
00367   * @{
00368   */
00369 /**
00370   * @brief  Convert DMAx_Channely into DMAx
00371   * @param  __CHANNEL_INSTANCE__ DMAx_Channely
00372   * @retval DMAx
00373   */
00374 #if defined(DMA2)
00375 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__)   \
00376 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ?  DMA2 : DMA1)
00377 #else
00378 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__)  (DMA1)
00379 #endif
00380
00381 /**
00382   * @brief  Convert DMAx_Channely into LL_DMA_CHANNEL_y
00383   * @param  __CHANNEL_INSTANCE__ DMAx_Channely
00384   * @retval LL_DMA_CHANNEL_y
00385   */
00386 #if defined (DMA2)
00387 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
00388 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \
00389 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
00390  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
00391  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
00392  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
00393  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
00394  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
00395  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
00396  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
00397  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
00398  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
00399  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
00400  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
00401  LL_DMA_CHANNEL_7)
00402 #else
00403 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \
00404 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
00405  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
00406  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
00407  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
00408  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
00409  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
00410  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
00411  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
00412  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
00413  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
00414  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
00415  LL_DMA_CHANNEL_7)
00416 #endif
00417 #else
00418 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \
00419 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
00420  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
00421  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
00422  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
00423  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
00424  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
00425  LL_DMA_CHANNEL_7)
00426 #endif
00427
00428 /**
00429   * @brief  Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
00430   * @param  __DMA_INSTANCE__ DMAx
00431   * @param  __CHANNEL__ LL_DMA_CHANNEL_y
00432   * @retval DMAx_Channely
00433   */
00434 #if defined (DMA2)
00435 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
00436 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)   \
00437 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
00438  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
00439  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
00440  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
00441  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
00442  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
00443  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
00444  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
00445  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
00446  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
00447  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
00448  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
00449  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
00450  DMA2_Channel7)
00451 #else
00452 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)   \
00453 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
00454  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
00455  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
00456  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
00457  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
00458  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
00459  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
00460  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
00461  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
00462  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
00463  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
00464  DMA1_Channel7)
00465 #endif
00466 #else
00467 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)   \
00468 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
00469  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
00470  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
00471  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
00472  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
00473  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
00474  DMA1_Channel7)
00475 #endif
00476
00477 /**
00478   * @}
00479   */
00480
00481 /**
00482   * @}
00483   */
00484
00485 /* Exported functions --------------------------------------------------------*/
00486 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
00487  * @{
00488  */
00489
00490 /** @defgroup DMA_LL_EF_Configuration Configuration
00491   * @{
00492   */
00493 /**
00494   * @brief  Enable DMA channel.
00495   * @rmtoll CCR          EN            LL_DMA_EnableChannel
00496   * @param  DMAx DMAx Instance
00497   * @param  Channel This parameter can be one of the following values:
00498   *         @arg @ref LL_DMA_CHANNEL_1
00499   *         @arg @ref LL_DMA_CHANNEL_2
00500   *         @arg @ref LL_DMA_CHANNEL_3
00501   *         @arg @ref LL_DMA_CHANNEL_4
00502   *         @arg @ref LL_DMA_CHANNEL_5
00503   *         @arg @ref LL_DMA_CHANNEL_6
00504   *         @arg @ref LL_DMA_CHANNEL_7
00505   * @retval None
00506   */
00507 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
00508 {
00509   SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN);
00510 }
00511
00512 /**
00513   * @brief  Disable DMA channel.
00514   * @rmtoll CCR          EN            LL_DMA_DisableChannel
00515   * @param  DMAx DMAx Instance
00516   * @param  Channel This parameter can be one of the following values:
00517   *         @arg @ref LL_DMA_CHANNEL_1
00518   *         @arg @ref LL_DMA_CHANNEL_2
00519   *         @arg @ref LL_DMA_CHANNEL_3
00520   *         @arg @ref LL_DMA_CHANNEL_4
00521   *         @arg @ref LL_DMA_CHANNEL_5
00522   *         @arg @ref LL_DMA_CHANNEL_6
00523   *         @arg @ref LL_DMA_CHANNEL_7
00524   * @retval None
00525   */
00526 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
00527 {
00528   CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN);
00529 }
00530
00531 /**
00532   * @brief  Check if DMA channel is enabled or disabled.
00533   * @rmtoll CCR          EN            LL_DMA_IsEnabledChannel
00534   * @param  DMAx DMAx Instance
00535   * @param  Channel This parameter can be one of the following values:
00536   *         @arg @ref LL_DMA_CHANNEL_1
00537   *         @arg @ref LL_DMA_CHANNEL_2
00538   *         @arg @ref LL_DMA_CHANNEL_3
00539   *         @arg @ref LL_DMA_CHANNEL_4
00540   *         @arg @ref LL_DMA_CHANNEL_5
00541   *         @arg @ref LL_DMA_CHANNEL_6
00542   *         @arg @ref LL_DMA_CHANNEL_7
00543   * @retval State of bit (1 or 0).
00544   */
00545 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
00546 {
00547   return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
00548                    DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL);
00549 }
00550
00551 /**
00552   * @brief  Configure all parameters link to DMA transfer.
00553   * @rmtoll CCR          DIR           LL_DMA_ConfigTransfer\n
00554   *         CCR          MEM2MEM       LL_DMA_ConfigTransfer\n
00555   *         CCR          CIRC          LL_DMA_ConfigTransfer\n
00556   *         CCR          PINC          LL_DMA_ConfigTransfer\n
00557   *         CCR          MINC          LL_DMA_ConfigTransfer\n
00558   *         CCR          PSIZE         LL_DMA_ConfigTransfer\n
00559   *         CCR          MSIZE         LL_DMA_ConfigTransfer\n
00560   *         CCR          PL            LL_DMA_ConfigTransfer
00561   * @param  DMAx DMAx Instance
00562   * @param  Channel This parameter can be one of the following values:
00563   *         @arg @ref LL_DMA_CHANNEL_1
00564   *         @arg @ref LL_DMA_CHANNEL_2
00565   *         @arg @ref LL_DMA_CHANNEL_3
00566   *         @arg @ref LL_DMA_CHANNEL_4
00567   *         @arg @ref LL_DMA_CHANNEL_5
00568   *         @arg @ref LL_DMA_CHANNEL_6
00569   *         @arg @ref LL_DMA_CHANNEL_7
00570   * @param  Configuration This parameter must be a combination of all the following values:
00571   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
00572   *         @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
00573   *         @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
00574   *         @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
00575   *         @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
00576   *         @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
00577   *         @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
00578   * @retval None
00579   */
00580 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
00581 {
00582   MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
00583              DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
00584              Configuration);
00585 }
00586
00587 /**
00588   * @brief  Set Data transfer direction (read from peripheral or from memory).
00589   * @rmtoll CCR          DIR           LL_DMA_SetDataTransferDirection\n
00590   *         CCR          MEM2MEM       LL_DMA_SetDataTransferDirection
00591   * @param  DMAx DMAx Instance
00592   * @param  Channel This parameter can be one of the following values:
00593   *         @arg @ref LL_DMA_CHANNEL_1
00594   *         @arg @ref LL_DMA_CHANNEL_2
00595   *         @arg @ref LL_DMA_CHANNEL_3
00596   *         @arg @ref LL_DMA_CHANNEL_4
00597   *         @arg @ref LL_DMA_CHANNEL_5
00598   *         @arg @ref LL_DMA_CHANNEL_6
00599   *         @arg @ref LL_DMA_CHANNEL_7
00600   * @param  Direction This parameter can be one of the following values:
00601   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
00602   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
00603   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
00604   * @retval None
00605   */
00606 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
00607 {
00608   MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
00609              DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
00610 }
00611
00612 /**
00613   * @brief  Get Data transfer direction (read from peripheral or from memory).
00614   * @rmtoll CCR          DIR           LL_DMA_GetDataTransferDirection\n
00615   *         CCR          MEM2MEM       LL_DMA_GetDataTransferDirection
00616   * @param  DMAx DMAx Instance
00617   * @param  Channel This parameter can be one of the following values:
00618   *         @arg @ref LL_DMA_CHANNEL_1
00619   *         @arg @ref LL_DMA_CHANNEL_2
00620   *         @arg @ref LL_DMA_CHANNEL_3
00621   *         @arg @ref LL_DMA_CHANNEL_4
00622   *         @arg @ref LL_DMA_CHANNEL_5
00623   *         @arg @ref LL_DMA_CHANNEL_6
00624   *         @arg @ref LL_DMA_CHANNEL_7
00625   * @retval Returned value can be one of the following values:
00626   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
00627   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
00628   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
00629   */
00630 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
00631 {
00632   return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
00633                    DMA_CCR_DIR | DMA_CCR_MEM2MEM));
00634 }
00635
00636 /**
00637   * @brief  Set DMA mode circular or normal.
00638   * @note The circular buffer mode cannot be used if the memory-to-memory
00639   * data transfer is configured on the selected Channel.
00640   * @rmtoll CCR          CIRC          LL_DMA_SetMode
00641   * @param  DMAx DMAx Instance
00642   * @param  Channel This parameter can be one of the following values:
00643   *         @arg @ref LL_DMA_CHANNEL_1
00644   *         @arg @ref LL_DMA_CHANNEL_2
00645   *         @arg @ref LL_DMA_CHANNEL_3
00646   *         @arg @ref LL_DMA_CHANNEL_4
00647   *         @arg @ref LL_DMA_CHANNEL_5
00648   *         @arg @ref LL_DMA_CHANNEL_6
00649   *         @arg @ref LL_DMA_CHANNEL_7
00650   * @param  Mode This parameter can be one of the following values:
00651   *         @arg @ref LL_DMA_MODE_NORMAL
00652   *         @arg @ref LL_DMA_MODE_CIRCULAR
00653   * @retval None
00654   */
00655 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
00656 {
00657   MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_CIRC,
00658              Mode);
00659 }
00660
00661 /**
00662   * @brief  Get DMA mode circular or normal.
00663   * @rmtoll CCR          CIRC          LL_DMA_GetMode
00664   * @param  DMAx DMAx Instance
00665   * @param  Channel This parameter can be one of the following values:
00666   *         @arg @ref LL_DMA_CHANNEL_1
00667   *         @arg @ref LL_DMA_CHANNEL_2
00668   *         @arg @ref LL_DMA_CHANNEL_3
00669   *         @arg @ref LL_DMA_CHANNEL_4
00670   *         @arg @ref LL_DMA_CHANNEL_5
00671   *         @arg @ref LL_DMA_CHANNEL_6
00672   *         @arg @ref LL_DMA_CHANNEL_7
00673   * @retval Returned value can be one of the following values:
00674   *         @arg @ref LL_DMA_MODE_NORMAL
00675   *         @arg @ref LL_DMA_MODE_CIRCULAR
00676   */
00677 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
00678 {
00679   return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
00680                    DMA_CCR_CIRC));
00681 }
00682
00683 /**
00684   * @brief  Set Peripheral increment mode.
00685   * @rmtoll CCR          PINC          LL_DMA_SetPeriphIncMode
00686   * @param  DMAx DMAx Instance
00687   * @param  Channel This parameter can be one of the following values:
00688   *         @arg @ref LL_DMA_CHANNEL_1
00689   *         @arg @ref LL_DMA_CHANNEL_2
00690   *         @arg @ref LL_DMA_CHANNEL_3
00691   *         @arg @ref LL_DMA_CHANNEL_4
00692   *         @arg @ref LL_DMA_CHANNEL_5
00693   *         @arg @ref LL_DMA_CHANNEL_6
00694   *         @arg @ref LL_DMA_CHANNEL_7
00695   * @param  PeriphOrM2MSrcIncMode This parameter can be one of the following values:
00696   *         @arg @ref LL_DMA_PERIPH_INCREMENT
00697   *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
00698   * @retval None
00699   */
00700 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
00701 {
00702   MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PINC,
00703              PeriphOrM2MSrcIncMode);
00704 }
00705
00706 /**
00707   * @brief  Get Peripheral increment mode.
00708   * @rmtoll CCR          PINC          LL_DMA_GetPeriphIncMode
00709   * @param  DMAx DMAx Instance
00710   * @param  Channel This parameter can be one of the following values:
00711   *         @arg @ref LL_DMA_CHANNEL_1
00712   *         @arg @ref LL_DMA_CHANNEL_2
00713   *         @arg @ref LL_DMA_CHANNEL_3
00714   *         @arg @ref LL_DMA_CHANNEL_4
00715   *         @arg @ref LL_DMA_CHANNEL_5
00716   *         @arg @ref LL_DMA_CHANNEL_6
00717   *         @arg @ref LL_DMA_CHANNEL_7
00718   * @retval Returned value can be one of the following values:
00719   *         @arg @ref LL_DMA_PERIPH_INCREMENT
00720   *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
00721   */
00722 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
00723 {
00724   return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
00725                    DMA_CCR_PINC));
00726 }
00727
00728 /**
00729   * @brief  Set Memory increment mode.
00730   * @rmtoll CCR          MINC          LL_DMA_SetMemoryIncMode
00731   * @param  DMAx DMAx Instance
00732   * @param  Channel This parameter can be one of the following values:
00733   *         @arg @ref LL_DMA_CHANNEL_1
00734   *         @arg @ref LL_DMA_CHANNEL_2
00735   *         @arg @ref LL_DMA_CHANNEL_3
00736   *         @arg @ref LL_DMA_CHANNEL_4
00737   *         @arg @ref LL_DMA_CHANNEL_5
00738   *         @arg @ref LL_DMA_CHANNEL_6
00739   *         @arg @ref LL_DMA_CHANNEL_7
00740   * @param  MemoryOrM2MDstIncMode This parameter can be one of the following values:
00741   *         @arg @ref LL_DMA_MEMORY_INCREMENT
00742   *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
00743   * @retval None
00744   */
00745 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
00746 {
00747   MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MINC,
00748              MemoryOrM2MDstIncMode);
00749 }
00750
00751 /**
00752   * @brief  Get Memory increment mode.
00753   * @rmtoll CCR          MINC          LL_DMA_GetMemoryIncMode
00754   * @param  DMAx DMAx Instance
00755   * @param  Channel This parameter can be one of the following values:
00756   *         @arg @ref LL_DMA_CHANNEL_1
00757   *         @arg @ref LL_DMA_CHANNEL_2
00758   *         @arg @ref LL_DMA_CHANNEL_3
00759   *         @arg @ref LL_DMA_CHANNEL_4
00760   *         @arg @ref LL_DMA_CHANNEL_5
00761   *         @arg @ref LL_DMA_CHANNEL_6
00762   *         @arg @ref LL_DMA_CHANNEL_7
00763   * @retval Returned value can be one of the following values:
00764   *         @arg @ref LL_DMA_MEMORY_INCREMENT
00765   *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
00766   */
00767 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
00768 {
00769   return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
00770                    DMA_CCR_MINC));
00771 }
00772
00773 /**
00774   * @brief  Set Peripheral size.
00775   * @rmtoll CCR          PSIZE         LL_DMA_SetPeriphSize
00776   * @param  DMAx DMAx Instance
00777   * @param  Channel This parameter can be one of the following values:
00778   *         @arg @ref LL_DMA_CHANNEL_1
00779   *         @arg @ref LL_DMA_CHANNEL_2
00780   *         @arg @ref LL_DMA_CHANNEL_3
00781   *         @arg @ref LL_DMA_CHANNEL_4
00782   *         @arg @ref LL_DMA_CHANNEL_5
00783   *         @arg @ref LL_DMA_CHANNEL_6
00784   *         @arg @ref LL_DMA_CHANNEL_7
00785   * @param  PeriphOrM2MSrcDataSize This parameter can be one of the following values:
00786   *         @arg @ref LL_DMA_PDATAALIGN_BYTE
00787   *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
00788   *         @arg @ref LL_DMA_PDATAALIGN_WORD
00789   * @retval None
00790   */
00791 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
00792 {
00793   MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PSIZE,
00794              PeriphOrM2MSrcDataSize);
00795 }
00796
00797 /**
00798   * @brief  Get Peripheral size.
00799   * @rmtoll CCR          PSIZE         LL_DMA_GetPeriphSize
00800   * @param  DMAx DMAx Instance
00801   * @param  Channel This parameter can be one of the following values:
00802   *         @arg @ref LL_DMA_CHANNEL_1
00803   *         @arg @ref LL_DMA_CHANNEL_2
00804   *         @arg @ref LL_DMA_CHANNEL_3
00805   *         @arg @ref LL_DMA_CHANNEL_4
00806   *         @arg @ref LL_DMA_CHANNEL_5
00807   *         @arg @ref LL_DMA_CHANNEL_6
00808   *         @arg @ref LL_DMA_CHANNEL_7
00809   * @retval Returned value can be one of the following values:
00810   *         @arg @ref LL_DMA_PDATAALIGN_BYTE
00811   *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
00812   *         @arg @ref LL_DMA_PDATAALIGN_WORD
00813   */
00814 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
00815 {
00816   return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
00817                    DMA_CCR_PSIZE));
00818 }
00819
00820 /**
00821   * @brief  Set Memory size.
00822   * @rmtoll CCR          MSIZE         LL_DMA_SetMemorySize
00823   * @param  DMAx DMAx Instance
00824   * @param  Channel This parameter can be one of the following values:
00825   *         @arg @ref LL_DMA_CHANNEL_1
00826   *         @arg @ref LL_DMA_CHANNEL_2
00827   *         @arg @ref LL_DMA_CHANNEL_3
00828   *         @arg @ref LL_DMA_CHANNEL_4
00829   *         @arg @ref LL_DMA_CHANNEL_5
00830   *         @arg @ref LL_DMA_CHANNEL_6
00831   *         @arg @ref LL_DMA_CHANNEL_7
00832   * @param  MemoryOrM2MDstDataSize This parameter can be one of the following values:
00833   *         @arg @ref LL_DMA_MDATAALIGN_BYTE
00834   *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
00835   *         @arg @ref LL_DMA_MDATAALIGN_WORD
00836   * @retval None
00837   */
00838 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
00839 {
00840   MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MSIZE,
00841              MemoryOrM2MDstDataSize);
00842 }
00843
00844 /**
00845   * @brief  Get Memory size.
00846   * @rmtoll CCR          MSIZE         LL_DMA_GetMemorySize
00847   * @param  DMAx DMAx Instance
00848   * @param  Channel This parameter can be one of the following values:
00849   *         @arg @ref LL_DMA_CHANNEL_1
00850   *         @arg @ref LL_DMA_CHANNEL_2
00851   *         @arg @ref LL_DMA_CHANNEL_3
00852   *         @arg @ref LL_DMA_CHANNEL_4
00853   *         @arg @ref LL_DMA_CHANNEL_5
00854   *         @arg @ref LL_DMA_CHANNEL_6
00855   *         @arg @ref LL_DMA_CHANNEL_7
00856   * @retval Returned value can be one of the following values:
00857   *         @arg @ref LL_DMA_MDATAALIGN_BYTE
00858   *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
00859   *         @arg @ref LL_DMA_MDATAALIGN_WORD
00860   */
00861 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
00862 {
00863   return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
00864                    DMA_CCR_MSIZE));
00865 }
00866
00867 /**
00868   * @brief  Set Channel priority level.
00869   * @rmtoll CCR          PL            LL_DMA_SetChannelPriorityLevel
00870   * @param  DMAx DMAx Instance
00871   * @param  Channel This parameter can be one of the following values:
00872   *         @arg @ref LL_DMA_CHANNEL_1
00873   *         @arg @ref LL_DMA_CHANNEL_2
00874   *         @arg @ref LL_DMA_CHANNEL_3
00875   *         @arg @ref LL_DMA_CHANNEL_4
00876   *         @arg @ref LL_DMA_CHANNEL_5
00877   *         @arg @ref LL_DMA_CHANNEL_6
00878   *         @arg @ref LL_DMA_CHANNEL_7
00879   * @param  Priority This parameter can be one of the following values:
00880   *         @arg @ref LL_DMA_PRIORITY_LOW
00881   *         @arg @ref LL_DMA_PRIORITY_MEDIUM
00882   *         @arg @ref LL_DMA_PRIORITY_HIGH
00883   *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
00884   * @retval None
00885   */
00886 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
00887 {
00888   MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PL,
00889              Priority);
00890 }
00891
00892 /**
00893   * @brief  Get Channel priority level.
00894   * @rmtoll CCR          PL            LL_DMA_GetChannelPriorityLevel
00895   * @param  DMAx DMAx Instance
00896   * @param  Channel This parameter can be one of the following values:
00897   *         @arg @ref LL_DMA_CHANNEL_1
00898   *         @arg @ref LL_DMA_CHANNEL_2
00899   *         @arg @ref LL_DMA_CHANNEL_3
00900   *         @arg @ref LL_DMA_CHANNEL_4
00901   *         @arg @ref LL_DMA_CHANNEL_5
00902   *         @arg @ref LL_DMA_CHANNEL_6
00903   *         @arg @ref LL_DMA_CHANNEL_7
00904   * @retval Returned value can be one of the following values:
00905   *         @arg @ref LL_DMA_PRIORITY_LOW
00906   *         @arg @ref LL_DMA_PRIORITY_MEDIUM
00907   *         @arg @ref LL_DMA_PRIORITY_HIGH
00908   *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
00909   */
00910 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
00911 {
00912   return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
00913                    DMA_CCR_PL));
00914 }
00915
00916 /**
00917   * @brief  Set Number of data to transfer.
00918   * @note   This action has no effect if
00919   *         channel is enabled.
00920   * @rmtoll CNDTR        NDT           LL_DMA_SetDataLength
00921   * @param  DMAx DMAx Instance
00922   * @param  Channel This parameter can be one of the following values:
00923   *         @arg @ref LL_DMA_CHANNEL_1
00924   *         @arg @ref LL_DMA_CHANNEL_2
00925   *         @arg @ref LL_DMA_CHANNEL_3
00926   *         @arg @ref LL_DMA_CHANNEL_4
00927   *         @arg @ref LL_DMA_CHANNEL_5
00928   *         @arg @ref LL_DMA_CHANNEL_6
00929   *         @arg @ref LL_DMA_CHANNEL_7
00930   * @param  NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
00931   * @retval None
00932   */
00933 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
00934 {
00935   MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CNDTR,
00936              DMA_CNDTR_NDT, NbData);
00937 }
00938
00939 /**
00940   * @brief  Get Number of data to transfer.
00941   * @note   Once the channel is enabled, the return value indicate the
00942   *         remaining bytes to be transmitted.
00943   * @rmtoll CNDTR        NDT           LL_DMA_GetDataLength
00944   * @param  DMAx DMAx Instance
00945   * @param  Channel This parameter can be one of the following values:
00946   *         @arg @ref LL_DMA_CHANNEL_1
00947   *         @arg @ref LL_DMA_CHANNEL_2
00948   *         @arg @ref LL_DMA_CHANNEL_3
00949   *         @arg @ref LL_DMA_CHANNEL_4
00950   *         @arg @ref LL_DMA_CHANNEL_5
00951   *         @arg @ref LL_DMA_CHANNEL_6
00952   *         @arg @ref LL_DMA_CHANNEL_7
00953   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
00954   */
00955 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
00956 {
00957   return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CNDTR,
00958                    DMA_CNDTR_NDT));
00959 }
00960
00961 /**
00962   * @brief  Configure the Source and Destination addresses.
00963   * @note   This API must not be called when the DMA channel is enabled.
00964   * @note   Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
00965   * @rmtoll CPAR         PA            LL_DMA_ConfigAddresses\n
00966   *         CMAR         MA            LL_DMA_ConfigAddresses
00967   * @param  DMAx DMAx Instance
00968   * @param  Channel This parameter can be one of the following values:
00969   *         @arg @ref LL_DMA_CHANNEL_1
00970   *         @arg @ref LL_DMA_CHANNEL_2
00971   *         @arg @ref LL_DMA_CHANNEL_3
00972   *         @arg @ref LL_DMA_CHANNEL_4
00973   *         @arg @ref LL_DMA_CHANNEL_5
00974   *         @arg @ref LL_DMA_CHANNEL_6
00975   *         @arg @ref LL_DMA_CHANNEL_7
00976   * @param  SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
00977   * @param  DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
00978   * @param  Direction This parameter can be one of the following values:
00979   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
00980   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
00981   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
00982   * @retval None
00983   */
00984 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
00985                                             uint32_t DstAddress, uint32_t Direction)
00986 {
00987   /* Direction Memory to Periph */
00988   if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
00989   {
00990     WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, SrcAddress);
00991     WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, DstAddress);
00992   }
00993   /* Direction Periph to Memory and Memory to Memory */
00994   else
00995   {
00996     WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, SrcAddress);
00997     WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, DstAddress);
00998   }
00999 }
01000
01001 /**
01002   * @brief  Set the Memory address.
01003   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
01004   * @note   This API must not be called when the DMA channel is enabled.
01005   * @rmtoll CMAR         MA            LL_DMA_SetMemoryAddress
01006   * @param  DMAx DMAx Instance
01007   * @param  Channel This parameter can be one of the following values:
01008   *         @arg @ref LL_DMA_CHANNEL_1
01009   *         @arg @ref LL_DMA_CHANNEL_2
01010   *         @arg @ref LL_DMA_CHANNEL_3
01011   *         @arg @ref LL_DMA_CHANNEL_4
01012   *         @arg @ref LL_DMA_CHANNEL_5
01013   *         @arg @ref LL_DMA_CHANNEL_6
01014   *         @arg @ref LL_DMA_CHANNEL_7
01015   * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01016   * @retval None
01017   */
01018 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
01019 {
01020   WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, MemoryAddress);
01021 }
01022
01023 /**
01024   * @brief  Set the Peripheral address.
01025   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
01026   * @note   This API must not be called when the DMA channel is enabled.
01027   * @rmtoll CPAR         PA            LL_DMA_SetPeriphAddress
01028   * @param  DMAx DMAx Instance
01029   * @param  Channel This parameter can be one of the following values:
01030   *         @arg @ref LL_DMA_CHANNEL_1
01031   *         @arg @ref LL_DMA_CHANNEL_2
01032   *         @arg @ref LL_DMA_CHANNEL_3
01033   *         @arg @ref LL_DMA_CHANNEL_4
01034   *         @arg @ref LL_DMA_CHANNEL_5
01035   *         @arg @ref LL_DMA_CHANNEL_6
01036   *         @arg @ref LL_DMA_CHANNEL_7
01037   * @param  PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01038   * @retval None
01039   */
01040 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
01041 {
01042   WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, PeriphAddress);
01043 }
01044
01045 /**
01046   * @brief  Get Memory address.
01047   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
01048   * @rmtoll CMAR         MA            LL_DMA_GetMemoryAddress
01049   * @param  DMAx DMAx Instance
01050   * @param  Channel This parameter can be one of the following values:
01051   *         @arg @ref LL_DMA_CHANNEL_1
01052   *         @arg @ref LL_DMA_CHANNEL_2
01053   *         @arg @ref LL_DMA_CHANNEL_3
01054   *         @arg @ref LL_DMA_CHANNEL_4
01055   *         @arg @ref LL_DMA_CHANNEL_5
01056   *         @arg @ref LL_DMA_CHANNEL_6
01057   *         @arg @ref LL_DMA_CHANNEL_7
01058   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01059   */
01060 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
01061 {
01062   return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR));
01063 }
01064
01065 /**
01066   * @brief  Get Peripheral address.
01067   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
01068   * @rmtoll CPAR         PA            LL_DMA_GetPeriphAddress
01069   * @param  DMAx DMAx Instance
01070   * @param  Channel This parameter can be one of the following values:
01071   *         @arg @ref LL_DMA_CHANNEL_1
01072   *         @arg @ref LL_DMA_CHANNEL_2
01073   *         @arg @ref LL_DMA_CHANNEL_3
01074   *         @arg @ref LL_DMA_CHANNEL_4
01075   *         @arg @ref LL_DMA_CHANNEL_5
01076   *         @arg @ref LL_DMA_CHANNEL_6
01077   *         @arg @ref LL_DMA_CHANNEL_7
01078   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01079   */
01080 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
01081 {
01082   return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR));
01083 }
01084
01085 /**
01086   * @brief  Set the Memory to Memory Source address.
01087   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
01088   * @note   This API must not be called when the DMA channel is enabled.
01089   * @rmtoll CPAR         PA            LL_DMA_SetM2MSrcAddress
01090   * @param  DMAx DMAx Instance
01091   * @param  Channel This parameter can be one of the following values:
01092   *         @arg @ref LL_DMA_CHANNEL_1
01093   *         @arg @ref LL_DMA_CHANNEL_2
01094   *         @arg @ref LL_DMA_CHANNEL_3
01095   *         @arg @ref LL_DMA_CHANNEL_4
01096   *         @arg @ref LL_DMA_CHANNEL_5
01097   *         @arg @ref LL_DMA_CHANNEL_6
01098   *         @arg @ref LL_DMA_CHANNEL_7
01099   * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01100   * @retval None
01101   */
01102 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
01103 {
01104   WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, MemoryAddress);
01105 }
01106
01107 /**
01108   * @brief  Set the Memory to Memory Destination address.
01109   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
01110   * @note   This API must not be called when the DMA channel is enabled.
01111   * @rmtoll CMAR         MA            LL_DMA_SetM2MDstAddress
01112   * @param  DMAx DMAx Instance
01113   * @param  Channel This parameter can be one of the following values:
01114   *         @arg @ref LL_DMA_CHANNEL_1
01115   *         @arg @ref LL_DMA_CHANNEL_2
01116   *         @arg @ref LL_DMA_CHANNEL_3
01117   *         @arg @ref LL_DMA_CHANNEL_4
01118   *         @arg @ref LL_DMA_CHANNEL_5
01119   *         @arg @ref LL_DMA_CHANNEL_6
01120   *         @arg @ref LL_DMA_CHANNEL_7
01121   * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01122   * @retval None
01123   */
01124 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
01125 {
01126   WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, MemoryAddress);
01127 }
01128
01129 /**
01130   * @brief  Get the Memory to Memory Source address.
01131   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
01132   * @rmtoll CPAR         PA            LL_DMA_GetM2MSrcAddress
01133   * @param  DMAx DMAx Instance
01134   * @param  Channel This parameter can be one of the following values:
01135   *         @arg @ref LL_DMA_CHANNEL_1
01136   *         @arg @ref LL_DMA_CHANNEL_2
01137   *         @arg @ref LL_DMA_CHANNEL_3
01138   *         @arg @ref LL_DMA_CHANNEL_4
01139   *         @arg @ref LL_DMA_CHANNEL_5
01140   *         @arg @ref LL_DMA_CHANNEL_6
01141   *         @arg @ref LL_DMA_CHANNEL_7
01142   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01143   */
01144 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
01145 {
01146   return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR));
01147 }
01148
01149 /**
01150   * @brief  Get the Memory to Memory Destination address.
01151   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
01152   * @rmtoll CMAR         MA            LL_DMA_GetM2MDstAddress
01153   * @param  DMAx DMAx Instance
01154   * @param  Channel This parameter can be one of the following values:
01155   *         @arg @ref LL_DMA_CHANNEL_1
01156   *         @arg @ref LL_DMA_CHANNEL_2
01157   *         @arg @ref LL_DMA_CHANNEL_3
01158   *         @arg @ref LL_DMA_CHANNEL_4
01159   *         @arg @ref LL_DMA_CHANNEL_5
01160   *         @arg @ref LL_DMA_CHANNEL_6
01161   *         @arg @ref LL_DMA_CHANNEL_7
01162   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01163   */
01164 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
01165 {
01166   return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR));
01167 }
01168
01169 /**
01170   * @brief  Set DMA request for DMA Channels on DMAMUX Channel x.
01171   * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
01172 #if defined(DMA2)
01173   *         DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7.
01174 #endif
01175   * @rmtoll CxCR         DMAREQ_ID     LL_DMA_SetPeriphRequest
01176   * @param  DMAx DMAx Instance
01177   * @param  Channel This parameter can be one of the following values:
01178   *         @arg @ref LL_DMA_CHANNEL_1
01179   *         @arg @ref LL_DMA_CHANNEL_2
01180   *         @arg @ref LL_DMA_CHANNEL_3
01181   *         @arg @ref LL_DMA_CHANNEL_4
01182   *         @arg @ref LL_DMA_CHANNEL_5
01183   *         @arg @ref LL_DMA_CHANNEL_6
01184   *         @arg @ref LL_DMA_CHANNEL_7
01185   * @param  Request This parameter can be one of the following values:
01186   *         @arg @ref LL_DMAMUX_REQ_MEM2MEM
01187   *         @arg @ref LL_DMAMUX_REQ_GENERATOR0
01188   *         @arg @ref LL_DMAMUX_REQ_GENERATOR1
01189   *         @arg @ref LL_DMAMUX_REQ_GENERATOR2
01190   *         @arg @ref LL_DMAMUX_REQ_GENERATOR3
01191   *         @arg @ref LL_DMAMUX_REQ_ADC1
01192   *         @arg @ref LL_DMAMUX_REQ_SPI1_RX
01193   *         @arg @ref LL_DMAMUX_REQ_SPI1_TX
01194   *         @arg @ref LL_DMAMUX_REQ_SPI2_RX
01195   *         @arg @ref LL_DMAMUX_REQ_SPI2_TX
01196   *         @arg @ref LL_DMAMUX_REQ_I2C1_RX
01197   *         @arg @ref LL_DMAMUX_REQ_I2C1_TX
01198   *         @arg @ref LL_DMAMUX_REQ_I2C3_RX
01199   *         @arg @ref LL_DMAMUX_REQ_I2C3_TX
01200   *         @arg @ref LL_DMAMUX_REQ_USART1_RX
01201   *         @arg @ref LL_DMAMUX_REQ_USART1_TX
01202   *         @arg @ref LL_DMAMUX_REQ_LPUART1_RX
01203   *         @arg @ref LL_DMAMUX_REQ_LPUART1_TX
01204   *         @arg @ref LL_DMAMUX_REQ_SAI1_A
01205   *         @arg @ref LL_DMAMUX_REQ_SAI1_B
01206   *         @arg @ref LL_DMAMUX_REQ_QUADSPI
01207   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH1
01208   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH2
01209   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH3
01210   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH4
01211   *         @arg @ref LL_DMAMUX_REQ_TIM1_UP
01212   *         @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
01213   *         @arg @ref LL_DMAMUX_REQ_TIM1_COM
01214   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH1
01215   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH2
01216   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH3
01217   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH4
01218   *         @arg @ref LL_DMAMUX_REQ_TIM2_UP
01219   *         @arg @ref LL_DMAMUX_REQ_TIM16_CH1
01220   *         @arg @ref LL_DMAMUX_REQ_TIM16_UP
01221   *         @arg @ref LL_DMAMUX_REQ_TIM17_CH1
01222   *         @arg @ref LL_DMAMUX_REQ_TIM17_UP
01223   *         @arg @ref LL_DMAMUX_REQ_AES1_IN
01224   *         @arg @ref LL_DMAMUX_REQ_AES1_OUT
01225   *         @arg @ref LL_DMAMUX_REQ_AES2_IN
01226   *         @arg @ref LL_DMAMUX_REQ_AES2_OUT
01227   * @retval None
01228   */
01229 __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
01230 {
01231   MODIFY_REG(__LL_DMA_INSTANCE_TO_DMAMUX_CCR(DMAx, Channel - 1U)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
01232 }
01233
01234 /**
01235   * @brief  Get DMA request for DMA Channels on DMAMUX Channel x.
01236   * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
01237 #if defined(DMA2)
01238   *         DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7.
01239 #endif
01240   * @rmtoll CxCR         DMAREQ_ID     LL_DMA_GetPeriphRequest
01241   * @param  DMAx DMAx Instance
01242   * @param  Channel This parameter can be one of the following values:
01243   *         @arg @ref LL_DMA_CHANNEL_1
01244   *         @arg @ref LL_DMA_CHANNEL_2
01245   *         @arg @ref LL_DMA_CHANNEL_3
01246   *         @arg @ref LL_DMA_CHANNEL_4
01247   *         @arg @ref LL_DMA_CHANNEL_5
01248   *         @arg @ref LL_DMA_CHANNEL_6
01249   *         @arg @ref LL_DMA_CHANNEL_7
01250   * @retval Returned value can be one of the following values:
01251   *         @arg @ref LL_DMAMUX_REQ_MEM2MEM
01252   *         @arg @ref LL_DMAMUX_REQ_GENERATOR0
01253   *         @arg @ref LL_DMAMUX_REQ_GENERATOR1
01254   *         @arg @ref LL_DMAMUX_REQ_GENERATOR2
01255   *         @arg @ref LL_DMAMUX_REQ_GENERATOR3
01256   *         @arg @ref LL_DMAMUX_REQ_ADC1
01257   *         @arg @ref LL_DMAMUX_REQ_SPI1_RX
01258   *         @arg @ref LL_DMAMUX_REQ_SPI1_TX
01259   *         @arg @ref LL_DMAMUX_REQ_SPI2_RX
01260   *         @arg @ref LL_DMAMUX_REQ_SPI2_TX
01261   *         @arg @ref LL_DMAMUX_REQ_I2C1_RX
01262   *         @arg @ref LL_DMAMUX_REQ_I2C1_TX
01263   *         @arg @ref LL_DMAMUX_REQ_I2C3_RX
01264   *         @arg @ref LL_DMAMUX_REQ_I2C3_TX
01265   *         @arg @ref LL_DMAMUX_REQ_USART1_RX
01266   *         @arg @ref LL_DMAMUX_REQ_USART1_TX
01267   *         @arg @ref LL_DMAMUX_REQ_LPUART1_RX
01268   *         @arg @ref LL_DMAMUX_REQ_LPUART1_TX
01269   *         @arg @ref LL_DMAMUX_REQ_SAI1_A
01270   *         @arg @ref LL_DMAMUX_REQ_SAI1_B
01271   *         @arg @ref LL_DMAMUX_REQ_QUADSPI
01272   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH1
01273   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH2
01274   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH3
01275   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH4
01276   *         @arg @ref LL_DMAMUX_REQ_TIM1_UP
01277   *         @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
01278   *         @arg @ref LL_DMAMUX_REQ_TIM1_COM
01279   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH1
01280   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH2
01281   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH3
01282   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH4
01283   *         @arg @ref LL_DMAMUX_REQ_TIM2_UP
01284   *         @arg @ref LL_DMAMUX_REQ_TIM16_CH1
01285   *         @arg @ref LL_DMAMUX_REQ_TIM16_UP
01286   *         @arg @ref LL_DMAMUX_REQ_TIM17_CH1
01287   *         @arg @ref LL_DMAMUX_REQ_TIM17_UP
01288   *         @arg @ref LL_DMAMUX_REQ_AES1_IN
01289   *         @arg @ref LL_DMAMUX_REQ_AES1_OUT
01290   *         @arg @ref LL_DMAMUX_REQ_AES2_IN
01291   *         @arg @ref LL_DMAMUX_REQ_AES2_OUT
01292   */
01293 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
01294 {
01295   return (READ_BIT(__LL_DMA_INSTANCE_TO_DMAMUX_CCR(DMAx, Channel - 1U)->CCR, DMAMUX_CxCR_DMAREQ_ID));
01296 }
01297
01298 /**
01299   * @}
01300   */
01301
01302 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
01303   * @{
01304   */
01305
01306 /**
01307   * @brief  Get Channel 1 global interrupt flag.
01308   * @rmtoll ISR          GIF1          LL_DMA_IsActiveFlag_GI1
01309   * @param  DMAx DMAx Instance
01310   * @retval State of bit (1 or 0).
01311   */
01312 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
01313 {
01314   return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL);
01315 }
01316
01317 /**
01318   * @brief  Get Channel 2 global interrupt flag.
01319   * @rmtoll ISR          GIF2          LL_DMA_IsActiveFlag_GI2
01320   * @param  DMAx DMAx Instance
01321   * @retval State of bit (1 or 0).
01322   */
01323 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
01324 {
01325   return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL);
01326 }
01327
01328 /**
01329   * @brief  Get Channel 3 global interrupt flag.
01330   * @rmtoll ISR          GIF3          LL_DMA_IsActiveFlag_GI3
01331   * @param  DMAx DMAx Instance
01332   * @retval State of bit (1 or 0).
01333   */
01334 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
01335 {
01336   return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL);
01337 }
01338
01339 /**
01340   * @brief  Get Channel 4 global interrupt flag.
01341   * @rmtoll ISR          GIF4          LL_DMA_IsActiveFlag_GI4
01342   * @param  DMAx DMAx Instance
01343   * @retval State of bit (1 or 0).
01344   */
01345 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
01346 {
01347   return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL);
01348 }
01349
01350 /**
01351   * @brief  Get Channel 5 global interrupt flag.
01352   * @rmtoll ISR          GIF5          LL_DMA_IsActiveFlag_GI5
01353   * @param  DMAx DMAx Instance
01354   * @retval State of bit (1 or 0).
01355   */
01356 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
01357 {
01358   return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL);
01359 }
01360
01361 /**
01362   * @brief  Get Channel 6 global interrupt flag.
01363   * @rmtoll ISR          GIF6          LL_DMA_IsActiveFlag_GI6
01364   * @param  DMAx DMAx Instance
01365   * @retval State of bit (1 or 0).
01366   */
01367 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
01368 {
01369   return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL);
01370 }
01371
01372 /**
01373   * @brief  Get Channel 7 global interrupt flag.
01374   * @rmtoll ISR          GIF7          LL_DMA_IsActiveFlag_GI7
01375   * @param  DMAx DMAx Instance
01376   * @retval State of bit (1 or 0).
01377   */
01378 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
01379 {
01380   return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL);
01381 }
01382
01383 /**
01384   * @brief  Get Channel 1 transfer complete flag.
01385   * @rmtoll ISR          TCIF1         LL_DMA_IsActiveFlag_TC1
01386   * @param  DMAx DMAx Instance
01387   * @retval State of bit (1 or 0).
01388   */
01389 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
01390 {
01391   return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL);
01392 }
01393
01394 /**
01395   * @brief  Get Channel 2 transfer complete flag.
01396   * @rmtoll ISR          TCIF2         LL_DMA_IsActiveFlag_TC2
01397   * @param  DMAx DMAx Instance
01398   * @retval State of bit (1 or 0).
01399   */
01400 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
01401 {
01402   return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL);
01403 }
01404
01405 /**
01406   * @brief  Get Channel 3 transfer complete flag.
01407   * @rmtoll ISR          TCIF3         LL_DMA_IsActiveFlag_TC3
01408   * @param  DMAx DMAx Instance
01409   * @retval State of bit (1 or 0).
01410   */
01411 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
01412 {
01413   return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL);
01414 }
01415
01416 /**
01417   * @brief  Get Channel 4 transfer complete flag.
01418   * @rmtoll ISR          TCIF4         LL_DMA_IsActiveFlag_TC4
01419   * @param  DMAx DMAx Instance
01420   * @retval State of bit (1 or 0).
01421   */
01422 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
01423 {
01424   return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL);
01425 }
01426
01427 /**
01428   * @brief  Get Channel 5 transfer complete flag.
01429   * @rmtoll ISR          TCIF5         LL_DMA_IsActiveFlag_TC5
01430   * @param  DMAx DMAx Instance
01431   * @retval State of bit (1 or 0).
01432   */
01433 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
01434 {
01435   return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL);
01436 }
01437
01438 /**
01439   * @brief  Get Channel 6 transfer complete flag.
01440   * @rmtoll ISR          TCIF6         LL_DMA_IsActiveFlag_TC6
01441   * @param  DMAx DMAx Instance
01442   * @retval State of bit (1 or 0).
01443   */
01444 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
01445 {
01446   return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL);
01447 }
01448
01449 /**
01450   * @brief  Get Channel 7 transfer complete flag.
01451   * @rmtoll ISR          TCIF7         LL_DMA_IsActiveFlag_TC7
01452   * @param  DMAx DMAx Instance
01453   * @retval State of bit (1 or 0).
01454   */
01455 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
01456 {
01457   return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL);
01458 }
01459
01460 /**
01461   * @brief  Get Channel 1 half transfer flag.
01462   * @rmtoll ISR          HTIF1         LL_DMA_IsActiveFlag_HT1
01463   * @param  DMAx DMAx Instance
01464   * @retval State of bit (1 or 0).
01465   */
01466 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
01467 {
01468   return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL);
01469 }
01470
01471 /**
01472   * @brief  Get Channel 2 half transfer flag.
01473   * @rmtoll ISR          HTIF2         LL_DMA_IsActiveFlag_HT2
01474   * @param  DMAx DMAx Instance
01475   * @retval State of bit (1 or 0).
01476   */
01477 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
01478 {
01479   return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL);
01480 }
01481
01482 /**
01483   * @brief  Get Channel 3 half transfer flag.
01484   * @rmtoll ISR          HTIF3         LL_DMA_IsActiveFlag_HT3
01485   * @param  DMAx DMAx Instance
01486   * @retval State of bit (1 or 0).
01487   */
01488 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
01489 {
01490   return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL);
01491 }
01492
01493 /**
01494   * @brief  Get Channel 4 half transfer flag.
01495   * @rmtoll ISR          HTIF4         LL_DMA_IsActiveFlag_HT4
01496   * @param  DMAx DMAx Instance
01497   * @retval State of bit (1 or 0).
01498   */
01499 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
01500 {
01501   return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL);
01502 }
01503
01504 /**
01505   * @brief  Get Channel 5 half transfer flag.
01506   * @rmtoll ISR          HTIF5         LL_DMA_IsActiveFlag_HT5
01507   * @param  DMAx DMAx Instance
01508   * @retval State of bit (1 or 0).
01509   */
01510 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
01511 {
01512   return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL);
01513 }
01514
01515 /**
01516   * @brief  Get Channel 6 half transfer flag.
01517   * @rmtoll ISR          HTIF6         LL_DMA_IsActiveFlag_HT6
01518   * @param  DMAx DMAx Instance
01519   * @retval State of bit (1 or 0).
01520   */
01521 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
01522 {
01523   return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL);
01524 }
01525
01526 /**
01527   * @brief  Get Channel 7 half transfer flag.
01528   * @rmtoll ISR          HTIF7         LL_DMA_IsActiveFlag_HT7
01529   * @param  DMAx DMAx Instance
01530   * @retval State of bit (1 or 0).
01531   */
01532 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
01533 {
01534   return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL);
01535 }
01536
01537 /**
01538   * @brief  Get Channel 1 transfer error flag.
01539   * @rmtoll ISR          TEIF1         LL_DMA_IsActiveFlag_TE1
01540   * @param  DMAx DMAx Instance
01541   * @retval State of bit (1 or 0).
01542   */
01543 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
01544 {
01545   return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL);
01546 }
01547
01548 /**
01549   * @brief  Get Channel 2 transfer error flag.
01550   * @rmtoll ISR          TEIF2         LL_DMA_IsActiveFlag_TE2
01551   * @param  DMAx DMAx Instance
01552   * @retval State of bit (1 or 0).
01553   */
01554 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
01555 {
01556   return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL);
01557 }
01558
01559 /**
01560   * @brief  Get Channel 3 transfer error flag.
01561   * @rmtoll ISR          TEIF3         LL_DMA_IsActiveFlag_TE3
01562   * @param  DMAx DMAx Instance
01563   * @retval State of bit (1 or 0).
01564   */
01565 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
01566 {
01567   return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL);
01568 }
01569
01570 /**
01571   * @brief  Get Channel 4 transfer error flag.
01572   * @rmtoll ISR          TEIF4         LL_DMA_IsActiveFlag_TE4
01573   * @param  DMAx DMAx Instance
01574   * @retval State of bit (1 or 0).
01575   */
01576 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
01577 {
01578   return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL);
01579 }
01580
01581 /**
01582   * @brief  Get Channel 5 transfer error flag.
01583   * @rmtoll ISR          TEIF5         LL_DMA_IsActiveFlag_TE5
01584   * @param  DMAx DMAx Instance
01585   * @retval State of bit (1 or 0).
01586   */
01587 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
01588 {
01589   return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL);
01590 }
01591
01592 /**
01593   * @brief  Get Channel 6 transfer error flag.
01594   * @rmtoll ISR          TEIF6         LL_DMA_IsActiveFlag_TE6
01595   * @param  DMAx DMAx Instance
01596   * @retval State of bit (1 or 0).
01597   */
01598 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
01599 {
01600   return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL);
01601 }
01602
01603 /**
01604   * @brief  Get Channel 7 transfer error flag.
01605   * @rmtoll ISR          TEIF7         LL_DMA_IsActiveFlag_TE7
01606   * @param  DMAx DMAx Instance
01607   * @retval State of bit (1 or 0).
01608   */
01609 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
01610 {
01611   return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL);
01612 }
01613
01614 /**
01615   * @brief  Clear Channel 1 global interrupt flag.
01616   * @rmtoll IFCR         CGIF1         LL_DMA_ClearFlag_GI1
01617   * @param  DMAx DMAx Instance
01618   * @retval None
01619   */
01620 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
01621 {
01622   WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
01623 }
01624
01625 /**
01626   * @brief  Clear Channel 2 global interrupt flag.
01627   * @rmtoll IFCR         CGIF2         LL_DMA_ClearFlag_GI2
01628   * @param  DMAx DMAx Instance
01629   * @retval None
01630   */
01631 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
01632 {
01633   WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
01634 }
01635
01636 /**
01637   * @brief  Clear Channel 3 global interrupt flag.
01638   * @rmtoll IFCR         CGIF3         LL_DMA_ClearFlag_GI3
01639   * @param  DMAx DMAx Instance
01640   * @retval None
01641   */
01642 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
01643 {
01644   WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
01645 }
01646
01647 /**
01648   * @brief  Clear Channel 4 global interrupt flag.
01649   * @rmtoll IFCR         CGIF4         LL_DMA_ClearFlag_GI4
01650   * @param  DMAx DMAx Instance
01651   * @retval None
01652   */
01653 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
01654 {
01655   WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
01656 }
01657
01658 /**
01659   * @brief  Clear Channel 5 global interrupt flag.
01660   * @rmtoll IFCR         CGIF5         LL_DMA_ClearFlag_GI5
01661   * @param  DMAx DMAx Instance
01662   * @retval None
01663   */
01664 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
01665 {
01666   WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
01667 }
01668
01669 /**
01670   * @brief  Clear Channel 6 global interrupt flag.
01671   * @rmtoll IFCR         CGIF6         LL_DMA_ClearFlag_GI6
01672   * @param  DMAx DMAx Instance
01673   * @retval None
01674   */
01675 __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
01676 {
01677   WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
01678 }
01679
01680 /**
01681   * @brief  Clear Channel 7 global interrupt flag.
01682   * @rmtoll IFCR         CGIF7         LL_DMA_ClearFlag_GI7
01683   * @param  DMAx DMAx Instance
01684   * @retval None
01685   */
01686 __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
01687 {
01688   WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
01689 }
01690
01691 /**
01692   * @brief  Clear Channel 1  transfer complete flag.
01693   * @rmtoll IFCR         CTCIF1        LL_DMA_ClearFlag_TC1
01694   * @param  DMAx DMAx Instance
01695   * @retval None
01696   */
01697 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
01698 {
01699   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
01700 }
01701
01702 /**
01703   * @brief  Clear Channel 2  transfer complete flag.
01704   * @rmtoll IFCR         CTCIF2        LL_DMA_ClearFlag_TC2
01705   * @param  DMAx DMAx Instance
01706   * @retval None
01707   */
01708 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
01709 {
01710   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
01711 }
01712
01713 /**
01714   * @brief  Clear Channel 3  transfer complete flag.
01715   * @rmtoll IFCR         CTCIF3        LL_DMA_ClearFlag_TC3
01716   * @param  DMAx DMAx Instance
01717   * @retval None
01718   */
01719 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
01720 {
01721   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
01722 }
01723
01724 /**
01725   * @brief  Clear Channel 4  transfer complete flag.
01726   * @rmtoll IFCR         CTCIF4        LL_DMA_ClearFlag_TC4
01727   * @param  DMAx DMAx Instance
01728   * @retval None
01729   */
01730 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
01731 {
01732   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
01733 }
01734
01735 /**
01736   * @brief  Clear Channel 5  transfer complete flag.
01737   * @rmtoll IFCR         CTCIF5        LL_DMA_ClearFlag_TC5
01738   * @param  DMAx DMAx Instance
01739   * @retval None
01740   */
01741 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
01742 {
01743   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
01744 }
01745
01746 /**
01747   * @brief  Clear Channel 6  transfer complete flag.
01748   * @rmtoll IFCR         CTCIF6        LL_DMA_ClearFlag_TC6
01749   * @param  DMAx DMAx Instance
01750   * @retval None
01751   */
01752 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
01753 {
01754   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
01755 }
01756
01757 /**
01758   * @brief  Clear Channel 7  transfer complete flag.
01759   * @rmtoll IFCR         CTCIF7        LL_DMA_ClearFlag_TC7
01760   * @param  DMAx DMAx Instance
01761   * @retval None
01762   */
01763 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
01764 {
01765   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
01766 }
01767
01768 /**
01769   * @brief  Clear Channel 1  half transfer flag.
01770   * @rmtoll IFCR         CHTIF1        LL_DMA_ClearFlag_HT1
01771   * @param  DMAx DMAx Instance
01772   * @retval None
01773   */
01774 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
01775 {
01776   WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
01777 }
01778
01779 /**
01780   * @brief  Clear Channel 2  half transfer flag.
01781   * @rmtoll IFCR         CHTIF2        LL_DMA_ClearFlag_HT2
01782   * @param  DMAx DMAx Instance
01783   * @retval None
01784   */
01785 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
01786 {
01787   WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
01788 }
01789
01790 /**
01791   * @brief  Clear Channel 3  half transfer flag.
01792   * @rmtoll IFCR         CHTIF3        LL_DMA_ClearFlag_HT3
01793   * @param  DMAx DMAx Instance
01794   * @retval None
01795   */
01796 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
01797 {
01798   WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
01799 }
01800
01801 /**
01802   * @brief  Clear Channel 4  half transfer flag.
01803   * @rmtoll IFCR         CHTIF4        LL_DMA_ClearFlag_HT4
01804   * @param  DMAx DMAx Instance
01805   * @retval None
01806   */
01807 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
01808 {
01809   WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
01810 }
01811
01812 /**
01813   * @brief  Clear Channel 5  half transfer flag.
01814   * @rmtoll IFCR         CHTIF5        LL_DMA_ClearFlag_HT5
01815   * @param  DMAx DMAx Instance
01816   * @retval None
01817   */
01818 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
01819 {
01820   WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
01821 }
01822
01823 /**
01824   * @brief  Clear Channel 6  half transfer flag.
01825   * @rmtoll IFCR         CHTIF6        LL_DMA_ClearFlag_HT6
01826   * @param  DMAx DMAx Instance
01827   * @retval None
01828   */
01829 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
01830 {
01831   WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
01832 }
01833
01834 /**
01835   * @brief  Clear Channel 7  half transfer flag.
01836   * @rmtoll IFCR         CHTIF7        LL_DMA_ClearFlag_HT7
01837   * @param  DMAx DMAx Instance
01838   * @retval None
01839   */
01840 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
01841 {
01842   WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
01843 }
01844
01845 /**
01846   * @brief  Clear Channel 1 transfer error flag.
01847   * @rmtoll IFCR         CTEIF1        LL_DMA_ClearFlag_TE1
01848   * @param  DMAx DMAx Instance
01849   * @retval None
01850   */
01851 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
01852 {
01853   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
01854 }
01855
01856 /**
01857   * @brief  Clear Channel 2 transfer error flag.
01858   * @rmtoll IFCR         CTEIF2        LL_DMA_ClearFlag_TE2
01859   * @param  DMAx DMAx Instance
01860   * @retval None
01861   */
01862 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
01863 {
01864   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
01865 }
01866
01867 /**
01868   * @brief  Clear Channel 3 transfer error flag.
01869   * @rmtoll IFCR         CTEIF3        LL_DMA_ClearFlag_TE3
01870   * @param  DMAx DMAx Instance
01871   * @retval None
01872   */
01873 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
01874 {
01875   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
01876 }
01877
01878 /**
01879   * @brief  Clear Channel 4 transfer error flag.
01880   * @rmtoll IFCR         CTEIF4        LL_DMA_ClearFlag_TE4
01881   * @param  DMAx DMAx Instance
01882   * @retval None
01883   */
01884 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
01885 {
01886   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
01887 }
01888
01889 /**
01890   * @brief  Clear Channel 5 transfer error flag.
01891   * @rmtoll IFCR         CTEIF5        LL_DMA_ClearFlag_TE5
01892   * @param  DMAx DMAx Instance
01893   * @retval None
01894   */
01895 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
01896 {
01897   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
01898 }
01899
01900 /**
01901   * @brief  Clear Channel 6 transfer error flag.
01902   * @rmtoll IFCR         CTEIF6        LL_DMA_ClearFlag_TE6
01903   * @param  DMAx DMAx Instance
01904   * @retval None
01905   */
01906 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
01907 {
01908   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
01909 }
01910
01911 /**
01912   * @brief  Clear Channel 7 transfer error flag.
01913   * @rmtoll IFCR         CTEIF7        LL_DMA_ClearFlag_TE7
01914   * @param  DMAx DMAx Instance
01915   * @retval None
01916   */
01917 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
01918 {
01919   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
01920 }
01921
01922 /**
01923   * @}
01924   */
01925
01926 /** @defgroup DMA_LL_EF_IT_Management IT_Management
01927   * @{
01928   */
01929 /**
01930   * @brief  Enable Transfer complete interrupt.
01931   * @rmtoll CCR          TCIE          LL_DMA_EnableIT_TC
01932   * @param  DMAx DMAx Instance
01933   * @param  Channel This parameter can be one of the following values:
01934   *         @arg @ref LL_DMA_CHANNEL_1
01935   *         @arg @ref LL_DMA_CHANNEL_2
01936   *         @arg @ref LL_DMA_CHANNEL_3
01937   *         @arg @ref LL_DMA_CHANNEL_4
01938   *         @arg @ref LL_DMA_CHANNEL_5
01939   *         @arg @ref LL_DMA_CHANNEL_6
01940   *         @arg @ref LL_DMA_CHANNEL_7
01941   * @retval None
01942   */
01943 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
01944 {
01945   SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TCIE);
01946 }
01947
01948 /**
01949   * @brief  Enable Half transfer interrupt.
01950   * @rmtoll CCR          HTIE          LL_DMA_EnableIT_HT
01951   * @param  DMAx DMAx Instance
01952   * @param  Channel This parameter can be one of the following values:
01953   *         @arg @ref LL_DMA_CHANNEL_1
01954   *         @arg @ref LL_DMA_CHANNEL_2
01955   *         @arg @ref LL_DMA_CHANNEL_3
01956   *         @arg @ref LL_DMA_CHANNEL_4
01957   *         @arg @ref LL_DMA_CHANNEL_5
01958   *         @arg @ref LL_DMA_CHANNEL_6
01959   *         @arg @ref LL_DMA_CHANNEL_7
01960   * @retval None
01961   */
01962 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
01963 {
01964   SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_HTIE);
01965 }
01966
01967 /**
01968   * @brief  Enable Transfer error interrupt.
01969   * @rmtoll CCR          TEIE          LL_DMA_EnableIT_TE
01970   * @param  DMAx DMAx Instance
01971   * @param  Channel This parameter can be one of the following values:
01972   *         @arg @ref LL_DMA_CHANNEL_1
01973   *         @arg @ref LL_DMA_CHANNEL_2
01974   *         @arg @ref LL_DMA_CHANNEL_3
01975   *         @arg @ref LL_DMA_CHANNEL_4
01976   *         @arg @ref LL_DMA_CHANNEL_5
01977   *         @arg @ref LL_DMA_CHANNEL_6
01978   *         @arg @ref LL_DMA_CHANNEL_7
01979   * @retval None
01980   */
01981 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
01982 {
01983   SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE);
01984 }
01985
01986 /**
01987   * @brief  Disable Transfer complete interrupt.
01988   * @rmtoll CCR          TCIE          LL_DMA_DisableIT_TC
01989   * @param  DMAx DMAx Instance
01990   * @param  Channel This parameter can be one of the following values:
01991   *         @arg @ref LL_DMA_CHANNEL_1
01992   *         @arg @ref LL_DMA_CHANNEL_2
01993   *         @arg @ref LL_DMA_CHANNEL_3
01994   *         @arg @ref LL_DMA_CHANNEL_4
01995   *         @arg @ref LL_DMA_CHANNEL_5
01996   *         @arg @ref LL_DMA_CHANNEL_6
01997   *         @arg @ref LL_DMA_CHANNEL_7
01998   * @retval None
01999   */
02000 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
02001 {
02002   CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TCIE);
02003 }
02004
02005 /**
02006   * @brief  Disable Half transfer interrupt.
02007   * @rmtoll CCR          HTIE          LL_DMA_DisableIT_HT
02008   * @param  DMAx DMAx Instance
02009   * @param  Channel This parameter can be one of the following values:
02010   *         @arg @ref LL_DMA_CHANNEL_1
02011   *         @arg @ref LL_DMA_CHANNEL_2
02012   *         @arg @ref LL_DMA_CHANNEL_3
02013   *         @arg @ref LL_DMA_CHANNEL_4
02014   *         @arg @ref LL_DMA_CHANNEL_5
02015   *         @arg @ref LL_DMA_CHANNEL_6
02016   *         @arg @ref LL_DMA_CHANNEL_7
02017   * @retval None
02018   */
02019 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
02020 {
02021   CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_HTIE);
02022 }
02023
02024 /**
02025   * @brief  Disable Transfer error interrupt.
02026   * @rmtoll CCR          TEIE          LL_DMA_DisableIT_TE
02027   * @param  DMAx DMAx Instance
02028   * @param  Channel This parameter can be one of the following values:
02029   *         @arg @ref LL_DMA_CHANNEL_1
02030   *         @arg @ref LL_DMA_CHANNEL_2
02031   *         @arg @ref LL_DMA_CHANNEL_3
02032   *         @arg @ref LL_DMA_CHANNEL_4
02033   *         @arg @ref LL_DMA_CHANNEL_5
02034   *         @arg @ref LL_DMA_CHANNEL_6
02035   *         @arg @ref LL_DMA_CHANNEL_7
02036   * @retval None
02037   */
02038 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
02039 {
02040   CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE);
02041 }
02042
02043 /**
02044   * @brief  Check if Transfer complete Interrupt is enabled.
02045   * @rmtoll CCR          TCIE          LL_DMA_IsEnabledIT_TC
02046   * @param  DMAx DMAx Instance
02047   * @param  Channel This parameter can be one of the following values:
02048   *         @arg @ref LL_DMA_CHANNEL_1
02049   *         @arg @ref LL_DMA_CHANNEL_2
02050   *         @arg @ref LL_DMA_CHANNEL_3
02051   *         @arg @ref LL_DMA_CHANNEL_4
02052   *         @arg @ref LL_DMA_CHANNEL_5
02053   *         @arg @ref LL_DMA_CHANNEL_6
02054   *         @arg @ref LL_DMA_CHANNEL_7
02055   * @retval State of bit (1 or 0).
02056   */
02057 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
02058 {
02059   return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
02060                    DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL);
02061 }
02062
02063 /**
02064   * @brief  Check if Half transfer Interrupt is enabled.
02065   * @rmtoll CCR          HTIE          LL_DMA_IsEnabledIT_HT
02066   * @param  DMAx DMAx Instance
02067   * @param  Channel This parameter can be one of the following values:
02068   *         @arg @ref LL_DMA_CHANNEL_1
02069   *         @arg @ref LL_DMA_CHANNEL_2
02070   *         @arg @ref LL_DMA_CHANNEL_3
02071   *         @arg @ref LL_DMA_CHANNEL_4
02072   *         @arg @ref LL_DMA_CHANNEL_5
02073   *         @arg @ref LL_DMA_CHANNEL_6
02074   *         @arg @ref LL_DMA_CHANNEL_7
02075   * @retval State of bit (1 or 0).
02076   */
02077 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
02078 {
02079   return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
02080                    DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL);
02081 }
02082
02083 /**
02084   * @brief  Check if Transfer error Interrupt is enabled.
02085   * @rmtoll CCR          TEIE          LL_DMA_IsEnabledIT_TE
02086   * @param  DMAx DMAx Instance
02087   * @param  Channel This parameter can be one of the following values:
02088   *         @arg @ref LL_DMA_CHANNEL_1
02089   *         @arg @ref LL_DMA_CHANNEL_2
02090   *         @arg @ref LL_DMA_CHANNEL_3
02091   *         @arg @ref LL_DMA_CHANNEL_4
02092   *         @arg @ref LL_DMA_CHANNEL_5
02093   *         @arg @ref LL_DMA_CHANNEL_6
02094   *         @arg @ref LL_DMA_CHANNEL_7
02095   * @retval State of bit (1 or 0).
02096   */
02097 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
02098 {
02099   return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
02100                    DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL);
02101 }
02102
02103 /**
02104   * @}
02105   */
02106
02107 #if defined(USE_FULL_LL_DRIVER)
02108 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
02109   * @{
02110   */
02111
02112 ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
02113 ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
02114 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
02115
02116 /**
02117   * @}
02118   */
02119 #endif /* USE_FULL_LL_DRIVER */
02120
02121 /**
02122   * @}
02123   */
02124
02125 /**
02126   * @}
02127   */
02128
02129 #endif /* DMA1 || DMA2 */
02130
02131 /**
02132   * @}
02133   */
02134
02135 #ifdef __cplusplus
02136 }
02137 #endif
02138
02139 #endif /* STM32WBxx_LL_DMA_H */
02140
02141 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_dmamux.h Source File

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stm32wbxx_ll_dmamux.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_dmamux.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DMAMUX LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_LL_DMAMUX_H
00022 #define STM32WBxx_LL_DMAMUX_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx.h"
00030
00031 /** @addtogroup STM32WBxx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (DMAMUX1)
00036
00037 /** @defgroup DMAMUX_LL DMAMUX
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /** @defgroup DMAMUX_LL_Private_Constants DMAMUX Private Constants
00045   * @{
00046   */
00047 /* Define used to get DMAMUX CCR register size */
00048 #define DMAMUX_CCR_SIZE                   0x00000004UL
00049
00050 /* Define used to get DMAMUX RGCR register size */
00051 #define DMAMUX_RGCR_SIZE                  0x00000004UL
00052 /**
00053   * @}
00054   */
00055
00056 /* Private macros ------------------------------------------------------------*/
00057 /* Exported types ------------------------------------------------------------*/
00058 /* Exported constants --------------------------------------------------------*/
00059 /** @defgroup DMAMUX_LL_Exported_Constants DMAMUX Exported Constants
00060   * @{
00061   */
00062 /** @defgroup DMAMUX_LL_EC_CLEAR_FLAG Clear Flags Defines
00063   * @brief    Flags defines which can be used with LL_DMAMUX_WriteReg function
00064   * @{
00065   */
00066 #define LL_DMAMUX_CFR_CSOF0               DMAMUX_CFR_CSOF0       /*!< Synchronization Event Overrun Flag Channel 0  */
00067 #define LL_DMAMUX_CFR_CSOF1               DMAMUX_CFR_CSOF1       /*!< Synchronization Event Overrun Flag Channel 1  */
00068 #define LL_DMAMUX_CFR_CSOF2               DMAMUX_CFR_CSOF2       /*!< Synchronization Event Overrun Flag Channel 2  */
00069 #define LL_DMAMUX_CFR_CSOF3               DMAMUX_CFR_CSOF3       /*!< Synchronization Event Overrun Flag Channel 3  */
00070 #define LL_DMAMUX_CFR_CSOF4               DMAMUX_CFR_CSOF4       /*!< Synchronization Event Overrun Flag Channel 4  */
00071 #define LL_DMAMUX_CFR_CSOF5               DMAMUX_CFR_CSOF5       /*!< Synchronization Event Overrun Flag Channel 5  */
00072 #define LL_DMAMUX_CFR_CSOF6               DMAMUX_CFR_CSOF6       /*!< Synchronization Event Overrun Flag Channel 6  */
00073 #if defined(DMA2)
00074 #define LL_DMAMUX_CFR_CSOF7               DMAMUX_CFR_CSOF7       /*!< Synchronization Event Overrun Flag Channel 7  */
00075 #define LL_DMAMUX_CFR_CSOF8               DMAMUX_CFR_CSOF8       /*!< Synchronization Event Overrun Flag Channel 8  */
00076 #define LL_DMAMUX_CFR_CSOF9               DMAMUX_CFR_CSOF9       /*!< Synchronization Event Overrun Flag Channel 9  */
00077 #define LL_DMAMUX_CFR_CSOF10              DMAMUX_CFR_CSOF10      /*!< Synchronization Event Overrun Flag Channel 10 */
00078 #define LL_DMAMUX_CFR_CSOF11              DMAMUX_CFR_CSOF11      /*!< Synchronization Event Overrun Flag Channel 11 */
00079 #define LL_DMAMUX_CFR_CSOF12              DMAMUX_CFR_CSOF12      /*!< Synchronization Event Overrun Flag Channel 12 */
00080 #define LL_DMAMUX_CFR_CSOF13              DMAMUX_CFR_CSOF13      /*!< Synchronization Event Overrun Flag Channel 13 */
00081 #endif
00082 #define LL_DMAMUX_RGCFR_RGCOF0            DMAMUX_RGCFR_COF0      /*!< Request Generator 0 Trigger Event Overrun Flag */
00083 #define LL_DMAMUX_RGCFR_RGCOF1            DMAMUX_RGCFR_COF1      /*!< Request Generator 1 Trigger Event Overrun Flag */
00084 #define LL_DMAMUX_RGCFR_RGCOF2            DMAMUX_RGCFR_COF2      /*!< Request Generator 2 Trigger Event Overrun Flag */
00085 #define LL_DMAMUX_RGCFR_RGCOF3            DMAMUX_RGCFR_COF3      /*!< Request Generator 3 Trigger Event Overrun Flag */
00086 /**
00087   * @}
00088   */
00089
00090 /** @defgroup DMAMUX_LL_EC_GET_FLAG Get Flags Defines
00091   * @brief    Flags defines which can be used with LL_DMAMUX_ReadReg function
00092   * @{
00093   */
00094 #define LL_DMAMUX_CSR_SOF0                DMAMUX_CSR_SOF0       /*!< Synchronization Event Overrun Flag Channel 0  */
00095 #define LL_DMAMUX_CSR_SOF1                DMAMUX_CSR_SOF1       /*!< Synchronization Event Overrun Flag Channel 1  */
00096 #define LL_DMAMUX_CSR_SOF2                DMAMUX_CSR_SOF2       /*!< Synchronization Event Overrun Flag Channel 2  */
00097 #define LL_DMAMUX_CSR_SOF3                DMAMUX_CSR_SOF3       /*!< Synchronization Event Overrun Flag Channel 3  */
00098 #define LL_DMAMUX_CSR_SOF4                DMAMUX_CSR_SOF4       /*!< Synchronization Event Overrun Flag Channel 4  */
00099 #define LL_DMAMUX_CSR_SOF5                DMAMUX_CSR_SOF5       /*!< Synchronization Event Overrun Flag Channel 5  */
00100 #define LL_DMAMUX_CSR_SOF6                DMAMUX_CSR_SOF6       /*!< Synchronization Event Overrun Flag Channel 6  */
00101 #if defined(DMA2)
00102 #define LL_DMAMUX_CSR_SOF7                DMAMUX_CSR_SOF7       /*!< Synchronization Event Overrun Flag Channel 7  */
00103 #define LL_DMAMUX_CSR_SOF8                DMAMUX_CSR_SOF8       /*!< Synchronization Event Overrun Flag Channel 8  */
00104 #define LL_DMAMUX_CSR_SOF9                DMAMUX_CSR_SOF9       /*!< Synchronization Event Overrun Flag Channel 9  */
00105 #define LL_DMAMUX_CSR_SOF10               DMAMUX_CSR_SOF10      /*!< Synchronization Event Overrun Flag Channel 10 */
00106 #define LL_DMAMUX_CSR_SOF11               DMAMUX_CSR_SOF11      /*!< Synchronization Event Overrun Flag Channel 11 */
00107 #define LL_DMAMUX_CSR_SOF12               DMAMUX_CSR_SOF12      /*!< Synchronization Event Overrun Flag Channel 12 */
00108 #define LL_DMAMUX_CSR_SOF13               DMAMUX_CSR_SOF13      /*!< Synchronization Event Overrun Flag Channel 13 */
00109 #endif
00110 #define LL_DMAMUX_RGSR_RGOF0              DMAMUX_RGSR_OF0       /*!< Request Generator 0 Trigger Event Overrun Flag */
00111 #define LL_DMAMUX_RGSR_RGOF1              DMAMUX_RGSR_OF1       /*!< Request Generator 1 Trigger Event Overrun Flag */
00112 #define LL_DMAMUX_RGSR_RGOF2              DMAMUX_RGSR_OF2       /*!< Request Generator 2 Trigger Event Overrun Flag */
00113 #define LL_DMAMUX_RGSR_RGOF3              DMAMUX_RGSR_OF3       /*!< Request Generator 3 Trigger Event Overrun Flag */
00114 /**
00115   * @}
00116   */
00117
00118 /** @defgroup DMAMUX_LL_EC_IT IT Defines
00119   * @brief    IT defines which can be used with LL_DMA_ReadReg and  LL_DMAMUX_WriteReg functions
00120   * @{
00121   */
00122 #define LL_DMAMUX_CCR_SOIE                DMAMUX_CxCR_SOIE          /*!< Synchronization Event Overrun Interrupt */
00123 #define LL_DMAMUX_RGCR_RGOIE              DMAMUX_RGxCR_OIE          /*!< Request Generation Trigger Event Overrun Interrupt    */
00124 /**
00125   * @}
00126   */
00127
00128 /** @defgroup DMAMUX_LL_EC_REQUEST Transfer request
00129   * @{
00130   */
00131 #define LL_DMAMUX_REQ_MEM2MEM             0x00000000U  /*!< memory to memory transfer  */
00132 #define LL_DMAMUX_REQ_GENERATOR0          0x00000001U  /*!< DMAMUX request generator 0 */
00133 #define LL_DMAMUX_REQ_GENERATOR1          0x00000002U  /*!< DMAMUX request generator 1 */
00134 #define LL_DMAMUX_REQ_GENERATOR2          0x00000003U  /*!< DMAMUX request generator 2 */
00135 #define LL_DMAMUX_REQ_GENERATOR3          0x00000004U  /*!< DMAMUX request generator 3 */
00136 #define LL_DMAMUX_REQ_ADC1                0x00000005U  /*!< DMAMUX ADC1 request        */
00137 #define LL_DMAMUX_REQ_SPI1_RX             0x00000006U  /*!< DMAMUX SPI1 RX request     */
00138 #define LL_DMAMUX_REQ_SPI1_TX             0x00000007U  /*!< DMAMUX SPI1 TX request     */
00139 #if defined(SPI2)
00140 #define LL_DMAMUX_REQ_SPI2_RX             0x00000008U  /*!< DMAMUX SPI2 RX request     */
00141 #define LL_DMAMUX_REQ_SPI2_TX             0x00000009U  /*!< DMAMUX SPI2 TX request     */
00142 #endif
00143 #define LL_DMAMUX_REQ_I2C1_RX             0x0000000AU  /*!< DMAMUX I2C1 RX request     */
00144 #define LL_DMAMUX_REQ_I2C1_TX             0x0000000BU  /*!< DMAMUX I2C1 TX request     */
00145 #if defined(I2C3)
00146 #define LL_DMAMUX_REQ_I2C3_RX             0x0000000CU  /*!< DMAMUX I2C3 RX request     */
00147 #define LL_DMAMUX_REQ_I2C3_TX             0x0000000DU  /*!< DMAMUX I2C3 TX request     */
00148 #endif
00149 #define LL_DMAMUX_REQ_USART1_RX           0x0000000EU  /*!< DMAMUX USART1 RX request   */
00150 #define LL_DMAMUX_REQ_USART1_TX           0x0000000FU  /*!< DMAMUX USART1 TX request   */
00151 #if defined(LPUART1)
00152 #define LL_DMAMUX_REQ_LPUART1_RX          0x00000010U  /*!< DMAMUX LPUART1 RX request  */
00153 #define LL_DMAMUX_REQ_LPUART1_TX          0x00000011U  /*!< DMAMUX LPUART1 TX request  */
00154 #endif
00155 #if defined(SAI1)
00156 #define LL_DMAMUX_REQ_SAI1_A              0x00000012U  /*!< DMAMUX SAI1 A request      */
00157 #define LL_DMAMUX_REQ_SAI1_B              0x00000013U  /*!< DMAMUX SAI1 B request      */
00158 #endif
00159 #if defined(QUADSPI)
00160 #define LL_DMAMUX_REQ_QUADSPI             0x00000014U  /*!< DMAMUX QUADSPI request     */
00161 #endif
00162 #define LL_DMAMUX_REQ_TIM1_CH1            0x00000015U  /*!< DMAMUX TIM1 CH1 request    */
00163 #define LL_DMAMUX_REQ_TIM1_CH2            0x00000016U  /*!< DMAMUX TIM1 CH2 request    */
00164 #define LL_DMAMUX_REQ_TIM1_CH3            0x00000017U  /*!< DMAMUX TIM1 CH3 request    */
00165 #define LL_DMAMUX_REQ_TIM1_CH4            0x00000018U  /*!< DMAMUX TIM1 CH4 request    */
00166 #define LL_DMAMUX_REQ_TIM1_UP             0x00000019U  /*!< DMAMUX TIM1 UP request     */
00167 #define LL_DMAMUX_REQ_TIM1_TRIG           0x0000001AU  /*!< DMAMUX TIM1 TRIG request   */
00168 #define LL_DMAMUX_REQ_TIM1_COM            0x0000001BU  /*!< DMAMUX TIM1 COM request    */
00169 #define LL_DMAMUX_REQ_TIM2_CH1            0x0000001CU  /*!< DMAMUX TIM2 CH1 request    */
00170 #define LL_DMAMUX_REQ_TIM2_CH2            0x0000001DU  /*!< DMAMUX TIM2 CH2 request    */
00171 #define LL_DMAMUX_REQ_TIM2_CH3            0x0000001EU  /*!< DMAMUX TIM2 CH3 request    */
00172 #define LL_DMAMUX_REQ_TIM2_CH4            0x0000001FU  /*!< DMAMUX TIM2 CH4 request    */
00173 #define LL_DMAMUX_REQ_TIM2_UP             0x00000020U  /*!< DMAMUX TIM2 UP request     */
00174 #define LL_DMAMUX_REQ_TIM16_CH1           0x00000021U  /*!< DMAMUX TIM16 CH1 request   */
00175 #define LL_DMAMUX_REQ_TIM16_UP            0x00000022U  /*!< DMAMUX TIM16 UP request    */
00176 #define LL_DMAMUX_REQ_TIM17_CH1           0x00000023U  /*!< DMAMUX TIM17 CH1 request   */
00177 #define LL_DMAMUX_REQ_TIM17_UP            0x00000024U  /*!< DMAMUX TIM17 UP request    */
00178 #if defined(AES1)
00179 #define LL_DMAMUX_REQ_AES1_IN             0x00000025U  /*!< DMAMUX AES1_IN request     */
00180 #define LL_DMAMUX_REQ_AES1_OUT            0x00000026U  /*!< DMAMUX AES1_OUT request    */
00181 #endif
00182 #define LL_DMAMUX_REQ_AES2_IN             0x00000027U  /*!< DMAMUX AES2_IN request     */
00183 #define LL_DMAMUX_REQ_AES2_OUT            0x00000028U  /*!< DMAMUX AES2_OUT request    */
00184 /**
00185   * @}
00186   */
00187
00188 /** @defgroup DMAMUX_LL_EC_CHANNEL DMAMUX Channel
00189   * @{
00190   */
00191 #define LL_DMAMUX_CHANNEL_0               0x00000000U               /*!< DMAMUX Channel 0 connected to DMA1 Channel 1  */
00192 #define LL_DMAMUX_CHANNEL_1               0x00000001U               /*!< DMAMUX Channel 1 connected to DMA1 Channel 2  */
00193 #define LL_DMAMUX_CHANNEL_2               0x00000002U               /*!< DMAMUX Channel 2 connected to DMA1 Channel 3  */
00194 #define LL_DMAMUX_CHANNEL_3               0x00000003U               /*!< DMAMUX Channel 3 connected to DMA1 Channel 4  */
00195 #define LL_DMAMUX_CHANNEL_4               0x00000004U               /*!< DMAMUX Channel 4 connected to DMA1 Channel 5  */
00196 #define LL_DMAMUX_CHANNEL_5               0x00000005U               /*!< DMAMUX Channel 5 connected to DMA1 Channel 6  */
00197 #define LL_DMAMUX_CHANNEL_6               0x00000006U               /*!< DMAMUX Channel 6 connected to DMA1 Channel 7  */
00198 #if defined(DMA2)
00199 #define LL_DMAMUX_CHANNEL_7               0x00000007U               /*!< DMAMUX Channel 7 connected to DMA2 Channel 1  */
00200 #define LL_DMAMUX_CHANNEL_8               0x00000008U               /*!< DMAMUX Channel 8 connected to DMA2 Channel 2  */
00201 #define LL_DMAMUX_CHANNEL_9               0x00000009U               /*!< DMAMUX Channel 9 connected to DMA2 Channel 3  */
00202 #define LL_DMAMUX_CHANNEL_10              0x0000000AU               /*!< DMAMUX Channel 10 connected to DMA2 Channel 4 */
00203 #define LL_DMAMUX_CHANNEL_11              0x0000000BU               /*!< DMAMUX Channel 11 connected to DMA2 Channel 5 */
00204 #define LL_DMAMUX_CHANNEL_12              0x0000000CU               /*!< DMAMUX Channel 12 connected to DMA2 Channel 6 */
00205 #define LL_DMAMUX_CHANNEL_13              0x0000000DU               /*!< DMAMUX Channel 13 connected to DMA2 Channel 7 */
00206 #endif
00207 /**
00208   * @}
00209   */
00210
00211 /** @defgroup DMAMUX_LL_EC_SYNC_NO Synchronization Signal Polarity
00212   * @{
00213   */
00214 #define LL_DMAMUX_SYNC_NO_EVENT            0x00000000U                               /*!< All requests are blocked   */
00215 #define LL_DMAMUX_SYNC_POL_RISING          DMAMUX_CxCR_SPOL_0                        /*!< Synchronization on event on rising edge */
00216 #define LL_DMAMUX_SYNC_POL_FALLING         DMAMUX_CxCR_SPOL_1                        /*!< Synchronization on event on falling edge */
00217 #define LL_DMAMUX_SYNC_POL_RISING_FALLING  (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1) /*!< Synchronization on event on rising and falling edge */
00218 /**
00219   * @}
00220   */
00221
00222 /** @defgroup DMAMUX_LL_EC_SYNC_EVT Synchronization Signal Event
00223   * @{
00224   */
00225 #define LL_DMAMUX_SYNC_EXTI_LINE0         0x00000000U                                                                                     /*!< Synchronization signal from EXTI Line0  */
00226 #define LL_DMAMUX_SYNC_EXTI_LINE1         DMAMUX_CxCR_SYNC_ID_0                                                                           /*!< Synchronization signal from EXTI Line1  */
00227 #define LL_DMAMUX_SYNC_EXTI_LINE2         DMAMUX_CxCR_SYNC_ID_1                                                                           /*!< Synchronization signal from EXTI Line2  */
00228 #define LL_DMAMUX_SYNC_EXTI_LINE3         (DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)                                                 /*!< Synchronization signal from EXTI Line3  */
00229 #define LL_DMAMUX_SYNC_EXTI_LINE4         DMAMUX_CxCR_SYNC_ID_2                                                                           /*!< Synchronization signal from EXTI Line4  */
00230 #define LL_DMAMUX_SYNC_EXTI_LINE5         (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0)                                                 /*!< Synchronization signal from EXTI Line5  */
00231 #define LL_DMAMUX_SYNC_EXTI_LINE6         (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1)                                                 /*!< Synchronization signal from EXTI Line6  */
00232 #define LL_DMAMUX_SYNC_EXTI_LINE7         (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)                         /*!< Synchronization signal from EXTI Line7  */
00233 #define LL_DMAMUX_SYNC_EXTI_LINE8         DMAMUX_CxCR_SYNC_ID_3                                                                           /*!< Synchronization signal from EXTI Line8  */
00234 #define LL_DMAMUX_SYNC_EXTI_LINE9         (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_0)                                                 /*!< Synchronization signal from EXTI Line9  */
00235 #define LL_DMAMUX_SYNC_EXTI_LINE10        (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1)                                                 /*!< Synchronization signal from EXTI Line10 */
00236 #define LL_DMAMUX_SYNC_EXTI_LINE11        (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)                         /*!< Synchronization signal from EXTI Line11 */
00237 #define LL_DMAMUX_SYNC_EXTI_LINE12        (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2)                                                 /*!< Synchronization signal from EXTI Line12 */
00238 #define LL_DMAMUX_SYNC_EXTI_LINE13        (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0)                         /*!< Synchronization signal from EXTI Line13 */
00239 #define LL_DMAMUX_SYNC_EXTI_LINE14        (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1)                         /*!< Synchronization signal from EXTI Line14 */
00240 #define LL_DMAMUX_SYNC_EXTI_LINE15        (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line15 */
00241 #define LL_DMAMUX_SYNC_DMAMUX_CH0         DMAMUX_CxCR_SYNC_ID_4                                                                           /*!< Synchronization signal from DMAMUX channel0 Event */
00242 #define LL_DMAMUX_SYNC_DMAMUX_CH1         (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_0)                                                 /*!< Synchronization signal from DMAMUX channel1 Event */
00243 #define LL_DMAMUX_SYNC_LPTIM1_OUT         (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1)                                                 /*!< Synchronization signal from LPTIM1 Ouput */
00244 #define LL_DMAMUX_SYNC_LPTIM2_OUT         (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)                         /*!< Synchronization signal from LPTIM2 Ouput */
00245 /**
00246   * @}
00247   */
00248
00249 /** @defgroup DMAMUX_LL_EC_REQUEST_GENERATOR Request Generator Channel
00250   * @{
00251   */
00252 #define LL_DMAMUX_REQ_GEN_0               0x00000000U
00253 #define LL_DMAMUX_REQ_GEN_1               0x00000001U
00254 #define LL_DMAMUX_REQ_GEN_2               0x00000002U
00255 #define LL_DMAMUX_REQ_GEN_3               0x00000003U
00256 /**
00257   * @}
00258   */
00259
00260 /** @defgroup DMAMUX_LL_EC_REQUEST_GEN_POLARITY External Request Signal Generation Polarity
00261   * @{
00262   */
00263 #define LL_DMAMUX_REQ_GEN_NO_EVENT             0x00000000U                                  /*!< No external DMA request  generation */
00264 #define LL_DMAMUX_REQ_GEN_POL_RISING           DMAMUX_RGxCR_GPOL_0                          /*!< External DMA request generation on event on rising edge */
00265 #define LL_DMAMUX_REQ_GEN_POL_FALLING          DMAMUX_RGxCR_GPOL_1                          /*!< External DMA request generation on event on falling edge */
00266 #define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING   (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1)  /*!< External DMA request generation on rising and falling edge */
00267 /**
00268   * @}
00269   */
00270
00271 /** @defgroup DMAMUX_LL_EC_REQUEST_GEN External Request Signal Generation
00272   * @{
00273   */
00274 #define LL_DMAMUX_REQ_GEN_EXTI_LINE0      0x00000000U                                                                                     /*!< Request signal generation from EXTI Line0  */
00275 #define LL_DMAMUX_REQ_GEN_EXTI_LINE1      DMAMUX_RGxCR_SIG_ID_0                                                                           /*!< Request signal generation from EXTI Line1  */
00276 #define LL_DMAMUX_REQ_GEN_EXTI_LINE2      DMAMUX_RGxCR_SIG_ID_1                                                                           /*!< Request signal generation from EXTI Line2  */
00277 #define LL_DMAMUX_REQ_GEN_EXTI_LINE3      (DMAMUX_RGxCR_SIG_ID_1 |DMAMUX_RGxCR_SIG_ID_0)                                                  /*!< Request signal generation from EXTI Line3  */
00278 #define LL_DMAMUX_REQ_GEN_EXTI_LINE4      DMAMUX_RGxCR_SIG_ID_2                                                                           /*!< Request signal generation from EXTI Line4  */
00279 #define LL_DMAMUX_REQ_GEN_EXTI_LINE5      (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0)                                                 /*!< Request signal generation from EXTI Line5  */
00280 #define LL_DMAMUX_REQ_GEN_EXTI_LINE6      (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1)                                                 /*!< Request signal generation from EXTI Line6  */
00281 #define LL_DMAMUX_REQ_GEN_EXTI_LINE7      (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)                         /*!< Request signal generation from EXTI Line7  */
00282 #define LL_DMAMUX_REQ_GEN_EXTI_LINE8      DMAMUX_RGxCR_SIG_ID_3                                                                           /*!< Request signal generation from EXTI Line8  */
00283 #define LL_DMAMUX_REQ_GEN_EXTI_LINE9      (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_0)                                                 /*!< Request signal generation from EXTI Line9  */
00284 #define LL_DMAMUX_REQ_GEN_EXTI_LINE10     (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1)                                                 /*!< Request signal generation from EXTI Line10 */
00285 #define LL_DMAMUX_REQ_GEN_EXTI_LINE11     (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)                         /*!< Request signal generation from EXTI Line11 */
00286 #define LL_DMAMUX_REQ_GEN_EXTI_LINE12     (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2)                                                 /*!< Request signal generation from EXTI Line12 */
00287 #define LL_DMAMUX_REQ_GEN_EXTI_LINE13     (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0)                         /*!< Request signal generation from EXTI Line13 */
00288 #define LL_DMAMUX_REQ_GEN_EXTI_LINE14     (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1)                         /*!< Request signal generation from EXTI Line14 */
00289 #define LL_DMAMUX_REQ_GEN_EXTI_LINE15     (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line15 */
00290 #define LL_DMAMUX_REQ_GEN_DMAMUX_CH0      DMAMUX_RGxCR_SIG_ID_4                                                                           /*!< Request signal generation from DMAMUX channel0 Event */
00291 #define LL_DMAMUX_REQ_GEN_DMAMUX_CH1      (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_0)                                                 /*!< Request signal generation from DMAMUX channel1 Event */
00292 #define LL_DMAMUX_REQ_GEN_LPTIM1_OUT      (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1)                                                 /*!< Request signal generation from LPTIM1 Ouput */
00293 #define LL_DMAMUX_REQ_GEN_LPTIM2_OUT      (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)                         /*!< Request signal generation from LPTIM2 Ouput */
00294 /**
00295   * @}
00296   */
00297
00298 /**
00299   * @}
00300   */
00301
00302 /* Exported macro ------------------------------------------------------------*/
00303 /** @defgroup DMAMUX_LL_Exported_Macros DMAMUX Exported Macros
00304   * @{
00305   */
00306
00307 /** @defgroup DMAMUX_LL_EM_WRITE_READ Common Write and read registers macros
00308   * @{
00309   */
00310 /**
00311   * @brief  Write a value in DMAMUX register
00312   * @param  __INSTANCE__ DMAMUX Instance
00313   * @param  __REG__ Register to be written
00314   * @param  __VALUE__ Value to be written in the register
00315   * @retval None
00316   */
00317 #define LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00318
00319 /**
00320   * @brief  Read a value in DMAMUX register
00321   * @param  __INSTANCE__ DMAMUX Instance
00322   * @param  __REG__ Register to be read
00323   * @retval Register value
00324   */
00325 #define LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00326 /**
00327   * @}
00328   */
00329
00330 /**
00331   * @}
00332   */
00333
00334 /* Exported functions --------------------------------------------------------*/
00335 /** @defgroup DMAMUX_LL_Exported_Functions DMAMUX Exported Functions
00336  * @{
00337  */
00338
00339 /** @defgroup DMAMUX_LL_EF_Configuration Configuration
00340   * @{
00341   */
00342 /**
00343   * @brief  Set DMAMUX request ID for DMAMUX Channel x.
00344   * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
00345 #if defined(DMA2)
00346   *         DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7.
00347 #endif
00348   * @rmtoll CxCR         DMAREQ_ID     LL_DMAMUX_SetRequestID
00349   * @param  DMAMUXx DMAMUXx Instance
00350   * @param  Channel This parameter can be one of the following values:
00351   *         @arg @ref LL_DMAMUX_CHANNEL_0
00352   *         @arg @ref LL_DMAMUX_CHANNEL_1
00353   *         @arg @ref LL_DMAMUX_CHANNEL_2
00354   *         @arg @ref LL_DMAMUX_CHANNEL_3
00355   *         @arg @ref LL_DMAMUX_CHANNEL_4
00356   *         @arg @ref LL_DMAMUX_CHANNEL_5
00357   *         @arg @ref LL_DMAMUX_CHANNEL_6
00358 #if defined(DMA2)
00359   *         @arg @ref LL_DMAMUX_CHANNEL_7
00360   *         @arg @ref LL_DMAMUX_CHANNEL_8
00361   *         @arg @ref LL_DMAMUX_CHANNEL_9
00362   *         @arg @ref LL_DMAMUX_CHANNEL_10
00363   *         @arg @ref LL_DMAMUX_CHANNEL_11
00364   *         @arg @ref LL_DMAMUX_CHANNEL_12
00365   *         @arg @ref LL_DMAMUX_CHANNEL_13
00366 #endif
00367   * @param  Request This parameter can be one of the following values:
00368   *         @arg @ref LL_DMAMUX_REQ_MEM2MEM
00369   *         @arg @ref LL_DMAMUX_REQ_GENERATOR0
00370   *         @arg @ref LL_DMAMUX_REQ_GENERATOR1
00371   *         @arg @ref LL_DMAMUX_REQ_GENERATOR2
00372   *         @arg @ref LL_DMAMUX_REQ_GENERATOR3
00373   *         @arg @ref LL_DMAMUX_REQ_ADC1
00374   *         @arg @ref LL_DMAMUX_REQ_SPI1_RX
00375   *         @arg @ref LL_DMAMUX_REQ_SPI1_TX
00376   *         @arg @ref LL_DMAMUX_REQ_SPI2_RX
00377   *         @arg @ref LL_DMAMUX_REQ_SPI2_TX
00378   *         @arg @ref LL_DMAMUX_REQ_I2C1_RX
00379   *         @arg @ref LL_DMAMUX_REQ_I2C1_TX
00380   *         @arg @ref LL_DMAMUX_REQ_I2C3_RX
00381   *         @arg @ref LL_DMAMUX_REQ_I2C3_TX
00382   *         @arg @ref LL_DMAMUX_REQ_USART1_RX
00383   *         @arg @ref LL_DMAMUX_REQ_USART1_TX
00384   *         @arg @ref LL_DMAMUX_REQ_LPUART1_RX
00385   *         @arg @ref LL_DMAMUX_REQ_LPUART1_TX
00386   *         @arg @ref LL_DMAMUX_REQ_SAI1_A
00387   *         @arg @ref LL_DMAMUX_REQ_SAI1_B
00388   *         @arg @ref LL_DMAMUX_REQ_QUADSPI
00389   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH1
00390   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH2
00391   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH3
00392   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH4
00393   *         @arg @ref LL_DMAMUX_REQ_TIM1_UP
00394   *         @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
00395   *         @arg @ref LL_DMAMUX_REQ_TIM1_COM
00396   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH1
00397   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH2
00398   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH3
00399   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH4
00400   *         @arg @ref LL_DMAMUX_REQ_TIM2_UP
00401   *         @arg @ref LL_DMAMUX_REQ_TIM16_CH1
00402   *         @arg @ref LL_DMAMUX_REQ_TIM16_UP
00403   *         @arg @ref LL_DMAMUX_REQ_TIM17_CH1
00404   *         @arg @ref LL_DMAMUX_REQ_TIM17_UP
00405   *         @arg @ref LL_DMAMUX_REQ_AES1_IN
00406   *         @arg @ref LL_DMAMUX_REQ_AES1_OUT
00407   *         @arg @ref LL_DMAMUX_REQ_AES2_IN
00408   *         @arg @ref LL_DMAMUX_REQ_AES2_OUT
00409   * @retval None
00410   */
00411 __STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef* DMAMUXx, uint32_t Channel, uint32_t Request)
00412 {
00413   (void)(DMAMUXx);
00414   MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
00415 }
00416
00417 /**
00418   * @brief  Get DMAMUX request ID for DMAMUX Channel x.
00419   * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
00420 #if defined(DMA2)
00421   *         DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7.
00422 #endif
00423   * @rmtoll CxCR         DMAREQ_ID     LL_DMAMUX_GetRequestID
00424   * @param  DMAMUXx DMAMUXx Instance
00425   * @param  Channel This parameter can be one of the following values:
00426   *         @arg @ref LL_DMAMUX_CHANNEL_0
00427   *         @arg @ref LL_DMAMUX_CHANNEL_1
00428   *         @arg @ref LL_DMAMUX_CHANNEL_2
00429   *         @arg @ref LL_DMAMUX_CHANNEL_3
00430   *         @arg @ref LL_DMAMUX_CHANNEL_4
00431   *         @arg @ref LL_DMAMUX_CHANNEL_5
00432   *         @arg @ref LL_DMAMUX_CHANNEL_6
00433   *         @arg @ref LL_DMAMUX_CHANNEL_7
00434   *         @arg @ref LL_DMAMUX_CHANNEL_8
00435   *         @arg @ref LL_DMAMUX_CHANNEL_9
00436   *         @arg @ref LL_DMAMUX_CHANNEL_10
00437   *         @arg @ref LL_DMAMUX_CHANNEL_11
00438   *         @arg @ref LL_DMAMUX_CHANNEL_12
00439   *         @arg @ref LL_DMAMUX_CHANNEL_13
00440   * @retval Returned value can be one of the following values:
00441   *         @arg @ref LL_DMAMUX_REQ_MEM2MEM
00442   *         @arg @ref LL_DMAMUX_REQ_GENERATOR0
00443   *         @arg @ref LL_DMAMUX_REQ_GENERATOR1
00444   *         @arg @ref LL_DMAMUX_REQ_GENERATOR2
00445   *         @arg @ref LL_DMAMUX_REQ_GENERATOR3
00446   *         @arg @ref LL_DMAMUX_REQ_ADC1
00447   *         @arg @ref LL_DMAMUX_REQ_SPI1_RX
00448   *         @arg @ref LL_DMAMUX_REQ_SPI1_TX
00449   *         @arg @ref LL_DMAMUX_REQ_SPI2_RX
00450   *         @arg @ref LL_DMAMUX_REQ_SPI2_TX
00451   *         @arg @ref LL_DMAMUX_REQ_I2C1_RX
00452   *         @arg @ref LL_DMAMUX_REQ_I2C1_TX
00453   *         @arg @ref LL_DMAMUX_REQ_I2C3_RX
00454   *         @arg @ref LL_DMAMUX_REQ_I2C3_TX
00455   *         @arg @ref LL_DMAMUX_REQ_USART1_RX
00456   *         @arg @ref LL_DMAMUX_REQ_USART1_TX
00457   *         @arg @ref LL_DMAMUX_REQ_LPUART1_RX
00458   *         @arg @ref LL_DMAMUX_REQ_LPUART1_TX
00459   *         @arg @ref LL_DMAMUX_REQ_SAI1_A
00460   *         @arg @ref LL_DMAMUX_REQ_SAI1_B
00461   *         @arg @ref LL_DMAMUX_REQ_QUADSPI
00462   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH1
00463   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH2
00464   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH3
00465   *         @arg @ref LL_DMAMUX_REQ_TIM1_CH4
00466   *         @arg @ref LL_DMAMUX_REQ_TIM1_UP
00467   *         @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
00468   *         @arg @ref LL_DMAMUX_REQ_TIM1_COM
00469   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH1
00470   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH2
00471   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH3
00472   *         @arg @ref LL_DMAMUX_REQ_TIM2_CH4
00473   *         @arg @ref LL_DMAMUX_REQ_TIM2_UP
00474   *         @arg @ref LL_DMAMUX_REQ_TIM16_CH1
00475   *         @arg @ref LL_DMAMUX_REQ_TIM16_UP
00476   *         @arg @ref LL_DMAMUX_REQ_TIM17_CH1
00477   *         @arg @ref LL_DMAMUX_REQ_TIM17_UP
00478   *         @arg @ref LL_DMAMUX_REQ_AES1_IN
00479   *         @arg @ref LL_DMAMUX_REQ_AES1_OUT
00480   *         @arg @ref LL_DMAMUX_REQ_AES2_IN
00481   *         @arg @ref LL_DMAMUX_REQ_AES2_OUT
00482   */
00483 __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
00484 {
00485   (void)(DMAMUXx);
00486   return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID));
00487 }
00488
00489 /**
00490   * @brief  Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
00491   * @rmtoll CxCR         NBREQ         LL_DMAMUX_SetSyncRequestNb
00492   * @param  DMAMUXx DMAMUXx Instance
00493   * @param  Channel This parameter can be one of the following values:
00494   *         @arg @ref LL_DMAMUX_CHANNEL_0
00495   *         @arg @ref LL_DMAMUX_CHANNEL_1
00496   *         @arg @ref LL_DMAMUX_CHANNEL_2
00497   *         @arg @ref LL_DMAMUX_CHANNEL_3
00498   *         @arg @ref LL_DMAMUX_CHANNEL_4
00499   *         @arg @ref LL_DMAMUX_CHANNEL_5
00500   *         @arg @ref LL_DMAMUX_CHANNEL_6
00501   *         @arg @ref LL_DMAMUX_CHANNEL_7
00502   *         @arg @ref LL_DMAMUX_CHANNEL_8
00503   *         @arg @ref LL_DMAMUX_CHANNEL_9
00504   *         @arg @ref LL_DMAMUX_CHANNEL_10
00505   *         @arg @ref LL_DMAMUX_CHANNEL_11
00506   *         @arg @ref LL_DMAMUX_CHANNEL_12
00507   *         @arg @ref LL_DMAMUX_CHANNEL_13
00508   * @param  RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
00509   * @retval None
00510   */
00511 __STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb)
00512 {
00513   (void)(DMAMUXx);
00514   MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ, ((RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos));
00515 }
00516
00517 /**
00518   * @brief  Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
00519   * @rmtoll CxCR         NBREQ         LL_DMAMUX_GetSyncRequestNb
00520   * @param  DMAMUXx DMAMUXx Instance
00521   * @param  Channel This parameter can be one of the following values:
00522   *         @arg @ref LL_DMAMUX_CHANNEL_0
00523   *         @arg @ref LL_DMAMUX_CHANNEL_1
00524   *         @arg @ref LL_DMAMUX_CHANNEL_2
00525   *         @arg @ref LL_DMAMUX_CHANNEL_3
00526   *         @arg @ref LL_DMAMUX_CHANNEL_4
00527   *         @arg @ref LL_DMAMUX_CHANNEL_5
00528   *         @arg @ref LL_DMAMUX_CHANNEL_6
00529   *         @arg @ref LL_DMAMUX_CHANNEL_7
00530   *         @arg @ref LL_DMAMUX_CHANNEL_8
00531   *         @arg @ref LL_DMAMUX_CHANNEL_9
00532   *         @arg @ref LL_DMAMUX_CHANNEL_10
00533   *         @arg @ref LL_DMAMUX_CHANNEL_11
00534   *         @arg @ref LL_DMAMUX_CHANNEL_12
00535   *         @arg @ref LL_DMAMUX_CHANNEL_13
00536   * @retval Between Min_Data = 1 and Max_Data = 32
00537   */
00538 __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
00539 {
00540   (void)(DMAMUXx);
00541   return (uint32_t)(((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ)) >> DMAMUX_CxCR_NBREQ_Pos) + 1U);
00542 }
00543
00544 /**
00545   * @brief  Set the polarity of the signal on which the DMA request is synchronized.
00546   * @rmtoll CxCR         SPOL          LL_DMAMUX_SetSyncPolarity
00547   * @param  DMAMUXx DMAMUXx Instance
00548   * @param  Channel This parameter can be one of the following values:
00549   *         @arg @ref LL_DMAMUX_CHANNEL_0
00550   *         @arg @ref LL_DMAMUX_CHANNEL_1
00551   *         @arg @ref LL_DMAMUX_CHANNEL_2
00552   *         @arg @ref LL_DMAMUX_CHANNEL_3
00553   *         @arg @ref LL_DMAMUX_CHANNEL_4
00554   *         @arg @ref LL_DMAMUX_CHANNEL_5
00555   *         @arg @ref LL_DMAMUX_CHANNEL_6
00556   *         @arg @ref LL_DMAMUX_CHANNEL_7
00557   *         @arg @ref LL_DMAMUX_CHANNEL_8
00558   *         @arg @ref LL_DMAMUX_CHANNEL_9
00559   *         @arg @ref LL_DMAMUX_CHANNEL_10
00560   *         @arg @ref LL_DMAMUX_CHANNEL_11
00561   *         @arg @ref LL_DMAMUX_CHANNEL_12
00562   *         @arg @ref LL_DMAMUX_CHANNEL_13
00563   * @param  Polarity This parameter can be one of the following values:
00564   *         @arg @ref LL_DMAMUX_SYNC_NO_EVENT
00565   *         @arg @ref LL_DMAMUX_SYNC_POL_RISING
00566   *         @arg @ref LL_DMAMUX_SYNC_POL_FALLING
00567   *         @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
00568   * @retval None
00569   */
00570 __STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity)
00571 {
00572   (void)(DMAMUXx);
00573   MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL, Polarity);
00574 }
00575
00576 /**
00577   * @brief  Get the polarity of the signal on which the DMA request is synchronized.
00578   * @rmtoll CxCR         SPOL          LL_DMAMUX_GetSyncPolarity
00579   * @param  DMAMUXx DMAMUXx Instance
00580   * @param  Channel This parameter can be one of the following values:
00581   *         @arg @ref LL_DMAMUX_CHANNEL_0
00582   *         @arg @ref LL_DMAMUX_CHANNEL_1
00583   *         @arg @ref LL_DMAMUX_CHANNEL_2
00584   *         @arg @ref LL_DMAMUX_CHANNEL_3
00585   *         @arg @ref LL_DMAMUX_CHANNEL_4
00586   *         @arg @ref LL_DMAMUX_CHANNEL_5
00587   *         @arg @ref LL_DMAMUX_CHANNEL_6
00588 #if defined(DMA2)
00589   *         @arg @ref LL_DMAMUX_CHANNEL_7
00590   *         @arg @ref LL_DMAMUX_CHANNEL_8
00591   *         @arg @ref LL_DMAMUX_CHANNEL_9
00592   *         @arg @ref LL_DMAMUX_CHANNEL_10
00593   *         @arg @ref LL_DMAMUX_CHANNEL_11
00594   *         @arg @ref LL_DMAMUX_CHANNEL_12
00595   *         @arg @ref LL_DMAMUX_CHANNEL_13
00596 #endif
00597   * @retval Returned value can be one of the following values:
00598   *         @arg @ref LL_DMAMUX_SYNC_NO_EVENT
00599   *         @arg @ref LL_DMAMUX_SYNC_POL_RISING
00600   *         @arg @ref LL_DMAMUX_SYNC_POL_FALLING
00601   *         @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
00602   */
00603 __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
00604 {
00605   (void)(DMAMUXx);
00606   return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL));
00607 }
00608
00609 /**
00610   * @brief  Enable the Event Generation on DMAMUX channel x.
00611   * @rmtoll CxCR         EGE           LL_DMAMUX_EnableEventGeneration
00612   * @param  DMAMUXx DMAMUXx Instance
00613   * @param  Channel This parameter can be one of the following values:
00614   *         @arg @ref LL_DMAMUX_CHANNEL_0
00615   *         @arg @ref LL_DMAMUX_CHANNEL_1
00616   *         @arg @ref LL_DMAMUX_CHANNEL_2
00617   *         @arg @ref LL_DMAMUX_CHANNEL_3
00618   *         @arg @ref LL_DMAMUX_CHANNEL_4
00619   *         @arg @ref LL_DMAMUX_CHANNEL_5
00620   *         @arg @ref LL_DMAMUX_CHANNEL_6
00621 #if defined(DMA2)
00622   *         @arg @ref LL_DMAMUX_CHANNEL_7
00623   *         @arg @ref LL_DMAMUX_CHANNEL_8
00624   *         @arg @ref LL_DMAMUX_CHANNEL_9
00625   *         @arg @ref LL_DMAMUX_CHANNEL_10
00626   *         @arg @ref LL_DMAMUX_CHANNEL_11
00627   *         @arg @ref LL_DMAMUX_CHANNEL_12
00628   *         @arg @ref LL_DMAMUX_CHANNEL_13
00629 #endif
00630   * @retval None
00631   */
00632 __STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
00633 {
00634   (void)(DMAMUXx);
00635   SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE);
00636 }
00637
00638 /**
00639   * @brief  Disable the Event Generation on DMAMUX channel x.
00640   * @rmtoll CxCR         EGE           LL_DMAMUX_DisableEventGeneration
00641   * @param  DMAMUXx DMAMUXx Instance
00642   * @param  Channel This parameter can be one of the following values:
00643   *         @arg @ref LL_DMAMUX_CHANNEL_0
00644   *         @arg @ref LL_DMAMUX_CHANNEL_1
00645   *         @arg @ref LL_DMAMUX_CHANNEL_2
00646   *         @arg @ref LL_DMAMUX_CHANNEL_3
00647   *         @arg @ref LL_DMAMUX_CHANNEL_4
00648   *         @arg @ref LL_DMAMUX_CHANNEL_5
00649   *         @arg @ref LL_DMAMUX_CHANNEL_6
00650 #if defined(DMA2)
00651   *         @arg @ref LL_DMAMUX_CHANNEL_7
00652   *         @arg @ref LL_DMAMUX_CHANNEL_8
00653   *         @arg @ref LL_DMAMUX_CHANNEL_9
00654   *         @arg @ref LL_DMAMUX_CHANNEL_10
00655   *         @arg @ref LL_DMAMUX_CHANNEL_11
00656   *         @arg @ref LL_DMAMUX_CHANNEL_12
00657   *         @arg @ref LL_DMAMUX_CHANNEL_13
00658 #endif
00659   * @retval None
00660   */
00661 __STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
00662 {
00663   (void)(DMAMUXx);
00664   CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE);
00665 }
00666
00667 /**
00668   * @brief  Check if the Event Generation on DMAMUX channel x is enabled or disabled.
00669   * @rmtoll CxCR         EGE           LL_DMAMUX_IsEnabledEventGeneration
00670   * @param  DMAMUXx DMAMUXx Instance
00671   * @param  Channel This parameter can be one of the following values:
00672   *         @arg @ref LL_DMAMUX_CHANNEL_0
00673   *         @arg @ref LL_DMAMUX_CHANNEL_1
00674   *         @arg @ref LL_DMAMUX_CHANNEL_2
00675   *         @arg @ref LL_DMAMUX_CHANNEL_3
00676   *         @arg @ref LL_DMAMUX_CHANNEL_4
00677   *         @arg @ref LL_DMAMUX_CHANNEL_5
00678   *         @arg @ref LL_DMAMUX_CHANNEL_6
00679 #if defined(DMA2)
00680   *         @arg @ref LL_DMAMUX_CHANNEL_7
00681   *         @arg @ref LL_DMAMUX_CHANNEL_8
00682   *         @arg @ref LL_DMAMUX_CHANNEL_9
00683   *         @arg @ref LL_DMAMUX_CHANNEL_10
00684   *         @arg @ref LL_DMAMUX_CHANNEL_11
00685   *         @arg @ref LL_DMAMUX_CHANNEL_12
00686   *         @arg @ref LL_DMAMUX_CHANNEL_13
00687 #endif
00688   * @retval State of bit (1 or 0).
00689   */
00690 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
00691 {
00692   (void)(DMAMUXx);
00693   return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE))? 1UL : 0UL);
00694 }
00695
00696 /**
00697   * @brief  Enable the synchronization mode.
00698   * @rmtoll CxCR         SE            LL_DMAMUX_EnableSync
00699   * @param  DMAMUXx DMAMUXx Instance
00700   * @param  Channel This parameter can be one of the following values:
00701   *         @arg @ref LL_DMAMUX_CHANNEL_0
00702   *         @arg @ref LL_DMAMUX_CHANNEL_1
00703   *         @arg @ref LL_DMAMUX_CHANNEL_2
00704   *         @arg @ref LL_DMAMUX_CHANNEL_3
00705   *         @arg @ref LL_DMAMUX_CHANNEL_4
00706   *         @arg @ref LL_DMAMUX_CHANNEL_5
00707   *         @arg @ref LL_DMAMUX_CHANNEL_6
00708 #if defined(DMA2)
00709   *         @arg @ref LL_DMAMUX_CHANNEL_7
00710   *         @arg @ref LL_DMAMUX_CHANNEL_8
00711   *         @arg @ref LL_DMAMUX_CHANNEL_9
00712   *         @arg @ref LL_DMAMUX_CHANNEL_10
00713   *         @arg @ref LL_DMAMUX_CHANNEL_11
00714   *         @arg @ref LL_DMAMUX_CHANNEL_12
00715   *         @arg @ref LL_DMAMUX_CHANNEL_13
00716 #endif
00717   * @retval None
00718   */
00719 __STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
00720 {
00721   (void)(DMAMUXx);
00722   SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE);
00723 }
00724
00725 /**
00726   * @brief  Disable the synchronization mode.
00727   * @rmtoll CxCR         SE            LL_DMAMUX_DisableSync
00728   * @param  DMAMUXx DMAMUXx Instance
00729   * @param  Channel This parameter can be one of the following values:
00730   *         @arg @ref LL_DMAMUX_CHANNEL_0
00731   *         @arg @ref LL_DMAMUX_CHANNEL_1
00732   *         @arg @ref LL_DMAMUX_CHANNEL_2
00733   *         @arg @ref LL_DMAMUX_CHANNEL_3
00734   *         @arg @ref LL_DMAMUX_CHANNEL_4
00735   *         @arg @ref LL_DMAMUX_CHANNEL_5
00736   *         @arg @ref LL_DMAMUX_CHANNEL_6
00737 #if defined(DMA2)
00738   *         @arg @ref LL_DMAMUX_CHANNEL_7
00739   *         @arg @ref LL_DMAMUX_CHANNEL_8
00740   *         @arg @ref LL_DMAMUX_CHANNEL_9
00741   *         @arg @ref LL_DMAMUX_CHANNEL_10
00742   *         @arg @ref LL_DMAMUX_CHANNEL_11
00743   *         @arg @ref LL_DMAMUX_CHANNEL_12
00744   *         @arg @ref LL_DMAMUX_CHANNEL_13
00745 #endif
00746   * @retval None
00747   */
00748 __STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
00749 {
00750   (void)(DMAMUXx);
00751   CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE);
00752 }
00753
00754 /**
00755   * @brief  Check if the synchronization mode is enabled or disabled.
00756   * @rmtoll CxCR         SE            LL_DMAMUX_IsEnabledSync
00757   * @param  DMAMUXx DMAMUXx Instance
00758   * @param  Channel This parameter can be one of the following values:
00759   *         @arg @ref LL_DMAMUX_CHANNEL_0
00760   *         @arg @ref LL_DMAMUX_CHANNEL_1
00761   *         @arg @ref LL_DMAMUX_CHANNEL_2
00762   *         @arg @ref LL_DMAMUX_CHANNEL_3
00763   *         @arg @ref LL_DMAMUX_CHANNEL_4
00764   *         @arg @ref LL_DMAMUX_CHANNEL_5
00765   *         @arg @ref LL_DMAMUX_CHANNEL_6
00766 #if defined(DMA2)
00767   *         @arg @ref LL_DMAMUX_CHANNEL_7
00768   *         @arg @ref LL_DMAMUX_CHANNEL_8
00769   *         @arg @ref LL_DMAMUX_CHANNEL_9
00770   *         @arg @ref LL_DMAMUX_CHANNEL_10
00771   *         @arg @ref LL_DMAMUX_CHANNEL_11
00772   *         @arg @ref LL_DMAMUX_CHANNEL_12
00773   *         @arg @ref LL_DMAMUX_CHANNEL_13
00774 #endif
00775   * @retval State of bit (1 or 0).
00776   */
00777 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
00778 {
00779   (void)(DMAMUXx);
00780   return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE))? 1UL : 0UL);
00781 }
00782
00783 /**
00784   * @brief  Set DMAMUX synchronization ID  on DMAMUX Channel x.
00785   * @rmtoll CxCR         SYNC_ID       LL_DMAMUX_SetSyncID
00786   * @param  DMAMUXx DMAMUXx Instance
00787   * @param  Channel This parameter can be one of the following values:
00788   *         @arg @ref LL_DMAMUX_CHANNEL_0
00789   *         @arg @ref LL_DMAMUX_CHANNEL_1
00790   *         @arg @ref LL_DMAMUX_CHANNEL_2
00791   *         @arg @ref LL_DMAMUX_CHANNEL_3
00792   *         @arg @ref LL_DMAMUX_CHANNEL_4
00793   *         @arg @ref LL_DMAMUX_CHANNEL_5
00794   *         @arg @ref LL_DMAMUX_CHANNEL_6
00795 #if defined(DMA2)
00796   *         @arg @ref LL_DMAMUX_CHANNEL_7
00797   *         @arg @ref LL_DMAMUX_CHANNEL_8
00798   *         @arg @ref LL_DMAMUX_CHANNEL_9
00799   *         @arg @ref LL_DMAMUX_CHANNEL_10
00800   *         @arg @ref LL_DMAMUX_CHANNEL_11
00801   *         @arg @ref LL_DMAMUX_CHANNEL_12
00802   *         @arg @ref LL_DMAMUX_CHANNEL_13
00803 #endif
00804   * @param  SyncID This parameter can be one of the following values:
00805   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0
00806   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1
00807   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2
00808   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3
00809   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4
00810   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5
00811   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6
00812   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7
00813   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8
00814   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9
00815   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10
00816   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11
00817   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12
00818   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13
00819   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14
00820   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15
00821   *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0
00822   *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1
00823   *         @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT
00824   *         @arg @ref LL_DMAMUX_SYNC_LPTIM2_OUT
00825   * @retval None
00826   */
00827 __STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID)
00828 {
00829   (void)(DMAMUXx);
00830   MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID, SyncID);
00831 }
00832
00833 /**
00834   * @brief  Get DMAMUX synchronization ID  on DMAMUX Channel x.
00835   * @rmtoll CxCR         SYNC_ID       LL_DMAMUX_GetSyncID
00836   * @param  DMAMUXx DMAMUXx Instance
00837   * @param  Channel This parameter can be one of the following values:
00838   *         @arg @ref LL_DMAMUX_CHANNEL_0
00839   *         @arg @ref LL_DMAMUX_CHANNEL_1
00840   *         @arg @ref LL_DMAMUX_CHANNEL_2
00841   *         @arg @ref LL_DMAMUX_CHANNEL_3
00842   *         @arg @ref LL_DMAMUX_CHANNEL_4
00843   *         @arg @ref LL_DMAMUX_CHANNEL_5
00844   *         @arg @ref LL_DMAMUX_CHANNEL_6
00845 #if defined(DMA2)
00846   *         @arg @ref LL_DMAMUX_CHANNEL_7
00847   *         @arg @ref LL_DMAMUX_CHANNEL_8
00848   *         @arg @ref LL_DMAMUX_CHANNEL_9
00849   *         @arg @ref LL_DMAMUX_CHANNEL_10
00850   *         @arg @ref LL_DMAMUX_CHANNEL_11
00851   *         @arg @ref LL_DMAMUX_CHANNEL_12
00852   *         @arg @ref LL_DMAMUX_CHANNEL_13
00853 #endif
00854   * @retval Returned value can be one of the following values:
00855   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0
00856   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1
00857   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2
00858   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3
00859   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4
00860   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5
00861   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6
00862   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7
00863   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8
00864   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9
00865   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10
00866   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11
00867   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12
00868   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13
00869   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14
00870   *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15
00871   *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0
00872   *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1
00873   *         @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT
00874   *         @arg @ref LL_DMAMUX_SYNC_LPTIM2_OUT
00875   */
00876 __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
00877 {
00878   (void)(DMAMUXx);
00879   return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID));
00880 }
00881
00882 /**
00883   * @brief  Enable the Request Generator.
00884   * @rmtoll RGxCR        GE            LL_DMAMUX_EnableRequestGen
00885   * @param  DMAMUXx DMAMUXx Instance
00886   * @param  RequestGenChannel This parameter can be one of the following values:
00887   *         @arg @ref LL_DMAMUX_REQ_GEN_0
00888   *         @arg @ref LL_DMAMUX_REQ_GEN_1
00889   *         @arg @ref LL_DMAMUX_REQ_GEN_2
00890   *         @arg @ref LL_DMAMUX_REQ_GEN_3
00891   * @retval None
00892   */
00893 __STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
00894 {
00895   (void)(DMAMUXx);
00896   SET_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE);
00897 }
00898
00899 /**
00900   * @brief  Disable the Request Generator.
00901   * @rmtoll RGxCR        GE            LL_DMAMUX_DisableRequestGen
00902   * @param  DMAMUXx DMAMUXx Instance
00903   * @param  RequestGenChannel This parameter can be one of the following values:
00904   *         @arg @ref LL_DMAMUX_REQ_GEN_0
00905   *         @arg @ref LL_DMAMUX_REQ_GEN_1
00906   *         @arg @ref LL_DMAMUX_REQ_GEN_2
00907   *         @arg @ref LL_DMAMUX_REQ_GEN_3
00908   * @retval None
00909   */
00910 __STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
00911 {
00912   (void)(DMAMUXx);
00913   CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE);
00914 }
00915
00916 /**
00917   * @brief  Check if the Request Generator is enabled or disabled.
00918   * @rmtoll RGxCR        GE            LL_DMAMUX_IsEnabledRequestGen
00919   * @param  DMAMUXx DMAMUXx Instance
00920   * @param  RequestGenChannel This parameter can be one of the following values:
00921   *         @arg @ref LL_DMAMUX_REQ_GEN_0
00922   *         @arg @ref LL_DMAMUX_REQ_GEN_1
00923   *         @arg @ref LL_DMAMUX_REQ_GEN_2
00924   *         @arg @ref LL_DMAMUX_REQ_GEN_3
00925   * @retval State of bit (1 or 0).
00926   */
00927 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
00928 {
00929   (void)(DMAMUXx);
00930   return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE))? 1UL : 0UL);
00931 }
00932
00933 /**
00934   * @brief  Set the polarity of the signal on which the DMA request is generated.
00935   * @rmtoll RGxCR        GPOL          LL_DMAMUX_SetRequestGenPolarity
00936   * @param  DMAMUXx DMAMUXx Instance
00937   * @param  RequestGenChannel This parameter can be one of the following values:
00938   *         @arg @ref LL_DMAMUX_REQ_GEN_0
00939   *         @arg @ref LL_DMAMUX_REQ_GEN_1
00940   *         @arg @ref LL_DMAMUX_REQ_GEN_2
00941   *         @arg @ref LL_DMAMUX_REQ_GEN_3
00942   * @param  Polarity This parameter can be one of the following values:
00943   *         @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
00944   *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
00945   *         @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
00946   *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
00947   * @retval None
00948   */
00949 __STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity)
00950 {
00951   (void)(DMAMUXx);
00952   MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL, Polarity);
00953 }
00954
00955 /**
00956   * @brief  Get the polarity of the signal on which the DMA request is generated.
00957   * @rmtoll RGxCR        GPOL          LL_DMAMUX_GetRequestGenPolarity
00958   * @param  DMAMUXx DMAMUXx Instance
00959   * @param  RequestGenChannel This parameter can be one of the following values:
00960   *         @arg @ref LL_DMAMUX_REQ_GEN_0
00961   *         @arg @ref LL_DMAMUX_REQ_GEN_1
00962   *         @arg @ref LL_DMAMUX_REQ_GEN_2
00963   *         @arg @ref LL_DMAMUX_REQ_GEN_3
00964   * @retval Returned value can be one of the following values:
00965   *         @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
00966   *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
00967   *         @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
00968   *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
00969   */
00970 __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
00971 {
00972   (void)(DMAMUXx);
00973   return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL));
00974 }
00975
00976 /**
00977   * @brief  Set the number of DMA request that will be autorized after a generation event.
00978   * @note   This field can only be written when Generator is disabled.
00979   * @rmtoll RGxCR        GNBREQ        LL_DMAMUX_SetGenRequestNb
00980   * @param  DMAMUXx DMAMUXx Instance
00981   * @param  RequestGenChannel This parameter can be one of the following values:
00982   *         @arg @ref LL_DMAMUX_REQ_GEN_0
00983   *         @arg @ref LL_DMAMUX_REQ_GEN_1
00984   *         @arg @ref LL_DMAMUX_REQ_GEN_2
00985   *         @arg @ref LL_DMAMUX_REQ_GEN_3
00986   * @param  RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
00987   * @retval None
00988   */
00989 __STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb)
00990 {
00991   (void)(DMAMUXx);
00992   MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos);
00993 }
00994
00995 /**
00996   * @brief  Get the number of DMA request that will be autorized after a generation event.
00997   * @rmtoll RGxCR        GNBREQ        LL_DMAMUX_GetGenRequestNb
00998   * @param  DMAMUXx DMAMUXx Instance
00999   * @param  RequestGenChannel This parameter can be one of the following values:
01000   *         @arg @ref LL_DMAMUX_REQ_GEN_0
01001   *         @arg @ref LL_DMAMUX_REQ_GEN_1
01002   *         @arg @ref LL_DMAMUX_REQ_GEN_2
01003   *         @arg @ref LL_DMAMUX_REQ_GEN_3
01004   * @retval Between Min_Data = 1 and Max_Data = 32
01005   */
01006 __STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
01007 {
01008   (void)(DMAMUXx);
01009   return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U);
01010 }
01011
01012 /**
01013   * @brief  Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x.
01014   * @rmtoll RGxCR        SIG_ID        LL_DMAMUX_SetRequestSignalID
01015   * @param  DMAMUXx DMAMUXx Instance
01016   * @param  RequestGenChannel This parameter can be one of the following values:
01017   *         @arg @ref LL_DMAMUX_REQ_GEN_0
01018   *         @arg @ref LL_DMAMUX_REQ_GEN_1
01019   *         @arg @ref LL_DMAMUX_REQ_GEN_2
01020   *         @arg @ref LL_DMAMUX_REQ_GEN_3
01021   * @param  RequestSignalID This parameter can be one of the following values:
01022   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0
01023   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1
01024   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2
01025   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3
01026   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4
01027   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5
01028   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6
01029   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7
01030   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8
01031   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9
01032   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10
01033   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11
01034   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12
01035   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13
01036   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14
01037   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15
01038   *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0
01039   *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1
01040   *         @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT
01041   *         @arg @ref LL_DMAMUX_REQ_GEN_LPTIM2_OUT
01042   * @retval None
01043   */
01044 __STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID)
01045 {
01046   (void)(DMAMUXx);
01047   MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID);
01048 }
01049
01050 /**
01051   * @brief  Get DMAMUX external Request Signal ID set on DMAMUX Channel x.
01052   * @rmtoll RGxCR        SIG_ID        LL_DMAMUX_GetRequestSignalID
01053   * @param  DMAMUXx DMAMUXx Instance
01054   * @param  RequestGenChannel This parameter can be one of the following values:
01055   *         @arg @ref LL_DMAMUX_REQ_GEN_0
01056   *         @arg @ref LL_DMAMUX_REQ_GEN_1
01057   *         @arg @ref LL_DMAMUX_REQ_GEN_2
01058   *         @arg @ref LL_DMAMUX_REQ_GEN_3
01059   * @retval Returned value can be one of the following values:
01060   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0
01061   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1
01062   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2
01063   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3
01064   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4
01065   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5
01066   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6
01067   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7
01068   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8
01069   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9
01070   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10
01071   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11
01072   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12
01073   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13
01074   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14
01075   *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15
01076   *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0
01077   *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1
01078   *         @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT
01079   *         @arg @ref LL_DMAMUX_REQ_GEN_LPTIM2_OUT
01080   */
01081 __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
01082 {
01083   (void)(DMAMUXx);
01084   return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID));
01085 }
01086
01087 /**
01088   * @}
01089   */
01090
01091 /** @defgroup DMAMUX_LL_EF_FLAG_Management FLAG_Management
01092   * @{
01093   */
01094
01095 /**
01096   * @brief  Get Synchronization Event Overrun Flag Channel 0.
01097   * @rmtoll CSR          SOF0          LL_DMAMUX_IsActiveFlag_SO0
01098   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01099   * @retval State of bit (1 or 0).
01100   */
01101 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
01102 {
01103   (void)(DMAMUXx);
01104   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL);
01105 }
01106
01107 /**
01108   * @brief  Get Synchronization Event Overrun Flag Channel 1.
01109   * @rmtoll CSR          SOF1          LL_DMAMUX_IsActiveFlag_SO1
01110   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01111   * @retval State of bit (1 or 0).
01112   */
01113 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
01114 {
01115   (void)(DMAMUXx);
01116   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL);
01117 }
01118
01119 /**
01120   * @brief  Get Synchronization Event Overrun Flag Channel 2.
01121   * @rmtoll CSR          SOF2          LL_DMAMUX_IsActiveFlag_SO2
01122   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01123   * @retval State of bit (1 or 0).
01124   */
01125 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
01126 {
01127   (void)(DMAMUXx);
01128   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL);
01129 }
01130
01131 /**
01132   * @brief  Get Synchronization Event Overrun Flag Channel 3.
01133   * @rmtoll CSR          SOF3          LL_DMAMUX_IsActiveFlag_SO3
01134   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01135   * @retval State of bit (1 or 0).
01136   */
01137 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
01138 {
01139   (void)(DMAMUXx);
01140   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL);
01141 }
01142
01143 /**
01144   * @brief  Get Synchronization Event Overrun Flag Channel 4.
01145   * @rmtoll CSR          SOF4          LL_DMAMUX_IsActiveFlag_SO4
01146   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01147   * @retval State of bit (1 or 0).
01148   */
01149 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
01150 {
01151   (void)(DMAMUXx);
01152   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL);
01153 }
01154
01155 /**
01156   * @brief  Get Synchronization Event Overrun Flag Channel 5.
01157   * @rmtoll CSR          SOF5          LL_DMAMUX_IsActiveFlag_SO5
01158   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01159   * @retval State of bit (1 or 0).
01160   */
01161 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
01162 {
01163   (void)(DMAMUXx);
01164   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL);
01165 }
01166
01167 /**
01168   * @brief  Get Synchronization Event Overrun Flag Channel 6.
01169   * @rmtoll CSR          SOF6          LL_DMAMUX_IsActiveFlag_SO6
01170   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01171   * @retval State of bit (1 or 0).
01172   */
01173 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
01174 {
01175   (void)(DMAMUXx);
01176   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL);
01177 }
01178
01179 /**
01180   * @brief  Get Synchronization Event Overrun Flag Channel 7.
01181   * @rmtoll CSR          SOF7          LL_DMAMUX_IsActiveFlag_SO7
01182   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01183   * @retval State of bit (1 or 0).
01184   */
01185 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
01186 {
01187   (void)(DMAMUXx);
01188   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL);
01189 }
01190
01191 /**
01192   * @brief  Get Synchronization Event Overrun Flag Channel 8.
01193   * @rmtoll CSR          SOF8          LL_DMAMUX_IsActiveFlag_SO8
01194   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01195   * @retval State of bit (1 or 0).
01196   */
01197 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
01198 {
01199   (void)(DMAMUXx);
01200   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL);
01201 }
01202
01203 /**
01204   * @brief  Get Synchronization Event Overrun Flag Channel 9.
01205   * @rmtoll CSR          SOF9          LL_DMAMUX_IsActiveFlag_SO9
01206   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01207   * @retval State of bit (1 or 0).
01208   */
01209 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
01210 {
01211   (void)(DMAMUXx);
01212   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL);
01213 }
01214
01215 /**
01216   * @brief  Get Synchronization Event Overrun Flag Channel 10.
01217   * @rmtoll CSR          SOF10         LL_DMAMUX_IsActiveFlag_SO10
01218   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01219   * @retval State of bit (1 or 0).
01220   */
01221 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
01222 {
01223   (void)(DMAMUXx);
01224   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL);
01225 }
01226
01227 /**
01228   * @brief  Get Synchronization Event Overrun Flag Channel 11.
01229   * @rmtoll CSR          SOF11         LL_DMAMUX_IsActiveFlag_SO11
01230   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01231   * @retval State of bit (1 or 0).
01232   */
01233 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
01234 {
01235   (void)(DMAMUXx);
01236   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL);
01237 }
01238
01239 /**
01240   * @brief  Get Synchronization Event Overrun Flag Channel 12.
01241   * @rmtoll CSR          SOF12         LL_DMAMUX_IsActiveFlag_SO12
01242   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01243   * @retval State of bit (1 or 0).
01244   */
01245 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)
01246 {
01247   (void)(DMAMUXx);
01248   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF12) == (DMAMUX_CSR_SOF12)) ? 1UL : 0UL);
01249 }
01250
01251 /**
01252   * @brief  Get Synchronization Event Overrun Flag Channel 13.
01253   * @rmtoll CSR          SOF13         LL_DMAMUX_IsActiveFlag_SO13
01254   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01255   * @retval State of bit (1 or 0).
01256   */
01257 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)
01258 {
01259   (void)(DMAMUXx);
01260   return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF13) == (DMAMUX_CSR_SOF13)) ? 1UL : 0UL);
01261 }
01262
01263 /**
01264   * @brief  Get Request Generator 0 Trigger Event Overrun Flag.
01265   * @rmtoll RGSR         OF0           LL_DMAMUX_IsActiveFlag_RGO0
01266   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01267   * @retval State of bit (1 or 0).
01268   */
01269 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
01270 {
01271   (void)(DMAMUXx);
01272   return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL);
01273 }
01274
01275 /**
01276   * @brief  Get Request Generator 1 Trigger Event Overrun Flag.
01277   * @rmtoll RGSR         OF1           LL_DMAMUX_IsActiveFlag_RGO1
01278   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01279   * @retval State of bit (1 or 0).
01280   */
01281 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
01282 {
01283   (void)(DMAMUXx);
01284   return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL);
01285 }
01286
01287 /**
01288   * @brief  Get Request Generator 2 Trigger Event Overrun Flag.
01289   * @rmtoll RGSR         OF2           LL_DMAMUX_IsActiveFlag_RGO2
01290   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01291   * @retval State of bit (1 or 0).
01292   */
01293 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
01294 {
01295   (void)(DMAMUXx);
01296   return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL);
01297 }
01298
01299 /**
01300   * @brief  Get Request Generator 3 Trigger Event Overrun Flag.
01301   * @rmtoll RGSR         OF3           LL_DMAMUX_IsActiveFlag_RGO3
01302   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01303   * @retval State of bit (1 or 0).
01304   */
01305 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
01306 {
01307   (void)(DMAMUXx);
01308   return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL);
01309 }
01310
01311 /**
01312   * @brief  Clear Synchronization Event Overrun Flag Channel 0.
01313   * @rmtoll CFR          CSOF0         LL_DMAMUX_ClearFlag_SO0
01314   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01315   * @retval None
01316   */
01317 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
01318 {
01319   (void)(DMAMUXx);
01320   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF0);
01321 }
01322
01323 /**
01324   * @brief  Clear Synchronization Event Overrun Flag Channel 1.
01325   * @rmtoll CFR          CSOF1         LL_DMAMUX_ClearFlag_SO1
01326   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01327   * @retval None
01328   */
01329 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
01330 {
01331   (void)(DMAMUXx);
01332   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF1);
01333 }
01334
01335 /**
01336   * @brief  Clear Synchronization Event Overrun Flag Channel 2.
01337   * @rmtoll CFR          CSOF2         LL_DMAMUX_ClearFlag_SO2
01338   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01339   * @retval None
01340   */
01341 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
01342 {
01343   (void)(DMAMUXx);
01344   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF2);
01345 }
01346
01347 /**
01348   * @brief  Clear Synchronization Event Overrun Flag Channel 3.
01349   * @rmtoll CFR          CSOF3         LL_DMAMUX_ClearFlag_SO3
01350   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01351   * @retval None
01352   */
01353 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
01354 {
01355   (void)(DMAMUXx);
01356   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF3);
01357 }
01358
01359 /**
01360   * @brief  Clear Synchronization Event Overrun Flag Channel 4.
01361   * @rmtoll CFR          CSOF4         LL_DMAMUX_ClearFlag_SO4
01362   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01363   * @retval None
01364   */
01365 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
01366 {
01367   (void)(DMAMUXx);
01368   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF4);
01369 }
01370
01371 /**
01372   * @brief  Clear Synchronization Event Overrun Flag Channel 5.
01373   * @rmtoll CFR          CSOF5         LL_DMAMUX_ClearFlag_SO5
01374   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01375   * @retval None
01376   */
01377 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
01378 {
01379   (void)(DMAMUXx);
01380   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF5);
01381 }
01382
01383 /**
01384   * @brief  Clear Synchronization Event Overrun Flag Channel 6.
01385   * @rmtoll CFR          CSOF6         LL_DMAMUX_ClearFlag_SO6
01386   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01387   * @retval None
01388   */
01389 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
01390 {
01391   (void)(DMAMUXx);
01392   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF6);
01393 }
01394
01395 /**
01396   * @brief  Clear Synchronization Event Overrun Flag Channel 7.
01397   * @rmtoll CFR          CSOF7         LL_DMAMUX_ClearFlag_SO7
01398   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01399   * @retval None
01400   */
01401 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
01402 {
01403   (void)(DMAMUXx);
01404   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF7);
01405 }
01406
01407 /**
01408   * @brief  Clear Synchronization Event Overrun Flag Channel 8.
01409   * @rmtoll CFR          CSOF8         LL_DMAMUX_ClearFlag_SO8
01410   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01411   * @retval None
01412   */
01413 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
01414 {
01415   (void)(DMAMUXx);
01416   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF8);
01417 }
01418
01419 /**
01420   * @brief  Clear Synchronization Event Overrun Flag Channel 9.
01421   * @rmtoll CFR          CSOF9         LL_DMAMUX_ClearFlag_SO9
01422   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01423   * @retval None
01424   */
01425 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
01426 {
01427   (void)(DMAMUXx);
01428   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF9);
01429 }
01430
01431 /**
01432   * @brief  Clear Synchronization Event Overrun Flag Channel 10.
01433   * @rmtoll CFR          CSOF10        LL_DMAMUX_ClearFlag_SO10
01434   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01435   * @retval None
01436   */
01437 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
01438 {
01439   (void)(DMAMUXx);
01440   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF10);
01441 }
01442
01443 /**
01444   * @brief  Clear Synchronization Event Overrun Flag Channel 11.
01445   * @rmtoll CFR          CSOF11        LL_DMAMUX_ClearFlag_SO11
01446   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01447   * @retval None
01448   */
01449 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
01450 {
01451   (void)(DMAMUXx);
01452   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF11);
01453 }
01454
01455 /**
01456   * @brief  Clear Synchronization Event Overrun Flag Channel 12.
01457   * @rmtoll CFR          CSOF12        LL_DMAMUX_ClearFlag_SO12
01458   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01459   * @retval None
01460   */
01461 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)
01462 {
01463   (void)(DMAMUXx);
01464   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF12);
01465 }
01466
01467 /**
01468   * @brief  Clear Synchronization Event Overrun Flag Channel 13.
01469   * @rmtoll CFR          CSOF13        LL_DMAMUX_ClearFlag_SO13
01470   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01471   * @retval None
01472   */
01473 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)
01474 {
01475   (void)(DMAMUXx);
01476   SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF13);
01477 }
01478
01479 /**
01480   * @brief  Clear Request Generator 0 Trigger Event Overrun Flag.
01481   * @rmtoll RGCFR        COF0          LL_DMAMUX_ClearFlag_RGO0
01482   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01483   * @retval None
01484   */
01485 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
01486 {
01487   (void)(DMAMUXx);
01488   SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF0);
01489 }
01490
01491 /**
01492   * @brief  Clear Request Generator 1 Trigger Event Overrun Flag.
01493   * @rmtoll RGCFR        COF1          LL_DMAMUX_ClearFlag_RGO1
01494   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01495   * @retval None
01496   */
01497 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
01498 {
01499   (void)(DMAMUXx);
01500   SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF1);
01501 }
01502
01503 /**
01504   * @brief  Clear Request Generator 2 Trigger Event Overrun Flag.
01505   * @rmtoll RGCFR        COF2          LL_DMAMUX_ClearFlag_RGO2
01506   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01507   * @retval None
01508   */
01509 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
01510 {
01511   (void)(DMAMUXx);
01512   SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF2);
01513 }
01514
01515 /**
01516   * @brief  Clear Request Generator 3 Trigger Event Overrun Flag.
01517   * @rmtoll RGCFR        COF3          LL_DMAMUX_ClearFlag_RGO3
01518   * @param  DMAMUXx DMAMUXx DMAMUXx Instance
01519   * @retval None
01520   */
01521 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
01522 {
01523   (void)(DMAMUXx);
01524   SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF3);
01525 }
01526
01527 /**
01528   * @}
01529   */
01530
01531 /** @defgroup DMAMUX_LL_EF_IT_Management IT_Management
01532   * @{
01533   */
01534
01535 /**
01536   * @brief  Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
01537   * @rmtoll CxCR         SOIE          LL_DMAMUX_EnableIT_SO
01538   * @param  DMAMUXx DMAMUXx Instance
01539   * @param  Channel This parameter can be one of the following values:
01540   *         @arg @ref LL_DMAMUX_CHANNEL_0
01541   *         @arg @ref LL_DMAMUX_CHANNEL_1
01542   *         @arg @ref LL_DMAMUX_CHANNEL_2
01543   *         @arg @ref LL_DMAMUX_CHANNEL_3
01544   *         @arg @ref LL_DMAMUX_CHANNEL_4
01545   *         @arg @ref LL_DMAMUX_CHANNEL_5
01546   *         @arg @ref LL_DMAMUX_CHANNEL_6
01547 #if defined(DMA2)
01548   *         @arg @ref LL_DMAMUX_CHANNEL_7
01549   *         @arg @ref LL_DMAMUX_CHANNEL_8
01550   *         @arg @ref LL_DMAMUX_CHANNEL_9
01551   *         @arg @ref LL_DMAMUX_CHANNEL_10
01552   *         @arg @ref LL_DMAMUX_CHANNEL_11
01553   *         @arg @ref LL_DMAMUX_CHANNEL_12
01554   *         @arg @ref LL_DMAMUX_CHANNEL_13
01555 #endif
01556   * @retval None
01557   */
01558 __STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
01559 {
01560   (void)(DMAMUXx);
01561   SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE);
01562 }
01563
01564 /**
01565   * @brief  Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
01566   * @rmtoll CxCR         SOIE          LL_DMAMUX_DisableIT_SO
01567   * @param  DMAMUXx DMAMUXx Instance
01568   * @param  Channel This parameter can be one of the following values:
01569   *         @arg @ref LL_DMAMUX_CHANNEL_0
01570   *         @arg @ref LL_DMAMUX_CHANNEL_1
01571   *         @arg @ref LL_DMAMUX_CHANNEL_2
01572   *         @arg @ref LL_DMAMUX_CHANNEL_3
01573   *         @arg @ref LL_DMAMUX_CHANNEL_4
01574   *         @arg @ref LL_DMAMUX_CHANNEL_5
01575   *         @arg @ref LL_DMAMUX_CHANNEL_6
01576 #if defined(DMA2)
01577   *         @arg @ref LL_DMAMUX_CHANNEL_7
01578   *         @arg @ref LL_DMAMUX_CHANNEL_8
01579   *         @arg @ref LL_DMAMUX_CHANNEL_9
01580   *         @arg @ref LL_DMAMUX_CHANNEL_10
01581   *         @arg @ref LL_DMAMUX_CHANNEL_11
01582   *         @arg @ref LL_DMAMUX_CHANNEL_12
01583   *         @arg @ref LL_DMAMUX_CHANNEL_13
01584 #endif
01585   * @retval None
01586   */
01587 __STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
01588 {
01589   (void)(DMAMUXx);
01590   CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE);
01591 }
01592
01593 /**
01594   * @brief  Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
01595   * @rmtoll CxCR         SOIE          LL_DMAMUX_IsEnabledIT_SO
01596   * @param  DMAMUXx DMAMUXx Instance
01597   * @param  Channel This parameter can be one of the following values:
01598   *         @arg @ref LL_DMAMUX_CHANNEL_0
01599   *         @arg @ref LL_DMAMUX_CHANNEL_1
01600   *         @arg @ref LL_DMAMUX_CHANNEL_2
01601   *         @arg @ref LL_DMAMUX_CHANNEL_3
01602   *         @arg @ref LL_DMAMUX_CHANNEL_4
01603   *         @arg @ref LL_DMAMUX_CHANNEL_5
01604   *         @arg @ref LL_DMAMUX_CHANNEL_6
01605 #if defined(DMA2)
01606   *         @arg @ref LL_DMAMUX_CHANNEL_7
01607   *         @arg @ref LL_DMAMUX_CHANNEL_8
01608   *         @arg @ref LL_DMAMUX_CHANNEL_9
01609   *         @arg @ref LL_DMAMUX_CHANNEL_10
01610   *         @arg @ref LL_DMAMUX_CHANNEL_11
01611   *         @arg @ref LL_DMAMUX_CHANNEL_12
01612   *         @arg @ref LL_DMAMUX_CHANNEL_13
01613 #endif
01614   * @retval State of bit (1 or 0).
01615   */
01616 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
01617 {
01618   (void)(DMAMUXx);
01619   return (((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE)) == (DMAMUX_CxCR_SOIE))? 1UL : 0UL);
01620 }
01621
01622 /**
01623   * @brief  Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
01624   * @rmtoll RGxCR        OIE           LL_DMAMUX_EnableIT_RGO
01625   * @param  DMAMUXx DMAMUXx Instance
01626   * @param  RequestGenChannel This parameter can be one of the following values:
01627   *         @arg @ref LL_DMAMUX_REQ_GEN_0
01628   *         @arg @ref LL_DMAMUX_REQ_GEN_1
01629   *         @arg @ref LL_DMAMUX_REQ_GEN_2
01630   *         @arg @ref LL_DMAMUX_REQ_GEN_3
01631   * @retval None
01632   */
01633 __STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
01634 {
01635   (void)(DMAMUXx);
01636   SET_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE);
01637 }
01638
01639 /**
01640   * @brief  Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
01641   * @rmtoll RGxCR        OIE           LL_DMAMUX_DisableIT_RGO
01642   * @param  DMAMUXx DMAMUXx Instance
01643   * @param  RequestGenChannel This parameter can be one of the following values:
01644   *         @arg @ref LL_DMAMUX_REQ_GEN_0
01645   *         @arg @ref LL_DMAMUX_REQ_GEN_1
01646   *         @arg @ref LL_DMAMUX_REQ_GEN_2
01647   *         @arg @ref LL_DMAMUX_REQ_GEN_3
01648   * @retval None
01649   */
01650 __STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
01651 {
01652   (void)(DMAMUXx);
01653   CLEAR_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE);
01654 }
01655
01656 /**
01657   * @brief  Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
01658   * @rmtoll RGxCR        OIE           LL_DMAMUX_IsEnabledIT_RGO
01659   * @param  DMAMUXx DMAMUXx Instance
01660   * @param  RequestGenChannel This parameter can be one of the following values:
01661   *         @arg @ref LL_DMAMUX_REQ_GEN_0
01662   *         @arg @ref LL_DMAMUX_REQ_GEN_1
01663   *         @arg @ref LL_DMAMUX_REQ_GEN_2
01664   *         @arg @ref LL_DMAMUX_REQ_GEN_3
01665   * @retval State of bit (1 or 0).
01666   */
01667 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
01668 {
01669   (void)(DMAMUXx);
01670   return ((READ_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE))? 1UL : 0UL);
01671 }
01672
01673 /**
01674   * @}
01675   */
01676
01677 /**
01678   * @}
01679   */
01680
01681 /**
01682   * @}
01683   */
01684
01685 #endif /* DMAMUX1 */
01686
01687 /**
01688   * @}
01689   */
01690
01691 #ifdef __cplusplus
01692 }
01693 #endif
01694
01695 #endif /* STM32WBxx_LL_DMAMUX_H */
01696
01697 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_exti.c Source File

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stm32wbxx_ll_exti.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_exti.c
00004   * @author  MCD Application Team
00005   * @brief   EXTI LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32wbxx_ll_exti.h"
00023 #ifdef  USE_FULL_ASSERT
00024 #include "stm32_assert.h"
00025 #else
00026 #define assert_param(expr) ((void)0U)
00027 #endif
00028
00029 /** @addtogroup STM32WBxx_LL_Driver
00030   * @{
00031   */
00032
00033 #if defined (EXTI)
00034
00035 /** @defgroup EXTI_LL EXTI
00036   * @{
00037   */
00038
00039 /* Private types -------------------------------------------------------------*/
00040 /* Private variables ---------------------------------------------------------*/
00041 /* Private constants ---------------------------------------------------------*/
00042 /* Private macros ------------------------------------------------------------*/
00043 /** @addtogroup EXTI_LL_Private_Macros
00044   * @{
00045   */
00046
00047 #define IS_LL_EXTI_LINE_0_31(__VALUE__)              (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
00048 #define IS_LL_EXTI_LINE_32_63(__VALUE__)             (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U)
00049
00050 #define IS_LL_EXTI_MODE(__VALUE__)                   (((__VALUE__) == LL_EXTI_MODE_IT)            \
00051                                                    || ((__VALUE__) == LL_EXTI_MODE_EVENT)         \
00052                                                    || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
00053
00054
00055 #define IS_LL_EXTI_TRIGGER(__VALUE__)                (((__VALUE__) == LL_EXTI_TRIGGER_NONE)       \
00056                                                    || ((__VALUE__) == LL_EXTI_TRIGGER_RISING)     \
00057                                                    || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING)    \
00058                                                    || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
00059
00060 /**
00061   * @}
00062   */
00063
00064 /* Private function prototypes -----------------------------------------------*/
00065
00066 /* Exported functions --------------------------------------------------------*/
00067 /** @addtogroup EXTI_LL_Exported_Functions
00068   * @{
00069   */
00070
00071 /** @addtogroup EXTI_LL_EF_Init
00072   * @{
00073   */
00074
00075 /**
00076   * @brief  De-initialize the EXTI registers to their default reset values.
00077   * @retval An ErrorStatus enumeration value:
00078   *          - SUCCESS: EXTI registers are de-initialized
00079   *          - ERROR: not applicable
00080   */
00081 ErrorStatus LL_EXTI_DeInit(void)
00082 {
00083   /* Rising Trigger selection register set to default reset values */
00084   LL_EXTI_WriteReg(RTSR1,  0x00000000U);
00085
00086   /* Falling Trigger selection register set to default reset values */
00087   LL_EXTI_WriteReg(FTSR1,  0x00000000U);
00088
00089   /* Software interrupt event register set to default reset values */
00090   LL_EXTI_WriteReg(SWIER1, 0x00000000U);
00091
00092   /* Pending register set to default reset values */
00093   LL_EXTI_WriteReg(PR1, 0xFFFFFFFFu);
00094
00095   /* Rising Trigger selection register 2 set to default reset values */
00096   LL_EXTI_WriteReg(RTSR2, 0x00000000U);
00097
00098   /* Falling Trigger selection register 2 set to default reset values */
00099   LL_EXTI_WriteReg(FTSR2, 0x00000000U);
00100
00101   /* Software interrupt event register 2 set to default reset values */
00102   LL_EXTI_WriteReg(SWIER2, 0x00000000U);
00103
00104   /* Pending register 2 set to default reset values */
00105   LL_EXTI_WriteReg(PR2, 0xFFFFFFFFu);
00106
00107   /* Interrupt mask register set to default reset values */
00108   LL_EXTI_WriteReg(IMR1, 0x00000000U);
00109   LL_EXTI_WriteReg(C2IMR1, 0x00000000U);
00110
00111   /* Event mask register set to default reset values */
00112   LL_EXTI_WriteReg(EMR1, 0x00000000U);
00113   LL_EXTI_WriteReg(C2EMR1, 0x00000000U);
00114
00115   /* Interrupt mask register 2 set to default reset values */
00116   LL_EXTI_WriteReg(IMR2, 0x00000000U);
00117   LL_EXTI_WriteReg(C2IMR2, 0x00000000U);
00118
00119   /* Event mask register 2 set to default reset values */
00120   LL_EXTI_WriteReg(EMR2, 0x00000000U);
00121   LL_EXTI_WriteReg(C2EMR2, 0x00000000U);
00122
00123   return SUCCESS;
00124 }
00125
00126 /**
00127   * @brief  Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
00128   * @param  EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
00129   * @retval An ErrorStatus enumeration value:
00130   *          - SUCCESS: EXTI registers are initialized
00131   *          - ERROR: not applicable
00132   */
00133 ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
00134 {
00135   ErrorStatus status = SUCCESS;
00136   /* Check the parameters */
00137   assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
00138   assert_param(IS_LL_EXTI_LINE_32_63(EXTI_InitStruct->Line_32_63));
00139   assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
00140   assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
00141
00142   /* ENABLE LineCommand */
00143   if (EXTI_InitStruct->LineCommand != DISABLE)
00144   {
00145     assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
00146
00147     /* Configure EXTI Lines in range from 0 to 31 */
00148     if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
00149     {
00150       switch (EXTI_InitStruct->Mode)
00151       {
00152         case LL_EXTI_MODE_IT:
00153           /* First Disable Event on provided Lines */
00154           LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
00155           /* Then Enable IT on provided Lines */
00156           LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
00157           break;
00158         case LL_EXTI_MODE_EVENT:
00159           /* First Disable IT on provided Lines */
00160           LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
00161           /* Then Enable Event on provided Lines */
00162           LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
00163           break;
00164         case LL_EXTI_MODE_IT_EVENT:
00165           /* Directly Enable IT & Event on provided Lines */
00166           LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
00167           LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
00168           break;
00169         default:
00170           status = ERROR;
00171           break;
00172       }
00173       if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
00174       {
00175         switch (EXTI_InitStruct->Trigger)
00176         {
00177           case LL_EXTI_TRIGGER_RISING:
00178             /* First Disable Falling Trigger on provided Lines */
00179             LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
00180             /* Then Enable Rising Trigger on provided Lines */
00181             LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
00182             break;
00183           case LL_EXTI_TRIGGER_FALLING:
00184             /* First Disable Rising Trigger on provided Lines */
00185             LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
00186             /* Then Enable Falling Trigger on provided Lines */
00187             LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
00188             break;
00189           case LL_EXTI_TRIGGER_RISING_FALLING:
00190             LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
00191             LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
00192             break;
00193           default:
00194             status = ERROR;
00195             break;
00196         }
00197       }
00198     }
00199     /* Configure EXTI Lines in range from 32 to 63 */
00200     if (EXTI_InitStruct->Line_32_63 != LL_EXTI_LINE_NONE)
00201     {
00202       switch (EXTI_InitStruct->Mode)
00203       {
00204         case LL_EXTI_MODE_IT:
00205           /* First Disable Event on provided Lines */
00206           LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
00207           /* Then Enable IT on provided Lines */
00208           LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63);
00209           break;
00210         case LL_EXTI_MODE_EVENT:
00211           /* First Disable IT on provided Lines */
00212           LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
00213           /* Then Enable Event on provided Lines */
00214           LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
00215           break;
00216         case LL_EXTI_MODE_IT_EVENT:
00217           /* Directly Enable IT & Event on provided Lines */
00218           LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63);
00219           LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
00220           break;
00221         default:
00222           status = ERROR;
00223           break;
00224       }
00225       if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
00226       {
00227         switch (EXTI_InitStruct->Trigger)
00228         {
00229           case LL_EXTI_TRIGGER_RISING:
00230             /* First Disable Falling Trigger on provided Lines */
00231             LL_EXTI_DisableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
00232             /* Then Enable IT on provided Lines */
00233             LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
00234             break;
00235           case LL_EXTI_TRIGGER_FALLING:
00236             /* First Disable Rising Trigger on provided Lines */
00237             LL_EXTI_DisableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
00238             /* Then Enable Falling Trigger on provided Lines */
00239             LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
00240             break;
00241           case LL_EXTI_TRIGGER_RISING_FALLING:
00242             LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
00243             LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
00244             break;
00245           default:
00246             status = ERROR;
00247             break;
00248         }
00249       }
00250     }
00251   }
00252   /* DISABLE LineCommand */
00253   else
00254   {
00255     /* De-configure EXTI Lines in range from 0 to 31 */
00256     LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
00257     LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
00258     /* De-configure EXTI Lines in range from 32 to 63 */
00259     LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
00260     LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
00261   }
00262   return status;
00263 }
00264
00265 /**
00266   * @brief  Set each @ref LL_EXTI_InitTypeDef field to default value.
00267   * @param  EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
00268   * @retval None
00269   */
00270 void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
00271 {
00272   EXTI_InitStruct->Line_0_31      = LL_EXTI_LINE_NONE;
00273   EXTI_InitStruct->Line_32_63     = LL_EXTI_LINE_NONE;
00274   EXTI_InitStruct->LineCommand    = DISABLE;
00275   EXTI_InitStruct->Mode           = LL_EXTI_MODE_IT;
00276   EXTI_InitStruct->Trigger        = LL_EXTI_TRIGGER_FALLING;
00277 }
00278
00279 /**
00280   * @}
00281   */
00282
00283 /**
00284   * @}
00285   */
00286
00287 /**
00288   * @}
00289   */
00290
00291 #endif /* defined (EXTI) */
00292
00293 /**
00294   * @}
00295   */
00296
00297 #endif /* USE_FULL_LL_DRIVER */
00298
00299 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_exti.h Source File

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stm32wbxx_ll_exti.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_exti.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of EXTI LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_LL_EXTI_H
00022 #define STM32WBxx_LL_EXTI_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx.h"
00030
00031 /** @addtogroup STM32WBxx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (EXTI)
00036
00037 /** @defgroup EXTI_LL EXTI
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /* Private Macros ------------------------------------------------------------*/
00045 #if defined(USE_FULL_LL_DRIVER)
00046 /** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
00047   * @{
00048   */
00049 /**
00050   * @}
00051   */
00052 #endif /*USE_FULL_LL_DRIVER*/
00053 /* Exported types ------------------------------------------------------------*/
00054 #if defined(USE_FULL_LL_DRIVER)
00055 /** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
00056   * @{
00057   */
00058 typedef struct
00059 {
00060
00061   uint32_t Line_0_31;           /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
00062                                      This parameter can be any combination of @ref EXTI_LL_EC_LINE */
00063
00064   uint32_t Line_32_63;          /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63
00065                                      This parameter can be any combination of @ref EXTI_LL_EC_LINE */
00066
00067   FunctionalState LineCommand;  /*!< Specifies the new state of the selected EXTI lines.
00068                                      This parameter can be set either to ENABLE or DISABLE */
00069
00070   uint8_t Mode;                 /*!< Specifies the mode for the EXTI lines.
00071                                      This parameter can be a value of @ref EXTI_LL_EC_MODE. */
00072
00073   uint8_t Trigger;              /*!< Specifies the trigger signal active edge for the EXTI lines.
00074                                      This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
00075 } LL_EXTI_InitTypeDef;
00076
00077 /**
00078   * @}
00079   */
00080 #endif /*USE_FULL_LL_DRIVER*/
00081
00082 /* Exported constants --------------------------------------------------------*/
00083 /** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
00084   * @{
00085   */
00086
00087 /** @defgroup EXTI_LL_EC_LINE LINE
00088   * @{
00089   */
00090 #define LL_EXTI_LINE_0                 EXTI_IMR1_IM0           /*!< Extended line 0 */
00091 #define LL_EXTI_LINE_1                 EXTI_IMR1_IM1           /*!< Extended line 1 */
00092 #define LL_EXTI_LINE_2                 EXTI_IMR1_IM2           /*!< Extended line 2 */
00093 #define LL_EXTI_LINE_3                 EXTI_IMR1_IM3           /*!< Extended line 3 */
00094 #define LL_EXTI_LINE_4                 EXTI_IMR1_IM4           /*!< Extended line 4 */
00095 #define LL_EXTI_LINE_5                 EXTI_IMR1_IM5           /*!< Extended line 5 */
00096 #define LL_EXTI_LINE_6                 EXTI_IMR1_IM6           /*!< Extended line 6 */
00097 #define LL_EXTI_LINE_7                 EXTI_IMR1_IM7           /*!< Extended line 7 */
00098 #define LL_EXTI_LINE_8                 EXTI_IMR1_IM8           /*!< Extended line 8 */
00099 #define LL_EXTI_LINE_9                 EXTI_IMR1_IM9           /*!< Extended line 9 */
00100 #define LL_EXTI_LINE_10                EXTI_IMR1_IM10          /*!< Extended line 10 */
00101 #define LL_EXTI_LINE_11                EXTI_IMR1_IM11          /*!< Extended line 11 */
00102 #define LL_EXTI_LINE_12                EXTI_IMR1_IM12          /*!< Extended line 12 */
00103 #define LL_EXTI_LINE_13                EXTI_IMR1_IM13          /*!< Extended line 13 */
00104 #define LL_EXTI_LINE_14                EXTI_IMR1_IM14          /*!< Extended line 14 */
00105 #define LL_EXTI_LINE_15                EXTI_IMR1_IM15          /*!< Extended line 15 */
00106 #define LL_EXTI_LINE_16                EXTI_IMR1_IM16          /*!< Extended line 16 */
00107 #define LL_EXTI_LINE_17                EXTI_IMR1_IM17          /*!< Extended line 17 */
00108 #define LL_EXTI_LINE_18                EXTI_IMR1_IM18          /*!< Extended line 18 */
00109 #define LL_EXTI_LINE_19                EXTI_IMR1_IM19          /*!< Extended line 19 */
00110 #define LL_EXTI_LINE_20                EXTI_IMR1_IM20          /*!< Extended line 20 */
00111 #define LL_EXTI_LINE_21                EXTI_IMR1_IM21          /*!< Extended line 21 */
00112 #define LL_EXTI_LINE_22                EXTI_IMR1_IM22          /*!< Extended line 22 */
00113 #define LL_EXTI_LINE_23                EXTI_IMR1_IM23          /*!< Extended line 23 */
00114 #define LL_EXTI_LINE_24                EXTI_IMR1_IM24          /*!< Extended line 24 */
00115 #define LL_EXTI_LINE_25                EXTI_IMR1_IM25          /*!< Extended line 25 */
00116 #define LL_EXTI_LINE_28                EXTI_IMR1_IM28          /*!< Extended line 28 */
00117 #define LL_EXTI_LINE_29                EXTI_IMR1_IM29          /*!< Extended line 29 */
00118 #define LL_EXTI_LINE_30                EXTI_IMR1_IM30          /*!< Extended line 30 */
00119 #define LL_EXTI_LINE_31                EXTI_IMR1_IM31          /*!< Extended line 31 */
00120 #define LL_EXTI_LINE_ALL_0_31          (LL_EXTI_LINE_0 | LL_EXTI_LINE_1 | LL_EXTI_LINE_2 | \
00121                                         LL_EXTI_LINE_3 | LL_EXTI_LINE_4 | LL_EXTI_LINE_5 | \
00122                                         LL_EXTI_LINE_6 | LL_EXTI_LINE_7 | LL_EXTI_LINE_8 | \
00123                                         LL_EXTI_LINE_9 | LL_EXTI_LINE_10 | LL_EXTI_LINE_11 | \
00124                                         LL_EXTI_LINE_12 | LL_EXTI_LINE_13 | LL_EXTI_LINE_14 | \
00125                                         LL_EXTI_LINE_15 | LL_EXTI_LINE_16 | LL_EXTI_LINE_17 | \
00126                                         LL_EXTI_LINE_18 | LL_EXTI_LINE_19 | LL_EXTI_LINE_20 | \
00127                                         LL_EXTI_LINE_21 | LL_EXTI_LINE_22 | LL_EXTI_LINE_23 | \
00128                                         LL_EXTI_LINE_24 | LL_EXTI_LINE_25 | LL_EXTI_LINE_28 | \
00129                                         LL_EXTI_LINE_29 | LL_EXTI_LINE_30 | LL_EXTI_LINE_31) /*!< All Extended line not reserved*/
00130
00131 #define LL_EXTI_LINE_33                EXTI_IMR2_IM33          /*!< Extended line 33 */
00132 #define LL_EXTI_LINE_36                EXTI_IMR2_IM36          /*!< Extended line 36 */
00133 #define LL_EXTI_LINE_37                EXTI_IMR2_IM37          /*!< Extended line 37 */
00134 #define LL_EXTI_LINE_38                EXTI_IMR2_IM38          /*!< Extended line 38 */
00135 #define LL_EXTI_LINE_39                EXTI_IMR2_IM39          /*!< Extended line 39 */
00136 #define LL_EXTI_LINE_40                EXTI_IMR2_IM40          /*!< Extended line 40 */
00137 #define LL_EXTI_LINE_41                EXTI_IMR2_IM41          /*!< Extended line 41 */
00138 #define LL_EXTI_LINE_42                EXTI_IMR2_IM42          /*!< Extended line 42 */
00139 #if defined (STM32WB55xx)
00140 #define LL_EXTI_LINE_43                EXTI_IMR2_IM43          /*!< Extended line 43 */
00141 #endif
00142 #define LL_EXTI_LINE_44                EXTI_IMR2_IM44          /*!< Extended line 44 */
00143 #define LL_EXTI_LINE_45                EXTI_IMR2_IM45          /*!< Extended line 45 */
00144 #define LL_EXTI_LINE_46                EXTI_IMR2_IM46          /*!< Extended line 46 */
00145 #define LL_EXTI_LINE_48                EXTI_IMR2_IM48          /*!< Extended line 48 */
00146 #if defined (STM32WB55xx)
00147 #define LL_EXTI_LINE_ALL_32_63         (LL_EXTI_LINE_33 | LL_EXTI_LINE_36 | LL_EXTI_LINE_37 | \
00148                                         LL_EXTI_LINE_38 | LL_EXTI_LINE_39 | LL_EXTI_LINE_40 | \
00149                                         LL_EXTI_LINE_41 | LL_EXTI_LINE_42 | LL_EXTI_LINE_43 | \
00150                                         LL_EXTI_LINE_44 | LL_EXTI_LINE_45 | LL_EXTI_LINE_46 | \
00151                                         LL_EXTI_LINE_48)                                        /*!< All Extended line not reserved*/
00152 #else
00153 #define LL_EXTI_LINE_ALL_32_63         (LL_EXTI_LINE_33 | LL_EXTI_LINE_36 | LL_EXTI_LINE_37 | \
00154                                         LL_EXTI_LINE_38 | LL_EXTI_LINE_39 | LL_EXTI_LINE_40 | \
00155                                         LL_EXTI_LINE_41 | LL_EXTI_LINE_42 | LL_EXTI_LINE_44 | \
00156                                         LL_EXTI_LINE_45 | LL_EXTI_LINE_46 | LL_EXTI_LINE_48)  /*!< All Extended line not reserved*/
00157 #endif
00158
00159
00160 #define LL_EXTI_LINE_ALL               (0xFFFFFFFFU)  /*!< All Extended line */
00161
00162 #if defined(USE_FULL_LL_DRIVER)
00163 #define LL_EXTI_LINE_NONE              (0x00000000U)  /*!< None Extended line */
00164 #endif /*USE_FULL_LL_DRIVER*/
00165
00166 /**
00167   * @}
00168   */
00169 #if defined(USE_FULL_LL_DRIVER)
00170
00171 /** @defgroup EXTI_LL_EC_MODE Mode
00172   * @{
00173   */
00174 #define LL_EXTI_MODE_IT                 ((uint8_t)0x00U) /*!< Interrupt Mode */
00175 #define LL_EXTI_MODE_EVENT              ((uint8_t)0x01U) /*!< Event Mode */
00176 #define LL_EXTI_MODE_IT_EVENT           ((uint8_t)0x02U) /*!< Interrupt & Event Mode */
00177 /**
00178   * @}
00179   */
00180
00181 /** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
00182   * @{
00183   */
00184 #define LL_EXTI_TRIGGER_NONE            ((uint8_t)0x00U) /*!< No Trigger Mode */
00185 #define LL_EXTI_TRIGGER_RISING          ((uint8_t)0x01U) /*!< Trigger Rising Mode */
00186 #define LL_EXTI_TRIGGER_FALLING         ((uint8_t)0x02U) /*!< Trigger Falling Mode */
00187 #define LL_EXTI_TRIGGER_RISING_FALLING  ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */
00188
00189 /**
00190   * @}
00191   */
00192
00193
00194 #endif /*USE_FULL_LL_DRIVER*/
00195
00196
00197 /**
00198   * @}
00199   */
00200
00201 /* Exported macro ------------------------------------------------------------*/
00202 /** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
00203   * @{
00204   */
00205
00206 /** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
00207   * @{
00208   */
00209
00210 /**
00211   * @brief  Write a value in EXTI register
00212   * @param  __REG__ Register to be written
00213   * @param  __VALUE__ Value to be written in the register
00214   * @retval None
00215   */
00216 #define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
00217
00218 /**
00219   * @brief  Read a value in EXTI register
00220   * @param  __REG__ Register to be read
00221   * @retval Register value
00222   */
00223 #define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
00224 /**
00225   * @}
00226   */
00227
00228
00229 /**
00230   * @}
00231   */
00232
00233
00234
00235 /* Exported functions --------------------------------------------------------*/
00236 /** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
00237  * @{
00238  */
00239 /** @defgroup EXTI_LL_EF_IT_Management IT_Management
00240   * @{
00241   */
00242
00243 /**
00244   * @brief  Enable ExtiLine Interrupt request for Lines in range 0 to 31
00245   * @rmtoll IMR1         IMx           LL_EXTI_EnableIT_0_31
00246   * @param  ExtiLine This parameter can be one of the following values:
00247   *         @arg @ref LL_EXTI_LINE_0
00248   *         @arg @ref LL_EXTI_LINE_1
00249   *         @arg @ref LL_EXTI_LINE_2
00250   *         @arg @ref LL_EXTI_LINE_3
00251   *         @arg @ref LL_EXTI_LINE_4
00252   *         @arg @ref LL_EXTI_LINE_5
00253   *         @arg @ref LL_EXTI_LINE_6
00254   *         @arg @ref LL_EXTI_LINE_7
00255   *         @arg @ref LL_EXTI_LINE_8
00256   *         @arg @ref LL_EXTI_LINE_9
00257   *         @arg @ref LL_EXTI_LINE_10
00258   *         @arg @ref LL_EXTI_LINE_11
00259   *         @arg @ref LL_EXTI_LINE_12
00260   *         @arg @ref LL_EXTI_LINE_13
00261   *         @arg @ref LL_EXTI_LINE_14
00262   *         @arg @ref LL_EXTI_LINE_15
00263   *         @arg @ref LL_EXTI_LINE_16
00264   *         @arg @ref LL_EXTI_LINE_17
00265   *         @arg @ref LL_EXTI_LINE_18
00266   *         @arg @ref LL_EXTI_LINE_19
00267   *         @arg @ref LL_EXTI_LINE_20
00268   *         @arg @ref LL_EXTI_LINE_21
00269   *         @arg @ref LL_EXTI_LINE_22
00270   *         @arg @ref LL_EXTI_LINE_23
00271   *         @arg @ref LL_EXTI_LINE_24
00272   *         @arg @ref LL_EXTI_LINE_25
00273   *         @arg @ref LL_EXTI_LINE_28
00274   *         @arg @ref LL_EXTI_LINE_29
00275   *         @arg @ref LL_EXTI_LINE_30
00276   *         @arg @ref LL_EXTI_LINE_31
00277   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00278   * @retval None
00279   */
00280 __STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
00281 {
00282   SET_BIT(EXTI->IMR1, ExtiLine);
00283 }
00284
00285 /**
00286   * @brief  Enable ExtiLine Interrupt request for Lines in range 0 to 31 for cpu2
00287   * @rmtoll C2IMR1         IMx           LL_C2_EXTI_EnableIT_0_31
00288   * @param  ExtiLine This parameter can be one of the following values:
00289   *         @arg @ref LL_EXTI_LINE_0
00290   *         @arg @ref LL_EXTI_LINE_1
00291   *         @arg @ref LL_EXTI_LINE_2
00292   *         @arg @ref LL_EXTI_LINE_3
00293   *         @arg @ref LL_EXTI_LINE_4
00294   *         @arg @ref LL_EXTI_LINE_5
00295   *         @arg @ref LL_EXTI_LINE_6
00296   *         @arg @ref LL_EXTI_LINE_7
00297   *         @arg @ref LL_EXTI_LINE_8
00298   *         @arg @ref LL_EXTI_LINE_9
00299   *         @arg @ref LL_EXTI_LINE_10
00300   *         @arg @ref LL_EXTI_LINE_11
00301   *         @arg @ref LL_EXTI_LINE_12
00302   *         @arg @ref LL_EXTI_LINE_13
00303   *         @arg @ref LL_EXTI_LINE_14
00304   *         @arg @ref LL_EXTI_LINE_15
00305   *         @arg @ref LL_EXTI_LINE_16
00306   *         @arg @ref LL_EXTI_LINE_17
00307   *         @arg @ref LL_EXTI_LINE_18
00308   *         @arg @ref LL_EXTI_LINE_19
00309   *         @arg @ref LL_EXTI_LINE_20
00310   *         @arg @ref LL_EXTI_LINE_21
00311   *         @arg @ref LL_EXTI_LINE_22
00312   *         @arg @ref LL_EXTI_LINE_23
00313   *         @arg @ref LL_EXTI_LINE_24
00314   *         @arg @ref LL_EXTI_LINE_25
00315   *         @arg @ref LL_EXTI_LINE_28
00316   *         @arg @ref LL_EXTI_LINE_29
00317   *         @arg @ref LL_EXTI_LINE_30
00318   *         @arg @ref LL_EXTI_LINE_31
00319   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00320   * @retval None
00321   */
00322 __STATIC_INLINE void LL_C2_EXTI_EnableIT_0_31(uint32_t ExtiLine)
00323 {
00324   SET_BIT(EXTI->C2IMR1, ExtiLine);
00325 }
00326
00327 /**
00328   * @brief  Enable ExtiLine Interrupt request for Lines in range 32 to 63
00329   * @rmtoll IMR2         IMx           LL_EXTI_EnableIT_32_63
00330   * @param  ExtiLine This parameter can be one of the following values:
00331   *         @arg @ref LL_EXTI_LINE_33
00332   *         @arg @ref LL_EXTI_LINE_36
00333   *         @arg @ref LL_EXTI_LINE_37
00334   *         @arg @ref LL_EXTI_LINE_38
00335   *         @arg @ref LL_EXTI_LINE_39
00336   *         @arg @ref LL_EXTI_LINE_40
00337   *         @arg @ref LL_EXTI_LINE_41
00338   *         @arg @ref LL_EXTI_LINE_42
00339   *         @arg @ref LL_EXTI_LINE_43 (*)
00340   *         @arg @ref LL_EXTI_LINE_44
00341   *         @arg @ref LL_EXTI_LINE_45
00342   *         @arg @ref LL_EXTI_LINE_46
00343   *         @arg @ref LL_EXTI_LINE_48
00344   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00345   *         (*) value not defined in all devices
00346   * @retval None
00347   */
00348 __STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine)
00349 {
00350   SET_BIT(EXTI->IMR2, ExtiLine);
00351 }
00352
00353 /**
00354   * @brief  Enable ExtiLine Interrupt request for Lines in range 32 to 63 for cpu2
00355   * @rmtoll C2IMR2         IMx           LL_C2_EXTI_EnableIT_32_63
00356   * @param  ExtiLine This parameter can be one of the following values:
00357   *         @arg @ref LL_EXTI_LINE_33
00358   *         @arg @ref LL_EXTI_LINE_36
00359   *         @arg @ref LL_EXTI_LINE_37
00360   *         @arg @ref LL_EXTI_LINE_38
00361   *         @arg @ref LL_EXTI_LINE_39
00362   *         @arg @ref LL_EXTI_LINE_40
00363   *         @arg @ref LL_EXTI_LINE_41
00364   *         @arg @ref LL_EXTI_LINE_42
00365   *         @arg @ref LL_EXTI_LINE_43 (*)
00366   *         @arg @ref LL_EXTI_LINE_44
00367   *         @arg @ref LL_EXTI_LINE_45
00368   *         @arg @ref LL_EXTI_LINE_46
00369   *         @arg @ref LL_EXTI_LINE_48
00370   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00371   *         (*) value not defined in all devices
00372   * @retval None
00373   */
00374 __STATIC_INLINE void LL_C2_EXTI_EnableIT_32_63(uint32_t ExtiLine)
00375 {
00376   SET_BIT(EXTI->C2IMR2, ExtiLine);
00377 }
00378
00379 /**
00380   * @brief  Disable ExtiLine Interrupt request for Lines in range 0 to 31
00381   * @rmtoll IMR1         IMx           LL_EXTI_DisableIT_0_31
00382   * @param  ExtiLine This parameter can be one of the following values:
00383   *         @arg @ref LL_EXTI_LINE_0
00384   *         @arg @ref LL_EXTI_LINE_1
00385   *         @arg @ref LL_EXTI_LINE_2
00386   *         @arg @ref LL_EXTI_LINE_3
00387   *         @arg @ref LL_EXTI_LINE_4
00388   *         @arg @ref LL_EXTI_LINE_5
00389   *         @arg @ref LL_EXTI_LINE_6
00390   *         @arg @ref LL_EXTI_LINE_7
00391   *         @arg @ref LL_EXTI_LINE_8
00392   *         @arg @ref LL_EXTI_LINE_9
00393   *         @arg @ref LL_EXTI_LINE_10
00394   *         @arg @ref LL_EXTI_LINE_11
00395   *         @arg @ref LL_EXTI_LINE_12
00396   *         @arg @ref LL_EXTI_LINE_13
00397   *         @arg @ref LL_EXTI_LINE_14
00398   *         @arg @ref LL_EXTI_LINE_15
00399   *         @arg @ref LL_EXTI_LINE_16
00400   *         @arg @ref LL_EXTI_LINE_17
00401   *         @arg @ref LL_EXTI_LINE_18
00402   *         @arg @ref LL_EXTI_LINE_19
00403   *         @arg @ref LL_EXTI_LINE_20
00404   *         @arg @ref LL_EXTI_LINE_21
00405   *         @arg @ref LL_EXTI_LINE_22
00406   *         @arg @ref LL_EXTI_LINE_23
00407   *         @arg @ref LL_EXTI_LINE_24
00408   *         @arg @ref LL_EXTI_LINE_25
00409   *         @arg @ref LL_EXTI_LINE_28
00410   *         @arg @ref LL_EXTI_LINE_29
00411   *         @arg @ref LL_EXTI_LINE_30
00412   *         @arg @ref LL_EXTI_LINE_31
00413   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00414   * @retval None
00415   */
00416 __STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
00417 {
00418   CLEAR_BIT(EXTI->IMR1, ExtiLine);
00419 }
00420
00421 /**
00422   * @brief  Disable ExtiLine Interrupt request for Lines in range 0 to 31 for cpu2
00423   * @rmtoll C2IMR1         IMx           LL_C2_EXTI_DisableIT_0_31
00424   * @param  ExtiLine This parameter can be one of the following values:
00425   *         @arg @ref LL_EXTI_LINE_0
00426   *         @arg @ref LL_EXTI_LINE_1
00427   *         @arg @ref LL_EXTI_LINE_2
00428   *         @arg @ref LL_EXTI_LINE_3
00429   *         @arg @ref LL_EXTI_LINE_4
00430   *         @arg @ref LL_EXTI_LINE_5
00431   *         @arg @ref LL_EXTI_LINE_6
00432   *         @arg @ref LL_EXTI_LINE_7
00433   *         @arg @ref LL_EXTI_LINE_8
00434   *         @arg @ref LL_EXTI_LINE_9
00435   *         @arg @ref LL_EXTI_LINE_10
00436   *         @arg @ref LL_EXTI_LINE_11
00437   *         @arg @ref LL_EXTI_LINE_12
00438   *         @arg @ref LL_EXTI_LINE_13
00439   *         @arg @ref LL_EXTI_LINE_14
00440   *         @arg @ref LL_EXTI_LINE_15
00441   *         @arg @ref LL_EXTI_LINE_16
00442   *         @arg @ref LL_EXTI_LINE_17
00443   *         @arg @ref LL_EXTI_LINE_18
00444   *         @arg @ref LL_EXTI_LINE_19
00445   *         @arg @ref LL_EXTI_LINE_20
00446   *         @arg @ref LL_EXTI_LINE_21
00447   *         @arg @ref LL_EXTI_LINE_22
00448   *         @arg @ref LL_EXTI_LINE_23
00449   *         @arg @ref LL_EXTI_LINE_24
00450   *         @arg @ref LL_EXTI_LINE_25
00451   *         @arg @ref LL_EXTI_LINE_28
00452   *         @arg @ref LL_EXTI_LINE_29
00453   *         @arg @ref LL_EXTI_LINE_30
00454   *         @arg @ref LL_EXTI_LINE_31
00455   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00456   * @retval None
00457   */
00458 __STATIC_INLINE void LL_C2_EXTI_DisableIT_0_31(uint32_t ExtiLine)
00459 {
00460   CLEAR_BIT(EXTI->C2IMR1, ExtiLine);
00461 }
00462
00463 /**
00464   * @brief  Disable ExtiLine Interrupt request for Lines in range 32 to 63
00465   * @rmtoll IMR2         IMx           LL_EXTI_DisableIT_32_63
00466   * @param  ExtiLine This parameter can be one of the following values:
00467   *         @arg @ref LL_EXTI_LINE_33
00468   *         @arg @ref LL_EXTI_LINE_36
00469   *         @arg @ref LL_EXTI_LINE_37
00470   *         @arg @ref LL_EXTI_LINE_38
00471   *         @arg @ref LL_EXTI_LINE_39
00472   *         @arg @ref LL_EXTI_LINE_40
00473   *         @arg @ref LL_EXTI_LINE_41
00474   *         @arg @ref LL_EXTI_LINE_42
00475   *         @arg @ref LL_EXTI_LINE_43 (*)
00476   *         @arg @ref LL_EXTI_LINE_44
00477   *         @arg @ref LL_EXTI_LINE_45
00478   *         @arg @ref LL_EXTI_LINE_46
00479   *         @arg @ref LL_EXTI_LINE_48
00480   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00481   *         (*) value not defined in all devices
00482   * @retval None
00483   */
00484 __STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine)
00485 {
00486   CLEAR_BIT(EXTI->IMR2, ExtiLine);
00487 }
00488
00489 /**
00490   * @brief  Disable ExtiLine Interrupt request for Lines in range 32 to 63 for cpu2
00491   * @rmtoll C2IMR2         IMx           LL_C2_EXTI_DisableIT_32_63
00492   * @param  ExtiLine This parameter can be one of the following values:
00493   *         @arg @ref LL_EXTI_LINE_33
00494   *         @arg @ref LL_EXTI_LINE_36
00495   *         @arg @ref LL_EXTI_LINE_37
00496   *         @arg @ref LL_EXTI_LINE_38
00497   *         @arg @ref LL_EXTI_LINE_39
00498   *         @arg @ref LL_EXTI_LINE_40
00499   *         @arg @ref LL_EXTI_LINE_41
00500   *         @arg @ref LL_EXTI_LINE_42
00501   *         @arg @ref LL_EXTI_LINE_43 (*)
00502   *         @arg @ref LL_EXTI_LINE_44
00503   *         @arg @ref LL_EXTI_LINE_45
00504   *         @arg @ref LL_EXTI_LINE_46
00505   *         @arg @ref LL_EXTI_LINE_48
00506   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00507   *         (*) value not defined in all devices
00508   * @retval None
00509   */
00510 __STATIC_INLINE void LL_C2_EXTI_DisableIT_32_63(uint32_t ExtiLine)
00511 {
00512   CLEAR_BIT(EXTI->C2IMR2, ExtiLine);
00513 }
00514
00515 /**
00516   * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
00517   * @rmtoll IMR1         IMx           LL_EXTI_IsEnabledIT_0_31
00518   * @param  ExtiLine This parameter can be one of the following values:
00519   *         @arg @ref LL_EXTI_LINE_0
00520   *         @arg @ref LL_EXTI_LINE_1
00521   *         @arg @ref LL_EXTI_LINE_2
00522   *         @arg @ref LL_EXTI_LINE_3
00523   *         @arg @ref LL_EXTI_LINE_4
00524   *         @arg @ref LL_EXTI_LINE_5
00525   *         @arg @ref LL_EXTI_LINE_6
00526   *         @arg @ref LL_EXTI_LINE_7
00527   *         @arg @ref LL_EXTI_LINE_8
00528   *         @arg @ref LL_EXTI_LINE_9
00529   *         @arg @ref LL_EXTI_LINE_10
00530   *         @arg @ref LL_EXTI_LINE_11
00531   *         @arg @ref LL_EXTI_LINE_12
00532   *         @arg @ref LL_EXTI_LINE_13
00533   *         @arg @ref LL_EXTI_LINE_14
00534   *         @arg @ref LL_EXTI_LINE_15
00535   *         @arg @ref LL_EXTI_LINE_16
00536   *         @arg @ref LL_EXTI_LINE_17
00537   *         @arg @ref LL_EXTI_LINE_18
00538   *         @arg @ref LL_EXTI_LINE_19
00539   *         @arg @ref LL_EXTI_LINE_20
00540   *         @arg @ref LL_EXTI_LINE_21
00541   *         @arg @ref LL_EXTI_LINE_22
00542   *         @arg @ref LL_EXTI_LINE_23
00543   *         @arg @ref LL_EXTI_LINE_24
00544   *         @arg @ref LL_EXTI_LINE_25
00545   *         @arg @ref LL_EXTI_LINE_28
00546   *         @arg @ref LL_EXTI_LINE_29
00547   *         @arg @ref LL_EXTI_LINE_30
00548   *         @arg @ref LL_EXTI_LINE_31
00549   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00550   * @retval State of bit (1 or 0).
00551   */
00552 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
00553 {
00554   return ((READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
00555 }
00556
00557 /**
00558   * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 for cpu2
00559   * @rmtoll C2IMR1         IMx           LL_C2_EXTI_IsEnabledIT_0_31
00560   * @param  ExtiLine This parameter can be one of the following values:
00561   *         @arg @ref LL_EXTI_LINE_0
00562   *         @arg @ref LL_EXTI_LINE_1
00563   *         @arg @ref LL_EXTI_LINE_2
00564   *         @arg @ref LL_EXTI_LINE_3
00565   *         @arg @ref LL_EXTI_LINE_4
00566   *         @arg @ref LL_EXTI_LINE_5
00567   *         @arg @ref LL_EXTI_LINE_6
00568   *         @arg @ref LL_EXTI_LINE_7
00569   *         @arg @ref LL_EXTI_LINE_8
00570   *         @arg @ref LL_EXTI_LINE_9
00571   *         @arg @ref LL_EXTI_LINE_10
00572   *         @arg @ref LL_EXTI_LINE_11
00573   *         @arg @ref LL_EXTI_LINE_12
00574   *         @arg @ref LL_EXTI_LINE_13
00575   *         @arg @ref LL_EXTI_LINE_14
00576   *         @arg @ref LL_EXTI_LINE_15
00577   *         @arg @ref LL_EXTI_LINE_16
00578   *         @arg @ref LL_EXTI_LINE_17
00579   *         @arg @ref LL_EXTI_LINE_18
00580   *         @arg @ref LL_EXTI_LINE_19
00581   *         @arg @ref LL_EXTI_LINE_20
00582   *         @arg @ref LL_EXTI_LINE_21
00583   *         @arg @ref LL_EXTI_LINE_22
00584   *         @arg @ref LL_EXTI_LINE_23
00585   *         @arg @ref LL_EXTI_LINE_24
00586   *         @arg @ref LL_EXTI_LINE_25
00587   *         @arg @ref LL_EXTI_LINE_28
00588   *         @arg @ref LL_EXTI_LINE_29
00589   *         @arg @ref LL_EXTI_LINE_30
00590   *         @arg @ref LL_EXTI_LINE_31
00591   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00592   * @retval State of bit (1 or 0).
00593   */
00594 __STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
00595 {
00596   return ((READ_BIT(EXTI->C2IMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
00597 }
00598
00599 /**
00600   * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63
00601   * @rmtoll IMR2         IMx           LL_EXTI_IsEnabledIT_32_63
00602   * @param  ExtiLine This parameter can be one of the following values:
00603   *         @arg @ref LL_EXTI_LINE_33
00604   *         @arg @ref LL_EXTI_LINE_36
00605   *         @arg @ref LL_EXTI_LINE_37
00606   *         @arg @ref LL_EXTI_LINE_38
00607   *         @arg @ref LL_EXTI_LINE_39
00608   *         @arg @ref LL_EXTI_LINE_40
00609   *         @arg @ref LL_EXTI_LINE_41
00610   *         @arg @ref LL_EXTI_LINE_42
00611   *         @arg @ref LL_EXTI_LINE_43 (*)
00612   *         @arg @ref LL_EXTI_LINE_44
00613   *         @arg @ref LL_EXTI_LINE_45
00614   *         @arg @ref LL_EXTI_LINE_46
00615   *         @arg @ref LL_EXTI_LINE_48
00616   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00617   *         (*) value not defined in all devices
00618   * @retval State of bit (1 or 0).
00619   */
00620 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine)
00621 {
00622   return ((READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
00623 }
00624
00625 /**
00626   * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63 for cpu2
00627   * @rmtoll C2IMR2         IMx           LL_C2_EXTI_IsEnabledIT_32_63
00628   * @param  ExtiLine This parameter can be one of the following values:
00629   *         @arg @ref LL_EXTI_LINE_33
00630   *         @arg @ref LL_EXTI_LINE_36
00631   *         @arg @ref LL_EXTI_LINE_37
00632   *         @arg @ref LL_EXTI_LINE_38
00633   *         @arg @ref LL_EXTI_LINE_39
00634   *         @arg @ref LL_EXTI_LINE_40
00635   *         @arg @ref LL_EXTI_LINE_41
00636   *         @arg @ref LL_EXTI_LINE_42
00637   *         @arg @ref LL_EXTI_LINE_43 (*)
00638   *         @arg @ref LL_EXTI_LINE_44
00639   *         @arg @ref LL_EXTI_LINE_45
00640   *         @arg @ref LL_EXTI_LINE_46
00641   *         @arg @ref LL_EXTI_LINE_48
00642   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00643   *         (*) value not defined in all devices
00644   * @retval State of bit (1 or 0).
00645   */
00646 __STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine)
00647 {
00648   return ((READ_BIT(EXTI->C2IMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
00649 }
00650
00651 /**
00652   * @}
00653   */
00654
00655 /** @defgroup EXTI_LL_EF_Event_Management Event_Management
00656   * @{
00657   */
00658
00659 /**
00660   * @brief  Enable ExtiLine Event request for Lines in range 0 to 31
00661   * @rmtoll EMR1         EMx           LL_EXTI_EnableEvent_0_31
00662   * @param  ExtiLine This parameter can be one of the following values:
00663   *         @arg @ref LL_EXTI_LINE_0
00664   *         @arg @ref LL_EXTI_LINE_1
00665   *         @arg @ref LL_EXTI_LINE_2
00666   *         @arg @ref LL_EXTI_LINE_3
00667   *         @arg @ref LL_EXTI_LINE_4
00668   *         @arg @ref LL_EXTI_LINE_5
00669   *         @arg @ref LL_EXTI_LINE_6
00670   *         @arg @ref LL_EXTI_LINE_7
00671   *         @arg @ref LL_EXTI_LINE_8
00672   *         @arg @ref LL_EXTI_LINE_9
00673   *         @arg @ref LL_EXTI_LINE_10
00674   *         @arg @ref LL_EXTI_LINE_11
00675   *         @arg @ref LL_EXTI_LINE_12
00676   *         @arg @ref LL_EXTI_LINE_13
00677   *         @arg @ref LL_EXTI_LINE_14
00678   *         @arg @ref LL_EXTI_LINE_15
00679   *         @arg @ref LL_EXTI_LINE_17
00680   *         @arg @ref LL_EXTI_LINE_18
00681   *         @arg @ref LL_EXTI_LINE_19
00682   *         @arg @ref LL_EXTI_LINE_20
00683   *         @arg @ref LL_EXTI_LINE_21
00684   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00685   * @retval None
00686   */
00687 __STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
00688 {
00689   SET_BIT(EXTI->EMR1, ExtiLine);
00690 }
00691
00692 /**
00693   * @brief  Enable ExtiLine Event request for Lines in range 0 to 31 for cpu2
00694   * @rmtoll C2EMR1         EMx           LL_C2_EXTI_EnableEvent_0_31
00695   * @param  ExtiLine This parameter can be one of the following values:
00696   *         @arg @ref LL_EXTI_LINE_0
00697   *         @arg @ref LL_EXTI_LINE_1
00698   *         @arg @ref LL_EXTI_LINE_2
00699   *         @arg @ref LL_EXTI_LINE_3
00700   *         @arg @ref LL_EXTI_LINE_4
00701   *         @arg @ref LL_EXTI_LINE_5
00702   *         @arg @ref LL_EXTI_LINE_6
00703   *         @arg @ref LL_EXTI_LINE_7
00704   *         @arg @ref LL_EXTI_LINE_8
00705   *         @arg @ref LL_EXTI_LINE_9
00706   *         @arg @ref LL_EXTI_LINE_10
00707   *         @arg @ref LL_EXTI_LINE_11
00708   *         @arg @ref LL_EXTI_LINE_12
00709   *         @arg @ref LL_EXTI_LINE_13
00710   *         @arg @ref LL_EXTI_LINE_14
00711   *         @arg @ref LL_EXTI_LINE_15
00712   *         @arg @ref LL_EXTI_LINE_17
00713   *         @arg @ref LL_EXTI_LINE_18
00714   *         @arg @ref LL_EXTI_LINE_19
00715   *         @arg @ref LL_EXTI_LINE_20
00716   *         @arg @ref LL_EXTI_LINE_21
00717   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00718   * @retval None
00719   */
00720 __STATIC_INLINE void LL_C2_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
00721 {
00722   SET_BIT(EXTI->C2EMR1, ExtiLine);
00723 }
00724
00725 /**
00726   * @brief  Enable ExtiLine Event request for Lines in range 32 to 63
00727   * @rmtoll EMR2         EMx           LL_EXTI_EnableEvent_32_63
00728   * @param  ExtiLine This parameter can be a combination of the following values:
00729   *         @arg @ref LL_EXTI_LINE_40
00730   *         @arg @ref LL_EXTI_LINE_41
00731   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00732   * @retval None
00733   */
00734 __STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine)
00735 {
00736   SET_BIT(EXTI->EMR2, ExtiLine);
00737 }
00738
00739 /**
00740   * @brief  Enable ExtiLine Event request for Lines in range 32 to 63 for cpu2
00741   * @rmtoll C2EMR2         EMx           LL_C2_EXTI_EnableEvent_32_63
00742   * @param  ExtiLine This parameter can be a combination of the following values:
00743   *         @arg @ref LL_EXTI_LINE_40
00744   *         @arg @ref LL_EXTI_LINE_41
00745   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00746   * @retval None
00747   */
00748 __STATIC_INLINE void LL_C2_EXTI_EnableEvent_32_63(uint32_t ExtiLine)
00749 {
00750   SET_BIT(EXTI->C2EMR2, ExtiLine);
00751 }
00752
00753 /**
00754   * @brief  Disable ExtiLine Event request for Lines in range 0 to 31
00755   * @rmtoll EMR1         EMx           LL_EXTI_DisableEvent_0_31
00756   * @param  ExtiLine This parameter can be one of the following values:
00757   *         @arg @ref LL_EXTI_LINE_0
00758   *         @arg @ref LL_EXTI_LINE_1
00759   *         @arg @ref LL_EXTI_LINE_2
00760   *         @arg @ref LL_EXTI_LINE_3
00761   *         @arg @ref LL_EXTI_LINE_4
00762   *         @arg @ref LL_EXTI_LINE_5
00763   *         @arg @ref LL_EXTI_LINE_6
00764   *         @arg @ref LL_EXTI_LINE_7
00765   *         @arg @ref LL_EXTI_LINE_8
00766   *         @arg @ref LL_EXTI_LINE_9
00767   *         @arg @ref LL_EXTI_LINE_10
00768   *         @arg @ref LL_EXTI_LINE_11
00769   *         @arg @ref LL_EXTI_LINE_12
00770   *         @arg @ref LL_EXTI_LINE_13
00771   *         @arg @ref LL_EXTI_LINE_14
00772   *         @arg @ref LL_EXTI_LINE_15
00773   *         @arg @ref LL_EXTI_LINE_17
00774   *         @arg @ref LL_EXTI_LINE_18
00775   *         @arg @ref LL_EXTI_LINE_19
00776   *         @arg @ref LL_EXTI_LINE_20
00777   *         @arg @ref LL_EXTI_LINE_21
00778   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00779   * @retval None
00780   */
00781 __STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
00782 {
00783   CLEAR_BIT(EXTI->EMR1, ExtiLine);
00784 }
00785
00786 /**
00787   * @brief  Disable ExtiLine Event request for Lines in range 0 to 31 for cpu2
00788   * @rmtoll C2EMR1         EMx           LL_C2_EXTI_DisableEvent_0_31
00789   * @param  ExtiLine This parameter can be one of the following values:
00790   *         @arg @ref LL_EXTI_LINE_0
00791   *         @arg @ref LL_EXTI_LINE_1
00792   *         @arg @ref LL_EXTI_LINE_2
00793   *         @arg @ref LL_EXTI_LINE_3
00794   *         @arg @ref LL_EXTI_LINE_4
00795   *         @arg @ref LL_EXTI_LINE_5
00796   *         @arg @ref LL_EXTI_LINE_6
00797   *         @arg @ref LL_EXTI_LINE_7
00798   *         @arg @ref LL_EXTI_LINE_8
00799   *         @arg @ref LL_EXTI_LINE_9
00800   *         @arg @ref LL_EXTI_LINE_10
00801   *         @arg @ref LL_EXTI_LINE_11
00802   *         @arg @ref LL_EXTI_LINE_12
00803   *         @arg @ref LL_EXTI_LINE_13
00804   *         @arg @ref LL_EXTI_LINE_14
00805   *         @arg @ref LL_EXTI_LINE_15
00806   *         @arg @ref LL_EXTI_LINE_17
00807   *         @arg @ref LL_EXTI_LINE_18
00808   *         @arg @ref LL_EXTI_LINE_19
00809   *         @arg @ref LL_EXTI_LINE_20
00810   *         @arg @ref LL_EXTI_LINE_21
00811   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00812   * @retval None
00813   */
00814 __STATIC_INLINE void LL_C2_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
00815 {
00816   CLEAR_BIT(EXTI->C2EMR1, ExtiLine);
00817 }
00818
00819 /**
00820   * @brief  Disable ExtiLine Event request for Lines in range 32 to 63
00821   * @rmtoll EMR2         EMx           LL_EXTI_DisableEvent_32_63
00822   * @param  ExtiLine This parameter can be a combination of the following values:
00823   *         @arg @ref LL_EXTI_LINE_40
00824   *         @arg @ref LL_EXTI_LINE_41
00825   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00826   * @retval None
00827   */
00828 __STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine)
00829 {
00830   CLEAR_BIT(EXTI->EMR2, ExtiLine);
00831 }
00832
00833 /**
00834   * @brief  Disable ExtiLine Event request for Lines in range 32 to 63 for cpu2
00835   * @rmtoll C2EMR2         EMx           LL_C2_EXTI_DisableEvent_32_63
00836   * @param  ExtiLine This parameter can be a combination of the following values:
00837   *         @arg @ref LL_EXTI_LINE_40
00838   *         @arg @ref LL_EXTI_LINE_41
00839   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00840   * @retval None
00841   */
00842 __STATIC_INLINE void LL_C2_EXTI_DisableEvent_32_63(uint32_t ExtiLine)
00843 {
00844   CLEAR_BIT(EXTI->C2EMR2, ExtiLine);
00845 }
00846
00847 /**
00848   * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
00849   * @rmtoll EMR1         EMx           LL_EXTI_IsEnabledEvent_0_31
00850   * @param  ExtiLine This parameter can be one of the following values:
00851   *         @arg @ref LL_EXTI_LINE_0
00852   *         @arg @ref LL_EXTI_LINE_1
00853   *         @arg @ref LL_EXTI_LINE_2
00854   *         @arg @ref LL_EXTI_LINE_3
00855   *         @arg @ref LL_EXTI_LINE_4
00856   *         @arg @ref LL_EXTI_LINE_5
00857   *         @arg @ref LL_EXTI_LINE_6
00858   *         @arg @ref LL_EXTI_LINE_7
00859   *         @arg @ref LL_EXTI_LINE_8
00860   *         @arg @ref LL_EXTI_LINE_9
00861   *         @arg @ref LL_EXTI_LINE_10
00862   *         @arg @ref LL_EXTI_LINE_11
00863   *         @arg @ref LL_EXTI_LINE_12
00864   *         @arg @ref LL_EXTI_LINE_13
00865   *         @arg @ref LL_EXTI_LINE_14
00866   *         @arg @ref LL_EXTI_LINE_15
00867   *         @arg @ref LL_EXTI_LINE_17
00868   *         @arg @ref LL_EXTI_LINE_18
00869   *         @arg @ref LL_EXTI_LINE_19
00870   *         @arg @ref LL_EXTI_LINE_20
00871   *         @arg @ref LL_EXTI_LINE_21
00872   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00873   * @note   Please check each device line mapping for EXTI Line availability
00874   * @retval State of bit (1 or 0).
00875   */
00876 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
00877 {
00878   return ((READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
00879 }
00880
00881 /**
00882   * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 for cpu2
00883   * @rmtoll C2EMR1         EMx           LL_C2_EXTI_IsEnabledEvent_0_31
00884   * @param  ExtiLine This parameter can be one of the following values:
00885   *         @arg @ref LL_EXTI_LINE_0
00886   *         @arg @ref LL_EXTI_LINE_1
00887   *         @arg @ref LL_EXTI_LINE_2
00888   *         @arg @ref LL_EXTI_LINE_3
00889   *         @arg @ref LL_EXTI_LINE_4
00890   *         @arg @ref LL_EXTI_LINE_5
00891   *         @arg @ref LL_EXTI_LINE_6
00892   *         @arg @ref LL_EXTI_LINE_7
00893   *         @arg @ref LL_EXTI_LINE_8
00894   *         @arg @ref LL_EXTI_LINE_9
00895   *         @arg @ref LL_EXTI_LINE_10
00896   *         @arg @ref LL_EXTI_LINE_11
00897   *         @arg @ref LL_EXTI_LINE_12
00898   *         @arg @ref LL_EXTI_LINE_13
00899   *         @arg @ref LL_EXTI_LINE_14
00900   *         @arg @ref LL_EXTI_LINE_15
00901   *         @arg @ref LL_EXTI_LINE_17
00902   *         @arg @ref LL_EXTI_LINE_18
00903   *         @arg @ref LL_EXTI_LINE_19
00904   *         @arg @ref LL_EXTI_LINE_20
00905   *         @arg @ref LL_EXTI_LINE_21
00906   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00907   * @note   Please check each device line mapping for EXTI Line availability
00908   * @retval State of bit (1 or 0).
00909   */
00910 __STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
00911 {
00912   return ((READ_BIT(EXTI->C2EMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
00913 }
00914
00915 /**
00916   * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63
00917   * @rmtoll EMR2         EMx           LL_EXTI_IsEnabledEvent_32_63
00918   * @param  ExtiLine This parameter can be a combination of the following values:
00919   *         @arg @ref LL_EXTI_LINE_40
00920   *         @arg @ref LL_EXTI_LINE_41
00921   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00922   * @retval State of bit (1 or 0).
00923   */
00924 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine)
00925 {
00926   return ((READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
00927 }
00928
00929 /**
00930   * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63 for cpu2
00931   * @rmtoll EMR2         EMx           LL_C2_EXTI_IsEnabledEvent_32_63
00932   * @param  ExtiLine This parameter can be a combination of the following values:
00933   *         @arg @ref LL_EXTI_LINE_40
00934   *         @arg @ref LL_EXTI_LINE_41
00935   *         @arg @ref LL_EXTI_LINE_ALL_32_63
00936   * @retval State of bit (1 or 0).
00937   */
00938 __STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine)
00939 {
00940   return ((READ_BIT(EXTI->C2EMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
00941 }
00942
00943 /**
00944   * @}
00945   */
00946
00947 /** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
00948   * @{
00949   */
00950
00951 /**
00952   * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
00953   * @note The configurable wakeup lines are edge-triggered. No glitch must be
00954   *       generated on these lines. If a rising edge on a configurable interrupt
00955   *       line occurs during a write operation in the EXTI_RTSR register, the
00956   *       pending bit is not set.
00957   *       Rising and falling edge triggers can be set for
00958   *       the same interrupt line. In this case, both generate a trigger
00959   *       condition.
00960   * @rmtoll RTSR1        RTx           LL_EXTI_EnableRisingTrig_0_31
00961   * @param  ExtiLine This parameter can be a combination of the following values:
00962   *         @arg @ref LL_EXTI_LINE_0
00963   *         @arg @ref LL_EXTI_LINE_1
00964   *         @arg @ref LL_EXTI_LINE_2
00965   *         @arg @ref LL_EXTI_LINE_3
00966   *         @arg @ref LL_EXTI_LINE_4
00967   *         @arg @ref LL_EXTI_LINE_5
00968   *         @arg @ref LL_EXTI_LINE_6
00969   *         @arg @ref LL_EXTI_LINE_7
00970   *         @arg @ref LL_EXTI_LINE_8
00971   *         @arg @ref LL_EXTI_LINE_9
00972   *         @arg @ref LL_EXTI_LINE_10
00973   *         @arg @ref LL_EXTI_LINE_11
00974   *         @arg @ref LL_EXTI_LINE_12
00975   *         @arg @ref LL_EXTI_LINE_13
00976   *         @arg @ref LL_EXTI_LINE_14
00977   *         @arg @ref LL_EXTI_LINE_15
00978   *         @arg @ref LL_EXTI_LINE_16
00979   *         @arg @ref LL_EXTI_LINE_17
00980   *         @arg @ref LL_EXTI_LINE_18
00981   *         @arg @ref LL_EXTI_LINE_19
00982   *         @arg @ref LL_EXTI_LINE_20
00983   *         @arg @ref LL_EXTI_LINE_21
00984   *         @arg @ref LL_EXTI_LINE_31
00985   * @retval None
00986   */
00987 __STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
00988 {
00989   SET_BIT(EXTI->RTSR1, ExtiLine);
00990
00991 }
00992
00993 /**
00994   * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
00995   * @note The configurable wakeup lines are edge-triggered. No glitch must be
00996   *       generated on these lines. If a rising edge on a configurable interrupt
00997   *       line occurs during a write operation in the EXTI_RTSR register, the
00998   *       pending bit is not set.Rising and falling edge triggers can be set for
00999   *       the same interrupt line. In this case, both generate a trigger
01000   *       condition.
01001   * @rmtoll RTSR2        RTx           LL_EXTI_EnableRisingTrig_32_63
01002   * @param  ExtiLine This parameter can be a combination of the following values:
01003   *         @arg @ref LL_EXTI_LINE_33
01004   *         @arg @ref LL_EXTI_LINE_40
01005   *         @arg @ref LL_EXTI_LINE_41
01006   * @retval None
01007   */
01008 __STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine)
01009 {
01010   SET_BIT(EXTI->RTSR2, ExtiLine);
01011 }
01012
01013 /**
01014   * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
01015   * @note The configurable wakeup lines are edge-triggered. No glitch must be
01016   *       generated on these lines. If a rising edge on a configurable interrupt
01017   *       line occurs during a write operation in the EXTI_RTSR register, the
01018   *       pending bit is not set.
01019   *       Rising and falling edge triggers can be set for
01020   *       the same interrupt line. In this case, both generate a trigger
01021   *       condition.
01022   * @rmtoll RTSR1        RTx           LL_EXTI_DisableRisingTrig_0_31
01023   * @param  ExtiLine This parameter can be a combination of the following values:
01024   *         @arg @ref LL_EXTI_LINE_0
01025   *         @arg @ref LL_EXTI_LINE_1
01026   *         @arg @ref LL_EXTI_LINE_2
01027   *         @arg @ref LL_EXTI_LINE_3
01028   *         @arg @ref LL_EXTI_LINE_4
01029   *         @arg @ref LL_EXTI_LINE_5
01030   *         @arg @ref LL_EXTI_LINE_6
01031   *         @arg @ref LL_EXTI_LINE_7
01032   *         @arg @ref LL_EXTI_LINE_8
01033   *         @arg @ref LL_EXTI_LINE_9
01034   *         @arg @ref LL_EXTI_LINE_10
01035   *         @arg @ref LL_EXTI_LINE_11
01036   *         @arg @ref LL_EXTI_LINE_12
01037   *         @arg @ref LL_EXTI_LINE_13
01038   *         @arg @ref LL_EXTI_LINE_14
01039   *         @arg @ref LL_EXTI_LINE_15
01040   *         @arg @ref LL_EXTI_LINE_16
01041   *         @arg @ref LL_EXTI_LINE_17
01042   *         @arg @ref LL_EXTI_LINE_18
01043   *         @arg @ref LL_EXTI_LINE_19
01044   *         @arg @ref LL_EXTI_LINE_20
01045   *         @arg @ref LL_EXTI_LINE_21
01046   *         @arg @ref LL_EXTI_LINE_31
01047   * @retval None
01048   */
01049 __STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
01050 {
01051   CLEAR_BIT(EXTI->RTSR1, ExtiLine);
01052
01053 }
01054
01055 /**
01056   * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
01057   * @note The configurable wakeup lines are edge-triggered. No glitch must be
01058   *       generated on these lines. If a rising edge on a configurable interrupt
01059   *       line occurs during a write operation in the EXTI_RTSR register, the
01060   *       pending bit is not set.
01061   *       Rising and falling edge triggers can be set for
01062   *       the same interrupt line. In this case, both generate a trigger
01063   *       condition.
01064   * @rmtoll RTSR2        RTx           LL_EXTI_DisableRisingTrig_32_63
01065   * @param  ExtiLine This parameter can be a combination of the following values:
01066   *         @arg @ref LL_EXTI_LINE_33
01067   *         @arg @ref LL_EXTI_LINE_40
01068   *         @arg @ref LL_EXTI_LINE_41
01069   * @retval None
01070   */
01071 __STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine)
01072 {
01073   CLEAR_BIT(EXTI->RTSR2, ExtiLine);
01074 }
01075
01076 /**
01077   * @brief  Check if rising edge trigger is enabled for Lines in range 0 to 31
01078   * @rmtoll RTSR1        RTx           LL_EXTI_IsEnabledRisingTrig_0_31
01079   * @param  ExtiLine This parameter can be a combination of the following values:
01080   *         @arg @ref LL_EXTI_LINE_0
01081   *         @arg @ref LL_EXTI_LINE_1
01082   *         @arg @ref LL_EXTI_LINE_2
01083   *         @arg @ref LL_EXTI_LINE_3
01084   *         @arg @ref LL_EXTI_LINE_4
01085   *         @arg @ref LL_EXTI_LINE_5
01086   *         @arg @ref LL_EXTI_LINE_6
01087   *         @arg @ref LL_EXTI_LINE_7
01088   *         @arg @ref LL_EXTI_LINE_8
01089   *         @arg @ref LL_EXTI_LINE_9
01090   *         @arg @ref LL_EXTI_LINE_10
01091   *         @arg @ref LL_EXTI_LINE_11
01092   *         @arg @ref LL_EXTI_LINE_12
01093   *         @arg @ref LL_EXTI_LINE_13
01094   *         @arg @ref LL_EXTI_LINE_14
01095   *         @arg @ref LL_EXTI_LINE_15
01096   *         @arg @ref LL_EXTI_LINE_16
01097   *         @arg @ref LL_EXTI_LINE_17
01098   *         @arg @ref LL_EXTI_LINE_18
01099   *         @arg @ref LL_EXTI_LINE_19
01100   *         @arg @ref LL_EXTI_LINE_20
01101   *         @arg @ref LL_EXTI_LINE_21
01102   *         @arg @ref LL_EXTI_LINE_31
01103   * @retval State of bit (1 or 0).
01104   */
01105 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
01106 {
01107   return ((READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
01108 }
01109
01110 /**
01111   * @brief  Check if rising edge trigger is enabled for Lines in range 32 to 63
01112   * @rmtoll RTSR2        RTx           LL_EXTI_IsEnabledRisingTrig_32_63
01113   * @param  ExtiLine This parameter can be a combination of the following values:
01114   *         @arg @ref LL_EXTI_LINE_33
01115   *         @arg @ref LL_EXTI_LINE_40
01116   *         @arg @ref LL_EXTI_LINE_41
01117   * @retval State of bit (1 or 0).
01118   */
01119 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine)
01120 {
01121   return ((READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
01122 }
01123
01124 /**
01125   * @}
01126   */
01127
01128 /** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
01129   * @{
01130   */
01131
01132 /**
01133   * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
01134   * @note The configurable wakeup lines are edge-triggered. No glitch must be
01135   *       generated on these lines. If a falling edge on a configurable interrupt
01136   *       line occurs during a write operation in the EXTI_FTSR register, the
01137   *       pending bit is not set.
01138   *       Rising and falling edge triggers can be set for
01139   *       the same interrupt line. In this case, both generate a trigger
01140   *       condition.
01141   * @rmtoll FTSR1        FTx           LL_EXTI_EnableFallingTrig_0_31
01142   * @param  ExtiLine This parameter can be a combination of the following values:
01143   *         @arg @ref LL_EXTI_LINE_0
01144   *         @arg @ref LL_EXTI_LINE_1
01145   *         @arg @ref LL_EXTI_LINE_2
01146   *         @arg @ref LL_EXTI_LINE_3
01147   *         @arg @ref LL_EXTI_LINE_4
01148   *         @arg @ref LL_EXTI_LINE_5
01149   *         @arg @ref LL_EXTI_LINE_6
01150   *         @arg @ref LL_EXTI_LINE_7
01151   *         @arg @ref LL_EXTI_LINE_8
01152   *         @arg @ref LL_EXTI_LINE_9
01153   *         @arg @ref LL_EXTI_LINE_10
01154   *         @arg @ref LL_EXTI_LINE_11
01155   *         @arg @ref LL_EXTI_LINE_12
01156   *         @arg @ref LL_EXTI_LINE_13
01157   *         @arg @ref LL_EXTI_LINE_14
01158   *         @arg @ref LL_EXTI_LINE_15
01159   *         @arg @ref LL_EXTI_LINE_16
01160   *         @arg @ref LL_EXTI_LINE_17
01161   *         @arg @ref LL_EXTI_LINE_18
01162   *         @arg @ref LL_EXTI_LINE_19
01163   *         @arg @ref LL_EXTI_LINE_20
01164   *         @arg @ref LL_EXTI_LINE_21
01165   *         @arg @ref LL_EXTI_LINE_31
01166   * @note   Please check each device line mapping for EXTI Line availability
01167   * @retval None
01168   */
01169 __STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
01170 {
01171   SET_BIT(EXTI->FTSR1, ExtiLine);
01172 }
01173
01174 /**
01175   * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
01176   * @note The configurable wakeup lines are edge-triggered. No glitch must be
01177   *       generated on these lines. If a Falling edge on a configurable interrupt
01178   *       line occurs during a write operation in the EXTI_FTSR register, the
01179   *       pending bit is not set.
01180   *       Rising and falling edge triggers can be set for
01181   *       the same interrupt line. In this case, both generate a trigger
01182   *       condition.
01183   * @rmtoll FTSR2        FTx           LL_EXTI_EnableFallingTrig_32_63
01184   * @param  ExtiLine This parameter can be a combination of the following values:
01185   *         @arg @ref LL_EXTI_LINE_33
01186   *         @arg @ref LL_EXTI_LINE_40
01187   *         @arg @ref LL_EXTI_LINE_41
01188   * @retval None
01189   */
01190 __STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine)
01191 {
01192   SET_BIT(EXTI->FTSR2, ExtiLine);
01193 }
01194
01195 /**
01196   * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
01197   * @note The configurable wakeup lines are edge-triggered. No glitch must be
01198   *       generated on these lines. If a Falling edge on a configurable interrupt
01199   *       line occurs during a write operation in the EXTI_FTSR register, the
01200   *       pending bit is not set.
01201   *       Rising and falling edge triggers can be set for the same interrupt line.
01202   *       In this case, both generate a trigger condition.
01203   * @rmtoll FTSR1        FTx           LL_EXTI_DisableFallingTrig_0_31
01204   * @param  ExtiLine This parameter can be a combination of the following values:
01205   *         @arg @ref LL_EXTI_LINE_0
01206   *         @arg @ref LL_EXTI_LINE_1
01207   *         @arg @ref LL_EXTI_LINE_2
01208   *         @arg @ref LL_EXTI_LINE_3
01209   *         @arg @ref LL_EXTI_LINE_4
01210   *         @arg @ref LL_EXTI_LINE_5
01211   *         @arg @ref LL_EXTI_LINE_6
01212   *         @arg @ref LL_EXTI_LINE_7
01213   *         @arg @ref LL_EXTI_LINE_8
01214   *         @arg @ref LL_EXTI_LINE_9
01215   *         @arg @ref LL_EXTI_LINE_10
01216   *         @arg @ref LL_EXTI_LINE_11
01217   *         @arg @ref LL_EXTI_LINE_12
01218   *         @arg @ref LL_EXTI_LINE_13
01219   *         @arg @ref LL_EXTI_LINE_14
01220   *         @arg @ref LL_EXTI_LINE_15
01221   *         @arg @ref LL_EXTI_LINE_16
01222   *         @arg @ref LL_EXTI_LINE_17
01223   *         @arg @ref LL_EXTI_LINE_18
01224   *         @arg @ref LL_EXTI_LINE_19
01225   *         @arg @ref LL_EXTI_LINE_20
01226   *         @arg @ref LL_EXTI_LINE_21
01227   *         @arg @ref LL_EXTI_LINE_31
01228   * @note   Please check each device line mapping for EXTI Line availability
01229   * @retval None
01230   */
01231 __STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
01232 {
01233   CLEAR_BIT(EXTI->FTSR1, ExtiLine);
01234 }
01235
01236 /**
01237   * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
01238   * @note The configurable wakeup lines are edge-triggered. No glitch must be
01239   *       generated on these lines. If a Falling edge on a configurable interrupt
01240   *       line occurs during a write operation in the EXTI_FTSR register, the
01241   *       pending bit is not set.
01242   *       Rising and falling edge triggers can be set for the same interrupt line.
01243   *       In this case, both generate a trigger condition.
01244   * @rmtoll FTSR2        FTx           LL_EXTI_DisableFallingTrig_32_63
01245   * @param  ExtiLine This parameter can be a combination of the following values:
01246   *         @arg @ref LL_EXTI_LINE_33
01247   *         @arg @ref LL_EXTI_LINE_40
01248   *         @arg @ref LL_EXTI_LINE_41
01249   * @retval None
01250   */
01251 __STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine)
01252 {
01253   CLEAR_BIT(EXTI->FTSR2, ExtiLine);
01254 }
01255
01256 /**
01257   * @brief  Check if falling edge trigger is enabled for Lines in range 0 to 31
01258   * @rmtoll FTSR1        FTx           LL_EXTI_IsEnabledFallingTrig_0_31
01259   * @param  ExtiLine This parameter can be a combination of the following values:
01260   *         @arg @ref LL_EXTI_LINE_0
01261   *         @arg @ref LL_EXTI_LINE_1
01262   *         @arg @ref LL_EXTI_LINE_2
01263   *         @arg @ref LL_EXTI_LINE_3
01264   *         @arg @ref LL_EXTI_LINE_4
01265   *         @arg @ref LL_EXTI_LINE_5
01266   *         @arg @ref LL_EXTI_LINE_6
01267   *         @arg @ref LL_EXTI_LINE_7
01268   *         @arg @ref LL_EXTI_LINE_8
01269   *         @arg @ref LL_EXTI_LINE_9
01270   *         @arg @ref LL_EXTI_LINE_10
01271   *         @arg @ref LL_EXTI_LINE_11
01272   *         @arg @ref LL_EXTI_LINE_12
01273   *         @arg @ref LL_EXTI_LINE_13
01274   *         @arg @ref LL_EXTI_LINE_14
01275   *         @arg @ref LL_EXTI_LINE_15
01276   *         @arg @ref LL_EXTI_LINE_16
01277   *         @arg @ref LL_EXTI_LINE_17
01278   *         @arg @ref LL_EXTI_LINE_18
01279   *         @arg @ref LL_EXTI_LINE_19
01280   *         @arg @ref LL_EXTI_LINE_20
01281   *         @arg @ref LL_EXTI_LINE_21
01282   *         @arg @ref LL_EXTI_LINE_31
01283   * @note   Please check each device line mapping for EXTI Line availability
01284   * @retval State of bit (1 or 0).
01285   */
01286 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
01287 {
01288   return ((READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
01289 }
01290
01291 /**
01292   * @brief  Check if falling edge trigger is enabled for Lines in range 32 to 63
01293   * @rmtoll FTSR2        FTx           LL_EXTI_IsEnabledFallingTrig_32_63
01294   * @param  ExtiLine This parameter can be a combination of the following values:
01295   *         @arg @ref LL_EXTI_LINE_33
01296   *         @arg @ref LL_EXTI_LINE_40
01297   *         @arg @ref LL_EXTI_LINE_41
01298   * @retval State of bit (1 or 0).
01299   */
01300 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine)
01301 {
01302   return ((READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
01303 }
01304
01305 /**
01306   * @}
01307   */
01308
01309 /** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
01310   * @{
01311   */
01312
01313 /**
01314   * @brief  Generate a software Interrupt Event for Lines in range 0 to 31
01315   * @note If the interrupt is enabled on this line in the EXTI_IMR1, writing a 1 to
01316   *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR1
01317   *       resulting in an interrupt request generation.
01318   *       This bit is cleared by clearing the corresponding bit in the EXTI_PR1
01319   *       register (by writing a 1 into the bit)
01320   * @rmtoll SWIER1       SWIx          LL_EXTI_GenerateSWI_0_31
01321   * @param  ExtiLine This parameter can be a combination of the following values:
01322   *         @arg @ref LL_EXTI_LINE_0
01323   *         @arg @ref LL_EXTI_LINE_1
01324   *         @arg @ref LL_EXTI_LINE_2
01325   *         @arg @ref LL_EXTI_LINE_3
01326   *         @arg @ref LL_EXTI_LINE_4
01327   *         @arg @ref LL_EXTI_LINE_5
01328   *         @arg @ref LL_EXTI_LINE_6
01329   *         @arg @ref LL_EXTI_LINE_7
01330   *         @arg @ref LL_EXTI_LINE_8
01331   *         @arg @ref LL_EXTI_LINE_9
01332   *         @arg @ref LL_EXTI_LINE_10
01333   *         @arg @ref LL_EXTI_LINE_11
01334   *         @arg @ref LL_EXTI_LINE_12
01335   *         @arg @ref LL_EXTI_LINE_13
01336   *         @arg @ref LL_EXTI_LINE_14
01337   *         @arg @ref LL_EXTI_LINE_15
01338   *         @arg @ref LL_EXTI_LINE_16
01339   *         @arg @ref LL_EXTI_LINE_17
01340   *         @arg @ref LL_EXTI_LINE_18
01341   *         @arg @ref LL_EXTI_LINE_19
01342   *         @arg @ref LL_EXTI_LINE_20
01343   *         @arg @ref LL_EXTI_LINE_21
01344   *         @arg @ref LL_EXTI_LINE_31
01345   * @note   Please check each device line mapping for EXTI Line availability
01346   * @retval None
01347   */
01348 __STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
01349 {
01350   SET_BIT(EXTI->SWIER1, ExtiLine);
01351 }
01352
01353 /**
01354   * @brief  Generate a software Interrupt Event for Lines in range 32 to 63
01355   * @note If the interrupt is enabled on this line inthe EXTI_IMR2, writing a 1 to
01356   *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2
01357   *       resulting in an interrupt request generation.
01358   *       This bit is cleared by clearing the corresponding bit in the EXTI_PR2
01359   *       register (by writing a 1 into the bit)
01360   * @rmtoll SWIER2       SWIx          LL_EXTI_GenerateSWI_32_63
01361   * @param  ExtiLine This parameter can be a combination of the following values:
01362   *         @arg @ref LL_EXTI_LINE_33
01363   *         @arg @ref LL_EXTI_LINE_40
01364   *         @arg @ref LL_EXTI_LINE_41
01365   * @retval None
01366   */
01367 __STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine)
01368 {
01369   SET_BIT(EXTI->SWIER2, ExtiLine);
01370 }
01371
01372 /**
01373   * @}
01374   */
01375
01376 /** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
01377   * @{
01378   */
01379
01380 /**
01381   * @brief  Check if the ExtLine Flag is set or not for Lines in range 0 to 31
01382   * @note This bit is set when the selected edge event arrives on the interrupt
01383   *       line. This bit is cleared by writing a 1 to the bit.
01384   * @rmtoll PR1          PIFx           LL_EXTI_IsActiveFlag_0_31
01385   * @param  ExtiLine This parameter can be a combination of the following values:
01386   *         @arg @ref LL_EXTI_LINE_0
01387   *         @arg @ref LL_EXTI_LINE_1
01388   *         @arg @ref LL_EXTI_LINE_2
01389   *         @arg @ref LL_EXTI_LINE_3
01390   *         @arg @ref LL_EXTI_LINE_4
01391   *         @arg @ref LL_EXTI_LINE_5
01392   *         @arg @ref LL_EXTI_LINE_6
01393   *         @arg @ref LL_EXTI_LINE_7
01394   *         @arg @ref LL_EXTI_LINE_8
01395   *         @arg @ref LL_EXTI_LINE_9
01396   *         @arg @ref LL_EXTI_LINE_10
01397   *         @arg @ref LL_EXTI_LINE_11
01398   *         @arg @ref LL_EXTI_LINE_12
01399   *         @arg @ref LL_EXTI_LINE_13
01400   *         @arg @ref LL_EXTI_LINE_14
01401   *         @arg @ref LL_EXTI_LINE_15
01402   *         @arg @ref LL_EXTI_LINE_16
01403   *         @arg @ref LL_EXTI_LINE_17
01404   *         @arg @ref LL_EXTI_LINE_18
01405   *         @arg @ref LL_EXTI_LINE_19
01406   *         @arg @ref LL_EXTI_LINE_20
01407   *         @arg @ref LL_EXTI_LINE_21
01408   *         @arg @ref LL_EXTI_LINE_31
01409   * @retval State of bit (1 or 0).
01410   */
01411 __STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
01412 {
01413   return ((READ_BIT(EXTI->PR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
01414 }
01415
01416 /**
01417   * @brief  Check if the ExtLine Flag is set or not for  Lines in range 32 to 63
01418   * @note This bit is set when the selected edge event arrives on the interrupt
01419   *       line. This bit is cleared by writing a 1 to the bit.
01420   * @rmtoll PR2          PIFx           LL_EXTI_IsActiveFlag_32_63
01421   * @param  ExtiLine This parameter can be a combination of the following values:
01422   *         @arg @ref LL_EXTI_LINE_33
01423   *         @arg @ref LL_EXTI_LINE_40
01424   *         @arg @ref LL_EXTI_LINE_41
01425   * @retval State of bit (1 or 0).
01426   */
01427 __STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine)
01428 {
01429   return ((READ_BIT(EXTI->PR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
01430 }
01431
01432 /**
01433   * @brief  Read ExtLine Combination Flag for Lines in range 0 to 31
01434   * @note This bit is set when the selected edge event arrives on the interrupt
01435   *       line. This bit is cleared by writing a 1 to the bit.
01436   * @rmtoll PR1          PIFx           LL_EXTI_ReadFlag_0_31
01437   * @param  ExtiLine This parameter can be a combination of the following values:
01438   *         @arg @ref LL_EXTI_LINE_0
01439   *         @arg @ref LL_EXTI_LINE_1
01440   *         @arg @ref LL_EXTI_LINE_2
01441   *         @arg @ref LL_EXTI_LINE_3
01442   *         @arg @ref LL_EXTI_LINE_4
01443   *         @arg @ref LL_EXTI_LINE_5
01444   *         @arg @ref LL_EXTI_LINE_6
01445   *         @arg @ref LL_EXTI_LINE_7
01446   *         @arg @ref LL_EXTI_LINE_8
01447   *         @arg @ref LL_EXTI_LINE_9
01448   *         @arg @ref LL_EXTI_LINE_10
01449   *         @arg @ref LL_EXTI_LINE_11
01450   *         @arg @ref LL_EXTI_LINE_12
01451   *         @arg @ref LL_EXTI_LINE_13
01452   *         @arg @ref LL_EXTI_LINE_14
01453   *         @arg @ref LL_EXTI_LINE_15
01454   *         @arg @ref LL_EXTI_LINE_16
01455   *         @arg @ref LL_EXTI_LINE_17
01456   *         @arg @ref LL_EXTI_LINE_18
01457   *         @arg @ref LL_EXTI_LINE_19
01458   *         @arg @ref LL_EXTI_LINE_20
01459   *         @arg @ref LL_EXTI_LINE_21
01460   *         @arg @ref LL_EXTI_LINE_31
01461   * @retval @note This bit is set when the selected edge event arrives on the interrupt
01462   */
01463 __STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
01464 {
01465   return (uint32_t)(READ_BIT(EXTI->PR1, ExtiLine));
01466 }
01467
01468 /**
01469   * @brief  Read ExtLine Combination Flag for  Lines in range 32 to 63
01470   * @note This bit is set when the selected edge event arrives on the interrupt
01471   *       line. This bit is cleared by writing a 1 to the bit.
01472   * @rmtoll PR2          PIFx           LL_EXTI_ReadFlag_32_63
01473   * @param  ExtiLine This parameter can be a combination of the following values:
01474   *         @arg @ref LL_EXTI_LINE_33
01475   *         @arg @ref LL_EXTI_LINE_40
01476   *         @arg @ref LL_EXTI_LINE_41
01477   * @retval @note This bit is set when the selected edge event arrives on the interrupt
01478   */
01479 __STATIC_INLINE uint32_t LL_EXTI_ReadFlag_32_63(uint32_t ExtiLine)
01480 {
01481   return (uint32_t)(READ_BIT(EXTI->PR2, ExtiLine));
01482 }
01483
01484 /**
01485   * @brief  Clear ExtLine Flags for Lines in range 0 to 31
01486   * @note This bit is set when the selected edge event arrives on the interrupt
01487   *       line. This bit is cleared by writing a 1 to the bit.
01488   * @rmtoll PR1          PIFx           LL_EXTI_ClearFlag_0_31
01489   * @param  ExtiLine This parameter can be a combination of the following values:
01490   *         @arg @ref LL_EXTI_LINE_0
01491   *         @arg @ref LL_EXTI_LINE_1
01492   *         @arg @ref LL_EXTI_LINE_2
01493   *         @arg @ref LL_EXTI_LINE_3
01494   *         @arg @ref LL_EXTI_LINE_4
01495   *         @arg @ref LL_EXTI_LINE_5
01496   *         @arg @ref LL_EXTI_LINE_6
01497   *         @arg @ref LL_EXTI_LINE_7
01498   *         @arg @ref LL_EXTI_LINE_8
01499   *         @arg @ref LL_EXTI_LINE_9
01500   *         @arg @ref LL_EXTI_LINE_10
01501   *         @arg @ref LL_EXTI_LINE_11
01502   *         @arg @ref LL_EXTI_LINE_12
01503   *         @arg @ref LL_EXTI_LINE_13
01504   *         @arg @ref LL_EXTI_LINE_14
01505   *         @arg @ref LL_EXTI_LINE_15
01506   *         @arg @ref LL_EXTI_LINE_16
01507   *         @arg @ref LL_EXTI_LINE_17
01508   *         @arg @ref LL_EXTI_LINE_18
01509   *         @arg @ref LL_EXTI_LINE_19
01510   *         @arg @ref LL_EXTI_LINE_20
01511   *         @arg @ref LL_EXTI_LINE_21
01512   *         @arg @ref LL_EXTI_LINE_31
01513   * @retval None
01514   */
01515 __STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
01516 {
01517   WRITE_REG(EXTI->PR1, ExtiLine);
01518 }
01519
01520 /**
01521   * @brief  Clear ExtLine Flags for Lines in range 32 to 63
01522   * @note This bit is set when the selected edge event arrives on the interrupt
01523   *       line. This bit is cleared by writing a 1 to the bit.
01524   * @rmtoll PR2          PIFx           LL_EXTI_ClearFlag_32_63
01525   * @param  ExtiLine This parameter can be a combination of the following values:
01526   *         @arg @ref LL_EXTI_LINE_33
01527   *         @arg @ref LL_EXTI_LINE_40
01528   *         @arg @ref LL_EXTI_LINE_41
01529   * @retval None
01530   */
01531 __STATIC_INLINE void LL_EXTI_ClearFlag_32_63(uint32_t ExtiLine)
01532 {
01533   WRITE_REG(EXTI->PR2, ExtiLine);
01534 }
01535
01536 /**
01537   * @}
01538   */
01539
01540 #if defined(USE_FULL_LL_DRIVER)
01541 /** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
01542   * @{
01543   */
01544
01545 ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
01546 ErrorStatus LL_EXTI_DeInit(void);
01547 void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
01548
01549
01550 /**
01551   * @}
01552   */
01553 #endif /* USE_FULL_LL_DRIVER */
01554
01555 /**
01556   * @}
01557   */
01558
01559 /**
01560   * @}
01561   */
01562
01563 #endif /* EXTI */
01564
01565 /**
01566   * @}
01567   */
01568
01569 #ifdef __cplusplus
01570 }
01571 #endif
01572
01573 #endif /* STM32WBxx_LL_EXTI_H */
01574
01575 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_gpio.c Source File

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stm32wbxx_ll_gpio.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_gpio.c
00004   * @author  MCD Application Team
00005   * @brief   GPIO LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32wbxx_ll_gpio.h"
00023 #include "stm32wbxx_ll_bus.h"
00024 #ifdef  USE_FULL_ASSERT
00025 #include "stm32_assert.h"
00026 #else
00027 #define assert_param(expr) ((void)0U)
00028 #endif
00029
00030 /** @addtogroup STM32WBxx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOH)
00035
00036 /** @addtogroup GPIO_LL
00037   * @{
00038   */
00039 /** MISRA C:2012 deviation rule has been granted for following rules:
00040   * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of
00041   * range of the shift operator in following API :
00042   * LL_GPIO_Init
00043   */
00044
00045 /* Private types -------------------------------------------------------------*/
00046 /* Private variables ---------------------------------------------------------*/
00047 /* Private constants ---------------------------------------------------------*/
00048 /* Private macros ------------------------------------------------------------*/
00049 /** @addtogroup GPIO_LL_Private_Macros
00050   * @{
00051   */
00052 #define IS_LL_GPIO_PIN(__VALUE__)          (((0x00u) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
00053
00054 #define IS_LL_GPIO_MODE(__VALUE__)         (((__VALUE__) == LL_GPIO_MODE_INPUT)     ||\
00055                                             ((__VALUE__) == LL_GPIO_MODE_OUTPUT)    ||\
00056                                             ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\
00057                                             ((__VALUE__) == LL_GPIO_MODE_ANALOG))
00058
00059 #define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__)  (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL)  ||\
00060                                             ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))
00061
00062 #define IS_LL_GPIO_SPEED(__VALUE__)        (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW)       ||\
00063                                             ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM)    ||\
00064                                             ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH)      ||\
00065                                             ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH))
00066
00067 #define IS_LL_GPIO_PULL(__VALUE__)         (((__VALUE__) == LL_GPIO_PULL_NO)   ||\
00068                                             ((__VALUE__) == LL_GPIO_PULL_UP)   ||\
00069                                             ((__VALUE__) == LL_GPIO_PULL_DOWN))
00070
00071 #define IS_LL_GPIO_ALTERNATE(__VALUE__)    (((__VALUE__) == LL_GPIO_AF_0  )   ||\
00072                                             ((__VALUE__) == LL_GPIO_AF_1  )   ||\
00073                                             ((__VALUE__) == LL_GPIO_AF_2  )   ||\
00074                                             ((__VALUE__) == LL_GPIO_AF_3  )   ||\
00075                                             ((__VALUE__) == LL_GPIO_AF_4  )   ||\
00076                                             ((__VALUE__) == LL_GPIO_AF_5  )   ||\
00077                                             ((__VALUE__) == LL_GPIO_AF_6  )   ||\
00078                                             ((__VALUE__) == LL_GPIO_AF_7  )   ||\
00079                                             ((__VALUE__) == LL_GPIO_AF_8  )   ||\
00080                                             ((__VALUE__) == LL_GPIO_AF_9  )   ||\
00081                                             ((__VALUE__) == LL_GPIO_AF_10 )   ||\
00082                                             ((__VALUE__) == LL_GPIO_AF_11 )   ||\
00083                                             ((__VALUE__) == LL_GPIO_AF_12 )   ||\
00084                                             ((__VALUE__) == LL_GPIO_AF_13 )   ||\
00085                                             ((__VALUE__) == LL_GPIO_AF_14 )   ||\
00086                                             ((__VALUE__) == LL_GPIO_AF_15 ))
00087 /**
00088   * @}
00089   */
00090
00091 /* Private function prototypes -----------------------------------------------*/
00092
00093 /* Exported functions --------------------------------------------------------*/
00094 /** @addtogroup GPIO_LL_Exported_Functions
00095   * @{
00096   */
00097
00098 /** @addtogroup GPIO_LL_EF_Init
00099   * @{
00100   */
00101
00102 /**
00103   * @brief  De-initialize GPIO registers (Registers restored to their default values).
00104   * @param  GPIOx GPIO Port
00105   * @retval An ErrorStatus enumeration value:
00106   *          - SUCCESS: GPIO registers are de-initialized
00107   *          - ERROR:   Wrong GPIO Port
00108   */
00109 ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
00110 {
00111   ErrorStatus status = SUCCESS;
00112
00113   /* Check the parameters */
00114   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
00115
00116   /* Force and Release reset on clock of GPIOx Port */
00117   if (GPIOx == GPIOA)
00118   {
00119     LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOA);
00120     LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOA);
00121   }
00122   else if (GPIOx == GPIOB)
00123   {
00124     LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOB);
00125     LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOB);
00126   }
00127   else if (GPIOx == GPIOC)
00128   {
00129     LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOC);
00130     LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOC);
00131   }
00132 #if defined(GPIOD)
00133   else if (GPIOx == GPIOD)
00134   {
00135     LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOD);
00136     LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOD);
00137   }
00138 #endif /* GPIOD */
00139 #if defined(GPIOE)
00140   else if (GPIOx == GPIOE)
00141   {
00142     LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOE);
00143     LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOE);
00144   }
00145 #endif /* GPIOE */
00146 #if defined(GPIOH)
00147   else if (GPIOx == GPIOH)
00148   {
00149     LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOH);
00150     LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOH);
00151   }
00152 #endif /* GPIOH */
00153   else
00154   {
00155     status = ERROR;
00156   }
00157
00158   return (status);
00159 }
00160
00161 /**
00162   * @brief  Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
00163   * @param  GPIOx GPIO Port
00164   * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
00165   *         that contains the configuration information for the specified GPIO peripheral.
00166   * @retval An ErrorStatus enumeration value:
00167   *          - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
00168   *          - ERROR:   Not applicable
00169   */
00170 ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
00171 {
00172   uint32_t pinpos;
00173   uint32_t currentpin;
00174
00175   /* Check the parameters */
00176   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
00177   assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));
00178   assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
00179   assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
00180
00181   /* ------------------------- Configure the port pins ---------------- */
00182   /* Initialize  pinpos on first pin set */
00183   pinpos = POSITION_VAL(GPIO_InitStruct->Pin);
00184
00185   /* Configure the port pins */
00186   while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00u)
00187   {
00188     /* Get current io position */
00189     currentpin = (GPIO_InitStruct->Pin) & (0x00000001uL << pinpos);
00190
00191     if (currentpin != 0x00u)
00192     {
00193       /* Pin Mode configuration */
00194       LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
00195
00196       if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
00197       {
00198         /* Check Speed mode parameters */
00199         assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed));
00200
00201         /* Speed mode configuration */
00202         LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
00203       }
00204
00205       /* Pull-up Pull down resistor configuration*/
00206       LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
00207
00208       if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)
00209       {
00210         /* Check Alternate parameter */
00211         assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate));
00212
00213         /* Speed mode configuration */
00214         if (POSITION_VAL(currentpin) < 0x00000008uL)
00215         {
00216           LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate);
00217         }
00218         else
00219         {
00220           LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
00221         }
00222       }
00223     }
00224     pinpos++;
00225   }
00226
00227   if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
00228   {
00229     /* Check Output mode parameters */
00230     assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
00231
00232     /* Output mode configuration*/
00233     LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
00234
00235   }
00236   return (SUCCESS);
00237 }
00238
00239 /**
00240   * @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
00241   * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
00242   *                          whose fields will be set to default values.
00243   * @retval None
00244   */
00245
00246 void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
00247 {
00248   /* Reset GPIO init structure parameters values */
00249   GPIO_InitStruct->Pin        = LL_GPIO_PIN_ALL;
00250   GPIO_InitStruct->Mode       = LL_GPIO_MODE_ANALOG;
00251   GPIO_InitStruct->Speed      = LL_GPIO_SPEED_FREQ_LOW;
00252   GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL;
00253   GPIO_InitStruct->Pull       = LL_GPIO_PULL_NO;
00254   GPIO_InitStruct->Alternate  = LL_GPIO_AF_0;
00255 }
00256
00257 /**
00258   * @}
00259   */
00260
00261 /**
00262   * @}
00263   */
00264
00265 /**
00266   * @}
00267   */
00268
00269 #endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOH) */
00270
00271 /**
00272   * @}
00273   */
00274
00275 #endif /* USE_FULL_LL_DRIVER */
00276
00277 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00278
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_gpio.h Source File

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stm32wbxx_ll_gpio.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_gpio.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of GPIO LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_LL_GPIO_H
00022 #define STM32WBxx_LL_GPIO_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx.h"
00030
00031 /** @addtogroup STM32WBxx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOH)
00036
00037 /** @defgroup GPIO_LL GPIO
00038   * @{
00039   */
00040 /** MISRA C:2012 deviation rule has been granted for following rules:
00041   * Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..]
00042   * which may be out of array bounds [..,UNKNOWN] in following APIs:
00043   * LL_GPIO_GetAFPin_0_7
00044   * LL_GPIO_SetAFPin_0_7
00045   * LL_GPIO_SetAFPin_8_15
00046   * LL_GPIO_GetAFPin_8_15
00047   */
00048
00049 /* Private types -------------------------------------------------------------*/
00050 /* Private variables ---------------------------------------------------------*/
00051 /* Private constants ---------------------------------------------------------*/
00052 /* Private macros ------------------------------------------------------------*/
00053 #if defined(USE_FULL_LL_DRIVER)
00054 /** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
00055   * @{
00056   */
00057
00058 /**
00059   * @}
00060   */
00061 #endif /*USE_FULL_LL_DRIVER*/
00062
00063 /* Exported types ------------------------------------------------------------*/
00064 #if defined(USE_FULL_LL_DRIVER)
00065 /** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
00066   * @{
00067   */
00068
00069 /**
00070   * @brief LL GPIO Init Structure definition
00071   */
00072 typedef struct
00073 {
00074   uint32_t Pin;          /*!< Specifies the GPIO pins to be configured.
00075                               This parameter can be any value of @ref GPIO_LL_EC_PIN */
00076
00077   uint32_t Mode;         /*!< Specifies the operating mode for the selected pins.
00078                               This parameter can be a value of @ref GPIO_LL_EC_MODE.
00079
00080                               GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
00081
00082   uint32_t Speed;        /*!< Specifies the speed for the selected pins.
00083                               This parameter can be a value of @ref GPIO_LL_EC_SPEED.
00084
00085                               GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
00086
00087   uint32_t OutputType;   /*!< Specifies the operating output type for the selected pins.
00088                               This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
00089
00090                               GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
00091
00092   uint32_t Pull;         /*!< Specifies the operating Pull-up/Pull down for the selected pins.
00093                               This parameter can be a value of @ref GPIO_LL_EC_PULL.
00094
00095                               GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
00096
00097   uint32_t Alternate;    /*!< Specifies the Peripheral to be connected to the selected pins.
00098                               This parameter can be a value of @ref GPIO_LL_EC_AF.
00099
00100                               GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/
00101 } LL_GPIO_InitTypeDef;
00102
00103 /**
00104   * @}
00105   */
00106 #endif /* USE_FULL_LL_DRIVER */
00107
00108 /* Exported constants --------------------------------------------------------*/
00109 /** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
00110   * @{
00111   */
00112
00113 /** @defgroup GPIO_LL_EC_PIN PIN
00114   * @{
00115   */
00116 #define LL_GPIO_PIN_0                      GPIO_BSRR_BS0 /*!< Select pin 0 */
00117 #define LL_GPIO_PIN_1                      GPIO_BSRR_BS1 /*!< Select pin 1 */
00118 #define LL_GPIO_PIN_2                      GPIO_BSRR_BS2 /*!< Select pin 2 */
00119 #define LL_GPIO_PIN_3                      GPIO_BSRR_BS3 /*!< Select pin 3 */
00120 #define LL_GPIO_PIN_4                      GPIO_BSRR_BS4 /*!< Select pin 4 */
00121 #define LL_GPIO_PIN_5                      GPIO_BSRR_BS5 /*!< Select pin 5 */
00122 #define LL_GPIO_PIN_6                      GPIO_BSRR_BS6 /*!< Select pin 6 */
00123 #define LL_GPIO_PIN_7                      GPIO_BSRR_BS7 /*!< Select pin 7 */
00124 #define LL_GPIO_PIN_8                      GPIO_BSRR_BS8 /*!< Select pin 8 */
00125 #define LL_GPIO_PIN_9                      GPIO_BSRR_BS9 /*!< Select pin 9 */
00126 #define LL_GPIO_PIN_10                     GPIO_BSRR_BS10 /*!< Select pin 10 */
00127 #define LL_GPIO_PIN_11                     GPIO_BSRR_BS11 /*!< Select pin 11 */
00128 #define LL_GPIO_PIN_12                     GPIO_BSRR_BS12 /*!< Select pin 12 */
00129 #define LL_GPIO_PIN_13                     GPIO_BSRR_BS13 /*!< Select pin 13 */
00130 #define LL_GPIO_PIN_14                     GPIO_BSRR_BS14 /*!< Select pin 14 */
00131 #define LL_GPIO_PIN_15                     GPIO_BSRR_BS15 /*!< Select pin 15 */
00132 #define LL_GPIO_PIN_ALL                    (GPIO_BSRR_BS0 | GPIO_BSRR_BS1  | GPIO_BSRR_BS2  | \
00133                                            GPIO_BSRR_BS3  | GPIO_BSRR_BS4  | GPIO_BSRR_BS5  | \
00134                                            GPIO_BSRR_BS6  | GPIO_BSRR_BS7  | GPIO_BSRR_BS8  | \
00135                                            GPIO_BSRR_BS9  | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \
00136                                            GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \
00137                                            GPIO_BSRR_BS15) /*!< Select all pins */
00138 /**
00139   * @}
00140   */
00141
00142 /** @defgroup GPIO_LL_EC_MODE Mode
00143   * @{
00144   */
00145 #define LL_GPIO_MODE_INPUT                 (0x00000000U) /*!< Select input mode */
00146 #define LL_GPIO_MODE_OUTPUT                GPIO_MODER_MODE0_0  /*!< Select output mode */
00147 #define LL_GPIO_MODE_ALTERNATE             GPIO_MODER_MODE0_1  /*!< Select alternate function mode */
00148 #define LL_GPIO_MODE_ANALOG                GPIO_MODER_MODE0    /*!< Select analog mode */
00149 /**
00150   * @}
00151   */
00152
00153 /** @defgroup GPIO_LL_EC_OUTPUT Output Type
00154   * @{
00155   */
00156 #define LL_GPIO_OUTPUT_PUSHPULL            (0x00000000U) /*!< Select push-pull as output type */
00157 #define LL_GPIO_OUTPUT_OPENDRAIN           GPIO_OTYPER_OT0 /*!< Select open-drain as output type */
00158 /**
00159   * @}
00160   */
00161
00162 /** @defgroup GPIO_LL_EC_SPEED Output Speed
00163   * @{
00164   */
00165 #define LL_GPIO_SPEED_FREQ_LOW             (0x00000000U) /*!< Select I/O low output speed    */
00166 #define LL_GPIO_SPEED_FREQ_MEDIUM          GPIO_OSPEEDR_OSPEED0_0 /*!< Select I/O medium output speed */
00167 #define LL_GPIO_SPEED_FREQ_HIGH            GPIO_OSPEEDR_OSPEED0_1 /*!< Select I/O fast output speed   */
00168 #define LL_GPIO_SPEED_FREQ_VERY_HIGH       GPIO_OSPEEDR_OSPEED0   /*!< Select I/O high output speed   */
00169 /**
00170   * @}
00171   */
00172
00173 /** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
00174   * @{
00175   */
00176 #define LL_GPIO_PULL_NO                    (0x00000000U) /*!< Select I/O no pull */
00177 #define LL_GPIO_PULL_UP                    GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */
00178 #define LL_GPIO_PULL_DOWN                  GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */
00179 /**
00180   * @}
00181   */
00182
00183 /** @defgroup GPIO_LL_EC_AF Alternate Function
00184   * @{
00185   */
00186 #define LL_GPIO_AF_0                       (0x0000000U) /*!< Select alternate function 0 */
00187 #define LL_GPIO_AF_1                       (0x0000001U) /*!< Select alternate function 1 */
00188 #define LL_GPIO_AF_2                       (0x0000002U) /*!< Select alternate function 2 */
00189 #define LL_GPIO_AF_3                       (0x0000003U) /*!< Select alternate function 3 */
00190 #define LL_GPIO_AF_4                       (0x0000004U) /*!< Select alternate function 4 */
00191 #define LL_GPIO_AF_5                       (0x0000005U) /*!< Select alternate function 5 */
00192 #define LL_GPIO_AF_6                       (0x0000006U) /*!< Select alternate function 6 */
00193 #define LL_GPIO_AF_7                       (0x0000007U) /*!< Select alternate function 7 */
00194 #define LL_GPIO_AF_8                       (0x0000008U) /*!< Select alternate function 8 */
00195 #define LL_GPIO_AF_9                       (0x0000009U) /*!< Select alternate function 9 */
00196 #define LL_GPIO_AF_10                      (0x000000AU) /*!< Select alternate function 10 */
00197 #define LL_GPIO_AF_11                      (0x000000BU) /*!< Select alternate function 11 */
00198 #define LL_GPIO_AF_12                      (0x000000CU) /*!< Select alternate function 12 */
00199 #define LL_GPIO_AF_13                      (0x000000DU) /*!< Select alternate function 13 */
00200 #define LL_GPIO_AF_14                      (0x000000EU) /*!< Select alternate function 14 */
00201 #define LL_GPIO_AF_15                      (0x000000FU) /*!< Select alternate function 15 */
00202 /**
00203   * @}
00204   */
00205
00206 /**
00207   * @}
00208   */
00209
00210 /* Exported macro ------------------------------------------------------------*/
00211 /** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
00212   * @{
00213   */
00214
00215 /** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
00216   * @{
00217   */
00218
00219 /**
00220   * @brief  Write a value in GPIO register
00221   * @param  __INSTANCE__ GPIO Instance
00222   * @param  __REG__ Register to be written
00223   * @param  __VALUE__ Value to be written in the register
00224   * @retval None
00225   */
00226 #define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00227
00228 /**
00229   * @brief  Read a value in GPIO register
00230   * @param  __INSTANCE__ GPIO Instance
00231   * @param  __REG__ Register to be read
00232   * @retval Register value
00233   */
00234 #define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00235 /**
00236   * @}
00237   */
00238
00239 /**
00240   * @}
00241   */
00242
00243 /* Exported functions --------------------------------------------------------*/
00244 /** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
00245   * @{
00246   */
00247
00248 /** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
00249   * @{
00250   */
00251
00252 /**
00253   * @brief  Configure gpio mode for a dedicated pin on dedicated port.
00254   * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
00255   * @note   Warning: only one pin can be passed as parameter.
00256   * @rmtoll MODER        MODEy         LL_GPIO_SetPinMode
00257   * @param  GPIOx GPIO Port
00258   * @param  Pin This parameter can be one of the following values:
00259   *         @arg @ref LL_GPIO_PIN_0
00260   *         @arg @ref LL_GPIO_PIN_1
00261   *         @arg @ref LL_GPIO_PIN_2
00262   *         @arg @ref LL_GPIO_PIN_3
00263   *         @arg @ref LL_GPIO_PIN_4
00264   *         @arg @ref LL_GPIO_PIN_5
00265   *         @arg @ref LL_GPIO_PIN_6
00266   *         @arg @ref LL_GPIO_PIN_7
00267   *         @arg @ref LL_GPIO_PIN_8
00268   *         @arg @ref LL_GPIO_PIN_9
00269   *         @arg @ref LL_GPIO_PIN_10
00270   *         @arg @ref LL_GPIO_PIN_11
00271   *         @arg @ref LL_GPIO_PIN_12
00272   *         @arg @ref LL_GPIO_PIN_13
00273   *         @arg @ref LL_GPIO_PIN_14
00274   *         @arg @ref LL_GPIO_PIN_15
00275   * @param  Mode This parameter can be one of the following values:
00276   *         @arg @ref LL_GPIO_MODE_INPUT
00277   *         @arg @ref LL_GPIO_MODE_OUTPUT
00278   *         @arg @ref LL_GPIO_MODE_ALTERNATE
00279   *         @arg @ref LL_GPIO_MODE_ANALOG
00280   * @retval None
00281   */
00282 __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
00283 {
00284   MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));
00285 }
00286
00287 /**
00288   * @brief  Return gpio mode for a dedicated pin on dedicated port.
00289   * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
00290   * @note   Warning: only one pin can be passed as parameter.
00291   * @rmtoll MODER        MODEy         LL_GPIO_GetPinMode
00292   * @param  GPIOx GPIO Port
00293   * @param  Pin This parameter can be one of the following values:
00294   *         @arg @ref LL_GPIO_PIN_0
00295   *         @arg @ref LL_GPIO_PIN_1
00296   *         @arg @ref LL_GPIO_PIN_2
00297   *         @arg @ref LL_GPIO_PIN_3
00298   *         @arg @ref LL_GPIO_PIN_4
00299   *         @arg @ref LL_GPIO_PIN_5
00300   *         @arg @ref LL_GPIO_PIN_6
00301   *         @arg @ref LL_GPIO_PIN_7
00302   *         @arg @ref LL_GPIO_PIN_8
00303   *         @arg @ref LL_GPIO_PIN_9
00304   *         @arg @ref LL_GPIO_PIN_10
00305   *         @arg @ref LL_GPIO_PIN_11
00306   *         @arg @ref LL_GPIO_PIN_12
00307   *         @arg @ref LL_GPIO_PIN_13
00308   *         @arg @ref LL_GPIO_PIN_14
00309   *         @arg @ref LL_GPIO_PIN_15
00310   * @retval Returned value can be one of the following values:
00311   *         @arg @ref LL_GPIO_MODE_INPUT
00312   *         @arg @ref LL_GPIO_MODE_OUTPUT
00313   *         @arg @ref LL_GPIO_MODE_ALTERNATE
00314   *         @arg @ref LL_GPIO_MODE_ANALOG
00315   */
00316 __STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
00317 {
00318   return (uint32_t)(READ_BIT(GPIOx->MODER,
00319                              (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
00320 }
00321
00322 /**
00323   * @brief  Configure gpio output type for several pins on dedicated port.
00324   * @note   Output type as to be set when gpio pin is in output or
00325   *         alternate modes. Possible type are Push-pull or Open-drain.
00326   * @rmtoll OTYPER       OTy           LL_GPIO_SetPinOutputType
00327   * @param  GPIOx GPIO Port
00328   * @param  PinMask This parameter can be a combination of the following values:
00329   *         @arg @ref LL_GPIO_PIN_0
00330   *         @arg @ref LL_GPIO_PIN_1
00331   *         @arg @ref LL_GPIO_PIN_2
00332   *         @arg @ref LL_GPIO_PIN_3
00333   *         @arg @ref LL_GPIO_PIN_4
00334   *         @arg @ref LL_GPIO_PIN_5
00335   *         @arg @ref LL_GPIO_PIN_6
00336   *         @arg @ref LL_GPIO_PIN_7
00337   *         @arg @ref LL_GPIO_PIN_8
00338   *         @arg @ref LL_GPIO_PIN_9
00339   *         @arg @ref LL_GPIO_PIN_10
00340   *         @arg @ref LL_GPIO_PIN_11
00341   *         @arg @ref LL_GPIO_PIN_12
00342   *         @arg @ref LL_GPIO_PIN_13
00343   *         @arg @ref LL_GPIO_PIN_14
00344   *         @arg @ref LL_GPIO_PIN_15
00345   *         @arg @ref LL_GPIO_PIN_ALL
00346   * @param  OutputType This parameter can be one of the following values:
00347   *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
00348   *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
00349   * @retval None
00350   */
00351 __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
00352 {
00353   MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
00354 }
00355
00356 /**
00357   * @brief  Return gpio output type for several pins on dedicated port.
00358   * @note   Output type as to be set when gpio pin is in output or
00359   *         alternate modes. Possible type are Push-pull or Open-drain.
00360   * @note   Warning: only one pin can be passed as parameter.
00361   * @rmtoll OTYPER       OTy           LL_GPIO_GetPinOutputType
00362   * @param  GPIOx GPIO Port
00363   * @param  Pin This parameter can be one of the following values:
00364   *         @arg @ref LL_GPIO_PIN_0
00365   *         @arg @ref LL_GPIO_PIN_1
00366   *         @arg @ref LL_GPIO_PIN_2
00367   *         @arg @ref LL_GPIO_PIN_3
00368   *         @arg @ref LL_GPIO_PIN_4
00369   *         @arg @ref LL_GPIO_PIN_5
00370   *         @arg @ref LL_GPIO_PIN_6
00371   *         @arg @ref LL_GPIO_PIN_7
00372   *         @arg @ref LL_GPIO_PIN_8
00373   *         @arg @ref LL_GPIO_PIN_9
00374   *         @arg @ref LL_GPIO_PIN_10
00375   *         @arg @ref LL_GPIO_PIN_11
00376   *         @arg @ref LL_GPIO_PIN_12
00377   *         @arg @ref LL_GPIO_PIN_13
00378   *         @arg @ref LL_GPIO_PIN_14
00379   *         @arg @ref LL_GPIO_PIN_15
00380   *         @arg @ref LL_GPIO_PIN_ALL
00381   * @retval Returned value can be one of the following values:
00382   *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
00383   *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
00384   */
00385 __STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
00386 {
00387   return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin));
00388 }
00389
00390 /**
00391   * @brief  Configure gpio speed for a dedicated pin on dedicated port.
00392   * @note   I/O speed can be Low, Medium, Fast or High speed.
00393   * @note   Warning: only one pin can be passed as parameter.
00394   * @note   Refer to datasheet for frequency specifications and the power
00395   *         supply and load conditions for each speed.
00396   * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_SetPinSpeed
00397   * @param  GPIOx GPIO Port
00398   * @param  Pin This parameter can be one of the following values:
00399   *         @arg @ref LL_GPIO_PIN_0
00400   *         @arg @ref LL_GPIO_PIN_1
00401   *         @arg @ref LL_GPIO_PIN_2
00402   *         @arg @ref LL_GPIO_PIN_3
00403   *         @arg @ref LL_GPIO_PIN_4
00404   *         @arg @ref LL_GPIO_PIN_5
00405   *         @arg @ref LL_GPIO_PIN_6
00406   *         @arg @ref LL_GPIO_PIN_7
00407   *         @arg @ref LL_GPIO_PIN_8
00408   *         @arg @ref LL_GPIO_PIN_9
00409   *         @arg @ref LL_GPIO_PIN_10
00410   *         @arg @ref LL_GPIO_PIN_11
00411   *         @arg @ref LL_GPIO_PIN_12
00412   *         @arg @ref LL_GPIO_PIN_13
00413   *         @arg @ref LL_GPIO_PIN_14
00414   *         @arg @ref LL_GPIO_PIN_15
00415   * @param  Speed This parameter can be one of the following values:
00416   *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
00417   *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
00418   *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
00419   *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
00420   * @retval None
00421   */
00422 __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t  Speed)
00423 {
00424   MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * 2U)),
00425              (Speed << (POSITION_VAL(Pin) * 2U)));
00426 }
00427
00428 /**
00429   * @brief  Return gpio speed for a dedicated pin on dedicated port.
00430   * @note   I/O speed can be Low, Medium, Fast or High speed.
00431   * @note   Warning: only one pin can be passed as parameter.
00432   * @note   Refer to datasheet for frequency specifications and the power
00433   *         supply and load conditions for each speed.
00434   * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_GetPinSpeed
00435   * @param  GPIOx GPIO Port
00436   * @param  Pin This parameter can be one of the following values:
00437   *         @arg @ref LL_GPIO_PIN_0
00438   *         @arg @ref LL_GPIO_PIN_1
00439   *         @arg @ref LL_GPIO_PIN_2
00440   *         @arg @ref LL_GPIO_PIN_3
00441   *         @arg @ref LL_GPIO_PIN_4
00442   *         @arg @ref LL_GPIO_PIN_5
00443   *         @arg @ref LL_GPIO_PIN_6
00444   *         @arg @ref LL_GPIO_PIN_7
00445   *         @arg @ref LL_GPIO_PIN_8
00446   *         @arg @ref LL_GPIO_PIN_9
00447   *         @arg @ref LL_GPIO_PIN_10
00448   *         @arg @ref LL_GPIO_PIN_11
00449   *         @arg @ref LL_GPIO_PIN_12
00450   *         @arg @ref LL_GPIO_PIN_13
00451   *         @arg @ref LL_GPIO_PIN_14
00452   *         @arg @ref LL_GPIO_PIN_15
00453   * @retval Returned value can be one of the following values:
00454   *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
00455   *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
00456   *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
00457   *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
00458   */
00459 __STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
00460 {
00461   return (uint32_t)(READ_BIT(GPIOx->OSPEEDR,
00462                              (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
00463 }
00464
00465 /**
00466   * @brief  Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
00467   * @note   Warning: only one pin can be passed as parameter.
00468   * @rmtoll PUPDR        PUPDy         LL_GPIO_SetPinPull
00469   * @param  GPIOx GPIO Port
00470   * @param  Pin This parameter can be one of the following values:
00471   *         @arg @ref LL_GPIO_PIN_0
00472   *         @arg @ref LL_GPIO_PIN_1
00473   *         @arg @ref LL_GPIO_PIN_2
00474   *         @arg @ref LL_GPIO_PIN_3
00475   *         @arg @ref LL_GPIO_PIN_4
00476   *         @arg @ref LL_GPIO_PIN_5
00477   *         @arg @ref LL_GPIO_PIN_6
00478   *         @arg @ref LL_GPIO_PIN_7
00479   *         @arg @ref LL_GPIO_PIN_8
00480   *         @arg @ref LL_GPIO_PIN_9
00481   *         @arg @ref LL_GPIO_PIN_10
00482   *         @arg @ref LL_GPIO_PIN_11
00483   *         @arg @ref LL_GPIO_PIN_12
00484   *         @arg @ref LL_GPIO_PIN_13
00485   *         @arg @ref LL_GPIO_PIN_14
00486   *         @arg @ref LL_GPIO_PIN_15
00487   * @param  Pull This parameter can be one of the following values:
00488   *         @arg @ref LL_GPIO_PULL_NO
00489   *         @arg @ref LL_GPIO_PULL_UP
00490   *         @arg @ref LL_GPIO_PULL_DOWN
00491   * @retval None
00492   */
00493 __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
00494 {
00495   MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U)));
00496 }
00497
00498 /**
00499   * @brief  Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
00500   * @note   Warning: only one pin can be passed as parameter.
00501   * @rmtoll PUPDR        PUPDy         LL_GPIO_GetPinPull
00502   * @param  GPIOx GPIO Port
00503   * @param  Pin This parameter can be one of the following values:
00504   *         @arg @ref LL_GPIO_PIN_0
00505   *         @arg @ref LL_GPIO_PIN_1
00506   *         @arg @ref LL_GPIO_PIN_2
00507   *         @arg @ref LL_GPIO_PIN_3
00508   *         @arg @ref LL_GPIO_PIN_4
00509   *         @arg @ref LL_GPIO_PIN_5
00510   *         @arg @ref LL_GPIO_PIN_6
00511   *         @arg @ref LL_GPIO_PIN_7
00512   *         @arg @ref LL_GPIO_PIN_8
00513   *         @arg @ref LL_GPIO_PIN_9
00514   *         @arg @ref LL_GPIO_PIN_10
00515   *         @arg @ref LL_GPIO_PIN_11
00516   *         @arg @ref LL_GPIO_PIN_12
00517   *         @arg @ref LL_GPIO_PIN_13
00518   *         @arg @ref LL_GPIO_PIN_14
00519   *         @arg @ref LL_GPIO_PIN_15
00520   * @retval Returned value can be one of the following values:
00521   *         @arg @ref LL_GPIO_PULL_NO
00522   *         @arg @ref LL_GPIO_PULL_UP
00523   *         @arg @ref LL_GPIO_PULL_DOWN
00524   */
00525 __STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
00526 {
00527   return (uint32_t)(READ_BIT(GPIOx->PUPDR,
00528                              (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
00529 }
00530
00531 /**
00532   * @brief  Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
00533   * @note   Possible values are from AF0 to AF15 depending on target.
00534   * @note   Warning: only one pin can be passed as parameter.
00535   * @rmtoll AFRL         AFSELy        LL_GPIO_SetAFPin_0_7
00536   * @param  GPIOx GPIO Port
00537   * @param  Pin This parameter can be one of the following values:
00538   *         @arg @ref LL_GPIO_PIN_0
00539   *         @arg @ref LL_GPIO_PIN_1
00540   *         @arg @ref LL_GPIO_PIN_2
00541   *         @arg @ref LL_GPIO_PIN_3
00542   *         @arg @ref LL_GPIO_PIN_4
00543   *         @arg @ref LL_GPIO_PIN_5
00544   *         @arg @ref LL_GPIO_PIN_6
00545   *         @arg @ref LL_GPIO_PIN_7
00546   * @param  Alternate This parameter can be one of the following values:
00547   *         @arg @ref LL_GPIO_AF_0
00548   *         @arg @ref LL_GPIO_AF_1
00549   *         @arg @ref LL_GPIO_AF_2
00550   *         @arg @ref LL_GPIO_AF_3
00551   *         @arg @ref LL_GPIO_AF_4
00552   *         @arg @ref LL_GPIO_AF_5
00553   *         @arg @ref LL_GPIO_AF_6
00554   *         @arg @ref LL_GPIO_AF_7
00555   *         @arg @ref LL_GPIO_AF_8
00556   *         @arg @ref LL_GPIO_AF_9
00557   *         @arg @ref LL_GPIO_AF_10
00558   *         @arg @ref LL_GPIO_AF_11
00559   *         @arg @ref LL_GPIO_AF_12
00560   *         @arg @ref LL_GPIO_AF_13
00561   *         @arg @ref LL_GPIO_AF_14
00562   *         @arg @ref LL_GPIO_AF_15
00563   * @retval None
00564   */
00565 __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
00566 {
00567   MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U)),
00568              (Alternate << (POSITION_VAL(Pin) * 4U)));
00569 }
00570
00571 /**
00572   * @brief  Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
00573   * @rmtoll AFRL         AFSELy        LL_GPIO_GetAFPin_0_7
00574   * @param  GPIOx GPIO Port
00575   * @param  Pin This parameter can be one of the following values:
00576   *         @arg @ref LL_GPIO_PIN_0
00577   *         @arg @ref LL_GPIO_PIN_1
00578   *         @arg @ref LL_GPIO_PIN_2
00579   *         @arg @ref LL_GPIO_PIN_3
00580   *         @arg @ref LL_GPIO_PIN_4
00581   *         @arg @ref LL_GPIO_PIN_5
00582   *         @arg @ref LL_GPIO_PIN_6
00583   *         @arg @ref LL_GPIO_PIN_7
00584   * @retval Returned value can be one of the following values:
00585   *         @arg @ref LL_GPIO_AF_0
00586   *         @arg @ref LL_GPIO_AF_1
00587   *         @arg @ref LL_GPIO_AF_2
00588   *         @arg @ref LL_GPIO_AF_3
00589   *         @arg @ref LL_GPIO_AF_4
00590   *         @arg @ref LL_GPIO_AF_5
00591   *         @arg @ref LL_GPIO_AF_6
00592   *         @arg @ref LL_GPIO_AF_7
00593   *         @arg @ref LL_GPIO_AF_8
00594   *         @arg @ref LL_GPIO_AF_9
00595   *         @arg @ref LL_GPIO_AF_10
00596   *         @arg @ref LL_GPIO_AF_11
00597   *         @arg @ref LL_GPIO_AF_12
00598   *         @arg @ref LL_GPIO_AF_13
00599   *         @arg @ref LL_GPIO_AF_14
00600   *         @arg @ref LL_GPIO_AF_15
00601   */
00602 __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
00603 {
00604   return (uint32_t)(READ_BIT(GPIOx->AFR[0],
00605                              (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
00606 }
00607
00608 /**
00609   * @brief  Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
00610   * @note   Possible values are from AF0 to AF15 depending on target.
00611   * @note   Warning: only one pin can be passed as parameter.
00612   * @rmtoll AFRH         AFSELy        LL_GPIO_SetAFPin_8_15
00613   * @param  GPIOx GPIO Port
00614   * @param  Pin This parameter can be one of the following values:
00615   *         @arg @ref LL_GPIO_PIN_8
00616   *         @arg @ref LL_GPIO_PIN_9
00617   *         @arg @ref LL_GPIO_PIN_10
00618   *         @arg @ref LL_GPIO_PIN_11
00619   *         @arg @ref LL_GPIO_PIN_12
00620   *         @arg @ref LL_GPIO_PIN_13
00621   *         @arg @ref LL_GPIO_PIN_14
00622   *         @arg @ref LL_GPIO_PIN_15
00623   * @param  Alternate This parameter can be one of the following values:
00624   *         @arg @ref LL_GPIO_AF_0
00625   *         @arg @ref LL_GPIO_AF_1
00626   *         @arg @ref LL_GPIO_AF_2
00627   *         @arg @ref LL_GPIO_AF_3
00628   *         @arg @ref LL_GPIO_AF_4
00629   *         @arg @ref LL_GPIO_AF_5
00630   *         @arg @ref LL_GPIO_AF_6
00631   *         @arg @ref LL_GPIO_AF_7
00632   *         @arg @ref LL_GPIO_AF_8
00633   *         @arg @ref LL_GPIO_AF_9
00634   *         @arg @ref LL_GPIO_AF_10
00635   *         @arg @ref LL_GPIO_AF_11
00636   *         @arg @ref LL_GPIO_AF_12
00637   *         @arg @ref LL_GPIO_AF_13
00638   *         @arg @ref LL_GPIO_AF_14
00639   *         @arg @ref LL_GPIO_AF_15
00640   * @retval None
00641   */
00642 __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
00643 {
00644   MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U)),
00645              (Alternate << (POSITION_VAL(Pin >> 8U) * 4U)));
00646 }
00647
00648 /**
00649   * @brief  Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
00650   * @note   Possible values are from AF0 to AF15 depending on target.
00651   * @rmtoll AFRH         AFSELy        LL_GPIO_GetAFPin_8_15
00652   * @param  GPIOx GPIO Port
00653   * @param  Pin This parameter can be one of the following values:
00654   *         @arg @ref LL_GPIO_PIN_8
00655   *         @arg @ref LL_GPIO_PIN_9
00656   *         @arg @ref LL_GPIO_PIN_10
00657   *         @arg @ref LL_GPIO_PIN_11
00658   *         @arg @ref LL_GPIO_PIN_12
00659   *         @arg @ref LL_GPIO_PIN_13
00660   *         @arg @ref LL_GPIO_PIN_14
00661   *         @arg @ref LL_GPIO_PIN_15
00662   * @retval Returned value can be one of the following values:
00663   *         @arg @ref LL_GPIO_AF_0
00664   *         @arg @ref LL_GPIO_AF_1
00665   *         @arg @ref LL_GPIO_AF_2
00666   *         @arg @ref LL_GPIO_AF_3
00667   *         @arg @ref LL_GPIO_AF_4
00668   *         @arg @ref LL_GPIO_AF_5
00669   *         @arg @ref LL_GPIO_AF_6
00670   *         @arg @ref LL_GPIO_AF_7
00671   *         @arg @ref LL_GPIO_AF_8
00672   *         @arg @ref LL_GPIO_AF_9
00673   *         @arg @ref LL_GPIO_AF_10
00674   *         @arg @ref LL_GPIO_AF_11
00675   *         @arg @ref LL_GPIO_AF_12
00676   *         @arg @ref LL_GPIO_AF_13
00677   *         @arg @ref LL_GPIO_AF_14
00678   *         @arg @ref LL_GPIO_AF_15
00679   */
00680 __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)
00681 {
00682   return (uint32_t)(READ_BIT(GPIOx->AFR[1],
00683                              (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U));
00684 }
00685
00686
00687 /**
00688   * @brief  Lock configuration of several pins for a dedicated port.
00689   * @note   When the lock sequence has been applied on a port bit, the
00690   *         value of this port bit can no longer be modified until the
00691   *         next reset.
00692   * @note   Each lock bit freezes a specific configuration register
00693   *         (control and alternate function registers).
00694   * @rmtoll LCKR         LCKK          LL_GPIO_LockPin
00695   * @param  GPIOx GPIO Port
00696   * @param  PinMask This parameter can be a combination of the following values:
00697   *         @arg @ref LL_GPIO_PIN_0
00698   *         @arg @ref LL_GPIO_PIN_1
00699   *         @arg @ref LL_GPIO_PIN_2
00700   *         @arg @ref LL_GPIO_PIN_3
00701   *         @arg @ref LL_GPIO_PIN_4
00702   *         @arg @ref LL_GPIO_PIN_5
00703   *         @arg @ref LL_GPIO_PIN_6
00704   *         @arg @ref LL_GPIO_PIN_7
00705   *         @arg @ref LL_GPIO_PIN_8
00706   *         @arg @ref LL_GPIO_PIN_9
00707   *         @arg @ref LL_GPIO_PIN_10
00708   *         @arg @ref LL_GPIO_PIN_11
00709   *         @arg @ref LL_GPIO_PIN_12
00710   *         @arg @ref LL_GPIO_PIN_13
00711   *         @arg @ref LL_GPIO_PIN_14
00712   *         @arg @ref LL_GPIO_PIN_15
00713   *         @arg @ref LL_GPIO_PIN_ALL
00714   * @retval None
00715   */
00716 __STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00717 {
00718   __IO uint32_t temp;
00719   WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
00720   WRITE_REG(GPIOx->LCKR, PinMask);
00721   WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
00722   /* Read LCKK register. This read is mandatory to complete key lock sequence */
00723   temp = READ_REG(GPIOx->LCKR);
00724   (void) temp;
00725 }
00726
00727 /**
00728   * @brief  Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
00729   * @rmtoll LCKR         LCKy          LL_GPIO_IsPinLocked
00730   * @param  GPIOx GPIO Port
00731   * @param  PinMask This parameter can be a combination of the following values:
00732   *         @arg @ref LL_GPIO_PIN_0
00733   *         @arg @ref LL_GPIO_PIN_1
00734   *         @arg @ref LL_GPIO_PIN_2
00735   *         @arg @ref LL_GPIO_PIN_3
00736   *         @arg @ref LL_GPIO_PIN_4
00737   *         @arg @ref LL_GPIO_PIN_5
00738   *         @arg @ref LL_GPIO_PIN_6
00739   *         @arg @ref LL_GPIO_PIN_7
00740   *         @arg @ref LL_GPIO_PIN_8
00741   *         @arg @ref LL_GPIO_PIN_9
00742   *         @arg @ref LL_GPIO_PIN_10
00743   *         @arg @ref LL_GPIO_PIN_11
00744   *         @arg @ref LL_GPIO_PIN_12
00745   *         @arg @ref LL_GPIO_PIN_13
00746   *         @arg @ref LL_GPIO_PIN_14
00747   *         @arg @ref LL_GPIO_PIN_15
00748   *         @arg @ref LL_GPIO_PIN_ALL
00749   * @retval State of bit (1 or 0).
00750   */
00751 __STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00752 {
00753   return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL);
00754 }
00755
00756 /**
00757   * @brief  Return 1 if one of the pin of a dedicated port is locked. else return 0.
00758   * @rmtoll LCKR         LCKK          LL_GPIO_IsAnyPinLocked
00759   * @param  GPIOx GPIO Port
00760   * @retval State of bit (1 or 0).
00761   */
00762 __STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
00763 {
00764   return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL);
00765 }
00766
00767 /**
00768   * @}
00769   */
00770
00771 /** @defgroup GPIO_LL_EF_Data_Access Data Access
00772   * @{
00773   */
00774
00775 /**
00776   * @brief  Return full input data register value for a dedicated port.
00777   * @rmtoll IDR          IDy           LL_GPIO_ReadInputPort
00778   * @param  GPIOx GPIO Port
00779   * @retval Input data register value of port
00780   */
00781 __STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
00782 {
00783   return (uint32_t)(READ_REG(GPIOx->IDR));
00784 }
00785
00786 /**
00787   * @brief  Return if input data level for several pins of dedicated port is high or low.
00788   * @rmtoll IDR          IDy           LL_GPIO_IsInputPinSet
00789   * @param  GPIOx GPIO Port
00790   * @param  PinMask This parameter can be a combination of the following values:
00791   *         @arg @ref LL_GPIO_PIN_0
00792   *         @arg @ref LL_GPIO_PIN_1
00793   *         @arg @ref LL_GPIO_PIN_2
00794   *         @arg @ref LL_GPIO_PIN_3
00795   *         @arg @ref LL_GPIO_PIN_4
00796   *         @arg @ref LL_GPIO_PIN_5
00797   *         @arg @ref LL_GPIO_PIN_6
00798   *         @arg @ref LL_GPIO_PIN_7
00799   *         @arg @ref LL_GPIO_PIN_8
00800   *         @arg @ref LL_GPIO_PIN_9
00801   *         @arg @ref LL_GPIO_PIN_10
00802   *         @arg @ref LL_GPIO_PIN_11
00803   *         @arg @ref LL_GPIO_PIN_12
00804   *         @arg @ref LL_GPIO_PIN_13
00805   *         @arg @ref LL_GPIO_PIN_14
00806   *         @arg @ref LL_GPIO_PIN_15
00807   *         @arg @ref LL_GPIO_PIN_ALL
00808   * @retval State of bit (1 or 0).
00809   */
00810 __STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00811 {
00812   return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL);
00813 }
00814
00815 /**
00816   * @brief  Write output data register for the port.
00817   * @rmtoll ODR          ODy           LL_GPIO_WriteOutputPort
00818   * @param  GPIOx GPIO Port
00819   * @param  PortValue Level value for each pin of the port
00820   * @retval None
00821   */
00822 __STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
00823 {
00824   WRITE_REG(GPIOx->ODR, PortValue);
00825 }
00826
00827 /**
00828   * @brief  Return full output data register value for a dedicated port.
00829   * @rmtoll ODR          ODy           LL_GPIO_ReadOutputPort
00830   * @param  GPIOx GPIO Port
00831   * @retval Output data register value of port
00832   */
00833 __STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
00834 {
00835   return (uint32_t)(READ_REG(GPIOx->ODR));
00836 }
00837
00838 /**
00839   * @brief  Return if input data level for several pins of dedicated port is high or low.
00840   * @rmtoll ODR          ODy           LL_GPIO_IsOutputPinSet
00841   * @param  GPIOx GPIO Port
00842   * @param  PinMask This parameter can be a combination of the following values:
00843   *         @arg @ref LL_GPIO_PIN_0
00844   *         @arg @ref LL_GPIO_PIN_1
00845   *         @arg @ref LL_GPIO_PIN_2
00846   *         @arg @ref LL_GPIO_PIN_3
00847   *         @arg @ref LL_GPIO_PIN_4
00848   *         @arg @ref LL_GPIO_PIN_5
00849   *         @arg @ref LL_GPIO_PIN_6
00850   *         @arg @ref LL_GPIO_PIN_7
00851   *         @arg @ref LL_GPIO_PIN_8
00852   *         @arg @ref LL_GPIO_PIN_9
00853   *         @arg @ref LL_GPIO_PIN_10
00854   *         @arg @ref LL_GPIO_PIN_11
00855   *         @arg @ref LL_GPIO_PIN_12
00856   *         @arg @ref LL_GPIO_PIN_13
00857   *         @arg @ref LL_GPIO_PIN_14
00858   *         @arg @ref LL_GPIO_PIN_15
00859   *         @arg @ref LL_GPIO_PIN_ALL
00860   * @retval State of bit (1 or 0).
00861   */
00862 __STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00863 {
00864   return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL);
00865 }
00866
00867 /**
00868   * @brief  Set several pins to high level on dedicated gpio port.
00869   * @rmtoll BSRR         BSy           LL_GPIO_SetOutputPin
00870   * @param  GPIOx GPIO Port
00871   * @param  PinMask This parameter can be a combination of the following values:
00872   *         @arg @ref LL_GPIO_PIN_0
00873   *         @arg @ref LL_GPIO_PIN_1
00874   *         @arg @ref LL_GPIO_PIN_2
00875   *         @arg @ref LL_GPIO_PIN_3
00876   *         @arg @ref LL_GPIO_PIN_4
00877   *         @arg @ref LL_GPIO_PIN_5
00878   *         @arg @ref LL_GPIO_PIN_6
00879   *         @arg @ref LL_GPIO_PIN_7
00880   *         @arg @ref LL_GPIO_PIN_8
00881   *         @arg @ref LL_GPIO_PIN_9
00882   *         @arg @ref LL_GPIO_PIN_10
00883   *         @arg @ref LL_GPIO_PIN_11
00884   *         @arg @ref LL_GPIO_PIN_12
00885   *         @arg @ref LL_GPIO_PIN_13
00886   *         @arg @ref LL_GPIO_PIN_14
00887   *         @arg @ref LL_GPIO_PIN_15
00888   *         @arg @ref LL_GPIO_PIN_ALL
00889   * @retval None
00890   */
00891 __STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00892 {
00893   WRITE_REG(GPIOx->BSRR, PinMask);
00894 }
00895
00896 /**
00897   * @brief  Set several pins to low level on dedicated gpio port.
00898   * @rmtoll BRR          BRy           LL_GPIO_ResetOutputPin
00899   * @param  GPIOx GPIO Port
00900   * @param  PinMask This parameter can be a combination of the following values:
00901   *         @arg @ref LL_GPIO_PIN_0
00902   *         @arg @ref LL_GPIO_PIN_1
00903   *         @arg @ref LL_GPIO_PIN_2
00904   *         @arg @ref LL_GPIO_PIN_3
00905   *         @arg @ref LL_GPIO_PIN_4
00906   *         @arg @ref LL_GPIO_PIN_5
00907   *         @arg @ref LL_GPIO_PIN_6
00908   *         @arg @ref LL_GPIO_PIN_7
00909   *         @arg @ref LL_GPIO_PIN_8
00910   *         @arg @ref LL_GPIO_PIN_9
00911   *         @arg @ref LL_GPIO_PIN_10
00912   *         @arg @ref LL_GPIO_PIN_11
00913   *         @arg @ref LL_GPIO_PIN_12
00914   *         @arg @ref LL_GPIO_PIN_13
00915   *         @arg @ref LL_GPIO_PIN_14
00916   *         @arg @ref LL_GPIO_PIN_15
00917   *         @arg @ref LL_GPIO_PIN_ALL
00918   * @retval None
00919   */
00920 __STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00921 {
00922   WRITE_REG(GPIOx->BRR, PinMask);
00923 }
00924
00925 /**
00926   * @brief  Toggle data value for several pin of dedicated port.
00927   * @rmtoll ODR          ODy           LL_GPIO_TogglePin
00928   * @param  GPIOx GPIO Port
00929   * @param  PinMask This parameter can be a combination of the following values:
00930   *         @arg @ref LL_GPIO_PIN_0
00931   *         @arg @ref LL_GPIO_PIN_1
00932   *         @arg @ref LL_GPIO_PIN_2
00933   *         @arg @ref LL_GPIO_PIN_3
00934   *         @arg @ref LL_GPIO_PIN_4
00935   *         @arg @ref LL_GPIO_PIN_5
00936   *         @arg @ref LL_GPIO_PIN_6
00937   *         @arg @ref LL_GPIO_PIN_7
00938   *         @arg @ref LL_GPIO_PIN_8
00939   *         @arg @ref LL_GPIO_PIN_9
00940   *         @arg @ref LL_GPIO_PIN_10
00941   *         @arg @ref LL_GPIO_PIN_11
00942   *         @arg @ref LL_GPIO_PIN_12
00943   *         @arg @ref LL_GPIO_PIN_13
00944   *         @arg @ref LL_GPIO_PIN_14
00945   *         @arg @ref LL_GPIO_PIN_15
00946   *         @arg @ref LL_GPIO_PIN_ALL
00947   * @retval None
00948   */
00949 __STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00950 {
00951   WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask);
00952 }
00953
00954 /**
00955   * @}
00956   */
00957
00958 #if defined(USE_FULL_LL_DRIVER)
00959 /** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
00960   * @{
00961   */
00962
00963 ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
00964 ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
00965 void        LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
00966
00967 /**
00968   * @}
00969   */
00970 #endif /* USE_FULL_LL_DRIVER */
00971
00972 /**
00973   * @}
00974   */
00975
00976 /**
00977   * @}
00978   */
00979
00980 #endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOH) */
00981 /**
00982   * @}
00983   */
00984
00985 #ifdef __cplusplus
00986 }
00987 #endif
00988
00989 #endif /* STM32WBxx_LL_GPIO_H */
00990
00991 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_hsem.h Source File

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stm32wbxx_ll_hsem.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_hsem.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of HSEM LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_LL_HSEM_H
00022 #define STM32WBxx_LL_HSEM_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx.h"
00030
00031 /** @addtogroup STM32WBxx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined(HSEM)
00036
00037 /** @defgroup HSEM_LL HSEM
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /* Private macros ------------------------------------------------------------*/
00045
00046 /* Exported types ------------------------------------------------------------*/
00047 /* Exported constants --------------------------------------------------------*/
00048
00049 /** @defgroup HSEM_LL_Exported_Constants HSEM Exported Constants
00050   * @{
00051   */
00052
00053 /** @defgroup HSEM_LL_EC_COREID COREID Defines
00054   * @{
00055   */
00056 #define LL_HSEM_COREID_NONE             0U
00057 #define LL_HSEM_COREID_CPU1             HSEM_CR_COREID_CPU1
00058 #define LL_HSEM_COREID_CPU2             HSEM_CR_COREID_CPU2
00059 #define LL_HSEM_COREID                  HSEM_CR_COREID_CURRENT
00060 /**
00061   * @}
00062   */
00063
00064 /** @defgroup HSEM_LL_EC_GET_FLAG Get Flags Defines
00065   * @brief    Flags defines which can be used with LL_HSEM_ReadReg function
00066   * @{
00067   */
00068
00069 #define LL_HSEM_SEMAPHORE_0                HSEM_C1IER_ISE0
00070 #define LL_HSEM_SEMAPHORE_1                HSEM_C1IER_ISE1
00071 #define LL_HSEM_SEMAPHORE_2                HSEM_C1IER_ISE2
00072 #define LL_HSEM_SEMAPHORE_3                HSEM_C1IER_ISE3
00073 #define LL_HSEM_SEMAPHORE_4                HSEM_C1IER_ISE4
00074 #define LL_HSEM_SEMAPHORE_5                HSEM_C1IER_ISE5
00075 #define LL_HSEM_SEMAPHORE_6                HSEM_C1IER_ISE6
00076 #define LL_HSEM_SEMAPHORE_7                HSEM_C1IER_ISE7
00077 #define LL_HSEM_SEMAPHORE_8                HSEM_C1IER_ISE8
00078 #define LL_HSEM_SEMAPHORE_9                HSEM_C1IER_ISE9
00079 #define LL_HSEM_SEMAPHORE_10               HSEM_C1IER_ISE10
00080 #define LL_HSEM_SEMAPHORE_11               HSEM_C1IER_ISE11
00081 #define LL_HSEM_SEMAPHORE_12               HSEM_C1IER_ISE12
00082 #define LL_HSEM_SEMAPHORE_13               HSEM_C1IER_ISE13
00083 #define LL_HSEM_SEMAPHORE_14               HSEM_C1IER_ISE14
00084 #define LL_HSEM_SEMAPHORE_15               HSEM_C1IER_ISE15
00085 #define LL_HSEM_SEMAPHORE_16               HSEM_C1IER_ISE16
00086 #define LL_HSEM_SEMAPHORE_17               HSEM_C1IER_ISE17
00087 #define LL_HSEM_SEMAPHORE_18               HSEM_C1IER_ISE18
00088 #define LL_HSEM_SEMAPHORE_19               HSEM_C1IER_ISE19
00089 #define LL_HSEM_SEMAPHORE_20               HSEM_C1IER_ISE20
00090 #define LL_HSEM_SEMAPHORE_21               HSEM_C1IER_ISE21
00091 #define LL_HSEM_SEMAPHORE_22               HSEM_C1IER_ISE22
00092 #define LL_HSEM_SEMAPHORE_23               HSEM_C1IER_ISE23
00093 #define LL_HSEM_SEMAPHORE_24               HSEM_C1IER_ISE24
00094 #define LL_HSEM_SEMAPHORE_25               HSEM_C1IER_ISE25
00095 #define LL_HSEM_SEMAPHORE_26               HSEM_C1IER_ISE26
00096 #define LL_HSEM_SEMAPHORE_27               HSEM_C1IER_ISE27
00097 #define LL_HSEM_SEMAPHORE_28               HSEM_C1IER_ISE28
00098 #define LL_HSEM_SEMAPHORE_29               HSEM_C1IER_ISE29
00099 #define LL_HSEM_SEMAPHORE_30               HSEM_C1IER_ISE30
00100 #define LL_HSEM_SEMAPHORE_31               HSEM_C1IER_ISE31
00101 #define LL_HSEM_SEMAPHORE_ALL              0xFFFFFFFFU
00102 /**
00103   * @}
00104   */
00105
00106 /**
00107   * @}
00108   */
00109
00110 /* Exported macro ------------------------------------------------------------*/
00111 /** @defgroup HSEM_LL_Exported_Macros HSEM Exported Macros
00112   * @{
00113   */
00114
00115 /** @defgroup HSEM_LL_EM_WRITE_READ Common Write and read registers Macros
00116   * @{
00117   */
00118
00119 /**
00120   * @brief  Write a value in HSEM register
00121   * @param  __INSTANCE__ HSEM Instance
00122   * @param  __REG__ Register to be written
00123   * @param  __VALUE__ Value to be written in the register
00124   * @retval None
00125   */
00126 #define LL_HSEM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00127
00128 /**
00129   * @brief  Read a value in HSEM register
00130   * @param  __INSTANCE__ HSEM Instance
00131   * @param  __REG__ Register to be read
00132   * @retval Register value
00133   */
00134 #define LL_HSEM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00135 /**
00136   * @}
00137   */
00138
00139 /**
00140   * @}
00141   */
00142
00143 /* Exported functions --------------------------------------------------------*/
00144 /** @defgroup HSEM_LL_Exported_Functions HSEM Exported Functions
00145   * @{
00146   */
00147
00148 /** @defgroup HSEM_LL_EF_Data_Management Data_Management
00149   * @{
00150   */
00151
00152
00153 /**
00154   * @brief  Return 1 if the semaphore is locked, else return 0.
00155   * @rmtoll R            LOCK          LL_HSEM_IsSemaphoreLocked
00156   * @param  HSEMx HSEM Instance.
00157   * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
00158   * @retval State of bit (1 or 0).
00159   */
00160 __STATIC_INLINE uint32_t LL_HSEM_IsSemaphoreLocked(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
00161 {
00162   return ((READ_BIT(HSEMx->R[Semaphore], HSEM_R_LOCK) == (HSEM_R_LOCK_Msk)) ? 1UL : 0UL);
00163 }
00164
00165 /**
00166   * @brief  Get core id.
00167   * @rmtoll R            COREID        LL_HSEM_GetCoreId
00168   * @param  HSEMx HSEM Instance.
00169   * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
00170   * @retval Returned value can be one of the following values:
00171   *         @arg @ref LL_HSEM_COREID_NONE
00172   *         @arg @ref LL_HSEM_COREID_CPU1
00173   *         @arg @ref LL_HSEM_COREID_CPU2
00174   */
00175 __STATIC_INLINE uint32_t LL_HSEM_GetCoreId(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
00176 {
00177   return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_COREID_Msk));
00178 }
00179
00180 /**
00181   * @brief  Get process id.
00182   * @rmtoll R            PROCID        LL_HSEM_GetProcessId
00183   * @param  HSEMx HSEM Instance.
00184   * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
00185   * @retval Process number. Value between Min_Data=0 and Max_Data=255
00186   */
00187 __STATIC_INLINE uint32_t LL_HSEM_GetProcessId(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
00188 {
00189   return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_PROCID_Msk));
00190 }
00191
00192 /**
00193   * @brief  Get the lock by writing in R register.
00194   * @note The R register has to be read to determined if the lock is taken.
00195   * @rmtoll R            LOCK          LL_HSEM_SetLock
00196   * @rmtoll R            COREID        LL_HSEM_SetLock
00197   * @rmtoll R            PROCID        LL_HSEM_SetLock
00198   * @param  HSEMx HSEM Instance.
00199   * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
00200   * @param  process Process id. Value between Min_Data=0 and Max_Data=255
00201   * @retval None
00202   */
00203 __STATIC_INLINE void LL_HSEM_SetLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
00204 {
00205   WRITE_REG(HSEMx->R[Semaphore], (HSEM_R_LOCK | LL_HSEM_COREID | process));
00206 }
00207
00208 /**
00209   * @brief  Get the lock with 2-step lock.
00210   * @rmtoll R            LOCK          LL_HSEM_2StepLock
00211   * @rmtoll R            COREID        LL_HSEM_2StepLock
00212   * @rmtoll R            PROCID        LL_HSEM_2StepLock
00213   * @param  HSEMx HSEM Instance.
00214   * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
00215   * @param  process Process id. Value between Min_Data=0 and Max_Data=255
00216   * @retval 1 lock fail, 0 lock successful or already locked by same process and core
00217   */
00218 __STATIC_INLINE uint32_t LL_HSEM_2StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
00219 {
00220   WRITE_REG(HSEMx->R[Semaphore], (HSEM_R_LOCK | LL_HSEM_COREID | process));
00221   return ((HSEMx->R[Semaphore] != (HSEM_R_LOCK | LL_HSEM_COREID | process)) ? 1UL : 0UL);
00222 }
00223
00224 /**
00225   * @brief  Get the lock with 1-step lock.
00226   * @rmtoll RLR          LOCK          LL_HSEM_1StepLock
00227   * @rmtoll RLR          COREID        LL_HSEM_1StepLock
00228   * @rmtoll RLR          PROCID        LL_HSEM_1StepLock
00229   * @param  HSEMx HSEM Instance.
00230   * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
00231   * @retval 1 lock fail, 0 lock successful or already locked by same core
00232   */
00233 __STATIC_INLINE uint32_t LL_HSEM_1StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
00234 {
00235   return ((HSEMx->RLR[Semaphore] != (HSEM_R_LOCK | LL_HSEM_COREID)) ? 1UL : 0UL);
00236 }
00237
00238 /**
00239   * @brief  Release the lock of the semaphore.
00240   * @note In case of LL_HSEM_1StepLock usage to lock a semaphore, the process is 0.
00241   * @rmtoll R            LOCK          LL_HSEM_ReleaseLock
00242   * @param  HSEMx HSEM Instance.
00243   * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
00244   * @param  process Process number. Value between Min_Data=0 and Max_Data=255
00245   * @retval None
00246   */
00247 __STATIC_INLINE void LL_HSEM_ReleaseLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
00248 {
00249   WRITE_REG(HSEMx->R[Semaphore], (LL_HSEM_COREID | process));
00250 }
00251
00252 /**
00253   * @brief  Get the lock status of the semaphore.
00254   * @rmtoll R            LOCK          LL_HSEM_GetStatus
00255   * @param  HSEMx HSEM Instance.
00256   * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
00257   * @retval 0 semaphore is free, 1 semaphore is locked  */
00258 __STATIC_INLINE uint32_t LL_HSEM_GetStatus(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
00259 {
00260   return ((HSEMx->R[Semaphore] != 0U) ? 1UL : 0UL);
00261 }
00262
00263 /**
00264   * @brief  Set the key.
00265   * @rmtoll KEYR         KEY           LL_HSEM_SetKey
00266   * @param  HSEMx HSEM Instance.
00267   * @param  key Key value.
00268   * @retval None
00269   */
00270 __STATIC_INLINE void LL_HSEM_SetKey(HSEM_TypeDef *HSEMx, uint32_t key)
00271 {
00272   WRITE_REG(HSEMx->KEYR, key << HSEM_KEYR_KEY_Pos);
00273 }
00274
00275 /**
00276   * @brief  Get the key.
00277   * @rmtoll KEYR         KEY           LL_HSEM_GetKey
00278   * @param  HSEMx HSEM Instance.
00279   * @retval key to unlock all semaphore from the same core
00280   */
00281 __STATIC_INLINE uint32_t LL_HSEM_GetKey(HSEM_TypeDef *HSEMx)
00282 {
00283   return (uint32_t)(READ_BIT(HSEMx->KEYR, HSEM_KEYR_KEY) >> HSEM_KEYR_KEY_Pos);
00284 }
00285
00286 /**
00287   * @brief  Release all semaphore with the same core id.
00288   * @rmtoll CR           KEY           LL_HSEM_ResetAllLock
00289   * @param  HSEMx HSEM Instance.
00290   * @param  key Key value.
00291   * @param  core This parameter can be one of the following values:
00292   *         @arg @ref LL_HSEM_COREID_CPU1
00293   *         @arg @ref LL_HSEM_COREID_CPU2
00294   * @retval None
00295   */
00296 __STATIC_INLINE void LL_HSEM_ResetAllLock(HSEM_TypeDef *HSEMx, uint32_t key, uint32_t core)
00297 {
00298   WRITE_REG(HSEMx->CR, (key << HSEM_CR_KEY_Pos) | core);
00299 }
00300
00301 /**
00302   * @}
00303   */
00304
00305 /** @defgroup HSEM_LL_EF_IT_Management IT_Management
00306   * @{
00307   */
00308
00309 /**
00310   * @brief  Enable interrupt.
00311   * @rmtoll C1IER         ISEM          LL_HSEM_EnableIT_C1IER
00312   * @param  HSEMx HSEM Instance.
00313   * @param  SemaphoreMask This parameter can be a combination of the following values:
00314   *         @arg @ref LL_HSEM_SEMAPHORE_0
00315   *         @arg @ref LL_HSEM_SEMAPHORE_1
00316   *         @arg @ref LL_HSEM_SEMAPHORE_2
00317   *         @arg @ref LL_HSEM_SEMAPHORE_3
00318   *         @arg @ref LL_HSEM_SEMAPHORE_4
00319   *         @arg @ref LL_HSEM_SEMAPHORE_5
00320   *         @arg @ref LL_HSEM_SEMAPHORE_6
00321   *         @arg @ref LL_HSEM_SEMAPHORE_7
00322   *         @arg @ref LL_HSEM_SEMAPHORE_8
00323   *         @arg @ref LL_HSEM_SEMAPHORE_9
00324   *         @arg @ref LL_HSEM_SEMAPHORE_10
00325   *         @arg @ref LL_HSEM_SEMAPHORE_11
00326   *         @arg @ref LL_HSEM_SEMAPHORE_12
00327   *         @arg @ref LL_HSEM_SEMAPHORE_13
00328   *         @arg @ref LL_HSEM_SEMAPHORE_14
00329   *         @arg @ref LL_HSEM_SEMAPHORE_15
00330   *         @arg @ref LL_HSEM_SEMAPHORE_16
00331   *         @arg @ref LL_HSEM_SEMAPHORE_17
00332   *         @arg @ref LL_HSEM_SEMAPHORE_18
00333   *         @arg @ref LL_HSEM_SEMAPHORE_19
00334   *         @arg @ref LL_HSEM_SEMAPHORE_20
00335   *         @arg @ref LL_HSEM_SEMAPHORE_21
00336   *         @arg @ref LL_HSEM_SEMAPHORE_22
00337   *         @arg @ref LL_HSEM_SEMAPHORE_23
00338   *         @arg @ref LL_HSEM_SEMAPHORE_24
00339   *         @arg @ref LL_HSEM_SEMAPHORE_25
00340   *         @arg @ref LL_HSEM_SEMAPHORE_26
00341   *         @arg @ref LL_HSEM_SEMAPHORE_27
00342   *         @arg @ref LL_HSEM_SEMAPHORE_28
00343   *         @arg @ref LL_HSEM_SEMAPHORE_29
00344   *         @arg @ref LL_HSEM_SEMAPHORE_30
00345   *         @arg @ref LL_HSEM_SEMAPHORE_31
00346   *         @arg @ref LL_HSEM_SEMAPHORE_ALL
00347   * @retval None
00348   */
00349 __STATIC_INLINE void LL_HSEM_EnableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
00350 {
00351   SET_BIT(HSEMx->C1IER, SemaphoreMask);
00352 }
00353
00354 /**
00355   * @brief  Disable interrupt.
00356   * @rmtoll C1IER          ISEM          LL_HSEM_DisableIT_C1IER
00357   * @param  HSEMx HSEM Instance.
00358   * @param  SemaphoreMask This parameter can be a combination of the following values:
00359   *         @arg @ref LL_HSEM_SEMAPHORE_0
00360   *         @arg @ref LL_HSEM_SEMAPHORE_1
00361   *         @arg @ref LL_HSEM_SEMAPHORE_2
00362   *         @arg @ref LL_HSEM_SEMAPHORE_3
00363   *         @arg @ref LL_HSEM_SEMAPHORE_4
00364   *         @arg @ref LL_HSEM_SEMAPHORE_5
00365   *         @arg @ref LL_HSEM_SEMAPHORE_6
00366   *         @arg @ref LL_HSEM_SEMAPHORE_7
00367   *         @arg @ref LL_HSEM_SEMAPHORE_8
00368   *         @arg @ref LL_HSEM_SEMAPHORE_9
00369   *         @arg @ref LL_HSEM_SEMAPHORE_10
00370   *         @arg @ref LL_HSEM_SEMAPHORE_11
00371   *         @arg @ref LL_HSEM_SEMAPHORE_12
00372   *         @arg @ref LL_HSEM_SEMAPHORE_13
00373   *         @arg @ref LL_HSEM_SEMAPHORE_14
00374   *         @arg @ref LL_HSEM_SEMAPHORE_15
00375   *         @arg @ref LL_HSEM_SEMAPHORE_16
00376   *         @arg @ref LL_HSEM_SEMAPHORE_17
00377   *         @arg @ref LL_HSEM_SEMAPHORE_18
00378   *         @arg @ref LL_HSEM_SEMAPHORE_19
00379   *         @arg @ref LL_HSEM_SEMAPHORE_20
00380   *         @arg @ref LL_HSEM_SEMAPHORE_21
00381   *         @arg @ref LL_HSEM_SEMAPHORE_22
00382   *         @arg @ref LL_HSEM_SEMAPHORE_23
00383   *         @arg @ref LL_HSEM_SEMAPHORE_24
00384   *         @arg @ref LL_HSEM_SEMAPHORE_25
00385   *         @arg @ref LL_HSEM_SEMAPHORE_26
00386   *         @arg @ref LL_HSEM_SEMAPHORE_27
00387   *         @arg @ref LL_HSEM_SEMAPHORE_28
00388   *         @arg @ref LL_HSEM_SEMAPHORE_29
00389   *         @arg @ref LL_HSEM_SEMAPHORE_30
00390   *         @arg @ref LL_HSEM_SEMAPHORE_31
00391   *         @arg @ref LL_HSEM_SEMAPHORE_ALL
00392   * @retval None
00393   */
00394 __STATIC_INLINE void LL_HSEM_DisableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
00395 {
00396   CLEAR_BIT(HSEMx->C1IER, SemaphoreMask);
00397 }
00398
00399 /**
00400   * @brief  Check if interrupt is enabled.
00401   * @rmtoll C1IER          ISEM          LL_HSEM_IsEnabledIT_C1IER
00402   * @param  HSEMx HSEM Instance.
00403   * @param  SemaphoreMask This parameter can be a combination of the following values:
00404   *         @arg @ref LL_HSEM_SEMAPHORE_0
00405   *         @arg @ref LL_HSEM_SEMAPHORE_1
00406   *         @arg @ref LL_HSEM_SEMAPHORE_2
00407   *         @arg @ref LL_HSEM_SEMAPHORE_3
00408   *         @arg @ref LL_HSEM_SEMAPHORE_4
00409   *         @arg @ref LL_HSEM_SEMAPHORE_5
00410   *         @arg @ref LL_HSEM_SEMAPHORE_6
00411   *         @arg @ref LL_HSEM_SEMAPHORE_7
00412   *         @arg @ref LL_HSEM_SEMAPHORE_8
00413   *         @arg @ref LL_HSEM_SEMAPHORE_9
00414   *         @arg @ref LL_HSEM_SEMAPHORE_10
00415   *         @arg @ref LL_HSEM_SEMAPHORE_11
00416   *         @arg @ref LL_HSEM_SEMAPHORE_12
00417   *         @arg @ref LL_HSEM_SEMAPHORE_13
00418   *         @arg @ref LL_HSEM_SEMAPHORE_14
00419   *         @arg @ref LL_HSEM_SEMAPHORE_15
00420   *         @arg @ref LL_HSEM_SEMAPHORE_16
00421   *         @arg @ref LL_HSEM_SEMAPHORE_17
00422   *         @arg @ref LL_HSEM_SEMAPHORE_18
00423   *         @arg @ref LL_HSEM_SEMAPHORE_19
00424   *         @arg @ref LL_HSEM_SEMAPHORE_20
00425   *         @arg @ref LL_HSEM_SEMAPHORE_21
00426   *         @arg @ref LL_HSEM_SEMAPHORE_22
00427   *         @arg @ref LL_HSEM_SEMAPHORE_23
00428   *         @arg @ref LL_HSEM_SEMAPHORE_24
00429   *         @arg @ref LL_HSEM_SEMAPHORE_25
00430   *         @arg @ref LL_HSEM_SEMAPHORE_26
00431   *         @arg @ref LL_HSEM_SEMAPHORE_27
00432   *         @arg @ref LL_HSEM_SEMAPHORE_28
00433   *         @arg @ref LL_HSEM_SEMAPHORE_29
00434   *         @arg @ref LL_HSEM_SEMAPHORE_30
00435   *         @arg @ref LL_HSEM_SEMAPHORE_31
00436   *         @arg @ref LL_HSEM_SEMAPHORE_ALL
00437   * @retval State of bit (1 or 0).
00438   */
00439 __STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
00440 {
00441   return ((READ_BIT(HSEMx->C1IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
00442 }
00443
00444 /**
00445   * @brief  Enable interrupt.
00446   * @rmtoll C2IER         ISEM          LL_HSEM_EnableIT_C2IER
00447   * @param  HSEMx HSEM Instance.
00448   * @param  SemaphoreMask This parameter can be a combination of the following values:
00449   *         @arg @ref LL_HSEM_SEMAPHORE_0
00450   *         @arg @ref LL_HSEM_SEMAPHORE_1
00451   *         @arg @ref LL_HSEM_SEMAPHORE_2
00452   *         @arg @ref LL_HSEM_SEMAPHORE_3
00453   *         @arg @ref LL_HSEM_SEMAPHORE_4
00454   *         @arg @ref LL_HSEM_SEMAPHORE_5
00455   *         @arg @ref LL_HSEM_SEMAPHORE_6
00456   *         @arg @ref LL_HSEM_SEMAPHORE_7
00457   *         @arg @ref LL_HSEM_SEMAPHORE_8
00458   *         @arg @ref LL_HSEM_SEMAPHORE_9
00459   *         @arg @ref LL_HSEM_SEMAPHORE_10
00460   *         @arg @ref LL_HSEM_SEMAPHORE_11
00461   *         @arg @ref LL_HSEM_SEMAPHORE_12
00462   *         @arg @ref LL_HSEM_SEMAPHORE_13
00463   *         @arg @ref LL_HSEM_SEMAPHORE_14
00464   *         @arg @ref LL_HSEM_SEMAPHORE_15
00465   *         @arg @ref LL_HSEM_SEMAPHORE_16
00466   *         @arg @ref LL_HSEM_SEMAPHORE_17
00467   *         @arg @ref LL_HSEM_SEMAPHORE_18
00468   *         @arg @ref LL_HSEM_SEMAPHORE_19
00469   *         @arg @ref LL_HSEM_SEMAPHORE_20
00470   *         @arg @ref LL_HSEM_SEMAPHORE_21
00471   *         @arg @ref LL_HSEM_SEMAPHORE_22
00472   *         @arg @ref LL_HSEM_SEMAPHORE_23
00473   *         @arg @ref LL_HSEM_SEMAPHORE_24
00474   *         @arg @ref LL_HSEM_SEMAPHORE_25
00475   *         @arg @ref LL_HSEM_SEMAPHORE_26
00476   *         @arg @ref LL_HSEM_SEMAPHORE_27
00477   *         @arg @ref LL_HSEM_SEMAPHORE_28
00478   *         @arg @ref LL_HSEM_SEMAPHORE_29
00479   *         @arg @ref LL_HSEM_SEMAPHORE_30
00480   *         @arg @ref LL_HSEM_SEMAPHORE_31
00481   *         @arg @ref LL_HSEM_SEMAPHORE_ALL
00482   * @retval None
00483   */
00484 __STATIC_INLINE void LL_HSEM_EnableIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
00485 {
00486   SET_BIT(HSEMx->C2IER, SemaphoreMask);
00487 }
00488
00489 /**
00490   * @brief  Disable interrupt.
00491   * @rmtoll C2IER          ISEM          LL_HSEM_DisableIT_C2IER
00492   * @param  HSEMx HSEM Instance.
00493   * @param  SemaphoreMask This parameter can be a combination of the following values:
00494   *         @arg @ref LL_HSEM_SEMAPHORE_0
00495   *         @arg @ref LL_HSEM_SEMAPHORE_1
00496   *         @arg @ref LL_HSEM_SEMAPHORE_2
00497   *         @arg @ref LL_HSEM_SEMAPHORE_3
00498   *         @arg @ref LL_HSEM_SEMAPHORE_4
00499   *         @arg @ref LL_HSEM_SEMAPHORE_5
00500   *         @arg @ref LL_HSEM_SEMAPHORE_6
00501   *         @arg @ref LL_HSEM_SEMAPHORE_7
00502   *         @arg @ref LL_HSEM_SEMAPHORE_8
00503   *         @arg @ref LL_HSEM_SEMAPHORE_9
00504   *         @arg @ref LL_HSEM_SEMAPHORE_10
00505   *         @arg @ref LL_HSEM_SEMAPHORE_11
00506   *         @arg @ref LL_HSEM_SEMAPHORE_12
00507   *         @arg @ref LL_HSEM_SEMAPHORE_13
00508   *         @arg @ref LL_HSEM_SEMAPHORE_14
00509   *         @arg @ref LL_HSEM_SEMAPHORE_15
00510   *         @arg @ref LL_HSEM_SEMAPHORE_16
00511   *         @arg @ref LL_HSEM_SEMAPHORE_17
00512   *         @arg @ref LL_HSEM_SEMAPHORE_18
00513   *         @arg @ref LL_HSEM_SEMAPHORE_19
00514   *         @arg @ref LL_HSEM_SEMAPHORE_20
00515   *         @arg @ref LL_HSEM_SEMAPHORE_21
00516   *         @arg @ref LL_HSEM_SEMAPHORE_22
00517   *         @arg @ref LL_HSEM_SEMAPHORE_23
00518   *         @arg @ref LL_HSEM_SEMAPHORE_24
00519   *         @arg @ref LL_HSEM_SEMAPHORE_25
00520   *         @arg @ref LL_HSEM_SEMAPHORE_26
00521   *         @arg @ref LL_HSEM_SEMAPHORE_27
00522   *         @arg @ref LL_HSEM_SEMAPHORE_28
00523   *         @arg @ref LL_HSEM_SEMAPHORE_29
00524   *         @arg @ref LL_HSEM_SEMAPHORE_30
00525   *         @arg @ref LL_HSEM_SEMAPHORE_31
00526   *         @arg @ref LL_HSEM_SEMAPHORE_ALL
00527   * @retval None
00528   */
00529 __STATIC_INLINE void LL_HSEM_DisableIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
00530 {
00531   CLEAR_BIT(HSEMx->C2IER, SemaphoreMask);
00532 }
00533
00534 /**
00535   * @brief  Check if interrupt is enabled.
00536   * @rmtoll C2IER          ISEM          LL_HSEM_IsEnabledIT_C2IER
00537   * @param  HSEMx HSEM Instance.
00538   * @param  SemaphoreMask This parameter can be a combination of the following values:
00539   *         @arg @ref LL_HSEM_SEMAPHORE_0
00540   *         @arg @ref LL_HSEM_SEMAPHORE_1
00541   *         @arg @ref LL_HSEM_SEMAPHORE_2
00542   *         @arg @ref LL_HSEM_SEMAPHORE_3
00543   *         @arg @ref LL_HSEM_SEMAPHORE_4
00544   *         @arg @ref LL_HSEM_SEMAPHORE_5
00545   *         @arg @ref LL_HSEM_SEMAPHORE_6
00546   *         @arg @ref LL_HSEM_SEMAPHORE_7
00547   *         @arg @ref LL_HSEM_SEMAPHORE_8
00548   *         @arg @ref LL_HSEM_SEMAPHORE_9
00549   *         @arg @ref LL_HSEM_SEMAPHORE_10
00550   *         @arg @ref LL_HSEM_SEMAPHORE_11
00551   *         @arg @ref LL_HSEM_SEMAPHORE_12
00552   *         @arg @ref LL_HSEM_SEMAPHORE_13
00553   *         @arg @ref LL_HSEM_SEMAPHORE_14
00554   *         @arg @ref LL_HSEM_SEMAPHORE_15
00555   *         @arg @ref LL_HSEM_SEMAPHORE_16
00556   *         @arg @ref LL_HSEM_SEMAPHORE_17
00557   *         @arg @ref LL_HSEM_SEMAPHORE_18
00558   *         @arg @ref LL_HSEM_SEMAPHORE_19
00559   *         @arg @ref LL_HSEM_SEMAPHORE_20
00560   *         @arg @ref LL_HSEM_SEMAPHORE_21
00561   *         @arg @ref LL_HSEM_SEMAPHORE_22
00562   *         @arg @ref LL_HSEM_SEMAPHORE_23
00563   *         @arg @ref LL_HSEM_SEMAPHORE_24
00564   *         @arg @ref LL_HSEM_SEMAPHORE_25
00565   *         @arg @ref LL_HSEM_SEMAPHORE_26
00566   *         @arg @ref LL_HSEM_SEMAPHORE_27
00567   *         @arg @ref LL_HSEM_SEMAPHORE_28
00568   *         @arg @ref LL_HSEM_SEMAPHORE_29
00569   *         @arg @ref LL_HSEM_SEMAPHORE_30
00570   *         @arg @ref LL_HSEM_SEMAPHORE_31
00571   *         @arg @ref LL_HSEM_SEMAPHORE_ALL
00572   * @retval State of bit (1 or 0).
00573   */
00574 __STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
00575 {
00576   return ((READ_BIT(HSEMx->C2IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
00577 }
00578 /**
00579   * @}
00580   */
00581
00582 /** @defgroup HSEM_LL_EF_FLAG_Management FLAG_Management
00583   * @{
00584   */
00585
00586 /**
00587   * @brief  Clear interrupt status.
00588   * @rmtoll C1ICR         ISEM          LL_HSEM_ClearFlag_C1ICR
00589   * @param  HSEMx HSEM Instance.
00590   * @param  SemaphoreMask This parameter can be a combination of the following values:
00591   *         @arg @ref LL_HSEM_SEMAPHORE_0
00592   *         @arg @ref LL_HSEM_SEMAPHORE_1
00593   *         @arg @ref LL_HSEM_SEMAPHORE_2
00594   *         @arg @ref LL_HSEM_SEMAPHORE_3
00595   *         @arg @ref LL_HSEM_SEMAPHORE_4
00596   *         @arg @ref LL_HSEM_SEMAPHORE_5
00597   *         @arg @ref LL_HSEM_SEMAPHORE_6
00598   *         @arg @ref LL_HSEM_SEMAPHORE_7
00599   *         @arg @ref LL_HSEM_SEMAPHORE_8
00600   *         @arg @ref LL_HSEM_SEMAPHORE_9
00601   *         @arg @ref LL_HSEM_SEMAPHORE_10
00602   *         @arg @ref LL_HSEM_SEMAPHORE_11
00603   *         @arg @ref LL_HSEM_SEMAPHORE_12
00604   *         @arg @ref LL_HSEM_SEMAPHORE_13
00605   *         @arg @ref LL_HSEM_SEMAPHORE_14
00606   *         @arg @ref LL_HSEM_SEMAPHORE_15
00607   *         @arg @ref LL_HSEM_SEMAPHORE_16
00608   *         @arg @ref LL_HSEM_SEMAPHORE_17
00609   *         @arg @ref LL_HSEM_SEMAPHORE_18
00610   *         @arg @ref LL_HSEM_SEMAPHORE_19
00611   *         @arg @ref LL_HSEM_SEMAPHORE_20
00612   *         @arg @ref LL_HSEM_SEMAPHORE_21
00613   *         @arg @ref LL_HSEM_SEMAPHORE_22
00614   *         @arg @ref LL_HSEM_SEMAPHORE_23
00615   *         @arg @ref LL_HSEM_SEMAPHORE_24
00616   *         @arg @ref LL_HSEM_SEMAPHORE_25
00617   *         @arg @ref LL_HSEM_SEMAPHORE_26
00618   *         @arg @ref LL_HSEM_SEMAPHORE_27
00619   *         @arg @ref LL_HSEM_SEMAPHORE_28
00620   *         @arg @ref LL_HSEM_SEMAPHORE_29
00621   *         @arg @ref LL_HSEM_SEMAPHORE_30
00622   *         @arg @ref LL_HSEM_SEMAPHORE_31
00623   *         @arg @ref LL_HSEM_SEMAPHORE_ALL
00624   * @retval None
00625   */
00626 __STATIC_INLINE void LL_HSEM_ClearFlag_C1ICR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
00627 {
00628   WRITE_REG(HSEMx->C1ICR, SemaphoreMask);
00629 }
00630
00631 /**
00632   * @brief  Get interrupt status from ISR register.
00633   * @rmtoll C1ISR         ISEM          LL_HSEM_IsActiveFlag_C1ISR
00634   * @param  HSEMx HSEM Instance.
00635   * @param  SemaphoreMask This parameter can be a combination of the following values:
00636   *         @arg @ref LL_HSEM_SEMAPHORE_0
00637   *         @arg @ref LL_HSEM_SEMAPHORE_1
00638   *         @arg @ref LL_HSEM_SEMAPHORE_2
00639   *         @arg @ref LL_HSEM_SEMAPHORE_3
00640   *         @arg @ref LL_HSEM_SEMAPHORE_4
00641   *         @arg @ref LL_HSEM_SEMAPHORE_5
00642   *         @arg @ref LL_HSEM_SEMAPHORE_6
00643   *         @arg @ref LL_HSEM_SEMAPHORE_7
00644   *         @arg @ref LL_HSEM_SEMAPHORE_8
00645   *         @arg @ref LL_HSEM_SEMAPHORE_9
00646   *         @arg @ref LL_HSEM_SEMAPHORE_10
00647   *         @arg @ref LL_HSEM_SEMAPHORE_11
00648   *         @arg @ref LL_HSEM_SEMAPHORE_12
00649   *         @arg @ref LL_HSEM_SEMAPHORE_13
00650   *         @arg @ref LL_HSEM_SEMAPHORE_14
00651   *         @arg @ref LL_HSEM_SEMAPHORE_15
00652   *         @arg @ref LL_HSEM_SEMAPHORE_16
00653   *         @arg @ref LL_HSEM_SEMAPHORE_17
00654   *         @arg @ref LL_HSEM_SEMAPHORE_18
00655   *         @arg @ref LL_HSEM_SEMAPHORE_19
00656   *         @arg @ref LL_HSEM_SEMAPHORE_20
00657   *         @arg @ref LL_HSEM_SEMAPHORE_21
00658   *         @arg @ref LL_HSEM_SEMAPHORE_22
00659   *         @arg @ref LL_HSEM_SEMAPHORE_23
00660   *         @arg @ref LL_HSEM_SEMAPHORE_24
00661   *         @arg @ref LL_HSEM_SEMAPHORE_25
00662   *         @arg @ref LL_HSEM_SEMAPHORE_26
00663   *         @arg @ref LL_HSEM_SEMAPHORE_27
00664   *         @arg @ref LL_HSEM_SEMAPHORE_28
00665   *         @arg @ref LL_HSEM_SEMAPHORE_29
00666   *         @arg @ref LL_HSEM_SEMAPHORE_30
00667   *         @arg @ref LL_HSEM_SEMAPHORE_31
00668   *         @arg @ref LL_HSEM_SEMAPHORE_ALL
00669   * @retval State of bit (1 or 0).
00670   */
00671 __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
00672 {
00673   return ((READ_BIT(HSEMx->C1ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
00674 }
00675
00676 /**
00677   * @brief  Get interrupt status from MISR register.
00678   * @rmtoll C1MISR        ISEM          LL_HSEM_IsActiveFlag_C1MISR
00679   * @param  HSEMx HSEM Instance.
00680   * @param  SemaphoreMask This parameter can be a combination of the following values:
00681   *         @arg @ref LL_HSEM_SEMAPHORE_0
00682   *         @arg @ref LL_HSEM_SEMAPHORE_1
00683   *         @arg @ref LL_HSEM_SEMAPHORE_2
00684   *         @arg @ref LL_HSEM_SEMAPHORE_3
00685   *         @arg @ref LL_HSEM_SEMAPHORE_4
00686   *         @arg @ref LL_HSEM_SEMAPHORE_5
00687   *         @arg @ref LL_HSEM_SEMAPHORE_6
00688   *         @arg @ref LL_HSEM_SEMAPHORE_7
00689   *         @arg @ref LL_HSEM_SEMAPHORE_8
00690   *         @arg @ref LL_HSEM_SEMAPHORE_9
00691   *         @arg @ref LL_HSEM_SEMAPHORE_10
00692   *         @arg @ref LL_HSEM_SEMAPHORE_11
00693   *         @arg @ref LL_HSEM_SEMAPHORE_12
00694   *         @arg @ref LL_HSEM_SEMAPHORE_13
00695   *         @arg @ref LL_HSEM_SEMAPHORE_14
00696   *         @arg @ref LL_HSEM_SEMAPHORE_15
00697   *         @arg @ref LL_HSEM_SEMAPHORE_16
00698   *         @arg @ref LL_HSEM_SEMAPHORE_17
00699   *         @arg @ref LL_HSEM_SEMAPHORE_18
00700   *         @arg @ref LL_HSEM_SEMAPHORE_19
00701   *         @arg @ref LL_HSEM_SEMAPHORE_20
00702   *         @arg @ref LL_HSEM_SEMAPHORE_21
00703   *         @arg @ref LL_HSEM_SEMAPHORE_22
00704   *         @arg @ref LL_HSEM_SEMAPHORE_23
00705   *         @arg @ref LL_HSEM_SEMAPHORE_24
00706   *         @arg @ref LL_HSEM_SEMAPHORE_25
00707   *         @arg @ref LL_HSEM_SEMAPHORE_26
00708   *         @arg @ref LL_HSEM_SEMAPHORE_27
00709   *         @arg @ref LL_HSEM_SEMAPHORE_28
00710   *         @arg @ref LL_HSEM_SEMAPHORE_29
00711   *         @arg @ref LL_HSEM_SEMAPHORE_30
00712   *         @arg @ref LL_HSEM_SEMAPHORE_31
00713   *         @arg @ref LL_HSEM_SEMAPHORE_ALL
00714   * @retval State of bit (1 or 0).
00715   */
00716 __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
00717 {
00718   return ((READ_BIT(HSEMx->C1MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
00719 }
00720
00721 /**
00722   * @brief  Clear interrupt status.
00723   * @rmtoll C2ICR         ISEM          LL_HSEM_ClearFlag_C2ICR
00724   * @param  HSEMx HSEM Instance.
00725   * @param  SemaphoreMask This parameter can be a combination of the following values:
00726   *         @arg @ref LL_HSEM_SEMAPHORE_0
00727   *         @arg @ref LL_HSEM_SEMAPHORE_1
00728   *         @arg @ref LL_HSEM_SEMAPHORE_2
00729   *         @arg @ref LL_HSEM_SEMAPHORE_3
00730   *         @arg @ref LL_HSEM_SEMAPHORE_4
00731   *         @arg @ref LL_HSEM_SEMAPHORE_5
00732   *         @arg @ref LL_HSEM_SEMAPHORE_6
00733   *         @arg @ref LL_HSEM_SEMAPHORE_7
00734   *         @arg @ref LL_HSEM_SEMAPHORE_8
00735   *         @arg @ref LL_HSEM_SEMAPHORE_9
00736   *         @arg @ref LL_HSEM_SEMAPHORE_10
00737   *         @arg @ref LL_HSEM_SEMAPHORE_11
00738   *         @arg @ref LL_HSEM_SEMAPHORE_12
00739   *         @arg @ref LL_HSEM_SEMAPHORE_13
00740   *         @arg @ref LL_HSEM_SEMAPHORE_14
00741   *         @arg @ref LL_HSEM_SEMAPHORE_15
00742   *         @arg @ref LL_HSEM_SEMAPHORE_16
00743   *         @arg @ref LL_HSEM_SEMAPHORE_17
00744   *         @arg @ref LL_HSEM_SEMAPHORE_18
00745   *         @arg @ref LL_HSEM_SEMAPHORE_19
00746   *         @arg @ref LL_HSEM_SEMAPHORE_20
00747   *         @arg @ref LL_HSEM_SEMAPHORE_21
00748   *         @arg @ref LL_HSEM_SEMAPHORE_22
00749   *         @arg @ref LL_HSEM_SEMAPHORE_23
00750   *         @arg @ref LL_HSEM_SEMAPHORE_24
00751   *         @arg @ref LL_HSEM_SEMAPHORE_25
00752   *         @arg @ref LL_HSEM_SEMAPHORE_26
00753   *         @arg @ref LL_HSEM_SEMAPHORE_27
00754   *         @arg @ref LL_HSEM_SEMAPHORE_28
00755   *         @arg @ref LL_HSEM_SEMAPHORE_29
00756   *         @arg @ref LL_HSEM_SEMAPHORE_30
00757   *         @arg @ref LL_HSEM_SEMAPHORE_31
00758   *         @arg @ref LL_HSEM_SEMAPHORE_ALL
00759   * @retval None
00760   */
00761 __STATIC_INLINE void LL_HSEM_ClearFlag_C2ICR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
00762 {
00763   WRITE_REG(HSEMx->C2ICR, SemaphoreMask);
00764 }
00765
00766 /**
00767   * @brief  Get interrupt status from ISR register.
00768   * @rmtoll C2ISR         ISEM          LL_HSEM_IsActiveFlag_C2ISR
00769   * @param  HSEMx HSEM Instance.
00770   * @param  SemaphoreMask This parameter can be a combination of the following values:
00771   *         @arg @ref LL_HSEM_SEMAPHORE_0
00772   *         @arg @ref LL_HSEM_SEMAPHORE_1
00773   *         @arg @ref LL_HSEM_SEMAPHORE_2
00774   *         @arg @ref LL_HSEM_SEMAPHORE_3
00775   *         @arg @ref LL_HSEM_SEMAPHORE_4
00776   *         @arg @ref LL_HSEM_SEMAPHORE_5
00777   *         @arg @ref LL_HSEM_SEMAPHORE_6
00778   *         @arg @ref LL_HSEM_SEMAPHORE_7
00779   *         @arg @ref LL_HSEM_SEMAPHORE_8
00780   *         @arg @ref LL_HSEM_SEMAPHORE_9
00781   *         @arg @ref LL_HSEM_SEMAPHORE_10
00782   *         @arg @ref LL_HSEM_SEMAPHORE_11
00783   *         @arg @ref LL_HSEM_SEMAPHORE_12
00784   *         @arg @ref LL_HSEM_SEMAPHORE_13
00785   *         @arg @ref LL_HSEM_SEMAPHORE_14
00786   *         @arg @ref LL_HSEM_SEMAPHORE_15
00787   *         @arg @ref LL_HSEM_SEMAPHORE_16
00788   *         @arg @ref LL_HSEM_SEMAPHORE_17
00789   *         @arg @ref LL_HSEM_SEMAPHORE_18
00790   *         @arg @ref LL_HSEM_SEMAPHORE_19
00791   *         @arg @ref LL_HSEM_SEMAPHORE_20
00792   *         @arg @ref LL_HSEM_SEMAPHORE_21
00793   *         @arg @ref LL_HSEM_SEMAPHORE_22
00794   *         @arg @ref LL_HSEM_SEMAPHORE_23
00795   *         @arg @ref LL_HSEM_SEMAPHORE_24
00796   *         @arg @ref LL_HSEM_SEMAPHORE_25
00797   *         @arg @ref LL_HSEM_SEMAPHORE_26
00798   *         @arg @ref LL_HSEM_SEMAPHORE_27
00799   *         @arg @ref LL_HSEM_SEMAPHORE_28
00800   *         @arg @ref LL_HSEM_SEMAPHORE_29
00801   *         @arg @ref LL_HSEM_SEMAPHORE_30
00802   *         @arg @ref LL_HSEM_SEMAPHORE_31
00803   *         @arg @ref LL_HSEM_SEMAPHORE_ALL
00804   * @retval State of bit (1 or 0).
00805   */
00806 __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
00807 {
00808   return ((READ_BIT(HSEMx->C2ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
00809 }
00810
00811 /**
00812   * @brief  Get interrupt status from MISR register.
00813   * @rmtoll C2MISR        ISEM          LL_HSEM_IsActiveFlag_C2MISR
00814   * @param  HSEMx HSEM Instance.
00815   * @param  SemaphoreMask This parameter can be a combination of the following values:
00816   *         @arg @ref LL_HSEM_SEMAPHORE_0
00817   *         @arg @ref LL_HSEM_SEMAPHORE_1
00818   *         @arg @ref LL_HSEM_SEMAPHORE_2
00819   *         @arg @ref LL_HSEM_SEMAPHORE_3
00820   *         @arg @ref LL_HSEM_SEMAPHORE_4
00821   *         @arg @ref LL_HSEM_SEMAPHORE_5
00822   *         @arg @ref LL_HSEM_SEMAPHORE_6
00823   *         @arg @ref LL_HSEM_SEMAPHORE_7
00824   *         @arg @ref LL_HSEM_SEMAPHORE_8
00825   *         @arg @ref LL_HSEM_SEMAPHORE_9
00826   *         @arg @ref LL_HSEM_SEMAPHORE_10
00827   *         @arg @ref LL_HSEM_SEMAPHORE_11
00828   *         @arg @ref LL_HSEM_SEMAPHORE_12
00829   *         @arg @ref LL_HSEM_SEMAPHORE_13
00830   *         @arg @ref LL_HSEM_SEMAPHORE_14
00831   *         @arg @ref LL_HSEM_SEMAPHORE_15
00832   *         @arg @ref LL_HSEM_SEMAPHORE_16
00833   *         @arg @ref LL_HSEM_SEMAPHORE_17
00834   *         @arg @ref LL_HSEM_SEMAPHORE_18
00835   *         @arg @ref LL_HSEM_SEMAPHORE_19
00836   *         @arg @ref LL_HSEM_SEMAPHORE_20
00837   *         @arg @ref LL_HSEM_SEMAPHORE_21
00838   *         @arg @ref LL_HSEM_SEMAPHORE_22
00839   *         @arg @ref LL_HSEM_SEMAPHORE_23
00840   *         @arg @ref LL_HSEM_SEMAPHORE_24
00841   *         @arg @ref LL_HSEM_SEMAPHORE_25
00842   *         @arg @ref LL_HSEM_SEMAPHORE_26
00843   *         @arg @ref LL_HSEM_SEMAPHORE_27
00844   *         @arg @ref LL_HSEM_SEMAPHORE_28
00845   *         @arg @ref LL_HSEM_SEMAPHORE_29
00846   *         @arg @ref LL_HSEM_SEMAPHORE_30
00847   *         @arg @ref LL_HSEM_SEMAPHORE_31
00848   *         @arg @ref LL_HSEM_SEMAPHORE_ALL
00849   * @retval State of bit (1 or 0).
00850   */
00851 __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
00852 {
00853   return ((READ_BIT(HSEMx->C2MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
00854 }
00855 /**
00856   * @}
00857   */
00858
00859 /**
00860   * @}
00861   */
00862
00863 /**
00864   * @}
00865   */
00866
00867 #endif /* defined(HSEM) */
00868
00869 /**
00870   * @}
00871   */
00872
00873 #ifdef __cplusplus
00874 }
00875 #endif
00876
00877 #endif /* __STM32WBxx_LL_HSEM_H */
00878
00879 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_i2c.c Source File

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stm32wbxx_ll_i2c.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_i2c.c
00004   * @author  MCD Application Team
00005   * @brief   I2C LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32wbxx_ll_i2c.h"
00023 #include "stm32wbxx_ll_bus.h"
00024 #ifdef  USE_FULL_ASSERT
00025 #include "stm32_assert.h"
00026 #else
00027 #define assert_param(expr) ((void)0U)
00028 #endif
00029
00030 /** @addtogroup STM32WBxx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined (I2C1) || defined (I2C3)
00035
00036 /** @defgroup I2C_LL I2C
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /* Private macros ------------------------------------------------------------*/
00044 /** @addtogroup I2C_LL_Private_Macros
00045   * @{
00046   */
00047
00048 #define IS_LL_I2C_PERIPHERAL_MODE(__VALUE__)    (((__VALUE__) == LL_I2C_MODE_I2C)          || \
00049                                                  ((__VALUE__) == LL_I2C_MODE_SMBUS_HOST)   || \
00050                                                  ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \
00051                                                  ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP))
00052
00053 #define IS_LL_I2C_ANALOG_FILTER(__VALUE__)      (((__VALUE__) == LL_I2C_ANALOGFILTER_ENABLE) || \
00054                                                  ((__VALUE__) == LL_I2C_ANALOGFILTER_DISABLE))
00055
00056 #define IS_LL_I2C_DIGITAL_FILTER(__VALUE__)     ((__VALUE__) <= 0x0000000FU)
00057
00058 #define IS_LL_I2C_OWN_ADDRESS1(__VALUE__)       ((__VALUE__) <= 0x000003FFU)
00059
00060 #define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__)   (((__VALUE__) == LL_I2C_ACK) || \
00061                                                  ((__VALUE__) == LL_I2C_NACK))
00062
00063 #define IS_LL_I2C_OWN_ADDRSIZE(__VALUE__)       (((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \
00064                                                  ((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT))
00065 /**
00066   * @}
00067   */
00068
00069 /* Private function prototypes -----------------------------------------------*/
00070
00071 /* Exported functions --------------------------------------------------------*/
00072 /** @addtogroup I2C_LL_Exported_Functions
00073   * @{
00074   */
00075
00076 /** @addtogroup I2C_LL_EF_Init
00077   * @{
00078   */
00079
00080 /**
00081   * @brief  De-initialize the I2C registers to their default reset values.
00082   * @param  I2Cx I2C Instance.
00083   * @retval An ErrorStatus enumeration value:
00084   *          - SUCCESS: I2C registers are de-initialized
00085   *          - ERROR: I2C registers are not de-initialized
00086   */
00087 ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx)
00088 {
00089   ErrorStatus status = SUCCESS;
00090
00091   /* Check the I2C Instance I2Cx */
00092   assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
00093
00094   if (I2Cx == I2C1)
00095   {
00096     /* Force reset of I2C clock */
00097     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1);
00098
00099     /* Release reset of I2C clock */
00100     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1);
00101   }
00102 #if defined(I2C3)
00103   else if (I2Cx == I2C3)
00104   {
00105     /* Force reset of I2C clock */
00106     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3);
00107
00108     /* Release reset of I2C clock */
00109     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3);
00110   }
00111 #endif
00112   else
00113   {
00114     status = ERROR;
00115   }
00116
00117   return status;
00118 }
00119
00120 /**
00121   * @brief  Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
00122   * @param  I2Cx I2C Instance.
00123   * @param  I2C_InitStruct pointer to a @ref LL_I2C_InitTypeDef structure.
00124   * @retval An ErrorStatus enumeration value:
00125   *          - SUCCESS: I2C registers are initialized
00126   *          - ERROR: Not applicable
00127   */
00128 ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
00129 {
00130   /* Check the I2C Instance I2Cx */
00131   assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
00132
00133   /* Check the I2C parameters from I2C_InitStruct */
00134   assert_param(IS_LL_I2C_PERIPHERAL_MODE(I2C_InitStruct->PeripheralMode));
00135   assert_param(IS_LL_I2C_ANALOG_FILTER(I2C_InitStruct->AnalogFilter));
00136   assert_param(IS_LL_I2C_DIGITAL_FILTER(I2C_InitStruct->DigitalFilter));
00137   assert_param(IS_LL_I2C_OWN_ADDRESS1(I2C_InitStruct->OwnAddress1));
00138   assert_param(IS_LL_I2C_TYPE_ACKNOWLEDGE(I2C_InitStruct->TypeAcknowledge));
00139   assert_param(IS_LL_I2C_OWN_ADDRSIZE(I2C_InitStruct->OwnAddrSize));
00140
00141   /* Disable the selected I2Cx Peripheral */
00142   LL_I2C_Disable(I2Cx);
00143
00144   /*---------------------------- I2Cx CR1 Configuration ------------------------
00145    * Configure the analog and digital noise filters with parameters :
00146    * - AnalogFilter: I2C_CR1_ANFOFF bit
00147    * - DigitalFilter: I2C_CR1_DNF[3:0] bits
00148    */
00149   LL_I2C_ConfigFilters(I2Cx, I2C_InitStruct->AnalogFilter, I2C_InitStruct->DigitalFilter);
00150
00151   /*---------------------------- I2Cx TIMINGR Configuration --------------------
00152    * Configure the SDA setup, hold time and the SCL high, low period with parameter :
00153    * - Timing: I2C_TIMINGR_PRESC[3:0], I2C_TIMINGR_SCLDEL[3:0], I2C_TIMINGR_SDADEL[3:0],
00154    *           I2C_TIMINGR_SCLH[7:0] and I2C_TIMINGR_SCLL[7:0] bits
00155    */
00156   LL_I2C_SetTiming(I2Cx, I2C_InitStruct->Timing);
00157
00158   /* Enable the selected I2Cx Peripheral */
00159   LL_I2C_Enable(I2Cx);
00160
00161   /*---------------------------- I2Cx OAR1 Configuration -----------------------
00162    * Disable, Configure and Enable I2Cx device own address 1 with parameters :
00163    * - OwnAddress1:  I2C_OAR1_OA1[9:0] bits
00164    * - OwnAddrSize:  I2C_OAR1_OA1MODE bit
00165    */
00166   LL_I2C_DisableOwnAddress1(I2Cx);
00167   LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize);
00168
00169   /* OwnAdress1 == 0 is reserved for General Call address */
00170   if (I2C_InitStruct->OwnAddress1 != 0U)
00171   {
00172     LL_I2C_EnableOwnAddress1(I2Cx);
00173   }
00174
00175   /*---------------------------- I2Cx MODE Configuration -----------------------
00176   * Configure I2Cx peripheral mode with parameter :
00177    * - PeripheralMode: I2C_CR1_SMBDEN and I2C_CR1_SMBHEN bits
00178    */
00179   LL_I2C_SetMode(I2Cx, I2C_InitStruct->PeripheralMode);
00180
00181   /*---------------------------- I2Cx CR2 Configuration ------------------------
00182    * Configure the ACKnowledge or Non ACKnowledge condition
00183    * after the address receive match code or next received byte with parameter :
00184    * - TypeAcknowledge: I2C_CR2_NACK bit
00185    */
00186   LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge);
00187
00188   return SUCCESS;
00189 }
00190
00191 /**
00192   * @brief  Set each @ref LL_I2C_InitTypeDef field to default value.
00193   * @param  I2C_InitStruct Pointer to a @ref LL_I2C_InitTypeDef structure.
00194   * @retval None
00195   */
00196 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct)
00197 {
00198   /* Set I2C_InitStruct fields to default values */
00199   I2C_InitStruct->PeripheralMode  = LL_I2C_MODE_I2C;
00200   I2C_InitStruct->Timing          = 0U;
00201   I2C_InitStruct->AnalogFilter    = LL_I2C_ANALOGFILTER_ENABLE;
00202   I2C_InitStruct->DigitalFilter   = 0U;
00203   I2C_InitStruct->OwnAddress1     = 0U;
00204   I2C_InitStruct->TypeAcknowledge = LL_I2C_NACK;
00205   I2C_InitStruct->OwnAddrSize     = LL_I2C_OWNADDRESS1_7BIT;
00206 }
00207
00208 /**
00209   * @}
00210   */
00211
00212 /**
00213   * @}
00214   */
00215
00216 /**
00217   * @}
00218   */
00219
00220 #endif /* I2C1 || I2C3 */
00221
00222 /**
00223   * @}
00224   */
00225
00226 #endif /* USE_FULL_LL_DRIVER */
00227
00228 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_i2c.h Source File

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stm32wbxx_ll_i2c.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_i2c.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of I2C LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_LL_I2C_H
00022 #define STM32WBxx_LL_I2C_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx.h"
00030
00031 /** @addtogroup STM32WBxx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (I2C1) || defined (I2C3)
00036
00037 /** @defgroup I2C_LL I2C
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043
00044 /* Private constants ---------------------------------------------------------*/
00045 /** @defgroup I2C_LL_Private_Constants I2C Private Constants
00046   * @{
00047   */
00048 /**
00049   * @}
00050   */
00051
00052 /* Private macros ------------------------------------------------------------*/
00053 #if defined(USE_FULL_LL_DRIVER)
00054 /** @defgroup I2C_LL_Private_Macros I2C Private Macros
00055   * @{
00056   */
00057 /**
00058   * @}
00059   */
00060 #endif /*USE_FULL_LL_DRIVER*/
00061
00062 /* Exported types ------------------------------------------------------------*/
00063 #if defined(USE_FULL_LL_DRIVER)
00064 /** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
00065   * @{
00066   */
00067 typedef struct
00068 {
00069   uint32_t PeripheralMode;      /*!< Specifies the peripheral mode.
00070                                      This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
00071
00072                                      This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
00073
00074   uint32_t Timing;              /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
00075                                      This parameter must be set by referring to the STM32CubeMX Tool and
00076                                      the helper macro @ref __LL_I2C_CONVERT_TIMINGS()
00077
00078                                      This feature can be modified afterwards using unitary function @ref LL_I2C_SetTiming(). */
00079
00080   uint32_t AnalogFilter;        /*!< Enables or disables analog noise filter.
00081                                      This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION
00082
00083                                      This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
00084
00085   uint32_t DigitalFilter;       /*!< Configures the digital noise filter.
00086                                      This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F
00087
00088                                      This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */
00089
00090   uint32_t OwnAddress1;         /*!< Specifies the device own address 1.
00091                                      This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
00092
00093                                      This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
00094
00095   uint32_t TypeAcknowledge;     /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
00096                                      This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
00097
00098                                      This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
00099
00100   uint32_t OwnAddrSize;         /*!< Specifies the device own address 1 size (7-bit or 10-bit).
00101                                      This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
00102
00103                                      This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
00104 } LL_I2C_InitTypeDef;
00105 /**
00106   * @}
00107   */
00108 #endif /*USE_FULL_LL_DRIVER*/
00109
00110 /* Exported constants --------------------------------------------------------*/
00111 /** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
00112   * @{
00113   */
00114
00115 /** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
00116   * @brief    Flags defines which can be used with LL_I2C_WriteReg function
00117   * @{
00118   */
00119 #define LL_I2C_ICR_ADDRCF                   I2C_ICR_ADDRCF          /*!< Address Matched flag   */
00120 #define LL_I2C_ICR_NACKCF                   I2C_ICR_NACKCF          /*!< Not Acknowledge flag   */
00121 #define LL_I2C_ICR_STOPCF                   I2C_ICR_STOPCF          /*!< Stop detection flag    */
00122 #define LL_I2C_ICR_BERRCF                   I2C_ICR_BERRCF          /*!< Bus error flag         */
00123 #define LL_I2C_ICR_ARLOCF                   I2C_ICR_ARLOCF          /*!< Arbitration Lost flag  */
00124 #define LL_I2C_ICR_OVRCF                    I2C_ICR_OVRCF           /*!< Overrun/Underrun flag  */
00125 #define LL_I2C_ICR_PECCF                    I2C_ICR_PECCF           /*!< PEC error flag         */
00126 #define LL_I2C_ICR_TIMOUTCF                 I2C_ICR_TIMOUTCF        /*!< Timeout detection flag */
00127 #define LL_I2C_ICR_ALERTCF                  I2C_ICR_ALERTCF         /*!< Alert flag             */
00128 /**
00129   * @}
00130   */
00131
00132 /** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
00133   * @brief    Flags defines which can be used with LL_I2C_ReadReg function
00134   * @{
00135   */
00136 #define LL_I2C_ISR_TXE                      I2C_ISR_TXE             /*!< Transmit data register empty        */
00137 #define LL_I2C_ISR_TXIS                     I2C_ISR_TXIS            /*!< Transmit interrupt status           */
00138 #define LL_I2C_ISR_RXNE                     I2C_ISR_RXNE            /*!< Receive data register not empty     */
00139 #define LL_I2C_ISR_ADDR                     I2C_ISR_ADDR            /*!< Address matched (slave mode)        */
00140 #define LL_I2C_ISR_NACKF                    I2C_ISR_NACKF           /*!< Not Acknowledge received flag       */
00141 #define LL_I2C_ISR_STOPF                    I2C_ISR_STOPF           /*!< Stop detection flag                 */
00142 #define LL_I2C_ISR_TC                       I2C_ISR_TC              /*!< Transfer Complete (master mode)     */
00143 #define LL_I2C_ISR_TCR                      I2C_ISR_TCR             /*!< Transfer Complete Reload            */
00144 #define LL_I2C_ISR_BERR                     I2C_ISR_BERR            /*!< Bus error                           */
00145 #define LL_I2C_ISR_ARLO                     I2C_ISR_ARLO            /*!< Arbitration lost                    */
00146 #define LL_I2C_ISR_OVR                      I2C_ISR_OVR             /*!< Overrun/Underrun (slave mode)       */
00147 #define LL_I2C_ISR_PECERR                   I2C_ISR_PECERR          /*!< PEC Error in reception (SMBus mode) */
00148 #define LL_I2C_ISR_TIMEOUT                  I2C_ISR_TIMEOUT         /*!< Timeout detection flag (SMBus mode) */
00149 #define LL_I2C_ISR_ALERT                    I2C_ISR_ALERT           /*!< SMBus alert (SMBus mode)            */
00150 #define LL_I2C_ISR_BUSY                     I2C_ISR_BUSY            /*!< Bus busy                            */
00151 /**
00152   * @}
00153   */
00154
00155 /** @defgroup I2C_LL_EC_IT IT Defines
00156   * @brief    IT defines which can be used with LL_I2C_ReadReg and  LL_I2C_WriteReg functions
00157   * @{
00158   */
00159 #define LL_I2C_CR1_TXIE                     I2C_CR1_TXIE            /*!< TX Interrupt enable                         */
00160 #define LL_I2C_CR1_RXIE                     I2C_CR1_RXIE            /*!< RX Interrupt enable                         */
00161 #define LL_I2C_CR1_ADDRIE                   I2C_CR1_ADDRIE          /*!< Address match Interrupt enable (slave only) */
00162 #define LL_I2C_CR1_NACKIE                   I2C_CR1_NACKIE          /*!< Not acknowledge received Interrupt enable   */
00163 #define LL_I2C_CR1_STOPIE                   I2C_CR1_STOPIE          /*!< STOP detection Interrupt enable             */
00164 #define LL_I2C_CR1_TCIE                     I2C_CR1_TCIE            /*!< Transfer Complete interrupt enable          */
00165 #define LL_I2C_CR1_ERRIE                    I2C_CR1_ERRIE           /*!< Error interrupts enable                     */
00166 /**
00167   * @}
00168   */
00169
00170 /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
00171   * @{
00172   */
00173 #define LL_I2C_MODE_I2C                    0x00000000U              /*!< I2C Master or Slave mode                                    */
00174 #define LL_I2C_MODE_SMBUS_HOST             I2C_CR1_SMBHEN           /*!< SMBus Host address acknowledge                              */
00175 #define LL_I2C_MODE_SMBUS_DEVICE           0x00000000U              /*!< SMBus Device default mode (Default address not acknowledge) */
00176 #define LL_I2C_MODE_SMBUS_DEVICE_ARP       I2C_CR1_SMBDEN           /*!< SMBus Device Default address acknowledge                    */
00177 /**
00178   * @}
00179   */
00180
00181 /** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
00182   * @{
00183   */
00184 #define LL_I2C_ANALOGFILTER_ENABLE          0x00000000U             /*!< Analog filter is enabled.  */
00185 #define LL_I2C_ANALOGFILTER_DISABLE         I2C_CR1_ANFOFF          /*!< Analog filter is disabled. */
00186 /**
00187   * @}
00188   */
00189
00190 /** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
00191   * @{
00192   */
00193 #define LL_I2C_ADDRESSING_MODE_7BIT         0x00000000U              /*!< Master operates in 7-bit addressing mode. */
00194 #define LL_I2C_ADDRESSING_MODE_10BIT        I2C_CR2_ADD10            /*!< Master operates in 10-bit addressing mode.*/
00195 /**
00196   * @}
00197   */
00198
00199 /** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
00200   * @{
00201   */
00202 #define LL_I2C_OWNADDRESS1_7BIT             0x00000000U             /*!< Own address 1 is a 7-bit address. */
00203 #define LL_I2C_OWNADDRESS1_10BIT            I2C_OAR1_OA1MODE        /*!< Own address 1 is a 10-bit address.*/
00204 /**
00205   * @}
00206   */
00207
00208 /** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
00209   * @{
00210   */
00211 #define LL_I2C_OWNADDRESS2_NOMASK           I2C_OAR2_OA2NOMASK      /*!< Own Address2 No mask.                                */
00212 #define LL_I2C_OWNADDRESS2_MASK01           I2C_OAR2_OA2MASK01      /*!< Only Address2 bits[7:2] are compared.                */
00213 #define LL_I2C_OWNADDRESS2_MASK02           I2C_OAR2_OA2MASK02      /*!< Only Address2 bits[7:3] are compared.                */
00214 #define LL_I2C_OWNADDRESS2_MASK03           I2C_OAR2_OA2MASK03      /*!< Only Address2 bits[7:4] are compared.                */
00215 #define LL_I2C_OWNADDRESS2_MASK04           I2C_OAR2_OA2MASK04      /*!< Only Address2 bits[7:5] are compared.                */
00216 #define LL_I2C_OWNADDRESS2_MASK05           I2C_OAR2_OA2MASK05      /*!< Only Address2 bits[7:6] are compared.                */
00217 #define LL_I2C_OWNADDRESS2_MASK06           I2C_OAR2_OA2MASK06      /*!< Only Address2 bits[7] are compared.                  */
00218 #define LL_I2C_OWNADDRESS2_MASK07           I2C_OAR2_OA2MASK07      /*!< No comparison is done. All Address2 are acknowledged.*/
00219 /**
00220   * @}
00221   */
00222
00223 /** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
00224   * @{
00225   */
00226 #define LL_I2C_ACK                          0x00000000U              /*!< ACK is sent after current received byte. */
00227 #define LL_I2C_NACK                         I2C_CR2_NACK             /*!< NACK is sent after current received byte.*/
00228 /**
00229   * @}
00230   */
00231
00232 /** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
00233   * @{
00234   */
00235 #define LL_I2C_ADDRSLAVE_7BIT               0x00000000U              /*!< Slave Address in 7-bit. */
00236 #define LL_I2C_ADDRSLAVE_10BIT              I2C_CR2_ADD10            /*!< Slave Address in 10-bit.*/
00237 /**
00238   * @}
00239   */
00240
00241 /** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
00242   * @{
00243   */
00244 #define LL_I2C_REQUEST_WRITE                0x00000000U              /*!< Master request a write transfer. */
00245 #define LL_I2C_REQUEST_READ                 I2C_CR2_RD_WRN           /*!< Master request a read transfer.  */
00246 /**
00247   * @}
00248   */
00249
00250 /** @defgroup I2C_LL_EC_MODE Transfer End Mode
00251   * @{
00252   */
00253 #define LL_I2C_MODE_RELOAD                  I2C_CR2_RELOAD                                      /*!< Enable I2C Reload mode.                                   */
00254 #define LL_I2C_MODE_AUTOEND                 I2C_CR2_AUTOEND                                     /*!< Enable I2C Automatic end mode with no HW PEC comparison.  */
00255 #define LL_I2C_MODE_SOFTEND                 0x00000000U                                         /*!< Enable I2C Software end mode with no HW PEC comparison.   */
00256 #define LL_I2C_MODE_SMBUS_RELOAD            LL_I2C_MODE_RELOAD                                  /*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */
00257 #define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC    LL_I2C_MODE_AUTOEND                                 /*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */
00258 #define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC    LL_I2C_MODE_SOFTEND                                 /*!< Enable SMBUS Software end mode with HW PEC comparison.    */
00259 #define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)   /*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */
00260 #define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)   /*!< Enable SMBUS Software end mode with HW PEC comparison.    */
00261 /**
00262   * @}
00263   */
00264
00265 /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
00266   * @{
00267   */
00268 #define LL_I2C_GENERATE_NOSTARTSTOP         0x00000000U                                                                /*!< Don't Generate Stop and Start condition.                */
00269 #define LL_I2C_GENERATE_STOP                (uint32_t)(0x80000000U | I2C_CR2_STOP)                                     /*!< Generate Stop condition (Size should be set to 0).      */
00270 #define LL_I2C_GENERATE_START_READ          (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)                   /*!< Generate Start for read request.                        */
00271 #define LL_I2C_GENERATE_START_WRITE         (uint32_t)(0x80000000U | I2C_CR2_START)                                    /*!< Generate Start for write request.                       */
00272 #define LL_I2C_GENERATE_RESTART_7BIT_READ   (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)                   /*!< Generate Restart for read request, slave 7Bit address.  */
00273 #define LL_I2C_GENERATE_RESTART_7BIT_WRITE  (uint32_t)(0x80000000U | I2C_CR2_START)                                    /*!< Generate Restart for write request, slave 7Bit address. */
00274 #define LL_I2C_GENERATE_RESTART_10BIT_READ  (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */
00275 #define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)                                    /*!< Generate Restart for write request, slave 10Bit address.*/
00276 /**
00277   * @}
00278   */
00279
00280 /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
00281   * @{
00282   */
00283 #define LL_I2C_DIRECTION_WRITE              0x00000000U              /*!< Write transfer request by master, slave enters receiver mode.  */
00284 #define LL_I2C_DIRECTION_READ               I2C_ISR_DIR              /*!< Read transfer request by master, slave enters transmitter mode.*/
00285 /**
00286   * @}
00287   */
00288
00289 /** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
00290   * @{
00291   */
00292 #define LL_I2C_DMA_REG_DATA_TRANSMIT        0x00000000U              /*!< Get address of data register used for transmission */
00293 #define LL_I2C_DMA_REG_DATA_RECEIVE         0x00000001U              /*!< Get address of data register used for reception */
00294 /**
00295   * @}
00296   */
00297
00298 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
00299   * @{
00300   */
00301 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW      0x00000000U          /*!< TimeoutA is used to detect SCL low level timeout.              */
00302 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE   /*!< TimeoutA is used to detect both SCL and SDA high level timeout.*/
00303 /**
00304   * @}
00305   */
00306
00307 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
00308   * @{
00309   */
00310 #define LL_I2C_SMBUS_TIMEOUTA               I2C_TIMEOUTR_TIMOUTEN                                   /*!< TimeoutA enable bit                                */
00311 #define LL_I2C_SMBUS_TIMEOUTB               I2C_TIMEOUTR_TEXTEN                                     /*!< TimeoutB (extended clock) enable bit               */
00312 #define LL_I2C_SMBUS_ALL_TIMEOUT            (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB (extended clock) enable bits */
00313 /**
00314   * @}
00315   */
00316
00317 /**
00318   * @}
00319   */
00320
00321 /* Exported macro ------------------------------------------------------------*/
00322 /** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
00323   * @{
00324   */
00325
00326 /** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
00327   * @{
00328   */
00329
00330 /**
00331   * @brief  Write a value in I2C register
00332   * @param  __INSTANCE__ I2C Instance
00333   * @param  __REG__ Register to be written
00334   * @param  __VALUE__ Value to be written in the register
00335   * @retval None
00336   */
00337 #define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00338
00339 /**
00340   * @brief  Read a value in I2C register
00341   * @param  __INSTANCE__ I2C Instance
00342   * @param  __REG__ Register to be read
00343   * @retval Register value
00344   */
00345 #define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00346 /**
00347   * @}
00348   */
00349
00350 /** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
00351   * @{
00352   */
00353 /**
00354   * @brief  Configure the SDA setup, hold time and the SCL high, low period.
00355   * @param  __PRESCALER__ This parameter must be a value between  Min_Data=0 and Max_Data=0xF.
00356   * @param  __DATA_SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc)
00357   * @param  __DATA_HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc)
00358   * @param  __CLOCK_HIGH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc)
00359   * @param  __CLOCK_LOW_PERIOD__ This parameter must be a value between  Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc)
00360   * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
00361   */
00362 #define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__)   \
00363         ((((uint32_t)(__PRESCALER__)         << I2C_TIMINGR_PRESC_Pos)  & I2C_TIMINGR_PRESC)   | \
00364          (((uint32_t)(__DATA_SETUP_TIME__)   << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL)  | \
00365          (((uint32_t)(__DATA_HOLD_TIME__)    << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL)  | \
00366          (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos)   & I2C_TIMINGR_SCLH)    | \
00367          (((uint32_t)(__CLOCK_LOW_PERIOD__)  << I2C_TIMINGR_SCLL_Pos)   & I2C_TIMINGR_SCLL))
00368 /**
00369   * @}
00370   */
00371
00372 /**
00373   * @}
00374   */
00375
00376 /* Exported functions --------------------------------------------------------*/
00377 /** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
00378   * @{
00379   */
00380
00381 /** @defgroup I2C_LL_EF_Configuration Configuration
00382   * @{
00383   */
00384
00385 /**
00386   * @brief  Enable I2C peripheral (PE = 1).
00387   * @rmtoll CR1          PE            LL_I2C_Enable
00388   * @param  I2Cx I2C Instance.
00389   * @retval None
00390   */
00391 __STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
00392 {
00393   SET_BIT(I2Cx->CR1, I2C_CR1_PE);
00394 }
00395
00396 /**
00397   * @brief  Disable I2C peripheral (PE = 0).
00398   * @note   When PE = 0, the I2C SCL and SDA lines are released.
00399   *         Internal state machines and status bits are put back to their reset value.
00400   *         When cleared, PE must be kept low for at least 3 APB clock cycles.
00401   * @rmtoll CR1          PE            LL_I2C_Disable
00402   * @param  I2Cx I2C Instance.
00403   * @retval None
00404   */
00405 __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
00406 {
00407   CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
00408 }
00409
00410 /**
00411   * @brief  Check if the I2C peripheral is enabled or disabled.
00412   * @rmtoll CR1          PE            LL_I2C_IsEnabled
00413   * @param  I2Cx I2C Instance.
00414   * @retval State of bit (1 or 0).
00415   */
00416 __STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
00417 {
00418   return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL);
00419 }
00420
00421 /**
00422   * @brief  Configure Noise Filters (Analog and Digital).
00423   * @note   If the analog filter is also enabled, the digital filter is added to analog filter.
00424   *         The filters can only be programmed when the I2C is disabled (PE = 0).
00425   * @rmtoll CR1          ANFOFF        LL_I2C_ConfigFilters\n
00426   *         CR1          DNF           LL_I2C_ConfigFilters
00427   * @param  I2Cx I2C Instance.
00428   * @param  AnalogFilter This parameter can be one of the following values:
00429   *         @arg @ref LL_I2C_ANALOGFILTER_ENABLE
00430   *         @arg @ref LL_I2C_ANALOGFILTER_DISABLE
00431   * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
00432   *         This parameter is used to configure the digital noise filter on SDA and SCL input.
00433   *         The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
00434   * @retval None
00435   */
00436 __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
00437 {
00438   MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos));
00439 }
00440
00441 /**
00442   * @brief  Configure Digital Noise Filter.
00443   * @note   If the analog filter is also enabled, the digital filter is added to analog filter.
00444   *         This filter can only be programmed when the I2C is disabled (PE = 0).
00445   * @rmtoll CR1          DNF           LL_I2C_SetDigitalFilter
00446   * @param  I2Cx I2C Instance.
00447   * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
00448   *         This parameter is used to configure the digital noise filter on SDA and SCL input.
00449   *         The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
00450   * @retval None
00451   */
00452 __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
00453 {
00454   MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);
00455 }
00456
00457 /**
00458   * @brief  Get the current Digital Noise Filter configuration.
00459   * @rmtoll CR1          DNF           LL_I2C_GetDigitalFilter
00460   * @param  I2Cx I2C Instance.
00461   * @retval Value between Min_Data=0x0 and Max_Data=0xF
00462   */
00463 __STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
00464 {
00465   return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
00466 }
00467
00468 /**
00469   * @brief  Enable Analog Noise Filter.
00470   * @note   This filter can only be programmed when the I2C is disabled (PE = 0).
00471   * @rmtoll CR1          ANFOFF        LL_I2C_EnableAnalogFilter
00472   * @param  I2Cx I2C Instance.
00473   * @retval None
00474   */
00475 __STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
00476 {
00477   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
00478 }
00479
00480 /**
00481   * @brief  Disable Analog Noise Filter.
00482   * @note   This filter can only be programmed when the I2C is disabled (PE = 0).
00483   * @rmtoll CR1          ANFOFF        LL_I2C_DisableAnalogFilter
00484   * @param  I2Cx I2C Instance.
00485   * @retval None
00486   */
00487 __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
00488 {
00489   SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
00490 }
00491
00492 /**
00493   * @brief  Check if Analog Noise Filter is enabled or disabled.
00494   * @rmtoll CR1          ANFOFF        LL_I2C_IsEnabledAnalogFilter
00495   * @param  I2Cx I2C Instance.
00496   * @retval State of bit (1 or 0).
00497   */
00498 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
00499 {
00500   return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL);
00501 }
00502
00503 /**
00504   * @brief  Enable DMA transmission requests.
00505   * @rmtoll CR1          TXDMAEN       LL_I2C_EnableDMAReq_TX
00506   * @param  I2Cx I2C Instance.
00507   * @retval None
00508   */
00509 __STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
00510 {
00511   SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
00512 }
00513
00514 /**
00515   * @brief  Disable DMA transmission requests.
00516   * @rmtoll CR1          TXDMAEN       LL_I2C_DisableDMAReq_TX
00517   * @param  I2Cx I2C Instance.
00518   * @retval None
00519   */
00520 __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
00521 {
00522   CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
00523 }
00524
00525 /**
00526   * @brief  Check if DMA transmission requests are enabled or disabled.
00527   * @rmtoll CR1          TXDMAEN       LL_I2C_IsEnabledDMAReq_TX
00528   * @param  I2Cx I2C Instance.
00529   * @retval State of bit (1 or 0).
00530   */
00531 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
00532 {
00533   return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL);
00534 }
00535
00536 /**
00537   * @brief  Enable DMA reception requests.
00538   * @rmtoll CR1          RXDMAEN       LL_I2C_EnableDMAReq_RX
00539   * @param  I2Cx I2C Instance.
00540   * @retval None
00541   */
00542 __STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
00543 {
00544   SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
00545 }
00546
00547 /**
00548   * @brief  Disable DMA reception requests.
00549   * @rmtoll CR1          RXDMAEN       LL_I2C_DisableDMAReq_RX
00550   * @param  I2Cx I2C Instance.
00551   * @retval None
00552   */
00553 __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
00554 {
00555   CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
00556 }
00557
00558 /**
00559   * @brief  Check if DMA reception requests are enabled or disabled.
00560   * @rmtoll CR1          RXDMAEN       LL_I2C_IsEnabledDMAReq_RX
00561   * @param  I2Cx I2C Instance.
00562   * @retval State of bit (1 or 0).
00563   */
00564 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
00565 {
00566   return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL);
00567 }
00568
00569 /**
00570   * @brief  Get the data register address used for DMA transfer
00571   * @rmtoll TXDR         TXDATA        LL_I2C_DMA_GetRegAddr\n
00572   *         RXDR         RXDATA        LL_I2C_DMA_GetRegAddr
00573   * @param  I2Cx I2C Instance
00574   * @param  Direction This parameter can be one of the following values:
00575   *         @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
00576   *         @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
00577   * @retval Address of data register
00578   */
00579 __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
00580 {
00581   register uint32_t data_reg_addr;
00582
00583   if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
00584   {
00585     /* return address of TXDR register */
00586     data_reg_addr = (uint32_t) & (I2Cx->TXDR);
00587   }
00588   else
00589   {
00590     /* return address of RXDR register */
00591     data_reg_addr = (uint32_t) & (I2Cx->RXDR);
00592   }
00593
00594   return data_reg_addr;
00595 }
00596
00597 /**
00598   * @brief  Enable Clock stretching.
00599   * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
00600   * @rmtoll CR1          NOSTRETCH     LL_I2C_EnableClockStretching
00601   * @param  I2Cx I2C Instance.
00602   * @retval None
00603   */
00604 __STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
00605 {
00606   CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
00607 }
00608
00609 /**
00610   * @brief  Disable Clock stretching.
00611   * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
00612   * @rmtoll CR1          NOSTRETCH     LL_I2C_DisableClockStretching
00613   * @param  I2Cx I2C Instance.
00614   * @retval None
00615   */
00616 __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
00617 {
00618   SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
00619 }
00620
00621 /**
00622   * @brief  Check if Clock stretching is enabled or disabled.
00623   * @rmtoll CR1          NOSTRETCH     LL_I2C_IsEnabledClockStretching
00624   * @param  I2Cx I2C Instance.
00625   * @retval State of bit (1 or 0).
00626   */
00627 __STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
00628 {
00629   return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
00630 }
00631
00632 /**
00633   * @brief  Enable hardware byte control in slave mode.
00634   * @rmtoll CR1          SBC           LL_I2C_EnableSlaveByteControl
00635   * @param  I2Cx I2C Instance.
00636   * @retval None
00637   */
00638 __STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
00639 {
00640   SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
00641 }
00642
00643 /**
00644   * @brief  Disable hardware byte control in slave mode.
00645   * @rmtoll CR1          SBC           LL_I2C_DisableSlaveByteControl
00646   * @param  I2Cx I2C Instance.
00647   * @retval None
00648   */
00649 __STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
00650 {
00651   CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
00652 }
00653
00654 /**
00655   * @brief  Check if hardware byte control in slave mode is enabled or disabled.
00656   * @rmtoll CR1          SBC           LL_I2C_IsEnabledSlaveByteControl
00657   * @param  I2Cx I2C Instance.
00658   * @retval State of bit (1 or 0).
00659   */
00660 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
00661 {
00662   return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL);
00663 }
00664
00665 /**
00666   * @brief  Enable Wakeup from STOP.
00667   * @note   Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
00668   *         WakeUpFromStop feature is supported by the I2Cx Instance.
00669   * @note   This bit can only be programmed when Digital Filter is disabled.
00670   * @rmtoll CR1          WUPEN         LL_I2C_EnableWakeUpFromStop
00671   * @param  I2Cx I2C Instance.
00672   * @retval None
00673   */
00674 __STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
00675 {
00676   SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
00677 }
00678
00679 /**
00680   * @brief  Disable Wakeup from STOP.
00681   * @note   Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
00682   *         WakeUpFromStop feature is supported by the I2Cx Instance.
00683   * @rmtoll CR1          WUPEN         LL_I2C_DisableWakeUpFromStop
00684   * @param  I2Cx I2C Instance.
00685   * @retval None
00686   */
00687 __STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
00688 {
00689   CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
00690 }
00691
00692 /**
00693   * @brief  Check if Wakeup from STOP is enabled or disabled.
00694   * @note   Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
00695   *         WakeUpFromStop feature is supported by the I2Cx Instance.
00696   * @rmtoll CR1          WUPEN         LL_I2C_IsEnabledWakeUpFromStop
00697   * @param  I2Cx I2C Instance.
00698   * @retval State of bit (1 or 0).
00699   */
00700 __STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx)
00701 {
00702   return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL);
00703 }
00704
00705 /**
00706   * @brief  Enable General Call.
00707   * @note   When enabled the Address 0x00 is ACKed.
00708   * @rmtoll CR1          GCEN          LL_I2C_EnableGeneralCall
00709   * @param  I2Cx I2C Instance.
00710   * @retval None
00711   */
00712 __STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
00713 {
00714   SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
00715 }
00716
00717 /**
00718   * @brief  Disable General Call.
00719   * @note   When disabled the Address 0x00 is NACKed.
00720   * @rmtoll CR1          GCEN          LL_I2C_DisableGeneralCall
00721   * @param  I2Cx I2C Instance.
00722   * @retval None
00723   */
00724 __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
00725 {
00726   CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
00727 }
00728
00729 /**
00730   * @brief  Check if General Call is enabled or disabled.
00731   * @rmtoll CR1          GCEN          LL_I2C_IsEnabledGeneralCall
00732   * @param  I2Cx I2C Instance.
00733   * @retval State of bit (1 or 0).
00734   */
00735 __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
00736 {
00737   return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);
00738 }
00739
00740 /**
00741   * @brief  Configure the Master to operate in 7-bit or 10-bit addressing mode.
00742   * @note   Changing this bit is not allowed, when the START bit is set.
00743   * @rmtoll CR2          ADD10         LL_I2C_SetMasterAddressingMode
00744   * @param  I2Cx I2C Instance.
00745   * @param  AddressingMode This parameter can be one of the following values:
00746   *         @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
00747   *         @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
00748   * @retval None
00749   */
00750 __STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
00751 {
00752   MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
00753 }
00754
00755 /**
00756   * @brief  Get the Master addressing mode.
00757   * @rmtoll CR2          ADD10         LL_I2C_GetMasterAddressingMode
00758   * @param  I2Cx I2C Instance.
00759   * @retval Returned value can be one of the following values:
00760   *         @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
00761   *         @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
00762   */
00763 __STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
00764 {
00765   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
00766 }
00767
00768 /**
00769   * @brief  Set the Own Address1.
00770   * @rmtoll OAR1         OA1           LL_I2C_SetOwnAddress1\n
00771   *         OAR1         OA1MODE       LL_I2C_SetOwnAddress1
00772   * @param  I2Cx I2C Instance.
00773   * @param  OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
00774   * @param  OwnAddrSize This parameter can be one of the following values:
00775   *         @arg @ref LL_I2C_OWNADDRESS1_7BIT
00776   *         @arg @ref LL_I2C_OWNADDRESS1_10BIT
00777   * @retval None
00778   */
00779 __STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
00780 {
00781   MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
00782 }
00783
00784 /**
00785   * @brief  Enable acknowledge on Own Address1 match address.
00786   * @rmtoll OAR1         OA1EN         LL_I2C_EnableOwnAddress1
00787   * @param  I2Cx I2C Instance.
00788   * @retval None
00789   */
00790 __STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
00791 {
00792   SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
00793 }
00794
00795 /**
00796   * @brief  Disable acknowledge on Own Address1 match address.
00797   * @rmtoll OAR1         OA1EN         LL_I2C_DisableOwnAddress1
00798   * @param  I2Cx I2C Instance.
00799   * @retval None
00800   */
00801 __STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
00802 {
00803   CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
00804 }
00805
00806 /**
00807   * @brief  Check if Own Address1 acknowledge is enabled or disabled.
00808   * @rmtoll OAR1         OA1EN         LL_I2C_IsEnabledOwnAddress1
00809   * @param  I2Cx I2C Instance.
00810   * @retval State of bit (1 or 0).
00811   */
00812 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
00813 {
00814   return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL);
00815 }
00816
00817 /**
00818   * @brief  Set the 7bits Own Address2.
00819   * @note   This action has no effect if own address2 is enabled.
00820   * @rmtoll OAR2         OA2           LL_I2C_SetOwnAddress2\n
00821   *         OAR2         OA2MSK        LL_I2C_SetOwnAddress2
00822   * @param  I2Cx I2C Instance.
00823   * @param  OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
00824   * @param  OwnAddrMask This parameter can be one of the following values:
00825   *         @arg @ref LL_I2C_OWNADDRESS2_NOMASK
00826   *         @arg @ref LL_I2C_OWNADDRESS2_MASK01
00827   *         @arg @ref LL_I2C_OWNADDRESS2_MASK02
00828   *         @arg @ref LL_I2C_OWNADDRESS2_MASK03
00829   *         @arg @ref LL_I2C_OWNADDRESS2_MASK04
00830   *         @arg @ref LL_I2C_OWNADDRESS2_MASK05
00831   *         @arg @ref LL_I2C_OWNADDRESS2_MASK06
00832   *         @arg @ref LL_I2C_OWNADDRESS2_MASK07
00833   * @retval None
00834   */
00835 __STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
00836 {
00837   MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
00838 }
00839
00840 /**
00841   * @brief  Enable acknowledge on Own Address2 match address.
00842   * @rmtoll OAR2         OA2EN         LL_I2C_EnableOwnAddress2
00843   * @param  I2Cx I2C Instance.
00844   * @retval None
00845   */
00846 __STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
00847 {
00848   SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
00849 }
00850
00851 /**
00852   * @brief  Disable  acknowledge on Own Address2 match address.
00853   * @rmtoll OAR2         OA2EN         LL_I2C_DisableOwnAddress2
00854   * @param  I2Cx I2C Instance.
00855   * @retval None
00856   */
00857 __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
00858 {
00859   CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
00860 }
00861
00862 /**
00863   * @brief  Check if Own Address1 acknowledge is enabled or disabled.
00864   * @rmtoll OAR2         OA2EN         LL_I2C_IsEnabledOwnAddress2
00865   * @param  I2Cx I2C Instance.
00866   * @retval State of bit (1 or 0).
00867   */
00868 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
00869 {
00870   return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL);
00871 }
00872
00873 /**
00874   * @brief  Configure the SDA setup, hold time and the SCL high, low period.
00875   * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
00876   * @rmtoll TIMINGR      TIMINGR       LL_I2C_SetTiming
00877   * @param  I2Cx I2C Instance.
00878   * @param  Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
00879   * @note   This parameter is computed with the STM32CubeMX Tool.
00880   * @retval None
00881   */
00882 __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
00883 {
00884   WRITE_REG(I2Cx->TIMINGR, Timing);
00885 }
00886
00887 /**
00888   * @brief  Get the Timing Prescaler setting.
00889   * @rmtoll TIMINGR      PRESC         LL_I2C_GetTimingPrescaler
00890   * @param  I2Cx I2C Instance.
00891   * @retval Value between Min_Data=0x0 and Max_Data=0xF
00892   */
00893 __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
00894 {
00895   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
00896 }
00897
00898 /**
00899   * @brief  Get the SCL low period setting.
00900   * @rmtoll TIMINGR      SCLL          LL_I2C_GetClockLowPeriod
00901   * @param  I2Cx I2C Instance.
00902   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
00903   */
00904 __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
00905 {
00906   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
00907 }
00908
00909 /**
00910   * @brief  Get the SCL high period setting.
00911   * @rmtoll TIMINGR      SCLH          LL_I2C_GetClockHighPeriod
00912   * @param  I2Cx I2C Instance.
00913   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
00914   */
00915 __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
00916 {
00917   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
00918 }
00919
00920 /**
00921   * @brief  Get the SDA hold time.
00922   * @rmtoll TIMINGR      SDADEL        LL_I2C_GetDataHoldTime
00923   * @param  I2Cx I2C Instance.
00924   * @retval Value between Min_Data=0x0 and Max_Data=0xF
00925   */
00926 __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
00927 {
00928   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
00929 }
00930
00931 /**
00932   * @brief  Get the SDA setup time.
00933   * @rmtoll TIMINGR      SCLDEL        LL_I2C_GetDataSetupTime
00934   * @param  I2Cx I2C Instance.
00935   * @retval Value between Min_Data=0x0 and Max_Data=0xF
00936   */
00937 __STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
00938 {
00939   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
00940 }
00941
00942 /**
00943   * @brief  Configure peripheral mode.
00944   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
00945   *         SMBus feature is supported by the I2Cx Instance.
00946   * @rmtoll CR1          SMBHEN        LL_I2C_SetMode\n
00947   *         CR1          SMBDEN        LL_I2C_SetMode
00948   * @param  I2Cx I2C Instance.
00949   * @param  PeripheralMode This parameter can be one of the following values:
00950   *         @arg @ref LL_I2C_MODE_I2C
00951   *         @arg @ref LL_I2C_MODE_SMBUS_HOST
00952   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
00953   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
00954   * @retval None
00955   */
00956 __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
00957 {
00958   MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode);
00959 }
00960
00961 /**
00962   * @brief  Get peripheral mode.
00963   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
00964   *         SMBus feature is supported by the I2Cx Instance.
00965   * @rmtoll CR1          SMBHEN        LL_I2C_GetMode\n
00966   *         CR1          SMBDEN        LL_I2C_GetMode
00967   * @param  I2Cx I2C Instance.
00968   * @retval Returned value can be one of the following values:
00969   *         @arg @ref LL_I2C_MODE_I2C
00970   *         @arg @ref LL_I2C_MODE_SMBUS_HOST
00971   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
00972   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
00973   */
00974 __STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
00975 {
00976   return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
00977 }
00978
00979 /**
00980   * @brief  Enable SMBus alert (Host or Device mode)
00981   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
00982   *         SMBus feature is supported by the I2Cx Instance.
00983   * @note   SMBus Device mode:
00984   *         - SMBus Alert pin is drived low and
00985   *           Alert Response Address Header acknowledge is enabled.
00986   *         SMBus Host mode:
00987   *         - SMBus Alert pin management is supported.
00988   * @rmtoll CR1          ALERTEN       LL_I2C_EnableSMBusAlert
00989   * @param  I2Cx I2C Instance.
00990   * @retval None
00991   */
00992 __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
00993 {
00994   SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
00995 }
00996
00997 /**
00998   * @brief  Disable SMBus alert (Host or Device mode)
00999   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01000   *         SMBus feature is supported by the I2Cx Instance.
01001   * @note   SMBus Device mode:
01002   *         - SMBus Alert pin is not drived (can be used as a standard GPIO) and
01003   *           Alert Response Address Header acknowledge is disabled.
01004   *         SMBus Host mode:
01005   *         - SMBus Alert pin management is not supported.
01006   * @rmtoll CR1          ALERTEN       LL_I2C_DisableSMBusAlert
01007   * @param  I2Cx I2C Instance.
01008   * @retval None
01009   */
01010 __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
01011 {
01012   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
01013 }
01014
01015 /**
01016   * @brief  Check if SMBus alert (Host or Device mode) is enabled or disabled.
01017   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01018   *         SMBus feature is supported by the I2Cx Instance.
01019   * @rmtoll CR1          ALERTEN       LL_I2C_IsEnabledSMBusAlert
01020   * @param  I2Cx I2C Instance.
01021   * @retval State of bit (1 or 0).
01022   */
01023 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
01024 {
01025   return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL);
01026 }
01027
01028 /**
01029   * @brief  Enable SMBus Packet Error Calculation (PEC).
01030   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01031   *         SMBus feature is supported by the I2Cx Instance.
01032   * @rmtoll CR1          PECEN         LL_I2C_EnableSMBusPEC
01033   * @param  I2Cx I2C Instance.
01034   * @retval None
01035   */
01036 __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
01037 {
01038   SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
01039 }
01040
01041 /**
01042   * @brief  Disable SMBus Packet Error Calculation (PEC).
01043   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01044   *         SMBus feature is supported by the I2Cx Instance.
01045   * @rmtoll CR1          PECEN         LL_I2C_DisableSMBusPEC
01046   * @param  I2Cx I2C Instance.
01047   * @retval None
01048   */
01049 __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
01050 {
01051   CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
01052 }
01053
01054 /**
01055   * @brief  Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
01056   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01057   *         SMBus feature is supported by the I2Cx Instance.
01058   * @rmtoll CR1          PECEN         LL_I2C_IsEnabledSMBusPEC
01059   * @param  I2Cx I2C Instance.
01060   * @retval State of bit (1 or 0).
01061   */
01062 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
01063 {
01064   return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL);
01065 }
01066
01067 /**
01068   * @brief  Configure the SMBus Clock Timeout.
01069   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01070   *         SMBus feature is supported by the I2Cx Instance.
01071   * @note   This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
01072   * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_ConfigSMBusTimeout\n
01073   *         TIMEOUTR     TIDLE         LL_I2C_ConfigSMBusTimeout\n
01074   *         TIMEOUTR     TIMEOUTB      LL_I2C_ConfigSMBusTimeout
01075   * @param  I2Cx I2C Instance.
01076   * @param  TimeoutA This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
01077   * @param  TimeoutAMode This parameter can be one of the following values:
01078   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
01079   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
01080   * @param  TimeoutB
01081   * @retval None
01082   */
01083 __STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
01084                                                uint32_t TimeoutB)
01085 {
01086   MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB,
01087              TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));
01088 }
01089
01090 /**
01091   * @brief  Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
01092   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01093   *         SMBus feature is supported by the I2Cx Instance.
01094   * @note   These bits can only be programmed when TimeoutA is disabled.
01095   * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_SetSMBusTimeoutA
01096   * @param  I2Cx I2C Instance.
01097   * @param  TimeoutA This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
01098   * @retval None
01099   */
01100 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
01101 {
01102   WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
01103 }
01104
01105 /**
01106   * @brief  Get the SMBus Clock TimeoutA setting.
01107   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01108   *         SMBus feature is supported by the I2Cx Instance.
01109   * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_GetSMBusTimeoutA
01110   * @param  I2Cx I2C Instance.
01111   * @retval Value between Min_Data=0 and Max_Data=0xFFF
01112   */
01113 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
01114 {
01115   return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
01116 }
01117
01118 /**
01119   * @brief  Set the SMBus Clock TimeoutA mode.
01120   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01121   *         SMBus feature is supported by the I2Cx Instance.
01122   * @note   This bit can only be programmed when TimeoutA is disabled.
01123   * @rmtoll TIMEOUTR     TIDLE         LL_I2C_SetSMBusTimeoutAMode
01124   * @param  I2Cx I2C Instance.
01125   * @param  TimeoutAMode This parameter can be one of the following values:
01126   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
01127   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
01128   * @retval None
01129   */
01130 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
01131 {
01132   WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
01133 }
01134
01135 /**
01136   * @brief  Get the SMBus Clock TimeoutA mode.
01137   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01138   *         SMBus feature is supported by the I2Cx Instance.
01139   * @rmtoll TIMEOUTR     TIDLE         LL_I2C_GetSMBusTimeoutAMode
01140   * @param  I2Cx I2C Instance.
01141   * @retval Returned value can be one of the following values:
01142   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
01143   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
01144   */
01145 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
01146 {
01147   return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
01148 }
01149
01150 /**
01151   * @brief  Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
01152   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01153   *         SMBus feature is supported by the I2Cx Instance.
01154   * @note   These bits can only be programmed when TimeoutB is disabled.
01155   * @rmtoll TIMEOUTR     TIMEOUTB      LL_I2C_SetSMBusTimeoutB
01156   * @param  I2Cx I2C Instance.
01157   * @param  TimeoutB This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
01158   * @retval None
01159   */
01160 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
01161 {
01162   WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos);
01163 }
01164
01165 /**
01166   * @brief  Get the SMBus Extented Cumulative Clock TimeoutB setting.
01167   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01168   *         SMBus feature is supported by the I2Cx Instance.
01169   * @rmtoll TIMEOUTR     TIMEOUTB      LL_I2C_GetSMBusTimeoutB
01170   * @param  I2Cx I2C Instance.
01171   * @retval Value between Min_Data=0 and Max_Data=0xFFF
01172   */
01173 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
01174 {
01175   return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
01176 }
01177
01178 /**
01179   * @brief  Enable the SMBus Clock Timeout.
01180   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01181   *         SMBus feature is supported by the I2Cx Instance.
01182   * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_EnableSMBusTimeout\n
01183   *         TIMEOUTR     TEXTEN        LL_I2C_EnableSMBusTimeout
01184   * @param  I2Cx I2C Instance.
01185   * @param  ClockTimeout This parameter can be one of the following values:
01186   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
01187   *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
01188   *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
01189   * @retval None
01190   */
01191 __STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
01192 {
01193   SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
01194 }
01195
01196 /**
01197   * @brief  Disable the SMBus Clock Timeout.
01198   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01199   *         SMBus feature is supported by the I2Cx Instance.
01200   * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_DisableSMBusTimeout\n
01201   *         TIMEOUTR     TEXTEN        LL_I2C_DisableSMBusTimeout
01202   * @param  I2Cx I2C Instance.
01203   * @param  ClockTimeout This parameter can be one of the following values:
01204   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
01205   *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
01206   *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
01207   * @retval None
01208   */
01209 __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
01210 {
01211   CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
01212 }
01213
01214 /**
01215   * @brief  Check if the SMBus Clock Timeout is enabled or disabled.
01216   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01217   *         SMBus feature is supported by the I2Cx Instance.
01218   * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_IsEnabledSMBusTimeout\n
01219   *         TIMEOUTR     TEXTEN        LL_I2C_IsEnabledSMBusTimeout
01220   * @param  I2Cx I2C Instance.
01221   * @param  ClockTimeout This parameter can be one of the following values:
01222   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
01223   *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
01224   *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
01225   * @retval State of bit (1 or 0).
01226   */
01227 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
01228 {
01229   return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout)) ? 1UL : 0UL);
01230 }
01231
01232 /**
01233   * @}
01234   */
01235
01236 /** @defgroup I2C_LL_EF_IT_Management IT_Management
01237   * @{
01238   */
01239
01240 /**
01241   * @brief  Enable TXIS interrupt.
01242   * @rmtoll CR1          TXIE          LL_I2C_EnableIT_TX
01243   * @param  I2Cx I2C Instance.
01244   * @retval None
01245   */
01246 __STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
01247 {
01248   SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
01249 }
01250
01251 /**
01252   * @brief  Disable TXIS interrupt.
01253   * @rmtoll CR1          TXIE          LL_I2C_DisableIT_TX
01254   * @param  I2Cx I2C Instance.
01255   * @retval None
01256   */
01257 __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
01258 {
01259   CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
01260 }
01261
01262 /**
01263   * @brief  Check if the TXIS Interrupt is enabled or disabled.
01264   * @rmtoll CR1          TXIE          LL_I2C_IsEnabledIT_TX
01265   * @param  I2Cx I2C Instance.
01266   * @retval State of bit (1 or 0).
01267   */
01268 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
01269 {
01270   return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL);
01271 }
01272
01273 /**
01274   * @brief  Enable RXNE interrupt.
01275   * @rmtoll CR1          RXIE          LL_I2C_EnableIT_RX
01276   * @param  I2Cx I2C Instance.
01277   * @retval None
01278   */
01279 __STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
01280 {
01281   SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
01282 }
01283
01284 /**
01285   * @brief  Disable RXNE interrupt.
01286   * @rmtoll CR1          RXIE          LL_I2C_DisableIT_RX
01287   * @param  I2Cx I2C Instance.
01288   * @retval None
01289   */
01290 __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
01291 {
01292   CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
01293 }
01294
01295 /**
01296   * @brief  Check if the RXNE Interrupt is enabled or disabled.
01297   * @rmtoll CR1          RXIE          LL_I2C_IsEnabledIT_RX
01298   * @param  I2Cx I2C Instance.
01299   * @retval State of bit (1 or 0).
01300   */
01301 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
01302 {
01303   return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL);
01304 }
01305
01306 /**
01307   * @brief  Enable Address match interrupt (slave mode only).
01308   * @rmtoll CR1          ADDRIE        LL_I2C_EnableIT_ADDR
01309   * @param  I2Cx I2C Instance.
01310   * @retval None
01311   */
01312 __STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
01313 {
01314   SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
01315 }
01316
01317 /**
01318   * @brief  Disable Address match interrupt (slave mode only).
01319   * @rmtoll CR1          ADDRIE        LL_I2C_DisableIT_ADDR
01320   * @param  I2Cx I2C Instance.
01321   * @retval None
01322   */
01323 __STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
01324 {
01325   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
01326 }
01327
01328 /**
01329   * @brief  Check if Address match interrupt is enabled or disabled.
01330   * @rmtoll CR1          ADDRIE        LL_I2C_IsEnabledIT_ADDR
01331   * @param  I2Cx I2C Instance.
01332   * @retval State of bit (1 or 0).
01333   */
01334 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
01335 {
01336   return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL);
01337 }
01338
01339 /**
01340   * @brief  Enable Not acknowledge received interrupt.
01341   * @rmtoll CR1          NACKIE        LL_I2C_EnableIT_NACK
01342   * @param  I2Cx I2C Instance.
01343   * @retval None
01344   */
01345 __STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
01346 {
01347   SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
01348 }
01349
01350 /**
01351   * @brief  Disable Not acknowledge received interrupt.
01352   * @rmtoll CR1          NACKIE        LL_I2C_DisableIT_NACK
01353   * @param  I2Cx I2C Instance.
01354   * @retval None
01355   */
01356 __STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
01357 {
01358   CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
01359 }
01360
01361 /**
01362   * @brief  Check if Not acknowledge received interrupt is enabled or disabled.
01363   * @rmtoll CR1          NACKIE        LL_I2C_IsEnabledIT_NACK
01364   * @param  I2Cx I2C Instance.
01365   * @retval State of bit (1 or 0).
01366   */
01367 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
01368 {
01369   return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL);
01370 }
01371
01372 /**
01373   * @brief  Enable STOP detection interrupt.
01374   * @rmtoll CR1          STOPIE        LL_I2C_EnableIT_STOP
01375   * @param  I2Cx I2C Instance.
01376   * @retval None
01377   */
01378 __STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
01379 {
01380   SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
01381 }
01382
01383 /**
01384   * @brief  Disable STOP detection interrupt.
01385   * @rmtoll CR1          STOPIE        LL_I2C_DisableIT_STOP
01386   * @param  I2Cx I2C Instance.
01387   * @retval None
01388   */
01389 __STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
01390 {
01391   CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
01392 }
01393
01394 /**
01395   * @brief  Check if STOP detection interrupt is enabled or disabled.
01396   * @rmtoll CR1          STOPIE        LL_I2C_IsEnabledIT_STOP
01397   * @param  I2Cx I2C Instance.
01398   * @retval State of bit (1 or 0).
01399   */
01400 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
01401 {
01402   return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL);
01403 }
01404
01405 /**
01406   * @brief  Enable Transfer Complete interrupt.
01407   * @note   Any of these events will generate interrupt :
01408   *         Transfer Complete (TC)
01409   *         Transfer Complete Reload (TCR)
01410   * @rmtoll CR1          TCIE          LL_I2C_EnableIT_TC
01411   * @param  I2Cx I2C Instance.
01412   * @retval None
01413   */
01414 __STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
01415 {
01416   SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
01417 }
01418
01419 /**
01420   * @brief  Disable Transfer Complete interrupt.
01421   * @note   Any of these events will generate interrupt :
01422   *         Transfer Complete (TC)
01423   *         Transfer Complete Reload (TCR)
01424   * @rmtoll CR1          TCIE          LL_I2C_DisableIT_TC
01425   * @param  I2Cx I2C Instance.
01426   * @retval None
01427   */
01428 __STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
01429 {
01430   CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
01431 }
01432
01433 /**
01434   * @brief  Check if Transfer Complete interrupt is enabled or disabled.
01435   * @rmtoll CR1          TCIE          LL_I2C_IsEnabledIT_TC
01436   * @param  I2Cx I2C Instance.
01437   * @retval State of bit (1 or 0).
01438   */
01439 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
01440 {
01441   return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL);
01442 }
01443
01444 /**
01445   * @brief  Enable Error interrupts.
01446   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01447   *         SMBus feature is supported by the I2Cx Instance.
01448   * @note   Any of these errors will generate interrupt :
01449   *         Arbitration Loss (ARLO)
01450   *         Bus Error detection (BERR)
01451   *         Overrun/Underrun (OVR)
01452   *         SMBus Timeout detection (TIMEOUT)
01453   *         SMBus PEC error detection (PECERR)
01454   *         SMBus Alert pin event detection (ALERT)
01455   * @rmtoll CR1          ERRIE         LL_I2C_EnableIT_ERR
01456   * @param  I2Cx I2C Instance.
01457   * @retval None
01458   */
01459 __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
01460 {
01461   SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
01462 }
01463
01464 /**
01465   * @brief  Disable Error interrupts.
01466   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01467   *         SMBus feature is supported by the I2Cx Instance.
01468   * @note   Any of these errors will generate interrupt :
01469   *         Arbitration Loss (ARLO)
01470   *         Bus Error detection (BERR)
01471   *         Overrun/Underrun (OVR)
01472   *         SMBus Timeout detection (TIMEOUT)
01473   *         SMBus PEC error detection (PECERR)
01474   *         SMBus Alert pin event detection (ALERT)
01475   * @rmtoll CR1          ERRIE         LL_I2C_DisableIT_ERR
01476   * @param  I2Cx I2C Instance.
01477   * @retval None
01478   */
01479 __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
01480 {
01481   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
01482 }
01483
01484 /**
01485   * @brief  Check if Error interrupts are enabled or disabled.
01486   * @rmtoll CR1          ERRIE         LL_I2C_IsEnabledIT_ERR
01487   * @param  I2Cx I2C Instance.
01488   * @retval State of bit (1 or 0).
01489   */
01490 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
01491 {
01492   return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL);
01493 }
01494
01495 /**
01496   * @}
01497   */
01498
01499 /** @defgroup I2C_LL_EF_FLAG_management FLAG_management
01500   * @{
01501   */
01502
01503 /**
01504   * @brief  Indicate the status of Transmit data register empty flag.
01505   * @note   RESET: When next data is written in Transmit data register.
01506   *         SET: When Transmit data register is empty.
01507   * @rmtoll ISR          TXE           LL_I2C_IsActiveFlag_TXE
01508   * @param  I2Cx I2C Instance.
01509   * @retval State of bit (1 or 0).
01510   */
01511 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
01512 {
01513   return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);
01514 }
01515
01516 /**
01517   * @brief  Indicate the status of Transmit interrupt flag.
01518   * @note   RESET: When next data is written in Transmit data register.
01519   *         SET: When Transmit data register is empty.
01520   * @rmtoll ISR          TXIS          LL_I2C_IsActiveFlag_TXIS
01521   * @param  I2Cx I2C Instance.
01522   * @retval State of bit (1 or 0).
01523   */
01524 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
01525 {
01526   return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL);
01527 }
01528
01529 /**
01530   * @brief  Indicate the status of Receive data register not empty flag.
01531   * @note   RESET: When Receive data register is read.
01532   *         SET: When the received data is copied in Receive data register.
01533   * @rmtoll ISR          RXNE          LL_I2C_IsActiveFlag_RXNE
01534   * @param  I2Cx I2C Instance.
01535   * @retval State of bit (1 or 0).
01536   */
01537 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
01538 {
01539   return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);
01540 }
01541
01542 /**
01543   * @brief  Indicate the status of Address matched flag (slave mode).
01544   * @note   RESET: Clear default value.
01545   *         SET: When the received slave address matched with one of the enabled slave address.
01546   * @rmtoll ISR          ADDR          LL_I2C_IsActiveFlag_ADDR
01547   * @param  I2Cx I2C Instance.
01548   * @retval State of bit (1 or 0).
01549   */
01550 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
01551 {
01552   return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL);
01553 }
01554
01555 /**
01556   * @brief  Indicate the status of Not Acknowledge received flag.
01557   * @note   RESET: Clear default value.
01558   *         SET: When a NACK is received after a byte transmission.
01559   * @rmtoll ISR          NACKF         LL_I2C_IsActiveFlag_NACK
01560   * @param  I2Cx I2C Instance.
01561   * @retval State of bit (1 or 0).
01562   */
01563 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
01564 {
01565   return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL);
01566 }
01567
01568 /**
01569   * @brief  Indicate the status of Stop detection flag.
01570   * @note   RESET: Clear default value.
01571   *         SET: When a Stop condition is detected.
01572   * @rmtoll ISR          STOPF         LL_I2C_IsActiveFlag_STOP
01573   * @param  I2Cx I2C Instance.
01574   * @retval State of bit (1 or 0).
01575   */
01576 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
01577 {
01578   return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
01579 }
01580
01581 /**
01582   * @brief  Indicate the status of Transfer complete flag (master mode).
01583   * @note   RESET: Clear default value.
01584   *         SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
01585   * @rmtoll ISR          TC            LL_I2C_IsActiveFlag_TC
01586   * @param  I2Cx I2C Instance.
01587   * @retval State of bit (1 or 0).
01588   */
01589 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
01590 {
01591   return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL);
01592 }
01593
01594 /**
01595   * @brief  Indicate the status of Transfer complete flag (master mode).
01596   * @note   RESET: Clear default value.
01597   *         SET: When RELOAD=1 and NBYTES date have been transferred.
01598   * @rmtoll ISR          TCR           LL_I2C_IsActiveFlag_TCR
01599   * @param  I2Cx I2C Instance.
01600   * @retval State of bit (1 or 0).
01601   */
01602 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
01603 {
01604   return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL);
01605 }
01606
01607 /**
01608   * @brief  Indicate the status of Bus error flag.
01609   * @note   RESET: Clear default value.
01610   *         SET: When a misplaced Start or Stop condition is detected.
01611   * @rmtoll ISR          BERR          LL_I2C_IsActiveFlag_BERR
01612   * @param  I2Cx I2C Instance.
01613   * @retval State of bit (1 or 0).
01614   */
01615 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
01616 {
01617   return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL);
01618 }
01619
01620 /**
01621   * @brief  Indicate the status of Arbitration lost flag.
01622   * @note   RESET: Clear default value.
01623   *         SET: When arbitration lost.
01624   * @rmtoll ISR          ARLO          LL_I2C_IsActiveFlag_ARLO
01625   * @param  I2Cx I2C Instance.
01626   * @retval State of bit (1 or 0).
01627   */
01628 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
01629 {
01630   return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL);
01631 }
01632
01633 /**
01634   * @brief  Indicate the status of Overrun/Underrun flag (slave mode).
01635   * @note   RESET: Clear default value.
01636   *         SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
01637   * @rmtoll ISR          OVR           LL_I2C_IsActiveFlag_OVR
01638   * @param  I2Cx I2C Instance.
01639   * @retval State of bit (1 or 0).
01640   */
01641 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
01642 {
01643   return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL);
01644 }
01645
01646 /**
01647   * @brief  Indicate the status of SMBus PEC error flag in reception.
01648   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01649   *         SMBus feature is supported by the I2Cx Instance.
01650   * @note   RESET: Clear default value.
01651   *         SET: When the received PEC does not match with the PEC register content.
01652   * @rmtoll ISR          PECERR        LL_I2C_IsActiveSMBusFlag_PECERR
01653   * @param  I2Cx I2C Instance.
01654   * @retval State of bit (1 or 0).
01655   */
01656 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
01657 {
01658   return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL);
01659 }
01660
01661 /**
01662   * @brief  Indicate the status of SMBus Timeout detection flag.
01663   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01664   *         SMBus feature is supported by the I2Cx Instance.
01665   * @note   RESET: Clear default value.
01666   *         SET: When a timeout or extended clock timeout occurs.
01667   * @rmtoll ISR          TIMEOUT       LL_I2C_IsActiveSMBusFlag_TIMEOUT
01668   * @param  I2Cx I2C Instance.
01669   * @retval State of bit (1 or 0).
01670   */
01671 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
01672 {
01673   return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL);
01674 }
01675
01676 /**
01677   * @brief  Indicate the status of SMBus alert flag.
01678   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01679   *         SMBus feature is supported by the I2Cx Instance.
01680   * @note   RESET: Clear default value.
01681   *         SET: When SMBus host configuration, SMBus alert enabled and
01682   *              a falling edge event occurs on SMBA pin.
01683   * @rmtoll ISR          ALERT         LL_I2C_IsActiveSMBusFlag_ALERT
01684   * @param  I2Cx I2C Instance.
01685   * @retval State of bit (1 or 0).
01686   */
01687 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
01688 {
01689   return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL);
01690 }
01691
01692 /**
01693   * @brief  Indicate the status of Bus Busy flag.
01694   * @note   RESET: Clear default value.
01695   *         SET: When a Start condition is detected.
01696   * @rmtoll ISR          BUSY          LL_I2C_IsActiveFlag_BUSY
01697   * @param  I2Cx I2C Instance.
01698   * @retval State of bit (1 or 0).
01699   */
01700 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
01701 {
01702   return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL);
01703 }
01704
01705 /**
01706   * @brief  Clear Address Matched flag.
01707   * @rmtoll ICR          ADDRCF        LL_I2C_ClearFlag_ADDR
01708   * @param  I2Cx I2C Instance.
01709   * @retval None
01710   */
01711 __STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
01712 {
01713   SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
01714 }
01715
01716 /**
01717   * @brief  Clear Not Acknowledge flag.
01718   * @rmtoll ICR          NACKCF        LL_I2C_ClearFlag_NACK
01719   * @param  I2Cx I2C Instance.
01720   * @retval None
01721   */
01722 __STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
01723 {
01724   SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
01725 }
01726
01727 /**
01728   * @brief  Clear Stop detection flag.
01729   * @rmtoll ICR          STOPCF        LL_I2C_ClearFlag_STOP
01730   * @param  I2Cx I2C Instance.
01731   * @retval None
01732   */
01733 __STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
01734 {
01735   SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
01736 }
01737
01738 /**
01739   * @brief  Clear Transmit data register empty flag (TXE).
01740   * @note   This bit can be clear by software in order to flush the transmit data register (TXDR).
01741   * @rmtoll ISR          TXE           LL_I2C_ClearFlag_TXE
01742   * @param  I2Cx I2C Instance.
01743   * @retval None
01744   */
01745 __STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
01746 {
01747   WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
01748 }
01749
01750 /**
01751   * @brief  Clear Bus error flag.
01752   * @rmtoll ICR          BERRCF        LL_I2C_ClearFlag_BERR
01753   * @param  I2Cx I2C Instance.
01754   * @retval None
01755   */
01756 __STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
01757 {
01758   SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
01759 }
01760
01761 /**
01762   * @brief  Clear Arbitration lost flag.
01763   * @rmtoll ICR          ARLOCF        LL_I2C_ClearFlag_ARLO
01764   * @param  I2Cx I2C Instance.
01765   * @retval None
01766   */
01767 __STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
01768 {
01769   SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
01770 }
01771
01772 /**
01773   * @brief  Clear Overrun/Underrun flag.
01774   * @rmtoll ICR          OVRCF         LL_I2C_ClearFlag_OVR
01775   * @param  I2Cx I2C Instance.
01776   * @retval None
01777   */
01778 __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
01779 {
01780   SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
01781 }
01782
01783 /**
01784   * @brief  Clear SMBus PEC error flag.
01785   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01786   *         SMBus feature is supported by the I2Cx Instance.
01787   * @rmtoll ICR          PECCF         LL_I2C_ClearSMBusFlag_PECERR
01788   * @param  I2Cx I2C Instance.
01789   * @retval None
01790   */
01791 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
01792 {
01793   SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
01794 }
01795
01796 /**
01797   * @brief  Clear SMBus Timeout detection flag.
01798   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01799   *         SMBus feature is supported by the I2Cx Instance.
01800   * @rmtoll ICR          TIMOUTCF      LL_I2C_ClearSMBusFlag_TIMEOUT
01801   * @param  I2Cx I2C Instance.
01802   * @retval None
01803   */
01804 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
01805 {
01806   SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
01807 }
01808
01809 /**
01810   * @brief  Clear SMBus Alert flag.
01811   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01812   *         SMBus feature is supported by the I2Cx Instance.
01813   * @rmtoll ICR          ALERTCF       LL_I2C_ClearSMBusFlag_ALERT
01814   * @param  I2Cx I2C Instance.
01815   * @retval None
01816   */
01817 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
01818 {
01819   SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
01820 }
01821
01822 /**
01823   * @}
01824   */
01825
01826 /** @defgroup I2C_LL_EF_Data_Management Data_Management
01827   * @{
01828   */
01829
01830 /**
01831   * @brief  Enable automatic STOP condition generation (master mode).
01832   * @note   Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
01833   *         This bit has no effect in slave mode or when RELOAD bit is set.
01834   * @rmtoll CR2          AUTOEND       LL_I2C_EnableAutoEndMode
01835   * @param  I2Cx I2C Instance.
01836   * @retval None
01837   */
01838 __STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
01839 {
01840   SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
01841 }
01842
01843 /**
01844   * @brief  Disable automatic STOP condition generation (master mode).
01845   * @note   Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
01846   * @rmtoll CR2          AUTOEND       LL_I2C_DisableAutoEndMode
01847   * @param  I2Cx I2C Instance.
01848   * @retval None
01849   */
01850 __STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
01851 {
01852   CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
01853 }
01854
01855 /**
01856   * @brief  Check if automatic STOP condition is enabled or disabled.
01857   * @rmtoll CR2          AUTOEND       LL_I2C_IsEnabledAutoEndMode
01858   * @param  I2Cx I2C Instance.
01859   * @retval State of bit (1 or 0).
01860   */
01861 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
01862 {
01863   return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL);
01864 }
01865
01866 /**
01867   * @brief  Enable reload mode (master mode).
01868   * @note   The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
01869   * @rmtoll CR2          RELOAD       LL_I2C_EnableReloadMode
01870   * @param  I2Cx I2C Instance.
01871   * @retval None
01872   */
01873 __STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
01874 {
01875   SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
01876 }
01877
01878 /**
01879   * @brief  Disable reload mode (master mode).
01880   * @note   The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
01881   * @rmtoll CR2          RELOAD       LL_I2C_DisableReloadMode
01882   * @param  I2Cx I2C Instance.
01883   * @retval None
01884   */
01885 __STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
01886 {
01887   CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
01888 }
01889
01890 /**
01891   * @brief  Check if reload mode is enabled or disabled.
01892   * @rmtoll CR2          RELOAD       LL_I2C_IsEnabledReloadMode
01893   * @param  I2Cx I2C Instance.
01894   * @retval State of bit (1 or 0).
01895   */
01896 __STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
01897 {
01898   return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL);
01899 }
01900
01901 /**
01902   * @brief  Configure the number of bytes for transfer.
01903   * @note   Changing these bits when START bit is set is not allowed.
01904   * @rmtoll CR2          NBYTES           LL_I2C_SetTransferSize
01905   * @param  I2Cx I2C Instance.
01906   * @param  TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
01907   * @retval None
01908   */
01909 __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
01910 {
01911   MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);
01912 }
01913
01914 /**
01915   * @brief  Get the number of bytes configured for transfer.
01916   * @rmtoll CR2          NBYTES           LL_I2C_GetTransferSize
01917   * @param  I2Cx I2C Instance.
01918   * @retval Value between Min_Data=0x0 and Max_Data=0xFF
01919   */
01920 __STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
01921 {
01922   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
01923 }
01924
01925 /**
01926   * @brief  Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
01927   * @note   Usage in Slave mode only.
01928   * @rmtoll CR2          NACK          LL_I2C_AcknowledgeNextData
01929   * @param  I2Cx I2C Instance.
01930   * @param  TypeAcknowledge This parameter can be one of the following values:
01931   *         @arg @ref LL_I2C_ACK
01932   *         @arg @ref LL_I2C_NACK
01933   * @retval None
01934   */
01935 __STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
01936 {
01937   MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
01938 }
01939
01940 /**
01941   * @brief  Generate a START or RESTART condition
01942   * @note   The START bit can be set even if bus is BUSY or I2C is in slave mode.
01943   *         This action has no effect when RELOAD is set.
01944   * @rmtoll CR2          START           LL_I2C_GenerateStartCondition
01945   * @param  I2Cx I2C Instance.
01946   * @retval None
01947   */
01948 __STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
01949 {
01950   SET_BIT(I2Cx->CR2, I2C_CR2_START);
01951 }
01952
01953 /**
01954   * @brief  Generate a STOP condition after the current byte transfer (master mode).
01955   * @rmtoll CR2          STOP          LL_I2C_GenerateStopCondition
01956   * @param  I2Cx I2C Instance.
01957   * @retval None
01958   */
01959 __STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
01960 {
01961   SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
01962 }
01963
01964 /**
01965   * @brief  Enable automatic RESTART Read request condition for 10bit address header (master mode).
01966   * @note   The master sends the complete 10bit slave address read sequence :
01967   *         Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction.
01968   * @rmtoll CR2          HEAD10R       LL_I2C_EnableAuto10BitRead
01969   * @param  I2Cx I2C Instance.
01970   * @retval None
01971   */
01972 __STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
01973 {
01974   CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
01975 }
01976
01977 /**
01978   * @brief  Disable automatic RESTART Read request condition for 10bit address header (master mode).
01979   * @note   The master only sends the first 7 bits of 10bit address in Read direction.
01980   * @rmtoll CR2          HEAD10R       LL_I2C_DisableAuto10BitRead
01981   * @param  I2Cx I2C Instance.
01982   * @retval None
01983   */
01984 __STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
01985 {
01986   SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
01987 }
01988
01989 /**
01990   * @brief  Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
01991   * @rmtoll CR2          HEAD10R       LL_I2C_IsEnabledAuto10BitRead
01992   * @param  I2Cx I2C Instance.
01993   * @retval State of bit (1 or 0).
01994   */
01995 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
01996 {
01997   return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL);
01998 }
01999
02000 /**
02001   * @brief  Configure the transfer direction (master mode).
02002   * @note   Changing these bits when START bit is set is not allowed.
02003   * @rmtoll CR2          RD_WRN           LL_I2C_SetTransferRequest
02004   * @param  I2Cx I2C Instance.
02005   * @param  TransferRequest This parameter can be one of the following values:
02006   *         @arg @ref LL_I2C_REQUEST_WRITE
02007   *         @arg @ref LL_I2C_REQUEST_READ
02008   * @retval None
02009   */
02010 __STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
02011 {
02012   MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
02013 }
02014
02015 /**
02016   * @brief  Get the transfer direction requested (master mode).
02017   * @rmtoll CR2          RD_WRN           LL_I2C_GetTransferRequest
02018   * @param  I2Cx I2C Instance.
02019   * @retval Returned value can be one of the following values:
02020   *         @arg @ref LL_I2C_REQUEST_WRITE
02021   *         @arg @ref LL_I2C_REQUEST_READ
02022   */
02023 __STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
02024 {
02025   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
02026 }
02027
02028 /**
02029   * @brief  Configure the slave address for transfer (master mode).
02030   * @note   Changing these bits when START bit is set is not allowed.
02031   * @rmtoll CR2          SADD           LL_I2C_SetSlaveAddr
02032   * @param  I2Cx I2C Instance.
02033   * @param  SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
02034   * @retval None
02035   */
02036 __STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
02037 {
02038   MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
02039 }
02040
02041 /**
02042   * @brief  Get the slave address programmed for transfer.
02043   * @rmtoll CR2          SADD           LL_I2C_GetSlaveAddr
02044   * @param  I2Cx I2C Instance.
02045   * @retval Value between Min_Data=0x0 and Max_Data=0x3F
02046   */
02047 __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
02048 {
02049   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
02050 }
02051
02052 /**
02053   * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
02054   * @rmtoll CR2          SADD          LL_I2C_HandleTransfer\n
02055   *         CR2          ADD10         LL_I2C_HandleTransfer\n
02056   *         CR2          RD_WRN        LL_I2C_HandleTransfer\n
02057   *         CR2          START         LL_I2C_HandleTransfer\n
02058   *         CR2          STOP          LL_I2C_HandleTransfer\n
02059   *         CR2          RELOAD        LL_I2C_HandleTransfer\n
02060   *         CR2          NBYTES        LL_I2C_HandleTransfer\n
02061   *         CR2          AUTOEND       LL_I2C_HandleTransfer\n
02062   *         CR2          HEAD10R       LL_I2C_HandleTransfer
02063   * @param  I2Cx I2C Instance.
02064   * @param  SlaveAddr Specifies the slave address to be programmed.
02065   * @param  SlaveAddrSize This parameter can be one of the following values:
02066   *         @arg @ref LL_I2C_ADDRSLAVE_7BIT
02067   *         @arg @ref LL_I2C_ADDRSLAVE_10BIT
02068   * @param  TransferSize Specifies the number of bytes to be programmed.
02069   *                       This parameter must be a value between Min_Data=0 and Max_Data=255.
02070   * @param  EndMode This parameter can be one of the following values:
02071   *         @arg @ref LL_I2C_MODE_RELOAD
02072   *         @arg @ref LL_I2C_MODE_AUTOEND
02073   *         @arg @ref LL_I2C_MODE_SOFTEND
02074   *         @arg @ref LL_I2C_MODE_SMBUS_RELOAD
02075   *         @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
02076   *         @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
02077   *         @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
02078   *         @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
02079   * @param  Request This parameter can be one of the following values:
02080   *         @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
02081   *         @arg @ref LL_I2C_GENERATE_STOP
02082   *         @arg @ref LL_I2C_GENERATE_START_READ
02083   *         @arg @ref LL_I2C_GENERATE_START_WRITE
02084   *         @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
02085   *         @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
02086   *         @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
02087   *         @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
02088   * @retval None
02089   */
02090 __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
02091                                            uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
02092 {
02093   MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
02094              I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
02095              SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request);
02096 }
02097
02098 /**
02099   * @brief  Indicate the value of transfer direction (slave mode).
02100   * @note   RESET: Write transfer, Slave enters in receiver mode.
02101   *         SET: Read transfer, Slave enters in transmitter mode.
02102   * @rmtoll ISR          DIR           LL_I2C_GetTransferDirection
02103   * @param  I2Cx I2C Instance.
02104   * @retval Returned value can be one of the following values:
02105   *         @arg @ref LL_I2C_DIRECTION_WRITE
02106   *         @arg @ref LL_I2C_DIRECTION_READ
02107   */
02108 __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
02109 {
02110   return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
02111 }
02112
02113 /**
02114   * @brief  Return the slave matched address.
02115   * @rmtoll ISR          ADDCODE       LL_I2C_GetAddressMatchCode
02116   * @param  I2Cx I2C Instance.
02117   * @retval Value between Min_Data=0x00 and Max_Data=0x3F
02118   */
02119 __STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
02120 {
02121   return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
02122 }
02123
02124 /**
02125   * @brief  Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
02126   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
02127   *         SMBus feature is supported by the I2Cx Instance.
02128   * @note   This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received.
02129   *         This bit has no effect when RELOAD bit is set.
02130   *         This bit has no effect in device mode when SBC bit is not set.
02131   * @rmtoll CR2          PECBYTE       LL_I2C_EnableSMBusPECCompare
02132   * @param  I2Cx I2C Instance.
02133   * @retval None
02134   */
02135 __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
02136 {
02137   SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
02138 }
02139
02140 /**
02141   * @brief  Check if the SMBus Packet Error byte internal comparison is requested or not.
02142   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
02143   *         SMBus feature is supported by the I2Cx Instance.
02144   * @rmtoll CR2          PECBYTE       LL_I2C_IsEnabledSMBusPECCompare
02145   * @param  I2Cx I2C Instance.
02146   * @retval State of bit (1 or 0).
02147   */
02148 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
02149 {
02150   return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL);
02151 }
02152
02153 /**
02154   * @brief  Get the SMBus Packet Error byte calculated.
02155   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
02156   *         SMBus feature is supported by the I2Cx Instance.
02157   * @rmtoll PECR         PEC           LL_I2C_GetSMBusPEC
02158   * @param  I2Cx I2C Instance.
02159   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
02160 */
02161 __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
02162 {
02163   return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
02164 }
02165
02166 /**
02167   * @brief  Read Receive Data register.
02168   * @rmtoll RXDR         RXDATA        LL_I2C_ReceiveData8
02169   * @param  I2Cx I2C Instance.
02170   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
02171   */
02172 __STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
02173 {
02174   return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
02175 }
02176
02177 /**
02178   * @brief  Write in Transmit Data Register .
02179   * @rmtoll TXDR         TXDATA        LL_I2C_TransmitData8
02180   * @param  I2Cx I2C Instance.
02181   * @param  Data Value between Min_Data=0x00 and Max_Data=0xFF
02182   * @retval None
02183   */
02184 __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
02185 {
02186   WRITE_REG(I2Cx->TXDR, Data);
02187 }
02188
02189 /**
02190   * @}
02191   */
02192
02193 #if defined(USE_FULL_LL_DRIVER)
02194 /** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
02195   * @{
02196   */
02197
02198 ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
02199 ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx);
02200 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
02201
02202
02203 /**
02204   * @}
02205   */
02206 #endif /* USE_FULL_LL_DRIVER */
02207
02208 /**
02209   * @}
02210   */
02211
02212 /**
02213   * @}
02214   */
02215
02216 #endif /* I2C1 || I2C3 */
02217
02218 /**
02219   * @}
02220   */
02221
02222 #ifdef __cplusplus
02223 }
02224 #endif
02225
02226 #endif /* STM32WBxx_LL_I2C_H */
02227
02228 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_ipcc.h Source File

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stm32wbxx_ll_ipcc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_ipcc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of IPCC LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_LL_IPCC_H
00022 #define STM32WBxx_LL_IPCC_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx.h"
00030
00031 /** @addtogroup STM32WBxx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined(IPCC)
00036
00037 /** @defgroup IPCC_LL IPCC
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /* Private macros ------------------------------------------------------------*/
00045 /* Exported types ------------------------------------------------------------*/
00046 /* Exported constants --------------------------------------------------------*/
00047 /** @defgroup IPCC_LL_Exported_Constants IPCC Exported Constants
00048   * @{
00049   */
00050
00051 /** @defgroup IPCC_LL_EC_GET_FLAG Get Flags Defines
00052   * @brief    Flags defines which can be used with LL_IPCC_ReadReg function
00053   * @{
00054   */
00055 #define LL_IPCC_C1TOC2SR_CH1F IPCC_C1TOC2SR_CH1F_Msk /*!< C1 transmit to C2 receive Channel1 status flag before masking */
00056 #define LL_IPCC_C1TOC2SR_CH2F IPCC_C1TOC2SR_CH2F_Msk /*!< C1 transmit to C2 receive Channel2 status flag before masking */
00057 #define LL_IPCC_C1TOC2SR_CH3F IPCC_C1TOC2SR_CH3F_Msk /*!< C1 transmit to C2 receive Channel3 status flag before masking */
00058 #define LL_IPCC_C1TOC2SR_CH4F IPCC_C1TOC2SR_CH4F_Msk /*!< C1 transmit to C2 receive Channel4 status flag before masking */
00059 #define LL_IPCC_C1TOC2SR_CH5F IPCC_C1TOC2SR_CH5F_Msk /*!< C1 transmit to C2 receive Channel5 status flag before masking */
00060 #define LL_IPCC_C1TOC2SR_CH6F IPCC_C1TOC2SR_CH6F_Msk /*!< C1 transmit to C2 receive Channel6 status flag before masking */
00061 #define LL_IPCC_C2TOC1SR_CH1F IPCC_C2TOC1SR_CH1F_Msk /*!< C2 transmit to C1 receive Channel1 status flag before masking */
00062 #define LL_IPCC_C2TOC1SR_CH2F IPCC_C2TOC1SR_CH2F_Msk /*!< C2 transmit to C1 receive Channel2 status flag before masking */
00063 #define LL_IPCC_C2TOC1SR_CH3F IPCC_C2TOC1SR_CH3F_Msk /*!< C2 transmit to C1 receive Channel3 status flag before masking */
00064 #define LL_IPCC_C2TOC1SR_CH4F IPCC_C2TOC1SR_CH4F_Msk /*!< C2 transmit to C1 receive Channel4 status flag before masking */
00065 #define LL_IPCC_C2TOC1SR_CH5F IPCC_C2TOC1SR_CH5F_Msk /*!< C2 transmit to C1 receive Channel5 status flag before masking */
00066 #define LL_IPCC_C2TOC1SR_CH6F IPCC_C2TOC1SR_CH6F_Msk /*!< C2 transmit to C1 receive Channel6 status flag before masking */
00067
00068 /**
00069   * @}
00070   */
00071
00072 /** @defgroup IPCC_LL_EC_Channel Channel
00073   * @{
00074   */
00075 #define LL_IPCC_CHANNEL_1 (0x00000001U) /*!< IPCC Channel 1 */
00076 #define LL_IPCC_CHANNEL_2 (0x00000002U) /*!< IPCC Channel 2 */
00077 #define LL_IPCC_CHANNEL_3 (0x00000004U) /*!< IPCC Channel 3 */
00078 #define LL_IPCC_CHANNEL_4 (0x00000008U) /*!< IPCC Channel 4 */
00079 #define LL_IPCC_CHANNEL_5 (0x00000010U) /*!< IPCC Channel 5 */
00080 #define LL_IPCC_CHANNEL_6 (0x00000020U) /*!< IPCC Channel 6 */
00081 /**
00082   * @}
00083   */
00084
00085 /**
00086   * @}
00087   */
00088
00089 /* Exported macro ------------------------------------------------------------*/
00090 /** @defgroup IPCC_LL_Exported_Macros IPCC Exported Macros
00091   * @{
00092   */
00093
00094 /** @defgroup IPCC_LL_EM_WRITE_READ Common Write and read registers Macros
00095   * @{
00096   */
00097
00098 /**
00099   * @brief  Write a value in IPCC register
00100   * @param  __INSTANCE__ IPCC Instance
00101   * @param  __REG__ Register to be written
00102   * @param  __VALUE__ Value to be written in the register
00103   * @retval None
00104   */
00105 #define LL_IPCC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00106
00107 /**
00108   * @brief  Read a value in IPCC register
00109   * @param  __INSTANCE__ IPCC Instance
00110   * @param  __REG__ Register to be read
00111   * @retval Register value
00112   */
00113 #define LL_IPCC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00114 /**
00115   * @}
00116   */
00117
00118 /**
00119   * @}
00120   */
00121
00122
00123 /* Exported functions --------------------------------------------------------*/
00124 /** @defgroup IPCC_LL_Exported_Functions IPCC Exported Functions
00125   * @{
00126   */
00127
00128 /** @defgroup IPCC_LL_EF_IT_Management IT_Management
00129   * @{
00130   */
00131
00132 /**
00133   * @brief  Enable Transmit channel free interrupt for processor 1.
00134   * @rmtoll C1CR          TXFIE         LL_C1_IPCC_EnableIT_TXF
00135   * @param  IPCCx IPCC Instance.
00136   * @retval None
00137   */
00138 __STATIC_INLINE void LL_C1_IPCC_EnableIT_TXF(IPCC_TypeDef *IPCCx)
00139 {
00140   SET_BIT(IPCCx->C1CR, IPCC_C1CR_TXFIE);
00141 }
00142
00143 /**
00144   * @brief  Disable Transmit channel free interrupt for processor 1.
00145   * @rmtoll C1CR          TXFIE         LL_C1_IPCC_DisableIT_TXF
00146   * @param  IPCCx IPCC Instance.
00147   * @retval None
00148   */
00149 __STATIC_INLINE void LL_C1_IPCC_DisableIT_TXF(IPCC_TypeDef *IPCCx)
00150 {
00151   CLEAR_BIT(IPCCx->C1CR, IPCC_C1CR_TXFIE);
00152 }
00153
00154 /**
00155   * @brief  Check if Transmit channel free interrupt for processor 1 is enabled.
00156   * @rmtoll C1CR          TXFIE         LL_C1_IPCC_IsEnabledIT_TXF
00157   * @param  IPCCx IPCC Instance.
00158   * @retval State of bit (1 or 0).
00159   */
00160 __STATIC_INLINE uint32_t LL_C1_IPCC_IsEnabledIT_TXF(IPCC_TypeDef const *const IPCCx)
00161 {
00162   return ((READ_BIT(IPCCx->C1CR, IPCC_C1CR_TXFIE) == (IPCC_C1CR_TXFIE)) ? 1UL : 0UL);
00163 }
00164
00165 /**
00166   * @brief  Enable Receive channel occupied interrupt for processor 1.
00167   * @rmtoll C1CR          RXOIE         LL_C1_IPCC_EnableIT_RXO
00168   * @param  IPCCx IPCC Instance.
00169   * @retval None
00170   */
00171 __STATIC_INLINE void LL_C1_IPCC_EnableIT_RXO(IPCC_TypeDef *IPCCx)
00172 {
00173   SET_BIT(IPCCx->C1CR, IPCC_C1CR_RXOIE);
00174 }
00175
00176 /**
00177   * @brief  Disable Receive channel occupied interrupt for processor 1.
00178   * @rmtoll C1CR          RXOIE         LL_C1_IPCC_DisableIT_RXO
00179   * @param  IPCCx IPCC Instance.
00180   * @retval None
00181   */
00182 __STATIC_INLINE void LL_C1_IPCC_DisableIT_RXO(IPCC_TypeDef *IPCCx)
00183 {
00184   CLEAR_BIT(IPCCx->C1CR, IPCC_C1CR_RXOIE);
00185 }
00186
00187 /**
00188   * @brief  Check if Receive channel occupied interrupt for processor 1 is enabled.
00189   * @rmtoll C1CR          RXOIE         LL_C1_IPCC_IsEnabledIT_RXO
00190   * @param  IPCCx IPCC Instance.
00191   * @retval State of bit (1 or 0).
00192   */
00193 __STATIC_INLINE uint32_t LL_C1_IPCC_IsEnabledIT_RXO(IPCC_TypeDef  const *const IPCCx)
00194 {
00195   return ((READ_BIT(IPCCx->C1CR, IPCC_C1CR_RXOIE) == (IPCC_C1CR_RXOIE)) ? 1UL : 0UL);
00196 }
00197
00198 /**
00199   * @brief  Enable Transmit channel free interrupt for processor 2.
00200   * @rmtoll C2CR          TXFIE         LL_C2_IPCC_EnableIT_TXF
00201   * @param  IPCCx IPCC Instance.
00202   * @retval None
00203   */
00204 __STATIC_INLINE void LL_C2_IPCC_EnableIT_TXF(IPCC_TypeDef *IPCCx)
00205 {
00206   SET_BIT(IPCCx->C2CR, IPCC_C2CR_TXFIE);
00207 }
00208
00209 /**
00210   * @brief  Disable Transmit channel free interrupt for processor 2.
00211   * @rmtoll C2CR          TXFIE         LL_C2_IPCC_DisableIT_TXF
00212   * @param  IPCCx IPCC Instance.
00213   * @retval None
00214   */
00215 __STATIC_INLINE void LL_C2_IPCC_DisableIT_TXF(IPCC_TypeDef *IPCCx)
00216 {
00217   CLEAR_BIT(IPCCx->C2CR, IPCC_C2CR_TXFIE);
00218 }
00219
00220 /**
00221   * @brief  Check if Transmit channel free interrupt for processor 2 is enabled.
00222   * @rmtoll C2CR          TXFIE         LL_C2_IPCC_IsEnabledIT_TXF
00223   * @param  IPCCx IPCC Instance.
00224   * @retval State of bit (1 or 0).
00225   */
00226 __STATIC_INLINE uint32_t LL_C2_IPCC_IsEnabledIT_TXF(IPCC_TypeDef  const *const IPCCx)
00227 {
00228   return ((READ_BIT(IPCCx->C2CR, IPCC_C2CR_TXFIE) == (IPCC_C2CR_TXFIE)) ? 1UL : 0UL);
00229 }
00230
00231 /**
00232   * @brief  Enable Receive channel occupied interrupt for processor 2.
00233   * @rmtoll C2CR          RXOIE         LL_C2_IPCC_EnableIT_RXO
00234   * @param  IPCCx IPCC Instance.
00235   * @retval None
00236   */
00237 __STATIC_INLINE void LL_C2_IPCC_EnableIT_RXO(IPCC_TypeDef *IPCCx)
00238 {
00239   SET_BIT(IPCCx->C2CR, IPCC_C2CR_RXOIE);
00240 }
00241
00242 /**
00243   * @brief  Disable Receive channel occupied interrupt for processor 2.
00244   * @rmtoll C2CR          RXOIE         LL_C2_IPCC_DisableIT_RXO
00245   * @param  IPCCx IPCC Instance.
00246   * @retval None
00247   */
00248 __STATIC_INLINE void LL_C2_IPCC_DisableIT_RXO(IPCC_TypeDef *IPCCx)
00249 {
00250   CLEAR_BIT(IPCCx->C2CR, IPCC_C2CR_RXOIE);
00251 }
00252
00253 /**
00254   * @brief  Check if Receive channel occupied interrupt for processor 2 is enabled.
00255   * @rmtoll C2CR          RXOIE         LL_C2_IPCC_IsEnabledIT_RXO
00256   * @param  IPCCx IPCC Instance.
00257   * @retval State of bit (1 or 0).
00258   */
00259 __STATIC_INLINE uint32_t LL_C2_IPCC_IsEnabledIT_RXO(IPCC_TypeDef const *const IPCCx)
00260 {
00261   return ((READ_BIT(IPCCx->C2CR, IPCC_C2CR_RXOIE) == (IPCC_C2CR_RXOIE)) ? 1UL : 0UL);
00262 }
00263
00264 /**
00265   * @}
00266   */
00267
00268 /** @defgroup IPCC_LL_EF_Configuration Configuration
00269   * @{
00270   */
00271
00272 /**
00273   * @brief  Unmask transmit channel free interrupt for processor 1.
00274   * @rmtoll C1MR        CH1FM           LL_C1_IPCC_EnableTransmitChannel\n
00275   *         C1MR        CH2FM           LL_C1_IPCC_EnableTransmitChannel\n
00276   *         C1MR        CH3FM           LL_C1_IPCC_EnableTransmitChannel\n
00277   *         C1MR        CH4FM           LL_C1_IPCC_EnableTransmitChannel\n
00278   *         C1MR        CH5FM           LL_C1_IPCC_EnableTransmitChannel\n
00279   *         C1MR        CH6FM           LL_C1_IPCC_EnableTransmitChannel
00280   * @param  IPCCx IPCC Instance.
00281   * @param  Channel This parameter can be a combination of the following values:
00282   *         @arg @ref LL_IPCC_CHANNEL_1
00283   *         @arg @ref LL_IPCC_CHANNEL_2
00284   *         @arg @ref LL_IPCC_CHANNEL_3
00285   *         @arg @ref LL_IPCC_CHANNEL_4
00286   *         @arg @ref LL_IPCC_CHANNEL_5
00287   *         @arg @ref LL_IPCC_CHANNEL_6
00288   * @retval None
00289   */
00290 __STATIC_INLINE void LL_C1_IPCC_EnableTransmitChannel(IPCC_TypeDef *IPCCx, uint32_t Channel)
00291 {
00292   CLEAR_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos);
00293 }
00294
00295 /**
00296   * @brief  Mask transmit channel free interrupt for processor 1.
00297   * @rmtoll C1MR        CH1FM           LL_C1_IPCC_DisableTransmitChannel\n
00298   *         C1MR        CH2FM           LL_C1_IPCC_DisableTransmitChannel\n
00299   *         C1MR        CH3FM           LL_C1_IPCC_DisableTransmitChannel\n
00300   *         C1MR        CH4FM           LL_C1_IPCC_DisableTransmitChannel\n
00301   *         C1MR        CH5FM           LL_C1_IPCC_DisableTransmitChannel\n
00302   *         C1MR        CH6FM           LL_C1_IPCC_DisableTransmitChannel
00303   * @param  IPCCx IPCC Instance.
00304   * @param  Channel This parameter can be a combination of the following values:
00305   *         @arg @ref LL_IPCC_CHANNEL_1
00306   *         @arg @ref LL_IPCC_CHANNEL_2
00307   *         @arg @ref LL_IPCC_CHANNEL_3
00308   *         @arg @ref LL_IPCC_CHANNEL_4
00309   *         @arg @ref LL_IPCC_CHANNEL_5
00310   *         @arg @ref LL_IPCC_CHANNEL_6
00311   * @retval None
00312   */
00313 __STATIC_INLINE void LL_C1_IPCC_DisableTransmitChannel(IPCC_TypeDef *IPCCx, uint32_t Channel)
00314 {
00315   SET_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos);
00316 }
00317
00318 /**
00319   * @brief  Check if Transmit channel free interrupt for processor 1 is masked.
00320   * @rmtoll C1MR        CH1FM           LL_C1_IPCC_IsEnabledTransmitChannel\n
00321   *         C1MR        CH2FM           LL_C1_IPCC_IsEnabledTransmitChannel\n
00322   *         C1MR        CH3FM           LL_C1_IPCC_IsEnabledTransmitChannel\n
00323   *         C1MR        CH4FM           LL_C1_IPCC_IsEnabledTransmitChannel\n
00324   *         C1MR        CH5FM           LL_C1_IPCC_IsEnabledTransmitChannel\n
00325   *         C1MR        CH6FM           LL_C1_IPCC_IsEnabledTransmitChannel
00326   * @param  IPCCx IPCC Instance.
00327   * @param  Channel This parameter can be one of the following values:
00328   *         @arg @ref LL_IPCC_CHANNEL_1
00329   *         @arg @ref LL_IPCC_CHANNEL_2
00330   *         @arg @ref LL_IPCC_CHANNEL_3
00331   *         @arg @ref LL_IPCC_CHANNEL_4
00332   *         @arg @ref LL_IPCC_CHANNEL_5
00333   *         @arg @ref LL_IPCC_CHANNEL_6
00334   * @retval State of bit (1 or 0).
00335   */
00336 __STATIC_INLINE uint32_t LL_C1_IPCC_IsEnabledTransmitChannel(IPCC_TypeDef const *const IPCCx, uint32_t Channel)
00337 {
00338   return ((READ_BIT(IPCCx->C1MR, Channel << IPCC_C1MR_CH1FM_Pos) != (Channel << IPCC_C1MR_CH1FM_Pos)) ? 1UL : 0UL);
00339 }
00340
00341 /**
00342   * @brief  Unmask receive channel occupied interrupt for processor 1.
00343   * @rmtoll C1MR        CH1OM           LL_C1_IPCC_EnableReceiveChannel\n
00344   *         C1MR        CH2OM           LL_C1_IPCC_EnableReceiveChannel\n
00345   *         C1MR        CH3OM           LL_C1_IPCC_EnableReceiveChannel\n
00346   *         C1MR        CH4OM           LL_C1_IPCC_EnableReceiveChannel\n
00347   *         C1MR        CH5OM           LL_C1_IPCC_EnableReceiveChannel\n
00348   *         C1MR        CH6OM           LL_C1_IPCC_EnableReceiveChannel
00349   * @param  IPCCx IPCC Instance.
00350   * @param  Channel This parameter can be a combination of the following values:
00351   *         @arg @ref LL_IPCC_CHANNEL_1
00352   *         @arg @ref LL_IPCC_CHANNEL_2
00353   *         @arg @ref LL_IPCC_CHANNEL_3
00354   *         @arg @ref LL_IPCC_CHANNEL_4
00355   *         @arg @ref LL_IPCC_CHANNEL_5
00356   *         @arg @ref LL_IPCC_CHANNEL_6
00357   * @retval None
00358   */
00359 __STATIC_INLINE void LL_C1_IPCC_EnableReceiveChannel(IPCC_TypeDef *IPCCx, uint32_t Channel)
00360 {
00361   CLEAR_BIT(IPCCx->C1MR, Channel);
00362 }
00363
00364 /**
00365   * @brief  Mask receive channel occupied interrupt for processor 1.
00366   * @rmtoll C1MR        CH1OM           LL_C1_IPCC_DisableReceiveChannel\n
00367   *         C1MR        CH2OM           LL_C1_IPCC_DisableReceiveChannel\n
00368   *         C1MR        CH3OM           LL_C1_IPCC_DisableReceiveChannel\n
00369   *         C1MR        CH4OM           LL_C1_IPCC_DisableReceiveChannel\n
00370   *         C1MR        CH5OM           LL_C1_IPCC_DisableReceiveChannel\n
00371   *         C1MR        CH6OM           LL_C1_IPCC_DisableReceiveChannel
00372   * @param  IPCCx IPCC Instance.
00373   * @param  Channel This parameter can be a combination of the following values:
00374   *         @arg @ref LL_IPCC_CHANNEL_1
00375   *         @arg @ref LL_IPCC_CHANNEL_2
00376   *         @arg @ref LL_IPCC_CHANNEL_3
00377   *         @arg @ref LL_IPCC_CHANNEL_4
00378   *         @arg @ref LL_IPCC_CHANNEL_5
00379   *         @arg @ref LL_IPCC_CHANNEL_6
00380   * @retval None
00381   */
00382 __STATIC_INLINE void LL_C1_IPCC_DisableReceiveChannel(IPCC_TypeDef *IPCCx, uint32_t Channel)
00383 {
00384   SET_BIT(IPCCx->C1MR, Channel);
00385 }
00386
00387 /**
00388   * @brief  Check if Receive channel occupied interrupt for processor 1 is masked.
00389   * @rmtoll C1MR        CH1OM           LL_C1_IPCC_IsEnabledReceiveChannel\n
00390   *         C1MR        CH2OM           LL_C1_IPCC_IsEnabledReceiveChannel\n
00391   *         C1MR        CH3OM           LL_C1_IPCC_IsEnabledReceiveChannel\n
00392   *         C1MR        CH4OM           LL_C1_IPCC_IsEnabledReceiveChannel\n
00393   *         C1MR        CH5OM           LL_C1_IPCC_IsEnabledReceiveChannel\n
00394   *         C1MR        CH6OM           LL_C1_IPCC_IsEnabledReceiveChannel
00395   * @param  IPCCx IPCC Instance.
00396   * @param  Channel This parameter can be one of the following values:
00397   *         @arg @ref LL_IPCC_CHANNEL_1
00398   *         @arg @ref LL_IPCC_CHANNEL_2
00399   *         @arg @ref LL_IPCC_CHANNEL_3
00400   *         @arg @ref LL_IPCC_CHANNEL_4
00401   *         @arg @ref LL_IPCC_CHANNEL_5
00402   *         @arg @ref LL_IPCC_CHANNEL_6
00403   * @retval State of bit (1 or 0).
00404   */
00405 __STATIC_INLINE uint32_t LL_C1_IPCC_IsEnabledReceiveChannel(IPCC_TypeDef const *const IPCCx, uint32_t Channel)
00406 {
00407   return ((READ_BIT(IPCCx->C1MR, Channel) != (Channel)) ? 1UL : 0UL);
00408 }
00409
00410 /**
00411   * @brief  Unmask transmit channel free interrupt for processor 2.
00412   * @rmtoll C2MR        CH1FM           LL_C2_IPCC_EnableTransmitChannel\n
00413   *         C2MR        CH2FM           LL_C2_IPCC_EnableTransmitChannel\n
00414   *         C2MR        CH3FM           LL_C2_IPCC_EnableTransmitChannel\n
00415   *         C2MR        CH4FM           LL_C2_IPCC_EnableTransmitChannel\n
00416   *         C2MR        CH5FM           LL_C2_IPCC_EnableTransmitChannel\n
00417   *         C2MR        CH6FM           LL_C2_IPCC_EnableTransmitChannel
00418   * @param  IPCCx IPCC Instance.
00419   * @param  Channel This parameter can be a combination of the following values:
00420   *         @arg @ref LL_IPCC_CHANNEL_1
00421   *         @arg @ref LL_IPCC_CHANNEL_2
00422   *         @arg @ref LL_IPCC_CHANNEL_3
00423   *         @arg @ref LL_IPCC_CHANNEL_4
00424   *         @arg @ref LL_IPCC_CHANNEL_5
00425   *         @arg @ref LL_IPCC_CHANNEL_6
00426   * @retval None
00427   */
00428 __STATIC_INLINE void LL_C2_IPCC_EnableTransmitChannel(IPCC_TypeDef *IPCCx, uint32_t Channel)
00429 {
00430   CLEAR_BIT(IPCCx->C2MR, Channel << IPCC_C2MR_CH1FM_Pos);
00431 }
00432
00433 /**
00434   * @brief  Mask transmit channel free interrupt for processor 2.
00435   * @rmtoll C2MR        CH1FM           LL_C2_IPCC_DisableTransmitChannel\n
00436   *         C2MR        CH2FM           LL_C2_IPCC_DisableTransmitChannel\n
00437   *         C2MR        CH3FM           LL_C2_IPCC_DisableTransmitChannel\n
00438   *         C2MR        CH4FM           LL_C2_IPCC_DisableTransmitChannel\n
00439   *         C2MR        CH5FM           LL_C2_IPCC_DisableTransmitChannel\n
00440   *         C2MR        CH6FM           LL_C2_IPCC_DisableTransmitChannel
00441   * @param  IPCCx IPCC Instance.
00442   * @param  Channel This parameter can be a combination of the following values:
00443   *         @arg @ref LL_IPCC_CHANNEL_1
00444   *         @arg @ref LL_IPCC_CHANNEL_2
00445   *         @arg @ref LL_IPCC_CHANNEL_3
00446   *         @arg @ref LL_IPCC_CHANNEL_4
00447   *         @arg @ref LL_IPCC_CHANNEL_5
00448   *         @arg @ref LL_IPCC_CHANNEL_6
00449   * @retval None
00450   */
00451 __STATIC_INLINE void LL_C2_IPCC_DisableTransmitChannel(IPCC_TypeDef *IPCCx, uint32_t Channel)
00452 {
00453   SET_BIT(IPCCx->C2MR, Channel << (IPCC_C2MR_CH1FM_Pos));
00454 }
00455
00456 /**
00457   * @brief  Check if Transmit channel free interrupt for processor 2 is masked.
00458   * @rmtoll C2MR        CH1FM           LL_C2_IPCC_IsEnabledTransmitChannel\n
00459   *         C2MR        CH2FM           LL_C2_IPCC_IsEnabledTransmitChannel\n
00460   *         C2MR        CH3FM           LL_C2_IPCC_IsEnabledTransmitChannel\n
00461   *         C2MR        CH4FM           LL_C2_IPCC_IsEnabledTransmitChannel\n
00462   *         C2MR        CH5FM           LL_C2_IPCC_IsEnabledTransmitChannel\n
00463   *         C2MR        CH6FM           LL_C2_IPCC_IsEnabledTransmitChannel
00464   * @param  IPCCx IPCC Instance.
00465   * @param  Channel This parameter can be one of the following values:
00466   *         @arg @ref LL_IPCC_CHANNEL_1
00467   *         @arg @ref LL_IPCC_CHANNEL_2
00468   *         @arg @ref LL_IPCC_CHANNEL_3
00469   *         @arg @ref LL_IPCC_CHANNEL_4
00470   *         @arg @ref LL_IPCC_CHANNEL_5
00471   *         @arg @ref LL_IPCC_CHANNEL_6
00472   * @retval State of bit (1 or 0).
00473   */
00474 __STATIC_INLINE uint32_t LL_C2_IPCC_IsEnabledTransmitChannel(IPCC_TypeDef const *const IPCCx, uint32_t Channel)
00475 {
00476   return ((READ_BIT(IPCCx->C2MR, Channel << IPCC_C2MR_CH1FM_Pos) != (Channel << IPCC_C2MR_CH1FM_Pos)) ? 1UL : 0UL);
00477 }
00478
00479 /**
00480   * @brief  Unmask receive channel occupied interrupt for processor 2.
00481   * @rmtoll C2MR        CH1OM           LL_C2_IPCC_EnableReceiveChannel\n
00482   *         C2MR        CH2OM           LL_C2_IPCC_EnableReceiveChannel\n
00483   *         C2MR        CH3OM           LL_C2_IPCC_EnableReceiveChannel\n
00484   *         C2MR        CH4OM           LL_C2_IPCC_EnableReceiveChannel\n
00485   *         C2MR        CH5OM           LL_C2_IPCC_EnableReceiveChannel\n
00486   *         C2MR        CH6OM           LL_C2_IPCC_EnableReceiveChannel
00487   * @param  IPCCx IPCC Instance.
00488   * @param  Channel This parameter can be a combination of the following values:
00489   *         @arg @ref LL_IPCC_CHANNEL_1
00490   *         @arg @ref LL_IPCC_CHANNEL_2
00491   *         @arg @ref LL_IPCC_CHANNEL_3
00492   *         @arg @ref LL_IPCC_CHANNEL_4
00493   *         @arg @ref LL_IPCC_CHANNEL_5
00494   *         @arg @ref LL_IPCC_CHANNEL_6
00495   * @retval None
00496   */
00497 __STATIC_INLINE void LL_C2_IPCC_EnableReceiveChannel(IPCC_TypeDef *IPCCx, uint32_t Channel)
00498 {
00499   CLEAR_BIT(IPCCx->C2MR, Channel);
00500 }
00501
00502 /**
00503   * @brief  Mask receive channel occupied interrupt for processor 1.
00504   * @rmtoll C2MR        CH1OM           LL_C2_IPCC_DisableReceiveChannel\n
00505   *         C2MR        CH2OM           LL_C2_IPCC_DisableReceiveChannel\n
00506   *         C2MR        CH3OM           LL_C2_IPCC_DisableReceiveChannel\n
00507   *         C2MR        CH4OM           LL_C2_IPCC_DisableReceiveChannel\n
00508   *         C2MR        CH5OM           LL_C2_IPCC_DisableReceiveChannel\n
00509   *         C2MR        CH6OM           LL_C2_IPCC_DisableReceiveChannel
00510   * @param  IPCCx IPCC Instance.
00511   * @param  Channel This parameter can be a combination of the following values:
00512   *         @arg @ref LL_IPCC_CHANNEL_1
00513   *         @arg @ref LL_IPCC_CHANNEL_2
00514   *         @arg @ref LL_IPCC_CHANNEL_3
00515   *         @arg @ref LL_IPCC_CHANNEL_4
00516   *         @arg @ref LL_IPCC_CHANNEL_5
00517   *         @arg @ref LL_IPCC_CHANNEL_6
00518   * @retval None
00519   */
00520 __STATIC_INLINE void LL_C2_IPCC_DisableReceiveChannel(IPCC_TypeDef *IPCCx, uint32_t Channel)
00521 {
00522   SET_BIT(IPCCx->C2MR, Channel);
00523 }
00524
00525 /**
00526   * @brief  Check if Receive channel occupied interrupt for processor 2 is masked.
00527   * @rmtoll C2MR        CH1OM           LL_C2_IPCC_IsEnabledReceiveChannel\n
00528   *         C2MR        CH2OM           LL_C2_IPCC_IsEnabledReceiveChannel\n
00529   *         C2MR        CH3OM           LL_C2_IPCC_IsEnabledReceiveChannel\n
00530   *         C2MR        CH4OM           LL_C2_IPCC_IsEnabledReceiveChannel\n
00531   *         C2MR        CH5OM           LL_C2_IPCC_IsEnabledReceiveChannel\n
00532   *         C2MR        CH6OM           LL_C2_IPCC_IsEnabledReceiveChannel
00533   * @param  IPCCx IPCC Instance.
00534   * @param  Channel This parameter can be one of the following values:
00535   *         @arg @ref LL_IPCC_CHANNEL_1
00536   *         @arg @ref LL_IPCC_CHANNEL_2
00537   *         @arg @ref LL_IPCC_CHANNEL_3
00538   *         @arg @ref LL_IPCC_CHANNEL_4
00539   *         @arg @ref LL_IPCC_CHANNEL_5
00540   *         @arg @ref LL_IPCC_CHANNEL_6
00541   * @retval State of bit (1 or 0).
00542   */
00543 __STATIC_INLINE uint32_t LL_C2_IPCC_IsEnabledReceiveChannel(IPCC_TypeDef const *const IPCCx, uint32_t Channel)
00544 {
00545   return ((READ_BIT(IPCCx->C2MR, Channel) != (Channel)) ? 1UL : 0UL);
00546 }
00547
00548 /**
00549   * @}
00550   */
00551
00552 /** @defgroup IPCC_LL_EF_FLAG_Management FLAG_Management
00553   * @{
00554   */
00555
00556 /**
00557   * @brief  Clear IPCC receive channel status for processor 1.
00558   * @note   Associated with IPCC_C2TOC1SR.CHxF
00559   * @rmtoll C1SCR        CH1C           LL_C1_IPCC_ClearFlag_CHx\n
00560   *         C1SCR        CH2C           LL_C1_IPCC_ClearFlag_CHx\n
00561   *         C1SCR        CH3C           LL_C1_IPCC_ClearFlag_CHx\n
00562   *         C1SCR        CH4C           LL_C1_IPCC_ClearFlag_CHx\n
00563   *         C1SCR        CH5C           LL_C1_IPCC_ClearFlag_CHx\n
00564   *         C1SCR        CH6C           LL_C1_IPCC_ClearFlag_CHx
00565   * @param  IPCCx IPCC Instance.
00566   * @param  Channel This parameter can be a combination of the following values:
00567   *         @arg @ref LL_IPCC_CHANNEL_1
00568   *         @arg @ref LL_IPCC_CHANNEL_2
00569   *         @arg @ref LL_IPCC_CHANNEL_3
00570   *         @arg @ref LL_IPCC_CHANNEL_4
00571   *         @arg @ref LL_IPCC_CHANNEL_5
00572   *         @arg @ref LL_IPCC_CHANNEL_6
00573   * @retval None
00574   */
00575 __STATIC_INLINE void LL_C1_IPCC_ClearFlag_CHx(IPCC_TypeDef *IPCCx, uint32_t Channel)
00576 {
00577   WRITE_REG(IPCCx->C1SCR, Channel);
00578 }
00579
00580 /**
00581   * @brief  Set IPCC transmit channel status for processor 1.
00582   * @note   Associated with IPCC_C1TOC2SR.CHxF
00583   * @rmtoll C1SCR        CH1S           LL_C1_IPCC_SetFlag_CHx\n
00584   *         C1SCR        CH2S           LL_C1_IPCC_SetFlag_CHx\n
00585   *         C1SCR        CH3S           LL_C1_IPCC_SetFlag_CHx\n
00586   *         C1SCR        CH4S           LL_C1_IPCC_SetFlag_CHx\n
00587   *         C1SCR        CH5S           LL_C1_IPCC_SetFlag_CHx\n
00588   *         C1SCR        CH6S           LL_C1_IPCC_SetFlag_CHx
00589   * @param  IPCCx IPCC Instance.
00590   * @param  Channel This parameter can be a combination of the following values:
00591   *         @arg @ref LL_IPCC_CHANNEL_1
00592   *         @arg @ref LL_IPCC_CHANNEL_2
00593   *         @arg @ref LL_IPCC_CHANNEL_3
00594   *         @arg @ref LL_IPCC_CHANNEL_4
00595   *         @arg @ref LL_IPCC_CHANNEL_5
00596   *         @arg @ref LL_IPCC_CHANNEL_6
00597   * @retval None
00598   */
00599 __STATIC_INLINE void LL_C1_IPCC_SetFlag_CHx(IPCC_TypeDef *IPCCx, uint32_t Channel)
00600 {
00601   WRITE_REG(IPCCx->C1SCR, Channel << IPCC_C1SCR_CH1S_Pos);
00602 }
00603
00604 /**
00605   * @brief  Get channel status for processor 1.
00606   * @rmtoll C1TOC2SR        CH1F           LL_C1_IPCC_IsActiveFlag_CHx\n
00607   *         C1TOC2SR        CH2F           LL_C1_IPCC_IsActiveFlag_CHx\n
00608   *         C1TOC2SR        CH3F           LL_C1_IPCC_IsActiveFlag_CHx\n
00609   *         C1TOC2SR        CH4F           LL_C1_IPCC_IsActiveFlag_CHx\n
00610   *         C1TOC2SR        CH5F           LL_C1_IPCC_IsActiveFlag_CHx\n
00611   *         C1TOC2SR        CH6F           LL_C1_IPCC_IsActiveFlag_CHx
00612   * @param  IPCCx IPCC Instance.
00613   * @param  Channel This parameter can be one of the following values:
00614   *         @arg @ref LL_IPCC_CHANNEL_1
00615   *         @arg @ref LL_IPCC_CHANNEL_2
00616   *         @arg @ref LL_IPCC_CHANNEL_3
00617   *         @arg @ref LL_IPCC_CHANNEL_4
00618   *         @arg @ref LL_IPCC_CHANNEL_5
00619   *         @arg @ref LL_IPCC_CHANNEL_6
00620   * @retval State of bit (1 or 0).
00621   */
00622 __STATIC_INLINE uint32_t LL_C1_IPCC_IsActiveFlag_CHx(IPCC_TypeDef  const *const IPCCx, uint32_t Channel)
00623 {
00624   return ((READ_BIT(IPCCx->C1TOC2SR, Channel) == (Channel)) ? 1UL : 0UL);
00625 }
00626
00627 /**
00628   * @brief  Clear IPCC receive channel status for processor 2.
00629   * @note   Associated with IPCC_C1TOC2SR.CHxF
00630   * @rmtoll C2SCR        CH1C           LL_C2_IPCC_ClearFlag_CHx\n
00631   *         C2SCR        CH2C           LL_C2_IPCC_ClearFlag_CHx\n
00632   *         C2SCR        CH3C           LL_C2_IPCC_ClearFlag_CHx\n
00633   *         C2SCR        CH4C           LL_C2_IPCC_ClearFlag_CHx\n
00634   *         C2SCR        CH5C           LL_C2_IPCC_ClearFlag_CHx\n
00635   *         C2SCR        CH6C           LL_C2_IPCC_ClearFlag_CHx
00636   * @param  IPCCx IPCC Instance.
00637   * @param  Channel This parameter can be a combination of the following values:
00638   *         @arg @ref LL_IPCC_CHANNEL_1
00639   *         @arg @ref LL_IPCC_CHANNEL_2
00640   *         @arg @ref LL_IPCC_CHANNEL_3
00641   *         @arg @ref LL_IPCC_CHANNEL_4
00642   *         @arg @ref LL_IPCC_CHANNEL_5
00643   *         @arg @ref LL_IPCC_CHANNEL_6
00644   * @retval None
00645   */
00646 __STATIC_INLINE void LL_C2_IPCC_ClearFlag_CHx(IPCC_TypeDef *IPCCx, uint32_t Channel)
00647 {
00648   WRITE_REG(IPCCx->C2SCR, Channel);
00649 }
00650
00651 /**
00652   * @brief  Set IPCC transmit channel status for processor 2.
00653   * @note   Associated with IPCC_C2TOC1SR.CHxF
00654   * @rmtoll C2SCR        CH1S           LL_C2_IPCC_SetFlag_CHx\n
00655   *         C2SCR        CH2S           LL_C2_IPCC_SetFlag_CHx\n
00656   *         C2SCR        CH3S           LL_C2_IPCC_SetFlag_CHx\n
00657   *         C2SCR        CH4S           LL_C2_IPCC_SetFlag_CHx\n
00658   *         C2SCR        CH5S           LL_C2_IPCC_SetFlag_CHx\n
00659   *         C2SCR        CH6S           LL_C2_IPCC_SetFlag_CHx
00660   * @param  IPCCx IPCC Instance.
00661   * @param  Channel This parameter can be a combination of the following values:
00662   *         @arg @ref LL_IPCC_CHANNEL_1
00663   *         @arg @ref LL_IPCC_CHANNEL_2
00664   *         @arg @ref LL_IPCC_CHANNEL_3
00665   *         @arg @ref LL_IPCC_CHANNEL_4
00666   *         @arg @ref LL_IPCC_CHANNEL_5
00667   *         @arg @ref LL_IPCC_CHANNEL_6
00668   * @retval None
00669   */
00670 __STATIC_INLINE void LL_C2_IPCC_SetFlag_CHx(IPCC_TypeDef *IPCCx, uint32_t Channel)
00671 {
00672   WRITE_REG(IPCCx->C2SCR, Channel << IPCC_C2SCR_CH1S_Pos);
00673 }
00674
00675 /**
00676   * @brief  Get channel status for processor 2.
00677   * @rmtoll C2TOC1SR        CH1F           LL_C2_IPCC_IsActiveFlag_CHx\n
00678   *         C2TOC1SR        CH2F           LL_C2_IPCC_IsActiveFlag_CHx\n
00679   *         C2TOC1SR        CH3F           LL_C2_IPCC_IsActiveFlag_CHx\n
00680   *         C2TOC1SR        CH4F           LL_C2_IPCC_IsActiveFlag_CHx\n
00681   *         C2TOC1SR        CH5F           LL_C2_IPCC_IsActiveFlag_CHx\n
00682   *         C2TOC1SR        CH6F           LL_C2_IPCC_IsActiveFlag_CHx
00683   * @param  IPCCx IPCC Instance.
00684   * @param  Channel This parameter can be one of the following values:
00685   *         @arg @ref LL_IPCC_CHANNEL_1
00686   *         @arg @ref LL_IPCC_CHANNEL_2
00687   *         @arg @ref LL_IPCC_CHANNEL_3
00688   *         @arg @ref LL_IPCC_CHANNEL_4
00689   *         @arg @ref LL_IPCC_CHANNEL_5
00690   *         @arg @ref LL_IPCC_CHANNEL_6
00691   * @retval State of bit (1 or 0).
00692   */
00693 __STATIC_INLINE uint32_t LL_C2_IPCC_IsActiveFlag_CHx(IPCC_TypeDef  const *const IPCCx, uint32_t Channel)
00694 {
00695   return ((READ_BIT(IPCCx->C2TOC1SR, Channel) == (Channel)) ? 1UL : 0UL);
00696 }
00697
00698 /**
00699   * @}
00700   */
00701
00702
00703 /**
00704   * @}
00705   */
00706
00707 /**
00708   * @}
00709   */
00710
00711 #endif /* defined(IPCC) */
00712
00713 /**
00714   * @}
00715   */
00716
00717 #ifdef __cplusplus
00718 }
00719 #endif
00720
00721 #endif /* STM32WBxx_LL_IPCC_H */
00722
00723 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_iwdg.h Source File

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stm32wbxx_ll_iwdg.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_iwdg.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of IWDG LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_LL_IWDG_H
00022 #define STM32WBxx_LL_IWDG_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx.h"
00030
00031 /** @addtogroup STM32WBxx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined(IWDG)
00036
00037 /** @defgroup IWDG_LL IWDG
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043
00044 /* Private constants ---------------------------------------------------------*/
00045 /** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
00046   * @{
00047   */
00048 #define LL_IWDG_KEY_RELOAD                 0x0000AAAAU               /*!< IWDG Reload Counter Enable   */
00049 #define LL_IWDG_KEY_ENABLE                 0x0000CCCCU               /*!< IWDG Peripheral Enable       */
00050 #define LL_IWDG_KEY_WR_ACCESS_ENABLE       0x00005555U               /*!< IWDG KR Write Access Enable  */
00051 #define LL_IWDG_KEY_WR_ACCESS_DISABLE      0x00000000U               /*!< IWDG KR Write Access Disable */
00052 /**
00053   * @}
00054   */
00055
00056 /* Private macros ------------------------------------------------------------*/
00057
00058 /* Exported types ------------------------------------------------------------*/
00059 /* Exported constants --------------------------------------------------------*/
00060 /** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants
00061   * @{
00062   */
00063
00064 /** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines
00065   * @brief    Flags defines which can be used with LL_IWDG_ReadReg function
00066   * @{
00067   */
00068 #define LL_IWDG_SR_PVU                     IWDG_SR_PVU                           /*!< Watchdog prescaler value update */
00069 #define LL_IWDG_SR_RVU                     IWDG_SR_RVU                           /*!< Watchdog counter reload value update */
00070 #define LL_IWDG_SR_WVU                     IWDG_SR_WVU                           /*!< Watchdog counter window value update */
00071 /**
00072   * @}
00073   */
00074
00075 /** @defgroup IWDG_LL_EC_PRESCALER  Prescaler Divider
00076   * @{
00077   */
00078 #define LL_IWDG_PRESCALER_4                0x00000000U                           /*!< Divider by 4   */
00079 #define LL_IWDG_PRESCALER_8                (IWDG_PR_PR_0)                        /*!< Divider by 8   */
00080 #define LL_IWDG_PRESCALER_16               (IWDG_PR_PR_1)                        /*!< Divider by 16  */
00081 #define LL_IWDG_PRESCALER_32               (IWDG_PR_PR_1 | IWDG_PR_PR_0)         /*!< Divider by 32  */
00082 #define LL_IWDG_PRESCALER_64               (IWDG_PR_PR_2)                        /*!< Divider by 64  */
00083 #define LL_IWDG_PRESCALER_128              (IWDG_PR_PR_2 | IWDG_PR_PR_0)         /*!< Divider by 128 */
00084 #define LL_IWDG_PRESCALER_256              (IWDG_PR_PR_2 | IWDG_PR_PR_1)         /*!< Divider by 256 */
00085 /**
00086   * @}
00087   */
00088
00089 /**
00090   * @}
00091   */
00092
00093 /* Exported macro ------------------------------------------------------------*/
00094 /** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros
00095   * @{
00096   */
00097
00098 /** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros
00099   * @{
00100   */
00101
00102 /**
00103   * @brief  Write a value in IWDG register
00104   * @param  __INSTANCE__ IWDG Instance
00105   * @param  __REG__ Register to be written
00106   * @param  __VALUE__ Value to be written in the register
00107   * @retval None
00108   */
00109 #define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00110
00111 /**
00112   * @brief  Read a value in IWDG register
00113   * @param  __INSTANCE__ IWDG Instance
00114   * @param  __REG__ Register to be read
00115   * @retval Register value
00116   */
00117 #define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00118 /**
00119   * @}
00120   */
00121
00122 /**
00123   * @}
00124   */
00125
00126
00127 /* Exported functions --------------------------------------------------------*/
00128 /** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions
00129   * @{
00130   */
00131 /** @defgroup IWDG_LL_EF_Configuration Configuration
00132   * @{
00133   */
00134
00135 /**
00136   * @brief  Start the Independent Watchdog
00137   * @note   Except if the hardware watchdog option is selected
00138   * @rmtoll KR           KEY           LL_IWDG_Enable
00139   * @param  IWDGx IWDG Instance
00140   * @retval None
00141   */
00142 __STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
00143 {
00144   WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE);
00145 }
00146
00147 /**
00148   * @brief  Reloads IWDG counter with value defined in the reload register
00149   * @rmtoll KR           KEY           LL_IWDG_ReloadCounter
00150   * @param  IWDGx IWDG Instance
00151   * @retval None
00152   */
00153 __STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
00154 {
00155   WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD);
00156 }
00157
00158 /**
00159   * @brief  Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
00160   * @rmtoll KR           KEY           LL_IWDG_EnableWriteAccess
00161   * @param  IWDGx IWDG Instance
00162   * @retval None
00163   */
00164 __STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
00165 {
00166   WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
00167 }
00168
00169 /**
00170   * @brief  Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
00171   * @rmtoll KR           KEY           LL_IWDG_DisableWriteAccess
00172   * @param  IWDGx IWDG Instance
00173   * @retval None
00174   */
00175 __STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
00176 {
00177   WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
00178 }
00179
00180 /**
00181   * @brief  Select the prescaler of the IWDG
00182   * @rmtoll PR           PR            LL_IWDG_SetPrescaler
00183   * @param  IWDGx IWDG Instance
00184   * @param  Prescaler This parameter can be one of the following values:
00185   *         @arg @ref LL_IWDG_PRESCALER_4
00186   *         @arg @ref LL_IWDG_PRESCALER_8
00187   *         @arg @ref LL_IWDG_PRESCALER_16
00188   *         @arg @ref LL_IWDG_PRESCALER_32
00189   *         @arg @ref LL_IWDG_PRESCALER_64
00190   *         @arg @ref LL_IWDG_PRESCALER_128
00191   *         @arg @ref LL_IWDG_PRESCALER_256
00192   * @retval None
00193   */
00194 __STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler)
00195 {
00196   WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler);
00197 }
00198
00199 /**
00200   * @brief  Get the selected prescaler of the IWDG
00201   * @rmtoll PR           PR            LL_IWDG_GetPrescaler
00202   * @param  IWDGx IWDG Instance
00203   * @retval Returned value can be one of the following values:
00204   *         @arg @ref LL_IWDG_PRESCALER_4
00205   *         @arg @ref LL_IWDG_PRESCALER_8
00206   *         @arg @ref LL_IWDG_PRESCALER_16
00207   *         @arg @ref LL_IWDG_PRESCALER_32
00208   *         @arg @ref LL_IWDG_PRESCALER_64
00209   *         @arg @ref LL_IWDG_PRESCALER_128
00210   *         @arg @ref LL_IWDG_PRESCALER_256
00211   */
00212 __STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)
00213 {
00214   return (READ_REG(IWDGx->PR));
00215 }
00216
00217 /**
00218   * @brief  Specify the IWDG down-counter reload value
00219   * @rmtoll RLR          RL            LL_IWDG_SetReloadCounter
00220   * @param  IWDGx IWDG Instance
00221   * @param  Counter Value between Min_Data=0 and Max_Data=0x0FFF
00222   * @retval None
00223   */
00224 __STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter)
00225 {
00226   WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter);
00227 }
00228
00229 /**
00230   * @brief  Get the specified IWDG down-counter reload value
00231   * @rmtoll RLR          RL            LL_IWDG_GetReloadCounter
00232   * @param  IWDGx IWDG Instance
00233   * @retval Value between Min_Data=0 and Max_Data=0x0FFF
00234   */
00235 __STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
00236 {
00237   return (READ_REG(IWDGx->RLR));
00238 }
00239
00240 /**
00241   * @brief  Specify high limit of the window value to be compared to the down-counter.
00242   * @rmtoll WINR         WIN           LL_IWDG_SetWindow
00243   * @param  IWDGx IWDG Instance
00244   * @param  Window Value between Min_Data=0 and Max_Data=0x0FFF
00245   * @retval None
00246   */
00247 __STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window)
00248 {
00249   WRITE_REG(IWDGx->WINR, IWDG_WINR_WIN & Window);
00250 }
00251
00252 /**
00253   * @brief  Get the high limit of the window value specified.
00254   * @rmtoll WINR         WIN           LL_IWDG_GetWindow
00255   * @param  IWDGx IWDG Instance
00256   * @retval Value between Min_Data=0 and Max_Data=0x0FFF
00257   */
00258 __STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx)
00259 {
00260   return (READ_REG(IWDGx->WINR));
00261 }
00262
00263 /**
00264   * @}
00265   */
00266
00267 /** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management
00268   * @{
00269   */
00270
00271 /**
00272   * @brief  Check if flag Prescaler Value Update is set or not
00273   * @rmtoll SR           PVU           LL_IWDG_IsActiveFlag_PVU
00274   * @param  IWDGx IWDG Instance
00275   * @retval State of bit (1 or 0).
00276   */
00277 __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
00278 {
00279   return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL);
00280 }
00281
00282 /**
00283   * @brief  Check if flag Reload Value Update is set or not
00284   * @rmtoll SR           RVU           LL_IWDG_IsActiveFlag_RVU
00285   * @param  IWDGx IWDG Instance
00286   * @retval State of bit (1 or 0).
00287   */
00288 __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
00289 {
00290   return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL);
00291 }
00292
00293 /**
00294   * @brief  Check if flag Window Value Update is set or not
00295   * @rmtoll SR           WVU           LL_IWDG_IsActiveFlag_WVU
00296   * @param  IWDGx IWDG Instance
00297   * @retval State of bit (1 or 0).
00298   */
00299 __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx)
00300 {
00301   return ((READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU)) ? 1UL : 0UL);
00302 }
00303
00304 /**
00305   * @brief  Check if all flags Prescaler, Reload & Window Value Update are reset or not
00306   * @rmtoll SR           PVU           LL_IWDG_IsReady\n
00307   *         SR           WVU           LL_IWDG_IsReady\n
00308   *         SR           RVU           LL_IWDG_IsReady
00309   * @param  IWDGx IWDG Instance
00310   * @retval State of bits (1 or 0).
00311   */
00312 __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
00313 {
00314   return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U) ? 1UL : 0UL);
00315 }
00316
00317 /**
00318   * @}
00319   */
00320
00321
00322 /**
00323   * @}
00324   */
00325
00326 /**
00327   * @}
00328   */
00329
00330 #endif /* IWDG */
00331
00332 /**
00333   * @}
00334   */
00335
00336 #ifdef __cplusplus
00337 }
00338 #endif
00339
00340 #endif /* STM32WBxx_LL_IWDG_H */
00341
00342 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_lptim.c Source File

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stm32wbxx_ll_lptim.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_lptim.c
00004   * @author  MCD Application Team
00005   * @brief   LPTIM LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32wbxx_ll_lptim.h"
00023 #include "stm32wbxx_ll_bus.h"
00024 #include "stm32wbxx_ll_rcc.h"
00025
00026
00027 #ifdef  USE_FULL_ASSERT
00028 #include "stm32_assert.h"
00029 #else
00030 #define assert_param(expr) ((void)0U)
00031 #endif
00032
00033 /** @addtogroup STM32WBxx_LL_Driver
00034   * @{
00035   */
00036
00037 #if defined (LPTIM1) || defined (LPTIM2)
00038
00039 /** @addtogroup LPTIM_LL
00040   * @{
00041   */
00042
00043 /* Private types -------------------------------------------------------------*/
00044 /* Private variables ---------------------------------------------------------*/
00045 /* Private constants ---------------------------------------------------------*/
00046 /* Private macros ------------------------------------------------------------*/
00047 /** @addtogroup LPTIM_LL_Private_Macros
00048   * @{
00049   */
00050 #define IS_LL_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \
00051                                           || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL))
00052
00053 #define IS_LL_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1)   \
00054                                              || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2)   \
00055                                              || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4)   \
00056                                              || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8)   \
00057                                              || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16)  \
00058                                              || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32)  \
00059                                              || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64)  \
00060                                              || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128))
00061
00062 #define IS_LL_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \
00063                                       || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE))
00064
00065 #define IS_LL_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \
00066                                              || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE))
00067 /**
00068   * @}
00069   */
00070
00071
00072 /* Private function prototypes -----------------------------------------------*/
00073 /* Private functions ---------------------------------------------------------*/
00074 /** @defgroup LPTIM_Private_Functions LPTIM Private Functions
00075   * @{
00076   */
00077 /**
00078   * @}
00079   */
00080 /* Exported functions --------------------------------------------------------*/
00081 /** @addtogroup LPTIM_LL_Exported_Functions
00082   * @{
00083   */
00084
00085 /** @addtogroup LPTIM_LL_EF_Init
00086   * @{
00087   */
00088
00089 /**
00090   * @brief  Set LPTIMx registers to their reset values.
00091   * @param  LPTIMx LP Timer instance
00092   * @retval An ErrorStatus enumeration value:
00093   *          - SUCCESS: LPTIMx registers are de-initialized
00094   *          - ERROR: invalid LPTIMx instance
00095   */
00096 ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx)
00097 {
00098   ErrorStatus result = SUCCESS;
00099
00100   /* Check the parameters */
00101   assert_param(IS_LPTIM_INSTANCE(LPTIMx));
00102
00103   if (LPTIMx == LPTIM1)
00104   {
00105     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1);
00106     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1);
00107   }
00108 #if defined(LPTIM2)
00109   else if (LPTIMx == LPTIM2)
00110   {
00111     LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPTIM2);
00112     LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPTIM2);
00113   }
00114 #endif /* LPTIM2 */
00115   else
00116   {
00117     result = ERROR;
00118   }
00119
00120   return result;
00121 }
00122
00123 /**
00124   * @brief  Set each fields of the LPTIM_InitStruct structure to its default
00125   *         value.
00126   * @param  LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure
00127   * @retval None
00128   */
00129 void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
00130 {
00131   /* Set the default configuration */
00132   LPTIM_InitStruct->ClockSource = LL_LPTIM_CLK_SOURCE_INTERNAL;
00133   LPTIM_InitStruct->Prescaler   = LL_LPTIM_PRESCALER_DIV1;
00134   LPTIM_InitStruct->Waveform    = LL_LPTIM_OUTPUT_WAVEFORM_PWM;
00135   LPTIM_InitStruct->Polarity    = LL_LPTIM_OUTPUT_POLARITY_REGULAR;
00136 }
00137
00138 /**
00139   * @brief  Configure the LPTIMx peripheral according to the specified parameters.
00140   * @note LL_LPTIM_Init can only be called when the LPTIM instance is disabled.
00141   * @note LPTIMx can be disabled using unitary function @ref LL_LPTIM_Disable().
00142   * @param  LPTIMx LP Timer Instance
00143   * @param  LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure
00144   * @retval An ErrorStatus enumeration value:
00145   *          - SUCCESS: LPTIMx instance has been initialized
00146   *          - ERROR: LPTIMx instance hasn't been initialized
00147   */
00148 ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
00149 {
00150   ErrorStatus result = SUCCESS;
00151   /* Check the parameters */
00152   assert_param(IS_LPTIM_INSTANCE(LPTIMx));
00153   assert_param(IS_LL_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource));
00154   assert_param(IS_LL_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler));
00155   assert_param(IS_LL_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform));
00156   assert_param(IS_LL_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity));
00157
00158   /* The LPTIMx_CFGR register must only be modified when the LPTIM is disabled
00159      (ENABLE bit is reset to 0).
00160   */
00161   if (LL_LPTIM_IsEnabled(LPTIMx) == 1UL)
00162   {
00163     result = ERROR;
00164   }
00165   else
00166   {
00167     /* Set CKSEL bitfield according to ClockSource value */
00168     /* Set PRESC bitfield according to Prescaler value */
00169     /* Set WAVE bitfield according to Waveform value */
00170     /* Set WAVEPOL bitfield according to Polarity value */
00171     MODIFY_REG(LPTIMx->CFGR,
00172                (LPTIM_CFGR_CKSEL | LPTIM_CFGR_PRESC | LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL),
00173                LPTIM_InitStruct->ClockSource | \
00174                LPTIM_InitStruct->Prescaler | \
00175                LPTIM_InitStruct->Waveform | \
00176                LPTIM_InitStruct->Polarity);
00177   }
00178
00179   return result;
00180 }
00181
00182 /**
00183   * @}
00184   */
00185
00186 /**
00187   * @}
00188   */
00189
00190 /**
00191   * @brief  Disable the LPTIM instance
00192   * @rmtoll CR           ENABLE        LL_LPTIM_Disable
00193   * @param  LPTIMx Low-Power Timer instance
00194   * @note   The following sequence is required to solve LPTIM disable HW limitation.
00195   *         Please check Errata Sheet ES0335 for more details under "MCU may remain
00196   *         stuck in LPTIM interrupt when entering Stop mode" section.
00197   * @retval None
00198   */
00199 void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
00200 {
00201   LL_RCC_ClocksTypeDef rcc_clock;
00202   uint32_t tmpclksource = 0;
00203   uint32_t tmpIER;
00204   uint32_t tmpCFGR;
00205   uint32_t tmpCMP;
00206   uint32_t tmpARR;
00207   uint32_t tmpOR;
00208
00209   /* Check the parameters */
00210   assert_param(IS_LPTIM_INSTANCE(LPTIMx));
00211
00212   __disable_irq();
00213
00214   /********** Save LPTIM Config *********/
00215   /* Save LPTIM source clock */
00216   switch ((uint32_t)LPTIMx)
00217   {
00218      case LPTIM1_BASE:
00219        tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE);
00220        break;
00221 #if defined(LPTIM2)
00222      case LPTIM2_BASE:
00223        tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE);
00224        break;
00225 #endif /* LPTIM2 */
00226      default:
00227        break;
00228   }
00229
00230   /* Save LPTIM configuration registers */
00231   tmpIER = LPTIMx->IER;
00232   tmpCFGR = LPTIMx->CFGR;
00233   tmpCMP = LPTIMx->CMP;
00234   tmpARR = LPTIMx->ARR;
00235   tmpOR = LPTIMx->OR;
00236
00237   /************* Reset LPTIM ************/
00238   (void)LL_LPTIM_DeInit(LPTIMx);
00239
00240   /********* Restore LPTIM Config *******/
00241   LL_RCC_GetSystemClocksFreq(&rcc_clock);
00242
00243   if ((tmpCMP != 0UL) || (tmpARR != 0UL))
00244   {
00245     /* Force LPTIM source kernel clock from APB */
00246     switch ((uint32_t)LPTIMx)
00247     {
00248        case LPTIM1_BASE:
00249          LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_PCLK1);
00250          break;
00251 #if defined(LPTIM2)
00252        case LPTIM2_BASE:
00253          LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE_PCLK1);
00254          break;
00255 #endif /* LPTIM2 */
00256        default:
00257          break;
00258     }
00259
00260     if (tmpCMP != 0UL)
00261     {
00262       /* Restore CMP and ARR registers (LPTIM should be enabled first) */
00263       LPTIMx->CR |= LPTIM_CR_ENABLE;
00264       LPTIMx->CMP = tmpCMP;
00265
00266       /* Polling on CMP write ok status after above restore operation */
00267       do
00268       {
00269         rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
00270       } while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
00271
00272       LL_LPTIM_ClearFlag_CMPOK(LPTIMx);
00273     }
00274
00275     if (tmpARR != 0UL)
00276     {
00277       LPTIMx->CR |= LPTIM_CR_ENABLE;
00278       LPTIMx->ARR = tmpARR;
00279
00280       LL_RCC_GetSystemClocksFreq(&rcc_clock);
00281       /* Polling on ARR write ok status after above restore operation */
00282       do
00283       {
00284         rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
00285       } while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
00286
00287       LL_LPTIM_ClearFlag_ARROK(LPTIMx);
00288     }
00289
00290     /* Restore LPTIM source kernel clock */
00291     LL_RCC_SetLPTIMClockSource(tmpclksource);
00292   }
00293
00294   /* Restore configuration registers (LPTIM should be disabled first) */
00295   LPTIMx->CR &= ~(LPTIM_CR_ENABLE);
00296   LPTIMx->IER = tmpIER;
00297   LPTIMx->CFGR = tmpCFGR;
00298   LPTIMx->OR = tmpOR;
00299
00300   __enable_irq();
00301 }
00302
00303 /**
00304   * @}
00305   */
00306
00307 #endif /* LPTIM1 || LPTIM2 */
00308
00309 /**
00310   * @}
00311   */
00312
00313 #endif /* USE_FULL_LL_DRIVER */
00314
00315 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_lptim.h Source File

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stm32wbxx_ll_lptim.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_lptim.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of LPTIM LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_LL_LPTIM_H
00022 #define STM32WBxx_LL_LPTIM_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx.h"
00030
00031 /** @addtogroup STM32WBxx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (LPTIM1) || defined (LPTIM2)
00036
00037 /** @defgroup LPTIM_LL LPTIM
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043
00044 /* Private constants ---------------------------------------------------------*/
00045
00046 /* Private macros ------------------------------------------------------------*/
00047 #if defined(USE_FULL_LL_DRIVER)
00048 /** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros
00049   * @{
00050   */
00051 /**
00052   * @}
00053   */
00054 #endif /*USE_FULL_LL_DRIVER*/
00055
00056 /* Exported types ------------------------------------------------------------*/
00057 #if defined(USE_FULL_LL_DRIVER)
00058 /** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  LPTIM Init structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t ClockSource;    /*!< Specifies the source of the clock used by the LPTIM instance.
00068                                 This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
00069
00070                                 This feature can be modified afterwards using unitary function @ref LL_LPTIM_SetClockSource().*/
00071
00072   uint32_t Prescaler;      /*!< Specifies the prescaler division ratio.
00073                                 This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
00074
00075                                 This feature can be modified afterwards using using unitary function @ref LL_LPTIM_SetPrescaler().*/
00076
00077   uint32_t Waveform;       /*!< Specifies the waveform shape.
00078                                 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
00079
00080                                 This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/
00081
00082   uint32_t Polarity;       /*!< Specifies waveform polarity.
00083                                 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_POLARITY.
00084
00085                                 This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/
00086 } LL_LPTIM_InitTypeDef;
00087
00088 /**
00089   * @}
00090   */
00091 #endif /* USE_FULL_LL_DRIVER */
00092
00093 /* Exported constants --------------------------------------------------------*/
00094 /** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants
00095   * @{
00096   */
00097
00098 /** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines
00099   * @brief    Flags defines which can be used with LL_LPTIM_ReadReg function
00100   * @{
00101   */
00102 #define LL_LPTIM_ISR_CMPM                     LPTIM_ISR_CMPM     /*!< Compare match */
00103 #define LL_LPTIM_ISR_ARRM                     LPTIM_ISR_ARRM     /*!< Autoreload match */
00104 #define LL_LPTIM_ISR_EXTTRIG                  LPTIM_ISR_EXTTRIG  /*!< External trigger edge event */
00105 #define LL_LPTIM_ISR_CMPOK                    LPTIM_ISR_CMPOK    /*!< Compare register update OK */
00106 #define LL_LPTIM_ISR_ARROK                    LPTIM_ISR_ARROK    /*!< Autoreload register update OK */
00107 #define LL_LPTIM_ISR_UP                       LPTIM_ISR_UP       /*!< Counter direction change down to up */
00108 #define LL_LPTIM_ISR_DOWN                     LPTIM_ISR_DOWN     /*!< Counter direction change up to down */
00109 /**
00110   * @}
00111   */
00112
00113 /** @defgroup LPTIM_LL_EC_IT IT Defines
00114   * @brief    IT defines which can be used with LL_LPTIM_ReadReg and  LL_LPTIM_WriteReg functions
00115   * @{
00116   */
00117 #define LL_LPTIM_IER_CMPMIE                   LPTIM_IER_CMPMIE       /*!< Compare match Interrupt Enable */
00118 #define LL_LPTIM_IER_ARRMIE                   LPTIM_IER_ARRMIE       /*!< Autoreload match Interrupt Enable */
00119 #define LL_LPTIM_IER_EXTTRIGIE                LPTIM_IER_EXTTRIGIE    /*!< External trigger valid edge Interrupt Enable */
00120 #define LL_LPTIM_IER_CMPOKIE                  LPTIM_IER_CMPOKIE      /*!< Compare register update OK Interrupt Enable */
00121 #define LL_LPTIM_IER_ARROKIE                  LPTIM_IER_ARROKIE      /*!< Autoreload register update OK Interrupt Enable */
00122 #define LL_LPTIM_IER_UPIE                     LPTIM_IER_UPIE         /*!< Direction change to UP Interrupt Enable */
00123 #define LL_LPTIM_IER_DOWNIE                   LPTIM_IER_DOWNIE       /*!< Direction change to down Interrupt Enable */
00124 /**
00125   * @}
00126   */
00127
00128 /** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
00129   * @{
00130   */
00131 #define LL_LPTIM_OPERATING_MODE_CONTINUOUS    LPTIM_CR_CNTSTRT /*!<LP Timer starts in continuous mode*/
00132 #define LL_LPTIM_OPERATING_MODE_ONESHOT       LPTIM_CR_SNGSTRT /*!<LP Tilmer starts in single mode*/
00133 /**
00134   * @}
00135   */
00136
00137 /** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode
00138   * @{
00139   */
00140 #define LL_LPTIM_UPDATE_MODE_IMMEDIATE        0x00000000U        /*!<Preload is disabled: registers are updated after each APB bus write access*/
00141 #define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD      LPTIM_CFGR_PRELOAD /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
00142 /**
00143   * @}
00144   */
00145
00146 /** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode
00147   * @{
00148   */
00149 #define LL_LPTIM_COUNTER_MODE_INTERNAL        0x00000000U          /*!<The counter is incremented following each internal clock pulse*/
00150 #define LL_LPTIM_COUNTER_MODE_EXTERNAL        LPTIM_CFGR_COUNTMODE /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
00151 /**
00152   * @}
00153   */
00154
00155 /** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
00156   * @{
00157   */
00158 #define LL_LPTIM_OUTPUT_WAVEFORM_PWM          0x00000000U     /*!<LPTIM  generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINOUS or SINGLE*/
00159 #define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE      LPTIM_CFGR_WAVE /*!<LPTIM  generates a Set Once waveform*/
00160 /**
00161   * @}
00162   */
00163
00164 /** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity
00165   * @{
00166   */
00167 #define LL_LPTIM_OUTPUT_POLARITY_REGULAR      0x00000000U             /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
00168 #define LL_LPTIM_OUTPUT_POLARITY_INVERSE      LPTIM_CFGR_WAVPOL       /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
00169 /**
00170   * @}
00171   */
00172
00173 /** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value
00174   * @{
00175   */
00176 #define LL_LPTIM_PRESCALER_DIV1               0x00000000U                               /*!<Prescaler division factor is set to 1*/
00177 #define LL_LPTIM_PRESCALER_DIV2               LPTIM_CFGR_PRESC_0                        /*!<Prescaler division factor is set to 2*/
00178 #define LL_LPTIM_PRESCALER_DIV4               LPTIM_CFGR_PRESC_1                        /*!<Prescaler division factor is set to 4*/
00179 #define LL_LPTIM_PRESCALER_DIV8               (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 8*/
00180 #define LL_LPTIM_PRESCALER_DIV16              LPTIM_CFGR_PRESC_2                        /*!<Prescaler division factor is set to 16*/
00181 #define LL_LPTIM_PRESCALER_DIV32              (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 32*/
00182 #define LL_LPTIM_PRESCALER_DIV64              (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1) /*!<Prescaler division factor is set to 64*/
00183 #define LL_LPTIM_PRESCALER_DIV128             LPTIM_CFGR_PRESC                          /*!<Prescaler division factor is set to 128*/
00184 /**
00185   * @}
00186   */
00187
00188 /** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source
00189   * @{
00190   */
00191 #define LL_LPTIM_TRIG_SOURCE_GPIO             0x00000000U                                                          /*!<External input trigger is connected to TIMx_ETR input*/
00192 #define LL_LPTIM_TRIG_SOURCE_RTCALARMA        LPTIM_CFGR_TRIGSEL_0                                                 /*!<External input trigger is connected to RTC Alarm A*/
00193 #define LL_LPTIM_TRIG_SOURCE_RTCALARMB        LPTIM_CFGR_TRIGSEL_1                                                 /*!<External input trigger is connected to RTC Alarm B*/
00194 #if defined(RTC_TAMPER1_SUPPORT)
00195 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP1         (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0)                        /*!<External input trigger is connected to RTC Tamper 1*/
00196 #endif /* RTC_TAMPER1_SUPPORT */
00197 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP2         LPTIM_CFGR_TRIGSEL_2                                                 /*!<External input trigger is connected to RTC Tamper 2*/
00198 #if defined(RTC_TAMPER3_SUPPORT)
00199 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP3         (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0)                        /*!<External input trigger is connected to RTC Tamper 3*/
00200 #endif /* RTC_TAMPER3_SUPPORT */
00201 #if defined(COMP1)
00202 #define LL_LPTIM_TRIG_SOURCE_COMP1            (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1)                        /*!<External input trigger is connected to COMP1 output*/
00203 #endif /* COMP1 */
00204 #if defined(COMP2)
00205 #define LL_LPTIM_TRIG_SOURCE_COMP2            LPTIM_CFGR_TRIGSEL                                                   /*!<External input trigger is connected to COMP2 output*/
00206 #endif /* COMP2 */
00207 /**
00208   * @}
00209   */
00210
00211 /** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter
00212   * @{
00213   */
00214 #define LL_LPTIM_TRIG_FILTER_NONE             0x00000000U         /*!<Any trigger active level change is considered as a valid trigger*/
00215 #define LL_LPTIM_TRIG_FILTER_2                LPTIM_CFGR_TRGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
00216 #define LL_LPTIM_TRIG_FILTER_4                LPTIM_CFGR_TRGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
00217 #define LL_LPTIM_TRIG_FILTER_8                LPTIM_CFGR_TRGFLT   /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
00218 /**
00219   * @}
00220   */
00221
00222 /** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity
00223   * @{
00224   */
00225 #define LL_LPTIM_TRIG_POLARITY_RISING         LPTIM_CFGR_TRIGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/
00226 #define LL_LPTIM_TRIG_POLARITY_FALLING        LPTIM_CFGR_TRIGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/
00227 #define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN   /*!<LPTIM counter starts when a rising or a falling edge is detected*/
00228 /**
00229   * @}
00230   */
00231
00232 /** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source
00233   * @{
00234   */
00235 #define LL_LPTIM_CLK_SOURCE_INTERNAL          0x00000000U      /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
00236 #define LL_LPTIM_CLK_SOURCE_EXTERNAL          LPTIM_CFGR_CKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
00237 /**
00238   * @}
00239   */
00240
00241 /** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter
00242   * @{
00243   */
00244 #define LL_LPTIM_CLK_FILTER_NONE              0x00000000U        /*!<Any external clock signal level change is considered as a valid transition*/
00245 #define LL_LPTIM_CLK_FILTER_2                 LPTIM_CFGR_CKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
00246 #define LL_LPTIM_CLK_FILTER_4                 LPTIM_CFGR_CKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
00247 #define LL_LPTIM_CLK_FILTER_8                 LPTIM_CFGR_CKFLT   /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
00248 /**
00249   * @}
00250   */
00251
00252 /** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity
00253   * @{
00254   */
00255 #define LL_LPTIM_CLK_POLARITY_RISING          0x00000000U        /*!< The rising edge is the active edge used for counting*/
00256 #define LL_LPTIM_CLK_POLARITY_FALLING         LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
00257 #define LL_LPTIM_CLK_POLARITY_RISING_FALLING  LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
00258 /**
00259   * @}
00260   */
00261
00262 /** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode
00263   * @{
00264   */
00265 #define LL_LPTIM_ENCODER_MODE_RISING          0x00000000U        /*!< The rising edge is the active edge used for counting*/
00266 #define LL_LPTIM_ENCODER_MODE_FALLING         LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
00267 #define LL_LPTIM_ENCODER_MODE_RISING_FALLING  LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
00268 /**
00269   * @}
00270   */
00271
00272 /** @defgroup LPTIM_EC_INPUT1_SRC Input1 Source
00273   * @{
00274   */
00275 #define LL_LPTIM_INPUT1_SRC_GPIO         0x00000000U            /*!< For LPTIM1 and LPTIM2 */
00276 #define LL_LPTIM_INPUT1_SRC_COMP1        LPTIM_OR_OR_0          /*!< For LPTIM1 and LPTIM2 */
00277 #define LL_LPTIM_INPUT1_SRC_COMP2        LPTIM_OR_OR_1          /*!< For LPTIM2 */
00278 #define LL_LPTIM_INPUT1_SRC_COMP1_COMP2  LPTIM_OR_OR            /*!< For LPTIM2 */
00279 /**
00280   * @}
00281   */
00282
00283 /** @defgroup LPTIM_EC_INPUT2_SRC Input2 Source
00284   * @{
00285   */
00286 #define LL_LPTIM_INPUT2_SRC_GPIO         0x00000000U                   /*!< For LPTIM1 */
00287 #define LL_LPTIM_INPUT2_SRC_COMP2        LPTIM_OR_OR_1                 /*!< For LPTIM1 */
00288 /**
00289   * @}
00290   */
00291
00292 /**
00293   * @}
00294   */
00295
00296 /* Exported macro ------------------------------------------------------------*/
00297 /** @defgroup LPTIM_LL_Exported_Macros LPTIM Exported Macros
00298   * @{
00299   */
00300
00301 /** @defgroup LPTIM_LL_EM_WRITE_READ Common Write and read registers Macros
00302   * @{
00303   */
00304
00305 /**
00306   * @brief  Write a value in LPTIM register
00307   * @param  __INSTANCE__ LPTIM Instance
00308   * @param  __REG__ Register to be written
00309   * @param  __VALUE__ Value to be written in the register
00310   * @retval None
00311   */
00312 #define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
00313
00314 /**
00315   * @brief  Read a value in LPTIM register
00316   * @param  __INSTANCE__ LPTIM Instance
00317   * @param  __REG__ Register to be read
00318   * @retval Register value
00319   */
00320 #define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
00321 /**
00322   * @}
00323   */
00324
00325 /**
00326   * @}
00327   */
00328
00329 /* Exported functions --------------------------------------------------------*/
00330 /** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
00331   * @{
00332   */
00333
00334 #if defined(USE_FULL_LL_DRIVER)
00335 /** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
00336   * @{
00337   */
00338
00339 ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx);
00340 void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
00341 ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
00342 void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx);
00343 /**
00344   * @}
00345   */
00346 #endif /* USE_FULL_LL_DRIVER */
00347
00348 /** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
00349   * @{
00350   */
00351
00352 /**
00353   * @brief  Enable the LPTIM instance
00354   * @note After setting the ENABLE bit, a delay of two counter clock is needed
00355   *       before the LPTIM instance is actually enabled.
00356   * @rmtoll CR           ENABLE        LL_LPTIM_Enable
00357   * @param  LPTIMx Low-Power Timer instance
00358   * @retval None
00359   */
00360 __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
00361 {
00362   SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
00363 }
00364
00365 /**
00366   * @brief  Indicates whether the LPTIM instance is enabled.
00367   * @rmtoll CR           ENABLE        LL_LPTIM_IsEnabled
00368   * @param  LPTIMx Low-Power Timer instance
00369   * @retval State of bit (1 or 0).
00370   */
00371 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx)
00372 {
00373   return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE)? 1UL : 0UL));
00374 }
00375
00376 /**
00377   * @brief  Starts the LPTIM counter in the desired mode.
00378   * @note LPTIM instance must be enabled before starting the counter.
00379   * @note It is possible to change on the fly from One Shot mode to
00380   *       Continuous mode.
00381   * @rmtoll CR           CNTSTRT       LL_LPTIM_StartCounter\n
00382   *         CR           SNGSTRT       LL_LPTIM_StartCounter
00383   * @param  LPTIMx Low-Power Timer instance
00384   * @param  OperatingMode This parameter can be one of the following values:
00385   *         @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS
00386   *         @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT
00387   * @retval None
00388   */
00389 __STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
00390 {
00391   MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);
00392 }
00393
00394 /**
00395   * @brief  Enable reset after read.
00396   * @note After calling this function any read access to LPTIM_CNT
00397   *        register will asynchronously reset the LPTIM_CNT register content.
00398   * @rmtoll CR           RSTARE        LL_LPTIM_EnableResetAfterRead
00399   * @param  LPTIMx Low-Power Timer instance
00400   * @retval None
00401   */
00402 __STATIC_INLINE void LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef *LPTIMx)
00403 {
00404   SET_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
00405 }
00406
00407 /**
00408   * @brief  Disable reset after read.
00409   * @rmtoll CR           RSTARE        LL_LPTIM_DisableResetAfterRead
00410   * @param  LPTIMx Low-Power Timer instance
00411   * @retval None
00412   */
00413 __STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx)
00414 {
00415   CLEAR_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
00416 }
00417
00418 /**
00419   * @brief  Indicate whether the reset after read feature is enabled.
00420   * @rmtoll CR           RSTARE        LL_LPTIM_IsEnabledResetAfterRead
00421   * @param  LPTIMx Low-Power Timer instance
00422   * @retval State of bit (1 or 0).
00423   */
00424 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(LPTIM_TypeDef *LPTIMx)
00425 {
00426   return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE)? 1UL : 0UL));
00427 }
00428
00429 /**
00430   * @brief  Reset of the LPTIM_CNT counter register (synchronous).
00431   * @note Due to the synchronous nature of this reset, it only takes
00432   *       place after a synchronization delay of 3 LPTIM core clock cycles
00433   *      (LPTIM core clock may be different from APB clock).
00434   * @note COUNTRST is automatically cleared by hardware
00435   * @rmtoll CR           COUNTRST       LL_LPTIM_ResetCounter\n
00436   * @param  LPTIMx Low-Power Timer instance
00437   * @retval None
00438   */
00439 __STATIC_INLINE void LL_LPTIM_ResetCounter(LPTIM_TypeDef *LPTIMx)
00440 {
00441   SET_BIT(LPTIMx->CR, LPTIM_CR_COUNTRST);
00442 }
00443
00444 /**
00445   * @brief  Set the LPTIM registers update mode (enable/disable register preload)
00446   * @note This function must be called when the LPTIM instance is disabled.
00447   * @rmtoll CFGR         PRELOAD       LL_LPTIM_SetUpdateMode
00448   * @param  LPTIMx Low-Power Timer instance
00449   * @param  UpdateMode This parameter can be one of the following values:
00450   *         @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
00451   *         @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
00452   * @retval None
00453   */
00454 __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
00455 {
00456   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode);
00457 }
00458
00459 /**
00460   * @brief  Get the LPTIM registers update mode
00461   * @rmtoll CFGR         PRELOAD       LL_LPTIM_GetUpdateMode
00462   * @param  LPTIMx Low-Power Timer instance
00463   * @retval Returned value can be one of the following values:
00464   *         @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
00465   *         @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
00466   */
00467 __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx)
00468 {
00469   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
00470 }
00471
00472 /**
00473   * @brief  Set the auto reload value
00474   * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
00475   * @note After a write to the LPTIMx_ARR register a new write operation to the
00476   *       same register can only be performed when the previous write operation
00477   *       is completed. Any successive write before  the ARROK flag is set, will
00478   *       lead to unpredictable results.
00479   * @note autoreload value be strictly greater than the compare value.
00480   * @rmtoll ARR          ARR           LL_LPTIM_SetAutoReload
00481   * @param  LPTIMx Low-Power Timer instance
00482   * @param  AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
00483   * @retval None
00484   */
00485 __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
00486 {
00487   MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload);
00488 }
00489
00490 /**
00491   * @brief  Get actual auto reload value
00492   * @rmtoll ARR          ARR           LL_LPTIM_GetAutoReload
00493   * @param  LPTIMx Low-Power Timer instance
00494   * @retval AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
00495   */
00496 __STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *LPTIMx)
00497 {
00498   return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
00499 }
00500
00501 /**
00502   * @brief  Set the compare value
00503   * @note After a write to the LPTIMx_CMP register a new write operation to the
00504   *       same register can only be performed when the previous write operation
00505   *       is completed. Any successive write before the CMPOK flag is set, will
00506   *       lead to unpredictable results.
00507   * @rmtoll CMP          CMP           LL_LPTIM_SetCompare
00508   * @param  LPTIMx Low-Power Timer instance
00509   * @param  CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
00510   * @retval None
00511   */
00512 __STATIC_INLINE void LL_LPTIM_SetCompare(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
00513 {
00514   MODIFY_REG(LPTIMx->CMP, LPTIM_CMP_CMP, CompareValue);
00515 }
00516
00517 /**
00518   * @brief  Get actual compare value
00519   * @rmtoll CMP          CMP           LL_LPTIM_GetCompare
00520   * @param  LPTIMx Low-Power Timer instance
00521   * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
00522   */
00523 __STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx)
00524 {
00525   return (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMP));
00526 }
00527
00528 /**
00529   * @brief  Get actual counter value
00530   * @note When the LPTIM instance is running with an asynchronous clock, reading
00531   *       the LPTIMx_CNT register may return unreliable values. So in this case
00532   *       it is necessary to perform two consecutive read accesses and verify
00533   *       that the two returned values are identical.
00534   * @rmtoll CNT          CNT           LL_LPTIM_GetCounter
00535   * @param  LPTIMx Low-Power Timer instance
00536   * @retval Counter value
00537   */
00538 __STATIC_INLINE uint32_t LL_LPTIM_GetCounter(LPTIM_TypeDef *LPTIMx)
00539 {
00540   return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
00541 }
00542
00543 /**
00544   * @brief  Set the counter mode (selection of the LPTIM counter clock source).
00545   * @note The counter mode can be set only when the LPTIM instance is disabled.
00546   * @rmtoll CFGR         COUNTMODE     LL_LPTIM_SetCounterMode
00547   * @param  LPTIMx Low-Power Timer instance
00548   * @param  CounterMode This parameter can be one of the following values:
00549   *         @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
00550   *         @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
00551   * @retval None
00552   */
00553 __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
00554 {
00555   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode);
00556 }
00557
00558 /**
00559   * @brief  Get the counter mode
00560   * @rmtoll CFGR         COUNTMODE     LL_LPTIM_GetCounterMode
00561   * @param  LPTIMx Low-Power Timer instance
00562   * @retval Returned value can be one of the following values:
00563   *         @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
00564   *         @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
00565   */
00566 __STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(LPTIM_TypeDef *LPTIMx)
00567 {
00568   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
00569 }
00570
00571 /**
00572   * @brief  Configure the LPTIM instance output (LPTIMx_OUT)
00573   * @note This function must be called when the LPTIM instance is disabled.
00574   * @note Regarding the LPTIM output polarity the change takes effect
00575   *       immediately, so the output default value will change immediately after
00576   *       the polarity is re-configured, even before the timer is enabled.
00577   * @rmtoll CFGR         WAVE          LL_LPTIM_ConfigOutput\n
00578   *         CFGR         WAVPOL        LL_LPTIM_ConfigOutput
00579   * @param  LPTIMx Low-Power Timer instance
00580   * @param  Waveform This parameter can be one of the following values:
00581   *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
00582   *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
00583   * @param  Polarity This parameter can be one of the following values:
00584   *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
00585   *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
00586   * @retval None
00587   */
00588 __STATIC_INLINE void LL_LPTIM_ConfigOutput(LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity)
00589 {
00590   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL, Waveform | Polarity);
00591 }
00592
00593 /**
00594   * @brief  Set  waveform shape
00595   * @rmtoll CFGR         WAVE          LL_LPTIM_SetWaveform
00596   * @param  LPTIMx Low-Power Timer instance
00597   * @param  Waveform This parameter can be one of the following values:
00598   *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
00599   *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
00600   * @retval None
00601   */
00602 __STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
00603 {
00604   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform);
00605 }
00606
00607 /**
00608   * @brief  Get actual waveform shape
00609   * @rmtoll CFGR         WAVE          LL_LPTIM_GetWaveform
00610   * @param  LPTIMx Low-Power Timer instance
00611   * @retval Returned value can be one of the following values:
00612   *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
00613   *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
00614   */
00615 __STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(LPTIM_TypeDef *LPTIMx)
00616 {
00617   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
00618 }
00619
00620 /**
00621   * @brief  Set  output polarity
00622   * @rmtoll CFGR         WAVPOL        LL_LPTIM_SetPolarity
00623   * @param  LPTIMx Low-Power Timer instance
00624   * @param  Polarity This parameter can be one of the following values:
00625   *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
00626   *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
00627   * @retval None
00628   */
00629 __STATIC_INLINE void LL_LPTIM_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Polarity)
00630 {
00631   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, Polarity);
00632 }
00633
00634 /**
00635   * @brief  Get actual output polarity
00636   * @rmtoll CFGR         WAVPOL        LL_LPTIM_GetPolarity
00637   * @param  LPTIMx Low-Power Timer instance
00638   * @retval Returned value can be one of the following values:
00639   *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
00640   *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
00641   */
00642 __STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(LPTIM_TypeDef *LPTIMx)
00643 {
00644   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL));
00645 }
00646
00647 /**
00648   * @brief  Set actual prescaler division ratio.
00649   * @note This function must be called when the LPTIM instance is disabled.
00650   * @note When the LPTIM is configured to be clocked by an internal clock source
00651   *       and the LPTIM counter is configured to be updated by active edges
00652   *       detected on the LPTIM external Input1, the internal clock provided to
00653   *       the LPTIM must be not be prescaled.
00654   * @rmtoll CFGR         PRESC         LL_LPTIM_SetPrescaler
00655   * @param  LPTIMx Low-Power Timer instance
00656   * @param  Prescaler This parameter can be one of the following values:
00657   *         @arg @ref LL_LPTIM_PRESCALER_DIV1
00658   *         @arg @ref LL_LPTIM_PRESCALER_DIV2
00659   *         @arg @ref LL_LPTIM_PRESCALER_DIV4
00660   *         @arg @ref LL_LPTIM_PRESCALER_DIV8
00661   *         @arg @ref LL_LPTIM_PRESCALER_DIV16
00662   *         @arg @ref LL_LPTIM_PRESCALER_DIV32
00663   *         @arg @ref LL_LPTIM_PRESCALER_DIV64
00664   *         @arg @ref LL_LPTIM_PRESCALER_DIV128
00665   * @retval None
00666   */
00667 __STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
00668 {
00669   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler);
00670 }
00671
00672 /**
00673   * @brief  Get actual prescaler division ratio.
00674   * @rmtoll CFGR         PRESC         LL_LPTIM_GetPrescaler
00675   * @param  LPTIMx Low-Power Timer instance
00676   * @retval Returned value can be one of the following values:
00677   *         @arg @ref LL_LPTIM_PRESCALER_DIV1
00678   *         @arg @ref LL_LPTIM_PRESCALER_DIV2
00679   *         @arg @ref LL_LPTIM_PRESCALER_DIV4
00680   *         @arg @ref LL_LPTIM_PRESCALER_DIV8
00681   *         @arg @ref LL_LPTIM_PRESCALER_DIV16
00682   *         @arg @ref LL_LPTIM_PRESCALER_DIV32
00683   *         @arg @ref LL_LPTIM_PRESCALER_DIV64
00684   *         @arg @ref LL_LPTIM_PRESCALER_DIV128
00685   */
00686 __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx)
00687 {
00688   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
00689 }
00690
00691 /**
00692   * @brief  Set LPTIM input 1 source (default GPIO).
00693   * @rmtoll OR         OR_0         LL_LPTIM_SetInput1Src
00694   * @rmtoll OR         OR_1         LL_LPTIM_SetInput1Src
00695   * @param  LPTIMx Low-Power Timer instance
00696   * @param  Src This parameter can be one of the following values:
00697   *         @arg @ref LL_LPTIM_INPUT1_SRC_GPIO
00698   *         @arg @ref LL_LPTIM_INPUT1_SRC_COMP1
00699   *         @arg @ref LL_LPTIM_INPUT1_SRC_COMP2
00700   *         @arg @ref LL_LPTIM_INPUT1_SRC_COMP1_COMP2
00701   * @retval None
00702   */
00703 __STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
00704 {
00705   WRITE_REG(LPTIMx->OR, Src);
00706 }
00707
00708 /**
00709   * @brief  Set LPTIM input 2 source (default GPIO).
00710   * @rmtoll OR         OR_0         LL_LPTIM_SetInput2Src
00711   * @param  LPTIMx Low-Power Timer instance
00712   * @param  Src This parameter can be one of the following values:
00713   *         @arg @ref LL_LPTIM_INPUT2_SRC_GPIO
00714   *         @arg @ref LL_LPTIM_INPUT2_SRC_COMP2
00715   * @retval None
00716   */
00717 __STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
00718 {
00719   WRITE_REG(LPTIMx->OR, Src);
00720 }
00721
00722 /**
00723   * @}
00724   */
00725
00726 /** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration
00727   * @{
00728   */
00729
00730 /**
00731   * @brief  Enable the timeout function
00732   * @note This function must be called when the LPTIM instance is disabled.
00733   * @note The first trigger event will start the timer, any successive trigger
00734   *       event will reset the counter and the timer will restart.
00735   * @note The timeout value corresponds to the compare value; if no trigger
00736   *       occurs within the expected time frame, the MCU is waked-up by the
00737   *       compare match event.
00738   * @rmtoll CFGR         TIMOUT        LL_LPTIM_EnableTimeout
00739   * @param  LPTIMx Low-Power Timer instance
00740   * @retval None
00741   */
00742 __STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx)
00743 {
00744   SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
00745 }
00746
00747 /**
00748   * @brief  Disable the timeout function
00749   * @note This function must be called when the LPTIM instance is disabled.
00750   * @note A trigger event arriving when the timer is already started will be
00751   *       ignored.
00752   * @rmtoll CFGR         TIMOUT        LL_LPTIM_DisableTimeout
00753   * @param  LPTIMx Low-Power Timer instance
00754   * @retval None
00755   */
00756 __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
00757 {
00758   CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
00759 }
00760
00761 /**
00762   * @brief  Indicate whether the timeout function is enabled.
00763   * @rmtoll CFGR         TIMOUT        LL_LPTIM_IsEnabledTimeout
00764   * @param  LPTIMx Low-Power Timer instance
00765   * @retval State of bit (1 or 0).
00766   */
00767 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx)
00768 {
00769   return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT)? 1UL : 0UL));
00770 }
00771
00772 /**
00773   * @brief  Start the LPTIM counter
00774   * @note This function must be called when the LPTIM instance is disabled.
00775   * @rmtoll CFGR         TRIGEN        LL_LPTIM_TrigSw
00776   * @param  LPTIMx Low-Power Timer instance
00777   * @retval None
00778   */
00779 __STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)
00780 {
00781   CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN);
00782 }
00783
00784 /**
00785   * @brief  Configure the external trigger used as a trigger event for the LPTIM.
00786   * @note This function must be called when the LPTIM instance is disabled.
00787   * @note An internal clock source must be present when a digital filter is
00788   *       required for the trigger.
00789   * @rmtoll CFGR         TRIGSEL       LL_LPTIM_ConfigTrigger\n
00790   *         CFGR         TRGFLT        LL_LPTIM_ConfigTrigger\n
00791   *         CFGR         TRIGEN        LL_LPTIM_ConfigTrigger
00792   * @param  LPTIMx Low-Power Timer instance
00793   * @param  Source This parameter can be one of the following values:
00794   *         @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
00795   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
00796   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
00797   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (*)
00798   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
00799   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (*)
00800   *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1 (*)
00801   *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2 (*)
00802   *
00803   *         (*)  Value not defined in all devices. \n
00804   *
00805   * @param  Filter This parameter can be one of the following values:
00806   *         @arg @ref LL_LPTIM_TRIG_FILTER_NONE
00807   *         @arg @ref LL_LPTIM_TRIG_FILTER_2
00808   *         @arg @ref LL_LPTIM_TRIG_FILTER_4
00809   *         @arg @ref LL_LPTIM_TRIG_FILTER_8
00810   * @param  Polarity This parameter can be one of the following values:
00811   *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
00812   *         @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
00813   *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
00814   * @retval None
00815   */
00816 __STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
00817 {
00818   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity);
00819 }
00820
00821 /**
00822   * @brief  Get actual external trigger source.
00823   * @rmtoll CFGR         TRIGSEL       LL_LPTIM_GetTriggerSource
00824   * @param  LPTIMx Low-Power Timer instance
00825   * @retval Returned value can be one of the following values:
00826   *         @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
00827   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
00828   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
00829   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (*)
00830   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
00831   *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (*)
00832   *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1 (*)
00833   *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2 (*)
00834   *
00835   *         (*)  Value not defined in all devices. \n
00836   *
00837   */
00838 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx)
00839 {
00840   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
00841 }
00842
00843 /**
00844   * @brief  Get actual external trigger filter.
00845   * @rmtoll CFGR         TRGFLT        LL_LPTIM_GetTriggerFilter
00846   * @param  LPTIMx Low-Power Timer instance
00847   * @retval Returned value can be one of the following values:
00848   *         @arg @ref LL_LPTIM_TRIG_FILTER_NONE
00849   *         @arg @ref LL_LPTIM_TRIG_FILTER_2
00850   *         @arg @ref LL_LPTIM_TRIG_FILTER_4
00851   *         @arg @ref LL_LPTIM_TRIG_FILTER_8
00852   */
00853 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx)
00854 {
00855   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
00856 }
00857
00858 /**
00859   * @brief  Get actual external trigger polarity.
00860   * @rmtoll CFGR         TRIGEN        LL_LPTIM_GetTriggerPolarity
00861   * @param  LPTIMx Low-Power Timer instance
00862   * @retval Returned value can be one of the following values:
00863   *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
00864   *         @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
00865   *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
00866   */
00867 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(LPTIM_TypeDef *LPTIMx)
00868 {
00869   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
00870 }
00871
00872 /**
00873   * @}
00874   */
00875
00876 /** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration
00877   * @{
00878   */
00879
00880 /**
00881   * @brief  Set the source of the clock used by the LPTIM instance.
00882   * @note This function must be called when the LPTIM instance is disabled.
00883   * @rmtoll CFGR         CKSEL         LL_LPTIM_SetClockSource
00884   * @param  LPTIMx Low-Power Timer instance
00885   * @param  ClockSource This parameter can be one of the following values:
00886   *         @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
00887   *         @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
00888   * @retval None
00889   */
00890 __STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
00891 {
00892   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource);
00893 }
00894
00895 /**
00896   * @brief  Get actual LPTIM instance clock source.
00897   * @rmtoll CFGR         CKSEL         LL_LPTIM_GetClockSource
00898   * @param  LPTIMx Low-Power Timer instance
00899   * @retval Returned value can be one of the following values:
00900   *         @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
00901   *         @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
00902   */
00903 __STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(LPTIM_TypeDef *LPTIMx)
00904 {
00905   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
00906 }
00907
00908 /**
00909   * @brief  Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source.
00910   * @note This function must be called when the LPTIM instance is disabled.
00911   * @note When both external clock signal edges are considered active ones,
00912   *       the LPTIM must also be clocked by an internal clock source with a
00913   *       frequency equal to at least four times the external clock frequency.
00914   * @note An internal clock source must be present when a digital filter is
00915   *       required for external clock.
00916   * @rmtoll CFGR         CKFLT         LL_LPTIM_ConfigClock\n
00917   *         CFGR         CKPOL         LL_LPTIM_ConfigClock
00918   * @param  LPTIMx Low-Power Timer instance
00919   * @param  ClockFilter This parameter can be one of the following values:
00920   *         @arg @ref LL_LPTIM_CLK_FILTER_NONE
00921   *         @arg @ref LL_LPTIM_CLK_FILTER_2
00922   *         @arg @ref LL_LPTIM_CLK_FILTER_4
00923   *         @arg @ref LL_LPTIM_CLK_FILTER_8
00924   * @param  ClockPolarity This parameter can be one of the following values:
00925   *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING
00926   *         @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
00927   *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
00928   * @retval None
00929   */
00930 __STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
00931 {
00932   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity);
00933 }
00934
00935 /**
00936   * @brief  Get actual clock polarity
00937   * @rmtoll CFGR         CKPOL         LL_LPTIM_GetClockPolarity
00938   * @param  LPTIMx Low-Power Timer instance
00939   * @retval Returned value can be one of the following values:
00940   *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING
00941   *         @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
00942   *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
00943   */
00944 __STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx)
00945 {
00946   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
00947 }
00948
00949 /**
00950   * @brief  Get actual clock digital filter
00951   * @rmtoll CFGR         CKFLT         LL_LPTIM_GetClockFilter
00952   * @param  LPTIMx Low-Power Timer instance
00953   * @retval Returned value can be one of the following values:
00954   *         @arg @ref LL_LPTIM_CLK_FILTER_NONE
00955   *         @arg @ref LL_LPTIM_CLK_FILTER_2
00956   *         @arg @ref LL_LPTIM_CLK_FILTER_4
00957   *         @arg @ref LL_LPTIM_CLK_FILTER_8
00958   */
00959 __STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(LPTIM_TypeDef *LPTIMx)
00960 {
00961   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
00962 }
00963
00964 /**
00965   * @}
00966   */
00967
00968 /** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode
00969   * @{
00970   */
00971
00972 /**
00973   * @brief  Configure the encoder mode.
00974   * @note This function must be called when the LPTIM instance is disabled.
00975   * @rmtoll CFGR         CKPOL         LL_LPTIM_SetEncoderMode
00976   * @param  LPTIMx Low-Power Timer instance
00977   * @param  EncoderMode This parameter can be one of the following values:
00978   *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING
00979   *         @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
00980   *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
00981   * @retval None
00982   */
00983 __STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
00984 {
00985   MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode);
00986 }
00987
00988 /**
00989   * @brief  Get actual encoder mode.
00990   * @rmtoll CFGR         CKPOL         LL_LPTIM_GetEncoderMode
00991   * @param  LPTIMx Low-Power Timer instance
00992   * @retval Returned value can be one of the following values:
00993   *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING
00994   *         @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
00995   *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
00996   */
00997 __STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(LPTIM_TypeDef *LPTIMx)
00998 {
00999   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
01000 }
01001
01002 /**
01003   * @brief  Enable the encoder mode
01004   * @note This function must be called when the LPTIM instance is disabled.
01005   * @note In this mode the LPTIM instance must be clocked by an internal clock
01006   *       source. Also, the prescaler division ratio must be equal to 1.
01007   * @note LPTIM instance must be configured in continuous mode prior enabling
01008   *       the encoder mode.
01009   * @rmtoll CFGR         ENC           LL_LPTIM_EnableEncoderMode
01010   * @param  LPTIMx Low-Power Timer instance
01011   * @retval None
01012   */
01013 __STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx)
01014 {
01015   SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
01016 }
01017
01018 /**
01019   * @brief  Disable the encoder mode
01020   * @note This function must be called when the LPTIM instance is disabled.
01021   * @rmtoll CFGR         ENC           LL_LPTIM_DisableEncoderMode
01022   * @param  LPTIMx Low-Power Timer instance
01023   * @retval None
01024   */
01025 __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
01026 {
01027   CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
01028 }
01029
01030 /**
01031   * @brief  Indicates whether the LPTIM operates in encoder mode.
01032   * @rmtoll CFGR         ENC           LL_LPTIM_IsEnabledEncoderMode
01033   * @param  LPTIMx Low-Power Timer instance
01034   * @retval State of bit (1 or 0).
01035   */
01036 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx)
01037 {
01038   return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC)? 1UL : 0UL));
01039 }
01040
01041 /**
01042   * @}
01043   */
01044
01045 /** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management
01046   * @{
01047   */
01048
01049 /**
01050   * @brief  Clear the compare match flag (CMPMCF)
01051   * @rmtoll ICR          CMPMCF        LL_LPTIM_ClearFLAG_CMPM
01052   * @param  LPTIMx Low-Power Timer instance
01053   * @retval None
01054   */
01055 __STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx)
01056 {
01057   SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF);
01058 }
01059
01060 /**
01061   * @brief  Inform application whether a compare match interrupt has occurred.
01062   * @rmtoll ISR          CMPM          LL_LPTIM_IsActiveFlag_CMPM
01063   * @param  LPTIMx Low-Power Timer instance
01064   * @retval State of bit (1 or 0).
01065   */
01066 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx)
01067 {
01068   return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM)? 1UL : 0UL));
01069 }
01070
01071 /**
01072   * @brief  Clear the autoreload match flag (ARRMCF)
01073   * @rmtoll ICR          ARRMCF        LL_LPTIM_ClearFLAG_ARRM
01074   * @param  LPTIMx Low-Power Timer instance
01075   * @retval None
01076   */
01077 __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx)
01078 {
01079   SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
01080 }
01081
01082 /**
01083   * @brief  Inform application whether a autoreload match interrupt has occured.
01084   * @rmtoll ISR          ARRM          LL_LPTIM_IsActiveFlag_ARRM
01085   * @param  LPTIMx Low-Power Timer instance
01086   * @retval State of bit (1 or 0).
01087   */
01088 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx)
01089 {
01090   return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM)? 1UL : 0UL));
01091 }
01092
01093 /**
01094   * @brief  Clear the external trigger valid edge flag(EXTTRIGCF).
01095   * @rmtoll ICR          EXTTRIGCF     LL_LPTIM_ClearFlag_EXTTRIG
01096   * @param  LPTIMx Low-Power Timer instance
01097   * @retval None
01098   */
01099 __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
01100 {
01101   SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF);
01102 }
01103
01104 /**
01105   * @brief  Inform application whether a valid edge on the selected external trigger input has occurred.
01106   * @rmtoll ISR          EXTTRIG       LL_LPTIM_IsActiveFlag_EXTTRIG
01107   * @param  LPTIMx Low-Power Timer instance
01108   * @retval State of bit (1 or 0).
01109   */
01110 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
01111 {
01112   return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG)? 1UL : 0UL));
01113 }
01114
01115 /**
01116   * @brief  Clear the compare register update interrupt flag (CMPOKCF).
01117   * @rmtoll ICR          CMPOKCF       LL_LPTIM_ClearFlag_CMPOK
01118   * @param  LPTIMx Low-Power Timer instance
01119   * @retval None
01120   */
01121 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
01122 {
01123   SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPOKCF);
01124 }
01125
01126 /**
01127   * @brief  Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed. If so, a new one can be initiated.
01128   * @rmtoll ISR          CMPOK         LL_LPTIM_IsActiveFlag_CMPOK
01129   * @param  LPTIMx Low-Power Timer instance
01130   * @retval State of bit (1 or 0).
01131   */
01132 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
01133 {
01134   return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK)? 1UL : 0UL));
01135 }
01136
01137 /**
01138   * @brief  Clear the autoreload register update interrupt flag (ARROKCF).
01139   * @rmtoll ICR          ARROKCF       LL_LPTIM_ClearFlag_ARROK
01140   * @param  LPTIMx Low-Power Timer instance
01141   * @retval None
01142   */
01143 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
01144 {
01145   SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF);
01146 }
01147
01148 /**
01149   * @brief  Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed. If so, a new one can be initiated.
01150   * @rmtoll ISR          ARROK         LL_LPTIM_IsActiveFlag_ARROK
01151   * @param  LPTIMx Low-Power Timer instance
01152   * @retval State of bit (1 or 0).
01153   */
01154 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx)
01155 {
01156   return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK)? 1UL : 0UL));
01157 }
01158
01159 /**
01160   * @brief  Clear the counter direction change to up interrupt flag (UPCF).
01161   * @rmtoll ICR          UPCF          LL_LPTIM_ClearFlag_UP
01162   * @param  LPTIMx Low-Power Timer instance
01163   * @retval None
01164   */
01165 __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
01166 {
01167   SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF);
01168 }
01169
01170 /**
01171   * @brief  Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode).
01172   * @rmtoll ISR          UP            LL_LPTIM_IsActiveFlag_UP
01173   * @param  LPTIMx Low-Power Timer instance
01174   * @retval State of bit (1 or 0).
01175   */
01176 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx)
01177 {
01178   return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP)? 1UL : 0UL));
01179 }
01180
01181 /**
01182   * @brief  Clear the counter direction change to down interrupt flag (DOWNCF).
01183   * @rmtoll ICR          DOWNCF        LL_LPTIM_ClearFlag_DOWN
01184   * @param  LPTIMx Low-Power Timer instance
01185   * @retval None
01186   */
01187 __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
01188 {
01189   SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF);
01190 }
01191
01192 /**
01193   * @brief  Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode).
01194   * @rmtoll ISR          DOWN          LL_LPTIM_IsActiveFlag_DOWN
01195   * @param  LPTIMx Low-Power Timer instance
01196   * @retval State of bit (1 or 0).
01197   */
01198 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx)
01199 {
01200   return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN)? 1UL : 0UL));
01201 }
01202
01203 /**
01204   * @}
01205   */
01206
01207 /** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management
01208   * @{
01209   */
01210
01211 /**
01212   * @brief  Enable compare match interrupt (CMPMIE).
01213   * @rmtoll IER          CMPMIE        LL_LPTIM_EnableIT_CMPM
01214   * @param  LPTIMx Low-Power Timer instance
01215   * @retval None
01216   */
01217 __STATIC_INLINE void LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef *LPTIMx)
01218 {
01219   SET_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
01220 }
01221
01222 /**
01223   * @brief  Disable compare match interrupt (CMPMIE).
01224   * @rmtoll IER          CMPMIE        LL_LPTIM_DisableIT_CMPM
01225   * @param  LPTIMx Low-Power Timer instance
01226   * @retval None
01227   */
01228 __STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx)
01229 {
01230   CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
01231 }
01232
01233 /**
01234   * @brief  Indicates whether the compare match interrupt (CMPMIE) is enabled.
01235   * @rmtoll IER          CMPMIE        LL_LPTIM_IsEnabledIT_CMPM
01236   * @param  LPTIMx Low-Power Timer instance
01237   * @retval State of bit (1 or 0).
01238   */
01239 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx)
01240 {
01241   return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE)? 1UL : 0UL));
01242 }
01243
01244 /**
01245   * @brief  Enable autoreload match interrupt (ARRMIE).
01246   * @rmtoll IER          ARRMIE        LL_LPTIM_EnableIT_ARRM
01247   * @param  LPTIMx Low-Power Timer instance
01248   * @retval None
01249   */
01250 __STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx)
01251 {
01252   SET_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
01253 }
01254
01255 /**
01256   * @brief  Disable autoreload match interrupt (ARRMIE).
01257   * @rmtoll IER          ARRMIE        LL_LPTIM_DisableIT_ARRM
01258   * @param  LPTIMx Low-Power Timer instance
01259   * @retval None
01260   */
01261 __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
01262 {
01263   CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
01264 }
01265
01266 /**
01267   * @brief  Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
01268   * @rmtoll IER          ARRMIE        LL_LPTIM_IsEnabledIT_ARRM
01269   * @param  LPTIMx Low-Power Timer instance
01270   * @retval State of bit (1 or 0).
01271   */
01272 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx)
01273 {
01274   return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE)? 1UL : 0UL));
01275 }
01276
01277 /**
01278   * @brief  Enable external trigger valid edge interrupt (EXTTRIGIE).
01279   * @rmtoll IER          EXTTRIGIE     LL_LPTIM_EnableIT_EXTTRIG
01280   * @param  LPTIMx Low-Power Timer instance
01281   * @retval None
01282   */
01283 __STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
01284 {
01285   SET_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
01286 }
01287
01288 /**
01289   * @brief  Disable external trigger valid edge interrupt (EXTTRIGIE).
01290   * @rmtoll IER          EXTTRIGIE     LL_LPTIM_DisableIT_EXTTRIG
01291   * @param  LPTIMx Low-Power Timer instance
01292   * @retval None
01293   */
01294 __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
01295 {
01296   CLEAR_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
01297 }
01298
01299 /**
01300   * @brief  Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
01301   * @rmtoll IER          EXTTRIGIE     LL_LPTIM_IsEnabledIT_EXTTRIG
01302   * @param  LPTIMx Low-Power Timer instance
01303   * @retval State of bit (1 or 0).
01304   */
01305 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
01306 {
01307   return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE)? 1UL : 0UL));
01308 }
01309
01310 /**
01311   * @brief  Enable compare register write completed interrupt (CMPOKIE).
01312   * @rmtoll IER          CMPOKIE       LL_LPTIM_EnableIT_CMPOK
01313   * @param  LPTIMx Low-Power Timer instance
01314   * @retval None
01315   */
01316 __STATIC_INLINE void LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
01317 {
01318   SET_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
01319 }
01320
01321 /**
01322   * @brief  Disable compare register write completed interrupt (CMPOKIE).
01323   * @rmtoll IER          CMPOKIE       LL_LPTIM_DisableIT_CMPOK
01324   * @param  LPTIMx Low-Power Timer instance
01325   * @retval None
01326   */
01327 __STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
01328 {
01329   CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
01330 }
01331
01332 /**
01333   * @brief  Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
01334   * @rmtoll IER          CMPOKIE       LL_LPTIM_IsEnabledIT_CMPOK
01335   * @param  LPTIMx Low-Power Timer instance
01336   * @retval State of bit (1 or 0).
01337   */
01338 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx)
01339 {
01340   return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE)? 1UL : 0UL));
01341 }
01342
01343 /**
01344   * @brief  Enable autoreload register write completed interrupt (ARROKIE).
01345   * @rmtoll IER          ARROKIE       LL_LPTIM_EnableIT_ARROK
01346   * @param  LPTIMx Low-Power Timer instance
01347   * @retval None
01348   */
01349 __STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)
01350 {
01351   SET_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
01352 }
01353
01354 /**
01355   * @brief  Disable autoreload register write completed interrupt (ARROKIE).
01356   * @rmtoll IER          ARROKIE       LL_LPTIM_DisableIT_ARROK
01357   * @param  LPTIMx Low-Power Timer instance
01358   * @retval None
01359   */
01360 __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
01361 {
01362   CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
01363 }
01364
01365 /**
01366   * @brief  Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
01367   * @rmtoll IER          ARROKIE       LL_LPTIM_IsEnabledIT_ARROK
01368   * @param  LPTIMx Low-Power Timer instance
01369   * @retval State of bit (1 or 0).
01370   */
01371 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx)
01372 {
01373   return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE)? 1UL : 0UL));
01374 }
01375
01376 /**
01377   * @brief  Enable direction change to up interrupt (UPIE).
01378   * @rmtoll IER          UPIE          LL_LPTIM_EnableIT_UP
01379   * @param  LPTIMx Low-Power Timer instance
01380   * @retval None
01381   */
01382 __STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)
01383 {
01384   SET_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
01385 }
01386
01387 /**
01388   * @brief  Disable direction change to up interrupt (UPIE).
01389   * @rmtoll IER          UPIE          LL_LPTIM_DisableIT_UP
01390   * @param  LPTIMx Low-Power Timer instance
01391   * @retval None
01392   */
01393 __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
01394 {
01395   CLEAR_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
01396 }
01397
01398 /**
01399   * @brief  Indicates whether the direction change to up interrupt (UPIE) is enabled.
01400   * @rmtoll IER          UPIE          LL_LPTIM_IsEnabledIT_UP
01401   * @param  LPTIMx Low-Power Timer instance
01402   * @retval State of bit (1 or 0).
01403   */
01404 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx)
01405 {
01406   return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE)? 1UL : 0UL));
01407 }
01408
01409 /**
01410   * @brief  Enable direction change to down interrupt (DOWNIE).
01411   * @rmtoll IER          DOWNIE        LL_LPTIM_EnableIT_DOWN
01412   * @param  LPTIMx Low-Power Timer instance
01413   * @retval None
01414   */
01415 __STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)
01416 {
01417   SET_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
01418 }
01419
01420 /**
01421   * @brief  Disable direction change to down interrupt (DOWNIE).
01422   * @rmtoll IER          DOWNIE        LL_LPTIM_DisableIT_DOWN
01423   * @param  LPTIMx Low-Power Timer instance
01424   * @retval None
01425   */
01426 __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
01427 {
01428   CLEAR_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
01429 }
01430
01431 /**
01432   * @brief  Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
01433   * @rmtoll IER          DOWNIE        LL_LPTIM_IsEnabledIT_DOWN
01434   * @param  LPTIMx Low-Power Timer instance
01435   * @retval State of bit (1 or 0).
01436   */
01437 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx)
01438 {
01439   return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE)? 1UL : 0UL);
01440 }
01441
01442 /**
01443   * @}
01444   */
01445
01446 /**
01447   * @}
01448   */
01449
01450 /**
01451   * @}
01452   */
01453
01454 #endif /* LPTIM1 || LPTIM2 */
01455
01456 /**
01457   * @}
01458   */
01459
01460 #ifdef __cplusplus
01461 }
01462 #endif
01463
01464 #endif /* STM32WBxx_LL_LPTIM_H */
01465
01466 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_lpuart.c Source File

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stm32wbxx_ll_lpuart.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_lpuart.c
00004   * @author  MCD Application Team
00005   * @brief   LPUART LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32wbxx_ll_lpuart.h"
00023 #include "stm32wbxx_ll_rcc.h"
00024 #include "stm32wbxx_ll_bus.h"
00025 #ifdef USE_FULL_ASSERT
00026 #include "stm32_assert.h"
00027 #else
00028 #define assert_param(expr) ((void)0U)
00029 #endif /* USE_FULL_ASSERT */
00030
00031 /** @addtogroup STM32WBxx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (LPUART1)
00036
00037 /** @addtogroup LPUART_LL
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /** @addtogroup LPUART_LL_Private_Constants
00045   * @{
00046   */
00047
00048 /**
00049   * @}
00050   */
00051
00052
00053 /* Private macros ------------------------------------------------------------*/
00054 /** @addtogroup LPUART_LL_Private_Macros
00055   * @{
00056   */
00057
00058 /* Check of parameters for configuration of LPUART registers                  */
00059
00060 #define IS_LL_LPUART_PRESCALER(__VALUE__)  (((__VALUE__) == LL_LPUART_PRESCALER_DIV1) \
00061                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV2) \
00062                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV4) \
00063                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV6) \
00064                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV8) \
00065                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV10) \
00066                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV12) \
00067                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV16) \
00068                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV32) \
00069                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV64) \
00070                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV128) \
00071                                             || ((__VALUE__) == LL_LPUART_PRESCALER_DIV256))
00072
00073 /* __BAUDRATE__ Depending on constraints applicable for LPUART BRR register   */
00074 /*              value :                                                       */
00075 /*                - fck must be in the range [3 x baudrate, 4096 x baudrate]  */
00076 /*                - LPUART_BRR register value should be >= 0x300              */
00077 /*                - LPUART_BRR register value should be <= 0xFFFFF (20 bits)  */
00078 /*              Baudrate specified by the user should belong to [8, 21300000].*/
00079 #define IS_LL_LPUART_BAUDRATE(__BAUDRATE__) (((__BAUDRATE__) <= 21300000U) && ((__BAUDRATE__) >= 8U))
00080
00081 /* __VALUE__ BRR content must be greater than or equal to 0x300. */
00082 #define IS_LL_LPUART_BRR_MIN(__VALUE__)   ((__VALUE__) >= 0x300U)
00083
00084 /* __VALUE__ BRR content must be lower than or equal to 0xFFFFF. */
00085 #define IS_LL_LPUART_BRR_MAX(__VALUE__)   ((__VALUE__) <= 0x000FFFFFU)
00086
00087 #define IS_LL_LPUART_DIRECTION(__VALUE__) (((__VALUE__) == LL_LPUART_DIRECTION_NONE) \
00088                                            || ((__VALUE__) == LL_LPUART_DIRECTION_RX) \
00089                                            || ((__VALUE__) == LL_LPUART_DIRECTION_TX) \
00090                                            || ((__VALUE__) == LL_LPUART_DIRECTION_TX_RX))
00091
00092 #define IS_LL_LPUART_PARITY(__VALUE__) (((__VALUE__) == LL_LPUART_PARITY_NONE) \
00093                                         || ((__VALUE__) == LL_LPUART_PARITY_EVEN) \
00094                                         || ((__VALUE__) == LL_LPUART_PARITY_ODD))
00095
00096 #define IS_LL_LPUART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_LPUART_DATAWIDTH_7B) \
00097                                            || ((__VALUE__) == LL_LPUART_DATAWIDTH_8B) \
00098                                            || ((__VALUE__) == LL_LPUART_DATAWIDTH_9B))
00099
00100 #define IS_LL_LPUART_STOPBITS(__VALUE__) (((__VALUE__) == LL_LPUART_STOPBITS_1) \
00101                                           || ((__VALUE__) == LL_LPUART_STOPBITS_2))
00102
00103 #define IS_LL_LPUART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_LPUART_HWCONTROL_NONE) \
00104                                            || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS) \
00105                                            || ((__VALUE__) == LL_LPUART_HWCONTROL_CTS) \
00106                                            || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS_CTS))
00107
00108 /**
00109   * @}
00110   */
00111
00112 /* Private function prototypes -----------------------------------------------*/
00113
00114 /* Exported functions --------------------------------------------------------*/
00115 /** @addtogroup LPUART_LL_Exported_Functions
00116   * @{
00117   */
00118
00119 /** @addtogroup LPUART_LL_EF_Init
00120   * @{
00121   */
00122
00123 /**
00124   * @brief  De-initialize LPUART registers (Registers restored to their default values).
00125   * @param  LPUARTx LPUART Instance
00126   * @retval An ErrorStatus enumeration value:
00127   *          - SUCCESS: LPUART registers are de-initialized
00128   *          - ERROR: not applicable
00129   */
00130 ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx)
00131 {
00132   ErrorStatus status = SUCCESS;
00133
00134   /* Check the parameters */
00135   assert_param(IS_LPUART_INSTANCE(LPUARTx));
00136
00137   if (LPUARTx == LPUART1)
00138   {
00139     /* Force reset of LPUART peripheral */
00140     LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPUART1);
00141
00142     /* Release reset of LPUART peripheral */
00143     LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPUART1);
00144   }
00145   else
00146   {
00147     status = ERROR;
00148   }
00149
00150   return (status);
00151 }
00152
00153 /**
00154   * @brief  Initialize LPUART registers according to the specified
00155   *         parameters in LPUART_InitStruct.
00156   * @note   As some bits in LPUART configuration registers can only be written when the LPUART is disabled (USART_CR1_UE bit =0),
00157   *         LPUART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
00158   * @note   Baud rate value stored in LPUART_InitStruct BaudRate field, should be valid (different from 0).
00159   * @param  LPUARTx LPUART Instance
00160   * @param  LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure
00161   *         that contains the configuration information for the specified LPUART peripheral.
00162   * @retval An ErrorStatus enumeration value:
00163   *          - SUCCESS: LPUART registers are initialized according to LPUART_InitStruct content
00164   *          - ERROR: Problem occurred during LPUART Registers initialization
00165   */
00166 ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct)
00167 {
00168   ErrorStatus status = ERROR;
00169   uint32_t periphclk;
00170
00171   /* Check the parameters */
00172   assert_param(IS_LPUART_INSTANCE(LPUARTx));
00173   assert_param(IS_LL_LPUART_PRESCALER(LPUART_InitStruct->PrescalerValue));
00174   assert_param(IS_LL_LPUART_BAUDRATE(LPUART_InitStruct->BaudRate));
00175   assert_param(IS_LL_LPUART_DATAWIDTH(LPUART_InitStruct->DataWidth));
00176   assert_param(IS_LL_LPUART_STOPBITS(LPUART_InitStruct->StopBits));
00177   assert_param(IS_LL_LPUART_PARITY(LPUART_InitStruct->Parity));
00178   assert_param(IS_LL_LPUART_DIRECTION(LPUART_InitStruct->TransferDirection));
00179   assert_param(IS_LL_LPUART_HWCONTROL(LPUART_InitStruct->HardwareFlowControl));
00180
00181   /* LPUART needs to be in disabled state, in order to be able to configure some bits in
00182      CRx registers. Otherwise (LPUART not in Disabled state) => return ERROR */
00183   if (LL_LPUART_IsEnabled(LPUARTx) == 0U)
00184   {
00185     /*---------------------------- LPUART CR1 Configuration -----------------------
00186      * Configure LPUARTx CR1 (LPUART Word Length, Parity and Transfer Direction bits) with parameters:
00187      * - DataWidth:          USART_CR1_M bits according to LPUART_InitStruct->DataWidth value
00188      * - Parity:             USART_CR1_PCE, USART_CR1_PS bits according to LPUART_InitStruct->Parity value
00189      * - TransferDirection:  USART_CR1_TE, USART_CR1_RE bits according to LPUART_InitStruct->TransferDirection value
00190      */
00191     MODIFY_REG(LPUARTx->CR1,
00192                (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE),
00193                (LPUART_InitStruct->DataWidth | LPUART_InitStruct->Parity | LPUART_InitStruct->TransferDirection));
00194
00195     /*---------------------------- LPUART CR2 Configuration -----------------------
00196      * Configure LPUARTx CR2 (Stop bits) with parameters:
00197      * - Stop Bits:          USART_CR2_STOP bits according to LPUART_InitStruct->StopBits value.
00198      */
00199     LL_LPUART_SetStopBitsLength(LPUARTx, LPUART_InitStruct->StopBits);
00200
00201     /*---------------------------- LPUART CR3 Configuration -----------------------
00202      * Configure LPUARTx CR3 (Hardware Flow Control) with parameters:
00203      * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to LPUART_InitStruct->HardwareFlowControl value.
00204      */
00205     LL_LPUART_SetHWFlowCtrl(LPUARTx, LPUART_InitStruct->HardwareFlowControl);
00206
00207     /*---------------------------- LPUART BRR Configuration -----------------------
00208      * Retrieve Clock frequency used for LPUART Peripheral
00209      */
00210     periphclk = LL_RCC_GetLPUARTClockFreq(LL_RCC_LPUART1_CLKSOURCE);
00211
00212     /* Configure the LPUART Baud Rate :
00213        - prescaler value is required
00214        - valid baud rate value (different from 0) is required
00215        - Peripheral clock as returned by RCC service, should be valid (different from 0).
00216     */
00217     if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
00218         && (LPUART_InitStruct->BaudRate != 0U))
00219     {
00220       status = SUCCESS;
00221       LL_LPUART_SetBaudRate(LPUARTx,
00222                             periphclk,
00223                             LPUART_InitStruct->PrescalerValue,
00224                             LPUART_InitStruct->BaudRate);
00225
00226       /* Check BRR is greater than or equal to 0x300 */
00227       assert_param(IS_LL_LPUART_BRR_MIN(LPUARTx->BRR));
00228
00229       /* Check BRR is lower than or equal to 0xFFFFF */
00230       assert_param(IS_LL_LPUART_BRR_MAX(LPUARTx->BRR));
00231     }
00232
00233     /*---------------------------- LPUART PRESC Configuration -----------------------
00234      * Configure LPUARTx PRESC (Prescaler) with parameters:
00235      * - PrescalerValue: LPUART_PRESC_PRESCALER bits according to LPUART_InitStruct->PrescalerValue value.
00236      */
00237     LL_LPUART_SetPrescaler(LPUARTx, LPUART_InitStruct->PrescalerValue);
00238   }
00239
00240   return (status);
00241 }
00242
00243 /**
00244   * @brief Set each @ref LL_LPUART_InitTypeDef field to default value.
00245   * @param LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure
00246   *                          whose fields will be set to default values.
00247   * @retval None
00248   */
00249
00250 void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct)
00251 {
00252   /* Set LPUART_InitStruct fields to default values */
00253   LPUART_InitStruct->PrescalerValue      = LL_LPUART_PRESCALER_DIV1;
00254   LPUART_InitStruct->BaudRate            = 9600U;
00255   LPUART_InitStruct->DataWidth           = LL_LPUART_DATAWIDTH_8B;
00256   LPUART_InitStruct->StopBits            = LL_LPUART_STOPBITS_1;
00257   LPUART_InitStruct->Parity              = LL_LPUART_PARITY_NONE ;
00258   LPUART_InitStruct->TransferDirection   = LL_LPUART_DIRECTION_TX_RX;
00259   LPUART_InitStruct->HardwareFlowControl = LL_LPUART_HWCONTROL_NONE;
00260 }
00261
00262 /**
00263   * @}
00264   */
00265
00266 /**
00267   * @}
00268   */
00269
00270 /**
00271   * @}
00272   */
00273
00274 #endif /* defined (LPUART1) */
00275
00276 /**
00277   * @}
00278   */
00279
00280 #endif /* USE_FULL_LL_DRIVER */
00281
00282 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00283
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_lpuart.h Source File

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stm32wbxx_ll_lpuart.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_lpuart.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of LPUART LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_LL_LPUART_H
00022 #define STM32WBxx_LL_LPUART_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx.h"
00030
00031 /** @addtogroup STM32WBxx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (LPUART1)
00036
00037 /** @defgroup LPUART_LL LPUART
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /** @defgroup LPUART_LL_Private_Variables LPUART Private Variables
00044   * @{
00045   */
00046 /* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */
00047 static const uint16_t LPUART_PRESCALER_TAB[] =
00048 {
00049   (uint16_t)1,
00050   (uint16_t)2,
00051   (uint16_t)4,
00052   (uint16_t)6,
00053   (uint16_t)8,
00054   (uint16_t)10,
00055   (uint16_t)12,
00056   (uint16_t)16,
00057   (uint16_t)32,
00058   (uint16_t)64,
00059   (uint16_t)128,
00060   (uint16_t)256
00061 };
00062 /**
00063   * @}
00064   */
00065
00066 /* Private constants ---------------------------------------------------------*/
00067 /** @defgroup LPUART_LL_Private_Constants LPUART Private Constants
00068   * @{
00069   */
00070 /* Defines used in Baud Rate related macros and corresponding register setting computation */
00071 #define LPUART_LPUARTDIV_FREQ_MUL     256U
00072 #define LPUART_BRR_MASK               0x000FFFFFU
00073 #define LPUART_BRR_MIN_VALUE          0x00000300U
00074 /**
00075   * @}
00076   */
00077
00078
00079 /* Private macros ------------------------------------------------------------*/
00080 #if defined(USE_FULL_LL_DRIVER)
00081 /** @defgroup LPUART_LL_Private_Macros LPUART Private Macros
00082   * @{
00083   */
00084 /**
00085   * @}
00086   */
00087 #endif /*USE_FULL_LL_DRIVER*/
00088
00089 /* Exported types ------------------------------------------------------------*/
00090 #if defined(USE_FULL_LL_DRIVER)
00091 /** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures
00092   * @{
00093   */
00094
00095 /**
00096   * @brief LL LPUART Init Structure definition
00097   */
00098 typedef struct
00099 {
00100   uint32_t PrescalerValue;            /*!< Specifies the Prescaler to compute the communication baud rate.
00101                                            This parameter can be a value of @ref LPUART_LL_EC_PRESCALER.
00102
00103                                            This feature can be modified afterwards using unitary function @ref LL_LPUART_SetPrescaler().*/
00104
00105   uint32_t BaudRate;                  /*!< This field defines expected LPUART communication baud rate.
00106
00107                                            This feature can be modified afterwards using unitary function @ref LL_LPUART_SetBaudRate().*/
00108
00109   uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
00110                                            This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH.
00111
00112                                            This feature can be modified afterwards using unitary function @ref LL_LPUART_SetDataWidth().*/
00113
00114   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
00115                                            This parameter can be a value of @ref LPUART_LL_EC_STOPBITS.
00116
00117                                            This feature can be modified afterwards using unitary function @ref LL_LPUART_SetStopBitsLength().*/
00118
00119   uint32_t Parity;                    /*!< Specifies the parity mode.
00120                                            This parameter can be a value of @ref LPUART_LL_EC_PARITY.
00121
00122                                            This feature can be modified afterwards using unitary function @ref LL_LPUART_SetParity().*/
00123
00124   uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
00125                                            This parameter can be a value of @ref LPUART_LL_EC_DIRECTION.
00126
00127                                            This feature can be modified afterwards using unitary function @ref LL_LPUART_SetTransferDirection().*/
00128
00129   uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
00130                                            This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL.
00131
00132                                            This feature can be modified afterwards using unitary function @ref LL_LPUART_SetHWFlowCtrl().*/
00133
00134 } LL_LPUART_InitTypeDef;
00135
00136 /**
00137   * @}
00138   */
00139 #endif /* USE_FULL_LL_DRIVER */
00140
00141 /* Exported constants --------------------------------------------------------*/
00142 /** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants
00143   * @{
00144   */
00145
00146 /** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines
00147   * @brief    Flags defines which can be used with LL_LPUART_WriteReg function
00148   * @{
00149   */
00150 #define LL_LPUART_ICR_PECF                 USART_ICR_PECF                /*!< Parity error flag */
00151 #define LL_LPUART_ICR_FECF                 USART_ICR_FECF                /*!< Framing error flag */
00152 #define LL_LPUART_ICR_NCF                  USART_ICR_NECF                /*!< Noise error detected flag */
00153 #define LL_LPUART_ICR_ORECF                USART_ICR_ORECF               /*!< Overrun error flag */
00154 #define LL_LPUART_ICR_IDLECF               USART_ICR_IDLECF              /*!< Idle line detected flag */
00155 #define LL_LPUART_ICR_TXFECF               USART_ICR_TXFECF              /*!< TX FIFO Empty Clear flag */
00156 #define LL_LPUART_ICR_TCCF                 USART_ICR_TCCF                /*!< Transmission complete flag */
00157 #define LL_LPUART_ICR_CTSCF                USART_ICR_CTSCF               /*!< CTS flag */
00158 #define LL_LPUART_ICR_CMCF                 USART_ICR_CMCF                /*!< Character match flag */
00159 #define LL_LPUART_ICR_WUCF                 USART_ICR_WUCF                /*!< Wakeup from Stop mode flag */
00160 /**
00161   * @}
00162   */
00163
00164 /** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines
00165   * @brief    Flags defines which can be used with LL_LPUART_ReadReg function
00166   * @{
00167   */
00168 #define LL_LPUART_ISR_PE                   USART_ISR_PE                  /*!< Parity error flag */
00169 #define LL_LPUART_ISR_FE                   USART_ISR_FE                  /*!< Framing error flag */
00170 #define LL_LPUART_ISR_NE                   USART_ISR_NE                  /*!< Noise detected flag */
00171 #define LL_LPUART_ISR_ORE                  USART_ISR_ORE                 /*!< Overrun error flag */
00172 #define LL_LPUART_ISR_IDLE                 USART_ISR_IDLE                /*!< Idle line detected flag */
00173 #define LL_LPUART_ISR_RXNE_RXFNE           USART_ISR_RXNE_RXFNE          /*!< Read data register or RX FIFO not empty flag */
00174 #define LL_LPUART_ISR_TC                   USART_ISR_TC                  /*!< Transmission complete flag */
00175 #define LL_LPUART_ISR_TXE_TXFNF            USART_ISR_TXE_TXFNF           /*!< Transmit data register empty or TX FIFO Not Full flag*/
00176 #define LL_LPUART_ISR_CTSIF                USART_ISR_CTSIF               /*!< CTS interrupt flag */
00177 #define LL_LPUART_ISR_CTS                  USART_ISR_CTS                 /*!< CTS flag */
00178 #define LL_LPUART_ISR_BUSY                 USART_ISR_BUSY                /*!< Busy flag */
00179 #define LL_LPUART_ISR_CMF                  USART_ISR_CMF                 /*!< Character match flag */
00180 #define LL_LPUART_ISR_SBKF                 USART_ISR_SBKF                /*!< Send break flag */
00181 #define LL_LPUART_ISR_RWU                  USART_ISR_RWU                 /*!< Receiver wakeup from Mute mode flag */
00182 #define LL_LPUART_ISR_WUF                  USART_ISR_WUF                 /*!< Wakeup from Stop mode flag */
00183 #define LL_LPUART_ISR_TEACK                USART_ISR_TEACK               /*!< Transmit enable acknowledge flag */
00184 #define LL_LPUART_ISR_REACK                USART_ISR_REACK               /*!< Receive enable acknowledge flag */
00185 #define LL_LPUART_ISR_TXFE                 USART_ISR_TXFE                /*!< TX FIFO empty flag */
00186 #define LL_LPUART_ISR_RXFF                 USART_ISR_RXFF                /*!< RX FIFO full flag */
00187 #define LL_LPUART_ISR_RXFT                 USART_ISR_RXFT                /*!< RX FIFO threshold flag */
00188 #define LL_LPUART_ISR_TXFT                 USART_ISR_TXFT                /*!< TX FIFO threshold flag */
00189 /**
00190   * @}
00191   */
00192
00193 /** @defgroup LPUART_LL_EC_IT IT Defines
00194   * @brief    IT defines which can be used with LL_LPUART_ReadReg and  LL_LPUART_WriteReg functions
00195   * @{
00196   */
00197 #define LL_LPUART_CR1_IDLEIE               USART_CR1_IDLEIE              /*!< IDLE interrupt enable */
00198 #define LL_LPUART_CR1_RXNEIE_RXFNEIE       USART_CR1_RXNEIE_RXFNEIE      /*!< Read data register and RXFIFO not empty interrupt enable */
00199 #define LL_LPUART_CR1_TCIE                 USART_CR1_TCIE                /*!< Transmission complete interrupt enable */
00200 #define LL_LPUART_CR1_TXEIE_TXFNFIE        USART_CR1_TXEIE_TXFNFIE       /*!< Transmit data register empty and TX FIFO not full interrupt enable */
00201 #define LL_LPUART_CR1_PEIE                 USART_CR1_PEIE                /*!< Parity error */
00202 #define LL_LPUART_CR1_CMIE                 USART_CR1_CMIE                /*!< Character match interrupt enable */
00203 #define LL_LPUART_CR1_TXFEIE               USART_CR1_TXFEIE              /*!< TX FIFO empty interrupt enable */
00204 #define LL_LPUART_CR1_RXFFIE               USART_CR1_RXFFIE              /*!< RX FIFO full interrupt enable */
00205 #define LL_LPUART_CR3_EIE                  USART_CR3_EIE                 /*!< Error interrupt enable */
00206 #define LL_LPUART_CR3_CTSIE                USART_CR3_CTSIE               /*!< CTS interrupt enable */
00207 #define LL_LPUART_CR3_WUFIE                USART_CR3_WUFIE               /*!< Wakeup from Stop mode interrupt enable */
00208 #define LL_LPUART_CR3_TXFTIE               USART_CR3_TXFTIE              /*!< TX FIFO threshold interrupt enable */
00209 #define LL_LPUART_CR3_RXFTIE               USART_CR3_RXFTIE              /*!< RX FIFO threshold interrupt enable */
00210 /**
00211   * @}
00212   */
00213
00214 /** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold
00215   * @{
00216   */
00217 #define LL_LPUART_FIFOTHRESHOLD_1_8        0x00000000U /*!< FIFO reaches 1/8 of its depth */
00218 #define LL_LPUART_FIFOTHRESHOLD_1_4        0x00000001U /*!< FIFO reaches 1/4 of its depth */
00219 #define LL_LPUART_FIFOTHRESHOLD_1_2        0x00000002U /*!< FIFO reaches 1/2 of its depth */
00220 #define LL_LPUART_FIFOTHRESHOLD_3_4        0x00000003U /*!< FIFO reaches 3/4 of its depth */
00221 #define LL_LPUART_FIFOTHRESHOLD_7_8        0x00000004U /*!< FIFO reaches 7/8 of its depth */
00222 #define LL_LPUART_FIFOTHRESHOLD_8_8        0x00000005U /*!< FIFO becomes empty for TX and full for RX */
00223 /**
00224   * @}
00225   */
00226
00227 /** @defgroup LPUART_LL_EC_DIRECTION Direction
00228   * @{
00229   */
00230 #define LL_LPUART_DIRECTION_NONE           0x00000000U                        /*!< Transmitter and Receiver are disabled */
00231 #define LL_LPUART_DIRECTION_RX             USART_CR1_RE                       /*!< Transmitter is disabled and Receiver is enabled */
00232 #define LL_LPUART_DIRECTION_TX             USART_CR1_TE                       /*!< Transmitter is enabled and Receiver is disabled */
00233 #define LL_LPUART_DIRECTION_TX_RX          (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter and Receiver are enabled */
00234 /**
00235   * @}
00236   */
00237
00238 /** @defgroup LPUART_LL_EC_PARITY Parity Control
00239   * @{
00240   */
00241 #define LL_LPUART_PARITY_NONE              0x00000000U                        /*!< Parity control disabled */
00242 #define LL_LPUART_PARITY_EVEN              USART_CR1_PCE                      /*!< Parity control enabled and Even Parity is selected */
00243 #define LL_LPUART_PARITY_ODD               (USART_CR1_PCE | USART_CR1_PS)     /*!< Parity control enabled and Odd Parity is selected */
00244 /**
00245   * @}
00246   */
00247
00248 /** @defgroup LPUART_LL_EC_WAKEUP Wakeup
00249   * @{
00250   */
00251 #define LL_LPUART_WAKEUP_IDLELINE          0x00000000U                        /*!<  LPUART wake up from Mute mode on Idle Line */
00252 #define LL_LPUART_WAKEUP_ADDRESSMARK       USART_CR1_WAKE                     /*!<  LPUART wake up from Mute mode on Address Mark */
00253 /**
00254   * @}
00255   */
00256
00257 /** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth
00258   * @{
00259   */
00260 #define LL_LPUART_DATAWIDTH_7B             USART_CR1_M1                       /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
00261 #define LL_LPUART_DATAWIDTH_8B             0x00000000U                        /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
00262 #define LL_LPUART_DATAWIDTH_9B             USART_CR1_M0                       /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
00263 /**
00264   * @}
00265   */
00266
00267 /** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler
00268   * @{
00269   */
00270 #define LL_LPUART_PRESCALER_DIV1           0x00000000U                                                                   /*!< Input clock not devided   */
00271 #define LL_LPUART_PRESCALER_DIV2           (USART_PRESC_PRESCALER_0)                                                     /*!< Input clock devided by 2  */
00272 #define LL_LPUART_PRESCALER_DIV4           (USART_PRESC_PRESCALER_1)                                                     /*!< Input clock devided by 4  */
00273 #define LL_LPUART_PRESCALER_DIV6           (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)                           /*!< Input clock devided by 6  */
00274 #define LL_LPUART_PRESCALER_DIV8           (USART_PRESC_PRESCALER_2)                                                     /*!< Input clock devided by 8  */
00275 #define LL_LPUART_PRESCALER_DIV10          (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0)                           /*!< Input clock devided by 10 */
00276 #define LL_LPUART_PRESCALER_DIV12          (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1)                           /*!< Input clock devided by 12 */
00277 #define LL_LPUART_PRESCALER_DIV16          (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 16 */
00278 #define LL_LPUART_PRESCALER_DIV32          (USART_PRESC_PRESCALER_3)                                                     /*!< Input clock devided by 32 */
00279 #define LL_LPUART_PRESCALER_DIV64          (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0)                           /*!< Input clock devided by 64 */
00280 #define LL_LPUART_PRESCALER_DIV128         (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1)                           /*!< Input clock devided by 128 */
00281 #define LL_LPUART_PRESCALER_DIV256         (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 256 */
00282 /**
00283   * @}
00284   */
00285
00286 /** @defgroup LPUART_LL_EC_STOPBITS Stop Bits
00287   * @{
00288   */
00289 #define LL_LPUART_STOPBITS_1               0x00000000U                        /*!< 1 stop bit */
00290 #define LL_LPUART_STOPBITS_2               USART_CR2_STOP_1                   /*!< 2 stop bits */
00291 /**
00292   * @}
00293   */
00294
00295 /** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap
00296   * @{
00297   */
00298 #define LL_LPUART_TXRX_STANDARD            0x00000000U                        /*!< TX/RX pins are used as defined in standard pinout */
00299 #define LL_LPUART_TXRX_SWAPPED             (USART_CR2_SWAP)                   /*!< TX and RX pins functions are swapped.             */
00300 /**
00301   * @}
00302   */
00303
00304 /** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
00305   * @{
00306   */
00307 #define LL_LPUART_RXPIN_LEVEL_STANDARD     0x00000000U                        /*!< RX pin signal works using the standard logic levels */
00308 #define LL_LPUART_RXPIN_LEVEL_INVERTED     (USART_CR2_RXINV)                  /*!< RX pin signal values are inverted.                  */
00309 /**
00310   * @}
00311   */
00312
00313 /** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
00314   * @{
00315   */
00316 #define LL_LPUART_TXPIN_LEVEL_STANDARD     0x00000000U                        /*!< TX pin signal works using the standard logic levels */
00317 #define LL_LPUART_TXPIN_LEVEL_INVERTED     (USART_CR2_TXINV)                  /*!< TX pin signal values are inverted.                  */
00318 /**
00319   * @}
00320   */
00321
00322 /** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion
00323   * @{
00324   */
00325 #define LL_LPUART_BINARY_LOGIC_POSITIVE    0x00000000U                        /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
00326 #define LL_LPUART_BINARY_LOGIC_NEGATIVE    USART_CR2_DATAINV                  /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
00327 /**
00328   * @}
00329   */
00330
00331 /** @defgroup LPUART_LL_EC_BITORDER Bit Order
00332   * @{
00333   */
00334 #define LL_LPUART_BITORDER_LSBFIRST        0x00000000U                        /*!< data is transmitted/received with data bit 0 first, following the start bit */
00335 #define LL_LPUART_BITORDER_MSBFIRST        USART_CR2_MSBFIRST                 /*!< data is transmitted/received with the MSB first, following the start bit */
00336 /**
00337   * @}
00338   */
00339
00340 /** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection
00341   * @{
00342   */
00343 #define LL_LPUART_ADDRESS_DETECT_4B        0x00000000U                        /*!< 4-bit address detection method selected */
00344 #define LL_LPUART_ADDRESS_DETECT_7B        USART_CR2_ADDM7                    /*!< 7-bit address detection (in 8-bit data mode) method selected */
00345 /**
00346   * @}
00347   */
00348
00349 /** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control
00350   * @{
00351   */
00352 #define LL_LPUART_HWCONTROL_NONE           0x00000000U                        /*!< CTS and RTS hardware flow control disabled */
00353 #define LL_LPUART_HWCONTROL_RTS            USART_CR3_RTSE                     /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
00354 #define LL_LPUART_HWCONTROL_CTS            USART_CR3_CTSE                     /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
00355 #define LL_LPUART_HWCONTROL_RTS_CTS        (USART_CR3_RTSE | USART_CR3_CTSE)  /*!< CTS and RTS hardware flow control enabled */
00356 /**
00357   * @}
00358   */
00359
00360 /** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation
00361   * @{
00362   */
00363 #define LL_LPUART_WAKEUP_ON_ADDRESS        0x00000000U                             /*!< Wake up active on address match */
00364 #define LL_LPUART_WAKEUP_ON_STARTBIT       USART_CR3_WUS_1                         /*!< Wake up active on Start bit detection */
00365 #define LL_LPUART_WAKEUP_ON_RXNE           (USART_CR3_WUS_0 | USART_CR3_WUS_1)     /*!< Wake up active on RXNE */
00366 /**
00367   * @}
00368   */
00369
00370 /** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity
00371   * @{
00372   */
00373 #define LL_LPUART_DE_POLARITY_HIGH         0x00000000U                        /*!< DE signal is active high */
00374 #define LL_LPUART_DE_POLARITY_LOW          USART_CR3_DEP                      /*!< DE signal is active low */
00375 /**
00376   * @}
00377   */
00378
00379 /** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data
00380   * @{
00381   */
00382 #define LL_LPUART_DMA_REG_DATA_TRANSMIT    0x00000000U                       /*!< Get address of data register used for transmission */
00383 #define LL_LPUART_DMA_REG_DATA_RECEIVE     0x00000001U                       /*!< Get address of data register used for reception */
00384 /**
00385   * @}
00386   */
00387
00388 /**
00389   * @}
00390   */
00391
00392 /* Exported macro ------------------------------------------------------------*/
00393 /** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros
00394   * @{
00395   */
00396
00397 /** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros
00398   * @{
00399   */
00400
00401 /**
00402   * @brief  Write a value in LPUART register
00403   * @param  __INSTANCE__ LPUART Instance
00404   * @param  __REG__ Register to be written
00405   * @param  __VALUE__ Value to be written in the register
00406   * @retval None
00407   */
00408 #define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00409
00410 /**
00411   * @brief  Read a value in LPUART register
00412   * @param  __INSTANCE__ LPUART Instance
00413   * @param  __REG__ Register to be read
00414   * @retval Register value
00415   */
00416 #define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00417 /**
00418   * @}
00419   */
00420
00421 /** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros
00422   * @{
00423   */
00424
00425 /**
00426   * @brief  Compute LPUARTDIV value according to Peripheral Clock and
00427   *         expected Baud Rate (20-bit value of LPUARTDIV is returned)
00428   * @param  __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance
00429   * @param  __PRESCALER__ This parameter can be one of the following values:
00430   *         @arg @ref LL_LPUART_PRESCALER_DIV1
00431   *         @arg @ref LL_LPUART_PRESCALER_DIV2
00432   *         @arg @ref LL_LPUART_PRESCALER_DIV4
00433   *         @arg @ref LL_LPUART_PRESCALER_DIV6
00434   *         @arg @ref LL_LPUART_PRESCALER_DIV8
00435   *         @arg @ref LL_LPUART_PRESCALER_DIV10
00436   *         @arg @ref LL_LPUART_PRESCALER_DIV12
00437   *         @arg @ref LL_LPUART_PRESCALER_DIV16
00438   *         @arg @ref LL_LPUART_PRESCALER_DIV32
00439   *         @arg @ref LL_LPUART_PRESCALER_DIV64
00440   *         @arg @ref LL_LPUART_PRESCALER_DIV128
00441   *         @arg @ref LL_LPUART_PRESCALER_DIV256
00442   * @param  __BAUDRATE__ Baud Rate value to achieve
00443   * @retval LPUARTDIV value to be used for BRR register filling
00444   */
00445 #define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)])) * LPUART_LPUARTDIV_FREQ_MUL)\
00446                                                                                 + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)
00447
00448 /**
00449   * @}
00450   */
00451
00452 /**
00453   * @}
00454   */
00455
00456 /* Exported functions --------------------------------------------------------*/
00457 /** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions
00458   * @{
00459   */
00460
00461 /** @defgroup LPUART_LL_EF_Configuration Configuration functions
00462   * @{
00463   */
00464
00465 /**
00466   * @brief  LPUART Enable
00467   * @rmtoll CR1          UE            LL_LPUART_Enable
00468   * @param  LPUARTx LPUART Instance
00469   * @retval None
00470   */
00471 __STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx)
00472 {
00473   SET_BIT(LPUARTx->CR1, USART_CR1_UE);
00474 }
00475
00476 /**
00477   * @brief  LPUART Disable
00478   * @note   When LPUART is disabled, LPUART prescalers and outputs are stopped immediately,
00479   *         and current operations are discarded. The configuration of the LPUART is kept, but all the status
00480   *         flags, in the LPUARTx_ISR are set to their default values.
00481   * @note   In order to go into low-power mode without generating errors on the line,
00482   *         the TE bit must be reset before and the software must wait
00483   *         for the TC bit in the LPUART_ISR to be set before resetting the UE bit.
00484   *         The DMA requests are also reset when UE = 0 so the DMA channel must
00485   *         be disabled before resetting the UE bit.
00486   * @rmtoll CR1          UE            LL_LPUART_Disable
00487   * @param  LPUARTx LPUART Instance
00488   * @retval None
00489   */
00490 __STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx)
00491 {
00492   CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE);
00493 }
00494
00495 /**
00496   * @brief  Indicate if LPUART is enabled
00497   * @rmtoll CR1          UE            LL_LPUART_IsEnabled
00498   * @param  LPUARTx LPUART Instance
00499   * @retval State of bit (1 or 0).
00500   */
00501 __STATIC_INLINE uint32_t LL_LPUART_IsEnabled(USART_TypeDef *LPUARTx)
00502 {
00503   return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
00504 }
00505
00506 /**
00507   * @brief  FIFO Mode Enable
00508   * @rmtoll CR1          FIFOEN        LL_LPUART_EnableFIFO
00509   * @param  LPUARTx LPUART Instance
00510   * @retval None
00511   */
00512 __STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx)
00513 {
00514   SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
00515 }
00516
00517 /**
00518   * @brief  FIFO Mode Disable
00519   * @rmtoll CR1          FIFOEN        LL_LPUART_DisableFIFO
00520   * @param  LPUARTx LPUART Instance
00521   * @retval None
00522   */
00523 __STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx)
00524 {
00525   CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
00526 }
00527
00528 /**
00529   * @brief  Indicate if FIFO Mode is enabled
00530   * @rmtoll CR1          FIFOEN        LL_LPUART_IsEnabledFIFO
00531   * @param  LPUARTx LPUART Instance
00532   * @retval State of bit (1 or 0).
00533   */
00534 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(USART_TypeDef *LPUARTx)
00535 {
00536   return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
00537 }
00538
00539 /**
00540   * @brief  Configure TX FIFO Threshold
00541   * @rmtoll CR3          TXFTCFG       LL_LPUART_SetTXFIFOThreshold
00542   * @param  LPUARTx LPUART Instance
00543   * @param  Threshold This parameter can be one of the following values:
00544   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
00545   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
00546   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
00547   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
00548   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
00549   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
00550   * @retval None
00551   */
00552 __STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
00553 {
00554   MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
00555 }
00556
00557 /**
00558   * @brief  Return TX FIFO Threshold Configuration
00559   * @rmtoll CR3          TXFTCFG       LL_LPUART_GetTXFIFOThreshold
00560   * @param  LPUARTx LPUART Instance
00561   * @retval Returned value can be one of the following values:
00562   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
00563   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
00564   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
00565   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
00566   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
00567   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
00568   */
00569 __STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(USART_TypeDef *LPUARTx)
00570 {
00571   return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
00572 }
00573
00574 /**
00575   * @brief  Configure RX FIFO Threshold
00576   * @rmtoll CR3          RXFTCFG       LL_LPUART_SetRXFIFOThreshold
00577   * @param  LPUARTx LPUART Instance
00578   * @param  Threshold This parameter can be one of the following values:
00579   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
00580   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
00581   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
00582   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
00583   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
00584   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
00585   * @retval None
00586   */
00587 __STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
00588 {
00589   MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
00590 }
00591
00592 /**
00593   * @brief  Return RX FIFO Threshold Configuration
00594   * @rmtoll CR3          RXFTCFG       LL_LPUART_GetRXFIFOThreshold
00595   * @param  LPUARTx LPUART Instance
00596   * @retval Returned value can be one of the following values:
00597   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
00598   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
00599   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
00600   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
00601   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
00602   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
00603   */
00604 __STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(USART_TypeDef *LPUARTx)
00605 {
00606   return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
00607 }
00608
00609 /**
00610   * @brief  Configure TX and RX FIFOs Threshold
00611   * @rmtoll CR3          TXFTCFG       LL_LPUART_ConfigFIFOsThreshold\n
00612   *         CR3          RXFTCFG       LL_LPUART_ConfigFIFOsThreshold
00613   * @param  LPUARTx LPUART Instance
00614   * @param  TXThreshold This parameter can be one of the following values:
00615   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
00616   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
00617   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
00618   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
00619   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
00620   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
00621   * @param  RXThreshold This parameter can be one of the following values:
00622   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
00623   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
00624   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
00625   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
00626   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
00627   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
00628   * @retval None
00629   */
00630 __STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)
00631 {
00632   MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | (RXThreshold << USART_CR3_RXFTCFG_Pos));
00633 }
00634
00635 /**
00636   * @brief  LPUART enabled in STOP Mode
00637   * @note   When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that
00638   *         LPUART clock selection is HSI or LSE in RCC.
00639   * @rmtoll CR1          UESM          LL_LPUART_EnableInStopMode
00640   * @param  LPUARTx LPUART Instance
00641   * @retval None
00642   */
00643 __STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)
00644 {
00645   SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
00646 }
00647
00648 /**
00649   * @brief  LPUART disabled in STOP Mode
00650   * @note   When this function is disabled, LPUART is not able to wake up the MCU from Stop mode
00651   * @rmtoll CR1          UESM          LL_LPUART_DisableInStopMode
00652   * @param  LPUARTx LPUART Instance
00653   * @retval None
00654   */
00655 __STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)
00656 {
00657   CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
00658 }
00659
00660 /**
00661   * @brief  Indicate if LPUART is enabled in STOP Mode
00662   *         (able to wake up MCU from Stop mode or not)
00663   * @rmtoll CR1          UESM          LL_LPUART_IsEnabledInStopMode
00664   * @param  LPUARTx LPUART Instance
00665   * @retval State of bit (1 or 0).
00666   */
00667 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx)
00668 {
00669   return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
00670 }
00671
00672 /**
00673   * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
00674   * @rmtoll CR1          RE            LL_LPUART_EnableDirectionRx
00675   * @param  LPUARTx LPUART Instance
00676   * @retval None
00677   */
00678 __STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)
00679 {
00680   SET_BIT(LPUARTx->CR1, USART_CR1_RE);
00681 }
00682
00683 /**
00684   * @brief  Receiver Disable
00685   * @rmtoll CR1          RE            LL_LPUART_DisableDirectionRx
00686   * @param  LPUARTx LPUART Instance
00687   * @retval None
00688   */
00689 __STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)
00690 {
00691   CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
00692 }
00693
00694 /**
00695   * @brief  Transmitter Enable
00696   * @rmtoll CR1          TE            LL_LPUART_EnableDirectionTx
00697   * @param  LPUARTx LPUART Instance
00698   * @retval None
00699   */
00700 __STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)
00701 {
00702   SET_BIT(LPUARTx->CR1, USART_CR1_TE);
00703 }
00704
00705 /**
00706   * @brief  Transmitter Disable
00707   * @rmtoll CR1          TE            LL_LPUART_DisableDirectionTx
00708   * @param  LPUARTx LPUART Instance
00709   * @retval None
00710   */
00711 __STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)
00712 {
00713   CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
00714 }
00715
00716 /**
00717   * @brief  Configure simultaneously enabled/disabled states
00718   *         of Transmitter and Receiver
00719   * @rmtoll CR1          RE            LL_LPUART_SetTransferDirection\n
00720   *         CR1          TE            LL_LPUART_SetTransferDirection
00721   * @param  LPUARTx LPUART Instance
00722   * @param  TransferDirection This parameter can be one of the following values:
00723   *         @arg @ref LL_LPUART_DIRECTION_NONE
00724   *         @arg @ref LL_LPUART_DIRECTION_RX
00725   *         @arg @ref LL_LPUART_DIRECTION_TX
00726   *         @arg @ref LL_LPUART_DIRECTION_TX_RX
00727   * @retval None
00728   */
00729 __STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection)
00730 {
00731   MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
00732 }
00733
00734 /**
00735   * @brief  Return enabled/disabled states of Transmitter and Receiver
00736   * @rmtoll CR1          RE            LL_LPUART_GetTransferDirection\n
00737   *         CR1          TE            LL_LPUART_GetTransferDirection
00738   * @param  LPUARTx LPUART Instance
00739   * @retval Returned value can be one of the following values:
00740   *         @arg @ref LL_LPUART_DIRECTION_NONE
00741   *         @arg @ref LL_LPUART_DIRECTION_RX
00742   *         @arg @ref LL_LPUART_DIRECTION_TX
00743   *         @arg @ref LL_LPUART_DIRECTION_TX_RX
00744   */
00745 __STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(USART_TypeDef *LPUARTx)
00746 {
00747   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE));
00748 }
00749
00750 /**
00751   * @brief  Configure Parity (enabled/disabled and parity mode if enabled)
00752   * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
00753   *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
00754   *         (depending on data width) and parity is checked on the received data.
00755   * @rmtoll CR1          PS            LL_LPUART_SetParity\n
00756   *         CR1          PCE           LL_LPUART_SetParity
00757   * @param  LPUARTx LPUART Instance
00758   * @param  Parity This parameter can be one of the following values:
00759   *         @arg @ref LL_LPUART_PARITY_NONE
00760   *         @arg @ref LL_LPUART_PARITY_EVEN
00761   *         @arg @ref LL_LPUART_PARITY_ODD
00762   * @retval None
00763   */
00764 __STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity)
00765 {
00766   MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
00767 }
00768
00769 /**
00770   * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
00771   * @rmtoll CR1          PS            LL_LPUART_GetParity\n
00772   *         CR1          PCE           LL_LPUART_GetParity
00773   * @param  LPUARTx LPUART Instance
00774   * @retval Returned value can be one of the following values:
00775   *         @arg @ref LL_LPUART_PARITY_NONE
00776   *         @arg @ref LL_LPUART_PARITY_EVEN
00777   *         @arg @ref LL_LPUART_PARITY_ODD
00778   */
00779 __STATIC_INLINE uint32_t LL_LPUART_GetParity(USART_TypeDef *LPUARTx)
00780 {
00781   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
00782 }
00783
00784 /**
00785   * @brief  Set Receiver Wake Up method from Mute mode.
00786   * @rmtoll CR1          WAKE          LL_LPUART_SetWakeUpMethod
00787   * @param  LPUARTx LPUART Instance
00788   * @param  Method This parameter can be one of the following values:
00789   *         @arg @ref LL_LPUART_WAKEUP_IDLELINE
00790   *         @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
00791   * @retval None
00792   */
00793 __STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method)
00794 {
00795   MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method);
00796 }
00797
00798 /**
00799   * @brief  Return Receiver Wake Up method from Mute mode
00800   * @rmtoll CR1          WAKE          LL_LPUART_GetWakeUpMethod
00801   * @param  LPUARTx LPUART Instance
00802   * @retval Returned value can be one of the following values:
00803   *         @arg @ref LL_LPUART_WAKEUP_IDLELINE
00804   *         @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
00805   */
00806 __STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(USART_TypeDef *LPUARTx)
00807 {
00808   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));
00809 }
00810
00811 /**
00812   * @brief  Set Word length (nb of data bits, excluding start and stop bits)
00813   * @rmtoll CR1          M             LL_LPUART_SetDataWidth
00814   * @param  LPUARTx LPUART Instance
00815   * @param  DataWidth This parameter can be one of the following values:
00816   *         @arg @ref LL_LPUART_DATAWIDTH_7B
00817   *         @arg @ref LL_LPUART_DATAWIDTH_8B
00818   *         @arg @ref LL_LPUART_DATAWIDTH_9B
00819   * @retval None
00820   */
00821 __STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth)
00822 {
00823   MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth);
00824 }
00825
00826 /**
00827   * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
00828   * @rmtoll CR1          M             LL_LPUART_GetDataWidth
00829   * @param  LPUARTx LPUART Instance
00830   * @retval Returned value can be one of the following values:
00831   *         @arg @ref LL_LPUART_DATAWIDTH_7B
00832   *         @arg @ref LL_LPUART_DATAWIDTH_8B
00833   *         @arg @ref LL_LPUART_DATAWIDTH_9B
00834   */
00835 __STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(USART_TypeDef *LPUARTx)
00836 {
00837   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));
00838 }
00839
00840 /**
00841   * @brief  Allow switch between Mute Mode and Active mode
00842   * @rmtoll CR1          MME           LL_LPUART_EnableMuteMode
00843   * @param  LPUARTx LPUART Instance
00844   * @retval None
00845   */
00846 __STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)
00847 {
00848   SET_BIT(LPUARTx->CR1, USART_CR1_MME);
00849 }
00850
00851 /**
00852   * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.
00853   * @rmtoll CR1          MME           LL_LPUART_DisableMuteMode
00854   * @param  LPUARTx LPUART Instance
00855   * @retval None
00856   */
00857 __STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)
00858 {
00859   CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
00860 }
00861
00862 /**
00863   * @brief  Indicate if switch between Mute Mode and Active mode is allowed
00864   * @rmtoll CR1          MME           LL_LPUART_IsEnabledMuteMode
00865   * @param  LPUARTx LPUART Instance
00866   * @retval State of bit (1 or 0).
00867   */
00868 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(USART_TypeDef *LPUARTx)
00869 {
00870   return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
00871 }
00872
00873 /**
00874   * @brief  Configure Clock source prescaler for baudrate generator and oversampling
00875   * @rmtoll PRESC        PRESCALER     LL_LPUART_SetPrescaler
00876   * @param  LPUARTx LPUART Instance
00877   * @param  PrescalerValue This parameter can be one of the following values:
00878   *         @arg @ref LL_LPUART_PRESCALER_DIV1
00879   *         @arg @ref LL_LPUART_PRESCALER_DIV2
00880   *         @arg @ref LL_LPUART_PRESCALER_DIV4
00881   *         @arg @ref LL_LPUART_PRESCALER_DIV6
00882   *         @arg @ref LL_LPUART_PRESCALER_DIV8
00883   *         @arg @ref LL_LPUART_PRESCALER_DIV10
00884   *         @arg @ref LL_LPUART_PRESCALER_DIV12
00885   *         @arg @ref LL_LPUART_PRESCALER_DIV16
00886   *         @arg @ref LL_LPUART_PRESCALER_DIV32
00887   *         @arg @ref LL_LPUART_PRESCALER_DIV64
00888   *         @arg @ref LL_LPUART_PRESCALER_DIV128
00889   *         @arg @ref LL_LPUART_PRESCALER_DIV256
00890   * @retval None
00891   */
00892 __STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue)
00893 {
00894   MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
00895 }
00896
00897 /**
00898   * @brief  Retrieve the Clock source prescaler for baudrate generator and oversampling
00899   * @rmtoll PRESC        PRESCALER     LL_LPUART_GetPrescaler
00900   * @param  LPUARTx LPUART Instance
00901   * @retval Returned value can be one of the following values:
00902   *         @arg @ref LL_LPUART_PRESCALER_DIV1
00903   *         @arg @ref LL_LPUART_PRESCALER_DIV2
00904   *         @arg @ref LL_LPUART_PRESCALER_DIV4
00905   *         @arg @ref LL_LPUART_PRESCALER_DIV6
00906   *         @arg @ref LL_LPUART_PRESCALER_DIV8
00907   *         @arg @ref LL_LPUART_PRESCALER_DIV10
00908   *         @arg @ref LL_LPUART_PRESCALER_DIV12
00909   *         @arg @ref LL_LPUART_PRESCALER_DIV16
00910   *         @arg @ref LL_LPUART_PRESCALER_DIV32
00911   *         @arg @ref LL_LPUART_PRESCALER_DIV64
00912   *         @arg @ref LL_LPUART_PRESCALER_DIV128
00913   *         @arg @ref LL_LPUART_PRESCALER_DIV256
00914   */
00915 __STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(USART_TypeDef *LPUARTx)
00916 {
00917   return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER));
00918 }
00919
00920 /**
00921   * @brief  Set the length of the stop bits
00922   * @rmtoll CR2          STOP          LL_LPUART_SetStopBitsLength
00923   * @param  LPUARTx LPUART Instance
00924   * @param  StopBits This parameter can be one of the following values:
00925   *         @arg @ref LL_LPUART_STOPBITS_1
00926   *         @arg @ref LL_LPUART_STOPBITS_2
00927   * @retval None
00928   */
00929 __STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits)
00930 {
00931   MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
00932 }
00933
00934 /**
00935   * @brief  Retrieve the length of the stop bits
00936   * @rmtoll CR2          STOP          LL_LPUART_GetStopBitsLength
00937   * @param  LPUARTx LPUART Instance
00938   * @retval Returned value can be one of the following values:
00939   *         @arg @ref LL_LPUART_STOPBITS_1
00940   *         @arg @ref LL_LPUART_STOPBITS_2
00941   */
00942 __STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(USART_TypeDef *LPUARTx)
00943 {
00944   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));
00945 }
00946
00947 /**
00948   * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
00949   * @note   Call of this function is equivalent to following function call sequence :
00950   *         - Data Width configuration using @ref LL_LPUART_SetDataWidth() function
00951   *         - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function
00952   *         - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function
00953   * @rmtoll CR1          PS            LL_LPUART_ConfigCharacter\n
00954   *         CR1          PCE           LL_LPUART_ConfigCharacter\n
00955   *         CR1          M             LL_LPUART_ConfigCharacter\n
00956   *         CR2          STOP          LL_LPUART_ConfigCharacter
00957   * @param  LPUARTx LPUART Instance
00958   * @param  DataWidth This parameter can be one of the following values:
00959   *         @arg @ref LL_LPUART_DATAWIDTH_7B
00960   *         @arg @ref LL_LPUART_DATAWIDTH_8B
00961   *         @arg @ref LL_LPUART_DATAWIDTH_9B
00962   * @param  Parity This parameter can be one of the following values:
00963   *         @arg @ref LL_LPUART_PARITY_NONE
00964   *         @arg @ref LL_LPUART_PARITY_EVEN
00965   *         @arg @ref LL_LPUART_PARITY_ODD
00966   * @param  StopBits This parameter can be one of the following values:
00967   *         @arg @ref LL_LPUART_STOPBITS_1
00968   *         @arg @ref LL_LPUART_STOPBITS_2
00969   * @retval None
00970   */
00971 __STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity,
00972                                                uint32_t StopBits)
00973 {
00974   MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
00975   MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
00976 }
00977
00978 /**
00979   * @brief  Configure TX/RX pins swapping setting.
00980   * @rmtoll CR2          SWAP          LL_LPUART_SetTXRXSwap
00981   * @param  LPUARTx LPUART Instance
00982   * @param  SwapConfig This parameter can be one of the following values:
00983   *         @arg @ref LL_LPUART_TXRX_STANDARD
00984   *         @arg @ref LL_LPUART_TXRX_SWAPPED
00985   * @retval None
00986   */
00987 __STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig)
00988 {
00989   MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig);
00990 }
00991
00992 /**
00993   * @brief  Retrieve TX/RX pins swapping configuration.
00994   * @rmtoll CR2          SWAP          LL_LPUART_GetTXRXSwap
00995   * @param  LPUARTx LPUART Instance
00996   * @retval Returned value can be one of the following values:
00997   *         @arg @ref LL_LPUART_TXRX_STANDARD
00998   *         @arg @ref LL_LPUART_TXRX_SWAPPED
00999   */
01000 __STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(USART_TypeDef *LPUARTx)
01001 {
01002   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));
01003 }
01004
01005 /**
01006   * @brief  Configure RX pin active level logic
01007   * @rmtoll CR2          RXINV         LL_LPUART_SetRXPinLevel
01008   * @param  LPUARTx LPUART Instance
01009   * @param  PinInvMethod This parameter can be one of the following values:
01010   *         @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
01011   *         @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
01012   * @retval None
01013   */
01014 __STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
01015 {
01016   MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod);
01017 }
01018
01019 /**
01020   * @brief  Retrieve RX pin active level logic configuration
01021   * @rmtoll CR2          RXINV         LL_LPUART_GetRXPinLevel
01022   * @param  LPUARTx LPUART Instance
01023   * @retval Returned value can be one of the following values:
01024   *         @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
01025   *         @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
01026   */
01027 __STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(USART_TypeDef *LPUARTx)
01028 {
01029   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));
01030 }
01031
01032 /**
01033   * @brief  Configure TX pin active level logic
01034   * @rmtoll CR2          TXINV         LL_LPUART_SetTXPinLevel
01035   * @param  LPUARTx LPUART Instance
01036   * @param  PinInvMethod This parameter can be one of the following values:
01037   *         @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
01038   *         @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
01039   * @retval None
01040   */
01041 __STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
01042 {
01043   MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod);
01044 }
01045
01046 /**
01047   * @brief  Retrieve TX pin active level logic configuration
01048   * @rmtoll CR2          TXINV         LL_LPUART_GetTXPinLevel
01049   * @param  LPUARTx LPUART Instance
01050   * @retval Returned value can be one of the following values:
01051   *         @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
01052   *         @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
01053   */
01054 __STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(USART_TypeDef *LPUARTx)
01055 {
01056   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));
01057 }
01058
01059 /**
01060   * @brief  Configure Binary data logic.
01061   *
01062   * @note   Allow to define how Logical data from the data register are send/received :
01063   *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
01064   * @rmtoll CR2          DATAINV       LL_LPUART_SetBinaryDataLogic
01065   * @param  LPUARTx LPUART Instance
01066   * @param  DataLogic This parameter can be one of the following values:
01067   *         @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
01068   *         @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
01069   * @retval None
01070   */
01071 __STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic)
01072 {
01073   MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic);
01074 }
01075
01076 /**
01077   * @brief  Retrieve Binary data configuration
01078   * @rmtoll CR2          DATAINV       LL_LPUART_GetBinaryDataLogic
01079   * @param  LPUARTx LPUART Instance
01080   * @retval Returned value can be one of the following values:
01081   *         @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
01082   *         @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
01083   */
01084 __STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(USART_TypeDef *LPUARTx)
01085 {
01086   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));
01087 }
01088
01089 /**
01090   * @brief  Configure transfer bit order (either Less or Most Significant Bit First)
01091   * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
01092   *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
01093   * @rmtoll CR2          MSBFIRST      LL_LPUART_SetTransferBitOrder
01094   * @param  LPUARTx LPUART Instance
01095   * @param  BitOrder This parameter can be one of the following values:
01096   *         @arg @ref LL_LPUART_BITORDER_LSBFIRST
01097   *         @arg @ref LL_LPUART_BITORDER_MSBFIRST
01098   * @retval None
01099   */
01100 __STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder)
01101 {
01102   MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
01103 }
01104
01105 /**
01106   * @brief  Return transfer bit order (either Less or Most Significant Bit First)
01107   * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
01108   *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
01109   * @rmtoll CR2          MSBFIRST      LL_LPUART_GetTransferBitOrder
01110   * @param  LPUARTx LPUART Instance
01111   * @retval Returned value can be one of the following values:
01112   *         @arg @ref LL_LPUART_BITORDER_LSBFIRST
01113   *         @arg @ref LL_LPUART_BITORDER_MSBFIRST
01114   */
01115 __STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(USART_TypeDef *LPUARTx)
01116 {
01117   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));
01118 }
01119
01120 /**
01121   * @brief  Set Address of the LPUART node.
01122   * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
01123   *         for wake up with address mark detection.
01124   * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.
01125   *         (b7-b4 should be set to 0)
01126   *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.
01127   *         (This is used in multiprocessor communication during Mute mode or Stop mode,
01128   *         for wake up with 7-bit address mark detection.
01129   *         The MSB of the character sent by the transmitter should be equal to 1.
01130   *         It may also be used for character detection during normal reception,
01131   *         Mute mode inactive (for example, end of block detection in ModBus protocol).
01132   *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]
01133   *         value and CMF flag is set on match)
01134   * @rmtoll CR2          ADD           LL_LPUART_ConfigNodeAddress\n
01135   *         CR2          ADDM7         LL_LPUART_ConfigNodeAddress
01136   * @param  LPUARTx LPUART Instance
01137   * @param  AddressLen This parameter can be one of the following values:
01138   *         @arg @ref LL_LPUART_ADDRESS_DETECT_4B
01139   *         @arg @ref LL_LPUART_ADDRESS_DETECT_7B
01140   * @param  NodeAddress 4 or 7 bit Address of the LPUART node.
01141   * @retval None
01142   */
01143 __STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
01144 {
01145   MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
01146              (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
01147 }
01148
01149 /**
01150   * @brief  Return 8 bit Address of the LPUART node as set in ADD field of CR2.
01151   * @note   If 4-bit Address Detection is selected in ADDM7,
01152   *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
01153   *         If 7-bit Address Detection is selected in ADDM7,
01154   *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
01155   * @rmtoll CR2          ADD           LL_LPUART_GetNodeAddress
01156   * @param  LPUARTx LPUART Instance
01157   * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)
01158   */
01159 __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(USART_TypeDef *LPUARTx)
01160 {
01161   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
01162 }
01163
01164 /**
01165   * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
01166   * @rmtoll CR2          ADDM7         LL_LPUART_GetNodeAddressLen
01167   * @param  LPUARTx LPUART Instance
01168   * @retval Returned value can be one of the following values:
01169   *         @arg @ref LL_LPUART_ADDRESS_DETECT_4B
01170   *         @arg @ref LL_LPUART_ADDRESS_DETECT_7B
01171   */
01172 __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(USART_TypeDef *LPUARTx)
01173 {
01174   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));
01175 }
01176
01177 /**
01178   * @brief  Enable RTS HW Flow Control
01179   * @rmtoll CR3          RTSE          LL_LPUART_EnableRTSHWFlowCtrl
01180   * @param  LPUARTx LPUART Instance
01181   * @retval None
01182   */
01183 __STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
01184 {
01185   SET_BIT(LPUARTx->CR3, USART_CR3_RTSE);
01186 }
01187
01188 /**
01189   * @brief  Disable RTS HW Flow Control
01190   * @rmtoll CR3          RTSE          LL_LPUART_DisableRTSHWFlowCtrl
01191   * @param  LPUARTx LPUART Instance
01192   * @retval None
01193   */
01194 __STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
01195 {
01196   CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE);
01197 }
01198
01199 /**
01200   * @brief  Enable CTS HW Flow Control
01201   * @rmtoll CR3          CTSE          LL_LPUART_EnableCTSHWFlowCtrl
01202   * @param  LPUARTx LPUART Instance
01203   * @retval None
01204   */
01205 __STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
01206 {
01207   SET_BIT(LPUARTx->CR3, USART_CR3_CTSE);
01208 }
01209
01210 /**
01211   * @brief  Disable CTS HW Flow Control
01212   * @rmtoll CR3          CTSE          LL_LPUART_DisableCTSHWFlowCtrl
01213   * @param  LPUARTx LPUART Instance
01214   * @retval None
01215   */
01216 __STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
01217 {
01218   CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE);
01219 }
01220
01221 /**
01222   * @brief  Configure HW Flow Control mode (both CTS and RTS)
01223   * @rmtoll CR3          RTSE          LL_LPUART_SetHWFlowCtrl\n
01224   *         CR3          CTSE          LL_LPUART_SetHWFlowCtrl
01225   * @param  LPUARTx LPUART Instance
01226   * @param  HardwareFlowControl This parameter can be one of the following values:
01227   *         @arg @ref LL_LPUART_HWCONTROL_NONE
01228   *         @arg @ref LL_LPUART_HWCONTROL_RTS
01229   *         @arg @ref LL_LPUART_HWCONTROL_CTS
01230   *         @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
01231   * @retval None
01232   */
01233 __STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
01234 {
01235   MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
01236 }
01237
01238 /**
01239   * @brief  Return HW Flow Control configuration (both CTS and RTS)
01240   * @rmtoll CR3          RTSE          LL_LPUART_GetHWFlowCtrl\n
01241   *         CR3          CTSE          LL_LPUART_GetHWFlowCtrl
01242   * @param  LPUARTx LPUART Instance
01243   * @retval Returned value can be one of the following values:
01244   *         @arg @ref LL_LPUART_HWCONTROL_NONE
01245   *         @arg @ref LL_LPUART_HWCONTROL_RTS
01246   *         @arg @ref LL_LPUART_HWCONTROL_CTS
01247   *         @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
01248   */
01249 __STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(USART_TypeDef *LPUARTx)
01250 {
01251   return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
01252 }
01253
01254 /**
01255   * @brief  Enable Overrun detection
01256   * @rmtoll CR3          OVRDIS        LL_LPUART_EnableOverrunDetect
01257   * @param  LPUARTx LPUART Instance
01258   * @retval None
01259   */
01260 __STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx)
01261 {
01262   CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
01263 }
01264
01265 /**
01266   * @brief  Disable Overrun detection
01267   * @rmtoll CR3          OVRDIS        LL_LPUART_DisableOverrunDetect
01268   * @param  LPUARTx LPUART Instance
01269   * @retval None
01270   */
01271 __STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx)
01272 {
01273   SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
01274 }
01275
01276 /**
01277   * @brief  Indicate if Overrun detection is enabled
01278   * @rmtoll CR3          OVRDIS        LL_LPUART_IsEnabledOverrunDetect
01279   * @param  LPUARTx LPUART Instance
01280   * @retval State of bit (1 or 0).
01281   */
01282 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(USART_TypeDef *LPUARTx)
01283 {
01284   return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
01285 }
01286
01287 /**
01288   * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
01289   * @rmtoll CR3          WUS           LL_LPUART_SetWKUPType
01290   * @param  LPUARTx LPUART Instance
01291   * @param  Type This parameter can be one of the following values:
01292   *         @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
01293   *         @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
01294   *         @arg @ref LL_LPUART_WAKEUP_ON_RXNE
01295   * @retval None
01296   */
01297 __STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type)
01298 {
01299   MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type);
01300 }
01301
01302 /**
01303   * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
01304   * @rmtoll CR3          WUS           LL_LPUART_GetWKUPType
01305   * @param  LPUARTx LPUART Instance
01306   * @retval Returned value can be one of the following values:
01307   *         @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
01308   *         @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
01309   *         @arg @ref LL_LPUART_WAKEUP_ON_RXNE
01310   */
01311 __STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx)
01312 {
01313   return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS));
01314 }
01315
01316 /**
01317   * @brief  Configure LPUART BRR register for achieving expected Baud Rate value.
01318   *
01319   * @note   Compute and set LPUARTDIV value in BRR Register (full BRR content)
01320   *         according to used Peripheral Clock and expected Baud Rate values
01321   * @note   Peripheral clock and Baud Rate values provided as function parameters should be valid
01322   *         (Baud rate value != 0).
01323   * @note   Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit,
01324   *         a care should be taken when generating high baud rates using high PeriphClk
01325   *         values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].
01326   * @rmtoll BRR          BRR           LL_LPUART_SetBaudRate
01327   * @param  LPUARTx LPUART Instance
01328   * @param  PeriphClk Peripheral Clock
01329   * @param  PrescalerValue This parameter can be one of the following values:
01330   *         @arg @ref LL_LPUART_PRESCALER_DIV1
01331   *         @arg @ref LL_LPUART_PRESCALER_DIV2
01332   *         @arg @ref LL_LPUART_PRESCALER_DIV4
01333   *         @arg @ref LL_LPUART_PRESCALER_DIV6
01334   *         @arg @ref LL_LPUART_PRESCALER_DIV8
01335   *         @arg @ref LL_LPUART_PRESCALER_DIV10
01336   *         @arg @ref LL_LPUART_PRESCALER_DIV12
01337   *         @arg @ref LL_LPUART_PRESCALER_DIV16
01338   *         @arg @ref LL_LPUART_PRESCALER_DIV32
01339   *         @arg @ref LL_LPUART_PRESCALER_DIV64
01340   *         @arg @ref LL_LPUART_PRESCALER_DIV128
01341   *         @arg @ref LL_LPUART_PRESCALER_DIV256
01342   * @param  BaudRate Baud Rate
01343   * @retval None
01344   */
01345 __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
01346                                            uint32_t BaudRate)
01347 {
01348   LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate);
01349 }
01350
01351 /**
01352   * @brief  Return current Baud Rate value, according to LPUARTDIV present in BRR register
01353   *         (full BRR content), and to used Peripheral Clock values
01354   * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
01355   * @rmtoll BRR          BRR           LL_LPUART_GetBaudRate
01356   * @param  LPUARTx LPUART Instance
01357   * @param  PeriphClk Peripheral Clock
01358   * @param  PrescalerValue This parameter can be one of the following values:
01359   *         @arg @ref LL_LPUART_PRESCALER_DIV1
01360   *         @arg @ref LL_LPUART_PRESCALER_DIV2
01361   *         @arg @ref LL_LPUART_PRESCALER_DIV4
01362   *         @arg @ref LL_LPUART_PRESCALER_DIV6
01363   *         @arg @ref LL_LPUART_PRESCALER_DIV8
01364   *         @arg @ref LL_LPUART_PRESCALER_DIV10
01365   *         @arg @ref LL_LPUART_PRESCALER_DIV12
01366   *         @arg @ref LL_LPUART_PRESCALER_DIV16
01367   *         @arg @ref LL_LPUART_PRESCALER_DIV32
01368   *         @arg @ref LL_LPUART_PRESCALER_DIV64
01369   *         @arg @ref LL_LPUART_PRESCALER_DIV128
01370   *         @arg @ref LL_LPUART_PRESCALER_DIV256
01371   * @retval Baud Rate
01372   */
01373 __STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue)
01374 {
01375   register uint32_t lpuartdiv;
01376   register uint32_t brrresult;
01377   register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue]));
01378
01379   lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;
01380
01381   if (lpuartdiv >= LPUART_BRR_MIN_VALUE)
01382   {
01383     brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);
01384   }
01385   else
01386   {
01387     brrresult = 0x0UL;
01388   }
01389
01390   return (brrresult);
01391 }
01392
01393 /**
01394   * @}
01395   */
01396
01397 /** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
01398   * @{
01399   */
01400
01401 /**
01402   * @brief  Enable Single Wire Half-Duplex mode
01403   * @rmtoll CR3          HDSEL         LL_LPUART_EnableHalfDuplex
01404   * @param  LPUARTx LPUART Instance
01405   * @retval None
01406   */
01407 __STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx)
01408 {
01409   SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
01410 }
01411
01412 /**
01413   * @brief  Disable Single Wire Half-Duplex mode
01414   * @rmtoll CR3          HDSEL         LL_LPUART_DisableHalfDuplex
01415   * @param  LPUARTx LPUART Instance
01416   * @retval None
01417   */
01418 __STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx)
01419 {
01420   CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
01421 }
01422
01423 /**
01424   * @brief  Indicate if Single Wire Half-Duplex mode is enabled
01425   * @rmtoll CR3          HDSEL         LL_LPUART_IsEnabledHalfDuplex
01426   * @param  LPUARTx LPUART Instance
01427   * @retval State of bit (1 or 0).
01428   */
01429 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(USART_TypeDef *LPUARTx)
01430 {
01431   return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
01432 }
01433
01434 /**
01435   * @}
01436   */
01437
01438 /** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
01439   * @{
01440   */
01441
01442 /**
01443   * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
01444   * @rmtoll CR1          DEDT          LL_LPUART_SetDEDeassertionTime
01445   * @param  LPUARTx LPUART Instance
01446   * @param  Time Value between Min_Data=0 and Max_Data=31
01447   * @retval None
01448   */
01449 __STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
01450 {
01451   MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
01452 }
01453
01454 /**
01455   * @brief  Return DEDT (Driver Enable De-Assertion Time)
01456   * @rmtoll CR1          DEDT          LL_LPUART_GetDEDeassertionTime
01457   * @param  LPUARTx LPUART Instance
01458   * @retval Time value expressed on 5 bits ([4:0] bits) : c
01459   */
01460 __STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(USART_TypeDef *LPUARTx)
01461 {
01462   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
01463 }
01464
01465 /**
01466   * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
01467   * @rmtoll CR1          DEAT          LL_LPUART_SetDEAssertionTime
01468   * @param  LPUARTx LPUART Instance
01469   * @param  Time Value between Min_Data=0 and Max_Data=31
01470   * @retval None
01471   */
01472 __STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
01473 {
01474   MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
01475 }
01476
01477 /**
01478   * @brief  Return DEAT (Driver Enable Assertion Time)
01479   * @rmtoll CR1          DEAT          LL_LPUART_GetDEAssertionTime
01480   * @param  LPUARTx LPUART Instance
01481   * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31
01482   */
01483 __STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(USART_TypeDef *LPUARTx)
01484 {
01485   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
01486 }
01487
01488 /**
01489   * @brief  Enable Driver Enable (DE) Mode
01490   * @rmtoll CR3          DEM           LL_LPUART_EnableDEMode
01491   * @param  LPUARTx LPUART Instance
01492   * @retval None
01493   */
01494 __STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx)
01495 {
01496   SET_BIT(LPUARTx->CR3, USART_CR3_DEM);
01497 }
01498
01499 /**
01500   * @brief  Disable Driver Enable (DE) Mode
01501   * @rmtoll CR3          DEM           LL_LPUART_DisableDEMode
01502   * @param  LPUARTx LPUART Instance
01503   * @retval None
01504   */
01505 __STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx)
01506 {
01507   CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM);
01508 }
01509
01510 /**
01511   * @brief  Indicate if Driver Enable (DE) Mode is enabled
01512   * @rmtoll CR3          DEM           LL_LPUART_IsEnabledDEMode
01513   * @param  LPUARTx LPUART Instance
01514   * @retval State of bit (1 or 0).
01515   */
01516 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(USART_TypeDef *LPUARTx)
01517 {
01518   return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
01519 }
01520
01521 /**
01522   * @brief  Select Driver Enable Polarity
01523   * @rmtoll CR3          DEP           LL_LPUART_SetDESignalPolarity
01524   * @param  LPUARTx LPUART Instance
01525   * @param  Polarity This parameter can be one of the following values:
01526   *         @arg @ref LL_LPUART_DE_POLARITY_HIGH
01527   *         @arg @ref LL_LPUART_DE_POLARITY_LOW
01528   * @retval None
01529   */
01530 __STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
01531 {
01532   MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);
01533 }
01534
01535 /**
01536   * @brief  Return Driver Enable Polarity
01537   * @rmtoll CR3          DEP           LL_LPUART_GetDESignalPolarity
01538   * @param  LPUARTx LPUART Instance
01539   * @retval Returned value can be one of the following values:
01540   *         @arg @ref LL_LPUART_DE_POLARITY_HIGH
01541   *         @arg @ref LL_LPUART_DE_POLARITY_LOW
01542   */
01543 __STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(USART_TypeDef *LPUARTx)
01544 {
01545   return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));
01546 }
01547
01548 /**
01549   * @}
01550   */
01551
01552 /** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management
01553   * @{
01554   */
01555
01556 /**
01557   * @brief  Check if the LPUART Parity Error Flag is set or not
01558   * @rmtoll ISR          PE            LL_LPUART_IsActiveFlag_PE
01559   * @param  LPUARTx LPUART Instance
01560   * @retval State of bit (1 or 0).
01561   */
01562 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(USART_TypeDef *LPUARTx)
01563 {
01564   return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
01565 }
01566
01567 /**
01568   * @brief  Check if the LPUART Framing Error Flag is set or not
01569   * @rmtoll ISR          FE            LL_LPUART_IsActiveFlag_FE
01570   * @param  LPUARTx LPUART Instance
01571   * @retval State of bit (1 or 0).
01572   */
01573 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(USART_TypeDef *LPUARTx)
01574 {
01575   return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
01576 }
01577
01578 /**
01579   * @brief  Check if the LPUART Noise error detected Flag is set or not
01580   * @rmtoll ISR          NE            LL_LPUART_IsActiveFlag_NE
01581   * @param  LPUARTx LPUART Instance
01582   * @retval State of bit (1 or 0).
01583   */
01584 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(USART_TypeDef *LPUARTx)
01585 {
01586   return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
01587 }
01588
01589 /**
01590   * @brief  Check if the LPUART OverRun Error Flag is set or not
01591   * @rmtoll ISR          ORE           LL_LPUART_IsActiveFlag_ORE
01592   * @param  LPUARTx LPUART Instance
01593   * @retval State of bit (1 or 0).
01594   */
01595 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(USART_TypeDef *LPUARTx)
01596 {
01597   return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
01598 }
01599
01600 /**
01601   * @brief  Check if the LPUART IDLE line detected Flag is set or not
01602   * @rmtoll ISR          IDLE          LL_LPUART_IsActiveFlag_IDLE
01603   * @param  LPUARTx LPUART Instance
01604   * @retval State of bit (1 or 0).
01605   */
01606 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx)
01607 {
01608   return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
01609 }
01610
01611 /* Legacy define */
01612 #define LL_LPUART_IsActiveFlag_RXNE  LL_LPUART_IsActiveFlag_RXNE_RXFNE
01613
01614 /**
01615   * @brief  Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not
01616   * @rmtoll ISR          RXNE_RXFNE    LL_LPUART_IsActiveFlag_RXNE_RXFNE
01617   * @param  LPUARTx LPUART Instance
01618   * @retval State of bit (1 or 0).
01619   */
01620 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *LPUARTx)
01621 {
01622   return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
01623 }
01624
01625 /**
01626   * @brief  Check if the LPUART Transmission Complete Flag is set or not
01627   * @rmtoll ISR          TC            LL_LPUART_IsActiveFlag_TC
01628   * @param  LPUARTx LPUART Instance
01629   * @retval State of bit (1 or 0).
01630   */
01631 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx)
01632 {
01633   return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
01634 }
01635
01636 /* Legacy define */
01637 #define LL_LPUART_IsActiveFlag_TXE  LL_LPUART_IsActiveFlag_TXE_TXFNF
01638
01639 /**
01640   * @brief  Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not
01641   * @rmtoll ISR          TXE_TXFNF     LL_LPUART_IsActiveFlag_TXE_TXFNF
01642   * @param  LPUARTx LPUART Instance
01643   * @retval State of bit (1 or 0).
01644   */
01645 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *LPUARTx)
01646 {
01647   return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
01648 }
01649
01650 /**
01651   * @brief  Check if the LPUART CTS interrupt Flag is set or not
01652   * @rmtoll ISR          CTSIF         LL_LPUART_IsActiveFlag_nCTS
01653   * @param  LPUARTx LPUART Instance
01654   * @retval State of bit (1 or 0).
01655   */
01656 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef *LPUARTx)
01657 {
01658   return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
01659 }
01660
01661 /**
01662   * @brief  Check if the LPUART CTS Flag is set or not
01663   * @rmtoll ISR          CTS           LL_LPUART_IsActiveFlag_CTS
01664   * @param  LPUARTx LPUART Instance
01665   * @retval State of bit (1 or 0).
01666   */
01667 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(USART_TypeDef *LPUARTx)
01668 {
01669   return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
01670 }
01671
01672 /**
01673   * @brief  Check if the LPUART Busy Flag is set or not
01674   * @rmtoll ISR          BUSY          LL_LPUART_IsActiveFlag_BUSY
01675   * @param  LPUARTx LPUART Instance
01676   * @retval State of bit (1 or 0).
01677   */
01678 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef *LPUARTx)
01679 {
01680   return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
01681 }
01682
01683 /**
01684   * @brief  Check if the LPUART Character Match Flag is set or not
01685   * @rmtoll ISR          CMF           LL_LPUART_IsActiveFlag_CM
01686   * @param  LPUARTx LPUART Instance
01687   * @retval State of bit (1 or 0).
01688   */
01689 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(USART_TypeDef *LPUARTx)
01690 {
01691   return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
01692 }
01693
01694 /**
01695   * @brief  Check if the LPUART Send Break Flag is set or not
01696   * @rmtoll ISR          SBKF          LL_LPUART_IsActiveFlag_SBK
01697   * @param  LPUARTx LPUART Instance
01698   * @retval State of bit (1 or 0).
01699   */
01700 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(USART_TypeDef *LPUARTx)
01701 {
01702   return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
01703 }
01704
01705 /**
01706   * @brief  Check if the LPUART Receive Wake Up from mute mode Flag is set or not
01707   * @rmtoll ISR          RWU           LL_LPUART_IsActiveFlag_RWU
01708   * @param  LPUARTx LPUART Instance
01709   * @retval State of bit (1 or 0).
01710   */
01711 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(USART_TypeDef *LPUARTx)
01712 {
01713   return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
01714 }
01715
01716 /**
01717   * @brief  Check if the LPUART Wake Up from stop mode Flag is set or not
01718   * @rmtoll ISR          WUF           LL_LPUART_IsActiveFlag_WKUP
01719   * @param  LPUARTx LPUART Instance
01720   * @retval State of bit (1 or 0).
01721   */
01722 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(USART_TypeDef *LPUARTx)
01723 {
01724   return ((READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
01725 }
01726
01727 /**
01728   * @brief  Check if the LPUART Transmit Enable Acknowledge Flag is set or not
01729   * @rmtoll ISR          TEACK         LL_LPUART_IsActiveFlag_TEACK
01730   * @param  LPUARTx LPUART Instance
01731   * @retval State of bit (1 or 0).
01732   */
01733 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef *LPUARTx)
01734 {
01735   return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
01736 }
01737
01738 /**
01739   * @brief  Check if the LPUART Receive Enable Acknowledge Flag is set or not
01740   * @rmtoll ISR          REACK         LL_LPUART_IsActiveFlag_REACK
01741   * @param  LPUARTx LPUART Instance
01742   * @retval State of bit (1 or 0).
01743   */
01744 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx)
01745 {
01746   return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
01747 }
01748
01749 /**
01750   * @brief  Check if the LPUART TX FIFO Empty Flag is set or not
01751   * @rmtoll ISR          TXFE          LL_LPUART_IsActiveFlag_TXFE
01752   * @param  LPUARTx LPUART Instance
01753   * @retval State of bit (1 or 0).
01754   */
01755 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(USART_TypeDef *LPUARTx)
01756 {
01757   return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
01758 }
01759
01760 /**
01761   * @brief  Check if the LPUART RX FIFO Full Flag is set or not
01762   * @rmtoll ISR          RXFF          LL_LPUART_IsActiveFlag_RXFF
01763   * @param  LPUARTx LPUART Instance
01764   * @retval State of bit (1 or 0).
01765   */
01766 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(USART_TypeDef *LPUARTx)
01767 {
01768   return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
01769 }
01770
01771 /**
01772   * @brief  Check if the LPUART TX FIFO Threshold Flag is set or not
01773   * @rmtoll ISR          TXFT          LL_LPUART_IsActiveFlag_TXFT
01774   * @param  LPUARTx LPUART Instance
01775   * @retval State of bit (1 or 0).
01776   */
01777 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(USART_TypeDef *LPUARTx)
01778 {
01779   return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
01780 }
01781
01782 /**
01783   * @brief  Check if the LPUART RX FIFO Threshold Flag is set or not
01784   * @rmtoll ISR          RXFT          LL_LPUART_IsActiveFlag_RXFT
01785   * @param  LPUARTx LPUART Instance
01786   * @retval State of bit (1 or 0).
01787   */
01788 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(USART_TypeDef *LPUARTx)
01789 {
01790   return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
01791 }
01792
01793 /**
01794   * @brief  Clear Parity Error Flag
01795   * @rmtoll ICR          PECF          LL_LPUART_ClearFlag_PE
01796   * @param  LPUARTx LPUART Instance
01797   * @retval None
01798   */
01799 __STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx)
01800 {
01801   WRITE_REG(LPUARTx->ICR, USART_ICR_PECF);
01802 }
01803
01804 /**
01805   * @brief  Clear Framing Error Flag
01806   * @rmtoll ICR          FECF          LL_LPUART_ClearFlag_FE
01807   * @param  LPUARTx LPUART Instance
01808   * @retval None
01809   */
01810 __STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx)
01811 {
01812   WRITE_REG(LPUARTx->ICR, USART_ICR_FECF);
01813 }
01814
01815 /**
01816   * @brief  Clear Noise detected Flag
01817   * @rmtoll ICR          NECF          LL_LPUART_ClearFlag_NE
01818   * @param  LPUARTx LPUART Instance
01819   * @retval None
01820   */
01821 __STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx)
01822 {
01823   WRITE_REG(LPUARTx->ICR, USART_ICR_NECF);
01824 }
01825
01826 /**
01827   * @brief  Clear OverRun Error Flag
01828   * @rmtoll ICR          ORECF         LL_LPUART_ClearFlag_ORE
01829   * @param  LPUARTx LPUART Instance
01830   * @retval None
01831   */
01832 __STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx)
01833 {
01834   WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF);
01835 }
01836
01837 /**
01838   * @brief  Clear IDLE line detected Flag
01839   * @rmtoll ICR          IDLECF        LL_LPUART_ClearFlag_IDLE
01840   * @param  LPUARTx LPUART Instance
01841   * @retval None
01842   */
01843 __STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx)
01844 {
01845   WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);
01846 }
01847
01848 /**
01849   * @brief  Clear TX FIFO Empty Flag
01850   * @rmtoll ICR          TXFECF        LL_LPUART_ClearFlag_TXFE
01851   * @param  LPUARTx LPUART Instance
01852   * @retval None
01853   */
01854 __STATIC_INLINE void LL_LPUART_ClearFlag_TXFE(USART_TypeDef *LPUARTx)
01855 {
01856   WRITE_REG(LPUARTx->ICR, USART_ICR_TXFECF);
01857 }
01858
01859 /**
01860   * @brief  Clear Transmission Complete Flag
01861   * @rmtoll ICR          TCCF          LL_LPUART_ClearFlag_TC
01862   * @param  LPUARTx LPUART Instance
01863   * @retval None
01864   */
01865 __STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx)
01866 {
01867   WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF);
01868 }
01869
01870 /**
01871   * @brief  Clear CTS Interrupt Flag
01872   * @rmtoll ICR          CTSCF         LL_LPUART_ClearFlag_nCTS
01873   * @param  LPUARTx LPUART Instance
01874   * @retval None
01875   */
01876 __STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx)
01877 {
01878   WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF);
01879 }
01880
01881 /**
01882   * @brief  Clear Character Match Flag
01883   * @rmtoll ICR          CMCF          LL_LPUART_ClearFlag_CM
01884   * @param  LPUARTx LPUART Instance
01885   * @retval None
01886   */
01887 __STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx)
01888 {
01889   WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF);
01890 }
01891
01892 /**
01893   * @brief  Clear Wake Up from stop mode Flag
01894   * @rmtoll ICR          WUCF          LL_LPUART_ClearFlag_WKUP
01895   * @param  LPUARTx LPUART Instance
01896   * @retval None
01897   */
01898 __STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx)
01899 {
01900   WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF);
01901 }
01902
01903 /**
01904   * @}
01905   */
01906
01907 /** @defgroup LPUART_LL_EF_IT_Management IT_Management
01908   * @{
01909   */
01910
01911 /**
01912   * @brief  Enable IDLE Interrupt
01913   * @rmtoll CR1          IDLEIE        LL_LPUART_EnableIT_IDLE
01914   * @param  LPUARTx LPUART Instance
01915   * @retval None
01916   */
01917 __STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
01918 {
01919   SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
01920 }
01921
01922 /* Legacy define */
01923 #define LL_LPUART_EnableIT_RXNE  LL_LPUART_EnableIT_RXNE_RXFNE
01924
01925 /**
01926   * @brief  Enable RX Not Empty and RX FIFO Not Empty Interrupt
01927   * @rmtoll CR1        RXNEIE_RXFNEIE  LL_LPUART_EnableIT_RXNE_RXFNE
01928   * @param  LPUARTx LPUART Instance
01929   * @retval None
01930   */
01931 __STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
01932 {
01933   SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
01934 }
01935
01936 /**
01937   * @brief  Enable Transmission Complete Interrupt
01938   * @rmtoll CR1          TCIE          LL_LPUART_EnableIT_TC
01939   * @param  LPUARTx LPUART Instance
01940   * @retval None
01941   */
01942 __STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
01943 {
01944   SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
01945 }
01946
01947 /* Legacy define */
01948 #define LL_LPUART_EnableIT_TXE  LL_LPUART_EnableIT_TXE_TXFNF
01949
01950 /**
01951   * @brief  Enable TX Empty and TX FIFO Not Full Interrupt
01952   * @rmtoll CR1         TXEIE_TXFNFIE  LL_LPUART_EnableIT_TXE_TXFNF
01953   * @param  LPUARTx LPUART Instance
01954   * @retval None
01955   */
01956 __STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
01957 {
01958   SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
01959 }
01960
01961 /**
01962   * @brief  Enable Parity Error Interrupt
01963   * @rmtoll CR1          PEIE          LL_LPUART_EnableIT_PE
01964   * @param  LPUARTx LPUART Instance
01965   * @retval None
01966   */
01967 __STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)
01968 {
01969   SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
01970 }
01971
01972 /**
01973   * @brief  Enable Character Match Interrupt
01974   * @rmtoll CR1          CMIE          LL_LPUART_EnableIT_CM
01975   * @param  LPUARTx LPUART Instance
01976   * @retval None
01977   */
01978 __STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)
01979 {
01980   SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
01981 }
01982
01983 /**
01984   * @brief  Enable TX FIFO Empty Interrupt
01985   * @rmtoll CR1          TXFEIE        LL_LPUART_EnableIT_TXFE
01986   * @param  LPUARTx LPUART Instance
01987   * @retval None
01988   */
01989 __STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx)
01990 {
01991   SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
01992 }
01993
01994 /**
01995   * @brief  Enable RX FIFO Full Interrupt
01996   * @rmtoll CR1          RXFFIE        LL_LPUART_EnableIT_RXFF
01997   * @param  LPUARTx LPUART Instance
01998   * @retval None
01999   */
02000 __STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx)
02001 {
02002   SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
02003 }
02004
02005 /**
02006   * @brief  Enable Error Interrupt
02007   * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
02008   *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
02009   *         - 0: Interrupt is inhibited
02010   *         - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
02011   * @rmtoll CR3          EIE           LL_LPUART_EnableIT_ERROR
02012   * @param  LPUARTx LPUART Instance
02013   * @retval None
02014   */
02015 __STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)
02016 {
02017   SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
02018 }
02019
02020 /**
02021   * @brief  Enable CTS Interrupt
02022   * @rmtoll CR3          CTSIE         LL_LPUART_EnableIT_CTS
02023   * @param  LPUARTx LPUART Instance
02024   * @retval None
02025   */
02026 __STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)
02027 {
02028   SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
02029 }
02030
02031 /**
02032   * @brief  Enable Wake Up from Stop Mode Interrupt
02033   * @rmtoll CR3          WUFIE         LL_LPUART_EnableIT_WKUP
02034   * @param  LPUARTx LPUART Instance
02035   * @retval None
02036   */
02037 __STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx)
02038 {
02039   SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
02040 }
02041
02042 /**
02043   * @brief  Enable TX FIFO Threshold Interrupt
02044   * @rmtoll CR3          TXFTIE        LL_LPUART_EnableIT_TXFT
02045   * @param  LPUARTx LPUART Instance
02046   * @retval None
02047   */
02048 __STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx)
02049 {
02050   SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
02051 }
02052
02053 /**
02054   * @brief  Enable RX FIFO Threshold Interrupt
02055   * @rmtoll CR3          RXFTIE        LL_LPUART_EnableIT_RXFT
02056   * @param  LPUARTx LPUART Instance
02057   * @retval None
02058   */
02059 __STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx)
02060 {
02061   SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
02062 }
02063
02064 /**
02065   * @brief  Disable IDLE Interrupt
02066   * @rmtoll CR1          IDLEIE        LL_LPUART_DisableIT_IDLE
02067   * @param  LPUARTx LPUART Instance
02068   * @retval None
02069   */
02070 __STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
02071 {
02072   CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
02073 }
02074
02075 /* Legacy define */
02076 #define LL_LPUART_DisableIT_RXNE  LL_LPUART_DisableIT_RXNE_RXFNE
02077
02078 /**
02079   * @brief  Disable RX Not Empty and RX FIFO Not Empty Interrupt
02080   * @rmtoll CR1        RXNEIE_RXFNEIE  LL_LPUART_DisableIT_RXNE_RXFNE
02081   * @param  LPUARTx LPUART Instance
02082   * @retval None
02083   */
02084 __STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
02085 {
02086   CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
02087 }
02088
02089 /**
02090   * @brief  Disable Transmission Complete Interrupt
02091   * @rmtoll CR1          TCIE          LL_LPUART_DisableIT_TC
02092   * @param  LPUARTx LPUART Instance
02093   * @retval None
02094   */
02095 __STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
02096 {
02097   CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
02098 }
02099
02100 /* Legacy define */
02101 #define LL_LPUART_DisableIT_TXE  LL_LPUART_DisableIT_TXE_TXFNF
02102
02103 /**
02104   * @brief  Disable TX Empty and TX FIFO Not Full Interrupt
02105   * @rmtoll CR1        TXEIE_TXFNFIE  LL_LPUART_DisableIT_TXE_TXFNF
02106   * @param  LPUARTx LPUART Instance
02107   * @retval None
02108   */
02109 __STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
02110 {
02111   CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
02112 }
02113
02114 /**
02115   * @brief  Disable Parity Error Interrupt
02116   * @rmtoll CR1          PEIE          LL_LPUART_DisableIT_PE
02117   * @param  LPUARTx LPUART Instance
02118   * @retval None
02119   */
02120 __STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)
02121 {
02122   CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
02123 }
02124
02125 /**
02126   * @brief  Disable Character Match Interrupt
02127   * @rmtoll CR1          CMIE          LL_LPUART_DisableIT_CM
02128   * @param  LPUARTx LPUART Instance
02129   * @retval None
02130   */
02131 __STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)
02132 {
02133   CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
02134 }
02135
02136 /**
02137   * @brief  Disable TX FIFO Empty Interrupt
02138   * @rmtoll CR1          TXFEIE        LL_LPUART_DisableIT_TXFE
02139   * @param  LPUARTx LPUART Instance
02140   * @retval None
02141   */
02142 __STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx)
02143 {
02144   CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
02145 }
02146
02147 /**
02148   * @brief  Disable RX FIFO Full Interrupt
02149   * @rmtoll CR1          RXFFIE        LL_LPUART_DisableIT_RXFF
02150   * @param  LPUARTx LPUART Instance
02151   * @retval None
02152   */
02153 __STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx)
02154 {
02155   CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
02156 }
02157
02158 /**
02159   * @brief  Disable Error Interrupt
02160   * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
02161   *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
02162   *         - 0: Interrupt is inhibited
02163   *         - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
02164   * @rmtoll CR3          EIE           LL_LPUART_DisableIT_ERROR
02165   * @param  LPUARTx LPUART Instance
02166   * @retval None
02167   */
02168 __STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)
02169 {
02170   CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
02171 }
02172
02173 /**
02174   * @brief  Disable CTS Interrupt
02175   * @rmtoll CR3          CTSIE         LL_LPUART_DisableIT_CTS
02176   * @param  LPUARTx LPUART Instance
02177   * @retval None
02178   */
02179 __STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)
02180 {
02181   CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
02182 }
02183
02184 /**
02185   * @brief  Disable Wake Up from Stop Mode Interrupt
02186   * @rmtoll CR3          WUFIE         LL_LPUART_DisableIT_WKUP
02187   * @param  LPUARTx LPUART Instance
02188   * @retval None
02189   */
02190 __STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx)
02191 {
02192   CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
02193 }
02194
02195 /**
02196   * @brief  Disable TX FIFO Threshold Interrupt
02197   * @rmtoll CR3          TXFTIE        LL_LPUART_DisableIT_TXFT
02198   * @param  LPUARTx LPUART Instance
02199   * @retval None
02200   */
02201 __STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx)
02202 {
02203   CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
02204 }
02205
02206 /**
02207   * @brief  Disable RX FIFO Threshold Interrupt
02208   * @rmtoll CR3          RXFTIE        LL_LPUART_DisableIT_RXFT
02209   * @param  LPUARTx LPUART Instance
02210   * @retval None
02211   */
02212 __STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx)
02213 {
02214   CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
02215 }
02216
02217 /**
02218   * @brief  Check if the LPUART IDLE Interrupt  source is enabled or disabled.
02219   * @rmtoll CR1          IDLEIE        LL_LPUART_IsEnabledIT_IDLE
02220   * @param  LPUARTx LPUART Instance
02221   * @retval State of bit (1 or 0).
02222   */
02223 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx)
02224 {
02225   return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
02226 }
02227
02228 /* Legacy define */
02229 #define LL_LPUART_IsEnabledIT_RXNE  LL_LPUART_IsEnabledIT_RXNE_RXFNE
02230
02231 /**
02232   * @brief  Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.
02233   * @rmtoll CR1        RXNEIE_RXFNEIE  LL_LPUART_IsEnabledIT_RXNE_RXFNE
02234   * @param  LPUARTx LPUART Instance
02235   * @retval State of bit (1 or 0).
02236   */
02237 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
02238 {
02239   return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
02240 }
02241
02242 /**
02243   * @brief  Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
02244   * @rmtoll CR1          TCIE          LL_LPUART_IsEnabledIT_TC
02245   * @param  LPUARTx LPUART Instance
02246   * @retval State of bit (1 or 0).
02247   */
02248 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx)
02249 {
02250   return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
02251 }
02252
02253 /* Legacy define */
02254 #define LL_LPUART_IsEnabledIT_TXE  LL_LPUART_IsEnabledIT_TXE_TXFNF
02255
02256 /**
02257   * @brief  Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled
02258   * @rmtoll CR1         TXEIE_TXFNFIE  LL_LPUART_IsEnabledIT_TXE_TXFNF
02259   * @param  LPUARTx LPUART Instance
02260   * @retval State of bit (1 or 0).
02261   */
02262 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
02263 {
02264   return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
02265 }
02266
02267 /**
02268   * @brief  Check if the LPUART Parity Error Interrupt is enabled or disabled.
02269   * @rmtoll CR1          PEIE          LL_LPUART_IsEnabledIT_PE
02270   * @param  LPUARTx LPUART Instance
02271   * @retval State of bit (1 or 0).
02272   */
02273 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(USART_TypeDef *LPUARTx)
02274 {
02275   return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
02276 }
02277
02278 /**
02279   * @brief  Check if the LPUART Character Match Interrupt is enabled or disabled.
02280   * @rmtoll CR1          CMIE          LL_LPUART_IsEnabledIT_CM
02281   * @param  LPUARTx LPUART Instance
02282   * @retval State of bit (1 or 0).
02283   */
02284 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx)
02285 {
02286   return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
02287 }
02288
02289 /**
02290   * @brief  Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled
02291   * @rmtoll CR1          TXFEIE        LL_LPUART_IsEnabledIT_TXFE
02292   * @param  LPUARTx LPUART Instance
02293   * @retval State of bit (1 or 0).
02294   */
02295 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(USART_TypeDef *LPUARTx)
02296 {
02297   return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
02298 }
02299
02300 /**
02301   * @brief  Check if the LPUART RX FIFO Full Interrupt is enabled or disabled
02302   * @rmtoll CR1          RXFFIE        LL_LPUART_IsEnabledIT_RXFF
02303   * @param  LPUARTx LPUART Instance
02304   * @retval State of bit (1 or 0).
02305   */
02306 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(USART_TypeDef *LPUARTx)
02307 {
02308   return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
02309 }
02310
02311 /**
02312   * @brief  Check if the LPUART Error Interrupt is enabled or disabled.
02313   * @rmtoll CR3          EIE           LL_LPUART_IsEnabledIT_ERROR
02314   * @param  LPUARTx LPUART Instance
02315   * @retval State of bit (1 or 0).
02316   */
02317 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef *LPUARTx)
02318 {
02319   return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
02320 }
02321
02322 /**
02323   * @brief  Check if the LPUART CTS Interrupt is enabled or disabled.
02324   * @rmtoll CR3          CTSIE         LL_LPUART_IsEnabledIT_CTS
02325   * @param  LPUARTx LPUART Instance
02326   * @retval State of bit (1 or 0).
02327   */
02328 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(USART_TypeDef *LPUARTx)
02329 {
02330   return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
02331 }
02332
02333 /**
02334   * @brief  Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.
02335   * @rmtoll CR3          WUFIE         LL_LPUART_IsEnabledIT_WKUP
02336   * @param  LPUARTx LPUART Instance
02337   * @retval State of bit (1 or 0).
02338   */
02339 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef *LPUARTx)
02340 {
02341   return ((READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
02342 }
02343
02344 /**
02345   * @brief  Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled
02346   * @rmtoll CR3          TXFTIE        LL_LPUART_IsEnabledIT_TXFT
02347   * @param  LPUARTx LPUART Instance
02348   * @retval State of bit (1 or 0).
02349   */
02350 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(USART_TypeDef *LPUARTx)
02351 {
02352   return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
02353 }
02354
02355 /**
02356   * @brief  Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled
02357   * @rmtoll CR3          RXFTIE        LL_LPUART_IsEnabledIT_RXFT
02358   * @param  LPUARTx LPUART Instance
02359   * @retval State of bit (1 or 0).
02360   */
02361 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(USART_TypeDef *LPUARTx)
02362 {
02363   return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
02364 }
02365
02366 /**
02367   * @}
02368   */
02369
02370 /** @defgroup LPUART_LL_EF_DMA_Management DMA_Management
02371   * @{
02372   */
02373
02374 /**
02375   * @brief  Enable DMA Mode for reception
02376   * @rmtoll CR3          DMAR          LL_LPUART_EnableDMAReq_RX
02377   * @param  LPUARTx LPUART Instance
02378   * @retval None
02379   */
02380 __STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)
02381 {
02382   SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
02383 }
02384
02385 /**
02386   * @brief  Disable DMA Mode for reception
02387   * @rmtoll CR3          DMAR          LL_LPUART_DisableDMAReq_RX
02388   * @param  LPUARTx LPUART Instance
02389   * @retval None
02390   */
02391 __STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)
02392 {
02393   CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
02394 }
02395
02396 /**
02397   * @brief  Check if DMA Mode is enabled for reception
02398   * @rmtoll CR3          DMAR          LL_LPUART_IsEnabledDMAReq_RX
02399   * @param  LPUARTx LPUART Instance
02400   * @retval State of bit (1 or 0).
02401   */
02402 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(USART_TypeDef *LPUARTx)
02403 {
02404   return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
02405 }
02406
02407 /**
02408   * @brief  Enable DMA Mode for transmission
02409   * @rmtoll CR3          DMAT          LL_LPUART_EnableDMAReq_TX
02410   * @param  LPUARTx LPUART Instance
02411   * @retval None
02412   */
02413 __STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)
02414 {
02415   SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
02416 }
02417
02418 /**
02419   * @brief  Disable DMA Mode for transmission
02420   * @rmtoll CR3          DMAT          LL_LPUART_DisableDMAReq_TX
02421   * @param  LPUARTx LPUART Instance
02422   * @retval None
02423   */
02424 __STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)
02425 {
02426   CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
02427 }
02428
02429 /**
02430   * @brief  Check if DMA Mode is enabled for transmission
02431   * @rmtoll CR3          DMAT          LL_LPUART_IsEnabledDMAReq_TX
02432   * @param  LPUARTx LPUART Instance
02433   * @retval State of bit (1 or 0).
02434   */
02435 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(USART_TypeDef *LPUARTx)
02436 {
02437   return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
02438 }
02439
02440 /**
02441   * @brief  Enable DMA Disabling on Reception Error
02442   * @rmtoll CR3          DDRE          LL_LPUART_EnableDMADeactOnRxErr
02443   * @param  LPUARTx LPUART Instance
02444   * @retval None
02445   */
02446 __STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
02447 {
02448   SET_BIT(LPUARTx->CR3, USART_CR3_DDRE);
02449 }
02450
02451 /**
02452   * @brief  Disable DMA Disabling on Reception Error
02453   * @rmtoll CR3          DDRE          LL_LPUART_DisableDMADeactOnRxErr
02454   * @param  LPUARTx LPUART Instance
02455   * @retval None
02456   */
02457 __STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
02458 {
02459   CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE);
02460 }
02461
02462 /**
02463   * @brief  Indicate if DMA Disabling on Reception Error is disabled
02464   * @rmtoll CR3          DDRE          LL_LPUART_IsEnabledDMADeactOnRxErr
02465   * @param  LPUARTx LPUART Instance
02466   * @retval State of bit (1 or 0).
02467   */
02468 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUARTx)
02469 {
02470   return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
02471 }
02472
02473 /**
02474   * @brief  Get the LPUART data register address used for DMA transfer
02475   * @rmtoll RDR          RDR           LL_LPUART_DMA_GetRegAddr\n
02476   * @rmtoll TDR          TDR           LL_LPUART_DMA_GetRegAddr
02477   * @param  LPUARTx LPUART Instance
02478   * @param  Direction This parameter can be one of the following values:
02479   *         @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT
02480   *         @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE
02481   * @retval Address of data register
02482   */
02483 __STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32_t Direction)
02484 {
02485   register uint32_t data_reg_addr;
02486
02487   if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT)
02488   {
02489     /* return address of TDR register */
02490     data_reg_addr = (uint32_t) &(LPUARTx->TDR);
02491   }
02492   else
02493   {
02494     /* return address of RDR register */
02495     data_reg_addr = (uint32_t) &(LPUARTx->RDR);
02496   }
02497
02498   return data_reg_addr;
02499 }
02500
02501 /**
02502   * @}
02503   */
02504
02505 /** @defgroup LPUART_LL_EF_Data_Management Data_Management
02506   * @{
02507   */
02508
02509 /**
02510   * @brief  Read Receiver Data register (Receive Data value, 8 bits)
02511   * @rmtoll RDR          RDR           LL_LPUART_ReceiveData8
02512   * @param  LPUARTx LPUART Instance
02513   * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF
02514   */
02515 __STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx)
02516 {
02517   return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU);
02518 }
02519
02520 /**
02521   * @brief  Read Receiver Data register (Receive Data value, 9 bits)
02522   * @rmtoll RDR          RDR           LL_LPUART_ReceiveData9
02523   * @param  LPUARTx LPUART Instance
02524   * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF
02525   */
02526 __STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(USART_TypeDef *LPUARTx)
02527 {
02528   return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
02529 }
02530
02531 /**
02532   * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
02533   * @rmtoll TDR          TDR           LL_LPUART_TransmitData8
02534   * @param  LPUARTx LPUART Instance
02535   * @param  Value between Min_Data=0x00 and Max_Data=0xFF
02536   * @retval None
02537   */
02538 __STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value)
02539 {
02540   LPUARTx->TDR = Value;
02541 }
02542
02543 /**
02544   * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
02545   * @rmtoll TDR          TDR           LL_LPUART_TransmitData9
02546   * @param  LPUARTx LPUART Instance
02547   * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
02548   * @retval None
02549   */
02550 __STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value)
02551 {
02552   LPUARTx->TDR = Value & 0x1FFUL;
02553 }
02554
02555 /**
02556   * @}
02557   */
02558
02559 /** @defgroup LPUART_LL_EF_Execution Execution
02560   * @{
02561   */
02562
02563 /**
02564   * @brief  Request Break sending
02565   * @rmtoll RQR          SBKRQ         LL_LPUART_RequestBreakSending
02566   * @param  LPUARTx LPUART Instance
02567   * @retval None
02568   */
02569 __STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx)
02570 {
02571   SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
02572 }
02573
02574 /**
02575   * @brief  Put LPUART in mute mode and set the RWU flag
02576   * @rmtoll RQR          MMRQ          LL_LPUART_RequestEnterMuteMode
02577   * @param  LPUARTx LPUART Instance
02578   * @retval None
02579   */
02580 __STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx)
02581 {
02582   SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ);
02583 }
02584
02585 /**
02586   * @brief  Request a Receive Data and FIFO flush
02587   * @note   Allows to discard the received data without reading them, and avoid an overrun
02588   *         condition.
02589   * @rmtoll RQR          RXFRQ         LL_LPUART_RequestRxDataFlush
02590   * @param  LPUARTx LPUART Instance
02591   * @retval None
02592   */
02593 __STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx)
02594 {
02595   SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
02596 }
02597
02598 /**
02599   * @}
02600   */
02601
02602 #if defined(USE_FULL_LL_DRIVER)
02603 /** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions
02604   * @{
02605   */
02606 ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx);
02607 ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct);
02608 void        LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);
02609 /**
02610   * @}
02611   */
02612 #endif /* USE_FULL_LL_DRIVER */
02613
02614 /**
02615   * @}
02616   */
02617
02618 /**
02619   * @}
02620   */
02621
02622 #endif /* LPUART1 */
02623
02624 /**
02625   * @}
02626   */
02627
02628 #ifdef __cplusplus
02629 }
02630 #endif
02631
02632 #endif /* STM32WBxx_LL_LPUART_H */
02633
02634 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_pka.c Source File

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stm32wbxx_ll_pka.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_pka.c
00004   * @author  MCD Application Team
00005   * @brief   PKA LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32wbxx_ll_pka.h"
00023 #include "stm32wbxx_ll_bus.h"
00024
00025 #ifdef  USE_FULL_ASSERT
00026 #include "stm32_assert.h"
00027 #else
00028 #define assert_param(expr) ((void)0U)
00029 #endif
00030
00031 /** @addtogroup STM32WBxx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined(PKA)
00036
00037 /** @addtogroup PKA_LL
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /* Private macros ------------------------------------------------------------*/
00045 /** @defgroup PKA_LL_Private_Macros PKA Private Constants
00046   * @{
00047   */
00048 #define IS_LL_PKA_MODE(__VALUE__)     (((__VALUE__) == LL_PKA_MODE_MONTGOMERY_PARAM_MOD_EXP) ||\
00049                                       ((__VALUE__) == LL_PKA_MODE_MONTGOMERY_PARAM)          ||\
00050                                       ((__VALUE__) == LL_PKA_MODE_MODULAR_EXP)               ||\
00051                                       ((__VALUE__) == LL_PKA_MODE_MONTGOMERY_PARAM_ECC)      ||\
00052                                       ((__VALUE__) == LL_PKA_MODE_ECC_KP_PRIMITIVE)          ||\
00053                                       ((__VALUE__) == LL_PKA_MODE_ECDSA_SIGNATURE)           ||\
00054                                       ((__VALUE__) == LL_PKA_MODE_ECDSA_VERIFICATION)        ||\
00055                                       ((__VALUE__) == LL_PKA_MODE_POINT_CHECK)               ||\
00056                                       ((__VALUE__) == LL_PKA_MODE_RSA_CRT_EXP)               ||\
00057                                       ((__VALUE__) == LL_PKA_MODE_MODULAR_INV)               ||\
00058                                       ((__VALUE__) == LL_PKA_MODE_ARITHMETIC_ADD)            ||\
00059                                       ((__VALUE__) == LL_PKA_MODE_ARITHMETIC_SUB)            ||\
00060                                       ((__VALUE__) == LL_PKA_MODE_ARITHMETIC_MUL)            ||\
00061                                       ((__VALUE__) == LL_PKA_MODE_COMPARISON)                ||\
00062                                       ((__VALUE__) == LL_PKA_MODE_MODULAR_REDUC)             ||\
00063                                       ((__VALUE__) == LL_PKA_MODE_MODULAR_ADD)               ||\
00064                                       ((__VALUE__) == LL_PKA_MODE_MODULAR_SUB)               ||\
00065                                       ((__VALUE__) == LL_PKA_MODE_MONTGOMERY_MUL))
00066
00067 /**
00068   * @}
00069   */
00070
00071 /* Private function prototypes -----------------------------------------------*/
00072
00073 /* Exported functions --------------------------------------------------------*/
00074 /** @addtogroup PKA_LL_Exported_Functions
00075   * @{
00076   */
00077
00078 /** @addtogroup PKA_LL_EF_Init
00079   * @{
00080   */
00081
00082 /**
00083   * @brief  De-initialize PKA registers (Registers restored to their default values).
00084   * @param  PKAx PKA Instance.
00085   * @retval ErrorStatus
00086   *          - SUCCESS: PKA registers are de-initialized
00087   *          - ERROR: PKA registers are not de-initialized
00088   */
00089 ErrorStatus LL_PKA_DeInit(PKA_TypeDef *PKAx)
00090 {
00091   ErrorStatus status = SUCCESS;
00092
00093   /* Check the parameters */
00094   assert_param(IS_PKA_ALL_INSTANCE(PKAx));
00095
00096   if (PKAx == PKA)
00097   {
00098     /* Force PKA reset */
00099     LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_PKA);
00100
00101     /* Release PKA reset */
00102     LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_PKA);
00103   }
00104   else
00105   {
00106     status = ERROR;
00107   }
00108
00109   return (status);
00110 }
00111
00112 /**
00113   * @brief  Initialize PKA registers according to the specified parameters in PKA_InitStruct.
00114   * @param  PKAx PKA Instance.
00115   * @param  PKA_InitStruct pointer to a @ref LL_PKA_InitTypeDef structure
00116   *         that contains the configuration information for the specified PKA peripheral.
00117   * @retval ErrorStatus
00118   *          - SUCCESS: PKA registers are initialized according to PKA_InitStruct content
00119   *          - ERROR:   Not applicable
00120   */
00121 ErrorStatus LL_PKA_Init(PKA_TypeDef *PKAx, LL_PKA_InitTypeDef *PKA_InitStruct)
00122 {
00123   assert_param(IS_PKA_ALL_INSTANCE(PKAx));
00124   assert_param(IS_LL_PKA_MODE(PKA_InitStruct->Mode));
00125
00126   LL_PKA_Config(PKAx, PKA_InitStruct->Mode);
00127
00128   return (SUCCESS);
00129 }
00130
00131 /**
00132   * @brief Set each @ref LL_PKA_InitTypeDef field to default value.
00133   * @param PKA_InitStruct pointer to a @ref LL_PKA_InitTypeDef structure
00134   *                       whose fields will be set to default values.
00135   * @retval None
00136   */
00137
00138 void LL_PKA_StructInit(LL_PKA_InitTypeDef *PKA_InitStruct)
00139 {
00140   /* Reset PKA init structure parameters values */
00141   PKA_InitStruct->Mode       = LL_PKA_MODE_MONTGOMERY_PARAM_MOD_EXP;
00142 }
00143
00144 /**
00145   * @}
00146   */
00147
00148 /**
00149   * @}
00150   */
00151
00152 /**
00153   * @}
00154   */
00155
00156 #endif /* defined (PKA) */
00157
00158 /**
00159   * @}
00160   */
00161
00162 #endif /* USE_FULL_LL_DRIVER */
00163
00164 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00165
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_pka.h Source File

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stm32wbxx_ll_pka.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_pka.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of PKA LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_LL_PKA_H
00022 #define STM32WBxx_LL_PKA_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx.h"
00030
00031 /** @addtogroup STM32WBxx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined(PKA)
00036
00037 /** @defgroup PKA_LL PKA
00038   * @{
00039   */
00040
00041 /* Private variables ---------------------------------------------------------*/
00042
00043 /* Exported types ------------------------------------------------------------*/
00044 #if defined(USE_FULL_LL_DRIVER)
00045 /** @defgroup PKA_LL_ES_INIT PKA Exported Init structure
00046   * @{
00047   */
00048
00049 /**
00050   * @brief  PKA Init structures definition
00051   */
00052 typedef struct
00053 {
00054   uint32_t Mode;          /*!< Specifies the PKA operation mode.
00055                                This parameter can be a value of @ref PKA_LL_EC_MODE.
00056
00057                                This feature can be modified afterwards using unitary function @ref LL_PKA_SetMode(). */
00058 } LL_PKA_InitTypeDef;
00059
00060 /**
00061   * @}
00062   */
00063 #endif /* USE_FULL_LL_DRIVER */
00064
00065 /* Exported constants --------------------------------------------------------*/
00066 /** @defgroup PKA_LL_Exported_Constants PKA Exported Constants
00067   * @{
00068   */
00069
00070 /** @defgroup PKA_LL_EC_GET_FLAG Get Flags Defines
00071   * @brief    Flags defines which can be used with LL_PKA_ReadReg function
00072   * @{
00073   */
00074 #define LL_PKA_SR_ADDRERRF                 PKA_SR_ADDRERRF
00075 #define LL_PKA_SR_RAMERRF                  PKA_SR_RAMERRF
00076 #define LL_PKA_SR_PROCENDF                 PKA_SR_PROCENDF
00077 #define LL_PKA_SR_BUSY                     PKA_SR_BUSY
00078 /**
00079   * @}
00080   */
00081
00082 /** @defgroup PKA_LL_EC_IT IT Defines
00083   * @brief    IT defines which can be used with LL_PKA_ReadReg and  LL_PKA_WriteReg functions
00084   * @{
00085   */
00086 #define LL_PKA_CR_ADDRERRIE                PKA_CR_ADDRERRIE
00087 #define LL_PKA_CR_RAMERRIE                 PKA_CR_RAMERRIE
00088 #define LL_PKA_CR_PROCENDIE                PKA_CR_PROCENDIE
00089 #define LL_PKA_CLRFR_PROCENDFC             PKA_CLRFR_PROCENDFC
00090 #define LL_PKA_CLRFR_RAMERRFC              PKA_CLRFR_RAMERRFC
00091 #define LL_PKA_CLRFR_ADDRERRFC             PKA_CLRFR_ADDRERRFC
00092 /**
00093   * @}
00094   */
00095
00096 /** @defgroup PKA_LL_EC_MODE Operation Mode
00097   * @brief    List of opearation mode.
00098   * @{
00099   */
00100 #define LL_PKA_MODE_MONTGOMERY_PARAM_MOD_EXP ((uint32_t)0x00000000U) /*!< Compute Montgomery parameter and modular exponentiation */
00101 #define LL_PKA_MODE_MONTGOMERY_PARAM         ((uint32_t)0x00000001U) /*!< Compute Montgomery parameter only */
00102 #define LL_PKA_MODE_MODULAR_EXP              ((uint32_t)0x00000002U) /*!< Compute modular exponentiation only (Montgomery parameter should be loaded) */
00103 #define LL_PKA_MODE_MONTGOMERY_PARAM_ECC     ((uint32_t)0x00000020U) /*!< Compute Montgomery parameter and compute ECC kP operation */
00104 #define LL_PKA_MODE_ECC_KP_PRIMITIVE         ((uint32_t)0x00000022U) /*!< Compute the ECC kP primitive only (Montgomery parameter should be loaded) */
00105 #define LL_PKA_MODE_ECDSA_SIGNATURE          ((uint32_t)0x00000024U) /*!< ECDSA signature */
00106 #define LL_PKA_MODE_ECDSA_VERIFICATION       ((uint32_t)0x00000026U) /*!< ECDSA verification */
00107 #define LL_PKA_MODE_POINT_CHECK              ((uint32_t)0x00000028U) /*!< Point check */
00108 #define LL_PKA_MODE_RSA_CRT_EXP              ((uint32_t)0x00000007U) /*!< RSA CRT exponentiation */
00109 #define LL_PKA_MODE_MODULAR_INV              ((uint32_t)0x00000008U) /*!< Modular inversion */
00110 #define LL_PKA_MODE_ARITHMETIC_ADD           ((uint32_t)0x00000009U) /*!< Arithmetic addition */
00111 #define LL_PKA_MODE_ARITHMETIC_SUB           ((uint32_t)0x0000000AU) /*!< Arithmetic subtraction */
00112 #define LL_PKA_MODE_ARITHMETIC_MUL           ((uint32_t)0x0000000BU) /*!< Arithmetic multiplication */
00113 #define LL_PKA_MODE_COMPARISON               ((uint32_t)0x0000000CU) /*!< Comparison */
00114 #define LL_PKA_MODE_MODULAR_REDUC            ((uint32_t)0x0000000DU) /*!< Modular reduction */
00115 #define LL_PKA_MODE_MODULAR_ADD              ((uint32_t)0x0000000EU) /*!< Modular addition */
00116 #define LL_PKA_MODE_MODULAR_SUB              ((uint32_t)0x0000000FU) /*!< Modular subtraction */
00117 #define LL_PKA_MODE_MONTGOMERY_MUL           ((uint32_t)0x00000010U) /*!< Montgomery multiplication */
00118 /**
00119   * @}
00120   */
00121
00122 /**
00123   * @}
00124   */
00125
00126 /* Exported macro ------------------------------------------------------------*/
00127 /** @defgroup PKA_LL_Exported_Macros PKA Exported Macros
00128   * @{
00129   */
00130
00131 /** @defgroup PKA_LL_EM_WRITE_READ Common Write and read registers Macros
00132   * @{
00133   */
00134
00135 /**
00136   * @brief  Write a value in PKA register
00137   * @param  __INSTANCE__ PKA Instance
00138   * @param  __REG__ Register to be written
00139   * @param  __VALUE__ Value to be written in the register
00140   * @retval None
00141   */
00142 #define LL_PKA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00143
00144 /**
00145   * @brief  Read a value in PKA register
00146   * @param  __INSTANCE__ PKA Instance
00147   * @param  __REG__ Register to be read
00148   * @retval Register value
00149   */
00150 #define LL_PKA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00151 /**
00152   * @}
00153   */
00154
00155 /**
00156   * @}
00157   */
00158
00159 /* Exported functions --------------------------------------------------------*/
00160 /** @defgroup PKA_LL_Exported_Functions PKA Exported Functions
00161   * @{
00162   */
00163
00164 /** @defgroup PKA_LL_EF_Configuration Configuration
00165   * @{
00166   */
00167
00168 /**
00169   * @brief  Configure PKA peripheral.
00170   * @brief  Set PKA operating mode.
00171   * @rmtoll CR           MODE          LL_PKA_Config
00172   * @param  PKAx PKA Instance.
00173   * @param  Mode This parameter can be one of the following values:
00174   *         @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM_MOD_EXP
00175   *         @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM
00176   *         @arg @ref LL_PKA_MODE_MODULAR_EXP
00177   *         @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM_ECC
00178   *         @arg @ref LL_PKA_MODE_ECC_KP_PRIMITIVE
00179   *         @arg @ref LL_PKA_MODE_ECDSA_SIGNATURE
00180   *         @arg @ref LL_PKA_MODE_ECDSA_VERIFICATION
00181   *         @arg @ref LL_PKA_MODE_POINT_CHECK
00182   *         @arg @ref LL_PKA_MODE_RSA_CRT_EXP
00183   *         @arg @ref LL_PKA_MODE_MODULAR_INV
00184   *         @arg @ref LL_PKA_MODE_ARITHMETIC_ADD
00185   *         @arg @ref LL_PKA_MODE_ARITHMETIC_SUB
00186   *         @arg @ref LL_PKA_MODE_ARITHMETIC_MUL
00187   *         @arg @ref LL_PKA_MODE_COMPARISON
00188   *         @arg @ref LL_PKA_MODE_MODULAR_REDUC
00189   *         @arg @ref LL_PKA_MODE_MODULAR_ADD
00190   *         @arg @ref LL_PKA_MODE_MODULAR_SUB
00191   *         @arg @ref LL_PKA_MODE_MONTGOMERY_MUL
00192   */
00193 __STATIC_INLINE void LL_PKA_Config(PKA_TypeDef *PKAx, uint32_t Mode)
00194 {
00195   MODIFY_REG(PKAx->CR, (PKA_CR_MODE), (Mode << PKA_CR_MODE_Pos));
00196 }
00197
00198 /**
00199   * @brief  Enable PKA peripheral.
00200   * @rmtoll CR           EN            LL_PKA_Enable
00201   * @param  PKAx PKA Instance.
00202   * @retval None
00203   */
00204 __STATIC_INLINE void LL_PKA_Enable(PKA_TypeDef *PKAx)
00205 {
00206   SET_BIT(PKAx->CR, PKA_CR_EN);
00207 }
00208
00209 /**
00210   * @brief  Disable PKA peripheral.
00211   * @rmtoll CR           EN            LL_PKA_Disable
00212   * @param  PKAx PKA Instance.
00213   * @retval None
00214   */
00215 __STATIC_INLINE void LL_PKA_Disable(PKA_TypeDef *PKAx)
00216 {
00217   CLEAR_BIT(PKAx->CR, PKA_CR_EN);
00218 }
00219
00220 /**
00221   * @brief  Check if the PKA peripheral is enabled or disabled.
00222   * @rmtoll CR           EN            LL_PKA_IsEnabled
00223   * @param  PKAx PKA Instance.
00224   * @retval State of bit (1 or 0).
00225   */
00226 __STATIC_INLINE uint32_t LL_PKA_IsEnabled(PKA_TypeDef *PKAx)
00227 {
00228   return ((READ_BIT(PKAx->CR, PKA_CR_EN) == (PKA_CR_EN)) ? 1UL : 0UL);
00229 }
00230
00231 /**
00232   * @brief  Set PKA operating mode.
00233   * @rmtoll CR           MODE          LL_PKA_SetMode
00234   * @param  PKAx PKA Instance.
00235   * @param  Mode This parameter can be one of the following values:
00236   *         @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM_MOD_EXP
00237   *         @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM
00238   *         @arg @ref LL_PKA_MODE_MODULAR_EXP
00239   *         @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM_ECC
00240   *         @arg @ref LL_PKA_MODE_ECC_KP_PRIMITIVE
00241   *         @arg @ref LL_PKA_MODE_ECDSA_SIGNATURE
00242   *         @arg @ref LL_PKA_MODE_ECDSA_VERIFICATION
00243   *         @arg @ref LL_PKA_MODE_POINT_CHECK
00244   *         @arg @ref LL_PKA_MODE_RSA_CRT_EXP
00245   *         @arg @ref LL_PKA_MODE_MODULAR_INV
00246   *         @arg @ref LL_PKA_MODE_ARITHMETIC_ADD
00247   *         @arg @ref LL_PKA_MODE_ARITHMETIC_SUB
00248   *         @arg @ref LL_PKA_MODE_ARITHMETIC_MUL
00249   *         @arg @ref LL_PKA_MODE_COMPARISON
00250   *         @arg @ref LL_PKA_MODE_MODULAR_REDUC
00251   *         @arg @ref LL_PKA_MODE_MODULAR_ADD
00252   *         @arg @ref LL_PKA_MODE_MODULAR_SUB
00253   *         @arg @ref LL_PKA_MODE_MONTGOMERY_MUL
00254   * @retval None
00255   */
00256 __STATIC_INLINE void LL_PKA_SetMode(PKA_TypeDef *PKAx, uint32_t Mode)
00257 {
00258   MODIFY_REG(PKAx->CR, PKA_CR_MODE, Mode << PKA_CR_MODE_Pos);
00259 }
00260
00261 /**
00262   * @brief  Get PKA operating mode.
00263   * @rmtoll CR           MODE          LL_PKA_GetMode
00264   * @param  PKAx PKA Instance.
00265   * @retval Returned value can be one of the following values:
00266   *         @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM_MOD_EXP
00267   *         @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM
00268   *         @arg @ref LL_PKA_MODE_MODULAR_EXP
00269   *         @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM_ECC
00270   *         @arg @ref LL_PKA_MODE_ECC_KP_PRIMITIVE
00271   *         @arg @ref LL_PKA_MODE_ECDSA_SIGNATURE
00272   *         @arg @ref LL_PKA_MODE_ECDSA_VERIFICATION
00273   *         @arg @ref LL_PKA_MODE_POINT_CHECK
00274   *         @arg @ref LL_PKA_MODE_RSA_CRT_EXP
00275   *         @arg @ref LL_PKA_MODE_MODULAR_INV
00276   *         @arg @ref LL_PKA_MODE_ARITHMETIC_ADD
00277   *         @arg @ref LL_PKA_MODE_ARITHMETIC_SUB
00278   *         @arg @ref LL_PKA_MODE_ARITHMETIC_MUL
00279   *         @arg @ref LL_PKA_MODE_COMPARISON
00280   *         @arg @ref LL_PKA_MODE_MODULAR_REDUC
00281   *         @arg @ref LL_PKA_MODE_MODULAR_ADD
00282   *         @arg @ref LL_PKA_MODE_MODULAR_SUB
00283   *         @arg @ref LL_PKA_MODE_MONTGOMERY_MUL
00284   */
00285 __STATIC_INLINE uint32_t LL_PKA_GetMode(PKA_TypeDef *PKAx)
00286 {
00287   return (uint32_t)(READ_BIT(PKAx->CR, PKA_CR_MODE) >> PKA_CR_MODE_Pos);
00288 }
00289
00290 /**
00291   * @brief  Start the operation selected using LL_PKA_SetMode.
00292   * @rmtoll CR           START         LL_PKA_Start
00293   * @param  PKAx PKA Instance.
00294   * @retval None
00295   */
00296 __STATIC_INLINE void LL_PKA_Start(PKA_TypeDef *PKAx)
00297 {
00298   SET_BIT(PKAx->CR, PKA_CR_START);
00299 }
00300
00301 /**
00302   * @}
00303   */
00304
00305 /** @defgroup PKA_LL_EF_IT_Management IT_Management
00306   * @{
00307   */
00308
00309 /**
00310   * @brief  Enable address error interrupt.
00311   * @rmtoll CR           ADDRERRIE     LL_PKA_EnableIT_ADDRERR
00312   * @param  PKAx PKA Instance.
00313   * @retval None
00314   */
00315 __STATIC_INLINE void LL_PKA_EnableIT_ADDRERR(PKA_TypeDef *PKAx)
00316 {
00317   SET_BIT(PKAx->CR, PKA_CR_ADDRERRIE);
00318 }
00319
00320 /**
00321   * @brief  Enable RAM error interrupt.
00322   * @rmtoll CR           RAMERRIE      LL_PKA_EnableIT_RAMERR
00323   * @param  PKAx PKA Instance.
00324   * @retval None
00325   */
00326 __STATIC_INLINE void LL_PKA_EnableIT_RAMERR(PKA_TypeDef *PKAx)
00327 {
00328   SET_BIT(PKAx->CR, PKA_CR_RAMERRIE);
00329 }
00330
00331 /**
00332   * @brief  Enable end of operation interrupt.
00333   * @rmtoll CR           PROCENDIE     LL_PKA_EnableIT_PROCEND
00334   * @param  PKAx PKA Instance.
00335   * @retval None
00336   */
00337 __STATIC_INLINE void LL_PKA_EnableIT_PROCEND(PKA_TypeDef *PKAx)
00338 {
00339   SET_BIT(PKAx->CR, PKA_CR_PROCENDIE);
00340 }
00341
00342 /**
00343   * @brief  Disable address error interrupt.
00344   * @rmtoll CR           ADDRERRIE     LL_PKA_DisableIT_ADDERR
00345   * @param  PKAx PKA Instance.
00346   * @retval None
00347   */
00348 __STATIC_INLINE void LL_PKA_DisableIT_ADDERR(PKA_TypeDef *PKAx)
00349 {
00350   CLEAR_BIT(PKAx->CR, PKA_CR_ADDRERRIE);
00351 }
00352
00353 /**
00354   * @brief  Disable RAM error interrupt.
00355   * @rmtoll CR           RAMERRIE      LL_PKA_DisableIT_RAMERR
00356   * @param  PKAx PKA Instance.
00357   * @retval None
00358   */
00359 __STATIC_INLINE void LL_PKA_DisableIT_RAMERR(PKA_TypeDef *PKAx)
00360 {
00361   CLEAR_BIT(PKAx->CR, PKA_CR_RAMERRIE);
00362 }
00363
00364 /**
00365   * @brief  Disable End of operation interrupt.
00366   * @rmtoll CR           PROCENDIE     LL_PKA_DisableIT_PROCEND
00367   * @param  PKAx PKA Instance.
00368   * @retval None
00369   */
00370 __STATIC_INLINE void LL_PKA_DisableIT_PROCEND(PKA_TypeDef *PKAx)
00371 {
00372   CLEAR_BIT(PKAx->CR, PKA_CR_PROCENDIE);
00373 }
00374
00375 /**
00376   * @brief  Check if address error interrupt is enabled.
00377   * @rmtoll CR           ADDRERRIE     LL_PKA_IsEnabledIT_ADDRERR
00378   * @param  PKAx PKA Instance.
00379   * @retval State of bit (1 or 0).
00380   */
00381 __STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_ADDRERR(PKA_TypeDef *PKAx)
00382 {
00383   return ((READ_BIT(PKAx->CR, PKA_CR_ADDRERRIE) == (PKA_CR_ADDRERRIE)) ? 1UL : 0UL);
00384 }
00385
00386 /**
00387   * @brief  Check if RAM error interrupt is enabled.
00388   * @rmtoll CR           RAMERRIE      LL_PKA_IsEnabledIT_RAMERR
00389   * @param  PKAx PKA Instance.
00390   * @retval State of bit (1 or 0).
00391   */
00392 __STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_RAMERR(PKA_TypeDef *PKAx)
00393 {
00394   return ((READ_BIT(PKAx->CR, PKA_CR_RAMERRIE) == (PKA_CR_RAMERRIE)) ? 1UL : 0UL);
00395 }
00396
00397 /**
00398   * @brief  Check if end of operation interrupt is enabled.
00399   * @rmtoll CR           PROCENDIE     LL_PKA_IsEnabledIT_PROCEND
00400   * @param  PKAx PKA Instance.
00401   * @retval State of bit (1 or 0).
00402   */
00403 __STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_PROCEND(PKA_TypeDef *PKAx)
00404 {
00405   return ((READ_BIT(PKAx->CR, PKA_CR_PROCENDIE) == (PKA_CR_PROCENDIE)) ? 1UL : 0UL);
00406 }
00407
00408 /**
00409   * @}
00410   */
00411
00412 /** @defgroup PKA_LL_EF_FLAG_Management PKA flag management
00413   * @{
00414   */
00415
00416 /**
00417   * @brief  Get PKA address error flag.
00418   * @rmtoll SR           ADDRERRF      LL_PKA_IsActiveFlag_ADDRERR
00419   * @param  PKAx PKA Instance.
00420   * @retval State of bit (1 or 0).
00421   */
00422 __STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_ADDRERR(PKA_TypeDef *PKAx)
00423 {
00424   return ((READ_BIT(PKAx->SR, PKA_SR_ADDRERRF) == (PKA_SR_ADDRERRF)) ? 1UL : 0UL);
00425 }
00426
00427 /**
00428   * @brief  Get PKA RAM error flag.
00429   * @rmtoll SR           RAMERRF       LL_PKA_IsActiveFlag_RAMERR
00430   * @param  PKAx PKA Instance.
00431   * @retval State of bit (1 or 0).
00432   */
00433 __STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_RAMERR(PKA_TypeDef *PKAx)
00434 {
00435   return ((READ_BIT(PKAx->SR, PKA_SR_RAMERRF) == (PKA_SR_RAMERRF)) ? 1UL : 0UL);
00436 }
00437
00438 /**
00439   * @brief  Get PKA end of operation flag.
00440   * @rmtoll SR           PROCENDF      LL_PKA_IsActiveFlag_PROCEND
00441   * @param  PKAx PKA Instance.
00442   * @retval State of bit (1 or 0).
00443   */
00444 __STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_PROCEND(PKA_TypeDef *PKAx)
00445 {
00446   return ((READ_BIT(PKAx->SR, PKA_SR_PROCENDF) == (PKA_SR_PROCENDF)) ? 1UL : 0UL);
00447 }
00448
00449 /**
00450   * @brief  Get PKA busy flag.
00451   * @rmtoll SR           BUSY          LL_PKA_IsActiveFlag_BUSY
00452   * @param  PKAx PKA Instance.
00453   * @retval State of bit (1 or 0).
00454   */
00455 __STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_BUSY(PKA_TypeDef *PKAx)
00456 {
00457   return ((READ_BIT(PKAx->SR, PKA_SR_BUSY) == (PKA_SR_BUSY)) ? 1UL : 0UL);
00458 }
00459
00460 /**
00461   * @brief  Clear PKA address error flag.
00462   * @rmtoll CLRFR        ADDRERRFC     LL_PKA_ClearFlag_ADDERR
00463   * @param  PKAx PKA Instance.
00464   * @retval None
00465   */
00466 __STATIC_INLINE void LL_PKA_ClearFlag_ADDERR(PKA_TypeDef *PKAx)
00467 {
00468   SET_BIT(PKAx->CLRFR, PKA_CLRFR_ADDRERRFC);
00469 }
00470
00471 /**
00472   * @brief  Clear PKA RAM error flag.
00473   * @rmtoll CLRFR        RAMERRFC      LL_PKA_ClearFlag_RAMERR
00474   * @param  PKAx PKA Instance.
00475   * @retval None
00476   */
00477 __STATIC_INLINE void LL_PKA_ClearFlag_RAMERR(PKA_TypeDef *PKAx)
00478 {
00479   SET_BIT(PKAx->CLRFR, PKA_CLRFR_RAMERRFC);
00480 }
00481
00482 /**
00483   * @brief  Clear PKA end of operation flag.
00484   * @rmtoll CLRFR        PROCENDFC     LL_PKA_ClearFlag_PROCEND
00485   * @param  PKAx PKA Instance.
00486   * @retval None
00487   */
00488 __STATIC_INLINE void LL_PKA_ClearFlag_PROCEND(PKA_TypeDef *PKAx)
00489 {
00490   SET_BIT(PKAx->CLRFR, PKA_CLRFR_PROCENDFC);
00491 }
00492
00493 /**
00494   * @}
00495   */
00496
00497 #if defined(USE_FULL_LL_DRIVER)
00498
00499 /** @defgroup PKA_LL_EF_Init Initialization and de-initialization functions
00500   * @{
00501   */
00502
00503 ErrorStatus LL_PKA_DeInit(PKA_TypeDef *PKAx);
00504 ErrorStatus LL_PKA_Init(PKA_TypeDef *PKAx, LL_PKA_InitTypeDef *PKA_InitStruct);
00505 void LL_PKA_StructInit(LL_PKA_InitTypeDef *PKA_InitStruct);
00506
00507 /**
00508   * @}
00509   */
00510
00511 #endif /* USE_FULL_LL_DRIVER */
00512 /**
00513   * @}
00514   */
00515
00516 /**
00517   * @}
00518   */
00519
00520 #endif /* defined(PKA) */
00521
00522 /**
00523   * @}
00524   */
00525
00526 #ifdef __cplusplus
00527 }
00528 #endif
00529
00530 #endif /* STM32WBxx_LL_PKA_H */
00531
00532 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_pwr.c Source File

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stm32wbxx_ll_pwr.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_pwr.c
00004   * @author  MCD Application Team
00005   * @brief   PWR LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32wbxx_ll_pwr.h"
00023 #include "stm32wbxx_ll_bus.h"
00024
00025 /** @addtogroup STM32WBxx_LL_Driver
00026   * @{
00027   */
00028
00029 #if defined(PWR)
00030
00031 /** @defgroup PWR_LL PWR
00032   * @{
00033   */
00034
00035 /* Private types -------------------------------------------------------------*/
00036 /* Private variables ---------------------------------------------------------*/
00037 /* Private constants ---------------------------------------------------------*/
00038
00039 /** @defgroup PWR_LL_Private_Constants PWR Private Constants
00040   * @{
00041   */
00042 /* Definitions of PWR registers reset value */
00043 #define PWR_CR1_RESET_VALUE   (0x00000200)
00044 #define PWR_CR2_RESET_VALUE   (0x00000000)
00045 #define PWR_CR3_RESET_VALUE   (0x00008000)
00046 #define PWR_CR4_RESET_VALUE   (0x00000000)
00047 #define PWR_CR5_RESET_VALUE   (0x00004272)
00048 #define PWR_PUCRA_RESET_VALUE (0x00000000)
00049 #define PWR_PDCRA_RESET_VALUE (0x00000000)
00050 #define PWR_PUCRB_RESET_VALUE (0x00000000)
00051 #define PWR_PDCRB_RESET_VALUE (0x00000000)
00052 #define PWR_PUCRC_RESET_VALUE (0x00000000)
00053 #define PWR_PDCRC_RESET_VALUE (0x00000000)
00054 #define PWR_PUCRD_RESET_VALUE (0x00000000)
00055 #define PWR_PDCRD_RESET_VALUE (0x00000000)
00056 #define PWR_PUCRE_RESET_VALUE (0x00000000)
00057 #define PWR_PDCRE_RESET_VALUE (0x00000000)
00058 #define PWR_PUCRH_RESET_VALUE (0x00000000)
00059 #define PWR_PDCRH_RESET_VALUE (0x00000000)
00060 #define PWR_C2CR1_RESET_VALUE (0x00000000)
00061 #define PWR_C2CR3_RESET_VALUE (0x00008000)
00062 /**
00063   * @}
00064   */
00065
00066 /* Private macros ------------------------------------------------------------*/
00067 /* Private function prototypes -----------------------------------------------*/
00068
00069 /* Exported functions --------------------------------------------------------*/
00070 /** @addtogroup PWR_LL_Exported_Functions
00071   * @{
00072   */
00073
00074 /** @addtogroup PWR_LL_EF_Init
00075   * @{
00076   */
00077
00078 /**
00079   * @brief  De-initialize the PWR registers to their default reset values.
00080   * @retval An ErrorStatus enumeration value:
00081   *          - SUCCESS: PWR registers are de-initialized
00082   *          - ERROR: not applicable
00083   */
00084 ErrorStatus LL_PWR_DeInit(void)
00085 {
00086   /* Apply reset values to all PWR registers */
00087   LL_PWR_WriteReg(CR1, PWR_CR1_RESET_VALUE);
00088   LL_PWR_WriteReg(CR2, PWR_CR2_RESET_VALUE);
00089   LL_PWR_WriteReg(CR3, PWR_CR3_RESET_VALUE);
00090   LL_PWR_WriteReg(CR4, PWR_CR4_RESET_VALUE);
00091   LL_PWR_WriteReg(CR5, PWR_CR5_RESET_VALUE);
00092   LL_PWR_WriteReg(PUCRA, PWR_PUCRA_RESET_VALUE);
00093   LL_PWR_WriteReg(PDCRA, PWR_PDCRA_RESET_VALUE);
00094   LL_PWR_WriteReg(PUCRB, PWR_PUCRB_RESET_VALUE);
00095   LL_PWR_WriteReg(PDCRB, PWR_PDCRB_RESET_VALUE);
00096   LL_PWR_WriteReg(PUCRC, PWR_PUCRC_RESET_VALUE);
00097   LL_PWR_WriteReg(PDCRC, PWR_PDCRC_RESET_VALUE);
00098 #if defined(GPIOD)
00099   LL_PWR_WriteReg(PUCRD, PWR_PUCRD_RESET_VALUE);
00100   LL_PWR_WriteReg(PDCRD, PWR_PDCRD_RESET_VALUE);
00101 #endif
00102   LL_PWR_WriteReg(PUCRE, PWR_PUCRE_RESET_VALUE);
00103   LL_PWR_WriteReg(PDCRE, PWR_PDCRE_RESET_VALUE);
00104   LL_PWR_WriteReg(PUCRH, PWR_PUCRH_RESET_VALUE);
00105   LL_PWR_WriteReg(PDCRH, PWR_PDCRH_RESET_VALUE);
00106   LL_PWR_WriteReg(C2CR1, PWR_C2CR1_RESET_VALUE);
00107   LL_PWR_WriteReg(C2CR3, PWR_C2CR3_RESET_VALUE);
00108
00109   /* Clear all flags */
00110   LL_PWR_WriteReg(SCR,
00111                     LL_PWR_SCR_CC2HF
00112                   | LL_PWR_SCR_C802AF
00113                   | LL_PWR_SCR_CBLEAF
00114                   | LL_PWR_SCR_CCRPEF
00115                   | LL_PWR_SCR_C802WUF
00116                   | LL_PWR_SCR_CBLEWUF
00117 #if defined(PWR_CR5_SMPSEN)
00118                   | LL_PWR_SCR_CBORHF
00119                   | LL_PWR_SCR_CSMPSFBF
00120 #endif
00121                   | LL_PWR_SCR_CWUF
00122                  );
00123
00124   LL_PWR_WriteReg(EXTSCR,
00125                     LL_PWR_EXTSCR_CCRPF
00126                   | LL_PWR_EXTSCR_C2CSSF
00127                   | LL_PWR_EXTSCR_C1CSSF
00128                  );
00129
00130   return SUCCESS;
00131 }
00132
00133 /**
00134   * @}
00135   */
00136
00137 /**
00138   * @}
00139   */
00140
00141 /**
00142   * @}
00143   */
00144 #endif /* defined(PWR) */
00145 /**
00146   * @}
00147   */
00148
00149 #endif /* USE_FULL_LL_DRIVER */
00150
00151 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_pwr.h Source File

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  • STM32WBxx_HAL_Driver
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stm32wbxx_ll_pwr.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_pwr.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of PWR LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_LL_PWR_H
00022 #define STM32WBxx_LL_PWR_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx.h"
00030
00031 /** @addtogroup STM32WBxx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined(PWR)
00036
00037 /** @defgroup PWR_LL PWR
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043
00044 /* Private constants ---------------------------------------------------------*/
00045 /** @defgroup PWR_LL_Private_Constants PWR Private Constants
00046   * @{
00047   */
00048
00049 #if defined(PWR_CR5_SMPSEN)
00050 /** @defgroup PWR_SMPS_Calibration PWR SMPS calibration
00051   * @{
00052   */
00053 #define SMPS_VOLTAGE_CAL_ADDR              ((uint32_t*) (0x1FFF7558UL))         /* SMPS output voltage calibration level corresponding to voltage "SMPS_VOLTAGE_CAL_VOLTAGE_MV" */
00054 #define SMPS_VOLTAGE_CAL_POS               (8UL)                                /* SMPS output voltage calibration level bitfield position */
00055 #define SMPS_VOLTAGE_CAL                   (0xFUL << SMPS_VOLTAGE_CAL_POS)      /* SMPS output voltage calibration level bitfield mask */
00056 #define SMPS_VOLTAGE_CAL_VOLTAGE_MV        (1500UL)                             /* SMPS output voltage calibration value (unit: mV) */
00057 #define SMPS_VOLTAGE_BASE_MV               (1200UL)                             /* SMPS output voltage base value (unit: mV) */
00058 #define SMPS_VOLTAGE_STEP_MV               (  50UL)                             /* SMPS output voltage step (unit: mV) */
00059 /**
00060   * @}
00061   */
00062 #endif
00063
00064 /**
00065   * @}
00066   */
00067
00068 /* Private macros ------------------------------------------------------------*/
00069
00070 /* Exported types ------------------------------------------------------------*/
00071 /* Exported constants --------------------------------------------------------*/
00072 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
00073   * @{
00074   */
00075
00076 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
00077   * @brief    Flags defines which can be used with LL_PWR_WriteReg function
00078   * @{
00079   */
00080 #define LL_PWR_SCR_CWUF                    PWR_SCR_CWUF
00081 #if defined(PWR_CR3_EWUP2)
00082 #define LL_PWR_SCR_CWUF5                   PWR_SCR_CWUF5
00083 #endif
00084 #define LL_PWR_SCR_CWUF4                   PWR_SCR_CWUF4
00085 #if defined(PWR_CR3_EWUP3)
00086 #define LL_PWR_SCR_CWUF3                   PWR_SCR_CWUF3
00087 #endif
00088 #if defined(PWR_CR3_EWUP2)
00089 #define LL_PWR_SCR_CWUF2                   PWR_SCR_CWUF2
00090 #endif
00091 #define LL_PWR_SCR_CWUF1                   PWR_SCR_CWUF1
00092 #define LL_PWR_SCR_CC2HF                   PWR_SCR_CC2HF
00093 #define LL_PWR_SCR_C802AF                  PWR_SCR_C802AF
00094 #define LL_PWR_SCR_CBLEAF                  PWR_SCR_CBLEAF
00095 #define LL_PWR_SCR_CCRPEF                  PWR_SCR_CCRPEF
00096 #define LL_PWR_SCR_C802WUF                 PWR_SCR_C802WUF
00097 #define LL_PWR_SCR_CBLEWUF                 PWR_SCR_CBLEWUF
00098 #if defined(PWR_CR5_SMPSEN)
00099 #define LL_PWR_SCR_CBORHF                  PWR_SCR_CBORHF
00100 #define LL_PWR_SCR_CSMPSFBF                PWR_SCR_CSMPSFBF
00101 #endif
00102 #define LL_PWR_EXTSCR_CCRPF                PWR_EXTSCR_CCRPF
00103 #define LL_PWR_EXTSCR_C2CSSF               PWR_EXTSCR_C2CSSF
00104 #define LL_PWR_EXTSCR_C1CSSF               PWR_EXTSCR_C1CSSF
00105 /**
00106   * @}
00107   */
00108
00109 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
00110   * @brief    Flags defines which can be used with LL_PWR_ReadReg function
00111   * @{
00112   */
00113 #define LL_PWR_SR1_WUFI                    PWR_SR1_WUFI
00114 #if defined(PWR_CR3_EWUP5)
00115 #define LL_PWR_SR1_WUF5                    PWR_SR1_WUF5
00116 #endif
00117 #define LL_PWR_SR1_WUF4                    PWR_SR1_WUF4
00118 #if defined(PWR_CR3_EWUP3)
00119 #define LL_PWR_SR1_WUF3                    PWR_SR1_WUF3
00120 #endif
00121 #if defined(PWR_CR3_EWUP2)
00122 #define LL_PWR_SR1_WUF2                    PWR_SR1_WUF2
00123 #endif
00124 #define LL_PWR_SR1_WUF1                    PWR_SR1_WUF1
00125 #define LL_PWR_SR2_PVMO3                   PWR_SR2_PVMO3
00126 #if defined(PWR_CR2_PVME1)
00127 #define LL_PWR_SR2_PVMO1                   PWR_SR2_PVMO1
00128 #endif
00129 #define LL_PWR_SR2_PVDO                    PWR_SR2_PVDO
00130 #if defined(PWR_CR1_VOS)
00131 #define LL_PWR_SR2_VOSF                    PWR_SR2_VOSF
00132 #endif
00133 #define LL_PWR_SR2_REGLPF                  PWR_SR2_REGLPF
00134 #define LL_PWR_SR2_REGLPS                  PWR_SR2_REGLPS
00135
00136 /* BOR flags */
00137 #define LL_PWR_FLAG_BORH                   PWR_SR1_BORHF  /* BORH interrupt flag */
00138
00139 #if defined(PWR_CR5_SMPSEN)
00140 /* SMPS flags */
00141 #define LL_PWR_FLAG_SMPS                   PWR_SR2_SMPSF  /* SMPS step down converter ready flag */
00142 #define LL_PWR_FLAG_SMPSB                  PWR_SR2_SMPSBF /* SMPS step down converter in bypass mode flag */
00143 #define LL_PWR_FLAG_SMPSFB                 PWR_SR1_SMPSFB /* SMPS step down converter forced in bypass mode interrupt flag */
00144 #endif
00145
00146 /* Radio (BLE or 802.15.4) flags */
00147 #define LL_PWR_FLAG_BLEWU                  PWR_SR1_BLEWUF  /* BLE wakeup interrupt flag */
00148 #define LL_PWR_FLAG_802WU                  PWR_SR1_802WUF  /* 802.15.4 wakeup interrupt flag */
00149 #define LL_PWR_FLAG_BLEA                   PWR_SR1_BLEAF   /* BLE end of activity interrupt flag */
00150 #define LL_PWR_FLAG_802A                   PWR_SR1_802AF   /* 802.15.4 end of activity interrupt flag */
00151 #define LL_PWR_FLAG_CRPE                   PWR_SR1_CRPEF   /* Critical radio phase end of activity interrupt flag */
00152 #define LL_PWR_FLAG_CRP                    PWR_EXTSCR_CRPF /* Critical radio system phase */
00153
00154 /* Multicore flags */
00155 #define LL_PWR_EXTSCR_C1SBF                PWR_EXTSCR_C1SBF   /* System standby flag for CPU1 */
00156 #define LL_PWR_EXTSCR_C1STOPF              PWR_EXTSCR_C1STOPF /* System stop flag for CPU1 */
00157 #define LL_PWR_EXTSCR_C1DS                 PWR_EXTSCR_C1DS    /* CPU1 deepsleep mode */
00158 #define LL_PWR_EXTSCR_C2SBF                PWR_EXTSCR_C2SBF   /* System standby flag for CPU2 */
00159 #define LL_PWR_EXTSCR_C2STOPF              PWR_EXTSCR_C2STOPF /* System stop flag for CPU2 */
00160 #define LL_PWR_EXTSCR_C2DS                 PWR_EXTSCR_C2DS    /* CPU2 deepsleep mode */
00161 #define LL_PWR_SR1_C2HF                    PWR_SR1_C2HF       /* CPU2 hold interrupt flag */
00162 /**
00163   * @}
00164   */
00165
00166 #if defined(PWR_CR1_VOS)
00167 /** @defgroup PWR_LL_EC_REGU_VOLTAGE REGU VOLTAGE
00168   * @{
00169   */
00170 #define LL_PWR_REGU_VOLTAGE_SCALE1         (PWR_CR1_VOS_0) /* Regulator voltage output range 1 mode, typical output voltage at 1.2 V, system frequency up to 64 MHz. */
00171 #define LL_PWR_REGU_VOLTAGE_SCALE2         (PWR_CR1_VOS_1) /* Regulator voltage output range 2 mode, typical output voltage at 1.0 V, system frequency up to 16 MHz. */
00172 /**
00173   * @}
00174   */
00175 #endif
00176
00177 /** @defgroup PWR_LL_EC_MODE_PWR MODE PWR
00178   * @{
00179   */
00180 #define LL_PWR_MODE_STOP0                  (0x000000000U)
00181 #define LL_PWR_MODE_STOP1                  (PWR_CR1_LPMS_0)
00182 #define LL_PWR_MODE_STOP2                  (PWR_CR1_LPMS_1)
00183 #define LL_PWR_MODE_STANDBY                (PWR_CR1_LPMS_1 | PWR_CR1_LPMS_0)
00184 #define LL_PWR_MODE_SHUTDOWN               (PWR_CR1_LPMS_2)
00185 /**
00186   * @}
00187   */
00188
00189 /** @defgroup PWR_LL_EC_FLASH_LPRUN_POWER_DOWN_MODE Flash power-down mode during low-power run mode
00190   * @{
00191   */
00192 #define LL_PWR_FLASH_LPRUN_MODE_IDLE       (0x000000000U)
00193 #define LL_PWR_FLASH_LPRUN_MODE_POWER_DOWN (PWR_CR1_FPDR)
00194 /**
00195   * @}
00196   */
00197
00198 /** @defgroup PWR_LL_EC_FLASH_SLEEP_POWER_DOWN_MODE Flash power-down mode during sleep mode
00199   * @{
00200   */
00201 #define LL_PWR_FLASH_SLEEP_MODE_IDLE       (0x000000000U)
00202 #define LL_PWR_FLASH_SLEEP_MODE_POWER_DOWN (PWR_CR1_FPDS)
00203 /**
00204   * @}
00205   */
00206
00207 /** @defgroup PWR_LL_EC_PVM Peripheral voltage monitoring
00208   * @{
00209   */
00210 #if defined(PWR_CR2_PVME1)
00211 #define LL_PWR_PVM_VDDUSB_1_2V             (PWR_CR2_PVME1)     /* Monitoring VDDUSB vs. 1.2V */
00212 #endif
00213 #define LL_PWR_PVM_VDDA_1_62V              (PWR_CR2_PVME3)     /* Monitoring VDDA vs. 1.62V  */
00214 /**
00215   * @}
00216   */
00217
00218 /** @defgroup PWR_LL_EC_PVDLEVEL PVDLEVEL
00219   * @{
00220   */
00221 #define LL_PWR_PVDLEVEL_0                  (0x00000000U)                                   /* VPVD0 around 2.0 V */
00222 #define LL_PWR_PVDLEVEL_1                  (PWR_CR2_PLS_0)                                 /* VPVD1 around 2.2 V */
00223 #define LL_PWR_PVDLEVEL_2                  (PWR_CR2_PLS_1)                                 /* VPVD2 around 2.4 V */
00224 #define LL_PWR_PVDLEVEL_3                  (PWR_CR2_PLS_1 | PWR_CR2_PLS_0)                 /* VPVD3 around 2.5 V */
00225 #define LL_PWR_PVDLEVEL_4                  (PWR_CR2_PLS_2)                                 /* VPVD4 around 2.6 V */
00226 #define LL_PWR_PVDLEVEL_5                  (PWR_CR2_PLS_2 | PWR_CR2_PLS_0)                 /* VPVD5 around 2.8 V */
00227 #define LL_PWR_PVDLEVEL_6                  (PWR_CR2_PLS_2 | PWR_CR2_PLS_1)                 /* VPVD6 around 2.9 V */
00228 #define LL_PWR_PVDLEVEL_7                  (PWR_CR2_PLS_2 | PWR_CR2_PLS_1 | PWR_CR2_PLS_0) /* External input analog voltage   (Compare internally to VREFINT) */
00229 /**
00230   * @}
00231   */
00232
00233 /** @defgroup PWR_LL_EC_WAKEUP WAKEUP
00234   * @{
00235   */
00236 #define LL_PWR_WAKEUP_PIN1                 (PWR_CR3_EWUP1)
00237 #if defined(PWR_CR3_EWUP2)
00238 #define LL_PWR_WAKEUP_PIN2                 (PWR_CR3_EWUP2)
00239 #endif
00240 #if defined(PWR_CR3_EWUP3)
00241 #define LL_PWR_WAKEUP_PIN3                 (PWR_CR3_EWUP3)
00242 #endif
00243 #define LL_PWR_WAKEUP_PIN4                 (PWR_CR3_EWUP4)
00244 #if defined(PWR_CR3_EWUP5)
00245 #define LL_PWR_WAKEUP_PIN5                 (PWR_CR3_EWUP5)
00246 #endif
00247 /**
00248   * @}
00249   */
00250
00251 /** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR BATT CHARG RESISTOR
00252   * @{
00253   */
00254 #define LL_PWR_BATT_CHARG_RESISTOR_5K      (0x00000000U)
00255 #define LL_PWR_BATT_CHARGRESISTOR_1_5K     (PWR_CR4_VBRS)
00256 /**
00257   * @}
00258   */
00259
00260 /** @defgroup PWR_LL_EC_GPIO GPIO
00261   * @{
00262   */
00263 #define LL_PWR_GPIO_A                      ((uint32_t)(&(PWR->PUCRA)))
00264 #define LL_PWR_GPIO_B                      ((uint32_t)(&(PWR->PUCRB)))
00265 #define LL_PWR_GPIO_C                      ((uint32_t)(&(PWR->PUCRC)))
00266 #define LL_PWR_GPIO_D                      ((uint32_t)(&(PWR->PUCRD)))
00267 #define LL_PWR_GPIO_E                      ((uint32_t)(&(PWR->PUCRE)))
00268 #define LL_PWR_GPIO_H                      ((uint32_t)(&(PWR->PUCRH)))
00269 /**
00270   * @}
00271   */
00272
00273 /** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT
00274   * @{
00275   */
00276 #if defined(PWR_PUCRC_PC0)
00277 /* Note: LL_PWR_GPIO_BIT_x defined from port C because all pins are available */
00278 /*       for PWR pull-up and pull-down.                                       */
00279 #define LL_PWR_GPIO_BIT_0                  (PWR_PUCRC_PC0)
00280 #define LL_PWR_GPIO_BIT_1                  (PWR_PUCRC_PC1)
00281 #define LL_PWR_GPIO_BIT_2                  (PWR_PUCRC_PC2)
00282 #define LL_PWR_GPIO_BIT_3                  (PWR_PUCRC_PC3)
00283 #define LL_PWR_GPIO_BIT_4                  (PWR_PUCRC_PC4)
00284 #define LL_PWR_GPIO_BIT_5                  (PWR_PUCRC_PC5)
00285 #define LL_PWR_GPIO_BIT_6                  (PWR_PUCRC_PC6)
00286 #define LL_PWR_GPIO_BIT_7                  (PWR_PUCRC_PC7)
00287 #define LL_PWR_GPIO_BIT_8                  (PWR_PUCRC_PC8)
00288 #define LL_PWR_GPIO_BIT_9                  (PWR_PUCRC_PC9)
00289 #define LL_PWR_GPIO_BIT_10                 (PWR_PUCRC_PC10)
00290 #define LL_PWR_GPIO_BIT_11                 (PWR_PUCRC_PC11)
00291 #define LL_PWR_GPIO_BIT_12                 (PWR_PUCRC_PC12)
00292 #define LL_PWR_GPIO_BIT_13                 (PWR_PUCRC_PC13)
00293 #define LL_PWR_GPIO_BIT_14                 (PWR_PUCRC_PC14)
00294 #define LL_PWR_GPIO_BIT_15                 (PWR_PUCRC_PC15)
00295 #else
00296 #define LL_PWR_GPIO_BIT_0                  (PWR_PUCRA_PA0)
00297 #define LL_PWR_GPIO_BIT_1                  (PWR_PUCRA_PA1)
00298 #define LL_PWR_GPIO_BIT_2                  (PWR_PUCRA_PA2)
00299 #define LL_PWR_GPIO_BIT_3                  (PWR_PUCRA_PA3)
00300 #define LL_PWR_GPIO_BIT_4                  (PWR_PUCRA_PA4)
00301 #define LL_PWR_GPIO_BIT_5                  (PWR_PUCRA_PA5)
00302 #define LL_PWR_GPIO_BIT_6                  (PWR_PUCRA_PA6)
00303 #define LL_PWR_GPIO_BIT_7                  (PWR_PUCRA_PA7)
00304 #define LL_PWR_GPIO_BIT_8                  (PWR_PUCRA_PA8)
00305 #define LL_PWR_GPIO_BIT_9                  (PWR_PUCRA_PA9)
00306 #define LL_PWR_GPIO_BIT_10                 (PWR_PUCRA_PA10)
00307 #define LL_PWR_GPIO_BIT_11                 (PWR_PUCRA_PA11)
00308 #define LL_PWR_GPIO_BIT_12                 (PWR_PUCRA_PA12)
00309 #define LL_PWR_GPIO_BIT_13                 (PWR_PUCRA_PA13)
00310 #define LL_PWR_GPIO_BIT_14                 (PWR_PUCRC_PC14)
00311 #define LL_PWR_GPIO_BIT_15                 (PWR_PUCRC_PC15)
00312 #endif
00313 /**
00314   * @}
00315   */
00316
00317 #if defined(PWR_CR5_SMPSEN)
00318 /** @defgroup PWR_LL_EC_BOR_CONFIGURATION BOR configuration
00319   * @{
00320   */
00321 #define LL_PWR_BOR_SYSTEM_RESET            (0x00000000U)     /*!< BOR will generate a system reset  */
00322 #define LL_PWR_BOR_SMPS_FORCE_BYPASS       (PWR_CR5_BORHC)   /*!< BOR will for SMPS step down converter in bypass mode */
00323 /**
00324   * @}
00325   */
00326
00327 /** @defgroup PWR_LL_EC_SMPS_OPERATING_MODES SMPS step down converter operating modes
00328   * @{
00329   */
00330 /* Note: Literals values are defined from register SR2 bits SMPSF and SMPSBF  */
00331 /*       but they are also used as register CR5 bits SMPSEN and SMPSBEN,      */
00332 /*       as used by all SMPS operating mode functions targetting different    */
00333 /*       registers:                                                           */
00334 /*       "LL_PWR_SMPS_SetMode()", "LL_PWR_SMPS_GetMode()"                     */
00335 /*       and "LL_PWR_SMPS_GetEffectiveMode()".                                */
00336 #define LL_PWR_SMPS_BYPASS                 (PWR_SR2_SMPSBF) /*!< SMPS step down in bypass mode. */
00337 #define LL_PWR_SMPS_STEP_DOWN              (PWR_SR2_SMPSF)  /*!< SMPS step down in step down mode if system low power mode is run, LP run or stop0. If system low power mode is stop1, stop2, standby, shutdown, then SMPS is forced in mode open to preserve energy stored in decoupling capacitor as long as possible. */
00338 /**
00339   * @}
00340   */
00341
00342 /** @defgroup PWR_LL_EC_SMPS_STARTUP_CURRENT SMPS step down converter supply startup current selection
00343   * @{
00344   */
00345 #define LL_PWR_SMPS_STARTUP_CURRENT_80MA   (0x00000000U)                                            /*!< SMPS step down converter supply startup current 80mA */
00346 #define LL_PWR_SMPS_STARTUP_CURRENT_100MA  (                                      PWR_CR5_SMPSSC_0) /*!< SMPS step down converter supply startup current 100mA */
00347 #define LL_PWR_SMPS_STARTUP_CURRENT_120MA  (                   PWR_CR5_SMPSSC_1                   ) /*!< SMPS step down converter supply startup current 120mA */
00348 #define LL_PWR_SMPS_STARTUP_CURRENT_140MA  (                   PWR_CR5_SMPSSC_1 | PWR_CR5_SMPSSC_0) /*!< SMPS step down converter supply startup current 140mA */
00349 #define LL_PWR_SMPS_STARTUP_CURRENT_160MA  (PWR_CR5_SMPSSC_2                                      ) /*!< SMPS step down converter supply startup current 160mA */
00350 #define LL_PWR_SMPS_STARTUP_CURRENT_180MA  (PWR_CR5_SMPSSC_2 |                    PWR_CR5_SMPSSC_0) /*!< SMPS step down converter supply startup current 180mA */
00351 #define LL_PWR_SMPS_STARTUP_CURRENT_200MA  (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_1                   ) /*!< SMPS step down converter supply startup current 200mA */
00352 #define LL_PWR_SMPS_STARTUP_CURRENT_220MA  (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_1 | PWR_CR5_SMPSSC_0) /*!< SMPS step down converter supply startup current 220mA */
00353 /**
00354   * @}
00355   */
00356
00357 /** @defgroup PWR_LL_EC_SMPS_OUTPUT_VOLTAGE_LEVEL SMPS step down converter output voltage scaling voltage level
00358   * @{
00359   */
00360 /* Note: SMPS voltage is trimmed during device production to control
00361          the actual voltage level variation from device to device. */
00362 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V20  (0x00000000U)                                                                   /*!< SMPS step down converter supply output voltage 1.20V */
00363 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V25  (                                                            PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.25V */
00364 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V30  (                                        PWR_CR5_SMPSVOS_1                    ) /*!< SMPS step down converter supply output voltage 1.30V */
00365 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V35  (                                        PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.35V */
00366 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40  (                    PWR_CR5_SMPSVOS_2                                        ) /*!< SMPS step down converter supply output voltage 1.40V */
00367 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V45  (                    PWR_CR5_SMPSVOS_2 |                     PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.45V */
00368 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V50  (                    PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1                    ) /*!< SMPS step down converter supply output voltage 1.50V */
00369 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V55  (                    PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.55V */
00370 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V60  (PWR_CR5_SMPSVOS_3                                                            ) /*!< SMPS step down converter supply output voltage 1.60V */
00371 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V65  (PWR_CR5_SMPSVOS_3 |                                         PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.65V */
00372 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V70  (PWR_CR5_SMPSVOS_3 |                     PWR_CR5_SMPSVOS_1                    ) /*!< SMPS step down converter supply output voltage 1.70V */
00373 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V75  (PWR_CR5_SMPSVOS_3 |                     PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.75V */
00374 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V80  (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2                                        ) /*!< SMPS step down converter supply output voltage 1.80V */
00375 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V85  (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 |                     PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.85V */
00376 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V90  (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1                    ) /*!< SMPS step down converter supply output voltage 1.90V */
00377 /**
00378   * @}
00379   */
00380 #endif
00381
00382 /**
00383   * @}
00384   */
00385
00386 /* Exported macro ------------------------------------------------------------*/
00387 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
00388   * @{
00389   */
00390
00391 /** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros
00392   * @{
00393   */
00394
00395 /**
00396   * @brief  Write a value in PWR register
00397   * @param  __REG__ Register to be written
00398   * @param  __VALUE__ Value to be written in the register
00399   * @retval None
00400   */
00401 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
00402
00403 /**
00404   * @brief  Read a value in PWR register
00405   * @param  __REG__ Register to be read
00406   * @retval Register value
00407   */
00408 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
00409 /**
00410   * @}
00411   */
00412
00413 /**
00414   * @}
00415   */
00416
00417
00418 /* Exported functions --------------------------------------------------------*/
00419 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
00420   * @{
00421   */
00422
00423 /** @defgroup PWR_LL_EF_Configuration Configuration
00424   * @{
00425   */
00426
00427 /**
00428   * @brief  Switch from run main mode to run low-power mode.
00429   * @rmtoll CR1          LPR           LL_PWR_EnterLowPowerRunMode
00430   * @retval None
00431   */
00432 __STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void)
00433 {
00434   SET_BIT(PWR->CR1, PWR_CR1_LPR);
00435 }
00436
00437 /**
00438   * @brief  Switch from run main mode to low-power mode.
00439   * @rmtoll CR1          LPR           LL_PWR_ExitLowPowerRunMode
00440   * @retval None
00441   */
00442 __STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void)
00443 {
00444   CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
00445 }
00446
00447 /**
00448   * @brief  Check if the regulator is in low-power mode
00449   * @rmtoll CR1          LPR           LL_PWR_IsEnabledLowPowerRunMode
00450   * @retval State of bit (1 or 0).
00451   */
00452 __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void)
00453 {
00454   return ((READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR)) ? 1UL : 0UL);
00455 }
00456
00457 #if defined(PWR_CR1_VOS)
00458 /**
00459   * @brief  Set the main internal regulator output voltage
00460   * @note   A delay is required for the internal regulator to be ready
00461   *         after the voltage scaling has been changed.
00462   *         Check whether regulator reached the selected voltage level
00463   *         can be done using function @ref LL_PWR_IsActiveFlag_VOS().
00464   * @rmtoll CR1          VOS           LL_PWR_SetRegulVoltageScaling
00465   * @param  VoltageScaling This parameter can be one of the following values:
00466   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
00467   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
00468   * @retval None
00469   */
00470 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
00471 {
00472   MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
00473 }
00474
00475 /**
00476   * @brief  Get the main internal regulator output voltage
00477   * @rmtoll CR1          VOS           LL_PWR_GetRegulVoltageScaling
00478   * @retval Returned value can be one of the following values:
00479   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
00480   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
00481   */
00482 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
00483 {
00484   return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS));
00485 }
00486 #endif
00487
00488 /**
00489   * @brief  Enable access to the backup domain
00490   * @rmtoll CR1          DBP           LL_PWR_EnableBkUpAccess
00491   * @retval None
00492   */
00493 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
00494 {
00495   SET_BIT(PWR->CR1, PWR_CR1_DBP);
00496 }
00497
00498 /**
00499   * @brief  Disable access to the backup domain
00500   * @rmtoll CR1          DBP           LL_PWR_DisableBkUpAccess
00501   * @retval None
00502   */
00503 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
00504 {
00505   CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
00506 }
00507
00508 /**
00509   * @brief  Check if the backup domain is enabled
00510   * @rmtoll CR1          DBP           LL_PWR_IsEnabledBkUpAccess
00511   * @retval State of bit (1 or 0).
00512   */
00513 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
00514 {
00515   return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL);
00516 }
00517
00518 /**
00519   * @brief  Set Low-Power mode
00520   * @rmtoll CR1          LPMS          LL_PWR_SetPowerMode
00521   * @param  LowPowerMode This parameter can be one of the following values:
00522   *         @arg @ref LL_PWR_MODE_STOP0
00523   *         @arg @ref LL_PWR_MODE_STOP1
00524   *         @arg @ref LL_PWR_MODE_STOP2
00525   *         @arg @ref LL_PWR_MODE_STANDBY
00526   *         @arg @ref LL_PWR_MODE_SHUTDOWN
00527   * @retval None
00528   */
00529 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode)
00530 {
00531   MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode);
00532 }
00533
00534 /**
00535   * @brief  Get Low-Power mode
00536   * @rmtoll CR1          LPMS          LL_PWR_GetPowerMode
00537   * @retval Returned value can be one of the following values:
00538   *         @arg @ref LL_PWR_MODE_STOP0
00539   *         @arg @ref LL_PWR_MODE_STOP1
00540   *         @arg @ref LL_PWR_MODE_STOP2
00541   *         @arg @ref LL_PWR_MODE_STANDBY
00542   *         @arg @ref LL_PWR_MODE_SHUTDOWN
00543   */
00544 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
00545 {
00546   return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS));
00547 }
00548
00549 /**
00550   * @brief  Set flash power-down mode during low-power run mode
00551   * @rmtoll CR1          FPDR          LL_PWR_SetFlashPowerModeLPRun
00552   * @param  FlashLowPowerMode This parameter can be one of the following values:
00553   *         @arg @ref LL_PWR_FLASH_LPRUN_MODE_IDLE
00554   *         @arg @ref LL_PWR_FLASH_LPRUN_MODE_POWER_DOWN
00555   * @retval None
00556   */
00557 __STATIC_INLINE void LL_PWR_SetFlashPowerModeLPRun(uint32_t FlashLowPowerMode)
00558 {
00559   /* Unlock bit FPDR */
00560   WRITE_REG(PWR->CR1, 0x0000C1B0U);
00561
00562   /* Update bit FPDR */
00563   MODIFY_REG(PWR->CR1, PWR_CR1_FPDR, FlashLowPowerMode);
00564 }
00565
00566 /**
00567   * @brief  Get flash power-down mode during low-power run mode
00568   * @rmtoll CR1          FPDR          LL_PWR_GetFlashPowerModeLPRun
00569   * @retval Returned value can be one of the following values:
00570   *         @arg @ref LL_PWR_FLASH_LPRUN_MODE_IDLE
00571   *         @arg @ref LL_PWR_FLASH_LPRUN_MODE_POWER_DOWN
00572   */
00573 __STATIC_INLINE uint32_t LL_PWR_GetFlashPowerModeLPRun(void)
00574 {
00575   return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_FPDR));
00576 }
00577
00578 /**
00579   * @brief  Set flash power-down mode during sleep mode
00580   * @rmtoll CR1          FPDS          LL_PWR_SetFlashPowerModeSleep
00581   * @param  FlashLowPowerMode This parameter can be one of the following values:
00582   *         @arg @ref LL_PWR_FLASH_SLEEP_MODE_IDLE
00583   *         @arg @ref LL_PWR_FLASH_SLEEP_MODE_POWER_DOWN
00584   * @retval None
00585   */
00586 __STATIC_INLINE void LL_PWR_SetFlashPowerModeSleep(uint32_t FlashLowPowerMode)
00587 {
00588   MODIFY_REG(PWR->CR1, PWR_CR1_FPDS, FlashLowPowerMode);
00589 }
00590
00591 /**
00592   * @brief  Get flash power-down mode during sleep mode
00593   * @rmtoll CR1          FPDS          LL_PWR_GetFlashPowerModeSleep
00594   * @retval Returned value can be one of the following values:
00595   *         @arg @ref LL_PWR_FLASH_SLEEP_MODE_IDLE
00596   *         @arg @ref LL_PWR_FLASH_SLEEP_MODE_POWER_DOWN
00597   */
00598 __STATIC_INLINE uint32_t LL_PWR_GetFlashPowerModeSleep(void)
00599 {
00600   return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_FPDS));
00601 }
00602
00603 #if defined(PWR_CR2_PVME1)
00604 /**
00605   * @brief  Enable VDDUSB supply
00606   * @rmtoll CR2          USV           LL_PWR_EnableVddUSB
00607   * @retval None
00608   */
00609 __STATIC_INLINE void LL_PWR_EnableVddUSB(void)
00610 {
00611   SET_BIT(PWR->CR2, PWR_CR2_USV);
00612 }
00613
00614 /**
00615   * @brief  Disable VDDUSB supply
00616   * @rmtoll CR2          USV           LL_PWR_DisableVddUSB
00617   * @retval None
00618   */
00619 __STATIC_INLINE void LL_PWR_DisableVddUSB(void)
00620 {
00621   CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
00622 }
00623
00624 /**
00625   * @brief  Check if VDDUSB supply is enabled
00626   * @rmtoll CR2          USV           LL_PWR_IsEnabledVddUSB
00627   * @retval State of bit (1 or 0).
00628   */
00629 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void)
00630 {
00631   return ((READ_BIT(PWR->CR2, PWR_CR2_USV) == (PWR_CR2_USV)) ? 1UL : 0UL);
00632 }
00633 #endif
00634
00635 /**
00636   * @brief  Enable the Power Voltage Monitoring on a peripheral
00637   * @rmtoll CR2          PVME1         LL_PWR_EnablePVM\n
00638   *         CR2          PVME3         LL_PWR_EnablePVM
00639   * @param  PeriphVoltage This parameter can be one of the following values:
00640   *         @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*)
00641   *         @arg @ref LL_PWR_PVM_VDDA_1_62V
00642   *
00643   *         (*) Not available on devices STM32WB50xx
00644   * @retval None
00645   */
00646 __STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage)
00647 {
00648   SET_BIT(PWR->CR2, PeriphVoltage);
00649 }
00650
00651 /**
00652   * @brief  Disable the Power Voltage Monitoring on a peripheral
00653   * @rmtoll CR2          PVME1         LL_PWR_DisablePVM\n
00654   *         CR2          PVME3         LL_PWR_DisablePVM
00655   * @param  PeriphVoltage This parameter can be one of the following values:
00656   *         @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*)
00657   *         @arg @ref LL_PWR_PVM_VDDA_1_62V
00658   *
00659   *         (*) Not available on devices STM32WB50xx
00660   * @retval None
00661   */
00662 __STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage)
00663 {
00664   CLEAR_BIT(PWR->CR2, PeriphVoltage);
00665 }
00666
00667 /**
00668   * @brief  Check if Power Voltage Monitoring is enabled on a peripheral
00669   * @rmtoll CR2          PVME1         LL_PWR_IsEnabledPVM\n
00670   *         CR2          PVME3         LL_PWR_IsEnabledPVM
00671   * @param  PeriphVoltage This parameter can be one of the following values:
00672   *         @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*)
00673   *         @arg @ref LL_PWR_PVM_VDDA_1_62V
00674   *
00675   *         (*) Not available on devices STM32WB50xx
00676   * @retval State of bit (1 or 0).
00677   */
00678 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)
00679 {
00680   return ((READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage)) ? 1UL : 0UL);
00681 }
00682
00683 /**
00684   * @brief  Configure the voltage threshold detected by the Power Voltage Detector
00685   * @rmtoll CR2          PLS           LL_PWR_SetPVDLevel
00686   * @param  PVDLevel This parameter can be one of the following values:
00687   *         @arg @ref LL_PWR_PVDLEVEL_0
00688   *         @arg @ref LL_PWR_PVDLEVEL_1
00689   *         @arg @ref LL_PWR_PVDLEVEL_2
00690   *         @arg @ref LL_PWR_PVDLEVEL_3
00691   *         @arg @ref LL_PWR_PVDLEVEL_4
00692   *         @arg @ref LL_PWR_PVDLEVEL_5
00693   *         @arg @ref LL_PWR_PVDLEVEL_6
00694   *         @arg @ref LL_PWR_PVDLEVEL_7
00695   * @retval None
00696   */
00697 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
00698 {
00699   MODIFY_REG(PWR->CR2, PWR_CR2_PLS, PVDLevel);
00700 }
00701
00702 /**
00703   * @brief  Get the voltage threshold detection
00704   * @rmtoll CR2          PLS           LL_PWR_GetPVDLevel
00705   * @retval Returned value can be one of the following values:
00706   *         @arg @ref LL_PWR_PVDLEVEL_0
00707   *         @arg @ref LL_PWR_PVDLEVEL_1
00708   *         @arg @ref LL_PWR_PVDLEVEL_2
00709   *         @arg @ref LL_PWR_PVDLEVEL_3
00710   *         @arg @ref LL_PWR_PVDLEVEL_4
00711   *         @arg @ref LL_PWR_PVDLEVEL_5
00712   *         @arg @ref LL_PWR_PVDLEVEL_6
00713   *         @arg @ref LL_PWR_PVDLEVEL_7
00714   */
00715 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
00716 {
00717   return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PLS));
00718 }
00719
00720 /**
00721   * @brief  Enable Power Voltage Detector
00722   * @rmtoll CR2          PVDE          LL_PWR_EnablePVD
00723   * @retval None
00724   */
00725 __STATIC_INLINE void LL_PWR_EnablePVD(void)
00726 {
00727   SET_BIT(PWR->CR2, PWR_CR2_PVDE);
00728 }
00729
00730 /**
00731   * @brief  Disable Power Voltage Detector
00732   * @rmtoll CR2          PVDE          LL_PWR_DisablePVD
00733   * @retval None
00734   */
00735 __STATIC_INLINE void LL_PWR_DisablePVD(void)
00736 {
00737   CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
00738 }
00739
00740 /**
00741   * @brief  Check if Power Voltage Detector is enabled
00742   * @rmtoll CR2          PVDE          LL_PWR_IsEnabledPVD
00743   * @retval State of bit (1 or 0).
00744   */
00745 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
00746 {
00747   return ((READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)) ? 1UL : 0UL);
00748 }
00749
00750 /**
00751   * @brief  Enable Internal Wake-up line
00752   * @rmtoll CR3          EIWF          LL_PWR_EnableInternWU
00753   * @retval None
00754   */
00755 __STATIC_INLINE void LL_PWR_EnableInternWU(void)
00756 {
00757   SET_BIT(PWR->CR3, PWR_CR3_EIWUL);
00758 }
00759
00760 /**
00761   * @brief  Disable Internal Wake-up line
00762   * @rmtoll CR3          EIWF          LL_PWR_DisableInternWU
00763   * @retval None
00764   */
00765 __STATIC_INLINE void LL_PWR_DisableInternWU(void)
00766 {
00767   CLEAR_BIT(PWR->CR3, PWR_CR3_EIWUL);
00768 }
00769
00770 /**
00771   * @brief  Check if Internal Wake-up line is enabled
00772   * @rmtoll CR3          EIWF          LL_PWR_IsEnabledInternWU
00773   * @retval State of bit (1 or 0).
00774   */
00775 __STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void)
00776 {
00777   return ((READ_BIT(PWR->CR3, PWR_CR3_EIWUL) == (PWR_CR3_EIWUL)) ? 1UL : 0UL);
00778 }
00779
00780 /**
00781   * @brief  Enable pull-up and pull-down configuration
00782   * @rmtoll CR3          APC           LL_PWR_EnablePUPDCfg
00783   * @retval None
00784   */
00785 __STATIC_INLINE void LL_PWR_EnablePUPDCfg(void)
00786 {
00787   SET_BIT(PWR->CR3, PWR_CR3_APC);
00788 }
00789
00790 /**
00791   * @brief  Disable pull-up and pull-down configuration
00792   * @rmtoll CR3          APC           LL_PWR_DisablePUPDCfg
00793   * @retval None
00794   */
00795 __STATIC_INLINE void LL_PWR_DisablePUPDCfg(void)
00796 {
00797   CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
00798 }
00799
00800 /**
00801   * @brief  Check if pull-up and pull-down configuration is enabled
00802   * @rmtoll CR3          APC           LL_PWR_IsEnabledPUPDCfg
00803   * @retval State of bit (1 or 0).
00804   */
00805 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void)
00806 {
00807   return ((READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC)) ? 1UL : 0UL);
00808 }
00809
00810 /**
00811   * @brief  Enable SRAM2 content retention in Standby mode
00812   * @rmtoll CR3          RRS           LL_PWR_EnableSRAM2Retention
00813   * @retval None
00814   */
00815 __STATIC_INLINE void LL_PWR_EnableSRAM2Retention(void)
00816 {
00817   SET_BIT(PWR->CR3, PWR_CR3_RRS);
00818 }
00819
00820 /**
00821   * @brief  Disable SRAM2 content retention in Standby mode
00822   * @rmtoll CR3          RRS           LL_PWR_DisableSRAM2Retention
00823   * @retval None
00824   */
00825 __STATIC_INLINE void LL_PWR_DisableSRAM2Retention(void)
00826 {
00827   CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
00828 }
00829
00830 /**
00831   * @brief  Check if SRAM2 content retention in Standby mode  is enabled
00832   * @rmtoll CR3          RRS           LL_PWR_IsEnabledSRAM2Retention
00833   * @retval State of bit (1 or 0).
00834   */
00835 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Retention(void)
00836 {
00837   return ((READ_BIT(PWR->CR3, PWR_CR3_RRS) == (PWR_CR3_RRS)) ? 1UL : 0UL);
00838 }
00839
00840 /**
00841   * @brief  Enable the WakeUp PINx functionality
00842   * @rmtoll CR3          EWUP1         LL_PWR_EnableWakeUpPin\n
00843   *         CR3          EWUP2         LL_PWR_EnableWakeUpPin\n
00844   *         CR3          EWUP3         LL_PWR_EnableWakeUpPin\n
00845   *         CR3          EWUP4         LL_PWR_EnableWakeUpPin\n
00846   *         CR3          EWUP5         LL_PWR_EnableWakeUpPin\n
00847   * @param  WakeUpPin This parameter can be one of the following values:
00848   *         @arg @ref LL_PWR_WAKEUP_PIN1
00849   *         @arg @ref LL_PWR_WAKEUP_PIN2 (*)
00850   *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
00851   *         @arg @ref LL_PWR_WAKEUP_PIN4
00852   *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
00853   *
00854   *         (*) Not available on devices STM32WB50xx
00855   * @retval None
00856   */
00857 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
00858 {
00859   SET_BIT(PWR->CR3, WakeUpPin);
00860 }
00861
00862 /**
00863   * @brief  Disable the WakeUp PINx functionality
00864   * @rmtoll CR3          EWUP1         LL_PWR_DisableWakeUpPin\n
00865   *         CR3          EWUP2         LL_PWR_DisableWakeUpPin\n
00866   *         CR3          EWUP3         LL_PWR_DisableWakeUpPin\n
00867   *         CR3          EWUP4         LL_PWR_DisableWakeUpPin\n
00868   *         CR3          EWUP5         LL_PWR_DisableWakeUpPin\n
00869   * @param  WakeUpPin This parameter can be one of the following values:
00870   *         @arg @ref LL_PWR_WAKEUP_PIN1
00871   *         @arg @ref LL_PWR_WAKEUP_PIN2 (*)
00872   *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
00873   *         @arg @ref LL_PWR_WAKEUP_PIN4
00874   *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
00875   *
00876   *         (*) Not available on devices STM32WB50xx
00877   * @retval None
00878   */
00879 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
00880 {
00881   CLEAR_BIT(PWR->CR3, WakeUpPin);
00882 }
00883
00884 /**
00885   * @brief  Check if the WakeUp PINx functionality is enabled
00886   * @rmtoll CR3          EWUP1         LL_PWR_IsEnabledWakeUpPin\n
00887   *         CR3          EWUP2         LL_PWR_IsEnabledWakeUpPin\n
00888   *         CR3          EWUP3         LL_PWR_IsEnabledWakeUpPin\n
00889   *         CR3          EWUP4         LL_PWR_IsEnabledWakeUpPin\n
00890   *         CR3          EWUP5         LL_PWR_IsEnabledWakeUpPin\n
00891   * @param  WakeUpPin This parameter can be one of the following values:
00892   *         @arg @ref LL_PWR_WAKEUP_PIN1
00893   *         @arg @ref LL_PWR_WAKEUP_PIN2 (*)
00894   *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
00895   *         @arg @ref LL_PWR_WAKEUP_PIN4
00896   *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
00897   *
00898   *         (*) Not available on devices STM32WB50xx
00899   * @retval State of bit (1 or 0).
00900   */
00901 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
00902 {
00903   return ((READ_BIT(PWR->CR3, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
00904 }
00905
00906 /**
00907   * @brief  Set the resistor impedance
00908   * @rmtoll CR4          VBRS          LL_PWR_SetBattChargResistor
00909   * @param  Resistor This parameter can be one of the following values:
00910   *         @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
00911   *         @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
00912   * @retval None
00913   */
00914 __STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
00915 {
00916   MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor);
00917 }
00918
00919 /**
00920   * @brief  Get the resistor impedance
00921   * @rmtoll CR4          VBRS          LL_PWR_GetBattChargResistor
00922   * @retval Returned value can be one of the following values:
00923   *         @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
00924   *         @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
00925   */
00926 __STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
00927 {
00928   return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS));
00929 }
00930
00931 /**
00932   * @brief  Enable battery charging
00933   * @rmtoll CR4          VBE           LL_PWR_EnableBatteryCharging
00934   * @retval None
00935   */
00936 __STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
00937 {
00938   SET_BIT(PWR->CR4, PWR_CR4_VBE);
00939 }
00940
00941 /**
00942   * @brief  Disable battery charging
00943   * @rmtoll CR4          VBE           LL_PWR_DisableBatteryCharging
00944   * @retval None
00945   */
00946 __STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
00947 {
00948   CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
00949 }
00950
00951 /**
00952   * @brief  Check if battery charging is enabled
00953   * @rmtoll CR4          VBE           LL_PWR_IsEnabledBatteryCharging
00954   * @retval State of bit (1 or 0).
00955   */
00956 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
00957 {
00958   return ((READ_BIT(PWR->CR4, PWR_CR4_VBE) == (PWR_CR4_VBE)) ? 1UL : 0UL);
00959 }
00960
00961 /**
00962   * @brief  Set the Wake-Up pin polarity low for the event detection
00963   * @rmtoll CR4          WP1           LL_PWR_SetWakeUpPinPolarityLow\n
00964   *         CR4          WP2           LL_PWR_SetWakeUpPinPolarityLow\n
00965   *         CR4          WP3           LL_PWR_SetWakeUpPinPolarityLow\n
00966   *         CR4          WP4           LL_PWR_SetWakeUpPinPolarityLow\n
00967   *         CR4          WP5           LL_PWR_SetWakeUpPinPolarityLow
00968   * @param  WakeUpPin This parameter can be one of the following values:
00969   *         @arg @ref LL_PWR_WAKEUP_PIN1
00970   *         @arg @ref LL_PWR_WAKEUP_PIN2 (*)
00971   *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
00972   *         @arg @ref LL_PWR_WAKEUP_PIN4
00973   *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
00974   *
00975   *         (*) Not available on devices STM32WB50xx
00976   * @retval None
00977   */
00978 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
00979 {
00980   SET_BIT(PWR->CR4, WakeUpPin);
00981 }
00982
00983 /**
00984   * @brief  Set the Wake-Up pin polarity high for the event detection
00985   * @rmtoll CR4          WP1           LL_PWR_SetWakeUpPinPolarityHigh\n
00986   *         CR4          WP2           LL_PWR_SetWakeUpPinPolarityHigh\n
00987   *         CR4          WP3           LL_PWR_SetWakeUpPinPolarityHigh\n
00988   *         CR4          WP4           LL_PWR_SetWakeUpPinPolarityHigh\n
00989   *         CR4          WP5           LL_PWR_SetWakeUpPinPolarityHigh
00990   * @param  WakeUpPin This parameter can be one of the following values:
00991   *         @arg @ref LL_PWR_WAKEUP_PIN1
00992   *         @arg @ref LL_PWR_WAKEUP_PIN2 (*)
00993   *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
00994   *         @arg @ref LL_PWR_WAKEUP_PIN4
00995   *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
00996   *
00997   *         (*) Not available on devices STM32WB50xx
00998   * @retval None
00999   */
01000 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
01001 {
01002   CLEAR_BIT(PWR->CR4, WakeUpPin);
01003 }
01004
01005 /**
01006   * @brief  Get the Wake-Up pin polarity for the event detection
01007   * @rmtoll CR4          WP1           LL_PWR_IsWakeUpPinPolarityLow\n
01008   *         CR4          WP2           LL_PWR_IsWakeUpPinPolarityLow\n
01009   *         CR4          WP3           LL_PWR_IsWakeUpPinPolarityLow\n
01010   *         CR4          WP4           LL_PWR_IsWakeUpPinPolarityLow\n
01011   *         CR4          WP5           LL_PWR_IsWakeUpPinPolarityLow
01012   * @param  WakeUpPin This parameter can be one of the following values:
01013   *         @arg @ref LL_PWR_WAKEUP_PIN1
01014   *         @arg @ref LL_PWR_WAKEUP_PIN2 (*)
01015   *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
01016   *         @arg @ref LL_PWR_WAKEUP_PIN4
01017   *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
01018   *
01019   *         (*) Not available on devices STM32WB50xx
01020   * @retval State of bit (1 or 0).
01021   */
01022 __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
01023 {
01024   return ((READ_BIT(PWR->CR4, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
01025 }
01026
01027 /**
01028   * @brief  Enable GPIO pull-up state in Standby and Shutdown modes
01029   * @note   Some pins are not configurable for pulling in Standby and Shutdown
01030   *         modes. Refer to reference manual for available pins and ports.
01031   * @rmtoll PUCRA        PU0-15        LL_PWR_EnableGPIOPullUp\n
01032   *         PUCRB        PU0-15        LL_PWR_EnableGPIOPullUp\n
01033   *         PUCRC        PU0-15        LL_PWR_EnableGPIOPullUp\n
01034   *         PUCRD        PU0-15        LL_PWR_EnableGPIOPullUp\n
01035   *         PUCRE        PU0-15        LL_PWR_EnableGPIOPullUp\n
01036   *         PUCRH        PU0-15        LL_PWR_EnableGPIOPullUp
01037   * @param  GPIO This parameter can be one of the following values:
01038   *         @arg @ref LL_PWR_GPIO_A
01039   *         @arg @ref LL_PWR_GPIO_B
01040   *         @arg @ref LL_PWR_GPIO_C
01041   *         @arg @ref LL_PWR_GPIO_D
01042   *         @arg @ref LL_PWR_GPIO_E
01043   *         @arg @ref LL_PWR_GPIO_H
01044   * @param  GPIONumber This parameter can be one of the following values:
01045   *         @arg @ref LL_PWR_GPIO_BIT_0
01046   *         @arg @ref LL_PWR_GPIO_BIT_1
01047   *         @arg @ref LL_PWR_GPIO_BIT_2
01048   *         @arg @ref LL_PWR_GPIO_BIT_3
01049   *         @arg @ref LL_PWR_GPIO_BIT_4
01050   *         @arg @ref LL_PWR_GPIO_BIT_5
01051   *         @arg @ref LL_PWR_GPIO_BIT_6
01052   *         @arg @ref LL_PWR_GPIO_BIT_7
01053   *         @arg @ref LL_PWR_GPIO_BIT_8
01054   *         @arg @ref LL_PWR_GPIO_BIT_9
01055   *         @arg @ref LL_PWR_GPIO_BIT_10
01056   *         @arg @ref LL_PWR_GPIO_BIT_11
01057   *         @arg @ref LL_PWR_GPIO_BIT_12
01058   *         @arg @ref LL_PWR_GPIO_BIT_13
01059   *         @arg @ref LL_PWR_GPIO_BIT_14
01060   *         @arg @ref LL_PWR_GPIO_BIT_15
01061   * @retval None
01062   */
01063 __STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
01064 {
01065   SET_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
01066 }
01067
01068 /**
01069   * @brief  Disable GPIO pull-up state in Standby and Shutdown modes
01070   * @note   Some pins are not configurable for pulling in Standby and Shutdown
01071   *         modes. Refer to reference manual for available pins and ports.
01072   * @rmtoll PUCRA        PU0-15        LL_PWR_DisableGPIOPullUp\n
01073   *         PUCRB        PU0-15        LL_PWR_DisableGPIOPullUp\n
01074   *         PUCRC        PU0-15        LL_PWR_DisableGPIOPullUp\n
01075   *         PUCRD        PU0-15        LL_PWR_DisableGPIOPullUp\n
01076   *         PUCRE        PU0-15        LL_PWR_DisableGPIOPullUp\n
01077   *         PUCRH        PU0-15        LL_PWR_DisableGPIOPullUp
01078   * @param  GPIO This parameter can be one of the following values:
01079   *         @arg @ref LL_PWR_GPIO_A
01080   *         @arg @ref LL_PWR_GPIO_B
01081   *         @arg @ref LL_PWR_GPIO_C
01082   *         @arg @ref LL_PWR_GPIO_D
01083   *         @arg @ref LL_PWR_GPIO_E
01084   *         @arg @ref LL_PWR_GPIO_H
01085   * @param  GPIONumber This parameter can be one of the following values:
01086   *         @arg @ref LL_PWR_GPIO_BIT_0
01087   *         @arg @ref LL_PWR_GPIO_BIT_1
01088   *         @arg @ref LL_PWR_GPIO_BIT_2
01089   *         @arg @ref LL_PWR_GPIO_BIT_3
01090   *         @arg @ref LL_PWR_GPIO_BIT_4
01091   *         @arg @ref LL_PWR_GPIO_BIT_5
01092   *         @arg @ref LL_PWR_GPIO_BIT_6
01093   *         @arg @ref LL_PWR_GPIO_BIT_7
01094   *         @arg @ref LL_PWR_GPIO_BIT_8
01095   *         @arg @ref LL_PWR_GPIO_BIT_9
01096   *         @arg @ref LL_PWR_GPIO_BIT_10
01097   *         @arg @ref LL_PWR_GPIO_BIT_11
01098   *         @arg @ref LL_PWR_GPIO_BIT_12
01099   *         @arg @ref LL_PWR_GPIO_BIT_13
01100   *         @arg @ref LL_PWR_GPIO_BIT_14
01101   *         @arg @ref LL_PWR_GPIO_BIT_15
01102   * @retval None
01103   */
01104 __STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
01105 {
01106   CLEAR_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
01107 }
01108
01109 /**
01110   * @brief  Check if GPIO pull-up state is enabled
01111   * @rmtoll PUCRA        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
01112   *         PUCRB        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
01113   *         PUCRC        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
01114   *         PUCRD        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
01115   *         PUCRE        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
01116   *         PUCRH        PU0-15        LL_PWR_IsEnabledGPIOPullUp
01117   * @param  GPIO This parameter can be one of the following values:
01118   *         @arg @ref LL_PWR_GPIO_A
01119   *         @arg @ref LL_PWR_GPIO_B
01120   *         @arg @ref LL_PWR_GPIO_C
01121   *         @arg @ref LL_PWR_GPIO_D
01122   *         @arg @ref LL_PWR_GPIO_E
01123   *         @arg @ref LL_PWR_GPIO_H
01124   * @param  GPIONumber This parameter can be one of the following values:
01125   *         @arg @ref LL_PWR_GPIO_BIT_0
01126   *         @arg @ref LL_PWR_GPIO_BIT_1
01127   *         @arg @ref LL_PWR_GPIO_BIT_2
01128   *         @arg @ref LL_PWR_GPIO_BIT_3
01129   *         @arg @ref LL_PWR_GPIO_BIT_4
01130   *         @arg @ref LL_PWR_GPIO_BIT_5
01131   *         @arg @ref LL_PWR_GPIO_BIT_6
01132   *         @arg @ref LL_PWR_GPIO_BIT_7
01133   *         @arg @ref LL_PWR_GPIO_BIT_8
01134   *         @arg @ref LL_PWR_GPIO_BIT_9
01135   *         @arg @ref LL_PWR_GPIO_BIT_10
01136   *         @arg @ref LL_PWR_GPIO_BIT_11
01137   *         @arg @ref LL_PWR_GPIO_BIT_12
01138   *         @arg @ref LL_PWR_GPIO_BIT_13
01139   *         @arg @ref LL_PWR_GPIO_BIT_14
01140   *         @arg @ref LL_PWR_GPIO_BIT_15
01141   * @retval State of bit (1 or 0).
01142   */
01143 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
01144 {
01145   return ((READ_BIT(*((__IO uint32_t *)GPIO), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
01146 }
01147
01148 /**
01149   * @brief  Enable GPIO pull-down state in Standby and Shutdown modes
01150   * @note   Some pins are not configurable for pulling in Standby and Shutdown
01151   *         modes. Refer to reference manual for available pins and ports.
01152   * @rmtoll PDCRA        PD0-15        LL_PWR_EnableGPIOPullDown\n
01153   *         PDCRB        PD0-15        LL_PWR_EnableGPIOPullDown\n
01154   *         PDCRC        PD0-15        LL_PWR_EnableGPIOPullDown\n
01155   *         PDCRD        PD0-15        LL_PWR_EnableGPIOPullDown\n
01156   *         PDCRE        PD0-15        LL_PWR_EnableGPIOPullDown\n
01157   *         PDCRH        PD0-15        LL_PWR_EnableGPIOPullDown
01158   * @param  GPIO This parameter can be one of the following values:
01159   *         @arg @ref LL_PWR_GPIO_A
01160   *         @arg @ref LL_PWR_GPIO_B
01161   *         @arg @ref LL_PWR_GPIO_C
01162   *         @arg @ref LL_PWR_GPIO_D
01163   *         @arg @ref LL_PWR_GPIO_E
01164   *         @arg @ref LL_PWR_GPIO_H
01165   * @param  GPIONumber This parameter can be one of the following values:
01166   *         @arg @ref LL_PWR_GPIO_BIT_0
01167   *         @arg @ref LL_PWR_GPIO_BIT_1
01168   *         @arg @ref LL_PWR_GPIO_BIT_2
01169   *         @arg @ref LL_PWR_GPIO_BIT_3
01170   *         @arg @ref LL_PWR_GPIO_BIT_4
01171   *         @arg @ref LL_PWR_GPIO_BIT_5
01172   *         @arg @ref LL_PWR_GPIO_BIT_6
01173   *         @arg @ref LL_PWR_GPIO_BIT_7
01174   *         @arg @ref LL_PWR_GPIO_BIT_8
01175   *         @arg @ref LL_PWR_GPIO_BIT_9
01176   *         @arg @ref LL_PWR_GPIO_BIT_10
01177   *         @arg @ref LL_PWR_GPIO_BIT_11
01178   *         @arg @ref LL_PWR_GPIO_BIT_12
01179   *         @arg @ref LL_PWR_GPIO_BIT_13
01180   *         @arg @ref LL_PWR_GPIO_BIT_14
01181   *         @arg @ref LL_PWR_GPIO_BIT_15
01182   * @retval None
01183   */
01184 __STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
01185 {
01186   SET_BIT(*((__IO uint32_t *)(GPIO + 4UL)), GPIONumber);
01187 }
01188
01189 /**
01190   * @brief  Disable GPIO pull-down state in Standby and Shutdown modes
01191   * @note   Some pins are not configurable for pulling in Standby and Shutdown
01192   *         modes. Refer to reference manual for available pins and ports.
01193   * @rmtoll PDCRA        PD0-15        LL_PWR_DisableGPIOPullDown\n
01194   *         PDCRB        PD0-15        LL_PWR_DisableGPIOPullDown\n
01195   *         PDCRC        PD0-15        LL_PWR_DisableGPIOPullDown\n
01196   *         PDCRD        PD0-15        LL_PWR_DisableGPIOPullDown\n
01197   *         PDCRE        PD0-15        LL_PWR_DisableGPIOPullDown\n
01198   *         PDCRH        PD0-15        LL_PWR_DisableGPIOPullDown
01199   * @param  GPIO This parameter can be one of the following values:
01200   *         @arg @ref LL_PWR_GPIO_A
01201   *         @arg @ref LL_PWR_GPIO_B
01202   *         @arg @ref LL_PWR_GPIO_C
01203   *         @arg @ref LL_PWR_GPIO_D
01204   *         @arg @ref LL_PWR_GPIO_E
01205   *         @arg @ref LL_PWR_GPIO_H
01206   * @param  GPIONumber This parameter can be one of the following values:
01207   *         @arg @ref LL_PWR_GPIO_BIT_0
01208   *         @arg @ref LL_PWR_GPIO_BIT_1
01209   *         @arg @ref LL_PWR_GPIO_BIT_2
01210   *         @arg @ref LL_PWR_GPIO_BIT_3
01211   *         @arg @ref LL_PWR_GPIO_BIT_4
01212   *         @arg @ref LL_PWR_GPIO_BIT_5
01213   *         @arg @ref LL_PWR_GPIO_BIT_6
01214   *         @arg @ref LL_PWR_GPIO_BIT_7
01215   *         @arg @ref LL_PWR_GPIO_BIT_8
01216   *         @arg @ref LL_PWR_GPIO_BIT_9
01217   *         @arg @ref LL_PWR_GPIO_BIT_10
01218   *         @arg @ref LL_PWR_GPIO_BIT_11
01219   *         @arg @ref LL_PWR_GPIO_BIT_12
01220   *         @arg @ref LL_PWR_GPIO_BIT_13
01221   *         @arg @ref LL_PWR_GPIO_BIT_14
01222   *         @arg @ref LL_PWR_GPIO_BIT_15
01223   * @retval None
01224   */
01225 __STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
01226 {
01227   CLEAR_BIT(*((__IO uint32_t *)(GPIO + 4UL)), GPIONumber);
01228 }
01229
01230 /**
01231   * @brief  Check if GPIO pull-down state is enabled
01232   * @rmtoll PDCRA        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
01233   *         PDCRB        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
01234   *         PDCRC        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
01235   *         PDCRD        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
01236   *         PDCRE        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
01237   *         PDCRH        PD0-15        LL_PWR_IsEnabledGPIOPullDown
01238   * @param  GPIO This parameter can be one of the following values:
01239   *         @arg @ref LL_PWR_GPIO_A
01240   *         @arg @ref LL_PWR_GPIO_B
01241   *         @arg @ref LL_PWR_GPIO_C
01242   *         @arg @ref LL_PWR_GPIO_D
01243   *         @arg @ref LL_PWR_GPIO_E
01244   *         @arg @ref LL_PWR_GPIO_H
01245   * @param  GPIONumber This parameter can be one of the following values:
01246   *         @arg @ref LL_PWR_GPIO_BIT_0
01247   *         @arg @ref LL_PWR_GPIO_BIT_1
01248   *         @arg @ref LL_PWR_GPIO_BIT_2
01249   *         @arg @ref LL_PWR_GPIO_BIT_3
01250   *         @arg @ref LL_PWR_GPIO_BIT_4
01251   *         @arg @ref LL_PWR_GPIO_BIT_5
01252   *         @arg @ref LL_PWR_GPIO_BIT_6
01253   *         @arg @ref LL_PWR_GPIO_BIT_7
01254   *         @arg @ref LL_PWR_GPIO_BIT_8
01255   *         @arg @ref LL_PWR_GPIO_BIT_9
01256   *         @arg @ref LL_PWR_GPIO_BIT_10
01257   *         @arg @ref LL_PWR_GPIO_BIT_11
01258   *         @arg @ref LL_PWR_GPIO_BIT_12
01259   *         @arg @ref LL_PWR_GPIO_BIT_13
01260   *         @arg @ref LL_PWR_GPIO_BIT_14
01261   *         @arg @ref LL_PWR_GPIO_BIT_15
01262   * @retval State of bit (1 or 0).
01263   */
01264 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
01265 {
01266   return ((READ_BIT(*((__IO uint32_t *)(GPIO + 4UL)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
01267 }
01268
01269 #if defined(PWR_CR5_SMPSEN)
01270 /**
01271   * @brief  Set BOR configuration
01272   * @rmtoll CR5          BORHC         LL_PWR_SetBORConfig
01273   * @param  BORConfiguration This parameter can be one of the following values:
01274   *         @arg @ref LL_PWR_BOR_SYSTEM_RESET
01275   *         @arg @ref LL_PWR_BOR_SMPS_FORCE_BYPASS
01276   */
01277 __STATIC_INLINE void LL_PWR_SetBORConfig(uint32_t BORConfiguration)
01278 {
01279   MODIFY_REG(PWR->CR5, PWR_CR5_BORHC, BORConfiguration);
01280 }
01281
01282 /**
01283   * @brief  Get BOR configuration
01284   * @rmtoll CR5          BORHC         LL_PWR_GetBORConfig
01285   * @retval Returned value can be one of the following values:
01286   *         @arg @ref LL_PWR_BOR_SYSTEM_RESET
01287   *         @arg @ref LL_PWR_BOR_SMPS_FORCE_BYPASS
01288   */
01289 __STATIC_INLINE uint32_t LL_PWR_GetBORConfig(void)
01290 {
01291   return (uint32_t)(READ_BIT(PWR->CR5, PWR_CR5_BORHC));
01292 }
01293 #endif
01294
01295 /**
01296   * @}
01297   */
01298
01299 #if defined(PWR_CR5_SMPSEN)
01300 /** @defgroup PWR_LL_EF_Configuration_SMPS Configuration of SMPS
01301   * @{
01302   */
01303
01304 /**
01305   * @brief  Set SMPS operating mode
01306   * @note   When SMPS step down converter SMPS mode is enabled,
01307   *         it is good practice to enable the BORH to monitor the supply:
01308   *         in this case, when the supply drops below the SMPS step down
01309   *         converter SMPS mode operating supply level,
01310   *         switching on the fly is performed automaticcaly
01311   *         and interruption is generated.
01312   *         Refer to function @ref LL_PWR_SetBORConfig().
01313   * @note   Occurence of SMPS step down converter forced in bypass mode
01314   *         can be monitored by flag and interruption.
01315   *         Refer to functions
01316   *         @ref LL_PWR_IsActiveFlag_SMPSFB(), @ref LL_PWR_ClearFlag_SMPSFB(),
01317   *         @ref LL_PWR_EnableIT_BORH_SMPSFB().
01318   * @rmtoll CR5          SMPSEN        LL_PWR_SMPS_SetMode \n
01319   *         CR5          SMPSBEN       LL_PWR_SMPS_SetMode
01320   * @param  OperatingMode This parameter can be one of the following values:
01321   *         @arg @ref LL_PWR_SMPS_BYPASS
01322   *         @arg @ref LL_PWR_SMPS_STEP_DOWN (1)
01323   *
01324   *         (1) SMPS operating mode step down or open depends on system low-power mode:
01325   *              - step down mode if system low power mode is run, LP run or stop0,
01326   *              - open mode if system low power mode is stop1, stop2, standby or shutdown
01327   * @retval None
01328   */
01329 __STATIC_INLINE void LL_PWR_SMPS_SetMode(uint32_t OperatingMode)
01330 {
01331   /* Note: Operation on bits performed to keep compatibility of literals      */
01332   /*       for all SMPS operating mode functions:                             */
01333   /*       "LL_PWR_SMPS_SetMode()", "LL_PWR_SMPS_GetMode()"                   */
01334   /*       and "LL_PWR_SMPS_GetEffectiveMode()".                              */
01335   MODIFY_REG(PWR->CR5, PWR_CR5_SMPSEN, (OperatingMode & PWR_SR2_SMPSF) << (PWR_CR5_SMPSEN_Pos - PWR_SR2_SMPSF_Pos));
01336 }
01337
01338 /**
01339   * @brief  Get SMPS operating mode
01340   * @rmtoll CR5          SMPSEN        LL_PWR_SMPS_GetMode \n
01341   *         CR5          SMPSBEN       LL_PWR_SMPS_GetMode
01342   * @retval Returned value can be one of the following values:
01343   *         @arg @ref LL_PWR_SMPS_BYPASS
01344   *         @arg @ref LL_PWR_SMPS_STEP_DOWN (1)
01345   *
01346   *         (1) SMPS operating mode step down or open depends on system low-power mode:
01347   *              - step down mode if system low power mode is run, LP run or stop0,
01348   *              - open mode if system low power mode is stop1, stop2, standby or shutdown
01349   */
01350 __STATIC_INLINE uint32_t LL_PWR_SMPS_GetMode(void)
01351 {
01352   /* Note: Operation on bits performed to keep compatibility of literals      */
01353   /*       for all SMPS operating mode functions:                             */
01354   /*       "LL_PWR_SMPS_SetMode()", "LL_PWR_SMPS_GetMode()"                   */
01355   /*       and "LL_PWR_SMPS_GetEffectiveMode()".                              */
01356   register uint32_t OperatingMode = (READ_BIT(PWR->CR5, PWR_CR5_SMPSEN) >> (PWR_CR5_SMPSEN_Pos - PWR_SR2_SMPSF_Pos));
01357
01358   OperatingMode = (OperatingMode | ((~OperatingMode >> 1U) & PWR_SR2_SMPSBF));
01359
01360   return OperatingMode;
01361 }
01362
01363 /**
01364   * @brief  Get SMPS effective operating mode
01365   * @note   SMPS operating mode can be changed by hardware, therefore
01366   *         requested operating mode can differ from effective low power mode.
01367   *         - dependency on system low-power mode:
01368   *           - step down mode if system low power mode is run, LP run or stop0,
01369   *           - open mode if system low power mode is stop1, stop2, standby or shutdown
01370   *         - dependency on BOR level:
01371   *           - bypass mode if supply voltage drops below BOR level
01372   * @note   This functions check flags of SMPS operating modes step down
01373   *         and bypass. If the SMPS is not among these 2 operating modes,
01374   *         then it can be in mode off or open.
01375   * @rmtoll SR2          SMPSF         LL_PWR_SMPS_GetEffectiveMode \n
01376   *         SR2          SMPSBF        LL_PWR_SMPS_GetEffectiveMode
01377   * @retval Returned value can be one of the following values:
01378   *         @arg @ref LL_PWR_SMPS_BYPASS
01379   *         @arg @ref LL_PWR_SMPS_STEP_DOWN (1)
01380   *
01381   *         (1) SMPS operating mode step down or open depends on system low-power mode:
01382   *              - step down mode if system low power mode is run, LP run or stop0,
01383   *              - open mode if system low power mode is stop1, stop2, standby or shutdown
01384   */
01385 __STATIC_INLINE uint32_t LL_PWR_SMPS_GetEffectiveMode(void)
01386 {
01387   return (uint32_t)(READ_BIT(PWR->SR2, (PWR_SR2_SMPSF | PWR_SR2_SMPSBF)));
01388 }
01389
01390 /**
01391   * @brief  SMPS step down converter enable
01392   * @note   This function can be used for specific usage of the SMPS,
01393   *         for general usage of the SMPS the function
01394   *         @ref LL_PWR_SMPS_SetMode() should be used instead.
01395   * @rmtoll CR5          SMPSEN        LL_PWR_SMPS_Enable
01396   * @retval None
01397   */
01398 __STATIC_INLINE void LL_PWR_SMPS_Enable(void)
01399 {
01400   SET_BIT(PWR->CR5, PWR_CR5_SMPSEN);
01401 }
01402
01403 /**
01404   * @brief  SMPS step down converter enable
01405   * @note   This function can be used for specific usage of the SMPS,
01406   *         for general usage of the SMPS the function
01407   *         @ref LL_PWR_SMPS_SetMode() should be used instead.
01408   * @rmtoll CR5          SMPSEN        LL_PWR_SMPS_Disable
01409   * @retval None
01410   */
01411 __STATIC_INLINE void LL_PWR_SMPS_Disable(void)
01412 {
01413   CLEAR_BIT(PWR->CR5, PWR_CR5_SMPSEN);
01414 }
01415
01416 /**
01417   * @brief  Check if the SMPS step down converter is enabled
01418   * @rmtoll CR5          SMPSEN        LL_PWR_SMPS_IsEnabled
01419   * @retval State of bit (1 or 0).
01420   */
01421 __STATIC_INLINE uint32_t LL_PWR_SMPS_IsEnabled(void)
01422 {
01423   return ((READ_BIT(PWR->CR5, PWR_CR5_SMPSEN) == (PWR_CR5_SMPSEN)) ? 1UL : 0UL);
01424 }
01425
01426 /**
01427   * @brief  Set SMPS step down converter supply startup current selection
01428   * @rmtoll CR5          SMPSSC        LL_PWR_SMPS_SetStartupCurrent
01429   * @param  StartupCurrent This parameter can be one of the following values:
01430   *         @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_80MA
01431   *         @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_100MA
01432   *         @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_120MA
01433   *         @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_140MA
01434   *         @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_160MA
01435   *         @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_180MA
01436   *         @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_200MA
01437   *         @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_220MA
01438   * @retval None
01439   */
01440 __STATIC_INLINE void LL_PWR_SMPS_SetStartupCurrent(uint32_t StartupCurrent)
01441 {
01442   MODIFY_REG(PWR->CR5, PWR_CR5_SMPSSC, StartupCurrent);
01443 }
01444
01445 /**
01446   * @brief  Get SMPS step down converter supply startup current selection
01447   * @rmtoll CR5          SMPSSC        LL_PWR_SMPS_GetStartupCurrent
01448   * @retval Returned value can be one of the following values:
01449   *         @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_80MA
01450   *         @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_100MA
01451   *         @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_120MA
01452   *         @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_140MA
01453   *         @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_160MA
01454   *         @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_180MA
01455   *         @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_200MA
01456   *         @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_220MA
01457   */
01458 __STATIC_INLINE uint32_t LL_PWR_SMPS_GetStartupCurrent(void)
01459 {
01460   return (uint32_t)(READ_BIT(PWR->CR5, PWR_CR5_SMPSSC));
01461 }
01462
01463 /**
01464   * @brief  Set SMPS step down converter output voltage scaling
01465   * @note   SMPS output voltage is calibrated in production,
01466   *         calibration parameters are applied to the voltage level parameter
01467   *         to reach the requested voltage value.
01468   * @rmtoll CR5          SMPSVOS       LL_PWR_SMPS_SetOutputVoltageLevel
01469   * @param  OutputVoltageLevel This parameter can be one of the following values:
01470   *         @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V20
01471   *         @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V25
01472   *         @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V30
01473   *         @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V35
01474   *         @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40
01475   *         @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V45
01476   *         @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V50
01477   *         @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V55
01478   *         @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V60
01479   *         @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V65
01480   *         @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V70
01481   *         @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V75
01482   *         @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V80
01483   *         @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V85
01484   *         @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V90
01485   * @retval None
01486   */
01487 __STATIC_INLINE void LL_PWR_SMPS_SetOutputVoltageLevel(uint32_t OutputVoltageLevel)
01488 {
01489   register __IO const uint32_t OutputVoltageLevel_calibration = (((*SMPS_VOLTAGE_CAL_ADDR) & SMPS_VOLTAGE_CAL) >> SMPS_VOLTAGE_CAL_POS);  /* SMPS output voltage level calibrated in production */
01490   register int32_t TrimmingSteps;                               /* Trimming steps between theorical output voltage and calibrated output voltage */
01491   register int32_t OutputVoltageLevelTrimmed;                   /* SMPS output voltage level after calibration: trimming value added to required level */
01492
01493   if(OutputVoltageLevel_calibration == 0UL)
01494   {
01495     /* Device with SMPS output voltage not calibrated in production: Apply output voltage value directly */
01496
01497     /* Update register */
01498     MODIFY_REG(PWR->CR5, PWR_CR5_SMPSVOS, OutputVoltageLevel);
01499   }
01500   else
01501   {
01502     /* Device with SMPS output voltage calibrated in production: Apply output voltage value after correction by calibration value */
01503
01504     TrimmingSteps = ((int32_t)OutputVoltageLevel_calibration - (int32_t)(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V50 >> PWR_CR5_SMPSVOS_Pos));
01505     OutputVoltageLevelTrimmed = ((int32_t)((uint32_t)(OutputVoltageLevel >> PWR_CR5_SMPSVOS_Pos)) + (int32_t)TrimmingSteps);
01506
01507     /* Clamp value to voltage trimming bitfield range */
01508     if(OutputVoltageLevelTrimmed < 0)
01509     {
01510       OutputVoltageLevelTrimmed = 0;
01511     }
01512     else
01513     {
01514       if(OutputVoltageLevelTrimmed > (int32_t)PWR_CR5_SMPSVOS)
01515       {
01516         OutputVoltageLevelTrimmed = (int32_t)PWR_CR5_SMPSVOS;
01517       }
01518     }
01519
01520     /* Update register */
01521     MODIFY_REG(PWR->CR5, PWR_CR5_SMPSVOS, (uint32_t)OutputVoltageLevelTrimmed);
01522   }
01523 }
01524
01525 /**
01526   * @brief  Get SMPS step down converter output voltage scaling
01527   * @note   SMPS output voltage is calibrated in production,
01528   *         calibration parameters are applied to the voltage level parameter
01529   *         to return the effective voltage value.
01530   * @rmtoll CR5          SMPSVOS       LL_PWR_SMPS_GetOutputVoltageLevel
01531   * @retval Returned value can be one of the following values:
01532   *         @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V20
01533   *         @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V25
01534   *         @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V30
01535   *         @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V35
01536   *         @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40
01537   *         @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V45
01538   *         @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V50
01539   *         @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V55
01540   *         @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V60
01541   *         @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V65
01542   *         @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V70
01543   *         @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V75
01544   *         @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V80
01545   *         @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V85
01546   *         @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V90
01547   */
01548 __STATIC_INLINE uint32_t LL_PWR_SMPS_GetOutputVoltageLevel(void)
01549 {
01550   register __IO const uint32_t OutputVoltageLevel_calibration = (((*SMPS_VOLTAGE_CAL_ADDR) & SMPS_VOLTAGE_CAL) >> SMPS_VOLTAGE_CAL_POS);  /* SMPS output voltage level calibrated in production */
01551   register int32_t TrimmingSteps;                               /* Trimming steps between theorical output voltage and calibrated output voltage */
01552   register int32_t OutputVoltageLevelTrimmed;                   /* SMPS output voltage level after calibration: trimming value added to required level */
01553
01554   if(OutputVoltageLevel_calibration == 0UL)
01555   {
01556     /* Device with SMPS output voltage not calibrated in production: Return output voltage value directly */
01557
01558     return (uint32_t)(READ_BIT(PWR->CR5, PWR_CR5_SMPSVOS));
01559   }
01560   else
01561   {
01562     /* Device with SMPS output voltage calibrated in production: Return output voltage value after correction by calibration value */
01563
01564     TrimmingSteps = ((int32_t)OutputVoltageLevel_calibration - (int32_t)(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V50 >> PWR_CR5_SMPSVOS_Pos)); /* Trimming steps between theorical output voltage and calibrated output voltage */
01565
01566     OutputVoltageLevelTrimmed = ((int32_t)((uint32_t)READ_BIT(PWR->CR5, PWR_CR5_SMPSVOS)) - TrimmingSteps);
01567
01568     /* Clamp value to voltage range */
01569     if(OutputVoltageLevelTrimmed < 0)
01570     {
01571       OutputVoltageLevelTrimmed = (int32_t)LL_PWR_SMPS_OUTPUT_VOLTAGE_1V20;
01572     }
01573     else
01574     {
01575       if(OutputVoltageLevelTrimmed > (int32_t)PWR_CR5_SMPSVOS)
01576       {
01577         OutputVoltageLevelTrimmed = (int32_t)LL_PWR_SMPS_OUTPUT_VOLTAGE_1V90;
01578       }
01579     }
01580
01581     return (uint32_t)OutputVoltageLevelTrimmed;
01582   }
01583 }
01584
01585 /**
01586   * @}
01587   */
01588 #endif
01589
01590 /** @defgroup PWR_LL_EF_Configuration_Multicore Configuration of multicore, intended to be executed by CPU1
01591   * @{
01592   */
01593
01594 /**
01595   * @brief  Boot CPU2 after reset or wakeup from stop or standby modes
01596   * @rmtoll CR4          C2BOOT        LL_PWR_EnableBootC2
01597   * @retval None
01598   */
01599 __STATIC_INLINE void LL_PWR_EnableBootC2(void)
01600 {
01601   SET_BIT(PWR->CR4, PWR_CR4_C2BOOT);
01602 }
01603
01604 /**
01605   * @brief  Release bit to boot CPU2 after reset or wakeup from stop or standby
01606   *         modes
01607   * @rmtoll CR4          C2BOOT        LL_PWR_DisableBootC2
01608   * @retval None
01609   */
01610 __STATIC_INLINE void LL_PWR_DisableBootC2(void)
01611 {
01612   CLEAR_BIT(PWR->CR4, PWR_CR4_C2BOOT);
01613 }
01614
01615 /**
01616   * @brief  Check if bit to boot CPU2 after reset or wakeup from stop or standby
01617   *         modes is set
01618   * @rmtoll CR4          C2BOOT        LL_PWR_IsEnabledBootC2
01619   * @retval State of bit (1 or 0)
01620   */
01621 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBootC2(void)
01622 {
01623   return ((READ_BIT(PWR->CR4, PWR_CR4_C2BOOT) == (PWR_CR4_C2BOOT)) ? 1UL : 0UL);
01624 }
01625
01626 /**
01627   * @}
01628   */
01629
01630 /** @defgroup PWR_LL_EF_Configuration_CPU2 Configuration of CPU2, intended to be executed by CPU2
01631   * @{
01632   */
01633
01634 /**
01635   * @brief  Set Low-Power mode for CPU2
01636   * @rmtoll C2CR1        LPMS          LL_C2_PWR_SetPowerMode
01637   * @param  LowPowerMode This parameter can be one of the following values:
01638   *         @arg @ref LL_PWR_MODE_STOP0
01639   *         @arg @ref LL_PWR_MODE_STOP1
01640   *         @arg @ref LL_PWR_MODE_STOP2
01641   *         @arg @ref LL_PWR_MODE_STANDBY
01642   *         @arg @ref LL_PWR_MODE_SHUTDOWN
01643   * @retval None
01644   */
01645 __STATIC_INLINE void LL_C2_PWR_SetPowerMode(uint32_t LowPowerMode)
01646 {
01647   MODIFY_REG(PWR->C2CR1, PWR_C2CR1_LPMS, LowPowerMode);
01648 }
01649
01650 /**
01651   * @brief  Get Low-Power mode for CPU2
01652   * @rmtoll C2CR1        LPMS          LL_C2_PWR_GetPowerMode
01653   * @retval Returned value can be one of the following values:
01654   *         @arg @ref LL_PWR_MODE_STOP0
01655   *         @arg @ref LL_PWR_MODE_STOP1
01656   *         @arg @ref LL_PWR_MODE_STOP2
01657   *         @arg @ref LL_PWR_MODE_STANDBY
01658   *         @arg @ref LL_PWR_MODE_SHUTDOWN
01659   */
01660 __STATIC_INLINE uint32_t LL_C2_PWR_GetPowerMode(void)
01661 {
01662   return (uint32_t)(READ_BIT(PWR->C2CR1, PWR_C2CR1_LPMS));
01663 }
01664
01665 /**
01666   * @brief  Set flash power-down mode during low-power run mode for CPU2
01667   * @rmtoll C2CR1        FPDR          LL_C2_PWR_SetFlashPowerModeLPRun
01668   * @param  FlashLowPowerMode This parameter can be one of the following values:
01669   *         @arg @ref LL_PWR_FLASH_LPRUN_MODE_IDLE
01670   *         @arg @ref LL_PWR_FLASH_LPRUN_MODE_POWER_DOWN
01671   * @retval None
01672   */
01673 __STATIC_INLINE void LL_C2_PWR_SetFlashPowerModeLPRun(uint32_t FlashLowPowerMode)
01674 {
01675   /* Unlock bit FPDR */
01676   WRITE_REG(PWR->C2CR1, 0x0000C1B0U);
01677
01678   /* Update bit FPDR */
01679   MODIFY_REG(PWR->C2CR1, PWR_C2CR1_FPDR, FlashLowPowerMode);
01680 }
01681
01682 /**
01683   * @brief  Get flash power-down mode during low-power run mode for CPU2
01684   * @rmtoll C2CR1        FPDR          LL_C2_PWR_GetFlashPowerModeLPRun
01685   * @retval Returned value can be one of the following values:
01686   *         @arg @ref LL_PWR_FLASH_LPRUN_MODE_IDLE
01687   *         @arg @ref LL_PWR_FLASH_LPRUN_MODE_POWER_DOWN
01688   */
01689 __STATIC_INLINE uint32_t LL_C2_PWR_GetFlashPowerModeLPRun(void)
01690 {
01691   return (uint32_t)(READ_BIT(PWR->C2CR1, PWR_C2CR1_FPDR));
01692 }
01693
01694 /**
01695   * @brief  Set flash power-down mode during sleep mode for CPU2
01696   * @rmtoll C2CR1        FPDS          LL_C2_PWR_SetFlashPowerModeSleep
01697   * @param  FlashLowPowerMode This parameter can be one of the following values:
01698   *         @arg @ref LL_PWR_FLASH_SLEEP_MODE_IDLE
01699   *         @arg @ref LL_PWR_FLASH_SLEEP_MODE_POWER_DOWN
01700   * @retval None
01701   */
01702 __STATIC_INLINE void LL_C2_PWR_SetFlashPowerModeSleep(uint32_t FlashLowPowerMode)
01703 {
01704   MODIFY_REG(PWR->C2CR1, PWR_C2CR1_FPDS, FlashLowPowerMode);
01705 }
01706
01707 /**
01708   * @brief  Get flash power-down mode during sleep mode for CPU2
01709   * @rmtoll C2CR1        FPDS          LL_C2_PWR_GetFlashPowerModeSleep
01710   * @retval Returned value can be one of the following values:
01711   *         @arg @ref LL_PWR_FLASH_SLEEP_MODE_IDLE
01712   *         @arg @ref LL_PWR_FLASH_SLEEP_MODE_POWER_DOWN
01713   */
01714 __STATIC_INLINE uint32_t LL_C2_PWR_GetFlashPowerModeSleep(void)
01715 {
01716   return (uint32_t)(READ_BIT(PWR->C2CR1, PWR_C2CR1_FPDS));
01717 }
01718
01719
01720 /**
01721   * @brief  Enable Internal Wake-up line for CPU2
01722   * @rmtoll C2CR3        EIWUL         LL_C2_PWR_EnableInternWU
01723   * @retval None
01724   */
01725 __STATIC_INLINE void LL_C2_PWR_EnableInternWU(void)
01726 {
01727   SET_BIT(PWR->C2CR3, PWR_C2CR3_EIWUL);
01728 }
01729
01730 /**
01731   * @brief  Disable Internal Wake-up line for CPU2
01732   * @rmtoll C2CR3        EIWUL         LL_C2_PWR_DisableInternWU
01733   * @retval None
01734   */
01735 __STATIC_INLINE void LL_C2_PWR_DisableInternWU(void)
01736 {
01737   CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_EIWUL);
01738 }
01739
01740 /**
01741   * @brief  Check if Internal Wake-up line is enabled for CPU2
01742   * @rmtoll C2CR3        EIWUL         LL_C2_PWR_IsEnabledInternWU
01743   * @retval State of bit (1 or 0).
01744   */
01745 __STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledInternWU(void)
01746 {
01747   return ((READ_BIT(PWR->C2CR3, PWR_C2CR3_EIWUL) == (PWR_C2CR3_EIWUL)) ? 1UL : 0UL);
01748 }
01749
01750 /**
01751   * @brief  Enable the WakeUp PINx functionality
01752   * @rmtoll C2CR3        EWUP1         LL_C2_PWR_EnableWakeUpPin\n
01753   *         C2CR3        EWUP2         LL_C2_PWR_EnableWakeUpPin\n
01754   *         C2CR3        EWUP3         LL_C2_PWR_EnableWakeUpPin\n
01755   *         C2CR3        EWUP4         LL_C2_PWR_EnableWakeUpPin\n
01756   *         C2CR3        EWUP5         LL_C2_PWR_EnableWakeUpPin
01757   * @param  WakeUpPin This parameter can be one of the following values:
01758   *         @arg @ref LL_PWR_WAKEUP_PIN1
01759   *         @arg @ref LL_PWR_WAKEUP_PIN2 (*)
01760   *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
01761   *         @arg @ref LL_PWR_WAKEUP_PIN4
01762   *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
01763   *
01764   *         (*) Not available on devices STM32WB50xx
01765   * @retval None
01766   */
01767 __STATIC_INLINE void LL_C2_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
01768 {
01769   SET_BIT(PWR->C2CR3, WakeUpPin);
01770 }
01771
01772 /**
01773   * @brief  Disable the WakeUp PINx functionality
01774   * @rmtoll C2CR3        EWUP1         LL_C2_PWR_DisableWakeUpPin\n
01775   *         C2CR3        EWUP2         LL_C2_PWR_DisableWakeUpPin\n
01776   *         C2CR3        EWUP3         LL_C2_PWR_DisableWakeUpPin\n
01777   *         C2CR3        EWUP4         LL_C2_PWR_DisableWakeUpPin\n
01778   *         C2CR3        EWUP5         LL_C2_PWR_DisableWakeUpPin
01779   * @param  WakeUpPin This parameter can be one of the following values:
01780   *         @arg @ref LL_PWR_WAKEUP_PIN1
01781   *         @arg @ref LL_PWR_WAKEUP_PIN2 (*)
01782   *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
01783   *         @arg @ref LL_PWR_WAKEUP_PIN4
01784   *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
01785   *
01786   *         (*) Not available on devices STM32WB50xx
01787   * @retval None
01788   */
01789 __STATIC_INLINE void LL_C2_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
01790 {
01791   CLEAR_BIT(PWR->C2CR3, WakeUpPin);
01792 }
01793
01794 /**
01795   * @brief  Check if the WakeUp PINx functionality is enabled
01796   * @rmtoll C2CR3        EWUP1         LL_C2_PWR_IsEnabledWakeUpPin\n
01797   *         C2CR3        EWUP2         LL_C2_PWR_IsEnabledWakeUpPin\n
01798   *         C2CR3        EWUP3         LL_C2_PWR_IsEnabledWakeUpPin\n
01799   *         C2CR3        EWUP4         LL_C2_PWR_IsEnabledWakeUpPin\n
01800   *         C2CR3        EWUP5         LL_C2_PWR_IsEnabledWakeUpPin
01801   * @param  WakeUpPin This parameter can be one of the following values:
01802   *         @arg @ref LL_PWR_WAKEUP_PIN1
01803   *         @arg @ref LL_PWR_WAKEUP_PIN2 (*)
01804   *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
01805   *         @arg @ref LL_PWR_WAKEUP_PIN4
01806   *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
01807   *
01808   *         (*) Not available on devices STM32WB50xx
01809   * @retval None
01810   */
01811 __STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
01812 {
01813   return ((READ_BIT(PWR->C2CR3, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
01814 }
01815
01816 /**
01817   * @brief  Enable pull-up and pull-down configuration for CPU2
01818   * @rmtoll C2CR3        APC           LL_C2_PWR_EnablePUPDCfg
01819   * @retval None
01820   */
01821 __STATIC_INLINE void LL_C2_PWR_EnablePUPDCfg(void)
01822 {
01823   SET_BIT(PWR->C2CR3, PWR_C2CR3_APC);
01824 }
01825
01826 /**
01827   * @brief  Disable pull-up and pull-down configuration for CPU2
01828   * @rmtoll C2CR3        APC           LL_C2_PWR_DisablePUPDCfg
01829   * @retval None
01830   */
01831 __STATIC_INLINE void LL_C2_PWR_DisablePUPDCfg(void)
01832 {
01833   CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_APC);
01834 }
01835
01836 /**
01837   * @brief  Check if pull-up and pull-down configuration is enabled for CPU2
01838   * @rmtoll C2CR3        APC           LL_C2_PWR_IsEnabledPUPDCfg
01839   * @retval State of bit (1 or 0).
01840   */
01841 __STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledPUPDCfg(void)
01842 {
01843   return ((READ_BIT(PWR->C2CR3, PWR_C2CR3_APC) == (PWR_C2CR3_APC)) ? 1UL : 0UL);
01844 }
01845
01846 /**
01847   * @}
01848   */
01849
01850 /** @defgroup PWR_LL_EF_Configuration_CPU2_Radio Configuration of radio (BLE or 802.15.4) of CPU2, intended to be executed by CPU2
01851   * @{
01852   */
01853
01854 /**
01855   * @brief  Wakeup BLE controller from its sleep mode
01856   * @note   This bit is automatically reset when BLE controller
01857   *         exit its sleep mode.
01858   * @rmtoll C2CR1        BLEEWKUP      LL_C2_PWR_WakeUp_BLE
01859   * @retval None
01860   */
01861 __STATIC_INLINE void LL_C2_PWR_WakeUp_BLE(void)
01862 {
01863   SET_BIT(PWR->C2CR1, PWR_C2CR1_BLEEWKUP);
01864 }
01865
01866 /**
01867   * @brief  Check if the BLE controller is woken-up from
01868   *         low-power mode.
01869   * @rmtoll C2CR1        BLEEWKUP      LL_C2_PWR_IsWokenUp_BLE
01870   * @retval State of bit (1 or 0) (value "0": BLE is not woken-up)
01871   */
01872 __STATIC_INLINE uint32_t LL_C2_PWR_IsWokenUp_BLE(void)
01873 {
01874   return ((READ_BIT(PWR->C2CR1, PWR_C2CR1_BLEEWKUP) == (PWR_C2CR1_BLEEWKUP)) ? 1UL : 0UL);
01875 }
01876
01877 /**
01878   * @brief  Wakeup 802.15.4 controller from its sleep mode
01879   * @note   This bit is automatically reset when 802.15.4 controller
01880   *         exit its sleep mode.
01881   * @rmtoll C2CR1        802EWKUP      LL_C2_PWR_WakeUp_802_15_4
01882   * @retval None
01883   */
01884 __STATIC_INLINE void LL_C2_PWR_WakeUp_802_15_4(void)
01885 {
01886   SET_BIT(PWR->C2CR1, PWR_C2CR1_802EWKUP);
01887 }
01888
01889 /**
01890   * @brief  Check if the 802.15.4 controller is woken-up from
01891   *         low-power mode.
01892   * @rmtoll C2CR1        802EWKUP      LL_C2_PWR_IsWokenUp_802_15_4
01893   * @retval State of bit (1 or 0) (value "0": 802.15.4 is not woken-up)
01894   */
01895 __STATIC_INLINE uint32_t LL_C2_PWR_IsWokenUp_802_15_4(void)
01896 {
01897   return ((READ_BIT(PWR->C2CR1, PWR_C2CR1_802EWKUP) == (PWR_C2CR1_802EWKUP)) ? 1UL : 0UL);
01898 }
01899
01900 /**
01901   * @}
01902   */
01903
01904 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
01905   * @{
01906   */
01907
01908 /**
01909   * @brief  Get Internal Wake-up line Flag
01910   * @rmtoll SR1          WUFI          LL_PWR_IsActiveFlag_InternWU
01911   * @retval State of bit (1 or 0).
01912   */
01913 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void)
01914 {
01915   return ((READ_BIT(PWR->SR1, PWR_SR1_WUFI) == (PWR_SR1_WUFI)) ? 1UL : 0UL);
01916 }
01917
01918 #if defined(PWR_CR3_EWUP5)
01919 /**
01920   * @brief  Get Wake-up Flag 5
01921   * @rmtoll SR1          WUF5          LL_PWR_IsActiveFlag_WU5
01922   * @retval State of bit (1 or 0).
01923   */
01924 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
01925 {
01926   return ((READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5)) ? 1UL : 0UL);
01927 }
01928 #endif
01929
01930 /**
01931   * @brief  Get Wake-up Flag 4
01932   * @rmtoll SR1          WUF4          LL_PWR_IsActiveFlag_WU4
01933   * @retval State of bit (1 or 0).
01934   */
01935 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
01936 {
01937   return ((READ_BIT(PWR->SR1, PWR_SR1_WUF4) == (PWR_SR1_WUF4)) ? 1UL : 0UL);
01938 }
01939
01940 #if defined(PWR_CR3_EWUP3)
01941 /**
01942   * @brief  Get Wake-up Flag 3
01943   * @rmtoll SR1          WUF3          LL_PWR_IsActiveFlag_WU3
01944   * @retval State of bit (1 or 0).
01945   */
01946 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
01947 {
01948   return ((READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)) ? 1UL : 0UL);
01949 }
01950 #endif
01951
01952 #if defined(PWR_CR3_EWUP2)
01953 /**
01954   * @brief  Get Wake-up Flag 2
01955   * @rmtoll SR1          WUF2          LL_PWR_IsActiveFlag_WU2
01956   * @retval State of bit (1 or 0).
01957   */
01958 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
01959 {
01960   return ((READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2)) ? 1UL : 0UL);
01961 }
01962 #endif
01963
01964 /**
01965   * @brief  Get Wake-up Flag 1
01966   * @rmtoll SR1          WUF1          LL_PWR_IsActiveFlag_WU1
01967   * @retval State of bit (1 or 0).
01968   */
01969 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
01970 {
01971   return ((READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1)) ? 1UL : 0UL);
01972 }
01973
01974 /**
01975   * @brief  Clear Wake-up Flags
01976   * @rmtoll SCR          CWUF          LL_PWR_ClearFlag_WU
01977   * @retval None
01978   */
01979 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
01980 {
01981   WRITE_REG(PWR->SCR, PWR_SCR_CWUF);
01982 }
01983
01984 #if defined(PWR_CR3_EWUP5)
01985 /**
01986   * @brief  Clear Wake-up Flag 5
01987   * @rmtoll SCR          CWUF5         LL_PWR_ClearFlag_WU5
01988   * @retval None
01989   */
01990 __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
01991 {
01992   WRITE_REG(PWR->SCR, PWR_SCR_CWUF5);
01993 }
01994 #endif
01995
01996 /**
01997   * @brief  Clear Wake-up Flag 4
01998   * @rmtoll SCR          CWUF4         LL_PWR_ClearFlag_WU4
01999   * @retval None
02000   */
02001 __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
02002 {
02003   WRITE_REG(PWR->SCR, PWR_SCR_CWUF4);
02004 }
02005
02006 #if defined(PWR_CR3_EWUP3)
02007 /**
02008   * @brief  Clear Wake-up Flag 3
02009   * @rmtoll SCR          CWUF3         LL_PWR_ClearFlag_WU3
02010   * @retval None
02011   */
02012 __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
02013 {
02014   WRITE_REG(PWR->SCR, PWR_SCR_CWUF3);
02015 }
02016 #endif
02017
02018 #if defined(PWR_CR3_EWUP2)
02019 /**
02020   * @brief  Clear Wake-up Flag 2
02021   * @rmtoll SCR          CWUF2         LL_PWR_ClearFlag_WU2
02022   * @retval None
02023   */
02024 __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
02025 {
02026   WRITE_REG(PWR->SCR, PWR_SCR_CWUF2);
02027 }
02028 #endif
02029
02030 /**
02031   * @brief  Clear Wake-up Flag 1
02032   * @rmtoll SCR          CWUF1         LL_PWR_ClearFlag_WU1
02033   * @retval None
02034   */
02035 __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
02036 {
02037   WRITE_REG(PWR->SCR, PWR_SCR_CWUF1);
02038 }
02039
02040
02041 /**
02042   * @brief  Indicate whether VDDA voltage is below or above PVM3 threshold
02043   * @rmtoll SR2          PVMO3         LL_PWR_IsActiveFlag_PVMO3
02044   * @retval State of bit (1 or 0).
02045   */
02046 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO3(void)
02047 {
02048   return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO3) == (PWR_SR2_PVMO3)) ? 1UL : 0UL);
02049 }
02050
02051 #if defined(PWR_CR2_PVME1)
02052 /**
02053   * @brief  Indicate whether VDDUSB voltage is below or above PVM1 threshold
02054   * @rmtoll SR2          PVMO1         LL_PWR_IsActiveFlag_PVMO1
02055   * @retval State of bit (1 or 0).
02056   */
02057 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO1(void)
02058 {
02059   return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO1) == (PWR_SR2_PVMO1)) ? 1UL : 0UL);
02060 }
02061 #endif
02062
02063 /**
02064   * @brief  Indicate whether VDD voltage is below or above the selected PVD threshold
02065   * @rmtoll SR2          PVDO          LL_PWR_IsActiveFlag_PVDO
02066   * @retval State of bit (1 or 0).
02067   */
02068 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
02069 {
02070   return ((READ_BIT(PWR->SR2, PWR_SR2_PVDO) == (PWR_SR2_PVDO)) ? 1UL : 0UL);
02071 }
02072
02073 #if defined(PWR_CR1_VOS)
02074 /**
02075   * @brief  Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
02076   * @rmtoll SR2          VOSF          LL_PWR_IsActiveFlag_VOS
02077   * @retval State of bit (1 or 0).
02078   */
02079 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
02080 {
02081   return ((READ_BIT(PWR->SR2, PWR_SR2_VOSF) == (PWR_SR2_VOSF)) ? 1UL : 0UL);
02082 }
02083 #endif
02084
02085 /**
02086   * @brief  Indicate whether the regulator is ready in main mode or is in low-power mode
02087   * @note   Take care, return value "0" means the regulator is ready. Return value "1" means the output voltage range is still changing.
02088   * @rmtoll SR2          REGLPF        LL_PWR_IsActiveFlag_REGLPF
02089   * @retval State of bit (1 or 0).
02090   */
02091 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void)
02092 {
02093   return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPF) == (PWR_SR2_REGLPF)) ? 1UL : 0UL);
02094 }
02095
02096 /**
02097   * @brief  Indicate whether or not the low-power regulator is ready
02098   * @rmtoll SR2          REGLPS        LL_PWR_IsActiveFlag_REGLPS
02099   * @retval State of bit (1 or 0).
02100   */
02101 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS(void)
02102 {
02103   return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPS) == (PWR_SR2_REGLPS)) ? 1UL : 0UL);
02104 }
02105
02106 /**
02107   * @brief  Get BORH interrupt flag
02108   * @rmtoll SR1          BORHF         LL_PWR_IsActiveFlag_BORH
02109   * @retval State of bit (1 or 0).
02110   */
02111 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BORH(void)
02112 {
02113   return ((READ_BIT(PWR->SR1, PWR_SR1_BORHF) == (PWR_SR1_BORHF)) ? 1UL : 0UL);
02114 }
02115
02116 /**
02117   * @brief  Clear BORH interrupt flag
02118   * @rmtoll SCR          CBORHF        LL_PWR_ClearFlag_BORH
02119   * @retval None
02120   */
02121 __STATIC_INLINE void LL_PWR_ClearFlag_BORH(void)
02122 {
02123   WRITE_REG(PWR->SCR, PWR_SCR_CBORHF);
02124 }
02125
02126 /**
02127   * @}
02128   */
02129
02130 #if defined(PWR_CR5_SMPSEN)
02131 /** @defgroup PWR_LL_EF_FLAG_Management_SMPS FLAG management for SMPS
02132   * @{
02133   */
02134
02135 /**
02136   * @brief  Get SMPS step down converter forced in bypass mode interrupt flag
02137   * @note   To activate flag of SMPS step down converter forced in bypass mode
02138   *         by BORH, BOR must be preliminarily configured to control SMPS
02139   *         operating mode.
02140   *         Refer to function @ref LL_PWR_SetBORConfig().
02141   * @rmtoll SR1          SMPSFBF       LL_PWR_IsActiveFlag_SMPSFB
02142   * @retval State of bit (1 or 0).
02143   */
02144 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SMPSFB(void)
02145 {
02146   return ((READ_BIT(PWR->SR1, PWR_SR1_SMPSFBF) == (PWR_SR1_SMPSFBF)) ? 1UL : 0UL);
02147 }
02148
02149 /**
02150   * @brief  Clear SMPS step down converter forced in bypass mode interrupt flag
02151   * @note   To activate flag of SMPS step down converter forced in bypass mode
02152   *         by BORH, BOR must be preliminarily configured to control SMPS
02153   *         operating mode.
02154   *         Refer to function @ref LL_PWR_SetBORConfig().
02155   * @rmtoll SCR          CSMPSFBF      LL_PWR_ClearFlag_SMPSFB
02156   * @retval None
02157   */
02158 __STATIC_INLINE void LL_PWR_ClearFlag_SMPSFB(void)
02159 {
02160   WRITE_REG(PWR->SCR, PWR_SCR_CSMPSFBF);
02161 }
02162
02163 /**
02164   * @}
02165   */
02166 #endif
02167
02168 /** @defgroup PWR_LL_EF_FLAG_Management_Radio FLAG management for radio (BLE or 802.15.4)
02169   * @{
02170   */
02171
02172 /**
02173   * @brief  Get BLE wakeup interrupt flag
02174   * @rmtoll SR1          BLEWUF        LL_PWR_IsActiveFlag_BLEWU
02175   * @retval State of bit (1 or 0).
02176   */
02177 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BLEWU(void)
02178 {
02179   return ((READ_BIT(PWR->SR1, PWR_SR1_BLEWUF) == (PWR_SR1_BLEWUF)) ? 1UL : 0UL);
02180 }
02181
02182 /**
02183   * @brief  Get 802.15.4 wakeup interrupt flag
02184   * @rmtoll SR1          802WUF        LL_PWR_IsActiveFlag_802WU
02185   * @retval State of bit (1 or 0).
02186   */
02187 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_802WU(void)
02188 {
02189   return ((READ_BIT(PWR->SR1, PWR_SR1_802WUF) == (PWR_SR1_802WUF)) ? 1UL : 0UL);
02190 }
02191
02192 /**
02193   * @brief  Get BLE end of activity interrupt flag
02194   * @rmtoll SR1          BLEAF         LL_PWR_IsActiveFlag_BLEA
02195   * @retval State of bit (1 or 0).
02196   */
02197 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BLEA(void)
02198 {
02199   return ((READ_BIT(PWR->SR1, PWR_SR1_BLEAF) == (PWR_SR1_BLEAF)) ? 1UL : 0UL);
02200 }
02201
02202 /**
02203   * @brief  Get 802.15.4 end of activity interrupt flag
02204   * @rmtoll SR1          802AF         LL_PWR_IsActiveFlag_802A
02205   * @retval State of bit (1 or 0).
02206   */
02207 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_802A(void)
02208 {
02209   return ((READ_BIT(PWR->SR1, PWR_SR1_802AF) == (PWR_SR1_802AF)) ? 1UL : 0UL);
02210 }
02211
02212 /**
02213   * @brief  Get critical radio phase end of activity interrupt flag
02214   * @rmtoll SR1          CRPEF         LL_PWR_IsActiveFlag_CRPE
02215   * @retval State of bit (1 or 0).
02216   */
02217 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_CRPE(void)
02218 {
02219   return ((READ_BIT(PWR->SR1, PWR_SR1_CRPEF) == (PWR_SR1_CRPEF)) ? 1UL : 0UL);
02220 }
02221
02222 /**
02223   * @brief  Get critical radio system phase flag
02224   * @rmtoll EXTSCR       CRPF          LL_PWR_IsActiveFlag_CRP
02225   * @retval State of bit (1 or 0).
02226   */
02227 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_CRP(void)
02228 {
02229   return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_CRPF) == (PWR_EXTSCR_CRPF)) ? 1UL : 0UL);
02230 }
02231
02232 /**
02233   * @brief  Clear BLE wakeup interrupt flag
02234   * @rmtoll SCR          BLEWU         LL_PWR_ClearFlag_BLEWU
02235   * @retval None
02236   */
02237 __STATIC_INLINE void LL_PWR_ClearFlag_BLEWU(void)
02238 {
02239   WRITE_REG(PWR->SCR, PWR_SCR_CBLEWUF);
02240 }
02241
02242 /**
02243   * @brief  Clear 802.15.4 wakeup interrupt flag
02244   * @rmtoll SCR          802WU         LL_PWR_ClearFlag_802WU
02245   * @retval None
02246   */
02247 __STATIC_INLINE void LL_PWR_ClearFlag_802WU(void)
02248 {
02249   WRITE_REG(PWR->SCR, PWR_SCR_C802WUF);
02250 }
02251
02252 /**
02253   * @brief  Clear BLE end of activity interrupt flag
02254   * @rmtoll SCR          BLEAF         LL_PWR_ClearFlag_BLEA
02255   * @retval None
02256   */
02257 __STATIC_INLINE void LL_PWR_ClearFlag_BLEA(void)
02258 {
02259   WRITE_REG(PWR->SCR, PWR_SCR_CBLEAF);
02260 }
02261
02262 /**
02263   * @brief  Clear 802.15.4 end of activity interrupt flag
02264   * @rmtoll SCR          802AF         LL_PWR_ClearFlag_802A
02265   * @retval None
02266   */
02267 __STATIC_INLINE void LL_PWR_ClearFlag_802A(void)
02268 {
02269   WRITE_REG(PWR->SCR, PWR_SCR_C802AF);
02270 }
02271
02272 /**
02273   * @brief  Clear critical radio phase end of activity interrupt flag
02274   * @rmtoll SCR          CCRPEF        LL_PWR_ClearFlag_CRPE
02275   * @retval None
02276   */
02277 __STATIC_INLINE void LL_PWR_ClearFlag_CRPE(void)
02278 {
02279   WRITE_REG(PWR->SCR, PWR_SCR_CCRPEF);
02280 }
02281
02282 /**
02283   * @brief  Clear critical radio system phase flag
02284   * @rmtoll EXTSCR       CCRP          LL_PWR_ClearFlag_CRP
02285   * @retval None
02286   */
02287 __STATIC_INLINE void LL_PWR_ClearFlag_CRP(void)
02288 {
02289   WRITE_REG(PWR->EXTSCR, PWR_EXTSCR_CCRPF);
02290 }
02291
02292 /**
02293   * @}
02294   */
02295
02296 /** @defgroup PWR_LL_EF_FLAG_Management_Multicore FLAG management for multicore
02297   * @{
02298   */
02299
02300 /**
02301   * @brief  Get CPU2 hold interrupt flag
02302   * @rmtoll SCR          CC2HF         LL_PWR_IsActiveFlag_C2H
02303   * @retval State of bit (1 or 0).
02304   */
02305 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C2H(void)
02306 {
02307   return ((READ_BIT(PWR->SR1, PWR_SR1_C2HF) == (PWR_SR1_C2HF)) ? 1UL : 0UL);
02308 }
02309
02310 /**
02311   * @brief  Get system stop flag for CPU1
02312   * @rmtoll EXTSCR       C1STOPF       LL_PWR_IsActiveFlag_C1STOP
02313   * @retval State of bit (1 or 0).
02314   */
02315 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C1STOP(void)
02316 {
02317   return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C1STOPF) == (PWR_EXTSCR_C1STOPF)) ? 1UL : 0UL);
02318 }
02319
02320 /**
02321   * @brief  Get system standby flag for CPU1
02322   * @rmtoll EXTSCR       C1SBF         LL_PWR_IsActiveFlag_C1SB
02323   * @retval State of bit (1 or 0).
02324   */
02325 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C1SB(void)
02326 {
02327   return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C1SBF) == (PWR_EXTSCR_C1SBF)) ? 1UL : 0UL);
02328 }
02329
02330 /**
02331   * @brief  Get deepsleep mode for CPU1
02332   * @rmtoll EXTSCR       C1DS          LL_PWR_IsActiveFlag_C1DS
02333   * @retval State of bit (1 or 0).
02334   */
02335 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C1DS(void)
02336 {
02337   return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C1DS) == (PWR_EXTSCR_C1DS)) ? 1UL : 0UL);
02338 }
02339
02340 /**
02341   * @brief  System stop flag for CPU2
02342   * @rmtoll EXTSCR       C2STOPF       LL_PWR_IsActiveFlag_C2STOP
02343   * @retval State of bit (1 or 0).
02344   */
02345 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C2STOP(void)
02346 {
02347   return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C2STOPF) == (PWR_EXTSCR_C2STOPF)) ? 1UL : 0UL);
02348 }
02349
02350 /**
02351   * @brief  System standby flag for CPU2
02352   * @rmtoll EXTSCR       C2SBF         LL_PWR_IsActiveFlag_C2SB
02353   * @retval State of bit (1 or 0).
02354   */
02355 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C2SB(void)
02356 {
02357   return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C2SBF) == (PWR_EXTSCR_C2SBF)) ? 1UL : 0UL);
02358 }
02359
02360 /**
02361   * @brief  Get deepsleep mode for CPU2
02362   * @rmtoll EXTSCR       C2DS          LL_PWR_IsActiveFlag_C2DS
02363   * @retval State of bit (1 or 0).
02364   */
02365 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C2DS(void)
02366 {
02367   return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C2DS) == (PWR_EXTSCR_C2DS)) ? 1UL : 0UL);
02368 }
02369
02370 /**
02371   * @brief  Clear CPU2 hold interrupt flag
02372   * @rmtoll SCR          CC2HF         LL_PWR_ClearFlag_C2H
02373   * @retval None
02374   */
02375 __STATIC_INLINE void LL_PWR_ClearFlag_C2H(void)
02376 {
02377   WRITE_REG(PWR->SCR, PWR_SCR_CC2HF);
02378 }
02379 /**
02380   * @brief  Clear standby and stop flags for CPU1
02381   * @rmtoll EXTSCR       C1CSSF        LL_PWR_ClearFlag_C1STOP_C1STB
02382   * @retval None
02383   */
02384 __STATIC_INLINE void LL_PWR_ClearFlag_C1STOP_C1STB(void)
02385 {
02386   WRITE_REG(PWR->EXTSCR, PWR_EXTSCR_C1CSSF);
02387 }
02388
02389 /**
02390   * @brief  Clear standby and stop flags for CPU2
02391   * @rmtoll EXTSCR       C2CSSF        LL_PWR_ClearFlag_C2STOP_C2STB
02392   * @retval None
02393   */
02394 __STATIC_INLINE void LL_PWR_ClearFlag_C2STOP_C2STB(void)
02395 {
02396   WRITE_REG(PWR->EXTSCR, PWR_EXTSCR_C2CSSF);
02397 }
02398
02399 /**
02400   * @}
02401   */
02402
02403 #if defined(PWR_CR5_SMPSEN)
02404 /** @defgroup PWR_LL_EF_IT_Management_SMPS PWR IT management for SMPS
02405   * @{
02406   */
02407
02408 /**
02409   * @brief  Enable SMPS step down converter forced in bypass mode by BORH
02410   *         interrupt for CPU1
02411   * @note   To activate flag of SMPS step down converter forced in bypass mode
02412   *         by BORH, BOR must be preliminarily configured to control SMPS
02413   *         operating mode.
02414   *         Refer to function @ref LL_PWR_SetBORConfig().
02415   * @rmtoll CR3          EBORHSMPSFB   LL_PWR_EnableIT_BORH_SMPSFB
02416   * @retval None
02417   */
02418 __STATIC_INLINE void LL_PWR_EnableIT_BORH_SMPSFB(void)
02419 {
02420   SET_BIT(PWR->CR3, PWR_CR3_EBORHSMPSFB);
02421 }
02422
02423 /**
02424   * @brief  Disable SMPS step down converter forced in bypass mode by BORH
02425   *         interrupt for CPU1
02426   * @rmtoll CR3          EBORHSMPSFB   LL_PWR_DisableIT_BORH_SMPSFB
02427   * @retval None
02428   */
02429 __STATIC_INLINE void LL_PWR_DisableIT_BORH_SMPSFB(void)
02430 {
02431   CLEAR_BIT(PWR->CR3, PWR_CR3_EBORHSMPSFB);
02432 }
02433
02434 /**
02435   * @brief  Check if SMPS step down converter forced in bypass mode by BORH
02436   *         interrupt is enabled for CPU1
02437   * @rmtoll CR3          EBORHSMPSFB   LL_PWR_IsEnabledIT_BORH_SMPSFB
02438   * @retval State of bit (1 or 0).
02439   */
02440 __STATIC_INLINE uint32_t LL_PWR_IsEnabledIT_BORH_SMPSFB(void)
02441 {
02442   return ((READ_BIT(PWR->CR3, PWR_CR3_EBORHSMPSFB) == (PWR_CR3_EBORHSMPSFB)) ? 1UL : 0UL);
02443 }
02444
02445 /**
02446   * @}
02447   */
02448 #endif
02449
02450 /** @defgroup PWR_LL_EF_IT_Management_Radio PWR IT management for radio (BLE or 802.15.4)
02451   * @{
02452   */
02453
02454 /**
02455   * @brief  Enable BLE end of activity interrupt for CPU1
02456   * @rmtoll CR3          EBLEA         LL_PWR_EnableIT_BLEA
02457   * @retval None
02458   */
02459 __STATIC_INLINE void LL_PWR_EnableIT_BLEA(void)
02460 {
02461   SET_BIT(PWR->CR3, PWR_CR3_EBLEA);
02462 }
02463
02464 /**
02465   * @brief  Enable 802.15.4 end of activity interrupt for CPU1
02466   * @rmtoll CR3          E802A         LL_PWR_EnableIT_802A
02467   * @retval None
02468   */
02469 __STATIC_INLINE void LL_PWR_EnableIT_802A(void)
02470 {
02471   SET_BIT(PWR->CR3, PWR_CR3_E802A);
02472 }
02473
02474
02475 /**
02476   * @brief  Disable BLE end of activity interrupt for CPU1
02477   * @rmtoll CR3          EBLEA         LL_PWR_DisableIT_BLEA
02478   * @retval None
02479   */
02480 __STATIC_INLINE void LL_PWR_DisableIT_BLEA(void)
02481 {
02482   CLEAR_BIT(PWR->CR3, PWR_CR3_EBLEA);
02483 }
02484
02485 /**
02486   * @brief  Disable 802.15.4 end of activity interrupt for CPU1
02487   * @rmtoll CR3          E802A         LL_PWR_DisableIT_802A
02488   * @retval None
02489   */
02490 __STATIC_INLINE void LL_PWR_DisableIT_802A(void)
02491 {
02492   CLEAR_BIT(PWR->CR3, PWR_CR3_E802A);
02493 }
02494
02495 /**
02496   * @brief  Check if BLE end of activity interrupt is enabled for CPU1
02497   * @rmtoll CR3          EBLEA         LL_PWR_IsEnabledIT_BLEA
02498   * @retval State of bit (1 or 0).
02499   */
02500 __STATIC_INLINE uint32_t LL_PWR_IsEnabledIT_BLEA(void)
02501 {
02502   return ((READ_BIT(PWR->CR3, PWR_CR3_EBLEA) == (PWR_CR3_EBLEA)) ? 1UL : 0UL);
02503 }
02504
02505 /**
02506   * @brief  Check if 802.15.4 end of activity interrupt is enabled for CPU1
02507   * @rmtoll CR3          E802A         LL_PWR_IsEnabledIT_802A
02508   * @retval State of bit (1 or 0).
02509   */
02510 __STATIC_INLINE uint32_t LL_PWR_IsEnabledIT_802A(void)
02511 {
02512   return ((READ_BIT(PWR->CR3, PWR_CR3_E802A) == (PWR_CR3_E802A)) ? 1UL : 0UL);
02513 }
02514
02515 /**
02516   * @brief  Enable critical radio phase end of activity interrupt for CPU1
02517   * @rmtoll CR3          ECRPE         LL_PWR_EnableIT_802A
02518   * @retval None
02519   */
02520 __STATIC_INLINE void LL_PWR_EnableIT_CRPE(void)
02521 {
02522   SET_BIT(PWR->CR3, PWR_CR3_ECRPE);
02523 }
02524
02525 /**
02526   * @brief  Disable critical radio phase end of activity interrupt for CPU1
02527   * @rmtoll CR3          ECRPE         LL_PWR_DisableIT_802A
02528   * @retval None
02529   */
02530 __STATIC_INLINE void LL_PWR_DisableIT_CRPE(void)
02531 {
02532   CLEAR_BIT(PWR->CR3, PWR_CR3_ECRPE);
02533 }
02534
02535 /**
02536   * @brief  Check if critical radio phase end of activity interrupt is enabled for CPU1
02537   * @rmtoll CR3          ECRPE         LL_PWR_IsEnabledIT_802A
02538   * @retval State of bit (1 or 0).
02539   */
02540 __STATIC_INLINE uint32_t LL_PWR_IsEnabledIT_CRPE(void)
02541 {
02542   return ((READ_BIT(PWR->CR3, PWR_CR3_ECRPE) == (PWR_CR3_ECRPE)) ? 1UL : 0UL);
02543 }
02544
02545 /**
02546   * @}
02547   */
02548
02549 /** @defgroup PWR_LL_EF_IT_Management_Multicore PWR IT management for multicore
02550   * @{
02551   */
02552
02553 /**
02554   * @brief  Enable CPU2 hold interrupt for CPU1
02555   * @rmtoll CR3          EC2H          LL_PWR_EnableIT_HoldCPU2
02556   * @retval None
02557   */
02558 __STATIC_INLINE void LL_PWR_EnableIT_HoldCPU2(void)
02559 {
02560   SET_BIT(PWR->CR3, PWR_CR3_EC2H);
02561 }
02562
02563 /**
02564   * @brief  Disable 802.15.4 host wakeup interrupt for CPU2
02565   * @rmtoll CR3          EC2H          LL_PWR_DisableIT_HoldCPU2
02566   * @retval None
02567   */
02568 __STATIC_INLINE void LL_PWR_DisableIT_HoldCPU2(void)
02569 {
02570   CLEAR_BIT(PWR->CR3, PWR_CR3_EC2H);
02571 }
02572
02573 /**
02574   * @brief  Check if BLE host wakeup interrupt is enabled for CPU2
02575   * @rmtoll CR3          EC2H          LL_PWR_IsEnabledIT_HoldCPU2
02576   * @retval State of bit (1 or 0).
02577   */
02578 __STATIC_INLINE uint32_t LL_PWR_IsEnabledIT_HoldCPU2(void)
02579 {
02580   return ((READ_BIT(PWR->CR3, PWR_CR3_EC2H) == (PWR_CR3_EC2H)) ? 1UL : 0UL);
02581 }
02582
02583 /**
02584   * @}
02585   */
02586
02587 /** @defgroup PWR_LL_EF_IT_Management_CPU2 PWR IT management of CPU2, intended to be executed by CPU2
02588   * @{
02589   */
02590
02591 /**
02592   * @brief  Enable BLE host wakeup interrupt for CPU2
02593   * @rmtoll C2CR3        EBLEWUP       LL_C2_PWR_EnableIT_BLEWU
02594   * @retval None
02595   */
02596 __STATIC_INLINE void LL_C2_PWR_EnableIT_BLEWU(void)
02597 {
02598   SET_BIT(PWR->C2CR3, PWR_C2CR3_EBLEWUP);
02599 }
02600
02601 /**
02602   * @brief  Enable 802.15.4 host wakeup interrupt for CPU2
02603   * @rmtoll C2CR3        E802WUP       LL_C2_PWR_EnableIT_802WU
02604   * @retval None
02605   */
02606 __STATIC_INLINE void LL_C2_PWR_EnableIT_802WU(void)
02607 {
02608   SET_BIT(PWR->C2CR3, PWR_C2CR3_E802WUP);
02609 }
02610
02611 /**
02612   * @brief  Disable BLE host wakeup interrupt for CPU2
02613   * @rmtoll C2CR3        EBLEWUP       LL_C2_PWR_DisableIT_BLEWU
02614   * @retval None
02615   */
02616 __STATIC_INLINE void LL_C2_PWR_DisableIT_BLEWU(void)
02617 {
02618   CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_EBLEWUP);
02619 }
02620
02621 /**
02622   * @brief  Disable 802.15.4 host wakeup interrupt for CPU2
02623   * @rmtoll C2CR3        E802WUP       LL_C2_PWR_DisableIT_802WU
02624   * @retval None
02625   */
02626 __STATIC_INLINE void LL_C2_PWR_DisableIT_802WU(void)
02627 {
02628   CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_E802WUP);
02629 }
02630
02631 /**
02632   * @brief  Check if BLE host wakeup interrupt is enabled for CPU2
02633   * @rmtoll C2CR3        EBLEWUP       LL_C2_PWR_IsEnabledIT_BLEWU
02634   * @retval State of bit (1 or 0).
02635   */
02636 __STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledIT_BLEWU(void)
02637 {
02638   return ((READ_BIT(PWR->C2CR3, PWR_C2CR3_EBLEWUP) == (PWR_C2CR3_EBLEWUP)) ? 1UL : 0UL);
02639 }
02640
02641 /**
02642   * @brief  Check if 802.15.4 host wakeup interrupt is enabled for CPU2
02643   * @rmtoll C2CR3        E802WUP       LL_C2_PWR_IsEnabledIT_802WU
02644   * @retval State of bit (1 or 0).
02645   */
02646 __STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledIT_802WU(void)
02647 {
02648   return ((READ_BIT(PWR->C2CR3, PWR_C2CR3_E802WUP) == (PWR_C2CR3_E802WUP)) ? 1UL : 0UL);
02649 }
02650
02651 /**
02652   * @}
02653   */
02654
02655 #if defined(USE_FULL_LL_DRIVER)
02656 /** @defgroup PWR_LL_EF_Init De-initialization function
02657   * @{
02658   */
02659 ErrorStatus LL_PWR_DeInit(void);
02660 /**
02661   * @}
02662   */
02663 #endif /* USE_FULL_LL_DRIVER */
02664
02665 /**
02666   * @}
02667   */
02668
02669 /**
02670   * @}
02671   */
02672
02673 #endif /* defined(PWR) */
02674
02675 /**
02676   * @}
02677   */
02678
02679 #ifdef __cplusplus
02680 }
02681 #endif
02682
02683 #endif /* STM32WBxx_LL_PWR_H */
02684
02685 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_rcc.c Source File

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stm32wbxx_ll_rcc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_rcc.c
00004   * @author  MCD Application Team
00005   * @brief   RCC LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32wbxx_ll_rcc.h"
00023 #ifdef  USE_FULL_ASSERT
00024 #include "stm32_assert.h"
00025 #else
00026 #define assert_param(expr) ((void)0U)
00027 #endif
00028 /** @addtogroup STM32WBxx_LL_Driver
00029   * @{
00030   */
00031
00032 #if defined(RCC)
00033
00034 /** @addtogroup RCC_LL
00035   * @{
00036   */
00037
00038 /* Private types -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 /* Private constants ---------------------------------------------------------*/
00041 /* Private macros ------------------------------------------------------------*/
00042 /** @addtogroup RCC_LL_Private_Macros
00043   * @{
00044   */
00045 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__)  ((__VALUE__) == LL_RCC_USART1_CLKSOURCE)
00046
00047 #if defined(LPUART1)
00048 #define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE)
00049 #endif
00050
00051 #if defined(I2C3)
00052 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
00053                                             || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
00054 #else
00055 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)    ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE)
00056 #endif
00057
00058 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \
00059                                             || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE))
00060
00061 #if defined(SAI1)
00062 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__)    ((__VALUE__) == LL_RCC_SAI1_CLKSOURCE)
00063 #endif
00064
00065 #define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
00066
00067 #define IS_LL_RCC_CLK48_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_CLK48_CLKSOURCE))
00068
00069 #if defined(USB)
00070 #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
00071 #endif
00072
00073 #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
00074
00075 /**
00076   * @}
00077   */
00078
00079 /* Private function prototypes -----------------------------------------------*/
00080 /** @defgroup RCC_LL_Private_Functions RCC Private functions
00081   * @{
00082   */
00083 uint32_t RCC_PLL_GetFreqDomain_SYS(void);
00084 uint32_t RCC_PLL_GetFreqDomain_SAI(void);
00085 uint32_t RCC_PLL_GetFreqDomain_ADC(void);
00086 uint32_t RCC_PLL_GetFreqDomain_48M(void);
00087
00088 #if defined(SAI1)
00089 uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void);
00090 uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void);
00091 uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void);
00092 #endif
00093
00094 uint32_t RCC_GetSystemClockFreq(void);
00095
00096
00097 uint32_t RCC_GetHCLK1ClockFreq(uint32_t SYSCLK_Frequency);
00098 uint32_t RCC_GetHCLK2ClockFreq(uint32_t SYSCLK_Frequency);
00099 uint32_t RCC_GetHCLK4ClockFreq(uint32_t SYSCLK_Frequency);
00100 uint32_t RCC_GetHCLK5ClockFreq(void);
00101
00102
00103 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
00104 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
00105 /**
00106   * @}
00107   */
00108
00109
00110 /* Exported functions --------------------------------------------------------*/
00111 /** @addtogroup RCC_LL_Exported_Functions
00112   * @{
00113   */
00114
00115 /** @addtogroup RCC_LL_EF_Init
00116   * @{
00117   */
00118
00119 /**
00120   * @brief  Reset the RCC clock  to the default reset state.
00121   * @note   The default reset state of the clock configuration is given below:
00122   *         - MSI ON and used as system clock source
00123   *         - HSE, HSI, HSI48, PLL and PLLSAI1 Source OFF
00124   *         - CPU1, CPU2, AHB4, APB1 and APB2 prescaler set to 1.
00125   *         - CSS, MCO OFF
00126   *         - All interrupts disabled
00127   * @note   This function doesn't modify the configuration of the
00128   *         - Peripheral clocks
00129   *         - LSI, LSE and RTC clocks
00130   * @retval An ErrorStatus enumeration value:
00131   *          - SUCCESS: RCC registers are de-initialized
00132   *          - ERROR: not applicable
00133   */
00134 ErrorStatus LL_RCC_DeInit(void)
00135 {
00136   uint32_t vl_mask;
00137
00138   /* Set MSION bit */
00139   LL_RCC_MSI_Enable();
00140
00141   /* Insure MSIRDY bit is set before writing default MSIRANGE value */
00142   while (LL_RCC_MSI_IsReady() == 0U)
00143   {}
00144
00145   /* Set MSIRANGE default value */
00146   LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_6);
00147
00148   /* Set MSITRIM bits to the reset value*/
00149   LL_RCC_MSI_SetCalibTrimming(0);
00150
00151   /* Set HSITRIM bits to the reset value*/
00152   LL_RCC_HSI_SetCalibTrimming(0x40U);
00153
00154   /* Reset CFGR register */
00155   LL_RCC_WriteReg(CFGR, 0x00070000U); /* MSI selected as System Clock and all prescaler to not divided */
00156
00157   /* Wait for MSI oscillator used as system clock */
00158   while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_MSI)
00159   {}
00160
00161   /* Write new mask in CR register */
00162   LL_RCC_WriteReg(CR, 0x00000061);
00163
00164   /* Wait for PLL READY bit to be reset */
00165   while (LL_RCC_PLL_IsReady() != 0U)
00166   {}
00167
00168   /* Reset PLLCFGR register */
00169   LL_RCC_WriteReg(PLLCFGR, 0x22041000U);
00170
00171 #if defined(SAI1)
00172   /* Wait for PLLSAI READY bit to be reset */
00173   while (LL_RCC_PLLSAI1_IsReady() != 0U)
00174   {}
00175
00176   /* Reset PLLSAI1CFGR register */
00177   LL_RCC_WriteReg(PLLSAI1CFGR, 0x22041000U);
00178 #endif
00179
00180   /* Disable all interrupts */
00181   LL_RCC_WriteReg(CIER, 0x00000000U);
00182
00183   /* Clear all interrupt flags */
00184 #if defined(SAI1)
00185   vl_mask = RCC_CICR_LSI1RDYC | RCC_CICR_LSERDYC | RCC_CICR_MSIRDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC | RCC_CICR_PLLRDYC | RCC_CICR_PLLSAI1RDYC | \
00186             RCC_CICR_CSSC | RCC_CICR_HSI48RDYC | RCC_CICR_LSECSSC | RCC_CICR_LSI2RDYC;
00187 #else
00188   vl_mask = RCC_CICR_LSI1RDYC | RCC_CICR_LSERDYC | RCC_CICR_MSIRDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC | RCC_CICR_PLLRDYC | \
00189             RCC_CICR_CSSC | RCC_CICR_HSI48RDYC | RCC_CICR_LSECSSC | RCC_CICR_LSI2RDYC;
00190 #endif
00191   LL_RCC_WriteReg(CICR, vl_mask);
00192
00193   /* Clear reset flags */
00194   LL_RCC_ClearResetFlags();
00195
00196 #if defined(RCC_SMPS_SUPPORT)
00197   /* SMPS reset */
00198   LL_RCC_WriteReg(SMPSCR, 0x00000301U); /* MSI default clock source */
00199 #endif
00200
00201   /* RF Wakeup Clock Source selection */
00202   LL_RCC_SetRFWKPClockSource(LL_RCC_RFWKP_CLKSOURCE_NONE);
00203
00204   /* HSI48 reset */
00205   LL_RCC_HSI48_Disable();
00206
00207   /* HSECR register write unlock & then reset*/
00208   LL_RCC_WriteReg(HSECR, HSE_CONTROL_UNLOCK_KEY);
00209   LL_RCC_WriteReg(HSECR, LL_RCC_HSE_CURRENTMAX_3); /* HSEGMC set to default value 011, current max limit 1.13 mA/V */
00210
00211   /* EXTCFGR reset*/
00212   LL_RCC_WriteReg(EXTCFGR, 0x00030000U);
00213
00214   return SUCCESS;
00215 }
00216
00217 /**
00218   * @}
00219   */
00220
00221 /** @addtogroup RCC_LL_EF_Get_Freq
00222   * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1 and APB2 buses clocks
00223   *         and different peripheral clocks available on the device.
00224   * @note   If SYSCLK source is MSI, function returns values based on MSI values(*)
00225   * @note   If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
00226   * @note   If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
00227   * @note   If SYSCLK source is PLL, function returns values based on HSE_VALUE(***)
00228   *         or HSI_VALUE(**) or MSI values(*) multiplied/divided by the PLL factors.
00229   * @note   (*)  MSI values are retrieved thanks to __LL_RCC_CALC_MSI_FREQ macro
00230   * @note   (**) HSI_VALUE is a constant defined in this file (default value
00231   *              16 MHz) but the real value may vary depending on the variations
00232   *              in voltage and temperature.
00233   * @note   (***) HSE_VALUE is a constant defined in this file (default value
00234   *               32 MHz), user has to ensure that HSE_VALUE is same as the real
00235   *               frequency of the crystal used. Otherwise, this function may
00236   *               have wrong result.
00237   * @note   The result of this function could be incorrect when using fractional
00238   *         value for HSE crystal.
00239   * @note   This function can be used by the user application to compute the
00240   *         baud-rate for the communication peripherals or configure other parameters.
00241   * @{
00242   */
00243
00244 /**
00245   * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1 and APB2 buses clocks
00246   * @note   Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
00247   *         must be called to update structure fields. Otherwise, any
00248   *         configuration based on this function will be incorrect.
00249   * @param  RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
00250   * @retval None
00251   */
00252 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
00253 {
00254   /* Get SYSCLK frequency */
00255   RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
00256
00257   /* HCLK1 clock frequency */
00258   RCC_Clocks->HCLK1_Frequency   = RCC_GetHCLK1ClockFreq(RCC_Clocks->SYSCLK_Frequency);
00259
00260   /* HCLK2 clock frequency */
00261   RCC_Clocks->HCLK2_Frequency   = RCC_GetHCLK2ClockFreq(RCC_Clocks->SYSCLK_Frequency);
00262
00263   /* HCLK4 clock frequency */
00264   RCC_Clocks->HCLK4_Frequency   = RCC_GetHCLK4ClockFreq(RCC_Clocks->SYSCLK_Frequency);
00265
00266   /* HCLK5 clock frequency */
00267   RCC_Clocks->HCLK5_Frequency   = RCC_GetHCLK5ClockFreq();
00268
00269   /* PCLK1 clock frequency */
00270   RCC_Clocks->PCLK1_Frequency  = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK1_Frequency);
00271
00272   /* PCLK2 clock frequency */
00273   RCC_Clocks->PCLK2_Frequency  = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK1_Frequency);
00274 }
00275
00276 #if defined(RCC_SMPS_SUPPORT)
00277 /**
00278   * @brief  Return SMPS clock frequency
00279   * @note   This function is only applicable when CPU runs,
00280   *         When waking up from Standby mode and powering on the VCODE supply, the HSI is
00281   *         selected as SMPS Step Down converter clock, independent from the selection in
00282   *         SMPSSEL.
00283   * @retval SMPS clock frequency (in Hz)
00284   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
00285   */
00286 uint32_t LL_RCC_GetSMPSClockFreq(void)
00287 {
00288   uint32_t smps_frequency;
00289   uint32_t smps_prescaler_index = ((LL_RCC_GetSMPSPrescaler()) >> RCC_SMPSCR_SMPSDIV_Pos);
00290   uint32_t smpsClockSource = LL_RCC_GetSMPSClockSource();
00291
00292   if (smpsClockSource == LL_RCC_SMPS_CLKSOURCE_STATUS_HSI) /* SMPS Clock source is HSI Osc. */
00293   {
00294     if (LL_RCC_HSI_IsReady() == 1U)
00295     {
00296       smps_frequency = HSI_VALUE / SmpsPrescalerTable[smps_prescaler_index][0];
00297     }
00298     else
00299     {
00300       smps_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00301     }
00302   }
00303   else if (smpsClockSource == LL_RCC_SMPS_CLKSOURCE_STATUS_HSE) /* SMPS Clock source is HSE Osc. */
00304   {
00305     if (LL_RCC_HSE_IsReady() == 1U)
00306     {
00307       smps_frequency = HSE_VALUE / SmpsPrescalerTable[smps_prescaler_index][5];
00308     }
00309     else
00310     {
00311       smps_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00312     }
00313   }
00314   else if (smpsClockSource == LL_RCC_SMPS_CLKSOURCE_STATUS_MSI) /* SMPS Clock source is MSI Osc. */
00315   {
00316     uint32_t msiRange = LL_RCC_MSI_GetRange();
00317
00318     if (msiRange == LL_RCC_MSIRANGE_8)
00319     {
00320       smps_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGE_8) / SmpsPrescalerTable[smps_prescaler_index][4];
00321     }
00322     else if (msiRange == LL_RCC_MSIRANGE_9)
00323     {
00324       smps_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGE_9) / SmpsPrescalerTable[smps_prescaler_index][3];
00325     }
00326     else if (msiRange == LL_RCC_MSIRANGE_10)
00327     {
00328       smps_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGE_10) / SmpsPrescalerTable[smps_prescaler_index][2];
00329     }
00330     else if (msiRange == LL_RCC_MSIRANGE_11)
00331     {
00332       smps_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGE_11) / SmpsPrescalerTable[smps_prescaler_index][1];
00333     }
00334     else
00335     {
00336       smps_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00337     }
00338   }
00339   else /* SMPS has no Clock */
00340   {
00341     smps_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00342   }
00343
00344   if (smps_frequency != LL_RCC_PERIPH_FREQUENCY_NO)
00345   {
00346     /* Systematic div by 2 */
00347     smps_frequency = smps_frequency >> 1U;
00348   }
00349
00350   return smps_frequency;
00351 }
00352
00353 #endif
00354
00355 /**
00356   * @brief  Return USARTx clock frequency
00357   * @param  USARTxSource This parameter can be one of the following values:
00358   *         @arg @ref LL_RCC_USART1_CLKSOURCE
00359   * @retval USART clock frequency (in Hz)
00360   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
00361   */
00362 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
00363 {
00364   uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00365
00366   /* Check parameter */
00367   assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
00368
00369   /* USART1CLK clock frequency */
00370   switch (LL_RCC_GetUSARTClockSource(USARTxSource))
00371   {
00372     case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
00373       usart_frequency = RCC_GetSystemClockFreq();
00374       break;
00375
00376     case LL_RCC_USART1_CLKSOURCE_HSI:    /* USART1 Clock is HSI Osc. */
00377       if (LL_RCC_HSI_IsReady() == 1U)
00378       {
00379         usart_frequency = HSI_VALUE;
00380       }
00381       break;
00382
00383     case LL_RCC_USART1_CLKSOURCE_LSE:    /* USART1 Clock is LSE Osc. */
00384       if (LL_RCC_LSE_IsReady() == 1U)
00385       {
00386         usart_frequency = LSE_VALUE;
00387       }
00388       break;
00389
00390     case LL_RCC_USART1_CLKSOURCE_PCLK2:  /* USART1 Clock is PCLK2 */
00391     default:
00392       usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLK1ClockFreq(RCC_GetSystemClockFreq()));
00393       break;
00394   }
00395   return usart_frequency;
00396 }
00397
00398 /**
00399   * @brief  Return I2Cx clock frequency
00400   * @param  I2CxSource This parameter can be one of the following values:
00401   *         @arg @ref LL_RCC_I2C1_CLKSOURCE
00402   *         @arg @ref LL_RCC_I2C3_CLKSOURCE
00403   * @retval I2C clock frequency (in Hz)
00404   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
00405   */
00406 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
00407 {
00408   uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00409
00410   /* Check parameter */
00411   assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
00412
00413   if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
00414   {
00415     /* I2C1 CLK clock frequency */
00416     switch (LL_RCC_GetI2CClockSource(I2CxSource))
00417     {
00418       case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
00419         i2c_frequency = RCC_GetSystemClockFreq();
00420         break;
00421
00422       case LL_RCC_I2C1_CLKSOURCE_HSI:    /* I2C1 Clock is HSI Osc. */
00423         if (LL_RCC_HSI_IsReady() == 1U)
00424         {
00425           i2c_frequency = HSI_VALUE;
00426         }
00427         break;
00428
00429       case LL_RCC_I2C1_CLKSOURCE_PCLK1:  /* I2C1 Clock is PCLK1 */
00430       default:
00431         i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLK1ClockFreq(RCC_GetSystemClockFreq()));
00432         break;
00433     }
00434   }
00435 #if defined(I2C3)
00436   else
00437   {
00438     /* I2C3 CLK clock frequency */
00439     switch (LL_RCC_GetI2CClockSource(I2CxSource))
00440     {
00441       case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */
00442         i2c_frequency = RCC_GetSystemClockFreq();
00443         break;
00444
00445       case LL_RCC_I2C3_CLKSOURCE_HSI:    /* I2C3 Clock is HSI Osc. */
00446         if (LL_RCC_HSI_IsReady() == 1U)
00447         {
00448           i2c_frequency = HSI_VALUE;
00449         }
00450         break;
00451
00452       case LL_RCC_I2C3_CLKSOURCE_PCLK1:  /* I2C3 Clock is PCLK1 */
00453       default:
00454         i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLK1ClockFreq(RCC_GetSystemClockFreq()));
00455         break;
00456     }
00457   }
00458 #endif
00459
00460   return i2c_frequency;
00461 }
00462
00463 #if defined(LPUART1)
00464 /**
00465   * @brief  Return LPUARTx clock frequency
00466   * @param  LPUARTxSource This parameter can be one of the following values:
00467   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE
00468   * @retval LPUART clock frequency (in Hz)
00469   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
00470   */
00471 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
00472 {
00473   uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00474
00475   /* Check parameter */
00476   assert_param(IS_LL_RCC_LPUART_CLKSOURCE(LPUARTxSource));
00477
00478   /* LPUART1CLK clock frequency */
00479   switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
00480   {
00481     case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */
00482       lpuart_frequency = RCC_GetSystemClockFreq();
00483       break;
00484
00485     case LL_RCC_LPUART1_CLKSOURCE_HSI:    /* LPUART1 Clock is HSI Osc. */
00486       if (LL_RCC_HSI_IsReady() == 1U)
00487       {
00488         lpuart_frequency = HSI_VALUE;
00489       }
00490       break;
00491
00492     case LL_RCC_LPUART1_CLKSOURCE_LSE:    /* LPUART1 Clock is LSE Osc. */
00493       if (LL_RCC_LSE_IsReady() == 1U)
00494       {
00495         lpuart_frequency = LSE_VALUE;
00496       }
00497       break;
00498
00499     case LL_RCC_LPUART1_CLKSOURCE_PCLK1:  /* LPUART1 Clock is PCLK1 */
00500     default:
00501       lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLK1ClockFreq(RCC_GetSystemClockFreq()));
00502       break;
00503   }
00504
00505   return lpuart_frequency;
00506 }
00507 #endif
00508
00509 /**
00510   * @brief  Return LPTIMx clock frequency
00511   * @param  LPTIMxSource This parameter can be one of the following values:
00512   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
00513   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE
00514   * @retval LPTIM clock frequency (in Hz)
00515   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready
00516   */
00517 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
00518 {
00519   uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00520   uint32_t temp = LL_RCC_LSI2_IsReady();
00521
00522   /* Check parameter */
00523   assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
00524
00525   if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
00526   {
00527     /* LPTIM1CLK clock frequency */
00528     switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
00529     {
00530       case LL_RCC_LPTIM1_CLKSOURCE_LSI:    /* LPTIM1 Clock is LSI Osc. */
00531         if ((LL_RCC_LSI1_IsReady() == 1UL) || (temp == 1UL))
00532         {
00533           lptim_frequency = LSI_VALUE;
00534         }
00535         break;
00536
00537       case LL_RCC_LPTIM1_CLKSOURCE_HSI:    /* LPTIM1 Clock is HSI Osc. */
00538         if (LL_RCC_HSI_IsReady() == 1U)
00539         {
00540           lptim_frequency = HSI_VALUE;
00541         }
00542         break;
00543
00544       case LL_RCC_LPTIM1_CLKSOURCE_LSE:    /* LPTIM1 Clock is LSE Osc. */
00545         if (LL_RCC_LSE_IsReady() == 1U)
00546         {
00547           lptim_frequency = LSE_VALUE;
00548         }
00549         break;
00550
00551       case LL_RCC_LPTIM1_CLKSOURCE_PCLK1:  /* LPTIM1 Clock is PCLK1 */
00552       default:
00553         lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLK1ClockFreq(RCC_GetSystemClockFreq()));
00554         break;
00555     }
00556   }
00557   else
00558   {
00559     /* LPTIM2CLK clock frequency */
00560     switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
00561     {
00562       case LL_RCC_LPTIM2_CLKSOURCE_LSI:    /* LPTIM2 Clock is LSI Osc. */
00563         if ((LL_RCC_LSI1_IsReady() == 1UL) || (temp == 1UL))
00564         {
00565           lptim_frequency = LSI_VALUE;
00566         }
00567         break;
00568
00569       case LL_RCC_LPTIM2_CLKSOURCE_HSI:    /* LPTIM2 Clock is HSI Osc. */
00570         if (LL_RCC_HSI_IsReady() == 1U)
00571         {
00572           lptim_frequency = HSI_VALUE;
00573         }
00574         break;
00575
00576       case LL_RCC_LPTIM2_CLKSOURCE_LSE:    /* LPTIM2 Clock is LSE Osc. */
00577         if (LL_RCC_LSE_IsReady() == 1U)
00578         {
00579           lptim_frequency = LSE_VALUE;
00580         }
00581         break;
00582
00583       case LL_RCC_LPTIM2_CLKSOURCE_PCLK1:  /* LPTIM2 Clock is PCLK1 */
00584       default:
00585         lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLK1ClockFreq(RCC_GetSystemClockFreq()));
00586         break;
00587     }
00588   }
00589
00590   return lptim_frequency;
00591 }
00592
00593 #if defined(SAI1)
00594 /**
00595   * @brief  Return SAIx clock frequency
00596   * @param  SAIxSource This parameter can be one of the following values:
00597   *         @arg @ref LL_RCC_SAI1_CLKSOURCE
00598   *
00599   * @retval SAI clock frequency (in Hz)
00600   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready
00601   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used
00602   */
00603 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
00604 {
00605   uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00606
00607   /* Check parameter */
00608   assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
00609
00610   switch (LL_RCC_GetSAIClockSource(SAIxSource))
00611   {
00612     case LL_RCC_SAI1_CLKSOURCE_HSI:        /* HSI clock used as SAI1 clock source */
00613       if (LL_RCC_HSI_IsReady() == 1U)
00614       {
00615         sai_frequency = HSI_VALUE;
00616       }
00617       break;
00618
00619     case LL_RCC_SAI1_CLKSOURCE_PLLSAI1:    /* PLLSAI1 clock used as SAI1 clock source */
00620       if (LL_RCC_PLLSAI1_IsReady() == 1U)
00621       {
00622         sai_frequency = RCC_PLLSAI1_GetFreqDomain_SAI();
00623       }
00624       break;
00625     case LL_RCC_SAI1_CLKSOURCE_PLL:        /* PLL clock used as SAI1 clock source */
00626       if (LL_RCC_PLL_IsReady() == 1U)
00627       {
00628         sai_frequency = RCC_PLL_GetFreqDomain_SAI();
00629       }
00630       break;
00631
00632     case LL_RCC_SAI1_CLKSOURCE_PIN:        /* External input clock used as SAI1 clock source */
00633     default:
00634       sai_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
00635       break;
00636   }
00637   return sai_frequency;
00638 }
00639 #endif
00640
00641 /**
00642   * @brief  Return CLK48x clock frequency
00643   * @param  CLK48xSource This parameter can be one of the following values:
00644   *         @arg @ref LL_RCC_CLK48_CLKSOURCE
00645   * @retval USB clock frequency (in Hz)
00646   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI or HSI48) or PLLs (PLL or PLLSAI1) is not ready
00647   */
00648 uint32_t LL_RCC_GetCLK48ClockFreq(uint32_t CLK48xSource)
00649 {
00650   uint32_t clk48_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00651
00652   /* Check parameter */
00653   assert_param(IS_LL_RCC_CLK48_CLKSOURCE(CLK48xSource));
00654
00655   /* CLK48CLK clock frequency */
00656   switch (LL_RCC_GetCLK48ClockSource(CLK48xSource))
00657   {
00658 #if defined(SAI1)
00659     case LL_RCC_CLK48_CLKSOURCE_PLLSAI1:       /* PLLSAI1 clock used as CLK48 clock source */
00660       if (LL_RCC_PLLSAI1_IsReady() == 1U)
00661       {
00662         clk48_frequency = RCC_PLLSAI1_GetFreqDomain_48M();
00663       }
00664       break;
00665 #endif
00666
00667     case LL_RCC_CLK48_CLKSOURCE_PLL:           /* PLL clock used as CLK48 clock source */
00668       if (LL_RCC_PLL_IsReady() == 1U)
00669       {
00670         clk48_frequency = RCC_PLL_GetFreqDomain_48M();
00671       }
00672       break;
00673
00674     case LL_RCC_CLK48_CLKSOURCE_MSI:           /* MSI clock used as CLK48 clock source */
00675       if (LL_RCC_MSI_IsReady() == 1U)
00676       {
00677         clk48_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
00678       }
00679       break;
00680
00681     case LL_RCC_CLK48_CLKSOURCE_HSI48:       /* HSI48 clock used as CLK48 clock source */
00682     default:
00683       if (LL_RCC_HSI48_IsReady() == 1U)
00684       {
00685         clk48_frequency = HSI48_VALUE;
00686       }
00687       break;
00688   }
00689
00690   return clk48_frequency;
00691 }
00692
00693 #if defined(USB)
00694 /**
00695   * @brief  Return USBx clock frequency
00696   * @param  USBxSource This parameter can be one of the following values:
00697   *         @arg @ref LL_RCC_CLK48_CLKSOURCE
00698   * @retval USB clock frequency (in Hz)
00699   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI or HSI48) or PLLs (PLL or PLLSAI1) is not ready
00700   */
00701 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
00702 {
00703   return LL_RCC_GetCLK48ClockFreq(USBxSource);
00704 }
00705 #endif
00706
00707 /**
00708   * @brief  Return RNGx clock frequency
00709   * @param  RNGxSource This parameter can be one of the following values:
00710   *         @arg @ref LL_RCC_RNG_CLKSOURCE
00711   * @retval RNG clock frequency (in Hz)
00712   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI or HSI48) or PLLs (PLL or PLLSAI1) is not ready
00713   */
00714 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
00715 {
00716   uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00717   uint32_t rngClockSource = LL_RCC_GetRNGClockSource(RNGxSource);
00718
00719   /* Check parameter */
00720   assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));
00721
00722   /* RNGCLK clock frequency */
00723   if (rngClockSource == LL_RCC_RNG_CLKSOURCE_LSI) /* LSI clock used as RNG clock source */
00724   {
00725     const uint32_t temp_lsi1Status = LL_RCC_LSI1_IsReady();
00726     const uint32_t temp_lsi2Status = LL_RCC_LSI2_IsReady();
00727     if ((temp_lsi1Status == 1U) || (temp_lsi2Status == 1U))
00728     {
00729       rng_frequency = LSI_VALUE;
00730     }
00731   }
00732   else if (rngClockSource == LL_RCC_RNG_CLKSOURCE_LSE) /* LSE clock used as RNG clock source */
00733   {
00734     if (LL_RCC_LSE_IsReady() == 1U)
00735     {
00736       rng_frequency = LSE_VALUE;
00737     }
00738   }
00739   else /* CLK48 clock used as RNG clock source */
00740   {
00741     /* Systematic Div by 3 */
00742     rng_frequency =  LL_RCC_GetCLK48ClockFreq(LL_RCC_CLK48_CLKSOURCE) / 3U;
00743   }
00744   return rng_frequency;
00745 }
00746
00747 /**
00748   * @brief  Return ADCx clock frequency
00749   * @param  ADCxSource This parameter can be one of the following values:
00750   *         @arg @ref LL_RCC_ADC_CLKSOURCE
00751   * @retval ADC clock frequency (in Hz)
00752   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
00753   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
00754   */
00755 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
00756 {
00757   uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00758
00759   /* Check parameter */
00760   assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
00761
00762   /* ADCCLK clock frequency */
00763   switch (LL_RCC_GetADCClockSource(ADCxSource))
00764   {
00765 #if defined(SAI1)
00766     case LL_RCC_ADC_CLKSOURCE_PLLSAI1:       /* PLLSAI1 clock used as ADC clock source */
00767       if (LL_RCC_PLLSAI1_IsReady() == 1U)
00768       {
00769         adc_frequency = RCC_PLLSAI1_GetFreqDomain_ADC();
00770       }
00771       break;
00772 #endif
00773
00774     case LL_RCC_ADC_CLKSOURCE_SYSCLK:        /* SYSCLK clock used as ADC clock source */
00775       adc_frequency = RCC_GetSystemClockFreq();
00776       break;
00777
00778     case LL_RCC_ADC_CLKSOURCE_PLL:           /* PLL clock used as USB clock source */
00779       if (LL_RCC_PLL_IsReady() == 1U)
00780       {
00781         adc_frequency = RCC_PLL_GetFreqDomain_ADC();
00782       }
00783       break;
00784
00785     case LL_RCC_ADC_CLKSOURCE_NONE:          /* No clock used as ADC clock source */
00786     default:
00787       adc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
00788       break;
00789   }
00790
00791   return adc_frequency;
00792 }
00793
00794 /**
00795   * @brief  Return RTC & LCD clock frequency
00796   * @retval RTC clock frequency (in Hz)
00797   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillators (LSI, LSE or HSE) are not ready
00798   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
00799   */
00800 uint32_t LL_RCC_GetRTCClockFreq(void)
00801 {
00802   uint32_t rtc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00803   uint32_t temp = LL_RCC_LSI2_IsReady();
00804
00805   /* RTCCLK clock frequency */
00806   switch (LL_RCC_GetRTCClockSource())
00807   {
00808     case LL_RCC_RTC_CLKSOURCE_LSE:       /* LSE clock used as RTC clock source */
00809       if (LL_RCC_LSE_IsReady() == 1U)
00810       {
00811         rtc_frequency = LSE_VALUE;
00812       }
00813       break;
00814
00815     case LL_RCC_RTC_CLKSOURCE_LSI:       /* LSI clock used as RTC clock source */
00816
00817       if ((LL_RCC_LSI1_IsReady() == 1UL) || (temp == 1UL))
00818       {
00819         rtc_frequency = LSI_VALUE;
00820       }
00821       break;
00822
00823     case LL_RCC_RTC_CLKSOURCE_HSE_DIV32:        /* HSE clock used as ADC clock source */
00824       rtc_frequency = HSE_VALUE / 32U;
00825       break;
00826
00827     case LL_RCC_RTC_CLKSOURCE_NONE:          /* No clock used as RTC clock source */
00828     default:
00829       rtc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
00830       break;
00831   }
00832
00833   return rtc_frequency;
00834 }
00835
00836 /**
00837   * @brief  Return RF Wakeup clock frequency
00838   * @retval RFWKP clock frequency (in Hz)
00839   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillators (LSI, LSE or HSE) are not ready
00840   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
00841   */
00842 uint32_t LL_RCC_GetRFWKPClockFreq(void)
00843 {
00844   uint32_t rfwkp_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00845   uint32_t temp = LL_RCC_LSI2_IsReady();
00846
00847   /* RTCCLK clock frequency */
00848   switch (LL_RCC_GetRFWKPClockSource())
00849   {
00850     case LL_RCC_RFWKP_CLKSOURCE_LSE:              /* LSE clock used as RF Wakeup clock source */
00851       if (LL_RCC_LSE_IsReady() == 1U)
00852       {
00853         rfwkp_frequency = LSE_VALUE;
00854       }
00855       break;
00856
00857     case LL_RCC_RFWKP_CLKSOURCE_LSI:              /* LSI clock used as RF Wakeup clock source */
00858       if ((LL_RCC_LSI1_IsReady() == 1UL) || (temp == 1UL))
00859       {
00860         rfwkp_frequency = LSI_VALUE;
00861       }
00862       break;
00863
00864     case LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024:       /* HSE clock used as RF Wakeup clock source */
00865       rfwkp_frequency = HSE_VALUE / 1024U;
00866       break;
00867
00868     case LL_RCC_RFWKP_CLKSOURCE_NONE:              /* No clock used as RF Wakeup clock source */
00869     default:
00870       rfwkp_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
00871       break;
00872   }
00873
00874   return rfwkp_frequency;
00875 }
00876
00877
00878 /**
00879   * @}
00880   */
00881
00882 /**
00883   * @}
00884   */
00885
00886 /** @addtogroup RCC_LL_Private_Functions
00887   * @{
00888   */
00889
00890 /**
00891   * @brief  Return SYSTEM clock (SYSCLK) frequency
00892   * @retval SYSTEM clock frequency (in Hz)
00893   */
00894 uint32_t RCC_GetSystemClockFreq(void)
00895 {
00896   uint32_t frequency;
00897
00898   /* Get SYSCLK source -------------------------------------------------------*/
00899   switch (LL_RCC_GetSysClkSource())
00900   {
00901     case LL_RCC_SYS_CLKSOURCE_STATUS_MSI:  /* MSI used as system clock source */
00902       frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
00903       break;
00904
00905     case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:  /* HSI used as system clock  source */
00906       frequency = HSI_VALUE;
00907       break;
00908
00909     case LL_RCC_SYS_CLKSOURCE_STATUS_HSE:  /* HSE used as system clock  source */
00910       if (LL_RCC_HSE_IsEnabledDiv2() == 1U)
00911       {
00912         frequency = HSE_VALUE / 2U;
00913       }
00914       else
00915       {
00916         frequency = HSE_VALUE;
00917       }
00918       break;
00919
00920     case LL_RCC_SYS_CLKSOURCE_STATUS_PLL:  /* PLL used as system clock  source */
00921       frequency = RCC_PLL_GetFreqDomain_SYS();
00922       break;
00923
00924     default:
00925       frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
00926       break;
00927   }
00928
00929   return frequency;
00930 }
00931
00932 /**
00933   * @brief  Return HCLK1 clock frequency
00934   * @param  SYSCLK_Frequency SYSCLK clock frequency
00935   * @retval HCLK1 clock frequency (in Hz)
00936   */
00937 uint32_t RCC_GetHCLK1ClockFreq(uint32_t SYSCLK_Frequency)
00938 {
00939   /* HCLK clock frequency */
00940   return __LL_RCC_CALC_HCLK1_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
00941 }
00942
00943 /**
00944   * @brief  Return HCLK2 clock frequency
00945   * @param  SYSCLK_Frequency SYSCLK clock frequency
00946   * @retval HCLK2 clock frequency (in Hz)
00947   */
00948 uint32_t RCC_GetHCLK2ClockFreq(uint32_t SYSCLK_Frequency)
00949 {
00950   /* HCLK clock frequency */
00951   return __LL_RCC_CALC_HCLK2_FREQ(SYSCLK_Frequency, LL_C2_RCC_GetAHBPrescaler());
00952 }
00953
00954 /**
00955   * @brief  Return HCLK clock frequency
00956   * @param  SYSCLK_Frequency SYSCLK clock frequency
00957   * @retval HCLK4 clock frequency (in Hz)
00958   */
00959 uint32_t RCC_GetHCLK4ClockFreq(uint32_t SYSCLK_Frequency)
00960 {
00961   /* HCLK clock frequency */
00962   return __LL_RCC_CALC_HCLK4_FREQ(SYSCLK_Frequency, LL_RCC_GetAHB4Prescaler());
00963 }
00964
00965 /**
00966   * @brief  Return HCLK5 clock frequency
00967   * @retval HCLK5 clock frequency (in Hz)
00968   */
00969 uint32_t RCC_GetHCLK5ClockFreq(void)
00970 {
00971   uint32_t frequency;
00972
00973   /* Get SYSCLK source -------------------------------------------------------*/
00974   switch (LL_RCC_GetRFClockSource())
00975   {
00976     case LL_RCC_RF_CLKSOURCE_HSI:  /* HSI used as system clock  source */
00977       frequency = HSI_VALUE;
00978       break;
00979
00980     case LL_RCC_RF_CLKSOURCE_HSE_DIV2:  /* HSE Div2 used as system clock source */
00981       frequency = HSE_VALUE / 2U;
00982       break;
00983
00984     default:
00985       frequency = HSI_VALUE;
00986       break;
00987   }
00988
00989   return frequency;
00990
00991 }
00992
00993
00994 /**
00995   * @brief  Return PCLK1 clock frequency
00996   * @param  HCLK_Frequency HCLK clock frequency
00997   * @retval PCLK1 clock frequency (in Hz)
00998   */
00999 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
01000 {
01001   /* PCLK1 clock frequency */
01002   return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
01003 }
01004
01005 /**
01006   * @brief  Return PCLK2 clock frequency
01007   * @param  HCLK_Frequency HCLK clock frequency
01008   * @retval PCLK2 clock frequency (in Hz)
01009   */
01010 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
01011 {
01012   /* PCLK2 clock frequency */
01013   return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
01014 }
01015
01016 /**
01017   * @brief  Return PLL clock (PLLRCLK) frequency used for system domain
01018   * @retval PLLRCLK clock frequency (in Hz)
01019   */
01020 uint32_t RCC_PLL_GetFreqDomain_SYS(void)
01021 {
01022   uint32_t pllinputfreq, pllsource;
01023
01024   /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI Value/ PLLM) * PLLN
01025      SYSCLK = PLL_VCO / PLLR
01026   */
01027   pllsource = LL_RCC_PLL_GetMainSource();
01028
01029   switch (pllsource)
01030   {
01031     case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLL clock source */
01032       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
01033       break;
01034
01035     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
01036       pllinputfreq = HSI_VALUE;
01037       break;
01038
01039     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
01040       if (LL_RCC_HSE_IsEnabledDiv2() == 1U)
01041       {
01042         pllinputfreq = HSE_VALUE / 2U;
01043       }
01044       else
01045       {
01046         pllinputfreq = HSE_VALUE;
01047       }
01048       break;
01049
01050     default:
01051       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
01052       break;
01053   }
01054   return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
01055                                    LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
01056 }
01057
01058 #if defined(SAI1)
01059 /**
01060   * @brief  Return PLL clock (PLLPCLK) frequency used for SAI domain
01061   * @retval PLLPCLK clock frequency (in Hz)
01062   */
01063 uint32_t RCC_PLL_GetFreqDomain_SAI(void)
01064 {
01065   uint32_t pllinputfreq, pllsource;
01066
01067   /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI Value / PLLM) * PLLN
01068      SAI Domain clock = PLL_VCO / PLLP
01069   */
01070   pllsource = LL_RCC_PLL_GetMainSource();
01071
01072   switch (pllsource)
01073   {
01074     case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLL clock source */
01075       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
01076       break;
01077
01078     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
01079       pllinputfreq = HSI_VALUE;
01080       break;
01081
01082     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
01083       if (LL_RCC_HSE_IsEnabledDiv2() == 1U)
01084       {
01085         pllinputfreq = HSE_VALUE / 2U;
01086       }
01087       else
01088       {
01089         pllinputfreq = HSE_VALUE;
01090       }
01091       break;
01092
01093     default:
01094       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
01095       break;
01096   }
01097   return __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
01098                                        LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
01099 }
01100 #endif
01101
01102 /**
01103   * @brief  Return PLL clock (PLLPCLK) frequency used for ADC domain
01104   * @retval PLLPCLK clock frequency (in Hz)
01105   */
01106 uint32_t RCC_PLL_GetFreqDomain_ADC(void)
01107 {
01108   uint32_t pllinputfreq, pllsource;
01109
01110   /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI Value / PLLM) * PLLN
01111      SAI Domain clock = PLL_VCO / PLLP
01112   */
01113   pllsource = LL_RCC_PLL_GetMainSource();
01114
01115   switch (pllsource)
01116   {
01117     case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLL clock source */
01118       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
01119       break;
01120
01121     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
01122       pllinputfreq = HSI_VALUE;
01123       break;
01124
01125     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
01126       if (LL_RCC_HSE_IsEnabledDiv2() == 1U)
01127       {
01128         pllinputfreq = HSE_VALUE / 2U;
01129       }
01130       else
01131       {
01132         pllinputfreq = HSE_VALUE;
01133       }
01134
01135       break;
01136
01137     default:
01138       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
01139       break;
01140   }
01141   return __LL_RCC_CALC_PLLCLK_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
01142                                        LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
01143 }
01144
01145
01146 /**
01147   * @brief  Return PLL clock (PLLQCLK) frequency used for 48 MHz domain
01148   * @retval PLLQCLK clock frequency (in Hz)
01149   */
01150 uint32_t RCC_PLL_GetFreqDomain_48M(void)
01151 {
01152   uint32_t pllinputfreq, pllsource;
01153
01154   /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI Value/ PLLM) * PLLN
01155      48M Domain clock = PLL_VCO / PLLQ
01156   */
01157   pllsource = LL_RCC_PLL_GetMainSource();
01158
01159   switch (pllsource)
01160   {
01161     case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLL clock source */
01162       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
01163       break;
01164
01165     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
01166       pllinputfreq = HSI_VALUE;
01167       break;
01168
01169     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
01170       if (LL_RCC_HSE_IsEnabledDiv2() == 1U)
01171       {
01172         pllinputfreq = HSE_VALUE / 2U;
01173       }
01174       else
01175       {
01176         pllinputfreq = HSE_VALUE;
01177       }
01178
01179       break;
01180
01181     default:
01182       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
01183       break;
01184   }
01185   return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
01186                                        LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
01187 }
01188
01189 #if defined(SAI1)
01190 /**
01191   * @brief  Return PLLSAI1 clock (PLLSAI1PCLK) frequency used for SAI domain
01192   * @retval PLLSAI1PCLK clock frequency (in Hz)
01193   */
01194 uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void)
01195 {
01196   uint32_t pllinputfreq, pllsource;
01197
01198   /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI Value/ PLLM) * PLLSAI1N */
01199   /* SAI Domain clock  = PLLSAI1_VCO / PLLSAI1P */
01200   pllsource = LL_RCC_PLL_GetMainSource();
01201
01202   switch (pllsource)
01203   {
01204     case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLLSAI1 clock source */
01205       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
01206       break;
01207
01208     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI1 clock source */
01209       pllinputfreq = HSI_VALUE;
01210       break;
01211
01212     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI1 clock source */
01213       if (LL_RCC_HSE_IsEnabledDiv2() == 1U)
01214       {
01215         pllinputfreq = HSE_VALUE / 2U;
01216       }
01217       else
01218       {
01219         pllinputfreq = HSE_VALUE;
01220       }
01221
01222       break;
01223
01224     default:
01225       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
01226       break;
01227   }
01228   return __LL_RCC_CALC_PLLSAI1_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
01229                                         LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetP());
01230 }
01231
01232 /**
01233   * @brief  Return PLLSAI1 clock (PLLSAI1QCLK) frequency used for 48Mhz domain
01234   * @retval PLLSAI1QCLK clock frequency (in Hz)
01235   */
01236 uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void)
01237 {
01238   uint32_t pllinputfreq, pllsource;
01239
01240   /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI Value/ PLLM) * PLLSAI1N */
01241   /* 48M Domain clock  = PLLSAI1_VCO / PLLSAI1Q */
01242   pllsource = LL_RCC_PLL_GetMainSource();
01243
01244   switch (pllsource)
01245   {
01246     case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLLSAI1 clock source */
01247       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
01248       break;
01249
01250     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI1 clock source */
01251       pllinputfreq = HSI_VALUE;
01252       break;
01253
01254     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI1 clock source */
01255       if (LL_RCC_HSE_IsEnabledDiv2() == 1U)
01256       {
01257         pllinputfreq = HSE_VALUE / 2U;
01258       }
01259       else
01260       {
01261         pllinputfreq = HSE_VALUE;
01262       }
01263       break;
01264
01265     default:
01266       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
01267       break;
01268   }
01269   return __LL_RCC_CALC_PLLSAI1_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
01270                                         LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetQ());
01271 }
01272
01273 /**
01274   * @brief  Return PLLSAI1 clock (PLLSAI1RCLK) frequency used for ADC domain
01275   * @retval PLLSAI1RCLK clock frequency (in Hz)
01276   */
01277 uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void)
01278 {
01279   uint32_t pllinputfreq, pllsource;
01280
01281   /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI Value/ PLLM) * PLLSAI1N */
01282   /* 48M Domain clock  = PLLSAI1_VCO / PLLSAI1R */
01283   pllsource = LL_RCC_PLL_GetMainSource();
01284
01285   switch (pllsource)
01286   {
01287     case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLLSAI1 clock source */
01288       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
01289       break;
01290
01291     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI1 clock source */
01292       pllinputfreq = HSI_VALUE;
01293       break;
01294
01295     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI1 clock source */
01296       if (LL_RCC_HSE_IsEnabledDiv2() == 1U)
01297       {
01298         pllinputfreq = HSE_VALUE / 2U;
01299       }
01300       else
01301       {
01302         pllinputfreq = HSE_VALUE;
01303       }
01304       break;
01305
01306     default:
01307       pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
01308       break;
01309   }
01310   return __LL_RCC_CALC_PLLSAI1_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
01311                                         LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetR());
01312 }
01313 #endif
01314
01315 /**
01316   * @}
01317   */
01318
01319 /**
01320   * @}
01321   */
01322
01323 #endif /* defined(RCC) */
01324
01325 /**
01326   * @}
01327   */
01328
01329 #endif /* USE_FULL_LL_DRIVER */
01330
01331 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_rcc.h Source File

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stm32wbxx_ll_rcc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_rcc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of RCC LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_LL_RCC_H
00022 #define STM32WBxx_LL_RCC_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx.h"
00030
00031 /** @addtogroup STM32WBxx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined(RCC)
00036
00037 /** @defgroup RCC_LL RCC
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /** @defgroup RCC_LL_Private_Variables RCC Private Variables
00044   * @{
00045   */
00046
00047 #define HSE_CONTROL_UNLOCK_KEY 0xCAFECAFEU
00048
00049 /**
00050   * @}
00051   */
00052
00053 /* Private constants ---------------------------------------------------------*/
00054 /* Private macros ------------------------------------------------------------*/
00055 #if defined(USE_FULL_LL_DRIVER)
00056 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
00057   * @{
00058   */
00059 /**
00060   * @}
00061   */
00062 #endif /*USE_FULL_LL_DRIVER*/
00063
00064 /* Exported types ------------------------------------------------------------*/
00065 #if defined(USE_FULL_LL_DRIVER)
00066 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
00067   * @{
00068   */
00069
00070 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
00071   * @{
00072   */
00073
00074 /**
00075   * @brief  RCC Clocks Frequency Structure
00076   */
00077 typedef struct
00078 {
00079   uint32_t SYSCLK_Frequency;         /*!< SYSCLK clock frequency */
00080   uint32_t HCLK1_Frequency;          /*!< HCLK1 clock frequency  */
00081   uint32_t HCLK2_Frequency;          /*!< HCLK2 clock frequency  */
00082   uint32_t HCLK4_Frequency;          /*!< HCLK4 clock frequency  */
00083   uint32_t HCLK5_Frequency;          /*!< HCLK5 clock frequency */
00084   uint32_t PCLK1_Frequency;          /*!< PCLK1 clock frequency  */
00085   uint32_t PCLK2_Frequency;          /*!< PCLK2 clock frequency  */
00086 } LL_RCC_ClocksTypeDef;
00087
00088 /**
00089   * @}
00090   */
00091
00092 /**
00093   * @}
00094   */
00095 #endif /* USE_FULL_LL_DRIVER */
00096
00097 /* Exported constants --------------------------------------------------------*/
00098 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
00099   * @{
00100   */
00101
00102 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
00103   * @brief    Defines used to adapt values of different oscillators
00104   * @note     These values could be modified in the user environment according to
00105   *           HW set-up.
00106   * @{
00107   */
00108 #if !defined  (HSE_VALUE)
00109 #define HSE_VALUE    32000000U  /*!< Value of the HSE oscillator in Hz */
00110 #endif /* HSE_VALUE */
00111
00112 #if !defined  (HSI_VALUE)
00113 #define HSI_VALUE    16000000U  /*!< Value of the HSI oscillator in Hz */
00114 #endif /* HSI_VALUE */
00115
00116 #if !defined  (LSE_VALUE)
00117 #define LSE_VALUE    32768U     /*!< Value of the LSE oscillator in Hz */
00118 #endif /* LSE_VALUE */
00119
00120 #if !defined  (LSI_VALUE)
00121 #define LSI_VALUE    32000U     /*!< Value of the LSI oscillator in Hz */
00122 #endif /* LSI_VALUE */
00123
00124 #if !defined  (HSI48_VALUE)
00125 #define HSI48_VALUE  48000000U  /*!< Value of the HSI48 oscillator in Hz */
00126 #endif /* HSI48_VALUE */
00127 /**
00128   * @}
00129   */
00130
00131 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
00132   * @brief    Flags defines which can be used with LL_RCC_WriteReg function
00133   * @{
00134   */
00135 #define LL_RCC_CICR_LSI1RDYC               RCC_CICR_LSI1RDYC    /*!< LSI1 Ready Interrupt Clear */
00136 #define LL_RCC_CICR_LSI2RDYC               RCC_CICR_LSI2RDYC    /*!< LSI1 Ready Interrupt Clear */
00137 #define LL_RCC_CICR_LSERDYC                RCC_CICR_LSERDYC     /*!< LSE Ready Interrupt Clear */
00138 #define LL_RCC_CICR_MSIRDYC                RCC_CICR_MSIRDYC     /*!< MSI Ready Interrupt Clear */
00139 #define LL_RCC_CICR_HSIRDYC                RCC_CICR_HSIRDYC     /*!< HSI Ready Interrupt Clear */
00140 #define LL_RCC_CICR_HSERDYC                RCC_CICR_HSERDYC     /*!< HSE Ready Interrupt Clear */
00141 #define LL_RCC_CICR_PLLRDYC                RCC_CICR_PLLRDYC     /*!< PLL Ready Interrupt Clear */
00142 #define LL_RCC_CICR_HSI48RDYC              RCC_CICR_HSI48RDYC   /*!< HSI48 Ready Interrupt Clear */
00143 #if defined(SAI1)
00144 #define LL_RCC_CICR_PLLSAI1RDYC            RCC_CICR_PLLSAI1RDYC /*!< PLLSAI1 Ready Interrupt Clear */
00145 #endif
00146 #define LL_RCC_CICR_LSECSSC                RCC_CICR_LSECSSC     /*!< LSE Clock Security System Interrupt Clear */
00147 #define LL_RCC_CICR_CSSC                   RCC_CICR_CSSC        /*!< Clock Security System Interrupt Clear */
00148 /**
00149   * @}
00150   */
00151
00152 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
00153   * @brief    Flags defines which can be used with LL_RCC_ReadReg function
00154   * @{
00155   */
00156 #define LL_RCC_CIFR_LSI1RDYF               RCC_CIFR_LSI1RDYF    /*!< LSI1 Ready Interrupt flag */
00157 #define LL_RCC_CIFR_LSI2RDYF               RCC_CIFR_LSI2RDYF    /*!< LSI2 Ready Interrupt flag */
00158 #define LL_RCC_CIFR_LSERDYF                RCC_CIFR_LSERDYF     /*!< LSE Ready Interrupt flag */
00159 #define LL_RCC_CIFR_MSIRDYF                RCC_CIFR_MSIRDYF     /*!< MSI Ready Interrupt flag */
00160 #define LL_RCC_CIFR_HSIRDYF                RCC_CIFR_HSIRDYF     /*!< HSI Ready Interrupt flag */
00161 #define LL_RCC_CIFR_HSERDYF                RCC_CIFR_HSERDYF     /*!< HSE Ready Interrupt flag */
00162 #define LL_RCC_CIFR_PLLRDYF                RCC_CIFR_PLLRDYF     /*!< PLL Ready Interrupt flag */
00163 #define LL_RCC_CIFR_HSI48RDYF              RCC_CIFR_HSI48RDYF   /*!< HSI48 Ready Interrupt flag */
00164 #if defined(SAI1)
00165 #define LL_RCC_CIFR_PLLSAI1RDYF            RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */
00166 #endif
00167 #define LL_RCC_CIFR_LSECSSF                RCC_CIFR_LSECSSF     /*!< LSE Clock Security System Interrupt flag */
00168 #define LL_RCC_CIFR_CSSF                   RCC_CIFR_CSSF        /*!< Clock Security System Interrupt flag */
00169 #define LL_RCC_CSR_LPWRRSTF                RCC_CSR_LPWRRSTF     /*!< Low-Power reset flag */
00170 #define LL_RCC_CSR_OBLRSTF                 RCC_CSR_OBLRSTF      /*!< OBL reset flag */
00171 #define LL_RCC_CSR_PINRSTF                 RCC_CSR_PINRSTF      /*!< PIN reset flag */
00172 #define LL_RCC_CSR_SFTRSTF                 RCC_CSR_SFTRSTF      /*!< Software Reset flag */
00173 #define LL_RCC_CSR_IWDGRSTF                RCC_CSR_IWDGRSTF     /*!< Independent Watchdog reset flag */
00174 #define LL_RCC_CSR_WWDGRSTF                RCC_CSR_WWDGRSTF     /*!< Window watchdog reset flag */
00175 #define LL_RCC_CSR_BORRSTF                 RCC_CSR_BORRSTF      /*!< BOR reset flag */
00176 /**
00177   * @}
00178   */
00179
00180 /** @defgroup RCC_LL_EC_IT IT Defines
00181   * @brief    IT defines which can be used with LL_RCC_ReadReg and  LL_RCC_WriteReg functions
00182   * @{
00183   */
00184 #define LL_RCC_CIER_LSI1RDYIE              RCC_CIER_LSI1RDYIE     /*!< LSI1 Ready Interrupt Enable */
00185 #define LL_RCC_CIER_LSI2RDYIE              RCC_CIER_LSI2RDYIE     /*!< LSI Ready Interrupt Enable */
00186 #define LL_RCC_CIER_LSERDYIE               RCC_CIER_LSERDYIE      /*!< LSE Ready Interrupt Enable */
00187 #define LL_RCC_CIER_MSIRDYIE               RCC_CIER_MSIRDYIE      /*!< MSI Ready Interrupt Enable */
00188 #define LL_RCC_CIER_HSIRDYIE               RCC_CIER_HSIRDYIE      /*!< HSI Ready Interrupt Enable */
00189 #define LL_RCC_CIER_HSERDYIE               RCC_CIER_HSERDYIE      /*!< HSE Ready Interrupt Enable */
00190 #define LL_RCC_CIER_PLLRDYIE               RCC_CIER_PLLRDYIE      /*!< PLL Ready Interrupt Enable */
00191 #define LL_RCC_CIER_HSI48RDYIE             RCC_CIER_HSI48RDYIE    /*!< HSI48 Ready Interrupt Enable */
00192 #if defined(SAI1)
00193 #define LL_RCC_CIER_PLLSAI1RDYIE           RCC_CIER_PLLSAI1RDYIE  /*!< PLLSAI1 Ready Interrupt Enable */
00194 #endif
00195 #define LL_RCC_CIER_LSECSSIE               RCC_CIER_LSECSSIE      /*!< LSE CSS Interrupt Enable */
00196 /**
00197   * @}
00198   */
00199
00200 /** @defgroup RCC_LL_EC_LSEDRIVE  LSE oscillator drive capability
00201   * @{
00202   */
00203 #define LL_RCC_LSEDRIVE_LOW                0x00000000U             /*!< Xtal mode lower driving capability */
00204 #define LL_RCC_LSEDRIVE_MEDIUMLOW          RCC_BDCR_LSEDRV_0       /*!< Xtal mode medium low driving capability */
00205 #define LL_RCC_LSEDRIVE_MEDIUMHIGH         RCC_BDCR_LSEDRV_1       /*!< Xtal mode medium high driving capability */
00206 #define LL_RCC_LSEDRIVE_HIGH               RCC_BDCR_LSEDRV         /*!< Xtal mode higher driving capability */
00207 /**
00208   * @}
00209   */
00210
00211 /** @defgroup RCC_LL_EC_MSIRANGE  MSI clock ranges
00212   * @{
00213   */
00214 #define LL_RCC_MSIRANGE_0                  RCC_CR_MSIRANGE_0  /*!< MSI = 100 KHz  */
00215 #define LL_RCC_MSIRANGE_1                  RCC_CR_MSIRANGE_1  /*!< MSI = 200 KHz  */
00216 #define LL_RCC_MSIRANGE_2                  RCC_CR_MSIRANGE_2  /*!< MSI = 400 KHz  */
00217 #define LL_RCC_MSIRANGE_3                  RCC_CR_MSIRANGE_3  /*!< MSI = 800 KHz  */
00218 #define LL_RCC_MSIRANGE_4                  RCC_CR_MSIRANGE_4  /*!< MSI = 1 MHz    */
00219 #define LL_RCC_MSIRANGE_5                  RCC_CR_MSIRANGE_5  /*!< MSI = 2 MHz    */
00220 #define LL_RCC_MSIRANGE_6                  RCC_CR_MSIRANGE_6  /*!< MSI = 4 MHz    */
00221 #define LL_RCC_MSIRANGE_7                  RCC_CR_MSIRANGE_7  /*!< MSI = 8 MHz    */
00222 #define LL_RCC_MSIRANGE_8                  RCC_CR_MSIRANGE_8  /*!< MSI = 16 MHz   */
00223 #define LL_RCC_MSIRANGE_9                  RCC_CR_MSIRANGE_9  /*!< MSI = 24 MHz   */
00224 #define LL_RCC_MSIRANGE_10                 RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz   */
00225 #define LL_RCC_MSIRANGE_11                 RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz   */
00226 /**
00227   * @}
00228   */
00229
00230
00231 /** @defgroup RCC_LL_EC_HSE_CURRENT_CONTROL  HSE current control max limits
00232   * @{
00233   */
00234 #define LL_RCC_HSE_CURRENTMAX_0            0x000000000U                               /*!< HSE current control max limit = 0.18 ma/V*/
00235 #define LL_RCC_HSE_CURRENTMAX_1            RCC_HSECR_HSEGMC0                          /*!< HSE current control max limit = 0.57 ma/V*/
00236 #define LL_RCC_HSE_CURRENTMAX_2            RCC_HSECR_HSEGMC1                          /*!< HSE current control max limit = 0.78 ma/V*/
00237 #define LL_RCC_HSE_CURRENTMAX_3            (RCC_HSECR_HSEGMC1|RCC_HSECR_HSEGMC0)      /*!< HSE current control max limit = 1.13 ma/V*/
00238 #define LL_RCC_HSE_CURRENTMAX_4            RCC_HSECR_HSEGMC2                          /*!< HSE current control max limit = 0.61 ma/V*/
00239 #define LL_RCC_HSE_CURRENTMAX_5            (RCC_HSECR_HSEGMC2|RCC_HSECR_HSEGMC0)      /*!< HSE current control max limit = 1.65 ma/V*/
00240 #define LL_RCC_HSE_CURRENTMAX_6            (RCC_HSECR_HSEGMC2|RCC_HSECR_HSEGMC1)      /*!< HSE current control max limit = 2.12 ma/V*/
00241 #define LL_RCC_HSE_CURRENTMAX_7            (RCC_HSECR_HSEGMC2|RCC_HSECR_HSEGMC1|RCC_HSECR_HSEGMC0) /*!< HSE current control max limit = 2.84 ma/V*/
00242 /**
00243   * @}
00244   */
00245
00246 /** @defgroup RCC_LL_EC_HSE_SENSE_AMPLIFIER  HSE sense amplifier threshold
00247   * @{
00248   */
00249 #define LL_RCC_HSEAMPTHRESHOLD_1_2         (0x000000000U)                          /*!< HSE sense amplifier bias current factor = 1/2*/
00250 #define LL_RCC_HSEAMPTHRESHOLD_3_4         RCC_HSECR_HSES                          /*!< HSE sense amplifier bias current factor = 3/4*/
00251 /**
00252   * @}
00253   */
00254
00255 /** @defgroup RCC_LL_EC_LSCO_CLKSOURCE  LSCO Selection
00256   * @{
00257   */
00258 #define LL_RCC_LSCO_CLKSOURCE_LSI          0x00000000U           /*!< LSI selection for low speed clock  */
00259 #define LL_RCC_LSCO_CLKSOURCE_LSE          RCC_BDCR_LSCOSEL      /*!< LSE selection for low speed clock  */
00260 /**
00261   * @}
00262   */
00263
00264 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE  System clock switch
00265   * @{
00266   */
00267 #define LL_RCC_SYS_CLKSOURCE_MSI           0x00000000U    /*!< MSI selection as system clock */
00268 #define LL_RCC_SYS_CLKSOURCE_HSI           RCC_CFGR_SW_0    /*!< HSI selection as system clock */
00269 #define LL_RCC_SYS_CLKSOURCE_HSE           RCC_CFGR_SW_1    /*!< HSE selection as system clock */
00270 #define LL_RCC_SYS_CLKSOURCE_PLL           (RCC_CFGR_SW_1 | RCC_CFGR_SW_0)    /*!< PLL selection as system clock */
00271 /**
00272   * @}
00273   */
00274
00275 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS  System clock switch status
00276   * @{
00277   */
00278 #define LL_RCC_SYS_CLKSOURCE_STATUS_MSI    0x00000000U   /*!< MSI used as system clock */
00279 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_0   /*!< HSI used as system clock */
00280 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_1   /*!< HSE used as system clock */
00281 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL    (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0)   /*!< PLL used as system clock */
00282 /**
00283   * @}
00284   */
00285
00286 /** @defgroup RCC_LL_EC_RF_CLKSOURCE_STATUS  RF system clock switch status
00287   * @{
00288   */
00289 #define LL_RCC_RF_CLKSOURCE_HSI            0x00000000U        /*!< HSI used as RF system clock */
00290 #define LL_RCC_RF_CLKSOURCE_HSE_DIV2       RCC_EXTCFGR_RFCSS  /*!< HSE divided by 2 used as RF system clock */
00291 /**
00292   * @}
00293   */
00294
00295
00296 /** @defgroup RCC_LL_EC_SYSCLK_DIV  AHB prescaler
00297   * @{
00298   */
00299 #define LL_RCC_SYSCLK_DIV_1                0x00000000U   /*!< SYSCLK not divided */
00300 #define LL_RCC_SYSCLK_DIV_2                RCC_CFGR_HPRE_3   /*!< SYSCLK divided by 2 */
00301 #define LL_RCC_SYSCLK_DIV_3                RCC_CFGR_HPRE_0   /*!< SYSCLK divided by 3 */
00302 #define LL_RCC_SYSCLK_DIV_4                (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0)   /*!< SYSCLK divided by 4 */
00303 #define LL_RCC_SYSCLK_DIV_5                RCC_CFGR_HPRE_1   /*!< SYSCLK divided by 5 */
00304 #define LL_RCC_SYSCLK_DIV_6                (RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0)   /*!< SYSCLK divided by 6 */
00305 #define LL_RCC_SYSCLK_DIV_8                (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1)   /*!< SYSCLK divided by 8 */
00306 #define LL_RCC_SYSCLK_DIV_10               (RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1)  /*!< SYSCLK divided by 10 */
00307 #define LL_RCC_SYSCLK_DIV_16               (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0)  /*!< SYSCLK divided by 16 */
00308 #define LL_RCC_SYSCLK_DIV_32               (RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0)  /*!< SYSCLK divided by 32 */
00309 #define LL_RCC_SYSCLK_DIV_64               (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2)  /*!< SYSCLK divided by 64 */
00310 #define LL_RCC_SYSCLK_DIV_128              (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 128 */
00311 #define LL_RCC_SYSCLK_DIV_256              (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 256 */
00312 #define LL_RCC_SYSCLK_DIV_512              (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 512 */
00313 /**
00314   * @}
00315   */
00316
00317 /** @defgroup RCC_LL_EC_APB1_DIV  APB low-speed prescaler (APB1)
00318   * @{
00319   */
00320 #define LL_RCC_APB1_DIV_1                  0x00000000U                            /*!< HCLK1 not divided */
00321 #define LL_RCC_APB1_DIV_2                  RCC_CFGR_PPRE1_2                       /*!< HCLK1 divided by 2 */
00322 #define LL_RCC_APB1_DIV_4                  (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_0)  /*!< HCLK1 divided by 4 */
00323 #define LL_RCC_APB1_DIV_8                  (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_1)  /*!< HCLK1 divided by 8 */
00324 #define LL_RCC_APB1_DIV_16                 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_1 | RCC_CFGR_PPRE1_0) /*!< HCLK1 divided by 16 */
00325 /**
00326   * @}
00327   */
00328
00329 /** @defgroup RCC_LL_EC_APB2_DIV  APB high-speed prescaler (APB2)
00330   * @{
00331   */
00332 #define LL_RCC_APB2_DIV_1                  0x00000000U                            /*!< HCLK1 not divided */
00333 #define LL_RCC_APB2_DIV_2                  RCC_CFGR_PPRE2_2                       /*!< HCLK1 divided by 2 */
00334 #define LL_RCC_APB2_DIV_4                  (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_0)  /*!< HCLK1 divided by 4 */
00335 #define LL_RCC_APB2_DIV_8                  (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_1)  /*!< HCLK1 divided by 8 */
00336 #define LL_RCC_APB2_DIV_16                 (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_1 | RCC_CFGR_PPRE2_0) /*!< HCLK1 divided by 16 */
00337 /**
00338   * @}
00339   */
00340
00341 /** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK  Wakeup from Stop and CSS backup clock selection
00342   * @{
00343   */
00344 #define LL_RCC_STOP_WAKEUPCLOCK_MSI        0x00000000U             /*!< MSI selection after wake-up from STOP */
00345 #define LL_RCC_STOP_WAKEUPCLOCK_HSI        RCC_CFGR_STOPWUCK       /*!< HSI selection after wake-up from STOP */
00346 /**
00347   * @}
00348   */
00349
00350 /** @defgroup RCC_LL_EC_MCO1SOURCE  MCO1 SOURCE selection
00351   * @{
00352   */
00353 #define LL_RCC_MCO1SOURCE_NOCLOCK          0x00000000U                                   /*!< MCO output disabled, no clock on MCO */
00354 #define LL_RCC_MCO1SOURCE_SYSCLK           RCC_CFGR_MCOSEL_0                             /*!< SYSCLK selection as MCO1 source */
00355 #define LL_RCC_MCO1SOURCE_MSI              RCC_CFGR_MCOSEL_1                             /*!< MSI selection as MCO1 source */
00356 #define LL_RCC_MCO1SOURCE_HSI              (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1)        /*!< HSI selection as MCO1 source */
00357 #define LL_RCC_MCO1SOURCE_HSE              RCC_CFGR_MCOSEL_2                             /*!< HSE after stabilization selection as MCO1 source */
00358 #define LL_RCC_MCO1SOURCE_PLLCLK           (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)         /*!< Main PLL selection as MCO1 source */
00359 #define LL_RCC_MCO1SOURCE_LSI1             (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)         /*!< LSI1 selection as MCO1 source */
00360 #define LL_RCC_MCO1SOURCE_LSI2             (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI2 selection as MCO1 source */
00361 #define LL_RCC_MCO1SOURCE_LSE              RCC_CFGR_MCOSEL_3                            /*!< LSE selection as MCO1 source */
00362 #define LL_RCC_MCO1SOURCE_HSI48            (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_3)        /*!< HSI48 selection as MCO1 source */
00363 #define LL_RCC_MCO1SOURCE_HSE_BEFORE_STAB  (RCC_CFGR_MCOSEL_2|RCC_CFGR_MCOSEL_3)        /*!< HSE before stabilization selection as MCO1 source */
00364 /**
00365   * @}
00366   */
00367
00368 /** @defgroup RCC_LL_EC_MCO1_DIV  MCO1 prescaler
00369   * @{
00370   */
00371 #define LL_RCC_MCO1_DIV_1                  0x00000000U                                   /*!< MCO not divided */
00372 #define LL_RCC_MCO1_DIV_2                  RCC_CFGR_MCOPRE_0                             /*!< MCO divided by 2 */
00373 #define LL_RCC_MCO1_DIV_4                  RCC_CFGR_MCOPRE_1                             /*!< MCO divided by 4 */
00374 #define LL_RCC_MCO1_DIV_8                  (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0)       /*!< MCO divided by 8 */
00375 #define LL_RCC_MCO1_DIV_16                 RCC_CFGR_MCOPRE_2                             /*!< MCO divided by 16 */
00376 /**
00377   * @}
00378   */
00379
00380 /** @defgroup RCC_LL_EC_SMPS_CLKSOURCE  SMPS clock switch
00381   * @{
00382   */
00383 #define LL_RCC_SMPS_CLKSOURCE_HSI           0x00000000U             /*!< HSI selection as SMPS clock */
00384 #define LL_RCC_SMPS_CLKSOURCE_MSI           RCC_SMPSCR_SMPSSEL_0    /*!< MSI selection as SMPS clock */
00385 #define LL_RCC_SMPS_CLKSOURCE_HSE           RCC_SMPSCR_SMPSSEL_1    /*!< HSE selection as SMPS clock */
00386
00387 /**
00388   * @}
00389   */
00390
00391 /** @defgroup RCC_LL_EC_SMPS_CLKSOURCE_STATUS  SMPS clock switch status
00392   * @{
00393   */
00394 #define LL_RCC_SMPS_CLKSOURCE_STATUS_HSI       0x00000000U                                   /*!< HSI used as SMPS clock */
00395 #define LL_RCC_SMPS_CLKSOURCE_STATUS_MSI       RCC_SMPSCR_SMPSSWS_0                          /*!< MSI used as SMPS clock */
00396 #define LL_RCC_SMPS_CLKSOURCE_STATUS_HSE       RCC_SMPSCR_SMPSSWS_1                          /*!< HSE used as SMPS clock */
00397 #define LL_RCC_SMPS_CLKSOURCE_STATUS_NO_CLOCK  (RCC_SMPSCR_SMPSSWS_0|RCC_SMPSCR_SMPSSWS_1)   /*!< No Clock used as SMPS clock */
00398
00399 /**
00400   * @}
00401   */
00402
00403 /** @defgroup RCC_LL_EC_SMPS_DIV  SMPS prescaler
00404     * @{
00405     */
00406 #define LL_RCC_SMPS_DIV_0                  (0x00000000U)                                     /*!< SMPS clock division 0 */
00407 #define LL_RCC_SMPS_DIV_1                  RCC_SMPSCR_SMPSDIV_0                              /*!< SMPS clock division 1 */
00408 #define LL_RCC_SMPS_DIV_2                  RCC_SMPSCR_SMPSDIV_1                              /*!< SMPS clock division 2 */
00409 #define LL_RCC_SMPS_DIV_3                  (RCC_SMPSCR_SMPSDIV_0|RCC_SMPSCR_SMPSDIV_1)       /*!< SMPS clock division 3 */
00410
00411 /**
00412     * @}
00413     */
00414
00415
00416
00417
00418 #if defined(USE_FULL_LL_DRIVER)
00419 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
00420   * @{
00421   */
00422 #define LL_RCC_PERIPH_FREQUENCY_NO         0x00000000U                 /*!< No clock enabled for the peripheral            */
00423 #define LL_RCC_PERIPH_FREQUENCY_NA         0xFFFFFFFFU                 /*!< Frequency cannot be provided as external clock */
00424 /**
00425   * @}
00426   */
00427 #endif /* USE_FULL_LL_DRIVER */
00428
00429 /** @defgroup RCC_LL_EC_USART1_CLKSOURCE USART1 CLKSOURCE
00430   * @{
00431   */
00432 #define LL_RCC_USART1_CLKSOURCE_PCLK2      0x00000000U                /*!< PCLK2 selected as USART1 clock */
00433 #define LL_RCC_USART1_CLKSOURCE_SYSCLK     RCC_CCIPR_USART1SEL_0      /*!< SYSCLK selected as USART1 clock */
00434 #define LL_RCC_USART1_CLKSOURCE_HSI        RCC_CCIPR_USART1SEL_1      /*!< HSI selected as USART1 clock */
00435 #define LL_RCC_USART1_CLKSOURCE_LSE        RCC_CCIPR_USART1SEL        /*!< LSE selected as USART1 clock */
00436 /**
00437   * @}
00438   */
00439
00440 /** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE LPUART1 CLKSOURCE
00441   * @{
00442   */
00443 #define LL_RCC_LPUART1_CLKSOURCE_PCLK1     0x00000000U               /*!< PCLK1 selected as LPUART1 clock */
00444 #define LL_RCC_LPUART1_CLKSOURCE_SYSCLK    RCC_CCIPR_LPUART1SEL_0    /*!< SYCLK selected as LPUART1 clock */
00445 #define LL_RCC_LPUART1_CLKSOURCE_HSI       RCC_CCIPR_LPUART1SEL_1    /*!< HSI selected as LPUART1 clock */
00446 #define LL_RCC_LPUART1_CLKSOURCE_LSE       RCC_CCIPR_LPUART1SEL      /*!< LSE selected as LPUART1 clock */
00447 /**
00448   * @}
00449   */
00450
00451 /** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE I2Cx CLKSOURCE
00452   * @{
00453   */
00454 #define LL_RCC_I2C1_CLKSOURCE_PCLK1        (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (0x00000000U >> 4))         /*!< PCLK1 selected as I2C1 clock */
00455 #define LL_RCC_I2C1_CLKSOURCE_SYSCLK       (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_0 >> 4)) /*!< SYSCLK selected as I2C1 clock */
00456 #define LL_RCC_I2C1_CLKSOURCE_HSI          (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_1 >> 4)) /*!< HSI selected as I2C1 clock */
00457 #if defined(I2C3)
00458 #define LL_RCC_I2C3_CLKSOURCE_PCLK1        (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (0x00000000U >> 4))         /*!< PCLK1 selected as I2C3 clock */
00459 #define LL_RCC_I2C3_CLKSOURCE_SYSCLK       (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_0 >> 4)) /*!< SYSCLK selected as I2C3 clock */
00460 #define LL_RCC_I2C3_CLKSOURCE_HSI          (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_1 >> 4)) /*!< HSI selected as I2C3 clock */
00461 #endif
00462 /**
00463   * @}
00464   */
00465
00466 /** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE LPTIMx CLKSOURCE
00467   * @{
00468   */
00469 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1      (uint32_t)(RCC_CCIPR_LPTIM1SEL | (0x00000000U >> 16))           /*!< PCLK1 selected as LPTIM1 clock */
00470 #define LL_RCC_LPTIM1_CLKSOURCE_LSI        (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16)) /*!< LSI selected as LPTIM1 clock */
00471 #define LL_RCC_LPTIM1_CLKSOURCE_HSI        (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16)) /*!< HSI selected as LPTIM1 clock */
00472 #define LL_RCC_LPTIM1_CLKSOURCE_LSE        (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16))   /*!< LSE selected as LPTIM1 clock */
00473 #define LL_RCC_LPTIM2_CLKSOURCE_PCLK1      (uint32_t)(RCC_CCIPR_LPTIM2SEL | (0x00000000U >> 16))           /*!< PCLK1 selected as LPTIM2 clock */
00474 #define LL_RCC_LPTIM2_CLKSOURCE_LSI        (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16)) /*!< LSI selected as LPTIM2 clock */
00475 #define LL_RCC_LPTIM2_CLKSOURCE_HSI        (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16)) /*!< HSI selected as LPTIM2 clock */
00476 #define LL_RCC_LPTIM2_CLKSOURCE_LSE        (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16))   /*!< LSE selected as LPTIM2 clock */
00477 /**
00478   * @}
00479   */
00480
00481 /** @defgroup RCC_LL_EC_SAI1_CLKSOURCE SAI1 CLKSOURCE
00482   * @{
00483   */
00484 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI1      0x00000000U            /*!< PLLSAI1 selected as SAI1 clock */
00485 #define LL_RCC_SAI1_CLKSOURCE_PLL          RCC_CCIPR_SAI1SEL_0    /*!< PLL selected as SAI1 clock */
00486 #define LL_RCC_SAI1_CLKSOURCE_HSI          RCC_CCIPR_SAI1SEL_1    /*!< HSI selected as SAI1 clock */
00487 #define LL_RCC_SAI1_CLKSOURCE_PIN          RCC_CCIPR_SAI1SEL      /*!< External input selected as SAI1 clock */
00488 /**
00489   * @}
00490   */
00491
00492 /** @defgroup RCC_LL_EC_CLK48_CLKSOURCE CLK48 CLKSOURCE
00493   * @{
00494   */
00495 #define LL_RCC_CLK48_CLKSOURCE_HSI48       0x00000000U           /*!< HSI48 selected as CLK48 clock*/
00496 #if defined(SAI1)
00497 #define LL_RCC_CLK48_CLKSOURCE_PLLSAI1     RCC_CCIPR_CLK48SEL_0  /*!< PLLSAI1 selected as CLK48 clock*/
00498 #endif
00499 #define LL_RCC_CLK48_CLKSOURCE_PLL         RCC_CCIPR_CLK48SEL_1  /*!< PLL selected as CLK48 clock*/
00500 #define LL_RCC_CLK48_CLKSOURCE_MSI         RCC_CCIPR_CLK48SEL    /*!< MSI selected as CLK48 clock*/
00501 /**
00502   * @}
00503   */
00504
00505 /** @defgroup RCC_LL_EC_USB_CLKSOURCE USB CLKSOURCE
00506   * @{
00507   */
00508 #define LL_RCC_USB_CLKSOURCE_HSI48         LL_RCC_CLK48_CLKSOURCE_HSI48    /*!< HSI48 selected as USB clock*/
00509 #if defined(SAI1)
00510 #define LL_RCC_USB_CLKSOURCE_PLLSAI1       LL_RCC_CLK48_CLKSOURCE_PLLSAI1  /*!< PLLSAI1 selected as USB clock*/
00511 #endif
00512 #define LL_RCC_USB_CLKSOURCE_PLL           LL_RCC_CLK48_CLKSOURCE_PLL      /*!< PLL selected as USB clock*/
00513 #define LL_RCC_USB_CLKSOURCE_MSI           LL_RCC_CLK48_CLKSOURCE_MSI      /*!< MSI selected as USB clock*/
00514 /**
00515   * @}
00516   */
00517
00518 /** @defgroup RCC_LL_EC_ADC_CLKSRC ADC CLKSRC
00519   * @{
00520   */
00521 #define LL_RCC_ADC_CLKSOURCE_NONE             0x00000000U        /*!< no Clock used as ADC clock*/
00522 #if defined(SAI1)
00523 #define LL_RCC_ADC_CLKSOURCE_PLLSAI1          RCC_CCIPR_ADCSEL_0 /*!< PLLSAI1 selected as ADC clock*/
00524 #endif
00525 #define LL_RCC_ADC_CLKSOURCE_PLL              RCC_CCIPR_ADCSEL_1 /*!< PLL selected as ADC clock*/
00526 #define LL_RCC_ADC_CLKSOURCE_SYSCLK           RCC_CCIPR_ADCSEL   /*!< SYSCLK selected as ADC clock*/
00527 /**
00528   * @}
00529   */
00530
00531 /** @defgroup RCC_LL_EC_RNG_CLKSRC RNG CLKSRC
00532   * @{
00533   */
00534 #define LL_RCC_RNG_CLKSOURCE_CLK48            0x00000000U        /*!< CLK48 divided by 3 selected as RNG Clock */
00535 #define LL_RCC_RNG_CLKSOURCE_LSI              RCC_CCIPR_RNGSEL_0 /*!< LSI selected as ADC clock*/
00536 #define LL_RCC_RNG_CLKSOURCE_LSE              RCC_CCIPR_RNGSEL_1 /*!< LSE selected as ADC clock*/
00537 /**
00538   * @}
00539   */
00540
00541 /** @defgroup RCC_LL_EC_USART1 USART1
00542   * @{
00543   */
00544 #define LL_RCC_USART1_CLKSOURCE            RCC_CCIPR_USART1SEL   /*!< USART1 clock source selection bits */
00545 /**
00546   * @}
00547   */
00548
00549 #if defined(LPUART1)
00550 /** @defgroup RCC_LL_EC_LPUART1 LPUART1
00551   * @{
00552   */
00553 #define LL_RCC_LPUART1_CLKSOURCE           RCC_CCIPR_LPUART1SEL  /*!< LPUART1 clock source selection bits */
00554 /**
00555   * @}
00556   */
00557 #endif
00558
00559 /** @defgroup RCC_LL_EC_I2C1 I2C1
00560   * @{
00561   */
00562 #define LL_RCC_I2C1_CLKSOURCE              RCC_CCIPR_I2C1SEL    /*!< I2C1 clock source selection bits */
00563 #define LL_RCC_I2C3_CLKSOURCE              RCC_CCIPR_I2C3SEL    /*!< I2C3 clock source selection bits */
00564 /**
00565   * @}
00566   */
00567
00568 /** @defgroup RCC_LL_EC_LPTIM1 LPTIM1
00569   * @{
00570   */
00571 #define LL_RCC_LPTIM1_CLKSOURCE            RCC_CCIPR_LPTIM1SEL  /*!< LPTIM1 clock source selection bits */
00572 #define LL_RCC_LPTIM2_CLKSOURCE            RCC_CCIPR_LPTIM2SEL  /*!< LPTIM2 clock source selection bits */
00573 /**
00574   * @}
00575   */
00576
00577 #if defined(SAI1)
00578 /** @defgroup RCC_LL_EC_SAI1 SAI1
00579   * @{
00580   */
00581 #define LL_RCC_SAI1_CLKSOURCE              RCC_CCIPR_SAI1SEL   /*!< SAI1 clock source selection bits */
00582 /**
00583   * @}
00584   */
00585 #endif
00586
00587 /** @defgroup RCC_LL_EC_CLK48 CLK48
00588   * @{
00589   */
00590 #define LL_RCC_CLK48_CLKSOURCE             RCC_CCIPR_CLK48SEL  /*!< USB clock source selection bits */
00591 /**
00592   * @}
00593   */
00594
00595 /** @defgroup RCC_LL_EC_USB USB
00596   * @{
00597   */
00598 #define LL_RCC_USB_CLKSOURCE               LL_RCC_CLK48_CLKSOURCE  /*!< USB clock source selection bits */
00599 /**
00600   * @}
00601   */
00602
00603 /** @defgroup RCC_LL_EC_RNG RNG
00604   * @{
00605   */
00606 #define LL_RCC_RNG_CLKSOURCE               RCC_CCIPR_RNGSEL  /*!< RNG clock source selection bits */
00607 /**
00608   * @}
00609   */
00610
00611 /** @defgroup RCC_LL_EC_ADC ADC
00612   * @{
00613   */
00614 #define LL_RCC_ADC_CLKSOURCE               RCC_CCIPR_ADCSEL   /*!< ADC clock source selection bits */
00615 /**
00616   * @}
00617   */
00618
00619 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE  RTC clock source selection
00620   * @{
00621   */
00622 #define LL_RCC_RTC_CLKSOURCE_NONE          0x00000000U                   /*!< No clock used as RTC clock */
00623 #define LL_RCC_RTC_CLKSOURCE_LSE           RCC_BDCR_RTCSEL_0             /*!< LSE oscillator clock used as RTC clock */
00624 #define LL_RCC_RTC_CLKSOURCE_LSI           RCC_BDCR_RTCSEL_1             /*!< LSI oscillator clock used as RTC clock */
00625 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32     RCC_BDCR_RTCSEL               /*!< HSE oscillator clock divided by 32 used as RTC clock */
00626
00627 /**
00628   * @}
00629   */
00630
00631 /** @defgroup RCC_LL_EC_RFWKP_CLKSOURCE  RF Wakeup clock source selection
00632   * @{
00633   */
00634 #define LL_RCC_RFWKP_CLKSOURCE_NONE          0x00000000U                   /*!< No clock used as RF Wakeup clock */
00635 #define LL_RCC_RFWKP_CLKSOURCE_LSE           RCC_CSR_RFWKPSEL_0             /*!< LSE oscillator clock used as RF Wakeup clock */
00636 #define LL_RCC_RFWKP_CLKSOURCE_LSI           RCC_CSR_RFWKPSEL_1             /*!< LSI oscillator clock used as RF Wakeup clock */
00637 #define LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024   RCC_CSR_RFWKPSEL               /*!< HSE oscillator clock divided by 1024 used as RF Wakeup clock */
00638
00639 /**
00640   * @}
00641   */
00642
00643
00644 /** @defgroup RCC_LL_EC_PLLSOURCE  PLL and PLLSAI1 entry clock source
00645   * @{
00646   */
00647 #define LL_RCC_PLLSOURCE_NONE              0x00000000U             /*!< No clock */
00648 #define LL_RCC_PLLSOURCE_MSI               RCC_PLLCFGR_PLLSRC_0  /*!< MSI clock selected as PLL entry clock source */
00649 #define LL_RCC_PLLSOURCE_HSI               RCC_PLLCFGR_PLLSRC_1  /*!< HSI clock selected as PLL entry clock source */
00650 #define LL_RCC_PLLSOURCE_HSE               (RCC_PLLCFGR_PLLSRC_1 | RCC_PLLCFGR_PLLSRC_0)  /*!< HSE clock selected as PLL entry clock source */
00651 /**
00652   * @}
00653   */
00654
00655 /** @defgroup RCC_LL_EC_PLLM_DIV  PLL and PLLSAI1 division factor
00656   * @{
00657   */
00658 #define LL_RCC_PLLM_DIV_1                  0x00000000U                                 /*!< PLL and PLLSAI1 division factor by 1 */
00659 #define LL_RCC_PLLM_DIV_2                  (RCC_PLLCFGR_PLLM_0)                        /*!< PLL and PLLSAI1 division factor by 2 */
00660 #define LL_RCC_PLLM_DIV_3                  (RCC_PLLCFGR_PLLM_1)                        /*!< PLL and PLLSAI1 division factor by 3 */
00661 #define LL_RCC_PLLM_DIV_4                  ((RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)) /*!< PLL and PLLSAI1 division factor by 4 */
00662 #define LL_RCC_PLLM_DIV_5                  (RCC_PLLCFGR_PLLM_2)                        /*!< PLL and PLLSAI1 division factor by 5 */
00663 #define LL_RCC_PLLM_DIV_6                  ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)) /*!< PLL and PLLSAI1 division factor by 6 */
00664 #define LL_RCC_PLLM_DIV_7                  ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)) /*!< PLL and PLLSAI1 division factor by 7 */
00665 #define LL_RCC_PLLM_DIV_8                  (RCC_PLLCFGR_PLLM)                          /*!< PLL and PLLSAI1 division factor by 8 */
00666 /**
00667   * @}
00668   */
00669
00670 /** @defgroup RCC_LL_EC_PLLR_DIV  PLL division factor (PLLR)
00671   * @{
00672   */
00673 #define LL_RCC_PLLR_DIV_2                  (RCC_PLLCFGR_PLLR_0)                     /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
00674 #define LL_RCC_PLLR_DIV_3                  (RCC_PLLCFGR_PLLR_1)                     /*!< Main PLL division factor for PLLCLK (system clock) by 3 */
00675 #define LL_RCC_PLLR_DIV_4                  (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0)  /*!< Main PLL division factor for PLLCLK (system clock) by 4 */
00676 #define LL_RCC_PLLR_DIV_5                  (RCC_PLLCFGR_PLLR_2)                     /*!< Main PLL division factor for PLLCLK (system clock) by 5 */
00677 #define LL_RCC_PLLR_DIV_6                  (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0)  /*!< Main PLL division factor for PLLCLK (system clock) by 6 */
00678 #define LL_RCC_PLLR_DIV_7                  (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1)  /*!< Main PLL division factor for PLLCLK (system clock) by 7 */
00679 #define LL_RCC_PLLR_DIV_8                  (RCC_PLLCFGR_PLLR)                       /*!< Main PLL division factor for PLLCLK (system clock) by 8 */
00680 /**
00681   * @}
00682   */
00683
00684 /** @defgroup RCC_LL_EC_PLLP_DIV  PLL division factor (PLLP)
00685   * @{
00686   */
00687 #define LL_RCC_PLLP_DIV_2                  (RCC_PLLCFGR_PLLP_0)                                              /*!< Main PLL division factor for PLLP output by 2 */
00688 #define LL_RCC_PLLP_DIV_3                  (RCC_PLLCFGR_PLLP_1)                                              /*!< Main PLL division factor for PLLP output by 3 */
00689 #define LL_RCC_PLLP_DIV_4                  (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1)                           /*!< Main PLL division factor for PLLP output by 4 */
00690 #define LL_RCC_PLLP_DIV_5                  (RCC_PLLCFGR_PLLP_2)                                              /*!< Main PLL division factor for PLLP output by 5 */
00691 #define LL_RCC_PLLP_DIV_6                  (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2)                           /*!< Main PLL division factor for PLLP output by 6 */
00692 #define LL_RCC_PLLP_DIV_7                  (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2)                           /*!< Main PLL division factor for PLLP output by 7 */
00693 #define LL_RCC_PLLP_DIV_8                  (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2)        /*!< Main PLL division factor for PLLP output by 8 */
00694 #define LL_RCC_PLLP_DIV_9                  (RCC_PLLCFGR_PLLP_3)                                              /*!< Main PLL division factor for PLLP output by 9 */
00695 #define LL_RCC_PLLP_DIV_10                 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3)                           /*!< Main PLL division factor for PLLP output by 10 */
00696 #define LL_RCC_PLLP_DIV_11                 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3)                           /*!< Main PLL division factor for PLLP output by 11 */
00697 #define LL_RCC_PLLP_DIV_12                 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3)        /*!< Main PLL division factor for PLLP output by 12 */
00698 #define LL_RCC_PLLP_DIV_13                 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)                           /*!< Main PLL division factor for PLLP output by 13 */
00699 #define LL_RCC_PLLP_DIV_14                 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)        /*!< Main PLL division factor for PLLP output by 14 */
00700 #define LL_RCC_PLLP_DIV_15                 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)        /*!< Main PLL division factor for PLLP output by 15 */
00701 #define LL_RCC_PLLP_DIV_16                 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)/*!< Main PLL division factor for PLLP output by 16 */
00702 #define LL_RCC_PLLP_DIV_17                 (RCC_PLLCFGR_PLLP_4)                                              /*!< Main PLL division factor for PLLP output by 17 */
00703 #define LL_RCC_PLLP_DIV_18                 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_4)                           /*!< Main PLL division factor for PLLP output by 18 */
00704 #define LL_RCC_PLLP_DIV_19                 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4)                           /*!< Main PLL division factor for PLLP output by 19 */
00705 #define LL_RCC_PLLP_DIV_20                 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4)        /*!< Main PLL division factor for PLLP output by 20 */
00706 #define LL_RCC_PLLP_DIV_21                 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)                           /*!< Main PLL division factor for PLLP output by 21 */
00707 #define LL_RCC_PLLP_DIV_22                 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)        /*!< Main PLL division factor for PLLP output by 22 */
00708 #define LL_RCC_PLLP_DIV_23                 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)        /*!< Main PLL division factor for PLLP output by 23 */
00709 #define LL_RCC_PLLP_DIV_24                 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 24 */
00710 #define LL_RCC_PLLP_DIV_25                 (RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)                           /*!< Main PLL division factor for PLLP output by 25 */
00711 #define LL_RCC_PLLP_DIV_26                 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)        /*!< Main PLL division factor for PLLP output by 26 */
00712 #define LL_RCC_PLLP_DIV_27                 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)        /*!< Main PLL division factor for PLLP output by 27*/
00713 #define LL_RCC_PLLP_DIV_28                 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 28 */
00714 #define LL_RCC_PLLP_DIV_29                 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)        /*!< Main PLL division factor for PLLP output by 29 */
00715 #define LL_RCC_PLLP_DIV_30                 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 30 */
00716 #define LL_RCC_PLLP_DIV_31                 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 31 */
00717 #define LL_RCC_PLLP_DIV_32                 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 32 */
00718 /**
00719   * @}
00720   */
00721
00722 /** @defgroup RCC_LL_EC_PLLQ_DIV  PLL division factor (PLLQ)
00723   * @{
00724   */
00725 #define LL_RCC_PLLQ_DIV_2                  (RCC_PLLCFGR_PLLQ_0)                    /*!< Main PLL division factor for PLLQ output by 2 */
00726 #define LL_RCC_PLLQ_DIV_3                  (RCC_PLLCFGR_PLLQ_1)                    /*!< Main PLL division factor for PLLQ output by 3 */
00727 #define LL_RCC_PLLQ_DIV_4                  (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 4 */
00728 #define LL_RCC_PLLQ_DIV_5                  (RCC_PLLCFGR_PLLQ_2)                    /*!< Main PLL division factor for PLLQ output by 5 */
00729 #define LL_RCC_PLLQ_DIV_6                  (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 6 */
00730 #define LL_RCC_PLLQ_DIV_7                  (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 7 */
00731 #define LL_RCC_PLLQ_DIV_8                  (RCC_PLLCFGR_PLLQ)                      /*!< Main PLL division factor for PLLQ output by 8 */
00732 /**
00733   * @}
00734   */
00735
00736
00737 /** @defgroup RCC_LL_EC_PLLSAI1Q  PLLSAI1 division factor (PLLQ)
00738   * @{
00739   */
00740 #define LL_RCC_PLLSAI1Q_DIV_2              (RCC_PLLSAI1CFGR_PLLQ_0)                                /*!< PLLSAI1 division factor for PLLSAI1Q output by 2 */
00741 #define LL_RCC_PLLSAI1Q_DIV_3              (RCC_PLLSAI1CFGR_PLLQ_1)                                /*!< PLLSAI1 division factor for PLLSAI1Q output by 3 */
00742 #define LL_RCC_PLLSAI1Q_DIV_4              (RCC_PLLSAI1CFGR_PLLQ_1 | RCC_PLLSAI1CFGR_PLLQ_0)       /*!< PLLSAI1 division factor for PLLSAI1Q output by 4 */
00743 #define LL_RCC_PLLSAI1Q_DIV_5              (RCC_PLLSAI1CFGR_PLLQ_2)                                /*!< PLLSAI1 division factor for PLLSAI1Q output by 5 */
00744 #define LL_RCC_PLLSAI1Q_DIV_6              (RCC_PLLSAI1CFGR_PLLQ_2 | RCC_PLLSAI1CFGR_PLLQ_0)       /*!< PLLSAI1 division factor for PLLSAI1Q output by 6 */
00745 #define LL_RCC_PLLSAI1Q_DIV_7              (RCC_PLLSAI1CFGR_PLLQ_2 | RCC_PLLSAI1CFGR_PLLQ_1)       /*!< PLLSAI1 division factor for PLLSAI1Q output by 7 */
00746 #define LL_RCC_PLLSAI1Q_DIV_8              (RCC_PLLSAI1CFGR_PLLQ_2 | RCC_PLLSAI1CFGR_PLLQ_1 | RCC_PLLSAI1CFGR_PLLQ_0)   /*!< PLLSAI1 division factor for PLLSAI1Q output by 8 */
00747 /**
00748   * @}
00749   */
00750
00751 /** @defgroup RCC_LL_EC_PLLSAI1P  PLLSAI1 division factor (PLLP)
00752   * @{
00753   */
00754 #define LL_RCC_PLLSAI1P_DIV_2                  (RCC_PLLSAI1CFGR_PLLP_0)                                              /*!< Main PLL division factor for PLLP output by 2 */
00755 #define LL_RCC_PLLSAI1P_DIV_3                  (RCC_PLLSAI1CFGR_PLLP_1)                                              /*!< Main PLL division factor for PLLP output by 3 */
00756 #define LL_RCC_PLLSAI1P_DIV_4                  (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1)                       /*!< Main PLL division factor for PLLP output by 4 */
00757 #define LL_RCC_PLLSAI1P_DIV_5                  (RCC_PLLSAI1CFGR_PLLP_2)                                              /*!< Main PLL division factor for PLLP output by 5 */
00758 #define LL_RCC_PLLSAI1P_DIV_6                  (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2)                       /*!< Main PLL division factor for PLLP output by 6 */
00759 #define LL_RCC_PLLSAI1P_DIV_7                  (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2)                       /*!< Main PLL division factor for PLLP output by 7 */
00760 #define LL_RCC_PLLSAI1P_DIV_8                  (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2)/*!< Main PLL division factor for PLLP output by 8 */
00761 #define LL_RCC_PLLSAI1P_DIV_9                  (RCC_PLLSAI1CFGR_PLLP_3)                                              /*!< Main PLL division factor for PLLP output by 9 */
00762 #define LL_RCC_PLLSAI1P_DIV_10                 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_3)                       /*!< Main PLL division factor for PLLP output by 10 */
00763 #define LL_RCC_PLLSAI1P_DIV_11                 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3)                       /*!< Main PLL division factor for PLLP output by 11 */
00764 #define LL_RCC_PLLSAI1P_DIV_12                 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3)/*!< Main PLL division factor for PLLP output by 12 */
00765 #define LL_RCC_PLLSAI1P_DIV_13                 (RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3)                       /*!< Main PLL division factor for PLLP output by 13 */
00766 #define LL_RCC_PLLSAI1P_DIV_14                 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3)/*!< Main PLL division factor for PLLP output by 14 */
00767 #define LL_RCC_PLLSAI1P_DIV_15                 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3)/*!< Main PLL division factor for PLLP output by 15 */
00768 #define LL_RCC_PLLSAI1P_DIV_16                 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3)/*!< Main PLL division factor for PLLP output by 16 */
00769 #define LL_RCC_PLLSAI1P_DIV_17                 (RCC_PLLSAI1CFGR_PLLP_4)                                              /*!< Main PLL division factor for PLLP output by 17 */
00770 #define LL_RCC_PLLSAI1P_DIV_18                 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_4)                       /*!< Main PLL division factor for PLLP output by 18 */
00771 #define LL_RCC_PLLSAI1P_DIV_19                 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_4)                       /*!< Main PLL division factor for PLLP output by 19 */
00772 #define LL_RCC_PLLSAI1P_DIV_20                 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 20 */
00773 #define LL_RCC_PLLSAI1P_DIV_21                 (RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4)                       /*!< Main PLL division factor for PLLP output by 21 */
00774 #define LL_RCC_PLLSAI1P_DIV_22                 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 22 */
00775 #define LL_RCC_PLLSAI1P_DIV_23                 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 23 */
00776 #define LL_RCC_PLLSAI1P_DIV_24                 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 24 */
00777 #define LL_RCC_PLLSAI1P_DIV_25                 (RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)                       /*!< Main PLL division factor for PLLP output by 25 */
00778 #define LL_RCC_PLLSAI1P_DIV_26                 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 26 */
00779 #define LL_RCC_PLLSAI1P_DIV_27                 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 27*/
00780 #define LL_RCC_PLLSAI1P_DIV_28                 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 28 */
00781 #define LL_RCC_PLLSAI1P_DIV_29                 (RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 29 */
00782 #define LL_RCC_PLLSAI1P_DIV_30                 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 30 */
00783 #define LL_RCC_PLLSAI1P_DIV_31                 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 31 */
00784 #define LL_RCC_PLLSAI1P_DIV_32                 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 32 */
00785 /**
00786   * @}
00787   */
00788
00789 /** @defgroup RCC_LL_EC_PLLSAI1R  PLLSAI1 division factor (PLLR)
00790   * @{
00791   */
00792 #define LL_RCC_PLLSAI1R_DIV_2              (RCC_PLLSAI1CFGR_PLLR_0)                                /*!< PLLSAI1 division factor for PLLSAI1R output by 2 */
00793 #define LL_RCC_PLLSAI1R_DIV_3              (RCC_PLLSAI1CFGR_PLLR_1)                                /*!< PLLSAI1 division factor for PLLSAI1R output by 3 */
00794 #define LL_RCC_PLLSAI1R_DIV_4              (RCC_PLLSAI1CFGR_PLLR_1 | RCC_PLLSAI1CFGR_PLLR_0)       /*!< PLLSAI1 division factor for PLLSAI1R output by 4 */
00795 #define LL_RCC_PLLSAI1R_DIV_5              (RCC_PLLSAI1CFGR_PLLR_2)                                /*!< PLLSAI1 division factor for PLLSAI1R output by 5 */
00796 #define LL_RCC_PLLSAI1R_DIV_6              (RCC_PLLSAI1CFGR_PLLR_2 | RCC_PLLSAI1CFGR_PLLR_0)       /*!< PLLSAI1 division factor for PLLSAI1R output by 6 */
00797 #define LL_RCC_PLLSAI1R_DIV_7              (RCC_PLLSAI1CFGR_PLLR_2 | RCC_PLLSAI1CFGR_PLLR_1)       /*!< PLLSAI1 division factor for PLLSAI1R output by 7 */
00798 #define LL_RCC_PLLSAI1R_DIV_8              (RCC_PLLSAI1CFGR_PLLR_2 | RCC_PLLSAI1CFGR_PLLR_1 | RCC_PLLSAI1CFGR_PLLR_0)   /*!< PLLSAI1 division factor for PLLSAI1R output by 8 */
00799 /**
00800   * @}
00801   */
00802
00803 /**
00804   * @}
00805   */
00806
00807 /* Exported macro ------------------------------------------------------------*/
00808 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
00809   * @{
00810   */
00811
00812 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
00813   * @{
00814   */
00815
00816 /**
00817   * @brief  Write a value in RCC register
00818   * @param  __REG__ Register to be written
00819   * @param  __VALUE__ Value to be written in the register
00820   * @retval None
00821   */
00822 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
00823
00824 /**
00825   * @brief  Read a value in RCC register
00826   * @param  __REG__ Register to be read
00827   * @retval Register value
00828   */
00829 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
00830 /**
00831   * @}
00832   */
00833
00834 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
00835   * @{
00836   */
00837
00838 /**
00839   * @brief  Helper macro to calculate the PLLRCLK frequency on system domain
00840   * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
00841   *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
00842   * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
00843   * @param  __PLLM__ This parameter can be one of the following values:
00844   *         @arg @ref LL_RCC_PLLM_DIV_1
00845   *         @arg @ref LL_RCC_PLLM_DIV_2
00846   *         @arg @ref LL_RCC_PLLM_DIV_3
00847   *         @arg @ref LL_RCC_PLLM_DIV_4
00848   *         @arg @ref LL_RCC_PLLM_DIV_5
00849   *         @arg @ref LL_RCC_PLLM_DIV_6
00850   *         @arg @ref LL_RCC_PLLM_DIV_7
00851   *         @arg @ref LL_RCC_PLLM_DIV_8
00852   * @param  __PLLN__ Between Min_Data = 6 and Max_Data = 127
00853   * @param  __PLLR__ This parameter can be one of the following values:
00854   *         @arg @ref LL_RCC_PLLR_DIV_2
00855   *         @arg @ref LL_RCC_PLLR_DIV_3
00856   *         @arg @ref LL_RCC_PLLR_DIV_4
00857   *         @arg @ref LL_RCC_PLLR_DIV_5
00858   *         @arg @ref LL_RCC_PLLR_DIV_6
00859   *         @arg @ref LL_RCC_PLLR_DIV_7
00860   *         @arg @ref LL_RCC_PLLR_DIV_8
00861   * @retval PLL clock frequency (in Hz)
00862   */
00863 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) * (__PLLN__)  / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
00864                    (((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U))
00865
00866 #if defined(SAI1)
00867 /**
00868   * @brief  Helper macro to calculate the PLLPCLK frequency used on SAI domain
00869   * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
00870   *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
00871   * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
00872   * @param  __PLLM__ This parameter can be one of the following values:
00873   *         @arg @ref LL_RCC_PLLM_DIV_1
00874   *         @arg @ref LL_RCC_PLLM_DIV_2
00875   *         @arg @ref LL_RCC_PLLM_DIV_3
00876   *         @arg @ref LL_RCC_PLLM_DIV_4
00877   *         @arg @ref LL_RCC_PLLM_DIV_5
00878   *         @arg @ref LL_RCC_PLLM_DIV_6
00879   *         @arg @ref LL_RCC_PLLM_DIV_7
00880   *         @arg @ref LL_RCC_PLLM_DIV_8
00881   * @param  __PLLN__ Between Min_Data = 6 and Max_Data = 127
00882   * @param  __PLLP__ This parameter can be one of the following values:
00883   *         @arg @ref LL_RCC_PLLP_DIV_2
00884   *         @arg @ref LL_RCC_PLLP_DIV_3
00885   *         @arg @ref LL_RCC_PLLP_DIV_4
00886   *         @arg @ref LL_RCC_PLLP_DIV_5
00887   *         @arg @ref LL_RCC_PLLP_DIV_6
00888   *         @arg @ref LL_RCC_PLLP_DIV_7
00889   *         @arg @ref LL_RCC_PLLP_DIV_8
00890   *         @arg @ref LL_RCC_PLLP_DIV_9
00891   *         @arg @ref LL_RCC_PLLP_DIV_10
00892   *         @arg @ref LL_RCC_PLLP_DIV_11
00893   *         @arg @ref LL_RCC_PLLP_DIV_12
00894   *         @arg @ref LL_RCC_PLLP_DIV_13
00895   *         @arg @ref LL_RCC_PLLP_DIV_14
00896   *         @arg @ref LL_RCC_PLLP_DIV_15
00897   *         @arg @ref LL_RCC_PLLP_DIV_16
00898   *         @arg @ref LL_RCC_PLLP_DIV_17
00899   *         @arg @ref LL_RCC_PLLP_DIV_18
00900   *         @arg @ref LL_RCC_PLLP_DIV_19
00901   *         @arg @ref LL_RCC_PLLP_DIV_20
00902   *         @arg @ref LL_RCC_PLLP_DIV_21
00903   *         @arg @ref LL_RCC_PLLP_DIV_22
00904   *         @arg @ref LL_RCC_PLLP_DIV_23
00905   *         @arg @ref LL_RCC_PLLP_DIV_24
00906   *         @arg @ref LL_RCC_PLLP_DIV_25
00907   *         @arg @ref LL_RCC_PLLP_DIV_26
00908   *         @arg @ref LL_RCC_PLLP_DIV_27
00909   *         @arg @ref LL_RCC_PLLP_DIV_28
00910   *         @arg @ref LL_RCC_PLLP_DIV_29
00911   *         @arg @ref LL_RCC_PLLP_DIV_30
00912   *         @arg @ref LL_RCC_PLLP_DIV_31
00913   * @retval PLL clock frequency (in Hz)
00914   */
00915 #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) * (__PLLN__)  / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U))/ \
00916                    (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U))
00917 #endif
00918
00919 /**
00920   * @brief  Helper macro to calculate the PLLPCLK frequency used on ADC domain
00921   * @note ex: @ref __LL_RCC_CALC_PLLCLK_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
00922   *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
00923   * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
00924   * @param  __PLLM__ This parameter can be one of the following values:
00925   *         @arg @ref LL_RCC_PLLM_DIV_1
00926   *         @arg @ref LL_RCC_PLLM_DIV_2
00927   *         @arg @ref LL_RCC_PLLM_DIV_3
00928   *         @arg @ref LL_RCC_PLLM_DIV_4
00929   *         @arg @ref LL_RCC_PLLM_DIV_5
00930   *         @arg @ref LL_RCC_PLLM_DIV_6
00931   *         @arg @ref LL_RCC_PLLM_DIV_7
00932   *         @arg @ref LL_RCC_PLLM_DIV_8
00933   * @param  __PLLN__ Between Min_Data = 6 and Max_Data = 127
00934   * @param  __PLLP__ This parameter can be one of the following values:
00935   *         @arg @ref LL_RCC_PLLP_DIV_2
00936   *         @arg @ref LL_RCC_PLLP_DIV_3
00937   *         @arg @ref LL_RCC_PLLP_DIV_4
00938   *         @arg @ref LL_RCC_PLLP_DIV_5
00939   *         @arg @ref LL_RCC_PLLP_DIV_6
00940   *         @arg @ref LL_RCC_PLLP_DIV_7
00941   *         @arg @ref LL_RCC_PLLP_DIV_8
00942   *         @arg @ref LL_RCC_PLLP_DIV_9
00943   *         @arg @ref LL_RCC_PLLP_DIV_10
00944   *         @arg @ref LL_RCC_PLLP_DIV_11
00945   *         @arg @ref LL_RCC_PLLP_DIV_12
00946   *         @arg @ref LL_RCC_PLLP_DIV_13
00947   *         @arg @ref LL_RCC_PLLP_DIV_14
00948   *         @arg @ref LL_RCC_PLLP_DIV_15
00949   *         @arg @ref LL_RCC_PLLP_DIV_16
00950   *         @arg @ref LL_RCC_PLLP_DIV_17
00951   *         @arg @ref LL_RCC_PLLP_DIV_18
00952   *         @arg @ref LL_RCC_PLLP_DIV_19
00953   *         @arg @ref LL_RCC_PLLP_DIV_20
00954   *         @arg @ref LL_RCC_PLLP_DIV_21
00955   *         @arg @ref LL_RCC_PLLP_DIV_22
00956   *         @arg @ref LL_RCC_PLLP_DIV_23
00957   *         @arg @ref LL_RCC_PLLP_DIV_24
00958   *         @arg @ref LL_RCC_PLLP_DIV_25
00959   *         @arg @ref LL_RCC_PLLP_DIV_26
00960   *         @arg @ref LL_RCC_PLLP_DIV_27
00961   *         @arg @ref LL_RCC_PLLP_DIV_28
00962   *         @arg @ref LL_RCC_PLLP_DIV_29
00963   *         @arg @ref LL_RCC_PLLP_DIV_30
00964   *         @arg @ref LL_RCC_PLLP_DIV_31
00965   *         @arg @ref LL_RCC_PLLP_DIV_32
00966   * @retval PLL clock frequency (in Hz)
00967   */
00968 #define __LL_RCC_CALC_PLLCLK_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
00969                    (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U))
00970
00971 /**
00972   * @brief  Helper macro to calculate the PLLQCLK frequency used on 48M domain
00973   * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
00974   *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
00975   * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
00976   * @param  __PLLM__ This parameter can be one of the following values:
00977   *         @arg @ref LL_RCC_PLLM_DIV_1
00978   *         @arg @ref LL_RCC_PLLM_DIV_2
00979   *         @arg @ref LL_RCC_PLLM_DIV_3
00980   *         @arg @ref LL_RCC_PLLM_DIV_4
00981   *         @arg @ref LL_RCC_PLLM_DIV_5
00982   *         @arg @ref LL_RCC_PLLM_DIV_6
00983   *         @arg @ref LL_RCC_PLLM_DIV_7
00984   *         @arg @ref LL_RCC_PLLM_DIV_8
00985   * @param  __PLLN__ Between Min_Data = 6 and Max_Data = 127
00986   * @param  __PLLQ__ This parameter can be one of the following values:
00987   *         @arg @ref LL_RCC_PLLQ_DIV_2
00988   *         @arg @ref LL_RCC_PLLQ_DIV_3
00989   *         @arg @ref LL_RCC_PLLQ_DIV_4
00990   *         @arg @ref LL_RCC_PLLQ_DIV_5
00991   *         @arg @ref LL_RCC_PLLQ_DIV_6
00992   *         @arg @ref LL_RCC_PLLQ_DIV_7
00993   *         @arg @ref LL_RCC_PLLQ_DIV_8
00994   * @retval PLL clock frequency (in Hz)
00995   */
00996 #define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
00997                    (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U))
00998
00999 #if defined(SAI1)
01000 /**
01001   * @brief  Helper macro to calculate the PLLSAI1PCLK frequency used for SAI domain
01002   * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
01003   *             @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ());
01004   * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
01005   * @param  __PLLM__ This parameter can be one of the following values:
01006   *         @arg @ref LL_RCC_PLLM_DIV_1
01007   *         @arg @ref LL_RCC_PLLM_DIV_2
01008   *         @arg @ref LL_RCC_PLLM_DIV_3
01009   *         @arg @ref LL_RCC_PLLM_DIV_4
01010   *         @arg @ref LL_RCC_PLLM_DIV_5
01011   *         @arg @ref LL_RCC_PLLM_DIV_6
01012   *         @arg @ref LL_RCC_PLLM_DIV_7
01013   *         @arg @ref LL_RCC_PLLM_DIV_8
01014   * @param  __PLLSAI1N__ Between 6 and 127
01015   * @param  __PLLSAI1P__ This parameter can be one of the following values:
01016   *         @arg @ref LL_RCC_PLLSAI1P_DIV_2
01017   *         @arg @ref LL_RCC_PLLSAI1P_DIV_3
01018   *         @arg @ref LL_RCC_PLLSAI1P_DIV_4
01019   *         @arg @ref LL_RCC_PLLSAI1P_DIV_5
01020   *         @arg @ref LL_RCC_PLLSAI1P_DIV_6
01021   *         @arg @ref LL_RCC_PLLSAI1P_DIV_7
01022   *         @arg @ref LL_RCC_PLLSAI1P_DIV_8
01023   *         @arg @ref LL_RCC_PLLSAI1P_DIV_9
01024   *         @arg @ref LL_RCC_PLLSAI1P_DIV_10
01025   *         @arg @ref LL_RCC_PLLSAI1P_DIV_11
01026   *         @arg @ref LL_RCC_PLLSAI1P_DIV_12
01027   *         @arg @ref LL_RCC_PLLSAI1P_DIV_13
01028   *         @arg @ref LL_RCC_PLLSAI1P_DIV_14
01029   *         @arg @ref LL_RCC_PLLSAI1P_DIV_15
01030   *         @arg @ref LL_RCC_PLLSAI1P_DIV_16
01031   *         @arg @ref LL_RCC_PLLSAI1P_DIV_17
01032   *         @arg @ref LL_RCC_PLLSAI1P_DIV_18
01033   *         @arg @ref LL_RCC_PLLSAI1P_DIV_19
01034   *         @arg @ref LL_RCC_PLLSAI1P_DIV_20
01035   *         @arg @ref LL_RCC_PLLSAI1P_DIV_21
01036   *         @arg @ref LL_RCC_PLLSAI1P_DIV_22
01037   *         @arg @ref LL_RCC_PLLSAI1P_DIV_23
01038   *         @arg @ref LL_RCC_PLLSAI1P_DIV_24
01039   *         @arg @ref LL_RCC_PLLSAI1P_DIV_25
01040   *         @arg @ref LL_RCC_PLLSAI1P_DIV_26
01041   *         @arg @ref LL_RCC_PLLSAI1P_DIV_27
01042   *         @arg @ref LL_RCC_PLLSAI1P_DIV_28
01043   *         @arg @ref LL_RCC_PLLSAI1P_DIV_29
01044   *         @arg @ref LL_RCC_PLLSAI1P_DIV_30
01045   *         @arg @ref LL_RCC_PLLSAI1P_DIV_31
01046   *         @arg @ref LL_RCC_PLLSAI1P_DIV_32
01047   * @retval PLLSAI1 clock frequency (in Hz)
01048   */
01049 #define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) \
01050                    ((__INPUTFREQ__) * (__PLLSAI1N__)  / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
01051                     (((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLP_Pos) + 1U))
01052
01053 /**
01054   * @brief  Helper macro to calculate the PLLSAI1QCLK frequency used on 48M domain
01055   * @note ex: @ref __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
01056   *             @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetQ ());
01057   * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
01058   * @param  __PLLM__ This parameter can be one of the following values:
01059   *         @arg @ref LL_RCC_PLLM_DIV_1
01060   *         @arg @ref LL_RCC_PLLM_DIV_2
01061   *         @arg @ref LL_RCC_PLLM_DIV_3
01062   *         @arg @ref LL_RCC_PLLM_DIV_4
01063   *         @arg @ref LL_RCC_PLLM_DIV_5
01064   *         @arg @ref LL_RCC_PLLM_DIV_6
01065   *         @arg @ref LL_RCC_PLLM_DIV_7
01066   *         @arg @ref LL_RCC_PLLM_DIV_8
01067   * @param  __PLLSAI1N__ Between 6 and 127
01068   * @param  __PLLSAI1Q__ This parameter can be one of the following values:
01069   *         @arg @ref LL_RCC_PLLSAI1Q_DIV_2
01070   *         @arg @ref LL_RCC_PLLSAI1Q_DIV_3
01071   *         @arg @ref LL_RCC_PLLSAI1Q_DIV_4
01072   *         @arg @ref LL_RCC_PLLSAI1Q_DIV_5
01073   *         @arg @ref LL_RCC_PLLSAI1Q_DIV_6
01074   *         @arg @ref LL_RCC_PLLSAI1Q_DIV_7
01075   *         @arg @ref LL_RCC_PLLSAI1Q_DIV_8
01076   * @retval PLLSAI1 clock frequency (in Hz)
01077   */
01078 #define __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1Q__) \
01079                    ((__INPUTFREQ__) * (__PLLSAI1N__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
01080                     (((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLQ_Pos) + 1U))
01081
01082 /**
01083   * @brief  Helper macro to calculate the PLLSAI1RCLK frequency used on ADC domain
01084   * @note ex: @ref __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
01085   *             @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetR ());
01086   * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
01087   * @param  __PLLM__ This parameter can be one of the following values:
01088   *         @arg @ref LL_RCC_PLLM_DIV_1
01089   *         @arg @ref LL_RCC_PLLM_DIV_2
01090   *         @arg @ref LL_RCC_PLLM_DIV_3
01091   *         @arg @ref LL_RCC_PLLM_DIV_4
01092   *         @arg @ref LL_RCC_PLLM_DIV_5
01093   *         @arg @ref LL_RCC_PLLM_DIV_6
01094   *         @arg @ref LL_RCC_PLLM_DIV_7
01095   *         @arg @ref LL_RCC_PLLM_DIV_8
01096   * @param  __PLLSAI1N__ Between 6 and 127
01097   * @param  __PLLSAI1R__ This parameter can be one of the following values:
01098   *         @arg @ref LL_RCC_PLLSAI1R_DIV_2
01099   *         @arg @ref LL_RCC_PLLSAI1R_DIV_3
01100   *         @arg @ref LL_RCC_PLLSAI1R_DIV_4
01101   *         @arg @ref LL_RCC_PLLSAI1R_DIV_5
01102   *         @arg @ref LL_RCC_PLLSAI1R_DIV_6
01103   *         @arg @ref LL_RCC_PLLSAI1R_DIV_7
01104   *         @arg @ref LL_RCC_PLLSAI1R_DIV_8
01105   * @retval PLLSAI1 clock frequency (in Hz)
01106   */
01107 #define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1R__) \
01108                    ((__INPUTFREQ__) * (__PLLSAI1N__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
01109                     (((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLR_Pos) + 1U))
01110 #endif
01111
01112 /**
01113   * @brief  Helper macro to calculate the HCLK1 frequency
01114   * @param  __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
01115   * @param  __CPU1PRESCALER__ This parameter can be one of the following values:
01116   *         @arg @ref LL_RCC_SYSCLK_DIV_1
01117   *         @arg @ref LL_RCC_SYSCLK_DIV_2
01118   *         @arg @ref LL_RCC_SYSCLK_DIV_3
01119   *         @arg @ref LL_RCC_SYSCLK_DIV_4
01120   *         @arg @ref LL_RCC_SYSCLK_DIV_5
01121   *         @arg @ref LL_RCC_SYSCLK_DIV_6
01122   *         @arg @ref LL_RCC_SYSCLK_DIV_8
01123   *         @arg @ref LL_RCC_SYSCLK_DIV_10
01124   *         @arg @ref LL_RCC_SYSCLK_DIV_16
01125   *         @arg @ref LL_RCC_SYSCLK_DIV_32
01126   *         @arg @ref LL_RCC_SYSCLK_DIV_64
01127   *         @arg @ref LL_RCC_SYSCLK_DIV_128
01128   *         @arg @ref LL_RCC_SYSCLK_DIV_256
01129   *         @arg @ref LL_RCC_SYSCLK_DIV_512
01130   * @retval HCLK1 clock frequency (in Hz)
01131   */
01132 #define __LL_RCC_CALC_HCLK1_FREQ(__SYSCLKFREQ__,__CPU1PRESCALER__) ((__SYSCLKFREQ__) / AHBPrescTable[((__CPU1PRESCALER__) & RCC_CFGR_HPRE) >>  RCC_CFGR_HPRE_Pos])
01133
01134 /**
01135   * @brief  Helper macro to calculate the HCLK2 frequency
01136   * @param  __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
01137   * @param  __CPU2PRESCALER__ This parameter can be one of the following values:
01138   *         @arg @ref LL_RCC_SYSCLK_DIV_1
01139   *         @arg @ref LL_RCC_SYSCLK_DIV_2
01140   *         @arg @ref LL_RCC_SYSCLK_DIV_3
01141   *         @arg @ref LL_RCC_SYSCLK_DIV_4
01142   *         @arg @ref LL_RCC_SYSCLK_DIV_5
01143   *         @arg @ref LL_RCC_SYSCLK_DIV_6
01144   *         @arg @ref LL_RCC_SYSCLK_DIV_8
01145   *         @arg @ref LL_RCC_SYSCLK_DIV_10
01146   *         @arg @ref LL_RCC_SYSCLK_DIV_16
01147   *         @arg @ref LL_RCC_SYSCLK_DIV_32
01148   *         @arg @ref LL_RCC_SYSCLK_DIV_64
01149   *         @arg @ref LL_RCC_SYSCLK_DIV_128
01150   *         @arg @ref LL_RCC_SYSCLK_DIV_256
01151   *         @arg @ref LL_RCC_SYSCLK_DIV_512
01152   * @retval HCLK2 clock frequency (in Hz)
01153   */
01154 #define __LL_RCC_CALC_HCLK2_FREQ(__SYSCLKFREQ__, __CPU2PRESCALER__) ((__SYSCLKFREQ__) / AHBPrescTable[((__CPU2PRESCALER__) & RCC_EXTCFGR_C2HPRE) >>  RCC_EXTCFGR_C2HPRE_Pos])
01155
01156 /**
01157   * @brief  Helper macro to calculate the HCLK4 frequency
01158   * @param  __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
01159   * @param  __AHB4PRESCALER__ This parameter can be one of the following values:
01160   *         @arg @ref LL_RCC_SYSCLK_DIV_1
01161   *         @arg @ref LL_RCC_SYSCLK_DIV_2
01162   *         @arg @ref LL_RCC_SYSCLK_DIV_3
01163   *         @arg @ref LL_RCC_SYSCLK_DIV_4
01164   *         @arg @ref LL_RCC_SYSCLK_DIV_5
01165   *         @arg @ref LL_RCC_SYSCLK_DIV_6
01166   *         @arg @ref LL_RCC_SYSCLK_DIV_8
01167   *         @arg @ref LL_RCC_SYSCLK_DIV_10
01168   *         @arg @ref LL_RCC_SYSCLK_DIV_16
01169   *         @arg @ref LL_RCC_SYSCLK_DIV_32
01170   *         @arg @ref LL_RCC_SYSCLK_DIV_64
01171   *         @arg @ref LL_RCC_SYSCLK_DIV_128
01172   *         @arg @ref LL_RCC_SYSCLK_DIV_256
01173   *         @arg @ref LL_RCC_SYSCLK_DIV_512
01174   * @retval HCLK4 clock frequency (in Hz)
01175   */
01176 #define __LL_RCC_CALC_HCLK4_FREQ(__SYSCLKFREQ__, __AHB4PRESCALER__) ((__SYSCLKFREQ__) / AHBPrescTable[(((__AHB4PRESCALER__) >> 4U) & RCC_EXTCFGR_SHDHPRE) >>  RCC_EXTCFGR_SHDHPRE_Pos])
01177
01178
01179 /**
01180   * @brief  Helper macro to calculate the PCLK1 frequency (ABP1)
01181   * @param  __HCLKFREQ__ HCLK frequency
01182   * @param  __APB1PRESCALER__ This parameter can be one of the following values:
01183   *         @arg @ref LL_RCC_APB1_DIV_1
01184   *         @arg @ref LL_RCC_APB1_DIV_2
01185   *         @arg @ref LL_RCC_APB1_DIV_4
01186   *         @arg @ref LL_RCC_APB1_DIV_8
01187   *         @arg @ref LL_RCC_APB1_DIV_16
01188   * @retval PCLK1 clock frequency (in Hz)
01189   */
01190 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> (APBPrescTable[(((__APB1PRESCALER__) & RCC_CFGR_PPRE1_Msk) >>  RCC_CFGR_PPRE1_Pos)] & 31U))
01191
01192 /**
01193   * @brief  Helper macro to calculate the PCLK2 frequency (ABP2)
01194   * @param  __HCLKFREQ__ HCLK frequency
01195   * @param  __APB2PRESCALER__ This parameter can be one of the following values:
01196   *         @arg @ref LL_RCC_APB2_DIV_1
01197   *         @arg @ref LL_RCC_APB2_DIV_2
01198   *         @arg @ref LL_RCC_APB2_DIV_4
01199   *         @arg @ref LL_RCC_APB2_DIV_8
01200   *         @arg @ref LL_RCC_APB2_DIV_16
01201   * @retval PCLK2 clock frequency (in Hz)
01202   */
01203 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> (APBPrescTable[(((__APB2PRESCALER__) & RCC_CFGR_PPRE2_Msk) >>  RCC_CFGR_PPRE2_Pos)] & 31U))
01204
01205 /**
01206   * @brief  Helper macro to calculate the MSI frequency (in Hz)
01207   * @note __MSIRANGE__can be retrieved by @ref LL_RCC_MSI_GetRange()
01208   * @param  __MSIRANGE__ This parameter can be one of the following values:
01209   *         @arg @ref LL_RCC_MSIRANGE_0
01210   *         @arg @ref LL_RCC_MSIRANGE_1
01211   *         @arg @ref LL_RCC_MSIRANGE_2
01212   *         @arg @ref LL_RCC_MSIRANGE_3
01213   *         @arg @ref LL_RCC_MSIRANGE_4
01214   *         @arg @ref LL_RCC_MSIRANGE_5
01215   *         @arg @ref LL_RCC_MSIRANGE_6
01216   *         @arg @ref LL_RCC_MSIRANGE_7
01217   *         @arg @ref LL_RCC_MSIRANGE_8
01218   *         @arg @ref LL_RCC_MSIRANGE_9
01219   *         @arg @ref LL_RCC_MSIRANGE_10
01220   *         @arg @ref LL_RCC_MSIRANGE_11
01221   * @retval MSI clock frequency (in Hz)
01222   */
01223 #define __LL_RCC_CALC_MSI_FREQ(__MSIRANGE__) MSIRangeTable[((__MSIRANGE__) & RCC_CR_MSIRANGE_Msk) >> RCC_CR_MSIRANGE_Pos]
01224 /**
01225   * @}
01226   */
01227
01228 /**
01229   * @}
01230   */
01231
01232 /* Exported functions --------------------------------------------------------*/
01233 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
01234   * @{
01235   */
01236
01237 /** @defgroup RCC_LL_EF_HSE HSE
01238   * @{
01239   */
01240
01241 /**
01242   * @brief  Enable HSE sysclk and pll prescaler division by 2
01243   * @rmtoll CR           HSEPRE        LL_RCC_HSE_EnableDiv2
01244   * @retval None
01245   */
01246 __STATIC_INLINE void LL_RCC_HSE_EnableDiv2(void)
01247 {
01248   SET_BIT(RCC->CR, RCC_CR_HSEPRE);
01249 }
01250
01251 /**
01252   * @brief  Disable HSE sysclk and pll prescaler
01253   * @rmtoll CR           HSEPRE        LL_RCC_HSE_DisableDiv2
01254   * @retval None
01255   */
01256 __STATIC_INLINE void LL_RCC_HSE_DisableDiv2(void)
01257 {
01258   CLEAR_BIT(RCC->CR, RCC_CR_HSEPRE);
01259 }
01260
01261 /**
01262   * @brief  Get HSE sysclk and pll prescaler
01263   * @rmtoll CR           HSEPRE        LL_RCC_HSE_IsEnabledDiv2
01264   * @retval None
01265   */
01266 __STATIC_INLINE uint32_t LL_RCC_HSE_IsEnabledDiv2(void)
01267 {
01268   return ((READ_BIT(RCC->CR, RCC_CR_HSEPRE) == (RCC_CR_HSEPRE)) ? 1UL : 0UL);
01269 }
01270
01271 /**
01272   * @brief  Enable the Clock Security System.
01273   * @rmtoll CR           CSSON         LL_RCC_HSE_EnableCSS
01274   * @retval None
01275   */
01276 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
01277 {
01278   SET_BIT(RCC->CR, RCC_CR_CSSON);
01279 }
01280
01281 /**
01282   * @brief  Enable HSE external oscillator (HSE Bypass)
01283   * @rmtoll CR           HSEBYP        LL_RCC_HSE_EnableBypass
01284   * @retval None
01285   */
01286 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
01287 {
01288   SET_BIT(RCC->CR, RCC_CR_HSEBYP);
01289 }
01290
01291 /**
01292   * @brief  Disable HSE external oscillator (HSE Bypass)
01293   * @rmtoll CR           HSEBYP        LL_RCC_HSE_DisableBypass
01294   * @retval None
01295   */
01296 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
01297 {
01298   CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
01299 }
01300
01301 /**
01302   * @brief  Enable HSE crystal oscillator (HSE ON)
01303   * @rmtoll CR           HSEON         LL_RCC_HSE_Enable
01304   * @retval None
01305   */
01306 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
01307 {
01308   SET_BIT(RCC->CR, RCC_CR_HSEON);
01309 }
01310
01311 /**
01312   * @brief  Disable HSE crystal oscillator (HSE ON)
01313   * @rmtoll CR           HSEON         LL_RCC_HSE_Disable
01314   * @retval None
01315   */
01316 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
01317 {
01318   CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
01319 }
01320
01321 /**
01322   * @brief  Check if HSE oscillator Ready
01323   * @rmtoll CR           HSERDY        LL_RCC_HSE_IsReady
01324   * @retval State of bit (1 or 0).
01325   */
01326 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
01327 {
01328   return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL);
01329 }
01330
01331 /**
01332   * @brief  Check if HSE clock control register is locked or not
01333   * @rmtoll HSECR           UNLOCKED        LL_RCC_HSE_IsClockControlLocked
01334   * @retval State of bit (1 or 0).
01335   */
01336 __STATIC_INLINE uint32_t LL_RCC_HSE_IsClockControlLocked(void)
01337 {
01338   return ((READ_BIT(RCC->HSECR, RCC_HSECR_UNLOCKED) != (RCC_HSECR_UNLOCKED)) ? 1UL : 0UL);
01339 }
01340
01341 /**
01342   * @brief  Set HSE capacitor tuning
01343   * @rmtoll HSECR        HSETUNE       LL_RCC_HSE_SetCapacitorTuning
01344   * @param  Value Between Min_Data = 0 and Max_Data = 63
01345   * @retval None
01346   */
01347 __STATIC_INLINE void LL_RCC_HSE_SetCapacitorTuning(uint32_t Value)
01348 {
01349   WRITE_REG(RCC->HSECR, HSE_CONTROL_UNLOCK_KEY);
01350   MODIFY_REG(RCC->HSECR, RCC_HSECR_HSETUNE, Value << RCC_HSECR_HSETUNE_Pos);
01351 }
01352
01353 /**
01354   * @brief  Get HSE capacitor tuning
01355   * @rmtoll HSECR        HSETUNE       LL_RCC_HSE_GetCapacitorTuning
01356   * @retval Between Min_Data = 0 and Max_Data = 63
01357   */
01358 __STATIC_INLINE uint32_t LL_RCC_HSE_GetCapacitorTuning(void)
01359 {
01360   return (uint32_t)(READ_BIT(RCC->HSECR, RCC_HSECR_HSETUNE) >> RCC_HSECR_HSETUNE_Pos);
01361 }
01362
01363 /**
01364   * @brief  Set HSE current control
01365   * @rmtoll HSECR        HSEGMC       LL_RCC_HSE_SetCurrentControl
01366   * @param  CurrentMax This parameter can be one of the following values:
01367   *         @arg @ref LL_RCC_HSE_CURRENTMAX_0
01368   *         @arg @ref LL_RCC_HSE_CURRENTMAX_1
01369   *         @arg @ref LL_RCC_HSE_CURRENTMAX_2
01370   *         @arg @ref LL_RCC_HSE_CURRENTMAX_3
01371   *         @arg @ref LL_RCC_HSE_CURRENTMAX_4
01372   *         @arg @ref LL_RCC_HSE_CURRENTMAX_5
01373   *         @arg @ref LL_RCC_HSE_CURRENTMAX_6
01374   *         @arg @ref LL_RCC_HSE_CURRENTMAX_7
01375   */
01376 __STATIC_INLINE void LL_RCC_HSE_SetCurrentControl(uint32_t CurrentMax)
01377 {
01378   WRITE_REG(RCC->HSECR, HSE_CONTROL_UNLOCK_KEY);
01379   MODIFY_REG(RCC->HSECR, RCC_HSECR_HSEGMC, CurrentMax);
01380 }
01381
01382 /**
01383   * @brief  Get HSE current control
01384   * @rmtoll HSECR        HSEGMC       LL_RCC_HSE_GetCurrentControl
01385   * @retval Returned value can be one of the following values:
01386   *         @arg @ref LL_RCC_HSE_CURRENTMAX_0
01387   *         @arg @ref LL_RCC_HSE_CURRENTMAX_1
01388   *         @arg @ref LL_RCC_HSE_CURRENTMAX_2
01389   *         @arg @ref LL_RCC_HSE_CURRENTMAX_3
01390   *         @arg @ref LL_RCC_HSE_CURRENTMAX_4
01391   *         @arg @ref LL_RCC_HSE_CURRENTMAX_5
01392   *         @arg @ref LL_RCC_HSE_CURRENTMAX_6
01393   *         @arg @ref LL_RCC_HSE_CURRENTMAX_7
01394   */
01395 __STATIC_INLINE uint32_t LL_RCC_HSE_GetCurrentControl(void)
01396 {
01397   return (uint32_t)(READ_BIT(RCC->HSECR, RCC_HSECR_HSEGMC));
01398 }
01399
01400 /**
01401   * @brief  Set HSE sense amplifier threshold
01402   * @rmtoll HSECR        HSES       LL_RCC_HSE_SetSenseAmplifier
01403   * @param  SenseAmplifier This parameter can be one of the following values:
01404   *         @arg @ref LL_RCC_HSEAMPTHRESHOLD_1_2
01405   *         @arg @ref LL_RCC_HSEAMPTHRESHOLD_3_4
01406   */
01407 __STATIC_INLINE void LL_RCC_HSE_SetSenseAmplifier(uint32_t SenseAmplifier)
01408 {
01409   WRITE_REG(RCC->HSECR, HSE_CONTROL_UNLOCK_KEY);
01410   MODIFY_REG(RCC->HSECR, RCC_HSECR_HSES, SenseAmplifier);
01411 }
01412
01413 /**
01414   * @brief  Get HSE current control
01415   * @rmtoll HSECR        HSES       LL_RCC_HSE_GetSenseAmplifier
01416   * @retval Returned value can be one of the following values:
01417   *         @arg @ref LL_RCC_HSEAMPTHRESHOLD_1_2
01418   *         @arg @ref LL_RCC_HSEAMPTHRESHOLD_3_4
01419   */
01420 __STATIC_INLINE uint32_t LL_RCC_HSE_GetSenseAmplifier(void)
01421 {
01422   return (uint32_t)(READ_BIT(RCC->HSECR, RCC_HSECR_HSES));
01423 }
01424 /**
01425   * @}
01426   */
01427
01428 /** @defgroup RCC_LL_EF_HSI HSI
01429   * @{
01430   */
01431
01432 /**
01433   * @brief  Enable HSI even in stop mode
01434   * @note HSI oscillator is forced ON even in Stop mode
01435   * @rmtoll CR           HSIKERON      LL_RCC_HSI_EnableInStopMode
01436   * @retval None
01437   */
01438 __STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
01439 {
01440   SET_BIT(RCC->CR, RCC_CR_HSIKERON);
01441 }
01442
01443 /**
01444   * @brief  Disable HSI in stop mode
01445   * @rmtoll CR           HSIKERON      LL_RCC_HSI_DisableInStopMode
01446   * @retval None
01447   */
01448 __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
01449 {
01450   CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
01451 }
01452
01453 /**
01454   * @brief  Check if HSI in stop mode is ready
01455   * @rmtoll CR           HSIKERON        LL_RCC_HSI_IsEnabledInStopMode
01456   * @retval State of bit (1 or 0).
01457   */
01458 __STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void)
01459 {
01460   return ((READ_BIT(RCC->CR, RCC_CR_HSIKERON) == (RCC_CR_HSIKERON)) ? 1UL : 0UL);
01461 }
01462
01463 /**
01464   * @brief  Enable HSI oscillator
01465   * @rmtoll CR           HSION         LL_RCC_HSI_Enable
01466   * @retval None
01467   */
01468 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
01469 {
01470   SET_BIT(RCC->CR, RCC_CR_HSION);
01471 }
01472
01473 /**
01474   * @brief  Disable HSI oscillator
01475   * @rmtoll CR           HSION         LL_RCC_HSI_Disable
01476   * @retval None
01477   */
01478 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
01479 {
01480   CLEAR_BIT(RCC->CR, RCC_CR_HSION);
01481 }
01482
01483 /**
01484   * @brief  Check if HSI clock is ready
01485   * @rmtoll CR           HSIRDY        LL_RCC_HSI_IsReady
01486   * @retval State of bit (1 or 0).
01487   */
01488 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
01489 {
01490   return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL);
01491 }
01492
01493 /**
01494   * @brief  Enable HSI Automatic from stop mode
01495   * @rmtoll CR           HSIASFS       LL_RCC_HSI_EnableAutoFromStop
01496   * @retval None
01497   */
01498 __STATIC_INLINE void LL_RCC_HSI_EnableAutoFromStop(void)
01499 {
01500   SET_BIT(RCC->CR, RCC_CR_HSIASFS);
01501 }
01502
01503 /**
01504   * @brief  Disable HSI Automatic from stop mode
01505   * @rmtoll CR           HSIASFS       LL_RCC_HSI_DisableAutoFromStop
01506   * @retval None
01507   */
01508 __STATIC_INLINE void LL_RCC_HSI_DisableAutoFromStop(void)
01509 {
01510   CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS);
01511 }
01512 /**
01513   * @brief  Get HSI Calibration value
01514   * @note When HSITRIM is written, HSICAL is updated with the sum of
01515   *       HSITRIM and the factory trim value
01516   * @rmtoll ICSCR        HSICAL        LL_RCC_HSI_GetCalibration
01517   * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
01518   */
01519 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
01520 {
01521   return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos);
01522 }
01523
01524 /**
01525   * @brief  Set HSI Calibration trimming
01526   * @note user-programmable trimming value that is added to the HSICAL
01527   * @note Default value is 64, which, when added to the HSICAL value,
01528   *       should trim the HSI to 16 MHz +/- 1 %
01529   * @rmtoll ICSCR        HSITRIM       LL_RCC_HSI_SetCalibTrimming
01530   * @param  Value Between Min_Data = 0 and Max_Data = 127
01531   * @retval None
01532   */
01533 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
01534 {
01535   MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
01536 }
01537
01538 /**
01539   * @brief  Get HSI Calibration trimming
01540   * @rmtoll ICSCR        HSITRIM       LL_RCC_HSI_GetCalibTrimming
01541   * @retval Between Min_Data = 0 and Max_Data = 127
01542   */
01543 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
01544 {
01545   return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
01546 }
01547
01548 /**
01549   * @}
01550   */
01551
01552 /** @defgroup RCC_LL_EF_HSI48 HSI48
01553   * @{
01554   */
01555
01556 /**
01557   * @brief  Enable HSI48
01558   * @rmtoll CRRCR          HSI48ON       LL_RCC_HSI48_Enable
01559   * @retval None
01560   */
01561 __STATIC_INLINE void LL_RCC_HSI48_Enable(void)
01562 {
01563   SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
01564 }
01565
01566 /**
01567   * @brief  Disable HSI48
01568   * @rmtoll CRRCR          HSI48ON       LL_RCC_HSI48_Disable
01569   * @retval None
01570   */
01571 __STATIC_INLINE void LL_RCC_HSI48_Disable(void)
01572 {
01573   CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
01574 }
01575
01576 /**
01577   * @brief  Check if HSI48 oscillator Ready
01578   * @rmtoll CRRCR          HSI48RDY      LL_RCC_HSI48_IsReady
01579   * @retval State of bit (1 or 0).
01580   */
01581 __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
01582 {
01583   return ((READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == (RCC_CRRCR_HSI48RDY)) ? 1UL : 0UL);
01584 }
01585
01586 /**
01587   * @brief  Get HSI48 Calibration value
01588   * @rmtoll CRRCR          HSI48CAL      LL_RCC_HSI48_GetCalibration
01589   * @retval Between Min_Data = 0x00 and Max_Data = 0x1FF
01590   */
01591 __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
01592 {
01593   return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
01594 }
01595
01596 /**
01597   * @}
01598   */
01599
01600 /** @defgroup RCC_LL_EF_LSE LSE
01601   * @{
01602   */
01603
01604 /**
01605   * @brief  Enable  Low Speed External (LSE) crystal.
01606   * @rmtoll BDCR         LSEON         LL_RCC_LSE_Enable
01607   * @retval None
01608   */
01609 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
01610 {
01611   SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
01612 }
01613
01614 /**
01615   * @brief  Disable  Low Speed External (LSE) crystal.
01616   * @rmtoll BDCR         LSEON         LL_RCC_LSE_Disable
01617   * @retval None
01618   */
01619 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
01620 {
01621   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
01622 }
01623
01624 /**
01625   * @brief  Check if Low Speed External (LSE) crystal has been enabled or not
01626   * @rmtoll BDCR         LSEON         LL_RCC_LSE_IsEnabled
01627   * @retval State of bit (1 or 0).
01628   */
01629 __STATIC_INLINE uint32_t LL_RCC_LSE_IsEnabled(void)
01630 {
01631   return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSEON) == (RCC_BDCR_LSEON)) ? 1UL : 0UL);
01632 }
01633
01634 /**
01635   * @brief  Enable external clock source (LSE bypass).
01636   * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_EnableBypass
01637   * @retval None
01638   */
01639 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
01640 {
01641   SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
01642 }
01643
01644 /**
01645   * @brief  Disable external clock source (LSE bypass).
01646   * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_DisableBypass
01647   * @retval None
01648   */
01649 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
01650 {
01651   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
01652 }
01653
01654 /**
01655   * @brief  Set LSE oscillator drive capability
01656   * @note The oscillator is in Xtal mode when it is not in bypass mode.
01657   * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_SetDriveCapability
01658   * @param  LSEDrive This parameter can be one of the following values:
01659   *         @arg @ref LL_RCC_LSEDRIVE_LOW
01660   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
01661   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
01662   *         @arg @ref LL_RCC_LSEDRIVE_HIGH
01663   * @retval None
01664   */
01665 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
01666 {
01667   MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
01668 }
01669
01670 /**
01671   * @brief  Get LSE oscillator drive capability
01672   * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_GetDriveCapability
01673   * @retval Returned value can be one of the following values:
01674   *         @arg @ref LL_RCC_LSEDRIVE_LOW
01675   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
01676   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
01677   *         @arg @ref LL_RCC_LSEDRIVE_HIGH
01678   */
01679 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
01680 {
01681   return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
01682 }
01683
01684 /**
01685   * @brief  Enable Clock security system on LSE.
01686   * @rmtoll BDCR         LSECSSON      LL_RCC_LSE_EnableCSS
01687   * @retval None
01688   */
01689 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
01690 {
01691   SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
01692 }
01693
01694 /**
01695   * @brief  Disable Clock security system on LSE.
01696   * @note Clock security system can be disabled only after a LSE
01697   *       failure detection. In that case it MUST be disabled by software.
01698   * @rmtoll BDCR         LSECSSON      LL_RCC_LSE_DisableCSS
01699   * @retval None
01700   */
01701 __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
01702 {
01703   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
01704 }
01705
01706 /**
01707   * @brief  Check if LSE oscillator Ready
01708   * @rmtoll BDCR         LSERDY        LL_RCC_LSE_IsReady
01709   * @retval State of bit (1 or 0).
01710   */
01711 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
01712 {
01713   return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL);
01714 }
01715
01716 /**
01717   * @brief  Check if CSS on LSE failure Detection
01718   * @rmtoll BDCR         LSECSSD       LL_RCC_LSE_IsCSSDetected
01719   * @retval State of bit (1 or 0).
01720   */
01721 __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
01722 {
01723   return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD)) ? 1UL : 0UL);
01724 }
01725
01726 /**
01727   * @}
01728   */
01729
01730 /** @defgroup RCC_LL_EF_LSI1 LSI1
01731   * @{
01732   */
01733
01734 /**
01735   * @brief  Enable LSI1 Oscillator
01736   * @rmtoll CSR          LSI1ON         LL_RCC_LSI1_Enable
01737   * @retval None
01738   */
01739 __STATIC_INLINE void LL_RCC_LSI1_Enable(void)
01740 {
01741   SET_BIT(RCC->CSR, RCC_CSR_LSI1ON);
01742 }
01743
01744 /**
01745   * @brief  Disable LSI1 Oscillator
01746   * @rmtoll CSR          LSI1ON         LL_RCC_LSI1_Disable
01747   * @retval None
01748   */
01749 __STATIC_INLINE void LL_RCC_LSI1_Disable(void)
01750 {
01751   CLEAR_BIT(RCC->CSR, RCC_CSR_LSI1ON);
01752 }
01753
01754 /**
01755   * @brief  Check if LSI1 is Ready
01756   * @rmtoll CSR          LSI1RDY        LL_RCC_LSI1_IsReady
01757   * @retval State of bit (1 or 0).
01758   */
01759 __STATIC_INLINE uint32_t LL_RCC_LSI1_IsReady(void)
01760 {
01761   return ((READ_BIT(RCC->CSR, RCC_CSR_LSI1RDY) == (RCC_CSR_LSI1RDY)) ? 1UL : 0UL);
01762 }
01763
01764 /**
01765   * @}
01766   */
01767
01768 /** @defgroup RCC_LL_EF_LSI2 LSI2
01769   * @{
01770   */
01771
01772 /**
01773   * @brief  Enable LSI2 Oscillator
01774   * @rmtoll CSR          LSI2ON         LL_RCC_LSI2_Enable
01775   * @retval None
01776   */
01777 __STATIC_INLINE void LL_RCC_LSI2_Enable(void)
01778 {
01779   SET_BIT(RCC->CSR, RCC_CSR_LSI2ON);
01780 }
01781
01782 /**
01783   * @brief  Disable LSI2 Oscillator
01784   * @rmtoll CSR          LSI2ON         LL_RCC_LSI2_Disable
01785   * @retval None
01786   */
01787 __STATIC_INLINE void LL_RCC_LSI2_Disable(void)
01788 {
01789   CLEAR_BIT(RCC->CSR, RCC_CSR_LSI2ON);
01790 }
01791
01792 /**
01793   * @brief  Check if LSI2 is Ready
01794   * @rmtoll CSR          LSI2RDY        LL_RCC_LSI2_IsReady
01795   * @retval State of bit (1 or 0).
01796   */
01797 __STATIC_INLINE uint32_t LL_RCC_LSI2_IsReady(void)
01798 {
01799   return ((READ_BIT(RCC->CSR, RCC_CSR_LSI2RDY) == (RCC_CSR_LSI2RDY)) ? 1UL : 0UL);
01800 }
01801
01802 /**
01803   * @brief  Set LSI2 trimming value
01804   * @rmtoll CSR        LSI2TRIM       LL_RCC_LSI2_SetTrimming
01805   * @param  Value Between Min_Data = 0 and Max_Data = 15
01806   * @retval None
01807   */
01808 __STATIC_INLINE void LL_RCC_LSI2_SetTrimming(uint32_t Value)
01809 {
01810   MODIFY_REG(RCC->CSR, RCC_CSR_LSI2TRIM, Value << RCC_CSR_LSI2TRIM_Pos);
01811 }
01812
01813 /**
01814   * @brief  Get LSI2 trimming value
01815   * @rmtoll CSR        LSI2TRIM       LL_RCC_LSI2_GetTrimming
01816   * @retval Between Min_Data = 0 and Max_Data = 12
01817   */
01818 __STATIC_INLINE uint32_t LL_RCC_LSI2_GetTrimming(void)
01819 {
01820   return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_LSI2TRIM) >> RCC_CSR_LSI2TRIM_Pos);
01821 }
01822
01823 /**
01824   * @}
01825   */
01826
01827 /** @defgroup RCC_LL_EF_MSI MSI
01828   * @{
01829   */
01830
01831 /**
01832   * @brief  Enable MSI oscillator
01833   * @rmtoll CR           MSION         LL_RCC_MSI_Enable
01834   * @retval None
01835   */
01836 __STATIC_INLINE void LL_RCC_MSI_Enable(void)
01837 {
01838   SET_BIT(RCC->CR, RCC_CR_MSION);
01839 }
01840
01841 /**
01842   * @brief  Disable MSI oscillator
01843   * @rmtoll CR           MSION         LL_RCC_MSI_Disable
01844   * @retval None
01845   */
01846 __STATIC_INLINE void LL_RCC_MSI_Disable(void)
01847 {
01848   CLEAR_BIT(RCC->CR, RCC_CR_MSION);
01849 }
01850
01851 /**
01852   * @brief  Check if MSI oscillator Ready
01853   * @rmtoll CR           MSIRDY        LL_RCC_MSI_IsReady
01854   * @retval State of bit (1 or 0).
01855   */
01856 __STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
01857 {
01858   return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY)) ? 1UL : 0UL);
01859 }
01860
01861 /**
01862   * @brief  Enable MSI PLL-mode (Hardware auto calibration with LSE)
01863   * @note MSIPLLEN must be enabled after LSE is enabled (LSEON enabled)
01864   *       and ready (LSERDY set by hardware)
01865   * @note hardware protection to avoid enabling MSIPLLEN if LSE is not
01866   *       ready
01867   * @rmtoll CR           MSIPLLEN      LL_RCC_MSI_EnablePLLMode
01868   * @retval None
01869   */
01870 __STATIC_INLINE void LL_RCC_MSI_EnablePLLMode(void)
01871 {
01872   SET_BIT(RCC->CR, RCC_CR_MSIPLLEN);
01873 }
01874
01875 /**
01876   * @brief  Disable MSI-PLL mode
01877   * @note cleared by hardware when LSE is disabled (LSEON = 0) or when
01878   *       the Clock Security System on LSE detects a LSE failure
01879   * @rmtoll CR           MSIPLLEN      LL_RCC_MSI_DisablePLLMode
01880   * @retval None
01881   */
01882 __STATIC_INLINE void LL_RCC_MSI_DisablePLLMode(void)
01883 {
01884   CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN);
01885 }
01886
01887
01888 /**
01889   * @brief  Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.
01890   * @rmtoll CR           MSIRANGE      LL_RCC_MSI_SetRange
01891   * @param  Range This parameter can be one of the following values:
01892   *         @arg @ref LL_RCC_MSIRANGE_0
01893   *         @arg @ref LL_RCC_MSIRANGE_1
01894   *         @arg @ref LL_RCC_MSIRANGE_2
01895   *         @arg @ref LL_RCC_MSIRANGE_3
01896   *         @arg @ref LL_RCC_MSIRANGE_4
01897   *         @arg @ref LL_RCC_MSIRANGE_5
01898   *         @arg @ref LL_RCC_MSIRANGE_6
01899   *         @arg @ref LL_RCC_MSIRANGE_7
01900   *         @arg @ref LL_RCC_MSIRANGE_8
01901   *         @arg @ref LL_RCC_MSIRANGE_9
01902   *         @arg @ref LL_RCC_MSIRANGE_10
01903   *         @arg @ref LL_RCC_MSIRANGE_11
01904   * @retval None
01905   */
01906 __STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)
01907 {
01908   MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, Range);
01909 }
01910
01911 /**
01912   * @brief  Get the Internal Multi Speed oscillator (MSI) clock range in run mode.
01913   * @rmtoll CR           MSIRANGE      LL_RCC_MSI_GetRange
01914   * @retval Returned value can be one of the following values:
01915   *         @arg @ref LL_RCC_MSIRANGE_0
01916   *         @arg @ref LL_RCC_MSIRANGE_1
01917   *         @arg @ref LL_RCC_MSIRANGE_2
01918   *         @arg @ref LL_RCC_MSIRANGE_3
01919   *         @arg @ref LL_RCC_MSIRANGE_4
01920   *         @arg @ref LL_RCC_MSIRANGE_5
01921   *         @arg @ref LL_RCC_MSIRANGE_6
01922   *         @arg @ref LL_RCC_MSIRANGE_7
01923   *         @arg @ref LL_RCC_MSIRANGE_8
01924   *         @arg @ref LL_RCC_MSIRANGE_9
01925   *         @arg @ref LL_RCC_MSIRANGE_10
01926   *         @arg @ref LL_RCC_MSIRANGE_11
01927   */
01928 __STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void)
01929 {
01930   uint32_t msiRange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE);
01931   if (msiRange > LL_RCC_MSIRANGE_11)
01932   {
01933     msiRange = LL_RCC_MSIRANGE_11;
01934   }
01935   return msiRange;
01936 }
01937
01938
01939 /**
01940   * @brief  Get MSI Calibration value
01941   * @note When MSITRIM is written, MSICAL is updated with the sum of
01942   *       MSITRIM and the factory trim value
01943   * @rmtoll ICSCR        MSICAL        LL_RCC_MSI_GetCalibration
01944   * @retval Between Min_Data = 0 and Max_Data = 255
01945   */
01946 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void)
01947 {
01948   return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_ICSCR_MSICAL_Pos);
01949 }
01950
01951 /**
01952   * @brief  Set MSI Calibration trimming
01953   * @note user-programmable trimming value that is added to the MSICAL
01954   * @rmtoll ICSCR        MSITRIM       LL_RCC_MSI_SetCalibTrimming
01955   * @param  Value Between Min_Data = 0 and Max_Data = 255
01956   * @retval None
01957   */
01958 __STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)
01959 {
01960   MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos);
01961 }
01962
01963 /**
01964   * @brief  Get MSI Calibration trimming
01965   * @rmtoll ICSCR        MSITRIM       LL_RCC_MSI_GetCalibTrimming
01966   * @retval Between 0 and 255
01967   */
01968 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void)
01969 {
01970   return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos);
01971 }
01972
01973 /**
01974   * @}
01975   */
01976
01977 /** @defgroup RCC_LL_EF_LSCO LSCO
01978   * @{
01979   */
01980
01981 /**
01982   * @brief  Enable Low speed clock
01983   * @rmtoll BDCR         LSCOEN        LL_RCC_LSCO_Enable
01984   * @retval None
01985   */
01986 __STATIC_INLINE void LL_RCC_LSCO_Enable(void)
01987 {
01988   SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
01989 }
01990
01991 /**
01992   * @brief  Disable Low speed clock
01993   * @rmtoll BDCR         LSCOEN        LL_RCC_LSCO_Disable
01994   * @retval None
01995   */
01996 __STATIC_INLINE void LL_RCC_LSCO_Disable(void)
01997 {
01998   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
01999 }
02000
02001 /**
02002   * @brief  Configure Low speed clock selection
02003   * @rmtoll BDCR         LSCOSEL       LL_RCC_LSCO_SetSource
02004   * @param  Source This parameter can be one of the following values:
02005   *         @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
02006   *         @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
02007   * @retval None
02008   */
02009 __STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
02010 {
02011   MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source);
02012 }
02013
02014 /**
02015   * @brief  Get Low speed clock selection
02016   * @rmtoll BDCR         LSCOSEL       LL_RCC_LSCO_GetSource
02017   * @retval Returned value can be one of the following values:
02018   *         @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
02019   *         @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
02020   */
02021 __STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
02022 {
02023   return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL));
02024 }
02025
02026 /**
02027   * @}
02028   */
02029
02030 /** @defgroup RCC_LL_EF_System System
02031   * @{
02032   */
02033
02034 /**
02035   * @brief  Configure the system clock source
02036   * @rmtoll CFGR         SW            LL_RCC_SetSysClkSource
02037   * @param  Source This parameter can be one of the following values:
02038   *         @arg @ref LL_RCC_SYS_CLKSOURCE_MSI
02039   *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
02040   *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
02041   *         @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
02042   * @retval None
02043   */
02044 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
02045 {
02046   MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
02047 }
02048
02049 /**
02050   * @brief  Get the system clock source
02051   * @rmtoll CFGR         SWS           LL_RCC_GetSysClkSource
02052   * @retval Returned value can be one of the following values:
02053   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI
02054   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
02055   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
02056   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
02057   */
02058 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
02059 {
02060   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
02061 }
02062
02063 /**
02064   * @brief  Get the RF clock source
02065   * @rmtoll EXTCFGR         RFCSS           LL_RCC_GetRFClockSource
02066   * @retval Returned value can be one of the following values:
02067   *         @arg @ref LL_RCC_RF_CLKSOURCE_HSI
02068   *         @arg @ref LL_RCC_RF_CLKSOURCE_HSE_DIV2
02069   */
02070 __STATIC_INLINE uint32_t LL_RCC_GetRFClockSource(void)
02071 {
02072   return (uint32_t)(READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_RFCSS));
02073 }
02074
02075 /**
02076   * @brief  Set RF Wakeup Clock Source
02077   * @rmtoll CSR         RFWKPSEL        LL_RCC_SetRFWKPClockSource
02078   * @param  Source This parameter can be one of the following values:
02079   *         @arg @ref LL_RCC_RFWKP_CLKSOURCE_NONE
02080   *         @arg @ref LL_RCC_RFWKP_CLKSOURCE_LSE
02081   *         @arg @ref LL_RCC_RFWKP_CLKSOURCE_LSI
02082   *         @arg @ref LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024
02083   * @retval None
02084   */
02085 __STATIC_INLINE void LL_RCC_SetRFWKPClockSource(uint32_t Source)
02086 {
02087   MODIFY_REG(RCC->CSR, RCC_CSR_RFWKPSEL, Source);
02088 }
02089
02090 /**
02091   * @brief  Get RF Wakeup Clock Source
02092   * @rmtoll CSR         RFWKPSEL        LL_RCC_GetRFWKPClockSource
02093   * @retval Returned value can be one of the following values:
02094   *         @arg @ref LL_RCC_RFWKP_CLKSOURCE_NONE
02095   *         @arg @ref LL_RCC_RFWKP_CLKSOURCE_LSE
02096   *         @arg @ref LL_RCC_RFWKP_CLKSOURCE_LSI
02097   *         @arg @ref LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024
02098   */
02099 __STATIC_INLINE uint32_t LL_RCC_GetRFWKPClockSource(void)
02100 {
02101   return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_RFWKPSEL));
02102 }
02103
02104 /**
02105   * @brief  Check if Radio System is reset.
02106   * @rmtoll CSR          RFRSTS       LL_RCC_IsRFUnderReset
02107   * @retval State of bit (1 or 0).
02108   */
02109 __STATIC_INLINE uint32_t LL_RCC_IsRFUnderReset(void)
02110 {
02111   return ((READ_BIT(RCC->CSR, RCC_CSR_RFRSTS) == (RCC_CSR_RFRSTS)) ? 1UL : 0UL);
02112 }
02113
02114 /**
02115   * @brief  Set AHB prescaler
02116   * @rmtoll CFGR         HPRE          LL_RCC_SetAHBPrescaler
02117   * @param  Prescaler This parameter can be one of the following values:
02118   *         @arg @ref LL_RCC_SYSCLK_DIV_1
02119   *         @arg @ref LL_RCC_SYSCLK_DIV_2
02120   *         @arg @ref LL_RCC_SYSCLK_DIV_3
02121   *         @arg @ref LL_RCC_SYSCLK_DIV_4
02122   *         @arg @ref LL_RCC_SYSCLK_DIV_5
02123   *         @arg @ref LL_RCC_SYSCLK_DIV_6
02124   *         @arg @ref LL_RCC_SYSCLK_DIV_8
02125   *         @arg @ref LL_RCC_SYSCLK_DIV_10
02126   *         @arg @ref LL_RCC_SYSCLK_DIV_16
02127   *         @arg @ref LL_RCC_SYSCLK_DIV_32
02128   *         @arg @ref LL_RCC_SYSCLK_DIV_64
02129   *         @arg @ref LL_RCC_SYSCLK_DIV_128
02130   *         @arg @ref LL_RCC_SYSCLK_DIV_256
02131   *         @arg @ref LL_RCC_SYSCLK_DIV_512
02132   * @retval None
02133   */
02134 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
02135 {
02136   MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
02137 }
02138
02139 /**
02140   * @brief  Set CPU2 AHB prescaler
02141   * @rmtoll EXTCFGR         C2HPRE          LL_C2_RCC_SetAHBPrescaler
02142   * @param  Prescaler This parameter can be one of the following values:
02143   *         @arg @ref LL_RCC_SYSCLK_DIV_1
02144   *         @arg @ref LL_RCC_SYSCLK_DIV_2
02145   *         @arg @ref LL_RCC_SYSCLK_DIV_3
02146   *         @arg @ref LL_RCC_SYSCLK_DIV_4
02147   *         @arg @ref LL_RCC_SYSCLK_DIV_5
02148   *         @arg @ref LL_RCC_SYSCLK_DIV_6
02149   *         @arg @ref LL_RCC_SYSCLK_DIV_8
02150   *         @arg @ref LL_RCC_SYSCLK_DIV_10
02151   *         @arg @ref LL_RCC_SYSCLK_DIV_16
02152   *         @arg @ref LL_RCC_SYSCLK_DIV_32
02153   *         @arg @ref LL_RCC_SYSCLK_DIV_64
02154   *         @arg @ref LL_RCC_SYSCLK_DIV_128
02155   *         @arg @ref LL_RCC_SYSCLK_DIV_256
02156   *         @arg @ref LL_RCC_SYSCLK_DIV_512
02157   * @retval None
02158   */
02159 __STATIC_INLINE void LL_C2_RCC_SetAHBPrescaler(uint32_t Prescaler)
02160 {
02161   MODIFY_REG(RCC->EXTCFGR, RCC_EXTCFGR_C2HPRE, Prescaler);
02162 }
02163
02164 /**
02165   * @brief  Set AHB4 prescaler
02166   * @rmtoll EXTCFGR         SHDHPRE          LL_RCC_SetAHB4Prescaler
02167   * @param  Prescaler This parameter can be one of the following values:
02168   *         @arg @ref LL_RCC_SYSCLK_DIV_1
02169   *         @arg @ref LL_RCC_SYSCLK_DIV_2
02170   *         @arg @ref LL_RCC_SYSCLK_DIV_3
02171   *         @arg @ref LL_RCC_SYSCLK_DIV_4
02172   *         @arg @ref LL_RCC_SYSCLK_DIV_5
02173   *         @arg @ref LL_RCC_SYSCLK_DIV_6
02174   *         @arg @ref LL_RCC_SYSCLK_DIV_8
02175   *         @arg @ref LL_RCC_SYSCLK_DIV_10
02176   *         @arg @ref LL_RCC_SYSCLK_DIV_16
02177   *         @arg @ref LL_RCC_SYSCLK_DIV_32
02178   *         @arg @ref LL_RCC_SYSCLK_DIV_64
02179   *         @arg @ref LL_RCC_SYSCLK_DIV_128
02180   *         @arg @ref LL_RCC_SYSCLK_DIV_256
02181   *         @arg @ref LL_RCC_SYSCLK_DIV_512
02182   * @retval None
02183   */
02184 __STATIC_INLINE void LL_RCC_SetAHB4Prescaler(uint32_t Prescaler)
02185 {
02186   MODIFY_REG(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPRE, Prescaler >> 4);
02187 }
02188
02189 /**
02190   * @brief  Set APB1 prescaler
02191   * @rmtoll CFGR         PPRE1         LL_RCC_SetAPB1Prescaler
02192   * @param  Prescaler This parameter can be one of the following values:
02193   *         @arg @ref LL_RCC_APB1_DIV_1
02194   *         @arg @ref LL_RCC_APB1_DIV_2
02195   *         @arg @ref LL_RCC_APB1_DIV_4
02196   *         @arg @ref LL_RCC_APB1_DIV_8
02197   *         @arg @ref LL_RCC_APB1_DIV_16
02198   * @retval None
02199   */
02200 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
02201 {
02202   MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
02203 }
02204
02205 /**
02206   * @brief  Set APB2 prescaler
02207   * @rmtoll CFGR         PPRE2         LL_RCC_SetAPB2Prescaler
02208   * @param  Prescaler This parameter can be one of the following values:
02209   *         @arg @ref LL_RCC_APB2_DIV_1
02210   *         @arg @ref LL_RCC_APB2_DIV_2
02211   *         @arg @ref LL_RCC_APB2_DIV_4
02212   *         @arg @ref LL_RCC_APB2_DIV_8
02213   *         @arg @ref LL_RCC_APB2_DIV_16
02214   * @retval None
02215   */
02216 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
02217 {
02218   MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
02219 }
02220
02221 /**
02222   * @brief  Get AHB prescaler
02223   * @rmtoll CFGR         HPRE          LL_RCC_GetAHBPrescaler
02224   * @retval Returned value can be one of the following values:
02225   *         @arg @ref LL_RCC_SYSCLK_DIV_1
02226   *         @arg @ref LL_RCC_SYSCLK_DIV_2
02227   *         @arg @ref LL_RCC_SYSCLK_DIV_3
02228   *         @arg @ref LL_RCC_SYSCLK_DIV_4
02229   *         @arg @ref LL_RCC_SYSCLK_DIV_5
02230   *         @arg @ref LL_RCC_SYSCLK_DIV_6
02231   *         @arg @ref LL_RCC_SYSCLK_DIV_8
02232   *         @arg @ref LL_RCC_SYSCLK_DIV_10
02233   *         @arg @ref LL_RCC_SYSCLK_DIV_16
02234   *         @arg @ref LL_RCC_SYSCLK_DIV_32
02235   *         @arg @ref LL_RCC_SYSCLK_DIV_64
02236   *         @arg @ref LL_RCC_SYSCLK_DIV_128
02237   *         @arg @ref LL_RCC_SYSCLK_DIV_256
02238   *         @arg @ref LL_RCC_SYSCLK_DIV_512
02239   */
02240 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
02241 {
02242   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
02243 }
02244
02245 /**
02246   * @brief  Get C2 AHB prescaler
02247   * @rmtoll EXTCFGR         C2HPRE          LL_C2_RCC_GetAHBPrescaler
02248   * @retval Returned value can be one of the following values:
02249   *         @arg @ref LL_RCC_SYSCLK_DIV_1
02250   *         @arg @ref LL_RCC_SYSCLK_DIV_2
02251   *         @arg @ref LL_RCC_SYSCLK_DIV_3
02252   *         @arg @ref LL_RCC_SYSCLK_DIV_4
02253   *         @arg @ref LL_RCC_SYSCLK_DIV_5
02254   *         @arg @ref LL_RCC_SYSCLK_DIV_6
02255   *         @arg @ref LL_RCC_SYSCLK_DIV_8
02256   *         @arg @ref LL_RCC_SYSCLK_DIV_10
02257   *         @arg @ref LL_RCC_SYSCLK_DIV_16
02258   *         @arg @ref LL_RCC_SYSCLK_DIV_32
02259   *         @arg @ref LL_RCC_SYSCLK_DIV_64
02260   *         @arg @ref LL_RCC_SYSCLK_DIV_128
02261   *         @arg @ref LL_RCC_SYSCLK_DIV_256
02262   *         @arg @ref LL_RCC_SYSCLK_DIV_512
02263   */
02264 __STATIC_INLINE uint32_t LL_C2_RCC_GetAHBPrescaler(void)
02265 {
02266   return (uint32_t)(READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_C2HPRE));
02267 }
02268
02269 /**
02270   * @brief  Get AHB4 prescaler
02271   * @rmtoll EXTCFGR         SHDHPRE          LL_RCC_GetAHB4Prescaler
02272   * @retval Returned value can be one of the following values:
02273   *         @arg @ref LL_RCC_SYSCLK_DIV_1
02274   *         @arg @ref LL_RCC_SYSCLK_DIV_2
02275   *         @arg @ref LL_RCC_SYSCLK_DIV_3
02276   *         @arg @ref LL_RCC_SYSCLK_DIV_4
02277   *         @arg @ref LL_RCC_SYSCLK_DIV_5
02278   *         @arg @ref LL_RCC_SYSCLK_DIV_6
02279   *         @arg @ref LL_RCC_SYSCLK_DIV_8
02280   *         @arg @ref LL_RCC_SYSCLK_DIV_10
02281   *         @arg @ref LL_RCC_SYSCLK_DIV_16
02282   *         @arg @ref LL_RCC_SYSCLK_DIV_32
02283   *         @arg @ref LL_RCC_SYSCLK_DIV_64
02284   *         @arg @ref LL_RCC_SYSCLK_DIV_128
02285   *         @arg @ref LL_RCC_SYSCLK_DIV_256
02286   *         @arg @ref LL_RCC_SYSCLK_DIV_512
02287   */
02288 __STATIC_INLINE uint32_t LL_RCC_GetAHB4Prescaler(void)
02289 {
02290   return (uint32_t)(READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPRE) << 4);
02291 }
02292
02293 /**
02294   * @brief  Get APB1 prescaler
02295   * @rmtoll CFGR         PPRE1         LL_RCC_GetAPB1Prescaler
02296   * @retval Returned value can be one of the following values:
02297   *         @arg @ref LL_RCC_APB1_DIV_1
02298   *         @arg @ref LL_RCC_APB1_DIV_2
02299   *         @arg @ref LL_RCC_APB1_DIV_4
02300   *         @arg @ref LL_RCC_APB1_DIV_8
02301   *         @arg @ref LL_RCC_APB1_DIV_16
02302   */
02303 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
02304 {
02305   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
02306 }
02307
02308 /**
02309   * @brief  Get APB2 prescaler
02310   * @rmtoll CFGR         PPRE2         LL_RCC_GetAPB2Prescaler
02311   * @retval Returned value can be one of the following values:
02312   *         @arg @ref LL_RCC_APB2_DIV_1
02313   *         @arg @ref LL_RCC_APB2_DIV_2
02314   *         @arg @ref LL_RCC_APB2_DIV_4
02315   *         @arg @ref LL_RCC_APB2_DIV_8
02316   *         @arg @ref LL_RCC_APB2_DIV_16
02317   */
02318 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
02319 {
02320   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
02321 }
02322
02323 /**
02324   * @brief  Set Clock After Wake-Up From Stop mode
02325   * @rmtoll CFGR         STOPWUCK      LL_RCC_SetClkAfterWakeFromStop
02326   * @param  Clock This parameter can be one of the following values:
02327   *         @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
02328   *         @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
02329   * @retval None
02330   */
02331 __STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)
02332 {
02333   MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock);
02334 }
02335
02336 /**
02337   * @brief  Get Clock After Wake-Up From Stop mode
02338   * @rmtoll CFGR         STOPWUCK      LL_RCC_GetClkAfterWakeFromStop
02339   * @retval Returned value can be one of the following values:
02340   *         @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
02341   *         @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
02342   */
02343 __STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void)
02344 {
02345   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK));
02346 }
02347
02348 /**
02349   * @}
02350   */
02351
02352 #if defined(RCC_SMPS_SUPPORT)
02353 /** @defgroup RCC_LL_EF_SMPS SMPS
02354   * @{
02355   */
02356 /**
02357   * @brief  Configure SMPS step down converter clock source
02358   * @rmtoll SMPSCR        SMPSSEL     LL_RCC_SetSMPSClockSource
02359   * @param  SMPSSource This parameter can be one of the following values:
02360   *         @arg @ref LL_RCC_SMPS_CLKSOURCE_HSI
02361   *         @arg @ref LL_RCC_SMPS_CLKSOURCE_MSI (*)
02362   *         @arg @ref LL_RCC_SMPS_CLKSOURCE_HSE
02363   * @note   The system must always be configured so as to get a SMPS Step Down
02364   *         converter clock frequency between 2 MHz and 8 MHz
02365   * @note   (*) The MSI shall only be selected as SMPS Step Down converter
02366   *          clock source when a supported SMPS Step Down converter clock
02367   *          MSIRANGE is set (LL_RCC_MSIRANGE_8 to LL_RCC_MSIRANGE_11)
02368   * @retval None
02369   */
02370 __STATIC_INLINE void LL_RCC_SetSMPSClockSource(uint32_t SMPSSource)
02371 {
02372   MODIFY_REG(RCC->SMPSCR, RCC_SMPSCR_SMPSSEL, SMPSSource);
02373 }
02374
02375 /**
02376   * @brief  Get the SMPS clock source selection
02377   * @rmtoll SMPSCR         SMPSSEL           LL_RCC_GetSMPSClockSelection
02378   * @retval Returned value can be one of the following values:
02379   *         @arg @ref LL_RCC_SMPS_CLKSOURCE_HSI
02380   *         @arg @ref LL_RCC_SMPS_CLKSOURCE_MSI
02381   *         @arg @ref LL_RCC_SMPS_CLKSOURCE_HSE
02382   */
02383 __STATIC_INLINE uint32_t LL_RCC_GetSMPSClockSelection(void)
02384 {
02385   return (uint32_t)(READ_BIT(RCC->SMPSCR, RCC_SMPSCR_SMPSSEL));
02386 }
02387
02388
02389 /**
02390   * @brief  Get the SMPS clock source
02391   * @rmtoll SMPSCR         SMPSSWS           LL_RCC_GetSMPSClockSource
02392   * @retval Returned value can be one of the following values:
02393   *         @arg @ref LL_RCC_SMPS_CLKSOURCE_STATUS_HSI
02394   *         @arg @ref LL_RCC_SMPS_CLKSOURCE_STATUS_MSI
02395   *         @arg @ref LL_RCC_SMPS_CLKSOURCE_STATUS_HSE
02396   *         @arg @ref LL_RCC_SMPS_CLKSOURCE_STATUS_NO_CLOCK
02397   */
02398 __STATIC_INLINE uint32_t LL_RCC_GetSMPSClockSource(void)
02399 {
02400   return (uint32_t)(READ_BIT(RCC->SMPSCR, RCC_SMPSCR_SMPSSWS));
02401 }
02402
02403 /**
02404   * @brief  Set SMPS prescaler
02405   * @rmtoll SMPSCR         SMPSDIV          LL_RCC_SetSMPSPrescaler
02406   * @param  Prescaler This parameter can be one of the following values:
02407   *         @arg @ref LL_RCC_SMPS_DIV_0
02408   *         @arg @ref LL_RCC_SMPS_DIV_1
02409   *         @arg @ref LL_RCC_SMPS_DIV_2
02410   *         @arg @ref LL_RCC_SMPS_DIV_3
02411   * @retval None
02412   */
02413 __STATIC_INLINE void LL_RCC_SetSMPSPrescaler(uint32_t Prescaler)
02414 {
02415   MODIFY_REG(RCC->SMPSCR, RCC_SMPSCR_SMPSDIV, Prescaler);
02416 }
02417
02418 /**
02419   * @brief  Get SMPS prescaler
02420   * @rmtoll SMPSCR         SMPSDIV          LL_RCC_GetSMPSPrescaler
02421   * @retval Returned value can be one of the following values:
02422   *         @arg @ref LL_RCC_SMPS_DIV_0
02423   *         @arg @ref LL_RCC_SMPS_DIV_1
02424   *         @arg @ref LL_RCC_SMPS_DIV_2
02425   *         @arg @ref LL_RCC_SMPS_DIV_3
02426   */
02427 __STATIC_INLINE uint32_t LL_RCC_GetSMPSPrescaler(void)
02428 {
02429   return (uint32_t)(READ_BIT(RCC->SMPSCR, RCC_SMPSCR_SMPSDIV));
02430 }
02431
02432 /**
02433   * @}
02434   */
02435 #endif
02436
02437 /** @defgroup RCC_LL_EF_MCO MCO
02438   * @{
02439   */
02440
02441 /**
02442   * @brief  Configure MCOx
02443   * @rmtoll CFGR         MCOSEL        LL_RCC_ConfigMCO\n
02444   *         CFGR         MCOPRE        LL_RCC_ConfigMCO
02445   * @param  MCOxSource This parameter can be one of the following values:
02446   *         @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
02447   *         @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
02448   *         @arg @ref LL_RCC_MCO1SOURCE_MSI
02449   *         @arg @ref LL_RCC_MCO1SOURCE_HSI
02450   *         @arg @ref LL_RCC_MCO1SOURCE_HSE
02451   *         @arg @ref LL_RCC_MCO1SOURCE_HSI48
02452   *         @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
02453   *         @arg @ref LL_RCC_MCO1SOURCE_LSI1
02454   *         @arg @ref LL_RCC_MCO1SOURCE_LSI2
02455   *         @arg @ref LL_RCC_MCO1SOURCE_LSE
02456   *         @arg @ref LL_RCC_MCO1SOURCE_HSE_BEFORE_STAB
02457   * @param  MCOxPrescaler This parameter can be one of the following values:
02458   *         @arg @ref LL_RCC_MCO1_DIV_1
02459   *         @arg @ref LL_RCC_MCO1_DIV_2
02460   *         @arg @ref LL_RCC_MCO1_DIV_4
02461   *         @arg @ref LL_RCC_MCO1_DIV_8
02462   *         @arg @ref LL_RCC_MCO1_DIV_16
02463   * @retval None
02464   */
02465 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
02466 {
02467   MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
02468 }
02469
02470 /**
02471   * @}
02472   */
02473
02474 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
02475   * @{
02476   */
02477
02478 /**
02479   * @brief  Configure USARTx clock source
02480   * @rmtoll CCIPR        USART1SEL     LL_RCC_SetUSARTClockSource
02481   * @param  USARTxSource This parameter can be one of the following values:
02482   *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
02483   *         @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
02484   *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
02485   *         @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
02486   * @retval None
02487   */
02488 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
02489 {
02490   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, USARTxSource);
02491 }
02492
02493 #if defined(LPUART1)
02494 /**
02495   * @brief  Configure LPUART1x clock source
02496   * @rmtoll CCIPR        LPUART1SEL    LL_RCC_SetLPUARTClockSource
02497   * @param  LPUARTxSource This parameter can be one of the following values:
02498   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
02499   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
02500   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
02501   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
02502   * @retval None
02503   */
02504 __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
02505 {
02506   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource);
02507 }
02508 #endif
02509
02510 /**
02511   * @brief  Configure I2Cx clock source
02512   * @rmtoll CCIPR        I2CxSEL       LL_RCC_SetI2CClockSource
02513   * @param  I2CxSource This parameter can be one of the following values:
02514   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
02515   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
02516   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
02517   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
02518   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
02519   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
02520   * @retval None
02521   */
02522 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
02523 {
02524   MODIFY_REG(RCC->CCIPR, ((I2CxSource >> 4) & 0x000FF000U), ((I2CxSource << 4) & 0x000FF000U));
02525 }
02526
02527 /**
02528   * @brief  Configure LPTIMx clock source
02529   * @rmtoll CCIPR        LPTIMxSEL     LL_RCC_SetLPTIMClockSource
02530   * @param  LPTIMxSource This parameter can be one of the following values:
02531   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
02532   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
02533   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
02534   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
02535   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
02536   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
02537   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
02538   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
02539   * @retval None
02540   */
02541 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
02542 {
02543   MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16));
02544 }
02545
02546 #if defined(SAI1)
02547 /**
02548   * @brief  Configure SAIx clock source
02549   * @rmtoll CCIPR        SAI1SEL       LL_RCC_SetSAIClockSource
02550   * @param  SAIxSource This parameter can be one of the following values:
02551   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1
02552   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
02553   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI
02554   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
02555   * @retval None
02556   */
02557 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
02558 {
02559   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, SAIxSource);
02560 }
02561 #endif
02562
02563 /**
02564   * @brief  Configure RNG clock source
02565   * @note In case of CLK48 clock selected, it must be configured first thanks to LL_RCC_SetCLK48ClockSource
02566   * @rmtoll CCIPR        RNGSEL      LL_RCC_SetRNGClockSource
02567   * @param  RNGxSource This parameter can be one of the following values:
02568   *         @arg @ref LL_RCC_RNG_CLKSOURCE_CLK48
02569   *         @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
02570   *         @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
02571   * @retval None
02572   */
02573 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
02574 {
02575   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGSEL, RNGxSource);
02576 }
02577
02578 /**
02579   * @brief  Configure CLK48 clock source
02580   * @rmtoll CCIPR        CLK48SEL      LL_RCC_SetCLK48ClockSource
02581   * @param  CLK48xSource This parameter can be one of the following values:
02582   *         @arg @ref LL_RCC_CLK48_CLKSOURCE_HSI48
02583   *         @arg @ref LL_RCC_CLK48_CLKSOURCE_PLLSAI1
02584   *         @arg @ref LL_RCC_CLK48_CLKSOURCE_PLL
02585   *         @arg @ref LL_RCC_CLK48_CLKSOURCE_MSI
02586   * @retval None
02587   */
02588 __STATIC_INLINE void LL_RCC_SetCLK48ClockSource(uint32_t CLK48xSource)
02589 {
02590   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, CLK48xSource);
02591 }
02592
02593 /**
02594   * @brief  Configure USB clock source
02595   * @rmtoll CCIPR        CLK48SEL      LL_RCC_SetUSBClockSource
02596   * @param  USBxSource This parameter can be one of the following values:
02597   *         @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
02598   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1
02599   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL
02600   *         @arg @ref LL_RCC_USB_CLKSOURCE_MSI
02601   * @retval None
02602   */
02603 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
02604 {
02605   LL_RCC_SetCLK48ClockSource(USBxSource);
02606 }
02607
02608 /**
02609   * @brief  Configure RNG clock source
02610   * @note Allow to configure the overall RNG Clock source, if CLK48 is selected as RNG
02611           Clock source, the CLK48xSource has to be configured
02612   * @rmtoll CCIPR        RNGSEL      LL_RCC_ConfigRNGClockSource
02613   * @rmtoll CCIPR        CLK48SEL    LL_RCC_ConfigRNGClockSource
02614   * @param  RNGxSource This parameter can be one of the following values:
02615   *         @arg @ref LL_RCC_RNG_CLKSOURCE_CLK48
02616   *         @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
02617   *         @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
02618   * @param  CLK48xSource This parameter can be one of the following values:
02619   *         @arg @ref LL_RCC_CLK48_CLKSOURCE_HSI48
02620   *         @arg @ref LL_RCC_CLK48_CLKSOURCE_PLLSAI1
02621   *         @arg @ref LL_RCC_CLK48_CLKSOURCE_PLL
02622   *         @arg @ref LL_RCC_CLK48_CLKSOURCE_MSI
02623
02624   * @retval None
02625   */
02626 __STATIC_INLINE void LL_RCC_ConfigRNGClockSource(uint32_t RNGxSource, uint32_t CLK48xSource)
02627 {
02628   if (RNGxSource == LL_RCC_RNG_CLKSOURCE_CLK48)
02629   {
02630     LL_RCC_SetCLK48ClockSource(CLK48xSource);
02631   }
02632   LL_RCC_SetRNGClockSource(RNGxSource);
02633 }
02634
02635
02636 /**
02637   * @brief  Configure ADC clock source
02638   * @rmtoll CCIPR        ADCSEL        LL_RCC_SetADCClockSource
02639   * @param  ADCxSource This parameter can be one of the following values:
02640   *         @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
02641   *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1
02642   *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLL
02643   *         @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
02644   * @retval None
02645   */
02646 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
02647 {
02648   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource);
02649 }
02650
02651 /**
02652   * @brief  Get USARTx clock source
02653   * @rmtoll CCIPR        USART1SEL     LL_RCC_GetUSARTClockSource
02654   * @param  USARTx This parameter can be one of the following values:
02655   *         @arg @ref LL_RCC_USART1_CLKSOURCE
02656   * @retval Returned value can be one of the following values:
02657   *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
02658   *         @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
02659   *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
02660   *         @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
02661   */
02662 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
02663 {
02664   return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx));
02665 }
02666
02667 #if defined(LPUART1)
02668 /**
02669   * @brief  Get LPUARTx clock source
02670   * @rmtoll CCIPR        LPUART1SEL    LL_RCC_GetLPUARTClockSource
02671   * @param  LPUARTx This parameter can be one of the following values:
02672   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE
02673   * @retval Returned value can be one of the following values:
02674   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
02675   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
02676   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
02677   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
02678   */
02679 __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
02680 {
02681   return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx));
02682 }
02683 #endif
02684
02685 /**
02686   * @brief  Get I2Cx clock source
02687   * @rmtoll CCIPR        I2CxSEL       LL_RCC_GetI2CClockSource
02688   * @param  I2Cx This parameter can be one of the following values:
02689   *         @arg @ref LL_RCC_I2C1_CLKSOURCE
02690   *         @arg @ref LL_RCC_I2C3_CLKSOURCE
02691   * @retval Returned value can be one of the following values:
02692   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
02693   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
02694   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
02695   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
02696   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
02697   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
02698   */
02699 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
02700 {
02701   return (uint32_t)((READ_BIT(RCC->CCIPR, I2Cx) >> 4) | (I2Cx << 4));
02702 }
02703
02704 /**
02705   * @brief  Get LPTIMx clock source
02706   * @rmtoll CCIPR        LPTIMxSEL     LL_RCC_GetLPTIMClockSource
02707   * @param  LPTIMx This parameter can be one of the following values:
02708   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
02709   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE
02710   * @retval Returned value can be one of the following values:
02711   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
02712   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
02713   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
02714   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
02715   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
02716   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
02717   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
02718   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
02719   */
02720 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
02721 {
02722   return (uint32_t)((READ_BIT(RCC->CCIPR, LPTIMx) >> 16) | LPTIMx);
02723 }
02724
02725 #if defined(SAI1)
02726 /**
02727   * @brief  Get SAIx clock source
02728   * @rmtoll CCIPR        SAI1SEL       LL_RCC_GetSAIClockSource
02729   * @param  SAIx This parameter can be one of the following values:
02730   *         @arg @ref LL_RCC_SAI1_CLKSOURCE
02731   * @retval Returned value can be one of the following values:
02732   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1
02733   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
02734   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI
02735   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
02736   */
02737 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
02738 {
02739   return (uint32_t)(READ_BIT(RCC->CCIPR, SAIx));
02740 }
02741 #endif
02742
02743 /**
02744   * @brief  Get RNGx clock source
02745   * @rmtoll CCIPR        RNGSEL      LL_RCC_GetRNGClockSource
02746   * @param  RNGx This parameter can be one of the following values:
02747   *         @arg @ref LL_RCC_RNG_CLKSOURCE
02748   * @retval Returned value can be one of the following values:
02749   *         @arg @ref LL_RCC_RNG_CLKSOURCE_CLK48
02750   *         @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
02751   *         @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
02752   */
02753 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
02754 {
02755   return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx));
02756 }
02757
02758 /**
02759   * @brief  Get CLK48x clock source
02760   * @rmtoll CCIPR        CLK48SEL      LL_RCC_GetCLK48ClockSource
02761   * @param  CLK48x This parameter can be one of the following values:
02762   *         @arg @ref LL_RCC_CLK48_CLKSOURCE
02763   * @retval Returned value can be one of the following values:
02764   *         @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
02765   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1
02766   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL
02767   *         @arg @ref LL_RCC_USB_CLKSOURCE_MSI
02768   */
02769 __STATIC_INLINE uint32_t LL_RCC_GetCLK48ClockSource(uint32_t CLK48x)
02770 {
02771   return (uint32_t)(READ_BIT(RCC->CCIPR, CLK48x));
02772 }
02773
02774 /**
02775   * @brief  Get USBx clock source
02776   * @rmtoll CCIPR        CLK48SEL      LL_RCC_GetUSBClockSource
02777   * @param  USBx This parameter can be one of the following values:
02778   *         @arg @ref LL_RCC_USB_CLKSOURCE
02779   * @retval Returned value can be one of the following values:
02780   *         @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
02781   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1
02782   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL
02783   *         @arg @ref LL_RCC_USB_CLKSOURCE_MSI
02784   */
02785 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
02786 {
02787   return LL_RCC_GetCLK48ClockSource(USBx);
02788 }
02789
02790 /**
02791   * @brief  Get ADCx clock source
02792   * @rmtoll CCIPR        ADCSEL        LL_RCC_GetADCClockSource
02793   * @param  ADCx This parameter can be one of the following values:
02794   *         @arg @ref LL_RCC_ADC_CLKSOURCE
02795   * @retval Returned value can be one of the following values:
02796   *         @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
02797   *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1
02798   *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLL
02799   *         @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
02800   */
02801 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
02802 {
02803   return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx));
02804 }
02805
02806 /**
02807   * @}
02808   */
02809
02810 /** @defgroup RCC_LL_EF_RTC RTC
02811   * @{
02812   */
02813
02814 /**
02815   * @brief  Set RTC Clock Source
02816   * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
02817   *       the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
02818   *       set). The BDRST bit can be used to reset them.
02819   * @rmtoll BDCR         RTCSEL        LL_RCC_SetRTCClockSource
02820   * @param  Source This parameter can be one of the following values:
02821   *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
02822   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
02823   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
02824   *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
02825   * @retval None
02826   */
02827 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
02828 {
02829   MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
02830 }
02831
02832 /**
02833   * @brief  Get RTC Clock Source
02834   * @rmtoll BDCR         RTCSEL        LL_RCC_GetRTCClockSource
02835   * @retval Returned value can be one of the following values:
02836   *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
02837   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
02838   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
02839   *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
02840   */
02841 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
02842 {
02843   return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
02844 }
02845
02846 /**
02847   * @brief  Enable RTC
02848   * @rmtoll BDCR         RTCEN         LL_RCC_EnableRTC
02849   * @retval None
02850   */
02851 __STATIC_INLINE void LL_RCC_EnableRTC(void)
02852 {
02853   SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
02854 }
02855
02856 /**
02857   * @brief  Disable RTC
02858   * @rmtoll BDCR         RTCEN         LL_RCC_DisableRTC
02859   * @retval None
02860   */
02861 __STATIC_INLINE void LL_RCC_DisableRTC(void)
02862 {
02863   CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
02864 }
02865
02866 /**
02867   * @brief  Check if RTC has been enabled or not
02868   * @rmtoll BDCR         RTCEN         LL_RCC_IsEnabledRTC
02869   * @retval State of bit (1 or 0).
02870   */
02871 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
02872 {
02873   return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)) ? 1UL : 0UL);
02874 }
02875
02876 /**
02877   * @brief  Force the Backup domain reset
02878   * @rmtoll BDCR         BDRST         LL_RCC_ForceBackupDomainReset
02879   * @retval None
02880   */
02881 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
02882 {
02883   SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
02884 }
02885
02886 /**
02887   * @brief  Release the Backup domain reset
02888   * @rmtoll BDCR         BDRST         LL_RCC_ReleaseBackupDomainReset
02889   * @retval None
02890   */
02891 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
02892 {
02893   CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
02894 }
02895
02896 /**
02897   * @}
02898   */
02899
02900
02901 /** @defgroup RCC_LL_EF_PLL PLL
02902   * @{
02903   */
02904
02905 /**
02906   * @brief  Enable PLL
02907   * @rmtoll CR           PLLON         LL_RCC_PLL_Enable
02908   * @retval None
02909   */
02910 __STATIC_INLINE void LL_RCC_PLL_Enable(void)
02911 {
02912   SET_BIT(RCC->CR, RCC_CR_PLLON);
02913 }
02914
02915 /**
02916   * @brief  Disable PLL
02917   * @note Cannot be disabled if the PLL clock is used as the system clock
02918   * @rmtoll CR           PLLON         LL_RCC_PLL_Disable
02919   * @retval None
02920   */
02921 __STATIC_INLINE void LL_RCC_PLL_Disable(void)
02922 {
02923   CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
02924 }
02925
02926 /**
02927   * @brief  Check if PLL Ready
02928   * @rmtoll CR           PLLRDY        LL_RCC_PLL_IsReady
02929   * @retval State of bit (1 or 0).
02930   */
02931 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
02932 {
02933   return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)) ? 1UL : 0UL);
02934 }
02935
02936 /**
02937   * @brief  Configure PLL used for SYSCLK Domain
02938   * @note PLL Source and PLLM Divider can be written only when PLL is disabled
02939   *       PLLSAI1 are disabled
02940   * @note PLLN/PLLR can be written only when PLL is disabled
02941   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_SYS\n
02942   *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_SYS\n
02943   *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_SYS\n
02944   *         PLLCFGR      PLLR          LL_RCC_PLL_ConfigDomain_SYS
02945   * @param  Source This parameter can be one of the following values:
02946   *         @arg @ref LL_RCC_PLLSOURCE_NONE
02947   *         @arg @ref LL_RCC_PLLSOURCE_MSI
02948   *         @arg @ref LL_RCC_PLLSOURCE_HSI
02949   *         @arg @ref LL_RCC_PLLSOURCE_HSE
02950   * @param  PLLM This parameter can be one of the following values:
02951   *         @arg @ref LL_RCC_PLLM_DIV_1
02952   *         @arg @ref LL_RCC_PLLM_DIV_2
02953   *         @arg @ref LL_RCC_PLLM_DIV_3
02954   *         @arg @ref LL_RCC_PLLM_DIV_4
02955   *         @arg @ref LL_RCC_PLLM_DIV_5
02956   *         @arg @ref LL_RCC_PLLM_DIV_6
02957   *         @arg @ref LL_RCC_PLLM_DIV_7
02958   *         @arg @ref LL_RCC_PLLM_DIV_8
02959   * @param  PLLN Between 6 and 127
02960   * @param  PLLR This parameter can be one of the following values:
02961   *         @arg @ref LL_RCC_PLLR_DIV_2
02962   *         @arg @ref LL_RCC_PLLR_DIV_4
02963   *         @arg @ref LL_RCC_PLLR_DIV_6
02964   *         @arg @ref LL_RCC_PLLR_DIV_8
02965   * @retval None
02966   */
02967 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
02968 {
02969   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
02970              Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR);
02971 }
02972
02973 #if defined(SAI1)
02974 /**
02975   * @brief  Configure PLL used for SAI domain clock
02976   * @note PLL Source and PLLM Divider can be written only when PLL is disabled
02977   *       PLLSAI1 are disabled
02978   * @note PLLN/PLLP can be written only when PLL is disabled
02979   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_SAI\n
02980   *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_SAI\n
02981   *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_SAI\n
02982   *         PLLCFGR      PLLP          LL_RCC_PLL_ConfigDomain_SAI
02983   * @param  Source This parameter can be one of the following values:
02984   *         @arg @ref LL_RCC_PLLSOURCE_NONE
02985   *         @arg @ref LL_RCC_PLLSOURCE_MSI
02986   *         @arg @ref LL_RCC_PLLSOURCE_HSI
02987   *         @arg @ref LL_RCC_PLLSOURCE_HSE
02988   * @param  PLLM This parameter can be one of the following values:
02989   *         @arg @ref LL_RCC_PLLM_DIV_1
02990   *         @arg @ref LL_RCC_PLLM_DIV_2
02991   *         @arg @ref LL_RCC_PLLM_DIV_3
02992   *         @arg @ref LL_RCC_PLLM_DIV_4
02993   *         @arg @ref LL_RCC_PLLM_DIV_5
02994   *         @arg @ref LL_RCC_PLLM_DIV_6
02995   *         @arg @ref LL_RCC_PLLM_DIV_7
02996   *         @arg @ref LL_RCC_PLLM_DIV_8
02997   * @param  PLLN Between 6 and 127
02998   * @param  PLLP This parameter can be one of the following values:
02999   *         @arg @ref LL_RCC_PLLP_DIV_2
03000   *         @arg @ref LL_RCC_PLLP_DIV_3
03001   *         @arg @ref LL_RCC_PLLP_DIV_4
03002   *         @arg @ref LL_RCC_PLLP_DIV_5
03003   *         @arg @ref LL_RCC_PLLP_DIV_6
03004   *         @arg @ref LL_RCC_PLLP_DIV_7
03005   *         @arg @ref LL_RCC_PLLP_DIV_8
03006   *         @arg @ref LL_RCC_PLLP_DIV_9
03007   *         @arg @ref LL_RCC_PLLP_DIV_10
03008   *         @arg @ref LL_RCC_PLLP_DIV_11
03009   *         @arg @ref LL_RCC_PLLP_DIV_12
03010   *         @arg @ref LL_RCC_PLLP_DIV_13
03011   *         @arg @ref LL_RCC_PLLP_DIV_14
03012   *         @arg @ref LL_RCC_PLLP_DIV_15
03013   *         @arg @ref LL_RCC_PLLP_DIV_16
03014   *         @arg @ref LL_RCC_PLLP_DIV_17
03015   *         @arg @ref LL_RCC_PLLP_DIV_18
03016   *         @arg @ref LL_RCC_PLLP_DIV_19
03017   *         @arg @ref LL_RCC_PLLP_DIV_20
03018   *         @arg @ref LL_RCC_PLLP_DIV_21
03019   *         @arg @ref LL_RCC_PLLP_DIV_22
03020   *         @arg @ref LL_RCC_PLLP_DIV_23
03021   *         @arg @ref LL_RCC_PLLP_DIV_24
03022   *         @arg @ref LL_RCC_PLLP_DIV_25
03023   *         @arg @ref LL_RCC_PLLP_DIV_26
03024   *         @arg @ref LL_RCC_PLLP_DIV_27
03025   *         @arg @ref LL_RCC_PLLP_DIV_28
03026   *         @arg @ref LL_RCC_PLLP_DIV_29
03027   *         @arg @ref LL_RCC_PLLP_DIV_30
03028   *         @arg @ref LL_RCC_PLLP_DIV_31
03029   *         @arg @ref LL_RCC_PLLP_DIV_32
03030   * @retval None
03031   */
03032 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
03033 {
03034   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP,
03035              Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
03036 }
03037 #endif
03038
03039 /**
03040   * @brief  Configure PLL used for ADC domain clock
03041   * @note PLL Source and PLLM Divider can be written only when PLL is disabled
03042   *       PLLSAI1 are disabled
03043   * @note PLLN/PLLP can be written only when PLL is disabled
03044   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_ADC\n
03045   *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_ADC\n
03046   *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_ADC\n
03047   *         PLLCFGR      PLLP          LL_RCC_PLL_ConfigDomain_ADC
03048   * @param  Source This parameter can be one of the following values:
03049   *         @arg @ref LL_RCC_PLLSOURCE_NONE
03050   *         @arg @ref LL_RCC_PLLSOURCE_MSI
03051   *         @arg @ref LL_RCC_PLLSOURCE_HSI
03052   *         @arg @ref LL_RCC_PLLSOURCE_HSE
03053   * @param  PLLM This parameter can be one of the following values:
03054   *         @arg @ref LL_RCC_PLLM_DIV_1
03055   *         @arg @ref LL_RCC_PLLM_DIV_2
03056   *         @arg @ref LL_RCC_PLLM_DIV_3
03057   *         @arg @ref LL_RCC_PLLM_DIV_4
03058   *         @arg @ref LL_RCC_PLLM_DIV_5
03059   *         @arg @ref LL_RCC_PLLM_DIV_6
03060   *         @arg @ref LL_RCC_PLLM_DIV_7
03061   *         @arg @ref LL_RCC_PLLM_DIV_8
03062   * @param  PLLN Between 6 and 127
03063   * @param  PLLP This parameter can be one of the following values:
03064   *         @arg @ref LL_RCC_PLLP_DIV_2
03065   *         @arg @ref LL_RCC_PLLP_DIV_3
03066   *         @arg @ref LL_RCC_PLLP_DIV_4
03067   *         @arg @ref LL_RCC_PLLP_DIV_5
03068   *         @arg @ref LL_RCC_PLLP_DIV_6
03069   *         @arg @ref LL_RCC_PLLP_DIV_7
03070   *         @arg @ref LL_RCC_PLLP_DIV_8
03071   *         @arg @ref LL_RCC_PLLP_DIV_9
03072   *         @arg @ref LL_RCC_PLLP_DIV_10
03073   *         @arg @ref LL_RCC_PLLP_DIV_11
03074   *         @arg @ref LL_RCC_PLLP_DIV_12
03075   *         @arg @ref LL_RCC_PLLP_DIV_13
03076   *         @arg @ref LL_RCC_PLLP_DIV_14
03077   *         @arg @ref LL_RCC_PLLP_DIV_15
03078   *         @arg @ref LL_RCC_PLLP_DIV_16
03079   *         @arg @ref LL_RCC_PLLP_DIV_17
03080   *         @arg @ref LL_RCC_PLLP_DIV_18
03081   *         @arg @ref LL_RCC_PLLP_DIV_19
03082   *         @arg @ref LL_RCC_PLLP_DIV_20
03083   *         @arg @ref LL_RCC_PLLP_DIV_21
03084   *         @arg @ref LL_RCC_PLLP_DIV_22
03085   *         @arg @ref LL_RCC_PLLP_DIV_23
03086   *         @arg @ref LL_RCC_PLLP_DIV_24
03087   *         @arg @ref LL_RCC_PLLP_DIV_25
03088   *         @arg @ref LL_RCC_PLLP_DIV_26
03089   *         @arg @ref LL_RCC_PLLP_DIV_27
03090   *         @arg @ref LL_RCC_PLLP_DIV_28
03091   *         @arg @ref LL_RCC_PLLP_DIV_29
03092   *         @arg @ref LL_RCC_PLLP_DIV_30
03093   *         @arg @ref LL_RCC_PLLP_DIV_31
03094   *         @arg @ref LL_RCC_PLLP_DIV_32
03095   * @retval None
03096   */
03097 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
03098 {
03099   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP,
03100              Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
03101 }
03102
03103 /**
03104   * @brief  Configure PLL used for 48Mhz domain clock
03105   * @note PLL Source and PLLM Divider can be written only when PLL is disabled
03106   *       PLLSAI1 are disabled
03107   * @note PLLN/PLLQ can be written only when PLL is disabled
03108   * @note This  can be selected for USB, RNG
03109   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_48M\n
03110   *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_48M\n
03111   *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_48M\n
03112   *         PLLCFGR      PLLQ          LL_RCC_PLL_ConfigDomain_48M
03113   * @param  Source This parameter can be one of the following values:
03114   *         @arg @ref LL_RCC_PLLSOURCE_NONE
03115   *         @arg @ref LL_RCC_PLLSOURCE_MSI
03116   *         @arg @ref LL_RCC_PLLSOURCE_HSI
03117   *         @arg @ref LL_RCC_PLLSOURCE_HSE
03118   * @param  PLLM This parameter can be one of the following values:
03119   *         @arg @ref LL_RCC_PLLM_DIV_1
03120   *         @arg @ref LL_RCC_PLLM_DIV_2
03121   *         @arg @ref LL_RCC_PLLM_DIV_3
03122   *         @arg @ref LL_RCC_PLLM_DIV_4
03123   *         @arg @ref LL_RCC_PLLM_DIV_5
03124   *         @arg @ref LL_RCC_PLLM_DIV_6
03125   *         @arg @ref LL_RCC_PLLM_DIV_7
03126   *         @arg @ref LL_RCC_PLLM_DIV_8
03127   * @param  PLLN Between 6 and 127
03128   * @param  PLLQ This parameter can be one of the following values:
03129   *         @arg @ref LL_RCC_PLLQ_DIV_2
03130   *         @arg @ref LL_RCC_PLLQ_DIV_3
03131   *         @arg @ref LL_RCC_PLLQ_DIV_4
03132   *         @arg @ref LL_RCC_PLLQ_DIV_5
03133   *         @arg @ref LL_RCC_PLLQ_DIV_6
03134   *         @arg @ref LL_RCC_PLLQ_DIV_7
03135   *         @arg @ref LL_RCC_PLLQ_DIV_8
03136   * @retval None
03137   */
03138 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
03139 {
03140   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
03141              Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
03142 }
03143
03144 /**
03145   * @brief  Get Main PLL multiplication factor for VCO
03146   * @rmtoll PLLCFGR      PLLN          LL_RCC_PLL_GetN
03147   * @retval Between 6 and 127
03148   */
03149 __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
03150 {
03151   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >>  RCC_PLLCFGR_PLLN_Pos);
03152 }
03153
03154 /**
03155   * @brief  Get Main PLL division factor for PLLP
03156   * @note   used for PLLSAI1CLK (SAI1 clock)
03157   * @rmtoll PLLCFGR      PLLP       LL_RCC_PLL_GetP
03158   * @retval Returned value can be one of the following values:
03159   *         @arg @ref LL_RCC_PLLP_DIV_2
03160   *         @arg @ref LL_RCC_PLLP_DIV_3
03161   *         @arg @ref LL_RCC_PLLP_DIV_4
03162   *         @arg @ref LL_RCC_PLLP_DIV_5
03163   *         @arg @ref LL_RCC_PLLP_DIV_6
03164   *         @arg @ref LL_RCC_PLLP_DIV_7
03165   *         @arg @ref LL_RCC_PLLP_DIV_8
03166   *         @arg @ref LL_RCC_PLLP_DIV_9
03167   *         @arg @ref LL_RCC_PLLP_DIV_10
03168   *         @arg @ref LL_RCC_PLLP_DIV_11
03169   *         @arg @ref LL_RCC_PLLP_DIV_12
03170   *         @arg @ref LL_RCC_PLLP_DIV_13
03171   *         @arg @ref LL_RCC_PLLP_DIV_14
03172   *         @arg @ref LL_RCC_PLLP_DIV_15
03173   *         @arg @ref LL_RCC_PLLP_DIV_16
03174   *         @arg @ref LL_RCC_PLLP_DIV_17
03175   *         @arg @ref LL_RCC_PLLP_DIV_18
03176   *         @arg @ref LL_RCC_PLLP_DIV_19
03177   *         @arg @ref LL_RCC_PLLP_DIV_20
03178   *         @arg @ref LL_RCC_PLLP_DIV_21
03179   *         @arg @ref LL_RCC_PLLP_DIV_22
03180   *         @arg @ref LL_RCC_PLLP_DIV_23
03181   *         @arg @ref LL_RCC_PLLP_DIV_24
03182   *         @arg @ref LL_RCC_PLLP_DIV_25
03183   *         @arg @ref LL_RCC_PLLP_DIV_26
03184   *         @arg @ref LL_RCC_PLLP_DIV_27
03185   *         @arg @ref LL_RCC_PLLP_DIV_28
03186   *         @arg @ref LL_RCC_PLLP_DIV_29
03187   *         @arg @ref LL_RCC_PLLP_DIV_30
03188   *         @arg @ref LL_RCC_PLLP_DIV_31
03189   *         @arg @ref LL_RCC_PLLP_DIV_32
03190   */
03191 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
03192 {
03193   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
03194 }
03195
03196 /**
03197   * @brief  Get Main PLL division factor for PLLQ
03198   * @note used for PLL48MCLK selected for USB, RNG (48 MHz clock)
03199   * @rmtoll PLLCFGR      PLLQ          LL_RCC_PLL_GetQ
03200   * @retval Returned value can be one of the following values:
03201   *         @arg @ref LL_RCC_PLLQ_DIV_2
03202   *         @arg @ref LL_RCC_PLLQ_DIV_3
03203   *         @arg @ref LL_RCC_PLLQ_DIV_4
03204   *         @arg @ref LL_RCC_PLLQ_DIV_5
03205   *         @arg @ref LL_RCC_PLLQ_DIV_6
03206   *         @arg @ref LL_RCC_PLLQ_DIV_7
03207   *         @arg @ref LL_RCC_PLLQ_DIV_8
03208   */
03209 __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
03210 {
03211   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
03212 }
03213
03214 /**
03215   * @brief  Get Main PLL division factor for PLLR
03216   * @note used for PLLCLK (system clock)
03217   * @rmtoll PLLCFGR      PLLR          LL_RCC_PLL_GetR
03218   * @retval Returned value can be one of the following values:
03219   *         @arg @ref LL_RCC_PLLR_DIV_2
03220   *         @arg @ref LL_RCC_PLLR_DIV_3
03221   *         @arg @ref LL_RCC_PLLR_DIV_4
03222   *         @arg @ref LL_RCC_PLLR_DIV_5
03223   *         @arg @ref LL_RCC_PLLR_DIV_6
03224   *         @arg @ref LL_RCC_PLLR_DIV_7
03225   *         @arg @ref LL_RCC_PLLR_DIV_8
03226   */
03227 __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
03228 {
03229   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
03230 }
03231
03232 /**
03233   * @brief  Get Division factor for the main PLL and other PLL
03234   * @rmtoll PLLCFGR      PLLM          LL_RCC_PLL_GetDivider
03235   * @retval Returned value can be one of the following values:
03236   *         @arg @ref LL_RCC_PLLM_DIV_1
03237   *         @arg @ref LL_RCC_PLLM_DIV_2
03238   *         @arg @ref LL_RCC_PLLM_DIV_3
03239   *         @arg @ref LL_RCC_PLLM_DIV_4
03240   *         @arg @ref LL_RCC_PLLM_DIV_5
03241   *         @arg @ref LL_RCC_PLLM_DIV_6
03242   *         @arg @ref LL_RCC_PLLM_DIV_7
03243   *         @arg @ref LL_RCC_PLLM_DIV_8
03244   */
03245 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
03246 {
03247   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
03248 }
03249
03250 #if defined(SAI1)
03251 /**
03252   * @brief  Enable PLL output mapped on SAI domain clock
03253   * @rmtoll PLLCFGR      PLLPEN        LL_RCC_PLL_EnableDomain_SAI
03254   * @retval None
03255   */
03256 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_SAI(void)
03257 {
03258   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
03259 }
03260
03261 /**
03262   * @brief  Disable PLL output mapped on SAI domain clock
03263   * @note In order to save power, when the PLLCLK  of the PLL is
03264   *       not used,  should be 0
03265   * @rmtoll PLLCFGR      PLLPEN        LL_RCC_PLL_DisableDomain_SAI
03266   * @retval None
03267   */
03268 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SAI(void)
03269 {
03270   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
03271 }
03272 #endif
03273
03274 /**
03275   * @brief  Enable PLL output mapped on ADC domain clock
03276   * @rmtoll PLLCFGR      PLLPEN        LL_RCC_PLL_EnableDomain_ADC
03277   * @retval None
03278   */
03279 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_ADC(void)
03280 {
03281   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
03282 }
03283
03284 /**
03285   * @brief  Disable PLL output mapped on ADC domain clock
03286   * @note In order to save power, when the PLLCLK  of the PLL is
03287   *       not used,  should be 0
03288   * @rmtoll PLLCFGR      PLLPEN        LL_RCC_PLL_DisableDomain_ADC
03289   * @retval None
03290   */
03291 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_ADC(void)
03292 {
03293   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
03294 }
03295
03296
03297 /**
03298   * @brief  Enable PLL output mapped on 48MHz domain clock
03299   * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_EnableDomain_48M
03300   * @retval None
03301   */
03302 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_48M(void)
03303 {
03304   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
03305 }
03306
03307 /**
03308   * @brief  Disable PLL output mapped on 48MHz domain clock
03309   * @note In order to save power, when the PLLCLK  of the PLL is
03310   *       not used,  should be 0
03311   * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_DisableDomain_48M
03312   * @retval None
03313   */
03314 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_48M(void)
03315 {
03316   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
03317 }
03318
03319 /**
03320   * @brief  Enable PLL output mapped on SYSCLK domain
03321   * @rmtoll PLLCFGR      PLLREN        LL_RCC_PLL_EnableDomain_SYS
03322   * @retval None
03323   */
03324 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)
03325 {
03326   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
03327 }
03328
03329 /**
03330   * @brief  Disable PLL output mapped on SYSCLK domain
03331   * @note Cannot be disabled if the PLL clock is used as the system clock
03332   * @note In order to save power, when the PLLCLK  of the PLL is
03333   *       not used, Main PLL  should be 0
03334   * @rmtoll PLLCFGR      PLLREN        LL_RCC_PLL_DisableDomain_SYS
03335   * @retval None
03336   */
03337 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void)
03338 {
03339   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
03340 }
03341
03342 /**
03343   * @}
03344   */
03345
03346 #if defined(SAI1)
03347 /** @defgroup RCC_LL_EF_PLLSAI1 PLLSAI1
03348   * @{
03349   */
03350
03351 /**
03352   * @brief  Enable PLLSAI1
03353   * @rmtoll CR           PLLSAI1ON     LL_RCC_PLLSAI1_Enable
03354   * @retval None
03355   */
03356 __STATIC_INLINE void LL_RCC_PLLSAI1_Enable(void)
03357 {
03358   SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
03359 }
03360
03361 /**
03362   * @brief  Disable PLLSAI1
03363   * @rmtoll CR           PLLSAI1ON     LL_RCC_PLLSAI1_Disable
03364   * @retval None
03365   */
03366 __STATIC_INLINE void LL_RCC_PLLSAI1_Disable(void)
03367 {
03368   CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
03369 }
03370
03371 /**
03372   * @brief  Check if PLLSAI1 Ready
03373   * @rmtoll CR           PLLSAI1RDY    LL_RCC_PLLSAI1_IsReady
03374   * @retval State of bit (1 or 0).
03375   */
03376 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsReady(void)
03377 {
03378   return ((READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY)) ? 1UL : 0UL);
03379 }
03380
03381 /**
03382   * @brief  Configure PLLSAI1 used for 48Mhz domain clock
03383   * @note PLL Source and PLLM Divider can be written only when PLL is disabled
03384   *       PLLSAI1 are disabled
03385   * @note PLLN/PLLQ can be written only when PLLSAI1 is disabled
03386   * @note This  can be selected for USB, RNG
03387   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI1_ConfigDomain_48M\n
03388   *         PLLCFGR      PLLM          LL_RCC_PLLSAI1_ConfigDomain_48M\n
03389   *         PLLSAI1CFGR  PLLN      LL_RCC_PLLSAI1_ConfigDomain_48M\n
03390   *         PLLSAI1CFGR  PLLQ      LL_RCC_PLLSAI1_ConfigDomain_48M
03391   * @param  Source This parameter can be one of the following values:
03392   *         @arg @ref LL_RCC_PLLSOURCE_NONE
03393   *         @arg @ref LL_RCC_PLLSOURCE_MSI
03394   *         @arg @ref LL_RCC_PLLSOURCE_HSI
03395   *         @arg @ref LL_RCC_PLLSOURCE_HSE
03396   * @param  PLLM This parameter can be one of the following values:
03397   *         @arg @ref LL_RCC_PLLM_DIV_1
03398   *         @arg @ref LL_RCC_PLLM_DIV_2
03399   *         @arg @ref LL_RCC_PLLM_DIV_3
03400   *         @arg @ref LL_RCC_PLLM_DIV_4
03401   *         @arg @ref LL_RCC_PLLM_DIV_5
03402   *         @arg @ref LL_RCC_PLLM_DIV_6
03403   *         @arg @ref LL_RCC_PLLM_DIV_7
03404   *         @arg @ref LL_RCC_PLLM_DIV_8
03405   * @param  PLLN Between 6 and 127
03406   * @param  PLLQ This parameter can be one of the following values:
03407   *         @arg @ref LL_RCC_PLLSAI1Q_DIV_2
03408   *         @arg @ref LL_RCC_PLLSAI1Q_DIV_3
03409   *         @arg @ref LL_RCC_PLLSAI1Q_DIV_4
03410   *         @arg @ref LL_RCC_PLLSAI1Q_DIV_5
03411   *         @arg @ref LL_RCC_PLLSAI1Q_DIV_6
03412   *         @arg @ref LL_RCC_PLLSAI1Q_DIV_7
03413   *         @arg @ref LL_RCC_PLLSAI1Q_DIV_8
03414   * @retval None
03415   */
03416 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
03417 {
03418   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
03419   MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLN | RCC_PLLSAI1CFGR_PLLQ, (PLLN << RCC_PLLSAI1CFGR_PLLN_Pos) | PLLQ);
03420 }
03421
03422 /**
03423   * @brief  Configure PLLSAI1 used for SAI domain clock
03424   * @note PLL Source and PLLM Divider can be written only when PLL is disabled
03425   *       PLLSAI1 are disabled
03426   * @note PLLN/PLLP can be written only when PLLSAI1 is disabled
03427   * @note This  can be selected for SAI1 or SAI2 (*)
03428   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI1_ConfigDomain_SAI\n
03429   *         PLLCFGR      PLLM          LL_RCC_PLLSAI1_ConfigDomain_SAI\n
03430   *         PLLSAI1CFGR  PLLN      LL_RCC_PLLSAI1_ConfigDomain_SAI\n
03431   *         PLLSAI1CFGR  PLLP   LL_RCC_PLLSAI1_ConfigDomain_SAI
03432   * @param  Source This parameter can be one of the following values:
03433   *         @arg @ref LL_RCC_PLLSOURCE_NONE
03434   *         @arg @ref LL_RCC_PLLSOURCE_MSI
03435   *         @arg @ref LL_RCC_PLLSOURCE_HSI
03436   *         @arg @ref LL_RCC_PLLSOURCE_HSE
03437   * @param  PLLM This parameter can be one of the following values:
03438   *         @arg @ref LL_RCC_PLLM_DIV_1
03439   *         @arg @ref LL_RCC_PLLM_DIV_2
03440   *         @arg @ref LL_RCC_PLLM_DIV_3
03441   *         @arg @ref LL_RCC_PLLM_DIV_4
03442   *         @arg @ref LL_RCC_PLLM_DIV_5
03443   *         @arg @ref LL_RCC_PLLM_DIV_6
03444   *         @arg @ref LL_RCC_PLLM_DIV_7
03445   *         @arg @ref LL_RCC_PLLM_DIV_8
03446   * @param  PLLN Between 6 and 127
03447   * @param  PLLP This parameter can be one of the following values:
03448   *         @arg @ref LL_RCC_PLLSAI1P_DIV_2
03449   *         @arg @ref LL_RCC_PLLSAI1P_DIV_3
03450   *         @arg @ref LL_RCC_PLLSAI1P_DIV_4
03451   *         @arg @ref LL_RCC_PLLSAI1P_DIV_5
03452   *         @arg @ref LL_RCC_PLLSAI1P_DIV_6
03453   *         @arg @ref LL_RCC_PLLSAI1P_DIV_7
03454   *         @arg @ref LL_RCC_PLLSAI1P_DIV_8
03455   *         @arg @ref LL_RCC_PLLSAI1P_DIV_9
03456   *         @arg @ref LL_RCC_PLLSAI1P_DIV_10
03457   *         @arg @ref LL_RCC_PLLSAI1P_DIV_11
03458   *         @arg @ref LL_RCC_PLLSAI1P_DIV_12
03459   *         @arg @ref LL_RCC_PLLSAI1P_DIV_13
03460   *         @arg @ref LL_RCC_PLLSAI1P_DIV_14
03461   *         @arg @ref LL_RCC_PLLSAI1P_DIV_15
03462   *         @arg @ref LL_RCC_PLLSAI1P_DIV_16
03463   *         @arg @ref LL_RCC_PLLSAI1P_DIV_17
03464   *         @arg @ref LL_RCC_PLLSAI1P_DIV_18
03465   *         @arg @ref LL_RCC_PLLSAI1P_DIV_19
03466   *         @arg @ref LL_RCC_PLLSAI1P_DIV_20
03467   *         @arg @ref LL_RCC_PLLSAI1P_DIV_21
03468   *         @arg @ref LL_RCC_PLLSAI1P_DIV_22
03469   *         @arg @ref LL_RCC_PLLSAI1P_DIV_23
03470   *         @arg @ref LL_RCC_PLLSAI1P_DIV_24
03471   *         @arg @ref LL_RCC_PLLSAI1P_DIV_25
03472   *         @arg @ref LL_RCC_PLLSAI1P_DIV_26
03473   *         @arg @ref LL_RCC_PLLSAI1P_DIV_27
03474   *         @arg @ref LL_RCC_PLLSAI1P_DIV_28
03475   *         @arg @ref LL_RCC_PLLSAI1P_DIV_29
03476   *         @arg @ref LL_RCC_PLLSAI1P_DIV_30
03477   *         @arg @ref LL_RCC_PLLSAI1P_DIV_31
03478   *         @arg @ref LL_RCC_PLLSAI1P_DIV_32
03479   * @retval None
03480   */
03481 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
03482 {
03483   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
03484   MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLN | RCC_PLLSAI1CFGR_PLLP,
03485              (PLLN << RCC_PLLSAI1CFGR_PLLN_Pos) | PLLP);
03486 }
03487
03488 /**
03489   * @brief  Configure PLLSAI1 used for ADC domain clock
03490   * @note PLL Source and PLLM Divider can be written only when PLL is disabled
03491   *       PLLSAI1 are disabled
03492   * @note PLLN/PLLR can be written only when PLLSAI1 is disabled
03493   * @note This  can be selected for ADC
03494   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI1_ConfigDomain_ADC\n
03495   *         PLLCFGR      PLLM          LL_RCC_PLLSAI1_ConfigDomain_ADC\n
03496   *         PLLSAI1CFGR  PLLN      LL_RCC_PLLSAI1_ConfigDomain_ADC\n
03497   *         PLLSAI1CFGR  PLLR      LL_RCC_PLLSAI1_ConfigDomain_ADC
03498   * @param  Source This parameter can be one of the following values:
03499   *         @arg @ref LL_RCC_PLLSOURCE_NONE
03500   *         @arg @ref LL_RCC_PLLSOURCE_MSI
03501   *         @arg @ref LL_RCC_PLLSOURCE_HSI
03502   *         @arg @ref LL_RCC_PLLSOURCE_HSE
03503   * @param  PLLM This parameter can be one of the following values:
03504   *         @arg @ref LL_RCC_PLLM_DIV_1
03505   *         @arg @ref LL_RCC_PLLM_DIV_2
03506   *         @arg @ref LL_RCC_PLLM_DIV_3
03507   *         @arg @ref LL_RCC_PLLM_DIV_4
03508   *         @arg @ref LL_RCC_PLLM_DIV_5
03509   *         @arg @ref LL_RCC_PLLM_DIV_6
03510   *         @arg @ref LL_RCC_PLLM_DIV_7
03511   *         @arg @ref LL_RCC_PLLM_DIV_8
03512   * @param  PLLN Between 6 and 127
03513   * @param  PLLR This parameter can be one of the following values:
03514   *         @arg @ref LL_RCC_PLLSAI1R_DIV_2
03515   *         @arg @ref LL_RCC_PLLSAI1R_DIV_3
03516   *         @arg @ref LL_RCC_PLLSAI1R_DIV_4
03517   *         @arg @ref LL_RCC_PLLSAI1R_DIV_5
03518   *         @arg @ref LL_RCC_PLLSAI1R_DIV_6
03519   *         @arg @ref LL_RCC_PLLSAI1R_DIV_7
03520   *         @arg @ref LL_RCC_PLLSAI1R_DIV_8
03521   * @retval None
03522   */
03523 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
03524 {
03525   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
03526   MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLN | RCC_PLLSAI1CFGR_PLLR, (PLLN << RCC_PLLSAI1CFGR_PLLN_Pos) | PLLR);
03527 }
03528
03529 /**
03530   * @brief  Get SAI1PLL multiplication factor for VCO
03531   * @rmtoll PLLSAI1CFGR  PLLN      LL_RCC_PLLSAI1_GetN
03532   * @retval Between 6 and 127
03533   */
03534 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetN(void)
03535 {
03536   return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLN) >> RCC_PLLSAI1CFGR_PLLN_Pos);
03537 }
03538
03539 /**
03540   * @brief  Get SAI1PLL division factor for PLLSAI1P
03541   * @note used for PLLSAI1CLK (SAI1 or SAI2 (*) clock).
03542   * @rmtoll PLLSAI1CFGR  PLLP      LL_RCC_PLLSAI1_GetP
03543   * @retval Returned value can be one of the following values:
03544   *         @arg @ref LL_RCC_PLLSAI1P_DIV_2
03545   *         @arg @ref LL_RCC_PLLSAI1P_DIV_3
03546   *         @arg @ref LL_RCC_PLLSAI1P_DIV_4
03547   *         @arg @ref LL_RCC_PLLSAI1P_DIV_5
03548   *         @arg @ref LL_RCC_PLLSAI1P_DIV_6
03549   *         @arg @ref LL_RCC_PLLSAI1P_DIV_7
03550   *         @arg @ref LL_RCC_PLLSAI1P_DIV_8
03551   *         @arg @ref LL_RCC_PLLSAI1P_DIV_9
03552   *         @arg @ref LL_RCC_PLLSAI1P_DIV_10
03553   *         @arg @ref LL_RCC_PLLSAI1P_DIV_11
03554   *         @arg @ref LL_RCC_PLLSAI1P_DIV_12
03555   *         @arg @ref LL_RCC_PLLSAI1P_DIV_13
03556   *         @arg @ref LL_RCC_PLLSAI1P_DIV_14
03557   *         @arg @ref LL_RCC_PLLSAI1P_DIV_15
03558   *         @arg @ref LL_RCC_PLLSAI1P_DIV_16
03559   *         @arg @ref LL_RCC_PLLSAI1P_DIV_17
03560   *         @arg @ref LL_RCC_PLLSAI1P_DIV_18
03561   *         @arg @ref LL_RCC_PLLSAI1P_DIV_19
03562   *         @arg @ref LL_RCC_PLLSAI1P_DIV_20
03563   *         @arg @ref LL_RCC_PLLSAI1P_DIV_21
03564   *         @arg @ref LL_RCC_PLLSAI1P_DIV_22
03565   *         @arg @ref LL_RCC_PLLSAI1P_DIV_23
03566   *         @arg @ref LL_RCC_PLLSAI1P_DIV_24
03567   *         @arg @ref LL_RCC_PLLSAI1P_DIV_25
03568   *         @arg @ref LL_RCC_PLLSAI1P_DIV_26
03569   *         @arg @ref LL_RCC_PLLSAI1P_DIV_27
03570   *         @arg @ref LL_RCC_PLLSAI1P_DIV_28
03571   *         @arg @ref LL_RCC_PLLSAI1P_DIV_29
03572   *         @arg @ref LL_RCC_PLLSAI1P_DIV_30
03573   *         @arg @ref LL_RCC_PLLSAI1P_DIV_31
03574   *         @arg @ref LL_RCC_PLLSAI1P_DIV_32
03575   */
03576 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void)
03577 {
03578   return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLP));
03579 }
03580
03581 /**
03582   * @brief  Get SAI1PLL division factor for PLLQ
03583   * @note used PLL48M2CLK selected for USB, RNG (48 MHz clock)
03584   * @rmtoll PLLSAI1CFGR  PLLQ      LL_RCC_PLLSAI1_GetQ
03585   * @retval Returned value can be one of the following values:
03586   *         @arg @ref LL_RCC_PLLSAI1Q_DIV_2
03587   *         @arg @ref LL_RCC_PLLSAI1Q_DIV_3
03588   *         @arg @ref LL_RCC_PLLSAI1Q_DIV_4
03589   *         @arg @ref LL_RCC_PLLSAI1Q_DIV_5
03590   *         @arg @ref LL_RCC_PLLSAI1Q_DIV_6
03591   *         @arg @ref LL_RCC_PLLSAI1Q_DIV_7
03592   *         @arg @ref LL_RCC_PLLSAI1Q_DIV_8
03593   */
03594 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetQ(void)
03595 {
03596   return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLQ));
03597 }
03598
03599 /**
03600   * @brief  Get PLLSAI1 division factor for PLLSAIR
03601   * @note used for PLLADC1CLK (ADC clock)
03602   * @rmtoll PLLSAI1CFGR  PLLR      LL_RCC_PLLSAI1_GetR
03603   * @retval Returned value can be one of the following values:
03604   *         @arg @ref LL_RCC_PLLSAI1R_DIV_2
03605   *         @arg @ref LL_RCC_PLLSAI1R_DIV_3
03606   *         @arg @ref LL_RCC_PLLSAI1R_DIV_4
03607   *         @arg @ref LL_RCC_PLLSAI1R_DIV_5
03608   *         @arg @ref LL_RCC_PLLSAI1R_DIV_6
03609   *         @arg @ref LL_RCC_PLLSAI1R_DIV_7
03610   *         @arg @ref LL_RCC_PLLSAI1R_DIV_8
03611   */
03612 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetR(void)
03613 {
03614   return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLR));
03615 }
03616
03617
03618 /**
03619   * @brief  Enable PLLSAI1 output mapped on SAI domain clock
03620   * @rmtoll PLLSAI1CFGR  PLLPEN    LL_RCC_PLLSAI1_EnableDomain_SAI
03621   * @retval None
03622   */
03623 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_SAI(void)
03624 {
03625   SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLPEN);
03626 }
03627
03628 /**
03629   * @brief  Disable PLLSAI1 output mapped on SAI domain clock
03630   * @note In order to save power, when  of the PLLSAI1 is
03631   *       not used, should be 0
03632   * @rmtoll PLLSAI1CFGR  PLLPEN    LL_RCC_PLLSAI1_DisableDomain_SAI
03633   * @retval None
03634   */
03635 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_SAI(void)
03636 {
03637   CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLPEN);
03638 }
03639
03640 /**
03641   * @brief  Enable PLLSAI1 output mapped on 48MHz domain clock
03642   * @rmtoll PLLSAI1CFGR  PLLQEN    LL_RCC_PLLSAI1_EnableDomain_48M
03643   * @retval None
03644   */
03645 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_48M(void)
03646 {
03647   SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLQEN);
03648 }
03649
03650 /**
03651   * @brief  Disable PLLSAI1 output mapped on 48MHz domain clock
03652   * @note In order to save power, when  of the PLLSAI1 is
03653   *       not used, should be 0
03654   * @rmtoll PLLSAI1CFGR  PLLQEN    LL_RCC_PLLSAI1_DisableDomain_48M
03655   * @retval None
03656   */
03657 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_48M(void)
03658 {
03659   CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLQEN);
03660 }
03661
03662 /**
03663   * @brief  Enable PLLSAI1 output mapped on ADC domain clock
03664   * @rmtoll PLLSAI1CFGR  PLLREN    LL_RCC_PLLSAI1_EnableDomain_ADC
03665   * @retval None
03666   */
03667 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_ADC(void)
03668 {
03669   SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLREN);
03670 }
03671
03672 /**
03673   * @brief  Disable PLLSAI1 output mapped on ADC domain clock
03674   * @note In order to save power, when  of the PLLSAI1 is
03675   *       not used, Main PLLSAI1 should be 0
03676   * @rmtoll PLLSAI1CFGR  PLLREN    LL_RCC_PLLSAI1_DisableDomain_ADC
03677   * @retval None
03678   */
03679 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_ADC(void)
03680 {
03681   CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLREN);
03682 }
03683 #endif
03684
03685 /**
03686   * @}
03687   */
03688
03689
03690
03691 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
03692   * @{
03693   */
03694
03695 /**
03696   * @brief  Clear LSI1 ready interrupt flag
03697   * @rmtoll CICR         LSI1RDYC       LL_RCC_ClearFlag_LSI1RDY
03698   * @retval None
03699   */
03700 __STATIC_INLINE void LL_RCC_ClearFlag_LSI1RDY(void)
03701 {
03702   SET_BIT(RCC->CICR, RCC_CICR_LSI1RDYC);
03703 }
03704
03705 /**
03706   * @brief  Clear LSI2 ready interrupt flag
03707   * @rmtoll CICR         LSI2RDYC       LL_RCC_ClearFlag_LSI2RDY
03708   * @retval None
03709   */
03710 __STATIC_INLINE void LL_RCC_ClearFlag_LSI2RDY(void)
03711 {
03712   SET_BIT(RCC->CICR, RCC_CICR_LSI2RDYC);
03713 }
03714
03715 /**
03716   * @brief  Clear LSE ready interrupt flag
03717   * @rmtoll CICR         LSERDYC       LL_RCC_ClearFlag_LSERDY
03718   * @retval None
03719   */
03720 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
03721 {
03722   SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
03723 }
03724
03725 /**
03726   * @brief  Clear MSI ready interrupt flag
03727   * @rmtoll CICR         MSIRDYC       LL_RCC_ClearFlag_MSIRDY
03728   * @retval None
03729   */
03730 __STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void)
03731 {
03732   SET_BIT(RCC->CICR, RCC_CICR_MSIRDYC);
03733 }
03734
03735 /**
03736   * @brief  Clear HSI ready interrupt flag
03737   * @rmtoll CICR         HSIRDYC       LL_RCC_ClearFlag_HSIRDY
03738   * @retval None
03739   */
03740 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
03741 {
03742   SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
03743 }
03744
03745 /**
03746   * @brief  Clear HSE ready interrupt flag
03747   * @rmtoll CICR         HSERDYC       LL_RCC_ClearFlag_HSERDY
03748   * @retval None
03749   */
03750 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
03751 {
03752   SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
03753 }
03754
03755 /**
03756   * @brief  Configure PLL clock source
03757   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_SetMainSource
03758   * @param PLLSource This parameter can be one of the following values:
03759   *         @arg @ref LL_RCC_PLLSOURCE_MSI
03760   *         @arg @ref LL_RCC_PLLSOURCE_HSI
03761   *         @arg @ref LL_RCC_PLLSOURCE_HSE
03762   * @retval None
03763   */
03764 __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
03765 {
03766   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
03767 }
03768
03769 /**
03770   * @brief  Get the oscillator used as PLL clock source.
03771   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_GetMainSource
03772   * @retval Returned value can be one of the following values:
03773   *         @arg @ref LL_RCC_PLLSOURCE_NONE
03774   *         @arg @ref LL_RCC_PLLSOURCE_MSI
03775   *         @arg @ref LL_RCC_PLLSOURCE_HSI
03776   *         @arg @ref LL_RCC_PLLSOURCE_HSE
03777   */
03778 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
03779 {
03780   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
03781 }
03782
03783 /**
03784   * @brief  Clear PLL ready interrupt flag
03785   * @rmtoll CICR         PLLRDYC       LL_RCC_ClearFlag_PLLRDY
03786   * @retval None
03787   */
03788 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
03789 {
03790   SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
03791 }
03792
03793 /**
03794   * @brief  Clear HSI48 ready interrupt flag
03795   * @rmtoll CICR          HSI48RDYC     LL_RCC_ClearFlag_HSI48RDY
03796   * @retval None
03797   */
03798 __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
03799 {
03800   SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
03801 }
03802
03803 #if defined(SAI1)
03804 /**
03805   * @brief  Clear PLLSAI1 ready interrupt flag
03806   * @rmtoll CICR         PLLSAI1RDYC   LL_RCC_ClearFlag_PLLSAI1RDY
03807   * @retval None
03808   */
03809 __STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI1RDY(void)
03810 {
03811   SET_BIT(RCC->CICR, RCC_CICR_PLLSAI1RDYC);
03812 }
03813 #endif
03814
03815 /**
03816   * @brief  Clear Clock security system interrupt flag
03817   * @rmtoll CICR         CSSC          LL_RCC_ClearFlag_HSECSS
03818   * @retval None
03819   */
03820 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
03821 {
03822   SET_BIT(RCC->CICR, RCC_CICR_CSSC);
03823 }
03824
03825 /**
03826   * @brief  Clear LSE Clock security system interrupt flag
03827   * @rmtoll CICR         LSECSSC       LL_RCC_ClearFlag_LSECSS
03828   * @retval None
03829   */
03830 __STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
03831 {
03832   SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
03833 }
03834
03835 /**
03836   * @brief  Check if LSI1 ready interrupt occurred or not
03837   * @rmtoll CIFR         LSI1RDYF       LL_RCC_IsActiveFlag_LSI1RDY
03838   * @retval State of bit (1 or 0).
03839   */
03840 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSI1RDY(void)
03841 {
03842   return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSI1RDYF) == (RCC_CIFR_LSI1RDYF)) ? 1UL : 0UL);
03843 }
03844
03845 /**
03846   * @brief  Check if LSI2 ready interrupt occurred or not
03847   * @rmtoll CIFR         LSI2RDYF       LL_RCC_IsActiveFlag_LSI2RDY
03848   * @retval State of bit (1 or 0).
03849   */
03850 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSI2RDY(void)
03851 {
03852   return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSI2RDYF) == (RCC_CIFR_LSI2RDYF)) ? 1UL : 0UL);
03853 }
03854
03855 /**
03856   * @brief  Check if LSE ready interrupt occurred or not
03857   * @rmtoll CIFR         LSERDYF       LL_RCC_IsActiveFlag_LSERDY
03858   * @retval State of bit (1 or 0).
03859   */
03860 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
03861 {
03862   return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)) ? 1UL : 0UL);
03863 }
03864
03865 /**
03866   * @brief  Check if MSI ready interrupt occurred or not
03867   * @rmtoll CIFR         MSIRDYF       LL_RCC_IsActiveFlag_MSIRDY
03868   * @retval State of bit (1 or 0).
03869   */
03870 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void)
03871 {
03872   return ((READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == (RCC_CIFR_MSIRDYF)) ? 1UL : 0UL);
03873 }
03874
03875 /**
03876   * @brief  Check if HSI ready interrupt occurred or not
03877   * @rmtoll CIFR         HSIRDYF       LL_RCC_IsActiveFlag_HSIRDY
03878   * @retval State of bit (1 or 0).
03879   */
03880 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
03881 {
03882   return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)) ? 1UL : 0UL);
03883 }
03884
03885 /**
03886   * @brief  Check if HSE ready interrupt occurred or not
03887   * @rmtoll CIFR         HSERDYF       LL_RCC_IsActiveFlag_HSERDY
03888   * @retval State of bit (1 or 0).
03889   */
03890 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
03891 {
03892   return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)) ? 1UL : 0UL);
03893 }
03894
03895 /**
03896   * @brief  Check if PLL ready interrupt occurred or not
03897   * @rmtoll CIFR         PLLRDYF       LL_RCC_IsActiveFlag_PLLRDY
03898   * @retval State of bit (1 or 0).
03899   */
03900 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
03901 {
03902   return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF)) ? 1UL : 0UL);
03903 }
03904
03905 /**
03906   * @brief  Check if HSI48 ready interrupt occurred or not
03907   * @rmtoll CIFR          HSI48RDYF     LL_RCC_IsActiveFlag_HSI48RDY
03908   * @retval State of bit (1 or 0).
03909   */
03910 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
03911 {
03912   return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF)) ? 1UL : 0UL);
03913 }
03914
03915 #if defined(SAI1)
03916 /**
03917   * @brief  Check if PLLSAI1 ready interrupt occurred or not
03918   * @rmtoll CIFR         PLLSAI1RDYF   LL_RCC_IsActiveFlag_PLLSAI1RDY
03919   * @retval State of bit (1 or 0).
03920   */
03921 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI1RDY(void)
03922 {
03923   return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == (RCC_CIFR_PLLSAI1RDYF)) ? 1UL : 0UL);
03924 }
03925 #endif
03926
03927 /**
03928   * @brief  Check if Clock security system interrupt occurred or not
03929   * @rmtoll CIFR         CSSF          LL_RCC_IsActiveFlag_HSECSS
03930   * @retval State of bit (1 or 0).
03931   */
03932 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
03933 {
03934   return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF)) ? 1UL : 0UL);
03935 }
03936
03937 /**
03938   * @brief  Check if LSE Clock security system interrupt occurred or not
03939   * @rmtoll CIFR         LSECSSF       LL_RCC_IsActiveFlag_LSECSS
03940   * @retval State of bit (1 or 0).
03941   */
03942 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
03943 {
03944   return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF)) ? 1UL : 0UL);
03945 }
03946
03947 /**
03948   * @brief  Check if HCLK1 prescaler flag value has been applied or not
03949   * @rmtoll CFGR         HPREF       LL_RCC_IsActiveFlag_HPRE
03950   * @retval State of bit (1 or 0).
03951   */
03952 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HPRE(void)
03953 {
03954   return ((READ_BIT(RCC->CFGR, RCC_CFGR_HPREF) == (RCC_CFGR_HPREF)) ? 1UL : 0UL);
03955 }
03956
03957 /**
03958   * @brief  Check if HCLK2 prescaler flag value has been applied or not
03959   * @rmtoll EXTCFGR         C2HPREF       LL_RCC_IsActiveFlag_C2HPRE
03960   * @retval State of bit (1 or 0).
03961   */
03962 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_C2HPRE(void)
03963 {
03964   return ((READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_C2HPREF) == (RCC_EXTCFGR_C2HPREF)) ? 1UL : 0UL);
03965 }
03966
03967 /**
03968   * @brief  Check if HCLK4 prescaler flag value has been applied or not
03969   * @rmtoll EXTCFGR         SHDHPREF       LL_RCC_IsActiveFlag_SHDHPRE
03970   * @retval State of bit (1 or 0).
03971   */
03972 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SHDHPRE(void)
03973 {
03974   return ((READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPREF) == (RCC_EXTCFGR_SHDHPREF)) ? 1UL : 0UL);
03975 }
03976
03977
03978 /**
03979   * @brief  Check if PLCK1 prescaler flag value has been applied or not
03980   * @rmtoll CFGR         PPRE1F       LL_RCC_IsActiveFlag_PPRE1
03981   * @retval State of bit (1 or 0).
03982   */
03983 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PPRE1(void)
03984 {
03985   return ((READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1F) == (RCC_CFGR_PPRE1F)) ? 1UL : 0UL);
03986 }
03987
03988 /**
03989   * @brief  Check if PLCK2 prescaler flag value has been applied or not
03990   * @rmtoll CFGR         PPRE2F       LL_RCC_IsActiveFlag_PPRE2
03991   * @retval State of bit (1 or 0).
03992   */
03993 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PPRE2(void)
03994 {
03995   return ((READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2F) == (RCC_CFGR_PPRE2F)) ? 1UL : 0UL);
03996 }
03997
03998 /**
03999   * @brief  Check if RCC flag Independent Watchdog reset is set or not.
04000   * @rmtoll CSR          IWDGRSTF      LL_RCC_IsActiveFlag_IWDGRST
04001   * @retval State of bit (1 or 0).
04002   */
04003 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
04004 {
04005   return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)) ? 1UL : 0UL);
04006 }
04007
04008 /**
04009   * @brief  Check if RCC flag Low Power reset is set or not.
04010   * @rmtoll CSR          LPWRRSTF      LL_RCC_IsActiveFlag_LPWRRST
04011   * @retval State of bit (1 or 0).
04012   */
04013 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
04014 {
04015   return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)) ? 1UL : 0UL);
04016 }
04017
04018 /**
04019   * @brief  Check if RCC flag Option byte reset is set or not.
04020   * @rmtoll CSR          OBLRSTF       LL_RCC_IsActiveFlag_OBLRST
04021   * @retval State of bit (1 or 0).
04022   */
04023 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
04024 {
04025   return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)) ? 1UL : 0UL);
04026 }
04027
04028 /**
04029   * @brief  Check if RCC flag Pin reset is set or not.
04030   * @rmtoll CSR          PINRSTF       LL_RCC_IsActiveFlag_PINRST
04031   * @retval State of bit (1 or 0).
04032   */
04033 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
04034 {
04035   return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)) ? 1UL : 0UL);
04036 }
04037
04038 /**
04039   * @brief  Check if RCC flag Software reset is set or not.
04040   * @rmtoll CSR          SFTRSTF       LL_RCC_IsActiveFlag_SFTRST
04041   * @retval State of bit (1 or 0).
04042   */
04043 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
04044 {
04045   return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)) ? 1UL : 0UL);
04046 }
04047
04048 /**
04049   * @brief  Check if RCC flag Window Watchdog reset is set or not.
04050   * @rmtoll CSR          WWDGRSTF      LL_RCC_IsActiveFlag_WWDGRST
04051   * @retval State of bit (1 or 0).
04052   */
04053 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
04054 {
04055   return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)) ? 1UL : 0UL);
04056 }
04057
04058 /**
04059   * @brief  Check if RCC flag BOR reset is set or not.
04060   * @rmtoll CSR          BORRSTF       LL_RCC_IsActiveFlag_BORRST
04061   * @retval State of bit (1 or 0).
04062   */
04063 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
04064 {
04065   return ((READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF)) ? 1UL : 0UL);
04066 }
04067
04068 /**
04069   * @brief  Set RMVF bit to clear the reset flags.
04070   * @rmtoll CSR          RMVF          LL_RCC_ClearResetFlags
04071   * @retval None
04072   */
04073 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
04074 {
04075   SET_BIT(RCC->CSR, RCC_CSR_RMVF);
04076 }
04077
04078 /**
04079   * @}
04080   */
04081
04082 /** @defgroup RCC_LL_EF_IT_Management IT Management
04083   * @{
04084   */
04085
04086 /**
04087   * @brief  Enable LSI1 ready interrupt
04088   * @rmtoll CIER         LSI1RDYIE      LL_RCC_EnableIT_LSI1RDY
04089   * @retval None
04090   */
04091 __STATIC_INLINE void LL_RCC_EnableIT_LSI1RDY(void)
04092 {
04093   SET_BIT(RCC->CIER, RCC_CIER_LSI1RDYIE);
04094 }
04095
04096 /**
04097   * @brief  Enable LSI2 ready interrupt
04098   * @rmtoll CIER         LSI2RDYIE      LL_RCC_EnableIT_LSI2RDY
04099   * @retval None
04100   */
04101 __STATIC_INLINE void LL_RCC_EnableIT_LSI2RDY(void)
04102 {
04103   SET_BIT(RCC->CIER, RCC_CIER_LSI2RDYIE);
04104 }
04105 /**
04106   * @brief  Enable LSE ready interrupt
04107   * @rmtoll CIER         LSERDYIE      LL_RCC_EnableIT_LSERDY
04108   * @retval None
04109   */
04110 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
04111 {
04112   SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
04113 }
04114
04115 /**
04116   * @brief  Enable MSI ready interrupt
04117   * @rmtoll CIER         MSIRDYIE      LL_RCC_EnableIT_MSIRDY
04118   * @retval None
04119   */
04120 __STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void)
04121 {
04122   SET_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
04123 }
04124
04125 /**
04126   * @brief  Enable HSI ready interrupt
04127   * @rmtoll CIER         HSIRDYIE      LL_RCC_EnableIT_HSIRDY
04128   * @retval None
04129   */
04130 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
04131 {
04132   SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
04133 }
04134
04135 /**
04136   * @brief  Enable HSE ready interrupt
04137   * @rmtoll CIER         HSERDYIE      LL_RCC_EnableIT_HSERDY
04138   * @retval None
04139   */
04140 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
04141 {
04142   SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
04143 }
04144
04145 /**
04146   * @brief  Enable PLL ready interrupt
04147   * @rmtoll CIER         PLLRDYIE      LL_RCC_EnableIT_PLLRDY
04148   * @retval None
04149   */
04150 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
04151 {
04152   SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
04153 }
04154
04155 /**
04156   * @brief  Enable HSI48 ready interrupt
04157   * @rmtoll CIER          HSI48RDYIE    LL_RCC_EnableIT_HSI48RDY
04158   * @retval None
04159   */
04160 __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
04161 {
04162   SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
04163 }
04164
04165 #if defined(SAI1)
04166 /**
04167   * @brief  Enable PLLSAI1 ready interrupt
04168   * @rmtoll CIER         PLLSAI1RDYIE  LL_RCC_EnableIT_PLLSAI1RDY
04169   * @retval None
04170   */
04171 __STATIC_INLINE void LL_RCC_EnableIT_PLLSAI1RDY(void)
04172 {
04173   SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);
04174 }
04175 #endif
04176
04177 /**
04178   * @brief  Enable LSE clock security system interrupt
04179   * @rmtoll CIER         LSECSSIE      LL_RCC_EnableIT_LSECSS
04180   * @retval None
04181   */
04182 __STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
04183 {
04184   SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
04185 }
04186
04187 /**
04188   * @brief  Disable LSI1 ready interrupt
04189   * @rmtoll CIER         LSI1RDYIE      LL_RCC_DisableIT_LSI1RDY
04190   * @retval None
04191   */
04192 __STATIC_INLINE void LL_RCC_DisableIT_LSI1RDY(void)
04193 {
04194   CLEAR_BIT(RCC->CIER, RCC_CIER_LSI1RDYIE);
04195 }
04196
04197 /**
04198   * @brief  Disable LSI2 ready interrupt
04199   * @rmtoll CIER         LSI2RDYIE      LL_RCC_DisableIT_LSI2RDY
04200   * @retval None
04201   */
04202 __STATIC_INLINE void LL_RCC_DisableIT_LSI2RDY(void)
04203 {
04204   CLEAR_BIT(RCC->CIER, RCC_CIER_LSI2RDYIE);
04205 }
04206 /**
04207   * @brief  Disable LSE ready interrupt
04208   * @rmtoll CIER         LSERDYIE      LL_RCC_DisableIT_LSERDY
04209   * @retval None
04210   */
04211 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
04212 {
04213   CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
04214 }
04215
04216 /**
04217   * @brief  Disable MSI ready interrupt
04218   * @rmtoll CIER         MSIRDYIE      LL_RCC_DisableIT_MSIRDY
04219   * @retval None
04220   */
04221 __STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void)
04222 {
04223   CLEAR_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
04224 }
04225
04226 /**
04227   * @brief  Disable HSI ready interrupt
04228   * @rmtoll CIER         HSIRDYIE      LL_RCC_DisableIT_HSIRDY
04229   * @retval None
04230   */
04231 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
04232 {
04233   CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
04234 }
04235
04236 /**
04237   * @brief  Disable HSE ready interrupt
04238   * @rmtoll CIER         HSERDYIE      LL_RCC_DisableIT_HSERDY
04239   * @retval None
04240   */
04241 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
04242 {
04243   CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
04244 }
04245
04246 /**
04247   * @brief  Disable PLL ready interrupt
04248   * @rmtoll CIER         PLLRDYIE      LL_RCC_DisableIT_PLLRDY
04249   * @retval None
04250   */
04251 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
04252 {
04253   CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
04254 }
04255
04256 /**
04257   * @brief  Disable HSI48 ready interrupt
04258   * @rmtoll CIER          HSI48RDYIE    LL_RCC_DisableIT_HSI48RDY
04259   * @retval None
04260   */
04261 __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
04262 {
04263   CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
04264 }
04265
04266 #if defined(SAI1)
04267 /**
04268   * @brief  Disable PLLSAI1 ready interrupt
04269   * @rmtoll CIER         PLLSAI1RDYIE  LL_RCC_DisableIT_PLLSAI1RDY
04270   * @retval None
04271   */
04272 __STATIC_INLINE void LL_RCC_DisableIT_PLLSAI1RDY(void)
04273 {
04274   CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);
04275 }
04276 #endif
04277
04278 /**
04279   * @brief  Disable LSE clock security system interrupt
04280   * @rmtoll CIER         LSECSSIE      LL_RCC_DisableIT_LSECSS
04281   * @retval None
04282   */
04283 __STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
04284 {
04285   CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
04286 }
04287
04288 /**
04289   * @brief  Checks if LSI1 ready interrupt source is enabled or disabled.
04290   * @rmtoll CIER         LSI1RDYIE      LL_RCC_IsEnabledIT_LSI1RDY
04291   * @retval State of bit (1 or 0).
04292   */
04293 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSI1RDY(void)
04294 {
04295   return ((READ_BIT(RCC->CIER, RCC_CIER_LSI1RDYIE) == (RCC_CIER_LSI1RDYIE)) ? 1UL : 0UL);
04296 }
04297
04298 /**
04299   * @brief  Checks if LSI2 ready interrupt source is enabled or disabled.
04300   * @rmtoll CIER         LSI2RDYIE      LL_RCC_IsEnabledIT_LSI2RDY
04301   * @retval State of bit (1 or 0).
04302   */
04303 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSI2RDY(void)
04304 {
04305   return ((READ_BIT(RCC->CIER, RCC_CIER_LSI2RDYIE) == (RCC_CIER_LSI2RDYIE)) ? 1UL : 0UL);
04306 }
04307 /**
04308   * @brief  Checks if LSE ready interrupt source is enabled or disabled.
04309   * @rmtoll CIER         LSERDYIE      LL_RCC_IsEnabledIT_LSERDY
04310   * @retval State of bit (1 or 0).
04311   */
04312 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
04313 {
04314   return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE)) ? 1UL : 0UL);
04315 }
04316
04317 /**
04318   * @brief  Checks if MSI ready interrupt source is enabled or disabled.
04319   * @rmtoll CIER         MSIRDYIE      LL_RCC_IsEnabledIT_MSIRDY
04320   * @retval State of bit (1 or 0).
04321   */
04322 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void)
04323 {
04324   return ((READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == (RCC_CIER_MSIRDYIE)) ? 1UL : 0UL);
04325 }
04326
04327 /**
04328   * @brief  Checks if HSI ready interrupt source is enabled or disabled.
04329   * @rmtoll CIER         HSIRDYIE      LL_RCC_IsEnabledIT_HSIRDY
04330   * @retval State of bit (1 or 0).
04331   */
04332 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
04333 {
04334   return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE)) ? 1UL : 0UL);
04335 }
04336
04337 /**
04338   * @brief  Checks if HSE ready interrupt source is enabled or disabled.
04339   * @rmtoll CIER         HSERDYIE      LL_RCC_IsEnabledIT_HSERDY
04340   * @retval State of bit (1 or 0).
04341   */
04342 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
04343 {
04344   return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE)) ? 1UL : 0UL);
04345 }
04346
04347 /**
04348   * @brief  Checks if PLL ready interrupt source is enabled or disabled.
04349   * @rmtoll CIER         PLLRDYIE      LL_RCC_IsEnabledIT_PLLRDY
04350   * @retval State of bit (1 or 0).
04351   */
04352 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
04353 {
04354   return ((READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE)) ? 1UL : 0UL);
04355 }
04356
04357 /**
04358   * @brief  Checks if HSI48 ready interrupt source is enabled or disabled.
04359   * @rmtoll CIER          HSI48RDYIE    LL_RCC_IsEnabledIT_HSI48RDY
04360   * @retval State of bit (1 or 0).
04361   */
04362 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
04363 {
04364   return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == (RCC_CIER_HSI48RDYIE)) ? 1UL : 0UL);
04365 }
04366
04367 #if defined(SAI1)
04368 /**
04369   * @brief  Checks if PLLSAI1 ready interrupt source is enabled or disabled.
04370   * @rmtoll CIER         PLLSAI1RDYIE  LL_RCC_IsEnabledIT_PLLSAI1RDY
04371   * @retval State of bit (1 or 0).
04372   */
04373 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI1RDY(void)
04374 {
04375   return ((READ_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) == (RCC_CIER_PLLSAI1RDYIE)) ? 1UL : 0UL);
04376 }
04377 #endif
04378
04379 /**
04380   * @brief  Checks if LSECSS interrupt source is enabled or disabled.
04381   * @rmtoll CIER         LSECSSIE      LL_RCC_IsEnabledIT_LSECSS
04382   * @retval State of bit (1 or 0).
04383   */
04384 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
04385 {
04386   return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == (RCC_CIER_LSECSSIE)) ? 1UL : 0UL);
04387 }
04388
04389 /**
04390   * @}
04391   */
04392
04393 #if defined(USE_FULL_LL_DRIVER)
04394 /** @defgroup RCC_LL_EF_Init De-initialization function
04395   * @{
04396   */
04397 ErrorStatus LL_RCC_DeInit(void);
04398 /**
04399   * @}
04400   */
04401
04402 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
04403   * @{
04404   */
04405 void        LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
04406 uint32_t    LL_RCC_GetSMPSClockFreq(void);
04407 uint32_t    LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
04408 uint32_t    LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
04409 #if defined(LPUART1)
04410 uint32_t    LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
04411 #endif
04412 uint32_t    LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
04413 #if defined(SAI1)
04414 uint32_t    LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
04415 #endif
04416 uint32_t    LL_RCC_GetCLK48ClockFreq(uint32_t CLK48xSource);
04417 uint32_t    LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
04418 uint32_t    LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
04419 uint32_t    LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
04420 uint32_t    LL_RCC_GetRTCClockFreq(void);
04421 uint32_t    LL_RCC_GetRFWKPClockFreq(void);
04422 /**
04423   * @}
04424   */
04425 #endif /* USE_FULL_LL_DRIVER */
04426
04427 /**
04428   * @}
04429   */
04430
04431 /**
04432   * @}
04433   */
04434
04435 #endif /* defined(RCC) */
04436
04437 /**
04438   * @}
04439   */
04440
04441 #ifdef __cplusplus
04442 }
04443 #endif
04444
04445 #endif /* STM32WBxx_LL_RCC_H */
04446
04447 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_rng.c Source File

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stm32wbxx_ll_rng.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_rng.c
00004   * @author  MCD Application Team
00005   * @brief   RNG LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32wbxx_ll_rng.h"
00023 #include "stm32wbxx_ll_bus.h"
00024
00025 #ifdef  USE_FULL_ASSERT
00026 #include "stm32_assert.h"
00027 #else
00028 #define assert_param(expr) ((void)0U)
00029 #endif
00030
00031 /** @addtogroup STM32WBxx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (RNG)
00036
00037 /** @addtogroup RNG_LL
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /* Private macros ------------------------------------------------------------*/
00045 /** @addtogroup RNG_LL_Private_Macros
00046   * @{
00047   */
00048 #define IS_LL_RNG_CED(__MODE__) (((__MODE__) == LL_RNG_CED_ENABLE) || \
00049                                  ((__MODE__) == LL_RNG_CED_DISABLE))
00050
00051 /**
00052   * @}
00053   */
00054 /* Private function prototypes -----------------------------------------------*/
00055
00056 /* Exported functions --------------------------------------------------------*/
00057 /** @addtogroup RNG_LL_Exported_Functions
00058   * @{
00059   */
00060
00061 /** @addtogroup RNG_LL_EF_Init
00062   * @{
00063   */
00064
00065 /**
00066   * @brief  De-initialize RNG registers (Registers restored to their default values).
00067   * @param  RNGx RNG Instance
00068   * @retval An ErrorStatus enumeration value:
00069   *          - SUCCESS: RNG registers are de-initialized
00070   *          - ERROR: not applicable
00071   */
00072 ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx)
00073 {
00074   /* Check the parameters */
00075   assert_param(IS_RNG_ALL_INSTANCE(RNGx));
00076   /* Enable RNG reset state */
00077   LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_RNG);
00078
00079   /* Release RNG from reset state */
00080   LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_RNG);
00081   return (SUCCESS);
00082 }
00083
00084 /**
00085   * @brief  Initialize RNG registers according to the specified parameters in RNG_InitStruct.
00086   * @param  RNGx RNG Instance
00087   * @param  RNG_InitStruct pointer to a LL_RNG_InitTypeDef structure
00088   *         that contains the configuration information for the specified RNG peripheral.
00089   * @retval An ErrorStatus enumeration value:
00090   *          - SUCCESS: RNG registers are initialized according to RNG_InitStruct content
00091   *          - ERROR: not applicable
00092   */
00093 ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct)
00094 {
00095   /* Check the parameters */
00096   assert_param(IS_RNG_ALL_INSTANCE(RNGx));
00097   assert_param(IS_LL_RNG_CED(RNG_InitStruct->ClockErrorDetection));
00098
00099   /* Clock Error Detection configuration */
00100   MODIFY_REG(RNGx->CR, RNG_CR_CED, RNG_InitStruct->ClockErrorDetection);
00101
00102   return (SUCCESS);
00103 }
00104
00105 /**
00106   * @brief Set each @ref LL_RNG_InitTypeDef field to default value.
00107   * @param RNG_InitStruct pointer to a @ref LL_RNG_InitTypeDef structure
00108   *                       whose fields will be set to default values.
00109   * @retval None
00110   */
00111 void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct)
00112 {
00113   /* Set RNG_InitStruct fields to default values */
00114   RNG_InitStruct->ClockErrorDetection = LL_RNG_CED_ENABLE;
00115
00116 }
00117 /**
00118   * @}
00119   */
00120
00121 /**
00122   * @}
00123   */
00124
00125 /**
00126   * @}
00127   */
00128
00129 #endif /* RNG */
00130
00131 /**
00132   * @}
00133   */
00134
00135 #endif /* USE_FULL_LL_DRIVER */
00136
00137 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00138
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_rng.h Source File

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stm32wbxx_ll_rng.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_rng.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of RNG LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_LL_RNG_H
00022 #define STM32WBxx_LL_RNG_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx.h"
00030
00031 /** @addtogroup STM32WBxx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (RNG)
00036
00037 /** @defgroup RNG_LL RNG
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /* Private macros ------------------------------------------------------------*/
00045
00046 /* Exported types ------------------------------------------------------------*/
00047 #if defined(USE_FULL_LL_DRIVER)
00048 /** @defgroup RNG_LL_ES_Init_Struct RNG Exported Init structures
00049   * @{
00050   */
00051
00052
00053 /**
00054   * @brief LL RNG Init Structure Definition
00055   */
00056 typedef struct
00057 {
00058   uint32_t         ClockErrorDetection; /*!< Clock error detection.
00059                                       This parameter can be one value of @ref RNG_LL_CED.
00060
00061                                       This parameter can be modified using unitary functions @ref LL_RNG_EnableClkErrorDetect(). */
00062 } LL_RNG_InitTypeDef;
00063
00064 /**
00065   * @}
00066   */
00067 #endif /* USE_FULL_LL_DRIVER */
00068 /* Exported constants --------------------------------------------------------*/
00069 /** @defgroup RNG_LL_Exported_Constants RNG Exported Constants
00070   * @{
00071   */
00072
00073 /** @defgroup RNG_LL_CED Clock Error Detection
00074   * @{
00075   */
00076 #define LL_RNG_CED_ENABLE         0x00000000U              /*!< Clock error detection enabled  */
00077 #define LL_RNG_CED_DISABLE        RNG_CR_CED               /*!< Clock error detection disabled */
00078 /**
00079   * @}
00080   */
00081
00082 /** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines
00083   * @brief    Flags defines which can be used with LL_RNG_ReadReg function
00084   * @{
00085   */
00086 #define LL_RNG_SR_DRDY RNG_SR_DRDY    /*!< Register contains valid random data */
00087 #define LL_RNG_SR_CECS RNG_SR_CECS    /*!< Clock error current status */
00088 #define LL_RNG_SR_SECS RNG_SR_SECS    /*!< Seed error current status */
00089 #define LL_RNG_SR_CEIS RNG_SR_CEIS    /*!< Clock error interrupt status */
00090 #define LL_RNG_SR_SEIS RNG_SR_SEIS    /*!< Seed error interrupt status */
00091 /**
00092   * @}
00093   */
00094
00095 /** @defgroup RNG_LL_EC_IT IT Defines
00096   * @brief    IT defines which can be used with LL_RNG_ReadReg and  LL_RNG_WriteReg macros
00097   * @{
00098   */
00099 #define LL_RNG_CR_IE   RNG_CR_IE      /*!< RNG Interrupt enable */
00100 /**
00101   * @}
00102   */
00103
00104 /**
00105   * @}
00106   */
00107
00108 /* Exported macro ------------------------------------------------------------*/
00109 /** @defgroup RNG_LL_Exported_Macros RNG Exported Macros
00110   * @{
00111   */
00112
00113 /** @defgroup RNG_LL_EM_WRITE_READ Common Write and read registers Macros
00114   * @{
00115   */
00116
00117 /**
00118   * @brief  Write a value in RNG register
00119   * @param  __INSTANCE__ RNG Instance
00120   * @param  __REG__ Register to be written
00121   * @param  __VALUE__ Value to be written in the register
00122   * @retval None
00123   */
00124 #define LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00125
00126 /**
00127   * @brief  Read a value in RNG register
00128   * @param  __INSTANCE__ RNG Instance
00129   * @param  __REG__ Register to be read
00130   * @retval Register value
00131   */
00132 #define LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00133 /**
00134   * @}
00135   */
00136
00137 /**
00138   * @}
00139   */
00140
00141
00142 /* Exported functions --------------------------------------------------------*/
00143 /** @defgroup RNG_LL_Exported_Functions RNG Exported Functions
00144   * @{
00145   */
00146 /** @defgroup RNG_LL_EF_Configuration RNG Configuration functions
00147   * @{
00148   */
00149
00150 /**
00151   * @brief  Enable Random Number Generation
00152   * @rmtoll CR           RNGEN         LL_RNG_Enable
00153   * @param  RNGx RNG Instance
00154   * @retval None
00155   */
00156 __STATIC_INLINE void LL_RNG_Enable(RNG_TypeDef *RNGx)
00157 {
00158   SET_BIT(RNGx->CR, RNG_CR_RNGEN);
00159 }
00160
00161 /**
00162   * @brief  Disable Random Number Generation
00163   * @rmtoll CR           RNGEN         LL_RNG_Disable
00164   * @param  RNGx RNG Instance
00165   * @retval None
00166   */
00167 __STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx)
00168 {
00169   CLEAR_BIT(RNGx->CR, RNG_CR_RNGEN);
00170 }
00171
00172 /**
00173   * @brief  Check if Random Number Generator is enabled
00174   * @rmtoll CR           RNGEN         LL_RNG_IsEnabled
00175   * @param  RNGx RNG Instance
00176   * @retval State of bit (1 or 0).
00177   */
00178 __STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx)
00179 {
00180   return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL);
00181 }
00182
00183 /**
00184   * @brief  Enable Clock Error Detection
00185   * @rmtoll CR           CED           LL_RNG_EnableClkErrorDetect
00186   * @param  RNGx RNG Instance
00187   * @retval None
00188   */
00189 __STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx)
00190 {
00191   CLEAR_BIT(RNGx->CR, RNG_CR_CED);
00192 }
00193
00194 /**
00195   * @brief  Disable RNG Clock Error Detection
00196   * @rmtoll CR           CED         LL_RNG_DisableClkErrorDetect
00197   * @param  RNGx RNG Instance
00198   * @retval None
00199   */
00200 __STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx)
00201 {
00202   SET_BIT(RNGx->CR, RNG_CR_CED);
00203 }
00204
00205 /**
00206   * @brief  Check if RNG Clock Error Detection is enabled
00207   * @rmtoll CR           CED         LL_RNG_IsEnabledClkErrorDetect
00208   * @param  RNGx RNG Instance
00209   * @retval State of bit (1 or 0).
00210   */
00211 __STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(RNG_TypeDef *RNGx)
00212 {
00213   return ((READ_BIT(RNGx->CR, RNG_CR_CED) != (RNG_CR_CED)) ? 1UL : 0UL);
00214 }
00215
00216 /**
00217   * @}
00218   */
00219
00220 /** @defgroup RNG_LL_EF_FLAG_Management FLAG Management
00221   * @{
00222   */
00223
00224 /**
00225   * @brief  Indicate if the RNG Data ready Flag is set or not
00226   * @rmtoll SR           DRDY          LL_RNG_IsActiveFlag_DRDY
00227   * @param  RNGx RNG Instance
00228   * @retval State of bit (1 or 0).
00229   */
00230 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx)
00231 {
00232   return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL);
00233 }
00234
00235 /**
00236   * @brief  Indicate if the Clock Error Current Status Flag is set or not
00237   * @rmtoll SR           CECS          LL_RNG_IsActiveFlag_CECS
00238   * @param  RNGx RNG Instance
00239   * @retval State of bit (1 or 0).
00240   */
00241 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx)
00242 {
00243   return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL);
00244 }
00245
00246 /**
00247   * @brief  Indicate if the Seed Error Current Status Flag is set or not
00248   * @rmtoll SR           SECS          LL_RNG_IsActiveFlag_SECS
00249   * @param  RNGx RNG Instance
00250   * @retval State of bit (1 or 0).
00251   */
00252 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx)
00253 {
00254   return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL);
00255 }
00256
00257 /**
00258   * @brief  Indicate if the Clock Error Interrupt Status Flag is set or not
00259   * @rmtoll SR           CEIS          LL_RNG_IsActiveFlag_CEIS
00260   * @param  RNGx RNG Instance
00261   * @retval State of bit (1 or 0).
00262   */
00263 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx)
00264 {
00265   return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL);
00266 }
00267
00268 /**
00269   * @brief  Indicate if the Seed Error Interrupt Status Flag is set or not
00270   * @rmtoll SR           SEIS          LL_RNG_IsActiveFlag_SEIS
00271   * @param  RNGx RNG Instance
00272   * @retval State of bit (1 or 0).
00273   */
00274 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef *RNGx)
00275 {
00276   return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL);
00277 }
00278
00279 /**
00280   * @brief  Clear Clock Error interrupt Status (CEIS) Flag
00281   * @rmtoll SR           CEIS          LL_RNG_ClearFlag_CEIS
00282   * @param  RNGx RNG Instance
00283   * @retval None
00284   */
00285 __STATIC_INLINE void LL_RNG_ClearFlag_CEIS(RNG_TypeDef *RNGx)
00286 {
00287   WRITE_REG(RNGx->SR, ~RNG_SR_CEIS);
00288 }
00289
00290 /**
00291   * @brief  Clear Seed Error interrupt Status (SEIS) Flag
00292   * @rmtoll SR           SEIS          LL_RNG_ClearFlag_SEIS
00293   * @param  RNGx RNG Instance
00294   * @retval None
00295   */
00296 __STATIC_INLINE void LL_RNG_ClearFlag_SEIS(RNG_TypeDef *RNGx)
00297 {
00298   WRITE_REG(RNGx->SR, ~RNG_SR_SEIS);
00299 }
00300
00301 /**
00302   * @}
00303   */
00304
00305 /** @defgroup RNG_LL_EF_IT_Management IT Management
00306   * @{
00307   */
00308
00309 /**
00310   * @brief  Enable Random Number Generator Interrupt
00311   *         (applies for either Seed error, Clock Error or Data ready interrupts)
00312   * @rmtoll CR           IE            LL_RNG_EnableIT
00313   * @param  RNGx RNG Instance
00314   * @retval None
00315   */
00316 __STATIC_INLINE void LL_RNG_EnableIT(RNG_TypeDef *RNGx)
00317 {
00318   SET_BIT(RNGx->CR, RNG_CR_IE);
00319 }
00320
00321 /**
00322   * @brief  Disable Random Number Generator Interrupt
00323   *         (applies for either Seed error, Clock Error or Data ready interrupts)
00324   * @rmtoll CR           IE            LL_RNG_DisableIT
00325   * @param  RNGx RNG Instance
00326   * @retval None
00327   */
00328 __STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx)
00329 {
00330   CLEAR_BIT(RNGx->CR, RNG_CR_IE);
00331 }
00332
00333 /**
00334   * @brief  Check if Random Number Generator Interrupt is enabled
00335   *         (applies for either Seed error, Clock Error or Data ready interrupts)
00336   * @rmtoll CR           IE            LL_RNG_IsEnabledIT
00337   * @param  RNGx RNG Instance
00338   * @retval State of bit (1 or 0).
00339   */
00340 __STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx)
00341 {
00342   return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL);
00343 }
00344
00345 /**
00346   * @}
00347   */
00348
00349 /** @defgroup RNG_LL_EF_Data_Management Data Management
00350   * @{
00351   */
00352
00353 /**
00354   * @brief  Return32-bit Random Number value
00355   * @rmtoll DR           RNDATA        LL_RNG_ReadRandData32
00356   * @param  RNGx RNG Instance
00357   * @retval Generated 32-bit random value
00358   */
00359 __STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx)
00360 {
00361   return (uint32_t)(READ_REG(RNGx->DR));
00362 }
00363
00364 /**
00365   * @}
00366   */
00367
00368 #if defined(USE_FULL_LL_DRIVER)
00369 /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions
00370   * @{
00371   */
00372 ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct);
00373 void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct);
00374 ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx);
00375
00376 /**
00377   * @}
00378   */
00379 #endif /* USE_FULL_LL_DRIVER */
00380
00381 /**
00382   * @}
00383   */
00384
00385 /**
00386   * @}
00387   */
00388
00389 #endif /* RNG */
00390
00391 /**
00392   * @}
00393   */
00394
00395 #ifdef __cplusplus
00396 }
00397 #endif
00398
00399 #endif /* __STM32WBxx_LL_RNG_H */
00400
00401 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_rtc.c Source File

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stm32wbxx_ll_rtc.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_rtc.c
00004   * @author  MCD Application Team
00005   * @brief   RTC LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32wbxx_ll_rtc.h"
00023 #include "stm32wbxx_ll_cortex.h"
00024 #ifdef  USE_FULL_ASSERT
00025 #include "stm32_assert.h"
00026 #else
00027 #define assert_param(expr) ((void)0U)
00028 #endif
00029
00030 /** @addtogroup STM32WBxx_LL_Driver
00031   * @{
00032   */
00033
00034 #if defined(RTC)
00035
00036 /** @addtogroup RTC_LL
00037   * @{
00038   */
00039
00040 /* Private types -------------------------------------------------------------*/
00041 /* Private variables ---------------------------------------------------------*/
00042 /* Private constants ---------------------------------------------------------*/
00043 /** @addtogroup RTC_LL_Private_Constants
00044   * @{
00045   */
00046 /* Default values used for prescaler */
00047 #define RTC_ASYNCH_PRESC_DEFAULT     0x0000007FU
00048 #define RTC_SYNCH_PRESC_DEFAULT      0x000000FFU
00049
00050 /* Values used for timeout */
00051 #define RTC_INITMODE_TIMEOUT         1000U /* 1s when tick set to 1ms */
00052 #define RTC_SYNCHRO_TIMEOUT          1000U /* 1s when tick set to 1ms */
00053 /**
00054   * @}
00055   */
00056
00057 /* Private macros ------------------------------------------------------------*/
00058 /** @addtogroup RTC_LL_Private_Macros
00059   * @{
00060   */
00061
00062 #define IS_LL_RTC_HOURFORMAT(__VALUE__) (((__VALUE__) == LL_RTC_HOURFORMAT_24HOUR) \
00063                                       || ((__VALUE__) == LL_RTC_HOURFORMAT_AMPM))
00064
00065 #define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__)   ((__VALUE__) <= 0x7FU)
00066
00067 #define IS_LL_RTC_SYNCH_PREDIV(__VALUE__)    ((__VALUE__) <= 0x7FFFU)
00068
00069 #define IS_LL_RTC_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_FORMAT_BIN) \
00070                                   || ((__VALUE__) == LL_RTC_FORMAT_BCD))
00071
00072 #define IS_LL_RTC_TIME_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_TIME_FORMAT_AM_OR_24) \
00073                                        || ((__VALUE__) == LL_RTC_TIME_FORMAT_PM))
00074
00075 #define IS_LL_RTC_HOUR12(__HOUR__)            (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))
00076 #define IS_LL_RTC_HOUR24(__HOUR__)            ((__HOUR__) <= 23U)
00077 #define IS_LL_RTC_MINUTES(__MINUTES__)        ((__MINUTES__) <= 59U)
00078 #define IS_LL_RTC_SECONDS(__SECONDS__)        ((__SECONDS__) <= 59U)
00079
00080 #define IS_LL_RTC_WEEKDAY(__VALUE__) (((__VALUE__) == LL_RTC_WEEKDAY_MONDAY) \
00081                                    || ((__VALUE__) == LL_RTC_WEEKDAY_TUESDAY) \
00082                                    || ((__VALUE__) == LL_RTC_WEEKDAY_WEDNESDAY) \
00083                                    || ((__VALUE__) == LL_RTC_WEEKDAY_THURSDAY) \
00084                                    || ((__VALUE__) == LL_RTC_WEEKDAY_FRIDAY) \
00085                                    || ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \
00086                                    || ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY))
00087
00088 #define IS_LL_RTC_DAY(__DAY__)    (((__DAY__) >= 1U) && ((__DAY__) <= 31U))
00089
00090 #define IS_LL_RTC_MONTH(__VALUE__) (((__VALUE__) == LL_RTC_MONTH_JANUARY) \
00091                                  || ((__VALUE__) == LL_RTC_MONTH_FEBRUARY) \
00092                                  || ((__VALUE__) == LL_RTC_MONTH_MARCH) \
00093                                  || ((__VALUE__) == LL_RTC_MONTH_APRIL) \
00094                                  || ((__VALUE__) == LL_RTC_MONTH_MAY) \
00095                                  || ((__VALUE__) == LL_RTC_MONTH_JUNE) \
00096                                  || ((__VALUE__) == LL_RTC_MONTH_JULY) \
00097                                  || ((__VALUE__) == LL_RTC_MONTH_AUGUST) \
00098                                  || ((__VALUE__) == LL_RTC_MONTH_SEPTEMBER) \
00099                                  || ((__VALUE__) == LL_RTC_MONTH_OCTOBER) \
00100                                  || ((__VALUE__) == LL_RTC_MONTH_NOVEMBER) \
00101                                  || ((__VALUE__) == LL_RTC_MONTH_DECEMBER))
00102
00103 #define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
00104
00105 #define IS_LL_RTC_ALMA_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMA_MASK_NONE) \
00106                                      || ((__VALUE__) == LL_RTC_ALMA_MASK_DATEWEEKDAY) \
00107                                      || ((__VALUE__) == LL_RTC_ALMA_MASK_HOURS) \
00108                                      || ((__VALUE__) == LL_RTC_ALMA_MASK_MINUTES) \
00109                                      || ((__VALUE__) == LL_RTC_ALMA_MASK_SECONDS) \
00110                                      || ((__VALUE__) == LL_RTC_ALMA_MASK_ALL))
00111
00112 #define IS_LL_RTC_ALMB_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMB_MASK_NONE) \
00113                                      || ((__VALUE__) == LL_RTC_ALMB_MASK_DATEWEEKDAY) \
00114                                      || ((__VALUE__) == LL_RTC_ALMB_MASK_HOURS) \
00115                                      || ((__VALUE__) == LL_RTC_ALMB_MASK_MINUTES) \
00116                                      || ((__VALUE__) == LL_RTC_ALMB_MASK_SECONDS) \
00117                                      || ((__VALUE__) == LL_RTC_ALMB_MASK_ALL))
00118
00119
00120 #define IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) || \
00121                                                   ((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY))
00122
00123 #define IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) || \
00124                                                   ((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY))
00125
00126
00127 /**
00128   * @}
00129   */
00130 /* Private function prototypes -----------------------------------------------*/
00131 /* Exported functions --------------------------------------------------------*/
00132 /** @addtogroup RTC_LL_Exported_Functions
00133   * @{
00134   */
00135
00136 /** @addtogroup RTC_LL_EF_Init
00137   * @{
00138   */
00139
00140 /**
00141   * @brief  De-Initializes the RTC registers to their default reset values.
00142   * @note   This function doesn't reset the RTC Clock source and RTC Backup Data
00143   *         registers.
00144   * @param  RTCx RTC Instance
00145   * @retval An ErrorStatus enumeration value:
00146   *          - SUCCESS: RTC registers are de-initialized
00147   *          - ERROR: RTC registers are not de-initialized
00148   */
00149 ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx)
00150 {
00151   ErrorStatus status = ERROR;
00152
00153   /* Check the parameter */
00154   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00155
00156   /* Disable the write protection for RTC registers */
00157   LL_RTC_DisableWriteProtection(RTCx);
00158
00159   /* Set Initialization mode */
00160   if (LL_RTC_EnterInitMode(RTCx) != ERROR)
00161   {
00162     /* Reset TR, DR and CR registers */
00163     WRITE_REG(RTCx->TR,       0x00000000U);
00164 #if defined(RTC_WAKEUP_SUPPORT)
00165     WRITE_REG(RTCx->WUTR,     RTC_WUTR_WUT);
00166 #endif /* RTC_WAKEUP_SUPPORT */
00167     WRITE_REG(RTCx->DR  ,     (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
00168     /* Reset All CR bits except CR[2:0] */
00169 #if defined(RTC_WAKEUP_SUPPORT)
00170     WRITE_REG(RTCx->CR, (READ_REG(RTCx->CR) & RTC_CR_WUCKSEL));
00171 #else
00172     WRITE_REG(RTCx, CR, 0x00000000U);
00173 #endif /* RTC_WAKEUP_SUPPORT */
00174     WRITE_REG(RTCx->PRER,     (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT));
00175     WRITE_REG(RTCx->ALRMAR,   0x00000000U);
00176     WRITE_REG(RTCx->ALRMBR,   0x00000000U);
00177     WRITE_REG(RTCx->SHIFTR,   0x00000000U);
00178     WRITE_REG(RTCx->CALR,     0x00000000U);
00179     WRITE_REG(RTCx->ALRMASSR, 0x00000000U);
00180     WRITE_REG(RTCx->ALRMBSSR, 0x00000000U);
00181
00182     /* Reset ISR register and exit initialization mode */
00183     WRITE_REG(RTCx->ISR,      0x00000000U);
00184
00185     /* Reset Tamper and alternate functions configuration register */
00186     WRITE_REG(RTCx->TAMPCR, 0x00000000U);
00187
00188     /* Reset Option register */
00189     WRITE_REG(RTCx->OR, 0x00000000U);
00190
00191     /* Wait till the RTC RSF flag is set */
00192     status = LL_RTC_WaitForSynchro(RTCx);
00193   }
00194
00195   /* Enable the write protection for RTC registers */
00196   LL_RTC_EnableWriteProtection(RTCx);
00197
00198   return status;
00199 }
00200
00201 /**
00202   * @brief  Initializes the RTC registers according to the specified parameters
00203   *         in RTC_InitStruct.
00204   * @param  RTCx RTC Instance
00205   * @param  RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure that contains
00206   *         the configuration information for the RTC peripheral.
00207   * @note   The RTC Prescaler register is write protected and can be written in
00208   *         initialization mode only.
00209   * @retval An ErrorStatus enumeration value:
00210   *          - SUCCESS: RTC registers are initialized
00211   *          - ERROR: RTC registers are not initialized
00212   */
00213 ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
00214 {
00215   ErrorStatus status = ERROR;
00216
00217   /* Check the parameters */
00218   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00219   assert_param(IS_LL_RTC_HOURFORMAT(RTC_InitStruct->HourFormat));
00220   assert_param(IS_LL_RTC_ASYNCH_PREDIV(RTC_InitStruct->AsynchPrescaler));
00221   assert_param(IS_LL_RTC_SYNCH_PREDIV(RTC_InitStruct->SynchPrescaler));
00222
00223   /* Disable the write protection for RTC registers */
00224   LL_RTC_DisableWriteProtection(RTCx);
00225
00226   /* Set Initialization mode */
00227   if (LL_RTC_EnterInitMode(RTCx) != ERROR)
00228   {
00229     /* Set Hour Format */
00230     LL_RTC_SetHourFormat(RTCx, RTC_InitStruct->HourFormat);
00231
00232     /* Configure Synchronous and Asynchronous prescaler factor */
00233     LL_RTC_SetSynchPrescaler(RTCx, RTC_InitStruct->SynchPrescaler);
00234     LL_RTC_SetAsynchPrescaler(RTCx, RTC_InitStruct->AsynchPrescaler);
00235
00236     /* Exit Initialization mode */
00237     LL_RTC_DisableInitMode(RTCx);
00238
00239     status = SUCCESS;
00240   }
00241   /* Enable the write protection for RTC registers */
00242   LL_RTC_EnableWriteProtection(RTCx);
00243
00244   return status;
00245 }
00246
00247 /**
00248   * @brief  Set each @ref LL_RTC_InitTypeDef field to default value.
00249   * @param  RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure which will be initialized.
00250   * @retval None
00251   */
00252 void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct)
00253 {
00254   /* Set RTC_InitStruct fields to default values */
00255   RTC_InitStruct->HourFormat      = LL_RTC_HOURFORMAT_24HOUR;
00256   RTC_InitStruct->AsynchPrescaler = RTC_ASYNCH_PRESC_DEFAULT;
00257   RTC_InitStruct->SynchPrescaler  = RTC_SYNCH_PRESC_DEFAULT;
00258 }
00259
00260 /**
00261   * @brief  Set the RTC current time.
00262   * @param  RTCx RTC Instance
00263   * @param  RTC_Format This parameter can be one of the following values:
00264   *         @arg @ref LL_RTC_FORMAT_BIN
00265   *         @arg @ref LL_RTC_FORMAT_BCD
00266   * @param  RTC_TimeStruct pointer to a RTC_TimeTypeDef structure that contains
00267   *                        the time configuration information for the RTC.
00268   * @retval An ErrorStatus enumeration value:
00269   *          - SUCCESS: RTC Time register is configured
00270   *          - ERROR: RTC Time register is not configured
00271   */
00272 ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
00273 {
00274   ErrorStatus status = ERROR;
00275
00276   /* Check the parameters */
00277   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00278   assert_param(IS_LL_RTC_FORMAT(RTC_Format));
00279
00280   if (RTC_Format == LL_RTC_FORMAT_BIN)
00281   {
00282     if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
00283     {
00284       assert_param(IS_LL_RTC_HOUR12(RTC_TimeStruct->Hours));
00285       assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
00286     }
00287     else
00288     {
00289       RTC_TimeStruct->TimeFormat = 0x00U;
00290       assert_param(IS_LL_RTC_HOUR24(RTC_TimeStruct->Hours));
00291     }
00292     assert_param(IS_LL_RTC_MINUTES(RTC_TimeStruct->Minutes));
00293     assert_param(IS_LL_RTC_SECONDS(RTC_TimeStruct->Seconds));
00294   }
00295   else
00296   {
00297     if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
00298     {
00299       assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
00300       assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
00301     }
00302     else
00303     {
00304       RTC_TimeStruct->TimeFormat = 0x00U;
00305       assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
00306     }
00307     assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes)));
00308     assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds)));
00309   }
00310
00311   /* Disable the write protection for RTC registers */
00312   LL_RTC_DisableWriteProtection(RTCx);
00313
00314   /* Set Initialization mode */
00315   if (LL_RTC_EnterInitMode(RTCx) != ERROR)
00316   {
00317     /* Check the input parameters format */
00318     if (RTC_Format != LL_RTC_FORMAT_BIN)
00319     {
00320       LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, RTC_TimeStruct->Hours,
00321                          RTC_TimeStruct->Minutes, RTC_TimeStruct->Seconds);
00322     }
00323     else
00324     {
00325       LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Hours),
00326                          __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Minutes),
00327                          __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Seconds));
00328     }
00329
00330     /* Exit Initialization mode */
00331     LL_RTC_DisableInitMode(RTC);
00332
00333     /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
00334     if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
00335     {
00336       status = LL_RTC_WaitForSynchro(RTCx);
00337     }
00338     else
00339     {
00340       status = SUCCESS;
00341     }
00342   }
00343   /* Enable the write protection for RTC registers */
00344   LL_RTC_EnableWriteProtection(RTCx);
00345
00346   return status;
00347 }
00348
00349 /**
00350   * @brief  Set each @ref LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
00351   * @param  RTC_TimeStruct pointer to a @ref LL_RTC_TimeTypeDef structure which will be initialized.
00352   * @retval None
00353   */
00354 void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct)
00355 {
00356   /* Time = 00h:00min:00sec */
00357   RTC_TimeStruct->TimeFormat = LL_RTC_TIME_FORMAT_AM_OR_24;
00358   RTC_TimeStruct->Hours      = 0U;
00359   RTC_TimeStruct->Minutes    = 0U;
00360   RTC_TimeStruct->Seconds    = 0U;
00361 }
00362
00363 /**
00364   * @brief  Set the RTC current date.
00365   * @param  RTCx RTC Instance
00366   * @param  RTC_Format This parameter can be one of the following values:
00367   *         @arg @ref LL_RTC_FORMAT_BIN
00368   *         @arg @ref LL_RTC_FORMAT_BCD
00369   * @param RTC_DateStruct pointer to a RTC_DateTypeDef structure that contains
00370   *                         the date configuration information for the RTC.
00371   * @retval An ErrorStatus enumeration value:
00372   *          - SUCCESS: RTC Day register is configured
00373   *          - ERROR: RTC Day register is not configured
00374   */
00375 ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct)
00376 {
00377   ErrorStatus status = ERROR;
00378
00379   /* Check the parameters */
00380   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00381   assert_param(IS_LL_RTC_FORMAT(RTC_Format));
00382
00383   if ((RTC_Format == LL_RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10U) == 0x10U))
00384   {
00385     RTC_DateStruct->Month = (RTC_DateStruct->Month & (uint8_t)~(0x10U)) + 0x0AU;
00386   }
00387   if (RTC_Format == LL_RTC_FORMAT_BIN)
00388   {
00389     assert_param(IS_LL_RTC_YEAR(RTC_DateStruct->Year));
00390     assert_param(IS_LL_RTC_MONTH(RTC_DateStruct->Month));
00391     assert_param(IS_LL_RTC_DAY(RTC_DateStruct->Day));
00392   }
00393   else
00394   {
00395     assert_param(IS_LL_RTC_YEAR(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Year)));
00396     assert_param(IS_LL_RTC_MONTH(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Month)));
00397     assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Day)));
00398   }
00399   assert_param(IS_LL_RTC_WEEKDAY(RTC_DateStruct->WeekDay));
00400
00401   /* Disable the write protection for RTC registers */
00402   LL_RTC_DisableWriteProtection(RTCx);
00403
00404   /* Set Initialization mode */
00405   if (LL_RTC_EnterInitMode(RTCx) != ERROR)
00406   {
00407     /* Check the input parameters format */
00408     if (RTC_Format != LL_RTC_FORMAT_BIN)
00409     {
00410       LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, RTC_DateStruct->Day, RTC_DateStruct->Month, RTC_DateStruct->Year);
00411     }
00412     else
00413     {
00414       LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Day),
00415                          __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Month), __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Year));
00416     }
00417
00418     /* Exit Initialization mode */
00419     LL_RTC_DisableInitMode(RTC);
00420
00421     /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
00422     if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
00423     {
00424       status = LL_RTC_WaitForSynchro(RTCx);
00425     }
00426     else
00427     {
00428       status = SUCCESS;
00429     }
00430   }
00431   /* Enable the write protection for RTC registers */
00432   LL_RTC_EnableWriteProtection(RTCx);
00433
00434   return status;
00435 }
00436
00437 /**
00438   * @brief  Set each @ref LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)
00439   * @param  RTC_DateStruct pointer to a @ref LL_RTC_DateTypeDef structure which will be initialized.
00440   * @retval None
00441   */
00442 void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct)
00443 {
00444   /* Monday, January 01 xx00 */
00445   RTC_DateStruct->WeekDay = LL_RTC_WEEKDAY_MONDAY;
00446   RTC_DateStruct->Day     = 1U;
00447   RTC_DateStruct->Month   = LL_RTC_MONTH_JANUARY;
00448   RTC_DateStruct->Year    = 0U;
00449 }
00450
00451 /**
00452   * @brief  Set the RTC Alarm A.
00453   * @note   The Alarm register can only be written when the corresponding Alarm
00454   *         is disabled (Use @ref LL_RTC_ALMA_Disable function).
00455   * @param  RTCx RTC Instance
00456   * @param  RTC_Format This parameter can be one of the following values:
00457   *         @arg @ref LL_RTC_FORMAT_BIN
00458   *         @arg @ref LL_RTC_FORMAT_BCD
00459   * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
00460   *                         contains the alarm configuration parameters.
00461   * @retval An ErrorStatus enumeration value:
00462   *          - SUCCESS: ALARMA registers are configured
00463   *          - ERROR: ALARMA registers are not configured
00464   */
00465 ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
00466 {
00467   /* Check the parameters */
00468   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00469   assert_param(IS_LL_RTC_FORMAT(RTC_Format));
00470   assert_param(IS_LL_RTC_ALMA_MASK(RTC_AlarmStruct->AlarmMask));
00471   assert_param(IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel));
00472
00473   if (RTC_Format == LL_RTC_FORMAT_BIN)
00474   {
00475     if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
00476     {
00477       assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours));
00478       assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
00479     }
00480     else
00481     {
00482       RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
00483       assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
00484     }
00485     assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
00486     assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
00487
00488     if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
00489     {
00490       assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay));
00491     }
00492     else
00493     {
00494       assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay));
00495     }
00496   }
00497   else
00498   {
00499     if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
00500     {
00501       assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
00502       assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
00503     }
00504     else
00505     {
00506       RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
00507       assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
00508     }
00509
00510     assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
00511     assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
00512
00513     if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
00514     {
00515       assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
00516     }
00517     else
00518     {
00519       assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
00520     }
00521   }
00522
00523   /* Disable the write protection for RTC registers */
00524   LL_RTC_DisableWriteProtection(RTCx);
00525
00526   /* Select weekday selection */
00527   if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
00528   {
00529     /* Set the date for ALARM */
00530     LL_RTC_ALMA_DisableWeekday(RTCx);
00531     if (RTC_Format != LL_RTC_FORMAT_BIN)
00532     {
00533       LL_RTC_ALMA_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
00534     }
00535     else
00536     {
00537       LL_RTC_ALMA_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay));
00538     }
00539   }
00540   else
00541   {
00542     /* Set the week day for ALARM */
00543     LL_RTC_ALMA_EnableWeekday(RTCx);
00544     LL_RTC_ALMA_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
00545   }
00546
00547   /* Configure the Alarm register */
00548   if (RTC_Format != LL_RTC_FORMAT_BIN)
00549   {
00550     LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours,
00551                            RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds);
00552   }
00553   else
00554   {
00555     LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat,
00556                            __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours),
00557                            __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes),
00558                            __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds));
00559   }
00560   /* Set ALARM mask */
00561   LL_RTC_ALMA_SetMask(RTCx, RTC_AlarmStruct->AlarmMask);
00562
00563   /* Enable the write protection for RTC registers */
00564   LL_RTC_EnableWriteProtection(RTCx);
00565
00566   return SUCCESS;
00567 }
00568
00569 /**
00570   * @brief  Set the RTC Alarm B.
00571   * @note   The Alarm register can only be written when the corresponding Alarm
00572   *         is disabled (@ref LL_RTC_ALMB_Disable function).
00573   * @param  RTCx RTC Instance
00574   * @param  RTC_Format This parameter can be one of the following values:
00575   *         @arg @ref LL_RTC_FORMAT_BIN
00576   *         @arg @ref LL_RTC_FORMAT_BCD
00577   * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
00578   *                         contains the alarm configuration parameters.
00579   * @retval An ErrorStatus enumeration value:
00580   *          - SUCCESS: ALARMB registers are configured
00581   *          - ERROR: ALARMB registers are not configured
00582   */
00583 ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
00584 {
00585   /* Check the parameters */
00586   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00587   assert_param(IS_LL_RTC_FORMAT(RTC_Format));
00588   assert_param(IS_LL_RTC_ALMB_MASK(RTC_AlarmStruct->AlarmMask));
00589   assert_param(IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel));
00590
00591   if (RTC_Format == LL_RTC_FORMAT_BIN)
00592   {
00593     if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
00594     {
00595       assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours));
00596       assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
00597     }
00598     else
00599     {
00600       RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
00601       assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
00602     }
00603     assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
00604     assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
00605
00606     if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
00607     {
00608       assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay));
00609     }
00610     else
00611     {
00612       assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay));
00613     }
00614   }
00615   else
00616   {
00617     if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
00618     {
00619       assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
00620       assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
00621     }
00622     else
00623     {
00624       RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
00625       assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
00626     }
00627
00628     assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
00629     assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
00630
00631     if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
00632     {
00633       assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
00634     }
00635     else
00636     {
00637       assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
00638     }
00639   }
00640
00641   /* Disable the write protection for RTC registers */
00642   LL_RTC_DisableWriteProtection(RTCx);
00643
00644   /* Select weekday selection */
00645   if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
00646   {
00647     /* Set the date for ALARM */
00648     LL_RTC_ALMB_DisableWeekday(RTCx);
00649     if (RTC_Format != LL_RTC_FORMAT_BIN)
00650     {
00651       LL_RTC_ALMB_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
00652     }
00653     else
00654     {
00655       LL_RTC_ALMB_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay));
00656     }
00657   }
00658   else
00659   {
00660     /* Set the week day for ALARM */
00661     LL_RTC_ALMB_EnableWeekday(RTCx);
00662     LL_RTC_ALMB_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
00663   }
00664
00665   /* Configure the Alarm register */
00666   if (RTC_Format != LL_RTC_FORMAT_BIN)
00667   {
00668     LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours,
00669                            RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds);
00670   }
00671   else
00672   {
00673     LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat,
00674                            __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours),
00675                            __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes),
00676                            __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds));
00677   }
00678   /* Set ALARM mask */
00679   LL_RTC_ALMB_SetMask(RTCx, RTC_AlarmStruct->AlarmMask);
00680
00681   /* Enable the write protection for RTC registers */
00682   LL_RTC_EnableWriteProtection(RTCx);
00683
00684   return SUCCESS;
00685 }
00686
00687 /**
00688   * @brief  Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec /
00689   *         Day = 1st day of the month/Mask = all fields are masked).
00690   * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
00691   * @retval None
00692   */
00693 void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
00694 {
00695   /* Alarm Time Settings : Time = 00h:00mn:00sec */
00696   RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMA_TIME_FORMAT_AM;
00697   RTC_AlarmStruct->AlarmTime.Hours      = 0U;
00698   RTC_AlarmStruct->AlarmTime.Minutes    = 0U;
00699   RTC_AlarmStruct->AlarmTime.Seconds    = 0U;
00700
00701   /* Alarm Day Settings : Day = 1st day of the month */
00702   RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMA_DATEWEEKDAYSEL_DATE;
00703   RTC_AlarmStruct->AlarmDateWeekDay    = 1U;
00704
00705   /* Alarm Masks Settings : Mask =  all fields are not masked */
00706   RTC_AlarmStruct->AlarmMask           = LL_RTC_ALMA_MASK_NONE;
00707 }
00708
00709 /**
00710   * @brief  Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec /
00711   *         Day = 1st day of the month/Mask = all fields are masked).
00712   * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
00713   * @retval None
00714   */
00715 void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
00716 {
00717   /* Alarm Time Settings : Time = 00h:00mn:00sec */
00718   RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMB_TIME_FORMAT_AM;
00719   RTC_AlarmStruct->AlarmTime.Hours      = 0U;
00720   RTC_AlarmStruct->AlarmTime.Minutes    = 0U;
00721   RTC_AlarmStruct->AlarmTime.Seconds    = 0U;
00722
00723   /* Alarm Day Settings : Day = 1st day of the month */
00724   RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMB_DATEWEEKDAYSEL_DATE;
00725   RTC_AlarmStruct->AlarmDateWeekDay    = 1U;
00726
00727   /* Alarm Masks Settings : Mask =  all fields are not masked */
00728   RTC_AlarmStruct->AlarmMask           = LL_RTC_ALMB_MASK_NONE;
00729 }
00730
00731 /**
00732   * @brief  Enters the RTC Initialization mode.
00733   * @note   The RTC Initialization mode is write protected, use the
00734   *         @ref LL_RTC_DisableWriteProtection before calling this function.
00735   * @param  RTCx RTC Instance
00736   * @retval An ErrorStatus enumeration value:
00737   *          - SUCCESS: RTC is in Init mode
00738   *          - ERROR: RTC is not in Init mode
00739   */
00740 ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx)
00741 {
00742   __IO uint32_t timeout = RTC_INITMODE_TIMEOUT;
00743   ErrorStatus status = SUCCESS;
00744   uint32_t tmp;
00745
00746   /* Check the parameter */
00747   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00748
00749   /* Check if the Initialization mode is set */
00750   if (LL_RTC_IsActiveFlag_INIT(RTCx) == 0U)
00751   {
00752     /* Set the Initialization mode */
00753     LL_RTC_EnableInitMode(RTCx);
00754
00755     /* Wait till RTC is in INIT state and if Time out is reached exit */
00756     tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
00757     while ((timeout != 0U) && (tmp != 1U))
00758     {
00759       if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
00760       {
00761         timeout --;
00762       }
00763       tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
00764       if (timeout == 0U)
00765       {
00766         status = ERROR;
00767       }
00768     }
00769   }
00770   return status;
00771 }
00772
00773 /**
00774   * @brief  Exit the RTC Initialization mode.
00775   * @note   When the initialization sequence is complete, the calendar restarts
00776   *         counting after 4 RTCCLK cycles.
00777   * @note   The RTC Initialization mode is write protected, use the
00778   *         @ref LL_RTC_DisableWriteProtection before calling this function.
00779   * @param  RTCx RTC Instance
00780   * @retval An ErrorStatus enumeration value:
00781   *          - SUCCESS: RTC exited from in Init mode
00782   *          - ERROR: Not applicable
00783   */
00784 ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx)
00785 {
00786   /* Check the parameter */
00787   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00788
00789   /* Disable initialization mode */
00790   LL_RTC_DisableInitMode(RTCx);
00791
00792   return SUCCESS;
00793 }
00794
00795 /**
00796   * @brief  Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are
00797   *         synchronized with RTC APB clock.
00798   * @note   The RTC Resynchronization mode is write protected, use the
00799   *         @ref LL_RTC_DisableWriteProtection before calling this function.
00800   * @note   To read the calendar through the shadow registers after Calendar
00801   *         initialization, calendar update or after wakeup from low power modes
00802   *         the software must first clear the RSF flag.
00803   *         The software must then wait until it is set again before reading
00804   *         the calendar, which means that the calendar registers have been
00805   *         correctly copied into the RTC_TR and RTC_DR shadow registers.
00806   * @param  RTCx RTC Instance
00807   * @retval An ErrorStatus enumeration value:
00808   *          - SUCCESS: RTC registers are synchronised
00809   *          - ERROR: RTC registers are not synchronised
00810   */
00811 ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx)
00812 {
00813   __IO uint32_t timeout = RTC_SYNCHRO_TIMEOUT;
00814   ErrorStatus status = SUCCESS;
00815   uint32_t tmp;
00816
00817   /* Check the parameter */
00818   assert_param(IS_RTC_ALL_INSTANCE(RTCx));
00819
00820   /* Clear RSF flag */
00821   LL_RTC_ClearFlag_RS(RTCx);
00822
00823   /* Wait the registers to be synchronised */
00824   tmp = LL_RTC_IsActiveFlag_RS(RTCx);
00825   while ((timeout != 0U) && (tmp != 0U))
00826   {
00827     if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
00828     {
00829       timeout--;
00830     }
00831     tmp = LL_RTC_IsActiveFlag_RS(RTCx);
00832     if (timeout == 0U)
00833     {
00834       status = ERROR;
00835     }
00836   }
00837
00838   if (status != ERROR)
00839   {
00840     timeout = RTC_SYNCHRO_TIMEOUT;
00841     tmp = LL_RTC_IsActiveFlag_RS(RTCx);
00842     while ((timeout != 0U) && (tmp != 1U))
00843     {
00844       if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
00845       {
00846         timeout--;
00847       }
00848       tmp = LL_RTC_IsActiveFlag_RS(RTCx);
00849       if (timeout == 0U)
00850       {
00851         status = ERROR;
00852       }
00853     }
00854   }
00855
00856   return (status);
00857 }
00858
00859 /**
00860   * @}
00861   */
00862
00863 /**
00864   * @}
00865   */
00866
00867 /**
00868   * @}
00869   */
00870
00871 #endif /* defined(RTC) */
00872
00873 /**
00874   * @}
00875   */
00876
00877 #endif /* USE_FULL_LL_DRIVER */
00878
00879 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_rtc.h Source File

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stm32wbxx_ll_rtc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_rtc.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of RTC LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_LL_RTC_H
00022 #define STM32WBxx_LL_RTC_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx.h"
00030
00031 /** @addtogroup STM32WBxx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined(RTC)
00036
00037 /** @defgroup RTC_LL RTC
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /** @defgroup RTC_LL_Private_Constants RTC Private Constants
00045   * @{
00046   */
00047
00048 /* Write protection defines */
00049 #define RTC_WRITE_PROTECTION_DISABLE  ((uint8_t)0xFFU)
00050 #define RTC_WRITE_PROTECTION_ENABLE_1 ((uint8_t)0xCAU)
00051 #define RTC_WRITE_PROTECTION_ENABLE_2 ((uint8_t)0x53U)
00052
00053 /* Defines used to combine date & time */
00054 #define RTC_OFFSET_WEEKDAY            (uint32_t)24U
00055 #define RTC_OFFSET_DAY                (uint32_t)16U
00056 #define RTC_OFFSET_MONTH              (uint32_t)8U
00057 #define RTC_OFFSET_HOUR               (uint32_t)16U
00058 #define RTC_OFFSET_MINUTE             (uint32_t)8U
00059
00060 /**
00061   * @}
00062   */
00063
00064 /* Private macros ------------------------------------------------------------*/
00065 #if defined(USE_FULL_LL_DRIVER)
00066 /** @defgroup RTC_LL_Private_Macros RTC Private Macros
00067   * @{
00068   */
00069 /**
00070   * @}
00071   */
00072 #endif /*USE_FULL_LL_DRIVER*/
00073
00074 /* Exported types ------------------------------------------------------------*/
00075 #if defined(USE_FULL_LL_DRIVER)
00076 /** @defgroup RTC_LL_ES_INIT RTC Exported Init structure
00077   * @{
00078   */
00079
00080 /**
00081   * @brief  RTC Init structures definition
00082   */
00083 typedef struct
00084 {
00085   uint32_t HourFormat;   /*!< Specifies the RTC Hours Format.
00086                               This parameter can be a value of @ref RTC_LL_EC_HOURFORMAT
00087
00088                               This feature can be modified afterwards using unitary function
00089                               @ref LL_RTC_SetHourFormat(). */
00090
00091   uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value.
00092                               This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F
00093
00094                               This feature can be modified afterwards using unitary function
00095                               @ref LL_RTC_SetAsynchPrescaler(). */
00096
00097   uint32_t SynchPrescaler;  /*!< Specifies the RTC Synchronous Predivider value.
00098                               This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF
00099
00100                               This feature can be modified afterwards using unitary function
00101                               @ref LL_RTC_SetSynchPrescaler(). */
00102 } LL_RTC_InitTypeDef;
00103
00104 /**
00105   * @brief  RTC Time structure definition
00106   */
00107 typedef struct
00108 {
00109   uint32_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
00110                             This parameter can be a value of @ref RTC_LL_EC_TIME_FORMAT
00111
00112                             This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetFormat(). */
00113
00114   uint8_t Hours;       /*!< Specifies the RTC Time Hours.
00115                             This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the @ref LL_RTC_TIME_FORMAT_PM is selected.
00116                             This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the @ref LL_RTC_TIME_FORMAT_AM_OR_24 is selected.
00117
00118                             This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetHour(). */
00119
00120   uint8_t Minutes;     /*!< Specifies the RTC Time Minutes.
00121                             This parameter must be a number between Min_Data = 0 and Max_Data = 59
00122
00123                             This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetMinute(). */
00124
00125   uint8_t Seconds;     /*!< Specifies the RTC Time Seconds.
00126                             This parameter must be a number between Min_Data = 0 and Max_Data = 59
00127
00128                             This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetSecond(). */
00129 } LL_RTC_TimeTypeDef;
00130
00131 /**
00132   * @brief  RTC Date structure definition
00133   */
00134 typedef struct
00135 {
00136   uint8_t WeekDay;  /*!< Specifies the RTC Date WeekDay.
00137                          This parameter can be a value of @ref RTC_LL_EC_WEEKDAY
00138
00139                          This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetWeekDay(). */
00140
00141   uint8_t Month;    /*!< Specifies the RTC Date Month.
00142                          This parameter can be a value of @ref RTC_LL_EC_MONTH
00143
00144                          This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetMonth(). */
00145
00146   uint8_t Day;      /*!< Specifies the RTC Date Day.
00147                          This parameter must be a number between Min_Data = 1 and Max_Data = 31
00148
00149                          This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetDay(). */
00150
00151   uint8_t Year;     /*!< Specifies the RTC Date Year.
00152                          This parameter must be a number between Min_Data = 0 and Max_Data = 99
00153
00154                          This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetYear(). */
00155 } LL_RTC_DateTypeDef;
00156
00157 /**
00158   * @brief  RTC Alarm structure definition
00159   */
00160 typedef struct
00161 {
00162   LL_RTC_TimeTypeDef AlarmTime;  /*!< Specifies the RTC Alarm Time members. */
00163
00164   uint32_t AlarmMask;            /*!< Specifies the RTC Alarm Masks.
00165                                       This parameter can be a value of @ref RTC_LL_EC_ALMA_MASK for ALARM A or @ref RTC_LL_EC_ALMB_MASK for ALARM B.
00166
00167                                       This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetMask() for ALARM A
00168                                       or @ref LL_RTC_ALMB_SetMask() for ALARM B
00169                                  */
00170
00171   uint32_t AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on day or WeekDay.
00172                                       This parameter can be a value of @ref RTC_LL_EC_ALMA_WEEKDAY_SELECTION for ALARM A or @ref RTC_LL_EC_ALMB_WEEKDAY_SELECTION for ALARM B
00173
00174                                       This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_EnableWeekday() or @ref LL_RTC_ALMA_DisableWeekday()
00175                                       for ALARM A or @ref LL_RTC_ALMB_EnableWeekday() or @ref LL_RTC_ALMB_DisableWeekday() for ALARM B
00176                                  */
00177
00178   uint8_t AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Day/WeekDay.
00179                                       If AlarmDateWeekDaySel set to day, this parameter  must be a number between Min_Data = 1 and Max_Data = 31.
00180
00181                                       This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetDay()
00182                                       for ALARM A or @ref LL_RTC_ALMB_SetDay() for ALARM B.
00183
00184                                       If AlarmDateWeekDaySel set to Weekday, this parameter can be a value of @ref RTC_LL_EC_WEEKDAY.
00185
00186                                       This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetWeekDay()
00187                                       for ALARM A or @ref LL_RTC_ALMB_SetWeekDay() for ALARM B.
00188                                  */
00189 } LL_RTC_AlarmTypeDef;
00190
00191 /**
00192   * @}
00193   */
00194 #endif /* USE_FULL_LL_DRIVER */
00195
00196 /* Exported constants --------------------------------------------------------*/
00197 /** @defgroup RTC_LL_Exported_Constants RTC Exported Constants
00198   * @{
00199   */
00200
00201 #if defined(USE_FULL_LL_DRIVER)
00202 /** @defgroup RTC_LL_EC_FORMAT FORMAT
00203   * @{
00204   */
00205 #define LL_RTC_FORMAT_BIN                  0x000000000U /*!< Binary data format */
00206 #define LL_RTC_FORMAT_BCD                  0x000000001U /*!< BCD data format */
00207 /**
00208   * @}
00209   */
00210
00211 /** @defgroup RTC_LL_EC_ALMA_WEEKDAY_SELECTION RTC Alarm A Date WeekDay
00212   * @{
00213   */
00214 #define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE    0x00000000U             /*!< Alarm A Date is selected */
00215 #define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL        /*!< Alarm A WeekDay is selected */
00216 /**
00217   * @}
00218   */
00219
00220 /** @defgroup RTC_LL_EC_ALMB_WEEKDAY_SELECTION RTC Alarm B Date WeekDay
00221   * @{
00222   */
00223 #define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE    0x00000000U             /*!< Alarm B Date is selected */
00224 #define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL        /*!< Alarm B WeekDay is selected */
00225 /**
00226   * @}
00227   */
00228
00229 #endif /* USE_FULL_LL_DRIVER */
00230
00231 /** @defgroup RTC_LL_EC_GET_FLAG Get Flags Defines
00232   * @brief    Flags defines which can be used with LL_RTC_ReadReg function
00233   * @{
00234   */
00235 #define LL_RTC_ISR_ITSF                    RTC_ISR_ITSF
00236 #define LL_RTC_ISR_RECALPF                 RTC_ISR_RECALPF
00237 #if defined(RTC_TAMPER3_SUPPORT)
00238 #define LL_RTC_ISR_TAMP3F                  RTC_ISR_TAMP3F
00239 #endif
00240 #if defined(RTC_TAMPER2_SUPPORT)
00241 #define LL_RTC_ISR_TAMP2F                  RTC_ISR_TAMP2F
00242 #endif
00243 #if defined(RTC_TAMPER1_SUPPORT)
00244 #define LL_RTC_ISR_TAMP1F                  RTC_ISR_TAMP1F
00245 #endif
00246 #define LL_RTC_ISR_TSOVF                   RTC_ISR_TSOVF
00247 #define LL_RTC_ISR_TSF                     RTC_ISR_TSF
00248 #define LL_RTC_ISR_WUTF                    RTC_ISR_WUTF
00249 #define LL_RTC_ISR_ALRBF                   RTC_ISR_ALRBF
00250 #define LL_RTC_ISR_ALRAF                   RTC_ISR_ALRAF
00251 #define LL_RTC_ISR_INITF                   RTC_ISR_INITF
00252 #define LL_RTC_ISR_RSF                     RTC_ISR_RSF
00253 #define LL_RTC_ISR_INITS                   RTC_ISR_INITS
00254 #define LL_RTC_ISR_SHPF                    RTC_ISR_SHPF
00255 #define LL_RTC_ISR_WUTWF                   RTC_ISR_WUTWF
00256 #define LL_RTC_ISR_ALRBWF                  RTC_ISR_ALRBWF
00257 #define LL_RTC_ISR_ALRAWF                  RTC_ISR_ALRAWF
00258 /**
00259   * @}
00260   */
00261
00262 /** @defgroup RTC_LL_EC_IT IT Defines
00263   * @brief    IT defines which can be used with LL_RTC_ReadReg and  LL_RTC_WriteReg functions
00264   * @{
00265   */
00266 #define LL_RTC_CR_TSIE                     RTC_CR_TSIE
00267 #define LL_RTC_CR_WUTIE                    RTC_CR_WUTIE
00268 #define LL_RTC_CR_ALRBIE                   RTC_CR_ALRBIE
00269 #define LL_RTC_CR_ALRAIE                   RTC_CR_ALRAIE
00270 #if defined(RTC_TAMPER3_SUPPORT)
00271 #define LL_RTC_TAMPCR_TAMP3IE              RTC_TAMPCR_TAMP3IE
00272 #endif
00273 #if defined(RTC_TAMPER2_SUPPORT)
00274 #define LL_RTC_TAMPCR_TAMP2IE              RTC_TAMPCR_TAMP2IE
00275 #endif
00276 #if defined(RTC_TAMPER1_SUPPORT)
00277 #define LL_RTC_TAMPCR_TAMP1IE              RTC_TAMPCR_TAMP1IE
00278 #endif
00279 #define LL_RTC_TAMPCR_TAMPIE               RTC_TAMPCR_TAMPIE
00280 /**
00281   * @}
00282   */
00283
00284 /** @defgroup RTC_LL_EC_WEEKDAY  WEEK DAY
00285   * @{
00286   */
00287 #define LL_RTC_WEEKDAY_MONDAY              ((uint8_t)0x01U) /*!< Monday    */
00288 #define LL_RTC_WEEKDAY_TUESDAY             ((uint8_t)0x02U) /*!< Tuesday   */
00289 #define LL_RTC_WEEKDAY_WEDNESDAY           ((uint8_t)0x03U) /*!< Wednesday */
00290 #define LL_RTC_WEEKDAY_THURSDAY            ((uint8_t)0x04U) /*!< Thrusday  */
00291 #define LL_RTC_WEEKDAY_FRIDAY              ((uint8_t)0x05U) /*!< Friday    */
00292 #define LL_RTC_WEEKDAY_SATURDAY            ((uint8_t)0x06U) /*!< Saturday  */
00293 #define LL_RTC_WEEKDAY_SUNDAY              ((uint8_t)0x07U) /*!< Sunday    */
00294 /**
00295   * @}
00296   */
00297
00298 /** @defgroup RTC_LL_EC_MONTH  MONTH
00299   * @{
00300   */
00301 #define LL_RTC_MONTH_JANUARY               ((uint8_t)0x01U)  /*!< January   */
00302 #define LL_RTC_MONTH_FEBRUARY              ((uint8_t)0x02U)  /*!< February  */
00303 #define LL_RTC_MONTH_MARCH                 ((uint8_t)0x03U)  /*!< March     */
00304 #define LL_RTC_MONTH_APRIL                 ((uint8_t)0x04U)  /*!< April     */
00305 #define LL_RTC_MONTH_MAY                   ((uint8_t)0x05U)  /*!< May       */
00306 #define LL_RTC_MONTH_JUNE                  ((uint8_t)0x06U)  /*!< June      */
00307 #define LL_RTC_MONTH_JULY                  ((uint8_t)0x07U)  /*!< July      */
00308 #define LL_RTC_MONTH_AUGUST                ((uint8_t)0x08U)  /*!< August    */
00309 #define LL_RTC_MONTH_SEPTEMBER             ((uint8_t)0x09U)  /*!< September */
00310 #define LL_RTC_MONTH_OCTOBER               ((uint8_t)0x10U)  /*!< October   */
00311 #define LL_RTC_MONTH_NOVEMBER              ((uint8_t)0x11U)  /*!< November  */
00312 #define LL_RTC_MONTH_DECEMBER              ((uint8_t)0x12U)  /*!< December  */
00313 /**
00314   * @}
00315   */
00316
00317 /** @defgroup RTC_LL_EC_HOURFORMAT  HOUR FORMAT
00318   * @{
00319   */
00320 #define LL_RTC_HOURFORMAT_24HOUR           0x00000000U           /*!< 24 hour/day format */
00321 #define LL_RTC_HOURFORMAT_AMPM             RTC_CR_FMT            /*!< AM/PM hour format */
00322 /**
00323   * @}
00324   */
00325
00326 /** @defgroup RTC_LL_EC_ALARMOUT  ALARM OUTPUT
00327   * @{
00328   */
00329 #define LL_RTC_ALARMOUT_DISABLE            0x00000000U             /*!< Output disabled */
00330 #define LL_RTC_ALARMOUT_ALMA               RTC_CR_OSEL_0           /*!< Alarm A output enabled */
00331 #define LL_RTC_ALARMOUT_ALMB               RTC_CR_OSEL_1           /*!< Alarm B output enabled */
00332 #define LL_RTC_ALARMOUT_WAKEUP             RTC_CR_OSEL             /*!< Wakeup output enabled */
00333 /**
00334   * @}
00335   */
00336
00337 /** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE  ALARM OUTPUT TYPE
00338   * @{
00339   */
00340 #define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN  0x00000000U                          /*!< RTC_ALARM, when mapped on PC13, is open-drain output */
00341 #define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL   RTC_OR_ALARMOUTTYPE /*!< RTC_ALARM, when mapped on PC13, is push-pull output */
00342 /**
00343   * @}
00344   */
00345
00346 /** @defgroup RTC_LL_EC_OUTPUTPOLARITY_PIN  OUTPUT POLARITY PIN
00347   * @{
00348   */
00349 #define LL_RTC_OUTPUTPOLARITY_PIN_HIGH     0x00000000U           /*!< Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)*/
00350 #define LL_RTC_OUTPUTPOLARITY_PIN_LOW      RTC_CR_POL            /*!< Pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL) */
00351 /**
00352   * @}
00353   */
00354
00355 /** @defgroup RTC_LL_EC_TIME_FORMAT TIME FORMAT
00356   * @{
00357   */
00358 #define LL_RTC_TIME_FORMAT_AM_OR_24        0x00000000U           /*!< AM or 24-hour format */
00359 #define LL_RTC_TIME_FORMAT_PM              RTC_TR_PM             /*!< PM */
00360 /**
00361   * @}
00362   */
00363
00364 /** @defgroup RTC_LL_EC_SHIFT_SECOND  SHIFT SECOND
00365   * @{
00366   */
00367 #define LL_RTC_SHIFT_SECOND_DELAY          0x00000000U           /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */
00368 #define LL_RTC_SHIFT_SECOND_ADVANCE        RTC_SHIFTR_ADD1S      /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */
00369 /**
00370   * @}
00371   */
00372
00373 /** @defgroup RTC_LL_EC_ALMA_MASK  ALARMA MASK
00374   * @{
00375   */
00376 #define LL_RTC_ALMA_MASK_NONE              0x00000000U             /*!< No masks applied on Alarm A*/
00377 #define LL_RTC_ALMA_MASK_DATEWEEKDAY       RTC_ALRMAR_MSK4         /*!< Date/day do not care in Alarm A comparison */
00378 #define LL_RTC_ALMA_MASK_HOURS             RTC_ALRMAR_MSK3         /*!< Hours do not care in Alarm A comparison */
00379 #define LL_RTC_ALMA_MASK_MINUTES           RTC_ALRMAR_MSK2         /*!< Minutes do not care in Alarm A comparison */
00380 #define LL_RTC_ALMA_MASK_SECONDS           RTC_ALRMAR_MSK1         /*!< Seconds do not care in Alarm A comparison */
00381 #define LL_RTC_ALMA_MASK_ALL               (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1) /*!< Masks all */
00382 /**
00383   * @}
00384   */
00385
00386 /** @defgroup RTC_LL_EC_ALMA_TIME_FORMAT  ALARMA TIME FORMAT
00387   * @{
00388   */
00389 #define LL_RTC_ALMA_TIME_FORMAT_AM         0x00000000U           /*!< AM or 24-hour format */
00390 #define LL_RTC_ALMA_TIME_FORMAT_PM         RTC_ALRMAR_PM         /*!< PM */
00391 /**
00392   * @}
00393   */
00394
00395 /** @defgroup RTC_LL_EC_ALMB_MASK  ALARMB MASK
00396   * @{
00397   */
00398 #define LL_RTC_ALMB_MASK_NONE              0x00000000U             /*!< No masks applied on Alarm B*/
00399 #define LL_RTC_ALMB_MASK_DATEWEEKDAY       RTC_ALRMBR_MSK4         /*!< Date/day do not care in Alarm B comparison */
00400 #define LL_RTC_ALMB_MASK_HOURS             RTC_ALRMBR_MSK3         /*!< Hours do not care in Alarm B comparison */
00401 #define LL_RTC_ALMB_MASK_MINUTES           RTC_ALRMBR_MSK2         /*!< Minutes do not care in Alarm B comparison */
00402 #define LL_RTC_ALMB_MASK_SECONDS           RTC_ALRMBR_MSK1         /*!< Seconds do not care in Alarm B comparison */
00403 #define LL_RTC_ALMB_MASK_ALL               (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1) /*!< Masks all */
00404 /**
00405   * @}
00406   */
00407
00408 /** @defgroup RTC_LL_EC_ALMB_TIME_FORMAT  ALARMB TIME FORMAT
00409   * @{
00410   */
00411 #define LL_RTC_ALMB_TIME_FORMAT_AM         0x00000000U           /*!< AM or 24-hour format */
00412 #define LL_RTC_ALMB_TIME_FORMAT_PM         RTC_ALRMBR_PM         /*!< PM */
00413 /**
00414   * @}
00415   */
00416
00417 /** @defgroup RTC_LL_EC_TIMESTAMP_EDGE  TIMESTAMP EDGE
00418   * @{
00419   */
00420 #define LL_RTC_TIMESTAMP_EDGE_RISING       0x00000000U           /*!< RTC_TS input rising edge generates a time-stamp event */
00421 #define LL_RTC_TIMESTAMP_EDGE_FALLING      RTC_CR_TSEDGE         /*!< RTC_TS input falling edge generates a time-stamp even */
00422 /**
00423   * @}
00424   */
00425
00426 /** @defgroup RTC_LL_EC_TS_TIME_FORMAT  TIMESTAMP TIME FORMAT
00427   * @{
00428   */
00429 #define LL_RTC_TS_TIME_FORMAT_AM           0x00000000U           /*!< AM or 24-hour format */
00430 #define LL_RTC_TS_TIME_FORMAT_PM           RTC_TSTR_PM           /*!< PM */
00431 /**
00432   * @}
00433   */
00434
00435 /** @defgroup RTC_LL_EC_TAMPER  TAMPER
00436   * @{
00437   */
00438 #if defined(RTC_TAMPER1_SUPPORT)
00439 #define LL_RTC_TAMPER_1                    RTC_TAMPCR_TAMP1E /*!< RTC_TAMP1 input detection */
00440 #endif /* RTC_TAMPER1_SUPPORT */
00441 #if defined(RTC_TAMPER2_SUPPORT)
00442 #if defined(RTC_TAMPER2_SUPPORT)
00443 #define LL_RTC_TAMPER_2                    RTC_TAMPCR_TAMP2E /*!< RTC_TAMP2 input detection */
00444 #endif
00445 #endif /* RTC_TAMPER2_SUPPORT */
00446 #if defined(RTC_TAMPER3_SUPPORT)
00447 #define LL_RTC_TAMPER_3                    RTC_TAMPCR_TAMP3E /*!< RTC_TAMP3 input detection */
00448 #endif /* RTC_TAMPER3_SUPPORT */
00449 /**
00450   * @}
00451   */
00452
00453 /** @defgroup RTC_LL_EC_TAMPER_MASK  TAMPER MASK
00454   * @{
00455   */
00456 #if defined(RTC_TAMPER1_SUPPORT)
00457 #define LL_RTC_TAMPER_MASK_TAMPER1         RTC_TAMPCR_TAMP1MF /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */
00458 #endif /* RTC_TAMPER1_SUPPORT */
00459 #if defined(RTC_TAMPER2_SUPPORT)
00460 #define LL_RTC_TAMPER_MASK_TAMPER2         RTC_TAMPCR_TAMP2MF /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */
00461 #endif /* RTC_TAMPER2_SUPPORT */
00462 #if defined(RTC_TAMPER3_SUPPORT)
00463 #define LL_RTC_TAMPER_MASK_TAMPER3         RTC_TAMPCR_TAMP3MF /*!< Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased */
00464 #endif /* RTC_TAMPER3_SUPPORT */
00465 /**
00466   * @}
00467   */
00468
00469 /** @defgroup RTC_LL_EC_TAMPER_NOERASE  TAMPER NO ERASE
00470   * @{
00471   */
00472 #if defined(RTC_TAMPER1_SUPPORT)
00473 #define LL_RTC_TAMPER_NOERASE_TAMPER1      RTC_TAMPCR_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */
00474 #endif /* RTC_TAMPER1_SUPPORT */
00475 #if defined(RTC_TAMPER2_SUPPORT)
00476 #define LL_RTC_TAMPER_NOERASE_TAMPER2      RTC_TAMPCR_TAMP2NOERASE /*!< Tamper 2 event does not erase the backup registers. */
00477 #endif /* RTC_TAMPER2_SUPPORT */
00478 #if defined(RTC_TAMPER3_SUPPORT)
00479 #define LL_RTC_TAMPER_NOERASE_TAMPER3      RTC_TAMPCR_TAMP3NOERASE /*!< Tamper 3 event does not erase the backup registers. */
00480 #endif /* RTC_TAMPER3_SUPPORT */
00481 /**
00482   * @}
00483   */
00484
00485 #if defined(RTC_TAMPCR_TAMPPRCH)
00486 /** @defgroup RTC_LL_EC_TAMPER_DURATION  TAMPER DURATION
00487   * @{
00488   */
00489 #define LL_RTC_TAMPER_DURATION_1RTCCLK     0x00000000U                             /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle  */
00490 #define LL_RTC_TAMPER_DURATION_2RTCCLK     RTC_TAMPCR_TAMPPRCH_0  /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */
00491 #define LL_RTC_TAMPER_DURATION_4RTCCLK     RTC_TAMPCR_TAMPPRCH_1  /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */
00492 #define LL_RTC_TAMPER_DURATION_8RTCCLK     RTC_TAMPCR_TAMPPRCH    /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */
00493 /**
00494   * @}
00495   */
00496 #endif /* RTC_TAMPCR_TAMPPRCH */
00497
00498 #if defined(RTC_TAMPCR_TAMPFLT)
00499 /** @defgroup RTC_LL_EC_TAMPER_FILTER  TAMPER FILTER
00500   * @{
00501   */
00502 #define LL_RTC_TAMPER_FILTER_DISABLE       0x00000000U                              /*!< Tamper filter is disabled */
00503 #define LL_RTC_TAMPER_FILTER_2SAMPLE       RTC_TAMPCR_TAMPFLT_0    /*!< Tamper is activated after 2 consecutive samples at the active level */
00504 #define LL_RTC_TAMPER_FILTER_4SAMPLE       RTC_TAMPCR_TAMPFLT_1    /*!< Tamper is activated after 4 consecutive samples at the active level */
00505 #define LL_RTC_TAMPER_FILTER_8SAMPLE       RTC_TAMPCR_TAMPFLT      /*!< Tamper is activated after 8 consecutive samples at the active level. */
00506 /**
00507   * @}
00508   */
00509 #endif /* RTC_TAMPCR_TAMPFLT */
00510
00511 #if defined(RTC_TAMPCR_TAMPFREQ)
00512 /** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV  TAMPER SAMPLING FREQUENCY DIVIDER
00513   * @{
00514   */
00515 #define LL_RTC_TAMPER_SAMPLFREQDIV_32768   0x00000000U                                                      /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 32768 */
00516 #define LL_RTC_TAMPER_SAMPLFREQDIV_16384   RTC_TAMPCR_TAMPFREQ_0                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 16384 */
00517 #define LL_RTC_TAMPER_SAMPLFREQDIV_8192    RTC_TAMPCR_TAMPFREQ_1                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 8192 */
00518 #define LL_RTC_TAMPER_SAMPLFREQDIV_4096    (RTC_TAMPCR_TAMPFREQ_1 | RTC_TAMPCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 4096 */
00519 #define LL_RTC_TAMPER_SAMPLFREQDIV_2048    RTC_TAMPCR_TAMPFREQ_2                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 2048 */
00520 #define LL_RTC_TAMPER_SAMPLFREQDIV_1024    (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 1024 */
00521 #define LL_RTC_TAMPER_SAMPLFREQDIV_512     (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 512 */
00522 #define LL_RTC_TAMPER_SAMPLFREQDIV_256     RTC_TAMPCR_TAMPFREQ                             /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 256 */
00523 /**
00524   * @}
00525   */
00526 #endif /* RTC_TAMPCR_TAMPFREQ */
00527
00528 /** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL  TAMPER ACTIVE LEVEL
00529   * @{
00530   */
00531 #if defined(RTC_TAMPER1_SUPPORT)
00532 #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1    RTC_TAMPCR_TAMP1TRG /*!< RTC_TAMP1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
00533 #endif /* RTC_TAMPER1_SUPPORT */
00534 #if defined(RTC_TAMPER2_SUPPORT)
00535 #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2    RTC_TAMPCR_TAMP2TRG /*!< RTC_TAMP2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
00536 #endif /* RTC_TAMPER2_SUPPORT */
00537 #if defined(RTC_TAMPER3_SUPPORT)
00538 #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3    RTC_TAMPCR_TAMP3TRG /*!< RTC_TAMP3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
00539 #endif /* RTC_TAMPER3_SUPPORT */
00540 /**
00541   * @}
00542   */
00543
00544 /** @defgroup RTC_LL_EC_WAKEUPCLOCK_DIV  WAKEUP CLOCK DIV
00545   * @{
00546   */
00547 #define LL_RTC_WAKEUPCLOCK_DIV_16          0x00000000U                           /*!< RTC/16 clock is selected */
00548 #define LL_RTC_WAKEUPCLOCK_DIV_8           (RTC_CR_WUCKSEL_0)                    /*!< RTC/8 clock is selected */
00549 #define LL_RTC_WAKEUPCLOCK_DIV_4           (RTC_CR_WUCKSEL_1)                    /*!< RTC/4 clock is selected */
00550 #define LL_RTC_WAKEUPCLOCK_DIV_2           (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0) /*!< RTC/2 clock is selected */
00551 #define LL_RTC_WAKEUPCLOCK_CKSPRE          (RTC_CR_WUCKSEL_2)                    /*!< ck_spre (usually 1 Hz) clock is selected */
00552 #define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT      (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1) /*!< ck_spre (usually 1 Hz) clock is selected and 2exp16 is added to the WUT counter value*/
00553 /**
00554   * @}
00555   */
00556
00557 #if defined(RTC_BACKUP_SUPPORT)
00558 /** @defgroup RTC_LL_EC_BKP  BACKUP
00559   * @{
00560   */
00561 #define LL_RTC_BKP_DR0                     0x00000000U
00562 #define LL_RTC_BKP_DR1                     0x00000001U
00563 #define LL_RTC_BKP_DR2                     0x00000002U
00564 #define LL_RTC_BKP_DR3                     0x00000003U
00565 #define LL_RTC_BKP_DR4                     0x00000004U
00566 #if RTC_BKP_NUMBER > 5
00567 #define LL_RTC_BKP_DR5                     0x00000005U
00568 #define LL_RTC_BKP_DR6                     0x00000006U
00569 #define LL_RTC_BKP_DR7                     0x00000007U
00570 #define LL_RTC_BKP_DR8                     0x00000008U
00571 #define LL_RTC_BKP_DR9                     0x00000009U
00572 #define LL_RTC_BKP_DR10                    0x0000000AU
00573 #define LL_RTC_BKP_DR11                    0x0000000BU
00574 #define LL_RTC_BKP_DR12                    0x0000000CU
00575 #define LL_RTC_BKP_DR13                    0x0000000DU
00576 #define LL_RTC_BKP_DR14                    0x0000000EU
00577 #define LL_RTC_BKP_DR15                    0x0000000FU
00578 #endif /* RTC_BKP_NUMBER > 5 */
00579
00580 #if RTC_BKP_NUMBER > 16
00581 #define LL_RTC_BKP_DR16                    0x00000010U
00582 #define LL_RTC_BKP_DR17                    0x00000011U
00583 #define LL_RTC_BKP_DR18                    0x00000012U
00584 #define LL_RTC_BKP_DR19                    0x00000013U
00585 #endif /* RTC_BKP_NUMBER > 16 */
00586 /**
00587   * @}
00588   */
00589 #endif /* RTC_BACKUP_SUPPORT */
00590
00591 /** @defgroup RTC_LL_EC_CALIB_OUTPUT  Calibration output
00592   * @{
00593   */
00594 #define LL_RTC_CALIB_OUTPUT_NONE           0x00000000U                 /*!< Calibration output disabled */
00595 #define LL_RTC_CALIB_OUTPUT_1HZ            (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 512 Hz */
00596 #define LL_RTC_CALIB_OUTPUT_512HZ          (RTC_CR_COE)                /*!< Calibration output is 1 Hz */
00597 /**
00598   * @}
00599   */
00600
00601 /** @defgroup RTC_LL_EC_CALIB_INSERTPULSE  Calibration pulse insertion
00602   * @{
00603   */
00604 #define LL_RTC_CALIB_INSERTPULSE_NONE      0x00000000U           /*!< No RTCCLK pulses are added */
00605 #define LL_RTC_CALIB_INSERTPULSE_SET       RTC_CALR_CALP         /*!< One RTCCLK pulse is effectively inserted every 2exp11 pulses (frequency increased by 488.5 ppm) */
00606 /**
00607   * @}
00608   */
00609
00610 /** @defgroup RTC_LL_EC_CALIB_PERIOD  Calibration period
00611   * @{
00612   */
00613 #define LL_RTC_CALIB_PERIOD_32SEC          0x00000000U           /*!< Use a 32-second calibration cycle period */
00614 #define LL_RTC_CALIB_PERIOD_16SEC          RTC_CALR_CALW16       /*!< Use a 16-second calibration cycle period */
00615 #define LL_RTC_CALIB_PERIOD_8SEC           RTC_CALR_CALW8        /*!< Use a 8-second calibration cycle period */
00616 /**
00617   * @}
00618   */
00619
00620 /**
00621   * @}
00622   */
00623
00624 /* Exported macro ------------------------------------------------------------*/
00625 /** @defgroup RTC_LL_Exported_Macros RTC Exported Macros
00626   * @{
00627   */
00628
00629 /** @defgroup RTC_LL_EM_WRITE_READ Common Write and read registers Macros
00630   * @{
00631   */
00632
00633 /**
00634   * @brief  Write a value in RTC register
00635   * @param  __INSTANCE__ RTC Instance
00636   * @param  __REG__ Register to be written
00637   * @param  __VALUE__ Value to be written in the register
00638   * @retval None
00639   */
00640 #define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00641
00642 /**
00643   * @brief  Read a value in RTC register
00644   * @param  __INSTANCE__ RTC Instance
00645   * @param  __REG__ Register to be read
00646   * @retval Register value
00647   */
00648 #define LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00649 /**
00650   * @}
00651   */
00652
00653 /** @defgroup RTC_LL_EM_Convert Convert helper Macros
00654   * @{
00655   */
00656
00657 /**
00658   * @brief  Helper macro to convert a value from 2 digit decimal format to BCD format
00659   * @param  __VALUE__ Byte to be converted
00660   * @retval Converted byte
00661   */
00662 #define __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))
00663
00664 /**
00665   * @brief  Helper macro to convert a value from BCD format to 2 digit decimal format
00666   * @param  __VALUE__ BCD value to be converted
00667   * @retval Converted byte
00668   */
00669 #define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) (uint8_t)((((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U ) + ((__VALUE__) & (uint8_t)0x0FU))
00670
00671 /**
00672   * @}
00673   */
00674
00675 /** @defgroup RTC_LL_EM_Date Date helper Macros
00676   * @{
00677   */
00678
00679 /**
00680   * @brief  Helper macro to retrieve weekday.
00681   * @param  __RTC_DATE__ Date returned by @ref  LL_RTC_DATE_Get function.
00682   * @retval Returned value can be one of the following values:
00683   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
00684   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
00685   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
00686   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
00687   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
00688   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
00689   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
00690   */
00691 #define __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)
00692
00693 /**
00694   * @brief  Helper macro to retrieve Year in BCD format
00695   * @param  __RTC_DATE__ Value returned by @ref  LL_RTC_DATE_Get
00696   * @retval Year in BCD format (0x00 . . . 0x99)
00697   */
00698 #define __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU)
00699
00700 /**
00701   * @brief  Helper macro to retrieve Month in BCD format
00702   * @param  __RTC_DATE__ Value returned by @ref  LL_RTC_DATE_Get
00703   * @retval Returned value can be one of the following values:
00704   *         @arg @ref LL_RTC_MONTH_JANUARY
00705   *         @arg @ref LL_RTC_MONTH_FEBRUARY
00706   *         @arg @ref LL_RTC_MONTH_MARCH
00707   *         @arg @ref LL_RTC_MONTH_APRIL
00708   *         @arg @ref LL_RTC_MONTH_MAY
00709   *         @arg @ref LL_RTC_MONTH_JUNE
00710   *         @arg @ref LL_RTC_MONTH_JULY
00711   *         @arg @ref LL_RTC_MONTH_AUGUST
00712   *         @arg @ref LL_RTC_MONTH_SEPTEMBER
00713   *         @arg @ref LL_RTC_MONTH_OCTOBER
00714   *         @arg @ref LL_RTC_MONTH_NOVEMBER
00715   *         @arg @ref LL_RTC_MONTH_DECEMBER
00716   */
00717 #define __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)
00718
00719 /**
00720   * @brief  Helper macro to retrieve Day in BCD format
00721   * @param  __RTC_DATE__ Value returned by @ref  LL_RTC_DATE_Get
00722   * @retval Day in BCD format (0x01 . . . 0x31)
00723   */
00724 #define __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)
00725
00726 /**
00727   * @}
00728   */
00729
00730 /** @defgroup RTC_LL_EM_Time Time helper Macros
00731   * @{
00732   */
00733
00734 /**
00735   * @brief  Helper macro to retrieve hour in BCD format
00736   * @param  __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
00737   * @retval Hours in BCD format (0x01. . .0x12 or between Min_Data=0x00 and Max_Data=0x23)
00738   */
00739 #define __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)
00740
00741 /**
00742   * @brief  Helper macro to retrieve minute in BCD format
00743   * @param  __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
00744   * @retval Minutes in BCD format (0x00. . .0x59)
00745   */
00746 #define __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)
00747
00748 /**
00749   * @brief  Helper macro to retrieve second in BCD format
00750   * @param  __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
00751   * @retval Seconds in  format (0x00. . .0x59)
00752   */
00753 #define __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU)
00754
00755 /**
00756   * @}
00757   */
00758
00759 /**
00760   * @}
00761   */
00762
00763 /* Exported functions --------------------------------------------------------*/
00764 /** @defgroup RTC_LL_Exported_Functions RTC Exported Functions
00765   * @{
00766   */
00767
00768 /** @defgroup RTC_LL_EF_Configuration Configuration
00769   * @{
00770   */
00771
00772 /**
00773   * @brief  Set Hours format (24 hour/day or AM/PM hour format)
00774   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
00775   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
00776   * @rmtoll CR           FMT           LL_RTC_SetHourFormat
00777   * @param  RTCx RTC Instance
00778   * @param  HourFormat This parameter can be one of the following values:
00779   *         @arg @ref LL_RTC_HOURFORMAT_24HOUR
00780   *         @arg @ref LL_RTC_HOURFORMAT_AMPM
00781   * @retval None
00782   */
00783 __STATIC_INLINE void LL_RTC_SetHourFormat(RTC_TypeDef *RTCx, uint32_t HourFormat)
00784 {
00785   MODIFY_REG(RTCx->CR, RTC_CR_FMT, HourFormat);
00786 }
00787
00788 /**
00789   * @brief  Get Hours format (24 hour/day or AM/PM hour format)
00790   * @rmtoll CR           FMT           LL_RTC_GetHourFormat
00791   * @param  RTCx RTC Instance
00792   * @retval Returned value can be one of the following values:
00793   *         @arg @ref LL_RTC_HOURFORMAT_24HOUR
00794   *         @arg @ref LL_RTC_HOURFORMAT_AMPM
00795   */
00796 __STATIC_INLINE uint32_t LL_RTC_GetHourFormat(RTC_TypeDef *RTCx)
00797 {
00798   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_FMT));
00799 }
00800
00801 /**
00802   * @brief  Select the flag to be routed to RTC_ALARM output
00803   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
00804   * @rmtoll CR           OSEL          LL_RTC_SetAlarmOutEvent
00805   * @param  RTCx RTC Instance
00806   * @param  AlarmOutput This parameter can be one of the following values:
00807   *         @arg @ref LL_RTC_ALARMOUT_DISABLE
00808   *         @arg @ref LL_RTC_ALARMOUT_ALMA
00809   *         @arg @ref LL_RTC_ALARMOUT_ALMB
00810   *         @arg @ref LL_RTC_ALARMOUT_WAKEUP
00811   * @retval None
00812   */
00813 __STATIC_INLINE void LL_RTC_SetAlarmOutEvent(RTC_TypeDef *RTCx, uint32_t AlarmOutput)
00814 {
00815   MODIFY_REG(RTCx->CR, RTC_CR_OSEL, AlarmOutput);
00816 }
00817
00818 /**
00819   * @brief  Get the flag to be routed to RTC_ALARM output
00820   * @rmtoll CR           OSEL          LL_RTC_GetAlarmOutEvent
00821   * @param  RTCx RTC Instance
00822   * @retval Returned value can be one of the following values:
00823   *         @arg @ref LL_RTC_ALARMOUT_DISABLE
00824   *         @arg @ref LL_RTC_ALARMOUT_ALMA
00825   *         @arg @ref LL_RTC_ALARMOUT_ALMB
00826   *         @arg @ref LL_RTC_ALARMOUT_WAKEUP
00827   */
00828 __STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx)
00829 {
00830   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL));
00831 }
00832
00833 /**
00834   * @brief  Set RTC_ALARM output type (ALARM in push-pull or open-drain output)
00835   * @note   Used only when RTC_ALARM is mapped on PC13
00836   * @rmtoll OR        ALARMOUTTYPE  LL_RTC_SetAlarmOutputType
00837   * @param  RTCx RTC Instance
00838   * @param  Output This parameter can be one of the following values:
00839   *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
00840   *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
00841   * @retval None
00842   */
00843 __STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Output)
00844 {
00845   MODIFY_REG(RTCx->OR, RTC_OR_ALARMOUTTYPE, Output);
00846 }
00847
00848 /**
00849   * @brief  Get RTC_ALARM output type (ALARM in push-pull or open-drain output)
00850   * @note   used only when RTC_ALARM is mapped on PC13
00851   * @rmtoll OR        ALARMOUTTYPE  LL_RTC_GetAlarmOutputType
00852   * @param  RTCx RTC Instance
00853   * @retval Returned value can be one of the following values:
00854   *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
00855   *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
00856   */
00857 __STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx)
00858 {
00859   return (uint32_t)(READ_BIT(RTCx->OR, RTC_OR_ALARMOUTTYPE));
00860 }
00861
00862 /**
00863   * @brief  Enable initialization mode
00864   * @note   Initialization mode is used to program time and date register (RTC_TR and RTC_DR)
00865   *         and prescaler register (RTC_PRER).
00866   *         Counters are stopped and start counting from the new value when INIT is reset.
00867   * @rmtoll ISR          INIT          LL_RTC_EnableInitMode
00868   * @param  RTCx RTC Instance
00869   * @retval None
00870   */
00871 __STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx)
00872 {
00873   /* Set the Initialization mode */
00874   WRITE_REG(RTCx->ISR, 0xFFFFFFFFU);
00875 }
00876
00877 /**
00878   * @brief  Disable initialization mode (Free running mode)
00879   * @rmtoll ISR          INIT          LL_RTC_DisableInitMode
00880   * @param  RTCx RTC Instance
00881   * @retval None
00882   */
00883 __STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx)
00884 {
00885   /* Exit Initialization mode */
00886   WRITE_REG(RTCx->ISR, (uint32_t)~RTC_ISR_INIT);
00887 }
00888
00889 /**
00890   * @brief  Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted)
00891   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
00892   * @rmtoll CR           POL           LL_RTC_SetOutputPolarity
00893   * @param  RTCx RTC Instance
00894   * @param  Polarity This parameter can be one of the following values:
00895   *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH
00896   *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW
00897   * @retval None
00898   */
00899 __STATIC_INLINE void LL_RTC_SetOutputPolarity(RTC_TypeDef *RTCx, uint32_t Polarity)
00900 {
00901   MODIFY_REG(RTCx->CR, RTC_CR_POL, Polarity);
00902 }
00903
00904 /**
00905   * @brief  Get Output polarity
00906   * @rmtoll CR           POL           LL_RTC_GetOutputPolarity
00907   * @param  RTCx RTC Instance
00908   * @retval Returned value can be one of the following values:
00909   *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH
00910   *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW
00911   */
00912 __STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(RTC_TypeDef *RTCx)
00913 {
00914   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_POL));
00915 }
00916
00917 /**
00918   * @brief  Enable Bypass the shadow registers
00919   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
00920   * @rmtoll CR           BYPSHAD       LL_RTC_EnableShadowRegBypass
00921   * @param  RTCx RTC Instance
00922   * @retval None
00923   */
00924 __STATIC_INLINE void LL_RTC_EnableShadowRegBypass(RTC_TypeDef *RTCx)
00925 {
00926   SET_BIT(RTCx->CR, RTC_CR_BYPSHAD);
00927 }
00928
00929 /**
00930   * @brief  Disable Bypass the shadow registers
00931   * @rmtoll CR           BYPSHAD       LL_RTC_DisableShadowRegBypass
00932   * @param  RTCx RTC Instance
00933   * @retval None
00934   */
00935 __STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx)
00936 {
00937   CLEAR_BIT(RTCx->CR, RTC_CR_BYPSHAD);
00938 }
00939
00940 /**
00941   * @brief  Check if Shadow registers bypass is enabled or not.
00942   * @rmtoll CR           BYPSHAD       LL_RTC_IsShadowRegBypassEnabled
00943   * @param  RTCx RTC Instance
00944   * @retval State of bit (1 or 0).
00945   */
00946 __STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx)
00947 {
00948   return ((READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD)) ? 1UL : 0UL);
00949 }
00950
00951 /**
00952   * @brief  Enable RTC_REFIN reference clock detection (50 or 60 Hz)
00953   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
00954   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
00955   * @rmtoll CR           REFCKON       LL_RTC_EnableRefClock
00956   * @param  RTCx RTC Instance
00957   * @retval None
00958   */
00959 __STATIC_INLINE void LL_RTC_EnableRefClock(RTC_TypeDef *RTCx)
00960 {
00961   SET_BIT(RTCx->CR, RTC_CR_REFCKON);
00962 }
00963
00964 /**
00965   * @brief  Disable RTC_REFIN reference clock detection (50 or 60 Hz)
00966   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
00967   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
00968   * @rmtoll CR           REFCKON       LL_RTC_DisableRefClock
00969   * @param  RTCx RTC Instance
00970   * @retval None
00971   */
00972 __STATIC_INLINE void LL_RTC_DisableRefClock(RTC_TypeDef *RTCx)
00973 {
00974   CLEAR_BIT(RTCx->CR, RTC_CR_REFCKON);
00975 }
00976
00977 /**
00978   * @brief  Set Asynchronous prescaler factor
00979   * @rmtoll PRER         PREDIV_A      LL_RTC_SetAsynchPrescaler
00980   * @param  RTCx RTC Instance
00981   * @param  AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7F
00982   * @retval None
00983   */
00984 __STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler)
00985 {
00986   MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_PRER_PREDIV_A_Pos);
00987 }
00988
00989 /**
00990   * @brief  Set Synchronous prescaler factor
00991   * @rmtoll PRER         PREDIV_S      LL_RTC_SetSynchPrescaler
00992   * @param  RTCx RTC Instance
00993   * @param  SynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7FFF
00994   * @retval None
00995   */
00996 __STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchPrescaler)
00997 {
00998   MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_S, SynchPrescaler);
00999 }
01000
01001 /**
01002   * @brief  Get Asynchronous prescaler factor
01003   * @rmtoll PRER         PREDIV_A      LL_RTC_GetAsynchPrescaler
01004   * @param  RTCx RTC Instance
01005   * @retval Value between Min_Data = 0 and Max_Data = 0x7F
01006   */
01007 __STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx)
01008 {
01009   return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos);
01010 }
01011
01012 /**
01013   * @brief  Get Synchronous prescaler factor
01014   * @rmtoll PRER         PREDIV_S      LL_RTC_GetSynchPrescaler
01015   * @param  RTCx RTC Instance
01016   * @retval Value between Min_Data = 0 and Max_Data = 0x7FFF
01017   */
01018 __STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(RTC_TypeDef *RTCx)
01019 {
01020   return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_S));
01021 }
01022
01023 /**
01024   * @brief  Enable the write protection for RTC registers.
01025   * @rmtoll WPR          KEY           LL_RTC_EnableWriteProtection
01026   * @param  RTCx RTC Instance
01027   * @retval None
01028   */
01029 __STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx)
01030 {
01031   WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_DISABLE);
01032 }
01033
01034 /**
01035   * @brief  Disable the write protection for RTC registers.
01036   * @rmtoll WPR          KEY           LL_RTC_DisableWriteProtection
01037   * @param  RTCx RTC Instance
01038   * @retval None
01039   */
01040 __STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx)
01041 {
01042   WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_1);
01043   WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2);
01044 }
01045
01046 /**
01047   * @brief  Enable RTC_OUT remap
01048   * @rmtoll OR           OUT_RMP       LL_RTC_EnableOutRemap
01049   * @param  RTCx RTC Instance
01050   * @retval None
01051   */
01052 __STATIC_INLINE void LL_RTC_EnableOutRemap(RTC_TypeDef *RTCx)
01053 {
01054   SET_BIT(RTCx->OR, RTC_OR_OUT_RMP);
01055 }
01056
01057 /**
01058   * @brief  Disable RTC_OUT remap
01059   * @rmtoll OR           OUT_RMP       LL_RTC_DisableOutRemap
01060   * @param  RTCx RTC Instance
01061   * @retval None
01062   */
01063 __STATIC_INLINE void LL_RTC_DisableOutRemap(RTC_TypeDef *RTCx)
01064 {
01065   CLEAR_BIT(RTCx->OR, RTC_OR_OUT_RMP);
01066 }
01067
01068 /**
01069   * @}
01070   */
01071
01072 /** @defgroup RTC_LL_EF_Time Time
01073   * @{
01074   */
01075
01076 /**
01077   * @brief  Set time format (AM/24-hour or PM notation)
01078   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01079   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
01080   * @rmtoll TR           PM            LL_RTC_TIME_SetFormat
01081   * @param  RTCx RTC Instance
01082   * @param  TimeFormat This parameter can be one of the following values:
01083   *         @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
01084   *         @arg @ref LL_RTC_TIME_FORMAT_PM
01085   * @retval None
01086   */
01087 __STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
01088 {
01089   MODIFY_REG(RTCx->TR, RTC_TR_PM, TimeFormat);
01090 }
01091
01092 /**
01093   * @brief  Get time format (AM or PM notation)
01094   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01095   *       before reading this bit
01096   * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
01097   *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
01098   * @rmtoll TR           PM            LL_RTC_TIME_GetFormat
01099   * @param  RTCx RTC Instance
01100   * @retval Returned value can be one of the following values:
01101   *         @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
01102   *         @arg @ref LL_RTC_TIME_FORMAT_PM
01103   */
01104 __STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef *RTCx)
01105 {
01106   return (uint32_t)(READ_BIT(RTCx->TR, RTC_TR_PM));
01107 }
01108
01109 /**
01110   * @brief  Set Hours in BCD format
01111   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01112   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
01113   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert hour from binary to BCD format
01114   * @rmtoll TR           HT            LL_RTC_TIME_SetHour\n
01115   *         TR           HU            LL_RTC_TIME_SetHour
01116   * @param  RTCx RTC Instance
01117   * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
01118   * @retval None
01119   */
01120 __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
01121 {
01122   MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU),
01123              (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)));
01124 }
01125
01126 /**
01127   * @brief  Get Hours in BCD format
01128   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01129   *       before reading this bit
01130   * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
01131   *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
01132   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert hour from BCD to
01133   *       Binary format
01134   * @rmtoll TR           HT            LL_RTC_TIME_GetHour\n
01135   *         TR           HU            LL_RTC_TIME_GetHour
01136   * @param  RTCx RTC Instance
01137   * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
01138   */
01139 __STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx)
01140 {
01141   register uint32_t temp;
01142
01143   temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU));
01144   return (uint32_t)((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos));
01145 }
01146
01147 /**
01148   * @brief  Set Minutes in BCD format
01149   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01150   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
01151   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
01152   * @rmtoll TR           MNT           LL_RTC_TIME_SetMinute\n
01153   *         TR           MNU           LL_RTC_TIME_SetMinute
01154   * @param  RTCx RTC Instance
01155   * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
01156   * @retval None
01157   */
01158 __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
01159 {
01160   MODIFY_REG(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU),
01161              (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)));
01162 }
01163
01164 /**
01165   * @brief  Get Minutes in BCD format
01166   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01167   *       before reading this bit
01168   * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
01169   *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
01170   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert minute from BCD
01171   *       to Binary format
01172   * @rmtoll TR           MNT           LL_RTC_TIME_GetMinute\n
01173   *         TR           MNU           LL_RTC_TIME_GetMinute
01174   * @param  RTCx RTC Instance
01175   * @retval Value between Min_Data=0x00 and Max_Data=0x59
01176   */
01177 __STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx)
01178 {
01179   register uint32_t temp;
01180
01181   temp = READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU));
01182   return (uint32_t)((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos));
01183 }
01184
01185 /**
01186   * @brief  Set Seconds in BCD format
01187   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01188   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
01189   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
01190   * @rmtoll TR           ST            LL_RTC_TIME_SetSecond\n
01191   *         TR           SU            LL_RTC_TIME_SetSecond
01192   * @param  RTCx RTC Instance
01193   * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
01194   * @retval None
01195   */
01196 __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
01197 {
01198   MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU),
01199              (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos)));
01200 }
01201
01202 /**
01203   * @brief  Get Seconds in BCD format
01204   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01205   *       before reading this bit
01206   * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
01207   *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
01208   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD
01209   *       to Binary format
01210   * @rmtoll TR           ST            LL_RTC_TIME_GetSecond\n
01211   *         TR           SU            LL_RTC_TIME_GetSecond
01212   * @param  RTCx RTC Instance
01213   * @retval Value between Min_Data=0x00 and Max_Data=0x59
01214   */
01215 __STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx)
01216 {
01217   register uint32_t temp;
01218
01219   temp = READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU));
01220   return (uint32_t)((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos));
01221 }
01222
01223 /**
01224   * @brief  Set time (hour, minute and second) in BCD format
01225   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01226   * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
01227   * @note TimeFormat and Hours should follow the same format
01228   * @rmtoll TR           PM            LL_RTC_TIME_Config\n
01229   *         TR           HT            LL_RTC_TIME_Config\n
01230   *         TR           HU            LL_RTC_TIME_Config\n
01231   *         TR           MNT           LL_RTC_TIME_Config\n
01232   *         TR           MNU           LL_RTC_TIME_Config\n
01233   *         TR           ST            LL_RTC_TIME_Config\n
01234   *         TR           SU            LL_RTC_TIME_Config
01235   * @param  RTCx RTC Instance
01236   * @param  Format12_24 This parameter can be one of the following values:
01237   *         @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
01238   *         @arg @ref LL_RTC_TIME_FORMAT_PM
01239   * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
01240   * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
01241   * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
01242   * @retval None
01243   */
01244 __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
01245 {
01246   register uint32_t temp;
01247
01248   temp = Format12_24                                                                                    | \
01249          (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos))     | \
01250          (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)) | \
01251          (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos));
01252   MODIFY_REG(RTCx->TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU), temp);
01253 }
01254
01255 /**
01256   * @brief  Get time (hour, minute and second) in BCD format
01257   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01258   *       before reading this bit
01259   * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
01260   *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
01261   * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
01262   *       are available to get independently each parameter.
01263   * @rmtoll TR           HT            LL_RTC_TIME_Get\n
01264   *         TR           HU            LL_RTC_TIME_Get\n
01265   *         TR           MNT           LL_RTC_TIME_Get\n
01266   *         TR           MNU           LL_RTC_TIME_Get\n
01267   *         TR           ST            LL_RTC_TIME_Get\n
01268   *         TR           SU            LL_RTC_TIME_Get
01269   * @param  RTCx RTC Instance
01270   * @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS).
01271   */
01272 __STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx)
01273 {
01274   register uint32_t temp;
01275
01276   temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU));
01277   return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR) |  \
01278                     (((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \
01279                     ((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos)));
01280 }
01281
01282 /**
01283   * @brief  Memorize whether the daylight saving time change has been performed
01284   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01285   * @rmtoll CR           BKP           LL_RTC_TIME_EnableDayLightStore
01286   * @param  RTCx RTC Instance
01287   * @retval None
01288   */
01289 __STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore(RTC_TypeDef *RTCx)
01290 {
01291   SET_BIT(RTCx->CR, RTC_CR_BKP);
01292 }
01293
01294 /**
01295   * @brief  Disable memorization whether the daylight saving time change has been performed.
01296   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01297   * @rmtoll CR           BKP           LL_RTC_TIME_DisableDayLightStore
01298   * @param  RTCx RTC Instance
01299   * @retval None
01300   */
01301 __STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx)
01302 {
01303   CLEAR_BIT(RTCx->CR, RTC_CR_BKP);
01304 }
01305
01306 /**
01307   * @brief  Check if RTC Day Light Saving stored operation has been enabled or not
01308   * @rmtoll CR           BKP           LL_RTC_TIME_IsDayLightStoreEnabled
01309   * @param  RTCx RTC Instance
01310   * @retval State of bit (1 or 0).
01311   */
01312 __STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx)
01313 {
01314   return ((READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP)) ? 1UL : 0UL);
01315 }
01316
01317 /**
01318   * @brief  Subtract 1 hour (winter time change)
01319   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01320   * @rmtoll CR           SUB1H         LL_RTC_TIME_DecHour
01321   * @param  RTCx RTC Instance
01322   * @retval None
01323   */
01324 __STATIC_INLINE void LL_RTC_TIME_DecHour(RTC_TypeDef *RTCx)
01325 {
01326   SET_BIT(RTCx->CR, RTC_CR_SUB1H);
01327 }
01328
01329 /**
01330   * @brief  Add 1 hour (summer time change)
01331   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01332   * @rmtoll CR           ADD1H         LL_RTC_TIME_IncHour
01333   * @param  RTCx RTC Instance
01334   * @retval None
01335   */
01336 __STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx)
01337 {
01338   SET_BIT(RTCx->CR, RTC_CR_ADD1H);
01339 }
01340
01341 /**
01342   * @brief  Get Sub second value in the synchronous prescaler counter.
01343   * @note  You can use both SubSeconds value and SecondFraction (PREDIV_S through
01344   *        LL_RTC_GetSynchPrescaler function) terms returned to convert Calendar
01345   *        SubSeconds value in second fraction ratio with time unit following
01346   *        generic formula:
01347   *          ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
01348   *        This conversion can be performed only if no shift operation is pending
01349   *        (ie. SHFP=0) when PREDIV_S >= SS.
01350   * @rmtoll SSR          SS            LL_RTC_TIME_GetSubSecond
01351   * @param  RTCx RTC Instance
01352   * @retval Sub second value (number between 0 and 65535)
01353   */
01354 __STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx)
01355 {
01356   return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS));
01357 }
01358
01359 /**
01360   * @brief  Synchronize to a remote clock with a high degree of precision.
01361   * @note   This operation effectively subtracts from (delays) or advance the clock of a fraction of a second.
01362   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01363   * @note   When REFCKON is set, firmware must not write to Shift control register.
01364   * @rmtoll SHIFTR       ADD1S         LL_RTC_TIME_Synchronize\n
01365   *         SHIFTR       SUBFS         LL_RTC_TIME_Synchronize
01366   * @param  RTCx RTC Instance
01367   * @param  ShiftSecond This parameter can be one of the following values:
01368   *         @arg @ref LL_RTC_SHIFT_SECOND_DELAY
01369   *         @arg @ref LL_RTC_SHIFT_SECOND_ADVANCE
01370   * @param  Fraction Number of Seconds Fractions (any value from 0 to 0x7FFF)
01371   * @retval None
01372   */
01373 __STATIC_INLINE void LL_RTC_TIME_Synchronize(RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction)
01374 {
01375   WRITE_REG(RTCx->SHIFTR, ShiftSecond | Fraction);
01376 }
01377
01378 /**
01379   * @}
01380   */
01381
01382 /** @defgroup RTC_LL_EF_Date Date
01383   * @{
01384   */
01385
01386 /**
01387   * @brief  Set Year in BCD format
01388   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Year from binary to BCD format
01389   * @rmtoll DR           YT            LL_RTC_DATE_SetYear\n
01390   *         DR           YU            LL_RTC_DATE_SetYear
01391   * @param  RTCx RTC Instance
01392   * @param  Year Value between Min_Data=0x00 and Max_Data=0x99
01393   * @retval None
01394   */
01395 __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year)
01396 {
01397   MODIFY_REG(RTCx->DR, (RTC_DR_YT | RTC_DR_YU),
01398              (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)));
01399 }
01400
01401 /**
01402   * @brief  Get Year in BCD format
01403   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01404   *       before reading this bit
01405   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format
01406   * @rmtoll DR           YT            LL_RTC_DATE_GetYear\n
01407   *         DR           YU            LL_RTC_DATE_GetYear
01408   * @param  RTCx RTC Instance
01409   * @retval Value between Min_Data=0x00 and Max_Data=0x99
01410   */
01411 __STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx)
01412 {
01413   register uint32_t temp;
01414
01415   temp = READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU));
01416   return (uint32_t)((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos));
01417 }
01418
01419 /**
01420   * @brief  Set Week day
01421   * @rmtoll DR           WDU           LL_RTC_DATE_SetWeekDay
01422   * @param  RTCx RTC Instance
01423   * @param  WeekDay This parameter can be one of the following values:
01424   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
01425   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
01426   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
01427   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
01428   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
01429   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
01430   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
01431   * @retval None
01432   */
01433 __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
01434 {
01435   MODIFY_REG(RTCx->DR, RTC_DR_WDU, WeekDay << RTC_DR_WDU_Pos);
01436 }
01437
01438 /**
01439   * @brief  Get Week day
01440   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01441   *       before reading this bit
01442   * @rmtoll DR           WDU           LL_RTC_DATE_GetWeekDay
01443   * @param  RTCx RTC Instance
01444   * @retval Returned value can be one of the following values:
01445   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
01446   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
01447   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
01448   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
01449   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
01450   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
01451   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
01452   */
01453 __STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx)
01454 {
01455   return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos);
01456 }
01457
01458 /**
01459   * @brief  Set Month in BCD format
01460   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Month from binary to BCD format
01461   * @rmtoll DR           MT            LL_RTC_DATE_SetMonth\n
01462   *         DR           MU            LL_RTC_DATE_SetMonth
01463   * @param  RTCx RTC Instance
01464   * @param  Month This parameter can be one of the following values:
01465   *         @arg @ref LL_RTC_MONTH_JANUARY
01466   *         @arg @ref LL_RTC_MONTH_FEBRUARY
01467   *         @arg @ref LL_RTC_MONTH_MARCH
01468   *         @arg @ref LL_RTC_MONTH_APRIL
01469   *         @arg @ref LL_RTC_MONTH_MAY
01470   *         @arg @ref LL_RTC_MONTH_JUNE
01471   *         @arg @ref LL_RTC_MONTH_JULY
01472   *         @arg @ref LL_RTC_MONTH_AUGUST
01473   *         @arg @ref LL_RTC_MONTH_SEPTEMBER
01474   *         @arg @ref LL_RTC_MONTH_OCTOBER
01475   *         @arg @ref LL_RTC_MONTH_NOVEMBER
01476   *         @arg @ref LL_RTC_MONTH_DECEMBER
01477   * @retval None
01478   */
01479 __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month)
01480 {
01481   MODIFY_REG(RTCx->DR, (RTC_DR_MT | RTC_DR_MU),
01482              (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)));
01483 }
01484
01485 /**
01486   * @brief  Get Month in BCD format
01487   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01488   *       before reading this bit
01489   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
01490   * @rmtoll DR           MT            LL_RTC_DATE_GetMonth\n
01491   *         DR           MU            LL_RTC_DATE_GetMonth
01492   * @param  RTCx RTC Instance
01493   * @retval Returned value can be one of the following values:
01494   *         @arg @ref LL_RTC_MONTH_JANUARY
01495   *         @arg @ref LL_RTC_MONTH_FEBRUARY
01496   *         @arg @ref LL_RTC_MONTH_MARCH
01497   *         @arg @ref LL_RTC_MONTH_APRIL
01498   *         @arg @ref LL_RTC_MONTH_MAY
01499   *         @arg @ref LL_RTC_MONTH_JUNE
01500   *         @arg @ref LL_RTC_MONTH_JULY
01501   *         @arg @ref LL_RTC_MONTH_AUGUST
01502   *         @arg @ref LL_RTC_MONTH_SEPTEMBER
01503   *         @arg @ref LL_RTC_MONTH_OCTOBER
01504   *         @arg @ref LL_RTC_MONTH_NOVEMBER
01505   *         @arg @ref LL_RTC_MONTH_DECEMBER
01506   */
01507 __STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx)
01508 {
01509   register uint32_t temp;
01510
01511   temp = READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU));
01512   return (uint32_t)((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos));
01513 }
01514
01515 /**
01516   * @brief  Set Day in BCD format
01517   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
01518   * @rmtoll DR           DT            LL_RTC_DATE_SetDay\n
01519   *         DR           DU            LL_RTC_DATE_SetDay
01520   * @param  RTCx RTC Instance
01521   * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
01522   * @retval None
01523   */
01524 __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
01525 {
01526   MODIFY_REG(RTCx->DR, (RTC_DR_DT | RTC_DR_DU),
01527              (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos)));
01528 }
01529
01530 /**
01531   * @brief  Get Day in BCD format
01532   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01533   *       before reading this bit
01534   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
01535   * @rmtoll DR           DT            LL_RTC_DATE_GetDay\n
01536   *         DR           DU            LL_RTC_DATE_GetDay
01537   * @param  RTCx RTC Instance
01538   * @retval Value between Min_Data=0x01 and Max_Data=0x31
01539   */
01540 __STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx)
01541 {
01542   register uint32_t temp;
01543
01544   temp = READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU));
01545   return (uint32_t)((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos));
01546 }
01547
01548 /**
01549   * @brief  Set date (WeekDay, Day, Month and Year) in BCD format
01550   * @rmtoll DR           WDU           LL_RTC_DATE_Config\n
01551   *         DR           MT            LL_RTC_DATE_Config\n
01552   *         DR           MU            LL_RTC_DATE_Config\n
01553   *         DR           DT            LL_RTC_DATE_Config\n
01554   *         DR           DU            LL_RTC_DATE_Config\n
01555   *         DR           YT            LL_RTC_DATE_Config\n
01556   *         DR           YU            LL_RTC_DATE_Config
01557   * @param  RTCx RTC Instance
01558   * @param  WeekDay This parameter can be one of the following values:
01559   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
01560   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
01561   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
01562   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
01563   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
01564   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
01565   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
01566   * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
01567   * @param  Month This parameter can be one of the following values:
01568   *         @arg @ref LL_RTC_MONTH_JANUARY
01569   *         @arg @ref LL_RTC_MONTH_FEBRUARY
01570   *         @arg @ref LL_RTC_MONTH_MARCH
01571   *         @arg @ref LL_RTC_MONTH_APRIL
01572   *         @arg @ref LL_RTC_MONTH_MAY
01573   *         @arg @ref LL_RTC_MONTH_JUNE
01574   *         @arg @ref LL_RTC_MONTH_JULY
01575   *         @arg @ref LL_RTC_MONTH_AUGUST
01576   *         @arg @ref LL_RTC_MONTH_SEPTEMBER
01577   *         @arg @ref LL_RTC_MONTH_OCTOBER
01578   *         @arg @ref LL_RTC_MONTH_NOVEMBER
01579   *         @arg @ref LL_RTC_MONTH_DECEMBER
01580   * @param  Year Value between Min_Data=0x00 and Max_Data=0x99
01581   * @retval None
01582   */
01583 __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year)
01584 {
01585   register uint32_t temp;
01586
01587   temp = (WeekDay << RTC_DR_WDU_Pos)                                                        | \
01588          (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos))   | \
01589          (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)) | \
01590          (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos));
01591
01592   MODIFY_REG(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU), temp);
01593 }
01594
01595 /**
01596   * @brief  Get date (WeekDay, Day, Month and Year) in BCD format
01597   * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
01598   *       before reading this bit
01599   * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH,
01600   * and __LL_RTC_GET_DAY are available to get independently each parameter.
01601   * @rmtoll DR           WDU           LL_RTC_DATE_Get\n
01602   *         DR           MT            LL_RTC_DATE_Get\n
01603   *         DR           MU            LL_RTC_DATE_Get\n
01604   *         DR           DT            LL_RTC_DATE_Get\n
01605   *         DR           DU            LL_RTC_DATE_Get\n
01606   *         DR           YT            LL_RTC_DATE_Get\n
01607   *         DR           YU            LL_RTC_DATE_Get
01608   * @param  RTCx RTC Instance
01609   * @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY).
01610   */
01611 __STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx)
01612 {
01613   register uint32_t temp;
01614
01615   temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU));
01616   return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \
01617                     (((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)) << RTC_OFFSET_DAY) | \
01618                     (((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)) << RTC_OFFSET_MONTH) | \
01619                     ((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos)));
01620 }
01621
01622 /**
01623   * @}
01624   */
01625
01626 /** @defgroup RTC_LL_EF_ALARMA ALARMA
01627   * @{
01628   */
01629
01630 /**
01631   * @brief  Enable Alarm A
01632   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01633   * @rmtoll CR           ALRAE         LL_RTC_ALMA_Enable
01634   * @param  RTCx RTC Instance
01635   * @retval None
01636   */
01637 __STATIC_INLINE void LL_RTC_ALMA_Enable(RTC_TypeDef *RTCx)
01638 {
01639   SET_BIT(RTCx->CR, RTC_CR_ALRAE);
01640 }
01641
01642 /**
01643   * @brief  Disable Alarm A
01644   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
01645   * @rmtoll CR           ALRAE         LL_RTC_ALMA_Disable
01646   * @param  RTCx RTC Instance
01647   * @retval None
01648   */
01649 __STATIC_INLINE void LL_RTC_ALMA_Disable(RTC_TypeDef *RTCx)
01650 {
01651   CLEAR_BIT(RTCx->CR, RTC_CR_ALRAE);
01652 }
01653
01654 /**
01655   * @brief  Specify the Alarm A masks.
01656   * @rmtoll ALRMAR       MSK4          LL_RTC_ALMA_SetMask\n
01657   *         ALRMAR       MSK3          LL_RTC_ALMA_SetMask\n
01658   *         ALRMAR       MSK2          LL_RTC_ALMA_SetMask\n
01659   *         ALRMAR       MSK1          LL_RTC_ALMA_SetMask
01660   * @param  RTCx RTC Instance
01661   * @param  Mask This parameter can be a combination of the following values:
01662   *         @arg @ref LL_RTC_ALMA_MASK_NONE
01663   *         @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY
01664   *         @arg @ref LL_RTC_ALMA_MASK_HOURS
01665   *         @arg @ref LL_RTC_ALMA_MASK_MINUTES
01666   *         @arg @ref LL_RTC_ALMA_MASK_SECONDS
01667   *         @arg @ref LL_RTC_ALMA_MASK_ALL
01668   * @retval None
01669   */
01670 __STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
01671 {
01672   MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1, Mask);
01673 }
01674
01675 /**
01676   * @brief  Get the Alarm A masks.
01677   * @rmtoll ALRMAR       MSK4          LL_RTC_ALMA_GetMask\n
01678   *         ALRMAR       MSK3          LL_RTC_ALMA_GetMask\n
01679   *         ALRMAR       MSK2          LL_RTC_ALMA_GetMask\n
01680   *         ALRMAR       MSK1          LL_RTC_ALMA_GetMask
01681   * @param  RTCx RTC Instance
01682   * @retval Returned value can be can be a combination of the following values:
01683   *         @arg @ref LL_RTC_ALMA_MASK_NONE
01684   *         @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY
01685   *         @arg @ref LL_RTC_ALMA_MASK_HOURS
01686   *         @arg @ref LL_RTC_ALMA_MASK_MINUTES
01687   *         @arg @ref LL_RTC_ALMA_MASK_SECONDS
01688   *         @arg @ref LL_RTC_ALMA_MASK_ALL
01689   */
01690 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(RTC_TypeDef *RTCx)
01691 {
01692   return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1));
01693 }
01694
01695 /**
01696   * @brief  Enable AlarmA Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)
01697   * @rmtoll ALRMAR       WDSEL         LL_RTC_ALMA_EnableWeekday
01698   * @param  RTCx RTC Instance
01699   * @retval None
01700   */
01701 __STATIC_INLINE void LL_RTC_ALMA_EnableWeekday(RTC_TypeDef *RTCx)
01702 {
01703   SET_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
01704 }
01705
01706 /**
01707   * @brief  Disable AlarmA Week day selection (DU[3:0] represents the date )
01708   * @rmtoll ALRMAR       WDSEL         LL_RTC_ALMA_DisableWeekday
01709   * @param  RTCx RTC Instance
01710   * @retval None
01711   */
01712 __STATIC_INLINE void LL_RTC_ALMA_DisableWeekday(RTC_TypeDef *RTCx)
01713 {
01714   CLEAR_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
01715 }
01716
01717 /**
01718   * @brief  Set ALARM A Day in BCD format
01719   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
01720   * @rmtoll ALRMAR       DT            LL_RTC_ALMA_SetDay\n
01721   *         ALRMAR       DU            LL_RTC_ALMA_SetDay
01722   * @param  RTCx RTC Instance
01723   * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
01724   * @retval None
01725   */
01726 __STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
01727 {
01728   MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU),
01729              (((Day & 0xF0U) << (RTC_ALRMAR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMAR_DU_Pos)));
01730 }
01731
01732 /**
01733   * @brief  Get ALARM A Day in BCD format
01734   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
01735   * @rmtoll ALRMAR       DT            LL_RTC_ALMA_GetDay\n
01736   *         ALRMAR       DU            LL_RTC_ALMA_GetDay
01737   * @param  RTCx RTC Instance
01738   * @retval Value between Min_Data=0x01 and Max_Data=0x31
01739   */
01740 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx)
01741 {
01742   register uint32_t temp;
01743
01744   temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU));
01745   return (uint32_t)((((temp & RTC_ALRMAR_DT) >> RTC_ALRMAR_DT_Pos) << 4U) | ((temp & RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos));
01746 }
01747
01748 /**
01749   * @brief  Set ALARM A Weekday
01750   * @rmtoll ALRMAR       DU            LL_RTC_ALMA_SetWeekDay
01751   * @param  RTCx RTC Instance
01752   * @param  WeekDay This parameter can be one of the following values:
01753   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
01754   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
01755   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
01756   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
01757   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
01758   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
01759   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
01760   * @retval None
01761   */
01762 __STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
01763 {
01764   MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_DU, WeekDay << RTC_ALRMAR_DU_Pos);
01765 }
01766
01767 /**
01768   * @brief  Get ALARM A Weekday
01769   * @rmtoll ALRMAR       DU            LL_RTC_ALMA_GetWeekDay
01770   * @param  RTCx RTC Instance
01771   * @retval Returned value can be one of the following values:
01772   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
01773   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
01774   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
01775   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
01776   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
01777   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
01778   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
01779   */
01780 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx)
01781 {
01782   return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos);
01783 }
01784
01785 /**
01786   * @brief  Set Alarm A time format (AM/24-hour or PM notation)
01787   * @rmtoll ALRMAR       PM            LL_RTC_ALMA_SetTimeFormat
01788   * @param  RTCx RTC Instance
01789   * @param  TimeFormat This parameter can be one of the following values:
01790   *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
01791   *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
01792   * @retval None
01793   */
01794 __STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
01795 {
01796   MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM, TimeFormat);
01797 }
01798
01799 /**
01800   * @brief  Get Alarm A time format (AM or PM notation)
01801   * @rmtoll ALRMAR       PM            LL_RTC_ALMA_GetTimeFormat
01802   * @param  RTCx RTC Instance
01803   * @retval Returned value can be one of the following values:
01804   *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
01805   *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
01806   */
01807 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef *RTCx)
01808 {
01809   return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_PM));
01810 }
01811
01812 /**
01813   * @brief  Set ALARM A Hours in BCD format
01814   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
01815   * @rmtoll ALRMAR       HT            LL_RTC_ALMA_SetHour\n
01816   *         ALRMAR       HU            LL_RTC_ALMA_SetHour
01817   * @param  RTCx RTC Instance
01818   * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
01819   * @retval None
01820   */
01821 __STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
01822 {
01823   MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU),
01824              (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)));
01825 }
01826
01827 /**
01828   * @brief  Get ALARM A Hours in BCD format
01829   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
01830   * @rmtoll ALRMAR       HT            LL_RTC_ALMA_GetHour\n
01831   *         ALRMAR       HU            LL_RTC_ALMA_GetHour
01832   * @param  RTCx RTC Instance
01833   * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
01834   */
01835 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx)
01836 {
01837   register uint32_t temp;
01838
01839   temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU));
01840   return (uint32_t)((((temp & RTC_ALRMAR_HT) >> RTC_ALRMAR_HT_Pos) << 4U) | ((temp & RTC_ALRMAR_HU) >> RTC_ALRMAR_HU_Pos));
01841 }
01842
01843 /**
01844   * @brief  Set ALARM A Minutes in BCD format
01845   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
01846   * @rmtoll ALRMAR       MNT           LL_RTC_ALMA_SetMinute\n
01847   *         ALRMAR       MNU           LL_RTC_ALMA_SetMinute
01848   * @param  RTCx RTC Instance
01849   * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
01850   * @retval None
01851   */
01852 __STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
01853 {
01854   MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU),
01855              (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)));
01856 }
01857
01858 /**
01859   * @brief  Get ALARM A Minutes in BCD format
01860   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
01861   * @rmtoll ALRMAR       MNT           LL_RTC_ALMA_GetMinute\n
01862   *         ALRMAR       MNU           LL_RTC_ALMA_GetMinute
01863   * @param  RTCx RTC Instance
01864   * @retval Value between Min_Data=0x00 and Max_Data=0x59
01865   */
01866 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx)
01867 {
01868   register uint32_t temp;
01869
01870   temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU));
01871   return (uint32_t)((((temp & RTC_ALRMAR_MNT) >> RTC_ALRMAR_MNT_Pos) << 4U) | ((temp & RTC_ALRMAR_MNU) >> RTC_ALRMAR_MNU_Pos));
01872 }
01873
01874 /**
01875   * @brief  Set ALARM A Seconds in BCD format
01876   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
01877   * @rmtoll ALRMAR       ST            LL_RTC_ALMA_SetSecond\n
01878   *         ALRMAR       SU            LL_RTC_ALMA_SetSecond
01879   * @param  RTCx RTC Instance
01880   * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
01881   * @retval None
01882   */
01883 __STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
01884 {
01885   MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU),
01886              (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos)));
01887 }
01888
01889 /**
01890   * @brief  Get ALARM A Seconds in BCD format
01891   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
01892   * @rmtoll ALRMAR       ST            LL_RTC_ALMA_GetSecond\n
01893   *         ALRMAR       SU            LL_RTC_ALMA_GetSecond
01894   * @param  RTCx RTC Instance
01895   * @retval Value between Min_Data=0x00 and Max_Data=0x59
01896   */
01897 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx)
01898 {
01899   register uint32_t temp;
01900
01901   temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
01902   return (uint32_t)((((temp & RTC_ALRMAR_ST) >> RTC_ALRMAR_ST_Pos) << 4U) | ((temp & RTC_ALRMAR_SU) >> RTC_ALRMAR_SU_Pos));
01903 }
01904
01905 /**
01906   * @brief  Set Alarm A Time (hour, minute and second) in BCD format
01907   * @rmtoll ALRMAR       PM            LL_RTC_ALMA_ConfigTime\n
01908   *         ALRMAR       HT            LL_RTC_ALMA_ConfigTime\n
01909   *         ALRMAR       HU            LL_RTC_ALMA_ConfigTime\n
01910   *         ALRMAR       MNT           LL_RTC_ALMA_ConfigTime\n
01911   *         ALRMAR       MNU           LL_RTC_ALMA_ConfigTime\n
01912   *         ALRMAR       ST            LL_RTC_ALMA_ConfigTime\n
01913   *         ALRMAR       SU            LL_RTC_ALMA_ConfigTime
01914   * @param  RTCx RTC Instance
01915   * @param  Format12_24 This parameter can be one of the following values:
01916   *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
01917   *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
01918   * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
01919   * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
01920   * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
01921   * @retval None
01922   */
01923 __STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
01924 {
01925   register uint32_t temp;
01926
01927   temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos))    | \
01928          (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \
01929          (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos));
01930
01931   MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | RTC_ALRMAR_ST | RTC_ALRMAR_SU, temp);
01932 }
01933
01934 /**
01935   * @brief  Get Alarm B Time (hour, minute and second) in BCD format
01936   * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
01937   * are available to get independently each parameter.
01938   * @rmtoll ALRMAR       HT            LL_RTC_ALMA_GetTime\n
01939   *         ALRMAR       HU            LL_RTC_ALMA_GetTime\n
01940   *         ALRMAR       MNT           LL_RTC_ALMA_GetTime\n
01941   *         ALRMAR       MNU           LL_RTC_ALMA_GetTime\n
01942   *         ALRMAR       ST            LL_RTC_ALMA_GetTime\n
01943   *         ALRMAR       SU            LL_RTC_ALMA_GetTime
01944   * @param  RTCx RTC Instance
01945   * @retval Combination of hours, minutes and seconds.
01946   */
01947 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(RTC_TypeDef *RTCx)
01948 {
01949   return (uint32_t)((LL_RTC_ALMA_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMA_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMA_GetSecond(RTCx));
01950 }
01951
01952 /**
01953   * @brief  Set Alarm A Mask the most-significant bits starting at this bit
01954   * @note This register can be written only when ALRAE is reset in RTC_CR register,
01955   *       or in initialization mode.
01956   * @rmtoll ALRMASSR     MASKSS        LL_RTC_ALMA_SetSubSecondMask
01957   * @param  RTCx RTC Instance
01958   * @param  Mask Value between Min_Data=0x00 and Max_Data=0xF
01959   * @retval None
01960   */
01961 __STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
01962 {
01963   MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS, Mask << RTC_ALRMASSR_MASKSS_Pos);
01964 }
01965
01966 /**
01967   * @brief  Get Alarm A Mask the most-significant bits starting at this bit
01968   * @rmtoll ALRMASSR     MASKSS        LL_RTC_ALMA_GetSubSecondMask
01969   * @param  RTCx RTC Instance
01970   * @retval Value between Min_Data=0x00 and Max_Data=0xF
01971   */
01972 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx)
01973 {
01974   return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos);
01975 }
01976
01977 /**
01978   * @brief  Set Alarm A Sub seconds value
01979   * @rmtoll ALRMASSR     SS            LL_RTC_ALMA_SetSubSecond
01980   * @param  RTCx RTC Instance
01981   * @param  Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF
01982   * @retval None
01983   */
01984 __STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)
01985 {
01986   MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_SS, Subsecond);
01987 }
01988
01989 /**
01990   * @brief  Get Alarm A Sub seconds value
01991   * @rmtoll ALRMASSR     SS            LL_RTC_ALMA_GetSubSecond
01992   * @param  RTCx RTC Instance
01993   * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF
01994   */
01995 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(RTC_TypeDef *RTCx)
01996 {
01997   return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SS));
01998 }
01999
02000 /**
02001   * @}
02002   */
02003
02004 /** @defgroup RTC_LL_EF_ALARMB ALARMB
02005   * @{
02006   */
02007
02008 /**
02009   * @brief  Enable Alarm B
02010   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02011   * @rmtoll CR           ALRBE         LL_RTC_ALMB_Enable
02012   * @param  RTCx RTC Instance
02013   * @retval None
02014   */
02015 __STATIC_INLINE void LL_RTC_ALMB_Enable(RTC_TypeDef *RTCx)
02016 {
02017   SET_BIT(RTCx->CR, RTC_CR_ALRBE);
02018 }
02019
02020 /**
02021   * @brief  Disable Alarm B
02022   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02023   * @rmtoll CR           ALRBE         LL_RTC_ALMB_Disable
02024   * @param  RTCx RTC Instance
02025   * @retval None
02026   */
02027 __STATIC_INLINE void LL_RTC_ALMB_Disable(RTC_TypeDef *RTCx)
02028 {
02029   CLEAR_BIT(RTCx->CR, RTC_CR_ALRBE);
02030 }
02031
02032 /**
02033   * @brief  Specify the Alarm B masks.
02034   * @rmtoll ALRMBR       MSK4          LL_RTC_ALMB_SetMask\n
02035   *         ALRMBR       MSK3          LL_RTC_ALMB_SetMask\n
02036   *         ALRMBR       MSK2          LL_RTC_ALMB_SetMask\n
02037   *         ALRMBR       MSK1          LL_RTC_ALMB_SetMask
02038   * @param  RTCx RTC Instance
02039   * @param  Mask This parameter can be a combination of the following values:
02040   *         @arg @ref LL_RTC_ALMB_MASK_NONE
02041   *         @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY
02042   *         @arg @ref LL_RTC_ALMB_MASK_HOURS
02043   *         @arg @ref LL_RTC_ALMB_MASK_MINUTES
02044   *         @arg @ref LL_RTC_ALMB_MASK_SECONDS
02045   *         @arg @ref LL_RTC_ALMB_MASK_ALL
02046   * @retval None
02047   */
02048 __STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
02049 {
02050   MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1, Mask);
02051 }
02052
02053 /**
02054   * @brief  Get the Alarm B masks.
02055   * @rmtoll ALRMBR       MSK4          LL_RTC_ALMB_GetMask\n
02056   *         ALRMBR       MSK3          LL_RTC_ALMB_GetMask\n
02057   *         ALRMBR       MSK2          LL_RTC_ALMB_GetMask\n
02058   *         ALRMBR       MSK1          LL_RTC_ALMB_GetMask
02059   * @param  RTCx RTC Instance
02060   * @retval Returned value can be can be a combination of the following values:
02061   *         @arg @ref LL_RTC_ALMB_MASK_NONE
02062   *         @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY
02063   *         @arg @ref LL_RTC_ALMB_MASK_HOURS
02064   *         @arg @ref LL_RTC_ALMB_MASK_MINUTES
02065   *         @arg @ref LL_RTC_ALMB_MASK_SECONDS
02066   *         @arg @ref LL_RTC_ALMB_MASK_ALL
02067   */
02068 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(RTC_TypeDef *RTCx)
02069 {
02070   return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1));
02071 }
02072
02073 /**
02074   * @brief  Enable AlarmB Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)
02075   * @rmtoll ALRMBR       WDSEL         LL_RTC_ALMB_EnableWeekday
02076   * @param  RTCx RTC Instance
02077   * @retval None
02078   */
02079 __STATIC_INLINE void LL_RTC_ALMB_EnableWeekday(RTC_TypeDef *RTCx)
02080 {
02081   SET_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
02082 }
02083
02084 /**
02085   * @brief  Disable AlarmB Week day selection (DU[3:0] represents the date )
02086   * @rmtoll ALRMBR       WDSEL         LL_RTC_ALMB_DisableWeekday
02087   * @param  RTCx RTC Instance
02088   * @retval None
02089   */
02090 __STATIC_INLINE void LL_RTC_ALMB_DisableWeekday(RTC_TypeDef *RTCx)
02091 {
02092   CLEAR_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
02093 }
02094
02095 /**
02096   * @brief  Set ALARM B Day in BCD format
02097   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
02098   * @rmtoll ALRMBR       DT            LL_RTC_ALMB_SetDay\n
02099   *         ALRMBR       DU            LL_RTC_ALMB_SetDay
02100   * @param  RTCx RTC Instance
02101   * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
02102   * @retval None
02103   */
02104 __STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
02105 {
02106   MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU),
02107              (((Day & 0xF0U) << (RTC_ALRMBR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMBR_DU_Pos)));
02108 }
02109
02110 /**
02111   * @brief  Get ALARM B Day in BCD format
02112   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
02113   * @rmtoll ALRMBR       DT            LL_RTC_ALMB_GetDay\n
02114   *         ALRMBR       DU            LL_RTC_ALMB_GetDay
02115   * @param  RTCx RTC Instance
02116   * @retval Value between Min_Data=0x01 and Max_Data=0x31
02117   */
02118 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx)
02119 {
02120   register uint32_t temp;
02121
02122   temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU));
02123   return (uint32_t)((((temp & RTC_ALRMBR_DT) >> RTC_ALRMBR_DT_Pos) << 4U) | ((temp & RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos));
02124 }
02125
02126 /**
02127   * @brief  Set ALARM B Weekday
02128   * @rmtoll ALRMBR       DU            LL_RTC_ALMB_SetWeekDay
02129   * @param  RTCx RTC Instance
02130   * @param  WeekDay This parameter can be one of the following values:
02131   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
02132   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
02133   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
02134   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
02135   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
02136   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
02137   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
02138   * @retval None
02139   */
02140 __STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
02141 {
02142   MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_DU, WeekDay << RTC_ALRMBR_DU_Pos);
02143 }
02144
02145 /**
02146   * @brief  Get ALARM B Weekday
02147   * @rmtoll ALRMBR       DU            LL_RTC_ALMB_GetWeekDay
02148   * @param  RTCx RTC Instance
02149   * @retval Returned value can be one of the following values:
02150   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
02151   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
02152   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
02153   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
02154   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
02155   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
02156   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
02157   */
02158 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef *RTCx)
02159 {
02160   return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos);
02161 }
02162
02163 /**
02164   * @brief  Set ALARM B time format (AM/24-hour or PM notation)
02165   * @rmtoll ALRMBR       PM            LL_RTC_ALMB_SetTimeFormat
02166   * @param  RTCx RTC Instance
02167   * @param  TimeFormat This parameter can be one of the following values:
02168   *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
02169   *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
02170   * @retval None
02171   */
02172 __STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
02173 {
02174   MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM, TimeFormat);
02175 }
02176
02177 /**
02178   * @brief  Get ALARM B time format (AM or PM notation)
02179   * @rmtoll ALRMBR       PM            LL_RTC_ALMB_GetTimeFormat
02180   * @param  RTCx RTC Instance
02181   * @retval Returned value can be one of the following values:
02182   *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
02183   *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
02184   */
02185 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(RTC_TypeDef *RTCx)
02186 {
02187   return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_PM));
02188 }
02189
02190 /**
02191   * @brief  Set ALARM B Hours in BCD format
02192   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
02193   * @rmtoll ALRMBR       HT            LL_RTC_ALMB_SetHour\n
02194   *         ALRMBR       HU            LL_RTC_ALMB_SetHour
02195   * @param  RTCx RTC Instance
02196   * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
02197   * @retval None
02198   */
02199 __STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
02200 {
02201   MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU),
02202              (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)));
02203 }
02204
02205 /**
02206   * @brief  Get ALARM B Hours in BCD format
02207   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
02208   * @rmtoll ALRMBR       HT            LL_RTC_ALMB_GetHour\n
02209   *         ALRMBR       HU            LL_RTC_ALMB_GetHour
02210   * @param  RTCx RTC Instance
02211   * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
02212   */
02213 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx)
02214 {
02215   register uint32_t temp;
02216
02217   temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU));
02218   return (uint32_t)((((temp & RTC_ALRMBR_HT) >> RTC_ALRMBR_HT_Pos) << 4U) | ((temp & RTC_ALRMBR_HU) >> RTC_ALRMBR_HU_Pos));
02219 }
02220
02221 /**
02222   * @brief  Set ALARM B Minutes in BCD format
02223   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
02224   * @rmtoll ALRMBR       MNT           LL_RTC_ALMB_SetMinute\n
02225   *         ALRMBR       MNU           LL_RTC_ALMB_SetMinute
02226   * @param  RTCx RTC Instance
02227   * @param  Minutes between Min_Data=0x00 and Max_Data=0x59
02228   * @retval None
02229   */
02230 __STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
02231 {
02232   MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU),
02233              (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)));
02234 }
02235
02236 /**
02237   * @brief  Get ALARM B Minutes in BCD format
02238   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
02239   * @rmtoll ALRMBR       MNT           LL_RTC_ALMB_GetMinute\n
02240   *         ALRMBR       MNU           LL_RTC_ALMB_GetMinute
02241   * @param  RTCx RTC Instance
02242   * @retval Value between Min_Data=0x00 and Max_Data=0x59
02243   */
02244 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx)
02245 {
02246   register uint32_t temp;
02247
02248   temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU));
02249   return (uint32_t)((((temp & RTC_ALRMBR_MNT) >> RTC_ALRMBR_MNT_Pos) << 4U) | ((temp & RTC_ALRMBR_MNU) >> RTC_ALRMBR_MNU_Pos));
02250 }
02251
02252 /**
02253   * @brief  Set ALARM B Seconds in BCD format
02254   * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
02255   * @rmtoll ALRMBR       ST            LL_RTC_ALMB_SetSecond\n
02256   *         ALRMBR       SU            LL_RTC_ALMB_SetSecond
02257   * @param  RTCx RTC Instance
02258   * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
02259   * @retval None
02260   */
02261 __STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
02262 {
02263   MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU),
02264              (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos)));
02265 }
02266
02267 /**
02268   * @brief  Get ALARM B Seconds in BCD format
02269   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
02270   * @rmtoll ALRMBR       ST            LL_RTC_ALMB_GetSecond\n
02271   *         ALRMBR       SU            LL_RTC_ALMB_GetSecond
02272   * @param  RTCx RTC Instance
02273   * @retval Value between Min_Data=0x00 and Max_Data=0x59
02274   */
02275 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx)
02276 {
02277   register uint32_t temp;
02278
02279   temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU));
02280   return (uint32_t)((((temp & RTC_ALRMBR_ST) >> RTC_ALRMBR_ST_Pos) << 4U) | ((temp & RTC_ALRMBR_SU) >> RTC_ALRMBR_SU_Pos));
02281 }
02282
02283 /**
02284   * @brief  Set Alarm B Time (hour, minute and second) in BCD format
02285   * @rmtoll ALRMBR       PM            LL_RTC_ALMB_ConfigTime\n
02286   *         ALRMBR       HT            LL_RTC_ALMB_ConfigTime\n
02287   *         ALRMBR       HU            LL_RTC_ALMB_ConfigTime\n
02288   *         ALRMBR       MNT           LL_RTC_ALMB_ConfigTime\n
02289   *         ALRMBR       MNU           LL_RTC_ALMB_ConfigTime\n
02290   *         ALRMBR       ST            LL_RTC_ALMB_ConfigTime\n
02291   *         ALRMBR       SU            LL_RTC_ALMB_ConfigTime
02292   * @param  RTCx RTC Instance
02293   * @param  Format12_24 This parameter can be one of the following values:
02294   *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
02295   *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
02296   * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
02297   * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
02298   * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
02299   * @retval None
02300   */
02301 __STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
02302 {
02303   register uint32_t temp;
02304
02305   temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos))    | \
02306          (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \
02307          (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos));
02308
02309   MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM| RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | RTC_ALRMBR_ST | RTC_ALRMBR_SU, temp);
02310 }
02311
02312 /**
02313   * @brief  Get Alarm B Time (hour, minute and second) in BCD format
02314   * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
02315   * are available to get independently each parameter.
02316   * @rmtoll ALRMBR       HT            LL_RTC_ALMB_GetTime\n
02317   *         ALRMBR       HU            LL_RTC_ALMB_GetTime\n
02318   *         ALRMBR       MNT           LL_RTC_ALMB_GetTime\n
02319   *         ALRMBR       MNU           LL_RTC_ALMB_GetTime\n
02320   *         ALRMBR       ST            LL_RTC_ALMB_GetTime\n
02321   *         ALRMBR       SU            LL_RTC_ALMB_GetTime
02322   * @param  RTCx RTC Instance
02323   * @retval Combination of hours, minutes and seconds.
02324   */
02325 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime(RTC_TypeDef *RTCx)
02326 {
02327   return (uint32_t)((LL_RTC_ALMB_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMB_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMB_GetSecond(RTCx));
02328 }
02329
02330 /**
02331   * @brief  Set Alarm B Mask the most-significant bits starting at this bit
02332   * @note This register can be written only when ALRBE is reset in RTC_CR register,
02333   *       or in initialization mode.
02334   * @rmtoll ALRMBSSR     MASKSS        LL_RTC_ALMB_SetSubSecondMask
02335   * @param  RTCx RTC Instance
02336   * @param  Mask Value between Min_Data=0x00 and Max_Data=0xF
02337   * @retval None
02338   */
02339 __STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
02340 {
02341   MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS, Mask << RTC_ALRMBSSR_MASKSS_Pos);
02342 }
02343
02344 /**
02345   * @brief  Get Alarm B Mask the most-significant bits starting at this bit
02346   * @rmtoll ALRMBSSR     MASKSS        LL_RTC_ALMB_GetSubSecondMask
02347   * @param  RTCx RTC Instance
02348   * @retval Value between Min_Data=0x00 and Max_Data=0xF
02349   */
02350 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef *RTCx)
02351 {
02352   return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS)  >> RTC_ALRMBSSR_MASKSS_Pos);
02353 }
02354
02355 /**
02356   * @brief  Set Alarm B Sub seconds value
02357   * @rmtoll ALRMBSSR     SS            LL_RTC_ALMB_SetSubSecond
02358   * @param  RTCx RTC Instance
02359   * @param  Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF
02360   * @retval None
02361   */
02362 __STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)
02363 {
02364   MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS, Subsecond);
02365 }
02366
02367 /**
02368   * @brief  Get Alarm B Sub seconds value
02369   * @rmtoll ALRMBSSR     SS            LL_RTC_ALMB_GetSubSecond
02370   * @param  RTCx RTC Instance
02371   * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF
02372   */
02373 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(RTC_TypeDef *RTCx)
02374 {
02375   return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS));
02376 }
02377
02378 /**
02379   * @}
02380   */
02381
02382 /** @defgroup RTC_LL_EF_Timestamp Timestamp
02383   * @{
02384   */
02385
02386 /**
02387   * @brief  Enable internal event timestamp
02388   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02389   * @rmtoll CR           ITSE          LL_RTC_TS_EnableInternalEvent
02390   * @param  RTCx RTC Instance
02391   * @retval None
02392   */
02393 __STATIC_INLINE void LL_RTC_TS_EnableInternalEvent(RTC_TypeDef *RTCx)
02394 {
02395   SET_BIT(RTCx->CR, RTC_CR_ITSE);
02396 }
02397
02398 /**
02399   * @brief  Disable internal event timestamp
02400   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02401   * @rmtoll CR           ITSE          LL_RTC_TS_DisableInternalEvent
02402   * @param  RTCx RTC Instance
02403   * @retval None
02404   */
02405 __STATIC_INLINE void LL_RTC_TS_DisableInternalEvent(RTC_TypeDef *RTCx)
02406 {
02407   CLEAR_BIT(RTCx->CR, RTC_CR_ITSE);
02408 }
02409
02410 /**
02411   * @brief  Enable Timestamp
02412   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02413   * @rmtoll CR           TSE           LL_RTC_TS_Enable
02414   * @param  RTCx RTC Instance
02415   * @retval None
02416   */
02417 __STATIC_INLINE void LL_RTC_TS_Enable(RTC_TypeDef *RTCx)
02418 {
02419   SET_BIT(RTCx->CR, RTC_CR_TSE);
02420 }
02421
02422 /**
02423   * @brief  Disable Timestamp
02424   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02425   * @rmtoll CR           TSE           LL_RTC_TS_Disable
02426   * @param  RTCx RTC Instance
02427   * @retval None
02428   */
02429 __STATIC_INLINE void LL_RTC_TS_Disable(RTC_TypeDef *RTCx)
02430 {
02431   CLEAR_BIT(RTCx->CR, RTC_CR_TSE);
02432 }
02433
02434 /**
02435   * @brief  Set Time-stamp event active edge
02436   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02437   * @note TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting
02438   * @rmtoll CR           TSEDGE        LL_RTC_TS_SetActiveEdge
02439   * @param  RTCx RTC Instance
02440   * @param  Edge This parameter can be one of the following values:
02441   *         @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
02442   *         @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING
02443   * @retval None
02444   */
02445 __STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge)
02446 {
02447   MODIFY_REG(RTCx->CR, RTC_CR_TSEDGE, Edge);
02448 }
02449
02450 /**
02451   * @brief  Get Time-stamp event active edge
02452   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02453   * @rmtoll CR           TSEDGE        LL_RTC_TS_GetActiveEdge
02454   * @param  RTCx RTC Instance
02455   * @retval Returned value can be one of the following values:
02456   *         @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
02457   *         @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING
02458   */
02459 __STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx)
02460 {
02461   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TSEDGE));
02462 }
02463
02464 /**
02465   * @brief  Get Timestamp AM/PM notation (AM or 24-hour format)
02466   * @rmtoll TSTR         PM            LL_RTC_TS_GetTimeFormat
02467   * @param  RTCx RTC Instance
02468   * @retval Returned value can be one of the following values:
02469   *         @arg @ref LL_RTC_TS_TIME_FORMAT_AM
02470   *         @arg @ref LL_RTC_TS_TIME_FORMAT_PM
02471   */
02472 __STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx)
02473 {
02474   return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_PM));
02475 }
02476
02477 /**
02478   * @brief  Get Timestamp Hours in BCD format
02479   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
02480   * @rmtoll TSTR         HT            LL_RTC_TS_GetHour\n
02481   *         TSTR         HU            LL_RTC_TS_GetHour
02482   * @param  RTCx RTC Instance
02483   * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
02484   */
02485 __STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx)
02486 {
02487   return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos);
02488 }
02489
02490 /**
02491   * @brief  Get Timestamp Minutes in BCD format
02492   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
02493   * @rmtoll TSTR         MNT           LL_RTC_TS_GetMinute\n
02494   *         TSTR         MNU           LL_RTC_TS_GetMinute
02495   * @param  RTCx RTC Instance
02496   * @retval Value between Min_Data=0x00 and Max_Data=0x59
02497   */
02498 __STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx)
02499 {
02500   return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos);
02501 }
02502
02503 /**
02504   * @brief  Get Timestamp Seconds in BCD format
02505   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
02506   * @rmtoll TSTR         ST            LL_RTC_TS_GetSecond\n
02507   *         TSTR         SU            LL_RTC_TS_GetSecond
02508   * @param  RTCx RTC Instance
02509   * @retval Value between Min_Data=0x00 and Max_Data=0x59
02510   */
02511 __STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx)
02512 {
02513   return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_ST | RTC_TSTR_SU));
02514 }
02515
02516 /**
02517   * @brief  Get Timestamp time (hour, minute and second) in BCD format
02518   * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
02519   * are available to get independently each parameter.
02520   * @rmtoll TSTR         HT            LL_RTC_TS_GetTime\n
02521   *         TSTR         HU            LL_RTC_TS_GetTime\n
02522   *         TSTR         MNT           LL_RTC_TS_GetTime\n
02523   *         TSTR         MNU           LL_RTC_TS_GetTime\n
02524   *         TSTR         ST            LL_RTC_TS_GetTime\n
02525   *         TSTR         SU            LL_RTC_TS_GetTime
02526   * @param  RTCx RTC Instance
02527   * @retval Combination of hours, minutes and seconds.
02528   */
02529 __STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx)
02530 {
02531   return (uint32_t)(READ_BIT(RTCx->TSTR,
02532                              RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT | RTC_TSTR_MNU | RTC_TSTR_ST | RTC_TSTR_SU));
02533 }
02534
02535 /**
02536   * @brief  Get Timestamp Week day
02537   * @rmtoll TSDR         WDU           LL_RTC_TS_GetWeekDay
02538   * @param  RTCx RTC Instance
02539   * @retval Returned value can be one of the following values:
02540   *         @arg @ref LL_RTC_WEEKDAY_MONDAY
02541   *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
02542   *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
02543   *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
02544   *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
02545   *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
02546   *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
02547   */
02548 __STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx)
02549 {
02550   return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos);
02551 }
02552
02553 /**
02554   * @brief  Get Timestamp Month in BCD format
02555   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
02556   * @rmtoll TSDR         MT            LL_RTC_TS_GetMonth\n
02557   *         TSDR         MU            LL_RTC_TS_GetMonth
02558   * @param  RTCx RTC Instance
02559   * @retval Returned value can be one of the following values:
02560   *         @arg @ref LL_RTC_MONTH_JANUARY
02561   *         @arg @ref LL_RTC_MONTH_FEBRUARY
02562   *         @arg @ref LL_RTC_MONTH_MARCH
02563   *         @arg @ref LL_RTC_MONTH_APRIL
02564   *         @arg @ref LL_RTC_MONTH_MAY
02565   *         @arg @ref LL_RTC_MONTH_JUNE
02566   *         @arg @ref LL_RTC_MONTH_JULY
02567   *         @arg @ref LL_RTC_MONTH_AUGUST
02568   *         @arg @ref LL_RTC_MONTH_SEPTEMBER
02569   *         @arg @ref LL_RTC_MONTH_OCTOBER
02570   *         @arg @ref LL_RTC_MONTH_NOVEMBER
02571   *         @arg @ref LL_RTC_MONTH_DECEMBER
02572   */
02573 __STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx)
02574 {
02575   return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos);
02576 }
02577
02578 /**
02579   * @brief  Get Timestamp Day in BCD format
02580   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
02581   * @rmtoll TSDR         DT            LL_RTC_TS_GetDay\n
02582   *         TSDR         DU            LL_RTC_TS_GetDay
02583   * @param  RTCx RTC Instance
02584   * @retval Value between Min_Data=0x01 and Max_Data=0x31
02585   */
02586 __STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx)
02587 {
02588   return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_DT | RTC_TSDR_DU));
02589 }
02590
02591 /**
02592   * @brief  Get Timestamp date (WeekDay, Day and Month) in BCD format
02593   * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_MONTH,
02594   * and __LL_RTC_GET_DAY are available to get independently each parameter.
02595   * @rmtoll TSDR         WDU           LL_RTC_TS_GetDate\n
02596   *         TSDR         MT            LL_RTC_TS_GetDate\n
02597   *         TSDR         MU            LL_RTC_TS_GetDate\n
02598   *         TSDR         DT            LL_RTC_TS_GetDate\n
02599   *         TSDR         DU            LL_RTC_TS_GetDate
02600   * @param  RTCx RTC Instance
02601   * @retval Combination of Weekday, Day and Month
02602   */
02603 __STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx)
02604 {
02605   return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | RTC_TSDR_DU));
02606 }
02607
02608 /**
02609   * @brief  Get time-stamp sub second value
02610   * @rmtoll TSSSR        SS            LL_RTC_TS_GetSubSecond
02611   * @param  RTCx RTC Instance
02612   * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
02613   */
02614 __STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef *RTCx)
02615 {
02616   return (uint32_t)(READ_BIT(RTCx->TSSSR, RTC_TSSSR_SS));
02617 }
02618
02619 #if defined(RTC_TAMPCR_TAMPTS)
02620 /**
02621   * @brief  Activate timestamp on tamper detection event
02622   * @rmtoll TAMPCR       TAMPTS        LL_RTC_TS_EnableOnTamper
02623   * @param  RTCx RTC Instance
02624   * @retval None
02625   */
02626 __STATIC_INLINE void LL_RTC_TS_EnableOnTamper(RTC_TypeDef *RTCx)
02627 {
02628   SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPTS);
02629 }
02630
02631 /**
02632   * @brief  Disable timestamp on tamper detection event
02633   * @rmtoll TAMPCR       TAMPTS        LL_RTC_TS_DisableOnTamper
02634   * @param  RTCx RTC Instance
02635   * @retval None
02636   */
02637 __STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx)
02638 {
02639   CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPTS);
02640 }
02641 #endif /* RTC_TAMPCR_TAMPTS */
02642
02643 /**
02644   * @}
02645   */
02646
02647 /** @defgroup RTC_LL_EF_Tamper Tamper
02648   * @{
02649   */
02650
02651 /**
02652   * @brief  Enable RTC_TAMPx input detection
02653   * @rmtoll TAMPCR       TAMP1E        LL_RTC_TAMPER_Enable\n
02654   *         TAMPCR       TAMP2E        LL_RTC_TAMPER_Enable\n
02655   *         TAMPCR       TAMP3E        LL_RTC_TAMPER_Enable
02656   * @param  RTCx RTC Instance
02657   * @param  Tamper This parameter can be a combination of the following values:
02658   *         @arg @ref LL_RTC_TAMPER_1 (*)
02659   *         @arg @ref LL_RTC_TAMPER_2
02660   *         @arg @ref LL_RTC_TAMPER_3 (*)
02661   *
02662   *         (*)  Value not defined in all devices. \n
02663   *
02664   * @retval None
02665   */
02666 __STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper)
02667 {
02668   SET_BIT(RTCx->TAMPCR, Tamper);
02669 }
02670
02671 /**
02672   * @brief  Clear RTC_TAMPx input detection
02673   * @rmtoll TAMPCR       TAMP1E        LL_RTC_TAMPER_Disable\n
02674   *         TAMPCR       TAMP2E        LL_RTC_TAMPER_Disable\n
02675   *         TAMPCR       TAMP3E        LL_RTC_TAMPER_Disable
02676   * @param  RTCx RTC Instance
02677   * @param  Tamper This parameter can be a combination of the following values:
02678   *         @arg @ref LL_RTC_TAMPER_1 (*)
02679   *         @arg @ref LL_RTC_TAMPER_2
02680   *         @arg @ref LL_RTC_TAMPER_3 (*)
02681   *
02682   *         (*)  Value not defined in all devices. \n
02683   *
02684   * @retval None
02685   */
02686 __STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper)
02687 {
02688   CLEAR_BIT(RTCx->TAMPCR, Tamper);
02689 }
02690
02691 /**
02692   * @brief  Enable Tamper mask flag
02693   * @note Associated Tamper IT must not enabled when tamper mask is set.
02694   * @rmtoll TAMPCR       TAMP1MF       LL_RTC_TAMPER_EnableMask\n
02695   *         TAMPCR       TAMP2MF       LL_RTC_TAMPER_EnableMask\n
02696   *         TAMPCR       TAMP3MF       LL_RTC_TAMPER_EnableMask
02697   * @param  RTCx RTC Instance
02698   * @param  Mask This parameter can be a combination of the following values:
02699   *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER1 (*)
02700   *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER2
02701   *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER3 (*)
02702   *
02703   *         (*)  Value not defined in all devices. \n
02704   *
02705   * @retval None
02706   */
02707 __STATIC_INLINE void LL_RTC_TAMPER_EnableMask(RTC_TypeDef *RTCx, uint32_t Mask)
02708 {
02709   SET_BIT(RTCx->TAMPCR, Mask);
02710 }
02711
02712 /**
02713   * @brief  Disable Tamper mask flag
02714   * @rmtoll TAMPCR       TAMP1MF       LL_RTC_TAMPER_DisableMask\n
02715   *         TAMPCR       TAMP2MF       LL_RTC_TAMPER_DisableMask\n
02716   *         TAMPCR       TAMP3MF       LL_RTC_TAMPER_DisableMask
02717   * @param  RTCx RTC Instance
02718   * @param  Mask This parameter can be a combination of the following values:
02719   *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER1 (*)
02720   *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER2
02721   *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER3 (*)
02722   *
02723   *         (*)  Value not defined in all devices. \n
02724   *
02725   * @retval None
02726   */
02727 __STATIC_INLINE void LL_RTC_TAMPER_DisableMask(RTC_TypeDef *RTCx, uint32_t Mask)
02728 {
02729   CLEAR_BIT(RTCx->TAMPCR, Mask);
02730 }
02731
02732 /**
02733   * @brief  Enable backup register erase after Tamper event detection
02734   * @rmtoll TAMPCR       TAMP1NOERASE  LL_RTC_TAMPER_EnableEraseBKP\n
02735   *         TAMPCR       TAMP2NOERASE  LL_RTC_TAMPER_EnableEraseBKP\n
02736   *         TAMPCR       TAMP3NOERASE  LL_RTC_TAMPER_EnableEraseBKP
02737   * @param  RTCx RTC Instance
02738   * @param  Tamper This parameter can be a combination of the following values:
02739   *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1 (*)
02740   *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2
02741   *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3 (*)
02742   *
02743   *         (*)  Value not defined in all devices. \n
02744   *
02745   * @retval None
02746   */
02747 __STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper)
02748 {
02749   CLEAR_BIT(RTCx->TAMPCR, Tamper);
02750 }
02751
02752 /**
02753   * @brief  Disable backup register erase after Tamper event detection
02754   * @rmtoll TAMPCR       TAMP1NOERASE  LL_RTC_TAMPER_DisableEraseBKP\n
02755   *         TAMPCR       TAMP2NOERASE  LL_RTC_TAMPER_DisableEraseBKP\n
02756   *         TAMPCR       TAMP3NOERASE  LL_RTC_TAMPER_DisableEraseBKP
02757   * @param  RTCx RTC Instance
02758   * @param  Tamper This parameter can be a combination of the following values:
02759   *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1 (*)
02760   *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2
02761   *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3 (*)
02762   *
02763   *         (*)  Value not defined in all devices. \n
02764   *
02765   * @retval None
02766   */
02767 __STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper)
02768 {
02769   SET_BIT(RTCx->TAMPCR, Tamper);
02770 }
02771
02772 #if defined(RTC_TAMPCR_TAMPPUDIS)
02773 /**
02774   * @brief  Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)
02775   * @rmtoll TAMPCR       TAMPPUDIS     LL_RTC_TAMPER_DisablePullUp
02776   * @param  RTCx RTC Instance
02777   * @retval None
02778   */
02779 __STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(RTC_TypeDef *RTCx)
02780 {
02781   SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPUDIS);
02782 }
02783
02784 /**
02785   * @brief  Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling)
02786   * @rmtoll TAMPCR       TAMPPUDIS     LL_RTC_TAMPER_EnablePullUp
02787   * @param  RTCx RTC Instance
02788   * @retval None
02789   */
02790 __STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(RTC_TypeDef *RTCx)
02791 {
02792   CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPUDIS);
02793 }
02794 #endif /* RTC_TAMPCR_TAMPPUDIS */
02795
02796 #if defined(RTC_TAMPCR_TAMPPRCH)
02797 /**
02798   * @brief  Set RTC_TAMPx precharge duration
02799   * @rmtoll TAMPCR       TAMPPRCH      LL_RTC_TAMPER_SetPrecharge
02800   * @param  RTCx RTC Instance
02801   * @param  Duration This parameter can be one of the following values:
02802   *         @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
02803   *         @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
02804   *         @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
02805   *         @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
02806   * @retval None
02807   */
02808 __STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(RTC_TypeDef *RTCx, uint32_t Duration)
02809 {
02810   MODIFY_REG(RTCx->TAMPCR, RTC_TAMPCR_TAMPPRCH, Duration);
02811 }
02812
02813 /**
02814   * @brief  Get RTC_TAMPx precharge duration
02815   * @rmtoll TAMPCR       TAMPPRCH      LL_RTC_TAMPER_GetPrecharge
02816   * @param  RTCx RTC Instance
02817   * @retval Returned value can be one of the following values:
02818   *         @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
02819   *         @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
02820   *         @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
02821   *         @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
02822   */
02823 __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx)
02824 {
02825   return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPRCH));
02826 }
02827 #endif /* RTC_TAMPCR_TAMPPRCH */
02828
02829 #if defined(RTC_TAMPCR_TAMPFLT)
02830 /**
02831   * @brief  Set RTC_TAMPx filter count
02832   * @rmtoll TAMPCR       TAMPFLT       LL_RTC_TAMPER_SetFilterCount
02833   * @param  RTCx RTC Instance
02834   * @param  FilterCount This parameter can be one of the following values:
02835   *         @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
02836   *         @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
02837   *         @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
02838   *         @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
02839   * @retval None
02840   */
02841 __STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(RTC_TypeDef *RTCx, uint32_t FilterCount)
02842 {
02843   MODIFY_REG(RTCx->TAMPCR, RTC_TAMPCR_TAMPFLT, FilterCount);
02844 }
02845
02846 /**
02847   * @brief  Get RTC_TAMPx filter count
02848   * @rmtoll TAMPCR       TAMPFLT       LL_RTC_TAMPER_GetFilterCount
02849   * @param  RTCx RTC Instance
02850   * @retval Returned value can be one of the following values:
02851   *         @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
02852   *         @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
02853   *         @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
02854   *         @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
02855   */
02856 __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx)
02857 {
02858   return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPFLT));
02859 }
02860 #endif /* RTC_TAMPCR_TAMPFLT */
02861
02862 #if defined(RTC_TAMPCR_TAMPFREQ)
02863 /**
02864   * @brief  Set Tamper sampling frequency
02865   * @rmtoll TAMPCR       TAMPFREQ      LL_RTC_TAMPER_SetSamplingFreq
02866   * @param  RTCx RTC Instance
02867   * @param  SamplingFreq This parameter can be one of the following values:
02868   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
02869   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
02870   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
02871   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
02872   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
02873   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
02874   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
02875   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
02876   * @retval None
02877   */
02878 __STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(RTC_TypeDef *RTCx, uint32_t SamplingFreq)
02879 {
02880   MODIFY_REG(RTCx->TAMPCR, RTC_TAMPCR_TAMPFREQ, SamplingFreq);
02881 }
02882
02883 /**
02884   * @brief  Get Tamper sampling frequency
02885   * @rmtoll TAMPCR       TAMPFREQ      LL_RTC_TAMPER_GetSamplingFreq
02886   * @param  RTCx RTC Instance
02887   * @retval Returned value can be one of the following values:
02888   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
02889   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
02890   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
02891   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
02892   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
02893   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
02894   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
02895   *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
02896   */
02897 __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx)
02898 {
02899   return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPFREQ));
02900 }
02901 #endif /* RTC_TAMPCR_TAMPFREQ */
02902
02903 /**
02904   * @brief  Enable Active level for Tamper input
02905   * @rmtoll TAMPCR       TAMP1TRG      LL_RTC_TAMPER_EnableActiveLevel\n
02906   *         TAMPCR       TAMP2TRG      LL_RTC_TAMPER_EnableActiveLevel\n
02907   *         TAMPCR       TAMP3TRG      LL_RTC_TAMPER_EnableActiveLevel
02908   * @param  RTCx RTC Instance
02909   * @param  Tamper This parameter can be a combination of the following values:
02910   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
02911   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
02912   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3
02913   *
02914   * @retval None
02915   */
02916 __STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
02917 {
02918   SET_BIT(RTCx->TAMPCR, Tamper);
02919 }
02920
02921 /**
02922   * @brief  Disable Active level for Tamper input
02923   * @rmtoll TAMPCR       TAMP1TRG      LL_RTC_TAMPER_DisableActiveLevel\n
02924   *         TAMPCR       TAMP2TRG      LL_RTC_TAMPER_DisableActiveLevel\n
02925   *         TAMPCR       TAMP3TRG      LL_RTC_TAMPER_DisableActiveLevel
02926   * @param  RTCx RTC Instance
02927   * @param  Tamper This parameter can be a combination of the following values:
02928   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
02929   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
02930   *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3
02931   *
02932   * @retval None
02933   */
02934 __STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
02935 {
02936   CLEAR_BIT(RTCx->TAMPCR, Tamper);
02937 }
02938
02939 /**
02940   * @}
02941   */
02942
02943 #if defined(RTC_WAKEUP_SUPPORT)
02944 /** @defgroup RTC_LL_EF_Wakeup Wakeup
02945   * @{
02946   */
02947
02948 /**
02949   * @brief  Enable Wakeup timer
02950   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02951   * @rmtoll CR           WUTE          LL_RTC_WAKEUP_Enable
02952   * @param  RTCx RTC Instance
02953   * @retval None
02954   */
02955 __STATIC_INLINE void LL_RTC_WAKEUP_Enable(RTC_TypeDef *RTCx)
02956 {
02957   SET_BIT(RTCx->CR, RTC_CR_WUTE);
02958 }
02959
02960 /**
02961   * @brief  Disable Wakeup timer
02962   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02963   * @rmtoll CR           WUTE          LL_RTC_WAKEUP_Disable
02964   * @param  RTCx RTC Instance
02965   * @retval None
02966   */
02967 __STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx)
02968 {
02969   CLEAR_BIT(RTCx->CR, RTC_CR_WUTE);
02970 }
02971
02972 /**
02973   * @brief  Check if Wakeup timer is enabled or not
02974   * @rmtoll CR           WUTE          LL_RTC_WAKEUP_IsEnabled
02975   * @param  RTCx RTC Instance
02976   * @retval State of bit (1 or 0).
02977   */
02978 __STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx)
02979 {
02980   return ((READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) ? 1UL : 0UL);
02981 }
02982
02983 /**
02984   * @brief  Select Wakeup clock
02985   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
02986   * @note Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1
02987   * @rmtoll CR           WUCKSEL       LL_RTC_WAKEUP_SetClock
02988   * @param  RTCx RTC Instance
02989   * @param  WakeupClock This parameter can be one of the following values:
02990   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16
02991   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8
02992   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4
02993   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2
02994   *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
02995   *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
02996   * @retval None
02997   */
02998 __STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupClock)
02999 {
03000   MODIFY_REG(RTCx->CR, RTC_CR_WUCKSEL, WakeupClock);
03001 }
03002
03003 /**
03004   * @brief  Get Wakeup clock
03005   * @rmtoll CR           WUCKSEL       LL_RTC_WAKEUP_GetClock
03006   * @param  RTCx RTC Instance
03007   * @retval Returned value can be one of the following values:
03008   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16
03009   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8
03010   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4
03011   *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2
03012   *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
03013   *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
03014   */
03015 __STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx)
03016 {
03017   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL));
03018 }
03019
03020 /**
03021   * @brief  Set Wakeup auto-reload value
03022   * @note Bit can be written only when WUTWF is set to 1 in RTC_ISR
03023   * @rmtoll WUTR         WUT           LL_RTC_WAKEUP_SetAutoReload
03024   * @param  RTCx RTC Instance
03025   * @param  Value Value between Min_Data=0x00 and Max_Data=0xFFFF
03026   * @retval None
03027   */
03028 __STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Value)
03029 {
03030   MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUT, Value);
03031 }
03032
03033 /**
03034   * @brief  Get Wakeup auto-reload value
03035   * @rmtoll WUTR         WUT           LL_RTC_WAKEUP_GetAutoReload
03036   * @param  RTCx RTC Instance
03037   * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
03038   */
03039 __STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx)
03040 {
03041   return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT));
03042 }
03043
03044 /**
03045   * @}
03046   */
03047 #endif /* RTC_WAKEUP_SUPPORT */
03048
03049 #if defined(RTC_BACKUP_SUPPORT)
03050 /** @defgroup RTC_LL_EF_Backup_Registers Backup_Registers
03051   * @{
03052   */
03053
03054 /**
03055   * @brief  Writes a data in a specified RTC Backup data register.
03056   * @rmtoll BKPxR        BKP           LL_RTC_BAK_SetRegister
03057   * @param  RTCx RTC Instance
03058   * @param  BackupRegister This parameter can be one of the following values:
03059   *         @arg @ref LL_RTC_BKP_DR0
03060   *         @arg @ref LL_RTC_BKP_DR1
03061   *         @arg @ref LL_RTC_BKP_DR2
03062   *         @arg @ref LL_RTC_BKP_DR3
03063   *         @arg @ref LL_RTC_BKP_DR4
03064   *         @arg @ref LL_RTC_BKP_DR5
03065   *         @arg @ref LL_RTC_BKP_DR6
03066   *         @arg @ref LL_RTC_BKP_DR7
03067   *         @arg @ref LL_RTC_BKP_DR8
03068   *         @arg @ref LL_RTC_BKP_DR9
03069   *         @arg @ref LL_RTC_BKP_DR10
03070   *         @arg @ref LL_RTC_BKP_DR11
03071   *         @arg @ref LL_RTC_BKP_DR12
03072   *         @arg @ref LL_RTC_BKP_DR13
03073   *         @arg @ref LL_RTC_BKP_DR14
03074   *         @arg @ref LL_RTC_BKP_DR15
03075   *         @arg @ref LL_RTC_BKP_DR16
03076   *         @arg @ref LL_RTC_BKP_DR17
03077   *         @arg @ref LL_RTC_BKP_DR18
03078   *         @arg @ref LL_RTC_BKP_DR19
03079   * @param  Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
03080   * @retval None
03081   */
03082 __STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)
03083 {
03084   register __IO uint32_t* tmp;
03085
03086   tmp = &(RTCx->BKP0R) + BackupRegister;
03087
03088   *tmp = Data;
03089 }
03090
03091 /**
03092   * @brief  Reads data from the specified RTC Backup data Register.
03093   * @rmtoll BKPxR        BKP           LL_RTC_BAK_GetRegister
03094   * @param  RTCx RTC Instance
03095   * @param  BackupRegister This parameter can be one of the following values:
03096   *         @arg @ref LL_RTC_BKP_DR0
03097   *         @arg @ref LL_RTC_BKP_DR1
03098   *         @arg @ref LL_RTC_BKP_DR2
03099   *         @arg @ref LL_RTC_BKP_DR3
03100   *         @arg @ref LL_RTC_BKP_DR4
03101   *         @arg @ref LL_RTC_BKP_DR5
03102   *         @arg @ref LL_RTC_BKP_DR6
03103   *         @arg @ref LL_RTC_BKP_DR7
03104   *         @arg @ref LL_RTC_BKP_DR8
03105   *         @arg @ref LL_RTC_BKP_DR9
03106   *         @arg @ref LL_RTC_BKP_DR10
03107   *         @arg @ref LL_RTC_BKP_DR11
03108   *         @arg @ref LL_RTC_BKP_DR12
03109   *         @arg @ref LL_RTC_BKP_DR13
03110   *         @arg @ref LL_RTC_BKP_DR14
03111   *         @arg @ref LL_RTC_BKP_DR15
03112   *         @arg @ref LL_RTC_BKP_DR16
03113   *         @arg @ref LL_RTC_BKP_DR17
03114   *         @arg @ref LL_RTC_BKP_DR18
03115   *         @arg @ref LL_RTC_BKP_DR19
03116   * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
03117   */
03118 __STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister)
03119 {
03120   register const __IO uint32_t *tmp;
03121
03122   tmp = &(RTCx->BKP0R) + BackupRegister;
03123
03124   /* Read the specified register */
03125   return *tmp;
03126 }
03127
03128 /**
03129   * @}
03130   */
03131 #endif /* RTC_BACKUP_SUPPORT */
03132
03133 /** @defgroup RTC_LL_EF_Calibration Calibration
03134   * @{
03135   */
03136
03137 /**
03138   * @brief  Set Calibration output frequency (1 Hz or 512 Hz)
03139   * @note Bits are write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03140   * @rmtoll CR           COE           LL_RTC_CAL_SetOutputFreq\n
03141   *         CR           COSEL         LL_RTC_CAL_SetOutputFreq
03142   * @param  RTCx RTC Instance
03143   * @param  Frequency This parameter can be one of the following values:
03144   *         @arg @ref LL_RTC_CALIB_OUTPUT_NONE
03145   *         @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
03146   *         @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
03147   * @retval None
03148   */
03149 __STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Frequency)
03150 {
03151   MODIFY_REG(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL, Frequency);
03152 }
03153
03154 /**
03155   * @brief  Get Calibration output frequency (1 Hz or 512 Hz)
03156   * @rmtoll CR           COE           LL_RTC_CAL_GetOutputFreq\n
03157   *         CR           COSEL         LL_RTC_CAL_GetOutputFreq
03158   * @param  RTCx RTC Instance
03159   * @retval Returned value can be one of the following values:
03160   *         @arg @ref LL_RTC_CALIB_OUTPUT_NONE
03161   *         @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
03162   *         @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
03163   */
03164 __STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx)
03165 {
03166   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL));
03167 }
03168
03169 /**
03170   * @brief  Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm)
03171   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03172   * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR
03173   * @rmtoll CALR         CALP          LL_RTC_CAL_SetPulse
03174   * @param  RTCx RTC Instance
03175   * @param  Pulse This parameter can be one of the following values:
03176   *         @arg @ref LL_RTC_CALIB_INSERTPULSE_NONE
03177   *         @arg @ref LL_RTC_CALIB_INSERTPULSE_SET
03178   * @retval None
03179   */
03180 __STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse)
03181 {
03182   MODIFY_REG(RTCx->CALR, RTC_CALR_CALP, Pulse);
03183 }
03184
03185 /**
03186   * @brief  Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm)
03187   * @rmtoll CALR         CALP          LL_RTC_CAL_IsPulseInserted
03188   * @param  RTCx RTC Instance
03189   * @retval State of bit (1 or 0).
03190   */
03191 __STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx)
03192 {
03193   return ((READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)) ? 1UL : 0UL);
03194 }
03195
03196 /**
03197   * @brief  Set the calibration cycle period
03198   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03199   * @note   Bit can be written only when RECALPF is set to 0 in RTC_ISR
03200   * @rmtoll CALR         CALW8         LL_RTC_CAL_SetPeriod\n
03201   *         CALR         CALW16        LL_RTC_CAL_SetPeriod
03202   * @param  RTCx RTC Instance
03203   * @param  Period This parameter can be one of the following values:
03204   *         @arg @ref LL_RTC_CALIB_PERIOD_32SEC
03205   *         @arg @ref LL_RTC_CALIB_PERIOD_16SEC
03206   *         @arg @ref LL_RTC_CALIB_PERIOD_8SEC
03207   * @retval None
03208   */
03209 __STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period)
03210 {
03211   MODIFY_REG(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16, Period);
03212 }
03213
03214 /**
03215   * @brief  Get the calibration cycle period
03216   * @rmtoll CALR         CALW8         LL_RTC_CAL_GetPeriod\n
03217   *         CALR         CALW16        LL_RTC_CAL_GetPeriod
03218   * @param  RTCx RTC Instance
03219   * @retval Returned value can be one of the following values:
03220   *         @arg @ref LL_RTC_CALIB_PERIOD_32SEC
03221   *         @arg @ref LL_RTC_CALIB_PERIOD_16SEC
03222   *         @arg @ref LL_RTC_CALIB_PERIOD_8SEC
03223   */
03224 __STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx)
03225 {
03226   return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16));
03227 }
03228
03229 /**
03230   * @brief  Set Calibration minus
03231   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03232   * @note   Bit can be written only when RECALPF is set to 0 in RTC_ISR
03233   * @rmtoll CALR         CALM          LL_RTC_CAL_SetMinus
03234   * @param  RTCx RTC Instance
03235   * @param  CalibMinus Value between Min_Data=0x00 and Max_Data=0x1FF
03236   * @retval None
03237   */
03238 __STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus)
03239 {
03240   MODIFY_REG(RTCx->CALR, RTC_CALR_CALM, CalibMinus);
03241 }
03242
03243 /**
03244   * @brief  Get Calibration minus
03245   * @rmtoll CALR         CALM          LL_RTC_CAL_GetMinus
03246   * @param  RTCx RTC Instance
03247   * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF
03248   */
03249 __STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx)
03250 {
03251   return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM));
03252 }
03253
03254 /**
03255   * @}
03256   */
03257
03258 /** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management
03259   * @{
03260   */
03261
03262 /**
03263   * @brief  Get Internal Time-stamp flag
03264   * @rmtoll ISR          ITSF          LL_RTC_IsActiveFlag_ITS
03265   * @param  RTCx RTC Instance
03266   * @retval State of bit (1 or 0).
03267   */
03268 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx)
03269 {
03270   return ((READ_BIT(RTCx->ISR, RTC_ISR_ITSF) == (RTC_ISR_ITSF)) ? 1UL : 0UL);
03271 }
03272
03273 /**
03274   * @brief  Get Recalibration pending Flag
03275   * @rmtoll ISR          RECALPF       LL_RTC_IsActiveFlag_RECALP
03276   * @param  RTCx RTC Instance
03277   * @retval State of bit (1 or 0).
03278   */
03279 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx)
03280 {
03281   return ((READ_BIT(RTCx->ISR, RTC_ISR_RECALPF) == (RTC_ISR_RECALPF)) ? 1UL : 0UL);
03282 }
03283
03284 #if defined(RTC_TAMPER3_SUPPORT)
03285 /**
03286   * @brief  Get RTC_TAMP3 detection flag
03287   * @rmtoll ISR          TAMP3F        LL_RTC_IsActiveFlag_TAMP3
03288   * @param  RTCx RTC Instance
03289   * @retval State of bit (1 or 0).
03290   */
03291 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx)
03292 {
03293   return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP3F) == (RTC_ISR_TAMP3F)) ? 1UL : 0UL);
03294 }
03295 #endif /* RTC_TAMPER3_SUPPORT */
03296
03297 #if defined(RTC_TAMPER2_SUPPORT)
03298 /**
03299   * @brief  Get RTC_TAMP2 detection flag
03300   * @rmtoll ISR          TAMP2F        LL_RTC_IsActiveFlag_TAMP2
03301   * @param  RTCx RTC Instance
03302   * @retval State of bit (1 or 0).
03303   */
03304 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx)
03305 {
03306   return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP2F) == (RTC_ISR_TAMP2F)) ? 1UL : 0UL);
03307 }
03308 #endif /* RTC_TAMPER2_SUPPORT */
03309
03310 #if defined(RTC_TAMPER1_SUPPORT)
03311 /**
03312   * @brief  Get RTC_TAMP1 detection flag
03313   * @rmtoll ISR          TAMP1F        LL_RTC_IsActiveFlag_TAMP1
03314   * @param  RTCx RTC Instance
03315   * @retval State of bit (1 or 0).
03316   */
03317 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx)
03318 {
03319   return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP1F) == (RTC_ISR_TAMP1F)) ? 1UL : 0UL);
03320 }
03321 #endif /* RTC_TAMPER1_SUPPORT */
03322
03323 /**
03324   * @brief  Get Time-stamp overflow flag
03325   * @rmtoll ISR          TSOVF         LL_RTC_IsActiveFlag_TSOV
03326   * @param  RTCx RTC Instance
03327   * @retval State of bit (1 or 0).
03328   */
03329 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx)
03330 {
03331   return ((READ_BIT(RTCx->ISR, RTC_ISR_TSOVF) == (RTC_ISR_TSOVF)) ? 1UL : 0UL);
03332 }
03333
03334 /**
03335   * @brief  Get Time-stamp flag
03336   * @rmtoll ISR          TSF           LL_RTC_IsActiveFlag_TS
03337   * @param  RTCx RTC Instance
03338   * @retval State of bit (1 or 0).
03339   */
03340 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx)
03341 {
03342   return ((READ_BIT(RTCx->ISR, RTC_ISR_TSF) == (RTC_ISR_TSF)) ? 1UL : 0UL);
03343 }
03344
03345 #if defined(RTC_WAKEUP_SUPPORT)
03346 /**
03347   * @brief  Get Wakeup timer flag
03348   * @rmtoll ISR          WUTF          LL_RTC_IsActiveFlag_WUT
03349   * @param  RTCx RTC Instance
03350   * @retval State of bit (1 or 0).
03351   */
03352 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx)
03353 {
03354   return ((READ_BIT(RTCx->ISR, RTC_ISR_WUTF) == (RTC_ISR_WUTF)) ? 1UL : 0UL);
03355 }
03356 #endif /* RTC_WAKEUP_SUPPORT */
03357
03358 /**
03359   * @brief  Get Alarm B flag
03360   * @rmtoll ISR          ALRBF         LL_RTC_IsActiveFlag_ALRB
03361   * @param  RTCx RTC Instance
03362   * @retval State of bit (1 or 0).
03363   */
03364 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx)
03365 {
03366   return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRBF) == (RTC_ISR_ALRBF)) ? 1UL : 0UL);
03367 }
03368
03369 /**
03370   * @brief  Get Alarm A flag
03371   * @rmtoll ISR          ALRAF         LL_RTC_IsActiveFlag_ALRA
03372   * @param  RTCx RTC Instance
03373   * @retval State of bit (1 or 0).
03374   */
03375 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx)
03376 {
03377   return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRAF) == (RTC_ISR_ALRAF)) ? 1UL : 0UL);
03378 }
03379
03380 /**
03381   * @brief  Clear Internal Time-stamp flag
03382   * @rmtoll ISR          ITSF          LL_RTC_ClearFlag_ITS
03383   * @param  RTCx RTC Instance
03384   * @retval None
03385   */
03386 __STATIC_INLINE void LL_RTC_ClearFlag_ITS(RTC_TypeDef *RTCx)
03387 {
03388   WRITE_REG(RTCx->ISR, (~((RTC_ISR_ITSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
03389 }
03390
03391 #if defined(RTC_TAMPER3_SUPPORT)
03392 /**
03393   * @brief  Clear RTC_TAMP3 detection flag
03394   * @rmtoll ISR          TAMP3F        LL_RTC_ClearFlag_TAMP3
03395   * @param  RTCx RTC Instance
03396   * @retval None
03397   */
03398 __STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(RTC_TypeDef *RTCx)
03399 {
03400   WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP3F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
03401 }
03402 #endif /* RTC_TAMPER3_SUPPORT */
03403
03404 #if defined(RTC_TAMPER2_SUPPORT)
03405 /**
03406   * @brief  Clear RTC_TAMP2 detection flag
03407   * @rmtoll ISR          TAMP2F        LL_RTC_ClearFlag_TAMP2
03408   * @param  RTCx RTC Instance
03409   * @retval None
03410   */
03411 __STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(RTC_TypeDef *RTCx)
03412 {
03413   WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP2F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
03414 }
03415 #endif /* RTC_TAMPER2_SUPPORT */
03416
03417 #if defined(RTC_TAMPER1_SUPPORT)
03418 /**
03419   * @brief  Clear RTC_TAMP1 detection flag
03420   * @rmtoll ISR          TAMP1F        LL_RTC_ClearFlag_TAMP1
03421   * @param  RTCx RTC Instance
03422   * @retval None
03423   */
03424 __STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(RTC_TypeDef *RTCx)
03425 {
03426   WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP1F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
03427 }
03428 #endif /* RTC_TAMPER1_SUPPORT */
03429
03430 /**
03431   * @brief  Clear Time-stamp overflow flag
03432   * @rmtoll ISR          TSOVF         LL_RTC_ClearFlag_TSOV
03433   * @param  RTCx RTC Instance
03434   * @retval None
03435   */
03436 __STATIC_INLINE void LL_RTC_ClearFlag_TSOV(RTC_TypeDef *RTCx)
03437 {
03438   WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSOVF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
03439 }
03440
03441 /**
03442   * @brief  Clear Time-stamp flag
03443   * @rmtoll ISR          TSF           LL_RTC_ClearFlag_TS
03444   * @param  RTCx RTC Instance
03445   * @retval None
03446   */
03447 __STATIC_INLINE void LL_RTC_ClearFlag_TS(RTC_TypeDef *RTCx)
03448 {
03449   WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
03450 }
03451
03452 #if defined(RTC_WAKEUP_SUPPORT)
03453 /**
03454   * @brief  Clear Wakeup timer flag
03455   * @rmtoll ISR          WUTF          LL_RTC_ClearFlag_WUT
03456   * @param  RTCx RTC Instance
03457   * @retval None
03458   */
03459 __STATIC_INLINE void LL_RTC_ClearFlag_WUT(RTC_TypeDef *RTCx)
03460 {
03461   WRITE_REG(RTCx->ISR, (~((RTC_ISR_WUTF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
03462 }
03463 #endif /* RTC_WAKEUP_SUPPORT */
03464
03465 /**
03466   * @brief  Clear Alarm B flag
03467   * @rmtoll ISR          ALRBF         LL_RTC_ClearFlag_ALRB
03468   * @param  RTCx RTC Instance
03469   * @retval None
03470   */
03471 __STATIC_INLINE void LL_RTC_ClearFlag_ALRB(RTC_TypeDef *RTCx)
03472 {
03473   WRITE_REG(RTCx->ISR, (~((RTC_ISR_ALRBF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
03474 }
03475
03476 /**
03477   * @brief  Clear Alarm A flag
03478   * @rmtoll ISR          ALRAF         LL_RTC_ClearFlag_ALRA
03479   * @param  RTCx RTC Instance
03480   * @retval None
03481   */
03482 __STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx)
03483 {
03484   WRITE_REG(RTCx->ISR, (~((RTC_ISR_ALRAF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
03485 }
03486
03487 /**
03488   * @brief  Get Initialization flag
03489   * @rmtoll ISR          INITF         LL_RTC_IsActiveFlag_INIT
03490   * @param  RTCx RTC Instance
03491   * @retval State of bit (1 or 0).
03492   */
03493 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx)
03494 {
03495   return ((READ_BIT(RTCx->ISR, RTC_ISR_INITF) == (RTC_ISR_INITF)) ? 1UL : 0UL);
03496 }
03497
03498 /**
03499   * @brief  Get Registers synchronization flag
03500   * @rmtoll ISR          RSF           LL_RTC_IsActiveFlag_RS
03501   * @param  RTCx RTC Instance
03502   * @retval State of bit (1 or 0).
03503   */
03504 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx)
03505 {
03506   return ((READ_BIT(RTCx->ISR, RTC_ISR_RSF) == (RTC_ISR_RSF)) ? 1UL : 0UL);
03507 }
03508
03509 /**
03510   * @brief  Clear Registers synchronization flag
03511   * @rmtoll ISR          RSF           LL_RTC_ClearFlag_RS
03512   * @param  RTCx RTC Instance
03513   * @retval None
03514   */
03515 __STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx)
03516 {
03517   WRITE_REG(RTCx->ISR, (~((RTC_ISR_RSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
03518 }
03519
03520 /**
03521   * @brief  Get Initialization status flag
03522   * @rmtoll ISR          INITS         LL_RTC_IsActiveFlag_INITS
03523   * @param  RTCx RTC Instance
03524   * @retval State of bit (1 or 0).
03525   */
03526 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx)
03527 {
03528   return ((READ_BIT(RTCx->ISR, RTC_ISR_INITS) == (RTC_ISR_INITS)) ? 1UL : 0UL);
03529 }
03530
03531 /**
03532   * @brief  Get Shift operation pending flag
03533   * @rmtoll ISR          SHPF          LL_RTC_IsActiveFlag_SHP
03534   * @param  RTCx RTC Instance
03535   * @retval State of bit (1 or 0).
03536   */
03537 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx)
03538 {
03539   return ((READ_BIT(RTCx->ISR, RTC_ISR_SHPF) == (RTC_ISR_SHPF)) ? 1UL : 0UL);
03540 }
03541
03542 #if defined(RTC_WAKEUP_SUPPORT)
03543 /**
03544   * @brief  Get Wakeup timer write flag
03545   * @rmtoll ISR          WUTWF         LL_RTC_IsActiveFlag_WUTW
03546   * @param  RTCx RTC Instance
03547   * @retval State of bit (1 or 0).
03548   */
03549 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx)
03550 {
03551   return ((READ_BIT(RTCx->ISR, RTC_ISR_WUTWF) == (RTC_ISR_WUTWF)) ? 1UL : 0UL);
03552 }
03553 #endif /* RTC_WAKEUP_SUPPORT */
03554
03555 /**
03556   * @brief  Get Alarm B write flag
03557   * @rmtoll ISR          ALRBWF        LL_RTC_IsActiveFlag_ALRBW
03558   * @param  RTCx RTC Instance
03559   * @retval State of bit (1 or 0).
03560   */
03561 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx)
03562 {
03563   return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRBWF) == (RTC_ISR_ALRBWF)) ? 1UL : 0UL);
03564 }
03565
03566 /**
03567   * @brief  Get Alarm A write flag
03568   * @rmtoll ISR          ALRAWF        LL_RTC_IsActiveFlag_ALRAW
03569   * @param  RTCx RTC Instance
03570   * @retval State of bit (1 or 0).
03571   */
03572 __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx)
03573 {
03574   return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRAWF) == (RTC_ISR_ALRAWF)) ? 1UL : 0UL);
03575 }
03576
03577 /**
03578   * @}
03579   */
03580
03581 /** @defgroup RTC_LL_EF_IT_Management IT_Management
03582   * @{
03583   */
03584
03585 /**
03586   * @brief  Enable Time-stamp interrupt
03587   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03588   * @rmtoll CR           TSIE          LL_RTC_EnableIT_TS
03589   * @param  RTCx RTC Instance
03590   * @retval None
03591   */
03592 __STATIC_INLINE void LL_RTC_EnableIT_TS(RTC_TypeDef *RTCx)
03593 {
03594   SET_BIT(RTCx->CR, RTC_CR_TSIE);
03595 }
03596
03597 /**
03598   * @brief  Disable Time-stamp interrupt
03599   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03600   * @rmtoll CR           TSIE          LL_RTC_DisableIT_TS
03601   * @param  RTCx RTC Instance
03602   * @retval None
03603   */
03604 __STATIC_INLINE void LL_RTC_DisableIT_TS(RTC_TypeDef *RTCx)
03605 {
03606   CLEAR_BIT(RTCx->CR, RTC_CR_TSIE);
03607 }
03608
03609 #if defined(RTC_WAKEUP_SUPPORT)
03610 /**
03611   * @brief  Enable Wakeup timer interrupt
03612   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03613   * @rmtoll CR           WUTIE         LL_RTC_EnableIT_WUT
03614   * @param  RTCx RTC Instance
03615   * @retval None
03616   */
03617 __STATIC_INLINE void LL_RTC_EnableIT_WUT(RTC_TypeDef *RTCx)
03618 {
03619   SET_BIT(RTCx->CR, RTC_CR_WUTIE);
03620 }
03621
03622 /**
03623   * @brief  Disable Wakeup timer interrupt
03624   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03625   * @rmtoll CR           WUTIE         LL_RTC_DisableIT_WUT
03626   * @param  RTCx RTC Instance
03627   * @retval None
03628   */
03629 __STATIC_INLINE void LL_RTC_DisableIT_WUT(RTC_TypeDef *RTCx)
03630 {
03631   CLEAR_BIT(RTCx->CR, RTC_CR_WUTIE);
03632 }
03633 #endif /* RTC_WAKEUP_SUPPORT */
03634
03635 /**
03636   * @brief  Enable Alarm B interrupt
03637   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03638   * @rmtoll CR           ALRBIE        LL_RTC_EnableIT_ALRB
03639   * @param  RTCx RTC Instance
03640   * @retval None
03641   */
03642 __STATIC_INLINE void LL_RTC_EnableIT_ALRB(RTC_TypeDef *RTCx)
03643 {
03644   SET_BIT(RTCx->CR, RTC_CR_ALRBIE);
03645 }
03646
03647 /**
03648   * @brief  Disable Alarm B interrupt
03649   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03650   * @rmtoll CR           ALRBIE        LL_RTC_DisableIT_ALRB
03651   * @param  RTCx RTC Instance
03652   * @retval None
03653   */
03654 __STATIC_INLINE void LL_RTC_DisableIT_ALRB(RTC_TypeDef *RTCx)
03655 {
03656   CLEAR_BIT(RTCx->CR, RTC_CR_ALRBIE);
03657 }
03658
03659 /**
03660   * @brief  Enable Alarm A interrupt
03661   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03662   * @rmtoll CR           ALRAIE        LL_RTC_EnableIT_ALRA
03663   * @param  RTCx RTC Instance
03664   * @retval None
03665   */
03666 __STATIC_INLINE void LL_RTC_EnableIT_ALRA(RTC_TypeDef *RTCx)
03667 {
03668   SET_BIT(RTCx->CR, RTC_CR_ALRAIE);
03669 }
03670
03671 /**
03672   * @brief  Disable Alarm A interrupt
03673   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
03674   * @rmtoll CR           ALRAIE        LL_RTC_DisableIT_ALRA
03675   * @param  RTCx RTC Instance
03676   * @retval None
03677   */
03678 __STATIC_INLINE void LL_RTC_DisableIT_ALRA(RTC_TypeDef *RTCx)
03679 {
03680   CLEAR_BIT(RTCx->CR, RTC_CR_ALRAIE);
03681 }
03682
03683 #if defined(RTC_TAMPER3_SUPPORT)
03684 /**
03685   * @brief  Enable Tamper 3 interrupt
03686   * @rmtoll TAMPCR       TAMP3IE       LL_RTC_EnableIT_TAMP3
03687   * @param  RTCx RTC Instance
03688   * @retval None
03689   */
03690 __STATIC_INLINE void LL_RTC_EnableIT_TAMP3(RTC_TypeDef *RTCx)
03691 {
03692   SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP3IE);
03693 }
03694
03695 /**
03696   * @brief  Disable Tamper 3 interrupt
03697   * @rmtoll TAMPCR       TAMP3IE       LL_RTC_DisableIT_TAMP3
03698   * @param  RTCx RTC Instance
03699   * @retval None
03700   */
03701 __STATIC_INLINE void LL_RTC_DisableIT_TAMP3(RTC_TypeDef *RTCx)
03702 {
03703   CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP3IE);
03704 }
03705 #endif /* RTC_TAMPER3_SUPPORT */
03706
03707 #if defined(RTC_TAMPER2_SUPPORT)
03708 /**
03709   * @brief  Enable Tamper 2 interrupt
03710   * @rmtoll TAMPCR       TAMP2IE       LL_RTC_EnableIT_TAMP2
03711   * @param  RTCx RTC Instance
03712   * @retval None
03713   */
03714 __STATIC_INLINE void LL_RTC_EnableIT_TAMP2(RTC_TypeDef *RTCx)
03715 {
03716   SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP2IE);
03717 }
03718
03719 /**
03720   * @brief  Disable Tamper 2 interrupt
03721   * @rmtoll TAMPCR       TAMP2IE       LL_RTC_DisableIT_TAMP2
03722   * @param  RTCx RTC Instance
03723   * @retval None
03724   */
03725 __STATIC_INLINE void LL_RTC_DisableIT_TAMP2(RTC_TypeDef *RTCx)
03726 {
03727   CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP2IE);
03728 }
03729 #endif /* RTC_TAMPER2_SUPPORT */
03730
03731 #if defined(RTC_TAMPER1_SUPPORT)
03732 /**
03733   * @brief  Enable Tamper 1 interrupt
03734   * @rmtoll TAMPCR       TAMP1IE       LL_RTC_EnableIT_TAMP1
03735   * @param  RTCx RTC Instance
03736   * @retval None
03737   */
03738 __STATIC_INLINE void LL_RTC_EnableIT_TAMP1(RTC_TypeDef *RTCx)
03739 {
03740   SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP1IE);
03741 }
03742
03743 /**
03744   * @brief  Disable Tamper 1 interrupt
03745   * @rmtoll TAMPCR       TAMP1IE       LL_RTC_DisableIT_TAMP1
03746   * @param  RTCx RTC Instance
03747   * @retval None
03748   */
03749 __STATIC_INLINE void LL_RTC_DisableIT_TAMP1(RTC_TypeDef *RTCx)
03750 {
03751   CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP1IE);
03752 }
03753 #endif /* RTC_TAMPER1_SUPPORT */
03754
03755 /**
03756   * @brief  Enable all Tamper Interrupt
03757   * @rmtoll TAMPCR       TAMPIE        LL_RTC_EnableIT_TAMP
03758   * @param  RTCx RTC Instance
03759   * @retval None
03760   */
03761 __STATIC_INLINE void LL_RTC_EnableIT_TAMP(RTC_TypeDef *RTCx)
03762 {
03763   SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPIE);
03764 }
03765
03766 /**
03767   * @brief  Disable all Tamper Interrupt
03768   * @rmtoll TAMPCR       TAMPIE        LL_RTC_DisableIT_TAMP
03769   * @param  RTCx RTC Instance
03770   * @retval None
03771   */
03772 __STATIC_INLINE void LL_RTC_DisableIT_TAMP(RTC_TypeDef *RTCx)
03773 {
03774   CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPIE);
03775 }
03776
03777 /**
03778   * @brief  Check if  Time-stamp interrupt is enabled or not
03779   * @rmtoll CR           TSIE          LL_RTC_IsEnabledIT_TS
03780   * @param  RTCx RTC Instance
03781   * @retval State of bit (1 or 0).
03782   */
03783 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx)
03784 {
03785   return ((READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE)) ? 1UL : 0UL);
03786 }
03787
03788 #if defined(RTC_WAKEUP_SUPPORT)
03789 /**
03790   * @brief  Check if  Wakeup timer interrupt is enabled or not
03791   * @rmtoll CR           WUTIE         LL_RTC_IsEnabledIT_WUT
03792   * @param  RTCx RTC Instance
03793   * @retval State of bit (1 or 0).
03794   */
03795 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx)
03796 {
03797   return ((READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE)) ? 1UL : 0UL);
03798 }
03799 #endif /* RTC_WAKEUP_SUPPORT */
03800
03801 /**
03802   * @brief  Check if  Alarm B interrupt is enabled or not
03803   * @rmtoll CR           ALRBIE        LL_RTC_IsEnabledIT_ALRB
03804   * @param  RTCx RTC Instance
03805   * @retval State of bit (1 or 0).
03806   */
03807 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx)
03808 {
03809   return ((READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE)) ? 1UL : 0UL);
03810 }
03811
03812 /**
03813   * @brief  Check if  Alarm A interrupt is enabled or not
03814   * @rmtoll CR           ALRAIE        LL_RTC_IsEnabledIT_ALRA
03815   * @param  RTCx RTC Instance
03816   * @retval State of bit (1 or 0).
03817   */
03818 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx)
03819 {
03820   return ((READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)) ? 1UL : 0UL);
03821 }
03822
03823 #if defined(RTC_TAMPER3_SUPPORT)
03824 /**
03825   * @brief  Check if  Tamper 3 interrupt is enabled or not
03826   * @rmtoll TAMPCR       TAMP3IE       LL_RTC_IsEnabledIT_TAMP3
03827   * @param  RTCx RTC Instance
03828   * @retval State of bit (1 or 0).
03829   */
03830 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(RTC_TypeDef *RTCx)
03831 {
03832   return ((READ_BIT(RTCx->TAMPCR,
03833                    RTC_TAMPCR_TAMP3IE) == (RTC_TAMPCR_TAMP3IE)) ? 1UL : 0UL);
03834 }
03835 #endif /* RTC_TAMPER3_SUPPORT */
03836
03837 #if defined(RTC_TAMPER2_SUPPORT)
03838 /**
03839   * @brief  Check if  Tamper 2 interrupt is enabled or not
03840   * @rmtoll TAMPCR       TAMP2IE       LL_RTC_IsEnabledIT_TAMP2
03841   * @param  RTCx RTC Instance
03842   * @retval State of bit (1 or 0).
03843   */
03844 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(RTC_TypeDef *RTCx)
03845 {
03846   return ((READ_BIT(RTCx->TAMPCR,
03847                    RTC_TAMPCR_TAMP2IE) == (RTC_TAMPCR_TAMP2IE)) ? 1UL : 0UL);
03848
03849 }
03850 #endif /* RTC_TAMPER2_SUPPORT */
03851
03852 #if defined(RTC_TAMPER1_SUPPORT)
03853 /**
03854   * @brief  Check if  Tamper 1 interrupt is enabled or not
03855   * @rmtoll TAMPCR       TAMP1IE       LL_RTC_IsEnabledIT_TAMP1
03856   * @param  RTCx RTC Instance
03857   * @retval State of bit (1 or 0).
03858   */
03859 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(RTC_TypeDef *RTCx)
03860 {
03861   return ((READ_BIT(RTCx->TAMPCR,
03862                    RTC_TAMPCR_TAMP1IE) == (RTC_TAMPCR_TAMP1IE)) ? 1UL : 0UL);
03863 }
03864 #endif /* RTC_TAMPER1_SUPPORT */
03865
03866 /**
03867   * @brief  Check if all the TAMPER interrupts are enabled or not
03868   * @rmtoll TAMPCR       TAMPIE        LL_RTC_IsEnabledIT_TAMP
03869   * @param  RTCx RTC Instance
03870   * @retval State of bit (1 or 0).
03871   */
03872 __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(RTC_TypeDef *RTCx)
03873 {
03874   return ((READ_BIT(RTCx->TAMPCR,
03875                    RTC_TAMPCR_TAMPIE) == (RTC_TAMPCR_TAMPIE)) ? 1UL : 0UL);
03876 }
03877
03878 /**
03879   * @}
03880   */
03881
03882 #if defined(USE_FULL_LL_DRIVER)
03883 /** @defgroup RTC_LL_EF_Init Initialization and de-initialization functions
03884   * @{
03885   */
03886
03887 ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx);
03888 ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct);
03889 void        LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct);
03890 ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct);
03891 void        LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct);
03892 ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct);
03893 void        LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct);
03894 ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
03895 ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
03896 void        LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
03897 void        LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
03898 ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx);
03899 ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx);
03900 ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx);
03901
03902 /**
03903   * @}
03904   */
03905 #endif /* USE_FULL_LL_DRIVER */
03906
03907 /**
03908   * @}
03909   */
03910
03911 /**
03912   * @}
03913   */
03914
03915 #endif /* defined(RTC) */
03916
03917 /**
03918   * @}
03919   */
03920
03921 #ifdef __cplusplus
03922 }
03923 #endif
03924
03925 #endif /* STM32WBxx_LL_RTC_H */
03926
03927 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_spi.c Source File

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stm32wbxx_ll_spi.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_spi.c
00004   * @author  MCD Application Team
00005   * @brief   SPI LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32wbxx_ll_spi.h"
00023 #include "stm32wbxx_ll_bus.h"
00024
00025 #ifdef  USE_FULL_ASSERT
00026 #include "stm32_assert.h"
00027 #else
00028 #define assert_param(expr) ((void)0U)
00029 #endif
00030
00031 /** @addtogroup STM32WBxx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (SPI1) || defined (SPI2)
00036
00037 /** @addtogroup SPI_LL
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043
00044 /* Private constants ---------------------------------------------------------*/
00045 /** @defgroup SPI_LL_Private_Constants SPI Private Constants
00046   * @{
00047   */
00048 /* SPI registers Masks */
00049 #define SPI_CR1_CLEAR_MASK                 (SPI_CR1_CPHA    | SPI_CR1_CPOL     | SPI_CR1_MSTR   | \
00050                                             SPI_CR1_BR      | SPI_CR1_LSBFIRST | SPI_CR1_SSI    | \
00051                                             SPI_CR1_SSM     | SPI_CR1_RXONLY   | SPI_CR1_CRCL   | \
00052                                             SPI_CR1_CRCNEXT | SPI_CR1_CRCEN    | SPI_CR1_BIDIOE | \
00053                                             SPI_CR1_BIDIMODE)
00054 /**
00055   * @}
00056   */
00057
00058 /* Private macros ------------------------------------------------------------*/
00059 /** @defgroup SPI_LL_Private_Macros SPI Private Macros
00060   * @{
00061   */
00062 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX)       \
00063                                                  || ((__VALUE__) == LL_SPI_SIMPLEX_RX)     \
00064                                                  || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
00065                                                  || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
00066
00067 #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
00068                                    || ((__VALUE__) == LL_SPI_MODE_SLAVE))
00069
00070 #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT)     \
00071                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT)  \
00072                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT)  \
00073                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT)  \
00074                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT)  \
00075                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT)  \
00076                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
00077                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
00078                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
00079                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
00080                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
00081                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
00082                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
00083
00084 #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
00085                                        || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
00086
00087 #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
00088                                     || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
00089
00090 #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT)          \
00091                                   || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
00092                                   || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
00093
00094 #define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2)      \
00095                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4)   \
00096                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8)   \
00097                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16)  \
00098                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32)  \
00099                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64)  \
00100                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
00101                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
00102
00103 #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
00104                                        || ((__VALUE__) == LL_SPI_MSB_FIRST))
00105
00106 #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
00107                                              || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
00108
00109 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
00110
00111 /**
00112   * @}
00113   */
00114
00115 /* Private function prototypes -----------------------------------------------*/
00116
00117 /* Exported functions --------------------------------------------------------*/
00118 /** @addtogroup SPI_LL_Exported_Functions
00119   * @{
00120   */
00121
00122 /** @addtogroup SPI_LL_EF_Init
00123   * @{
00124   */
00125
00126 /**
00127   * @brief  De-initialize the SPI registers to their default reset values.
00128   * @param  SPIx SPI Instance
00129   * @retval An ErrorStatus enumeration value:
00130   *          - SUCCESS: SPI registers are de-initialized
00131   *          - ERROR: SPI registers are not de-initialized
00132   */
00133 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
00134 {
00135   ErrorStatus status = ERROR;
00136
00137   /* Check the parameters */
00138   assert_param(IS_SPI_ALL_INSTANCE(SPIx));
00139
00140 #if defined(SPI1)
00141   if (SPIx == SPI1)
00142   {
00143     /* Force reset of SPI clock */
00144     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
00145
00146     /* Release reset of SPI clock */
00147     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
00148
00149     status = SUCCESS;
00150   }
00151 #endif /* SPI1 */
00152 #if defined(SPI2)
00153   if (SPIx == SPI2)
00154   {
00155     /* Force reset of SPI clock */
00156     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
00157
00158     /* Release reset of SPI clock */
00159     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
00160
00161     status = SUCCESS;
00162   }
00163 #endif /* SPI2 */
00164
00165   return status;
00166 }
00167
00168 /**
00169   * @brief  Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
00170   * @note   As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
00171   *         SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
00172   * @param  SPIx SPI Instance
00173   * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
00174   * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
00175   */
00176 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
00177 {
00178   ErrorStatus status = ERROR;
00179
00180   /* Check the SPI Instance SPIx*/
00181   assert_param(IS_SPI_ALL_INSTANCE(SPIx));
00182
00183   /* Check the SPI parameters from SPI_InitStruct*/
00184   assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
00185   assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
00186   assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
00187   assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
00188   assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
00189   assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
00190   assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
00191   assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
00192   assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
00193
00194   if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
00195   {
00196     /*---------------------------- SPIx CR1 Configuration ------------------------
00197      * Configure SPIx CR1 with parameters:
00198      * - TransferDirection:  SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
00199      * - Master/Slave Mode:  SPI_CR1_MSTR bit
00200      * - ClockPolarity:      SPI_CR1_CPOL bit
00201      * - ClockPhase:         SPI_CR1_CPHA bit
00202      * - NSS management:     SPI_CR1_SSM bit
00203      * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
00204      * - BitOrder:           SPI_CR1_LSBFIRST bit
00205      * - CRCCalculation:     SPI_CR1_CRCEN bit
00206      */
00207     MODIFY_REG(SPIx->CR1,
00208                SPI_CR1_CLEAR_MASK,
00209                SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode |
00210                SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
00211                SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
00212                SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
00213
00214     /*---------------------------- SPIx CR2 Configuration ------------------------
00215      * Configure SPIx CR2 with parameters:
00216      * - DataWidth:          DS[3:0] bits
00217      * - NSS management:     SSOE bit
00218      */
00219     MODIFY_REG(SPIx->CR2,
00220                SPI_CR2_DS | SPI_CR2_SSOE,
00221                SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U));
00222
00223     /*---------------------------- SPIx CRCPR Configuration ----------------------
00224      * Configure SPIx CRCPR with parameters:
00225      * - CRCPoly:            CRCPOLY[15:0] bits
00226      */
00227     if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
00228     {
00229       assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
00230       LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
00231     }
00232     status = SUCCESS;
00233   }
00234
00235   return status;
00236 }
00237
00238 /**
00239   * @brief  Set each @ref LL_SPI_InitTypeDef field to default value.
00240   * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
00241   * whose fields will be set to default values.
00242   * @retval None
00243   */
00244 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
00245 {
00246   /* Set SPI_InitStruct fields to default values */
00247   SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
00248   SPI_InitStruct->Mode              = LL_SPI_MODE_SLAVE;
00249   SPI_InitStruct->DataWidth         = LL_SPI_DATAWIDTH_8BIT;
00250   SPI_InitStruct->ClockPolarity     = LL_SPI_POLARITY_LOW;
00251   SPI_InitStruct->ClockPhase        = LL_SPI_PHASE_1EDGE;
00252   SPI_InitStruct->NSS               = LL_SPI_NSS_HARD_INPUT;
00253   SPI_InitStruct->BaudRate          = LL_SPI_BAUDRATEPRESCALER_DIV2;
00254   SPI_InitStruct->BitOrder          = LL_SPI_MSB_FIRST;
00255   SPI_InitStruct->CRCCalculation    = LL_SPI_CRCCALCULATION_DISABLE;
00256   SPI_InitStruct->CRCPoly           = 7U;
00257 }
00258
00259 /**
00260   * @}
00261   */
00262
00263 /**
00264   * @}
00265   */
00266
00267 /**
00268   * @}
00269   */
00270
00271 #endif /* defined (SPI1) || defined (SPI2) */
00272
00273 /**
00274   * @}
00275   */
00276
00277 #endif /* USE_FULL_LL_DRIVER */
00278
00279 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_spi.h Source File

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stm32wbxx_ll_spi.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_spi.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SPI LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_LL_SPI_H
00022 #define STM32WBxx_LL_SPI_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx.h"
00030
00031 /** @addtogroup STM32WBxx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (SPI1) || defined (SPI2)
00036
00037 /** @defgroup SPI_LL SPI
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private macros ------------------------------------------------------------*/
00044
00045 /* Exported types ------------------------------------------------------------*/
00046 #if defined(USE_FULL_LL_DRIVER)
00047 /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
00048   * @{
00049   */
00050
00051 /**
00052   * @brief  SPI Init structures definition
00053   */
00054 typedef struct
00055 {
00056   uint32_t TransferDirection;       /*!< Specifies the SPI unidirectional or bidirectional data mode.
00057                                          This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
00058
00059                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
00060
00061   uint32_t Mode;                    /*!< Specifies the SPI mode (Master/Slave).
00062                                          This parameter can be a value of @ref SPI_LL_EC_MODE.
00063
00064                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
00065
00066   uint32_t DataWidth;               /*!< Specifies the SPI data width.
00067                                          This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
00068
00069                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
00070
00071   uint32_t ClockPolarity;           /*!< Specifies the serial clock steady state.
00072                                          This parameter can be a value of @ref SPI_LL_EC_POLARITY.
00073
00074                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
00075
00076   uint32_t ClockPhase;              /*!< Specifies the clock active edge for the bit capture.
00077                                          This parameter can be a value of @ref SPI_LL_EC_PHASE.
00078
00079                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
00080
00081   uint32_t NSS;                     /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
00082                                          This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
00083
00084                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
00085
00086   uint32_t BaudRate;                /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
00087                                          This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
00088                                          @note The communication clock is derived from the master clock. The slave clock does not need to be set.
00089
00090                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
00091
00092   uint32_t BitOrder;                /*!< Specifies whether data transfers start from MSB or LSB bit.
00093                                          This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
00094
00095                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
00096
00097   uint32_t CRCCalculation;          /*!< Specifies if the CRC calculation is enabled or not.
00098                                          This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
00099
00100                                          This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
00101
00102   uint32_t CRCPoly;                 /*!< Specifies the polynomial used for the CRC calculation.
00103                                          This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
00104
00105                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
00106
00107 } LL_SPI_InitTypeDef;
00108
00109 /**
00110   * @}
00111   */
00112 #endif /* USE_FULL_LL_DRIVER */
00113
00114 /* Exported constants --------------------------------------------------------*/
00115 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
00116   * @{
00117   */
00118
00119 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
00120   * @brief    Flags defines which can be used with LL_SPI_ReadReg function
00121   * @{
00122   */
00123 #define LL_SPI_SR_RXNE                     SPI_SR_RXNE               /*!< Rx buffer not empty flag         */
00124 #define LL_SPI_SR_TXE                      SPI_SR_TXE                /*!< Tx buffer empty flag             */
00125 #define LL_SPI_SR_BSY                      SPI_SR_BSY                /*!< Busy flag                        */
00126 #define LL_SPI_SR_CRCERR                   SPI_SR_CRCERR             /*!< CRC error flag                   */
00127 #define LL_SPI_SR_MODF                     SPI_SR_MODF               /*!< Mode fault flag                  */
00128 #define LL_SPI_SR_OVR                      SPI_SR_OVR                /*!< Overrun flag                     */
00129 #define LL_SPI_SR_FRE                      SPI_SR_FRE                /*!< TI mode frame format error flag  */
00130 /**
00131   * @}
00132   */
00133
00134 /** @defgroup SPI_LL_EC_IT IT Defines
00135   * @brief    IT defines which can be used with LL_SPI_ReadReg and  LL_SPI_WriteReg functions
00136   * @{
00137   */
00138 #define LL_SPI_CR2_RXNEIE                  SPI_CR2_RXNEIE            /*!< Rx buffer not empty interrupt enable */
00139 #define LL_SPI_CR2_TXEIE                   SPI_CR2_TXEIE             /*!< Tx buffer empty interrupt enable     */
00140 #define LL_SPI_CR2_ERRIE                   SPI_CR2_ERRIE             /*!< Error interrupt enable               */
00141 /**
00142   * @}
00143   */
00144
00145 /** @defgroup SPI_LL_EC_MODE Operation Mode
00146   * @{
00147   */
00148 #define LL_SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)    /*!< Master configuration  */
00149 #define LL_SPI_MODE_SLAVE                  0x00000000U                     /*!< Slave configuration   */
00150 /**
00151   * @}
00152   */
00153
00154 /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
00155   * @{
00156   */
00157 #define LL_SPI_PROTOCOL_MOTOROLA           0x00000000U               /*!< Motorola mode. Used as default value */
00158 #define LL_SPI_PROTOCOL_TI                 (SPI_CR2_FRF)             /*!< TI mode                              */
00159 /**
00160   * @}
00161   */
00162
00163 /** @defgroup SPI_LL_EC_PHASE Clock Phase
00164   * @{
00165   */
00166 #define LL_SPI_PHASE_1EDGE                 0x00000000U               /*!< First clock transition is the first data capture edge  */
00167 #define LL_SPI_PHASE_2EDGE                 (SPI_CR1_CPHA)            /*!< Second clock transition is the first data capture edge */
00168 /**
00169   * @}
00170   */
00171
00172 /** @defgroup SPI_LL_EC_POLARITY Clock Polarity
00173   * @{
00174   */
00175 #define LL_SPI_POLARITY_LOW                0x00000000U               /*!< Clock to 0 when idle */
00176 #define LL_SPI_POLARITY_HIGH               (SPI_CR1_CPOL)            /*!< Clock to 1 when idle */
00177 /**
00178   * @}
00179   */
00180
00181 /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
00182   * @{
00183   */
00184 #define LL_SPI_BAUDRATEPRESCALER_DIV2      0x00000000U                                    /*!< BaudRate control equal to fPCLK/2   */
00185 #define LL_SPI_BAUDRATEPRESCALER_DIV4      (SPI_CR1_BR_0)                                 /*!< BaudRate control equal to fPCLK/4   */
00186 #define LL_SPI_BAUDRATEPRESCALER_DIV8      (SPI_CR1_BR_1)                                 /*!< BaudRate control equal to fPCLK/8   */
00187 #define LL_SPI_BAUDRATEPRESCALER_DIV16     (SPI_CR1_BR_1 | SPI_CR1_BR_0)                  /*!< BaudRate control equal to fPCLK/16  */
00188 #define LL_SPI_BAUDRATEPRESCALER_DIV32     (SPI_CR1_BR_2)                                 /*!< BaudRate control equal to fPCLK/32  */
00189 #define LL_SPI_BAUDRATEPRESCALER_DIV64     (SPI_CR1_BR_2 | SPI_CR1_BR_0)                  /*!< BaudRate control equal to fPCLK/64  */
00190 #define LL_SPI_BAUDRATEPRESCALER_DIV128    (SPI_CR1_BR_2 | SPI_CR1_BR_1)                  /*!< BaudRate control equal to fPCLK/128 */
00191 #define LL_SPI_BAUDRATEPRESCALER_DIV256    (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)   /*!< BaudRate control equal to fPCLK/256 */
00192 /**
00193   * @}
00194   */
00195
00196 /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
00197   * @{
00198   */
00199 #define LL_SPI_LSB_FIRST                   (SPI_CR1_LSBFIRST)        /*!< Data is transmitted/received with the LSB first */
00200 #define LL_SPI_MSB_FIRST                   0x00000000U               /*!< Data is transmitted/received with the MSB first */
00201 /**
00202   * @}
00203   */
00204
00205 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
00206   * @{
00207   */
00208 #define LL_SPI_FULL_DUPLEX                 0x00000000U                          /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
00209 #define LL_SPI_SIMPLEX_RX                  (SPI_CR1_RXONLY)                     /*!< Simplex Rx mode.  Rx transfer only on 1 line    */
00210 #define LL_SPI_HALF_DUPLEX_RX              (SPI_CR1_BIDIMODE)                   /*!< Half-Duplex Rx mode. Rx transfer on 1 line      */
00211 #define LL_SPI_HALF_DUPLEX_TX              (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)  /*!< Half-Duplex Tx mode. Tx transfer on 1 line      */
00212 /**
00213   * @}
00214   */
00215
00216 /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
00217   * @{
00218   */
00219 #define LL_SPI_NSS_SOFT                    (SPI_CR1_SSM)                     /*!< NSS managed internally. NSS pin not used and free              */
00220 #define LL_SPI_NSS_HARD_INPUT              0x00000000U                       /*!< NSS pin used in Input. Only used in Master mode                */
00221 #define LL_SPI_NSS_HARD_OUTPUT             (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
00222 /**
00223   * @}
00224   */
00225
00226 /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
00227   * @{
00228   */
00229 #define LL_SPI_DATAWIDTH_4BIT              (SPI_CR2_DS_0 | SPI_CR2_DS_1)                               /*!< Data length for SPI transfer:  4 bits */
00230 #define LL_SPI_DATAWIDTH_5BIT              (SPI_CR2_DS_2)                                              /*!< Data length for SPI transfer:  5 bits */
00231 #define LL_SPI_DATAWIDTH_6BIT              (SPI_CR2_DS_2 | SPI_CR2_DS_0)                               /*!< Data length for SPI transfer:  6 bits */
00232 #define LL_SPI_DATAWIDTH_7BIT              (SPI_CR2_DS_2 | SPI_CR2_DS_1)                               /*!< Data length for SPI transfer:  7 bits */
00233 #define LL_SPI_DATAWIDTH_8BIT              (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)                /*!< Data length for SPI transfer:  8 bits */
00234 #define LL_SPI_DATAWIDTH_9BIT              (SPI_CR2_DS_3)                                              /*!< Data length for SPI transfer:  9 bits */
00235 #define LL_SPI_DATAWIDTH_10BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_0)                               /*!< Data length for SPI transfer: 10 bits */
00236 #define LL_SPI_DATAWIDTH_11BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_1)                               /*!< Data length for SPI transfer: 11 bits */
00237 #define LL_SPI_DATAWIDTH_12BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0)                /*!< Data length for SPI transfer: 12 bits */
00238 #define LL_SPI_DATAWIDTH_13BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2)                               /*!< Data length for SPI transfer: 13 bits */
00239 #define LL_SPI_DATAWIDTH_14BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0)                /*!< Data length for SPI transfer: 14 bits */
00240 #define LL_SPI_DATAWIDTH_15BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1)                /*!< Data length for SPI transfer: 15 bits */
00241 #define LL_SPI_DATAWIDTH_16BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 16 bits */
00242 /**
00243   * @}
00244   */
00245 #if defined(USE_FULL_LL_DRIVER)
00246
00247 /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
00248   * @{
00249   */
00250 #define LL_SPI_CRCCALCULATION_DISABLE      0x00000000U               /*!< CRC calculation disabled */
00251 #define LL_SPI_CRCCALCULATION_ENABLE       (SPI_CR1_CRCEN)           /*!< CRC calculation enabled  */
00252 /**
00253   * @}
00254   */
00255 #endif /* USE_FULL_LL_DRIVER */
00256
00257 /** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length
00258   * @{
00259   */
00260 #define LL_SPI_CRC_8BIT                    0x00000000U               /*!<  8-bit CRC length */
00261 #define LL_SPI_CRC_16BIT                   (SPI_CR1_CRCL)            /*!< 16-bit CRC length */
00262 /**
00263   * @}
00264   */
00265
00266 /** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
00267   * @{
00268   */
00269 #define LL_SPI_RX_FIFO_TH_HALF             0x00000000U               /*!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) */
00270 #define LL_SPI_RX_FIFO_TH_QUARTER          (SPI_CR2_FRXTH)           /*!< RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit)  */
00271 /**
00272   * @}
00273   */
00274
00275 /** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level
00276   * @{
00277   */
00278 #define LL_SPI_RX_FIFO_EMPTY               0x00000000U                       /*!< FIFO reception empty */
00279 #define LL_SPI_RX_FIFO_QUARTER_FULL        (SPI_SR_FRLVL_0)                  /*!< FIFO reception 1/4   */
00280 #define LL_SPI_RX_FIFO_HALF_FULL           (SPI_SR_FRLVL_1)                  /*!< FIFO reception 1/2   */
00281 #define LL_SPI_RX_FIFO_FULL                (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception full  */
00282 /**
00283   * @}
00284   */
00285
00286 /** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level
00287   * @{
00288   */
00289 #define LL_SPI_TX_FIFO_EMPTY               0x00000000U                       /*!< FIFO transmission empty */
00290 #define LL_SPI_TX_FIFO_QUARTER_FULL        (SPI_SR_FTLVL_0)                  /*!< FIFO transmission 1/4   */
00291 #define LL_SPI_TX_FIFO_HALF_FULL           (SPI_SR_FTLVL_1)                  /*!< FIFO transmission 1/2   */
00292 #define LL_SPI_TX_FIFO_FULL                (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission full  */
00293 /**
00294   * @}
00295   */
00296
00297 /** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity
00298   * @{
00299   */
00300 #define LL_SPI_DMA_PARITY_EVEN             0x00000000U   /*!< Select DMA parity Even */
00301 #define LL_SPI_DMA_PARITY_ODD              0x00000001U   /*!< Select DMA parity Odd  */
00302
00303 /**
00304   * @}
00305   */
00306
00307 /**
00308   * @}
00309   */
00310
00311 /* Exported macro ------------------------------------------------------------*/
00312 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
00313   * @{
00314   */
00315
00316 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
00317   * @{
00318   */
00319
00320 /**
00321   * @brief  Write a value in SPI register
00322   * @param  __INSTANCE__ SPI Instance
00323   * @param  __REG__ Register to be written
00324   * @param  __VALUE__ Value to be written in the register
00325   * @retval None
00326   */
00327 #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00328
00329 /**
00330   * @brief  Read a value in SPI register
00331   * @param  __INSTANCE__ SPI Instance
00332   * @param  __REG__ Register to be read
00333   * @retval Register value
00334   */
00335 #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00336 /**
00337   * @}
00338   */
00339
00340 /**
00341   * @}
00342   */
00343
00344 /* Exported functions --------------------------------------------------------*/
00345 /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
00346   * @{
00347   */
00348
00349 /** @defgroup SPI_LL_EF_Configuration Configuration
00350   * @{
00351   */
00352
00353 /**
00354   * @brief  Enable SPI peripheral
00355   * @rmtoll CR1          SPE           LL_SPI_Enable
00356   * @param  SPIx SPI Instance
00357   * @retval None
00358   */
00359 __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
00360 {
00361   SET_BIT(SPIx->CR1, SPI_CR1_SPE);
00362 }
00363
00364 /**
00365   * @brief  Disable SPI peripheral
00366   * @note   When disabling the SPI, follow the procedure described in the Reference Manual.
00367   * @rmtoll CR1          SPE           LL_SPI_Disable
00368   * @param  SPIx SPI Instance
00369   * @retval None
00370   */
00371 __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
00372 {
00373   CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
00374 }
00375
00376 /**
00377   * @brief  Check if SPI peripheral is enabled
00378   * @rmtoll CR1          SPE           LL_SPI_IsEnabled
00379   * @param  SPIx SPI Instance
00380   * @retval State of bit (1 or 0).
00381   */
00382 __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
00383 {
00384   return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
00385 }
00386
00387 /**
00388   * @brief  Set SPI operation mode to Master or Slave
00389   * @note   This bit should not be changed when communication is ongoing.
00390   * @rmtoll CR1          MSTR          LL_SPI_SetMode\n
00391   *         CR1          SSI           LL_SPI_SetMode
00392   * @param  SPIx SPI Instance
00393   * @param  Mode This parameter can be one of the following values:
00394   *         @arg @ref LL_SPI_MODE_MASTER
00395   *         @arg @ref LL_SPI_MODE_SLAVE
00396   * @retval None
00397   */
00398 __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
00399 {
00400   MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
00401 }
00402
00403 /**
00404   * @brief  Get SPI operation mode (Master or Slave)
00405   * @rmtoll CR1          MSTR          LL_SPI_GetMode\n
00406   *         CR1          SSI           LL_SPI_GetMode
00407   * @param  SPIx SPI Instance
00408   * @retval Returned value can be one of the following values:
00409   *         @arg @ref LL_SPI_MODE_MASTER
00410   *         @arg @ref LL_SPI_MODE_SLAVE
00411   */
00412 __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
00413 {
00414   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
00415 }
00416
00417 /**
00418   * @brief  Set serial protocol used
00419   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
00420   * @rmtoll CR2          FRF           LL_SPI_SetStandard
00421   * @param  SPIx SPI Instance
00422   * @param  Standard This parameter can be one of the following values:
00423   *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA
00424   *         @arg @ref LL_SPI_PROTOCOL_TI
00425   * @retval None
00426   */
00427 __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
00428 {
00429   MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
00430 }
00431
00432 /**
00433   * @brief  Get serial protocol used
00434   * @rmtoll CR2          FRF           LL_SPI_GetStandard
00435   * @param  SPIx SPI Instance
00436   * @retval Returned value can be one of the following values:
00437   *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA
00438   *         @arg @ref LL_SPI_PROTOCOL_TI
00439   */
00440 __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
00441 {
00442   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
00443 }
00444
00445 /**
00446   * @brief  Set clock phase
00447   * @note   This bit should not be changed when communication is ongoing.
00448   *         This bit is not used in SPI TI mode.
00449   * @rmtoll CR1          CPHA          LL_SPI_SetClockPhase
00450   * @param  SPIx SPI Instance
00451   * @param  ClockPhase This parameter can be one of the following values:
00452   *         @arg @ref LL_SPI_PHASE_1EDGE
00453   *         @arg @ref LL_SPI_PHASE_2EDGE
00454   * @retval None
00455   */
00456 __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
00457 {
00458   MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
00459 }
00460
00461 /**
00462   * @brief  Get clock phase
00463   * @rmtoll CR1          CPHA          LL_SPI_GetClockPhase
00464   * @param  SPIx SPI Instance
00465   * @retval Returned value can be one of the following values:
00466   *         @arg @ref LL_SPI_PHASE_1EDGE
00467   *         @arg @ref LL_SPI_PHASE_2EDGE
00468   */
00469 __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
00470 {
00471   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
00472 }
00473
00474 /**
00475   * @brief  Set clock polarity
00476   * @note   This bit should not be changed when communication is ongoing.
00477   *         This bit is not used in SPI TI mode.
00478   * @rmtoll CR1          CPOL          LL_SPI_SetClockPolarity
00479   * @param  SPIx SPI Instance
00480   * @param  ClockPolarity This parameter can be one of the following values:
00481   *         @arg @ref LL_SPI_POLARITY_LOW
00482   *         @arg @ref LL_SPI_POLARITY_HIGH
00483   * @retval None
00484   */
00485 __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
00486 {
00487   MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
00488 }
00489
00490 /**
00491   * @brief  Get clock polarity
00492   * @rmtoll CR1          CPOL          LL_SPI_GetClockPolarity
00493   * @param  SPIx SPI Instance
00494   * @retval Returned value can be one of the following values:
00495   *         @arg @ref LL_SPI_POLARITY_LOW
00496   *         @arg @ref LL_SPI_POLARITY_HIGH
00497   */
00498 __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
00499 {
00500   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
00501 }
00502
00503 /**
00504   * @brief  Set baud rate prescaler
00505   * @note   These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
00506   * @rmtoll CR1          BR            LL_SPI_SetBaudRatePrescaler
00507   * @param  SPIx SPI Instance
00508   * @param  BaudRate This parameter can be one of the following values:
00509   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
00510   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
00511   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
00512   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
00513   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
00514   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
00515   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
00516   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
00517   * @retval None
00518   */
00519 __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
00520 {
00521   MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
00522 }
00523
00524 /**
00525   * @brief  Get baud rate prescaler
00526   * @rmtoll CR1          BR            LL_SPI_GetBaudRatePrescaler
00527   * @param  SPIx SPI Instance
00528   * @retval Returned value can be one of the following values:
00529   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
00530   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
00531   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
00532   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
00533   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
00534   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
00535   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
00536   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
00537   */
00538 __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
00539 {
00540   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
00541 }
00542
00543 /**
00544   * @brief  Set transfer bit order
00545   * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
00546   * @rmtoll CR1          LSBFIRST      LL_SPI_SetTransferBitOrder
00547   * @param  SPIx SPI Instance
00548   * @param  BitOrder This parameter can be one of the following values:
00549   *         @arg @ref LL_SPI_LSB_FIRST
00550   *         @arg @ref LL_SPI_MSB_FIRST
00551   * @retval None
00552   */
00553 __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
00554 {
00555   MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
00556 }
00557
00558 /**
00559   * @brief  Get transfer bit order
00560   * @rmtoll CR1          LSBFIRST      LL_SPI_GetTransferBitOrder
00561   * @param  SPIx SPI Instance
00562   * @retval Returned value can be one of the following values:
00563   *         @arg @ref LL_SPI_LSB_FIRST
00564   *         @arg @ref LL_SPI_MSB_FIRST
00565   */
00566 __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
00567 {
00568   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
00569 }
00570
00571 /**
00572   * @brief  Set transfer direction mode
00573   * @note   For Half-Duplex mode, Rx Direction is set by default.
00574   *         In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
00575   * @rmtoll CR1          RXONLY        LL_SPI_SetTransferDirection\n
00576   *         CR1          BIDIMODE      LL_SPI_SetTransferDirection\n
00577   *         CR1          BIDIOE        LL_SPI_SetTransferDirection
00578   * @param  SPIx SPI Instance
00579   * @param  TransferDirection This parameter can be one of the following values:
00580   *         @arg @ref LL_SPI_FULL_DUPLEX
00581   *         @arg @ref LL_SPI_SIMPLEX_RX
00582   *         @arg @ref LL_SPI_HALF_DUPLEX_RX
00583   *         @arg @ref LL_SPI_HALF_DUPLEX_TX
00584   * @retval None
00585   */
00586 __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
00587 {
00588   MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
00589 }
00590
00591 /**
00592   * @brief  Get transfer direction mode
00593   * @rmtoll CR1          RXONLY        LL_SPI_GetTransferDirection\n
00594   *         CR1          BIDIMODE      LL_SPI_GetTransferDirection\n
00595   *         CR1          BIDIOE        LL_SPI_GetTransferDirection
00596   * @param  SPIx SPI Instance
00597   * @retval Returned value can be one of the following values:
00598   *         @arg @ref LL_SPI_FULL_DUPLEX
00599   *         @arg @ref LL_SPI_SIMPLEX_RX
00600   *         @arg @ref LL_SPI_HALF_DUPLEX_RX
00601   *         @arg @ref LL_SPI_HALF_DUPLEX_TX
00602   */
00603 __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
00604 {
00605   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
00606 }
00607
00608 /**
00609   * @brief  Set frame data width
00610   * @rmtoll CR2          DS            LL_SPI_SetDataWidth
00611   * @param  SPIx SPI Instance
00612   * @param  DataWidth This parameter can be one of the following values:
00613   *         @arg @ref LL_SPI_DATAWIDTH_4BIT
00614   *         @arg @ref LL_SPI_DATAWIDTH_5BIT
00615   *         @arg @ref LL_SPI_DATAWIDTH_6BIT
00616   *         @arg @ref LL_SPI_DATAWIDTH_7BIT
00617   *         @arg @ref LL_SPI_DATAWIDTH_8BIT
00618   *         @arg @ref LL_SPI_DATAWIDTH_9BIT
00619   *         @arg @ref LL_SPI_DATAWIDTH_10BIT
00620   *         @arg @ref LL_SPI_DATAWIDTH_11BIT
00621   *         @arg @ref LL_SPI_DATAWIDTH_12BIT
00622   *         @arg @ref LL_SPI_DATAWIDTH_13BIT
00623   *         @arg @ref LL_SPI_DATAWIDTH_14BIT
00624   *         @arg @ref LL_SPI_DATAWIDTH_15BIT
00625   *         @arg @ref LL_SPI_DATAWIDTH_16BIT
00626   * @retval None
00627   */
00628 __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
00629 {
00630   MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth);
00631 }
00632
00633 /**
00634   * @brief  Get frame data width
00635   * @rmtoll CR2          DS            LL_SPI_GetDataWidth
00636   * @param  SPIx SPI Instance
00637   * @retval Returned value can be one of the following values:
00638   *         @arg @ref LL_SPI_DATAWIDTH_4BIT
00639   *         @arg @ref LL_SPI_DATAWIDTH_5BIT
00640   *         @arg @ref LL_SPI_DATAWIDTH_6BIT
00641   *         @arg @ref LL_SPI_DATAWIDTH_7BIT
00642   *         @arg @ref LL_SPI_DATAWIDTH_8BIT
00643   *         @arg @ref LL_SPI_DATAWIDTH_9BIT
00644   *         @arg @ref LL_SPI_DATAWIDTH_10BIT
00645   *         @arg @ref LL_SPI_DATAWIDTH_11BIT
00646   *         @arg @ref LL_SPI_DATAWIDTH_12BIT
00647   *         @arg @ref LL_SPI_DATAWIDTH_13BIT
00648   *         @arg @ref LL_SPI_DATAWIDTH_14BIT
00649   *         @arg @ref LL_SPI_DATAWIDTH_15BIT
00650   *         @arg @ref LL_SPI_DATAWIDTH_16BIT
00651   */
00652 __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
00653 {
00654   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS));
00655 }
00656
00657 /**
00658   * @brief  Set threshold of RXFIFO that triggers an RXNE event
00659   * @rmtoll CR2          FRXTH         LL_SPI_SetRxFIFOThreshold
00660   * @param  SPIx SPI Instance
00661   * @param  Threshold This parameter can be one of the following values:
00662   *         @arg @ref LL_SPI_RX_FIFO_TH_HALF
00663   *         @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
00664   * @retval None
00665   */
00666 __STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
00667 {
00668   MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold);
00669 }
00670
00671 /**
00672   * @brief  Get threshold of RXFIFO that triggers an RXNE event
00673   * @rmtoll CR2          FRXTH         LL_SPI_GetRxFIFOThreshold
00674   * @param  SPIx SPI Instance
00675   * @retval Returned value can be one of the following values:
00676   *         @arg @ref LL_SPI_RX_FIFO_TH_HALF
00677   *         @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
00678   */
00679 __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx)
00680 {
00681   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH));
00682 }
00683
00684 /**
00685   * @}
00686   */
00687
00688 /** @defgroup SPI_LL_EF_CRC_Management CRC Management
00689   * @{
00690   */
00691
00692 /**
00693   * @brief  Enable CRC
00694   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
00695   * @rmtoll CR1          CRCEN         LL_SPI_EnableCRC
00696   * @param  SPIx SPI Instance
00697   * @retval None
00698   */
00699 __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
00700 {
00701   SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
00702 }
00703
00704 /**
00705   * @brief  Disable CRC
00706   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
00707   * @rmtoll CR1          CRCEN         LL_SPI_DisableCRC
00708   * @param  SPIx SPI Instance
00709   * @retval None
00710   */
00711 __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
00712 {
00713   CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
00714 }
00715
00716 /**
00717   * @brief  Check if CRC is enabled
00718   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
00719   * @rmtoll CR1          CRCEN         LL_SPI_IsEnabledCRC
00720   * @param  SPIx SPI Instance
00721   * @retval State of bit (1 or 0).
00722   */
00723 __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
00724 {
00725   return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
00726 }
00727
00728 /**
00729   * @brief  Set CRC Length
00730   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
00731   * @rmtoll CR1          CRCL          LL_SPI_SetCRCWidth
00732   * @param  SPIx SPI Instance
00733   * @param  CRCLength This parameter can be one of the following values:
00734   *         @arg @ref LL_SPI_CRC_8BIT
00735   *         @arg @ref LL_SPI_CRC_16BIT
00736   * @retval None
00737   */
00738 __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
00739 {
00740   MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength);
00741 }
00742
00743 /**
00744   * @brief  Get CRC Length
00745   * @rmtoll CR1          CRCL          LL_SPI_GetCRCWidth
00746   * @param  SPIx SPI Instance
00747   * @retval Returned value can be one of the following values:
00748   *         @arg @ref LL_SPI_CRC_8BIT
00749   *         @arg @ref LL_SPI_CRC_16BIT
00750   */
00751 __STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
00752 {
00753   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL));
00754 }
00755
00756 /**
00757   * @brief  Set CRCNext to transfer CRC on the line
00758   * @note   This bit has to be written as soon as the last data is written in the SPIx_DR register.
00759   * @rmtoll CR1          CRCNEXT       LL_SPI_SetCRCNext
00760   * @param  SPIx SPI Instance
00761   * @retval None
00762   */
00763 __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
00764 {
00765   SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
00766 }
00767
00768 /**
00769   * @brief  Set polynomial for CRC calculation
00770   * @rmtoll CRCPR        CRCPOLY       LL_SPI_SetCRCPolynomial
00771   * @param  SPIx SPI Instance
00772   * @param  CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
00773   * @retval None
00774   */
00775 __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
00776 {
00777   WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
00778 }
00779
00780 /**
00781   * @brief  Get polynomial for CRC calculation
00782   * @rmtoll CRCPR        CRCPOLY       LL_SPI_GetCRCPolynomial
00783   * @param  SPIx SPI Instance
00784   * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
00785   */
00786 __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
00787 {
00788   return (uint32_t)(READ_REG(SPIx->CRCPR));
00789 }
00790
00791 /**
00792   * @brief  Get Rx CRC
00793   * @rmtoll RXCRCR       RXCRC         LL_SPI_GetRxCRC
00794   * @param  SPIx SPI Instance
00795   * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
00796   */
00797 __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
00798 {
00799   return (uint32_t)(READ_REG(SPIx->RXCRCR));
00800 }
00801
00802 /**
00803   * @brief  Get Tx CRC
00804   * @rmtoll TXCRCR       TXCRC         LL_SPI_GetTxCRC
00805   * @param  SPIx SPI Instance
00806   * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
00807   */
00808 __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
00809 {
00810   return (uint32_t)(READ_REG(SPIx->TXCRCR));
00811 }
00812
00813 /**
00814   * @}
00815   */
00816
00817 /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
00818   * @{
00819   */
00820
00821 /**
00822   * @brief  Set NSS mode
00823   * @note   LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
00824   * @rmtoll CR1          SSM           LL_SPI_SetNSSMode\n
00825   * @rmtoll CR2          SSOE          LL_SPI_SetNSSMode
00826   * @param  SPIx SPI Instance
00827   * @param  NSS This parameter can be one of the following values:
00828   *         @arg @ref LL_SPI_NSS_SOFT
00829   *         @arg @ref LL_SPI_NSS_HARD_INPUT
00830   *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
00831   * @retval None
00832   */
00833 __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
00834 {
00835   MODIFY_REG(SPIx->CR1, SPI_CR1_SSM,  NSS);
00836   MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
00837 }
00838
00839 /**
00840   * @brief  Get NSS mode
00841   * @rmtoll CR1          SSM           LL_SPI_GetNSSMode\n
00842   * @rmtoll CR2          SSOE          LL_SPI_GetNSSMode
00843   * @param  SPIx SPI Instance
00844   * @retval Returned value can be one of the following values:
00845   *         @arg @ref LL_SPI_NSS_SOFT
00846   *         @arg @ref LL_SPI_NSS_HARD_INPUT
00847   *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
00848   */
00849 __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
00850 {
00851   register uint32_t Ssm  = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
00852   register uint32_t Ssoe = (READ_BIT(SPIx->CR2,  SPI_CR2_SSOE) << 16U);
00853   return (Ssm | Ssoe);
00854 }
00855
00856 /**
00857   * @brief  Enable NSS pulse management
00858   * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
00859   * @rmtoll CR2          NSSP          LL_SPI_EnableNSSPulseMgt
00860   * @param  SPIx SPI Instance
00861   * @retval None
00862   */
00863 __STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
00864 {
00865   SET_BIT(SPIx->CR2, SPI_CR2_NSSP);
00866 }
00867
00868 /**
00869   * @brief  Disable NSS pulse management
00870   * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
00871   * @rmtoll CR2          NSSP          LL_SPI_DisableNSSPulseMgt
00872   * @param  SPIx SPI Instance
00873   * @retval None
00874   */
00875 __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
00876 {
00877   CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP);
00878 }
00879
00880 /**
00881   * @brief  Check if NSS pulse is enabled
00882   * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
00883   * @rmtoll CR2          NSSP          LL_SPI_IsEnabledNSSPulse
00884   * @param  SPIx SPI Instance
00885   * @retval State of bit (1 or 0).
00886   */
00887 __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
00888 {
00889   return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL);
00890 }
00891
00892 /**
00893   * @}
00894   */
00895
00896 /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
00897   * @{
00898   */
00899
00900 /**
00901   * @brief  Check if Rx buffer is not empty
00902   * @rmtoll SR           RXNE          LL_SPI_IsActiveFlag_RXNE
00903   * @param  SPIx SPI Instance
00904   * @retval State of bit (1 or 0).
00905   */
00906 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
00907 {
00908   return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
00909 }
00910
00911 /**
00912   * @brief  Check if Tx buffer is empty
00913   * @rmtoll SR           TXE           LL_SPI_IsActiveFlag_TXE
00914   * @param  SPIx SPI Instance
00915   * @retval State of bit (1 or 0).
00916   */
00917 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
00918 {
00919   return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
00920 }
00921
00922 /**
00923   * @brief  Get CRC error flag
00924   * @rmtoll SR           CRCERR        LL_SPI_IsActiveFlag_CRCERR
00925   * @param  SPIx SPI Instance
00926   * @retval State of bit (1 or 0).
00927   */
00928 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
00929 {
00930   return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
00931 }
00932
00933 /**
00934   * @brief  Get mode fault error flag
00935   * @rmtoll SR           MODF          LL_SPI_IsActiveFlag_MODF
00936   * @param  SPIx SPI Instance
00937   * @retval State of bit (1 or 0).
00938   */
00939 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
00940 {
00941   return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
00942 }
00943
00944 /**
00945   * @brief  Get overrun error flag
00946   * @rmtoll SR           OVR           LL_SPI_IsActiveFlag_OVR
00947   * @param  SPIx SPI Instance
00948   * @retval State of bit (1 or 0).
00949   */
00950 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
00951 {
00952   return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
00953 }
00954
00955 /**
00956   * @brief  Get busy flag
00957   * @note   The BSY flag is cleared under any one of the following conditions:
00958   * -When the SPI is correctly disabled
00959   * -When a fault is detected in Master mode (MODF bit set to 1)
00960   * -In Master mode, when it finishes a data transmission and no new data is ready to be
00961   * sent
00962   * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
00963   * each data transfer.
00964   * @rmtoll SR           BSY           LL_SPI_IsActiveFlag_BSY
00965   * @param  SPIx SPI Instance
00966   * @retval State of bit (1 or 0).
00967   */
00968 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
00969 {
00970   return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
00971 }
00972
00973 /**
00974   * @brief  Get frame format error flag
00975   * @rmtoll SR           FRE           LL_SPI_IsActiveFlag_FRE
00976   * @param  SPIx SPI Instance
00977   * @retval State of bit (1 or 0).
00978   */
00979 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
00980 {
00981   return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL);
00982 }
00983
00984 /**
00985   * @brief  Get FIFO reception Level
00986   * @rmtoll SR           FRLVL         LL_SPI_GetRxFIFOLevel
00987   * @param  SPIx SPI Instance
00988   * @retval Returned value can be one of the following values:
00989   *         @arg @ref LL_SPI_RX_FIFO_EMPTY
00990   *         @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL
00991   *         @arg @ref LL_SPI_RX_FIFO_HALF_FULL
00992   *         @arg @ref LL_SPI_RX_FIFO_FULL
00993   */
00994 __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx)
00995 {
00996   return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL));
00997 }
00998
00999 /**
01000   * @brief  Get FIFO Transmission Level
01001   * @rmtoll SR           FTLVL         LL_SPI_GetTxFIFOLevel
01002   * @param  SPIx SPI Instance
01003   * @retval Returned value can be one of the following values:
01004   *         @arg @ref LL_SPI_TX_FIFO_EMPTY
01005   *         @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL
01006   *         @arg @ref LL_SPI_TX_FIFO_HALF_FULL
01007   *         @arg @ref LL_SPI_TX_FIFO_FULL
01008   */
01009 __STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx)
01010 {
01011   return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL));
01012 }
01013
01014 /**
01015   * @brief  Clear CRC error flag
01016   * @rmtoll SR           CRCERR        LL_SPI_ClearFlag_CRCERR
01017   * @param  SPIx SPI Instance
01018   * @retval None
01019   */
01020 __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
01021 {
01022   CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
01023 }
01024
01025 /**
01026   * @brief  Clear mode fault error flag
01027   * @note   Clearing this flag is done by a read access to the SPIx_SR
01028   *         register followed by a write access to the SPIx_CR1 register
01029   * @rmtoll SR           MODF          LL_SPI_ClearFlag_MODF
01030   * @param  SPIx SPI Instance
01031   * @retval None
01032   */
01033 __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
01034 {
01035   __IO uint32_t tmpreg_sr;
01036   tmpreg_sr = SPIx->SR;
01037   (void) tmpreg_sr;
01038   CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
01039 }
01040
01041 /**
01042   * @brief  Clear overrun error flag
01043   * @note   Clearing this flag is done by a read access to the SPIx_DR
01044   *         register followed by a read access to the SPIx_SR register
01045   * @rmtoll SR           OVR           LL_SPI_ClearFlag_OVR
01046   * @param  SPIx SPI Instance
01047   * @retval None
01048   */
01049 __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
01050 {
01051   __IO uint32_t tmpreg;
01052   tmpreg = SPIx->DR;
01053   (void) tmpreg;
01054   tmpreg = SPIx->SR;
01055   (void) tmpreg;
01056 }
01057
01058 /**
01059   * @brief  Clear frame format error flag
01060   * @note   Clearing this flag is done by reading SPIx_SR register
01061   * @rmtoll SR           FRE           LL_SPI_ClearFlag_FRE
01062   * @param  SPIx SPI Instance
01063   * @retval None
01064   */
01065 __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
01066 {
01067   __IO uint32_t tmpreg;
01068   tmpreg = SPIx->SR;
01069   (void) tmpreg;
01070 }
01071
01072 /**
01073   * @}
01074   */
01075
01076 /** @defgroup SPI_LL_EF_IT_Management Interrupt Management
01077   * @{
01078   */
01079
01080 /**
01081   * @brief  Enable error interrupt
01082   * @note   This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
01083   * @rmtoll CR2          ERRIE         LL_SPI_EnableIT_ERR
01084   * @param  SPIx SPI Instance
01085   * @retval None
01086   */
01087 __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
01088 {
01089   SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
01090 }
01091
01092 /**
01093   * @brief  Enable Rx buffer not empty interrupt
01094   * @rmtoll CR2          RXNEIE        LL_SPI_EnableIT_RXNE
01095   * @param  SPIx SPI Instance
01096   * @retval None
01097   */
01098 __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
01099 {
01100   SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
01101 }
01102
01103 /**
01104   * @brief  Enable Tx buffer empty interrupt
01105   * @rmtoll CR2          TXEIE         LL_SPI_EnableIT_TXE
01106   * @param  SPIx SPI Instance
01107   * @retval None
01108   */
01109 __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
01110 {
01111   SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
01112 }
01113
01114 /**
01115   * @brief  Disable error interrupt
01116   * @note   This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
01117   * @rmtoll CR2          ERRIE         LL_SPI_DisableIT_ERR
01118   * @param  SPIx SPI Instance
01119   * @retval None
01120   */
01121 __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
01122 {
01123   CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
01124 }
01125
01126 /**
01127   * @brief  Disable Rx buffer not empty interrupt
01128   * @rmtoll CR2          RXNEIE        LL_SPI_DisableIT_RXNE
01129   * @param  SPIx SPI Instance
01130   * @retval None
01131   */
01132 __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
01133 {
01134   CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
01135 }
01136
01137 /**
01138   * @brief  Disable Tx buffer empty interrupt
01139   * @rmtoll CR2          TXEIE         LL_SPI_DisableIT_TXE
01140   * @param  SPIx SPI Instance
01141   * @retval None
01142   */
01143 __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
01144 {
01145   CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
01146 }
01147
01148 /**
01149   * @brief  Check if error interrupt is enabled
01150   * @rmtoll CR2          ERRIE         LL_SPI_IsEnabledIT_ERR
01151   * @param  SPIx SPI Instance
01152   * @retval State of bit (1 or 0).
01153   */
01154 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
01155 {
01156   return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
01157 }
01158
01159 /**
01160   * @brief  Check if Rx buffer not empty interrupt is enabled
01161   * @rmtoll CR2          RXNEIE        LL_SPI_IsEnabledIT_RXNE
01162   * @param  SPIx SPI Instance
01163   * @retval State of bit (1 or 0).
01164   */
01165 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
01166 {
01167   return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL);
01168 }
01169
01170 /**
01171   * @brief  Check if Tx buffer empty interrupt
01172   * @rmtoll CR2          TXEIE         LL_SPI_IsEnabledIT_TXE
01173   * @param  SPIx SPI Instance
01174   * @retval State of bit (1 or 0).
01175   */
01176 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
01177 {
01178   return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
01179 }
01180
01181 /**
01182   * @}
01183   */
01184
01185 /** @defgroup SPI_LL_EF_DMA_Management DMA Management
01186   * @{
01187   */
01188
01189 /**
01190   * @brief  Enable DMA Rx
01191   * @rmtoll CR2          RXDMAEN       LL_SPI_EnableDMAReq_RX
01192   * @param  SPIx SPI Instance
01193   * @retval None
01194   */
01195 __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
01196 {
01197   SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
01198 }
01199
01200 /**
01201   * @brief  Disable DMA Rx
01202   * @rmtoll CR2          RXDMAEN       LL_SPI_DisableDMAReq_RX
01203   * @param  SPIx SPI Instance
01204   * @retval None
01205   */
01206 __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
01207 {
01208   CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
01209 }
01210
01211 /**
01212   * @brief  Check if DMA Rx is enabled
01213   * @rmtoll CR2          RXDMAEN       LL_SPI_IsEnabledDMAReq_RX
01214   * @param  SPIx SPI Instance
01215   * @retval State of bit (1 or 0).
01216   */
01217 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
01218 {
01219   return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL);
01220 }
01221
01222 /**
01223   * @brief  Enable DMA Tx
01224   * @rmtoll CR2          TXDMAEN       LL_SPI_EnableDMAReq_TX
01225   * @param  SPIx SPI Instance
01226   * @retval None
01227   */
01228 __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
01229 {
01230   SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
01231 }
01232
01233 /**
01234   * @brief  Disable DMA Tx
01235   * @rmtoll CR2          TXDMAEN       LL_SPI_DisableDMAReq_TX
01236   * @param  SPIx SPI Instance
01237   * @retval None
01238   */
01239 __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
01240 {
01241   CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
01242 }
01243
01244 /**
01245   * @brief  Check if DMA Tx is enabled
01246   * @rmtoll CR2          TXDMAEN       LL_SPI_IsEnabledDMAReq_TX
01247   * @param  SPIx SPI Instance
01248   * @retval State of bit (1 or 0).
01249   */
01250 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
01251 {
01252   return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL);
01253 }
01254
01255 /**
01256   * @brief  Set parity of  Last DMA reception
01257   * @rmtoll CR2          LDMARX        LL_SPI_SetDMAParity_RX
01258   * @param  SPIx SPI Instance
01259   * @param  Parity This parameter can be one of the following values:
01260   *         @arg @ref LL_SPI_DMA_PARITY_ODD
01261   *         @arg @ref LL_SPI_DMA_PARITY_EVEN
01262   * @retval None
01263   */
01264 __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity)
01265 {
01266   MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos));
01267 }
01268
01269 /**
01270   * @brief  Get parity configuration for  Last DMA reception
01271   * @rmtoll CR2          LDMARX        LL_SPI_GetDMAParity_RX
01272   * @param  SPIx SPI Instance
01273   * @retval Returned value can be one of the following values:
01274   *         @arg @ref LL_SPI_DMA_PARITY_ODD
01275   *         @arg @ref LL_SPI_DMA_PARITY_EVEN
01276   */
01277 __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx)
01278 {
01279   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos);
01280 }
01281
01282 /**
01283   * @brief  Set parity of  Last DMA transmission
01284   * @rmtoll CR2          LDMATX        LL_SPI_SetDMAParity_TX
01285   * @param  SPIx SPI Instance
01286   * @param  Parity This parameter can be one of the following values:
01287   *         @arg @ref LL_SPI_DMA_PARITY_ODD
01288   *         @arg @ref LL_SPI_DMA_PARITY_EVEN
01289   * @retval None
01290   */
01291 __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity)
01292 {
01293   MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos));
01294 }
01295
01296 /**
01297   * @brief  Get parity configuration for Last DMA transmission
01298   * @rmtoll CR2          LDMATX        LL_SPI_GetDMAParity_TX
01299   * @param  SPIx SPI Instance
01300   * @retval Returned value can be one of the following values:
01301   *         @arg @ref LL_SPI_DMA_PARITY_ODD
01302   *         @arg @ref LL_SPI_DMA_PARITY_EVEN
01303   */
01304 __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx)
01305 {
01306   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos);
01307 }
01308
01309 /**
01310   * @brief  Get the data register address used for DMA transfer
01311   * @rmtoll DR           DR            LL_SPI_DMA_GetRegAddr
01312   * @param  SPIx SPI Instance
01313   * @retval Address of data register
01314   */
01315 __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
01316 {
01317   return (uint32_t) &(SPIx->DR);
01318 }
01319
01320 /**
01321   * @}
01322   */
01323
01324 /** @defgroup SPI_LL_EF_DATA_Management DATA Management
01325   * @{
01326   */
01327
01328 /**
01329   * @brief  Read 8-Bits in the data register
01330   * @rmtoll DR           DR            LL_SPI_ReceiveData8
01331   * @param  SPIx SPI Instance
01332   * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
01333   */
01334 __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
01335 {
01336   return (uint8_t)(READ_REG(SPIx->DR));
01337 }
01338
01339 /**
01340   * @brief  Read 16-Bits in the data register
01341   * @rmtoll DR           DR            LL_SPI_ReceiveData16
01342   * @param  SPIx SPI Instance
01343   * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
01344   */
01345 __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
01346 {
01347   return (uint16_t)(READ_REG(SPIx->DR));
01348 }
01349
01350 /**
01351   * @brief  Write 8-Bits in the data register
01352   * @rmtoll DR           DR            LL_SPI_TransmitData8
01353   * @param  SPIx SPI Instance
01354   * @param  TxData Value between Min_Data=0x00 and Max_Data=0xFF
01355   * @retval None
01356   */
01357 __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
01358 {
01359 #if defined (__GNUC__)
01360   __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
01361   *spidr = TxData;
01362 #else
01363   *((__IO uint8_t *)&SPIx->DR) = TxData;
01364 #endif /* __GNUC__ */
01365 }
01366
01367 /**
01368   * @brief  Write 16-Bits in the data register
01369   * @rmtoll DR           DR            LL_SPI_TransmitData16
01370   * @param  SPIx SPI Instance
01371   * @param  TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
01372   * @retval None
01373   */
01374 __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
01375 {
01376 #if defined (__GNUC__)
01377   __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
01378   *spidr = TxData;
01379 #else
01380   SPIx->DR = TxData;
01381 #endif /* __GNUC__ */
01382 }
01383
01384 /**
01385   * @}
01386   */
01387 #if defined(USE_FULL_LL_DRIVER)
01388 /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
01389   * @{
01390   */
01391
01392 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
01393 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
01394 void        LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
01395
01396 /**
01397   * @}
01398   */
01399 #endif /* USE_FULL_LL_DRIVER */
01400 /**
01401   * @}
01402   */
01403
01404 /**
01405   * @}
01406   */
01407
01408 #endif /* defined (SPI1) || defined (SPI2) */
01409
01410 /**
01411   * @}
01412   */
01413
01414 #ifdef __cplusplus
01415 }
01416 #endif
01417
01418 #endif /* STM32WBxx_LL_SPI_H */
01419
01420 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_system.h Source File

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stm32wbxx_ll_system.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_system.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of SYSTEM LL module.
00006   @verbatim
00007   ==============================================================================
00008                      ##### How to use this driver #####
00009   ==============================================================================
00010     [..]
00011     The LL SYSTEM driver contains a set of generic APIs that can be
00012     used by user:
00013       (+) Some of the FLASH features need to be handled in the SYSTEM file.
00014       (+) Access to DBGCMU registers
00015       (+) Access to SYSCFG registers
00016       (+) Access to VREFBUF registers
00017
00018   @endverbatim
00019   ******************************************************************************
00020   * @attention
00021   *
00022   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00023   * All rights reserved.</center></h2>
00024   *
00025   * This software component is licensed by ST under BSD 3-Clause license,
00026   * the "License"; You may not use this file except in compliance with the
00027   * License. You may obtain a copy of the License at:
00028   *                        opensource.org/licenses/BSD-3-Clause
00029   *
00030   ******************************************************************************
00031   */
00032
00033 /* Define to prevent recursive inclusion -------------------------------------*/
00034 #ifndef STM32WBxx_LL_SYSTEM_H
00035 #define STM32WBxx_LL_SYSTEM_H
00036
00037 #ifdef __cplusplus
00038 extern "C" {
00039 #endif
00040
00041 /* Includes ------------------------------------------------------------------*/
00042 #include "stm32wbxx.h"
00043
00044 /** @addtogroup STM32WBxx_LL_Driver
00045   * @{
00046   */
00047
00048 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF)
00049
00050 /** @defgroup SYSTEM_LL SYSTEM
00051   * @{
00052   */
00053
00054 /* Private types -------------------------------------------------------------*/
00055 /* Private variables ---------------------------------------------------------*/
00056
00057 /* Private constants ---------------------------------------------------------*/
00058 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
00059   * @{
00060   */
00061
00062 /**
00063   * @}
00064   */
00065
00066 /* Private macros ------------------------------------------------------------*/
00067
00068 /* Exported types ------------------------------------------------------------*/
00069 /* Exported constants --------------------------------------------------------*/
00070 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
00071   * @{
00072   */
00073
00074 /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
00075 * @{
00076 */
00077 #define LL_SYSCFG_REMAP_FLASH                   0x00000000U                                           /*!< Main Flash memory mapped at 0x00000000   */
00078 #define LL_SYSCFG_REMAP_SYSTEMFLASH             SYSCFG_MEMRMP_MEM_MODE_0                              /*!< System Flash memory mapped at 0x00000000 */
00079 #define LL_SYSCFG_REMAP_SRAM                    (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000               */
00080 #if defined(QUADSPI)
00081 #define LL_SYSCFG_REMAP_QUADSPI                 (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1) /*!< QUADSPI memory mapped at 0x00000000      */
00082 #endif
00083 /**
00084   * @}
00085   */
00086
00087 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
00088   * @{
00089   */
00090 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6          SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6       */
00091 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7          SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7       */
00092 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8          SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8       */
00093 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9          SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9       */
00094 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1         SYSCFG_CFGR1_I2C1_FMP    /*!< Enable Fast Mode Plus on I2C1 pins */
00095 #if defined(I2C3)
00096 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3         SYSCFG_CFGR1_I2C3_FMP    /*!< Enable Fast Mode Plus on I2C3 pins */
00097 #endif
00098 /**
00099   * @}
00100   */
00101
00102 /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
00103   * @{
00104   */
00105 #define LL_SYSCFG_EXTI_PORTA                    0U /*!< EXTI PORT A */
00106 #define LL_SYSCFG_EXTI_PORTB                    1U /*!< EXTI PORT B */
00107 #define LL_SYSCFG_EXTI_PORTC                    2U /*!< EXTI PORT C */
00108 #define LL_SYSCFG_EXTI_PORTD                    3U /*!< EXTI PORT D */
00109 #define LL_SYSCFG_EXTI_PORTE                    4U /*!< EXTI PORT E */
00110 #define LL_SYSCFG_EXTI_PORTH                    7U /*!< EXTI PORT H */
00111 /**
00112   * @}
00113   */
00114
00115 /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
00116   * @{
00117   */
00118 #define LL_SYSCFG_EXTI_LINE0                    (uint32_t)((0x000FU << 16U) | 0U) /*!< EXTI_POSITION_0  | EXTICR[0] */
00119 #define LL_SYSCFG_EXTI_LINE1                    (uint32_t)((0x00F0U << 16U) | 0U) /*!< EXTI_POSITION_4  | EXTICR[0] */
00120 #define LL_SYSCFG_EXTI_LINE2                    (uint32_t)((0x0F00U << 16U) | 0U) /*!< EXTI_POSITION_8  | EXTICR[0] */
00121 #define LL_SYSCFG_EXTI_LINE3                    (uint32_t)((0xF000U << 16U) | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */
00122 #define LL_SYSCFG_EXTI_LINE4                    (uint32_t)((0x000FU << 16U) | 1U) /*!< EXTI_POSITION_0  | EXTICR[1] */
00123 #define LL_SYSCFG_EXTI_LINE5                    (uint32_t)((0x00F0U << 16U) | 1U) /*!< EXTI_POSITION_4  | EXTICR[1] */
00124 #define LL_SYSCFG_EXTI_LINE6                    (uint32_t)((0x0F00U << 16U) | 1U) /*!< EXTI_POSITION_8  | EXTICR[1] */
00125 #define LL_SYSCFG_EXTI_LINE7                    (uint32_t)((0xF000U << 16U) | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */
00126 #define LL_SYSCFG_EXTI_LINE8                    (uint32_t)((0x000FU << 16U) | 2U) /*!< EXTI_POSITION_0  | EXTICR[2] */
00127 #define LL_SYSCFG_EXTI_LINE9                    (uint32_t)((0x00F0U << 16U) | 2U) /*!< EXTI_POSITION_4  | EXTICR[2] */
00128 #define LL_SYSCFG_EXTI_LINE10                   (uint32_t)((0x0F00U << 16U) | 2U) /*!< EXTI_POSITION_8  | EXTICR[2] */
00129 #define LL_SYSCFG_EXTI_LINE11                   (uint32_t)((0xF000U << 16U) | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */
00130 #define LL_SYSCFG_EXTI_LINE12                   (uint32_t)((0x000FU << 16U) | 3U) /*!< EXTI_POSITION_0  | EXTICR[3] */
00131 #define LL_SYSCFG_EXTI_LINE13                   (uint32_t)((0x00F0U << 16U) | 3U) /*!< EXTI_POSITION_4  | EXTICR[3] */
00132 #define LL_SYSCFG_EXTI_LINE14                   (uint32_t)((0x0F00U << 16U) | 3U) /*!< EXTI_POSITION_8  | EXTICR[3] */
00133 #define LL_SYSCFG_EXTI_LINE15                   (uint32_t)((0xF000U << 16U) | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */
00134 /**
00135   * @}
00136   */
00137
00138 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
00139   * @{
00140   */
00141 #define LL_SYSCFG_TIMBREAK_ECC                  SYSCFG_CFGR2_ECCL       /*!< Enables and locks the ECC error signal
00142                                                                               with Break Input of TIM1/16/17                                */
00143 #define LL_SYSCFG_TIMBREAK_PVD                  SYSCFG_CFGR2_PVDL       /*!< Enables and locks the PVD connection
00144                                                                               with TIM1/16/17 Break Input
00145                                                                               and also the PVDE and PLS bits of the Power Control Interface */
00146 #define LL_SYSCFG_TIMBREAK_SRAM2_PARITY         SYSCFG_CFGR2_SPL        /*!< Enables and locks the SRAM2_PARITY error signal
00147                                                                               with Break Input of TIM1/16/17                                */
00148 #define LL_SYSCFG_TIMBREAK_LOCKUP               SYSCFG_CFGR2_CLL        /*!< Enables and locks the LOCKUP output of CortexM4
00149                                                                               with Break Input of TIM1/16/17                                */
00150 /**
00151   * @}
00152   */
00153
00154 /** @defgroup SYSTEM_LL_EC_SRAM2WRP SYSCFG SRAM2 WRITE PROTECTION
00155   * @{
00156   */
00157 #define LL_SYSCFG_SRAM2WRP_PAGE0                SYSCFG_SWPR1_PAGE0       /*!< SRAM2A Write protection page 0  */
00158 #define LL_SYSCFG_SRAM2WRP_PAGE1                SYSCFG_SWPR1_PAGE1       /*!< SRAM2A Write protection page 1  */
00159 #define LL_SYSCFG_SRAM2WRP_PAGE2                SYSCFG_SWPR1_PAGE2       /*!< SRAM2A Write protection page 2  */
00160 #define LL_SYSCFG_SRAM2WRP_PAGE3                SYSCFG_SWPR1_PAGE3       /*!< SRAM2A Write protection page 3  */
00161 #define LL_SYSCFG_SRAM2WRP_PAGE4                SYSCFG_SWPR1_PAGE4       /*!< SRAM2A Write protection page 4  */
00162 #define LL_SYSCFG_SRAM2WRP_PAGE5                SYSCFG_SWPR1_PAGE5       /*!< SRAM2A Write protection page 5  */
00163 #define LL_SYSCFG_SRAM2WRP_PAGE6                SYSCFG_SWPR1_PAGE6       /*!< SRAM2A Write protection page 6  */
00164 #define LL_SYSCFG_SRAM2WRP_PAGE7                SYSCFG_SWPR1_PAGE7       /*!< SRAM2A Write protection page 7  */
00165 #define LL_SYSCFG_SRAM2WRP_PAGE8                SYSCFG_SWPR1_PAGE8       /*!< SRAM2A Write protection page 8  */
00166 #define LL_SYSCFG_SRAM2WRP_PAGE9                SYSCFG_SWPR1_PAGE9       /*!< SRAM2A Write protection page 9  */
00167 #define LL_SYSCFG_SRAM2WRP_PAGE10               SYSCFG_SWPR1_PAGE10      /*!< SRAM2A Write protection page 10 */
00168 #define LL_SYSCFG_SRAM2WRP_PAGE11               SYSCFG_SWPR1_PAGE11      /*!< SRAM2A Write protection page 11 */
00169 #define LL_SYSCFG_SRAM2WRP_PAGE12               SYSCFG_SWPR1_PAGE12      /*!< SRAM2A Write protection page 12 */
00170 #define LL_SYSCFG_SRAM2WRP_PAGE13               SYSCFG_SWPR1_PAGE13      /*!< SRAM2A Write protection page 13 */
00171 #define LL_SYSCFG_SRAM2WRP_PAGE14               SYSCFG_SWPR1_PAGE14      /*!< SRAM2A Write protection page 14 */
00172 #define LL_SYSCFG_SRAM2WRP_PAGE15               SYSCFG_SWPR1_PAGE15      /*!< SRAM2A Write protection page 15 */
00173 #define LL_SYSCFG_SRAM2WRP_PAGE16               SYSCFG_SWPR1_PAGE16      /*!< SRAM2A Write protection page 16 */
00174 #define LL_SYSCFG_SRAM2WRP_PAGE17               SYSCFG_SWPR1_PAGE17      /*!< SRAM2A Write protection page 17 */
00175 #define LL_SYSCFG_SRAM2WRP_PAGE18               SYSCFG_SWPR1_PAGE18      /*!< SRAM2A Write protection page 18 */
00176 #define LL_SYSCFG_SRAM2WRP_PAGE19               SYSCFG_SWPR1_PAGE19      /*!< SRAM2A Write protection page 19 */
00177 #define LL_SYSCFG_SRAM2WRP_PAGE20               SYSCFG_SWPR1_PAGE20      /*!< SRAM2A Write protection page 20 */
00178 #define LL_SYSCFG_SRAM2WRP_PAGE21               SYSCFG_SWPR1_PAGE21      /*!< SRAM2A Write protection page 21 */
00179 #define LL_SYSCFG_SRAM2WRP_PAGE22               SYSCFG_SWPR1_PAGE22      /*!< SRAM2A Write protection page 22 */
00180 #define LL_SYSCFG_SRAM2WRP_PAGE23               SYSCFG_SWPR1_PAGE23      /*!< SRAM2A Write protection page 23 */
00181 #define LL_SYSCFG_SRAM2WRP_PAGE24               SYSCFG_SWPR1_PAGE24      /*!< SRAM2A Write protection page 24 */
00182 #define LL_SYSCFG_SRAM2WRP_PAGE25               SYSCFG_SWPR1_PAGE25      /*!< SRAM2A Write protection page 25 */
00183 #define LL_SYSCFG_SRAM2WRP_PAGE26               SYSCFG_SWPR1_PAGE26      /*!< SRAM2A Write protection page 26 */
00184 #define LL_SYSCFG_SRAM2WRP_PAGE27               SYSCFG_SWPR1_PAGE27      /*!< SRAM2A Write protection page 27 */
00185 #define LL_SYSCFG_SRAM2WRP_PAGE28               SYSCFG_SWPR1_PAGE28      /*!< SRAM2A Write protection page 28 */
00186 #define LL_SYSCFG_SRAM2WRP_PAGE29               SYSCFG_SWPR1_PAGE29      /*!< SRAM2A Write protection page 29 */
00187 #define LL_SYSCFG_SRAM2WRP_PAGE30               SYSCFG_SWPR1_PAGE30      /*!< SRAM2A Write protection page 30 */
00188 #define LL_SYSCFG_SRAM2WRP_PAGE31               SYSCFG_SWPR1_PAGE31      /*!< SRAM2A Write protection page 31 */
00189
00190 #define LL_SYSCFG_SRAM2WRP_PAGE32               SYSCFG_SWPR2_PAGE32      /*!< SRAM2B Write protection page 32 */
00191 #define LL_SYSCFG_SRAM2WRP_PAGE33               SYSCFG_SWPR2_PAGE33      /*!< SRAM2B Write protection page 33 */
00192 #define LL_SYSCFG_SRAM2WRP_PAGE34               SYSCFG_SWPR2_PAGE34      /*!< SRAM2B Write protection page 34 */
00193 #define LL_SYSCFG_SRAM2WRP_PAGE35               SYSCFG_SWPR2_PAGE35      /*!< SRAM2B Write protection page 35 */
00194 #define LL_SYSCFG_SRAM2WRP_PAGE36               SYSCFG_SWPR2_PAGE36      /*!< SRAM2B Write protection page 36 */
00195 #define LL_SYSCFG_SRAM2WRP_PAGE37               SYSCFG_SWPR2_PAGE37      /*!< SRAM2B Write protection page 37 */
00196 #define LL_SYSCFG_SRAM2WRP_PAGE38               SYSCFG_SWPR2_PAGE38      /*!< SRAM2B Write protection page 38 */
00197 #define LL_SYSCFG_SRAM2WRP_PAGE39               SYSCFG_SWPR2_PAGE39      /*!< SRAM2B Write protection page 39 */
00198 #define LL_SYSCFG_SRAM2WRP_PAGE40               SYSCFG_SWPR2_PAGE40      /*!< SRAM2B Write protection page 40 */
00199 #define LL_SYSCFG_SRAM2WRP_PAGE41               SYSCFG_SWPR2_PAGE41      /*!< SRAM2B Write protection page 41 */
00200 #define LL_SYSCFG_SRAM2WRP_PAGE42               SYSCFG_SWPR2_PAGE42      /*!< SRAM2B Write protection page 42 */
00201 #define LL_SYSCFG_SRAM2WRP_PAGE43               SYSCFG_SWPR2_PAGE43      /*!< SRAM2B Write protection page 43 */
00202 #define LL_SYSCFG_SRAM2WRP_PAGE44               SYSCFG_SWPR2_PAGE44      /*!< SRAM2B Write protection page 44 */
00203 #define LL_SYSCFG_SRAM2WRP_PAGE45               SYSCFG_SWPR2_PAGE45      /*!< SRAM2B Write protection page 45 */
00204 #define LL_SYSCFG_SRAM2WRP_PAGE46               SYSCFG_SWPR2_PAGE46      /*!< SRAM2B Write protection page 46 */
00205 #define LL_SYSCFG_SRAM2WRP_PAGE47               SYSCFG_SWPR2_PAGE47      /*!< SRAM2B Write protection page 47 */
00206 #define LL_SYSCFG_SRAM2WRP_PAGE48               SYSCFG_SWPR2_PAGE48      /*!< SRAM2B Write protection page 48 */
00207 #define LL_SYSCFG_SRAM2WRP_PAGE49               SYSCFG_SWPR2_PAGE49      /*!< SRAM2B Write protection page 49 */
00208 #define LL_SYSCFG_SRAM2WRP_PAGE50               SYSCFG_SWPR2_PAGE50      /*!< SRAM2B Write protection page 50 */
00209 #define LL_SYSCFG_SRAM2WRP_PAGE51               SYSCFG_SWPR2_PAGE51      /*!< SRAM2B Write protection page 51 */
00210 #define LL_SYSCFG_SRAM2WRP_PAGE52               SYSCFG_SWPR2_PAGE52      /*!< SRAM2B Write protection page 52 */
00211 #define LL_SYSCFG_SRAM2WRP_PAGE53               SYSCFG_SWPR2_PAGE53      /*!< SRAM2B Write protection page 53 */
00212 #define LL_SYSCFG_SRAM2WRP_PAGE54               SYSCFG_SWPR2_PAGE54      /*!< SRAM2B Write protection page 54 */
00213 #define LL_SYSCFG_SRAM2WRP_PAGE55               SYSCFG_SWPR2_PAGE55      /*!< SRAM2B Write protection page 55 */
00214 #define LL_SYSCFG_SRAM2WRP_PAGE56               SYSCFG_SWPR2_PAGE56      /*!< SRAM2B Write protection page 56 */
00215 #define LL_SYSCFG_SRAM2WRP_PAGE57               SYSCFG_SWPR2_PAGE57      /*!< SRAM2B Write protection page 57 */
00216 #define LL_SYSCFG_SRAM2WRP_PAGE58               SYSCFG_SWPR2_PAGE58      /*!< SRAM2B Write protection page 58 */
00217 #define LL_SYSCFG_SRAM2WRP_PAGE59               SYSCFG_SWPR2_PAGE59      /*!< SRAM2B Write protection page 59 */
00218 #define LL_SYSCFG_SRAM2WRP_PAGE60               SYSCFG_SWPR2_PAGE60      /*!< SRAM2B Write protection page 60 */
00219 #define LL_SYSCFG_SRAM2WRP_PAGE61               SYSCFG_SWPR2_PAGE61      /*!< SRAM2B Write protection page 61 */
00220 #define LL_SYSCFG_SRAM2WRP_PAGE62               SYSCFG_SWPR2_PAGE62      /*!< SRAM2B Write protection page 62 */
00221 #define LL_SYSCFG_SRAM2WRP_PAGE63               SYSCFG_SWPR2_PAGE63      /*!< SRAM2B Write protection page 63 */
00222 /**
00223   * @}
00224   */
00225
00226 /** @defgroup SYSTEM_LL_EC_IM SYSCFG CPU1 INTERRUPT MASK
00227   * @{
00228   */
00229 #define LL_SYSCFG_GRP1_TIM1                     SYSCFG_IMR1_TIM1IM     /*!< Enabling of interrupt from Timer 1 to CPU1                    */
00230 #define LL_SYSCFG_GRP1_TIM16                    SYSCFG_IMR1_TIM16IM    /*!< Enabling of interrupt from Timer 16 to CPU1                   */
00231 #define LL_SYSCFG_GRP1_TIM17                    SYSCFG_IMR1_TIM17IM    /*!< Enabling of interrupt from Timer 17 to CPU1                   */
00232
00233 #define LL_SYSCFG_GRP1_EXTI5                    SYSCFG_IMR1_EXTI5IM    /*!< Enabling of interrupt from External Interrupt Line 5 to CPU1  */
00234 #define LL_SYSCFG_GRP1_EXTI6                    SYSCFG_IMR1_EXTI6IM    /*!< Enabling of interrupt from External Interrupt Line 6 to CPU1  */
00235 #define LL_SYSCFG_GRP1_EXTI7                    SYSCFG_IMR1_EXTI7IM    /*!< Enabling of interrupt from External Interrupt Line 7 to CPU1  */
00236 #define LL_SYSCFG_GRP1_EXTI8                    SYSCFG_IMR1_EXTI8IM    /*!< Enabling of interrupt from External Interrupt Line 8 to CPU1  */
00237 #define LL_SYSCFG_GRP1_EXTI9                    SYSCFG_IMR1_EXTI9IM    /*!< Enabling of interrupt from External Interrupt Line 9 to CPU1  */
00238 #define LL_SYSCFG_GRP1_EXTI10                   SYSCFG_IMR1_EXTI10IM   /*!< Enabling of interrupt from External Interrupt Line 10 to CPU1 */
00239 #define LL_SYSCFG_GRP1_EXTI11                   SYSCFG_IMR1_EXTI11IM   /*!< Enabling of interrupt from External Interrupt Line 11 to CPU1 */
00240 #define LL_SYSCFG_GRP1_EXTI12                   SYSCFG_IMR1_EXTI12IM   /*!< Enabling of interrupt from External Interrupt Line 12 to CPU1 */
00241 #define LL_SYSCFG_GRP1_EXTI13                   SYSCFG_IMR1_EXTI13IM   /*!< Enabling of interrupt from External Interrupt Line 13 to CPU1 */
00242 #define LL_SYSCFG_GRP1_EXTI14                   SYSCFG_IMR1_EXTI14IM   /*!< Enabling of interrupt from External Interrupt Line 14 to CPU1 */
00243 #define LL_SYSCFG_GRP1_EXTI15                   SYSCFG_IMR1_EXTI15IM   /*!< Enabling of interrupt from External Interrupt Line 15 to CPU1 */
00244
00245 #if defined(SYSCFG_IMR2_PVM1IM)
00246 #define LL_SYSCFG_GRP2_PVM1                     SYSCFG_IMR2_PVM1IM     /*!< Enabling of interrupt from Power Voltage Monitoring 1 to CPU1 */
00247 #endif
00248 #define LL_SYSCFG_GRP2_PVM3                     SYSCFG_IMR2_PVM3IM     /*!< Enabling of interrupt from Power Voltage Monitoring 3 to CPU1 */
00249 #define LL_SYSCFG_GRP2_PVD                      SYSCFG_IMR2_PVDIM      /*!< Enabling of interrupt from Power Voltage Detector to CPU1     */
00250 /**
00251   * @}
00252   */
00253
00254 /** @defgroup SYSTEM_LL_EC_C2_IM SYSCFG CPU2 INTERRUPT MASK
00255   * @{
00256   */
00257 #define LL_C2_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS  SYSCFG_C2IMR1_RTCSTAMPTAMPLSECSSIM /*!< Enabling of interrupt from RTC TimeStamp, RTC Tampers
00258                                                                                       and LSE Clock Security System to CPU2                             */
00259 #define LL_C2_SYSCFG_GRP1_RTCWKUP               SYSCFG_C2IMR1_RTCWKUPIM  /*!< Enabling of interrupt from RTC Wakeup to CPU2                     */
00260 #define LL_C2_SYSCFG_GRP1_RTCALARM              SYSCFG_C2IMR1_RTCALARMIM /*!< Enabling of interrupt from RTC Alarms to CPU2                     */
00261 #define LL_C2_SYSCFG_GRP1_RCC                   SYSCFG_C2IMR1_RCCIM      /*!< Enabling of interrupt from RCC to CPU2                            */
00262 #define LL_C2_SYSCFG_GRP1_FLASH                 SYSCFG_C2IMR1_FLASHIM    /*!< Enabling of interrupt from FLASH to CPU2                          */
00263 #define LL_C2_SYSCFG_GRP1_PKA                   SYSCFG_C2IMR1_PKAIM      /*!< Enabling of interrupt from Public Key Accelerator to CPU2         */
00264 #define LL_C2_SYSCFG_GRP1_RNG                   SYSCFG_C2IMR1_RNGIM      /*!< Enabling of interrupt from Random Number Generator to CPU2        */
00265 #if defined(AES1)
00266 #define LL_C2_SYSCFG_GRP1_AES1                  SYSCFG_C2IMR1_AES1IM     /*!< Enabling of interrupt from Advanced Encryption Standard 1 to CPU2 */
00267 #endif
00268 #if defined(COMP1)
00269 #define LL_C2_SYSCFG_GRP1_COMP                  SYSCFG_C2IMR1_COMPIM     /*!< Enabling of interrupt from Comparator to CPU2                     */
00270 #endif
00271 #define LL_C2_SYSCFG_GRP1_ADC                   SYSCFG_C2IMR1_ADCIM      /*!< Enabling of interrupt from Analog Digital Converter to CPU2       */
00272
00273 #define LL_C2_SYSCFG_GRP1_EXTI0                 SYSCFG_C2IMR1_EXTI0IM    /*!< Enabling of interrupt from External Interrupt Line 0 to CPU2      */
00274 #define LL_C2_SYSCFG_GRP1_EXTI1                 SYSCFG_C2IMR1_EXTI1IM    /*!< Enabling of interrupt from External Interrupt Line 1 to CPU2      */
00275 #define LL_C2_SYSCFG_GRP1_EXTI2                 SYSCFG_C2IMR1_EXTI2IM    /*!< Enabling of interrupt from External Interrupt Line 2 to CPU2      */
00276 #define LL_C2_SYSCFG_GRP1_EXTI3                 SYSCFG_C2IMR1_EXTI3IM    /*!< Enabling of interrupt from External Interrupt Line 3 to CPU2      */
00277 #define LL_C2_SYSCFG_GRP1_EXTI4                 SYSCFG_C2IMR1_EXTI4IM    /*!< Enabling of interrupt from External Interrupt Line 4 to CPU2      */
00278 #define LL_C2_SYSCFG_GRP1_EXTI5                 SYSCFG_C2IMR1_EXTI5IM    /*!< Enabling of interrupt from External Interrupt Line 5 to CPU2      */
00279 #define LL_C2_SYSCFG_GRP1_EXTI6                 SYSCFG_C2IMR1_EXTI6IM    /*!< Enabling of interrupt from External Interrupt Line 6 to CPU2      */
00280 #define LL_C2_SYSCFG_GRP1_EXTI7                 SYSCFG_C2IMR1_EXTI7IM    /*!< Enabling of interrupt from External Interrupt Line 7 to CPU2      */
00281 #define LL_C2_SYSCFG_GRP1_EXTI8                 SYSCFG_C2IMR1_EXTI8IM    /*!< Enabling of interrupt from External Interrupt Line 8 to CPU2      */
00282 #define LL_C2_SYSCFG_GRP1_EXTI9                 SYSCFG_C2IMR1_EXTI9IM    /*!< Enabling of interrupt from External Interrupt Line 9 to CPU2      */
00283 #define LL_C2_SYSCFG_GRP1_EXTI10                SYSCFG_C2IMR1_EXTI10IM   /*!< Enabling of interrupt from External Interrupt Line 10 to CPU2     */
00284 #define LL_C2_SYSCFG_GRP1_EXTI11                SYSCFG_C2IMR1_EXTI11IM   /*!< Enabling of interrupt from External Interrupt Line 11 to CPU2     */
00285 #define LL_C2_SYSCFG_GRP1_EXTI12                SYSCFG_C2IMR1_EXTI12IM   /*!< Enabling of interrupt from External Interrupt Line 12 to CPU2     */
00286 #define LL_C2_SYSCFG_GRP1_EXTI13                SYSCFG_C2IMR1_EXTI13IM   /*!< Enabling of interrupt from External Interrupt Line 13 to CPU2     */
00287 #define LL_C2_SYSCFG_GRP1_EXTI14                SYSCFG_C2IMR1_EXTI14IM   /*!< Enabling of interrupt from External Interrupt Line 14 to CPU2     */
00288 #define LL_C2_SYSCFG_GRP1_EXTI15                SYSCFG_C2IMR1_EXTI15IM   /*!< Enabling of interrupt from External Interrupt Line 15 to CPU2     */
00289
00290 #define LL_C2_SYSCFG_GRP2_DMA1CH1               SYSCFG_C2IMR2_DMA1CH1IM  /*!< Enabling of interrupt from DMA1 Channel 1 to CPU2                 */
00291 #define LL_C2_SYSCFG_GRP2_DMA1CH2               SYSCFG_C2IMR2_DMA1CH2IM  /*!< Enabling of interrupt from DMA1 Channel 2 to CPU2                 */
00292 #define LL_C2_SYSCFG_GRP2_DMA1CH3               SYSCFG_C2IMR2_DMA1CH3IM  /*!< Enabling of interrupt from DMA1 Channel 3 to CPU2                 */
00293 #define LL_C2_SYSCFG_GRP2_DMA1CH4               SYSCFG_C2IMR2_DMA1CH4IM  /*!< Enabling of interrupt from DMA1 Channel 4 to CPU2                 */
00294 #define LL_C2_SYSCFG_GRP2_DMA1CH5               SYSCFG_C2IMR2_DMA1CH5IM  /*!< Enabling of interrupt from DMA1 Channel 5 to CPU2                 */
00295 #define LL_C2_SYSCFG_GRP2_DMA1CH6               SYSCFG_C2IMR2_DMA1CH6IM  /*!< Enabling of interrupt from DMA1 Channel 6 to CPU2                 */
00296 #define LL_C2_SYSCFG_GRP2_DMA1CH7               SYSCFG_C2IMR2_DMA1CH7IM  /*!< Enabling of interrupt from DMA1 Channel 7 to CPU2                 */
00297
00298 #if defined(DMA2)
00299 #define LL_C2_SYSCFG_GRP2_DMA2CH1               SYSCFG_C2IMR2_DMA2CH1IM  /*!< Enabling of interrupt from DMA2 Channel 1 to CPU2                 */
00300 #define LL_C2_SYSCFG_GRP2_DMA2CH2               SYSCFG_C2IMR2_DMA2CH2IM  /*!< Enabling of interrupt from DMA2 Channel 2 to CPU2                 */
00301 #define LL_C2_SYSCFG_GRP2_DMA2CH3               SYSCFG_C2IMR2_DMA2CH3IM  /*!< Enabling of interrupt from DMA2 Channel 3 to CPU2                 */
00302 #define LL_C2_SYSCFG_GRP2_DMA2CH4               SYSCFG_C2IMR2_DMA2CH4IM  /*!< Enabling of interrupt from DMA2 Channel 4 to CPU2                 */
00303 #define LL_C2_SYSCFG_GRP2_DMA2CH5               SYSCFG_C2IMR2_DMA2CH5IM  /*!< Enabling of interrupt from DMA2 Channel 5 to CPU2                 */
00304 #define LL_C2_SYSCFG_GRP2_DMA2CH6               SYSCFG_C2IMR2_DMA2CH6IM  /*!< Enabling of interrupt from DMA2 Channel 6 to CPU2                 */
00305 #define LL_C2_SYSCFG_GRP2_DMA2CH7               SYSCFG_C2IMR2_DMA2CH7IM  /*!< Enabling of interrupt from DMA2 Channel 7 to CPU2                 */
00306 #endif
00307
00308 #define LL_C2_SYSCFG_GRP2_DMAMUX1               SYSCFG_C2IMR2_DMAMUX1IM  /*!< Enabling of interrupt from DMAMUX1 to CPU2                        */
00309 #if defined(SYSCFG_C2IMR2_PVM1IM)
00310 #define LL_C2_SYSCFG_GRP2_PVM1                  SYSCFG_C2IMR2_PVM1IM     /*!< Enabling of interrupt from Power Voltage Monitoring 1 to CPU2     */
00311 #endif
00312 #define LL_C2_SYSCFG_GRP2_PVM3                  SYSCFG_C2IMR2_PVM3IM     /*!< Enabling of interrupt from Power Voltage Monitoring 3 to CPU2     */
00313 #define LL_C2_SYSCFG_GRP2_PVD                   SYSCFG_C2IMR2_PVDIM      /*!< Enabling of interrupt from Power Voltage Detector to CPU2         */
00314 #define LL_C2_SYSCFG_GRP2_TSC                   SYSCFG_C2IMR2_TSCIM      /*!< Enabling of interrupt from Touch Sensing Controller to CPU2       */
00315 #if defined(LCD)
00316 #define LL_C2_SYSCFG_GRP2_LCD                   SYSCFG_C2IMR2_LCDIM      /*!< Enabling of interrupt from Liquid Crystal Display to CPU2         */
00317 #endif
00318 /**
00319   * @}
00320   */
00321
00322 /** @defgroup SYSTEM_LL_EC_SECURE_IP_ACCESS SYSCFG SECURE IP ACCESS
00323   * @{
00324   */
00325 #if defined(AES1)
00326 #define LL_SYSCFG_SECURE_ACCESS_AES1            SYSCFG_SIPCR_SAES1       /*!< Enabling the security access of Advanced Encryption Standard 1 KEY[7:0] */
00327 #endif
00328 #define LL_SYSCFG_SECURE_ACCESS_AES2            SYSCFG_SIPCR_SAES2       /*!< Enabling the security access of Advanced Encryption Standard 2          */
00329 #define LL_SYSCFG_SECURE_ACCESS_PKA             SYSCFG_SIPCR_SPKA        /*!< Enabling the security access of Public Key Accelerator                  */
00330 #define LL_SYSCFG_SECURE_ACCESS_RNG             SYSCFG_SIPCR_SRNG        /*!< Enabling the security access of Random Number Generator                 */
00331 /**
00332   * @}
00333   */
00334
00335 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU CPU1 APB1 GRP1 STOP IP
00336   * @{
00337   */
00338 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP      DBGMCU_APB1FZR1_DBG_TIM2_STOP   /*!< The counter clock of TIM2 is stopped when the core is halted              */
00339 #define LL_DBGMCU_APB1_GRP1_RTC_STOP       DBGMCU_APB1FZR1_DBG_RTC_STOP    /*!< The clock of the RTC counter is stopped when the core is halted           */
00340 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP      DBGMCU_APB1FZR1_DBG_WWDG_STOP   /*!< The window watchdog counter clock is stopped when the core is halted      */
00341 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP      DBGMCU_APB1FZR1_DBG_IWDG_STOP   /*!< The independent watchdog counter clock is stopped when the core is halted */
00342 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP      DBGMCU_APB1FZR1_DBG_I2C1_STOP   /*!< The I2C1 SMBus timeout is frozen                                          */
00343 #if defined(I2C3)
00344 #define LL_DBGMCU_APB1_GRP1_I2C3_STOP      DBGMCU_APB1FZR1_DBG_I2C3_STOP   /*!< The I2C3 SMBus timeout is frozen                                          */
00345 #endif
00346 #define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP    DBGMCU_APB1FZR1_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted            */
00347 /**
00348   * @}
00349   */
00350
00351 /** @defgroup SYSTEM_LL_EC_C2_APB1_GRP1_STOP_IP DBGMCU CPU2 APB1 GRP1 STOP IP
00352   * @{
00353   */
00354 #define LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP   DBGMCU_C2APB1FZR1_DBG_TIM2_STOP   /*!< The counter clock of TIM2 is stopped when the core is halted              */
00355 #define LL_C2_DBGMCU_APB1_GRP1_RTC_STOP    DBGMCU_C2APB1FZR1_DBG_RTC_STOP    /*!< The clock of the RTC counter is stopped when the core is halted           */
00356 #define LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP   DBGMCU_C2APB1FZR1_DBG_IWDG_STOP   /*!< The independent watchdog counter clock is stopped when the core is halted */
00357 #define LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP   DBGMCU_C2APB1FZR1_DBG_I2C1_STOP   /*!< The I2C1 SMBus timeout is frozen                                          */
00358 #if defined(I2C3)
00359 #define LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP   DBGMCU_C2APB1FZR1_DBG_I2C3_STOP   /*!< The I2C3 SMBus timeout is frozen                                          */
00360 #endif
00361 #define LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_C2APB1FZR1_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted            */
00362 /**
00363   * @}
00364   */
00365
00366 /** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU CPU1 APB1 GRP2 STOP IP
00367   * @{
00368   */
00369 #define LL_DBGMCU_APB1_GRP2_LPTIM2_STOP    DBGMCU_APB1FZR2_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted            */
00370 /**
00371   * @}
00372   */
00373
00374 /** @defgroup SYSTEM_LL_EC_C2_APB1_GRP2_STOP_IP DBGMCU CPU2 APB1 GRP2 STOP IP
00375   * @{
00376   */
00377 #define LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_C2APB1FZR2_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted            */
00378 /**
00379   * @}
00380   */
00381
00382 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU CPU1 APB2 GRP1 STOP IP
00383   * @{
00384   */
00385 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP      DBGMCU_APB2FZR_DBG_TIM1_STOP   /*!< The counter clock of TIM1 is stopped when the core is halted              */
00386 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP     DBGMCU_APB2FZR_DBG_TIM16_STOP  /*!< The counter clock of TIM16 is stopped when the core is halted             */
00387 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP     DBGMCU_APB2FZR_DBG_TIM17_STOP  /*!< The counter clock of TIM17 is stopped when the core is halted             */
00388 /**
00389   * @}
00390   */
00391
00392 /** @defgroup SYSTEM_LL_EC_C2_APB2_GRP1_STOP_IP DBGMCU CPU2 APB2 GRP1 STOP IP
00393   * @{
00394   */
00395 #define LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP   DBGMCU_C2APB2FZR_DBG_TIM1_STOP   /*!< The counter clock of TIM1 is stopped when the core is halted              */
00396 #define LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP  DBGMCU_C2APB2FZR_DBG_TIM16_STOP  /*!< The counter clock of TIM16 is stopped when the core is halted             */
00397 #define LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP  DBGMCU_C2APB2FZR_DBG_TIM17_STOP  /*!< The counter clock of TIM17 is stopped when the core is halted             */
00398 /**
00399   * @}
00400   */
00401
00402 #if defined(VREFBUF)
00403 /** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE
00404   * @{
00405   */
00406 #define LL_VREFBUF_VOLTAGE_SCALE0          0x00000000U     /*!< Voltage reference scale 0 (VREF_OUT1) */
00407 #define LL_VREFBUF_VOLTAGE_SCALE1          VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */
00408 /**
00409   * @}
00410   */
00411 #endif /* VREFBUF */
00412
00413 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
00414   * @{
00415   */
00416 #define LL_FLASH_LATENCY_0                 FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero wait state   */
00417 #define LL_FLASH_LATENCY_1                 FLASH_ACR_LATENCY_1WS   /*!< FLASH One wait state    */
00418 #define LL_FLASH_LATENCY_2                 FLASH_ACR_LATENCY_2WS   /*!< FLASH Two wait states   */
00419 #define LL_FLASH_LATENCY_3                 FLASH_ACR_LATENCY_3WS   /*!< FLASH Three wait states */
00420
00421 /**
00422   * @}
00423   */
00424
00425 /**
00426   * @}
00427   */
00428
00429 /* Exported macro ------------------------------------------------------------*/
00430
00431 /* Exported functions --------------------------------------------------------*/
00432 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
00433   * @{
00434   */
00435
00436 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
00437   * @{
00438   */
00439
00440 /**
00441   * @brief  Set memory mapping at address 0x00000000
00442   * @rmtoll SYSCFG_MEMRMP MEM_MODE      LL_SYSCFG_SetRemapMemory
00443   * @param  Memory This parameter can be one of the following values:
00444   *         @arg @ref LL_SYSCFG_REMAP_FLASH
00445   *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
00446   *         @arg @ref LL_SYSCFG_REMAP_SRAM
00447   *         @arg @ref LL_SYSCFG_REMAP_QUADSPI
00448   * @retval None
00449   */
00450 __STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
00451 {
00452   MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
00453 }
00454
00455 /**
00456   * @brief  Get memory mapping at address 0x00000000
00457   * @rmtoll SYSCFG_MEMRMP MEM_MODE      LL_SYSCFG_GetRemapMemory
00458   * @retval Returned value can be one of the following values:
00459   *         @arg @ref LL_SYSCFG_REMAP_FLASH
00460   *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
00461   *         @arg @ref LL_SYSCFG_REMAP_SRAM
00462   *         @arg @ref LL_SYSCFG_REMAP_QUADSPI
00463   */
00464 __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
00465 {
00466   return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
00467 }
00468
00469 /**
00470   * @brief  Enable I/O analog switch voltage booster.
00471   * @note   When voltage booster is enabled, I/O analog switches are supplied
00472   *         by a dedicated voltage booster, from VDD power domain. This is
00473   *         the recommended configuration with low VDDA voltage operation.
00474   * @note   The I/O analog switch voltage booster is relevant for peripherals
00475   *         using I/O in analog input: ADC and COMP.
00476   *         However, COMP inputs have a high impedance and
00477   *         voltage booster do not impact performance significantly.
00478   *         Therefore, the voltage booster is mainly intended for
00479   *         usage with ADC.
00480   * @rmtoll SYSCFG_CFGR1 BOOSTEN       LL_SYSCFG_EnableAnalogBooster
00481   * @retval None
00482   */
00483 __STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
00484 {
00485   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
00486 }
00487
00488 /**
00489   * @brief  Disable I/O analog switch voltage booster.
00490   * @note   When voltage booster is enabled, I/O analog switches are supplied
00491   *         by a dedicated voltage booster, from VDD power domain. This is
00492   *         the recommended configuration with low VDDA voltage operation.
00493   * @note   The I/O analog switch voltage booster is relevant for peripherals
00494   *         using I/O in analog input: ADC and COMP.
00495   *         However, COMP inputs have a high impedance and
00496   *         voltage booster do not impact performance significantly.
00497   *         Therefore, the voltage booster is mainly intended for
00498   *         usage with ADC.
00499   * @rmtoll SYSCFG_CFGR1 BOOSTEN       LL_SYSCFG_DisableAnalogBooster
00500   * @retval None
00501   */
00502 __STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
00503 {
00504   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
00505 }
00506
00507 /**
00508   * @brief  Enable the Analog GPIO switch to control voltage selection
00509   *         when the supply voltage is supplied by VDDA
00510   * @rmtoll SYSCFG_CFGR1   ANASWVDD   LL_SYSCFG_EnableAnalogGpioSwitch
00511   * @note   Activating the gpio switch enable IOs analog switches supplied by VDDA
00512   * @retval None
00513   */
00514 __STATIC_INLINE void LL_SYSCFG_EnableAnalogGpioSwitch(void)
00515 {
00516   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD);
00517 }
00518
00519 /**
00520   * @brief  Disable the Analog GPIO switch to control voltage selection
00521   *         when the supply voltage is supplied by VDDA
00522   * @rmtoll SYSCFG_CFGR1   ANASWVDD   LL_SYSCFG_DisableAnalogGpioSwitch
00523   * @note   Activating the gpio switch enable IOs analog switches supplied by VDDA
00524   * @retval None
00525   */
00526 __STATIC_INLINE void LL_SYSCFG_DisableAnalogGpioSwitch(void)
00527 {
00528   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD);
00529 }
00530
00531 /**
00532   * @brief  Enable the I2C fast mode plus driving capability.
00533   * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP   LL_SYSCFG_EnableFastModePlus\n
00534   *         SYSCFG_CFGR1 I2Cx_FMP      LL_SYSCFG_EnableFastModePlus
00535   * @param  ConfigFastModePlus This parameter can be a combination of the following values:
00536   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
00537   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
00538   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
00539   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
00540   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
00541   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
00542   * @retval None
00543   */
00544 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
00545 {
00546   SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
00547 }
00548
00549 /**
00550   * @brief  Disable the I2C fast mode plus driving capability.
00551   * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP   LL_SYSCFG_DisableFastModePlus\n
00552   *         SYSCFG_CFGR1 I2Cx_FMP      LL_SYSCFG_DisableFastModePlus
00553   * @param  ConfigFastModePlus This parameter can be a combination of the following values:
00554   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
00555   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
00556   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
00557   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
00558   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
00559   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
00560   * @retval None
00561   */
00562 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
00563 {
00564   CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
00565 }
00566
00567 /**
00568   * @brief  Enable Floating Point Unit Invalid operation Interrupt
00569   * @rmtoll SYSCFG_CFGR1 FPU_IE_0      LL_SYSCFG_EnableIT_FPU_IOC
00570   * @retval None
00571   */
00572 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void)
00573 {
00574   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
00575 }
00576
00577 /**
00578   * @brief  Enable Floating Point Unit Divide-by-zero Interrupt
00579   * @rmtoll SYSCFG_CFGR1 FPU_IE_1      LL_SYSCFG_EnableIT_FPU_DZC
00580   * @retval None
00581   */
00582 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void)
00583 {
00584   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
00585 }
00586
00587 /**
00588   * @brief  Enable Floating Point Unit Underflow Interrupt
00589   * @rmtoll SYSCFG_CFGR1 FPU_IE_2      LL_SYSCFG_EnableIT_FPU_UFC
00590   * @retval None
00591   */
00592 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void)
00593 {
00594   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
00595 }
00596
00597 /**
00598   * @brief  Enable Floating Point Unit Overflow Interrupt
00599   * @rmtoll SYSCFG_CFGR1 FPU_IE_3      LL_SYSCFG_EnableIT_FPU_OFC
00600   * @retval None
00601   */
00602 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void)
00603 {
00604   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
00605 }
00606
00607 /**
00608   * @brief  Enable Floating Point Unit Input denormal Interrupt
00609   * @rmtoll SYSCFG_CFGR1 FPU_IE_4      LL_SYSCFG_EnableIT_FPU_IDC
00610   * @retval None
00611   */
00612 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void)
00613 {
00614   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
00615 }
00616
00617 /**
00618   * @brief  Enable Floating Point Unit Inexact Interrupt
00619   * @rmtoll SYSCFG_CFGR1 FPU_IE_5      LL_SYSCFG_EnableIT_FPU_IXC
00620   * @retval None
00621   */
00622 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void)
00623 {
00624   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
00625 }
00626
00627 /**
00628   * @brief  Disable Floating Point Unit Invalid operation Interrupt
00629   * @rmtoll SYSCFG_CFGR1 FPU_IE_0      LL_SYSCFG_DisableIT_FPU_IOC
00630   * @retval None
00631   */
00632 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void)
00633 {
00634   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
00635 }
00636
00637 /**
00638   * @brief  Disable Floating Point Unit Divide-by-zero Interrupt
00639   * @rmtoll SYSCFG_CFGR1 FPU_IE_1      LL_SYSCFG_DisableIT_FPU_DZC
00640   * @retval None
00641   */
00642 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void)
00643 {
00644   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
00645 }
00646
00647 /**
00648   * @brief  Disable Floating Point Unit Underflow Interrupt
00649   * @rmtoll SYSCFG_CFGR1 FPU_IE_2      LL_SYSCFG_DisableIT_FPU_UFC
00650   * @retval None
00651   */
00652 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void)
00653 {
00654   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
00655 }
00656
00657 /**
00658   * @brief  Disable Floating Point Unit Overflow Interrupt
00659   * @rmtoll SYSCFG_CFGR1 FPU_IE_3      LL_SYSCFG_DisableIT_FPU_OFC
00660   * @retval None
00661   */
00662 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void)
00663 {
00664   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
00665 }
00666
00667 /**
00668   * @brief  Disable Floating Point Unit Input denormal Interrupt
00669   * @rmtoll SYSCFG_CFGR1 FPU_IE_4      LL_SYSCFG_DisableIT_FPU_IDC
00670   * @retval None
00671   */
00672 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void)
00673 {
00674   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
00675 }
00676
00677 /**
00678   * @brief  Disable Floating Point Unit Inexact Interrupt
00679   * @rmtoll SYSCFG_CFGR1 FPU_IE_5      LL_SYSCFG_DisableIT_FPU_IXC
00680   * @retval None
00681   */
00682 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void)
00683 {
00684   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
00685 }
00686
00687 /**
00688   * @brief  Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
00689   * @rmtoll SYSCFG_CFGR1 FPU_IE_0      LL_SYSCFG_IsEnabledIT_FPU_IOC
00690   * @retval State of bit (1 or 0).
00691   */
00692 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void)
00693 {
00694   return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) == (SYSCFG_CFGR1_FPU_IE_0)) ? 1UL : 0UL);
00695 }
00696
00697 /**
00698   * @brief  Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
00699   * @rmtoll SYSCFG_CFGR1 FPU_IE_1      LL_SYSCFG_IsEnabledIT_FPU_DZC
00700   * @retval State of bit (1 or 0).
00701   */
00702 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void)
00703 {
00704   return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) == (SYSCFG_CFGR1_FPU_IE_1)) ? 1UL : 0UL);
00705 }
00706
00707 /**
00708   * @brief  Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
00709   * @rmtoll SYSCFG_CFGR1 FPU_IE_2      LL_SYSCFG_IsEnabledIT_FPU_UFC
00710   * @retval State of bit (1 or 0).
00711   */
00712 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void)
00713 {
00714   return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) == (SYSCFG_CFGR1_FPU_IE_2)) ? 1UL : 0UL);
00715 }
00716
00717 /**
00718   * @brief  Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
00719   * @rmtoll SYSCFG_CFGR1 FPU_IE_3      LL_SYSCFG_IsEnabledIT_FPU_OFC
00720   * @retval State of bit (1 or 0).
00721   */
00722 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void)
00723 {
00724   return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) == (SYSCFG_CFGR1_FPU_IE_3)) ? 1UL : 0UL);
00725 }
00726
00727 /**
00728   * @brief  Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
00729   * @rmtoll SYSCFG_CFGR1 FPU_IE_4      LL_SYSCFG_IsEnabledIT_FPU_IDC
00730   * @retval State of bit (1 or 0).
00731   */
00732 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void)
00733 {
00734   return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) == (SYSCFG_CFGR1_FPU_IE_4)) ? 1UL : 0UL);
00735 }
00736
00737 /**
00738   * @brief  Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
00739   * @rmtoll SYSCFG_CFGR1 FPU_IE_5      LL_SYSCFG_IsEnabledIT_FPU_IXC
00740   * @retval State of bit (1 or 0).
00741   */
00742 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
00743 {
00744   return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) == (SYSCFG_CFGR1_FPU_IE_5)) ? 1UL : 0UL);
00745 }
00746
00747 /**
00748   * @brief  Configure source input for the EXTI external interrupt.
00749   * @rmtoll SYSCFG_EXTICR1 EXTIx         LL_SYSCFG_SetEXTISource\n
00750   *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_SetEXTISource\n
00751   *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_SetEXTISource\n
00752   *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_SetEXTISource
00753   * @param  Port This parameter can be one of the following values:
00754   *         @arg @ref LL_SYSCFG_EXTI_PORTA
00755   *         @arg @ref LL_SYSCFG_EXTI_PORTB
00756   *         @arg @ref LL_SYSCFG_EXTI_PORTC
00757   *         @arg @ref LL_SYSCFG_EXTI_PORTD
00758   *         @arg @ref LL_SYSCFG_EXTI_PORTE
00759   *         @arg @ref LL_SYSCFG_EXTI_PORTH
00760   *
00761   * @param  Line This parameter can be one of the following values:
00762   *         @arg @ref LL_SYSCFG_EXTI_LINE0
00763   *         @arg @ref LL_SYSCFG_EXTI_LINE1
00764   *         @arg @ref LL_SYSCFG_EXTI_LINE2
00765   *         @arg @ref LL_SYSCFG_EXTI_LINE3
00766   *         @arg @ref LL_SYSCFG_EXTI_LINE4
00767   *         @arg @ref LL_SYSCFG_EXTI_LINE5
00768   *         @arg @ref LL_SYSCFG_EXTI_LINE6
00769   *         @arg @ref LL_SYSCFG_EXTI_LINE7
00770   *         @arg @ref LL_SYSCFG_EXTI_LINE8
00771   *         @arg @ref LL_SYSCFG_EXTI_LINE9
00772   *         @arg @ref LL_SYSCFG_EXTI_LINE10
00773   *         @arg @ref LL_SYSCFG_EXTI_LINE11
00774   *         @arg @ref LL_SYSCFG_EXTI_LINE12
00775   *         @arg @ref LL_SYSCFG_EXTI_LINE13
00776   *         @arg @ref LL_SYSCFG_EXTI_LINE14
00777   *         @arg @ref LL_SYSCFG_EXTI_LINE15
00778   * @retval None
00779   */
00780 __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
00781 {
00782   MODIFY_REG(SYSCFG->EXTICR[Line & 0x03U], (Line >> 16U), (Port << ((POSITION_VAL((Line >> 16U))) & 0x0000000FUL)));
00783 }
00784
00785 /**
00786   * @brief  Get the configured defined for specific EXTI Line
00787   * @rmtoll SYSCFG_EXTICR1 EXTIx         LL_SYSCFG_GetEXTISource\n
00788   *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_GetEXTISource\n
00789   *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_GetEXTISource\n
00790   *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_GetEXTISource
00791   * @param  Line This parameter can be one of the following values:
00792   *         @arg @ref LL_SYSCFG_EXTI_LINE0
00793   *         @arg @ref LL_SYSCFG_EXTI_LINE1
00794   *         @arg @ref LL_SYSCFG_EXTI_LINE2
00795   *         @arg @ref LL_SYSCFG_EXTI_LINE3
00796   *         @arg @ref LL_SYSCFG_EXTI_LINE4
00797   *         @arg @ref LL_SYSCFG_EXTI_LINE5
00798   *         @arg @ref LL_SYSCFG_EXTI_LINE6
00799   *         @arg @ref LL_SYSCFG_EXTI_LINE7
00800   *         @arg @ref LL_SYSCFG_EXTI_LINE8
00801   *         @arg @ref LL_SYSCFG_EXTI_LINE9
00802   *         @arg @ref LL_SYSCFG_EXTI_LINE10
00803   *         @arg @ref LL_SYSCFG_EXTI_LINE11
00804   *         @arg @ref LL_SYSCFG_EXTI_LINE12
00805   *         @arg @ref LL_SYSCFG_EXTI_LINE13
00806   *         @arg @ref LL_SYSCFG_EXTI_LINE14
00807   *         @arg @ref LL_SYSCFG_EXTI_LINE15
00808   * @retval Returned value can be one of the following values:
00809   *         @arg @ref LL_SYSCFG_EXTI_PORTA
00810   *         @arg @ref LL_SYSCFG_EXTI_PORTB
00811   *         @arg @ref LL_SYSCFG_EXTI_PORTC
00812   *         @arg @ref LL_SYSCFG_EXTI_PORTD
00813   *         @arg @ref LL_SYSCFG_EXTI_PORTE
00814   *         @arg @ref LL_SYSCFG_EXTI_PORTH
00815   */
00816 __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
00817 {
00818   return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x03U], (Line >> 16U)) >> (POSITION_VAL(Line >> 16U) & 0x0000000FUL) );
00819 }
00820
00821 /**
00822   * @brief  Enable SRAM2 Erase (starts a hardware SRAM2 erase operation. This bit is
00823   * automatically cleared at the end of the SRAM2 erase operation.)
00824   * @note This bit is write-protected: setting this bit is possible only after the
00825   *       correct key sequence is written in the SYSCFG_SKR register.
00826   * @rmtoll SYSCFG_SCSR  SRAM2ER       LL_SYSCFG_EnableSRAM2Erase
00827   * @retval None
00828   */
00829 __STATIC_INLINE void LL_SYSCFG_EnableSRAM2Erase(void)
00830 {
00831   SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER);
00832 }
00833
00834 /**
00835   * @brief  Check if SRAM2 erase operation is on going
00836   * @rmtoll SYSCFG_SCSR  SRAM2BSY      LL_SYSCFG_IsSRAM2EraseOngoing
00837   * @retval State of bit (1 or 0).
00838   */
00839 __STATIC_INLINE uint32_t LL_SYSCFG_IsSRAM2EraseOngoing(void)
00840 {
00841   return ((READ_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2BSY) == (SYSCFG_SCSR_SRAM2BSY)) ? 1UL : 0UL);
00842 }
00843
00844 /**
00845   * @brief  Disable CPU2 SRAM fetch (execution) (This bit can be set by Firmware
00846   *         and will only be reset by a Hardware reset, including a reset after Standby.)
00847   * @note Firmware writing 0 has no effect.
00848   * @rmtoll SYSCFG_SCSR  C2RFD         LL_SYSCFG_DisableSRAMFetch
00849   * @retval None
00850   */
00851 __STATIC_INLINE void LL_SYSCFG_DisableSRAMFetch(void)
00852 {
00853   SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_C2RFD);
00854 }
00855
00856 /**
00857   * @brief  Check if CPU2 SRAM fetch is enabled
00858   * @rmtoll SYSCFG_SCSR  C2RFD         LL_SYSCFG_IsEnabledSRAMFetch
00859   * @retval State of bit (1 or 0).
00860   */
00861 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledSRAMFetch(void)
00862 {
00863   return ((READ_BIT(SYSCFG->SCSR, SYSCFG_SCSR_C2RFD) != (SYSCFG_SCSR_C2RFD)) ? 1UL : 0UL);
00864 }
00865
00866 /**
00867   * @brief  Set connections to TIM1/16/17 Break inputs
00868   * @rmtoll SYSCFG_CFGR2 CLL           LL_SYSCFG_SetTIMBreakInputs\n
00869   *         SYSCFG_CFGR2 SPL           LL_SYSCFG_SetTIMBreakInputs\n
00870   *         SYSCFG_CFGR2 PVDL          LL_SYSCFG_SetTIMBreakInputs\n
00871   *         SYSCFG_CFGR2 ECCL          LL_SYSCFG_SetTIMBreakInputs
00872   * @param  Break This parameter can be a combination of the following values:
00873   *         @arg @ref LL_SYSCFG_TIMBREAK_ECC
00874   *         @arg @ref LL_SYSCFG_TIMBREAK_PVD
00875   *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY
00876   *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
00877   * @retval None
00878   */
00879 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
00880 {
00881   MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL, Break);
00882 }
00883
00884 /**
00885   * @brief  Get connections to TIM1/16/17 Break inputs
00886   * @rmtoll SYSCFG_CFGR2 CLL           LL_SYSCFG_GetTIMBreakInputs\n
00887   *         SYSCFG_CFGR2 SPL           LL_SYSCFG_GetTIMBreakInputs\n
00888   *         SYSCFG_CFGR2 PVDL          LL_SYSCFG_GetTIMBreakInputs\n
00889   *         SYSCFG_CFGR2 ECCL          LL_SYSCFG_GetTIMBreakInputs
00890   * @retval Returned value can be can be a combination of the following values:
00891   *         @arg @ref LL_SYSCFG_TIMBREAK_ECC
00892   *         @arg @ref LL_SYSCFG_TIMBREAK_PVD
00893   *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY
00894   *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
00895   */
00896 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
00897 {
00898   return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL));
00899 }
00900
00901 /**
00902   * @brief  Check if SRAM2 parity error detected
00903   * @rmtoll SYSCFG_CFGR2 SPF           LL_SYSCFG_IsActiveFlag_SP
00904   * @retval State of bit (1 or 0).
00905   */
00906 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
00907 {
00908   return ((READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) == (SYSCFG_CFGR2_SPF)) ? 1UL : 0UL);
00909 }
00910
00911 /**
00912   * @brief  Clear SRAM2 parity error flag
00913   * @rmtoll SYSCFG_CFGR2 SPF           LL_SYSCFG_ClearFlag_SP
00914   * @retval None
00915   */
00916 __STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
00917 {
00918   SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF);
00919 }
00920
00921 /**
00922   * @brief  Enable SRAM2 page write protection for Pages in range 0 to 31
00923   * @note Write protection is cleared only by a system reset
00924   * @rmtoll SYSCFG_SWPR1 PxWP          LL_SYSCFG_EnableSRAM2PageWRP_0_31
00925   * @param  SRAM2WRP This parameter can be a combination of the following values:
00926   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE0
00927   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE1
00928   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE2
00929   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE3
00930   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE4
00931   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE5
00932   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE6
00933   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE7
00934   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE8
00935   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE9
00936   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE10
00937   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE11
00938   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE12
00939   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE13
00940   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE14
00941   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE15
00942   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE16
00943   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE17
00944   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE18
00945   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE19
00946   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE20
00947   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE21
00948   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE22
00949   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE23
00950   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE24
00951   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE25
00952   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE26
00953   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE27
00954   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE28
00955   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE29
00956   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE30
00957   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE31
00958   * @retval None
00959   */
00960 /* Legacy define */
00961 #define LL_SYSCFG_EnableSRAM2PageWRP    LL_SYSCFG_EnableSRAM2PageWRP_0_31
00962 __STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP_0_31(uint32_t SRAM2WRP)
00963 {
00964   SET_BIT(SYSCFG->SWPR1, SRAM2WRP);
00965 }
00966
00967 /**
00968   * @brief  Enable SRAM2 page write protection for Pages in range 32 to 63
00969   * @note Write protection is cleared only by a system reset
00970   * @rmtoll SYSCFG_SWPR2 PxWP          LL_SYSCFG_EnableSRAM2PageWRP_32_63
00971   * @param  SRAM2WRP This parameter can be a combination of the following values:
00972   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE32
00973   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE33
00974   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE34
00975   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE35
00976   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE36
00977   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE37
00978   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE38
00979   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE39
00980   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE40
00981   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE41
00982   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE42
00983   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE43
00984   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE44
00985   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE45
00986   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE46
00987   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE47
00988   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE48
00989   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE49
00990   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE50
00991   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE51
00992   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE52
00993   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE53
00994   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE54
00995   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE55
00996   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE56
00997   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE57
00998   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE58
00999   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE59
01000   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE60
01001   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE61
01002   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE62
01003   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE63
01004   * @retval None
01005   */
01006 __STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP_32_63(uint32_t SRAM2WRP)
01007 {
01008   SET_BIT(SYSCFG->SWPR2, SRAM2WRP);
01009 }
01010
01011 /**
01012   * @brief  SRAM2 page write protection lock prior to erase
01013   * @rmtoll SYSCFG_SKR   KEY           LL_SYSCFG_LockSRAM2WRP
01014   * @retval None
01015   */
01016 __STATIC_INLINE void LL_SYSCFG_LockSRAM2WRP(void)
01017 {
01018   /* Writing a wrong key reactivates the write protection */
01019   WRITE_REG(SYSCFG->SKR, 0x00U);
01020 }
01021
01022 /**
01023   * @brief  SRAM2 page write protection unlock prior to erase
01024   * @rmtoll SYSCFG_SKR   KEY           LL_SYSCFG_UnlockSRAM2WRP
01025   * @retval None
01026   */
01027 __STATIC_INLINE void LL_SYSCFG_UnlockSRAM2WRP(void)
01028 {
01029   /* unlock the write protection of the SRAM2ER bit */
01030   WRITE_REG(SYSCFG->SKR, 0xCAU);
01031   WRITE_REG(SYSCFG->SKR, 0x53U);
01032 }
01033
01034 /**
01035   * @brief  Enable CPU1 Interrupt Mask
01036   * @rmtoll SYSCFG_IMR1  TIM1IM      LL_SYSCFG_GRP1_EnableIT\n
01037   *         SYSCFG_IMR1  TIM16IM     LL_SYSCFG_GRP1_EnableIT\n
01038   *         SYSCFG_IMR1  TIM17IM     LL_SYSCFG_GRP1_EnableIT\n
01039   *         SYSCFG_IMR1  EXTIxIM     LL_SYSCFG_GRP1_EnableIT
01040   * @param  Interrupt This parameter can be a combination of the following values:
01041   *         @arg @ref LL_SYSCFG_GRP1_TIM1
01042   *         @arg @ref LL_SYSCFG_GRP1_TIM16
01043   *         @arg @ref LL_SYSCFG_GRP1_TIM17
01044   *         @arg @ref LL_SYSCFG_GRP1_EXTI5
01045   *         @arg @ref LL_SYSCFG_GRP1_EXTI6
01046   *         @arg @ref LL_SYSCFG_GRP1_EXTI7
01047   *         @arg @ref LL_SYSCFG_GRP1_EXTI8
01048   *         @arg @ref LL_SYSCFG_GRP1_EXTI9
01049   *         @arg @ref LL_SYSCFG_GRP1_EXTI10
01050   *         @arg @ref LL_SYSCFG_GRP1_EXTI11
01051   *         @arg @ref LL_SYSCFG_GRP1_EXTI12
01052   *         @arg @ref LL_SYSCFG_GRP1_EXTI13
01053   *         @arg @ref LL_SYSCFG_GRP1_EXTI14
01054   *         @arg @ref LL_SYSCFG_GRP1_EXTI15
01055   * @retval None
01056   */
01057 __STATIC_INLINE void LL_SYSCFG_GRP1_EnableIT(uint32_t Interrupt)
01058 {
01059   CLEAR_BIT(SYSCFG->IMR1, Interrupt);
01060 }
01061
01062 /**
01063   * @brief  Enable CPU1 Interrupt Mask
01064   * @rmtoll SYSCFG_IMR1  PVM1IM      LL_SYSCFG_GRP2_EnableIT\n
01065   *         SYSCFG_IMR1  PVM3IM      LL_SYSCFG_GRP2_EnableIT\n
01066   *         SYSCFG_IMR1  PVDIM       LL_SYSCFG_GRP2_EnableIT
01067   * @param  Interrupt This parameter can be a combination of the following values:
01068   *         @arg @ref LL_SYSCFG_GRP2_PVM1
01069   *         @arg @ref LL_SYSCFG_GRP2_PVM3
01070   *         @arg @ref LL_SYSCFG_GRP2_PVD
01071   * @retval None
01072   */
01073 __STATIC_INLINE void LL_SYSCFG_GRP2_EnableIT(uint32_t Interrupt)
01074 {
01075   CLEAR_BIT(SYSCFG->IMR2, Interrupt);
01076 }
01077
01078 /**
01079   * @brief  Disable CPU1 Interrupt Mask
01080   * @rmtoll SYSCFG_IMR1  TIM1IM      LL_SYSCFG_GRP1_DisableIT\n
01081   *         SYSCFG_IMR1  TIM16IM     LL_SYSCFG_GRP1_DisableIT\n
01082   *         SYSCFG_IMR1  TIM17IM     LL_SYSCFG_GRP1_DisableIT\n
01083   *         SYSCFG_IMR1  EXTIxIM     LL_SYSCFG_GRP1_DisableIT
01084   * @param  Interrupt This parameter can be a combination of the following values:
01085   *         @arg @ref LL_SYSCFG_GRP1_TIM1
01086   *         @arg @ref LL_SYSCFG_GRP1_TIM16
01087   *         @arg @ref LL_SYSCFG_GRP1_TIM17
01088   *         @arg @ref LL_SYSCFG_GRP1_EXTI5
01089   *         @arg @ref LL_SYSCFG_GRP1_EXTI6
01090   *         @arg @ref LL_SYSCFG_GRP1_EXTI7
01091   *         @arg @ref LL_SYSCFG_GRP1_EXTI8
01092   *         @arg @ref LL_SYSCFG_GRP1_EXTI9
01093   *         @arg @ref LL_SYSCFG_GRP1_EXTI10
01094   *         @arg @ref LL_SYSCFG_GRP1_EXTI11
01095   *         @arg @ref LL_SYSCFG_GRP1_EXTI12
01096   *         @arg @ref LL_SYSCFG_GRP1_EXTI13
01097   *         @arg @ref LL_SYSCFG_GRP1_EXTI14
01098   *         @arg @ref LL_SYSCFG_GRP1_EXTI15
01099   * @retval None
01100   */
01101 __STATIC_INLINE void LL_SYSCFG_GRP1_DisableIT(uint32_t Interrupt)
01102 {
01103   SET_BIT(SYSCFG->IMR1, Interrupt);
01104 }
01105
01106 /**
01107   * @brief  Disable CPU1 Interrupt Mask
01108   * @rmtoll SYSCFG_IMR2  PVM1IM      LL_SYSCFG_GRP2_DisableIT\n
01109   *         SYSCFG_IMR2  PVM3IM      LL_SYSCFG_GRP2_DisableIT\n
01110   *         SYSCFG_IMR2  PVDIM       LL_SYSCFG_GRP2_DisableIT
01111   * @param  Interrupt This parameter can be a combination of the following values:
01112   *         @arg @ref LL_SYSCFG_GRP2_PVM1
01113   *         @arg @ref LL_SYSCFG_GRP2_PVM3
01114   *         @arg @ref LL_SYSCFG_GRP2_PVD
01115   * @retval None
01116   */
01117 __STATIC_INLINE void LL_SYSCFG_GRP2_DisableIT(uint32_t Interrupt)
01118 {
01119   SET_BIT(SYSCFG->IMR2, Interrupt);
01120 }
01121
01122 /**
01123   * @brief  Indicate if CPU1 Interrupt Mask is enabled
01124   * @rmtoll SYSCFG_IMR1  TIM1IM      LL_SYSCFG_GRP1_IsEnabledIT\n
01125   *         SYSCFG_IMR1  TIM16IM     LL_SYSCFG_GRP1_IsEnabledIT\n
01126   *         SYSCFG_IMR1  TIM17IM     LL_SYSCFG_GRP1_IsEnabledIT\n
01127   *         SYSCFG_IMR1  EXTIxIM     LL_SYSCFG_GRP1_IsEnabledIT
01128   * @param  Interrupt This parameter can be one of the following values:
01129   *         @arg @ref LL_SYSCFG_GRP1_TIM1
01130   *         @arg @ref LL_SYSCFG_GRP1_TIM16
01131   *         @arg @ref LL_SYSCFG_GRP1_TIM17
01132   *         @arg @ref LL_SYSCFG_GRP1_EXTI5
01133   *         @arg @ref LL_SYSCFG_GRP1_EXTI6
01134   *         @arg @ref LL_SYSCFG_GRP1_EXTI7
01135   *         @arg @ref LL_SYSCFG_GRP1_EXTI8
01136   *         @arg @ref LL_SYSCFG_GRP1_EXTI9
01137   *         @arg @ref LL_SYSCFG_GRP1_EXTI10
01138   *         @arg @ref LL_SYSCFG_GRP1_EXTI11
01139   *         @arg @ref LL_SYSCFG_GRP1_EXTI12
01140   *         @arg @ref LL_SYSCFG_GRP1_EXTI13
01141   *         @arg @ref LL_SYSCFG_GRP1_EXTI14
01142   *         @arg @ref LL_SYSCFG_GRP1_EXTI15
01143   * @retval State of bit (1 or 0).
01144   */
01145 __STATIC_INLINE uint32_t LL_SYSCFG_GRP1_IsEnabledIT(uint32_t Interrupt)
01146 {
01147   return ((READ_BIT(SYSCFG->IMR1, Interrupt) != (Interrupt)) ? 1UL : 0UL);
01148 }
01149
01150 /**
01151   * @brief  Indicate if CPU1 Interrupt Mask is enabled
01152   * @rmtoll SYSCFG_IMR2  PVM1IM      LL_SYSCFG_GRP2_IsEnabledIT\n
01153   *         SYSCFG_IMR2  PVM3IM      LL_SYSCFG_GRP2_IsEnabledIT\n
01154   *         SYSCFG_IMR2  PVDIM       LL_SYSCFG_GRP2_IsEnabledIT
01155   * @param  Interrupt This parameter can be one of the following values:
01156   *         @arg @ref LL_SYSCFG_GRP2_PVM1
01157   *         @arg @ref LL_SYSCFG_GRP2_PVM3
01158   *         @arg @ref LL_SYSCFG_GRP2_PVD
01159   * @retval State of bit (1 or 0).
01160   */
01161 __STATIC_INLINE uint32_t LL_SYSCFG_GRP2_IsEnabledIT(uint32_t Interrupt)
01162 {
01163   return ((READ_BIT(SYSCFG->IMR2, Interrupt) != (Interrupt)) ? 1UL : 0UL);
01164 }
01165
01166 /**
01167   * @brief  Enable CPU2 Interrupt Mask
01168   * @rmtoll SYSCFG_C2IMR1  RTCSTAMPTAMPLSECSSIM      LL_C2_SYSCFG_GRP1_EnableIT\n
01169   *         SYSCFG_C2IMR1  RTCWKUPIM   LL_C2_SYSCFG_GRP1_EnableIT\n
01170   *         SYSCFG_C2IMR1  RTCALARMIM  LL_C2_SYSCFG_GRP1_EnableIT\n
01171   *         SYSCFG_C2IMR1  RCCIM       LL_C2_SYSCFG_GRP1_EnableIT\n
01172   *         SYSCFG_C2IMR1  FLASHIM     LL_C2_SYSCFG_GRP1_EnableIT\n
01173   *         SYSCFG_C2IMR1  PKAIM       LL_C2_SYSCFG_GRP1_EnableIT\n
01174   *         SYSCFG_C2IMR1  RNGIM       LL_C2_SYSCFG_GRP1_EnableIT\n
01175   *         SYSCFG_C2IMR1  AES1IM      LL_C2_SYSCFG_GRP1_EnableIT\n
01176   *         SYSCFG_C2IMR1  COMPIM      LL_C2_SYSCFG_GRP1_EnableIT\n
01177   *         SYSCFG_C2IMR1  ADCIM       LL_C2_SYSCFG_GRP1_EnableIT\n
01178   *         SYSCFG_C2IMR1  EXTIxIM     LL_C2_SYSCFG_GRP1_EnableIT
01179   * @param  Interrupt This parameter can be a combination of the following values:
01180   *         @arg @ref LL_C2_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS
01181   *         @arg @ref LL_C2_SYSCFG_GRP1_RTCWKUP
01182   *         @arg @ref LL_C2_SYSCFG_GRP1_RTCALARM
01183   *         @arg @ref LL_C2_SYSCFG_GRP1_RCC
01184   *         @arg @ref LL_C2_SYSCFG_GRP1_FLASH
01185   *         @arg @ref LL_C2_SYSCFG_GRP1_PKA
01186   *         @arg @ref LL_C2_SYSCFG_GRP1_RNG
01187   *         @arg @ref LL_C2_SYSCFG_GRP1_AES1
01188   *         @arg @ref LL_C2_SYSCFG_GRP1_COMP
01189   *         @arg @ref LL_C2_SYSCFG_GRP1_ADC
01190   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI0
01191   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI1
01192   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI2
01193   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI3
01194   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI4
01195   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI5
01196   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI6
01197   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI7
01198   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI8
01199   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI9
01200   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI10
01201   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI11
01202   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI12
01203   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI13
01204   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI14
01205   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI15
01206   * @retval None
01207   */
01208 __STATIC_INLINE void LL_C2_SYSCFG_GRP1_EnableIT(uint32_t Interrupt)
01209 {
01210   CLEAR_BIT(SYSCFG->C2IMR1, Interrupt);
01211 }
01212
01213 /**
01214   * @brief  Enable CPU2 Interrupt Mask
01215   * @rmtoll SYSCFG_C2IMR2  DMA1CHxIM   LL_C2_SYSCFG_GRP2_EnableIT\n
01216   *         SYSCFG_C2IMR2  DMA2CHxIM   LL_C2_SYSCFG_GRP2_EnableIT\n
01217   *         SYSCFG_C2IMR2  PVM1IM      LL_C2_SYSCFG_GRP2_EnableIT\n
01218   *         SYSCFG_C2IMR2  PVM3IM      LL_C2_SYSCFG_GRP2_EnableIT\n
01219   *         SYSCFG_C2IMR2  PVDIM       LL_C2_SYSCFG_GRP2_EnableIT\n
01220   *         SYSCFG_C2IMR2  TSCIM       LL_C2_SYSCFG_GRP2_EnableIT\n
01221   *         SYSCFG_C2IMR2  LCDIM       LL_C2_SYSCFG_GRP2_EnableIT
01222   * @param  Interrupt This parameter can be a combination of the following values:
01223   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH1
01224   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH2
01225   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH3
01226   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH4
01227   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH5
01228   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH6
01229   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH7
01230   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH1
01231   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH2
01232   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH3
01233   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH4
01234   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH5
01235   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH6
01236   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH7
01237   *         @arg @ref LL_C2_SYSCFG_GRP2_DMAMUX1
01238   *         @arg @ref LL_C2_SYSCFG_GRP2_PVM1
01239   *         @arg @ref LL_C2_SYSCFG_GRP2_PVM3
01240   *         @arg @ref LL_C2_SYSCFG_GRP2_PVD
01241   *         @arg @ref LL_C2_SYSCFG_GRP2_TSC
01242   *         @arg @ref LL_C2_SYSCFG_GRP2_LCD
01243   * @retval None
01244   */
01245 __STATIC_INLINE void LL_C2_SYSCFG_GRP2_EnableIT(uint32_t Interrupt)
01246 {
01247   CLEAR_BIT(SYSCFG->C2IMR2, Interrupt);
01248 }
01249
01250 /**
01251   * @brief  Disable CPU2 Interrupt Mask
01252   * @rmtoll SYSCFG_C2IMR1  RTCSTAMPTAMPLSECSSIM      LL_C2_SYSCFG_GRP1_DisableIT\n
01253   *         SYSCFG_C2IMR1  RTCWKUPIM   LL_C2_SYSCFG_GRP1_DisableIT\n
01254   *         SYSCFG_C2IMR1  RTCALARMIM  LL_C2_SYSCFG_GRP1_DisableIT\n
01255   *         SYSCFG_C2IMR1  RCCIM       LL_C2_SYSCFG_GRP1_DisableIT\n
01256   *         SYSCFG_C2IMR1  FLASHIM     LL_C2_SYSCFG_GRP1_DisableIT\n
01257   *         SYSCFG_C2IMR1  PKAIM       LL_C2_SYSCFG_GRP1_DisableIT\n
01258   *         SYSCFG_C2IMR1  RNGIM       LL_C2_SYSCFG_GRP1_DisableIT\n
01259   *         SYSCFG_C2IMR1  AES1IM      LL_C2_SYSCFG_GRP1_DisableIT\n
01260   *         SYSCFG_C2IMR1  COMPIM      LL_C2_SYSCFG_GRP1_DisableIT\n
01261   *         SYSCFG_C2IMR1  ADCIM       LL_C2_SYSCFG_GRP1_DisableIT\n
01262   *         SYSCFG_C2IMR1  EXTIxIM     LL_C2_SYSCFG_GRP1_DisableIT
01263   * @param  Interrupt This parameter can be a combination of the following values:
01264   *         @arg @ref LL_C2_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS
01265   *         @arg @ref LL_C2_SYSCFG_GRP1_RTCWKUP
01266   *         @arg @ref LL_C2_SYSCFG_GRP1_RTCALARM
01267   *         @arg @ref LL_C2_SYSCFG_GRP1_RCC
01268   *         @arg @ref LL_C2_SYSCFG_GRP1_FLASH
01269   *         @arg @ref LL_C2_SYSCFG_GRP1_PKA
01270   *         @arg @ref LL_C2_SYSCFG_GRP1_RNG
01271   *         @arg @ref LL_C2_SYSCFG_GRP1_AES1
01272   *         @arg @ref LL_C2_SYSCFG_GRP1_COMP
01273   *         @arg @ref LL_C2_SYSCFG_GRP1_ADC
01274   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI0
01275   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI1
01276   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI2
01277   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI3
01278   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI4
01279   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI5
01280   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI6
01281   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI7
01282   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI8
01283   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI9
01284   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI10
01285   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI11
01286   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI12
01287   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI13
01288   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI14
01289   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI15
01290   * @retval None
01291   */
01292 __STATIC_INLINE void LL_C2_SYSCFG_GRP1_DisableIT(uint32_t Interrupt)
01293 {
01294   SET_BIT(SYSCFG->C2IMR1, Interrupt);
01295 }
01296
01297 /**
01298   * @brief  Disable CPU2 Interrupt Mask
01299   * @rmtoll SYSCFG_C2IMR2  DMA1CHxIM   LL_C2_SYSCFG_GRP2_DisableIT\n
01300   *         SYSCFG_C2IMR2  DMA2CHxIM   LL_C2_SYSCFG_GRP2_DisableIT\n
01301   *         SYSCFG_C2IMR2  PVM1IM      LL_C2_SYSCFG_GRP2_DisableIT\n
01302   *         SYSCFG_C2IMR2  PVM3IM      LL_C2_SYSCFG_GRP2_DisableIT\n
01303   *         SYSCFG_C2IMR2  PVDIM       LL_C2_SYSCFG_GRP2_DisableIT\n
01304   *         SYSCFG_C2IMR2  TSCIM       LL_C2_SYSCFG_GRP2_DisableIT\n
01305   *         SYSCFG_C2IMR2  LCDIM       LL_C2_SYSCFG_GRP2_DisableIT
01306   * @param  Interrupt This parameter can be a combination of the following values:
01307   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH1
01308   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH2
01309   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH3
01310   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH4
01311   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH5
01312   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH6
01313   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH7
01314   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH1
01315   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH2
01316   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH3
01317   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH4
01318   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH5
01319   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH6
01320   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH7
01321   *         @arg @ref LL_C2_SYSCFG_GRP2_DMAMUX1
01322   *         @arg @ref LL_C2_SYSCFG_GRP2_PVM1
01323   *         @arg @ref LL_C2_SYSCFG_GRP2_PVM3
01324   *         @arg @ref LL_C2_SYSCFG_GRP2_PVD
01325   *         @arg @ref LL_C2_SYSCFG_GRP2_TSC
01326   *         @arg @ref LL_C2_SYSCFG_GRP2_LCD
01327   * @retval None
01328   */
01329 __STATIC_INLINE void LL_C2_SYSCFG_GRP2_DisableIT(uint32_t Interrupt)
01330 {
01331   SET_BIT(SYSCFG->C2IMR2, Interrupt);
01332 }
01333
01334 /**
01335   * @brief  Indicate if CPU2 Interrupt Mask is enabled
01336   * @rmtoll SYSCFG_C2IMR1  RTCSTAMPTAMPLSECSSIM      LL_C2_SYSCFG_GRP1_EnableIT\n
01337   *         SYSCFG_C2IMR1  RTCWKUPIM   LL_C2_SYSCFG_GRP1_IsEnabledIT\n
01338   *         SYSCFG_C2IMR1  RTCALARMIM  LL_C2_SYSCFG_GRP1_IsEnabledIT\n
01339   *         SYSCFG_C2IMR1  RCCIM       LL_C2_SYSCFG_GRP1_IsEnabledIT\n
01340   *         SYSCFG_C2IMR1  FLASHIM     LL_C2_SYSCFG_GRP1_IsEnabledIT\n
01341   *         SYSCFG_C2IMR1  PKAIM       LL_C2_SYSCFG_GRP1_IsEnabledIT\n
01342   *         SYSCFG_C2IMR1  RNGIM       LL_C2_SYSCFG_GRP1_IsEnabledIT\n
01343   *         SYSCFG_C2IMR1  AES1IM      LL_C2_SYSCFG_GRP1_IsEnabledIT\n
01344   *         SYSCFG_C2IMR1  COMPIM      LL_C2_SYSCFG_GRP1_IsEnabledIT\n
01345   *         SYSCFG_C2IMR1  ADCIM       LL_C2_SYSCFG_GRP1_IsEnabledIT\n
01346   *         SYSCFG_C2IMR1  EXTIxIM     LL_C2_SYSCFG_GRP1_IsEnabledIT
01347   * @param  Interrupt This parameter can be one of the following values:
01348   *         @arg @ref LL_C2_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS
01349   *         @arg @ref LL_C2_SYSCFG_GRP1_RTCWKUP
01350   *         @arg @ref LL_C2_SYSCFG_GRP1_RTCALARM
01351   *         @arg @ref LL_C2_SYSCFG_GRP1_RCC
01352   *         @arg @ref LL_C2_SYSCFG_GRP1_FLASH
01353   *         @arg @ref LL_C2_SYSCFG_GRP1_PKA
01354   *         @arg @ref LL_C2_SYSCFG_GRP1_RNG
01355   *         @arg @ref LL_C2_SYSCFG_GRP1_AES1
01356   *         @arg @ref LL_C2_SYSCFG_GRP1_COMP
01357   *         @arg @ref LL_C2_SYSCFG_GRP1_ADC
01358   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI0
01359   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI1
01360   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI2
01361   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI3
01362   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI4
01363   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI5
01364   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI6
01365   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI7
01366   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI8
01367   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI9
01368   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI10
01369   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI11
01370   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI12
01371   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI13
01372   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI14
01373   *         @arg @ref LL_C2_SYSCFG_GRP1_EXTI15
01374   * @retval State of bit (1 or 0).
01375   */
01376 __STATIC_INLINE uint32_t LL_C2_SYSCFG_GRP1_IsEnabledIT(uint32_t Interrupt)
01377 {
01378   return ((READ_BIT(SYSCFG->C2IMR1, Interrupt) != (Interrupt)) ? 1UL : 0UL);
01379 }
01380
01381 /**
01382   * @brief  Indicate if CPU2 Interrupt Mask is enabled
01383   * @rmtoll SYSCFG_C2IMR2  DMA1CHxIM   LL_C2_SYSCFG_GRP2_IsEnabledIT\n
01384   *         SYSCFG_C2IMR2  DMA2CHxIM   LL_C2_SYSCFG_GRP2_IsEnabledIT\n
01385   *         SYSCFG_C2IMR2  PVM1IM      LL_C2_SYSCFG_GRP2_IsEnabledIT\n
01386   *         SYSCFG_C2IMR2  PVM3IM      LL_C2_SYSCFG_GRP2_IsEnabledIT\n
01387   *         SYSCFG_C2IMR2  PVDIM       LL_C2_SYSCFG_GRP2_IsEnabledIT\n
01388   *         SYSCFG_C2IMR2  TSCIM       LL_C2_SYSCFG_GRP2_IsEnabledIT\n
01389   *         SYSCFG_C2IMR2  LCDIM       LL_C2_SYSCFG_GRP2_IsEnabledIT
01390   * @param  Interrupt This parameter can be one of the following values:
01391   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH1
01392   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH2
01393   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH3
01394   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH4
01395   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH5
01396   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH6
01397   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH7
01398   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH1
01399   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH2
01400   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH3
01401   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH4
01402   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH5
01403   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH6
01404   *         @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH7
01405   *         @arg @ref LL_C2_SYSCFG_GRP2_DMAMUX1
01406   *         @arg @ref LL_C2_SYSCFG_GRP2_PVM1
01407   *         @arg @ref LL_C2_SYSCFG_GRP2_PVM3
01408   *         @arg @ref LL_C2_SYSCFG_GRP2_PVD
01409   *         @arg @ref LL_C2_SYSCFG_GRP2_TSC
01410   *         @arg @ref LL_C2_SYSCFG_GRP2_LCD
01411   * @retval State of bit (1 or 0).
01412   */
01413 __STATIC_INLINE uint32_t LL_C2_SYSCFG_GRP2_IsEnabledIT(uint32_t Interrupt)
01414 {
01415   return ((READ_BIT(SYSCFG->C2IMR2, Interrupt) != (Interrupt)) ? 1UL : 0UL);
01416 }
01417
01418 /**
01419   * @brief  Enable the access for security IP
01420   * @rmtoll SYSCFG_SIPCR SAES1         LL_SYSCFG_EnableSecurityAccess\n
01421   *         SYSCFG_CFGR1 SAES2         LL_SYSCFG_EnableSecurityAccess\n
01422   *         SYSCFG_CFGR1 SPKA          LL_SYSCFG_EnableSecurityAccess\n
01423   *         SYSCFG_CFGR1 SRNG          LL_SYSCFG_EnableSecurityAccess
01424   * @param  SecurityAccess This parameter can be a combination of the following values:
01425   *         @arg @ref LL_SYSCFG_SECURE_ACCESS_AES1
01426   *         @arg @ref LL_SYSCFG_SECURE_ACCESS_AES2
01427   *         @arg @ref LL_SYSCFG_SECURE_ACCESS_PKA
01428   *         @arg @ref LL_SYSCFG_SECURE_ACCESS_RNG
01429   * @retval None
01430   */
01431 __STATIC_INLINE void LL_SYSCFG_EnableSecurityAccess(uint32_t SecurityAccess)
01432 {
01433   SET_BIT(SYSCFG->SIPCR, SecurityAccess);
01434 }
01435
01436 /**
01437   * @brief  Disable the access for security IP
01438   * @rmtoll SYSCFG_SIPCR SAES1         LL_SYSCFG_DisableSecurityAccess\n
01439   *         SYSCFG_CFGR1 SAES2         LL_SYSCFG_DisableSecurityAccess\n
01440   *         SYSCFG_CFGR1 SPKA          LL_SYSCFG_DisableSecurityAccess\n
01441   *         SYSCFG_CFGR1 SRNG          LL_SYSCFG_DisableSecurityAccess
01442   * @param  SecurityAccess This parameter can be a combination of the following values:
01443   *         @arg @ref LL_SYSCFG_SECURE_ACCESS_AES1
01444   *         @arg @ref LL_SYSCFG_SECURE_ACCESS_AES2
01445   *         @arg @ref LL_SYSCFG_SECURE_ACCESS_PKA
01446   *         @arg @ref LL_SYSCFG_SECURE_ACCESS_RNG
01447   * @retval None
01448   */
01449 __STATIC_INLINE void LL_SYSCFG_DisableSecurityAccess(uint32_t SecurityAccess)
01450 {
01451   CLEAR_BIT(SYSCFG->SIPCR, SecurityAccess);
01452 }
01453
01454 /**
01455   * @brief  Indicate if access for security IP is enabled
01456   * @rmtoll SYSCFG_SIPCR SAES1         LL_SYSCFG_IsEnabledSecurityAccess\n
01457   *         SYSCFG_CFGR1 SAES2         LL_SYSCFG_IsEnabledSecurityAccess\n
01458   *         SYSCFG_CFGR1 SPKA          LL_SYSCFG_IsEnabledSecurityAccess\n
01459   *         SYSCFG_CFGR1 SRNG          LL_SYSCFG_IsEnabledSecurityAccess
01460   * @param  SecurityAccess This parameter can be one of the following values:
01461   *         @arg @ref LL_SYSCFG_SECURE_ACCESS_AES1
01462   *         @arg @ref LL_SYSCFG_SECURE_ACCESS_AES2
01463   *         @arg @ref LL_SYSCFG_SECURE_ACCESS_PKA
01464   *         @arg @ref LL_SYSCFG_SECURE_ACCESS_RNG
01465   * @retval State of bit (1 or 0).
01466   */
01467 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledSecurityAccess(uint32_t SecurityAccess)
01468 {
01469   return ((READ_BIT(SYSCFG->SIPCR, SecurityAccess) == (SecurityAccess)) ? 1UL : 0UL);
01470 }
01471
01472 /**
01473   * @}
01474   */
01475
01476 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
01477   * @note  DBGMCU is only accessible by Cortex M4
01478   *        To access on DBGMCU, Cortex M0+ need to request to the Cortex M4
01479   *        the action.
01480   * @{
01481   */
01482
01483 /**
01484   * @brief  Return the device identifier
01485   * @note   For STM32WBxxxx devices, the device ID is 0x495
01486   * @rmtoll DBGMCU_IDCODE DEV_ID        LL_DBGMCU_GetDeviceID
01487   * @retval Values between Min_Data=0x00 and Max_Data=0xFFF (ex: device ID is 0x495)
01488   */
01489 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
01490 {
01491   return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
01492 }
01493
01494 /**
01495   * @brief  Return the device revision identifier
01496   * @note   This field indicates the revision of the device.
01497   * @rmtoll DBGMCU_IDCODE REV_ID        LL_DBGMCU_GetRevisionID
01498   * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
01499   */
01500 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
01501 {
01502   return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
01503 }
01504
01505 /**
01506   * @brief  Enable the Debug Module during SLEEP mode
01507   * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_EnableDBGSleepMode
01508   * @retval None
01509   */
01510 __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
01511 {
01512   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
01513 }
01514
01515 /**
01516   * @brief  Disable the Debug Module during SLEEP mode
01517   * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_DisableDBGSleepMode
01518   * @retval None
01519   */
01520 __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
01521 {
01522   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
01523 }
01524
01525 /**
01526   * @brief  Enable the Debug Module during STOP mode
01527   * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_EnableDBGStopMode
01528   * @retval None
01529   */
01530 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
01531 {
01532   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
01533 }
01534
01535 /**
01536   * @brief  Disable the Debug Module during STOP mode
01537   * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_DisableDBGStopMode
01538   * @retval None
01539   */
01540 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
01541 {
01542   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
01543 }
01544
01545 /**
01546   * @brief  Enable the Debug Module during STANDBY mode
01547   * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_EnableDBGStandbyMode
01548   * @retval None
01549   */
01550 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
01551 {
01552   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
01553 }
01554
01555 /**
01556   * @brief  Disable the Debug Module during STANDBY mode
01557   * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_DisableDBGStandbyMode
01558   * @retval None
01559   */
01560 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
01561 {
01562   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
01563 }
01564
01565 /**
01566   * @brief  Enable the clock for Trace port
01567   * @rmtoll DBGMCU_CR TRACE_CLKEN         LL_DBGMCU_EnableTraceClock\n
01568   */
01569 __STATIC_INLINE void LL_DBGMCU_EnableTraceClock(void)
01570 {
01571   SET_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN);
01572 }
01573
01574 /**
01575   * @brief  Disable the clock for Trace port
01576   * @rmtoll DBGMCU_CR TRACE_CLKEN         LL_DBGMCU_DisableTraceClock\n
01577   * @retval None
01578   */
01579 __STATIC_INLINE void LL_DBGMCU_DisableTraceClock(void)
01580 {
01581   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN);
01582 }
01583
01584 /**
01585   * @brief  Indicate if the clock for Trace port is enabled
01586   * @rmtoll DBGMCU_CR TRACE_CLKEN         LL_DBGMCU_IsEnabledTraceClock\n
01587   * @retval State of bit (1 or 0).
01588   */
01589 __STATIC_INLINE uint32_t LL_DBGMCU_IsEnabledTraceClock(void)
01590 {
01591   return ((READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN) == (DBGMCU_CR_TRACE_IOEN)) ? 1UL : 0UL);
01592 }
01593
01594 /**
01595   * @brief  Enable the external trigger ouput
01596   * @note   When enable the external trigger is output (state of bit 1),
01597   *         TRGIO pin is connected to TRGOUT.
01598   * @rmtoll DBGMCU_CR TRGOEN         LL_DBGMCU_EnableTriggerOutput\n
01599   */
01600 __STATIC_INLINE void LL_DBGMCU_EnableTriggerOutput(void)
01601 {
01602   SET_BIT(DBGMCU->CR, DBGMCU_CR_TRGOEN);
01603 }
01604
01605 /**
01606   * @brief  Disable the external trigger ouput
01607   * @note   When disable external trigger is input (state of bit 0),
01608   *         TRGIO pin is connected to TRGIN.
01609   * @rmtoll DBGMCU_CR TRGOEN         LL_DBGMCU_DisableTriggerOutput\n
01610   * @retval None
01611   */
01612 __STATIC_INLINE void LL_DBGMCU_DisableTriggerOutput(void)
01613 {
01614   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_TRGOEN);
01615 }
01616
01617 /**
01618   * @brief  Indicate if the external trigger is output or input direction
01619   * @note   When the external trigger is output (state of bit 1),
01620   *         TRGIO pin is connected to TRGOUT.
01621   *         When the external trigger is input (state of bit 0),
01622   *         TRGIO pin is connected to TRGIN.
01623   * @rmtoll DBGMCU_CR TRGOEN         LL_DBGMCU_EnableTriggerOutput\n
01624   * @retval State of bit (1 or 0).
01625   */
01626 __STATIC_INLINE uint32_t LL_DBGMCU_IsEnabledTriggerOutput(void)
01627 {
01628   return ((READ_BIT(DBGMCU->CR, DBGMCU_CR_TRGOEN) == (DBGMCU_CR_TRGOEN)) ? 1UL : 0UL);
01629 }
01630
01631 /**
01632   * @brief  Freeze CPU1 APB1 peripherals (group1 peripherals)
01633   * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP1_FreezePeriph
01634   * @param  Periphs This parameter can be a combination of the following values:
01635   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
01636   *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
01637   *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
01638   *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
01639   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
01640   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
01641   *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
01642   * @retval None
01643   */
01644 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
01645 {
01646   SET_BIT(DBGMCU->APB1FZR1, Periphs);
01647 }
01648
01649 /**
01650   * @brief  Freeze CPU2 APB1 peripherals (group1 peripherals)
01651   * @rmtoll DBGMCU_C2APB1FZR1 DBG_xxxx_STOP  LL_C2_DBGMCU_APB1_GRP1_FreezePeriph
01652   * @param  Periphs This parameter can be a combination of the following values:
01653   *         @arg @ref LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP
01654   *         @arg @ref LL_C2_DBGMCU_APB1_GRP1_RTC_STOP
01655   *         @arg @ref LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP
01656   *         @arg @ref LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP
01657   *         @arg @ref LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP
01658   *         @arg @ref LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP
01659   * @retval None
01660   */
01661 __STATIC_INLINE void LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
01662 {
01663   SET_BIT(DBGMCU->C2APB1FZR1, Periphs);
01664 }
01665
01666 /**
01667   * @brief  Freeze CPU1 APB1 peripherals (group2 peripherals)
01668   * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP2_FreezePeriph
01669   * @param  Periphs This parameter can be a combination of the following values:
01670   *         @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
01671   * @retval None
01672   */
01673 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
01674 {
01675   SET_BIT(DBGMCU->APB1FZR2, Periphs);
01676 }
01677
01678 /**
01679   * @brief  Freeze CPU2 APB1 peripherals (group2 peripherals)
01680   * @rmtoll DBGMCU_C2APB1FZR2 DBG_xxxx_STOP  LL_C2_DBGMCU_APB1_GRP2_FreezePeriph
01681   * @param  Periphs This parameter can be a combination of the following values:
01682   *         @arg @ref LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP
01683   * @retval None
01684   */
01685 __STATIC_INLINE void LL_C2_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
01686 {
01687   SET_BIT(DBGMCU->C2APB1FZR2, Periphs);
01688 }
01689
01690 /**
01691   * @brief  Unfreeze CPU1 APB1 peripherals (group1 peripherals)
01692   * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP1_UnFreezePeriph
01693   * @param  Periphs This parameter can be a combination of the following values:
01694   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
01695   *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
01696   *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
01697   *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
01698   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
01699   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
01700   *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
01701   * @retval None
01702   */
01703 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
01704 {
01705   CLEAR_BIT(DBGMCU->APB1FZR1, Periphs);
01706 }
01707
01708 /**
01709   * @brief  Unfreeze CPU2 APB1 peripherals (group1 peripherals)
01710   * @rmtoll DBGMCU_C2APB1FZR1 DBG_xxxx_STOP  LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph
01711   * @param  Periphs This parameter can be a combination of the following values:
01712   *         @arg @ref LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP
01713   *         @arg @ref LL_C2_DBGMCU_APB1_GRP1_RTC_STOP
01714   *         @arg @ref LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP
01715   *         @arg @ref LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP
01716   *         @arg @ref LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP
01717   *         @arg @ref LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP
01718   * @retval None
01719   */
01720 __STATIC_INLINE void LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
01721 {
01722   CLEAR_BIT(DBGMCU->C2APB1FZR1, Periphs);
01723 }
01724
01725 /**
01726   * @brief  Unfreeze CPU1 APB1 peripherals (group2 peripherals)
01727   * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP2_UnFreezePeriph
01728   * @param  Periphs This parameter can be a combination of the following values:
01729   *         @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
01730   * @retval None
01731   */
01732 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
01733 {
01734   CLEAR_BIT(DBGMCU->APB1FZR2, Periphs);
01735 }
01736
01737 /**
01738   * @brief  Unfreeze CPU2 APB1 peripherals (group2 peripherals)
01739   * @rmtoll DBGMCU_C2APB1FZR2 DBG_xxxx_STOP  LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph
01740   * @param  Periphs This parameter can be a combination of the following values:
01741   *         @arg @ref LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP
01742   * @retval None
01743   */
01744 __STATIC_INLINE void LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
01745 {
01746   CLEAR_BIT(DBGMCU->C2APB1FZR2, Periphs);
01747 }
01748
01749 /**
01750   * @brief  Freeze CPU1 APB2 peripherals
01751   * @rmtoll DBGMCU_APB2FZR DBG_TIMx_STOP  LL_DBGMCU_APB2_GRP1_FreezePeriph
01752   * @param  Periphs This parameter can be a combination of the following values:
01753   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
01754   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
01755   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
01756   * @retval None
01757   */
01758 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
01759 {
01760   SET_BIT(DBGMCU->APB2FZR, Periphs);
01761 }
01762
01763 /**
01764   * @brief  Freeze CPU2 APB2 peripherals
01765   * @rmtoll DBGMCU_C2APB2FZR DBG_TIMx_STOP  LL_C2_DBGMCU_APB2_GRP1_FreezePeriph
01766   * @param  Periphs This parameter can be a combination of the following values:
01767   *         @arg @ref LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP
01768   *         @arg @ref LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP
01769   *         @arg @ref LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP
01770   * @retval None
01771   */
01772 __STATIC_INLINE void LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
01773 {
01774   SET_BIT(DBGMCU->C2APB2FZR, Periphs);
01775 }
01776
01777 /**
01778   * @brief  Unfreeze CPU1 APB2 peripherals
01779   * @rmtoll DBGMCU_APB2FZR DBG_TIMx_STOP  LL_DBGMCU_APB2_GRP1_UnFreezePeriph
01780   * @param  Periphs This parameter can be a combination of the following values:
01781   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
01782   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
01783   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
01784   * @retval None
01785   */
01786 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
01787 {
01788   CLEAR_BIT(DBGMCU->APB2FZR, Periphs);
01789 }
01790
01791 /**
01792   * @brief  Unfreeze CPU2 APB2 peripherals
01793   * @rmtoll DBGMCU_C2APB2FZR DBG_TIMx_STOP  LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph
01794   * @param  Periphs This parameter can be a combination of the following values:
01795   *         @arg @ref LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP
01796   *         @arg @ref LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP
01797   *         @arg @ref LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP
01798   * @retval None
01799   */
01800 __STATIC_INLINE void LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
01801 {
01802   CLEAR_BIT(DBGMCU->C2APB2FZR, Periphs);
01803 }
01804
01805 /**
01806   * @}
01807   */
01808
01809 #if defined(VREFBUF)
01810 /** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF
01811   * @{
01812   */
01813
01814 /**
01815   * @brief  Enable Internal voltage reference
01816   * @rmtoll VREFBUF_CSR  ENVR          LL_VREFBUF_Enable
01817   * @retval None
01818   */
01819 __STATIC_INLINE void LL_VREFBUF_Enable(void)
01820 {
01821   SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
01822 }
01823
01824 /**
01825   * @brief  Disable Internal voltage reference
01826   * @rmtoll VREFBUF_CSR  ENVR          LL_VREFBUF_Disable
01827   * @retval None
01828   */
01829 __STATIC_INLINE void LL_VREFBUF_Disable(void)
01830 {
01831   CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
01832 }
01833
01834 /**
01835   * @brief  Enable high impedance (VREF+pin is high impedance)
01836   * @rmtoll VREFBUF_CSR  HIZ           LL_VREFBUF_EnableHIZ
01837   * @retval None
01838   */
01839 __STATIC_INLINE void LL_VREFBUF_EnableHIZ(void)
01840 {
01841   SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
01842 }
01843
01844 /**
01845   * @brief  Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
01846   * @rmtoll VREFBUF_CSR  HIZ           LL_VREFBUF_DisableHIZ
01847   * @retval None
01848   */
01849 __STATIC_INLINE void LL_VREFBUF_DisableHIZ(void)
01850 {
01851   CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
01852 }
01853
01854 /**
01855   * @brief  Set the Voltage reference scale
01856   * @rmtoll VREFBUF_CSR  VRS           LL_VREFBUF_SetVoltageScaling
01857   * @param  Scale This parameter can be one of the following values:
01858   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
01859   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
01860   * @retval None
01861   */
01862 __STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale)
01863 {
01864   MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale);
01865 }
01866
01867 /**
01868   * @brief  Get the Voltage reference scale
01869   * @rmtoll VREFBUF_CSR  VRS           LL_VREFBUF_GetVoltageScaling
01870   * @retval Returned value can be one of the following values:
01871   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
01872   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
01873   */
01874 __STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void)
01875 {
01876   return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS));
01877 }
01878
01879 /**
01880   * @brief  Check if Voltage reference buffer is ready
01881   * @rmtoll VREFBUF_CSR  VRR           LL_VREFBUF_IsVREFReady
01882   * @retval State of bit (1 or 0).
01883   */
01884 __STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void)
01885 {
01886   return ((READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == (VREFBUF_CSR_VRR)) ? 1UL : 0UL);
01887 }
01888
01889 /**
01890   * @brief  Get the trimming code for VREFBUF calibration
01891   * @rmtoll VREFBUF_CCR  TRIM          LL_VREFBUF_GetTrimming
01892   * @retval Between 0 and 0x3F
01893   */
01894 __STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void)
01895 {
01896   return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM));
01897 }
01898
01899 /**
01900   * @brief  Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)
01901   * @rmtoll VREFBUF_CCR  TRIM          LL_VREFBUF_SetTrimming
01902   * @param  Value Between 0 and 0x3F
01903   * @retval None
01904   */
01905 __STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value)
01906 {
01907   WRITE_REG(VREFBUF->CCR, Value);
01908 }
01909
01910 /**
01911   * @}
01912   */
01913 #endif /* VREFBUF */
01914
01915 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
01916   * @{
01917   */
01918
01919 /**
01920   * @brief  Set FLASH Latency
01921   * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_SetLatency
01922   * @param  Latency This parameter can be one of the following values:
01923   *         @arg @ref LL_FLASH_LATENCY_0
01924   *         @arg @ref LL_FLASH_LATENCY_1
01925   *         @arg @ref LL_FLASH_LATENCY_2
01926   *         @arg @ref LL_FLASH_LATENCY_3
01927   * @retval None
01928   */
01929 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
01930 {
01931   MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
01932 }
01933
01934 /**
01935   * @brief  Get FLASH Latency
01936   * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_GetLatency
01937   * @retval Returned value can be one of the following values:
01938   *         @arg @ref LL_FLASH_LATENCY_0
01939   *         @arg @ref LL_FLASH_LATENCY_1
01940   *         @arg @ref LL_FLASH_LATENCY_2
01941   *         @arg @ref LL_FLASH_LATENCY_3
01942   */
01943 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
01944 {
01945   return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
01946 }
01947
01948 /**
01949   * @brief  Enable Prefetch
01950   * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_EnablePrefetch
01951   * @retval None
01952   */
01953 __STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
01954 {
01955   SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
01956 }
01957
01958 /**
01959   * @brief  Disable Prefetch
01960   * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_DisablePrefetch
01961   * @rmtoll FLASH_C2ACR  PRFTEN        LL_FLASH_DisablePrefetch
01962   * @retval None
01963   */
01964 __STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
01965 {
01966   CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
01967 }
01968
01969 /**
01970   * @brief  Check if Prefetch buffer is enabled
01971   * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_IsPrefetchEnabled
01972   * @rmtoll FLASH_C2ACR  C2PRFTEN      LL_FLASH_IsPrefetchEnabled
01973   * @retval State of bit (1 or 0).
01974   */
01975 __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
01976 {
01977   return ((READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN)) ? 1UL : 0UL);
01978 }
01979
01980 /**
01981   * @brief  Enable Instruction cache
01982   * @rmtoll FLASH_ACR    ICEN          LL_FLASH_EnableInstCache
01983   * @rmtoll FLASH_C2ACR  ICEN          LL_FLASH_EnableInstCache
01984   * @retval None
01985   */
01986 __STATIC_INLINE void LL_FLASH_EnableInstCache(void)
01987 {
01988   SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
01989 }
01990
01991 /**
01992   * @brief  Disable Instruction cache
01993   * @rmtoll FLASH_ACR    ICEN          LL_FLASH_DisableInstCache
01994   * @rmtoll FLASH_C2ACR  ICEN          LL_FLASH_DisableInstCache
01995   * @retval None
01996   */
01997 __STATIC_INLINE void LL_FLASH_DisableInstCache(void)
01998 {
01999   CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
02000 }
02001
02002 /**
02003   * @brief  Enable Data cache
02004   * @rmtoll FLASH_ACR    DCEN          LL_FLASH_EnableDataCache
02005   * @retval None
02006   */
02007 __STATIC_INLINE void LL_FLASH_EnableDataCache(void)
02008 {
02009   SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);
02010 }
02011
02012 /**
02013   * @brief  Disable Data cache
02014   * @rmtoll FLASH_ACR    DCEN          LL_FLASH_DisableDataCache
02015   * @retval None
02016   */
02017 __STATIC_INLINE void LL_FLASH_DisableDataCache(void)
02018 {
02019   CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);
02020 }
02021
02022 /**
02023   * @brief  Enable Instruction cache reset
02024   * @note  bit can be written only when the instruction cache is disabled
02025   * @rmtoll FLASH_ACR    ICRST         LL_FLASH_EnableInstCacheReset
02026   * @rmtoll FLASH_C2ACR  ICRST         LL_FLASH_EnableInstCacheReset
02027   * @retval None
02028   */
02029 __STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
02030 {
02031   SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
02032 }
02033
02034 /**
02035   * @brief  Disable Instruction cache reset
02036   * @rmtoll FLASH_ACR    ICRST         LL_FLASH_DisableInstCacheReset
02037   * @rmtoll FLASH_C2ACR  ICRST         LL_FLASH_DisableInstCacheReset
02038   * @retval None
02039   */
02040 __STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
02041 {
02042   CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
02043 }
02044
02045 /**
02046   * @brief  Enable Data cache reset
02047   * @note bit can be written only when the data cache is disabled
02048   * @rmtoll FLASH_ACR    DCRST         LL_FLASH_EnableDataCacheReset
02049   * @retval None
02050   */
02051 __STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void)
02052 {
02053   SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);
02054 }
02055
02056 /**
02057   * @brief  Disable Data cache reset
02058   * @rmtoll FLASH_ACR    DCRST         LL_FLASH_DisableDataCacheReset
02059   * @retval None
02060   */
02061 __STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void)
02062 {
02063   CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);
02064 }
02065
02066 /**
02067   * @brief  Suspend new program or erase operation request
02068   * @note   Any new Flash program and erase operation on both CPU side will be suspended
02069   *         until this bit and the same bit in Flash CPU2 access control register (FLASH_C2ACR) are
02070   *         cleared. The PESD bit in both the Flash status register (FLASH_SR) and Flash
02071   *         CPU2 status register (FLASH_C2SR) register will be set when at least one PES
02072   *         bit in FLASH_ACR or FLASH_C2ACR is set.
02073   * @rmtoll FLASH_ACR    PES         LL_FLASH_SuspendOperation
02074   * @rmtoll FLASH_C2ACR  PES         LL_FLASH_SuspendOperation
02075   * @retval None
02076   */
02077 __STATIC_INLINE void LL_FLASH_SuspendOperation(void)
02078 {
02079   SET_BIT(FLASH->ACR, FLASH_ACR_PES);
02080 }
02081
02082 /**
02083   * @brief  Allow new program or erase operation request
02084   * @note   Any new Flash program and erase operation on both CPU side will be allowed
02085   *         until one of this bit or the same bit in Flash CPU2 access control register (FLASH_C2ACR) is
02086   *         set. The PESD bit in both the Flash status register (FLASH_SR) and Flash
02087   *         CPU2 status register (FLASH_C2SR) register will be clear when both PES
02088   *         bit in FLASH_ACR or FLASH_C2ACR is cleared.
02089   * @rmtoll FLASH_ACR    PES      LL_FLASH_AllowOperation
02090   * @rmtoll FLASH_C2ACR  PES      LL_FLASH_AllowOperation
02091   * @retval None
02092   */
02093 __STATIC_INLINE void LL_FLASH_AllowOperation(void)
02094 {
02095   CLEAR_BIT(FLASH->ACR, FLASH_ACR_PES);
02096 }
02097
02098 /**
02099   * @brief  Check if new program or erase operation request from CPU2 is suspended
02100   * @rmtoll FLASH_ACR    PES         LL_FLASH_IsOperationSuspended
02101   * @rmtoll FLASH_C2ACR  PES         LL_FLASH_IsOperationSuspended
02102   * @retval State of bit (1 or 0).
02103   */
02104 __STATIC_INLINE uint32_t LL_FLASH_IsOperationSuspended(void)
02105 {
02106   return ((READ_BIT(FLASH->ACR, FLASH_ACR_PES) == (FLASH_ACR_PES)) ? 1UL : 0UL);
02107 }
02108
02109 /**
02110   * @brief  Check if new program or erase operation request from CPU1 or CPU2 is suspended
02111   * @rmtoll FLASH_SR      PESD         LL_FLASH_IsActiveFlag_OperationSuspended
02112   * @rmtoll FLASH_C2SR    PESD         LL_FLASH_IsActiveFlag_OperationSuspended
02113   * @retval State of bit (1 or 0).
02114   */
02115 __STATIC_INLINE uint32_t LL_FLASH_IsActiveFlag_OperationSuspended(void)
02116 {
02117   return ((READ_BIT(FLASH->SR, FLASH_SR_PESD) == (FLASH_SR_PESD)) ? 1UL : 0UL);
02118 }
02119
02120 /**
02121   * @brief  Set EMPTY flag information as Flash User area empty
02122   * @rmtoll FLASH_ACR    EMPTY      LL_FLASH_SetEmptyFlag
02123   * @retval None
02124   */
02125 __STATIC_INLINE void LL_FLASH_SetEmptyFlag(void)
02126 {
02127   SET_BIT(FLASH->ACR, FLASH_ACR_EMPTY);
02128 }
02129
02130 /**
02131   * @brief  Clear EMPTY flag information as Flash User area programmed
02132   * @rmtoll FLASH_ACR    EMPTY      LL_FLASH_ClearEmptyFlag
02133   * @retval None
02134   */
02135 __STATIC_INLINE void LL_FLASH_ClearEmptyFlag(void)
02136 {
02137   CLEAR_BIT(FLASH->ACR, FLASH_ACR_EMPTY);
02138 }
02139
02140 /**
02141   * @brief  Check if the EMPTY flag is set or reset
02142   * @rmtoll FLASH_ACR    EMPTY      LL_FLASH_IsEmptyFlag
02143   * @retval State of bit (1 or 0).
02144   */
02145 __STATIC_INLINE uint32_t LL_FLASH_IsEmptyFlag(void)
02146 {
02147   return ((READ_BIT(FLASH->ACR, FLASH_ACR_EMPTY) == FLASH_ACR_EMPTY) ? 1UL : 0UL);
02148 }
02149
02150 /**
02151   * @brief  Get IPCC buffer base address
02152   * @rmtoll FLASH_IPCCBR    IPCCDBA       LL_FLASH_GetIPCCBufferAddr
02153   * @retval IPCC data buffer base address offset
02154   */
02155 __STATIC_INLINE uint32_t LL_FLASH_GetIPCCBufferAddr(void)
02156 {
02157   return (uint32_t)(READ_BIT(FLASH->IPCCBR, FLASH_IPCCBR_IPCCDBA));
02158 }
02159
02160 /**
02161   * @brief  Get CPU2 boot reset vector
02162   * @rmtoll FLASH_SRRVR    SBRV       LL_FLASH_GetC2BootResetVect
02163   * @retval CPU2 boot reset vector
02164   */
02165 __STATIC_INLINE uint32_t LL_FLASH_GetC2BootResetVect(void)
02166 {
02167   return (uint32_t)(READ_BIT(FLASH->SRRVR, FLASH_SRRVR_SBRV));
02168 }
02169
02170 /**
02171   * @brief  Return the Unique Device Number
02172   * @note   The 64-bit UID64 may be used by Firmware to derive BLE 48-bit Device Address EUI-48 or
02173   *         802.15.4 64-bit Device Address EUI-64.
02174   * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
02175   */
02176 __STATIC_INLINE uint32_t LL_FLASH_GetUDN(void)
02177 {
02178   return (uint32_t)(READ_REG(*((uint32_t *)UID64_BASE)));
02179 }
02180
02181 /**
02182   * @brief  Return the Device ID
02183   * @note   The 64-bit UID64 may be used by Firmware to derive BLE 48-bit Device Address EUI-48 or
02184   *         802.15.4 64-bit Device Address EUI-64.
02185   *         For STM32WBxxxx devices, the device ID is 0x26
02186   * @retval Values between Min_Data=0x00 and Max_Data=0xFF (ex: Device ID is 0x26 fo STM32WB55x)
02187   */
02188 __STATIC_INLINE uint32_t LL_FLASH_GetDeviceID(void)
02189 {
02190   return (uint32_t)((READ_REG(*((uint32_t *)UID64_BASE + 1U))) & 0x000000FFU);
02191 }
02192
02193 /**
02194   * @brief  Return the ST Company ID
02195   * @note   The 64-bit UID64 may be used by Firmware to derive BLE 48-bit Device Address EUI-48 or
02196   *         802.15.4 64-bit Device Address EUI-64.
02197   *         For STM32WBxxxx devices, the ST Compagny ID is 0x0080E1
02198   * @retval Values between Min_Data=0x00 and Max_Data=0xFFFFFF (ex: ST Compagny ID is 0x0080E1)
02199   */
02200 __STATIC_INLINE uint32_t LL_FLASH_GetSTCompanyID(void)
02201 {
02202   return (uint32_t)(((READ_REG(*((uint32_t *)UID64_BASE + 1U))) >> 8U ) & 0x00FFFFFFU);
02203 }
02204 /**
02205   * @}
02206   */
02207
02208 /**
02209   * @}
02210   */
02211
02212 /**
02213   * @}
02214   */
02215
02216 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) */
02217
02218 /**
02219   * @}
02220   */
02221
02222 #ifdef __cplusplus
02223 }
02224 #endif
02225
02226 #endif /* STM32WBxx_LL_SYSTEM_H */
02227
02228 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_tim.c Source File

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stm32wbxx_ll_tim.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_tim.c
00004   * @author  MCD Application Team
00005   * @brief   TIM LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32wbxx_ll_tim.h"
00023 #include "stm32wbxx_ll_bus.h"
00024
00025 #ifdef  USE_FULL_ASSERT
00026 #include "stm32_assert.h"
00027 #else
00028 #define assert_param(expr) ((void)0U)
00029 #endif /* USE_FULL_ASSERT */
00030
00031 /** @addtogroup STM32WBxx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (TIM1) || defined (TIM2) || defined (TIM16) || defined (TIM7)
00036
00037 /** @addtogroup TIM_LL
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /* Private macros ------------------------------------------------------------*/
00045 /** @addtogroup TIM_LL_Private_Macros
00046   * @{
00047   */
00048 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
00049                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
00050                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
00051                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
00052                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
00053
00054 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
00055                                             || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
00056                                             || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
00057
00058 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
00059                                      || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
00060                                      || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
00061                                      || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
00062                                      || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
00063                                      || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
00064                                      || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
00065                                      || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
00066                                      || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
00067                                      || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
00068                                      || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
00069                                      || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
00070                                      || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
00071                                      || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
00072
00073 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
00074                                       || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
00075
00076 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
00077                                          || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
00078
00079 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
00080                                           || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
00081
00082 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
00083                                           || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
00084                                           || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
00085
00086 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
00087                                     || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
00088                                     || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
00089                                     || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
00090
00091 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
00092                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
00093                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
00094                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
00095                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
00096                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
00097                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
00098                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
00099                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
00100                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
00101                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
00102                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
00103                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
00104                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
00105                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
00106                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
00107
00108 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
00109                                           || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
00110                                           || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
00111
00112 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
00113                                           || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
00114                                           || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
00115
00116 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
00117                                                   || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
00118
00119 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
00120                                          || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
00121
00122 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
00123                                          || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
00124
00125 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
00126                                          || ((__VALUE__) == LL_TIM_LOCKLEVEL_1)   \
00127                                          || ((__VALUE__) == LL_TIM_LOCKLEVEL_2)   \
00128                                          || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
00129
00130 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
00131                                           || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
00132
00133 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
00134                                              || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
00135
00136 #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1)     \
00137                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2)  \
00138                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4)  \
00139                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8)  \
00140                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6)  \
00141                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8)  \
00142                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6)  \
00143                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8)  \
00144                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6)  \
00145                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8)  \
00146                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
00147                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
00148                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
00149                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
00150                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
00151                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
00152
00153 #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
00154                                            || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
00155
00156 #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
00157                                               || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
00158
00159 #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1)    \
00160                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2)  \
00161                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4)  \
00162                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8)  \
00163                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6)  \
00164                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8)  \
00165                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6)  \
00166                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8)  \
00167                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6)  \
00168                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8)  \
00169                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
00170                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
00171                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
00172                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
00173                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
00174                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
00175
00176 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
00177                                                      || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
00178 /**
00179   * @}
00180   */
00181
00182
00183 /* Private function prototypes -----------------------------------------------*/
00184 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
00185   * @{
00186   */
00187 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
00188 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
00189 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
00190 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
00191 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
00192 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
00193 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
00194 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
00195 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
00196 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
00197 /**
00198   * @}
00199   */
00200
00201 /* Exported functions --------------------------------------------------------*/
00202 /** @addtogroup TIM_LL_Exported_Functions
00203   * @{
00204   */
00205
00206 /** @addtogroup TIM_LL_EF_Init
00207   * @{
00208   */
00209
00210 /**
00211   * @brief  Set TIMx registers to their reset values.
00212   * @param  TIMx Timer instance
00213   * @retval An ErrorStatus enumeration value:
00214   *          - SUCCESS: TIMx registers are de-initialized
00215   *          - ERROR: invalid TIMx instance
00216   */
00217 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
00218 {
00219   ErrorStatus result = SUCCESS;
00220
00221   /* Check the parameters */
00222   assert_param(IS_TIM_INSTANCE(TIMx));
00223
00224   if (TIMx == TIM1)
00225   {
00226     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
00227     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
00228   }
00229   else if (TIMx == TIM2)
00230   {
00231     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
00232     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
00233   }
00234   else if (TIMx == TIM16)
00235   {
00236     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
00237     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
00238   }
00239   else if (TIMx == TIM17)
00240   {
00241     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
00242     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
00243   }
00244   else
00245   {
00246     result = ERROR;
00247   }
00248
00249   return result;
00250 }
00251
00252 /**
00253   * @brief  Set the fields of the time base unit configuration data structure
00254   *         to their default values.
00255   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
00256   * @retval None
00257   */
00258 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
00259 {
00260   /* Set the default configuration */
00261   TIM_InitStruct->Prescaler         = (uint16_t)0x0000;
00262   TIM_InitStruct->CounterMode       = LL_TIM_COUNTERMODE_UP;
00263   TIM_InitStruct->Autoreload        = 0xFFFFFFFFU;
00264   TIM_InitStruct->ClockDivision     = LL_TIM_CLOCKDIVISION_DIV1;
00265   TIM_InitStruct->RepetitionCounter = (uint8_t)0x00;
00266 }
00267
00268 /**
00269   * @brief  Configure the TIMx time base unit.
00270   * @param  TIMx Timer Instance
00271   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
00272   * @retval An ErrorStatus enumeration value:
00273   *          - SUCCESS: TIMx registers are de-initialized
00274   *          - ERROR: not applicable
00275   */
00276 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
00277 {
00278   uint32_t tmpcr1;
00279
00280   /* Check the parameters */
00281   assert_param(IS_TIM_INSTANCE(TIMx));
00282   assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
00283   assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
00284
00285   tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
00286
00287   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
00288   {
00289     /* Select the Counter Mode */
00290     MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
00291   }
00292
00293   if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
00294   {
00295     /* Set the clock division */
00296     MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
00297   }
00298
00299   /* Write to TIMx CR1 */
00300   LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
00301
00302   /* Set the Autoreload value */
00303   LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
00304
00305   /* Set the Prescaler value */
00306   LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
00307
00308   if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
00309   {
00310     /* Set the Repetition Counter value */
00311     LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
00312   }
00313
00314   /* Generate an update event to reload the Prescaler
00315      and the repetition counter value (if applicable) immediately */
00316   LL_TIM_GenerateEvent_UPDATE(TIMx);
00317
00318   return SUCCESS;
00319 }
00320
00321 /**
00322   * @brief  Set the fields of the TIMx output channel configuration data
00323   *         structure to their default values.
00324   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
00325   * @retval None
00326   */
00327 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
00328 {
00329   /* Set the default configuration */
00330   TIM_OC_InitStruct->OCMode       = LL_TIM_OCMODE_FROZEN;
00331   TIM_OC_InitStruct->OCState      = LL_TIM_OCSTATE_DISABLE;
00332   TIM_OC_InitStruct->OCNState     = LL_TIM_OCSTATE_DISABLE;
00333   TIM_OC_InitStruct->CompareValue = 0x00000000U;
00334   TIM_OC_InitStruct->OCPolarity   = LL_TIM_OCPOLARITY_HIGH;
00335   TIM_OC_InitStruct->OCNPolarity  = LL_TIM_OCPOLARITY_HIGH;
00336   TIM_OC_InitStruct->OCIdleState  = LL_TIM_OCIDLESTATE_LOW;
00337   TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
00338 }
00339
00340 /**
00341   * @brief  Configure the TIMx output channel.
00342   * @param  TIMx Timer Instance
00343   * @param  Channel This parameter can be one of the following values:
00344   *         @arg @ref LL_TIM_CHANNEL_CH1
00345   *         @arg @ref LL_TIM_CHANNEL_CH2
00346   *         @arg @ref LL_TIM_CHANNEL_CH3
00347   *         @arg @ref LL_TIM_CHANNEL_CH4
00348   *         @arg @ref LL_TIM_CHANNEL_CH5
00349   *         @arg @ref LL_TIM_CHANNEL_CH6
00350   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
00351   * @retval An ErrorStatus enumeration value:
00352   *          - SUCCESS: TIMx output channel is initialized
00353   *          - ERROR: TIMx output channel is not initialized
00354   */
00355 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
00356 {
00357   ErrorStatus result = ERROR;
00358
00359   switch (Channel)
00360   {
00361     case LL_TIM_CHANNEL_CH1:
00362       result = OC1Config(TIMx, TIM_OC_InitStruct);
00363       break;
00364     case LL_TIM_CHANNEL_CH2:
00365       result = OC2Config(TIMx, TIM_OC_InitStruct);
00366       break;
00367     case LL_TIM_CHANNEL_CH3:
00368       result = OC3Config(TIMx, TIM_OC_InitStruct);
00369       break;
00370     case LL_TIM_CHANNEL_CH4:
00371       result = OC4Config(TIMx, TIM_OC_InitStruct);
00372       break;
00373     case LL_TIM_CHANNEL_CH5:
00374       result = OC5Config(TIMx, TIM_OC_InitStruct);
00375       break;
00376     case LL_TIM_CHANNEL_CH6:
00377       result = OC6Config(TIMx, TIM_OC_InitStruct);
00378       break;
00379     default:
00380       break;
00381   }
00382
00383   return result;
00384 }
00385
00386 /**
00387   * @brief  Set the fields of the TIMx input channel configuration data
00388   *         structure to their default values.
00389   * @param  TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
00390   * @retval None
00391   */
00392 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
00393 {
00394   /* Set the default configuration */
00395   TIM_ICInitStruct->ICPolarity    = LL_TIM_IC_POLARITY_RISING;
00396   TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
00397   TIM_ICInitStruct->ICPrescaler   = LL_TIM_ICPSC_DIV1;
00398   TIM_ICInitStruct->ICFilter      = LL_TIM_IC_FILTER_FDIV1;
00399 }
00400
00401 /**
00402   * @brief  Configure the TIMx input channel.
00403   * @param  TIMx Timer Instance
00404   * @param  Channel This parameter can be one of the following values:
00405   *         @arg @ref LL_TIM_CHANNEL_CH1
00406   *         @arg @ref LL_TIM_CHANNEL_CH2
00407   *         @arg @ref LL_TIM_CHANNEL_CH3
00408   *         @arg @ref LL_TIM_CHANNEL_CH4
00409   * @param  TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
00410   * @retval An ErrorStatus enumeration value:
00411   *          - SUCCESS: TIMx output channel is initialized
00412   *          - ERROR: TIMx output channel is not initialized
00413   */
00414 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
00415 {
00416   ErrorStatus result = ERROR;
00417
00418   switch (Channel)
00419   {
00420     case LL_TIM_CHANNEL_CH1:
00421       result = IC1Config(TIMx, TIM_IC_InitStruct);
00422       break;
00423     case LL_TIM_CHANNEL_CH2:
00424       result = IC2Config(TIMx, TIM_IC_InitStruct);
00425       break;
00426     case LL_TIM_CHANNEL_CH3:
00427       result = IC3Config(TIMx, TIM_IC_InitStruct);
00428       break;
00429     case LL_TIM_CHANNEL_CH4:
00430       result = IC4Config(TIMx, TIM_IC_InitStruct);
00431       break;
00432     default:
00433       break;
00434   }
00435
00436   return result;
00437 }
00438
00439 /**
00440   * @brief  Fills each TIM_EncoderInitStruct field with its default value
00441   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
00442   * @retval None
00443   */
00444 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
00445 {
00446   /* Set the default configuration */
00447   TIM_EncoderInitStruct->EncoderMode    = LL_TIM_ENCODERMODE_X2_TI1;
00448   TIM_EncoderInitStruct->IC1Polarity    = LL_TIM_IC_POLARITY_RISING;
00449   TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
00450   TIM_EncoderInitStruct->IC1Prescaler   = LL_TIM_ICPSC_DIV1;
00451   TIM_EncoderInitStruct->IC1Filter      = LL_TIM_IC_FILTER_FDIV1;
00452   TIM_EncoderInitStruct->IC2Polarity    = LL_TIM_IC_POLARITY_RISING;
00453   TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
00454   TIM_EncoderInitStruct->IC2Prescaler   = LL_TIM_ICPSC_DIV1;
00455   TIM_EncoderInitStruct->IC2Filter      = LL_TIM_IC_FILTER_FDIV1;
00456 }
00457
00458 /**
00459   * @brief  Configure the encoder interface of the timer instance.
00460   * @param  TIMx Timer Instance
00461   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
00462   * @retval An ErrorStatus enumeration value:
00463   *          - SUCCESS: TIMx registers are de-initialized
00464   *          - ERROR: not applicable
00465   */
00466 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
00467 {
00468   uint32_t tmpccmr1;
00469   uint32_t tmpccer;
00470
00471   /* Check the parameters */
00472   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
00473   assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
00474   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
00475   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
00476   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
00477   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
00478   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
00479   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
00480   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
00481   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
00482
00483   /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
00484   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
00485
00486   /* Get the TIMx CCMR1 register value */
00487   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
00488
00489   /* Get the TIMx CCER register value */
00490   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
00491
00492   /* Configure TI1 */
00493   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
00494   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
00495   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
00496   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
00497
00498   /* Configure TI2 */
00499   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F  | TIM_CCMR1_IC2PSC);
00500   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
00501   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
00502   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
00503
00504   /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
00505   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
00506   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
00507   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
00508   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
00509
00510   /* Set encoder mode */
00511   LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
00512
00513   /* Write to TIMx CCMR1 */
00514   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
00515
00516   /* Write to TIMx CCER */
00517   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
00518
00519   return SUCCESS;
00520 }
00521
00522 /**
00523   * @brief  Set the fields of the TIMx Hall sensor interface configuration data
00524   *         structure to their default values.
00525   * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
00526   * @retval None
00527   */
00528 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
00529 {
00530   /* Set the default configuration */
00531   TIM_HallSensorInitStruct->IC1Polarity       = LL_TIM_IC_POLARITY_RISING;
00532   TIM_HallSensorInitStruct->IC1Prescaler      = LL_TIM_ICPSC_DIV1;
00533   TIM_HallSensorInitStruct->IC1Filter         = LL_TIM_IC_FILTER_FDIV1;
00534   TIM_HallSensorInitStruct->CommutationDelay  = 0U;
00535 }
00536
00537 /**
00538   * @brief  Configure the Hall sensor interface of the timer instance.
00539   * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
00540   *       to the TI1 input channel
00541   * @note TIMx slave mode controller is configured in reset mode.
00542           Selected internal trigger is TI1F_ED.
00543   * @note Channel 1 is configured as input, IC1 is mapped on TRC.
00544   * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
00545   *       between 2 changes on the inputs. It gives information about motor speed.
00546   * @note Channel 2 is configured in output PWM 2 mode.
00547   * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
00548   * @note OC2REF is selected as trigger output on TRGO.
00549   * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
00550   *       when TIMx operates in Hall sensor interface mode.
00551   * @param  TIMx Timer Instance
00552   * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
00553   * @retval An ErrorStatus enumeration value:
00554   *          - SUCCESS: TIMx registers are de-initialized
00555   *          - ERROR: not applicable
00556   */
00557 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
00558 {
00559   uint32_t tmpcr2;
00560   uint32_t tmpccmr1;
00561   uint32_t tmpccer;
00562   uint32_t tmpsmcr;
00563
00564   /* Check the parameters */
00565   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
00566   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
00567   assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
00568   assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
00569
00570   /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
00571   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
00572
00573   /* Get the TIMx CR2 register value */
00574   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
00575
00576   /* Get the TIMx CCMR1 register value */
00577   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
00578
00579   /* Get the TIMx CCER register value */
00580   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
00581
00582   /* Get the TIMx SMCR register value */
00583   tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
00584
00585   /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
00586   tmpcr2 |= TIM_CR2_TI1S;
00587
00588   /* OC2REF signal is used as trigger output (TRGO) */
00589   tmpcr2 |= LL_TIM_TRGO_OC2REF;
00590
00591   /* Configure the slave mode controller */
00592   tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
00593   tmpsmcr |= LL_TIM_TS_TI1F_ED;
00594   tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
00595
00596   /* Configure input channel 1 */
00597   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
00598   tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
00599   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
00600   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
00601
00602   /* Configure input channel 2 */
00603   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE  | TIM_CCMR1_OC2PE  | TIM_CCMR1_OC2CE);
00604   tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
00605
00606   /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
00607   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
00608   tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
00609   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
00610
00611   /* Write to TIMx CR2 */
00612   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
00613
00614   /* Write to TIMx SMCR */
00615   LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
00616
00617   /* Write to TIMx CCMR1 */
00618   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
00619
00620   /* Write to TIMx CCER */
00621   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
00622
00623   /* Write to TIMx CCR2 */
00624   LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
00625
00626   return SUCCESS;
00627 }
00628
00629 /**
00630   * @brief  Set the fields of the Break and Dead Time configuration data structure
00631   *         to their default values.
00632   * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
00633   * @retval None
00634   */
00635 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
00636 {
00637   /* Set the default configuration */
00638   TIM_BDTRInitStruct->OSSRState       = LL_TIM_OSSR_DISABLE;
00639   TIM_BDTRInitStruct->OSSIState       = LL_TIM_OSSI_DISABLE;
00640   TIM_BDTRInitStruct->LockLevel       = LL_TIM_LOCKLEVEL_OFF;
00641   TIM_BDTRInitStruct->DeadTime        = (uint8_t)0x00;
00642   TIM_BDTRInitStruct->BreakState      = LL_TIM_BREAK_DISABLE;
00643   TIM_BDTRInitStruct->BreakPolarity   = LL_TIM_BREAK_POLARITY_LOW;
00644   TIM_BDTRInitStruct->BreakFilter     = LL_TIM_BREAK_FILTER_FDIV1;
00645   TIM_BDTRInitStruct->Break2State     = LL_TIM_BREAK2_DISABLE;
00646   TIM_BDTRInitStruct->Break2Polarity  = LL_TIM_BREAK2_POLARITY_LOW;
00647   TIM_BDTRInitStruct->Break2Filter    = LL_TIM_BREAK2_FILTER_FDIV1;
00648   TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
00649 }
00650
00651 /**
00652   * @brief  Configure the Break and Dead Time feature of the timer instance.
00653   * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
00654   *  and DTG[7:0] can be write-locked depending on the LOCK configuration, it
00655   *  can be necessary to configure all of them during the first write access to
00656   *  the TIMx_BDTR register.
00657   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
00658   *       a timer instance provides a break input.
00659   * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
00660   *       a timer instance provides a second break input.
00661   * @param  TIMx Timer Instance
00662   * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
00663   * @retval An ErrorStatus enumeration value:
00664   *          - SUCCESS: Break and Dead Time is initialized
00665   *          - ERROR: not applicable
00666   */
00667 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
00668 {
00669   uint32_t tmpbdtr = 0;
00670
00671   /* Check the parameters */
00672   assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
00673   assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
00674   assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
00675   assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
00676   assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
00677   assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
00678   assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
00679
00680   /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
00681   the OSSI State, the dead time value and the Automatic Output Enable Bit */
00682
00683   /* Set the BDTR bits */
00684   MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
00685   MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
00686   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
00687   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
00688   MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
00689   MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
00690   MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
00691   MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
00692   if (IS_TIM_ADVANCED_INSTANCE(TIMx))
00693   {
00694     assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
00695     MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
00696   }
00697
00698   if (IS_TIM_BKIN2_INSTANCE(TIMx))
00699   {
00700     assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
00701     assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
00702     assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
00703
00704     /* Set the BREAK2 input related BDTR bit-fields */
00705     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
00706     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
00707     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
00708   }
00709
00710   /* Set TIMx_BDTR */
00711   LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
00712
00713   return SUCCESS;
00714 }
00715 /**
00716   * @}
00717   */
00718
00719 /**
00720   * @}
00721   */
00722
00723 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
00724   *  @brief   Private functions
00725   * @{
00726   */
00727 /**
00728   * @brief  Configure the TIMx output channel 1.
00729   * @param  TIMx Timer Instance
00730   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
00731   * @retval An ErrorStatus enumeration value:
00732   *          - SUCCESS: TIMx registers are de-initialized
00733   *          - ERROR: not applicable
00734   */
00735 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
00736 {
00737   uint32_t tmpccmr1;
00738   uint32_t tmpccer;
00739   uint32_t tmpcr2;
00740
00741   /* Check the parameters */
00742   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
00743   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
00744   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
00745   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
00746   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
00747   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
00748
00749   /* Disable the Channel 1: Reset the CC1E Bit */
00750   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
00751
00752   /* Get the TIMx CCER register value */
00753   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
00754
00755   /* Get the TIMx CR2 register value */
00756   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
00757
00758   /* Get the TIMx CCMR1 register value */
00759   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
00760
00761   /* Reset Capture/Compare selection Bits */
00762   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
00763
00764   /* Set the Output Compare Mode */
00765   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
00766
00767   /* Set the Output Compare Polarity */
00768   MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
00769
00770   /* Set the Output State */
00771   MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
00772
00773   if (IS_TIM_BREAK_INSTANCE(TIMx))
00774   {
00775     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
00776     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
00777
00778     /* Set the complementary output Polarity */
00779     MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
00780
00781     /* Set the complementary output State */
00782     MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
00783
00784     /* Set the Output Idle state */
00785     MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
00786
00787     /* Set the complementary output Idle state */
00788     MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
00789   }
00790
00791   /* Write to TIMx CR2 */
00792   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
00793
00794   /* Write to TIMx CCMR1 */
00795   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
00796
00797   /* Set the Capture Compare Register value */
00798   LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
00799
00800   /* Write to TIMx CCER */
00801   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
00802
00803   return SUCCESS;
00804 }
00805
00806 /**
00807   * @brief  Configure the TIMx output channel 2.
00808   * @param  TIMx Timer Instance
00809   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
00810   * @retval An ErrorStatus enumeration value:
00811   *          - SUCCESS: TIMx registers are de-initialized
00812   *          - ERROR: not applicable
00813   */
00814 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
00815 {
00816   uint32_t tmpccmr1;
00817   uint32_t tmpccer;
00818   uint32_t tmpcr2;
00819
00820   /* Check the parameters */
00821   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
00822   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
00823   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
00824   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
00825   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
00826   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
00827
00828   /* Disable the Channel 2: Reset the CC2E Bit */
00829   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
00830
00831   /* Get the TIMx CCER register value */
00832   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
00833
00834   /* Get the TIMx CR2 register value */
00835   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
00836
00837   /* Get the TIMx CCMR1 register value */
00838   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
00839
00840   /* Reset Capture/Compare selection Bits */
00841   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
00842
00843   /* Select the Output Compare Mode */
00844   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
00845
00846   /* Set the Output Compare Polarity */
00847   MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
00848
00849   /* Set the Output State */
00850   MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
00851
00852   if (IS_TIM_BREAK_INSTANCE(TIMx))
00853   {
00854     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
00855     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
00856
00857     /* Set the complementary output Polarity */
00858     MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
00859
00860     /* Set the complementary output State */
00861     MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
00862
00863     /* Set the Output Idle state */
00864     MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
00865
00866     /* Set the complementary output Idle state */
00867     MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
00868   }
00869
00870   /* Write to TIMx CR2 */
00871   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
00872
00873   /* Write to TIMx CCMR1 */
00874   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
00875
00876   /* Set the Capture Compare Register value */
00877   LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
00878
00879   /* Write to TIMx CCER */
00880   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
00881
00882   return SUCCESS;
00883 }
00884
00885 /**
00886   * @brief  Configure the TIMx output channel 3.
00887   * @param  TIMx Timer Instance
00888   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
00889   * @retval An ErrorStatus enumeration value:
00890   *          - SUCCESS: TIMx registers are de-initialized
00891   *          - ERROR: not applicable
00892   */
00893 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
00894 {
00895   uint32_t tmpccmr2;
00896   uint32_t tmpccer;
00897   uint32_t tmpcr2;
00898
00899   /* Check the parameters */
00900   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
00901   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
00902   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
00903   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
00904   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
00905   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
00906
00907   /* Disable the Channel 3: Reset the CC3E Bit */
00908   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
00909
00910   /* Get the TIMx CCER register value */
00911   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
00912
00913   /* Get the TIMx CR2 register value */
00914   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
00915
00916   /* Get the TIMx CCMR2 register value */
00917   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
00918
00919   /* Reset Capture/Compare selection Bits */
00920   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
00921
00922   /* Select the Output Compare Mode */
00923   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
00924
00925   /* Set the Output Compare Polarity */
00926   MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
00927
00928   /* Set the Output State */
00929   MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
00930
00931   if (IS_TIM_BREAK_INSTANCE(TIMx))
00932   {
00933     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
00934     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
00935
00936     /* Set the complementary output Polarity */
00937     MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
00938
00939     /* Set the complementary output State */
00940     MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
00941
00942     /* Set the Output Idle state */
00943     MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
00944
00945     /* Set the complementary output Idle state */
00946     MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
00947   }
00948
00949   /* Write to TIMx CR2 */
00950   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
00951
00952   /* Write to TIMx CCMR2 */
00953   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
00954
00955   /* Set the Capture Compare Register value */
00956   LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
00957
00958   /* Write to TIMx CCER */
00959   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
00960
00961   return SUCCESS;
00962 }
00963
00964 /**
00965   * @brief  Configure the TIMx output channel 4.
00966   * @param  TIMx Timer Instance
00967   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
00968   * @retval An ErrorStatus enumeration value:
00969   *          - SUCCESS: TIMx registers are de-initialized
00970   *          - ERROR: not applicable
00971   */
00972 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
00973 {
00974   uint32_t tmpccmr2;
00975   uint32_t tmpccer;
00976   uint32_t tmpcr2;
00977
00978   /* Check the parameters */
00979   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
00980   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
00981   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
00982   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
00983   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
00984   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
00985
00986   /* Disable the Channel 4: Reset the CC4E Bit */
00987   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
00988
00989   /* Get the TIMx CCER register value */
00990   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
00991
00992   /* Get the TIMx CR2 register value */
00993   tmpcr2 =  LL_TIM_ReadReg(TIMx, CR2);
00994
00995   /* Get the TIMx CCMR2 register value */
00996   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
00997
00998   /* Reset Capture/Compare selection Bits */
00999   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
01000
01001   /* Select the Output Compare Mode */
01002   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
01003
01004   /* Set the Output Compare Polarity */
01005   MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
01006
01007   /* Set the Output State */
01008   MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
01009
01010   if (IS_TIM_BREAK_INSTANCE(TIMx))
01011   {
01012     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
01013     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
01014
01015     /* Set the Output Idle state */
01016     MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
01017   }
01018
01019   /* Write to TIMx CR2 */
01020   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
01021
01022   /* Write to TIMx CCMR2 */
01023   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
01024
01025   /* Set the Capture Compare Register value */
01026   LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
01027
01028   /* Write to TIMx CCER */
01029   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
01030
01031   return SUCCESS;
01032 }
01033
01034 /**
01035   * @brief  Configure the TIMx output channel 5.
01036   * @param  TIMx Timer Instance
01037   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
01038   * @retval An ErrorStatus enumeration value:
01039   *          - SUCCESS: TIMx registers are de-initialized
01040   *          - ERROR: not applicable
01041   */
01042 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
01043 {
01044   uint32_t tmpccmr3;
01045   uint32_t tmpccer;
01046
01047   /* Check the parameters */
01048   assert_param(IS_TIM_CC5_INSTANCE(TIMx));
01049   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
01050   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
01051   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
01052   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
01053   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
01054
01055   /* Disable the Channel 5: Reset the CC5E Bit */
01056   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
01057
01058   /* Get the TIMx CCER register value */
01059   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
01060
01061   /* Get the TIMx CCMR3 register value */
01062   tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
01063
01064   /* Select the Output Compare Mode */
01065   MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
01066
01067   /* Set the Output Compare Polarity */
01068   MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
01069
01070   /* Set the Output State */
01071   MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
01072
01073   if (IS_TIM_BREAK_INSTANCE(TIMx))
01074   {
01075     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
01076     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
01077
01078     /* Set the Output Idle state */
01079     MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
01080
01081   }
01082
01083   /* Write to TIMx CCMR3 */
01084   LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
01085
01086   /* Set the Capture Compare Register value */
01087   LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
01088
01089   /* Write to TIMx CCER */
01090   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
01091
01092   return SUCCESS;
01093 }
01094
01095 /**
01096   * @brief  Configure the TIMx output channel 6.
01097   * @param  TIMx Timer Instance
01098   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
01099   * @retval An ErrorStatus enumeration value:
01100   *          - SUCCESS: TIMx registers are de-initialized
01101   *          - ERROR: not applicable
01102   */
01103 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
01104 {
01105   uint32_t tmpccmr3;
01106   uint32_t tmpccer;
01107
01108   /* Check the parameters */
01109   assert_param(IS_TIM_CC6_INSTANCE(TIMx));
01110   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
01111   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
01112   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
01113   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
01114   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
01115
01116   /* Disable the Channel 5: Reset the CC6E Bit */
01117   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
01118
01119   /* Get the TIMx CCER register value */
01120   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
01121
01122   /* Get the TIMx CCMR3 register value */
01123   tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
01124
01125   /* Select the Output Compare Mode */
01126   MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
01127
01128   /* Set the Output Compare Polarity */
01129   MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
01130
01131   /* Set the Output State */
01132   MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
01133
01134   if (IS_TIM_BREAK_INSTANCE(TIMx))
01135   {
01136     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
01137     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
01138
01139     /* Set the Output Idle state */
01140     MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
01141   }
01142
01143   /* Write to TIMx CCMR3 */
01144   LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
01145
01146   /* Set the Capture Compare Register value */
01147   LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
01148
01149   /* Write to TIMx CCER */
01150   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
01151
01152   return SUCCESS;
01153 }
01154
01155 /**
01156   * @brief  Configure the TIMx input channel 1.
01157   * @param  TIMx Timer Instance
01158   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
01159   * @retval An ErrorStatus enumeration value:
01160   *          - SUCCESS: TIMx registers are de-initialized
01161   *          - ERROR: not applicable
01162   */
01163 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
01164 {
01165   /* Check the parameters */
01166   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
01167   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
01168   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
01169   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
01170   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
01171
01172   /* Disable the Channel 1: Reset the CC1E Bit */
01173   TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
01174
01175   /* Select the Input and set the filter and the prescaler value */
01176   MODIFY_REG(TIMx->CCMR1,
01177              (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
01178              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
01179
01180   /* Select the Polarity and set the CC1E Bit */
01181   MODIFY_REG(TIMx->CCER,
01182              (TIM_CCER_CC1P | TIM_CCER_CC1NP),
01183              (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
01184
01185   return SUCCESS;
01186 }
01187
01188 /**
01189   * @brief  Configure the TIMx input channel 2.
01190   * @param  TIMx Timer Instance
01191   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
01192   * @retval An ErrorStatus enumeration value:
01193   *          - SUCCESS: TIMx registers are de-initialized
01194   *          - ERROR: not applicable
01195   */
01196 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
01197 {
01198   /* Check the parameters */
01199   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
01200   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
01201   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
01202   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
01203   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
01204
01205   /* Disable the Channel 2: Reset the CC2E Bit */
01206   TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
01207
01208   /* Select the Input and set the filter and the prescaler value */
01209   MODIFY_REG(TIMx->CCMR1,
01210              (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
01211              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
01212
01213   /* Select the Polarity and set the CC2E Bit */
01214   MODIFY_REG(TIMx->CCER,
01215              (TIM_CCER_CC2P | TIM_CCER_CC2NP),
01216              ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
01217
01218   return SUCCESS;
01219 }
01220
01221 /**
01222   * @brief  Configure the TIMx input channel 3.
01223   * @param  TIMx Timer Instance
01224   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
01225   * @retval An ErrorStatus enumeration value:
01226   *          - SUCCESS: TIMx registers are de-initialized
01227   *          - ERROR: not applicable
01228   */
01229 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
01230 {
01231   /* Check the parameters */
01232   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
01233   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
01234   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
01235   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
01236   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
01237
01238   /* Disable the Channel 3: Reset the CC3E Bit */
01239   TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
01240
01241   /* Select the Input and set the filter and the prescaler value */
01242   MODIFY_REG(TIMx->CCMR2,
01243              (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
01244              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
01245
01246   /* Select the Polarity and set the CC3E Bit */
01247   MODIFY_REG(TIMx->CCER,
01248              (TIM_CCER_CC3P | TIM_CCER_CC3NP),
01249              ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
01250
01251   return SUCCESS;
01252 }
01253
01254 /**
01255   * @brief  Configure the TIMx input channel 4.
01256   * @param  TIMx Timer Instance
01257   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
01258   * @retval An ErrorStatus enumeration value:
01259   *          - SUCCESS: TIMx registers are de-initialized
01260   *          - ERROR: not applicable
01261   */
01262 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
01263 {
01264   /* Check the parameters */
01265   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
01266   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
01267   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
01268   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
01269   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
01270
01271   /* Disable the Channel 4: Reset the CC4E Bit */
01272   TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
01273
01274   /* Select the Input and set the filter and the prescaler value */
01275   MODIFY_REG(TIMx->CCMR2,
01276              (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
01277              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
01278
01279   /* Select the Polarity and set the CC2E Bit */
01280   MODIFY_REG(TIMx->CCER,
01281              (TIM_CCER_CC4P | TIM_CCER_CC4NP),
01282              ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
01283
01284   return SUCCESS;
01285 }
01286
01287
01288 /**
01289   * @}
01290   */
01291
01292 /**
01293   * @}
01294   */
01295
01296 #endif /* TIM1 || TIM2 || TIM16 || TIM17 */
01297
01298 /**
01299   * @}
01300   */
01301
01302 #endif /* USE_FULL_LL_DRIVER */
01303
01304 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:36 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_tim.h Source File

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stm32wbxx_ll_tim.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_tim.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of TIM LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef __STM32WBxx_LL_TIM_H
00022 #define __STM32WBxx_LL_TIM_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx.h"
00030
00031 /** @addtogroup STM32WBxx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (TIM1) || defined (TIM2) || defined (TIM16) || defined (TIM7)
00036
00037 /** @defgroup TIM_LL TIM
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
00044   * @{
00045   */
00046 static const uint8_t OFFSET_TAB_CCMRx[] =
00047 {
00048   0x00U,   /* 0: TIMx_CH1  */
00049   0x00U,   /* 1: TIMx_CH1N */
00050   0x00U,   /* 2: TIMx_CH2  */
00051   0x00U,   /* 3: TIMx_CH2N */
00052   0x04U,   /* 4: TIMx_CH3  */
00053   0x04U,   /* 5: TIMx_CH3N */
00054   0x04U,   /* 6: TIMx_CH4  */
00055   0x3CU,   /* 7: TIMx_CH5  */
00056   0x3CU    /* 8: TIMx_CH6  */
00057 };
00058
00059 static const uint8_t SHIFT_TAB_OCxx[] =
00060 {
00061   0U,            /* 0: OC1M, OC1FE, OC1PE */
00062   0U,            /* 1: - NA */
00063   8U,            /* 2: OC2M, OC2FE, OC2PE */
00064   0U,            /* 3: - NA */
00065   0U,            /* 4: OC3M, OC3FE, OC3PE */
00066   0U,            /* 5: - NA */
00067   8U,            /* 6: OC4M, OC4FE, OC4PE */
00068   0U,            /* 7: OC5M, OC5FE, OC5PE */
00069   8U             /* 8: OC6M, OC6FE, OC6PE */
00070 };
00071
00072 static const uint8_t SHIFT_TAB_ICxx[] =
00073 {
00074   0U,            /* 0: CC1S, IC1PSC, IC1F */
00075   0U,            /* 1: - NA */
00076   8U,            /* 2: CC2S, IC2PSC, IC2F */
00077   0U,            /* 3: - NA */
00078   0U,            /* 4: CC3S, IC3PSC, IC3F */
00079   0U,            /* 5: - NA */
00080   8U,            /* 6: CC4S, IC4PSC, IC4F */
00081   0U,            /* 7: - NA */
00082   0U             /* 8: - NA */
00083 };
00084
00085 static const uint8_t SHIFT_TAB_CCxP[] =
00086 {
00087   0U,            /* 0: CC1P */
00088   2U,            /* 1: CC1NP */
00089   4U,            /* 2: CC2P */
00090   6U,            /* 3: CC2NP */
00091   8U,            /* 4: CC3P */
00092   10U,           /* 5: CC3NP */
00093   12U,           /* 6: CC4P */
00094   16U,           /* 7: CC5P */
00095   20U            /* 8: CC6P */
00096 };
00097
00098 static const uint8_t SHIFT_TAB_OISx[] =
00099 {
00100   0U,            /* 0: OIS1 */
00101   1U,            /* 1: OIS1N */
00102   2U,            /* 2: OIS2 */
00103   3U,            /* 3: OIS2N */
00104   4U,            /* 4: OIS3 */
00105   5U,            /* 5: OIS3N */
00106   6U,            /* 6: OIS4 */
00107   8U,            /* 7: OIS5 */
00108   10U            /* 8: OIS6 */
00109 };
00110 /**
00111   * @}
00112   */
00113
00114 /* Private constants ---------------------------------------------------------*/
00115 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
00116   * @{
00117   */
00118
00119 /* Defines used for the bit position in the register and perform offsets */
00120 #define TIM_POSITION_BRK_SOURCE            (POSITION_VAL(Source) & 0x1FUL)
00121
00122 /* Generic bit definitions for TIMx_AF1 register */
00123 #define TIMx_AF1_BKINE     TIM1_AF1_BKINE     /*!< BRK BKIN input enable */
00124 #if defined(COMP1) && defined(COMP2)
00125 #define TIMx_AF1_BKCOMP1E  TIM1_AF1_BKCMP1E   /*!< BRK COMP1 enable */
00126 #define TIMx_AF1_BKCOMP2E  TIM1_AF1_BKCMP2E   /*!< BRK COMP2 enable */
00127 #endif /* COMP1 && COMP2 */
00128 #define TIMx_AF1_BKINP     TIM1_AF1_BKINP     /*!< BRK BKIN input polarity */
00129 #if defined(COMP1) && defined(COMP2)
00130 #define TIMx_AF1_BKCOMP1P  TIM1_AF1_BKCMP1P   /*!< BRK COMP1 input polarity */
00131 #define TIMx_AF1_BKCOMP2P  TIM1_AF1_BKCMP2P   /*!< BRK COMP2 input polarity */
00132 #endif /* COMP1 && COMP2 */
00133 #define TIMx_AF1_ETRSEL    TIM1_AF1_ETRSEL    /*!< TIMx ETR source selection */
00134
00135 /* Generic bit definitions for TIMx_AF2 register */
00136 #define TIMx_AF2_BK2INE    TIM1_AF2_BK2INE      /*!< BRK2 BKIN2 input enable */
00137 #if defined(COMP1) && defined(COMP2)
00138 #define TIMx_AF2_BK2COMP1E TIM1_AF2_BK2CMP1E    /*!< BRK2 COMP1 enable */
00139 #define TIMx_AF2_BK2COMP2E TIM1_AF2_BK2CMP2E    /*!< BRK2 COMP2 enable */
00140 #endif /* COMP1 && COMP2 */
00141 #define TIMx_AF2_BK2INP    TIM1_AF2_BK2INP      /*!< BRK2 BKIN2 input polarity */
00142 #if defined(COMP1) && defined(COMP2)
00143 #define TIMx_AF2_BK2COMP1P TIM1_AF2_BK2CMP1P    /*!< BRK2 COMP1 input polarity */
00144 #define TIMx_AF2_BK2COMP2P TIM1_AF2_BK2CMP2P    /*!< BRK2 COMP2 input polarity */
00145 #endif /* COMP1 && COMP2 */
00146
00147 /* Remap mask definitions */
00148 #define TIMx_OR_RMP_SHIFT 16U
00149 #define TIMx_OR_RMP_MASK  0x0000FFFFU
00150 #define TIM1_OR_RMP_MASK  ((TIM1_OR_ETR_ADC1_RMP | TIM1_OR_TI1_RMP) << TIMx_OR_RMP_SHIFT)
00151 #define TIM2_OR_RMP_MASK  ((TIM2_OR_TI4_RMP | TIM2_OR_ETR_RMP | TIM2_OR_ITR1_RMP) << TIMx_OR_RMP_SHIFT)
00152 #define TIM16_OR_RMP_MASK (TIM16_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
00153 #define TIM17_OR_RMP_MASK (TIM17_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
00154
00155 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
00156 #define DT_DELAY_1 ((uint8_t)0x7F)
00157 #define DT_DELAY_2 ((uint8_t)0x3F)
00158 #define DT_DELAY_3 ((uint8_t)0x1F)
00159 #define DT_DELAY_4 ((uint8_t)0x1F)
00160
00161 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
00162 #define DT_RANGE_1 ((uint8_t)0x00)
00163 #define DT_RANGE_2 ((uint8_t)0x80)
00164 #define DT_RANGE_3 ((uint8_t)0xC0)
00165 #define DT_RANGE_4 ((uint8_t)0xE0)
00166
00167 /** Legacy definitions for compatibility purpose
00168 @cond 0
00169   */
00170 /**
00171 @endcond
00172   */
00173
00174 /**
00175   * @}
00176   */
00177
00178 /* Private macros ------------------------------------------------------------*/
00179 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
00180   * @{
00181   */
00182 /** @brief  Convert channel id into channel index.
00183   * @param  __CHANNEL__ This parameter can be one of the following values:
00184   *         @arg @ref LL_TIM_CHANNEL_CH1
00185   *         @arg @ref LL_TIM_CHANNEL_CH1N
00186   *         @arg @ref LL_TIM_CHANNEL_CH2
00187   *         @arg @ref LL_TIM_CHANNEL_CH2N
00188   *         @arg @ref LL_TIM_CHANNEL_CH3
00189   *         @arg @ref LL_TIM_CHANNEL_CH3N
00190   *         @arg @ref LL_TIM_CHANNEL_CH4
00191   *         @arg @ref LL_TIM_CHANNEL_CH5
00192   *         @arg @ref LL_TIM_CHANNEL_CH6
00193   * @retval none
00194   */
00195 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
00196   (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
00197    ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
00198    ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
00199    ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
00200    ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
00201    ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
00202    ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
00203    ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
00204
00205 /** @brief  Calculate the deadtime sampling period(in ps).
00206   * @param  __TIMCLK__ timer input clock frequency (in Hz).
00207   * @param  __CKD__ This parameter can be one of the following values:
00208   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
00209   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
00210   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
00211   * @retval none
00212   */
00213 #define TIM_CALC_DTS(__TIMCLK__, __CKD__)                                                        \
00214   (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__))         : \
00215    ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
00216    ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
00217 /**
00218   * @}
00219   */
00220
00221
00222 /* Exported types ------------------------------------------------------------*/
00223 #if defined(USE_FULL_LL_DRIVER)
00224 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
00225   * @{
00226   */
00227
00228 /**
00229   * @brief  TIM Time Base configuration structure definition.
00230   */
00231 typedef struct
00232 {
00233   uint16_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
00234                                    This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
00235
00236                                    This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
00237
00238   uint32_t CounterMode;       /*!< Specifies the counter mode.
00239                                    This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
00240
00241                                    This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
00242
00243   uint32_t Autoreload;        /*!< Specifies the auto reload value to be loaded into the active
00244                                    Auto-Reload Register at the next update event.
00245                                    This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
00246                                    Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
00247
00248                                    This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
00249
00250   uint32_t ClockDivision;     /*!< Specifies the clock division.
00251                                    This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
00252
00253                                    This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
00254
00255   uint8_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
00256                                    reaches zero, an update event is generated and counting restarts
00257                                    from the RCR value (N).
00258                                    This means in PWM mode that (N+1) corresponds to:
00259                                       - the number of PWM periods in edge-aligned mode
00260                                       - the number of half PWM period in center-aligned mode
00261                                    This parameter must be a number between 0x00 and 0xFF.
00262
00263                                    This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
00264 } LL_TIM_InitTypeDef;
00265
00266 /**
00267   * @brief  TIM Output Compare configuration structure definition.
00268   */
00269 typedef struct
00270 {
00271   uint32_t OCMode;        /*!< Specifies the output mode.
00272                                This parameter can be a value of @ref TIM_LL_EC_OCMODE.
00273
00274                                This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
00275
00276   uint32_t OCState;       /*!< Specifies the TIM Output Compare state.
00277                                This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
00278
00279                                This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
00280
00281   uint32_t OCNState;      /*!< Specifies the TIM complementary Output Compare state.
00282                                This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
00283
00284                                This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
00285
00286   uint32_t CompareValue;  /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
00287                                This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
00288
00289                                This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
00290
00291   uint32_t OCPolarity;    /*!< Specifies the output polarity.
00292                                This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
00293
00294                                This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
00295
00296   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
00297                                This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
00298
00299                                This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
00300
00301
00302   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
00303                                This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
00304
00305                                This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
00306
00307   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
00308                                This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
00309
00310                                This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
00311 } LL_TIM_OC_InitTypeDef;
00312
00313 /**
00314   * @brief  TIM Input Capture configuration structure definition.
00315   */
00316
00317 typedef struct
00318 {
00319
00320   uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
00321                                This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
00322
00323                                This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
00324
00325   uint32_t ICActiveInput; /*!< Specifies the input.
00326                                This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
00327
00328                                This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
00329
00330   uint32_t ICPrescaler;   /*!< Specifies the Input Capture Prescaler.
00331                                This parameter can be a value of @ref TIM_LL_EC_ICPSC.
00332
00333                                This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
00334
00335   uint32_t ICFilter;      /*!< Specifies the input capture filter.
00336                                This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
00337
00338                                This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
00339 } LL_TIM_IC_InitTypeDef;
00340
00341
00342 /**
00343   * @brief  TIM Encoder interface configuration structure definition.
00344   */
00345 typedef struct
00346 {
00347   uint32_t EncoderMode;     /*!< Specifies the encoder resolution (x2 or x4).
00348                                  This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
00349
00350                                  This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
00351
00352   uint32_t IC1Polarity;     /*!< Specifies the active edge of TI1 input.
00353                                  This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
00354
00355                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
00356
00357   uint32_t IC1ActiveInput;  /*!< Specifies the TI1 input source
00358                                  This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
00359
00360                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
00361
00362   uint32_t IC1Prescaler;    /*!< Specifies the TI1 input prescaler value.
00363                                  This parameter can be a value of @ref TIM_LL_EC_ICPSC.
00364
00365                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
00366
00367   uint32_t IC1Filter;       /*!< Specifies the TI1 input filter.
00368                                  This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
00369
00370                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
00371
00372   uint32_t IC2Polarity;      /*!< Specifies the active edge of TI2 input.
00373                                  This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
00374
00375                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
00376
00377   uint32_t IC2ActiveInput;  /*!< Specifies the TI2 input source
00378                                  This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
00379
00380                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
00381
00382   uint32_t IC2Prescaler;    /*!< Specifies the TI2 input prescaler value.
00383                                  This parameter can be a value of @ref TIM_LL_EC_ICPSC.
00384
00385                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
00386
00387   uint32_t IC2Filter;       /*!< Specifies the TI2 input filter.
00388                                  This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
00389
00390                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
00391
00392 } LL_TIM_ENCODER_InitTypeDef;
00393
00394 /**
00395   * @brief  TIM Hall sensor interface configuration structure definition.
00396   */
00397 typedef struct
00398 {
00399
00400   uint32_t IC1Polarity;        /*!< Specifies the active edge of TI1 input.
00401                                     This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
00402
00403                                     This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
00404
00405   uint32_t IC1Prescaler;       /*!< Specifies the TI1 input prescaler value.
00406                                     Prescaler must be set to get a maximum counter period longer than the
00407                                     time interval between 2 consecutive changes on the Hall inputs.
00408                                     This parameter can be a value of @ref TIM_LL_EC_ICPSC.
00409
00410                                     This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
00411
00412   uint32_t IC1Filter;          /*!< Specifies the TI1 input filter.
00413                                     This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
00414
00415                                     This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
00416
00417   uint32_t CommutationDelay;   /*!< Specifies the compare value to be loaded into the Capture Compare Register.
00418                                     A positive pulse (TRGO event) is generated with a programmable delay every time
00419                                     a change occurs on the Hall inputs.
00420                                     This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
00421
00422                                     This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
00423 } LL_TIM_HALLSENSOR_InitTypeDef;
00424
00425 /**
00426   * @brief  BDTR (Break and Dead Time) structure definition
00427   */
00428 typedef struct
00429 {
00430   uint32_t OSSRState;            /*!< Specifies the Off-State selection used in Run mode.
00431                                       This parameter can be a value of @ref TIM_LL_EC_OSSR
00432
00433                                       This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
00434
00435                                       @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
00436
00437   uint32_t OSSIState;            /*!< Specifies the Off-State used in Idle state.
00438                                       This parameter can be a value of @ref TIM_LL_EC_OSSI
00439
00440                                       This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
00441
00442                                       @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
00443
00444   uint32_t LockLevel;            /*!< Specifies the LOCK level parameters.
00445                                       This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
00446
00447                                       @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
00448                                             has been written, their content is frozen until the next reset.*/
00449
00450   uint8_t DeadTime;              /*!< Specifies the delay time between the switching-off and the
00451                                       switching-on of the outputs.
00452                                       This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
00453
00454                                       This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
00455
00456                                       @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
00457
00458   uint16_t BreakState;           /*!< Specifies whether the TIM Break input is enabled or not.
00459                                       This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
00460
00461                                       This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
00462
00463                                       @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
00464
00465   uint32_t BreakPolarity;        /*!< Specifies the TIM Break Input pin polarity.
00466                                       This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
00467
00468                                       This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
00469
00470                                       @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
00471
00472   uint32_t BreakFilter;          /*!< Specifies the TIM Break Filter.
00473                                       This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
00474
00475                                       This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
00476
00477                                       @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
00478
00479   uint32_t Break2State;          /*!< Specifies whether the TIM Break2 input is enabled or not.
00480                                       This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
00481
00482                                       This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
00483
00484                                       @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
00485
00486   uint32_t Break2Polarity;        /*!< Specifies the TIM Break2 Input pin polarity.
00487                                       This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
00488
00489                                       This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
00490
00491                                       @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
00492
00493   uint32_t Break2Filter;          /*!< Specifies the TIM Break2 Filter.
00494                                       This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
00495
00496                                       This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
00497
00498                                       @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
00499
00500   uint32_t AutomaticOutput;      /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
00501                                       This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
00502
00503                                       This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
00504
00505                                       @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
00506 } LL_TIM_BDTR_InitTypeDef;
00507
00508 /**
00509   * @}
00510   */
00511 #endif /* USE_FULL_LL_DRIVER */
00512
00513 /* Exported constants --------------------------------------------------------*/
00514 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
00515   * @{
00516   */
00517
00518 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
00519   * @brief    Flags defines which can be used with LL_TIM_ReadReg function.
00520   * @{
00521   */
00522 #define LL_TIM_SR_UIF                          TIM_SR_UIF           /*!< Update interrupt flag */
00523 #define LL_TIM_SR_CC1IF                        TIM_SR_CC1IF         /*!< Capture/compare 1 interrupt flag */
00524 #define LL_TIM_SR_CC2IF                        TIM_SR_CC2IF         /*!< Capture/compare 2 interrupt flag */
00525 #define LL_TIM_SR_CC3IF                        TIM_SR_CC3IF         /*!< Capture/compare 3 interrupt flag */
00526 #define LL_TIM_SR_CC4IF                        TIM_SR_CC4IF         /*!< Capture/compare 4 interrupt flag */
00527 #define LL_TIM_SR_CC5IF                        TIM_SR_CC5IF         /*!< Capture/compare 5 interrupt flag */
00528 #define LL_TIM_SR_CC6IF                        TIM_SR_CC6IF         /*!< Capture/compare 6 interrupt flag */
00529 #define LL_TIM_SR_COMIF                        TIM_SR_COMIF         /*!< COM interrupt flag */
00530 #define LL_TIM_SR_TIF                          TIM_SR_TIF           /*!< Trigger interrupt flag */
00531 #define LL_TIM_SR_BIF                          TIM_SR_BIF           /*!< Break interrupt flag */
00532 #define LL_TIM_SR_B2IF                         TIM_SR_B2IF          /*!< Second break interrupt flag */
00533 #define LL_TIM_SR_CC1OF                        TIM_SR_CC1OF         /*!< Capture/Compare 1 overcapture flag */
00534 #define LL_TIM_SR_CC2OF                        TIM_SR_CC2OF         /*!< Capture/Compare 2 overcapture flag */
00535 #define LL_TIM_SR_CC3OF                        TIM_SR_CC3OF         /*!< Capture/Compare 3 overcapture flag */
00536 #define LL_TIM_SR_CC4OF                        TIM_SR_CC4OF         /*!< Capture/Compare 4 overcapture flag */
00537 #define LL_TIM_SR_SBIF                         TIM_SR_SBIF          /*!< System Break interrupt flag  */
00538 /**
00539   * @}
00540   */
00541
00542 #if defined(USE_FULL_LL_DRIVER)
00543 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
00544   * @{
00545   */
00546 #define LL_TIM_BREAK_DISABLE            0x00000000U             /*!< Break function disabled */
00547 #define LL_TIM_BREAK_ENABLE             TIM_BDTR_BKE            /*!< Break function enabled */
00548 /**
00549   * @}
00550   */
00551
00552 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
00553   * @{
00554   */
00555 #define LL_TIM_BREAK2_DISABLE            0x00000000U              /*!< Break2 function disabled */
00556 #define LL_TIM_BREAK2_ENABLE             TIM_BDTR_BK2E            /*!< Break2 function enabled */
00557 /**
00558   * @}
00559   */
00560
00561 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
00562   * @{
00563   */
00564 #define LL_TIM_AUTOMATICOUTPUT_DISABLE         0x00000000U             /*!< MOE can be set only by software */
00565 #define LL_TIM_AUTOMATICOUTPUT_ENABLE          TIM_BDTR_AOE            /*!< MOE can be set by software or automatically at the next update event */
00566 /**
00567   * @}
00568   */
00569 #endif /* USE_FULL_LL_DRIVER */
00570
00571 /** @defgroup TIM_LL_EC_IT IT Defines
00572   * @brief    IT defines which can be used with LL_TIM_ReadReg and  LL_TIM_WriteReg functions.
00573   * @{
00574   */
00575 #define LL_TIM_DIER_UIE                        TIM_DIER_UIE         /*!< Update interrupt enable */
00576 #define LL_TIM_DIER_CC1IE                      TIM_DIER_CC1IE       /*!< Capture/compare 1 interrupt enable */
00577 #define LL_TIM_DIER_CC2IE                      TIM_DIER_CC2IE       /*!< Capture/compare 2 interrupt enable */
00578 #define LL_TIM_DIER_CC3IE                      TIM_DIER_CC3IE       /*!< Capture/compare 3 interrupt enable */
00579 #define LL_TIM_DIER_CC4IE                      TIM_DIER_CC4IE       /*!< Capture/compare 4 interrupt enable */
00580 #define LL_TIM_DIER_COMIE                      TIM_DIER_COMIE       /*!< COM interrupt enable */
00581 #define LL_TIM_DIER_TIE                        TIM_DIER_TIE         /*!< Trigger interrupt enable */
00582 #define LL_TIM_DIER_BIE                        TIM_DIER_BIE         /*!< Break interrupt enable */
00583 /**
00584   * @}
00585   */
00586
00587 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
00588   * @{
00589   */
00590 #define LL_TIM_UPDATESOURCE_REGULAR            0x00000000U          /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
00591 #define LL_TIM_UPDATESOURCE_COUNTER            TIM_CR1_URS          /*!< Only counter overflow/underflow generates an update request */
00592 /**
00593   * @}
00594   */
00595
00596 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
00597   * @{
00598   */
00599 #define LL_TIM_ONEPULSEMODE_SINGLE             TIM_CR1_OPM          /*!< Counter is not stopped at update event */
00600 #define LL_TIM_ONEPULSEMODE_REPETITIVE         0x00000000U          /*!< Counter stops counting at the next update event */
00601 /**
00602   * @}
00603   */
00604
00605 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
00606   * @{
00607   */
00608 #define LL_TIM_COUNTERMODE_UP                  0x00000000U          /*!<Counter used as upcounter */
00609 #define LL_TIM_COUNTERMODE_DOWN                TIM_CR1_DIR          /*!< Counter used as downcounter */
00610 #define LL_TIM_COUNTERMODE_CENTER_UP           TIM_CR1_CMS_0        /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting down. */
00611 #define LL_TIM_COUNTERMODE_CENTER_DOWN         TIM_CR1_CMS_1        /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up */
00612 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN      TIM_CR1_CMS          /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up or down. */
00613 /**
00614   * @}
00615   */
00616
00617 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
00618   * @{
00619   */
00620 #define LL_TIM_CLOCKDIVISION_DIV1              0x00000000U          /*!< tDTS=tCK_INT */
00621 #define LL_TIM_CLOCKDIVISION_DIV2              TIM_CR1_CKD_0        /*!< tDTS=2*tCK_INT */
00622 #define LL_TIM_CLOCKDIVISION_DIV4              TIM_CR1_CKD_1        /*!< tDTS=4*tCK_INT */
00623 /**
00624   * @}
00625   */
00626
00627 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
00628   * @{
00629   */
00630 #define LL_TIM_COUNTERDIRECTION_UP             0x00000000U          /*!< Timer counter counts up */
00631 #define LL_TIM_COUNTERDIRECTION_DOWN           TIM_CR1_DIR          /*!< Timer counter counts down */
00632 /**
00633   * @}
00634   */
00635
00636 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare  Update Source
00637   * @{
00638   */
00639 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY        0x00000000U          /*!< Capture/compare control bits are updated by setting the COMG bit only */
00640 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI    TIM_CR2_CCUS         /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
00641 /**
00642   * @}
00643   */
00644
00645 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
00646   * @{
00647   */
00648 #define LL_TIM_CCDMAREQUEST_CC                 0x00000000U          /*!< CCx DMA request sent when CCx event occurs */
00649 #define LL_TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS         /*!< CCx DMA requests sent when update event occurs */
00650 /**
00651   * @}
00652   */
00653
00654 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
00655   * @{
00656   */
00657 #define LL_TIM_LOCKLEVEL_OFF                   0x00000000U          /*!< LOCK OFF - No bit is write protected */
00658 #define LL_TIM_LOCKLEVEL_1                     TIM_BDTR_LOCK_0      /*!< LOCK Level 1 */
00659 #define LL_TIM_LOCKLEVEL_2                     TIM_BDTR_LOCK_1      /*!< LOCK Level 2 */
00660 #define LL_TIM_LOCKLEVEL_3                     TIM_BDTR_LOCK        /*!< LOCK Level 3 */
00661 /**
00662   * @}
00663   */
00664
00665 /** @defgroup TIM_LL_EC_CHANNEL Channel
00666   * @{
00667   */
00668 #define LL_TIM_CHANNEL_CH1                     TIM_CCER_CC1E     /*!< Timer input/output channel 1 */
00669 #define LL_TIM_CHANNEL_CH1N                    TIM_CCER_CC1NE    /*!< Timer complementary output channel 1 */
00670 #define LL_TIM_CHANNEL_CH2                     TIM_CCER_CC2E     /*!< Timer input/output channel 2 */
00671 #define LL_TIM_CHANNEL_CH2N                    TIM_CCER_CC2NE    /*!< Timer complementary output channel 2 */
00672 #define LL_TIM_CHANNEL_CH3                     TIM_CCER_CC3E     /*!< Timer input/output channel 3 */
00673 #define LL_TIM_CHANNEL_CH3N                    TIM_CCER_CC3NE    /*!< Timer complementary output channel 3 */
00674 #define LL_TIM_CHANNEL_CH4                     TIM_CCER_CC4E     /*!< Timer input/output channel 4 */
00675 #define LL_TIM_CHANNEL_CH5                     TIM_CCER_CC5E     /*!< Timer output channel 5 */
00676 #define LL_TIM_CHANNEL_CH6                     TIM_CCER_CC6E     /*!< Timer output channel 6 */
00677 /**
00678   * @}
00679   */
00680
00681 #if defined(USE_FULL_LL_DRIVER)
00682 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
00683   * @{
00684   */
00685 #define LL_TIM_OCSTATE_DISABLE                 0x00000000U             /*!< OCx is not active */
00686 #define LL_TIM_OCSTATE_ENABLE                  TIM_CCER_CC1E           /*!< OCx signal is output on the corresponding output pin */
00687 /**
00688   * @}
00689   */
00690 #endif /* USE_FULL_LL_DRIVER */
00691
00692 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
00693   * @{
00694   */
00695 #define LL_TIM_OCMODE_FROZEN                   0x00000000U                                              /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
00696 #define LL_TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!<OCyREF is forced high on compare match*/
00697 #define LL_TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!<OCyREF is forced low on compare match*/
00698 #define LL_TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF toggles on compare match*/
00699 #define LL_TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!<OCyREF is forced low*/
00700 #define LL_TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF is forced high*/
00701 #define LL_TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive.  In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
00702 #define LL_TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active.  In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
00703 #define LL_TIM_OCMODE_RETRIG_OPM1              TIM_CCMR1_OC1M_3                                         /*!<Retrigerrable OPM mode 1*/
00704 #define LL_TIM_OCMODE_RETRIG_OPM2              (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)                    /*!<Retrigerrable OPM mode 2*/
00705 #define LL_TIM_OCMODE_COMBINED_PWM1            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)                    /*!<Combined PWM mode 1*/
00706 #define LL_TIM_OCMODE_COMBINED_PWM2            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
00707 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
00708 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)                      /*!<Asymmetric PWM mode 2*/
00709 /**
00710   * @}
00711   */
00712
00713 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
00714   * @{
00715   */
00716 #define LL_TIM_OCPOLARITY_HIGH                 0x00000000U                 /*!< OCxactive high*/
00717 #define LL_TIM_OCPOLARITY_LOW                  TIM_CCER_CC1P               /*!< OCxactive low*/
00718 /**
00719   * @}
00720   */
00721
00722 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
00723   * @{
00724   */
00725 #define LL_TIM_OCIDLESTATE_LOW                 0x00000000U             /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
00726 #define LL_TIM_OCIDLESTATE_HIGH                TIM_CR2_OIS1            /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
00727 /**
00728   * @}
00729   */
00730
00731 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
00732   * @{
00733   */
00734 #define LL_TIM_GROUPCH5_NONE                   0x00000000U           /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
00735 #define LL_TIM_GROUPCH5_OC1REFC                TIM_CCR5_GC5C1        /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
00736 #define LL_TIM_GROUPCH5_OC2REFC                TIM_CCR5_GC5C2        /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
00737 #define LL_TIM_GROUPCH5_OC3REFC                TIM_CCR5_GC5C3        /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
00738 /**
00739   * @}
00740   */
00741
00742 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
00743   * @{
00744   */
00745 #define LL_TIM_ACTIVEINPUT_DIRECTTI            (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
00746 #define LL_TIM_ACTIVEINPUT_INDIRECTTI          (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
00747 #define LL_TIM_ACTIVEINPUT_TRC                 (TIM_CCMR1_CC1S << 16U)   /*!< ICx is mapped on TRC */
00748 /**
00749   * @}
00750   */
00751
00752 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
00753   * @{
00754   */
00755 #define LL_TIM_ICPSC_DIV1                      0x00000000U                    /*!< No prescaler, capture is done each time an edge is detected on the capture input */
00756 #define LL_TIM_ICPSC_DIV2                      (TIM_CCMR1_IC1PSC_0 << 16U)    /*!< Capture is done once every 2 events */
00757 #define LL_TIM_ICPSC_DIV4                      (TIM_CCMR1_IC1PSC_1 << 16U)    /*!< Capture is done once every 4 events */
00758 #define LL_TIM_ICPSC_DIV8                      (TIM_CCMR1_IC1PSC << 16U)      /*!< Capture is done once every 8 events */
00759 /**
00760   * @}
00761   */
00762
00763 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
00764   * @{
00765   */
00766 #define LL_TIM_IC_FILTER_FDIV1                 0x00000000U                                                        /*!< No filter, sampling is done at fDTS */
00767 #define LL_TIM_IC_FILTER_FDIV1_N2              (TIM_CCMR1_IC1F_0 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=2 */
00768 #define LL_TIM_IC_FILTER_FDIV1_N4              (TIM_CCMR1_IC1F_1 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=4 */
00769 #define LL_TIM_IC_FILTER_FDIV1_N8              ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fCK_INT, N=8 */
00770 #define LL_TIM_IC_FILTER_FDIV2_N6              (TIM_CCMR1_IC1F_2 << 16U)                                          /*!< fSAMPLING=fDTS/2, N=6 */
00771 #define LL_TIM_IC_FILTER_FDIV2_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/2, N=8 */
00772 #define LL_TIM_IC_FILTER_FDIV4_N6              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/4, N=6 */
00773 #define LL_TIM_IC_FILTER_FDIV4_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/4, N=8 */
00774 #define LL_TIM_IC_FILTER_FDIV8_N6              (TIM_CCMR1_IC1F_3 << 16U)                                          /*!< fSAMPLING=fDTS/8, N=6 */
00775 #define LL_TIM_IC_FILTER_FDIV8_N8              ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/8, N=8 */
00776 #define LL_TIM_IC_FILTER_FDIV16_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/16, N=5 */
00777 #define LL_TIM_IC_FILTER_FDIV16_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/16, N=6 */
00778 #define LL_TIM_IC_FILTER_FDIV16_N8             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)                     /*!< fSAMPLING=fDTS/16, N=8 */
00779 #define LL_TIM_IC_FILTER_FDIV32_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/32, N=5 */
00780 #define LL_TIM_IC_FILTER_FDIV32_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)  /*!< fSAMPLING=fDTS/32, N=6 */
00781 #define LL_TIM_IC_FILTER_FDIV32_N8             (TIM_CCMR1_IC1F << 16U)                                            /*!< fSAMPLING=fDTS/32, N=8 */
00782 /**
00783   * @}
00784   */
00785
00786 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
00787   * @{
00788   */
00789 #define LL_TIM_IC_POLARITY_RISING              0x00000000U                      /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
00790 #define LL_TIM_IC_POLARITY_FALLING             TIM_CCER_CC1P                    /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
00791 #define LL_TIM_IC_POLARITY_BOTHEDGE            (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
00792 /**
00793   * @}
00794   */
00795
00796 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
00797   * @{
00798   */
00799 #define LL_TIM_CLOCKSOURCE_INTERNAL            0x00000000U                                          /*!< The timer is clocked by the internal clock provided from the RCC */
00800 #define LL_TIM_CLOCKSOURCE_EXT_MODE1           (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)   /*!< Counter counts at each rising or falling edge on a selected input*/
00801 #define LL_TIM_CLOCKSOURCE_EXT_MODE2           TIM_SMCR_ECE                                         /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
00802 /**
00803   * @}
00804   */
00805
00806 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
00807   * @{
00808   */
00809 #define LL_TIM_ENCODERMODE_X2_TI1                     TIM_SMCR_SMS_0                                                     /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
00810 #define LL_TIM_ENCODERMODE_X2_TI2                     TIM_SMCR_SMS_1                                                     /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
00811 #define LL_TIM_ENCODERMODE_X4_TI12                   (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
00812 /**
00813   * @}
00814   */
00815
00816 /** @defgroup TIM_LL_EC_TRGO Trigger Output
00817   * @{
00818   */
00819 #define LL_TIM_TRGO_RESET                      0x00000000U                                     /*!< UG bit from the TIMx_EGR register is used as trigger output */
00820 #define LL_TIM_TRGO_ENABLE                     TIM_CR2_MMS_0                                   /*!< Counter Enable signal (CNT_EN) is used as trigger output */
00821 #define LL_TIM_TRGO_UPDATE                     TIM_CR2_MMS_1                                   /*!< Update event is used as trigger output */
00822 #define LL_TIM_TRGO_CC1IF                      (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                 /*!< CC1 capture or a compare match is used as trigger output */
00823 #define LL_TIM_TRGO_OC1REF                     TIM_CR2_MMS_2                                   /*!< OC1REF signal is used as trigger output */
00824 #define LL_TIM_TRGO_OC2REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                 /*!< OC2REF signal is used as trigger output */
00825 #define LL_TIM_TRGO_OC3REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                 /*!< OC3REF signal is used as trigger output */
00826 #define LL_TIM_TRGO_OC4REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
00827 /**
00828   * @}
00829   */
00830
00831 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
00832   * @{
00833   */
00834 #define LL_TIM_TRGO2_RESET                     0x00000000U                                                         /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
00835 #define LL_TIM_TRGO2_ENABLE                    TIM_CR2_MMS2_0                                                      /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
00836 #define LL_TIM_TRGO2_UPDATE                    TIM_CR2_MMS2_1                                                      /*!< Update event is used as trigger output 2 */
00837 #define LL_TIM_TRGO2_CC1F                      (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                                   /*!< CC1 capture or a compare match is used as trigger output 2 */
00838 #define LL_TIM_TRGO2_OC1                       TIM_CR2_MMS2_2                                                      /*!< OC1REF signal is used as trigger output 2 */
00839 #define LL_TIM_TRGO2_OC2                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                                   /*!< OC2REF signal is used as trigger output 2 */
00840 #define LL_TIM_TRGO2_OC3                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)                                   /*!< OC3REF signal is used as trigger output 2 */
00841 #define LL_TIM_TRGO2_OC4                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC4REF signal is used as trigger output 2 */
00842 #define LL_TIM_TRGO2_OC5                       TIM_CR2_MMS2_3                                                      /*!< OC5REF signal is used as trigger output 2 */
00843 #define LL_TIM_TRGO2_OC6                       (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)                                   /*!< OC6REF signal is used as trigger output 2 */
00844 #define LL_TIM_TRGO2_OC4_RISINGFALLING         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)                                   /*!< OC4REF rising or falling edges are used as trigger output 2 */
00845 #define LL_TIM_TRGO2_OC6_RISINGFALLING         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC6REF rising or falling edges are used as trigger output 2 */
00846 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING     (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)                                   /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
00847 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                  /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
00848 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING     (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)                   /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
00849 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
00850 /**
00851   * @}
00852   */
00853
00854 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
00855   * @{
00856   */
00857 #define LL_TIM_SLAVEMODE_DISABLED              0x00000000U                         /*!< Slave mode disabled */
00858 #define LL_TIM_SLAVEMODE_RESET                 TIM_SMCR_SMS_2                      /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
00859 #define LL_TIM_SLAVEMODE_GATED                 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)   /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
00860 #define LL_TIM_SLAVEMODE_TRIGGER               (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)   /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
00861 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3                      /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI)  reinitializes the counter, generates an update of the registers and starts the counter */
00862 /**
00863   * @}
00864   */
00865
00866 /** @defgroup TIM_LL_EC_TS Trigger Selection
00867   * @{
00868   */
00869 #define LL_TIM_TS_ITR0                         0x00000000U                                                     /*!< Internal Trigger 0 (ITR0) is used as trigger input */
00870 #define LL_TIM_TS_ITR1                         TIM_SMCR_TS_0                                                   /*!< Internal Trigger 1 (ITR1) is used as trigger input */
00871 #define LL_TIM_TS_ITR2                         TIM_SMCR_TS_1                                                   /*!< Internal Trigger 2 (ITR2) is used as trigger input */
00872 #define LL_TIM_TS_ITR3                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                 /*!< Internal Trigger 3 (ITR3) is used as trigger input */
00873 #define LL_TIM_TS_TI1F_ED                      TIM_SMCR_TS_2                                                   /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
00874 #define LL_TIM_TS_TI1FP1                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)                                 /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
00875 #define LL_TIM_TS_TI2FP2                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)                                 /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
00876 #define LL_TIM_TS_ETRF                         (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)                 /*!< Filtered external Trigger (ETRF) is used as trigger input */
00877 /**
00878   * @}
00879   */
00880
00881 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
00882   * @{
00883   */
00884 #define LL_TIM_ETR_POLARITY_NONINVERTED        0x00000000U             /*!< ETR is non-inverted, active at high level or rising edge */
00885 #define LL_TIM_ETR_POLARITY_INVERTED           TIM_SMCR_ETP            /*!< ETR is inverted, active at low level or falling edge */
00886 /**
00887   * @}
00888   */
00889
00890 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
00891   * @{
00892   */
00893 #define LL_TIM_ETR_PRESCALER_DIV1              0x00000000U             /*!< ETR prescaler OFF */
00894 #define LL_TIM_ETR_PRESCALER_DIV2              TIM_SMCR_ETPS_0         /*!< ETR frequency is divided by 2 */
00895 #define LL_TIM_ETR_PRESCALER_DIV4              TIM_SMCR_ETPS_1         /*!< ETR frequency is divided by 4 */
00896 #define LL_TIM_ETR_PRESCALER_DIV8              TIM_SMCR_ETPS           /*!< ETR frequency is divided by 8 */
00897 /**
00898   * @}
00899   */
00900
00901 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
00902   * @{
00903   */
00904 #define LL_TIM_ETR_FILTER_FDIV1                0x00000000U                                          /*!< No filter, sampling is done at fDTS */
00905 #define LL_TIM_ETR_FILTER_FDIV1_N2             TIM_SMCR_ETF_0                                       /*!< fSAMPLING=fCK_INT, N=2 */
00906 #define LL_TIM_ETR_FILTER_FDIV1_N4             TIM_SMCR_ETF_1                                       /*!< fSAMPLING=fCK_INT, N=4 */
00907 #define LL_TIM_ETR_FILTER_FDIV1_N8             (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fCK_INT, N=8 */
00908 #define LL_TIM_ETR_FILTER_FDIV2_N6             TIM_SMCR_ETF_2                                       /*!< fSAMPLING=fDTS/2, N=6 */
00909 #define LL_TIM_ETR_FILTER_FDIV2_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/2, N=8 */
00910 #define LL_TIM_ETR_FILTER_FDIV4_N6             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/4, N=6 */
00911 #define LL_TIM_ETR_FILTER_FDIV4_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/4, N=8 */
00912 #define LL_TIM_ETR_FILTER_FDIV8_N6             TIM_SMCR_ETF_3                                       /*!< fSAMPLING=fDTS/8, N=8 */
00913 #define LL_TIM_ETR_FILTER_FDIV8_N8             (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/16, N=5 */
00914 #define LL_TIM_ETR_FILTER_FDIV16_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/16, N=6 */
00915 #define LL_TIM_ETR_FILTER_FDIV16_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/16, N=8 */
00916 #define LL_TIM_ETR_FILTER_FDIV16_N8            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)                    /*!< fSAMPLING=fDTS/16, N=5 */
00917 #define LL_TIM_ETR_FILTER_FDIV32_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/32, N=5 */
00918 #define LL_TIM_ETR_FILTER_FDIV32_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)   /*!< fSAMPLING=fDTS/32, N=6 */
00919 #define LL_TIM_ETR_FILTER_FDIV32_N8            TIM_SMCR_ETF                                         /*!< fSAMPLING=fDTS/32, N=8 */
00920 /**
00921   * @}
00922   */
00923
00924 /** @defgroup TIM_LL_EC_ETRSOURCE External Trigger Source
00925   * @{
00926   */
00927 #define LL_TIM_ETRSOURCE_LEGACY                0x00000000U                                       /*!< ETR legacy mode */
00928 #if defined(COMP1) && defined(COMP2)
00929 #define LL_TIM_ETRSOURCE_COMP1                 TIM1_AF1_ETRSEL_0                                 /*!< ETR input is connected to COMP1_OUT */
00930 #define LL_TIM_ETRSOURCE_COMP2                 TIM1_AF1_ETRSEL_1                                 /*!< ETR input is connected to COMP2_OUT */
00931 #endif /* COMP1 && COMP2 */
00932 #define LL_TIM_ETRSOURCE_GPIO                  LL_TIM_ETRSOURCE_LEGACY                           /*!< ETR input is connected to GPIO through TIMx ETR remapping capability */
00933 #define LL_TIM_ETRSOURCE_ADC1_AWD1             LL_TIM_ETRSOURCE_LEGACY                           /*!< ETR input is connected to ADC1 analog watchdog 1 through TIMx ETR remapping capability */
00934 #define LL_TIM_ETRSOURCE_ADC1_AWD2             LL_TIM_ETRSOURCE_LEGACY                           /*!< ETR input is connected to ADC1 analog watchdog 2 through TIMx ETR remapping capability */
00935 #define LL_TIM_ETRSOURCE_ADC1_AWD3             LL_TIM_ETRSOURCE_LEGACY                           /*!< ETR input is connected to ADC1 analog watchdog 3 through TIMx ETR remapping capability */
00936 /**
00937   * @}
00938   */
00939
00940 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
00941   * @{
00942   */
00943 #define LL_TIM_BREAK_POLARITY_LOW              0x00000000U               /*!< Break input BRK is active low */
00944 #define LL_TIM_BREAK_POLARITY_HIGH             TIM_BDTR_BKP              /*!< Break input BRK is active high */
00945 /**
00946   * @}
00947   */
00948
00949 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
00950   * @{
00951   */
00952 #define LL_TIM_BREAK_FILTER_FDIV1              0x00000000U   /*!< No filter, BRK acts asynchronously */
00953 #define LL_TIM_BREAK_FILTER_FDIV1_N2           0x00010000U   /*!< fSAMPLING=fCK_INT, N=2 */
00954 #define LL_TIM_BREAK_FILTER_FDIV1_N4           0x00020000U   /*!< fSAMPLING=fCK_INT, N=4 */
00955 #define LL_TIM_BREAK_FILTER_FDIV1_N8           0x00030000U   /*!< fSAMPLING=fCK_INT, N=8 */
00956 #define LL_TIM_BREAK_FILTER_FDIV2_N6           0x00040000U   /*!< fSAMPLING=fDTS/2, N=6 */
00957 #define LL_TIM_BREAK_FILTER_FDIV2_N8           0x00050000U   /*!< fSAMPLING=fDTS/2, N=8 */
00958 #define LL_TIM_BREAK_FILTER_FDIV4_N6           0x00060000U   /*!< fSAMPLING=fDTS/4, N=6 */
00959 #define LL_TIM_BREAK_FILTER_FDIV4_N8           0x00070000U   /*!< fSAMPLING=fDTS/4, N=8 */
00960 #define LL_TIM_BREAK_FILTER_FDIV8_N6           0x00080000U   /*!< fSAMPLING=fDTS/8, N=6 */
00961 #define LL_TIM_BREAK_FILTER_FDIV8_N8           0x00090000U   /*!< fSAMPLING=fDTS/8, N=8 */
00962 #define LL_TIM_BREAK_FILTER_FDIV16_N5          0x000A0000U   /*!< fSAMPLING=fDTS/16, N=5 */
00963 #define LL_TIM_BREAK_FILTER_FDIV16_N6          0x000B0000U   /*!< fSAMPLING=fDTS/16, N=6 */
00964 #define LL_TIM_BREAK_FILTER_FDIV16_N8          0x000C0000U   /*!< fSAMPLING=fDTS/16, N=8 */
00965 #define LL_TIM_BREAK_FILTER_FDIV32_N5          0x000D0000U   /*!< fSAMPLING=fDTS/32, N=5 */
00966 #define LL_TIM_BREAK_FILTER_FDIV32_N6          0x000E0000U   /*!< fSAMPLING=fDTS/32, N=6 */
00967 #define LL_TIM_BREAK_FILTER_FDIV32_N8          0x000F0000U   /*!< fSAMPLING=fDTS/32, N=8 */
00968 /**
00969   * @}
00970   */
00971
00972 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
00973   * @{
00974   */
00975 #define LL_TIM_BREAK2_POLARITY_LOW             0x00000000U             /*!< Break input BRK2 is active low */
00976 #define LL_TIM_BREAK2_POLARITY_HIGH            TIM_BDTR_BK2P           /*!< Break input BRK2 is active high */
00977 /**
00978   * @}
00979   */
00980
00981 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
00982   * @{
00983   */
00984 #define LL_TIM_BREAK2_FILTER_FDIV1             0x00000000U   /*!< No filter, BRK acts asynchronously */
00985 #define LL_TIM_BREAK2_FILTER_FDIV1_N2          0x00100000U   /*!< fSAMPLING=fCK_INT, N=2 */
00986 #define LL_TIM_BREAK2_FILTER_FDIV1_N4          0x00200000U   /*!< fSAMPLING=fCK_INT, N=4 */
00987 #define LL_TIM_BREAK2_FILTER_FDIV1_N8          0x00300000U   /*!< fSAMPLING=fCK_INT, N=8 */
00988 #define LL_TIM_BREAK2_FILTER_FDIV2_N6          0x00400000U   /*!< fSAMPLING=fDTS/2, N=6 */
00989 #define LL_TIM_BREAK2_FILTER_FDIV2_N8          0x00500000U   /*!< fSAMPLING=fDTS/2, N=8 */
00990 #define LL_TIM_BREAK2_FILTER_FDIV4_N6          0x00600000U   /*!< fSAMPLING=fDTS/4, N=6 */
00991 #define LL_TIM_BREAK2_FILTER_FDIV4_N8          0x00700000U   /*!< fSAMPLING=fDTS/4, N=8 */
00992 #define LL_TIM_BREAK2_FILTER_FDIV8_N6          0x00800000U   /*!< fSAMPLING=fDTS/8, N=6 */
00993 #define LL_TIM_BREAK2_FILTER_FDIV8_N8          0x00900000U   /*!< fSAMPLING=fDTS/8, N=8 */
00994 #define LL_TIM_BREAK2_FILTER_FDIV16_N5         0x00A00000U   /*!< fSAMPLING=fDTS/16, N=5 */
00995 #define LL_TIM_BREAK2_FILTER_FDIV16_N6         0x00B00000U   /*!< fSAMPLING=fDTS/16, N=6 */
00996 #define LL_TIM_BREAK2_FILTER_FDIV16_N8         0x00C00000U   /*!< fSAMPLING=fDTS/16, N=8 */
00997 #define LL_TIM_BREAK2_FILTER_FDIV32_N5         0x00D00000U   /*!< fSAMPLING=fDTS/32, N=5 */
00998 #define LL_TIM_BREAK2_FILTER_FDIV32_N6         0x00E00000U   /*!< fSAMPLING=fDTS/32, N=6 */
00999 #define LL_TIM_BREAK2_FILTER_FDIV32_N8         0x00F00000U   /*!< fSAMPLING=fDTS/32, N=8 */
01000 /**
01001   * @}
01002   */
01003
01004 /** @defgroup TIM_LL_EC_OSSI OSSI
01005   * @{
01006   */
01007 #define LL_TIM_OSSI_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
01008 #define LL_TIM_OSSI_ENABLE                     TIM_BDTR_OSSI           /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
01009 /**
01010   * @}
01011   */
01012
01013 /** @defgroup TIM_LL_EC_OSSR OSSR
01014   * @{
01015   */
01016 #define LL_TIM_OSSR_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
01017 #define LL_TIM_OSSR_ENABLE                     TIM_BDTR_OSSR           /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
01018 /**
01019   * @}
01020   */
01021
01022 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
01023   * @{
01024   */
01025 #define LL_TIM_BREAK_INPUT_BKIN                0x00000000U  /*!< TIMx_BKIN input */
01026 #define LL_TIM_BREAK_INPUT_BKIN2               0x00000004U  /*!< TIMx_BKIN2 input */
01027 /**
01028   * @}
01029   */
01030
01031 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
01032   * @{
01033   */
01034 #define LL_TIM_BKIN_SOURCE_BKIN                TIM1_AF1_BKINE      /*!< BKIN input from AF controller */
01035 #if defined(COMP1) && defined(COMP2)
01036 #define LL_TIM_BKIN_SOURCE_BKCOMP1             TIM1_AF1_BKCMP1E    /*!< internal signal: COMP1 output */
01037 #define LL_TIM_BKIN_SOURCE_BKCOMP2             TIM1_AF1_BKCMP2E    /*!< internal signal: COMP2 output */
01038 #endif /* COMP1 && COMP2 */
01039 /**
01040   * @}
01041   */
01042
01043 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
01044   * @{
01045   */
01046 #define LL_TIM_BKIN_POLARITY_LOW               TIM1_AF1_BKINP           /*!< BRK BKIN input is active low */
01047 #define LL_TIM_BKIN_POLARITY_HIGH              0x00000000U              /*!< BRK BKIN input is active high */
01048 /**
01049   * @}
01050   */
01051
01052 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
01053   * @{
01054   */
01055 #define LL_TIM_DMABURST_BASEADDR_CR1           0x00000000U                                                      /*!< TIMx_CR1 register is the DMA base address for DMA burst */
01056 #define LL_TIM_DMABURST_BASEADDR_CR2           TIM_DCR_DBA_0                                                    /*!< TIMx_CR2 register is the DMA base address for DMA burst */
01057 #define LL_TIM_DMABURST_BASEADDR_SMCR          TIM_DCR_DBA_1                                                    /*!< TIMx_SMCR register is the DMA base address for DMA burst */
01058 #define LL_TIM_DMABURST_BASEADDR_DIER          (TIM_DCR_DBA_1 |  TIM_DCR_DBA_0)                                 /*!< TIMx_DIER register is the DMA base address for DMA burst */
01059 #define LL_TIM_DMABURST_BASEADDR_SR            TIM_DCR_DBA_2                                                    /*!< TIMx_SR register is the DMA base address for DMA burst */
01060 #define LL_TIM_DMABURST_BASEADDR_EGR           (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                                  /*!< TIMx_EGR register is the DMA base address for DMA burst */
01061 #define LL_TIM_DMABURST_BASEADDR_CCMR1         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                                  /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
01062 #define LL_TIM_DMABURST_BASEADDR_CCMR2         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
01063 #define LL_TIM_DMABURST_BASEADDR_CCER          TIM_DCR_DBA_3                                                    /*!< TIMx_CCER register is the DMA base address for DMA burst */
01064 #define LL_TIM_DMABURST_BASEADDR_CNT           (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                                  /*!< TIMx_CNT register is the DMA base address for DMA burst */
01065 #define LL_TIM_DMABURST_BASEADDR_PSC           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                                  /*!< TIMx_PSC register is the DMA base address for DMA burst */
01066 #define LL_TIM_DMABURST_BASEADDR_ARR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_ARR register is the DMA base address for DMA burst */
01067 #define LL_TIM_DMABURST_BASEADDR_RCR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)                                  /*!< TIMx_RCR register is the DMA base address for DMA burst */
01068 #define LL_TIM_DMABURST_BASEADDR_CCR1          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
01069 #define LL_TIM_DMABURST_BASEADDR_CCR2          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
01070 #define LL_TIM_DMABURST_BASEADDR_CCR3          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
01071 #define LL_TIM_DMABURST_BASEADDR_CCR4          TIM_DCR_DBA_4                                                    /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
01072 #define LL_TIM_DMABURST_BASEADDR_BDTR          (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)                                  /*!< TIMx_BDTR register is the DMA base address for DMA burst */
01073 #define LL_TIM_DMABURST_BASEADDR_OR            (TIM_DCR_DBA_4 | TIM_DCR_DBA_2)                                  /*!< TIMx_OR register is the DMA base address for DMA burst */
01074 #define LL_TIM_DMABURST_BASEADDR_CCMR3         (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
01075 #define LL_TIM_DMABURST_BASEADDR_CCR5          (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
01076 #define LL_TIM_DMABURST_BASEADDR_CCR6          (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
01077 #define LL_TIM_DMABURST_BASEADDR_AF1           (TIM_DCR_DBA_4 | TIM_DCR_DBA_3)                                  /*!< TIMx_AF1 register is the DMA base address for DMA burst */
01078 #define LL_TIM_DMABURST_BASEADDR_AF2           (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                  /*!< TIMx_AF2 register is the DMA base address for DMA burst */
01079 /**
01080   * @}
01081   */
01082
01083 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
01084   * @{
01085   */
01086 #define LL_TIM_DMABURST_LENGTH_1TRANSFER       0x00000000U                                                     /*!< Transfer is done to 1 register starting from the DMA burst base address */
01087 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS      TIM_DCR_DBL_0                                                   /*!< Transfer is done to 2 registers starting from the DMA burst base address */
01088 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS      TIM_DCR_DBL_1                                                   /*!< Transfer is done to 3 registers starting from the DMA burst base address */
01089 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS      (TIM_DCR_DBL_1 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 4 registers starting from the DMA burst base address */
01090 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS      TIM_DCR_DBL_2                                                   /*!< Transfer is done to 5 registers starting from the DMA burst base address */
01091 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 6 registers starting from the DMA burst base address */
01092 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 7 registers starting from the DMA burst base address */
01093 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 1 registers starting from the DMA burst base address */
01094 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS      TIM_DCR_DBL_3                                                   /*!< Transfer is done to 9 registers starting from the DMA burst base address */
01095 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 10 registers starting from the DMA burst base address */
01096 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 11 registers starting from the DMA burst base address */
01097 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 12 registers starting from the DMA burst base address */
01098 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)                                 /*!< Transfer is done to 13 registers starting from the DMA burst base address */
01099 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 14 registers starting from the DMA burst base address */
01100 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                 /*!< Transfer is done to 15 registers starting from the DMA burst base address */
01101 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
01102 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS     TIM_DCR_DBL_4                                                   /*!< Transfer is done to 17 registers starting from the DMA burst base address */
01103 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS     (TIM_DCR_DBL_4 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 18 registers starting from the DMA burst base address */
01104 /**
01105   * @}
01106   */
01107
01108 /** @defgroup TIM_LL_EC_TIM1_ETR_ADC1_RMP  TIM1 External Trigger ADC1 Remap
01109   * @{
01110   */
01111 #define LL_TIM_TIM1_ETR_ADC1_RMP_NC    TIM1_OR_RMP_MASK                                              /*!< TIM1_ETR is not connected to ADC1 analog watchdog x */
01112 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (TIM1_OR_ETR_ADC1_RMP_0 | TIM1_OR_RMP_MASK)                    /*!< TIM1_ETR is connected to ADC1 analog watchdog 1 */
01113 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (TIM1_OR_ETR_ADC1_RMP_1 | TIM1_OR_RMP_MASK)                    /*!< TIM1_ETR is connected to ADC1 analog watchdog 2 */
01114 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (TIM1_OR_ETR_ADC1_RMP | TIM1_OR_RMP_MASK)                      /*!< TIM1_ETR is connected to ADC1 analog watchdog 3 */
01115 /**
01116   * @}
01117   */
01118
01119 /** @defgroup TIM_LL_EC_TIM1_TI1_RMP  TIM1 External Input Ch1 Remap
01120   * @{
01121   */
01122 #define LL_TIM_TIM1_TI1_RMP_GPIO  TIM1_OR_RMP_MASK                                                   /*!< TIM1 input capture 1 is connected to GPIO */
01123 #if defined(COMP1)
01124 #define LL_TIM_TIM1_TI1_RMP_COMP1 (TIM1_OR_TI1_RMP | TIM1_OR_RMP_MASK)                               /*!< TIM1 input capture 1 is connected to COMP1 output */
01125 #endif /* COMP1 */
01126 /**
01127   * @}
01128   */
01129
01130 /** @defgroup TIM_LL_EC_TIM2_ITR1_RMP  TIM2 Internal Trigger1 Remap
01131   * @{
01132   */
01133 #define LL_TIM_TIM2_ITR1_RMP_NONE          TIM2_OR_RMP_MASK                                           /* !< No internal trigger on TIM2_ITR1 */
01134 #if defined(USB)
01135 #define LL_TIM_TIM2_ITR1_RMP_USB_SOF       (TIM2_OR_ITR1_RMP)                                         /* !< TIM2_ITR1 is connected to USB SOF */
01136 #endif /* USB */
01137 /**
01138   * @}
01139   */
01140
01141 /** @defgroup TIM_LL_EC_TIM2_ETR_RMP  TIM2 External Trigger Remap
01142   * @{
01143   */
01144 #define LL_TIM_TIM2_ETR_RMP_GPIO  TIM2_OR_RMP_MASK                                                   /*!< TIM2_ETR is connected to GPIO */
01145 #define LL_TIM_TIM2_ETR_RMP_LSE  (TIM2_OR_ETR_RMP | TIM2_OR_RMP_MASK)                               /*!< TIM2_ETR is connected to LSE  */
01146 /**
01147   * @}
01148   */
01149
01150 /** @defgroup TIM_LL_EC_TIM2_TI4_RMP  TIM2 External Input Ch4 Remap
01151   * @{
01152   */
01153 #define LL_TIM_TIM2_TI4_RMP_GPIO        TIM2_OR_RMP_MASK                                             /*!< TIM2 input capture 4 is connected to GPIO */
01154 #if defined(COMP1) && defined(COMP2)
01155 #define LL_TIM_TIM2_TI4_RMP_COMP1       (TIM2_OR_TI4_RMP_0 | TIM2_OR_RMP_MASK)                       /*!< TIM2 input capture 4 is connected to COMP1_OUT */
01156 #define LL_TIM_TIM2_TI4_RMP_COMP2       (TIM2_OR_TI4_RMP_1 | TIM2_OR_RMP_MASK)                       /*!< TIM2 input capture 4 is connected to COMP2_OUT */
01157 #define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM2_OR_TI4_RMP | TIM2_OR_RMP_MASK)                         /*!< TIM2 input capture 4 is connected to logical OR between COMP1_OUT and COMP2_OUT */
01158 #endif /* COMP1 && COMP2 */
01159 /**
01160   * @}
01161   */
01162 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP  TIM16 External Input Ch1 Remap
01163   * @{
01164   */
01165 #define LL_TIM_TIM16_TI1_RMP_GPIO TIM16_OR_RMP_MASK                                                  /*!< TIM16 input capture 1 is connected to GPIO */
01166 #define LL_TIM_TIM16_TI1_RMP_LSI  (TIM16_OR_TI1_RMP_0 | TIM16_OR_RMP_MASK)                           /*!< TIM16 input capture 1 is connected to LSI */
01167 #define LL_TIM_TIM16_TI1_RMP_LSE  (TIM16_OR_TI1_RMP_1 | TIM16_OR_RMP_MASK)                           /*!< TIM16 input capture 1 is connected to LSE */
01168 #define LL_TIM_TIM16_TI1_RMP_RTC  (TIM16_OR_TI1_RMP_1 | TIM16_OR_TI1_RMP_0 | TIM16_OR_RMP_MASK)      /*!< TIM16 input capture 1 is connected to RTC wakeup interrupt */
01169 /**
01170   * @}
01171   */
01172
01173 /** @defgroup TIM_LL_EC_TIM17_TI1_RMP  TIM17 Timer Input Ch1 Remap
01174   * @{
01175   */
01176 #define LL_TIM_TIM17_TI1_RMP_GPIO   TIM17_OR_RMP_MASK                                                /*!< TIM17 input capture 1 is connected to GPIO */
01177 #define LL_TIM_TIM17_TI1_RMP_MSI    (TIM17_OR_TI1_RMP_0 | TIM17_OR_RMP_MASK)                         /*!< TIM17 input capture 1 is connected to MSI */
01178 #define LL_TIM_TIM17_TI1_RMP_HSE_32 (TIM17_OR_TI1_RMP_1 | TIM17_OR_RMP_MASK)                         /*!< TIM17 input capture 1 is connected to HSE/32 */
01179 #define LL_TIM_TIM17_TI1_RMP_MCO    (TIM17_OR_TI1_RMP | TIM17_OR_RMP_MASK)                           /*!< TIM17 input capture 1 is connected to MCO */
01180 /**
01181   * @}
01182   */
01183
01184 /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
01185   * @{
01186   */
01187 #define LL_TIM_OCREF_CLR_INT_OCREF_CLR     0x00000000U         /*!< OCREF_CLR_INT is connected to the OCREF_CLR input */
01188 #define LL_TIM_OCREF_CLR_INT_ETR    TIM_SMCR_OCCS       /*!< OCREF_CLR_INT is connected to ETRF */
01189 /**
01190   * @}
01191   */
01192
01193 /** Legacy definitions for compatibility purpose
01194 @cond 0
01195   */
01196 #define LL_TIM_BKIN_SOURCE_DFBK  LL_TIM_BKIN_SOURCE_DF1BK
01197 /**
01198 @endcond
01199   */
01200 /**
01201   * @}
01202   */
01203
01204 /* Exported macro ------------------------------------------------------------*/
01205 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
01206   * @{
01207   */
01208
01209 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
01210   * @{
01211   */
01212 /**
01213   * @brief  Write a value in TIM register.
01214   * @param  __INSTANCE__ TIM Instance
01215   * @param  __REG__ Register to be written
01216   * @param  __VALUE__ Value to be written in the register
01217   * @retval None
01218   */
01219 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
01220
01221 /**
01222   * @brief  Read a value in TIM register.
01223   * @param  __INSTANCE__ TIM Instance
01224   * @param  __REG__ Register to be read
01225   * @retval Register value
01226   */
01227 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
01228 /**
01229   * @}
01230   */
01231
01232 /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
01233   * @{
01234   */
01235
01236 /**
01237   * @brief  HELPER macro retrieving the UIFCPY flag from the counter value.
01238   * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
01239   * @note  Relevant only if UIF flag remapping has been enabled  (UIF status bit is copied
01240   *        to TIMx_CNT register bit 31)
01241   * @param  __CNT__ Counter value
01242   * @retval UIF status bit
01243   */
01244 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__)  \
01245   (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
01246
01247 /**
01248   * @brief  HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
01249   * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
01250   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01251   * @param  __CKD__ This parameter can be one of the following values:
01252   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
01253   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
01254   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
01255   * @param  __DT__ deadtime duration (in ns)
01256   * @retval DTG[0:7]
01257   */
01258 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)  \
01259   ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))    ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  & DT_DELAY_1) :                                               \
01260     (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
01261     (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
01262     (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
01263     0U)
01264
01265 /**
01266   * @brief  HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
01267   * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
01268   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01269   * @param  __CNTCLK__ counter clock frequency (in Hz)
01270   * @retval Prescaler value  (between Min_Data=0 and Max_Data=65535)
01271   */
01272 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__)   \
01273   (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
01274
01275 /**
01276   * @brief  HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
01277   * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
01278   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01279   * @param  __PSC__ prescaler
01280   * @param  __FREQ__ output signal frequency (in Hz)
01281   * @retval  Auto-reload value  (between Min_Data=0 and Max_Data=65535)
01282   */
01283 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
01284   ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
01285
01286 /**
01287   * @brief  HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
01288   * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
01289   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01290   * @param  __PSC__ prescaler
01291   * @param  __DELAY__ timer output compare active/inactive delay (in us)
01292   * @retval Compare value  (between Min_Data=0 and Max_Data=65535)
01293   */
01294 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)  \
01295   ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
01296               / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
01297
01298 /**
01299   * @brief  HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
01300   * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
01301   * @param  __TIMCLK__ timer input clock frequency (in Hz)
01302   * @param  __PSC__ prescaler
01303   * @param  __DELAY__ timer output compare active/inactive delay (in us)
01304   * @param  __PULSE__ pulse duration (in us)
01305   * @retval Auto-reload value  (between Min_Data=0 and Max_Data=65535)
01306   */
01307 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \
01308   ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
01309               + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
01310
01311 /**
01312   * @brief  HELPER macro retrieving the ratio of the input capture prescaler
01313   * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
01314   * @param  __ICPSC__ This parameter can be one of the following values:
01315   *         @arg @ref LL_TIM_ICPSC_DIV1
01316   *         @arg @ref LL_TIM_ICPSC_DIV2
01317   *         @arg @ref LL_TIM_ICPSC_DIV4
01318   *         @arg @ref LL_TIM_ICPSC_DIV8
01319   * @retval Input capture prescaler ratio (1, 2, 4 or 8)
01320   */
01321 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__)  \
01322   ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
01323
01324
01325 /**
01326   * @}
01327   */
01328
01329
01330 /**
01331   * @}
01332   */
01333
01334 /* Exported functions --------------------------------------------------------*/
01335 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
01336   * @{
01337   */
01338
01339 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
01340   * @{
01341   */
01342 /**
01343   * @brief  Enable timer counter.
01344   * @rmtoll CR1          CEN           LL_TIM_EnableCounter
01345   * @param  TIMx Timer instance
01346   * @retval None
01347   */
01348 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
01349 {
01350   SET_BIT(TIMx->CR1, TIM_CR1_CEN);
01351 }
01352
01353 /**
01354   * @brief  Disable timer counter.
01355   * @rmtoll CR1          CEN           LL_TIM_DisableCounter
01356   * @param  TIMx Timer instance
01357   * @retval None
01358   */
01359 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
01360 {
01361   CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
01362 }
01363
01364 /**
01365   * @brief  Indicates whether the timer counter is enabled.
01366   * @rmtoll CR1          CEN           LL_TIM_IsEnabledCounter
01367   * @param  TIMx Timer instance
01368   * @retval State of bit (1 or 0).
01369   */
01370 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
01371 {
01372   return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
01373 }
01374
01375 /**
01376   * @brief  Enable update event generation.
01377   * @rmtoll CR1          UDIS          LL_TIM_EnableUpdateEvent
01378   * @param  TIMx Timer instance
01379   * @retval None
01380   */
01381 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
01382 {
01383   CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
01384 }
01385
01386 /**
01387   * @brief  Disable update event generation.
01388   * @rmtoll CR1          UDIS          LL_TIM_DisableUpdateEvent
01389   * @param  TIMx Timer instance
01390   * @retval None
01391   */
01392 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
01393 {
01394   SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
01395 }
01396
01397 /**
01398   * @brief  Indicates whether update event generation is enabled.
01399   * @rmtoll CR1          UDIS          LL_TIM_IsEnabledUpdateEvent
01400   * @param  TIMx Timer instance
01401   * @retval Inverted state of bit (0 or 1).
01402   */
01403 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
01404 {
01405   return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
01406 }
01407
01408 /**
01409   * @brief  Set update event source
01410   * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
01411   *       generate an update interrupt or DMA request if enabled:
01412   *        - Counter overflow/underflow
01413   *        - Setting the UG bit
01414   *        - Update generation through the slave mode controller
01415   * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
01416   *       overflow/underflow generates an update interrupt or DMA request if enabled.
01417   * @rmtoll CR1          URS           LL_TIM_SetUpdateSource
01418   * @param  TIMx Timer instance
01419   * @param  UpdateSource This parameter can be one of the following values:
01420   *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
01421   *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
01422   * @retval None
01423   */
01424 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
01425 {
01426   MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
01427 }
01428
01429 /**
01430   * @brief  Get actual event update source
01431   * @rmtoll CR1          URS           LL_TIM_GetUpdateSource
01432   * @param  TIMx Timer instance
01433   * @retval Returned value can be one of the following values:
01434   *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
01435   *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
01436   */
01437 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
01438 {
01439   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
01440 }
01441
01442 /**
01443   * @brief  Set one pulse mode (one shot v.s. repetitive).
01444   * @rmtoll CR1          OPM           LL_TIM_SetOnePulseMode
01445   * @param  TIMx Timer instance
01446   * @param  OnePulseMode This parameter can be one of the following values:
01447   *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
01448   *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
01449   * @retval None
01450   */
01451 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
01452 {
01453   MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
01454 }
01455
01456 /**
01457   * @brief  Get actual one pulse mode.
01458   * @rmtoll CR1          OPM           LL_TIM_GetOnePulseMode
01459   * @param  TIMx Timer instance
01460   * @retval Returned value can be one of the following values:
01461   *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
01462   *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
01463   */
01464 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
01465 {
01466   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
01467 }
01468
01469 /**
01470   * @brief  Set the timer counter counting mode.
01471   * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
01472   *       check whether or not the counter mode selection feature is supported
01473   *       by a timer instance.
01474   * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
01475   *       requires a timer reset to avoid unexpected direction
01476   *       due to DIR bit readonly in center aligned mode.
01477   * @rmtoll CR1          DIR           LL_TIM_SetCounterMode\n
01478   *         CR1          CMS           LL_TIM_SetCounterMode
01479   * @param  TIMx Timer instance
01480   * @param  CounterMode This parameter can be one of the following values:
01481   *         @arg @ref LL_TIM_COUNTERMODE_UP
01482   *         @arg @ref LL_TIM_COUNTERMODE_DOWN
01483   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
01484   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
01485   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
01486   * @retval None
01487   */
01488 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
01489 {
01490   MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
01491 }
01492
01493 /**
01494   * @brief  Get actual counter mode.
01495   * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
01496   *       check whether or not the counter mode selection feature is supported
01497   *       by a timer instance.
01498   * @rmtoll CR1          DIR           LL_TIM_GetCounterMode\n
01499   *         CR1          CMS           LL_TIM_GetCounterMode
01500   * @param  TIMx Timer instance
01501   * @retval Returned value can be one of the following values:
01502   *         @arg @ref LL_TIM_COUNTERMODE_UP
01503   *         @arg @ref LL_TIM_COUNTERMODE_DOWN
01504   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
01505   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
01506   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
01507   */
01508 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
01509 {
01510   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS));
01511 }
01512
01513 /**
01514   * @brief  Enable auto-reload (ARR) preload.
01515   * @rmtoll CR1          ARPE          LL_TIM_EnableARRPreload
01516   * @param  TIMx Timer instance
01517   * @retval None
01518   */
01519 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
01520 {
01521   SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
01522 }
01523
01524 /**
01525   * @brief  Disable auto-reload (ARR) preload.
01526   * @rmtoll CR1          ARPE          LL_TIM_DisableARRPreload
01527   * @param  TIMx Timer instance
01528   * @retval None
01529   */
01530 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
01531 {
01532   CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
01533 }
01534
01535 /**
01536   * @brief  Indicates whether auto-reload (ARR) preload is enabled.
01537   * @rmtoll CR1          ARPE          LL_TIM_IsEnabledARRPreload
01538   * @param  TIMx Timer instance
01539   * @retval State of bit (1 or 0).
01540   */
01541 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
01542 {
01543   return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
01544 }
01545
01546 /**
01547   * @brief  Set the division ratio between the timer clock  and the sampling clock used by the dead-time generators (when supported) and the digital filters.
01548   * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
01549   *       whether or not the clock division feature is supported by the timer
01550   *       instance.
01551   * @rmtoll CR1          CKD           LL_TIM_SetClockDivision
01552   * @param  TIMx Timer instance
01553   * @param  ClockDivision This parameter can be one of the following values:
01554   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
01555   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
01556   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
01557   * @retval None
01558   */
01559 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
01560 {
01561   MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
01562 }
01563
01564 /**
01565   * @brief  Get the actual division ratio between the timer clock  and the sampling clock used by the dead-time generators (when supported) and the digital filters.
01566   * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
01567   *       whether or not the clock division feature is supported by the timer
01568   *       instance.
01569   * @rmtoll CR1          CKD           LL_TIM_GetClockDivision
01570   * @param  TIMx Timer instance
01571   * @retval Returned value can be one of the following values:
01572   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
01573   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
01574   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
01575   */
01576 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
01577 {
01578   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
01579 }
01580
01581 /**
01582   * @brief  Set the counter value.
01583   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
01584   *       whether or not a timer instance supports a 32 bits counter.
01585   * @rmtoll CNT          CNT           LL_TIM_SetCounter
01586   * @param  TIMx Timer instance
01587   * @param  Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
01588   * @retval None
01589   */
01590 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
01591 {
01592   WRITE_REG(TIMx->CNT, Counter);
01593 }
01594
01595 /**
01596   * @brief  Get the counter value.
01597   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
01598   *       whether or not a timer instance supports a 32 bits counter.
01599   * @rmtoll CNT          CNT           LL_TIM_GetCounter
01600   * @param  TIMx Timer instance
01601   * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
01602   */
01603 __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
01604 {
01605   return (uint32_t)(READ_REG(TIMx->CNT));
01606 }
01607
01608 /**
01609   * @brief  Get the current direction of the counter
01610   * @rmtoll CR1          DIR           LL_TIM_GetDirection
01611   * @param  TIMx Timer instance
01612   * @retval Returned value can be one of the following values:
01613   *         @arg @ref LL_TIM_COUNTERDIRECTION_UP
01614   *         @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
01615   */
01616 __STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
01617 {
01618   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
01619 }
01620
01621 /**
01622   * @brief  Set the prescaler value.
01623   * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
01624   * @note The prescaler can be changed on the fly as this control register is buffered. The new
01625   *       prescaler ratio is taken into account at the next update event.
01626   * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
01627   * @rmtoll PSC          PSC           LL_TIM_SetPrescaler
01628   * @param  TIMx Timer instance
01629   * @param  Prescaler between Min_Data=0 and Max_Data=65535
01630   * @retval None
01631   */
01632 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
01633 {
01634   WRITE_REG(TIMx->PSC, Prescaler);
01635 }
01636
01637 /**
01638   * @brief  Get the prescaler value.
01639   * @rmtoll PSC          PSC           LL_TIM_GetPrescaler
01640   * @param  TIMx Timer instance
01641   * @retval  Prescaler value between Min_Data=0 and Max_Data=65535
01642   */
01643 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
01644 {
01645   return (uint32_t)(READ_REG(TIMx->PSC));
01646 }
01647
01648 /**
01649   * @brief  Set the auto-reload value.
01650   * @note The counter is blocked while the auto-reload value is null.
01651   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
01652   *       whether or not a timer instance supports a 32 bits counter.
01653   * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
01654   * @rmtoll ARR          ARR           LL_TIM_SetAutoReload
01655   * @param  TIMx Timer instance
01656   * @param  AutoReload between Min_Data=0 and Max_Data=65535
01657   * @retval None
01658   */
01659 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
01660 {
01661   WRITE_REG(TIMx->ARR, AutoReload);
01662 }
01663
01664 /**
01665   * @brief  Get the auto-reload value.
01666   * @rmtoll ARR          ARR           LL_TIM_GetAutoReload
01667   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
01668   *       whether or not a timer instance supports a 32 bits counter.
01669   * @param  TIMx Timer instance
01670   * @retval Auto-reload value
01671   */
01672 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
01673 {
01674   return (uint32_t)(READ_REG(TIMx->ARR));
01675 }
01676
01677 /**
01678   * @brief  Set the repetition counter value.
01679   * @note For advanced timer instances RepetitionCounter can be up to 65535.
01680   * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
01681   *       whether or not a timer instance supports a repetition counter.
01682   * @rmtoll RCR          REP           LL_TIM_SetRepetitionCounter
01683   * @param  TIMx Timer instance
01684   * @param  RepetitionCounter between Min_Data=0 and Max_Data=255
01685   * @retval None
01686   */
01687 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
01688 {
01689   WRITE_REG(TIMx->RCR, RepetitionCounter);
01690 }
01691
01692 /**
01693   * @brief  Get the repetition counter value.
01694   * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
01695   *       whether or not a timer instance supports a repetition counter.
01696   * @rmtoll RCR          REP           LL_TIM_GetRepetitionCounter
01697   * @param  TIMx Timer instance
01698   * @retval Repetition counter value
01699   */
01700 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
01701 {
01702   return (uint32_t)(READ_REG(TIMx->RCR));
01703 }
01704
01705 /**
01706   * @brief  Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
01707   * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
01708   * @rmtoll CR1          UIFREMAP      LL_TIM_EnableUIFRemap
01709   * @param  TIMx Timer instance
01710   * @retval None
01711   */
01712 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
01713 {
01714   SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
01715 }
01716
01717 /**
01718   * @brief  Disable update interrupt flag (UIF) remapping.
01719   * @rmtoll CR1          UIFREMAP      LL_TIM_DisableUIFRemap
01720   * @param  TIMx Timer instance
01721   * @retval None
01722   */
01723 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
01724 {
01725   CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
01726 }
01727
01728 /**
01729   * @}
01730   */
01731
01732 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
01733   * @{
01734   */
01735 /**
01736   * @brief  Enable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
01737   * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
01738   *       they are updated only when a commutation event (COM) occurs.
01739   * @note Only on channels that have a complementary output.
01740   * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
01741   *       whether or not a timer instance is able to generate a commutation event.
01742   * @rmtoll CR2          CCPC          LL_TIM_CC_EnablePreload
01743   * @param  TIMx Timer instance
01744   * @retval None
01745   */
01746 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
01747 {
01748   SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
01749 }
01750
01751 /**
01752   * @brief  Disable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
01753   * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
01754   *       whether or not a timer instance is able to generate a commutation event.
01755   * @rmtoll CR2          CCPC          LL_TIM_CC_DisablePreload
01756   * @param  TIMx Timer instance
01757   * @retval None
01758   */
01759 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
01760 {
01761   CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
01762 }
01763
01764 /**
01765   * @brief  Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
01766   * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
01767   *       whether or not a timer instance is able to generate a commutation event.
01768   * @rmtoll CR2          CCUS          LL_TIM_CC_SetUpdate
01769   * @param  TIMx Timer instance
01770   * @param  CCUpdateSource This parameter can be one of the following values:
01771   *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
01772   *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
01773   * @retval None
01774   */
01775 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
01776 {
01777   MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
01778 }
01779
01780 /**
01781   * @brief  Set the trigger of the capture/compare DMA request.
01782   * @rmtoll CR2          CCDS          LL_TIM_CC_SetDMAReqTrigger
01783   * @param  TIMx Timer instance
01784   * @param  DMAReqTrigger This parameter can be one of the following values:
01785   *         @arg @ref LL_TIM_CCDMAREQUEST_CC
01786   *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
01787   * @retval None
01788   */
01789 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
01790 {
01791   MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
01792 }
01793
01794 /**
01795   * @brief  Get actual trigger of the capture/compare DMA request.
01796   * @rmtoll CR2          CCDS          LL_TIM_CC_GetDMAReqTrigger
01797   * @param  TIMx Timer instance
01798   * @retval Returned value can be one of the following values:
01799   *         @arg @ref LL_TIM_CCDMAREQUEST_CC
01800   *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
01801   */
01802 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
01803 {
01804   return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
01805 }
01806
01807 /**
01808   * @brief  Set the lock level to freeze the
01809   *         configuration of several capture/compare parameters.
01810   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
01811   *       the lock mechanism is supported by a timer instance.
01812   * @rmtoll BDTR         LOCK          LL_TIM_CC_SetLockLevel
01813   * @param  TIMx Timer instance
01814   * @param  LockLevel This parameter can be one of the following values:
01815   *         @arg @ref LL_TIM_LOCKLEVEL_OFF
01816   *         @arg @ref LL_TIM_LOCKLEVEL_1
01817   *         @arg @ref LL_TIM_LOCKLEVEL_2
01818   *         @arg @ref LL_TIM_LOCKLEVEL_3
01819   * @retval None
01820   */
01821 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
01822 {
01823   MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
01824 }
01825
01826 /**
01827   * @brief  Enable capture/compare channels.
01828   * @rmtoll CCER         CC1E          LL_TIM_CC_EnableChannel\n
01829   *         CCER         CC1NE         LL_TIM_CC_EnableChannel\n
01830   *         CCER         CC2E          LL_TIM_CC_EnableChannel\n
01831   *         CCER         CC2NE         LL_TIM_CC_EnableChannel\n
01832   *         CCER         CC3E          LL_TIM_CC_EnableChannel\n
01833   *         CCER         CC3NE         LL_TIM_CC_EnableChannel\n
01834   *         CCER         CC4E          LL_TIM_CC_EnableChannel\n
01835   *         CCER         CC5E          LL_TIM_CC_EnableChannel\n
01836   *         CCER         CC6E          LL_TIM_CC_EnableChannel
01837   * @param  TIMx Timer instance
01838   * @param  Channels This parameter can be a combination of the following values:
01839   *         @arg @ref LL_TIM_CHANNEL_CH1
01840   *         @arg @ref LL_TIM_CHANNEL_CH1N
01841   *         @arg @ref LL_TIM_CHANNEL_CH2
01842   *         @arg @ref LL_TIM_CHANNEL_CH2N
01843   *         @arg @ref LL_TIM_CHANNEL_CH3
01844   *         @arg @ref LL_TIM_CHANNEL_CH3N
01845   *         @arg @ref LL_TIM_CHANNEL_CH4
01846   *         @arg @ref LL_TIM_CHANNEL_CH5
01847   *         @arg @ref LL_TIM_CHANNEL_CH6
01848   * @retval None
01849   */
01850 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
01851 {
01852   SET_BIT(TIMx->CCER, Channels);
01853 }
01854
01855 /**
01856   * @brief  Disable capture/compare channels.
01857   * @rmtoll CCER         CC1E          LL_TIM_CC_DisableChannel\n
01858   *         CCER         CC1NE         LL_TIM_CC_DisableChannel\n
01859   *         CCER         CC2E          LL_TIM_CC_DisableChannel\n
01860   *         CCER         CC2NE         LL_TIM_CC_DisableChannel\n
01861   *         CCER         CC3E          LL_TIM_CC_DisableChannel\n
01862   *         CCER         CC3NE         LL_TIM_CC_DisableChannel\n
01863   *         CCER         CC4E          LL_TIM_CC_DisableChannel\n
01864   *         CCER         CC5E          LL_TIM_CC_DisableChannel\n
01865   *         CCER         CC6E          LL_TIM_CC_DisableChannel
01866   * @param  TIMx Timer instance
01867   * @param  Channels This parameter can be a combination of the following values:
01868   *         @arg @ref LL_TIM_CHANNEL_CH1
01869   *         @arg @ref LL_TIM_CHANNEL_CH1N
01870   *         @arg @ref LL_TIM_CHANNEL_CH2
01871   *         @arg @ref LL_TIM_CHANNEL_CH2N
01872   *         @arg @ref LL_TIM_CHANNEL_CH3
01873   *         @arg @ref LL_TIM_CHANNEL_CH3N
01874   *         @arg @ref LL_TIM_CHANNEL_CH4
01875   *         @arg @ref LL_TIM_CHANNEL_CH5
01876   *         @arg @ref LL_TIM_CHANNEL_CH6
01877   * @retval None
01878   */
01879 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
01880 {
01881   CLEAR_BIT(TIMx->CCER, Channels);
01882 }
01883
01884 /**
01885   * @brief  Indicate whether channel(s) is(are) enabled.
01886   * @rmtoll CCER         CC1E          LL_TIM_CC_IsEnabledChannel\n
01887   *         CCER         CC1NE         LL_TIM_CC_IsEnabledChannel\n
01888   *         CCER         CC2E          LL_TIM_CC_IsEnabledChannel\n
01889   *         CCER         CC2NE         LL_TIM_CC_IsEnabledChannel\n
01890   *         CCER         CC3E          LL_TIM_CC_IsEnabledChannel\n
01891   *         CCER         CC3NE         LL_TIM_CC_IsEnabledChannel\n
01892   *         CCER         CC4E          LL_TIM_CC_IsEnabledChannel\n
01893   *         CCER         CC5E          LL_TIM_CC_IsEnabledChannel\n
01894   *         CCER         CC6E          LL_TIM_CC_IsEnabledChannel
01895   * @param  TIMx Timer instance
01896   * @param  Channels This parameter can be a combination of the following values:
01897   *         @arg @ref LL_TIM_CHANNEL_CH1
01898   *         @arg @ref LL_TIM_CHANNEL_CH1N
01899   *         @arg @ref LL_TIM_CHANNEL_CH2
01900   *         @arg @ref LL_TIM_CHANNEL_CH2N
01901   *         @arg @ref LL_TIM_CHANNEL_CH3
01902   *         @arg @ref LL_TIM_CHANNEL_CH3N
01903   *         @arg @ref LL_TIM_CHANNEL_CH4
01904   *         @arg @ref LL_TIM_CHANNEL_CH5
01905   *         @arg @ref LL_TIM_CHANNEL_CH6
01906   * @retval State of bit (1 or 0).
01907   */
01908 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
01909 {
01910   return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
01911 }
01912
01913 /**
01914   * @}
01915   */
01916
01917 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
01918   * @{
01919   */
01920 /**
01921   * @brief  Configure an output channel.
01922   * @rmtoll CCMR1        CC1S          LL_TIM_OC_ConfigOutput\n
01923   *         CCMR1        CC2S          LL_TIM_OC_ConfigOutput\n
01924   *         CCMR2        CC3S          LL_TIM_OC_ConfigOutput\n
01925   *         CCMR2        CC4S          LL_TIM_OC_ConfigOutput\n
01926   *         CCMR3        CC5S          LL_TIM_OC_ConfigOutput\n
01927   *         CCMR3        CC6S          LL_TIM_OC_ConfigOutput\n
01928   *         CCER         CC1P          LL_TIM_OC_ConfigOutput\n
01929   *         CCER         CC2P          LL_TIM_OC_ConfigOutput\n
01930   *         CCER         CC3P          LL_TIM_OC_ConfigOutput\n
01931   *         CCER         CC4P          LL_TIM_OC_ConfigOutput\n
01932   *         CCER         CC5P          LL_TIM_OC_ConfigOutput\n
01933   *         CCER         CC6P          LL_TIM_OC_ConfigOutput\n
01934   *         CR2          OIS1          LL_TIM_OC_ConfigOutput\n
01935   *         CR2          OIS2          LL_TIM_OC_ConfigOutput\n
01936   *         CR2          OIS3          LL_TIM_OC_ConfigOutput\n
01937   *         CR2          OIS4          LL_TIM_OC_ConfigOutput\n
01938   *         CR2          OIS5          LL_TIM_OC_ConfigOutput\n
01939   *         CR2          OIS6          LL_TIM_OC_ConfigOutput
01940   * @param  TIMx Timer instance
01941   * @param  Channel This parameter can be one of the following values:
01942   *         @arg @ref LL_TIM_CHANNEL_CH1
01943   *         @arg @ref LL_TIM_CHANNEL_CH2
01944   *         @arg @ref LL_TIM_CHANNEL_CH3
01945   *         @arg @ref LL_TIM_CHANNEL_CH4
01946   *         @arg @ref LL_TIM_CHANNEL_CH5
01947   *         @arg @ref LL_TIM_CHANNEL_CH6
01948   * @param  Configuration This parameter must be a combination of all the following values:
01949   *         @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
01950   *         @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
01951   * @retval None
01952   */
01953 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
01954 {
01955   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
01956   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
01957   CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
01958   MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
01959              (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
01960   MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
01961              (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
01962 }
01963
01964 /**
01965   * @brief  Define the behavior of the output reference signal OCxREF from which
01966   *         OCx and OCxN (when relevant) are derived.
01967   * @rmtoll CCMR1        OC1M          LL_TIM_OC_SetMode\n
01968   *         CCMR1        OC2M          LL_TIM_OC_SetMode\n
01969   *         CCMR2        OC3M          LL_TIM_OC_SetMode\n
01970   *         CCMR2        OC4M          LL_TIM_OC_SetMode\n
01971   *         CCMR3        OC5M          LL_TIM_OC_SetMode\n
01972   *         CCMR3        OC6M          LL_TIM_OC_SetMode
01973   * @param  TIMx Timer instance
01974   * @param  Channel This parameter can be one of the following values:
01975   *         @arg @ref LL_TIM_CHANNEL_CH1
01976   *         @arg @ref LL_TIM_CHANNEL_CH2
01977   *         @arg @ref LL_TIM_CHANNEL_CH3
01978   *         @arg @ref LL_TIM_CHANNEL_CH4
01979   *         @arg @ref LL_TIM_CHANNEL_CH5
01980   *         @arg @ref LL_TIM_CHANNEL_CH6
01981   * @param  Mode This parameter can be one of the following values:
01982   *         @arg @ref LL_TIM_OCMODE_FROZEN
01983   *         @arg @ref LL_TIM_OCMODE_ACTIVE
01984   *         @arg @ref LL_TIM_OCMODE_INACTIVE
01985   *         @arg @ref LL_TIM_OCMODE_TOGGLE
01986   *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
01987   *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
01988   *         @arg @ref LL_TIM_OCMODE_PWM1
01989   *         @arg @ref LL_TIM_OCMODE_PWM2
01990   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
01991   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
01992   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
01993   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
01994   *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
01995   *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
01996   * @retval None
01997   */
01998 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
01999 {
02000   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02001   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02002   MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]),  Mode << SHIFT_TAB_OCxx[iChannel]);
02003 }
02004
02005 /**
02006   * @brief  Get the output compare mode of an output channel.
02007   * @rmtoll CCMR1        OC1M          LL_TIM_OC_GetMode\n
02008   *         CCMR1        OC2M          LL_TIM_OC_GetMode\n
02009   *         CCMR2        OC3M          LL_TIM_OC_GetMode\n
02010   *         CCMR2        OC4M          LL_TIM_OC_GetMode\n
02011   *         CCMR3        OC5M          LL_TIM_OC_GetMode\n
02012   *         CCMR3        OC6M          LL_TIM_OC_GetMode
02013   * @param  TIMx Timer instance
02014   * @param  Channel This parameter can be one of the following values:
02015   *         @arg @ref LL_TIM_CHANNEL_CH1
02016   *         @arg @ref LL_TIM_CHANNEL_CH2
02017   *         @arg @ref LL_TIM_CHANNEL_CH3
02018   *         @arg @ref LL_TIM_CHANNEL_CH4
02019   *         @arg @ref LL_TIM_CHANNEL_CH5
02020   *         @arg @ref LL_TIM_CHANNEL_CH6
02021   * @retval Returned value can be one of the following values:
02022   *         @arg @ref LL_TIM_OCMODE_FROZEN
02023   *         @arg @ref LL_TIM_OCMODE_ACTIVE
02024   *         @arg @ref LL_TIM_OCMODE_INACTIVE
02025   *         @arg @ref LL_TIM_OCMODE_TOGGLE
02026   *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
02027   *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
02028   *         @arg @ref LL_TIM_OCMODE_PWM1
02029   *         @arg @ref LL_TIM_OCMODE_PWM2
02030   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
02031   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
02032   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
02033   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
02034   *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
02035   *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
02036   */
02037 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
02038 {
02039   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02040   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02041   return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
02042 }
02043
02044 /**
02045   * @brief  Set the polarity of an output channel.
02046   * @rmtoll CCER         CC1P          LL_TIM_OC_SetPolarity\n
02047   *         CCER         CC1NP         LL_TIM_OC_SetPolarity\n
02048   *         CCER         CC2P          LL_TIM_OC_SetPolarity\n
02049   *         CCER         CC2NP         LL_TIM_OC_SetPolarity\n
02050   *         CCER         CC3P          LL_TIM_OC_SetPolarity\n
02051   *         CCER         CC3NP         LL_TIM_OC_SetPolarity\n
02052   *         CCER         CC4P          LL_TIM_OC_SetPolarity\n
02053   *         CCER         CC5P          LL_TIM_OC_SetPolarity\n
02054   *         CCER         CC6P          LL_TIM_OC_SetPolarity
02055   * @param  TIMx Timer instance
02056   * @param  Channel This parameter can be one of the following values:
02057   *         @arg @ref LL_TIM_CHANNEL_CH1
02058   *         @arg @ref LL_TIM_CHANNEL_CH1N
02059   *         @arg @ref LL_TIM_CHANNEL_CH2
02060   *         @arg @ref LL_TIM_CHANNEL_CH2N
02061   *         @arg @ref LL_TIM_CHANNEL_CH3
02062   *         @arg @ref LL_TIM_CHANNEL_CH3N
02063   *         @arg @ref LL_TIM_CHANNEL_CH4
02064   *         @arg @ref LL_TIM_CHANNEL_CH5
02065   *         @arg @ref LL_TIM_CHANNEL_CH6
02066   * @param  Polarity This parameter can be one of the following values:
02067   *         @arg @ref LL_TIM_OCPOLARITY_HIGH
02068   *         @arg @ref LL_TIM_OCPOLARITY_LOW
02069   * @retval None
02070   */
02071 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
02072 {
02073   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02074   MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),  Polarity << SHIFT_TAB_CCxP[iChannel]);
02075 }
02076
02077 /**
02078   * @brief  Get the polarity of an output channel.
02079   * @rmtoll CCER         CC1P          LL_TIM_OC_GetPolarity\n
02080   *         CCER         CC1NP         LL_TIM_OC_GetPolarity\n
02081   *         CCER         CC2P          LL_TIM_OC_GetPolarity\n
02082   *         CCER         CC2NP         LL_TIM_OC_GetPolarity\n
02083   *         CCER         CC3P          LL_TIM_OC_GetPolarity\n
02084   *         CCER         CC3NP         LL_TIM_OC_GetPolarity\n
02085   *         CCER         CC4P          LL_TIM_OC_GetPolarity\n
02086   *         CCER         CC5P          LL_TIM_OC_GetPolarity\n
02087   *         CCER         CC6P          LL_TIM_OC_GetPolarity
02088   * @param  TIMx Timer instance
02089   * @param  Channel This parameter can be one of the following values:
02090   *         @arg @ref LL_TIM_CHANNEL_CH1
02091   *         @arg @ref LL_TIM_CHANNEL_CH1N
02092   *         @arg @ref LL_TIM_CHANNEL_CH2
02093   *         @arg @ref LL_TIM_CHANNEL_CH2N
02094   *         @arg @ref LL_TIM_CHANNEL_CH3
02095   *         @arg @ref LL_TIM_CHANNEL_CH3N
02096   *         @arg @ref LL_TIM_CHANNEL_CH4
02097   *         @arg @ref LL_TIM_CHANNEL_CH5
02098   *         @arg @ref LL_TIM_CHANNEL_CH6
02099   * @retval Returned value can be one of the following values:
02100   *         @arg @ref LL_TIM_OCPOLARITY_HIGH
02101   *         @arg @ref LL_TIM_OCPOLARITY_LOW
02102   */
02103 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
02104 {
02105   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02106   return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
02107 }
02108
02109 /**
02110   * @brief  Set the IDLE state of an output channel
02111   * @note This function is significant only for the timer instances
02112   *       supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
02113   *       can be used to check whether or not a timer instance provides
02114   *       a break input.
02115   * @rmtoll CR2         OIS1          LL_TIM_OC_SetIdleState\n
02116   *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
02117   *         CR2         OIS2          LL_TIM_OC_SetIdleState\n
02118   *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
02119   *         CR2         OIS3          LL_TIM_OC_SetIdleState\n
02120   *         CR2         OIS3N         LL_TIM_OC_SetIdleState\n
02121   *         CR2         OIS4          LL_TIM_OC_SetIdleState\n
02122   *         CR2         OIS5          LL_TIM_OC_SetIdleState\n
02123   *         CR2         OIS6          LL_TIM_OC_SetIdleState
02124   * @param  TIMx Timer instance
02125   * @param  Channel This parameter can be one of the following values:
02126   *         @arg @ref LL_TIM_CHANNEL_CH1
02127   *         @arg @ref LL_TIM_CHANNEL_CH1N
02128   *         @arg @ref LL_TIM_CHANNEL_CH2
02129   *         @arg @ref LL_TIM_CHANNEL_CH2N
02130   *         @arg @ref LL_TIM_CHANNEL_CH3
02131   *         @arg @ref LL_TIM_CHANNEL_CH3N
02132   *         @arg @ref LL_TIM_CHANNEL_CH4
02133   *         @arg @ref LL_TIM_CHANNEL_CH5
02134   *         @arg @ref LL_TIM_CHANNEL_CH6
02135   * @param  IdleState This parameter can be one of the following values:
02136   *         @arg @ref LL_TIM_OCIDLESTATE_LOW
02137   *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
02138   * @retval None
02139   */
02140 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
02141 {
02142   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02143   MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),  IdleState << SHIFT_TAB_OISx[iChannel]);
02144 }
02145
02146 /**
02147   * @brief  Get the IDLE state of an output channel
02148   * @rmtoll CR2         OIS1          LL_TIM_OC_GetIdleState\n
02149   *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
02150   *         CR2         OIS2          LL_TIM_OC_GetIdleState\n
02151   *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
02152   *         CR2         OIS3          LL_TIM_OC_GetIdleState\n
02153   *         CR2         OIS3N         LL_TIM_OC_GetIdleState\n
02154   *         CR2         OIS4          LL_TIM_OC_GetIdleState\n
02155   *         CR2         OIS5          LL_TIM_OC_GetIdleState\n
02156   *         CR2         OIS6          LL_TIM_OC_GetIdleState
02157   * @param  TIMx Timer instance
02158   * @param  Channel This parameter can be one of the following values:
02159   *         @arg @ref LL_TIM_CHANNEL_CH1
02160   *         @arg @ref LL_TIM_CHANNEL_CH1N
02161   *         @arg @ref LL_TIM_CHANNEL_CH2
02162   *         @arg @ref LL_TIM_CHANNEL_CH2N
02163   *         @arg @ref LL_TIM_CHANNEL_CH3
02164   *         @arg @ref LL_TIM_CHANNEL_CH3N
02165   *         @arg @ref LL_TIM_CHANNEL_CH4
02166   *         @arg @ref LL_TIM_CHANNEL_CH5
02167   *         @arg @ref LL_TIM_CHANNEL_CH6
02168   * @retval Returned value can be one of the following values:
02169   *         @arg @ref LL_TIM_OCIDLESTATE_LOW
02170   *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
02171   */
02172 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
02173 {
02174   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02175   return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
02176 }
02177
02178 /**
02179   * @brief  Enable fast mode for the output channel.
02180   * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
02181   * @rmtoll CCMR1        OC1FE          LL_TIM_OC_EnableFast\n
02182   *         CCMR1        OC2FE          LL_TIM_OC_EnableFast\n
02183   *         CCMR2        OC3FE          LL_TIM_OC_EnableFast\n
02184   *         CCMR2        OC4FE          LL_TIM_OC_EnableFast\n
02185   *         CCMR3        OC5FE          LL_TIM_OC_EnableFast\n
02186   *         CCMR3        OC6FE          LL_TIM_OC_EnableFast
02187   * @param  TIMx Timer instance
02188   * @param  Channel This parameter can be one of the following values:
02189   *         @arg @ref LL_TIM_CHANNEL_CH1
02190   *         @arg @ref LL_TIM_CHANNEL_CH2
02191   *         @arg @ref LL_TIM_CHANNEL_CH3
02192   *         @arg @ref LL_TIM_CHANNEL_CH4
02193   *         @arg @ref LL_TIM_CHANNEL_CH5
02194   *         @arg @ref LL_TIM_CHANNEL_CH6
02195   * @retval None
02196   */
02197 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
02198 {
02199   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02200   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02201   SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
02202
02203 }
02204
02205 /**
02206   * @brief  Disable fast mode for the output channel.
02207   * @rmtoll CCMR1        OC1FE          LL_TIM_OC_DisableFast\n
02208   *         CCMR1        OC2FE          LL_TIM_OC_DisableFast\n
02209   *         CCMR2        OC3FE          LL_TIM_OC_DisableFast\n
02210   *         CCMR2        OC4FE          LL_TIM_OC_DisableFast\n
02211   *         CCMR3        OC5FE          LL_TIM_OC_DisableFast\n
02212   *         CCMR3        OC6FE          LL_TIM_OC_DisableFast
02213   * @param  TIMx Timer instance
02214   * @param  Channel This parameter can be one of the following values:
02215   *         @arg @ref LL_TIM_CHANNEL_CH1
02216   *         @arg @ref LL_TIM_CHANNEL_CH2
02217   *         @arg @ref LL_TIM_CHANNEL_CH3
02218   *         @arg @ref LL_TIM_CHANNEL_CH4
02219   *         @arg @ref LL_TIM_CHANNEL_CH5
02220   *         @arg @ref LL_TIM_CHANNEL_CH6
02221   * @retval None
02222   */
02223 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
02224 {
02225   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02226   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02227   CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
02228
02229 }
02230
02231 /**
02232   * @brief  Indicates whether fast mode is enabled for the output channel.
02233   * @rmtoll CCMR1        OC1FE          LL_TIM_OC_IsEnabledFast\n
02234   *         CCMR1        OC2FE          LL_TIM_OC_IsEnabledFast\n
02235   *         CCMR2        OC3FE          LL_TIM_OC_IsEnabledFast\n
02236   *         CCMR2        OC4FE          LL_TIM_OC_IsEnabledFast\n
02237   *         CCMR3        OC5FE          LL_TIM_OC_IsEnabledFast\n
02238   *         CCMR3        OC6FE          LL_TIM_OC_IsEnabledFast
02239   * @param  TIMx Timer instance
02240   * @param  Channel This parameter can be one of the following values:
02241   *         @arg @ref LL_TIM_CHANNEL_CH1
02242   *         @arg @ref LL_TIM_CHANNEL_CH2
02243   *         @arg @ref LL_TIM_CHANNEL_CH3
02244   *         @arg @ref LL_TIM_CHANNEL_CH4
02245   *         @arg @ref LL_TIM_CHANNEL_CH5
02246   *         @arg @ref LL_TIM_CHANNEL_CH6
02247   * @retval State of bit (1 or 0).
02248   */
02249 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
02250 {
02251   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02252   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02253   register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
02254   return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
02255 }
02256
02257 /**
02258   * @brief  Enable compare register (TIMx_CCRx) preload for the output channel.
02259   * @rmtoll CCMR1        OC1PE          LL_TIM_OC_EnablePreload\n
02260   *         CCMR1        OC2PE          LL_TIM_OC_EnablePreload\n
02261   *         CCMR2        OC3PE          LL_TIM_OC_EnablePreload\n
02262   *         CCMR2        OC4PE          LL_TIM_OC_EnablePreload\n
02263   *         CCMR3        OC5PE          LL_TIM_OC_EnablePreload\n
02264   *         CCMR3        OC6PE          LL_TIM_OC_EnablePreload
02265   * @param  TIMx Timer instance
02266   * @param  Channel This parameter can be one of the following values:
02267   *         @arg @ref LL_TIM_CHANNEL_CH1
02268   *         @arg @ref LL_TIM_CHANNEL_CH2
02269   *         @arg @ref LL_TIM_CHANNEL_CH3
02270   *         @arg @ref LL_TIM_CHANNEL_CH4
02271   *         @arg @ref LL_TIM_CHANNEL_CH5
02272   *         @arg @ref LL_TIM_CHANNEL_CH6
02273   * @retval None
02274   */
02275 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
02276 {
02277   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02278   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02279   SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
02280 }
02281
02282 /**
02283   * @brief  Disable compare register (TIMx_CCRx) preload for the output channel.
02284   * @rmtoll CCMR1        OC1PE          LL_TIM_OC_DisablePreload\n
02285   *         CCMR1        OC2PE          LL_TIM_OC_DisablePreload\n
02286   *         CCMR2        OC3PE          LL_TIM_OC_DisablePreload\n
02287   *         CCMR2        OC4PE          LL_TIM_OC_DisablePreload\n
02288   *         CCMR3        OC5PE          LL_TIM_OC_DisablePreload\n
02289   *         CCMR3        OC6PE          LL_TIM_OC_DisablePreload
02290   * @param  TIMx Timer instance
02291   * @param  Channel This parameter can be one of the following values:
02292   *         @arg @ref LL_TIM_CHANNEL_CH1
02293   *         @arg @ref LL_TIM_CHANNEL_CH2
02294   *         @arg @ref LL_TIM_CHANNEL_CH3
02295   *         @arg @ref LL_TIM_CHANNEL_CH4
02296   *         @arg @ref LL_TIM_CHANNEL_CH5
02297   *         @arg @ref LL_TIM_CHANNEL_CH6
02298   * @retval None
02299   */
02300 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
02301 {
02302   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02303   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02304   CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
02305 }
02306
02307 /**
02308   * @brief  Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
02309   * @rmtoll CCMR1        OC1PE          LL_TIM_OC_IsEnabledPreload\n
02310   *         CCMR1        OC2PE          LL_TIM_OC_IsEnabledPreload\n
02311   *         CCMR2        OC3PE          LL_TIM_OC_IsEnabledPreload\n
02312   *         CCMR2        OC4PE          LL_TIM_OC_IsEnabledPreload\n
02313   *         CCMR3        OC5PE          LL_TIM_OC_IsEnabledPreload\n
02314   *         CCMR3        OC6PE          LL_TIM_OC_IsEnabledPreload
02315   * @param  TIMx Timer instance
02316   * @param  Channel This parameter can be one of the following values:
02317   *         @arg @ref LL_TIM_CHANNEL_CH1
02318   *         @arg @ref LL_TIM_CHANNEL_CH2
02319   *         @arg @ref LL_TIM_CHANNEL_CH3
02320   *         @arg @ref LL_TIM_CHANNEL_CH4
02321   *         @arg @ref LL_TIM_CHANNEL_CH5
02322   *         @arg @ref LL_TIM_CHANNEL_CH6
02323   * @retval State of bit (1 or 0).
02324   */
02325 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
02326 {
02327   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02328   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02329   register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
02330   return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
02331 }
02332
02333 /**
02334   * @brief  Enable clearing the output channel on an external event.
02335   * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
02336   * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
02337   *       or not a timer instance can clear the OCxREF signal on an external event.
02338   * @rmtoll CCMR1        OC1CE          LL_TIM_OC_EnableClear\n
02339   *         CCMR1        OC2CE          LL_TIM_OC_EnableClear\n
02340   *         CCMR2        OC3CE          LL_TIM_OC_EnableClear\n
02341   *         CCMR2        OC4CE          LL_TIM_OC_EnableClear\n
02342   *         CCMR3        OC5CE          LL_TIM_OC_EnableClear\n
02343   *         CCMR3        OC6CE          LL_TIM_OC_EnableClear
02344   * @param  TIMx Timer instance
02345   * @param  Channel This parameter can be one of the following values:
02346   *         @arg @ref LL_TIM_CHANNEL_CH1
02347   *         @arg @ref LL_TIM_CHANNEL_CH2
02348   *         @arg @ref LL_TIM_CHANNEL_CH3
02349   *         @arg @ref LL_TIM_CHANNEL_CH4
02350   *         @arg @ref LL_TIM_CHANNEL_CH5
02351   *         @arg @ref LL_TIM_CHANNEL_CH6
02352   * @retval None
02353   */
02354 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
02355 {
02356   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02357   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02358   SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
02359 }
02360
02361 /**
02362   * @brief  Disable clearing the output channel on an external event.
02363   * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
02364   *       or not a timer instance can clear the OCxREF signal on an external event.
02365   * @rmtoll CCMR1        OC1CE          LL_TIM_OC_DisableClear\n
02366   *         CCMR1        OC2CE          LL_TIM_OC_DisableClear\n
02367   *         CCMR2        OC3CE          LL_TIM_OC_DisableClear\n
02368   *         CCMR2        OC4CE          LL_TIM_OC_DisableClear\n
02369   *         CCMR3        OC5CE          LL_TIM_OC_DisableClear\n
02370   *         CCMR3        OC6CE          LL_TIM_OC_DisableClear
02371   * @param  TIMx Timer instance
02372   * @param  Channel This parameter can be one of the following values:
02373   *         @arg @ref LL_TIM_CHANNEL_CH1
02374   *         @arg @ref LL_TIM_CHANNEL_CH2
02375   *         @arg @ref LL_TIM_CHANNEL_CH3
02376   *         @arg @ref LL_TIM_CHANNEL_CH4
02377   *         @arg @ref LL_TIM_CHANNEL_CH5
02378   *         @arg @ref LL_TIM_CHANNEL_CH6
02379   * @retval None
02380   */
02381 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
02382 {
02383   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02384   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02385   CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
02386 }
02387
02388 /**
02389   * @brief  Indicates clearing the output channel on an external event is enabled for the output channel.
02390   * @note This function enables clearing the output channel on an external event.
02391   * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
02392   * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
02393   *       or not a timer instance can clear the OCxREF signal on an external event.
02394   * @rmtoll CCMR1        OC1CE          LL_TIM_OC_IsEnabledClear\n
02395   *         CCMR1        OC2CE          LL_TIM_OC_IsEnabledClear\n
02396   *         CCMR2        OC3CE          LL_TIM_OC_IsEnabledClear\n
02397   *         CCMR2        OC4CE          LL_TIM_OC_IsEnabledClear\n
02398   *         CCMR3        OC5CE          LL_TIM_OC_IsEnabledClear\n
02399   *         CCMR3        OC6CE          LL_TIM_OC_IsEnabledClear
02400   * @param  TIMx Timer instance
02401   * @param  Channel This parameter can be one of the following values:
02402   *         @arg @ref LL_TIM_CHANNEL_CH1
02403   *         @arg @ref LL_TIM_CHANNEL_CH2
02404   *         @arg @ref LL_TIM_CHANNEL_CH3
02405   *         @arg @ref LL_TIM_CHANNEL_CH4
02406   *         @arg @ref LL_TIM_CHANNEL_CH5
02407   *         @arg @ref LL_TIM_CHANNEL_CH6
02408   * @retval State of bit (1 or 0).
02409   */
02410 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
02411 {
02412   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02413   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02414   register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
02415   return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
02416 }
02417
02418 /**
02419   * @brief  Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
02420   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
02421   *       dead-time insertion feature is supported by a timer instance.
02422   * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
02423   * @rmtoll BDTR         DTG           LL_TIM_OC_SetDeadTime
02424   * @param  TIMx Timer instance
02425   * @param  DeadTime between Min_Data=0 and Max_Data=255
02426   * @retval None
02427   */
02428 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
02429 {
02430   MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
02431 }
02432
02433 /**
02434   * @brief  Set compare value for output channel 1 (TIMx_CCR1).
02435   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
02436   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02437   *       whether or not a timer instance supports a 32 bits counter.
02438   * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
02439   *       output channel 1 is supported by a timer instance.
02440   * @rmtoll CCR1         CCR1          LL_TIM_OC_SetCompareCH1
02441   * @param  TIMx Timer instance
02442   * @param  CompareValue between Min_Data=0 and Max_Data=65535
02443   * @retval None
02444   */
02445 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
02446 {
02447   WRITE_REG(TIMx->CCR1, CompareValue);
02448 }
02449
02450 /**
02451   * @brief  Set compare value for output channel 2 (TIMx_CCR2).
02452   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
02453   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02454   *       whether or not a timer instance supports a 32 bits counter.
02455   * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
02456   *       output channel 2 is supported by a timer instance.
02457   * @rmtoll CCR2         CCR2          LL_TIM_OC_SetCompareCH2
02458   * @param  TIMx Timer instance
02459   * @param  CompareValue between Min_Data=0 and Max_Data=65535
02460   * @retval None
02461   */
02462 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
02463 {
02464   WRITE_REG(TIMx->CCR2, CompareValue);
02465 }
02466
02467 /**
02468   * @brief  Set compare value for output channel 3 (TIMx_CCR3).
02469   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
02470   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02471   *       whether or not a timer instance supports a 32 bits counter.
02472   * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
02473   *       output channel is supported by a timer instance.
02474   * @rmtoll CCR3         CCR3          LL_TIM_OC_SetCompareCH3
02475   * @param  TIMx Timer instance
02476   * @param  CompareValue between Min_Data=0 and Max_Data=65535
02477   * @retval None
02478   */
02479 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
02480 {
02481   WRITE_REG(TIMx->CCR3, CompareValue);
02482 }
02483
02484 /**
02485   * @brief  Set compare value for output channel 4 (TIMx_CCR4).
02486   * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
02487   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02488   *       whether or not a timer instance supports a 32 bits counter.
02489   * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
02490   *       output channel 4 is supported by a timer instance.
02491   * @rmtoll CCR4         CCR4          LL_TIM_OC_SetCompareCH4
02492   * @param  TIMx Timer instance
02493   * @param  CompareValue between Min_Data=0 and Max_Data=65535
02494   * @retval None
02495   */
02496 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
02497 {
02498   WRITE_REG(TIMx->CCR4, CompareValue);
02499 }
02500
02501 /**
02502   * @brief  Set compare value for output channel 5 (TIMx_CCR5).
02503   * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
02504   *       output channel 5 is supported by a timer instance.
02505   * @rmtoll CCR5         CCR5          LL_TIM_OC_SetCompareCH5
02506   * @param  TIMx Timer instance
02507   * @param  CompareValue between Min_Data=0 and Max_Data=65535
02508   * @retval None
02509   */
02510 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
02511 {
02512   MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
02513 }
02514
02515 /**
02516   * @brief  Set compare value for output channel 6 (TIMx_CCR6).
02517   * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
02518   *       output channel 6 is supported by a timer instance.
02519   * @rmtoll CCR6         CCR6          LL_TIM_OC_SetCompareCH6
02520   * @param  TIMx Timer instance
02521   * @param  CompareValue between Min_Data=0 and Max_Data=65535
02522   * @retval None
02523   */
02524 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
02525 {
02526   WRITE_REG(TIMx->CCR6, CompareValue);
02527 }
02528
02529 /**
02530   * @brief  Get compare value (TIMx_CCR1) set for  output channel 1.
02531   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
02532   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02533   *       whether or not a timer instance supports a 32 bits counter.
02534   * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
02535   *       output channel 1 is supported by a timer instance.
02536   * @rmtoll CCR1         CCR1          LL_TIM_OC_GetCompareCH1
02537   * @param  TIMx Timer instance
02538   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02539   */
02540 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
02541 {
02542   return (uint32_t)(READ_REG(TIMx->CCR1));
02543 }
02544
02545 /**
02546   * @brief  Get compare value (TIMx_CCR2) set for  output channel 2.
02547   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
02548   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02549   *       whether or not a timer instance supports a 32 bits counter.
02550   * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
02551   *       output channel 2 is supported by a timer instance.
02552   * @rmtoll CCR2         CCR2          LL_TIM_OC_GetCompareCH2
02553   * @param  TIMx Timer instance
02554   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02555   */
02556 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
02557 {
02558   return (uint32_t)(READ_REG(TIMx->CCR2));
02559 }
02560
02561 /**
02562   * @brief  Get compare value (TIMx_CCR3) set for  output channel 3.
02563   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
02564   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02565   *       whether or not a timer instance supports a 32 bits counter.
02566   * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
02567   *       output channel 3 is supported by a timer instance.
02568   * @rmtoll CCR3         CCR3          LL_TIM_OC_GetCompareCH3
02569   * @param  TIMx Timer instance
02570   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02571   */
02572 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
02573 {
02574   return (uint32_t)(READ_REG(TIMx->CCR3));
02575 }
02576
02577 /**
02578   * @brief  Get compare value (TIMx_CCR4) set for  output channel 4.
02579   * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
02580   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02581   *       whether or not a timer instance supports a 32 bits counter.
02582   * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
02583   *       output channel 4 is supported by a timer instance.
02584   * @rmtoll CCR4         CCR4          LL_TIM_OC_GetCompareCH4
02585   * @param  TIMx Timer instance
02586   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02587   */
02588 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
02589 {
02590   return (uint32_t)(READ_REG(TIMx->CCR4));
02591 }
02592
02593 /**
02594   * @brief  Get compare value (TIMx_CCR5) set for  output channel 5.
02595   * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
02596   *       output channel 5 is supported by a timer instance.
02597   * @rmtoll CCR5         CCR5          LL_TIM_OC_GetCompareCH5
02598   * @param  TIMx Timer instance
02599   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02600   */
02601 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
02602 {
02603   return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
02604 }
02605
02606 /**
02607   * @brief  Get compare value (TIMx_CCR6) set for  output channel 6.
02608   * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
02609   *       output channel 6 is supported by a timer instance.
02610   * @rmtoll CCR6         CCR6          LL_TIM_OC_GetCompareCH6
02611   * @param  TIMx Timer instance
02612   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02613   */
02614 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)
02615 {
02616   return (uint32_t)(READ_REG(TIMx->CCR6));
02617 }
02618
02619 /**
02620   * @brief  Select on which reference signal the OC5REF is combined to.
02621   * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
02622   *       whether or not a timer instance supports the combined 3-phase PWM mode.
02623   * @rmtoll CCR5         GC5C3          LL_TIM_SetCH5CombinedChannels\n
02624   *         CCR5         GC5C2          LL_TIM_SetCH5CombinedChannels\n
02625   *         CCR5         GC5C1          LL_TIM_SetCH5CombinedChannels
02626   * @param  TIMx Timer instance
02627   * @param  GroupCH5 This parameter can be a combination of the following values:
02628   *         @arg @ref LL_TIM_GROUPCH5_NONE
02629   *         @arg @ref LL_TIM_GROUPCH5_OC1REFC
02630   *         @arg @ref LL_TIM_GROUPCH5_OC2REFC
02631   *         @arg @ref LL_TIM_GROUPCH5_OC3REFC
02632   * @retval None
02633   */
02634 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
02635 {
02636   MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
02637 }
02638
02639 /**
02640   * @}
02641   */
02642
02643 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
02644   * @{
02645   */
02646 /**
02647   * @brief  Configure input channel.
02648   * @rmtoll CCMR1        CC1S          LL_TIM_IC_Config\n
02649   *         CCMR1        IC1PSC        LL_TIM_IC_Config\n
02650   *         CCMR1        IC1F          LL_TIM_IC_Config\n
02651   *         CCMR1        CC2S          LL_TIM_IC_Config\n
02652   *         CCMR1        IC2PSC        LL_TIM_IC_Config\n
02653   *         CCMR1        IC2F          LL_TIM_IC_Config\n
02654   *         CCMR2        CC3S          LL_TIM_IC_Config\n
02655   *         CCMR2        IC3PSC        LL_TIM_IC_Config\n
02656   *         CCMR2        IC3F          LL_TIM_IC_Config\n
02657   *         CCMR2        CC4S          LL_TIM_IC_Config\n
02658   *         CCMR2        IC4PSC        LL_TIM_IC_Config\n
02659   *         CCMR2        IC4F          LL_TIM_IC_Config\n
02660   *         CCER         CC1P          LL_TIM_IC_Config\n
02661   *         CCER         CC1NP         LL_TIM_IC_Config\n
02662   *         CCER         CC2P          LL_TIM_IC_Config\n
02663   *         CCER         CC2NP         LL_TIM_IC_Config\n
02664   *         CCER         CC3P          LL_TIM_IC_Config\n
02665   *         CCER         CC3NP         LL_TIM_IC_Config\n
02666   *         CCER         CC4P          LL_TIM_IC_Config\n
02667   *         CCER         CC4NP         LL_TIM_IC_Config
02668   * @param  TIMx Timer instance
02669   * @param  Channel This parameter can be one of the following values:
02670   *         @arg @ref LL_TIM_CHANNEL_CH1
02671   *         @arg @ref LL_TIM_CHANNEL_CH2
02672   *         @arg @ref LL_TIM_CHANNEL_CH3
02673   *         @arg @ref LL_TIM_CHANNEL_CH4
02674   * @param  Configuration This parameter must be a combination of all the following values:
02675   *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
02676   *         @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
02677   *         @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
02678   *         @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
02679   * @retval None
02680   */
02681 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
02682 {
02683   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02684   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02685   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
02686              ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S))  << SHIFT_TAB_ICxx[iChannel]);
02687   MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
02688              (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
02689 }
02690
02691 /**
02692   * @brief  Set the active input.
02693   * @rmtoll CCMR1        CC1S          LL_TIM_IC_SetActiveInput\n
02694   *         CCMR1        CC2S          LL_TIM_IC_SetActiveInput\n
02695   *         CCMR2        CC3S          LL_TIM_IC_SetActiveInput\n
02696   *         CCMR2        CC4S          LL_TIM_IC_SetActiveInput
02697   * @param  TIMx Timer instance
02698   * @param  Channel This parameter can be one of the following values:
02699   *         @arg @ref LL_TIM_CHANNEL_CH1
02700   *         @arg @ref LL_TIM_CHANNEL_CH2
02701   *         @arg @ref LL_TIM_CHANNEL_CH3
02702   *         @arg @ref LL_TIM_CHANNEL_CH4
02703   * @param  ICActiveInput This parameter can be one of the following values:
02704   *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
02705   *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
02706   *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
02707   * @retval None
02708   */
02709 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
02710 {
02711   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02712   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02713   MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
02714 }
02715
02716 /**
02717   * @brief  Get the current active input.
02718   * @rmtoll CCMR1        CC1S          LL_TIM_IC_GetActiveInput\n
02719   *         CCMR1        CC2S          LL_TIM_IC_GetActiveInput\n
02720   *         CCMR2        CC3S          LL_TIM_IC_GetActiveInput\n
02721   *         CCMR2        CC4S          LL_TIM_IC_GetActiveInput
02722   * @param  TIMx Timer instance
02723   * @param  Channel This parameter can be one of the following values:
02724   *         @arg @ref LL_TIM_CHANNEL_CH1
02725   *         @arg @ref LL_TIM_CHANNEL_CH2
02726   *         @arg @ref LL_TIM_CHANNEL_CH3
02727   *         @arg @ref LL_TIM_CHANNEL_CH4
02728   * @retval Returned value can be one of the following values:
02729   *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
02730   *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
02731   *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
02732   */
02733 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
02734 {
02735   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02736   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02737   return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
02738 }
02739
02740 /**
02741   * @brief  Set the prescaler of input channel.
02742   * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_SetPrescaler\n
02743   *         CCMR1        IC2PSC        LL_TIM_IC_SetPrescaler\n
02744   *         CCMR2        IC3PSC        LL_TIM_IC_SetPrescaler\n
02745   *         CCMR2        IC4PSC        LL_TIM_IC_SetPrescaler
02746   * @param  TIMx Timer instance
02747   * @param  Channel This parameter can be one of the following values:
02748   *         @arg @ref LL_TIM_CHANNEL_CH1
02749   *         @arg @ref LL_TIM_CHANNEL_CH2
02750   *         @arg @ref LL_TIM_CHANNEL_CH3
02751   *         @arg @ref LL_TIM_CHANNEL_CH4
02752   * @param  ICPrescaler This parameter can be one of the following values:
02753   *         @arg @ref LL_TIM_ICPSC_DIV1
02754   *         @arg @ref LL_TIM_ICPSC_DIV2
02755   *         @arg @ref LL_TIM_ICPSC_DIV4
02756   *         @arg @ref LL_TIM_ICPSC_DIV8
02757   * @retval None
02758   */
02759 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
02760 {
02761   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02762   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02763   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
02764 }
02765
02766 /**
02767   * @brief  Get the current prescaler value acting on an  input channel.
02768   * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_GetPrescaler\n
02769   *         CCMR1        IC2PSC        LL_TIM_IC_GetPrescaler\n
02770   *         CCMR2        IC3PSC        LL_TIM_IC_GetPrescaler\n
02771   *         CCMR2        IC4PSC        LL_TIM_IC_GetPrescaler
02772   * @param  TIMx Timer instance
02773   * @param  Channel This parameter can be one of the following values:
02774   *         @arg @ref LL_TIM_CHANNEL_CH1
02775   *         @arg @ref LL_TIM_CHANNEL_CH2
02776   *         @arg @ref LL_TIM_CHANNEL_CH3
02777   *         @arg @ref LL_TIM_CHANNEL_CH4
02778   * @retval Returned value can be one of the following values:
02779   *         @arg @ref LL_TIM_ICPSC_DIV1
02780   *         @arg @ref LL_TIM_ICPSC_DIV2
02781   *         @arg @ref LL_TIM_ICPSC_DIV4
02782   *         @arg @ref LL_TIM_ICPSC_DIV8
02783   */
02784 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
02785 {
02786   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02787   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02788   return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
02789 }
02790
02791 /**
02792   * @brief  Set the input filter duration.
02793   * @rmtoll CCMR1        IC1F          LL_TIM_IC_SetFilter\n
02794   *         CCMR1        IC2F          LL_TIM_IC_SetFilter\n
02795   *         CCMR2        IC3F          LL_TIM_IC_SetFilter\n
02796   *         CCMR2        IC4F          LL_TIM_IC_SetFilter
02797   * @param  TIMx Timer instance
02798   * @param  Channel This parameter can be one of the following values:
02799   *         @arg @ref LL_TIM_CHANNEL_CH1
02800   *         @arg @ref LL_TIM_CHANNEL_CH2
02801   *         @arg @ref LL_TIM_CHANNEL_CH3
02802   *         @arg @ref LL_TIM_CHANNEL_CH4
02803   * @param  ICFilter This parameter can be one of the following values:
02804   *         @arg @ref LL_TIM_IC_FILTER_FDIV1
02805   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
02806   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
02807   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
02808   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
02809   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
02810   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
02811   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
02812   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
02813   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
02814   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
02815   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
02816   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
02817   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
02818   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
02819   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
02820   * @retval None
02821   */
02822 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
02823 {
02824   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02825   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02826   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
02827 }
02828
02829 /**
02830   * @brief  Get the input filter duration.
02831   * @rmtoll CCMR1        IC1F          LL_TIM_IC_GetFilter\n
02832   *         CCMR1        IC2F          LL_TIM_IC_GetFilter\n
02833   *         CCMR2        IC3F          LL_TIM_IC_GetFilter\n
02834   *         CCMR2        IC4F          LL_TIM_IC_GetFilter
02835   * @param  TIMx Timer instance
02836   * @param  Channel This parameter can be one of the following values:
02837   *         @arg @ref LL_TIM_CHANNEL_CH1
02838   *         @arg @ref LL_TIM_CHANNEL_CH2
02839   *         @arg @ref LL_TIM_CHANNEL_CH3
02840   *         @arg @ref LL_TIM_CHANNEL_CH4
02841   * @retval Returned value can be one of the following values:
02842   *         @arg @ref LL_TIM_IC_FILTER_FDIV1
02843   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
02844   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
02845   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
02846   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
02847   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
02848   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
02849   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
02850   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
02851   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
02852   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
02853   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
02854   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
02855   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
02856   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
02857   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
02858   */
02859 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
02860 {
02861   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02862   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02863   return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
02864 }
02865
02866 /**
02867   * @brief  Set the input channel polarity.
02868   * @rmtoll CCER         CC1P          LL_TIM_IC_SetPolarity\n
02869   *         CCER         CC1NP         LL_TIM_IC_SetPolarity\n
02870   *         CCER         CC2P          LL_TIM_IC_SetPolarity\n
02871   *         CCER         CC2NP         LL_TIM_IC_SetPolarity\n
02872   *         CCER         CC3P          LL_TIM_IC_SetPolarity\n
02873   *         CCER         CC3NP         LL_TIM_IC_SetPolarity\n
02874   *         CCER         CC4P          LL_TIM_IC_SetPolarity\n
02875   *         CCER         CC4NP         LL_TIM_IC_SetPolarity
02876   * @param  TIMx Timer instance
02877   * @param  Channel This parameter can be one of the following values:
02878   *         @arg @ref LL_TIM_CHANNEL_CH1
02879   *         @arg @ref LL_TIM_CHANNEL_CH2
02880   *         @arg @ref LL_TIM_CHANNEL_CH3
02881   *         @arg @ref LL_TIM_CHANNEL_CH4
02882   * @param  ICPolarity This parameter can be one of the following values:
02883   *         @arg @ref LL_TIM_IC_POLARITY_RISING
02884   *         @arg @ref LL_TIM_IC_POLARITY_FALLING
02885   *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
02886   * @retval None
02887   */
02888 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
02889 {
02890   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02891   MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
02892              ICPolarity << SHIFT_TAB_CCxP[iChannel]);
02893 }
02894
02895 /**
02896   * @brief  Get the current input channel polarity.
02897   * @rmtoll CCER         CC1P          LL_TIM_IC_GetPolarity\n
02898   *         CCER         CC1NP         LL_TIM_IC_GetPolarity\n
02899   *         CCER         CC2P          LL_TIM_IC_GetPolarity\n
02900   *         CCER         CC2NP         LL_TIM_IC_GetPolarity\n
02901   *         CCER         CC3P          LL_TIM_IC_GetPolarity\n
02902   *         CCER         CC3NP         LL_TIM_IC_GetPolarity\n
02903   *         CCER         CC4P          LL_TIM_IC_GetPolarity\n
02904   *         CCER         CC4NP         LL_TIM_IC_GetPolarity
02905   * @param  TIMx Timer instance
02906   * @param  Channel This parameter can be one of the following values:
02907   *         @arg @ref LL_TIM_CHANNEL_CH1
02908   *         @arg @ref LL_TIM_CHANNEL_CH2
02909   *         @arg @ref LL_TIM_CHANNEL_CH3
02910   *         @arg @ref LL_TIM_CHANNEL_CH4
02911   * @retval Returned value can be one of the following values:
02912   *         @arg @ref LL_TIM_IC_POLARITY_RISING
02913   *         @arg @ref LL_TIM_IC_POLARITY_FALLING
02914   *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
02915   */
02916 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
02917 {
02918   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02919   return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
02920           SHIFT_TAB_CCxP[iChannel]);
02921 }
02922
02923 /**
02924   * @brief  Connect the TIMx_CH1, CH2 and CH3 pins  to the TI1 input (XOR combination).
02925   * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
02926   *       a timer instance provides an XOR input.
02927   * @rmtoll CR2          TI1S          LL_TIM_IC_EnableXORCombination
02928   * @param  TIMx Timer instance
02929   * @retval None
02930   */
02931 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
02932 {
02933   SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
02934 }
02935
02936 /**
02937   * @brief  Disconnect the TIMx_CH1, CH2 and CH3 pins  from the TI1 input.
02938   * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
02939   *       a timer instance provides an XOR input.
02940   * @rmtoll CR2          TI1S          LL_TIM_IC_DisableXORCombination
02941   * @param  TIMx Timer instance
02942   * @retval None
02943   */
02944 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
02945 {
02946   CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
02947 }
02948
02949 /**
02950   * @brief  Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
02951   * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
02952   * a timer instance provides an XOR input.
02953   * @rmtoll CR2          TI1S          LL_TIM_IC_IsEnabledXORCombination
02954   * @param  TIMx Timer instance
02955   * @retval State of bit (1 or 0).
02956   */
02957 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
02958 {
02959   return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
02960 }
02961
02962 /**
02963   * @brief  Get captured value for input channel 1.
02964   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
02965   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02966   *       whether or not a timer instance supports a 32 bits counter.
02967   * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
02968   *       input channel 1 is supported by a timer instance.
02969   * @rmtoll CCR1         CCR1          LL_TIM_IC_GetCaptureCH1
02970   * @param  TIMx Timer instance
02971   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
02972   */
02973 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
02974 {
02975   return (uint32_t)(READ_REG(TIMx->CCR1));
02976 }
02977
02978 /**
02979   * @brief  Get captured value for input channel 2.
02980   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
02981   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02982   *       whether or not a timer instance supports a 32 bits counter.
02983   * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
02984   *       input channel 2 is supported by a timer instance.
02985   * @rmtoll CCR2         CCR2          LL_TIM_IC_GetCaptureCH2
02986   * @param  TIMx Timer instance
02987   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
02988   */
02989 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
02990 {
02991   return (uint32_t)(READ_REG(TIMx->CCR2));
02992 }
02993
02994 /**
02995   * @brief  Get captured value for input channel 3.
02996   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
02997   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
02998   *       whether or not a timer instance supports a 32 bits counter.
02999   * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
03000   *       input channel 3 is supported by a timer instance.
03001   * @rmtoll CCR3         CCR3          LL_TIM_IC_GetCaptureCH3
03002   * @param  TIMx Timer instance
03003   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
03004   */
03005 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
03006 {
03007   return (uint32_t)(READ_REG(TIMx->CCR3));
03008 }
03009
03010 /**
03011   * @brief  Get captured value for input channel 4.
03012   * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
03013   * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
03014   *       whether or not a timer instance supports a 32 bits counter.
03015   * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
03016   *       input channel 4 is supported by a timer instance.
03017   * @rmtoll CCR4         CCR4          LL_TIM_IC_GetCaptureCH4
03018   * @param  TIMx Timer instance
03019   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
03020   */
03021 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
03022 {
03023   return (uint32_t)(READ_REG(TIMx->CCR4));
03024 }
03025
03026 /**
03027   * @}
03028   */
03029
03030 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
03031   * @{
03032   */
03033 /**
03034   * @brief  Enable external clock mode 2.
03035   * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
03036   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
03037   *       whether or not a timer instance supports external clock mode2.
03038   * @rmtoll SMCR         ECE           LL_TIM_EnableExternalClock
03039   * @param  TIMx Timer instance
03040   * @retval None
03041   */
03042 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
03043 {
03044   SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
03045 }
03046
03047 /**
03048   * @brief  Disable external clock mode 2.
03049   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
03050   *       whether or not a timer instance supports external clock mode2.
03051   * @rmtoll SMCR         ECE           LL_TIM_DisableExternalClock
03052   * @param  TIMx Timer instance
03053   * @retval None
03054   */
03055 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
03056 {
03057   CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
03058 }
03059
03060 /**
03061   * @brief  Indicate whether external clock mode 2 is enabled.
03062   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
03063   *       whether or not a timer instance supports external clock mode2.
03064   * @rmtoll SMCR         ECE           LL_TIM_IsEnabledExternalClock
03065   * @param  TIMx Timer instance
03066   * @retval State of bit (1 or 0).
03067   */
03068 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
03069 {
03070   return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
03071 }
03072
03073 /**
03074   * @brief  Set the clock source of the counter clock.
03075   * @note when selected clock source is external clock mode 1, the timer input
03076   *       the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
03077   *       function. This timer input must be configured by calling
03078   *       the @ref LL_TIM_IC_Config() function.
03079   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
03080   *       whether or not a timer instance supports external clock mode1.
03081   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
03082   *       whether or not a timer instance supports external clock mode2.
03083   * @rmtoll SMCR         SMS           LL_TIM_SetClockSource\n
03084   *         SMCR         ECE           LL_TIM_SetClockSource
03085   * @param  TIMx Timer instance
03086   * @param  ClockSource This parameter can be one of the following values:
03087   *         @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
03088   *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
03089   *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
03090   * @retval None
03091   */
03092 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
03093 {
03094   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
03095 }
03096
03097 /**
03098   * @brief  Set the encoder interface mode.
03099   * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
03100   *       whether or not a timer instance supports the encoder mode.
03101   * @rmtoll SMCR         SMS           LL_TIM_SetEncoderMode
03102   * @param  TIMx Timer instance
03103   * @param  EncoderMode This parameter can be one of the following values:
03104   *         @arg @ref LL_TIM_ENCODERMODE_X2_TI1
03105   *         @arg @ref LL_TIM_ENCODERMODE_X2_TI2
03106   *         @arg @ref LL_TIM_ENCODERMODE_X4_TI12
03107   * @retval None
03108   */
03109 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
03110 {
03111   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
03112 }
03113
03114 /**
03115   * @}
03116   */
03117
03118 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
03119   * @{
03120   */
03121 /**
03122   * @brief  Set the trigger output (TRGO) used for timer synchronization .
03123   * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
03124   *       whether or not a timer instance can operate as a master timer.
03125   * @rmtoll CR2          MMS           LL_TIM_SetTriggerOutput
03126   * @param  TIMx Timer instance
03127   * @param  TimerSynchronization This parameter can be one of the following values:
03128   *         @arg @ref LL_TIM_TRGO_RESET
03129   *         @arg @ref LL_TIM_TRGO_ENABLE
03130   *         @arg @ref LL_TIM_TRGO_UPDATE
03131   *         @arg @ref LL_TIM_TRGO_CC1IF
03132   *         @arg @ref LL_TIM_TRGO_OC1REF
03133   *         @arg @ref LL_TIM_TRGO_OC2REF
03134   *         @arg @ref LL_TIM_TRGO_OC3REF
03135   *         @arg @ref LL_TIM_TRGO_OC4REF
03136   * @retval None
03137   */
03138 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
03139 {
03140   MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
03141 }
03142
03143 /**
03144   * @brief  Set the trigger output 2 (TRGO2) used for ADC synchronization .
03145   * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
03146   *       whether or not a timer instance can be used for ADC synchronization.
03147   * @rmtoll CR2          MMS2          LL_TIM_SetTriggerOutput2
03148   * @param  TIMx Timer Instance
03149   * @param  ADCSynchronization This parameter can be one of the following values:
03150   *         @arg @ref LL_TIM_TRGO2_RESET
03151   *         @arg @ref LL_TIM_TRGO2_ENABLE
03152   *         @arg @ref LL_TIM_TRGO2_UPDATE
03153   *         @arg @ref LL_TIM_TRGO2_CC1F
03154   *         @arg @ref LL_TIM_TRGO2_OC1
03155   *         @arg @ref LL_TIM_TRGO2_OC2
03156   *         @arg @ref LL_TIM_TRGO2_OC3
03157   *         @arg @ref LL_TIM_TRGO2_OC4
03158   *         @arg @ref LL_TIM_TRGO2_OC5
03159   *         @arg @ref LL_TIM_TRGO2_OC6
03160   *         @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
03161   *         @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
03162   *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
03163   *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
03164   *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
03165   *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
03166   * @retval None
03167   */
03168 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
03169 {
03170   MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
03171 }
03172
03173 /**
03174   * @brief  Set the synchronization mode of a slave timer.
03175   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
03176   *       a timer instance can operate as a slave timer.
03177   * @rmtoll SMCR         SMS           LL_TIM_SetSlaveMode
03178   * @param  TIMx Timer instance
03179   * @param  SlaveMode This parameter can be one of the following values:
03180   *         @arg @ref LL_TIM_SLAVEMODE_DISABLED
03181   *         @arg @ref LL_TIM_SLAVEMODE_RESET
03182   *         @arg @ref LL_TIM_SLAVEMODE_GATED
03183   *         @arg @ref LL_TIM_SLAVEMODE_TRIGGER
03184   *         @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
03185   * @retval None
03186   */
03187 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
03188 {
03189   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
03190 }
03191
03192 /**
03193   * @brief  Set the selects the trigger input to be used to synchronize the counter.
03194   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
03195   *       a timer instance can operate as a slave timer.
03196   * @rmtoll SMCR         TS            LL_TIM_SetTriggerInput
03197   * @param  TIMx Timer instance
03198   * @param  TriggerInput This parameter can be one of the following values:
03199   *         @arg @ref LL_TIM_TS_ITR0
03200   *         @arg @ref LL_TIM_TS_ITR1
03201   *         @arg @ref LL_TIM_TS_ITR2
03202   *         @arg @ref LL_TIM_TS_ITR3
03203   *         @arg @ref LL_TIM_TS_TI1F_ED
03204   *         @arg @ref LL_TIM_TS_TI1FP1
03205   *         @arg @ref LL_TIM_TS_TI2FP2
03206   *         @arg @ref LL_TIM_TS_ETRF
03207   * @retval None
03208   */
03209 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
03210 {
03211   MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
03212 }
03213
03214 /**
03215   * @brief  Enable the Master/Slave mode.
03216   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
03217   *       a timer instance can operate as a slave timer.
03218   * @rmtoll SMCR         MSM           LL_TIM_EnableMasterSlaveMode
03219   * @param  TIMx Timer instance
03220   * @retval None
03221   */
03222 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
03223 {
03224   SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
03225 }
03226
03227 /**
03228   * @brief  Disable the Master/Slave mode.
03229   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
03230   *       a timer instance can operate as a slave timer.
03231   * @rmtoll SMCR         MSM           LL_TIM_DisableMasterSlaveMode
03232   * @param  TIMx Timer instance
03233   * @retval None
03234   */
03235 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
03236 {
03237   CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
03238 }
03239
03240 /**
03241   * @brief Indicates whether the Master/Slave mode is enabled.
03242   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
03243   * a timer instance can operate as a slave timer.
03244   * @rmtoll SMCR         MSM           LL_TIM_IsEnabledMasterSlaveMode
03245   * @param  TIMx Timer instance
03246   * @retval State of bit (1 or 0).
03247   */
03248 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
03249 {
03250   return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
03251 }
03252
03253 /**
03254   * @brief  Configure the external trigger (ETR) input.
03255   * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
03256   *       a timer instance provides an external trigger input.
03257   * @rmtoll SMCR         ETP           LL_TIM_ConfigETR\n
03258   *         SMCR         ETPS          LL_TIM_ConfigETR\n
03259   *         SMCR         ETF           LL_TIM_ConfigETR
03260   * @param  TIMx Timer instance
03261   * @param  ETRPolarity This parameter can be one of the following values:
03262   *         @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
03263   *         @arg @ref LL_TIM_ETR_POLARITY_INVERTED
03264   * @param  ETRPrescaler This parameter can be one of the following values:
03265   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV1
03266   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV2
03267   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV4
03268   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV8
03269   * @param  ETRFilter This parameter can be one of the following values:
03270   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1
03271   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
03272   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
03273   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
03274   *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
03275   *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
03276   *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
03277   *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
03278   *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
03279   *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
03280   *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
03281   *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
03282   *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
03283   *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
03284   *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
03285   *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
03286   * @retval None
03287   */
03288 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
03289                                       uint32_t ETRFilter)
03290 {
03291   MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
03292 }
03293
03294 /**
03295   * @brief  Select the external trigger (ETR) input source.
03296   * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
03297   *       not a timer instance supports ETR source selection.
03298   * @note When this function is called with LL_TIM_ETRSOURCE_GPIO,
03299   *       LL_TIM_ETRSOURCE_ADC1_AWD1, LL_TIM_ETRSOURCE_ADC1_AWD2 or
03300   *       LL_TIM_ETRSOURCE_ADC1_AWD3, ETR source relies on TIMx ETR remapping
03301   *       capability configured through the function @ref LL_TIM_SetRemap().
03302   * @rmtoll AF1          ETRSEL        LL_TIM_SetETRSource
03303   * @param  TIMx Timer instance
03304   * @param  ETRSource This parameter can be one of the following values:
03305   *         @arg @ref LL_TIM_ETRSOURCE_GPIO
03306   *         @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD1
03307   *         @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD2
03308   *         @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD3
03309   *         @arg @ref LL_TIM_ETRSOURCE_COMP1
03310   *         @arg @ref LL_TIM_ETRSOURCE_COMP2
03311   * @retval None
03312   */
03313 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
03314 {
03315
03316   MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
03317 }
03318
03319 /**
03320   * @}
03321   */
03322
03323 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
03324   * @{
03325   */
03326 /**
03327   * @brief  Enable the break function.
03328   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03329   *       a timer instance provides a break input.
03330   * @rmtoll BDTR         BKE           LL_TIM_EnableBRK
03331   * @param  TIMx Timer instance
03332   * @retval None
03333   */
03334 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
03335 {
03336   SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
03337 }
03338
03339 /**
03340   * @brief  Disable the break function.
03341   * @rmtoll BDTR         BKE           LL_TIM_DisableBRK
03342   * @param  TIMx Timer instance
03343   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03344   *       a timer instance provides a break input.
03345   * @retval None
03346   */
03347 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
03348 {
03349   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
03350 }
03351
03352 /**
03353   * @brief  Configure the break input.
03354   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03355   *       a timer instance provides a break input.
03356   * @rmtoll BDTR         BKP           LL_TIM_ConfigBRK\n
03357   *         BDTR         BKF           LL_TIM_ConfigBRK
03358   * @param  TIMx Timer instance
03359   * @param  BreakPolarity This parameter can be one of the following values:
03360   *         @arg @ref LL_TIM_BREAK_POLARITY_LOW
03361   *         @arg @ref LL_TIM_BREAK_POLARITY_HIGH
03362   * @param  BreakFilter This parameter can be one of the following values:
03363   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1
03364   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
03365   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
03366   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
03367   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
03368   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
03369   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
03370   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
03371   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
03372   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
03373   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
03374   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
03375   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
03376   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
03377   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
03378   *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
03379   * @retval None
03380   */
03381 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity,
03382                                       uint32_t BreakFilter)
03383 {
03384   MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter);
03385 }
03386
03387 /**
03388   * @brief  Enable the break 2 function.
03389   * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
03390   *       a timer instance provides a second break input.
03391   * @rmtoll BDTR         BK2E          LL_TIM_EnableBRK2
03392   * @param  TIMx Timer instance
03393   * @retval None
03394   */
03395 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
03396 {
03397   SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
03398 }
03399
03400 /**
03401   * @brief  Disable the break  2 function.
03402   * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
03403   *       a timer instance provides a second break input.
03404   * @rmtoll BDTR         BK2E          LL_TIM_DisableBRK2
03405   * @param  TIMx Timer instance
03406   * @retval None
03407   */
03408 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
03409 {
03410   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
03411 }
03412
03413 /**
03414   * @brief  Configure the break 2 input.
03415   * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
03416   *       a timer instance provides a second break input.
03417   * @rmtoll BDTR         BK2P          LL_TIM_ConfigBRK2\n
03418   *         BDTR         BK2F          LL_TIM_ConfigBRK2
03419   * @param  TIMx Timer instance
03420   * @param  Break2Polarity This parameter can be one of the following values:
03421   *         @arg @ref LL_TIM_BREAK2_POLARITY_LOW
03422   *         @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
03423   * @param  Break2Filter This parameter can be one of the following values:
03424   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
03425   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
03426   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
03427   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
03428   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
03429   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
03430   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
03431   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
03432   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
03433   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
03434   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
03435   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
03436   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
03437   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
03438   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
03439   *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
03440   * @retval None
03441   */
03442 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
03443 {
03444   MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter);
03445 }
03446
03447 /**
03448   * @brief  Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
03449   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03450   *       a timer instance provides a break input.
03451   * @rmtoll BDTR         OSSI          LL_TIM_SetOffStates\n
03452   *         BDTR         OSSR          LL_TIM_SetOffStates
03453   * @param  TIMx Timer instance
03454   * @param  OffStateIdle This parameter can be one of the following values:
03455   *         @arg @ref LL_TIM_OSSI_DISABLE
03456   *         @arg @ref LL_TIM_OSSI_ENABLE
03457   * @param  OffStateRun This parameter can be one of the following values:
03458   *         @arg @ref LL_TIM_OSSR_DISABLE
03459   *         @arg @ref LL_TIM_OSSR_ENABLE
03460   * @retval None
03461   */
03462 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
03463 {
03464   MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
03465 }
03466
03467 /**
03468   * @brief  Enable automatic output (MOE can be set by software or automatically when a break input is active).
03469   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03470   *       a timer instance provides a break input.
03471   * @rmtoll BDTR         AOE           LL_TIM_EnableAutomaticOutput
03472   * @param  TIMx Timer instance
03473   * @retval None
03474   */
03475 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
03476 {
03477   SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
03478 }
03479
03480 /**
03481   * @brief  Disable automatic output (MOE can be set only by software).
03482   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03483   *       a timer instance provides a break input.
03484   * @rmtoll BDTR         AOE           LL_TIM_DisableAutomaticOutput
03485   * @param  TIMx Timer instance
03486   * @retval None
03487   */
03488 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
03489 {
03490   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
03491 }
03492
03493 /**
03494   * @brief  Indicate whether automatic output is enabled.
03495   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03496   *       a timer instance provides a break input.
03497   * @rmtoll BDTR         AOE           LL_TIM_IsEnabledAutomaticOutput
03498   * @param  TIMx Timer instance
03499   * @retval State of bit (1 or 0).
03500   */
03501 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
03502 {
03503   return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
03504 }
03505
03506 /**
03507   * @brief  Enable the outputs (set the MOE bit in TIMx_BDTR register).
03508   * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
03509   *       software and is reset in case of break or break2 event
03510   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03511   *       a timer instance provides a break input.
03512   * @rmtoll BDTR         MOE           LL_TIM_EnableAllOutputs
03513   * @param  TIMx Timer instance
03514   * @retval None
03515   */
03516 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
03517 {
03518   SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
03519 }
03520
03521 /**
03522   * @brief  Disable the outputs (reset the MOE bit in TIMx_BDTR register).
03523   * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
03524   *       software and is reset in case of break or break2 event.
03525   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03526   *       a timer instance provides a break input.
03527   * @rmtoll BDTR         MOE           LL_TIM_DisableAllOutputs
03528   * @param  TIMx Timer instance
03529   * @retval None
03530   */
03531 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
03532 {
03533   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
03534 }
03535
03536 /**
03537   * @brief  Indicates whether outputs are enabled.
03538   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
03539   *       a timer instance provides a break input.
03540   * @rmtoll BDTR         MOE           LL_TIM_IsEnabledAllOutputs
03541   * @param  TIMx Timer instance
03542   * @retval State of bit (1 or 0).
03543   */
03544 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
03545 {
03546   return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
03547 }
03548
03549 /**
03550   * @brief  Enable the signals connected to the designated timer break input.
03551   * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
03552   *       or not a timer instance allows for break input selection.
03553   * @rmtoll AF1          BKINE         LL_TIM_EnableBreakInputSource\n
03554   *         AF1          BKCMP1E       LL_TIM_EnableBreakInputSource\n
03555   *         AF1          BKCMP2E       LL_TIM_EnableBreakInputSource\n
03556   *         AF2          BK2INE        LL_TIM_EnableBreakInputSource\n
03557   *         AF2          BK2CMP1E      LL_TIM_EnableBreakInputSource\n
03558   *         AF2          BK2CMP2E      LL_TIM_EnableBreakInputSource
03559   * @param  TIMx Timer instance
03560   * @param  BreakInput This parameter can be one of the following values:
03561   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
03562   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
03563   * @param  Source This parameter can be one of the following values:
03564   *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
03565   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 (*)
03566   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 (*)
03567   *
03568   *         (*)  Value not defined in all devices.
03569   * @retval None
03570   */
03571 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
03572 {
03573   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
03574   SET_BIT(*pReg, Source);
03575 }
03576
03577 /**
03578   * @brief  Disable the signals connected to the designated timer break input.
03579   * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
03580   *       or not a timer instance allows for break input selection.
03581   * @rmtoll AF1          BKINE         LL_TIM_DisableBreakInputSource\n
03582   *         AF1          BKCMP1E       LL_TIM_DisableBreakInputSource\n
03583   *         AF1          BKCMP2E       LL_TIM_DisableBreakInputSource\n
03584   *         AF2          BK2INE        LL_TIM_DisableBreakInputSource\n
03585   *         AF2          BK2CMP1E      LL_TIM_DisableBreakInputSource\n
03586   *         AF2          BK2CMP2E      LL_TIM_DisableBreakInputSource
03587   * @param  TIMx Timer instance
03588   * @param  BreakInput This parameter can be one of the following values:
03589   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
03590   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
03591   * @param  Source This parameter can be one of the following values:
03592   *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
03593   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 (*)
03594   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 (*)
03595   *
03596   *         (*)  Value not defined in all devices.
03597   * @retval None
03598   */
03599 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
03600 {
03601   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
03602   CLEAR_BIT(*pReg, Source);
03603 }
03604
03605 /**
03606   * @brief  Set the polarity of the break signal for the timer break input.
03607   * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
03608   *       or not a timer instance allows for break input selection.
03609   * @rmtoll AF1          BKINP         LL_TIM_SetBreakInputSourcePolarity\n
03610   *         AF1          BKCMP1P       LL_TIM_SetBreakInputSourcePolarity\n
03611   *         AF1          BKCMP2P       LL_TIM_SetBreakInputSourcePolarity\n
03612   *         AF2          BK2INP        LL_TIM_SetBreakInputSourcePolarity\n
03613   *         AF2          BK2CMP1P      LL_TIM_SetBreakInputSourcePolarity\n
03614   *         AF2          BK2CMP2P      LL_TIM_SetBreakInputSourcePolarity
03615   * @param  TIMx Timer instance
03616   * @param  BreakInput This parameter can be one of the following values:
03617   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
03618   *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
03619   * @param  Source This parameter can be one of the following values:
03620   *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
03621   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 (*)
03622   *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 (*)
03623   * @param  Polarity This parameter can be one of the following values:
03624   *         @arg @ref LL_TIM_BKIN_POLARITY_LOW
03625   *         @arg @ref LL_TIM_BKIN_POLARITY_HIGH
03626   *
03627   *         (*)  Value not defined in all devices.
03628   * @retval None
03629   */
03630 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
03631                                                         uint32_t Polarity)
03632 {
03633   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
03634   MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
03635 }
03636 /**
03637   * @}
03638   */
03639
03640 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
03641   * @{
03642   */
03643 /**
03644   * @brief  Configures the timer DMA burst feature.
03645   * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
03646   *       not a timer instance supports the DMA burst mode.
03647   * @rmtoll DCR          DBL           LL_TIM_ConfigDMABurst\n
03648   *         DCR          DBA           LL_TIM_ConfigDMABurst
03649   * @param  TIMx Timer instance
03650   * @param  DMABurstBaseAddress This parameter can be one of the following values:
03651   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
03652   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
03653   *         @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
03654   *         @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
03655   *         @arg @ref LL_TIM_DMABURST_BASEADDR_SR
03656   *         @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
03657   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
03658   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
03659   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
03660   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
03661   *         @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
03662   *         @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
03663   *         @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
03664   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
03665   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
03666   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
03667   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
03668   *         @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
03669   *         @arg @ref LL_TIM_DMABURST_BASEADDR_OR
03670   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
03671   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
03672   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
03673   *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
03674   *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
03675   * @param  DMABurstLength This parameter can be one of the following values:
03676   *         @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
03677   *         @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
03678   *         @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
03679   *         @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
03680   *         @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
03681   *         @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
03682   *         @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
03683   *         @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
03684   *         @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
03685   *         @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
03686   *         @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
03687   *         @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
03688   *         @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
03689   *         @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
03690   *         @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
03691   *         @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
03692   *         @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
03693   *         @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
03694   * @retval None
03695   */
03696 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
03697 {
03698   MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
03699 }
03700
03701 /**
03702   * @}
03703   */
03704
03705 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
03706   * @{
03707   */
03708 /**
03709   * @brief  Remap TIM inputs (input channel, internal/external triggers).
03710   * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
03711   *       a some timer inputs can be remapped.
03712   * @rmtoll TIM1_OR    ETR_ADC1_RMP      LL_TIM_SetRemap\n
03713   *         TIM1_OR    TI1_RMP           LL_TIM_SetRemap\n
03714   *         TIM2_OR    ITR1_RMP          LL_TIM_SetRemap\n
03715   *         TIM2_OR    TI4_RMP           LL_TIM_SetRemap\n
03716   *         TIM2_OR    TI1_RMP           LL_TIM_SetRemap\n
03717   *         TIM16_OR   TI1_RMP           LL_TIM_SetRemap\n
03718   *         TIM17_OR   TI1_RMP           LL_TIM_SetRemap\n
03719   * @param  TIMx Timer instance
03720   * @param  Remap Remap param depends on the TIMx. Description available only
03721   *         in CHM version of the User Manual (not in .pdf).
03722   *         Otherwise see Reference Manual description of OR registers.
03723   *
03724   *         Below description summarizes "Timer Instance" and "Remap" param combinations:
03725   *
03726   *         TIM1: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where
03727   *
03728   *            . . ADC1_RMP can be one of the following values
03729   *            @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC
03730   *            @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1
03731   *            @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2
03732   *            @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3
03733   *
03734   *            . . TI1_RMP can be one of the following values
03735   *            @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO
03736   *            @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1 (*)
03737   *
03738   *         TIM2: any combination of ITR1_RMP, ETR1_RMP, TI4_RMP where
03739   *
03740   *            ITR1_RMP can be one of the following values
03741   *            @arg @ref LL_TIM_TIM2_ITR1_RMP_NONE
03742   *            @arg @ref LL_TIM_TIM2_ITR1_RMP_USB_SOF (*)
03743   *
03744   *            . . ETR1_RMP can be one of the following values
03745   *            @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO
03746   *            @arg @ref LL_TIM_TIM2_ETR_RMP_LSE
03747   *
03748   *            . . TI4_RMP can be one of the following values
03749   *            @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO
03750   *            @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1 (*)
03751   *            @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2 (*)
03752   *            @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (*)
03753   *
03754   *         TIM16: one of the following values
03755   *
03756   *            @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
03757   *            @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
03758   *            @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
03759   *            @arg @ref LL_TIM_TIM16_TI1_RMP_RTC
03760   *
03761   *         TIM17: one of the following values
03762   *
03763   *            @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO
03764   *            @arg @ref LL_TIM_TIM17_TI1_RMP_MSI
03765   *            @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32
03766   *            @arg @ref LL_TIM_TIM17_TI1_RMP_MCO
03767   *
03768   *         (*)  Value not defined in all devices. \n
03769   * @retval None
03770   */
03771 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
03772 {
03773   MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
03774 }
03775
03776 /**
03777   * @}
03778   */
03779
03780 /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
03781   * @{
03782   */
03783 /**
03784   * @brief  Set the OCREF clear input source
03785   * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
03786   * @note This function can only be used in Output compare and PWM modes.
03787   * @rmtoll SMCR          OCCS                LL_TIM_SetOCRefClearInputSource
03788   * @param  TIMx Timer instance
03789   * @param  OCRefClearInputSource This parameter can be one of the following values:
03790   *         @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR
03791   *         @arg @ref LL_TIM_OCREF_CLR_INT_ETR
03792   * @retval None
03793   */
03794 __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
03795 {
03796   MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
03797 }
03798 /**
03799   * @}
03800   */
03801
03802 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
03803   * @{
03804   */
03805 /**
03806   * @brief  Clear the update interrupt flag (UIF).
03807   * @rmtoll SR           UIF           LL_TIM_ClearFlag_UPDATE
03808   * @param  TIMx Timer instance
03809   * @retval None
03810   */
03811 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
03812 {
03813   WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
03814 }
03815
03816 /**
03817   * @brief  Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
03818   * @rmtoll SR           UIF           LL_TIM_IsActiveFlag_UPDATE
03819   * @param  TIMx Timer instance
03820   * @retval State of bit (1 or 0).
03821   */
03822 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
03823 {
03824   return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
03825 }
03826
03827 /**
03828   * @brief  Clear the Capture/Compare 1 interrupt flag (CC1F).
03829   * @rmtoll SR           CC1IF         LL_TIM_ClearFlag_CC1
03830   * @param  TIMx Timer instance
03831   * @retval None
03832   */
03833 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
03834 {
03835   WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
03836 }
03837
03838 /**
03839   * @brief  Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
03840   * @rmtoll SR           CC1IF         LL_TIM_IsActiveFlag_CC1
03841   * @param  TIMx Timer instance
03842   * @retval State of bit (1 or 0).
03843   */
03844 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
03845 {
03846   return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
03847 }
03848
03849 /**
03850   * @brief  Clear the Capture/Compare 2 interrupt flag (CC2F).
03851   * @rmtoll SR           CC2IF         LL_TIM_ClearFlag_CC2
03852   * @param  TIMx Timer instance
03853   * @retval None
03854   */
03855 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
03856 {
03857   WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
03858 }
03859
03860 /**
03861   * @brief  Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
03862   * @rmtoll SR           CC2IF         LL_TIM_IsActiveFlag_CC2
03863   * @param  TIMx Timer instance
03864   * @retval State of bit (1 or 0).
03865   */
03866 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
03867 {
03868   return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
03869 }
03870
03871 /**
03872   * @brief  Clear the Capture/Compare 3 interrupt flag (CC3F).
03873   * @rmtoll SR           CC3IF         LL_TIM_ClearFlag_CC3
03874   * @param  TIMx Timer instance
03875   * @retval None
03876   */
03877 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
03878 {
03879   WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
03880 }
03881
03882 /**
03883   * @brief  Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
03884   * @rmtoll SR           CC3IF         LL_TIM_IsActiveFlag_CC3
03885   * @param  TIMx Timer instance
03886   * @retval State of bit (1 or 0).
03887   */
03888 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
03889 {
03890   return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
03891 }
03892
03893 /**
03894   * @brief  Clear the Capture/Compare 4 interrupt flag (CC4F).
03895   * @rmtoll SR           CC4IF         LL_TIM_ClearFlag_CC4
03896   * @param  TIMx Timer instance
03897   * @retval None
03898   */
03899 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
03900 {
03901   WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
03902 }
03903
03904 /**
03905   * @brief  Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
03906   * @rmtoll SR           CC4IF         LL_TIM_IsActiveFlag_CC4
03907   * @param  TIMx Timer instance
03908   * @retval State of bit (1 or 0).
03909   */
03910 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
03911 {
03912   return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
03913 }
03914
03915 /**
03916   * @brief  Clear the Capture/Compare 5 interrupt flag (CC5F).
03917   * @rmtoll SR           CC5IF         LL_TIM_ClearFlag_CC5
03918   * @param  TIMx Timer instance
03919   * @retval None
03920   */
03921 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
03922 {
03923   WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
03924 }
03925
03926 /**
03927   * @brief  Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
03928   * @rmtoll SR           CC5IF         LL_TIM_IsActiveFlag_CC5
03929   * @param  TIMx Timer instance
03930   * @retval State of bit (1 or 0).
03931   */
03932 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx)
03933 {
03934   return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
03935 }
03936
03937 /**
03938   * @brief  Clear the Capture/Compare 6 interrupt flag (CC6F).
03939   * @rmtoll SR           CC6IF         LL_TIM_ClearFlag_CC6
03940   * @param  TIMx Timer instance
03941   * @retval None
03942   */
03943 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
03944 {
03945   WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
03946 }
03947
03948 /**
03949   * @brief  Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
03950   * @rmtoll SR           CC6IF         LL_TIM_IsActiveFlag_CC6
03951   * @param  TIMx Timer instance
03952   * @retval State of bit (1 or 0).
03953   */
03954 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx)
03955 {
03956   return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
03957 }
03958
03959 /**
03960   * @brief  Clear the commutation interrupt flag (COMIF).
03961   * @rmtoll SR           COMIF         LL_TIM_ClearFlag_COM
03962   * @param  TIMx Timer instance
03963   * @retval None
03964   */
03965 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
03966 {
03967   WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
03968 }
03969
03970 /**
03971   * @brief  Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
03972   * @rmtoll SR           COMIF         LL_TIM_IsActiveFlag_COM
03973   * @param  TIMx Timer instance
03974   * @retval State of bit (1 or 0).
03975   */
03976 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
03977 {
03978   return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
03979 }
03980
03981 /**
03982   * @brief  Clear the trigger interrupt flag (TIF).
03983   * @rmtoll SR           TIF           LL_TIM_ClearFlag_TRIG
03984   * @param  TIMx Timer instance
03985   * @retval None
03986   */
03987 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
03988 {
03989   WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
03990 }
03991
03992 /**
03993   * @brief  Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
03994   * @rmtoll SR           TIF           LL_TIM_IsActiveFlag_TRIG
03995   * @param  TIMx Timer instance
03996   * @retval State of bit (1 or 0).
03997   */
03998 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
03999 {
04000   return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
04001 }
04002
04003 /**
04004   * @brief  Clear the break interrupt flag (BIF).
04005   * @rmtoll SR           BIF           LL_TIM_ClearFlag_BRK
04006   * @param  TIMx Timer instance
04007   * @retval None
04008   */
04009 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
04010 {
04011   WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
04012 }
04013
04014 /**
04015   * @brief  Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
04016   * @rmtoll SR           BIF           LL_TIM_IsActiveFlag_BRK
04017   * @param  TIMx Timer instance
04018   * @retval State of bit (1 or 0).
04019   */
04020 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
04021 {
04022   return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
04023 }
04024
04025 /**
04026   * @brief  Clear the break 2 interrupt flag (B2IF).
04027   * @rmtoll SR           B2IF          LL_TIM_ClearFlag_BRK2
04028   * @param  TIMx Timer instance
04029   * @retval None
04030   */
04031 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
04032 {
04033   WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
04034 }
04035
04036 /**
04037   * @brief  Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
04038   * @rmtoll SR           B2IF          LL_TIM_IsActiveFlag_BRK2
04039   * @param  TIMx Timer instance
04040   * @retval State of bit (1 or 0).
04041   */
04042 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx)
04043 {
04044   return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
04045 }
04046
04047 /**
04048   * @brief  Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
04049   * @rmtoll SR           CC1OF         LL_TIM_ClearFlag_CC1OVR
04050   * @param  TIMx Timer instance
04051   * @retval None
04052   */
04053 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
04054 {
04055   WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
04056 }
04057
04058 /**
04059   * @brief  Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
04060   * @rmtoll SR           CC1OF         LL_TIM_IsActiveFlag_CC1OVR
04061   * @param  TIMx Timer instance
04062   * @retval State of bit (1 or 0).
04063   */
04064 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
04065 {
04066   return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
04067 }
04068
04069 /**
04070   * @brief  Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
04071   * @rmtoll SR           CC2OF         LL_TIM_ClearFlag_CC2OVR
04072   * @param  TIMx Timer instance
04073   * @retval None
04074   */
04075 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
04076 {
04077   WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
04078 }
04079
04080 /**
04081   * @brief  Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
04082   * @rmtoll SR           CC2OF         LL_TIM_IsActiveFlag_CC2OVR
04083   * @param  TIMx Timer instance
04084   * @retval State of bit (1 or 0).
04085   */
04086 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
04087 {
04088   return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
04089 }
04090
04091 /**
04092   * @brief  Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
04093   * @rmtoll SR           CC3OF         LL_TIM_ClearFlag_CC3OVR
04094   * @param  TIMx Timer instance
04095   * @retval None
04096   */
04097 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
04098 {
04099   WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
04100 }
04101
04102 /**
04103   * @brief  Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
04104   * @rmtoll SR           CC3OF         LL_TIM_IsActiveFlag_CC3OVR
04105   * @param  TIMx Timer instance
04106   * @retval State of bit (1 or 0).
04107   */
04108 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
04109 {
04110   return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
04111 }
04112
04113 /**
04114   * @brief  Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
04115   * @rmtoll SR           CC4OF         LL_TIM_ClearFlag_CC4OVR
04116   * @param  TIMx Timer instance
04117   * @retval None
04118   */
04119 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
04120 {
04121   WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
04122 }
04123
04124 /**
04125   * @brief  Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
04126   * @rmtoll SR           CC4OF         LL_TIM_IsActiveFlag_CC4OVR
04127   * @param  TIMx Timer instance
04128   * @retval State of bit (1 or 0).
04129   */
04130 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
04131 {
04132   return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
04133 }
04134
04135 /**
04136   * @brief  Clear the system break interrupt flag (SBIF).
04137   * @rmtoll SR           SBIF          LL_TIM_ClearFlag_SYSBRK
04138   * @param  TIMx Timer instance
04139   * @retval None
04140   */
04141 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
04142 {
04143   WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
04144 }
04145
04146 /**
04147   * @brief  Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
04148   * @rmtoll SR           SBIF          LL_TIM_IsActiveFlag_SYSBRK
04149   * @param  TIMx Timer instance
04150   * @retval State of bit (1 or 0).
04151   */
04152 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx)
04153 {
04154   return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
04155 }
04156
04157 /**
04158   * @}
04159   */
04160
04161 /** @defgroup TIM_LL_EF_IT_Management IT-Management
04162   * @{
04163   */
04164 /**
04165   * @brief  Enable update interrupt (UIE).
04166   * @rmtoll DIER         UIE           LL_TIM_EnableIT_UPDATE
04167   * @param  TIMx Timer instance
04168   * @retval None
04169   */
04170 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
04171 {
04172   SET_BIT(TIMx->DIER, TIM_DIER_UIE);
04173 }
04174
04175 /**
04176   * @brief  Disable update interrupt (UIE).
04177   * @rmtoll DIER         UIE           LL_TIM_DisableIT_UPDATE
04178   * @param  TIMx Timer instance
04179   * @retval None
04180   */
04181 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
04182 {
04183   CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
04184 }
04185
04186 /**
04187   * @brief  Indicates whether the update interrupt (UIE) is enabled.
04188   * @rmtoll DIER         UIE           LL_TIM_IsEnabledIT_UPDATE
04189   * @param  TIMx Timer instance
04190   * @retval State of bit (1 or 0).
04191   */
04192 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
04193 {
04194   return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
04195 }
04196
04197 /**
04198   * @brief  Enable capture/compare 1 interrupt (CC1IE).
04199   * @rmtoll DIER         CC1IE         LL_TIM_EnableIT_CC1
04200   * @param  TIMx Timer instance
04201   * @retval None
04202   */
04203 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
04204 {
04205   SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
04206 }
04207
04208 /**
04209   * @brief  Disable capture/compare 1  interrupt (CC1IE).
04210   * @rmtoll DIER         CC1IE         LL_TIM_DisableIT_CC1
04211   * @param  TIMx Timer instance
04212   * @retval None
04213   */
04214 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
04215 {
04216   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
04217 }
04218
04219 /**
04220   * @brief  Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
04221   * @rmtoll DIER         CC1IE         LL_TIM_IsEnabledIT_CC1
04222   * @param  TIMx Timer instance
04223   * @retval State of bit (1 or 0).
04224   */
04225 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
04226 {
04227   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
04228 }
04229
04230 /**
04231   * @brief  Enable capture/compare 2 interrupt (CC2IE).
04232   * @rmtoll DIER         CC2IE         LL_TIM_EnableIT_CC2
04233   * @param  TIMx Timer instance
04234   * @retval None
04235   */
04236 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
04237 {
04238   SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
04239 }
04240
04241 /**
04242   * @brief  Disable capture/compare 2  interrupt (CC2IE).
04243   * @rmtoll DIER         CC2IE         LL_TIM_DisableIT_CC2
04244   * @param  TIMx Timer instance
04245   * @retval None
04246   */
04247 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
04248 {
04249   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
04250 }
04251
04252 /**
04253   * @brief  Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
04254   * @rmtoll DIER         CC2IE         LL_TIM_IsEnabledIT_CC2
04255   * @param  TIMx Timer instance
04256   * @retval State of bit (1 or 0).
04257   */
04258 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
04259 {
04260   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
04261 }
04262
04263 /**
04264   * @brief  Enable capture/compare 3 interrupt (CC3IE).
04265   * @rmtoll DIER         CC3IE         LL_TIM_EnableIT_CC3
04266   * @param  TIMx Timer instance
04267   * @retval None
04268   */
04269 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
04270 {
04271   SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
04272 }
04273
04274 /**
04275   * @brief  Disable capture/compare 3  interrupt (CC3IE).
04276   * @rmtoll DIER         CC3IE         LL_TIM_DisableIT_CC3
04277   * @param  TIMx Timer instance
04278   * @retval None
04279   */
04280 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
04281 {
04282   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
04283 }
04284
04285 /**
04286   * @brief  Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
04287   * @rmtoll DIER         CC3IE         LL_TIM_IsEnabledIT_CC3
04288   * @param  TIMx Timer instance
04289   * @retval State of bit (1 or 0).
04290   */
04291 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
04292 {
04293   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
04294 }
04295
04296 /**
04297   * @brief  Enable capture/compare 4 interrupt (CC4IE).
04298   * @rmtoll DIER         CC4IE         LL_TIM_EnableIT_CC4
04299   * @param  TIMx Timer instance
04300   * @retval None
04301   */
04302 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
04303 {
04304   SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
04305 }
04306
04307 /**
04308   * @brief  Disable capture/compare 4  interrupt (CC4IE).
04309   * @rmtoll DIER         CC4IE         LL_TIM_DisableIT_CC4
04310   * @param  TIMx Timer instance
04311   * @retval None
04312   */
04313 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
04314 {
04315   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
04316 }
04317
04318 /**
04319   * @brief  Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
04320   * @rmtoll DIER         CC4IE         LL_TIM_IsEnabledIT_CC4
04321   * @param  TIMx Timer instance
04322   * @retval State of bit (1 or 0).
04323   */
04324 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
04325 {
04326   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
04327 }
04328
04329 /**
04330   * @brief  Enable commutation interrupt (COMIE).
04331   * @rmtoll DIER         COMIE         LL_TIM_EnableIT_COM
04332   * @param  TIMx Timer instance
04333   * @retval None
04334   */
04335 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
04336 {
04337   SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
04338 }
04339
04340 /**
04341   * @brief  Disable commutation interrupt (COMIE).
04342   * @rmtoll DIER         COMIE         LL_TIM_DisableIT_COM
04343   * @param  TIMx Timer instance
04344   * @retval None
04345   */
04346 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
04347 {
04348   CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
04349 }
04350
04351 /**
04352   * @brief  Indicates whether the commutation interrupt (COMIE) is enabled.
04353   * @rmtoll DIER         COMIE         LL_TIM_IsEnabledIT_COM
04354   * @param  TIMx Timer instance
04355   * @retval State of bit (1 or 0).
04356   */
04357 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
04358 {
04359   return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
04360 }
04361
04362 /**
04363   * @brief  Enable trigger interrupt (TIE).
04364   * @rmtoll DIER         TIE           LL_TIM_EnableIT_TRIG
04365   * @param  TIMx Timer instance
04366   * @retval None
04367   */
04368 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
04369 {
04370   SET_BIT(TIMx->DIER, TIM_DIER_TIE);
04371 }
04372
04373 /**
04374   * @brief  Disable trigger interrupt (TIE).
04375   * @rmtoll DIER         TIE           LL_TIM_DisableIT_TRIG
04376   * @param  TIMx Timer instance
04377   * @retval None
04378   */
04379 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
04380 {
04381   CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
04382 }
04383
04384 /**
04385   * @brief  Indicates whether the trigger interrupt (TIE) is enabled.
04386   * @rmtoll DIER         TIE           LL_TIM_IsEnabledIT_TRIG
04387   * @param  TIMx Timer instance
04388   * @retval State of bit (1 or 0).
04389   */
04390 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
04391 {
04392   return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
04393 }
04394
04395 /**
04396   * @brief  Enable break interrupt (BIE).
04397   * @rmtoll DIER         BIE           LL_TIM_EnableIT_BRK
04398   * @param  TIMx Timer instance
04399   * @retval None
04400   */
04401 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
04402 {
04403   SET_BIT(TIMx->DIER, TIM_DIER_BIE);
04404 }
04405
04406 /**
04407   * @brief  Disable break interrupt (BIE).
04408   * @rmtoll DIER         BIE           LL_TIM_DisableIT_BRK
04409   * @param  TIMx Timer instance
04410   * @retval None
04411   */
04412 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
04413 {
04414   CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
04415 }
04416
04417 /**
04418   * @brief  Indicates whether the break interrupt (BIE) is enabled.
04419   * @rmtoll DIER         BIE           LL_TIM_IsEnabledIT_BRK
04420   * @param  TIMx Timer instance
04421   * @retval State of bit (1 or 0).
04422   */
04423 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
04424 {
04425   return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
04426 }
04427
04428 /**
04429   * @}
04430   */
04431
04432 /** @defgroup TIM_LL_EF_DMA_Management DMA-Management
04433   * @{
04434   */
04435 /**
04436   * @brief  Enable update DMA request (UDE).
04437   * @rmtoll DIER         UDE           LL_TIM_EnableDMAReq_UPDATE
04438   * @param  TIMx Timer instance
04439   * @retval None
04440   */
04441 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
04442 {
04443   SET_BIT(TIMx->DIER, TIM_DIER_UDE);
04444 }
04445
04446 /**
04447   * @brief  Disable update DMA request (UDE).
04448   * @rmtoll DIER         UDE           LL_TIM_DisableDMAReq_UPDATE
04449   * @param  TIMx Timer instance
04450   * @retval None
04451   */
04452 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
04453 {
04454   CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
04455 }
04456
04457 /**
04458   * @brief  Indicates whether the update DMA request  (UDE) is enabled.
04459   * @rmtoll DIER         UDE           LL_TIM_IsEnabledDMAReq_UPDATE
04460   * @param  TIMx Timer instance
04461   * @retval State of bit (1 or 0).
04462   */
04463 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
04464 {
04465   return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
04466 }
04467
04468 /**
04469   * @brief  Enable capture/compare 1 DMA request (CC1DE).
04470   * @rmtoll DIER         CC1DE         LL_TIM_EnableDMAReq_CC1
04471   * @param  TIMx Timer instance
04472   * @retval None
04473   */
04474 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
04475 {
04476   SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
04477 }
04478
04479 /**
04480   * @brief  Disable capture/compare 1  DMA request (CC1DE).
04481   * @rmtoll DIER         CC1DE         LL_TIM_DisableDMAReq_CC1
04482   * @param  TIMx Timer instance
04483   * @retval None
04484   */
04485 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
04486 {
04487   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
04488 }
04489
04490 /**
04491   * @brief  Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
04492   * @rmtoll DIER         CC1DE         LL_TIM_IsEnabledDMAReq_CC1
04493   * @param  TIMx Timer instance
04494   * @retval State of bit (1 or 0).
04495   */
04496 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
04497 {
04498   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
04499 }
04500
04501 /**
04502   * @brief  Enable capture/compare 2 DMA request (CC2DE).
04503   * @rmtoll DIER         CC2DE         LL_TIM_EnableDMAReq_CC2
04504   * @param  TIMx Timer instance
04505   * @retval None
04506   */
04507 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
04508 {
04509   SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
04510 }
04511
04512 /**
04513   * @brief  Disable capture/compare 2  DMA request (CC2DE).
04514   * @rmtoll DIER         CC2DE         LL_TIM_DisableDMAReq_CC2
04515   * @param  TIMx Timer instance
04516   * @retval None
04517   */
04518 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
04519 {
04520   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
04521 }
04522
04523 /**
04524   * @brief  Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
04525   * @rmtoll DIER         CC2DE         LL_TIM_IsEnabledDMAReq_CC2
04526   * @param  TIMx Timer instance
04527   * @retval State of bit (1 or 0).
04528   */
04529 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
04530 {
04531   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
04532 }
04533
04534 /**
04535   * @brief  Enable capture/compare 3 DMA request (CC3DE).
04536   * @rmtoll DIER         CC3DE         LL_TIM_EnableDMAReq_CC3
04537   * @param  TIMx Timer instance
04538   * @retval None
04539   */
04540 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
04541 {
04542   SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
04543 }
04544
04545 /**
04546   * @brief  Disable capture/compare 3  DMA request (CC3DE).
04547   * @rmtoll DIER         CC3DE         LL_TIM_DisableDMAReq_CC3
04548   * @param  TIMx Timer instance
04549   * @retval None
04550   */
04551 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
04552 {
04553   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
04554 }
04555
04556 /**
04557   * @brief  Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
04558   * @rmtoll DIER         CC3DE         LL_TIM_IsEnabledDMAReq_CC3
04559   * @param  TIMx Timer instance
04560   * @retval State of bit (1 or 0).
04561   */
04562 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
04563 {
04564   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
04565 }
04566
04567 /**
04568   * @brief  Enable capture/compare 4 DMA request (CC4DE).
04569   * @rmtoll DIER         CC4DE         LL_TIM_EnableDMAReq_CC4
04570   * @param  TIMx Timer instance
04571   * @retval None
04572   */
04573 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
04574 {
04575   SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
04576 }
04577
04578 /**
04579   * @brief  Disable capture/compare 4  DMA request (CC4DE).
04580   * @rmtoll DIER         CC4DE         LL_TIM_DisableDMAReq_CC4
04581   * @param  TIMx Timer instance
04582   * @retval None
04583   */
04584 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
04585 {
04586   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
04587 }
04588
04589 /**
04590   * @brief  Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
04591   * @rmtoll DIER         CC4DE         LL_TIM_IsEnabledDMAReq_CC4
04592   * @param  TIMx Timer instance
04593   * @retval State of bit (1 or 0).
04594   */
04595 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
04596 {
04597   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
04598 }
04599
04600 /**
04601   * @brief  Enable commutation DMA request (COMDE).
04602   * @rmtoll DIER         COMDE         LL_TIM_EnableDMAReq_COM
04603   * @param  TIMx Timer instance
04604   * @retval None
04605   */
04606 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
04607 {
04608   SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
04609 }
04610
04611 /**
04612   * @brief  Disable commutation DMA request (COMDE).
04613   * @rmtoll DIER         COMDE         LL_TIM_DisableDMAReq_COM
04614   * @param  TIMx Timer instance
04615   * @retval None
04616   */
04617 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
04618 {
04619   CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
04620 }
04621
04622 /**
04623   * @brief  Indicates whether the commutation DMA request (COMDE) is enabled.
04624   * @rmtoll DIER         COMDE         LL_TIM_IsEnabledDMAReq_COM
04625   * @param  TIMx Timer instance
04626   * @retval State of bit (1 or 0).
04627   */
04628 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
04629 {
04630   return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
04631 }
04632
04633 /**
04634   * @brief  Enable trigger interrupt (TDE).
04635   * @rmtoll DIER         TDE           LL_TIM_EnableDMAReq_TRIG
04636   * @param  TIMx Timer instance
04637   * @retval None
04638   */
04639 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
04640 {
04641   SET_BIT(TIMx->DIER, TIM_DIER_TDE);
04642 }
04643
04644 /**
04645   * @brief  Disable trigger interrupt (TDE).
04646   * @rmtoll DIER         TDE           LL_TIM_DisableDMAReq_TRIG
04647   * @param  TIMx Timer instance
04648   * @retval None
04649   */
04650 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
04651 {
04652   CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
04653 }
04654
04655 /**
04656   * @brief  Indicates whether the trigger interrupt (TDE) is enabled.
04657   * @rmtoll DIER         TDE           LL_TIM_IsEnabledDMAReq_TRIG
04658   * @param  TIMx Timer instance
04659   * @retval State of bit (1 or 0).
04660   */
04661 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
04662 {
04663   return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
04664 }
04665
04666 /**
04667   * @}
04668   */
04669
04670 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
04671   * @{
04672   */
04673 /**
04674   * @brief  Generate an update event.
04675   * @rmtoll EGR          UG            LL_TIM_GenerateEvent_UPDATE
04676   * @param  TIMx Timer instance
04677   * @retval None
04678   */
04679 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
04680 {
04681   SET_BIT(TIMx->EGR, TIM_EGR_UG);
04682 }
04683
04684 /**
04685   * @brief  Generate Capture/Compare 1 event.
04686   * @rmtoll EGR          CC1G          LL_TIM_GenerateEvent_CC1
04687   * @param  TIMx Timer instance
04688   * @retval None
04689   */
04690 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
04691 {
04692   SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
04693 }
04694
04695 /**
04696   * @brief  Generate Capture/Compare 2 event.
04697   * @rmtoll EGR          CC2G          LL_TIM_GenerateEvent_CC2
04698   * @param  TIMx Timer instance
04699   * @retval None
04700   */
04701 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
04702 {
04703   SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
04704 }
04705
04706 /**
04707   * @brief  Generate Capture/Compare 3 event.
04708   * @rmtoll EGR          CC3G          LL_TIM_GenerateEvent_CC3
04709   * @param  TIMx Timer instance
04710   * @retval None
04711   */
04712 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
04713 {
04714   SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
04715 }
04716
04717 /**
04718   * @brief  Generate Capture/Compare 4 event.
04719   * @rmtoll EGR          CC4G          LL_TIM_GenerateEvent_CC4
04720   * @param  TIMx Timer instance
04721   * @retval None
04722   */
04723 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
04724 {
04725   SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
04726 }
04727
04728 /**
04729   * @brief  Generate commutation event.
04730   * @rmtoll EGR          COMG          LL_TIM_GenerateEvent_COM
04731   * @param  TIMx Timer instance
04732   * @retval None
04733   */
04734 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
04735 {
04736   SET_BIT(TIMx->EGR, TIM_EGR_COMG);
04737 }
04738
04739 /**
04740   * @brief  Generate trigger event.
04741   * @rmtoll EGR          TG            LL_TIM_GenerateEvent_TRIG
04742   * @param  TIMx Timer instance
04743   * @retval None
04744   */
04745 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
04746 {
04747   SET_BIT(TIMx->EGR, TIM_EGR_TG);
04748 }
04749
04750 /**
04751   * @brief  Generate break event.
04752   * @rmtoll EGR          BG            LL_TIM_GenerateEvent_BRK
04753   * @param  TIMx Timer instance
04754   * @retval None
04755   */
04756 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
04757 {
04758   SET_BIT(TIMx->EGR, TIM_EGR_BG);
04759 }
04760
04761 /**
04762   * @brief  Generate break 2 event.
04763   * @rmtoll EGR          B2G           LL_TIM_GenerateEvent_BRK2
04764   * @param  TIMx Timer instance
04765   * @retval None
04766   */
04767 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
04768 {
04769   SET_BIT(TIMx->EGR, TIM_EGR_B2G);
04770 }
04771
04772 /**
04773   * @}
04774   */
04775
04776 #if defined(USE_FULL_LL_DRIVER)
04777 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
04778   * @{
04779   */
04780
04781 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
04782 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
04783 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
04784 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
04785 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
04786 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
04787 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
04788 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
04789 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
04790 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
04791 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
04792 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
04793 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
04794 /**
04795   * @}
04796   */
04797 #endif /* USE_FULL_LL_DRIVER */
04798
04799 /**
04800   * @}
04801   */
04802
04803 /**
04804   * @}
04805   */
04806
04807 #endif /* TIM1 || TIM2 || TIM16 || TIM17 */
04808
04809 /**
04810   * @}
04811   */
04812
04813 #ifdef __cplusplus
04814 }
04815 #endif
04816
04817 #endif /* __STM32WBxx_LL_TIM_H */
04818 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_usart.c Source File

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stm32wbxx_ll_usart.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_usart.c
00004   * @author  MCD Application Team
00005   * @brief   USART LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 #if defined(USE_FULL_LL_DRIVER)
00020
00021 /* Includes ------------------------------------------------------------------*/
00022 #include "stm32wbxx_ll_usart.h"
00023 #include "stm32wbxx_ll_rcc.h"
00024 #include "stm32wbxx_ll_bus.h"
00025 #ifdef  USE_FULL_ASSERT
00026 #include "stm32_assert.h"
00027 #else
00028 #define assert_param(expr) ((void)0U)
00029 #endif
00030
00031 /** @addtogroup STM32WBxx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (USART1)
00036
00037 /** @addtogroup USART_LL
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /** @addtogroup USART_LL_Private_Constants
00045   * @{
00046   */
00047
00048 /**
00049   * @}
00050   */
00051
00052
00053 /* Private macros ------------------------------------------------------------*/
00054 /** @addtogroup USART_LL_Private_Macros
00055   * @{
00056   */
00057
00058 #define IS_LL_USART_PRESCALER(__VALUE__)  (((__VALUE__) == LL_USART_PRESCALER_DIV1) \
00059                                         || ((__VALUE__) == LL_USART_PRESCALER_DIV2) \
00060                                         || ((__VALUE__) == LL_USART_PRESCALER_DIV4) \
00061                                         || ((__VALUE__) == LL_USART_PRESCALER_DIV6) \
00062                                         || ((__VALUE__) == LL_USART_PRESCALER_DIV8) \
00063                                         || ((__VALUE__) == LL_USART_PRESCALER_DIV10) \
00064                                         || ((__VALUE__) == LL_USART_PRESCALER_DIV12) \
00065                                         || ((__VALUE__) == LL_USART_PRESCALER_DIV16) \
00066                                         || ((__VALUE__) == LL_USART_PRESCALER_DIV32) \
00067                                         || ((__VALUE__) == LL_USART_PRESCALER_DIV64) \
00068                                         || ((__VALUE__) == LL_USART_PRESCALER_DIV128) \
00069                                         || ((__VALUE__) == LL_USART_PRESCALER_DIV256))
00070
00071 /* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
00072  *              divided by the smallest oversampling used on the USART (i.e. 8)    */
00073 #define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 8000000U)
00074
00075 /* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
00076 #define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
00077
00078 /* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */
00079 #define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
00080
00081 #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
00082                                        || ((__VALUE__) == LL_USART_DIRECTION_RX) \
00083                                        || ((__VALUE__) == LL_USART_DIRECTION_TX) \
00084                                        || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
00085
00086 #define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
00087                                     || ((__VALUE__) == LL_USART_PARITY_EVEN) \
00088                                     || ((__VALUE__) == LL_USART_PARITY_ODD))
00089
00090 #define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \
00091                                        || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
00092                                        || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
00093
00094 #define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
00095                                           || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
00096
00097 #define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
00098                                               || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
00099
00100 #define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
00101                                         || ((__VALUE__) == LL_USART_PHASE_2EDGE))
00102
00103 #define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
00104                                            || ((__VALUE__) == LL_USART_POLARITY_HIGH))
00105
00106 #define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
00107                                          || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
00108
00109 #define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
00110                                       || ((__VALUE__) == LL_USART_STOPBITS_1) \
00111                                       || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
00112                                       || ((__VALUE__) == LL_USART_STOPBITS_2))
00113
00114 #define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
00115                                        || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
00116                                        || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
00117                                        || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
00118
00119 /**
00120   * @}
00121   */
00122
00123 /* Private function prototypes -----------------------------------------------*/
00124
00125 /* Exported functions --------------------------------------------------------*/
00126 /** @addtogroup USART_LL_Exported_Functions
00127   * @{
00128   */
00129
00130 /** @addtogroup USART_LL_EF_Init
00131   * @{
00132   */
00133
00134 /**
00135   * @brief  De-initialize USART registers (Registers restored to their default values).
00136   * @param  USARTx USART Instance
00137   * @retval An ErrorStatus enumeration value:
00138   *          - SUCCESS: USART registers are de-initialized
00139   *          - ERROR: USART registers are not de-initialized
00140   */
00141 ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
00142 {
00143   ErrorStatus status = SUCCESS;
00144
00145   /* Check the parameters */
00146   assert_param(IS_UART_INSTANCE(USARTx));
00147
00148   if (USARTx == USART1)
00149   {
00150     /* Force reset of USART clock */
00151     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
00152
00153     /* Release reset of USART clock */
00154     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
00155   }
00156   else
00157   {
00158     status = ERROR;
00159   }
00160
00161   return (status);
00162 }
00163
00164 /**
00165   * @brief  Initialize USART registers according to the specified
00166   *         parameters in USART_InitStruct.
00167   * @note   As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
00168   *         USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
00169   * @note   Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
00170   * @param  USARTx USART Instance
00171   * @param  USART_InitStruct pointer to a LL_USART_InitTypeDef structure
00172   *         that contains the configuration information for the specified USART peripheral.
00173   * @retval An ErrorStatus enumeration value:
00174   *          - SUCCESS: USART registers are initialized according to USART_InitStruct content
00175   *          - ERROR: Problem occurred during USART Registers initialization
00176   */
00177 ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
00178 {
00179   ErrorStatus status = ERROR;
00180   uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
00181
00182   /* Check the parameters */
00183   assert_param(IS_UART_INSTANCE(USARTx));
00184   assert_param(IS_LL_USART_PRESCALER(USART_InitStruct->PrescalerValue));
00185   assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
00186   assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
00187   assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
00188   assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
00189   assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
00190   assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
00191   assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
00192
00193   /* USART needs to be in disabled state, in order to be able to configure some bits in
00194      CRx registers */
00195   if (LL_USART_IsEnabled(USARTx) == 0U)
00196   {
00197     /*---------------------------- USART CR1 Configuration ---------------------
00198      * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
00199      * - DataWidth:          USART_CR1_M bits according to USART_InitStruct->DataWidth value
00200      * - Parity:             USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
00201      * - TransferDirection:  USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
00202      * - Oversampling:       USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
00203      */
00204     MODIFY_REG(USARTx->CR1,
00205                (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
00206                 USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
00207                (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
00208                 USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
00209
00210     /*---------------------------- USART CR2 Configuration ---------------------
00211      * Configure USARTx CR2 (Stop bits) with parameters:
00212      * - Stop Bits:          USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
00213      * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
00214      */
00215     LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
00216
00217     /*---------------------------- USART CR3 Configuration ---------------------
00218      * Configure USARTx CR3 (Hardware Flow Control) with parameters:
00219      * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
00220      */
00221     LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
00222
00223     /*---------------------------- USART BRR Configuration ---------------------
00224      * Retrieve Clock frequency used for USART Peripheral
00225      */
00226     if (USARTx == USART1)
00227     {
00228       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART1_CLKSOURCE);
00229     }
00230     else
00231     {
00232       /* Nothing to do, as error code is already assigned to ERROR value */
00233     }
00234
00235     /* Configure the USART Baud Rate :
00236        - prescaler value is required
00237        - valid baud rate value (different from 0) is required
00238        - Peripheral clock as returned by RCC service, should be valid (different from 0).
00239     */
00240     if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
00241         && (USART_InitStruct->BaudRate != 0U))
00242     {
00243       status = SUCCESS;
00244       LL_USART_SetBaudRate(USARTx,
00245                            periphclk,
00246                            USART_InitStruct->PrescalerValue,
00247                            USART_InitStruct->OverSampling,
00248                            USART_InitStruct->BaudRate);
00249
00250       /* Check BRR is greater than or equal to 16d */
00251       assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
00252
00253       /* Check BRR is lower than or equal to 0xFFFF */
00254       assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR));
00255     }
00256
00257     /*---------------------------- USART PRESC Configuration -----------------------
00258      * Configure USARTx PRESC (Prescaler) with parameters:
00259      * - PrescalerValue: USART_PRESC_PRESCALER bits according to USART_InitStruct->PrescalerValue value.
00260      */
00261     LL_USART_SetPrescaler(USARTx, USART_InitStruct->PrescalerValue);
00262   }
00263   /* Endif (=> USART not in Disabled state => return ERROR) */
00264
00265   return (status);
00266 }
00267
00268 /**
00269   * @brief Set each @ref LL_USART_InitTypeDef field to default value.
00270   * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
00271   *                         whose fields will be set to default values.
00272   * @retval None
00273   */
00274
00275 void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
00276 {
00277   /* Set USART_InitStruct fields to default values */
00278   USART_InitStruct->PrescalerValue      = LL_USART_PRESCALER_DIV1;
00279   USART_InitStruct->BaudRate            = 9600U;
00280   USART_InitStruct->DataWidth           = LL_USART_DATAWIDTH_8B;
00281   USART_InitStruct->StopBits            = LL_USART_STOPBITS_1;
00282   USART_InitStruct->Parity              = LL_USART_PARITY_NONE ;
00283   USART_InitStruct->TransferDirection   = LL_USART_DIRECTION_TX_RX;
00284   USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
00285   USART_InitStruct->OverSampling        = LL_USART_OVERSAMPLING_16;
00286 }
00287
00288 /**
00289   * @brief  Initialize USART Clock related settings according to the
00290   *         specified parameters in the USART_ClockInitStruct.
00291   * @note   As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
00292   *         USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
00293   * @param  USARTx USART Instance
00294   * @param  USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
00295   *         that contains the Clock configuration information for the specified USART peripheral.
00296   * @retval An ErrorStatus enumeration value:
00297   *          - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
00298   *          - ERROR: Problem occurred during USART Registers initialization
00299   */
00300 ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
00301 {
00302   ErrorStatus status = SUCCESS;
00303
00304   /* Check USART Instance and Clock signal output parameters */
00305   assert_param(IS_UART_INSTANCE(USARTx));
00306   assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
00307
00308   /* USART needs to be in disabled state, in order to be able to configure some bits in
00309      CRx registers */
00310   if (LL_USART_IsEnabled(USARTx) == 0U)
00311   {
00312     /*---------------------------- USART CR2 Configuration -----------------------*/
00313     /* If Clock signal has to be output */
00314     if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
00315     {
00316       /* Deactivate Clock signal delivery :
00317        * - Disable Clock Output:        USART_CR2_CLKEN cleared
00318        */
00319       LL_USART_DisableSCLKOutput(USARTx);
00320     }
00321     else
00322     {
00323       /* Ensure USART instance is USART capable */
00324       assert_param(IS_USART_INSTANCE(USARTx));
00325
00326       /* Check clock related parameters */
00327       assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
00328       assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
00329       assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
00330
00331       /*---------------------------- USART CR2 Configuration -----------------------
00332        * Configure USARTx CR2 (Clock signal related bits) with parameters:
00333        * - Enable Clock Output:         USART_CR2_CLKEN set
00334        * - Clock Polarity:              USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
00335        * - Clock Phase:                 USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
00336        * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
00337        */
00338       MODIFY_REG(USARTx->CR2,
00339                  USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
00340                  USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
00341                  USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
00342     }
00343   }
00344   /* Else (USART not in Disabled state => return ERROR */
00345   else
00346   {
00347     status = ERROR;
00348   }
00349
00350   return (status);
00351 }
00352
00353 /**
00354   * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
00355   * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
00356   *                              whose fields will be set to default values.
00357   * @retval None
00358   */
00359 void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
00360 {
00361   /* Set LL_USART_ClockInitStruct fields with default values */
00362   USART_ClockInitStruct->ClockOutput       = LL_USART_CLOCK_DISABLE;
00363   USART_ClockInitStruct->ClockPolarity     = LL_USART_POLARITY_LOW;            /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
00364   USART_ClockInitStruct->ClockPhase        = LL_USART_PHASE_1EDGE;             /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
00365   USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT;  /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
00366 }
00367
00368 /**
00369   * @}
00370   */
00371
00372 /**
00373   * @}
00374   */
00375
00376 /**
00377   * @}
00378   */
00379
00380 #endif /* USART1 */
00381
00382 /**
00383   * @}
00384   */
00385
00386 #endif /* USE_FULL_LL_DRIVER */
00387
00388 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00389
Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_usart.h Source File

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stm32wbxx_ll_usart.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_usart.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of USART LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_LL_USART_H
00022 #define STM32WBxx_LL_USART_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx.h"
00030
00031 /** @addtogroup STM32WBxx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (USART1)
00036
00037 /** @defgroup USART_LL USART
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /** @defgroup USART_LL_Private_Variables USART Private Variables
00044   * @{
00045   */
00046 /* Array used to get the USART prescaler division decimal values versus @ref USART_LL_EC_PRESCALER values */
00047 static const uint16_t USART_PRESCALER_TAB[] =
00048 {
00049   (uint16_t)1,
00050   (uint16_t)2,
00051   (uint16_t)4,
00052   (uint16_t)6,
00053   (uint16_t)8,
00054   (uint16_t)10,
00055   (uint16_t)12,
00056   (uint16_t)16,
00057   (uint16_t)32,
00058   (uint16_t)64,
00059   (uint16_t)128,
00060   (uint16_t)256
00061 };
00062 /**
00063   * @}
00064   */
00065
00066 /* Private constants ---------------------------------------------------------*/
00067 /** @defgroup USART_LL_Private_Constants USART Private Constants
00068   * @{
00069   */
00070 /**
00071   * @}
00072   */
00073
00074 /* Private macros ------------------------------------------------------------*/
00075 #if defined(USE_FULL_LL_DRIVER)
00076 /** @defgroup USART_LL_Private_Macros USART Private Macros
00077   * @{
00078   */
00079 /**
00080   * @}
00081   */
00082 #endif /*USE_FULL_LL_DRIVER*/
00083
00084 /* Exported types ------------------------------------------------------------*/
00085 #if defined(USE_FULL_LL_DRIVER)
00086 /** @defgroup USART_LL_ES_INIT USART Exported Init structures
00087   * @{
00088   */
00089
00090 /**
00091   * @brief LL USART Init Structure definition
00092   */
00093 typedef struct
00094 {
00095   uint32_t PrescalerValue;            /*!< Specifies the Prescaler to compute the communication baud rate.
00096                                            This parameter can be a value of @ref USART_LL_EC_PRESCALER.
00097
00098                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetPrescaler().*/
00099
00100   uint32_t BaudRate;                  /*!< This field defines expected Usart communication baud rate.
00101
00102                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/
00103
00104   uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
00105                                            This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
00106
00107                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/
00108
00109   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
00110                                            This parameter can be a value of @ref USART_LL_EC_STOPBITS.
00111
00112                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/
00113
00114   uint32_t Parity;                    /*!< Specifies the parity mode.
00115                                            This parameter can be a value of @ref USART_LL_EC_PARITY.
00116
00117                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/
00118
00119   uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
00120                                            This parameter can be a value of @ref USART_LL_EC_DIRECTION.
00121
00122                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/
00123
00124   uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
00125                                            This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
00126
00127                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/
00128
00129   uint32_t OverSampling;              /*!< Specifies whether USART oversampling mode is 16 or 8.
00130                                            This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
00131
00132                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/
00133
00134 } LL_USART_InitTypeDef;
00135
00136 /**
00137   * @brief LL USART Clock Init Structure definition
00138   */
00139 typedef struct
00140 {
00141   uint32_t ClockOutput;               /*!< Specifies whether the USART clock is enabled or disabled.
00142                                            This parameter can be a value of @ref USART_LL_EC_CLOCK.
00143
00144                                            USART HW configuration can be modified afterwards using unitary functions
00145                                            @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().
00146                                            For more details, refer to description of this function. */
00147
00148   uint32_t ClockPolarity;             /*!< Specifies the steady state of the serial clock.
00149                                            This parameter can be a value of @ref USART_LL_EC_POLARITY.
00150
00151                                            USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity().
00152                                            For more details, refer to description of this function. */
00153
00154   uint32_t ClockPhase;                /*!< Specifies the clock transition on which the bit capture is made.
00155                                            This parameter can be a value of @ref USART_LL_EC_PHASE.
00156
00157                                            USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase().
00158                                            For more details, refer to description of this function. */
00159
00160   uint32_t LastBitClockPulse;         /*!< Specifies whether the clock pulse corresponding to the last transmitted
00161                                            data bit (MSB) has to be output on the SCLK pin in synchronous mode.
00162                                            This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
00163
00164                                            USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput().
00165                                            For more details, refer to description of this function. */
00166
00167 } LL_USART_ClockInitTypeDef;
00168
00169 /**
00170   * @}
00171   */
00172 #endif /* USE_FULL_LL_DRIVER */
00173
00174 /* Exported constants --------------------------------------------------------*/
00175 /** @defgroup USART_LL_Exported_Constants USART Exported Constants
00176   * @{
00177   */
00178
00179 /** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines
00180   * @brief    Flags defines which can be used with LL_USART_WriteReg function
00181   * @{
00182   */
00183 #define LL_USART_ICR_PECF                       USART_ICR_PECF                /*!< Parity error flag */
00184 #define LL_USART_ICR_FECF                       USART_ICR_FECF                /*!< Framing error flag */
00185 #define LL_USART_ICR_NECF                       USART_ICR_NECF                /*!< Noise error detected flag */
00186 #define LL_USART_ICR_ORECF                      USART_ICR_ORECF               /*!< Overrun error flag */
00187 #define LL_USART_ICR_IDLECF                     USART_ICR_IDLECF              /*!< Idle line detected flag */
00188 #define LL_USART_ICR_TXFECF                     USART_ICR_TXFECF              /*!< TX FIFO Empty Clear flag */
00189 #define LL_USART_ICR_TCCF                       USART_ICR_TCCF                /*!< Transmission complete flag */
00190 #define LL_USART_ICR_TCBGTCF                    USART_ICR_TCBGTCF             /*!< Transmission completed before guard time flag */
00191 #define LL_USART_ICR_LBDCF                      USART_ICR_LBDCF               /*!< LIN break detection flag */
00192 #define LL_USART_ICR_CTSCF                      USART_ICR_CTSCF               /*!< CTS flag */
00193 #define LL_USART_ICR_RTOCF                      USART_ICR_RTOCF               /*!< Receiver timeout flag */
00194 #define LL_USART_ICR_EOBCF                      USART_ICR_EOBCF               /*!< End of block flag */
00195 #define LL_USART_ICR_UDRCF                      USART_ICR_UDRCF               /*!< SPI Slave Underrun Clear flag */
00196 #define LL_USART_ICR_CMCF                       USART_ICR_CMCF                /*!< Character match flag */
00197 #define LL_USART_ICR_WUCF                       USART_ICR_WUCF                /*!< Wakeup from Stop mode flag */
00198 /**
00199   * @}
00200   */
00201
00202 /** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
00203   * @brief    Flags defines which can be used with LL_USART_ReadReg function
00204   * @{
00205   */
00206 #define LL_USART_ISR_PE                         USART_ISR_PE                  /*!< Parity error flag */
00207 #define LL_USART_ISR_FE                         USART_ISR_FE                  /*!< Framing error flag */
00208 #define LL_USART_ISR_NE                         USART_ISR_NE                  /*!< Noise detected flag */
00209 #define LL_USART_ISR_ORE                        USART_ISR_ORE                 /*!< Overrun error flag */
00210 #define LL_USART_ISR_IDLE                       USART_ISR_IDLE                /*!< Idle line detected flag */
00211 #define LL_USART_ISR_RXNE_RXFNE                 USART_ISR_RXNE_RXFNE          /*!< Read data register or RX FIFO not empty flag */
00212 #define LL_USART_ISR_TC                         USART_ISR_TC                  /*!< Transmission complete flag */
00213 #define LL_USART_ISR_TXE_TXFNF                  USART_ISR_TXE_TXFNF           /*!< Transmit data register empty or TX FIFO Not Full flag*/
00214 #define LL_USART_ISR_LBDF                       USART_ISR_LBDF                /*!< LIN break detection flag */
00215 #define LL_USART_ISR_CTSIF                      USART_ISR_CTSIF               /*!< CTS interrupt flag */
00216 #define LL_USART_ISR_CTS                        USART_ISR_CTS                 /*!< CTS flag */
00217 #define LL_USART_ISR_RTOF                       USART_ISR_RTOF                /*!< Receiver timeout flag */
00218 #define LL_USART_ISR_EOBF                       USART_ISR_EOBF                /*!< End of block flag */
00219 #define LL_USART_ISR_UDR                        USART_ISR_UDR                 /*!< SPI Slave underrun error flag */
00220 #define LL_USART_ISR_ABRE                       USART_ISR_ABRE                /*!< Auto baud rate error flag */
00221 #define LL_USART_ISR_ABRF                       USART_ISR_ABRF                /*!< Auto baud rate flag */
00222 #define LL_USART_ISR_BUSY                       USART_ISR_BUSY                /*!< Busy flag */
00223 #define LL_USART_ISR_CMF                        USART_ISR_CMF                 /*!< Character match flag */
00224 #define LL_USART_ISR_SBKF                       USART_ISR_SBKF                /*!< Send break flag */
00225 #define LL_USART_ISR_RWU                        USART_ISR_RWU                 /*!< Receiver wakeup from Mute mode flag */
00226 #define LL_USART_ISR_WUF                        USART_ISR_WUF                 /*!< Wakeup from Stop mode flag */
00227 #define LL_USART_ISR_TEACK                      USART_ISR_TEACK               /*!< Transmit enable acknowledge flag */
00228 #define LL_USART_ISR_REACK                      USART_ISR_REACK               /*!< Receive enable acknowledge flag */
00229 #define LL_USART_ISR_TXFE                       USART_ISR_TXFE                /*!< TX FIFO empty flag */
00230 #define LL_USART_ISR_RXFF                       USART_ISR_RXFF                /*!< RX FIFO full flag */
00231 #define LL_USART_ISR_TCBGT                      USART_ISR_TCBGT               /*!< Transmission complete before guard time completion flag */
00232 #define LL_USART_ISR_RXFT                       USART_ISR_RXFT                /*!< RX FIFO threshold flag */
00233 #define LL_USART_ISR_TXFT                       USART_ISR_TXFT                /*!< TX FIFO threshold flag */
00234 /**
00235   * @}
00236   */
00237
00238 /** @defgroup USART_LL_EC_IT IT Defines
00239   * @brief    IT defines which can be used with LL_USART_ReadReg and  LL_USART_WriteReg functions
00240   * @{
00241   */
00242 #define LL_USART_CR1_IDLEIE                     USART_CR1_IDLEIE              /*!< IDLE interrupt enable */
00243 #define LL_USART_CR1_RXNEIE_RXFNEIE             USART_CR1_RXNEIE_RXFNEIE      /*!< Read data register and RXFIFO not empty interrupt enable */
00244 #define LL_USART_CR1_TCIE                       USART_CR1_TCIE                /*!< Transmission complete interrupt enable */
00245 #define LL_USART_CR1_TXEIE_TXFNFIE              USART_CR1_TXEIE_TXFNFIE       /*!< Transmit data register empty and TX FIFO not full interrupt enable */
00246 #define LL_USART_CR1_PEIE                       USART_CR1_PEIE                /*!< Parity error */
00247 #define LL_USART_CR1_CMIE                       USART_CR1_CMIE                /*!< Character match interrupt enable */
00248 #define LL_USART_CR1_RTOIE                      USART_CR1_RTOIE               /*!< Receiver timeout interrupt enable */
00249 #define LL_USART_CR1_EOBIE                      USART_CR1_EOBIE               /*!< End of Block interrupt enable */
00250 #define LL_USART_CR1_TXFEIE                     USART_CR1_TXFEIE              /*!< TX FIFO empty interrupt enable */
00251 #define LL_USART_CR1_RXFFIE                     USART_CR1_RXFFIE              /*!< RX FIFO full interrupt enable */
00252 #define LL_USART_CR2_LBDIE                      USART_CR2_LBDIE               /*!< LIN break detection interrupt enable */
00253 #define LL_USART_CR3_EIE                        USART_CR3_EIE                 /*!< Error interrupt enable */
00254 #define LL_USART_CR3_CTSIE                      USART_CR3_CTSIE               /*!< CTS interrupt enable */
00255 #define LL_USART_CR3_WUFIE                      USART_CR3_WUFIE               /*!< Wakeup from Stop mode interrupt enable */
00256 #define LL_USART_CR3_TXFTIE                     USART_CR3_TXFTIE              /*!< TX FIFO threshold interrupt enable */
00257 #define LL_USART_CR3_TCBGTIE                    USART_CR3_TCBGTIE             /*!< Transmission complete before guard time interrupt enable */
00258 #define LL_USART_CR3_RXFTIE                     USART_CR3_RXFTIE              /*!< RX FIFO threshold interrupt enable */
00259 /**
00260   * @}
00261   */
00262
00263 /** @defgroup USART_LL_EC_FIFOTHRESHOLD FIFO Threshold
00264   * @{
00265   */
00266 #define LL_USART_FIFOTHRESHOLD_1_8              0x00000000U /*!< FIFO reaches 1/8 of its depth */
00267 #define LL_USART_FIFOTHRESHOLD_1_4              0x00000001U /*!< FIFO reaches 1/4 of its depth */
00268 #define LL_USART_FIFOTHRESHOLD_1_2              0x00000002U /*!< FIFO reaches 1/2 of its depth */
00269 #define LL_USART_FIFOTHRESHOLD_3_4              0x00000003U /*!< FIFO reaches 3/4 of its depth */
00270 #define LL_USART_FIFOTHRESHOLD_7_8              0x00000004U /*!< FIFO reaches 7/8 of its depth */
00271 #define LL_USART_FIFOTHRESHOLD_8_8              0x00000005U /*!< FIFO becomes empty for TX and full for RX */
00272 /**
00273   * @}
00274   */
00275
00276 /** @defgroup USART_LL_EC_DIRECTION Communication Direction
00277   * @{
00278   */
00279 #define LL_USART_DIRECTION_NONE                 0x00000000U                        /*!< Transmitter and Receiver are disabled */
00280 #define LL_USART_DIRECTION_RX                   USART_CR1_RE                       /*!< Transmitter is disabled and Receiver is enabled */
00281 #define LL_USART_DIRECTION_TX                   USART_CR1_TE                       /*!< Transmitter is enabled and Receiver is disabled */
00282 #define LL_USART_DIRECTION_TX_RX                (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter and Receiver are enabled */
00283 /**
00284   * @}
00285   */
00286
00287 /** @defgroup USART_LL_EC_PARITY Parity Control
00288   * @{
00289   */
00290 #define LL_USART_PARITY_NONE                    0x00000000U                          /*!< Parity control disabled */
00291 #define LL_USART_PARITY_EVEN                    USART_CR1_PCE                        /*!< Parity control enabled and Even Parity is selected */
00292 #define LL_USART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)       /*!< Parity control enabled and Odd Parity is selected */
00293 /**
00294   * @}
00295   */
00296
00297 /** @defgroup USART_LL_EC_WAKEUP Wakeup
00298   * @{
00299   */
00300 #define LL_USART_WAKEUP_IDLELINE                0x00000000U           /*!<  USART wake up from Mute mode on Idle Line */
00301 #define LL_USART_WAKEUP_ADDRESSMARK             USART_CR1_WAKE        /*!<  USART wake up from Mute mode on Address Mark */
00302 /**
00303   * @}
00304   */
00305
00306 /** @defgroup USART_LL_EC_DATAWIDTH Datawidth
00307   * @{
00308   */
00309 #define LL_USART_DATAWIDTH_7B                   USART_CR1_M1            /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
00310 #define LL_USART_DATAWIDTH_8B                   0x00000000U             /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
00311 #define LL_USART_DATAWIDTH_9B                   USART_CR1_M0            /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
00312 /**
00313   * @}
00314   */
00315
00316 /** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
00317   * @{
00318   */
00319 #define LL_USART_OVERSAMPLING_16                0x00000000U            /*!< Oversampling by 16 */
00320 #define LL_USART_OVERSAMPLING_8                 USART_CR1_OVER8        /*!< Oversampling by 8 */
00321 /**
00322   * @}
00323   */
00324
00325 #if defined(USE_FULL_LL_DRIVER)
00326 /** @defgroup USART_LL_EC_CLOCK Clock Signal
00327   * @{
00328   */
00329
00330 #define LL_USART_CLOCK_DISABLE                  0x00000000U            /*!< Clock signal not provided */
00331 #define LL_USART_CLOCK_ENABLE                   USART_CR2_CLKEN        /*!< Clock signal provided */
00332 /**
00333   * @}
00334   */
00335 #endif /*USE_FULL_LL_DRIVER*/
00336
00337 /** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
00338   * @{
00339   */
00340 #define LL_USART_LASTCLKPULSE_NO_OUTPUT         0x00000000U           /*!< The clock pulse of the last data bit is not output to the SCLK pin */
00341 #define LL_USART_LASTCLKPULSE_OUTPUT            USART_CR2_LBCL        /*!< The clock pulse of the last data bit is output to the SCLK pin */
00342 /**
00343   * @}
00344   */
00345
00346 /** @defgroup USART_LL_EC_PHASE Clock Phase
00347   * @{
00348   */
00349 #define LL_USART_PHASE_1EDGE                    0x00000000U           /*!< The first clock transition is the first data capture edge */
00350 #define LL_USART_PHASE_2EDGE                    USART_CR2_CPHA        /*!< The second clock transition is the first data capture edge */
00351 /**
00352   * @}
00353   */
00354
00355 /** @defgroup USART_LL_EC_POLARITY Clock Polarity
00356   * @{
00357   */
00358 #define LL_USART_POLARITY_LOW                   0x00000000U           /*!< Steady low value on SCLK pin outside transmission window*/
00359 #define LL_USART_POLARITY_HIGH                  USART_CR2_CPOL        /*!< Steady high value on SCLK pin outside transmission window */
00360 /**
00361   * @}
00362   */
00363
00364 /** @defgroup USART_LL_EC_PRESCALER Clock Source Prescaler
00365   * @{
00366   */
00367 #define LL_USART_PRESCALER_DIV1                 0x00000000U                                                                   /*!< Input clock not devided   */
00368 #define LL_USART_PRESCALER_DIV2                 (USART_PRESC_PRESCALER_0)                                                     /*!< Input clock devided by 2  */
00369 #define LL_USART_PRESCALER_DIV4                 (USART_PRESC_PRESCALER_1)                                                     /*!< Input clock devided by 4  */
00370 #define LL_USART_PRESCALER_DIV6                 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)                           /*!< Input clock devided by 6  */
00371 #define LL_USART_PRESCALER_DIV8                 (USART_PRESC_PRESCALER_2)                                                     /*!< Input clock devided by 8  */
00372 #define LL_USART_PRESCALER_DIV10                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0)                           /*!< Input clock devided by 10 */
00373 #define LL_USART_PRESCALER_DIV12                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1)                           /*!< Input clock devided by 12 */
00374 #define LL_USART_PRESCALER_DIV16                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 16 */
00375 #define LL_USART_PRESCALER_DIV32                (USART_PRESC_PRESCALER_3)                                                     /*!< Input clock devided by 32 */
00376 #define LL_USART_PRESCALER_DIV64                (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0)                           /*!< Input clock devided by 64 */
00377 #define LL_USART_PRESCALER_DIV128               (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1)                           /*!< Input clock devided by 128 */
00378 #define LL_USART_PRESCALER_DIV256               (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 256 */
00379 /**
00380   * @}
00381   */
00382
00383 /** @defgroup USART_LL_EC_STOPBITS Stop Bits
00384   * @{
00385   */
00386 #define LL_USART_STOPBITS_0_5                   USART_CR2_STOP_0                           /*!< 0.5 stop bit */
00387 #define LL_USART_STOPBITS_1                     0x00000000U                                /*!< 1 stop bit */
00388 #define LL_USART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1)      /*!< 1.5 stop bits */
00389 #define LL_USART_STOPBITS_2                     USART_CR2_STOP_1                           /*!< 2 stop bits */
00390 /**
00391   * @}
00392   */
00393
00394 /** @defgroup USART_LL_EC_TXRX TX RX Pins Swap
00395   * @{
00396   */
00397 #define LL_USART_TXRX_STANDARD                  0x00000000U           /*!< TX/RX pins are used as defined in standard pinout */
00398 #define LL_USART_TXRX_SWAPPED                   (USART_CR2_SWAP)      /*!< TX and RX pins functions are swapped.             */
00399 /**
00400   * @}
00401   */
00402
00403 /** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
00404   * @{
00405   */
00406 #define LL_USART_RXPIN_LEVEL_STANDARD           0x00000000U           /*!< RX pin signal works using the standard logic levels */
00407 #define LL_USART_RXPIN_LEVEL_INVERTED           (USART_CR2_RXINV)     /*!< RX pin signal values are inverted.                  */
00408 /**
00409   * @}
00410   */
00411
00412 /** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
00413   * @{
00414   */
00415 #define LL_USART_TXPIN_LEVEL_STANDARD           0x00000000U           /*!< TX pin signal works using the standard logic levels */
00416 #define LL_USART_TXPIN_LEVEL_INVERTED           (USART_CR2_TXINV)     /*!< TX pin signal values are inverted.                  */
00417 /**
00418   * @}
00419   */
00420
00421 /** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion
00422   * @{
00423   */
00424 #define LL_USART_BINARY_LOGIC_POSITIVE          0x00000000U           /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
00425 #define LL_USART_BINARY_LOGIC_NEGATIVE          USART_CR2_DATAINV     /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
00426 /**
00427   * @}
00428   */
00429
00430 /** @defgroup USART_LL_EC_BITORDER Bit Order
00431   * @{
00432   */
00433 #define LL_USART_BITORDER_LSBFIRST              0x00000000U           /*!< data is transmitted/received with data bit 0 first, following the start bit */
00434 #define LL_USART_BITORDER_MSBFIRST              USART_CR2_MSBFIRST    /*!< data is transmitted/received with the MSB first, following the start bit */
00435 /**
00436   * @}
00437   */
00438
00439 /** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection
00440   * @{
00441   */
00442 #define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT    0x00000000U                                 /*!< Measurement of the start bit is used to detect the baud rate */
00443 #define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0                         /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */
00444 #define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME    USART_CR2_ABRMODE_1                         /*!< 0x7F frame detection */
00445 #define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME    (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */
00446 /**
00447   * @}
00448   */
00449
00450 /** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection
00451   * @{
00452   */
00453 #define LL_USART_ADDRESS_DETECT_4B              0x00000000U           /*!< 4-bit address detection method selected */
00454 #define LL_USART_ADDRESS_DETECT_7B              USART_CR2_ADDM7       /*!< 7-bit address detection (in 8-bit data mode) method selected */
00455 /**
00456   * @}
00457   */
00458
00459 /** @defgroup USART_LL_EC_HWCONTROL Hardware Control
00460   * @{
00461   */
00462 #define LL_USART_HWCONTROL_NONE                 0x00000000U                          /*!< CTS and RTS hardware flow control disabled */
00463 #define LL_USART_HWCONTROL_RTS                  USART_CR3_RTSE                       /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
00464 #define LL_USART_HWCONTROL_CTS                  USART_CR3_CTSE                       /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
00465 #define LL_USART_HWCONTROL_RTS_CTS              (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< CTS and RTS hardware flow control enabled */
00466 /**
00467   * @}
00468   */
00469
00470 /** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation
00471   * @{
00472   */
00473 #define LL_USART_WAKEUP_ON_ADDRESS              0x00000000U                             /*!< Wake up active on address match */
00474 #define LL_USART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1                         /*!< Wake up active on Start bit detection */
00475 #define LL_USART_WAKEUP_ON_RXNE                 (USART_CR3_WUS_0 | USART_CR3_WUS_1)     /*!< Wake up active on RXNE */
00476 /**
00477   * @}
00478   */
00479
00480 /** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
00481   * @{
00482   */
00483 #define LL_USART_IRDA_POWER_NORMAL              0x00000000U           /*!< IrDA normal power mode */
00484 #define LL_USART_IRDA_POWER_LOW                 USART_CR3_IRLP        /*!< IrDA low power mode */
00485 /**
00486   * @}
00487   */
00488
00489 /** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
00490   * @{
00491   */
00492 #define LL_USART_LINBREAK_DETECT_10B            0x00000000U           /*!< 10-bit break detection method selected */
00493 #define LL_USART_LINBREAK_DETECT_11B            USART_CR2_LBDL        /*!< 11-bit break detection method selected */
00494 /**
00495   * @}
00496   */
00497
00498 /** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity
00499   * @{
00500   */
00501 #define LL_USART_DE_POLARITY_HIGH               0x00000000U           /*!< DE signal is active high */
00502 #define LL_USART_DE_POLARITY_LOW                USART_CR3_DEP         /*!< DE signal is active low */
00503 /**
00504   * @}
00505   */
00506
00507 /** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data
00508   * @{
00509   */
00510 #define LL_USART_DMA_REG_DATA_TRANSMIT          0x00000000U          /*!< Get address of data register used for transmission */
00511 #define LL_USART_DMA_REG_DATA_RECEIVE           0x00000001U          /*!< Get address of data register used for reception */
00512 /**
00513   * @}
00514   */
00515
00516 /**
00517   * @}
00518   */
00519
00520 /* Exported macro ------------------------------------------------------------*/
00521 /** @defgroup USART_LL_Exported_Macros USART Exported Macros
00522   * @{
00523   */
00524
00525 /** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
00526   * @{
00527   */
00528
00529 /**
00530   * @brief  Write a value in USART register
00531   * @param  __INSTANCE__ USART Instance
00532   * @param  __REG__ Register to be written
00533   * @param  __VALUE__ Value to be written in the register
00534   * @retval None
00535   */
00536 #define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00537
00538 /**
00539   * @brief  Read a value in USART register
00540   * @param  __INSTANCE__ USART Instance
00541   * @param  __REG__ Register to be read
00542   * @retval Register value
00543   */
00544 #define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00545 /**
00546   * @}
00547   */
00548
00549 /** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
00550   * @{
00551   */
00552
00553 /**
00554   * @brief  Compute USARTDIV value according to Peripheral Clock and
00555   *         expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
00556   * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
00557   * @param  __PRESCALER__ This parameter can be one of the following values:
00558   *         @arg @ref LL_USART_PRESCALER_DIV1
00559   *         @arg @ref LL_USART_PRESCALER_DIV2
00560   *         @arg @ref LL_USART_PRESCALER_DIV4
00561   *         @arg @ref LL_USART_PRESCALER_DIV6
00562   *         @arg @ref LL_USART_PRESCALER_DIV8
00563   *         @arg @ref LL_USART_PRESCALER_DIV10
00564   *         @arg @ref LL_USART_PRESCALER_DIV12
00565   *         @arg @ref LL_USART_PRESCALER_DIV16
00566   *         @arg @ref LL_USART_PRESCALER_DIV32
00567   *         @arg @ref LL_USART_PRESCALER_DIV64
00568   *         @arg @ref LL_USART_PRESCALER_DIV128
00569   *         @arg @ref LL_USART_PRESCALER_DIV256
00570   * @param  __BAUDRATE__ Baud rate value to achieve
00571   * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
00572   */
00573 #define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (((((__PERIPHCLK__)/(uint32_t)(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U) + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
00574
00575 /**
00576   * @brief  Compute USARTDIV value according to Peripheral Clock and
00577   *         expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
00578   * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
00579   * @param  __PRESCALER__ This parameter can be one of the following values:
00580   *         @arg @ref LL_USART_PRESCALER_DIV1
00581   *         @arg @ref LL_USART_PRESCALER_DIV2
00582   *         @arg @ref LL_USART_PRESCALER_DIV4
00583   *         @arg @ref LL_USART_PRESCALER_DIV6
00584   *         @arg @ref LL_USART_PRESCALER_DIV8
00585   *         @arg @ref LL_USART_PRESCALER_DIV10
00586   *         @arg @ref LL_USART_PRESCALER_DIV12
00587   *         @arg @ref LL_USART_PRESCALER_DIV16
00588   *         @arg @ref LL_USART_PRESCALER_DIV32
00589   *         @arg @ref LL_USART_PRESCALER_DIV64
00590   *         @arg @ref LL_USART_PRESCALER_DIV128
00591   *         @arg @ref LL_USART_PRESCALER_DIV256
00592   * @param  __BAUDRATE__ Baud rate value to achieve
00593   * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
00594   */
00595 #define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((__PERIPHCLK__)/(uint32_t)(USART_PRESCALER_TAB[(__PRESCALER__)])) + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
00596
00597 /**
00598   * @}
00599   */
00600
00601 /**
00602   * @}
00603   */
00604
00605 /* Exported functions --------------------------------------------------------*/
00606
00607 /** @defgroup USART_LL_Exported_Functions USART Exported Functions
00608   * @{
00609   */
00610
00611 /** @defgroup USART_LL_EF_Configuration Configuration functions
00612   * @{
00613   */
00614
00615 /**
00616   * @brief  USART Enable
00617   * @rmtoll CR1          UE            LL_USART_Enable
00618   * @param  USARTx USART Instance
00619   * @retval None
00620   */
00621 __STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
00622 {
00623   SET_BIT(USARTx->CR1, USART_CR1_UE);
00624 }
00625
00626 /**
00627   * @brief  USART Disable (all USART prescalers and outputs are disabled)
00628   * @note   When USART is disabled, USART prescalers and outputs are stopped immediately,
00629   *         and current operations are discarded. The configuration of the USART is kept, but all the status
00630   *         flags, in the USARTx_ISR are set to their default values.
00631   * @rmtoll CR1          UE            LL_USART_Disable
00632   * @param  USARTx USART Instance
00633   * @retval None
00634   */
00635 __STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
00636 {
00637   CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
00638 }
00639
00640 /**
00641   * @brief  Indicate if USART is enabled
00642   * @rmtoll CR1          UE            LL_USART_IsEnabled
00643   * @param  USARTx USART Instance
00644   * @retval State of bit (1 or 0).
00645   */
00646 __STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
00647 {
00648   return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1U : 0U);
00649 }
00650
00651 /**
00652   * @brief  FIFO Mode Enable
00653   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00654   *         FIFO mode feature is supported by the USARTx instance.
00655   * @rmtoll CR1          FIFOEN        LL_USART_EnableFIFO
00656   * @param  USARTx USART Instance
00657   * @retval None
00658   */
00659 __STATIC_INLINE void LL_USART_EnableFIFO(USART_TypeDef *USARTx)
00660 {
00661   SET_BIT(USARTx->CR1, USART_CR1_FIFOEN);
00662 }
00663
00664 /**
00665   * @brief  FIFO Mode Disable
00666   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00667   *         FIFO mode feature is supported by the USARTx instance.
00668   * @rmtoll CR1          FIFOEN        LL_USART_DisableFIFO
00669   * @param  USARTx USART Instance
00670   * @retval None
00671   */
00672 __STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx)
00673 {
00674   CLEAR_BIT(USARTx->CR1, USART_CR1_FIFOEN);
00675 }
00676
00677 /**
00678   * @brief  Indicate if FIFO Mode is enabled
00679   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00680   *         FIFO mode feature is supported by the USARTx instance.
00681   * @rmtoll CR1          FIFOEN        LL_USART_IsEnabledFIFO
00682   * @param  USARTx USART Instance
00683   * @retval State of bit (1 or 0).
00684   */
00685 __STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(USART_TypeDef *USARTx)
00686 {
00687   return ((READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1U : 0U);
00688 }
00689
00690 /**
00691   * @brief  Configure TX FIFO Threshold
00692   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00693   *         FIFO mode feature is supported by the USARTx instance.
00694   * @rmtoll CR3          TXFTCFG       LL_USART_SetTXFIFOThreshold
00695   * @param  USARTx USART Instance
00696   * @param  Threshold This parameter can be one of the following values:
00697   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
00698   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
00699   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
00700   *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
00701   *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
00702   *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
00703   * @retval None
00704   */
00705 __STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
00706 {
00707   MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
00708 }
00709
00710 /**
00711   * @brief  Return TX FIFO Threshold Configuration
00712   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00713   *         FIFO mode feature is supported by the USARTx instance.
00714   * @rmtoll CR3          TXFTCFG       LL_USART_GetTXFIFOThreshold
00715   * @param  USARTx USART Instance
00716   * @retval Returned value can be one of the following values:
00717   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
00718   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
00719   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
00720   *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
00721   *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
00722   *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
00723   */
00724 __STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(USART_TypeDef *USARTx)
00725 {
00726   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
00727 }
00728
00729 /**
00730   * @brief  Configure RX FIFO Threshold
00731   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00732   *         FIFO mode feature is supported by the USARTx instance.
00733   * @rmtoll CR3          RXFTCFG       LL_USART_SetRXFIFOThreshold
00734   * @param  USARTx USART Instance
00735   * @param  Threshold This parameter can be one of the following values:
00736   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
00737   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
00738   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
00739   *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
00740   *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
00741   *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
00742   * @retval None
00743   */
00744 __STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
00745 {
00746   MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
00747 }
00748
00749 /**
00750   * @brief  Return RX FIFO Threshold Configuration
00751   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00752   *         FIFO mode feature is supported by the USARTx instance.
00753   * @rmtoll CR3          RXFTCFG       LL_USART_GetRXFIFOThreshold
00754   * @param  USARTx USART Instance
00755   * @retval Returned value can be one of the following values:
00756   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
00757   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
00758   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
00759   *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
00760   *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
00761   *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
00762   */
00763 __STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(USART_TypeDef *USARTx)
00764 {
00765   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
00766 }
00767
00768 /**
00769   * @brief  Configure TX and RX FIFOs Threshold
00770   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
00771   *         FIFO mode feature is supported by the USARTx instance.
00772   * @rmtoll CR3          TXFTCFG       LL_USART_ConfigFIFOsThreshold\n
00773   *         CR3          RXFTCFG       LL_USART_ConfigFIFOsThreshold
00774   * @param  USARTx USART Instance
00775   * @param  TXThreshold This parameter can be one of the following values:
00776   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
00777   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
00778   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
00779   *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
00780   *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
00781   *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
00782   * @param  RXThreshold This parameter can be one of the following values:
00783   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
00784   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
00785   *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
00786   *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
00787   *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
00788   *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
00789   * @retval None
00790   */
00791 __STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold)
00792 {
00793   MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | (RXThreshold << USART_CR3_RXFTCFG_Pos));
00794 }
00795
00796 /**
00797   * @brief  USART enabled in STOP Mode.
00798   * @note   When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that
00799   *         USART clock selection is HSI or LSE in RCC.
00800   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
00801   *         Wake-up from Stop mode feature is supported by the USARTx instance.
00802   * @rmtoll CR1          UESM          LL_USART_EnableInStopMode
00803   * @param  USARTx USART Instance
00804   * @retval None
00805   */
00806 __STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)
00807 {
00808   SET_BIT(USARTx->CR1, USART_CR1_UESM);
00809 }
00810
00811 /**
00812   * @brief  USART disabled in STOP Mode.
00813   * @note   When this function is disabled, USART is not able to wake up the MCU from Stop mode
00814   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
00815   *         Wake-up from Stop mode feature is supported by the USARTx instance.
00816   * @rmtoll CR1          UESM          LL_USART_DisableInStopMode
00817   * @param  USARTx USART Instance
00818   * @retval None
00819   */
00820 __STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
00821 {
00822   CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
00823 }
00824
00825 /**
00826   * @brief  Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
00827   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
00828   *         Wake-up from Stop mode feature is supported by the USARTx instance.
00829   * @rmtoll CR1          UESM          LL_USART_IsEnabledInStopMode
00830   * @param  USARTx USART Instance
00831   * @retval State of bit (1 or 0).
00832   */
00833 __STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx)
00834 {
00835   return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1U : 0U);
00836 }
00837
00838 /**
00839   * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
00840   * @rmtoll CR1          RE            LL_USART_EnableDirectionRx
00841   * @param  USARTx USART Instance
00842   * @retval None
00843   */
00844 __STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
00845 {
00846   SET_BIT(USARTx->CR1, USART_CR1_RE);
00847 }
00848
00849 /**
00850   * @brief  Receiver Disable
00851   * @rmtoll CR1          RE            LL_USART_DisableDirectionRx
00852   * @param  USARTx USART Instance
00853   * @retval None
00854   */
00855 __STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
00856 {
00857   CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
00858 }
00859
00860 /**
00861   * @brief  Transmitter Enable
00862   * @rmtoll CR1          TE            LL_USART_EnableDirectionTx
00863   * @param  USARTx USART Instance
00864   * @retval None
00865   */
00866 __STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
00867 {
00868   SET_BIT(USARTx->CR1, USART_CR1_TE);
00869 }
00870
00871 /**
00872   * @brief  Transmitter Disable
00873   * @rmtoll CR1          TE            LL_USART_DisableDirectionTx
00874   * @param  USARTx USART Instance
00875   * @retval None
00876   */
00877 __STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
00878 {
00879   CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
00880 }
00881
00882 /**
00883   * @brief  Configure simultaneously enabled/disabled states
00884   *         of Transmitter and Receiver
00885   * @rmtoll CR1          RE            LL_USART_SetTransferDirection\n
00886   *         CR1          TE            LL_USART_SetTransferDirection
00887   * @param  USARTx USART Instance
00888   * @param  TransferDirection This parameter can be one of the following values:
00889   *         @arg @ref LL_USART_DIRECTION_NONE
00890   *         @arg @ref LL_USART_DIRECTION_RX
00891   *         @arg @ref LL_USART_DIRECTION_TX
00892   *         @arg @ref LL_USART_DIRECTION_TX_RX
00893   * @retval None
00894   */
00895 __STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
00896 {
00897   MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
00898 }
00899
00900 /**
00901   * @brief  Return enabled/disabled states of Transmitter and Receiver
00902   * @rmtoll CR1          RE            LL_USART_GetTransferDirection\n
00903   *         CR1          TE            LL_USART_GetTransferDirection
00904   * @param  USARTx USART Instance
00905   * @retval Returned value can be one of the following values:
00906   *         @arg @ref LL_USART_DIRECTION_NONE
00907   *         @arg @ref LL_USART_DIRECTION_RX
00908   *         @arg @ref LL_USART_DIRECTION_TX
00909   *         @arg @ref LL_USART_DIRECTION_TX_RX
00910   */
00911 __STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)
00912 {
00913   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
00914 }
00915
00916 /**
00917   * @brief  Configure Parity (enabled/disabled and parity mode if enabled).
00918   * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
00919   *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
00920   *         (9th or 8th bit depending on data width) and parity is checked on the received data.
00921   * @rmtoll CR1          PS            LL_USART_SetParity\n
00922   *         CR1          PCE           LL_USART_SetParity
00923   * @param  USARTx USART Instance
00924   * @param  Parity This parameter can be one of the following values:
00925   *         @arg @ref LL_USART_PARITY_NONE
00926   *         @arg @ref LL_USART_PARITY_EVEN
00927   *         @arg @ref LL_USART_PARITY_ODD
00928   * @retval None
00929   */
00930 __STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
00931 {
00932   MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
00933 }
00934
00935 /**
00936   * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
00937   * @rmtoll CR1          PS            LL_USART_GetParity\n
00938   *         CR1          PCE           LL_USART_GetParity
00939   * @param  USARTx USART Instance
00940   * @retval Returned value can be one of the following values:
00941   *         @arg @ref LL_USART_PARITY_NONE
00942   *         @arg @ref LL_USART_PARITY_EVEN
00943   *         @arg @ref LL_USART_PARITY_ODD
00944   */
00945 __STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)
00946 {
00947   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
00948 }
00949
00950 /**
00951   * @brief  Set Receiver Wake Up method from Mute mode.
00952   * @rmtoll CR1          WAKE          LL_USART_SetWakeUpMethod
00953   * @param  USARTx USART Instance
00954   * @param  Method This parameter can be one of the following values:
00955   *         @arg @ref LL_USART_WAKEUP_IDLELINE
00956   *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
00957   * @retval None
00958   */
00959 __STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
00960 {
00961   MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
00962 }
00963
00964 /**
00965   * @brief  Return Receiver Wake Up method from Mute mode
00966   * @rmtoll CR1          WAKE          LL_USART_GetWakeUpMethod
00967   * @param  USARTx USART Instance
00968   * @retval Returned value can be one of the following values:
00969   *         @arg @ref LL_USART_WAKEUP_IDLELINE
00970   *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
00971   */
00972 __STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)
00973 {
00974   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
00975 }
00976
00977 /**
00978   * @brief  Set Word length (i.e. nb of data bits, excluding start and stop bits)
00979   * @rmtoll CR1          M0            LL_USART_SetDataWidth\n
00980   *         CR1          M1            LL_USART_SetDataWidth
00981   * @param  USARTx USART Instance
00982   * @param  DataWidth This parameter can be one of the following values:
00983   *         @arg @ref LL_USART_DATAWIDTH_7B
00984   *         @arg @ref LL_USART_DATAWIDTH_8B
00985   *         @arg @ref LL_USART_DATAWIDTH_9B
00986   * @retval None
00987   */
00988 __STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
00989 {
00990   MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
00991 }
00992
00993 /**
00994   * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
00995   * @rmtoll CR1          M0            LL_USART_GetDataWidth\n
00996   *         CR1          M1            LL_USART_GetDataWidth
00997   * @param  USARTx USART Instance
00998   * @retval Returned value can be one of the following values:
00999   *         @arg @ref LL_USART_DATAWIDTH_7B
01000   *         @arg @ref LL_USART_DATAWIDTH_8B
01001   *         @arg @ref LL_USART_DATAWIDTH_9B
01002   */
01003 __STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)
01004 {
01005   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
01006 }
01007
01008 /**
01009   * @brief  Allow switch between Mute Mode and Active mode
01010   * @rmtoll CR1          MME           LL_USART_EnableMuteMode
01011   * @param  USARTx USART Instance
01012   * @retval None
01013   */
01014 __STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx)
01015 {
01016   SET_BIT(USARTx->CR1, USART_CR1_MME);
01017 }
01018
01019 /**
01020   * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.
01021   * @rmtoll CR1          MME           LL_USART_DisableMuteMode
01022   * @param  USARTx USART Instance
01023   * @retval None
01024   */
01025 __STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx)
01026 {
01027   CLEAR_BIT(USARTx->CR1, USART_CR1_MME);
01028 }
01029
01030 /**
01031   * @brief  Indicate if switch between Mute Mode and Active mode is allowed
01032   * @rmtoll CR1          MME           LL_USART_IsEnabledMuteMode
01033   * @param  USARTx USART Instance
01034   * @retval State of bit (1 or 0).
01035   */
01036 __STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx)
01037 {
01038   return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1U : 0U);
01039 }
01040
01041 /**
01042   * @brief  Set Oversampling to 8-bit or 16-bit mode
01043   * @rmtoll CR1          OVER8         LL_USART_SetOverSampling
01044   * @param  USARTx USART Instance
01045   * @param  OverSampling This parameter can be one of the following values:
01046   *         @arg @ref LL_USART_OVERSAMPLING_16
01047   *         @arg @ref LL_USART_OVERSAMPLING_8
01048   * @retval None
01049   */
01050 __STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
01051 {
01052   MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
01053 }
01054
01055 /**
01056   * @brief  Return Oversampling mode
01057   * @rmtoll CR1          OVER8         LL_USART_GetOverSampling
01058   * @param  USARTx USART Instance
01059   * @retval Returned value can be one of the following values:
01060   *         @arg @ref LL_USART_OVERSAMPLING_16
01061   *         @arg @ref LL_USART_OVERSAMPLING_8
01062   */
01063 __STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)
01064 {
01065   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
01066 }
01067
01068 /**
01069   * @brief  Configure if Clock pulse of the last data bit is output to the SCLK pin or not
01070   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
01071   *         Synchronous mode is supported by the USARTx instance.
01072   * @rmtoll CR2          LBCL          LL_USART_SetLastClkPulseOutput
01073   * @param  USARTx USART Instance
01074   * @param  LastBitClockPulse This parameter can be one of the following values:
01075   *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
01076   *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
01077   * @retval None
01078   */
01079 __STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
01080 {
01081   MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
01082 }
01083
01084 /**
01085   * @brief  Retrieve Clock pulse of the last data bit output configuration
01086   *         (Last bit Clock pulse output to the SCLK pin or not)
01087   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
01088   *         Synchronous mode is supported by the USARTx instance.
01089   * @rmtoll CR2          LBCL          LL_USART_GetLastClkPulseOutput
01090   * @param  USARTx USART Instance
01091   * @retval Returned value can be one of the following values:
01092   *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
01093   *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
01094   */
01095 __STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)
01096 {
01097   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
01098 }
01099
01100 /**
01101   * @brief  Select the phase of the clock output on the SCLK pin in synchronous mode
01102   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
01103   *         Synchronous mode is supported by the USARTx instance.
01104   * @rmtoll CR2          CPHA          LL_USART_SetClockPhase
01105   * @param  USARTx USART Instance
01106   * @param  ClockPhase This parameter can be one of the following values:
01107   *         @arg @ref LL_USART_PHASE_1EDGE
01108   *         @arg @ref LL_USART_PHASE_2EDGE
01109   * @retval None
01110   */
01111 __STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
01112 {
01113   MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
01114 }
01115
01116 /**
01117   * @brief  Return phase of the clock output on the SCLK pin in synchronous mode
01118   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
01119   *         Synchronous mode is supported by the USARTx instance.
01120   * @rmtoll CR2          CPHA          LL_USART_GetClockPhase
01121   * @param  USARTx USART Instance
01122   * @retval Returned value can be one of the following values:
01123   *         @arg @ref LL_USART_PHASE_1EDGE
01124   *         @arg @ref LL_USART_PHASE_2EDGE
01125   */
01126 __STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)
01127 {
01128   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
01129 }
01130
01131 /**
01132   * @brief  Select the polarity of the clock output on the SCLK pin in synchronous mode
01133   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
01134   *         Synchronous mode is supported by the USARTx instance.
01135   * @rmtoll CR2          CPOL          LL_USART_SetClockPolarity
01136   * @param  USARTx USART Instance
01137   * @param  ClockPolarity This parameter can be one of the following values:
01138   *         @arg @ref LL_USART_POLARITY_LOW
01139   *         @arg @ref LL_USART_POLARITY_HIGH
01140   * @retval None
01141   */
01142 __STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
01143 {
01144   MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
01145 }
01146
01147 /**
01148   * @brief  Return polarity of the clock output on the SCLK pin in synchronous mode
01149   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
01150   *         Synchronous mode is supported by the USARTx instance.
01151   * @rmtoll CR2          CPOL          LL_USART_GetClockPolarity
01152   * @param  USARTx USART Instance
01153   * @retval Returned value can be one of the following values:
01154   *         @arg @ref LL_USART_POLARITY_LOW
01155   *         @arg @ref LL_USART_POLARITY_HIGH
01156   */
01157 __STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)
01158 {
01159   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
01160 }
01161
01162 /**
01163   * @brief  Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
01164   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
01165   *         Synchronous mode is supported by the USARTx instance.
01166   * @note   Call of this function is equivalent to following function call sequence :
01167   *         - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
01168   *         - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
01169   *         - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function
01170   * @rmtoll CR2          CPHA          LL_USART_ConfigClock\n
01171   *         CR2          CPOL          LL_USART_ConfigClock\n
01172   *         CR2          LBCL          LL_USART_ConfigClock
01173   * @param  USARTx USART Instance
01174   * @param  Phase This parameter can be one of the following values:
01175   *         @arg @ref LL_USART_PHASE_1EDGE
01176   *         @arg @ref LL_USART_PHASE_2EDGE
01177   * @param  Polarity This parameter can be one of the following values:
01178   *         @arg @ref LL_USART_POLARITY_LOW
01179   *         @arg @ref LL_USART_POLARITY_HIGH
01180   * @param  LBCPOutput This parameter can be one of the following values:
01181   *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
01182   *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
01183   * @retval None
01184   */
01185 __STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
01186 {
01187   MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);
01188 }
01189
01190 /**
01191   * @brief  Configure Clock source prescaler for baudrate generator and oversampling
01192   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
01193   *         FIFO mode feature is supported by the USARTx instance.
01194   * @rmtoll PRESC        PRESCALER     LL_USART_SetPrescaler
01195   * @param  USARTx USART Instance
01196   * @param  PrescalerValue This parameter can be one of the following values:
01197   *         @arg @ref LL_USART_PRESCALER_DIV1
01198   *         @arg @ref LL_USART_PRESCALER_DIV2
01199   *         @arg @ref LL_USART_PRESCALER_DIV4
01200   *         @arg @ref LL_USART_PRESCALER_DIV6
01201   *         @arg @ref LL_USART_PRESCALER_DIV8
01202   *         @arg @ref LL_USART_PRESCALER_DIV10
01203   *         @arg @ref LL_USART_PRESCALER_DIV12
01204   *         @arg @ref LL_USART_PRESCALER_DIV16
01205   *         @arg @ref LL_USART_PRESCALER_DIV32
01206   *         @arg @ref LL_USART_PRESCALER_DIV64
01207   *         @arg @ref LL_USART_PRESCALER_DIV128
01208   *         @arg @ref LL_USART_PRESCALER_DIV256
01209   * @retval None
01210   */
01211 __STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
01212 {
01213   MODIFY_REG(USARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
01214 }
01215
01216 /**
01217   * @brief  Retrieve the Clock source prescaler for baudrate generator and oversampling
01218   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
01219   *         FIFO mode feature is supported by the USARTx instance.
01220   * @rmtoll PRESC        PRESCALER     LL_USART_GetPrescaler
01221   * @param  USARTx USART Instance
01222   * @retval Returned value can be one of the following values:
01223   *         @arg @ref LL_USART_PRESCALER_DIV1
01224   *         @arg @ref LL_USART_PRESCALER_DIV2
01225   *         @arg @ref LL_USART_PRESCALER_DIV4
01226   *         @arg @ref LL_USART_PRESCALER_DIV6
01227   *         @arg @ref LL_USART_PRESCALER_DIV8
01228   *         @arg @ref LL_USART_PRESCALER_DIV10
01229   *         @arg @ref LL_USART_PRESCALER_DIV12
01230   *         @arg @ref LL_USART_PRESCALER_DIV16
01231   *         @arg @ref LL_USART_PRESCALER_DIV32
01232   *         @arg @ref LL_USART_PRESCALER_DIV64
01233   *         @arg @ref LL_USART_PRESCALER_DIV128
01234   *         @arg @ref LL_USART_PRESCALER_DIV256
01235   */
01236 __STATIC_INLINE uint32_t LL_USART_GetPrescaler(USART_TypeDef *USARTx)
01237 {
01238   return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER));
01239 }
01240
01241 /**
01242   * @brief  Enable Clock output on SCLK pin
01243   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
01244   *         Synchronous mode is supported by the USARTx instance.
01245   * @rmtoll CR2          CLKEN         LL_USART_EnableSCLKOutput
01246   * @param  USARTx USART Instance
01247   * @retval None
01248   */
01249 __STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
01250 {
01251   SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
01252 }
01253
01254 /**
01255   * @brief  Disable Clock output on SCLK pin
01256   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
01257   *         Synchronous mode is supported by the USARTx instance.
01258   * @rmtoll CR2          CLKEN         LL_USART_DisableSCLKOutput
01259   * @param  USARTx USART Instance
01260   * @retval None
01261   */
01262 __STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
01263 {
01264   CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
01265 }
01266
01267 /**
01268   * @brief  Indicate if Clock output on SCLK pin is enabled
01269   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
01270   *         Synchronous mode is supported by the USARTx instance.
01271   * @rmtoll CR2          CLKEN         LL_USART_IsEnabledSCLKOutput
01272   * @param  USARTx USART Instance
01273   * @retval State of bit (1 or 0).
01274   */
01275 __STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)
01276 {
01277   return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1U : 0U);
01278 }
01279
01280 /**
01281   * @brief  Set the length of the stop bits
01282   * @rmtoll CR2          STOP          LL_USART_SetStopBitsLength
01283   * @param  USARTx USART Instance
01284   * @param  StopBits This parameter can be one of the following values:
01285   *         @arg @ref LL_USART_STOPBITS_0_5
01286   *         @arg @ref LL_USART_STOPBITS_1
01287   *         @arg @ref LL_USART_STOPBITS_1_5
01288   *         @arg @ref LL_USART_STOPBITS_2
01289   * @retval None
01290   */
01291 __STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
01292 {
01293   MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
01294 }
01295
01296 /**
01297   * @brief  Retrieve the length of the stop bits
01298   * @rmtoll CR2          STOP          LL_USART_GetStopBitsLength
01299   * @param  USARTx USART Instance
01300   * @retval Returned value can be one of the following values:
01301   *         @arg @ref LL_USART_STOPBITS_0_5
01302   *         @arg @ref LL_USART_STOPBITS_1
01303   *         @arg @ref LL_USART_STOPBITS_1_5
01304   *         @arg @ref LL_USART_STOPBITS_2
01305   */
01306 __STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)
01307 {
01308   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
01309 }
01310
01311 /**
01312   * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
01313   * @note   Call of this function is equivalent to following function call sequence :
01314   *         - Data Width configuration using @ref LL_USART_SetDataWidth() function
01315   *         - Parity Control and mode configuration using @ref LL_USART_SetParity() function
01316   *         - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
01317   * @rmtoll CR1          PS            LL_USART_ConfigCharacter\n
01318   *         CR1          PCE           LL_USART_ConfigCharacter\n
01319   *         CR1          M0            LL_USART_ConfigCharacter\n
01320   *         CR1          M1            LL_USART_ConfigCharacter\n
01321   *         CR2          STOP          LL_USART_ConfigCharacter
01322   * @param  USARTx USART Instance
01323   * @param  DataWidth This parameter can be one of the following values:
01324   *         @arg @ref LL_USART_DATAWIDTH_7B
01325   *         @arg @ref LL_USART_DATAWIDTH_8B
01326   *         @arg @ref LL_USART_DATAWIDTH_9B
01327   * @param  Parity This parameter can be one of the following values:
01328   *         @arg @ref LL_USART_PARITY_NONE
01329   *         @arg @ref LL_USART_PARITY_EVEN
01330   *         @arg @ref LL_USART_PARITY_ODD
01331   * @param  StopBits This parameter can be one of the following values:
01332   *         @arg @ref LL_USART_STOPBITS_0_5
01333   *         @arg @ref LL_USART_STOPBITS_1
01334   *         @arg @ref LL_USART_STOPBITS_1_5
01335   *         @arg @ref LL_USART_STOPBITS_2
01336   * @retval None
01337   */
01338 __STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,
01339                                               uint32_t StopBits)
01340 {
01341   MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
01342   MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
01343 }
01344
01345 /**
01346   * @brief  Configure TX/RX pins swapping setting.
01347   * @rmtoll CR2          SWAP          LL_USART_SetTXRXSwap
01348   * @param  USARTx USART Instance
01349   * @param  SwapConfig This parameter can be one of the following values:
01350   *         @arg @ref LL_USART_TXRX_STANDARD
01351   *         @arg @ref LL_USART_TXRX_SWAPPED
01352   * @retval None
01353   */
01354 __STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig)
01355 {
01356   MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig);
01357 }
01358
01359 /**
01360   * @brief  Retrieve TX/RX pins swapping configuration.
01361   * @rmtoll CR2          SWAP          LL_USART_GetTXRXSwap
01362   * @param  USARTx USART Instance
01363   * @retval Returned value can be one of the following values:
01364   *         @arg @ref LL_USART_TXRX_STANDARD
01365   *         @arg @ref LL_USART_TXRX_SWAPPED
01366   */
01367 __STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(USART_TypeDef *USARTx)
01368 {
01369   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP));
01370 }
01371
01372 /**
01373   * @brief  Configure RX pin active level logic
01374   * @rmtoll CR2          RXINV         LL_USART_SetRXPinLevel
01375   * @param  USARTx USART Instance
01376   * @param  PinInvMethod This parameter can be one of the following values:
01377   *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
01378   *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
01379   * @retval None
01380   */
01381 __STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
01382 {
01383   MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod);
01384 }
01385
01386 /**
01387   * @brief  Retrieve RX pin active level logic configuration
01388   * @rmtoll CR2          RXINV         LL_USART_GetRXPinLevel
01389   * @param  USARTx USART Instance
01390   * @retval Returned value can be one of the following values:
01391   *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
01392   *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
01393   */
01394 __STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(USART_TypeDef *USARTx)
01395 {
01396   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV));
01397 }
01398
01399 /**
01400   * @brief  Configure TX pin active level logic
01401   * @rmtoll CR2          TXINV         LL_USART_SetTXPinLevel
01402   * @param  USARTx USART Instance
01403   * @param  PinInvMethod This parameter can be one of the following values:
01404   *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
01405   *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
01406   * @retval None
01407   */
01408 __STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
01409 {
01410   MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod);
01411 }
01412
01413 /**
01414   * @brief  Retrieve TX pin active level logic configuration
01415   * @rmtoll CR2          TXINV         LL_USART_GetTXPinLevel
01416   * @param  USARTx USART Instance
01417   * @retval Returned value can be one of the following values:
01418   *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
01419   *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
01420   */
01421 __STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(USART_TypeDef *USARTx)
01422 {
01423   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV));
01424 }
01425
01426 /**
01427   * @brief  Configure Binary data logic.
01428   * @note   Allow to define how Logical data from the data register are send/received :
01429   *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
01430   * @rmtoll CR2          DATAINV       LL_USART_SetBinaryDataLogic
01431   * @param  USARTx USART Instance
01432   * @param  DataLogic This parameter can be one of the following values:
01433   *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
01434   *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
01435   * @retval None
01436   */
01437 __STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic)
01438 {
01439   MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic);
01440 }
01441
01442 /**
01443   * @brief  Retrieve Binary data configuration
01444   * @rmtoll CR2          DATAINV       LL_USART_GetBinaryDataLogic
01445   * @param  USARTx USART Instance
01446   * @retval Returned value can be one of the following values:
01447   *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
01448   *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
01449   */
01450 __STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(USART_TypeDef *USARTx)
01451 {
01452   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV));
01453 }
01454
01455 /**
01456   * @brief  Configure transfer bit order (either Less or Most Significant Bit First)
01457   * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
01458   *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
01459   * @rmtoll CR2          MSBFIRST      LL_USART_SetTransferBitOrder
01460   * @param  USARTx USART Instance
01461   * @param  BitOrder This parameter can be one of the following values:
01462   *         @arg @ref LL_USART_BITORDER_LSBFIRST
01463   *         @arg @ref LL_USART_BITORDER_MSBFIRST
01464   * @retval None
01465   */
01466 __STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder)
01467 {
01468   MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
01469 }
01470
01471 /**
01472   * @brief  Return transfer bit order (either Less or Most Significant Bit First)
01473   * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
01474   *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
01475   * @rmtoll CR2          MSBFIRST      LL_USART_GetTransferBitOrder
01476   * @param  USARTx USART Instance
01477   * @retval Returned value can be one of the following values:
01478   *         @arg @ref LL_USART_BITORDER_LSBFIRST
01479   *         @arg @ref LL_USART_BITORDER_MSBFIRST
01480   */
01481 __STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx)
01482 {
01483   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST));
01484 }
01485
01486 /**
01487   * @brief  Enable Auto Baud-Rate Detection
01488   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
01489   *         Auto Baud Rate detection feature is supported by the USARTx instance.
01490   * @rmtoll CR2          ABREN         LL_USART_EnableAutoBaudRate
01491   * @param  USARTx USART Instance
01492   * @retval None
01493   */
01494 __STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx)
01495 {
01496   SET_BIT(USARTx->CR2, USART_CR2_ABREN);
01497 }
01498
01499 /**
01500   * @brief  Disable Auto Baud-Rate Detection
01501   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
01502   *         Auto Baud Rate detection feature is supported by the USARTx instance.
01503   * @rmtoll CR2          ABREN         LL_USART_DisableAutoBaudRate
01504   * @param  USARTx USART Instance
01505   * @retval None
01506   */
01507 __STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx)
01508 {
01509   CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN);
01510 }
01511
01512 /**
01513   * @brief  Indicate if Auto Baud-Rate Detection mechanism is enabled
01514   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
01515   *         Auto Baud Rate detection feature is supported by the USARTx instance.
01516   * @rmtoll CR2          ABREN         LL_USART_IsEnabledAutoBaud
01517   * @param  USARTx USART Instance
01518   * @retval State of bit (1 or 0).
01519   */
01520 __STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx)
01521 {
01522   return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1U : 0U);
01523 }
01524
01525 /**
01526   * @brief  Set Auto Baud-Rate mode bits
01527   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
01528   *         Auto Baud Rate detection feature is supported by the USARTx instance.
01529   * @rmtoll CR2          ABRMODE       LL_USART_SetAutoBaudRateMode
01530   * @param  USARTx USART Instance
01531   * @param  AutoBaudRateMode This parameter can be one of the following values:
01532   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
01533   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
01534   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
01535   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
01536   * @retval None
01537   */
01538 __STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
01539 {
01540   MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode);
01541 }
01542
01543 /**
01544   * @brief  Return Auto Baud-Rate mode
01545   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
01546   *         Auto Baud Rate detection feature is supported by the USARTx instance.
01547   * @rmtoll CR2          ABRMODE       LL_USART_GetAutoBaudRateMode
01548   * @param  USARTx USART Instance
01549   * @retval Returned value can be one of the following values:
01550   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
01551   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
01552   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
01553   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
01554   */
01555 __STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx)
01556 {
01557   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
01558 }
01559
01560 /**
01561   * @brief  Enable Receiver Timeout
01562   * @rmtoll CR2          RTOEN         LL_USART_EnableRxTimeout
01563   * @param  USARTx USART Instance
01564   * @retval None
01565   */
01566 __STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx)
01567 {
01568   SET_BIT(USARTx->CR2, USART_CR2_RTOEN);
01569 }
01570
01571 /**
01572   * @brief  Disable Receiver Timeout
01573   * @rmtoll CR2          RTOEN         LL_USART_DisableRxTimeout
01574   * @param  USARTx USART Instance
01575   * @retval None
01576   */
01577 __STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx)
01578 {
01579   CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN);
01580 }
01581
01582 /**
01583   * @brief  Indicate if Receiver Timeout feature is enabled
01584   * @rmtoll CR2          RTOEN         LL_USART_IsEnabledRxTimeout
01585   * @param  USARTx USART Instance
01586   * @retval State of bit (1 or 0).
01587   */
01588 __STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx)
01589 {
01590   return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1U : 0U);
01591 }
01592
01593 /**
01594   * @brief  Set Address of the USART node.
01595   * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
01596   *         for wake up with address mark detection.
01597   * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.
01598   *         (b7-b4 should be set to 0)
01599   *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.
01600   *         (This is used in multiprocessor communication during Mute mode or Stop mode,
01601   *         for wake up with 7-bit address mark detection.
01602   *         The MSB of the character sent by the transmitter should be equal to 1.
01603   *         It may also be used for character detection during normal reception,
01604   *         Mute mode inactive (for example, end of block detection in ModBus protocol).
01605   *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]
01606   *         value and CMF flag is set on match)
01607   * @rmtoll CR2          ADD           LL_USART_ConfigNodeAddress\n
01608   *         CR2          ADDM7         LL_USART_ConfigNodeAddress
01609   * @param  USARTx USART Instance
01610   * @param  AddressLen This parameter can be one of the following values:
01611   *         @arg @ref LL_USART_ADDRESS_DETECT_4B
01612   *         @arg @ref LL_USART_ADDRESS_DETECT_7B
01613   * @param  NodeAddress 4 or 7 bit Address of the USART node.
01614   * @retval None
01615   */
01616 __STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
01617 {
01618   MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
01619              (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
01620 }
01621
01622 /**
01623   * @brief  Return 8 bit Address of the USART node as set in ADD field of CR2.
01624   * @note   If 4-bit Address Detection is selected in ADDM7,
01625   *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
01626   *         If 7-bit Address Detection is selected in ADDM7,
01627   *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
01628   * @rmtoll CR2          ADD           LL_USART_GetNodeAddress
01629   * @param  USARTx USART Instance
01630   * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
01631   */
01632 __STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)
01633 {
01634   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
01635 }
01636
01637 /**
01638   * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
01639   * @rmtoll CR2          ADDM7         LL_USART_GetNodeAddressLen
01640   * @param  USARTx USART Instance
01641   * @retval Returned value can be one of the following values:
01642   *         @arg @ref LL_USART_ADDRESS_DETECT_4B
01643   *         @arg @ref LL_USART_ADDRESS_DETECT_7B
01644   */
01645 __STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx)
01646 {
01647   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7));
01648 }
01649
01650 /**
01651   * @brief  Enable RTS HW Flow Control
01652   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01653   *         Hardware Flow control feature is supported by the USARTx instance.
01654   * @rmtoll CR3          RTSE          LL_USART_EnableRTSHWFlowCtrl
01655   * @param  USARTx USART Instance
01656   * @retval None
01657   */
01658 __STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
01659 {
01660   SET_BIT(USARTx->CR3, USART_CR3_RTSE);
01661 }
01662
01663 /**
01664   * @brief  Disable RTS HW Flow Control
01665   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01666   *         Hardware Flow control feature is supported by the USARTx instance.
01667   * @rmtoll CR3          RTSE          LL_USART_DisableRTSHWFlowCtrl
01668   * @param  USARTx USART Instance
01669   * @retval None
01670   */
01671 __STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
01672 {
01673   CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
01674 }
01675
01676 /**
01677   * @brief  Enable CTS HW Flow Control
01678   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01679   *         Hardware Flow control feature is supported by the USARTx instance.
01680   * @rmtoll CR3          CTSE          LL_USART_EnableCTSHWFlowCtrl
01681   * @param  USARTx USART Instance
01682   * @retval None
01683   */
01684 __STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
01685 {
01686   SET_BIT(USARTx->CR3, USART_CR3_CTSE);
01687 }
01688
01689 /**
01690   * @brief  Disable CTS HW Flow Control
01691   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01692   *         Hardware Flow control feature is supported by the USARTx instance.
01693   * @rmtoll CR3          CTSE          LL_USART_DisableCTSHWFlowCtrl
01694   * @param  USARTx USART Instance
01695   * @retval None
01696   */
01697 __STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
01698 {
01699   CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
01700 }
01701
01702 /**
01703   * @brief  Configure HW Flow Control mode (both CTS and RTS)
01704   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01705   *         Hardware Flow control feature is supported by the USARTx instance.
01706   * @rmtoll CR3          RTSE          LL_USART_SetHWFlowCtrl\n
01707   *         CR3          CTSE          LL_USART_SetHWFlowCtrl
01708   * @param  USARTx USART Instance
01709   * @param  HardwareFlowControl This parameter can be one of the following values:
01710   *         @arg @ref LL_USART_HWCONTROL_NONE
01711   *         @arg @ref LL_USART_HWCONTROL_RTS
01712   *         @arg @ref LL_USART_HWCONTROL_CTS
01713   *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
01714   * @retval None
01715   */
01716 __STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
01717 {
01718   MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
01719 }
01720
01721 /**
01722   * @brief  Return HW Flow Control configuration (both CTS and RTS)
01723   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01724   *         Hardware Flow control feature is supported by the USARTx instance.
01725   * @rmtoll CR3          RTSE          LL_USART_GetHWFlowCtrl\n
01726   *         CR3          CTSE          LL_USART_GetHWFlowCtrl
01727   * @param  USARTx USART Instance
01728   * @retval Returned value can be one of the following values:
01729   *         @arg @ref LL_USART_HWCONTROL_NONE
01730   *         @arg @ref LL_USART_HWCONTROL_RTS
01731   *         @arg @ref LL_USART_HWCONTROL_CTS
01732   *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
01733   */
01734 __STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)
01735 {
01736   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
01737 }
01738
01739 /**
01740   * @brief  Enable One bit sampling method
01741   * @rmtoll CR3          ONEBIT        LL_USART_EnableOneBitSamp
01742   * @param  USARTx USART Instance
01743   * @retval None
01744   */
01745 __STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
01746 {
01747   SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
01748 }
01749
01750 /**
01751   * @brief  Disable One bit sampling method
01752   * @rmtoll CR3          ONEBIT        LL_USART_DisableOneBitSamp
01753   * @param  USARTx USART Instance
01754   * @retval None
01755   */
01756 __STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
01757 {
01758   CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
01759 }
01760
01761 /**
01762   * @brief  Indicate if One bit sampling method is enabled
01763   * @rmtoll CR3          ONEBIT        LL_USART_IsEnabledOneBitSamp
01764   * @param  USARTx USART Instance
01765   * @retval State of bit (1 or 0).
01766   */
01767 __STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)
01768 {
01769   return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1U : 0U);
01770 }
01771
01772 /**
01773   * @brief  Enable Overrun detection
01774   * @rmtoll CR3          OVRDIS        LL_USART_EnableOverrunDetect
01775   * @param  USARTx USART Instance
01776   * @retval None
01777   */
01778 __STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx)
01779 {
01780   CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS);
01781 }
01782
01783 /**
01784   * @brief  Disable Overrun detection
01785   * @rmtoll CR3          OVRDIS        LL_USART_DisableOverrunDetect
01786   * @param  USARTx USART Instance
01787   * @retval None
01788   */
01789 __STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx)
01790 {
01791   SET_BIT(USARTx->CR3, USART_CR3_OVRDIS);
01792 }
01793
01794 /**
01795   * @brief  Indicate if Overrun detection is enabled
01796   * @rmtoll CR3          OVRDIS        LL_USART_IsEnabledOverrunDetect
01797   * @param  USARTx USART Instance
01798   * @retval State of bit (1 or 0).
01799   */
01800 __STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx)
01801 {
01802   return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1U : 0U);
01803 }
01804
01805 /**
01806   * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
01807   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
01808   *         Wake-up from Stop mode feature is supported by the USARTx instance.
01809   * @rmtoll CR3          WUS           LL_USART_SetWKUPType
01810   * @param  USARTx USART Instance
01811   * @param  Type This parameter can be one of the following values:
01812   *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
01813   *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
01814   *         @arg @ref LL_USART_WAKEUP_ON_RXNE
01815   * @retval None
01816   */
01817 __STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type)
01818 {
01819   MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type);
01820 }
01821
01822 /**
01823   * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
01824   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
01825   *         Wake-up from Stop mode feature is supported by the USARTx instance.
01826   * @rmtoll CR3          WUS           LL_USART_GetWKUPType
01827   * @param  USARTx USART Instance
01828   * @retval Returned value can be one of the following values:
01829   *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
01830   *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
01831   *         @arg @ref LL_USART_WAKEUP_ON_RXNE
01832   */
01833 __STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx)
01834 {
01835   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));
01836 }
01837
01838 /**
01839   * @brief  Configure USART BRR register for achieving expected Baud Rate value.
01840   * @note   Compute and set USARTDIV value in BRR Register (full BRR content)
01841   *         according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
01842   * @note   Peripheral clock and Baud rate values provided as function parameters should be valid
01843   *         (Baud rate value != 0)
01844   * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
01845   * @rmtoll BRR          BRR           LL_USART_SetBaudRate
01846   * @param  USARTx USART Instance
01847   * @param  PeriphClk Peripheral Clock
01848   * @param  PrescalerValue This parameter can be one of the following values:
01849   *         @arg @ref LL_USART_PRESCALER_DIV1
01850   *         @arg @ref LL_USART_PRESCALER_DIV2
01851   *         @arg @ref LL_USART_PRESCALER_DIV4
01852   *         @arg @ref LL_USART_PRESCALER_DIV6
01853   *         @arg @ref LL_USART_PRESCALER_DIV8
01854   *         @arg @ref LL_USART_PRESCALER_DIV10
01855   *         @arg @ref LL_USART_PRESCALER_DIV12
01856   *         @arg @ref LL_USART_PRESCALER_DIV16
01857   *         @arg @ref LL_USART_PRESCALER_DIV32
01858   *         @arg @ref LL_USART_PRESCALER_DIV64
01859   *         @arg @ref LL_USART_PRESCALER_DIV128
01860   *         @arg @ref LL_USART_PRESCALER_DIV256
01861   * @param  OverSampling This parameter can be one of the following values:
01862   *         @arg @ref LL_USART_OVERSAMPLING_16
01863   *         @arg @ref LL_USART_OVERSAMPLING_8
01864   * @param  BaudRate Baud Rate
01865   * @retval None
01866   */
01867 __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling,
01868                                           uint32_t BaudRate)
01869 {
01870   register uint32_t usartdiv;
01871   register uint32_t brrtemp;
01872
01873   if (OverSampling == LL_USART_OVERSAMPLING_8)
01874   {
01875     usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint16_t)PrescalerValue, BaudRate));
01876     brrtemp = usartdiv & 0xFFF0U;
01877     brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
01878     USARTx->BRR = brrtemp;
01879   }
01880   else
01881   {
01882     USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint16_t)PrescalerValue, BaudRate));
01883   }
01884 }
01885
01886 /**
01887   * @brief  Return current Baud Rate value, according to USARTDIV present in BRR register
01888   *         (full BRR content), and to used Peripheral Clock and Oversampling mode values
01889   * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
01890   * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
01891   * @rmtoll BRR          BRR           LL_USART_GetBaudRate
01892   * @param  USARTx USART Instance
01893   * @param  PeriphClk Peripheral Clock
01894   * @param  PrescalerValue This parameter can be one of the following values:
01895   *         @arg @ref LL_USART_PRESCALER_DIV1
01896   *         @arg @ref LL_USART_PRESCALER_DIV2
01897   *         @arg @ref LL_USART_PRESCALER_DIV4
01898   *         @arg @ref LL_USART_PRESCALER_DIV6
01899   *         @arg @ref LL_USART_PRESCALER_DIV8
01900   *         @arg @ref LL_USART_PRESCALER_DIV10
01901   *         @arg @ref LL_USART_PRESCALER_DIV12
01902   *         @arg @ref LL_USART_PRESCALER_DIV16
01903   *         @arg @ref LL_USART_PRESCALER_DIV32
01904   *         @arg @ref LL_USART_PRESCALER_DIV64
01905   *         @arg @ref LL_USART_PRESCALER_DIV128
01906   *         @arg @ref LL_USART_PRESCALER_DIV256
01907   * @param  OverSampling This parameter can be one of the following values:
01908   *         @arg @ref LL_USART_OVERSAMPLING_16
01909   *         @arg @ref LL_USART_OVERSAMPLING_8
01910   * @retval Baud Rate
01911   */
01912 __STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling)
01913 {
01914   register uint32_t usartdiv;
01915   register uint32_t brrresult = 0x0U;
01916   register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (uint32_t)(USART_PRESCALER_TAB[(uint16_t)PrescalerValue]));
01917
01918   usartdiv = USARTx->BRR;
01919
01920   if(usartdiv == 0U)
01921   {
01922     /* Do not perform a division by 0 */
01923   }
01924   else if (OverSampling == LL_USART_OVERSAMPLING_8)
01925   {
01926     usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
01927     if(usartdiv != 0U)
01928     {
01929       brrresult = (periphclkpresc * 2U) / usartdiv;
01930     }
01931   }
01932   else
01933   {
01934     if ((usartdiv & 0xFFFFU) != 0U)
01935     {
01936       brrresult = periphclkpresc / usartdiv;
01937     }
01938   }
01939   return (brrresult);
01940 }
01941
01942 /**
01943   * @brief  Set Receiver Time Out Value (expressed in nb of bits duration)
01944   * @rmtoll RTOR         RTO           LL_USART_SetRxTimeout
01945   * @param  USARTx USART Instance
01946   * @param  Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
01947   * @retval None
01948   */
01949 __STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout)
01950 {
01951   MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout);
01952 }
01953
01954 /**
01955   * @brief  Get Receiver Time Out Value (expressed in nb of bits duration)
01956   * @rmtoll RTOR         RTO           LL_USART_GetRxTimeout
01957   * @param  USARTx USART Instance
01958   * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
01959   */
01960 __STATIC_INLINE uint32_t LL_USART_GetRxTimeout(USART_TypeDef *USARTx)
01961 {
01962   return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO));
01963 }
01964
01965 /**
01966   * @brief  Set Block Length value in reception
01967   * @rmtoll RTOR         BLEN          LL_USART_SetBlockLength
01968   * @param  USARTx USART Instance
01969   * @param  BlockLength Value between Min_Data=0x00 and Max_Data=0xFF
01970   * @retval None
01971   */
01972 __STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength)
01973 {
01974   MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos);
01975 }
01976
01977 /**
01978   * @brief  Get Block Length value in reception
01979   * @rmtoll RTOR         BLEN          LL_USART_GetBlockLength
01980   * @param  USARTx USART Instance
01981   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
01982   */
01983 __STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx)
01984 {
01985   return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos);
01986 }
01987
01988 /**
01989   * @}
01990   */
01991
01992 /** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature
01993   * @{
01994   */
01995
01996 /**
01997   * @brief  Enable IrDA mode
01998   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
01999   *         IrDA feature is supported by the USARTx instance.
02000   * @rmtoll CR3          IREN          LL_USART_EnableIrda
02001   * @param  USARTx USART Instance
02002   * @retval None
02003   */
02004 __STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
02005 {
02006   SET_BIT(USARTx->CR3, USART_CR3_IREN);
02007 }
02008
02009 /**
02010   * @brief  Disable IrDA mode
02011   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02012   *         IrDA feature is supported by the USARTx instance.
02013   * @rmtoll CR3          IREN          LL_USART_DisableIrda
02014   * @param  USARTx USART Instance
02015   * @retval None
02016   */
02017 __STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
02018 {
02019   CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
02020 }
02021
02022 /**
02023   * @brief  Indicate if IrDA mode is enabled
02024   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02025   *         IrDA feature is supported by the USARTx instance.
02026   * @rmtoll CR3          IREN          LL_USART_IsEnabledIrda
02027   * @param  USARTx USART Instance
02028   * @retval State of bit (1 or 0).
02029   */
02030 __STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
02031 {
02032   return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1U : 0U);
02033 }
02034
02035 /**
02036   * @brief  Configure IrDA Power Mode (Normal or Low Power)
02037   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02038   *         IrDA feature is supported by the USARTx instance.
02039   * @rmtoll CR3          IRLP          LL_USART_SetIrdaPowerMode
02040   * @param  USARTx USART Instance
02041   * @param  PowerMode This parameter can be one of the following values:
02042   *         @arg @ref LL_USART_IRDA_POWER_NORMAL
02043   *         @arg @ref LL_USART_IRDA_POWER_LOW
02044   * @retval None
02045   */
02046 __STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
02047 {
02048   MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
02049 }
02050
02051 /**
02052   * @brief  Retrieve IrDA Power Mode configuration (Normal or Low Power)
02053   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02054   *         IrDA feature is supported by the USARTx instance.
02055   * @rmtoll CR3          IRLP          LL_USART_GetIrdaPowerMode
02056   * @param  USARTx USART Instance
02057   * @retval Returned value can be one of the following values:
02058   *         @arg @ref LL_USART_IRDA_POWER_NORMAL
02059   *         @arg @ref LL_USART_PHASE_2EDGE
02060   */
02061 __STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
02062 {
02063   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
02064 }
02065
02066 /**
02067   * @brief  Set Irda prescaler value, used for dividing the USART clock source
02068   *         to achieve the Irda Low Power frequency (8 bits value)
02069   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02070   *         IrDA feature is supported by the USARTx instance.
02071   * @rmtoll GTPR         PSC           LL_USART_SetIrdaPrescaler
02072   * @param  USARTx USART Instance
02073   * @param  PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
02074   * @retval None
02075   */
02076 __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
02077 {
02078   MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
02079 }
02080
02081 /**
02082   * @brief  Return Irda prescaler value, used for dividing the USART clock source
02083   *         to achieve the Irda Low Power frequency (8 bits value)
02084   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02085   *         IrDA feature is supported by the USARTx instance.
02086   * @rmtoll GTPR         PSC           LL_USART_GetIrdaPrescaler
02087   * @param  USARTx USART Instance
02088   * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
02089   */
02090 __STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)
02091 {
02092   return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
02093 }
02094
02095 /**
02096   * @}
02097   */
02098
02099 /** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature
02100   * @{
02101   */
02102
02103 /**
02104   * @brief  Enable Smartcard NACK transmission
02105   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02106   *         Smartcard feature is supported by the USARTx instance.
02107   * @rmtoll CR3          NACK          LL_USART_EnableSmartcardNACK
02108   * @param  USARTx USART Instance
02109   * @retval None
02110   */
02111 __STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
02112 {
02113   SET_BIT(USARTx->CR3, USART_CR3_NACK);
02114 }
02115
02116 /**
02117   * @brief  Disable Smartcard NACK transmission
02118   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02119   *         Smartcard feature is supported by the USARTx instance.
02120   * @rmtoll CR3          NACK          LL_USART_DisableSmartcardNACK
02121   * @param  USARTx USART Instance
02122   * @retval None
02123   */
02124 __STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
02125 {
02126   CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
02127 }
02128
02129 /**
02130   * @brief  Indicate if Smartcard NACK transmission is enabled
02131   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02132   *         Smartcard feature is supported by the USARTx instance.
02133   * @rmtoll CR3          NACK          LL_USART_IsEnabledSmartcardNACK
02134   * @param  USARTx USART Instance
02135   * @retval State of bit (1 or 0).
02136   */
02137 __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
02138 {
02139   return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1U : 0U);
02140 }
02141
02142 /**
02143   * @brief  Enable Smartcard mode
02144   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02145   *         Smartcard feature is supported by the USARTx instance.
02146   * @rmtoll CR3          SCEN          LL_USART_EnableSmartcard
02147   * @param  USARTx USART Instance
02148   * @retval None
02149   */
02150 __STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
02151 {
02152   SET_BIT(USARTx->CR3, USART_CR3_SCEN);
02153 }
02154
02155 /**
02156   * @brief  Disable Smartcard mode
02157   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02158   *         Smartcard feature is supported by the USARTx instance.
02159   * @rmtoll CR3          SCEN          LL_USART_DisableSmartcard
02160   * @param  USARTx USART Instance
02161   * @retval None
02162   */
02163 __STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
02164 {
02165   CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
02166 }
02167
02168 /**
02169   * @brief  Indicate if Smartcard mode is enabled
02170   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02171   *         Smartcard feature is supported by the USARTx instance.
02172   * @rmtoll CR3          SCEN          LL_USART_IsEnabledSmartcard
02173   * @param  USARTx USART Instance
02174   * @retval State of bit (1 or 0).
02175   */
02176 __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
02177 {
02178   return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1U : 0U);
02179 }
02180
02181 /**
02182   * @brief  Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
02183   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02184   *         Smartcard feature is supported by the USARTx instance.
02185   * @note   This bit-field specifies the number of retries in transmit and receive, in Smartcard mode.
02186   *         In transmission mode, it specifies the number of automatic retransmission retries, before
02187   *         generating a transmission error (FE bit set).
02188   *         In reception mode, it specifies the number or erroneous reception trials, before generating a
02189   *         reception error (RXNE and PE bits set)
02190   * @rmtoll CR3          SCARCNT       LL_USART_SetSmartcardAutoRetryCount
02191   * @param  USARTx USART Instance
02192   * @param  AutoRetryCount Value between Min_Data=0 and Max_Data=7
02193   * @retval None
02194   */
02195 __STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount)
02196 {
02197   MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos);
02198 }
02199
02200 /**
02201   * @brief  Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
02202   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02203   *         Smartcard feature is supported by the USARTx instance.
02204   * @rmtoll CR3          SCARCNT       LL_USART_GetSmartcardAutoRetryCount
02205   * @param  USARTx USART Instance
02206   * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)
02207   */
02208 __STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USARTx)
02209 {
02210   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos);
02211 }
02212
02213 /**
02214   * @brief  Set Smartcard prescaler value, used for dividing the USART clock
02215   *         source to provide the SMARTCARD Clock (5 bits value)
02216   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02217   *         Smartcard feature is supported by the USARTx instance.
02218   * @rmtoll GTPR         PSC           LL_USART_SetSmartcardPrescaler
02219   * @param  USARTx USART Instance
02220   * @param  PrescalerValue Value between Min_Data=0 and Max_Data=31
02221   * @retval None
02222   */
02223 __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
02224 {
02225   MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
02226 }
02227
02228 /**
02229   * @brief  Return Smartcard prescaler value, used for dividing the USART clock
02230   *         source to provide the SMARTCARD Clock (5 bits value)
02231   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02232   *         Smartcard feature is supported by the USARTx instance.
02233   * @rmtoll GTPR         PSC           LL_USART_GetSmartcardPrescaler
02234   * @param  USARTx USART Instance
02235   * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
02236   */
02237 __STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
02238 {
02239   return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
02240 }
02241
02242 /**
02243   * @brief  Set Smartcard Guard time value, expressed in nb of baud clocks periods
02244   *         (GT[7:0] bits : Guard time value)
02245   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02246   *         Smartcard feature is supported by the USARTx instance.
02247   * @rmtoll GTPR         GT            LL_USART_SetSmartcardGuardTime
02248   * @param  USARTx USART Instance
02249   * @param  GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
02250   * @retval None
02251   */
02252 __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
02253 {
02254   MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_GTPR_GT_Pos);
02255 }
02256
02257 /**
02258   * @brief  Return Smartcard Guard time value, expressed in nb of baud clocks periods
02259   *         (GT[7:0] bits : Guard time value)
02260   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02261   *         Smartcard feature is supported by the USARTx instance.
02262   * @rmtoll GTPR         GT            LL_USART_GetSmartcardGuardTime
02263   * @param  USARTx USART Instance
02264   * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
02265   */
02266 __STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
02267 {
02268   return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos);
02269 }
02270
02271 /**
02272   * @}
02273   */
02274
02275 /** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
02276   * @{
02277   */
02278
02279 /**
02280   * @brief  Enable Single Wire Half-Duplex mode
02281   * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
02282   *         Half-Duplex mode is supported by the USARTx instance.
02283   * @rmtoll CR3          HDSEL         LL_USART_EnableHalfDuplex
02284   * @param  USARTx USART Instance
02285   * @retval None
02286   */
02287 __STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
02288 {
02289   SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
02290 }
02291
02292 /**
02293   * @brief  Disable Single Wire Half-Duplex mode
02294   * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
02295   *         Half-Duplex mode is supported by the USARTx instance.
02296   * @rmtoll CR3          HDSEL         LL_USART_DisableHalfDuplex
02297   * @param  USARTx USART Instance
02298   * @retval None
02299   */
02300 __STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
02301 {
02302   CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
02303 }
02304
02305 /**
02306   * @brief  Indicate if Single Wire Half-Duplex mode is enabled
02307   * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
02308   *         Half-Duplex mode is supported by the USARTx instance.
02309   * @rmtoll CR3          HDSEL         LL_USART_IsEnabledHalfDuplex
02310   * @param  USARTx USART Instance
02311   * @retval State of bit (1 or 0).
02312   */
02313 __STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
02314 {
02315   return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1U : 0U);
02316 }
02317
02318 /**
02319   * @}
02320   */
02321
02322 /** @defgroup USART_LL_EF_Configuration_SPI_SLAVE Configuration functions related to SPI Slave feature
02323   * @{
02324   */
02325 /**
02326   * @brief  Enable SPI Synchronous Slave mode
02327   * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
02328   *         SPI Slave mode feature is supported by the USARTx instance.
02329   * @rmtoll CR2          SLVEN         LL_USART_EnableSPISlave
02330   * @param  USARTx USART Instance
02331   * @retval None
02332   */
02333 __STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef *USARTx)
02334 {
02335   SET_BIT(USARTx->CR2, USART_CR2_SLVEN);
02336 }
02337
02338 /**
02339   * @brief  Disable SPI Synchronous Slave mode
02340   * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
02341   *         SPI Slave mode feature is supported by the USARTx instance.
02342   * @rmtoll CR2          SLVEN         LL_USART_DisableSPISlave
02343   * @param  USARTx USART Instance
02344   * @retval None
02345   */
02346 __STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *USARTx)
02347 {
02348   CLEAR_BIT(USARTx->CR2, USART_CR2_SLVEN);
02349 }
02350
02351 /**
02352   * @brief  Indicate if  SPI Synchronous Slave mode is enabled
02353   * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
02354   *         SPI Slave mode feature is supported by the USARTx instance.
02355   * @rmtoll CR2          SLVEN         LL_USART_IsEnabledSPISlave
02356   * @param  USARTx USART Instance
02357   * @retval State of bit (1 or 0).
02358   */
02359 __STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(USART_TypeDef *USARTx)
02360 {
02361   return ((READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)) ? 1U : 0U);
02362 }
02363
02364 /**
02365   * @brief  Enable SPI Slave Selection using NSS input pin
02366   * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
02367   *         SPI Slave mode feature is supported by the USARTx instance.
02368   * @note   SPI Slave Selection depends on NSS input pin
02369   *         (The slave is selected when NSS is low and deselected when NSS is high).
02370   * @rmtoll CR2          DIS_NSS       LL_USART_EnableSPISlaveSelect
02371   * @param  USARTx USART Instance
02372   * @retval None
02373   */
02374 __STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef *USARTx)
02375 {
02376   CLEAR_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
02377 }
02378
02379 /**
02380   * @brief  Disable SPI Slave Selection using NSS input pin
02381   * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
02382   *         SPI Slave mode feature is supported by the USARTx instance.
02383   * @note   SPI Slave will be always selected and NSS input pin will be ignored.
02384   * @rmtoll CR2          DIS_NSS       LL_USART_DisableSPISlaveSelect
02385   * @param  USARTx USART Instance
02386   * @retval None
02387   */
02388 __STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx)
02389 {
02390   SET_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
02391 }
02392
02393 /**
02394   * @brief  Indicate if  SPI Slave Selection depends on NSS input pin
02395   * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
02396   *         SPI Slave mode feature is supported by the USARTx instance.
02397   * @rmtoll CR2          DIS_NSS       LL_USART_IsEnabledSPISlaveSelect
02398   * @param  USARTx USART Instance
02399   * @retval State of bit (1 or 0).
02400   */
02401 __STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(USART_TypeDef *USARTx)
02402 {
02403   return ((READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)) ? 1U : 0U);
02404 }
02405
02406 /**
02407   * @}
02408   */
02409
02410 /** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature
02411   * @{
02412   */
02413
02414 /**
02415   * @brief  Set LIN Break Detection Length
02416   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02417   *         LIN feature is supported by the USARTx instance.
02418   * @rmtoll CR2          LBDL          LL_USART_SetLINBrkDetectionLen
02419   * @param  USARTx USART Instance
02420   * @param  LINBDLength This parameter can be one of the following values:
02421   *         @arg @ref LL_USART_LINBREAK_DETECT_10B
02422   *         @arg @ref LL_USART_LINBREAK_DETECT_11B
02423   * @retval None
02424   */
02425 __STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
02426 {
02427   MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
02428 }
02429
02430 /**
02431   * @brief  Return LIN Break Detection Length
02432   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02433   *         LIN feature is supported by the USARTx instance.
02434   * @rmtoll CR2          LBDL          LL_USART_GetLINBrkDetectionLen
02435   * @param  USARTx USART Instance
02436   * @retval Returned value can be one of the following values:
02437   *         @arg @ref LL_USART_LINBREAK_DETECT_10B
02438   *         @arg @ref LL_USART_LINBREAK_DETECT_11B
02439   */
02440 __STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)
02441 {
02442   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
02443 }
02444
02445 /**
02446   * @brief  Enable LIN mode
02447   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02448   *         LIN feature is supported by the USARTx instance.
02449   * @rmtoll CR2          LINEN         LL_USART_EnableLIN
02450   * @param  USARTx USART Instance
02451   * @retval None
02452   */
02453 __STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
02454 {
02455   SET_BIT(USARTx->CR2, USART_CR2_LINEN);
02456 }
02457
02458 /**
02459   * @brief  Disable LIN mode
02460   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02461   *         LIN feature is supported by the USARTx instance.
02462   * @rmtoll CR2          LINEN         LL_USART_DisableLIN
02463   * @param  USARTx USART Instance
02464   * @retval None
02465   */
02466 __STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
02467 {
02468   CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
02469 }
02470
02471 /**
02472   * @brief  Indicate if LIN mode is enabled
02473   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02474   *         LIN feature is supported by the USARTx instance.
02475   * @rmtoll CR2          LINEN         LL_USART_IsEnabledLIN
02476   * @param  USARTx USART Instance
02477   * @retval State of bit (1 or 0).
02478   */
02479 __STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
02480 {
02481   return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1U : 0U);
02482 }
02483
02484 /**
02485   * @}
02486   */
02487
02488 /** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
02489   * @{
02490   */
02491
02492 /**
02493   * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
02494   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02495   *         Driver Enable feature is supported by the USARTx instance.
02496   * @rmtoll CR1          DEDT          LL_USART_SetDEDeassertionTime
02497   * @param  USARTx USART Instance
02498   * @param  Time Value between Min_Data=0 and Max_Data=31
02499   * @retval None
02500   */
02501 __STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time)
02502 {
02503   MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
02504 }
02505
02506 /**
02507   * @brief  Return DEDT (Driver Enable De-Assertion Time)
02508   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02509   *         Driver Enable feature is supported by the USARTx instance.
02510   * @rmtoll CR1          DEDT          LL_USART_GetDEDeassertionTime
02511   * @param  USARTx USART Instance
02512   * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
02513   */
02514 __STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx)
02515 {
02516   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
02517 }
02518
02519 /**
02520   * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
02521   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02522   *         Driver Enable feature is supported by the USARTx instance.
02523   * @rmtoll CR1          DEAT          LL_USART_SetDEAssertionTime
02524   * @param  USARTx USART Instance
02525   * @param  Time Value between Min_Data=0 and Max_Data=31
02526   * @retval None
02527   */
02528 __STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time)
02529 {
02530   MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
02531 }
02532
02533 /**
02534   * @brief  Return DEAT (Driver Enable Assertion Time)
02535   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02536   *         Driver Enable feature is supported by the USARTx instance.
02537   * @rmtoll CR1          DEAT          LL_USART_GetDEAssertionTime
02538   * @param  USARTx USART Instance
02539   * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
02540   */
02541 __STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx)
02542 {
02543   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
02544 }
02545
02546 /**
02547   * @brief  Enable Driver Enable (DE) Mode
02548   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02549   *         Driver Enable feature is supported by the USARTx instance.
02550   * @rmtoll CR3          DEM           LL_USART_EnableDEMode
02551   * @param  USARTx USART Instance
02552   * @retval None
02553   */
02554 __STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx)
02555 {
02556   SET_BIT(USARTx->CR3, USART_CR3_DEM);
02557 }
02558
02559 /**
02560   * @brief  Disable Driver Enable (DE) Mode
02561   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02562   *         Driver Enable feature is supported by the USARTx instance.
02563   * @rmtoll CR3          DEM           LL_USART_DisableDEMode
02564   * @param  USARTx USART Instance
02565   * @retval None
02566   */
02567 __STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx)
02568 {
02569   CLEAR_BIT(USARTx->CR3, USART_CR3_DEM);
02570 }
02571
02572 /**
02573   * @brief  Indicate if Driver Enable (DE) Mode is enabled
02574   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02575   *         Driver Enable feature is supported by the USARTx instance.
02576   * @rmtoll CR3          DEM           LL_USART_IsEnabledDEMode
02577   * @param  USARTx USART Instance
02578   * @retval State of bit (1 or 0).
02579   */
02580 __STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx)
02581 {
02582   return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1U : 0U);
02583 }
02584
02585 /**
02586   * @brief  Select Driver Enable Polarity
02587   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02588   *         Driver Enable feature is supported by the USARTx instance.
02589   * @rmtoll CR3          DEP           LL_USART_SetDESignalPolarity
02590   * @param  USARTx USART Instance
02591   * @param  Polarity This parameter can be one of the following values:
02592   *         @arg @ref LL_USART_DE_POLARITY_HIGH
02593   *         @arg @ref LL_USART_DE_POLARITY_LOW
02594   * @retval None
02595   */
02596 __STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity)
02597 {
02598   MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity);
02599 }
02600
02601 /**
02602   * @brief  Return Driver Enable Polarity
02603   * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
02604   *         Driver Enable feature is supported by the USARTx instance.
02605   * @rmtoll CR3          DEP           LL_USART_GetDESignalPolarity
02606   * @param  USARTx USART Instance
02607   * @retval Returned value can be one of the following values:
02608   *         @arg @ref LL_USART_DE_POLARITY_HIGH
02609   *         @arg @ref LL_USART_DE_POLARITY_LOW
02610   */
02611 __STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(USART_TypeDef *USARTx)
02612 {
02613   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP));
02614 }
02615
02616 /**
02617   * @}
02618   */
02619
02620 /** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
02621   * @{
02622   */
02623
02624 /**
02625   * @brief  Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
02626   * @note   In UART mode, the following bits must be kept cleared:
02627   *           - LINEN bit in the USART_CR2 register,
02628   *           - CLKEN bit in the USART_CR2 register,
02629   *           - SCEN bit in the USART_CR3 register,
02630   *           - IREN bit in the USART_CR3 register,
02631   *           - HDSEL bit in the USART_CR3 register.
02632   * @note   Call of this function is equivalent to following function call sequence :
02633   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02634   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
02635   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02636   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02637   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02638   * @note   Other remaining configurations items related to Asynchronous Mode
02639   *         (as Baud Rate, Word length, Parity, ...) should be set using
02640   *         dedicated functions
02641   * @rmtoll CR2          LINEN         LL_USART_ConfigAsyncMode\n
02642   *         CR2          CLKEN         LL_USART_ConfigAsyncMode\n
02643   *         CR3          SCEN          LL_USART_ConfigAsyncMode\n
02644   *         CR3          IREN          LL_USART_ConfigAsyncMode\n
02645   *         CR3          HDSEL         LL_USART_ConfigAsyncMode
02646   * @param  USARTx USART Instance
02647   * @retval None
02648   */
02649 __STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
02650 {
02651   /* In Asynchronous mode, the following bits must be kept cleared:
02652   - LINEN, CLKEN bits in the USART_CR2 register,
02653   - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
02654   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
02655   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
02656 }
02657
02658 /**
02659   * @brief  Perform basic configuration of USART for enabling use in Synchronous Mode
02660   * @note   In Synchronous mode, the following bits must be kept cleared:
02661   *           - LINEN bit in the USART_CR2 register,
02662   *           - SCEN bit in the USART_CR3 register,
02663   *           - IREN bit in the USART_CR3 register,
02664   *           - HDSEL bit in the USART_CR3 register.
02665   *         This function also sets the USART in Synchronous mode.
02666   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
02667   *         Synchronous mode is supported by the USARTx instance.
02668   * @note   Call of this function is equivalent to following function call sequence :
02669   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02670   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02671   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02672   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02673   *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
02674   * @note   Other remaining configurations items related to Synchronous Mode
02675   *         (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using
02676   *         dedicated functions
02677   * @rmtoll CR2          LINEN         LL_USART_ConfigSyncMode\n
02678   *         CR2          CLKEN         LL_USART_ConfigSyncMode\n
02679   *         CR3          SCEN          LL_USART_ConfigSyncMode\n
02680   *         CR3          IREN          LL_USART_ConfigSyncMode\n
02681   *         CR3          HDSEL         LL_USART_ConfigSyncMode
02682   * @param  USARTx USART Instance
02683   * @retval None
02684   */
02685 __STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
02686 {
02687   /* In Synchronous mode, the following bits must be kept cleared:
02688   - LINEN bit in the USART_CR2 register,
02689   - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
02690   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
02691   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
02692   /* set the UART/USART in Synchronous mode */
02693   SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
02694 }
02695
02696 /**
02697   * @brief  Perform basic configuration of USART for enabling use in LIN Mode
02698   * @note   In LIN mode, the following bits must be kept cleared:
02699   *           - STOP and CLKEN bits in the USART_CR2 register,
02700   *           - SCEN bit in the USART_CR3 register,
02701   *           - IREN bit in the USART_CR3 register,
02702   *           - HDSEL bit in the USART_CR3 register.
02703   *         This function also set the UART/USART in LIN mode.
02704   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02705   *         LIN feature is supported by the USARTx instance.
02706   * @note   Call of this function is equivalent to following function call sequence :
02707   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
02708   *         - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
02709   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02710   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02711   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02712   *         - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
02713   * @note   Other remaining configurations items related to LIN Mode
02714   *         (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using
02715   *         dedicated functions
02716   * @rmtoll CR2          CLKEN         LL_USART_ConfigLINMode\n
02717   *         CR2          STOP          LL_USART_ConfigLINMode\n
02718   *         CR2          LINEN         LL_USART_ConfigLINMode\n
02719   *         CR3          IREN          LL_USART_ConfigLINMode\n
02720   *         CR3          SCEN          LL_USART_ConfigLINMode\n
02721   *         CR3          HDSEL         LL_USART_ConfigLINMode
02722   * @param  USARTx USART Instance
02723   * @retval None
02724   */
02725 __STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
02726 {
02727   /* In LIN mode, the following bits must be kept cleared:
02728   - STOP and CLKEN bits in the USART_CR2 register,
02729   - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
02730   CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
02731   CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
02732   /* Set the UART/USART in LIN mode */
02733   SET_BIT(USARTx->CR2, USART_CR2_LINEN);
02734 }
02735
02736 /**
02737   * @brief  Perform basic configuration of USART for enabling use in Half Duplex Mode
02738   * @note   In Half Duplex mode, the following bits must be kept cleared:
02739   *           - LINEN bit in the USART_CR2 register,
02740   *           - CLKEN bit in the USART_CR2 register,
02741   *           - SCEN bit in the USART_CR3 register,
02742   *           - IREN bit in the USART_CR3 register,
02743   *         This function also sets the UART/USART in Half Duplex mode.
02744   * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
02745   *         Half-Duplex mode is supported by the USARTx instance.
02746   * @note   Call of this function is equivalent to following function call sequence :
02747   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02748   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
02749   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02750   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02751   *         - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
02752   * @note   Other remaining configurations items related to Half Duplex Mode
02753   *         (as Baud Rate, Word length, Parity, ...) should be set using
02754   *         dedicated functions
02755   * @rmtoll CR2          LINEN         LL_USART_ConfigHalfDuplexMode\n
02756   *         CR2          CLKEN         LL_USART_ConfigHalfDuplexMode\n
02757   *         CR3          HDSEL         LL_USART_ConfigHalfDuplexMode\n
02758   *         CR3          SCEN          LL_USART_ConfigHalfDuplexMode\n
02759   *         CR3          IREN          LL_USART_ConfigHalfDuplexMode
02760   * @param  USARTx USART Instance
02761   * @retval None
02762   */
02763 __STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
02764 {
02765   /* In Half Duplex mode, the following bits must be kept cleared:
02766   - LINEN and CLKEN bits in the USART_CR2 register,
02767   - SCEN and IREN bits in the USART_CR3 register.*/
02768   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
02769   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
02770   /* set the UART/USART in Half Duplex mode */
02771   SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
02772 }
02773
02774 /**
02775   * @brief  Perform basic configuration of USART for enabling use in Smartcard Mode
02776   * @note   In Smartcard mode, the following bits must be kept cleared:
02777   *           - LINEN bit in the USART_CR2 register,
02778   *           - IREN bit in the USART_CR3 register,
02779   *           - HDSEL bit in the USART_CR3 register.
02780   *         This function also configures Stop bits to 1.5 bits and
02781   *         sets the USART in Smartcard mode (SCEN bit).
02782   *         Clock Output is also enabled (CLKEN).
02783   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
02784   *         Smartcard feature is supported by the USARTx instance.
02785   * @note   Call of this function is equivalent to following function call sequence :
02786   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02787   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02788   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02789   *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
02790   *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
02791   *         - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
02792   * @note   Other remaining configurations items related to Smartcard Mode
02793   *         (as Baud Rate, Word length, Parity, ...) should be set using
02794   *         dedicated functions
02795   * @rmtoll CR2          LINEN         LL_USART_ConfigSmartcardMode\n
02796   *         CR2          STOP          LL_USART_ConfigSmartcardMode\n
02797   *         CR2          CLKEN         LL_USART_ConfigSmartcardMode\n
02798   *         CR3          HDSEL         LL_USART_ConfigSmartcardMode\n
02799   *         CR3          SCEN          LL_USART_ConfigSmartcardMode
02800   * @param  USARTx USART Instance
02801   * @retval None
02802   */
02803 __STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
02804 {
02805   /* In Smartcard mode, the following bits must be kept cleared:
02806   - LINEN bit in the USART_CR2 register,
02807   - IREN and HDSEL bits in the USART_CR3 register.*/
02808   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
02809   CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
02810   /* Configure Stop bits to 1.5 bits */
02811   /* Synchronous mode is activated by default */
02812   SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
02813   /* set the UART/USART in Smartcard mode */
02814   SET_BIT(USARTx->CR3, USART_CR3_SCEN);
02815 }
02816
02817 /**
02818   * @brief  Perform basic configuration of USART for enabling use in Irda Mode
02819   * @note   In IRDA mode, the following bits must be kept cleared:
02820   *           - LINEN bit in the USART_CR2 register,
02821   *           - STOP and CLKEN bits in the USART_CR2 register,
02822   *           - SCEN bit in the USART_CR3 register,
02823   *           - HDSEL bit in the USART_CR3 register.
02824   *         This function also sets the UART/USART in IRDA mode (IREN bit).
02825   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
02826   *         IrDA feature is supported by the USARTx instance.
02827   * @note   Call of this function is equivalent to following function call sequence :
02828   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02829   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
02830   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02831   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02832   *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
02833   *         - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
02834   * @note   Other remaining configurations items related to Irda Mode
02835   *         (as Baud Rate, Word length, Power mode, ...) should be set using
02836   *         dedicated functions
02837   * @rmtoll CR2          LINEN         LL_USART_ConfigIrdaMode\n
02838   *         CR2          CLKEN         LL_USART_ConfigIrdaMode\n
02839   *         CR2          STOP          LL_USART_ConfigIrdaMode\n
02840   *         CR3          SCEN          LL_USART_ConfigIrdaMode\n
02841   *         CR3          HDSEL         LL_USART_ConfigIrdaMode\n
02842   *         CR3          IREN          LL_USART_ConfigIrdaMode
02843   * @param  USARTx USART Instance
02844   * @retval None
02845   */
02846 __STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
02847 {
02848   /* In IRDA mode, the following bits must be kept cleared:
02849   - LINEN, STOP and CLKEN bits in the USART_CR2 register,
02850   - SCEN and HDSEL bits in the USART_CR3 register.*/
02851   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
02852   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
02853   /* set the UART/USART in IRDA mode */
02854   SET_BIT(USARTx->CR3, USART_CR3_IREN);
02855 }
02856
02857 /**
02858   * @brief  Perform basic configuration of USART for enabling use in Multi processor Mode
02859   *         (several USARTs connected in a network, one of the USARTs can be the master,
02860   *         its TX output connected to the RX inputs of the other slaves USARTs).
02861   * @note   In MultiProcessor mode, the following bits must be kept cleared:
02862   *           - LINEN bit in the USART_CR2 register,
02863   *           - CLKEN bit in the USART_CR2 register,
02864   *           - SCEN bit in the USART_CR3 register,
02865   *           - IREN bit in the USART_CR3 register,
02866   *           - HDSEL bit in the USART_CR3 register.
02867   * @note   Call of this function is equivalent to following function call sequence :
02868   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
02869   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
02870   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
02871   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
02872   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
02873   * @note   Other remaining configurations items related to Multi processor Mode
02874   *         (as Baud Rate, Wake Up Method, Node address, ...) should be set using
02875   *         dedicated functions
02876   * @rmtoll CR2          LINEN         LL_USART_ConfigMultiProcessMode\n
02877   *         CR2          CLKEN         LL_USART_ConfigMultiProcessMode\n
02878   *         CR3          SCEN          LL_USART_ConfigMultiProcessMode\n
02879   *         CR3          HDSEL         LL_USART_ConfigMultiProcessMode\n
02880   *         CR3          IREN          LL_USART_ConfigMultiProcessMode
02881   * @param  USARTx USART Instance
02882   * @retval None
02883   */
02884 __STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
02885 {
02886   /* In Multi Processor mode, the following bits must be kept cleared:
02887   - LINEN and CLKEN bits in the USART_CR2 register,
02888   - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
02889   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
02890   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
02891 }
02892
02893 /**
02894   * @}
02895   */
02896
02897 /** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
02898   * @{
02899   */
02900
02901 /**
02902   * @brief  Check if the USART Parity Error Flag is set or not
02903   * @rmtoll ISR          PE            LL_USART_IsActiveFlag_PE
02904   * @param  USARTx USART Instance
02905   * @retval State of bit (1 or 0).
02906   */
02907 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
02908 {
02909   return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1U : 0U);
02910 }
02911
02912 /**
02913   * @brief  Check if the USART Framing Error Flag is set or not
02914   * @rmtoll ISR          FE            LL_USART_IsActiveFlag_FE
02915   * @param  USARTx USART Instance
02916   * @retval State of bit (1 or 0).
02917   */
02918 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
02919 {
02920   return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1U : 0U);
02921 }
02922
02923 /**
02924   * @brief  Check if the USART Noise error detected Flag is set or not
02925   * @rmtoll ISR          NE            LL_USART_IsActiveFlag_NE
02926   * @param  USARTx USART Instance
02927   * @retval State of bit (1 or 0).
02928   */
02929 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
02930 {
02931   return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1U : 0U);
02932 }
02933
02934 /**
02935   * @brief  Check if the USART OverRun Error Flag is set or not
02936   * @rmtoll ISR          ORE           LL_USART_IsActiveFlag_ORE
02937   * @param  USARTx USART Instance
02938   * @retval State of bit (1 or 0).
02939   */
02940 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
02941 {
02942   return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1U : 0U);
02943 }
02944
02945 /**
02946   * @brief  Check if the USART IDLE line detected Flag is set or not
02947   * @rmtoll ISR          IDLE          LL_USART_IsActiveFlag_IDLE
02948   * @param  USARTx USART Instance
02949   * @retval State of bit (1 or 0).
02950   */
02951 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
02952 {
02953   return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1U : 0U);
02954 }
02955
02956 /* Legacy define */
02957 #define LL_USART_IsActiveFlag_RXNE  LL_USART_IsActiveFlag_RXNE_RXFNE
02958
02959 /**
02960   * @brief  Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not
02961   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
02962   *         FIFO mode feature is supported by the USARTx instance.
02963   * @rmtoll ISR          RXNE_RXFNE    LL_USART_IsActiveFlag_RXNE_RXFNE
02964   * @param  USARTx USART Instance
02965   * @retval State of bit (1 or 0).
02966   */
02967 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *USARTx)
02968 {
02969   return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1U : 0U);
02970 }
02971
02972 /**
02973   * @brief  Check if the USART Transmission Complete Flag is set or not
02974   * @rmtoll ISR          TC            LL_USART_IsActiveFlag_TC
02975   * @param  USARTx USART Instance
02976   * @retval State of bit (1 or 0).
02977   */
02978 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
02979 {
02980   return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1U : 0U);
02981 }
02982
02983 /* Legacy define */
02984 #define LL_USART_IsActiveFlag_TXE  LL_USART_IsActiveFlag_TXE_TXFNF
02985
02986 /**
02987   * @brief  Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not
02988   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
02989   *         FIFO mode feature is supported by the USARTx instance.
02990   * @rmtoll ISR          TXE_TXFNF     LL_USART_IsActiveFlag_TXE_TXFNF
02991   * @param  USARTx USART Instance
02992   * @retval State of bit (1 or 0).
02993   */
02994 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *USARTx)
02995 {
02996   return ((READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1U : 0U);
02997 }
02998
02999 /**
03000   * @brief  Check if the USART LIN Break Detection Flag is set or not
03001   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
03002   *         LIN feature is supported by the USARTx instance.
03003   * @rmtoll ISR          LBDF          LL_USART_IsActiveFlag_LBD
03004   * @param  USARTx USART Instance
03005   * @retval State of bit (1 or 0).
03006   */
03007 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
03008 {
03009   return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1U : 0U);
03010 }
03011
03012 /**
03013   * @brief  Check if the USART CTS interrupt Flag is set or not
03014   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
03015   *         Hardware Flow control feature is supported by the USARTx instance.
03016   * @rmtoll ISR          CTSIF         LL_USART_IsActiveFlag_nCTS
03017   * @param  USARTx USART Instance
03018   * @retval State of bit (1 or 0).
03019   */
03020 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
03021 {
03022   return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1U : 0U);
03023 }
03024
03025 /**
03026   * @brief  Check if the USART CTS Flag is set or not
03027   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
03028   *         Hardware Flow control feature is supported by the USARTx instance.
03029   * @rmtoll ISR          CTS           LL_USART_IsActiveFlag_CTS
03030   * @param  USARTx USART Instance
03031   * @retval State of bit (1 or 0).
03032   */
03033 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx)
03034 {
03035   return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1U : 0U);
03036 }
03037
03038 /**
03039   * @brief  Check if the USART Receiver Time Out Flag is set or not
03040   * @rmtoll ISR          RTOF          LL_USART_IsActiveFlag_RTO
03041   * @param  USARTx USART Instance
03042   * @retval State of bit (1 or 0).
03043   */
03044 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx)
03045 {
03046   return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1U : 0U);
03047 }
03048
03049 /**
03050   * @brief  Check if the USART End Of Block Flag is set or not
03051   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03052   *         Smartcard feature is supported by the USARTx instance.
03053   * @rmtoll ISR          EOBF          LL_USART_IsActiveFlag_EOB
03054   * @param  USARTx USART Instance
03055   * @retval State of bit (1 or 0).
03056   */
03057 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx)
03058 {
03059   return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1U : 0U);
03060 }
03061
03062 /**
03063   * @brief  Check if the SPI Slave Underrun error flag is set or not
03064   * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
03065   *         SPI Slave mode feature is supported by the USARTx instance.
03066   * @rmtoll ISR          UDR           LL_USART_IsActiveFlag_UDR
03067   * @param  USARTx USART Instance
03068   * @retval State of bit (1 or 0).
03069   */
03070 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(USART_TypeDef *USARTx)
03071 {
03072   return ((READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)) ? 1U : 0U);
03073 }
03074
03075 /**
03076   * @brief  Check if the USART Auto-Baud Rate Error Flag is set or not
03077   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
03078   *         Auto Baud Rate detection feature is supported by the USARTx instance.
03079   * @rmtoll ISR          ABRE          LL_USART_IsActiveFlag_ABRE
03080   * @param  USARTx USART Instance
03081   * @retval State of bit (1 or 0).
03082   */
03083 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx)
03084 {
03085   return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1U : 0U);
03086 }
03087
03088 /**
03089   * @brief  Check if the USART Auto-Baud Rate Flag is set or not
03090   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
03091   *         Auto Baud Rate detection feature is supported by the USARTx instance.
03092   * @rmtoll ISR          ABRF          LL_USART_IsActiveFlag_ABR
03093   * @param  USARTx USART Instance
03094   * @retval State of bit (1 or 0).
03095   */
03096 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx)
03097 {
03098   return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1U : 0U);
03099 }
03100
03101 /**
03102   * @brief  Check if the USART Busy Flag is set or not
03103   * @rmtoll ISR          BUSY          LL_USART_IsActiveFlag_BUSY
03104   * @param  USARTx USART Instance
03105   * @retval State of bit (1 or 0).
03106   */
03107 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx)
03108 {
03109   return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1U : 0U);
03110 }
03111
03112 /**
03113   * @brief  Check if the USART Character Match Flag is set or not
03114   * @rmtoll ISR          CMF           LL_USART_IsActiveFlag_CM
03115   * @param  USARTx USART Instance
03116   * @retval State of bit (1 or 0).
03117   */
03118 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx)
03119 {
03120   return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1U : 0U);
03121 }
03122
03123 /**
03124   * @brief  Check if the USART Send Break Flag is set or not
03125   * @rmtoll ISR          SBKF          LL_USART_IsActiveFlag_SBK
03126   * @param  USARTx USART Instance
03127   * @retval State of bit (1 or 0).
03128   */
03129 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
03130 {
03131   return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1U : 0U);
03132 }
03133
03134 /**
03135   * @brief  Check if the USART Receive Wake Up from mute mode Flag is set or not
03136   * @rmtoll ISR          RWU           LL_USART_IsActiveFlag_RWU
03137   * @param  USARTx USART Instance
03138   * @retval State of bit (1 or 0).
03139   */
03140 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
03141 {
03142   return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1U : 0U);
03143 }
03144
03145 /**
03146   * @brief  Check if the USART Wake Up from stop mode Flag is set or not
03147   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
03148   *         Wake-up from Stop mode feature is supported by the USARTx instance.
03149   * @rmtoll ISR          WUF           LL_USART_IsActiveFlag_WKUP
03150   * @param  USARTx USART Instance
03151   * @retval State of bit (1 or 0).
03152   */
03153 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx)
03154 {
03155   return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1U : 0U);
03156 }
03157
03158 /**
03159   * @brief  Check if the USART Transmit Enable Acknowledge Flag is set or not
03160   * @rmtoll ISR          TEACK         LL_USART_IsActiveFlag_TEACK
03161   * @param  USARTx USART Instance
03162   * @retval State of bit (1 or 0).
03163   */
03164 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx)
03165 {
03166   return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1U : 0U);
03167 }
03168
03169 /**
03170   * @brief  Check if the USART Receive Enable Acknowledge Flag is set or not
03171   * @rmtoll ISR          REACK         LL_USART_IsActiveFlag_REACK
03172   * @param  USARTx USART Instance
03173   * @retval State of bit (1 or 0).
03174   */
03175 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx)
03176 {
03177   return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1U : 0U);
03178 }
03179
03180 /**
03181   * @brief  Check if the USART TX FIFO Empty Flag is set or not
03182   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03183   *         FIFO mode feature is supported by the USARTx instance.
03184   * @rmtoll ISR          TXFE          LL_USART_IsActiveFlag_TXFE
03185   * @param  USARTx USART Instance
03186   * @retval State of bit (1 or 0).
03187   */
03188 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(USART_TypeDef *USARTx)
03189 {
03190   return ((READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1U : 0U);
03191 }
03192
03193 /**
03194   * @brief  Check if the USART RX FIFO Full Flag is set or not
03195   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03196   *         FIFO mode feature is supported by the USARTx instance.
03197   * @rmtoll ISR          RXFF          LL_USART_IsActiveFlag_RXFF
03198   * @param  USARTx USART Instance
03199   * @retval State of bit (1 or 0).
03200   */
03201 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(USART_TypeDef *USARTx)
03202 {
03203   return ((READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1U : 0U);
03204 }
03205
03206 /**
03207   * @brief  Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not
03208   * @rmtoll ISR          TCBGT         LL_USART_IsActiveFlag_TCBGT
03209   * @param  USARTx USART Instance
03210   * @retval State of bit (1 or 0).
03211   */
03212 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx)
03213 {
03214   return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1U : 0U);
03215 }
03216
03217 /**
03218   * @brief  Check if the USART TX FIFO Threshold Flag is set or not
03219   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03220   *         FIFO mode feature is supported by the USARTx instance.
03221   * @rmtoll ISR          TXFT          LL_USART_IsActiveFlag_TXFT
03222   * @param  USARTx USART Instance
03223   * @retval State of bit (1 or 0).
03224   */
03225 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(USART_TypeDef *USARTx)
03226 {
03227   return ((READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1U : 0U);
03228 }
03229
03230 /**
03231   * @brief  Check if the USART RX FIFO Threshold Flag is set or not
03232   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03233   *         FIFO mode feature is supported by the USARTx instance.
03234   * @rmtoll ISR          RXFT          LL_USART_IsActiveFlag_RXFT
03235   * @param  USARTx USART Instance
03236   * @retval State of bit (1 or 0).
03237   */
03238 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(USART_TypeDef *USARTx)
03239 {
03240   return ((READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1U : 0U);
03241 }
03242
03243 /**
03244   * @brief  Clear Parity Error Flag
03245   * @rmtoll ICR          PECF          LL_USART_ClearFlag_PE
03246   * @param  USARTx USART Instance
03247   * @retval None
03248   */
03249 __STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
03250 {
03251   WRITE_REG(USARTx->ICR, USART_ICR_PECF);
03252 }
03253
03254 /**
03255   * @brief  Clear Framing Error Flag
03256   * @rmtoll ICR          FECF          LL_USART_ClearFlag_FE
03257   * @param  USARTx USART Instance
03258   * @retval None
03259   */
03260 __STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
03261 {
03262   WRITE_REG(USARTx->ICR, USART_ICR_FECF);
03263 }
03264
03265 /**
03266   * @brief  Clear Noise Error detected Flag
03267   * @rmtoll ICR          NECF           LL_USART_ClearFlag_NE
03268   * @param  USARTx USART Instance
03269   * @retval None
03270   */
03271 __STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
03272 {
03273   WRITE_REG(USARTx->ICR, USART_ICR_NECF);
03274 }
03275
03276 /**
03277   * @brief  Clear OverRun Error Flag
03278   * @rmtoll ICR          ORECF         LL_USART_ClearFlag_ORE
03279   * @param  USARTx USART Instance
03280   * @retval None
03281   */
03282 __STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
03283 {
03284   WRITE_REG(USARTx->ICR, USART_ICR_ORECF);
03285 }
03286
03287 /**
03288   * @brief  Clear IDLE line detected Flag
03289   * @rmtoll ICR          IDLECF        LL_USART_ClearFlag_IDLE
03290   * @param  USARTx USART Instance
03291   * @retval None
03292   */
03293 __STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
03294 {
03295   WRITE_REG(USARTx->ICR, USART_ICR_IDLECF);
03296 }
03297
03298 /**
03299   * @brief  Clear TX FIFO Empty Flag
03300   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03301   *         FIFO mode feature is supported by the USARTx instance.
03302   * @rmtoll ICR          TXFECF        LL_USART_ClearFlag_TXFE
03303   * @param  USARTx USART Instance
03304   * @retval None
03305   */
03306 __STATIC_INLINE void LL_USART_ClearFlag_TXFE(USART_TypeDef *USARTx)
03307 {
03308   WRITE_REG(USARTx->ICR, USART_ICR_TXFECF);
03309 }
03310
03311 /**
03312   * @brief  Clear Transmission Complete Flag
03313   * @rmtoll ICR          TCCF          LL_USART_ClearFlag_TC
03314   * @param  USARTx USART Instance
03315   * @retval None
03316   */
03317 __STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
03318 {
03319   WRITE_REG(USARTx->ICR, USART_ICR_TCCF);
03320 }
03321
03322 /**
03323   * @brief  Clear Smartcard Transmission Complete Before Guard Time Flag
03324   * @rmtoll ICR          TCBGTCF       LL_USART_ClearFlag_TCBGT
03325   * @param  USARTx USART Instance
03326   * @retval None
03327   */
03328 __STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx)
03329 {
03330   WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF);
03331 }
03332
03333 /**
03334   * @brief  Clear LIN Break Detection Flag
03335   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
03336   *         LIN feature is supported by the USARTx instance.
03337   * @rmtoll ICR          LBDCF         LL_USART_ClearFlag_LBD
03338   * @param  USARTx USART Instance
03339   * @retval None
03340   */
03341 __STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
03342 {
03343   WRITE_REG(USARTx->ICR, USART_ICR_LBDCF);
03344 }
03345
03346 /**
03347   * @brief  Clear CTS Interrupt Flag
03348   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
03349   *         Hardware Flow control feature is supported by the USARTx instance.
03350   * @rmtoll ICR          CTSCF         LL_USART_ClearFlag_nCTS
03351   * @param  USARTx USART Instance
03352   * @retval None
03353   */
03354 __STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
03355 {
03356   WRITE_REG(USARTx->ICR, USART_ICR_CTSCF);
03357 }
03358
03359 /**
03360   * @brief  Clear Receiver Time Out Flag
03361   * @rmtoll ICR          RTOCF         LL_USART_ClearFlag_RTO
03362   * @param  USARTx USART Instance
03363   * @retval None
03364   */
03365 __STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx)
03366 {
03367   WRITE_REG(USARTx->ICR, USART_ICR_RTOCF);
03368 }
03369
03370 /**
03371   * @brief  Clear End Of Block Flag
03372   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03373   *         Smartcard feature is supported by the USARTx instance.
03374   * @rmtoll ICR          EOBCF         LL_USART_ClearFlag_EOB
03375   * @param  USARTx USART Instance
03376   * @retval None
03377   */
03378 __STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx)
03379 {
03380   WRITE_REG(USARTx->ICR, USART_ICR_EOBCF);
03381 }
03382
03383 /**
03384   * @brief  Clear SPI Slave Underrun Flag
03385   * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
03386   *         SPI Slave mode feature is supported by the USARTx instance.
03387   * @rmtoll ICR          UDRCF         LL_USART_ClearFlag_UDR
03388   * @param  USARTx USART Instance
03389   * @retval None
03390   */
03391 __STATIC_INLINE void LL_USART_ClearFlag_UDR(USART_TypeDef *USARTx)
03392 {
03393   WRITE_REG(USARTx->ICR, USART_ICR_UDRCF);
03394 }
03395
03396 /**
03397   * @brief  Clear Character Match Flag
03398   * @rmtoll ICR          CMCF          LL_USART_ClearFlag_CM
03399   * @param  USARTx USART Instance
03400   * @retval None
03401   */
03402 __STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx)
03403 {
03404   WRITE_REG(USARTx->ICR, USART_ICR_CMCF);
03405 }
03406
03407 /**
03408   * @brief  Clear Wake Up from stop mode Flag
03409   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
03410   *         Wake-up from Stop mode feature is supported by the USARTx instance.
03411   * @rmtoll ICR          WUCF          LL_USART_ClearFlag_WKUP
03412   * @param  USARTx USART Instance
03413   * @retval None
03414   */
03415 __STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx)
03416 {
03417   WRITE_REG(USARTx->ICR, USART_ICR_WUCF);
03418 }
03419
03420 /**
03421   * @}
03422   */
03423
03424 /** @defgroup USART_LL_EF_IT_Management IT_Management
03425   * @{
03426   */
03427
03428 /**
03429   * @brief  Enable IDLE Interrupt
03430   * @rmtoll CR1          IDLEIE        LL_USART_EnableIT_IDLE
03431   * @param  USARTx USART Instance
03432   * @retval None
03433   */
03434 __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
03435 {
03436   SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
03437 }
03438
03439 /* Legacy define */
03440 #define LL_USART_EnableIT_RXNE  LL_USART_EnableIT_RXNE_RXFNE
03441
03442 /**
03443   * @brief  Enable RX Not Empty and RX FIFO Not Empty Interrupt
03444   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03445   *         FIFO mode feature is supported by the USARTx instance.
03446   * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_EnableIT_RXNE_RXFNE
03447   * @param  USARTx USART Instance
03448   * @retval None
03449   */
03450 __STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
03451 {
03452   SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
03453 }
03454
03455 /**
03456   * @brief  Enable Transmission Complete Interrupt
03457   * @rmtoll CR1          TCIE          LL_USART_EnableIT_TC
03458   * @param  USARTx USART Instance
03459   * @retval None
03460   */
03461 __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
03462 {
03463   SET_BIT(USARTx->CR1, USART_CR1_TCIE);
03464 }
03465
03466 /* Legacy define */
03467 #define LL_USART_EnableIT_TXE  LL_USART_EnableIT_TXE_TXFNF
03468
03469 /**
03470   * @brief  Enable TX Empty and TX FIFO Not Full Interrupt
03471   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03472   *         FIFO mode feature is supported by the USARTx instance.
03473   * @rmtoll CR1         TXEIE_TXFNFIE  LL_USART_EnableIT_TXE_TXFNF
03474   * @param  USARTx USART Instance
03475   * @retval None
03476   */
03477 __STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx)
03478 {
03479   SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
03480 }
03481
03482 /**
03483   * @brief  Enable Parity Error Interrupt
03484   * @rmtoll CR1          PEIE          LL_USART_EnableIT_PE
03485   * @param  USARTx USART Instance
03486   * @retval None
03487   */
03488 __STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
03489 {
03490   SET_BIT(USARTx->CR1, USART_CR1_PEIE);
03491 }
03492
03493 /**
03494   * @brief  Enable Character Match Interrupt
03495   * @rmtoll CR1          CMIE          LL_USART_EnableIT_CM
03496   * @param  USARTx USART Instance
03497   * @retval None
03498   */
03499 __STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx)
03500 {
03501   SET_BIT(USARTx->CR1, USART_CR1_CMIE);
03502 }
03503
03504 /**
03505   * @brief  Enable Receiver Timeout Interrupt
03506   * @rmtoll CR1          RTOIE         LL_USART_EnableIT_RTO
03507   * @param  USARTx USART Instance
03508   * @retval None
03509   */
03510 __STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx)
03511 {
03512   SET_BIT(USARTx->CR1, USART_CR1_RTOIE);
03513 }
03514
03515 /**
03516   * @brief  Enable End Of Block Interrupt
03517   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03518   *         Smartcard feature is supported by the USARTx instance.
03519   * @rmtoll CR1          EOBIE         LL_USART_EnableIT_EOB
03520   * @param  USARTx USART Instance
03521   * @retval None
03522   */
03523 __STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx)
03524 {
03525   SET_BIT(USARTx->CR1, USART_CR1_EOBIE);
03526 }
03527
03528 /**
03529   * @brief  Enable TX FIFO Empty Interrupt
03530   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03531   *         FIFO mode feature is supported by the USARTx instance.
03532   * @rmtoll CR1          TXFEIE        LL_USART_EnableIT_TXFE
03533   * @param  USARTx USART Instance
03534   * @retval None
03535   */
03536 __STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx)
03537 {
03538   SET_BIT(USARTx->CR1, USART_CR1_TXFEIE);
03539 }
03540
03541 /**
03542   * @brief  Enable RX FIFO Full Interrupt
03543   * @rmtoll CR1          RXFFIE        LL_USART_EnableIT_RXFF
03544   * @param  USARTx USART Instance
03545   * @retval None
03546   */
03547 __STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx)
03548 {
03549   SET_BIT(USARTx->CR1, USART_CR1_RXFFIE);
03550 }
03551
03552 /**
03553   * @brief  Enable LIN Break Detection Interrupt
03554   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
03555   *         LIN feature is supported by the USARTx instance.
03556   * @rmtoll CR2          LBDIE         LL_USART_EnableIT_LBD
03557   * @param  USARTx USART Instance
03558   * @retval None
03559   */
03560 __STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
03561 {
03562   SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
03563 }
03564
03565 /**
03566   * @brief  Enable Error Interrupt
03567   * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
03568   *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
03569   *           0: Interrupt is inhibited
03570   *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
03571   * @rmtoll CR3          EIE           LL_USART_EnableIT_ERROR
03572   * @param  USARTx USART Instance
03573   * @retval None
03574   */
03575 __STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
03576 {
03577   SET_BIT(USARTx->CR3, USART_CR3_EIE);
03578 }
03579
03580 /**
03581   * @brief  Enable CTS Interrupt
03582   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
03583   *         Hardware Flow control feature is supported by the USARTx instance.
03584   * @rmtoll CR3          CTSIE         LL_USART_EnableIT_CTS
03585   * @param  USARTx USART Instance
03586   * @retval None
03587   */
03588 __STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
03589 {
03590   SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
03591 }
03592
03593 /**
03594   * @brief  Enable Wake Up from Stop Mode Interrupt
03595   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
03596   *         Wake-up from Stop mode feature is supported by the USARTx instance.
03597   * @rmtoll CR3          WUFIE         LL_USART_EnableIT_WKUP
03598   * @param  USARTx USART Instance
03599   * @retval None
03600   */
03601 __STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx)
03602 {
03603   SET_BIT(USARTx->CR3, USART_CR3_WUFIE);
03604 }
03605
03606 /**
03607   * @brief  Enable TX FIFO Threshold Interrupt
03608   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03609   *         FIFO mode feature is supported by the USARTx instance.
03610   * @rmtoll CR3          TXFTIE        LL_USART_EnableIT_TXFT
03611   * @param  USARTx USART Instance
03612   * @retval None
03613   */
03614 __STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx)
03615 {
03616   SET_BIT(USARTx->CR3, USART_CR3_TXFTIE);
03617 }
03618
03619 /**
03620   * @brief  Enable Smartcard Transmission Complete Before Guard Time Interrupt
03621   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03622   *         Smartcard feature is supported by the USARTx instance.
03623   * @rmtoll CR3          TCBGTIE       LL_USART_EnableIT_TCBGT
03624   * @param  USARTx USART Instance
03625   * @retval None
03626   */
03627 __STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx)
03628 {
03629   SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
03630 }
03631
03632 /**
03633   * @brief  Enable RX FIFO Threshold Interrupt
03634   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03635   *         FIFO mode feature is supported by the USARTx instance.
03636   * @rmtoll CR3          RXFTIE        LL_USART_EnableIT_RXFT
03637   * @param  USARTx USART Instance
03638   * @retval None
03639   */
03640 __STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx)
03641 {
03642   SET_BIT(USARTx->CR3, USART_CR3_RXFTIE);
03643 }
03644
03645 /**
03646   * @brief  Disable IDLE Interrupt
03647   * @rmtoll CR1          IDLEIE        LL_USART_DisableIT_IDLE
03648   * @param  USARTx USART Instance
03649   * @retval None
03650   */
03651 __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
03652 {
03653   CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
03654 }
03655
03656 /* Legacy define */
03657 #define LL_USART_DisableIT_RXNE  LL_USART_DisableIT_RXNE_RXFNE
03658
03659 /**
03660   * @brief  Disable RX Not Empty and RX FIFO Not Empty Interrupt
03661   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03662   *         FIFO mode feature is supported by the USARTx instance.
03663   * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_DisableIT_RXNE_RXFNE
03664   * @param  USARTx USART Instance
03665   * @retval None
03666   */
03667 __STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
03668 {
03669   CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
03670 }
03671
03672 /**
03673   * @brief  Disable Transmission Complete Interrupt
03674   * @rmtoll CR1          TCIE          LL_USART_DisableIT_TC
03675   * @param  USARTx USART Instance
03676   * @retval None
03677   */
03678 __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
03679 {
03680   CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
03681 }
03682
03683 /* Legacy define */
03684 #define LL_USART_DisableIT_TXE  LL_USART_DisableIT_TXE_TXFNF
03685
03686 /**
03687   * @brief  Disable TX Empty and TX FIFO Not Full Interrupt
03688   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03689   *         FIFO mode feature is supported by the USARTx instance.
03690   * @rmtoll CR1        TXEIE_TXFNFIE  LL_USART_DisableIT_TXE_TXFNF
03691   * @param  USARTx USART Instance
03692   * @retval None
03693   */
03694 __STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx)
03695 {
03696   CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
03697 }
03698
03699 /**
03700   * @brief  Disable Parity Error Interrupt
03701   * @rmtoll CR1          PEIE          LL_USART_DisableIT_PE
03702   * @param  USARTx USART Instance
03703   * @retval None
03704   */
03705 __STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
03706 {
03707   CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
03708 }
03709
03710 /**
03711   * @brief  Disable Character Match Interrupt
03712   * @rmtoll CR1          CMIE          LL_USART_DisableIT_CM
03713   * @param  USARTx USART Instance
03714   * @retval None
03715   */
03716 __STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx)
03717 {
03718   CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE);
03719 }
03720
03721 /**
03722   * @brief  Disable Receiver Timeout Interrupt
03723   * @rmtoll CR1          RTOIE         LL_USART_DisableIT_RTO
03724   * @param  USARTx USART Instance
03725   * @retval None
03726   */
03727 __STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx)
03728 {
03729   CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE);
03730 }
03731
03732 /**
03733   * @brief  Disable End Of Block Interrupt
03734   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03735   *         Smartcard feature is supported by the USARTx instance.
03736   * @rmtoll CR1          EOBIE         LL_USART_DisableIT_EOB
03737   * @param  USARTx USART Instance
03738   * @retval None
03739   */
03740 __STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx)
03741 {
03742   CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);
03743 }
03744
03745 /**
03746   * @brief  Disable TX FIFO Empty Interrupt
03747   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03748   *         FIFO mode feature is supported by the USARTx instance.
03749   * @rmtoll CR1          TXFEIE        LL_USART_DisableIT_TXFE
03750   * @param  USARTx USART Instance
03751   * @retval None
03752   */
03753 __STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx)
03754 {
03755   CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE);
03756 }
03757
03758 /**
03759   * @brief  Disable RX FIFO Full Interrupt
03760   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03761   *         FIFO mode feature is supported by the USARTx instance.
03762   * @rmtoll CR1          RXFFIE        LL_USART_DisableIT_RXFF
03763   * @param  USARTx USART Instance
03764   * @retval None
03765   */
03766 __STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx)
03767 {
03768   CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE);
03769 }
03770
03771 /**
03772   * @brief  Disable LIN Break Detection Interrupt
03773   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
03774   *         LIN feature is supported by the USARTx instance.
03775   * @rmtoll CR2          LBDIE         LL_USART_DisableIT_LBD
03776   * @param  USARTx USART Instance
03777   * @retval None
03778   */
03779 __STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
03780 {
03781   CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
03782 }
03783
03784 /**
03785   * @brief  Disable Error Interrupt
03786   * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
03787   *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
03788   *           0: Interrupt is inhibited
03789   *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
03790   * @rmtoll CR3          EIE           LL_USART_DisableIT_ERROR
03791   * @param  USARTx USART Instance
03792   * @retval None
03793   */
03794 __STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
03795 {
03796   CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
03797 }
03798
03799 /**
03800   * @brief  Disable CTS Interrupt
03801   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
03802   *         Hardware Flow control feature is supported by the USARTx instance.
03803   * @rmtoll CR3          CTSIE         LL_USART_DisableIT_CTS
03804   * @param  USARTx USART Instance
03805   * @retval None
03806   */
03807 __STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
03808 {
03809   CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
03810 }
03811
03812 /**
03813   * @brief  Disable Wake Up from Stop Mode Interrupt
03814   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
03815   *         Wake-up from Stop mode feature is supported by the USARTx instance.
03816   * @rmtoll CR3          WUFIE         LL_USART_DisableIT_WKUP
03817   * @param  USARTx USART Instance
03818   * @retval None
03819   */
03820 __STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx)
03821 {
03822   CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);
03823 }
03824
03825 /**
03826   * @brief  Disable TX FIFO Threshold Interrupt
03827   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03828   *         FIFO mode feature is supported by the USARTx instance.
03829   * @rmtoll CR3          TXFTIE        LL_USART_DisableIT_TXFT
03830   * @param  USARTx USART Instance
03831   * @retval None
03832   */
03833 __STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx)
03834 {
03835   CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE);
03836 }
03837
03838 /**
03839   * @brief  Disable Smartcard Transmission Complete Before Guard Time Interrupt
03840   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03841   *         Smartcard feature is supported by the USARTx instance.
03842   * @rmtoll CR3          TCBGTIE       LL_USART_DisableIT_TCBGT
03843   * @param  USARTx USART Instance
03844   * @retval None
03845   */
03846 __STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx)
03847 {
03848   CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
03849 }
03850
03851 /**
03852   * @brief  Disable RX FIFO Threshold Interrupt
03853   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03854   *         FIFO mode feature is supported by the USARTx instance.
03855   * @rmtoll CR3          RXFTIE        LL_USART_DisableIT_RXFT
03856   * @param  USARTx USART Instance
03857   * @retval None
03858   */
03859 __STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx)
03860 {
03861   CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE);
03862 }
03863
03864 /**
03865   * @brief  Check if the USART IDLE Interrupt  source is enabled or disabled.
03866   * @rmtoll CR1          IDLEIE        LL_USART_IsEnabledIT_IDLE
03867   * @param  USARTx USART Instance
03868   * @retval State of bit (1 or 0).
03869   */
03870 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
03871 {
03872   return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1U : 0U);
03873 }
03874
03875 /* Legacy define */
03876 #define LL_USART_IsEnabledIT_RXNE  LL_USART_IsEnabledIT_RXNE_RXFNE
03877
03878 /**
03879   * @brief  Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled.
03880   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03881   *         FIFO mode feature is supported by the USARTx instance.
03882   * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_IsEnabledIT_RXNE_RXFNE
03883   * @param  USARTx USART Instance
03884   * @retval State of bit (1 or 0).
03885   */
03886 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *USARTx)
03887 {
03888   return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1U : 0U);
03889 }
03890
03891 /**
03892   * @brief  Check if the USART Transmission Complete Interrupt is enabled or disabled.
03893   * @rmtoll CR1          TCIE          LL_USART_IsEnabledIT_TC
03894   * @param  USARTx USART Instance
03895   * @retval State of bit (1 or 0).
03896   */
03897 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
03898 {
03899   return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1U : 0U);
03900 }
03901
03902 /* Legacy define */
03903 #define LL_USART_IsEnabledIT_TXE  LL_USART_IsEnabledIT_TXE_TXFNF
03904
03905 /**
03906   * @brief  Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled
03907   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03908   *         FIFO mode feature is supported by the USARTx instance.
03909   * @rmtoll CR1         TXEIE_TXFNFIE  LL_USART_IsEnabledIT_TXE_TXFNF
03910   * @param  USARTx USART Instance
03911   * @retval State of bit (1 or 0).
03912   */
03913 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *USARTx)
03914 {
03915   return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1U : 0U);
03916 }
03917
03918 /**
03919   * @brief  Check if the USART Parity Error Interrupt is enabled or disabled.
03920   * @rmtoll CR1          PEIE          LL_USART_IsEnabledIT_PE
03921   * @param  USARTx USART Instance
03922   * @retval State of bit (1 or 0).
03923   */
03924 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
03925 {
03926   return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1U : 0U);
03927 }
03928
03929 /**
03930   * @brief  Check if the USART Character Match Interrupt is enabled or disabled.
03931   * @rmtoll CR1          CMIE          LL_USART_IsEnabledIT_CM
03932   * @param  USARTx USART Instance
03933   * @retval State of bit (1 or 0).
03934   */
03935 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx)
03936 {
03937   return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1U : 0U);
03938 }
03939
03940 /**
03941   * @brief  Check if the USART Receiver Timeout Interrupt is enabled or disabled.
03942   * @rmtoll CR1          RTOIE         LL_USART_IsEnabledIT_RTO
03943   * @param  USARTx USART Instance
03944   * @retval State of bit (1 or 0).
03945   */
03946 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx)
03947 {
03948   return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1U : 0U);
03949 }
03950
03951 /**
03952   * @brief  Check if the USART End Of Block Interrupt is enabled or disabled.
03953   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
03954   *         Smartcard feature is supported by the USARTx instance.
03955   * @rmtoll CR1          EOBIE         LL_USART_IsEnabledIT_EOB
03956   * @param  USARTx USART Instance
03957   * @retval State of bit (1 or 0).
03958   */
03959 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx)
03960 {
03961   return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1U : 0U);
03962 }
03963
03964 /**
03965   * @brief  Check if the USART TX FIFO Empty Interrupt is enabled or disabled
03966   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03967   *         FIFO mode feature is supported by the USARTx instance.
03968   * @rmtoll CR1          TXFEIE        LL_USART_IsEnabledIT_TXFE
03969   * @param  USARTx USART Instance
03970   * @retval State of bit (1 or 0).
03971   */
03972 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(USART_TypeDef *USARTx)
03973 {
03974   return ((READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1U : 0U);
03975 }
03976
03977 /**
03978   * @brief  Check if the USART RX FIFO Full Interrupt is enabled or disabled
03979   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
03980   *         FIFO mode feature is supported by the USARTx instance.
03981   * @rmtoll CR1          RXFFIE        LL_USART_IsEnabledIT_RXFF
03982   * @param  USARTx USART Instance
03983   * @retval State of bit (1 or 0).
03984   */
03985 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(USART_TypeDef *USARTx)
03986 {
03987   return ((READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1U : 0U);
03988 }
03989
03990 /**
03991   * @brief  Check if the USART LIN Break Detection Interrupt is enabled or disabled.
03992   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
03993   *         LIN feature is supported by the USARTx instance.
03994   * @rmtoll CR2          LBDIE         LL_USART_IsEnabledIT_LBD
03995   * @param  USARTx USART Instance
03996   * @retval State of bit (1 or 0).
03997   */
03998 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
03999 {
04000   return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1U : 0U);
04001 }
04002
04003 /**
04004   * @brief  Check if the USART Error Interrupt is enabled or disabled.
04005   * @rmtoll CR3          EIE           LL_USART_IsEnabledIT_ERROR
04006   * @param  USARTx USART Instance
04007   * @retval State of bit (1 or 0).
04008   */
04009 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
04010 {
04011   return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1U : 0U);
04012 }
04013
04014 /**
04015   * @brief  Check if the USART CTS Interrupt is enabled or disabled.
04016   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
04017   *         Hardware Flow control feature is supported by the USARTx instance.
04018   * @rmtoll CR3          CTSIE         LL_USART_IsEnabledIT_CTS
04019   * @param  USARTx USART Instance
04020   * @retval State of bit (1 or 0).
04021   */
04022 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
04023 {
04024   return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1U : 0U);
04025 }
04026
04027 /**
04028   * @brief  Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
04029   * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
04030   *         Wake-up from Stop mode feature is supported by the USARTx instance.
04031   * @rmtoll CR3          WUFIE         LL_USART_IsEnabledIT_WKUP
04032   * @param  USARTx USART Instance
04033   * @retval State of bit (1 or 0).
04034   */
04035 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx)
04036 {
04037   return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1U : 0U);
04038 }
04039
04040 /**
04041   * @brief  Check if USART TX FIFO Threshold Interrupt is enabled or disabled
04042   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
04043   *         FIFO mode feature is supported by the USARTx instance.
04044   * @rmtoll CR3          TXFTIE        LL_USART_IsEnabledIT_TXFT
04045   * @param  USARTx USART Instance
04046   * @retval State of bit (1 or 0).
04047   */
04048 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(USART_TypeDef *USARTx)
04049 {
04050   return ((READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1U : 0U);
04051 }
04052
04053 /**
04054   * @brief  Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.
04055   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
04056   *         Smartcard feature is supported by the USARTx instance.
04057   * @rmtoll CR3          TCBGTIE       LL_USART_IsEnabledIT_TCBGT
04058   * @param  USARTx USART Instance
04059   * @retval State of bit (1 or 0).
04060   */
04061 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx)
04062 {
04063   return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1U : 0U);
04064 }
04065
04066 /**
04067   * @brief  Check if USART RX FIFO Threshold Interrupt is enabled or disabled
04068   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
04069   *         FIFO mode feature is supported by the USARTx instance.
04070   * @rmtoll CR3          RXFTIE        LL_USART_IsEnabledIT_RXFT
04071   * @param  USARTx USART Instance
04072   * @retval State of bit (1 or 0).
04073   */
04074 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(USART_TypeDef *USARTx)
04075 {
04076   return ((READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1U : 0U);
04077 }
04078
04079 /**
04080   * @}
04081   */
04082
04083 /** @defgroup USART_LL_EF_DMA_Management DMA_Management
04084   * @{
04085   */
04086
04087 /**
04088   * @brief  Enable DMA Mode for reception
04089   * @rmtoll CR3          DMAR          LL_USART_EnableDMAReq_RX
04090   * @param  USARTx USART Instance
04091   * @retval None
04092   */
04093 __STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
04094 {
04095   SET_BIT(USARTx->CR3, USART_CR3_DMAR);
04096 }
04097
04098 /**
04099   * @brief  Disable DMA Mode for reception
04100   * @rmtoll CR3          DMAR          LL_USART_DisableDMAReq_RX
04101   * @param  USARTx USART Instance
04102   * @retval None
04103   */
04104 __STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
04105 {
04106   CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
04107 }
04108
04109 /**
04110   * @brief  Check if DMA Mode is enabled for reception
04111   * @rmtoll CR3          DMAR          LL_USART_IsEnabledDMAReq_RX
04112   * @param  USARTx USART Instance
04113   * @retval State of bit (1 or 0).
04114   */
04115 __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
04116 {
04117   return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1U : 0U);
04118 }
04119
04120 /**
04121   * @brief  Enable DMA Mode for transmission
04122   * @rmtoll CR3          DMAT          LL_USART_EnableDMAReq_TX
04123   * @param  USARTx USART Instance
04124   * @retval None
04125   */
04126 __STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
04127 {
04128   SET_BIT(USARTx->CR3, USART_CR3_DMAT);
04129 }
04130
04131 /**
04132   * @brief  Disable DMA Mode for transmission
04133   * @rmtoll CR3          DMAT          LL_USART_DisableDMAReq_TX
04134   * @param  USARTx USART Instance
04135   * @retval None
04136   */
04137 __STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
04138 {
04139   CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
04140 }
04141
04142 /**
04143   * @brief  Check if DMA Mode is enabled for transmission
04144   * @rmtoll CR3          DMAT          LL_USART_IsEnabledDMAReq_TX
04145   * @param  USARTx USART Instance
04146   * @retval State of bit (1 or 0).
04147   */
04148 __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
04149 {
04150   return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1U : 0U);
04151 }
04152
04153 /**
04154   * @brief  Enable DMA Disabling on Reception Error
04155   * @rmtoll CR3          DDRE          LL_USART_EnableDMADeactOnRxErr
04156   * @param  USARTx USART Instance
04157   * @retval None
04158   */
04159 __STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx)
04160 {
04161   SET_BIT(USARTx->CR3, USART_CR3_DDRE);
04162 }
04163
04164 /**
04165   * @brief  Disable DMA Disabling on Reception Error
04166   * @rmtoll CR3          DDRE          LL_USART_DisableDMADeactOnRxErr
04167   * @param  USARTx USART Instance
04168   * @retval None
04169   */
04170 __STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx)
04171 {
04172   CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE);
04173 }
04174
04175 /**
04176   * @brief  Indicate if DMA Disabling on Reception Error is disabled
04177   * @rmtoll CR3          DDRE          LL_USART_IsEnabledDMADeactOnRxErr
04178   * @param  USARTx USART Instance
04179   * @retval State of bit (1 or 0).
04180   */
04181 __STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx)
04182 {
04183   return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1U : 0U);
04184 }
04185
04186 /**
04187   * @brief  Get the data register address used for DMA transfer
04188   * @rmtoll RDR          RDR           LL_USART_DMA_GetRegAddr\n
04189   * @rmtoll TDR          TDR           LL_USART_DMA_GetRegAddr
04190   * @param  USARTx USART Instance
04191   * @param  Direction This parameter can be one of the following values:
04192   *         @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT
04193   *         @arg @ref LL_USART_DMA_REG_DATA_RECEIVE
04194   * @retval Address of data register
04195   */
04196 __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction)
04197 {
04198   register uint32_t data_reg_addr;
04199
04200   if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
04201   {
04202     /* return address of TDR register */
04203     data_reg_addr = (uint32_t) & (USARTx->TDR);
04204   }
04205   else
04206   {
04207     /* return address of RDR register */
04208     data_reg_addr = (uint32_t) & (USARTx->RDR);
04209   }
04210
04211   return data_reg_addr;
04212 }
04213
04214 /**
04215   * @}
04216   */
04217
04218 /** @defgroup USART_LL_EF_Data_Management Data_Management
04219   * @{
04220   */
04221
04222 /**
04223   * @brief  Read Receiver Data register (Receive Data value, 8 bits)
04224   * @rmtoll RDR          RDR           LL_USART_ReceiveData8
04225   * @param  USARTx USART Instance
04226   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
04227   */
04228 __STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
04229 {
04230   return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU);
04231 }
04232
04233 /**
04234   * @brief  Read Receiver Data register (Receive Data value, 9 bits)
04235   * @rmtoll RDR          RDR           LL_USART_ReceiveData9
04236   * @param  USARTx USART Instance
04237   * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
04238   */
04239 __STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)
04240 {
04241   return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
04242 }
04243
04244 /**
04245   * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
04246   * @rmtoll TDR          TDR           LL_USART_TransmitData8
04247   * @param  USARTx USART Instance
04248   * @param  Value between Min_Data=0x00 and Max_Data=0xFF
04249   * @retval None
04250   */
04251 __STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
04252 {
04253   USARTx->TDR = Value;
04254 }
04255
04256 /**
04257   * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
04258   * @rmtoll TDR          TDR           LL_USART_TransmitData9
04259   * @param  USARTx USART Instance
04260   * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
04261   * @retval None
04262   */
04263 __STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
04264 {
04265   USARTx->TDR = Value & 0x1FFUL;
04266 }
04267
04268 /**
04269   * @}
04270   */
04271
04272 /** @defgroup USART_LL_EF_Execution Execution
04273   * @{
04274   */
04275
04276 /**
04277   * @brief  Request an Automatic Baud Rate measurement on next received data frame
04278   * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
04279   *         Auto Baud Rate detection feature is supported by the USARTx instance.
04280   * @rmtoll RQR          ABRRQ         LL_USART_RequestAutoBaudRate
04281   * @param  USARTx USART Instance
04282   * @retval None
04283   */
04284 __STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx)
04285 {
04286   SET_BIT(USARTx->RQR, USART_RQR_ABRRQ);
04287 }
04288
04289 /**
04290   * @brief  Request Break sending
04291   * @rmtoll RQR          SBKRQ         LL_USART_RequestBreakSending
04292   * @param  USARTx USART Instance
04293   * @retval None
04294   */
04295 __STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
04296 {
04297   SET_BIT(USARTx->RQR, USART_RQR_SBKRQ);
04298 }
04299
04300 /**
04301   * @brief  Put USART in mute mode and set the RWU flag
04302   * @rmtoll RQR          MMRQ          LL_USART_RequestEnterMuteMode
04303   * @param  USARTx USART Instance
04304   * @retval None
04305   */
04306 __STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
04307 {
04308   SET_BIT(USARTx->RQR, USART_RQR_MMRQ);
04309 }
04310
04311 /**
04312   * @brief  Request a Receive Data and FIFO flush
04313   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
04314   *         FIFO mode feature is supported by the USARTx instance.
04315   * @note   Allows to discard the received data without reading them, and avoid an overrun
04316   *         condition.
04317   * @rmtoll RQR          RXFRQ         LL_USART_RequestRxDataFlush
04318   * @param  USARTx USART Instance
04319   * @retval None
04320   */
04321 __STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx)
04322 {
04323   SET_BIT(USARTx->RQR, USART_RQR_RXFRQ);
04324 }
04325
04326 /**
04327   * @brief  Request a Transmit data and FIFO flush
04328   * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
04329   *         FIFO mode feature is supported by the USARTx instance.
04330   * @rmtoll RQR          TXFRQ         LL_USART_RequestTxDataFlush
04331   * @param  USARTx USART Instance
04332   * @retval None
04333   */
04334 __STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx)
04335 {
04336   SET_BIT(USARTx->RQR, USART_RQR_TXFRQ);
04337 }
04338
04339 /**
04340   * @}
04341   */
04342
04343 #if defined(USE_FULL_LL_DRIVER)
04344 /** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
04345   * @{
04346   */
04347 ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);
04348 ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct);
04349 void        LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
04350 ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
04351 void        LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
04352 /**
04353   * @}
04354   */
04355 #endif /* USE_FULL_LL_DRIVER */
04356
04357 /**
04358   * @}
04359   */
04360
04361 /**
04362   * @}
04363   */
04364
04365 #endif /* USART1 */
04366
04367 /**
04368   * @}
04369   */
04370
04371 #ifdef __cplusplus
04372 }
04373 #endif
04374
04375 #endif /* STM32WBxx_LL_USART_H */
04376
04377 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_utils.c Source File

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stm32wbxx_ll_utils.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_utils.c
00004   * @author  MCD Application Team
00005   * @brief   UTILS LL module driver.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019 /* Includes ------------------------------------------------------------------*/
00020 #include "stm32wbxx_ll_utils.h"
00021 #include "stm32wbxx_ll_rcc.h"
00022 #include "stm32wbxx_ll_system.h"
00023 #include "stm32wbxx_ll_pwr.h"
00024 #ifdef  USE_FULL_ASSERT
00025 #include "stm32_assert.h"
00026 #else
00027 #define assert_param(expr) ((void)0U)
00028 #endif
00029
00030 /** @addtogroup STM32WBxx_LL_Driver
00031   * @{
00032   */
00033
00034 /** @addtogroup UTILS_LL
00035   * @{
00036   */
00037
00038 /* Private types -------------------------------------------------------------*/
00039 /* Private variables ---------------------------------------------------------*/
00040 /* Private constants ---------------------------------------------------------*/
00041 /** @addtogroup UTILS_LL_Private_Constants
00042   * @{
00043   */
00044 #define UTILS_MAX_FREQUENCY_SCALE1  64000000U        /*!< Maximum frequency for system clock at power scale1, in Hz */
00045 #if defined(PWR_CR1_VOS)
00046 #define UTILS_MAX_FREQUENCY_SCALE2  16000000U        /*!< Maximum frequency for system clock at power scale2, in Hz */
00047 #endif
00048
00049 /* Defines used for PLL range */
00050 #define UTILS_PLLVCO_INPUT_MIN        2660000U       /*!< Frequency min for PLLVCO input, in Hz   */
00051 #define UTILS_PLLVCO_INPUT_MAX       16000000U       /*!< Frequency max for PLLVCO input, in Hz   */
00052 #define UTILS_PLLVCO_OUTPUT_MIN      96000000U       /*!< Frequency min for PLLVCO output, in Hz  */
00053 #define UTILS_PLLVCO_OUTPUT_MAX     344000000U       /*!< Frequency max for PLLVCO output, in Hz  */
00054
00055 /* Defines used for HCLK2 frequency check */
00056 #define UTILS_HCLK2_MAX             32000000U        /*!< HCLK2 frequency maximum at 32MHz */
00057
00058 /**
00059   * @}
00060   */
00061
00062 /* Private macros ------------------------------------------------------------*/
00063 /** @addtogroup UTILS_LL_Private_Macros
00064   * @{
00065   */
00066 #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1)   \
00067                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2)   \
00068                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_3)   \
00069                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4)   \
00070                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_5)   \
00071                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_6)   \
00072                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8)   \
00073                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_10)  \
00074                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16)  \
00075                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_32)  \
00076                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64)  \
00077                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
00078                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
00079                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
00080
00081 #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
00082                                       || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
00083                                       || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
00084                                       || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
00085                                       || ((__VALUE__) == LL_RCC_APB1_DIV_16))
00086
00087 #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
00088                                       || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
00089                                       || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
00090                                       || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
00091                                       || ((__VALUE__) == LL_RCC_APB2_DIV_16))
00092
00093 #define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_1) \
00094                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_2) \
00095                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \
00096                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \
00097                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \
00098                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \
00099                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \
00100                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_8))
00101
00102 #define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((6U <= (__VALUE__)) && ((__VALUE__) <= 127U))
00103
00104 #define IS_LL_UTILS_PLLR_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLR_DIV_2) \
00105                                         || ((__VALUE__) == LL_RCC_PLLR_DIV_3) \
00106                                         || ((__VALUE__) == LL_RCC_PLLR_DIV_4) \
00107                                         || ((__VALUE__) == LL_RCC_PLLR_DIV_5) \
00108                                         || ((__VALUE__) == LL_RCC_PLLR_DIV_6) \
00109                                         || ((__VALUE__) == LL_RCC_PLLR_DIV_7) \
00110                                         || ((__VALUE__) == LL_RCC_PLLR_DIV_8))
00111
00112 #define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__)  ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))
00113
00114 #define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))
00115
00116 #if defined(PWR_CR1_VOS)
00117 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
00118                                              ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2))
00119 #else
00120 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1)
00121 #endif
00122
00123 #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
00124                                         || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
00125
00126 #define countof(a)   (sizeof(a) / sizeof(*(a)))
00127 /**
00128   * @}
00129   */
00130 /* Private function prototypes -----------------------------------------------*/
00131 /** @defgroup UTILS_LL_Private_Functions UTILS Private functions
00132   * @{
00133   */
00134 static uint32_t    UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
00135 static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK4_Frequency);
00136 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
00137 static ErrorStatus UTILS_PLL_IsBusy(void);
00138
00139 /**
00140   * @}
00141   */
00142
00143 /* Exported functions --------------------------------------------------------*/
00144 /** @addtogroup UTILS_LL_Exported_Functions
00145   * @{
00146   */
00147
00148 /** @addtogroup UTILS_LL_EF_DELAY
00149   * @{
00150   */
00151
00152 /**
00153   * @brief  This function configures the Cortex-M SysTick source to have 1ms time base.
00154   * @note   When a RTOS is used, it is recommended to avoid changing the Systick
00155   *         configuration by calling this function, for a delay use rather osDelay RTOS service.
00156   * @param  HCLKFrequency HCLK frequency in Hz
00157   * @note   HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq (HCLK1_Frequency field)
00158   * @retval None
00159   */
00160 void LL_Init1msTick(uint32_t HCLKFrequency)
00161 {
00162   /* Use frequency provided in argument */
00163   LL_InitTick(HCLKFrequency, 1000);
00164 }
00165
00166
00167 /**
00168   * @brief  This function provides accurate delay (in milliseconds) based
00169   *         on SysTick counter flag
00170   * @note   When a RTOS is used, it is recommended to avoid using blocking delay
00171   *         and use rather osDelay service.
00172   * @note   To respect 1ms timebase, user should call @ref LL_Init1msTick function which
00173   *         will configure Systick to 1ms
00174   * @param  Delay specifies the delay time length, in milliseconds.
00175   * @retval None
00176   */
00177 void LL_mDelay(uint32_t Delay)
00178 {
00179   uint32_t mDelay = Delay;
00180   __IO uint32_t  tmp = SysTick->CTRL;  /* Clear the COUNTFLAG first */
00181   /* Add this code to indicate that local variable is not used */
00182   ((void)tmp);
00183
00184   /* Add a period to guaranty minimum wait */
00185   if (mDelay < LL_MAX_DELAY)
00186   {
00187     mDelay++;
00188   }
00189
00190   while (mDelay != 0U)
00191   {
00192     if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
00193     {
00194       mDelay--;
00195     }
00196   }
00197 }
00198
00199 /**
00200   * @}
00201   */
00202
00203 /** @addtogroup UTILS_EF_SYSTEM
00204   *  @brief    System Configuration functions
00205   *
00206   @verbatim
00207  ===============================================================================
00208            ##### System Configuration functions #####
00209  ===============================================================================
00210     [..]
00211          System, HCLK1, HCLK2, AHBS, AHBRF and APB buses clocks configuration
00212
00213          (+) The maximum frequency of the SYSCLK, HCLK1, HCLK4, PCLK1 and PCLK2
00214              is 640000000 Hz.
00215  ....... (+) The maximum frequency of the HCLK2 is 320000000 Hz.
00216
00217   @endverbatim
00218   @internal
00219              Depending on the device voltage range, the maximum frequency should be
00220              adapted accordingly:
00221              (++) HCLK4 clock frequency for STM32WB55xx device
00222              (++) +--------------------------------------------------------+
00223              (++) | Latency         |     HCLK4 clock frequency (MHz)      |
00224              (++) |                 |--------------------------------------|
00225              (++) |                 |  voltage range 1  | voltage range 2  |
00226              (++) |                 |       1.2 V       |     1.0 V        |
00227              (++) |-----------------|-------------------|------------------|
00228              (++) |0WS(1 CPU cycles)|   0 < HCLK4 <= 18 |  0 < HCLK4 <= 6  |
00229              (++) |-----------------|-------------------|------------------|
00230              (++) |1WS(2 CPU cycles)|  18 < HCLK4 <= 36 |  6 < HCLK4 <= 12 |
00231              (++) |-----------------|-------------------|------------------|
00232              (++) |2WS(3 CPU cycles)|  36 < HCLK4 <= 54 | 12 < HCLK4 <= 16|
00233              (++) |-----------------|-------------------|------------------|
00234              (++) |3WS(4 CPU cycles)|  54 < HCLK4 <= 64 |       N.A.       |
00235              (++) +--------------------------------------------------------+
00236   @endinternal
00237   * @{
00238   */
00239
00240 /**
00241   * @brief  This function sets directly SystemCoreClock CMSIS variable.
00242   * @note   Variable can be calculated also through SystemCoreClockUpdate function.
00243   * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq (HCLK1_Frequency field))
00244   * @retval None
00245   */
00246 void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
00247 {
00248   /* HCLK clock frequency */
00249   SystemCoreClock = HCLKFrequency;
00250 }
00251
00252 /**
00253   * @brief  This function configures system clock with MSI as clock source of the PLL
00254   * @note   The application needs to ensure that PLL and PLLSAI1 are disabled.
00255   * @note   The application needs to ensure that PLL configuration is valid
00256   * @note   The application needs to ensure that MSI range is valid.
00257   * @note   The application needs to ensure that BUS prescalers are valid
00258   * @note   Function is based on the following formula:
00259   *         - PLL output frequency = (((MSI frequency / PLLM) * PLLN) / PLLR)
00260   *         - PLLM: ensure that the VCO input frequency ranges from 2.66 to 16 MHz (PLLVCO_input = MSI frequency / PLLM)
00261   *         - PLLN: ensure that the VCO output frequency is between 96 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
00262   *         - PLLR: ensure that max frequency at 64000000 Hz is reached (PLLVCO_output / PLLR)
00263   * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
00264   *                             the configuration information for the PLL.
00265   * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
00266   *                             the configuration information for the BUS prescalers.
00267   * @retval An ErrorStatus enumeration value:
00268   *          - SUCCESS: Max frequency configuration done
00269   *          - ERROR: Max frequency configuration not done
00270   */
00271 ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
00272                                          LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
00273 {
00274   ErrorStatus status;
00275   uint32_t pllrfreq, hclk2freq, msi_range;
00276
00277   /* Check if one of the PLL is enabled */
00278   if (UTILS_PLL_IsBusy() == SUCCESS)
00279   {
00280     /* Get the current MSI range & check coherency */
00281     msi_range =  LL_RCC_MSI_GetRange();
00282     switch (msi_range)
00283     {
00284       case LL_RCC_MSIRANGE_0:     /* MSI = 100 KHz  */
00285       case LL_RCC_MSIRANGE_1:     /* MSI = 200 KHz  */
00286       case LL_RCC_MSIRANGE_2:     /* MSI = 400 KHz  */
00287       case LL_RCC_MSIRANGE_3:     /* MSI = 800 KHz  */
00288       case LL_RCC_MSIRANGE_4:     /* MSI = 1 MHz    */
00289       case LL_RCC_MSIRANGE_5:     /* MSI = 2 MHz    */
00290         /* PLLVCO input frequency can not in the range from 2.66 to 16 MHz*/
00291         status = ERROR;
00292         break;
00293
00294       case LL_RCC_MSIRANGE_6:     /* MSI = 4 MHz    */
00295       case LL_RCC_MSIRANGE_7:     /* MSI = 8 MHz    */
00296       case LL_RCC_MSIRANGE_8:     /* MSI = 16 MHz   */
00297       case LL_RCC_MSIRANGE_9:     /* MSI = 24 MHz   */
00298       case LL_RCC_MSIRANGE_10:    /* MSI = 32 MHz   */
00299       case LL_RCC_MSIRANGE_11:    /* MSI = 48 MHz   */
00300       default:
00301         status = SUCCESS;
00302         break;
00303     }
00304
00305     /* PLL is ready, MSI range is valid and HCLK2 frequency is coherent
00306        Main PLL configuration and activation */
00307     if (status != ERROR)
00308     {
00309       /* Calculate the new PLL output frequency & verify all PLL stages are correct (VCO input ranges,
00310          VCO output ranges & SYSCLK max) when assert activated */
00311       pllrfreq = UTILS_GetPLLOutputFrequency(__LL_RCC_CALC_MSI_FREQ(msi_range), UTILS_PLLInitStruct);
00312       hclk2freq = __LL_RCC_CALC_HCLK2_FREQ(pllrfreq, UTILS_ClkInitStruct->CPU2CLKDivider);
00313
00314       /* Check HCLK2 frequency coherency */
00315       if (hclk2freq > UTILS_HCLK2_MAX)
00316       {
00317         /* HCLK2 frequency can not be higher than 32Mhz */
00318         status = ERROR;
00319       }
00320       else
00321       {
00322
00323         /* Enable MSI if not enabled */
00324         if (LL_RCC_MSI_IsReady() != 1U)
00325         {
00326           LL_RCC_MSI_Enable();
00327           while ((LL_RCC_MSI_IsReady() != 1U))
00328           {
00329             /* Wait for MSI ready */
00330           }
00331         }
00332
00333         /* Configure PLL domain SYS */
00334         LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
00335                                     UTILS_PLLInitStruct->PLLR);
00336
00337         /* Enable PLL and switch system clock to PLL - latency check done internally */
00338         status = UTILS_EnablePLLAndSwitchSystem(pllrfreq, UTILS_ClkInitStruct);
00339       }
00340     }
00341   }
00342   else
00343   {
00344     /* Current PLL configuration cannot be modified */
00345     status = ERROR;
00346   }
00347
00348   return status;
00349 }
00350
00351 /**
00352   * @brief  This function configures system clock at maximum frequency with HSI as clock source of the PLL
00353   * @note   The application need to ensure that PLL and/or PLLSAI1 are disabled.
00354   * @note   The application needs to ensure that PLL configuration is valid
00355   * @note   The application needs to ensure that BUS prescalers are valid
00356   * @note   Function is based on the following formula:
00357   *         - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLR)
00358   *         - PLLM: ensure that the VCO input frequency ranges from 2.66 to 16 MHz (PLLVCO_input = HSI frequency / PLLM)
00359   *         - PLLN: ensure that the VCO output frequency is between 96 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
00360   *         - PLLR: ensure that max frequency at 64000000 Hz is reach (PLLVCO_output / PLLR)
00361   * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
00362   *                             the configuration information for the PLL.
00363   * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
00364   *                             the configuration information for the BUS prescalers.
00365   * @retval An ErrorStatus enumeration value:
00366   *          - SUCCESS: Max frequency configuration done
00367   *          - ERROR: Max frequency configuration not done
00368   */
00369 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
00370                                          LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
00371 {
00372   ErrorStatus status;
00373   uint32_t pllrfreq, hclk2freq;
00374
00375   /* Check if one of the PLL is enabled */
00376   if (UTILS_PLL_IsBusy() == SUCCESS)
00377   {
00378     /* Calculate the new PLL output frequency */
00379     pllrfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
00380     hclk2freq = __LL_RCC_CALC_HCLK2_FREQ(pllrfreq, UTILS_ClkInitStruct->CPU2CLKDivider);
00381
00382     /* Check HCLK2 frequency coherency */
00383     if (hclk2freq > UTILS_HCLK2_MAX)
00384     {
00385       /* HCLK2 frequency can not be higher than 32Mhz */
00386       status = ERROR;
00387     }
00388     else
00389     {
00390       /* Enable HSI if not enabled */
00391       if (LL_RCC_HSI_IsReady() != 1U)
00392       {
00393         LL_RCC_HSI_Enable();
00394         while (LL_RCC_HSI_IsReady() != 1U)
00395         {
00396           /* Wait for HSI ready */
00397         }
00398       }
00399
00400       /* Configure PLL */
00401       LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
00402                                   UTILS_PLLInitStruct->PLLR);
00403
00404       /* Enable PLL and switch system clock to PLL */
00405       status = UTILS_EnablePLLAndSwitchSystem(pllrfreq, UTILS_ClkInitStruct);
00406     }
00407   }
00408   else
00409   {
00410     /* Current PLL configuration cannot be modified */
00411     status = ERROR;
00412   }
00413
00414   return status;
00415 }
00416
00417 /**
00418   * @brief  This function configures system clock with HSE as clock source of the PLL
00419   * @note   The application need to ensure that PLL and/or PLLSAI1 are disabled.
00420   * @note   The application needs to ensure that PLL configuration is valid
00421   * @note   The application needs to ensure that BUS prescalers are valid
00422   * @note   Function is based on the following formula:
00423   *         - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLR)
00424   *         - PLLM: ensure that the VCO input frequency ranges from 2.66 to 16 MHz (PLLVCO_input = HSE frequency / PLLM)
00425   *         - PLLN: ensure that the VCO output frequency is between 96 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
00426   *         - PLLR: ensure that max frequency at 64000000 Hz is reached (PLLVCO_output / PLLR)
00427   * @param  HSEBypass This parameter can be one of the following values:
00428   *         @arg @ref LL_UTILS_HSEBYPASS_ON
00429   *         @arg @ref LL_UTILS_HSEBYPASS_OFF
00430   * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
00431   *                             the configuration information for the PLL.
00432   * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
00433   *                             the configuration information for the BUS prescalers.
00434   * @retval An ErrorStatus enumeration value:
00435   *          - SUCCESS: Max frequency configuration done
00436   *          - ERROR: Max frequency configuration not done
00437   */
00438 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
00439 {
00440   ErrorStatus status;
00441   uint32_t pllrfreq, hclk2freq;
00442
00443   /* Check the parameters */
00444   assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
00445
00446   /* Check if one of the PLL is enabled */
00447   if (UTILS_PLL_IsBusy() == SUCCESS)
00448   {
00449     /* Calculate the new PLL output frequency */
00450     pllrfreq = UTILS_GetPLLOutputFrequency(HSE_VALUE, UTILS_PLLInitStruct);
00451     hclk2freq = __LL_RCC_CALC_HCLK2_FREQ(pllrfreq, UTILS_ClkInitStruct->CPU2CLKDivider);
00452
00453     /* Check HCLK2 frequency coherency */
00454     if (hclk2freq > UTILS_HCLK2_MAX)
00455     {
00456       /* HCLK2 frequency can not be higher than 32Mhz */
00457       status = ERROR;
00458     }
00459     else
00460     {
00461
00462       /* Enable HSE if not enabled */
00463       if (LL_RCC_HSE_IsReady() != 1U)
00464       {
00465         /* Check if need to enable HSE bypass feature or not */
00466         if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
00467         {
00468           LL_RCC_HSE_EnableBypass();
00469         }
00470         else
00471         {
00472           LL_RCC_HSE_DisableBypass();
00473         }
00474
00475         /* Enable HSE */
00476         LL_RCC_HSE_Enable();
00477         while (LL_RCC_HSE_IsReady() != 1U)
00478         {
00479           /* Wait for HSE ready */
00480         }
00481       }
00482
00483       /* Configure PLL */
00484       LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
00485                                   UTILS_PLLInitStruct->PLLR);
00486
00487       /* Enable PLL and switch system clock to PLL */
00488       status = UTILS_EnablePLLAndSwitchSystem(pllrfreq, UTILS_ClkInitStruct);
00489     }
00490   }
00491   else
00492   {
00493     /* Current PLL configuration cannot be modified */
00494     status = ERROR;
00495   }
00496
00497   return status;
00498 }
00499
00500
00501 /**
00502   * @}
00503   */
00504
00505
00506 /**
00507   * @}
00508   */
00509
00510 /** @addtogroup UTILS_LL_Private_Functions
00511   * @{
00512   */
00513 /**
00514   * @brief  Update number of Flash wait states in line with new frequency and current
00515             voltage range.
00516   * @param  HCLK4_Frequency  HCLK4 frequency
00517   * @retval An ErrorStatus enumeration value:
00518   *          - SUCCESS: Latency has been modified
00519   *          - ERROR: Latency cannot be modified
00520   */
00521 static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK4_Frequency)
00522 {
00523   ErrorStatus status = SUCCESS;
00524   uint32_t latency   = LL_FLASH_LATENCY_0;  /* default value 0WS */
00525   uint16_t index;
00526
00527   /* Array used for FLASH latency according to HCLK4 Frequency */
00528   /* Flash Clock source (HCLK4) range in MHz with a VCORE is range1 */
00529   const uint32_t UTILS_CLK_SRC_RANGE_VOS1[] = {18000000U, 36000000U, 54000000U, UTILS_MAX_FREQUENCY_SCALE1};
00530
00531 #if defined(PWR_CR1_VOS)
00532   /* Flash Clock source (HCLK4) range in MHz with a VCORE is range2 */
00533   const uint32_t UTILS_CLK_SRC_RANGE_VOS2[] = {6000000U, 12000000U, UTILS_MAX_FREQUENCY_SCALE2};
00534 #endif
00535
00536   /* Flash Latency range */
00537   const uint32_t UTILS_LATENCY_RANGE[] = {LL_FLASH_LATENCY_0, LL_FLASH_LATENCY_1, LL_FLASH_LATENCY_2, LL_FLASH_LATENCY_3};
00538
00539   /* Frequency cannot be equal to 0 */
00540   if (HCLK4_Frequency == 0U)
00541   {
00542     status = ERROR;
00543   }
00544   else
00545   {
00546 #if defined(PWR_CR1_VOS)
00547     if (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
00548     {
00549       for (index = 0; index < countof(UTILS_CLK_SRC_RANGE_VOS1); index++)
00550       {
00551         if (HCLK4_Frequency <= UTILS_CLK_SRC_RANGE_VOS1[index])
00552         {
00553           latency = UTILS_LATENCY_RANGE[index];
00554           break;
00555         }
00556       }
00557     }
00558     else /* SCALE2 */
00559     {
00560       for (index = 0; index < countof(UTILS_CLK_SRC_RANGE_VOS2); index++)
00561       {
00562         if (HCLK4_Frequency <= UTILS_CLK_SRC_RANGE_VOS2[index])
00563         {
00564           latency = UTILS_LATENCY_RANGE[index];
00565           break;
00566         }
00567       }
00568     }
00569 #else
00570     for (index = 0; index < countof(UTILS_CLK_SRC_RANGE_VOS1); index++)
00571     {
00572       if (HCLK4_Frequency <= UTILS_CLK_SRC_RANGE_VOS1[index])
00573       {
00574         latency = UTILS_LATENCY_RANGE[index];
00575         break;
00576       }
00577     }
00578 #endif
00579
00580     LL_FLASH_SetLatency(latency);
00581
00582     /* Check that the new number of wait states is taken into account to access the Flash
00583        memory by reading the FLASH_ACR register */
00584     while (LL_FLASH_GetLatency() != latency)
00585     {
00586     }
00587   }
00588   return status;
00589 }
00590
00591 /**
00592   * @brief  Function to check that PLL can be modified
00593   * @param  PLL_InputFrequency  PLL input frequency (in Hz)
00594   * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
00595   *                             the configuration information for the PLL.
00596   * @retval PLL output frequency (in Hz)
00597   */
00598 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
00599 {
00600   uint32_t pllfreq;
00601
00602   /* Check the parameters */
00603   assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
00604   assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
00605   assert_param(IS_LL_UTILS_PLLR_VALUE(UTILS_PLLInitStruct->PLLR));
00606
00607   /* Check different PLL parameters according to RM                          */
00608   /*  - PLLM: ensure that the VCO input frequency ranges from 2.66 to 16 MHz.   */
00609   pllfreq = PLL_InputFrequency / (((UTILS_PLLInitStruct->PLLM >> RCC_PLLCFGR_PLLM_Pos) + 1U));
00610   assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq));
00611
00612   /*  - PLLN: ensure that the VCO output frequency is between 96 and 344 MHz.*/
00613   pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos));
00614   assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));
00615
00616   /*  - PLLR: ensure that max frequency at 64000000 Hz is reached                   */
00617   pllfreq = pllfreq / ((UTILS_PLLInitStruct->PLLR >> RCC_PLLCFGR_PLLR_Pos) + 1U);
00618   assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
00619
00620   return pllfreq;
00621 }
00622
00623 /**
00624   * @brief  Function to check that PLL can be modified
00625   * @retval An ErrorStatus enumeration value:
00626   *          - SUCCESS: PLL modification can be done
00627   *          - ERROR: PLL is busy
00628   */
00629 static ErrorStatus UTILS_PLL_IsBusy(void)
00630 {
00631   ErrorStatus status = SUCCESS;
00632
00633   /* Check if PLL is busy*/
00634   if (LL_RCC_PLL_IsReady() != 0U)
00635   {
00636     /* PLL configuration cannot be modified */
00637     status = ERROR;
00638   }
00639 #if defined(SAI1)
00640   /* Check if PLLSAI1 is busy*/
00641   if (LL_RCC_PLLSAI1_IsReady() != 0U)
00642   {
00643     /* PLLSAI1 configuration cannot be modified */
00644     status = ERROR;
00645   }
00646 #endif
00647
00648   return status;
00649 }
00650
00651 /**
00652   * @brief  Function to enable PLL and switch system clock to PLL
00653   * @param  SYSCLK_Frequency SYSCLK frequency
00654   * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
00655   *                             the configuration information for the BUS prescalers.
00656   * @retval An ErrorStatus enumeration value:
00657   *          - SUCCESS: No problem to switch system to PLL
00658   *          - ERROR: Problem to switch system to PLL
00659   */
00660 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
00661 {
00662   ErrorStatus status = SUCCESS;
00663   uint32_t hclks_frequency_target, hclks_frequency_current, sysclk_current;
00664
00665   assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->CPU1CLKDivider));
00666   assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->CPU2CLKDivider));
00667   assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHB4CLKDivider));
00668   assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
00669   assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
00670
00671   /* Calculate HCLK4 frequency based on SYSCLK_Frequency target */
00672   hclks_frequency_target = __LL_RCC_CALC_HCLK4_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHB4CLKDivider);
00673
00674   /* Calculate HCLK4 frequency current */
00675   sysclk_current = (SystemCoreClock * AHBPrescTable[(LL_RCC_GetAHBPrescaler() & RCC_CFGR_HPRE) >>  RCC_CFGR_HPRE_Pos]);
00676   hclks_frequency_current = __LL_RCC_CALC_HCLK4_FREQ(sysclk_current, LL_RCC_GetAHB4Prescaler());
00677
00678   /* Increasing the number of wait states because of higher CPU frequency */
00679   if (hclks_frequency_current < hclks_frequency_target)
00680   {
00681     /* Set FLASH latency to highest latency */
00682     status = UTILS_SetFlashLatency(hclks_frequency_target);
00683   }
00684
00685   /* Update system clock configuration */
00686   if (status == SUCCESS)
00687   {
00688     /* Enable PLL */
00689     LL_RCC_PLL_Enable();
00690     LL_RCC_PLL_EnableDomain_SYS();
00691     while (LL_RCC_PLL_IsReady() != 1U)
00692     {
00693       /* Wait for PLL ready */
00694     }
00695
00696     /* Sysclk activation on the main PLL */
00697     LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->CPU1CLKDivider);
00698     LL_C2_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->CPU2CLKDivider);
00699     LL_RCC_SetAHB4Prescaler(UTILS_ClkInitStruct->AHB4CLKDivider);
00700     LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
00701     while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
00702     {
00703       /* Wait for system clock switch to PLL */
00704     }
00705
00706     /* Set APB1 & APB2 prescaler*/
00707     LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
00708     LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
00709   }
00710
00711   /* Decreasing the number of wait states because of lower CPU frequency */
00712   if (hclks_frequency_current > hclks_frequency_target)
00713   {
00714     /* Set FLASH latency to lowest latency */
00715     status = UTILS_SetFlashLatency(hclks_frequency_target);
00716   }
00717
00718   /* Update SystemCoreClock variable */
00719   if (status == SUCCESS)
00720   {
00721     LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK1_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->CPU1CLKDivider));
00722   }
00723
00724   return status;
00725 }
00726
00727 /**
00728   * @}
00729   */
00730
00731
00732
00733 /**
00734   * @}
00735   */
00736
00737 /**
00738   * @}
00739   */
00740
00741 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_utils.h Source File

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stm32wbxx_ll_utils.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_utils.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of UTILS LL module.
00006   @verbatim
00007   ==============================================================================
00008                      ##### How to use this driver #####
00009   ==============================================================================
00010     [..]
00011     The LL UTILS driver contains a set of generic APIs that can be
00012     used by user:
00013       (+) Device electronic signature
00014       (+) Timing functions
00015       (+) PLL configuration functions
00016
00017   @endverbatim
00018   ******************************************************************************
00019   * @attention
00020   *
00021   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00022   * All rights reserved.</center></h2>
00023   *
00024   * This software component is licensed by ST under BSD 3-Clause license,
00025   * the "License"; You may not use this file except in compliance with the
00026   * License. You may obtain a copy of the License at:
00027   *                        opensource.org/licenses/BSD-3-Clause
00028   *
00029   ******************************************************************************
00030   */
00031
00032 /* Define to prevent recursive inclusion -------------------------------------*/
00033 #ifndef STM32WBxx_LL_UTILS_H
00034 #define STM32WBxx_LL_UTILS_H
00035
00036 #ifdef __cplusplus
00037 extern "C" {
00038 #endif
00039
00040 /* Includes ------------------------------------------------------------------*/
00041 #include "stm32wbxx.h"
00042
00043 /** @addtogroup STM32WBxx_LL_Driver
00044   * @{
00045   */
00046
00047 /** @defgroup UTILS_LL UTILS
00048   * @{
00049   */
00050
00051 /* Private types -------------------------------------------------------------*/
00052 /* Private variables ---------------------------------------------------------*/
00053
00054 /* Private constants ---------------------------------------------------------*/
00055 /** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
00056   * @{
00057   */
00058
00059 /* Max delay can be used in LL_mDelay */
00060 #define LL_MAX_DELAY                  0xFFFFFFFFU
00061
00062 /**
00063  * @brief Unique device ID register base address
00064  */
00065 #define UID_BASE_ADDRESS              UID_BASE
00066
00067 /**
00068  * @brief Flash size data register base address
00069  */
00070 #define FLASHSIZE_BASE_ADDRESS        FLASHSIZE_BASE
00071
00072 /**
00073  * @brief Package data register base address
00074  */
00075 #define PACKAGE_BASE_ADDRESS          PACKAGE_BASE
00076
00077 /**
00078   * @}
00079   */
00080
00081 /* Private macros ------------------------------------------------------------*/
00082 /** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
00083   * @{
00084   */
00085 /**
00086   * @}
00087   */
00088 /* Exported types ------------------------------------------------------------*/
00089 /** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
00090   * @{
00091   */
00092 /**
00093   * @brief  UTILS PLL structure definition
00094   */
00095 typedef struct
00096 {
00097   uint32_t PLLM;   /*!< Division factor for PLL VCO input clock.
00098                         This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV
00099
00100                         This feature can be modified afterwards using unitary function
00101                         @ref LL_RCC_PLL_ConfigDomain_SYS(). */
00102
00103   uint32_t PLLN;   /*!< Multiplication factor for PLL VCO output clock.
00104                         This parameter must be a number between Min_Data = 6 and Max_Data = 127
00105
00106                         This feature can be modified afterwards using unitary function
00107                         @ref LL_RCC_PLL_ConfigDomain_SYS(). */
00108
00109   uint32_t PLLR;   /*!< Division for the main system clock.
00110                         This parameter can be a value of @ref RCC_LL_EC_PLLR_DIV
00111
00112                         This feature can be modified afterwards using unitary function
00113                         @ref LL_RCC_PLL_ConfigDomain_SYS(). */
00114 } LL_UTILS_PLLInitTypeDef;
00115
00116 /**
00117   * @brief  UTILS System, AHB and APB buses clock configuration structure definition
00118   */
00119 typedef struct
00120 {
00121   uint32_t CPU1CLKDivider;         /*!< The CPU1 clock (HCLK1) divider. This clock is derived from the system clock (SYSCLK).
00122                                         This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
00123
00124                                         This feature can be modified afterwards using unitary function
00125                                         @ref LL_RCC_SetAHBPrescaler(). */
00126
00127   uint32_t CPU2CLKDivider;         /*!< The CPU2 clock (HCLK2) divider. This clock is derived from the system clock (SYSCLK).
00128                                         This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
00129
00130                                         This feature can be modified afterwards using unitary function
00131                                         @ref LL_C2_RCC_SetAHBPrescaler(). */
00132
00133   uint32_t AHB4CLKDivider;         /*!< The AHBS clock (HCLK4) divider. This clock is derived from the system clock (SYSCLK).
00134                                         This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
00135
00136                                         This feature can be modified afterwards using unitary function
00137                                         @ref LL_RCC_SetAHB4Prescaler(). */
00138
00139   uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK1).
00140                                        This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
00141
00142                                        This feature can be modified afterwards using unitary function
00143                                        @ref LL_RCC_SetAPB1Prescaler(). */
00144
00145   uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK1).
00146                                        This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
00147
00148                                        This feature can be modified afterwards using unitary function
00149                                        @ref LL_RCC_SetAPB2Prescaler(). */
00150
00151 } LL_UTILS_ClkInitTypeDef;
00152
00153 /**
00154   * @}
00155   */
00156
00157 /* Exported constants --------------------------------------------------------*/
00158 /** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
00159   * @{
00160   */
00161
00162 /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
00163   * @{
00164   */
00165 #define LL_UTILS_HSEBYPASS_OFF        0x00000000U       /*!< HSE Bypass is not enabled                */
00166 #define LL_UTILS_HSEBYPASS_ON         0x00000001U       /*!< HSE Bypass is enabled                    */
00167 /**
00168   * @}
00169   */
00170
00171 /** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
00172   * @{
00173   */
00174 #define LL_UTILS_PACKAGETYPE_CSP100         0x00000011U /*!< CSP100 package type                      */
00175 #define LL_UTILS_PACKAGETYPE_CSP100_C       0x00000012U /*!< CSP100 package type w/ capfree LDO       */
00176 #define LL_UTILS_PACKAGETYPE_QFN68          0x00000013U /*!< QFN68 package type                       */
00177 #define LL_UTILS_PACKAGETYPE_QFN68_C        0x00000014U /*!< QFN68 package type w/ capfree LDO        */
00178 #define LL_UTILS_PACKAGETYPE_QFN48          0x0000000AU /*!< QFN48 package type                       */
00179 #define LL_UTILS_PACKAGETYPE_QFN48_C        0x00000015U /*!< QFN48 package type w/ capfree LDO        */
00180 /**
00181   * @}
00182   */
00183
00184 /**
00185   * @}
00186   */
00187
00188 /* Exported macro ------------------------------------------------------------*/
00189
00190 /* Exported functions --------------------------------------------------------*/
00191 /** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
00192   * @{
00193   */
00194
00195 /** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
00196   * @{
00197   */
00198 /**
00199   * @brief  Get Word0 of the unique device identifier (UID based on 96 bits)
00200   * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format
00201   */
00202 __STATIC_INLINE uint32_t LL_GetUID_Word0(void)
00203 {
00204   return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
00205 }
00206
00207 /**
00208   * @brief  Get Word1 of the unique device identifier (UID based on 96 bits)
00209   * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])
00210   */
00211 __STATIC_INLINE uint32_t LL_GetUID_Word1(void)
00212 {
00213   return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
00214 }
00215
00216 /**
00217   * @brief  Get Word2 of the unique device identifier (UID based on 96 bits)
00218   * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24]
00219   */
00220 __STATIC_INLINE uint32_t LL_GetUID_Word2(void)
00221 {
00222   return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
00223 }
00224
00225 /**
00226   * @brief  Get Flash memory size
00227   * @note   This bitfield indicates the size of the device Flash memory expressed in
00228   *         Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
00229   * @retval FLASH_SIZE[15:0]: Flash memory size
00230   */
00231 __STATIC_INLINE uint32_t LL_GetFlashSize(void)
00232 {
00233   return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0x0000FFFFUL);
00234 }
00235
00236 /**
00237   * @brief  Get Package type
00238   * @retval Returned value can be one of the following values:
00239   *         @arg @ref LL_UTILS_PACKAGETYPE_CSP100
00240   *         @arg @ref LL_UTILS_PACKAGETYPE_CSP100_C
00241   *         @arg @ref LL_UTILS_PACKAGETYPE_QFN68
00242   *         @arg @ref LL_UTILS_PACKAGETYPE_QFN68_C
00243   *         @arg @ref LL_UTILS_PACKAGETYPE_QFN48
00244   *         @arg @ref LL_UTILS_PACKAGETYPE_QFN48_C
00245   *
00246   */
00247 __STATIC_INLINE uint32_t LL_GetPackageType(void)
00248 {
00249   return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU);
00250 }
00251
00252 /**
00253   * @}
00254   */
00255
00256 /** @defgroup UTILS_LL_EF_DELAY DELAY
00257   * @{
00258   */
00259 /**
00260   * @brief  This function configures the Cortex-M SysTick source of the time base.
00261   * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq (HCLK1_Frequency field))
00262   * @note   When a RTOS is used, it is recommended to avoid changing the SysTick
00263   *         configuration by calling this function, for a delay use rather osDelay RTOS service.
00264   * @param  Ticks Number of ticks
00265   * @retval None
00266   */
00267 __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
00268 {
00269   /* Configure the SysTick to have interrupt in 1ms time base */
00270   SysTick->LOAD  = (uint32_t)((HCLKFrequency / Ticks) - 1UL);  /* set reload register */
00271   SysTick->VAL   = 0UL;                                       /* Load the SysTick Counter Value */
00272   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
00273                    SysTick_CTRL_ENABLE_Msk;                   /* Enable the Systick Timer */
00274 }
00275
00276 void        LL_Init1msTick(uint32_t HCLKFrequency);
00277
00278 void        LL_mDelay(uint32_t Delay);
00279
00280 /**
00281   * @}
00282   */
00283
00284 /** @defgroup UTILS_EF_SYSTEM SYSTEM
00285   * @{
00286   */
00287
00288 void        LL_SetSystemCoreClock(uint32_t HCLKFrequency);
00289 ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
00290                                          LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
00291 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
00292                                          LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
00293 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEBypass,
00294                                          LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
00295
00296 /**
00297   * @}
00298   */
00299
00300 /**
00301   * @}
00302   */
00303
00304 /**
00305   * @}
00306   */
00307
00308 /**
00309   * @}
00310   */
00311
00312 #ifdef __cplusplus
00313 }
00314 #endif
00315
00316 #endif /* STM32WBxx_LL_UTILS_H */
00317
00318 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Fri Sep 6 2019 11:34:37 for STM32WB55xx HAL User Manual by doxygen 1.7.6.1


STM32WB55xx HAL User Manual: stm32wbxx_ll_wwdg.h Source File

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stm32wbxx_ll_wwdg.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32wbxx_ll_wwdg.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of WWDG LL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
00010   * All rights reserved.</center></h2>
00011   *
00012   * This software component is licensed by ST under BSD 3-Clause license,
00013   * the "License"; You may not use this file except in compliance with the
00014   * License. You may obtain a copy of the License at:
00015   *                        opensource.org/licenses/BSD-3-Clause
00016   *
00017   ******************************************************************************
00018   */
00019
00020 /* Define to prevent recursive inclusion -------------------------------------*/
00021 #ifndef STM32WBxx_LL_WWDG_H
00022 #define STM32WBxx_LL_WWDG_H
00023
00024 #ifdef __cplusplus
00025 extern "C" {
00026 #endif
00027
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm32wbxx.h"
00030
00031 /** @addtogroup STM32WBxx_LL_Driver
00032   * @{
00033   */
00034
00035 #if defined (WWDG)
00036
00037 /** @defgroup WWDG_LL WWDG
00038   * @{
00039   */
00040
00041 /* Private types -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 /* Private constants ---------------------------------------------------------*/
00044 /* Private macros ------------------------------------------------------------*/
00045 /* Exported types ------------------------------------------------------------*/
00046 /* Exported constants --------------------------------------------------------*/
00047 /** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
00048   * @{
00049   */
00050
00051 /** @defgroup WWDG_LL_EC_IT IT Defines
00052   * @brief    IT defines which can be used with LL_WWDG_ReadReg and  LL_WWDG_WriteReg functions
00053   * @{
00054   */
00055 #define LL_WWDG_CFR_EWI                     WWDG_CFR_EWI
00056 /**
00057   * @}
00058   */
00059
00060 /** @defgroup WWDG_LL_EC_PRESCALER  PRESCALER
00061   * @{
00062   */
00063 #define LL_WWDG_PRESCALER_1                 0x00000000u                                               /*!< WWDG counter clock = (PCLK1/4096)/1 */
00064 #define LL_WWDG_PRESCALER_2                 WWDG_CFR_WDGTB_0                                          /*!< WWDG counter clock = (PCLK1/4096)/2 */
00065 #define LL_WWDG_PRESCALER_4                 WWDG_CFR_WDGTB_1                                          /*!< WWDG counter clock = (PCLK1/4096)/4 */
00066 #define LL_WWDG_PRESCALER_8                 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1)                     /*!< WWDG counter clock = (PCLK1/4096)/8 */
00067 #define LL_WWDG_PRESCALER_16                WWDG_CFR_WDGTB_2                                          /*!< WWDG counter clock = (PCLK1/4096)/16 */
00068 #define LL_WWDG_PRESCALER_32                (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0)                     /*!< WWDG counter clock = (PCLK1/4096)/32 */
00069 #define LL_WWDG_PRESCALER_64                (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1)                     /*!< WWDG counter clock = (PCLK1/4096)/64 */
00070 #define LL_WWDG_PRESCALER_128               (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)  /*!< WWDG counter clock = (PCLK1/4096)/128 */
00071 /**
00072   * @}
00073   */
00074
00075 /**
00076   * @}
00077   */
00078
00079 /* Exported macro ------------------------------------------------------------*/
00080 /** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
00081   * @{
00082   */
00083 /** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
00084   * @{
00085   */
00086 /**
00087   * @brief  Write a value in WWDG register
00088   * @param  __INSTANCE__ WWDG Instance
00089   * @param  __REG__ Register to be written
00090   * @param  __VALUE__ Value to be written in the register
00091   * @retval None
00092   */
00093 #define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00094
00095 /**
00096   * @brief  Read a value in WWDG register
00097   * @param  __INSTANCE__ WWDG Instance
00098   * @param  __REG__ Register to be read
00099   * @retval Register value
00100   */
00101 #define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00102 /**
00103   * @}
00104   */
00105
00106 /**
00107   * @}
00108   */
00109
00110 /* Exported functions --------------------------------------------------------*/
00111 /** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
00112   * @{
00113   */
00114
00115 /** @defgroup WWDG_LL_EF_Configuration Configuration
00116   * @{
00117   */
00118 /**
00119   * @brief  Enable Window Watchdog. The watchdog is always disabled after a reset.
00120   * @note   It is enabled by setting the WDGA bit in the WWDG_CR register,
00121   *         then it cannot be disabled again except by a reset.
00122   *         This bit is set by software and only cleared by hardware after a reset.
00123   *         When WDGA = 1, the watchdog can generate a reset.
00124   * @rmtoll CR           WDGA          LL_WWDG_Enable
00125   * @param  WWDGx WWDG Instance
00126   * @retval None
00127   */
00128 __STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
00129 {
00130   SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
00131 }
00132
00133 /**
00134   * @brief  Checks if Window Watchdog is enabled
00135   * @rmtoll CR           WDGA          LL_WWDG_IsEnabled
00136   * @param  WWDGx WWDG Instance
00137   * @retval State of bit (1 or 0).
00138   */
00139 __STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
00140 {
00141   return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL);
00142 }
00143
00144 /**
00145   * @brief  Set the Watchdog counter value to provided value (7-bits T[6:0])
00146   * @note   When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
00147   *         This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
00148   *         A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
00149   *         Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
00150   * @rmtoll CR           T             LL_WWDG_SetCounter
00151   * @param  WWDGx WWDG Instance
00152   * @param  Counter 0..0x7F (7 bit counter value)
00153   * @retval None
00154   */
00155 __STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
00156 {
00157   MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
00158 }
00159
00160 /**
00161   * @brief  Return current Watchdog Counter Value (7 bits counter value)
00162   * @rmtoll CR           T             LL_WWDG_GetCounter
00163   * @param  WWDGx WWDG Instance
00164   * @retval 7 bit Watchdog Counter value
00165   */
00166 __STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
00167 {
00168   return (READ_BIT(WWDGx->CR, WWDG_CR_T));
00169 }
00170
00171 /**
00172   * @brief  Set the time base of the prescaler (WDGTB).
00173   * @note   Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
00174   *         is decremented every (4096 x 2expWDGTB) PCLK cycles
00175   * @rmtoll CFR          WDGTB         LL_WWDG_SetPrescaler
00176   * @param  WWDGx WWDG Instance
00177   * @param  Prescaler This parameter can be one of the following values:
00178   *         @arg @ref LL_WWDG_PRESCALER_1
00179   *         @arg @ref LL_WWDG_PRESCALER_2
00180   *         @arg @ref LL_WWDG_PRESCALER_4
00181   *         @arg @ref LL_WWDG_PRESCALER_8
00182   *         @arg @ref LL_WWDG_PRESCALER_16
00183   *         @arg @ref LL_WWDG_PRESCALER_32
00184   *         @arg @ref LL_WWDG_PRESCALER_64
00185   *         @arg @ref LL_WWDG_PRESCALER_128
00186   * @retval None
00187   */
00188 __STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
00189 {
00190   MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
00191 }
00192
00193 /**
00194   * @brief  Return current Watchdog Prescaler Value
00195   * @rmtoll CFR          WDGTB         LL_WWDG_GetPrescaler
00196   * @param  WWDGx WWDG Instance
00197   * @retval Returned value can be one of the following values:
00198   *         @arg @ref LL_WWDG_PRESCALER_1
00199   *         @arg @ref LL_WWDG_PRESCALER_2
00200   *         @arg @ref LL_WWDG_PRESCALER_4
00201   *         @arg @ref LL_WWDG_PRESCALER_8
00202   *         @arg @ref LL_WWDG_PRESCALER_16
00203   *         @arg @ref LL_WWDG_PRESCALER_32
00204   *         @arg @ref LL_WWDG_PRESCALER_64
00205   *         @arg @ref LL_WWDG_PRESCALER_128
00206   */
00207 __STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
00208 {
00209   return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
00210 }
00211
00212 /**
00213   * @brief  Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
00214   * @note   This window value defines when write in the WWDG_CR register
00215   *         to program Watchdog counter is allowed.
00216   *         Watchdog counter value update must occur only when the counter value
00217   *         is lower than the Watchdog window register value.
00218   *         Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
00219   *         (in the control register) is refreshed before the downcounter has reached
00220   *         the watchdog window register value.
00221   *         Physically is possible to set the Window lower then 0x40 but it is not recommended.
00222   *         To generate an immediate reset, it is possible to set the Counter lower than 0x40.
00223   * @rmtoll CFR          W             LL_WWDG_SetWindow
00224   * @param  WWDGx WWDG Instance
00225   * @param  Window 0x00..0x7F (7 bit Window value)
00226   * @retval None
00227   */
00228 __STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
00229 {
00230   MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
00231 }
00232
00233 /**
00234   * @brief  Return current Watchdog Window Value (7 bits value)
00235   * @rmtoll CFR          W             LL_WWDG_GetWindow
00236   * @param  WWDGx WWDG Instance
00237   * @retval 7 bit Watchdog Window value
00238   */
00239 __STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
00240 {
00241   return (READ_BIT(WWDGx->CFR, WWDG_CFR_W));
00242 }
00243
00244 /**
00245   * @}
00246   */
00247
00248 /** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
00249   * @{
00250   */
00251 /**
00252   * @brief  Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
00253   * @note   This bit is set by hardware when the counter has reached the value 0x40.
00254   *         It must be cleared by software by writing 0.
00255   *         A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
00256   * @rmtoll SR           EWIF          LL_WWDG_IsActiveFlag_EWKUP
00257   * @param  WWDGx WWDG Instance
00258   * @retval State of bit (1 or 0).
00259   */
00260 __STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
00261 {
00262   return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL);
00263 }
00264
00265 /**
00266   * @brief  Clear WWDG Early Wakeup Interrupt Flag (EWIF)
00267   * @rmtoll SR           EWIF          LL_WWDG_ClearFlag_EWKUP
00268   * @param  WWDGx WWDG Instance
00269   * @retval None
00270   */
00271 __STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
00272 {
00273   WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
00274 }
00275
00276 /**
00277   * @}
00278   */
00279
00280 /** @defgroup WWDG_LL_EF_IT_Management IT_Management
00281   * @{
00282   */
00283 /**
00284   * @brief  Enable the Early Wakeup Interrupt.
00285   * @note   When set, an interrupt occurs whenever the counter reaches value 0x40.
00286   *         This interrupt is only cleared by hardware after a reset
00287   * @rmtoll CFR          EWI           LL_WWDG_EnableIT_EWKUP
00288   * @param  WWDGx WWDG Instance
00289   * @retval None
00290   */
00291 __STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
00292 {
00293   SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
00294 }
00295
00296 /**
00297   * @brief  Check if Early Wakeup Interrupt is enabled
00298   * @rmtoll CFR          EWI           LL_WWDG_IsEnabledIT_EWKUP
00299   * @param  WWDGx WWDG Instance
00300   * @retval State of bit (1 or 0).
00301   */
00302 __STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
00303 {
00304   return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL);
00305 }
00306
00307 /**
00308   * @}
00309   */
00310
00311 /**
00312   * @}
00313   */
00314
00315 /**
00316   * @}
00317   */
00318
00319 #endif /* WWDG */
00320
00321 /**
00322   * @}
00323   */
00324
00325 #ifdef __cplusplus
00326 }
00327 #endif
00328
00329 #endif /* STM32WBxx_LL_WWDG_H */
00330
00331 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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